diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 776000623ce..b5e0634eade 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -423,7 +423,9 @@ "hpmicro/hpm5300evk", "hpmicro/hpm5301evklite", "hpmicro/hpm6800evk", - "hpmicro/hpm6e00evk" + "hpmicro/hpm6e00evk", + "hpmicro/hpm6p00evk", + "hpmicro/hpm5e00evk" ] }, { diff --git a/bsp/hpmicro/.ignore_format.yml b/bsp/hpmicro/.ignore_format.yml index 65bf18b330a..f0f65ef717f 100644 --- a/bsp/hpmicro/.ignore_format.yml +++ b/bsp/hpmicro/.ignore_format.yml @@ -4,11 +4,24 @@ dir_path: - hpm6200evk/startup + - hpm6200evk/board - hpm6300evk/startup + - hpm6300evk/board - hpm6750evk/startup + - hpm6750evk/board - hpm6750evk2/startup + - hpm6750evk2/board - hpm6750evkmini/startup + - hpm6750evkmini/board - hpm5300evk/startup + - hpm5300evk/board - hpm5301evklite/startup + - hpm5301evklite/board - hpm6800evk/startup - - libraries/hpm_sdk + - hpm6800evk/board + - hpm6e00evk/startup + - hpm6e00evk/board + - hpm6p00evk/startup + - hpm6p00evk/board + - hpm5e00evk/startup + - hpm5e00evk/board diff --git a/bsp/hpmicro/README.md b/bsp/hpmicro/README.md new file mode 100644 index 00000000000..5d21c2380e7 --- /dev/null +++ b/bsp/hpmicro/README.md @@ -0,0 +1,193 @@ +# HPMicro Board Support Package (BSP) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides an overview of the HPMicro BSPs (Board Support Package) available in the RT-Thread repository. Each BSP is tailored for specific HPMicro development boards, offering necessary drivers and configurations to run RT-Thread seamlessly on RISC-V based HPMicro microcontrollers. + +The document consists of the following parts: + +- HPMicro BSP Overview +- Available BSPs +- Quick Start Guide +- Common Development Environment Setup +- References + +By reading the Quick Start Guide section, developers can quickly get their hands on any HPMicro BSP and run RT-Thread on the board. Each individual BSP contains detailed documentation for specific board features and advanced usage. + +## Available BSPs + +Below is a comprehensive list of HPMicro BSPs currently supported: + +| BSP Name | Supported Board | MCU | Description | +|----------|-----------------|-----|-------------| +| hpm5300evk | HPM5300EVK | HPM5361 | Development board for HPM5300 series | +| hpm5301evklite | HPM5301EVKLITE | HPM5301 | Lite version development board for HPM5301 | +| hpm5e00evk | HPM5E00EVK | HPM5E31 | Development board for HPM5E00 series | +| hpm6200evk | HPM6200EVK | HPM6200 | Development board for HPM6200 series | +| hpm6300evk | HPM6300EVK | HPM6360 | Development board for HPM6300 series with Ethernet support | +| hpm6750evk | HPM6750EVK | HPM6750 | Development board for HPM6750 series with dual-core RISC-V | +| hpm6750evk2 | HPM6750EVK2 | HPM6750 | Second generation development board for HPM6750 series | +| hpm6750evkmini | HPM6750EVKMINI | HPM6750 | Mini development board for HPM6750 series | +| hpm6800evk | HPM6800EVK | HPM6800 | Development board for HPM6800 series | +| hpm6e00evk | HPM6E00EVK | HPM6E00 | Development board for HPM6E00 series | +| hpm6p00evk | HPM6P00EVK | HPM6P00 | Development board for HPM6P00 series | + +## Quick Start Guide + +### Prerequisites + +Before getting started with any HPMicro BSP, you need to prepare the following development environment: + +#### 1. RT-Thread ENV +- Download and install [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) + +#### 2. RISC-V Toolchain +- Download the RISC-V toolchain: [riscv32-gnu-toolchain](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) +- Extract it to a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` + +#### 3. OpenOCD for HPMicro +- Download OpenOCD: [rtt-debugger-support-package](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) +- Extract it to a specified directory, for example: `C:\DevTools\openocd-hpmicro` +- Set environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +### Getting Started with a Specific BSP + +1. **Navigate to the desired BSP directory**: + ```bash + cd rt-thread/bsp/hpmicro/ + ``` + +2. **Configure the project**: + - Open RT-Thread ENV command-line + - Change directory to the BSP directory + - Run `menuconfig` to configure the project + +3. **Build the project**: + ```bash + scons -jN # N equals to the number of CPU cores + ``` + +4. **Hardware Connection**: + - Switch BOOT pin to 2'b00 + - Connect the `PWR_DEBUG` port to PC via TYPE-C cable + +5. **Download and Debug**: + - Use the provided OpenOCD scripts for downloading and debugging + - Refer to individual BSP README files for specific commands + +### Running Results + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool (115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +msh > +``` + +## Common Peripheral Support + +Most HPMicro BSPs support the following peripherals: + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | -------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| UART | √ | | +| PWM | √ | | +| RTC | √ | | +| On-Board Debugger | √ | ft2232 | + +Additional peripherals may be supported depending on the specific board: +- **Ethernet**: Available on + - HPM6300EVK + - HPM6750EVK + - HPM6750EVK2 + - HPM6750EVKMINI + ART-Pi Industry IO extension + - HPM6800EVK + - HPM6E00EVK + - HPM6P00EVK + - HPM5E00EVK +- **CAN**: Available on HPM6750 series Development Boards, HPM5300EVK, HPM6800EVK, HPM6E00EVK, HPM6P00EVK and HPM5E00EVK +- **SDIO**: Available on HPM6300EVK, HPM6750EVKMINI, HPM6750EVK, HPM6750EVK2 and HPM6800EVK +- **Display/Audio**: Available on HPM6750EVK, HPM6800EVK, HPM6E00EVK，HPM6P00EVK + +## Development Environment Setup + + +### Using Command Line Tools + +1. Set up the environment variables as described in the Prerequisites section +2. Use `scons` for building +3. Use OpenOCD and GDB for debugging or use the Ozone + JLink for debugging + +## Individual BSP Documentation + +Each BSP contains its own detailed README file with: +- Board-specific hardware information +- Peripheral configuration details +- Specific download and debug commands +- Advanced features and examples + +Please refer to the individual BSP directories for detailed documentation: +- `hpm5300evk/README.md` +- `hpm5301evklite/README.md` +- `hpm5e00evk/README.md` +- `hpm6200evk/README.md` +- `hpm6300evk/README.md` +- `hpm6750evk/README.md` +- `hpm6750evk2/README.md` +- `hpm6750evkmini/README.md` +- `hpm6800evk/README.md` +- `hpm6e00evk/README.md` +- `hpm6p00evk/README.md` + +## Troubleshooting + +### Common Issues + +1. **Toolchain not found**: Ensure `RTT_RISCV_TOOLCHAIN` environment variable is set correctly +2. **OpenOCD connection failed**: Check USB connection and driver installation +3. **Build errors**: Verify all dependencies are installed and environment variables are set +4. **Serial communication issues**: Check baud rate (115200) and COM port settings + +### Getting Help + +- Check the individual BSP README files for board-specific issues +- Visit [RT-Thread Community](https://club.rt-thread.org/) +- Refer to [RT-Thread Documentation](https://www.rt-thread.org/document/site/) + +## References + +- [RT-Thread Document Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread ENV](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPMicro Official Website](https://www.hpmicro.com/) +- [HPMicro SDK Documentation](https://hpmicro.github.io/) +- [RISC-V Toolchain](https://github.com/riscv/riscv-gnu-toolchain) + +## Contributing + +Contributions to enhance existing BSPs or add new ones are welcome. Please follow the RT-Thread contribution guidelines and ensure that your BSP adheres to the project's standards. + +For contributing to HPMicro BSPs: +1. Fork the `RT-Thread` repository +2. Create a feature branch +3. Make your changes following the existing code style +4. Test your changes thoroughly +5. Submit a pull request with a clear description + +## License + +This BSP is released under the [RT-Thread license](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE). \ No newline at end of file diff --git a/bsp/hpmicro/README_zh.md b/bsp/hpmicro/README_zh.md new file mode 100644 index 00000000000..ac006d2f928 --- /dev/null +++ b/bsp/hpmicro/README_zh.md @@ -0,0 +1,192 @@ +# HPMicro 板级支持包 (BSP) 介绍 + +[English](README.md) | + +## 简介 + +本文档提供了 RT-Thread 仓库中可用的 HPMicro BSP（板级支持包）的概述。每个 BSP 都针对特定的 HPMicro 开发板进行了定制，提供必要的驱动程序和配置，以便在基于 RISC-V 的 HPMicro 微控制器上无缝运行 RT-Thread。 + +本文档包含以下部分： + +- HPMicro BSP 概述 +- 可用的 BSP +- 快速开始指南 +- 通用开发环境设置 +- 参考资料 + +通过阅读快速开始指南部分，开发者可以快速上手任何 HPMicro BSP 并在开发板上运行 RT-Thread。每个单独的 BSP 都包含特定开发板功能和高级用法的详细文档。 + +## 可用的 BSP + +以下是当前支持的 HPMicro BSP 的完整列表： + +| BSP 名称 | 支持的开发板 | MCU | 描述 | +|----------|-------------|-----|------| +| hpm5300evk | HPM5300EVK | HPM5361 | HPM5300 系列开发板 | +| hpm5301evklite | HPM5301EVKLITE | HPM5301 | HPM5301精简版开发板 | +| hpm5e00evk | HPM5E00EVK | HPM5E31 | HPM5E00 系列开发板 | +| hpm6200evk | HPM6200EVK | HPM6200 | HPM6200 系列开发板 | +| hpm6300evk | HPM6300EVK | HPM6360 | HPM6300 系列开发板，支持以太网 | +| hpm6750evk | HPM6750EVK | HPM6750 | HPM6750 系列开发板，双核 RISC-V | +| hpm6750evk2 | HPM6750EVK2 | HPM6750 | HPM6750 系列第二代开发板 | +| hpm6750evkmini | HPM6750EVKMINI | HPM6750 | HPM6750 系列迷你开发板 | +| hpm6800evk | HPM6800EVK | HPM6800 | HPM6800 系列开发板 | +| hpm6e00evk | HPM6E00EVK | HPM6E00 | HPM6E00 系列开发板 | +| hpm6p00evk | HPM6P00EVK | HPM6P00 | HPM6P00 系列开发板 | + +## 快速开始指南 + +### 前提条件 + +在开始使用任何 HPMicro BSP 之前，您需要准备以下开发环境： + +#### 1. RT-Thread ENV +- 下载并安装 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) + +#### 2. RISC-V 工具链 +- 下载 RISC-V 工具链：[riscv32-gnu-toolchain](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) +- 解压到指定目录，例如：`C:\DevTools\riscv32-gnu-toolchain` +- 设置环境变量 `RTT_RISCV_TOOLCHAIN` 为 `\bin` + - 例如：`C:\DevTools\riscv32-gnu-toolchain\bin` + +#### 3. HPMicro 专用 OpenOCD +- 下载 OpenOCD：[rtt-debugger-support-package](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) +- 解压到指定目录，例如：`C:\DevTools\openocd-hpmicro` +- 设置环境变量 `OPENOCD_HPMICRO` 为 `\bin` + - 例如：`C:\DevTools\openocd-hpmicro\bin` + +### 使用特定 BSP 开始 + +1. **导航到所需的 BSP 目录**： + ```bash + cd rt-thread/bsp/hpmicro/ + ``` + +2. **配置项目**： + - 打开 RT-Thread ENV 命令行 + - 切换到 BSP 目录 + - 运行 `menuconfig` 来配置项目 + +3. **构建项目**： + ```bash + scons -jN # N 等于 CPU 核心数 + ``` + +4. **硬件连接**： + - 将 BOOT 引脚切换到 2'b00 + - 通过 TYPE-C 线缆将 `PWR_DEBUG` 端口连接到 PC + +5. **下载和调试**： + - 使用提供的 OpenOCD 脚本进行下载和调试 + - 参考各个 BSP 的 README 文件获取具体命令 + +### 运行结果 + +项目成功下载后，系统会自动运行。开发板上的 LED 会周期性闪烁。 + +将开发板的串口连接到 PC，通过串口终端工具（115200-8-1-N）与其通信。重置开发板后，将观察到 RT-Thread 的启动信息： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +msh > +``` + +## 通用外设支持 + +大多数 HPMicro BSP 支持以下外设： + +| **板载外设** | **支持** | **备注** | +| ------------ | -------- | -------- | +| USB | √ | | +| QSPI Flash | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| UART | √ | | +| PWM | √ | | +| RTC | √ | | +| 板载调试器 | √ | ft2232 | + +根据特定开发板，可能支持其他外设： +- **以太网**：在如下开发板上可用 + - HPM6300EVK + - HPM6750EVK + - HPM6750EVK2 + - HPM6750EVKMINI + ART-Pi Industry IO 扩展板 + - HPM6800EVK + - HPM6E00EVK + - HPM6P00EVK + - HPM5E00EVK +- **CAN**：HPM5300EVK、HPM6750系列开发板，HPM6300EVK，HPM6800EVK, HPM6E00EVK, HPM6P00EVK 和HPM5E00EVK +- **SDIO**：HPM6300EVK、HPM6750EVK 系列可用 +- **显示/音频**：HPM6750EVK 系列可用 + +## 开发环境设置 + +### 使用命令行工具 + +1. 按照前提条件部分所述设置环境变量 +2. 使用 `scons` 进行构建 +3. 使用 OpenOCD 和 GDB 进行调试 + +## 各个 BSP 文档 + +每个 BSP 都包含自己的详细 README 文件，内容包括： +- 特定开发板的硬件信息 +- 外设配置详情 +- 具体的下载和调试命令 +- 高级功能和示例 + +请参考各个 BSP 目录获取详细文档： +- `hpm5300evk/README.md` +- `hpm5301evklite/README.md` +- `hpm5e00evk/README.md` +- `hpm6200evk/README.md` +- `hpm6300evk/README.md` +- `hpm6750evk/README.md` +- `hpm6750evk2/README.md` +- `hpm6750evkmini/README.md` +- `hpm6800evk/README.md` +- `hpm6e00evk/README.md` +- `hpm6p00evk/README.md` + +## 故障排除 + +### 常见问题 + +1. **找不到工具链**：确保 `RTT_RISCV_TOOLCHAIN` 环境变量设置正确 +2. **OpenOCD 连接失败**：检查 USB 连接和驱动程序安装 +3. **构建错误**：验证所有依赖项已安装且环境变量已设置 +4. **串口通信问题**：检查波特率（115200）和 COM 端口设置 + +### 获取帮助 + +- 查看各个 BSP 的 README 文件了解特定开发板的问题 +- 访问 [RT-Thread 社区](https://club.rt-thread.org/) +- 参考 [RT-Thread 文档](https://www.rt-thread.org/document/site/) + +## 参考资料 + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread ENV](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPMicro 官方网站](https://www.hpmicro.com/) +- [HPMicro SDK 文档](https://hpmicro.github.io/) +- [RISC-V 工具链](https://github.com/riscv/riscv-gnu-toolchain) + +## 贡献 + +欢迎对增强现有 BSP 或添加新 BSP 做出贡献。请遵循 RT-Thread 贡献指南，确保您的 BSP 符合项目标准。 + +为 HPMicro BSP 做出贡献： +1. Fork `RT-Thread` 仓库 +2. 创建功能分支 +3. 按照现有代码风格进行更改 +4. 彻底测试您的更改 +5. 提交带有清晰描述的拉取请求 + +## 许可证 + +此 BSP 在 [RT-Thread 许可证](https://github.com/RT-Thread/rt-thread/blob/master/LICENSE) 下发布。 diff --git a/bsp/hpmicro/hpm5300evk/.config b/bsp/hpmicro/hpm5300evk/.config index f1f2ad94582..8545ddc59bc 100644 --- a/bsp/hpmicro/hpm5300evk/.config +++ b/bsp/hpmicro/hpm5300evk/.config @@ -104,8 +104,6 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options CONFIG_RT_NAME_MAX=8 @@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -376,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -483,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -572,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -617,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -710,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -791,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -833,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -846,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1017,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1355,20 +1394,28 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM5300_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM5000=y +CONFIG_SOC_HPM5300=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y CONFIG_BSP_UART0_RX_BUFSIZE=128 CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART7 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_GPTMR is not set diff --git a/bsp/hpmicro/hpm5300evk/SConstruct b/bsp/hpmicro/hpm5300evk/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm5300evk/SConstruct +++ b/bsp/hpmicro/hpm5300evk/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm5300evk/board/Kconfig b/bsp/hpmicro/hpm5300evk/board/Kconfig index 20bc12d04ba..b02bba277d9 100644 --- a/bsp/hpmicro/hpm5300evk/board/Kconfig +++ b/bsp/hpmicro/hpm5300evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM5000 +config SOC_HPM5300 bool - select SOC_SERIES_HPM5300 + select SOC_HPM5300_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers" bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -41,6 +47,10 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -64,6 +74,118 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART7 bool "Enable UART7" @@ -95,29 +217,125 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif config BSP_USING_SPI1 bool "Enable SPI1" default y if BSP_USING_SPI1 config BSP_SPI1_USING_DMA - bool "Enable SPI1 DMA" - default n + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice endif config BSP_USING_SPI2 bool "Enable SPI2" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice endif config BSP_USING_SPI3 bool "Enable SPI3" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice endif endif @@ -126,35 +344,98 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_HWTIMER if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C bool "Enable I2C" default n + select RT_USING_I2C if BSP_USING_I2C if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" default y - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" - default n - endif - + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" - default n - endif + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_XPI_FLASH @@ -165,6 +446,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n + select RT_USING_PWM if BSP_USING_PWM menuconfig BSP_USING_USB bool "Enable USB" @@ -172,6 +454,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB HOST" @@ -200,15 +483,39 @@ menu "On-chip Peripheral Drivers" config BSP_USING_MCAN0 bool "Enable MCAN0" default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN1 bool "Enable MCAN1" default n + if BSP_USING_MCAN1 + config BSP_MCAN1_IRQ_PRIORITY + int "MCAN1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN2 bool "Enable MCAN2" default n + if BSP_USING_MCAN2 + config BSP_MCAN2_IRQ_PRIORITY + int "MCAN2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN3 bool "Enable MCAN3" default n + if BSP_USING_MCAN3 + config BSP_MCAN3_IRQ_PRIORITY + int "MCAN3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC @@ -226,11 +533,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC1 bool "Enable ADC1" default n - config BSP_USING_ADC2 - bool "Enable ADC2" - default n endif endif endmenu - endmenu diff --git a/bsp/hpmicro/hpm5300evk/board/board.c b/bsp/hpmicro/hpm5300evk/board/board.c index ce3f1ee0cee..f967e2deb70 100644 --- a/bsp/hpmicro/hpm5300evk/board/board.c +++ b/bsp/hpmicro/hpm5300evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -13,8 +13,8 @@ #include "hpm_pllctlv2_drv.h" #include "hpm_i2c_drv.h" #include "hpm_pcfg_drv.h" +#include -static board_timer_cb timer_cb; /** * @brief FLASH configuration option definitions: @@ -49,7 +49,7 @@ static board_timer_cb timer_cb; * 2 - Internal loopback * 3 - External DQS * [3:0] Frequency option - * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz * * option[2] (Effective only if the bit[3:0] in option[0] > 1) * [31:20] Reserved @@ -70,11 +70,11 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0}; +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -89,8 +89,6 @@ void board_init_console(void) */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -143,7 +141,6 @@ void board_print_clock_freq(void) void board_init(void) { - init_xtal_pins(); init_py_pins_as_pgpio(); board_init_usb_dp_dm_pins(); @@ -176,7 +173,7 @@ void board_init_usb_dp_dm_pins(void) } else { uint8_t tmp; tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); - sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); /* NOLINT */ clock_add_to_group(clock_usb0, 0); usb_phy_disable_dp_dm_pulldown(HPM_USB0); clock_remove_from_group(clock_usb0, 0); @@ -205,67 +202,26 @@ void board_init_clock(void) clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_rom, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart1, 0); - clock_add_to_group(clock_uart2, 0); - clock_add_to_group(clock_uart3, 0); - clock_add_to_group(clock_uart4, 0); - clock_add_to_group(clock_uart5, 0); - clock_add_to_group(clock_uart6, 0); - /* group0[1] */ - clock_add_to_group(clock_uart7, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_watchdog1, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_tsns, 0); - clock_add_to_group(clock_crc0, 0); - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_dac0, 0); - clock_add_to_group(clock_dac1, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_opa0, 0); - clock_add_to_group(clock_opa1, 0); clock_add_to_group(clock_mot0, 0); - clock_add_to_group(clock_rng, 0); - clock_add_to_group(clock_sdp, 0); - clock_add_to_group(clock_kman, 0); clock_add_to_group(clock_gpio, 0); clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xpi0, 0); - clock_add_to_group(clock_usb0, 0); + clock_add_to_group(clock_ptpc, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Bump up DCDC voltage to 1175mv */ - pcfg_dcdc_set_voltage(HPM_PCFG, 1175); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3); /* Configure PLL0 Post Divider */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 960MHz */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 600MHz */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 400MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0); /* PLL0CLK0: 960MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p6); /* PLL0CLK1: 600MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk2, pllctlv2_div_2p4); /* PLL0CLK2: 400MHz */ /* Configure PLL0 Frequency to 960MHz */ - pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 960000000); + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, 960000000); clock_update_core_clock(); @@ -283,6 +239,9 @@ void board_delay_ms(uint32_t ms) clock_cpu_delay_ms(ms); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -290,7 +249,6 @@ void board_timer_isr(void) timer_cb(); } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); void board_timer_create(uint32_t ms, board_timer_cb cb) { @@ -310,6 +268,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_init_gpio_pins(void) { @@ -323,15 +282,19 @@ void board_init_led_pins(void) gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); } -void board_init_usb_pins(void) +void board_init_usb(USB_Type *ptr) { - init_usb_pins(); - usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); - /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ - board_delay_ms(100); + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); - /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ - /* usb_phy_using_internal_vbus(BOARD_USB); */ + /* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + /* usb_phy_using_internal_vbus(ptr); */ + } } void board_led_write(uint8_t state) @@ -383,18 +346,12 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); } -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -402,10 +359,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); } - + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -413,7 +370,7 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc1, clk_adc_src_ana1); clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U); } - + clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); } @@ -425,6 +382,17 @@ void board_init_adc16_pins(void) init_adc_pins(); } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; @@ -438,7 +406,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) clock_set_dac_source(clock_dac0, clk_dac_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2); } - + clock_add_to_group(clock_dac0, 0); freq = clock_get_frequency(clock_dac0); } else if (ptr == HPM_DAC1) { if (clk_src_ahb == true) { @@ -449,7 +417,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) clock_set_dac_source(clock_dac1, clk_dac_src_ana3); clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); } - + clock_add_to_group(clock_dac1, 0); freq = clock_get_frequency(clock_dac1); } @@ -487,17 +455,6 @@ uint32_t board_init_can_clock(MCAN_Type *ptr) return freq; } -uint32_t board_init_pwm_clock(PWM_Type *ptr) -{ - uint32_t freq = 0; - (void) ptr; - - clock_add_to_group(clock_mot0, 0); - freq = clock_get_frequency(clock_mot0); - - return freq; -} - void board_init_rgb_pwm_pins(void) { init_led_pins_as_pwm(); @@ -536,26 +493,19 @@ uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { - clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 8); clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else if (ptr == HPM_UART3) { - clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 8); clock_add_to_group(clock_uart3, 0); freq = clock_get_frequency(clock_uart3); - } else if (ptr == HPM_UART7) { - clock_set_source_divider(clock_uart7, clk_src_pll0_clk2, 6); /* 80MHz */ - clock_add_to_group(clock_uart7, 0); - freq = clock_get_frequency(clock_uart7); } + return freq; } @@ -577,39 +527,51 @@ void board_i2c_bus_clear(I2C_Type *ptr) printf("I2C bus is ready\n"); return; } - i2s_gen_reset_signal(ptr, 9); + i2c_gen_reset_signal(ptr, 9); board_delay_ms(100); printf("I2C bus is cleared\n"); } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { i2c_config_t config; hpm_stat_t stat; uint32_t freq; - if (ptr == NULL) { - return; - } + + freq = board_init_i2c_clock(ptr); init_i2c_pins(ptr); board_i2c_bus_clear(ptr); - - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } - } void board_init_adc_qeiv2_pins(void) @@ -629,34 +591,37 @@ void board_lin_transceiver_control(bool enable) } } +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} + uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) { - uint32_t freq = 0; - clock_name_t gptmr_clock =0; - uint32_t HPM_GPTMR = (uint32_t)ptr; - bool gptmr_valid = true; - - switch(HPM_GPTMR){ - case HPM_GPTMR0_BASE: - gptmr_clock = clock_gptmr0; - break; - case HPM_GPTMR1_BASE: - gptmr_clock = clock_gptmr1; - break; - case HPM_GPTMR2_BASE: - gptmr_clock = clock_gptmr2; - break; - case HPM_GPTMR3_BASE: - gptmr_clock = clock_gptmr3; - break; - default: - gptmr_valid = false; - } - if(gptmr_valid) - { - clock_add_to_group(gptmr_clock, 0); - clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(gptmr_clock); + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ } return freq; } + diff --git a/bsp/hpmicro/hpm5300evk/board/board.h b/bsp/hpmicro/hpm5300evk/board/board.h index ab2718b88e4..8593a05c2e0 100644 --- a/bsp/hpmicro/hpm5300evk/board/board.h +++ b/bsp/hpmicro/hpm5300evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -23,6 +23,7 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ @@ -41,14 +42,24 @@ /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART2 -#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart2 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PA26 + +/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */ +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr3 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 + /* uart lin sample section */ #define BOARD_UART_LIN HPM_UART3 #define BOARD_UART_LIN_IRQ IRQn_UART3 @@ -56,7 +67,6 @@ #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOA #define BOARD_UART_LIN_TX_PIN (15U) /* PA15 should align with used pin in pinmux configuration */ - #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART @@ -64,9 +74,9 @@ #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #endif @@ -82,6 +92,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* modbus sample section */ #define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE @@ -126,13 +138,12 @@ /* 12V Power Enable for lin transceiver */ #define BOARD_SUPPORT_LIN_TRANSCEIVER_CONTROL 1 -#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 -#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA -#define BOARD_12V_EN_GPIO_PIN 24 -#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL HPM_GPIO0 -#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA -#define BOARD_LIN_TRANSCEIVER_GPIO_PIN 13 - +#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 +#define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_12V_EN_GPIO_PIN 24 +#define BOARD_LIN_TRANSCEIVER_GPIO_CTRL HPM_GPIO0 +#define BOARD_LIN_TRANSCEIVER_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LIN_TRANSCEIVER_GPIO_PIN 13 /* gpiom section */ #define BOARD_APP_GPIOM_BASE HPM_GPIOM @@ -144,6 +155,7 @@ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA #define BOARD_APP_GPIO_PIN 9 #define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A +#define BOARD_BUTTON_PRESSED_VALUE 0 /* spi section */ #define BOARD_APP_SPI_BASE HPM_SPI1 @@ -164,12 +176,14 @@ #define BOARD_APP_ADC16_IRQn IRQn_ADC0 #define BOARD_APP_ADC16_CH_1 (13U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) -#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI -#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A @@ -206,6 +220,7 @@ #define BOARD_APP_TRGM HPM_TRGM0 #define BOARD_APP_PWM_IRQ IRQn_PWM0 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM0_SYNCI +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 /*BLDC pwm*/ /*PWM define*/ @@ -231,15 +246,16 @@ /*HALL define*/ /*RDC*/ +#define BOARD_RDC_BASE HPM_RDC #define BOARD_RDC_TRGM HPM_TRGM0 -#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 -#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0 -#define BOARD_RDC_TRG_ADC_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_RDC_TRG_IN HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 +#define BOARD_RDC_TRG_OUT TRGM_TRGOCFG_MOT_GPIO0 +#define BOARD_RDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_RDC_ADC_I_BASE HPM_ADC0 #define BOARD_RDC_ADC_Q_BASE HPM_ADC1 #define BOARD_RDC_ADC_I_CHN (5U) #define BOARD_RDC_ADC_Q_CHN (6U) -#define BOARD_RDC_ADC_IRQn IRQn_ADC0 +#define BOARD_RDC_IRQ IRQn_RDC #define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete #define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A @@ -250,16 +266,44 @@ #define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) #define BOARD_BLDC_QEI_CLOCK_SOURCE clock_mot0 #define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) -#define BOARD_BLDC_QEI_ADC_MATRIX_ADC0 trgm_adc_matrix_output_to_qei1_adc0 -#define BOARD_BLDC_QEI_ADC_MATRIX_ADC1 trgm_adc_matrix_output_to_qei1_adc1 + +#define BOARD_APP_QEIV2_BASE HPM_QEI1 +#define BOARD_APP_QEIV2_IRQ IRQn_QEI1 +#define BOARD_APP_QEI_CLOCK_SOURCE clock_mot0 +#define BOARD_APP_QEI_ADC_COS_BASE HPM_ADC0 +#define BOARD_APP_QEI_ADC_COS_CHN (4U) +#define BOARD_APP_QEI_ADC_SIN_BASE HPM_ADC1 +#define BOARD_APP_QEI_ADC_SIN_CHN (5U) +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_qei1_adc0 +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei1_adc1 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc0 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc1 +#define BOARD_APP_QEI_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A /*Timer define*/ #define BOARD_BLDC_TMR_1MS HPM_GPTMR2 #define BOARD_BLDC_TMR_CH 0 #define BOARD_BLDC_TMR_CMP 0 #define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 #define BOARD_BLDC_TMR_RELOAD (100000U) +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) + /*adc*/ #define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 @@ -275,23 +319,38 @@ #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_DMA_MUX_SRC HPM_DMA_SRC_MOT_0 +#define BOARD_BLDC_DMA_CHN (0U) +#define BOARD_BLDC_DMA_TRG_DST TRGM_TRGOCFG_TRGM_DMA0 +#define BOARD_BLDC_DMA_TRG_SRC HPM_TRGM0_DMA_SRC_TRGM0 +#define BOARD_BLDC_DMA_TRG_INDEX TRGM_DMACFG_0 +#define BOARD_BLDC_DMA_TRG_CMP_INDEX (9U) +#define BOARD_BLDC_DMA_TRG_IN HPM_TRGM0_INPUT_SRC_PWM0_CH9REF + +/* PLB */ +#define BOARD_PLB_CLOCK_NAME clock_mot0 #define BOARD_PLB_COUNTER HPM_PLB #define BOARD_PLB_PWM_BASE HPM_PWM0 #define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 #define BOARD_PLB_TRGM HPM_TRGM0 #define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_CH8REF) -#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00) -#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02) -#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00) -#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO2) +#define BOARD_PLB_IN_PWM_TRG (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT16) +#define BOARD_PLB_TO_TRG_IN (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_TRG_OUT (HPM_TRGM0_OUTPUT_SRC_TRGM0_P2) #define BOARD_PLB_IO_TRG_SHIFT (2) #define BOARD_PLB_PWM_CMP (8U) #define BOARD_PLB_PWM_CHN (8U) #define BOARD_PLB_CHN plb_chn0 +#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P4 +#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 +#define BOARD_PLB_FILTER_IO_TRG_SHIFT (2) + /* QEO */ #define BOARD_QEO HPM_QEO0 #define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0 @@ -302,13 +361,12 @@ /* SEI */ #define BOARD_SEI HPM_SEI #define BOARD_SEI_CTRL SEI_CTRL_1 -#define BOARD_SEI_IRQn IRQn_SEI1 - -/* USB */ -#define BOARD_USB HPM_USB0 +#define BOARD_SEI_IRQn IRQn_SEI0_1 +#define BOARD_SEI_CLOCK_NAME clock_mot0 /* OPAMP */ -#define BOARD_APP_OPAMP HPM_OPAMP0 +#define BOARD_APP_OPAMP HPM_OPAMP0 +#define BOARD_APP_OPAMP_CLOCK clock_opa0 #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 @@ -323,11 +381,62 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR2 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 +#define BOARD_THREADX_TIMER HPM_GPTMR2 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR2 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr2 + +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_I2S_SPI_CS_GPIO_PIN 11 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA11 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 3 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 1 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 0 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 2 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0 + +#define BOARD_APP_CLK_REF_PIN_NAME "P1[15] (PA30)" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0 +#define BOARD_APP_CLK_REF_SRC_NAME clk_src_pll1_clk1 +#define BOARD_APP_PLLCTLV2_TEST_PLL pllctlv2_pll1 +#define BOARD_APP_PLLCTLV2_TEST_PLL_CLK pllctlv2_clk1 +#define BOARD_APP_PLLCTLV2_TEST_PLL_NAME clk_pll1clk1 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -338,16 +447,17 @@ void board_init(void); void board_init_console(void); void board_init_gpio_pins(void); void board_init_led_pins(void); -void board_init_usb_pins(void); +void board_init_usb(USB_Type *ptr); void board_led_write(uint8_t state); void board_led_toggle(void); void board_init_uart(UART_Type *ptr); uint32_t board_init_spi_clock(SPI_Type *ptr); void board_init_spi_pins(SPI_Type *ptr); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); void board_init_adc16_pins(void); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); +void board_init_acmp_pins(void); +void board_init_acmp_clock(ACMP_Type *ptr); void board_init_can(MCAN_Type *ptr); uint32_t board_init_can_clock(MCAN_Type *ptr); void board_init_rgb_pwm_pins(void); @@ -372,13 +482,17 @@ void board_init_pmp(void); uint32_t board_init_uart_clock(UART_Type *ptr); void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_adc_qeiv2_pins(void); void board_lin_transceiver_control(bool enable); + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void board_init_clk_ref_pin(void); uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); -uint32_t board_init_pwm_clock(PWM_Type *ptr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 77% rename from bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld index f11f360946b..12af13362ed 100644 --- a/bsp/hpmicro/hpm5300evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768 AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K } @@ -41,22 +41,25 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -77,12 +80,12 @@ SECTIONS KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -107,12 +110,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -146,6 +143,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -158,19 +169,14 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; } > DLM /* Note: the .tbss and .tdata section should be adjacent */ @@ -178,22 +184,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -221,10 +231,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -245,6 +255,26 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; .heap(NOLOAD) : { @@ -265,7 +295,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -276,8 +307,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > DLM diff --git a/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld index 196cbe56efe..26d57856025 100644 --- a/bsp/hpmicro/hpm5300evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm5300evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000; MEMORY { ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + DLM (w) : ORIGIN = 0x80300, LENGTH = 96K - 768 NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k } SECTIONS @@ -30,10 +30,6 @@ SECTIONS KEEP(*(.vector_table)) . = ALIGN(8); } > ILM - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > ILM .text : { . = ALIGN(8); @@ -56,7 +52,7 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(8); - + /********************************************* * * RT-Thread related sections - Start @@ -92,28 +88,74 @@ SECTIONS __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); } > ILM - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .tdata : AT(etext) { + .rel : { + KEEP(*(.rel*)) + } > DLM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > ILM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; - + *(.data) *(.data*) *(.sdata) @@ -138,10 +180,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -164,43 +206,39 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > DLM - - .rel : { - KEEP(*(.rel*)) - } > DLM - .bss(NOLOAD) : { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM + } > NONCACHEABLE_RAM - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; @@ -221,24 +259,4 @@ SECTIONS .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); } diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.c b/bsp/hpmicro/hpm5300evk/board/pinmux.c index 2f17df67529..268926772e9 100644 --- a/bsp/hpmicro/hpm5300evk/board/pinmux.c +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,15 +15,6 @@ #include "board.h" #include "pinmux.h" -void init_xtal_pins(void) -{ - /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ - /* - * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - */ -} - void init_py_pins_as_pgpio(void) { /* Set PY00-PY05 default function to PGPIO */ @@ -48,10 +39,6 @@ void init_uart_pins(UART_Type *ptr) /* using for uart_lin function */ HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_UART3_RXD; HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_UART3_TXD; - } else if (ptr == HPM_UART7) { - /* using for uart_lin function */ - HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_UART7_TXD; - HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_UART7_RXD; } else { ; } @@ -115,6 +102,13 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -126,6 +120,13 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PA25].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -136,6 +137,7 @@ void init_gptmr_pins(GPTMR_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0; HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0; HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3; } } @@ -197,31 +199,27 @@ void init_adc_qeiv2_pins(void) HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 /ADC1.5 */ } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */ - /* - * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - */ - - /* Package QFN32 should be set PA26 and PA27 pins as analog type to enable USB_P and USB_N. */ - /* - * HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - * HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - */ + if (ptr == HPM_USB0) { + /* Package QFN48 and LQFP64 should be set PA24 and PA25 pins as analog type to enable USB_P and USB_N. */ + /* + * HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + * HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + */ + + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; - /* USB0_ID */ - HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; - /* USB0_OC */ - HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; - /* USB0_PWR */ - HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; - - /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; - HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; - HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; + } } void init_can_pins(MCAN_Type *ptr) @@ -254,8 +252,15 @@ void init_dac_pins(DAC_Type *ptr) } } -void init_plb_pins(void) +void init_plb_pulse_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02; +} + +void init_plb_filter_pins(void) { + HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_TRGM0_P_04; HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_TRGM0_P_02; } @@ -323,3 +328,41 @@ void init_opamp_pins(void) HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } + + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR0) { + if (as_comp) { + switch (channel) { + case 0: + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR0_COMP_0; + break; + case 1: + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + break; + case 3: + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3; + break; + default: + break; + } + } else { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0; + } + } + } +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_SOC_REF0; +} diff --git a/bsp/hpmicro/hpm5300evk/board/pinmux.h b/bsp/hpmicro/hpm5300evk/board/pinmux.h index 1ff17798655..738593a2b64 100644 --- a/bsp/hpmicro/hpm5300evk/board/pinmux.h +++ b/bsp/hpmicro/hpm5300evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,7 +11,6 @@ #ifdef __cplusplus extern "C" { #endif -void init_xtal_pins(void); void init_py_pins_as_pgpio(void); void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); @@ -28,12 +27,13 @@ void init_pwm_pins(PWM_Type *ptr); void init_adc_pins(void); void init_adc_bldc_pins(void); void init_adc_qeiv2_pins(void); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_can_pins(MCAN_Type *ptr); void init_dac_pins(DAC_Type *ptr); void init_led_pins_as_gpio(void); void init_led_pins_as_pwm(void); -void init_plb_pins(void); +void init_plb_pulse_pins(void); +void init_plb_filter_pins(void); void init_qeo_pins(QEO_Type *ptr); void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); void init_rdc_pin(void); @@ -42,6 +42,10 @@ void init_qeiv2_ab_pins(QEIV2_Type *ptr); void init_qeiv2_abz_pins(QEIV2_Type *ptr); void init_opamp_pins(void); void init_lin_transceiver_ctrl_pin(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pin(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.c b/bsp/hpmicro/hpm5300evk/board/rtt_board.c index bb0dcdd1888..e5b5d95897e 100644 --- a/bsp/hpmicro/hpm5300evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.c @@ -52,7 +52,7 @@ void rtt_board_init(void) os_tick_config(); /* Configure the USB pins*/ - board_init_usb_pins(); + board_init_usb(HPM_USB0); /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ rt_hw_uart_init(); @@ -63,6 +63,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); } @@ -95,7 +96,7 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); + board_init_usb(HPM_USB0); } ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) @@ -107,7 +108,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->SOFTWARE_RESET = 1000U; while(1) { @@ -127,3 +128,50 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk2, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + (void) ptr; + + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif diff --git a/bsp/hpmicro/hpm5300evk/board/rtt_board.h b/bsp/hpmicro/hpm5300evk/board/rtt_board.h index 78b51752c62..d6aa4c2f971 100644 --- a/bsp/hpmicro/hpm5300evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm5300evk/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,8 +10,10 @@ #include "hpm_common.h" #include "hpm_soc.h" #include +#include "board.h" /* gpio section */ +#define APP_LED0 (0U) #define APP_LED0_PIN_NUM GET_PIN(A, 23) #define APP_LED_ON (1) #define APP_LED_OFF (0) @@ -19,6 +21,11 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* CAN section */ #define BOARD_CAN_NAME "can0" #define BOARD_CAN_HWFILTER_INDEX (0U) @@ -31,6 +38,10 @@ #define BOARD_PWM_NAME "pwm0" #define BOARD_PWM_CHANNEL (6) +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + #define IRQn_PendSV IRQn_DEBUG0 /*************************************************************** diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.h b/bsp/hpmicro/hpm5300evk/rtconfig.h index b9bbf3995a2..ab0ca761fd5 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.h +++ b/bsp/hpmicro/hpm5300evk/rtconfig.h @@ -104,6 +104,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -300,6 +302,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -379,18 +395,21 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM5300_SERIES /* Hardware Drivers Config */ -#define SOC_HPM5000 +#define SOC_HPM5300 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_UART0_RX_BUFSIZE 128 #define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm5300evk/rtconfig.py b/bsp/hpmicro/hpm5300evk/rtconfig.py index 610c915fd3a..5f213308c5a 100644 --- a/bsp/hpmicro/hpm5300evk/rtconfig.py +++ b/bsp/hpmicro/hpm5300evk/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c index b0bab335d52..36ec0334321 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/startup.c @@ -4,125 +4,132 @@ * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt - */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S index 2708b48e455..fa7e7f9c1cd 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/port_gcc.S @@ -5,7 +5,7 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S index 76463936442..2ba3169ea4c 100644 --- a/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm5300evk/startup/HPM5361/toolchains/gcc/start.S @@ -62,7 +62,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm5301evklite/.config b/bsp/hpmicro/hpm5301evklite/.config index c56b54aaab8..43cbfbcd350 100644 --- a/bsp/hpmicro/hpm5301evklite/.config +++ b/bsp/hpmicro/hpm5301evklite/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -376,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -483,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -572,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -617,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -710,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -791,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -833,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -846,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1017,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1355,21 +1394,26 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM5300_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM5000=y +CONFIG_SOC_HPM5300=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y CONFIG_BSP_UART0_RX_BUFSIZE=128 CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set -# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART3 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set diff --git a/bsp/hpmicro/hpm5301evklite/SConstruct b/bsp/hpmicro/hpm5301evklite/SConstruct index 93b39143516..a4d1f600062 100644 --- a/bsp/hpmicro/hpm5301evklite/SConstruct +++ b/bsp/hpmicro/hpm5301evklite/SConstruct @@ -55,17 +55,7 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm5301evklite/board/Kconfig b/bsp/hpmicro/hpm5301evklite/board/Kconfig index 2950dc6e485..63888530c25 100644 --- a/bsp/hpmicro/hpm5301evklite/board/Kconfig +++ b/bsp/hpmicro/hpm5301evklite/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM5000 +config SOC_HPM5300 bool - select SOC_SERIES_HPM5300 + select SOC_HPM5300_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -12,6 +12,12 @@ menu "On-chip Peripheral Drivers" bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -41,6 +47,37 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -64,29 +101,37 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 endif - menuconfig BSP_USING_UART6 - bool "Enable UART6" + menuconfig BSP_USING_UART3 + bool "Enable UART3" default n - if BSP_USING_UART6 - config BSP_UART6_RX_USING_DMA - bool "Enable UART6 RX DMA" - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n - config BSP_UART6_TX_USING_DMA - bool "Enable UART6 TX DMA" - depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA default n - config BSP_UART6_RX_BUFSIZE - int "Set UART6 RX buffer size" + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" range 64 65535 depends on RT_USING_SERIAL_V2 default 1024 - config BSP_UART6_TX_BUFSIZE - int "Set UART6 TX buffer size" + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 endif endif @@ -95,48 +140,225 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif config BSP_USING_SPI1 bool "Enable SPI1" default y + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif config BSP_USING_SPI2 bool "Enable SPI2" default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif config BSP_USING_SPI3 bool "Enable SPI3" default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice + endif endif + menuconfig BSP_USING_GPTMR bool "Enable GPTMR" default n select RT_USING_HWTIMER if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C bool "Enable I2C" default n + select RT_USING_I2C if BSP_USING_I2C if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" default y - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" - default n - endif - + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" - default n - endif + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_XPI_FLASH @@ -150,6 +372,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB HOST" diff --git a/bsp/hpmicro/hpm5301evklite/board/board.c b/bsp/hpmicro/hpm5301evklite/board/board.c index 5c966c01141..6d2339c1d41 100644 --- a/bsp/hpmicro/hpm5301evklite/board/board.c +++ b/bsp/hpmicro/hpm5301evklite/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -13,8 +13,7 @@ #include "hpm_pllctlv2_drv.h" #include "hpm_i2c_drv.h" #include "hpm_pcfg_drv.h" - -static board_timer_cb timer_cb; +#include /** * @brief FLASH configuration option definitions: @@ -49,7 +48,7 @@ static board_timer_cb timer_cb; * 2 - Internal loopback * 3 - External DQS * [3:0] Frequency option - * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz * * option[2] (Effective only if the bit[3:0] in option[0] > 1) * [31:20] Reserved @@ -70,11 +69,11 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90002, 0x00000006, 0x1000, 0x0}; +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000005, 0x1000, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -89,8 +88,6 @@ void board_init_console(void) */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -143,7 +140,6 @@ void board_print_clock_freq(void) void board_init(void) { - init_xtal_pins(); init_py_pins_as_pgpio(); board_init_usb_dp_dm_pins(); @@ -176,7 +172,7 @@ void board_init_usb_dp_dm_pins(void) } else { uint8_t tmp; tmp = sysctl_resource_target_get_mode(HPM_SYSCTL, sysctl_resource_xtal); - sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); + sysctl_resource_target_set_mode(HPM_SYSCTL, sysctl_resource_xtal, 0x03); /* NOLINT */ clock_add_to_group(clock_usb0, 0); usb_phy_disable_dp_dm_pulldown(HPM_USB0); clock_remove_from_group(clock_usb0, 0); @@ -199,31 +195,20 @@ void board_init_clock(void) sysctl_clock_set_preset(HPM_SYSCTL, 2); } + /* select XTAL as pll ref clock */ + pllctlv2_select_reference_clock(HPM_PLLCTLV2, pllctlv2_pll0, 0); + pllctlv2_select_reference_clock(HPM_PLLCTLV2, pllctlv2_pll1, 0); + /* group0[0] */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_ahb, 0); clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_rom, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_uart0, 0); - clock_add_to_group(clock_uart3, 0); - - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_watchdog1, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_tsns, 0); - clock_add_to_group(clock_crc0, 0); - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_mot0, 0); /* for trgm and synt peripheral */ clock_add_to_group(clock_gpio, 0); clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xpi0, 0); - clock_add_to_group(clock_usb0, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); @@ -234,11 +219,11 @@ void board_init_clock(void) /* Configure CPU to 360MHz, AXI/AHB to 120MHz */ sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll0_clk0, 2, 3); /* Configure PLL0 Post Divider */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); /* PLL0CLK0: 720MHz */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 1, 3); /* PLL0CLK1: 450MHz */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 2, 7); /* PLL0CLK2: 300MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0); /* PLL0CLK0: 720MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p2); /* PLL0CLK1: 600MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk2, pllctlv2_div_1p8); /* PLL0CLK2: 400MHz */ /* Configure PLL0 Frequency to 720MHz */ - pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, 720000000); + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, 720000000); clock_update_core_clock(); @@ -246,32 +231,6 @@ void board_init_clock(void) clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); } -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) -{ - uint32_t freq = 0; - clock_name_t gptmr_clock =0; - uint32_t HPM_GPTMR = (uint32_t)ptr; - bool gptmr_valid = true; - - switch(HPM_GPTMR){ - case HPM_GPTMR0_BASE: - gptmr_clock = clock_gptmr0; - break; - case HPM_GPTMR1_BASE: - gptmr_clock = clock_gptmr1; - break; - default: - gptmr_valid = false; - } - if(gptmr_valid) - { - clock_add_to_group(gptmr_clock, 0); - clock_set_source_divider(gptmr_clock, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(gptmr_clock); - } - return freq; -} - void board_delay_us(uint32_t us) { clock_cpu_delay_us(us); @@ -282,6 +241,17 @@ void board_delay_ms(uint32_t ms) clock_cpu_delay_ms(ms); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + void board_timer_create(uint32_t ms, board_timer_cb cb) { uint32_t gptmr_freq; @@ -300,6 +270,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_init_gpio_pins(void) { @@ -313,15 +284,19 @@ void board_init_led_pins(void) gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); } -void board_init_usb_pins(void) +void board_init_usb(USB_Type *ptr) { - init_usb_pins(); - usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); - /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ - board_delay_ms(100); + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); - /* As QFN32, QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ - usb_phy_using_internal_vbus(BOARD_USB); + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As QFN48 and LQFP64 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + usb_phy_using_internal_vbus(ptr); + } } void board_led_write(uint8_t state) @@ -373,18 +348,12 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); } -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -404,6 +373,17 @@ void board_init_adc16_pins(void) init_adc_pins(); } +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + void board_disable_output_rgb_led(uint8_t color) { (void) color; @@ -427,15 +407,9 @@ uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); - } else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_pll0_clk2, 6); - clock_add_to_group(clock_uart2, 0); - freq = clock_get_frequency(clock_uart2); } else if (ptr == HPM_UART3) { - clock_set_source_divider(clock_uart3, clk_src_pll0_clk2, 6); /* 50MHz */ clock_add_to_group(clock_uart3, 0); freq = clock_get_frequency(clock_uart3); } @@ -456,35 +430,78 @@ void board_i2c_bus_clear(I2C_Type *ptr) printf("I2C bus is ready\n"); return; } - i2s_gen_reset_signal(ptr, 9); + i2c_gen_reset_signal(ptr, 9); board_delay_ms(100); printf("I2C bus is cleared\n"); } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { i2c_config_t config; hpm_stat_t stat; uint32_t freq; - if (ptr == NULL) { - return; - } + + freq = board_init_i2c_clock(ptr); init_i2c_pins(ptr); board_i2c_bus_clear(ptr); - - clock_add_to_group(clock_i2c2, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } +} + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; } diff --git a/bsp/hpmicro/hpm5301evklite/board/board.h b/bsp/hpmicro/hpm5301evklite/board/board.h index 1c4793fbc6b..ca5146dc36f 100644 --- a/bsp/hpmicro/hpm5301evklite/board/board.h +++ b/bsp/hpmicro/hpm5301evklite/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -23,6 +23,7 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ @@ -39,15 +40,26 @@ #define BOARD_RUNNING_CORE HPM_CORE0 #endif +/* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART3 -#define BOARD_APP_UART_IRQ IRQn_UART3 +#define BOARD_APP_UART_BASE HPM_UART3 +#define BOARD_APP_UART_IRQ IRQn_UART3 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart3 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART3_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART3_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PA26 + +/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */ +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR1 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr1 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 + /* uart lin sample section */ #define BOARD_UART_LIN BOARD_APP_UART_BASE #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ @@ -55,7 +67,6 @@ #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOB #define BOARD_UART_LIN_TX_PIN (15U) /* PB15 should align with used pin in pinmux configuration */ - #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART @@ -63,9 +74,9 @@ #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #endif @@ -81,6 +92,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* modbus sample section */ #define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE @@ -93,26 +106,26 @@ #define BOARD_FLASH_SIZE (SIZE_1MB) /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C2 -#define BOARD_APP_I2C_IRQ IRQn_I2C2 -#define BOARD_APP_I2C_CLK_NAME clock_i2c2 +#define BOARD_APP_I2C_BASE HPM_I2C3 +#define BOARD_APP_I2C_IRQ IRQn_I2C3 +#define BOARD_APP_I2C_CLK_NAME clock_i2c3 #define BOARD_APP_I2C_DMA HPM_HDMA #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C2 +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C3 /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR0 #define BOARD_GPTMR_IRQ IRQn_GPTMR0 -#define BOARD_GPTMR_CHANNEL 0 -#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_CHANNEL 1 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_1 #define BOARD_GPTMR_CLK_NAME clock_gptmr0 #define BOARD_GPTMR_PWM HPM_GPTMR0 -#define BOARD_GPTMR_PWM_CHANNEL 0 -#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_0 +#define BOARD_GPTMR_PWM_CHANNEL 1 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_1 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 #define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 -#define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 2 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 /* User LED */ @@ -121,91 +134,94 @@ #define BOARD_LED_GPIO_PIN 10 #define BOARD_LED_OFF_LEVEL 1 -#define BOARD_LED_ON_LEVEL 0 +#define BOARD_LED_ON_LEVEL 0 /* 12V Power Enable*/ -#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 +#define BOARD_12V_EN_GPIO_CTRL HPM_GPIO0 #define BOARD_12V_EN_GPIO_INDEX GPIO_DI_GPIOA -#define BOARD_12V_EN_GPIO_PIN 24 +#define BOARD_12V_EN_GPIO_PIN 24 /* gpiom section */ #define BOARD_APP_GPIOM_BASE HPM_GPIOM #define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO #define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast -/* GPIO read value macro,spec for sample cherryusb on board hpm5301evklite*/ -#define BOARD_BUTTON_PRESSED_VALUE 1 - /* tinyuf2 button on hpm5301evklite*/ #define BOARD_BUTTON_TINYUF2_PIN 9 /* User button */ -#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOA -#define BOARD_APP_GPIO_PIN 3 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A +#define BOARD_APP_GPIO_PIN 3 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_A +#define BOARD_BUTTON_PRESSED_VALUE 1 /* spi section */ -#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_BASE HPM_SPI1 #define BOARD_APP_SPI_CLK_NAME clock_spi1 #define BOARD_APP_SPI_IRQ IRQn_SPI1 #define BOARD_APP_SPI_SCLK_FREQ (20000000UL) #define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) #define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) -#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX -#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX -#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 -#define BOARD_SPI_CS_PIN IOC_PAD_PA26 -#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PA26 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) /* ADC section */ -#define BOARD_APP_ADC16_NAME "ADC0" -#define BOARD_APP_ADC16_BASE HPM_ADC0 -#define BOARD_APP_ADC16_IRQn IRQn_ADC0 -#define BOARD_APP_ADC16_CH_1 (11U) -#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) - -#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (2U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* Flash section */ -#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) /* CALLBACK TIMER section */ -#define BOARD_CALLBACK_TIMER (HPM_GPTMR1) -#define BOARD_CALLBACK_TIMER_CH 0 -#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_CALLBACK_TIMER (HPM_GPTMR1) +#define BOARD_CALLBACK_TIMER_CH 0 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR1 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr1) /*Timer define*/ -#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 -#define BOARD_BLDC_TMR_CH 0 -#define BOARD_BLDC_TMR_CMP 0 -#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 -#define BOARD_BLDC_TMR_RELOAD (100000U) +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_RELOAD (100000U) /*adc*/ -#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) -#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete - -#define BOARD_BLDC_ADC_CH_U (5U) -#define BOARD_BLDC_ADC_CH_V (6U) -#define BOARD_BLDC_ADC_CH_W (4U) -#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 -#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_MODULE (ADCX_MODULE_ADC16) +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (5U) +#define BOARD_BLDC_ADC_CH_V (6U) +#define BOARD_BLDC_ADC_CH_W (4U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A -#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A - -/* USB */ -#define BOARD_USB HPM_USB0 +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) +#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_BLDC_DMA_MUX_SRC HPM_DMA_SRC_MOT_0 +#define BOARD_BLDC_DMA_CHN (0U) +#define BOARD_BLDC_DMA_TRG_DST TRGM_TRGOCFG_TRGM_DMA0 +#define BOARD_BLDC_DMA_TRG_SRC HPM_TRGM0_DMA_SRC_TRGM0 +#define BOARD_BLDC_DMA_TRG_INDEX TRGM_DMACFG_0 +#define BOARD_BLDC_DMA_TRG_CMP_INDEX (9U) +#define BOARD_BLDC_DMA_TRG_IN HPM_TRGM0_INPUT_SRC_PWM0_CH9REF #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 @@ -220,29 +236,77 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR0 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr0 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR0 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR0 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr0 +#define BOARD_THREADX_TIMER HPM_GPTMR0 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr0 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR0 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr0 + +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_I2S_SPI_CS_GPIO_PIN 31 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA31 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR1 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 1 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 3 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 0 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0 + +#define BOARD_APP_CLK_REF_PIN_NAME "J3[32] (PA09)" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ typedef void (*board_timer_cb)(void); -void board_init_console(void); void board_init_gpio_pins(void); void board_init_led_pins(void); -void board_init_usb_pins(void); +void board_init_usb(USB_Type *ptr); void board_led_write(uint8_t state); void board_led_toggle(void); +void board_init_console(void); void board_init_uart(UART_Type *ptr); uint32_t board_init_spi_clock(SPI_Type *ptr); void board_init_spi_pins(SPI_Type *ptr); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); void board_init_adc16_pins(void); +void board_init_acmp_pins(void); +void board_init_acmp_clock(ACMP_Type *ptr); void board_disable_output_rgb_led(uint8_t color); void board_enable_output_rgb_led(uint8_t color); void board_write_spi_cs(uint32_t pin, uint8_t state); @@ -251,7 +315,6 @@ void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void board_init(void); void board_init_usb_dp_dm_pins(void); void board_init_clock(void); -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); void board_delay_us(uint32_t us); void board_delay_ms(uint32_t ms); void board_timer_create(uint32_t ms, board_timer_cb cb); @@ -263,7 +326,13 @@ void board_init_pmp(void); uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void board_init_clk_ref_pin(void); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld similarity index 77% rename from bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld index f11f360946b..12af13362ed 100644 --- a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,7 +14,7 @@ MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080300, LENGTH = 128K - 768 AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K } @@ -41,22 +41,25 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -77,12 +80,12 @@ SECTIONS KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -107,12 +110,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -146,6 +143,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -158,19 +169,14 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; } > DLM /* Note: the .tbss and .tdata section should be adjacent */ @@ -178,22 +184,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -221,10 +231,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -245,6 +255,26 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM + + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; .heap(NOLOAD) : { @@ -265,7 +295,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -276,8 +307,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > DLM diff --git a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld index 196cbe56efe..26d57856025 100644 --- a/bsp/hpmicro/hpm5301evklite/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm5301evklite/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x8000; MEMORY { ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + DLM (w) : ORIGIN = 0x80300, LENGTH = 96K - 768 NONCACHEABLE_RAM (wx) : ORIGIN = 0x98000, LENGTH = NONCACHEABLE_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k } SECTIONS @@ -30,10 +30,6 @@ SECTIONS KEEP(*(.vector_table)) . = ALIGN(8); } > ILM - - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > ILM .text : { . = ALIGN(8); @@ -56,7 +52,7 @@ SECTIONS KEEP (*(.init)) KEEP (*(.fini)) . = ALIGN(8); - + /********************************************* * * RT-Thread related sections - Start @@ -92,28 +88,74 @@ SECTIONS __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); } > ILM - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - .tdata : AT(etext) { + .rel : { + KEEP(*(.rel*)) + } > DLM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > ILM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; - + *(.data) *(.data*) *(.sdata) @@ -138,10 +180,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -164,43 +206,39 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > DLM - - .rel : { - KEEP(*(.rel*)) - } > DLM - .bss(NOLOAD) : { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM + } > NONCACHEABLE_RAM - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; @@ -221,24 +259,4 @@ SECTIONS .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); } diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.c b/bsp/hpmicro/hpm5301evklite/board/pinmux.c index bc17b8750de..439a57dd452 100644 --- a/bsp/hpmicro/hpm5301evklite/board/pinmux.c +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023,2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -15,15 +15,6 @@ #include "board.h" #include "pinmux.h" -void init_xtal_pins(void) -{ - /* Package QFN32 should be set PA30 and PA31 pins as analog type to enable xtal. */ - /* - * HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - * HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - */ -} - void init_py_pins_as_pgpio(void) { /* Set PY00-PY05 default function to PGPIO */ @@ -40,10 +31,6 @@ void init_uart_pins(UART_Type *ptr) if (ptr == HPM_UART0) { HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; - } else if (ptr == HPM_UART2) { - HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_UART2_TXD; - HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_UART2_RXD; - HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_UART2_DE; } else if (ptr == HPM_UART3) { HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_UART3_TXD; HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_UART3_RXD; @@ -73,8 +60,11 @@ void init_i2c_pins(I2C_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_IOC->PAD[IOC_PAD_PB08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PB09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - } else { - ; + } else if (ptr == HPM_I2C3) { + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_I2C3_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_I2C3_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); } } @@ -96,6 +86,12 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -106,13 +102,26 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_SPI1_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PA29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } void init_gptmr_pins(GPTMR_Type *ptr) { - (void) ptr; + if (ptr == HPM_GPTMR0) { + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPTMR0_COMP_2; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + } else if (ptr == HPM_GPTMR1) { + HPM_IOC->PAD[IOC_PAD_PA02].FUNC_CTL = IOC_PA02_FUNC_CTL_GPTMR1_COMP_1; + } } void init_butn_pins(void) @@ -152,22 +161,24 @@ void init_adc_bldc_pins(void) HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IV: ADC0.6 /ADC1.6 */ } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - - /* USB0_ID */ - HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; - /* USB0_OC */ - HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; - /* USB0_PWR */ - HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; - - /* PY port IO needs to configure PIOC as well */ - HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; - HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; - HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; + if (ptr == HPM_USB0) { + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_USB0_PWR; + + /* PY port IO needs to configure PIOC as well */ + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02; + } } void init_led_pins_as_gpio(void) @@ -175,3 +186,43 @@ void init_led_pins_as_gpio(void) HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10; } +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA26].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPIO_A_26; +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR0) { + if (as_comp) { + switch (channel) { + case 1: + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_GPTMR0_COMP_1; + break; + case 2: + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_GPTMR0_COMP_2; + break; + case 3: + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_GPTMR0_COMP_3; + break; + default: + break; + } + } else { + if (channel == 1) { + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1; + } + } + } else if (ptr == HPM_GPTMR1) { + if ((as_comp == true) && (channel == 3)) { + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPTMR1_COMP_3; + } + } +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_SOC_REF0; +} diff --git a/bsp/hpmicro/hpm5301evklite/board/pinmux.h b/bsp/hpmicro/hpm5301evklite/board/pinmux.h index 4e5f2e53040..3e37d1bf1bc 100644 --- a/bsp/hpmicro/hpm5301evklite/board/pinmux.h +++ b/bsp/hpmicro/hpm5301evklite/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023,2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,9 +11,9 @@ #ifdef __cplusplus extern "C" { #endif -void init_xtal_pins(void); void init_py_pins_as_pgpio(void); void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); @@ -23,8 +23,12 @@ void init_butn_pins(void); void init_acmp_pins(void); void init_adc_pins(void); void init_adc_bldc_pins(void); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_led_pins_as_gpio(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pin(void); + #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c index 1ac0279b9e7..3c1ef45f2b5 100644 --- a/bsp/hpmicro/hpm5301evklite/board/rtt_board.c +++ b/bsp/hpmicro/hpm5301evklite/board/rtt_board.c @@ -52,7 +52,7 @@ void rtt_board_init(void) os_tick_config(); /* Configure the USB pins*/ - board_init_usb_pins(); + board_init_usb(HPM_USB0); /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ rt_hw_uart_init(); @@ -63,6 +63,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); } @@ -96,7 +97,7 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); + board_init_usb(HPM_USB0); } ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) @@ -108,7 +109,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->SOFTWARE_RESET = 1000U; while(1) { @@ -117,3 +118,39 @@ void rt_hw_cpu_reset(void) } MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk2, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } + + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif diff --git a/bsp/hpmicro/hpm5301evklite/board/rtt_board.h b/bsp/hpmicro/hpm5301evklite/board/rtt_board.h index 9bb7db4b652..c7e3db8e1ac 100644 --- a/bsp/hpmicro/hpm5301evklite/board/rtt_board.h +++ b/bsp/hpmicro/hpm5301evklite/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,8 +10,10 @@ #include "hpm_common.h" #include "hpm_soc.h" #include +#include "board.h" /* gpio section */ +#define APP_LED0 (0U) #define APP_LED0_PIN_NUM GET_PIN(A, 10) #define APP_LED_ON (1) #define APP_LED_OFF (0) @@ -21,13 +23,23 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* CAN section */ #define BOARD_CAN_NAME "can0" #define BOARD_CAN_HWFILTER_INDEX (0U) /* UART section */ -#define BOARD_UART_NAME "uart2" -#define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE +#define BOARD_UART_NAME "uart3" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART3_RX_BUFSIZE + +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 #define IRQn_PendSV IRQn_DEBUG0 diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.h b/bsp/hpmicro/hpm5301evklite/rtconfig.h index b9bbf3995a2..cefa30ff7a7 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.h +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -76,6 +76,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -104,6 +105,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -300,6 +303,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -379,18 +396,21 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM5300_SERIES /* Hardware Drivers Config */ -#define SOC_HPM5000 +#define SOC_HPM5300 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_UART0_RX_BUFSIZE 128 #define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm5301evklite/rtconfig.py b/bsp/hpmicro/hpm5301evklite/rtconfig.py index 7dfd2e32bb0..97ab4bb71eb 100644 --- a/bsp/hpmicro/hpm5301evklite/rtconfig.py +++ b/bsp/hpmicro/hpm5301evklite/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c index b0bab335d52..36ec0334321 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/startup.c @@ -4,125 +4,132 @@ * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt - */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm5301evklite/startup/HPM5301/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm5e00evk/.config b/bsp/hpmicro/hpm5e00evk/.config new file mode 100644 index 00000000000..7d72b717728 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/.config @@ -0,0 +1,1434 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +# CONFIG_RT_USING_DEBUG is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +CONFIG_RT_USING_LEGACY=y +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_HPM5E00_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM5E00=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_PWMV2 is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/hpmicro/hpm5e00evk/.cproject b/bsp/hpmicro/hpm5e00evk/.cproject new file mode 100644 index 00000000000..eafefd8ef55 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/.cproject @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm5e00evk/.project b/bsp/hpmicro/hpm5e00evk/.project new file mode 100644 index 00000000000..0d08d5512da --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/.project @@ -0,0 +1,27 @@ + + + blink_led + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bsp/hpmicro/hpm5e00evk/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm5e00evk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000000..9f1acfcfba2 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini b/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini new file mode 100644 index 00000000000..421ec3853ee --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +# Fri Apr 25 13:53:29 2025 +cfg_version=v3.0 + +board_name= +bsp_version= +bsp_path= +chip_name= +project_base_rtt_bsp=true +is_use_scons_build=true +hardware_adapter= +selected_rtt_version=latest +board_base_nano_proj=false +is_base_example_project=false +example_name= +project_type=rt-thread +os_branch=master +os_version=latest +project_name=blink_led +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/Kconfig b/bsp/hpmicro/hpm5e00evk/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hpmicro/hpm5e00evk/README.md b/bsp/hpmicro/hpm5e00evk/README.md new file mode 100644 index 00000000000..1852f9e539d --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/README.md @@ -0,0 +1,114 @@ +# HPMicro HPM5E00EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM5E00EVK development board. + +The document consists of the following parts: + +- HPM5E00EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM5E00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, motor control，etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5E00EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm5e00evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/README_zh.md b/bsp/hpmicro/hpm5e00evk/README_zh.md new file mode 100644 index 00000000000..c22d6f2c068 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/README_zh.md @@ -0,0 +1,113 @@ +# 先楫 HPM5E00EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM5E00EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM5E00EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM5E00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm5e00.cfg -f boards\debug_scripts\boards\hpm5e00evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM5E00EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm5e00evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/SConscript b/bsp/hpmicro/hpm5e00evk/SConscript new file mode 100644 index 00000000000..014c428d0a3 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm5e00evk/SConstruct b/bsp/hpmicro/hpm5e00evk/SConstruct new file mode 100644 index 00000000000..a4d1f600062 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/SConstruct @@ -0,0 +1,65 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + + + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm5e00evk/applications/SConscript b/bsp/hpmicro/hpm5e00evk/applications/SConscript new file mode 100644 index 00000000000..a65aa4d8553 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5e00evk/applications/main.c b/bsp/hpmicro/hpm5e00evk/applications/main.c new file mode 100644 index 00000000000..a5a7f07c737 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/applications/main.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + +int main(void) +{ + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm5e00evk/board/Kconfig b/bsp/hpmicro/hpm5e00evk/board/Kconfig new file mode 100644 index 00000000000..6e8a2b2341d --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/Kconfig @@ -0,0 +1,606 @@ +menu "Hardware Drivers Config" + +config SOC_HPM5E00 + bool + select SOC_HPM5E00_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BSP_USING_ENET_PHY_RTL8211 + bool + default n + +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice + endif + endif + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + + if BSP_USING_ETH + choice + prompt "ETH" + default BSP_USING_ETH0 + + config BSP_USING_ETH0 + bool "Enable ETH0" + select BSP_USING_ENET_PHY_RTL8211 + endchoice + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + select RT_USING_CACHE + default n + config BSP_USING_USB_HOST + bool "Enable USB Host" + select RT_USING_CACHE + default n + endif + + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_PWMV2 + bool "Enable PWM" + default n + select RT_USING_PWM if BSP_USING_PWMV2 + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + if BSP_USING_MCAN1 + config BSP_MCAN1_IRQ_PRIORITY + int "MCAN1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + if BSP_USING_MCAN2 + config BSP_MCAN2_IRQ_PRIORITY + int "MCAN2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + if BSP_USING_MCAN3 + config BSP_MCAN3_IRQ_PRIORITY + int "MCAN3 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + endif + +endmenu + + + + +endmenu + diff --git a/bsp/hpmicro/hpm5e00evk/board/SConscript b/bsp/hpmicro/hpm5e00evk/board/SConscript new file mode 100644 index 00000000000..57460d8a1ee --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/SConscript @@ -0,0 +1,18 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM5E31'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5e00evk/board/board.c b/bsp/hpmicro/hpm5e00evk/board/board.c new file mode 100644 index 00000000000..14b9f61a8c8 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/board.c @@ -0,0 +1,716 @@ +/* + * Copyright (c) 2023-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "hpm_clock_drv.h" +/* #include "hpm_sysctl_drv.h" */ +#include "hpm_pllctlv2_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_pcfg_drv.h" + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 111MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90002, 0x00000005, 0x1000, 0x0 }; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb0)); + printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif)); + printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis)); + printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic)); + printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_print_banner(void) +{ + const uint8_t banner[] = { "\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n" }; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} +#endif + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2c_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + + freq = board_init_i2c_clock(ptr); + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } else if (ptr == HPM_SPI3) { + clock_add_to_group(clock_spi3, 0); + return clock_get_frequency(clock_spi3); + } else { + ; + } + return 0; +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); + + /* Key A*/ + gpio_set_pin_input(BOARD_APP_GPIO_CTRL, BOARD_APP_GPIO_INDEX, BOARD_APP_GPIO_PIN); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +void board_init_led_pins(void) +{ + init_led_pins(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_pmp(void) +{ + pmp_entry_t pmp_entry[16]; + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + volatile uint32_t axi_sram_start = 0x01200000; /* AXI SRAM start */ + volatile uint32_t axi_sram_end = 0x01240000; /* AXI SRAM end */ + uint32_t start_addr, end_addr, length; + uint8_t index = 0; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + if ((start_addr >= axi_sram_start) && (end_addr <= axi_sram_end)) { + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } + pmp_config(&pmp_entry[0], index); + } +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32ul * 1000ul * 9u); + + /* select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + /* Add Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_ahb0, 0); + clock_add_to_group(clock_axif, 0); + clock_add_to_group(clock_axis, 0); + clock_add_to_group(clock_axic, 0); + clock_add_to_group(clock_rom0, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_ptpc, 0); + /* Motor Related */ + clock_add_to_group(clock_qei0, 0); + clock_add_to_group(clock_plb0, 0); + clock_add_to_group(clock_qei1, 0); + clock_add_to_group(clock_qeo0, 0); + clock_add_to_group(clock_qeo1, 0); + clock_add_to_group(clock_pwm0, 0); + clock_add_to_group(clock_pwm1, 0); + clock_add_to_group(clock_emds, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); + + /* Configure PLL0 Post Divider */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0); /* PLL0CLK0: 480MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk1, pllctlv2_div_1p2); /* PLL0CLK1: 400MHz */ + /* Configure PLL0 Frequency to 480MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, BOARD_CPU_FREQ); + /* CPU clock use clk_src_pll0_clk0 */ + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_update_core_clock(); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART4) { + clock_add_to_group(clock_uart4, 0); + freq = clock_get_frequency(clock_uart4); + } else { + /* Not supported */ + } + return freq; +} + +void board_init_usb(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + + /* As LQFP100 has no vbus pin, so should be call usb_phy_using_internal_vbus() API to use internal vbus. */ + /* usb_phy_using_internal_vbus(ptr); */ + } +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) /* motor system should be use clk_adc_src_ahb0 */ +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + clock_add_to_group(clock_adc0, 0); + if (clk_src_bus) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + clock_add_to_group(clock_adc1, 0); + if (clk_src_bus) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + } + freq = clock_get_frequency(clock_adc1); + } else { + ; + } + + return freq; +} + +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_MCAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_add_to_group(clock_can1, 0); + clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_MCAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_add_to_group(clock_can2, 0); + clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_MCAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_add_to_group(clock_can3, 0); + clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, 0); + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ + /* clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); */ /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET0) { + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + (void) ptr; + return enet_pbl_32; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, 0); + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll2, pllctlv2_clk1, pllctlv2_div_4p0); + /* set eth clock frequency at 50MHz for enet0 */ + /* clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); */ + } else { + return status_fail; + } + } + } else { + return status_invalid_argument; + } + + enet_rmii_enable_clock(ptr, internal); /* defined in hpm_enet_soc_drv.h, not sure */ + + return status_success; +} + +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); /* defined in hpm_enet_soc_drv.h, not sure */ + } + + return status_invalid_argument; +} + +void board_init_owr_pins(OWR_Type *ptr) +{ + init_owr_pins(ptr); +} + +void board_init_ethercat(ESC_Type *ptr) +{ + (void)ptr; + + clock_add_to_group(clock_esc0, 0); + + init_esc_pins(); + /* PHY reset pin */ + gpio_set_pin_output_with_initial(HPM_GPIO0, BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY0_RESET_PIN_INDEX, 0); +#if BOARD_ECAT_SUPPORT_PORT1 + gpio_set_pin_output_with_initial(HPM_GPIO0, BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY1_RESET_PIN_INDEX, 0); +#endif +#if BOARD_ECAT_SUPPORT_PORT2 + gpio_set_pin_output_with_initial(HPM_GPIO0, BOARD_ECAT_PHY2_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY2_RESET_PIN_INDEX, 0); +#endif +} + +/* switch and led pin for ethercat io test */ +void board_init_switch_led(void) +{ + init_esc_in_out_pin(); + + gpio_set_pin_input(BOARD_ECAT_IN1_GPIO, BOARD_ECAT_IN1_GPIO_PORT_INDEX, BOARD_ECAT_IN1_GPIO_PIN_INDEX); + gpio_set_pin_input(BOARD_ECAT_IN2_GPIO, BOARD_ECAT_IN2_GPIO_PORT_INDEX, BOARD_ECAT_IN2_GPIO_PIN_INDEX); + + gpio_set_pin_output_with_initial(BOARD_ECAT_OUT1_GPIO, BOARD_ECAT_OUT1_GPIO_PORT_INDEX, BOARD_ECAT_OUT1_GPIO_PIN_INDEX, 0); + gpio_set_pin_output_with_initial(BOARD_ECAT_OUT2_GPIO, BOARD_ECAT_OUT2_GPIO_PORT_INDEX, BOARD_ECAT_OUT2_GPIO_PIN_INDEX, 0); +} + + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_owr_clock(OWR_Type *ptr) +{ + (void) ptr; + + clock_add_to_group(BOARD_OWR_CLK_NAME, 0); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pins(); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} + diff --git a/bsp/hpmicro/hpm5e00evk/board/board.h b/bsp/hpmicro/hpm5e00evk/board/board.h new file mode 100644 index 00000000000..b34b6cc3b5b --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/board.h @@ -0,0 +1,662 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "pinmux.h" +#include "hpm_trgm_drv.h" +#include "hpm_gptmr_drv.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm5e00evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) +#define BOARD_CPU_FREQ (480000000UL) + +#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP0 +#define BOARD_ACMP_CLK clock_acmp0 +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 +#define BOARD_ACMP_IRQ IRQn_ACMP0_1 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ + +/* uart section */ +#define BOARD_APP_UART_BASE HPM_UART4 +#define BOARD_APP_UART_IRQ IRQn_UART4 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart4 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART4_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART4_TX + +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PD13 + +/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */ +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr3 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR3 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr3 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR3 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC +#define BOARD_UART_LIN_TX_PIN (16U) /* PC16 should align with used pin in pinmux configuration */ +#define BOARD_UART_LIN_PLB_TRGM_IN_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P05 /* align with used pin in pinmux configuration */ + +/* plb lin baudrate detection */ +#define BOARD_PLB_TRGM_FILTER_GPIO_INPUT0 HPM_TRGM0_FILTER_SRC_TRGM0_P00 +#define BOARD_PLB_TRGM_DMA_REQ0 HPM_TRGM0_DMA_SRC_TRGM_0 + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#else +#define BOARD_CONSOLE_UART_BASE HPM_UART11 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart11 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART11 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART11_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART11_RX +#endif +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +#define BOARD_FEMC_ASYNC_SRAM_CS_INDEX 0 +#define BOARD_FEMC_ASYNC_SRAM_AD_MUX_MODE false +#define BOARD_FEMC_ASYNC_SRAM_SIZE (128 * SIZE_1KB) + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (1 * SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C0 +#define BOARD_APP_I2C_IRQ IRQn_I2C0 +#define BOARD_APP_I2C_CLK_NAME clock_i2c0 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM0 +#define BOARD_APP_PWM_CLOCK_NAME clock_pwm0 +#define BOARD_APP_PWM_OUT1 pwm_channel_0 +#define BOARD_APP_PWM_OUT2 pwm_channel_1 +#define BOARD_APP_PWM_OUT3 pwm_channel_2 +#define BOARD_APP_PWM_OUT4 pwm_channel_3 +#define BOARD_APP_PWM_OUT5 pwm_channel_4 +#define BOARD_APP_PWM_OUT6 pwm_channel_5 +#define BOARD_APP_PWM_FAULT_PIN (5) +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM0 +#define BOARD_APP_TRGM_PWM_OUTPUT HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN_0 +#define BOARD_APP_TRGM_PWM_OUTPUT1 HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN_1 +#define BOARD_APP_TRGM_PWM_OUTPUT2 HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN_2 +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR0 +#define BOARD_GPTMR_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_CHANNEL 2 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR0_2 +#define BOARD_GPTMR_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM HPM_GPTMR0 +#define BOARD_GPTMR_PWM_CHANNEL 2 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR0_2 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_QEI HPM_GPTMR1 +#define BOARD_GPTMR_QEI_CLK_NAME clock_gptmr1 +#define BOARD_GPTMR_QEI_CH_GROUP gptmr_qei_ch_group_23 +#define BOARD_GPTMR_QEI_PHMAX 4000 + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOC +#define BOARD_APP_GPIO_PIN 21 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_C +#define BOARD_BUTTON_PRESSED_VALUE 0 + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI1 +#define BOARD_APP_SPI_CLK_NAME clock_spi1 +#define BOARD_APP_SPI_IRQ IRQn_SPI1 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI1_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI1_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PC11 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000006U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC0" +#define BOARD_APP_ADC16_BASE HPM_ADC0 +#define BOARD_APP_ADC16_IRQn IRQn_ADC0 +#define BOARD_APP_ADC16_CH_1 (1U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN1 +#define BOARD_APP_CAN_IRQn IRQn_MCAN1 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR3) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr3) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR3) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) + +/* LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOC +#define BOARD_LED_GPIO_PIN 28 +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL 1 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* enet section */ +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_ENET_RGMII_RST_GPIO_PIN (19U) + +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (0U) + +#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RGMII_PPS0_PINOUT (0) + +/* MOTOR */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/*BLDC PWM */ +#define BOARD_BLDCPWM HPM_PWM0 +#define BOARD_BLDC_UH_PWM_OUTPIN (0U) +#define BOARD_BLDC_UL_PWM_OUTPIN (1U) +#define BOARD_BLDC_VH_PWM_OUTPIN (2U) +#define BOARD_BLDC_VL_PWM_OUTPIN (3U) +#define BOARD_BLDC_WH_PWM_OUTPIN (4U) +#define BOARD_BLDC_WL_PWM_OUTPIN (5U) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM0 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (20U) + +/* BLDC ADC */ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (5U) +#define BOARD_BLDC_ADC_CH_V (4U) +#define BOARD_BLDC_ADC_CH_W (6U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_OUT_CHN (0U) + +/* BLDC TRGM */ +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 +#define BOARD_BLDC_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A + +/* BLDC TIMER */ +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_BASE HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) + +/* QEIV2 */ +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEIV2_BASE HPM_QEI0 +#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_qei0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +#define BOARD_APP_QEIV2_BASE HPM_QEI0 +#define BOARD_APP_QEIV2_IRQ IRQn_QEI0 +#define BOARD_APP_QEI_CLOCK_SOURCE clock_qei0 +#define BOARD_APP_QEI_ADC_COS_BASE HPM_ADC0 +#define BOARD_APP_QEI_ADC_COS_CHN (6U) +#define BOARD_APP_QEI_ADC_SIN_BASE HPM_ADC1 +#define BOARD_APP_QEI_ADC_SIN_CHN (5U) +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_qei0_adc0 +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei0_adc1 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc0 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc1 +#define BOARD_APP_QEI_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A + +/* PLB */ +#define BOARD_PLB_CLOCK_NAME clock_plb0 + +#define BOARD_PLB_COUNTER HPM_PLB +#define BOARD_PLB_PWM_BASE HPM_PWM0 +#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLB_TRGM HPM_TRGM0 +#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0) +#define BOARD_PLB_IN_PWM_TRG (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT32) +#define BOARD_PLB_TYPEB_INPUT0 (TRGM_TRGOCFG_PLB_IN_32) +#define BOARD_PLB_TO_TRG_IN (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_TRG_OUT (HPM_TRGM0_OUTPUT_SRC_TRGM0_P05) +#define BOARD_PLB_IO_TRG_SHIFT (5) +#define BOARD_PLB_PWM_CMP (8U) +#define BOARD_PLB_PWM_CHN (8U) +#define BOARD_PLB_CHN plb_chn0 + +#define BOARD_PLB_PHASE_COUNT_DEFAULT (4000) +#define BOARD_PLB_FILTER_LENGTH_DEFAULT (100) +#define BOARD_PLB_QEI_A_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P07 +#define BOARD_PLB_QEI_B_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P06 +#define BOARD_PLB_QEI_Z_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P05 + +#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P02 +#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_TRGM0_P04 +#define BOARD_PLB_FILTER_IO_TRG_SHIFT (4) + +/* QEO ABZ */ +#define BOARD_QEO HPM_QEO1 +#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo1 +#define BOARD_QEO_TRGM_POS_IN trgm_pos_matrix_in_from_qei0 +/* QEO PWM */ +#define BOARD_QEO_PWM HPM_QEO0 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */ +#define BOARD_QEO_TRGM_POS_PWM trgm_pos_matrix_output_to_qeo0 +#define BOARD_QEO_PWM_TRGM_POS_IN trgm_pos_matrix_in_from_qei0 +#define BOARD_QEO_PWM_SAFETY_TRGM HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN_1 + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR1 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 + +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 +#define BOARD_FREERTOS_TICK_SRC_PWM_COUNTER pwm_counter_0 +#define BOARD_FREERTOS_TICK_SRC_PWM_SHADOW PWMV2_SHADOW_INDEX(0) + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR1 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR1 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr1 + +/* EtherCAT definitions */ +/* ECAT PORT0 must support */ +#define BOARD_ECAT_SUPPORT_PORT1 (1) +#define BOARD_ECAT_SUPPORT_PORT2 (1) /* require expansion board */ + +#define BOARD_ECAT_SUPPORT_RUN_ERROR_LED (0) /* board not supports RUN/ERROR led */ + +/* invert esc port link signal, require low level for linkup */ +#define BOARD_ECAT_PORT0_LINK_INVERT true /* depend on hardware */ +#define BOARD_ECAT_PORT1_LINK_INVERT false /* depend on hardware */ +#define BOARD_ECAT_PORT2_LINK_INVERT false /* depend on hardware */ + +#define BOARD_ECAT_PHY0_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOB +#define BOARD_ECAT_PHY0_RESET_PIN_INDEX (24) + +#define BOARD_ECAT_PHY1_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOB +#define BOARD_ECAT_PHY1_RESET_PIN_INDEX (24) + +#define BOARD_ECAT_PHY2_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY2_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOB +#define BOARD_ECAT_PHY2_RESET_PIN_INDEX (24) +#define BOARD_ECAT_PHY_RESET_LEVEL (0) + +#define BOARD_ECAT_IN1_GPIO HPM_GPIO0 +#define BOARD_ECAT_IN1_GPIO_PORT_INDEX GPIO_DO_GPIOD +#define BOARD_ECAT_IN1_GPIO_PIN_INDEX (6U) + +#define BOARD_ECAT_IN2_GPIO HPM_GPIO0 +#define BOARD_ECAT_IN2_GPIO_PORT_INDEX GPIO_DO_GPIOD +#define BOARD_ECAT_IN2_GPIO_PIN_INDEX (12U) + +#define BOARD_ECAT_OUT1_GPIO HPM_GPIO0 +#define BOARD_ECAT_OUT1_GPIO_PORT_INDEX GPIO_DO_GPIOC +#define BOARD_ECAT_OUT1_GPIO_PIN_INDEX (24U) + +#define BOARD_ECAT_OUT2_GPIO HPM_GPIO0 +#define BOARD_ECAT_OUT2_GPIO_PORT_INDEX GPIO_DO_GPIOC +#define BOARD_ECAT_OUT2_GPIO_PIN_INDEX (23) + +#define BOARD_ECAT_OUT_ON_LEVEL (1) + +#define BOARD_ECAT_NMII_LINK0_CTRL_INDEX 2 +#define BOARD_ECAT_NMII_LINK1_CTRL_INDEX 5 +#define BOARD_ECAT_NMII_LINK2_CTRL_INDEX 6 + +/* ECAT PHY address definition */ +#define BOARD_ECAT_PHY_ADDR_OFFSET (1U) +#define BOARD_ECAT_PORT0_PHY_ADDR (0U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT0_PHY_ADDR */ +#define BOARD_ECAT_PORT1_PHY_ADDR (1U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT1_PHY_ADDR */ +#define BOARD_ECAT_PORT2_PHY_ADDR (2U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT2_PHY_ADDR */ + +/* the address of ecat flash emulate eeprom component in flash */ +#define BOARD_ECAT_FLASH_EMULATE_EEPROM_ADDR (0x80000) /* offset 512K */ + +/* sdm section */ +#define BOARD_SDM HPM_SDM0 +#define BOARD_SDM_IRQ IRQn_SDM0 +#define BOARD_SDM_CHANNEL 0 +#define BOARD_SDM_TRGM HPM_TRGM0 +#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CLK clock_gptmr3 +#define BOARD_SDM_TRGM_GPTMR_CH 2 +#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 +#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM0_OUTPUT_SRC_SDM0_PWM_SOC15 +#define BOARD_SDM_TRGM_SYNC_SRC (15) +/* need to provide clock to sdm sensor */ +#define BOARD_SDM_SENSOR_REQUIRE_CLK true +#define BOARD_SDM_CLK_PWM HPM_PWM1 +#define BOARD_SDM_CLK_PWM_CLK_NAME clock_pwm1 +#define BOARD_SDM_CLK_PWM_OUT (7) + +/* LOBS */ +#define BOARD_LOBS_TRIG_GROUP lobs_signal_group_PC +#define BOARD_LOBS_TRIG_PIN_0 11 +#define BOARD_LOBS_TRIG_PIN_1 10 + +/* PPI */ +#define BOARD_PPI_ASYNC_SRAM_AD_MUX_MODE true +#define BOARD_PPI_ASYNC_SRAM_CS_INDEX 0 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ0_7 ppi_dq_pins_16_23 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ8_15 ppi_dq_pins_24_31 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ16_23 ppi_dq_pins_0_7 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ24_31 ppi_dq_pins_8_15 +#define BOARD_PPI_ASYNC_SRAM_ADV_CTRL_PIN 0 +#define BOARD_PPI_ASYNC_SRAM_WE_CTRL_PIN 1 +#define BOARD_PPI_ASYNC_SRAM_OE_CTRL_PIN 3 +#define BOARD_PPI_ASYNC_SRAM_SIZE (256 * SIZE_1KB) + +#define BOARD_PPI_ADC_CS_INDEX 1 + +/* EUI */ +#define BOARD_EUI HPM_EUI1 +#define BOARD_EUI_IRQ IRQn_EUI1 +#define BOARD_EUI_CLOCK_NAME clock_eui1 +#define BOARD_EUI_DEDICATE_OUT_LINES eui_dedicate_output_3_lines +#define BOARD_EUI_ESC_KEY_ROW 0 +#define BOARD_EUI_ESC_KEY_COL 0 +#define BOARD_EUI_UP_KEY_ROW 0 +#define BOARD_EUI_UP_KEY_COL 1 +#define BOARD_EUI_ENTER_KEY_ROW 0 +#define BOARD_EUI_ENTER_KEY_COL 2 +#define BOARD_EUI_LEFT_KEY_ROW 1 +#define BOARD_EUI_LEFT_KEY_COL 0 +#define BOARD_EUI_DOWN_KEY_ROW 1 +#define BOARD_EUI_DOWN_KEY_COL 1 +#define BOARD_EUI_RIGHT_KEY_ROW 1 +#define BOARD_EUI_RIGHT_KEY_COL 2 + +/* Bit0-seg A, Bit1-seg B , Bit2-seg C, Bit3-seg D, Bit4-seg E , Bit5-seg F, Bit6-seg G, Bit7-seg DP */ +/* Code Data: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, b, C, d, E, F */ +#define BOARD_EUI_SEG_ENCODE_DATA { 0x3f, 0x06, 0x5b, 0x4f, 0x66, 0x6d, 0x7d, 0x07, 0x7f, 0x6f, 0x77, 0x7c, 0x39, 0x5e, 0x79, 0x71 } +#define BOARD_EUI_SEG_DP_BIT_MASK BIT7_MASK + +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOD +#define BOARD_I2S_SPI_CS_GPIO_PIN 24 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PD24 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR1 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 3 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 3 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0 + +#define BOARD_OWR HPM_OWR0 +#define BOARD_OWR_CLK_NAME clock_owire0 +#define BOARD_OWR_CLK clock_get_frequency(BOARD_OWR_CLK_NAME); + +#define BOARD_APP_CLK_REF_PIN_NAME "P5[22] (PC30)" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref1 + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_can(MCAN_Type *ptr); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +uint8_t board_get_led_gpio_off_level(void); +void board_init_led_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); +void board_init_owr_pins(OWR_Type *ptr); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); +uint32_t board_init_femc_clock(void); +uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); +void board_init_acmp_clock(ACMP_Type *ptr); +void board_init_owr_clock(OWR_Type *ptr); +void board_init_adc16_pins(void); +void board_init_acmp_pins(void); +void board_init_usb(USB_Type *ptr); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); + +void board_init_ethercat(ESC_Type *ptr); + +void board_init_switch_led(void); +void board_init_adc_qeiv2_pins(void); +void init_pwm_fault_pins(void); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void board_init_clk_ref_pin(void); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg new file mode 100644 index 00000000000..e3c75108fc8 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/boards/hpm5e00evk.cfg @@ -0,0 +1,89 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 + +# xpi0_hybrid configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0xB0000000 +# - flash size: 0x2000000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0_hybrid hpm_xpi 0xB0000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 00000000000..b9ae1121044 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 00000000000..580d98ef853 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 00000000000..4fb0fba2e70 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 00000000000..fd8f04428c9 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 00000000000..e9d6e6d6984 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg new file mode 100644 index 00000000000..2f4045a4062 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/debug_scripts/openocd/soc/hpm5e00.cfg @@ -0,0 +1,18 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm5e00 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +proc reset_soc {} { + $::_TARGET0 riscv dmi_write 0x39 0xF410001C + $::_TARGET0 riscv dmi_write 0x3C 24000000 +} diff --git a/bsp/hpmicro/hpm5e00evk/board/fal_cfg.h b/bsp/hpmicro/hpm5e00evk/board/fal_cfg.h new file mode 100644 index 00000000000..c79baa66c2f --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/fal_cfg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm5e00evk/board/fal_flash_port.c b/bsp/hpmicro/hpm5e00evk/board/fal_flash_port.c new file mode 100644 index 00000000000..7be597c903f --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, rt_uint8_t *buf, rt_size_t size); +static int write(long offset, const rt_uint8_t *buf, rt_size_t size); +static int erase(long offset, rt_size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + rt_uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + rt_uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, rt_uint8_t *buf, rt_size_t size) +{ + rt_uint32_t flash_addr = nor_flash0.addr + offset; + rt_uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + rt_uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + rt_uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const rt_uint32_t *buf, rt_size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const rt_uint8_t *buf, rt_size_t size) +{ + rt_uint32_t *src = NULL; + rt_uint32_t buf_32[64]; + rt_uint32_t write_size; + rt_size_t remaining_size = size; + int ret = (int)size; + + rt_uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + rt_uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + rt_uint32_t write_size_in_page = page_size - offset_in_page; + rt_uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, rt_size_t size) +{ + rt_uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + rt_uint32_t block_size; + rt_uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + rt_uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c similarity index 98% rename from bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c rename to bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c index 25493d1289d..bbb1b25beb4 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.c +++ b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.c @@ -7,6 +7,7 @@ * */ +#include #include "hpm_wm8960.h" #ifndef HPM_WM8960_MCLK_TOLERANCE @@ -491,16 +492,20 @@ hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32 hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) { - uint8_t buff[2]; /* The first 7 bits (B15 to B9) are address bits that select which control register */ /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ - buff[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); - buff[1] = (uint8_t)(val & 0xFFU); + rt_size_t size; + rt_uint8_t data[2]; + data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); + data[1] = (uint8_t)(val & 0xFFU); - /* record reg val */ - wm8960_reg_val[reg] = val; + size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U); + if (size != 2) { + return status_fail; + } - return i2c_master_write(control->ptr, control->slave_address, buff, 2U); + wm8960_reg_val[reg] = val; + return status_success; } hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h similarity index 96% rename from bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h rename to bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h index 6b85407368c..a163a52390a 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960.h +++ b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960.h @@ -7,11 +7,15 @@ * */ -#ifndef _HPM_SGTL5000_H_ -#define _HPM_SGTL5000_H_ - -#include "hpm_i2c_drv.h" -#include "hpm_common.h" +#ifndef _HPM_WM8960_H_ +#define _HPM_WM8960_H_ + +//#include "hpm_i2c_drv.h" +//#include "hpm_common.h" +#include +#include +#include "rtt_board.h" +#include "drivers/dev_i2c.h" #include "hpm_wm8960_regs.h" #define WM8960_I2C_ADDR 0x1A @@ -81,7 +85,7 @@ typedef struct wm8960_config { } wm8960_config_t; typedef struct { - I2C_Type *ptr; /* I2C bus */ + struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ uint8_t slave_address; /* code device address */ } wm8960_control_t; @@ -220,4 +224,4 @@ hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); -#endif /* _HPM_SGTL5000_H_ */ +#endif /* _HPM_WM8960_H_ */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960_regs.h b/bsp/hpmicro/hpm5e00evk/board/hpm_wm8960_regs.h similarity index 100% rename from bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8960/hpm_wm8960_regs.h rename to bsp/hpmicro/hpm5e00evk/board/hpm_wm8960_regs.h diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld similarity index 68% rename from bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_xip.ld rename to bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld index 697fcfc26c9..6fba8803610 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_xip.ld +++ b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_hybrid_rtt.ld @@ -1,33 +1,33 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 64K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; MEMORY { - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K + FLASH (rx) : ORIGIN = 0xB0000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k } -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__nor_cfg_option_load_addr__ = ORIGIN(FLASH) + 0x400; +__boot_header_load_addr__ = ORIGIN(FLASH) + 0x1000; +__app_load_addr__ = ORIGIN(FLASH) + 0x3000; __boot_header_length__ = __boot_header_end__ - __boot_header_start__; __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - SECTIONS { .nor_cfg_option __nor_cfg_option_load_addr__ : { KEEP(*(.nor_cfg_option)) - } > XPI0 + } > FLASH .boot_header __boot_header_load_addr__ : { __boot_header_start__ = .; @@ -35,27 +35,42 @@ SECTIONS KEEP(*(.fw_info_table)) KEEP(*(.dc_info)) __boot_header_end__ = .; - } > XPI0 + } > FLASH .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) - } > XPI0 + . = ALIGN(16); + } > FLASH __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); + + . = ALIGN(16); __vector_ram_end__ = .; } > ILM + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -68,16 +83,18 @@ SECTIONS *(.gnu*) *(.pl*) + KEEP(*(.eh_frame)) + *(.eh_frame*) + KEEP (*(.init)) KEEP (*(.fini)) - - /* section information for usbh class */ . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - /* RT-Thread related sections - Start */ + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -102,33 +119,90 @@ SECTIONS __rtmsymtab_end = .; /* RT-Thread related sections - end */ + + /* section information for usbh class */ . = ALIGN(8); - } > XPI0 + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > FLASH .eh_frame : { __eh_frame_start = .; KEEP(*(.eh_frame)) __eh_frame_end = .; - } > XPI0 + } > FLASH .eh_frame_hdr : { KEEP(*(.eh_frame_hdr)) - } > XPI0 + } > FLASH __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - .rel : { KEEP(*(.rel*)) - } > XPI0 + } > FLASH PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - __data_load_addr__ = etext; + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > ILM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > ILM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > ILM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > ILM + + __data_load_addr__ = etext + SIZEOF(.tdata); .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; @@ -157,16 +231,18 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); + PROVIDE(__ctors_start__ = .); KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.*))) KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); . = ALIGN(8); KEEP(*crtbegin*.o(.dtors)) @@ -178,119 +254,59 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > DLM + } > ILM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > DLM - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { + .framebuffer (NOLOAD) : { . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) + KEEP(*(.framebuffer)) . = ALIGN(8); - PROVIDE(__tdata_end__ = .); } > DLM - .tbss (NOLOAD) : { + .stack(NOLOAD) : { . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) + __stack_base__ = .; + . += STACK_SIZE; . = ALIGN(8); - PROVIDE(__tbss_end__ = .); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); } > DLM - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); + __noncacheable_start__ = .; __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) __noncacheable_init_end__ = .; . = ALIGN(8); } > DLM - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; + __noncacheable_end__ = .; . = ALIGN(8); } > DLM - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - .ahb_sram (NOLOAD) : { KEEP(*(.ahb_sram)) } > AHB_SRAM - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") } diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld new file mode 100644 index 00000000000..25384416a2a --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt.ld @@ -0,0 +1,331 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_start__ = .; + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + __noncacheable_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + +} diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld new file mode 100644 index 00000000000..f71e19fab9b --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -0,0 +1,350 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 256K + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_start__ = .; + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + __noncacheable_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + +} diff --git a/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld new file mode 100644 index 00000000000..d3f989e15c6 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/linker_scripts/gcc/ram_rtt.ld @@ -0,0 +1,265 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; + +MEMORY +{ + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > ILM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > ILM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + } > ILM + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + . = ALIGN(8); + PROVIDE(__ramfunc_start__ = .); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_start__ = .; + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > DLM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + __noncacheable_end__ = .; + . = ALIGN(8); + } > DLM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > DLM + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM + +} diff --git a/bsp/hpmicro/hpm5e00evk/board/pinmux.c b/bsp/hpmicro/hpm5e00evk/board/pinmux.c new file mode 100644 index 00000000000..a110e7b956a --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/pinmux.c @@ -0,0 +1,640 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART4) { + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_UART4_TXD; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_UART4_RXD; + } else { + ; + } +} + +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == HPM_UART5) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PC22].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_GPIO_C_22; + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C0) { +#if 1 + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +#else + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; /* Codec0 */ + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD09].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PD08].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; +#endif + } else if (ptr == HPM_I2C1) { /* AT24C02 */ + } else if (ptr == HPM_I2C2) { /* Codec1 */ + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_I2C2_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_I2C2_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD03].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PD02].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + ; + } +} + +void init_ppi_pins(void) +{ + /* DQ Group A */ + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_PPI0_DQ_00; + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_PPI0_DQ_01; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_PPI0_DQ_02; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_PPI0_DQ_03; + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_PPI0_DQ_04; + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_PPI0_DQ_05; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_PPI0_DQ_06; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_PPI0_DQ_07; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PD14_FUNC_CTL_PPI0_DQ_08; + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_PPI0_DQ_09; + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_PPI0_DQ_10; + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_PPI0_DQ_11; + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_PPI0_DQ_12; + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_PPI0_DQ_13; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_PPI0_DQ_14; + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_PPI0_DQ_15; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_PPI0_DQ_16; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_PPI0_DQ_17; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PPI0_DQ_18; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PPI0_DQ_19; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PPI0_DQ_20; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PPI0_DQ_21; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PPI0_DQ_22; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_PPI0_DQ_23; + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_PPI0_DQ_24; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_PPI0_DQ_25; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PPI0_DQ_26; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PPI0_DQ_27; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PPI0_DQ_28; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_PPI0_DQ_29; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_PPI0_DQ_30; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_PPI0_DQ_31; + + /* Improve DQ pins driver strength */ + HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC00].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC01].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC07].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC07].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = (HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL & ~IOC_PAD_PAD_CTL_DS_MASK) | IOC_PAD_PAD_CTL_DS_SET(5); + + /* DM Group A */ + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_PPI0_DM_0; + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_PPI0_DM_1; + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_PPI0_DM_2; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_PPI0_DM_3; + + /* CS */ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_PPI0_CS_0; + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_PPI0_CS_1; + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_PPI0_CS_2; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_PPI0_CS_3; + + /* CTRL */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_PPI0_CTR_0; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_PPI0_CTR_1; + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_PPI0_CTR_2; + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_PPI0_CTR_3; + HPM_IOC->PAD[IOC_PAD_PE00].FUNC_CTL = IOC_PE00_FUNC_CTL_PPI0_CTR_4; + HPM_IOC->PAD[IOC_PAD_PE01].FUNC_CTL = IOC_PE01_FUNC_CTL_PPI0_CTR_5; + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_PPI0_CTR_6; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_PPI0_CTR_7; + + /* CLK */ + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_PPI0_CLK; + + /* DQ Group B */ + /* + * HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_PPI0_DQ_00; + * HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_PPI0_DQ_01; + * HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_PPI0_DQ_02; + * HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_PPI0_DQ_03; + * HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_PPI0_DQ_04; + * HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_PPI0_DQ_05; + * HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_PPI0_DQ_06; + * HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_PPI0_DQ_07; + * HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_PPI0_DQ_08; + * HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_PPI0_DQ_09; + * HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_PPI0_DQ_10; + * HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_PPI0_DQ_11; + * HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_PPI0_DQ_12; + * HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_PPI0_DQ_13; + * HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_PPI0_DQ_14; + * HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_PPI0_DQ_15; + */ + + /* DM Group B */ + /* + * HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_PPI0_DM_0; + * HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_PPI0_DM_1; + */ +} + +void init_sdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF17].FUNC_CTL = IOC_PF17_FUNC_CTL_SDM0_CLK_0; + HPM_IOC->PAD[IOC_PAD_PF16].FUNC_CTL = IOC_PF16_FUNC_CTL_SDM0_DAT_0; +} + +void init_pwm_pin_as_sdm_clock(void) +{ + HPM_IOC->PAD[IOC_PAD_PF15].FUNC_CTL = IOC_PF15_FUNC_CTL_PWM1_P_7; +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* LED_G */ + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_GPIO_C_28; + HPM_IOC->PAD[IOC_PAD_PC28].PAD_CTL = pad_ctl; + + /* KEYA */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_GPIO_C_21; + HPM_IOC->PAD[IOC_PAD_PC21].PAD_CTL = pad_ctl; + + /* KEYB */ + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_GPIO_C_25; + HPM_IOC->PAD[IOC_PAD_PC25].PAD_CTL = pad_ctl; +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_SPI1_CS_0; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI1_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + } else { + ; + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI1) { + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_GPIO_C_11; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_SPI1_MISO; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_SPI1_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + } +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + trgm_output_t trgm0_io_config = {0}; + if (ptr == HPM_GPTMR0) { + trgm0_io_config.invert = 0; + trgm0_io_config.type = trgm_output_same_as_input; + + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_TRGM_P_00; + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P00; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_CAPT_2, &trgm0_io_config); + + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_TRGM_P_07; + trgm_enable_io_output(HPM_TRGM0, 1 << 7); + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P07, &trgm0_io_config); + + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_TRGM_P_15; + trgm_enable_io_output(HPM_TRGM0, 1 << 15); + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P15, &trgm0_io_config); + } else if (ptr == HPM_GPTMR1) { + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_TRGM_P_03; + trgm_enable_io_output(HPM_TRGM0, 1 << 3); + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P03, &trgm0_io_config); + } +} + +void init_hall_trgm_pins(void) +{ + init_qeiv2_uvw_pins(BOARD_BLDC_QEIV2_BASE); +} + +void init_qei_trgm_pins(void) +{ + init_qeiv2_ab_pins(BOARD_BLDC_QEIV2_BASE); +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ +} + +void init_acmp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* CMP1.INN6 */ +} + +void init_pwm_fault_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05; +} + +void init_pwm_pins(PWMV2_Type *ptr) +{ + if (ptr == HPM_PWM0) { + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_PWM0_P_0; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_PWM0_P_1; + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_PWM0_P_2; + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_PWM0_P_3; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_PWM0_P_4; + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_PWM0_P_5; + } else { + ; + } +} + +void init_usb_pins(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF22].FUNC_CTL = IOC_PF22_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF23].FUNC_CTL = IOC_PF23_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PF19_FUNC_CTL_USB0_PWR; + } +} + +void init_clk_obs_pins(void) +{ + /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ +} + +void init_qeo_pins(QEOV2_Type *ptr) +{ + if (ptr == HPM_QEO1) { + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_QEO1_Z; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_QEO1_A; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_QEO1_B; + } +} + +void init_qeiv2_uvw_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_QEI0_B; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_QEI0_Z; + } else { + } +} + +void init_qeiv2_ab_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_QEI0_B; + } else { + ; + } +} + +void init_qeiv2_abz_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_QEI0_B; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_QEI0_Z; + } else { + ; + } +} + + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_GPIO_C_19; + + HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_ETH0_MDIO; + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_ETH0_MDC; + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_ETH0_RXDV; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_ETH0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_ETH0_RXD_3; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_ETH0_RXCK; + + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_ETH0_TXCK; + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_ETH0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_ETH0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_ETH0_TXEN; + } +} + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF18].FUNC_CTL = IOC_PF18_FUNC_CTL_ETH0_EVTO_0; +} + +void init_adc16_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_owr_pins(OWR_Type *ptr) +{ + (void) ptr; + + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_OWR0_DAT; +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC0.6 / ADC1.6 : cos_ch */ + HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.5 / ADC1.5 : sin_ch */ +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN1) { + HPM_IOC->PAD[IOC_PAD_PE05].FUNC_CTL = IOC_PE05_FUNC_CTL_MCAN1_TXD; + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_MCAN1_RXD; + HPM_IOC->PAD[IOC_PAD_PE03].FUNC_CTL = IOC_PE03_FUNC_CTL_MCAN1_STBY; + } else { + /* Invalid CAN instance */ + } +} + +void init_led_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_GPIO_A_09; +} + +void init_led_pins_as_pwm(void) +{ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_TRGM_P_09; +} + +void init_plb_ab_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_TRGM_P_06; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_TRGM_P_07; +} + +void init_plb_lin_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05; +} + +void init_plb_pulse_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_TRGM_P_05; +} + +void init_plb_filter_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_TRGM_P_02; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_TRGM_P_04; +} + +/* Pin configuration is required when ESC use actual eeprom devices */ +void init_esc_eeprom_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_ESC0_SCL; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_ESC0_SDA; +} + +/* Pin configuration is required when ESC use actual eeprom devices, use i2c peripheral init eeprom content */ +void init_esc_eeprom_as_i2c_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PD08].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PD09].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + +void init_esc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK; + HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_ESC0_MDIO; + HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_ESC0_MDC; + + /* ESC needs to configure these pins for specific functions, see ESC IOCFG registers */ + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; /* GPIO to reset PHY */ + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ESC0_CTR_2; /* NMII_LINK0 function */ + HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* Internally pull up to avoid suspension */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_ESC0_CTR_5; /* NMII_LINK1 function */ + HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* Internally pull up to avoid suspension */ + HPM_IOC->PAD[IOC_PAD_PE02].FUNC_CTL = IOC_PE02_FUNC_CTL_ESC0_CTR_6; /* NMII_LINK2 function */ + HPM_IOC->PAD[IOC_PAD_PE02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); /* Internally pull up to avoid suspension */ + + /* ESC port0 */ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_ESC0_P0_TXCK; + HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PA29_FUNC_CTL_ESC0_P0_TXEN; + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_ESC0_P0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_ESC0_P0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PA27_FUNC_CTL_ESC0_P0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PA28_FUNC_CTL_ESC0_P0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_ESC0_P0_RXCK; + HPM_IOC->PAD[IOC_PAD_PA16].FUNC_CTL = IOC_PA16_FUNC_CTL_ESC0_P0_RXDV; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_ESC0_P0_RXER; + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_ESC0_P0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ESC0_P0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ESC0_P0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_ESC0_P0_RXD_3; + + /* ESC port1 */ + HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PF02_FUNC_CTL_ESC0_P1_TXCK; + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_ESC0_P1_TXEN; + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_ESC0_P1_TXD_0; + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_ESC0_P1_TXD_1; + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ESC0_P1_TXD_2; + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_ESC0_P1_TXD_3; + HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_ESC0_P1_RXCK; + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_ESC0_P1_RXDV; + HPM_IOC->PAD[IOC_PAD_PF14].FUNC_CTL = IOC_PF14_FUNC_CTL_ESC0_P1_RXER; + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_ESC0_P1_RXD_0; + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_ESC0_P1_RXD_1; + HPM_IOC->PAD[IOC_PAD_PF11].FUNC_CTL = IOC_PF11_FUNC_CTL_ESC0_P1_RXD_2; + HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_ESC0_P1_RXD_3; + + /* ESC port2 */ + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_ESC0_P2_RXDV; + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_ESC0_P2_RXD_0; + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_ESC0_P2_RXD_1; + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_ESC0_P2_RXD_2; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_ESC0_P2_RXD_3; + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_ESC0_P2_RXCK; + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_ESC0_P2_RXER; + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_ESC0_P2_TXCK; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_ESC0_P2_TXD_0; + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PD25_FUNC_CTL_ESC0_P2_TXD_1; + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PD26_FUNC_CTL_ESC0_P2_TXD_2; + HPM_IOC->PAD[IOC_PAD_PD27].FUNC_CTL = IOC_PD27_FUNC_CTL_ESC0_P2_TXD_3; + HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_ESC0_P2_TXEN; +} + +/* ESC input/output demo pins */ +void init_esc_in_out_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_GPIO_D_06; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_GPIO_D_12; + + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_GPIO_C_24; +} + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PD13].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_GPIO_D_13; +} + +void init_eui_pins(EUI_Type *ptr) +{ + if (ptr == HPM_EUI1) { + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_EUI1_CK; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_EUI1_SH; + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_EUI1_DI; + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_EUI1_DO; + } else { + ; + } +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + trgm_output_t trgm0_io_config = {0}; + if (ptr == HPM_GPTMR0) { + if (as_comp == true) { + if (channel == 2) { + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_TRGM_P_07; + trgm_enable_io_output(HPM_TRGM0, 1 << 7); + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P07, &trgm0_io_config); + } else if (channel == 3) { + HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_TRGM_P_15; + trgm_enable_io_output(HPM_TRGM0, 1 << 15); + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P15, &trgm0_io_config); + } else { + ; + } + } else { + if (channel == 2) { + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_TRGM_P_00; + trgm0_io_config.invert = 0; + trgm0_io_config.type = trgm_output_same_as_input; + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P00; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_CAPT_2, &trgm0_io_config); + } else if (channel == 3) { + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_TRGM_P_08; + trgm0_io_config.invert = 0; + trgm0_io_config.type = trgm_output_same_as_input; + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P08; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR0_CAPT_3, &trgm0_io_config); + } else { + ; + } + } + } else if (ptr == HPM_GPTMR1) { + if (as_comp == true) { + if (channel == 2) { + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_TRGM_P_03; + trgm_enable_io_output(HPM_TRGM0, 1 << 3); + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_TRGM0_P03, &trgm0_io_config); + } + } else { + if (channel == 2) { + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_TRGM_P_00; + trgm0_io_config.invert = 0; + trgm0_io_config.type = trgm_output_same_as_input; + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P00; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR1_CAPT_2, &trgm0_io_config); + } else if (channel == 3) { + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_TRGM_P_08; + trgm0_io_config.invert = 0; + trgm0_io_config.type = trgm_output_same_as_input; + trgm0_io_config.input = HPM_TRGM0_INPUT_SRC_TRGM0_P08; + trgm_output_config(HPM_TRGM0, HPM_TRGM0_OUTPUT_SRC_GPTMR1_CAPT_3, &trgm0_io_config); + } else { + ; + } + } + } +} + +void init_clk_ref_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_SOC_REF1; +} diff --git a/bsp/hpmicro/hpm5e00evk/board/pinmux.h b/bsp/hpmicro/hpm5e00evk/board/pinmux.h new file mode 100644 index 00000000000..427479bab28 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/pinmux.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_ppi_pins(void); +void init_sdm_pins(void); +void init_pwm_pin_as_sdm_clock(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm_pins(PWMV2_Type *ptr); +void init_usb_pins(USB_Type *ptr); +void init_qeo_pins(QEOV2_Type *ptr); +void init_qeiv2_uvw_pins(QEIV2_Type *ptr); +void init_qeiv2_ab_pins(QEIV2_Type *ptr); +void init_qeiv2_abz_pins(QEIV2_Type *ptr); +void init_enet_pins(ENET_Type *ptr); +void init_enet_pps_pins(void); +void init_adc16_pins(void); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_led_pins(void); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_plb_ab_pins(void); +void init_plb_pulse_pins(void); +void init_plb_filter_pins(void); +void init_plb_lin_pins(void); +void init_esc_pins(void); +void init_esc_in_out_pin(void); +void init_eui_pins(EUI_Type *ptr); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_owr_pins(OWR_Type *ptr); +void init_clk_ref_pins(void); +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm5e00evk/board/rtt_board.c b/bsp/hpmicro/hpm5e00evk/board/rtt_board.c new file mode 100644 index 00000000000..d93e3a314c6 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/rtt_board.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + board_init_led_pins(); + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb(HPM_USB0); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE |= (1UL << 31); + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + clock_add_to_group(clock_adc0, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + clock_add_to_group(clock_adc1, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc1); + } else { + ; + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWMV2_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_pwm0, 0); + freq = clock_get_frequency(clock_pwm0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_pwm1, 0); + freq = clock_get_frequency(clock_pwm1); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif diff --git a/bsp/hpmicro/hpm5e00evk/board/rtt_board.h b/bsp/hpmicro/hpm5e00evk/board/rtt_board.h new file mode 100644 index 00000000000..fd4967ad7f9 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/board/rtt_board.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2021 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include "board.h" + +/* gpio section */ +#define APP_LED0 (0U) +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOC +#define APP_LED0_GPIO_PIN 28 +#define APP_LED_ON (1) +#define APP_LED_OFF (0) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + +/* CAN section */ +#define BOARD_CAN_NAME "can1" +#define BOARD_CAN_HWFILTER_INDEX (1U) + +/* UART section */ +#define BOARD_UART_NAME "uart4" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART4_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm0" +#define BOARD_PWM_CHANNEL (0U) + +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + +#define IRQn_PendSV IRQn_DEBUG0 + +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm5e00evk/figures/board.png b/bsp/hpmicro/hpm5e00evk/figures/board.png new file mode 100644 index 00000000000..b2d10d7f108 Binary files /dev/null and b/bsp/hpmicro/hpm5e00evk/figures/board.png differ diff --git a/bsp/hpmicro/hpm5e00evk/makefile.targets b/bsp/hpmicro/hpm5e00evk/makefile.targets new file mode 100644 index 00000000000..e71da5a6e1e --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard ../linkscripts/*/*.lds) $(wildcard ../linkscripts/*/*/*.lds) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig.h b/bsp/hpmicro/hpm5e00evk/rtconfig.h new file mode 100644 index 00000000000..1ecff2398b9 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/rtconfig.h @@ -0,0 +1,418 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER + +/* kservice options */ + +/* end of kservice options */ + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_HPM5E00_SERIES + +/* Hardware Drivers Config */ + +#define SOC_HPM5E00 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig.py b/bsp/hpmicro/hpm5e00evk/rtconfig.py new file mode 100644 index 00000000000..eb1161dc9e2 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/rtconfig.py @@ -0,0 +1,150 @@ +# Copyright 2021-2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +SOC_FAMILY='HPM5E00' +CHIP_NAME='HPM5E31' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h b/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h new file mode 100644 index 00000000000..b7ae18b3266 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/rtconfig_preinc.h @@ -0,0 +1,18 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HPM6880 +#define HPM6E80 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/SConscript b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/SConscript new file mode 100644 index 00000000000..a1ec2c8e79f --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c new file mode 100644 index 00000000000..e3f85a9e0ee --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/startup.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ +#ifndef __SES_RISCV + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } +#endif +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + +#ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); +#endif + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init(void) +{ +} diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/port_gcc.S new file mode 100644 index 00000000000..6e8933bd7af --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/port_gcc.S @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + .section .text.entry, "ax" + .align 2 + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S new file mode 100644 index 00000000000..c2000769245 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/start.S @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, SW_handler + csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/vectors.S new file mode 100644 index 00000000000..81b47d89a8c --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/toolchains/gcc/vectors.S @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap +IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ + IRQ_HANDLER 7 /* GPIO0_V IRQ handler */ + IRQ_HANDLER 8 /* GPIO0_W IRQ handler */ + IRQ_HANDLER 9 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 11 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 12 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 13 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 14 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 15 /* OWR0 IRQ handler */ + IRQ_HANDLER 16 /* OWR1 IRQ handler */ + IRQ_HANDLER 17 /* EUI0 IRQ handler */ + IRQ_HANDLER 18 /* EUI1 IRQ handler */ + IRQ_HANDLER 19 /* UART0 IRQ handler */ + IRQ_HANDLER 20 /* UART1 IRQ handler */ + IRQ_HANDLER 21 /* UART2 IRQ handler */ + IRQ_HANDLER 22 /* UART3 IRQ handler */ + IRQ_HANDLER 23 /* UART4 IRQ handler */ + IRQ_HANDLER 24 /* UART5 IRQ handler */ + IRQ_HANDLER 25 /* UART6 IRQ handler */ + IRQ_HANDLER 26 /* UART7 IRQ handler */ + IRQ_HANDLER 27 /* I2C0 IRQ handler */ + IRQ_HANDLER 28 /* I2C1 IRQ handler */ + IRQ_HANDLER 29 /* I2C2 IRQ handler */ + IRQ_HANDLER 30 /* I2C3 IRQ handler */ + IRQ_HANDLER 31 /* SPI0 IRQ handler */ + IRQ_HANDLER 32 /* SPI1 IRQ handler */ + IRQ_HANDLER 33 /* SPI2 IRQ handler */ + IRQ_HANDLER 34 /* SPI3 IRQ handler */ + IRQ_HANDLER 35 /* TSNS IRQ handler */ + IRQ_HANDLER 36 /* MBX0A IRQ handler */ + IRQ_HANDLER 37 /* MBX0B IRQ handler */ + IRQ_HANDLER 38 /* EWDG0 IRQ handler */ + IRQ_HANDLER 39 /* EWDG1 IRQ handler */ + IRQ_HANDLER 40 /* HDMA IRQ handler */ + IRQ_HANDLER 41 /* LOBS IRQ handler */ + IRQ_HANDLER 42 /* ADC0 IRQ handler */ + IRQ_HANDLER 43 /* ADC1 IRQ handler */ + IRQ_HANDLER 44 /* ACMP0[0] IRQ handler */ + IRQ_HANDLER 45 /* ACMP0[1] IRQ handler */ + IRQ_HANDLER 46 /* MCAN0 IRQ handler */ + IRQ_HANDLER 47 /* MCAN1 IRQ handler */ + IRQ_HANDLER 48 /* MCAN2 IRQ handler */ + IRQ_HANDLER 49 /* MCAN3 IRQ handler */ + IRQ_HANDLER 50 /* PTPC IRQ handler */ + IRQ_HANDLER 51 /* QEI0 IRQ handler */ + IRQ_HANDLER 52 /* QEI1 IRQ handler */ + IRQ_HANDLER 53 /* PWM0 IRQ handler */ + IRQ_HANDLER 54 /* PWM1 IRQ handler */ + IRQ_HANDLER 55 /* SDM0 IRQ handler */ + IRQ_HANDLER 56 /* TRGM[0] IRQ handler */ + IRQ_HANDLER 57 /* TRGM[1] IRQ handler */ + IRQ_HANDLER 58 /* ENET0 IRQ handler */ + IRQ_HANDLER 59 /* NTMR0 IRQ handler */ + IRQ_HANDLER 60 /* USB0 IRQ handler */ + IRQ_HANDLER 61 /* ESC IRQ handler */ + IRQ_HANDLER 62 /* ESC_SYNC0 IRQ handler */ + IRQ_HANDLER 63 /* ESC_SYNC1 IRQ handler */ + IRQ_HANDLER 64 /* ESC_RESET IRQ handler */ + IRQ_HANDLER 65 /* XPI0 IRQ handler */ + IRQ_HANDLER 66 /* PPI IRQ handler */ + IRQ_HANDLER 67 /* XDMA IRQ handler */ + IRQ_HANDLER 68 /* PGPIO IRQ handler */ + IRQ_HANDLER 69 /* PEWDG IRQ handler */ + IRQ_HANDLER 70 /* PTMR IRQ handler */ + IRQ_HANDLER 71 /* PUART IRQ handler */ + IRQ_HANDLER 72 /* FUSE IRQ handler */ + IRQ_HANDLER 73 /* DGO_PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 74 /* DGO_CNT_WAKEUP IRQ handler */ + IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 76 /* SYSCTL IRQ handler */ + IRQ_HANDLER 77 /* CPU0 IRQ handler */ + IRQ_HANDLER 78 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 79 /* DEBUG1 IRQ handler */ diff --git a/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/trap.c b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/trap.c new file mode 100644 index 00000000000..470b3fe2662 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/HPM5E31/trap.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm5e00evk/startup/SConscript b/bsp/hpmicro/hpm5e00evk/startup/SConscript new file mode 100644 index 00000000000..de51a7c0d63 --- /dev/null +++ b/bsp/hpmicro/hpm5e00evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/.config b/bsp/hpmicro/hpm6200evk/.config index af2e756acb0..64ed4c6bad3 100644 --- a/bsp/hpmicro/hpm6200evk/.config +++ b/bsp/hpmicro/hpm6200evk/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -190,7 +191,7 @@ CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_LEGACY=y CONFIG_RT_USING_MSH=y CONFIG_RT_USING_FINSH=y CONFIG_FINSH_USING_MSH=y @@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -211,22 +213,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # # DFS: device virtual file system # -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=16 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=4 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_DFS is not set # end of DFS: device virtual file system # CONFIG_RT_USING_FAL is not set @@ -240,10 +227,11 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set @@ -390,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -497,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -586,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -631,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -724,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -805,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -847,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -860,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1031,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1369,10 +1394,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM6200_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM6000=y +CONFIG_SOC_HPM6200=y # # On-chip Peripheral Drivers @@ -1382,6 +1409,8 @@ CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_UART0_RX_USING_DMA is not set # CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 # CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_SPI is not set diff --git a/bsp/hpmicro/hpm6200evk/SConstruct b/bsp/hpmicro/hpm6200evk/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6200evk/SConstruct +++ b/bsp/hpmicro/hpm6200evk/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6200evk/board/Kconfig b/bsp/hpmicro/hpm6200evk/board/Kconfig index 8f251ca0ffe..43fbd1d4ba0 100644 --- a/bsp/hpmicro/hpm6200evk/board/Kconfig +++ b/bsp/hpmicro/hpm6200evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6000 +config SOC_HPM6200 bool - select SOC_SERIES_HPM6000 + select SOC_HPM6200_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y diff --git a/bsp/hpmicro/hpm6200evk/board/board.c b/bsp/hpmicro/hpm6200evk/board/board.c index e32e72117f6..5025badde52 100644 --- a/bsp/hpmicro/hpm6200evk/board/board.c +++ b/bsp/hpmicro/hpm6200evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024 HPMicro + * Copyright (c) 2023-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause * * @@ -19,10 +19,7 @@ #include "hpm_trgm_drv.h" #include "hpm_pllctlv2_drv.h" #include "hpm_pcfg_drv.h" - -static board_timer_cb timer_cb; -ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag; - +#include /** * @brief FLASH configuration option definitions: * option[0]: @@ -77,11 +74,11 @@ ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; +__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -95,8 +92,6 @@ void board_init_console(void) And a uart rx dma request will be generated by default uart fifo dma trigger level. */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -188,6 +183,7 @@ void board_init(void) void board_init_core1(void) { + clock_update_core_clock(); board_init_console(); board_init_pmp(); } @@ -202,6 +198,9 @@ void board_delay_ms(uint32_t ms) clock_cpu_delay_ms(ms); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -209,7 +208,6 @@ void board_timer_isr(void) timer_cb(); } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); void board_timer_create(uint32_t ms, board_timer_cb cb) { @@ -229,6 +227,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -262,30 +261,43 @@ void board_i2c_bus_clear(I2C_Type *ptr) } } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { i2c_config_t config; hpm_stat_t stat; uint32_t freq; - if (ptr == NULL) { - return; - } + freq = board_init_i2c_clock(ptr); board_i2c_bus_clear(ptr); init_i2c_pins(ptr); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } @@ -294,22 +306,13 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_spi_clock(SPI_Type *ptr) { if (ptr == HPM_SPI1) { - /* SPI1 clock configure */ clock_add_to_group(clock_spi1, 0); - clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); /* 80MHz */ - return clock_get_frequency(clock_spi1); } else if (ptr == HPM_SPI2) { - /* SPI3 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_pll0_clk0, 5U); /* 80MHz */ - return clock_get_frequency(clock_spi2); } else if (ptr == HPM_SPI3) { - /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); - clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */ - return clock_get_frequency(clock_spi3); } return 0; @@ -397,24 +400,12 @@ void board_led_write(uint8_t state) gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); } -void board_init_usb_pins(void) +void board_init_usb(USB_Type *ptr) { - /* set pull-up for USBx ID pin */ - init_usb_pins(); - - /* configure USBx ID pin as input function */ - gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); -} - -uint8_t board_get_usb_id_status(void) -{ - return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + } } void board_init_pmp(void) @@ -472,89 +463,44 @@ void board_init_clock(void) /* Select clock setting preset1 */ sysctl_clock_set_preset(HPM_SYSCTL, 2); } - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_ahbp, 0); clock_add_to_group(clock_axic, 0); clock_add_to_group(clock_axis, 0); - - clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_xpi0, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_lin0, 0); - clock_add_to_group(clock_lin1, 0); - clock_add_to_group(clock_lin2, 0); - clock_add_to_group(clock_lin3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_sdp, 0); clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_ram0, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); clock_add_to_group(clock_mot0, 0); clock_add_to_group(clock_mot1, 0); clock_add_to_group(clock_mot2, 0); clock_add_to_group(clock_mot3, 0); - clock_add_to_group(clock_acmp, 0); clock_add_to_group(clock_synt, 0); - clock_add_to_group(clock_lmm0, 0); - clock_add_to_group(clock_lmm1, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - - clock_add_to_group(clock_dac0, 0); - clock_add_to_group(clock_dac1, 0); - - clock_add_to_group(clock_tsns, 0); - clock_add_to_group(clock_crc0, 0); - clock_add_to_group(clock_sdm0, 0); - + clock_add_to_group(clock_ptpc, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Add the CPU1 clock to Group1 */ + /* Add clocks to Group1 */ + clock_add_to_group(clock_cpu1, 1); clock_add_to_group(clock_mchtmr1, 1); - /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); /* Bump up DCDC voltage to 1275mv */ pcfg_dcdc_set_voltage(HPM_PCFG, 1275); - /* Connect CAN2/CAN3 to pll0clk0*/ - clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 1); - clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 1); - - /* Configure CPU to 600MHz, AXI/AHB to 200MHz */ - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3); - /* Configure PLL1_CLK0 Post Divider to 1 */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 0); - pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 600000000); + /* Configure CPU to 600MHz, AXI/AHB to 200MHz. CPU1 clock freqency same as CPU0 */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk1, 1, 3, 3); + /* Configure PLL1 Post Divider */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll1, pllctlv2_clk0, pllctlv2_div_2p0); /* PLL1CLK0: 480MHz */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll1, pllctlv2_clk1, pllctlv2_div_1p6); /* PLL1CLK1: 600MHz */ + /* Configure PLL1 Frequency to 960MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll1, 960000000); clock_update_core_clock(); /* Configure mchtmr to 24MHz */ @@ -562,72 +508,12 @@ void board_init_clock(void) clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); } -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr3); - } - else { - /* Invalid instance */ - } - return freq; -} - -uint32_t board_init_adc12_clock(ADC16_Type *ptr) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - switch ((uint32_t)ptr) { - case HPM_ADC0_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc0, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc0); - break; - case HPM_ADC1_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc1, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc1); - break; - case HPM_ADC2_BASE: - /* Configure the ADC clock to 200MHz */ - clock_set_adc_source(clock_adc2, clk_adc_src_ana0); - clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); - freq = clock_get_frequency(clock_adc2); - break; - default: - /* Invalid ADC instance */ - break; - } - return freq; -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) -{ - uint32_t freq = 0; - - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -635,10 +521,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U); } - + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -646,10 +532,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc1, clk_adc_src_ana1); clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U); } - + clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); - } else if (ptr == HPM_ADC2) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); } else { @@ -657,7 +543,7 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc2, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U); } - + clock_add_to_group(clock_adc2, 0); freq = clock_get_frequency(clock_adc2); } @@ -677,7 +563,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) clock_set_dac_source(clock_dac0, clk_dac_src_ana3); clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); } - + clock_add_to_group(clock_dac0, 0); freq = clock_get_frequency(clock_dac0); } else if (ptr == HPM_DAC1) { if (clk_src_ahb == true) { @@ -688,7 +574,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) clock_set_dac_source(clock_dac1, clk_dac_src_ana4); clock_set_source_divider(clock_ana4, clk_src_pll0_clk1, 2); } - + clock_add_to_group(clock_dac1, 0); freq = clock_get_frequency(clock_dac1); } @@ -706,18 +592,22 @@ uint32_t board_init_can_clock(MCAN_Type *ptr) if (ptr == HPM_MCAN0) { /* Set the CAN0 peripheral clock to 8MHz */ clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5); + clock_add_to_group(clock_can0, 0); freq = clock_get_frequency(clock_can0); } else if (ptr == HPM_MCAN1) { /* Set the CAN1 peripheral clock to 8MHz */ clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5); + clock_add_to_group(clock_can1, 0); freq = clock_get_frequency(clock_can1); } else if (ptr == HPM_MCAN2) { /* Set the CAN2 peripheral clock to 8MHz */ clock_set_source_divider(clock_can2, clk_src_pll0_clk0, 5); + clock_add_to_group(clock_can2, 0); freq = clock_get_frequency(clock_can2); } else if (ptr == HPM_MCAN3) { /* Set the CAN2 peripheral clock to 8MHz */ clock_set_source_divider(clock_can3, clk_src_pll0_clk0, 5); + clock_add_to_group(clock_can3, 0); freq = clock_get_frequency(clock_can3); } else { /* Invalid CAN instance */ @@ -730,6 +620,17 @@ void board_init_adc16_pins(void) init_adc_pins(); } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + void board_init_rgb_pwm_pins(void) { init_led_pins_as_pwm(); @@ -781,44 +682,51 @@ uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 6); clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { - clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 6); clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 6); clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); - } else if (ptr == HPM_UART6) { - clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 6); - clock_add_to_group(clock_uart6, 0); - freq = clock_get_frequency(clock_uart6); } else { /* Not supported */ } return freq; } -uint32_t board_init_pwm_clock(PWM_Type *ptr) +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) { - uint32_t freq = 0; - if (ptr == HPM_PWM0) { - clock_add_to_group(clock_mot0, 0); - freq = clock_get_frequency(clock_mot0); - } else if (ptr == HPM_PWM1) { - clock_add_to_group(clock_mot1, 0); - freq = clock_get_frequency(clock_mot1); - } else if (ptr == HPM_PWM2) { - clock_add_to_group(clock_mot2, 0); - freq = clock_get_frequency(clock_mot2); - } else if (ptr == HPM_PWM3) { - clock_add_to_group(clock_mot3, 0); - freq = clock_get_frequency(clock_mot3); - } else { + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pins(); +} +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ } return freq; } + diff --git a/bsp/hpmicro/hpm6200evk/board/board.h b/bsp/hpmicro/hpm6200evk/board/board.h index ac74d1ca1d4..5395f8d53ab 100644 --- a/bsp/hpmicro/hpm6200evk/board/board.h +++ b/bsp/hpmicro/hpm6200evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,6 +12,7 @@ #include "hpm_clock_drv.h" #include "hpm_soc.h" #include "hpm_soc_feature.h" +#include "hpm_trgm_drv.h" #include "pinmux.h" #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #include "hpm_debug_console.h" @@ -22,27 +23,22 @@ #define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE -/* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX - #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART2 -#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart2 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PB02 + /* uart lin sample section */ #define BOARD_UART_LIN BOARD_APP_UART_BASE #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ @@ -50,7 +46,6 @@ #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC #define BOARD_UART_LIN_TX_PIN (26U) /* PC26 should align with used pin in pinmux configuration */ - #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART @@ -59,15 +54,15 @@ #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_UART_BASE HPM_UART2 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart2 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART2 +#define BOARD_CONSOLE_UART_BASE HPM_UART2 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart2 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART2 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX #endif @@ -83,6 +78,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -102,9 +99,11 @@ #define BOARD_SDM_CHANNEL 3 #define BOARD_SDM_TRGM HPM_TRGM3 #define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CLK clock_gptmr3 #define BOARD_SDM_TRGM_GPTMR_CH 2 #define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 #define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 +#define BOARD_SDM_TRGM_SYNC_SRC (15) /* lin section */ #define BOARD_LIN HPM_LIN0 @@ -117,13 +116,13 @@ #define BOARD_FLASH_SIZE (16 * SIZE_1MB) /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C3 -#define BOARD_APP_I2C_IRQ IRQn_I2C3 -#define BOARD_APP_I2C_CLK_NAME clock_i2c3 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C3 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_I2C_BASE HPM_I2C3 +#define BOARD_APP_I2C_IRQ IRQn_I2C3 +#define BOARD_APP_I2C_CLK_NAME clock_i2c3 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C3 + #define BOARD_I2C_GPIO_CTRL HPM_GPIO0 #define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOB #define BOARD_I2C_SCL_GPIO_PIN 20 @@ -132,17 +131,20 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR1 @@ -199,12 +201,14 @@ #define BOARD_APP_ADC16_IRQn IRQn_ADC0 #define BOARD_APP_ADC16_CH_1 (8U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) -#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI -#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A @@ -229,11 +233,6 @@ #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) -/* USB section */ -#define BOARD_USB0_ID_PORT (HPM_GPIO0) -#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC) -#define BOARD_USB0_ID_GPIO_PIN (23) - /*BLDC pwm*/ /*PWM define*/ @@ -258,12 +257,14 @@ /*HALL define*/ -#define BOARD_BLDC_HALL_BASE HPM_HALL0 -#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 -#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 -#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 -#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 -#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_HALL_BASE HPM_HALL0 +#define BOARD_BLDC_HALL_TRGM HPM_TRGM0 +#define BOARD_BLDC_HALL_IRQ IRQn_HALL0 +#define BOARD_BLDC_HALL_TRGM_HALL_U_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P6 +#define BOARD_BLDC_HALL_TRGM_HALL_V_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P7 +#define BOARD_BLDC_HALL_TRGM_HALL_W_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P8 +/**< The default value is 0. When this value is defined, it means that the development board wiring sequence is different from the others. */ +#define BOARD_BLDC_HALL_DIR_INV (1) #define BOARD_BLDC_HALL_MOTOR_PHASE_COUNT_PER_REV (1000U) /*QEI*/ @@ -283,8 +284,25 @@ #define BOARD_BLDC_TMR_CH 0 #define BOARD_BLDC_TMR_CMP 0 #define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 #define BOARD_BLDC_TMR_RELOAD (100000U) +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) + /*adc*/ #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 #define BOARD_BLDC_ADC_U_BASE HPM_ADC0 @@ -300,8 +318,9 @@ #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_CH8REF + /*PLA*/ #define BOARD_PLA_COUNTER HPM_PLA0 @@ -315,6 +334,10 @@ #define BOARD_PLA_PWM_CMP (8U) #define BOARD_PLA_PWM_CHN (8U) +#define BOARD_PLA_PWM_IN_CHN pla_filter1_inchn0 +#define BOARD_PLA_LEVEL1_FILTER_IN_END pla_filter1_inchn7 +#define BOARD_PLA_LEVEL1_FILTER_OUT_END pla_filter1_outchn7 + /* APP PWM */ #define BOARD_APP_PWM HPM_PWM0 #define BOARD_APP_PWM_CLOCK_NAME clock_mot0 @@ -325,13 +348,17 @@ #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI /* APP HRPWM */ -#define BOARD_APP_HRPWM HPM_PWM1 -#define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1 -#define BOARD_APP_HRPWM_OUT1 0 -#define BOARD_APP_HRPWM_OUT2 2 -#define BOARD_APP_HRPWM_TRGM HPM_TRGM1 - -#define BOARD_CPU_FREQ (480000000UL) +#define BOARD_APP_HRPWM HPM_PWM1 +#define BOARD_APP_HRPWM_CLOCK_NAME clock_mot1 +#define BOARD_APP_HRPWM_OUT1 0 +#define BOARD_APP_HRPWM_OUT2 2 +#define BOARD_APP_HRPWM_TRGM HPM_TRGM1 +#define BOARD_APP_HRPWM_FAULT_CAP_CMP_INDEX (15U) +#define BOARD_APP_HRPWM_IRQ IRQn_PWM1 +#define BOARD_APP_HRPWM_FAULT_TRGM_SRC HPM_TRGM0_INPUT_SRC_DEBUG_FLAG +#define BOARD_APP_HRPWM_FAULT_TRGM_OUT TRGM_TRGOCFG_PWM_IN15 + +#define BOARD_CPU_FREQ (600000000UL) /* LED */ #define BOARD_R_GPIO_CTRL HPM_GPIO0 @@ -355,6 +382,7 @@ /* Key Section */ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ #define BOARD_APP_GPIO_PIN 2 +#define BOARD_BUTTON_PRESSED_VALUE 0 /* RGB LED Section */ #define BOARD_RED_PWM_IRQ IRQn_PWM3 @@ -498,15 +526,65 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR1 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 +#define BOARD_THREADX_TIMER HPM_GPTMR1 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR1 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr1 /* Tamper Section */ #define BOARD_TAMP_ACTIVE_CH 4 #define BOARD_TAMP_LOW_LEVEL_CH 6 +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_I2S_SPI_CS_GPIO_PIN 31 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PB31 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR1 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 0 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr1 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR1 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 1 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr1 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR1 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr1 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR1 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR1 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 3 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr1 + +/* BGPR */ +#define BOARD_BGPR HPM_BGPR + +#define BOARD_APP_CLK_REF_PIN_NAME "J1[4] (PA14)" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref0 + + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -519,6 +597,7 @@ void board_init_console(void); void board_init_core1(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_can(MCAN_Type *ptr); @@ -540,26 +619,24 @@ void board_led_toggle(void); /* Initialize SoC overall clocks */ void board_init_clock(void); -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); - uint32_t board_init_spi_clock(SPI_Type *ptr); void board_init_lin_pins(LIN_Type *ptr); uint32_t board_init_lin_clock(LIN_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); + +void board_init_acmp_clock(ACMP_Type *ptr); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); void board_init_adc16_pins(void); - +void board_init_acmp_pins(void); void board_init_dac_pins(DAC_Type *ptr); uint32_t board_init_can_clock(MCAN_Type *ptr); -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); -uint8_t board_get_usb_id_status(void); +void board_init_usb(USB_Type *ptr); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: @@ -576,7 +653,11 @@ void board_ungate_mchtmr_at_lp_mode(void); /* Initialize the UART clock */ uint32_t board_init_uart_clock(UART_Type *ptr); -uint32_t board_init_pwm_clock(PWM_Type *ptr); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); + +void board_init_clk_ref_pin(void); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld index a052e496ff0..8539708e369 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -44,22 +44,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -80,12 +84,12 @@ SECTIONS KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -110,12 +114,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -149,6 +147,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -161,6 +173,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -181,22 +203,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -224,10 +250,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -248,7 +274,10 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + .heap(NOLOAD) : { . = ALIGN(8); @@ -268,7 +297,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > DLM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -279,8 +309,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld new file mode 100644 index 00000000000..366923d61af --- /dev/null +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/flash_usb_nic.ld @@ -0,0 +1,330 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 144K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x4000; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = 64K + AXI_SRAM (wx) : ORIGIN = 0x01090000, LENGTH = 176K + SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > ILM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + __share_mem_start__ = ORIGIN(SHARE_RAM); + __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); + +} diff --git a/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 76% rename from bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld index 67adc0489b7..83c625a6445 100644 --- a/bsp/hpmicro/hpm6200evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6200evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,20 +1,20 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x2000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 0x8000; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 0x10000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 128K; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 32k; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 128K - DLM (w) : ORIGIN = 0x80000, LENGTH = 96K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x90000, LENGTH = NONCACHEABLE_SIZE - AXI_SRAM (wx) : ORIGIN = 0x01084000, LENGTH = 224K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01080000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x01088000, LENGTH = 208K SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k } @@ -94,11 +94,11 @@ SECTIONS PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > AXI_SRAM + } > ILM .rel : { KEEP(*(.rel*)) - } > AXI_SRAM + } > ILM .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) @@ -124,22 +124,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -167,10 +171,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -193,7 +197,18 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_ram_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast_ram.init); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -201,7 +216,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > ILM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast_ram.init) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -218,8 +234,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -246,5 +265,6 @@ SECTIONS . += HEAP_SIZE; __heap_end__ = .; - } > DLM + } > AXI_SRAM } +ASSERT((((__noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init) <= ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM does not have enough space! ******") \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.c b/bsp/hpmicro/hpm6200evk/board/pinmux.c index 13e02932d82..9b022a40cee 100644 --- a/bsp/hpmicro/hpm6200evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 hpmicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -115,11 +115,12 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI; HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } else if (ptr == HPM_SPI2) { - HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_SPI2_CSN; - HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO; - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI; - HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PB04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -130,11 +131,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_SPI1_MOSI; HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } else if (ptr == HPM_SPI2) { - HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_GPIO_C_22; - HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_SPI2_MISO; - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_SPI2_MOSI; - HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PB03].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PB04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -149,8 +151,18 @@ void init_gptmr_pins(GPTMR_Type *ptr) { if (ptr == HPM_GPTMR1) { HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0; + /* TMR1 compare 0 */ HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPTMR1_COMP_0; + /* TMR1 compare 1 */ HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPTMR1_COMP_1; + /* TMR1 compare 2 */ + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_TRGM1_P_00; + trgm_output_t trgm1_io_config0 = {0}; + trgm1_io_config0.invert = 0; + trgm1_io_config0.type = trgm_output_same_as_input; + trgm1_io_config0.input = HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2; + trgm_output_config(HPM_TRGM1, HPM_TRGM1_OUTPUT_SRC_TRGM1_P0, &trgm1_io_config0); + trgm_enable_io_output(HPM_TRGM1, 1 << 0); } } @@ -214,10 +226,13 @@ void init_adc_bldc_pins(void) HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; - HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + if (ptr == HPM_USB0) { + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_USB0_ID; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_USB0_PWR; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_USB0_OC; + } } void init_can_pins(MCAN_Type *ptr) @@ -324,3 +339,46 @@ void init_tamper_pins(void) HPM_BIOC->PAD[IOC_PAD_PZ04].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK; HPM_BIOC->PAD[IOC_PAD_PZ05].PAD_CTL &= ~IOC_PAD_PAD_CTL_OD_MASK; } + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB02].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_GPIO_B_02; +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR1) { + if (as_comp) { + switch (channel) { + case 0: + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPTMR1_COMP_0; + break; + case 1: + HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PA26_FUNC_CTL_GPTMR1_COMP_1; + break; + case 2: + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_TRGM1_P_00; + trgm_output_t trgm1_io_config0 = {0}; + trgm1_io_config0.invert = 0; + trgm1_io_config0.type = trgm_output_same_as_input; + trgm1_io_config0.input = HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2; + trgm_output_config(HPM_TRGM1, HPM_TRGM1_OUTPUT_SRC_TRGM1_P0, &trgm1_io_config0); + trgm_enable_io_output(HPM_TRGM1, 1 << 0); + break; + default: + break; + } + } else { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0; + } + } + } +} + +void init_clk_ref_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_SOC_REF0; +} diff --git a/bsp/hpmicro/hpm6200evk/board/pinmux.h b/bsp/hpmicro/hpm6200evk/board/pinmux.h index 12686d8d7e2..c91350dd665 100644 --- a/bsp/hpmicro/hpm6200evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6200evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 hpmicro + * Copyright (c) 2022-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -27,7 +27,7 @@ void init_pwm_pins(PWM_Type *ptr); void init_hrpwm_pins(PWM_Type *ptr); void init_adc_pins(void); void init_dac_pins(DAC_Type *ptr); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_can_pins(MCAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); @@ -41,7 +41,9 @@ void init_sdm_pins(void); void init_pla_tamagawa_pins(void); void init_motor_over_zero_sensorless_adc_pins(void); void init_tamper_pins(void); - +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pins(void); #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.c b/bsp/hpmicro/hpm6200evk/board/rtt_board.c index 8e9d5a1d7b9..86b5a92a259 100644 --- a/bsp/hpmicro/hpm6200evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.c @@ -60,6 +60,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); } @@ -93,7 +94,7 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); + board_init_usb(HPM_USB0); } ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) @@ -105,7 +106,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->RESET_HOT &= ~(1UL << 31); HPM_PPOR->RESET_COLD |= (1UL << 31); @@ -127,3 +128,94 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk0, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk0, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk0 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk0, 2U); + } + clock_add_to_group(clock_adc2, 0); + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif + + +void hpm_usb_isr_enable(uint32_t base) +{ + if (base == HPM_USB0_BASE) { + intc_m_enable_irq_with_priority(IRQn_USB0, 4); + } else { +#ifdef HPM_USB1_BASE + intc_m_enable_irq_with_priority(IRQn_USB1, 4); +#endif + } +} + +void hpm_usb_isr_disable(uint32_t base) +{ + if (base == HPM_USB0_BASE) { + intc_m_disable_irq(IRQn_USB0); + } else { +#ifdef HPM_USB1_BASE + intc_m_disable_irq(IRQn_USB1); +#endif + } +} diff --git a/bsp/hpmicro/hpm6200evk/board/rtt_board.h b/bsp/hpmicro/hpm6200evk/board/rtt_board.h index e21cb87f520..0f659c19280 100644 --- a/bsp/hpmicro/hpm6200evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6200evk/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,8 +10,10 @@ #include "hpm_common.h" #include "hpm_soc.h" #include +#include "board.h" /* gpio section */ +#define APP_LED0 (0U) #define APP_LED0_PIN_NUM GET_PIN(B, 19) #define APP_LED_ON (1) #define APP_LED_OFF (0) @@ -21,6 +23,12 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* CAN section */ #define BOARD_CAN_NAME "can0" #define BOARD_CAN_HWFILTER_INDEX (0U) @@ -33,6 +41,10 @@ #define BOARD_PWM_NAME "pwm0" #define BOARD_PWM_CHANNEL (0) +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + #define IRQn_PendSV IRQn_DEBUG_0 /*************************************************************** diff --git a/bsp/hpmicro/hpm6200evk/rtconfig.h b/bsp/hpmicro/hpm6200evk/rtconfig.h index 2277889b6aa..cab6e7a84fc 100644 --- a/bsp/hpmicro/hpm6200evk/rtconfig.h +++ b/bsp/hpmicro/hpm6200evk/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -75,6 +75,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -103,6 +104,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -110,6 +113,7 @@ #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 #define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_LEGACY #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH @@ -127,14 +131,6 @@ /* DFS: device virtual file system */ -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 4 -#define DFS_FILESYSTEM_TYPES_MAX 4 -#define RT_USING_DFS_DEVFS /* end of DFS: device virtual file system */ /* Device Drivers */ @@ -142,9 +138,9 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE #define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN /* end of Device Drivers */ @@ -307,6 +303,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -386,16 +396,19 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM6200_SERIES /* Hardware Drivers Config */ -#define SOC_HPM6000 +#define SOC_HPM6200 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm6200evk/rtconfig.py b/bsp/hpmicro/hpm6200evk/rtconfig.py index c45d5ed584a..788b591efe3 100644 --- a/bsp/hpmicro/hpm6200evk/rtconfig.py +++ b/bsp/hpmicro/hpm6200evk/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c b/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c index b0bab335d52..1928adaf580 100644 --- a/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c +++ b/bsp/hpmicro/hpm6200evk/startup/HPM6280/startup.c @@ -1,128 +1,135 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt - */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S b/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S index df204d00ee3..93ff037c998 100644 --- a/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6200evk/startup/HPM6280/toolchains/gcc/start.S @@ -54,7 +54,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6300evk/.config b/bsp/hpmicro/hpm6300evk/.config index 2c76d9e352a..c2619098e9b 100644 --- a/bsp/hpmicro/hpm6300evk/.config +++ b/bsp/hpmicro/hpm6300evk/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -129,9 +127,9 @@ CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=512 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -225,10 +227,11 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set @@ -377,6 +380,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -484,6 +488,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -573,6 +578,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -618,6 +624,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -711,6 +718,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -792,6 +800,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -834,6 +844,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -847,6 +861,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1018,6 +1057,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1356,18 +1396,30 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM6300_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM6000=y +CONFIG_SOC_HPM6300=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set # CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set diff --git a/bsp/hpmicro/hpm6300evk/SConstruct b/bsp/hpmicro/hpm6300evk/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6300evk/SConstruct +++ b/bsp/hpmicro/hpm6300evk/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6300evk/board/Kconfig b/bsp/hpmicro/hpm6300evk/board/Kconfig index 10ed1844a84..7a1ea26dbfe 100644 --- a/bsp/hpmicro/hpm6300evk/board/Kconfig +++ b/bsp/hpmicro/hpm6300evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6000 +config SOC_HPM6300 bool - select SOC_SERIES_HPM6000 + select SOC_HPM6300_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -11,11 +11,23 @@ config BSP_USING_ENET_PHY_RTL8201 bool default n +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -45,6 +57,37 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART2 bool "Enable UART2" @@ -68,50 +111,287 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 endif endif - - menuconfig BSP_USING_SPI bool "Enable SPI" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif config BSP_USING_SPI1 bool "Enable SPI1" - default y + default n if BSP_USING_SPI1 config BSP_SPI1_USING_DMA - bool "Enable SPI1 DMA" - default n + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice endif config BSP_USING_SPI2 bool "Enable SPI2" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice endif config BSP_USING_SPI3 bool "Enable SPI3" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH + + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + if BSP_USING_ETH choice prompt "ETH" @@ -125,11 +405,43 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC" default n select RT_USING_SDIO if BSP_USING_SDXC + select RT_USING_PIN if BSP_USING_SDXC if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" default n if BSP_USING_SDXC0 + config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC0_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC0_USE_NONCACHEABLE_BUFFER + config BSP_SDXC0_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC0_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + + config BSP_SDXC0_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_4BIT @@ -144,6 +456,9 @@ menu "On-chip Peripheral Drivers" config BSP_SDXC0_VOLTAGE_3V3 bool "3.3V" endchoice + config BSP_SDXC0_VSEL_PIN + default "None" + string "VSEL pin name" config BSP_SDXC0_PWR_PIN default "None" string "PWR pin name" @@ -155,15 +470,42 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_HWTIMER if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR3 bool "Enable GPTMR3" default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -173,20 +515,51 @@ menu "On-chip Peripheral Drivers" config BSP_USING_I2C0 bool "Enable I2C0" default y - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" - default n - endif - + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" - default n - endif + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_FEMC @@ -206,6 +579,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n + select RT_USING_PWM if BSP_USING_PWM menuconfig BSP_USING_USB bool "Enable USB" @@ -213,6 +587,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB HOST" @@ -242,9 +617,21 @@ menu "On-chip Peripheral Drivers" config BSP_USING_CAN0 bool "Enable CAN0" default n + if BSP_USING_CAN0 + config BSP_CAN0_IRQ_PRIORITY + int "CAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN1 bool "Enable CAN1" default n + if BSP_USING_CAN1 + config BSP_CAN1_IRQ_PRIORITY + int "CAN1 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC diff --git a/bsp/hpmicro/hpm6300evk/board/board.c b/bsp/hpmicro/hpm6300evk/board/board.c index ed7fdc48d65..8e9a744078b 100644 --- a/bsp/hpmicro/hpm6300evk/board/board.c +++ b/bsp/hpmicro/hpm6300evk/board/board.c @@ -23,9 +23,7 @@ #include "hpm_pcfg_drv.h" #include "hpm_debug_console.h" - -static board_timer_cb timer_cb; -ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag; +#include /** * @brief FLASH configuration option definitions: @@ -81,11 +79,11 @@ ATTR_PLACE_AT_NONCACHEABLE_BSS static bool init_delay_flag; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -99,8 +97,6 @@ void board_init_console(void) And a uart rx dma request will be generated by default uart fifo dma trigger level. */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -169,7 +165,6 @@ void board_ungate_mchtmr_at_lp_mode(void) void board_init(void) { - pcfg_dcdc_set_voltage(HPM_PCFG, 1100); board_init_clock(); board_init_console(); board_init_pmp(); @@ -183,12 +178,13 @@ void board_init(void) void board_init_sdram_pins(void) { - init_sdram_pins(); + init_femc_pins(); } uint32_t board_init_femc_clock(void) { clock_add_to_group(clock_femc, 0); + /* Configure the SDRAM to 166MHz */ clock_set_source_divider(clock_femc, clk_src_pll0_clk1, 2U); @@ -205,6 +201,9 @@ void board_delay_ms(uint32_t ms) clock_cpu_delay_ms(ms); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -212,7 +211,6 @@ void board_timer_isr(void) timer_cb(); } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); void board_timer_create(uint32_t ms, board_timer_cb cb) { @@ -232,6 +230,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -265,30 +264,43 @@ void board_i2c_bus_clear(I2C_Type *ptr) } } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { i2c_config_t config; hpm_stat_t stat; uint32_t freq; - if (ptr == NULL) { - return; - } + freq = board_init_i2c_clock(ptr); board_i2c_bus_clear(ptr); init_i2c_pins(ptr); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } @@ -297,10 +309,7 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_spi_clock(SPI_Type *ptr) { if (ptr == HPM_SPI3) { - /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); - clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); /* 80MHz */ - return clock_get_frequency(clock_spi3); } return 0; @@ -349,24 +358,12 @@ void board_led_write(uint8_t state) gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); } -void board_init_usb_pins(void) -{ - /* set pull-up for USBx ID pin */ - init_usb_pins(); - - /* configure USBx ID pin as input function */ - gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); -} - -uint8_t board_get_usb_id_status(void) +void board_init_usb(USB_Type *ptr) { - return gpio_read_pin(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + } } void board_init_pmp(void) @@ -412,76 +409,37 @@ void board_init_clock(void) sysctl_clock_set_preset(HPM_SYSCTL, 2); } - - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_ahbp, 0); clock_add_to_group(clock_axic, 0); clock_add_to_group(clock_axis, 0); - - clock_add_to_group(clock_mchtmr0, 0); - clock_add_to_group(clock_femc, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_sdxc0, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_sdp, 0); clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_ram0, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); clock_add_to_group(clock_mot0, 0); clock_add_to_group(clock_mot1, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_dao, 0); clock_add_to_group(clock_synt, 0); - clock_add_to_group(clock_lmm0, 0); - clock_add_to_group(clock_pdm, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - - clock_add_to_group(clock_dac0, 0); - - clock_add_to_group(clock_i2s0, 0); - clock_add_to_group(clock_i2s1, 0); - - clock_add_to_group(clock_ffa0, 0); - clock_add_to_group(clock_tsns, 0); - + clock_add_to_group(clock_ptpc, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Configure CPU to 480MHz, AXI/AHB to 160MHz */ - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 3, 3); - /* Configure PLL1_CLK0 Post Divider to 1.2 */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 1, 0, 1); - /* Configure PLL1 clock frequencey to 576MHz, the PLL1_CLK0 frequency = 576MHz / 1.2 = 480MHz */ - pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 1, 576000000); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); + + /* Configure CPU to 648MHz, AXI/AHB to 162MHz */ + sysctl_config_cpu0_domain_clock(HPM_SYSCTL, clock_source_pll1_clk0, 1, 4, 4); + /* Configure PLL1_CLK0 Post Divider to 1 */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll1, pllctlv2_clk0, pllctlv2_div_1p0); /* PLL1CLK0: 648MHz */ + /* Configure PLL1_CLK1 Post Divider to 2 */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll1, pllctlv2_clk1, pllctlv2_div_2p0); /* PLL1CLK1: 324MHz */ + /* Configure PLL1 clock frequency to 648MHz */ + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll1, BOARD_CPU_FREQ); clock_update_core_clock(); /* Configure mchtmr to 24MHz */ @@ -514,12 +472,12 @@ void board_init_adc16_pins(void) init_adc_pins(); } -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@160MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -527,10 +485,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll0_clk1, 2U); } - + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@160MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -538,10 +496,10 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc1, clk_adc_src_ana1); clock_set_source_divider(clock_ana1, clk_src_pll0_clk1, 2U); } - + clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); - } else if (ptr == HPM_ADC2) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@160MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); } else { @@ -549,13 +507,24 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc2, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2U); } - + clock_add_to_group(clock_adc2, 0); freq = clock_get_frequency(clock_adc2); } return freq; } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) { uint32_t freq = 0; @@ -569,7 +538,7 @@ uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) clock_set_dac_source(clock_dac0, clk_dac_src_ana3); clock_set_source_divider(clock_ana3, clk_src_pll0_clk1, 2); } - + clock_add_to_group(clock_dac0, 0); freq = clock_get_frequency(clock_dac0); } @@ -587,10 +556,12 @@ uint32_t board_init_can_clock(CAN_Type *ptr) if (ptr == HPM_CAN0) { /* Set the CAN0 peripheral clock to 80MHz */ clock_set_source_divider(clock_can0, clk_src_pll0_clk0, 5); + clock_add_to_group(clock_can0, 0); freq = clock_get_frequency(clock_can0); } else if (ptr == HPM_CAN1) { /* Set the CAN1 peripheral clock to 80MHz */ clock_set_source_divider(clock_can1, clk_src_pll0_clk0, 5); + clock_add_to_group(clock_can1, 0); freq = clock_get_frequency(clock_can1); } else { /* Invalid CAN instance */ @@ -598,53 +569,18 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr3); - } - else { - /* Invalid instance */ - } - return freq; -} - -void board_sd_power_switch(SDXC_Type *ptr, bool on_off) -{ - /* This feature is not supported */ -} - +#ifdef INIT_EXT_RAM_FOR_DATA /* * this function will be called during startup to initialize external memory for data use */ void _init_ext_ram(void) { uint32_t femc_clk_in_hz; - board_init_sdram_pins(); - femc_clk_in_hz = board_init_femc_clock(); - femc_config_t config = {0}; femc_sdram_config_t sdram_config = {0}; + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); femc_default_config(HPM_FEMC, &config); femc_init(HPM_FEMC, &config); @@ -654,7 +590,7 @@ void _init_ext_ram(void) sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS; sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ @@ -677,22 +613,25 @@ void _init_ext_ram(void) femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } - +#endif uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { - if (ptr != HPM_SDXC0) { - break; - } clock_name_t sdxc_clk = clock_sdxc0; + clock_add_to_group(sdxc_clk, 0); sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); /* Configure the SDXC Frequency to 200MHz */ clock_set_source_divider(sdxc_clk, clk_src_pll0_clk0, 2); sdxc_enable_freq_selection(ptr); + hpm_stat_t status = clock_wait_source_stable(sdxc_clk); + if (status != status_success) { + break; + } + /* Configure the clock below 400KHz for the identification state */ if (freq <= 400000UL) { sdxc_set_clock_divider(ptr, 600); @@ -742,6 +681,7 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { /* set clock source */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for ent0 ptp clock */ clock_set_source_divider(clock_ptp0, clk_src_pll0_clk0, 4); /* 100MHz */ } else { @@ -755,11 +695,12 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { /* Configure Enet clock to output reference clock */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); if (internal) { /* set pll output frequency at 1GHz */ - if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1000000000UL) == status_success) { - /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1, 15); + if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll2, pllctlv2_clk1, pllctlv2_div_4p0); /* set eth clock frequency at 50MHz for enet0 */ clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); } else { @@ -797,15 +738,12 @@ uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { - clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else { @@ -814,13 +752,6 @@ uint32_t board_init_uart_clock(UART_Type *ptr) return freq; } -uint32_t board_init_pwm_clock(PWM_Type *ptr) -{ - uint32_t freq = 0; - (void) ptr; - return freq; -} - uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) { (void) ptr; @@ -854,3 +785,39 @@ void board_init_enet_pps_pins(ENET_Type *ptr) (void) ptr; init_enet_pps_pins(); } + +void board_init_enet_pps_capture_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_capture_pins(); +} + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} + diff --git a/bsp/hpmicro/hpm6300evk/board/board.h b/bsp/hpmicro/hpm6300evk/board/board.h index 63b9d826370..1caf7410747 100644 --- a/bsp/hpmicro/hpm6300evk/board/board.h +++ b/bsp/hpmicro/hpm6300evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -12,6 +12,7 @@ #include "hpm_clock_drv.h" #include "hpm_soc.h" #include "hpm_soc_feature.h" +#include "hpm_trgm_drv.h" #include "pinmux.h" #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #include "hpm_debug_console.h" @@ -20,27 +21,22 @@ #define BOARD_NAME "hpm6300evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) -/* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX - #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART2 -#define BOARD_APP_UART_IRQ IRQn_UART2 +#define BOARD_APP_UART_BASE HPM_UART2 +#define BOARD_APP_UART_IRQ IRQn_UART2 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart2 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART2_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART2_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PC18 + #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART @@ -49,15 +45,15 @@ #if CONSOLE_TYPE_UART == BOARD_CONSOLE_TYPE #ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_UART_BASE HPM_UART13 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif @@ -99,6 +95,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -113,13 +111,13 @@ #define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) -#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) /* nor flash section */ #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) @@ -140,17 +138,20 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_5 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR2 @@ -170,6 +171,7 @@ /* gpio section */ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ #define BOARD_APP_GPIO_PIN 2 +#define BOARD_BUTTON_PRESSED_VALUE 0 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ @@ -207,7 +209,8 @@ /* i2s section */ #define BOARD_APP_I2S_BASE HPM_I2S0 -#define BOARD_APP_I2S_DATA_LINE (2U) +#define BOARD_APP_I2S_TX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_RX_DATA_LINE I2S_DATA_LINE_2 #define BOARD_APP_I2S_CLK_NAME clock_i2s0 #define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 #define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 @@ -217,6 +220,10 @@ #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_AUXI_SNAPSHOT HPM_ENET0 +#define BOARD_ENET_AUXI_SNAPSHOT_IDX enet_ptp_auxi_snapshot_trigger_0 +#define BOARD_ENET_AUXI_SNAPSHOT_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RMII HPM_ENET0 #define BOARD_ENET_RMII_RST_GPIO #define BOARD_ENET_RMII_RST_GPIO_INDEX @@ -226,32 +233,20 @@ #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) #define BOARD_ENET_RMII_PPS0_PINOUT (1) -#define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET0_INT_REF_CLK (1U) -#define BOARD_ENET0_PHY_RST_TIME (30) - -#if BOARD_ENET0_INF -#define BOARD_ENET0_TX_DLY (0U) -#define BOARD_ENET0_RX_DLY (0U) -#endif - -#if __USE_ENET_PTP -#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) -#endif - - /* ADC section */ #define BOARD_APP_ADC16_NAME "ADC0" #define BOARD_APP_ADC16_BASE HPM_ADC0 #define BOARD_APP_ADC16_IRQn IRQn_ADC0 #define BOARD_APP_ADC16_CH_1 (6U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) -#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI -#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A @@ -278,21 +273,18 @@ /* SDXC section */ #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_SDCARD_SDXC_IRQ IRQn_SDXC0 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) #define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION (1) #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_EMMC_SDXC_IRQ IRQn_SDXC0 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) #define BOARD_APP_EMMC_SUPPORT_1V8 (0) #define BOARD_APP_EMMC_SUPPORT_4BIT (1) #define BOARD_APP_EMMC_HOST_USING_IRQ (0) -/* USB section */ -#define BOARD_USB0_ID_PORT (HPM_GPIO0) -#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOC) -#define BOARD_USB0_ID_GPIO_PIN (23) - /*BLDC pwm*/ /*PWM define*/ @@ -342,8 +334,25 @@ #define BOARD_BLDC_TMR_CH 0 #define BOARD_BLDC_TMR_CMP 0 #define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 #define BOARD_BLDC_TMR_RELOAD (100000U) +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) + /*adc*/ #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 #define BOARD_BLDC_ADC_U_BASE HPM_ADC1 @@ -359,8 +368,9 @@ #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM0_CH8REF + /* APP PWM */ #define BOARD_APP_PWM HPM_PWM0 @@ -371,7 +381,7 @@ #define BOARD_APP_PWM_IRQ IRQn_PWM0 #define BOARD_APP_TRGM_PWM_OUTPUT TRGM_TRGOCFG_PWM_SYNCI -#define BOARD_CPU_FREQ (480000000UL) +#define BOARD_CPU_FREQ (648000000UL) /* LED */ #define BOARD_LED_GPIO_CTRL HPM_GPIO0 @@ -393,15 +403,62 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR1 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr1 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR1 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 +#define BOARD_THREADX_TIMER HPM_GPTMR1 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr1 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR1 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR1 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr1 + /* Tamper Section */ #define BOARD_TAMP_NO_LEVEL_PINS #define BOARD_TAMP_ACTIVE_CH 6 +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_I2S_SPI_CS_GPIO_PIN 7 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA07 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR2 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 0 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr2 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR2 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 1 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr2 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR2 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr2 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR2 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR2 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 3 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr2 + +/* BGPR */ +#define BOARD_BGPR HPM_BGPR + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -412,6 +469,7 @@ void board_init(void); void board_init_console(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_can(CAN_Type *ptr); @@ -433,29 +491,26 @@ void board_init_clock(void); uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); + +void board_init_acmp_clock(ACMP_Type *ptr); uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); void board_init_adc16_pins(void); - +void board_init_acmp_pins(void); void board_init_dac_pins(DAC_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); -uint32_t board_init_i2s_clock(I2S_Type *ptr); -uint32_t board_init_pdm_clock(void); -uint32_t board_init_dao_clock(void); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); -uint8_t board_get_usb_id_status(void); +void board_init_usb(USB_Type *ptr); void board_init_enet_pps_pins(ENET_Type *ptr); +void board_init_enet_pps_capture_pins(ENET_Type *ptr); uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); @@ -478,14 +533,15 @@ void board_ungate_mchtmr_at_lp_mode(void); /* Initialize the UART clock */ uint32_t board_init_uart_clock(UART_Type *ptr); -uint32_t board_init_pwm_clock(PWM_Type *ptr); - /* * Get GPIO pin level of onboard LED */ uint8_t board_get_led_gpio_off_level(void); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld new file mode 100644 index 00000000000..d083b1957f2 --- /dev/null +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld @@ -0,0 +1,352 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x80000, LENGTH = 128K + AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 384K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + /* WHD related */ + KEEP(*whd_bus*.o (.text .text* .rodata .rodata*)) + KEEP(*whd_buffer_api.o (.text .text* .rodata .rodata*)) + KEEP(*whd_cdc_bdc.o (.text .text* .rodata .rodata*)) + KEEP(*whd_events.o (.text .text* .rodata .rodata*)) + KEEP(*whd_msgbuf_txrx.o (.text .text* .rodata .rodata*)) + KEEP(*whd_network_if.o (.text .text* .rodata .rodata*)) + KEEP(*whd_sdpcm.o (.text .text* .rodata .rodata*)) + KEEP(*whd_thread.o (.text .text* .rodata .rodata*)) + KEEP(*cyhal*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld index 3447cd8b7cf..f17f1020886 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,6 @@ MEMORY NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -46,23 +45,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; - } > AXI_SRAM + } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -86,12 +88,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -116,12 +118,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -155,6 +151,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -167,6 +177,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -187,22 +207,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -230,10 +254,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -254,7 +278,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -279,7 +305,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -290,8 +317,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -300,10 +330,6 @@ SECTIONS KEEP(*(.ahb_sram)) } > AHB_SRAM - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt_enet.ld similarity index 82% rename from bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt_enet.ld index 41339193998..2bcf46ee20c 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,6 @@ MEMORY NONCACHEABLE_RAM (wx) : ORIGIN = 0x10E0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -46,23 +45,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -106,16 +108,12 @@ SECTIONS KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -173,6 +171,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -181,6 +193,20 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -201,22 +227,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -244,10 +274,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -268,7 +298,10 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + .heap(NOLOAD) : { . = ALIGN(8); @@ -293,7 +326,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -304,8 +338,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -314,10 +351,6 @@ SECTIONS KEEP(*(.ahb_sram)) } > AHB_SRAM - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_sdram_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld rename to bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_sdram_rtt.ld index 4197cc4fe10..8e0be81fec5 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/flash_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,7 +20,6 @@ MEMORY SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } __nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; @@ -46,23 +45,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -82,16 +84,16 @@ SECTIONS KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - + /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -149,6 +151,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -161,6 +177,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -176,26 +202,31 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -223,10 +254,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -247,9 +278,12 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -260,8 +294,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -270,11 +307,6 @@ SECTIONS KEEP(*(.ahb_sram)) } > AHB_SRAM - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .heap(NOLOAD) : { . = ALIGN(8); __heap_start__ = .; diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 82% rename from bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld index af3b9df8d72..39525b220b2 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,6 @@ MEMORY NONCACHEABLE_RAM (wx) : ORIGIN = 0x10F0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS @@ -26,14 +25,14 @@ SECTIONS .start : { . = ALIGN(8); KEEP(*(.start)) - } > AXI_SRAM + } > ILM .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) . = ALIGN(8); - } > AXI_SRAM + } > ILM .text : { . = ALIGN(8); @@ -96,16 +95,26 @@ SECTIONS PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > AXI_SRAM + } > ILM .rel : { KEEP(*(.rel*)) - } > AXI_SRAM + } > ILM .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -126,22 +135,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -169,10 +182,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -195,15 +208,17 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM + } > ILM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -214,8 +229,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -227,10 +245,6 @@ SECTIONS KEEP(*(.ahb_sram)) } > AHB_SRAM - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; @@ -255,7 +269,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld similarity index 87% rename from bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld rename to bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld index 3c584f46e16..7b04b9be329 100644 --- a/bsp/hpmicro/hpm6300evk/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6300evk/board/linker_scripts/gcc/ram_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,6 @@ MEMORY NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k } SECTIONS @@ -119,7 +118,7 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM + } > DLM /* Note: .tbss and .tdata should be adjacent */ .tbss(NOLOAD) : { @@ -129,9 +128,10 @@ SECTIONS *(.tcommon*) _end = .; __tbss_end__ = .; - } > AXI_SRAM + } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; @@ -139,9 +139,10 @@ SECTIONS *(.tdata*) . = ALIGN(8); __tdata_end__ = .; - } > AXI_SRAM + } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -169,10 +170,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -193,17 +194,19 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > AXI_SRAM + } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); - } > AXI_SRAM + } > ILM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -214,8 +217,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -227,10 +233,6 @@ SECTIONS KEEP(*(.ahb_sram)) } > AHB_SRAM - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; @@ -238,7 +240,7 @@ SECTIONS PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); PROVIDE (__rt_rvstack = .); - } > AXI_SRAM + } > DLM .framebuffer (NOLOAD) : { KEEP(*(.framebuffer)) diff --git a/bsp/hpmicro/hpm6300evk/board/pinmux.c b/bsp/hpmicro/hpm6300evk/board/pinmux.c index 86d4008e184..864ac478970 100644 --- a/bsp/hpmicro/hpm6300evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 HPMicro + * Copyright (c) 2022-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -80,7 +80,7 @@ void init_i2c_pins(I2C_Type *ptr) } } -void init_sdram_pins(void) +void init_femc_pins(void) { HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -90,7 +90,7 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #UB */ HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -100,13 +100,13 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #LB */ HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #ADV */ HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -114,52 +114,19 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #OE */ - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #WE */ HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); -} -void init_sram_pins(void) -{ - /* Non-MUX */ /* MUX */ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ - HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ - HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ - - HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ - HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ - HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ - HPM_IOC->PAD[IOC_PAD_PA29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ - HPM_IOC->PAD[IOC_PAD_PA28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ - HPM_IOC->PAD[IOC_PAD_PA27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ - HPM_IOC->PAD[IOC_PAD_PA26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ - HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ - HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ - HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ - HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ - HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ - HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ - HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ - HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ - HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ - - HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ - HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ - HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ - HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ + HPM_IOC->PAD[IOC_PAD_PX07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); /* DQS */ + + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #CE */ } void init_gpio_pins(void) @@ -184,6 +151,12 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PC18].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC21].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC19].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -194,6 +167,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI; HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO; HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PC18].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC21].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC19].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PC20].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -202,15 +181,25 @@ void init_pins(void) #ifdef BOARD_CONSOLE_UART_BASE init_uart_pins(BOARD_CONSOLE_UART_BASE); #endif - init_sdram_pins(); + init_femc_pins(); } void init_gptmr_pins(GPTMR_Type *ptr) { if (ptr == HPM_GPTMR2) { HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; + /* TMR2 compare 0 */ HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; + /* TMR2 compare 1 */ HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_GPTMR2_COMP_1; + /* TMR2 compare 2 */ + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_TRGM1_P_04; + trgm_output_t trgm1_io_config0 = {0}; + trgm1_io_config0.invert = 0; + trgm1_io_config0.type = trgm_output_same_as_input; + trgm1_io_config0.input = HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2; + trgm_output_config(HPM_TRGM1, HPM_TRGM1_OUTPUT_SRC_TRGM1_P4, &trgm1_io_config0); + trgm_enable_io_output(HPM_TRGM1, 1 << 4); } } @@ -273,10 +262,8 @@ void init_pwm_pins(PWM_Type *ptr) void init_adc_pins(void) { - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0.INA6 */ + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } void init_adc_bldc_pins(void) @@ -286,10 +273,11 @@ void init_adc_bldc_pins(void) HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; - HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + if (ptr == HPM_USB0) { + ; + } } void init_can_pins(CAN_Type *ptr) @@ -366,11 +354,7 @@ void init_clk_obs_pins(void) void init_led_pins(void) { - /* Pull up */ - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); - HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_GPIO_A_07; - HPM_IOC->PAD[IOC_PAD_PA07].PAD_CTL = pad_ctl; } void init_dac_pins(DAC_Type *ptr) @@ -392,8 +376,52 @@ void init_enet_pps_pins(void) HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_ETH0_EVTO_1; } +void init_enet_pps_capture_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_ETH0_EVTI_0; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_ETH0_EVTI_1; +} + void init_tamper_pins(void) { HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_TAMP_06 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_BIOC->PAD[IOC_PAD_PZ07].FUNC_CTL = BIOC_PZ07_FUNC_CTL_TAMP_07; } + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PC18].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18; +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR2) { + if (as_comp) { + switch (channel) { + case 0: + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_GPTMR2_COMP_0; + break; + case 1: + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_GPTMR2_COMP_1; + break; + case 2: + HPM_IOC->PAD[IOC_PAD_PA24].FUNC_CTL = IOC_PA24_FUNC_CTL_TRGM1_P_04; + trgm_output_t trgm1_io_config0 = {0}; + trgm1_io_config0.invert = 0; + trgm1_io_config0.type = trgm_output_same_as_input; + trgm1_io_config0.input = HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2; + trgm_output_config(HPM_TRGM1, HPM_TRGM1_OUTPUT_SRC_TRGM1_P4, &trgm1_io_config0); + trgm_enable_io_output(HPM_TRGM1, 1 << 4); + break; + default: + break; + } + } else { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0; + } + } + } +} diff --git a/bsp/hpmicro/hpm6300evk/board/pinmux.h b/bsp/hpmicro/hpm6300evk/board/pinmux.h index 1f4061bd92b..2d6f6c8259e 100644 --- a/bsp/hpmicro/hpm6300evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6300evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - *Copyright (c) 2022-2023 HPMicro + *Copyright (c) 2022-2024 HPMicro * *SPDX-License-Identifier: BSD-3-Clause * @@ -14,8 +14,7 @@ extern "C" { void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); void init_i2c_pins(I2C_Type *ptr); -void init_sdram_pins(void); -void init_sram_pins(void); +void init_femc_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -32,7 +31,7 @@ void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); void init_adc_pins(void); void init_dac_pins(DAC_Type *ptr); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); @@ -40,7 +39,10 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins(void); void init_trgmux_pins(uint32_t pin); void init_enet_pps_pins(void); +void init_enet_pps_capture_pins(void); void init_tamper_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.c b/bsp/hpmicro/hpm6300evk/board/rtt_board.c index 8e9d5a1d7b9..6335b08037a 100644 --- a/bsp/hpmicro/hpm6300evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.c @@ -60,6 +60,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL); } @@ -93,7 +94,7 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); + board_init_usb(HPM_USB0); } ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) @@ -105,7 +106,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->RESET_HOT &= ~(1UL << 31); HPM_PPOR->RESET_COLD |= (1UL << 31); @@ -127,3 +128,70 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll0_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll0_clk1, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll0_clk1, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@160MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@166MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll0_clk1, 2U); + } + clock_add_to_group(clock_adc2, 0); + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} + +uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + return clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + return clock_get_frequency(clock_i2s1); + } else { + return 0; + } +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + (void) ptr; + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif diff --git a/bsp/hpmicro/hpm6300evk/board/rtt_board.h b/bsp/hpmicro/hpm6300evk/board/rtt_board.h index 16f539bc628..e2b4ae674cf 100644 --- a/bsp/hpmicro/hpm6300evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6300evk/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,8 +10,10 @@ #include "hpm_common.h" #include "hpm_soc.h" #include +#include "board.h" /* gpio section */ +#define APP_LED0 (0U) #define APP_LED0_PIN_NUM GET_PIN(A, 7) #define APP_LED_ON (0) #define APP_LED_OFF (1) @@ -21,6 +23,12 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* CAN section */ #define BOARD_CAN_NAME "can0" #define BOARD_CAN_HWFILTER_INDEX (0U) @@ -29,10 +37,27 @@ #define BOARD_UART_NAME "uart2" #define BOARD_UART_RX_BUFFER_SIZE BSP_UART2_RX_BUFSIZE +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + #define BOARD_SD_NAME "sd0" #define IRQn_PendSV IRQn_DEBUG_0 +#define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (1U) +#define BOARD_ENET0_PHY_RST_TIME (30) + +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif + +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + /*************************************************************** * * RT-Thread related definitions diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.h b/bsp/hpmicro/hpm6300evk/rtconfig.h index 82fd86d36ef..c01f4bb4774 100644 --- a/bsp/hpmicro/hpm6300evk/rtconfig.h +++ b/bsp/hpmicro/hpm6300evk/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -75,7 +75,8 @@ #define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -104,6 +105,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -136,8 +139,8 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE #define RT_USING_RTC #define RT_USING_PIN /* end of Device Drivers */ @@ -301,6 +304,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -380,16 +397,21 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM6300_SERIES /* Hardware Drivers Config */ -#define SOC_HPM6000 +#define SOC_HPM6300 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm6300evk/rtconfig.py b/bsp/hpmicro/hpm6300evk/rtconfig.py index 5ef6eea2846..3c13aac2fe3 100644 --- a/bsp/hpmicro/hpm6300evk/rtconfig.py +++ b/bsp/hpmicro/hpm6300evk/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c b/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c index b0bab335d52..1928adaf580 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/startup.c @@ -1,128 +1,135 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt - */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S index fdc2052aa31..350628abebe 100644 --- a/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6300evk/startup/HPM6360/toolchains/gcc/start.S @@ -69,7 +69,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6750evk/.config b/bsp/hpmicro/hpm6750evk/.config index 307c971666f..f1284da1f32 100644 --- a/bsp/hpmicro/hpm6750evk/.config +++ b/bsp/hpmicro/hpm6750evk/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -199,6 +197,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -225,10 +224,11 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set @@ -377,6 +377,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -484,6 +485,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -573,6 +575,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -618,6 +621,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -711,6 +715,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -792,6 +797,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -834,6 +840,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -847,6 +857,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1018,6 +1053,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1367,6 +1403,8 @@ CONFIG_SOC_HPM6000=y CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 # CONFIG_BSP_USING_UART6 is not set # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set @@ -1381,7 +1419,7 @@ CONFIG_BSP_USING_UART0=y # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_FEMC is not set -# CONFIG_INIT_EXT_RAM_FOR_DATA is not set +CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_XPI_FLASH is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_DAO is not set diff --git a/bsp/hpmicro/hpm6750evk/SConstruct b/bsp/hpmicro/hpm6750evk/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6750evk/SConstruct +++ b/bsp/hpmicro/hpm6750evk/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6750evk/board/SConscript b/bsp/hpmicro/hpm6750evk/board/SConscript index 2124e479bc9..37744fa2ebc 100644 --- a/bsp/hpmicro/hpm6750evk/board/SConscript +++ b/bsp/hpmicro/hpm6750evk/board/SConscript @@ -8,6 +8,7 @@ src = Split(""" rtt_board.c pinmux.c fal_flash_port.c + cherryusb_port.c hpm_sgtl5000.c """) diff --git a/bsp/hpmicro/hpm6750evk/board/board.c b/bsp/hpmicro/hpm6750evk/board/board.c index a7e027bc700..daa8d8b45f7 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.c +++ b/bsp/hpmicro/hpm6750evk/board/board.c @@ -23,9 +23,10 @@ #include "hpm_pllctl_drv.h" #include "hpm_enet_drv.h" #include "hpm_pcfg_drv.h" - -static board_timer_cb timer_cb; -static bool invert_led_level; +#include +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT +#include "hpm_enet_phy_common.h" +#endif /** * @brief FLASH configuration option definitions: @@ -81,11 +82,11 @@ static bool invert_led_level; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x1000, 0x0}; +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000007, 0xE, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -99,8 +100,6 @@ void board_init_console(void) And a uart rx dma request will be generated by default uart fifo dma trigger level. */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -136,11 +135,6 @@ void board_print_clock_freq(void) printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); - printf("display:\t %luHz\n", clock_get_frequency(clock_display)); - printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); - printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); - printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); - printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); printf("==============================\n"); } @@ -151,11 +145,6 @@ void board_init_uart(UART_Type *ptr) board_init_uart_clock(ptr); } -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ -} - void board_print_banner(void) { const uint8_t banner[] = {"\n\ @@ -177,10 +166,7 @@ void board_print_banner(void) static void board_turnoff_rgb_led(void) { - uint8_t p11_stat; - uint8_t p12_stat; - uint8_t p13_stat; - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(BOARD_LED_OFF_LEVEL); HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; @@ -188,23 +174,6 @@ static void board_turnoff_rgb_led(void) HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; - - p11_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 11); - p12_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12); - p13_stat = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 13); - - invert_led_level = false; - /* - * check led gpio level - */ - if ((p11_stat & p12_stat & p13_stat) == 0) { - /* Rev B */ - invert_led_level = true; - pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); - HPM_IOC->PAD[IOC_PAD_PB11].PAD_CTL = pad_ctl; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = pad_ctl; - HPM_IOC->PAD[IOC_PAD_PB13].PAD_CTL = pad_ctl; - } } void board_ungate_mchtmr_at_lp_mode(void) @@ -219,7 +188,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -230,19 +198,21 @@ void board_init(void) void board_init_core1(void) { + clock_update_core_clock(); board_init_console(); board_init_pmp(); } void board_init_sdram_pins(void) { - init_sdram_pins(); + init_femc_pins(); } uint32_t board_init_femc_clock(void) { + clock_add_to_group(clock_femc, 0); + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ - /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ return clock_get_frequency(clock_femc); } @@ -250,10 +220,9 @@ uint32_t board_init_femc_clock(void) uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 - static void set_reset_pin_level_tm070rdh13(uint8_t level) { - gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, level); + gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, level); } static void set_backlight_tm070rdh13(uint16_t percent) @@ -265,8 +234,12 @@ void board_init_lcd_rgb_tm070rdh13(void) { init_lcd_pins(BOARD_LCD_BASE); + gpio_set_pin_output(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN); + gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 0); + gpio_write_pin(BOARD_LCD_POWER_EN_GPIO_BASE, BOARD_LCD_POWER_EN_GPIO_INDEX, BOARD_LCD_POWER_EN_GPIO_PIN, 1); + gpio_set_pin_output(BOARD_LCD_BACKLIGHT_GPIO_BASE, BOARD_LCD_BACKLIGHT_GPIO_INDEX, BOARD_LCD_BACKLIGHT_GPIO_PIN); - gpio_set_pin_output(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN); + gpio_set_pin_output(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN); hpm_panel_hw_interface_t hw_if = {0}; hpm_panel_t *panel = hpm_panel_find_device_default(); @@ -285,11 +258,9 @@ void board_init_lcd_rgb_tm070rdh13(void) hpm_panel_init(panel); hpm_panel_power_on(panel); } - #endif #ifdef CONFIG_HPM_PANEL - uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) { clock_add_to_group(clock_name, 0); @@ -348,6 +319,9 @@ void board_delay_us(uint32_t us) clock_cpu_delay_us(us); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -355,7 +329,6 @@ void board_timer_isr(void) timer_cb(); } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); void board_timer_create(uint32_t ms, board_timer_cb cb) { @@ -375,6 +348,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -408,28 +382,43 @@ void board_i2c_bus_clear(I2C_Type *ptr) } } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; hpm_stat_t stat; uint32_t freq; - i2c_config_t config; + freq = board_init_i2c_clock(ptr); board_i2c_bus_clear(ptr); - init_i2c_pins(ptr); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); - stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } @@ -438,61 +427,28 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; - clock_name_t clock_name = clock_uart0; - bool need_init_clock = true; if (ptr == HPM_UART0) { - clock_name = clock_uart0; - } else if (ptr == HPM_UART1) { - clock_name = clock_uart1; - } else if (ptr == HPM_UART2) { - clock_name = clock_uart2; - } else if (ptr == HPM_UART3) { - clock_name = clock_uart3; - } else if (ptr == HPM_UART4) { - clock_name = clock_uart4; - } else if (ptr == HPM_UART5) { - clock_name = clock_uart5; + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART6) { - clock_name = clock_uart6; - } else if (ptr == HPM_UART7) { - clock_name = clock_uart7; - } else if (ptr == HPM_UART8) { - clock_name = clock_uart8; - } else if (ptr == HPM_UART9) { - clock_name = clock_uart9; - } else if (ptr == HPM_UART10) { - clock_name = clock_uart10; - } else if (ptr == HPM_UART11) { - clock_name = clock_uart11; - } else if (ptr == HPM_UART12) { - clock_name = clock_uart12; + clock_add_to_group(clock_uart6, 0); + freq = clock_get_frequency(clock_uart6); } else if (ptr == HPM_UART13) { - clock_name = clock_uart13; + clock_add_to_group(clock_uart13, 0); + freq = clock_get_frequency(clock_uart13); } else if (ptr == HPM_UART14) { - clock_name = clock_uart14; - } else if (ptr == HPM_UART15) { - clock_name = clock_uart15; + clock_add_to_group(clock_uart14, 0); + freq = clock_get_frequency(clock_uart14); } else { - /* Unsupported instance */ - need_init_clock = false; - } - - if (need_init_clock) { - clock_set_source_divider(clock_name, clk_src_osc24m, 1); - clock_add_to_group(clock_name, 0); - freq = clock_get_frequency(clock_name); + /* Not supported */ } - return freq; } uint32_t board_init_spi_clock(SPI_Type *ptr) { if (ptr == HPM_SPI2) { - /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */ - return clock_get_frequency(clock_spi2); } return 0; @@ -515,12 +471,7 @@ void board_init_cap_touch(void) void board_init_gpio_pins(void) { - uint8_t led_pin_pull_selsect; - HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - - led_pin_pull_selsect = gpio_read_pin(BOARD_G_GPIO_CTRL, GPIO_DI_GPIOB, 12); - init_gpio_pins(led_pin_pull_selsect); + init_gpio_pins(); } void board_init_spi_pins(SPI_Type *ptr) @@ -542,20 +493,12 @@ void board_write_spi_cs(uint32_t pin, uint8_t state) uint8_t board_get_led_pwm_off_level(void) { - if (invert_led_level) { - return BOARD_LED_ON_LEVEL; - } else { - return BOARD_LED_OFF_LEVEL; - } + return BOARD_LED_OFF_LEVEL; } uint8_t board_get_led_gpio_off_level(void) { - if (invert_led_level) { - return BOARD_LED_ON_LEVEL; - } else { - return BOARD_LED_OFF_LEVEL; - } + return BOARD_LED_OFF_LEVEL; } void board_init_led_pins(void) @@ -571,7 +514,7 @@ void board_led_toggle(void) { #ifdef BOARD_LED_TOGGLE_RGB static uint8_t i; - gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, invert_led_level ? ((1 << i) << BOARD_R_GPIO_PIN) : ((7 & ~(1 << i)) << BOARD_R_GPIO_PIN)); + gpio_write_port(BOARD_R_GPIO_CTRL, BOARD_R_GPIO_INDEX, (7 & (1 << i)) << BOARD_R_GPIO_PIN); i++; i = i % 3; #else @@ -597,24 +540,12 @@ void board_write_cam_rst(uint8_t state) } -void board_init_usb_pins(void) +void board_init_usb(USB_Type *ptr) { - /* set pull-up for USBx OC pins and ID pins */ - init_usb_pins(); + clock_name_t usb_clk = (ptr == HPM_USB0) ? clock_usb0 : clock_usb1; - /* configure USBx ID pins as input function */ - gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); - gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN); - - /* configure USBx OC Flag pins as input function */ - gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); - gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; + init_usb_pins(ptr); + clock_add_to_group(usb_clk, 0); } void board_init_pmp(void) @@ -656,96 +587,43 @@ void board_init_clock(void) sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); } - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_femc, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_gptmr4, 0); - clock_add_to_group(clock_gptmr5, 0); - clock_add_to_group(clock_gptmr6, 0); - clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_display, 0); - clock_add_to_group(clock_sdxc0, 0); - clock_add_to_group(clock_sdxc1, 0); - clock_add_to_group(clock_camera0, 0); - clock_add_to_group(clock_camera1, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_eth1, 0); - clock_add_to_group(clock_sdp, 0); - clock_add_to_group(clock_xdma, 0); clock_add_to_group(clock_ram0, 0); clock_add_to_group(clock_ram1, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_usb1, 0); - clock_add_to_group(clock_jpeg, 0); - clock_add_to_group(clock_pdma, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); clock_add_to_group(clock_mot0, 0); clock_add_to_group(clock_mot1, 0); clock_add_to_group(clock_mot2, 0); clock_add_to_group(clock_mot3, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_dao, 0); clock_add_to_group(clock_synt, 0); - clock_add_to_group(clock_lmm0, 0); - clock_add_to_group(clock_lmm1, 0); - clock_add_to_group(clock_pdm, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - clock_add_to_group(clock_adc3, 0); - - clock_add_to_group(clock_i2s0, 0); - clock_add_to_group(clock_i2s1, 0); - clock_add_to_group(clock_i2s2, 0); - clock_add_to_group(clock_i2s3, 0); + clock_add_to_group(clock_ptpc, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Add the CPU1 clock to Group1 */ + /* Add clocks to Group1 */ + clock_add_to_group(clock_cpu1, 1); clock_add_to_group(clock_mchtmr1, 1); - clock_add_to_group(clock_mbx1, 1); /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); - /* Bump up DCDC voltage to 1200mv */ - pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { - printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); + printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); while (1) { } } @@ -765,10 +643,12 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) if (ptr == HPM_CAM0) { /* Configure camera clock to 24MHz */ clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera0, 0); freq = clock_get_frequency(clock_camera0); } else if (ptr == HPM_CAM1) { /* Configure camera clock to 24MHz */ clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera1, 0); freq = clock_get_frequency(clock_camera1); } else { /* Invalid camera instance */ @@ -776,22 +656,11 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) return freq; } -uint32_t board_init_lcd_clock(void) -{ - uint32_t freq; - clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 59.4MHz */ - clock_set_source_divider(clock_display, (clk_src_t) clock_source_pll4_clk0, 10U); - freq = clock_get_frequency(clock_display); - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + board_config_i2s_clock(DAO_I2S, 48000); return clock_get_frequency(clock_dao); } @@ -800,8 +669,7 @@ uint32_t board_init_pdm_clock(void) { clock_add_to_group(clock_pdm, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + board_config_i2s_clock(PDM_I2S, 16000); return clock_get_frequency(clock_pdm); } @@ -816,32 +684,6 @@ void board_init_i2s_pins(I2S_Type *ptr) init_i2s_pins(ptr); } -uint32_t board_init_i2s_clock(I2S_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_I2S0) { - clock_add_to_group(clock_i2s0, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - - freq = clock_get_frequency(clock_i2s0); - } else if (ptr == HPM_I2S1) { - clock_add_to_group(clock_i2s1, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); - - freq = clock_get_frequency(clock_i2s1); - } else { - ; - } - - return freq; -} - -/* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { uint32_t freq = 0; @@ -881,12 +723,12 @@ void board_init_adc16_pins(void) init_adc16_pins(); } -uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -894,9 +736,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -904,9 +747,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc1, clk_adc_src_ana1); clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); - } else if (ptr == HPM_ADC2) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); } else { @@ -914,18 +758,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc2, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc2, 0); freq = clock_get_frequency(clock_adc2); - } - - return freq; -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) -{ - uint32_t freq = 0; - - if (ptr == HPM_ADC3) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC3) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); } else { @@ -933,13 +769,24 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc3, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); } - + clock_add_to_group(clock_adc3, 0); freq = clock_get_frequency(clock_adc3); } return freq; } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + void board_init_can(CAN_Type *ptr) { init_can_pins(ptr); @@ -951,18 +798,22 @@ uint32_t board_init_can_clock(CAN_Type *ptr) if (ptr == HPM_CAN0) { /* Set the CAN0 peripheral clock to 80MHz */ clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can0, 0); freq = clock_get_frequency(clock_can0); } else if (ptr == HPM_CAN1) { /* Set the CAN1 peripheral clock to 80MHz */ clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can1, 0); freq = clock_get_frequency(clock_can1); } else if (ptr == HPM_CAN2) { /* Set the CAN2 peripheral clock to 80MHz */ clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can2, 0); freq = clock_get_frequency(clock_can2); } else if (ptr == HPM_CAN3) { /* Set the CAN3 peripheral clock to 80MHz */ clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can3, 0); freq = clock_get_frequency(clock_can3); } else { /* Invalid CAN instance */ @@ -970,91 +821,18 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } -uint32_t board_init_pwm_clock(PWM_Type *ptr) -{ - uint32_t freq = 0; - if (ptr == HPM_PWM0) { - clock_add_to_group(clock_mot0, 0); - freq = clock_get_frequency(clock_mot0); - } else if (ptr == HPM_PWM1) { - clock_add_to_group(clock_mot1, 0); - freq = clock_get_frequency(clock_mot1); - } else if (ptr == HPM_PWM2) { - clock_add_to_group(clock_mot2, 0); - freq = clock_get_frequency(clock_mot2); - } else if (ptr == HPM_PWM3) { - clock_add_to_group(clock_mot3, 0); - freq = clock_get_frequency(clock_mot3); - } else { - - } - return freq; -} - -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr3); - } - else if (ptr == HPM_GPTMR4) { - clock_add_to_group(clock_gptmr4, 0); - clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr4); - } - else if (ptr == HPM_GPTMR5) { - clock_add_to_group(clock_gptmr5, 0); - clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr5); - } - else if (ptr == HPM_GPTMR6) { - clock_add_to_group(clock_gptmr6, 0); - clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr6); - } - else if (ptr == HPM_GPTMR7) { - clock_add_to_group(clock_gptmr7, 0); - clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr7); - } - else { - /* Invalid instance */ - } - return freq; -} - - +#ifdef INIT_EXT_RAM_FOR_DATA /* * this function will be called during startup to initialize external memory for data use */ void _init_ext_ram(void) { uint32_t femc_clk_in_hz; - clock_add_to_group(clock_femc, 0); - board_init_sdram_pins(); - femc_clk_in_hz = board_init_femc_clock(); - femc_config_t config = {0}; femc_sdram_config_t sdram_config = {0}; + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); femc_default_config(HPM_FEMC, &config); femc_init(HPM_FEMC, &config); @@ -1064,7 +842,7 @@ void _init_ext_ram(void) sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS; sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ @@ -1087,22 +865,14 @@ void _init_ext_ram(void) femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } - - -void board_sd_power_switch(SDXC_Type *ptr, bool on_off) -{ - /* This feature is not supported on current board */ -} - +#endif uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { - if (ptr != HPM_SDXC1) { - break; - } clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + clock_add_to_group(sdxc_clk, 0); sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); /* Configure the clock below 400KHz for the identification state */ @@ -1132,6 +902,12 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver if (need_inverse) { sdxc_enable_inverse_clock(ptr, true); } + + hpm_stat_t status = clock_wait_source_stable(sdxc_clk); + if (status != status_success) { + break; + } + sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -1232,9 +1008,11 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { /* set clock source */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ } else if (ptr == HPM_ENET1) { + clock_add_to_group(clock_ptp1, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ } else { @@ -1246,21 +1024,20 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { + clock_name_t eth_clk = (ptr == HPM_ENET0) ? clock_eth0 : clock_eth1; + /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET1) { - if (internal) { - /* set pll output frequency at 1GHz */ - if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { - /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */ - pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); - /* set eth clock frequency at 50MHz for enet0 */ - clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5); - } else { - return status_fail; - } + clock_add_to_group(eth_clk, BOARD_RUNNING_CORE & 0x1); + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 */ + pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(eth_clk, clk_src_pll2_clk1, 5); + } else { + return status_fail; } - } else { - return status_invalid_argument; } enet_rmii_enable_clock(ptr, internal); @@ -1271,6 +1048,7 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); } @@ -1347,6 +1125,12 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +void board_init_enet_pps_capture_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_capture_pins(); +} + #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT hpm_stat_t board_init_multiple_enet_pins(void) @@ -1440,3 +1224,50 @@ void board_init_dao_pins(void) { init_dao_pins(); } + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr4); + } else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr5); + } else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr6); + } else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr7); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} + diff --git a/bsp/hpmicro/hpm6750evk/board/board.h b/bsp/hpmicro/hpm6750evk/board/board.h index 35afc0bbec4..da43d3b139b 100644 --- a/bsp/hpmicro/hpm6750evk/board/board.h +++ b/bsp/hpmicro/hpm6750evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,8 +33,8 @@ /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART13 -#define BOARD_APP_UART_IRQ IRQn_UART13 +#define BOARD_APP_UART_BASE HPM_UART13 +#define BOARD_APP_UART_IRQ IRQn_UART13 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart13 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX @@ -67,6 +67,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -95,15 +97,15 @@ #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_UART_BASE HPM_UART13 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif @@ -113,13 +115,13 @@ #endif /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) -#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) #define BOARD_FLASH_SIZE (16 << 20) @@ -129,12 +131,15 @@ /* lcd section */ #define BOARD_LCD_BASE HPM_LCDC #define BOARD_LCD_IRQ IRQn_LCDC_D0 -#define BOARD_LCD_POWER_GPIO_BASE HPM_GPIO0 -#define BOARD_LCD_POWER_GPIO_INDEX GPIO_DO_GPIOB -#define BOARD_LCD_POWER_GPIO_PIN 16 +#define BOARD_LCD_RESET_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_RESET_GPIO_INDEX GPIO_DO_GPIOB +#define BOARD_LCD_RESET_GPIO_PIN 16 #define BOARD_LCD_BACKLIGHT_GPIO_BASE HPM_GPIO0 #define BOARD_LCD_BACKLIGHT_GPIO_INDEX GPIO_DO_GPIOB #define BOARD_LCD_BACKLIGHT_GPIO_PIN 10 +#define BOARD_LCD_POWER_EN_GPIO_BASE HPM_GPIO0 +#define BOARD_LCD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOZ +#define BOARD_LCD_POWER_EN_GPIO_PIN 00 /* i2c section */ #define BOARD_APP_I2C_BASE HPM_I2C0 @@ -168,17 +173,20 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR4 @@ -217,6 +225,7 @@ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ #define BOARD_APP_GPIO_PIN 2 +#define BOARD_BUTTON_PRESSED_VALUE 0 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ @@ -248,9 +257,9 @@ /* Flash section */ #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x0000000EU) /* lcd section */ @@ -265,13 +274,26 @@ #define BOARD_PDMA_BASE HPM_PDMA /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S0 -#define BOARD_APP_I2S_DATA_LINE (2U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s0 -#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX -#define BOARD_APP_I2S_IRQ IRQn_I2S0 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_TX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_RX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 + +#define BOARD_MIC_I2S HPM_I2S0 +#define BOARD_MIC_I2S_CLK_NAME clock_i2s0 +#define BOARD_MIC_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_MIC_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX + +#define BOARD_SPEAKER_I2S HPM_I2S1 +#define BOARD_SPEAKER_I2S_CLK_NAME clock_i2s1 +#define BOARD_SPEAKER_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_SPEAKER_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S1_TX + +/* pdm selection */ #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) @@ -281,6 +303,10 @@ #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_AUXI_SNAPSHOT HPM_ENET0 +#define BOARD_ENET_AUXI_SNAPSHOT_IDX enet_ptp_auxi_snapshot_trigger_1 +#define BOARD_ENET_AUXI_SNAPSHOT_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF @@ -343,18 +369,21 @@ #define BOARD_APP_ADC16_IRQn IRQn_ADC3 #define BOARD_APP_ADC16_CH_1 (2U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) - -#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI -#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A - -#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI -#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC12_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A @@ -377,6 +406,7 @@ /* SDXC section */ #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SDXC_IRQ IRQn_SDXC1 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) @@ -390,11 +420,14 @@ #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ #endif -#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) -#define BOARD_APP_EMMC_SUPPORT_3V3 (1) -#define BOARD_APP_EMMC_SUPPORT_1V8 (0) -#define BOARD_APP_EMMC_SUPPORT_4BIT (1) -#define BOARD_APP_EMMC_HOST_USING_IRQ (0) +#define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_EMMC_SDXC_IRQ IRQn_SDXC1 +#define BOARD_APP_EMMC_SUPPORT_3V3 (1) +#define BOARD_APP_EMMC_SUPPORT_1V8 (0) +#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_SUPPORT_POWER_SWITCH (1) +#define BOARD_APP_EMMC_POWER_SWITCH_USING_GPIO (1) +#define BOARD_APP_EMMC_HOST_USING_IRQ (0) /* USB section */ #define BOARD_USB0_ID_PORT (HPM_GPIO0) @@ -524,7 +557,7 @@ #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) -#define BOARD_CPU_FREQ (648000000UL) +#define BOARD_CPU_FREQ (816000000UL) #define BOARD_APP_DISPLAY_CLOCK clock_display @@ -562,6 +595,7 @@ void board_init_console(void); void board_init_core1(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); void board_lcd_backlight(bool is_on); @@ -587,7 +621,6 @@ void board_fpga_power_enable(void); void board_init_cam_pins(void); void board_write_cam_rst(uint8_t state); - /* Initialize SoC overall clocks */ void board_init_clock(void); @@ -597,24 +630,17 @@ uint32_t board_init_uart_clock(UART_Type *ptr); /* Initialize the CAM(camera) dot clock */ uint32_t board_init_cam_clock(CAM_Type *ptr); -/* Initialize the LCD pixel clock */ -uint32_t board_init_lcd_clock(void); - uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_acmp_clock(ACMP_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); -uint32_t board_init_pwm_clock(PWM_Type *ptr); - -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); hpm_stat_t board_set_audio_pll_clock(uint32_t freq); void board_init_i2s_pins(I2S_Type *ptr); -uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); @@ -625,11 +651,11 @@ void board_init_dao_pins(void); void board_init_adc12_pins(void); void board_init_adc16_pins(void); - -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_acmp_pins(void); +void board_init_usb(USB_Type *ptr); void board_init_enet_pps_pins(ENET_Type *ptr); +void board_init_enet_pps_capture_pins(ENET_Type *ptr); uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); @@ -679,9 +705,14 @@ uint8_t board_get_led_pwm_off_level(void); */ uint8_t board_get_led_gpio_off_level(void); -void board_init_trgm0_p6_pin(void); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); + +/* + * brief Initialize the clock reference pin. + */ +void board_init_clk_ref_pin(void); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6750evk/board/cherryusb_port.c b/bsp/hpmicro/hpm6750evk/board/cherryusb_port.c new file mode 100644 index 00000000000..d79bf933d0b --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/cherryusb_port.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/04/23 sakumisu first version + */ +#include +#include + +/* low level init here, this has implemented in cherryusb */ + +/* low level deinit here, this has implemented in cherryusb */ + +#ifdef RT_CHERRYUSB_DEVICE_TEMPLATE_MSC +int cherryusb_devinit(void) +{ + extern void msc_ram_init(uint8_t busid, uintptr_t reg_base); + + board_init_usb_pins(); + + msc_ram_init(0, HPM_USB0_BASE); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_devinit); +#endif + +#ifdef RT_CHERRYUSB_HOST +#include "usbh_core.h" + +int cherryusb_hostinit(void) +{ + board_init_usb_pins(); + + usbh_initialize(0, HPM_USB0_BASE); + return 0; +} +INIT_COMPONENT_EXPORT(cherryusb_hostinit); +#endif \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg index 601b6809518..1e5fd26f1d8 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-dual-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause # @@ -36,8 +36,15 @@ proc dmi_read_memory {addr} { } proc release_core1 {} { - # set start point for core1 - dmi_write_memory 0xF4002C08 0x20016284 + + set chip_rev [dmi_read_memory 0x2001FF00] + + if {$chip_rev != 0x56010100 } { + # set start point for core1 + dmi_write_memory 0xF4002C08 0x20016284 + } else { + dmi_write_memory 0xF4002C08 0x2001660c + } # set boot flag for core1 dmi_write_memory 0xF4002C0C 0xC1BEF1A9 @@ -46,16 +53,16 @@ proc release_core1 {} { dmi_write_memory 0xF4002C00 0x1000 } -$_TARGET0 configure -event examine-end { - release_core1 -} - set _TARGET1 $_CHIP.cpu1 target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 $_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 +$_TARGET1 configure -event examine-start { + release_core1 +} + $_TARGET1 configure -event reset-deassert-pre { - $::_TARGET1 arp_poll + $::_TARGET0 arp_poll release_core1 } diff --git a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg index 8e2bbe5f19d..f873527fb72 100644 --- a/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg +++ b/bsp/hpmicro/hpm6750evk/board/debug_scripts/openocd/soc/hpm6750-single-core.cfg @@ -1,4 +1,4 @@ -# Copyright 2021 hpmicro +# Copyright (c) 2021 HPMicro # SPDX-License-Identifier: BSD-3-Clause set _CHIP hpm6750 diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld new file mode 100644 index 00000000000..2f39e2409d8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld @@ -0,0 +1,357 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 768K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + /* hpm_sdk drivers */ + KEEP(*hpm_sdxc_drv*.o (.text .text* .rodata .rodata*)) + + /* WHD related */ + KEEP(*whd_bus*.o (.text .text* .rodata .rodata*)) + KEEP(*whd_sdpcm*.o (.text .text* .rodata .rodata*)) + KEEP(*whd_thread*.o (.text .text* .rodata .rodata*)) + + /* LWIP */ + KEEP(*lwip*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 78% rename from bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld index 42ee5b0612e..8b4f6137da8 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -86,12 +89,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -116,12 +119,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -155,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -167,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -187,22 +208,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -230,10 +255,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -254,7 +279,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -279,7 +306,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -290,8 +318,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -310,7 +341,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt_enet.ld similarity index 80% rename from bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt_enet.ld index f1d2bf25ac5..bcd6c6e1252 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -106,16 +109,12 @@ SECTIONS KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -173,6 +172,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -181,6 +194,20 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -201,22 +228,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -244,10 +275,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -268,7 +299,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -293,7 +326,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -304,8 +338,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -324,7 +361,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_sdram_rtt.ld similarity index 77% rename from bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld rename to bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_sdram_rtt.ld index 9ac0b042499..8618b40e550 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/flash_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -82,16 +85,16 @@ SECTIONS KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - + /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -141,7 +144,6 @@ SECTIONS /* RT-Thread related sections - end */ - /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; @@ -150,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -162,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -177,6 +203,7 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); __tbss_start__ = .; @@ -186,17 +213,20 @@ SECTIONS __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -224,10 +254,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -248,9 +278,12 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -261,8 +294,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 68% rename from bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld index 97483a9e302..e03cd86e664 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,10 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K + AXI_SRAM1 (w) : ORIGIN = 0x01100000, LENGTH = 768K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -87,63 +88,53 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); + . = ALIGN(8); } > AXI_SRAM + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > AXI_SRAM + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > AXI_SRAM + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > AXI_SRAM + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - .tdata : AT(etext) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - .data : AT(etext + __tdata_end__ - __tdata_start__) { - . = ALIGN(8); + /* NOTE: + Please keep in mind that the load section for rw data is after .text section + Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section + and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: + 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ + 2. the generated binary file will be larger because the space occupied by + NOLOAD sections will be filled + */ + __data_load_addr__ = __etext; + .data : AT(__data_load_addr__) { __data_start__ = .; + . = ALIGN(8); __global_pointer$ = . + 0x800; *(.data) *(.data*) @@ -169,10 +160,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -193,17 +184,19 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > DLM + } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { PROVIDE(__ramfunc_start__ = .); + . = ALIGN(8); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -211,11 +204,64 @@ SECTIONS . = ALIGN(8); } > NONCACHEABLE_RAM + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + /* Note: Place all NOLOAD sections together */ + .tbss(NOLOAD) : { + . += SIZEOF(.noncacheable.init); + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM1 + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM1 + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -238,11 +284,11 @@ SECTIONS PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); PROVIDE (__rt_rvstack = .); - } > DLM + } > AXI_SRAM1 .framebuffer (NOLOAD) : { KEEP(*(.framebuffer)) - } > AXI_SRAM + } > AXI_SRAM1 .heap (NOLOAD) : { . = ALIGN(8); @@ -250,12 +296,11 @@ SECTIONS . += HEAP_SIZE; __heap_end__ = .; - } > AXI_SRAM + } > AXI_SRAM1 .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_sdram_rtt.ld similarity index 70% rename from bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld rename to bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_sdram_rtt.ld index 0458805797b..fc810f781dc 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk/board/linker_scripts/gcc/ram_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -94,55 +94,44 @@ SECTIONS KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); } > AXI_SRAM .rel : { KEEP(*(.rel*)) } > AXI_SRAM + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > AXI_SRAM + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > AXI_SRAM + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - .tdata : AT(etext) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - .data : AT(etext + __tdata_end__ - __tdata_start__) { + /* NOTE: + Please keep in mind that the load section for rw data is after .text section + Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section + and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: + 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ + 2. the generated binary file will be larger because the space occupied by + NOLOAD sections will be filled + */ + __data_load_addr__ = __etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -170,10 +159,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -196,7 +185,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -204,7 +194,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -212,11 +203,63 @@ SECTIONS . = ALIGN(8); } > NONCACHEABLE_RAM + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + /* Note: Place all NOLOAD sections together */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.c b/bsp/hpmicro/hpm6750evk/board/pinmux.c index 8056ca54327..096b1c8a4de 100644 --- a/bsp/hpmicro/hpm6750evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -142,7 +142,7 @@ void init_i2c_pins(I2C_Type *ptr) } } -void init_sdram_pins(void) +void init_femc_pins(void) { HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -204,65 +204,15 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #OE */ } -void init_sram_pins(void) -{ - /* Non-MUX */ /* MUX */ - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ - HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ - HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ - HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ - HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ - HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ - HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ - HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ - HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ - - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ - - HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ - HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ -} - -void init_gpio_pins(uint8_t led_pull_select) +void init_gpio_pins(void) { HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; - HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(led_pull_select); + HPM_IOC->PAD[IOC_PAD_PB12].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); #ifdef USING_GPIO0_FOR_GPIOZ HPM_IOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_GPIO_Z_02; @@ -279,6 +229,11 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE27].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } } @@ -289,15 +244,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } -} -void init_pins(void) -{ -#ifdef BOARD_CONSOLE_UART_BASE - init_uart_pins(BOARD_CONSOLE_UART_BASE); -#endif - init_sdram_pins(); + HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE27].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + } } void init_gptmr_pins(GPTMR_Type *ptr) @@ -311,11 +263,11 @@ void init_gptmr_pins(GPTMR_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; } if (ptr == HPM_GPTMR5) { - /* TMR5 capture 2 */ + /* TMR5 compare 2 */ HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; trgm_enable_io_output(HPM_TRGM2, 1 << 10); - /* TMR5 capture 3 */ + /* TMR5 compare 3 */ HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; trgm_enable_io_output(HPM_TRGM2, 1 << 11); @@ -497,23 +449,15 @@ void init_adc_bldc_pins(void) HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - /* USB0_ID */ - HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; - HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB0_OC */ - HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; - HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB1_ID */ - HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07; - HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB1_OC */ - HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05; - HPM_IOC->PAD[IOC_PAD_PF05].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + if (ptr == HPM_USB0) { + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_USB0_ID; + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_USB0_OC; + } else if (ptr == HPM_USB1) { + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_USB1_ID; + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_USB1_OC; + } } void init_can_pins(CAN_Type *ptr) @@ -567,7 +511,7 @@ void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) /* SDXC1.DATA0 */ HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - if ((width == 4)) { + if (width == 4) { /* SDXC1.DATA1 */ HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; diff --git a/bsp/hpmicro/hpm6750evk/board/pinmux.h b/bsp/hpmicro/hpm6750evk/board/pinmux.h index f90130b2910..183ad517630 100644 --- a/bsp/hpmicro/hpm6750evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evk/board/pinmux.h @@ -16,9 +16,8 @@ void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); -void init_sdram_pins(void); -void init_sram_pins(void); -void init_gpio_pins(uint8_t pin_stat); +void init_femc_pins(void); +void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); void init_pins(void); @@ -34,17 +33,13 @@ void init_butn_pins(void); void init_acmp_pins(void); void init_enet_pins(ENET_Type *ptr); void init_pwm_pins(PWM_Type *ptr); -void init_adc12_pins(void); -void init_adc16_pins(void); -void init_usb_pins(void); -void init_can_pins(CAN_Type *ptr); void init_sdxc_cmd_pin(SDXC_Type *ptr, bool open_drain, bool is_1v8); void init_sdxc_cd_pin(SDXC_Type *ptr, bool as_gpio); void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio); void init_adc12_pins(void); void init_adc16_pins(void); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); @@ -52,7 +47,11 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); void init_enet_pps_pins(void); +void init_enet_pps_capture_pins(void); void init_tamper_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pin(void); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.c b/bsp/hpmicro/hpm6750evk/board/rtt_board.c index 42f3e9a8b7c..ea3693f1410 100644 --- a/bsp/hpmicro/hpm6750evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -15,20 +15,13 @@ #include #include #include "hpm_dma_mgr.h" +#include "hpm_l1c_drv.h" #include "hpm_mchtmr_drv.h" extern int rt_hw_uart_init(void); void os_tick_config(void); void rtt_board_init(void); -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void os_tick_config(void) { sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); @@ -37,8 +30,14 @@ void os_tick_config(void) enable_mchtmr_irq(); } +void rtt_os_tick_clock(void) +{ + clock_add_to_group(clock_mchtmr0, 0); +} + void rtt_board_init(void) { + rtt_os_tick_clock(); board_init_clock(); board_init_console(); board_init_pmp(); @@ -60,6 +59,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); @@ -98,19 +98,12 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); -} - -ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) -{ - HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - - rt_tick_increase(); + board_init_usb(HPM_USB0); } void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->RESET_HOT &= ~(1UL << 31); HPM_PPOR->RESET_COLD |= (1UL << 31); @@ -121,3 +114,150 @@ void rt_hw_cpu_reset(void) } MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +uint32_t rtt_board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc2, 0); + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC3) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc3, 0); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) + +#ifdef HPM_USB1_BASE +extern void hpm_isr_usb1(void); +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, hpm_isr_usb1) +#endif +#endif + + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/board/rtt_board.h b/bsp/hpmicro/hpm6750evk/board/rtt_board.h index 67fa97bd9c9..9b0790fe14a 100644 --- a/bsp/hpmicro/hpm6750evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evk/board/rtt_board.h @@ -11,6 +11,9 @@ #include "hpm_soc.h" /* gpio section */ +#define APP_LED0 (0U) +#define APP_LED1 (1U) +#define APP_LED2 (2U) #define APP_LED0_GPIO_CTRL HPM_GPIO0 #define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB #define APP_LED0_GPIO_PIN 11 @@ -28,6 +31,12 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* SPI WIFI section */ #define RW007_RST_PIN (IOC_PAD_PE02) #define RW007_INT_BUSY_PIN (IOC_PAD_PE01) @@ -58,6 +67,34 @@ #define IRQn_PendSV IRQn_DEBUG_0 +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (21U) +#endif +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET1_RST_GPIO_PIN (26U) + +#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET1_INT_REF_CLK (1U) +#define BOARD_ENET1_PHY_RST_TIME (30) + +#if BOARD_ENET1_INF +#define BOARD_ENET1_TX_DLY (0U) +#define BOARD_ENET1_RX_DLY (0U) +#endif + +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +#endif + /*************************************************************** * * RT-Thread related definitions diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.h b/bsp/hpmicro/hpm6750evk/rtconfig.h index 82fd86d36ef..2f064c82439 100644 --- a/bsp/hpmicro/hpm6750evk/rtconfig.h +++ b/bsp/hpmicro/hpm6750evk/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -76,6 +76,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -136,8 +137,8 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE #define RT_USING_RTC #define RT_USING_PIN /* end of Device Drivers */ @@ -301,6 +302,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -390,6 +405,9 @@ #define BSP_USING_GPIO #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm6750evk/rtconfig.py b/bsp/hpmicro/hpm6750evk/rtconfig.py index 0f29ec05180..1a8d20c3c06 100644 --- a/bsp/hpmicro/hpm6750evk/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk/rtconfig.py @@ -3,6 +3,39 @@ import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c index b0bab335d52..4fc6914d566 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/startup.c @@ -1,128 +1,139 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + /* NOTE: Invalid I-Cache in case the I-Cache was filled with incorrect data during prefetch before copying the ram + * function code to its destination. */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + fencei(); + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S index 238e05b43bb..5ac683dbc27 100644 --- a/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evk/startup/HPM6750/toolchains/gcc/start.S @@ -75,7 +75,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6750evk2/.config b/bsp/hpmicro/hpm6750evk2/.config index 1bc1afc9c96..3716e7e6c15 100644 --- a/bsp/hpmicro/hpm6750evk2/.config +++ b/bsp/hpmicro/hpm6750evk2/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -242,10 +244,11 @@ CONFIG_RT_USING_SYSTEM_WORKQUEUE=y CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set @@ -263,9 +266,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set @@ -404,6 +405,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -511,6 +513,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -600,6 +603,7 @@ CONFIG_RT_USING_POSIX_POLL=y # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -645,6 +649,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -738,6 +743,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -819,6 +825,8 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -861,6 +869,10 @@ CONFIG_RT_USING_POSIX_POLL=y # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -874,6 +886,31 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1045,6 +1082,7 @@ CONFIG_RT_USING_POSIX_POLL=y # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1383,22 +1421,40 @@ CONFIG_RT_USING_POSIX_POLL=y # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM6700_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM6000=y +CONFIG_SOC_HPM6700=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_UART11 is not set +# CONFIG_BSP_USING_UART12 is not set # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_UART15 is not set # CONFIG_BSP_USING_SPI is not set -CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_SDXC is not set # CONFIG_BSP_USING_TOUCH is not set @@ -1407,8 +1463,8 @@ CONFIG_BSP_USING_RTC=y # CONFIG_BSP_USING_PDMA is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set -# CONFIG_BSP_USING_FEMC is not set -# CONFIG_INIT_EXT_RAM_FOR_DATA is not set +CONFIG_BSP_USING_FEMC=y +CONFIG_INIT_EXT_RAM_FOR_DATA=y # CONFIG_BSP_USING_XPI_FLASH is not set # CONFIG_BSP_USING_PWM is not set # CONFIG_BSP_USING_DAO is not set diff --git a/bsp/hpmicro/hpm6750evk2/SConstruct b/bsp/hpmicro/hpm6750evk2/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6750evk2/SConstruct +++ b/bsp/hpmicro/hpm6750evk2/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6750evk2/board/Kconfig b/bsp/hpmicro/hpm6750evk2/board/Kconfig index 653d57867a2..9f97bd4a7d3 100644 --- a/bsp/hpmicro/hpm6750evk2/board/Kconfig +++ b/bsp/hpmicro/hpm6750evk2/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6000 +config SOC_HPM6700 bool - select SOC_SERIES_HPM6000 + select SOC_HPM6700_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -15,11 +15,23 @@ config BSP_USING_ENET_PHY_RTL8201 bool default n +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -48,6 +60,145 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -71,6 +222,172 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART8 + bool "Enable UART8" + default n + if BSP_USING_UART8 + config BSP_UART8_RX_USING_DMA + bool "Enable UART8 RX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + default n + config BSP_UART8_TX_USING_DMA + bool "Enable UART8 TX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + default n + config BSP_UART8_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART8_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART8_IRQ_PRIORITY + int "UART8 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART9 + bool "Enable UART9" + default n + if BSP_USING_UART9 + config BSP_UART9_RX_USING_DMA + bool "Enable UART9 RX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + default n + config BSP_UART9_TX_USING_DMA + bool "Enable UART9 TX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + default n + config BSP_UART9_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART9_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART9_IRQ_PRIORITY + int "UART9 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_USING_DMA + bool "Enable UART10 RX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + default n + config BSP_UART10_TX_USING_DMA + bool "Enable UART10 TX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + default n + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART10_IRQ_PRIORITY + int "UART10 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART11 + bool "Enable UART11" + default n + if BSP_USING_UART11 + config BSP_UART11_RX_USING_DMA + bool "Enable UART11 RX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + default n + config BSP_UART11_TX_USING_DMA + bool "Enable UART11 TX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + default n + config BSP_UART11_RX_BUFSIZE + int "Set UART11 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART11_TX_BUFSIZE + int "Set UART11 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART11_IRQ_PRIORITY + int "UART11 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART12 + bool "Enable UART12" + default n + if BSP_USING_UART12 + config BSP_UART12_RX_USING_DMA + bool "Enable UART12 RX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + default n + config BSP_UART12_TX_USING_DMA + bool "Enable UART12 TX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + default n + config BSP_UART12_RX_BUFSIZE + int "Set UART12 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART12_TX_BUFSIZE + int "Set UART12 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART12_IRQ_PRIORITY + int "UART12 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART13 bool "Enable UART13" @@ -94,6 +411,10 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART13_IRQ_PRIORITY + int "UART13 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART14 bool "Enable UART14" @@ -118,6 +439,33 @@ menu "On-chip Peripheral Drivers" depends on RT_USING_SERIAL_V2 default 0 endif + menuconfig BSP_USING_UART15 + bool "Enable UART15" + default n + if BSP_USING_UART15 + config BSP_UART15_RX_USING_DMA + bool "Enable UART15 RX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + default n + config BSP_UART15_TX_USING_DMA + bool "Enable UART15 TX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + default n + config BSP_UART15_RX_BUFSIZE + int "Set UART15 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART15_TX_BUFSIZE + int "Set UART15 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART15_IRQ_PRIORITY + int "UART15 Interrupt Priority" + range 1 7 + default 1 + endif endif @@ -126,41 +474,140 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif config BSP_USING_SPI1 bool "Enable SPI1" - default y + default n if BSP_USING_SPI1 config BSP_SPI1_USING_DMA - bool "Enable SPI1 DMA" - default n + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice endif config BSP_USING_SPI2 bool "Enable SPI2" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice endif config BSP_USING_SPI3 bool "Enable SPI3" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + if BSP_USING_ETH config BSP_USING_ETH0 bool "Enable ETH0" @@ -177,11 +624,43 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC" default n select RT_USING_SDIO if BSP_USING_SDXC + select RT_USING_PIN if BSP_USING_SDXC if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" default n if BSP_USING_SDXC0 + config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC0_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC0_USE_NONCACHEABLE_BUFFER + config BSP_SDXC0_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC0_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + + config BSP_SDXC0_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT @@ -214,6 +693,36 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC1" default n if BSP_USING_SDXC1 + config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC1_USE_CACHEABLE_BUFFER + config BSP_SDXC1_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC1_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC1_USE_CACHEABLE_BUFFER + config BSP_SDXC1_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC1_USE_NONCACHEABLE_BUFFER + config BSP_SDXC1_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC1_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + config BSP_SDXC1_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 choice prompt "Select BUS_WIDTH" default BSP_SDXC1_BUS_WIDTH_4BIT @@ -245,8 +754,8 @@ menu "On-chip Peripheral Drivers" bool "Enable touch" default n if BSP_USING_TOUCH - config BSP_USING_TOUCH_GT911 - bool "Enable GT911" + config BSP_USING_TOUCH_GT9xx + bool "Enable GT9xx" default y config BSP_USING_TOUCH_FT5406 @@ -278,27 +787,78 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_HWTIMER if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR3 bool "Enable GPTMR3" default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR4 bool "Enable GPTMR4" default n + if BSP_USING_GPTMR4 + config BSP_GPTMR4_IRQ_PRIORITY + int "GPTMR4 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR5 bool "Enable GPTMR5" default n + if BSP_USING_GPTMR5 + config BSP_GPTMR5_IRQ_PRIORITY + int "GPTMR5 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR6 bool "Enable GPTMR6" default n + if BSP_USING_GPTMR6 + config BSP_GPTMR6_IRQ_PRIORITY + int "GPTMR6 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR7 bool "Enable GPTMR7" default n + if BSP_USING_GPTMR7 + config BSP_GPTMR7_IRQ_PRIORITY + int "GPTMR7 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -309,11 +869,51 @@ menu "On-chip Peripheral Drivers" config BSP_USING_I2C0 bool "Enable I2C0" default y - endif - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_FEMC @@ -332,6 +932,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n + select RT_USING_PWM if BSP_USING_PWM menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -362,18 +963,12 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n - select RT_USING_CHERRYUSB - select RT_CHERRYUSB_DEVICE - select RT_CHERRYUSB_DEVICE_SPEED_HS - select RT_CHERRYUSB_DEVICE_HPM config BSP_USING_USB_HOST bool "Enable USB Host" - default n select RT_USING_CACHE - select RT_USING_CHERRYUSB - select RT_CHERRYUSB_HOST - select RT_CHERRYUSB_HOST_EHCI_HPM + default n endif @@ -404,15 +999,39 @@ menu "On-chip Peripheral Drivers" config BSP_USING_CAN0 bool "Enable CAN0" default n + if BSP_USING_CAN0 + config BSP_CAN0_IRQ_PRIORITY + int "CAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN1 bool "Enable CAN1" default n + if BSP_USING_CAN1 + config BSP_CAN1_IRQ_PRIORITY + int "CAN1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN2 bool "Enable CAN2" default n + if BSP_USING_CAN2 + config BSP_CAN2_IRQ_PRIORITY + int "CAN2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN3 bool "Enable CAN3" default n + if BSP_USING_CAN3 + config BSP_CAN3_IRQ_PRIORITY + int "CAN3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC @@ -433,7 +1052,7 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC2 bool "Enable ADC2" default n - endif + endif menuconfig BSP_USING_ADC16 bool "Enable ADC16" default n @@ -442,7 +1061,7 @@ menu "On-chip Peripheral Drivers" bool "Enable ADC3" default n endif - endif + endif menuconfig BSP_USING_CAMERA bool "Enable camera" @@ -481,6 +1100,12 @@ menu "On-chip Peripheral Drivers" bool "Enable RTT LCD Driver" select BSP_USING_LCD default n + if BSP_USING_RTT_LCD_DRIVER + config BSP_RTT_LCD_IRQ_PRIORITY + int "RTT LCD Interrupt Priority" + range 1 7 + default 1 + endif endmenu endmenu diff --git a/bsp/hpmicro/hpm6750evk2/board/board.c b/bsp/hpmicro/hpm6750evk2/board/board.c index b7d31abde30..73fdf9f8666 100644 --- a/bsp/hpmicro/hpm6750evk2/board/board.c +++ b/bsp/hpmicro/hpm6750evk2/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024 HPMicro + * Copyright (c) 2022-2024 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -23,8 +23,10 @@ #include "hpm_pllctl_drv.h" #include "hpm_enet_drv.h" #include "hpm_pcfg_drv.h" - -static board_timer_cb timer_cb; +#include +#if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT +#include "hpm_enet_phy_common.h" +#endif /** * @brief FLASH configuration option definitions: @@ -80,11 +82,11 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000007, 0xE, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -98,8 +100,6 @@ void board_init_console(void) And a uart rx dma request will be generated by default uart fifo dma trigger level. */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -135,11 +135,6 @@ void board_print_clock_freq(void) printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); - printf("display:\t %luHz\n", clock_get_frequency(clock_display)); - printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); - printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); - printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); - printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); printf("==============================\n"); } @@ -150,11 +145,6 @@ void board_init_uart(UART_Type *ptr) board_init_uart_clock(ptr); } -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ -} - void board_print_banner(void) { const uint8_t banner[] = {"\n\ @@ -176,7 +166,7 @@ void board_print_banner(void) static void board_turnoff_rgb_led(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PE_SET(BOARD_LED_OFF_LEVEL); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(BOARD_LED_OFF_LEVEL); HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_GPIO_B_11; HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_GPIO_B_12; HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_GPIO_B_13; @@ -198,7 +188,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -209,19 +198,21 @@ void board_init(void) void board_init_core1(void) { + clock_update_core_clock(); board_init_console(); board_init_pmp(); } void board_init_sdram_pins(void) { - init_sdram_pins(); + init_femc_pins(); } uint32_t board_init_femc_clock(void) { + clock_add_to_group(clock_femc, 0); + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ - /* clock_set_source_divider(clock_femc, clk_src_pll1_clk1, 2U); [> 200Mhz <] */ return clock_get_frequency(clock_femc); } @@ -229,7 +220,6 @@ uint32_t board_init_femc_clock(void) uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 - static void set_reset_pin_level_tm070rdh13(uint8_t level) { gpio_write_pin(BOARD_LCD_RESET_GPIO_BASE, BOARD_LCD_RESET_GPIO_INDEX, BOARD_LCD_RESET_GPIO_PIN, level); @@ -268,11 +258,9 @@ void board_init_lcd_rgb_tm070rdh13(void) hpm_panel_init(panel); hpm_panel_power_on(panel); } - #endif #ifdef CONFIG_HPM_PANEL - uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) { clock_add_to_group(clock_name, 0); @@ -331,6 +319,9 @@ void board_delay_us(uint32_t us) clock_cpu_delay_us(us); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -338,7 +329,6 @@ void board_timer_isr(void) timer_cb(); } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); void board_timer_create(uint32_t ms, board_timer_cb cb) { @@ -358,6 +348,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -391,28 +382,43 @@ void board_i2c_bus_clear(I2C_Type *ptr) } } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; hpm_stat_t stat; uint32_t freq; - i2c_config_t config; + freq = board_init_i2c_clock(ptr); board_i2c_bus_clear(ptr); - init_i2c_pins(ptr); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); - stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t)BOARD_CAP_I2C_BASE); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } @@ -420,62 +426,29 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_uart_clock(UART_Type *ptr) { - uint32_t freq = 0; - clock_name_t clock_name = clock_uart0; - bool need_init_clock = true; + uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_name = clock_uart0; - } else if (ptr == HPM_UART1) { - clock_name = clock_uart1; - } else if (ptr == HPM_UART2) { - clock_name = clock_uart2; - } else if (ptr == HPM_UART3) { - clock_name = clock_uart3; - } else if (ptr == HPM_UART4) { - clock_name = clock_uart4; - } else if (ptr == HPM_UART5) { - clock_name = clock_uart5; + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART6) { - clock_name = clock_uart6; - } else if (ptr == HPM_UART7) { - clock_name = clock_uart7; - } else if (ptr == HPM_UART8) { - clock_name = clock_uart8; - } else if (ptr == HPM_UART9) { - clock_name = clock_uart9; - } else if (ptr == HPM_UART10) { - clock_name = clock_uart10; - } else if (ptr == HPM_UART11) { - clock_name = clock_uart11; - } else if (ptr == HPM_UART12) { - clock_name = clock_uart12; + clock_add_to_group(clock_uart6, 0); + freq = clock_get_frequency(clock_uart6); } else if (ptr == HPM_UART13) { - clock_name = clock_uart13; + clock_add_to_group(clock_uart13, 0); + freq = clock_get_frequency(clock_uart13); } else if (ptr == HPM_UART14) { - clock_name = clock_uart14; - } else if (ptr == HPM_UART15) { - clock_name = clock_uart15; + clock_add_to_group(clock_uart14, 0); + freq = clock_get_frequency(clock_uart14); } else { - /* Unsupported instance */ - need_init_clock = false; + /* Not supported */ } - - if (need_init_clock) { - clock_set_source_divider(clock_name, clk_src_osc24m, 1); - clock_add_to_group(clock_name, 0); - freq = clock_get_frequency(clock_name); - } - return freq; } uint32_t board_init_spi_clock(SPI_Type *ptr) { if (ptr == HPM_SPI2) { - /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); /* 80MHz */ - return clock_get_frequency(clock_spi2); } return 0; @@ -491,8 +464,8 @@ void board_init_cap_touch(void) gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); board_delay_ms(1); gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); - board_delay_ms(6); - gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + board_delay_ms(55); + gpio_set_pin_input(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); board_init_i2c(BOARD_CAP_I2C_BASE); } @@ -565,27 +538,14 @@ void board_init_cam_pins(void) void board_write_cam_rst(uint8_t state) { gpio_write_pin(BOARD_CAM_RST_GPIO_CTRL, BOARD_CAM_RST_GPIO_INDEX, BOARD_CAM_RST_GPIO_PIN, state); - } -void board_init_usb_pins(void) +void board_init_usb(USB_Type *ptr) { - /* set pull-up for USBx OC pins and ID pins */ - init_usb_pins(); - - /* configure USBx ID pins as input function */ - gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); - gpio_set_pin_input(BOARD_USB1_ID_PORT, BOARD_USB1_ID_GPIO_INDEX, BOARD_USB1_ID_GPIO_PIN); + clock_name_t usb_clk = (ptr == HPM_USB0) ? clock_usb0 : clock_usb1; - /* configure USBx OC Flag pins as input function */ - gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); - gpio_set_pin_input(BOARD_USB1_OC_PORT, BOARD_USB1_OC_GPIO_INDEX, BOARD_USB1_OC_GPIO_PIN); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; + init_usb_pins(ptr); + clock_add_to_group(usb_clk, 0); } void board_init_pmp(void) @@ -627,96 +587,43 @@ void board_init_clock(void) sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); } - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_femc, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_gptmr4, 0); - clock_add_to_group(clock_gptmr5, 0); - clock_add_to_group(clock_gptmr6, 0); - clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_display, 0); - clock_add_to_group(clock_sdxc0, 0); - clock_add_to_group(clock_sdxc1, 0); - clock_add_to_group(clock_camera0, 0); - clock_add_to_group(clock_camera1, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_eth1, 0); - clock_add_to_group(clock_sdp, 0); - clock_add_to_group(clock_xdma, 0); clock_add_to_group(clock_ram0, 0); clock_add_to_group(clock_ram1, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_usb1, 0); - clock_add_to_group(clock_jpeg, 0); - clock_add_to_group(clock_pdma, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); clock_add_to_group(clock_mot0, 0); clock_add_to_group(clock_mot1, 0); clock_add_to_group(clock_mot2, 0); clock_add_to_group(clock_mot3, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_dao, 0); clock_add_to_group(clock_synt, 0); - clock_add_to_group(clock_lmm0, 0); - clock_add_to_group(clock_lmm1, 0); - clock_add_to_group(clock_pdm, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - clock_add_to_group(clock_adc3, 0); - - clock_add_to_group(clock_i2s0, 0); - clock_add_to_group(clock_i2s1, 0); - clock_add_to_group(clock_i2s2, 0); - clock_add_to_group(clock_i2s3, 0); + clock_add_to_group(clock_ptpc, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Add the CPU1 clock to Group1 */ + /* Add clocks to Group1 */ + clock_add_to_group(clock_cpu1, 1); clock_add_to_group(clock_mchtmr1, 1); - clock_add_to_group(clock_mbx1, 1); /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); - /* Bump up DCDC voltage to 1200mv */ - pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { - printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); + printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); while (1) { } } @@ -736,10 +643,12 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) if (ptr == HPM_CAM0) { /* Configure camera clock to 24MHz */ clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera0, 0); freq = clock_get_frequency(clock_camera0); } else if (ptr == HPM_CAM1) { /* Configure camera clock to 24MHz */ clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera1, 0); freq = clock_get_frequency(clock_camera1); } else { /* Invalid camera instance */ @@ -747,22 +656,11 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) return freq; } -uint32_t board_init_lcd_clock(void) -{ - uint32_t freq; - clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 59.4MHz */ - clock_set_source_divider(clock_display, clk_src_pll4_clk0, 10U); - freq = clock_get_frequency(clock_display); - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + board_config_i2s_clock(DAO_I2S, 48000); return clock_get_frequency(clock_dao); } @@ -771,8 +669,7 @@ uint32_t board_init_pdm_clock(void) { clock_add_to_group(clock_pdm, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + board_config_i2s_clock(PDM_I2S, 16000); return clock_get_frequency(clock_pdm); } @@ -787,32 +684,6 @@ void board_init_i2s_pins(I2S_Type *ptr) init_i2s_pins(ptr); } -uint32_t board_init_i2s_clock(I2S_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_I2S0) { - clock_add_to_group(clock_i2s0, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - - freq = clock_get_frequency(clock_i2s0); - } else if (ptr == HPM_I2S1) { - clock_add_to_group(clock_i2s1, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); - - freq = clock_get_frequency(clock_i2s1); - } else { - ; - } - - return freq; -} - -/* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { uint32_t freq = 0; @@ -852,12 +723,12 @@ void board_init_adc16_pins(void) init_adc16_pins(); } -uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -865,9 +736,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -875,9 +747,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc1, clk_adc_src_ana1); clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); - } else if (ptr == HPM_ADC2) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); } else { @@ -885,18 +758,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc2, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc2, 0); freq = clock_get_frequency(clock_adc2); - } - - return freq; -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) -{ - uint32_t freq = 0; - - if (ptr == HPM_ADC3) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC3) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); } else { @@ -904,13 +769,24 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc3, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); } - + clock_add_to_group(clock_adc3, 0); freq = clock_get_frequency(clock_adc3); } return freq; } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + void board_init_can(CAN_Type *ptr) { init_can_pins(ptr); @@ -922,18 +798,22 @@ uint32_t board_init_can_clock(CAN_Type *ptr) if (ptr == HPM_CAN0) { /* Set the CAN0 peripheral clock to 80MHz */ clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can0, 0); freq = clock_get_frequency(clock_can0); } else if (ptr == HPM_CAN1) { /* Set the CAN1 peripheral clock to 80MHz */ clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can1, 0); freq = clock_get_frequency(clock_can1); } else if (ptr == HPM_CAN2) { /* Set the CAN2 peripheral clock to 80MHz */ clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can2, 0); freq = clock_get_frequency(clock_can2); } else if (ptr == HPM_CAN3) { /* Set the CAN3 peripheral clock to 80MHz */ clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can3, 0); freq = clock_get_frequency(clock_can3); } else { /* Invalid CAN instance */ @@ -941,70 +821,18 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr3); - } - else if (ptr == HPM_GPTMR4) { - clock_add_to_group(clock_gptmr4, 0); - clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr4); - } - else if (ptr == HPM_GPTMR5) { - clock_add_to_group(clock_gptmr5, 0); - clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr5); - } - else if (ptr == HPM_GPTMR6) { - clock_add_to_group(clock_gptmr6, 0); - clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr6); - } - else if (ptr == HPM_GPTMR7) { - clock_add_to_group(clock_gptmr7, 0); - clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr7); - } - else { - /* Invalid instance */ - } - return freq; -} - - +#ifdef INIT_EXT_RAM_FOR_DATA /* * this function will be called during startup to initialize external memory for data use */ void _init_ext_ram(void) { uint32_t femc_clk_in_hz; - clock_add_to_group(clock_femc, 0); - board_init_sdram_pins(); - femc_clk_in_hz = board_init_femc_clock(); - femc_config_t config = {0}; femc_sdram_config_t sdram_config = {0}; + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); femc_default_config(HPM_FEMC, &config); femc_init(HPM_FEMC, &config); @@ -1014,7 +842,7 @@ void _init_ext_ram(void) sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS; sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ @@ -1037,23 +865,14 @@ void _init_ext_ram(void) femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } - -void board_sd_power_switch(SDXC_Type *ptr, bool on_off) -{ - if (ptr == BOARD_APP_SDCARD_SDXC_BASE) { - init_sdxc_pwr_pin(ptr, true); - gpio_set_pin_output_with_initial(BOARD_APP_SDCARD_POWER_EN_GPIO_BASE, BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX, BOARD_APP_SDCARD_POWER_EN_GPIO_PIN, on_off); - } -} +#endif uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { - if (ptr != BOARD_APP_SDCARD_SDXC_BASE) { - break; - } clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + clock_add_to_group(sdxc_clk, 0); sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); /* Configure the clock below 400KHz for the identification state */ @@ -1083,6 +902,12 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver if (need_inverse) { sdxc_enable_inverse_clock(ptr, true); } + + hpm_stat_t status = clock_wait_source_stable(sdxc_clk); + if (status != status_success) { + break; + } + sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -1090,19 +915,6 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver return actual_freq; } -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr) -{ - /* This feature is not supported */ -} - -bool board_sd_detect_card(SDXC_Type *ptr) -{ - GPIO_Type *gpio = BOARD_APP_SDCARD_CARD_DETECTION_GPIO; - uint32_t gpio_index = BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX; - uint32_t pin_index = BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX; - return ((gpio->DI[gpio_index].VALUE & (1UL << pin_index)) == 0U); -} - static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) { pwm_cmp_config_t cmp_config = {0}; @@ -1196,9 +1008,11 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { /* set clock source */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ } else if (ptr == HPM_ENET1) { + clock_add_to_group(clock_ptp1, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ } else { @@ -1210,21 +1024,20 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { + clock_name_t eth_clk = (ptr == HPM_ENET0) ? clock_eth0 : clock_eth1; + /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET1) { - if (internal) { - /* set pll output frequency at 1GHz */ - if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { - /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */ - pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); - /* set eth clock frequency at 50MHz for enet0 */ - clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5); - } else { - return status_fail; - } + clock_add_to_group(eth_clk, BOARD_RUNNING_CORE & 0x1); + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 */ + pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(eth_clk, clk_src_pll2_clk1, 5); + } else { + return status_fail; } - } else { - return status_invalid_argument; } enet_rmii_enable_clock(ptr, internal); @@ -1235,6 +1048,7 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); } @@ -1311,6 +1125,12 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +void board_init_enet_pps_capture_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_capture_pins(); +} + #if defined(ENET_MULTIPLE_PORT) && ENET_MULTIPLE_PORT hpm_stat_t board_init_multiple_enet_pins(void) @@ -1401,3 +1221,50 @@ void board_init_dao_pins(void) { init_dao_pins(); } + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr4); + } else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr5); + } else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr6); + } else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr7); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} + diff --git a/bsp/hpmicro/hpm6750evk2/board/board.h b/bsp/hpmicro/hpm6750evk2/board/board.h index 7d6487312e7..dd11af92724 100644 --- a/bsp/hpmicro/hpm6750evk2/board/board.h +++ b/bsp/hpmicro/hpm6750evk2/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -33,13 +33,14 @@ /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART13 -#define BOARD_APP_UART_IRQ IRQn_UART13 +#define BOARD_APP_UART_BASE HPM_UART13 +#define BOARD_APP_UART_IRQ IRQn_UART13 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart13 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PE31 /* uart rx idle demo section */ #define BOARD_UART_IDLE BOARD_APP_UART_BASE @@ -67,6 +68,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -95,15 +98,15 @@ #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_UART_BASE HPM_UART13 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif @@ -113,19 +116,17 @@ #endif /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) -#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS +#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) #define BOARD_FLASH_SIZE (16 << 20) -#define BOARD_FEMC_DQS_FLOATING 1 - /* lcd section */ #define BOARD_LCD_BASE HPM_LCDC #define BOARD_LCD_IRQ IRQn_LCDC_D0 @@ -171,17 +172,20 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR4 @@ -220,6 +224,7 @@ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ #define BOARD_APP_GPIO_PIN 2 +#define BOARD_BUTTON_PRESSED_VALUE 0 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ @@ -251,9 +256,9 @@ /* Flash section */ #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x0000000EU) /* lcd section */ @@ -268,13 +273,26 @@ #define BOARD_PDMA_BASE HPM_PDMA /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S0 -#define BOARD_APP_I2S_DATA_LINE (2U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s0 -#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX -#define BOARD_APP_I2S_IRQ IRQn_I2S0 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_TX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_RX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 + +#define BOARD_MIC_I2S HPM_I2S0 +#define BOARD_MIC_I2S_CLK_NAME clock_i2s0 +#define BOARD_MIC_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_MIC_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX + +#define BOARD_SPEAKER_I2S HPM_I2S1 +#define BOARD_SPEAKER_I2S_CLK_NAME clock_i2s1 +#define BOARD_SPEAKER_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_SPEAKER_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S1_TX + +/* pdm selection */ #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) @@ -284,6 +302,10 @@ #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_AUXI_SNAPSHOT HPM_ENET0 +#define BOARD_ENET_AUXI_SNAPSHOT_IDX enet_ptp_auxi_snapshot_trigger_1 +#define BOARD_ENET_AUXI_SNAPSHOT_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOF @@ -303,35 +325,6 @@ #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp1) #define BOARD_ENET_RMII_PPS0_PINOUT (0) -#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET0_INT_REF_CLK (0U) -#define BOARD_ENET0_PHY_RST_TIME (30) -#if BOARD_ENET0_INF -#define BOARD_ENET0_TX_DLY (0U) -#define BOARD_ENET0_RX_DLY (7U) -#endif -#if __USE_ENET_PTP -#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) -#endif - -#define BOARD_ENET1_RST_GPIO HPM_GPIO0 -#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE -#define BOARD_ENET1_RST_GPIO_PIN (26U) - -#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET1_INT_REF_CLK (1U) -#define BOARD_ENET1_PHY_RST_TIME (30) - -#if BOARD_ENET1_INF -#define BOARD_ENET1_TX_DLY (0U) -#define BOARD_ENET1_RX_DLY (0U) -#endif - -#if __USE_ENET_PTP -#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) -#endif - - /* ADC section */ #define BOARD_APP_ADC12_NAME "ADC0" #define BOARD_APP_ADC12_BASE HPM_ADC0 @@ -344,18 +337,21 @@ #define BOARD_APP_ADC16_IRQn IRQn_ADC3 #define BOARD_APP_ADC16_CH_1 (2U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) - -#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI -#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A - -#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI -#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC12_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A @@ -378,6 +374,7 @@ /* SDXC section */ #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SDXC_IRQ IRQn_SDXC1 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) #define BOARD_APP_SDCARD_SUPPORT_1V8 (0) #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) @@ -390,19 +387,14 @@ #if defined(BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO) && (BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO == 1) #define BOARD_APP_SDCARD_CARD_DETECTION_PIN IOC_PAD_PD15 #define BOARD_APP_SDCARD_CARD_DETECTION_PIN_POL 1 /* PIN value 0 means card is inserted */ -#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO HPM_GPIO0 -#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX GPIO_DI_GPIOD -#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX 15 #endif #if defined(BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO) && (BOARD_APP_SDCARD_POWER_SWITCH_USING_GPIO == 1) -#define BOARD_APP_SDCARD_POWER_EN_GPIO_BASE HPM_GPIO0 -#define BOARD_APP_SDCARD_POWER_EN_GPIO_INDEX GPIO_DO_GPIOC -#define BOARD_APP_SDCARD_POWER_EN_GPIO_PIN 20 #define BOARD_APP_SDCARD_POWER_SWITCH_PIN IOC_PAD_PC20 #define BOARD_APP_SDCARD_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ #endif #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_EMMC_SDXC_IRQ IRQn_SDXC1 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) #define BOARD_APP_EMMC_SUPPORT_1V8 (0) #define BOARD_APP_EMMC_SUPPORT_4BIT (1) @@ -414,22 +406,28 @@ #define BOARD_APP_EMMC_POWER_SWITCH_PIN_POL 0 /* PIN value 1 means power is supplied */ #endif -/* USB section */ -#define BOARD_USB0_ID_PORT (HPM_GPIO0) -#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) -#define BOARD_USB0_ID_GPIO_PIN (10) - -#define BOARD_USB0_OC_PORT (HPM_GPIO0) -#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) -#define BOARD_USB0_OC_GPIO_PIN (8) +#define BOARD_APP_SDIO_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDIO_SDXC_IRQ IRQn_SDXC1 +#define BOARD_APP_SDIO_SUPPORT_3V3 (1) +#define BOARD_APP_SDIO_SUPPORT_1V8 (0) +#define BOARD_APP_SDIO_SUPPORT_4BIT (1) +#define BOARD_APP_SDIO_SUPPORT_POWER_SWITCH (1) +#define BOARD_APP_SDIO_SUPPORT_VOLTAGE_SWITCH (0) +#define BOARD_APP_SDIO_SUPPORT_CARD_DETECTION (0) +#define BOARD_APP_SDIO_POWER_SWITCH_USING_GPIO (1) +#define BOARD_APP_SDIO_VOLTAGE_SWITCH_USING_GPIO (0) +#define BOARD_APP_SDIO_POWER_SWITCH_USING_GPIO (1) +#ifdef BOARD_APP_SDIO_POWER_SWITCH_USING_GPIO +#define BOARD_APP_SDIO_POWER_SWITCH_PIN IOC_PAD_PC20 +#endif -#define BOARD_USB1_ID_PORT (HPM_GPIO0) -#define BOARD_USB1_ID_GPIO_INDEX (GPIO_DO_GPIOF) -#define BOARD_USB1_ID_GPIO_PIN (7) +#define BOARD_APP_SDIO_WIFI_OOB_PORT (HPM_GPIO0) +#define BOARD_APP_SDIO_WIFI_OOB_PIN (IOC_PAD_PD24) +#define BOARD_APP_SDIO_WIFI_OOB_IRQ IRQn_GPIO0_D +#define BOARD_APP_SDIO_WIFI_WL_REG_ON_PORT (HPM_GPIO0) +#define BOARD_APP_SDIO_WIFI_WL_REG_ON_PIN (IOC_PAD_PD19) +#define BOARD_APP_SDIO_WIFI_SDXC_PORT BOARD_APP_SDIO_SDXC_BASE -#define BOARD_USB1_OC_PORT (HPM_GPIO0) -#define BOARD_USB1_OC_GPIO_INDEX (GPIO_DI_GPIOF) -#define BOARD_USB1_OC_GPIO_PIN (5) /*BLDC pwm*/ @@ -480,17 +478,29 @@ /*Timer define*/ -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) -#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS -#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH -#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP -#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ -#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) /*adc*/ #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 @@ -507,8 +517,9 @@ #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG2A #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM2_INPUT_SRC_PWM2_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM2_INPUT_SRC_PWM2_CH8REF + #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 /* APP PWM */ @@ -546,7 +557,7 @@ #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) -#define BOARD_CPU_FREQ (648000000UL) +#define BOARD_CPU_FREQ (816000000UL) #define BOARD_APP_DISPLAY_CLOCK clock_display @@ -563,16 +574,65 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR6 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 +#define BOARD_THREADX_TIMER HPM_GPTMR6 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR6 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr6 /* Tamper Section */ #define BOARD_TAMP_ACTIVE_CH 8 #define BOARD_TAMP_LOW_LEVEL_CH 10 +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOD +#define BOARD_I2S_SPI_CS_GPIO_PIN 25 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PD25 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR3 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 1 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr3 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 3 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR5 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr5 + +#define BOARD_APP_CLK_REF_PIN_NAME "J10[7] (PE24)" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref1 + +/* BGPR */ +#define BOARD_BGPR HPM_BGPR + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -585,6 +645,7 @@ void board_init_console(void); void board_init_core1(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); void board_lcd_backlight(bool is_on); @@ -619,39 +680,32 @@ uint32_t board_init_uart_clock(UART_Type *ptr); /* Initialize the CAM(camera) dot clock */ uint32_t board_init_cam_clock(CAM_Type *ptr); -/* Initialize the LCD pixel clock */ -uint32_t board_init_lcd_clock(void); - uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_acmp_clock(ACMP_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + hpm_stat_t board_set_audio_pll_clock(uint32_t freq); void board_init_i2s_pins(I2S_Type *ptr); -uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); -void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); -bool board_sd_detect_card(SDXC_Type *ptr); void board_init_dao_pins(void); void board_init_adc12_pins(void); void board_init_adc16_pins(void); - -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_acmp_pins(void); +void board_init_usb(USB_Type *ptr); void board_init_enet_pps_pins(ENET_Type *ptr); +void board_init_enet_pps_capture_pins(ENET_Type *ptr); uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); @@ -701,6 +755,15 @@ uint8_t board_get_led_pwm_off_level(void); */ uint8_t board_get_led_gpio_off_level(void); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); + +/* + * brief Initialize the clock reference pin. + */ +void board_init_clk_ref_pin(void); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld new file mode 100644 index 00000000000..2f39e2409d8 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld @@ -0,0 +1,357 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 768K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > AXI_SRAM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + /* hpm_sdk drivers */ + KEEP(*hpm_sdxc_drv*.o (.text .text* .rodata .rodata*)) + + /* WHD related */ + KEEP(*whd_bus*.o (.text .text* .rodata .rodata*)) + KEEP(*whd_sdpcm*.o (.text .text* .rodata .rodata*)) + KEEP(*whd_thread*.o (.text .text* .rodata .rodata*)) + + /* LWIP */ + KEEP(*lwip*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > AXI_SRAM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld similarity index 78% rename from bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld index 42ee5b0612e..8b4f6137da8 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -86,12 +89,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -116,12 +119,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -155,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -167,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -187,22 +208,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -230,10 +255,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -254,7 +279,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -279,7 +306,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -290,8 +318,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -310,7 +341,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt_enet.ld similarity index 80% rename from bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt_enet.ld index f1d2bf25ac5..bcd6c6e1252 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -106,16 +109,12 @@ SECTIONS KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -173,6 +172,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -181,6 +194,20 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -201,22 +228,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -244,10 +275,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -268,7 +299,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -293,7 +326,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -304,8 +338,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -324,7 +361,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_sdram_rtt.ld similarity index 77% rename from bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld rename to bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_sdram_rtt.ld index 218084bf969..8618b40e550 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/flash_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -82,16 +85,16 @@ SECTIONS KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - + /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -149,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -161,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -176,6 +203,7 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); __tbss_start__ = .; @@ -185,17 +213,20 @@ SECTIONS __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -223,10 +254,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -247,9 +278,12 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -260,8 +294,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld new file mode 100644 index 00000000000..e03cd86e664 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_rtt.ld @@ -0,0 +1,306 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; + +MEMORY +{ + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K + AXI_SRAM1 (w) : ORIGIN = 0x01100000, LENGTH = 768K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k +} + +SECTIONS +{ + .start : { + . = ALIGN(8); + KEEP(*(.start)) + } > AXI_SRAM + + .vectors : { + . = ALIGN(8); + KEEP(*(.isr_vector)) + KEEP(*(.vector_table)) + . = ALIGN(8); + } > AXI_SRAM + + .text : { + . = ALIGN(8); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + *(FalPartTable) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); + } > AXI_SRAM + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > AXI_SRAM + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > AXI_SRAM + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > AXI_SRAM + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + /* NOTE: + Please keep in mind that the load section for rw data is after .text section + Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section + and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: + 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ + 2. the generated binary file will be larger because the space occupied by + NOLOAD sections will be filled + */ + __data_load_addr__ = __etext; + .data : AT(__data_load_addr__) { + __data_start__ = .; + . = ALIGN(8); + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + + __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { + PROVIDE(__ramfunc_start__ = .); + . = ALIGN(8); + *(.fast) + . = ALIGN(8); + PROVIDE(__ramfunc_end__ = .); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + /* Note: Place all NOLOAD sections together */ + .tbss(NOLOAD) : { + . += SIZEOF(.noncacheable.init); + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM1 + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM1 + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE (__rt_rvstack = .); + } > AXI_SRAM1 + + .framebuffer (NOLOAD) : { + KEEP(*(.framebuffer)) + } > AXI_SRAM1 + + .heap (NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + + } > AXI_SRAM1 + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_sdram_rtt.ld similarity index 70% rename from bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld rename to bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_sdram_rtt.ld index cd15d78304c..fc810f781dc 100644 --- a/bsp/hpmicro/hpm6750evk/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/gcc/ram_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -87,61 +87,51 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); } > AXI_SRAM .rel : { KEEP(*(.rel*)) } > AXI_SRAM + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > AXI_SRAM + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > AXI_SRAM + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - .tdata : AT(etext) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - .data : AT(etext + __tdata_end__ - __tdata_start__) { + /* NOTE: + Please keep in mind that the load section for rw data is after .text section + Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section + and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: + 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ + 2. the generated binary file will be larger because the space occupied by + NOLOAD sections will be filled + */ + __data_load_addr__ = __etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -169,10 +159,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -195,7 +185,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -203,7 +194,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -211,11 +203,63 @@ SECTIONS . = ALIGN(8); } > NONCACHEABLE_RAM + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + /* Note: Place all NOLOAD sections together */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6750evk2/board/pinmux.c b/bsp/hpmicro/hpm6750evk2/board/pinmux.c index a918344b2b7..2abb2245be5 100644 --- a/bsp/hpmicro/hpm6750evk2/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -132,9 +132,9 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr) void init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C0) { - HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PB11_FUNC_CTL_I2C0_SCL + HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_I2C0_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA + HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_I2C0_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; /* PZ port IO needs to configure BIOC as well */ HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3; @@ -147,7 +147,7 @@ void init_i2c_pins(I2C_Type *ptr) } } -void init_sdram_pins(void) +void init_femc_pins(void) { HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -183,7 +183,7 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #WE */ HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -196,7 +196,7 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #ADV */ HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); @@ -205,63 +205,13 @@ void init_sdram_pins(void) HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #LB */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #UB */ HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); -} -void init_sram_pins(void) -{ - /* Non-MUX */ /* MUX */ - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ - HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ - HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ - HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ - HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ - HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ - HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ - HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ - HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ - - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ - - HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ - HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #OE */ } void init_gpio_pins(void) @@ -284,6 +234,11 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE27].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } } @@ -294,15 +249,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PE30_FUNC_CTL_SPI2_MOSI; HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PE28_FUNC_CTL_SPI2_MISO; HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PE27_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); - } -} -void init_pins(void) -{ -#ifdef BOARD_CONSOLE_UART_BASE - init_uart_pins(BOARD_CONSOLE_UART_BASE); -#endif - init_sdram_pins(); + HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE28].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PE27].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + } } void init_gptmr_pins(GPTMR_Type *ptr) @@ -481,11 +433,7 @@ void init_pwm_pins(PWM_Type *ptr) void init_adc12_pins(void) { - /* ADC0/1/2.VIN7 */ - HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2.VIN10 */ - HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - /* ADC0/1/2.VIN11 */ + /* ADC0.VIN11 */ HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } @@ -502,23 +450,15 @@ void init_adc_bldc_pins(void) HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - /* USB0_ID */ - HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; - HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB0_OC */ - HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; - HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB1_ID */ - HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07; - HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB1_OC */ - HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_GPIO_F_05; - HPM_IOC->PAD[IOC_PAD_PF05].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + if (ptr == HPM_USB0) { + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_USB0_ID; + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_USB0_OC; + } else if (ptr == HPM_USB1) { + HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_USB1_ID; + HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_USB1_OC; + } } void init_can_pins(CAN_Type *ptr) @@ -572,7 +512,7 @@ void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) /* SDXC1.DATA0 */ HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - if ((width == 4)) { + if (width == 4) { /* SDXC1.DATA1 */ HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; @@ -626,9 +566,64 @@ void init_enet_pps_pins(void) HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; } +void init_enet_pps_capture_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_ETH0_EVTI_1; +} + void init_tamper_pins(void) { HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = BIOC_PZ08_FUNC_CTL_TAMP_08 | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_TAMP_09; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_TAMP_10; } + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PE31].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PE31_FUNC_CTL_GPIO_E_31; +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR3) { + if ((channel == 1) && (as_comp == true)) { + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR3_COMP_1; + } + } else if (ptr == HPM_GPTMR4) { + if ((channel == 1) && (as_comp == false)) { + HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1; + } + } else if (ptr == HPM_GPTMR5) { + if (as_comp == true) { + switch (channel) { + case 2: + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; + trgm_enable_io_output(HPM_TRGM2, 1 << 10); + trgm_output_t trgm2IoConfig0; + trgm2IoConfig0.invert = 0; + trgm2IoConfig0.type = trgm_output_same_as_input; + trgm2IoConfig0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2IoConfig0); + break; + case 3: + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_TRGM2_P_11; + trgm_enable_io_output(HPM_TRGM2, 1 << 11); + trgm_output_t trgm2IoConfig1; + trgm2IoConfig1.invert = 0; + trgm2IoConfig1.type = trgm_output_same_as_input; + trgm2IoConfig1.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P11, &trgm2IoConfig1); + break; + default: + break; + } + } + } +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_SOC_REF1; +} diff --git a/bsp/hpmicro/hpm6750evk2/board/pinmux.h b/bsp/hpmicro/hpm6750evk2/board/pinmux.h index 7b850152b53..ac8a2e7c35f 100644 --- a/bsp/hpmicro/hpm6750evk2/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evk2/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -16,8 +16,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); -void init_sdram_pins(void); -void init_sram_pins(void); +void init_femc_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -40,7 +39,7 @@ void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8); void init_sdxc_pwr_pin(SDXC_Type *ptr, bool as_gpio); void init_adc12_pins(void); void init_adc16_pins(void); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_can_pins(CAN_Type *ptr); void init_adc_bldc_pins(void); void init_rgb_pwm_pins(void); @@ -48,7 +47,11 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); void init_enet_pps_pins(void); +void init_enet_pps_capture_pins(void); void init_tamper_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pin(void); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c index 41b5b9e7b37..ea3693f1410 100644 --- a/bsp/hpmicro/hpm6750evk2/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.c @@ -15,20 +15,13 @@ #include #include #include "hpm_dma_mgr.h" +#include "hpm_l1c_drv.h" #include "hpm_mchtmr_drv.h" extern int rt_hw_uart_init(void); void os_tick_config(void); void rtt_board_init(void); -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void os_tick_config(void) { sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); @@ -37,8 +30,14 @@ void os_tick_config(void) enable_mchtmr_irq(); } +void rtt_os_tick_clock(void) +{ + clock_add_to_group(clock_mchtmr0, 0); +} + void rtt_board_init(void) { + rtt_os_tick_clock(); board_init_clock(); board_init_console(); board_init_pmp(); @@ -60,6 +59,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); @@ -98,19 +98,12 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); -} - -ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) -{ - HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - - rt_tick_increase(); + board_init_usb(HPM_USB0); } void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->RESET_HOT &= ~(1UL << 31); HPM_PPOR->RESET_COLD |= (1UL << 31); @@ -132,3 +125,139 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc2, 0); + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC3) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc3, 0); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) + +#ifdef HPM_USB1_BASE +extern void hpm_isr_usb1(void); +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, hpm_isr_usb1) +#endif +#endif + + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk2/board/rtt_board.h b/bsp/hpmicro/hpm6750evk2/board/rtt_board.h index fbe587f3af6..c35fe875cf7 100644 --- a/bsp/hpmicro/hpm6750evk2/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evk2/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,9 @@ #include "hpm_soc.h" /* gpio section */ +#define APP_LED0 (0U) +#define APP_LED1 (1U) +#define APP_LED2 (2U) #define APP_LED0_GPIO_CTRL HPM_GPIO0 #define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB #define APP_LED0_GPIO_PIN 11 @@ -28,6 +31,12 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* SPI WIFI section */ #define RW007_RST_PIN (IOC_PAD_PE02) #define RW007_INT_BUSY_PIN (IOC_PAD_PE01) @@ -54,6 +63,34 @@ #define IRQn_PendSV IRQn_DEBUG_0 +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (7U) +#endif +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET1_RST_GPIO_PIN (26U) + +#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET1_INT_REF_CLK (1U) +#define BOARD_ENET1_PHY_RST_TIME (30) + +#if BOARD_ENET1_INF +#define BOARD_ENET1_TX_DLY (0U) +#define BOARD_ENET1_RX_DLY (0U) +#endif + +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +#endif + /*************************************************************** * * RT-Thread related definitions diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.h b/bsp/hpmicro/hpm6750evk2/rtconfig.h index 3a7ea8d3597..f4225f1286c 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.h +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -75,6 +75,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 2048 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -103,6 +104,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -146,9 +149,8 @@ #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 #define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_RTC +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE #define RT_USING_PIN /* end of Device Drivers */ @@ -313,6 +315,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -392,17 +408,23 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM6700_SERIES /* Hardware Drivers Config */ -#define SOC_HPM6000 +#define SOC_HPM6700 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 -#define BSP_USING_RTC +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 +#define BSP_USING_FEMC +#define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.py b/bsp/hpmicro/hpm6750evk2/rtconfig.py index b32af3b14f4..d0b944eb3fa 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.py +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2024 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c index b0bab335d52..4fc6914d566 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/startup.c @@ -1,128 +1,139 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + /* NOTE: Invalid I-Cache in case the I-Cache was filled with incorrect data during prefetch before copying the ram + * function code to its destination. */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + fencei(); + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S index 238e05b43bb..5ac683dbc27 100644 --- a/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evk2/startup/HPM6750/toolchains/gcc/start.S @@ -75,7 +75,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6750evkmini/.config b/bsp/hpmicro/hpm6750evkmini/.config index a3b198c1e86..dba4da6d0b8 100644 --- a/bsp/hpmicro/hpm6750evkmini/.config +++ b/bsp/hpmicro/hpm6750evkmini/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -183,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -199,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -225,10 +227,11 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y # CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set @@ -246,7 +249,9 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_MTD_NOR is not set # CONFIG_RT_USING_MTD_NAND is not set # CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set # CONFIG_RT_USING_SDIO is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set @@ -375,6 +380,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -483,6 +489,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -572,6 +579,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -617,6 +625,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -710,6 +719,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -791,6 +801,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -833,6 +845,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -846,6 +862,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1017,6 +1058,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1355,23 +1397,41 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM6700_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM6000=y +CONFIG_SOC_HPM6700=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 # CONFIG_RW007_USING_WIFI is not set CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set # CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_UART11 is not set +# CONFIG_BSP_USING_UART12 is not set # CONFIG_BSP_USING_UART13 is not set # CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_UART15 is not set # CONFIG_BSP_USING_SPI is not set -CONFIG_BSP_USING_RTC=y +# CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_SDXC is not set # CONFIG_BSP_USING_TOUCH is not set diff --git a/bsp/hpmicro/hpm6750evkmini/SConstruct b/bsp/hpmicro/hpm6750evkmini/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6750evkmini/SConstruct +++ b/bsp/hpmicro/hpm6750evkmini/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6750evkmini/board/Kconfig b/bsp/hpmicro/hpm6750evkmini/board/Kconfig index 31468bd6da1..29c636386ec 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/Kconfig +++ b/bsp/hpmicro/hpm6750evkmini/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6000 +config SOC_HPM6700 bool - select SOC_SERIES_HPM6000 + select SOC_HPM6700_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -11,11 +11,23 @@ config BSP_USING_ENET_PHY_LAN8720 bool default n +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif config RW007_USING_BLE bool "Enable RW007 BLE" @@ -25,8 +37,8 @@ menu "On-chip Peripheral Drivers" config RW007_USING_WIFI bool "Enable RW007 WIFI" - select RT_USING_SPI if RW007_USING_BLE - select BSP_USING_SPI1 if RW007_USING_BLE + select RT_USING_SPI if RW007_USING_WIFI + select BSP_USING_SPI1 if RW007_USING_WIFI menuconfig BSP_USING_UART bool "Enable UART" @@ -56,6 +68,145 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART6 bool "Enable UART6" @@ -79,6 +230,172 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART8 + bool "Enable UART8" + default n + if BSP_USING_UART8 + config BSP_UART8_RX_USING_DMA + bool "Enable UART8 RX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + default n + config BSP_UART8_TX_USING_DMA + bool "Enable UART8 TX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + default n + config BSP_UART8_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART8_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART8_IRQ_PRIORITY + int "UART8 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART9 + bool "Enable UART9" + default n + if BSP_USING_UART9 + config BSP_UART9_RX_USING_DMA + bool "Enable UART9 RX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + default n + config BSP_UART9_TX_USING_DMA + bool "Enable UART9 TX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + default n + config BSP_UART9_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART9_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART9_IRQ_PRIORITY + int "UART9 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_USING_DMA + bool "Enable UART10 RX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + default n + config BSP_UART10_TX_USING_DMA + bool "Enable UART10 TX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + default n + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART10_IRQ_PRIORITY + int "UART10 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART11 + bool "Enable UART11" + default n + if BSP_USING_UART11 + config BSP_UART11_RX_USING_DMA + bool "Enable UART11 RX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + default n + config BSP_UART11_TX_USING_DMA + bool "Enable UART11 TX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + default n + config BSP_UART11_RX_BUFSIZE + int "Set UART11 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART11_TX_BUFSIZE + int "Set UART11 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART11_IRQ_PRIORITY + int "UART11 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART12 + bool "Enable UART12" + default n + if BSP_USING_UART12 + config BSP_UART12_RX_USING_DMA + bool "Enable UART12 RX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + default n + config BSP_UART12_TX_USING_DMA + bool "Enable UART12 TX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + default n + config BSP_UART12_RX_BUFSIZE + int "Set UART12 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART12_TX_BUFSIZE + int "Set UART12 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART12_IRQ_PRIORITY + int "UART12 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART13 bool "Enable UART13" @@ -102,6 +419,10 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART13_IRQ_PRIORITY + int "UART13 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART14 bool "Enable UART14" @@ -125,50 +446,179 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART14_IRQ_PRIORITY + int "UART14 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART15 + bool "Enable UART15" + default n + if BSP_USING_UART15 + config BSP_UART15_RX_USING_DMA + bool "Enable UART15 RX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + default n + config BSP_UART15_TX_USING_DMA + bool "Enable UART15 TX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + default n + config BSP_UART15_RX_BUFSIZE + int "Set UART15 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART15_TX_BUFSIZE + int "Set UART15 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART15_IRQ_PRIORITY + int "UART15 Interrupt Priority" + range 1 7 + default 1 endif endif - - menuconfig BSP_USING_SPI bool "Enable SPI" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif config BSP_USING_SPI1 bool "Enable SPI1" - default y + default n if BSP_USING_SPI1 config BSP_SPI1_USING_DMA - bool "Enable SPI1 DMA" - default n + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice endif config BSP_USING_SPI2 bool "Enable SPI2" default n if BSP_USING_SPI2 config BSP_SPI2_USING_DMA - bool "Enable SPI2 DMA" - default n + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice endif config BSP_USING_SPI3 bool "Enable SPI3" default n if BSP_USING_SPI3 config BSP_SPI3_USING_DMA - bool "Enable SPI3 DMA" - default n + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH + + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + if BSP_USING_ETH config BSP_USING_ETH1 bool "Enable ETH1" @@ -180,11 +630,43 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC" default n select RT_USING_SDIO if BSP_USING_SDXC + select RT_USING_PIN if BSP_USING_SDXC if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" default n if BSP_USING_SDXC0 + config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC0_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC0_USE_NONCACHEABLE_BUFFER + config BSP_SDXC0_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC0_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + + config BSP_SDXC0_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT @@ -197,7 +679,7 @@ menu "On-chip Peripheral Drivers" endchoice choice prompt "Select Voltage" - default BSP_SDXC0_VOLTAGE_1V8 + default BSP_SDXC0_VOLTAGE_3V3 config BSP_SDXC0_VOLTAGE_3V3 bool "3.3V" config BSP_SDXC0_VOLTAGE_1V8 @@ -217,39 +699,69 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC1" default n if BSP_USING_SDXC1 - choice - prompt "Select BUS_WIDTH" - default BSP_SDXC1_BUS_WIDTH_4BIT - config BSP_SDXC1_BUS_WIDTH_1BIT - bool "1-bit" - config BSP_SDXC1_BUS_WIDTH_4BIT - bool "4-bit" - endchoice - choice - prompt "Select Voltage" - default BSP_SDXC1_VOLTAGE_3V3 - config BSP_SDXC1_VOLTAGE_3V3 - bool "3.3V" - config BSP_SDXC1_VOLTAGE_1V8 - bool "1.8V" - config BSP_SDXC1_VOLTAGE_DUAL - bool "Dual voltage 3.3V / 1.8V" - endchoice - config BSP_SDXC1_VSEL_PIN + config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC1_USE_CACHEABLE_BUFFER + config BSP_SDXC1_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC1_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC1_USE_CACHEABLE_BUFFER + config BSP_SDXC1_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC1_USE_NONCACHEABLE_BUFFER + config BSP_SDXC1_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC1_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + config BSP_SDXC1_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC1_BUS_WIDTH_4BIT + config BSP_SDXC1_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC1_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC1_VOLTAGE_3V3 + config BSP_SDXC1_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC1_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC1_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC1_VSEL_PIN default "PD29" string "VSEL pin name" - config BSP_SDXC1_PWR_PIN + config BSP_SDXC1_PWR_PIN default "None" string "PWR pin name" - endif + endif endif menuconfig BSP_USING_TOUCH bool "Enable touch" default n if BSP_USING_TOUCH - config BSP_USING_TOUCH_GT911 - bool "Enable GT911" + config BSP_USING_TOUCH_GT9xx + bool "Enable GT9xx" default y config BSP_USING_TOUCH_FT5406 @@ -281,53 +793,133 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_HWTIMER if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR3 bool "Enable GPTMR3" default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR4 bool "Enable GPTMR4" default n + if BSP_USING_GPTMR4 + config BSP_GPTMR4_IRQ_PRIORITY + int "GPTMR4 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR5 bool "Enable GPTMR5" default n + if BSP_USING_GPTMR5 + config BSP_GPTMR5_IRQ_PRIORITY + int "GPTMR5 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR6 bool "Enable GPTMR6" default n + if BSP_USING_GPTMR6 + config BSP_GPTMR6_IRQ_PRIORITY + int "GPTMR6 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR7 bool "Enable GPTMR7" default n + if BSP_USING_GPTMR7 + config BSP_GPTMR7_IRQ_PRIORITY + int "GPTMR7 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C bool "Enable I2C" default n + select RT_USING_I2C if BSP_USING_I2C if BSP_USING_I2C config BSP_USING_I2C0 bool "Enable I2C0" default y - - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" - default n - endif - + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" - default n - endif - + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_FEMC @@ -346,6 +938,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PWM bool "Enable PWM" default n + select RT_USING_PWM if BSP_USING_PWM menuconfig BSP_USING_DAO bool "Enable Audio DAO play" @@ -373,6 +966,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB HOST" @@ -408,45 +1002,69 @@ menu "On-chip Peripheral Drivers" config BSP_USING_CAN0 bool "Enable CAN0" default n + if BSP_USING_CAN0 + config BSP_CAN0_IRQ_PRIORITY + int "CAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN1 bool "Enable CAN1" default n + if BSP_USING_CAN1 + config BSP_CAN1_IRQ_PRIORITY + int "CAN1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN2 bool "Enable CAN2" default n + if BSP_USING_CAN2 + config BSP_CAN2_IRQ_PRIORITY + int "CAN2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_CAN3 bool "Enable CAN3" default n + if BSP_USING_CAN3 + config BSP_CAN3_IRQ_PRIORITY + int "CAN3 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC if BSP_USING_ADC - if BSP_USING_ADC - menuconfig BSP_USING_ADC12 - bool "Enable ADC12" - default n - if BSP_USING_ADC12 - config BSP_USING_ADC0 - bool "Enable ADC0" - default n - config BSP_USING_ADC1 - bool "Enable ADC1" - default n - config BSP_USING_ADC2 - bool "Enable ADC2" - default n - endif - menuconfig BSP_USING_ADC16 - bool "Enable ADC16" - default n - if BSP_USING_ADC16 - config BSP_USING_ADC3 - bool "Enable ADC3" - default n - endif - endif + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC12 + bool "Enable ADC12" + default n + if BSP_USING_ADC12 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif menuconfig BSP_USING_CAMERA bool "Enable camera" @@ -486,6 +1104,12 @@ menu "On-chip Peripheral Drivers" bool "Enable RTT LCD Driver" select BSP_USING_LCD default n + if BSP_USING_RTT_LCD_DRIVER + config BSP_RTT_LCD_IRQ_PRIORITY + int "RTT LCD Interrupt Priority" + range 1 7 + default 1 + endif endmenu diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.c b/bsp/hpmicro/hpm6750evkmini/board/board.c index 8f96532fe20..17a6df6a568 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -23,9 +23,8 @@ #include "hpm_pwm_drv.h" #include "hpm_pcfg_drv.h" #include "hpm_enet_drv.h" +#include - -static board_timer_cb timer_cb; static bool invert_led_level; /** @@ -82,11 +81,11 @@ static bool invert_led_level; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__ ((section(".nor_cfg_option"))) const uint32_t option[4] = {0xfcf90001, 0x00000007, 0x0, 0x0}; +__attribute__ ((section(".nor_cfg_option"), used)) const uint32_t option[4] = {0xfcf90002, 0x00000007, 0xE, 0x0}; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -100,8 +99,6 @@ void board_init_console(void) And a uart rx dma request will be generated by default uart fifo dma trigger level. */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -137,25 +134,16 @@ void board_print_clock_freq(void) printf("xpi0:\t\t %luHz\n", clock_get_frequency(clock_xpi0)); printf("xpi1:\t\t %luHz\n", clock_get_frequency(clock_xpi1)); printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); - printf("display:\t %luHz\n", clock_get_frequency(clock_display)); - printf("cam0:\t\t %luHz\n", clock_get_frequency(clock_camera0)); - printf("cam1:\t\t %luHz\n", clock_get_frequency(clock_camera1)); - printf("jpeg:\t\t %luHz\n", clock_get_frequency(clock_jpeg)); - printf("pdma:\t\t %luHz\n", clock_get_frequency(clock_pdma)); printf("==============================\n"); } void board_init_uart(UART_Type *ptr) { + /* configure uart's pin before opening uart's clock */ init_uart_pins(ptr); board_init_uart_clock(ptr); } -void board_init_ahb(void) -{ - clock_set_source_divider(clock_ahb,clk_src_pll1_clk1,2);/*200m hz*/ -} - void board_print_banner(void) { const uint8_t banner[] = {"\n\ @@ -237,7 +225,6 @@ void board_init(void) board_init_clock(); board_init_console(); board_init_pmp(); - board_init_ahb(); #if BOARD_SHOW_CLOCK board_print_clock_freq(); #endif @@ -248,25 +235,28 @@ void board_init(void) void board_init_core1(void) { + clock_update_core_clock(); board_init_console(); board_init_pmp(); } void board_init_sdram_pins(void) { - init_sdram_pins(); + init_femc_pins(); } uint32_t board_init_femc_clock(void) { + clock_add_to_group(clock_femc, 0); + clock_set_source_divider(clock_femc, clk_src_pll2_clk0, 2U); /* 166Mhz */ + return clock_get_frequency(clock_femc); } uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz); #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 - static void set_reset_pin_level_tm070rdh13(uint8_t level) { gpio_write_pin(BOARD_LCD_POWER_GPIO_BASE, BOARD_LCD_POWER_GPIO_INDEX, BOARD_LCD_POWER_GPIO_PIN, level); @@ -301,11 +291,9 @@ void board_init_lcd_rgb_tm070rdh13(void) hpm_panel_init(panel); hpm_panel_power_on(panel); } - #endif #ifdef CONFIG_HPM_PANEL - uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) { clock_add_to_group(clock_name, 0); @@ -329,6 +317,29 @@ void board_init_lcd(void) #endif } +/* + * Fix Errata E00039 + * + * The vpw in hpm67 soc is invalid, but actual timing of vpw is equal to hpw. + * So we need to fix the vpw to make it equal to hpw. + * The vpw is fixed by compensating the back porch, we need keep to total time of xsync and back porch unchanged. + */ +void board_lcdc_vpw_fix(lcdc_config_t *config) +{ + uint32_t hpw = config->hsync.pulse_width; + uint32_t vpw = config->vsync.pulse_width; + uint32_t diff; + + if (vpw < hpw) { + diff = hpw - vpw; + config->hsync.pulse_width = vpw; + config->hsync.back_porch_pulse += diff; + } else if (hpw < vpw) { + diff = vpw - hpw; + config->vsync.back_porch_pulse += diff; + } +} + void board_panel_para_to_lcdc(lcdc_config_t *config) { const hpm_panel_timing_t *timing; @@ -351,6 +362,8 @@ void board_panel_para_to_lcdc(lcdc_config_t *config) config->control.invert_href = timing->de_pol; config->control.invert_pixel_data = timing->pixel_data_pol; config->control.invert_pixel_clock = timing->pixel_clk_pol; + + board_lcdc_vpw_fix(config); } #endif @@ -364,6 +377,9 @@ void board_delay_us(uint32_t us) clock_cpu_delay_us(us); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -371,7 +387,6 @@ void board_timer_isr(void) timer_cb(); } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); void board_timer_create(uint32_t ms, board_timer_cb cb) { @@ -391,6 +406,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -424,28 +440,43 @@ void board_i2c_bus_clear(I2C_Type *ptr) } } +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + void board_init_i2c(I2C_Type *ptr) { + i2c_config_t config; hpm_stat_t stat; uint32_t freq; - i2c_config_t config; + freq = board_init_i2c_clock(ptr); board_i2c_bus_clear(ptr); - init_i2c_pins(ptr); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - /* Configure the I2C clock to 24MHz */ - clock_set_source_divider(BOARD_CAP_I2C_CLK_NAME, clk_src_osc24m, 1U); - config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_CAP_I2C_CLK_NAME); - stat = i2c_init_master(BOARD_CAP_I2C_BASE, freq, &config); + stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t) BOARD_CAP_I2C_BASE); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } @@ -453,85 +484,49 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_uart_clock(UART_Type *ptr) { - uint32_t freq = 0; - clock_name_t clock_name = clock_uart0; - bool need_init_clock = true; + uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_name = clock_uart0; - } else if (ptr == HPM_UART1) { - clock_name = clock_uart1; - } else if (ptr == HPM_UART2) { - clock_name = clock_uart2; - } else if (ptr == HPM_UART3) { - clock_name = clock_uart3; - } else if (ptr == HPM_UART4) { - clock_name = clock_uart4; - } else if (ptr == HPM_UART5) { - clock_name = clock_uart5; + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART6) { - clock_name = clock_uart6; + clock_add_to_group(clock_uart6, 0); + freq = clock_get_frequency(clock_uart6); } else if (ptr == HPM_UART7) { - clock_name = clock_uart7; - } else if (ptr == HPM_UART8) { - clock_name = clock_uart8; - } else if (ptr == HPM_UART9) { - clock_name = clock_uart9; - } else if (ptr == HPM_UART10) { - clock_name = clock_uart10; - } else if (ptr == HPM_UART11) { - clock_name = clock_uart11; - } else if (ptr == HPM_UART12) { - clock_name = clock_uart12; + clock_add_to_group(clock_uart7, 0); + freq = clock_get_frequency(clock_uart7); } else if (ptr == HPM_UART13) { - clock_name = clock_uart13; + clock_add_to_group(clock_uart13, 0); + freq = clock_get_frequency(clock_uart13); } else if (ptr == HPM_UART14) { - clock_name = clock_uart14; - } else if (ptr == HPM_UART15) { - clock_name = clock_uart15; + clock_add_to_group(clock_uart14, 0); + freq = clock_get_frequency(clock_uart14); } else { - /* Unsupported instance */ - need_init_clock = false; - } - - if (need_init_clock) { - clock_set_source_divider(clock_name, clk_src_osc24m, 1); - clock_add_to_group(clock_name, 0); - freq = clock_get_frequency(clock_name); + /* Not supported */ } - return freq; } - uint32_t board_init_spi_clock(SPI_Type *ptr) { uint32_t freq = 0; if (ptr == HPM_SPI0) { /* SPI0 clock configure */ clock_add_to_group(clock_spi0, 0); - clock_set_source_divider(clock_spi0, clk_src_pll1_clk1, 5U); - freq = clock_get_frequency(clock_spi0); } else if (ptr == HPM_SPI1) { /* SPI1 clock configure */ clock_add_to_group(clock_spi1, 0); - clock_set_source_divider(clock_spi1, clk_src_pll1_clk1, 5U); - freq = clock_get_frequency(clock_spi1); } else if (ptr == HPM_SPI2) { /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); - clock_set_source_divider(clock_spi2, clk_src_pll1_clk1, 5U); - freq = clock_get_frequency(clock_spi2); } else if (ptr == HPM_SPI3) { /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); - clock_set_source_divider(clock_spi3, clk_src_pll1_clk1, 5U); - freq = clock_get_frequency(clock_spi3); } else { @@ -547,15 +542,15 @@ void board_init_cap_touch(void) gpio_set_pin_output_with_initial(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); board_delay_ms(1); - gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 1); - board_delay_ms(10); + gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + board_delay_ms(1); gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); + board_delay_ms(55); + gpio_set_pin_input(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); - gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); board_init_i2c(BOARD_CAP_I2C_BASE); } - void board_init_gpio_pins(void) { init_gpio_pins(); @@ -611,22 +606,12 @@ void board_init_cam_pins(void) init_cam_pins(HPM_CAM0); } -void board_init_usb_pins(void) -{ - /* set pull-up for USBx OC pin and ID pin */ - init_usb_pins(HPM_USB0); - - /* configure USBx ID pin as input function */ - gpio_set_pin_input(BOARD_USB0_ID_PORT, BOARD_USB0_ID_GPIO_INDEX, BOARD_USB0_ID_GPIO_PIN); - - /* configure USBx OC Flag pin as input function */ - gpio_set_pin_input(BOARD_USB0_OC_PORT, BOARD_USB0_OC_GPIO_INDEX, BOARD_USB0_OC_GPIO_PIN); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +void board_init_usb(USB_Type *ptr) { - (void) usb_index; - (void) level; + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + } } void board_init_pmp(void) @@ -668,96 +653,43 @@ void board_init_clock(void) sysctl_clock_set_preset(HPM_SYSCTL, sysctl_preset_1); } - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_axi0, 0); clock_add_to_group(clock_axi1, 0); clock_add_to_group(clock_axi2, 0); clock_add_to_group(clock_ahb, 0); - clock_add_to_group(clock_femc, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xpi0, 0); clock_add_to_group(clock_xpi1, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_gptmr4, 0); - clock_add_to_group(clock_gptmr5, 0); - clock_add_to_group(clock_gptmr6, 0); - clock_add_to_group(clock_gptmr7, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_display, 0); - clock_add_to_group(clock_sdxc0, 0); - clock_add_to_group(clock_sdxc1, 0); - clock_add_to_group(clock_camera0, 0); - clock_add_to_group(clock_camera1, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_eth1, 0); - clock_add_to_group(clock_sdp, 0); - clock_add_to_group(clock_xdma, 0); clock_add_to_group(clock_ram0, 0); clock_add_to_group(clock_ram1, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_usb1, 0); - clock_add_to_group(clock_jpeg, 0); - clock_add_to_group(clock_pdma, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); clock_add_to_group(clock_mot0, 0); clock_add_to_group(clock_mot1, 0); clock_add_to_group(clock_mot2, 0); clock_add_to_group(clock_mot3, 0); - clock_add_to_group(clock_acmp, 0); - clock_add_to_group(clock_dao, 0); clock_add_to_group(clock_synt, 0); - clock_add_to_group(clock_lmm0, 0); - clock_add_to_group(clock_lmm1, 0); - clock_add_to_group(clock_pdm, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - clock_add_to_group(clock_adc3, 0); - - clock_add_to_group(clock_i2s0, 0); - clock_add_to_group(clock_i2s1, 0); - clock_add_to_group(clock_i2s2, 0); - clock_add_to_group(clock_i2s3, 0); + clock_add_to_group(clock_ptpc, 0); /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Add the CPU1 clock to Group1 */ + /* Add clocks to Group1 */ + clock_add_to_group(clock_cpu1, 1); clock_add_to_group(clock_mchtmr1, 1); - clock_add_to_group(clock_mbx1, 1); /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); - /* Bump up DCDC voltage to 1200mv */ - pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); pcfg_dcdc_switch_to_dcm_mode(HPM_PCFG); if (status_success != pllctl_init_int_pll_with_freq(HPM_PLLCTL, 0, BOARD_CPU_FREQ)) { - printf("Failed to set pll0_clk0 to %luHz\n", BOARD_CPU_FREQ); + printf("Failed to set pll0_clk0 to %ldHz\n", BOARD_CPU_FREQ); while (1) { } } @@ -777,10 +709,12 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) if (ptr == HPM_CAM0) { /* Configure camera clock to 24MHz */ clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera0, 0); freq = clock_get_frequency(clock_camera0); } else if (ptr == HPM_CAM1) { /* Configure camera clock to 24MHz */ clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera1, 0); freq = clock_get_frequency(clock_camera1); } else { /* Invalid camera instance */ @@ -788,22 +722,11 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) return freq; } -uint32_t board_init_lcd_clock(void) -{ - uint32_t freq; - clock_add_to_group(clock_display, 0); - /* Configure LCDC clock to 29.7MHz */ - clock_set_source_divider(clock_display, clk_src_pll4_clk0, 20U); - freq = clock_get_frequency(clock_display); - return freq; -} - uint32_t board_init_dao_clock(void) { clock_add_to_group(clock_dao, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + board_config_i2s_clock(DAO_I2S, 48000); return clock_get_frequency(clock_dao); } @@ -812,8 +735,7 @@ uint32_t board_init_pdm_clock(void) { clock_add_to_group(clock_pdm, 0); - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + board_config_i2s_clock(PDM_I2S, 16000); return clock_get_frequency(clock_pdm); } @@ -828,32 +750,6 @@ void board_init_i2s_pins(I2S_Type *ptr) init_i2s_pins(ptr); } -uint32_t board_init_i2s_clock(I2S_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_I2S0) { - clock_add_to_group(clock_i2s0, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); - - freq = clock_get_frequency(clock_i2s0); - } else if (ptr == HPM_I2S1) { - clock_add_to_group(clock_i2s1, 0); - - sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); - sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); - - freq = clock_get_frequency(clock_i2s1); - } else { - ; - } - - return freq; -} - -/* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { uint32_t freq = 0; @@ -893,12 +789,12 @@ void board_init_adc16_pins(void) init_adc16_pins(); } -uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -906,9 +802,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); - } else if (ptr == HPM_ADC1) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -916,9 +813,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc1, clk_adc_src_ana1); clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc1, 0); freq = clock_get_frequency(clock_adc1); - } else if (ptr == HPM_ADC2) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); } else { @@ -926,18 +824,10 @@ uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc2, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); } + clock_add_to_group(clock_adc2, 0); freq = clock_get_frequency(clock_adc2); - } - - return freq; -} - -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) -{ - uint32_t freq = 0; - - if (ptr == HPM_ADC3) { - if (clk_src_ahb) { + } else if (ptr == (void *)HPM_ADC3) { + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); } else { @@ -945,13 +835,24 @@ uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) clock_set_adc_source(clock_adc3, clk_adc_src_ana2); clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); } - + clock_add_to_group(clock_adc3, 0); freq = clock_get_frequency(clock_adc3); } return freq; } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + void board_init_can(CAN_Type *ptr) { init_can_pins(ptr); @@ -963,18 +864,22 @@ uint32_t board_init_can_clock(CAN_Type *ptr) if (ptr == HPM_CAN0) { /* Set the CAN0 peripheral clock to 80MHz */ clock_set_source_divider(clock_can0, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can0, 0); freq = clock_get_frequency(clock_can0); } else if (ptr == HPM_CAN1) { /* Set the CAN1 peripheral clock to 80MHz */ clock_set_source_divider(clock_can1, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can1, 0); freq = clock_get_frequency(clock_can1); } else if (ptr == HPM_CAN2) { /* Set the CAN2 peripheral clock to 80MHz */ clock_set_source_divider(clock_can2, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can2, 0); freq = clock_get_frequency(clock_can2); } else if (ptr == HPM_CAN3) { /* Set the CAN3 peripheral clock to 80MHz */ clock_set_source_divider(clock_can3, clk_src_pll1_clk1, 5); + clock_add_to_group(clock_can3, 0); freq = clock_get_frequency(clock_can3); } else { /* Invalid CAN instance */ @@ -982,90 +887,18 @@ uint32_t board_init_can_clock(CAN_Type *ptr) return freq; } -uint32_t board_init_pwm_clock(PWM_Type *ptr) -{ - uint32_t freq = 0; - if (ptr == HPM_PWM0) { - clock_add_to_group(clock_mot0, 0); - freq = clock_get_frequency(clock_mot0); - } else if (ptr == HPM_PWM1) { - clock_add_to_group(clock_mot1, 0); - freq = clock_get_frequency(clock_mot1); - } else if (ptr == HPM_PWM2) { - clock_add_to_group(clock_mot2, 0); - freq = clock_get_frequency(clock_mot2); - } else if (ptr == HPM_PWM3) { - clock_add_to_group(clock_mot3, 0); - freq = clock_get_frequency(clock_mot3); - } else { - - } - return freq; -} - -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) -{ - uint32_t freq = 0; - - if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr3); - } - else if (ptr == HPM_GPTMR4) { - clock_add_to_group(clock_gptmr4, 0); - clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr4); - } - else if (ptr == HPM_GPTMR5) { - clock_add_to_group(clock_gptmr5, 0); - clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr5); - } - else if (ptr == HPM_GPTMR6) { - clock_add_to_group(clock_gptmr6, 0); - clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr6); - } - else if (ptr == HPM_GPTMR7) { - clock_add_to_group(clock_gptmr7, 0); - clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk1, 4); - freq = clock_get_frequency(clock_gptmr7); - } - else { - /* Invalid instance */ - } - return freq; -} - +#ifdef INIT_EXT_RAM_FOR_DATA /* * this function will be called during startup to initialize external memory for data use */ void _init_ext_ram(void) { uint32_t femc_clk_in_hz; - clock_add_to_group(clock_femc, 0); - board_init_sdram_pins(); - femc_clk_in_hz = board_init_femc_clock(); - femc_config_t config = {0}; femc_sdram_config_t sdram_config = {0}; + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); femc_default_config(HPM_FEMC, &config); femc_init(HPM_FEMC, &config); @@ -1075,7 +908,7 @@ void _init_ext_ram(void) sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS; sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ @@ -1098,21 +931,14 @@ void _init_ext_ram(void) femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); } - - -void board_sd_power_switch(SDXC_Type *ptr, bool on_off) -{ - /* This feature is not supported by current board*/ -} +#endif uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse) { uint32_t actual_freq = 0; do { - if (ptr != HPM_SDXC1) { - break; - } clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; + clock_add_to_group(sdxc_clk, 0); sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); /* Configure the clock below 400KHz for the identification state */ @@ -1142,6 +968,12 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver if (need_inverse) { sdxc_enable_inverse_clock(ptr, true); } + + hpm_stat_t status = clock_wait_source_stable(sdxc_clk); + if (status != status_success) { + break; + } + sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk); } while (false); @@ -1149,7 +981,6 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver return actual_freq; } - static void set_rgb_output_off(PWM_Type *ptr, uint8_t pin, uint8_t cmp_index) { pwm_cmp_config_t cmp_config = {0}; @@ -1231,8 +1062,10 @@ void board_init_beep_pwm_pins(void) hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); /* 100MHz */ } else if (ptr == HPM_ENET1) { + clock_add_to_group(clock_ptp1, BOARD_RUNNING_CORE & 0x1); clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); /* 100MHz */ } else { return status_invalid_argument; @@ -1243,21 +1076,20 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { + clock_name_t eth_clk = (ptr == HPM_ENET0) ? clock_eth0 : clock_eth1; + /* Configure Enet clock to output reference clock */ - if (ptr == HPM_ENET0 || ptr == HPM_ENET1) { - if (internal) { - /* set pll output frequency at 1GHz */ - if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { - /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 */ - pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); - /* set eth clock frequency at 50MHz for enet0 */ - clock_set_source_divider(ptr == HPM_ENET0 ? clock_eth0 : clock_eth1, clk_src_pll2_clk1, 5); - } else { - return status_fail; - } + clock_add_to_group(eth_clk, BOARD_RUNNING_CORE & 0x1); + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctl_init_int_pll_with_freq(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 */ + pllctl_set_div(HPM_PLLCTL, PLLCTL_PLL_PLL2, 1, 4); + /* set eth clock frequency at 50MHz for enet0 */ + clock_set_source_divider(eth_clk, clk_src_pll2_clk1, 5); + } else { + return status_fail; } - } else { - return status_invalid_argument; } enet_rmii_enable_clock(ptr, internal); @@ -1299,7 +1131,14 @@ uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) { - (void) ptr; + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else if (ptr == HPM_ENET1) { + intc_m_enable_irq(IRQn_ENET1); + } else { + return status_invalid_argument; + } + return status_success; } @@ -1315,7 +1154,60 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +void board_init_enet_pps_capture_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_capture_pins(); +} + void board_init_dao_pins(void) { init_dao_pins(); } + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr4); + } else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr5); + } else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr6); + } else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr7); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} + diff --git a/bsp/hpmicro/hpm6750evkmini/board/board.h b/bsp/hpmicro/hpm6750evkmini/board/board.h index c86e7704341..53f8426f664 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/board.h +++ b/bsp/hpmicro/hpm6750evkmini/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,6 +14,7 @@ #include "hpm_clock_drv.h" #include "pinmux.h" #include "hpm_lcdc_drv.h" +#include "hpm_trgm_drv.h" #ifdef CONFIG_HPM_PANEL #include "hpm_panel.h" #endif @@ -32,14 +33,16 @@ /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART13 -#define BOARD_APP_UART_IRQ IRQn_UART13 +#define BOARD_APP_UART_BASE HPM_UART13 +#define BOARD_APP_UART_IRQ IRQn_UART13 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart13 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PB24 + /* uart rx idle demo section */ #define BOARD_UART_IDLE BOARD_APP_UART_BASE #define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ @@ -66,6 +69,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -84,7 +89,7 @@ #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ #define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOZ -#define BOARD_UART_LIN_TX_PIN (9U) /* PC03 should align with used pin in pinmux configuration */ +#define BOARD_UART_LIN_TX_PIN (9U) /* PZ09 should align with used pin in pinmux configuration */ #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE @@ -94,15 +99,15 @@ #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE #if BOARD_RUNNING_CORE == HPM_CORE0 -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #else -#define BOARD_CONSOLE_UART_BASE HPM_UART13 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 +#define BOARD_CONSOLE_UART_BASE HPM_UART13 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart13 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART13 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART13_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART13_RX #endif @@ -112,15 +117,13 @@ #endif /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (16 * SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS -#define BOARD_SDRAM_REFRESH_COUNT (4096UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) -#define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (2UL) - -#define BOARD_FEMC_DQS_FLOATING 1 +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (16 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS +#define BOARD_SDRAM_REFRESH_COUNT (4096UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) /* lcd section */ #define BOARD_LCD_BASE HPM_LCDC @@ -161,17 +164,20 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ #define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR5 @@ -212,6 +218,7 @@ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOZ #define BOARD_APP_GPIO_PIN 2 +#define BOARD_BUTTON_PRESSED_VALUE 0 /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ @@ -243,9 +250,9 @@ /* Flash section */ #define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) -#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90001U) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) #define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000007U) -#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00000000U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x0000000EU) #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) #define BOARD_FLASH_SIZE (8 << 20) @@ -263,9 +270,27 @@ #define BOARD_PDMA_BASE HPM_PDMA /* i2s section */ -#define BOARD_APP_I2S_CLK_NAME clock_i2s1 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_MIC_I2S HPM_I2S0 +#define BOARD_MIC_I2S_CLK_NAME clock_i2s0 +#define BOARD_MIC_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_MIC_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX + +#define BOARD_SPEAKER_I2S HPM_I2S1 +#define BOARD_SPEAKER_I2S_CLK_NAME clock_i2s1 +#define BOARD_SPEAKER_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_SPEAKER_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S1_TX + +#define BOARD_MASTER_I2S HPM_I2S0 +#define BOARD_MASTER_I2S_CLK_NAME clock_i2s0 +#define BOARD_MASTER_I2S_RX_DATA_LINE I2S_DATA_LINE_1 +#define BOARD_MASTER_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX + +#define BOARD_SLAVE_I2S HPM_I2S0 +#define BOARD_SLAVE_I2S_CLK_NAME clock_i2s0 +#define BOARD_SLAVE_I2S_TX_DATA_LINE I2S_DATA_LINE_1 +#define BOARD_SLAVE_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S0_TX + +/* pdm selection */ #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) @@ -274,6 +299,10 @@ #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_AUXI_SNAPSHOT HPM_ENET0 +#define BOARD_ENET_AUXI_SNAPSHOT_IDX enet_ptp_auxi_snapshot_trigger_0 +#define BOARD_ENET_AUXI_SNAPSHOT_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RMII_RST_GPIO_INDEX GPIO_DO_GPIOD #define BOARD_ENET_RMII_RST_GPIO_PIN (15U) @@ -281,38 +310,6 @@ #define BOARD_ENET_RMII_INT_REF_CLK (0U) #define BOARD_ENET_RMII_PTP_CLOCK clock_ptp1 -#define BOARD_ENET1_RST_GPIO HPM_GPIO0 -#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE -#define BOARD_ENET1_RST_GPIO_PIN (26U) - -#define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET0_INT_REF_CLK (0U) -#define BOARD_ENET0_PHY_RST_TIME (30) - -#if BOARD_ENET0_INF -#define BOARD_ENET0_TX_DLY (0U) -#define BOARD_ENET0_RX_DLY (0U) -#endif - -#if __USE_ENET_PTP -#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) -#endif - -#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET1_INT_REF_CLK (0U) -#define BOARD_ENET1_PHY_RST_TIME (30) - -#if BOARD_ENET1_INF -#define BOARD_ENET1_TX_DLY (0U) -#define BOARD_ENET1_RX_DLY (0U) -#endif - -#if __USE_ENET_PTP -#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) -#endif - - - /* ADC section */ #define BOARD_APP_ADC12_NAME "ADC0" #define BOARD_APP_ADC12_BASE HPM_ADC0 @@ -325,18 +322,21 @@ #define BOARD_APP_ADC16_BASE HPM_ADC3 #define BOARD_APP_ADC16_CH_1 (2U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc3) - -#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI -#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A - -#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 -#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 -#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF -#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI -#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC12_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC12_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC12_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC12_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC12_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC0_STRGI +#define BOARD_APP_ADC12_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_mot0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_CH8REF +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_APP_ADC12_PMT_TRIG_CH ADC12_CONFIG_TRG0A #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A @@ -357,15 +357,9 @@ #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR7 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr7) -/* timer for 1ms*/ -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) - /* SDXC section */ #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SDXC_IRQ IRQn_SDXC1 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) #define BOARD_APP_SDCARD_SUPPORT_1V8 (1) #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) @@ -381,6 +375,7 @@ #endif #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_EMMC_SDXC_IRQ IRQn_SDXC1 #define BOARD_APP_EMMC_SUPPORT_3V3 (1) #define BOARD_APP_EMMC_SUPPORT_1V8 (0) #define BOARD_APP_EMMC_SUPPORT_4BIT (1) @@ -392,15 +387,6 @@ #define BOARD_APP_EMMC_VSEL_PIN IOC_PAD_PD29 #endif -/* USB section */ -#define BOARD_USB0_ID_PORT (HPM_GPIO0) -#define BOARD_USB0_ID_GPIO_INDEX (GPIO_DO_GPIOF) -#define BOARD_USB0_ID_GPIO_PIN (10) - -#define BOARD_USB0_OC_PORT (HPM_GPIO0) -#define BOARD_USB0_OC_GPIO_INDEX (GPIO_DI_GPIOF) -#define BOARD_USB0_OC_GPIO_PIN (8) - /* APP PWM */ #define BOARD_APP_PWM HPM_PWM0 #define BOARD_APP_PWM_CLOCK_NAME clock_mot0 @@ -486,17 +472,28 @@ /*Timer define*/ -#define BOARD_TMR_1MS HPM_GPTMR2 -#define BOARD_TMR_1MS_CH 0 -#define BOARD_TMR_1MS_CMP 0 -#define BOARD_TMR_1MS_IRQ IRQn_GPTMR2 -#define BOARD_TMR_1MS_RELOAD (100000U) - -#define BOARD_BLDC_TMR_1MS BOARD_TMR_1MS -#define BOARD_BLDC_TMR_CH BOARD_TMR_1MS_CH -#define BOARD_BLDC_TMR_CMP BOARD_TMR_1MS_CMP -#define BOARD_BLDC_TMR_IRQ BOARD_TMR_1MS_IRQ -#define BOARD_BLDC_TMR_RELOAD BOARD_TMR_1MS_RELOAD +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) /*adc*/ #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC12 @@ -513,11 +510,12 @@ #define BOARD_BLDC_ADC_TRG ADC12_CONFIG_TRG1A #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) #define BOARD_BLDC_PWM_TRIG_CMP_INDEX (8U) -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM1_INPUT_SRC_PWM1_CH8REF -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_ADC TRGM_TRGOCFG_ADCX_PTRGI0A +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM1_INPUT_SRC_PWM1_CH8REF + #define BOARD_BLDC_ADC_IRQn IRQn_ADC0 -#define BOARD_CPU_FREQ (648000000UL) +#define BOARD_CPU_FREQ (816000000UL) #define BOARD_APP_DISPLAY_CLOCK clock_display @@ -534,11 +532,32 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR4 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr4 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_mot0 + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR4 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR4 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr4 +#define BOARD_THREADX_TIMER HPM_GPTMR4 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr4 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR4 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR4 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr4 + #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE 0 #endif @@ -547,6 +566,35 @@ #define BOARD_TAMP_ACTIVE_CH 8 #define BOARD_TAMP_LOW_LEVEL_CH 10 +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOD +#define BOARD_I2S_SPI_CS_GPIO_PIN 25 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PD25 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 0 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 1 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR5 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 3 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr5 + +/* BGPR */ +#define BOARD_BGPR HPM_BGPR + +#define BOARD_APP_CLK_REF_PIN_NAME "P2[16]" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref1 + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -559,6 +607,7 @@ void board_init_console(void); void board_init_core1(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_lcd(void); void board_lcd_backlight(bool is_on); @@ -592,33 +641,22 @@ uint32_t board_init_uart_clock(UART_Type *ptr); /* Initialize the CAM(camera) dot clock */ uint32_t board_init_cam_clock(CAM_Type *ptr); -/* Initialize the LCD pixel clock */ -uint32_t board_init_lcd_clock(void); - -uint32_t board_init_uart_clock(UART_Type *ptr); - uint32_t board_init_spi_clock(SPI_Type *ptr); -uint32_t board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +void board_init_acmp_clock(ACMP_Type *ptr); uint32_t board_init_can_clock(CAN_Type *ptr); -uint32_t board_init_pwm_clock(PWM_Type *ptr); - hpm_stat_t board_set_audio_pll_clock(uint32_t freq); void board_init_i2s_pins(I2S_Type *ptr); -uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); -uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); void board_init_sd_pins(SDXC_Type *ptr); - uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); void board_sd_switch_pins_to_1v8(SDXC_Type *ptr); bool board_sd_detect_card(SDXC_Type *ptr); @@ -627,11 +665,11 @@ void board_init_dao_pins(void); void board_init_adc12_pins(void); void board_init_adc16_pins(void); - -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_acmp_pins(void); +void board_init_usb(USB_Type *ptr); void board_init_enet_pps_pins(ENET_Type *ptr); +void board_init_enet_pps_capture_pins(ENET_Type *ptr); uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); @@ -671,7 +709,11 @@ uint8_t board_get_led_pwm_off_level(void); */ uint8_t board_get_led_gpio_off_level(void); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); + +void board_init_clk_ref_pin(void); + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld similarity index 78% rename from bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld index 87e8489a730..21ea55a2cb6 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -86,12 +89,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -116,12 +119,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -155,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -167,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -187,22 +208,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -230,10 +255,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -254,7 +279,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -279,7 +306,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -290,8 +318,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt_enet.ld similarity index 80% rename from bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt_enet.ld index 705d3d328a2..d46f1913fff 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 16M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1280K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -106,16 +109,12 @@ SECTIONS KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -173,6 +172,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -181,6 +194,20 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -201,22 +228,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -244,10 +275,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -268,7 +299,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -293,7 +326,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -304,8 +338,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -324,7 +361,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_sdram_rtt.ld similarity index 77% rename from bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld rename to bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_sdram_rtt.ld index 9e97c660112..cae486ba987 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/flash_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,9 +14,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -82,16 +85,16 @@ SECTIONS KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - + /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > AXI_SRAM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -149,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -161,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -176,6 +203,7 @@ SECTIONS __bss_end__ = .; } > AXI_SRAM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); __tbss_start__ = .; @@ -185,17 +213,20 @@ SECTIONS __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -223,10 +254,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -247,9 +278,12 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -260,8 +294,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld similarity index 68% rename from bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld index 731fbafe63d..cc221f78bf7 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,10 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K + AXI_SRAM1 (w) : ORIGIN = 0x01100000, LENGTH = 768K NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -87,63 +88,53 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); + . = ALIGN(8); } > AXI_SRAM + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > AXI_SRAM + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > AXI_SRAM + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > AXI_SRAM + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > DLM - - .tdata : AT(etext) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - . = ALIGN(8); - __tdata_end__ = .; - } > DLM - - .data : AT(etext + __tdata_end__ - __tdata_start__) { - . = ALIGN(8); + /* NOTE: + Please keep in mind that the load section for rw data is after .text section + Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section + and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: + 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ + 2. the generated binary file will be larger because the space occupied by + NOLOAD sections will be filled + */ + __data_load_addr__ = __etext; + .data : AT(__data_load_addr__) { __data_start__ = .; + . = ALIGN(8); __global_pointer$ = . + 0x800; *(.data) *(.data*) @@ -169,10 +160,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -193,17 +184,19 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > DLM + } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { PROVIDE(__ramfunc_start__ = .); + . = ALIGN(8); *(.fast) . = ALIGN(8); PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -211,11 +204,64 @@ SECTIONS . = ALIGN(8); } > NONCACHEABLE_RAM + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + /* Note: Place all NOLOAD sections together */ + .tbss(NOLOAD) : { + . += SIZEOF(.noncacheable.init); + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM1 + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM1 + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -238,11 +284,11 @@ SECTIONS PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); PROVIDE (__rt_rvstack = .); - } > DLM + } > AXI_SRAM1 .framebuffer (NOLOAD) : { KEEP(*(.framebuffer)) - } > AXI_SRAM + } > AXI_SRAM1 .heap (NOLOAD) : { . = ALIGN(8); @@ -250,12 +296,11 @@ SECTIONS . += HEAP_SIZE; __heap_end__ = .; - } > AXI_SRAM + } > AXI_SRAM1 .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_sdram_rtt.ld similarity index 70% rename from bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld rename to bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_sdram_rtt.ld index 1e7c3e6fcd3..d702772429f 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6750evkmini/board/linker_scripts/gcc/ram_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -12,9 +12,9 @@ NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 4M; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1536K + ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K + DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 1536K NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + SDRAM_SIZE - NONCACHEABLE_SIZE, LENGTH = NONCACHEABLE_SIZE SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - NONCACHEABLE_SIZE AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k @@ -87,61 +87,51 @@ SECTIONS /* RT-Thread related sections - end */ + /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; KEEP(*(.usbh_class_info)) __usbh_class_info_end__ = .; - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); } > AXI_SRAM .rel : { KEEP(*(.rel*)) } > AXI_SRAM + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > AXI_SRAM + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > AXI_SRAM + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + . = ALIGN(8); + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .fast_ram (NOLOAD) : { KEEP(*(.fast_ram)) } > DLM - .bss(NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - /* Note: .tbss and .tdata should be adjacent */ - .tbss(NOLOAD) : { - . = ALIGN(8); - __tbss_start__ = .; - *(.tbss*) - *(.tcommon*) - _end = .; - __tbss_end__ = .; - } > AXI_SRAM - - .tdata : AT(etext) { - . = ALIGN(8); - __tdata_start__ = .; - __thread_pointer = .; - *(.tdata) - *(.tdata*) - . = ALIGN(8); - __tdata_end__ = .; - } > AXI_SRAM - - .data : AT(etext + __tdata_end__ - __tdata_start__) { + /* NOTE: + Please keep in mind that the load section for rw data is after .text section + Here end user should avoid place any NOLOAD sections (such as .bss) in the space between .text section + and data load section if all sections are placed into the same adjacent space. Otherwise, the following conditions must be taken into account: + 1. The size for all NOLOAD sections smust be added during computing __data_load_addr__ + 2. the generated binary file will be larger because the space occupied by + NOLOAD sections will be filled + */ + __data_load_addr__ = __etext; + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -169,10 +159,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -195,7 +185,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = __data_load_addr__ + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -203,7 +194,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = __fast_load_addr__ + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -211,11 +203,63 @@ SECTIONS . = ALIGN(8); } > NONCACHEABLE_RAM + __fast_ram_init_load_addr__ = __noncacheable_init_load_addr__ + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + /* Note: .tbss and .tdata should be adjacent */ + __tdata_load_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + /* Note: Place all NOLOAD sections together */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -231,10 +275,6 @@ SECTIONS KEEP(*(.backup_sram)) } > APB_SRAM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c index 33d93cd5dd2..68ce3d99ad3 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.c +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -159,103 +159,71 @@ void init_i2c_pins(I2C_Type *ptr) } } } - -void init_sdram_pins(void) -{ - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_FEMC_DQ_14; - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_DQ_15; - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_FEMC_DQ_12; - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_FEMC_DQ_13; - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_DQ_00; - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_DQ_10; - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_FEMC_DQ_11; - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_FEMC_DQ_01; - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_FEMC_DQ_08; - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_FEMC_DQ_09; - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_DQ_04; - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_FEMC_DQ_03; - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_FEMC_DQ_02; - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_DQ_07; - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_FEMC_DQ_06; - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_DQ_05; - - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_A_11; - HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_A_09; - HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_A_10; - HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_A_08; - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_A_07; - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_A_06; - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_A_01; - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_A_00; - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_A_05; - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_A_04; - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_A_03; - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_A_02; - - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_BA1; - HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_BA0; - HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_FEMC_CLK; - HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_FEMC_CKE; - HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_CS_0; - HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_RAS; - HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_FEMC_CAS; - HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PC24_FUNC_CTL_FEMC_WE; - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_DM_0; - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_DM_1; -} - -void init_sram_pins(void) -{ - /* Non-MUX */ /* MUX */ - HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A0 */ /* A16 */ - HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A1 */ /* A17 */ - HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A2 */ /* A18 */ - HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A3 */ /* A19 */ - HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A4 */ /* A20 */ - HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A5 */ /* A21 */ - HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A6 */ /* A22 */ - HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A7 */ /* A23 */ - HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A8 */ - HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A9 */ - HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A10 */ - HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A11 */ - HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A12 */ - HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A13 */ - HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A14 */ - HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A15 */ - HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A16 */ - HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A17 */ - HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A18 */ - HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A19 */ - HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A20 */ - HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A21 */ - HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A22 */ - HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* A23 */ - - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D0 */ /* AD0 */ - HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D1 */ /* AD1 */ - HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D2 */ /* AD2 */ - HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D3 */ /* AD3 */ - HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D4 */ /* AD4 */ - HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D5 */ /* AD5 */ - HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D6 */ /* AD6 */ - HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D7 */ /* AD7 */ - HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D8 */ /* AD8 */ - HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D9 */ /* AD9 */ - HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D10 */ /* AD10 */ - HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D11 */ /* AD11 */ - HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D12 */ /* AD12 */ - HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D13 */ /* AD13 */ - HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D14 */ /* AD14 */ - HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* D15 */ /* AD15 */ - - HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #CE */ - HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #OE */ - HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #WE */ - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #UB */ - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #LB */ - HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* #ADV */ +void init_femc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #WE */ + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #ADV */ + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC24].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #LB */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #UB */ + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #CE */ + HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12); /* SRAM #OE */ } void init_gpio_pins(void) @@ -277,16 +245,31 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PE03].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PD30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PD31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } else if (ptr == HPM_SPI2) { HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_SPI2_CSN; HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } else if (ptr == HPM_SPI3) { HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_SPI3_CSN; HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB29].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } } @@ -297,16 +280,31 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI1_MOSI; HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_SPI1_MISO; HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SPI1_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PE03].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PD30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PD31].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } else if (ptr == HPM_SPI2) { HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_SPI2_MOSI; HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_SPI2_MISO; HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB22].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PB25].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PB21].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } else if (ptr == HPM_SPI3) { HPM_IOC->PAD[IOC_PAD_PB29].FUNC_CTL = IOC_PB29_FUNC_CTL_GPIO_B_29; HPM_IOC->PAD[IOC_PAD_PB30].FUNC_CTL = IOC_PB30_FUNC_CTL_SPI3_MOSI; HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_SPI3_MISO; HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); + + HPM_IOC->PAD[IOC_PAD_PB29].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB30].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PC03].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PC02].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(6) | IOC_PAD_PAD_CTL_PE_SET(1); } } @@ -315,7 +313,7 @@ void init_pins(void) #ifdef BOARD_CONSOLE_UART_BASE init_uart_pins(BOARD_CONSOLE_UART_BASE); #endif - init_sdram_pins(); + init_femc_pins(); } void init_gptmr_pins(GPTMR_Type *ptr) @@ -327,6 +325,14 @@ void init_gptmr_pins(GPTMR_Type *ptr) HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_GPTMR5_COMP_0; /* TMR5 compare 1*/ HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPTMR5_COMP_1; + /* TMR5 compare 2*/ + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; + trgm_enable_io_output(HPM_TRGM2, 1 << 10); + trgm_output_t trgm2IoConfig0; + trgm2IoConfig0.invert = 0; + trgm2IoConfig0.type = trgm_output_same_as_input; + trgm2IoConfig0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2IoConfig0); } } @@ -472,13 +478,8 @@ void init_adc_bldc_pins(void) void init_usb_pins(USB_Type *ptr) { if (ptr == HPM_USB0) { - /* USB0 ID */ - HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_GPIO_F_10; - HPM_IOC->PAD[IOC_PAD_PF10].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); - - /* USB0 OC */ - HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; - HPM_IOC->PAD[IOC_PAD_PF08].PAD_CTL = IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1); + HPM_IOC->PAD[IOC_PAD_PF10].FUNC_CTL = IOC_PF10_FUNC_CTL_USB0_ID; + HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_USB0_OC; } } @@ -541,7 +542,7 @@ void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) /* SDXC1.DATA0 */ HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD18].PAD_CTL = pad_ctl; - if ((width == 4)) { + if (width == 4) { /* SDXC1.DATA1 */ HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = func_ctl; HPM_IOC->PAD[IOC_PAD_PD17].PAD_CTL = pad_ctl; @@ -598,7 +599,12 @@ void init_enet_pps_pins(void) { HPM_IOC->PAD[IOC_PAD_PF05].FUNC_CTL = IOC_PF05_FUNC_CTL_ETH0_EVTO_0; HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_ETH0_EVTO_1; - HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_ETH0_EVTO_2; +} + +void init_enet_pps_capture_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_ETH0_EVTI_0; + HPM_IOC->PAD[IOC_PAD_PF01].FUNC_CTL = IOC_PF01_FUNC_CTL_ETH0_EVTI_1; } void init_tamper_pins(void) @@ -607,3 +613,47 @@ void init_tamper_pins(void) HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = BIOC_PZ09_FUNC_CTL_TAMP_09; HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = BIOC_PZ10_FUNC_CTL_TAMP_10; } + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PB24].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PB24].FUNC_CTL = IOC_PB24_FUNC_CTL_GPIO_B_24; +} + + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR5) { + if (as_comp == true) { + switch (channel) { + case 0: + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_GPTMR5_COMP_0; + break; + case 1: + HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPTMR5_COMP_1; + break; + case 2: + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PD24_FUNC_CTL_TRGM2_P_10; + trgm_enable_io_output(HPM_TRGM2, 1 << 10); + trgm_output_t trgm2IoConfig0; + trgm2IoConfig0.invert = 0; + trgm2IoConfig0.type = trgm_output_same_as_input; + trgm2IoConfig0.input = HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2; + trgm_output_config(HPM_TRGM2, HPM_TRGM2_OUTPUT_SRC_TRGM2_P10, &trgm2IoConfig0); + break; + default: + break; + } + } else { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPTMR5_CAPT_1; + } + } + } +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_SOC_REF1; +} diff --git a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h index f8689ccf042..1ae0f3ffad9 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/pinmux.h +++ b/bsp/hpmicro/hpm6750evkmini/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2024 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -17,8 +17,7 @@ void init_uart_pin_as_gpio(UART_Type *ptr); void init_lcd_pins(LCDC_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_cap_pins(void); -void init_sdram_pins(void); -void init_sram_pins(void); +void init_femc_pins(void); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); @@ -54,8 +53,11 @@ void init_led_pins_as_pwm(void); void init_led_pins_as_gpio(void); void init_trgmux_pins(uint32_t pin); void init_enet_pps_pins(void); +void init_enet_pps_capture_pins(void); void init_tamper_pins(void); - +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pin(void); #ifdef __cplusplus } #endif diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c index 41b5b9e7b37..056bd3902f1 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024 HPMicro + * Copyright (c) 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -15,20 +15,13 @@ #include #include #include "hpm_dma_mgr.h" +#include "hpm_l1c_drv.h" #include "hpm_mchtmr_drv.h" extern int rt_hw_uart_init(void); void os_tick_config(void); void rtt_board_init(void); -void rt_hw_board_init(void) -{ - rtt_board_init(); - - /* Call the RT-Thread Component Board Initialization */ - rt_components_board_init(); -} - void os_tick_config(void) { sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); @@ -37,8 +30,14 @@ void os_tick_config(void) enable_mchtmr_irq(); } +void rtt_os_tick_clock(void) +{ + clock_add_to_group(clock_mchtmr0, 0); +} + void rtt_board_init(void) { + rtt_os_tick_clock(); board_init_clock(); board_init_console(); board_init_pmp(); @@ -60,6 +59,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); @@ -98,19 +98,12 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); -} - -ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) -{ - HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; - - rt_tick_increase(); + board_init_usb(HPM_USB0); } void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->RESET_HOT &= ~(1UL << 31); HPM_PPOR->RESET_COLD |= (1UL << 31); @@ -132,3 +125,139 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc12_clock(ADC12_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana1, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } else if (ptr == HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc2, 0); + freq = clock_get_frequency(clock_adc2); + } + + return freq; +} + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC3) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from pll1_clk1 divided by 2 (@200MHz by default) */ + clock_set_adc_source(clock_adc3, clk_adc_src_ana2); + clock_set_source_divider(clock_ana2, clk_src_pll1_clk1, 2U); + } + clock_add_to_group(clock_adc3, 0); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud0, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s0, clock_source_i2s_aud0_clk); + + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + + sysctl_config_clock(HPM_SYSCTL, clock_node_aud1, clock_source_pll3_clk0, 25); + sysctl_set_adc_i2s_clock_mux(HPM_SYSCTL, clock_node_i2s1, clock_source_i2s_aud1_clk); + + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_mot0, 0); + freq = clock_get_frequency(clock_mot0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_mot1, 0); + freq = clock_get_frequency(clock_mot1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_mot2, 0); + freq = clock_get_frequency(clock_mot2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_mot3, 0); + freq = clock_get_frequency(clock_mot3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) + +#ifdef HPM_USB1_BASE +extern void hpm_isr_usb1(void); +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, hpm_isr_usb1) +#endif +#endif + + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h index 474555a89a0..03a9f038369 100644 --- a/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h +++ b/bsp/hpmicro/hpm6750evkmini/board/rtt_board.h @@ -11,6 +11,9 @@ #include "hpm_soc.h" /* gpio section */ +#define APP_LED0 (0U) +#define APP_LED1 (1U) +#define APP_LED2 (2U) #define APP_LED0_GPIO_CTRL HPM_GPIO0 #define APP_LED0_GPIO_INDEX GPIO_DI_GPIOB #define APP_LED0_GPIO_PIN 19 @@ -20,14 +23,20 @@ #define APP_LED2_GPIO_CTRL HPM_GPIO0 #define APP_LED2_GPIO_INDEX GPIO_DI_GPIOB #define APP_LED2_GPIO_PIN 20 -#define APP_LED_ON (1) -#define APP_LED_OFF (0) +#define APP_LED_ON (0) +#define APP_LED_OFF (1) /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* SPI WIFI section */ #define RW007_RST_PIN (IOC_PAD_PE02) #define RW007_INT_BUSY_PIN (IOC_PAD_PE01) @@ -52,6 +61,36 @@ #define IRQn_PendSV IRQn_DEBUG_0 +#define BOARD_ENET0_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) + +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif + +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + +#define BOARD_ENET1_RST_GPIO HPM_GPIO0 +#define BOARD_ENET1_RST_GPIO_INDEX GPIO_DO_GPIOE +#define BOARD_ENET1_RST_GPIO_PIN (26U) + +#define BOARD_ENET1_INF (0U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET1_INT_REF_CLK (0U) +#define BOARD_ENET1_PHY_RST_TIME (30) + +#if BOARD_ENET1_INF +#define BOARD_ENET1_TX_DLY (0U) +#define BOARD_ENET1_RX_DLY (0U) +#endif + +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET1_PTP_CLOCK (clock_ptp1) +#endif + /*************************************************************** * * RT-Thread related definitions diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.h b/bsp/hpmicro/hpm6750evkmini/rtconfig.h index 3114aeb78ef..eb9507e6b97 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.h +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -76,6 +76,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -104,6 +105,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -136,8 +139,9 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_USING_RTC #define RT_USING_PIN /* end of Device Drivers */ @@ -300,6 +304,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -379,17 +397,21 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM6700_SERIES /* Hardware Drivers Config */ -#define SOC_HPM6000 +#define SOC_HPM6700 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 -#define BSP_USING_RTC +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 #define BSP_USING_FEMC #define INIT_EXT_RAM_FOR_DATA /* end of On-chip Peripheral Drivers */ diff --git a/bsp/hpmicro/hpm6750evkmini/rtconfig.py b/bsp/hpmicro/hpm6750evkmini/rtconfig.py index 0f29ec05180..d0b944eb3fa 100644 --- a/bsp/hpmicro/hpm6750evkmini/rtconfig.py +++ b/bsp/hpmicro/hpm6750evkmini/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c index b0bab335d52..4fc6914d566 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/startup.c @@ -1,128 +1,139 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include - -void system_init(void); - -extern int entry(void); - -extern void __libc_init_array(void); -extern void __libc_fini_array(void); - -void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_irq_from_intc(); - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#ifndef CONFIG_NOT_ENABLE_ICACHE - l1c_ic_enable(); -#endif -#ifndef CONFIG_NOT_ENABLE_DCACHE - l1c_dc_enable(); -#endif -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; -#ifdef FLASH_XIP - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - extern uint8_t __etext[]; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tbss_start__[], __tbss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - - /* tbss section */ - size = __tbss_end__ - __tbss_start__; - for (i = 0; i < size; i++) { - *(__tbss_start__ + i) = 0; - } - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* tdata section LMA: etext */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc length */ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); - } -} - -__attribute__((weak)) int main(void) -{ - while(1); -} - -void reset_handler(void) -{ - /** - * Disable preemptive interrupt + #include "hpm_common.h" + #include "hpm_soc.h" + #include "hpm_l1c_drv.h" + #include + + void system_init(void); + + extern int entry(void); + + extern void __libc_init_array(void); + extern void __libc_fini_array(void); + + void system_init(void) + { + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); + #ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); + #endif + #ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); + #endif + } + + __attribute__((weak)) void c_startup(void) + { + #ifndef __SES_RISCV + uint32_t i, size; + #ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } + #endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } + /* NOTE: Invalid I-Cache in case the I-Cache was filled with incorrect data during prefetch before copying the ram + * function code to its destination. */ - HPM_PLIC->FEATURE = 0; - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - c_startup(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Do global constructors */ - __libc_init_array(); - - - - /* Entry function */ - entry(); -} - - -__attribute__((weak)) void _init() -{ -} + fencei(); + #endif + } + + __attribute__((weak)) int main(void) + { + while(1); + } + + void reset_handler(void) + { + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + + #ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); + #endif + + /* Entry function */ + entry(); + } + + + __attribute__((weak)) void _init(void) + { + } + \ No newline at end of file diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S index 238e05b43bb..5ac683dbc27 100644 --- a/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6750evkmini/startup/HPM6750/toolchains/gcc/start.S @@ -75,7 +75,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6800evk/.config b/bsp/hpmicro/hpm6800evk/.config index 5b5c6e2dede..d53b9524580 100644 --- a/bsp/hpmicro/hpm6800evk/.config +++ b/bsp/hpmicro/hpm6800evk/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -187,6 +185,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -203,6 +204,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -253,13 +255,7 @@ CONFIG_RT_SERIAL_USING_DMA=y # CONFIG_RT_USING_PM is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SOFT_SPI is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set +# CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -386,6 +382,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -493,6 +490,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -582,6 +580,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -627,6 +626,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -720,6 +720,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -801,6 +802,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -843,6 +846,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -856,6 +863,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1027,6 +1059,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1365,26 +1398,37 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM6800_SERIES=y + # # Hardware Drivers Config # -CONFIG_SOC_HPM6000=y +CONFIG_SOC_HPM6800=y # # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_UART0_RX_USING_DMA is not set # CONFIG_BSP_UART0_TX_USING_DMA is not set CONFIG_BSP_UART0_RX_BUFSIZE=128 CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set CONFIG_BSP_USING_UART3=y # CONFIG_BSP_UART3_RX_USING_DMA is not set # CONFIG_BSP_UART3_TX_USING_DMA is not set CONFIG_BSP_UART3_RX_BUFSIZE=1024 CONFIG_BSP_UART3_TX_BUFSIZE=0 +CONFIG_BSP_UART3_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set # CONFIG_BSP_USING_ETH is not set @@ -1395,7 +1439,6 @@ CONFIG_BSP_UART3_TX_BUFSIZE=0 # CONFIG_BSP_USING_PDMA is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set -# CONFIG_BSP_USING_FEMC is not set # CONFIG_INIT_EXT_RAM_FOR_DATA is not set # CONFIG_BSP_USING_XPI_FLASH is not set # CONFIG_BSP_USING_DAO is not set @@ -1412,6 +1455,8 @@ CONFIG_BSP_UART3_TX_BUFSIZE=0 # CONFIG_BSP_USING_PIXELMUX is not set # CONFIG_BSP_USING_MIPI_CSI is not set # CONFIG_BSP_USING_MIPI_DSI is not set +# CONFIG_BSP_USING_LVB is not set +# CONFIG_BSP_USING_LCB is not set # CONFIG_BSP_USING_RTT_LCD_DRIVER is not set # end of On-chip Peripheral Drivers # end of Hardware Drivers Config diff --git a/bsp/hpmicro/hpm6800evk/SConstruct b/bsp/hpmicro/hpm6800evk/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6800evk/SConstruct +++ b/bsp/hpmicro/hpm6800evk/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6800evk/board/Kconfig b/bsp/hpmicro/hpm6800evk/board/Kconfig index 44139d760f1..9e8d58ad4e2 100644 --- a/bsp/hpmicro/hpm6800evk/board/Kconfig +++ b/bsp/hpmicro/hpm6800evk/board/Kconfig @@ -1,8 +1,8 @@ menu "Hardware Drivers Config" -config SOC_HPM6000 +config SOC_HPM6800 bool - select SOC_SERIES_HPM6000 + select SOC_HPM6800_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -11,11 +11,23 @@ config BSP_USING_ENET_PHY_RTL8211 bool default n +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -44,6 +56,64 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART3 bool "Enable UART3" @@ -67,15 +137,216 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 endif endif - menuconfig BSP_USING_SPI bool "Enable SPI" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif config BSP_USING_SPI3 bool "Enable SPI3" default n @@ -83,18 +354,43 @@ menu "On-chip Peripheral Drivers" config BSP_SPI3_USING_DMA bool "Enable SPI3 DMA" default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + if BSP_USING_ETH choice prompt "ETH" @@ -110,11 +406,43 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC" default n select RT_USING_SDIO if BSP_USING_SDXC + select RT_USING_PIN if BSP_USING_SDXC if BSP_USING_SDXC config BSP_USING_SDXC0 bool "Enable SDXC0" default n if BSP_USING_SDXC0 + config BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC0_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC0_USE_CACHEABLE_BUFFER + config BSP_SDXC0_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC0_USE_NONCACHEABLE_BUFFER + config BSP_SDXC0_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC0_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + + config BSP_SDXC0_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 choice prompt "Select BUS_WIDTH" default BSP_SDXC0_BUS_WIDTH_8BIT @@ -147,39 +475,69 @@ menu "On-chip Peripheral Drivers" bool "Enable SDXC1" default y if BSP_USING_SDXC1 - choice - prompt "Select BUS_WIDTH" - default BSP_SDXC1_BUS_WIDTH_4BIT - config BSP_SDXC1_BUS_WIDTH_1BIT - bool "1-bit" - config BSP_SDXC1_BUS_WIDTH_4BIT - bool "4-bit" - endchoice - choice - prompt "Select Voltage" - default BSP_SDXC1_VOLTAGE_3V3 - config BSP_SDXC1_VOLTAGE_3V3 - bool "3.3V" - config BSP_SDXC1_VOLTAGE_1V8 - bool "1.8V" - config BSP_SDXC1_VOLTAGE_DUAL - bool "Dual voltage 3.3V / 1.8V" - endchoice - config BSP_SDXC1_VSEL_PIN + config BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN + bool "Enable Interrupt-driven mode" + default n + choice + prompt "Select buffer type for unaligned data transfer" + default BSP_SDXC1_USE_CACHEABLE_BUFFER + config BSP_SDXC1_USE_CACHEABLE_BUFFER + bool "Use cacheable buffer" + config BSP_SDXC1_USE_NONCACHEABLE_BUFFER + bool "Use non-cacheable buffer" + endchoice + if BSP_SDXC1_USE_CACHEABLE_BUFFER + config BSP_SDXC1_CACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + endif + if BSP_SDXC1_USE_NONCACHEABLE_BUFFER + config BSP_SDXC1_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR + int "Non-cacheable buffer size in sectors(512 bytes per sector)" + range 1 1024 + default 32 + config BSP_SDXC1_NONCACHEABLE_BUF_IN_FAST_RAM + bool "Place non-cacheable buffer into FAST RAM(available only if FAST_RAM is in ILM/DLM)" + default n + endif + config BSP_SDXC1_IRQ_PRIORITY + int "SDXC Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select BUS_WIDTH" + default BSP_SDXC1_BUS_WIDTH_4BIT + config BSP_SDXC1_BUS_WIDTH_1BIT + bool "1-bit" + config BSP_SDXC1_BUS_WIDTH_4BIT + bool "4-bit" + endchoice + choice + prompt "Select Voltage" + default BSP_SDXC1_VOLTAGE_3V3 + config BSP_SDXC1_VOLTAGE_3V3 + bool "3.3V" + config BSP_SDXC1_VOLTAGE_1V8 + bool "1.8V" + config BSP_SDXC1_VOLTAGE_DUAL + bool "Dual voltage 3.3V / 1.8V" + endchoice + config BSP_SDXC1_VSEL_PIN default "PD12" - string "VSEL pin name" - config BSP_SDXC1_PWR_PIN + string "VSEL pin name" + config BSP_SDXC1_PWR_PIN default "PD07" - string "PWR pin name" - endif + string "PWR pin name" + endif endif menuconfig BSP_USING_TOUCH bool "Enable touch" default n if BSP_USING_TOUCH - config BSP_USING_TOUCH_GT911 - bool "Enable GT911" + config BSP_USING_TOUCH_GT9xx + bool "Enable GT9xx" default y config BSP_USING_TOUCH_FT5406 @@ -211,27 +569,78 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_HWTIMER if BSP_USING_GPTMR if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR3 bool "Enable GPTMR3" default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR4 bool "Enable GPTMR4" default n + if BSP_USING_GPTMR4 + config BSP_GPTMR4_IRQ_PRIORITY + int "GPTMR4 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR5 bool "Enable GPTMR5" default n + if BSP_USING_GPTMR5 + config BSP_GPTMR5_IRQ_PRIORITY + int "GPTMR5 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR6 bool "Enable GPTMR6" default n + if BSP_USING_GPTMR6 + config BSP_GPTMR6_IRQ_PRIORITY + int "GPTMR6 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR7 bool "Enable GPTMR7" default n + if BSP_USING_GPTMR7 + config BSP_GPTMR7_IRQ_PRIORITY + int "GPTMR7 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -242,32 +651,53 @@ menu "On-chip Peripheral Drivers" config BSP_USING_I2C0 bool "Enable I2C0" default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C1 bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - endif - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" - default n - endif - if BSP_USING_I2C1 - config BSP_I2C1_USING_DMA - bool "Enable I2C1 DMA" - default n - endif - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" - default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif endif - menuconfig BSP_USING_FEMC - bool "Enable DRAM" - default y menuconfig INIT_EXT_RAM_FOR_DATA bool "INIT_EXT_RAM_FOR_DATA" @@ -308,6 +738,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB Host" @@ -337,27 +768,75 @@ menu "On-chip Peripheral Drivers" config BSP_USING_MCAN0 bool "Enable MCAN0" default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN1 bool "Enable MCAN1" default n + if BSP_USING_MCAN1 + config BSP_MCAN1_IRQ_PRIORITY + int "MCAN1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN2 bool "Enable MCAN2" default n + if BSP_USING_MCAN2 + config BSP_MCAN2_IRQ_PRIORITY + int "MCAN2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN3 bool "Enable MCAN3" default n + if BSP_USING_MCAN3 + config BSP_MCAN3_IRQ_PRIORITY + int "MCAN3 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN4 bool "Enable MCAN4" default n + if BSP_USING_MCAN4 + config BSP_MCAN4_IRQ_PRIORITY + int "MCAN4 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN5 bool "Enable MCAN5" default n + if BSP_USING_MCAN5 + config BSP_MCAN5_IRQ_PRIORITY + int "MCAN5 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN6 bool "Enable MCAN6" default n + if BSP_USING_MCAN6 + config BSP_MCAN6_IRQ_PRIORITY + int "MCAN6 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN7 bool "Enable MCAN7" default n + if BSP_USING_MCAN7 + config BSP_MCAN7_IRQ_PRIORITY + int "MCAN7 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC @@ -365,20 +844,6 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_ADC if BSP_USING_ADC if BSP_USING_ADC - menuconfig BSP_USING_ADC12 - bool "Enable ADC12" - default n - if BSP_USING_ADC12 - config BSP_USING_ADC0 - bool "Enable ADC0" - default n - config BSP_USING_ADC1 - bool "Enable ADC1" - default n - config BSP_USING_ADC2 - bool "Enable ADC2" - default n - endif menuconfig BSP_USING_ADC16 bool "Enable ADC16" default n @@ -392,18 +857,19 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_CAMERA bool "Enable camera" default n + select BSP_USING_CAM if BSP_USING_CAMERA + select BSP_USING_MIPI_CSI if BSP_USING_CAMERA if BSP_USING_CAMERA - config BSP_USING_CAMERA_MT9M114 - bool "Enable mt9m114" - default y - - config BSP_USING_CAMERA_OV5640 - bool "Enable ov5640" - default n - - config BSP_USING_CAMERA_OV7725 - bool "Enable ov7725" - default n + choice + prompt "Select camera" + default BSP_USING_CAMERA_OV5640 + config BSP_USING_CAMERA_MT9M114 + bool "Enable mt9m114" + config BSP_USING_CAMERA_OV5640 + bool "Enable ov5640" + config BSP_USING_CAMERA_OV7725 + bool "Enable ov7725" + endchoice endif menuconfig BSP_USING_JPEG @@ -417,20 +883,22 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_PANEL bool "Enable panel" default n + select BSP_USING_MIPI_DSI if BSP_USING_PANEL + select BSP_USING_PIXELMUX if BSP_USING_PANEL if BSP_USING_PANEL - config BSP_USEING_PANEL_RGB_TM070RDH13 - bool "Enable RGB TM070RDH13" - default n - config BSP_USEING_PANEL_MIPI_MC10128007_31B - bool "Enable MIPI MC10128007_31B" - default y - config BSP_USEING_PANEL_LVDS_TM103XDGP01 - bool "Enable LVDS TM103XDGP01" - default n - config BSP_USEING_PANEL_LVDS_CC10128007 - bool "Enable LVDS CC10128007" - default n - endif + choice + prompt "Select Panel" + default BSP_USEING_PANEL_MIPI_MC10128007_31B + config BSP_USEING_PANEL_RGB_TM070RDH13 + bool "Enable RGB TM070RDH13" + config BSP_USEING_PANEL_MIPI_MC10128007_31B + bool "Enable MIPI MC10128007_31B" + config BSP_USEING_PANEL_LVDS_TM103XDGP01 + bool "Enable LVDS TM103XDGP01" + config BSP_USEING_PANEL_LVDS_CC10128007 + bool "Enable LVDS CC10128007" + endchoice + endif menuconfig BSP_USING_PIXELMUX bool "Enable pixelmux Driver" @@ -443,10 +911,25 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_MIPI_DSI bool "Enable MIPI DSI Driver" default n + + menuconfig BSP_USING_LVB + bool "Enable LVB Driver" + default n + + menuconfig BSP_USING_LCB + bool "Enable LCB Driver" + default n + menuconfig BSP_USING_RTT_LCD_DRIVER bool "Enable RTT LCD Driver" select BSP_USING_LCD default n + if BSP_USING_RTT_LCD_DRIVER + config BSP_RTT_LCD_IRQ_PRIORITY + int "RTT LCD Interrupt Priority" + range 1 7 + default 1 + endif endmenu endmenu diff --git a/bsp/hpmicro/hpm6800evk/board/board.c b/bsp/hpmicro/hpm6800evk/board/board.c index a483ab39051..52da53c800d 100644 --- a/bsp/hpmicro/hpm6800evk/board/board.c +++ b/bsp/hpmicro/hpm6800evk/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause * * @@ -26,8 +26,7 @@ #include "hpm_usb_drv.h" #include "hpm_mipi_dsi_drv.h" #include "hpm_mipi_dsi_phy_drv.h" - -static board_timer_cb timer_cb; +#include /** * @brief FLASH configuration option definitions: @@ -83,11 +82,11 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; +__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -102,8 +101,6 @@ void board_init_console(void) */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -202,6 +199,9 @@ void board_delay_ms(uint32_t ms) clock_cpu_delay_ms(ms); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -210,8 +210,6 @@ void board_timer_isr(void) } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); - void board_timer_create(uint32_t ms, board_timer_cb cb) { uint32_t gptmr_freq; @@ -230,6 +228,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -244,47 +243,49 @@ void board_i2c_bus_clear(I2C_Type *ptr) printf("I2C bus is ready\n"); return; } - i2s_gen_reset_signal(ptr, 9); + i2c_gen_reset_signal(ptr, 9); board_delay_ms(100); printf("I2C bus is cleared\n"); } -void board_init_i2c(I2C_Type *ptr) +uint32_t board_init_i2c_clock(I2C_Type *ptr) { - hpm_stat_t stat; - uint32_t freq; - i2c_config_t config; - - init_i2c_pins(ptr); - board_i2c_bus_clear(ptr); + uint32_t freq = 0; if (ptr == HPM_I2C0) { clock_add_to_group(clock_i2c0, 0); - clock_set_source_divider(clock_i2c0, clk_src_osc24m, 1U); freq = clock_get_frequency(clock_i2c0); } else if (ptr == HPM_I2C1) { clock_add_to_group(clock_i2c1, 0); - clock_set_source_divider(clock_i2c1, clk_src_osc24m, 1U); freq = clock_get_frequency(clock_i2c1); } else if (ptr == HPM_I2C2) { clock_add_to_group(clock_i2c2, 0); - clock_set_source_divider(clock_i2c2, clk_src_osc24m, 1U); freq = clock_get_frequency(clock_i2c2); } else if (ptr == HPM_I2C3) { clock_add_to_group(clock_i2c3, 0); - clock_set_source_divider(clock_i2c3, clk_src_osc24m, 1U); freq = clock_get_frequency(clock_i2c3); } else { - printf("invild i2c base address 0x%x\n", (uint32_t) ptr); - while (1) { - } + ; } + return freq; +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + + freq = board_init_i2c_clock(ptr); + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { - printf("failed to initialize i2c 0x%x\n", (uint32_t) ptr); + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); while (1) { } } @@ -293,15 +294,12 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_spi_clock(SPI_Type *ptr) { if (ptr == HPM_SPI1) { - /* SPI1 clock configure */ clock_add_to_group(clock_spi1, 0); return clock_get_frequency(clock_spi1); } else if (ptr == HPM_SPI2) { - /* SPI2 clock configure */ clock_add_to_group(clock_spi2, 0); return clock_get_frequency(clock_spi2); } else if (ptr == HPM_SPI3) { - /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); return clock_get_frequency(clock_spi3); } @@ -394,11 +392,10 @@ void board_init_pmp(void) assert((length & (length - 1U)) == 0U); assert((start_addr & (length - 1U)) == 0U); - pmp_entry_t pmp_entry[3] = { 0 }; + pmp_entry_t pmp_entry[4] = { 0 }; pmp_entry[0].pmp_addr = PMP_NAPOT_ADDR(0x0000000, 0x80000000); pmp_entry[0].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); - pmp_entry[1].pmp_addr = PMP_NAPOT_ADDR(0x80000000, 0x80000000); pmp_entry[1].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); @@ -406,6 +403,23 @@ void board_init_pmp(void) pmp_entry[2].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); pmp_entry[2].pma_addr = PMA_NAPOT_ADDR(start_addr, length); pmp_entry[2].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + +#ifdef CONFIG_VGLITE + extern uint32_t __gpu_start__[]; + extern uint32_t __gpu_end__[]; + uint32_t gpu_start_addr = (uint32_t) __gpu_start__; + uint32_t gpu_end_addr = (uint32_t) __gpu_end__; + uint32_t gpu_length = gpu_end_addr - gpu_start_addr; + + if (gpu_length) { + assert((gpu_length & (gpu_length - 1U)) == 0U); + assert((gpu_start_addr & (gpu_length - 1U)) == 0U); + pmp_entry[3].pmp_addr = PMP_NAPOT_ADDR(gpu_start_addr, gpu_length); + pmp_entry[3].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[3].pma_addr = PMA_NAPOT_ADDR(gpu_start_addr, gpu_length); + pmp_entry[3].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_WB_NO_ALLOC, AMO_EN); + } +#endif pmp_config(&pmp_entry[0], ARRAY_SIZE(pmp_entry)); } @@ -419,8 +433,8 @@ void board_init_display_system_clock(void) clock_add_to_group(clock_lcd0, 0); clock_add_to_group(clock_dsi0, 0); clock_add_to_group(clock_dsi1, 0); - clock_add_to_group(clock_cam0, 0); - clock_add_to_group(clock_cam1, 0); + clock_add_to_group(clock_camera0, 0); + clock_add_to_group(clock_camera1, 0); clock_add_to_group(clock_jpeg, 0); clock_add_to_group(clock_pdma, 0); } @@ -435,8 +449,7 @@ void board_init_clock(void) /* Select clock setting preset1 */ sysctl_clock_set_preset(HPM_SYSCTL, 2); } - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_ahb, 0); clock_add_to_group(clock_axic, 0); @@ -444,70 +457,24 @@ void board_init_clock(void) clock_add_to_group(clock_axiv, 0); clock_add_to_group(clock_axid, 0); clock_add_to_group(clock_axig, 0); - clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_xpi0, 0); - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - clock_add_to_group(clock_spi0, 0); - clock_add_to_group(clock_spi1, 0); - clock_add_to_group(clock_spi2, 0); - clock_add_to_group(clock_spi3, 0); - clock_add_to_group(clock_can0, 0); - clock_add_to_group(clock_can1, 0); - clock_add_to_group(clock_can2, 0); - clock_add_to_group(clock_can3, 0); - clock_add_to_group(clock_can4, 0); - clock_add_to_group(clock_can5, 0); - clock_add_to_group(clock_can6, 0); - clock_add_to_group(clock_can7, 0); - clock_add_to_group(clock_ptpc, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_sdp, 0); clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xram, 0); - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_kman, 0); + clock_add_to_group(clock_lmm0, 0); clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_hdma, 0); - clock_add_to_group(clock_rng, 0); - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_crc0, 0); - clock_add_to_group(clock_dao, 0); - clock_add_to_group(clock_pdm, 0); - clock_add_to_group(clock_smix, 0); - - clock_add_to_group(clock_i2s0, 0); - clock_add_to_group(clock_i2s1, 0); - clock_add_to_group(clock_i2s2, 0); - clock_add_to_group(clock_i2s3, 0); - - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_ffa, 0); - - clock_add_to_group(clock_tsns, 0); - + clock_add_to_group(clock_ptpc, 0); board_init_display_system_clock(); - /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); - /* Bump up DCDC voltage to 1150mv */ - pcfg_dcdc_set_voltage(HPM_PCFG, 1150); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); /* Configure PLL1_CLK0 Post Divider to 1 */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, 0, 0, 0); - pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, 0, BOARD_CPU_FREQ); + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll0, pllctlv2_clk0, pllctlv2_div_1p0); + pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll0, BOARD_CPU_FREQ); /* Configure axis to 200MHz */ clock_set_source_divider(clock_axis, clk_src_pll1_clk0, 4); @@ -532,34 +499,42 @@ uint32_t board_init_can_clock(MCAN_Type *ptr) if (ptr == HPM_MCAN0) { /* Set the CAN0 peripheral clock to 80MHz */ clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can0, 0); freq = clock_get_frequency(clock_can0); } else if (ptr == HPM_MCAN1) { /* Set the CAN1 peripheral clock to 80MHz */ clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can1, 0); freq = clock_get_frequency(clock_can1); } else if (ptr == HPM_MCAN2) { /* Set the CAN2 peripheral clock to 8MHz */ clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can2, 0); freq = clock_get_frequency(clock_can2); } else if (ptr == HPM_MCAN3) { /* Set the CAN3 peripheral clock to 80MHz */ clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can3, 0); freq = clock_get_frequency(clock_can3); } else if (ptr == HPM_MCAN4) { /* Set the CAN4 peripheral clock to 80MHz */ clock_set_source_divider(clock_can4, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can4, 0); freq = clock_get_frequency(clock_can4); } else if (ptr == HPM_MCAN5) { /* Set the CAN5 peripheral clock to 80MHz */ clock_set_source_divider(clock_can5, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can5, 0); freq = clock_get_frequency(clock_can5); } else if (ptr == HPM_MCAN6) { /* Set the CAN6 peripheral clock to 80MHz */ clock_set_source_divider(clock_can6, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can6, 0); freq = clock_get_frequency(clock_can6); } else if (ptr == HPM_MCAN7) { /* Set the CAN7 peripheral clock to 80MHz */ clock_set_source_divider(clock_can7, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_can7, 0); freq = clock_get_frequency(clock_can7); } else { /* Invalid CAN instance */ @@ -571,19 +546,15 @@ uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_osc24m, 1); clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { - clock_set_source_divider(clock_uart1, clk_src_osc24m, 1); clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_osc24m, 1); clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else if (ptr == HPM_UART3) { - clock_set_source_divider(clock_uart3, clk_src_osc24m, 1); clock_add_to_group(clock_uart3, 0); freq = clock_get_frequency(clock_uart3); } else { @@ -652,7 +623,11 @@ static void set_backlight_cc10128007(uint16_t percent) static void set_video_router_cc10128007(void) { pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_lvds); +#if defined(CONFIG_HPM_PANEL_MULTI_ENABLE) && CONFIG_HPM_PANEL_MULTI_ENABLE + pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_sel_lcdc1); +#else pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_sel_lcdc0); +#endif } void board_init_lcd_lvds_cc10128007(void) @@ -664,10 +639,15 @@ void board_init_lcd_lvds_cc10128007(void) init_mipi_lvds_tx_phy1_pin(); hpm_panel_hw_interface_t hw_if = {0}; +#if defined(CONFIG_HPM_PANEL_MULTI_ENABLE) && CONFIG_HPM_PANEL_MULTI_ENABLE + hpm_panel_t *panel = hpm_panel_find_device(BOARD_MULTI_PANEL_LVDS_NAME); + const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); + uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(BOARD_MULTI_PANEL_LVDS_LCDC_CLK, timing->pixel_clock_khz); +#else hpm_panel_t *panel = hpm_panel_find_device_default(); const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); - uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz); +#endif hw_if.set_video_router = set_video_router_cc10128007; hw_if.set_backlight = set_backlight_cc10128007; hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; @@ -708,9 +688,14 @@ void board_init_lcd_mipi_mc10128007_31b(void) init_mipi_lvds_tx_phy0_pin(); hpm_panel_hw_interface_t hw_if = {0}; +#if defined(CONFIG_HPM_PANEL_MULTI_ENABLE) && CONFIG_HPM_PANEL_MULTI_ENABLE + hpm_panel_t *panel = hpm_panel_find_device(BOARD_MULTI_PANEL_MIPI_NAME); +#else hpm_panel_t *panel = hpm_panel_find_device_default(); +#endif const hpm_panel_timing_t *timing = hpm_panel_get_timing(panel); uint32_t lcdc_pixel_clk_khz = board_lcdc_clock_init(clock_lcd0, timing->pixel_clock_khz); + hw_if.set_reset_pin_level = set_reset_pin_level_mc10128007_31b; hw_if.set_video_router = set_video_router_mc10128007_31b; hw_if.lcdc_pixel_clk_khz = lcdc_pixel_clk_khz; @@ -796,6 +781,10 @@ uint32_t board_lcdc_clock_init(clock_name_t clock_name, uint32_t pixel_clk_khz) void board_init_lcd(void) { +#if defined(CONFIG_HPM_PANEL_MULTI_ENABLE) && CONFIG_HPM_PANEL_MULTI_ENABLE + board_init_lcd_lvds_cc10128007(); + board_init_lcd_mipi_mc10128007_31b(); +#else #if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 board_init_lcd_rgb_tm070rdh13(); #endif @@ -811,12 +800,18 @@ void board_init_lcd(void) #if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01 board_init_lcd_lvds_tm103xdgp01(); #endif +#endif } -void board_panel_para_to_lcdc(lcdc_config_t *config) +void board_panel_para_to_lcdc_by_name(char *name, lcdc_config_t *config) { const hpm_panel_timing_t *timing; - hpm_panel_t *panel = hpm_panel_find_device_default(); + hpm_panel_t *panel; + + if (name) + panel = hpm_panel_find_device(name); + else + panel = hpm_panel_find_device_default(); timing = hpm_panel_get_timing(panel); config->resolution_x = timing->hactive; @@ -836,6 +831,11 @@ void board_panel_para_to_lcdc(lcdc_config_t *config) config->control.invert_pixel_data = timing->pixel_data_pol; config->control.invert_pixel_clock = timing->pixel_clk_pol; } + +void board_panel_para_to_lcdc(lcdc_config_t *config) +{ + board_panel_para_to_lcdc_by_name(NULL, config); +} #endif void board_init_gwc(void) @@ -843,6 +843,7 @@ void board_init_gwc(void) clock_add_to_group(clock_gwc0, 0); clock_add_to_group(clock_gwc1, 0); clock_add_to_group(clock_lcd0, 0); + clock_add_to_group(clock_crc0, 0); } void board_init_cap_touch(void) @@ -855,8 +856,8 @@ void board_init_cap_touch(void) gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); board_delay_ms(1); gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_RST_GPIO_INDEX, BOARD_CAP_RST_GPIO_PIN, 1); - board_delay_ms(6); - gpio_write_pin(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, 0); + board_delay_ms(55); + gpio_set_pin_input(BOARD_CAP_RST_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); board_init_i2c(BOARD_CAP_I2C_BASE); } @@ -886,12 +887,14 @@ uint32_t board_init_cam_clock(CAM_Type *ptr) uint32_t freq = 0; if (ptr == HPM_CAM0) { /* Configure camera clock to 24MHz */ - clock_set_source_divider(clock_cam0, clk_src_osc24m, 1U); - freq = clock_get_frequency(clock_cam0); + clock_set_source_divider(clock_camera0, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera0, 0); + freq = clock_get_frequency(clock_camera0); } else if (ptr == HPM_CAM1) { /* Configure camera clock to 24MHz */ - clock_set_source_divider(clock_cam1, clk_src_osc24m, 1U); - freq = clock_get_frequency(clock_cam1); + clock_set_source_divider(clock_camera1, clk_src_osc24m, 1U); + clock_add_to_group(clock_camera1, 0); + freq = clock_get_frequency(clock_camera1); } else { /* Invalid camera instance */ } @@ -912,7 +915,6 @@ void board_write_mipi_csi_cam_rst(uint8_t state) gpio_write_pin(HPM_GPIO0, GPIO_DI_GPIOB, 0, state); } - static void _cpu_wait_ms(uint32_t cpu_freq, uint32_t ms) { uint32_t ticks_per_us = (cpu_freq + 1000000UL - 1UL) / 1000000UL; @@ -923,6 +925,11 @@ static void _cpu_wait_ms(uint32_t cpu_freq, uint32_t ms) void init_ddr2_800(void) { + /* Reduce the leakage by changing the DDR IO to high-z mode */ + HPM_DDRPHY->ACIOCR = 0x30c00813; + HPM_DDRPHY->DXCCR = 0x4418189c; + HPM_DDRPHY->DSGCR = 0xe004641f; + /* Enable On-chip DCDC 1.8V output */ HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1800) | PCFG_DCDCM_MODE_MODE_SET(1); @@ -1050,8 +1057,13 @@ void init_ddr2_800(void) void init_ddr3l_1333(void) { + /* Reduce the leakage by changing the DDR IO to high-z mode */ + HPM_DDRPHY->ACIOCR = 0x30c00813; + HPM_DDRPHY->DXCCR = 0x4418189c; + HPM_DDRPHY->DSGCR = 0xe004641f; + /* Enable On-chip DCDC 1.4V output */ - HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1400) | PCFG_DCDCM_MODE_MODE_SET(5); + HPM_PCFG->DCDCM_MODE = PCFG_DCDCM_MODE_VOLT_SET(1400) | PCFG_DCDCM_MODE_MODE_SET(1); /* Change DDR clock to 333.33MHz, namely: DDR3-1333 */ clock_set_source_divider(clock_axif, clk_src_pll1_clk1, 2); @@ -1069,8 +1081,6 @@ void init_ddr3l_1333(void) /* Clear DFI_INIT_COMPLETE_EN bit */ HPM_DDRCTL->DFIMISC &= ~DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK; - HPM_DDRPHY->DSGCR = 0xf004641f; - *(volatile uint32_t *) (HPM_DDRPHY_BASE + 0x3000UL) |= (1UL << 0); /* Release DDR core reset */ @@ -1162,43 +1172,15 @@ void _init_ext_ram(void) #endif } -void board_init_usb_pins(void) -{ - init_usb_pins(); - usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); - /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ - board_delay_ms(100); -} - -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) +void board_init_usb(USB_Type *ptr) { - (void) usb_index; - (void) level; -} - -void board_sd_power_switch(SDXC_Type *ptr, bool power_on) -{ - if (ptr == HPM_SDXC1) { - init_sdxc_pwr_pin(ptr, true); - uint32_t gpio_index = BOARD_APP_SDCARD_POWER_SWITCH_PIN / 32; - uint32_t pin_index = BOARD_APP_SDCARD_POWER_SWITCH_PIN % 32; - - if (power_on) { - HPM_GPIO0->DO[gpio_index].SET = 1UL << pin_index; - } else { - HPM_GPIO0->DO[gpio_index].CLEAR = 1UL << pin_index; - } - } -} + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); -void board_init_sd_pins(SDXC_Type *ptr) -{ - if (ptr == HPM_SDXC0) { - init_sdxc_cmd_pin(ptr, false, true); - init_sdxc_clk_data_pins(ptr, 8, true); - } else { - init_sdxc_cmd_pin(ptr, false, false); - init_sdxc_clk_data_pins(ptr, 4, false); + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); } } @@ -1206,15 +1188,11 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver { uint32_t actual_freq = 0; do { - if ((ptr != HPM_SDXC0) && (ptr != HPM_SDXC1)) { - break; - } clock_name_t sdxc_clk = (ptr == HPM_SDXC0) ? clock_sdxc0 : clock_sdxc1; clock_add_to_group(sdxc_clk, 0); sdxc_enable_inverse_clock(ptr, false); sdxc_enable_sd_clock(ptr, false); - clock_set_source_divider(sdxc_clk, clk_src_pll1_clk0, 4U); /* Configure the clock below 400KHz for the identification state */ if (freq <= 400000UL) { @@ -1236,10 +1214,11 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver /* Set clock to 100MHz */ sdxc_set_clock_divider(ptr, 2U); } - /* Configure the clock to 133MHz for SDR104/HS200/HS400 */ + /* Configure the clock to 166MHz for SDR104/HS200/HS400 */ else if (freq <= 208000000UL) { - /* 166MHz */ - clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 5U); + /* set the SDXC0 clock to 166MHz (eMMC), set the SDXC1 clock to 133MHz */ + uint32_t div = (sdxc_clk == clock_sdxc0) ? 4 : 5; + clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, div); sdxc_set_clock_divider(ptr, 1U); } /* For other unsupported clock ranges, configure the clock to 24MHz */ @@ -1250,6 +1229,12 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver if (need_inverse) { sdxc_enable_inverse_clock(ptr, true); } + + hpm_stat_t status = clock_wait_source_stable(sdxc_clk); + if (status != status_success) { + break; + } + sdxc_enable_sd_clock(ptr, true); actual_freq = clock_get_frequency(sdxc_clk) / sdxc_get_clock_divider(ptr); } while (false); @@ -1259,67 +1244,56 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver uint32_t board_init_dao_clock(void) { + clock_add_to_group(clock_dao, 0); + + board_config_i2s_clock(DAO_I2S, 48000); + return clock_get_frequency(clock_dao); } uint32_t board_init_pdm_clock(void) { - return clock_get_frequency(clock_pdm); -} + clock_add_to_group(clock_pdm, 0); -uint32_t board_init_i2s_clock(I2S_Type *ptr) -{ - if (ptr == HPM_I2S0) { - return clock_get_frequency(clock_i2s0); - } else if (ptr == HPM_I2S1) { - return clock_get_frequency(clock_i2s1); - } else if (ptr == HPM_I2S2) { - return clock_get_frequency(clock_i2s2); - } else if (ptr == HPM_I2S3) { - return clock_get_frequency(clock_i2s3); - } else { - return 0; - } + board_config_i2s_clock(PDM_I2S, 16000); + + return clock_get_frequency(clock_pdm); } -/* adjust I2S source clock base on sample rate */ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) { + uint32_t freq = 0; + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); if ((sample_rate % 22050) == 0) { clock_set_source_divider(clock_aud0, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ - clock_add_to_group(clock_i2s0, 0); - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); } else { clock_set_source_divider(clock_aud0, clk_src_pll3_clk0, 21); /* default 24576000Hz */ - clock_add_to_group(clock_i2s0, 0); - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); } - return clock_get_frequency(clock_i2s0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud0 */ + freq = clock_get_frequency(clock_i2s0); } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); if ((sample_rate % 22050) == 0) { clock_set_source_divider(clock_aud1, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ - clock_add_to_group(clock_i2s1, 0); - clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); } else { clock_set_source_divider(clock_aud1, clk_src_pll3_clk0, 21); /* default 24576000Hz */ - clock_add_to_group(clock_i2s1, 0); - clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); } - return clock_get_frequency(clock_i2s1); + clock_set_i2s_source(clock_i2s1, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud1 */ + freq = clock_get_frequency(clock_i2s1); } else if (ptr == HPM_I2S3) { + clock_add_to_group(clock_i2s3, 0); if ((sample_rate % 22050) == 0) { clock_set_source_divider(clock_aud3, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ - clock_add_to_group(clock_i2s3, 0); - clock_set_i2s_source(clock_i2s3, clk_i2s_src_aud3); } else { clock_set_source_divider(clock_aud3, clk_src_pll3_clk0, 21); /* default 24576000Hz */ - clock_add_to_group(clock_i2s3, 0); - clock_set_i2s_source(clock_i2s3, clk_i2s_src_aud3); } - return clock_get_frequency(clock_i2s3); + clock_set_i2s_source(clock_i2s3, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud3 */ + freq = clock_get_frequency(clock_i2s3); } - return 0; + + return freq; } hpm_stat_t board_init_enet_pins(ENET_Type *ptr) @@ -1383,10 +1357,17 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +void board_init_enet_pps_capture_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_capture_pins(); +} + hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { /* set clock source */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 800MHz to get a clock at 100MHz for the enet0 ptp function */ clock_set_source_divider(clock_ptp0, clk_src_pll1_clk0, 8); /* 100MHz */ } else { @@ -1400,12 +1381,18 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { (void) ptr; (void) internal; + + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); + } + return status_success; } hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); } @@ -1417,73 +1404,69 @@ void board_init_adc16_pins(void) init_adc_pins(); } -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) { uint32_t freq = 0; - if (ptr == HPM_ADC0) { - if (clk_src_ahb) { + if (ptr == (void *)HPM_ADC0) { + if (clk_src_bus) { /* Configure the ADC clock from AXI (@200MHz by default)*/ - clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + clock_set_adc_source(clock_adc0, clk_adc_src_axi0); } else { /* Configure the ADC clock from pll0_clk1 divided by 4 (@200MHz by default) */ clock_set_adc_source(clock_adc0, clk_adc_src_ana0); clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); } - + clock_add_to_group(clock_adc0, 0); freq = clock_get_frequency(clock_adc0); } return freq; } +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +void board_init_clk_ref_pin(void) +{ + init_clk_ref_pin(); +} uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) { - uint32_t freq = 0; - + uint32_t freq = 0U; if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk0, 10); + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr3); - } - else if (ptr == HPM_GPTMR4) { - clock_add_to_group(clock_gptmr4, 0); - clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr4); - } - else if (ptr == HPM_GPTMR5) { - clock_add_to_group(clock_gptmr5, 0); - clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr5); - } - else if (ptr == HPM_GPTMR6) { - clock_add_to_group(clock_gptmr6, 0); - clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr6); - } - else if (ptr == HPM_GPTMR7) { - clock_add_to_group(clock_gptmr7, 0); - clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk0, 10); + } else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr7); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ } - else { - /* Invalid instance */ - } + return freq; } diff --git a/bsp/hpmicro/hpm6800evk/board/board.h b/bsp/hpmicro/hpm6800evk/board/board.h index 6753711b5f0..822815e51be 100644 --- a/bsp/hpmicro/hpm6800evk/board/board.h +++ b/bsp/hpmicro/hpm6800evk/board/board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -24,29 +24,22 @@ #define BOARD_NAME "hpm6800evk" #define BOARD_UF2_SIGNATURE (0x0A4D5048UL) -/* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX -#define TEST_DMA_CONTROLLER HPM_HDMA -#define TEST_DMA_IRQ IRQn_HDMA - #ifndef BOARD_RUNNING_CORE #define BOARD_RUNNING_CORE HPM_CORE0 #endif /* uart section */ #ifndef BOARD_APP_UART_BASE -#define BOARD_APP_UART_BASE HPM_UART3 -#define BOARD_APP_UART_IRQ IRQn_UART3 +#define BOARD_APP_UART_BASE HPM_UART3 +#define BOARD_APP_UART_IRQ IRQn_UART3 #define BOARD_APP_UART_BAUDRATE (115200UL) #define BOARD_APP_UART_CLK_NAME clock_uart3 #define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART3_RX #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART3_TX #endif +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PE04 + /* uart lin sample section */ #define BOARD_UART_LIN BOARD_APP_UART_BASE #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ @@ -54,16 +47,15 @@ #define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOE #define BOARD_UART_LIN_TX_PIN (15U) /* PE15 should align with used pin in pinmux configuration */ - #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE #define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART #endif #if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART #ifndef BOARD_CONSOLE_UART_BASE -#define BOARD_CONSOLE_UART_BASE HPM_UART0 -#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 -#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 #define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX #define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX #endif @@ -78,6 +70,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -102,13 +96,12 @@ #define BOARD_FLASH_SIZE (16 * SIZE_1MB) /* i2c section */ -#define BOARD_APP_I2C_BASE HPM_I2C1 -#define BOARD_APP_I2C_IRQ IRQn_I2C1 -#define BOARD_APP_I2C_CLK_NAME clock_i2c1 -#define BOARD_APP_I2C_DMA HPM_HDMA -#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX -#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C1 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 +#define BOARD_APP_I2C_BASE HPM_I2C1 +#define BOARD_APP_I2C_IRQ IRQn_I2C1 +#define BOARD_APP_I2C_CLK_NAME clock_i2c1 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C1 /* cam */ #define BOARD_CAM_I2C_BASE HPM_I2C0 @@ -140,13 +133,26 @@ #define BOARD_CAP_I2C_CLK_GPIO_PIN (8) /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S3 -#define BOARD_APP_I2S_DATA_LINE (2U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s3 -#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S3_TX -#define BOARD_APP_I2S_IRQ IRQn_I2S3 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 +#define BOARD_APP_I2S_BASE HPM_I2S3 +#define BOARD_APP_I2S_TX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_RX_DATA_LINE I2S_DATA_LINE_2 +#define BOARD_APP_I2S_CLK_NAME clock_i2s3 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S3_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S3 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll3_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll3clk0 + +#define BOARD_MIC_I2S HPM_I2S0 +#define BOARD_MIC_I2S_CLK_NAME clock_i2s0 +#define BOARD_MIC_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_MIC_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX + +#define BOARD_SPEAKER_I2S HPM_I2S1 +#define BOARD_SPEAKER_I2S_CLK_NAME clock_i2s1 +#define BOARD_SPEAKER_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_SPEAKER_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S1_TX + +/* pdm selection */ #define BOARD_PDM_SINGLE_CHANNEL_MASK (0x02U) #define BOARD_PDM_DUAL_CHANNEL_MASK (0x22U) @@ -155,11 +161,13 @@ #define BOARD_CODEC_I2C_CLK_NAME clock_i2c3 /* dma section */ -#define BOARD_APP_XDMA HPM_XDMA -#define BOARD_APP_HDMA HPM_HDMA -#define BOARD_APP_XDMA_IRQ IRQn_XDMA -#define BOARD_APP_HDMA_IRQ IRQn_HDMA -#define BOARD_APP_DMAMUX HPM_DMAMUX +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR2 @@ -176,6 +184,9 @@ #define BOARD_GPTMR_PWM_SYNC_CHANNEL 1 #define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr2 +/* gpio software filter*/ +#define DEBOUNCE_THRESHOLD_IN_MS 150 + /* pinmux section */ #define USING_GPIO0_FOR_GPIOZ #ifndef USING_GPIO0_FOR_GPIOZ @@ -221,7 +232,7 @@ #define BOARD_APP_ADC16_IRQn IRQn_ADC0 #define BOARD_APP_ADC16_CH_1 (8U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) - +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_axi0) #define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A /* CAN section */ @@ -240,7 +251,7 @@ #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) -#define BOARD_CPU_FREQ (500000000UL) +#define BOARD_CPU_FREQ (600000000UL) /* LED */ #define BOARD_R_GPIO_CTRL HPM_GPIO0 @@ -268,6 +279,7 @@ /* Key */ #define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOF #define BOARD_APP_GPIO_PIN 6 +#define BOARD_BUTTON_PRESSED_VALUE 0 /* ACMP desction */ #define BOARD_ACMP 0 @@ -294,6 +306,15 @@ #define BOARD_LCD_HEIGHT PANEL_SIZE_HEIGHT #endif +#define BOARD_MULTI_PANEL_LVDS_LCDC_BASE HPM_LCDC1 +#define BOARD_MULTI_PANEL_LVDS_LCDC_CLK clock_lcd1 +#define BOARD_MULTI_PANEL_LVDS_NAME "cc10128007" + +#define BOARD_MULTI_PANEL_MIPI_LCDC_BASE HPM_LCDC +#define BOARD_MULTI_PANEL_MIPI_LCDC_CLK clock_lcd0 +#define BOARD_MULTI_PANEL_MIPI_NAME "mc10128007_31b" + + /* pdma section */ #define BOARD_PDMA_BASE HPM_PDMA #ifndef IRQn_PDMA_D0 @@ -307,22 +328,37 @@ #define BOARD_SHOW_BANNER 1 #endif -/* USB */ -#define BOARD_USB HPM_USB0 - /* FreeRTOS Definitions */ #define BOARD_FREERTOS_TIMER HPM_GPTMR2 #define BOARD_FREERTOS_TIMER_CHANNEL 1 #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + /* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR2 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 +#define BOARD_THREADX_TIMER HPM_GPTMR2 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR2 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr2 + /* SDXC section */ #define BOARD_APP_SDCARD_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDCARD_SDXC_IRQ IRQn_SDXC1 #define BOARD_APP_SDCARD_SUPPORT_3V3 (1) #define BOARD_APP_SDCARD_SUPPORT_1V8 (1) #define BOARD_APP_SDCARD_SUPPORT_4BIT (1) @@ -343,21 +379,54 @@ #ifdef BOARD_APP_SDCARD_VOLTAGE_SWITCH_USING_GPIO #define BOARD_APP_SDCARD_VSEL_PIN IOC_PAD_PD12 #endif +#define BOARD_APP_SDCARD_HOST_USING_IRQ (1) #define BOARD_APP_EMMC_SDXC_BASE (HPM_SDXC0) +#define BOARD_APP_EMMC_SDXC_IRQ IRQn_SDXC0 #define BOARD_APP_EMMC_SUPPORT_3V3 (0) #define BOARD_APP_EMMC_SUPPORT_1V8 (1) -#define BOARD_APP_EMMC_SUPPORT_4BIT (1) +#define BOARD_APP_EMMC_SUPPORT_4BIT (0) #define BOARD_APP_EMMC_SUPPORT_8BIT (1) #define BOARD_APP_EMMC_SUPPORT_DS (1) #define BOARD_APP_EMMC_HOST_USING_IRQ (0) + +#define BOARD_APP_SDIO_SDXC_BASE (HPM_SDXC1) +#define BOARD_APP_SDIO_SDXC_IRQ IRQn_SDXC1 +#define BOARD_APP_SDIO_SUPPORT_3V3 (1) +#define BOARD_APP_SDIO_SUPPORT_1V8 (0) +#define BOARD_APP_SDIO_SUPPORT_4BIT (1) +#define BOARD_APP_SDIO_SUPPORT_POWER_SWITCH (1) +#define BOARD_APP_SDIO_SUPPORT_VOLTAGE_SWITCH (0) +#define BOARD_APP_SDIO_SUPPORT_CARD_DETECTION (0) +#define BOARD_APP_SDIO_POWER_SWITCH_USING_GPIO (1) +#define BOARD_APP_SDIO_VOLTAGE_SWITCH_USING_GPIO (0) +#define BOARD_APP_SDIO_POWER_SWITCH_USING_GPIO (1) +#ifdef BOARD_APP_SDIO_POWER_SWITCH_USING_GPIO +#define BOARD_APP_SDIO_POWER_SWITCH_PIN IOC_PAD_PD07 +#endif +#ifdef BOARD_APP_SDIO_VOLTAGE_SWITCH_USING_GPIO +#define BOARD_APP_SDIO_VSEL_PIN IOC_PAD_PD12 +#endif + + +#define BOARD_APP_SDIO_WIFI_OOB_PORT (HPM_GPIO0) +#define BOARD_APP_SDIO_WIFI_OOB_PIN (IOC_PAD_PE16) +#define BOARD_APP_SDIO_WIFI_OOB_IRQ IRQn_GPIO0_E +#define BOARD_APP_SDIO_WIFI_WL_REG_ON_PORT (HPM_GPIO0) +#define BOARD_APP_SDIO_WIFI_WL_REG_ON_PIN (IOC_PAD_PE17) +#define BOARD_APP_SDIO_WIFI_SDXC_PORT HPM_SDXC1 + /* enet section */ #define BOARD_ENET_COUNT (1U) #define BOARD_ENET_PPS HPM_ENET0 #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 +#define BOARD_ENET_AUXI_SNAPSHOT HPM_ENET0 +#define BOARD_ENET_AUXI_SNAPSHOT_IDX enet_ptp_auxi_snapshot_trigger_0 +#define BOARD_ENET_AUXI_SNAPSHOT_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RGMII_PHY_ITF enet_inf_rgmii #define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOD @@ -368,18 +437,6 @@ #define BOARD_ENET_RGMII_PTP_CLOCK clock_ptp0 #define BOARD_ENET_RGMII_PPS0_PINOUT (1) -#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET0_INT_REF_CLK (0U) -#define BOARD_ENET0_PHY_RST_TIME (30) -#if BOARD_ENET0_INF -#define BOARD_ENET0_TX_DLY (0U) -#define BOARD_ENET0_RX_DLY (0U) -#endif -#if __USE_ENET_PTP -#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) -#endif - - /* dram section */ #define DDR_TYPE_DDR2 (0U) #define DDR_TYPE_DDR3L (1U) @@ -396,6 +453,39 @@ #define BOARD_TAMP_ACTIVE_CH 4 #define BOARD_TAMP_LOW_LEVEL_CH 6 +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_I2S_SPI_CS_GPIO_PIN 27 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PE27 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR2 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 0 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr2 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR2 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 1 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr2 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR2 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr2 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR2 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR5 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 3 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr2 + +#define BOARD_APP_CLK_REF_PIN_NAME "J20[7] (PD31)" +#define BOARD_APP_CLK_REF_CLK_NAME clock_ref1 +#define BOARD_APP_CLK_REF_SRC_NAME clk_src_pll4_clk0 +#define BOARD_APP_PLLCTLV2_TEST_PLL pllctlv2_pll4 +#define BOARD_APP_PLLCTLV2_TEST_PLL_CLK pllctlv2_clk0 +#define BOARD_APP_PLLCTLV2_TEST_PLL_NAME clk_pll4clk0 + +/* BGPR */ +#define BOARD_BGPR HPM_BGPR + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ @@ -406,6 +496,7 @@ void board_init(void); void board_init_console(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_can(MCAN_Type *ptr); @@ -428,6 +519,7 @@ uint32_t board_init_spi_clock(SPI_Type *ptr); uint32_t board_init_can_clock(MCAN_Type *ptr); void board_init_enet_pps_pins(ENET_Type *ptr); +void board_init_enet_pps_capture_pins(ENET_Type *ptr); uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); @@ -454,11 +546,11 @@ uint32_t board_init_uart_clock(UART_Type *ptr); void board_lcd_backlight(bool is_on); void board_init_lcd(void); +void board_panel_para_to_lcdc_by_name(char *name, lcdc_config_t *config); void board_panel_para_to_lcdc(lcdc_config_t *config); void board_init_gwc(void); void board_init_cap_touch(void); -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_usb(USB_Type *ptr); void board_init_sd_pins(SDXC_Type *ptr); uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inverse); @@ -467,11 +559,10 @@ bool board_sd_detect_card(SDXC_Type *ptr); uint32_t board_init_dao_clock(void); uint32_t board_init_pdm_clock(void); -uint32_t board_init_i2s_clock(I2S_Type *ptr); uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); void board_init_adc16_pins(void); -uint32_t board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); void board_init_cam_pins(void); void board_write_cam_rst(uint8_t state); @@ -480,9 +571,10 @@ uint32_t board_init_cam_clock(CAM_Type *ptr); void board_init_mipi_csi_cam_pins(void); void board_write_mipi_csi_cam_rst(uint8_t state); -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); -void board_sd_power_switch(SDXC_Type *ptr, bool on_off); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void board_init_clk_ref_pin(void); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); #if defined(__cplusplus) } diff --git a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg index cbc88524f1e..5f21fd27b46 100644 --- a/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg +++ b/bsp/hpmicro/hpm6800evk/board/debug_scripts/openocd/boards/hpm6800evk.cfg @@ -206,13 +206,13 @@ proc init_dram {} { } $_TARGET0 configure -event reset-end { - init_clock + # init_clock # init_ddr3 } $_TARGET0 configure -event reset-init { - init_clock - init_ddr3 + init_clock + # init_ddr3 } $_TARGET0 configure -event gdb-attach { diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld new file mode 100644 index 00000000000..07a7c2e8a45 --- /dev/null +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_airoc_wifi_rtt.ld @@ -0,0 +1,350 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 16M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 64K; +SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 256M; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 256K + DLM (w) : ORIGIN = 0x80000, LENGTH = 256K + AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 448K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01270000, LENGTH = NONCACHEABLE_SIZE + SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE + AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k + APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + /* WHD kernel and HAL layer */ + KEEP(*whd_*.o (.text .text* .rodata .rodata*)) + KEEP(*cyhal_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > DLM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > DLM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > DLM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > DLM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > DLM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + .apb_sram (NOLOAD) : { + KEEP(*(.backup_sram)) + } > APB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + + .sdram (NOLOAD) : { + . = ALIGN(8); + __sdram_start__ = .; + __sdram_end__ = .; + } > SDRAM +} diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld index 733c17d56d9..5757100f7dd 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -86,12 +89,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -116,12 +119,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -155,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -167,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -187,22 +208,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -230,10 +255,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -253,8 +278,10 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > DLM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + } > DLM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -277,9 +304,10 @@ SECTIONS PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM + } > DLM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -290,8 +318,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld similarity index 81% rename from bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld index 5b4b3188800..aa698239890 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; - } > AXI_SRAM + } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -106,16 +109,12 @@ SECTIONS KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; - } > AXI_SRAM + } > ILM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -173,6 +172,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -181,6 +194,20 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -194,29 +221,33 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM + } > DLM /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; - } > AXI_SRAM + } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; - } > AXI_SRAM + } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -244,10 +275,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -267,8 +298,10 @@ SECTIONS PROVIDE (__edata = .); PROVIDE (_edata = .); PROVIDE (edata = .); - } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + } > DLM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -291,9 +324,10 @@ SECTIONS PROVIDE (_stack = .); PROVIDE (_stack_in_dlm = .); PROVIDE( __rt_rvstack = . ); - } > AXI_SRAM + } > DLM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -304,8 +338,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -324,7 +361,6 @@ SECTIONS .sdram (NOLOAD) : { . = ALIGN(8); __sdram_start__ = .; - . += SDRAM_SIZE; __sdram_end__ = .; } > SDRAM } diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld rename to bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld index 0a9399843e8..7879f8390d6 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/flash_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/flash_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -46,23 +46,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -82,16 +85,16 @@ SECTIONS KEEP(*mem.o (.text .text* .rodata .rodata*)) KEEP(*mempool.o (.text .text* .rodata .rodata*)) /* RT-Thread Core End */ - + /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -149,6 +152,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -161,6 +178,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -176,26 +203,31 @@ SECTIONS __bss_end__ = .; } > DLM + /* Note: the .tbss and .tdata section should be adjacent */ .tbss(NOLOAD) : { . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -223,10 +255,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -247,9 +279,12 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > DLM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -260,8 +295,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 83% rename from bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld index 2ffd29d0b27..84a5a559013 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,6 +106,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -126,22 +136,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -169,10 +183,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -195,7 +209,8 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -203,7 +218,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -214,8 +230,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld similarity index 88% rename from bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld rename to bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld index d0d07958ccb..f990ab84eda 100644 --- a/bsp/hpmicro/hpm6800evk/board/linker_scripts/ram_sdram_rtt.ld +++ b/bsp/hpmicro/hpm6800evk/board/linker_scripts/gcc/ram_sdram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -119,7 +119,7 @@ SECTIONS . = ALIGN(8); _end = .; __bss_end__ = .; - } > AXI_SRAM + } > DLM /* Note: .tbss and .tdata should be adjacent */ .tbss(NOLOAD) : { @@ -129,9 +129,10 @@ SECTIONS *(.tcommon*) _end = .; __tbss_end__ = .; - } > AXI_SRAM + } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; @@ -139,9 +140,10 @@ SECTIONS *(.tdata*) . = ALIGN(8); __tdata_end__ = .; - } > AXI_SRAM + } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -169,10 +171,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -195,7 +197,8 @@ SECTIONS PROVIDE (edata = .); } > AXI_SRAM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -203,7 +206,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -214,8 +218,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6800evk/board/pinmux.c b/bsp/hpmicro/hpm6800evk/board/pinmux.c index 203c6756d63..84314edd476 100644 --- a/bsp/hpmicro/hpm6800evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6800evk/board/pinmux.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 hpmicro + * Copyright (c) 2023-2024 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -56,22 +56,6 @@ void init_cap_pins(void) HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; } -void init_i2c_pins_as_gpio(I2C_Type *ptr) -{ - if (ptr == HPM_I2C3) { - HPM_IOC->PAD[IOC_PAD_PD28].FUNC_CTL = IOC_PD28_FUNC_CTL_GPIO_D_28; - HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_GPIO_D_29; - } else if (ptr == HPM_I2C1) { - HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_GPIO_E_12; - HPM_IOC->PAD[IOC_PAD_PE13].FUNC_CTL = IOC_PE13_FUNC_CTL_GPIO_E_13; - } else if (ptr == HPM_I2C0) { - HPM_IOC->PAD[IOC_PAD_PF09].FUNC_CTL = IOC_PF09_FUNC_CTL_GPIO_F_09; - HPM_IOC->PAD[IOC_PAD_PF08].FUNC_CTL = IOC_PF08_FUNC_CTL_GPIO_F_08; - } else { - ; - } -} - void init_i2c_pins(I2C_Type *ptr) { if (ptr == HPM_I2C3) { /* Audio */ @@ -138,10 +122,10 @@ void init_gpio_pins(void) /* configure pad setting: pull enable and pull up, schmitt trigger enable */ /* enable schmitt trigger to eliminate jitter of pin used as button */ HPM_IOC->PAD[IOC_PAD_PF06].FUNC_CTL = IOC_PF06_FUNC_CTL_GPIO_F_06; - HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11); + HPM_IOC->PAD[IOC_PAD_PF06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(3); HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PF07_FUNC_CTL_GPIO_F_07; - HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(11); + HPM_IOC->PAD[IOC_PAD_PF07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_HYS_MASK | IOC_PAD_PAD_CTL_PRS_SET(3); } void init_spi_pins(SPI_Type *ptr) @@ -151,6 +135,12 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO; HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI; HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_SPI3_CS_0; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PE05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE06].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PE07].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -161,6 +151,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_SPI3_MISO; HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_SPI3_MOSI; HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PE05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE06].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PE07].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -177,6 +173,7 @@ void init_gptmr_pins(GPTMR_Type *ptr) HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0; HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0; HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1; + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPTMR2_COMP_2; } } @@ -316,16 +313,16 @@ void init_sdxc_clk_data_pins(SDXC_Type *ptr, uint32_t width, bool is_1v8) } } - - -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - /* USB0_ID */ - HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID; - /* USB0_OC */ - HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC; - /* USB0_PWR */ - HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR; + if (ptr == HPM_USB0) { + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF04].FUNC_CTL = IOC_PF04_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF03].FUNC_CTL = IOC_PF03_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PF00].FUNC_CTL = IOC_PF00_FUNC_CTL_USB0_PWR; + } } void init_can_pins(MCAN_Type *ptr) @@ -520,25 +517,19 @@ void init_enet_pins(ENET_Type *ptr) void init_enet_pps_pins(void) { HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_ETH0_EVTO_0; + HPM_IOC->PAD[IOC_PAD_PE10].FUNC_CTL = IOC_PE10_FUNC_CTL_ETH0_EVTO_1; +} + +void init_enet_pps_capture_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PE17_FUNC_CTL_ETH0_EVTI_0; + HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PE19_FUNC_CTL_ETH0_EVTI_1; } void init_adc_pins(void) { - HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE18].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE19].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* ADC0.INA12 */ HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE27].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE28].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE29].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE30].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; - HPM_IOC->PAD[IOC_PAD_PE31].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; } void init_tamper_pins(void) @@ -547,3 +538,43 @@ void init_tamper_pins(void) HPM_BIOC->PAD[IOC_PAD_PZ05].FUNC_CTL = BIOC_PZ05_FUNC_CTL_TAMP_PZ_05; HPM_BIOC->PAD[IOC_PAD_PZ06].FUNC_CTL = BIOC_PZ06_FUNC_CTL_TAMP_PZ_06; } + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PE04].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04; +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR2) { + if (as_comp) { + switch (channel) { + case 0: + HPM_IOC->PAD[IOC_PAD_PE23].FUNC_CTL = IOC_PE23_FUNC_CTL_GPTMR2_COMP_0; + break; + case 1: + HPM_IOC->PAD[IOC_PAD_PE24].FUNC_CTL = IOC_PE24_FUNC_CTL_GPTMR2_COMP_1; + break; + case 2: + HPM_IOC->PAD[IOC_PAD_PE26].FUNC_CTL = IOC_PE26_FUNC_CTL_GPTMR2_COMP_2; + default: + break; + } + } else { + switch (channel) { + case 0: + HPM_IOC->PAD[IOC_PAD_PE22].FUNC_CTL = IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0; + break; + default: + break; + } + } + } +} + +void init_clk_ref_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_SOC_REF1; +} diff --git a/bsp/hpmicro/hpm6800evk/board/pinmux.h b/bsp/hpmicro/hpm6800evk/board/pinmux.h index e71c1039643..a95cd360a8f 100644 --- a/bsp/hpmicro/hpm6800evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6800evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 hpmicro + * Copyright (c) 2023-2024 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,7 +14,6 @@ extern "C" { void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); void init_cap_pins(void); -void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_gpio_pins(void); void init_spi_pins(SPI_Type *ptr); @@ -26,9 +25,8 @@ void init_qei_trgm_pins(void); void init_butn_pins(void); void init_acmp_pins(void); void init_adc_pins(void); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_can_pins(MCAN_Type *ptr); -void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_led_pins_as_gpio(void); void init_cam_pins(void); void init_cam_mipi_csi_pins(void); @@ -53,8 +51,12 @@ void init_dao_pins(void); void init_pdm_pins(void); void init_enet_pins(ENET_Type *ptr); void init_enet_pps_pins(void); +void init_enet_pps_capture_pins(void); void init_adc_pins(void); void init_tamper_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_clk_ref_pin(void); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6800evk/board/rtt_board.c b/bsp/hpmicro/hpm6800evk/board/rtt_board.c index 1172c561b7c..338e4ad77f6 100644 --- a/bsp/hpmicro/hpm6800evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6800evk/board/rtt_board.c @@ -61,6 +61,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); @@ -99,7 +100,7 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); + board_init_usb(HPM_USB0); } ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) @@ -111,7 +112,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->SOFTWARE_RESET = 1000U; while(1) { @@ -130,3 +131,50 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb) +{ + uint32_t freq = 0; + + if (ptr == HPM_ADC0) { + if (clk_src_ahb) { + /* Configure the ADC clock from AXI (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_axi0); + } else { + /* Configure the ADC clock from pll0_clk1 divided by 4 (@200MHz by default) */ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } + + return freq; +} + +uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + return clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + return clock_get_frequency(clock_i2s1); + } else if (ptr == HPM_I2S2) { + clock_add_to_group(clock_i2s2, 0); + return clock_get_frequency(clock_i2s2); + } else if (ptr == HPM_I2S3) { + clock_add_to_group(clock_i2s3, 0); + return clock_get_frequency(clock_i2s3); + } else { + return 0; + } +} + + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif + + diff --git a/bsp/hpmicro/hpm6800evk/board/rtt_board.h b/bsp/hpmicro/hpm6800evk/board/rtt_board.h index ebba0c10e39..a6a4dd6f881 100644 --- a/bsp/hpmicro/hpm6800evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6800evk/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,9 @@ #include "hpm_soc.h" /* gpio section */ +#define APP_LED0 (0U) +#define APP_LED1 (1U) +#define APP_LED2 (2U) #define APP_LED0_GPIO_CTRL HPM_GPIO0 #define APP_LED0_GPIO_INDEX GPIO_DI_GPIOF #define APP_LED0_GPIO_PIN 1 @@ -28,6 +31,12 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* CAN section */ #define BOARD_CAN_NAME "can3" #define BOARD_CAN_HWFILTER_INDEX (3U) @@ -46,6 +55,17 @@ #define IRQn_PendSV IRQn_DEBUG0 +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + /*************************************************************** * * RT-Thread related definitions diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.h b/bsp/hpmicro/hpm6800evk/rtconfig.h index cf8c7c07f6a..dd951a90dac 100644 --- a/bsp/hpmicro/hpm6800evk/rtconfig.h +++ b/bsp/hpmicro/hpm6800evk/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -76,6 +76,7 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ @@ -108,6 +109,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -142,7 +145,6 @@ #define RT_USING_SERIAL_V2 #define RT_SERIAL_BUF_STRATEGY_OVERWRITE #define RT_SERIAL_USING_DMA -#define RT_USING_SPI #define RT_USING_PIN /* end of Device Drivers */ @@ -305,6 +307,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -384,21 +400,25 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM6800_SERIES /* Hardware Drivers Config */ -#define SOC_HPM6000 +#define SOC_HPM6800 /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_UART0_RX_BUFSIZE 128 #define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 #define BSP_USING_UART3 #define BSP_UART3_RX_BUFSIZE 1024 #define BSP_UART3_TX_BUFSIZE 0 +#define BSP_UART3_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm6800evk/rtconfig.py b/bsp/hpmicro/hpm6800evk/rtconfig.py index 5e40026924c..c3ecd888d68 100644 --- a/bsp/hpmicro/hpm6800evk/rtconfig.py +++ b/bsp/hpmicro/hpm6800evk/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c b/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c index b0bab335d52..c0a88c32092 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/startup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * */ @@ -9,6 +9,7 @@ #include "hpm_l1c_drv.h" #include + void system_init(void); extern int entry(void); @@ -20,6 +21,7 @@ void system_init(void) { disable_global_irq(CSR_MSTATUS_MIE_MASK); disable_irq_from_intc(); + enable_irq_from_intc(); enable_global_irq(CSR_MSTATUS_MIE_MASK); #ifndef CONFIG_NOT_ENABLE_ICACHE @@ -32,6 +34,7 @@ void system_init(void) __attribute__((weak)) void c_startup(void) { +#ifndef __SES_RISCV uint32_t i, size; #ifdef FLASH_XIP extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; @@ -45,6 +48,10 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __bss_start__[], __bss_end__[]; extern uint8_t __tbss_start__[], __tbss_end__[]; extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; extern uint8_t __data_start__[], __data_end__[]; extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; @@ -71,26 +78,27 @@ __attribute__((weak)) void c_startup(void) /* tdata section LMA: etext */ size = __tdata_end__ - __tdata_start__; for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); } /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } /* noncacheable init section LMA: etext + data length + ramfunc length */ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } +#endif } __attribute__((weak)) int main(void) @@ -113,9 +121,10 @@ void reset_handler(void) /* Call platform specific hardware initialization */ system_init(); +#ifndef __SES_RISCV /* Do global constructors */ __libc_init_array(); - +#endif /* Entry function */ @@ -123,6 +132,6 @@ void reset_handler(void) } -__attribute__((weak)) void _init() +__attribute__((weak)) void _init(void) { } diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S index 63433e71ae0..c2000769245 100644 --- a/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6800evk/startup/HPM6880/toolchains/gcc/start.S @@ -77,7 +77,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6e00evk/.config b/bsp/hpmicro/hpm6e00evk/.config index c5fb968704f..1f70dda049b 100644 --- a/bsp/hpmicro/hpm6e00evk/.config +++ b/bsp/hpmicro/hpm6e00evk/.config @@ -104,11 +104,9 @@ # # CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set # end of rt_strnlen options - -# CONFIG_RT_UTEST_TC_USING_KLIBC is not set # end of klibc options -CONFIG_RT_NAME_MAX=8 +CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_NANO is not set # CONFIG_RT_USING_AMP is not set @@ -131,7 +129,7 @@ CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TIMER_ALL_SOFT is not set -# CONFIG_RT_USING_CPU_USAGE_TRACER is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y # # kservice options @@ -139,11 +137,7 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 # CONFIG_RT_USING_TINY_FFS is not set # end of kservice options -CONFIG_RT_USING_DEBUG=y -CONFIG_RT_DEBUGING_ASSERT=y -CONFIG_RT_DEBUGING_COLOR=y -CONFIG_RT_DEBUGING_CONTEXT=y -# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_DEBUG is not set # CONFIG_RT_USING_CI_ACTION is not set # @@ -187,6 +181,9 @@ CONFIG_RT_VER_NUM=0x50201 CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # end of RT-Thread Kernel +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + # # RT-Thread Components # @@ -203,6 +200,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20 CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set CONFIG_FINSH_USING_SYMTAB=y CONFIG_FINSH_CMD_SIZE=80 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y @@ -215,22 +213,7 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # # DFS: device virtual file system # -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_DFS_FD_MAX=16 -CONFIG_RT_USING_DFS_V1=y -# CONFIG_RT_USING_DFS_V2 is not set -CONFIG_DFS_FILESYSTEMS_MAX=4 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_CROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_TMPFS is not set -# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_DFS is not set # end of DFS: device virtual file system # CONFIG_RT_USING_FAL is not set @@ -244,10 +227,11 @@ CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set @@ -394,6 +378,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set # # Wi-Fi @@ -501,6 +486,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QMODBUS is not set # CONFIG_PKG_USING_PNET is not set # CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set # end of IoT - internet of things # @@ -590,6 +576,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # tools packages # # CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set # CONFIG_PKG_USING_EASYFLASH is not set # CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set @@ -635,6 +622,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZDEBUG is not set # CONFIG_PKG_USING_RVBACKTRACE is not set # CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set # end of tools packages # @@ -728,6 +716,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RMP is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set # CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set # end of system packages # @@ -809,6 +798,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_MM32 is not set @@ -851,6 +842,10 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # HC32 DDL Drivers # +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set # end of HC32 DDL Drivers # @@ -864,6 +859,31 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set # end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK # end of HAL & SDK Drivers # @@ -1035,6 +1055,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SEAN_WS2812B is not set # CONFIG_PKG_USING_IC74HC165 is not set # CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set # CONFIG_PKG_USING_SPI_TOOLS is not set # end of peripheral libraries and drivers @@ -1373,6 +1394,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # end of Arduino libraries # end of RT-Thread online packages +CONFIG_SOC_HPM6E00_SERIES=y + # # Hardware Drivers Config # @@ -1382,13 +1405,32 @@ CONFIG_SOC_HPM6E00=y # On-chip Peripheral Drivers # CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 CONFIG_BSP_USING_UART=y CONFIG_BSP_USING_UART0=y # CONFIG_BSP_UART0_RX_USING_DMA is not set # CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 # CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_UART11 is not set +# CONFIG_BSP_USING_UART12 is not set +# CONFIG_BSP_USING_UART13 is not set +# CONFIG_BSP_USING_UART14 is not set +# CONFIG_BSP_USING_UART15 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_TSW is not set # CONFIG_BSP_USING_ETH is not set # CONFIG_BSP_USING_GPTMR is not set # CONFIG_BSP_USING_I2C is not set diff --git a/bsp/hpmicro/hpm6e00evk/.cproject b/bsp/hpmicro/hpm6e00evk/.cproject new file mode 100644 index 00000000000..eafefd8ef55 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/.cproject @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm6e00evk/.project b/bsp/hpmicro/hpm6e00evk/.project new file mode 100644 index 00000000000..0d08d5512da --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/.project @@ -0,0 +1,27 @@ + + + blink_led + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bsp/hpmicro/hpm6e00evk/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm6e00evk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000000..9f1acfcfba2 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/.settings/projcfg.ini b/bsp/hpmicro/hpm6e00evk/.settings/projcfg.ini new file mode 100644 index 00000000000..421ec3853ee --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +# Fri Apr 25 13:53:29 2025 +cfg_version=v3.0 + +board_name= +bsp_version= +bsp_path= +chip_name= +project_base_rtt_bsp=true +is_use_scons_build=true +hardware_adapter= +selected_rtt_version=latest +board_base_nano_proj=false +is_base_example_project=false +example_name= +project_type=rt-thread +os_branch=master +os_version=latest +project_name=blink_led +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk \ No newline at end of file diff --git a/bsp/hpmicro/hpm6e00evk/README.md b/bsp/hpmicro/hpm6e00evk/README.md index d01a32f084f..a00e74ec0b9 100644 --- a/bsp/hpmicro/hpm6e00evk/README.md +++ b/bsp/hpmicro/hpm6e00evk/README.md @@ -30,6 +30,7 @@ Each peripheral supporting condition for this BSP is as follows: | USB | √ | | | QSPI Flash | √ | | | Ethernet | √ | | +| EtherCAT Slave |√ | | | GPIO | √ | | | SPI | √ | | | I2C | √ | | diff --git a/bsp/hpmicro/hpm6e00evk/README_zh.md b/bsp/hpmicro/hpm6e00evk/README_zh.md index 9ac8ba5b463..0af8550fe09 100644 --- a/bsp/hpmicro/hpm6e00evk/README_zh.md +++ b/bsp/hpmicro/hpm6e00evk/README_zh.md @@ -16,7 +16,7 @@ ## 板级资源介绍 -HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联、音频和电机控制等应用。 +HPM6E00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联、音频和电机控制等应用。 开发板外观如下图所示： @@ -33,6 +33,7 @@ HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板， | USB | √ | | | QSPI Flash | √ | | | 以太网 | √ | | +| EtherCAT从站 | √ | | | GPIO | √ | | | SPI | √ | | | I2C | √ | | diff --git a/bsp/hpmicro/hpm6e00evk/SConstruct b/bsp/hpmicro/hpm6e00evk/SConstruct index 93b39143516..ce70828c063 100644 --- a/bsp/hpmicro/hpm6e00evk/SConstruct +++ b/bsp/hpmicro/hpm6e00evk/SConstruct @@ -55,17 +55,6 @@ GDB = rtconfig.GDB # prepare building environment objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) -hpm_library = 'hpm_sdk' -rtconfig.BSP_LIBRARY_TYPE = hpm_library - -# include soc -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript'))) - -# include libraries -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript'))) - -# include components -objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript'))) # includes rtt drivers diff --git a/bsp/hpmicro/hpm6e00evk/board/Kconfig b/bsp/hpmicro/hpm6e00evk/board/Kconfig index 180c7d1a059..795107e16ca 100644 --- a/bsp/hpmicro/hpm6e00evk/board/Kconfig +++ b/bsp/hpmicro/hpm6e00evk/board/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Drivers Config" config SOC_HPM6E00 bool - select SOC_SERIES_HPM6E00 + select SOC_HPM6E00_SERIES select RT_USING_COMPONENTS_INIT select RT_USING_USER_MAIN default y @@ -11,11 +11,27 @@ config BSP_USING_ENET_PHY_RTL8211 bool default n +config BSP_USING_TSW_PHY_RTL8211 + bool + default n + +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + menu "On-chip Peripheral Drivers" config BSP_USING_GPIO bool "Enable GPIO" select RT_USING_PIN if BSP_USING_GPIO default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif menuconfig BSP_USING_UART bool "Enable UART" @@ -44,6 +60,10 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 endif menuconfig BSP_USING_UART1 bool "Enable UART1" @@ -67,6 +87,388 @@ menu "On-chip Peripheral Drivers" range 0 65535 depends on RT_USING_SERIAL_V2 default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART8 + bool "Enable UART8" + default n + if BSP_USING_UART8 + config BSP_UART8_RX_USING_DMA + bool "Enable UART8 RX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + default n + config BSP_UART8_TX_USING_DMA + bool "Enable UART8 TX DMA" + depends on BSP_USING_UART8 && RT_SERIAL_USING_DMA + default n + config BSP_UART8_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART8_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART8_IRQ_PRIORITY + int "UART8 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART9 + bool "Enable UART9" + default n + if BSP_USING_UART9 + config BSP_UART9_RX_USING_DMA + bool "Enable UART9 RX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + default n + config BSP_UART9_TX_USING_DMA + bool "Enable UART9 TX DMA" + depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA + default n + config BSP_UART9_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART9_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART9_IRQ_PRIORITY + int "UART9 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_USING_DMA + bool "Enable UART10 RX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + default n + config BSP_UART10_TX_USING_DMA + bool "Enable UART10 TX DMA" + depends on BSP_USING_UART10 && RT_SERIAL_USING_DMA + default n + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART10_IRQ_PRIORITY + int "UART10 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART11 + bool "Enable UART11" + default n + if BSP_USING_UART11 + config BSP_UART11_RX_USING_DMA + bool "Enable UART11 RX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + default n + config BSP_UART11_TX_USING_DMA + bool "Enable UART11 TX DMA" + depends on BSP_USING_UART11 && RT_SERIAL_USING_DMA + default n + config BSP_UART11_RX_BUFSIZE + int "Set UART11 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART11_TX_BUFSIZE + int "Set UART11 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART11_IRQ_PRIORITY + int "UART11 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART12 + bool "Enable UART12" + default n + if BSP_USING_UART12 + config BSP_UART12_RX_USING_DMA + bool "Enable UART12 RX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + default n + config BSP_UART12_TX_USING_DMA + bool "Enable UART12 TX DMA" + depends on BSP_USING_UART12 && RT_SERIAL_USING_DMA + default n + config BSP_UART12_RX_BUFSIZE + int "Set UART12 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART12_TX_BUFSIZE + int "Set UART12 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART12_IRQ_PRIORITY + int "UART12 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART13 + bool "Enable UART13" + default n + if BSP_USING_UART13 + config BSP_UART13_RX_USING_DMA + bool "Enable UART13 RX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + config BSP_UART13_TX_USING_DMA + bool "Enable UART13 TX DMA" + depends on BSP_USING_UART13 && RT_SERIAL_USING_DMA + default n + config BSP_UART13_RX_BUFSIZE + int "Set UART13 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART13_TX_BUFSIZE + int "Set UART13 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART13_IRQ_PRIORITY + int "UART13 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART14 + bool "Enable UART14" + default n + if BSP_USING_UART14 + config BSP_UART14_RX_USING_DMA + bool "Enable UART14 RX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + config BSP_UART14_TX_USING_DMA + bool "Enable UART14 TX DMA" + depends on BSP_USING_UART14 && RT_SERIAL_USING_DMA + default n + config BSP_UART14_RX_BUFSIZE + int "Set UART14 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART14_TX_BUFSIZE + int "Set UART14 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART14_IRQ_PRIORITY + int "UART14 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART15 + bool "Enable UART15" + default n + if BSP_USING_UART15 + config BSP_UART15_RX_USING_DMA + bool "Enable UART15 RX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + default n + config BSP_UART15_TX_USING_DMA + bool "Enable UART15 TX DMA" + depends on BSP_USING_UART15 && RT_SERIAL_USING_DMA + default n + config BSP_UART15_RX_BUFSIZE + int "Set UART15 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART15_TX_BUFSIZE + int "Set UART15 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART15_IRQ_PRIORITY + int "UART15 Interrupt Priority" + range 1 7 + default 1 endif endif @@ -76,13 +478,227 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_SPI if BSP_USING_SPI if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice + endif + config BSP_USING_SPI4 + bool "Enable SPI4" + default n + if BSP_USING_SPI4 + config BSP_SPI4_USING_DMA + bool "Enable SPI4 DMA" + default n + config BSP_SPI4_IRQ_PRIORITY + int "SPI4 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI4 CS TYPE" + default BSP_SPI4_USING_SOFT_CS + config BSP_SPI4_USING_SOFT_CS + bool "Enable SPI4 software cs" + config BSP_SPI4_USING_HARD_CS + bool "Enable SPI4 hardware cs" + endchoice + choice + prompt "Select SPI4 IO mode" + default BSP_SPI4_USING_SINGLE_IO + config BSP_SPI4_USING_SINGLE_IO + bool "Enable SPI4 single IO mode" + config BSP_SPI4_USING_DUAL_IO + bool "Enable SPI4 dual IO mode" + config BSP_SPI4_USING_QUAD_IO + bool "Enable SPI4 quad IO mode" + endchoice + endif + config BSP_USING_SPI5 + bool "Enable SPI5" + default n + if BSP_USING_SPI5 + config BSP_SPI5_USING_DMA + bool "Enable SPI5 DMA" + default n + config BSP_SPI5_IRQ_PRIORITY + int "SPI5 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI5 CS TYPE" + default BSP_SPI5_USING_SOFT_CS + config BSP_SPI5_USING_SOFT_CS + bool "Enable SPI5 software cs" + config BSP_SPI5_USING_HARD_CS + bool "Enable SPI5 hardware cs" + endchoice + choice + prompt "Select SPI5 IO mode" + default BSP_SPI5_USING_SINGLE_IO + config BSP_SPI5_USING_SINGLE_IO + bool "Enable SPI5 single IO mode" + config BSP_SPI5_USING_DUAL_IO + bool "Enable SPI5 dual IO mode" + config BSP_SPI5_USING_QUAD_IO + bool "Enable SPI5 quad IO mode" + endchoice + endif + config BSP_USING_SPI6 + bool "Enable SPI6" + default n + if BSP_USING_SPI6 + config BSP_SPI6_USING_DMA + bool "Enable SPI6 DMA" + default n + config BSP_SPI6_IRQ_PRIORITY + int "SPI6 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI6 CS TYPE" + default BSP_SPI6_USING_SOFT_CS + config BSP_SPI6_USING_SOFT_CS + bool "Enable SPI6 software cs" + config BSP_SPI6_USING_HARD_CS + bool "Enable SPI6 hardware cs" + endchoice + choice + prompt "Select SPI6 IO mode" + default BSP_SPI6_USING_SINGLE_IO + config BSP_SPI6_USING_SINGLE_IO + bool "Enable SPI6 single IO mode" + config BSP_SPI6_USING_DUAL_IO + bool "Enable SPI6 dual IO mode" + config BSP_SPI6_USING_QUAD_IO + bool "Enable SPI6 quad IO mode" + endchoice + endif config BSP_USING_SPI7 bool "Enable SPI7" - default n + default y if BSP_USING_SPI7 config BSP_SPI7_USING_DMA bool "Enable SPI7 DMA" default n + config BSP_SPI7_IRQ_PRIORITY + int "SPI7 Interrupt Priority" + range 1 7 + default 1 choice prompt "Select SPI7 CS TYPE" default BSP_SPI7_USING_SOFT_CS @@ -91,18 +707,38 @@ menu "On-chip Peripheral Drivers" config BSP_SPI7_USING_HARD_CS bool "Enable SPI7 hardware cs" endchoice + choice + prompt "Select SPI7 IO mode" + default BSP_SPI7_USING_SINGLE_IO + config BSP_SPI7_USING_SINGLE_IO + bool "Enable SPI7 single IO mode" + config BSP_SPI7_USING_DUAL_IO + bool "Enable SPI7 dual IO mode" + config BSP_SPI7_USING_QUAD_IO + bool "Enable SPI7 quad IO mode" + endchoice endif endif menuconfig BSP_USING_RTC bool "Enable RTC" default n + select RT_USING_RTC if BSP_USING_RTC + + menuconfig BSP_USING_TSW + bool "Enable TSW" + default n + + select RT_USING_TSW + select BSP_USING_TSW_PHY_RTL8211 if BSP_USING_TSW menuconfig BSP_USING_ETH bool "Enable Ethernet" default n - select RT_USING_ETH + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + if BSP_USING_ETH choice prompt "ETH" @@ -121,28 +757,77 @@ menu "On-chip Peripheral Drivers" if BSP_USING_GPTMR config BSP_USING_GPTMR0 bool "Enable GPTMR0" + depends on !HPM_USING_VECTOR_PREEMPTED_MODE default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR1 bool "Enable GPTMR1" default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR2 bool "Enable GPTMR2" default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR3 bool "Enable GPTMR3" default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR4 bool "Enable GPTMR4" default n + if BSP_USING_GPTMR4 + config BSP_GPTMR4_IRQ_PRIORITY + int "GPTMR4 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR5 bool "Enable GPTMR5" default n + if BSP_USING_GPTMR5 + config BSP_GPTMR5_IRQ_PRIORITY + int "GPTMR5 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR6 bool "Enable GPTMR6" default n + if BSP_USING_GPTMR6 + config BSP_GPTMR6_IRQ_PRIORITY + int "GPTMR6 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_GPTMR7 bool "Enable GPTMR7" default n + if BSP_USING_GPTMR7 + config BSP_GPTMR7_IRQ_PRIORITY + int "GPTMR7 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_I2C @@ -153,27 +838,99 @@ menu "On-chip Peripheral Drivers" config BSP_USING_I2C0 bool "Enable I2C0" default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C1 bool "Enable I2C1" default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_I2C3 bool "Enable I2C3" default n - endif - if BSP_USING_I2C0 - config BSP_I2C0_USING_DMA - bool "Enable I2C0 DMA" + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C4 + bool "Enable I2C4" default n - endif - if BSP_USING_I2C1 - config BSP_I2C1_USING_DMA - bool "Enable I2C1 DMA" + if BSP_USING_I2C4 + config BSP_I2C4_USING_DMA + bool "Enable I2C4 DMA" + default n + config BSP_I2C4_IRQ_PRIORITY + int "I2C4 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C5 + bool "Enable I2C5" default n - endif - if BSP_USING_I2C3 - config BSP_I2C3_USING_DMA - bool "Enable I2C3 DMA" + if BSP_USING_I2C5 + config BSP_I2C5_USING_DMA + bool "Enable I2C5 DMA" + default n + config BSP_I2C5_IRQ_PRIORITY + int "I2C5 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C6 + bool "Enable I2C6" default n + if BSP_USING_I2C6 + config BSP_I2C6_USING_DMA + bool "Enable I2C6 DMA" + default n + config BSP_I2C6_IRQ_PRIORITY + int "I2C6 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C7 + bool "Enable I2C7" + default n + if BSP_USING_I2C7 + config BSP_I2C7_USING_DMA + bool "Enable I2C7 DMA" + default n + config BSP_I2C7_IRQ_PRIORITY + int "I2C7 Interrupt Priority" + range 1 7 + default 1 + endif endif @@ -211,6 +968,7 @@ menu "On-chip Peripheral Drivers" if BSP_USING_USB config BSP_USING_USB_DEVICE bool "Enable USB Device" + select RT_USING_CACHE default n config BSP_USING_USB_HOST bool "Enable USB Host" @@ -231,10 +989,11 @@ menu "On-chip Peripheral Drivers" bool "Enable EWDG1" default n endif - + menuconfig BSP_USING_PWMV2 bool "Enable PWM" default n + select RT_USING_PWM if BSP_USING_PWMV2 menuconfig BSP_USING_MCAN bool "Enable MCAN" @@ -244,27 +1003,75 @@ menu "On-chip Peripheral Drivers" config BSP_USING_MCAN0 bool "Enable MCAN0" default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN1 bool "Enable MCAN1" default n + if BSP_USING_MCAN1 + config BSP_MCAN1_IRQ_PRIORITY + int "MCAN1 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN2 bool "Enable MCAN2" default n + if BSP_USING_MCAN2 + config BSP_MCAN2_IRQ_PRIORITY + int "MCAN2 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN3 bool "Enable MCAN3" default n + if BSP_USING_MCAN3 + config BSP_MCAN3_IRQ_PRIORITY + int "MCAN3 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN4 bool "Enable MCAN4" default n + if BSP_USING_MCAN4 + config BSP_MCAN4_IRQ_PRIORITY + int "MCAN4 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN5 bool "Enable MCAN5" default n + if BSP_USING_MCAN5 + config BSP_MCAN5_IRQ_PRIORITY + int "MCAN5 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN6 bool "Enable MCAN6" default n + if BSP_USING_MCAN6 + config BSP_MCAN6_IRQ_PRIORITY + int "MCAN6 Interrupt Priority" + range 1 7 + default 1 + endif config BSP_USING_MCAN7 bool "Enable MCAN7" default n + if BSP_USING_MCAN7 + config BSP_MCAN7_IRQ_PRIORITY + int "MCAN7 Interrupt Priority" + range 1 7 + default 1 + endif endif menuconfig BSP_USING_ADC @@ -272,10 +1079,10 @@ menu "On-chip Peripheral Drivers" default n select RT_USING_ADC if BSP_USING_ADC if BSP_USING_ADC - menuconfig BSP_USING_ADC12 - bool "Enable ADC12" + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" default n - if BSP_USING_ADC12 + if BSP_USING_ADC16 config BSP_USING_ADC0 bool "Enable ADC0" default n @@ -285,13 +1092,8 @@ menu "On-chip Peripheral Drivers" config BSP_USING_ADC2 bool "Enable ADC2" default n - endif - menuconfig BSP_USING_ADC16 - bool "Enable ADC16" - default n - if BSP_USING_ADC16 - config BSP_USING_ADC0 - bool "Enable ADC0" + config BSP_USING_ADC3 + bool "Enable ADC3" default n endif endif diff --git a/bsp/hpmicro/hpm6e00evk/board/SConscript b/bsp/hpmicro/hpm6e00evk/board/SConscript index d6bfd64ec29..a00d788005e 100644 --- a/bsp/hpmicro/hpm6e00evk/board/SConscript +++ b/bsp/hpmicro/hpm6e00evk/board/SConscript @@ -12,7 +12,7 @@ src = Split(""" """) CPPPATH = [cwd] -CPPDEFINES=['D45', 'HPM6880'] +CPPDEFINES=['D45', 'HPM6E80'] group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) diff --git a/bsp/hpmicro/hpm6e00evk/board/board.c b/bsp/hpmicro/hpm6e00evk/board/board.c index fc95b92eea9..e786fe8e757 100644 --- a/bsp/hpmicro/hpm6e00evk/board/board.c +++ b/bsp/hpmicro/hpm6e00evk/board/board.c @@ -21,8 +21,8 @@ #include "hpm_femc_drv.h" #include "hpm_pwmv2_drv.h" #include "hpm_esc_drv.h" - -static board_timer_cb timer_cb; +#include "hpm_tsw_drv.h" +#include /** * @brief FLASH configuration option definitions: @@ -78,11 +78,11 @@ static board_timer_cb timer_cb; * 0 - 4MB / 1 - 8MB / 2 - 16MB */ #if defined(FLASH_XIP) && FLASH_XIP -__attribute__((section(".nor_cfg_option"))) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; +__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90001, 0x00000007, 0x0, 0x0 }; #endif #if defined(FLASH_UF2) && FLASH_UF2 -ATTR_PLACE_AT(".uf2_signature") const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; #endif void board_init_console(void) @@ -97,8 +97,6 @@ void board_init_console(void) */ init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); - /* Configure the UART clock to 24MHz */ - clock_set_source_divider(BOARD_CONSOLE_UART_CLK_NAME, clk_src_osc24m, 1U); clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); cfg.type = BOARD_CONSOLE_TYPE; @@ -171,7 +169,7 @@ void board_ungate_mchtmr_at_lp_mode(void) static void board_turnoff_rgb_led(void) { - uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PE_SET(BOARD_LED_OFF_LEVEL); + uint32_t pad_ctl = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(BOARD_LED_OFF_LEVEL); HPM_IOC->PAD[IOC_PAD_PE14].FUNC_CTL = IOC_PE14_FUNC_CTL_GPIO_E_14; HPM_IOC->PAD[IOC_PAD_PE15].FUNC_CTL = IOC_PE15_FUNC_CTL_GPIO_E_15; HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_GPIO_E_04; @@ -197,6 +195,7 @@ void board_init(void) void board_init_core1(void) { + clock_update_core_clock(); board_init_console(); board_init_pmp(); } @@ -212,8 +211,8 @@ uint32_t board_init_femc_clock(void) /* Default FEMC clock is 166MHz */ - /* Configure the FEMC to 133MHz */ - /* clock_set_source_divider(clock_femc, clk_src_pll1_clk0, 6U); */ + /* Configure the FEMC to clk_src_pll1_clk0 / div, the clk_src_pll1_clk0 default frequency is 800MHz. */ + /* clock_set_source_divider(clock_femc, clk_src_pll1_clk0, 6U); */ /* Set FEMC clock to 133MHz */ return clock_get_frequency(clock_femc); } @@ -228,6 +227,9 @@ void board_delay_ms(uint32_t ms) clock_cpu_delay_ms(ms); } +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) void board_timer_isr(void) { if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { @@ -236,8 +238,6 @@ void board_timer_isr(void) } } -SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr); - void board_timer_create(uint32_t ms, board_timer_cb cb) { uint32_t gptmr_freq; @@ -256,6 +256,7 @@ void board_timer_create(uint32_t ms, board_timer_cb cb) gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); } +#endif void board_i2c_bus_clear(I2C_Type *ptr) { @@ -270,49 +271,58 @@ void board_i2c_bus_clear(I2C_Type *ptr) printf("I2C bus is ready\n"); return; } - i2s_gen_reset_signal(ptr, 9); + i2c_gen_reset_signal(ptr, 9); board_delay_ms(100); printf("I2C bus is cleared\n"); } -void board_init_i2c(I2C_Type *ptr) +uint32_t board_init_i2c_clock(I2C_Type *ptr) { - i2c_config_t config; - hpm_stat_t stat; - uint32_t freq; - if (ptr == NULL) { - return; - } - - init_i2c_pins(ptr); - board_i2c_bus_clear(ptr); + uint32_t freq = 0; if (ptr == HPM_I2C0) { clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); } else if (ptr == HPM_I2C1) { clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); } else if (ptr == HPM_I2C2) { clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); } else if (ptr == HPM_I2C3) { clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); } else if (ptr == HPM_I2C4) { clock_add_to_group(clock_i2c4, 0); + freq = clock_get_frequency(clock_i2c4); } else if (ptr == HPM_I2C5) { clock_add_to_group(clock_i2c5, 0); + freq = clock_get_frequency(clock_i2c5); } else if (ptr == HPM_I2C6) { clock_add_to_group(clock_i2c6, 0); + freq = clock_get_frequency(clock_i2c6); } else if (ptr == HPM_I2C7) { clock_add_to_group(clock_i2c7, 0); + freq = clock_get_frequency(clock_i2c7); } else { ; } - /* Configure the I2C clock to 24MHz */ - /* clock_set_source_divider(BOARD_APP_I2C_CLK_NAME, clk_src_osc24m, 1U); */ + return freq; +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + + freq = board_init_i2c_clock(ptr); + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); config.i2c_mode = i2c_mode_normal; config.is_10bit_addressing = false; - freq = clock_get_frequency(BOARD_APP_I2C_CLK_NAME); stat = i2c_init_master(ptr, freq, &config); if (stat != status_success) { printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); @@ -324,30 +334,21 @@ void board_init_i2c(I2C_Type *ptr) uint32_t board_init_spi_clock(SPI_Type *ptr) { if (ptr == HPM_SPI1) { - /* SPI1 clock configure */ clock_add_to_group(clock_spi1, 0); - /* clock_set_source_divider(clock_spi1, clk_src_pll0_clk0, 5U); */ - return clock_get_frequency(clock_spi1); } else if (ptr == HPM_SPI3) { - /* SPI3 clock configure */ clock_add_to_group(clock_spi3, 0); - /* clock_set_source_divider(clock_spi3, clk_src_pll0_clk0, 5U); */ - return clock_get_frequency(clock_spi3); } else if (ptr == HPM_SPI6) { - /* SPI6 clock configure */ clock_add_to_group(clock_spi6, 0); - /* clock_set_source_divider(clock_spi6, clk_src_pll0_clk0, 5U); */ - return clock_get_frequency(clock_spi6); } else if (ptr == HPM_SPI7) { - /* SPI6 clock configure */ - clock_add_to_group(clock_spi7, 0); - /* clock_set_source_divider(clock_spi6, clk_src_pll0_clk0, 5U); */ - - return clock_get_frequency(clock_spi7); + clock_add_to_group(clock_spi7, 0); + return clock_get_frequency(clock_spi7); + } else { + ; } + return 0; } @@ -432,19 +433,11 @@ void board_led_write(uint8_t state) gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); } -static void set_rgb_output_off(PWMV2_Type *ptr, uint8_t counter, uint8_t channel, uint8_t shadow_id, uint8_t cmp_id) -{ - -} void board_init_rgb_pwm_pins(void) { board_turnoff_rgb_led(); - set_rgb_output_off(BOARD_RED_PWM, BOARD_RED_PWM_COUNTER_INDEX, BOARD_RED_PWM_OUT_CH, BOARD_RED_PWM_SHADOW_ID, BOARD_RED_PWM_CMP_ID); - set_rgb_output_off(BOARD_GREEN_PWM, BOARD_GREEN_PWM_COUNTER_INDEX, BOARD_GREEN_PWM_OUT_CH, BOARD_GREEN_PWM_SHADOW_ID, BOARD_GREEN_PWM_CMP_ID); - set_rgb_output_off(BOARD_BLUE_PWM, BOARD_BLUE_PWM_COUNTER_INDEX, BOARD_BLUE_PWM_OUT_CH, BOARD_BLUE_PWM_SHADOW_ID, BOARD_BLUE_PWM_CMP_ID); - init_led_pins_as_pwm(); } @@ -453,13 +446,13 @@ void board_disable_output_rgb_led(uint8_t color) { switch (color) { case BOARD_RGB_RED: - pwmv2_channel_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT_CH); + pwmv2_channel_disable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); break; case BOARD_RGB_GREEN: - pwmv2_channel_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT_CH); + pwmv2_channel_disable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); break; case BOARD_RGB_BLUE: - pwmv2_channel_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT_CH); + pwmv2_channel_disable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); break; default: while (1) { @@ -472,13 +465,13 @@ void board_enable_output_rgb_led(uint8_t color) { switch (color) { case BOARD_RGB_RED: - pwmv2_channel_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT_CH); + pwmv2_channel_enable_output(BOARD_RED_PWM, BOARD_RED_PWM_OUT); break; case BOARD_RGB_GREEN: - pwmv2_channel_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT_CH); + pwmv2_channel_enable_output(BOARD_GREEN_PWM, BOARD_GREEN_PWM_OUT); break; case BOARD_RGB_BLUE: - pwmv2_channel_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT_CH); + pwmv2_channel_enable_output(BOARD_BLUE_PWM, BOARD_BLUE_PWM_OUT); break; default: while (1) { @@ -511,6 +504,7 @@ void board_init_pmp(void) pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); index++; } + pmp_config(&pmp_entry[0], index); } @@ -524,8 +518,7 @@ void board_init_clock(void) /* select clock setting preset1 */ sysctl_clock_set_preset(HPM_SYSCTL, 2); } - /* Add most Clocks to group 0 */ - /* not open uart clock in this API, uart should configure pin function before opening clock */ + /* Add Clocks to group 0 */ clock_add_to_group(clock_cpu0, 0); clock_add_to_group(clock_mchtmr0, 0); clock_add_to_group(clock_ahb0, 0); @@ -541,25 +534,9 @@ void board_init_clock(void) clock_add_to_group(clock_ram1, 0); clock_add_to_group(clock_hdma, 0); clock_add_to_group(clock_xdma, 0); - clock_add_to_group(clock_femc, 0); - - clock_add_to_group(clock_gptmr0, 0); - clock_add_to_group(clock_gptmr1, 0); - clock_add_to_group(clock_gptmr2, 0); - clock_add_to_group(clock_gptmr3, 0); - clock_add_to_group(clock_gptmr4, 0); - clock_add_to_group(clock_gptmr5, 0); - clock_add_to_group(clock_gptmr6, 0); - clock_add_to_group(clock_gptmr7, 0); + clock_add_to_group(clock_gpio, 0); clock_add_to_group(clock_ptpc, 0); - - clock_add_to_group(clock_puart, 0); - clock_add_to_group(clock_watchdog0, 0); - clock_add_to_group(clock_watchdog1, 0); - clock_add_to_group(clock_watchdog2, 0); - clock_add_to_group(clock_watchdog3, 0); - clock_add_to_group(clock_pwdg, 0); - + /* Motor Related */ clock_add_to_group(clock_qei0, 0); clock_add_to_group(clock_qei1, 0); clock_add_to_group(clock_qei2, 0); @@ -574,8 +551,6 @@ void board_init_clock(void) clock_add_to_group(clock_pwm3, 0); clock_add_to_group(clock_rdc0, 0); clock_add_to_group(clock_rdc1, 0); - clock_add_to_group(clock_sdm0, 0); - clock_add_to_group(clock_sdm1, 0); clock_add_to_group(clock_plb0, 0); clock_add_to_group(clock_sei0, 0); clock_add_to_group(clock_mtg0, 0); @@ -585,58 +560,21 @@ void board_init_clock(void) clock_add_to_group(clock_clc0, 0); clock_add_to_group(clock_clc1, 0); clock_add_to_group(clock_emds, 0); - - clock_add_to_group(clock_cmp0, 0); - clock_add_to_group(clock_cmp1, 0); - clock_add_to_group(clock_cmp2, 0); - clock_add_to_group(clock_cmp3, 0); - - clock_add_to_group(clock_crc0, 0); - clock_add_to_group(clock_tsns, 0); - clock_add_to_group(clock_mbx0, 0); - clock_add_to_group(clock_mbx1, 0); - clock_add_to_group(clock_gpio, 0); - clock_add_to_group(clock_ppi0, 0); - clock_add_to_group(clock_lobs, 0); - clock_add_to_group(clock_rng, 0); - clock_add_to_group(clock_sdp, 0); - clock_add_to_group(clock_pka, 0); - clock_add_to_group(clock_kman, 0); - clock_add_to_group(clock_ffa0, 0); - - clock_add_to_group(clock_usb0, 0); - clock_add_to_group(clock_esc0, 0); - clock_add_to_group(clock_eth0, 0); - clock_add_to_group(clock_ptp0, 0); - clock_add_to_group(clock_ntmr0, 0); - clock_add_to_group(clock_ref0, 0); - clock_add_to_group(clock_ref1, 0); - clock_add_to_group(clock_tsn1, 0); - clock_add_to_group(clock_tsn2, 0); - clock_add_to_group(clock_tsn3, 0); - - clock_add_to_group(clock_i2c0, 0); - clock_add_to_group(clock_i2c1, 0); - clock_add_to_group(clock_i2c2, 0); - clock_add_to_group(clock_i2c3, 0); - - clock_add_to_group(clock_adc0, 0); - clock_add_to_group(clock_adc1, 0); - clock_add_to_group(clock_adc2, 0); - clock_add_to_group(clock_adc3, 0); - /* Connect Group0 to CPU0 */ clock_connect_group_to_cpu(0, 0); /* Add the CPU1 clock to Group1 */ - clock_add_to_group(clock_cpu1, 0); + clock_add_to_group(clock_cpu1, 1); clock_add_to_group(clock_mchtmr1, 1); - /* Connect Group1 to CPU1 */ clock_connect_group_to_cpu(1, 1); - /* Bump up DCDC voltage to 1200mv */ - pcfg_dcdc_set_voltage(HPM_PCFG, 1200); + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); + + /* Set CPU clock to 600MHz */ + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); /* Configure mchtmr to 24MHz */ clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); @@ -649,19 +587,15 @@ uint32_t board_init_uart_clock(UART_Type *ptr) { uint32_t freq = 0U; if (ptr == HPM_UART0) { - clock_set_source_divider(clock_uart0, clk_src_pll1_clk0, 10); clock_add_to_group(clock_uart0, 0); freq = clock_get_frequency(clock_uart0); } else if (ptr == HPM_UART1) { - clock_set_source_divider(clock_uart1, clk_src_pll1_clk0, 10); clock_add_to_group(clock_uart1, 0); freq = clock_get_frequency(clock_uart1); } else if (ptr == HPM_UART2) { - clock_set_source_divider(clock_uart2, clk_src_pll1_clk0, 10); clock_add_to_group(clock_uart2, 0); freq = clock_get_frequency(clock_uart2); } else if (ptr == HPM_UART6) { - clock_set_source_divider(clock_uart6, clk_src_pll1_clk0, 10); clock_add_to_group(clock_uart6, 0); freq = clock_get_frequency(clock_uart6); } else { @@ -677,12 +611,11 @@ uint32_t board_init_uart_clock(UART_Type *ptr) void _init_ext_ram(void) { uint32_t femc_clk_in_hz; - board_init_sdram_pins(); - femc_clk_in_hz = board_init_femc_clock(); - femc_config_t config = {0}; femc_sdram_config_t sdram_config = {0}; + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); femc_default_config(HPM_FEMC, &config); femc_init(HPM_FEMC, &config); @@ -692,7 +625,7 @@ void _init_ext_ram(void) sdram_config.prescaler = 0x3; sdram_config.burst_len_in_byte = 8; sdram_config.auto_refresh_count_in_one_burst = 1; - sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; + sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS; sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ @@ -719,18 +652,16 @@ void _init_ext_ram(void) } #endif -void board_init_usb_pins(void) +void board_init_usb(USB_Type *ptr) { - init_usb_pins(); - usb_hcd_set_power_ctrl_polarity(BOARD_USB, true); - /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ - board_delay_ms(100); -} + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level) -{ - (void) usb_index; - (void) level; + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + } } uint32_t board_init_dao_clock(void) @@ -767,7 +698,7 @@ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) } else { clock_set_source_divider(clock_aud0, clk_src_pll2_clk0, 21); /* default 24576000Hz */ } - clock_set_i2s_source(clock_i2s0, clk_i2s_src_aud0); + clock_set_i2s_source(clock_i2s0, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud0 */ freq = clock_get_frequency(clock_i2s0); } else if (ptr == HPM_I2S1) { clock_add_to_group(clock_i2s1, 0); @@ -776,7 +707,7 @@ uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) } else { clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 21); /* default 24576000Hz */ } - clock_set_i2s_source(clock_i2s1, clk_i2s_src_aud1); + clock_set_i2s_source(clock_i2s1, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud1 */ freq = clock_get_frequency(clock_i2s1); } else { ; @@ -790,12 +721,13 @@ void board_init_adc16_pins(void) init_adc16_pins(); } -uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) /* motor system should be use clk_adc_src_ahb0 */ { uint32_t freq = 0; if (ptr == (void *)HPM_ADC0) { - if (clk_src_ahb) { + clock_add_to_group(clock_adc0, 0); + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); } else { @@ -805,7 +737,8 @@ uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system sh } freq = clock_get_frequency(clock_adc0); } else if (ptr == (void *)HPM_ADC1) { - if (clk_src_ahb) { + clock_add_to_group(clock_adc1, 0); + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); } else { @@ -815,7 +748,8 @@ uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system sh } freq = clock_get_frequency(clock_adc1); } else if (ptr == (void *)HPM_ADC2) { - if (clk_src_ahb) { + clock_add_to_group(clock_adc2, 0); + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); } else { @@ -825,7 +759,8 @@ uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system sh } freq = clock_get_frequency(clock_adc2); } else if (ptr == (void *)HPM_ADC3) { - if (clk_src_ahb) { + clock_add_to_group(clock_adc3, 0); + if (clk_src_bus) { /* Configure the ADC clock from AHB (@200MHz by default)*/ clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); } else { @@ -834,11 +769,24 @@ uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system sh clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); } freq = clock_get_frequency(clock_adc3); + } else { + ; } return freq; } +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + void board_init_can(MCAN_Type *ptr) { init_can_pins(ptr); @@ -897,11 +845,9 @@ hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) { /* set clock source */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ /* clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); */ /* 100MHz */ - } else if (ptr == HPM_ENET1) { - /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet1 ptp function */ - /* clock_set_source_divider(clock_ptp1, clk_src_pll1_clk1, 4); */ /* 100MHz */ } else { return status_invalid_argument; } @@ -969,15 +915,22 @@ void board_init_enet_pps_pins(ENET_Type *ptr) init_enet_pps_pins(); } +void board_init_enet_pps_capture_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_capture_pins(); +} + hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) { /* Configure Enet clock to output reference clock */ if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); if (internal) { /* set pll output frequency at 1GHz */ - if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1000000000UL) == status_success) { - /* set pll2_clk1 output frequence at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ - pllctlv2_set_postdiv(HPM_PLLCTLV2, PLLCTLV2_PLL_PLL2, 1, 15); + if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll2, pllctlv2_clk1, pllctlv2_div_4p0); /* set eth clock frequency at 50MHz for enet0 */ /* clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); */ } else { @@ -988,7 +941,7 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) return status_invalid_argument; } - enet_rmii_enable_clock(ptr, internal); /* defined in hpm_enet_soc_drv.h, not sure */ + enet_rmii_enable_clock(ptr, internal); return status_success; } @@ -996,7 +949,8 @@ hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) { if (ptr == HPM_ENET0) { - return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); /* defined in hpm_enet_soc_drv.h, not sure */ + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); } return status_invalid_argument; @@ -1010,6 +964,9 @@ void board_init_dao_pins(void) void board_init_ethercat(ESC_Type *ptr) { (void)ptr; + + clock_add_to_group(clock_esc0, 0); + init_esc_pins(); /* keep ECAT PHY reset */ gpio_set_pin_output_with_initial(BOARD_ECAT_PHY0_RESET_GPIO, BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX, BOARD_ECAT_PHY0_RESET_PIN_INDEX, BOARD_ECAT_PHY_RESET_LEVEL); @@ -1028,29 +985,46 @@ void board_init_switch_led(void) gpio_set_pin_output_with_initial(BOARD_ECAT_OUT2_GPIO, BOARD_ECAT_OUT2_GPIO_PORT_INDEX, BOARD_ECAT_OUT2_GPIO_PIN_INDEX, 0); } -void board_init_tsw(TSW_Type *ptr) +void board_init_tsw_pins(TSW_Type *ptr) { - (void)ptr; + (void) ptr; init_tsw_pins(); - /* PORT1/PORT2: JL1111 RST(PA10) */ - gpio_set_pin_output_with_initial(HPM_GPIO0, GPIO_DO_GPIOA, 10, 0); - gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 10, 0); - board_delay_ms(100); - gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 10, 1); - - /* PORT3: RTL8211 RST(PA10) */ - gpio_set_pin_output_with_initial(HPM_GPIO0, GPIO_DO_GPIOA, 14, 0); - gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 14, 0); - board_delay_ms(100); - gpio_write_pin(HPM_GPIO0, GPIO_DO_GPIOA, 14, 1); + clock_add_to_group(clock_tsn1, 0); + clock_add_to_group(clock_tsn2, 0); + clock_add_to_group(clock_tsn3, 0); + clock_add_to_group(clock_esc0, 0); /* Enable XI clock for JL1111 */ esc_core_enable_clock(HPM_ESC, true); esc_phy_enable_clock(HPM_ESC, true); } +void board_reset_tsw_phy(TSW_Type *ptr, uint8_t port) +{ + (void) ptr; + + if (port == TSW_TSNPORT_PORT1 || port == TSW_TSNPORT_PORT2) { + gpio_set_pin_output_with_initial(BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO, BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_INDEX, BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_PIN, 0); + gpio_write_pin(BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO, BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_INDEX, BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_PIN, 0); + board_delay_ms(100); + gpio_write_pin(BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO, BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_INDEX, BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_PIN, 1); + } + + if (port == TSW_TSNPORT_PORT3) { + gpio_set_pin_output_with_initial(BOARD_TSW_PORT3_PHY_RST_GPIO, BOARD_TSW_PORT3_PHY_RST_GPIO_INDEX, BOARD_TSW_PORT3_PHY_RST_GPIO_PIN, 0); + gpio_write_pin(BOARD_TSW_PORT3_PHY_RST_GPIO, BOARD_TSW_PORT3_PHY_RST_GPIO_INDEX, BOARD_TSW_PORT3_PHY_RST_GPIO_PIN, 0); + board_delay_ms(100); + gpio_write_pin(BOARD_TSW_PORT3_PHY_RST_GPIO, BOARD_TSW_PORT3_PHY_RST_GPIO_INDEX, BOARD_TSW_PORT3_PHY_RST_GPIO_PIN, 1); + } +} + +void board_init_tsw_rgmii_clock_delay(TSW_Type *ptr, uint8_t port) +{ + tsw_set_port_clock_delay(ptr, port, BOARD_TSW_PORT3_RGMII_TX_DLY, BOARD_TSW_PORT3_RGMII_TX_DLY); +} + void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) { init_sei_pins(ptr, sei_ctrl_idx); @@ -1061,72 +1035,44 @@ void board_init_adc_qeiv2_pins(void) init_adc_qeiv2_pins(); } -uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) { - uint32_t freq = 0; + init_gptmr_channel_pin(ptr, channel, as_comp); +} +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; if (ptr == HPM_GPTMR0) { - clock_add_to_group(clock_gptmr0, 0); - clock_set_source_divider(clock_gptmr0, clk_src_pll1_clk0, 8); + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr0); - } - else if (ptr == HPM_GPTMR1) { - clock_add_to_group(clock_gptmr1, 0); - clock_set_source_divider(clock_gptmr1, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr1); - } - else if (ptr == HPM_GPTMR2) { - clock_add_to_group(clock_gptmr2, 0); - clock_set_source_divider(clock_gptmr2, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr2); - } - else if (ptr == HPM_GPTMR3) { - clock_add_to_group(clock_gptmr3, 0); - clock_set_source_divider(clock_gptmr3, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr3); - } - else if (ptr == HPM_GPTMR4) { - clock_add_to_group(clock_gptmr4, 0); - clock_set_source_divider(clock_gptmr4, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR4) { + clock_add_to_group(clock_gptmr4, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr4); - } - else if (ptr == HPM_GPTMR5) { - clock_add_to_group(clock_gptmr5, 0); - clock_set_source_divider(clock_gptmr5, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR5) { + clock_add_to_group(clock_gptmr5, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr5); - } - else if (ptr == HPM_GPTMR6) { - clock_add_to_group(clock_gptmr6, 0); - clock_set_source_divider(clock_gptmr6, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR6) { + clock_add_to_group(clock_gptmr6, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr6); - } - else if (ptr == HPM_GPTMR7) { - clock_add_to_group(clock_gptmr7, 0); - clock_set_source_divider(clock_gptmr7, clk_src_pll1_clk0, 8); + } else if (ptr == HPM_GPTMR7) { + clock_add_to_group(clock_gptmr7, BOARD_RUNNING_CORE & 0x1); freq = clock_get_frequency(clock_gptmr7); - } - else { - /* Invalid instance */ - } -} - -uint32_t board_init_pwm_clock(PWMV2_Type *ptr) -{ - uint32_t freq = 0; - if (ptr == HPM_PWM0) { - clock_add_to_group(clock_pwm0, 0); - freq = clock_get_frequency(clock_pwm0); - } else if (ptr == HPM_PWM1) { - clock_add_to_group(clock_pwm1, 0); - freq = clock_get_frequency(clock_pwm1); - } else if (ptr == HPM_PWM2) { - clock_add_to_group(clock_pwm2, 0); - freq = clock_get_frequency(clock_pwm2); - } else if (ptr == HPM_PWM3) { - clock_add_to_group(clock_pwm3, 0); - freq = clock_get_frequency(clock_pwm3); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); } else { - + /* Not supported */ } return freq; } + diff --git a/bsp/hpmicro/hpm6e00evk/board/board.h b/bsp/hpmicro/hpm6e00evk/board/board.h index 75e9f2e12a1..5f6b9617707 100644 --- a/bsp/hpmicro/hpm6e00evk/board/board.h +++ b/bsp/hpmicro/hpm6e00evk/board/board.h @@ -9,9 +9,11 @@ #define _HPM_BOARD_H #include #include "hpm_common.h" -#include "hpm_clock_drv.h" #include "hpm_soc.h" #include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "hpm_lobs_drv.h" +#include "hpm_trgm_drv.h" #include "pinmux.h" #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #include "hpm_debug_console.h" @@ -29,6 +31,7 @@ /* ACMP desction */ #define BOARD_ACMP HPM_ACMP0 +#define BOARD_ACMP_CLK clock_acmp0 #define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN1 #define BOARD_ACMP_IRQ IRQn_ACMP0_1 #define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ @@ -44,7 +47,15 @@ #define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART1_TX #endif -#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PF27 +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PF27 + +/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */ +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr3 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 /* uart rx idle demo section */ #define BOARD_UART_IDLE BOARD_APP_UART_BASE @@ -68,6 +79,11 @@ #define BOARD_ENET_PPS HPM_ENET0 #define BOARD_ENET_PPS_IDX enet_pps_0 #define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_AUXI_SNAPSHOT HPM_ENET0 +#define BOARD_ENET_AUXI_SNAPSHOT_IDX enet_ptp_auxi_snapshot_trigger_0 +#define BOARD_ENET_AUXI_SNAPSHOT_PTP_CLOCK clock_ptp0 + #define BOARD_ENET_RMII HPM_ENET0 #define BOARD_ENET_RMII_RST_GPIO #define BOARD_ENET_RMII_RST_GPIO_INDEX @@ -77,16 +93,23 @@ #define BOARD_ENET_RMII_PTP_CLOCK (clock_ptp0) #define BOARD_ENET_RMII_PPS0_PINOUT (1) -#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ -#define BOARD_ENET0_INT_REF_CLK (0U) -#define BOARD_ENET0_PHY_RST_TIME (30) -#if BOARD_ENET0_INF -#define BOARD_ENET0_TX_DLY (0U) -#define BOARD_ENET0_RX_DLY (0U) -#endif -#if __USE_ENET_PTP -#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) -#endif +/* tsw section */ +#define BOARD_TSW HPM_TSW +#define BOARD_TSW_PORT TSW_TSNPORT_PORT3 +#define BOARD_TSW_IRQ IRQn_TSW_3 +#define BOARD_TSW_PORT_NUM TSW_TSNPORT_PORT3 + 1 +#define BOARD_TSW_PORT_ITF tsw_port_phy_itf_rgmii + +#define BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO HPM_GPIO0 +#define BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_INDEX GPIO_DO_GPIOA +#define BOARD_TSW_PORT1_PORT2_PHY_RST_GPIO_PIN (10U) + +#define BOARD_TSW_PORT3_PHY_RST_GPIO HPM_GPIO0 +#define BOARD_TSW_PORT3_PHY_RST_GPIO_INDEX GPIO_DO_GPIOA +#define BOARD_TSW_PORT3_PHY_RST_GPIO_PIN (14U) + +#define BOARD_TSW_PORT3_RGMII_TX_DLY (0U) +#define BOARD_TSW_PORT3_RGMII_RX_DLY (0U) /* usb cdc acm uart section */ #define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE @@ -98,8 +121,13 @@ #define BOARD_UART_LIN BOARD_APP_UART_BASE #define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ #define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME -#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOC -#define BOARD_UART_LIN_TX_PIN (23U) /* PC23 should align with used pin in pinmux configuration */ +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOY +#define BOARD_UART_LIN_TX_PIN (7U) /* PY07 is used UART_LIN tx function, align with used pin in pinmux configuration */ +#define BOARD_UART_LIN_PLB_TRGM_IN_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P05 /* align with used pin in pinmux configuration */ + +/* plb lin baudrate detection */ +#define BOARD_PLB_TRGM_FILTER_GPIO_INPUT0 HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN0 +#define BOARD_PLB_TRGM_DMA_REQ0 HPM_TRGM0_DMA_SRC_TRGM0 #if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE #ifndef BOARD_CONSOLE_TYPE @@ -128,6 +156,8 @@ /* rtthread-nano finsh section */ #define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ /* modbus sample section */ #define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE @@ -136,12 +166,13 @@ #define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ /* sdram section */ -#define BOARD_SDRAM_ADDRESS (0x40000000UL) -#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) -#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 -#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS -#define BOARD_SDRAM_REFRESH_COUNT (8192UL) -#define BOARD_SDRAM_REFRESH_IN_MS (64UL) +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) /* nor flash section */ #define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) @@ -155,25 +186,31 @@ #define BOARD_APP_I2C_DMAMUX HPM_DMAMUX #define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C0 -#define BOARD_APP_I2C_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0 -#define BOARD_I2C_GPIO_CTRL HPM_GPIO0 -#define BOARD_I2C_SCL_GPIO_INDEX GPIO_DO_GPIOY -#define BOARD_I2C_SCL_GPIO_PIN 2 -#define BOARD_I2C_SDA_GPIO_INDEX GPIO_DO_GPIOY -#define BOARD_I2C_SDA_GPIO_PIN 3 - /* i2c for i2s codec section */ #define BOARD_CODEC_I2C_BASE HPM_I2C1 #define BOARD_CODEC_I2C_CLK_NAME clock_i2c1 /* i2s section */ -#define BOARD_APP_I2S_BASE HPM_I2S0 -#define BOARD_APP_I2S_DATA_LINE (0U) -#define BOARD_APP_I2S_CLK_NAME clock_i2s0 -#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 -#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 -#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX -#define BOARD_APP_I2S_IRQ IRQn_I2S0 +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_TX_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_APP_I2S_RX_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX +#define BOARD_APP_I2S_IRQ IRQn_I2S0 + +#define BOARD_MIC_I2S HPM_I2S0 +#define BOARD_MIC_I2S_CLK_NAME clock_i2s0 +#define BOARD_MIC_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_MIC_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX + +#define BOARD_SPEAKER_I2S HPM_I2S1 +#define BOARD_SPEAKER_I2S_CLK_NAME clock_i2s1 +#define BOARD_SPEAKER_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_SPEAKER_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S1_TX + +/* pdm selection */ #define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) #define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) @@ -183,21 +220,25 @@ #define BOARD_APP_XDMA_IRQ IRQn_XDMA #define BOARD_APP_HDMA_IRQ IRQn_HDMA #define BOARD_APP_DMAMUX HPM_DMAMUX -#define TEST_DMA_CONTROLLER HPM_HDMA -#define TEST_DMA_IRQ IRQn_HDMA +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA /* APP PWM */ -#define BOARD_APP_PWM HPM_PWM1 -#define BOARD_APP_PWM_CLOCK_NAME clock_pwm1 -#define BOARD_APP_PWM_OUT1 pwm_channel_0 -#define BOARD_APP_PWM_OUT2 pwm_channel_1 -#define BOARD_APP_PWM_OUT3 pwm_channel_2 -#define BOARD_APP_PWM_OUT4 pwm_channel_3 -#define BOARD_APP_PWM_FAULT_PIN (5) -#define BOARD_APP_TRGM HPM_TRGM0 -#define BOARD_APP_PWM_IRQ IRQn_PWM1 -#define BOARD_APP_TRGM_PWM_OUTPUT HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0 -#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 +#define BOARD_APP_PWM HPM_PWM1 +#define BOARD_APP_PWM_CLOCK_NAME clock_pwm1 +#define BOARD_APP_PWM_OUT1 pwm_channel_0 +#define BOARD_APP_PWM_OUT2 pwm_channel_1 +#define BOARD_APP_PWM_OUT3 pwm_channel_2 +#define BOARD_APP_PWM_OUT4 pwm_channel_3 +#define BOARD_APP_PWM_OUT5 pwm_channel_4 +#define BOARD_APP_PWM_OUT6 pwm_channel_5 +#define BOARD_APP_PWM_FAULT_PIN (5) +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM1 +#define BOARD_APP_TRGM_PWM_OUTPUT HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0 +#define BOARD_APP_TRGM_PWM_OUTPUT1 HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1 +#define BOARD_APP_TRGM_PWM_OUTPUT2 HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2 +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 /* gptmr section */ #define BOARD_GPTMR HPM_GPTMR4 @@ -210,15 +251,16 @@ #define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR4_0 #define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr4 #define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR4 -#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR0 -#define BOARD_GPTMR_PWM_SYNC_CHANNEL 0 -#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr0 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR4 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 3 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr4 /* User button */ -#define BOARD_APP_GPIO_CTRL HPM_GPIO0 -#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOB -#define BOARD_APP_GPIO_PIN 24 -#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_B +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOB +#define BOARD_APP_GPIO_PIN 24 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_B +#define BOARD_BUTTON_PRESSED_VALUE 0 #define BOARD_APP_GPIO_CTRL2 HPM_GPIO0 #define BOARD_APP_GPIO_INDEX2 GPIO_DI_GPIOB @@ -255,6 +297,7 @@ #define BOARD_APP_ADC16_IRQn IRQn_ADC0 #define BOARD_APP_ADC16_CH_1 (15U) #define BOARD_APP_ADC16_CLK_NAME (clock_adc0) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) #define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 #define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 @@ -280,9 +323,6 @@ #define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR3 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3) -/* USB section */ -#define BOARD_USB HPM_USB0 - /* LED */ #define BOARD_R_GPIO_CTRL HPM_GPIO0 #define BOARD_R_GPIO_INDEX GPIO_DI_GPIOE @@ -305,37 +345,29 @@ /* RGB LED Section */ #define BOARD_RED_PWM_IRQ IRQn_PWM1 #define BOARD_RED_PWM HPM_PWM1 -#define BOARD_RED_PWM_OUT_CH 6 -#define BOARD_RED_PWM_SHADOW_ID 1 -#define BOARD_RED_PWM_CMP_ID 6 -#define BOARD_RED_PWM_COUNTER_INDEX 2 +#define BOARD_RED_PWM_OUT pwm_channel_6 +#define BOARD_RED_PWM_CMP 12 #define BOARD_RED_PWM_CMP_INITIAL_ZERO true -#define BOARD_RED_PWM_CLOCK_NAME clock_mot1 +#define BOARD_RED_PWM_CLOCK_NAME clock_pwm1 #define BOARD_GREEN_PWM_IRQ IRQn_PWM1 #define BOARD_GREEN_PWM HPM_PWM1 -#define BOARD_GREEN_PWM_OUT_CH 7 -#define BOARD_GREEN_PWM_SHADOW_ID 2 -#define BOARD_GREEN_PWM_CMP_ID 7 -#define BOARD_GREEN_PWM_COUNTER_INDEX 2 +#define BOARD_GREEN_PWM_OUT pwm_channel_7 +#define BOARD_GREEN_PWM_CMP 14 #define BOARD_GREEN_PWM_CMP_INITIAL_ZERO true -#define BOARD_GREEN_PWM_CLOCK_NAME clock_mot1 +#define BOARD_GREEN_PWM_CLOCK_NAME clock_pwm1 #define BOARD_BLUE_PWM_IRQ IRQn_PWM0 #define BOARD_BLUE_PWM HPM_PWM0 -#define BOARD_BLUE_PWM_OUT_CH 4 -#define BOARD_BLUE_PWM_SHADOW_ID 3 -#define BOARD_BLUE_PWM_CMP_ID 4 -#define BOARD_BLUE_PWM_COUNTER_INDEX 1 +#define BOARD_BLUE_PWM_OUT pwm_channel_4 +#define BOARD_BLUE_PWM_CMP 8 #define BOARD_BLUE_PWM_CMP_INITIAL_ZERO true -#define BOARD_BLUE_PWM_CLOCK_NAME clock_mot0 +#define BOARD_BLUE_PWM_CLOCK_NAME clock_pwm0 #define BOARD_RGB_RED 0 #define BOARD_RGB_GREEN (BOARD_RGB_RED + 1) #define BOARD_RGB_BLUE (BOARD_RGB_RED + 2) -/* pdma section */ -#define BOARD_PDMA_BASE HPM_PDMA #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 @@ -349,14 +381,11 @@ #define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOA #define BOARD_ENET_RGMII_RST_GPIO_PIN (14U) -#define BOARD_ENET_RGMII HPM_ENET0 -#define BOARD_ENET_RGMII_TX_DLY (0U) -#define BOARD_ENET_RGMII_RX_DLY (0U) - -#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) - -/* TSW section */ -#define BOARD_TSW HPM_TSW +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (0U) +#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) /* MOTOR */ #define BOARD_MOTOR_CLK_NAME clock_mot0 @@ -381,17 +410,11 @@ #define BOARD_BLDCPWM_CMP_INDEX_7 (7U) #define BOARD_BLDCPWM_CMP_TRIG_CMP (16U) -#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 -#define BOARD_BLDC_TMR_CH 0 -#define BOARD_BLDC_TMR_CMP 0 -#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 -#define BOARD_BLDC_TMR_RELOAD (100000U) - /* BLDC ADC */ #define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 -#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 -#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 -#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC1 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC2 #define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete #define BOARD_BLDC_ADC_CH_U (14U) @@ -401,13 +424,19 @@ #define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) #define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A #define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) -#define BOARD_BLDC_TRG_NUM TRGM_TRGOCFG_ADCX_PTRGI0A #define BOARD_BLDC_PWM_TRIG_OUT_CHN (0U) +#define BOARD_BLDC_DMA_MUX_SRC HPM_DMA_SRC_MOT_0 +#define BOARD_BLDC_DMA_CHN (0U) +#define BOARD_BLDC_DMA_TRG_DST TRGM_TRGOCFG_TRGM_DMA0 +#define BOARD_BLDC_DMA_TRG_SRC HPM_TRGM0_DMA_SRC_TRGM0 +#define BOARD_BLDC_DMA_TRG_INDEX TRGM_DMACFG_0 +#define BOARD_BLDC_DMA_TRG_CMP_INDEX (9U) +#define BOARD_BLDC_DMA_TRG_IN HPM_TRGM0_INPUT_SRC_PWM0_CH9REF /* BLDC TRGM */ -#define BOARD_BLDC_TRIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 -#define BOARD_BLDC_TRIGMUX_OUT_NUM_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A -#define BOARD_BLDC_TRIGMUX_OUT_NUM_VSC HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0 +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 +#define BOARD_BLDC_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_VSC HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0 #define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC0 trgm_adc_matrix_output_to_vsc0_adc0 #define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC1 trgm_adc_matrix_output_to_vsc0_adc1 @@ -433,34 +462,57 @@ #define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC1 trgm_dac_matrix_in_from_qeo0_dac1 #define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC2 trgm_dac_matrix_in_from_qeo0_dac2 +#define BOARD_BLDC_QEO HPM_QEO0 #define BOARD_BLDC_TRGM_POS_MATRIX_TO_VSC trgm_pos_matrix_output_to_vsc0 #define BOARD_BLDC_TRGM_POS_MATRIX_TO_QEO trgm_pos_matrix_output_to_qeo0 #define BOARD_BLDC_TRGM_POS_MATRIX_FROM_QEI trgm_pos_matrix_in_from_qei0 /* BLDC TIMER */ -#define BOARD_BLDC_TMR_BASE HPM_GPTMR2 -#define BOARD_BLDC_TMR_CH 0 -#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 -#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 -#define BOARD_BLDC_TMR_PERIOD_MS (1u) +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_BASE HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_HW_FOC_SPEED_KP (0.01f) +#define BOARD_BLDC_HW_FOC_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_HW_FOC_POSITION_KP (34.7f) +#define BOARD_BLDC_HW_FOC_POSITION_KI (0.113f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.015f) +#define BOARD_BLDC_HFI_PLL_KP (10.0f) +#define BOARD_BLDC_HFI_PLL_KI (1.0f) /* HALL */ /* RDC */ -#define BOARD_RDC_BASE HPM_RDC0 -#define BOARD_RDC_TRGM HPM_TRGM0 -#define BOARD_RDC_TRGIGMUX_IN_NUM HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0 -#define BOARD_RDC_TRG_NUM TRGM_TRGOCFG_MOT_GPIO0 -#define BOARD_RDC_TRG_ADC_NUM HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A -#define BOARD_RDC_ADC_I_BASE HPM_ADC0 -#define BOARD_RDC_ADC_Q_BASE HPM_ADC1 -#define BOARD_RDC_ADC_I_CHN (14U) -#define BOARD_RDC_ADC_Q_CHN (10U) -#define BOARD_RDC_ADC_IRQn IRQn_ADC0 -#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete -#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A -#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_rdc0_adc0 -#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_rdc0_adc1 +#define BOARD_RDC_BASE HPM_RDC0 +#define BOARD_RDC_TRGM HPM_TRGM0 +#define BOARD_RDC_TRG_IN HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0 +#define BOARD_RDC_TRG_OUT TRGM_TRGOCFG_TRGM0_P00 +#define BOARD_RDC_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A +#define BOARD_RDC_ADC_I_BASE HPM_ADC0 +#define BOARD_RDC_ADC_Q_BASE HPM_ADC1 +#define BOARD_RDC_ADC_I_CHN (14U) +#define BOARD_RDC_ADC_Q_CHN (10U) +#define BOARD_RDC_IRQ IRQn_RDC0 +#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete +#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_rdc0_adc0 +#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_rdc0_adc1 #define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_I trgm_adc_matrix_in_from_adc0 #define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_Q trgm_adc_matrix_in_from_adc1 @@ -483,43 +535,57 @@ #define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei3_adc1 #define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc2 #define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc0 +#define BOARD_APP_QEI_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A /* PLB */ +#define BOARD_PLB_CLOCK_NAME clock_plb0 + #define BOARD_PLB_COUNTER HPM_PLB #define BOARD_PLB_PWM_BASE HPM_PWM0 #define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 #define BOARD_PLB_TRGM HPM_TRGM0 #define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0) -#define BOARD_PLB_IN_PWM_TRG_NUM (TRGM_TRGOCFG_PLB_IN_00) -#define BOARD_PLB_IN_PWM_PULSE_TRG_NUM (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_IN_PWM_TRG (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG (TRGM_TRGOCFG_PLB_IN_02) #define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT32) -#define BOARD_PLB_TYPEB_INPUT0 (TRGM_TRGOCFG_PLB_IN_32) -#define BOARD_PLB_OUT_TRG (HPM_TRGM0_INPUT_SRC_PLB_OUT00) -#define BOARD_PLB_IO_TRG_NUM (TRGM_TRGOCFG_MOT_GPIO5) +#define BOARD_PLB_TO_TRG_IN (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_TRG_OUT (HPM_TRGM0_OUTPUT_SRC_TRGM0_P05) #define BOARD_PLB_IO_TRG_SHIFT (5) #define BOARD_PLB_PWM_CMP (8U) #define BOARD_PLB_PWM_CHN (8U) #define BOARD_PLB_CHN plb_chn0 +#define BOARD_PLB_PHASE_COUNT_DEFAULT (4000) +#define BOARD_PLB_FILTER_LENGTH_DEFAULT (100) +#define BOARD_PLB_QEI_A_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P06 +#define BOARD_PLB_QEI_B_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P07 +#define BOARD_PLB_QEI_Z_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P05 + +#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P10 +#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_TRGM0_P12 +#define BOARD_PLB_FILTER_IO_TRG_SHIFT (12) + /* QEO */ #define BOARD_QEO HPM_QEO0 #define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo0 -#define BOARD_QEO_PWM HPM_QEO1 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */ -#define BOARD_QEO_TRGM_POS_PWM trgm_pos_matrix_output_to_qeo1 +#define BOARD_QEO_PWM HPM_QEO1 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */ +#define BOARD_QEO_TRGM_POS_PWM trgm_pos_matrix_output_to_qeo1 +#define BOARD_QEO_PWM_SAFETY_TRGM HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 /* SEI */ -#define BOARD_SEI HPM_SEI -#define BOARD_SEI_CTRL SEI_CTRL_1 -#define BOARD_SEI_IRQn IRQn_SEI_1 +#define BOARD_SEI HPM_SEI +#define BOARD_SEI_CTRL SEI_CTRL_1 +#define BOARD_SEI_IRQn IRQn_SEI0_1 +#define BOARD_SEI_CLOCK_NAME clock_sei0 #define BOARD_TRGM_POS_SOURCE_SEI trgm_pos_matrix_in_from_sei_pos1 /* MTG */ #define BOARD_TRGM_POS_DEST_MTG trgm_pos_matrix_output_to_mtg0 /* VSC */ -#define BOARD_VSC HPM_VSC0 -#define BOARD_VSC_IRQn IRQn_VSC0 +#define BOARD_VSC HPM_VSC0 +#define BOARD_VSC_IRQn IRQn_VSC0 /* CLC */ #define BOARD_CLC HPM_CLC0 @@ -535,6 +601,7 @@ #define BOARD_SDM_CHANNEL 0 #define BOARD_SDM_TRGM HPM_TRGM0 #define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CLK clock_gptmr3 #define BOARD_SDM_TRGM_GPTMR_CH 2 #define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 #define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15 @@ -545,21 +612,26 @@ #define BOARD_SDM_CLK_PWM_CLK_NAME clock_pwm2 #define BOARD_SDM_CLK_PWM_OUT (3) - - /* EtherCAT definitions */ /* ECAT PORT0 must support */ -#define BOARD_ECAT_SUPPORT_PORT1 (1) -#define BOARD_ECAT_SUPPORT_PORT2 (0) +#define BOARD_ECAT_SUPPORT_PORT1 (1) +#define BOARD_ECAT_SUPPORT_PORT2 (0) -#define BOARD_ECAT_PHY0_RESET_GPIO HPM_GPIO0 -#define BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA -#define BOARD_ECAT_PHY0_RESET_PIN_INDEX (10) +#define BOARD_ECAT_SUPPORT_RUN_ERROR_LED (1) /* board supports RUN/ERROR led */ -#define BOARD_ECAT_PHY1_RESET_GPIO HPM_GPIO0 -#define BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA -#define BOARD_ECAT_PHY1_RESET_PIN_INDEX (10) -#define BOARD_ECAT_PHY_RESET_LEVEL (0) +/* invert esc port link signal, require low level for linkup */ +#define BOARD_ECAT_PORT0_LINK_INVERT true /* depend on hardware */ +#define BOARD_ECAT_PORT1_LINK_INVERT true /* depend on hardware */ +#define BOARD_ECAT_PORT2_LINK_INVERT false /* depend on hardware */ + +#define BOARD_ECAT_PHY0_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY0_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA +#define BOARD_ECAT_PHY0_RESET_PIN_INDEX (10) + +#define BOARD_ECAT_PHY1_RESET_GPIO HPM_GPIO0 +#define BOARD_ECAT_PHY1_RESET_GPIO_PORT_INDEX GPIO_DO_GPIOA +#define BOARD_ECAT_PHY1_RESET_PIN_INDEX (10) +#define BOARD_ECAT_PHY_RESET_LEVEL (0) #define BOARD_ECAT_IN1_GPIO HPM_GPIO0 #define BOARD_ECAT_IN1_GPIO_PORT_INDEX GPIO_DO_GPIOC @@ -577,13 +649,25 @@ #define BOARD_ECAT_OUT2_GPIO_PORT_INDEX BOARD_R_GPIO_INDEX #define BOARD_ECAT_OUT2_GPIO_PIN_INDEX BOARD_R_GPIO_PIN -#define BOARD_ECAT_OUT_ON_LEVEL (1) /* ECAT control LED on level */ +#define BOARD_ECAT_OUT_ON_LEVEL (1) /* ECAT control LED on level */ #define BOARD_ECAT_NMII_LINK0_CTRL_INDEX 3 #define BOARD_ECAT_NMII_LINK1_CTRL_INDEX 0 #define BOARD_ECAT_LED_RUN_CTRL_INDEX 1 #define BOARD_ECAT_LED_ERROR_CTRL_INDEX 6 +/* ECAT PHY address definition */ +#define BOARD_ECAT_PHY_ADDR_OFFSET (0U) +#define BOARD_ECAT_PORT0_PHY_ADDR (0U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT0_PHY_ADDR */ +#define BOARD_ECAT_PORT1_PHY_ADDR (1U) /* actual PHY address = BOARD_ECAT_PHY_ADDR_OFFSET + BOARD_ECAT_PORT1_PHY_ADDR */ + +/* I2C is required when ESC use actual eeprom devices, I2C use to init EEPROM content */ +#define BOARD_ECAT_INIT_EEPROM_I2C HPM_I2C1 +#define BOARD_ECAT_INIT_EEPROM_I2C_CLK clock_i2c1 + +/* the address of ecat flash emulate eeprom component in flash */ +#define BOARD_ECAT_FLASH_EMULATE_EEPROM_ADDR (0x200000) /* offset 2M */ + #ifndef BOARD_SHOW_CLOCK #define BOARD_SHOW_CLOCK 1 #endif @@ -597,47 +681,78 @@ #define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR6 #define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr6 +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_pwm0 +#define BOARD_FREERTOS_TICK_SRC_PWM_COUNTER pwm_counter_0 +#define BOARD_FREERTOS_TICK_SRC_PWM_SHADOW PWMV2_SHADOW_INDEX(0) + #define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR #define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 #define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR #define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr -/* Threadx Definitions */ -#define BOARD_THREADX_TIMER HPM_GPTMR6 -#define BOARD_THREADX_TIMER_CHANNEL 1 -#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 -#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 -#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR -#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 -#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR -#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR6 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr6 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR6 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR6 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr6 /* LOBS */ -#define BOARD_LOBS_TRIG_GROUP 5 /* group5 <--> PF */ -#define BOARD_LOBS_TRIG_PIN 26 +#define BOARD_LOBS_TRIG_GROUP lobs_signal_group_PF +#define BOARD_LOBS_TRIG_PIN_0 25 +#define BOARD_LOBS_TRIG_PIN_1 26 /* i2s over spi Section*/ -#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 -#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOE -#define BOARD_I2S_SPI_CS_GPIO_PIN 6 -#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA06 - -#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR5 -#define BOARD_GPTMR_I2S_MCLK_CHANNEL 2 -#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr5 - -#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR4 -#define BOARD_GPTMR_I2S_LRCK_CHANNEL 0 -#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr4 - -#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR0 -#define BOARD_GPTMR_I2S_BLCK_CHANNEL 0 -#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr0 - -#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0 -#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0 -#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1 -#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0 +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOE +#define BOARD_I2S_SPI_CS_GPIO_PIN 6 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA06 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR5 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 2 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr5 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR4 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 0 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr4 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR4 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 3 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr4 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR0 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr0 + +/* PPI */ +#define BOARD_PPI_ASYNC_SRAM_AD_MUX_MODE true +#define BOARD_PPI_ASYNC_SRAM_CS_INDEX 0 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ0_7 ppi_dq_pins_0_7 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ8_15 ppi_dq_pins_8_15 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ16_23 ppi_dq_pins_16_23 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ24_31 ppi_dq_pins_24_31 +#define BOARD_PPI_ASYNC_SRAM_ADV_CTRL_PIN 3 +#define BOARD_PPI_ASYNC_SRAM_WE_CTRL_PIN 4 +#define BOARD_PPI_ASYNC_SRAM_OE_CTRL_PIN 5 +#define BOARD_PPI_ASYNC_SRAM_SIZE (128 * 1024) + +#define BOARD_PPI_ADC_CS_INDEX 0 + +/* BGPR */ + #define BOARD_BGPR HPM_BGPR0 #if defined(__cplusplus) extern "C" { @@ -649,6 +764,7 @@ void board_init(void); void board_init_console(void); void board_init_core1(void); void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); void board_init_i2c(I2C_Type *ptr); void board_init_can(MCAN_Type *ptr); void board_init_sdram_pins(void); @@ -667,16 +783,18 @@ uint32_t board_init_femc_clock(void); uint32_t board_init_uart_clock(UART_Type *ptr); uint32_t board_init_spi_clock(SPI_Type *ptr); uint32_t board_init_can_clock(MCAN_Type *ptr); -uint32_t board_init_adc16_clock(void *ptr, bool clk_src_ahb); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); +void board_init_acmp_clock(ACMP_Type *ptr); void board_init_i2s_pins(I2S_Type *ptr); uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); uint32_t board_init_pdm_clock(void); uint32_t board_init_dao_clock(void); void board_init_dao_pins(void); void board_init_adc16_pins(void); -void board_init_usb_pins(void); -void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level); +void board_init_acmp_pins(void); +void board_init_usb(USB_Type *ptr); void board_init_enet_pps_pins(ENET_Type *ptr); +void board_init_enet_pps_capture_pins(ENET_Type *ptr); uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); hpm_stat_t board_init_enet_pins(ENET_Type *ptr); @@ -685,6 +803,9 @@ hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); +void board_reset_tsw_phy(TSW_Type *ptr, uint8_t port); +void board_init_tsw_pins(TSW_Type *ptr); +void board_init_tsw_rgmii_clock_delay(TSW_Type *ptr, uint8_t port); /* * @brief Initialize PMP and PMA for but not limited to the following purposes: @@ -702,12 +823,17 @@ void board_ungate_mchtmr_at_lp_mode(void); uint8_t board_get_led_gpio_off_level(void); void board_init_ethercat(ESC_Type *ptr); void board_init_switch_led(void); -void board_init_tsw(TSW_Type *ptr); void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); void board_init_adc_qeiv2_pins(void); +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); + +uint8_t board_get_led_pwm_off_level(void); +void board_disable_output_rgb_led(uint8_t color); +void board_enable_output_rgb_led(uint8_t color); +void board_init_rgb_pwm_pins(void); uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); -uint32_t board_init_pwm_clock(PWMV2_Type *ptr); + #if defined(__cplusplus) } #endif /* __cplusplus */ diff --git a/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c index 7be597c903f..6960ab7f675 100644 --- a/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c +++ b/bsp/hpmicro/hpm6e00evk/board/fal_flash_port.c @@ -57,9 +57,9 @@ static rt_base_t s_interrupt_level; ***************************************************************************************************/ static int init(void); -static int read(long offset, rt_uint8_t *buf, rt_size_t size); -static int write(long offset, const rt_uint8_t *buf, rt_size_t size); -static int erase(long offset, rt_size_t size); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); static xpi_nor_config_t s_flashcfg; @@ -99,9 +99,9 @@ FAL_RAMFUNC static int init(void) else { /* update the flash chip information */ - rt_uint32_t sector_size; + uint32_t sector_size; rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); - rt_uint32_t flash_size; + uint32_t flash_size; rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); nor_flash0.blk_size = sector_size; nor_flash0.len = flash_size; @@ -118,12 +118,12 @@ FAL_RAMFUNC static int init(void) * @param size Size of data to be read * @return actual read bytes */ -FAL_RAMFUNC static int read(long offset, rt_uint8_t *buf, rt_size_t size) +FAL_RAMFUNC static int read(long offset, uint8_t *buf, size_t size) { - rt_uint32_t flash_addr = nor_flash0.addr + offset; - rt_uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); - rt_uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); - rt_uint32_t aligned_size = aligned_end - aligned_start; + uint32_t flash_addr = nor_flash0.addr + offset; + uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + uint32_t aligned_size = aligned_end - aligned_start; rt_base_t level = rt_hw_interrupt_disable(); l1c_dc_invalidate(aligned_start, aligned_size); rt_hw_interrupt_enable(level); @@ -140,7 +140,7 @@ FAL_RAMFUNC static int read(long offset, rt_uint8_t *buf, rt_size_t size) * @param size Size of data to be written * @return actual size of written data or error code */ -FAL_RAMFUNC static int write_unaligned_page_data(long offset, const rt_uint32_t *buf, rt_size_t size) +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const uint32_t *buf, size_t size) { hpm_stat_t status; @@ -165,21 +165,21 @@ FAL_RAMFUNC static int write_unaligned_page_data(long offset, const rt_uint32_t * @param size Size of data to be written * @return actual size of written data or error code */ -FAL_RAMFUNC static int write(long offset, const rt_uint8_t *buf, rt_size_t size) +FAL_RAMFUNC static int write(long offset, const uint8_t *buf, size_t size) { - rt_uint32_t *src = NULL; - rt_uint32_t buf_32[64]; - rt_uint32_t write_size; - rt_size_t remaining_size = size; + uint32_t *src = NULL; + uint32_t buf_32[64]; + uint32_t write_size; + size_t remaining_size = size; int ret = (int)size; - rt_uint32_t page_size; + uint32_t page_size; rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); - rt_uint32_t offset_in_page = offset % page_size; + uint32_t offset_in_page = offset % page_size; if (offset_in_page != 0) { - rt_uint32_t write_size_in_page = page_size - offset_in_page; - rt_uint32_t write_page_size = MIN(write_size_in_page, size); + uint32_t write_size_in_page = page_size - offset_in_page; + uint32_t write_page_size = MIN(write_size_in_page, size); (void) rt_memcpy(buf_32, buf, write_page_size); write_size = write_unaligned_page_data(offset, buf_32, write_page_size); if (write_size < 0) @@ -228,17 +228,17 @@ FAL_RAMFUNC static int write(long offset, const rt_uint8_t *buf, rt_size_t size) * @ret RT_EOK Erase operation is successful * @retval -RT_ERROR Erase operation failed */ -FAL_RAMFUNC static int erase(long offset, rt_size_t size) +FAL_RAMFUNC static int erase(long offset, size_t size) { - rt_uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); hpm_stat_t status; int ret = (int)size; - rt_uint32_t block_size; - rt_uint32_t sector_size; + uint32_t block_size; + uint32_t sector_size; (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); - rt_uint32_t erase_unit; + uint32_t erase_unit; while (aligned_size > 0) { FAL_ENTER_CRITICAL(); diff --git a/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h index a288b08db97..a163a52390a 100644 --- a/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h +++ b/bsp/hpmicro/hpm6e00evk/board/hpm_wm8960.h @@ -15,7 +15,7 @@ #include #include #include "rtt_board.h" -#include "drivers/i2c.h" +#include "drivers/dev_i2c.h" #include "hpm_wm8960_regs.h" #define WM8960_I2C_ADDR 0x1A diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld similarity index 79% rename from bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt.ld rename to bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld index 8c732d2ac2a..f2cbfced976 100644 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,23 +43,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -83,12 +86,12 @@ SECTIONS /* HPMicro Driver Wrapper */ KEEP(*drv_*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -113,12 +116,6 @@ SECTIONS * RT-Thread related sections - Start * *********************************************/ - /* section information for utest */ - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - /* section information for finsh shell */ . = ALIGN(4); __fsymtab_start = .; @@ -152,6 +149,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -164,6 +175,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -184,22 +205,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -227,10 +252,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -251,7 +276,9 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); .heap(NOLOAD) : { . = ALIGN(8); @@ -276,7 +303,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -287,8 +315,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt_enet.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld similarity index 81% rename from bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt_enet.ld rename to bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld index 26ed72c84a9..e1068d6059b 100644 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/flash_rtt_enet.ld +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2024 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,23 +43,26 @@ SECTIONS .start __app_load_addr__ : { . = ALIGN(8); KEEP(*(.start)) + . = ALIGN(16); } > XPI0 __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); .vectors : AT(__vector_load_addr__) { - . = ALIGN(8); + . = ALIGN(16); __vector_ram_start__ = .; KEEP(*(.vector_table)) KEEP(*(.isr_vector)) - . = ALIGN(8); + . = ALIGN(16); __vector_ram_end__ = .; } > ILM - .fast : AT(etext + __data_end__ - __tdata_start__) { - . = ALIGN(8); + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); __ramfunc_start__ = .; *(.fast) + *(.fast.*) + . = ALIGN(16); /* RT-Thread Core Start */ KEEP(*context_gcc.o(.text* .rodata*)) @@ -103,16 +106,12 @@ SECTIONS KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) - . = ALIGN(8); + . = ALIGN(16); __ramfunc_end__ = .; } > ILM - .fast_ram (NOLOAD) : { - KEEP(*(.fast_ram)) - } > DLM - - .text (__vector_load_addr__ + __vector_ram_end__ - __vector_ram_start__) : { - . = ALIGN(8); + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); *(.text) *(.text*) *(.rodata) @@ -170,6 +169,20 @@ SECTIONS } > XPI0 + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + .rel : { KEEP(*(.rel*)) } > XPI0 @@ -178,6 +191,20 @@ SECTIONS PROVIDE (_etext = .); PROVIDE (etext = .); + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -198,22 +225,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > AXI_SRAM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > AXI_SRAM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -241,10 +272,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -265,7 +296,10 @@ SECTIONS PROVIDE (_edata = .); PROVIDE (edata = .); } > AXI_SRAM - __fw_size__ = __data_end__ - __tdata_start__ + etext - __app_load_addr__; + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + .heap(NOLOAD) : { . = ALIGN(8); @@ -290,7 +324,8 @@ SECTIONS PROVIDE( __rt_rvstack = . ); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -301,8 +336,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 82% rename from bsp/hpmicro/hpm6e00evk/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld index 79769ad59d5..8bcf794005a 100644 --- a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,5 +1,5 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -103,6 +103,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -123,22 +133,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -166,10 +180,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -192,7 +206,8 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -200,7 +215,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -211,8 +227,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_xip.icf b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt.icf similarity index 77% rename from bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_xip.icf rename to bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt.icf index 7dc4b22072c..d098add1f13 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_xip.icf +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt.icf @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,18 +7,17 @@ define memory with size = 4G; /* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ +define region FLASH = [from 0x80003000 size 16M - 0x3000 ]; /* FLASH */ define region ILM = [from 0x00000000 size 256k]; /* ILM */ define region DLM = [from 0x00200000 size 256k]; /* DLM */ define region AXI_SRAM = [from 0x01200000 size 512k]; define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; define region AHB_SRAM = [from 0xF0200000 size 32k]; /* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors with fixed order { section .vector_table, section .isr_vector, section .isr_vector.* }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; @@ -27,10 +26,10 @@ define block tbss { section .tbss, section .tbss. define block tdata { section .tdata, section .tdata.* }; define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block heap with size = 64K, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; +define block framebuffer with alignment = 8 { section .framebuffer, section .framebuffer.* }; define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; define block rtthread_FSymTab { section FSymTab }; define block rtthread_VSymTab { section VSymTab }; @@ -40,18 +39,17 @@ define block rtthread_RTMSymTab { section RTMSymTab /* Symbols */ define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; +define exported symbol __app_load_addr__ = start of region FLASH; define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; + define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; +define exported symbol __rt_rvstack = end of block stack + 1; define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; @@ -68,27 +66,40 @@ define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; /* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; +do not initialize { section .noncacheable, section .fast_ram }; // Legacy sections, kept for backwards compatibility do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; +initialize by copy with packing=auto { section .noncacheable.init, section .noncacheable.init.*, section .fast_ram.init, section .fast_ram.init.* }; initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; + +initialize by copy { + section .text.rt_*, + section .text.trap*, + section .text.entry, + section .text.context_gcc, + }; +place in ILM { + section .text.rt_*, + section .text.trap*, + section .text.entry, + section .text.context_gcc, + }; + /* Placement */ place in NOR_CFG_OPTION { section .nor_cfg_option }; place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; +place at start of FLASH with fixed order { symbol _start }; place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { +place in FLASH with minimum size order { block tdata_load, // Thread-local-storage load image block ctors, // Constructors block block dtors, // Destructors block @@ -97,6 +108,7 @@ place in XPI0 with minimum size order { block rtthread_VSymTab, block rtthread_rti_fn, block rtthread_RTMSymTab, + block cherryusb_usbh_class_info, readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) readexec // Catch-all for (readonly) executable code (e.g. .text) }; @@ -110,18 +122,16 @@ define access readonly { section .gcc_except_table, section .gcc_except_table.* define access readonly { section .eh_frame, section .eh_frame.* }; define access readonly { section .sdata.DW.* }; -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in ILM { section .fast, section .fast.*, section .text.*nx* }; // "ramfunc" section place in AXI_SRAM { block framebuffer }; place in AXI_SRAM { block tls, // Thread-local-storage block readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory +place in NONCACHEABLE_RAM { section .noncacheable.non_init, section .noncacheable.non_init.*, section .noncacheable.init, section .noncacheable.init.*, section .noncacheable.bss, section .noncacheable.bss.*, section .noncacheable }; +place in AHB_SRAM { section .ahb_sram, section .ahb_sram.*}; // AHB SRAM memory +place in DLM { section .fast_ram.init, section .fast_ram.init.*, section .fast_ram.non_init, section .fast_ram.non_init.*, section .fast_ram.bss, section .fast_ram.bss.*, section .fast_ram }; // Fast access memory place in DLM { block heap }; // Heap reserved block place at end of DLM { block stack }; // Stack reserved block diff --git a/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt_enet.icf b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt_enet.icf new file mode 100644 index 00000000000..e41aca2d4e2 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/flash_rtt_enet.icf @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + + +define memory with size = 4G; + +/* Regions */ +define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; +define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; +define region FLASH = [from 0x80003000 size 16M - 0x3000 ]; /* FLASH */ +define region ILM = [from 0x00000000 size 256k]; /* ILM */ +define region DLM = [from 0x00200000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01200000 size 512k]; +define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; +define region AHB_SRAM = [from 0xF0200000 size 32k]; + +/* Blocks */ +define block vectors with fixed order { section .vector_table, section .isr_vector, section .isr_vector.* }; +define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; +define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; +define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; +define block eh_frame { section .eh_frame, section .eh_frame.* }; +define block tbss { section .tbss, section .tbss.* }; +define block tdata { section .tdata, section .tdata.* }; +define block tls with fixed order { block tbss, block tdata }; +define block tdata_load { copy of block tdata }; +define block heap with size = 32K, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; +define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; +define block framebuffer with alignment = 8 { section .framebuffer, section .framebuffer.* }; +define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; +define block rtthread_FSymTab { section FSymTab }; +define block rtthread_VSymTab { section VSymTab }; +define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; +define block rtthread_RTMSymTab { section RTMSymTab }; + +/* Symbols */ +define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; +define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; +define exported symbol __app_load_addr__ = start of region FLASH; +define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; +define exported symbol __boot_header_length__ = size of block boot_header; + +define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; +define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; + +define exported symbol _stack_safe = end of block stack + 1; +define exported symbol _stack = end of block stack + 1; +define exported symbol __rt_rvstack = end of block stack + 1; +define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; +define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; + +define exported symbol __fsymtab_start = start of block rtthread_FSymTab; +define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; + +define exported symbol __vsymtab_start = start of block rtthread_VSymTab; +define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; + +define exported symbol __rt_init_start = start of block rtthread_rti_fn; +define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; + +define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; +define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; + +/* Initialization */ +do not initialize { section .noncacheable, section .fast_ram }; // Legacy sections, kept for backwards compatibility +do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; +do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility +do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs + +initialize by copy with packing=auto { section .noncacheable.init, section .noncacheable.init.*, section .fast_ram.init, section .fast_ram.init.* }; +initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections +initialize by copy with packing=auto { section .sdata, section .sdata.* }; +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections + +initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one +initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. +initialize by copy { block vectors, block vectors_s }; + +initialize by copy { + section .text.rt_*, + section .text.trap*, + section .text.entry, + section .text.context_gcc, + + section .text.tcpip_*, + section .text.tcp_*, + section .text.ethernet_*, + section .text.lwip_*, + section .text.eth_rx_thread_entry, + section .text.enet0_pbuf_free_custom, + section .text.enet1_pbuf_free_custom, + section .text.free_rx_dma_descriptor, + section .text.isr_enet, + section .text.eth_rx_callback, + section .text.eth_device_ready, + section .text._rt_*, + section .text.enet_*, + section .text.pbuf_*, + section .text.do_memp_malloc_pool, + section .text.do_memp_free_pool, + section .text.sys_*, + section .text.*tcp*, + section .text.*udp*, + section .text.raw*, + section .text.iperf*, + section .text.netconn*, + section .text.net*, + section .text.ip4*, + section .text.recv*, + section .text.sal*, + section .text.send*, + section .text.etharp*, + section .text.phy*, + section .text.ethernetif*, + section .text.mem*, + section .text.memp*, + section .text.event_callback, + }; +place in ILM { + section .text.rt_*, + section .text.trap*, + section .text.entry, + section .text.context_gcc, + + section .text.tcpip_*, + section .text.tcp_*, + section .text.ethernet_*, + section .text.lwip_*, + section .text.eth_rx_thread_entry, + section .text.enet0_pbuf_free_custom, + section .text.enet1_pbuf_free_custom, + section .text.free_rx_dma_descriptor, + section .text.isr_enet, + section .text.eth_rx_callback, + section .text.eth_device_ready, + section .text._rt_*, + section .text.enet_*, + section .text.pbuf_*, + section .text.do_memp_malloc_pool, + section .text.do_memp_free_pool, + section .text.sys_*, + section .text.*tcp*, + section .text.*udp*, + section .text.raw*, + section .text.iperf*, + section .text.netconn*, + section .text.net*, + section .text.ip4*, + section .text.recv*, + section .text.sal*, + section .text.send*, + section .text.etharp*, + section .text.phy*, + section .text.ethernetif*, + section .text.mem*, + section .text.memp*, + section .text.event_callback, + }; + + +/* Placement */ +place in NOR_CFG_OPTION { section .nor_cfg_option }; +place in BOOT_HEADER with fixed order { block boot_header }; +place at start of FLASH with fixed order { symbol _start }; +place at start of ILM with fixed order { block vectors, block vectors_s }; +place in FLASH with minimum size order { + block tdata_load, // Thread-local-storage load image + block ctors, // Constructors block + block dtors, // Destructors block + block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) + block rtthread_FSymTab, + block rtthread_VSymTab, + block rtthread_rti_fn, + block rtthread_RTMSymTab, + block cherryusb_usbh_class_info, + readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) + readexec // Catch-all for (readonly) executable code (e.g. .text) + }; + +// +// The GNU compiler creates these exception-related sections as writeable. +// Override the section header flag and make them readonly so they can be +// placed into flash. +// +define access readonly { section .gcc_except_table, section .gcc_except_table.* }; +define access readonly { section .eh_frame, section .eh_frame.* }; +define access readonly { section .sdata.DW.* }; + +place in ILM { section .fast, section .fast.*, section .text.*nx* }; // "ramfunc" section +place in AXI_SRAM { block framebuffer }; +place in AXI_SRAM { + block tls, // Thread-local-storage block + readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) + zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) + }; +place in NONCACHEABLE_RAM { section .noncacheable.non_init, section .noncacheable.non_init.*, section .noncacheable.init, section .noncacheable.init.*, section .noncacheable.bss, section .noncacheable.bss.*, section .noncacheable }; +place in AHB_SRAM { section .ahb_sram, section .ahb_sram.*}; // AHB SRAM memory +place in DLM { section .fast_ram.init, section .fast_ram.init.*, section .fast_ram.non_init, section .fast_ram.non_init.*, section .fast_ram.bss, section .fast_ram.bss.*, section .fast_ram }; // Fast access memory +place in DLM { block heap }; // Heap reserved block +place at end of DLM { block stack }; // Stack reserved block + +/* Keep */ +keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; +keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/ram_rtt.icf similarity index 77% rename from bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_uf2.icf rename to bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/ram_rtt.icf index 08e6fea3588..bd71a9e7dd8 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_uf2.icf +++ b/bsp/hpmicro/hpm6e00evk/board/linker_scripts/segger/ram_rtt.icf @@ -1,23 +1,20 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; /* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x01240000 size 256k]; -define region AHB_SRAM = [from 0xF0400000 size 32k]; -define region APB_SRAM = [from 0xF4130000 size 16k]; +define region DLM = [from 0x00200000 size 256k]; /* DLM */ +define region AXI_SRAM = [from 0x01200000 size 512k]; +define region NONCACHEABLE_RAM = [from 0x01280000 size 512k]; +define region AHB_SRAM = [from 0xF0200000 size 32k]; /* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; +define block vectors with fixed order { section .vector_table, section .isr_vector, section .isr_vector.* }; define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; @@ -26,10 +23,10 @@ define block tbss { section .tbss, section .tbss. define block tdata { section .tdata, section .tdata.* }; define block tls with fixed order { block tbss, block tdata }; define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; +define block heap with size = 128K, alignment = 8, /* fill =0x00, */ readwrite access { }; define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; +define block framebuffer with alignment = 8 { section .framebuffer, section .framebuffer.* }; define block rtthread_FSymTab { section FSymTab }; define block rtthread_VSymTab { section VSymTab }; define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; @@ -40,6 +37,7 @@ define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RA define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; define exported symbol _stack_safe = end of block stack + 1; define exported symbol _stack = end of block stack + 1; +define exported symbol __rt_rvstack = end of block stack + 1; define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; @@ -56,27 +54,24 @@ define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; /* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; +do not initialize { section .noncacheable, section .fast_ram }; // Legacy sections, kept for backwards compatibility do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; +initialize by copy with packing=auto { section .noncacheable.init, section .noncacheable.init.*, section .fast_ram.init, section .fast_ram.init.* }; initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections +initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; + /* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { +place at start of AXI_SRAM with fixed order { symbol _start, block vectors, block vectors_s }; +place in AXI_SRAM with minimum size order { block tdata_load, // Thread-local-storage load image block ctors, // Constructors block block dtors, // Destructors block @@ -85,6 +80,7 @@ place in XPI0 with minimum size order { block rtthread_VSymTab, block rtthread_rti_fn, block rtthread_RTMSymTab, + block cherryusb_usbh_class_info, readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) readexec // Catch-all for (readonly) executable code (e.g. .text) }; @@ -98,21 +94,18 @@ define access readonly { section .gcc_except_table, section .gcc_except_table.* define access readonly { section .eh_frame, section .eh_frame.* }; define access readonly { section .sdata.DW.* }; -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; +place in AXI_SRAM { section .fast, section .fast.*, section .text.*nx* }; // "ramfunc" section place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { +place in DLM { block tls, // Thread-local-storage block readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block +place in NONCACHEABLE_RAM { section .noncacheable.non_init, section .noncacheable.non_init.*, section .noncacheable.init, section .noncacheable.init.*, section .noncacheable.bss, section .noncacheable.bss.*, section .noncacheable }; +place in AHB_SRAM { section .ahb_sram, section .ahb_sram.*}; // AHB SRAM memory +place in DLM { section .fast_ram.init, section .fast_ram.init.*, section .fast_ram.non_init, section .fast_ram.non_init.*, section .fast_ram.bss, section .fast_ram.bss.*, section .fast_ram }; // Fast access memory +place in AXI_SRAM { block heap }; // Heap reserved block place at end of DLM { block stack }; // Stack reserved block /* Keep */ -keep { section .uf2_signature }; keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/hpm6e00evk/board/pinmux.c b/bsp/hpmicro/hpm6e00evk/board/pinmux.c index 27f72fa1cbe..1de940b4a0e 100644 --- a/bsp/hpmicro/hpm6e00evk/board/pinmux.c +++ b/bsp/hpmicro/hpm6e00evk/board/pinmux.c @@ -37,13 +37,15 @@ void init_uart_pins(UART_Type *ptr) void init_uart_pin_as_gpio(UART_Type *ptr) { - if (ptr == HPM_UART0) { + if (ptr == BOARD_UART_LIN) { /* pull-up */ - HPM_IOC->PAD[IOC_PAD_PA00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PA01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY07].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY06].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); - HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_GPIO_A_00; - HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_GPIO_A_01; + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_GPIO_Y_07; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_GPIO_Y_06; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; } } @@ -72,30 +74,6 @@ void init_i2c_pins(I2C_Type *ptr) } } -void init_i2c_pins_as_gpio(I2C_Type *ptr) -{ - if (ptr == HPM_I2C0) { - HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_GPIO_Y_02; - HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_GPIO_Y_03; - HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_PGPIO_Y_02; - HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_PGPIO_Y_03; - } else if (ptr == HPM_I2C1) { -#if 1 - /* WM8960 audio_codec */ - HPM_IOC->PAD[IOC_PAD_PF12].FUNC_CTL = IOC_PF12_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PF13].FUNC_CTL = IOC_PF13_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; -#else - /* raspberry-Pi_IF */ - HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; - HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_GPIO_Y_06; - HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_GPIO_Y_07; -#endif - } else { - ; - } -} - void init_femc_pins(void) { HPM_IOC->PAD[IOC_PAD_PD02].FUNC_CTL = IOC_PD02_FUNC_CTL_FEMC_A_00; @@ -161,13 +139,13 @@ void init_femc_pins(void) HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_FEMC_CLK_0; HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_FEMC_WE; HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_FEMC_CS_0; - HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_CS_1; + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_FEMC_CS_1; /* SRAM: CS0 */ /* SRAM */ HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_FEMC_SCLK_0; HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PD07_FUNC_CTL_FEMC_SCLK_1; - HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_SCS_0; - HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_SCS_1; + HPM_IOC->PAD[IOC_PAD_PC30].FUNC_CTL = IOC_PC30_FUNC_CTL_FEMC_SCS_0; /* SRAM: CS1 */ + HPM_IOC->PAD[IOC_PAD_PC31].FUNC_CTL = IOC_PC31_FUNC_CTL_FEMC_SCS_1; /* SRAM: CS2 */ HPM_IOC->PAD[IOC_PAD_PC22].FUNC_CTL = IOC_PC22_FUNC_CTL_FEMC_SRDY; } @@ -290,6 +268,12 @@ void init_spi_pins(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PF26_FUNC_CTL_SPI7_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PF28_FUNC_CTL_SPI7_MISO; HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PF29_FUNC_CTL_SPI7_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PF27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PF26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PF28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PF29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } else { ; } @@ -302,6 +286,12 @@ void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) HPM_IOC->PAD[IOC_PAD_PF26].FUNC_CTL = IOC_PF26_FUNC_CTL_SPI7_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1); HPM_IOC->PAD[IOC_PAD_PF28].FUNC_CTL = IOC_PF28_FUNC_CTL_SPI7_MISO; HPM_IOC->PAD[IOC_PAD_PF29].FUNC_CTL = IOC_PF29_FUNC_CTL_SPI7_MOSI; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PF27].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PF26].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PF28].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PF29].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); } } @@ -310,9 +300,7 @@ void init_gptmr_pins(GPTMR_Type *ptr) if (ptr == HPM_GPTMR4) { HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0; HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR4_COMP_0; - } - if (ptr == HPM_GPTMR0) { - HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_GPTMR0_COMP_0; + HPM_IOC->PAD[IOC_PAD_PF15].FUNC_CTL = IOC_PF15_FUNC_CTL_GPTMR4_COMP_3; } if (ptr == HPM_GPTMR5) { HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_GPTMR5_COMP_2; @@ -368,14 +356,16 @@ void init_pwm_pins(PWMV2_Type *ptr) } } -void init_usb_pins(void) +void init_usb_pins(USB_Type *ptr) { - /* USB0_ID */ - HPM_IOC->PAD[IOC_PAD_PF22].FUNC_CTL = IOC_PF22_FUNC_CTL_USB0_ID; - /* USB0_OC */ - HPM_IOC->PAD[IOC_PAD_PF23].FUNC_CTL = IOC_PF23_FUNC_CTL_USB0_OC; - /* USB0_PWR */ - HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PF19_FUNC_CTL_USB0_PWR; + if (ptr == HPM_USB0) { + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PF22].FUNC_CTL = IOC_PF22_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PF23].FUNC_CTL = IOC_PF23_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PF19].FUNC_CTL = IOC_PF19_FUNC_CTL_USB0_PWR; + } } void init_clk_obs_pins(void) @@ -494,13 +484,18 @@ void init_enet_pins(ENET_Type *ptr) void init_enet_pps_pins(void) { + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_ETH0_EVTO_0; + HPM_IOC->PAD[IOC_PAD_PF20].FUNC_CTL = IOC_PF20_FUNC_CTL_ETH0_EVTO_1; +} +void init_enet_pps_capture_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE07].FUNC_CTL = IOC_PE07_FUNC_CTL_ETH0_EVTI_0; } void init_adc16_pins(void) { HPM_IOC->PAD[IOC_PAD_PF07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.IN15 */ - HPM_IOC->PAD[IOC_PAD_PF02].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC0.IN15 */ } void init_adc_bldc_pins(void) @@ -553,19 +548,52 @@ void init_led_pins_as_pwm(void) HPM_IOC->PAD[IOC_PAD_PE04].FUNC_CTL = IOC_PE04_FUNC_CTL_PWM0_P_4; } -void init_plb_pins(void) +void init_plb_pulse_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05; +} + +void init_plb_ab_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_TRGM_P_07; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_TRGM_P_06; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05; +} + +void init_plb_lin_pins(void) { HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_TRGM_P_05; } +void init_plb_filter_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PE10].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PE10].FUNC_CTL = IOC_PE10_FUNC_CTL_TRGM_P_10; + HPM_IOC->PAD[IOC_PAD_PE12].FUNC_CTL = IOC_PE12_FUNC_CTL_TRGM_P_12; +} + +/* Pin configuration is required when ESC use actual eeprom devices */ +void init_esc_eeprom_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_ESC0_SDA; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_ESC0_SCL; +} + +/* Pin configuration is required when ESC use actual eeprom devices, use i2c peripheral init eeprom content */ +void init_esc_eeprom_as_i2c_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_I2C1_SDA | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PA13].PAD_CTL = IOC_PAD_PAD_CTL_OD_SET(1) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); +} + void init_esc_pins(void) { /* ESC */ HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_ESC0_REFCK; HPM_IOC->PAD[IOC_PAD_PA30].FUNC_CTL = IOC_PA30_FUNC_CTL_ESC0_MDIO; HPM_IOC->PAD[IOC_PAD_PA31].FUNC_CTL = IOC_PA31_FUNC_CTL_ESC0_MDC; - HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_ESC0_SDA; - HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_ESC0_SCL; /* ESC needs to configure these pins for specific functions, see ESC IOCFG registers */ HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_GPIO_A_10; /* GPIO to reset PHY */ @@ -603,6 +631,8 @@ void init_esc_pins(void) HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_ESC0_P1_RXD_1; HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_ESC0_P1_RXD_2; HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_ESC0_P1_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PE06].FUNC_CTL = IOC_PE06_FUNC_CTL_ESC0_EVTO_0; /* ESC SYNC0 signal */ } void init_tsw_pins(void) @@ -674,6 +704,9 @@ void init_tsw_pins(void) /* PORT3 PHY RST */ HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_GPIO_A_14; + + /* PPS */ + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_TSW0_EVTO_0; } void init_tamper_pins(void) @@ -696,4 +729,24 @@ void init_uart_break_signal_pin(void) { HPM_IOC->PAD[IOC_PAD_PF27].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); HPM_IOC->PAD[IOC_PAD_PF27].FUNC_CTL = IOC_PF27_FUNC_CTL_GPIO_F_27; -} \ No newline at end of file +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if (ptr == HPM_GPTMR4) { + if (as_comp == true) { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_GPTMR4_COMP_0; + } else if (channel == 3) { + HPM_IOC->PAD[IOC_PAD_PF15].FUNC_CTL = IOC_PF15_FUNC_CTL_GPTMR4_COMP_3; + } + } else if ((as_comp == false) && (channel == 0)) { + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0; + } + } else if (ptr == HPM_GPTMR5) { + if ((as_comp == true) && (channel == 2)) { + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_GPTMR5_COMP_2; + } + } +} + diff --git a/bsp/hpmicro/hpm6e00evk/board/pinmux.h b/bsp/hpmicro/hpm6e00evk/board/pinmux.h index 13633d11609..01aa0f437f6 100644 --- a/bsp/hpmicro/hpm6e00evk/board/pinmux.h +++ b/bsp/hpmicro/hpm6e00evk/board/pinmux.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 hpmicro + * Copyright (c) 2023-2024 hpmicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -13,7 +13,6 @@ extern "C" { #endif void init_uart_pins(UART_Type *ptr); void init_uart_pin_as_gpio(UART_Type *ptr); -void init_i2c_pins_as_gpio(I2C_Type *ptr); void init_i2c_pins(I2C_Type *ptr); void init_femc_pins(void); void init_ppi_pins(void); @@ -28,7 +27,7 @@ void init_qei_trgm_pins(void); void init_butn_pins(void); void init_acmp_pins(void); void init_pwm_pins(PWMV2_Type *ptr); -void init_usb_pins(void); +void init_usb_pins(USB_Type *ptr); void init_i2s_pins(I2S_Type *ptr); void init_qeo_pins(QEOV2_Type *ptr); void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); @@ -40,19 +39,26 @@ void init_dao_pins(void); void init_pdm_pins(void); void init_enet_pins(ENET_Type *ptr); void init_enet_pps_pins(void); +void init_enet_pps_capture_pins(void); void init_adc16_pins(void); void init_adc_bldc_pins(void); void init_adc_qeiv2_pins(void); void init_can_pins(MCAN_Type *ptr); void init_led_pins_as_gpio(void); void init_led_pins_as_pwm(void); -void init_plb_pins(void); +void init_plb_pulse_pins(void); +void init_plb_ab_pins(void); +void init_plb_lin_pins(void); +void init_plb_filter_pins(void); +void init_esc_eeprom_pin(void); +void init_esc_eeprom_as_i2c_pin(void); void init_esc_pins(void); void init_esc_in_out_pin(void); void init_tsw_pins(void); void init_tamper_pins(void); void init_pwm_fault_pins(void); void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); #ifdef __cplusplus } diff --git a/bsp/hpmicro/hpm6e00evk/board/rtt_board.c b/bsp/hpmicro/hpm6e00evk/board/rtt_board.c index ac67a31d8a6..034b6ea751b 100644 --- a/bsp/hpmicro/hpm6e00evk/board/rtt_board.c +++ b/bsp/hpmicro/hpm6e00evk/board/rtt_board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024 HPMicro + * Copyright (c) 2021-2023 HPMicro * SPDX-License-Identifier: BSD-3-Clause * */ @@ -8,6 +8,7 @@ #include "rtt_board.h" #include "hpm_uart_drv.h" #include "hpm_gpio_drv.h" +#include "hpm_mchtmr_drv.h" #include "hpm_pmp_drv.h" #include "assert.h" #include "hpm_clock_drv.h" @@ -60,6 +61,7 @@ void rtt_board_init(void) void app_init_led_pins(void) { + board_init_led_pins(); gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN); gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN); @@ -98,7 +100,7 @@ void rt_hw_console_output(const char *str) void app_init_usb_pins(void) { - board_init_usb_pins(); + board_init_usb(HPM_USB0); } ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) @@ -110,7 +112,7 @@ ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) void rt_hw_cpu_reset(void) { - HPM_PPOR->RESET_ENABLE = (1UL << 31); + HPM_PPOR->RESET_ENABLE |= (1UL << 31); HPM_PPOR->SOFTWARE_RESET = 1000U; while(1) { @@ -129,3 +131,83 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) } } #endif + +uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + clock_add_to_group(clock_adc0, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc0, 0); + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc1, 0); + freq = clock_get_frequency(clock_adc1); + } else if (ptr == (void *)HPM_ADC2) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc2, 0); + freq = clock_get_frequency(clock_adc2); + } else if (ptr == (void *)HPM_ADC3) { + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ana3); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + clock_add_to_group(clock_adc3, 0); + freq = clock_get_frequency(clock_adc3); + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWMV2_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_pwm0, 0); + freq = clock_get_frequency(clock_pwm0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_pwm1, 0); + freq = clock_get_frequency(clock_pwm1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_pwm2, 0); + freq = clock_get_frequency(clock_pwm2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_pwm3, 0); + freq = clock_get_frequency(clock_pwm3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif diff --git a/bsp/hpmicro/hpm6e00evk/board/rtt_board.h b/bsp/hpmicro/hpm6e00evk/board/rtt_board.h index 0c056aec764..539a7e8e4d1 100644 --- a/bsp/hpmicro/hpm6e00evk/board/rtt_board.h +++ b/bsp/hpmicro/hpm6e00evk/board/rtt_board.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 hpmicro + * Copyright (c) 2021 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -9,8 +9,12 @@ #define _RTT_BOARD_H #include "hpm_common.h" #include "hpm_soc.h" +#include "board.h" /* gpio section */ +#define APP_LED0 (0U) +#define APP_LED1 (1U) +#define APP_LED2 (2U) #define APP_LED0_GPIO_CTRL HPM_GPIO0 #define APP_LED0_GPIO_INDEX GPIO_DI_GPIOE #define APP_LED0_GPIO_PIN 14 @@ -28,6 +32,12 @@ /* mchtimer section */ #define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + /* CAN section */ #define BOARD_CAN_NAME "can4" #define BOARD_CAN_HWFILTER_INDEX (4U) @@ -45,8 +55,23 @@ #define BOARD_PWM_NAME "pwm1" #define BOARD_PWM_CHANNEL (0U) +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + #define IRQn_PendSV IRQn_DEBUG0 +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + /*************************************************************** * * RT-Thread related definitions diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig.h b/bsp/hpmicro/hpm6e00evk/rtconfig.h index 20a7dd994f3..b9d2d931601 100644 --- a/bsp/hpmicro/hpm6e00evk/rtconfig.h +++ b/bsp/hpmicro/hpm6e00evk/rtconfig.h @@ -61,7 +61,7 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 8 +#define RT_NAME_MAX 16 #define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 @@ -76,14 +76,11 @@ #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER /* kservice options */ /* end of kservice options */ -#define RT_USING_DEBUG -#define RT_DEBUGING_ASSERT -#define RT_DEBUGING_COLOR -#define RT_DEBUGING_CONTEXT /* Inter-Thread communication */ @@ -108,6 +105,8 @@ #define RT_VER_NUM 0x50201 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 /* RT-Thread Components */ @@ -132,14 +131,6 @@ /* DFS: device virtual file system */ -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FD_MAX 16 -#define RT_USING_DFS_V1 -#define DFS_FILESYSTEMS_MAX 4 -#define DFS_FILESYSTEM_TYPES_MAX 4 -#define RT_USING_DFS_DEVFS /* end of DFS: device virtual file system */ /* Device Drivers */ @@ -147,9 +138,9 @@ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE #define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_PIN /* end of Device Drivers */ @@ -312,6 +303,20 @@ /* NXP HAL & SDK Drivers */ /* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ /* end of HAL & SDK Drivers */ /* sensors drivers */ @@ -391,6 +396,7 @@ /* end of Arduino libraries */ /* end of RT-Thread online packages */ +#define SOC_HPM6E00_SERIES /* Hardware Drivers Config */ @@ -399,8 +405,12 @@ /* On-chip Peripheral Drivers */ #define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 #define BSP_USING_UART #define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 /* end of On-chip Peripheral Drivers */ /* end of Hardware Drivers Config */ diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig.py b/bsp/hpmicro/hpm6e00evk/rtconfig.py index 17038267b29..93cffbd04a9 100644 --- a/bsp/hpmicro/hpm6e00evk/rtconfig.py +++ b/bsp/hpmicro/hpm6e00evk/rtconfig.py @@ -1,8 +1,41 @@ -# Copyright 2021-2023 HPMicro +# Copyright 2021-2025 HPMicro # SPDX-License-Identifier: BSD-3-Clause import os import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + # toolchains options ARCH='risc-v' @@ -80,27 +113,27 @@ AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'ram_release': CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/ram_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' elif BUILD == 'flash_debug': CFLAGS += ' -gdwarf-2' AFLAGS += ' -gdwarf-2' CFLAGS += ' -O0' LFLAGS += ' -O0' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' elif BUILD == 'flash_release': CFLAGS += ' -O2' LFLAGS += ' -O2' CFLAGS += ' -DFLASH_XIP=1' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' else: CFLAGS += ' -O2' LFLAGS += ' -O2' - LINKER_FILE = 'board/linker_scripts/flash_rtt.ld' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' LFLAGS += ' -T ' + LINKER_FILE POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h new file mode 100644 index 00000000000..b7ae18b3266 --- /dev/null +++ b/bsp/hpmicro/hpm6e00evk/rtconfig_preinc.h @@ -0,0 +1,18 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HPM6880 +#define HPM6E80 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c index 1831ade7756..e3f85a9e0ee 100644 --- a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/startup.c @@ -32,6 +32,7 @@ void system_init(void) __attribute__((weak)) void c_startup(void) { +#ifndef __SES_RISCV uint32_t i, size; #ifdef FLASH_XIP extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; @@ -45,6 +46,10 @@ __attribute__((weak)) void c_startup(void) extern uint8_t __bss_start__[], __bss_end__[]; extern uint8_t __tbss_start__[], __tbss_end__[]; extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; extern uint8_t __data_start__[], __data_end__[]; extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; @@ -71,26 +76,27 @@ __attribute__((weak)) void c_startup(void) /* tdata section LMA: etext */ size = __tdata_end__ - __tdata_start__; for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__etext + i); + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); } /* data section LMA: etext */ size = __data_end__ - __data_start__; for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i); + *(__data_start__ + i) = *(__data_load_addr__ + i); } /* ramfunc section LMA: etext + data length */ size = __ramfunc_end__ - __ramfunc_start__; for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i); + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); } /* noncacheable init section LMA: etext + data length + ramfunc length */ size = __noncacheable_init_end__ - __noncacheable_init_start__; for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i); + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); } +#endif } __attribute__((weak)) int main(void) @@ -113,16 +119,16 @@ void reset_handler(void) /* Call platform specific hardware initialization */ system_init(); +#ifndef __SES_RISCV /* Do global constructors */ __libc_init_array(); - - +#endif /* Entry function */ entry(); } -__attribute__((weak)) void _init() +__attribute__((weak)) void _init(void) { } diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S index 2708b48e455..6e8933bd7af 100644 --- a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/port_gcc.S @@ -5,7 +5,8 @@ * */ #include "cpuport.h" - + .section .text.entry, "ax" + .align 2 .globl rt_hw_do_after_save_above .type rt_hw_do_after_save_above,@function rt_hw_do_after_save_above: diff --git a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S index 63433e71ae0..c2000769245 100644 --- a/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S +++ b/bsp/hpmicro/hpm6e00evk/startup/HPM6E80/toolchains/gcc/start.S @@ -77,7 +77,6 @@ _start: nmi_handler: 1: j 1b - .global default_irq_handler .weak default_irq_handler .align 2 default_irq_handler: diff --git a/bsp/hpmicro/hpm6p00evk/.config b/bsp/hpmicro/hpm6p00evk/.config new file mode 100644 index 00000000000..d5948b46cc6 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/.config @@ -0,0 +1,1441 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +CONFIG_RT_USING_CPU_USAGE_TRACER=y + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RISCV32=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +# CONFIG_RT_USING_SERIAL_V1 is not set +CONFIG_RT_USING_SERIAL_V2=y +# CONFIG_RT_SERIAL_BUF_STRATEGY_DROP is not set +CONFIG_RT_SERIAL_BUF_STRATEGY_OVERWRITE=y +CONFIG_RT_SERIAL_USING_DMA=y +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_NUCLEI_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers + +# +# HPMicro SDK +# +CONFIG_PKG_USING_HPM_SDK=y +CONFIG_PKG_HPM_SDK_PATH="/packages/peripherals/hal-sdk/hpmicro/hpm_sdk" +# CONFIG_PKG_USING_HPM_SDK_V110 is not set +CONFIG_PKG_USING_HPM_SDK_LATEST_VERSION=y +CONFIG_PKG_HPM_SDK_VER="latest" +# end of HPMicro SDK +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_HPM6P00_SERIES=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HPM6P00=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_GPIO_IRQ_PRIORITY=1 +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART0=y +# CONFIG_BSP_UART0_RX_USING_DMA is not set +# CONFIG_BSP_UART0_TX_USING_DMA is not set +CONFIG_BSP_UART0_RX_BUFSIZE=128 +CONFIG_BSP_UART0_TX_BUFSIZE=0 +CONFIG_BSP_UART0_IRQ_PRIORITY=1 +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_GPTMR is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_XPI_FLASH is not set +# CONFIG_BSP_USING_DAO is not set +# CONFIG_BSP_USING_PDM is not set +# CONFIG_BSP_USING_I2S is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_EWDG is not set +# CONFIG_BSP_USING_PWMV2 is not set +# CONFIG_BSP_USING_MCAN is not set +# CONFIG_BSP_USING_ADC is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/hpmicro/hpm6p00evk/.cproject b/bsp/hpmicro/hpm6p00evk/.cproject new file mode 100644 index 00000000000..eafefd8ef55 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/.cproject @@ -0,0 +1,227 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hpmicro/hpm6p00evk/.project b/bsp/hpmicro/hpm6p00evk/.project new file mode 100644 index 00000000000..0d08d5512da --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/.project @@ -0,0 +1,27 @@ + + + blink_led + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.rt-thread.studio.rttnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/bsp/hpmicro/hpm6p00evk/.settings/org.eclipse.core.runtime.prefs b/bsp/hpmicro/hpm6p00evk/.settings/org.eclipse.core.runtime.prefs new file mode 100644 index 00000000000..9f1acfcfba2 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/.settings/org.eclipse.core.runtime.prefs @@ -0,0 +1,3 @@ +content-types/enabled=true +content-types/org.eclipse.cdt.core.asmSource/file-extensions=s +eclipse.preferences.version=1 \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini b/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini new file mode 100644 index 00000000000..421ec3853ee --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/.settings/projcfg.ini @@ -0,0 +1,20 @@ +#RT-Thread Studio Project Configuration +# Fri Apr 25 13:53:29 2025 +cfg_version=v3.0 + +board_name= +bsp_version= +bsp_path= +chip_name= +project_base_rtt_bsp=true +is_use_scons_build=true +hardware_adapter= +selected_rtt_version=latest +board_base_nano_proj=false +is_base_example_project=false +example_name= +project_type=rt-thread +os_branch=master +os_version=latest +project_name=blink_led +output_project_path=D:\oss\rt-thread\bsp\hpmicro\hpm6e00evk \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/Kconfig b/bsp/hpmicro/hpm6p00evk/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hpmicro/hpm6p00evk/README.md b/bsp/hpmicro/hpm6p00evk/README.md new file mode 100644 index 00000000000..355edee54ed --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/README.md @@ -0,0 +1,115 @@ +# HPMicro HPM6P00EVK BSP(Board Support Package) Introduction + +[中文页](README_zh.md) | + +## Introduction + +This document provides brief introduction of the BSP (board support package) for the HPM6P00EVK development board. + +The document consists of the following parts: + +- HPM6P00EVK Board Resources Introduction +- Quickly Getting Started +- Refreences + +By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources. + +## Board Resources Introduction + +HPM6P00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, Audio, motor control，etc. +![board](figures/board.png) + + +## Peripheral Condition + +Each peripheral supporting condition for this BSP is as follows: + + +| **On-board Peripherals** | **Support** | **Note** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| Ethernet | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| AUDIO | √ | | +| PWM | √ | | +| On-Board Debugger | √ | ft2232 | + + +## Execution Instruction + +### Quickly Getting Started + +The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command + +#### Parpare Environment +- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain` +- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `\bin` + - For example: `C:\DevTools\riscv32-gnu-toolchain\bin` +- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro` + - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `\bin` + - For example: `C:\DevTools\openocd-hpmicro\bin` + +#### Configure and Build project + +Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can: + +- Configure the project via `menuconfig` in `RT-Thread ENV` +- Build the project using `scons -jN`, `N` equals to the number of CPU cores +- Clean the project using `scons -c` + +#### Hardware Connection + +- Switch BOOT pin to 2'b00 +- Connect the `PWR_DEBUG` port to PC via TYPE-C cable + + +#### Dowload / Debug + +- Users can download the project via the below command: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- Users can debug the project via the below command: + + - Connect debugger via `OpenOCD`: + +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg +``` + - Start Debugger via `GDB`: + +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + - In the `gdb shell`, type the following commands: + +```console +load +c +``` + +### **Running Results** + +Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically. + +Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **References** + +- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6P00EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6p00evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/README_zh.md b/bsp/hpmicro/hpm6p00evk/README_zh.md new file mode 100644 index 00000000000..e4a10fef31e --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/README_zh.md @@ -0,0 +1,114 @@ +# 先楫 HPM6P00EVK BSP(板级支持包)说明 + +[English](README.md) | + +## 简介 + +本文档为 HPM6P00EVK 的 BSP (板级支持包) 说明。 + +本文包含如下部分: + +- HPM6P00EVK 板级资源介绍 +- 快速上手指南 +- 参考链接 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 板级资源介绍 + +HPM6P00EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联、音频和电机控制等应用。 + +开发板外观如下图所示： + +![board](figures/board.png) + + +## 板载外设 + +本 BSP 目前对外设的支持情况如下: + + +| **板载外设** | **支持情况** | **备注** | +| ------------------------ | ----------- | ------------------------------------- | +| USB | √ | | +| QSPI Flash | √ | | +| 以太网 | √ | | +| GPIO | √ | | +| SPI | √ | | +| I2C | √ | | +| AUDIO | √ | | +| PWM | √ | | +| 板载调试器 | √ | ft2232 | + + +## 使用说明 + +### 快速开始 + +本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。 + +#### 准备环境 +- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool) +- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip) + - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain` +- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin` +- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip) + - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro` + - 将 `OPENOCD_HPMICRO`环境变量设置为 `\bin`，如： `C:\DevTools\openocd-hpmicro\bin` + +#### 配置和构建工程 + +通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以: + +- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能 +- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数 +- 通过 `scons -c` 命令清除构建 + +#### 硬件连接 + +- 将BOOT 引脚拨到2'b00 +- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑 + +#### 下载 和 调试 + +- 通过如下命令完成下载: + ```console + %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown" + ``` + +- 通过如下命令实现调试: + + - 通过 `OpenOCD` 来连接开发板: +```console +%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6p80-single-core.cfg -f boards\debug_scripts\boards\hpm6p00evk.cfg +``` + - 通过 `GDB` 实现调试: +```console +%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf +``` + + - 在`GDB Shell`中使用如下命令来加载和运行: + +```console +load +c +``` + +### **运行结果** + +一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。 + +配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志： + +``` + \ | / +- RT - Thread Operating System + / | \ 5.2.2 build Aug 16 2025 18:18:18 + 2006 - 2025 Copyright by RT-Thread team +``` + +## **参考链接** + +- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README) +- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md) +- [HPM6P00EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6p00evk) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/SConscript b/bsp/hpmicro/hpm6p00evk/SConscript new file mode 100644 index 00000000000..014c428d0a3 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/SConscript @@ -0,0 +1,17 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +ASFLAGS = ' -I' + cwd + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/hpm6p00evk/SConstruct b/bsp/hpmicro/hpm6p00evk/SConstruct new file mode 100644 index 00000000000..ce70828c063 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/SConstruct @@ -0,0 +1,64 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +AddOption('--run', + dest = 'run', + type='string', + nargs=1, + action = 'store', + default = "", + help = 'Upload or debug application using openocd') + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, + CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') + +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) +env['ASCOM'] = env['ASPPCOM'] + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(os.path.join(SDK_ROOT, 'libraries')): + libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries') +else: + libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries') + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + + +GDB = rtconfig.GDB + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + + + +# includes rtt drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hpmicro/hpm6p00evk/applications/SConscript b/bsp/hpmicro/hpm6p00evk/applications/SConscript new file mode 100644 index 00000000000..a65aa4d8553 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/applications/SConscript @@ -0,0 +1,14 @@ +import rtconfig + +from building import * + +cwd = GetCurrentDir() + +src = Glob('*.c') + +CPPDEFINES=[] +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6p00evk/applications/main.c b/bsp/hpmicro/hpm6p00evk/applications/main.c new file mode 100644 index 00000000000..a5a7f07c737 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/applications/main.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * Change Logs: + * Date Author Notes + * 2021-08-13 Fan YANG first version + * + */ + +#include +#include +#include "rtt_board.h" + +void thread_entry(void *arg); + +int main(void) +{ + app_init_led_pins(); + + static uint32_t led_thread_arg = 0; + rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10); + rt_thread_startup(led_thread); + + return 0; +} + +void thread_entry(void *arg) +{ + while(1){ + app_led_write(0, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(0, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(1, APP_LED_OFF); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_ON); + rt_thread_mdelay(500); + app_led_write(2, APP_LED_OFF); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hpmicro/hpm6p00evk/board/Kconfig b/bsp/hpmicro/hpm6p00evk/board/Kconfig new file mode 100644 index 00000000000..beaf5b3a9ed --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/Kconfig @@ -0,0 +1,634 @@ +menu "Hardware Drivers Config" + +config SOC_HPM6P00 + bool + select SOC_HPM6P00_SERIES + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +config BSP_USING_ENET_PHY_RTL8211 + bool + default n + +if BSP_USING_ETH + config LWIP_SUPPORT_CUSTOM_PBUF + int + default 1 +endif + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN if BSP_USING_GPIO + default n + if BSP_USING_GPIO + config BSP_GPIO_IRQ_PRIORITY + int "GPIO Interrupt Priority" + range 1 7 + default 1 + endif + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART0 + bool "Enable UART0 (Debugger)" + default y + if BSP_USING_UART0 + config BSP_UART0_RX_USING_DMA + bool "Enable UART0 RX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_TX_USING_DMA + bool "Enable UART0 TX DMA" + depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA + default n + config BSP_UART0_RX_BUFSIZE + int "Set UART0 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 128 + config BSP_UART0_TX_BUFSIZE + int "Set UART0 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART0_IRQ_PRIORITY + int "UART0 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART1_IRQ_PRIORITY + int "UART1 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART2_IRQ_PRIORITY + int "UART2 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART3_IRQ_PRIORITY + int "UART3 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART4_IRQ_PRIORITY + int "UART4 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART5_IRQ_PRIORITY + int "UART5 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART6_IRQ_PRIORITY + int "UART6 Interrupt Priority" + range 1 7 + default 1 + endif + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 1024 + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + config BSP_UART7_IRQ_PRIORITY + int "UART7 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + + menuconfig BSP_USING_SPI + bool "Enable SPI" + default n + select RT_USING_SPI if BSP_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI0 + bool "Enable SPI0" + default n + if BSP_USING_SPI0 + config BSP_SPI0_USING_DMA + bool "Enable SPI0 DMA" + default n + config BSP_SPI0_IRQ_PRIORITY + int "SPI0 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI0 CS TYPE" + default BSP_SPI0_USING_SOFT_CS + config BSP_SPI0_USING_SOFT_CS + bool "Enable SPI0 software cs" + config BSP_SPI0_USING_HARD_CS + bool "Enable SPI0 hardware cs" + endchoice + choice + prompt "Select SPI0 IO mode" + default BSP_SPI0_USING_SINGLE_IO + config BSP_SPI0_USING_SINGLE_IO + bool "Enable SPI0 single IO mode" + config BSP_SPI0_USING_DUAL_IO + bool "Enable SPI0 dual IO mode" + config BSP_SPI0_USING_QUAD_IO + bool "Enable SPI0 quad IO mode" + endchoice + endif + config BSP_USING_SPI1 + bool "Enable SPI1" + default n + if BSP_USING_SPI1 + config BSP_SPI1_USING_DMA + bool "Enable SPI1 DMA" + default n + config BSP_SPI1_IRQ_PRIORITY + int "SPI1 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI1 CS TYPE" + default BSP_SPI1_USING_SOFT_CS + config BSP_SPI1_USING_SOFT_CS + bool "Enable SPI1 software cs" + config BSP_SPI1_USING_HARD_CS + bool "Enable SPI1 hardware cs" + endchoice + choice + prompt "Select SPI1 IO mode" + default BSP_SPI1_USING_SINGLE_IO + config BSP_SPI1_USING_SINGLE_IO + bool "Enable SPI1 single IO mode" + config BSP_SPI1_USING_DUAL_IO + bool "Enable SPI1 dual IO mode" + config BSP_SPI1_USING_QUAD_IO + bool "Enable SPI1 quad IO mode" + endchoice + endif + config BSP_USING_SPI2 + bool "Enable SPI2" + default n + if BSP_USING_SPI2 + config BSP_SPI2_USING_DMA + bool "Enable SPI2 DMA" + default n + config BSP_SPI2_IRQ_PRIORITY + int "SPI2 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI2 CS TYPE" + default BSP_SPI2_USING_SOFT_CS + config BSP_SPI2_USING_SOFT_CS + bool "Enable SPI2 software cs" + config BSP_SPI2_USING_HARD_CS + bool "Enable SPI2 hardware cs" + endchoice + choice + prompt "Select SPI2 IO mode" + default BSP_SPI2_USING_SINGLE_IO + config BSP_SPI2_USING_SINGLE_IO + bool "Enable SPI2 single IO mode" + config BSP_SPI2_USING_DUAL_IO + bool "Enable SPI2 dual IO mode" + config BSP_SPI2_USING_QUAD_IO + bool "Enable SPI2 quad IO mode" + endchoice + endif + config BSP_USING_SPI3 + bool "Enable SPI3" + default n + if BSP_USING_SPI3 + config BSP_SPI3_USING_DMA + bool "Enable SPI3 DMA" + default n + config BSP_SPI3_IRQ_PRIORITY + int "SPI3 Interrupt Priority" + range 1 7 + default 1 + choice + prompt "Select SPI3 CS TYPE" + default BSP_SPI3_USING_SOFT_CS + config BSP_SPI3_USING_SOFT_CS + bool "Enable SPI3 software cs" + config BSP_SPI3_USING_HARD_CS + bool "Enable SPI3 hardware cs" + endchoice + choice + prompt "Select SPI3 IO mode" + default BSP_SPI3_USING_SINGLE_IO + config BSP_SPI3_USING_SINGLE_IO + bool "Enable SPI3 single IO mode" + config BSP_SPI3_USING_DUAL_IO + bool "Enable SPI3 dual IO mode" + config BSP_SPI3_USING_QUAD_IO + bool "Enable SPI3 quad IO mode" + endchoice + endif + endif + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + + select RT_USING_ETH if BSP_USING_ETH + select RT_USING_PHY if BSP_USING_ETH + + if BSP_USING_ETH + choice + prompt "ETH" + default BSP_USING_ETH0 + + config BSP_USING_ETH0 + bool "Enable ETH0" + select BSP_USING_ENET_PHY_RTL8211 + endchoice + endif + + menuconfig BSP_USING_GPTMR + bool "Enable GPTMR" + default n + select RT_USING_HWTIMER if BSP_USING_GPTMR + if BSP_USING_GPTMR + config BSP_USING_GPTMR0 + bool "Enable GPTMR0" + default n + if BSP_USING_GPTMR0 + config BSP_GPTMR0_IRQ_PRIORITY + int "GPTMR0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR1 + bool "Enable GPTMR1" + default n + if BSP_USING_GPTMR1 + config BSP_GPTMR1_IRQ_PRIORITY + int "GPTMR1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR2 + bool "Enable GPTMR2" + default n + if BSP_USING_GPTMR2 + config BSP_GPTMR2_IRQ_PRIORITY + int "GPTMR2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_GPTMR3 + bool "Enable GPTMR3" + default n + if BSP_USING_GPTMR3 + config BSP_GPTMR3_IRQ_PRIORITY + int "GPTMR3 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C if BSP_USING_I2C + if BSP_USING_I2C + config BSP_USING_I2C0 + bool "Enable I2C0" + default y + if BSP_USING_I2C0 + config BSP_I2C0_USING_DMA + bool "Enable I2C0 DMA" + default n + config BSP_I2C0_IRQ_PRIORITY + int "I2C0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C1 + bool "Enable I2C1" + default n + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool "Enable I2C1 DMA" + default n + config BSP_I2C1_IRQ_PRIORITY + int "I2C1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C2 + bool "Enable I2C2" + default n + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool "Enable I2C2 DMA" + default n + config BSP_I2C2_IRQ_PRIORITY + int "I2C2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_I2C3 + bool "Enable I2C3" + default n + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool "Enable I2C3 DMA" + default n + config BSP_I2C3_IRQ_PRIORITY + int "I2C3 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + + menuconfig BSP_USING_XPI_FLASH + bool "Enable XPI FLASH" + default n + select RT_USING_FAL if BSP_USING_XPI_FLASH + + menuconfig BSP_USING_DAO + bool "Enable Audio DAO play" + default n + select RT_USING_AUDIO if BSP_USING_DAO + + menuconfig BSP_USING_PDM + bool "Enable Audio PDM record" + default n + select RT_USING_AUDIO if BSP_USING_PDM + + menuconfig BSP_USING_I2S + bool "Enable Audio I2S device" + default n + select RT_USING_AUDIO if BSP_USING_I2S + if BSP_USING_I2S + config BSP_USING_I2S0 + bool "Enable I2S0" + default y + config BSP_USING_AUDIO_CODEC_WM8960 + bool "Enable audio codec on board" + default y + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + if BSP_USING_USB + config BSP_USING_USB_DEVICE + bool "Enable USB Device" + select RT_USING_CACHE + default n + config BSP_USING_USB_HOST + bool "Enable USB Host" + select RT_USING_CACHE + default n + endif + + + menuconfig BSP_USING_EWDG + bool "Enable EWDG" + default n + select RT_USING_WDT if BSP_USING_EWDG + if BSP_USING_EWDG + config BSP_USING_EWDG0 + bool "Enable EWDG0" + default n + config BSP_USING_EWDG1 + bool "Enable EWDG1" + default n + endif + + menuconfig BSP_USING_PWMV2 + bool "Enable PWM" + default n + select RT_USING_PWM if BSP_USING_PWMV2 + + menuconfig BSP_USING_MCAN + bool "Enable MCAN" + default n + select RT_USING_CAN if BSP_USING_MCAN + if BSP_USING_MCAN + config BSP_USING_MCAN0 + bool "Enable MCAN0" + default n + if BSP_USING_MCAN0 + config BSP_MCAN0_IRQ_PRIORITY + int "MCAN0 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_MCAN1 + bool "Enable MCAN1" + default n + if BSP_USING_MCAN1 + config BSP_MCAN1_IRQ_PRIORITY + int "MCAN1 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_MCAN2 + bool "Enable MCAN2" + default n + if BSP_USING_MCAN2 + config BSP_MCAN2_IRQ_PRIORITY + int "MCAN2 Interrupt Priority" + range 1 7 + default 1 + endif + config BSP_USING_MCAN3 + bool "Enable MCAN3" + default n + if BSP_USING_MCAN3 + config BSP_MCAN3_IRQ_PRIORITY + int "MCAN3 Interrupt Priority" + range 1 7 + default 1 + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC if BSP_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC16 + bool "Enable ADC16" + default n + if BSP_USING_ADC16 + config BSP_USING_ADC0 + bool "Enable ADC0" + default n + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + config BSP_USING_ADC3 + bool "Enable ADC3" + default n + endif + endif + +endmenu + + + + +endmenu + diff --git a/bsp/hpmicro/hpm6p00evk/board/SConscript b/bsp/hpmicro/hpm6p00evk/board/SConscript new file mode 100644 index 00000000000..631538058db --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/SConscript @@ -0,0 +1,19 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers +src = Split(""" + board.c + rtt_board.c + pinmux.c + fal_flash_port.c + hpm_wm8960.c +""") + +CPPPATH = [cwd] +CPPDEFINES=['D45', 'HPM6P81'] + +group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6p00evk/board/board.c b/bsp/hpmicro/hpm6p00evk/board/board.c new file mode 100644 index 00000000000..1c2f11ea064 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/board.c @@ -0,0 +1,884 @@ +/* + * Copyright (c) 2024,2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + * + */ + +#include "board.h" +#include "hpm_uart_drv.h" +#include "hpm_gptmr_drv.h" +#include "hpm_i2c_drv.h" +#include "hpm_gpio_drv.h" +#include "pinmux.h" +#include "hpm_pmp_drv.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include "hpm_pllctlv2_drv.h" +#include "hpm_pcfg_drv.h" +#include "hpm_enet_drv.h" +#include "hpm_usb_drv.h" +#include "hpm_femc_drv.h" +#include + +/** + * @brief FLASH configuration option definitions: + * option[0]: + * [31:16] 0xfcf9 - FLASH configuration option tag + * [15:4] 0 - Reserved + * [3:0] option words (exclude option[0]) + * option[1]: + * [31:28] Flash probe type + * 0 - SFDP SDR / 1 - SFDP DDR + * 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) + * 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V + * 6 - OctaBus DDR (SPI -> OPI DDR) + * 8 - Xccela DDR (SPI -> OPI DDR) + * 10 - EcoXiP DDR (SPI -> OPI DDR) + * [27:24] Command Pads after Power-on Reset + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [23:20] Command Pads after Configuring FLASH + * 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI + * [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) + * 0 - Not needed + * 1 - QE bit is at bit 6 in Status Register 1 + * 2 - QE bit is at bit1 in Status Register 2 + * 3 - QE bit is at bit7 in Status Register 2 + * 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 + * [15:8] Dummy cycles + * 0 - Auto-probed / detected / default value + * Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet + * [7:4] Misc. + * 0 - Not used + * 1 - SPI mode + * 2 - Internal loopback + * 3 - External DQS + * [3:0] Frequency option + * 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz + * + * option[2] (Effective only if the bit[3:0] in option[0] > 1) + * [31:20] Reserved + * [19:16] IO voltage + * 0 - 3V / 1 - 1.8V + * [15:12] Pin group + * 0 - 1st group / 1 - 2nd group + * [11:8] Connection selection + * 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) + * [7:0] Drive Strength + * 0 - Default value + * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports + * JESD216) + * [31:16] reserved + * [15:12] Sector Erase Command Option, not required here + * [11:8] Sector Size Option, not required here + * [7:0] Flash Size Option + * 0 - 4MB / 1 - 8MB / 2 - 16MB + */ +#if defined(FLASH_XIP) && FLASH_XIP +__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90002, 0x00000005, 0x1000, 0x0 }; +#endif + +#if defined(FLASH_UF2) && FLASH_UF2 +ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE; +#endif + +void board_init_console(void) +{ +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART + console_config_t cfg; + + /* uart needs to configure pin function before enabling clock, otherwise the level change of + * uart rx pin when configuring pin function will cause a wrong data to be received. + * And a uart rx dma request will be generated by default uart fifo dma trigger level. + */ + init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE); + + clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0); + + cfg.type = BOARD_CONSOLE_TYPE; + cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE; + cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME); + cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE; + + if (status_success != console_init(&cfg)) { + /* failed to initialize debug console */ + while (1) { + } + } +#else + while (1) + ; +#endif +#endif +} + +void board_print_clock_freq(void) +{ + printf("==============================\n"); + printf(" %s clock summary\n", BOARD_NAME); + printf("==============================\n"); + printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0)); + printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1)); + printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb0)); + printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif)); + printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis)); + printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic)); + printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0)); + printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc)); + printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0)); + printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1)); + printf("==============================\n"); +} + +void board_init_uart(UART_Type *ptr) +{ + /* configure uart's pin before opening uart's clock */ + init_uart_pins(ptr); + board_init_uart_clock(ptr); +} + +void board_print_banner(void) +{ + const uint8_t banner[] = { "\n\ +----------------------------------------------------------------------\n\ +$$\\ $$\\ $$$$$$$\\ $$\\ $$\\ $$\\\n\ +$$ | $$ |$$ __$$\\ $$$\\ $$$ |\\__|\n\ +$$ | $$ |$$ | $$ |$$$$\\ $$$$ |$$\\ $$$$$$$\\ $$$$$$\\ $$$$$$\\\n\ +$$$$$$$$ |$$$$$$$ |$$\\$$\\$$ $$ |$$ |$$ _____|$$ __$$\\ $$ __$$\\\n\ +$$ __$$ |$$ ____/ $$ \\$$$ $$ |$$ |$$ / $$ | \\__|$$ / $$ |\n\ +$$ | $$ |$$ | $$ |\\$ /$$ |$$ |$$ | $$ | $$ | $$ |\n\ +$$ | $$ |$$ | $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ | \\$$$$$$ |\n\ +\\__| \\__|\\__| \\__| \\__|\\__| \\_______|\\__| \\______/\n\ +----------------------------------------------------------------------\n" }; +#ifdef SDK_VERSION_STRING + printf("hpm_sdk: %s\n", SDK_VERSION_STRING); +#endif + printf("%s", banner); +} + +void board_ungate_mchtmr_at_lp_mode(void) +{ + /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */ + sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock); +} + +void board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); +#if BOARD_SHOW_CLOCK + board_print_clock_freq(); +#endif +#if BOARD_SHOW_BANNER + board_print_banner(); +#endif +} + +void board_init_core1(void) +{ + clock_update_core_clock(); + board_init_console(); + board_init_pmp(); +} + +void board_init_sdram_pins(void) +{ + init_femc_pins(); +} + +uint32_t board_init_femc_clock(void) +{ + clock_add_to_group(clock_femc, 0); + + /* Default FEMC clock is 166MHz */ + + /* Configure the FEMC to clk_src_pll1_clk0 / div, the clk_src_pll1_clk0 default frequency is 800MHz. */ + clock_set_source_divider(clock_femc, clk_src_pll1_clk0, 6U); /* Set FEMC clock to 133MHz */ + + return clock_get_frequency(clock_femc); +} + +void board_delay_us(uint32_t us) +{ + clock_cpu_delay_us(us); +} + +void board_delay_ms(uint32_t ms) +{ + clock_cpu_delay_ms(ms); +} + +#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT +static board_timer_cb timer_cb; +SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr) +void board_timer_isr(void) +{ + if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) { + gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH)); + timer_cb(); + } +} + +void board_timer_create(uint32_t ms, board_timer_cb cb) +{ + uint32_t gptmr_freq; + gptmr_channel_config_t config; + + timer_cb = cb; + gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config); + + clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0); + gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME); + + config.reload = gptmr_freq / 1000 * ms; + gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false); + gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH)); + intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1); + + gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH); +} +#endif + +void board_i2c_bus_clear(I2C_Type *ptr) +{ + if (i2c_get_line_scl_status(ptr) == false) { + printf("CLK is low, please power cycle the board\n"); + while (1) { + } + } + if (i2c_get_line_sda_status(ptr) == false) { + printf("SDA is low, try to issue I2C bus clear\n"); + } else { + printf("I2C bus is ready\n"); + return; + } + i2c_gen_reset_signal(ptr, 9); + board_delay_ms(100); + printf("I2C bus is cleared\n"); +} + +uint32_t board_init_i2c_clock(I2C_Type *ptr) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2C0) { + clock_add_to_group(clock_i2c0, 0); + freq = clock_get_frequency(clock_i2c0); + } else if (ptr == HPM_I2C1) { + clock_add_to_group(clock_i2c1, 0); + freq = clock_get_frequency(clock_i2c1); + } else if (ptr == HPM_I2C2) { + clock_add_to_group(clock_i2c2, 0); + freq = clock_get_frequency(clock_i2c2); + } else if (ptr == HPM_I2C3) { + clock_add_to_group(clock_i2c3, 0); + freq = clock_get_frequency(clock_i2c3); + } else { + ; + } + + return freq; +} + +void board_init_i2c(I2C_Type *ptr) +{ + i2c_config_t config; + hpm_stat_t stat; + uint32_t freq; + + freq = board_init_i2c_clock(ptr); + init_i2c_pins(ptr); + board_i2c_bus_clear(ptr); + + config.i2c_mode = i2c_mode_normal; + config.is_10bit_addressing = false; + stat = i2c_init_master(ptr, freq, &config); + if (stat != status_success) { + printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr); + while (1) { + } + } +} + +uint32_t board_init_spi_clock(SPI_Type *ptr) +{ + if (ptr == HPM_SPI0) { + clock_add_to_group(clock_spi0, 0); + return clock_get_frequency(clock_spi0); + } else if (ptr == HPM_SPI1) { + clock_add_to_group(clock_spi1, 0); + return clock_get_frequency(clock_spi1); + } else if (ptr == HPM_SPI2) { + clock_add_to_group(clock_spi2, 0); + return clock_get_frequency(clock_spi2); + } else if (ptr == HPM_SPI3) { + clock_add_to_group(clock_spi3, 0); + return clock_get_frequency(clock_spi3); + } + return 0; +} + +void board_init_gpio_pins(void) +{ + init_gpio_pins(); +} + +void board_init_spi_pins(SPI_Type *ptr) +{ + init_spi_pins(ptr); +} + +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + init_spi_pins_with_gpio_as_cs(ptr); + gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN), + GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL); +} + +void board_write_spi_cs(uint32_t pin, uint8_t state) +{ + gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state); +} + +uint8_t board_get_led_pwm_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +uint8_t board_get_led_gpio_off_level(void) +{ + return BOARD_LED_OFF_LEVEL; +} + +void board_init_led_pins(void) +{ + init_led_pins_as_gpio(); + gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level()); +} + +void board_led_toggle(void) +{ + gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN); +} + +void board_led_write(uint8_t state) +{ + gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state); +} + +void board_init_pmp(void) +{ + uint32_t start_addr; + uint32_t end_addr; + uint32_t length; + pmp_entry_t pmp_entry[16]; + uint8_t index = 0; + + /* Init noncachable memory */ + extern uint32_t __noncacheable_start__[]; + extern uint32_t __noncacheable_end__[]; + start_addr = (uint32_t) __noncacheable_start__; + end_addr = (uint32_t) __noncacheable_end__; + length = end_addr - start_addr; + if (length > 0) { + /* Ensure the address and the length are power of 2 aligned */ + assert((length & (length - 1U)) == 0U); + assert((start_addr & (length - 1U)) == 0U); + pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK); + pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length); + pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN); + index++; + } + + pmp_config(&pmp_entry[0], index); +} + +void board_init_clock(void) +{ + uint32_t cpu0_freq = clock_get_frequency(clock_cpu0); + if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) { + /* Configure the External OSC ramp-up time: ~9ms */ + pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32ul * 1000ul * 9u); + + /* select clock setting preset1 */ + sysctl_clock_set_preset(HPM_SYSCTL, 2); + } + /* Add Clocks to group 0 */ + clock_add_to_group(clock_cpu0, 0); + clock_add_to_group(clock_mchtmr0, 0); + clock_add_to_group(clock_ahb0, 0); + clock_add_to_group(clock_axif, 0); + clock_add_to_group(clock_axis, 0); + clock_add_to_group(clock_axic, 0); + clock_add_to_group(clock_rom0, 0); + clock_add_to_group(clock_xpi0, 0); + clock_add_to_group(clock_lmm0, 0); + clock_add_to_group(clock_lmm1, 0); + clock_add_to_group(clock_ram0, 0); + clock_add_to_group(clock_hdma, 0); + clock_add_to_group(clock_xdma, 0); + clock_add_to_group(clock_gpio, 0); + clock_add_to_group(clock_ptpc, 0); + /* Motor Related */ + clock_add_to_group(clock_qei0, 0); + clock_add_to_group(clock_qei1, 0); + clock_add_to_group(clock_qeo0, 0); + clock_add_to_group(clock_qeo1, 0); + clock_add_to_group(clock_pwm0, 0); + clock_add_to_group(clock_pwm1, 0); + clock_add_to_group(clock_pwm2, 0); + clock_add_to_group(clock_pwm3, 0); + clock_add_to_group(clock_rdc0, 0); + clock_add_to_group(clock_plb0, 0); + clock_add_to_group(clock_sei0, 0); + clock_add_to_group(clock_mtg0, 0); + clock_add_to_group(clock_vsc0, 0); + clock_add_to_group(clock_clc0, 0); + clock_add_to_group(clock_emds, 0); + /* Connect Group0 to CPU0 */ + clock_connect_group_to_cpu(0, 0); + + /* Add the CPU1 clock to Group1 */ + clock_add_to_group(clock_cpu1, 1); + clock_add_to_group(clock_mchtmr1, 1); + /* Connect Group1 to CPU1 */ + clock_connect_group_to_cpu(1, 1); + + /* Bump up DCDC voltage to 1275mv */ + pcfg_dcdc_set_voltage(HPM_PCFG, 1275); + + /* Set CPU clock to 600MHz */ + clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1); + clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1); + + /* Configure mchtmr to 24MHz */ + clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1); + clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1); + + clock_update_core_clock(); +} + +uint32_t board_init_uart_clock(UART_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_UART0) { + clock_add_to_group(clock_uart0, 0); + freq = clock_get_frequency(clock_uart0); + } else if (ptr == HPM_UART1) { + clock_add_to_group(clock_uart1, 0); + freq = clock_get_frequency(clock_uart1); + } else if (ptr == HPM_UART2) { + clock_add_to_group(clock_uart2, 0); + freq = clock_get_frequency(clock_uart2); + } else if (ptr == HPM_UART3) { + clock_add_to_group(clock_uart3, 0); + freq = clock_get_frequency(clock_uart3); + } else if (ptr == HPM_UART4) { + clock_add_to_group(clock_uart4, 0); + freq = clock_get_frequency(clock_uart4); + } else if (ptr == HPM_UART5) { + clock_add_to_group(clock_uart5, 0); + freq = clock_get_frequency(clock_uart5); + } else if (ptr == HPM_UART6) { + clock_add_to_group(clock_uart6, 0); + freq = clock_get_frequency(clock_uart6); + } else if (ptr == HPM_UART7) { + clock_add_to_group(clock_uart7, 0); + freq = clock_get_frequency(clock_uart7); + } else { + /* Not supported */ + } + return freq; +} + +#ifdef INIT_EXT_RAM_FOR_DATA +/* + * this function will be called during startup to initialize external memory for data use + */ +void _init_ext_ram(void) +{ + uint32_t femc_clk_in_hz; + femc_config_t config = {0}; + femc_sdram_config_t sdram_config = {0}; + + board_init_sdram_pins(); + femc_clk_in_hz = board_init_femc_clock(); + femc_default_config(HPM_FEMC, &config); + femc_init(HPM_FEMC, &config); + + femc_get_typical_sdram_config(HPM_FEMC, &sdram_config); + + sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4; + sdram_config.prescaler = 0x3; + sdram_config.burst_len_in_byte = 8; + sdram_config.auto_refresh_count_in_one_burst = 1; + sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS; + sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3; + + sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */ + sdram_config.refresh_recover_in_ns = 60; /* Trc */ + sdram_config.act_to_precharge_in_ns = 42; /* Tras */ + sdram_config.act_to_rw_in_ns = 18; /* Trcd */ + sdram_config.precharge_to_act_in_ns = 18; /* Trp */ + sdram_config.act_to_act_in_ns = 12; /* Trrd */ + sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */ + sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */ + + sdram_config.cs = BOARD_SDRAM_CS; + sdram_config.base_address = BOARD_SDRAM_ADDRESS; + sdram_config.size_in_byte = BOARD_SDRAM_SIZE; + sdram_config.port_size = BOARD_SDRAM_PORT_SIZE; + sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT; + sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS; + sdram_config.delay_cell_disable = false; + sdram_config.delay_cell_value = 13; + + femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config); +} +#endif + +void board_init_usb(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + init_usb_pins(ptr); + clock_add_to_group(clock_usb0, 0); + + usb_hcd_set_power_ctrl_polarity(ptr, true); + /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */ + board_delay_ms(100); + } +} + +uint32_t board_init_dao_clock(void) +{ + clock_add_to_group(clock_dao, 0); + + board_config_i2s_clock(DAO_I2S, 48000); + + return clock_get_frequency(clock_dao); +} + +uint32_t board_init_pdm_clock(void) +{ + clock_add_to_group(clock_pdm, 0); + + board_config_i2s_clock(PDM_I2S, 16000); + + return clock_get_frequency(clock_pdm); +} + +void board_init_i2s_pins(I2S_Type *ptr) +{ + init_i2s_pins(ptr); +} + +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate) +{ + uint32_t freq = 0; + + if (ptr == HPM_I2S0) { + clock_add_to_group(clock_i2s0, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud0, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud0, clk_src_pll2_clk0, 21); /* default 24576000Hz */ + } + clock_set_i2s_source(clock_i2s0, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud0 */ + freq = clock_get_frequency(clock_i2s0); + } else if (ptr == HPM_I2S1) { + clock_add_to_group(clock_i2s1, 0); + if ((sample_rate % 22050) == 0) { + clock_set_source_divider(clock_aud1, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */ + } else { + clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 21); /* default 24576000Hz */ + } + clock_set_i2s_source(clock_i2s1, clk_i2s_src_audn); /* clk_i2s_src_audn is equal to clk_i2s_src_aud1 */ + freq = clock_get_frequency(clock_i2s1); + } else { + ; + } + + return freq; +} + +void board_init_adc16_pins(void) +{ + init_adc16_pins(); +} + +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus) /* motor system should be use clk_adc_src_ahb0 */ +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + clock_add_to_group(clock_adc0, 0); + if (clk_src_bus) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + clock_add_to_group(clock_adc1, 0); + if (clk_src_bus) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == (void *)HPM_ADC2) { + clock_add_to_group(clock_adc2, 0); + if (clk_src_bus) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc2); + } else if (ptr == (void *)HPM_ADC3) { + clock_add_to_group(clock_adc3, 0); + if (clk_src_bus) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ana3); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc3); + } else { + ; + } + + return freq; +} + +void board_init_acmp_pins(void) +{ + init_acmp_pins(); +} + +void board_init_acmp_clock(ACMP_Type *ptr) +{ + (void)ptr; + clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1); +} + +void board_init_can(MCAN_Type *ptr) +{ + init_can_pins(ptr); +} + +uint32_t board_init_can_clock(MCAN_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_MCAN0) { + /* Set the CAN0 peripheral clock to 80MHz */ + clock_add_to_group(clock_can0, 0); + clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can0); + } else if (ptr == HPM_MCAN1) { + /* Set the CAN1 peripheral clock to 80MHz */ + clock_add_to_group(clock_can1, 0); + clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can1); + } else if (ptr == HPM_MCAN2) { + /* Set the CAN2 peripheral clock to 80MHz */ + clock_add_to_group(clock_can2, 0); + clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can2); + } else if (ptr == HPM_MCAN3) { + /* Set the CAN3 peripheral clock to 80MHz */ + clock_add_to_group(clock_can3, 0); + clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10); + freq = clock_get_frequency(clock_can3); + } else { + /* Invalid CAN instance */ + } + return freq; +} + +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr) +{ + /* set clock source */ + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1); + /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */ + /* clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); */ /* 100MHz */ + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_init_enet_pins(ENET_Type *ptr) +{ + init_enet_pins(ptr); + + if (ptr == HPM_ENET0) { + gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0); + board_delay_ms(1); + gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1); + } else { + return status_invalid_argument; + } + + return status_success; +} + +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr) +{ + (void) ptr; + return enet_pbl_32; +} + +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_enable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + intc_m_disable_irq(IRQn_ENET0); + } else { + return status_invalid_argument; + } + + return status_success; +} + +void board_init_enet_pps_pins(ENET_Type *ptr) +{ + (void) ptr; + init_enet_pps_pins(); +} + +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal) +{ + /* Configure Enet clock to output reference clock */ + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); + if (internal) { + /* set pll output frequency at 1GHz */ + if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll2, 1000000000UL) == status_success) { + /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */ + pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll2, pllctlv2_clk1, pllctlv2_div_4p0); + /* set eth clock frequency at 50MHz for enet0 */ + /* clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); */ + } else { + return status_fail; + } + } + } else { + return status_invalid_argument; + } + + enet_rmii_enable_clock(ptr, internal); /* defined in hpm_enet_soc_drv.h, not sure */ + + return status_success; +} + +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1); + return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY); + } + + return status_invalid_argument; +} + +void board_init_dao_pins(void) +{ + init_dao_pins(); +} + +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + init_sei_pins(ptr, sei_ctrl_idx); +} + +void board_init_adc_qeiv2_pins(void) +{ + init_adc_qeiv2_pins(); +} + +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb) +{ + (void)ptr; + (void)clk_src_ahb; + + if (ptr == HPM_DAC0) { + clock_add_to_group(clock_dac0, 0); + } else if (ptr == HPM_DAC1) { + clock_add_to_group(clock_dac1, 0); + } else { + ; + } + + return clock_get_frequency(clock_ahb0); +} + +void board_init_dac_pins(DAC_Type *ptr) +{ + init_dac_pins(ptr); +} + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + init_gptmr_channel_pin(ptr, channel, as_comp); +} + +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr) +{ + uint32_t freq = 0U; + if (ptr == HPM_GPTMR0) { + clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr0); + } else if (ptr == HPM_GPTMR1) { + clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr1); + } else if (ptr == HPM_GPTMR2) { + clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr2); + } else if (ptr == HPM_GPTMR3) { + clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_gptmr3); + } else if (ptr == HPM_PTMR) { + clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1); + freq = clock_get_frequency(clock_ptmr); + } else { + /* Not supported */ + } + return freq; +} diff --git a/bsp/hpmicro/hpm6p00evk/board/board.h b/bsp/hpmicro/hpm6p00evk/board/board.h new file mode 100644 index 00000000000..775eeb5833c --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/board.h @@ -0,0 +1,725 @@ +/* + * Copyright (c) 2024-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_BOARD_H +#define _HPM_BOARD_H +#include +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_soc_feature.h" +#include "hpm_clock_drv.h" +#include "hpm_lobs_drv.h" +#include "pinmux.h" +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#include "hpm_debug_console.h" +#endif + +#define BOARD_NAME "hpm6p00evk" +#define BOARD_UF2_SIGNATURE (0x0A4D5048UL) +#define BOARD_CPU_FREQ (600000000UL) + +#define SEC_CORE_IMG_START CORE1_ILM_LOCAL_BASE + +#ifndef BOARD_RUNNING_CORE +#define BOARD_RUNNING_CORE HPM_CORE0 +#endif + +/* ACMP desction */ +#define BOARD_ACMP HPM_ACMP2 +#define BOARD_ACMP_CLK clock_acmp2 +#define BOARD_ACMP_CHANNEL ACMP_CHANNEL_CHN0 +#define BOARD_ACMP_IRQ IRQn_ACMP2_0 +#define BOARD_ACMP_PLUS_INPUT ACMP_INPUT_DAC_OUT /* use internal DAC */ +#define BOARD_ACMP_MINUS_INPUT ACMP_INPUT_ANALOG_6 /* align with used pin */ + +/* uart section */ +#ifndef BOARD_APP_UART_BASE +#define BOARD_APP_UART_BASE HPM_UART4 +#define BOARD_APP_UART_IRQ IRQn_UART4 +#define BOARD_APP_UART_BAUDRATE (115200UL) +#define BOARD_APP_UART_CLK_NAME clock_uart4 +#define BOARD_APP_UART_RX_DMA_REQ HPM_DMA_SRC_UART4_RX +#define BOARD_APP_UART_TX_DMA_REQ HPM_DMA_SRC_UART4_TX +#endif + +#define BOARD_APP_UART_BREAK_SIGNAL_PIN IOC_PAD_PY05 + +/* Trigger UART: UART0~3 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG0, UART4~7 use HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 */ +#define BOARD_APP_UART_TRIG HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 +#define BOARD_UART_TRGM HPM_TRGM0 +#define BOARD_UART_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_UART_TRGM_GPTMR_CLK clock_gptmr3 +#define BOARD_UART_TRGM_GPTMR_CH 2 +#define BOARD_UART_TRGM_GPTMR_INPUT HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 + +/* uart rx idle demo section */ +#define BOARD_UART_IDLE BOARD_APP_UART_BASE +#define BOARD_UART_IDLE_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_IDLE_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_IDLE_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_UART_IDLE_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +#define BOARD_UART_IDLE_GPTMR HPM_GPTMR2 +#define BOARD_UART_IDLE_GPTMR_CLK_NAME clock_gptmr2 +#define BOARD_UART_IDLE_GPTMR_IRQ IRQn_GPTMR2 +#define BOARD_UART_IDLE_GPTMR_CMP_CH 0 +#define BOARD_UART_IDLE_GPTMR_CAP_CH 2 + +/* uart microros sample section */ +#define BOARD_MICROROS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MICROROS_UART_IRQ BOARD_APP_UART_IRQ +#define BOARD_MICROROS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME + +/* enet section */ +#define BOARD_ENET_PPS HPM_ENET0 +#define BOARD_ENET_PPS_IDX enet_pps_0 +#define BOARD_ENET_PPS_PTP_CLOCK clock_ptp0 + +#define BOARD_ENET_RGMII HPM_ENET0 +#define BOARD_ENET_RGMII_RST_GPIO HPM_GPIO0 +#define BOARD_ENET_RGMII_RST_GPIO_INDEX GPIO_DO_GPIOC +#define BOARD_ENET_RGMII_RST_GPIO_PIN (22U) +#define BOARD_ENET_RGMII_TX_DLY (0U) +#define BOARD_ENET_RGMII_RX_DLY (0U) +#define BOARD_ENET_RGMII_PTP_CLOCK (clock_ptp0) +#define BOARD_ENET_RGMII_PPS0_PINOUT (1) + +/* usb cdc acm uart section */ +#define BOARD_USB_CDC_ACM_UART BOARD_APP_UART_BASE +#define BOARD_USB_CDC_ACM_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_USB_CDC_ACM_UART_TX_DMA_SRC BOARD_APP_UART_TX_DMA_REQ +#define BOARD_USB_CDC_ACM_UART_RX_DMA_SRC BOARD_APP_UART_RX_DMA_REQ + +/* uart lin sample section */ +#define BOARD_UART_LIN BOARD_APP_UART_BASE +#define BOARD_UART_LIN_IRQ BOARD_APP_UART_IRQ +#define BOARD_UART_LIN_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_UART_LIN_TX_PORT GPIO_DI_GPIOY +#define BOARD_UART_LIN_TX_PIN (0U) /* PY00 should align with used pin in pinmux configuration */ +#define BOARD_UART_LIN_PLB_TRGM_IN_SRC HPM_TRGM0_INPUT_SRC_TRGM0_P08 /* align with used pin in pinmux configuration */ + +/* plb lin baudrate detection */ +#define BOARD_PLB_TRGM_FILTER_GPIO_INPUT0 HPM_TRGM0_FILTER_SRC_TRGM0_P00 +#define BOARD_PLB_TRGM_DMA_REQ0 HPM_TRGM0_DMA_SRC_TRGM0 + +#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE +#ifndef BOARD_CONSOLE_TYPE +#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART +#endif + +#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART +#ifndef BOARD_CONSOLE_UART_BASE +#if BOARD_RUNNING_CORE == HPM_CORE0 +#define BOARD_CONSOLE_UART_BASE HPM_UART0 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart0 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART0 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART0_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART0_RX +#else +#define BOARD_CONSOLE_UART_BASE HPM_UART4 +#define BOARD_CONSOLE_UART_CLK_NAME clock_uart4 +#define BOARD_CONSOLE_UART_IRQ IRQn_UART4 +#define BOARD_CONSOLE_UART_TX_DMA_REQ HPM_DMA_SRC_UART4_TX +#define BOARD_CONSOLE_UART_RX_DMA_REQ HPM_DMA_SRC_UART4_RX +#endif +#endif +#define BOARD_CONSOLE_UART_BAUDRATE (115200UL) +#endif +#endif + +/* rtthread-nano finsh section */ +#define BOARD_RT_CONSOLE_BASE BOARD_CONSOLE_UART_BASE +#define BOARD_RT_CONSOLE_CLK_NAME BOARD_CONSOLE_UART_CLK_NAME +#define BOARD_RT_CONSOLE_IRQ BOARD_CONSOLE_UART_IRQ + +/* modbus sample section */ +#define BOARD_MODBUS_UART_BASE BOARD_APP_UART_BASE +#define BOARD_MODBUS_UART_CLK_NAME BOARD_APP_UART_CLK_NAME +#define BOARD_MODBUS_UART_RX_DMA_REQ BOARD_APP_UART_RX_DMA_REQ +#define BOARD_MODBUS_UART_TX_DMA_REQ BOARD_APP_UART_TX_DMA_REQ + +/* sdram section */ +#define BOARD_SDRAM_ADDRESS (0x40000000UL) +#define BOARD_SDRAM_SIZE (32 * SIZE_1MB) +#define BOARD_SDRAM_CS FEMC_SDRAM_CS0 +#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS +#define BOARD_SDRAM_COLUMN_ADDR_BITS FEMC_SDRAM_COLUMN_ADDR_9_BITS +#define BOARD_SDRAM_REFRESH_COUNT (8192UL) +#define BOARD_SDRAM_REFRESH_IN_MS (64UL) + +#define BOARD_FEMC_ASYNC_SRAM_CS_INDEX 2 +#define BOARD_FEMC_ASYNC_SRAM_AD_MUX_MODE true +#define BOARD_FEMC_ASYNC_SRAM_SIZE (1024 * SIZE_1KB) + +/* nor flash section */ +#define BOARD_FLASH_BASE_ADDRESS (0x80000000UL) +#define BOARD_FLASH_SIZE (1 * SIZE_1MB) + +/* i2c section */ +#define BOARD_APP_I2C_BASE HPM_I2C1 +#define BOARD_APP_I2C_IRQ IRQn_I2C1 +#define BOARD_APP_I2C_CLK_NAME clock_i2c1 +#define BOARD_APP_I2C_DMA HPM_HDMA +#define BOARD_APP_I2C_DMAMUX HPM_DMAMUX +#define BOARD_APP_I2C_DMA_SRC HPM_DMA_SRC_I2C1 + +/* i2c for i2s codec section */ +#define BOARD_CODEC_I2C_BASE HPM_I2C3 +#define BOARD_CODEC_I2C_CLK_NAME clock_i2c3 + +/* PDM record data BUFF size */ +#define BOARD_PDM_USING_SMALL_BUFF true + +/* i2s section */ +#define BOARD_APP_I2S_BASE HPM_I2S0 +#define BOARD_APP_I2S_CLK_NAME clock_i2s0 +#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0 +#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0 +#define BOARD_APP_I2S_TX_DATA_LINE I2S_DATA_LINE_3 +#define BOARD_APP_I2S_RX_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_APP_I2S_TX_DMA_REQ HPM_DMA_SRC_I2S0_TX_3 +#define BOARD_APP_I2S_IRQ IRQn_I2S0 + +#define BOARD_MIC_I2S HPM_I2S0 +#define BOARD_MIC_I2S_CLK_NAME clock_i2s0 +#define BOARD_MIC_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_MIC_I2S_RX_DMAMUX_SRC HPM_DMA_SRC_I2S0_RX_0 + +#define BOARD_SPEAKER_I2S HPM_I2S1 +#define BOARD_SPEAKER_I2S_CLK_NAME clock_i2s1 +#define BOARD_SPEAKER_I2S_DATA_LINE I2S_DATA_LINE_0 +#define BOARD_SPEAKER_I2S_TX_DMAMUX_SRC HPM_DMA_SRC_I2S1_TX_0 + +/* pdm selection */ +#define BOARD_PDM_SINGLE_CHANNEL_MASK (1U) +#define BOARD_PDM_DUAL_CHANNEL_MASK (0x11U) + +/* dma section */ +#define BOARD_APP_XDMA HPM_XDMA +#define BOARD_APP_HDMA HPM_HDMA +#define BOARD_APP_XDMA_IRQ IRQn_XDMA +#define BOARD_APP_HDMA_IRQ IRQn_HDMA +#define BOARD_APP_DMAMUX HPM_DMAMUX +#define TEST_DMA_CONTROLLER HPM_XDMA +#define TEST_DMA_IRQ IRQn_XDMA + +/* APP PWM */ +#define BOARD_APP_PWM HPM_PWM1 +#define BOARD_APP_PWM_CLOCK_NAME clock_pwm1 +#define BOARD_APP_PWM_OUT1 pwm_channel_0 +#define BOARD_APP_PWM_OUT2 pwm_channel_1 +#define BOARD_APP_PWM_OUT3 pwm_channel_2 +#define BOARD_APP_PWM_OUT4 pwm_channel_3 +#define BOARD_APP_PWM_OUT5 pwm_channel_4 +#define BOARD_APP_PWM_OUT6 pwm_channel_5 +#define BOARD_APP_PWM_FAULT_PIN (2) +#define BOARD_APP_TRGM HPM_TRGM0 +#define BOARD_APP_PWM_IRQ IRQn_PWM1 +#define BOARD_APP_TRGM_PWM_OUTPUT HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0 +#define BOARD_APP_TRGM_PWM_OUTPUT1 HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1 +#define BOARD_APP_TRGM_PWM_OUTPUT2 HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2 +#define BOARD_APP_TRGM_PWM_INPUT HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 + +/* gptmr section */ +#define BOARD_GPTMR HPM_GPTMR3 +#define BOARD_GPTMR_IRQ IRQn_GPTMR3 +#define BOARD_GPTMR_CHANNEL 0 +#define BOARD_GPTMR_DMA_SRC HPM_DMA_SRC_GPTMR3_0 +#define BOARD_GPTMR_CLK_NAME clock_gptmr3 +#define BOARD_GPTMR_PWM HPM_GPTMR3 +#define BOARD_GPTMR_PWM_CHANNEL 0 +#define BOARD_GPTMR_PWM_DMA_SRC HPM_DMA_SRC_GPTMR3_0 +#define BOARD_GPTMR_PWM_CLK_NAME clock_gptmr3 +#define BOARD_GPTMR_PWM_IRQ IRQn_GPTMR3 +#define BOARD_GPTMR_PWM_SYNC HPM_GPTMR3 +#define BOARD_GPTMR_PWM_SYNC_CHANNEL 2 +#define BOARD_GPTMR_PWM_SYNC_CLK_NAME clock_gptmr3 + +/* User button */ +#define BOARD_APP_GPIO_CTRL HPM_GPIO0 +#define BOARD_APP_GPIO_INDEX GPIO_DI_GPIOC +#define BOARD_APP_GPIO_PIN 23 +#define BOARD_APP_GPIO_IRQ IRQn_GPIO0_C +#define BOARD_BUTTON_PRESSED_VALUE 0 + +/* gpiom section */ +#define BOARD_APP_GPIOM_BASE HPM_GPIOM +#define BOARD_APP_GPIOM_USING_CTRL HPM_FGPIO +#define BOARD_APP_GPIOM_USING_CTRL_NAME gpiom_core0_fast + +/* spi section */ +#define BOARD_APP_SPI_BASE HPM_SPI2 +#define BOARD_APP_SPI_CLK_NAME clock_spi2 +#define BOARD_APP_SPI_IRQ IRQn_SPI2 +#define BOARD_APP_SPI_SCLK_FREQ (20000000UL) +#define BOARD_APP_SPI_ADDR_LEN_IN_BYTES (1U) +#define BOARD_APP_SPI_DATA_LEN_IN_BITS (8U) +#define BOARD_APP_SPI_RX_DMA HPM_DMA_SRC_SPI2_RX +#define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI2_TX +#define BOARD_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_SPI_CS_PIN IOC_PAD_PY05 +#define BOARD_SPI_CS_ACTIVE_LEVEL (0U) + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 + +/* Flash section */ +#define BOARD_APP_XPI_NOR_XPI_BASE (HPM_XPI0) +#define BOARD_APP_XPI_NOR_CFG_OPT_HDR (0xfcf90002U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0 (0x00000005U) +#define BOARD_APP_XPI_NOR_CFG_OPT_OPT1 (0x00001000U) + +/* ADC section */ +#define BOARD_APP_ADC16_NAME "ADC2" +#define BOARD_APP_ADC16_BASE HPM_ADC2 +#define BOARD_APP_ADC16_IRQn IRQn_ADC2 +#define BOARD_APP_ADC16_CH_1 (10U) +#define BOARD_APP_ADC16_CLK_NAME (clock_adc2) +#define BOARD_APP_ADC16_CLK_BUS (clk_adc_src_ahb0) + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ TRGM_TRGOCFG_ADC2_STRGI + +#define BOARD_APP_ADC16_NAME_MASTER "ADC2" +#define BOARD_APP_ADC16_BASE_MASTER HPM_ADC2 +#define BOARD_APP_ADC16_IRQn_MASTER IRQn_ADC2 +#define BOARD_APP_ADC16_CLK_NAME_MASTER (clock_adc2) + +#define BOARD_APP_ADC16_NAME_SLAVE "ADC3" +#define BOARD_APP_ADC16_BASE_SLAVE HPM_ADC3 +#define BOARD_APP_ADC16_IRQn_SLAVE IRQn_ADC3 +#define BOARD_APP_ADC16_CLK_NAME_SLAVE (clock_adc3) + +#define BOARD_APP_ADC16_MASTER_CH_1 (1U) +#define BOARD_APP_ADC16_SLAVE_CH_1 (0U) + +#define BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME clock_pwm0 +#define BOARD_APP_ADC16_HW_TRIG_SRC HPM_PWM0 +#define BOARD_APP_ADC16_HW_TRGM HPM_TRGM0 +#define BOARD_APP_ADC16_HW_TRGM_IN HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ_MASTER TRGM_TRGOCFG_ADC2_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_SEQ_SLAVE TRGM_TRGOCFG_ADC3_STRGI +#define BOARD_APP_ADC16_HW_TRGM_OUT_PMT TRGM_TRGOCFG_ADCX_PTRGI0A + +#define BOARD_APP_ADC16_PMT_TRIG_CH ADC16_CONFIG_TRG0A + +/* DAC section */ +#define BOARD_DAC_BASE HPM_DAC0 +#define BOARD_DAC_IRQn IRQn_DAC0 +#define BOARD_APP_DAC_CLOCK_NAME clock_dac0 + +/* CAN section */ +#define BOARD_APP_CAN_BASE HPM_MCAN1 +#define BOARD_APP_CAN_IRQn IRQn_MCAN1 + +/* + * timer for board delay + */ +#define BOARD_DELAY_TIMER (HPM_GPTMR0) +#define BOARD_DELAY_TIMER_CH 0 +#define BOARD_DELAY_TIMER_CLK_NAME (clock_gptmr0) + +#define BOARD_CALLBACK_TIMER (HPM_GPTMR0) +#define BOARD_CALLBACK_TIMER_CH 1 +#define BOARD_CALLBACK_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr0) + +/* LED */ +#define BOARD_LED_GPIO_CTRL HPM_GPIO0 +#define BOARD_LED_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_LED_GPIO_PIN 25 +#define BOARD_LED_OFF_LEVEL 0 +#define BOARD_LED_ON_LEVEL 1 + +/* MOTOR */ +#define BOARD_MOTOR_CLK_NAME clock_mot0 + +/*BLDC PWM */ +#define BOARD_BLDCPWM HPM_PWM1 +#define BOARD_BLDC_UH_PWM_OUTPIN (pwm_channel_0) +#define BOARD_BLDC_UL_PWM_OUTPIN (pwm_channel_1) +#define BOARD_BLDC_VH_PWM_OUTPIN (pwm_channel_2) +#define BOARD_BLDC_VL_PWM_OUTPIN (pwm_channel_3) +#define BOARD_BLDC_WH_PWM_OUTPIN (pwm_channel_4) +#define BOARD_BLDC_WL_PWM_OUTPIN (pwm_channel_5) +#define BOARD_BLDCPWM_TRGM HPM_TRGM0 +#define BOARD_BLDCAPP_PWM_IRQ IRQn_PWM1 +#define BOARD_BLDCPWM_CMP_INDEX_0 (0U) +#define BOARD_BLDCPWM_CMP_INDEX_1 (1U) +#define BOARD_BLDCPWM_CMP_INDEX_2 (2U) +#define BOARD_BLDCPWM_CMP_INDEX_3 (3U) +#define BOARD_BLDCPWM_CMP_INDEX_4 (4U) +#define BOARD_BLDCPWM_CMP_INDEX_5 (5U) +#define BOARD_BLDCPWM_CMP_INDEX_6 (6U) +#define BOARD_BLDCPWM_CMP_INDEX_7 (7U) +#define BOARD_BLDCPWM_CMP_TRIG_CMP (16U) + +/* BLDC ADC */ +#define BOARD_BLDC_ADC_MODULE ADCX_MODULE_ADC16 +#define BOARD_BLDC_ADC_U_BASE HPM_ADC0 +#define BOARD_BLDC_ADC_V_BASE HPM_ADC2 +#define BOARD_BLDC_ADC_W_BASE HPM_ADC3 +#define BOARD_BLDC_ADC_TRIG_FLAG adc16_event_trig_complete + +#define BOARD_BLDC_ADC_CH_U (14U) +#define BOARD_BLDC_ADC_CH_V (8U) +#define BOARD_BLDC_ADC_CH_W (9U) +#define BOARD_BLDC_ADC_IRQn IRQn_ADC0 /* ADC_U_IRQ */ +#define BOARD_BLDC_ADC_PMT_DMA_SIZE_IN_4BYTES (ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES) +#define BOARD_BLDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_BLDC_ADC_PREEMPT_TRIG_LEN (1U) +#define BOARD_BLDC_PWM_TRIG_OUT_CHN (0U) +#define BOARD_BLDC_DMA_MUX_SRC HPM_DMA_SRC_MOT_0 +#define BOARD_BLDC_DMA_CHN (0U) +#define BOARD_BLDC_DMA_TRG_DST TRGM_TRGOCFG_TRGM_DMA0 +#define BOARD_BLDC_DMA_TRG_SRC HPM_TRGM0_DMA_SRC_TRGM0 +#define BOARD_BLDC_DMA_TRG_INDEX TRGM_DMACFG_0 +#define BOARD_BLDC_DMA_TRG_CMP_INDEX (9U) +#define BOARD_BLDC_DMA_TRG_IN HPM_TRGM0_INPUT_SRC_PWM0_CH9REF + +/* BLDC TRGM */ +#define BOARD_BLDC_PWM_TRG_ADC HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 +#define BOARD_BLDC_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A +#define BOARD_BLDC_TRG_VSC HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0 + +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC0 trgm_adc_matrix_output_to_vsc0_adc0 +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC1 trgm_adc_matrix_output_to_vsc0_adc1 +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_VSC_ADC2 trgm_adc_matrix_output_to_vsc0_adc2 +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_U trgm_adc_matrix_in_from_adc0 /* ADC_U_BASE */ +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_V trgm_adc_matrix_in_from_adc2 /* ADC_V_BASE */ +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_ADC_W trgm_adc_matrix_in_from_adc3 /* ADC_W_BASE */ + +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_CLC_ID_ADC trgm_adc_matrix_output_to_clc0_id_adc +#define BOARD_BLDC_TRGM_ADC_MATRIX_TO_CLC_IQ_ADC trgm_adc_matrix_output_to_clc0_iq_adc +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_VSC_ID_ADC trgm_adc_matrix_in_from_vsc0_id_adc +#define BOARD_BLDC_TRGM_ADC_MATRIX_FROM_VSC_IQ_ADC trgm_adc_matrix_in_from_vsc0_iq_adc + +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_QEO_VD_DAC trgm_dac_matrix_output_to_qeo0_vd_dac +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_QEO_VQ_DAC trgm_dac_matrix_output_to_qeo0_vq_dac +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_CLC_VD_DAC trgm_dac_matrix_in_from_clc0_vd_dac +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_CLC_VQ_DAC trgm_dac_matrix_in_from_clc0_vq_dac + +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC0 trgm_dac_matrix_output_to_pwm1_dac0 +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC1 trgm_dac_matrix_output_to_pwm1_dac1 +#define BOARD_BLDC_TRGM_DAC_MATRIX_TO_PWM_DAC2 trgm_dac_matrix_output_to_pwm1_dac2 +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC0 trgm_dac_matrix_in_from_qeo0_dac0 +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC1 trgm_dac_matrix_in_from_qeo0_dac1 +#define BOARD_BLDC_TRGM_DAC_MATRIX_FROM_QEO_DAC2 trgm_dac_matrix_in_from_qeo0_dac2 + +#define BOARD_BLDC_QEO HPM_QEO0 +#define BOARD_BLDC_TRGM_POS_MATRIX_TO_VSC trgm_pos_matrix_output_to_vsc0 +#define BOARD_BLDC_TRGM_POS_MATRIX_TO_QEO trgm_pos_matrix_output_to_qeo0 +#define BOARD_BLDC_TRGM_POS_MATRIX_FROM_QEI trgm_pos_matrix_in_from_qei0 + +/* BLDC TIMER */ +#define BOARD_BLDC_TMR_1MS HPM_GPTMR2 +#define BOARD_BLDC_TMR_BASE HPM_GPTMR2 +#define BOARD_BLDC_TMR_CH 0 +#define BOARD_BLDC_TMR_CMP 0 +#define BOARD_BLDC_TMR_IRQ IRQn_GPTMR2 +#define BOARD_BLDC_TMR_CLOCK clock_gptmr2 +#define BOARD_BLDC_TMR_RELOAD (100000U) + +/* BLDC PARAM */ +#define BOARD_BLDC_BLOCK_SPEED_KP (0.0005f) +#define BOARD_BLDC_BLOCK_SPEED_KI (0.000009f) + +#define BOARD_BLDC_HW_FOC_SPEED_KP (0.01f) +#define BOARD_BLDC_HW_FOC_SPEED_KI (0.001f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KP (0.0074f) +#define BOARD_BLDC_SW_FOC_SPEED_LOOP_SPEED_KI (0.0001f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KP (0.05f) +#define BOARD_BLDC_SW_FOC_POSITION_LOOP_SPEED_KI (0.001f) +#define BOARD_BLDC_HW_FOC_POSITION_KP (34.7f) +#define BOARD_BLDC_HW_FOC_POSITION_KI (0.113f) +#define BOARD_BLDC_SW_FOC_POSITION_KP (154.7f) +#define BOARD_BLDC_SW_FOC_POSITION_KI (0.113f) + +#define BOARD_BLDC_HFI_SPEED_LOOP_KP (40.0f) +#define BOARD_BLDC_HFI_SPEED_LOOP_KI (0.005f) +#define BOARD_BLDC_HFI_PLL_KP (11.0f) +#define BOARD_BLDC_HFI_PLL_KI (0.008f) + +/* HALL */ + +/* RDC */ +#define BOARD_RDC_BASE HPM_RDC0 +#define BOARD_RDC_TRGM HPM_TRGM0 +#define BOARD_RDC_TRG_IN HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0 +#define BOARD_RDC_TRG_OUT TRGM_TRGOCFG_TRGM0_P00 +#define BOARD_RDC_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A +#define BOARD_RDC_ADC_I_BASE HPM_ADC0 +#define BOARD_RDC_ADC_Q_BASE HPM_ADC2 +#define BOARD_RDC_ADC_I_CHN (14U) +#define BOARD_RDC_ADC_Q_CHN (8U) +#define BOARD_RDC_IRQ IRQn_RDC0 +#define BOARD_RDC_ADC_TRIG_FLAG adc16_event_trig_complete +#define BOARD_RDC_ADC_TRG ADC16_CONFIG_TRG0A +#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_rdc0_adc0 +#define BOARD_APP_RDC_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_rdc0_adc1 +#define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_I trgm_adc_matrix_in_from_adc0 +#define BOARD_APP_RDC_ADC_MATRIX_FROM_ADC_Q trgm_adc_matrix_in_from_adc2 + +/* QEIV2 */ +#define BOARD_BLDC_QEI_TRGM HPM_TRGM0 +#define BOARD_BLDC_QEIV2_BASE HPM_QEI0 +#define BOARD_BLDC_QEIV2_IRQ IRQn_QEI0 +#define BOARD_BLDC_QEI_MOTOR_PHASE_COUNT_PER_REV (16U) +#define BOARD_BLDC_QEI_CLOCK_SOURCE clock_qei0 +#define BOARD_BLDC_QEI_FOC_PHASE_COUNT_PER_REV (4000U) + +#define BOARD_APP_QEIV2_BASE HPM_QEI1 +#define BOARD_APP_QEIV2_IRQ IRQn_QEI1 +#define BOARD_APP_QEI_CLOCK_SOURCE clock_qei1 +#define BOARD_APP_QEI_ADC_COS_BASE HPM_ADC2 +#define BOARD_APP_QEI_ADC_COS_CHN (9U) +#define BOARD_APP_QEI_ADC_SIN_BASE HPM_ADC0 +#define BOARD_APP_QEI_ADC_SIN_CHN (14U) +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC0 trgm_adc_matrix_output_to_qei1_adc0 +#define BOARD_APP_QEI_ADC_MATRIX_TO_ADC1 trgm_adc_matrix_output_to_qei1_adc1 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_COS trgm_adc_matrix_in_from_adc2 +#define BOARD_APP_QEI_ADC_MATRIX_FROM_ADC_SIN trgm_adc_matrix_in_from_adc0 +#define BOARD_APP_QEI_TRG_ADC HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A + +/* PLB */ +#define BOARD_PLB_CLOCK_NAME clock_plb0 + +#define BOARD_PLB_COUNTER HPM_PLB +#define BOARD_PLB_PWM_BASE HPM_PWM0 +#define BOARD_PLB_PWM_CLOCK_NAME clock_mot0 +#define BOARD_PLB_TRGM HPM_TRGM0 +#define BOARD_PLB_PWM_TRG (HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0) +#define BOARD_PLB_IN_PWM_TRG (TRGM_TRGOCFG_PLB_IN_00) +#define BOARD_PLB_IN_PWM_PULSE_TRG (TRGM_TRGOCFG_PLB_IN_02) +#define BOARD_PLB_CLR_SIGNAL_INPUT (HPM_TRGM0_INPUT_SRC_PLB_OUT32) +#define BOARD_PLB_TO_TRG_IN (HPM_TRGM0_INPUT_SRC_PLB_OUT00) +#define BOARD_PLB_TRG_OUT (HPM_TRGM0_OUTPUT_SRC_TRGM0_P10) +#define BOARD_PLB_IO_TRG_SHIFT (10) +#define BOARD_PLB_PWM_CMP (8U) +#define BOARD_PLB_PWM_CHN (8U) +#define BOARD_PLB_CHN plb_chn0 + +#define BOARD_PLB_PHASE_COUNT_DEFAULT (4000) +#define BOARD_PLB_FILTER_LENGTH_DEFAULT (100) +#define BOARD_PLB_QEI_A_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P08 +#define BOARD_PLB_QEI_B_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P09 +#define BOARD_PLB_QEI_Z_PIN_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P10 + +#define BOARD_PLB_FILTER_SIG_INPUT_SOURCE HPM_TRGM0_INPUT_SRC_TRGM0_P10 +#define BOARD_PLB_FILTER_SIG_OUTUPT_SOURCE HPM_TRGM0_OUTPUT_SRC_TRGM0_P12 +#define BOARD_PLB_FILTER_IO_TRG_SHIFT (12) + +/* QEO */ +#define BOARD_QEO HPM_QEO1 +#define BOARD_QEO_TRGM_POS trgm_pos_matrix_output_to_qeo1 + +#define BOARD_QEO_PWM HPM_QEO1 /*QEO instance should align with PWM instance, such as QEO1 -> PWM1 */ +#define BOARD_QEO_TRGM_POS_PWM trgm_pos_matrix_output_to_qeo1 +#define BOARD_QEO_PWM_SAFETY_TRGM HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 + +/* SEI */ +#define BOARD_SEI HPM_SEI +#define BOARD_SEI_CTRL SEI_CTRL_1 +#define BOARD_SEI_IRQn IRQn_SEI0_1 +#define BOARD_SEI_CLOCK_NAME clock_sei0 +#define BOARD_TRGM_POS_SOURCE_SEI trgm_pos_matrix_in_from_sei_pos1 + +/* MTG */ +#define BOARD_TRGM_POS_DEST_MTG trgm_pos_matrix_output_to_mtg0 + +/* VSC */ +#define BOARD_VSC HPM_VSC0 +#define BOARD_VSC_IRQn IRQn_VSC0 + +/* CLC */ +#define BOARD_CLC HPM_CLC0 +#define BOARD_CLC_IRQn IRQn_CLC0_0 + +/* Tamper Section */ +#define BOARD_TAMP_ACTIVE_CH 4 +#define BOARD_TAMP_LOW_LEVEL_CH 6 + +/* sdm section */ +#define BOARD_SDM HPM_SDM0 +#define BOARD_SDM_IRQ IRQn_SDM0 +#define BOARD_SDM_CHANNEL 0 +#define BOARD_SDM_TRGM HPM_TRGM0 +#define BOARD_SDM_TRGM_GPTMR HPM_GPTMR3 +#define BOARD_SDM_TRGM_GPTMR_CLK clock_gptmr3 +#define BOARD_SDM_TRGM_GPTMR_CH 2 +#define BOARD_SDM_TRGM_INPUT_SRC HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 +#define BOARD_SDM_TRGM_OUTPUT_DST HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15 +#define BOARD_SDM_TRGM_SYNC_SRC (15) +/* need to provide clock to sdm sensor */ +#define BOARD_SDM_SENSOR_REQUIRE_CLK true +#define BOARD_SDM_CLK_PWM HPM_PWM0 +#define BOARD_SDM_CLK_PWM_CLK_NAME clock_pwm0 +#define BOARD_SDM_CLK_PWM_OUT (2) + +#ifndef BOARD_SHOW_CLOCK +#define BOARD_SHOW_CLOCK 1 +#endif +#ifndef BOARD_SHOW_BANNER +#define BOARD_SHOW_BANNER 1 +#endif + +/* FreeRTOS Definitions */ +#define BOARD_FREERTOS_TIMER HPM_GPTMR2 +#define BOARD_FREERTOS_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_FREERTOS_TIMER_CLK_NAME clock_gptmr2 + +#define BOARD_FREERTOS_TICK_SRC_PWM HPM_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_IRQ IRQn_PWM0 +#define BOARD_FREERTOS_TICK_SRC_PWM_CLK_NAME clock_pwm0 +#define BOARD_FREERTOS_TICK_SRC_PWM_COUNTER pwm_counter_0 +#define BOARD_FREERTOS_TICK_SRC_PWM_SHADOW PWMV2_SHADOW_INDEX(0) + +#define BOARD_FREERTOS_LOWPOWER_TIMER HPM_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_FREERTOS_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_FREERTOS_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* Threadx Definitions */ +#define BOARD_THREADX_TIMER HPM_GPTMR2 +#define BOARD_THREADX_TIMER_CHANNEL 1 +#define BOARD_THREADX_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_THREADX_TIMER_CLK_NAME clock_gptmr2 + +#define BOARD_THREADX_LOWPOWER_TIMER HPM_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CHANNEL 1 +#define BOARD_THREADX_LOWPOWER_TIMER_IRQ IRQn_PTMR +#define BOARD_THREADX_LOWPOWER_TIMER_CLK_NAME clock_ptmr + +/* uC/OS-III Definitions */ +#define BOARD_UCOS_TIMER HPM_GPTMR2 +#define BOARD_UCOS_TIMER_CHANNEL 1 +#define BOARD_UCOS_TIMER_IRQ IRQn_GPTMR2 +#define BOARD_UCOS_TIMER_CLK_NAME clock_gptmr2 + +/* LOBS */ +#define BOARD_LOBS_TRIG_GROUP lobs_signal_group_PC +#define BOARD_LOBS_TRIG_PIN_0 28 +#define BOARD_LOBS_TRIG_PIN_1 29 + +/* i2s over spi Section*/ +#define BOARD_I2S_SPI_CS_GPIO_CTRL HPM_GPIO0 +#define BOARD_I2S_SPI_CS_GPIO_INDEX GPIO_DI_GPIOA +#define BOARD_I2S_SPI_CS_GPIO_PIN 16 +#define BOARD_I2S_SPI_CS_GPIO_PAD IOC_PAD_PA16 + +#define BOARD_GPTMR_I2S_MCLK HPM_GPTMR0 +#define BOARD_GPTMR_I2S_MCLK_CHANNEL 2 +#define BOARD_GPTMR_I2S_MCLK_CLK_NAME clock_gptmr0 + +#define BOARD_GPTMR_I2S_LRCK HPM_GPTMR3 +#define BOARD_GPTMR_I2S_LRCK_CHANNEL 0 +#define BOARD_GPTMR_I2S_LRCK_CLK_NAME clock_gptmr3 + +#define BOARD_GPTMR_I2S_BCLK HPM_GPTMR3 +#define BOARD_GPTMR_I2S_BLCK_CHANNEL 2 +#define BOARD_GPTMR_I2S_BLCK_CLK_NAME clock_gptmr3 + +#define BOARD_GPTMR_I2S_FINSH HPM_GPTMR3 +#define BOARD_GPTMR_I2S_FINSH_IRQ IRQn_GPTMR3 +#define BOARD_GPTMR_I2S_FINSH_CHANNEL 1 +#define BOARD_GPTMR_I2S_FINSH_CLK_NAME clock_gptmr3 + +/* PPI */ +#define BOARD_PPI_ASYNC_SRAM_AD_MUX_MODE true +#define BOARD_PPI_ASYNC_SRAM_CS_INDEX 3 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ0_7 ppi_dq_pins_0_7 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ8_15 ppi_dq_pins_8_15 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ16_23 ppi_dq_pins_16_23 +#define BOARD_PPI_ASYNC_SRAM_SIG_DQ24_31 ppi_dq_pins_24_31 +#define BOARD_PPI_ASYNC_SRAM_ADV_CTRL_PIN 7 +#define BOARD_PPI_ASYNC_SRAM_WE_CTRL_PIN 6 +#define BOARD_PPI_ASYNC_SRAM_OE_CTRL_PIN 5 +#define BOARD_PPI_ASYNC_SRAM_SIZE (1024 * SIZE_1KB) + +#define BOARD_PPI_ADC_CS_INDEX 2 + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +typedef void (*board_timer_cb)(void); + +void board_init(void); +void board_init_console(void); +void board_init_core1(void); +void board_init_uart(UART_Type *ptr); +uint32_t board_init_i2c_clock(I2C_Type *ptr); +void board_init_i2c(I2C_Type *ptr); +void board_init_can(MCAN_Type *ptr); +void board_init_femc_pins(void); +void board_init_gpio_pins(void); +void board_init_spi_pins(SPI_Type *ptr); +void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void board_write_spi_cs(uint32_t pin, uint8_t state); +uint8_t board_get_led_gpio_off_level(void); +void board_init_led_pins(void); +void board_led_write(uint8_t state); +void board_led_toggle(void); + +/* Initialize SoC overall clocks */ +void board_init_clock(void); +uint32_t board_init_femc_clock(void); +uint32_t board_init_uart_clock(UART_Type *ptr); +uint32_t board_init_spi_clock(SPI_Type *ptr); +uint32_t board_init_can_clock(MCAN_Type *ptr); +uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus); +uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb); +void board_init_acmp_clock(ACMP_Type *ptr); +void board_init_i2s_pins(I2S_Type *ptr); +uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate); +uint32_t board_init_pdm_clock(void); +uint32_t board_init_dao_clock(void); +void board_init_dao_pins(void); +void board_init_adc16_pins(void); +void board_init_acmp_pins(void); +void board_init_dac_pins(DAC_Type *ptr); +void board_init_usb(USB_Type *ptr); +void board_init_enet_pps_pins(ENET_Type *ptr); +uint8_t board_get_enet_dma_pbl(ENET_Type *ptr); +hpm_stat_t board_reset_enet_phy(ENET_Type *ptr); +hpm_stat_t board_init_enet_pins(ENET_Type *ptr); +hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal); +hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr); +hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr); +hpm_stat_t board_enable_enet_irq(ENET_Type *ptr); +hpm_stat_t board_disable_enet_irq(ENET_Type *ptr); + +/* + * @brief Initialize PMP and PMA for but not limited to the following purposes: + * -- non-cacheable memory initialization + */ +void board_init_pmp(void); +void board_delay_us(uint32_t us); +void board_delay_ms(uint32_t ms); +void board_timer_create(uint32_t ms, board_timer_cb cb); +void board_ungate_mchtmr_at_lp_mode(void); + +/* + * Get GPIO pin level of onboard LED + */ +uint8_t board_get_led_gpio_off_level(void); +void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void board_init_adc_qeiv2_pins(void); + +void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +uint32_t board_init_gptmr_clock(GPTMR_Type *ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _HPM_BOARD_H */ diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg new file mode 100644 index 00000000000..9e3359ae885 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/boards/hpm6p00evk.cfg @@ -0,0 +1,80 @@ +# Copyright (c) 2024,2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +# openocd flash driver argument: +# - option0: +# [31:28] Flash probe type +# 0 - SFDP SDR / 1 - SFDP DDR +# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address) +# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V +# 6 - OctaBus DDR (SPI -> OPI DDR) +# 8 - Xccela DDR (SPI -> OPI DDR) +# 10 - EcoXiP DDR (SPI -> OPI DDR) +# [27:24] Command Pads after Power-on Reset +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [23:20] Command Pads after Configuring FLASH +# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI +# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only) +# 0 - Not needed +# 1 - QE bit is at bit6 in Status Register 1 +# 2 - QE bit is at bit1 in Status Register 2 +# 3 - QE bit is at bit7 in Status Register 2 +# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31 +# [15:8] Dummy cycles +# 0 - Auto-probed / detected / default value +# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet +# [7:4] Misc. +# 0 - Not used +# 1 - SPI mode +# 2 - Internal loopback +# 3 - External DQS +# [3:0] Frequency option +# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz +# - option1: +# [31:20] Reserved +# [19:16] IO voltage +# 0 - 3V / 1 - 1.8V +# [15:12] Pin group +# 0 - 1st group / 1 - 2nd group +# [11:8] Connection selection +# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively) +# [7:0] Drive Strength +# 0 - Default value + +# xpi0 configs +# - flash driver: hpm_xpi +# - flash ctrl index: 0xF3000000 +# - base address: 0x80000000 +# - flash size: 0x2000000 +# - flash option0: 0x5 +# - flash option1: 0x1000 +flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000 + +proc init_clock {} { + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x1 + + $::_TARGET0 riscv dmi_write 0x39 0xF4002000 + $::_TARGET0 riscv dmi_write 0x3C 0x2 + + $::_TARGET0 riscv dmi_write 0x39 0xF4000800 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000810 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000820 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + + $::_TARGET0 riscv dmi_write 0x39 0xF4000830 + $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF + echo "clocks has been enabled!" +} + +$_TARGET0 configure -event reset-init { + init_clock +} + +$_TARGET0 configure -event gdb-attach { + reset halt +} diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg new file mode 100644 index 00000000000..b9ae1121044 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/cmsis_dap.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/cmsis-dap.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg new file mode 100644 index 00000000000..580d98ef853 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft2232.cfg @@ -0,0 +1,15 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0208 0x020b +ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800 + diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg new file mode 100644 index 00000000000..4fb0fba2e70 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/ft232.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +reset_config trst_and_srst +adapter srst delay 50 + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6014 + +ftdi_layout_init 0x0018 0x001b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg new file mode 100644 index 00000000000..fd8f04428c9 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/jlink.cfg @@ -0,0 +1,11 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 + +source [find interface/jlink.cfg] + +transport select jtag +reset_config srst_only diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg new file mode 100644 index 00000000000..e9d6e6d6984 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/probes/nds_aice_micro.cfg @@ -0,0 +1,14 @@ +# Copyright 2021 hpmicro +# SPDX-License-Identifier: BSD-3-Clause + +bindto 0.0.0.0 +adapter speed 10000 +adapter srst delay 500 +reset_config srst_only + +adapter driver ftdi +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x010b +ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400 +ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800 diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg new file mode 100644 index 00000000000..a3f2ee73f0c --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-dual-core.cfg @@ -0,0 +1,67 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause +# + + +set _CHIP hpm6p00 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +# source [find soc/hpm_common_csr.cfg] + +proc dmi_write {reg value} { + $::_TARGET0 riscv dmi_write ${reg} ${value} +} + +proc dmi_read {reg} { + set v [$::_TARGET0 riscv dmi_read ${reg}] + return ${v} +} +proc dmi_write_memory {addr value} { + dmi_write 0x39 ${addr} + dmi_write 0x3C ${value} +} + +proc dmi_read_memory {addr} { + set sbcs [expr { 0x100000 | [dmi_read 0x38] }] + dmi_write 0x38 ${sbcs} + dmi_write 0x39 ${addr} + set value [dmi_read 0x3C] + return ${value} +} + +proc release_core1 {} { + dmi_write_memory 0xF4002C00 0x1000 +} + +set _TARGET1 $_CHIP.cpu1 +target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1 +$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +# source [find soc/hpm_common_csr.cfg] + +$_TARGET1 configure -event examine-start { + release_core1 +} + +$_TARGET1 configure -event reset-deassert-pre { + $::_TARGET0 arp_poll + release_core1 +} + +$_TARGET0 configure -event reset-end { + $::_TARGET0 riscv dmi_write 0x39 0xF4002010 + $::_TARGET0 riscv dmi_write 0x3C 0x2 +} + +proc reset_soc {} { + $::_TARGET0 riscv dmi_write 0x39 0xF410001C + $::_TARGET0 riscv dmi_write 0x3C 24000000 +} diff --git a/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg new file mode 100644 index 00000000000..e370159ab6f --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/debug_scripts/openocd/soc/hpm6p80-single-core.cfg @@ -0,0 +1,20 @@ +# Copyright (c) 2024 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +set _CHIP hpm6p00 +set _CPUTAPID 0x1000563D +jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID + +set _TARGET0 $_CHIP.cpu0 +target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0 + +$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0 + +targets $_TARGET0 + +# source [find soc/hpm_common_csr.cfg] + +proc reset_soc {} { + $::_TARGET0 riscv dmi_write 0x39 0xF410001C + $::_TARGET0 riscv dmi_write 0x3C 24000000 +} diff --git a/bsp/hpmicro/hpm6p00evk/board/fal_cfg.h b/bsp/hpmicro/hpm6p00evk/board/fal_cfg.h new file mode 100644 index 00000000000..c79baa66c2f --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/fal_cfg.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +#ifdef RT_USING_FAL +#define NOR_FLASH_DEV_NAME "norflash0" +#define NOR_FLASH_MEM_BASE 0x80000000UL +#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL + +/* ===================== Flash device Configuration ========================= */ +extern struct fal_flash_dev nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &nor_flash0, \ +} +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 256*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 512*1024, 256*1024, 0}, \ + {FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 768*1024, 256*1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ +#endif /* RT_USING_FAL */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hpmicro/hpm6p00evk/board/fal_flash_port.c b/bsp/hpmicro/hpm6p00evk/board/fal_flash_port.c new file mode 100644 index 00000000000..7be597c903f --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/fal_flash_port.c @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2022 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2022-03-09 hpmicro First implementation + * 2022-08-01 hpmicro Fixed random crashing during kvdb_init + * 2022-08-03 hpmicro Improved erase speed + * 2023-05-15 hpmicro Disable global interrupt during FLASH operation for FLASH build + * + */ +#include +#include +#ifdef RT_USING_FAL +#include "fal.h" +#include "hpm_romapi.h" +#include "board.h" +#include "hpm_l1c_drv.h" + +#if defined(FLASH_XIP) && (FLASH_XIP == 1) + +static rt_base_t s_interrupt_level; +#define FAL_ENTER_CRITICAL() do {\ + rt_exit_critical();\ + fencei();\ + s_interrupt_level = rt_hw_interrupt_disable();\ + } while(0) + +#define FAL_EXIT_CRITICAL() do {\ + ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\ + fencei();\ + rt_exit_critical();\ + rt_hw_interrupt_enable(s_interrupt_level);\ + } while(0) + +#define FAL_RAMFUNC __attribute__((section(".isr_vector"))) + +#else +#define FAL_ENTER_CRITICAL() rt_enter_critical() + +#define FAL_EXIT_CRITICAL() rt_exit_critical() + +#define FAL_RAMFUNC + +#endif + +/*************************************************************************************************** + * FAL Porting Guide + * + * 1. Most FLASH devices do not support RWW (Read-while-Write), the codes to access the FLASH + * must be placed at RAM or ROM code + * 2. During FLASH erase/program, it is recommended to disable the interrupt, or place the + * interrupt related codes to RAM + * + ***************************************************************************************************/ + +static int init(void); +static int read(long offset, rt_uint8_t *buf, rt_size_t size); +static int write(long offset, const rt_uint8_t *buf, rt_size_t size); +static int erase(long offset, rt_size_t size); + +static xpi_nor_config_t s_flashcfg; + +/** + * @brief FAL Flash device context + */ +struct fal_flash_dev nor_flash0 = + { + .name = NOR_FLASH_DEV_NAME, + /* If porting this code to the device with FLASH connected to XPI1, the address must be changed to 0x90000000 */ + .addr = NOR_FLASH_MEM_BASE, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = { .init = init, .read = read, .write = write, .erase = erase }, + .write_gran = 1 + }; + +/** + * @brief FAL initialization + * This function probes the FLASH using the ROM API + */ +FAL_RAMFUNC static int init(void) +{ + int ret = RT_EOK; + xpi_nor_config_option_t cfg_option; + cfg_option.header.U = BOARD_APP_XPI_NOR_CFG_OPT_HDR; + cfg_option.option0.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT0; + cfg_option.option1.U = BOARD_APP_XPI_NOR_CFG_OPT_OPT1; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_auto_config(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, &cfg_option); + FAL_EXIT_CRITICAL(); + if (status != status_success) + { + ret = -RT_ERROR; + } + else + { + /* update the flash chip information */ + rt_uint32_t sector_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + rt_uint32_t flash_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_total_size, &flash_size); + nor_flash0.blk_size = sector_size; + nor_flash0.len = flash_size; + } + + return ret; +} + +/** + * @brief FAL read function + * Read data from FLASH + * @param offset FLASH offset + * @param buf Buffer to hold data read by this API + * @param size Size of data to be read + * @return actual read bytes + */ +FAL_RAMFUNC static int read(long offset, rt_uint8_t *buf, rt_size_t size) +{ + rt_uint32_t flash_addr = nor_flash0.addr + offset; + rt_uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(flash_addr); + rt_uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(flash_addr + size); + rt_uint32_t aligned_size = aligned_end - aligned_start; + rt_base_t level = rt_hw_interrupt_disable(); + l1c_dc_invalidate(aligned_start, aligned_size); + rt_hw_interrupt_enable(level); + + (void) rt_memcpy(buf, (void*) flash_addr, size); + + return size; +} + +/** + * @brief Write unaligned data to the page + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write_unaligned_page_data(long offset, const rt_uint32_t *buf, rt_size_t size) +{ + hpm_stat_t status; + + FAL_ENTER_CRITICAL(); + status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, buf, offset, size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + return -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + } + + return size; +} + +/** + * @brief FAL write function + * Write data to specified FLASH address + * @param offset FLASH offset + * @param buf Data buffer + * @param size Size of data to be written + * @return actual size of written data or error code + */ +FAL_RAMFUNC static int write(long offset, const rt_uint8_t *buf, rt_size_t size) +{ + rt_uint32_t *src = NULL; + rt_uint32_t buf_32[64]; + rt_uint32_t write_size; + rt_size_t remaining_size = size; + int ret = (int)size; + + rt_uint32_t page_size; + rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_page_size, &page_size); + rt_uint32_t offset_in_page = offset % page_size; + if (offset_in_page != 0) + { + rt_uint32_t write_size_in_page = page_size - offset_in_page; + rt_uint32_t write_page_size = MIN(write_size_in_page, size); + (void) rt_memcpy(buf_32, buf, write_page_size); + write_size = write_unaligned_page_data(offset, buf_32, write_page_size); + if (write_size < 0) + { + ret = -RT_ERROR; + goto write_quit; + } + + remaining_size -= write_page_size; + offset += write_page_size; + buf += write_page_size; + } + + while (remaining_size > 0) + { + write_size = MIN(remaining_size, sizeof(buf_32)); + rt_memcpy(buf_32, buf, write_size); + src = &buf_32[0]; + + FAL_ENTER_CRITICAL(); + hpm_stat_t status = rom_xpi_nor_program(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, src, + offset, write_size); + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + rt_kprintf("write failed, status=%d\n", status); + break; + } + + remaining_size -= write_size; + buf += write_size; + offset += write_size; + } + +write_quit: + return ret; +} + +/** + * @brief FAL erase function + * Erase specified FLASH region + * @param offset the start FLASH address to be erased + * @param size size of the region to be erased + * @ret RT_EOK Erase operation is successful + * @retval -RT_ERROR Erase operation failed + */ +FAL_RAMFUNC static int erase(long offset, rt_size_t size) +{ + rt_uint32_t aligned_size = (size + nor_flash0.blk_size - 1U) & ~(nor_flash0.blk_size - 1U); + hpm_stat_t status; + int ret = (int)size; + + rt_uint32_t block_size; + rt_uint32_t sector_size; + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_sector_size, §or_size); + (void) rom_xpi_nor_get_property(BOARD_APP_XPI_NOR_XPI_BASE, &s_flashcfg, xpi_nor_property_block_size, &block_size); + rt_uint32_t erase_unit; + while (aligned_size > 0) + { + FAL_ENTER_CRITICAL(); + if ((offset % block_size == 0) && (aligned_size >= block_size)) + { + erase_unit = block_size; + status = rom_xpi_nor_erase_block(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + else + { + erase_unit = sector_size; + status = rom_xpi_nor_erase_sector(BOARD_APP_XPI_NOR_XPI_BASE, xpi_xfer_channel_auto, &s_flashcfg, offset); + } + FAL_EXIT_CRITICAL(); + + if (status != status_success) + { + ret = -RT_ERROR; + break; + } + offset += erase_unit; + aligned_size -= erase_unit; + } + + return ret; +} +#endif /* RT_USING_FAL */ diff --git a/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960.c b/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960.c new file mode 100644 index 00000000000..bbb1b25beb4 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include "hpm_wm8960.h" + +#ifndef HPM_WM8960_MCLK_TOLERANCE +#define HPM_WM8960_MCLK_TOLERANCE (4U) +#endif + +/* wm8960 register default value */ +static const uint16_t wm8960_default_reg_val[WM8960_REG_NUM] = { + 0x0097, 0x0097, 0x0000, 0x0000, 0x0000, 0x0008, 0x0000, 0x000a, 0x01c0, 0x0000, 0x00ff, 0x00ff, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x007b, 0x0100, 0x0032, 0x0000, 0x00c3, 0x00c3, 0x01c0, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0100, 0x0050, 0x0050, 0x0050, 0x0050, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0040, 0x0000, 0x0000, 0x0050, 0x0050, 0x0000, 0x0002, 0x0037, 0x004d, 0x0080, 0x0008, 0x0031, 0x0026, 0x00e9, +}; + +/* store reg value */ +static uint16_t wm8960_reg_val[WM8960_REG_NUM]; + +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config) +{ + assert(control != NULL); + assert(config != NULL); + + hpm_stat_t stat = status_success; + + (void)memcpy(wm8960_reg_val, wm8960_default_reg_val, sizeof(wm8960_default_reg_val)); + + /* Reset */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RESET, 0x00)); + + /* Power on input modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0xFE)); + /* Power on output modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x1F8)); + /* Power on PGA and mixer */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + + /* ADC and DAC uses same clock */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_IFACE2, 0x40)); + + /* set data protocol */ + HPM_CHECK_RET(wm8960_set_protocol(control, config->bus)); + + /* set wm8960 as slave */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_MS_MASK, WM8960_IFACE1_MS_SET(0))); + + /* invert LRCLK */ + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_LRP_MASK, WM8960_IFACE1_LRP_SET(1))); + + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL1, 0xC0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ADDCTL4, 0x40)); + + /* ADC volume, 8dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, 0x1D3)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, 0x1D3)); + + /* Digital DAC volume, 0dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, 0x1E0)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, 0x1E0)); + + /* Headphone volume, LOUT1 and ROUT1, 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, 0x17F)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, 0x17F)); + + /* speaker volume 6dB */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, 0x1ff)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, 0x1ff)); + /* enable class D output */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xf7)); + + /* Unmute DAC. */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_DACCTL1, 0x0000)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + + HPM_CHECK_RET(wm8960_set_data_format(control, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width)); + + /* set data route */ + HPM_CHECK_RET(wm8960_set_data_route(control, config)); + + return status_success; +} + +hpm_stat_t wm8960_deinit(wm8960_control_t *control) +{ + hpm_stat_t stat = status_success; + + /* power off all modules */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER2, 0x00U)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x00U)); + + return status_success; +} + +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol) +{ + return wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_FORMAT_MASK, (uint16_t)protocol); +} + +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable) +{ + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCL_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_ADCR_MASK, + ((uint16_t)enable << WM8960_POWER1_ADCR_SHIFT))); + break; + case wm8960_module_dac: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACL_MASK, + ((uint16_t)enable << WM8960_POWER2_DACL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_DACR_MASK, + ((uint16_t)enable << WM8960_POWER2_DACR_SHIFT))); + break; + case wm8960_module_vref: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_VREF_MASK, + ((uint16_t)enable << WM8960_POWER1_VREF_SHIFT))); + break; + case wm8960_module_ana_in: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINL_MASK, + ((uint16_t)enable << WM8960_POWER1_AINL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_AINR_MASK, + ((uint16_t)enable << WM8960_POWER1_AINR_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_LMIC_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_RMIC_MASK, + ((uint16_t)enable << WM8960_POWER3_RMIC_SHIFT))); + break; + case wm8960_module_lineout: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_LOUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_LOUT1_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_ROUT1_MASK, + ((uint16_t)enable << WM8960_POWER2_ROUT1_SHIFT))); + break; + case wm8960_module_micbais: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER1, WM8960_POWER1_MICB_MASK, + ((uint16_t)enable << WM8960_POWER1_MICB_SHIFT))); + break; + case wm8960_module_speaker: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKL_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKL_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER2, WM8960_POWER2_SPKR_MASK, + ((uint16_t)enable << WM8960_POWER2_SPKR_SHIFT))); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_CLASSD1, 0xF7)); + break; + case wm8960_module_output_mixer: + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_LOMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_LOMIX_SHIFT))); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_POWER3, WM8960_POWER3_ROMIX_MASK, + ((uint16_t)enable << WM8960_POWER3_ROMIX_SHIFT))); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config) +{ + hpm_stat_t stat = status_success; + + /* select left input */ + HPM_CHECK_RET(wm8960_set_left_input(control, config->left_input)); + /* select right input */ + HPM_CHECK_RET(wm8960_set_right_input(control, config->right_input)); + /* select source to output mixer */ + HPM_CHECK_RET(wm8960_config_input_to_output_mixer(control, config->play_source)); + + switch (config->route) { + case wm8960_route_bypass: + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback: + /* I2S_IN-> DAC-> HP */ + /* Set power for DAC */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x0C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_playback_and_record: + /* Set power */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x3C)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_dac, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_output_mixer, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_lineout, true)); + break; + case wm8960_route_record: + /* ANA_IN->ADC->I2S_OUT */ + /* Power up ADC and AIN */ + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER3, 0x30)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_micbais, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_ana_in, true)); + HPM_CHECK_RET(wm8960_set_module(control, wm8960_module_adc, true)); + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINL_MASK | WM8960_POWER1_ADCL_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX1, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX1, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + + switch (input) { + case wm8960_input_closed: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val &= (uint16_t) ~(WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + break; + case wm8960_input_single_ended_mic: + /* Only LMN1 enabled, LMICBOOST to 13db, LMIC2B enabled */ + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x138)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x178)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_differential_mic_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK | WM8960_POWER1_MICB_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINPATH, 0x1B8)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, 0x117)); + break; + case wm8960_input_line_input2: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0xEU; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + case wm8960_input_line_input3: + HPM_CHECK_RET(wm8960_read_reg(WM8960_POWER1, &val)); + val |= (WM8960_POWER1_AINR_MASK | WM8960_POWER1_ADCR_MASK); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_POWER1, val)); + HPM_CHECK_RET(wm8960_read_reg(WM8960_INBMIX2, &val)); + val |= 0x70U; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_INBMIX2, val)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume) +{ + uint16_t vol = 0; + hpm_stat_t stat = status_success; + switch (module) { + case wm8960_module_adc: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + /* Update volume */ + vol = (uint16_t)(0x100U | volume); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LADC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RADC, vol)); + } + break; + case wm8960_module_dac: + if (volume > 255U) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LDAC, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RDAC, vol)); + } + break; + case wm8960_module_headphone: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT1, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT1, vol)); + } + break; + case wm8960_module_ana_in: + if (volume > 0x3FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LINVOL, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_RINVOL, vol)); + } + break; + case wm8960_module_speaker: + if (volume > 0x7FU) { + stat = status_invalid_argument; + } else { + vol = (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + vol = 0x100U | (uint16_t)volume; + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_LOUT2, vol)); + HPM_CHECK_RET(wm8960_write_reg(control, WM8960_ROUT2, vol)); + } + break; + default: + stat = status_invalid_argument; + break; + } + return stat; +} + +static bool wm8960_check_clock_tolerance(uint32_t source, uint32_t target) +{ + uint32_t delta = (source >= target) ? (source - target) : (target - source); + if (delta * 100 <= HPM_WM8960_MCLK_TOLERANCE * target) { + return true; + } + return false; +} + +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits) +{ + hpm_stat_t stat = status_success; + uint16_t val = 0; + uint32_t ratio[7] = {256, 256 * 1.5, 256 * 2, 256 * 3, 256 * 4, 256 * 5.5, 256 * 6}; + bool clock_meet_requirement = false; + + if (sysclk / sample_rate > 256 * 6) { + sysclk = sysclk / 2; + val = WM8960_CLOCK1_SYSCLKDIV_SET(2U); /* SYSCLK Pre-divider */ + } + + for (uint8_t i = 0; i < 7; i++) { + if (wm8960_check_clock_tolerance(sysclk, sample_rate * ratio[i])) { + val |= ((i << WM8960_CLOCK1_ADCDIV_SHIFT) | (i << WM8960_CLOCK1_DACDIV_SHIFT)); + clock_meet_requirement = true; + break; + } + } + + if (!clock_meet_requirement) { + return status_invalid_argument; + } + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_CLOCK1, 0x1FEU, val)); + + /* set sample bit */ + switch (bits) { + case 16: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(0U)); + break; + case 20: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(1U)); + break; + case 24: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(2U)); + break; + case 32: + stat = wm8960_modify_reg(control, WM8960_IFACE1, WM8960_IFACE1_WL_MASK, WM8960_IFACE1_WL_SET(3U)); + break; + default: + stat = status_invalid_argument; + break; + } + + return stat; +} + +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source) +{ + hpm_stat_t stat = status_success; + + if ((play_source & (uint32_t)wm8960_play_source_input_mixer) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_dac) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x00U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x100U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x100U)); + } + + if ((play_source & (uint32_t)wm8960_play_source_input3) != 0U) { + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS1, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_BYPASS2, 0x80U, 0x0U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_LOUTMIX, 0x180U, 0x80U)); + HPM_CHECK_RET(wm8960_modify_reg(control, WM8960_ROUTMIX, 0x180U, 0x80U)); + } + + return stat; +} + + +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val) +{ + /* The first 7 bits (B15 to B9) are address bits that select which control register */ + /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ + rt_size_t size; + rt_uint8_t data[2]; + data[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); + data[1] = (uint8_t)(val & 0xFFU); + + size = rt_i2c_master_send(control->i2c_bus, control->slave_address, RT_I2C_WR, data, 2U); + if (size != 2) { + return status_fail; + } + + wm8960_reg_val[reg] = val; + return status_success; +} + +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val) +{ + if (reg >= WM8960_REG_NUM) { + return status_invalid_argument; + } + *val = wm8960_reg_val[reg]; + + return status_success; +} + +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val) +{ + hpm_stat_t stat = 0; + uint16_t reg_val; + + /* Read the register value out */ + stat = wm8960_read_reg(reg, ®_val); + if (stat != status_success) { + return status_fail; + } + + /* Modify the value */ + reg_val &= (uint16_t)~mask; + reg_val |= val; + + /* Write the data to register */ + stat = wm8960_write_reg(control, reg, reg_val); + if (stat != status_success) { + return status_fail; + } + + return status_success; +} diff --git a/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960.h b/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960.h new file mode 100644 index 00000000000..a163a52390a --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_H_ +#define _HPM_WM8960_H_ + +//#include "hpm_i2c_drv.h" +//#include "hpm_common.h" +#include +#include +#include "rtt_board.h" +#include "drivers/dev_i2c.h" +#include "hpm_wm8960_regs.h" + +#define WM8960_I2C_ADDR 0x1A + +typedef enum wm8960_module { + wm8960_module_adc = 0, /* ADC module in WM8960 */ + wm8960_module_dac = 1, /* DAC module in WM8960 */ + wm8960_module_vref = 2, /* VREF module */ + wm8960_module_headphone = 3, /* Headphone */ + wm8960_module_micbais = 4, /* Mic bias */ + wm8960_module_ana_in = 6, /* Analog in PGA */ + wm8960_module_lineout = 7, /* Line out module */ + wm8960_module_speaker = 8, /* Speaker module */ + wm8960_module_output_mixer = 9, /* Output mixer */ +} wm8960_module_t; + +/* wm8960 play source for output mixer */ +typedef enum wm8960_play_source { + wm8960_play_source_input_mixer = 1, /* Input Boost Mixer to Output Mixer */ + wm8960_play_source_input3 = 2, /* L/RINPUT3 to Output Mixer */ + wm8960_play_source_dac = 4, /* DAC to Output Mixer */ +} wm8960_play_source_t; + +/* WM8960 data route */ +typedef enum wm8960_route { + wm8960_route_bypass = 0, /* ANA_IN->Headphone. */ + wm8960_route_playback = 1, /* I2SIN->DAC->Headphone. */ + wm8960_route_playback_and_record = 2, /* I2SIN->DAC->Headphone, ANA_IN->ADC->I2SOUT. */ + wm8960_route_record = 5 /* ANA_IN->ADC->I2SOUT. */ +} wm8960_route_t; + +/* The audio data transfer protocol choice */ +typedef enum wm8960_protocol { + wm8960_bus_i2s = 2, /* I2S type */ + wm8960_bus_left_justified = 1, /* Left justified mode */ + wm8960_bus_right_justified = 0, /* Right justified mode */ + wm8960_bus_pcma = 3, /* PCM A mode */ + wm8960_bus_pcmb = 3 | (1 << 4) /* PCM B mode */ +} wm8960_protocol_t; + +/* wm8960 input source */ +typedef enum wm8960_input { + wm8960_input_closed = 0, /* Input device is closed */ + wm8960_input_single_ended_mic = 1, /* Input as single ended mic, only use L/RINPUT1 */ + wm8960_input_differential_mic_input2 = 2, /* Input as differential mic, use L/RINPUT1 and L/RINPUT2 */ + wm8960_input_differential_mic_input3 = 3, /* Input as differential mic, use L/RINPUT1 and L/RINPUT3*/ + wm8960_input_line_input2 = 4, /* Input as line input, only use L/RINPUT2 */ + wm8960_input_line_input3 = 5 /* Input as line input, only use L/RINPUT3 */ +} wm8960_input_t; + +/* wm8960 audio format */ +typedef struct wm8960_audio_format { + uint32_t mclk_hz; /* master clock frequency */ + uint32_t sample_rate; /* sample rate */ + uint32_t bit_width; /* bit width */ +} wm8960_audio_format_t; + +/* configure structure of WM8960 */ +typedef struct wm8960_config { + wm8960_route_t route; /* Audio data route.*/ + wm8960_protocol_t bus; /* Audio transfer protocol */ + bool enable_speaker; /* True means enable class D speaker as output, false means no */ + wm8960_input_t left_input; /* Left input source for WM8960 */ + wm8960_input_t right_input; /* Right input source for wm8960 */ + wm8960_play_source_t play_source; /* play source */ + wm8960_audio_format_t format; /* Audio format */ +} wm8960_config_t; + +typedef struct { + struct rt_i2c_bus_device *i2c_bus; /* I2C bus device */ + uint8_t slave_address; /* code device address */ +} wm8960_control_t; + + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * @brief WM8960 initialize function. + * + * @param control WM8960 control structure. + * @param config WM8960 configuration structure. + */ +hpm_stat_t wm8960_init(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Deinit the WM8960 codec. + * + * This function close all modules in WM8960 to save power. + * + * @param control WM8960 control structure pointer. + */ +hpm_stat_t wm8960_deinit(wm8960_control_t *control); + +/** + * @brief Set audio data route in WM8960. + * + * This function would set the data route according to route. + * + * @param control WM8960 control structure. + * @param config Audio configure structure in WM8960. + */ +hpm_stat_t wm8960_set_data_route(wm8960_control_t *control, wm8960_config_t *config); + +/** + * @brief Set left audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_left_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set right audio input source in WM8960. + * + * @param control WM8960 control structure. + * @param input Audio input source. + */ +hpm_stat_t wm8960_set_right_input(wm8960_control_t *control, wm8960_input_t input); + +/** + * @brief Set the audio transfer protocol. + * + * @param control WM8960 control structure. + * @param protocol Audio data transfer protocol. + */ +hpm_stat_t wm8960_set_protocol(wm8960_control_t *control, wm8960_protocol_t protocol); + +/** + * @brief Set the volume of different modules in WM8960. + * + * This function would set the volume of WM8960 modules. Uses need to appoint the module. + * The function assume that left channel and right channel has the same volume. + * + * Module:wm8960_module_adc, volume range value: 0 is mute, 1-255 is -97db to 30db + * Module:wm8960_module_dac, volume range value: 0 is mute, 1-255 is -127db to 0db + * Module:wm8960_module_headphone, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * Module:wm8960_module_ana_in, volume range value: 0 - 0x3F is -17.25db to 30db + * Module:wm8960_module_speaker, volume range value: 0 - 2F is mute, 0x30 - 0x7F is -73db to 6db + * + * + * @param control WM8960 control structure. + * @param module Module to set volume, it can be ADC, DAC, Headphone and so on. + * @param volume Volume value need to be set. + */ +hpm_stat_t wm8960_set_volume(wm8960_control_t *control, wm8960_module_t module, uint32_t volume); + +/** + * @brief Enable/disable expected module. + * + * @param control WM8960 control structure. + * @param module Module expected to enable. + * @param enable Enable or disable moudles. + */ +hpm_stat_t wm8960_set_module(wm8960_control_t *control, wm8960_module_t module, bool enable); + +/** + * @brief SET the WM8960 play source. + * + * @param control WM8960 control structure. + * @param play_source play source + * + * @return kStatus_WM8904_Success if successful, different code otherwise.. + */ +hpm_stat_t wm8960_config_input_to_output_mixer(wm8960_control_t *control, uint32_t play_source); + +/** + * @brief Configure the data format of audio data. + * + * This function would configure the registers about the sample rate, bit depths. + * + * @param control WM8960 control structure pointer. + * @param sysclk system clock of the codec which can be generated by MCLK or PLL output. + * @param sample_rate Sample rate of audio file running in WM8960. WM8960 now + * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. + * @param bits Bit depth of audio file (WM8960 only supports 16bit, 20bit, 24bit + * and 32 bit in HW). + */ +hpm_stat_t wm8960_set_data_format(wm8960_control_t *control, uint32_t sysclk, uint32_t sample_rate, uint32_t bits); + + +/** + * @brief Write register to WM8960 using I2C. + * + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_write_reg(wm8960_control_t *control, uint8_t reg, uint16_t val); + +/** + * @brief Read register from WM8960 using I2C. + * @param reg The register address in WM8960. + * @param val Value written to. + */ +hpm_stat_t wm8960_read_reg(uint8_t reg, uint16_t *val); + +/** + * @brief Modify some bits in the register using I2C. + * @param control WM8960 control structure. + * @param reg The register address in WM8960. + * @param mask The mask code for the bits want to write. The bit you want to write should be 0. + * @param val Value needs to write into the register. + */ +hpm_stat_t wm8960_modify_reg(wm8960_control_t *control, uint8_t reg, uint16_t mask, uint16_t val); + + +#endif /* _HPM_WM8960_H_ */ diff --git a/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960_regs.h b/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960_regs.h new file mode 100644 index 00000000000..a484f2937c1 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/hpm_wm8960_regs.h @@ -0,0 +1,2139 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _HPM_WM8960_REG_H_ +#define _HPM_WM8960_REG_H_ + +/* WM8960 register number */ +#define WM8960_REG_NUM 56U + +/* Define the register address of WM8960 */ +#define WM8960_LINVOL 0x0U /* Left Input Volume */ +#define WM8960_RINVOL 0x1U /* Right Input Volume */ +#define WM8960_LOUT1 0x2U /* LOUT1 Volume */ +#define WM8960_ROUT1 0x3U /* ROUT1 Volume */ +#define WM8960_CLOCK1 0x4U /* Clocking(1) */ +#define WM8960_DACCTL1 0x5U /* ADC and DAC Control (1) */ +#define WM8960_DACCTL2 0x6U /* ADC and DAC Control (2) */ +#define WM8960_IFACE1 0x7U /* Audio Interface */ +#define WM8960_CLOCK2 0x8U /* Clocking(2) */ +#define WM8960_IFACE2 0x9U /* Audio Interface */ +#define WM8960_LDAC 0xaU /* Left DAC */ +#define WM8960_RDAC 0xbU /* Right DAC Volume */ +#define WM8960_RESET 0xfU /* RESET */ +#define WM8960_3D 0x10U /* 3D Control */ +#define WM8960_ALC1 0x11U /* ALC (1) */ +#define WM8960_ALC2 0x12U /* ALC (2) */ +#define WM8960_ALC3 0x13U /* ALC (3) */ +#define WM8960_NOISEG 0x14U /* Noise Gate */ +#define WM8960_LADC 0x15U /* Left ADC Volume */ +#define WM8960_RADC 0x16U /* Right ADC Volume */ +#define WM8960_ADDCTL1 0x17U /* Additional Control (1) */ +#define WM8960_ADDCTL2 0x18U /* Additional Control (2) */ +#define WM8960_POWER1 0x19U /* Power Mgmt (1) */ +#define WM8960_POWER2 0x1aU /* Power Mgmt (2) */ +#define WM8960_ADDCTL3 0x1bU /* Additional Control (3) */ +#define WM8960_APOP1 0x1cU /* Anti-Pop 1 */ +#define WM8960_APOP2 0x1dU /* Anti-pop 2 */ +#define WM8960_LINPATH 0x20U /* ADCL Signal Path */ +#define WM8960_RINPATH 0x21U /* ADCR Signal Path */ +#define WM8960_LOUTMIX 0x22U /* Left Out Mix */ +#define WM8960_ROUTMIX 0x25U /* Right Out Mix */ +#define WM8960_MONOMIX1 0x26U /* Mono Out Mix (1) */ +#define WM8960_MONOMIX2 0x27U /* Mono Out Mix (2) */ +#define WM8960_LOUT2 0x28U /* Left Speaker Volume */ +#define WM8960_ROUT2 0x29U /* Right Speaker Volume */ +#define WM8960_MONO 0x2aU /* OUT3 Volume */ +#define WM8960_INBMIX1 0x2bU /* Left Input Boost Mixer */ +#define WM8960_INBMIX2 0x2cU /* Right Input Boost Mixer */ +#define WM8960_BYPASS1 0x2dU /* Left Bypass */ +#define WM8960_BYPASS2 0x2eU /* Right Bypass */ +#define WM8960_POWER3 0x2fU /* Power Mgmt (3) */ +#define WM8960_ADDCTL4 0x30U /* Additional Control (4) */ +#define WM8960_CLASSD1 0x31U /* Class D Control (1) */ +#define WM8960_CLASSD3 0x33U /* Class D Control (2) */ +#define WM8960_PLL1 0x34U /* PLL (1) */ +#define WM8960_PLL2 0x35U /* PLL (2) */ +#define WM8960_PLL3 0x36U /* PLL (3) */ +#define WM8960_PLL4 0x37U /* PLL (4) */ + +/* Bitfield definition for register: LINVO */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_LINVO_IPVU_MASK (0x100U) +#define WM8960_LINVO_IPVU_SHIFT (8U) +#define WM8960_LINVO_IPVU_SET(x) (((uint16_t)(x) << WM8960_LINVO_IPVU_SHIFT) & WM8960_LINVO_IPVU_MASK) +#define WM8960_LINVO_IPVU_GET(x) (((uint16_t)(x) & WM8960_LINVO_IPVU_MASK) >> WM8960_LINVO_IPVU_SHIFT) + +/* + * LINMUTE (RW) + * + * Left Input PGA Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: IPVU must be set to un-mute. + */ +#define WM8960_LINVO_LINMUTE_MASK (0x80U) +#define WM8960_LINVO_LINMUTE_SHIFT (7U) +#define WM8960_LINVO_LINMUTE_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINMUTE_SHIFT) & WM8960_LINVO_LINMUTE_MASK) +#define WM8960_LINVO_LINMUTE_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINMUTE_MASK) >> WM8960_LINVO_LINMUTE_SHIFT) + +/* + * LIZC (RW) + * + * Left Input PGA Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately + */ +#define WM8960_LINVO_LIZC_MASK (0x40U) +#define WM8960_LINVO_LIZC_SHIFT (6U) +#define WM8960_LINVO_LIZC_SET(x) (((uint16_t)(x) << WM8960_LINVO_LIZC_SHIFT) & WM8960_LINVO_LIZC_MASK) +#define WM8960_LINVO_LIZC_GET(x) (((uint16_t)(x) & WM8960_LINVO_LIZC_MASK) >> WM8960_LINVO_LIZC_SHIFT) + +/* + * LINVOL (RW) + * + * Left Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_LINVO_LINVOL_MASK (0x3FU) +#define WM8960_LINVO_LINVOL_SHIFT (0U) +#define WM8960_LINVO_LINVOL_SET(x) (((uint16_t)(x) << WM8960_LINVO_LINVOL_SHIFT) & WM8960_LINVO_LINVOL_MASK) +#define WM8960_LINVO_LINVOL_GET(x) (((uint16_t)(x) & WM8960_LINVO_LINVOL_MASK) >> WM8960_LINVO_LINVOL_SHIFT) + +/* Bitfield definition for register: RINVOL */ +/* + * IPVU (RW) + * + * Input PGA Volume Update + * Writing a 1 to this bit will cause left and right + * input PGA volumes to be updated (LINVOL and RINVOL) + */ +#define WM8960_RINVOL_IPVU_MASK (0x100U) +#define WM8960_RINVOL_IPVU_SHIFT (8U) +#define WM8960_RINVOL_IPVU_SET(x) (((uint16_t)(x) << WM8960_RINVOL_IPVU_SHIFT) & WM8960_RINVOL_IPVU_MASK) +#define WM8960_RINVOL_IPVU_GET(x) (((uint16_t)(x) & WM8960_RINVOL_IPVU_MASK) >> WM8960_RINVOL_IPVU_SHIFT) + +/* + * RINMUTE (RW) + * + * Right Input PGA Analogue Mute + * 1 = Enable Mute + * 0 = Disable Mute + * Note: IPVU must be set to un-mute. + */ +#define WM8960_RINVOL_RINMUTE_MASK (0x80U) +#define WM8960_RINVOL_RINMUTE_SHIFT (7U) +#define WM8960_RINVOL_RINMUTE_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINMUTE_SHIFT) & WM8960_RINVOL_RINMUTE_MASK) +#define WM8960_RINVOL_RINMUTE_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINMUTE_MASK) >> WM8960_RINVOL_RINMUTE_SHIFT) + +/* + * RIZC (RW) + * + * Right Input PGA Zero Cross Detector + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_RINVOL_RIZC_MASK (0x40U) +#define WM8960_RINVOL_RIZC_SHIFT (6U) +#define WM8960_RINVOL_RIZC_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RIZC_SHIFT) & WM8960_RINVOL_RIZC_MASK) +#define WM8960_RINVOL_RIZC_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RIZC_MASK) >> WM8960_RINVOL_RIZC_SHIFT) + +/* + * RINVOL (RW) + * + * Right Input PGA Volume Control + * 111111 = +30dB + * 111110 = +29.25dB + * . . 0.75dB steps down to + * 000000 = -17.25dB + */ +#define WM8960_RINVOL_RINVOL_MASK (0x3FU) +#define WM8960_RINVOL_RINVOL_SHIFT (0U) +#define WM8960_RINVOL_RINVOL_SET(x) (((uint16_t)(x) << WM8960_RINVOL_RINVOL_SHIFT) & WM8960_RINVOL_RINVOL_MASK) +#define WM8960_RINVOL_RINVOL_GET(x) (((uint16_t)(x) & WM8960_RINVOL_RINVOL_MASK) >> WM8960_RINVOL_RINVOL_SHIFT) + +/* Bitfield definition for register: LOUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_LOUT1_OUT1VU_MASK (0x100U) +#define WM8960_LOUT1_OUT1VU_SHIFT (8U) +#define WM8960_LOUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_LOUT1_OUT1VU_SHIFT) & WM8960_LOUT1_OUT1VU_MASK) +#define WM8960_LOUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_LOUT1_OUT1VU_MASK) >> WM8960_LOUT1_OUT1VU_SHIFT) + +/* + * LO1ZC (RW) + * + * Left Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_LOUT1_LO1ZC_MASK (0x80U) +#define WM8960_LOUT1_LO1ZC_SHIFT (7U) +#define WM8960_LOUT1_LO1ZC_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LO1ZC_SHIFT) & WM8960_LOUT1_LO1ZC_MASK) +#define WM8960_LOUT1_LO1ZC_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LO1ZC_MASK) >> WM8960_LOUT1_LO1ZC_SHIFT) + +/* + * LOUT1VOL (RW) + * + * LOUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT1_LOUT1VOL_MASK (0x7FU) +#define WM8960_LOUT1_LOUT1VOL_SHIFT (0U) +#define WM8960_LOUT1_LOUT1VOL_SET(x) (((uint16_t)(x) << WM8960_LOUT1_LOUT1VOL_SHIFT) & WM8960_LOUT1_LOUT1VOL_MASK) +#define WM8960_LOUT1_LOUT1VOL_GET(x) (((uint16_t)(x) & WM8960_LOUT1_LOUT1VOL_MASK) >> WM8960_LOUT1_LOUT1VOL_SHIFT) + +/* Bitfield definition for register: ROUT1 */ +/* + * OUT1VU (RW) + * + * Headphone Output PGA Volume Update + * Writing a 1 to this bit will cause left and right + * headphone output volumes to be updated + * (LOUT1VOL and ROUT1VOL) + */ +#define WM8960_ROUT1_OUT1VU_MASK (0x100U) +#define WM8960_ROUT1_OUT1VU_SHIFT (8U) +#define WM8960_ROUT1_OUT1VU_SET(x) (((uint16_t)(x) << WM8960_ROUT1_OUT1VU_SHIFT) & WM8960_ROUT1_OUT1VU_MASK) +#define WM8960_ROUT1_OUT1VU_GET(x) (((uint16_t)(x) & WM8960_ROUT1_OUT1VU_MASK) >> WM8960_ROUT1_OUT1VU_SHIFT) + +/* + * RO1ZC (RW) + * + * Right Headphone Output Zero Cross Enable + * 0 = Change gain immediately + * 1 = Change gain on zero cross only + */ +#define WM8960_ROUT1_RO1ZC_MASK (0x80U) +#define WM8960_ROUT1_RO1ZC_SHIFT (7U) +#define WM8960_ROUT1_RO1ZC_SET(x) (((uint16_t)(x) << WM8960_ROUT1_RO1ZC_SHIFT) & WM8960_ROUT1_RO1ZC_MASK) +#define WM8960_ROUT1_RO1ZC_GET(x) (((uint16_t)(x) & WM8960_ROUT1_RO1ZC_MASK) >> WM8960_ROUT1_RO1ZC_SHIFT) + +/* + * ROUT1VOL (RW) + * + * ROUT1 Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT1_ROUT1VOL_MASK (0x7FU) +#define WM8960_ROUT1_ROUT1VOL_SHIFT (0U) +#define WM8960_ROUT1_ROUT1VOL_SET(x) (((uint16_t)(x) << WM8960_ROUT1_ROUT1VOL_SHIFT) & WM8960_ROUT1_ROUT1VOL_MASK) +#define WM8960_ROUT1_ROUT1VOL_GET(x) (((uint16_t)(x) & WM8960_ROUT1_ROUT1VOL_MASK) >> WM8960_ROUT1_ROUT1VOL_SHIFT) + +/* Bitfield definition for register: CLOCK1 */ +/* + * ADCDIV (RW) + * + * ADC Sample rate divider (Also determines + * ADCLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_ADCDIV_MASK (0x1C0U) +#define WM8960_CLOCK1_ADCDIV_SHIFT (6U) +#define WM8960_CLOCK1_ADCDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_ADCDIV_SHIFT) & WM8960_CLOCK1_ADCDIV_MASK) +#define WM8960_CLOCK1_ADCDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_ADCDIV_MASK) >> WM8960_CLOCK1_ADCDIV_SHIFT) + +/* + * DACDIV (RW) + * + * DAC Sample rate divider (Also determines + * DACLRC in master mode) + * 000 = SYSCLK / (1.0 * 256) + * 001 = SYSCLK / (1.5 * 256) + * 010 = SYSCLK / (2 * 256) + * 011 = SYSCLK / (3 * 256) + * 100 = SYSCLK / (4 * 256) + * 101 = SYSCLK / (5.5 * 256) + * 110 = SYSCLK / (6 * 256) + * 111 = Reserved + */ +#define WM8960_CLOCK1_DACDIV_MASK (0x38U) +#define WM8960_CLOCK1_DACDIV_SHIFT (3U) +#define WM8960_CLOCK1_DACDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_DACDIV_SHIFT) & WM8960_CLOCK1_DACDIV_MASK) +#define WM8960_CLOCK1_DACDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_DACDIV_MASK) >> WM8960_CLOCK1_DACDIV_SHIFT) + +/* + * SYSCLKDIV (RW) + * + * SYSCLK Pre-divider. Clock source (MCLK or + * PLL output) will be divided by this value to + * generate SYSCLK. + * 00 = Divide SYSCLK by 1 + * 01 = Reserved + * 10 = Divide SYSCLK by 2 + * 11 = Reserved + */ +#define WM8960_CLOCK1_SYSCLKDIV_MASK (0x6U) +#define WM8960_CLOCK1_SYSCLKDIV_SHIFT (1U) +#define WM8960_CLOCK1_SYSCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_SYSCLKDIV_SHIFT) & WM8960_CLOCK1_SYSCLKDIV_MASK) +#define WM8960_CLOCK1_SYSCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_SYSCLKDIV_MASK) >> WM8960_CLOCK1_SYSCLKDIV_SHIFT) + +/* + * CLKSEL (RW) + * + * SYSCLK Selection + * 0 = SYSCLK derived from MCLK + * 1 = SYSCLK derived from PLL output + */ +#define WM8960_CLOCK1_CLKSEL_MASK (0x1U) +#define WM8960_CLOCK1_CLKSEL_SHIFT (0U) +#define WM8960_CLOCK1_CLKSEL_SET(x) (((uint16_t)(x) << WM8960_CLOCK1_CLKSEL_SHIFT) & WM8960_CLOCK1_CLKSEL_MASK) +#define WM8960_CLOCK1_CLKSEL_GET(x) (((uint16_t)(x) & WM8960_CLOCK1_CLKSEL_MASK) >> WM8960_CLOCK1_CLKSEL_SHIFT) + +/* Bitfield definition for register: DACCTL1 */ +/* + * DACDIV2 (RW) + * + * DAC 6dB Attenuate Enable + * 0 = Disabled (0dB) + * 1 = -6dB Enabled + */ +#define WM8960_DACCTL1_DACDIV2_MASK (0x80U) +#define WM8960_DACCTL1_DACDIV2_SHIFT (7U) +#define WM8960_DACCTL1_DACDIV2_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACDIV2_SHIFT) & WM8960_DACCTL1_DACDIV2_MASK) +#define WM8960_DACCTL1_DACDIV2_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACDIV2_MASK) >> WM8960_DACCTL1_DACDIV2_SHIFT) + +/* + * ADCPOL (RW) + * + * ADC polarity control: + * 00 = Polarity not inverted + * 01 = ADC L inverted + * 10 = ADC R inverted + * 11 = ADC L and R inverted + */ +#define WM8960_DACCTL1_ADCPOL_MASK (0x60U) +#define WM8960_DACCTL1_ADCPOL_SHIFT (5U) +#define WM8960_DACCTL1_ADCPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCPOL_SHIFT) & WM8960_DACCTL1_ADCPOL_MASK) +#define WM8960_DACCTL1_ADCPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCPOL_MASK) >> WM8960_DACCTL1_ADCPOL_SHIFT) + +/* + * DACMU (RW) + * + * DAC Digital Soft Mute + * 1 = Mute + * 0 = No mute (signal active) + */ +#define WM8960_DACCTL1_DACMU_MASK (0x8U) +#define WM8960_DACCTL1_DACMU_SHIFT (3U) +#define WM8960_DACCTL1_DACMU_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DACMU_SHIFT) & WM8960_DACCTL1_DACMU_MASK) +#define WM8960_DACCTL1_DACMU_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DACMU_MASK) >> WM8960_DACCTL1_DACMU_SHIFT) + +/* + * DEEMPH (RW) + * + * De-emphasis Control + * 11 = 48kHz sample rate + * 10 = 44.1kHz sample rate + * 01 = 32kHz sample rate + * 00 = No de-emphasis + */ +#define WM8960_DACCTL1_DEEMPH_MASK (0x6U) +#define WM8960_DACCTL1_DEEMPH_SHIFT (1U) +#define WM8960_DACCTL1_DEEMPH_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_DEEMPH_SHIFT) & WM8960_DACCTL1_DEEMPH_MASK) +#define WM8960_DACCTL1_DEEMPH_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_DEEMPH_MASK) >> WM8960_DACCTL1_DEEMPH_SHIFT) + +/* + * ADCHPD (RW) + * + * ADC High Pass Filter Disable + * 0 = Enable high pass filter on left and right channels + * 1 = Disable high pass filter on left and right channels + */ +#define WM8960_DACCTL1_ADCHPD_MASK (0x1U) +#define WM8960_DACCTL1_ADCHPD_SHIFT (0U) +#define WM8960_DACCTL1_ADCHPD_SET(x) (((uint16_t)(x) << WM8960_DACCTL1_ADCHPD_SHIFT) & WM8960_DACCTL1_ADCHPD_MASK) +#define WM8960_DACCTL1_ADCHPD_GET(x) (((uint16_t)(x) & WM8960_DACCTL1_ADCHPD_MASK) >> WM8960_DACCTL1_ADCHPD_SHIFT) + +/* Bitfield definition for register: DACCTL2 */ +/* + * DACPOL (RW) + * + * DAC polarity control: + * 00 = Polarity not inverted + * 01 = DAC L inverted + * 10 = DAC R inverted + * 11 = DAC L and R inverted + */ +#define WM8960_DACCTL2_DACPOL_MASK (0x60U) +#define WM8960_DACCTL2_DACPOL_SHIFT (5U) +#define WM8960_DACCTL2_DACPOL_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACPOL_SHIFT) & WM8960_DACCTL2_DACPOL_MASK) +#define WM8960_DACCTL2_DACPOL_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACPOL_MASK) >> WM8960_DACCTL2_DACPOL_SHIFT) + +/* + * DACSMM (RW) + * + * DAC Soft Mute Mode + * 0 = Disabling soft-mute (DACMU=0) will cause + * the volume to change immediately to the + * LDACVOL / RDACVOL settings + * 1 = Disabling soft-mute (DACMU=0) will cause + * the volume to ramp up gradually to the + * LDACVOL / RDACVOL settings + */ +#define WM8960_DACCTL2_DACSMM_MASK (0x8U) +#define WM8960_DACCTL2_DACSMM_SHIFT (3U) +#define WM8960_DACCTL2_DACSMM_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSMM_SHIFT) & WM8960_DACCTL2_DACSMM_MASK) +#define WM8960_DACCTL2_DACSMM_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSMM_MASK) >> WM8960_DACCTL2_DACSMM_SHIFT) + +/* + * DACMR (RW) + * + * DAC Soft Mute Ramp Rate + * 0 = Fast ramp (24kHz at fs=48k, providing + * maximum delay of 10.7ms) + * 1 = Slow ramp (1.5kHz at fs=48k, providing + * maximum delay of 171ms) + */ +#define WM8960_DACCTL2_DACMR_MASK (0x4U) +#define WM8960_DACCTL2_DACMR_SHIFT (2U) +#define WM8960_DACCTL2_DACMR_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACMR_SHIFT) & WM8960_DACCTL2_DACMR_MASK) +#define WM8960_DACCTL2_DACMR_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACMR_MASK) >> WM8960_DACCTL2_DACMR_SHIFT) + +/* + * DACSLOPE (RW) + * + * Selects DAC filter characteristics + * 0 = Normal mode + * 1 = Sloping stopband + */ +#define WM8960_DACCTL2_DACSLOPE_MASK (0x2U) +#define WM8960_DACCTL2_DACSLOPE_SHIFT (1U) +#define WM8960_DACCTL2_DACSLOPE_SET(x) (((uint16_t)(x) << WM8960_DACCTL2_DACSLOPE_SHIFT) & WM8960_DACCTL2_DACSLOPE_MASK) +#define WM8960_DACCTL2_DACSLOPE_GET(x) (((uint16_t)(x) & WM8960_DACCTL2_DACSLOPE_MASK) >> WM8960_DACCTL2_DACSLOPE_SHIFT) + +/* Bitfield definition for register: IFACE1 */ +/* + * ALRSWAP (RW) + * + * Left/Right ADC Channel Swap + * 1 = Swap left and right ADC data in audio + * interface + * 0 = Output left and right data as normal + */ +#define WM8960_IFACE1_ALRSWAP_MASK (0x100U) +#define WM8960_IFACE1_ALRSWAP_SHIFT (8U) +#define WM8960_IFACE1_ALRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_ALRSWAP_SHIFT) & WM8960_IFACE1_ALRSWAP_MASK) +#define WM8960_IFACE1_ALRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_ALRSWAP_MASK) >> WM8960_IFACE1_ALRSWAP_SHIFT) + +/* + * BCLKINV (RW) + * + * BCLK invert bit (for master and slave modes) + * 0 = BCLK not inverted + * 1 = BCLK inverted + */ +#define WM8960_IFACE1_BCLKINV_MASK (0x80U) +#define WM8960_IFACE1_BCLKINV_SHIFT (7U) +#define WM8960_IFACE1_BCLKINV_SET(x) (((uint16_t)(x) << WM8960_IFACE1_BCLKINV_SHIFT) & WM8960_IFACE1_BCLKINV_MASK) +#define WM8960_IFACE1_BCLKINV_GET(x) (((uint16_t)(x) & WM8960_IFACE1_BCLKINV_MASK) >> WM8960_IFACE1_BCLKINV_SHIFT) + +/* + * MS (RW) + * + * Master / Slave Mode Control + * 0 = Enable slave mode + * 1 = Enable master mode + */ +#define WM8960_IFACE1_MS_MASK (0x40U) +#define WM8960_IFACE1_MS_SHIFT (6U) +#define WM8960_IFACE1_MS_SET(x) (((uint16_t)(x) << WM8960_IFACE1_MS_SHIFT) & WM8960_IFACE1_MS_MASK) +#define WM8960_IFACE1_MS_GET(x) (((uint16_t)(x) & WM8960_IFACE1_MS_MASK) >> WM8960_IFACE1_MS_SHIFT) + +/* + * DLRSWAP (RW) + * + * Left/Right DAC Channel Swap + * 0 = Output left and right data as normal + * 1 = Swap left and right DAC data in audio interface + */ +#define WM8960_IFACE1_DLRSWAP_MASK (0x20U) +#define WM8960_IFACE1_DLRSWAP_SHIFT (5U) +#define WM8960_IFACE1_DLRSWAP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_DLRSWAP_SHIFT) & WM8960_IFACE1_DLRSWAP_MASK) +#define WM8960_IFACE1_DLRSWAP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_DLRSWAP_MASK) >> WM8960_IFACE1_DLRSWAP_SHIFT) + +/* + * LRP (RW) + * + * Right, left and I2S modes – LRCLK polarity + * 0 = normal LRCLK polarity + * 1 = invert LRCLK polarity + * DSP Mode – mode A/B select + * 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) + * 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) + */ +#define WM8960_IFACE1_LRP_MASK (0x10U) +#define WM8960_IFACE1_LRP_SHIFT (4U) +#define WM8960_IFACE1_LRP_SET(x) (((uint16_t)(x) << WM8960_IFACE1_LRP_SHIFT) & WM8960_IFACE1_LRP_MASK) +#define WM8960_IFACE1_LRP_GET(x) (((uint16_t)(x) & WM8960_IFACE1_LRP_MASK) >> WM8960_IFACE1_LRP_SHIFT) + +/* + * WL (RW) + * + * Audio Data Word Length + * 00 = 16 bits + * 01 = 20 bits + * 10 = 24 bits + * 11 = 32 bits (see Note) + */ +#define WM8960_IFACE1_WL_MASK (0xCU) +#define WM8960_IFACE1_WL_SHIFT (2U) +#define WM8960_IFACE1_WL_SET(x) (((uint16_t)(x) << WM8960_IFACE1_WL_SHIFT) & WM8960_IFACE1_WL_MASK) +#define WM8960_IFACE1_WL_GET(x) (((uint16_t)(x) & WM8960_IFACE1_WL_MASK) >> WM8960_IFACE1_WL_SHIFT) + +/* + * FORMAT (RW) + * + * 00 = Right justified + * 01 = Left justified + * 10 = I2S Format + * 11 = DSP Mode + */ +#define WM8960_IFACE1_FORMAT_MASK (0x3U) +#define WM8960_IFACE1_FORMAT_SHIFT (0U) +#define WM8960_IFACE1_FORMAT_SET(x) (((uint16_t)(x) << WM8960_IFACE1_FORMAT_SHIFT) & WM8960_IFACE1_FORMAT_MASK) +#define WM8960_IFACE1_FORMAT_GET(x) (((uint16_t)(x) & WM8960_IFACE1_FORMAT_MASK) >> WM8960_IFACE1_FORMAT_SHIFT) + +/* Bitfield definition for register: CLOCK2 */ +/* + * DCLKDIV (RW) + * + * Class D switching clock divider. + * 000 = SYSCLK / 1.5 (Not recommended) + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 6 + * 101 = SYSCLK / 8 + * 110 = SYSCLK / 12 + * 111 = SYSCLK / 16 + */ +#define WM8960_CLOCK2_DCLKDIV_MASK (0x1C0U) +#define WM8960_CLOCK2_DCLKDIV_SHIFT (6U) +#define WM8960_CLOCK2_DCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_DCLKDIV_SHIFT) & WM8960_CLOCK2_DCLKDIV_MASK) +#define WM8960_CLOCK2_DCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_DCLKDIV_MASK) >> WM8960_CLOCK2_DCLKDIV_SHIFT) + +/* + * BCLKDIV (RW) + * + * BCLK Frequency (Master Mode) + * 0000 = SYSCLK + * 0001 = SYSCLK / 1.5 + * 0010 = SYSCLK / 2 + * 0011 = SYSCLK / 3 + * 0100 = SYSCLK / 4 + * 0101 = SYSCLK / 5.5 + * 0110 = SYSCLK / 6 + * 0111 = SYSCLK / 8 + * 1000 = SYSCLK / 11 + * 1001 = SYSCLK / 12 + * 1010 = SYSCLK / 16 + * 1011 = SYSCLK / 22 + * 1100 = SYSCLK / 24 + * 1101 to 1111 = SYSCLK / 32 + */ +#define WM8960_CLOCK2_BCLKDIV_MASK (0xFU) +#define WM8960_CLOCK2_BCLKDIV_SHIFT (0U) +#define WM8960_CLOCK2_BCLKDIV_SET(x) (((uint16_t)(x) << WM8960_CLOCK2_BCLKDIV_SHIFT) & WM8960_CLOCK2_BCLKDIV_MASK) +#define WM8960_CLOCK2_BCLKDIV_GET(x) (((uint16_t)(x) & WM8960_CLOCK2_BCLKDIV_MASK) >> WM8960_CLOCK2_BCLKDIV_SHIFT) + +/* Bitfield definition for register: IFACE2 */ +/* + * ALRCGPIO (RW) + * + * ADCLRC/GPIO1 Pin Function Select + * 0 = ADCLRC frame clock for ADC + * 1 = GPIO pin + */ +#define WM8960_IFACE2_ALRCGPIO_MASK (0x40U) +#define WM8960_IFACE2_ALRCGPIO_SHIFT (6U) +#define WM8960_IFACE2_ALRCGPIO_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ALRCGPIO_SHIFT) & WM8960_IFACE2_ALRCGPIO_MASK) +#define WM8960_IFACE2_ALRCGPIO_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ALRCGPIO_MASK) >> WM8960_IFACE2_ALRCGPIO_SHIFT) + +/* + * WL8 (RW) + * + * 8-Bit Word Length Select (Used with + * companding) + * 0 = Off + * 1 = Device operates in 8-bit mode. + */ +#define WM8960_IFACE2_WL8_MASK (0x20U) +#define WM8960_IFACE2_WL8_SHIFT (5U) +#define WM8960_IFACE2_WL8_SET(x) (((uint16_t)(x) << WM8960_IFACE2_WL8_SHIFT) & WM8960_IFACE2_WL8_MASK) +#define WM8960_IFACE2_WL8_GET(x) (((uint16_t)(x) & WM8960_IFACE2_WL8_MASK) >> WM8960_IFACE2_WL8_SHIFT) + +/* + * DACCOMP (RW) + * + * DAC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_DACCOMP_MASK (0x18U) +#define WM8960_IFACE2_DACCOMP_SHIFT (3U) +#define WM8960_IFACE2_DACCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_DACCOMP_SHIFT) & WM8960_IFACE2_DACCOMP_MASK) +#define WM8960_IFACE2_DACCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_DACCOMP_MASK) >> WM8960_IFACE2_DACCOMP_SHIFT) + +/* + * ADCCOMP (RW) + * + * ADC companding + * 00 = off + * 01 = reserved + * 10 = μ-law + * 11 = A-law + */ +#define WM8960_IFACE2_ADCCOMP_MASK (0x6U) +#define WM8960_IFACE2_ADCCOMP_SHIFT (1U) +#define WM8960_IFACE2_ADCCOMP_SET(x) (((uint16_t)(x) << WM8960_IFACE2_ADCCOMP_SHIFT) & WM8960_IFACE2_ADCCOMP_MASK) +#define WM8960_IFACE2_ADCCOMP_GET(x) (((uint16_t)(x) & WM8960_IFACE2_ADCCOMP_MASK) >> WM8960_IFACE2_ADCCOMP_SHIFT) + +/* + * LOOPBACK (RW) + * + * Digital Loopback Function + * 0 = No loopback. + * 1 = Loopback enabled, ADC data output is fed + * directly into DAC data input + */ +#define WM8960_IFACE2_LOOPBACK_MASK (0x1U) +#define WM8960_IFACE2_LOOPBACK_SHIFT (0U) +#define WM8960_IFACE2_LOOPBACK_SET(x) (((uint16_t)(x) << WM8960_IFACE2_LOOPBACK_SHIFT) & WM8960_IFACE2_LOOPBACK_MASK) +#define WM8960_IFACE2_LOOPBACK_GET(x) (((uint16_t)(x) & WM8960_IFACE2_LOOPBACK_MASK) >> WM8960_IFACE2_LOOPBACK_SHIFT) + +/* Bitfield definition for register: LDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_LDAC_DACVU_MASK (0x100U) +#define WM8960_LDAC_DACVU_SHIFT (8U) +#define WM8960_LDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_LDAC_DACVU_SHIFT) & WM8960_LDAC_DACVU_MASK) +#define WM8960_LDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_LDAC_DACVU_MASK) >> WM8960_LDAC_DACVU_SHIFT) + +/* + * LDACVOL (RW) + * + * Left DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_LDAC_LDACVOL_MASK (0xFFU) +#define WM8960_LDAC_LDACVOL_SHIFT (0U) +#define WM8960_LDAC_LDACVOL_SET(x) (((uint16_t)(x) << WM8960_LDAC_LDACVOL_SHIFT) & WM8960_LDAC_LDACVOL_MASK) +#define WM8960_LDAC_LDACVOL_GET(x) (((uint16_t)(x) & WM8960_LDAC_LDACVOL_MASK) >> WM8960_LDAC_LDACVOL_SHIFT) + +/* Bitfield definition for register: RDAC */ +/* + * DACVU (RW) + * + * DAC Volume Update + * Writing a 1 to this bit will cause left and right + * DAC volumes to be updated (LDACVOL and RDACVOL) + */ +#define WM8960_RDAC_DACVU_MASK (0x100U) +#define WM8960_RDAC_DACVU_SHIFT (8U) +#define WM8960_RDAC_DACVU_SET(x) (((uint16_t)(x) << WM8960_RDAC_DACVU_SHIFT) & WM8960_RDAC_DACVU_MASK) +#define WM8960_RDAC_DACVU_GET(x) (((uint16_t)(x) & WM8960_RDAC_DACVU_MASK) >> WM8960_RDAC_DACVU_SHIFT) + +/* + * RDACVOL (RW) + * + * Right DAC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -127dB + * 0000 0010 = -126.5dB + * ... 0.5dB steps up to + * 1111 1111 = 0dB + */ +#define WM8960_RDAC_RDACVOL_MASK (0xFFU) +#define WM8960_RDAC_RDACVOL_SHIFT (0U) +#define WM8960_RDAC_RDACVOL_SET(x) (((uint16_t)(x) << WM8960_RDAC_RDACVOL_SHIFT) & WM8960_RDAC_RDACVOL_MASK) +#define WM8960_RDAC_RDACVOL_GET(x) (((uint16_t)(x) & WM8960_RDAC_RDACVOL_MASK) >> WM8960_RDAC_RDACVOL_SHIFT) + +/* Bitfield definition for register: RESET */ +/* + * RESET (RW) + * + * Writing to this register resets all registers to their default state. + */ +#define WM8960_RESET_RESET_MASK (0x1FFU) +#define WM8960_RESET_RESET_SHIFT (0U) +#define WM8960_RESET_RESET_SET(x) (((uint16_t)(x) << WM8960_RESET_RESET_SHIFT) & WM8960_RESET_RESET_MASK) +#define WM8960_RESET_RESET_GET(x) (((uint16_t)(x) & WM8960_RESET_RESET_MASK) >> WM8960_RESET_RESET_SHIFT) + +/* Bitfield definition for register: 3D */ +/* + * 3DUC (RW) + * + * 3D Enhance Filter Upper Cut-Off Frequency + * 0 = High (Recommended for fs>=32kHz) + * 1 = Low (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DUC_MASK (0x40U) +#define WM8960_3D_3DUC_SHIFT (6U) +#define WM8960_3D_3DUC_SET(x) (((uint16_t)(x) << WM8960_3D_3DUC_SHIFT) & WM8960_3D_3DUC_MASK) +#define WM8960_3D_3DUC_GET(x) (((uint16_t)(x) & WM8960_3D_3DUC_MASK) >> WM8960_3D_3DUC_SHIFT) + +/* + * 3DLC (RW) + * + * 3D Enhance Filter Lower Cut-Off Frequency + * 0 = Low (Recommended for fs>=32kHz) + * 1 = High (Recommended for fs<32kHz) + */ +#define WM8960_3D_3DLC_MASK (0x20U) +#define WM8960_3D_3DLC_SHIFT (5U) +#define WM8960_3D_3DLC_SET(x) (((uint16_t)(x) << WM8960_3D_3DLC_SHIFT) & WM8960_3D_3DLC_MASK) +#define WM8960_3D_3DLC_GET(x) (((uint16_t)(x) & WM8960_3D_3DLC_MASK) >> WM8960_3D_3DLC_SHIFT) + +/* + * 3DDEPTH (RW) + * + * 3D Stereo Depth + * 0000 = 0% (minimum 3D effect) + * 0001 = 6.67% + * .... + * 1110 = 93.3% + * 1111 = 100% (maximum 3D effect) + */ +#define WM8960_3D_3DDEPTH_MASK (0x1EU) +#define WM8960_3D_3DDEPTH_SHIFT (1U) +#define WM8960_3D_3DDEPTH_SET(x) (((uint16_t)(x) << WM8960_3D_3DDEPTH_SHIFT) & WM8960_3D_3DDEPTH_MASK) +#define WM8960_3D_3DDEPTH_GET(x) (((uint16_t)(x) & WM8960_3D_3DDEPTH_MASK) >> WM8960_3D_3DDEPTH_SHIFT) + +/* + * 3DEN (RW) + * + * 3D Stereo Enhancement Enable + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_3D_3DEN_MASK (0x1U) +#define WM8960_3D_3DEN_SHIFT (0U) +#define WM8960_3D_3DEN_SET(x) (((uint16_t)(x) << WM8960_3D_3DEN_SHIFT) & WM8960_3D_3DEN_MASK) +#define WM8960_3D_3DEN_GET(x) (((uint16_t)(x) & WM8960_3D_3DEN_MASK) >> WM8960_3D_3DEN_SHIFT) + +/* Bitfield definition for register: ALC1 */ +/* + * ALCSEL (RW) + * + * ALC Function Select + * 00 = ALC off (PGA gain set by register) + * 01 = Right channel only + * 10 = Left channel only + * 11 = Stereo (PGA registers unused) Note: + * ensure that LINVOL and RINVOL settings + * (reg. 0 and 1) are the same before entering this mode. + */ +#define WM8960_ALC1_ALCSEL_MASK (0x180U) +#define WM8960_ALC1_ALCSEL_SHIFT (7U) +#define WM8960_ALC1_ALCSEL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCSEL_SHIFT) & WM8960_ALC1_ALCSEL_MASK) +#define WM8960_ALC1_ALCSEL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCSEL_MASK) >> WM8960_ALC1_ALCSEL_SHIFT) + +/* + * MAXGAIN (RW) + * + * Set Maximum Gain of PGA (During ALC + * operation) + * 111 : +30dB + * 110 : +24dB + * ….(-6dB steps) + * 001 : -6dB + * 000 : -12dB + */ +#define WM8960_ALC1_MAXGAIN_MASK (0x70U) +#define WM8960_ALC1_MAXGAIN_SHIFT (4U) +#define WM8960_ALC1_MAXGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC1_MAXGAIN_SHIFT) & WM8960_ALC1_MAXGAIN_MASK) +#define WM8960_ALC1_MAXGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC1_MAXGAIN_MASK) >> WM8960_ALC1_MAXGAIN_SHIFT) + +/* + * ALCL (RW) + * + * ALC Target (Sets signal level at ADC input) + * 0000 = -22.5dB FS + * 0001 = -21.0dB FS + * … (1.5dB steps) + * 1101 = -3.0dB FS + * 1110 = -1.5dB FS + * 1111 = -1.5dB FS + */ +#define WM8960_ALC1_ALCL_MASK (0xFU) +#define WM8960_ALC1_ALCL_SHIFT (0U) +#define WM8960_ALC1_ALCL_SET(x) (((uint16_t)(x) << WM8960_ALC1_ALCL_SHIFT) & WM8960_ALC1_ALCL_MASK) +#define WM8960_ALC1_ALCL_GET(x) (((uint16_t)(x) & WM8960_ALC1_ALCL_MASK) >> WM8960_ALC1_ALCL_SHIFT) + +/* Bitfield definition for register: ALC2 */ +/* + * MINGAIN (RW) + * + * Set Minimum Gain of PGA (During ALC + * operation) + * 000 = -17.25dB + * 001 = -11.25dB + * 010 = -5.25dB + * 011 = +0.75dB + * 100 = +6.75dB + * 101 = +12.75dB + * 110 = +18.75dB + * 111 = +24.75dB + */ +#define WM8960_ALC2_MINGAIN_MASK (0x70U) +#define WM8960_ALC2_MINGAIN_SHIFT (4U) +#define WM8960_ALC2_MINGAIN_SET(x) (((uint16_t)(x) << WM8960_ALC2_MINGAIN_SHIFT) & WM8960_ALC2_MINGAIN_MASK) +#define WM8960_ALC2_MINGAIN_GET(x) (((uint16_t)(x) & WM8960_ALC2_MINGAIN_MASK) >> WM8960_ALC2_MINGAIN_SHIFT) + +/* + * HLD (RW) + * + * ALC hold time before gain is increased. + * 0000 = 0ms + * 0001 = 2.67ms + * 0010 = 5.33ms + * … (time doubles with every step) + * 1111 = 43.691s + */ +#define WM8960_ALC2_HLD_MASK (0xFU) +#define WM8960_ALC2_HLD_SHIFT (0U) +#define WM8960_ALC2_HLD_SET(x) (((uint16_t)(x) << WM8960_ALC2_HLD_SHIFT) & WM8960_ALC2_HLD_MASK) +#define WM8960_ALC2_HLD_GET(x) (((uint16_t)(x) & WM8960_ALC2_HLD_MASK) >> WM8960_ALC2_HLD_SHIFT) + +/* Bitfield definition for register: ALC3 */ +/* + * ALCMODE (RW) + * + * Determines the ALC mode of operation: + * 0 = ALC mode + * 1 = Limiter mode + */ +#define WM8960_ALC3_ALCMODE_MASK (0x100U) +#define WM8960_ALC3_ALCMODE_SHIFT (8U) +#define WM8960_ALC3_ALCMODE_SET(x) (((uint16_t)(x) << WM8960_ALC3_ALCMODE_SHIFT) & WM8960_ALC3_ALCMODE_MASK) +#define WM8960_ALC3_ALCMODE_GET(x) (((uint16_t)(x) & WM8960_ALC3_ALCMODE_MASK) >> WM8960_ALC3_ALCMODE_SHIFT) + +/* + * DCY (RW) + * + * ALC decay (gain ramp-up) time + * 0000 = 24ms + * 0001 = 48ms + * 0010 = 96ms + * … (time doubles with every step) + * 1010 or higher = 24.58s + */ +#define WM8960_ALC3_DCY_MASK (0xF0U) +#define WM8960_ALC3_DCY_SHIFT (4U) +#define WM8960_ALC3_DCY_SET(x) (((uint16_t)(x) << WM8960_ALC3_DCY_SHIFT) & WM8960_ALC3_DCY_MASK) +#define WM8960_ALC3_DCY_GET(x) (((uint16_t)(x) & WM8960_ALC3_DCY_MASK) >> WM8960_ALC3_DCY_SHIFT) + +/* + * ATK (RW) + * + * ALC attack (gain ramp-down) time + * 0000 = 6ms + * 0001 = 12ms + * 0010 = 24ms + * … (time doubles with every step) + * 1010 or higher = 6.14s + */ +#define WM8960_ALC3_ATK_MASK (0xFU) +#define WM8960_ALC3_ATK_SHIFT (0U) +#define WM8960_ALC3_ATK_SET(x) (((uint16_t)(x) << WM8960_ALC3_ATK_SHIFT) & WM8960_ALC3_ATK_MASK) +#define WM8960_ALC3_ATK_GET(x) (((uint16_t)(x) & WM8960_ALC3_ATK_MASK) >> WM8960_ALC3_ATK_SHIFT) + +/* Bitfield definition for register: NOISEG */ +/* + * NGTH (RW) + * + * Noise gate threshold + * 00000 -76.5dBfs + * 00001 -75dBfs + * … 1.5 dB steps + * 11110 -31.5dBfs + * 11111 -30dBfs + */ +#define WM8960_NOISEG_NGTH_MASK (0xF8U) +#define WM8960_NOISEG_NGTH_SHIFT (3U) +#define WM8960_NOISEG_NGTH_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGTH_SHIFT) & WM8960_NOISEG_NGTH_MASK) +#define WM8960_NOISEG_NGTH_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGTH_MASK) >> WM8960_NOISEG_NGTH_SHIFT) + +/* + * NGAT (RW) + * + * Noise gate function enable + * 0 = disable + * 1 = enable + */ +#define WM8960_NOISEG_NGAT_MASK (0x1U) +#define WM8960_NOISEG_NGAT_SHIFT (0U) +#define WM8960_NOISEG_NGAT_SET(x) (((uint16_t)(x) << WM8960_NOISEG_NGAT_SHIFT) & WM8960_NOISEG_NGAT_MASK) +#define WM8960_NOISEG_NGAT_GET(x) (((uint16_t)(x) & WM8960_NOISEG_NGAT_MASK) >> WM8960_NOISEG_NGAT_SHIFT) + +/* Bitfield definition for register: LADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and + * RADCVOL) + */ +#define WM8960_LADC_ADCVU_MASK (0x100U) +#define WM8960_LADC_ADCVU_SHIFT (8U) +#define WM8960_LADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_LADC_ADCVU_SHIFT) & WM8960_LADC_ADCVU_MASK) +#define WM8960_LADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_LADC_ADCVU_MASK) >> WM8960_LADC_ADCVU_SHIFT) + +/* + * LADCVOL (RW) + * + * Left ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_LADC_LADCVOL_MASK (0xFFU) +#define WM8960_LADC_LADCVOL_SHIFT (0U) +#define WM8960_LADC_LADCVOL_SET(x) (((uint16_t)(x) << WM8960_LADC_LADCVOL_SHIFT) & WM8960_LADC_LADCVOL_MASK) +#define WM8960_LADC_LADCVOL_GET(x) (((uint16_t)(x) & WM8960_LADC_LADCVOL_MASK) >> WM8960_LADC_LADCVOL_SHIFT) + +/* Bitfield definition for register: RADC */ +/* + * ADCVU (RW) + * + * ADC Volume Update + * Writing a 1 to this bit will cause left and right + * ADC volumes to be updated (LADCVOL and RADCVOL) + */ +#define WM8960_RADC_ADCVU_MASK (0x100U) +#define WM8960_RADC_ADCVU_SHIFT (8U) +#define WM8960_RADC_ADCVU_SET(x) (((uint16_t)(x) << WM8960_RADC_ADCVU_SHIFT) & WM8960_RADC_ADCVU_MASK) +#define WM8960_RADC_ADCVU_GET(x) (((uint16_t)(x) & WM8960_RADC_ADCVU_MASK) >> WM8960_RADC_ADCVU_SHIFT) + +/* + * RADCVOL (RW) + * + * Right ADC Digital Volume Control + * 0000 0000 = Digital Mute + * 0000 0001 = -97dB + * 0000 0010 = -96.5dB + * ... 0.5dB steps up to + * 1111 1111 = +30dB + */ +#define WM8960_RADC_RADCVOL_MASK (0xFFU) +#define WM8960_RADC_RADCVOL_SHIFT (0U) +#define WM8960_RADC_RADCVOL_SET(x) (((uint16_t)(x) << WM8960_RADC_RADCVOL_SHIFT) & WM8960_RADC_RADCVOL_MASK) +#define WM8960_RADC_RADCVOL_GET(x) (((uint16_t)(x) & WM8960_RADC_RADCVOL_MASK) >> WM8960_RADC_RADCVOL_SHIFT) + +/* Bitfield definition for register: ADDCTL1 */ +/* + * TSDEN (RW) + * + * Thermal Shutdown Enable + * 0 = Thermal shutdown disabled + * 1 = Thermal shutdown enabled + * (TSENSEN must be enabled for this function to work) + */ +#define WM8960_ADDCTL1_TSDEN_MASK (0x100U) +#define WM8960_ADDCTL1_TSDEN_SHIFT (8U) +#define WM8960_ADDCTL1_TSDEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TSDEN_SHIFT) & WM8960_ADDCTL1_TSDEN_MASK) +#define WM8960_ADDCTL1_TSDEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TSDEN_MASK) >> WM8960_ADDCTL1_TSDEN_SHIFT) + +/* + * VSEL (RW) + * + * Analogue Bias Optimisation + * 00 = Reserved + * 01 = Increased bias current optimized for + * AVDD=2.7V + * 1X = Lowest bias current, optimized for + * AVDD=3.3V + */ +#define WM8960_ADDCTL1_VSEL_MASK (0xC0U) +#define WM8960_ADDCTL1_VSEL_SHIFT (6U) +#define WM8960_ADDCTL1_VSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_VSEL_SHIFT) & WM8960_ADDCTL1_VSEL_MASK) +#define WM8960_ADDCTL1_VSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_VSEL_MASK) >> WM8960_ADDCTL1_VSEL_SHIFT) + +/* + * DMONOMIX (RW) + * + * DAC Mono Mix + * 0 = Stereo + * 1 = Mono (Mono MIX output on enabled DACs + */ +#define WM8960_ADDCTL1_DMONOMIX_MASK (0x10U) +#define WM8960_ADDCTL1_DMONOMIX_SHIFT (4U) +#define WM8960_ADDCTL1_DMONOMIX_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DMONOMIX_SHIFT) & WM8960_ADDCTL1_DMONOMIX_MASK) +#define WM8960_ADDCTL1_DMONOMIX_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DMONOMIX_MASK) >> WM8960_ADDCTL1_DMONOMIX_SHIFT) + +/* + * DATSEL (RW) + * + * ADC Data Output Select + * 00: left data = left ADC; right data =right ADC + * 01: left data = left ADC; right data = left ADC + * 10: left data = right ADC; right data =right ADC + * 11: left data = right ADC; right data = left ADC + */ +#define WM8960_ADDCTL1_DATSEL_MASK (0xCU) +#define WM8960_ADDCTL1_DATSEL_SHIFT (2U) +#define WM8960_ADDCTL1_DATSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_DATSEL_SHIFT) & WM8960_ADDCTL1_DATSEL_MASK) +#define WM8960_ADDCTL1_DATSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_DATSEL_MASK) >> WM8960_ADDCTL1_DATSEL_SHIFT) + +/* + * TOCLKSEL (RW) + * + * Slow Clock Select (Used for volume update + * timeouts and for jack detect debounce) + * 0 = SYSCLK / 221 (Slower Response) + * 1 = SYSCLK / 219 (Faster Response) + */ +#define WM8960_ADDCTL1_TOCLKSEL_MASK (0x2U) +#define WM8960_ADDCTL1_TOCLKSEL_SHIFT (1U) +#define WM8960_ADDCTL1_TOCLKSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOCLKSEL_SHIFT) & WM8960_ADDCTL1_TOCLKSEL_MASK) +#define WM8960_ADDCTL1_TOCLKSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOCLKSEL_MASK) >> WM8960_ADDCTL1_TOCLKSEL_SHIFT) + +/* + * TOEN (RW) + * + * Enables Slow Clock for Volume Update Timeout + * and Jack Detect Debounce + * 0 = Slow clock disabled + * 1 = Slow clock enabled + */ +#define WM8960_ADDCTL1_TOEN_MASK (0x1U) +#define WM8960_ADDCTL1_TOEN_SHIFT (0U) +#define WM8960_ADDCTL1_TOEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL1_TOEN_SHIFT) & WM8960_ADDCTL1_TOEN_MASK) +#define WM8960_ADDCTL1_TOEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL1_TOEN_MASK) >> WM8960_ADDCTL1_TOEN_SHIFT) + +/* Bitfield definition for register: ADDCTL2 */ +/* + * HPSWEN (RW) + * + * Headphone Switch Enable + * 0 = Headphone switch disabled + * 1 = Headphone switch enabled + */ +#define WM8960_ADDCTL2_HPSWEN_MASK (0x40U) +#define WM8960_ADDCTL2_HPSWEN_SHIFT (6U) +#define WM8960_ADDCTL2_HPSWEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWEN_SHIFT) & WM8960_ADDCTL2_HPSWEN_MASK) +#define WM8960_ADDCTL2_HPSWEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWEN_MASK) >> WM8960_ADDCTL2_HPSWEN_SHIFT) + +/* + * HPSWPOL (RW) + * + * Headphone Switch Polarity + * 0 = HPDETECT high = headphone + * 1 = HPDETECT high = speaker + */ +#define WM8960_ADDCTL2_HPSWPOL_MASK (0x20U) +#define WM8960_ADDCTL2_HPSWPOL_SHIFT (5U) +#define WM8960_ADDCTL2_HPSWPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_HPSWPOL_SHIFT) & WM8960_ADDCTL2_HPSWPOL_MASK) +#define WM8960_ADDCTL2_HPSWPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_HPSWPOL_MASK) >> WM8960_ADDCTL2_HPSWPOL_SHIFT) + +/* + * TRIS (RW) + * + * Tristates ADCDAT and switches ADCLRC, + * DACLRC and BCLK to inputs. + * 0 = ADCDAT is an output; ADCLRC, DACLRC + * and BCLK are inputs (slave mode) or outputs + * (master mode) + * 1 = ADCDAT is tristated; DACLRC and BCLK + * are inputs; ADCLRC is an input (when not + * configured as a GPIO) + */ +#define WM8960_ADDCTL2_TRIS_MASK (0x8U) +#define WM8960_ADDCTL2_TRIS_SHIFT (3U) +#define WM8960_ADDCTL2_TRIS_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_TRIS_SHIFT) & WM8960_ADDCTL2_TRIS_MASK) +#define WM8960_ADDCTL2_TRIS_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_TRIS_MASK) >> WM8960_ADDCTL2_TRIS_SHIFT) + +/* + * LRCM (RW) + * + * Selects disable mode for ADCLRC and DACLRC + * (Master mode) + * 0 = ADCLRC disabled when ADC (Left and + * Right) disabled; DACLRC disabled when + * DAC (Left and Right) disabled. + * 1 = ADCLRC and DACLRC disabled only when + * ADC (Left and Right) and DAC (Left and Right) + * are disabled. + */ +#define WM8960_ADDCTL2_LRCM_MASK (0x4U) +#define WM8960_ADDCTL2_LRCM_SHIFT (2U) +#define WM8960_ADDCTL2_LRCM_SET(x) (((uint16_t)(x) << WM8960_ADDCTL2_LRCM_SHIFT) & WM8960_ADDCTL2_LRCM_MASK) +#define WM8960_ADDCTL2_LRCM_GET(x) (((uint16_t)(x) & WM8960_ADDCTL2_LRCM_MASK) >> WM8960_ADDCTL2_LRCM_SHIFT) + +/* Bitfield definition for register: POWER1 */ +/* + * VMIDSEL (RW) + * + * Vmid Divider Enable and Select + * 00 = Vmid disabled (for OFF mode) + * 01 = 2 x 50k divider enabled (for playback / + * record) + * 10 = 2 x 250k divider enabled (for low-power + * standby) + * 11 = 2 x 5k divider enabled (for fast start-up) + */ +#define WM8960_POWER1_VMIDSEL_MASK (0x180U) +#define WM8960_POWER1_VMIDSEL_SHIFT (7U) +#define WM8960_POWER1_VMIDSEL_SET(x) (((uint16_t)(x) << WM8960_POWER1_VMIDSEL_SHIFT) & WM8960_POWER1_VMIDSEL_MASK) +#define WM8960_POWER1_VMIDSEL_GET(x) (((uint16_t)(x) & WM8960_POWER1_VMIDSEL_MASK) >> WM8960_POWER1_VMIDSEL_SHIFT) + +/* + * VREF (RW) + * + * VREF (necessary for all other functions) + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_VREF_MASK (0x40U) +#define WM8960_POWER1_VREF_SHIFT (6U) +#define WM8960_POWER1_VREF_SET(x) (((uint16_t)(x) << WM8960_POWER1_VREF_SHIFT) & WM8960_POWER1_VREF_MASK) +#define WM8960_POWER1_VREF_GET(x) (((uint16_t)(x) & WM8960_POWER1_VREF_MASK) >> WM8960_POWER1_VREF_SHIFT) + +/* + * AINL (RW) + * + * Analogue in PGA Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINL_MASK (0x20U) +#define WM8960_POWER1_AINL_SHIFT (5U) +#define WM8960_POWER1_AINL_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINL_SHIFT) & WM8960_POWER1_AINL_MASK) +#define WM8960_POWER1_AINL_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINL_MASK) >> WM8960_POWER1_AINL_SHIFT) + +/* + * AINR (RW) + * + * Analogue in PGA Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_AINR_MASK (0x10U) +#define WM8960_POWER1_AINR_SHIFT (4U) +#define WM8960_POWER1_AINR_SET(x) (((uint16_t)(x) << WM8960_POWER1_AINR_SHIFT) & WM8960_POWER1_AINR_MASK) +#define WM8960_POWER1_AINR_GET(x) (((uint16_t)(x) & WM8960_POWER1_AINR_MASK) >> WM8960_POWER1_AINR_SHIFT) + +/* + * ADCL (RW) + * + * ADC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCL_MASK (0x8U) +#define WM8960_POWER1_ADCL_SHIFT (3U) +#define WM8960_POWER1_ADCL_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCL_SHIFT) & WM8960_POWER1_ADCL_MASK) +#define WM8960_POWER1_ADCL_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCL_MASK) >> WM8960_POWER1_ADCL_SHIFT) + +/* + * ADCR (RW) + * + * ADC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_ADCR_MASK (0x4U) +#define WM8960_POWER1_ADCR_SHIFT (2U) +#define WM8960_POWER1_ADCR_SET(x) (((uint16_t)(x) << WM8960_POWER1_ADCR_SHIFT) & WM8960_POWER1_ADCR_MASK) +#define WM8960_POWER1_ADCR_GET(x) (((uint16_t)(x) & WM8960_POWER1_ADCR_MASK) >> WM8960_POWER1_ADCR_SHIFT) + +/* + * MICB (RW) + * + * MICBIAS + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER1_MICB_MASK (0x2U) +#define WM8960_POWER1_MICB_SHIFT (1U) +#define WM8960_POWER1_MICB_SET(x) (((uint16_t)(x) << WM8960_POWER1_MICB_SHIFT) & WM8960_POWER1_MICB_MASK) +#define WM8960_POWER1_MICB_GET(x) (((uint16_t)(x) & WM8960_POWER1_MICB_MASK) >> WM8960_POWER1_MICB_SHIFT) + +/* + * DIGENB (RW) + * + * Master Clock Disable + * 0 = Master clock enabled + * 1 = Master clock disabled + */ +#define WM8960_POWER1_DIGENB_MASK (0x1U) +#define WM8960_POWER1_DIGENB_SHIFT (0U) +#define WM8960_POWER1_DIGENB_SET(x) (((uint16_t)(x) << WM8960_POWER1_DIGENB_SHIFT) & WM8960_POWER1_DIGENB_MASK) +#define WM8960_POWER1_DIGENB_GET(x) (((uint16_t)(x) & WM8960_POWER1_DIGENB_MASK) >> WM8960_POWER1_DIGENB_SHIFT) + +/* Bitfield definition for register: POWER2 */ +/* + * DACL (RW) + * + * DAC Left + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACL_MASK (0x100U) +#define WM8960_POWER2_DACL_SHIFT (8U) +#define WM8960_POWER2_DACL_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACL_SHIFT) & WM8960_POWER2_DACL_MASK) +#define WM8960_POWER2_DACL_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACL_MASK) >> WM8960_POWER2_DACL_SHIFT) + +/* + * DACR (RW) + * + * DAC Right + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_DACR_MASK (0x80U) +#define WM8960_POWER2_DACR_SHIFT (7U) +#define WM8960_POWER2_DACR_SET(x) (((uint16_t)(x) << WM8960_POWER2_DACR_SHIFT) & WM8960_POWER2_DACR_MASK) +#define WM8960_POWER2_DACR_GET(x) (((uint16_t)(x) & WM8960_POWER2_DACR_MASK) >> WM8960_POWER2_DACR_SHIFT) + +/* + * LOUT1 (RW) + * + * LOUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_LOUT1_MASK (0x40U) +#define WM8960_POWER2_LOUT1_SHIFT (6U) +#define WM8960_POWER2_LOUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_LOUT1_SHIFT) & WM8960_POWER2_LOUT1_MASK) +#define WM8960_POWER2_LOUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_LOUT1_MASK) >> WM8960_POWER2_LOUT1_SHIFT) + +/* + * ROUT1 (RW) + * + * ROUT1 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_ROUT1_MASK (0x20U) +#define WM8960_POWER2_ROUT1_SHIFT (5U) +#define WM8960_POWER2_ROUT1_SET(x) (((uint16_t)(x) << WM8960_POWER2_ROUT1_SHIFT) & WM8960_POWER2_ROUT1_MASK) +#define WM8960_POWER2_ROUT1_GET(x) (((uint16_t)(x) & WM8960_POWER2_ROUT1_MASK) >> WM8960_POWER2_ROUT1_SHIFT) + +/* + * SPKL (RW) + * + * SPK_LP/SPK_LN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKL_MASK (0x10U) +#define WM8960_POWER2_SPKL_SHIFT (4U) +#define WM8960_POWER2_SPKL_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKL_SHIFT) & WM8960_POWER2_SPKL_MASK) +#define WM8960_POWER2_SPKL_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKL_MASK) >> WM8960_POWER2_SPKL_SHIFT) + +/* + * SPKR (RW) + * + * SPK_RP/SPK_RN Output Buffers + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_SPKR_MASK (0x8U) +#define WM8960_POWER2_SPKR_SHIFT (3U) +#define WM8960_POWER2_SPKR_SET(x) (((uint16_t)(x) << WM8960_POWER2_SPKR_SHIFT) & WM8960_POWER2_SPKR_MASK) +#define WM8960_POWER2_SPKR_GET(x) (((uint16_t)(x) & WM8960_POWER2_SPKR_MASK) >> WM8960_POWER2_SPKR_SHIFT) + +/* + * OUT3 (RW) + * + * OUT3 Output Buffer + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_OUT3_MASK (0x2U) +#define WM8960_POWER2_OUT3_SHIFT (1U) +#define WM8960_POWER2_OUT3_SET(x) (((uint16_t)(x) << WM8960_POWER2_OUT3_SHIFT) & WM8960_POWER2_OUT3_MASK) +#define WM8960_POWER2_OUT3_GET(x) (((uint16_t)(x) & WM8960_POWER2_OUT3_MASK) >> WM8960_POWER2_OUT3_SHIFT) + +/* + * PLL_EN (RW) + * + * PLL Enable + * 0 = Power down + * 1 = Power up + */ +#define WM8960_POWER2_PLL_EN_MASK (0x1U) +#define WM8960_POWER2_PLL_EN_SHIFT (0U) +#define WM8960_POWER2_PLL_EN_SET(x) (((uint16_t)(x) << WM8960_POWER2_PLL_EN_SHIFT) & WM8960_POWER2_PLL_EN_MASK) +#define WM8960_POWER2_PLL_EN_GET(x) (((uint16_t)(x) & WM8960_POWER2_PLL_EN_MASK) >> WM8960_POWER2_PLL_EN_SHIFT) + +/* Bitfield definition for register: ADDCTL3 */ +/* + * VROI (RW) + * + * VREF to Analogue Output Resistance (Disabled + * Outputs) + * 0 = 500 VMID to output + * 1 = 20k VMID to output + */ +#define WM8960_ADDCTL3_VROI_MASK (0x40U) +#define WM8960_ADDCTL3_VROI_SHIFT (6U) +#define WM8960_ADDCTL3_VROI_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_VROI_SHIFT) & WM8960_ADDCTL3_VROI_MASK) +#define WM8960_ADDCTL3_VROI_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_VROI_MASK) >> WM8960_ADDCTL3_VROI_SHIFT) + +/* + * OUT3CAP (RW) + * + * Capless Mode Headphone Switch Enable + * 0 = OUT3 unaffected by jack detect events + * 1 = OUT3 enabled and disabled together with + * HP_L and HP_R in response to jack detect + * events + */ +#define WM8960_ADDCTL3_OUT3CAP_MASK (0x8U) +#define WM8960_ADDCTL3_OUT3CAP_SHIFT (3U) +#define WM8960_ADDCTL3_OUT3CAP_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_OUT3CAP_SHIFT) & WM8960_ADDCTL3_OUT3CAP_MASK) +#define WM8960_ADDCTL3_OUT3CAP_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_OUT3CAP_MASK) >> WM8960_ADDCTL3_OUT3CAP_SHIFT) + +/* + * ADC_ALC_SR (RW) + * + * ALC Sample Rate + * 000 = 44.1k / 48k + * 001 = 32k + * 010 = 22.05k / 24k + * 011 = 16k + * 100 = 11.25k / 12k + * 101 = 8k + * 110 and 111 = Reserved + */ +#define WM8960_ADDCTL3_ADC_ALC_SR_MASK (0x7U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SHIFT (0U) +#define WM8960_ADDCTL3_ADC_ALC_SR_SET(x) (((uint16_t)(x) << WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) +#define WM8960_ADDCTL3_ADC_ALC_SR_GET(x) (((uint16_t)(x) & WM8960_ADDCTL3_ADC_ALC_SR_MASK) >> WM8960_ADDCTL3_ADC_ALC_SR_SHIFT) + +/* Bitfield definition for register: APOP1 */ +/* + * POBCTRL (RW) + * + * Selects the bias current source for output + * amplifiers and VMID buffer + * 0 = VMID / R bias + * 1 = VGS / R bias + */ +#define WM8960_APOP1_POBCTRL_MASK (0x80U) +#define WM8960_APOP1_POBCTRL_SHIFT (7U) +#define WM8960_APOP1_POBCTRL_SET(x) (((uint16_t)(x) << WM8960_APOP1_POBCTRL_SHIFT) & WM8960_APOP1_POBCTRL_MASK) +#define WM8960_APOP1_POBCTRL_GET(x) (((uint16_t)(x) & WM8960_APOP1_POBCTRL_MASK) >> WM8960_APOP1_POBCTRL_SHIFT) + +/* + * BUFDCOPEN (RW) + * + * Enables the VGS / R current generator + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFDCOPEN_MASK (0x10U) +#define WM8960_APOP1_BUFDCOPEN_SHIFT (4U) +#define WM8960_APOP1_BUFDCOPEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFDCOPEN_SHIFT) & WM8960_APOP1_BUFDCOPEN_MASK) +#define WM8960_APOP1_BUFDCOPEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFDCOPEN_MASK) >> WM8960_APOP1_BUFDCOPEN_SHIFT) + +/* + * BUFIOEN (RW) + * + * Enables the VGS / R current generator and the + * analogue input and output bias + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_BUFIOEN_MASK (0x8U) +#define WM8960_APOP1_BUFIOEN_SHIFT (3U) +#define WM8960_APOP1_BUFIOEN_SET(x) (((uint16_t)(x) << WM8960_APOP1_BUFIOEN_SHIFT) & WM8960_APOP1_BUFIOEN_MASK) +#define WM8960_APOP1_BUFIOEN_GET(x) (((uint16_t)(x) & WM8960_APOP1_BUFIOEN_MASK) >> WM8960_APOP1_BUFIOEN_SHIFT) + +/* + * SOFT_ST (RW) + * + * Enables VMID soft start + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP1_SOFT_ST_MASK (0x4U) +#define WM8960_APOP1_SOFT_ST_SHIFT (2U) +#define WM8960_APOP1_SOFT_ST_SET(x) (((uint16_t)(x) << WM8960_APOP1_SOFT_ST_SHIFT) & WM8960_APOP1_SOFT_ST_MASK) +#define WM8960_APOP1_SOFT_ST_GET(x) (((uint16_t)(x) & WM8960_APOP1_SOFT_ST_MASK) >> WM8960_APOP1_SOFT_ST_SHIFT) + +/* + * HPSTBY (RW) + * + * Headphone Amplifier Standby + * 0 = Standby mode disabled (Normal operation) + * 1 = Standby mode enabled + */ +#define WM8960_APOP1_HPSTBY_MASK (0x1U) +#define WM8960_APOP1_HPSTBY_SHIFT (0U) +#define WM8960_APOP1_HPSTBY_SET(x) (((uint16_t)(x) << WM8960_APOP1_HPSTBY_SHIFT) & WM8960_APOP1_HPSTBY_MASK) +#define WM8960_APOP1_HPSTBY_GET(x) (((uint16_t)(x) & WM8960_APOP1_HPSTBY_MASK) >> WM8960_APOP1_HPSTBY_SHIFT) + +/* Bitfield definition for register: APOP2 */ +/* + * DISOP (RW) + * + * Discharges the DC-blocking headphone + * capacitors on HP_L and HP_R + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_APOP2_DISOP_MASK (0x40U) +#define WM8960_APOP2_DISOP_SHIFT (6U) +#define WM8960_APOP2_DISOP_SET(x) (((uint16_t)(x) << WM8960_APOP2_DISOP_SHIFT) & WM8960_APOP2_DISOP_MASK) +#define WM8960_APOP2_DISOP_GET(x) (((uint16_t)(x) & WM8960_APOP2_DISOP_MASK) >> WM8960_APOP2_DISOP_SHIFT) + +/* + * DRES (RW) + * + * DRES determines the value of the resistors used + * to discharge the DC-blocking headphone + * capacitors when DISOP=1 + * DRES[1:0] Resistance (Ohms) + * 0 0 400 + * 0 1 200 + * 1 0 600 + * 1 1 150 + */ +#define WM8960_APOP2_DRES_MASK (0x30U) +#define WM8960_APOP2_DRES_SHIFT (4U) +#define WM8960_APOP2_DRES_SET(x) (((uint16_t)(x) << WM8960_APOP2_DRES_SHIFT) & WM8960_APOP2_DRES_MASK) +#define WM8960_APOP2_DRES_GET(x) (((uint16_t)(x) & WM8960_APOP2_DRES_MASK) >> WM8960_APOP2_DRES_SHIFT) + +/* Bitfield definition for register: LINPATH */ +/* + * LMN1 (RW) + * + * Connect LINPUT1 to inverting input of Left Input + * PGA + * 0 = LINPUT1 not connected to PGA + * 1 = LINPUT1 connected to PGA + */ +#define WM8960_LINPATH_LMN1_MASK (0x100U) +#define WM8960_LINPATH_LMN1_SHIFT (8U) +#define WM8960_LINPATH_LMN1_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMN1_SHIFT) & WM8960_LINPATH_LMN1_MASK) +#define WM8960_LINPATH_LMN1_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMN1_MASK) >> WM8960_LINPATH_LMN1_SHIFT) + +/* + * LMP3 (RW) + * + * Connect LINPUT3 to non-inverting input of Left + * Input PGA + * 0 = LINPUT3 not connected to PGA + * 1 = LINPUT3 connected to PGA (Constant input + * impedance) + */ +#define WM8960_LINPATH_LMP3_MASK (0x80U) +#define WM8960_LINPATH_LMP3_SHIFT (7U) +#define WM8960_LINPATH_LMP3_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP3_SHIFT) & WM8960_LINPATH_LMP3_MASK) +#define WM8960_LINPATH_LMP3_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP3_MASK) >> WM8960_LINPATH_LMP3_SHIFT) + +/* + * LMP2 (RW) + * + * Connect LINPUT2 to non-inverting input of Left + * Input PGA + * 0 = LINPUT2 not connected to PGA + * 1 = LINPUT2 connected to PGA (Constant input impedance) + */ +#define WM8960_LINPATH_LMP2_MASK (0x40U) +#define WM8960_LINPATH_LMP2_SHIFT (6U) +#define WM8960_LINPATH_LMP2_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMP2_SHIFT) & WM8960_LINPATH_LMP2_MASK) +#define WM8960_LINPATH_LMP2_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMP2_MASK) >> WM8960_LINPATH_LMP2_SHIFT) + +/* + * LMICBOOST (RW) + * + * Left Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_LINPATH_LMICBOOST_MASK (0x30U) +#define WM8960_LINPATH_LMICBOOST_SHIFT (4U) +#define WM8960_LINPATH_LMICBOOST_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMICBOOST_SHIFT) & WM8960_LINPATH_LMICBOOST_MASK) +#define WM8960_LINPATH_LMICBOOST_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMICBOOST_MASK) >> WM8960_LINPATH_LMICBOOST_SHIFT) + +/* + * LMIC2B (RW) + * + * Connect Left Input PGA to Left Input Boost Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_LINPATH_LMIC2B_MASK (0x8U) +#define WM8960_LINPATH_LMIC2B_SHIFT (3U) +#define WM8960_LINPATH_LMIC2B_SET(x) (((uint16_t)(x) << WM8960_LINPATH_LMIC2B_SHIFT) & WM8960_LINPATH_LMIC2B_MASK) +#define WM8960_LINPATH_LMIC2B_GET(x) (((uint16_t)(x) & WM8960_LINPATH_LMIC2B_MASK) >> WM8960_LINPATH_LMIC2B_SHIFT) + +/* Bitfield definition for register: RINPATH */ +/* + * RMN1 (RW) + * + * Connect RINPUT1 to inverting input of Right + * Input PGA + * 0 = RINPUT1 not connected to PGA + * 1 = RINPUT1 connected to PGA + */ +#define WM8960_RINPATH_RMN1_MASK (0x100U) +#define WM8960_RINPATH_RMN1_SHIFT (8U) +#define WM8960_RINPATH_RMN1_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMN1_SHIFT) & WM8960_RINPATH_RMN1_MASK) +#define WM8960_RINPATH_RMN1_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMN1_MASK) >> WM8960_RINPATH_RMN1_SHIFT) + +/* + * RMP3 (RW) + * + * Connect RINPUT3 to non-inverting input of Right + * Input PGA + * 0 = RINPUT3 not connected to PGA + * 1 = RINPUT3 connected to PGA (Constant input impedance) + */ +#define WM8960_RINPATH_RMP3_MASK (0x80U) +#define WM8960_RINPATH_RMP3_SHIFT (7U) +#define WM8960_RINPATH_RMP3_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP3_SHIFT) & WM8960_RINPATH_RMP3_MASK) +#define WM8960_RINPATH_RMP3_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP3_MASK) >> WM8960_RINPATH_RMP3_SHIFT) + +/* + * RMP2 (RW) + * + * Connect RINPUT2 to non-inverting input of Right + * Input PGA + * 0 = RINPUT2 not connected to PGA + * 1 = RINPUT2 connected to PGA (Constant input + * impedance) + */ +#define WM8960_RINPATH_RMP2_MASK (0x40U) +#define WM8960_RINPATH_RMP2_SHIFT (6U) +#define WM8960_RINPATH_RMP2_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMP2_SHIFT) & WM8960_RINPATH_RMP2_MASK) +#define WM8960_RINPATH_RMP2_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMP2_MASK) >> WM8960_RINPATH_RMP2_SHIFT) + +/* + * RMICBOOST (RW) + * + * Right Channel Input PGA Boost Gain + * 00 = +0dB + * 01 = +13dB + * 10 = +20dB + * 11 = +29dB + */ +#define WM8960_RINPATH_RMICBOOST_MASK (0x30U) +#define WM8960_RINPATH_RMICBOOST_SHIFT (4U) +#define WM8960_RINPATH_RMICBOOST_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMICBOOST_SHIFT) & WM8960_RINPATH_RMICBOOST_MASK) +#define WM8960_RINPATH_RMICBOOST_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMICBOOST_MASK) >> WM8960_RINPATH_RMICBOOST_SHIFT) + +/* + * RMIC2B (RW) + * + * Connect Right Input PGA to Right Input Boost + * Mixer + * 0 = Not connected + * 1 = Connected + */ +#define WM8960_RINPATH_RMIC2B_MASK (0x8U) +#define WM8960_RINPATH_RMIC2B_SHIFT (3U) +#define WM8960_RINPATH_RMIC2B_SET(x) (((uint16_t)(x) << WM8960_RINPATH_RMIC2B_SHIFT) & WM8960_RINPATH_RMIC2B_MASK) +#define WM8960_RINPATH_RMIC2B_GET(x) (((uint16_t)(x) & WM8960_RINPATH_RMIC2B_MASK) >> WM8960_RINPATH_RMIC2B_SHIFT) + +/* Bitfield definition for register: LOUTMIX */ +/* + * LD2LO (RW) + * + * Left DAC to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LD2LO_MASK (0x100U) +#define WM8960_LOUTMIX_LD2LO_SHIFT (8U) +#define WM8960_LOUTMIX_LD2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LD2LO_SHIFT) & WM8960_LOUTMIX_LD2LO_MASK) +#define WM8960_LOUTMIX_LD2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LD2LO_MASK) >> WM8960_LOUTMIX_LD2LO_SHIFT) + +/* + * LI2LO (RW) + * + * LINPUT3 to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_LOUTMIX_LI2LO_MASK (0x80U) +#define WM8960_LOUTMIX_LI2LO_SHIFT (7U) +#define WM8960_LOUTMIX_LI2LO_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LO_SHIFT) & WM8960_LOUTMIX_LI2LO_MASK) +#define WM8960_LOUTMIX_LI2LO_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LO_MASK) >> WM8960_LOUTMIX_LI2LO_SHIFT) + +/* + * LI2LOVOL (RW) + * + * LINPUT3 to Left Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_LOUTMIX_LI2LOVOL_MASK (0x70U) +#define WM8960_LOUTMIX_LI2LOVOL_SHIFT (4U) +#define WM8960_LOUTMIX_LI2LOVOL_SET(x) (((uint16_t)(x) << WM8960_LOUTMIX_LI2LOVOL_SHIFT) & WM8960_LOUTMIX_LI2LOVOL_MASK) +#define WM8960_LOUTMIX_LI2LOVOL_GET(x) (((uint16_t)(x) & WM8960_LOUTMIX_LI2LOVOL_MASK) >> WM8960_LOUTMIX_LI2LOVOL_SHIFT) + +/* Bitfield definition for register: ROUTMIX */ +/* + * RD2RO (RW) + * + * Right DAC to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RD2RO_MASK (0x100U) +#define WM8960_ROUTMIX_RD2RO_SHIFT (8U) +#define WM8960_ROUTMIX_RD2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RD2RO_SHIFT) & WM8960_ROUTMIX_RD2RO_MASK) +#define WM8960_ROUTMIX_RD2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RD2RO_MASK) >> WM8960_ROUTMIX_RD2RO_SHIFT) + +/* + * RI2RO (RW) + * + * RINPUT3 to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_ROUTMIX_RI2RO_MASK (0x80U) +#define WM8960_ROUTMIX_RI2RO_SHIFT (7U) +#define WM8960_ROUTMIX_RI2RO_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2RO_SHIFT) & WM8960_ROUTMIX_RI2RO_MASK) +#define WM8960_ROUTMIX_RI2RO_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2RO_MASK) >> WM8960_ROUTMIX_RI2RO_SHIFT) + +/* + * RI2ROVOL (RW) + * + * RINPUT3 to Right Output Mixer Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_ROUTMIX_RI2ROVOL_MASK (0x70U) +#define WM8960_ROUTMIX_RI2ROVOL_SHIFT (4U) +#define WM8960_ROUTMIX_RI2ROVOL_SET(x) (((uint16_t)(x) << WM8960_ROUTMIX_RI2ROVOL_SHIFT) & WM8960_ROUTMIX_RI2ROVOL_MASK) +#define WM8960_ROUTMIX_RI2ROVOL_GET(x) (((uint16_t)(x) & WM8960_ROUTMIX_RI2ROVOL_MASK) >> WM8960_ROUTMIX_RI2ROVOL_SHIFT) + +/* Bitfield definition for register: MONOMIX1 */ +/* + * L2MO (RW) + * + * Left Output Mixer to Mono Output Mixer Control + * 0 = Left channel mix disabled + * 1 = Left channel mix enabled + */ +#define WM8960_MONOMIX1_L2MO_MASK (0x80U) +#define WM8960_MONOMIX1_L2MO_SHIFT (7U) +#define WM8960_MONOMIX1_L2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX1_L2MO_SHIFT) & WM8960_MONOMIX1_L2MO_MASK) +#define WM8960_MONOMIX1_L2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX1_L2MO_MASK) >> WM8960_MONOMIX1_L2MO_SHIFT) + +/* Bitfield definition for register: MONOMIX2 */ +/* + * R2MO (RW) + * + * Right Output Mixer to Mono Output Mixer Control + * 0 = Right channel mix disabled + * 1 = Right channel mix enabled + */ +#define WM8960_MONOMIX2_R2MO_MASK (0x80U) +#define WM8960_MONOMIX2_R2MO_SHIFT (7U) +#define WM8960_MONOMIX2_R2MO_SET(x) (((uint16_t)(x) << WM8960_MONOMIX2_R2MO_SHIFT) & WM8960_MONOMIX2_R2MO_MASK) +#define WM8960_MONOMIX2_R2MO_GET(x) (((uint16_t)(x) & WM8960_MONOMIX2_R2MO_MASK) >> WM8960_MONOMIX2_R2MO_SHIFT) + +/* Bitfield definition for register: LOUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_LOUT2_SPKVU_MASK (0x100U) +#define WM8960_LOUT2_SPKVU_SHIFT (8U) +#define WM8960_LOUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKVU_SHIFT) & WM8960_LOUT2_SPKVU_MASK) +#define WM8960_LOUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKVU_MASK) >> WM8960_LOUT2_SPKVU_SHIFT) + +/* + * SPKLZC (RW) + * + * Left Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_LOUT2_SPKLZC_MASK (0x80U) +#define WM8960_LOUT2_SPKLZC_SHIFT (7U) +#define WM8960_LOUT2_SPKLZC_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLZC_SHIFT) & WM8960_LOUT2_SPKLZC_MASK) +#define WM8960_LOUT2_SPKLZC_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLZC_MASK) >> WM8960_LOUT2_SPKLZC_SHIFT) + +/* + * SPKLVOL (RW) + * + * SPK_LP/SPK_LN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_LOUT2_SPKLVOL_MASK (0x7FU) +#define WM8960_LOUT2_SPKLVOL_SHIFT (0U) +#define WM8960_LOUT2_SPKLVOL_SET(x) (((uint16_t)(x) << WM8960_LOUT2_SPKLVOL_SHIFT) & WM8960_LOUT2_SPKLVOL_MASK) +#define WM8960_LOUT2_SPKLVOL_GET(x) (((uint16_t)(x) & WM8960_LOUT2_SPKLVOL_MASK) >> WM8960_LOUT2_SPKLVOL_SHIFT) + +/* Bitfield definition for register: ROUT2 */ +/* + * SPKVU (RW) + * + * Speaker Volume Update + * Writing a 1 to this bit will cause left and right + * speaker volumes to be updated (SPKLVOL and SPKRVOL) + */ +#define WM8960_ROUT2_SPKVU_MASK (0x100U) +#define WM8960_ROUT2_SPKVU_SHIFT (8U) +#define WM8960_ROUT2_SPKVU_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKVU_SHIFT) & WM8960_ROUT2_SPKVU_MASK) +#define WM8960_ROUT2_SPKVU_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKVU_MASK) >> WM8960_ROUT2_SPKVU_SHIFT) + +/* + * SPKRZC (RW) + * + * Right Speaker Zero Cross Enable + * 1 = Change gain on zero cross only + * 0 = Change gain immediately + */ +#define WM8960_ROUT2_SPKRZC_MASK (0x80U) +#define WM8960_ROUT2_SPKRZC_SHIFT (7U) +#define WM8960_ROUT2_SPKRZC_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRZC_SHIFT) & WM8960_ROUT2_SPKRZC_MASK) +#define WM8960_ROUT2_SPKRZC_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRZC_MASK) >> WM8960_ROUT2_SPKRZC_SHIFT) + +/* + * SPKRVOL (RW) + * + * SPK_RP/SPK_RN Volume + * 1111111 = +6dB + * … 1dB steps down to + * 0110000 = -73dB + * 0101111 to 0000000 = Analogue MUTE + */ +#define WM8960_ROUT2_SPKRVOL_MASK (0x7FU) +#define WM8960_ROUT2_SPKRVOL_SHIFT (0U) +#define WM8960_ROUT2_SPKRVOL_SET(x) (((uint16_t)(x) << WM8960_ROUT2_SPKRVOL_SHIFT) & WM8960_ROUT2_SPKRVOL_MASK) +#define WM8960_ROUT2_SPKRVOL_GET(x) (((uint16_t)(x) & WM8960_ROUT2_SPKRVOL_MASK) >> WM8960_ROUT2_SPKRVOL_SHIFT) + +/* Bitfield definition for register: MONO */ +/* + * MOUTVOL (RW) + * + * Mono Output Mixer Volume Control + * 0 = 0dB + * 1 = -6dB + */ +#define WM8960_MONO_MOUTVOL_MASK (0x40U) +#define WM8960_MONO_MOUTVOL_SHIFT (6U) +#define WM8960_MONO_MOUTVOL_SET(x) (((uint16_t)(x) << WM8960_MONO_MOUTVOL_SHIFT) & WM8960_MONO_MOUTVOL_MASK) +#define WM8960_MONO_MOUTVOL_GET(x) (((uint16_t)(x) & WM8960_MONO_MOUTVOL_MASK) >> WM8960_MONO_MOUTVOL_SHIFT) + +/* Bitfield definition for register: INBMIX1 */ +/* + * LIN3BOOST (RW) + * + * LINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX1_LIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX1_LIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN3BOOST_SHIFT) & WM8960_INBMIX1_LIN3BOOST_MASK) +#define WM8960_INBMIX1_LIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN3BOOST_MASK) >> WM8960_INBMIX1_LIN3BOOST_SHIFT) + +/* + * LIN2BOOST (RW) + * + * LINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX1_LIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX1_LIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX1_LIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX1_LIN2BOOST_SHIFT) & WM8960_INBMIX1_LIN2BOOST_MASK) +#define WM8960_INBMIX1_LIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX1_LIN2BOOST_MASK) >> WM8960_INBMIX1_LIN2BOOST_SHIFT) + +/* Bitfield definition for register: INBMIX2 */ +/* + * RIN3BOOST (RW) + * + * RINPUT3 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN3BOOST_MASK (0x70U) +#define WM8960_INBMIX2_RIN3BOOST_SHIFT (4U) +#define WM8960_INBMIX2_RIN3BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN3BOOST_SHIFT) & WM8960_INBMIX2_RIN3BOOST_MASK) +#define WM8960_INBMIX2_RIN3BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN3BOOST_MASK) >> WM8960_INBMIX2_RIN3BOOST_SHIFT) + +/* + * RIN2BOOST (RW) + * + * RINPUT2 to Boost Mixer Gain + * 000 = Mute + * 001 = -12dB + * ...3dB steps up to + * 111 = +6dB + */ +#define WM8960_INBMIX2_RIN2BOOST_MASK (0xEU) +#define WM8960_INBMIX2_RIN2BOOST_SHIFT (1U) +#define WM8960_INBMIX2_RIN2BOOST_SET(x) (((uint16_t)(x) << WM8960_INBMIX2_RIN2BOOST_SHIFT) & WM8960_INBMIX2_RIN2BOOST_MASK) +#define WM8960_INBMIX2_RIN2BOOST_GET(x) (((uint16_t)(x) & WM8960_INBMIX2_RIN2BOOST_MASK) >> WM8960_INBMIX2_RIN2BOOST_SHIFT) + +/* Bitfield definition for register: BYPASS1 */ +/* + * LB2LO (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS1_LB2LO_MASK (0x80U) +#define WM8960_BYPASS1_LB2LO_SHIFT (7U) +#define WM8960_BYPASS1_LB2LO_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LO_SHIFT) & WM8960_BYPASS1_LB2LO_MASK) +#define WM8960_BYPASS1_LB2LO_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LO_MASK) >> WM8960_BYPASS1_LB2LO_SHIFT) + +/* + * LB2LOVOL (RW) + * + * Left Input Boost Mixer to Left Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS1_LB2LOVOL_MASK (0x70U) +#define WM8960_BYPASS1_LB2LOVOL_SHIFT (4U) +#define WM8960_BYPASS1_LB2LOVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS1_LB2LOVOL_SHIFT) & WM8960_BYPASS1_LB2LOVOL_MASK) +#define WM8960_BYPASS1_LB2LOVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS1_LB2LOVOL_MASK) >> WM8960_BYPASS1_LB2LOVOL_SHIFT) + +/* Bitfield definition for register: BYPASS2 */ +/* + * RB2RO (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * 0 = Disable (Mute) + * 1 = Enable Path + */ +#define WM8960_BYPASS2_RB2RO_MASK (0x80U) +#define WM8960_BYPASS2_RB2RO_SHIFT (7U) +#define WM8960_BYPASS2_RB2RO_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2RO_SHIFT) & WM8960_BYPASS2_RB2RO_MASK) +#define WM8960_BYPASS2_RB2RO_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2RO_MASK) >> WM8960_BYPASS2_RB2RO_SHIFT) + +/* + * RB2ROVOL (RW) + * + * Right Input Boost Mixer to Right Output Mixer + * Volume + * 000 = 0dB + * ...(3dB steps) + * 111 = -21dB + */ +#define WM8960_BYPASS2_RB2ROVOL_MASK (0x70U) +#define WM8960_BYPASS2_RB2ROVOL_SHIFT (4U) +#define WM8960_BYPASS2_RB2ROVOL_SET(x) (((uint16_t)(x) << WM8960_BYPASS2_RB2ROVOL_SHIFT) & WM8960_BYPASS2_RB2ROVOL_MASK) +#define WM8960_BYPASS2_RB2ROVOL_GET(x) (((uint16_t)(x) & WM8960_BYPASS2_RB2ROVOL_MASK) >> WM8960_BYPASS2_RB2ROVOL_SHIFT) + +/* Bitfield definition for register: POWER3 */ +/* + * LMIC (RW) + * + * Left Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINL = 1) + */ +#define WM8960_POWER3_LMIC_MASK (0x20U) +#define WM8960_POWER3_LMIC_SHIFT (5U) +#define WM8960_POWER3_LMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_LMIC_SHIFT) & WM8960_POWER3_LMIC_MASK) +#define WM8960_POWER3_LMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_LMIC_MASK) >> WM8960_POWER3_LMIC_SHIFT) + +/* + * RMIC (RW) + * + * Right Channel Input PGA Enable + * 0 = PGA disabled + * 1 = PGA enabled (if AINR = 1) + */ +#define WM8960_POWER3_RMIC_MASK (0x10U) +#define WM8960_POWER3_RMIC_SHIFT (4U) +#define WM8960_POWER3_RMIC_SET(x) (((uint16_t)(x) << WM8960_POWER3_RMIC_SHIFT) & WM8960_POWER3_RMIC_MASK) +#define WM8960_POWER3_RMIC_GET(x) (((uint16_t)(x) & WM8960_POWER3_RMIC_MASK) >> WM8960_POWER3_RMIC_SHIFT) + +/* + * LOMIX (RW) + * + * Left Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_LOMIX_MASK (0x8U) +#define WM8960_POWER3_LOMIX_SHIFT (3U) +#define WM8960_POWER3_LOMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_LOMIX_SHIFT) & WM8960_POWER3_LOMIX_MASK) +#define WM8960_POWER3_LOMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_LOMIX_MASK) >> WM8960_POWER3_LOMIX_SHIFT) + +/* + * ROMIX (RW) + * + * Right Output Mixer Enable Control + * 0 = Disabled + * 1 = Enabled + */ +#define WM8960_POWER3_ROMIX_MASK (0x4U) +#define WM8960_POWER3_ROMIX_SHIFT (2U) +#define WM8960_POWER3_ROMIX_SET(x) (((uint16_t)(x) << WM8960_POWER3_ROMIX_SHIFT) & WM8960_POWER3_ROMIX_MASK) +#define WM8960_POWER3_ROMIX_GET(x) (((uint16_t)(x) & WM8960_POWER3_ROMIX_MASK) >> WM8960_POWER3_ROMIX_SHIFT) + +/* Bitfield definition for register: ADDCTL4 */ +/* + * GPIOPOL (RW) + * + * GPIO Polarity Invert + * 0 = Non inverted + * 1 = Inverted + */ +#define WM8960_ADDCTL4_GPIOPOL_MASK (0x80U) +#define WM8960_ADDCTL4_GPIOPOL_SHIFT (7U) +#define WM8960_ADDCTL4_GPIOPOL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOPOL_SHIFT) & WM8960_ADDCTL4_GPIOPOL_MASK) +#define WM8960_ADDCTL4_GPIOPOL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOPOL_MASK) >> WM8960_ADDCTL4_GPIOPOL_SHIFT) + +/* + * GPIOSEL (RW) + * + * ADCLRC/GPIO1 GPIO Function Select: + * 000 = Jack detect input + * 001 = Reserved + * 010 = Temperature ok + * 011 = Debounced jack detect output + * 100 = SYSCLK output + * 101 = PLL lock + * 110 = Logic 0 + * 111 = Logic 1 + */ +#define WM8960_ADDCTL4_GPIOSEL_MASK (0x70U) +#define WM8960_ADDCTL4_GPIOSEL_SHIFT (4U) +#define WM8960_ADDCTL4_GPIOSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_GPIOSEL_SHIFT) & WM8960_ADDCTL4_GPIOSEL_MASK) +#define WM8960_ADDCTL4_GPIOSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_GPIOSEL_MASK) >> WM8960_ADDCTL4_GPIOSEL_SHIFT) + +/* + * HPSEL (RW) + * + * Headphone Switch Input Select + * 0X = GPIO1 used for jack detect input (Requires + * ADCLRC pin to be configured as a GPIO) + * 10 = JD2 used for jack detect input + * 11 = JD3 used for jack detect input + */ +#define WM8960_ADDCTL4_HPSEL_MASK (0xCU) +#define WM8960_ADDCTL4_HPSEL_SHIFT (2U) +#define WM8960_ADDCTL4_HPSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_HPSEL_SHIFT) & WM8960_ADDCTL4_HPSEL_MASK) +#define WM8960_ADDCTL4_HPSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_HPSEL_MASK) >> WM8960_ADDCTL4_HPSEL_SHIFT) + +/* + * TSENSEN (RW) + * + * Temperature Sensor Enable + * 0 = Temperature sensor disabled + * 1 = Temperature sensor enabled + */ +#define WM8960_ADDCTL4_TSENSEN_MASK (0x2U) +#define WM8960_ADDCTL4_TSENSEN_SHIFT (1U) +#define WM8960_ADDCTL4_TSENSEN_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_TSENSEN_SHIFT) & WM8960_ADDCTL4_TSENSEN_MASK) +#define WM8960_ADDCTL4_TSENSEN_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_TSENSEN_MASK) >> WM8960_ADDCTL4_TSENSEN_SHIFT) + +/* + * MBSEL (RW) + * + * Microphone Bias Voltage Control + * 0 = 0.9 * AVDD + * 1 = 0.65 * AVDD + */ +#define WM8960_ADDCTL4_MBSEL_MASK (0x1U) +#define WM8960_ADDCTL4_MBSEL_SHIFT (0U) +#define WM8960_ADDCTL4_MBSEL_SET(x) (((uint16_t)(x) << WM8960_ADDCTL4_MBSEL_SHIFT) & WM8960_ADDCTL4_MBSEL_MASK) +#define WM8960_ADDCTL4_MBSEL_GET(x) (((uint16_t)(x) & WM8960_ADDCTL4_MBSEL_MASK) >> WM8960_ADDCTL4_MBSEL_SHIFT) + +/* Bitfield definition for register: CLASSD1 */ +/* + * SPK_OP_EN (RW) + * + * Enable Class D Speaker Outputs + * 00 = Off + * 01 = Left speaker only + * 10 = Right speaker only + * 11 = Left and right speakers enabled + */ +#define WM8960_CLASSD1_SPK_OP_EN_MASK (0xC0U) +#define WM8960_CLASSD1_SPK_OP_EN_SHIFT (6U) +#define WM8960_CLASSD1_SPK_OP_EN_SET(x) (((uint16_t)(x) << WM8960_CLASSD1_SPK_OP_EN_SHIFT) & WM8960_CLASSD1_SPK_OP_EN_MASK) +#define WM8960_CLASSD1_SPK_OP_EN_GET(x) (((uint16_t)(x) & WM8960_CLASSD1_SPK_OP_EN_MASK) >> WM8960_CLASSD1_SPK_OP_EN_SHIFT) + +/* Bitfield definition for register: CLASSD3 */ +/* + * DCGAIN (RW) + * + * DC Speaker Boost (Boosts speaker DC output + * level by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_DCGAIN_MASK (0x38U) +#define WM8960_CLASSD3_DCGAIN_SHIFT (3U) +#define WM8960_CLASSD3_DCGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_DCGAIN_SHIFT) & WM8960_CLASSD3_DCGAIN_MASK) +#define WM8960_CLASSD3_DCGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_DCGAIN_MASK) >> WM8960_CLASSD3_DCGAIN_SHIFT) + +/* + * ACGAIN (RW) + * + * AC Speaker Boost (Boosts speaker AC output + * signal by up to 1.8 x on left and right channels) + * 000 = 1.00x boost (+0dB) + * 001 = 1.27x boost (+2.1dB) + * 010 = 1.40x boost (+2.9dB) + * 011 = 1.52x boost (+3.6dB) + * 100 = 1.67x boost (+4.5dB) + * 101 = 1.8x boost (+5.1dB) + * 110 to 111 = Reserved + */ +#define WM8960_CLASSD3_ACGAIN_MASK (0x7U) +#define WM8960_CLASSD3_ACGAIN_SHIFT (0U) +#define WM8960_CLASSD3_ACGAIN_SET(x) (((uint16_t)(x) << WM8960_CLASSD3_ACGAIN_SHIFT) & WM8960_CLASSD3_ACGAIN_MASK) +#define WM8960_CLASSD3_ACGAIN_GET(x) (((uint16_t)(x) & WM8960_CLASSD3_ACGAIN_MASK) >> WM8960_CLASSD3_ACGAIN_SHIFT) + +/* Bitfield definition for register: PLL1 */ +/* + * OPCLKDIV (RW) + * + * SYSCLK Output to GPIO Clock Division ratio + * 000 = SYSCLK + * 001 = SYSCLK / 2 + * 010 = SYSCLK / 3 + * 011 = SYSCLK / 4 + * 100 = SYSCLK / 5.5 + * 101 = SYSCLK / 6 + */ +#define WM8960_PLL1_OPCLKDIV_MASK (0x1C0U) +#define WM8960_PLL1_OPCLKDIV_SHIFT (6U) +#define WM8960_PLL1_OPCLKDIV_SET(x) (((uint16_t)(x) << WM8960_PLL1_OPCLKDIV_SHIFT) & WM8960_PLL1_OPCLKDIV_MASK) +#define WM8960_PLL1_OPCLKDIV_GET(x) (((uint16_t)(x) & WM8960_PLL1_OPCLKDIV_MASK) >> WM8960_PLL1_OPCLKDIV_SHIFT) + +/* + * SDM (RW) + * + * Enable Integer Mode + * 0 = Integer mode + * 1 = Fractional mode + */ +#define WM8960_PLL1_SDM_MASK (0x20U) +#define WM8960_PLL1_SDM_SHIFT (5U) +#define WM8960_PLL1_SDM_SET(x) (((uint16_t)(x) << WM8960_PLL1_SDM_SHIFT) & WM8960_PLL1_SDM_MASK) +#define WM8960_PLL1_SDM_GET(x) (((uint16_t)(x) & WM8960_PLL1_SDM_MASK) >> WM8960_PLL1_SDM_SHIFT) + +/* + * PLLPRESCALE (RW) + * + * Divide MCLK by 2 before input to PLL + * 0 = Divide by 1 + * 1 = Divide by 2 + */ +#define WM8960_PLL1_PLLPRESCALE_MASK (0x10U) +#define WM8960_PLL1_PLLPRESCALE_SHIFT (4U) +#define WM8960_PLL1_PLLPRESCALE_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLPRESCALE_SHIFT) & WM8960_PLL1_PLLPRESCALE_MASK) +#define WM8960_PLL1_PLLPRESCALE_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLPRESCALE_MASK) >> WM8960_PLL1_PLLPRESCALE_SHIFT) + +/* + * PLLN (RW) + * + * Integer (N) part of PLL input/output frequency + * ratio. Use values greater than 5 and less than 13 + */ +#define WM8960_PLL1_PLLN_MASK (0xFU) +#define WM8960_PLL1_PLLN_SHIFT (0U) +#define WM8960_PLL1_PLLN_SET(x) (((uint16_t)(x) << WM8960_PLL1_PLLN_SHIFT) & WM8960_PLL1_PLLN_MASK) +#define WM8960_PLL1_PLLN_GET(x) (((uint16_t)(x) & WM8960_PLL1_PLLN_MASK) >> WM8960_PLL1_PLLN_SHIFT) + +/* Bitfield definition for register: PLL2 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL2_PLLK_MASK (0xFFU) +#define WM8960_PLL2_PLLK_SHIFT (0U) +#define WM8960_PLL2_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL2_PLLK_SHIFT) & WM8960_PLL2_PLLK_MASK) +#define WM8960_PLL2_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL2_PLLK_MASK) >> WM8960_PLL2_PLLK_SHIFT) + +/* Bitfield definition for register: PLL3 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL3_PLLK_MASK (0xFFU) +#define WM8960_PLL3_PLLK_SHIFT (0U) +#define WM8960_PLL3_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL3_PLLK_SHIFT) & WM8960_PLL3_PLLK_MASK) +#define WM8960_PLL3_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL3_PLLK_MASK) >> WM8960_PLL3_PLLK_SHIFT) + +/* Bitfield definition for register: PLL4 */ +/* + * PLLK (RW) + * + * Fractional (K) part of PLL1 input/output + * frequency ratio (treat as one 24-digit binary number). + */ +#define WM8960_PLL4_PLLK_MASK (0xFFU) +#define WM8960_PLL4_PLLK_SHIFT (0U) +#define WM8960_PLL4_PLLK_SET(x) (((uint16_t)(x) << WM8960_PLL4_PLLK_SHIFT) & WM8960_PLL4_PLLK_MASK) +#define WM8960_PLL4_PLLK_GET(x) (((uint16_t)(x) & WM8960_PLL4_PLLK_MASK) >> WM8960_PLL4_PLLK_SHIFT) + + +#endif /* _HPM_WM8960_REG_H_ */ diff --git a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld new file mode 100644 index 00000000000..8dc4e5efc8d --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt.ld @@ -0,0 +1,335 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01200000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 128K + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); + +} diff --git a/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt_enet.ld b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt_enet.ld new file mode 100644 index 00000000000..5790d33157a --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/flash_rtt_enet.ld @@ -0,0 +1,355 @@ +/* + * Copyright 2021-2025 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + */ + +ENTRY(_start) + +STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; +FLASH_SIZE = DEFINED(_flash_size) ? _flash_size : 1M; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; + +MEMORY +{ + XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = FLASH_SIZE + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01200000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 128K + AHB_SRAM (w): ORIGIN = 0xF0200000, LENGTH = 32k +} + +__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; +__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; +__app_load_addr__ = ORIGIN(XPI0) + 0x3000; +__boot_header_length__ = __boot_header_end__ - __boot_header_start__; +__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; + +SECTIONS +{ + .nor_cfg_option __nor_cfg_option_load_addr__ : { + KEEP(*(.nor_cfg_option)) + } > XPI0 + + .boot_header __boot_header_load_addr__ : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > XPI0 + + .start __app_load_addr__ : { + . = ALIGN(8); + KEEP(*(.start)) + . = ALIGN(16); + } > XPI0 + + __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); + .vectors : AT(__vector_load_addr__) { + . = ALIGN(16); + __vector_ram_start__ = .; + KEEP(*(.vector_table)) + KEEP(*(.isr_vector)) + + . = ALIGN(16); + __vector_ram_end__ = .; + } > ILM + + .fast : AT(__fast_load_addr__) { + . = ALIGN(16); + __ramfunc_start__ = .; + *(.fast) + *(.fast.*) + . = ALIGN(16); + + /* RT-Thread Core Start */ + KEEP(*context_gcc.o(.text* .rodata*)) + KEEP(*port*.o (.text .text* .rodata .rodata*)) + KEEP(*interrupt_gcc.o (.text .text* .rodata .rodata*)) + KEEP(*trap_common.o (.text .text* .rodata .rodata*)) + KEEP(*irq.o (.text .text* .rodata .rodata*)) + KEEP(*clock.o (.text .text* .rodata .rodata*)) + KEEP(*kservice.o (.text .text* .rodata .rodata*)) + KEEP(*scheduler*.o (.text .text* .rodata .rodata*)) + KEEP(*trap*.o (.text .text* .rodata .rodata*)) + KEEP(*idle.o (.text .text* .rodata .rodata*)) + KEEP(*ipc.o (.text .text* .rodata .rodata*)) + KEEP(*slab.o (.text .text* .rodata .rodata*)) + KEEP(*thread.o (.text .text* .rodata .rodata*)) + KEEP(*object.o (.text .text* .rodata .rodata*)) + KEEP(*timer.o (.text .text* .rodata .rodata*)) + KEEP(*mem.o (.text .text* .rodata .rodata*)) + KEEP(*memheap.o (.text .text* .rodata .rodata*)) + KEEP(*mempool.o (.text .text* .rodata .rodata*)) + /* RT-Thread Core End */ + + /* HPMicro Driver Wrapper */ + KEEP(*drv_*.o (.text .text* .rodata .rodata*)) + KEEP(*api_lib*.o (.text .text* .rodata .rodata*)) + KEEP(*api_msg*.o (.text .text* .rodata .rodata*)) + KEEP(*if_api*.o (.text .text* .rodata .rodata*)) + KEEP(*netbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*netdb*.o (.text .text* .rodata .rodata*)) + KEEP(*netifapi*.o (.text .text* .rodata .rodata*)) + KEEP(*sockets*.o (.text .text* .rodata .rodata*)) + KEEP(*tcpip*.o (.text .text* .rodata .rodata*)) + KEEP(*inet_chksum*.o (.text .text* .rodata .rodata*)) + KEEP(*memp*.o (.text .text* .rodata .rodata*)) + KEEP(*netif*.o (.text .text* .rodata .rodata*)) + KEEP(*pbuf*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_in*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp_out*.o (.text .text* .rodata .rodata*)) + KEEP(*tcp*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernet*.o (.text .text* .rodata .rodata*)) + KEEP(*ethernetif*.o (.text .text* .rodata .rodata*)) + + . = ALIGN(16); + __ramfunc_end__ = .; + } > ILM + + .text (__vector_load_addr__ + SIZEOF(.vectors)) : { + . = ALIGN(16); + *(.text) + *(.text*) + *(.rodata) + *(.rodata*) + *(.srodata) + *(.srodata*) + + *(.hash) + *(.dyn*) + *(.gnu*) + *(.pl*) + + KEEP(*(.eh_frame)) + *(.eh_frame*) + + KEEP (*(.init)) + KEEP (*(.fini)) + . = ALIGN(8); + + /********************************************* + * + * RT-Thread related sections - Start + * + *********************************************/ + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section information for modules */ + . = ALIGN(4); + __rtmsymtab_start = .; + KEEP(*(RTMSymTab)) + __rtmsymtab_end = .; + + /* RT-Thread related sections - end */ + + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + } > XPI0 + + + .eh_frame : + { + __eh_frame_start = .; + KEEP(*(.eh_frame)) + __eh_frame_end = .; + } > XPI0 + + .eh_frame_hdr : + { + KEEP(*(.eh_frame_hdr)) + } > XPI0 + __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; + __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; + + .rel : { + KEEP(*(.rel*)) + } > XPI0 + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .fast_ram (NOLOAD) : { + KEEP(*(.fast_ram)) + } > DLM + + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + + .bss(NOLOAD) : { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss*) + *(.sbss*) + *(.scommon) + *(.scommon*) + *(.dynsbss*) + *(COMMON) + . = ALIGN(8); + _end = .; + __bss_end__ = .; + } > AXI_SRAM + + /* Note: the .tbss and .tdata section should be adjacent */ + .tbss(NOLOAD) : { + . = ALIGN(8); + __tbss_start__ = .; + *(.tbss*) + *(.gnu.linkonce.tb.*) + *(.tcommon*) + _end = .; + __tbss_end__ = .; + } > AXI_SRAM + + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { + . = ALIGN(8); + __tdata_start__ = .; + __thread_pointer = .; + *(.tdata) + *(.tdata*) + *(.gnu.linkonce.td.*) + . = ALIGN(8); + __tdata_end__ = .; + } > AXI_SRAM + + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { + . = ALIGN(8); + __data_start__ = .; + __global_pointer$ = . + 0x800; + *(.data) + *(.data*) + *(.sdata) + *(.sdata*) + + KEEP(*(.jcr)) + KEEP(*(.dynamic)) + KEEP(*(.got*)) + KEEP(*(.got)) + KEEP(*(.gcc_except_table)) + KEEP(*(.gcc_except_table.*)) + + . = ALIGN(8); + PROVIDE(__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE(__preinit_array_end = .); + + . = ALIGN(8); + PROVIDE(__init_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + + . = ALIGN(8); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); + + . = ALIGN(8); + PROVIDE(__ctors_start__ = .); + KEEP(*crtbegin*.o(.ctors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) + KEEP(*(SORT(.ctors.*))) + KEEP(*(.ctors)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(8); + KEEP(*crtbegin*.o(.dtors)) + KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + . = ALIGN(8); + __data_end__ = .; + PROVIDE (__edata = .); + PROVIDE (_edata = .); + PROVIDE (edata = .); + } > AXI_SRAM + __fast_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata); + + __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init) + SIZEOF(.eh_frame) + SIZEOF(.eh_frame_hdr); + + + + .heap(NOLOAD) : { + . = ALIGN(8); + __heap_start__ = .; + . += HEAP_SIZE; + __heap_end__ = .; + } > AXI_SRAM + + .framebuffer (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.framebuffer)) + . = ALIGN(8); + } > AXI_SRAM + + .stack(NOLOAD) : { + . = ALIGN(8); + __stack_base__ = .; + . += STACK_SIZE; + . = ALIGN(8); + PROVIDE (_stack = .); + PROVIDE (_stack_in_dlm = .); + PROVIDE( __rt_rvstack = . ); + } > AXI_SRAM + + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { + . = ALIGN(8); + __noncacheable_init_start__ = .; + KEEP(*(.noncacheable.init)) + __noncacheable_init_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .noncacheable.bss (NOLOAD) : { + . = ALIGN(8); + KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) + __noncacheable_bss_start__ = .; + KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) + __noncacheable_bss_end__ = .; + . = ALIGN(8); + } > NONCACHEABLE_RAM + + .ahb_sram (NOLOAD) : { + KEEP(*(.ahb_sram)) + } > AHB_SRAM + + __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); + __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); +} diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld similarity index 77% rename from bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld rename to bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld index 7d022d2db74..717bb058274 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/ram_rtt.ld +++ b/bsp/hpmicro/hpm6p00evk/board/linker_scripts/gcc/ram_rtt.ld @@ -1,24 +1,21 @@ /* - * Copyright 2021-2023 HPMicro + * Copyright 2021-2025 HPMicro * SPDX-License-Identifier: BSD-3-Clause */ ENTRY(_start) STACK_SIZE = DEFINED(_stack_size) ? _stack_size : 0x4000; -HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 256K; -SDRAM_SIZE = DEFINED(_sdram_size) ? _sdram_size : 32M; -NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 256K; +HEAP_SIZE = DEFINED(_heap_size) ? _heap_size : 32K; +NONCACHEABLE_SIZE = DEFINED(_noncacheable_size) ? _noncacheable_size : 128K; MEMORY { - ILM (wx) : ORIGIN = 0, LENGTH = 256K - DLM (w) : ORIGIN = 0x80000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 1280K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x11C0000, LENGTH = NONCACHEABLE_SIZE - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = SDRAM_SIZE - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k + ILM (wx) : ORIGIN = 0, LENGTH = 128K + DLM (w) : ORIGIN = 0x00200000, LENGTH = 128K + NONCACHEABLE_RAM (wx) : ORIGIN = 0x01200000, LENGTH = NONCACHEABLE_SIZE + AXI_SRAM (wx) : ORIGIN = 0x01220000, LENGTH = 128K + AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k } SECTIONS @@ -26,14 +23,14 @@ SECTIONS .start : { . = ALIGN(8); KEEP(*(.start)) - } > AXI_SRAM + } > ILM .vectors : { . = ALIGN(8); KEEP(*(.isr_vector)) KEEP(*(.vector_table)) . = ALIGN(8); - } > AXI_SRAM + } > ILM .text : { . = ALIGN(8); @@ -87,7 +84,6 @@ SECTIONS /* RT-Thread related sections - end */ - /* section information for usbh class */ . = ALIGN(8); __usbh_class_info_start__ = .; @@ -97,7 +93,7 @@ SECTIONS PROVIDE (__etext = .); PROVIDE (_etext = .); PROVIDE (etext = .); - } > AXI_SRAM + } > ILM .rel : { KEEP(*(.rel*)) @@ -107,6 +103,16 @@ SECTIONS KEEP(*(.fast_ram)) } > DLM + __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); + .fast_ram.init : AT(__fast_ram_init_load_addr__) { + . = ALIGN(8); + __fast_ram_init_start__ = .; + KEEP(*(.fast_ram.init)) + KEEP(*(.fast_ram.init.*)) + __fast_ram_init_end__ = .; + . = ALIGN(8); + } > DLM + .bss(NOLOAD) : { . = ALIGN(8); __bss_start__ = .; @@ -127,22 +133,26 @@ SECTIONS . = ALIGN(8); __tbss_start__ = .; *(.tbss*) + *(.gnu.linkonce.tb.*) *(.tcommon*) _end = .; __tbss_end__ = .; } > DLM - .tdata : AT(etext) { + __tdata_load_addr__ = etext; + .tdata : AT(__tdata_load_addr__) { . = ALIGN(8); __tdata_start__ = .; __thread_pointer = .; *(.tdata) *(.tdata*) + *(.gnu.linkonce.td.*) . = ALIGN(8); __tdata_end__ = .; } > DLM - .data : AT(etext + __tdata_end__ - __tdata_start__) { + __data_load_addr__ = etext + SIZEOF(.tdata); + .data : AT(__data_load_addr__) { . = ALIGN(8); __data_start__ = .; __global_pointer$ = . + 0x800; @@ -170,10 +180,10 @@ SECTIONS PROVIDE(__init_array_end = .); . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); + PROVIDE(__fini_array_start = .); + KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE(__fini_array_end = .); . = ALIGN(8); PROVIDE(__ctors_start__ = .); @@ -196,7 +206,8 @@ SECTIONS PROVIDE (edata = .); } > DLM - .fast : AT(etext + __data_end__ - __tdata_start__) { + __fast_load_addr__ = etext + SIZEOF(.tdata) + SIZEOF(.data); + .fast : AT(__fast_load_addr__) { . = ALIGN(8); PROVIDE(__ramfunc_start__ = .); *(.fast) @@ -204,7 +215,8 @@ SECTIONS PROVIDE(__ramfunc_end__ = .); } > AXI_SRAM - .noncacheable.init : AT(etext + __data_end__ - __tdata_start__ + __ramfunc_end__ - __ramfunc_start__) { + __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.tdata) + SIZEOF(.fast); + .noncacheable.init : AT(__noncacheable_init_load_addr__) { . = ALIGN(8); __noncacheable_init_start__ = .; KEEP(*(.noncacheable.init)) @@ -215,8 +227,11 @@ SECTIONS .noncacheable.bss (NOLOAD) : { . = ALIGN(8); KEEP(*(.noncacheable)) + KEEP(*(.noncacheable.non_init)) + KEEP(*(.noncacheable.non_init.*)) __noncacheable_bss_start__ = .; KEEP(*(.noncacheable.bss)) + KEEP(*(.noncacheable.bss.*)) __noncacheable_bss_end__ = .; . = ALIGN(8); } > NONCACHEABLE_RAM @@ -228,10 +243,6 @@ SECTIONS KEEP(*(.ahb_sram)) } > AHB_SRAM - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - .stack(NOLOAD) : { . = ALIGN(8); __stack_base__ = .; @@ -253,10 +264,4 @@ SECTIONS } > AXI_SRAM - .sdram (NOLOAD) : { - . = ALIGN(8); - __sdram_start__ = .; - . += SDRAM_SIZE; - __sdram_end__ = .; - } > SDRAM } diff --git a/bsp/hpmicro/hpm6p00evk/board/pinmux.c b/bsp/hpmicro/hpm6p00evk/board/pinmux.c new file mode 100644 index 00000000000..00da125e993 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/pinmux.c @@ -0,0 +1,559 @@ +/* + * Copyright (c) 2024 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +/* + * Note: + * PY and PZ IOs: if any SOC pin function needs to be routed to these IOs, + * besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that + * expected SoC function can be enabled on these IOs. + * + */ +#include "board.h" + +void init_uart_pins(UART_Type *ptr) +{ + if (ptr == HPM_UART0) { + HPM_IOC->PAD[IOC_PAD_PA00].FUNC_CTL = IOC_PA00_FUNC_CTL_UART0_TXD; + HPM_IOC->PAD[IOC_PAD_PA01].FUNC_CTL = IOC_PA01_FUNC_CTL_UART0_RXD; + } else if (ptr == HPM_UART4) { + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_PY_00; + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_UART4_TXD; + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PY01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_PY_01; + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_UART4_RXD; + } else if (ptr == HPM_PUART) { + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_PURT_TXD; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_PURT_RXD; + } else { + ; + } +} + +/* for uart_lin case, need to configure pin as gpio to sent break signal */ +void init_uart_pin_as_gpio(UART_Type *ptr) +{ + if (ptr == BOARD_UART_LIN) { + /* pull-up */ + HPM_IOC->PAD[IOC_PAD_PY00].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY01].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_PY_00; + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_GPIO_Y_00; + + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_PY_01; + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_GPIO_Y_01; + } +} + +void init_i2c_pins(I2C_Type *ptr) +{ + if (ptr == HPM_I2C3) { /* Codec */ + HPM_IOC->PAD[IOC_PAD_PB07].FUNC_CTL = IOC_PB07_FUNC_CTL_I2C3_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PB06].FUNC_CTL = IOC_PB06_FUNC_CTL_I2C3_SDA; + HPM_IOC->PAD[IOC_PAD_PB07].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PB06].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else if (ptr == HPM_I2C1) { + HPM_IOC->PAD[IOC_PAD_PC29].FUNC_CTL = IOC_PC29_FUNC_CTL_I2C1_SCL | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PC28].FUNC_CTL = IOC_PC28_FUNC_CTL_I2C1_SDA; + HPM_IOC->PAD[IOC_PAD_PC29].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + HPM_IOC->PAD[IOC_PAD_PC28].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK; + } else { + ; + } +} + +void init_femc_pins(void) +{ + uint32_t pad_ctl; + + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_FEMC_A_00; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_FEMC_A_01; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_FEMC_A_02; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_FEMC_A_03; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_FEMC_A_04; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_FEMC_A_05; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_FEMC_A_06; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_FEMC_A_07; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_FEMC_A_08; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_FEMC_A_09; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_FEMC_A_10; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_FEMC_A_11; /* SRAM: NWE */ + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_FEMC_A_12; /* SRAM: NOE */ + + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_FEMC_DQ_00; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_FEMC_DQ_01; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_FEMC_DQ_02; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_FEMC_DQ_03; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_FEMC_DQ_04; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_FEMC_DQ_05; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_FEMC_DQ_06; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_FEMC_DQ_07; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_FEMC_DQ_08; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_FEMC_DQ_09; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_FEMC_DQ_10; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_FEMC_DQ_11; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_FEMC_DQ_12; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_FEMC_DQ_13; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_FEMC_DQ_14; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_FEMC_DQ_15; + + /* Improve DQ pins driver strength */ + pad_ctl = IOC_PAD_PAD_CTL_SR_SET(1) | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_DS_SET(4); + HPM_IOC->PAD[IOC_PAD_PC12].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC13].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC14].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC15].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC16].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC17].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC18].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC19].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC04].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC05].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC06].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC07].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC08].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC09].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC10].PAD_CTL = pad_ctl; + HPM_IOC->PAD[IOC_PAD_PC11].PAD_CTL = pad_ctl; + + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_FEMC_DM_0; /* SRAM: NLB */ + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_FEMC_DM_1; /* SRAM: NUB */ + + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_FEMC_BA0; + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_FEMC_BA1; /* SRAM: NADV */ + + /* SDRAM */ + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_FEMC_CS_0; +/* HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_FEMC_CS_1; */ /* JTAG */ /* SRAM: CS0 */ + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_FEMC_CAS; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_FEMC_RAS; + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_FEMC_CKE; + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_FEMC_CLK_0; + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_FEMC_WE; + + HPM_IOC->PAD[IOC_PAD_PB28].FUNC_CTL = IOC_PB28_FUNC_CTL_FEMC_DQS | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + + /* SRAM */ +/* HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_FEMC_SCLK_0; */ /* JTAG */ + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_FEMC_SCLK_1; +/* HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_FEMC_SCS_0; */ /* JTAG */ /* SRAM: CS1 */ + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_FEMC_SCS_1; /* SRAM: CS2 */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_FEMC_SRDY; +} + +void init_ppi_pins(void) +{ + /* DQ */ + HPM_IOC->PAD[IOC_PAD_PC12].FUNC_CTL = IOC_PC12_FUNC_CTL_PPI0_DQ_00; + HPM_IOC->PAD[IOC_PAD_PC13].FUNC_CTL = IOC_PC13_FUNC_CTL_PPI0_DQ_01; + HPM_IOC->PAD[IOC_PAD_PC14].FUNC_CTL = IOC_PC14_FUNC_CTL_PPI0_DQ_02; + HPM_IOC->PAD[IOC_PAD_PC15].FUNC_CTL = IOC_PC15_FUNC_CTL_PPI0_DQ_03; + HPM_IOC->PAD[IOC_PAD_PC16].FUNC_CTL = IOC_PC16_FUNC_CTL_PPI0_DQ_04; + HPM_IOC->PAD[IOC_PAD_PC17].FUNC_CTL = IOC_PC17_FUNC_CTL_PPI0_DQ_05; + HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_PPI0_DQ_06; + HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_PPI0_DQ_07; + HPM_IOC->PAD[IOC_PAD_PC04].FUNC_CTL = IOC_PC04_FUNC_CTL_PPI0_DQ_08; + HPM_IOC->PAD[IOC_PAD_PC05].FUNC_CTL = IOC_PC05_FUNC_CTL_PPI0_DQ_09; + HPM_IOC->PAD[IOC_PAD_PC06].FUNC_CTL = IOC_PC06_FUNC_CTL_PPI0_DQ_10; + HPM_IOC->PAD[IOC_PAD_PC07].FUNC_CTL = IOC_PC07_FUNC_CTL_PPI0_DQ_11; + HPM_IOC->PAD[IOC_PAD_PC08].FUNC_CTL = IOC_PC08_FUNC_CTL_PPI0_DQ_12; + HPM_IOC->PAD[IOC_PAD_PC09].FUNC_CTL = IOC_PC09_FUNC_CTL_PPI0_DQ_13; + HPM_IOC->PAD[IOC_PAD_PC10].FUNC_CTL = IOC_PC10_FUNC_CTL_PPI0_DQ_14; + HPM_IOC->PAD[IOC_PAD_PC11].FUNC_CTL = IOC_PC11_FUNC_CTL_PPI0_DQ_15; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_PPI0_DQ_16; + HPM_IOC->PAD[IOC_PAD_PB01].FUNC_CTL = IOC_PB01_FUNC_CTL_PPI0_DQ_17; + HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_PPI0_DQ_18; + HPM_IOC->PAD[IOC_PAD_PB03].FUNC_CTL = IOC_PB03_FUNC_CTL_PPI0_DQ_19; + HPM_IOC->PAD[IOC_PAD_PB04].FUNC_CTL = IOC_PB04_FUNC_CTL_PPI0_DQ_20; + HPM_IOC->PAD[IOC_PAD_PB05].FUNC_CTL = IOC_PB05_FUNC_CTL_PPI0_DQ_21; + HPM_IOC->PAD[IOC_PAD_PB12].FUNC_CTL = IOC_PB12_FUNC_CTL_PPI0_DQ_22; + HPM_IOC->PAD[IOC_PAD_PB13].FUNC_CTL = IOC_PB13_FUNC_CTL_PPI0_DQ_23; + HPM_IOC->PAD[IOC_PAD_PB14].FUNC_CTL = IOC_PB14_FUNC_CTL_PPI0_DQ_24; + HPM_IOC->PAD[IOC_PAD_PB15].FUNC_CTL = IOC_PB15_FUNC_CTL_PPI0_DQ_25; + HPM_IOC->PAD[IOC_PAD_PA15].FUNC_CTL = IOC_PA15_FUNC_CTL_PPI0_DQ_26; + HPM_IOC->PAD[IOC_PAD_PB16].FUNC_CTL = IOC_PB16_FUNC_CTL_PPI0_DQ_27; + HPM_IOC->PAD[IOC_PAD_PB17].FUNC_CTL = IOC_PB17_FUNC_CTL_PPI0_DQ_28; +/* HPM_IOC->PAD[IOC_PAD_PA06].FUNC_CTL = IOC_PA06_FUNC_CTL_PPI0_DQ_29; */ /* JTAG */ +/* HPM_IOC->PAD[IOC_PAD_PA07].FUNC_CTL = IOC_PA07_FUNC_CTL_PPI0_DQ_30; */ /* JTAG */ + HPM_IOC->PAD[IOC_PAD_PB18].FUNC_CTL = IOC_PB18_FUNC_CTL_PPI0_DQ_31; + + /* DM */ + HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_PPI0_DM_0; + HPM_IOC->PAD[IOC_PAD_PC03].FUNC_CTL = IOC_PC03_FUNC_CTL_PPI0_DM_1; + HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_PPI0_DM_2; + HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_PPI0_DM_3; + + /* CS */ + HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = IOC_PA12_FUNC_CTL_PPI0_CS_0; +/* HPM_IOC->PAD[IOC_PAD_PA08].FUNC_CTL = IOC_PA08_FUNC_CTL_PPI0_CS_1; */ /* JTAG */ + HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PA14_FUNC_CTL_PPI0_CS_2; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_PPI0_CS_3; + + /* CTRL */ + HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_PPI0_CTR_0; + HPM_IOC->PAD[IOC_PAD_PB20].FUNC_CTL = IOC_PB20_FUNC_CTL_PPI0_CTR_1; + HPM_IOC->PAD[IOC_PAD_PA09].FUNC_CTL = IOC_PA09_FUNC_CTL_PPI0_CTR_2; + HPM_IOC->PAD[IOC_PAD_PA13].FUNC_CTL = IOC_PA13_FUNC_CTL_PPI0_CTR_3; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_PPI0_CTR_4; + HPM_IOC->PAD[IOC_PAD_PB27].FUNC_CTL = IOC_PB27_FUNC_CTL_PPI0_CTR_5; + HPM_IOC->PAD[IOC_PAD_PB26].FUNC_CTL = IOC_PB26_FUNC_CTL_PPI0_CTR_6; + HPM_IOC->PAD[IOC_PAD_PB25].FUNC_CTL = IOC_PB25_FUNC_CTL_PPI0_CTR_7; + + /* CLK */ + HPM_IOC->PAD[IOC_PAD_PB19].FUNC_CTL = IOC_PB19_FUNC_CTL_PPI0_CLK; +} + +void init_sdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_SDM0_CLK_0; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_SDM0_DAT_0; +} + +/* board PWM provide clock to SDM sensor */ +void init_pwm_pin_as_sdm_clock(void) +{ + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_PWM0_P_2; +} + +void init_gpio_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; + HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_HYS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_butn_pins(void) +{ + /* configure pad setting: pull enable and pull up, schmitt trigger enable */ + /* enable schmitt trigger to eliminate jitter of pin used as button */ + + /* Button */ + HPM_IOC->PAD[IOC_PAD_PC23].FUNC_CTL = IOC_PC23_FUNC_CTL_GPIO_C_23; + HPM_IOC->PAD[IOC_PAD_PC23].PAD_CTL = IOC_PAD_PAD_CTL_HYS_SET(1) | IOC_PAD_PAD_CTL_OD_SET(1); +} + +void init_spi_pins(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SPI2_CS_0; + HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SPI2_MOSI; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_SOC_PY_04; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PY05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PY06].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PY07].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + } +} + +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr) +{ + if (ptr == HPM_SPI2) { + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; + HPM_IOC->PAD[IOC_PAD_PY04].FUNC_CTL = IOC_PY04_FUNC_CTL_SPI2_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK; + HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SPI2_MISO; + HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SPI2_MOSI; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05; + HPM_PIOC->PAD[IOC_PAD_PY04].FUNC_CTL = PIOC_PY04_FUNC_CTL_SOC_PY_04; + HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = PIOC_PY06_FUNC_CTL_SOC_PY_06; + HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = PIOC_PY07_FUNC_CTL_SOC_PY_07; + + /* set max frequency slew rate(200M) */ + HPM_IOC->PAD[IOC_PAD_PY05].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1) | IOC_PAD_PAD_CTL_PRS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY04].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PY06].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + HPM_IOC->PAD[IOC_PAD_PY07].PAD_CTL = IOC_PAD_PAD_CTL_SR_MASK | IOC_PAD_PAD_CTL_SPD_SET(3); + } +} + +void init_gptmr_pins(GPTMR_Type *ptr) +{ + if (ptr == HPM_GPTMR0) { + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_GPTMR0_COMP_2; + } else if (ptr == HPM_GPTMR3) { + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_GPTMR3_COMP_0; + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_GPTMR3_CAPT_0; + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_PY_00; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_PY_01; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_GPTMR3_COMP_2; + } +} + +void init_hall_trgm_pins(void) +{ + init_qeiv2_uvw_pins(BOARD_BLDC_QEIV2_BASE); +} + +void init_qei_trgm_pins(void) +{ + init_qeiv2_ab_pins(BOARD_BLDC_QEIV2_BASE); +} + +void init_acmp_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* CMP4_INN6/CMP5_INN6/CMP6_INN6/CMP7_INN6 */ +} + +void init_pwm_fault_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_TRGM_P_02; +} + +void init_pwm_pins(PWMV2_Type *ptr) +{ + if (ptr == HPM_PWM1) { + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_PWM1_P_0; + HPM_IOC->PAD[IOC_PAD_PD09].FUNC_CTL = IOC_PD09_FUNC_CTL_PWM1_P_1; + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_PWM1_P_2; + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_PWM1_P_3; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_PWM1_P_4; + HPM_IOC->PAD[IOC_PAD_PD13].FUNC_CTL = IOC_PD13_FUNC_CTL_PWM1_P_5; + } +} + +void init_usb_pins(USB_Type *ptr) +{ + if (ptr == HPM_USB0) { + /* USB0_P */ + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* USB0_N */ + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + /* USB0_ID */ + HPM_IOC->PAD[IOC_PAD_PC25].FUNC_CTL = IOC_PC25_FUNC_CTL_USB0_ID; + /* USB0_OC */ + HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_USB0_OC; + /* USB0_PWR */ + HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_USB0_PWR; + } +} + +void init_clk_obs_pins(void) +{ + /* HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0; */ +} + +void init_i2s_pins(I2S_Type *ptr) +{ + if (ptr == HPM_I2S0) { + HPM_IOC->PAD[IOC_PAD_PA20].FUNC_CTL = IOC_PA20_FUNC_CTL_I2S0_MCLK; + HPM_IOC->PAD[IOC_PAD_PA21].FUNC_CTL = IOC_PA21_FUNC_CTL_I2S0_BCLK; + HPM_IOC->PAD[IOC_PAD_PA22].FUNC_CTL = IOC_PA22_FUNC_CTL_I2S0_FCLK; + HPM_IOC->PAD[IOC_PAD_PB00].FUNC_CTL = IOC_PB00_FUNC_CTL_I2S0_TXD_3; + HPM_IOC->PAD[IOC_PAD_PA23].FUNC_CTL = IOC_PA23_FUNC_CTL_I2S0_RXD_0; + } else { + ; + } +} + +void init_qeo_pins(QEOV2_Type *ptr) +{ + if (ptr == HPM_QEO1) { + HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL = IOC_PC00_FUNC_CTL_QEO1_A; + HPM_IOC->PAD[IOC_PAD_PC01].FUNC_CTL = IOC_PC01_FUNC_CTL_QEO1_B; + HPM_IOC->PAD[IOC_PAD_PC02].FUNC_CTL = IOC_PC02_FUNC_CTL_QEO1_Z; + } +} + +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx) +{ + if (ptr == HPM_SEI) { + if (sei_ctrl_idx == SEI_CTRL_1) { + HPM_IOC->PAD[IOC_PAD_PB08].FUNC_CTL = IOC_PB08_FUNC_CTL_SEI1_TX; + HPM_IOC->PAD[IOC_PAD_PB09].FUNC_CTL = IOC_PB09_FUNC_CTL_SEI1_RX; + HPM_IOC->PAD[IOC_PAD_PB10].FUNC_CTL = IOC_PB10_FUNC_CTL_SEI1_DE; + HPM_IOC->PAD[IOC_PAD_PB11].FUNC_CTL = IOC_PB11_FUNC_CTL_SEI1_CK; + } + } +} + +void init_qeiv2_uvw_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_QEI0_B; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_QEI0_Z; + } +} + +void init_qeiv2_ab_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_QEI0_B; + } +} + +void init_qeiv2_abz_pins(QEIV2_Type *ptr) +{ + if (ptr == HPM_QEI0) { + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_QEI0_A; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_QEI0_B; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_QEI0_Z; + } +} + +void init_rdc_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PA17].FUNC_CTL = IOC_PA17_FUNC_CTL_RDC0_PWM_P; + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; +} + +void init_dao_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PY03].FUNC_CTL = IOC_PY03_FUNC_CTL_DAO_RP; + HPM_IOC->PAD[IOC_PAD_PY02].FUNC_CTL = IOC_PY02_FUNC_CTL_DAO_RN; + HPM_PIOC->PAD[IOC_PAD_PY03].FUNC_CTL = PIOC_PY03_FUNC_CTL_SOC_PY_03; + HPM_PIOC->PAD[IOC_PAD_PY02].FUNC_CTL = PIOC_PY02_FUNC_CTL_SOC_PY_02; +} + +void init_pdm_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD22].FUNC_CTL = IOC_PD22_FUNC_CTL_PDM0_CLK; + HPM_IOC->PAD[IOC_PAD_PD23].FUNC_CTL = IOC_PD23_FUNC_CTL_PDM0_D_0; +} + +void init_enet_pins(ENET_Type *ptr) +{ + if (ptr == HPM_ENET0) { + HPM_IOC->PAD[IOC_PAD_PD00].FUNC_CTL = IOC_PD00_FUNC_CTL_ETH0_RXCK; + HPM_IOC->PAD[IOC_PAD_PD01].FUNC_CTL = IOC_PD01_FUNC_CTL_ETH0_RXDV; + + HPM_IOC->PAD[IOC_PAD_PD03].FUNC_CTL = IOC_PD03_FUNC_CTL_ETH0_RXD_0; + HPM_IOC->PAD[IOC_PAD_PD04].FUNC_CTL = IOC_PD04_FUNC_CTL_ETH0_RXD_1; + HPM_IOC->PAD[IOC_PAD_PD05].FUNC_CTL = IOC_PD05_FUNC_CTL_ETH0_RXD_2; + HPM_IOC->PAD[IOC_PAD_PD06].FUNC_CTL = IOC_PD06_FUNC_CTL_ETH0_RXD_3; + + HPM_IOC->PAD[IOC_PAD_PA18].FUNC_CTL = IOC_PA18_FUNC_CTL_ETH0_MDC; + HPM_IOC->PAD[IOC_PAD_PA19].FUNC_CTL = IOC_PA19_FUNC_CTL_ETH0_MDIO; + + HPM_IOC->PAD[IOC_PAD_PD16].FUNC_CTL = IOC_PD16_FUNC_CTL_ETH0_TXCK; + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PD17_FUNC_CTL_ETH0_TXEN; + + HPM_IOC->PAD[IOC_PAD_PD18].FUNC_CTL = IOC_PD18_FUNC_CTL_ETH0_TXD_0; + HPM_IOC->PAD[IOC_PAD_PD19].FUNC_CTL = IOC_PD19_FUNC_CTL_ETH0_TXD_1; + HPM_IOC->PAD[IOC_PAD_PD20].FUNC_CTL = IOC_PD20_FUNC_CTL_ETH0_TXD_2; + HPM_IOC->PAD[IOC_PAD_PD21].FUNC_CTL = IOC_PD21_FUNC_CTL_ETH0_TXD_3; + } +} + +void init_enet_pps_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD11].FUNC_CTL = IOC_PD11_FUNC_CTL_ETH0_EVTO_0; +} + +void init_adc16_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD26].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_B: ADC2/3.IN10 */ +} + +void init_adc_bldc_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 */ + HPM_IOC->PAD[IOC_PAD_PD24].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC2.08 / ADC3.08 */ + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC2.09 / ADC3.09 */ +} + +void init_adc_qeiv2_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD25].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IW: ADC2.09 / ADC3.09 cos_ch */ + HPM_IOC->PAD[IOC_PAD_PD14].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* ADC_IU: ADC0.14 / ADC1.14 sin_ch */ +} + +void init_can_pins(MCAN_Type *ptr) +{ + if (ptr == HPM_MCAN1) { + HPM_IOC->PAD[IOC_PAD_PD30].FUNC_CTL = IOC_PD30_FUNC_CTL_MCAN1_RXD; + HPM_IOC->PAD[IOC_PAD_PD31].FUNC_CTL = IOC_PD31_FUNC_CTL_MCAN1_TXD; + HPM_IOC->PAD[IOC_PAD_PD29].FUNC_CTL = IOC_PD29_FUNC_CTL_MCAN1_STBY; + } else { + /* Invalid CAN instance */ + } +} + +void init_led_pins_as_gpio(void) +{ + HPM_IOC->PAD[IOC_PAD_PA25].FUNC_CTL = IOC_PA25_FUNC_CTL_GPIO_A_25; +} + +void init_led_pins_as_pwm(void) +{ + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_TRGM_P_08; +} + +void init_plb_pulse_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_TRGM_P_10; +} + +void init_plb_ab_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PB23].FUNC_CTL = IOC_PB23_FUNC_CTL_TRGM_P_08; + HPM_IOC->PAD[IOC_PAD_PB22].FUNC_CTL = IOC_PB22_FUNC_CTL_TRGM_P_09; + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_TRGM_P_10; +} + +void init_plb_lin_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD08].FUNC_CTL = IOC_PD08_FUNC_CTL_TRGM_P_08; +} + +void init_plb_filter_pins(void) +{ + HPM_IOC->PAD[IOC_PAD_PD10].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(0); + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_TRGM_P_10; + HPM_IOC->PAD[IOC_PAD_PD12].FUNC_CTL = IOC_PD12_FUNC_CTL_TRGM_P_12; +} + +/* for uart_rx_line_status case, need to a gpio pin to sent break signal */ +void init_uart_break_signal_pin(void) +{ + HPM_IOC->PAD[IOC_PAD_PY05].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05; + HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = PIOC_PY05_FUNC_CTL_SOC_PY_05; +} + +void init_dac_pins(DAC_Type *ptr) +{ + if (ptr == HPM_DAC0) { + HPM_IOC->PAD[IOC_PAD_PD07].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC0.OUT */ + } else if (ptr == HPM_DAC1) { + HPM_IOC->PAD[IOC_PAD_PD17].FUNC_CTL = IOC_PAD_FUNC_CTL_ANALOG_MASK; /* DAC1.OUT */ + } +} + +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp) +{ + if ((ptr == HPM_GPTMR0) && (channel == 2) && (as_comp == true)) { + HPM_IOC->PAD[IOC_PAD_PD10].FUNC_CTL = IOC_PD10_FUNC_CTL_GPTMR0_COMP_2; + } else if (ptr == HPM_GPTMR3) { + if (as_comp == false) { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PY01].FUNC_CTL = IOC_PY01_FUNC_CTL_GPTMR3_CAPT_0; + HPM_PIOC->PAD[IOC_PAD_PY01].FUNC_CTL = PIOC_PY01_FUNC_CTL_SOC_PY_01; + } + } else { + if (channel == 0) { + HPM_IOC->PAD[IOC_PAD_PY00].FUNC_CTL = IOC_PY00_FUNC_CTL_GPTMR3_COMP_0; + HPM_PIOC->PAD[IOC_PAD_PY00].FUNC_CTL = PIOC_PY00_FUNC_CTL_SOC_PY_00; + } else if (channel == 2) { + HPM_IOC->PAD[IOC_PAD_PB21].FUNC_CTL = IOC_PB21_FUNC_CTL_GPTMR3_COMP_2; + } + } + } +} + diff --git a/bsp/hpmicro/hpm6p00evk/board/pinmux.h b/bsp/hpmicro/hpm6p00evk/board/pinmux.h new file mode 100644 index 00000000000..66c226788da --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/pinmux.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2024 hpmicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef HPM_PINMUX_H +#define HPM_PINMUX_H + +#ifdef __cplusplus +extern "C" { +#endif +void init_uart_pins(UART_Type *ptr); +void init_uart_pin_as_gpio(UART_Type *ptr); +void init_i2c_pins(I2C_Type *ptr); +void init_femc_pins(void); +void init_ppi_pins(void); +void init_sdm_pins(void); +void init_pwm_pin_as_sdm_clock(void); +void init_gpio_pins(void); +void init_spi_pins(SPI_Type *ptr); +void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr); +void init_gptmr_pins(GPTMR_Type *ptr); +void init_hall_trgm_pins(void); +void init_qei_trgm_pins(void); +void init_butn_pins(void); +void init_acmp_pins(void); +void init_pwm_pins(PWMV2_Type *ptr); +void init_usb_pins(USB_Type *ptr); +void init_i2s_pins(I2S_Type *ptr); +void init_qeo_pins(QEOV2_Type *ptr); +void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx); +void init_qeiv2_uvw_pins(QEIV2_Type *ptr); +void init_qeiv2_ab_pins(QEIV2_Type *ptr); +void init_qeiv2_abz_pins(QEIV2_Type *ptr); +void init_rdc_pin(void); +void init_dao_pins(void); +void init_pdm_pins(void); +void init_enet_pins(ENET_Type *ptr); +void init_enet_pps_pins(void); +void init_adc16_pins(void); +void init_dac_pins(DAC_Type *ptr); +void init_adc_bldc_pins(void); +void init_adc_qeiv2_pins(void); +void init_can_pins(MCAN_Type *ptr); +void init_led_pins_as_gpio(void); +void init_led_pins_as_pwm(void); +void init_plb_pulse_pins(void); +void init_plb_ab_pins(void); +void init_plb_filter_pins(void); +void init_pwm_fault_pins(void); +void init_uart_break_signal_pin(void); +void init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp); +void init_plb_lin_pins(void); + +#ifdef __cplusplus +} +#endif +#endif /* HPM_PINMUX_H */ diff --git a/bsp/hpmicro/hpm6p00evk/board/rtt_board.c b/bsp/hpmicro/hpm6p00evk/board/rtt_board.c new file mode 100644 index 00000000000..a20fe8ea455 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/rtt_board.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2023-2024 HPMicro + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "board.h" +#include "rtt_board.h" +#include "hpm_uart_drv.h" +#include "hpm_gpio_drv.h" +#include "hpm_pmp_drv.h" +#include "assert.h" +#include "hpm_clock_drv.h" +#include "hpm_sysctl_drv.h" +#include +#include +#include "hpm_dma_mgr.h" +#include "hpm_mchtmr_drv.h" + +extern int rt_hw_uart_init(void); +void os_tick_config(void); +void rtt_board_init(void); + +void rt_hw_board_init(void) +{ + rtt_board_init(); + + /* Call the RT-Thread Component Board Initialization */ + rt_components_board_init(); +} + +void os_tick_config(void) +{ + sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1); + sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0); + mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND); + enable_mchtmr_irq(); +} + +void rtt_board_init(void) +{ + board_init_clock(); + board_init_console(); + board_init_pmp(); + + dma_mgr_init(); + + /* initialize memory system */ + rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); + + /* Configure the OS Tick */ + os_tick_config(); + + /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */ + rt_hw_uart_init(); + + /* Set console device */ + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +} + +void app_init_led_pins(void) +{ + board_init_led_pins(); + gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN); + + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF); +} + +void app_led_write(uint32_t index, bool state) +{ + switch (index) + { + case 0: + gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state); + break; + default: + /* Suppress the toolchain warnings */ + break; + } +} + +void rt_hw_console_output(const char *str) +{ + while (*str != '\0') + { + uart_send_byte(BOARD_APP_UART_BASE, *str++); + } +} + +void app_init_usb_pins(void) +{ + board_init_usb(HPM_USB0); +} + +ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void) +{ + HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND; + + rt_tick_increase(); +} + +void rt_hw_cpu_reset(void) +{ + HPM_PPOR->RESET_ENABLE |= (1UL << 31); + HPM_PPOR->SOFTWARE_RESET = 1000U; + while(1) { + + } +} + +MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board); + +#ifdef RT_USING_CACHE +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +uint32_t rtt_board_init_adc16_clock(void *ptr, bool clk_src_ahb) /* motor system should be use clk_adc_src_ahb0 */ +{ + uint32_t freq = 0; + + if (ptr == (void *)HPM_ADC0) { + clock_add_to_group(clock_adc0, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc0, clk_adc_src_ana0); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc0); + } else if (ptr == (void *)HPM_ADC1) { + clock_add_to_group(clock_adc1, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc1, clk_adc_src_ana1); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc1); + } else if (ptr == (void *)HPM_ADC2) { + clock_add_to_group(clock_adc2, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc2, clk_adc_src_ana2); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc2); + } else if (ptr == (void *)HPM_ADC3) { + clock_add_to_group(clock_adc3, 0); + if (clk_src_ahb) { + /* Configure the ADC clock from AHB (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ahb0); + } else { + /* Configure the ADC clock from ANA (@200MHz by default)*/ + clock_set_adc_source(clock_adc3, clk_adc_src_ana3); + clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U); + } + freq = clock_get_frequency(clock_adc3); + } else { + ; + } + + return freq; +} + +uint32_t rtt_board_init_pwm_clock(PWMV2_Type *ptr) +{ + uint32_t freq = 0; + if (ptr == HPM_PWM0) { + clock_add_to_group(clock_pwm0, 0); + freq = clock_get_frequency(clock_pwm0); + } else if (ptr == HPM_PWM1) { + clock_add_to_group(clock_pwm1, 0); + freq = clock_get_frequency(clock_pwm1); + } else if (ptr == HPM_PWM2) { + clock_add_to_group(clock_pwm2, 0); + freq = clock_get_frequency(clock_pwm2); + } else if (ptr == HPM_PWM3) { + clock_add_to_group(clock_pwm3, 0); + freq = clock_get_frequency(clock_pwm3); + } else { + + } + return freq; +} + +#ifdef CONFIG_CHERRYUSB_CUSTOM_IRQ_HANDLER +extern void hpm_isr_usb0(void); +RTT_DECLARE_EXT_ISR_M(IRQn_USB0, hpm_isr_usb0) +#endif diff --git a/bsp/hpmicro/hpm6p00evk/board/rtt_board.h b/bsp/hpmicro/hpm6p00evk/board/rtt_board.h new file mode 100644 index 00000000000..bb183d4cf01 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/board/rtt_board.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2024-2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _RTT_BOARD_H +#define _RTT_BOARD_H +#include "hpm_common.h" +#include "hpm_soc.h" +#include "board.h" + +/* gpio section */ +#define APP_LED0 (0U) +#define APP_LED0_GPIO_CTRL HPM_GPIO0 +#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOA +#define APP_LED0_GPIO_PIN 25 +#define APP_LED_ON (0) +#define APP_LED_OFF (1) + + + +/* mchtimer section */ +#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL) + +/* gptmr as os_tick */ +#define BOARD_OS_TIMER HPM_GPTMR0 +#define BOARD_OS_TIMER_CH 1 +#define BOARD_OS_TIMER_IRQ IRQn_GPTMR0 +#define BOARD_OS_TIMER_CLK_NAME (clock_gptmr0) + +/* CAN section */ +#define BOARD_CAN_NAME "can1" +#define BOARD_CAN_HWFILTER_INDEX (1U) + +/* UART section */ +#define BOARD_UART_NAME "uart4" +#define BOARD_UART_RX_BUFFER_SIZE BSP_UART4_RX_BUFSIZE + +/* PWM section */ +#define BOARD_PWM_NAME "pwm1" +#define BOARD_PWM_CHANNEL (0U) + +/* ADC section */ +#define BOARD_ADC_NAME BOARD_APP_ADC16_NAME +#define BOARD_ADC_CHANNEL BOARD_APP_ADC16_CH_1 + +#define IRQn_PendSV IRQn_DEBUG0 + +#define BOARD_ENET0_INF (1U) /* 0: RMII, 1: RGMII */ +#define BOARD_ENET0_INT_REF_CLK (0U) +#define BOARD_ENET0_PHY_RST_TIME (30) +#if BOARD_ENET0_INF +#define BOARD_ENET0_TX_DLY (0U) +#define BOARD_ENET0_RX_DLY (0U) +#endif +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP +#define BOARD_ENET0_PTP_CLOCK (clock_ptp0) +#endif + +/*************************************************************** + * + * RT-Thread related definitions + * + **************************************************************/ +extern unsigned int __heap_start__; +extern unsigned int __heap_end__; + +#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__) +#define RT_HW_HEAP_END ((void*)&__heap_end__) + + +typedef struct { + uint16_t vdd; + uint8_t bus_width; + uint8_t drive_strength; +}sdxc_io_cfg_t; + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + + +void app_init_led_pins(void); +void app_led_write(uint32_t index, bool state); +void app_init_usb_pins(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _RTT_BOARD_H */ diff --git a/bsp/hpmicro/hpm6p00evk/figures/board.png b/bsp/hpmicro/hpm6p00evk/figures/board.png new file mode 100644 index 00000000000..13f0fb8b8db Binary files /dev/null and b/bsp/hpmicro/hpm6p00evk/figures/board.png differ diff --git a/bsp/hpmicro/hpm6p00evk/makefile.targets b/bsp/hpmicro/hpm6p00evk/makefile.targets new file mode 100644 index 00000000000..e71da5a6e1e --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/makefile.targets @@ -0,0 +1,6 @@ +clean2: + -$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS) + -$(RM) $(OBJS) *.elf + -@echo ' ' + +*.elf: $(wildcard ../linkscripts/*/*.lds) $(wildcard ../linkscripts/*/*/*.lds) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig.h b/bsp/hpmicro/hpm6p00evk/rtconfig.h new file mode 100644 index 00000000000..55026070891 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/rtconfig.h @@ -0,0 +1,421 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 16 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 +#define RT_USING_CPU_USAGE_TRACER + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart0" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_RISCV +#define ARCH_RISCV32 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V2 +#define RT_SERIAL_BUF_STRATEGY_OVERWRITE +#define RT_SERIAL_USING_DMA +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ + +/* HPMicro SDK */ + +#define PKG_USING_HPM_SDK +#define PKG_USING_HPM_SDK_LATEST_VERSION +/* end of HPMicro SDK */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_HPM6P00_SERIES + +/* Hardware Drivers Config */ + +#define SOC_HPM6P00 + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_GPIO_IRQ_PRIORITY 1 +#define BSP_USING_UART +#define BSP_USING_UART0 +#define BSP_UART0_RX_BUFSIZE 128 +#define BSP_UART0_TX_BUFSIZE 0 +#define BSP_UART0_IRQ_PRIORITY 1 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig.py b/bsp/hpmicro/hpm6p00evk/rtconfig.py new file mode 100644 index 00000000000..5ff491039c0 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/rtconfig.py @@ -0,0 +1,150 @@ +# Copyright 2021-2025 HPMicro +# SPDX-License-Identifier: BSD-3-Clause + +import os +import sys +import rtconfig + + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + need_update = True + for p in os.listdir("packages"): + if p.startswith("hpm_sdk-"): + need_update = False + break + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + + +# toolchains options +ARCH='risc-v' +CPU='hpmicro' +SOC_FAMILY='HPM6P00' +CHIP_NAME='HPM6P81' + +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +# Fallback toolchain info +FALLBACK_TOOLCHAIN_VENDOR='RISC-V' +FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32' +FALLBACK_TOOLCHAIN_VER='2022-04-12' + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH') +if RTT_EXEC_PATH != None: + folders = RTT_EXEC_PATH.split(os.sep) + # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO` + if 'arm_gcc' in folders and 'platform' in folders: + RTT_EXEC_PATH = '' + for path in folders: + if path != 'platform': + RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep + else: + break + RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin') + # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio + if 'platform' in folders: + os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_RISCV_TOOLCHAIN'): + EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN') + else: + EXEC_PATH = r'/opt/riscv-gnu-gcc/bin' +else: + print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL) + +BUILD = 'flash_debug' + +if PLATFORM == 'gcc': + PREFIX = 'riscv32-unknown-elf-' + CC = PREFIX + 'gcc' + CXX = PREFIX + 'g++' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + GDB = PREFIX + 'gdb' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + STRIP = PREFIX + 'strip' + + ARCH_ABI = ' -mcmodel=medlow ' + DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common ' + CFLAGS = DEVICE + AFLAGS = CFLAGS + LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections ' + + CPATH = '' + LPATH = '' + + if BUILD == 'ram_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'ram_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/ram_rtt.ld' + elif BUILD == 'flash_debug': + CFLAGS += ' -gdwarf-2' + AFLAGS += ' -gdwarf-2' + CFLAGS += ' -O0' + LFLAGS += ' -O0' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + elif BUILD == 'flash_release': + CFLAGS += ' -O2' + LFLAGS += ' -O2' + CFLAGS += ' -DFLASH_XIP=1' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + else: + CFLAGS += ' -O2' + LFLAGS += ' -O2' + LINKER_FILE = 'board/linker_scripts/gcc/flash_rtt.ld' + LFLAGS += ' -T ' + LINKER_FILE + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + + # module setting + CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' + CFLAGS = CFLAGS + ' -std=gnu11' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h b/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h new file mode 100644 index 00000000000..b7ae18b3266 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/rtconfig_preinc.h @@ -0,0 +1,18 @@ + +#ifndef RTCONFIG_PREINC_H__ +#define RTCONFIG_PREINC_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread pre-include file */ + +#define D45 +#define HPM6880 +#define HPM6E80 +#define HPMSOC_HAS_HPMSDK_DMAV2 +#define RT_USING_LIBC +#define RT_USING_NEWLIBC +#define _POSIX_C_SOURCE 1 +#define _REENT_SMALL +#define __RTTHREAD__ + +#endif /*RTCONFIG_PREINC_H__*/ diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/SConscript b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/SConscript new file mode 100644 index 00000000000..a1ec2c8e79f --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/SConscript @@ -0,0 +1,19 @@ +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() + +# add the startup files + +src = Glob('*.c') + +if rtconfig.PLATFORM == 'gcc': + src += [os.path.join('toolchains', 'gcc', 'start.S')] + src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')] + +CPPPATH = [cwd] +CPPDEFINES=['D45', rtconfig.CHIP_NAME] + +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c new file mode 100644 index 00000000000..e3f85a9e0ee --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/startup.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * + */ + +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_l1c_drv.h" +#include + +void system_init(void); + +extern int entry(void); + +extern void __libc_init_array(void); +extern void __libc_fini_array(void); + +void system_init(void) +{ + disable_global_irq(CSR_MSTATUS_MIE_MASK); + disable_irq_from_intc(); + enable_irq_from_intc(); + enable_global_irq(CSR_MSTATUS_MIE_MASK); +#ifndef CONFIG_NOT_ENABLE_ICACHE + l1c_ic_enable(); +#endif +#ifndef CONFIG_NOT_ENABLE_DCACHE + l1c_dc_enable(); +#endif +} + +__attribute__((weak)) void c_startup(void) +{ +#ifndef __SES_RISCV + uint32_t i, size; +#ifdef FLASH_XIP + extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; + size = __vector_ram_end__ - __vector_ram_start__; + for (i = 0; i < size; i++) { + *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); + } +#endif + + extern uint8_t __etext[]; + extern uint8_t __bss_start__[], __bss_end__[]; + extern uint8_t __tbss_start__[], __tbss_end__[]; + extern uint8_t __tdata_start__[], __tdata_end__[]; + extern uint8_t __fast_load_addr__[]; + extern uint8_t __noncacheable_init_load_addr__[]; + extern uint8_t __data_load_addr__[]; + extern uint8_t __tdata_load_addr__[]; + extern uint8_t __data_start__[], __data_end__[]; + extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; + extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; + extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; + + /* tbss section */ + size = __tbss_end__ - __tbss_start__; + for (i = 0; i < size; i++) { + *(__tbss_start__ + i) = 0; + } + + /* bss section */ + size = __bss_end__ - __bss_start__; + for (i = 0; i < size; i++) { + *(__bss_start__ + i) = 0; + } + + /* noncacheable bss section */ + size = __noncacheable_bss_end__ - __noncacheable_bss_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_bss_start__ + i) = 0; + } + + /* tdata section LMA: etext */ + size = __tdata_end__ - __tdata_start__; + for (i = 0; i < size; i++) { + *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); + } + + /* data section LMA: etext */ + size = __data_end__ - __data_start__; + for (i = 0; i < size; i++) { + *(__data_start__ + i) = *(__data_load_addr__ + i); + } + + /* ramfunc section LMA: etext + data length */ + size = __ramfunc_end__ - __ramfunc_start__; + for (i = 0; i < size; i++) { + *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); + } + + /* noncacheable init section LMA: etext + data length + ramfunc length */ + size = __noncacheable_init_end__ - __noncacheable_init_start__; + for (i = 0; i < size; i++) { + *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); + } +#endif +} + +__attribute__((weak)) int main(void) +{ + while(1); +} + +void reset_handler(void) +{ + /** + * Disable preemptive interrupt + */ + HPM_PLIC->FEATURE = 0; + /* + * Initialize LMA/VMA sections. + * Relocation for any sections that need to be copied from LMA to VMA. + */ + c_startup(); + + /* Call platform specific hardware initialization */ + system_init(); + +#ifndef __SES_RISCV + /* Do global constructors */ + __libc_init_array(); +#endif + + /* Entry function */ + entry(); +} + + +__attribute__((weak)) void _init(void) +{ +} diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/port_gcc.S b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/port_gcc.S new file mode 100644 index 00000000000..6e8933bd7af --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/port_gcc.S @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "cpuport.h" + .section .text.entry, "ax" + .align 2 + .globl rt_hw_do_after_save_above + .type rt_hw_do_after_save_above,@function +rt_hw_do_after_save_above: + addi sp, sp, -4 + STORE ra, 0 * REGBYTES(sp) + + csrr t1, mcause + andi t1, t1, 0x3FF + /* get ISR */ + la t2, trap_entry + jalr t2 + + LOAD ra, 0 * REGBYTES(sp) + addi sp, sp, 4 + ret diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S new file mode 100644 index 00000000000..c2000769245 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/start.S @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2021-2023 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + #include + #include "hpm_csr_regs.h" + .section .start, "ax" + + .global _start + .type _start,@function + +_start: + /* Initialize global pointer */ + .option push + .option norelax + la gp, __global_pointer$ + la tp, __thread_pointer + .option pop + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef INIT_EXT_RAM_FOR_DATA + la t0, _stack_in_dlm + mv sp, t0 + call _init_ext_ram +#endif + + /* Initialize stack pointer */ + la t0, _stack + mv sp, t0 + +#ifdef __nds_execit + /* Initialize EXEC.IT table */ + la t0, _ITB_BASE_ + csrw uitb, t0 +#endif + +#ifdef __riscv_flen + /* Enable FPU */ + li t0, CSR_MSTATUS_FS_MASK + csrrs t0, mstatus, t0 + + /* Initialize FCSR */ + fscsr zero +#endif + +#ifdef HPM_USING_VECTOR_PREEMPTED_MODE + /* Initial machine trap-vector Base */ + la t0, __vector_table + csrw mtvec, t0 + /* Enable vectored external PLIC interrupt */ + csrsi CSR_MMISC_CTL, 2 +#else + /* Initial machine trap-vector Base */ + la t0, SW_handler + csrw mtvec, t0 + /* Disable vectored external PLIC interrupt */ + csrci CSR_MMISC_CTL, 2 +#endif + + /* System reset handler */ + call reset_handler + + /* Infinite loop, if returned accidently */ +1: j 1b + + .weak nmi_handler +nmi_handler: +1: j 1b + + .weak default_irq_handler + .align 2 +default_irq_handler: +1: j 1b + + .macro IRQ_HANDLER irq + .weak default_isr_\irq + .set default_isr_\irq, default_irq_handler + .long default_isr_\irq + .endm + +#include "vectors.S" diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S new file mode 100644 index 00000000000..51d8f5dc5c6 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/toolchains/gcc/vectors.S @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + .section .vector_table, "a" + .global __vector_table + .align 9 +__vector_table: + .weak default_isr_trap + .set default_isr_trap, SW_handler + .long default_isr_trap + IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ + IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ + IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ + IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ + IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ + IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ + IRQ_HANDLER 7 /* GPIO1_A IRQ handler */ + IRQ_HANDLER 8 /* GPIO1_B IRQ handler */ + IRQ_HANDLER 9 /* GPIO1_C IRQ handler */ + IRQ_HANDLER 10 /* GPIO1_D IRQ handler */ + IRQ_HANDLER 11 /* GPIO1_X IRQ handler */ + IRQ_HANDLER 12 /* GPIO1_Y IRQ handler */ + IRQ_HANDLER 13 /* GPTMR0 IRQ handler */ + IRQ_HANDLER 14 /* GPTMR1 IRQ handler */ + IRQ_HANDLER 15 /* GPTMR2 IRQ handler */ + IRQ_HANDLER 16 /* GPTMR3 IRQ handler */ + IRQ_HANDLER 17 /* Reserved */ + IRQ_HANDLER 18 /* Reserved */ + IRQ_HANDLER 19 /* Reserved */ + IRQ_HANDLER 20 /* Reserved */ + IRQ_HANDLER 21 /* UART0 IRQ handler */ + IRQ_HANDLER 22 /* UART1 IRQ handler */ + IRQ_HANDLER 23 /* UART2 IRQ handler */ + IRQ_HANDLER 24 /* UART3 IRQ handler */ + IRQ_HANDLER 25 /* UART4 IRQ handler */ + IRQ_HANDLER 26 /* UART5 IRQ handler */ + IRQ_HANDLER 27 /* UART6 IRQ handler */ + IRQ_HANDLER 28 /* UART7 IRQ handler */ + IRQ_HANDLER 29 /* I2C0 IRQ handler */ + IRQ_HANDLER 30 /* I2C1 IRQ handler */ + IRQ_HANDLER 31 /* I2C2 IRQ handler */ + IRQ_HANDLER 32 /* I2C3 IRQ handler */ + IRQ_HANDLER 33 /* SPI0 IRQ handler */ + IRQ_HANDLER 34 /* SPI1 IRQ handler */ + IRQ_HANDLER 35 /* SPI2 IRQ handler */ + IRQ_HANDLER 36 /* SPI3 IRQ handler */ + IRQ_HANDLER 37 /* TSNS IRQ handler */ + IRQ_HANDLER 38 /* MBX0A IRQ handler */ + IRQ_HANDLER 39 /* MBX0B IRQ handler */ + IRQ_HANDLER 40 /* MBX1A IRQ handler */ + IRQ_HANDLER 41 /* MBX1B IRQ handler */ + IRQ_HANDLER 42 /* EWDG0 IRQ handler */ + IRQ_HANDLER 43 /* EWDG1 IRQ handler */ + IRQ_HANDLER 44 /* EWDG2 IRQ handler */ + IRQ_HANDLER 45 /* EWDG3 IRQ handler */ + IRQ_HANDLER 46 /* HDMA IRQ handler */ + IRQ_HANDLER 47 /* LOBS IRQ handler */ + IRQ_HANDLER 48 /* ADC0 IRQ handler */ + IRQ_HANDLER 49 /* ADC1 IRQ handler */ + IRQ_HANDLER 50 /* ADC2 IRQ handler */ + IRQ_HANDLER 51 /* ADC3 IRQ handler */ + IRQ_HANDLER 52 /* DAC0 IRQ handler */ + IRQ_HANDLER 53 /* DAC1 IRQ handler */ + IRQ_HANDLER 54 /* ACMP0[0] IRQ handler */ + IRQ_HANDLER 55 /* ACMP0[1] IRQ handler */ + IRQ_HANDLER 56 /* ACMP1[0] IRQ handler */ + IRQ_HANDLER 57 /* ACMP1[1] IRQ handler */ + IRQ_HANDLER 58 /* ACMP2[0] IRQ handler */ + IRQ_HANDLER 59 /* ACMP2[1] IRQ handler */ + IRQ_HANDLER 60 /* ACMP3[0] IRQ handler */ + IRQ_HANDLER 61 /* ACMP3[1] IRQ handler */ + IRQ_HANDLER 62 /* I2S0 IRQ handler */ + IRQ_HANDLER 63 /* I2S1 IRQ handler */ + IRQ_HANDLER 64 /* DAO IRQ handler */ + IRQ_HANDLER 65 /* PDM IRQ handler */ + IRQ_HANDLER 66 /* MCAN0 IRQ handler */ + IRQ_HANDLER 67 /* MCAN1 IRQ handler */ + IRQ_HANDLER 68 /* MCAN2 IRQ handler */ + IRQ_HANDLER 69 /* MCAN3 IRQ handler */ + IRQ_HANDLER 70 /* PTPC IRQ handler */ + IRQ_HANDLER 71 /* QEI0 IRQ handler */ + IRQ_HANDLER 72 /* QEI1 IRQ handler */ + IRQ_HANDLER 73 /* PWM0 IRQ handler */ + IRQ_HANDLER 74 /* PWM1 IRQ handler */ + IRQ_HANDLER 75 /* PWM2 IRQ handler */ + IRQ_HANDLER 76 /* PWM3 IRQ handler */ + IRQ_HANDLER 77 /* RDC0 IRQ handler */ + IRQ_HANDLER 78 /* SDM0 IRQ handler */ + IRQ_HANDLER 79 /* SEI0[0] IRQ handler */ + IRQ_HANDLER 80 /* SEI0[1] IRQ handler */ + IRQ_HANDLER 81 /* MTG0 IRQ handler */ + IRQ_HANDLER 82 /* VSC0 IRQ handler */ + IRQ_HANDLER 83 /* CLC0[0] IRQ handler */ + IRQ_HANDLER 84 /* CLC0[1] IRQ handler */ + IRQ_HANDLER 85 /* TRGMUX0 IRQ handler */ + IRQ_HANDLER 86 /* TRGMUX1 IRQ handler */ + IRQ_HANDLER 87 /* ENET0 IRQ handler */ + IRQ_HANDLER 88 /* NTMR0 IRQ handler */ + IRQ_HANDLER 89 /* USB0 IRQ handler */ + IRQ_HANDLER 90 /* XPI0 IRQ handler */ + IRQ_HANDLER 91 /* FEMC IRQ handler */ + IRQ_HANDLER 92 /* PPI IRQ handler */ + IRQ_HANDLER 93 /* XDMA IRQ handler */ + IRQ_HANDLER 94 /* FFA IRQ handler */ + IRQ_HANDLER 95 /* SDP IRQ handler */ + IRQ_HANDLER 96 /* RNG IRQ handler */ + IRQ_HANDLER 97 /* PSEC IRQ handler */ + IRQ_HANDLER 98 /* PGPIO IRQ handler */ + IRQ_HANDLER 99 /* PEWDG IRQ handler */ + IRQ_HANDLER 100 /* PTMR IRQ handler */ + IRQ_HANDLER 101 /* PUART IRQ handler */ + IRQ_HANDLER 102 /* FUSE IRQ handler */ + IRQ_HANDLER 103 /* SECMON IRQ handler */ + IRQ_HANDLER 104 /* PAD_WAKEUP IRQ handler */ + IRQ_HANDLER 105 /* BROWNOUT IRQ handler */ + IRQ_HANDLER 106 /* SYSCTL IRQ handler */ + IRQ_HANDLER 107 /* CPU0 IRQ handler */ + IRQ_HANDLER 108 /* CPU1 IRQ handler */ + IRQ_HANDLER 109 /* DEBUG0 IRQ handler */ + IRQ_HANDLER 110 /* DEBUG1 IRQ handler */ \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/trap.c b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/trap.c new file mode 100644 index 00000000000..470b3fe2662 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/HPM6P81/trap.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2021-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "hpm_common.h" +#include "hpm_soc.h" +#include +#include "rt_hw_stack_frame.h" + +#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned +#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault +#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction +#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint +#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned +#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault +#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned +#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault +#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode +#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode +#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode +#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault +#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault +#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault + +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_COP 12 +#define IRQ_HOST 13 + +#ifdef DEBUG +#define RT_EXCEPTION_TRACE rt_kprintf +#else +#define RT_EXCEPTION_TRACE(...) +#endif + +typedef void (*isr_func_t)(void); + +static volatile rt_hw_stack_frame_t *s_stack_frame; + +__attribute((weak)) void mchtmr_isr(void) +{ +} + +__attribute__((weak)) void mswi_isr(void) +{ +} + +__attribute__((weak)) void syscall_handler(uint32_t n, uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3) +{ +} + +void rt_show_stack_frame(void) +{ + RT_EXCEPTION_TRACE("Stack frame:\r\n----------------------------------------\r\n"); + RT_EXCEPTION_TRACE("ra : 0x%08x\r\n", s_stack_frame->ra); + RT_EXCEPTION_TRACE("mstatus : 0x%08x\r\n", read_csr(0x300));//mstatus + RT_EXCEPTION_TRACE("t0 : 0x%08x\r\n", s_stack_frame->t0); + RT_EXCEPTION_TRACE("t1 : 0x%08x\r\n", s_stack_frame->t1); + RT_EXCEPTION_TRACE("t2 : 0x%08x\r\n", s_stack_frame->t2); + RT_EXCEPTION_TRACE("a0 : 0x%08x\r\n", s_stack_frame->a0); + RT_EXCEPTION_TRACE("a1 : 0x%08x\r\n", s_stack_frame->a1); + RT_EXCEPTION_TRACE("a2 : 0x%08x\r\n", s_stack_frame->a2); + RT_EXCEPTION_TRACE("a3 : 0x%08x\r\n", s_stack_frame->a3); + RT_EXCEPTION_TRACE("a4 : 0x%08x\r\n", s_stack_frame->a4); + RT_EXCEPTION_TRACE("a5 : 0x%08x\r\n", s_stack_frame->a5); +#ifndef __riscv_32e + RT_EXCEPTION_TRACE("a6 : 0x%08x\r\n", s_stack_frame->a6); + RT_EXCEPTION_TRACE("a7 : 0x%08x\r\n", s_stack_frame->a7); + RT_EXCEPTION_TRACE("t3 : 0x%08x\r\n", s_stack_frame->t3); + RT_EXCEPTION_TRACE("t4 : 0x%08x\r\n", s_stack_frame->t4); + RT_EXCEPTION_TRACE("t5 : 0x%08x\r\n", s_stack_frame->t5); + RT_EXCEPTION_TRACE("t6 : 0x%08x\r\n", s_stack_frame->t6); +#endif +} + +uint32_t exception_handler(uint32_t cause, uint32_t epc) +{ + /* Unhandled Trap */ + uint32_t mdcause = read_csr(CSR_MDCAUSE); + uint32_t mtval = read_csr(CSR_MTVAL); + rt_uint32_t mscratch = read_csr(0x340); + + s_stack_frame = (rt_hw_stack_frame_t *)mscratch; + rt_show_stack_frame(); + + switch (cause) + { + case MCAUSE_INSTR_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: instruction address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_INSTR_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: instruction access fault happened, mtval=0x%08x, epc=0x%08x\n", mtval, epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_ILLEGAL_INSTR: + RT_EXCEPTION_TRACE("exception: illegal instruction was met, mtval=0x%08x\n", mtval); + switch (mdcause & 0x07) + { + case 0: + RT_EXCEPTION_TRACE("mdcause: the actual faulting instruction is stored in the mtval CSR\r\n"); + break; + case 1: + RT_EXCEPTION_TRACE("mdcause: FP disabled exception \r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: ACE disabled exception \r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_BREAKPOINT: + RT_EXCEPTION_TRACE("exception: breakpoint was hit, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: load address was mis-aligned, mtval=0x%08x\n", mtval); + break; + case MCAUSE_LOAD_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: load access fault happened, epc=%08x, mdcause=0x%x\n", epc, mdcause); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + case MCAUSE_STORE_AMO_ADDR_MISALIGNED: + RT_EXCEPTION_TRACE("exception: store amo address was misaligned, epc=%08x\n", epc); + break; + case MCAUSE_STORE_AMO_ACCESS_FAULT: + RT_EXCEPTION_TRACE("exception: store amo access fault happened, epc=%08x\n", epc); + switch (mdcause & 0x07) + { + case 1: + RT_EXCEPTION_TRACE("mdcause: ECC/Parity error\r\n"); + break; + case 2: + RT_EXCEPTION_TRACE("mdcause: PMP instruction access violation \r\n"); + break; + case 3: + RT_EXCEPTION_TRACE("mdcause: BUS error\r\n"); + break; + case 4: + RT_EXCEPTION_TRACE("mdcause: Misaligned access \r\n"); + break; + case 5: + RT_EXCEPTION_TRACE("mdcause: PMP empty hole access \r\n"); + break; + case 6: + RT_EXCEPTION_TRACE("mdcause: PMA attribute inconsistency\r\n"); + break; + case 7: + RT_EXCEPTION_TRACE("mdcause: PMA NAMO exception \r\n"); + default: + RT_EXCEPTION_TRACE("mdcause: reserved \r\n"); + break; + } + break; + default: + RT_EXCEPTION_TRACE("Unknown exception happened, cause=%d\n", cause); + break; + } + + rt_kprintf("cause=0x%08x, epc=0x%08x, ra=0x%08x\n", cause, epc, s_stack_frame->ra); + while(1) { + } +} + +void trap_entry(void); + +void trap_entry(void) +{ + uint32_t mcause = read_csr(CSR_MCAUSE); + uint32_t mepc = read_csr(CSR_MEPC); + uint32_t mstatus = read_csr(CSR_MSTATUS); + +#if SUPPORT_PFT_ARCH + uint32_t mxstatus = read_csr(CSR_MXSTATUS); +#endif +#ifdef __riscv_dsp + int ucode = read_csr(CSR_UCODE); +#endif +#ifdef __riscv_flen + int fcsr = read_fcsr(); +#endif + + /* clobbers list for ecall */ +#ifdef __riscv_32e + __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); +#else + __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); +#endif + + /* Do your trap handling */ + uint32_t cause_type = mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK; + uint32_t irq_index; + if (mcause & CSR_MCAUSE_INTERRUPT_MASK) + { + switch (cause_type) + { + /* Machine timer interrupt */ + case IRQ_M_TIMER: + mchtmr_isr(); + break; + /* Machine EXT interrupt */ + case IRQ_M_EXT: + /* Claim interrupt */ + irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); + /* Execute EXT interrupt handler */ + if (irq_index > 0) + { + ((isr_func_t) __vector_table[irq_index])(); + /* Complete interrupt */ + __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); + } + break; + /* Machine SWI interrupt */ + case IRQ_M_SOFT: + mswi_isr(); + intc_m_complete_swi(); + break; + } + } + else if (cause_type == MCAUSE_ECALL_FROM_MACHINE_MODE) + { + /* Machine Syscal call */ + __asm volatile( + "mv a4, a3\n" + "mv a3, a2\n" + "mv a2, a1\n" + "mv a1, a0\n" +#ifdef __riscv_32e + "mv a0, t0\n" +#else + "mv a0, a7\n" +#endif + "call syscall_handler\n" + : : : "a4" + ); + mepc += 4; + } + else + { + mepc = exception_handler(mcause, mepc); + } + + /* Restore CSR */ + write_csr(CSR_MSTATUS, mstatus); + write_csr(CSR_MEPC, mepc); +#if SUPPORT_PFT_ARCH + write_csr(CSR_MXSTATUS, mxstatus); +#endif +#ifdef __riscv_dsp + write_csr(CSR_UCODE, ucode); +#endif +#ifdef __riscv_flen + write_fcsr(fcsr); +#endif +} + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +} \ No newline at end of file diff --git a/bsp/hpmicro/hpm6p00evk/startup/SConscript b/bsp/hpmicro/hpm6p00evk/startup/SConscript new file mode 100644 index 00000000000..de51a7c0d63 --- /dev/null +++ b/bsp/hpmicro/hpm6p00evk/startup/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +Import('rtconfig') +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] + +objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript')) +ASFLAGS = ' -I' + cwd + +Return('objs') \ No newline at end of file diff --git a/bsp/hpmicro/libraries/Kconfig b/bsp/hpmicro/libraries/Kconfig index faf5bc5bb41..2384b531765 100644 --- a/bsp/hpmicro/libraries/Kconfig +++ b/bsp/hpmicro/libraries/Kconfig @@ -1,4 +1,47 @@ -config SOC_HPM6000_SERIES - bool +config SOC_HPM6700_SERIES + bool select ARCH_RISCV32 select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM6300_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM6200_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM5300_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM6800_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM6E00_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM6P00_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK + +config SOC_HPM5E00_SERIES + bool + select ARCH_RISCV32 + select ARCH_RISCV_DPU + select PKG_USING_HPM_SDK \ No newline at end of file diff --git a/bsp/hpmicro/libraries/SConscript b/bsp/hpmicro/libraries/SConscript new file mode 100644 index 00000000000..1bc8f912511 --- /dev/null +++ b/bsp/hpmicro/libraries/SConscript @@ -0,0 +1,14 @@ +import os +import rtconfig +from building import * + + +objs = [] +cwd = GetCurrentDir() +list = os.listdir(cwd) + +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/hpmicro/libraries/drivers/SConscript b/bsp/hpmicro/libraries/drivers/SConscript index 3a73503e74b..d558ae6e9b5 100644 --- a/bsp/hpmicro/libraries/drivers/SConscript +++ b/bsp/hpmicro/libraries/drivers/SConscript @@ -68,6 +68,10 @@ if GetDepend('BSP_USING_MCAN'): if GetDepend(['BSP_USING_RTT_LCD_DRIVER']): src += ['drv_lcd.c'] +if GetDepend('BSP_USING_TSW'): + src += ['drv_tsw.c'] + src += ['drv_tsw_phy.c'] + path = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) diff --git a/bsp/hpmicro/libraries/drivers/drv_adc.c b/bsp/hpmicro/libraries/drivers/drv_adc.c index 9db3fce9220..f29ad153106 100644 --- a/bsp/hpmicro/libraries/drivers/drv_adc.c +++ b/bsp/hpmicro/libraries/drivers/drv_adc.c @@ -33,7 +33,10 @@ typedef struct adc_channel_state_t chn_state[16]; }hpm_rtt_adc; - +#if defined(ADC12_SOC_MAX_CH_NUM) +extern uint32_t rtt_board_init_adc12_clock(ADC16_Type *ptr); +#endif +extern uint32_t rtt_board_init_adc16_clock(ADC16_Type *ptr, bool clk_src_ahb); static uint32_t hpm_adc_init_clock(struct rt_adc_device *device); static void hpm_adc_init_pins(struct rt_adc_device *device); @@ -113,11 +116,11 @@ static uint32_t hpm_adc_init_clock(struct rt_adc_device *device) #if defined(ADC12_SOC_MAX_CH_NUM) if (hpm_adc->is_adc12) { - clock_freq = board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base,true); + clock_freq = rtt_board_init_adc12_clock((ADC12_Type*)hpm_adc->adc_base,true); } else #endif { - clock_freq = board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base,true); + clock_freq = rtt_board_init_adc16_clock((ADC16_Type*)hpm_adc->adc_base,true); } return clock_freq; } diff --git a/bsp/hpmicro/libraries/drivers/drv_can.c b/bsp/hpmicro/libraries/drivers/drv_can.c index 3c8f5032441..b94f0e10ea7 100644 --- a/bsp/hpmicro/libraries/drivers/drv_can.c +++ b/bsp/hpmicro/libraries/drivers/drv_can.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2023 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,7 @@ * Date Author Notes * 2022-05-08 HPMicro the first version * 2023-05-08 HPMicro Adapt RT-Thread v5.0.0 + * 2025/03-25 HPMicro Add configurable interrupt priority support */ #include @@ -15,6 +16,7 @@ #include "board.h" #include "hpm_can_drv.h" +#include "hpm_clock_drv.h" #define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ #define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ @@ -28,6 +30,8 @@ typedef struct _hpm_can_struct CAN_Type *can_base; /**< CAN Base address */ const char *name; /**< CAN device name */ int32_t irq_num; /**< CAN IRQ index */ + uint8_t irq_priority; /**< CAN IRQ priority */ + clock_name_t clk_name; /**< CAN clock name */ uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ can_config_t can_config; /**< CAN configuration for IP */ struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ @@ -97,13 +101,19 @@ static hpm_can_t dev_can0 = .name = "can0", .irq_num = IRQn_CAN0, .fifo_index = 0, + .clk_name = clock_can0, +#if defined(BSP_CAN0_IRQ_PRIORITY) + .irq_priority = BSP_CAN0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); void can0_isr(void) { hpm_can_isr(&dev_can0); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN0, can0_isr); #endif @@ -114,12 +124,18 @@ static hpm_can_t dev_can1 = .name = "can1", .irq_num = IRQn_CAN1, .fifo_index = 1, + .clk_name = clock_can1, +#if defined(BSP_CAN1_IRQ_PRIORITY) + .irq_priority = BSP_CAN1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); void can1_isr(void) { hpm_can_isr(&dev_can1); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN1, can1_isr); #endif #if defined(HPM_CAN2_BASE) && defined(BSP_USING_CAN2) @@ -129,12 +145,18 @@ static hpm_can_t dev_can2 = .name = "can2", .irq_num = IRQn_CAN2, .fifo_index = 2, + .clk_name = clock_can2, +#if defined(BSP_CAN2_IRQ_PRIORITY) + .irq_priority = BSP_CAN2_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); void can2_isr(void) { hpm_can_isr(&dev_can2); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN2, can2_isr); #endif #if defined(HPM_CAN3_BASE) && defined(BSP_USING_CAN3) @@ -144,12 +166,18 @@ static hpm_can_t dev_can3 = .name = "can3", .irq_num = IRQn_CAN3, .fifo_index = 3, + .clk_name = clock_can3, +#if defined(BSP_CAN3_IRQ_PRIORITY) + .irq_priority = BSP_CAN3_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); void can3_isr(void) { hpm_can_isr(&dev_can3); } -SDK_DECLARE_EXT_ISR_M(IRQn_CAN3, can3_isr); #endif static hpm_can_t *hpm_cans[] = { @@ -303,7 +331,8 @@ static rt_err_t hpm_can_configure(struct rt_can_device *can, struct can_configur drv_can->can_config.enable_tx_buffer_priority_mode = (cfg->privmode != 0U) ? true : false; init_can_pins(drv_can->can_base); - uint32_t can_clk = board_init_can_clock(drv_can->can_base); + clock_add_to_group(drv_can->clk_name, BOARD_RUNNING_CORE & 0x1); + uint32_t can_clk = clock_get_frequency(drv_can->clk_name); drv_can->can_config.filter_list_num = drv_can->filter_num; drv_can->can_config.filter_list = &drv_can->filter_list[0]; hpm_stat_t status = can_init(drv_can->can_base, &drv_can->can_config, can_clk); @@ -365,14 +394,14 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) uint8_t irq_txrx_mask = CAN_EVENT_RECEIVE | CAN_EVENT_RX_BUF_ALMOST_FULL | CAN_EVENT_RX_BUF_FULL | CAN_EVENT_RX_BUF_OVERRUN; drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); - intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } else if (arg_val == RT_DEVICE_FLAG_INT_TX) { uint8_t irq_txrx_mask = CAN_EVENT_TX_PRIMARY_BUF | CAN_EVENT_TX_SECONDARY_BUF; drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask; can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); - intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { @@ -382,7 +411,7 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg) drv_can->can_config.irq_error_enable_mask |= irq_error_mask; can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask); can_enable_error_irq(drv_can->can_base, irq_error_mask); - intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } else { diff --git a/bsp/hpmicro/libraries/drivers/drv_enet.c b/bsp/hpmicro/libraries/drivers/drv_enet.c index 781e51b580a..95df8cd8ddc 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -7,6 +7,7 @@ * Date Author Notes * 2022-01-11 HPMicro First version * 2022-07-10 HPMicro Driver optimization for multiple instances + * 2024-04-15 HPMicro Fixed an issue that received data is probabilistically overwritten */ #include @@ -30,6 +31,9 @@ __RW uint8_t enet0_rx_buff[ENET0_RX_BUFF_COUNT][ENET0_RX_BUFF_SIZE]; /* Ethernet ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet0_tx_buff[ENET0_TX_BUFF_COUNT][ENET0_TX_BUFF_SIZE]; /* Ethernet0 Transmit Buffer */ +LWIP_MEMPOOL_DECLARE(enet0_rx_pool, ENET0_RX_BUFF_COUNT, sizeof(my_custom_pbuf_t), "Custom RX PBUF pool"); +static enet_frame_t enet0_frame[ENET0_RX_BUFF_COUNT] = {0}; + struct eth_device eth0_dev; static enet_device enet0_dev; static enet_buff_config_t enet0_rx_buff_cfg = {.buffer = (uint32_t)enet0_rx_buff, @@ -42,7 +46,7 @@ static enet_buff_config_t enet0_tx_buff_cfg = {.buffer = (uint32_t)enet0_tx_buff .size = ENET0_TX_BUFF_SIZE }; -#if __USE_ENET_PTP +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP static enet_ptp_ts_update_t ptp_timestamp0 = {0, 0}; static enet_ptp_config_t ptp_config0 = {.timestamp_rollover_mode = enet_ts_dig_rollover_control, .update_method = enet_ptp_time_fine_update, @@ -52,6 +56,7 @@ static enet_ptp_config_t ptp_config0 = {.timestamp_rollover_mode = enet_ts_dig_r static hpm_enet_t enet0 = {.name = "E0", .base = HPM_ENET0, + .clock_name = clock_eth0, .irq_num = IRQn_ENET0, .inf = BOARD_ENET0_INF, .eth_dev = ð0_dev, @@ -60,6 +65,7 @@ static hpm_enet_t enet0 = {.name = "E0", .tx_buff_cfg = &enet0_tx_buff_cfg, .dma_rx_desc_tab = enet0_dma_rx_desc_tab, .dma_tx_desc_tab = enet0_dma_tx_desc_tab, + .frame = enet0_frame, #if !BOARD_ENET0_INF .int_refclk = BOARD_ENET0_INT_REF_CLK, #else @@ -67,7 +73,7 @@ static hpm_enet_t enet0 = {.name = "E0", .rx_delay = BOARD_ENET0_RX_DLY, #endif -#if __USE_ENET_PTP +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP .ptp_clk_src = BOARD_ENET0_PTP_CLOCK, .ptp_config = &ptp_config0, .ptp_timestamp = &ptp_timestamp0 @@ -94,6 +100,9 @@ __RW uint8_t enet1_rx_buff[ENET1_RX_BUFF_COUNT][ENET1_RX_BUFF_SIZE]; /* Ethernet ATTR_PLACE_AT_WITH_ALIGNMENT(".fast_ram", ENET_SOC_BUFF_ADDR_ALIGNMENT) __RW uint8_t enet1_tx_buff[ENET1_TX_BUFF_COUNT][ENET1_TX_BUFF_SIZE]; /* Ethernet1 Transmit Buffer */ +LWIP_MEMPOOL_DECLARE(enet1_rx_pool, ENET1_RX_BUFF_COUNT, sizeof(my_custom_pbuf_t), "Custom RX PBUF pool"); +static enet_frame_t enet1_frame[ENET1_RX_BUFF_COUNT] = {0}; + struct eth_device eth1_dev; static enet_device enet1_dev; static enet_buff_config_t enet1_rx_buff_cfg = {.buffer = (uint32_t)enet1_rx_buff, @@ -106,7 +115,7 @@ static enet_buff_config_t enet1_tx_buff_cfg = {.buffer = (uint32_t)enet1_tx_buff .size = ENET1_TX_BUFF_SIZE }; -#if __USE_ENET_PTP +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP static enet_ptp_ts_update_t ptp_timestamp1 = {0, 0}; static enet_ptp_config_t ptp_config1 = {.timestamp_rollover_mode = enet_ts_dig_rollover_control, .update_method = enet_ptp_time_fine_update, @@ -116,6 +125,7 @@ static enet_ptp_config_t ptp_config1 = {.timestamp_rollover_mode = enet_ts_dig_r static hpm_enet_t enet1 = {.name = "E1", .base = HPM_ENET1, + .clock_name = clock_eth1, .irq_num = IRQn_ENET1, .inf = BOARD_ENET1_INF, .eth_dev = ð1_dev, @@ -124,6 +134,8 @@ static hpm_enet_t enet1 = {.name = "E1", .tx_buff_cfg = &enet1_tx_buff_cfg, .dma_rx_desc_tab = enet1_dma_rx_desc_tab, .dma_tx_desc_tab = enet1_dma_tx_desc_tab, + .frame = enet1_frame, + #if !BOARD_ENET1_INF .int_refclk = BOARD_ENET1_INT_REF_CLK, #else @@ -131,7 +143,7 @@ static hpm_enet_t enet1 = {.name = "E1", .rx_delay = BOARD_ENET1_RX_DLY, #endif -#if __USE_ENET_PTP +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP .ptp_clk_src = BOARD_ENET1_PTP_CLOCK, .ptp_config = &ptp_config1, .ptp_timestamp = &ptp_timestamp1 @@ -149,6 +161,54 @@ static hpm_enet_t *s_geths[] = { #endif }; +void free_rx_dma_descriptor(void *p) +{ + enet_frame_t *frame; + + /* Release descriptors to DMA */ + frame = (enet_frame_t *)p; + + /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ + enet_rx_desc_t *dma_rx_desc = frame->rx_desc; + + for (uint32_t i = 0; i < frame->seg; i++) { + dma_rx_desc->rdes0_bm.own = 1; + dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); + } + + /* Clear Segment_Count */ + frame->seg = 0; + frame->free = 0; +} + +#ifdef BSP_USING_ETH0 +void enet0_pbuf_free_custom(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + my_custom_pbuf_t *my_pbuf = (my_custom_pbuf_t *)p; + + SYS_ARCH_PROTECT(old_level); + free_rx_dma_descriptor((void *)my_pbuf->dma_descriptor); + + LWIP_MEMPOOL_FREE(enet0_rx_pool, my_pbuf); + SYS_ARCH_UNPROTECT(old_level); +} +#endif + +#ifdef BSP_USING_ETH1 +void enet1_pbuf_free_custom(struct pbuf *p) +{ + SYS_ARCH_DECL_PROTECT(old_level); + my_custom_pbuf_t *my_pbuf = (my_custom_pbuf_t *)p; + + SYS_ARCH_PROTECT(old_level); + free_rx_dma_descriptor((void *)my_pbuf->dma_descriptor); + + LWIP_MEMPOOL_FREE(enet1_rx_pool, my_pbuf); + SYS_ARCH_UNPROTECT(old_level); +} +#endif + ATTR_WEAK uint8_t enet_get_mac_address(ENET_Type *ptr, uint8_t *mac) { uint32_t macl, mach; @@ -200,14 +260,13 @@ static rt_err_t hpm_enet_init(enet_device *init) board_init_enet_rmii_reference_clock(init->instance, init->int_refclk); } -#if ENET_SOC_RGMII_EN /* Set RGMII clock delay */ if (init->media_interface == enet_inf_rgmii) { - enet_rgmii_enable_clock(init->instance); + clock_add_to_group(init->clock_name, BOARD_RUNNING_CORE & 0x1); enet_rgmii_set_clock_delay(init->instance, init->tx_delay, init->rx_delay); } -#endif + /* Get the default interrupt config */ enet_get_default_interrupt_config(init->instance, &init->int_config); @@ -217,7 +276,7 @@ static rt_err_t hpm_enet_init(enet_device *init) /* Disable LPI interrupt */ enet_disable_lpi_interrupt(init->instance); -#if __USE_ENET_PTP +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP /* initialize PTP Clock */ board_init_enet_ptp_clock(init->instance); @@ -365,7 +424,7 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) if (dma_tx_desc->tdes0_bm.own != 0) { LOG_E("DMA tx desc buffer is not valid\n"); - return ERR_BUF; + return ERR_INPROGRESS; } buffer = (uint8_t *)(dma_tx_desc->tdes2_bm.buffer1); @@ -387,7 +446,7 @@ static rt_err_t rt_hpm_eth_tx(rt_device_t dev, struct pbuf * p) } /* Copy the remaining bytes */ - buffer = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); + buffer = (void *)sys_address_to_core_local_mem(BOARD_RUNNING_CORE, (uint32_t)buffer); SMEMCPY((uint8_t *)((uint8_t *)buffer + buffer_offset), (uint8_t *)((uint8_t *)q->payload + payload_offset), bytes_left_to_copy); @@ -416,7 +475,6 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) uint32_t rx_buff_size = enet_dev->desc.rx_buff_cfg.size; uint16_t len = 0; uint8_t *buffer; - enet_frame_t frame = {0, 0, 0}; enet_rx_desc_t *dma_rx_desc; uint32_t buffer_offset = 0; uint32_t payload_offset = 0; @@ -424,71 +482,47 @@ static struct pbuf *rt_hpm_eth_rx(rt_device_t dev) uint32_t i = 0; /* Get a received frame */ - frame = enet_get_received_frame_interrupt(&enet_dev->desc.rx_desc_list_cur, - &enet_dev->desc.rx_frame_info, - enet_dev->desc.rx_buff_cfg.count); + RT_ASSERT(!enet_dev->frame[enet_dev->cnt].free); + if (enet_dev->frame[enet_dev->cnt].free == 0) { + enet_dev->frame[enet_dev->cnt] = enet_get_received_frame_interrupt(&enet_dev->desc.rx_desc_list_cur, &enet_dev->desc.rx_frame_info, enet_dev->desc.rx_buff_cfg.count); + } else { + return p; + } /* Obtain the size of the packet and put it into the "len" variable. */ - len = frame.length; - buffer = (uint8_t *)frame.buffer; - + len = enet_dev->frame[enet_dev->cnt].length; + buffer = (uint8_t *)sys_address_to_core_local_mem(BOARD_RUNNING_CORE, enet_dev->frame[enet_dev->cnt].buffer); LOG_D("The current received frame length : %d\n", len); if (len > 0) { - /* allocate a pbuf chain of pbufs from the Lwip buffer pool */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + enet_dev->frame[enet_dev->cnt].free = 1; - if (p != NULL) - { - dma_rx_desc = frame.rx_desc; - buffer_offset = 0; - for (q = p; q != NULL; q = q->next) - { - bytes_left_to_copy = q->len; - payload_offset = 0; - - /* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size*/ - while ((bytes_left_to_copy + buffer_offset) > rx_buff_size) - { - /* Copy data to pbuf */ - SMEMCPY((uint8_t *)((uint8_t *)q->payload + payload_offset), (uint8_t *)((uint8_t *)buffer + buffer_offset), (rx_buff_size - buffer_offset)); - - /* Point to next descriptor */ - dma_rx_desc = (enet_rx_desc_t *)(dma_rx_desc->rdes3_bm.next_desc); - buffer = (uint8_t *)(dma_rx_desc->rdes2_bm.buffer1); - - bytes_left_to_copy = bytes_left_to_copy - (rx_buff_size - buffer_offset); - payload_offset = payload_offset + (rx_buff_size - buffer_offset); - buffer_offset = 0; - } - /* Copy remaining data in pbuf */ - q->payload = (void *)sys_address_to_core_local_mem(0, (uint32_t)buffer); - buffer_offset = buffer_offset + bytes_left_to_copy; - } +#ifdef BSP_USING_ETH0 + if (enet_dev->instance == HPM_ENET0) { + my_custom_pbuf_t *my_pbuf = (my_custom_pbuf_t *)LWIP_MEMPOOL_ALLOC(enet0_rx_pool); + my_pbuf->p.custom_free_function = enet0_pbuf_free_custom; + my_pbuf->dma_descriptor = (void *)&enet_dev->frame[enet_dev->cnt]; + p = pbuf_alloced_custom(PBUF_RAW, enet_dev->frame[enet_dev->cnt].length, PBUF_REF, &my_pbuf->p, buffer, enet_dev->desc.rx_buff_cfg.size); + enet_dev->cnt = ++enet_dev->cnt % enet_dev->desc.rx_buff_cfg.count; } +#endif - /* Release descriptors to DMA */ - /* Point to first descriptor */ - dma_rx_desc = frame.rx_desc; - - /* Set Own bit in Rx descriptors: gives the buffers back to DMA */ - for (i = 0; i < enet_dev->desc.rx_frame_info.seg_count; i++) - { - dma_rx_desc->rdes0_bm.own = 1; - dma_rx_desc = (enet_rx_desc_t*)(dma_rx_desc->rdes3_bm.next_desc); +#ifdef BSP_USING_ETH1 + if (enet_dev->instance == HPM_ENET1) { + my_custom_pbuf_t *my_pbuf = (my_custom_pbuf_t *)LWIP_MEMPOOL_ALLOC(enet1_rx_pool); + my_pbuf->p.custom_free_function = enet1_pbuf_free_custom; + my_pbuf->dma_descriptor = (void *)&enet_dev->frame[enet_dev->cnt]; + p = pbuf_alloced_custom(PBUF_RAW, enet_dev->frame[enet_dev->cnt].length, PBUF_REF, &my_pbuf->p, buffer, enet_dev->desc.rx_buff_cfg.size); + enet_dev->cnt = ++enet_dev->cnt % enet_dev->desc.rx_buff_cfg.count; } - +#endif /* Clear Segment_Count */ enet_dev->desc.rx_frame_info.seg_count = 0; } /* Resume Rx Process */ - if (ENET_DMA_STATUS_RU_GET(enet_dev->instance->DMA_STATUS)) - { - enet_dev->instance->DMA_STATUS = ENET_DMA_STATUS_RU_MASK; - enet_dev->instance->DMA_RX_POLL_DEMAND = 1; - } + enet_rx_resume(enet_dev->instance); return p; } @@ -520,25 +554,33 @@ void isr_enet(hpm_enet_t *obj) } #ifdef BSP_USING_ETH0 +SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0) void isr_enet0(void) { isr_enet(&enet0); } -SDK_DECLARE_EXT_ISR_M(IRQn_ENET0, isr_enet0) #endif #ifdef BSP_USING_ETH1 +SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1) void isr_enet1(void) { isr_enet(&enet1); } -SDK_DECLARE_EXT_ISR_M(IRQn_ENET1, isr_enet1) #endif int rt_hw_eth_init(void) { rt_err_t err = RT_ERROR; +#ifdef BSP_USING_ETH0 + LWIP_MEMPOOL_INIT(enet0_rx_pool); +#endif + +#ifdef BSP_USING_ETH1 + LWIP_MEMPOOL_INIT(enet1_rx_pool); +#endif + for (uint32_t i = 0; i < ARRAY_SIZE(s_geths); i++) { /* Clear memory */ @@ -566,6 +608,9 @@ int rt_hw_eth_init(void) /* Set instance */ s_geths[i]->enet_dev->instance = s_geths[i]->base; + /* Set clock name */ + s_geths[i]->enet_dev->clock_name = s_geths[i]->clock_name; + /* Set media interface */ s_geths[i]->enet_dev->media_interface = s_geths[i]->inf ? enet_inf_rgmii : enet_inf_rmii; @@ -580,7 +625,7 @@ int rt_hw_eth_init(void) } -#if __USE_ENET_PTP +#if defined(__USE_ENET_PTP) && __USE_ENET_PTP /* Set PTP function */ s_geths[i]->enet_dev->ptp_clk_src = s_geths[i]->ptp_clk_src; s_geths[i]->enet_dev->ptp_config = *s_geths[i]->ptp_config; @@ -590,6 +635,10 @@ int rt_hw_eth_init(void) /* Set the irq number */ s_geths[i]->enet_dev->irq_number = s_geths[i]->irq_num; + /* Set the frame buffer and counter */ + s_geths[i]->enet_dev->frame = s_geths[i]->frame; + s_geths[i]->enet_dev->cnt = 0; + /* Set the parent parameters */ s_geths[i]->eth_dev->parent.init = rt_hpm_eth_init; s_geths[i]->eth_dev->parent.open = rt_hpm_eth_open; diff --git a/bsp/hpmicro/libraries/drivers/drv_enet_phy.c b/bsp/hpmicro/libraries/drivers/drv_enet_phy.c index 6ded32f75f3..0e809a25646 100644 --- a/bsp/hpmicro/libraries/drivers/drv_enet_phy.c +++ b/bsp/hpmicro/libraries/drivers/drv_enet_phy.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023-2024 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -11,6 +11,10 @@ #include "rtthread.h" +#if !defined(RT_USING_PHY) +#error Please enable phy abstraction layer or remove the current file from your project! +#endif + #ifdef RT_USING_PHY #include #include @@ -200,7 +204,7 @@ static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *d static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) { - enet_phy_status_t phy_status; + enet_phy_status_t phy_status = {0}; if (phy->bus->hw_obj == HPM_ENET0) { diff --git a/bsp/hpmicro/libraries/drivers/drv_ewdt.c b/bsp/hpmicro/libraries/drivers/drv_ewdt.c index 40a6502e7d1..02496c2c36c 100644 --- a/bsp/hpmicro/libraries/drivers/drv_ewdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_ewdt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2023 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -39,38 +39,38 @@ static void hpm_wdog_isr(rt_watchdog_t *wdt); #if defined(BSP_USING_EWDG0) rt_watchdog_t wdog0; +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG0, wdog0_isr) void wdog0_isr(void) { hpm_wdog_isr(&wdog0); } -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG0, wdog0_isr) #endif #if defined(BSP_USING_EWDG1) rt_watchdog_t wdog1; +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG1, wdog1_isr) void wdog1_isr(void) { hpm_wdog_isr(&wdog1); } -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG1, wdog1_isr) #endif #if defined(BSP_USING_EWDG2) rt_watchdog_t wdog2; +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG2, wdog2_isr) void wdog2_isr(void) { hpm_wdog_isr(&wdog2); } -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG2, wdog2_isr) #endif #if defined(BSP_USING_EWDG3) rt_watchdog_t wdog3; +SDK_DECLARE_EXT_ISR_M(IRQn_EWDG3, wdog3_isr) void wdog3_isr(void) { hpm_wdog_isr(&wdog3); } -SDK_DECLARE_EXT_ISR_M(IRQn_EWDG3, wdog3_isr) #endif static hpm_wdog_t wdogs[] = { @@ -106,7 +106,7 @@ static hpm_wdog_t wdogs[] = { #ifdef BSP_USING_EWDG3 { - .wdog_name = HPM_EWDG3, + .wdog_base = HPM_EWDG3, .device_name = "wdt3", .clock_name = clock_watchdog3, .irq_num = IRQn_EWDG3, @@ -127,7 +127,7 @@ static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) ewdg_config_t config; - printf("Init Watchdog\n"); + LOG_I("Init Watchdog\n"); ewdg_get_default_config(base, &config); /* Enable EWDG */ config.enable_watchdog = true; @@ -211,7 +211,7 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) /* Initialize the EWDG */ hpm_stat_t status = ewdg_init(base, &config); if (status != status_success) { - printf(" EWDG initialization failed, error_code=%d\n", status); + LOG_E(" EWDG initialization failed, error_code=%d\n", status); } /* delay 1ms to ensure above configure take effective*/ rt_thread_mdelay(1); diff --git a/bsp/hpmicro/libraries/drivers/drv_gpio.c b/bsp/hpmicro/libraries/drivers/drv_gpio.c index 45637250334..663e7918cf6 100644 --- a/bsp/hpmicro/libraries/drivers/drv_gpio.c +++ b/bsp/hpmicro/libraries/drivers/drv_gpio.c @@ -20,7 +20,6 @@ #ifdef BSP_USING_GPIO #include #include -#include "board.h" #include "drv_gpio.h" #include "hpm_gpio_drv.h" #include "hpm_gpiom_drv.h" @@ -32,6 +31,7 @@ typedef struct { uint32_t gpio_idx; uint32_t irq_num; + uint8_t irq_priority; struct rt_pin_irq_hdr *pin_irq_tbl; } gpio_irq_map_t; @@ -71,37 +71,134 @@ static struct rt_pin_irq_hdr hpm_gpio0_z_pin_hdr[32]; static const gpio_irq_map_t hpm_gpio_irq_map[] = { #ifdef GPIO_DO_GPIOA - { GPIO_IE_GPIOA, IRQn_GPIO0_A, hpm_gpio0_a_pin_hdr }, + { + GPIO_IE_GPIOA, + IRQn_GPIO0_A, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_a_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOB - { GPIO_IE_GPIOB, IRQn_GPIO0_B, hpm_gpio0_b_pin_hdr }, + { + GPIO_IE_GPIOB, + IRQn_GPIO0_B, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_b_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOC - { GPIO_IE_GPIOC, IRQn_GPIO0_C, hpm_gpio0_c_pin_hdr }, + { + GPIO_IE_GPIOC, + IRQn_GPIO0_C, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_c_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOD - { GPIO_IE_GPIOD, IRQn_GPIO0_D, hpm_gpio0_d_pin_hdr }, + { + GPIO_IE_GPIOD, + IRQn_GPIO0_D, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_d_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOE - { GPIO_IE_GPIOE, IRQn_GPIO0_E, hpm_gpio0_e_pin_hdr }, + { + GPIO_IE_GPIOE, + IRQn_GPIO0_E, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_e_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOF - { GPIO_IE_GPIOF, IRQn_GPIO0_F, hpm_gpio0_f_pin_hdr }, + { + GPIO_IE_GPIOF, + IRQn_GPIO0_F, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_f_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOV - { GPIO_IE_GPIOV, IRQn_GPIO0_V, hpm_gpio0_v_pin_hdr }, + { + GPIO_IE_GPIOV, + IRQn_GPIO0_V, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_v_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOW - { GPIO_IE_GPIOW, IRQn_GPIO0_W, hpm_gpio0_w_pin_hdr }, + { + GPIO_IE_GPIOW, + IRQn_GPIO0_W, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_w_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOX - { GPIO_IE_GPIOX, IRQn_GPIO0_X, hpm_gpio0_x_pin_hdr }, + { + GPIO_IE_GPIOX, + IRQn_GPIO0_X, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_x_pin_hdr }, #endif #ifdef GPIO_DO_GPIOY - { GPIO_IE_GPIOY, IRQn_GPIO0_Y, hpm_gpio0_y_pin_hdr }, + { + GPIO_IE_GPIOY, + IRQn_GPIO0_Y, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_y_pin_hdr + }, #endif #ifdef GPIO_DO_GPIOZ - { GPIO_IE_GPIOZ, IRQn_GPIO0_Z, hpm_gpio0_z_pin_hdr }, + { + GPIO_IE_GPIOZ, + IRQn_GPIO0_Z, +#if defined(BSP_GPIO_IRQ_PRIORITY) + BSP_GPIO_IRQ_PRIORITY, +#else + 1, +#endif + hpm_gpio0_z_pin_hdr }, #endif }; @@ -136,6 +233,21 @@ static int hpm_get_gpio_irq_num(uint32_t gpio_idx) return irq_num; } +static int hpm_get_gpio_irq_priority(uint32_t gpio_idx) +{ + int irq_priority = -1; + + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_gpio_irq_map); i++) + { + if (hpm_gpio_irq_map[i].gpio_idx == gpio_idx) + { + irq_priority = hpm_gpio_irq_map[i].irq_priority; + break; + } + } + return irq_priority; +} + static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base) { /* Lookup the Pin IRQ Header Table */ @@ -164,91 +276,91 @@ static void hpm_gpio_isr(uint32_t gpio_idx, GPIO_Type *base) } #ifdef GPIO_DO_GPIOA +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr) void gpioa_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOA, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_A, gpioa_isr) #endif #ifdef GPIO_DO_GPIOB +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr) void gpiob_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOB, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_B, gpiob_isr) #endif #ifdef GPIO_DO_GPIOC +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr) void gpioc_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOC, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_C, gpioc_isr) #endif #ifdef GPIO_DO_GPIOD +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr) void gpiod_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOD, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_D, gpiod_isr) #endif #ifdef GPIO_DO_GPIOE +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr) void gpioe_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOE, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_E, gpioe_isr) #endif #ifdef GPIO_DO_GPIOF +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr) void gpiof_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOF, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_F, gpiof_isr) #endif #ifdef GPIO_DO_GPIOV +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_V, gpiox_isr) void gpiov_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOV, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_V, gpiox_isr) #endif #ifdef GPIO_DO_GPIOW +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_W, gpiox_isr) void gpiow_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOW, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_W, gpiox_isr) #endif #ifdef GPIO_DO_GPIOX +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr) void gpiox_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOX, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_X, gpiox_isr) #endif #ifdef GPIO_DO_GPIOY +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr) void gpioy_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOY, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Y, gpioy_isr) #endif #ifdef GPIO_DO_GPIOZ +SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr) void gpioz_isr(void) { hpm_gpio_isr(GPIO_IF_GPIOZ, HPM_GPIO0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPIO0_Z, gpioz_isr) #endif /** @@ -317,7 +429,7 @@ static void hpm_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) break; case PIN_MODE_INPUT_PULLUP: gpio_set_pin_input(HPM_GPIO0, gpio_idx, pin_idx); - HPM_IOC->PAD[pin].PAD_CTL |= IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); + HPM_IOC->PAD[pin].PAD_CTL = IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1); break; case PIN_MODE_OUTPUT_OD: gpio_set_pin_output(HPM_GPIO0, gpio_idx, pin_idx); @@ -423,9 +535,10 @@ static rt_err_t hpm_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_u break; } gpio_config_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx, trigger); - uint32_t irq_num = hpm_get_gpio_irq_num(gpio_idx); + rt_uint32_t irq_num = hpm_get_gpio_irq_num(gpio_idx); + rt_uint32_t irq_priority = hpm_get_gpio_irq_priority(gpio_idx); gpio_enable_pin_interrupt(HPM_GPIO0, gpio_idx, pin_idx); - intc_m_enable_irq_with_priority(irq_num, 1); + intc_m_enable_irq_with_priority(irq_num, irq_priority); } else if (enabled == PIN_IRQ_DISABLE) { diff --git a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c index 5b6118f69c8..7b29c99b513 100644 --- a/bsp/hpmicro/libraries/drivers/drv_hwtimer.c +++ b/bsp/hpmicro/libraries/drivers/drv_hwtimer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -14,6 +14,7 @@ #include "board.h" #include "hpm_gptmr_drv.h" +#include "hpm_clock_drv.h" typedef struct _hpm_gptimer { @@ -23,6 +24,7 @@ typedef struct _hpm_gptimer uint32_t channel; clock_name_t clock_name; int32_t irq_num; + uint8_t irq_priority; } hpm_gptimer_t; static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state); @@ -50,28 +52,116 @@ static const struct rt_hwtimer_info hpm_hwtimer_info = { #ifdef BSP_USING_GPTMR0 -static hpm_gptimer_t timer0 = {.name = "GPT0", .base = HPM_GPTMR0, .clock_name = clock_gptmr0, .irq_num = IRQn_GPTMR0 }; +static hpm_gptimer_t timer0 = +{ + .name = "GPT0", + .base = HPM_GPTMR0, + .clock_name = clock_gptmr0, + .irq_num = IRQn_GPTMR0, +#if defined(BSP_GPTMR0_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR1 -static hpm_gptimer_t timer1 = {.name = "GPT1", .base = HPM_GPTMR1, .clock_name = clock_gptmr1, .irq_num = IRQn_GPTMR1 }; +static hpm_gptimer_t timer1 = +{ + .name = "GPT1", + .base = HPM_GPTMR1, + .clock_name = clock_gptmr1, + .irq_num = IRQn_GPTMR1, +#if defined(BSP_GPTMR1_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR2 -static hpm_gptimer_t timer2 = {.name = "GPT2", .base = HPM_GPTMR2, .clock_name = clock_gptmr2, .irq_num = IRQn_GPTMR2 }; +static hpm_gptimer_t timer2 = +{ + .name = "GPT2", + .base = HPM_GPTMR2, + .clock_name = clock_gptmr2, + .irq_num = IRQn_GPTMR2, +#if defined(BSP_GPTMR2_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR2_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR3 -static hpm_gptimer_t timer3 = {.name = "GPT3", .base = HPM_GPTMR3, .clock_name = clock_gptmr3, .irq_num = IRQn_GPTMR3 }; +static hpm_gptimer_t timer3 = +{ + .name = "GPT3", + .base = HPM_GPTMR3, + .clock_name = clock_gptmr3, + .irq_num = IRQn_GPTMR3, +#if defined(BSP_GPTMR3_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR3_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR4 -static hpm_gptimer_t timer4 = {.name = "GPT4", .base = HPM_GPTMR4, .clock_name = clock_gptmr4, .irq_num = IRQn_GPTMR4 }; +static hpm_gptimer_t timer4 = +{ + .name = "GPT4", + .base = HPM_GPTMR4, + .clock_name = clock_gptmr4, + .irq_num = IRQn_GPTMR4, +#if defined(BSP_GPTMR4_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR4_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR5 -static hpm_gptimer_t timer5 = {.name = "GPT5", .base = HPM_GPTMR5, .clock_name = clock_gptmr5, .irq_num = IRQn_GPTMR5 }; +static hpm_gptimer_t timer5 = +{ + .name = "GPT5", + .base = HPM_GPTMR5, + .clock_name = clock_gptmr5, + .irq_num = IRQn_GPTMR5, +#if defined(BSP_GPTMR5_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR5_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR6 -static hpm_gptimer_t timer6 = {.name = "GPT6", .base = HPM_GPTMR6, .clock_name = clock_gptmr6, .irq_num = IRQn_GPTMR6 }; +static hpm_gptimer_t timer6 = +{ + .name = "GPT6", + .base = HPM_GPTMR6, + .clock_name = clock_gptmr6, + .irq_num = IRQn_GPTMR6, +#if defined(BSP_GPTMR6_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR6_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif #ifdef BSP_USING_GPTMR7 -static hpm_gptimer_t timer7 = {.name = "GPT7", .base = HPM_GPTMR7, .clock_name = clock_gptmr7, .irq_num = IRQn_GPTMR7 }; +static hpm_gptimer_t timer7 = +{ + .name = "GPT7", + .base = HPM_GPTMR7, + .clock_name = clock_gptmr7, + .irq_num = IRQn_GPTMR7, +#if defined(BSP_GPTMR7_IRQ_PRIORITY) + .irq_priority = BSP_GPTMR7_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +}; #endif @@ -103,67 +193,68 @@ static hpm_gptimer_t *s_gptimers[] = { }; #ifdef BSP_USING_GPTMR0 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR0, gptmr0_isr); void gptmr0_isr(void) { hpm_hwtmr_isr(&timer0); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR0, gptmr0_isr); #endif #ifdef BSP_USING_GPTMR1 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR1, gptmr1_isr); void gptmr1_isr(void) { hpm_hwtmr_isr(&timer1); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR1, gptmr1_isr); #endif #ifdef BSP_USING_GPTMR2 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR2, gptmr2_isr); void gptmr2_isr(void) { hpm_hwtmr_isr(&timer2); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR2, gptmr2_isr); #endif #ifdef BSP_USING_GPTMR3 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR3, gptmr3_isr); void gptmr3_isr(void) { hpm_hwtmr_isr(&timer3); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR3, gptmr3_isr); #endif #ifdef BSP_USING_GPTMR4 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR4, gptmr4_isr); void gptmr4_isr(void) { hpm_hwtmr_isr(&timer4); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR4, gptmr4_isr); #endif #ifdef BSP_USING_GPTMR5 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR5, gptmr5_isr); void gptmr5_isr(void) { hpm_hwtmr_isr(&timer5); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR5, gptmr5_isr); #endif #ifdef BSP_USING_GPTMR6 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR6, gptmr6_isr); void gptmr6_isr(void) { hpm_hwtmr_isr(&timer6); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR6, gptmr6_isr); #endif #ifdef BSP_USING_GPTMR7 +SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR7, gptmr7_isr); void gptmr7_isr(void) { hpm_hwtmr_isr(&timer7); } -SDK_DECLARE_EXT_ISR_M(IRQn_GPTMR7, gptmr7_isr); + #endif static void hpm_hwtmr_isr(hpm_gptimer_t *timer) @@ -184,7 +275,8 @@ static void hpm_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) if (state == 1) { - hpm_gptmr->timer.freq = board_init_gptmr_clock(base); + clock_add_to_group(hpm_gptmr->clock_name, BOARD_RUNNING_CORE & 0x1); + hpm_gptmr->timer.freq = clock_get_frequency(hpm_gptmr->clock_name); gptmr_channel_get_default_config(base, &config); gptmr_channel_config(base, hpm_gptmr->channel, &config, false); } @@ -210,7 +302,7 @@ static rt_err_t hpm_hwtimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtim gptmr_channel_update_count(base, hpm_gptmr->channel, 0); gptmr_start_counter(base, hpm_gptmr->channel); - intc_m_enable_irq_with_priority(hpm_gptmr->irq_num, 1); + intc_m_enable_irq_with_priority(hpm_gptmr->irq_num, hpm_gptmr->irq_priority); return RT_EOK; } diff --git a/bsp/hpmicro/libraries/drivers/drv_i2c.c b/bsp/hpmicro/libraries/drivers/drv_i2c.c index f5a676df739..15481ca8c0e 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2c.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2c.c @@ -37,6 +37,7 @@ struct hpm_i2c dma_resource_t dma; rt_uint8_t i2c_irq; rt_uint8_t is_read; + rt_uint8_t irq_priority; }; static struct hpm_i2c hpm_i2cs[] = @@ -51,6 +52,11 @@ static struct hpm_i2c hpm_i2cs[] = #endif .dmamux = HPM_DMA_SRC_I2C0, .i2c_irq = IRQn_I2C0, +#if defined(BSP_I2C0_IRQ_PRIORITY) + .irq_priority = BSP_I2C0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }, #endif #if defined(BSP_USING_I2C1) @@ -63,6 +69,11 @@ static struct hpm_i2c hpm_i2cs[] = #endif .dmamux = HPM_DMA_SRC_I2C1, .i2c_irq = IRQn_I2C1, +#if defined(BSP_I2C1_IRQ_PRIORITY) + .irq_priority = BSP_I2C1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }, #endif #if defined(BSP_USING_I2C2) @@ -75,6 +86,11 @@ static struct hpm_i2c hpm_i2cs[] = #endif .dmamux = HPM_DMA_SRC_I2C2, .i2c_irq = IRQn_I2C2, +#if defined(BSP_I2C2_IRQ_PRIORITY) + .irq_priority = BSP_I2C2_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }, #endif #if defined(BSP_USING_I2C3) @@ -87,11 +103,83 @@ static struct hpm_i2c hpm_i2cs[] = #endif .dmamux = HPM_DMA_SRC_I2C3, .i2c_irq = IRQn_I2C3, +#if defined(BSP_I2C3_IRQ_PRIORITY) + .irq_priority = BSP_I2C3_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + }, +#endif +#if defined(BSP_USING_I2C4) + { + .base = HPM_I2C4, + .bus_name = "i2c4", + .clk_name = clock_i2c4, +#if defined(BSP_I2C4_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C4, + .i2c_irq = IRQn_I2C4, +#if defined(BSP_I2C4_IRQ_PRIORITY) + .irq_priority = BSP_I2C4_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + }, +#endif +#if defined(BSP_USING_I2C5) + { + .base = HPM_I2C5, + .bus_name = "i2c5", + .clk_name = clock_i2c5, +#if defined(BSP_I2C5_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C5, + .i2c_irq = IRQn_I2C5, +#if defined(BSP_I2C5_IRQ_PRIORITY) + .irq_priority = BSP_I2C5_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + }, +#endif +#if defined(BSP_USING_I2C6) + { + .base = HPM_I2C6, + .bus_name = "i2c6", + .clk_name = clock_i2c6, +#if defined(BSP_I2C6_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C6, + .i2c_irq = IRQn_I2C6, +#if defined(BSP_I2C6_IRQ_PRIORITY) + .irq_priority = BSP_I2C6_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + }, +#endif +#if defined(BSP_USING_I2C7) + { + .base = HPM_I2C7, + .bus_name = "i2c7", + .clk_name = clock_i2c7, +#if defined(BSP_I2C7_USING_DMA) + .enable_dma = RT_TRUE, +#endif + .dmamux = HPM_DMA_SRC_I2C7, + .i2c_irq = IRQn_I2C7, +#if defined(BSP_I2C7_IRQ_PRIORITY) + .irq_priority = BSP_I2C7_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif }, #endif }; -static hpm_stat_t i2c_transfer(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, uint16_t flags); + static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num); static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size); static hpm_stat_t i2c_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t dst, uint32_t size); @@ -126,37 +214,70 @@ static inline void handle_i2c_isr(I2C_Type *ptr) } #if defined(BSP_USING_I2C0) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C0, i2c0_isr); void i2c0_isr(void) { handle_i2c_isr(HPM_I2C0); } -SDK_DECLARE_EXT_ISR_M(IRQn_I2C0, i2c0_isr); #endif #if defined(BSP_USING_I2C1) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C1, i2c1_isr); void i2c1_isr(void) { handle_i2c_isr(HPM_I2C1); } -SDK_DECLARE_EXT_ISR_M(IRQn_I2C1, i2c1_isr); #endif #if defined(BSP_USING_I2C2) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C2, i2c2_isr); void i2c2_isr(void) { handle_i2c_isr(HPM_I2C2); } -SDK_DECLARE_EXT_ISR_M(IRQn_I2C2, i2c2_isr); #endif #if defined(BSP_USING_I2C3) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C3, i2c3_isr); void i2c3_isr(void) { handle_i2c_isr(HPM_I2C3); } -SDK_DECLARE_EXT_ISR_M(IRQn_I2C3, i2c3_isr); #endif +#if defined(BSP_USING_I2C4) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C4, i2c4_isr); +void i2c4_isr(void) +{ + handle_i2c_isr(HPM_I2C4); +} +#endif + +#if defined(BSP_USING_I2C5) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C5, i2c5_isr); +void i2c5_isr(void) +{ + handle_i2c_isr(HPM_I2C5); +} +#endif + +#if defined(BSP_USING_I2C6) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C6, i2c6_isr); +void i2c6_isr(void) +{ + handle_i2c_isr(HPM_I2C6); +} +#endif + +#if defined(BSP_USING_I2C7) +SDK_DECLARE_EXT_ISR_M(IRQn_I2C7, i2c7_isr); +void i2c7_isr(void) +{ + handle_i2c_isr(HPM_I2C7); +} +#endif + + static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size) { dma_handshake_config_t config; @@ -241,7 +362,6 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct } else { - aligned_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_buf); /* The allocated pointer is always RT_ALIGN_SIZE aligned */ raw_alloc_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); RT_ASSERT(raw_alloc_buf != RT_NULL); @@ -395,7 +515,7 @@ int rt_hw_i2c_init(void) for (uint32_t i = 0; i < sizeof(hpm_i2cs) / sizeof(hpm_i2cs[0]); i++) { init_i2c_pins(hpm_i2cs[i].base); - clock_add_to_group(hpm_i2cs[i].clk_name, 0); + clock_add_to_group(hpm_i2cs[i].clk_name, BOARD_RUNNING_CORE & 0x1); clock_set_source_divider(hpm_i2cs[i].clk_name, clk_src_osc24m, 1U); config.i2c_mode = i2c_mode_normal; @@ -416,7 +536,7 @@ int rt_hw_i2c_init(void) } dma_mgr_install_chn_tc_callback(&hpm_i2cs[i].dma, i2c_dma_channel_tc_callback, (void *)&hpm_i2cs[i]); dma_mgr_enable_dma_irq_with_priority(&hpm_i2cs[i].dma, 1); - intc_m_enable_irq_with_priority(hpm_i2cs[i].i2c_irq, 2); + intc_m_enable_irq_with_priority(hpm_i2cs[i].i2c_irq, hpm_i2cs[i].irq_priority); i2c_disable_irq(hpm_i2cs[i].base, I2C_EVENT_TRANSACTION_COMPLETE); rt_sprintf(sem_name, "%s_s", hpm_i2cs[i].bus_name); hpm_i2cs[i].xfer_sem = rt_sem_create(sem_name, 0, RT_IPC_FLAG_PRIO); diff --git a/bsp/hpmicro/libraries/drivers/drv_i2s.c b/bsp/hpmicro/libraries/drivers/drv_i2s.c index 4108e4fb686..3c966186226 100644 --- a/bsp/hpmicro/libraries/drivers/drv_i2s.c +++ b/bsp/hpmicro/libraries/drivers/drv_i2s.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023 HPMicro + * Copyright (c) 2022-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -28,6 +28,8 @@ #include "drv_i2s.h" #include "drivers/dev_audio.h" +extern uint32_t rtt_board_init_i2s_clock(I2S_Type *ptr); + static rt_ssize_t hpm_i2s_transmit(struct rt_audio_device* audio, const void* writeBuf, void* readBuf, rt_size_t size); /** @@ -89,7 +91,7 @@ static struct hpm_i2s hpm_i2s_set[] = #if defined(BSP_USING_I2S1) && defined(HPM_I2S1) { .dev_name = "i2s1", - .base = HPM_I2S1; + .base = HPM_I2S1, .clk_name = clock_i2s1, .rx_dma_req = HPM_DMA_SRC_I2S1_RX, .tx_dma_req = HPM_DMA_SRC_I2S1_TX, @@ -147,7 +149,7 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) struct hpm_i2s* hpm_audio = (struct hpm_i2s*)audio->parent.user_data; init_i2s_pins(hpm_audio->base); - board_init_i2s_clock(hpm_audio->base); + rtt_board_init_i2s_clock(hpm_audio->base); /* enable dma request */ i2s_enable_rx_dma_request(hpm_audio->base); @@ -165,6 +167,7 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) transfer.channel_slot_mask = I2S_CHANNEL_SLOT_MASK(0); /* one channel */ transfer.audio_depth = i2s_audio_depth_16_bits; transfer.master_mode = true; + transfer.data_line = BOARD_APP_I2S_RX_DATA_LINE; hpm_audio->transfer = transfer; /* record i2s parameter to audio_config */ hpm_audio->audio_config.samplerate = 48000U; @@ -172,7 +175,7 @@ static rt_err_t hpm_i2s_init(struct rt_audio_device* audio) hpm_audio->audio_config.channels = 1; if (status_success != i2s_config_transfer(hpm_audio->base, mclk_hz, &transfer)) { - LOG_E("dao_i2s configure transfer failed\n"); + LOG_E("i2s configure transfer failed\n"); return -RT_ERROR; } @@ -410,15 +413,17 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio /* Stop I2S transfer if the I2S needs to be re-configured */ bool is_enabled = i2s_is_enabled(hpm_audio->base); + i2s_disable(hpm_audio->base); + i2s_reset_tx_rx(hpm_audio->base); if (is_enabled) { if (hpm_audio->i2s_state == hpm_i2s_state_read) { - dma_abort_channel(hpm_audio->rx_dma_resource.base, hpm_audio->rx_dma_resource.channel); + dma_abort_channel(hpm_audio->rx_dma_resource.base, 1u << hpm_audio->rx_dma_resource.channel); } if (hpm_audio->i2s_state == hpm_i2s_state_write) { - dma_abort_channel(hpm_audio->tx_dma_resource.base, hpm_audio->tx_dma_resource.channel); + dma_abort_channel(hpm_audio->tx_dma_resource.base, 1u << hpm_audio->tx_dma_resource.channel); } } if (status_success != i2s_config_transfer(hpm_audio->base, clock_get_frequency(hpm_audio->clk_name), &hpm_audio->transfer)) @@ -429,6 +434,14 @@ static rt_err_t hpm_i2s_configure(struct rt_audio_device* audio, struct rt_audio /* Restore I2S to previous state */ if (is_enabled) { + if (hpm_audio->i2s_state == hpm_i2s_state_read) + { + i2s_disable_rx_dma_request(hpm_audio->base); + if (I2S_FIFO_SIZE != hpm_i2s_transmit(&hpm_audio->audio, NULL, hpm_audio->rx_buff, I2S_FIFO_SIZE)) { + return -RT_ERROR; + } + i2s_enable_rx_dma_request(hpm_audio->base); + } i2s_enable(hpm_audio->base); } @@ -500,12 +513,12 @@ static rt_err_t hpm_i2s_stop(struct rt_audio_device* audio, int stream) if (stream == AUDIO_STREAM_REPLAY) { dma_resource_t *dma_resource = &hpm_audio->tx_dma_resource; - dma_abort_channel(dma_resource->base, dma_resource->channel); + dma_abort_channel(dma_resource->base, 1u << dma_resource->channel); dma_mgr_release_resource(dma_resource); } else if (stream == AUDIO_STREAM_RECORD) { dma_resource_t *dma_resource = &hpm_audio->rx_dma_resource; - dma_abort_channel(dma_resource->base, dma_resource->channel); + dma_abort_channel(dma_resource->base, 1u << dma_resource->channel); dma_mgr_release_resource(dma_resource); } else { return -RT_ERROR; diff --git a/bsp/hpmicro/libraries/drivers/drv_lcd.c b/bsp/hpmicro/libraries/drivers/drv_lcd.c index 645b04e7101..1fa4951f9d6 100644 --- a/bsp/hpmicro/libraries/drivers/drv_lcd.c +++ b/bsp/hpmicro/libraries/drivers/drv_lcd.c @@ -26,6 +26,7 @@ struct hpm_lcd { LCDC_Type *lcd_base; rt_uint8_t lcd_irq; + rt_uint8_t lcd_irq_priority; struct rt_semaphore lcd_lock; char *bus_name; struct rt_device parent; @@ -58,6 +59,11 @@ static struct hpm_lcd hpm_lcds[] = .lcd_buffer_size = (PANEL_SIZE_WIDTH * PANEL_SIZE_HEIGHT * LCD_BITS_PER_PIXEL / 8), .lcd_base = HPM_LCDC, .lcd_irq = BOARD_LCD_IRQ, +#if defined(BSP_RTT_LCD_IRQ_PRIORITY) + .lcd_irq_priority = BSP_RTT_LCD_IRQ_PRIORITY, +#else + .lcd_irq_priority = 7, +#endif .parent.type = RT_Device_Class_Graphic, #ifdef RT_USING_DEVICE_OPS .parent.ops = &hpm_lcd_ops, @@ -72,13 +78,13 @@ static struct hpm_lcd hpm_lcds[] = }, }; +SDK_DECLARE_EXT_ISR_M(BOARD_LCD_IRQ, isr_lcd_d0) void isr_lcd_d0(void) { lcdc_disable_interrupt(hpm_lcds[0].lcd_base, LCDC_INT_EN_VSYNC_MASK); rt_sem_release(&hpm_lcds[0].lcd_lock); lcdc_clear_status(hpm_lcds[0].lcd_base, LCDC_ST_VSYNC_MASK); } -SDK_DECLARE_EXT_ISR_M(BOARD_LCD_IRQ, isr_lcd_d0) static rt_err_t hpm_lcd_init(struct rt_device *device) { @@ -199,7 +205,7 @@ static int hpm_lcdc_init(struct hpm_lcd *lcd, struct rt_device_graphic_info *inf lcdc_turn_on_display(lcd->lcd_base); lcdc_enable_interrupt(lcd->lcd_base, LCDC_INT_EN_VSYNC_MASK); - intc_m_enable_irq_with_priority(lcd->lcd_irq, 7); + intc_m_enable_irq_with_priority(lcd->lcd_irq, lcd->lcd_irq_priority); return 0; } diff --git a/bsp/hpmicro/libraries/drivers/drv_mcan.c b/bsp/hpmicro/libraries/drivers/drv_mcan.c index 01d5a626865..55dcfcb8ade 100644 --- a/bsp/hpmicro/libraries/drivers/drv_mcan.c +++ b/bsp/hpmicro/libraries/drivers/drv_mcan.c @@ -1,12 +1,12 @@ /* - * Copyright (c) 2023-2024 HPMicro + * Copyright (c) 2023-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * * Change Logs: * Date Author Notes * 2023-04-07 HPMicro the first version - * 2023-05-31 HPMicro add MCAN4-MCAN7 support + * 2024-05-31 HPMicro add MCAN4-7 support */ #include @@ -15,7 +15,7 @@ #include "board.h" #include "hpm_mcan_drv.h" - +#include "hpm_clock_drv.h" #define CAN_SEND_WAIT_MS_MAX (1000U) /* CAN maximum wait time for transmission */ #define CAN_SENDBOX_NUM (1U) /* CAN Hardware Transmission buffer number */ @@ -29,7 +29,13 @@ typedef struct _hpm_can_struct MCAN_Type *can_base; /**< CAN Base address */ const char *name; /**< CAN device name */ int32_t irq_num; /**< CAN IRQ index */ + uint8_t irq_priority; /**< CAN IRQ priority */ + clock_name_t clk_name; /**< CAN clock name */ uint32_t fifo_index; /**< FIFO index, it is a fake value to satisfy the driver framework */ +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + uint32_t ram_base; + uint32_t ram_size; +#endif mcan_config_t can_config; /**< CAN configuration for IP */ struct rt_can_device can_dev; /**< CAN device configuration in rt-thread */ uint32_t irq_txrx_err_enable_mask; /**< CAN TX and RX IRQ Enable Mask */ @@ -44,7 +50,7 @@ static const mcan_filter_elem_t k_default_std_id_filter = { .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, /* Store message into RXFIFO0 if matching */ .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, - /* For Standard Identify only */ + /* For Standard ID only */ .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, /* Sync Message, only evaluated when "CCCR.UTSU" is set */ .sync_message = 0U, @@ -59,7 +65,7 @@ static const mcan_filter_elem_t k_default_ext_id_filter = { .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, /* Store message into RXFIFO0 if matching */ .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, - /* For Standard Identify only */ + /* For Extended ID only */ .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, /* Sync Message, only evaluated when "CCCR.UTSU" is set */ .sync_message = 0, @@ -125,20 +131,57 @@ static void hpm_mcan_isr(hpm_can_t *hpm_can); */ static uint8_t can_get_data_bytes_from_dlc(uint32_t dlc); +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) +#if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan0_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN1_BASE) && defined(BSP_USING_MCAN1) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan1_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan2_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan3_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan4_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan5_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan6_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) +ATTR_PLACE_AT(".ahb_sram") uint32_t mcan7_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS]; +#endif +#endif + #if defined(HPM_MCAN0_BASE) && defined(BSP_USING_MCAN0) static hpm_can_t dev_can0 = { .can_base = HPM_MCAN0, .name = "can0", .irq_num = IRQn_MCAN0, +#if defined(BSP_MCAN0_IRQ_PRIORITY) + .irq_priority = BSP_MCAN0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 0, + .clk_name = clock_can0, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan0_msg_buf, + .ram_size = sizeof(mcan0_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN0, can0_isr); void can0_isr(void) { hpm_mcan_isr(&dev_can0); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN0, can0_isr); #endif @@ -148,13 +191,23 @@ static hpm_can_t dev_can1 = .can_base = HPM_MCAN1, .name = "can1", .irq_num = IRQn_MCAN1, +#if defined(BSP_MCAN1_IRQ_PRIORITY) + .irq_priority = BSP_MCAN1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 1, + .clk_name = clock_can1, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan1_msg_buf, + .ram_size = sizeof(mcan1_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN1, can1_isr); void can1_isr(void) { hpm_mcan_isr(&dev_can1); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN1, can1_isr); #endif #if defined(HPM_MCAN2_BASE) && defined(BSP_USING_MCAN2) @@ -163,13 +216,23 @@ static hpm_can_t dev_can2 = .can_base = HPM_MCAN2, .name = "can2", .irq_num = IRQn_MCAN2, +#if defined(BSP_MCAN2_IRQ_PRIORITY) + .irq_priority = BSP_MCAN2_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 2, + .clk_name = clock_can2, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan2_msg_buf, + .ram_size = sizeof(mcan2_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN2, can2_isr); void can2_isr(void) { hpm_mcan_isr(&dev_can2); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN2, can2_isr); #endif #if defined(HPM_MCAN3_BASE) && defined(BSP_USING_MCAN3) @@ -178,13 +241,23 @@ static hpm_can_t dev_can3 = .can_base = HPM_MCAN3, .name = "can3", .irq_num = IRQn_MCAN3, +#if defined(BSP_MCAN3_IRQ_PRIORITY) + .irq_priority = BSP_MCAN3_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 3, + .clk_name = clock_can3, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan3_msg_buf, + .ram_size = sizeof(mcan3_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN3, can3_isr); void can3_isr(void) { hpm_mcan_isr(&dev_can3); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN3, can3_isr); #endif #if defined(HPM_MCAN4_BASE) && defined(BSP_USING_MCAN4) @@ -193,13 +266,23 @@ static hpm_can_t dev_can4 = .can_base = HPM_MCAN4, .name = "can4", .irq_num = IRQn_MCAN4, +#if defined(BSP_MCAN4_IRQ_PRIORITY) + .irq_priority = BSP_MCAN4_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 4, + .clk_name = clock_can4, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan4_msg_buf, + .ram_size = sizeof(mcan4_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN4, can4_isr); void can4_isr(void) { hpm_mcan_isr(&dev_can4); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN4, can4_isr); #endif #if defined(HPM_MCAN5_BASE) && defined(BSP_USING_MCAN5) @@ -208,13 +291,23 @@ static hpm_can_t dev_can5 = .can_base = HPM_MCAN5, .name = "can5", .irq_num = IRQn_MCAN5, +#if defined(BSP_MCAN5_IRQ_PRIORITY) + .irq_priority = BSP_MCAN5_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 5, + .clk_name = clock_can5, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan5_msg_buf, + .ram_size = sizeof(mcan5_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN5, can5_isr); void can5_isr(void) { hpm_mcan_isr(&dev_can5); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN5, can5_isr); #endif #if defined(HPM_MCAN6_BASE) && defined(BSP_USING_MCAN6) @@ -223,13 +316,23 @@ static hpm_can_t dev_can6 = .can_base = HPM_MCAN6, .name = "can6", .irq_num = IRQn_MCAN6, +#if defined(BSP_MCAN6_IRQ_PRIORITY) + .irq_priority = BSP_MCAN6_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 6, + .clk_name = clock_can6, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan6_msg_buf, + .ram_size = sizeof(mcan6_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN6, can6_isr); void can6_isr(void) { hpm_mcan_isr(&dev_can6); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN6, can6_isr); #endif #if defined(HPM_MCAN7_BASE) && defined(BSP_USING_MCAN7) @@ -238,13 +341,23 @@ static hpm_can_t dev_can7 = .can_base = HPM_MCAN7, .name = "can7", .irq_num = IRQn_MCAN7, +#if defined(BSP_MCAN7_IRQ_PRIORITY) + .irq_priority = BSP_MCAN7_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif .fifo_index = 7, + .clk_name = clock_can7, +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + .ram_base = (uint32_t) &mcan7_msg_buf, + .ram_size = sizeof(mcan7_msg_buf), +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_MCAN7, can7_isr); void can7_isr(void) { hpm_mcan_isr(&dev_can7); } -SDK_DECLARE_EXT_ISR_M(IRQn_MCAN7, can7_isr); #endif static hpm_can_t *hpm_cans[] = { @@ -406,7 +519,8 @@ static rt_err_t hpm_mcan_configure(struct rt_can_device *can, struct can_configu } init_can_pins(drv_can->can_base); - uint32_t can_clk = board_init_can_clock(drv_can->can_base); + clock_add_to_group(drv_can->clk_name, BOARD_RUNNING_CORE & 0x1); + uint32_t can_clk = clock_get_frequency(drv_can->clk_name); drv_can->can_config.all_filters_config.std_id_filter_list.filter_elem_list = &drv_can->std_can_filters[0]; drv_can->can_config.all_filters_config.std_id_filter_list.mcan_filter_elem_count = drv_can->std_filter_num; @@ -473,7 +587,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); - intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } else if (arg_val == RT_DEVICE_FLAG_INT_TX) { @@ -482,7 +596,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); mcan_enable_txbuf_interrupt(drv_can->can_base, ~0UL); - intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } else if (arg_val == RT_DEVICE_CAN_INT_ERR) { @@ -490,7 +604,7 @@ static rt_err_t hpm_mcan_control(struct rt_can_device *can, int cmd, void *arg) drv_can->irq_txrx_err_enable_mask |= irq_txrx_mask; drv_can->can_config.interrupt_mask |= irq_txrx_mask; mcan_enable_interrupts(drv_can->can_base, drv_can->irq_txrx_err_enable_mask); - intc_m_enable_irq_with_priority(drv_can->irq_num, 1); + intc_m_enable_irq_with_priority(drv_can->irq_num, drv_can->irq_priority); } else { @@ -814,6 +928,10 @@ int rt_hw_mcan_init(void) hpm_cans[i]->can_dev.config = config; hpm_cans[i]->ext_filter_num = 0; hpm_cans[i]->std_filter_num = 0; +#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) + mcan_msg_buf_attr_t attr = { hpm_cans[i]->ram_base, hpm_cans[i]->ram_size }; + hpm_stat_t status = mcan_set_msg_buf_attr(hpm_cans[i]->can_base, &attr); +#endif mcan_get_default_config(hpm_cans[i]->can_base, &hpm_cans[i]->can_config); rt_hw_can_register(&hpm_cans[i]->can_dev, hpm_cans[i]->name, &hpm_can_ops, hpm_cans[i]); } diff --git a/bsp/hpmicro/libraries/drivers/drv_pwm.c b/bsp/hpmicro/libraries/drivers/drv_pwm.c index 02ece6f9f34..7d1d0a49967 100644 --- a/bsp/hpmicro/libraries/drivers/drv_pwm.c +++ b/bsp/hpmicro/libraries/drivers/drv_pwm.c @@ -85,6 +85,12 @@ static pwm_counter_t pwmv2_counter_tbl[PWMV2_CNT_NUM * 2] = { }; #endif +#if defined(HPMSOC_HAS_HPMSDK_PWMV2) +extern uint32_t rtt_board_init_pwm_clock(PWMV2_Type *ptr); +#else +extern uint32_t rtt_board_init_pwm_clock(PWM_Type *ptr); +#endif + rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, uint32_t period, uint32_t pulse) { #if defined(HPMSOC_HAS_HPMSDK_PWMV2) @@ -101,7 +107,7 @@ rt_err_t hpm_generate_central_aligned_waveform(uint8_t pwm_index, uint8_t channe pwm_base = pwm_base_tbl[pwm_index]; init_pwm_pins(pwm_base); - freq = board_init_pwm_clock(pwm_base); + freq = rtt_board_init_pwm_clock(pwm_base); if(period != 0) { reload = (uint64_t)freq * period / 1000000000; } else { @@ -193,7 +199,7 @@ rt_err_t hpm_set_central_aligned_waveform(uint8_t pwm_index, uint8_t channel, ui uint32_t freq; pwm_base = pwm_base_tbl[pwm_index]; - freq = board_init_pwm_clock(pwm_base); + freq = rtt_board_init_pwm_clock(pwm_base); if(period != 0) { reload = (uint64_t)freq * period / 1000000000; } else { diff --git a/bsp/hpmicro/libraries/drivers/drv_rtc.c b/bsp/hpmicro/libraries/drivers/drv_rtc.c index 1968629326b..c87e23cf055 100644 --- a/bsp/hpmicro/libraries/drivers/drv_rtc.c +++ b/bsp/hpmicro/libraries/drivers/drv_rtc.c @@ -7,6 +7,8 @@ * Date Author Notes * 2021-09-19 HPMicro First version * 2023-05-08 HPMicro Adapt RT-Thread V5.0.0 + * 2025-05-23 HPMicro Support setting and getting timeval + * 2025-05-26 HPMicro Support 64-bit time_t and alarm set/getting */ #include "board.h" #include "drv_rtc.h" @@ -33,6 +35,8 @@ static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args); static time_t hpm_rtc_get_timestamp(void); static int hpm_rtc_set_timestamp(time_t timestamp); +static int hpm_rtc_set_alarm(struct rt_rtc_wkalarm *alarm); +static int hpm_rtc_get_alarm(struct rt_rtc_wkalarm *alarm); /******************************************************************************************* * @@ -63,6 +67,21 @@ static struct rt_device hpm_rtc= { #endif }; +/***************************************************** + * RTC interrupt handler +******************************************************/ +#ifdef RT_USING_ALARM +void rtc_isr(void) +{ + uint32_t rtc_alarm_flag = rtc_get_alarm_flags(HPM_RTC); + if ((rtc_alarm_flag & RTC_ALARM_FLAG_ALARM0_MASK) != 0) + { + rt_alarm_update(&hpm_rtc, 1); + } + rtc_clear_alarm_flags(HPM_RTC, RTC_ALARM_FLAG_ALARM0_MASK | RTC_ALARM_FLAG_ALARM1_MASK); +} +RTT_DECLARE_EXT_ISR_M(IRQn_RTC, rtc_isr); +#endif /******************************************************************************************* * * Codes @@ -96,13 +115,33 @@ static rt_err_t hpm_rtc_control(rt_device_t dev, int cmd, void *args) rt_err_t err = RT_EOK; + struct timeval tv; + switch(cmd) { case RT_DEVICE_CTRL_RTC_GET_TIME: - *(uint32_t *)args = hpm_rtc_get_timestamp(); + if (sizeof(uint32_t) == sizeof(time_t)) { + *(uint32_t *)args = hpm_rtc_get_timestamp(); + } else if (sizeof(uint64_t) == sizeof(time_t)) { + *(uint64_t *)args = hpm_rtc_get_timestamp(); + } break; case RT_DEVICE_CTRL_RTC_SET_TIME: hpm_rtc_set_timestamp(*(time_t *)args); break; + case RT_DEVICE_CTRL_RTC_GET_TIMEVAL: + tv = rtc_get_timeval(HPM_RTC); + memcpy(args, &tv, sizeof(tv)); + break; + case RT_DEVICE_CTRL_RTC_SET_TIMEVAL: + memcpy(&tv, args, sizeof(tv)); + rtc_config_time(HPM_RTC, tv.tv_sec); + break; + case RT_DEVICE_CTRL_RTC_SET_ALARM: + err = hpm_rtc_set_alarm((struct rt_rtc_wkalarm *)args); + break; + case RT_DEVICE_CTRL_RTC_GET_ALARM: + err = hpm_rtc_get_alarm((struct rt_rtc_wkalarm *)args); + break; default: err = RT_EINVAL; break; @@ -125,6 +164,77 @@ static int hpm_rtc_set_timestamp(time_t timestamp) return RT_EOK; } +static int hpm_rtc_set_alarm(struct rt_rtc_wkalarm *alarm) +{ +#ifdef RT_USING_ALARM + rtc_alarm_config_t config; + time_t now; + time_t alarm_time; + struct tm tm_alarm = {0}; + if (alarm->enable == RT_TRUE) { + /* Clear all pending interrupt flags first */ + rtc_clear_alarm_flag(HPM_RTC, 0); + rtc_clear_alarm_flag(HPM_RTC, 1); + tm_alarm.tm_sec = alarm->tm_sec; + tm_alarm.tm_min = alarm->tm_min; + tm_alarm.tm_hour = alarm->tm_hour; + tm_alarm.tm_mday = alarm->tm_mday; + tm_alarm.tm_mon = alarm->tm_mon; + tm_alarm.tm_year = alarm->tm_year; +#ifdef RT_ALARM_USING_LOCAL_TIME + alarm_time = mktime(&tm_alarm); +#else + alarm_time = timegm(&tm_alarm); +#endif + now = rtc_get_time(HPM_RTC); + if (alarm_time <= now) { + return -RT_ERROR; + } + config.period = alarm_time; + config.type = RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT; + config.index = 0; + if (rtc_config_alarm(HPM_RTC, &config) != status_success) { + return -RT_ERROR; + } + rtc_enable_alarm_interrupt(HPM_RTC, 0, true); + intc_m_enable_irq_with_priority(IRQn_RTC, 1); + } else { + rtc_enable_alarm_interrupt(HPM_RTC, 0, false); + intc_m_disable_irq(IRQn_RTC); + } + return RT_EOK; +#else + return -RT_EINVAL; +#endif +} + +static int hpm_rtc_get_alarm(struct rt_rtc_wkalarm *alarm) +{ +#ifdef RT_USING_ALARM + time_t alarm_time; + struct tm alarm_tm; + if (RTC_ALARM_EN_ENABLE0_GET(HPM_RTC->ALARM_EN) == 0) { + alarm->enable = RT_FALSE; + } else { + alarm->enable = RT_TRUE; + } + alarm_time = RTC_ALARM0_ALARM_GET(HPM_RTC->ALARM0); +#ifdef RT_ALARM_USING_LOCAL_TIME + localtime_r(&alarm_time, &alarm_tm); +#else + gmtime_r(&alarm_time, &alarm_tm); +#endif + alarm->tm_sec = alarm_tm.tm_sec; + alarm->tm_min = alarm_tm.tm_min; + alarm->tm_hour = alarm_tm.tm_hour; + alarm->tm_mday = alarm_tm.tm_mday; + alarm->tm_mon = alarm_tm.tm_mon; + alarm->tm_year = alarm_tm.tm_year; + return RT_EOK; +#else + return -RT_EINVAL; +#endif +} int rt_hw_rtc_init(void) { diff --git a/bsp/hpmicro/libraries/drivers/drv_sdio.c b/bsp/hpmicro/libraries/drivers/drv_sdio.c index 541395ed5ba..58088c14f8c 100644 --- a/bsp/hpmicro/libraries/drivers/drv_sdio.c +++ b/bsp/hpmicro/libraries/drivers/drv_sdio.c @@ -14,39 +14,31 @@ * 2024-05-25 HPMicro Added HS200 & HS400 support, optimize the cache-management policy for read * 2024-05-26 HPMicro Added UHS-I support, added DDR50 and High Speed DDR mode support * 2024-06-19 HPMicro Added timeout check for SDXC transfer + * 2025-03-06 HPMicro Adapt hpm-sdk v1.9.0 + * 2025-03-24 HPMicro Added ADMA3 support, added interrupt driven mode + * 2025-04-11 HPMicro Added the non-cacheable buffer support, avoided dynamic memory allocation at transfer stage */ #include #ifdef BSP_USING_SDXC -#include -#include #include +#include #include "board.h" #include "hpm_sdxc_drv.h" #include "hpm_l1c_drv.h" -#define CACHE_LINESIZE HPM_L1C_CACHELINE_SIZE -#define SDXC_ADMA_TABLE_WORDS (2U) -#define SDXC_AMDA2_ADDR_ALIGN (4U) -#define SDXC_DATA_TIMEOUT (0xFU) +#define CACHELINE_SIZE HPM_L1C_CACHELINE_SIZE +#define SDXC_ADMA_TABLE_WORDS SDXC_AMDA3_DESC_MIN_WORDS +#define SDXC_AMDA_ADDR_ALIGNMENT (4U) +#define SDXC_ADMA_XFER_SIZE_ALIGNMENT (4U) +#define SDXC_DATA_TIMEOUT (1000) /* 1000ms */ +#define SDMMC_DEFAULT_SECTOR_SIZE (512U) #define SDXC_CACHELINE_ALIGN_DOWN(x) HPM_L1C_CACHELINE_ALIGN_DOWN(x) #define SDXC_CACHELINE_ALIGN_UP(x) HPM_L1C_CACHELINE_ALIGN_UP(x) -#define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHE_LINESIZE) == 0U) - -/** - * Note: Allocate cache-line aligned buffer in the SD/eMMC read/write case may require larger heap size - * if the read/write length is a big number (for example: 64KB), the RT-Thread RTOS may - * be unable to allocate enough size of buffer if the heap size is small. - * - * Keep this option disabled by default, please enable it if the default setting cannot meet - * real requirement of application. - */ -#ifndef HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF -#define HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF 0 -#endif +#define SDXC_IS_CACHELINE_ALIGNED(n) ((uint32_t)(n) % (uint32_t)(CACHELINE_SIZE) == 0U) struct hpm_mmcsd { @@ -59,7 +51,7 @@ struct hpm_mmcsd rt_uint32_t *buf; SDXC_Type *sdxc_base; int32_t irq_num; - uint32_t *sdxc_adma2_table; + uint32_t *sdxc_adma_table; bool support_8bit; bool support_4bit; bool support_1v8; @@ -72,7 +64,12 @@ struct hpm_mmcsd uint16_t vdd; const char *vsel_pin_name; const char *pwr_pin_name; - + bool enable_interrupt_driven; + bool use_noncacheable_buf; + uint8_t *data_buf; + uint32_t data_buf_size; + uint8_t irq_priority; + rt_event_t xfer_event; }; /** @@ -96,7 +93,9 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r static void hpm_sdmmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg); static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en); static void hpm_sdmmc_host_recovery(SDXC_Type *base); -static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); +static hpm_stat_t hpm_sdmmc_transfer_polling(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); +static hpm_stat_t hpm_sdmmc_transfer_interrupt_driven(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); +static hpm_stat_t hpm_sdmmc_transfer(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode); static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host); @@ -117,11 +116,8 @@ static void hpm_sdmmc_pin_init(const char *pin_name, bool is_output) return; } - rt_uint8_t mode = (is_output) ? PIN_MODE_OUTPUT : PIN_MODE_INPUT_PULLUP; - if (is_output) - { - rt_pin_mode(pin, mode); - } + rt_uint8_t mode = is_output ? PIN_MODE_OUTPUT : PIN_MODE_INPUT_PULLUP; + rt_pin_mode(pin, mode); } static void hpm_sdmmc_pin_write(const char *pin_name, rt_uint8_t value) @@ -194,7 +190,6 @@ static rt_int32_t hpm_sdmmc_switch_uhs_voltage(struct rt_mmcsd_host *host) /* 7. Check DAT[3:0], make sure the value is 4'b0000 */ delay_cnt = 1000000UL; - data3_0_level; do { data3_0_level = sdxc_get_data3_0_level(mmcsd->sdxc_base); @@ -216,21 +211,55 @@ static const struct rt_mmcsd_host_ops hpm_mmcsd_host_ops = .request = hpm_sdmmc_request, .set_iocfg = hpm_sdmmc_set_iocfg, .get_card_status = NULL, - .enable_sdio_irq = NULL, + .enable_sdio_irq = hpm_sdmmc_enable_sdio_irq, .execute_tuning = hpm_sdmmc_execute_tuning, .switch_uhs_voltage = hpm_sdmmc_switch_uhs_voltage, - }; +void hpm_sdmmc_isr(struct hpm_mmcsd *mmcsd) +{ + SDXC_Type *base = mmcsd->sdxc_base; + uint32_t int_stat = sdxc_get_interrupt_status(base); + uint32_t int_signal_en = sdxc_get_interrupt_signal(base); + if (((int_stat & SDXC_INT_STAT_CARD_INTERRUPT_MASK) != 0) && + ((int_signal_en & SDXC_INT_STAT_CARD_INTERRUPT_MASK) != 0)) + { + hpm_sdmmc_enable_sdio_irq(mmcsd->host, 0); + rt_sem_release(mmcsd->host->sdio_irq_sem); + } + if (mmcsd->enable_interrupt_driven) + { + const uint32_t xfer_done_or_err_int_mask = SDXC_INT_STAT_CMD_COMPLETE_MASK \ + | SDXC_INT_STAT_XFER_COMPLETE_MASK \ + | SDXC_INT_STAT_ERR_INTERRUPT_MASK; + if (((int_signal_en & xfer_done_or_err_int_mask) != 0U) && ((int_stat & xfer_done_or_err_int_mask) != 0U)) { + uint32_t event_flags = int_stat & xfer_done_or_err_int_mask; + rt_event_send(mmcsd->xfer_event, event_flags); + sdxc_clear_interrupt_status(base, event_flags); + } + } +} + #if defined(BSP_USING_SDXC0) -/* Place the ADMA2 table to non-cacheable region */ -ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc0_adma2_table[SDXC_ADMA_TABLE_WORDS]; +void sdxc0_isr(void); +/* Place the ADMA table to non-cacheable region */ +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(8) static uint32_t s_sdxc0_adma_table[SDXC_ADMA_TABLE_WORDS]; + +#if defined(BSP_SDXC0_USE_NONCACHEABLE_BUFFER) +#if defined(BSP_SDXC0_NONCACHEABLE_BUF_IN_FAST_RAM) +ATTR_PLACE_AT_FAST_RAM_WITH_ALIGNMENT(8) +#else +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(8) +#endif +static uint8_t s_sdxc0_noncacheable_buf[BSP_SDXC0_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR * SDMMC_DEFAULT_SECTOR_SIZE]; +#endif + /* SDXC0 */ static struct hpm_mmcsd s_hpm_sdxc0 = { .name = "sd0", .sdxc_base = HPM_SDXC0, - .sdxc_adma2_table = s_sdxc0_adma2_table, + .sdxc_adma_table = s_sdxc0_adma_table, .irq_num = IRQn_SDXC0, #if defined(BSP_SDXC0_BUS_WIDTH_8BIT) .support_8bit = true, @@ -259,17 +288,51 @@ static struct hpm_mmcsd s_hpm_sdxc0 = #if defined(BSP_SDXC0_PWR_PIN) .pwr_pin_name = BSP_SDXC0_PWR_PIN, #endif +#if defined(BSP_SDXC0_ENABLE_INTERRUPT_DRIVEN) + .enable_interrupt_driven = true, +#endif +#if defined(BSP_SDXC0_REQUIRE_CACHELINE_ALIGNED_BUF) + .require_cacheline_aligned_buf = true, +#endif +#if defined(BSP_SDXC0_IRQ_PRIORITY) + .irq_priority = BSP_SDXC0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +#if defined (BSP_SDXC0_USE_NONCACHEABLE_BUFFER) + .use_noncacheable_buf = true, + .data_buf = s_sdxc0_noncacheable_buf, + .data_buf_size = sizeof(s_sdxc0_noncacheable_buf), +#endif +#if defined(BSP_SDXC0_USE_CACHEABLE_BUFFER) + .data_buf_size = BSP_SDXC0_CACHEABLE_BUFFER_SIZE_IN_SECTOR * SDMMC_DEFAULT_SECTOR_SIZE, +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_SDXC0, sdxc0_isr); +void sdxc0_isr(void) +{ + hpm_sdmmc_isr(&s_hpm_sdxc0); +} #endif #if defined(BSP_USING_SDXC1) -/* Place the ADMA2 table to non-cacheable region */ -ATTR_PLACE_AT_NONCACHEABLE static uint32_t s_sdxc1_adma2_table[SDXC_ADMA_TABLE_WORDS]; +void sdxc1_isr(void); +/* Place the ADMA table to non-cacheable region */ +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(8) static uint32_t s_sdxc1_adma_table[SDXC_ADMA_TABLE_WORDS]; +#if defined(BSP_SDXC1_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR) + +#if defined(BSP_SDXC1_USE_NONCACHEABLE_BUFFER) +ATTR_PLACE_AT_FAST_RAM_WITH_ALIGNMENT(8) +#else +ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(8) +#endif +static uint8_t s_sdxc1_noncacheable_buf[BSP_SDXC1_NONCACHEABLE_BUFFER_SIZE_IN_SECTOR * SDMMC_DEFAULT_SECTOR_SIZE]; +#endif static struct hpm_mmcsd s_hpm_sdxc1 = { .name = "sd1", .sdxc_base = HPM_SDXC1, - .sdxc_adma2_table = s_sdxc1_adma2_table, + .sdxc_adma_table = s_sdxc1_adma_table, .irq_num = IRQn_SDXC1, #if defined(BSP_SDXC1_BUS_WIDTH_8BIT) .support_8bit = true, @@ -297,7 +360,31 @@ static struct hpm_mmcsd s_hpm_sdxc1 = #if defined(BSP_SDXC1_PWR_PIN) .pwr_pin_name = BSP_SDXC1_PWR_PIN, #endif +#if defined(BSP_SDXC1_ENABLE_INTERRUPT_DRIVEN) + .enable_interrupt_driven = true, +#endif +#if defined(BSP_SDXC1_REQUIRE_CACHELINE_ALIGNED_BUF) + .require_cacheline_aligned_buf = true, +#endif +#if defined(BSP_SDXC1_IRQ_PRIORITY) + .irq_priority = BSP_SDXC1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif +#if defined (BSP_SDXC1_USE_NONCACHEABLE_BUFFER) + .use_noncacheable_buf = true, + .data_buf = s_sdxc1_noncacheable_buf, + .data_buf_size = sizeof(s_sdxc1_noncacheable_buf), +#endif +#if defined(BSP_SDXC1_USE_CACHEABLE_BUFFER) + .data_buf_size = BSP_SDXC1_CACHEABLE_BUFFER_SIZE_IN_SECTOR * SDMMC_DEFAULT_SECTOR_SIZE, +#endif }; +SDK_DECLARE_EXT_ISR_M(IRQn_SDXC1, sdxc1_isr); +void sdxc1_isr(void) +{ + hpm_sdmmc_isr(&s_hpm_sdxc1); +} #endif static struct hpm_mmcsd *hpm_sdxcs[] = @@ -312,10 +399,12 @@ static struct hpm_mmcsd *hpm_sdxcs[] = static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_t opcode) { - RT_ASSERT(host != RT_NULL); RT_ASSERT(host->private_data != RT_NULL); + RT_ASSERT(host != RT_NULL); + RT_ASSERT(host->private_data != RT_NULL); struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; SDXC_Type *base = mmcsd->sdxc_base; + RT_ASSERT(base != RT_NULL); /* Prepare the Auto tuning environment */ sdxc_stop_clock_during_phase_code_change(base, true); @@ -327,36 +416,72 @@ static rt_int32_t hpm_sdmmc_execute_tuning(struct rt_mmcsd_host *host, rt_int32_ return (err != status_success) ? -RT_EPERM : RT_EOK; } -static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +static hpm_stat_t hpm_sdmmc_transfer_polling(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) { hpm_stat_t status; + SDXC_Type *base = mmcsd->sdxc_base; sdxc_command_t *cmd = xfer->command; sdxc_data_t *data = xfer->data; - status = sdxc_transfer_nonblocking(base, dma_config, xfer); - if (status != status_success) + volatile uint32_t interrupt_status; + volatile rt_tick_t start_tick; + rt_tick_t current_tick; + bool need_chk_xfer_stat = false; + sdxc_clear_interrupt_status(base, ~0UL); + if (data == NULL) { - return -RT_ERROR; - } - /* Wait until idle */ - volatile uint32_t interrupt_status = sdxc_get_interrupt_status(base); - volatile rt_base_t start_tick = rt_tick_get(); - while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK)) - { - interrupt_status = sdxc_get_interrupt_status(base); - status = sdxc_parse_interrupt_status(base); - HPM_BREAK_IF(status != status_success); - rt_base_t current_tick = rt_tick_get(); - if ((current_tick - start_tick) > RT_TICK_PER_SECOND) + (void)sdxc_send_command(base, cmd); + /* Wait until idle */ + start_tick = rt_tick_get(); + do + { + interrupt_status = sdxc_get_interrupt_status(base); + status = sdxc_parse_interrupt_status(base); + HPM_BREAK_IF(status != status_success); + current_tick = rt_tick_get(); + if ((current_tick - start_tick) > RT_TICK_PER_SECOND) { + status = status_timeout; + break; + } + } while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK)); + + if ((status == status_success) && (cmd->resp_type == sdxc_dev_resp_r1b)) { - return -RT_ETIMEOUT; + need_chk_xfer_stat = true; } } - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_CMD_COMPLETE_MASK); - if (status == status_success) + else { - status = sdxc_receive_cmd_response(base, cmd); + status = sdxc_transfer_nonblocking(base, dma_config, xfer); + if (status != status_success) + { + return status; + } + if (dma_config->dma_type == sdxc_dmasel_adma2) + { + /* Wait until idle */ + interrupt_status = sdxc_get_interrupt_status(base); + start_tick = rt_tick_get(); + while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK)) + { + interrupt_status = sdxc_get_interrupt_status(base); + status = sdxc_parse_interrupt_status(base); + HPM_BREAK_IF(status != status_success); + current_tick = rt_tick_get(); + if ((current_tick - start_tick) > RT_TICK_PER_SECOND) + { + status = status_timeout; + break; + } + } + } + + if (status == status_success) + { + need_chk_xfer_stat = true; + } } - if ((status == status_success) && (data != RT_NULL)) + + if (need_chk_xfer_stat) { interrupt_status = sdxc_get_interrupt_status(base); start_tick = rt_tick_get(); @@ -365,17 +490,107 @@ static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_co interrupt_status = sdxc_get_interrupt_status(base); status = sdxc_parse_interrupt_status(base); HPM_BREAK_IF(status != status_success); - rt_base_t current_tick = rt_tick_get(); + current_tick = rt_tick_get(); if ((current_tick - start_tick) > RT_TICK_PER_SECOND) { - return -RT_ETIMEOUT; + status = status_timeout; + break; } } } + if (status == status_success) + { + status = sdxc_receive_cmd_response(base, cmd); + } return status; } +static hpm_stat_t hpm_sdmmc_transfer_interrupt_driven(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +{ + hpm_stat_t status; + SDXC_Type *base = mmcsd->sdxc_base; + sdxc_command_t *cmd = xfer->command; + sdxc_data_t *data = xfer->data; + bool need_chk_xfer_stat = false; + sdxc_clear_interrupt_status(base, ~0UL); + if (data == NULL) + { + (void)sdxc_send_command(base, cmd); + /* Wait until idle */ + const uint32_t wait_event_flags = SDXC_INT_STAT_CMD_COMPLETE_MASK \ + | SDXC_INT_STAT_ERR_INTERRUPT_MASK; + rt_err_t err = rt_event_recv(mmcsd->xfer_event, wait_event_flags, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_TICK_PER_SECOND, NULL); + if (err == RT_EOK) + { + status = sdxc_parse_interrupt_status(base); + } + else + { + status = status_timeout; + } + + if ((status == status_success) && (cmd->resp_type == sdxc_dev_resp_r1b)) + { + need_chk_xfer_stat = true; + } + } + else + { + status = sdxc_transfer_nonblocking(base, dma_config, xfer); + if (status != status_success) + { + return status; + } + if (dma_config->dma_type == sdxc_dmasel_adma2) + { + const uint32_t wait_event_flags = SDXC_INT_STAT_CMD_COMPLETE_MASK | SDXC_INT_STAT_ERR_INTERRUPT_MASK; + rt_err_t err = rt_event_recv(mmcsd->xfer_event, wait_event_flags, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_TICK_PER_SECOND, NULL); + if (err == RT_EOK) + { + status = sdxc_parse_interrupt_status(base); + } + else + { + status = status_timeout; + } + } + + if (status == status_success) + { + need_chk_xfer_stat = true; + } + } + if (need_chk_xfer_stat) + { + const uint32_t wait_event_flags = SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_INT_STAT_ERR_INTERRUPT_MASK; + rt_err_t err = rt_event_recv(mmcsd->xfer_event, wait_event_flags, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, RT_TICK_PER_SECOND, NULL); + if (err == RT_EOK) + { + status = sdxc_parse_interrupt_status(base); + } + } + if (status == status_success) + { + status = sdxc_receive_cmd_response(base, cmd); + } + + return status; +} + + +static hpm_stat_t hpm_sdmmc_transfer(struct hpm_mmcsd *mmcsd, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) +{ + if (mmcsd->enable_interrupt_driven) + { + return hpm_sdmmc_transfer_interrupt_driven(mmcsd, dma_config, xfer); + } + else + { + return hpm_sdmmc_transfer_polling(mmcsd, dma_config, xfer); + } +} + /** * !@brief SDMMC request implementation based on HPMicro SDXC Host */ @@ -390,8 +605,7 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r sdxc_xfer_t xfer = { 0 }; sdxc_command_t sdxc_cmd = { 0 }; sdxc_data_t sdxc_data = { 0 }; - uint32_t *raw_alloc_buf = RT_NULL; - uint32_t *aligned_buf = RT_NULL; + bool need_copy_back = false; hpm_stat_t err = status_invalid_argument; struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; struct rt_mmcsd_cmd *cmd = req->cmd; @@ -444,95 +658,78 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r sdxc_data.enable_auto_cmd23 = false; sdxc_data.enable_ignore_error = false; - sdxc_data.data_type = sdxc_xfer_data_normal; sdxc_data.block_size = data->blksize; sdxc_data.block_cnt = data->blks; - /* configure adma2 */ - adma_config.dma_type = sdxc_dmasel_adma2; + /* configure adma3 */ + adma_config.dma_type = sdxc_dmasel_adma3; adma_config.adma_table = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, - (uint32_t) mmcsd->sdxc_adma2_table); + (uint32_t) mmcsd->sdxc_adma_table); adma_config.adma_table_words = SDXC_ADMA_TABLE_WORDS; - rt_size_t xfer_buf_addr = (uint32_t)data->buf; + size_t xfer_buf_addr = (uint32_t)data->buf; uint32_t xfer_len = data->blks * data->blksize; + bool need_cache_maintenance = true; if ((req->data->flags & DATA_DIR_WRITE) != 0U) { uint32_t write_size = xfer_len; - rt_size_t aligned_start; + size_t aligned_start; uint32_t aligned_size; -#if defined(HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF) && (HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF == 1) - if (!SDXC_IS_CACHELINE_ALIGNED(xfer_buf_addr) || !SDXC_IS_CACHELINE_ALIGNED(write_size)) -#else - if ((xfer_buf_addr % 4 != 0) || (write_size % 4 != 0)) -#endif + if ((xfer_buf_addr % CACHELINE_SIZE != 0) || (write_size % CACHELINE_SIZE != 0)) { - write_size = SDXC_CACHELINE_ALIGN_UP(xfer_len); - raw_alloc_buf = (uint32_t *) rt_malloc(write_size + CACHE_LINESIZE - RT_ALIGN_SIZE); - RT_ASSERT(raw_alloc_buf != RT_NULL); - aligned_buf = (uint32_t *) SDXC_CACHELINE_ALIGN_UP(raw_alloc_buf); - RT_ASSERT(aligned_buf != RT_NULL); - memcpy(aligned_buf, data->buf, xfer_len); - memset(aligned_buf + write_size, 0, write_size - xfer_len); - sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) aligned_buf); - + uint32_t write_size = xfer_len; + aligned_size = SDXC_CACHELINE_ALIGN_UP(write_size); + rt_memcpy(mmcsd->data_buf, data->buf, xfer_len); + rt_memset(&mmcsd->data_buf[write_size], 0, aligned_size - write_size); + sdxc_data.tx_data = (uint32_t const *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)mmcsd->data_buf); aligned_start = (uint32_t)sdxc_data.tx_data; - aligned_size = write_size; + need_cache_maintenance = !mmcsd->use_noncacheable_buf; } else { - sdxc_data.tx_data = (uint32_t const *) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, xfer_buf_addr); - - aligned_start = SDXC_CACHELINE_ALIGN_DOWN(sdxc_data.tx_data); - rt_size_t aligned_end = SDXC_CACHELINE_ALIGN_UP((uint32_t)sdxc_data.tx_data + write_size); - aligned_size = aligned_end - aligned_start; + sdxc_data.tx_data = (uint32_t const *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, xfer_buf_addr); + aligned_start = (uint32_t)sdxc_data.tx_data; + aligned_size = write_size; } - l1c_dc_flush(aligned_start, aligned_size); + if (need_cache_maintenance) + { + l1c_dc_flush(aligned_start, aligned_size); + } + sdxc_data.rx_data = NULL; } else { uint32_t read_size = xfer_len; -#if defined(HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF) && (HPM_SDXC_ALLOC_CACHELINE_ALIGNED_BUF == 1) - if (!SDXC_IS_CACHELINE_ALIGNED(xfer_buf_addr) || !SDXC_IS_CACHELINE_ALIGNED(read_size)) -#else - if ((xfer_buf_addr % 4 != 0) || (read_size % 4 != 0)) -#endif + uint32_t aligned_read_size; + if ((xfer_buf_addr % CACHELINE_SIZE != 0) || (read_size % CACHELINE_SIZE != 0)) { - uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); - raw_alloc_buf = (uint32_t *) rt_malloc(aligned_read_size + CACHE_LINESIZE - RT_ALIGN_SIZE); - RT_ASSERT(raw_alloc_buf != RT_NULL); - aligned_buf = (uint32_t *) SDXC_CACHELINE_ALIGN_UP(raw_alloc_buf); - sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t) aligned_buf); - /* Invalidate cache-line for the new allocated buffer */ - l1c_dc_invalidate((uint32_t) sdxc_data.rx_data, aligned_read_size); + aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); + sdxc_data.rx_data = (uint32_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)mmcsd->data_buf); + need_copy_back = true; + need_cache_maintenance = !mmcsd->use_noncacheable_buf; } else { - sdxc_data.rx_data = (uint32_t*) core_local_mem_to_sys_address(BOARD_RUNNING_CORE, xfer_buf_addr); - rt_size_t buf_start = (uint32_t) sdxc_data.rx_data; - rt_size_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN(buf_start); - rt_size_t end_addr = buf_start + xfer_len; - /* FLUSH un-cacheline aligned memory region */ - if ((buf_start % HPM_L1C_CACHELINE_SIZE) != 0) { - l1c_dc_writeback(aligned_start, HPM_L1C_CACHELINE_SIZE); - } - if ((end_addr % HPM_L1C_CACHELINE_SIZE) != 0) { - uint32_t aligned_tail = HPM_L1C_CACHELINE_ALIGN_DOWN(end_addr); - l1c_dc_writeback(aligned_tail, HPM_L1C_CACHELINE_SIZE); - } + aligned_read_size = read_size; + sdxc_data.rx_data = (uint32_t *)core_local_mem_to_sys_address(BOARD_RUNNING_CORE, xfer_buf_addr); + } + /* Invalidate cache-line for the new allocated buffer */ + if (need_cache_maintenance) + { + l1c_dc_invalidate((uint32_t)sdxc_data.rx_data, aligned_read_size); } sdxc_data.tx_data = RT_NULL; } xfer.data = &sdxc_data; - /* Align the write/read size since the ADMA2 engine in the SDXC cannot transfer unaligned size of data */ - if ((cmd->cmd_code == SD_IO_RW_EXTENDED) && (xfer_len % 4 != 0)) + /* Align the write/read size since the ADMA engine in the SDXC cannot transfer unaligned size of data */ + if ((cmd->cmd_code == SD_IO_RW_EXTENDED) && (xfer_len % SDXC_ADMA_XFER_SIZE_ALIGNMENT != 0)) { sdio_cmd53_arg_t cmd53_arg; cmd53_arg.value = sdxc_cmd.cmd_argument; - cmd53_arg.count = HPM_ALIGN_UP(xfer_len, 4); + cmd53_arg.count = HPM_ALIGN_UP(xfer_len, SDXC_ADMA_XFER_SIZE_ALIGNMENT); sdxc_cmd.cmd_argument = cmd53_arg.value; - sdxc_data.block_size = HPM_ALIGN_UP(xfer_len, 4); + sdxc_data.block_size = HPM_ALIGN_UP(xfer_len, SDXC_ADMA_XFER_SIZE_ALIGNMENT); } } @@ -541,7 +738,7 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r xfer.data->enable_auto_cmd12 = true; } - err = hpm_sdmmc_transfer(mmcsd->sdxc_base, &adma_config, &xfer); + err = hpm_sdmmc_transfer(mmcsd, &adma_config, &xfer); LOG_I("cmd=%d, arg=%x\n", cmd->cmd_code, cmd->arg); if (err != status_success) { @@ -558,7 +755,9 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r if (sdxc_cmd.resp_type == sdxc_dev_resp_r2) { LOG_I("resp:0x%08x 0x%08x 0x%08x 0x%08x\n", sdxc_cmd.response[0], - sdxc_cmd.response[1], sdxc_cmd.response[2], sdxc_cmd.response[3]); + sdxc_cmd.response[1], + sdxc_cmd.response[2], + sdxc_cmd.response[3]); } else { @@ -568,32 +767,12 @@ static void hpm_sdmmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r if ((sdxc_data.rx_data != NULL) && (cmd->err == RT_EOK)) { uint32_t read_size = data->blks * data->blksize; - if (aligned_buf != RT_NULL) - { - uint32_t aligned_read_size = SDXC_CACHELINE_ALIGN_UP(read_size); - rt_base_t level = rt_hw_interrupt_disable(); - l1c_dc_invalidate((uint32_t) aligned_buf, aligned_read_size); - rt_hw_interrupt_enable(level); - memcpy(data->buf, aligned_buf, read_size); - } - else + if (need_copy_back) { - rt_size_t aligned_start = SDXC_CACHELINE_ALIGN_DOWN(sdxc_data.rx_data); - rt_size_t aligned_end = SDXC_CACHELINE_ALIGN_UP((uint32_t)sdxc_data.rx_data + read_size); - uint32_t aligned_size = aligned_end - aligned_start; - rt_base_t level = rt_hw_interrupt_disable(); - l1c_dc_invalidate(aligned_start, aligned_size); - rt_hw_interrupt_enable(level); + rt_memcpy(data->buf, mmcsd->data_buf, read_size); } } - if (raw_alloc_buf != RT_NULL) - { - rt_free(raw_alloc_buf); - raw_alloc_buf = RT_NULL; - aligned_buf = RT_NULL; - } - if ((cmd->flags & RESP_MASK) == RESP_R2) { cmd->resp[3] = sdxc_cmd.response[0]; @@ -802,13 +981,16 @@ static void hpm_sdmmc_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en) RT_ASSERT(host->private_data != RT_NULL); struct hpm_mmcsd *mmcsd = (struct hpm_mmcsd *) host->private_data; + RT_ASSERT(mmcsd->sdxc_base != RT_NULL); + SDXC_Type *base = mmcsd->sdxc_base; if (en != 0) { - intc_m_enable_irq_with_priority(mmcsd->irq_num, 1); + sdxc_enable_interrupt_signal(base, SDXC_INT_STAT_CARD_INTERRUPT_MASK, true); + sdxc_enable_interrupt_status(base, SDXC_INT_STAT_CARD_INTERRUPT_MASK, true); } else { - intc_m_disable_irq(mmcsd->irq_num); + sdxc_enable_interrupt_status(base, SDXC_INT_STAT_CARD_INTERRUPT_MASK, false); } } @@ -864,7 +1046,8 @@ int rt_hw_sdio_init(void) struct rt_mmcsd_host *host = NULL; struct hpm_mmcsd *mmcsd = NULL; - for (uint32_t i = 0; i < ARRAY_SIZE(hpm_sdxcs); i++) { + for (uint32_t i = 0; i < ARRAY_SIZE(hpm_sdxcs); i++) + { host = mmcsd_alloc_host(); if (host == NULL) { @@ -922,10 +1105,16 @@ int rt_hw_sdio_init(void) rt_strncpy(host->name, mmcsd->name, RT_NAME_MAX); - host->max_seg_size = 0x80000; + if (!mmcsd->use_noncacheable_buf) + { + mmcsd->data_buf = rt_malloc_align(mmcsd->data_buf_size, CACHELINE_SIZE); + } + RT_ASSERT(mmcsd->data_buf != RT_NULL); + host->max_seg_size = mmcsd->data_buf_size; host->max_dma_segs = 1; host->max_blk_size = 512; - host->max_blk_count = 1024; + host->max_blk_count = mmcsd->data_buf_size / SDMMC_DEFAULT_SECTOR_SIZE; + mmcsd->host = host; @@ -933,7 +1122,7 @@ int rt_hw_sdio_init(void) board_sd_configure_clock(mmcsd->sdxc_base, 375000, true); sdxc_config_t sdxc_config = { 0 }; - sdxc_config.data_timeout = 1000; + sdxc_config.data_timeout = SDXC_DATA_TIMEOUT; sdxc_init(mmcsd->sdxc_base, &sdxc_config); host->private_data = mmcsd; @@ -959,8 +1148,21 @@ int rt_hw_sdio_init(void) rt_thread_mdelay(1); } + if (mmcsd->enable_interrupt_driven) + { + char event_name[RT_NAME_MAX]; + snprintf(event_name, sizeof(event_name), "%s%s", mmcsd->name, "_evt"); + mmcsd->xfer_event = rt_event_create(event_name, RT_IPC_FLAG_FIFO); + RT_ASSERT(mmcsd->xfer_event != RT_NULL); + const uint32_t irq_mask = SDXC_INT_STAT_CMD_COMPLETE_MASK \ + | SDXC_INT_STAT_XFER_COMPLETE_MASK \ + | SDXC_INT_STAT_ERR_INTERRUPT_MASK; + sdxc_enable_interrupt_signal(mmcsd->sdxc_base, irq_mask, true); + } + intc_m_enable_irq_with_priority(mmcsd->irq_num, mmcsd->irq_priority); + mmcsd_change(host); - }; + } if (err != RT_EOK) { diff --git a/bsp/hpmicro/libraries/drivers/drv_spi.c b/bsp/hpmicro/libraries/drivers/drv_spi.c index 2e5e6407d67..bfdfd262761 100644 --- a/bsp/hpmicro/libraries/drivers/drv_spi.c +++ b/bsp/hpmicro/libraries/drivers/drv_spi.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024 HPMicro + * Copyright (c) 2021-2025 HPMicro * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,6 +10,9 @@ * 2023-07-14 HPMicro Manage the DMA buffer alignment in driver * 2023-12-14 HPMicro change state blocking wait to interrupt semaphore wait for DMA * 2024-06-10 HPMicro Add the SPI pin settings + * 2025-03-17 HPMicro Improve SPI driver,support SPI/DSPI/QSPI + * 2025-07-14 HPMicro Check CS pin in xfer API + * 2025-08-05 HPMicro Optimized cache alignment handling for DMA transfers */ #include @@ -23,7 +26,90 @@ #include "hpm_dmamux_drv.h" #include "hpm_l1c_drv.h" +#include "hpm_clock_drv.h" +#define DBG_TAG "drv.spi" +#define DBG_LVL DBG_INFO +#include +#if defined(BSP_USING_SPI0) +#ifndef BSP_SPI0_USING_QUAD_IO +#ifndef BSP_SPI0_USING_DUAL_IO +#ifndef BSP_SPI0_USING_SINGLE_IO +#define BSP_SPI0_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI1) +#ifndef BSP_SPI1_USING_QUAD_IO +#ifndef BSP_SPI1_USING_DUAL_IO +#ifndef BSP_SPI1_USING_SINGLE_IO +#define BSP_SPI1_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI2) +#ifndef BSP_SPI2_USING_QUAD_IO +#ifndef BSP_SPI2_USING_DUAL_IO +#ifndef BSP_SPI2_USING_SINGLE_IO +#define BSP_SPI2_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI3) +#ifndef BSP_SPI3_USING_QUAD_IO +#ifndef BSP_SPI3_USING_DUAL_IO +#ifndef BSP_SPI3_USING_SINGLE_IO +#define BSP_SPI3_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI4) +#ifndef BSP_SPI4_USING_QUAD_IO +#ifndef BSP_SPI4_USING_DUAL_IO +#ifndef BSP_SPI4_USING_SINGLE_IO +#define BSP_SPI4_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI5) +#ifndef BSP_SPI5_USING_QUAD_IO +#ifndef BSP_SPI5_USING_DUAL_IO +#ifndef BSP_SPI5_USING_SINGLE_IO +#define BSP_SPI5_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI6) +#ifndef BSP_SPI6_USING_QUAD_IO +#ifndef BSP_SPI6_USING_DUAL_IO +#ifndef BSP_SPI6_USING_SINGLE_IO +#define BSP_SPI6_USING_SINGLE_IO +#endif +#endif +#endif +#endif + +#if defined(BSP_USING_SPI7) +#ifndef BSP_SPI7_USING_QUAD_IO +#ifndef BSP_SPI7_USING_DUAL_IO +#ifndef BSP_SPI7_USING_SINGLE_IO +#define BSP_SPI7_USING_SINGLE_IO +#endif +#endif +#endif +#endif struct hpm_spi @@ -31,6 +117,8 @@ struct hpm_spi uint32_t instance; char *bus_name; SPI_Type *spi_base; + clock_name_t clk_name; + spi_data_phase_format_t spi_io_mode; spi_control_config_t control_config; struct rt_spi_bus spi_bus; rt_sem_t xfer_sem; @@ -40,12 +128,21 @@ struct hpm_spi dma_resource_t tx_dma; dma_resource_t rx_dma; rt_uint8_t spi_irq; + rt_uint8_t spi_irq_priority; rt_sem_t spi_xfer_done_sem; rt_sem_t txdma_xfer_done_sem; rt_sem_t rxdma_xfer_done_sem; void (*spi_pins_init)(SPI_Type *spi_base); }; +typedef struct { + rt_uint8_t *raw_alloc_tx_buf; + rt_uint8_t *raw_alloc_rx_buf; + rt_uint8_t *aligned_tx_buf; + rt_uint8_t *aligned_rx_buf; + rt_uint32_t aligned_size; +} spi_dma_buf_ctx_t; + static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg); static rt_ssize_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg); @@ -53,14 +150,31 @@ static struct hpm_spi hpm_spis[] = { #if defined(BSP_USING_SPI0) { +#if defined(BSP_SPI0_USING_SINGLE_IO) .bus_name = "spi0", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI0_USING_DUAL_IO) + .bus_name = "dspi0", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI0_USING_QUAD_IO) + .bus_name = "qspi0", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI0, + .clk_name = clock_spi0, #if defined(BSP_SPI0_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI0_TX, .rx_dmamux = HPM_DMA_SRC_SPI0_RX, .spi_irq = IRQn_SPI0, +#if defined(BSP_SPI0_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI0_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI0_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -70,14 +184,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI1) { +#if defined(BSP_SPI1_USING_SINGLE_IO) .bus_name = "spi1", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI1_USING_DUAL_IO) + .bus_name = "dspi1", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI1_USING_QUAD_IO) + .bus_name = "qspi1", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI1, + .clk_name = clock_spi1, #if defined(BSP_SPI1_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI1_TX, .rx_dmamux = HPM_DMA_SRC_SPI1_RX, .spi_irq = IRQn_SPI1, +#if defined(BSP_SPI1_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI1_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI1_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -87,14 +218,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI2) { +#if defined(BSP_SPI2_USING_SINGLE_IO) .bus_name = "spi2", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI2_USING_DUAL_IO) + .bus_name = "dspi2", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI2_USING_QUAD_IO) + .bus_name = "qspi2", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI2, + .clk_name = clock_spi2, #if defined(BSP_SPI2_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI2_TX, .rx_dmamux = HPM_DMA_SRC_SPI2_RX, .spi_irq = IRQn_SPI2, +#if defined(BSP_SPI2_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI2_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI2_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -104,14 +252,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI3) { +#if defined(BSP_SPI3_USING_SINGLE_IO) .bus_name = "spi3", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI3_USING_DUAL_IO) + .bus_name = "dspi3", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI3_USING_QUAD_IO) + .bus_name = "qspi3", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI3, + .clk_name = clock_spi3, #if defined(BSP_SPI3_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI3_TX, .rx_dmamux = HPM_DMA_SRC_SPI3_RX, .spi_irq = IRQn_SPI3, +#if defined(BSP_SPI3_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI3_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI3_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -121,14 +286,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI4) { +#if defined(BSP_SPI4_USING_SINGLE_IO) .bus_name = "spi4", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI4_USING_DUAL_IO) + .bus_name = "dspi4", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI4_USING_QUAD_IO) + .bus_name = "qspi4", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI4, + .clk_name = clock_spi4, #if defined(BSP_SPI4_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI4_TX, .rx_dmamux = HPM_DMA_SRC_SPI4_RX, .spi_irq = IRQn_SPI4, +#if defined(BSP_SPI4_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI4_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI4_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -138,14 +320,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI5) { +#if defined(BSP_SPI5_USING_SINGLE_IO) .bus_name = "spi5", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI5_USING_DUAL_IO) + .bus_name = "dspi5", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI5_USING_QUAD_IO) + .bus_name = "qspi5", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI5, + .clk_name = clock_spi5, #if defined(BSP_SPI5_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI5_TX, .rx_dmamux = HPM_DMA_SRC_SPI5_RX, .spi_irq = IRQn_SPI5, +#if defined(BSP_SPI5_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI5_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI5_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -155,14 +354,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI6) { +#if defined(BSP_SPI6_USING_SINGLE_IO) .bus_name = "spi6", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI6_USING_DUAL_IO) + .bus_name = "dspi6", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI6_USING_QUAD_IO) + .bus_name = "qspi6", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI6, + .clk_name = clock_spi6, #if defined(BSP_SPI6_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI6_TX, .rx_dmamux = HPM_DMA_SRC_SPI6_RX, .spi_irq = IRQn_SPI6, +#if defined(BSP_SPI6_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI6_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI6_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -172,14 +388,31 @@ static struct hpm_spi hpm_spis[] = #endif #if defined(BSP_USING_SPI7) { +#if defined(BSP_SPI7_USING_SINGLE_IO) .bus_name = "spi7", + .spi_io_mode = spi_single_io_mode, +#endif +#if defined(BSP_SPI7_USING_DUAL_IO) + .bus_name = "dspi7", + .spi_io_mode = spi_dual_io_mode, +#endif +#if defined(BSP_SPI7_USING_QUAD_IO) + .bus_name = "qspi7", + .spi_io_mode = spi_quad_io_mode, +#endif .spi_base = HPM_SPI7, + .clk_name = clock_spi7, #if defined(BSP_SPI7_USING_DMA) .enable_dma = RT_TRUE, #endif .tx_dmamux = HPM_DMA_SRC_SPI7_TX, .rx_dmamux = HPM_DMA_SRC_SPI7_RX, .spi_irq = IRQn_SPI7, +#if defined(BSP_SPI7_IRQ_PRIORITY) + .spi_irq_priority = BSP_SPI7_IRQ_PRIORITY, +#else + .spi_irq_priority = 1, +#endif #if !defined BSP_SPI7_USING_HARD_CS .spi_pins_init = init_spi_pins_with_gpio_as_cs, #else @@ -188,7 +421,6 @@ static struct hpm_spi hpm_spis[] = }, #endif }; - static struct rt_spi_ops hpm_spi_ops = { .configure = hpm_spi_configure, @@ -204,49 +436,81 @@ static inline void handle_spi_isr(SPI_Type *ptr) irq_status = spi_get_interrupt_status(ptr); if (irq_status & spi_end_int) { + spi_clear_interrupt_status(ptr, spi_end_int); for (uint32_t i = 0; i < sizeof(hpm_spis) / sizeof(hpm_spis[0]); i++) { if (hpm_spis[i].spi_base == ptr) { rt_sem_release(hpm_spis[i].spi_xfer_done_sem); + break; } } - spi_disable_interrupt(ptr, spi_end_int); - spi_clear_interrupt_status(ptr, spi_end_int); } rt_hw_interrupt_enable(level); } #if defined(BSP_USING_SPI0) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI0, spi0_isr); void spi0_isr(void) { handle_spi_isr(HPM_SPI0); } -SDK_DECLARE_EXT_ISR_M(IRQn_SPI0, spi0_isr); #endif #if defined(BSP_USING_SPI1) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI1, spi1_isr); void spi1_isr(void) { handle_spi_isr(HPM_SPI1); } -SDK_DECLARE_EXT_ISR_M(IRQn_SPI1, spi1_isr); #endif #if defined(BSP_USING_SPI2) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI2, spi2_isr); void spi2_isr(void) { handle_spi_isr(HPM_SPI2); } -SDK_DECLARE_EXT_ISR_M(IRQn_SPI2, spi2_isr); #endif #if defined(BSP_USING_SPI3) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI3, spi3_isr); void spi3_isr(void) { handle_spi_isr(HPM_SPI3); } -SDK_DECLARE_EXT_ISR_M(IRQn_SPI3, spi3_isr); +#endif + +#if defined(BSP_USING_SPI4) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI4, spi4_isr); +void spi4_isr(void) +{ + handle_spi_isr(HPM_SPI4); +} +#endif + +#if defined(BSP_USING_SPI5) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI5, spi5_isr); +void spi5_isr(void) +{ + handle_spi_isr(HPM_SPI5); +} +#endif + +#if defined(BSP_USING_SPI6) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI6, spi6_isr); +void spi6_isr(void) +{ + handle_spi_isr(HPM_SPI6); +} +#endif + +#if defined(BSP_USING_SPI7) +SDK_DECLARE_EXT_ISR_M(IRQn_SPI7, spi7_isr); +void spi7_isr(void) +{ + handle_spi_isr(HPM_SPI7); +} #endif void spi_dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) @@ -273,40 +537,48 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co { spi_timing_config_t timing_config = { 0 }; spi_format_config_t format_config = { 0 }; - struct hpm_spi *spi = RT_NULL; - - spi = (struct hpm_spi *) (device->bus->parent.user_data); + hpm_stat_t stat = status_success; + spi = (struct hpm_spi *)(device->bus->parent.user_data); RT_ASSERT(spi != RT_NULL); - - if (cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32) - { - return -RT_EINVAL; - } - - spi_master_get_default_timing_config(&timing_config); - spi_master_get_default_format_config(&format_config); + /* hpm spi data width support 1 ~ 32 */ + RT_ASSERT((cfg->data_width > 0) && (cfg->data_width <= 32)); spi->spi_pins_init(spi->spi_base); - - timing_config.master_config.clk_src_freq_in_hz = board_init_spi_clock(spi->spi_base); + struct rt_spi_configuration *spi_cfg = cfg; + + if (spi_cfg->mode & RT_SPI_SLAVE) { + spi_slave_get_default_format_config(&format_config); + spi_slave_get_default_control_config(&spi->control_config); + spi->control_config.slave_config.slave_data_only = true; + } else { + spi_master_get_default_timing_config(&timing_config); + spi_master_get_default_format_config(&format_config); + spi_master_get_default_control_config(&spi->control_config); + timing_config.master_config.cs2sclk = spi_cs2sclk_half_sclk_1; + timing_config.master_config.csht = spi_csht_half_sclk_1; + timing_config.master_config.clk_src_freq_in_hz = board_init_spi_clock(spi->spi_base); + if (spi_cfg->max_hz > timing_config.master_config.clk_src_freq_in_hz) { + spi_cfg->max_hz = timing_config.master_config.clk_src_freq_in_hz; + } + timing_config.master_config.sclk_freq_in_hz = spi_cfg->max_hz; + stat = spi_master_timing_init(spi->spi_base, &timing_config); + LOG_D("spi clock frequency = %d, spi sclk frequency = %d", timing_config.master_config.clk_src_freq_in_hz, timing_config.master_config.sclk_freq_in_hz); + if (stat != status_success) { + LOG_E("spi clock frequency = %d, spi sclk frequency = %d \n", timing_config.master_config.clk_src_freq_in_hz, timing_config.master_config.sclk_freq_in_hz); + LOG_E("set spi master sclk frequency fail, SPI_freq / spi_sclk must be an integer multiple and the ratio must be an even number."); + return -RT_EINVAL; + } + } format_config.common_config.data_len_in_bits = cfg->data_width; - format_config.common_config.cpha = cfg->mode & RT_SPI_CPHA ? 1 : 0; - format_config.common_config.cpol = cfg->mode & RT_SPI_CPOL ? 1 : 0; - format_config.common_config.lsb = cfg->mode & RT_SPI_MSB ? false : true; + format_config.common_config.cpha = (cfg->mode & RT_SPI_CPHA) ? spi_sclk_sampling_even_clk_edges : spi_sclk_sampling_odd_clk_edges; + format_config.common_config.cpol = (cfg->mode & RT_SPI_CPOL) ? spi_sclk_high_idle : spi_sclk_low_idle; + format_config.common_config.lsb = (cfg->mode & RT_SPI_MSB) ? false : true; format_config.common_config.mosi_bidir = cfg->mode & RT_SPI_3WIRE ? true : false; spi_format_init(spi->spi_base, &format_config); - if (cfg->max_hz > timing_config.master_config.clk_src_freq_in_hz) - { - cfg->max_hz = timing_config.master_config.clk_src_freq_in_hz; - } - timing_config.master_config.sclk_freq_in_hz = cfg->max_hz; - - spi_master_timing_init(spi->spi_base, &timing_config); - spi_master_get_default_control_config(&spi->control_config); spi->control_config.master_config.addr_enable = false; spi->control_config.master_config.cmd_enable = false; spi->control_config.master_config.token_enable = false; @@ -316,304 +588,779 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co } - -static hpm_stat_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_spi_message *msg) +static rt_err_t hpm_spi_check_params(struct rt_spi_device *device, struct rt_spi_message *msg) { - struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); - hpm_stat_t spi_stat = status_success; + struct rt_spi_message *spi_msg = (struct rt_spi_message *)msg; + +#ifdef RT_USING_QSPI + struct rt_qspi_message *qspi_msg = (struct rt_qspi_message *)msg; + struct rt_qspi_device *qspi_dev = (struct rt_qspi_device *)device; + struct rt_qspi_configuration *qspi_cfg = (struct rt_qspi_configuration *)&qspi_dev->config; +#endif - uint32_t remaining_size = msg->length; - uint32_t transfer_len; - uint8_t *tx_buf = (uint8_t*) msg->send_buf; - uint8_t *rx_buf = (uint8_t*) msg->recv_buf; - while (remaining_size > 0) + if ((device->config.mode == RT_SPI_SLAVE) && (msg->length > SPI_SOC_TRANSFER_COUNT_MAX)) { + LOG_E("spi SPI transfer cannot exceed %d bytes for slave\n", SPI_SOC_TRANSFER_COUNT_MAX); + return -RT_EINVAL; + } + + if ((device->config.mode == RT_SPI_SLAVE) && ((msg->recv_buf == RT_NULL) || (msg->send_buf == RT_NULL))) { - transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); - spi->control_config.common_config.tx_dma_enable = false; - spi->control_config.common_config.rx_dma_enable = false; - if (msg->send_buf != NULL && msg->recv_buf != NULL) - { - spi->control_config.common_config.trans_mode = spi_trans_write_read_together; - spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, tx_buf, transfer_len, rx_buf, transfer_len); + LOG_E("spi only support read write toggther mode for slave\n"); + return -RT_EINVAL; + } +#ifdef RT_USING_QSPI + if (device->bus->mode == RT_SPI_BUS_MODE_QSPI) { + if ((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER) { + if (qspi_msg->instruction.qspi_lines > 1) { + LOG_E("dspi/qspi only support single instruction(command) phase for master\n"); + return -RT_EINVAL; + } } - else if (msg->send_buf != NULL) - { - spi->control_config.common_config.trans_mode = spi_trans_write_only; - spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, (uint8_t*) tx_buf, transfer_len, - NULL, 0); + + if (((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER) && ((msg->recv_buf != RT_NULL) && (msg->send_buf != RT_NULL)) && + (qspi_msg->dummy_cycles > 0)) { + LOG_E("dspi/qspi only not support dummy phase on read write toggther mode for master\n"); + return -RT_EINVAL; } - else - { - spi->control_config.common_config.trans_mode = spi_trans_read_only; - spi_stat = spi_transfer(spi->spi_base, &spi->control_config, - NULL, - NULL, - NULL, 0, rx_buf, transfer_len); + + if (qspi_msg->address.size != 0) { + if (((qspi_msg->address.size != 8) && (qspi_msg->address.size != 16) && (qspi_msg->address.size != 24) && (qspi_msg->address.size != 32))) { + LOG_E("dspi/qspi only support address phase size 8/16/24/32 for master\n"); + return -RT_EINVAL; + } } - if (spi_stat != status_success) - { - break; + if (qspi_msg->address.qspi_lines != 0) { + if ((qspi_msg->address.qspi_lines != 1) && (qspi_msg->address.qspi_lines != 2) && (qspi_msg->address.qspi_lines != 4)) { + LOG_E("dspi/qspi only support address phase qspi lines 1/2/4 for master\n"); + return -RT_EINVAL; + } } - if (tx_buf != NULL) - { - tx_buf += transfer_len; + if (qspi_msg->alternate_bytes.size != 0) { + LOG_E("dspi/qspi not support alternate phase size 0 for master\n"); + return -RT_EINVAL; } - if (rx_buf != NULL) - { - rx_buf += transfer_len; + + if (qspi_cfg->qspi_dl_width != 0) { + switch (qspi_cfg->qspi_dl_width) + { + case 1: + if (qspi_msg->dummy_cycles != 0) { + if ((qspi_msg->dummy_cycles > (4 * 8))) { + LOG_E("spi only support dummy phase cycles < 32 for master\n"); + return -RT_EINVAL; + } + if ((qspi_msg->dummy_cycles != 0) && (qspi_msg->dummy_cycles % 8)) { + LOG_E("The number of cycles should be an integer multiple of 8 for spi master\n"); + return -RT_EINVAL; + } + } + break; + case 2: + if (qspi_msg->dummy_cycles != 0) { + if (qspi_msg->dummy_cycles > (4 * 4)) { + LOG_E("dspi only support dummy phase cycles < 16 for master\n"); + return -RT_EINVAL; + } + if (qspi_msg->dummy_cycles % 4) { + LOG_E("The number of cycles should be an integer multiple of 4 for spi master\n"); + return -RT_EINVAL; + } + } + break; + case 4: + if (qspi_msg->dummy_cycles != 0) { + if (qspi_msg->dummy_cycles > (4 * 2)) { + LOG_E("qspi only support dummy phase cycles < 8 for master\n"); + return -RT_EINVAL; + } + if (qspi_msg->dummy_cycles % 2) { + LOG_E("The number of cycles should be an integer multiple of 2 for spi master\n"); + return -RT_EINVAL; + } + } + break; + default: + LOG_E("spi only support data phase qspi lines 1/2/4 for master\n"); + return -RT_EINVAL; + } } - remaining_size -= transfer_len; } +#endif + return RT_EOK; +} - return spi_stat; +bool hpm_qspi_parse_phase_message(struct rt_spi_device *device, struct rt_qspi_message *msg, + spi_control_config_t *control_config, rt_uint8_t *cmd, rt_uint32_t *addr) +{ + rt_uint8_t dummy_bytes = 0; + bool need_dummy = RT_FALSE; + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); +#ifdef RT_USING_QSPI + struct rt_qspi_message *qspi_msg = (struct rt_qspi_message *)msg; + struct rt_qspi_device *qspi_dev = (struct rt_qspi_device *)device; + struct rt_qspi_configuration *qspi_cfg = (struct rt_qspi_configuration *)&qspi_dev->config; + if ((device->bus->mode == RT_SPI_BUS_MODE_QSPI) && ((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER)) { + if (msg->instruction.qspi_lines == 1) { + (*cmd) = msg->instruction.content; + control_config->master_config.cmd_enable = RT_TRUE; + } else { + control_config->master_config.cmd_enable = RT_FALSE; + } + if (msg->address.qspi_lines != 0) { + control_config->master_config.addr_enable = RT_TRUE; + switch (msg->address.qspi_lines) { + case 1: + control_config->master_config.addr_phase_fmt = spi_address_phase_format_single_io_mode; + break; + case 2: + case 4: + control_config->master_config.addr_phase_fmt = spi_address_phase_format_dualquad_io_mode; + break; + default: + break; + } + } else { + control_config->master_config.addr_enable = RT_FALSE; + } + if (msg->address.size != 0) { + (*addr) = msg->address.content; + control_config->master_config.addr_enable = RT_TRUE; + switch (msg->address.size) { + case 8: + spi_set_address_len(spi->spi_base, addrlen_8bit); + break; + case 16: + spi_set_address_len(spi->spi_base, addrlen_16bit); + break; + case 24: + spi_set_address_len(spi->spi_base, addrlen_24bit); + break; + case 32: + spi_set_address_len(spi->spi_base, addrlen_32bit); + break; + default: + break; + } + } else { + control_config->master_config.addr_enable = RT_FALSE; + } + if (msg->dummy_cycles == 0) { + need_dummy = RT_FALSE; + } else { + need_dummy = RT_TRUE; + switch (msg->qspi_data_lines) + { + case 1: + dummy_bytes = (msg->dummy_cycles + 7) / 8; + break; + case 2: + dummy_bytes = (msg->dummy_cycles + 3) / 4; + break; + case 4: + dummy_bytes = (msg->dummy_cycles + 1) / 2; + break; + default: + break; + } + } + if (dummy_bytes != 0) { + switch (dummy_bytes) + { + case 1: + control_config->common_config.dummy_cnt = spi_dummy_count_1; + break; + case 2: + control_config->common_config.dummy_cnt = spi_dummy_count_2; + break; + case 3: + control_config->common_config.dummy_cnt = spi_dummy_count_3; + break; + case 4: + control_config->common_config.dummy_cnt = spi_dummy_count_4; + break; + default: + break; + } + } + if (qspi_cfg->qspi_dl_width == 1) { + if (msg->qspi_data_lines == 1) { + spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; + } else { + LOG_E("msg data_lines must be 1 when qspi_dl_width is 1, but msg data_lines is %d\n", msg->qspi_data_lines); + } + } else if (qspi_cfg->qspi_dl_width == 2) { + if (msg->qspi_data_lines == 1) { + spi->control_config.common_config.data_phase_fmt = spi_dual_io_mode; + } else if (msg->qspi_data_lines == 2) { + spi->control_config.common_config.data_phase_fmt = spi_quad_io_mode; + } else { + LOG_E("msg data_lines must be 1 or 2 when qspi_dl_width is 2, but msg data_lines is %d\n", msg->qspi_data_lines); + } + } else if (qspi_cfg->qspi_dl_width == 4) { + if (msg->qspi_data_lines == 1) { + spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; + } else if (msg->qspi_data_lines == 2) { + spi->control_config.common_config.data_phase_fmt = spi_dual_io_mode; + } else if (msg->qspi_data_lines == 4) { + spi->control_config.common_config.data_phase_fmt = spi_quad_io_mode; + } else { + spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; + } + } else { + spi->control_config.common_config.data_phase_fmt = spi_single_io_mode; + } + } +#endif + return need_dummy; } +static rt_ssize_t hpm_spi_send_no_data(SPI_Type *ptr, spi_control_config_t *config, uint8_t *cmd, uint32_t *addr, struct rt_qspi_message *qspi_msg) +{ + rt_ssize_t actual_len = 0; + hpm_stat_t spi_stat = status_success; + if (config->master_config.cmd_enable == true || config->master_config.addr_enable == true) { + config->common_config.trans_mode = spi_trans_no_data; + spi_stat = spi_transfer(ptr, config, cmd, addr, NULL, 0, NULL, 0); + if (spi_stat != status_success) { + actual_len = -RT_EIO; + } else { + if (qspi_msg->instruction.qspi_lines > 0) { + actual_len++; + } + if (qspi_msg->address.size > 0) { + switch (qspi_msg->address.size) + { + case 8: + actual_len++; + break; + case 16: + actual_len += 2; + break; + case 24: + actual_len += 3; + break; + case 32: + actual_len += 4; + break; + default: + break; + } + } + } + } + return actual_len; +} +static rt_ssize_t hpm_spi_xfer_polling(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); + rt_ssize_t actual_len = 0; + hpm_stat_t spi_stat = status_success; + struct rt_spi_message *_msg = (struct rt_spi_message *)msg; + struct rt_spi_message *spi_msg = (struct rt_spi_message *)_msg; +#ifdef RT_USING_QSPI + struct rt_qspi_message *qspi_msg = RT_NULL; +#endif + rt_uint32_t remaining_size = _msg->length; + rt_uint32_t transfer_len; + rt_uint8_t *tx_buf = (rt_uint8_t*) _msg->send_buf; + rt_uint8_t *rx_buf = (rt_uint8_t*) _msg->recv_buf; + rt_uint8_t cmd = 0; + rt_uint32_t addr = 0; + rt_uint32_t index = 0; + bool need_dummy = RT_FALSE; + RT_ASSERT(spi != RT_NULL); -hpm_stat_t spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint8_t data_width, uint32_t size) + spi->control_config.common_config.tx_dma_enable = false; + spi->control_config.common_config.rx_dma_enable = false; + if (device->config.mode == RT_SPI_SLAVE) { +#if 0 + spi_slave_enable_data_only(spi->spi_base); + spi_set_transfer_mode(spi->spi_base, spi_trans_write_read_together); +#endif + LOG_E("Spi slave does not support polling transmission\n"); + return -RT_EINVAL; + } + while (_msg != RT_NULL) { + tx_buf = (rt_uint8_t*) _msg->send_buf; + rx_buf = (rt_uint8_t*) _msg->recv_buf; + index = 0; + if (hpm_spi_check_params(device, _msg) != RT_EOK) { + return -RT_EINVAL; + } +#ifdef RT_USING_QSPI + qspi_msg = (struct rt_qspi_message *)_msg; + need_dummy = hpm_qspi_parse_phase_message(device, qspi_msg, &spi->control_config, &cmd, &addr); + remaining_size = _msg->length; + if (remaining_size == 0) { + actual_len = hpm_spi_send_no_data(spi->spi_base, &spi->control_config, &cmd, &addr, qspi_msg); + } +#endif + while (remaining_size > 0) { + transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); + /* Next sub-packet: Disable CMD and ADDR phase for the following packet */ + if (index > 0) { + spi->control_config.master_config.cmd_enable = RT_FALSE; + spi->control_config.master_config.addr_enable = RT_FALSE; + } + if ((_msg->send_buf != NULL) && (_msg->recv_buf != NULL)) { + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, tx_buf, transfer_len, rx_buf, transfer_len); + } + else if (_msg->send_buf != NULL) { + if ((need_dummy == RT_TRUE) && (index == 0)) { + spi->control_config.common_config.trans_mode = spi_trans_dummy_write; + } else { + spi->control_config.common_config.trans_mode = spi_trans_write_only; + } + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, (uint8_t*) tx_buf, transfer_len, NULL, 0); + } + else if (_msg->recv_buf != NULL){ + if ((need_dummy == RT_TRUE) && (index == 0)) { + spi->control_config.common_config.trans_mode = spi_trans_dummy_read; + } else { + spi->control_config.common_config.trans_mode = spi_trans_read_only; + } + spi_stat = spi_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, NULL, 0, rx_buf, transfer_len); + } + if (spi_stat != status_success) { + actual_len = -RT_EIO; + break; + } + if (tx_buf != NULL) { + tx_buf += transfer_len; + } + if (rx_buf != NULL) { + rx_buf += transfer_len; + } + remaining_size -= transfer_len; + actual_len += transfer_len; + index++; + } + _msg = _msg->next; + } + return actual_len; +} + +static hpm_stat_t hpm_spi_tx_dma_config(struct rt_spi_device *device, uint8_t *buff, uint32_t size) { - dma_handshake_config_t config; - config.ch_index = ch_num; - config.dst = (uint32_t)&spi_ptr->DATA; - config.dst_fixed = true; - config.src = src; - config.src_fixed = false; - config.data_width = data_width; - config.size_in_byte = size; - - return dma_setup_handshake(dma_ptr, &config, true); + hpm_stat_t stat = status_success; + uint8_t transfer_width; + uint32_t buf_addr; + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); + dma_resource_t *resource = &spi->tx_dma; + uint32_t core_id = read_csr(CSR_MHARTID); + if (data_len_in_bytes > 2) { + data_len_in_bytes = 4; /* must be 4 aglin */ + /* word */ + transfer_width = DMA_MGR_TRANSFER_WIDTH_WORD; + } else { + /* byte or half_word*/ + transfer_width = data_len_in_bytes - 1; + } + if (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)) { + return status_invalid_argument; + } + buf_addr = core_local_mem_to_sys_address(core_id, (uint32_t)buff); + HPM_CHECK_RET(dma_mgr_set_chn_src_addr(resource, buf_addr)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_width(resource, transfer_width)); + HPM_CHECK_RET(dma_mgr_set_chn_src_width(resource, transfer_width)); + HPM_CHECK_RET(dma_mgr_set_chn_transize(resource, size / data_len_in_bytes)); + return stat; } -hpm_stat_t spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint8_t data_width, uint32_t size) +static hpm_stat_t hpm_spi_tx_dma_start(struct rt_spi_device *device) { - dma_handshake_config_t config; - config.ch_index = ch_num; - config.dst = dst; - config.dst_fixed = false; - config.src = (uint32_t)&spi_ptr->DATA; - config.src_fixed = true; - config.data_width = data_width; - config.size_in_byte = size; - - return dma_setup_handshake(dma_ptr, &config, true); + hpm_stat_t stat = status_success; + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + dma_resource_t *resource = &spi->tx_dma; + HPM_CHECK_RET(dma_mgr_enable_channel(resource)); + return stat; } -static rt_uint32_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_message *msg) + +static hpm_stat_t hpm_spi_rx_dma_config(struct rt_spi_device *device, uint8_t *buff, uint32_t size) { - struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); - hpm_stat_t spi_stat = status_success; - uint32_t remaining_size = msg->length; - uint32_t transfer_len; - uint8_t *raw_alloc_tx_buf = RT_NULL; - uint8_t *raw_alloc_rx_buf = RT_NULL; - uint8_t *aligned_tx_buf = RT_NULL; - uint8_t *aligned_rx_buf = RT_NULL; - uint32_t aligned_len = 0; - if (msg->length <= 0) - { + hpm_stat_t stat = status_success; + uint8_t transfer_width; + uint32_t buf_addr; + uint32_t core_id = read_csr(CSR_MHARTID); + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); + dma_resource_t *resource = &spi->rx_dma; + if (data_len_in_bytes > 2) { + data_len_in_bytes = 4; /* must be 4 aglin */ + /* word */ + transfer_width = DMA_MGR_TRANSFER_WIDTH_WORD; + } else { + /* byte or half_word*/ + transfer_width = data_len_in_bytes - 1; + } + if (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)) { return status_invalid_argument; } - aligned_len = (msg->length + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); - if (msg->send_buf != RT_NULL) - { - if (l1c_dc_is_enabled()) - { - /* The allocated pointer is always RT_ALIGN_SIZE aligned */ - raw_alloc_tx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); - RT_ASSERT(raw_alloc_tx_buf != RT_NULL); - aligned_tx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_tx_buf); - rt_memcpy(aligned_tx_buf, msg->send_buf, msg->length); - l1c_dc_flush((uint32_t) aligned_tx_buf, aligned_len); + buf_addr = core_local_mem_to_sys_address(core_id, (uint32_t)buff); + HPM_CHECK_RET(dma_mgr_set_chn_dst_addr(resource, buf_addr)); + HPM_CHECK_RET(dma_mgr_set_chn_src_width(resource, transfer_width)); + HPM_CHECK_RET(dma_mgr_set_chn_dst_width(resource, transfer_width)); + HPM_CHECK_RET(dma_mgr_set_chn_transize(resource, size / data_len_in_bytes)); + HPM_CHECK_RET(dma_mgr_enable_channel(resource)); + return stat; +} + +static hpm_stat_t hpm_spi_rx_dma_start(struct rt_spi_device *device) +{ + hpm_stat_t stat = status_success; + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + dma_resource_t *resource = &spi->rx_dma; + HPM_CHECK_RET(dma_mgr_enable_channel(resource)); + return stat; +} +static void hpm_spi_transfer_data_cache_handle(struct rt_spi_message *msg, spi_dma_buf_ctx_t *ctx, rt_uint32_t len) +{ + rt_uint32_t transfer_len; + rt_uint8_t *tx_buf = RT_NULL; + rt_uint8_t *rx_buf = RT_NULL; + uint32_t aligned_start = 0; + uint32_t aligned_end = 0; + uint32_t aligned_size = 0; + if (msg->send_buf != RT_NULL) { + if (l1c_dc_is_enabled() == true) { + if (((rt_uint32_t)msg->send_buf % HPM_L1C_CACHELINE_SIZE) || (len % HPM_L1C_CACHELINE_SIZE)) { + ctx->aligned_size = (len + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); + ctx->raw_alloc_tx_buf = (rt_uint8_t*)rt_malloc_align(ctx->aligned_size, HPM_L1C_CACHELINE_SIZE); + RT_ASSERT(ctx->raw_alloc_tx_buf != RT_NULL); + ctx->aligned_tx_buf = ctx->raw_alloc_tx_buf; + rt_memcpy(ctx->aligned_tx_buf, msg->send_buf, len); + l1c_dc_flush((uint32_t) (ctx->aligned_tx_buf), ctx->aligned_size); + } else { + ctx->aligned_tx_buf = (uint8_t*) msg->send_buf; + aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(ctx->aligned_tx_buf)); + aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)(ctx->aligned_tx_buf) + msg->length); + aligned_size = aligned_end - aligned_start; + ctx->aligned_size = aligned_size; + l1c_dc_writeback(aligned_start, aligned_size); + } + } else { + ctx->aligned_tx_buf = (uint8_t*) msg->send_buf; + ctx->aligned_size = len; } - else - { - aligned_tx_buf = (uint8_t*) msg->send_buf; + + } + if (msg->recv_buf != RT_NULL) { + if (l1c_dc_is_enabled() == true) { + if (((rt_uint32_t)msg->recv_buf % HPM_L1C_CACHELINE_SIZE) || (len % HPM_L1C_CACHELINE_SIZE)) { + ctx->aligned_size = (len + HPM_L1C_CACHELINE_SIZE - 1U) & ~(HPM_L1C_CACHELINE_SIZE - 1U); + ctx->raw_alloc_rx_buf = (uint8_t*)rt_malloc_align(ctx->aligned_size, HPM_L1C_CACHELINE_SIZE); + RT_ASSERT(ctx->raw_alloc_rx_buf != RT_NULL); + ctx->aligned_rx_buf = ctx->raw_alloc_rx_buf; + l1c_dc_invalidate((uint32_t)(ctx->aligned_rx_buf), ctx->aligned_size); + } else { + ctx->aligned_rx_buf = (uint8_t*)msg->recv_buf; + ctx->aligned_size = len; + } + } else { + ctx->aligned_rx_buf = (uint8_t*) msg->recv_buf; + ctx->aligned_size = len; } } - if (msg->recv_buf != RT_NULL) - { - if (l1c_dc_is_enabled()) - { - /* The allocated pointer is always RT_ALIGN_SIZE aligned */ - raw_alloc_rx_buf = (uint8_t*)rt_malloc(aligned_len + HPM_L1C_CACHELINE_SIZE - RT_ALIGN_SIZE); - RT_ASSERT(raw_alloc_rx_buf != RT_NULL); - aligned_rx_buf = (uint8_t*)HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)raw_alloc_rx_buf); +} + +static hpm_stat_t hpm_spi_transmit_use_fifo(struct rt_spi_device *device, struct rt_spi_message *msg, rt_uint32_t *remaining_size, + rt_uint8_t *cmd, rt_uint32_t *addr, bool *need_dummy, rt_ssize_t *actual_len) +{ + hpm_stat_t stat = status_fail; + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + if (((*remaining_size) <= SPI_SOC_FIFO_DEPTH) && ((device->config.mode & RT_SPI_MASTER) == RT_SPI_MASTER) + && (msg->send_buf != NULL) && (msg->recv_buf == NULL)) { + spi_enable_interrupt(spi->spi_base, spi_end_int); + if ((*need_dummy) == RT_TRUE) { + spi->control_config.common_config.trans_mode = spi_trans_dummy_write; + } else { + spi->control_config.common_config.trans_mode = spi_trans_write_only; } - else - { - aligned_rx_buf = msg->recv_buf; + stat = spi_control_init(spi->spi_base, &spi->control_config, (*remaining_size), 0); + if (stat != status_success) { + return stat; + } + uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(spi->spi_base); + if (msg->send_buf != NULL) { + for (uint8_t j = 0; j < (*remaining_size); j++) { + switch (data_len_in_bytes) { + case 1: + spi->spi_base->DATA = *(uint8_t *)msg->send_buf; + break; + case 2: + spi->spi_base->DATA = *(uint16_t *)msg->send_buf; + break; + default: + spi->spi_base->DATA = *(uint32_t *)msg->send_buf; + break; + } + msg->send_buf += data_len_in_bytes; + (*actual_len) += data_len_in_bytes; + } } + spi->spi_base->ADDR = SPI_ADDR_ADDR_SET(*addr); + spi->spi_base->CMD = SPI_CMD_CMD_SET(*cmd); + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); } + return stat; +} - uint8_t *tx_buf = aligned_tx_buf; - uint8_t *rx_buf = aligned_rx_buf; - - uint32_t core_id = read_csr(CSR_MHARTID); - spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); - spi->control_config.common_config.tx_dma_enable = false; - spi->control_config.common_config.rx_dma_enable = false; - spi_disable_interrupt(spi->spi_base, spi_end_int); - while (remaining_size > 0) - { - transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); - if (msg->send_buf != NULL && msg->recv_buf != NULL) +static rt_ssize_t hpm_spi_xfer_dma(struct rt_spi_device *device, struct rt_spi_message *msg) +{ + spi_dma_buf_ctx_t dma_buf_ctx = {0}; + rt_uint8_t cmd = 0; + rt_uint32_t addr = 0, aligned_len = 0; + rt_uint32_t remaining_size = msg->length; + rt_uint32_t transfer_len; + rt_uint8_t *tx_buf = RT_NULL; + rt_uint8_t *rx_buf = RT_NULL; + uint32_t aligned_start = 0; + uint32_t aligned_end = 0; + uint32_t aligned_size = 0; + rt_ssize_t actual_len = 0; + bool need_dummy = RT_FALSE; + hpm_stat_t stat = status_success; + rt_uint32_t index; + struct rt_spi_message *_msg = (struct rt_spi_message *)msg; + struct rt_spi_message *spi_msg = (struct rt_spi_message *)_msg; +#ifdef RT_USING_QSPI + struct rt_qspi_message *qspi_msg = RT_NULL; +#endif + struct hpm_spi *spi = (struct hpm_spi *)(device->bus->parent.user_data); + spi_enable_interrupt(spi->spi_base, spi_end_int); + while (_msg != RT_NULL) { + index = 0; + if (hpm_spi_check_params(device, _msg) != RT_EOK) { + return -RT_EINVAL; + } + remaining_size = _msg->length; +#ifdef RT_USING_QSPI + qspi_msg = (struct rt_qspi_message *)_msg; + need_dummy = hpm_qspi_parse_phase_message(device, qspi_msg, &spi->control_config, &cmd, &addr); + if (remaining_size == 0) { + actual_len = hpm_spi_send_no_data(spi->spi_base, &spi->control_config, &cmd, &addr, qspi_msg); + } else +#endif { - spi_enable_interrupt(spi->spi_base, spi_end_int); - spi->control_config.common_config.tx_dma_enable = true; - spi->control_config.common_config.rx_dma_enable = true; - spi->control_config.common_config.trans_mode = spi_trans_write_read_together; - spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, - transfer_len); - if (spi_stat != status_success) - { - break; - } - dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); - spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, - core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), - DMA_TRANSFER_WIDTH_BYTE, transfer_len); - - /* setup spi rx trigger dma transfer*/ - dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); - spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, - core_local_mem_to_sys_address(core_id, (uint32_t) rx_buf), - DMA_TRANSFER_WIDTH_BYTE, transfer_len); - if (spi_stat != status_success) - { - break; + if (remaining_size > 0) { + /* If the length is less than SPI_SOC_FIFO_DEPTH, use fifo mode to transmit data */ + stat = hpm_spi_transmit_use_fifo(device, _msg, &remaining_size, &cmd, &addr, &need_dummy, &actual_len); + if (stat == status_success) { + _msg = _msg->next; + continue; + } + hpm_spi_transfer_data_cache_handle(_msg, &dma_buf_ctx, msg->length); + tx_buf = dma_buf_ctx.aligned_tx_buf; + rx_buf = dma_buf_ctx.aligned_rx_buf; + dma_mgr_disable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); + dma_mgr_disable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); } - dma_mgr_enable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); - dma_mgr_enable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); - rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); - rt_sem_take(spi->txdma_xfer_done_sem, RT_WAITING_FOREVER); - rt_sem_take(spi->rxdma_xfer_done_sem, RT_WAITING_FOREVER); } - else if (msg->send_buf != NULL) - { - spi_enable_interrupt(spi->spi_base, spi_end_int); - spi->control_config.common_config.tx_dma_enable = true; - spi->control_config.common_config.trans_mode = spi_trans_write_only; - spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, transfer_len, 0); - if (spi_stat != status_success) - { - break; + while (remaining_size > 0) { + transfer_len = MIN(SPI_SOC_TRANSFER_COUNT_MAX, remaining_size); + /* Next sub-packet: Disable CMD and ADDR phase for the following packet */ + if (index > 0) { + spi->control_config.master_config.cmd_enable = RT_FALSE; + spi->control_config.master_config.addr_enable = RT_FALSE; } - dmamux_config(HPM_DMAMUX, spi->tx_dma.channel, spi->tx_dmamux, true); - spi_stat = spi_tx_trigger_dma(spi->tx_dma.base, spi->tx_dma.channel, spi->spi_base, - core_local_mem_to_sys_address(core_id, (uint32_t) tx_buf), - DMA_TRANSFER_WIDTH_BYTE, transfer_len); - if (spi_stat != status_success) - { - break; + if (_msg->send_buf != NULL && _msg->recv_buf != NULL) { + dma_mgr_enable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); + dma_mgr_enable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); + spi->control_config.common_config.tx_dma_enable = RT_TRUE; + spi->control_config.common_config.rx_dma_enable = RT_TRUE; + spi->control_config.common_config.trans_mode = spi_trans_write_read_together; + /* for spi_trans_write_read_together mode, the operation sequence is recommended as follows: */ + /* first: config rx dma transfer and start rx dma */ + stat = hpm_spi_rx_dma_config(device, rx_buf, transfer_len); + if (stat != status_success) { + break; + } + stat = hpm_spi_rx_dma_start(device); + if (stat != status_success) { + break; + } + /* second: config tx dma transfer */ + stat = hpm_spi_tx_dma_config(device, tx_buf, transfer_len); + if (stat != status_success) { + break; + } + /* third: config spi */ + stat = spi_control_init(spi->spi_base, &spi->control_config, transfer_len, transfer_len); + if (stat != status_success) { + break; + } + /* fourth: set spi address and enable spi rx /tx dma */ + spi_write_address(spi->spi_base, spi_master_mode, &spi->control_config, &addr); + spi_enable_rx_dma(spi->spi_base); +#if defined(HPM_IP_FEATURE_SPI_DMA_TX_REQ_AFTER_CMD_FO_MASTER) && (HPM_IP_FEATURE_SPI_DMA_TX_REQ_AFTER_CMD_FO_MASTER == 1) + spi_master_enable_tx_dma_request_after_cmd_write(spi->spi_base); +#endif + spi_enable_tx_dma(spi->spi_base); + /* fifth: start tx dma */ + stat = hpm_spi_tx_dma_start(device); + if (stat != status_success) { + break; + } + /* sixth: Write the command, which marks the beginning of an SPI transfer */ + spi_write_command(spi->spi_base, spi_master_mode, &spi->control_config, &cmd); + /* to ensure complete transmission, check both SPI transfer completion and DMA transfer completion */ + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->txdma_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->rxdma_xfer_done_sem, RT_WAITING_FOREVER); + } else if (_msg->send_buf != NULL) { + dma_mgr_enable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); + spi->control_config.common_config.tx_dma_enable = RT_TRUE; + spi->control_config.common_config.rx_dma_enable = RT_FALSE; + if ((need_dummy == RT_TRUE) && (index == 0)) { + spi->control_config.common_config.trans_mode = spi_trans_dummy_write; + } else { + spi->control_config.common_config.trans_mode = spi_trans_write_only; + } + stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, transfer_len, RT_NULL); + if (stat != status_success) { + break; + } + stat = hpm_spi_tx_dma_config(device, tx_buf, transfer_len); + if (stat != status_success) { + break; + } + stat = hpm_spi_tx_dma_start(device); + if (stat != status_success) { + break; + } + /* to ensure complete transmission, check both SPI transfer completion and DMA transfer completion */ + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->txdma_xfer_done_sem, RT_WAITING_FOREVER); + } else if (_msg->recv_buf != NULL) { + dma_mgr_enable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); + spi->control_config.common_config.tx_dma_enable = RT_FALSE; + spi->control_config.common_config.rx_dma_enable = RT_TRUE; + if ((need_dummy == RT_TRUE) && (index == 0)) { + spi->control_config.common_config.trans_mode = spi_trans_dummy_read; + } else { + spi->control_config.common_config.trans_mode = spi_trans_read_only; + } + stat = hpm_spi_rx_dma_config(device, rx_buf, transfer_len); + if (stat != status_success) { + break; + } + stat = hpm_spi_rx_dma_start(device); + if (stat != status_success) { + break; + } + stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, &cmd, &addr, RT_NULL, transfer_len); + if (stat != status_success) { + break; + } + /* to ensure complete transmission, check both SPI transfer completion and DMA transfer completion */ + rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); + rt_sem_take(spi->rxdma_xfer_done_sem, RT_WAITING_FOREVER); } - dma_mgr_enable_chn_irq(&spi->tx_dma, DMA_MGR_INTERRUPT_MASK_TC); - rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); - rt_sem_take(spi->txdma_xfer_done_sem, RT_WAITING_FOREVER); - } - else - { - spi->control_config.common_config.rx_dma_enable = true; - spi->control_config.common_config.trans_mode = spi_trans_read_only; - spi_stat = spi_setup_dma_transfer(spi->spi_base, &spi->control_config, NULL, NULL, 0, transfer_len); - if (spi_stat != status_success) - { - break; + if (tx_buf != NULL) { + tx_buf += transfer_len; } - /* setup spi rx trigger dma transfer*/ - dmamux_config(HPM_DMAMUX, spi->rx_dma.channel, spi->rx_dmamux, true); - spi_stat = spi_rx_trigger_dma(spi->rx_dma.base, spi->rx_dma.channel, spi->spi_base, - core_local_mem_to_sys_address(core_id, (uint32_t) rx_buf), - DMA_TRANSFER_WIDTH_BYTE, transfer_len); - if (spi_stat != status_success) - { - break; + if (rx_buf != NULL) { + rx_buf += transfer_len; } - spi_enable_interrupt(spi->spi_base, spi_end_int); - dma_mgr_enable_chn_irq(&spi->rx_dma, DMA_MGR_INTERRUPT_MASK_TC); - rt_sem_take(spi->spi_xfer_done_sem, RT_WAITING_FOREVER); - rt_sem_take(spi->rxdma_xfer_done_sem, RT_WAITING_FOREVER); + remaining_size -= transfer_len; + actual_len += transfer_len; + index++; } - if (tx_buf != NULL) - { - tx_buf += transfer_len; - } - if (rx_buf != NULL) - { - rx_buf += transfer_len; - } - remaining_size -= transfer_len; - spi->spi_base->CTRL &= ~(SPI_CTRL_TXDMAEN_MASK | SPI_CTRL_RXDMAEN_MASK); - } - - if (l1c_dc_is_enabled() && (msg->length > 0)) - { - /* cache invalidate for receive buff */ - if (aligned_tx_buf != RT_NULL) - { - rt_free(raw_alloc_tx_buf); - raw_alloc_tx_buf = RT_NULL; - aligned_tx_buf = RT_NULL; + if (l1c_dc_is_enabled() && (_msg->length > 0)) { + if (((rt_uint32_t)msg->send_buf % HPM_L1C_CACHELINE_SIZE) || (_msg->length % HPM_L1C_CACHELINE_SIZE)) { + if (dma_buf_ctx.aligned_tx_buf != RT_NULL) { + rt_free_align(dma_buf_ctx.raw_alloc_tx_buf); + dma_buf_ctx.raw_alloc_tx_buf = RT_NULL; + dma_buf_ctx.aligned_tx_buf = RT_NULL; + } + } + if ((l1c_dc_is_enabled() == true) && (_msg->recv_buf != RT_NULL) && (dma_buf_ctx.aligned_rx_buf != RT_NULL)) { + l1c_dc_invalidate((uint32_t) dma_buf_ctx.aligned_rx_buf, dma_buf_ctx.aligned_size); + if (((rt_uint32_t)msg->recv_buf % HPM_L1C_CACHELINE_SIZE) || (_msg->length % HPM_L1C_CACHELINE_SIZE)) { + rt_memcpy(_msg->recv_buf, dma_buf_ctx.aligned_rx_buf, _msg->length); + rt_free_align(dma_buf_ctx.raw_alloc_rx_buf); + dma_buf_ctx.raw_alloc_rx_buf = RT_NULL; + dma_buf_ctx.aligned_rx_buf = RT_NULL; + } + } } - - if (aligned_rx_buf != RT_NULL) - { - l1c_dc_invalidate((uint32_t) aligned_rx_buf, aligned_len); - rt_memcpy(msg->recv_buf, aligned_rx_buf, msg->length); - rt_free(raw_alloc_rx_buf); - raw_alloc_rx_buf = RT_NULL; - aligned_rx_buf = RT_NULL; + if (stat != status_success) { + actual_len = -RT_EIO; + break; } + _msg = _msg->next; } - - return spi_stat; + spi_disable_interrupt(spi->spi_base, spi_end_int); + return actual_len; } - static rt_ssize_t hpm_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *msg) { RT_ASSERT(device != RT_NULL); RT_ASSERT(msg != RT_NULL); RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL); + rt_ssize_t len; cs_ctrl_callback_t cs_pin_control = (cs_ctrl_callback_t) device->parent.user_data; struct hpm_spi *spi = (struct hpm_spi *) (device->bus->parent.user_data); hpm_stat_t spi_stat = status_success; + if (device->cs_pin == PIN_NONE) { + if ((cs_pin_control != NULL) && msg->cs_take) { + cs_pin_control(SPI_CS_TAKE); + } + } else { + if (msg->cs_take && !(device->config.mode & RT_SPI_NO_CS)) { + if (device->config.mode & RT_SPI_CS_HIGH) { + rt_pin_write(device->cs_pin, PIN_HIGH); + } else { + rt_pin_write(device->cs_pin, PIN_LOW); + } + } - if ((cs_pin_control != NULL) && msg->cs_take) - { - cs_pin_control(SPI_CS_TAKE); } - if (spi->enable_dma) - { - spi_stat = hpm_spi_xfer_dma(device, msg); - } - else - { - spi_stat = hpm_spi_xfer_polling(device, msg); + if (spi->enable_dma) { + len = hpm_spi_xfer_dma(device, msg); + } else { + len = hpm_spi_xfer_polling(device, msg); } - if (spi_stat != status_success) - { - msg->length = 0; + if (device->cs_pin == PIN_NONE) { + if ((cs_pin_control != NULL) && msg->cs_release) { + cs_pin_control(SPI_CS_RELEASE); + } + } else { + if (msg->cs_release && !(device->config.mode & RT_SPI_NO_CS)) { + if (device->config.mode & RT_SPI_CS_HIGH) { + rt_pin_write(device->cs_pin, PIN_LOW); + } else { + rt_pin_write(device->cs_pin, PIN_HIGH); + } + } } + return len; +} - if ((cs_pin_control != NULL) && msg->cs_release) - { - cs_pin_control(SPI_CS_RELEASE); - } +#ifdef RT_USING_QSPI +void enter_qspi_mode(struct rt_qspi_device *device) +{ + (void)device; +} - return msg->length; +void exit_qspi_mode(struct rt_qspi_device *device) +{ + (void)device; } +#endif rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, cs_ctrl_callback_t callback) { @@ -621,15 +1368,39 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, RT_ASSERT(device_name != RT_NULL); rt_err_t result; - struct rt_spi_device *spi_device; +#ifdef RT_USING_QSPI + struct rt_qspi_device *qspi_dev; + qspi_dev = (struct rt_qspi_device *) rt_malloc(sizeof(struct rt_qspi_device)); + qspi_dev->enter_qspi_mode = enter_qspi_mode; + qspi_dev->exit_qspi_mode = exit_qspi_mode; + RT_ASSERT(qspi_dev != RT_NULL); + result = rt_spi_bus_attach_device(&qspi_dev->parent, device_name, bus_name, (void*)callback); + RT_ASSERT(result == RT_EOK); + struct hpm_spi *spi = RT_NULL; + spi = (struct hpm_spi *)(qspi_dev->parent.bus->parent.user_data); + switch (spi->spi_io_mode) { + case spi_single_io_mode: + qspi_dev->config.qspi_dl_width = 1; + break; + case spi_dual_io_mode: + qspi_dev->config.qspi_dl_width = 2; + break; + case spi_quad_io_mode: + qspi_dev->config.qspi_dl_width = 4; + break; + default: + qspi_dev->config.qspi_dl_width = 1; + break; + } +#else + struct rt_spi_device *spi_device; /* attach the device to spi bus*/ spi_device = (struct rt_spi_device *) rt_malloc(sizeof(struct rt_spi_device)); RT_ASSERT(spi_device != RT_NULL); - result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void*)callback); RT_ASSERT(result == RT_EOK); - +#endif return result; } @@ -639,33 +1410,58 @@ int rt_hw_spi_init(void) rt_err_t ret = RT_EOK; hpm_stat_t stat; - + dma_mgr_chn_conf_t chg_config; for (uint32_t i = 0; i < sizeof(hpm_spis) / sizeof(hpm_spis[0]); i++) { struct hpm_spi *spi = &hpm_spis[i]; - spi->spi_bus.parent.user_data = spi; + clock_add_to_group(spi->clk_name, BOARD_RUNNING_CORE & 0x1); if (spi->enable_dma) { + dma_mgr_get_default_chn_config(&chg_config); + chg_config.src_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + chg_config.dst_width = DMA_MGR_TRANSFER_WIDTH_BYTE; + /* spi tx dma config */ stat = dma_mgr_request_resource(&spi->tx_dma); - dma_mgr_install_chn_tc_callback(&spi->tx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); if (stat != status_success) { + LOG_E("[spi%d]tx dma request resource failed\n", i); return -RT_ERROR; } - + chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; + chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; + chg_config.dst_addr = (uint32_t)&spi->spi_base->DATA; + chg_config.en_dmamux = true; + chg_config.dmamux_src = spi->tx_dmamux; + dma_mgr_setup_channel(&spi->tx_dma, &chg_config); + dma_mgr_install_chn_tc_callback(&spi->tx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); + /* spi rx dma config */ stat = dma_mgr_request_resource(&spi->rx_dma); - dma_mgr_install_chn_tc_callback(&spi->rx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); - if (stat != status_success) - { + if (stat != status_success) { + LOG_E("[spi%d]rx dma request resource failed\n", i); return -RT_ERROR; } - intc_m_enable_irq_with_priority(hpm_spis[i].spi_irq, 2); + chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; + chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; + chg_config.src_addr = (uint32_t)&spi->spi_base->DATA; + chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; + chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; + chg_config.en_dmamux = true; + chg_config.dmamux_src = spi->rx_dmamux; + dma_mgr_setup_channel(&spi->rx_dma, &chg_config); + dma_mgr_install_chn_tc_callback(&spi->rx_dma, spi_dma_channel_tc_callback, (void *)&hpm_spis[i]); + + intc_m_enable_irq_with_priority(hpm_spis[i].spi_irq, hpm_spis[i].spi_irq_priority); dma_mgr_enable_dma_irq_with_priority(&spi->tx_dma, 1); dma_mgr_enable_dma_irq_with_priority(&spi->rx_dma, 1); } - +#ifdef RT_USING_QSPI + ret = rt_qspi_bus_register(&spi->spi_bus, spi->bus_name, &hpm_spi_ops); +#else ret = rt_spi_bus_register(&spi->spi_bus, spi->bus_name, &hpm_spi_ops); +#endif if (ret != RT_EOK) { break; diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw.c b/bsp/hpmicro/libraries/drivers/drv_tsw.c new file mode 100644 index 00000000000..79f30222509 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_tsw.c @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2025-3-31 Jiading Initial version + */ + +#include + +#ifdef BSP_USING_TSW +#include +#include "drv_tsw.h" +#include "board.h" + +#if defined(BSP_USING_TSW_PHY_RTL8211) +#include "hpm_rtl8211.h" +#endif + +ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(TSW_SOC_DATA_BUS_WIDTH) uint8_t send_buff[TSW_SEND_DESC_COUNT][TSW_SEND_BUFF_LEN]; +ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(TSW_SOC_DATA_BUS_WIDTH) uint8_t recv_buff[TSW_RECV_DESC_COUNT][TSW_RECV_BUFF_LEN]; +ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(TSW_SOC_DATA_BUS_WIDTH) tsw_frame_t frame[TSW_FRAME_BUFF_COUNT]; + +struct eth_device eth0_dev; +static tsw_device tsw0_dev; + +static tsw_buff_config_t tsw_rx_buff_cfg = {.buffer = (uint32_t)recv_buff, + .count = TSW_RECV_DESC_COUNT, + .size = TSW_RECV_BUFF_LEN + }; + +static tsw_buff_config_t tsw_tx_buff_cfg = {.buffer = (uint32_t)send_buff, + .count = TSW_SEND_DESC_COUNT, + .size = TSW_SEND_BUFF_LEN + }; + +static hpm_tsw_t tsw = {.name = "E0", + .base = BOARD_TSW, + .port = BOARD_TSW_PORT, + .irq_num = IRQn_TSW_0, + .inf = BOARD_TSW_PORT_ITF, + .eth_dev = ð0_dev, + .tsw_dev = &tsw0_dev, + .rx_buff_cfg = &tsw_rx_buff_cfg, + .tx_buff_cfg = &tsw_tx_buff_cfg, + .tx_delay = BOARD_TSW_PORT3_RGMII_TX_DLY, + .rx_delay = BOARD_TSW_PORT3_RGMII_RX_DLY + }; + +mac_init_t mac_init[] = { + {MAC0_ADDR0, MAC0_ADDR1, MAC0_ADDR2, MAC0_ADDR3, MAC0_ADDR4, MAC0_ADDR5} +}; + +static hpm_tsw_t *s_geths[] = { + &tsw +}; + +ATTR_WEAK rt_err_t tsw_get_mac_address(TSW_Type *ptr, uint8_t *mac) +{ + /* load MAC address from MACRO definitions */ + SMEMCPY(mac, &mac_init[0], TSW_MAC_COUNT); + + return RT_EOK; +} + +static rt_err_t hpm_tsw_init(tsw_device *init) +{ + tsw_dma_config_t config; + uint8_t *ptx, *prx; + rtl8211_config_t phy_config; + + /* Set RGMII clock delay */ + if (init->media_interface == tsw_port_phy_itf_rgmii) { + tsw_set_port_clock_delay(init->instance, init->port, init->tx_delay, init->rx_delay); + } + + /* Disable all MACs(TX/RX) */ + tsw_ep_disable_all_mac_ctrl(init->instance, tsw_mac_type_emac); + + /* Set MAC Address */ + tsw_ep_set_mac_addr(init->instance, init->port, init->mac, true); + + /* Set MAC Mode: GMII, CLKSEL: REFCLK */ + tsw_ep_set_mac_mode(init->instance, init->port, init->media_interface == tsw_port_phy_itf_rgmii ? tsw_mac_mode_gmii : tsw_mac_mode_mii); + + /* Set port PHY interface */ + tsw_set_port_interface(init->instance, init->port, init->media_interface); + + /* Enable all MACs(TX/RX) */ + tsw_ep_enable_all_mac_ctrl(init->instance, tsw_mac_type_emac); + + /* Clear CAM */ + tsw_clear_cam(init->instance); + + /* Wait for CAM clearing completion */ + rt_thread_mdelay(10); + + /* Enable VLAN-ID 1 at all ports */ + tsw_set_cam_vlan_port(init->instance); + + /* Get the default DMA config */ + tsw_get_default_dma_config(&config); + + /* Initialize DMA for sending */ + tsw_init_send(init->instance, &config); + + ptx = (uint8_t *)(init->tx_buff_cfg->buffer); + for (uint8_t i = 0; i < init->tx_buff_cfg->count; i++) { + ptx[i * init->tx_buff_cfg->size] = init->port + 1; + } + + /* Initialize DMA for receiving */ + config.irq = true; + tsw_init_recv(init->instance, &config); + + prx = (uint8_t *)(init->rx_buff_cfg->buffer); + for (uint8_t i = 0; i < init->rx_buff_cfg->count; i++) { + tsw_commit_recv_desc(init->instance, &prx[i * init->rx_buff_cfg->size], init->rx_buff_cfg->size, i); + } + + /* Enable TSW IRQ */ + intc_m_enable_irq(init->irq_number); + + return RT_EOK; +} + +static rt_err_t rt_hpm_tsw_init(rt_device_t dev) +{ + uint8_t mac[TSW_MAC_COUNT]; + + tsw_device *tsw_dev = (tsw_device *)dev->user_data; + + /* Initialize GPIOs */ + board_init_tsw_pins(tsw_dev->instance); + + /* Reset an TSW PHY */ + board_reset_tsw_phy(tsw_dev->instance, tsw_dev->port); + + /* Get MAC address */ + tsw_get_mac_address(tsw_dev->instance, mac); + + /* Set mac0 address */ + memcpy(tsw_dev->mac, mac, TSW_MAC_COUNT); + + /* Initialize MAC and DMA */ + if (hpm_tsw_init(tsw_dev) == 0) { + LOG_D("Ethernet control initialize successfully\n"); + return RT_EOK; + } else { + LOG_D("Ethernet control initialize unsuccessfully\n"); + return -RT_ERROR; + } +} + +static rt_err_t rt_hpm_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_hpm_tsw_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_ssize_t rt_hpm_tsw_read(rt_device_t dev, rt_off_t pos, void * buffer, rt_size_t size) +{ + return 0; +} + +static rt_ssize_t rt_hpm_tsw_write(rt_device_t dev, rt_off_t pos, const void * buffer, rt_size_t size) +{ + return 0; +} + +static rt_err_t rt_hpm_tsw_control(rt_device_t dev, int cmd, void * args) +{ + uint8_t *mac = (uint8_t *)args; + tsw_device *tsw_dev = (tsw_device *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + if (args != NULL) { + tsw_get_mac_address(tsw_dev->instance, (uint8_t *)mac); + SMEMCPY(args, mac, TSW_MAC_COUNT); + } else { + return -RT_ERROR; + } + break; + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_hpm_tsw_tx(rt_device_t dev, struct pbuf * p) +{ + struct pbuf *q; + static uint32_t i = 0; + uint32_t id; + uint32_t length = TSW_SOC_SWITCH_HEADER_LEN; + tsw_device *tsw_dev = (tsw_device *)dev->user_data; + uint8_t *ptx = ((uint8_t *)tsw_dev->tx_buff_cfg->buffer); + + id = i++ % TSW_SOC_DMA_MAX_DESC_COUNT; + + for (q = p; q != NULL; q = q->next) { + SMEMCPY(&ptx[id * tsw_dev->tx_buff_cfg->size + TSW_SOC_SWITCH_HEADER_LEN], q->payload, q->len); + length += q->len; + } + + tsw_send_frame(tsw_dev->instance, &ptx[id * tsw_dev->tx_buff_cfg->size], length, id); + + return ERR_OK; +} + +static struct pbuf *rt_hpm_tsw_rx(rt_device_t dev) +{ + struct pbuf *p = NULL, *q; + static uint8_t idx = 0; + tsw_device *tsw_dev = (tsw_device *)dev->user_data; + uint8_t *prx = (uint8_t *)tsw_dev->rx_buff_cfg->buffer; + + if (frame[idx].length > TSW_SOC_SWITCH_HEADER_LEN) { + /* Allocate a pbuf chain of pbufs from the lwIP buffer pool */ + p = pbuf_alloc(PBUF_RAW, frame[idx].length - TSW_SOC_SWITCH_HEADER_LEN, PBUF_POOL); + if (p != NULL) { + for (q = p; q != NULL; q = q->next) { + /* pass the buffer to pbuf */ + frame[idx].buffer = &prx[frame[idx].id * tsw_dev->rx_buff_cfg->size]; + SMEMCPY(q->payload, &frame[idx].buffer[TSW_SOC_SWITCH_HEADER_LEN], q->len); + frame[idx].length = 0; + idx++; + idx %= TSW_FRAME_BUFF_COUNT; + } + } + } + + return p; +} + +static void eth_rx_callback(struct eth_device* dev) +{ + rt_err_t result; + result = eth_device_ready(dev); + if (result != RT_EOK) { + LOG_I("Receive callback error = %d\n", result); + } +} + +void isr_tsw(hpm_tsw_t *obj) +{ + static int idx = 0; + uint8_t *prx = (uint8_t *)obj->tsw_dev->rx_buff_cfg->buffer; + + tsw_recv_frame(obj->base, &frame[idx]); + tsw_commit_recv_desc(obj->base, &prx[idx * obj->tsw_dev->rx_buff_cfg->size], TSW_RECV_BUFF_LEN, idx); + idx++; + idx %= TSW_FRAME_BUFF_COUNT; + eth_rx_callback(obj->eth_dev); +} + +SDK_DECLARE_EXT_ISR_M(IRQn_TSW_0, isr_tsw_port_cpu) +void isr_tsw_port_cpu(void) +{ + isr_tsw(&tsw); +} + +int rt_hw_tsw_init(void) +{ + rt_err_t err = RT_ERROR; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_geths); i++) { + /* Set TX & RX buffer config */ + s_geths[i]->tsw_dev->tx_buff_cfg = s_geths[i]->tx_buff_cfg; + s_geths[i]->tsw_dev->rx_buff_cfg = s_geths[i]->rx_buff_cfg; + + /* Set media interface */ + s_geths[i]->tsw_dev->media_interface = s_geths[i]->inf; + + /* Set instance */ + s_geths[i]->tsw_dev->instance = s_geths[i]->base; + + /* Set Port */ + s_geths[i]->tsw_dev->port = s_geths[i]->port; + + /* Set TX/RX delay */ + s_geths[i]->tsw_dev->tx_delay = s_geths[i]->tx_delay; + s_geths[i]->tsw_dev->rx_delay = s_geths[i]->rx_delay; + + /* Set IRQ number */ + s_geths[i]->tsw_dev->irq_number = s_geths[i]->irq_num; + + /* Set the parent parameters */ + s_geths[i]->eth_dev->parent.init = rt_hpm_tsw_init; + s_geths[i]->eth_dev->parent.close = rt_hpm_tsw_close; + s_geths[i]->eth_dev->parent.read = rt_hpm_tsw_read; + s_geths[i]->eth_dev->parent.write = rt_hpm_tsw_write; + s_geths[i]->eth_dev->parent.control = rt_hpm_tsw_control; + + s_geths[i]->eth_dev->parent.user_data = s_geths[i]->tsw_dev; + + s_geths[i]->eth_dev->eth_rx = rt_hpm_tsw_rx; + s_geths[i]->eth_dev->eth_tx = rt_hpm_tsw_tx; + + err = eth_device_init(s_geths[i]->eth_dev, s_geths[i]->name); + + if (RT_EOK == err) { + LOG_D("Ethernet device %d initialize successfully!\n", i); + } else { + LOG_D("Ethernet device %d initialize unsuccessfully!\n"); + return err; + } + } + + return err; +} +INIT_DEVICE_EXPORT(rt_hw_tsw_init); +#endif /* BSP_USING_TSW */ diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw.h b/bsp/hpmicro/libraries/drivers/drv_tsw.h new file mode 100644 index 00000000000..fc612ec9b06 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_tsw.h @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_TSW_H +#define DRV_TSW_H + +#include +#include "hpm_tsw_drv.h" +#include "board.h" + +#define TSW_MAC_COUNT (6U) +#define TSW_FRAME_BUFF_COUNT (16U) + +typedef enum { + TSW_MAC_ADDR_PARA_ERROR = -1, + TSW_MAC_ADDR_FROM_OTP_MAC, + TSW_MAC_ADDR_FROM_OTP_UUID, + TSW_MAC_ADDR_FROM_MACRO +} tsw_mac_addr_t; + +typedef struct { + uint32_t buffer; + uint16_t count; + uint16_t size; +} tsw_buff_config_t; + +typedef struct { + uint8_t mac_addr0; + uint8_t mac_addr1; + uint8_t mac_addr2; + uint8_t mac_addr3; + uint8_t mac_addr4; + uint8_t mac_addr5; +} mac_init_t; + +typedef struct { + TSW_Type *instance; + uint8_t port; + tsw_buff_config_t *rx_buff_cfg; + tsw_buff_config_t *tx_buff_cfg; + uint8_t mac[TSW_MAC_COUNT]; + uint8_t media_interface; + uint32_t irq_number; + bool int_refclk; + uint8_t tx_delay; + uint8_t rx_delay; +} tsw_device; + +typedef struct { + const char *name; + TSW_Type *base; + clock_name_t clock_name; + int32_t irq_num; + uint8_t inf; + struct eth_device *eth_dev; + tsw_device *tsw_dev; + uint8_t port; + tsw_buff_config_t *rx_buff_cfg; + tsw_buff_config_t *tx_buff_cfg; + uint8_t tx_delay; + uint8_t rx_delay; + bool int_refclk; +} hpm_tsw_t; + +#define IS_UUID_INVALID(UUID) (UUID[0] == 0 && \ + UUID[1] == 0 && \ + UUID[2] == 0 && \ + UUID[3] == 0) + +#define IS_MAC_INVALID(MAC) (MAC[0] == 0 && \ + MAC[1] == 0 && \ + MAC[2] == 0 && \ + MAC[3] == 0 && \ + MAC[4] == 0 && \ + MAC[5] == 0) + +#ifndef MAC0_ADDR0 +#define MAC0_ADDR0 (0x98U) +#endif + +#ifndef MAC0_ADDR1 +#define MAC0_ADDR1 (0x2CU) +#endif + +#ifndef MAC0_ADDR2 +#define MAC0_ADDR2 (0xBCU) +#endif + +#ifndef MAC0_ADDR3 +#define MAC0_ADDR3 (0xB1U) +#endif + +#ifndef MAC0_ADDR4 +#define MAC0_ADDR4 (0x9FU) +#endif + +#ifndef MAC0_ADDR5 +#define MAC0_ADDR5 (0x17U) +#endif + +int rt_hw_tsw_init(void); + +#endif /* DRV_TSW_H */ + diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c new file mode 100644 index 00000000000..7eb80740897 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Change Logs: + * Date Author Notes + * 2025-3-31 Jiading Initial version + */ + +#include "rtthread.h" + +#ifdef RT_USING_PHY +#include +#include +#include "hpm_tsw_drv.h" +#include "drv_tsw_phy.h" +#include "hpm_tsw_phy.h" +#include "hpm_soc.h" +#include "netif/ethernetif.h" +#include "board.h" + +typedef struct { + TSW_Type *instance; + uint8_t port; +} tsw_phy_instance_t; + +typedef struct +{ + char *mdio_name; + tsw_phy_instance_t *phy_ins; + struct eth_device *eth_dev; + phy_device_t *phy_dev; + struct rt_mdio_bus *mdio_bus; +} tsw_phy_handle_t; + +typedef struct +{ + uint8_t phy_handle_cnt; + tsw_phy_handle_t **phy_handle; +} tsw_phy_monitor_handle_t; + +extern struct eth_device eth0_dev; +static phy_device_t phy0_dev; +static struct rt_mdio_bus_ops mdio0_bus_ops; +static struct rt_mdio_bus mdio0_bus = {.ops = &mdio0_bus_ops}; +static tsw_phy_instance_t instance = {.instance = BOARD_TSW, + .port = BOARD_TSW_PORT + }; + +static tsw_phy_handle_t tsw_phy_handle = { + .phy_ins = &instance, + .eth_dev = ð0_dev, + .phy_dev = &phy0_dev, + .mdio_name = "MDIO0", + .mdio_bus = &mdio0_bus, +}; + +static tsw_phy_handle_t *s_gphys[] = { + &tsw_phy_handle +}; + +tsw_phy_monitor_handle_t phy_monitor_handle = { + .phy_handle_cnt = ARRAY_SIZE(s_gphys), + .phy_handle = s_gphys +}; + +static struct rt_phy_ops phy_ops; + +static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz) +{ + tsw_phy_instance_t *phy_ins = (tsw_phy_instance_t *)object; + + if (phy_ins->instance == HPM_TSW) { + rtl8211_config_t phy_config; + + /* Set MDC clock frequency */ + tsw_ep_set_mdio_config(phy_ins->instance, phy_ins->port, src_clock_hz / (2 * PHY_MDIO_CLK_FREQ) - 1); + + /* PHY Reset */ + rtl8211_reset(phy_ins->instance, phy_ins->port); + rtl8211_basic_mode_default_config(phy_ins->instance, &phy_config); + if (rtl8211_basic_mode_init(phy_ins->instance, phy_ins->port, &phy_config) == true) { + return PHY_STATUS_OK; + } else { + return PHY_STATUS_FAIL; + } + } + + return -RT_EINVAL; +} + +static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + hpm_stat_t stat; + tsw_phy_instance_t *phy_ins = ((struct rt_mdio_bus *)bus)->hw_obj; + + stat = tsw_ep_mdio_read(phy_ins->instance, phy_ins->port, addr, reg, (uint16_t *)data); + + if (stat == status_success) { + return size; + } else { + return 0; + } +} + +static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size) +{ + hpm_stat_t stat; + tsw_phy_instance_t *phy_ins = ((struct rt_mdio_bus *)bus)->hw_obj; + + stat = tsw_ep_mdio_write(phy_ins->instance, phy_ins->port, addr, reg, *(uint16_t *)data); + + if (stat == status_success) { + return size; + } else { + return 0; + } +} + +static rt_phy_status phy_get_link_status(rt_phy_t *phy, rt_bool_t *status) +{ + tsw_phy_instance_t *phy_ins = phy->bus->hw_obj; + tsw_phy_status_t phy_status; + + if (phy_ins->instance == HPM_TSW) { + #if defined(__USE_RTL8211) && __USE_RTL8211 + rtl8211_get_phy_status(phy_ins->instance, phy_ins->port, &phy_status); + #endif + } + + *status = phy_status.tsw_phy_link; + + return PHY_STATUS_OK; +} + +static rt_phy_status phy_get_link_speed_duplex(rt_phy_t *phy, rt_uint32_t *speed, rt_uint32_t *duplex) +{ + tsw_phy_instance_t *phy_ins = phy->bus->hw_obj; + tsw_phy_status_t phy_status; + + if (phy_ins->instance == HPM_TSW) { + #if defined(__USE_RTL8211) && __USE_RTL8211 + rtl8211_get_phy_status(phy_ins->instance, phy_ins->port, &phy_status); + #endif + } + + *speed = phy_status.tsw_phy_speed; + *duplex = phy_status.tsw_phy_duplex; + + return PHY_STATUS_OK; +} + +static void phy_poll_status(void *parameter) +{ + int ret; + phy_info_t phy_info; + rt_bool_t status; + rt_device_t dev; + rt_phy_msg_t msg; + rt_uint32_t speed, duplex; + phy_device_t *phy_dev; + struct eth_device* eth_dev; + char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"}; + tsw_port_speed_t port_speed[] = {tsw_port_speed_10mbps, tsw_port_speed_100mbps, tsw_port_speed_1000mbps}; + tsw_phy_monitor_handle_t *phy_monitor_handle = (tsw_phy_monitor_handle_t *)parameter; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) { + eth_dev = phy_monitor_handle->phy_handle[i]->eth_dev; + phy_dev = phy_monitor_handle->phy_handle[i]->phy_dev; + + phy_dev->phy.ops->get_link_status(&phy_dev->phy, &status); + + if (status) { + phy_dev->phy.ops->get_link_speed_duplex(&phy_dev->phy, &phy_info.phy_speed, &phy_info.phy_duplex); + + ret = memcmp(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + if (ret != 0) { + memcpy(&phy_dev->phy_info, &phy_info, sizeof(phy_info_t)); + } + } + + if (phy_dev->phy_link != status) { + phy_dev->phy_link = status ? PHY_LINK_UP : PHY_LINK_DOWN; + eth_device_linkchange(eth_dev, status); + LOG_I("PHY Status: %s", status ? "Link up" : "Link down\n"); + if (status == PHY_LINK_UP) { + LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]); + LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex"); + tsw_set_port_speed(phy_monitor_handle->phy_handle[i]->phy_ins->instance, phy_monitor_handle->phy_handle[i]->phy_ins->port, port_speed[phy_dev->phy_info.phy_speed]); + if (!(phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX)) { + LOG_E("Error: PHY is in half duplex now, but TSW MAC supports only full duplex mode!\n"); + return; + } + } + } + } +} + +static void phy_detection(void *parameter) +{ + phy_device_t *phy_dev = (phy_device_t *)parameter; + + if (phy_dev->phy.ops->init(phy_dev->phy.bus->hw_obj, 0, PHY_MDIO_CSR_CLK_FREQ) != PHY_STATUS_OK) { + LOG_E("No any PHY device is detected! Please check your hardware!\n"); + } + + return; + +} + +static void phy_monitor_thread_entry(void *args) +{ + rt_timer_t phy_status_timer; + + tsw_phy_monitor_handle_t *phy_monitor_handle = (tsw_phy_monitor_handle_t *)args; + + for (uint32_t i = 0; i < phy_monitor_handle->phy_handle_cnt; i++) { + LOG_D("Detect a PHY%d\n", i); + phy_detection(phy_monitor_handle->phy_handle[i]->phy_dev); + } + + phy_status_timer = rt_timer_create("PHY_Monitor", phy_poll_status, phy_monitor_handle, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER); + + if (!phy_status_timer || rt_timer_start(phy_status_timer) != RT_EOK) { + LOG_E("Failed to start link change detection timer\n"); + } +} + +int phy_device_register(void) +{ + rt_err_t err = -RT_ERROR; + rt_thread_t thread_phy_monitor; + + /* Set ops for PHY */ + phy_ops.init = phy_init; + phy_ops.get_link_status = phy_get_link_status; + phy_ops.get_link_speed_duplex = phy_get_link_speed_duplex; + + for (uint32_t i = 0; i < ARRAY_SIZE(s_gphys); i++) { + /* Set PHY address */ + s_gphys[i]->phy_dev->phy.addr = 0xffff; + + /* Set MIDO bus */ + s_gphys[i]->mdio_bus->hw_obj = s_gphys[i]->phy_ins; + s_gphys[i]->mdio_bus->name = s_gphys[i]->mdio_name; + s_gphys[i]->mdio_bus->ops->read = phy_read; + s_gphys[i]->mdio_bus->ops->write = phy_write; + s_gphys[i]->phy_dev->phy.bus = s_gphys[i]->mdio_bus; + s_gphys[i]->phy_dev->phy.ops = &phy_ops; + + rt_hw_phy_register(&s_gphys[i]->phy_dev->phy, NULL); + } + + /* Start PHY monitor */ + thread_phy_monitor = rt_thread_create("PHY Monitor", phy_monitor_thread_entry, &phy_monitor_handle, 4096, RT_THREAD_PRIORITY_MAX - 2, 2); + + if (thread_phy_monitor != RT_NULL) { + rt_thread_startup(thread_phy_monitor); + } else { + err = -RT_ERROR; + } + + return err; +} +INIT_PREV_EXPORT(phy_device_register); +#endif /* RT_USING_PHY */ diff --git a/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h new file mode 100644 index 00000000000..d7d36041050 --- /dev/null +++ b/bsp/hpmicro/libraries/drivers/drv_tsw_phy.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2025 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef DRV_TSW_PHY_H +#define DRV_TSW_PHY_H + +#include "hpm_ioc_regs.h" +#include + +#if defined(BSP_USING_TSW_PHY_RTL8211) +#include "hpm_rtl8211.h" +#endif + +#ifndef PHY_MDIO_CLK_FREQ +#define PHY_MDIO_CLK_FREQ (2500000U) +#endif + +#ifndef PHY_MDIO_CSR_CLK_FREQ +#define PHY_MDIO_CSR_CLK_FREQ (100000000U) +#endif + +enum phy_link_status { + PHY_LINK_DOWN = 0U, + PHY_LINK_UP +}; + +typedef struct { + rt_uint32_t phy_speed; + rt_uint32_t phy_duplex; +} phy_info_t; + +typedef struct { + rt_uint32_t phy_link; + rt_phy_t phy; + phy_info_t phy_info; +} phy_device_t; + +#endif /* DRV_TSW_PHY_H */ + + + + diff --git a/bsp/hpmicro/libraries/drivers/drv_uart.c b/bsp/hpmicro/libraries/drivers/drv_uart.c index 6e57d117783..991fa6142ea 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart.c @@ -15,7 +15,7 @@ #include "drv_uart.h" #include "hpm_uart_drv.h" #include "hpm_sysctl_drv.h" - +#include "hpm_clock_drv.h" #ifdef RT_USING_SERIAL @@ -23,7 +23,9 @@ struct hpm_uart { UART_Type *uart_base; - uint32_t irq_num; + rt_uint32_t irq_num; + rt_uint8_t irq_priority; + clock_name_t clk_name; struct rt_serial_device *serial; char *device_name; }; @@ -39,156 +41,156 @@ static int hpm_uart_getc(struct rt_serial_device *serial); #if defined(BSP_USING_UART0) struct rt_serial_device serial0; +SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) void uart0_isr(void) { hpm_uart_isr(&serial0); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) #endif #if defined(BSP_USING_UART1) struct rt_serial_device serial1; +SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) void uart1_isr(void) { hpm_uart_isr(&serial1); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) #endif #if defined(BSP_USING_UART2) struct rt_serial_device serial2; +SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) void uart2_isr(void) { hpm_uart_isr(&serial2); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) #endif #if defined(BSP_USING_UART3) struct rt_serial_device serial3; +SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) void uart3_isr(void) { hpm_uart_isr(&serial3); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) #endif #if defined(BSP_USING_UART4) struct rt_serial_device serial4; +SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) void uart4_isr(void) { hpm_uart_isr(&serial4); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) #endif #if defined(BSP_USING_UART5) struct rt_serial_device serial5; +SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) void uart5_isr(void) { hpm_uart_isr(&serial5); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) #endif #if defined(BSP_USING_UART6) struct rt_serial_device serial6; +SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) void uart6_isr(void) { hpm_uart_isr(&serial6); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) #endif #if defined(BSP_USING_UART7) struct rt_serial_device serial7; +SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) void uart7_isr(void) { hpm_uart_isr(&serial7); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) #endif #if defined(BSP_USING_UART8) struct rt_serial_device serial8; +SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) void uart8_isr(void) { hpm_uart_isr(&serial8); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) #endif #if defined(BSP_USING_UART9) struct rt_serial_device serial9; +SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) void uart9_isr(void) { hpm_uart_isr(&serial9); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) #endif #if defined(BSP_USING_UART10) struct rt_serial_device serial10; +SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) void uart10_isr(void) { hpm_uart_isr(&serial10); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) #endif #if defined(BSP_USING_UART11) struct rt_serial_device serial11; +SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) void uart11_isr(void) { hpm_uart_isr(&serial11); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) #endif #if defined(BSP_USING_UART12) struct rt_serial_device serial12; +SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) void uart12_isr(void) { hpm_uart_isr(&serial12); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) #endif #if defined(BSP_USING_UART13) struct rt_serial_device serial13; +SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) void uart13_isr(void) { hpm_uart_isr(&serial13); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) #endif #if defined(BSP_USING_UART14) struct rt_serial_device serial14; +SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) void uart14_isr(void) { hpm_uart_isr(&serial14); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) #endif #if defined(BSP_USING_UART15) struct rt_serial_device serial15; +SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) void uart15_isr(void) { hpm_uart_isr(&serial15); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) #endif static const struct hpm_uart uarts[] = { @@ -196,6 +198,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART0, IRQn_UART0, +#if defined(BSP_UART0_IRQ_PRIORITY) + .irq_priority = BSP_UART0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart0, &serial0, "uart0", }, @@ -205,6 +213,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART1, IRQn_UART1, +#if defined(BSP_UART1_IRQ_PRIORITY) + .irq_priority = BSP_UART1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart1, &serial1, "uart1", }, @@ -214,6 +228,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART2, IRQn_UART2, +#if defined(BSP_UART2_IRQ_PRIORITY) + .irq_priority = BSP_UART2_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart2, &serial2, "uart2", }, @@ -223,6 +243,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART3, IRQn_UART3, +#if defined(BSP_UART3_IRQ_PRIORITY) + .irq_priority = BSP_UART3_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart3, &serial3, "uart3", }, @@ -232,6 +258,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART4, IRQn_UART4, +#if defined(BSP_UART4_IRQ_PRIORITY) + .irq_priority = BSP_UART4_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart4, &serial4, "uart4", }, @@ -241,6 +273,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART5, IRQn_UART5, +#if defined(BSP_UART5_IRQ_PRIORITY) + .irq_priority = BSP_UART5_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart5, &serial5, "uart5", }, @@ -250,6 +288,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART6, IRQn_UART6, +#if defined(BSP_UART6_IRQ_PRIORITY) + .irq_priority = BSP_UART6_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart6, &serial6, "uart6", }, @@ -259,6 +303,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART7, IRQn_UART7, +#if defined(BSP_UART7_IRQ_PRIORITY) + .irq_priority = BSP_UART7_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart7, &serial7, "uart7", }, @@ -268,6 +318,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART8, IRQn_UART8, +#if defined(BSP_UART8_IRQ_PRIORITY) + .irq_priority = BSP_UART8_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart8, &serial8, "uart8", }, @@ -277,6 +333,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART9, IRQn_UART9, +#if defined(BSP_UART9_IRQ_PRIORITY) + .irq_priority = BSP_UART9_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart9, &serial9, "uart9", }, @@ -286,6 +348,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART10, IRQn_UART10, +#if defined(BSP_UART10_IRQ_PRIORITY) + .irq_priority = BSP_UART10_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart10, &serial10, "uart10", }, @@ -295,6 +363,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART11, IRQn_UART11, +#if defined(BSP_UART11_IRQ_PRIORITY) + .irq_priority = BSP_UART11_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart11, &serial11, "uart11", }, @@ -304,6 +378,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART12, IRQn_UART12, +#if defined(BSP_UART12_IRQ_PRIORITY) + .irq_priority = BSP_UART12_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart12, &serial12, "uart12", }, @@ -313,6 +393,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART13, IRQn_UART13, +#if defined(BSP_UART13_IRQ_PRIORITY) + .irq_priority = BSP_UART13_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart13, &serial13, "uart13", }, @@ -322,6 +408,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART14, IRQn_UART14, +#if defined(BSP_UART14_IRQ_PRIORITY) + .irq_priority = BSP_UART14_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart14, &serial14, "uart14", }, @@ -331,6 +423,12 @@ static const struct hpm_uart uarts[] = { { HPM_UART15, IRQn_UART15, +#if defined(BSP_UART15_IRQ_PRIORITY) + .irq_priority = BSP_UART15_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart15, &serial15, "uart15", }, @@ -367,15 +465,14 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria init_uart_pins(uart->uart_base); uart_default_config(uart->uart_base, &uart_config); - - uart_config.src_freq_in_hz = board_init_uart_clock(uart->uart_base); + clock_add_to_group(uart->clk_name, BOARD_RUNNING_CORE & 0x1); + uart_config.src_freq_in_hz = clock_get_frequency(uart->clk_name); uart_config.baudrate = cfg->baud_rate; uart_config.num_of_stop_bits = cfg->stop_bits; uart_config.parity = cfg->parity; uart_config.word_length = cfg->data_bits - DATA_BITS_5; - board_init_uart(uart->uart_base); uart_init(uart->uart_base, &uart_config); hpm_uart_control(serial, RT_DEVICE_CTRL_SET_INT, NULL); @@ -398,7 +495,7 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */ uart_enable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); - intc_m_enable_irq_with_priority(uart->irq_num, 1); + intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); break; } diff --git a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c index 70a4203b5ed..279236978a9 100644 --- a/bsp/hpmicro/libraries/drivers/drv_uart_v2.c +++ b/bsp/hpmicro/libraries/drivers/drv_uart_v2.c @@ -22,6 +22,7 @@ #include "hpm_dma_mgr.h" #include "hpm_soc.h" +#include "hpm_clock_drv.h" #ifdef RT_USING_SERIAL_V2 @@ -47,7 +48,9 @@ static void hpm_uart_receive_dma_next(struct rt_serial_device *serial); struct hpm_uart { UART_Type *uart_base; - uint32_t irq_num; + rt_uint32_t irq_num; + rt_uint8_t irq_priority; + clock_name_t clk_name; struct rt_serial_device *serial; char *device_name; #ifdef RT_SERIAL_USING_DMA @@ -99,156 +102,156 @@ int hpm_uart_dma_register_channel(struct rt_serial_device *serial, #if defined(BSP_USING_UART0) struct rt_serial_device serial0; +SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) void uart0_isr(void) { hpm_uart_isr(&serial0); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART0,uart0_isr) #endif #if defined(BSP_USING_UART1) struct rt_serial_device serial1; +SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) void uart1_isr(void) { hpm_uart_isr(&serial1); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART1,uart1_isr) #endif #if defined(BSP_USING_UART2) struct rt_serial_device serial2; +SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) void uart2_isr(void) { hpm_uart_isr(&serial2); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART2,uart2_isr) #endif #if defined(BSP_USING_UART3) struct rt_serial_device serial3; +SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) void uart3_isr(void) { hpm_uart_isr(&serial3); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART3,uart3_isr) #endif #if defined(BSP_USING_UART4) struct rt_serial_device serial4; +SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) void uart4_isr(void) { hpm_uart_isr(&serial4); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART4,uart4_isr) #endif #if defined(BSP_USING_UART5) struct rt_serial_device serial5; +SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) void uart5_isr(void) { hpm_uart_isr(&serial5); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART5,uart5_isr) #endif #if defined(BSP_USING_UART6) struct rt_serial_device serial6; +SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) void uart6_isr(void) { hpm_uart_isr(&serial6); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART6,uart6_isr) #endif #if defined(BSP_USING_UART7) struct rt_serial_device serial7; +SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) void uart7_isr(void) { hpm_uart_isr(&serial7); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART7,uart7_isr) #endif #if defined(BSP_USING_UART8) struct rt_serial_device serial8; +SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) void uart8_isr(void) { hpm_uart_isr(&serial8); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART8,uart8_isr) #endif #if defined(BSP_USING_UART9) struct rt_serial_device serial9; +SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) void uart9_isr(void) { hpm_uart_isr(&serial9); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART9,uart9_isr) #endif #if defined(BSP_USING_UART10) struct rt_serial_device serial10; +SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) void uart10_isr(void) { hpm_uart_isr(&serial10); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART10,uart10_isr) #endif #if defined(BSP_USING_UART11) struct rt_serial_device serial11; +SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) void uart11_isr(void) { hpm_uart_isr(&serial11); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART11,uart11_isr) #endif #if defined(BSP_USING_UART12) struct rt_serial_device serial12; +SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) void uart12_isr(void) { hpm_uart_isr(&serial12); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART12,uart12_isr) #endif #if defined(BSP_USING_UART13) struct rt_serial_device serial13; +SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) void uart13_isr(void) { hpm_uart_isr(&serial13); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART13,uart13_isr) #endif #if defined(BSP_USING_UART14) struct rt_serial_device serial14; +SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) void uart14_isr(void) { hpm_uart_isr(&serial14); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART14,uart14_isr) #endif #if defined(BSP_USING_UART15) struct rt_serial_device serial15; +SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) void uart15_isr(void) { hpm_uart_isr(&serial15); } -SDK_DECLARE_EXT_ISR_M(IRQn_UART15,uart15_isr) #endif static struct hpm_uart uarts[] = @@ -257,6 +260,12 @@ static struct hpm_uart uarts[] = { HPM_UART0, IRQn_UART0, +#if defined(BSP_UART0_IRQ_PRIORITY) + .irq_priority = BSP_UART0_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart0, &serial0, "uart0", #ifdef RT_SERIAL_USING_DMA @@ -271,6 +280,12 @@ static struct hpm_uart uarts[] = { HPM_UART1, IRQn_UART1, +#if defined(BSP_UART1_IRQ_PRIORITY) + .irq_priority = BSP_UART1_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart1, &serial1, "uart1", #ifdef RT_SERIAL_USING_DMA @@ -285,6 +300,12 @@ static struct hpm_uart uarts[] = { HPM_UART2, IRQn_UART2, +#if defined(BSP_UART2_IRQ_PRIORITY) + .irq_priority = BSP_UART2_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart2, &serial2, "uart2", #ifdef RT_SERIAL_USING_DMA @@ -299,6 +320,12 @@ static struct hpm_uart uarts[] = { HPM_UART3, IRQn_UART3, +#if defined(BSP_UART3_IRQ_PRIORITY) + .irq_priority = BSP_UART3_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart3, &serial3, "uart3", #ifdef RT_SERIAL_USING_DMA @@ -313,6 +340,12 @@ static struct hpm_uart uarts[] = { HPM_UART4, IRQn_UART4, +#if defined(BSP_UART4_IRQ_PRIORITY) + .irq_priority = BSP_UART4_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart4, &serial4, "uart4", #ifdef RT_SERIAL_USING_DMA @@ -327,6 +360,12 @@ static struct hpm_uart uarts[] = { HPM_UART5, IRQn_UART5, +#if defined(BSP_UART5_IRQ_PRIORITY) + .irq_priority = BSP_UART5_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart5, &serial5, "uart5", #ifdef RT_SERIAL_USING_DMA @@ -341,6 +380,12 @@ static struct hpm_uart uarts[] = { HPM_UART6, IRQn_UART6, +#if defined(BSP_UART6_IRQ_PRIORITY) + .irq_priority = BSP_UART6_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart6, &serial6, "uart6", #ifdef RT_SERIAL_USING_DMA @@ -355,6 +400,12 @@ static struct hpm_uart uarts[] = { HPM_UART7, IRQn_UART7, +#if defined(BSP_UART7_IRQ_PRIORITY) + .irq_priority = BSP_UART7_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart7, &serial7, "uart7", #ifdef RT_SERIAL_USING_DMA @@ -369,6 +420,12 @@ static struct hpm_uart uarts[] = { HPM_UART8, IRQn_UART8, +#if defined(BSP_UART8_IRQ_PRIORITY) + .irq_priority = BSP_UART8_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart8, &serial8, "uart8", #ifdef RT_SERIAL_USING_DMA @@ -383,6 +440,12 @@ static struct hpm_uart uarts[] = { HPM_UART9, IRQn_UART9, +#if defined(BSP_UART9_IRQ_PRIORITY) + .irq_priority = BSP_UART9_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart9, &serial9, "uart9", #ifdef RT_SERIAL_USING_DMA @@ -397,6 +460,12 @@ static struct hpm_uart uarts[] = { HPM_UART10, IRQn_UART10, +#if defined(BSP_UART10_IRQ_PRIORITY) + .irq_priority = BSP_UART10_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart10, &serial10, "uart10", #ifdef RT_SERIAL_USING_DMA @@ -411,6 +480,12 @@ static struct hpm_uart uarts[] = { HPM_UART11, IRQn_UART11, +#if defined(BSP_UART11_IRQ_PRIORITY) + .irq_priority = BSP_UART11_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart11, &serial11, "uart11", #ifdef RT_SERIAL_USING_DMA @@ -425,6 +500,12 @@ static struct hpm_uart uarts[] = { HPM_UART12, IRQn_UART12, +#if defined(BSP_UART12_IRQ_PRIORITY) + .irq_priority = BSP_UART12_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart12, &serial12, "uart12", #ifdef RT_SERIAL_USING_DMA @@ -439,6 +520,12 @@ static struct hpm_uart uarts[] = { HPM_UART13, IRQn_UART13, +#if defined(BSP_UART13_IRQ_PRIORITY) + .irq_priority = BSP_UART13_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart13, &serial13, "uart13", #ifdef RT_SERIAL_USING_DMA @@ -453,6 +540,12 @@ static struct hpm_uart uarts[] = { HPM_UART14, IRQn_UART14, +#if defined(BSP_UART14_IRQ_PRIORITY) + .irq_priority = BSP_UART14_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart14, &serial14, "uart14", #ifdef RT_SERIAL_USING_DMA @@ -467,6 +560,12 @@ static struct hpm_uart uarts[] = { HPM_UART15, IRQn_UART15, +#if defined(BSP_UART15_IRQ_PRIORITY) + .irq_priority = BSP_UART15_IRQ_PRIORITY, +#else + .irq_priority = 1, +#endif + clock_uart15, &serial15, "uart15", #ifdef RT_SERIAL_USING_DMA @@ -644,8 +743,8 @@ static void hpm_uart_isr(struct rt_serial_device *serial) if (irq_id == uart_intr_id_rx_data_avail) { while (uart_check_status(uart->uart_base, uart_stat_data_ready)) { count++; - char chr = uart_read_byte(uart->uart_base); - rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr); + put_char = uart_read_byte(uart->uart_base); + rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); /*in order to ensure rx fifo there are remaining bytes*/ if (count > 12) { break; @@ -655,8 +754,8 @@ static void hpm_uart_isr(struct rt_serial_device *serial) if (irq_id == uart_intr_id_rx_timeout) { while ((uart_check_status(uart->uart_base, uart_stat_data_ready)) || (uart_check_status(uart->uart_base, uart_stat_overrun_error))) { - char chr = uart_read_byte(uart->uart_base); - rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr); + put_char= uart_read_byte(uart->uart_base); + rt_ringbuffer_putchar(&(rx_fifo->rb), put_char); } rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } @@ -684,7 +783,10 @@ static void hpm_uart_isr(struct rt_serial_device *serial) } #if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) && defined(RT_SERIAL_USING_DMA) if (uart_is_rxline_idle(uart->uart_base)) { - uart_rx_done(serial); + if ((uart->rx_chn_ctx.resource.base != RT_NULL) && (dma_get_remaining_transfer_size(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel) > 0)) { + /* if the rxline is idle, but the dma transfer is not finished, it means that the rxline idle interrupt is triggered before the dma transfer is finished */ + uart_rx_done(serial); + } uart_clear_rxline_idle_flag(uart->uart_base); uart_flush(uart->uart_base); } @@ -703,8 +805,8 @@ static rt_err_t hpm_uart_configure(struct rt_serial_device *serial, struct seria init_uart_pins(uart->uart_base); uart_default_config(uart->uart_base, &uart_config); - - uart_config.src_freq_in_hz = board_init_uart_clock(uart->uart_base); + clock_add_to_group(uart->clk_name, BOARD_RUNNING_CORE & 0x1); + uart_config.src_freq_in_hz = clock_get_frequency(uart->clk_name); uart_config.baudrate = cfg->baud_rate; uart_config.num_of_stop_bits = cfg->stop_bits; uart_config.parity = cfg->parity; @@ -804,10 +906,9 @@ static int hpm_uart_dma_config(struct rt_serial_device *serial, void *arg) dma_mgr_enable_channel(&uart->rx_chn_ctx.resource); dma_mgr_enable_chn_irq(&uart->rx_chn_ctx.resource, DMA_MGR_INTERRUPT_MASK_TC); dma_mgr_enable_dma_irq_with_priority(&uart->rx_chn_ctx.resource, 1); -#if !defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) || (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 0) hpm_uart_dma_register_channel(serial, false, uart_rx_done, RT_NULL, RT_NULL); -#else - intc_m_enable_irq_with_priority(uart->irq_num, 1); +#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) + intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); #endif } else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) { chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; @@ -928,11 +1029,11 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void if (ctrl_arg == RT_DEVICE_FLAG_INT_RX) { /* enable rx irq */ uart_enable_irq(uart->uart_base, uart_intr_rx_data_avail_or_timeout); - intc_m_enable_irq_with_priority(uart->irq_num, 2); + intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); } else if (ctrl_arg == RT_DEVICE_FLAG_INT_TX) { /* enable tx irq */ uart_enable_irq(uart->uart_base, uart_intr_tx_slot_avail); - intc_m_enable_irq_with_priority(uart->irq_num, 1); + intc_m_enable_irq_with_priority(uart->irq_num, uart->irq_priority); } break; diff --git a/bsp/hpmicro/libraries/drivers/drv_wdt.c b/bsp/hpmicro/libraries/drivers/drv_wdt.c index d594dbc4493..ae1bae48e1f 100644 --- a/bsp/hpmicro/libraries/drivers/drv_wdt.c +++ b/bsp/hpmicro/libraries/drivers/drv_wdt.c @@ -25,6 +25,7 @@ typedef struct hpm_wdog clock_name_t clock_name; uint32_t irq_num; rt_watchdog_t *wdog; + wdg_control_t wdog_ctrl; }hpm_wdog_t; static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt); @@ -35,49 +36,40 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args); static void hpm_wdog_isr(rt_watchdog_t *wdt); -static wdg_control_t wdog_ctrl = { - .reset_interval = reset_interval_clock_period_mult_16k, - .interrupt_interval = interrupt_interval_clock_period_multi_8k, - .reset_enable = true, - .interrupt_enable = false, - .clksrc = wdg_clksrc_extclk, - .wdg_enable = false, -}; - #if defined(BSP_USING_WDG0) rt_watchdog_t wdog0; +SDK_DECLARE_EXT_ISR_M(IRQn_WDG0, wdog0_isr) void wdog0_isr(void) { hpm_wdog_isr(&wdog0); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDG0, wdog0_isr) #endif #if defined(BSP_USING_WDG1) rt_watchdog_t wdog1; +SDK_DECLARE_EXT_ISR_M(IRQn_WDG1, wdog1_isr) void wdog1_isr(void) { hpm_wdog_isr(&wdog1); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDG1, wdog1_isr) #endif #if defined(BSP_USING_WDG2) rt_watchdog_t wdog2; +SDK_DECLARE_EXT_ISR_M(IRQn_WDG2, wdog2_isr) void wdog2_isr(void) { hpm_wdog_isr(&wdog2); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDG2, wdog2_isr) #endif #if defined(BSP_USING_WDG3) rt_watchdog_t wdog3; +SDK_DECLARE_EXT_ISR_M(IRQn_WDG3, wdog3_isr) void wdog3_isr(void) { hpm_wdog_isr(&wdog3); } -SDK_DECLARE_EXT_ISR_M(IRQn_WDG3, wdog3_isr) #endif static hpm_wdog_t wdogs[] = { @@ -88,6 +80,14 @@ static hpm_wdog_t wdogs[] = { .clock_name = clock_watchdog0, .irq_num = IRQn_WDG0, .wdog = &wdog0, + .wdog_ctrl = { + .reset_interval = reset_interval_clock_period_mult_16k, + .interrupt_interval = interrupt_interval_clock_period_multi_8k, + .reset_enable = true, + .interrupt_enable = false, + .clksrc = wdg_clksrc_extclk, + .wdg_enable = false, + }, }, #endif @@ -98,6 +98,14 @@ static hpm_wdog_t wdogs[] = { .clock_name = clock_watchdog1, .irq_num = IRQn_WDG1, .wdog = &wdog1, + .wdog_ctrl = { + .reset_interval = reset_interval_clock_period_mult_16k, + .interrupt_interval = interrupt_interval_clock_period_multi_8k, + .reset_enable = true, + .interrupt_enable = false, + .clksrc = wdg_clksrc_extclk, + .wdg_enable = false, + }, }, #endif @@ -108,16 +116,32 @@ static hpm_wdog_t wdogs[] = { .clock_name = clock_watchdog2, .irq_num = IRQn_WDG2, .wdog = &wdog2, + .wdog_ctrl = { + .reset_interval = reset_interval_clock_period_mult_16k, + .interrupt_interval = interrupt_interval_clock_period_multi_8k, + .reset_enable = true, + .interrupt_enable = false, + .clksrc = wdg_clksrc_extclk, + .wdg_enable = false, + }, }, #endif #ifdef BSP_USING_WDG3 { - .wdog_name = HPM_WDG3, + .wdog_base = HPM_WDG3, .device_name = "wdt3", .clock_name = clock_watchdog3, .irq_num = IRQn_WDG3, .wdog = &wdog3, + .wdog_ctrl = { + .reset_interval = reset_interval_clock_period_mult_16k, + .interrupt_interval = interrupt_interval_clock_period_multi_8k, + .reset_enable = true, + .interrupt_enable = false, + .clksrc = wdg_clksrc_extclk, + .wdg_enable = false, + }, }, #endif }; @@ -132,7 +156,9 @@ static rt_err_t hpm_wdog_init(rt_watchdog_t *wdt) hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; - wdg_init(base, &wdog_ctrl); + clock_add_to_group(hpm_wdog->clock_name, BOARD_RUNNING_CORE & 0x1); + + wdg_init(base, &hpm_wdog->wdog_ctrl); return RT_EOK; } @@ -145,6 +171,7 @@ static rt_err_t hpm_wdog_open(rt_watchdog_t *wdt, rt_uint16_t oflag) rt_enter_critical(); wdg_enable(base); rt_exit_critical(); + return RT_EOK; } static rt_err_t hpm_wdog_close(rt_watchdog_t *wdt) @@ -177,6 +204,7 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) hpm_wdog_t *hpm_wdog = (hpm_wdog_t*)wdt->parent.user_data; WDG_Type *base = hpm_wdog->wdog_base; + wdg_control_t *wdog_ctrl = &hpm_wdog->wdog_ctrl; uint32_t temp; switch (cmd) @@ -190,12 +218,12 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) RT_ASSERT(*(uint32_t *)args != 0); temp = *(uint32_t *)args; temp *= 1000000U; /* Convert to microseconds */ - wdog_ctrl.interrupt_interval = wdg_convert_interrupt_interval_from_us(WDG_EXT_CLK_FREQ, temp); - wdog_ctrl.reset_interval = reset_interval_clock_period_mult_128; - wdog_ctrl.reset_enable = true; - wdog_ctrl.interrupt_enable = true; - wdog_ctrl.clksrc = wdg_clksrc_extclk; - wdog_ctrl.wdg_enable = false; + wdog_ctrl->interrupt_interval = wdg_convert_interrupt_interval_from_us(WDG_EXT_CLK_FREQ, temp); + wdog_ctrl->reset_interval = reset_interval_clock_period_mult_128; /* Intentionally hard-coded */ + wdog_ctrl->reset_enable = true; + wdog_ctrl->interrupt_enable = true; + wdog_ctrl->clksrc = wdg_clksrc_extclk; + wdog_ctrl->wdg_enable = false; hpm_wdog_init(wdt); break; case RT_DEVICE_CTRL_WDT_KEEPALIVE: @@ -212,7 +240,7 @@ static rt_err_t hpm_wdog_control(rt_watchdog_t *wdt, int cmd, void *args) break; } - return RT_EOK; + return ret; } void hpm_wdog_isr(rt_watchdog_t *wdt) @@ -235,7 +263,7 @@ int rt_hw_wdt_init(void) for (uint32_t i = 0; i < sizeof(wdogs) / sizeof(wdogs[0]); i++) { wdogs[i].wdog->ops = &hpm_wdog_ops; - clock_add_to_group(wdogs[i].clock_name, 0); + clock_add_to_group(wdogs[i].clock_name, BOARD_RUNNING_CORE & 0x1); err = rt_hw_watchdog_register(wdogs[i].wdog, wdogs[i].device_name, RT_DEVICE_FLAG_RDWR, (void *)&wdogs[i]); if (err != RT_EOK) { diff --git a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md b/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md deleted file mode 100644 index 51d831255fc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md +++ /dev/null @@ -1,1519 +0,0 @@ -# Change Log - -## [1.6.0] - 2024-06-28: - -Main changes since 1.5.0 -Tested Segger Embedded Studio Version: 8.10d -Tested IAR Embedded Workbench for RISC-V Version: 3.30.1 - -### Known Issue: - - some IAR projects does not work properly when optimization level is increased - -### Changed: - - soc: reorganize the directory structure - - soc: hpm6750: declare get_frequency_for_source API for clock drver header file - - soc: update soc cmakelists to add b ext info - - soc: hpm6750: add feature for ioc pad ctrl setting issue - - soc: toolchains: gcc: correct LMA for NOLOAD sections - - soc: move eh_frame into separate section - - boards: hpm6750xxxx apply workaround for E00029. - - boards: change hpm5301evklite adc16 channel - - boards: board.h: adc16: add marco BOARD_APP_ADC16_HW_TRIG_SRC_CLK_NAME - - boards: adjust function position of adc pin initialization - - boards: hpm6300evk and hpm6e00evk: sdram use px07 as femc dqs pin - - boards: hpm6e00evk: rename init_sdram_pins to init_femc_pins - - boards: hpm6e00evk: change board i2c instance to I2C0 - - drivers: can/mcan add parameter check for low-level bit timing. - - drivers: enet: add bitfield ENET0_RMII_TXCLK_SEL for hpm6300 - - drivers: i2c: add DATACNT high byte process - - drivers: pwm: update HRPWM process - - drivers: spi: optimize reading speed for spi_read_data API - - drivers: spi: add set/get data phase format APIs for spi master - - drivers: spi: delete the spi startand operation APIs - - drivers: adc16: remove an unused member conv_duration from adc16_config_t - - drivers: enet: update for enet_interrupt_enable_t - - drivers: mcan reduce unnecessary register access in mcan_read_rxfifo. - - drivers: mtg: add calculate function param clock - - drivers: mtg: add several calculate functions - - drivers: mcan lookeup the mcan msg ram base via mcan_soc_msg_buf variable if the MSG_BUF is in AHB RAM. - - drivers: adc16: disable improvement logic of adc16 for continuous sampling maximum voltage - - drivers: mcan improve transmitter delay compensation setting logic. - - drivers: femc: rename data_width_in_byte to cmd_data_width - - drivers: femc: update ns2cycle() to align up - - drivers: common: add packed attribute - - drivers: femc: delete duplicate config - - drivers: mtg: change the default parameters to the low order filter - - drivers: adc16: add API adc16_set_seq_hw_trigger_enable() - - drivers: spi : convert enumeration return in that gets parameters APIs - - drivers: pwm: add fault recovery code. - - driver: pwm: change pwm trig time - - components: enet_phy: dp83867/rtl8211: move the macro definition RGMII to board-level CMakeLists.txt - - components: eeprom_emulation: Add ATTR_RAMFUNC for all function - - components: eeprom_emulation: add power-off protection mechanism. - - components: dma_mgr: add burst in fixed transfer size and swap feature - - components: spi: add full_duplex and half_duplex operating APIs - - components: spi: support 1 to 32 bits width transfer for nonblocking APIs - - components: usb: device: support iso transfer mult feature - - middleware: hpm_sdmmc add emmc sleep & wakeup function. - - middleware: tinyusb: ehci: support chain transfer - - middleware: threadx: add low power support - - middleware: cherryusb: update for advance descriptor - - middleware: hpm_sdmmc: optimized to support multiple cards - - middleware: cherryusb/tinyusb/usbx: enable suspend isr - - middleware: FreeRTOS: update to 202210.01 lts - - middleware: cherryusb: update to v1.3.0 - - middleware: freertos: modify missed timer count num - - middleware: freertos: update IAR port file - - middleware: freertos: delete fence operations - - middleware: freertos: make the calculation more simple. - - middleware: hpm_sdmmc add cache control macro. - - middleware: hpm_sdmmc: improve the logic for detecting CMD23 support. - - middleware: freertos: add tickless stop mode support - - middleware: freertos: add user custom process function call - - middleware: hpm_mcl_v2: add hpm smc control. - - middleware: freertos: place xPortxxx to isr_vector section - - middleware: hpm_math: add dsp support for zcc - - middleware: microros: add zcc support - - middleware: rtos: asm adjustment for zcc toolchain - - middleware: hpm_mcl_v2: add pwm dead area compensation. - - middleware: hpm_mcl_v2: add dq axis decoupling function - - middleware: cherryusb: add macro USBH_USE_CUSTOM_ISR/USBD_USE_CUSTOM_ISR - - middleware: lvgl: upgrade to v9 - - middleware: lvgl: rewrite the scissor. - - middleware: lvgl: upgrade allocate algorithm for draw_buf. - - samples: rdc: remove unused dac driver in sample - - samples: lwip/netxduo/modbus: add conditional compile for reference clock setting in RMII mode - - samples: audio_codec: common: change FIL_SEARCH_NUM from 10 to 20 - - samples: dhyrstone: surpress build warnings - - samples: dhrystone Optimize performance. - - samples: coremark Optimize performance. - - samples: drivers: spi: interrupt: transmission optimization. The transmission will start after the configuration is completed. - - samples: adapt spi components to drive and move to the samples dir for spi sdcard samples - - samples: cherryusb: device: change descriptor string to HPMicro - - samples: cherryusb: device: use advanced descriptor to support high/full speed - - samples: rename jpeg to image - - samples: drivers: sdxc: sd_fatfs: add card hotplug support - - samples: cherryusb: host: usbnet: replace block to noblock for read terminal char - - samples: cherryusb: host: usbnet: decrease lwip MEM_SIZE - - samples: cherryusb: move host hid info print code to thread - - samples: audio_codec: refactoring code - - samples: spi: dma: SPI master transmission optimization - - samples: mtg: make the open_loop_trajectory sample more readable - - samples: drivers: adc16: add some misc optimization - - samples: drivers: adc16: add pwmv2 support - - samples: motor_ctrl: bldc_foc_hw: remove hardware control - - samples: drivers: mcan add tips for the usage of tdc. - - samples: vglite: update rtos config file to fit gptmr tickless mode - - samples: lwip/modus/netxduo: add a function call to get the enet default interrupt config - - samples: sdm: using pwm to provide clock for sdm sensor. - - samples: spi_components: half_duplex: updated to support 1 to 32bits width transfer - - samples: spi_components: full_duplex: updated to support 1 to 32bits width transfer - - samples: add freertos tickless stop mode sample - - samples: benchmark: update compile options for zcc - - samples: drivers: adc16: optimize the process logic of sequence and preemption - - samples: drivers: sei: device: tamagawa: update eeprom cmd - - samples: adc12: optimization for trigger mux and trigger frequency settings - - samples: sei: device: tamagawa: support EEPROM protocol - - samples: mcl: add pwm dead area compensation. - - samples: motor_ctrl: add dq axis decoupling function - - samples: cherryusb: move dual_port samples to dual_port folder - - samples: cherryusb: adapter to cherryusb v1.3.0 - - samples: drivers: adc12/adc16/dac: support abort feature in interactive terminal - - samples: lwip: lwip_iperf: support abort feature to reselect the test mode - - samples: lwip: common: multiple: add definitions of remote ip addresses for iperf - - samples: motor_ctrl: bldc_lvlg_foc: add lvgl v8.3.5 for this demo - - samples: tinyusb: uac2: support full speed - - samples: power_mode_switch: update readme - - samples: cherryusb: uac2: change default samplerate order - - samples: bldc_foc: update bldc_foc_angle_align() for hardware loop - - cmake: toolchain: add ar option to remove timestamp - - cmake: toolchain: suppress output while querying spec - - cmake: lld: update link option for zcc - - cmake/scripts/soc: support b ext convertion to tools - - cmake: sdk_app_src_glob: modify to recursive - -### Fixed: - - soc: update USE_NONVECTOR_MODE defined used - - soc: initialize .fast_ram.* section - - soc: iar linker: fix safe stack init - - soc: add missing ptmr clock - - soc: hpm6880: fix get_frequency_for_i2s error - - soc: hpm6880: Modify the value of SPI_SOC_FIFO_DEPTH from 4 to 8. for hpm_soc_feature.h - - soc: toolchain: iar fix iar ram_stress issue in ram_debug build. - - boards: hpm5301evklite: fixed can't output work for gptmr samples such as pwm_generate - - drivers: enet: fix the clearing of DMA PBL setting - - drivers: dma: fix dma_clear_transfer_status() API - - drivers: sdxc Fix timeout calculation issue and DMA enabling logic. - - drivers: adc16: fix the logic of adc16_set_pmt_queue_enable() when the parameter enable is false - - drivers: mbox: fix error that BEIE can't be operated by interface - - drivers: spi: fixed assignment value error for spi_set_clock_phase and spi_set_clock_polarity APIs - - drivers: lcdc: fix ST and DMA_ST clear api. - - drivers: mipi_dsi: fix MIPI_DSI_FMT_RGB565 config. - - drivers: spi: fixed assignment error issue for enable/disable address phase APIs - - drivers: i2c: fix return value type of i2c_get_data_count() - - components: usb device/enet_phy: fix unwanted files in localize folder - - components: panle: fix panel timing. - - components: eeprom_emulation: demo flash crashed. - - middleware: cherryusb: ehci: delete timeout clear before give sem - - middleware: uC/OS-III: modify fpu context save&restore - - middleware: cherryusb: fix freertos enter/exit critical - - middleware: audio_codec: fix hpm_wav_decode() single channel pbuf data - - middleware: mclv2: fix andes toolchain compiler error. - - middleware: cherryusb: fix ehci_qh_pool init miss busid for v1.3.0 - - middleware: lwip: apps: lwiperf: fix the bug of failing to restart iperf in TCP/UDP server mode - - middleware: tinyusb: fix _usbd_dev.speed error to support full speed - - middleware: hpm_mcl_v2: fix uncontrolled after large changes in motor speed. - - samples: dhyrstone: fix build issue for release type using nds toolchain - - samples: lwip: lwip_tcpclient: fix TCP commnuication error after DHCP enabled - - samples: lwip: lwip_tcpclient_freertos_socket: fix connection error before IP assigned from DHCP - - samples: correct cmsis_os2/mem_pool project name - - samples: multicore: common Fix SDP memcpy blocking issue in ram_build. - - samples: lwip: lwip_tcpecho_xxx_rtthread_nano: fix failing to get IP by DHCP serivice - - samples: spi_sdcard: fixed the place section name error issue - - samples: cherryusb: audio: fix wm8960 codec volume max value - - samples: img: jpeg_decode: fix decode when only one qtab exist. - - samples: tflm: mlperf: remove unnecessary codes. - - samples: fix cherryusb mic no sound error - - samples: spi_components: polling: fixed doesn't work for polling samples - - samples: tamagawa: fix delay times is zero. - - samples: bldc_foc: fix hardware_foc position loop error - - cmake: link ndsgcc itf for application - - cmake: localize_sdk: use utf-8 as default encoding - - cmake: ide: keep preprocessing definition - -### Added: - - soc: add zcc toolchain support - - soc: clock_driver Add clock_set_wdg_source API. - - soc: gcc linker: add fast_ram.init section size overflow check - - soc: add FreeRTOS vector mode support - - soc/board: add HPM6E80 support - - drivers: common: add macros for .fast_ram.* - - drivers: enet: add an API enet_get_default_interrupt_config - - drivers: enet: add MII mode support - - drivers: common add api for converting tick to us or ms. - - drivers: pllctlv2 add new API to configure PLL. - - drivers: uart: add uart_modem_write_rts_pin API - - drivers: uart: add get/clear addr match flags APIs such as addr_match, addr_match_idle, data_lost - - drivers: add lobs drivers - - drivers: usb: add some APIs for low power future usage drivers: spi: add spi_slave_set_user_status API - - drivers: usb: add suspend/resume APIs - - drivers: usb: add enter/exit lower power suspend APIs - - drivers: spi: add read SPI RX/TX FIFO size APIs - - drivers: usb: add usb_set_port_test_mode() API - - drivers: sdp add new apis. - - drivers: mcan add new api for canceling pending transmission. - - drivers: mtg: add get&clear event irq interface - - drivers: qeiv2: add oneshot mode - - drivers: add clc driver - - drivers: add vsc driver - - drivers: spi: add get/set shift direction APIs - - drivers: uart: add an new API uart_try_receive_byte() - - drivers: pixelmux: add api that set mipi dsi date type. - - drivers: gptmr: add monitor function APIs - - drivers: gptmr: add opmode APIs - - drivers: gptmr: add qeimode APIs - - components: add i2s_over_spi - - components: codec: add wm8978 - - components: enet_phy: add jl1111 driver - - components: add ppi components - - components: touch: add gt9271 driver. - - components: debug_console: add a new API console_try_receive_byte() - - middleware: add lodepng - - middleware: add minimp3 - - samples: cherryusb: device: add WinUSB 1.0 and WinUSB 2.0 samples - - samples: lwip: add LPI interrupt mask setting - - samples: add i2s_emulation sample - - samples: lvgl_audio_player: support mp3 decoder - - samples: uart: add uart_rx_line_status sample - - samples: add half_duplex samples for spi_components - - samples: add full_duplex samples for spi_components - - samples: drivers: sdxc: emmc add new sameple for eMMC sleep & awake. - - samples: drivers: add lobs sample - - samples: drivers: spi: sd/sd_fatfs: support DMA transfer - - samples: threadx: add low power mode sample - - samples: image: add png encoder sample - - samples: image: add png decoder sample - - samples: audio_codec: add decoder_mp3 sample - - samples: ppi: add parallel adc sample - - samples: ppi: add async_sram sample - - samples: qeov2: add wave_out sample - - samples: qeov2: add abz_out sample - - samples: pwm: add async fault demo - - samples: motor_ctrl: add hardware foc - - samples: drivers: pwmv2: add pwmv2 pair waveform - - samples: dmav2: add dmav2_fixed_burst_swap sample - - samples: qeiv2: add oneshot mode sample - - samples: add smix_dao sample. - - samples: add ecat_io sample. - - samples: cherryusb: add one host and one device dual port sample - - samples: add pwm/hrpwm fault mode - - samples: lwip: add lwip_iperf_multi_ports - - samples: drivers: tsw: add a tsn_switch sample - - cmake: add symbol HPM_BUILD_TYPE to specify build type - - docs: add generated cmake_intro.rst - - docs: getting started: add zcc support related information - -## [1.5.0] - 2024-03-29: - -Main changes since 1.4.0 - -Tested Segger Embedded Studio Version: 7.32a -Tested IAR Embedded Workbench for RISC-V Version: 3.20.1 - -### Known Issue: - - some IAR projects does not work properly when optimization level is increased - -### Changed: - - soc: iomux: update macro prefix in pmic_iomux and batt_iomux. - - soc: feature: change usb endpoint max number from 8 to 16 - - soc: correct svd files and add subpart module list - - drivers: usb: change usb_phy_get_line_state() to external function - - drivers: qeiv2: update filter length setting - - drivers: adc12/adc16: add sanity check for sample cycle - - drivers: femc: add delay_cell_disable config option - - drivers: i2s: change fifo threshold parameter. - - drivers: i2c: replace and use the macro definition of hpm_soc_ip_feature. - - drivers: uart: supplementary description of uart_check_status API. - - components: enet_phy: lan8720/rtl8201/rtl8211: unify the default config with type bool - - components: enet_phy: remove unused included header file - - components: enet_phy: rtl8201/rtl8211: update register description - - components: dma_mgr: change isr handler from static to public - - middleware: tinyusb: host: use echi drivers - - middleware: tinyusb: rename CFG_TUSB_HOST_DEVICE_MAX to CFG_TUH_DEVICE_MAX - - middleware: tinyusb: update to v0.16 - - middleware: rtthread-nano: use soc reset_handler and define MAIN_ENTRY as entry - - middleware: fatfs: tinyusb: adapter to tinyusb update - - middleware: threadx: use TX_TIMER_TICKS_PER_SECOND to config work ticks - - middleware: threadx: use samples tx_user.h - - middleware: uC/OS-III: enable sw interrupt in OSCtxSw/OSIntCtxSw - - middleware: ucos: ports: Added IAR portable layer for ucos. - - middleware: cherryusb/azure_rtos: add defined __ICCRISCV__ for iar - - middleware: hpm_math: simplify libdsp path. - - middleware: cherryusb: update to v1.1.0 - - middleware: rtthread-nano:halt cpu when exception occur. - - middleware: hpm_math: simplify libnn path. - - middleware: threadx: move frequently called function to ram. - - middleware: tinyusb: change endpoint number from 8 to 16 - - middleware: usbx: change endpoint number from 8 to 16 - - middleware: cherryusb: msc device: update to support multi lun and deinit - - middleware: eclipse_threadx: update license - - middleware: fatfs: tinyusb: add osal_task_delay() when use rtos wait - - middleware: tinyusb: update CMakeLists.txt and delete custom osal_task_delay() - - middleware: tinyusb: add debounce in port change isr - - samples: erpc: add middleware src use middleware CMakeLists.txt - - samples: multicore: core1: use board_init_core1() API - - samples: multicore: coremark: delete custom reset_handler and use app_main as MAIN_ENTRY - - samples: tinyusb: update samples to adapter tinyusb v0.16 - - samples: usbx: host: delete unused hpm_usb_host.h - - samples: usb: delete CONFIG_USB_HOST set - - samples: lvgl_coremark: disable freqswitch_btn when coremark running - - samples: mono: move to driver directory. - - samples: freertos: change configMAX_PRIORITIES from 7 to 32 - - samples: rtthread: delete unused macro RT_THREAD_PRIORITY_32 - - samples: cherryusb: usbnet: decrease rtos stack config size - - samples: lwip: all: unify logs about IP information - - samples: lwip: lwip_https_server: remove an unused file - - samples: lwip: all: update DHCP progress logic - - samples: lwip: common: remove s_pxNetIf - - samples: lwip: adjust the directories of netconf.c/netcof.h - - samples: lwip: common: optimize speed for getting IP from DHCP server - - samples: lwip: rename common_lwip.c to common.c - - samples: lwip: common: adjust the call logic of netif_set_up/netif_set_down - - samples: lwip: common: change the time of invoking netif_user_notification - - samples: lwip: common: rename user_notification to netif_user_notification - - samples: lwip: adjust directory structures to be compatible with single and multiple network ports - - samples: use generate_ide_projects for new samples - - samples: cherryusb: device: cdc acm: reorganize directory structure - - samplse: gptmr: t_shape_accel_decel: modify the source address mode of DMA. - - samples: cherryusb: device: change readbuf size from 2048 to CDC_MAX_MPS - - samples: drivers: femc: update sdram dqs config - - samples: update app.yaml to use ip_feature - - samples: drivers: uart: change to app uart - - samples: audio_codec: update wm8960 I2S protocol. - - samples: drivers: cam: change cam sample to cam_dvp sample. - - samples: usbx: device: msc: decrease ram disk size to 16KB - - samples: cherryusb: msc device: update to support multi lun - - samples: driver: uart_lin: support LIN transceiver on board. - - samples: adc: temp: rename temp to adc16_temperature - - samples: bldc block: Compatible with both hall and qeiv2 peripherals. - - samples: motor_ctrl: Modify the value of pwm reload. - - samples: lwip: common: single/multiple: update the size passed into sys_mbox_new() - - samples: lwip: common: single/multiple: replace enet_get_link_status with netif_is_link_up - - samples: lwip: lwip_https_server: remove unused header file - - samples: lwip: rename macro TCP_XXX_PORT - - samples: lwip: add cmake flag for netconn/socket api - - samples: decode_wav: sd_fafts: update sd_choose_music. - - samples: power_mode_switch: maintain xpi0 clock on switching preset - - samples: dhrystone Change the optmization level to O3. - - samples: tinyusb: hid_generic_inout: delete redundant image - - samples: power_mode_switch: hpm67/hpm63: preserve femc clock at wait/stop mode - - samples: erpc: core1: use optimization -os - - samples: update uart_tamagawa to use software trig if TRGM not exist. - - samples: eeprom_emulation: reduce management area - - samples: sdxc: use block_size instead of 512 - - samples: erpc: add -fno-exceptions compile option - - samples: tinyusb: disable debug log print - - boards: hpm5300evk and hpm6800evk: add delay after USB_PWR Pin init for power stable - - boards: hpm6750evkmini: modify gptmr pins. - - boards: hpm6200evk: modify gptmr pins. - - boards: hpm6200evk: modify the i2c pins. - - boards: hpm6750xxx: update sdram dqs config - - boards: hpm6800evk:pinmux Increase drive strength for sdxc pins - - boards: iomux: update macro prefix for pmic_iomux and batt_iomux. - - boards: rename board feature - - boards: update BOARD_APP_UART definition - - boards: rename console definitions - - boards: hpm5301evklite: update uart clock in board.c. - - boards: hpm6750evkmini: change BOARD_GPTMR_PWM_DMA_SRC definition. - - docs: samples: use glob in high level readme. - - docs: update top level readme. - - docs: netxduo: update sntp readme. - - docs: threadx: update threadx hello readme. - - docs: lwip: align pictures to the left - - docs: pip: add cmake doc dependency - - docs: add changelog to sphnix-doc. - - scripts: ses: generate asm after build by default. - - scripts: update linked project path logic. - - scripts: check_board_cap.py: check ip feature's availability - - cmake: remove CMP0116 setting. - - cmake&scripts: clarify the error caused by core1 compiling failure. - - scripts: ses/iar: use relpath in project file - -### Added: - - soc: hpm6360/hpm6750/hpm6800: add MAC-related definitions in OTP section - - soc: reset: add MAIN_ENTRY macro to custom define main entry - - soc: add hpm6850 and hpm6830 part. - - soc: soc_modules.list: add tamper drivers - - soc: Add IAR toolchain support. - - soc: add ip feature to soc_modules.list - - soc: add hpm_soc_ip_feature.h - - soc: driver: ppor: add reset hold operation APIs - - soc: clock_driver add the clock_get_divider API. - - soc: sysctl: add apis to control clock preservation - - soc: toolchains: gcc: ram linker: add ILM last address overflow check - - drivers: mcan Add timeout counter support. - - drivers: tamper: add tamper driver - - drivers: cam: add cam_update_buffer2 API - - drivers: opamp: Add user configuration code. - - drivers: lcdc: add stride for layer config. - - drivers: pdma: add pdma_blit_ex. - - drivers:pllctl add out-of-bound check in pllctl driver. - - components:uart_lin: add hpm_uart_lin_send_wakeup() API - - components: enet_phy: add LAN8720 driver - - components: enet_phy: add definition of enet_phy_link_status_t - - middleware: cherryusb: host: add dual port support - - middleware: cmsis_os2: adapter to rtthread wrapper - - middleware: cmsis_os2: update freertos files - - middleware: cmsis_os2: adapter to threadx wrapper - - middleware: cmsis_os2: adapter to ucOS-III wrapper - - middleware: hpm_sdmmc Add eMMC config partition API. - - middleware: cherryusb Add IAR toolchain support - - middleware: erpc Fix IAR RISC-V support issue - - middleware: tflm: add IAR riscv support in flatbuffer - - middleware: FreeRTOS: portable:Added IAR portable layer. - - middleware: segger_rtt Added EWRISCV support - - middleware: hpm_math Add nds_dsp library for IAR. - - middleware: lwip: cc: add PACK_STRUCT_XXX definitions for IAR platform - - middleware: uC/OS-III: enable plicsw in IAR asm code - - middleware: add tinyengine - - middleware: threadx: add support for gptmr. - - middleware: threadx: add profile support. - - middleware: add agile_modbus. - - middleware: add cherryrb. - - middleware: cherryusb Add missing swap32/swap16 implementation. - - middleware: hpm_mclv2: add block type drive motors - - middleware: cherryusb: fix usbh_core ep0 buffer index - - boards: hpm6200xxx and hpm6750xxx: add board_init_core1() API - - boards: add tamper feature and pins init - - boards: hpm5300evk: add board_init_console() declaration in board.h - - boards: hpm6750evk/hpm6750evk2: add board_dual_usb feature - - boards: openocd: add windows guide to *_all_in_one.cfg - - boards: openocd: soc: add reset_soc proc - - board:add pgpio configuration on hpm5301evklite - - samples: drivers: add mono sample. - - samples: drivers:mcan Add timeout counter sample. - - samples: drivers: tamper: add tamper sample - - samples: cmsis_os2: blinky: add rtthread samples - - samples: cmsis_os2: add msg_queue sample - - samples: cmsis_os2: add mem_pool samples - - samples: cmsis_os2: msg_queue: add ucOS-III support - - samples: cmsis_os2: blinky: add ucOS-III support - - samples: lwip: common: add a task netif_update_link_status - - samples: lwip: add MAC address load from OPT MAC area - - samples: cherryusb: device: cdc acm: add cdc_acm_uart_com sample - - samples: cherryusb: device: add msc sdcard sample - - samples: tinyengine: add person detection. - - samples: rtos: add threadx gptmr sample. - - samples: modbus: tcp: add tcp samples. - - samples: modbus: rtu: add rtu sample. - - samples: add cherryrb sample. - - samples: cherryusb: host: add dual port sample - - samples: cherryusb: device: add dual port sample - - samples: cherryusb: device: add dual lun msc sample - - samples: lwip: ports: rtthread-nano: multiple: add arch-related files - - samples: lwip: ports: freertos: multiple: add arch-related files - - samples: lwip: common: multiple: osal: add osTaskFunction definition - - samples: lwip: add a lwip_tcpecho_multi_ports_rtthread-nano sample - - samples: lwip: add a lwip_tcpecho_multi_ports_freertos - - samples: lwip: lwip_tcpecho_xxx: add definitions for task priorities - - samples: lwip: lwip_tcpecho_freertos_socket: newly add - - samples: lwip: lwip_tcpclient: newly add - - samples: lwip: add lwip_tcpclient_freertos_socket - - samples: vglite: add sample of rotate tiger. - - samples: lwip: lwip_tcpclient_freertos_socket: fix failure to run - - samples: lwip: lwip_tcpclient: fix failure to run with some release-related type - - samples: jpeg: jpeg_encode: add debounce for button. - - docs: add cmake doc - - docs: hpm5300evk: add qeiv2 sin/cos pins - - scripts: support sdk project localization. - - cmake: add nds-gcc options to sdk_lib for nds-gcc. - - cmake/scripts: add IAR project generation support - - cmake: add symbols to specify linker for tools. - - cmake: add sdk_*_src_glob. - - cmake: add custom targets for localization. - -### Fixed: - - soc: hpm6750: fix segger linker vectors order - - soc: hpm_interrupt.h Fix compiling warning for DSP related macros - - soc: hpm6750: otp Fix OTP program and read logic - - soc: hpm6880: clock Fix wrong enum value for TSNS clock. - - soc: clock driver: correct the clock name value for pll clocks. - - soc: HPM6280: fix adc/dac clock setting - - soc: ppor: fix ppor clear reset flag and set reset type API error - - soc: HPM6880: fix i2s clock config driver - - drivers: adc12: fix calibration setting error - - drivers: cam: DMASA_FB2 need to be assigned whether FB2 buffer is enable or not. - - drivers:can correct the logic of disabling re-transmission for ptb & stb. - - drivers: qeo: fix driver error - - drivers: i2s: ensure valid BCLK before call software reset. - - drivers: pdma: fixed OUT_PS[] config. - - components: wm8960: invert LRCLK to align with soc I2S. - - middleware: uC/OS-III: fix register t0 unsafe. - - middleware: ptpd: fix netShutdown error in ptpd initialization - - middleware: cmsis_os2: task should call exit interface before exit - - middleware: threadx: fix threadx profile RA register save and restore bug. - - middleware: hpm_mcl: fix divide-by-zero error. refs: hpm_sdk-#1091 - - middleware: cherryusb/tinyusb/usbx: device: fix transfer_len not reset - - middleware: cherryusb/usbx: fix dtd return problem - - middleware: cherryusb/tinyusb/usbx: fix usb device interrupt should be check active status - - middleware: tinyusb: fix ehci cap_reg address error - - middleware: tinyusb: fix hid report id - - middleware: cherryusb: fix usbd_ep_close not reset ep_enable flag - - middleware: cherryusb: fix rndis message length check - - middleware: freertos: fix implementation error in xPortIsInsideInterrupt. - - boards: hpm6200evk: fix tamper pin config - - board: openocd: all_in_one: hpm6800 config file is missed. - - boards: openocd: all_in_one: hpm5300: correct soc config name. - - samples: threadx hello: fix printing errors. - - samples: drivers: ad12/adc16: fix initialization sequence for trigger source, trigger mux and trigger target config - - samples: lwip: lwip_ptp: fix netSend error before link-up - - samples: dma: fix dma uart init position - - samples: drivers:spi:master_trans_large_amound_of_data Fix logic error if SPI support 4GB transfer size - - samples: sdxc: add boundary protection for last 1024 blocks test - - samples: lwip: common: multiple: fix typo of enet_update_dhcp_state() - - samples: lwip: common: single/multiple: fix timeout passed into sys_arch_mbox_fetch() - - samples: e2prom: bugfix: base read fail if run perf firstly .refs:hpm_sdk-#1499 - - samples: modbus: tcp: use volatile to prevent the compiler from optimizing out key variables - - samples: modbus: rtu: fixed failed to run after turning on optimization issue. - - samples: power_mode_switch: hpm68xx: fix ddr access issue for wait/stop mode - - samples: cherryrb: fixed stack overflow issue - - samples: lwip: lwip_tcpecho_multi_ports_ports_rtthread-nano: fix failure to run - - sample: jpeg: jpeg_encode: fix that udisk can't be mounted when first capture. - - cmake: correct board search path symbol for core1. - - cmake: gcc: fix system include path. - - cmake: fix sdk_link_libraries failed to link std lib. - - cmake: EXTAR_LD_FLAGS to be added as ld options. - - docs: lwip_ptp: v1: salve: fix format error - - docs: samples: ppor: change title from sysctl to ppor - - docs: hpm6750evk2: fix table display error - -## [1.4.0] - 2023-12-29: - -Main changes since 1.3.0 - -Tested Segger Embedded Studio Version: 7.32 - -### Changed: - - soc: hpm5301: add hpm5301 - - soc: hpm6880: add hpm6880 - - soc: HPM6750: pcfg: update dcdc dcm mode config - - soc: clock driver: update clock_set_source_divider() and clock_get_source() - - boards: add hpm5301evklite - - boards: add hpm6800evk - - boards: update clock_set_source_divider() to use clk_src_t type param - - boards: hpm6750evkmini: use the same uart port as core1 for some samples. - - drivers: dao: update driver support new feature on hpm6800 - - drivers: adc16: update comment about cal_avg_cfg in calibration - - drivers: qeiv2: change adc trigmux name x to 0 and y to 1 - - drivers: femc: add overflow protect to time config - - drivers: mcan Enlarge the range of CAN_EVENT_ERROR. - - components: serial_nor: add subdirectory in cmakelists - - middleware: cherryusb: update to v0.10.2 - - middleware: cherryusb: rename host and device isr - - middleware: FreeRTOS: xPortIsInsideInterrupt() using CSR_MSCRATCH - - middleware:hpm_sdmmc Enhanced all speed modes support for SD and eMMC. - - middleware: usbx: device: support chain transfer - - samples: cherryusb: host: rndis: integrate dhcp thread into ping thread for host rndis ping and iperf sample - - samples: adc: temp: add isr for temp out of thresholds - - samples: drivers: acmp: optimization for comparing input voltage - - samples: lwip: add DHCP macro definition in CMakeLists.txt - - samples: lwip_ptp: enable DHCP feature in PTP samples - - samples: drivers: qeiv2: update API for adc-qeiv2 pin initialization - - samples: bldc_foc: change adc buffer size from 40 words to 48 words - - samples: remove explicitly c++ standard setting. - - samples: driver: cam: set default cmake build type - - samples: lwip: update to Class C static IP adress - - samples: tinyuf2: remove unnecessary cache ops. - - samples: lwip: lwip_tcpecho_freertos: optimization for API call in a thread-safe way - - samples: lwip: lwip_ptp: v1: slave: update static ip - - samples: lwip: optimize DHCP enable logic - - samples: lwip: opts: adjust the allocation strategy of memory pool - - samples: lwip: lwip_iperf: adjust MEM_SIZE for saving memory consumption - - samples: lwip: lwip_tcpecho_multi_ports: update the second IP with C class - - samples: enet: optimization for PHY selections - - samples: dma: update uart rx circle transfer buffer size - - samples: drivers: sdxc/emmc Correct doc for emmc sample. - - cmake: sdk_link_libraries link libraries for supported tools. - - cmake: add project name for hpm_sdk sub directory. - - cmake: decouple CMAKE_BUILD_TYPE and linker script. - - cmake: ses: remove -Ox from gcc option list. - - cmake: set default c++ standard to c++11. - - Update CONFIG_HAS_xxx to HPMSOC_HAS_xxx. - - segger: enable all warnings. - - segger: release: release optimization level use cmakelist config - - scripts: ses: set intermediate dir in project file. - - docs: remove quick start guide from top level readme - - docs: change doc structure. - -### Added: - - soc: HPM5361: add trgm filter shift length feature - - soc & drivers: hpm5300: add DMAMUX_SOC_WRITEONLY and TRGM_SOC_HAS_DMAMUX_EN features - - drivers: lcb: add lcb driver. - - drivers: sdxc add more APIs for timing and power control. - - drivers: mipi_csi: add mipi csi. - - drivers: cam: add cam_stop_safely API - - components: usb: device: add dtd chain transfer - - components: panel: enable panel component. - - components: camera: ov5640: add mipi interface. - - middleware: rtthread-nano: add v3.1.5 - - middleware: rtthread-nano: add FPU support. - - middleware: tinyusb: device: update to support chain transfer - - middleware: cherryusb: device: update to support chain transfer - - middleware: vglite: add 4.0.49. - - middleware: cherryusb: add USB_OSAL_WAITING_FOREVER for sem and mq use - - middleware: add hpm_mcl_v2 - - middleware: lwip: add ptpd v1 & v2 - - middleware: cmsis_os2: add source files. - - samples: mcl: add step motor. - - samples: lwip: lwip_ptp: v2: support IEEE1588 V2 - - samples: cherryusb: add audio_v2_mic_speaker_rtthread sample - - samples: cherryusb: host: add hid and msc rtthread samples - - samples: cherryusb: host: usbnet: add support ec20 module sample. - - samples: cmsis_os2: add blinky sample. - - samples: driver: mipi_csi: add mipi_csi. - - samples: mcan Support MCAN4-7 loopback testing. - - cmake: support custom output file name. - -### Fixed: - - soc: fix cache maintenance at startup - - soc: hpm53xx Correct exip API tree offset. - - soc: toolchain: missing .fast.* in gnu ld linker script. - - soc: fix tbss and tdata section not initialized. - - soc: sysctl: sysctl_enable_group_resource() should be check LOC_BUSY - - soc: hpm5300 Correct Cache size and Cacheline size. - - boards: hpm6750evkmini Fix the issue that eMMC is still 3.3V even 1.8V is selected. - - boards: hpm5301evklite correct jlink script device number. - - components: camera: power_up is enable by default for ov5640/ov7725. - - docs: samples: drivers: add numberic index. - - drivers/soc: fix build warning - - drivers: i2c: add slave device response judgment for master read/write APIs - - drivers: opamp: fix opamp vssa connect error. - - drivers: pllv2: fix pllctlv2_pll_is_stable() API - - drivers: qeiv2: fix invalid argument check - - drivers: dac: fix the upper limit value setting for DAC_OUTPUT - - drivers: jpeg: fix pixel format index for out buffer. - - drivers: uart: fix not support oversample 32 for rx idle detection on hpm5300 - - middleware:ftafs Fix SD card init crash. - - middleware: mcl: fix path plan error. - - middleware: hpm_sdmmc Fix the issue that IO initialization work unstable on HPM6300. - - middleware: hpm_sdmmc Fix voltage switch setting issue for SD and eMMC. - - middleware: hpm_sdmmc Fix the PWR and VSEL IO initiaization issue. refs:hpm-sdk-#863 - - samples: sei: fix nikon sample crc calc error. - - samples: cherryusb: msc device: add pre-format fat12 file system in u disk - - samples: adcx: replace const with a macro for ADC sample cycle - - samples: tinyusb:fix the usb host pin init. - - samples: motor_ctrl: bldc_littlevgl_foc: program crash. - - samples: qeiv2: uvw: fix uninitialized pointer usage - - samples: cherryusb: fix semaphore give in isr - - samples: drivers: Fix the issue that can error example may block. - - samples: uart_irq: fix unable to limit receive large than buffer size. - - samples: drivers:sdxc:emmc remove infinite loop for emmc initialization. - - samples: drivers: i2s: fix tx underflow during tx start - - samples: lwip: lwip_tcpecho_multiple_ports: fix no echo data when receiving large amounts of data - - samples: mcl: pwm duty set error. - - samples: cherryusb: host: usbnet: fixed when performing a stress test with a large amount of iperf data, will send fai. - - samples: cherryusb: audio_v2_mic_speaker_rtthread: fix mic no voice problem - - samples: jpeg_decode: add delay after usb pins init for waiting power stable - - samples: hfi: hpm6750evk2: fix the motor shake. - - cmake: segger: remove workstation specific path info. - - cmake/soc: fix heap/stack size setting for andes toolchain. - - cmake: ses: correct device name for core1. - -## [1.3.0] - 2023-09-28: - -Main changes since 1.2.0 - -Tested Segger Embedded Studio Version: 7.32 - -### Changed: - - boards: hpm6200evk/hpm6300evk: delete unwanted clock_ahb div set - - boards: hpm6750xxx: switch dcdc work mode to dcm mode - - docs: sdk: boards: hpm6750evk2: add pps pin information - - component: wm8960: support sysclk pre-divider - - components: serial_nor: add serial nor flash. - - openocd: probes: ft2232: remove trst and srst config. - - ip: cam：remove 0x5c MAX_WN_CYCLE register in regs.h - - driver: cam: remove invalid register - - drivers: i2s: update API - - drivers: adc: adc12/adc16: rename adc16_get_busywait to adc16_is_nonblocking_mode - - drivers: adc: adc12/adc16: update adcx_init API - - drivers: pllctrl: update pllctrl drivers - - drivers: spi : add spi enable and disable datamerge - - drivers: spi : add spi_set_address_len API - - drivers: pdgo Add missing APIs - - drivers: uart: update uart rx idle flag process and fifo control - - soc: delete_unnecessary_ppor_reset_bit_field - - soc: hpm_gpiom_soc_drv.h: delete gpiom_gpio_t soc name - - soc: delete DMA_SOC_BUS_NUM Macro - - soc: pcfg: update pcfg SCG_CTRL related drivers - - soc: hpm6750:startup Enable LMM1 clock before access to LMM1 - - soc: gcc ld: add memory used size check - - middleware: cherryusb: update to v0.10.1 - - middleware: guix: demo adapts to 800 * 480 resolution - - middleware: guix: improve demo display performance - - middleware: cherryusb: update for midi descriptor define - - middleware: cherryusb: update for midi - - samples: drivers: adc: adc12/adc16: speed optimization for oneshot reading - - samples: drivers: adc: adc12/adc16： update API call used for nonblocking judgement - - samples: drivers: adc: adc12/adc16: update API call related to blocking setting in oneshot mode - - samples: drivers: adc: adc12/adc16: reduce the input parameters of init_trigger_target function - - samples: drivers: adc: adc12/adc16: update init_oneshot_config - - samples: drivers: adc: adc12/adc16: optimization for clearing interrupt status - - samples: drivers: pwm: Add pwm clock jitter demo - - samples: cherryusb: hid host: separate mouse and keyboard urb - - samples: hrpwm: Add demo for updating hrpwm frequency - - samples: drivers:mcan Add CAN error handling and refined logic. - - samples: mbx: move dualcore mbx sample to multicore folder - - samples: cherryusb: update for v0.10.1 - - samples: motor_ctrl: bldc smc: gcc toolcahin enable fpu. - - samples: lwip: lwip_tcpecho_freertos: optimization in a thread-safety way - - samples: qeo: update qeo abz frequency configuration - - samples: gptmr: add sent_signal sample. - - samples: lwip: lwip_ptp: remove the dependency on pps0 pinout - - samples: dma_manager: update for use dma_mgr_setup_channel() - - samples: drivers: gptmr: pwm_measure: support use dma - - samples: lwip: lwip_httpsrv/lwip_https_server: rename project names for uniform naming - - samples: multicore: lvgl_coremark: delete custom linker files and using andes toolchain - - samples: flash_algo: update device size. - - samples: cherryusb: host: hid: use ep_mps to fill urb - -### Added: - - cmake: ses: support specify custom openocd board cfg file. - - cmake: support specifying minimum sdk version in app.yaml. - - boards: add hpm5300evk - - components: eeprom_emulation: add hpm nor-flash support - - components: eeprom_emulation: add eeprom emulation component - - soc: add APIs for get or set sysctl resource status - - drivers: common: add HPM_ALIGN_DOWN and HPM_ALIGN_UP define - - drivers: adc: ad12/adc16: add adcx_set_blocking_read/adcx_set_nonblocking_read - - drivers: add encoder position driver - - drivers: lcdc: add enable/disable background in alpha blender. - - drivers: usb: add api to set dp/dm pin pulldown resistance - - drivers: spi: add spi_get_rx_fifo_valid_data_size and spi_get_tx_fifo_valid_data_size APIs - - drivers: spi: add directIO function APIs - - drivers: enet: add rx resume API - - drivers: adc16: add resolution setting in adc16_get_default_config API - - drivers:rtc Add rtc_get_timeval API. - - drivers:mcan Add mcan_transmit_via_txfifo_nonblocking API. - - drivers: usb: add usb_hcd_set_power_ctrl_polarity() API - - drivers: plb: add plb drivers - - drivers: linv2: add linv2 driver - - drivers: sei: add sei driver - - drivers: dmav2: add dmav2 driver - - drivers: qeo: add qeo driver - - drivers: qeiv2: add qeiv2 driver - - drivers: mmc: add mmc driver - - drivers: rdc: add rdc driver - - drivers: add opamp driver - - drivers: bgpr: add related APIs for bgpr - - middleware: FreeRTOS: add xPortIsInsideInterrupt() API - - middleware: threadx: add definition automatically when enable traceX - - middleware: freeRTOS: add use gptmr to generate interrupt - - middleware: hpm_mcl: add hfi - - samples: drivers: adc: adc12/adc16: add wdog feature - - samples: add opamp demo - - samples: cherryusb: rndis: host: add iperf sample. - - samples: cherryusb: rndis: host: add ping sample. - - samples: drivers: adc: adc12/adc16: add hw trigger configuration in sequence mode - - samples: eeprom_emulation: add eeprom emulation perf test sample - - samples: eeprom_emulation: add base api demo - - samples: tracex: add demo for traceX usage - - samples: cherryusb: add audio_v1_mic_speaker_midi sample - - samples: cherryusb: add midi device sample - - samples: drivers: sei: add sei samples - - samples: drivers: plb: add plb demo - - samples: drivers: mmc: add mmc demo - - samples: drivers: qeiv2: add qeiv2 demo - - samples: drivers: qeo: add qeo demo - - samples: drivers: dmav2: add dmav2 demo - - samples: drivers: linv2: add linv2 demo - - samples: drivers: rdc: add rdc demo - - samples: drivers: pdgo Add PDGO samples - - samples: drivers: ewdg Add EWDG sample - - samples: lwip: add a lwip_tcpecho_multi_ports sample - - samples: motor_ctrl: add hfi - -### Fixed: - - cmake: fix segger default heap and stack size config - - cmake: fix add_subdirectory_ifdef arg processing. - - doc: boards: hpm6300evk: fix acmp pin info. - - boards: hpm6750evkmini: fix board_init_rgb_pwm_pins() problem - - boards: hpm6200evk: fix BOARD_G_GPIO_CTRL defined in wrong position - - openocd: hpm6750-dual-core: fix expression warning. - - component: wm8960: fix clock tolerance process - - soc: toolchains: segger: block tls add with fixed order - - soc: toolchain: gcc: fix Thread-Local Storage problem - - soc: segger linker files: fix heap and ctors initialize - - soc: fix interrupt complete operation - - soc: pcfg: fix DCDC_PROT[OVERLOAD_LP] bit access - - soc: ip: adc12: fix ADC12 threshold setting - - soc: HPM6750: fix clock setting and frequency obatining error - - soc: HPM6360: fix clock source definitions for ADC16 - - soc: HPM6280: fix clock source definitions for ADC16 - - soc: HPM6360: fix obtaining clock source error for DAC - - soc: HPM6280: fix obtaining clock source for DAC - - drivers: adc16: add bus mode enable control APIs - - drivers: adc16: fix ahb setting - - drivers: cam: clear the status of CAM should not affect other bits - - drivers: trgmux: filter function can't work. - - drivers: src: adc16: fix end count setting - - drivers: adc/dac: fix interrupt status clearing - - drivers: adc16: fix DMA access format - - drivers: sdm: fix over sample rate and signal sync problem - - drivers: pwm: fix pwm xcmp enable setting - - drivers: pwm: correct external fault polarity setting. - - drivers: pwm: add update hrpwm reload shadow api - - drivers: spi: fix can't set change data_bits use spi_set_data_bits API - - drivers: ptpc: fix ptpc_clear_irq_status API issue. - - drivers: i2c: fix i2c_clear_status API issue. - - drivers: gptmr: fix gptmr_clear_status API issue. - - middleware: erpc: rpmsg_lite: fix platform_in_isr() error - - middleware:hpm_sdmmc Fix the issue sdsc cards are not supported. - - middleware: threadx: fix D extend asm code error - - samples: usbx: add multi devices and hot plug support - - samples: motor_ctrl: fix adc trig invalidate. - - samples: lwip: fix TCP reception error when size over 2KB - - samples: lwip: DHCP failure in lwip_tcpecho_freertos - - samples: drivers: adc: adc12: fix the status flag judgement in isr process - - samples: rgb_led: fix cmp shadow error - - samples: gptmr: pwm_generate: fix inaccurate duty in high frequency - - samples: lwip: low_level_input: fix the network storm issue - - samples: timer_basic: fix inconsistent use of defines - - samples: drivers: adc: adc16: fix the bit of interrupt status clearing in sequence mode - - samples: power_mode_switch: trigger system lowpower for standby mode - - samples: touch_panel: fix error data when 5 fingers touch screen at same time. - - samples: jpeg: jpeg_decode: fixed lcd display is tore when decoder is running - - samples: jpeg: jpeg_decode: malloc out of memory on gcc - - samples: drivers:can Fix abnormal behavior on can error sample. - - samples: segger_rtt: call board_init_clock. - - samples: drivers: acmp: fix one toggle value but multi toggle pulses - - samples: lwip_tcpecho_freerstos: fix code stuck with gcc toolchain - - samples: jpeg: fix JPEG_USE_UDISK compile error - - samples: bldc_foc: fix input value range. - - samples: cherryusb: rndis: udp_echo: fix echo extra char - - samples: usbx: fix global var placement - - samples: power_mode_switch: set to preset_1 after exiting wait mode. - - samples: pla: fix pla first pulse abnormal. - - samples: plb: fix the first pulse is abnormal. - -## [1.2.0] - 2023-06-30: - -Main changes since 1.1.0 - -Tested Segger Embedded Studio Version: 7.22 - -### Changed: - - boards: hpm6750evk*: decrease core frequency from 816MHz to 648MHz - - openocd: soc: hpm6280: simplify dual core release core1 approach. - - cmake: segger: configure optimization level according to gcc level. - - soc: dmamux: move it from ip to soc - - soc: interrupt: adjust irq api. #659 - - soc: improve svd file - - soc: hpm_soc_feature.h: remove ADC16_SOC_TEMP_CH_EN for some specified Socs - - components: enet_phy: update the common enet phy header file - - components: sgtl5000 and wm8960: update clock setting - - drivers: uart: update uart driver - - drivers: pdma: improve quality of scale - - drivers: adc: adjust wait_dis type in adc16_config_t struct - - drivers: enet: update rmii reference clock setting API for ENET - - utils: hpm_swap: escape for andes toolchain. - - middleware: hpm_sdmmc: add spi sdcard - - middleware: motor_ctrl: change the file organization - - middleware: motor_ctrl: remove slide control content from foc - - middleware: lvgl: upgrade to v8.3.5 (with pdma) - - middleware: lvgl: Add direct mode - - middleware: cherryusb: update version to v0.8.0 - - samples: I2S_DMA and I2S Interrupt: update sample behavior - - samples: cherryusb: hid host: separate mouse and keyboard urb - - samples: cherryusb: increase max interface and endpoint number Configuration - - samples: cherryusb: uac2: move setting sampling freq to isr - - samples: cherryusb: audio: update descriptor for identification - - samples: audio_codec: set codec voice to max and increase irq priority - - samples: multicore: lvgl_coremark: delete custom linker files and using andes toolchain - - samples: lvgl_audio_player: update CMakeLists.txt to using noncacheable framebuffer - - samples: spi: clean the redundant code - - samples: i2c: improve the processing of FIFO in ISR - - samples: drivers: uart: update uart_rx_timeout demo - - samples: drivers: gptmr: split sample into multiple function samples - - samples: drivers: adc: optimization for all macro definitions in applications - - samples: drivers: adc: update struct member names - - samples: update clock divider setting for ADC-related examples - - samples: cherryusb: move vid/pid etc definition to usb_config.h - - samples: cherryusb: device: update vid to hpmicro 0x34B7 - - samples: cherryusb: change API update for v0.8 - - samples: cherryusb: device: audiov1: change to full speed mode - - samples: tinyusb: uac2: update descriptor and sample - - samples: lwip: disable mmc interrupt settings - - samples: lwip: lwip_ptp: v1: sync precision improvement - -### Added: - - cmake: toolchains: add isa spec 20191213 support. - - cmake: ses: support set ses raw option in CMakeLists.txt - - cmake: add option to specify board search path. - - cmake: generate compile_commands.json file - - soc: hpm_soc_feature: add a common macro for ADC12 and ADC16 - - drivers: cam: add new APIs - - drivers: spi: add new APIs - - drivers: i2c: add new APIs - - drivers: I2S: add i2s_check_data_line_status API - - drivers: dma: add dma_set_transfer_src_width_byte_size() API - - drivers: gptmr: add output capture APIs - - drivers: gptmr: add gptmr_channel_get_dma_request_event api - - drivers: adc: add adc16_trigger_pmt_by_sw API - - drivers: enet: add some APIs related to interrupt settings - - drivers: enet: add a new API for transmisstion - - drivers: usb: add macro CONFIG_USB_DEVICE_FS to set full speed mode - - components: uart_lin: add uart lin component - - components: add smbus - - components: add sccb - - middleware: lvgl: add macro HPM_LVGL_FRAMEBUFFER_NONCACHEABLE - - middleware: add AzureRTOS (threadx/usbx/netx/guix) - - middleware: hpm_mcl: sensorless over-zero - - middleware: add smc - - middleware: hpm_sdmmc Add eMMC support - - middleware: hpm_math: add bit conversion function - - middleware: add uC/OS-III - - middleware: cherryusb: audio: add feedback descriptor - - middleware: cherryusb: audio: add param to set endpoint bmAttributes - - middleware: microros: add microros foxy sources - - samples: drivers: spi: add spi_sdcard_fatfs sample - - samples: drivers: spi: add sd sample - - samples: add uart_lin - - samples: motor_ctrl: sensorless: over-zero demo - - samples: cherryusb: add rndis host dhcp samples - - samples: drivers: sdxc :emmc Added eMMC sample - - samples: drivers: adc12: update irq pattern for sequence usage - - samples: drivers: pla: add pla tamagawa demo - - samples: drivers: gptmr: add counter_sync sample - - samples: drivers: gptmr: add timer_basic sample - - samples: drivers: gptmr: add t_shape_accel_decel sample - - samples: drivers: dma/gptmr: add trigger dma transfer using gptmr event sample - - samples: drivers: uart add uart_rx_timeout sample - - samples: i2c: add smbus samples - - samples: lwip: lwip_tcpecho_freertos: add self-adaption - - samples: cherryusb: hid host: move usbh_submit_urb() out of condition - - samples: cherryusb: add composite freertos sample - - samples: cherryusb: add rndis freertos sample - - samples: cherryusb: add msc freertos sample - - samples: cherryusb: add audio v2 mic speaker freertos sample - - samples: cherryusb: add hid mouse freertos sample - - samples: cherryusb: add hid keyboard freertos sample - - samples: cherryusb: add cdc acm freertos sample - - samples: cherryusb: add rndis tcp server sample - - samples: cherryusb: add rndis device udp_echo sample - - samples: cherryusb: add rndis device http_server sample - - samples: cherryusb: device: add audio_v2_speaker_sync sample - - samples: add several uC/OS-III samples - - samples: smc: add smc demo - - samples: microros: add subscriber, sevice and publisher - - samples: uC/OS-III: mutex - -### Fixed: - - cmake: ses: fix __SEGGER_RTL_vfprintf issue with nds tool in SES 7.20. - - soc: hpm6280: Modify the number of PWM cmps. - - soc: reset.c: __dso_handle needs to be declared for nds toolchain. - - soc: fix max buffer length in sequence mode for ADC - - soc: HPM6750: enet soc drv: fix set clock delay settings - - soc:hpm6360:sdxc Correct clock divider settting issue - - drivers: pla: missing Union Field - - drivers: spi: fix the problem of CMD and ADDR configuration order - - drivers: i2c: fix clock frequency error rate problem - - drivers: i2c: clear CMPL bit in API to avoid blocking the trans - - drivers: i2c: fix i2c slave device read and write fail - - drivers: i2c: fix read data unexpected multi transition. - - drivers: i2c: fix w1c clear status error - - driver: usb: fix w1c clear flag error - - drivers: gptmr: fix dma request enum definition - - drivers: adc: fix logics for judging the validity of arguments - - component: uart_lin: fix break signal problem - - middleware: cherryusb: fix buffer size error - - middleware: lvgl: fix fbbuffer option - - samples: gptmr: fix pwm_measure sample compile waring - - samples: jpeg: fix interchange format of exif support - - samples: jpeg: fix jpeg decode - - samples: drivers: spi: fix the problem of CMD and ADDR configuration order - - samples: drivers: mcan: can_fd loopback test setting is incorrect - - samples: cherryusb: http_server_freertos: fix printf content error - - samples: cherryusb: audio: change endpoint attributes for support MACBOOK - - samples: tinyusb: msc: increase block numbers for windows format - - samples: lwip: lwip_httpsrv: fix reload or refresh error - -## [1.1.0] - 2023-03-31: - -Main changes since 1.0.0 - -Tested Segger Embedded Studio Version: 7.10 - -### Changed: - - docs: add new docs for rtd project. - - soc: ip: enet: update the enet register file - - soc: ip: adc16: update the adc16 header file - - soc: hpm_romapi - Add APIs for configuring remapping, exip regions - - drivers: enet: improve APIs related to PPS - - drivers: adc: change adc bus blocking interface - - drivers: adc: optimize getting oneshot result - - drivers: src: update the default config for ADC12&ADC16 - - boards: rename board-level APIs related to enet - - components: enet_phy: rtl8201: update the register file - - middleware: hpm_math: update dsp version - - middleware: erpc: update to v1.10.0 - - samples: uart: rename uart_dma_rx_idle to uart_software_rx_idle - - samples: uart: add hardware rx idle detection sample - - samples: multicore: erpc: core1 add sdk_compile_options(-O1) - - samples: drivers: gptmr: update sample output. - - samples: lwip: common: arch: ethernetif: update a calling function name - - samples:drivers: adc: optimize oneshot handler - -### Added: - - arch: add FPU related APIs - - soc/board: add HPM6280 support - - soc: HPM6750: acmp: add ACMP section - - components: add mt9m114 support - - drivers: add raw8 pixel format support - - drivers: csr - Implement CSR driver - - drivers: adc: adc16: support resolution setting - - drivers/samples: add SDM/PLA/CRC/MCAN - - drivers: I2C: add new API - - drivers: adc: adc16: support resolution setting - - drivers: enet: add enet control config for transmission - - middleware: cherryusb: audio: update class driver and demo template - - middleware: add mbedtls lib files with SDP acceleration - - freeRTOS: add support for static allocation - - samples: drivers: enet: add a pps demo - - samples: cherryusb: add audio samples - - samples: add the resolution parameter in all demos with ADC16 - - samples: add rfft demo - - sampels: i2c: add interrupt b2b samples - - samples: drivers: i2s: add an i2s_master demo - - samples: drivers: i2s: add an i2s_slave demo - - samples : rom_api : add sw_gm_api filter - - samples: add the resolution parameter in all demos with ADC16 - -### Fixed: - - openocd: hpm6300evk: update sdram initialization. - - drivers: trgmux: trigmux edge filter setting error - - drivers: enet: fix register access error - - drivers: adc16: fix the config error of ADC16_CONFIG1 - - drivers: i2c: fix i2c timing configuration - - drivers: SPI: fix SPI status API - - drivers: fix gptmr cmp value don't minus one - - drivers: mcan: correct the mcan ext_id filter issue - - drivers: I2C: fix issue in i2c_master_address_read API - - drivers: Self_ACK cannot be set in CAN driver - - drivers: rtc rtc_config_alarm always return error code - - cmake: correct source code compilation - - soc: toolchain: gcc: initialize heap for SES - - soc: gcc linker files: add NOLOAD keyword to noncacheable.bss section - - soc: HPM6360: gcc: ld: correct noncacheable region name. - - drivers: qei: Fix speed display always zero - - middleware: freertos: disable global irq before vTaskStartScheduler - - freeRTOS: fix trap when enable float feature - - freeRTOS: fix tick lost - - freeRTOS: fix segger project build warning - - samples: drivers: i2s: fix CFGR config - - samples: drivers: fix acmp toggle error - - samples: lwip: fix the DHCP issue - - samples: uart: fix irq_id judgment - - samples: fix the order of uart pin configuration and clock configuration - - samples: update spi dma sample - - samples: drivers: sysctl: correct reset enable approach. - - samples: fix dma_general_transfer sample memory out of bounds - - samples: drivers: wdog: Fix logic issue on finding the nearest interrupt interval - - sample: audio_codec: decoder_wav: add '\0' to fatfs path - -## [1.00.0] - 2022-12-31: - -Main changes since 0.14.0 - -Tested Segger Embedded Studio Version: 7.10 - -### Changed: - - boards: add version info in banner. - - board: lcdc: move panel para to board - - components: spi component to support to transfer different width of data in dma handshake mode - - drivers: rename dram to femc - - middleware: cherryusb update to v0.7.0 - - middleware: erpc: update for support rtos - - middleware: hpm_mcl: update api naming - - samples: erpc: rename erpc_matrix_multiply_rpmsg to erpc_matrix_multiply_rpmsg_bm - - samples: erpc: reorganize erpc_matrix_multiply_rpmsg samples - - samples: erpc: move samples folder to erpc_matrix_multiply_rpmsg - - samples: update i2c/spi dma channel and dmamux channel definition - - ses: project template: use demo.* as output file naming. - - soc: HPM6750: toolchains: update linker files - - soc: HPM6360: toolchains: update linker files - -### Added: - - arch: riscv: add read_clear_csr() API - - component: add wm8960 support - - component: add usb device iso transfer support - - drivers: hpm_common: include hpm_sdk_version.h. - - drivers: common: add NOP and WFI. - - drivers: uart: add api to recv/send byte directly. - - soc: HPM6750 linker files: rename rpmsg_sh_mem to sh_mem - - cmake: add sdk version header file generation. - - middleware: tinyusb: add audio class - - middleware: hpm_math: add NN library - - samples: erpc: add erpc_two_way_rpc_rpmsg_rtos sample - - samples: erpc: add erpc_matrix_multiply_rpmsg_rtos sample - - samples: add power mode switch demo. #282 - - samples: drivers: adc: add a temperature measurement demo - - samples: drviers: femc: add sram sample - - samples: lwip demo for FreeRTOS - - samples: lwip demo of interrupt usage - - samples: tinyusb: add uac2 demo - - samples: tflm: add face detection demo - - samples: tflm: add MLPerf Tiny benchmark demo - - samples: lwip: common: feature: add a LPI interrupt process - -### Fixed: - - drivers:interrupt: Fix FPU context crashing in nested irq case - - drivers: src: adc: fix adc result in period mode - - segger: update app directory structure in SES. - - soc: disable irq during cache maintenance - - middleware: lvgl: fps calculation to No. - - samples: get off level based on board api. - - samples: multicore: hello: core1 rgb led does not change correctly. - -## [0.14.0] - 2022-10-31: - -Main changes since 0.13.0 - -Tested Segger Embedded Studio Version: 6.34a - -### Changed: - - drivers: inc: update adc driver - - drivers: gptmr: update reload value - - components: enet_phy: optimize APIs - - components: enet_phy: dp83867: rename functions - - components: conditionally add debug_console - - middleware: add cherryusb (0.6.0) - - middleware: littlevgl: update to v8.3.1 - - middleware: fatfs: file name encoding in utf-8 - - middleware: freertos: support nested irq handling - - middleware: hpm_mcl: Optimized motor control foc speed - - samples: drivers: dma src move to dma_general_transfer folder - - samples: lwip: update all static addresses and all gateway addresses - - samples: lwip: lwip_iperf: optimize the interactive log - - samples: tinyusb: device: hid_generic_inout: optimize the python script - - openocd: HPM6750A1 silicon in hpm6750-dual-core.cfg - - header file: update the enet/conctl register files - - header file: Update TRGMUX0 pin input source definition - - header file: update the ADC12 header files - - scripts: ses: organize file in ses according to real path. - - cmake: split gcc and ses source - - board: bump HPM6750 DCDC voltage to 1200mv - -### Fixed: - - drivers: pdma: fix scale api issue - - drivers: i2c: update DATACNT processing - - drivers: i2s: fix i2s interrupt workaround in i2s_init - - drivers: pwm: fix pwm capture function error - - drivers: pwm: fix pwm capture configuration error - - drivers: clock: fix error in clock_set_xxx_source - - drivers: wdg: timeout calculation error - - drivers: trgm_drv: bugfix: include error - - drivers: romapi: call fencei after flash erase/write operation - - drivers: watchdog: overflow - - drivers: usb: host controller initialization issue - - drivers: i2s: i2s_enable() issue fix - - middleware: tinyusb: src: class: fix the HID report desc macro - - samples: drivers: adc: optimize all ADC demos - - samples: drivers: adc: fix all channel initializations without a default value - - samples: motor_ctrl: hardware trigger api usage error - - samples: audio_codec: update clock process for 44100 sample rate - - samples: lcdc: boundary pixel is incorrenct - - samples: multicore: BOOT_HEADER was missing in multicore core0 example - - samples: drivers: i2s: correct audio data if depth < 32bit. - - samples: hpm_math: fft_perf_test: Fix error printing information - - samples: fix pdm2dao noise problem - - samples: lwip: fix the enet throughput degradation - - soc: correct address overlapping SES XIP linker file - - soc: correct the interrupt context switch issue - - soc: fix Lack of interrupt claim for swi - - boards: fix some rmii reference clock APIs - -### Added: - - boards: add hpm6750evk2 support - - soc: add initfini.c - - drivers: lcdc: add y8 support - - drivers: spi: update data_length processing - - drivers: spi: add api to enable/disable spi dma request - - drivers: pmp: Add pmp_config_entry API - - components: add ipc_event_mgr - - component: spi: add cache maintain - - middleware: add erpc - - samples: lwip: support self-adaptive port speed and duplex mode - - samples: jpeg: support grayscale - - samples: drivers: spi: use api to get data length - - samples: drivers: spi: add interrupt b2b sample - - samples: drivers: mbx: add singlecore samples - - samples: drivers: add dma circle transfer - - samples: drivers: pwm: add pwm capture demo - - samples: provide OTP API demo - - samples: add cherryusb hid/msc/cdc samples - - samples: add Guomi API example - - samples: add erpc sample - - samples: add segger_rtt - -## [0.13.0] - 2022-07-31: - -Main changes since 0.12.1 - -### Changed: - - drivers: adc: fix sequence and preemption mode - - drivers: usb: automatically change transceiver type in host mode - - drivers: pwm: modify the interface for setting the pwm shadow register trigger function - - drivers: sdxc: driver improvement - - samples: jpeg demo update - - samples: motor_ctrl: Optimize motor control performance - - samples: motor_ctrl: Modify the pwm update method to be hardware triggered - - samples: audio_codec: wav: Modify the interface - - samples: audio_codec: add dao support - - samples: tinyusb: update all USB project names - - samples: adc: place DMA buffer in noncacheable - - components: usb: update two struct definitions for the hcd_data_t and the dcd_data_t - - middleware: littlevgl: update double buffer refresh approach. - - middleware: fatfs: enable exfat format - - middleware: fatfs: change 'USB' to lowercase - - middleware: hpm_math: remove cache operations from the ffa interface - - scripts: ses: update file path using $(HPM_SDK_BASE) - -### Fixed: - - drivers: gpiom: fix spelling errors in API names - - drivers: enet: fix ptp time offset update - - drivers: cam: fix store mode configuration - - drivers: can: Fix the issue can timestamp cannot be enabled - - drivers: gpio: incorrect return type gpio_get_port_interrupt_flags. - - middleware: audio_codec: decoder_wav: fix wav codec problem - - middleware: tinyusb: fix the alignment of _hcd_data - - soc: driver: clock: i2s get clock error - - soc: hpm_misc.h: fix incorrect system address mapping. - - soc: SVD files: fix SDP peripheral reset value problem - - soc: disable vector mode explicitly. - - boards: correct device name in ses project - - board: correct the printf format for frequency and register base - - python: fix ses project generation on windows - - samples: adc: fix not working in sequence mode and preemption mode - - ses: set obj path for common configuration. - - cmake: ses: put app source into separate category in ses. - -### Added: - - components: enet_phy: add rtl8211 driver - - components: hpm_spi: add initial SPI component - - components: add DMA Manager - - drivers: cam: add new API - - drivers: uart: add uart_set_baudrate API - - drivers: spi: update dma transfer API - - samples: tinyusb: host: add a hid demo - - samples: drivers: spi: add master_trans_large_amount_of_data example - - samples: decoder_wav: Add support for different bit rates and bits - - samples: drivers: audio: automatic acquisition of i2s clock frequency - - middleware: tinyusb: update portable file for USB host - -## [0.12.1] - 2022-07-01: - -Main changes since 0.12.0 - -### Fixed: - - update lwipopt.h for updated enet driver - -## [0.12.0] - 2022-06-30: - -Tested with SES 6.32 - -Main changes since 0.11.0 - -### Changed: - - boards: hpm6360evk has been renamed to hpm6300evk - - boards: Use CSR_CYCLE in the clock_delay function - - soc: hpm_soc.h: include hpm_common.h - - driver: rename hpm_pmu_drv.c to hpm_pcfg_drv.h - - driver: spi: change to non-blocking interfaces - - driver: dma: update driver to adapt to different DMA instance constraints - - components: enet_phy: update dp83867 driver - - components: enet_phy: remove rtl8211 driver - - cmake: enable nano newlib by default - - cmake: move distclean to the beginning - - middleware: littlevgl enable PDMA by default - - middleware: tinyusb: upgrade to 0.13.0 - - samples: tinyusb: device: cdc_msc: adjust buffer size - - samples: drivers: plic: use gpio toggle count as nested irq - -### Fixed: - - drivers: pwm: fix function name inconsistency bug - - drivers: enet: remove "board.h" in enet driver - - drivers: clock: Fix bugs in hpm6360 clock driver - - drivers: clock: returns wrong adc/dac clock in HPM6360 - - drivers: dram: failed to configure 8bit mode. - - freertos: fix issue about running on core1 - - boards: hpm6300evk pmp_entry set initial value - - middleware: littlevgl: fix pdma cache op issue - - middleware: littlevgl: fix doxygen markdown for pdma driver - - middleware: lvgl: ses: update ram linker. - - middleware: hpm_math: fix ffa cache size error - - samples: audio_codec: remove the wrong dependency - - samples: FATFS demo cannot support write/read if FATFS passes unaligned buffer address - -### Added: - - samples: add memstress and flash stress - - drivers: clock: add implement common delay function based on mcycle and mcycleh register - - boards: add hpm6300evk support - - boards: hpm6750evkmini: motor control support - - soc: add svd files - - middleware: lwip: iperf: enable iperf and add udp function - - samples: lwip: add lwip_iperf - -## [0.11.0] - 2022-05-31: -Main changes since 0.10.0-hpm6360-er - -### Changed: - - readme: change the location of the starting document - - components: change hal_adc_xx to hpm_adc_xx - - drivers: update the I2C driver - - cmake: change default rv_arch to rv32imac - - cmake: modified in a zephyr-compatible way - - drivers: uart: redefined struct with zephyr - - cmake: change soc and board name - - cmake: ses: support enable ext_dsp in project file. - - samples/tinyusb/host: optimize the toggle rate of the blinking led - - samples/tinyusb/device: replace mchtimer with board_timer for led_linking_taskk - - samples/tinyusb/device: optimize the implement of led_blinking_task - - soc: update IP header and soc header files - -### Fixed: - - samples: motor_ctrl: bldc_block: fix some error - - middleware: hpm_math: fix andes toolchain compile error - - middleware: hpm_math: fix libdsp.a error - - middleware: hpm_math: add ext-dsp for SES - - samples: openocd_algo: fix func_table placement. - - boards: hpm6360evk: correct cpu frequency - - boards: fix warning caused by code irregularities - - boards: LED status is not the same between hpm6750mini rev-A and rev-B - - boards: update board_led_write. - -### Added: - - driver: add spi_setup_dma_transfer() API - - middleware: hpm_math: add software fft function - - middleware: hpm_math: add ffa to hpm_math - - samples: i2c: update the sample b2b - - samples: hpm_math: add fft_performance demo - - samples: add SPI DMA sample - - samples: multicore coremark using debug console only - - samples: 1588: add ptp v1 master/slave - -## [0.10.0_hpm6300] - 2022-05-16: -Main changes since 0.10.0 - -### Changed: - - ip register header file update - - ses_proj: using generated complete cpu_regs_xml to replace general cpu registers xml - - drivers: gpiom: move gpiom_gpio_t into hpm_gpiom_src.h - - drivers: update the enet driver - - samples: dram: change sdram test address in dma demo - - samples: drivers: mbx: exclude flash targets for core0 as well. - - samples: lwip: update ethernetif.c - -### Fixed: - - drivers: ptpc: update ptpc_init_timer_with_initial. - - drivers: can: bug fix and update - - soc: correct vector table inclusion and swi name - - env.sh: fix HPM_SDK_BASE setting problem with msys. - - samples: sha256_example: failed to run case 13 and 14 with gcc. - -### Added: - - soc: add HPM6360 support - - drivers: add ffa, pllctlv2, dac - - boards: add hpm6360evk support - - components: add adcx module - - components/enet_phy: add the RTL8201 driver - - samples: drivers: dac, ffa - - samples: rgb_red: add evkmini ver B support - -## [0.10.0] - 2022-04-30: -Main changes since 0.9.0 - -### Changed: - - drivers: gptmr: split irq enable/disable interface - - drivers: can: 155 Update SJW setting in CAN driver - - soc: HPM6750: rename safe stack symbol in link script - - components: debug_console: wait uart tx flag on writing. - -### Added: - - drivers: enet: add 1588 support - - drivers: can: Add TDC support - - drivers: mchtmr: add counter init API. - - drivers: dma: add dma_disable_channel() API - - middleware: add wav decoder - - samples: lwip: add ptp demos - - samples: tinyusb: add msc, cdc demo - - samples: audio_codec: add wav player demo - - samples: add tinyuf2 initial support - - samples: add initial uart dma rx idle demo - -### Fixed: - - soc: HPM6750: sysctl: fix cpu lp mode API. - - drivers: uart: correct baudrate calculation. - - drivers: usb: fix: no response in device mode when a USB cable is pluged out - - boards: correct the pin setting related to USB - -## [0.9.0] - 2022-04-01: -Main changes since 0.8.0 - -### Changed: - - drivers: update WDG, UART, DMA, DMAMUX driver - - drivers: enet remove enet_intf_selection - - drivers: can: support configure bit timing via low-level bit timing parameters - - drivers: optimize gpio driver - - samples: exclude flash targets for mbx core1 - - samples: adjust SES project setting for coremark - - samples: jpeg: update and integration jpeg decode samples - - ses: use relpath for linker script in project file - - ses: add HPM device name in generated project file - - soc: HPM6750: add an interface selection api - -### Added: - - soc: HPM6750: add ram linker for core1 - - ses: support to use Andes toolchain - - middleware: add hpm_math (replacing hpm_dsp) - - samples: add lwip httpd - - drivers: add section and alignment general instructions in hpm_common.h - -### Fixed: - - boards: hpm6750evk: fix bldc adc pinmux error - - boards : hpm6750evk : pinmux : fix spi init pins error - - samples: sdp: fix non-cacheable data initialization issue - - samples: littlevgl: fix wrong picture patch in README - -## [0.8.0] - 2022-03-04: -All changes since 0.7.3 - -### Changed: - - rename middleware/sdmmc to middleware/hpm_sdmmc - - place isr into .isr_vector section for irq non-vector mode - - change csr functions to support llvm - -### Fixed: - - ses: fix issue in register xml - - freertor: fix trap handler at non-vector mode - - sdxc: fix software reset issue - -### Added: - - add sdk doc - - add more sample doc - - add multicore demo - - i2c/uart: add dma support - - add tensorflow lite for microcontroller - -## [0.7.3] - 2022-02-23: -All changes since 0.7.2 - -### Changed: - - freertos: change exception handling - -## [0.7.2] - 2022-02-21: -All changes since 0.7.1 - -### Changed: - - freertos: change freertos irq stack definition, passed in CMakeLists.txt, defined in linker - - soc: hpm6750: add DISABLE_IRQ_PREEMPTIVE to check if it needs to enable irq preemption - -### Fixed: - - freertos: disable irq preemption - -## [0.7.1] - 2022-02-13: - -All changes since 0.7.0 - -### Changed: - - drivers: adc12: update adc12_prd_config_t - - samples: can: update case with interrupt and communication between two boards - -### Fixed: - - drivers: can: fix blocking transcation issue - - samples: mbx: support run this example in SES - - SES: startup: add fpu enable if abi is set to enable hw fp - -### Added: - - samples: multicore: add flash based multicore example - - drivers: can: add apis to recvieve message for non-blocking use - -## [0.7.0] - 2022-01-30: - -All changes since 0.6.2 - -### Changed: - - update default CPU frequency to 816MHz from 648MHz - - update the ip headers - - drivers: gpio: replace gpio_XXX_pins with gpio_XXX_port - - drivers: gpio: remove pin level enum definition - - drivers: i2s: driver update to remove mclk_div - - drivers: ptpc: update driver - - drivers: common: update get first set bit API - - drivers: uart: split one enable with parameter into enable and disable interfaces - - drivers: pwm: change name of output_channel config API - - drivers: trgm: split separate API to enable/disable io output - - soc: HPM6750: initialize noncacheable data in startup - - soc: HPM6750: l1c: update fence.i call - - samples: hello_world: add LED flashing - - samples: littlevgl: remove lvgl example - -### Fixed: - - hpm6750evkmini: correct refresh cycle number of sdram - - hpm6750evkmini: Fix the SDRAM memory range issue in flash_sdram_xip linker file - - SES: remove no_relax option for linker, since segger has provide a patch to its ld for ses v6.10. - - drivers: gpio: fix read pin issue: - - drivers: usb: fix usb disconnection under linux environment - - drivers: sdxc: Fixed the compatibility issue on different SD/eMMC cards in the sdcard_fatfs demo - - drivers: gptmr: incorrect DMAEN configuration condition - - drivers: gptmr: clear CNTRST bit after set. - - SDK_DECLARE_EXT_ISR_M cannot work in the c++ file - - FreeRTOS: fix ISR_STACK setting - - components: touch: gt911: fix gpio write pin call - -### Added: - - SEG: add register definition file in generated embedded studio project - - samples: drivers: gpiom: Add example to demonstrate gpiom's function - - drivers: common: add macro to put data into noncacheable sections - - middleware: integrate lwip - diff --git a/bsp/hpmicro/libraries/hpm_sdk/LICENSE b/bsp/hpmicro/libraries/hpm_sdk/LICENSE deleted file mode 100644 index fcbba7dbefa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/LICENSE +++ /dev/null @@ -1,31 +0,0 @@ -BSD 3-Clause "New" or "Revised" License -https://spdx.org/licenses/BSD-3-Clause.html - -Copyright (c) 2021-2023, HPMicro. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, -this list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation -and/or other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its contributors -may be used to endorse or promote products derived from this software without -specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. - diff --git a/bsp/hpmicro/libraries/hpm_sdk/README.md b/bsp/hpmicro/libraries/hpm_sdk/README.md deleted file mode 100644 index 389c0384ebb..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/README.md +++ /dev/null @@ -1,50 +0,0 @@ -``` mermaid -gantt - title HPM SDK Release Plan - dateFormat YYYY-MM-DD - section Mainline Release - v1.5.0 :a1, 2024-01-01, 2024-03-31 - v1.6.0 :a2, 2024-04-01, 2024-06-30 - v1.7.0 :a3, 2024-07-01, 2024-09-30 - v1.8.0 :a4, 2024-10-01, 2024-12-31 -``` - -[中文](README_zh.md) - -# HPM SDK Overview -The HPM SDK Project is a software development kit based on HPMicro's MCUs, which supports a wide range of MCUs, based on the BSD license, including drivers, middleware and RTOS, such as littlevgl/ lwIP/ TinyUSB/ FreeRTOS, etc. It supports a large number of Boards. - -## SDK Directory Structure - -| Name | Description | -|--------|--------| -| /arch | cpu architecture | -| /boards | board support files | -| /cmake | cmake extensions | -| /components | software components | -| /docs | documentation | -| /drivers | low level driver files | -| /middleware | middleware files | -| /samples | sample source for drivers, middleware, components | -| /scripts | util scripts | -| /soc | SoC specific source | -| /utils | util source | - -## SDK Documentation -- Local: - SDK documentation can be built locally, once it's done, it can be accessed with the following entries: - - >/docs/index.html - - >/docs/index_zh.html - > Please refer to for [hpm_sdk Getting Started](docs/en/get_started.md) more details about documentation building. -- Online: - - http://hpm-sdk.readthedocs.io/ - - http://hpm-sdk-zh.readthedocs.io/ - -## Repositories -- hpm_sdk: https://github.com/hpmicro/hpm_sdk -- sdk_env: https://github.com/hpmicro/sdk_env -- sdk extra demo: https://github.com/hpmicro/hpm_sdk_extra -- openocd (hpmicro patched): https://github.com/hpmicro/riscv-openocd -- gnu gcc toolchain: https://github.com/hpmicro/riscv-gnu-toolchain - -> Note: repositories are mirrored on gitee. diff --git a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md b/bsp/hpmicro/libraries/hpm_sdk/README_zh.md deleted file mode 100644 index 22b86f655ad..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/README_zh.md +++ /dev/null @@ -1,50 +0,0 @@ -``` mermaid -gantt - title HPM SDK Release Plan - dateFormat YYYY-MM-DD - section Mainline Release - v1.5.0 :a1, 2024-01-01, 2024-03-31 - v1.6.0 :a2, 2024-04-01, 2024-06-30 - v1.7.0 :a3, 2024-07-01, 2024-09-30 - v1.8.0 :a4, 2024-10-01, 2024-12-31 -``` - -[English](README.md) - -# HPM SDK 概述 -HPM SDK项目是基于HPMicro 公司的MCU编写的软件开发包，支持多种MCU。基于BSD许可证，包含了底层驱动，中间件和RTOS，例如littlevgl/ lwIP/ TinyUSB/ FreeRTOS等，支持大量评估板。 - -## HPM SDK 目录结构 - -| 目录名称 | 描述 | -|--------|--------| -| /arch | cpu架构相关文件 | -| /boards | 板级文件 | -| /cmake | cmake扩展 | -| /components | 软件组件 | -| /docs | 文档 | -| /drivers | 底层驱动文件| -| /middleware | 中间件 | -| /samples | 驱动、中间件以及软件组件示例代码 | -| /scripts | 辅助脚本 | -| /soc | SoC相关文件 | -| /utils | 辅助文件 | - -## SDK文档 -- 本地文档: - SDK文档可以进行本地编译，成功编译之后可以通过以下入口访问本地文档: - - >/docs/index.html - - >/docs/index_zh.html - > 文档编译方式请参考[hpm_sdk Getting Started](docs/zh/get_started.md) -- 在线文档： - - http://hpm-sdk.readthedocs.io/ - - http://hpm-sdk-zh.readthedocs.io/ - -## 代码仓库 -- hpm_sdk github: https://github.com/hpmicro/hpm_sdk -- sdk_env github: https://github.com/hpmicro/sdk_env -- sdk extra demo: https://github.com/hpmicro/hpm_sdk_extra -- openocd (hpmicro patched): https://github.com/hpmicro/riscv-openocd -- gnu gcc toolchain: https://github.com/hpmicro/riscv-gnu-toolchain - -> 仓库在gitee上有对应的镜像。 diff --git a/bsp/hpmicro/libraries/hpm_sdk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/SConscript deleted file mode 100644 index be4f47acd28..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/SConscript +++ /dev/null @@ -1,128 +0,0 @@ -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd + '/arch', cwd + "/drivers/inc", cwd + '/soc/' + rtconfig.SOC_FAMILY + '/' + '/ip'] - -# The set of source files associated with this SConscript file. -src = [] - -CPPDEFINES=[] - -src += ['drivers/src/hpm_pmp_drv.c'] -src += ['drivers/src/hpm_pcfg_drv.c'] - -if rtconfig.SOC_FAMILY == "HPM6700": - src += ['drivers/src/hpm_pllctl_drv.c'] -else: - src += ['drivers/src/hpm_pllctlv2_drv.c'] - -if rtconfig.SOC_FAMILY == "HPM6700" or rtconfig.SOC_FAMILY == "HPM6300" or rtconfig.SOC_FAMILY == "HPM6200": - src += ['drivers/src/hpm_dma_drv.c'] -else: - src += ['drivers/src/hpm_dmav2_drv.c'] - CPPDEFINES = ['HPMSOC_HAS_HPMSDK_DMAV2'] - -if GetDepend(['BSP_USING_GPIO']): - src += ['drivers/src/hpm_gpio_drv.c'] - -if GetDepend(['BSP_USING_UART']): - src += ['drivers/src/hpm_uart_drv.c'] - -if GetDepend(['BSP_USING_I2C']): - src += ['drivers/src/hpm_i2c_drv.c'] - -if GetDepend(['BSP_USING_SPI']): - src += ['drivers/src/hpm_spi_drv.c'] - -if GetDepend(['BSP_USING_RTC']): - src += ['drivers/src/hpm_rtc_drv.c'] - -if GetDepend(['BSP_USING_WDG']): - src += ['drivers/src/hpm_wdg_drv.c'] - -if GetDepend(['BSP_USING_EWDG']): - src += ['drivers/src/hpm_ewdg_drv.c'] - -if GetDepend(['BSP_USING_ADC']): - if GetDepend(['BSP_USING_ADC12']): - src += ['drivers/src/hpm_adc12_drv.c'] - if GetDepend(['BSP_USING_ADC16']): - src += ['drivers/src/hpm_adc16_drv.c'] - -if GetDepend(['BSP_USING_CAN']): - src += ['drivers/src/hpm_can_drv.c'] - -if GetDepend(['BSP_USING_MCAN']): - src += ['drivers/src/hpm_mcan_drv.c'] - -if GetDepend(['BSP_USING_ETH']): - src += ['drivers/src/hpm_enet_drv.c'] - -if GetDepend(['BSP_USING_DMA']): - src += ['drivers/src/hpm_dma_drv.c'] - -if GetDepend(['BSP_USING_SDXC']): - src += ['drivers/src/hpm_sdxc_drv.c'] - -if GetDepend(['BSP_USING_LCD']): - src += ['drivers/src/hpm_lcdc_drv.c'] - -if GetDepend(['BSP_USING_GPTMR']) or GetDepend('HPM_USING_VECTOR_PREEMPTED_MODE'): - src += ['drivers/src/hpm_gptmr_drv.c'] - -if GetDepend(['BSP_USING_FEMC']): - src += ['drivers/src/hpm_femc_drv.c'] - -if GetDepend(['BSP_USING_PWM']): - src += ['drivers/src/hpm_pwm_drv.c'] - -if GetDepend(['BSP_USING_PWMV2']): - src += ['drivers/src/hpm_pwmv2_drv.c'] - -if GetDepend(['BSP_USING_USB']): - src += ['drivers/src/hpm_usb_drv.c'] - -if GetDepend(['BSP_USING_I2S']): - src += ['drivers/src/hpm_i2s_drv.c'] - -if GetDepend(['BSP_USING_PDM']): - src += ['drivers/src/hpm_pdm_drv.c'] - src += ['drivers/src/hpm_i2s_drv.c'] - -if GetDepend(['BSP_USING_DAO']): - src += ['drivers/src/hpm_dao_drv.c'] - src += ['drivers/src/hpm_i2s_drv.c'] - -if GetDepend(['BSP_USING_PDMA']): - src += ['drivers/src/hpm_pdma_drv.c'] - -if GetDepend(['BSP_USING_JPEG']): - src += ['drivers/src/hpm_jpeg_drv.c'] - -if GetDepend(['BSP_USING_CAM']): - src += ['drivers/src/hpm_cam_drv.c'] - -if GetDepend(['BSP_USING_PIXELMUX']): - src += ['drivers/src/hpm_pixelmux_drv.c'] - -if GetDepend(['BSP_USING_MIPI_CSI']): - src += ['drivers/src/hpm_mipi_csi_drv.c'] - src += ['drivers/src/hpm_mipi_csi_phy_drv.c'] - -if GetDepend(['BSP_USING_MIPI_DSI']): - src += ['drivers/src/hpm_mipi_dsi_drv.c'] - src += ['drivers/src/hpm_mipi_dsi_phy_drv.c'] - -if GetDepend(['BSP_USING_LVB']): - src += ['drivers/src/hpm_lvb_drv.c'] - -if GetDepend(['BSP_USING_LCB']): - src += ['drivers/src/hpm_lcb_drv.c'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/VERSION b/bsp/hpmicro/libraries/hpm_sdk/VERSION deleted file mode 100644 index e110767a670..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/VERSION +++ /dev/null @@ -1,5 +0,0 @@ -VERSION_MAJOR = 1 -VERSION_MINOR = 5 -PATCHLEVEL = 0 -VERSION_TWEAK = 0 -EXTRAVERSION = 0 diff --git a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h b/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h deleted file mode 100644 index 8cdaf950948..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/arch/riscv/riscv_core.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef RISCV_CORE_H -#define RISCV_CORE_H - -#include "hpm_common.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief write fp csr - * - * @param v value to be set - */ -#define write_fcsr(v) __asm volatile("fscsr %0" : : "r"(v)) - -/** - * @brief clear bits in csr - * - * @param csr_num specific csr - * @param bit bits to be cleared - */ -#define clear_csr(csr_num, bit) __asm volatile("csrc %0, %1" : : "i"(csr_num), "r"(bit)) - -/** - * @brief read and clear bits in csr - * - * @param csr_num specific csr - * @param bit bits to be cleared - * - * @return csr value before cleared - */ -#define read_clear_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrc %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) - -/** - * @brief read and set bits in csr - * - * @param csr_num specific csr - * @param bit bits to be set - * - * @return csr value before set - */ -#define read_set_csr(csr_num, bit) ({ volatile uint32_t v = 0; __asm volatile("csrrs %0, %1, %2" : "=r"(v) : "i"(csr_num), "r"(bit)); v; }) - -/** - * @brief set bits in csr - * - * @param csr_num specific csr - * @param bit bits to be set - */ -#define set_csr(csr_num, bit) __asm volatile("csrs %0, %1" : : "i"(csr_num), "r"(bit)) - -/** - * @brief write value to csr - * - * @param csr_num specific csr - * @param v value to be written - */ -#define write_csr(csr_num, v) __asm volatile("csrw %0, %1" : : "i"(csr_num), "r"(v)) - -/** - * @brief read value of specific csr - * - * @param csr_num specific csr - * - * @return csr value - */ -#define read_csr(csr_num) ({ uint32_t v; __asm volatile("csrr %0, %1" : "=r"(v) : "i"(csr_num)); v; }) - -/** - * @brief read fp csr - * - * @return fp csr value - */ -#define read_fcsr() ({ uint32_t v; __asm volatile("frcsr %0" : "=r"(v)); v; }) - -/** - * @brief execute fence.i - * - */ -#define fencei() __asm volatile("fence.i") - -/** - * @brief execute fence rw - * - */ -#define fencerw() __asm volatile("fence rw, rw") - -/** - * @brief execute fence iorw - * - */ -#define fenceiorw() __asm volatile("fence iorw, iorw") - -/** - * @brief enable fpu - */ -#define enable_fpu() read_set_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK) - -/** - * @brief disable fpu - */ -#define disable_fpu() read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_FS_MASK) - -/** - * @brief clear fcsr - */ -#define clear_fcsr() write_fcsr(0) - -#ifdef __cplusplus -} -#endif - - -#endif /* RISCV_CORE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript b/bsp/hpmicro/libraries/hpm_sdk/components/SConscript deleted file mode 100644 index 7d876325fe8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/SConscript +++ /dev/null @@ -1,118 +0,0 @@ -Import('rtconfig') -import os -from building import * - -#get current directory -cwd = GetCurrentDir() - -CPPDEFINES=[] - -# Update include path -path = [ os.path.join(cwd, 'debug_console'), os.path.join(cwd, 'touch'), os.path.join(cwd, 'usb'), os.path.join(cwd, 'dma_mgr')] - -# The set of source files associated with this SConscript file. -src = [] - -src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ] -src += [ os.path.join(cwd, 'dma_mgr', 'hpm_dma_mgr.c') ] - -if GetDepend(['BSP_USING_TOUCH_GT9xx']): - src += [os.path.join(cwd, 'touch', 'gt9xx', 'hpm_touch_gt9xx.c') ] - src += [os.path.join(cwd, 'touch', 'gt9xx', 'hpm_gt9xx.c') ] - path += [ os.path.join(cwd, 'touch', 'gt9xx') ] - CPPDEFINES += ['CONFIG_TOUCH_GT9XX=1'] -if GetDepend(['BSP_USING_TOUCH_FT5406']): - src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_touch_ft5406.c') ] - src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_ft5406.c') ] - path += [ os.path.join(cwd, 'touch', 'ft5406') ] - CPPDEFINES += ['CONFIG_TOUCH_FT5406=1'] -if GetDepend(['BSP_USING_USB_DEVICE']): - src += [ os.path.join(cwd, 'usb', 'device', 'hpm_usb_device.c') ] - path += [ os.path.join(cwd, 'usb', 'device') ] -if GetDepend(['BSP_USING_USB_HOST']): - src += [ os.path.join(cwd, 'usb', 'host', 'hpm_usb_host.c') ] - path += [ os.path.join(cwd, 'usb', 'host') ] - CPPDEFINES += ['USB_HOST_MCU_CORE=HPM_CORE0'] -if GetDepend(['BSP_USING_ETH0']): - if GetDepend(['BSP_USING_ENET_PHY_DP83867']): - src += [ os.path.join(cwd, 'enet_phy/dp83867/hpm_dp83867.c') ] - path += [ os.path.join(cwd, 'enet_phy') ] - path += [ os.path.join(cwd, 'enet_phy/dp83867') ] - CPPDEFINES += ['__USE_DP83867=1'] -if GetDepend(['BSP_USING_ETH1']): - if GetDepend(['BSP_USING_ENET_PHY_DP83848']): - src += [ os.path.join(cwd, 'enet_phy/dp83848/hpm_dp83848.c') ] - path += [ os.path.join(cwd, 'enet_phy') ] - path += [ os.path.join(cwd, 'enet_phy/dp83848') ] - CPPDEFINES += ['__USE_DP83848=1'] -if GetDepend(['BSP_USING_ETH0']): - if GetDepend(['BSP_USING_ENET_PHY_RTL8211']): - src += [ os.path.join(cwd, 'enet_phy/rtl8211/hpm_rtl8211.c') ] - path += [ os.path.join(cwd, 'enet_phy') ] - path += [ os.path.join(cwd, 'enet_phy/rtl8211') ] - CPPDEFINES += ['__USE_RTL8211=1'] - if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): - src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] - path += [ os.path.join(cwd, 'enet_phy') ] - path += [ os.path.join(cwd, 'enet_phy/rtl8201') ] - CPPDEFINES += ['__USE_RTL8201=1'] -if GetDepend(['BSP_USING_ETH1']): - if GetDepend(['BSP_USING_ENET_PHY_RTL8201']): - src += [ os.path.join(cwd, 'enet_phy/rtl8201/hpm_rtl8201.c') ] - path += [ os.path.join(cwd, 'enet_phy') ] - path += [ os.path.join(cwd, 'enet_phy/rtl8201') ] - CPPDEFINES += ['__USE_RTL8201=1'] - if GetDepend(['BSP_USING_ENET_PHY_LAN8720']): - src += [ os.path.join(cwd, 'enet_phy/lan8720/hpm_lan8720.c') ] - path += [ os.path.join(cwd, 'enet_phy') ] - path += [ os.path.join(cwd, 'enet_phy/lan8720') ] - CPPDEFINES += ['__USE_LAN8720=1'] -if GetDepend(['BSP_USING_CAMERA']): - path += [ os.path.join(cwd, 'camera') ] -if GetDepend(['BSP_USING_CAMERA_MT9M114']): - src += [os.path.join(cwd, 'camera', 'mt9m114', 'hpm_mt9m114.c') ] - src += [os.path.join(cwd, 'camera', 'mt9m114', 'hpm_camera_mt9m114.c') ] - path += [ os.path.join(cwd, 'camera', 'mt9m114') ] - CPPDEFINES += ['CONFIG_CAMERA_MT9M114=1'] -if GetDepend(['BSP_USING_CAMERA_OV5640']): - src += [os.path.join(cwd, 'camera', 'ov5640', 'hpm_camera_ov5640.c') ] - src += [os.path.join(cwd, 'camera', 'ov5640', 'hpm_ov5640.c') ] - path += [ os.path.join(cwd, 'camera', 'ov5640') ] - CPPDEFINES += ['CONFIG_CAMERA_OV5640=1'] -if GetDepend(['BSP_USING_CAMERA_OV7725']): - src += [os.path.join(cwd, 'camera', 'ov7725', 'hpm_camera_ov7725.c') ] - src += [os.path.join(cwd, 'camera', 'ov7725', 'hpm_ov7725.c') ] - path += [ os.path.join(cwd, 'camera', 'ov7725') ] - CPPDEFINES += ['CONFIG_CAMERA_OV7725=1'] -if GetDepend(['BSP_USING_PANEL']): - path += [ os.path.join(cwd, 'panel') ] - src += [os.path.join(cwd, 'panel', 'hpm_panel.c') ] - CPPDEFINES += ['CONFIG_HPM_PANEL'] -if GetDepend(['BSP_USEING_PANEL_RGB_TM070RDH13']): - src += [os.path.join(cwd, 'panel', 'panels', 'tm070rdh13.c') ] - path += [ os.path.join(cwd, 'panel', 'panels') ] - CPPDEFINES += ['PANEL_SIZE_WIDTH=800'] - CPPDEFINES += ['PANEL_SIZE_HEIGHT=480'] - CPPDEFINES += ['CONFIG_PANEL_RGB_TM070RDH13=1'] -if GetDepend(['BSP_USEING_PANEL_MIPI_MC10128007_31B']): - src += [os.path.join(cwd, 'panel', 'panels', 'mc10128007_31b.c') ] - path += [ os.path.join(cwd, 'panel', 'panels') ] - CPPDEFINES += ['PANEL_SIZE_WIDTH=800'] - CPPDEFINES += ['PANEL_SIZE_HEIGHT=1280'] - CPPDEFINES += ['CONFIG_PANEL_MIPI_MC10128007_31B=1'] -if GetDepend(['BSP_USEING_PANEL_LVDS_TM103XDGP01']): - src += [os.path.join(cwd, 'panel', 'panels', 'tm103xdgp01.c') ] - path += [ os.path.join(cwd, 'panel', 'panels') ] - CPPDEFINES += ['PANEL_SIZE_WIDTH=1920'] - CPPDEFINES += ['PANEL_SIZE_HEIGHT=720'] - CPPDEFINES += ['CONFIG_PANEL_LVDS_TM103XDGP01=1'] -if GetDepend(['BSP_USEING_PANEL_LVDS_CC10128007']): - src += [os.path.join(cwd, 'panel', 'panels', 'cc10128007.c') ] - path += [ os.path.join(cwd, 'panel', 'panels') ] - CPPDEFINES += ['PANEL_SIZE_WIDTH=800'] - CPPDEFINES += ['PANEL_SIZE_HEIGHT=1280'] - CPPDEFINES += ['CONFIG_PANEL_LVDS_CC10128007=1'] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h b/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h deleted file mode 100644 index 2aaafaaf08f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/adc/hpm_adc.h +++ /dev/null @@ -1,626 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ADC_H -#define HPM_ADC_H - -#include "hpm_common.h" -#ifdef HPMSOC_HAS_HPMSDK_ADC12 -#include "hpm_adc12_drv.h" -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 -#include "hpm_adc16_drv.h" -#endif -#include "hpm_soc_feature.h" -/** - * @brief ADC HAL driver APIs - * @defgroup hpm_adc_interface HPM ADC driver APIs - * @ingroup hpm_adc_interfaces - * @{ - */ - -/** - * @brief An ADC peripheral base address. - * - */ -typedef union { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - ADC12_Type *adc12; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - ADC16_Type *adc16; -#endif -} adc_base; - -/** - * @brief use adc12 or adc16. - * - */ -#define ADCX_MODULE_ADC12 1 -#define ADCX_MODULE_ADC16 2 - -typedef enum { - adc_module_adc12 = ADCX_MODULE_ADC12, - adc_module_adc16 = ADCX_MODULE_ADC16 -} adc_module; - -/** - * @brief ADC common configuration struct. - * - */ -typedef struct { - adc_module module; - adc_base adc_base; - struct { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_config_t adc12; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_config_t adc16; -#endif - } config; -} adc_config_t; - -/** - * @brief ADC channel configuration struct. - * - */ -typedef struct { - adc_module module; - adc_base adc_base; - struct { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_channel_config_t adc12_ch; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_channel_config_t adc16_ch; -#endif - } config; -} adc_channel_config_t; - -/** - * @brief ADC DMA configuration struct. - * - */ -typedef struct { - adc_module module; - adc_base adc_base; - struct { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_dma_config_t adc12; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_dma_config_t adc16; -#endif - } config; -} adc_dma_config_t; - -/** - * @brief ADC configuration struct for period mode. - * - */ -typedef struct { - adc_module module; - adc_base adc_base; - struct { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_prd_config_t adc12; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_prd_config_t adc16; -#endif - } config; -} adc_prd_config_t; - -/** - * @brief ADC configuration struct for sequence mode. - * - */ -typedef struct { - adc_module module; - adc_base adc_base; - struct { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_seq_config_t adc12; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_seq_config_t adc16; -#endif - } config; -} adc_seq_config_t; - -/** - * @brief ADC trigger configuration struct for preempt mode. - * - */ -typedef struct { - adc_module module; - adc_base adc_base; - struct { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_pmt_config_t adc12; -#endif -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_pmt_config_t adc16; -#endif - } config; -} adc_pmt_config_t; - - -typedef struct { - adc_module module; - adc_base adc_base; -} adc_type; - - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get a default configuration for an ADC instance. - * - * @param[out] config A pointer to the configuration struct of "adc_config_t". - * - */ -static inline void hpm_adc_init_default_config(adc_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_get_default_config(&config->config.adc12); -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_get_default_config(&config->config.adc16); -#endif - } -} - -/** - * @brief Get a default configuration for an ADC channel instance. - * - * @param[out] config A pointer to the configuration struct of "adc_channel_config_t". - * - */ -static inline void hpm_adc_init_channel_default_config(adc_channel_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_get_channel_default_config(&config->config.adc12_ch); -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_get_channel_default_config(&config->config.adc16_ch); -#endif - } -} - -/** - * @brief Initialize an ADC instance. - * - * @param[in] config A pointer to the configuration struct of "adc_config_t". - * @retval status_success Initialize an ADC instance successfully. - * @retval status_invalid_argument Initialize an ADC instance unsuccessfully because of passing one or more invalid arguments. - */ -static inline hpm_stat_t hpm_adc_init(adc_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_init(config->adc_base.adc12, &config->config.adc12); -#else - return status_invalid_argument; -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_init(config->adc_base.adc16, &config->config.adc16); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Initialize an ADC channel. - * - * @param[in] config A pointer to the configuration struct of "adc_config_t". - * @retval status_success Initialize an ADC instance successfully. - * @retval status_invalid_argument Initialize an ADC instance unsuccessfully because of passing one or more invalid arguments. - */ -static inline hpm_stat_t hpm_adc_channel_init(adc_channel_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_init_channel(config->adc_base.adc12, &config->config.adc12_ch); -#else - return status_invalid_argument; -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_init_channel(config->adc_base.adc16, &config->config.adc16_ch); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Configure the periodic mode for an ADC instance. - * - * @param[in] config A pointer to the configuration struct of "adc_prd_config_t". - * @retval status_success Configure the periodic mode for an ADC instance successfully. - * @retval status_invalid_argument Configure the periodic mode for an ADC instance unsuccessfully because of passing one or more invalid arguments. - * - */ -static inline hpm_stat_t hpm_adc_set_period_config(adc_prd_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_set_prd_config(config->adc_base.adc12, &config->config.adc12); -#else - return status_invalid_argument; -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_set_prd_config(config->adc_base.adc16, &config->config.adc16); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Configure the sequence mode for an ADC instance. - * - * @param[in] config A pointer to configuration struct of "adc_seq_config_t". - * @retval status_success Configure the sequence mode for an ADC instance successfully. - * @retval status_invalid_argument Configure the sequence mode for an ADC instance unsuccessfully because of passing one or more invalid arguments. - */ -static inline hpm_stat_t hpm_adc_set_sequence_config(adc_seq_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_set_seq_config(config->adc_base.adc12, &config->config.adc12); -#else - return status_invalid_argument; -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_set_seq_config(config->adc_base.adc16, &config->config.adc16); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Configure the preemption mode for an ADC instance. - * - * @param[in] config a pointer to configuration struct of "adc_pmt_config_t". - * @retval status_success Configure the preemption mode for an ADC instance successfully. - * @retval status_invalid_argument Configure the preemption mode for an ADC instance unsuccessfully because of passing one or more invalid arguments. - */ -static inline hpm_stat_t hpm_adc_set_preempt_config(adc_pmt_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_set_pmt_config(config->adc_base.adc12, &config->config.adc12); -#else - return status_invalid_argument; -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_set_pmt_config(config->adc_base.adc16, &config->config.adc16); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Configure the stop position offset in the specified memory for DMA write operation for sequence mode. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] stop_pos The stop position offset. - */ -static inline void hpm_adc_set_seq_stop_pos(adc_type *ptr, uint16_t stop_pos) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_set_seq_stop_pos(ptr->adc_base.adc12, stop_pos); -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_set_seq_stop_pos(ptr->adc_base.adc16, stop_pos); -#endif - } -} - -/** - * @brief Configure the start address of DMA write operation for preemption mode. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] addr The start address of DMA write operation. - */ -static inline void hpm_adc_init_pmt_dma(adc_type *ptr, uint32_t addr) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_init_pmt_dma(ptr->adc_base.adc12, addr); -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_init_pmt_dma(ptr->adc_base.adc16, addr); -#endif - } -} - -/** - * @brief Configure the start address of DMA write operation for preemption mode. - * - * @param[in] config A pointer to configuration struct of "adc_dma_config_t". - */ -static inline void hpm_adc_init_seq_dma(adc_dma_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_init_seq_dma(config->adc_base.adc12, &config->config.adc12); -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_init_seq_dma(config->adc_base.adc16, &config->config.adc16); -#endif - } -} - -/** - * @brief Reset value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus - * until the ADC completes the conversion. - * - * @param[in] config A pointer to configuration struct of "adc_dma_config_t". - */ -static inline void hpm_adc_disable_busywait(adc_dma_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_disable_busywait(config->adc_base.adc12); -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_disable_busywait(config->adc_base.adc16); -#endif - } -} - -/** - * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus - * until the ADC has completed its conversion. - * - * @param[in] config A pointer to configuration struct of "adc_dma_config_t". - */ -static inline void hpm_adc_enable_busywait(adc_dma_config_t *config) -{ - if (config->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_enable_busywait(config->adc_base.adc12); -#endif - } else if (config->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_enable_busywait(config->adc_base.adc16); -#endif - } -} - - -/** - * @brief Get ADC status flags. - * - * This function gets all ADC status flags. - * @param[in] ptr An ADC peripheral base address. - * @retval Status The ADC interrupt status flags. - */ -static inline uint32_t hpm_adc_get_status_flags(adc_type *ptr) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_get_status_flags(ptr->adc_base.adc12); -#else - return status_invalid_argument; -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_get_status_flags(ptr->adc_base.adc16); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Get status flag of a conversion. - * - * This status flag is only used when wait_dis is set to disable. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] ch An ADC peripheral channel. - * @retval Status It means the current conversion is valid. - */ -static inline bool hpm_adc_get_conv_valid_status(adc_type *ptr, uint8_t ch) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_get_conv_valid_status(ptr->adc_base.adc12, ch); -#else - return status_invalid_argument; -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_get_conv_valid_status(ptr->adc_base.adc16, ch); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Clear status flags. - * - * Only the specified flags can be cleared by writing INT_STS register. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] mask Mask value for flags to be cleared. Refer to "adc12_irq_event_t". Refer to "adc16_irq_event_t". - */ -static inline void hpm_adc_clear_status_flags(adc_type *ptr, uint32_t mask) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_clear_status_flags(ptr->adc_base.adc12, mask); -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_clear_status_flags(ptr->adc_base.adc16, mask); -#endif - } -} - -/** - * @brief Enable interrupts. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] mask Mask value for interrupt events. Refer to "adc12_irq_event_t".Refer to "adc16_irq_event_t". - */ -static inline void hpm_adc_enable_interrupts(adc_type *ptr, uint32_t mask) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_enable_interrupts(ptr->adc_base.adc12, mask); -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_enable_interrupts(ptr->adc_base.adc16, mask); -#endif - } -} - -/** - * @brief Disable interrupts. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] mask Mask value for interrupt events. Refer to "adc12_irq_event_t".Refer to "adc16_irq_event_t". - */ -static inline void hpm_adc_disable_interrupts(adc_type *ptr, uint32_t mask) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - adc12_disable_interrupts(ptr->adc_base.adc12, mask); -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - adc16_disable_interrupts(ptr->adc_base.adc16, mask); -#endif - } -} - -/** - * @brief Get the result in oneshot mode. - * - * @param[in] ptr An ADC peripheral base address. - * @param[in] ch An ADC peripheral channel. - * @param[out] result The result of an ADC12 conversion. - * - * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. - * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully because of passing invalid arguments. - */ -static inline hpm_stat_t hpm_adc_get_oneshot_result(adc_type *ptr, uint8_t ch, uint16_t *result) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_get_oneshot_result(ptr->adc_base.adc12, ch, result); -#else - return status_invalid_argument; -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_get_oneshot_result(ptr->adc_base.adc16, ch, result); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Get the result in periodic mode. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] ch An ADC12 peripheral channel. - * @param[out] result The result of an ADC12 conversion. - * - * @retval status_success Get the result of an ADC12 conversion in periodic mode successfully. - * @retval status_invalid_argument Get the result of an ADC12 conversion in periodic mode unsuccessfully because of passing invalid arguments. - */ -static inline hpm_stat_t hpm_adc_get_prd_result(adc_type *ptr, uint8_t ch, uint16_t *result) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_get_prd_result(ptr->adc_base.adc12, ch, result); -#else - return status_invalid_argument; -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_get_prd_result(ptr->adc_base.adc16, ch, result); -#else - return status_invalid_argument; -#endif - } else { - return status_invalid_argument; - } -} - -/** - * @brief Do a software trigger for sequence mode. - * - * @param[in] ptr An adc peripheral base address. - * - */ -static inline hpm_stat_t hpm_adc_trigger_seq_by_sw(adc_type *ptr) -{ - if (ptr->module == adc_module_adc12) { -#ifdef HPMSOC_HAS_HPMSDK_ADC12 - return adc12_trigger_seq_by_sw(ptr->adc_base.adc12); -#endif - } else if (ptr->module == adc_module_adc16) { -#ifdef HPMSOC_HAS_HPMSDK_ADC16 - return adc16_trigger_seq_by_sw(ptr->adc_base.adc16); -#endif - } else { - return status_invalid_argument; - } -} - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h deleted file mode 100644 index e55587bf4da..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_CAMERA_H -#define HPM_CAMERA_H - -#if defined(CONFIG_CAMERA_OV7725) && CONFIG_CAMERA_OV7725 -#include "hpm_ov7725.h" -#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV7725_ACTIVE_IMAGE_WIDTH -#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV7725_ACTIVE_IMAGE_HEIGHT -#define CAMERA_DEVICE_ADDR OV7725_I2C_ADDR -#elif defined(CONFIG_CAMERA_OV5640) && CONFIG_CAMERA_OV5640 -#include "hpm_ov5640.h" -#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH OV5640_ACTIVE_IMAGE_WIDTH -#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT OV5640_ACTIVE_IMAGE_HEIGHT -#define CAMERA_DEVICE_ADDR OV5640_I2C_ADDR -#elif defined(CONFIG_CAMERA_MT9M114) && CONFIG_CAMERA_MT9M114 -#include "hpm_mt9m114.h" -#define CAMERA_MAX_IMAGE_OUTPUT_WIDTH MT9M114_ACTIVE_IMAGE_WIDTH -#define CAMERA_MAX_IMAGE_OUTPUT_HEIGHT MT9M114_ACTIVE_IMAGE_HEIGHT -#define CAMERA_DEVICE_ADDR MT9M114_I2C_ADDR -#else -#error "unknown camera type, either have CONFIG_CAMERA_OV7725 or CONFIG_CAMERA_OV5640 defined" -#endif - - -#endif /* HPM_CAMERA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h deleted file mode 100644 index 77872164d94..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/hpm_camera_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_CAMERA_CONFIG_H -#define HPM_CAMERA_CONFIG_H - -#include "hpm_common.h" -#include "hpm_display_common.h" -#include "hpm_i2c_drv.h" - -/* Macro to define video resolution. */ -#define HPM_CAMERA_RESOLUTION(width, height) ((uint32_t)(width) | ((uint32_t)(height) << 16U)) - -typedef struct { - I2C_Type *ptr; - void (*delay_ms)(uint32_t ms); - void (*write_rst)(uint8_t state); - void (*write_pwdn)(uint8_t state); - uint16_t i2c_device_addr; -} camera_context_t; - -typedef struct { - bool hsync_active_low; - bool vsync_active_low; -} camera_param_dvp_t; - -typedef struct { - bool de_active_low; - bool hsync_active_low; - bool vsync_active_low; -} camera_param_mipi_t; - -typedef enum { - camera_interface_dvp, - camera_interface_mipi, -} camera_interface_t; - -typedef struct { - uint32_t width; - uint32_t height; - display_pixel_format_t pixel_format; - camera_interface_t interface; - void *interface_param; -} camera_config_t; - -/* Video Resolution definition. */ -typedef enum { - video_resolution_5mp = HPM_CAMERA_RESOLUTION(2592, 1944), /* 5MP, 2592 * 1944 */ - video_resolution_sxga = HPM_CAMERA_RESOLUTION(1280, 800), /* SXGA, 1280 * 800 */ - video_resolution_1080p = HPM_CAMERA_RESOLUTION(1920, 1080), /* 1080P, 1920 * 1280*/ - video_resolution_720p = HPM_CAMERA_RESOLUTION(1280, 720), /* 720P, 1280 * 720 */ - video_resolution_800_480 = HPM_CAMERA_RESOLUTION(800, 480), /* 640 * 480 */ - video_resolution_vga = HPM_CAMERA_RESOLUTION(640, 480), /* VGA, 640 * 480 */ - video_resolution_480_272 = HPM_CAMERA_RESOLUTION(480, 272), /* 480 * 272 */ - video_resolution_qvga = HPM_CAMERA_RESOLUTION(320, 240), /* QVGA, 320 * 240 */ -} camera_resolution_t; - -/* Camera light mode type. */ -typedef enum { - camera_light_mode_auto = 0, - camera_light_mode_sunny, - camera_light_mode_cloudy, - camera_light_mode_office, - camera_light_mode_home, - camera_light_mode_night, -} camera_light_mode_t; - -/* Camera special effect type. */ -typedef enum { - camera_special_effect_normal = 0, /* Normal. */ - camera_special_effect_bw, /* B & W */ - camera_special_effect_sepia, /* Sepia. */ - camera_special_effect_bluish, /* Bluish. */ - camera_special_effect_redish, /* Redish. */ - camera_special_effect_greenish, /* Greenish. */ - camera_special_effect_negtive, /* Negtive. */ - camera_special_effect_over_exposure, /* OverExposure. */ - camera_special_effect_solarize, /* Solarize. */ -} camera_special_effect_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * camera device initialization - */ -hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config); -hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config); -hpm_stat_t camera_device_get_mipi_param(camera_context_t *camera_context, camera_config_t *camera_config); - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CAMERA_CONFIG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c deleted file mode 100644 index b6c12e37bbe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_camera_mt9m114.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mt9m114.h" - -static camera_param_dvp_t camera_dvp_param = { - .hsync_active_low = true, - .vsync_active_low = true, -}; - -hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) -{ - assert(camera_context->delay_ms != NULL); - - hpm_stat_t stat = status_success; - - /* first check chipid */ - stat = mt9m114_check_chip_id(camera_context); - if (stat != status_success) { - return stat; - } - - /* software reset */ - stat = mt9m114_software_reset(camera_context); - if (stat != status_success) { - return stat; - } - camera_context->delay_ms(20); - - stat = mt9m114_init(camera_context, camera_config); - - return stat; -} - -hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) -{ - camera_config->interface_param = (void *)&camera_dvp_param; - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c deleted file mode 100644 index 9571a8f6399..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.c +++ /dev/null @@ -1,484 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mt9m114.h" -#include "board.h" -#include "hpm_clock_drv.h" -#include - -#if defined(MT9M114_SHOW_DEBUG_INFO) && MT9M114_SHOW_DEBUG_INFO -#define DEBUG_INFO(...) printf(__VA_ARGS__) -#else -#define DEBUG_INFO(...) -#endif - -#if MT9M114_ERROR_ACTION_BLOCK -#define ERROR_ACTION() do { \ - DEBUG_INFO("[ERROR]:%s %d\n", __func__, __LINE__); \ - for (;;) { \ - } \ - } while (0) -#else -#define ERROR_ACTION() return (status_fail) -#endif - -const mt9m114_reg_t mt9m114_vga[] = { - {MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_START, 2, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ - {MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_START, 2, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ - {MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_END, 2, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 973 */ - {MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_END, 2, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1293 */ - {MT9M114_VAR_CAM_SENSOR_CFG_CPIPE_LAST_ROW, 2, 0x01E3}, /* cam_sensor_cfg_cpipe_last_row = 483 */ - {MT9M114_VAR_CAM_CROP_WINDOW_WIDTH, 2, 0x0280}, /* cam_crop_window_width = 640 */ - {MT9M114_VAR_CAM_CROP_WINDOW_HEIGHT, 2, 0x01E0}, /* cam_crop_window_height = 480 */ - {MT9M114_VAR_CAM_OUTPUT_WIDTH, 2, 0x0280}, /* cam_output_width = 640 */ - {MT9M114_VAR_CAM_OUTPUT_HEIGHT, 2, 0x01E0}, /* cam_output_height = 480 */ - {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XEND, 2, 0x027F}, /* cam_stat_awb_clip_window_xend = 639 */ - {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YEND, 2, 0x01DF}, /* cam_stat_awb_clip_window_yend = 479 */ - {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XEND, 2, 0x007F}, /* cam_stat_ae_initial_window_xend = 127 */ - {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YEND, 2, 0x005F}, /* cam_stat_ae_initial_window_yend = 95 */ -}; - -const mt9m114_reg_t mt9m114_init_config[] = { - {MT9M114_REG_LOGICAL_ADDRESS_ACCESS, 2u, 0x1000}, - /* PLL Fout = (Fin * 2 * m) / ((n + 1) * (p + 1)) */ - {MT9M114_VAR_CAM_SYSCTL_PLL_ENABLE, 1u, 0x01}, /* cam_sysctl_pll_enable = 1 */ - {MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_M_N, 2u, 0x0120}, /* cam_sysctl_pll_divider_m_n = 288 */ - {MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_P, 2u, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ - {MT9M114_VAR_CAM_SENSOR_CFG_PIXCLK, 4u, 0x2DC6C00}, /* cam_sensor_cfg_pixclk = 48000000 */ - {0x316A, 2, 0x8270}, /* auto txlo_row for hot pixel and linear full well optimization */ - {0x316C, 2, 0x8270}, /* auto txlo for hot pixel and linear full well optimization */ - {0x3ED0, 2, 0x2305}, /* eclipse setting, ecl range=1, ecl value=2, ivln=3 */ - {0x3ED2, 2, 0x77CF}, /* TX_hi=12 */ - {0x316E, 2, 0x8202}, /* auto ecl , threshold 2x, ecl=0 at high gain, ecl=2 for low gain */ - {0x3180, 2, 0x87FF}, /* enable delta dark */ - {0x30D4, 2, 0x6080}, /* disable column correction due to AE oscillation problem */ - {0xA802, 2, 0x0008}, /* RESERVED_AE_TRACK_02 */ - {0x3E14, 2, 0xFF39}, /* Enabling pixout clamping to VAA during ADC streaming to solve column band issue */ - /* APGA */ - {0xC95E, 2u, 0x0000}, - - {MT9M114_VAR_CAM_SENSOR_CFG_ROW_SPEED, 2u, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ - {MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN, 2u, 0x01C3}, /* cam_sensor_cfg_fine_integ_time_min = 451 */ - {MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX, 2u, 0x03BA}, /* cam_sensor_cfg_fine_integ_time_max = 954 */ - {MT9M114_VAR_CAM_SENSOR_CFG_FRAME_LENGTH_LINES, 2u, 0x02DE}, /* cam_sensor_cfg_frame_length_lines = 734 */ - {MT9M114_VAR_CAM_SENSOR_CFG_LINE_LENGTH_PCK, 2u, 0x04A5}, /* cam_sensor_cfg_line_length_pck = 1189 */ - {MT9M114_VAR_CAM_SENSOR_CFG_FINE_CORRECTION, 2u, 0x00E0}, /* cam_sensor_cfg_fine_correction = 224 */ - {MT9M114_VAR_CAM_SENSOR_CFG_REG_0_DATA, 2u, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ - {MT9M114_VAR_CAM_SENSOR_CONTROL_READ_MODE, 2u, 0x0332}, /* cam_sensor_control_read_mode = 816 */ - {MT9M114_VAR_CAM_CROP_WINDOW_XOFFSET, 2u, 0x0000}, /* cam_crop_window_xoffset = 0 */ - {MT9M114_VAR_CAM_CROP_WINDOW_YOFFSET, 2u, 0x0000}, /* cam_crop_window_yoffset = 0 */ - {MT9M114_VAR_CAM_CROP_CROPMODE, 1u, 0x03}, /* cam_crop_cropmode = 3 */ - {MT9M114_VAR_CAM_AET_AEMODE, 1u, 0x00}, /* cam_aet_aemode = 0 */ - {MT9M114_VAR_CAM_AET_MAX_FRAME_RATE, 2u, 0x3700}, /* cam_aet_max_frame_rate = 14080 */ - {MT9M114_VAR_CAM_AET_MIN_FRAME_RATE, 2u, 0x3700}, /* cam_aet_min_frame_rate = 14080 */ - - /* Camera control module */ - {0xC892, 2u, 0x0267}, - {0xC894, 2u, 0xFF1A}, - {0xC896, 2u, 0xFFB3}, - {0xC898, 2u, 0xFF80}, - {0xC89A, 2u, 0x0166}, - {0xC89C, 2u, 0x0003}, - {0xC89E, 2u, 0xFF9A}, - {0xC8A0, 2u, 0xFEB4}, - {0xC8A2, 2u, 0x024D}, - {0xC8A4, 2u, 0x01BF}, - {0xC8A6, 2u, 0xFF01}, - {0xC8A8, 2u, 0xFFF3}, - {0xC8AA, 2u, 0xFF75}, - {0xC8AC, 2u, 0x0198}, - {0xC8AE, 2u, 0xFFFD}, - {0xC8B0, 2u, 0xFF9A}, - {0xC8B2, 2u, 0xFEE7}, - {0xC8B4, 2u, 0x02A8}, - {0xC8B6, 2u, 0x01D9}, - {0xC8B8, 2u, 0xFF26}, - {0xC8BA, 2u, 0xFFF3}, - {0xC8BC, 2u, 0xFFB3}, - {0xC8BE, 2u, 0x0132}, - {0xC8C0, 2u, 0xFFE8}, - {0xC8C2, 2u, 0xFFDA}, - {0xC8C4, 2u, 0xFECD}, - {0xC8C6, 2u, 0x02C2}, - {0xC8C8, 2u, 0x0075}, - {0xC8CA, 2u, 0x011C}, - {0xC8CC, 2u, 0x009A}, - {0xC8CE, 2u, 0x0105}, - {0xC8D0, 2u, 0x00A4}, - {0xC8D2, 2u, 0x00AC}, - {0xC8D4, 2u, 0x0A8C}, - {0xC8D6, 2u, 0x0F0A}, - {0xC8D8, 2u, 0x1964}, - - /* Automatic White balance */ - {MT9M114_VAR_CAM_AWB_AWB_XSHIFT_PRE_ADJ, 2u, 0x0033}, - {MT9M114_VAR_CAM_AWB_AWB_YSHIFT_PRE_ADJ, 2u, 0x003C}, - {MT9M114_VAR_CAM_AWB_AWB_XSCALE, 1u, 0x03}, - {MT9M114_VAR_CAM_AWB_AWB_YSCALE, 1u, 0x02}, - {0xC8F4, 2u, 0x0000}, - {0xC8F6, 2u, 0x0000}, - {0xC8F8, 2u, 0x0000}, - {0xC8FA, 2u, 0xE724}, - {0xC8FC, 2u, 0x1583}, - {0xC8FE, 2u, 0x2045}, - {0xC900, 2u, 0x03FF}, - {0xC902, 2u, 0x007C}, - {0xC90C, 1u, 0x80}, - {0xC90D, 1u, 0x80}, - {0xC90E, 1u, 0x80}, - {0xC90F, 1u, 0x88}, - {0xC910, 1u, 0x80}, - {0xC911, 1u, 0x80}, - - /* CPIPE Preference */ - {0xC926, 2u, 0x0020}, - {0xC928, 2u, 0x009A}, - {0xC946, 2u, 0x0070}, - {0xC948, 2u, 0x00F3}, - {0xC944, 1u, 0x20}, - {0xC945, 1u, 0x9A}, - {0xC92A, 1u, 0x80}, - {0xC92B, 1u, 0x4B}, - {0xC92C, 1u, 0x00}, - {0xC92D, 1u, 0xFF}, - {0xC92E, 1u, 0x3C}, - {0xC92F, 1u, 0x02}, - {0xC930, 1u, 0x06}, - {0xC931, 1u, 0x64}, - {0xC932, 1u, 0x01}, - {0xC933, 1u, 0x0C}, - {0xC934, 1u, 0x3C}, - {0xC935, 1u, 0x3C}, - {0xC936, 1u, 0x3C}, - {0xC937, 1u, 0x0F}, - {0xC938, 1u, 0x64}, - {0xC939, 1u, 0x64}, - {0xC93A, 1u, 0x64}, - {0xC93B, 1u, 0x32}, - {0xC93C, 2u, 0x0020}, - {0xC93E, 2u, 0x009A}, - {0xC940, 2u, 0x00DC}, - {0xC942, 1u, 0x38}, - {0xC943, 1u, 0x30}, - {0xC944, 1u, 0x50}, - {0xC945, 1u, 0x19}, - {0xC94A, 2u, 0x0230}, - {0xC94C, 2u, 0x0010}, - {0xC94E, 2u, 0x01CD}, - {0xC950, 1u, 0x05}, - {0xC951, 1u, 0x40}, - {0xC87B, 1u, 0x1B}, - {0xC890, 2u, 0x0080}, - {0xC886, 2u, 0x0100}, - {0xC87C, 2u, 0x005A}, - {0xB42A, 1u, 0x05}, - {0xA80A, 1u, 0x20}, - - {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XSTART, 2u, 0x0000}, /* cam_stat_awb_clip_window_xstart = 0 */ - {MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YSTART, 2u, 0x0000}, /* cam_stat_awb_clip_window_ystart = 0 */ - {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XSTART, 2u, 0x0000}, /* cam_stat_ae_initial_window_xstart = 0 */ - {MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YSTART, 2u, 0x0000}, /* cam_stat_ae_initial_window_ystart = 0 */ - {MT9M114_REG_PAD_SLEW, 2u, 0x0777}, /* Pad slew rate */ - {MT9M114_VAR_CAM_OUTPUT_FORMAT_YUV, 2u, 0x0038}, /* Must set cam_output_format_yuv_clip for CSI */ -}; - -hpm_stat_t mt9m114_read_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, void *value) -{ - hpm_stat_t status; - uint16_t subaddr = ((reg & 0xff) << 8) | ((reg & 0xff00) >> 8); - uint8_t data[4]; - uint8_t i = 0; - - status = i2c_master_address_read(context->ptr, context->i2c_device_addr, \ - (uint8_t *)&subaddr, MT9M114_REG_ADDR_LEN, \ - data, reg_size); - if (status_success == status) { - while (reg_size--) { - ((uint8_t *)value)[i++] = data[reg_size]; - } - } - return status; -} - -hpm_stat_t mt9m114_write_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t value) -{ - uint16_t subaddr = ((reg & 0xff) << 8) | ((reg & 0xff00) >> 8); - uint8_t data[4]; - uint8_t i; - - i = reg_size; - while (i--) { - data[i] = (uint8_t)value; - value >>= 8; - } - return i2c_master_address_write(context->ptr, context->i2c_device_addr, \ - (uint8_t *)&subaddr, MT9M114_REG_ADDR_LEN, \ - data, reg_size); -} - -hpm_stat_t mt9m114_modify_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t mask, uint32_t value) -{ - hpm_stat_t status; - uint32_t reg_value; - - status = mt9m114_read_register(context, reg, reg_size, ®_value); - - if (status_success != status) { - return status; - } - - reg_value = (reg_value & ~(mask)) | (value & mask); - - return mt9m114_write_register(context, reg, reg_size, reg_value); -} - -hpm_stat_t mt9m114_multiwrite(camera_context_t *context, const mt9m114_reg_t regs[], uint32_t num) -{ - hpm_stat_t status = status_success; - - for (uint32_t i = 0; i < num; i++) { - status = mt9m114_write_register(context, regs[i].reg, regs[i].size, regs[i].value); - if (status_success != status) { - ERROR_ACTION(); - } - } - - return status; -} - -hpm_stat_t mt9m114_host_command(camera_context_t *context, uint16_t command) -{ - if (mt9m114_write_register(context, MT9M114_REG_COMMAND_REGISTER, 2, (command | MT9M114_COMMAND_OK)) != 0) { - return status_fail; - } - - for (int i = 0; i < MT9M114_HOST_CMD_TIMEOUT; i++, context->delay_ms(1)) { - uint16_t reg_data; - - if (mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2, ®_data) != 0) { - return status_fail; - } - - if ((reg_data & command) == 0) { - return (reg_data & MT9M114_COMMAND_OK) ? 0 : -1; - } - - if (i == (MT9M114_HOST_CMD_TIMEOUT - 1)) { - return status_fail; - } - } - - return status_success; -} - -hpm_stat_t mt9m114_refresh(camera_context_t *context) -{ - hpm_stat_t ret = mt9m114_host_command(context, MT9M114_COMMAND_REFRESH); - - if (ret != status_success) { - return ret; - } - - uint8_t reg_data; - - if (mt9m114_read_register(context, MT9M114_VAR_SEQ_ERROR_CODE, 1, ®_data) != 0) { - return status_fail; - } - - return reg_data == 0 ? status_success : status_fail; -} - -hpm_stat_t mt9m114_get_current_state(camera_context_t *context, uint8_t *state) -{ - return mt9m114_read_register(context, MT9M114_VAR_SYSMGR_CURRENT_STATE, 1u, state); -} - -hpm_stat_t mt9m114_software_reset(camera_context_t *context) -{ - hpm_stat_t status; - uint16_t value; - assert(context->delay_ms != NULL); - - mt9m114_modify_register(context, MT9M114_REG_RESET_AND_MISC_CONTROL, 2, 0x01, 0x01); - context->delay_ms(1); - mt9m114_modify_register(context, MT9M114_REG_RESET_AND_MISC_CONTROL, 2, 0x01, 0x00); - context->delay_ms(50); - - /* forever loop if softreset is not done. Loop until reg 0x80's bit 1 is 0 */ - while (1) { - status = mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2u, &value); - if (status != status_success) { - ERROR_ACTION(); - } - if (!(value & MT9M114_COMMAND_SET_STATE)) { - DEBUG_INFO("[Camera]:sw reset finish\n"); - break; - } - } - return status_success; -} - -hpm_stat_t mt9m114_setstate(camera_context_t *context, uint16_t next_state) -{ - uint16_t value; - hpm_stat_t status = status_success; - - /* Set the desired next state. */ - status = mt9m114_write_register(context, MT9M114_VAR_SYSMGR_NEXT_STATE, 1, next_state); - if (status_success != status) { - ERROR_ACTION(); - } - - /* Check that the FW is ready to accept a new command. */ - context->delay_ms(1); - while (1) { - status = mt9m114_read_register(context, MT9M114_REG_COMMAND_REGISTER, 2u, &value); - if (status_success != status) { - ERROR_ACTION(); - } - if (!(value & MT9M114_COMMAND_SET_STATE)) { - break; - } - DEBUG_INFO("[Camera]:Set State cmd bit is already set\n"); - } - DEBUG_INFO("[Camera]:Issue the Set State command 0x%x\n", next_state); - - /* Issue the Set State command. */ - return mt9m114_host_command(context, MT9M114_COMMAND_SET_STATE); -} - -hpm_stat_t mt9m114_set_pixformat(camera_context_t *context, display_pixel_format_t pixformat) -{ - uint16_t reg = 0; - - switch (pixformat) { - case display_pixel_format_yuv422: - reg = MT9M114_OUTPUT_FORMAT_YUV | MT9M114_OUTPUT_FORMAT_SWAP_BYTES; - break; - case display_pixel_format_rgb565: - reg = MT9M114_OUTPUT_FORMAT_RGB | MT9M114_OUTPUT_FORMAT_RGB565 | MT9M114_OUTPUT_FORMAT_SWAP_BYTES; - break; - default: - return status_invalid_argument; - } - - if (mt9m114_write_register(context, MT9M114_VAR_CAM_OUTPUT_FORMAT, 2, reg) != 0) { - return status_fail; - } - - return mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); -} - -hpm_stat_t mt9m114_set_framerate(camera_context_t *context, int framerate) -{ - if (mt9m114_write_register(context, MT9M114_VAR_CAM_AET_MAX_FRAME_RATE, 2, framerate * 256) != 0) { - return status_fail; - } - - if (mt9m114_write_register(context, MT9M114_VAR_CAM_AET_MIN_FRAME_RATE, 2, framerate * 128) != 0) { - return status_fail; - } - - return mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); -} - -hpm_stat_t mt9m114_set_brightness(camera_context_t *context, int level) /* -16 to +16 */ -{ - int new_level = level * 2; - - if ((new_level < -32) || (32 < new_level)) { - return status_fail; - } - - if (mt9m114_write_register(context, MT9M114_VAR_UVC_BRIGHTNESS_CONTROL, 2, new_level + 55) != 0) { - return status_fail; - } - - return mt9m114_refresh(context); -} - -hpm_stat_t mt9m114_start(camera_context_t *handle) -{ - return mt9m114_setstate(handle, MT9M114_SYS_STATE_START_STREAMING); -} - -hpm_stat_t mt9m114_stop(camera_context_t *handle) -{ - return mt9m114_setstate(handle, MT9M114_SYS_STATE_ENTER_SUSPEND); -} - -hpm_stat_t mt9m114_check_chip_id(camera_context_t *handle) -{ - hpm_stat_t status = status_success; - uint16_t chip_id; - - status = mt9m114_read_register(handle, MT9M114_REG_CHIP_ID, 2u, &chip_id); - if (status_success != status) { - DEBUG_INFO("[ERROR] read MT9M114 chipid register failed %d\n", status); - return status_fail; - } - if (MT9M114_CHIP_ID != chip_id) { - DEBUG_INFO("[ERROR] chipid is %04x(expect %04x)\n", chip_id, MT9M114_CHIP_ID); - return status_fail; - } - return status_success; -} - -hpm_stat_t mt9m114_enable_mono(camera_context_t *handle, bool enable) -{ - uint16_t value = 0; - mt9m114_read_register(handle, 0x332E, 2u, &value); - if (enable) - value = value | 0x0004; - else - value = value & 0xFFFB; - mt9m114_write_register(handle, 0x332E, 2u, value); - return 0; -} - -hpm_stat_t mt9m114_init(camera_context_t *context, camera_config_t *camera_config) -{ - hpm_stat_t status = status_success; - - /* set init configs */ - DEBUG_INFO("[Camera]:set frame per sec ...\n"); - mt9m114_multiwrite(context, mt9m114_init_config, ARRAY_SIZE(mt9m114_init_config)); - - /* Pixel format. */ - DEBUG_INFO("[Camera]:set format...\n"); - status = mt9m114_set_pixformat(context, camera_config->pixel_format); - if (status_success != status) { - DEBUG_INFO("[ERROR] set output format %d\n", status); - ERROR_ACTION(); - } - - /* set cam port output control... */ - DEBUG_INFO("[Camera]:set cam port output control...\n"); - status = mt9m114_write_register(context, MT9M114_VAR_CAM_PORT_OUTPUT_CONTROL, 2, 0x8008); - if (status_success != status) { - DEBUG_INFO("[ERROR] set cam port output control... %d\n", status); - ERROR_ACTION(); - } - - /* set resolution... */ - DEBUG_INFO("[Camera]:set resolution...\n"); - status = mt9m114_multiwrite(context, mt9m114_vga, ARRAY_SIZE(mt9m114_vga)); - if (status_success != status) { - DEBUG_INFO("[ERROR] set resolution... %d\n", status); - ERROR_ACTION(); - } - - /* set change command */ - DEBUG_INFO("[Camera]:set change command...\n"); - status = mt9m114_setstate(context, MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE); - if (status_success != status) { - DEBUG_INFO("[ERROR] set change command... %d\n", status); - ERROR_ACTION(); - } - DEBUG_INFO("MT9M114 init done\n"); - return status; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h deleted file mode 100644 index a8e2bf7ae8e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/mt9m114/hpm_mt9m114.h +++ /dev/null @@ -1,867 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MT9M114_H -#define HPM_MT9M114_H -#include "hpm_camera_config.h" -#include "hpm_common.h" - -/* MT9M114_ERROR_ACTION_BLOCK - * 0 : return fail - * 1 : print error message to console and block - */ -#define MT9M114_ERROR_ACTION_BLOCK 0 -#define MT9M114_HOST_CMD_TIMEOUT 100 - -#ifndef MT9M114_ACTIVE_IMAGE_WIDTH -#define MT9M114_ACTIVE_IMAGE_WIDTH (640U) -#endif - -#ifndef MT9M114_ACTIVE_IMAGE_HEIGHT -#define MT9M114_ACTIVE_IMAGE_HEIGHT (480U) -#endif - -#define DUMMY_LINES 8 -#define DUMMY_COLUMNS 8 - -#define SENSOR_WIDTH 1296 -#define SENSOR_HEIGHT 976 - -#define DUMMY_WIDTH_BUFFER 8 -#define DUMMY_HEIGHT_BUFFER 8 - -#define ACTIVE_SENSOR_WIDTH (SENSOR_WIDTH - (2 * DUMMY_COLUMNS)) -#define ACTIVE_SENSOR_HEIGHT (SENSOR_HEIGHT - (2 * DUMMY_LINES)) - -/** - * @brief MT9M114 sensor driver APIs - * @defgroup MT9M114_interface sensor driver APIs - * @ingroup component_interfaces - * @{ - * - - */ -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ - -/** - * @brief MT9M114 definition - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -#if defined(MT9M114_DUAL_CAMERA) -#define MT9M114_I2C_ADDR 0x48 -#define MT9M114_I2C_ADDR_IR 0x5D -#else -#define MT9M114_I2C_ADDR 0x48 -#endif -#define MT9M114_CHIP_ID 0x2481 - -#define MT9M114_REG_ADDR_LEN (2) - -/*! @brief MT9M114 register definitions.*/ - -/* 1.Core registers */ -#define MT9M114_REG_Y_ADDR_START 0x3002 -#define MT9M114_REG_X_ADDR_START 0x3004 -#define MT9M114_REG_Y_ADDR_END 0x3006 -#define MT9M114_REG_X_ADDR_END 0x3008 -#define MT9M114_REG_FRAME_LENGTH_LINES 0x300A -#define MT9M114_REG_LINE_LENGTH_PCK_ 0x300C -#define MT9M114_REG_COARSE_INTEGRATION_TIME 0x3012 -#define MT9M114_REG_FINE_INTEGRATION_TIME 0x3014 -#define MT9M114_REG_RESET_REGISTER 0x301A -#define MT9M114_REG_FLASH 0x3046 -#define MT9M114_REG_FLASH_COUNT 0x3048 -#define MT9M114_REG_GREEN1_GAIN 0x3056 -#define MT9M114_REG_BLUE_GAIN 0x3058 -#define MT9M114_REG_RED_GAIN 0x305A -#define MT9M114_REG_GREEN2_GAIN 0x305C -#define MT9M114_REG_GLOBAL_GAIN 0x305E -#define MT9M114_REG_FUSE_ID1 0x31F4 -#define MT9M114_REG_FUSE_ID2 0x31F6 -#define MT9M114_REG_FUSE_ID3 0x31F8 -#define MT9M114_REG_FUSE_ID4 0x31FA -#define MT9M114_REG_CHAIN_CONTROL 0x31FC -#define MT9M114_REG_CUSTOMER_REV 0x31FE - -/* 2.SOC1 registers */ -#define MT9M114_REG_COLOR_PIPELINE_CONTROL 0x3210 - -/* 3.SOC2 registers */ -#define MT9M114_REG_P_G1_P0Q0 0x3640 -#define MT9M114_REG_P_G1_P0Q1 0x3642 -#define MT9M114_REG_P_G1_P0Q2 0x3644 -#define MT9M114_REG_P_G1_P0Q3 0x3646 -#define MT9M114_REG_P_G1_P0Q4 0x3648 -#define MT9M114_REG_P_R_P0Q0 0x364A -#define MT9M114_REG_P_R_P0Q1 0x364C -#define MT9M114_REG_P_R_P0Q2 0x364E -#define MT9M114_REG_P_R_P0Q3 0x3650 -#define MT9M114_REG_P_R_P0Q4 0x3652 -#define MT9M114_REG_P_B_P0Q0 0x3654 -#define MT9M114_REG_P_B_P0Q1 0x3656 -#define MT9M114_REG_P_B_P0Q2 0x3658 -#define MT9M114_REG_P_B_P0Q3 0x365A -#define MT9M114_REG_P_B_P0Q4 0x365C -#define MT9M114_REG_P_G2_P0Q0 0x365E -#define MT9M114_REG_P_G2_P0Q1 0x3660 -#define MT9M114_REG_P_G2_P0Q2 0x3662 -#define MT9M114_REG_P_G2_P0Q3 0x3664 -#define MT9M114_REG_P_G2_P0Q4 0x3666 -#define MT9M114_REG_P_G1_P1Q0 0x3680 -#define MT9M114_REG_P_G1_P1Q1 0x3682 -#define MT9M114_REG_P_G1_P1Q2 0x3684 -#define MT9M114_REG_P_G1_P1Q3 0x3686 -#define MT9M114_REG_P_G1_P1Q4 0x3688 -#define MT9M114_REG_P_R_P1Q0 0x368A -#define MT9M114_REG_P_R_P1Q1 0x368C -#define MT9M114_REG_P_R_P1Q2 0x368E -#define MT9M114_REG_P_R_P1Q3 0x3690 -#define MT9M114_REG_P_R_P1Q4 0x3692 -#define MT9M114_REG_P_B_P1Q0 0x3694 -#define MT9M114_REG_P_B_P1Q1 0x3696 -#define MT9M114_REG_P_B_P1Q2 0x3698 -#define MT9M114_REG_P_B_P1Q3 0x369A -#define MT9M114_REG_P_B_P1Q4 0x369C -#define MT9M114_REG_P_G2_P1Q0 0x369E -#define MT9M114_REG_P_G2_P1Q1 0x36A0 -#define MT9M114_REG_P_G2_P1Q2 0x36A2 -#define MT9M114_REG_P_G2_P1Q3 0x36A4 -#define MT9M114_REG_P_G2_P1Q4 0x36A6 -#define MT9M114_REG_P_G1_P2Q0 0x36C0 -#define MT9M114_REG_P_G1_P2Q1 0x36C2 -#define MT9M114_REG_P_G1_P2Q2 0x36C4 -#define MT9M114_REG_P_G1_P2Q3 0x36C6 -#define MT9M114_REG_P_G1_P2Q4 0x36C8 -#define MT9M114_REG_P_R_P2Q0 0x36CA -#define MT9M114_REG_P_R_P2Q1 0x36CC -#define MT9M114_REG_P_R_P2Q2 0x36CE -#define MT9M114_REG_P_R_P2Q3 0x36D0 -#define MT9M114_REG_P_R_P2Q4 0x36D2 -#define MT9M114_REG_P_B_P2Q0 0x36D4 -#define MT9M114_REG_P_B_P2Q1 0x36D6 -#define MT9M114_REG_P_B_P2Q2 0x36D8 -#define MT9M114_REG_P_B_P2Q3 0x36DA -#define MT9M114_REG_P_B_P2Q4 0x36DC -#define MT9M114_REG_P_G2_P2Q0 0x36DE -#define MT9M114_REG_P_G2_P2Q1 0x36E0 -#define MT9M114_REG_P_G2_P2Q2 0x36E2 -#define MT9M114_REG_P_G2_P2Q3 0x36E4 -#define MT9M114_REG_P_G2_P2Q4 0x36E6 -#define MT9M114_REG_P_G1_P3Q0 0x3700 -#define MT9M114_REG_P_G1_P3Q1 0x3702 -#define MT9M114_REG_P_G1_P3Q2 0x3704 -#define MT9M114_REG_P_G1_P3Q3 0x3706 -#define MT9M114_REG_P_G1_P3Q4 0x3708 -#define MT9M114_REG_P_R_P3Q0 0x370A -#define MT9M114_REG_P_R_P3Q1 0x370C -#define MT9M114_REG_P_R_P3Q2 0x370E -#define MT9M114_REG_P_R_P3Q3 0x3710 -#define MT9M114_REG_P_R_P3Q4 0x3712 -#define MT9M114_REG_P_B_P3Q0 0x3714 -#define MT9M114_REG_P_B_P3Q1 0x3716 -#define MT9M114_REG_P_B_P3Q2 0x3718 -#define MT9M114_REG_P_B_P3Q3 0x371A -#define MT9M114_REG_P_B_P3Q4 0x371C -#define MT9M114_REG_P_G2_P3Q0 0x371E -#define MT9M114_REG_P_G2_P3Q1 0x3720 -#define MT9M114_REG_P_G2_P3Q2 0x3722 -#define MT9M114_REG_P_G2_P3Q3 0x3724 -#define MT9M114_REG_P_G2_P3Q4 0x3726 -#define MT9M114_REG_P_G1_P4Q0 0x3740 -#define MT9M114_REG_P_G1_P4Q1 0x3742 -#define MT9M114_REG_P_G1_P4Q2 0x3744 -#define MT9M114_REG_P_G1_P4Q3 0x3746 -#define MT9M114_REG_P_G1_P4Q4 0x3748 -#define MT9M114_REG_P_R_P4Q0 0x374A -#define MT9M114_REG_P_R_P4Q1 0x374C -#define MT9M114_REG_P_R_P4Q2 0x374E -#define MT9M114_REG_P_R_P4Q3 0x3750 -#define MT9M114_REG_P_R_P4Q4 0x3752 -#define MT9M114_REG_P_B_P4Q0 0x3754 -#define MT9M114_REG_P_B_P4Q1 0x3756 -#define MT9M114_REG_P_B_P4Q2 0x3758 -#define MT9M114_REG_P_B_P4Q3 0x375A -#define MT9M114_REG_P_B_P4Q4 0x375C -#define MT9M114_REG_P_G2_P4Q0 0x375E -#define MT9M114_REG_P_G2_P4Q1 0x3760 -#define MT9M114_REG_P_G2_P4Q2 0x3762 -#define MT9M114_REG_P_G2_P4Q3 0x3764 -#define MT9M114_REG_P_G2_P4Q4 0x3766 -#define MT9M114_REG_CENTER_ROW 0x3782 -#define MT9M114_REG_CENTER_COLUMN 0x3784 - -/* 4.SYSCTL registers */ -#define MT9M114_REG_CHIP_ID 0x0000 -#define MT9M114_REG_CLOCKS_CONTROL 0x0016 -#define MT9M114_REG_RESET_AND_MISC_CONTROL 0x001A -#define MT9M114_REG_PAD_SLEW 0x001E -#define MT9M114_REG_USER_DEFINED_DEVICE_ADDRESS_ID 0x002E -#define MT9M114_REG_PAD_CONTROL 0x0032 -#define MT9M114_REG_COMMAND_REGISTER 0x0080 - -/* 5.XDMA registers */ -#define MT9M114_REG_ACCESS_CTL_STAT 0x0982 -#define MT9M114_REG_PHYSICAL_ADDRESS_ACCESS 0x098A -#define MT9M114_REG_LOGICAL_ADDRESS_ACCESS 0x098E -#define MT9M114_REG_MCU_VARIABLE_DATA0 0x0990 -#define MT9M114_REG_MCU_VARIABLE_DATA1 0x0992 -#define MT9M114_REG_MCU_VARIABLE_DATA2 0x0994 -#define MT9M114_REG_MCU_VARIABLE_DATA3 0x0996 -#define MT9M114_REG_MCU_VARIABLE_DATA4 0x0998 -#define MT9M114_REG_MCU_VARIABLE_DATA5 0x099A -#define MT9M114_REG_MCU_VARIABLE_DATA6 0x099C -#define MT9M114_REG_MCU_VARIABLE_DATA7 0x099E - -/*! @brief MT9M114 variables definitions.*/ - -/* 01.Monitor variables */ -#define MT9M114_VAR_MON_MAJOR_VERSION 0x8000 -#define MT9M114_VAR_MON_MINOR_VERSION 0x8002 -#define MT9M114_VAR_MON_RELEASE_VERSION 0x8004 -#define MT9M114_VAR_MON_HEARTBEAT 0x8006 - -/* 02.Sequencer variables */ -#define MT9M114_VAR_SEQ_ERROR_CODE 0x8406 - -/* 03.AE_Rule variables */ -#define MT9M114_VAR_AE_RULE_ALGO 0xA404 -#define MT9M114_VAR_AE_RULE_AVG_Y_FROM_STATS 0xA406 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_0 0xA407 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_1 0xA408 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_2 0xA409 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_3 0xA40A -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_0_4 0xA40B -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_0 0xA40C -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_1 0xA40D -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_2 0xA40E -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_3 0xA40F -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_1_4 0xA410 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_0 0xA411 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_1 0xA412 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_2 0xA413 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_3 0xA414 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_2_4 0xA415 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_0 0xA416 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_1 0xA417 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_2 0xA418 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_3 0xA419 -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_3_4 0xA41A -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_0 0xA41B -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_1 0xA41C -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_2 0xA41D -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_3 0xA41E -#define MT9M114_VAR_AE_RULE_AE_WEIGHT_TABLE_4_4 0xA41F -#define MT9M114_VAR_AE_RULE_AE_ADAPTIVE_STRENGTH 0xA420 - -/* 04.AE_Track variables */ -#define MT9M114_VAR_AE_TRACK_STATUS 0xA800 -#define MT9M114_VAR_AE_TRACK_ALGO 0xA804 -#define MT9M114_VAR_AE_TRACK_TARGET_AVERAGE_LUMA 0xA807 -#define MT9M114_VAR_AE_TRACK_GATE_PERCENTAGE 0xA808 -#define MT9M114_VAR_AE_TRACK_CURRENT_AVERAGE_LUMA 0xA809 -#define MT9M114_VAR_AE_TRACK_AE_TRACKING_DAMPENING_SPEED 0xA80A -#define MT9M114_VAR_AE_TRACK_AE_DAMPENING_SPEED 0xA80B -#define MT9M114_VAR_AE_TRACK_SKIP_FRAMES_COUNTER 0xA80D -#define MT9M114_VAR_AE_TRACK_CURRENT_FLICKER_LINES 0xA80E -#define MT9M114_VAR_AE_TRACK_FDZONE 0xA818 -#define MT9M114_VAR_AE_TRACK_ZONE 0xA81B -#define MT9M114_VAR_AE_TRACK_FLICKER_LINES_50HZ 0xA826 -#define MT9M114_VAR_AE_TRACK_VIRT_EXPOSURE_LOG 0xA828 -#define MT9M114_VAR_AE_TRACK_MIN_VIRT_EXPOSURE_LOG_ZONE0 0xA82A -#define MT9M114_VAR_AE_TRACK_MAX_VIRT_EXPOSURE_LOG_ZONE0 0xA82C -#define MT9M114_VAR_AE_TRACK_MAX_VIRT_EXPOSURE_LOG_ZONE1 0xA82E -#define MT9M114_VAR_AE_TRACK_VIRT_GAIN 0xA838 - -/* 05.AWB variables */ -#define MT9M114_VAR_AWB_STATUS 0xAC00 -#define MT9M114_VAR_AWB_MODE 0xAC02 -#define MT9M114_VAR_AWB_R_RATIO_LOWER 0xAC06 -#define MT9M114_VAR_AWB_R_RATIO_UPPER 0xAC07 -#define MT9M114_VAR_AWB_B_RATIO_LOWER 0xAC08 -#define MT9M114_VAR_AWB_B_RATIO_UPPER 0xAC09 -#define MT9M114_VAR_AWB_R_SCENE_RATIO_LOWER 0xAC0A -#define MT9M114_VAR_AWB_R_SCENE_RATIO_UPPER 0xAC0B -#define MT9M114_VAR_AWB_B_SCENE_RATIO_LOWER 0xAC0C -#define MT9M114_VAR_AWB_B_SCENE_RATIO_UPPER 0xAC0D -#define MT9M114_VAR_AWB_R_RATIO_PRE_AWB 0xAC0E -#define MT9M114_VAR_AWB_B_RATIO_PRE_AWB 0xAC0F -#define MT9M114_VAR_AWB_R_GAIN 0xAC12 -#define MT9M114_VAR_AWB_B_GAIN 0xAC14 -#define MT9M114_VAR_AWB_PRE_AWB_RATIOS_TRACKING_SPEED 0xAC16 -#define MT9M114_VAR_AWB_PIXEL_THRESHOLD_COUNT 0xAC18 - -/* 06.BlackLevel variables */ -#define MT9M114_VAR_BLACKLEVEL_ALGO 0xB004 -#define MT9M114_VAR_BLACKLEVEL_MAX_BLACK_LEVEL 0xB00C -#define MT9M114_VAR_BLACKLEVEL_BLACK_LEVEL_DAMPENING 0xB00D - -/* 07.CCM variables */ -#define MT9M114_VAR_CCM_ALGO 0xB404 -#define MT9M114_VAR_CCM_0 0xB406 -#define MT9M114_VAR_CCM_1 0xB408 -#define MT9M114_VAR_CCM_2 0xB40A -#define MT9M114_VAR_CCM_3 0xB40C -#define MT9M114_VAR_CCM_4 0xB40E -#define MT9M114_VAR_CCM_5 0xB410 -#define MT9M114_VAR_CCM_6 0xB412 -#define MT9M114_VAR_CCM_7 0xB414 -#define MT9M114_VAR_CCM_8 0xB416 -#define MT9M114_VAR_CCM_LL_DELTA_CCM_0 0xB418 -#define MT9M114_VAR_CCM_LL_DELTA_CCM_1 0xB41A -#define MT9M114_VAR_CCM_LL_DELTA_CCM_2 0xB41C -#define MT9M114_VAR_CCM_LL_DELTA_CCM_3 0xB41E -#define MT9M114_VAR_CCM_LL_DELTA_CCM_4 0xB420 -#define MT9M114_VAR_CCM_LL_DELTA_CCM_5 0xB422 -#define MT9M114_VAR_CCM_LL_DELTA_CCM_6 0xB424 -#define MT9M114_VAR_CCM_LL_DELTA_CCM_7 0xB426 -#define MT9M114_VAR_CCM_LL_DELTA_CCM_8 0xB428 -#define MT9M114_VAR_CCM_DELTA_GAIN 0xB42A -#define MT9M114_VAR_CCM_DELTA_THRESH 0xB42B - -/* 08.LowLight variables */ -#define MT9M114_VAR_LL_MODE 0xBC02 -#define MT9M114_VAR_LL_ALGO 0xBC04 -#define MT9M114_VAR_LL_GAMMA_SELECT 0xBC07 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_0 0xBC0A -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_1 0xBC0B -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_2 0xBC0C -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_3 0xBC0D -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_4 0xBC0E -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_5 0xBC0F -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_6 0xBC10 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_7 0xBC11 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_8 0xBC12 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_9 0xBC13 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_10 0xBC14 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_11 0xBC15 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_12 0xBC16 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_13 0xBC17 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_14 0xBC18 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_15 0xBC19 -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_16 0xBC1A -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_17 0xBC1B -#define MT9M114_VAR_LL_GAMMA_CONTRAST_CURVE_18 0xBC1C -#define MT9M114_VAR_LL_GAMMA_NRCURVE_0 0xBC1D -#define MT9M114_VAR_LL_GAMMA_NRCURVE_1 0xBC1E -#define MT9M114_VAR_LL_GAMMA_NRCURVE_2 0xBC1F -#define MT9M114_VAR_LL_GAMMA_NRCURVE_3 0xBC20 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_4 0xBC21 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_5 0xBC22 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_6 0xBC23 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_7 0xBC24 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_8 0xBC25 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_9 0xBC26 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_10 0xBC27 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_11 0xBC28 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_12 0xBC29 -#define MT9M114_VAR_LL_GAMMA_NRCURVE_13 0xBC2A -#define MT9M114_VAR_LL_GAMMA_NRCURVE_14 0xBC2B -#define MT9M114_VAR_LL_GAMMA_NRCURVE_15 0xBC2C -#define MT9M114_VAR_LL_GAMMA_NRCURVE_16 0xBC2D -#define MT9M114_VAR_LL_GAMMA_NRCURVE_17 0xBC2E -#define MT9M114_VAR_LL_GAMMA_NRCURVE_18 0xBC2F -#define MT9M114_VAR_LL_BM_PRECISION_BITS 0xBC31 -#define MT9M114_VAR_LL_AVERAGE_LUMA_FADE_TO_BLACK 0xBC3A -#define MT9M114_VAR_LL_FADE_TO_BLACK_DAMPENING_SPEED 0xBC3C - -/* 09.CameraControl variables */ -#define MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_START 0xC800 -#define MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_START 0xC802 -#define MT9M114_VAR_CAM_SENSOR_CFG_Y_ADDR_END 0xC804 -#define MT9M114_VAR_CAM_SENSOR_CFG_X_ADDR_END 0xC806 -#define MT9M114_VAR_CAM_SENSOR_CFG_PIXCLK 0xC808 -#define MT9M114_VAR_CAM_SENSOR_CFG_ROW_SPEED 0xC80C -#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MIN 0xC80E -#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_INTEG_TIME_MAX 0xC810 -#define MT9M114_VAR_CAM_SENSOR_CFG_FRAME_LENGTH_LINES 0xC812 -#define MT9M114_VAR_CAM_SENSOR_CFG_LINE_LENGTH_PCK 0xC814 -#define MT9M114_VAR_CAM_SENSOR_CFG_FINE_CORRECTION 0xC816 -#define MT9M114_VAR_CAM_SENSOR_CFG_CPIPE_LAST_ROW 0xC818 -#define MT9M114_VAR_CAM_SENSOR_CFG_REG_0_DATA 0xC826 -#define MT9M114_VAR_CAM_SENSOR_CONTROL_READ_MODE 0xC834 -#define MT9M114_VAR_CAM_SENSOR_CONTROL_ANALOG_GAIN 0xC836 -#define MT9M114_VAR_CAM_SENSOR_CONTROL_VIRT_COLUMN_GAIN 0xC838 -#define MT9M114_VAR_CAM_SENSOR_CONTROL_FRAME_LENGTH_LINES 0xC83A -#define MT9M114_VAR_CAM_SENSOR_CONTROL_COARSE_INTEGRATION_TIME 0xC83C -#define MT9M114_VAR_CAM_SENSOR_CONTROL_FINE_INTEGRATION_TIME 0xC83E -#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_RED 0xC840 -#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_GREEN1 0xC842 -#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_GREEN2 0xC844 -#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_BLUE 0xC846 -#define MT9M114_VAR_CAM_CPIPE_CONTROL_DGAIN_SECOND 0xC848 -#define MT9M114_VAR_CAM_CPIPE_CONTROL_SECOND_BLACK_LEVEL 0xC84B -#define MT9M114_VAR_CAM_MODE_SELECT 0xC84C -#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_SELECT 0xC84D -#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_RED 0xC84E -#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_GREEN 0xC850 -#define MT9M114_VAR_CAM_MODE_TEST_PATTERN_BLUE 0xC852 -#define MT9M114_VAR_CAM_CROP_WINDOW_XOFFSET 0xC854 -#define MT9M114_VAR_CAM_CROP_WINDOW_YOFFSET 0xC856 -#define MT9M114_VAR_CAM_CROP_WINDOW_WIDTH 0xC858 -#define MT9M114_VAR_CAM_CROP_WINDOW_HEIGHT 0xC85A -#define MT9M114_VAR_CAM_CROP_CROPMODE 0xC85C -#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_MODE 0xC85E -#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_PERCENTAGE 0xC860 -#define MT9M114_VAR_CAM_SCALE_VERTICAL_TC_STRETCH_FACTOR 0xC862 -#define MT9M114_VAR_CAM_OUTPUT_WIDTH 0xC868 -#define MT9M114_VAR_CAM_OUTPUT_HEIGHT 0xC86A -#define MT9M114_VAR_CAM_OUTPUT_FORMAT 0xC86C -#define MT9M114_VAR_CAM_OUTPUT_FORMAT_YUV 0xC86E -#define MT9M114_VAR_CAM_OUTPUT_Y_OFFSET 0xC870 -#define MT9M114_VAR_CAM_HUE_ANGLE 0xC873 -#define MT9M114_VAR_CAM_SFX_CONTROL 0xC874 -#define MT9M114_VAR_CAM_SFX_SOLARIZATION_THRESH 0xC875 -#define MT9M114_VAR_CAM_SFX_SEPIA_CR 0xC876 -#define MT9M114_VAR_CAM_SFX_SEPIA_CB 0xC877 -#define MT9M114_VAR_CAM_AET_AEMODE 0xC878 -#define MT9M114_VAR_CAM_AET_SKIP_FRAMES 0xC879 -#define MT9M114_VAR_CAM_AET_TARGET_AVERAGE_LUMA 0xC87A -#define MT9M114_VAR_CAM_AET_TARGET_AVERAGE_LUMA_DARK 0xC87B -#define MT9M114_VAR_CAM_AET_BLACK_CLIPPING_TARGET 0xC87C -#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_INT_TIME_PCLK 0xC87E -#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_DGAIN 0xC880 -#define MT9M114_VAR_CAM_AET_AE_MAX_VIRT_DGAIN 0xC882 -#define MT9M114_VAR_CAM_AET_AE_MIN_VIRT_AGAIN 0xC884 -#define MT9M114_VAR_CAM_AET_AE_MAX_VIRT_AGAIN 0xC886 -#define MT9M114_VAR_CAM_AET_AE_VIRT_GAIN_TH_EG 0xC888 -#define MT9M114_VAR_CAM_AET_AE_EG_GATE_PERCENTAGE 0xC88A -#define MT9M114_VAR_CAM_AET_FLICKER_FREQ_HZ 0xC88B -#define MT9M114_VAR_CAM_AET_MAX_FRAME_RATE 0xC88C -#define MT9M114_VAR_CAM_AET_MIN_FRAME_RATE 0xC88E -#define MT9M114_VAR_CAM_AET_TARGET_GAIN 0xC890 -#define MT9M114_VAR_CAM_AWB_CCM_L_0 0xC892 -#define MT9M114_VAR_CAM_AWB_CCM_L_1 0xC894 -#define MT9M114_VAR_CAM_AWB_CCM_L_2 0xC896 -#define MT9M114_VAR_CAM_AWB_CCM_L_3 0xC898 -#define MT9M114_VAR_CAM_AWB_CCM_L_4 0xC89A -#define MT9M114_VAR_CAM_AWB_CCM_L_5 0xC89C -#define MT9M114_VAR_CAM_AWB_CCM_L_6 0xC89E -#define MT9M114_VAR_CAM_AWB_CCM_L_7 0xC8A0 -#define MT9M114_VAR_CAM_AWB_CCM_L_8 0xC8A2 -#define MT9M114_VAR_CAM_AWB_CCM_M_0 0xC8A4 -#define MT9M114_VAR_CAM_AWB_CCM_M_1 0xC8A6 -#define MT9M114_VAR_CAM_AWB_CCM_M_2 0xC8A8 -#define MT9M114_VAR_CAM_AWB_CCM_M_3 0xC8AA -#define MT9M114_VAR_CAM_AWB_CCM_M_4 0xC8AC -#define MT9M114_VAR_CAM_AWB_CCM_M_5 0xC8AE -#define MT9M114_VAR_CAM_AWB_CCM_M_6 0xC8B0 -#define MT9M114_VAR_CAM_AWB_CCM_M_7 0xC8B2 -#define MT9M114_VAR_CAM_AWB_CCM_M_8 0xC8B4 -#define MT9M114_VAR_CAM_AWB_CCM_R_0 0xC8B6 -#define MT9M114_VAR_CAM_AWB_CCM_R_1 0xC8B8 -#define MT9M114_VAR_CAM_AWB_CCM_R_2 0xC8BA -#define MT9M114_VAR_CAM_AWB_CCM_R_3 0xC8BC -#define MT9M114_VAR_CAM_AWB_CCM_R_4 0xC8BE -#define MT9M114_VAR_CAM_AWB_CCM_R_5 0xC8C0 -#define MT9M114_VAR_CAM_AWB_CCM_R_6 0xC8C2 -#define MT9M114_VAR_CAM_AWB_CCM_R_7 0xC8C4 -#define MT9M114_VAR_CAM_AWB_CCM_R_8 0xC8C6 -#define MT9M114_VAR_CAM_AWB_CCM_L_RG_GAIN 0xC8C8 -#define MT9M114_VAR_CAM_AWB_CCM_L_BG_GAIN 0xC8CA -#define MT9M114_VAR_CAM_AWB_CCM_M_RG_GAIN 0xC8CC -#define MT9M114_VAR_CAM_AWB_CCM_M_BG_GAIN 0xC8CE -#define MT9M114_VAR_CAM_AWB_CCM_R_RG_GAIN 0xC8D0 -#define MT9M114_VAR_CAM_AWB_CCM_R_BG_GAIN 0xC8D2 -#define MT9M114_VAR_CAM_AWB_CCM_L_CTEMP 0xC8D4 -#define MT9M114_VAR_CAM_AWB_CCM_M_CTEMP 0xC8D6 -#define MT9M114_VAR_CAM_AWB_CCM_R_CTEMP 0xC8D8 -#define MT9M114_VAR_CAM_AWB_LL_CCM_0 0xC8DA -#define MT9M114_VAR_CAM_AWB_LL_CCM_1 0xC8DC -#define MT9M114_VAR_CAM_AWB_LL_CCM_2 0xC8DE -#define MT9M114_VAR_CAM_AWB_LL_CCM_3 0xC8E0 -#define MT9M114_VAR_CAM_AWB_LL_CCM_4 0xC8E2 -#define MT9M114_VAR_CAM_AWB_LL_CCM_5 0xC8E4 -#define MT9M114_VAR_CAM_AWB_LL_CCM_6 0xC8E6 -#define MT9M114_VAR_CAM_AWB_LL_CCM_7 0xC8E8 -#define MT9M114_VAR_CAM_AWB_LL_CCM_8 0xC8EA -#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE_MIN 0xC8EC -#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE_MAX 0xC8EE -#define MT9M114_VAR_CAM_AWB_COLOR_TEMPERATURE 0xC8F0 -#define MT9M114_VAR_CAM_AWB_AWB_XSCALE 0xC8F2 -#define MT9M114_VAR_CAM_AWB_AWB_YSCALE 0xC8F3 -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_0 0xC8F4 -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_1 0xC8F6 -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_2 0xC8F8 -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_3 0xC8FA -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_4 0xC8FC -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_5 0xC8FE -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_6 0xC900 -#define MT9M114_VAR_CAM_AWB_AWB_WEIGHTS_7 0xC902 -#define MT9M114_VAR_CAM_AWB_AWB_XSHIFT_PRE_ADJ 0xC904 -#define MT9M114_VAR_CAM_AWB_AWB_YSHIFT_PRE_ADJ 0xC906 -#define MT9M114_VAR_CAM_AWB_AWBMODE 0xC909 -#define MT9M114_VAR_CAM_AWB_TINTS_CTEMP_THRESHOLD 0xC90A -#define MT9M114_VAR_CAM_AWB_K_R_L 0xC90C -#define MT9M114_VAR_CAM_AWB_K_G_L 0xC90D -#define MT9M114_VAR_CAM_AWB_K_B_L 0xC90E -#define MT9M114_VAR_CAM_AWB_K_R_R 0xC90F -#define MT9M114_VAR_CAM_AWB_K_G_R 0xC910 -#define MT9M114_VAR_CAM_AWB_K_B_R 0xC911 -#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XSTART 0xC914 -#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YSTART 0xC916 -#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_XEND 0xC918 -#define MT9M114_VAR_CAM_STAT_AWB_CLIP_WINDOW_YEND 0xC91A -#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XSTART 0xC91C -#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YSTART 0xC91E -#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_XEND 0xC920 -#define MT9M114_VAR_CAM_STAT_AE_INITIAL_WINDOW_YEND 0xC922 -#define MT9M114_VAR_CAM_LL_LLMODE 0xC924 -#define MT9M114_VAR_CAM_LL_START_BRIGHTNESS 0xC926 -#define MT9M114_VAR_CAM_LL_STOP_BRIGHTNESS 0xC928 -#define MT9M114_VAR_CAM_LL_START_SATURATION 0xC92A -#define MT9M114_VAR_CAM_LL_END_SATURATION 0xC92B -#define MT9M114_VAR_CAM_LL_START_DESATURATION 0xC92C -#define MT9M114_VAR_CAM_LL_END_DESATURATION 0xC92D -#define MT9M114_VAR_CAM_LL_START_DEMOSAIC 0xC92E -#define MT9M114_VAR_CAM_LL_START_AP_GAIN 0xC92F -#define MT9M114_VAR_CAM_LL_START_AP_THRESH 0xC930 -#define MT9M114_VAR_CAM_LL_STOP_DEMOSAIC 0xC931 -#define MT9M114_VAR_CAM_LL_STOP_AP_GAIN 0xC932 -#define MT9M114_VAR_CAM_LL_STOP_AP_THRESH 0xC933 -#define MT9M114_VAR_CAM_LL_START_NR_RED 0xC934 -#define MT9M114_VAR_CAM_LL_START_NR_GREEN 0xC935 -#define MT9M114_VAR_CAM_LL_START_NR_BLUE 0xC936 -#define MT9M114_VAR_CAM_LL_START_NR_THRESH 0xC937 -#define MT9M114_VAR_CAM_LL_STOP_NR_RED 0xC938 -#define MT9M114_VAR_CAM_LL_STOP_NR_GREEN 0xC939 -#define MT9M114_VAR_CAM_LL_STOP_NR_BLUE 0xC93A -#define MT9M114_VAR_CAM_LL_STOP_NR_THRESH 0xC93B -#define MT9M114_VAR_CAM_LL_START_CONTRAST_BM 0xC93C -#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_BM 0xC93E -#define MT9M114_VAR_CAM_LL_GAMMA 0xC940 -#define MT9M114_VAR_CAM_LL_START_CONTRAST_GRADIENT 0xC942 -#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_GRADIENT 0xC943 -#define MT9M114_VAR_CAM_LL_START_CONTRAST_LUMA_PERCENTAGE 0xC944 -#define MT9M114_VAR_CAM_LL_STOP_CONTRAST_LUMA_PERCENTAGE 0xC945 -#define MT9M114_VAR_CAM_LL_START_GAIN_METRIC 0xC946 -#define MT9M114_VAR_CAM_LL_STOP_GAIN_METRIC 0xC948 -#define MT9M114_VAR_CAM_LL_START_FADE_TO_BLACK_LUMA 0xC94A -#define MT9M114_VAR_CAM_LL_STOP_FADE_TO_BLACK_LUMA 0xC94C -#define MT9M114_VAR_CAM_LL_CLUSTER_DC_TH_BM 0xC94E -#define MT9M114_VAR_CAM_LL_CLUSTER_DC_GATE_PERCENTAGE 0xC950 -#define MT9M114_VAR_CAM_LL_SUMMING_SENSITIVITY_FACTOR 0xC951 -#define MT9M114_VAR_CAM_LL_START_TARGET_LUMA_BM 0xC952 -#define MT9M114_VAR_CAM_LL_STOP_TARGET_LUMA_BM 0xC954 -#define MT9M114_VAR_CAM_LL_INV_BRIGHTNESS_METRIC 0xC956 -#define MT9M114_VAR_CAM_LL_GAIN_METRIC 0xC958 -#define MT9M114_VAR_CAM_SEQ_UV_COLOR_BOOST 0xC95A -#define MT9M114_VAR_CAM_PGA_PGA_CONTROL 0xC95E -#define MT9M114_VAR_CAM_PGA_L_CONFIG_COLOUR_TEMP 0xC960 -#define MT9M114_VAR_CAM_PGA_L_CONFIG_GREEN_RED_Q14 0xC962 -#define MT9M114_VAR_CAM_PGA_L_CONFIG_RED_Q14 0xC964 -#define MT9M114_VAR_CAM_PGA_L_CONFIG_GREEN_BLUE_Q14 0xC966 -#define MT9M114_VAR_CAM_PGA_L_CONFIG_BLUE_Q14 0xC968 -#define MT9M114_VAR_CAM_PGA_M_CONFIG_COLOUR_TEMP 0xC96A -#define MT9M114_VAR_CAM_PGA_M_CONFIG_GREEN_RED_Q14 0xC96C -#define MT9M114_VAR_CAM_PGA_M_CONFIG_RED_Q14 0xC96E -#define MT9M114_VAR_CAM_PGA_M_CONFIG_GREEN_BLUE_Q14 0xC970 -#define MT9M114_VAR_CAM_PGA_M_CONFIG_BLUE_Q14 0xC972 -#define MT9M114_VAR_CAM_PGA_R_CONFIG_COLOUR_TEMP 0xC974 -#define MT9M114_VAR_CAM_PGA_R_CONFIG_GREEN_RED_Q14 0xC976 -#define MT9M114_VAR_CAM_PGA_R_CONFIG_RED_Q14 0xC978 -#define MT9M114_VAR_CAM_PGA_R_CONFIG_GREEN_BLUE_Q14 0xC97A -#define MT9M114_VAR_CAM_PGA_R_CONFIG_BLUE_Q14 0xC97C -#define MT9M114_VAR_CAM_SYSCTL_PLL_ENABLE 0xC97E -#define MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_M_N 0xC980 -#define MT9M114_VAR_CAM_SYSCTL_PLL_DIVIDER_P 0xC982 -#define MT9M114_VAR_CAM_PORT_OUTPUT_CONTROL 0xC984 -#define MT9M114_VAR_CAM_PORT_PORCH 0xC986 -#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_HS_ZERO 0xC988 -#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_HS_EXIT_HS_TRAIL 0xC98A -#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_CLK_POST_CLK_PRE 0xC98C -#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_CLK_ZERO 0xC98E -#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_T_LPX 0xC990 -#define MT9M114_VAR_CAM_PORT_MIPI_TIMING_INIT_TIMING 0xC992 - -/* 10.UVC_Control variables */ -#define MT9M114_VAR_UVC_AE_MODE_CONTROL 0xCC00 -#define MT9M114_VAR_UVC_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0xCC01 -#define MT9M114_VAR_UVC_AE_PRIORITY_CONTROL 0xCC02 -#define MT9M114_VAR_UVC_POWER_LINE_FREQUENCY_CONTROL 0xCC03 -#define MT9M114_VAR_UVC_EXPOSURE_TIME_ABSOLUTE_CONTROL 0xCC04 -#define MT9M114_VAR_UVC_BACKLIGHT_COMPENSATION_CONTROL 0xCC08 -#define MT9M114_VAR_UVC_BRIGHTNESS_CONTROL 0xCC0A -#define MT9M114_VAR_UVC_CONTRAST_CONTROL 0xCC0C -#define MT9M114_VAR_UVC_GAIN_CONTROL 0xCC0E -#define MT9M114_VAR_UVC_HUE_CONTROL 0xCC10 -#define MT9M114_VAR_UVC_SATURATION_CONTROL 0xCC12 -#define MT9M114_VAR_UVC_SHARPNESS_CONTROL 0xCC14 -#define MT9M114_VAR_UVC_GAMMA_CONTROL 0xCC16 -#define MT9M114_VAR_UVC_WHITE_BALANCE_TEMPERATURE_CONTROL 0xCC18 -#define MT9M114_VAR_UVC_FRAME_INTERVAL_CONTROL 0xCC1C -#define MT9M114_VAR_UVC_MANUAL_EXPOSURE_CONFIGURATION 0xCC20 -#define MT9M114_VAR_UVC_FLICKER_AVOIDANCE_CONFIGURATION 0xCC21 -#define MT9M114_VAR_UVC_ALGO 0xCC22 -#define MT9M114_VAR_UVC_RESULT_STATUS 0xCC24 - -/* 11.SystemManager variables */ -#define MT9M114_VAR_SYSMGR_NEXT_STATE 0xDC00 -#define MT9M114_VAR_SYSMGR_CURRENT_STATE 0xDC01 -#define MT9M114_VAR_SYSMGR_CMD_STATUS 0xDC02 - -/* 12.PatchLoader variables */ -#define MT9M114_VAR_PATCHLDR_LOADER_ADDRESS 0xE000 -#define MT9M114_VAR_PATCHLDR_PATCH_ID 0xE002 -#define MT9M114_VAR_PATCHLDR_FIRMWARE_ID 0xE004 -#define MT9M114_VAR_PATCHLDR_APPLY_STATUS 0xE008 -#define MT9M114_VAR_PATCHLDR_NUM_PATCHES 0xE009 -#define MT9M114_VAR_PATCHLDR_PATCH_ID_0 0xE00A -#define MT9M114_VAR_PATCHLDR_PATCH_ID_1 0xE00C -#define MT9M114_VAR_PATCHLDR_PATCH_ID_2 0xE00E -#define MT9M114_VAR_PATCHLDR_PATCH_ID_3 0xE010 -#define MT9M114_VAR_PATCHLDR_PATCH_ID_4 0xE012 -#define MT9M114_VAR_PATCHLDR_PATCH_ID_5 0xE014 -#define MT9M114_VAR_PATCHLDR_PATCH_ID_6 0xE016 -#define MT9M114_VAR_PATCHLDR_PATCH_ID_7 0xE018 - -/* 13.Patch variables */ -#define MT9M114_VAR_PATCHVARS_DELTA_DK_CORRECTION_FACTOR 0xE400 -#define MT9M114_VAR_CAM_AUTO_BINNING_MODE (0xE801) - -/* 14.CommandHandler variables */ -#define MT9M114_VAR_CMD_HANDLER_WAIT_EVENT_ID 0xFC00 -#define MT9M114_VAR_CMD_HANDLER_NUM_EVENTS 0xFC02 - -/*! @brief MT9M114 command definitions. */ -#define MT9M114_COMMAND_APPLY_PATCH 0x0001 -#define MT9M114_COMMAND_SET_STATE 0x0002 -#define MT9M114_COMMAND_REFRESH 0x0004 -#define MT9M114_COMMAND_WAIT_FOR_EVENT 0x0008 -#define MT9M114_COMMAND_OK 0x8000 - -/*! @brief MT9M114 system state definitions. */ -#define MT9M114_SYS_STATE_ENTER_CONFIG_CHANGE 0x28 -#define MT9M114_SYS_STATE_STREAMING 0x31 -#define MT9M114_SYS_STATE_START_STREAMING 0x34 -#define MT9M114_SYS_STATE_ENTER_SUSPEND 0x40 -#define MT9M114_SYS_STATE_SUSPENDED 0x41 -#define MT9M114_SYS_STATE_ENTER_STANDBY 0x50 -#define MT9M114_SYS_STATE_STANDBY 0x52 -#define MT9M114_SYS_STATE_LEAVE_STANDBY 0x54 - -/*! @brief MT9M114 system set-state command retults. */ -#define MT9M114_SYS_STATE_SET_RESULT_ENOERR 0x00 /* command successful */ -#define MT9M114_SYS_STATE_SET_RESULTEINVAL 0x0C /* invalid configuration */ -#define MT9M114_SYS_STATE_SET_RESULTENOSPC 0x0D /* resource not available */ - -#define MT9M114_OUTPUT_FORMAT_SWAP_RB (1 << 0) -#define MT9M114_OUTPUT_FORMAT_SWAP_BYTES (1 << 1) -#define MT9M114_OUTPUT_FORMAT_MONO (1 << 2) -#define MT9M114_OUTPUT_FORMAT_BT656 (1 << 3) -#define MT9M114_OUTPUT_FORMAT_BT656_FIXED (1 << 4) -#define MT9M114_OUTPUT_FORMAT_YUV (0 << 8) -#define MT9M114_OUTPUT_FORMAT_RGB (1 << 8) -#define MT9M114_OUTPUT_FORMAT_BAYER (2 << 8) -#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10 (0 << 10) -#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_PRE (1 << 10) -#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_POST (2 << 10) -#define MT9M114_OUTPUT_FORMAT_PROCESSED_BAYER (3 << 10) -#define MT9M114_OUTPUT_FORMAT_RGB565 (0 << 12) -#define MT9M114_OUTPUT_FORMAT_RGB555 (1 << 12) -#define MT9M114_OUTPUT_FORMAT_XRGB444 (2 << 12) -#define MT9M114_OUTPUT_FORMAT_RGB444X (3 << 12) - -#define MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR (0x1) -#define MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP (0x2) -#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN_MASK (0x30) -#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN (0x30) -#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN_MASK (0x300) -#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN (0x300) - -#ifdef __cplusplus -extern "C" { -#endif -typedef struct { - uint16_t reg; /* 16bit reg address */ - uint8_t size; /* reg size in byte */ - uint32_t value; /* reg value */ -} mt9m114_reg_t; - -/*! - * @brief MT9M114 read register. - * - * @param[in] context camera_operate_context. - * @param[in] reg reg address(16 bits) - * @param[in] reg_size reg size in bytes - * @param[out] value reg data from device - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_read_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, void *value); - -/*! - * @brief MT9M114 write register. - * - * @param[in] context camera_operate_context. - * @param[in] reg reg address(16 bits) - * @param[in] reg_size reg size in bytes - * @param[in] value reg data to device - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_write_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t value); - -/*! - * @brief MT9M114 modify register. - * - * @param[in] context camera_operate_context. - * @param[in] reg reg address(16 bits) - * @param[in] reg_size reg size in bytes - * @param[in] mask bits can be modified - * @param[in] value value should be set - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_modify_register(camera_context_t *context, uint32_t reg, uint32_t reg_size, uint32_t mask, uint32_t value); - -/*! - * @brief MT9M114 multiwrite registers. - * - * @param[in] context camera_operate_context. - * @param[in] regs pointer to array of mt9m114_reg_t, include reg addr, reg size and value - * @param[in] num array size of [regs] - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_multiwrite(camera_context_t *context, const mt9m114_reg_t regs[], uint32_t num); - -/*! - * @brief MT9M114 check chipid. - * - * @param[in] context camera_operate_context. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_check_chip_id(camera_context_t *context); - -/*! - * @brief MT9M114 set next state and switch to it. - * - * @param[in] context camera_operate_context. - * @param[in] next_state next device state. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_setstate(camera_context_t *context, uint16_t next_state); - -/*! - * @brief MT9M114 get current state. - * - * @param[in] context camera_operate_context. - * @param[out] state current device state. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_get_current_state(camera_context_t *context, uint8_t *state); - -/*! - * @brief MT9M114 soft reset. - * - * @param[in] context camera_operate_context. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_software_reset(camera_context_t *context); - -/*! - * @brief MT9M114 set pixformat. - * - * @param[in] context camera_operate_context. - * @param[in] pixformat pixformat. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_set_pixformat(camera_context_t *context, display_pixel_format_t pixformat); - -/*! - * @brief MT9M114 set framerate. - * - * @param[in] context camera_operate_context. - * @param[in] framerate framerate. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_set_framerate(camera_context_t *context, int framerate); - -/*! - * @brief MT9M114 set brightness. - * - * @param[in] context camera_operate_context. - * @param[in] level brightness. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_set_brightness(camera_context_t *context, int level); - -/*! - * @brief MT9M114 start to transfer image data. - * - * @param[in] context camera_operate_context. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_start(camera_context_t *context); - -/*! - * @brief MT9M114 stop working and enter SUSPEND mode. - * - * @param[in] context camera_operate_context. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_stop(camera_context_t *context); - -/*! - * @brief MT9M114 enable or disable MONO mode. - * - * @param[in] context camera_operate_context. - * @param[in] enable enable or disable mono. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_enable_mono(camera_context_t *context, bool enable); - -/*! - * @brief MT9M114 initialization. - * - * @param[in] context camera_operate_context. - * - * @retval status_success if success. - * @retval status_fail if fail. - */ -hpm_stat_t mt9m114_init(camera_context_t *context, camera_config_t *camera_config); -#ifdef __cplusplus -} -#endif - -/** - * @} - * - */ - -#endif /* HPM_MT9M114_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c deleted file mode 100644 index b9d0b675b35..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_camera_ov5640.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ov5640.h" - -static camera_param_dvp_t camera_dvp_param = { - .hsync_active_low = true, - .vsync_active_low = false, -}; - -static camera_param_mipi_t camera_mipi_param = { - .de_active_low = true, - .hsync_active_low = false, - .vsync_active_low = false, -}; - -hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) -{ - assert(camera_context->delay_ms != NULL); - - hpm_stat_t stat = status_success; - - /* execute power up sequence */ - ov5640_power_up(camera_context); - - /* software reset */ - stat = ov5640_software_reset(camera_context); - if (stat != status_success) { - return stat; - } - camera_context->delay_ms(20); - - stat = ov5640_init(camera_context, camera_config); - - return stat; -} - -hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) -{ - (void)camera_context; - camera_config->interface_param = (void *)&camera_dvp_param; - return status_success; -} - -hpm_stat_t camera_device_get_mipi_param(camera_context_t *camera_context, camera_config_t *camera_config) -{ - (void)camera_context; - camera_config->interface_param = (void *)&camera_mipi_param; - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c deleted file mode 100644 index d6996143b57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.c +++ /dev/null @@ -1,895 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ov5640.h" - -static const ov5640_reg_val_t ov5640_init_param[] = { - {0x3008, 0x42}, - /* System setting. */ - {0x3103, 0x03}, - {0x3000, 0x00}, - {0x3004, 0xff}, - {0x3002, 0x1c}, - {0x3006, 0xc3}, - {0x302e, 0x08}, - {0x3037, 0x13}, - {0x3108, 0x01}, - {0x3618, 0x00}, - {0x3612, 0x29}, - {0x3708, 0x64}, - {0x3709, 0x52}, - {0x370c, 0x03}, - {0x3820, 0x41}, - {0x3821, 0x07}, - {0x3630, 0x36}, - {0x3631, 0x0e}, - {0x3632, 0xe2}, - {0x3633, 0x12}, - {0x3621, 0xe0}, - {0x3704, 0xa0}, - {0x3703, 0x5a}, - {0x3715, 0x78}, - {0x3717, 0x01}, - {0x370b, 0x60}, - {0x3705, 0x1a}, - {0x3905, 0x02}, - {0x3906, 0x10}, - {0x3901, 0x0a}, - {0x3731, 0x12}, - {0x3600, 0x08}, - {0x3601, 0x33}, - {0x302d, 0x60}, - {0x3620, 0x52}, - {0x371b, 0x20}, - {0x471c, 0x50}, - {0x3a13, 0x43}, - {0x3a18, 0x00}, - {0x3a19, 0x7c}, - {0x3635, 0x13}, - {0x3636, 0x03}, - {0x3634, 0x40}, - {0x3622, 0x01}, - {0x3c01, 0x00}, - {0x3a00, 0x58}, - {0x4001, 0x02}, - {0x4004, 0x02}, - {0x4005, 0x1a}, - {0x5001, 0xa3}, - - /* AEC */ - {0x3a0f, 0x30}, - {0x3a10, 0x28}, - {0x3a1b, 0x30}, - {0x3a1e, 0x26}, - {0x3a11, 0x60}, - {0x3a1f, 0x14}, - - /* AWB */ - {0x5180, 0xff}, - {0x5181, 0xf2}, - {0x5182, 0x00}, - {0x5183, 0x14}, - {0x5184, 0x25}, - {0x5185, 0x24}, - {0x5186, 0x09}, - {0x5187, 0x09}, - {0x5188, 0x09}, - {0x5189, 0x88}, - {0x518a, 0x54}, - {0x518b, 0xee}, - {0x518c, 0xb2}, - {0x518d, 0x50}, - {0x518e, 0x34}, - {0x518f, 0x6b}, - {0x5190, 0x46}, - {0x5191, 0xf8}, - {0x5192, 0x04}, - {0x5193, 0x70}, - {0x5194, 0xf0}, - {0x5195, 0xf0}, - {0x5196, 0x03}, - {0x5197, 0x01}, - {0x5198, 0x04}, - {0x5199, 0x6c}, - {0x519a, 0x04}, - {0x519b, 0x00}, - {0x519c, 0x09}, - {0x519d, 0x2b}, - {0x519e, 0x38}, - - /* Color Matrix */ - {0x5381, 0x1e}, - {0x5382, 0x5b}, - {0x5383, 0x08}, - {0x5384, 0x0a}, - {0x5385, 0x7e}, - {0x5386, 0x88}, - {0x5387, 0x7c}, - {0x5388, 0x6c}, - {0x5389, 0x10}, - {0x538a, 0x01}, - {0x538b, 0x98}, - - /* sharp */ - {0x5300, 0x08}, - {0x5301, 0x30}, - {0x5302, 0x10}, - {0x5303, 0x00}, - {0x5304, 0x08}, - {0x5305, 0x30}, - {0x5306, 0x08}, - {0x5307, 0x16}, - {0x5309, 0x08}, - {0x530a, 0x30}, - {0x530b, 0x04}, - {0x530c, 0x06}, - - /* Gamma */ - {0x5480, 0x01}, - {0x5481, 0x08}, - {0x5482, 0x14}, - {0x5483, 0x28}, - {0x5484, 0x51}, - {0x5485, 0x65}, - {0x5486, 0x71}, - {0x5487, 0x7d}, - {0x5488, 0x87}, - {0x5489, 0x91}, - {0x548a, 0x9a}, - {0x548b, 0xaa}, - {0x548c, 0xb8}, - {0x548d, 0xcd}, - {0x548e, 0xdd}, - {0x548f, 0xea}, - {0x5490, 0x1d}, - - /* UV adjust. */ - {0x5580, 0x02}, - {0x5583, 0x40}, - {0x5584, 0x10}, - {0x5589, 0x10}, - {0x558a, 0x00}, - {0x558b, 0xf8}, - - /* Lens correction. */ - {0x5800, 0x23}, - {0x5801, 0x14}, - {0x5802, 0x0f}, - {0x5803, 0x0f}, - {0x5804, 0x12}, - {0x5805, 0x26}, - {0x5806, 0x0c}, - {0x5807, 0x08}, - {0x5808, 0x05}, - {0x5809, 0x05}, - {0x580a, 0x08}, - {0x580b, 0x0d}, - {0x580c, 0x08}, - {0x580d, 0x03}, - {0x580e, 0x00}, - {0x580f, 0x00}, - {0x5810, 0x03}, - {0x5811, 0x09}, - {0x5812, 0x07}, - {0x5813, 0x03}, - {0x5814, 0x00}, - {0x5815, 0x01}, - {0x5816, 0x03}, - {0x5817, 0x08}, - {0x5818, 0x0d}, - {0x5819, 0x08}, - {0x581a, 0x05}, - {0x581b, 0x06}, - {0x581c, 0x08}, - {0x581d, 0x0e}, - {0x581e, 0x29}, - {0x581f, 0x17}, - {0x5820, 0x11}, - {0x5821, 0x11}, - {0x5822, 0x15}, - {0x5823, 0x28}, - {0x5824, 0x46}, - {0x5825, 0x26}, - {0x5826, 0x08}, - {0x5827, 0x26}, - {0x5828, 0x64}, - {0x5829, 0x26}, - {0x582a, 0x24}, - {0x582b, 0x22}, - {0x582c, 0x24}, - {0x582d, 0x24}, - {0x582e, 0x06}, - {0x582f, 0x22}, - {0x5830, 0x40}, - {0x5831, 0x42}, - {0x5832, 0x24}, - {0x5833, 0x26}, - {0x5834, 0x24}, - {0x5835, 0x22}, - {0x5836, 0x22}, - {0x5837, 0x26}, - {0x5838, 0x44}, - {0x5839, 0x24}, - {0x583a, 0x26}, - {0x583b, 0x28}, - {0x583c, 0x42}, - {0x583d, 0xce}, - {0x481c, 0x00}, - {0x481d, 0x1}, - - /* 50/60Hz detection */ - {0x3a02, 0x0b}, /* 60Hz max exposure, night mode 5fps */ - {0x3a03, 0x88}, /* 60Hz max exposure */ - {0x3a14, 0x0b}, /* 50Hz max exposure, night mode 5fps */ - {0x3a15, 0x88}, /* 50Hz max exposure */ - {0x3c01, 0x34}, /* Band auto, bit[7] */ - {0x3c04, 0x28}, /* threshold low sum */ - {0x3c05, 0x98}, /* threshold high sum */ - {0x3c06, 0x00}, /* light meter 1 threshold[15:8] */ - {0x3c07, 0x08}, /* light meter 1 threshold[7:0] */ - {0x3c08, 0x00}, /* light meter 2 threshold[15:8] */ - {0x3c09, 0x1c}, /* light meter 2 threshold[7:0] */ - {0x3c0a, 0x9c}, /* sample number[15:8] */ - {0x3c0b, 0x40}, /* sample number[7:0] */ - {0x3708, 0x64}, - {0x4001, 0x02}, /* BLC start from line 2 */ - {0x4005, 0x1a}, /* BLC always update */ - {0x3000, 0x00}, /* enable blocks */ - {0x3004, 0xff}, /* enable clocks */ - {0x302e, 0x00}, - {0x440e, 0x00}, - {0x5000, 0xa7}, /* Lenc on, raw gamma on, BPC on, WPC on, CIP on */ -}; - -/* Resolution configuration */ -static const ov5640_reg_val_t ov5640_resolution_800_480_param[] = { - {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, - {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, - {0x3808, 0x03}, {0x3809, 0x20}, {0x380A, 0x01}, {0x380B, 0xe0}, - {0x380C, 0x07}, {0x380D, 0x68}, {0x380E, 0x03}, {0x380F, 0xd8}, - {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, -}; - -static const ov5640_reg_val_t ov5640_resolution_vga_param[] = { - {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, - {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, - {0x3808, 0x02}, {0x3809, 0x80}, {0x380A, 0x01}, {0x380B, 0xe0}, - {0x380C, 0x07}, {0x380D, 0x68}, {0x380E, 0x03}, {0x380F, 0xd8}, - {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, -}; - -static const ov5640_reg_val_t ov5640_resolution_qvga_param[] = { - {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, - {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, - {0x3808, 0x01}, {0x3809, 0x40}, {0x380A, 0x00}, {0x380B, 0xf0}, - {0x380C, 0x07}, {0x380D, 0x68}, {0x380E, 0x03}, {0x380F, 0xd8}, - {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06}, {0x3814, 0x31}, {0x3815, 0x31}, -}; - -static const ov5640_reg_val_t ov5640_resolution_480_272_param[] = { - {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0xfa}, - {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x06}, {0x3807, 0xa9}, - {0x3808, 0x01}, {0x3809, 0xE0}, {0x380A, 0x01}, {0x380B, 0x10}, - {0x380C, 0x07}, {0x380D, 0x64}, {0x380E, 0x02}, {0x380F, 0xe4}, - {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x04}, {0x3814, 0x31}, {0x3815, 0x31}, -}; - -static const ov5640_reg_val_t ov5640_resolution_720p_param[] = { - {0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0xfa}, - {0x3804, 0x0a}, {0x3805, 0x3f}, {0x3806, 0x06}, {0x3807, 0xa9}, - {0x3808, 0x05}, {0x3809, 0x00}, {0x380A, 0x02}, {0x380B, 0xd0}, - {0x380C, 0x07}, {0x380D, 0x64}, {0x380E, 0x02}, {0x380F, 0xe4}, - {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x04}, {0x3814, 0x31}, {0x3815, 0x31}, -}; - -static const ov5640_reg_val_t ov5640_resolution_1080p_param[] = { - {0x3800, 0x01}, {0x3801, 0x50}, {0x3802, 0x01}, {0x3803, 0xb2}, - {0x3804, 0x08}, {0x3805, 0xef}, {0x3806, 0x05}, {0x3807, 0xf1}, - {0x3808, 0x07}, {0x3809, 0x80}, {0x380A, 0x04}, {0x380B, 0x38}, - {0x380C, 0x09}, {0x380D, 0xc4}, {0x380E, 0x04}, {0x380F, 0x60}, - {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x04}, {0x3814, 0x11}, {0x3815, 0x11}, -}; - -/* DVP clock */ -static const ov5640_clock_config_t ov5640_dvp_clock_configs[] = { - { - .resolution = (uint32_t)video_resolution_800_480, - .pllctrl1 = 0x11, - .pllctrl2 = 0x46, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x22, - }, - { - .resolution = (uint32_t)video_resolution_vga, - .pllctrl1 = 0x11, - .pllctrl2 = 0x46, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x22, - }, - { - .resolution = (uint32_t)video_resolution_qvga, - .pllctrl1 = 0x11, - .pllctrl2 = 0x46, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x22, - }, - { - .resolution = (uint32_t)video_resolution_480_272, - .pllctrl1 = 0x21, - .pllctrl2 = 0x69, - .vfifoctrl0c = 0x20, - .pclkdiv = 0x04, - .pclkperiod = 0x16, - }, - { - .resolution = (uint32_t)video_resolution_720p, - .pllctrl1 = 0x21, - .pllctrl2 = 0x69, - .vfifoctrl0c = 0x20, - .pclkdiv = 0x04, - .pclkperiod = 0x16, - }, - { - .resolution = (uint32_t)video_resolution_1080p, - .pllctrl1 = 0x21, - .pllctrl2 = 0x69, - .vfifoctrl0c = 0x20, - .pclkdiv = 0x04, - .pclkperiod = 0x16, - }, -}; - -/* MIPI clock */ -static const ov5640_clock_config_t ov5640_mipi_clock_configs[] = { - { - .resolution = (uint32_t)video_resolution_800_480, - .pllctrl1 = 0x14, - .pllctrl2 = 0x38, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x0a, - }, - { - .resolution = (uint32_t)video_resolution_vga, - .pllctrl1 = 0x14, - .pllctrl2 = 0x38, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x0a, - }, - { - .resolution = (uint32_t)video_resolution_qvga, - .pllctrl1 = 0x14, - .pllctrl2 = 0x38, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x0a, - }, - { - .resolution = (uint32_t)video_resolution_480_272, - .pllctrl1 = 0x14, - .pllctrl2 = 0x38, - .vfifoctrl0c = 0x22, - .pclkdiv = 0x02, - .pclkperiod = 0x0a, - }, - { - .resolution = (uint32_t)video_resolution_720p, - .pllctrl1 = 0x21, - .pllctrl2 = 0x54, - .vfifoctrl0c = 0x20, - .pclkdiv = 0x04, - .pclkperiod = 0x0a, - }, - { - .resolution = (uint32_t)video_resolution_1080p, - .pllctrl1 = 0x11, - .pllctrl2 = 0x54, - .vfifoctrl0c = 0x20, - .pclkdiv = 0x04, - .pclkperiod = 0x0a, - }, -}; - -static const ov5640_light_mode_config_t ov5640_light_mode_configs[] = { - /* Auto. */ - { - .lightmode = camera_light_mode_auto, - .awbctrl = 0x00, - .awbr_h = 0x04, - .awbr_l = 0x00, - .awbg_h = 0x04, - .awbg_l = 0x00, - .awbb_h = 0x04, - .awbb_l = 0x00, - }, - /* Sunny. */ - { - .lightmode = camera_light_mode_sunny, - .awbctrl = 0x01, - .awbr_h = 0x06, - .awbr_l = 0x1c, - .awbg_h = 0x04, - .awbg_l = 0x00, - .awbb_h = 0x04, - .awbb_l = 0xf3, - }, - /* Office. */ - { - .lightmode = camera_light_mode_office, - .awbctrl = 0x01, - .awbr_h = 0x05, - .awbr_l = 0x48, - .awbg_h = 0x04, - .awbg_l = 0x00, - .awbb_h = 0x07, - .awbb_l = 0xcf, - }, - /* Cloudy. */ - { - .lightmode = camera_light_mode_cloudy, - .awbctrl = 0x01, - .awbr_h = 0x06, - .awbr_l = 0x48, - .awbg_h = 0x04, - .awbg_l = 0x00, - .awbb_h = 0x04, - .awbb_l = 0xd3, - }, - /* Home. */ - { - .lightmode = camera_light_mode_home, - .awbctrl = 0x01, - .awbr_h = 0x04, - .awbr_l = 0x10, - .awbg_h = 0x04, - .awbg_l = 0x00, - .awbb_h = 0x08, - .awbb_l = 0x40, - }, -}; - -static const ov5640_special_effect_config_t ov5640_special_effect_configs[] = { - /* Normal. */ - { - .effect = camera_special_effect_normal, - .sdectrl0 = 0x06, - .sdectrl3 = 0x40, - .sdectrl4 = 0x10, - }, - /* Bluish. */ - { - .effect = camera_special_effect_bluish, - .sdectrl0 = 0x1e, - .sdectrl3 = 0xa0, - .sdectrl4 = 0x40, - }, - /* Redish. */ - { - .effect = camera_special_effect_redish, - .sdectrl0 = 0x1e, - .sdectrl3 = 0x80, - .sdectrl4 = 0xc0, - }, - /* B & W */ - { - .effect = camera_special_effect_bw, - .sdectrl0 = 0x1e, - .sdectrl3 = 0x80, - .sdectrl4 = 0x80, - }, - /* Sepia. */ - { - .effect = camera_special_effect_sepia, - .sdectrl0 = 0x1e, - .sdectrl3 = 0x40, - .sdectrl4 = 0xa0, - }, - /* Negtive. */ - { - .effect = camera_special_effect_negtive, - .sdectrl0 = 0x40, - .sdectrl3 = 0x40, - .sdectrl4 = 0x10, - }, - /* Greenish. */ - { - .effect = camera_special_effect_greenish, - .sdectrl0 = 0x1e, - .sdectrl3 = 0x60, - .sdectrl4 = 0x60, - }, -}; - -static const ov5640_clock_config_t *ov5640_get_clock_config(const camera_config_t *config) -{ - uint32_t i; - - if (camera_interface_dvp == config->interface) { - for (i = 0; i < ARRAY_SIZE(ov5640_dvp_clock_configs); i++) { - if (HPM_CAMERA_RESOLUTION(config->width, config->height) == ov5640_dvp_clock_configs[i].resolution) { - return &ov5640_dvp_clock_configs[i]; - } - } - } else if (camera_interface_mipi == config->interface) { - for (i = 0; i < ARRAY_SIZE(ov5640_mipi_clock_configs); i++) { - if (HPM_CAMERA_RESOLUTION(config->width, config->height) == ov5640_mipi_clock_configs[i].resolution) { - return &ov5640_mipi_clock_configs[i]; - } - } - } - - return NULL; -} - -hpm_stat_t ov5640_read_register(camera_context_t *context, uint16_t reg, uint8_t *buf) -{ - uint8_t r[2]; - r[0] = reg >> 8; - r[1] = reg & 0xFF; - - hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, r, 2); - if (stat != status_success) { - return stat; - } - return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1); -} - -hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_t val) -{ - uint8_t r[2]; - r[0] = reg >> 8; - r[1] = reg & 0xFF; - return i2c_master_address_write(context->ptr, context->i2c_device_addr, r, sizeof(r), &val, 1); -} - -hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_reg_val_t regval[], uint32_t len) -{ - uint32_t i; - hpm_stat_t stat = status_success; - - for (i = 0; i < len; i++) { - HPM_CHECK_RET(ov5640_write_register(context, regval[i].regaddr, regval[i].regval)); - } - - return stat; -} - -hpm_stat_t ov5640_software_reset(camera_context_t *context) -{ - hpm_stat_t stat = status_success; - - HPM_CHECK_RET(ov5640_write_register(context, 0x3103, 0x11)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3008, 0x82)); - - return stat; -} - -hpm_stat_t ov5640_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format) -{ - hpm_stat_t stat = status_success; - - switch (pixel_format) { - case display_pixel_format_y8: - case display_pixel_format_yuv422: - HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x30)); - HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); - break; - case display_pixel_format_ycbcr422: - HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x32)); - HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x00)); - break; - case display_pixel_format_rgb565: - HPM_CHECK_RET(ov5640_write_register(context, 0x4300, 0x6F)); - HPM_CHECK_RET(ov5640_write_register(context, 0x501f, 0x01)); - break; - default: - stat = status_invalid_argument; - break; - } - - return stat; -} - -hpm_stat_t ov5640_check_chip_id(camera_context_t *context) -{ - hpm_stat_t stat = status_success; - uint8_t val_h = 0; - uint8_t val_l = 0; - - HPM_CHECK_RET(ov5640_read_register(context, OV5640_CHIP_ID_HIGH_BYTE_ADDR, &val_h)); - HPM_CHECK_RET(ov5640_read_register(context, OV5640_CHIP_ID_LOW_BYTE_ADDR, &val_l)); - - if (val_h != OV5640_CHIP_ID_HIGH_BYTE_VALUE) { - return status_fail; - } - - if (val_l != OV5640_CHIP_ID_LOW_BYTE_VALUE) { - return status_fail; - } - - return stat; -} - -hpm_stat_t ov5640_set_image_size(camera_context_t *context, camera_config_t *ov_config) -{ - hpm_stat_t stat = status_success; - - switch (HPM_CAMERA_RESOLUTION(ov_config->width, ov_config->height)) { - case video_resolution_800_480: - stat = ov5640_write_multi_registers(context, ov5640_resolution_800_480_param, ARRAY_SIZE(ov5640_resolution_800_480_param)); - break; - case video_resolution_vga: - stat = ov5640_write_multi_registers(context, ov5640_resolution_vga_param, ARRAY_SIZE(ov5640_resolution_vga_param)); - break; - case video_resolution_qvga: - stat = ov5640_write_multi_registers(context, ov5640_resolution_qvga_param, ARRAY_SIZE(ov5640_resolution_qvga_param)); - break; - case video_resolution_480_272: - stat = ov5640_write_multi_registers(context, ov5640_resolution_480_272_param, ARRAY_SIZE(ov5640_resolution_480_272_param)); - break; - case video_resolution_720p: - stat = ov5640_write_multi_registers(context, ov5640_resolution_720p_param, ARRAY_SIZE(ov5640_resolution_720p_param)); - break; - case video_resolution_1080p: - stat = ov5640_write_multi_registers(context, ov5640_resolution_1080p_param, ARRAY_SIZE(ov5640_resolution_1080p_param)); - break; - default: - stat = status_invalid_argument; - break; - } - - return stat; -} - -hpm_stat_t ov5640_set_clock_config(camera_context_t *context, camera_config_t *ov_config) -{ - hpm_stat_t stat = status_success; - const ov5640_clock_config_t *clock_config = ov5640_get_clock_config(ov_config); - - if (NULL == clock_config) { - return status_invalid_argument; - } - - HPM_CHECK_RET(ov5640_write_register(context, 0x3035, clock_config->pllctrl1)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3036, clock_config->pllctrl2)); - HPM_CHECK_RET(ov5640_write_register(context, 0x460c, clock_config->vfifoctrl0c)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3824, clock_config->pclkdiv)); - HPM_CHECK_RET(ov5640_write_register(context, 0x4837, clock_config->pclkperiod)); - - return stat; -} - -hpm_stat_t ov5640_set_interface(camera_context_t *context, camera_config_t *ov_config) -{ - hpm_stat_t stat = status_success; - - if (camera_interface_dvp == ov_config->interface) { - HPM_CHECK_RET(ov5640_write_register(context, 0x3034, 0x1a)); - - /* Set Frex, Vsync, Href, PCLK, data, GPIO to output. */ - HPM_CHECK_RET(ov5640_write_register(context, 0x3017, 0xFF)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3018, 0xFF)); - - /* DVP mode */ - HPM_CHECK_RET(ov5640_write_register(context, 0x300e, 0x58)); - } else if (camera_interface_mipi == ov_config->interface) { - HPM_CHECK_RET(ov5640_write_register(context, 0x481D, 0x20)); - HPM_CHECK_RET(ov5640_write_register(context, 0x481C, 0x0)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3034, 0x18)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3017, 0x00)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3018, 0x00)); - /* 2lanes mode */ - HPM_CHECK_RET(ov5640_write_register(context, 0x300e, 0x45)); - HPM_CHECK_RET(ov5640_write_register(context, 0x302e, 0x08)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x4800, 0x04)); - } - - return stat; -} - -hpm_stat_t ov5640_start(camera_context_t *context) -{ - return ov5640_write_register(context, 0x3008, 0x02); -} - -hpm_stat_t ov5640_stop(camera_context_t *context) -{ - return ov5640_write_register(context, 0x3008, 0x42); -} - -hpm_stat_t ov5640_flip(camera_context_t *context) -{ - hpm_stat_t stat = status_success; - HPM_CHECK_RET(ov5640_write_register(context, 0x3821, 1)); - return stat; -} - - -hpm_stat_t ov5640_set_brightness(camera_context_t *context, int32_t brightness) -{ - hpm_stat_t stat = status_success; - - if ((brightness < -4) || (brightness > 4)) { - return status_invalid_argument; - } - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); - if (brightness >= 0) { - HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x01)); - } else { - brightness = -brightness; - HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x09)); - } - - HPM_CHECK_RET(ov5640_write_register(context, 0x5587, ((uint8_t)brightness) << 4U)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); - - return stat; -} - -hpm_stat_t ov5640_set_contrast(camera_context_t *context, int32_t contrast) -{ - hpm_stat_t stat = status_success; - uint8_t regval; - - if ((-4 > contrast) || (4 < contrast)) { - return status_invalid_argument; - } - - contrast = 0x20 + contrast * 0x04; - regval = (uint8_t)contrast; - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x5580, 0x04)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5585, regval)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5586, regval)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); - - return stat; -} - -hpm_stat_t ov5640_set_saturation(camera_context_t *context, int32_t saturation) -{ - hpm_stat_t stat = status_success; - uint8_t regval; - - if ((-4 > saturation) || (4 < saturation)) { - return status_invalid_argument; - } - - saturation = 0x40 + saturation * 0x10; - regval = (uint8_t)saturation; - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x5580, 0x02)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5583, regval)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5584, regval)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5588, 0x41)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); - - return stat; -} - -hpm_stat_t ov5640_set_light_mode(camera_context_t *context, int32_t lightmode) -{ - hpm_stat_t stat = status_success; - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(ov5640_light_mode_configs); i++) { - if (lightmode == (int32_t)ov5640_light_mode_configs[i].lightmode) { - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x3406, ov5640_light_mode_configs[i].awbctrl)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3400, ov5640_light_mode_configs[i].awbr_h)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3401, ov5640_light_mode_configs[i].awbr_l)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3402, ov5640_light_mode_configs[i].awbg_h)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3403, ov5640_light_mode_configs[i].awbg_l)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3404, ov5640_light_mode_configs[i].awbb_h)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3405, ov5640_light_mode_configs[i].awbb_l)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); - - return stat; - } - } - - /* No configuration found. */ - return status_invalid_argument; -} - -hpm_stat_t ov5640_set_special_effect(camera_context_t *context, int32_t effect) -{ - hpm_stat_t stat = status_success; - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(ov5640_special_effect_configs); i++) { - if (effect == (int32_t)ov5640_special_effect_configs[i].effect) { - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x03)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x5580, ov5640_special_effect_configs[i].sdectrl0)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5583, ov5640_special_effect_configs[i].sdectrl3)); - HPM_CHECK_RET(ov5640_write_register(context, 0x5584, ov5640_special_effect_configs[i].sdectrl4)); - - HPM_CHECK_RET(ov5640_write_register(context, 0x5003, 0x08)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0x13)); - HPM_CHECK_RET(ov5640_write_register(context, 0x3212, 0xa3)); - - return stat; - } - } - - /* No configuration found. */ - return status_invalid_argument; -} - -hpm_stat_t ov5640_init(camera_context_t *context, camera_config_t *ov_config) -{ - hpm_stat_t stat = status_success; - - /* check the chip id */ - HPM_CHECK_RET(ov5640_check_chip_id(context)); - - /* Initialize: load registers value */ - HPM_CHECK_RET(ov5640_write_multi_registers(context, ov5640_init_param, ARRAY_SIZE(ov5640_init_param))); - - /* configure image windowing */ - HPM_CHECK_RET(ov5640_set_image_size(context, ov_config)); - - HPM_CHECK_RET(ov5640_flip(context)); - - /* configure Pixel format */ - HPM_CHECK_RET(ov5640_set_pixel_format(context, ov_config->pixel_format)); - - /* configure PCLK clock */ - HPM_CHECK_RET(ov5640_set_clock_config(context, ov_config)); - - /* configure interface */ - HPM_CHECK_RET(ov5640_set_interface(context, ov_config)); - - /* configure contrast */ - HPM_CHECK_RET(ov5640_set_contrast(context, 2)); - - /* camera start */ - HPM_CHECK_RET(ov5640_write_register(context, 0x3008, 0x02)); - - return stat; -} - -void ov5640_power_up(camera_context_t *context) -{ - assert(context->delay_ms != NULL); - - if (context->write_rst) { - context->write_rst(OV5640_RST_ACTIVE); - } - if (context->write_pwdn) { - context->write_pwdn(OV5640_PWDN_ACTIVE); - } - context->delay_ms(5); - if (context->write_pwdn) { - context->write_pwdn(OV5640_PWDN_INACTIVE); - } - context->delay_ms(2); - if (context->write_rst) { - context->write_rst(OV5640_RST_INACTIVE); - } - context->delay_ms(20); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h deleted file mode 100644 index d7ab07abbca..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov5640/hpm_ov5640.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_OV5640_H -#define HPM_OV5640_H - -#include "hpm_common.h" -#include "hpm_camera_config.h" - -#define OV5640_ACTIVE_IMAGE_WIDTH (2592U) -#define OV5640_ACTIVE_IMAGE_HEIGHT (1944U) -#define OV5640_I2C_ADDR (0x3CU) -#define OV5640_CHIP_ID_HIGH_BYTE_ADDR (0x300A) -#define OV5640_CHIP_ID_HIGH_BYTE_VALUE (0x56) -#define OV5640_CHIP_ID_LOW_BYTE_ADDR (0x300B) -#define OV5640_CHIP_ID_LOW_BYTE_VALUE (0x40) - -#define OV5640_RST_ACTIVE 0 -#define OV5640_RST_INACTIVE 1 -#define OV5640_PWDN_ACTIVE 1 -#define OV5640_PWDN_INACTIVE 0 - -/* Camera clock configuration elements. */ -typedef struct { - uint32_t resolution; - uint8_t fps; - uint8_t pllctrl1; - uint8_t pllctrl2; - uint8_t vfifoctrl0c; - uint8_t pclkdiv; - uint8_t pclkperiod; -} ov5640_clock_config_t; - -typedef struct { - uint8_t lightmode; - uint8_t awbctrl; - uint8_t awbr_h; - uint8_t awbr_l; - uint8_t awbg_h; - uint8_t awbg_l; - uint8_t awbb_h; - uint8_t awbb_l; -} ov5640_light_mode_config_t; - -typedef struct { - uint8_t effect; - uint8_t sdectrl0; - uint8_t sdectrl3; - uint8_t sdectrl4; -} ov5640_special_effect_config_t; - -typedef struct { - uint16_t regaddr; - uint8_t regval; -} ov5640_reg_val_t; - -typedef struct { - uint32_t resolution; /*!< Resolution. */ - ov5640_reg_val_t param[]; /*!< register value from 0x3800 to 0x3813. */ -} ov5640_resolution_param_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * ov5640 initialization - */ -hpm_stat_t ov5640_init(camera_context_t *context, camera_config_t *ov_config); - -/* - * ov5640 read register - */ -hpm_stat_t ov5640_read_register(camera_context_t *context, uint16_t reg, uint8_t *buf); - -/* - * ov5640 write register - */ -hpm_stat_t ov5640_write_register(camera_context_t *context, uint16_t reg, uint8_t val); - -/* - * ov5640 write multi register - */ -hpm_stat_t ov5640_write_multi_registers(camera_context_t *context, const ov5640_reg_val_t regval[], uint32_t len); - -/* - * ov5640 softreset - */ -hpm_stat_t ov5640_software_reset(camera_context_t *context); - -/* - * ov5640 set pixel format - */ -hpm_stat_t ov5640_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format); - -/* - * ov5640 check chip id - */ -hpm_stat_t ov5640_check_chip_id(camera_context_t *context); - -/* - * ov5640 set image size - */ -hpm_stat_t ov5640_set_image_size(camera_context_t *context, camera_config_t *ov_config); - -/* - * ov5640 set clock config - */ -hpm_stat_t ov5640_set_clock_config(camera_context_t *context, camera_config_t *ov_config); - -/* - * ov5640 set interface - */ -hpm_stat_t ov5640_set_interface(camera_context_t *context, camera_config_t *ov_config); - -/** - * @brief set ov5640 flip - * - * @param context @ref camera_context_t - * @return hpm_stat_t - */ -hpm_stat_t ov5640_flip(camera_context_t *context); - -/* - * ov5640 start - */ -hpm_stat_t ov5640_start(camera_context_t *context); - -/* - * ov5640 stop - */ -hpm_stat_t ov5640_stop(camera_context_t *context); - -/* - * ov5640 set brightness - */ -hpm_stat_t ov5640_set_brightness(camera_context_t *context, int32_t brightness); - -/* - * ov5640 set contrast - */ -hpm_stat_t ov5640_set_contrast(camera_context_t *context, int32_t contrast); - -/* - * ov5640 set saturation - */ -hpm_stat_t ov5640_set_saturation(camera_context_t *context, int32_t saturation); - -/* - * ov5640 set environment light mode - */ -hpm_stat_t ov5640_set_light_mode(camera_context_t *context, int32_t lightmode); - -/* - * ov5640 set special effect - */ -hpm_stat_t ov5640_set_special_effect(camera_context_t *context, int32_t effect); - -/** - * @brief ov5640 power up - * - * @param [in] context camera_context_t - */ -void ov5640_power_up(camera_context_t *context); - -#ifdef __cplusplus -} -#endif -#endif /* HPM_OV5640_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c deleted file mode 100644 index 1c436b7280b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_camera_ov7725.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ov7725.h" - -static camera_param_dvp_t camera_dvp_param = { - .hsync_active_low = true, - .vsync_active_low = false, -}; - -hpm_stat_t camera_device_init(camera_context_t *camera_context, camera_config_t *camera_config) -{ - assert(camera_context->delay_ms != NULL); - - hpm_stat_t stat = status_success; - - /* execute power up sequence */ - ov7725_power_up(camera_context); - - /* software reset */ - stat = ov7725_software_reset(camera_context); - if (stat != status_success) { - return stat; - } - camera_context->delay_ms(50); - - stat = ov7725_init(camera_context, camera_config); - - return stat; -} - -hpm_stat_t camera_device_get_dvp_param(camera_context_t *camera_context, camera_config_t *camera_config) -{ - (void)camera_context; - camera_config->interface_param = (void *)&camera_dvp_param; - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c deleted file mode 100644 index 8e6c09f4e22..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ov7725.h" - -static const uint8_t ov7725_default_regs[][2] = { - {COM4, 0x41}, /* bypass PLL */ - - /* - * VGA Window Size - */ - {HSTART, 0x22}, - {HSIZE, 0xa4}, - {VSTART, 0x07}, - {VSIZE, 0xf0}, - {HREF, 0x00}, - - /* - * Scale down to VGA Resolution - */ - {HOUTSIZE, 0xA0}, - {VOUTSIZE, 0xF0}, - - {COM12, 0x03}, - {EXHCH, 0x00}, - {TGT_B, 0x7F}, - {FIXGAIN, 0x09}, - {AWB_CTRL0, 0xE0}, - {DSP_CTRL1, 0xFF}, - {DSP_CTRL2, 0x20}, - {DSP_CTRL3, 0x00}, - {DSP_CTRL4, 0x00}, - - {COM8, 0xF8}, - {COM6, 0xC5}, - {COM9, 0x11}, - {COM10, COM10_VSYNC_NEG | COM10_PCLK_MASK}, /* Invert VSYNC and MASK PCLK */ - {BDBASE, 0x7F}, - {DBSTEP, 0x03}, - {AEW, 0x70}, - {AEB, 0x43}, - {VPT, 0xA1}, - {EXHCL, 0x00}, - {AWB_CTRL3, 0xAA}, - {COM8, 0xFF}, - - /* - * Gamma - */ - {GAM1, 0x0C}, - {GAM2, 0x16}, - {GAM3, 0x2A}, - {GAM4, 0x4E}, - {GAM5, 0x61}, - {GAM6, 0x6F}, - {GAM7, 0x7B}, - {GAM8, 0x86}, - {GAM9, 0x8E}, - {GAM10, 0x97}, - {GAM11, 0xA4}, - {GAM12, 0xAF}, - {GAM13, 0xC5}, - {GAM14, 0xD7}, - {GAM15, 0xE8}, - - {SLOP, 0x20}, - {EDGE1, 0x05}, - {EDGE2, 0x03}, - {EDGE3, 0x00}, - {DNSOFF, 0x01}, - - {MTX1, 0xB0}, - {MTX2, 0x9D}, - {MTX3, 0x13}, - {MTX4, 0x16}, - {MTX5, 0x7B}, - {MTX6, 0x91}, - {MTX_CTRL, 0x1E}, - - {BRIGHTNESS, 0x08}, - {CONTRAST, 0x20}, - {UVADJ0, 0x81}, - {SDE, (SDE_CONT_BRIGHT_EN | SDE_SATURATION_EN)}, - - /* - * For 30 fps/60Hz - */ - {DM_LNL, 0x00}, - {DM_LNH, 0x00}, - {BDBASE, 0x7F}, - {DBSTEP, 0x03}, - - /* - * Lens Correction, should be tuned with real camera module - */ - {LC_RADI, 0x10}, - {LC_COEF, 0x10}, - {LC_COEFB, 0x14}, - {LC_COEFR, 0x17}, - {LC_CTR, 0x05}, - {COM5, 0x65}, -}; - - -static const uint8_t ov7725_default_yuv_regs[][2] = { - {COM12, 0x03}, - {HSTART, 0x22}, - {HSIZE, 0xa4}, - {VSTART, 0x07}, - {VSIZE, 0xf0}, - {HREF, 0x00}, - {HOUTSIZE, 0xa0}, - {VOUTSIZE, 0xf0}, - {EXHCH, 0x00}, - {CLKRC, 0x01}, - {TGT_B, 0x7f}, - {FIXGAIN, 0x09}, - {AWB_CTRL0, 0xe0}, - {DSP_CTRL1, 0xff}, - {DSP_CTRL2, 0x20}, - {DSP_CTRL3, 0x00}, - {DSP_CTRL4, 0x48}, - {COM8, 0xf0}, - {COM4, 0x41}, /* 0x51/ 0x61/ 0x71 for different AEC/AGC window */ - {COM6, 0xc5}, - {COM9, 0x11}, - {BDBASE, 0x7f}, - {DBSTEP, 0x03}, - {AEW, 0x40}, - {AEB, 0x30}, - {VPT, 0xa1}, - {EXHCL, 0x00}, - {AWB_CTRL3, 0xaa}, - {COM8, 0xff}, - {EDGE1, 0x05}, - {DNSOFF, 0x01}, - {EDGE2, 0x03}, - {EDGE3, 0x00}, - {MTX1, 0xb0}, - {MTX2, 0x9d}, - {MTX3, 0x13}, - {MTX4, 0x16}, - {MTX5, 0x7b}, - {MTX6, 0x91}, - {MTX_CTRL, 0x1e}, - {BRIGHTNESS, 0x08}, - {CONTRAST, 0x20}, - {UVADJ0, 0x81}, - {SDE, 0x06}, - /* Gamma */ - {GAM1, 0x0c}, - {GAM2, 0x16}, - {GAM3, 0x2a}, - {GAM4, 0x4e}, - {GAM5, 0x61}, - {GAM6, 0x6f}, - {GAM7, 0x7b}, - {GAM8, 0x86}, - {GAM9, 0x8e}, - {GAM10, 0x97}, - {GAM11, 0xa4}, - {GAM12, 0xaf}, - {GAM13, 0xc5}, - {GAM14, 0xd7}, - {GAM15, 0xe8}, - {SLOP, 0x20}, - /* for 30 fps,0Hz */ - {DM_LNL, 0x00}, - {BDBASE, 0x7f}, - {DBSTEP, 0x03}, - - /* Lens Correcon, should be tuned with real camera module */ - {LC_RADI, 0x10}, - {LC_COEF, 0x10}, - {LC_COEFB, 0x14}, - {LC_COEFR, 0x17}, - {LC_CTR, 0x05}, - {COM5, 0x65}, -}; - -hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf) -{ - hpm_stat_t stat = i2c_master_write(context->ptr, context->i2c_device_addr, ®, 1); - if (stat != status_success) { - return stat; - } - return i2c_master_read(context->ptr, context->i2c_device_addr, buf, 1); - -} - -hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val) -{ - return i2c_master_address_write(context->ptr, context->i2c_device_addr, ®, 1, &val, 1); -} - -hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count) -{ - hpm_stat_t stat = status_success; - for (uint32_t i = 0, j = 0; i < count; i++, j += 2) { - stat = ov7725_write_register(context, reg_values[j], reg_values[j+1]); - if (stat != status_success) { - break; - } - } - return stat; -} - -hpm_stat_t ov7725_software_reset(camera_context_t *context) -{ - hpm_stat_t stat = status_success; - - stat = ov7725_write_register(context, COM7, COM7_RESET); - if (stat != status_success) { - return stat; - } - - return stat; -} - -hpm_stat_t ov7725_check_chip_id(camera_context_t *context) -{ - hpm_stat_t stat = status_success; - uint8_t val_h = 0; - uint8_t val_l = 0; - - HPM_CHECK_RET(ov7725_read_register(context, OV7725_CHIP_ID_HIGH_BYTE_ADDR, &val_h)); - HPM_CHECK_RET(ov7725_read_register(context, OV7725_CHIP_ID_LOW_BYTE_ADDR, &val_l)); - - if (val_h != OV7725_CHIP_ID_HIGH_BYTE_VALUE) { - return status_fail; - } - - if (val_l != OV7725_CHIP_ID_LOW_BYTE_VALUE) { - return status_fail; - } - - return stat; -} - -static hpm_stat_t ov7725_set_framesize(camera_context_t *context, uint16_t width, uint16_t height) -{ - hpm_stat_t stat = status_success; - uint32_t hstart = 0x22U << 2; - uint32_t vstart = 0x7U << 1; - uint32_t hsize = width + 16; - - stat |= ov7725_write_register(context, HSTART, hstart >> 2); - stat |= ov7725_write_register(context, HSIZE, hsize >> 2); - stat |= ov7725_write_register(context, VSTART, vstart >> 1); - stat |= ov7725_write_register(context, VSIZE, height >> 1); - - stat |= ov7725_write_register(context, HOUTSIZE, width >> 2); - stat |= ov7725_write_register(context, VOUTSIZE, height >> 1); - - stat |= ov7725_write_register(context, HREF, - ((vstart & 1) << 6) | ((hstart & 3) << 4) | ((height & 1) << 2) | ((hsize & 3) << 0)); - - stat = ov7725_write_register(context, EXHCH, ((height & 0x1) << 2) | (width & 0x3)); - if (stat != status_success) { - return stat; - } - return stat; -} - -hpm_stat_t ov7725_set_pixel_format(camera_context_t *context, display_pixel_format_t pixel_format) -{ - hpm_stat_t stat = status_success; - uint8_t val = 0; - - stat |= ov7725_read_register(context, COM7, &val); - val &= ~0x1F; - switch (pixel_format) { - case display_pixel_format_rgb565: - val |= COM7_FMT_RGB565; - break; - case display_pixel_format_rgb444: - val |= COM7_FMT_RGB444; - break; - case display_pixel_format_yuv422: - case display_pixel_format_y8: - val |= COM7_FMT_YUV; - break; - case display_pixel_format_raw8: - stat |= ov7725_write_register(context, DSP_CTRL4, DSP_CTRL4_RAW8); - val |= COM7_FMT_R_BAYER; - break; - default: - stat = status_invalid_argument; - break; - } - if (stat != status_success) { - return stat; - } - - stat |= ov7725_write_register(context, COM7, val); - if (stat != status_success) { - return stat; - } - return stat; -} - -hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config) -{ - hpm_stat_t stat = status_success; - - switch (ov_config->pixel_format) { - case display_pixel_format_yuv422: - case display_pixel_format_y8: - ov7725_load_settings(context, (uint8_t *) ov7725_default_yuv_regs, ARRAY_SIZE(ov7725_default_yuv_regs)); - break; - default: - ov7725_load_settings(context, (uint8_t *) ov7725_default_regs, ARRAY_SIZE(ov7725_default_regs)); - stat |= ov7725_write_register(context, COM7, COM7_RES_VGA | COM7_FMT_RGB565); - stat |= ov7725_write_register(context, COM10, 0); - stat |= ov7725_write_register(context, COM3, 0); - break; - } - - stat |= ov7725_write_register(context, CLKRC, 0x2); - stat |= ov7725_write_register(context, COM4, 0x41); - - stat |= ov7725_set_framesize(context, ov_config->width, ov_config->height); - stat |= ov7725_set_pixel_format(context, ov_config->pixel_format); - if (stat != status_success) { - return stat; - } - - return stat; -} - -void ov7725_power_up(camera_context_t *context) -{ - assert(context->delay_ms != NULL); - - if (context->write_rst) { - context->write_rst(OV7725_RST_ACTIVE); - } - if (context->write_pwdn) { - context->write_pwdn(OV7725_PWDN_ACTIVE); - } - context->delay_ms(5); - if (context->write_pwdn) { - context->write_pwdn(OV7725_PWDN_INACTIVE); - } - context->delay_ms(2); - if (context->write_rst) { - context->write_rst(OV7725_RST_INACTIVE); - } - context->delay_ms(20); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h b/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h deleted file mode 100644 index d3df505e88b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/camera/ov7725/hpm_ov7725.h +++ /dev/null @@ -1,426 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_OV7725_H -#define HPM_OV7725_H -#include "hpm_common.h" -#include "hpm_camera_config.h" - -/** - * @brief OV7725 sensor driver APIs - * @defgroup ov7725_interface sensor driver APIs - * @ingroup component_interfaces - * @{ - * - - */ -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ - -/** - * @brief OV7725 definition - */ -#define OV7725_ACTIVE_IMAGE_WIDTH (480U) -#define OV7725_ACTIVE_IMAGE_HEIGHT (480U) -#define OV7725_I2C_ADDR (0x21U) -#define OV7725_CHIP_ID_HIGH_BYTE_ADDR (0x0A) -#define OV7725_CHIP_ID_HIGH_BYTE_VALUE (0x77) -#define OV7725_CHIP_ID_LOW_BYTE_ADDR (0x0B) -#define OV7725_CHIP_ID_LOW_BYTE_VALUE (0x21) /* need to check */ - -#define OV7725_RST_ACTIVE 0 -#define OV7725_RST_INACTIVE 1 -#define OV7725_PWDN_ACTIVE 1 -#define OV7725_PWDN_INACTIVE 0 -/** - * @brief OV7725 registers - */ -#define GAIN (0x00U) /* AGC – Gain control gain setting */ -#define BLUE (0x01U) /* AWB – Blue channel gain setting */ -#define RED (0x02U) /* AWB – Red channel gain setting */ -#define GREEN (0x03U) /* AWB – Green channel gain setting */ - -#define BAVG (0x05U) /* U/B Average Level */ -#define GAVG (0x06U) /* Y/Gb Average Level */ -#define RAVG (0x07U) /* V/R Average Level */ -#define AECH (0x08U) /* Exposure Value – AEC MSBs */ - -#define COM2 (0x09U) /* Common Control 2 */ -#define COM2_SOFT_SLEEP (0x10U) /* Soft sleep mode */ -#define COM2_OUT_DRIVE_1x (0x00U) /* Output drive capability 1x */ -#define COM2_OUT_DRIVE_2x (0x01U) /* Output drive capability 2x */ -#define COM2_OUT_DRIVE_3x (0x02U) /* Output drive capability 3x */ -#define COM2_OUT_DRIVE_4x (0x03U) /* Output drive capability 4x */ - -#define PID (0x0AU) /* Product ID Number MSB */ -#define VER (0x0BU) /* Product ID Number LSB */ - -#define COM3 (0x0CU) /* Common Control 3 */ -#define COM3_VFLIP (0x80U) /* Vertical flip image ON/OFF selection */ -#define COM3_MIRROR (0x40U) /* Horizontal mirror image ON/OFF selection */ -#define COM3_SWAP_BR (0x20U) /* Swap B/R output sequence in RGB output mode */ -#define COM3_SWAP_YUV (0x10U) /* Swap Y/UV output sequence in YUV output mode */ -#define COM3_SWAP_MSB (0x08U) /* Swap output MSB/LSB */ -#define COM3_TRI_CLOCK (0x04U) /* Tri-state option for output clock at power-down period */ -#define COM3_TRI_DATA (0x02U) /* Tri-state option for output data at power-down period */ -#define COM3_COLOR_BAR (0x01U) /* Sensor color bar test pattern output enable */ - -#define COM4 (0x0DU) /* Common Control 4 */ -#define COM4_PLL_BYPASS (0x00U) /* Bypass PLL */ -#define COM4_PLL_4x (0x40U) /* PLL frequency 4x */ -#define COM4_PLL_6x (0x80U) /* PLL frequency 6x */ -#define COM4_PLL_8x (0xc0U) /* PLL frequency 8x */ -#define COM4_AEC_FULL (0x00U) /* AEC evaluate full window */ -#define COM4_AEC_1_2 (0x10U) /* AEC evaluate 1/2 window */ -#define COM4_AEC_1_4 (0x20U) /* AEC evaluate 1/4 window */ -#define COM4_AEC_2_3 (0x30U) /* AEC evaluate 2/3 window */ - -#define COM5 (0x0EU) /* Common Control 5 */ -#define COM5_AFR (0x80U) /* Auto frame rate control ON/OFF selection (night mode) */ -#define COM5_AFR_SPEED (0x40U) /* Auto frame rate control speed selection */ -#define COM5_AFR_0 (0x00U) /* No reduction of frame rate */ -#define COM5_AFR_1_2 (0x10U) /* Max reduction to 1/2 frame rate */ -#define COM5_AFR_1_4 (0x20U) /* Max reduction to 1/4 frame rate */ -#define COM5_AFR_1_8 (0x30U) /* Max reduction to 1/8 frame rate */ -#define COM5_AFR_4x (0x04U) /* Add frame when AGC reaches 4x gain */ -#define COM5_AFR_8x (0x08U) /* Add frame when AGC reaches 8x gain */ -#define COM5_AFR_16x (0x0cU) /* Add frame when AGC reaches 16x gain */ -#define COM5_AEC_NO_LIMIT (0x01U) /* No limit to AEC increase step */ - -#define COM6 (0x0FU) /* Common Control 6 */ -#define COM6_AUTO_WINDOW (0x01U) /* Auto window setting ON/OFF selection when format changes */ - -#define AEC (0x10U) /* AEC[7:0] (see register AECH for AEC[15:8]) */ -#define CLKRC (0x11U) /* Internal Clock */ - -#define COM7 (0x12U) /* Common Control 7 */ -#define COM7_RESET (0x80U) /* SCCB Register Reset */ -#define COM7_RES_VGA (0x00U) /* Resolution VGA */ -#define COM7_RES_QVGA (0x40U) /* Resolution QVGA */ -#define COM7_BT656 (0x20U) /* BT.656 protocol ON/OFF */ -#define COM7_SENSOR_RAW (0x10U) /* Sensor RAW */ -#define COM7_FMT_GBR422 (0x02U) /* RGB output format GBR422 */ -#define COM7_FMT_RGB565 (0x06U) /* RGB output format RGB565 */ -#define COM7_FMT_RGB555 (0x0AU) /* RGB output format RGB555 */ -#define COM7_FMT_RGB444 (0x0EU) /* RGB output format RGB444 */ -#define COM7_FMT_YUV (0x00U) /* Output format YUV */ -#define COM7_FMT_P_BAYER (0x01U) /* Output format Processed Bayer RAW */ -#define COM7_FMT_R_BAYER (0x03U) /* Output format Bayer RAW */ - -#define COM8 (0x13U) /* Common Control 8 */ -#define COM8_FAST_AUTO (0x80U) /* Enable fast AGC/AEC algorithm */ -#define COM8_STEP_VSYNC (0x00U) /* AEC - Step size limited to vertical blank */ -#define COM8_STEP_UNLIMIT (0x40U) /* AEC - Step size unlimited step size */ -#define COM8_BANDF_EN (0x20U) /* Banding filter ON/OFF */ -#define COM8_AEC_BANDF (0x10U) /* Enable AEC below banding value */ -#define COM8_AEC_FINE_EN (0x08U) /* Fine AEC ON/OFF control */ -#define COM8_AGC_EN (0x04U) /* AGC Enable */ -#define COM8_AWB_EN (0x02U) /* AWB Enable */ -#define COM8_AEC_EN (0x01U) /* AEC Enable */ - -#define COM9 (0x14U) /* Common Control 9 */ -#define COM9_HISTO_AVG (0x80U) /* Histogram or average based AEC/AGC selection */ -#define COM9_AGC_GAIN_2x (0x00U) /* Automatic Gain Ceiling 2x */ -#define COM9_AGC_GAIN_4x (0x10U) /* Automatic Gain Ceiling 4x */ -#define COM9_AGC_GAIN_8x (0x20U) /* Automatic Gain Ceiling 8x */ -#define COM9_AGC_GAIN_16x (0x30U) /* Automatic Gain Ceiling 16x */ -#define COM9_AGC_GAIN_32x (0x40U) /* Automatic Gain Ceiling 32x */ -#define COM9_DROP_VSYNC (0x04U) /* Drop VSYNC output of corrupt frame */ -#define COM9_DROP_HREF (0x02U) /* Drop HREF output of corrupt frame */ - -#define COM10 (0x15U) /* Common Control 10 */ -#define COM10_NEGATIVE (0x80U) /* Output negative data */ -#define COM10_HSYNC_EN (0x40U) /* HREF changes to HSYNC */ -#define COM10_PCLK_FREE (0x00U) /* PCLK output option: free running PCLK */ -#define COM10_PCLK_MASK (0x20U) /* PCLK output option: masked during horizontal blank */ -#define COM10_PCLK_REV (0x10U) /* PCLK reverse */ -#define COM10_HREF_REV (0x08U) /* HREF reverse */ -#define COM10_VSYNC_FALLING (0x00U) /* VSYNC changes on falling edge of PCLK */ -#define COM10_VSYNC_RISING (0x04U) /* VSYNC changes on rising edge of PCLK */ -#define COM10_VSYNC_NEG (0x02U) /* VSYNC negative */ -#define COM10_OUT_RANGE_8 (0x01U) /* Output data range: Full range */ -#define COM10_OUT_RANGE_10 (0x00U) /* Output data range: Data from [10] to [F0] (8 MSBs) */ - -#define REG16 (0x16U) /* Register 16 */ -#define REG16_BIT_SHIFT (0x80U) /* Bit shift test pattern options */ -#define HSTART (0x17U) /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */ -#define HSIZE (0x18U) /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */ -#define VSTART (0x19U) /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */ -#define VSIZE (0x1AU) /* Vertical Sensor Size (1 LSB is at HREF[2]) */ -#define PSHFT (0x1BU) /* Data Format - Pixel Delay Select */ -#define REG_MIDH (0x1CU) /* Manufacturer ID Byte – High */ -#define REG_MIDL (0x1DU) /* Manufacturer ID Byte – Low */ -#define LAEC (0x1FU) /* Fine AEC Value - defines exposure value less than one row period */ - -#define COM11 (0x20U) /* Common Control 11 */ -#define COM11_SNGL_FRAME_EN (0x02U) /* Single frame ON/OFF selection */ -#define COM11_SNGL_XFR_TRIG (0x01U) /* Single frame transfer trigger */ - -#define BDBASE (0x22U) /* Banding Filter Minimum AEC Value */ -#define DBSTEP (0x23U) /* Banding Filter Maximum Step */ -#define AEW (0x24U) /* AGC/AEC - Stable Operating Region (Upper Limit) */ -#define AEB (0x25U) /* AGC/AEC - Stable Operating Region (Lower Limit) */ -#define VPT (0x26U) /* AGC/AEC Fast Mode Operating Region */ -#define REG28 (0x28U) /* Selection on the number of dummy rows, N */ -#define HOUTSIZE (0x29U) /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */ -#define EXHCH (0x2AU) /* Dummy Pixel Insert MSB */ -#define EXHCL (0x2BU) /* Dummy Pixel Insert LSB */ -#define VOUTSIZE (0x2CU) /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */ -#define ADVFL (0x2DU) /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */ -#define ADVFH (0x2EU) /* MSB of Insert Dummy Rows in Vertical Sync */ -#define YAVE (0x2FU) /* Y/G Channel Average Value */ -#define LUMHTH (0x30U) /* Histogram AEC/AGC Luminance High Level Threshold */ -#define LUMLTH (0x31U) /* Histogram AEC/AGC Luminance Low Level Threshold */ -#define HREF (0x32U) /* Image Start and Size Control */ -#define DM_LNL (0x33U) /* Dummy Row Low 8 Bits */ -#define DM_LNH (0x34U) /* Dummy Row High 8 Bits */ -#define ADOFF_B (0x35U) /* AD Offset Compensation Value for B Channel */ -#define ADOFF_R (0x36U) /* AD Offset Compensation Value for R Channel */ -#define ADOFF_GB (0x37U) /* AD Offset Compensation Value for GB Channel */ -#define ADOFF_GR (0x38U) /* AD Offset Compensation Value for GR Channel */ -#define OFF_B (0x39U) /* AD Offset Compensation Value for B Channel */ -#define OFF_R (0x3AU) /* AD Offset Compensation Value for R Channel */ -#define OFF_GB (0x3BU) /* AD Offset Compensation Value for GB Channel */ -#define OFF_GR (0x3CU) /* AD Offset Compensation Value for GR Channel */ -#define COM12 (0x3DU) /* DC offset compensation for analog process */ - -#define COM13 (0x3EU) /* Common Control 13 */ -#define COM13_BLC_EN (0x80U) /* BLC enable */ -#define COM13_ADC_EN (0x40U) /* ADC channel BLC ON/OFF control */ -#define COM13_ANALOG_BLC (0x20U) /* Analog processing channel BLC ON/OFF control */ -#define COM13_ABLC_GAIN_EN (0x04U) /* ABLC gain trigger enable */ - -#define COM14 (0x3FU) /* Common Control 14 */ -#define COM15 (0x40U) /* Common Control 15 */ -#define COM16 (0x41U) /* Common Control 16 */ -#define TGT_B (0x42U) /* BLC Blue Channel Target Value */ -#define TGT_R (0x43U) /* BLC Red Channel Target Value */ -#define TGT_GB (0x44U) /* BLC Gb Channel Target Value */ -#define TGT_GR (0x45U) /* BLC Gr Channel Target Value */ - -#define LC_CTR (0x46U) /* Lens Correction Control */ -#define LC_CTR_RGB_COMP_1 (0x00U) /* R, G, and B channel compensation coefficient is set by LC_COEF ((0x49U)) */ -/* R, G, and B channel compensation coefficient is set by registers LC_COEFB ((0x4BU)), LC_COEF ((0x49U)), and LC_COEFR ((0x4CU)), respectively */ -#define LC_CTR_RGB_COMP_3 (0x04U) -#define LC_CTR_EN (0x01U) /* Lens correction enable */ -#define LC_XC (0x47U) /* X Coordinate of Lens Correction Center Relative to Array Center */ -#define LC_YC (0x48U) /* Y Coordinate of Lens Correction Center Relative to Array Center */ -#define LC_COEF (0x49U) /* Lens Correction Coefficient */ -#define LC_RADI (0x4AU) /* Lens Correction Radius */ -#define LC_COEFB (0x4BU) /* Lens Correction B Channel Compensation Coefficient */ -#define LC_COEFR (0x4CU) /* Lens Correction R Channel Compensation Coefficient */ - -#define FIXGAIN (0x4DU) /* Analog Fix Gain Amplifier */ -#define AREF0 (0x4EU) /* Sensor Reference Control */ -#define AREF1 (0x4FU) /* Sensor Reference Current Control */ -#define AREF2 (0x50U) /* Analog Reference Control */ -#define AREF3 (0x51U) /* ADC Reference Control */ -#define AREF4 (0x52U) /* ADC Reference Control */ -#define AREF5 (0x53U) /* ADC Reference Control */ -#define AREF6 (0x54U) /* Analog Reference Control */ -#define AREF7 (0x55U) /* Analog Reference Control */ -#define UFIX (0x60U) /* U Channel Fixed Value Output */ -#define VFIX (0x61U) /* V Channel Fixed Value Output */ -#define AWBB_BLK (0x62U) /* AWB Option for Advanced AWB */ - -#define AWB_CTRL0 (0x63U) /* AWB Control Byte 0 */ -#define AWB_CTRL0_GAIN_EN (0x80U) /* AWB gain enable */ -#define AWB_CTRL0_CALC_EN (0x40U) /* AWB calculate enable */ -#define AWB_CTRL0_WBC_MASK (0x0FU) /* WBC threshold 2 */ - -#define DSP_CTRL1 (0x64U) /* DSP Control Byte 1 */ -#define DSP_CTRL1_FIFO_EN (0x80U) /* FIFO enable/disable selection */ -#define DSP_CTRL1_UV_EN (0x40U) /* UV adjust function ON/OFF selection */ -#define DSP_CTRL1_SDE_EN (0x20U) /* SDE enable */ -#define DSP_CTRL1_MTRX_EN (0x10U) /* Color matrix ON/OFF selection */ -#define DSP_CTRL1_INTRP_EN (0x08U) /* Interpolation ON/OFF selection */ -#define DSP_CTRL1_GAMMA_EN (0x04U) /* Gamma function ON/OFF selection */ -#define DSP_CTRL1_BLACK_EN (0x02U) /* Black defect auto correction ON/OFF */ -#define DSP_CTRL1_WHITE_EN (0x01U) /* White defect auto correction ON/OFF */ - -#define DSP_CTRL2 (0x65U) /* DSP Control Byte 2 */ -#define DSP_CTRL2_VDCW_EN (0x08U) /* Vertical DCW enable */ -#define DSP_CTRL2_HDCW_EN (0x04U) /* Horizontal DCW enable */ -#define DSP_CTRL2_VZOOM_EN (0x02U) /* Vertical zoom out enable */ -#define DSP_CTRL2_HZOOM_EN (0x01U) /* Horizontal zoom out enable */ - -#define DSP_CTRL3 (0x66U) /* DSP Control Byte 3 */ -#define DSP_CTRL3_UV_EN (0x80U) /* UV output sequence option */ -#define DSP_CTRL3_CBAR_EN (0x20U) /* DSP color bar ON/OFF selection */ -#define DSP_CTRL3_FIFO_EN (0x08U) /* FIFO power down ON/OFF selection */ -#define DSP_CTRL3_SCAL1_PWDN (0x04U) /* Scaling module power down control 1 */ -#define DSP_CTRL3_SCAL2_PWDN (0x02U) /* Scaling module power down control 2 */ -#define DSP_CTRL3_INTRP_PWDN (0x01U) /* Interpolation module power down control */ - -#define DSP_CTRL4 (0x67U) /* DSP Control Byte 4 */ -#define DSP_CTRL4_YUV_RGB (0x00U) /* Output selection YUV or RGB */ -#define DSP_CTRL4_RAW8 (0x02U) /* Output selection RAW8 */ -#define DSP_CTRL4_RAW10 (0x03U) /* Output selection RAW10 */ - -#define AWB_BIAS (0x68U) /* AWB BLC Level Clip */ -#define AWB_CTRL1 (0x69U) /* AWB Control 1 */ -#define AWB_CTRL2 (0x6AU) /* AWB Control 2 */ - -#define AWB_CTRL3 (0x6BU) /* AWB Control 3 */ -#define AWB_CTRL3_ADVANCED (0x80U) /* AWB mode select - Advanced AWB */ -#define AWB_CTRL3_SIMPLE (0x00U) /* AWB mode select - Simple AWB */ - -#define AWB_CTRL4 (0x6CU) /* AWB Control 4 */ -#define AWB_CTRL5 (0x6DU) /* AWB Control 5 */ -#define AWB_CTRL6 (0x6EU) /* AWB Control 6 */ -#define AWB_CTRL7 (0x6FU) /* AWB Control 7 */ -#define AWB_CTRL8 (0x70U) /* AWB Control 8 */ -#define AWB_CTRL9 (0x71U) /* AWB Control 9 */ -#define AWB_CTRL10 (0x72U) /* AWB Control 10 */ -#define AWB_CTRL11 (0x73U) /* AWB Control 11 */ -#define AWB_CTRL12 (0x74U) /* AWB Control 12 */ -#define AWB_CTRL13 (0x75U) /* AWB Control 13 */ -#define AWB_CTRL14 (0x76U) /* AWB Control 14 */ -#define AWB_CTRL15 (0x77U) /* AWB Control 15 */ -#define AWB_CTRL16 (0x78U) /* AWB Control 16 */ -#define AWB_CTRL17 (0x79U) /* AWB Control 17 */ -#define AWB_CTRL18 (0x7AU) /* AWB Control 18 */ -#define AWB_CTRL19 (0x7BU) /* AWB Control 19 */ -#define AWB_CTRL20 (0x7CU) /* AWB Control 20 */ -#define AWB_CTRL21 (0x7DU) /* AWB Control 21 */ -#define GAM1 (0x7EU) /* Gamma Curve 1st Segment Input End Point (0x04U) Output Value */ -#define GAM2 (0x7FU) /* Gamma Curve 2nd Segment Input End Point (0x08U) Output Value */ -#define GAM3 (0x80U) /* Gamma Curve 3rd Segment Input End Point (0x10U) Output Value */ -#define GAM4 (0x81U) /* Gamma Curve 4th Segment Input End Point (0x20U) Output Value */ -#define GAM5 (0x82U) /* Gamma Curve 5th Segment Input End Point (0x28U) Output Value */ -#define GAM6 (0x83U) /* Gamma Curve 6th Segment Input End Point (0x30U) Output Value */ -#define GAM7 (0x84U) /* Gamma Curve 7th Segment Input End Point (0x38U) Output Value */ -#define GAM8 (0x85U) /* Gamma Curve 8th Segment Input End Point (0x40U) Output Value */ -#define GAM9 (0x86U) /* Gamma Curve 9th Segment Input End Point (0x48U) Output Value */ -#define GAM10 (0x87U) /* Gamma Curve 10th Segment Input End Point (0x50U) Output Value */ -#define GAM11 (0x88U) /* Gamma Curve 11th Segment Input End Point (0x60U) Output Value */ -#define GAM12 (0x89U) /* Gamma Curve 12th Segment Input End Point (0x70U) Output Value */ -#define GAM13 (0x8AU) /* Gamma Curve 13th Segment Input End Point (0x90U) Output Value */ -#define GAM14 (0x8BU) /* Gamma Curve 14th Segment Input End Point (0xB0U) Output Value */ -#define GAM15 (0x8CU) /* Gamma Curve 15th Segment Input End Point (0xD0U) Output Value */ -#define SLOP (0x8DU) /* Gamma Curve Highest Segment Slope */ -#define DNSTH (0x8EU) /* De-noise Threshold */ -#define EDGE0 (0x8FU) /* Edge Enhancement Strength Control */ -#define EDGE1 (0x90U) /* Edge Enhancement Threshold Control */ -#define DNSOFF (0x91U) /* Auto De-noise Threshold Control */ -#define EDGE2 (0x92U) /* Edge Enhancement Strength Upper Limit */ -#define EDGE3 (0x93U) /* Edge Enhancement Strength Upper Limit */ -#define MTX1 (0x94U) /* Matrix Coefficient 1 */ -#define MTX2 (0x95U) /* Matrix Coefficient 2 */ -#define MTX3 (0x96U) /* Matrix Coefficient 3 */ -#define MTX4 (0x97U) /* Matrix Coefficient 4 */ -#define MTX5 (0x98U) /* Matrix Coefficient 5 */ -#define MTX6 (0x99U) /* Matrix Coefficient 6 */ - -#define MTX_CTRL (0x9AU) /* Matrix Control */ -#define MTX_CTRL_DBL_EN (0x80U) /* Matrix double ON/OFF selection */ - -#define BRIGHTNESS (0x9BU) /* Brightness Control */ -#define CONTRAST (0x9CU) /* Contrast Gain */ -#define UVADJ0 (0x9EU) /* Auto UV Adjust Control 0 */ -#define UVADJ1 (0x9FU) /* Auto UV Adjust Control 1 */ -#define SCAL0 (0xA0U) /* DCW Ratio Control */ -#define SCAL1 (0xA1U) /* Horizontal Zoom Out Control */ -#define SCAL2 (0xA2U) /* Vertical Zoom Out Control */ -#define FIFODLYM (0xA3U) /* FIFO Manual Mode Delay Control */ -#define FIFODLYA (0xA4U) /* FIFO Auto Mode Delay Control */ - -#define SDE (0xA6U) /* Special Digital Effect Control */ -#define SDE_NEGATIVE_EN (0x40U) /* Negative image enable */ -#define SDE_GRAYSCALE_EN (0x20U) /* Gray scale image enable */ -#define SDE_V_FIXED_EN (0x10U) /* V fixed value enable */ -#define SDE_U_FIXED_EN (0x08U) /* U fixed value enable */ -#define SDE_CONT_BRIGHT_EN (0x04U) /* Contrast/Brightness enable */ -#define SDE_SATURATION_EN (0x02U) /* Saturation enable */ -#define SDE_HUE_EN (0x01U) /* Hue enable */ - -#define USAT (0xA7U) /* U Component Saturation Gain */ -#define VSAT (0xA8U) /* V Component Saturation Gain */ -#define HUECOS (0xA9U) /* Cosine value × (0x80U) */ -#define HUESIN (0xAAU) /* Sine value × (0x80U) */ -#define SIGN_BIT (0xABU) /* Sign Bit for Hue and Brightness */ - -#define DSPAUTO (0xACU) /* DSP Auto Function ON/OFF Control */ -#define DSPAUTO_AWB_EN (0x80U) /* AWB auto threshold control */ -#define DSPAUTO_DENOISE_EN (0x40U) /* De-noise auto threshold control */ -#define DSPAUTO_EDGE_EN (0x20U) /* Sharpness (edge enhancement) auto strength control */ -#define DSPAUTO_UV_EN (0x10U) /* UV adjust auto slope control */ -#define DSPAUTO_SCAL0_EN (0x08U) /* Auto scaling factor control (register SCAL0 ((0xA0U))) */ -#define DSPAUTO_SCAL1_EN (0x04U) /* Auto scaling factor control (registers SCAL1 ((0xA1U) and SCAL2 ((0xA2U)))*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief ov7725 initialization routine - * @param [in] context camera_context_t - * @param [in] ov_config camera config structure - */ -hpm_stat_t ov7725_init(camera_context_t *context, camera_config_t *ov_config); - -/** - * @brief ov7725 read register - * @param [in] context camera_context_t - * @param [in] reg register address - * @param [in] buf buffer to store read data - * @retval status_success if everything is okay - */ -hpm_stat_t ov7725_read_register(camera_context_t *context, uint8_t reg, uint8_t *buf); - -/** - * @brief ov7725 write register - * @param [in] context camera_context_t - * @param [in] reg register address - * @param [in] val value to be written - * @retval status_success if everything is okay - */ -hpm_stat_t ov7725_write_register(camera_context_t *context, uint8_t reg, uint8_t val); - -/** - * @brief ov7725 reset - * @param [in] context camera_context_t - */ -hpm_stat_t ov7725_software_reset(camera_context_t *context); - -/** - * @brief ov7725 check chip id - * @param [in] context camera_context_t - */ -hpm_stat_t ov7725_check_chip_id(camera_context_t *context); - - -/** - * @brief ov7725 load set of register-value pairs - * - * @param [in] context camera_context_t - * @param [in] reg_values register-value pair in 2-d array form, ex. reg_values[][2] = {{COM3, 0x1}}; - * @parma [in] count register-value pair count in 2-d array - * @retval status_success if everything is okay - */ -hpm_stat_t ov7725_load_settings(camera_context_t *context, uint8_t *reg_values, uint32_t count); - -/** - * @brief ov7725 power up - * - * @param [in] context camera_context_t - */ -void ov7725_power_up(camera_context_t *context); - -#ifdef __cplusplus -} -#endif - -/** - * @} - * - */ - -#endif /* HPM_OV7725_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c deleted file mode 100644 index 64dcd75d880..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.c +++ /dev/null @@ -1,648 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sgtl5000.h" - -#ifndef HPM_SGTL5000_MCLK_TOLERANCE -#define HPM_SGTL5000_MCLK_TOLERANCE (4U) -#endif - -hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config) -{ - assert(context != NULL); - assert(config != NULL); - - if (sgtl_write_reg(context, CHIP_ANA_POWER, 0x6AFF) != status_success) { - return status_fail; - } - - /* Set the data route */ - if (sgtl_set_data_route(context, config->route) != status_success) { - return status_fail; - } - - /* Set sgtl5000 to master or slave */ - sgtl_set_master_mode(context, config->master); - - /* - * Input Volume Control - * Configure ADC left and right analog volume to desired default. - * Example shows volume of 0dB. - */ - if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0000U) != status_success) { - return status_fail; - } - - /* - * Volume and Mute Control - * Configure HP_OUT left and right volume to minimum, unmute. - * HP_OUT and ramp the volume up to desired volume. - */ - if (sgtl_write_reg(context, CHIP_ANA_HP_CTRL, 0x1818U) != status_success) { - return status_fail; - } - - if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFEFU, 0x0000U) != status_success) { - return status_fail; - } - - /* LINEOUT and DAC volume control */ - if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFEFFU, 0x0000U) != status_success) { - return status_fail; - } - - /* Configure DAC left and right digital volume */ - if (sgtl_write_reg(context, CHIP_DAC_VOL, 0x5C5CU) != status_success) { - return status_fail; - } - - /* Configure ADC volume, reduce 6db. */ - if (sgtl_write_reg(context, CHIP_ANA_ADC_CTRL, 0x0100U) != status_success) { - return status_fail; - } - - /* Unmute DAC */ - if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFFBU, 0x0000U) != status_success) { - return status_fail; - } - - if (sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, 0xFFF7U, 0x0000U) != status_success) { - return status_fail; - } - - /* Unmute ADC */ - if (sgtl_modify_reg(context, CHIP_ANA_CTRL, 0xFFFEU, 0x0000U) != status_success) { - return status_fail; - } - - /* Set the audio format */ - if (sgtl_set_protocol(context, config->bus) != status_success) { - return status_fail; - } - - if (sgtl_config_data_format(context, config->format.mclk_hz, config->format.sample_rate, config->format.bit_width) != - status_success) { - return status_fail; - } - - /* sclk valid edge */ - if (config->format.sclk_edge == sgtl_sclk_valid_edge_rising) { - if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE) != - status_success) { - return status_fail; - } - } else { - if (sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE) != - status_success) { - return status_fail; - } - } - - return status_success; -} - -hpm_stat_t sgtl_deinit(sgtl_context_t *context) -{ - hpm_stat_t stat = status_success; - - HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_dap)); - HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_disable_module(context, sgtl_module_lineout)); - - return stat; -} - -void sgtl_set_master_mode(sgtl_context_t *context, bool master) -{ - if (master == true) { - (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_MASTER); - } else { - (void)sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MS_CLR_MASK, SGTL5000_I2S_SLAVE); - } -} - -hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module) -{ - hpm_stat_t stat = status_success; - switch (module) { - case sgtl_module_adc: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_ADC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_ADC_POWERUP_SHIFT))); - break; - case sgtl_module_dac: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAC_POWERUP_SHIFT))); - break; - case sgtl_module_dap: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAP_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, - ((uint16_t)1U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); - break; - case sgtl_module_i2sin: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_I2S_IN_ENABLE_SHIFT))); - break; - case sgtl_module_i2sout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, - ((uint16_t)1U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); - break; - case sgtl_module_hp: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); - break; - case sgtl_module_lineout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, - ((uint16_t)1U << SGTL5000_LINEOUT_POWERUP_SHIFT))); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module) -{ - hpm_stat_t stat = status_success; - switch (module) { - case sgtl_module_adc: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_ADC_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_ADC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_ADC_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_ADC_POWERUP_SHIFT))); - break; - case sgtl_module_dac: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAC_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAC_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_DAC_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAC_POWERUP_SHIFT))); - break; - case sgtl_module_dap: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_DAP_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAP_ENABLE_SHIFT))); - HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, - ((uint16_t)0U << SGTL5000_DAP_CONTROL_DAP_EN_SHIFT))); - break; - case sgtl_module_i2sin: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_IN_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_I2S_IN_ENABLE_SHIFT))); - break; - case sgtl_module_i2sout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_DIG_POWER, SGTL5000_I2S_OUT_ENABLE_CLR_MASK, - ((uint16_t)0U << SGTL5000_I2S_OUT_ENABLE_SHIFT))); - break; - case sgtl_module_hp: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_HEADPHONE_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_HEADPHONE_POWERUP_SHIFT))); - break; - case sgtl_module_lineout: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_POWER, SGTL5000_LINEOUT_POWERUP_CLR_MASK, - ((uint16_t)0U << SGTL5000_LINEOUT_POWERUP_SHIFT))); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route) -{ - hpm_stat_t stat = status_success; - switch (route) { - case sgtl_route_bypass: - /* Bypass means from line-in to HP*/ - HPM_CHECK_RET(sgtl_write_reg(context, CHIP_DIG_POWER, 0x0000)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_LINEIN)); - break; - case sgtl_route_playback: - /* Data route I2S_IN-> DAC-> HP */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - break; - case sgtl_route_playback_record: - /* I2S IN->DAC->HP LINE_IN->ADC->I2S_OUT */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); - break; - case sgtl_route_playback_with_dap: - /* I2S_IN->DAP->DAC->HP */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - break; - case sgtl_route_playback_with_dap_record: - /* I2S_IN->DAP->DAC->HP, LINE_IN->ADC->I2S_OUT */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_hp)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dac)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sin)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_dap)); - HPM_CHECK_RET(sgtl_modify_reg(context, SGTL5000_DAP_CONTROL, SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK, 0x0001)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAP_SEL_CLR_MASK, SGTL5000_DAP_SEL_I2S_IN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_DAC_SEL_CLR_MASK, SGTL5000_DAC_SEL_DAP)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_HP_CLR_MASK, SGTL5000_SEL_HP_DAC)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); - break; - case sgtl_route_record: - /* LINE_IN->ADC->I2S_OUT */ - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_i2sout)); - HPM_CHECK_RET(sgtl_enable_module(context, sgtl_module_adc)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_SEL_ADC_CLR_MASK, SGTL5000_SEL_ADC_LINEIN)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_SSS_CTRL, SGTL5000_I2S_OUT_SEL_CLR_MASK, SGTL5000_I2S_OUT_SEL_ADC)); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol) -{ - hpm_stat_t stat = status_success; - switch (protocol) { - case sgtl_bus_i2s: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); - break; - case sgtl_bus_left_justified: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_I2S_LJ)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); - break; - case sgtl_bus_right_justified: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_RJ)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_RISING_EDGE)); - break; - case sgtl_bus_pcma: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_ONE_BIT_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); - break; - case sgtl_bus_pcmb: - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_MODE_CLR_MASK, SGTL5000_I2S_MODE_PCM)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_LRALIGN_CLR_MASK, SGTL5000_I2S_NO_DELAY)); - HPM_CHECK_RET(sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_SCLK_INV_CLR_MASK, SGTL5000_I2S_VAILD_FALLING_EDGE)); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume) -{ - uint16_t vol = 0; - hpm_stat_t stat = status_success; - switch (module) { - case sgtl_module_adc: - if (volume > SGTL5000_ADC_MAX_VOLUME_VALUE) { - return status_invalid_argument; - } - - vol = (uint16_t)(volume | (volume << 4U)); - stat = sgtl_modify_reg(context, CHIP_ANA_ADC_CTRL, - SGTL5000_ADC_VOL_LEFT_CLR_MASK & SGTL5000_ADC_VOL_RIGHT_CLR_MASK, vol); - break; - case sgtl_module_dac: - if ((volume > SGTL5000_DAC_MAX_VOLUME_VALUE) || (volume < SGTL5000_DAC_MIN_VOLUME_VALUE)) { - return status_invalid_argument; - } - vol = (uint16_t)(volume | (volume << 8U)); - stat = sgtl_write_reg(context, CHIP_DAC_VOL, vol); - break; - case sgtl_module_hp: - if (volume > SGTL5000_HEADPHONE_MAX_VOLUME_VALUE) { - return status_invalid_argument; - } - vol = (uint16_t)(volume | (volume << 8U)); - stat = sgtl_write_reg(context, CHIP_ANA_HP_CTRL, vol); - break; - case sgtl_module_lineout: - if (volume > SGTL5000_LINE_OUT_MAX_VOLUME_VALUE) { - return status_invalid_argument; - } - vol = (uint16_t)(volume | (volume << 8U)); - stat = sgtl_write_reg(context, CHIP_LINE_OUT_VOL, vol); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module) -{ - uint16_t vol = 0; - hpm_stat_t stat = status_success; - - switch (module) { - case sgtl_module_adc: - stat = sgtl_read_reg(context, CHIP_ANA_ADC_CTRL, &vol); - vol = (vol & (uint16_t)SGTL5000_ADC_VOL_LEFT_GET_MASK) >> SGTL5000_ADC_VOL_LEFT_SHIFT; - break; - case sgtl_module_dac: - stat = sgtl_read_reg(context, CHIP_DAC_VOL, &vol); - vol = (vol & (uint16_t)SGTL5000_DAC_VOL_LEFT_GET_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT; - break; - case sgtl_module_hp: - stat = sgtl_read_reg(context, CHIP_ANA_HP_CTRL, &vol); - vol = (vol & (uint16_t)SGTL5000_HP_VOL_LEFT_GET_MASK) >> SGTL5000_HP_VOL_LEFT_SHIFT; - break; - case sgtl_module_lineout: - stat = sgtl_read_reg(context, CHIP_LINE_OUT_VOL, &vol); - vol = (vol & (uint16_t)SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK) >> SGTL5000_LINE_OUT_VOL_LEFT_SHIFT; - break; - default: - vol = 0; - break; - } - return stat == status_success ? vol : 0U; -} - -hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute) -{ - hpm_stat_t stat = status_success; - switch (module) { - case sgtl_module_adc: - stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_ADC_CLR_MASK, mute ? 1U : 0U); - break; - case sgtl_module_dac: - if (mute) { - stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, - SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x000C); - } else { - stat = sgtl_modify_reg(context, CHIP_ADCDAC_CTRL, - SGTL5000_DAC_MUTE_LEFT_CLR_MASK & SGTL5000_DAC_MUTE_RIGHT_CLR_MASK, 0x0000); - } - break; - case sgtl_module_hp: - stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_HP_CLR_MASK, - ((uint16_t)mute << SGTL5000_MUTE_HP_SHIFT)); - break; - case sgtl_module_lineout: - stat = sgtl_modify_reg(context, CHIP_ANA_CTRL, SGTL5000_MUTE_LO_CLR_MASK, - ((uint16_t)mute << SGTL5000_MUTE_LO_SHIFT)); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -static bool sgtl_check_clock_tolerance(uint32_t source, uint32_t target) -{ - uint32_t delta = (source >= target) ? (source - target) : (target - source); - if (delta * 100 <= HPM_SGTL5000_MCLK_TOLERANCE * target) { - return true; - } - return false; -} - -hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits) -{ - uint16_t val = 0; - uint16_t regVal = 0; - uint32_t mul_div = 0U; - uint32_t sysFs = 0U; - hpm_stat_t stat = status_success; - - /* Over sample rate can only up to 512, the least to 8k */ - if ((mclk / (MIN(sample_rate * 6U, 96000U)) > 512U) || (mclk / sample_rate < 256U)) { - return status_invalid_argument; - } - - /* Configure the sample rate */ - switch (sample_rate) { - case 8000: - if (mclk > 32000U * 512U) { - val = 0x0038; - sysFs = 48000; - } else { - val = 0x0020; - sysFs = 32000; - } - break; - case 11025: - val = 0x0024; - sysFs = 44100; - break; - case 12000: - val = 0x0028; - sysFs = 48000; - break; - case 16000: - if (mclk > 32000U * 512U) { - val = 0x003C; - sysFs = 96000; - } else { - val = 0x0010; - sysFs = 32000; - } - break; - case 22050: - val = 0x0014; - sysFs = 44100; - break; - case 24000: - if (mclk > 48000U * 512U) { - val = 0x002C; - sysFs = 96000; - } else { - val = 0x0018; - sysFs = 48000; - } - break; - case 32000: - val = 0x0000; - sysFs = 32000; - break; - case 44100: - val = 0x0004; - sysFs = 44100; - break; - case 48000: - if (mclk > 48000U * 512U) { - val = 0x001C; - sysFs = 96000; - } else { - val = 0x0008; - sysFs = 48000; - } - break; - case 96000: - val = 0x000C; - sysFs = 96000; - break; - default: - stat = status_invalid_argument; - break; - } - - if (stat != status_success) { - return stat; - } - - if (sgtl_read_reg(context, CHIP_I2S_CTRL, ®Val) != status_success) { - return status_fail; - } - - mul_div = mclk / sysFs; - - if (sgtl_check_clock_tolerance(mul_div, 256)) { - mul_div = 256; - } else if (sgtl_check_clock_tolerance(mul_div, 384)) { - mul_div = 384; - } else if (sgtl_check_clock_tolerance(mul_div, 512)) { - mul_div = 512; - } else { - return status_invalid_argument; - } - val |= (mul_div / 128U - 2U); - - if (sgtl_write_reg(context, CHIP_CLK_CTRL, val) != status_success) { - return status_fail; - } - - /* Data bits configure,sgtl supports 16bit, 20bit 24bit, 32bit */ - if (sgtl_modify_reg(context, CHIP_I2S_CTRL, 0xFEFF, SGTL5000_I2S_SCLKFREQ_64FS) != status_success) { - return status_fail; - } - - switch (bits) { - case 16: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_16); - break; - case 20: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_20); - break; - case 24: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_24); - break; - case 32: - stat = sgtl_modify_reg(context, CHIP_I2S_CTRL, SGTL5000_I2S_DLEN_CLR_MASK, SGTL5000_I2S_DLEN_32); - break; - default: - stat = status_invalid_argument; - break; - } - - return stat; -} - -hpm_stat_t sgtl_set_pay(sgtl_context_t *context, uint32_t playSource) -{ - uint16_t regValue = 0U, regBitMask = 0x40U; - - /* headphone source form PGA */ - if (playSource == (uint32_t)sgtl_play_source_linein) { - regValue = 0x40U; - } else { - /* headphone source from DAC */ - regValue = 0U; - } - - return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); -} - -hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource) -{ - uint16_t regValue = 0U, regBitMask = 0x4U; - - /* ADC source form LINEIN */ - if (recordSource == (uint32_t)sgtl_record_source_linein) { - regValue = 0x4U; - } else { - /* ADC source from MIC */ - regValue = 0U; - } - - return sgtl_modify_reg(context, CHIP_ANA_CTRL, regBitMask, regValue); -} - -hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val) -{ - uint8_t r[2]; - uint8_t d[2]; - r[0] = reg >> 8; - r[1] = reg & 0xFF; - d[0] = (uint8_t) (val>>8); - d[1] = (uint8_t) (val & 0xFF); - - return i2c_master_address_write(context->ptr, context->slave_address, r, 2U, d, 2U); -} - -hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val) -{ - hpm_stat_t stat = status_success; - uint8_t r[2]; - uint8_t d[2]; - r[0] = reg >> 8; - r[1] = reg & 0xFF; - - stat = i2c_master_address_read(context->ptr, context->slave_address, r, 2U, d, 2U); - - *val = (uint16_t)((d[0] << 8) | d[1]); - - return stat; -} - -hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val) -{ - hpm_stat_t retval = 0; - uint16_t reg_val; - - /* Read the register value out */ - retval = sgtl_read_reg(context, reg, ®_val); - if (retval != status_success) { - return status_fail; - } - - /* Modify the value */ - reg_val &= clr_mask; - reg_val |= val; - - /* Write the data to register */ - retval = sgtl_write_reg(context, reg, reg_val); - if (retval != status_success) { - return status_fail; - } - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h deleted file mode 100644 index dbf146933ed..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/sgtl5000/hpm_sgtl5000.h +++ /dev/null @@ -1,1022 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_SGTL5000_H_ -#define _HPM_SGTL5000_H_ - -#include "hpm_i2c_drv.h" - -/*! - * @addtogroup sgtl5000 - * @ingroup codec - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief Define the register address of sgtl5000. */ -#define CHIP_ID 0x0000U -#define CHIP_DIG_POWER 0x0002U -#define CHIP_CLK_CTRL 0x0004U -#define CHIP_I2S_CTRL 0x0006U -#define CHIP_SSS_CTRL 0x000AU -#define CHIP_ADCDAC_CTRL 0x000EU -#define CHIP_DAC_VOL 0x0010U -#define CHIP_PAD_STRENGTH 0x0014U -#define CHIP_ANA_ADC_CTRL 0x0020U -#define CHIP_ANA_HP_CTRL 0x0022U -#define CHIP_ANA_CTRL 0x0024U -#define CHIP_LINREG_CTRL 0x0026U -#define CHIP_REF_CTRL 0x0028U -#define CHIP_MIC_CTRL 0x002AU -#define CHIP_LINE_OUT_CTRL 0x002CU -#define CHIP_LINE_OUT_VOL 0x002EU -#define CHIP_ANA_POWER 0x0030U -#define CHIP_PLL_CTRL 0x0032U -#define CHIP_CLK_TOP_CTRL 0x0034U -#define CHIP_ANA_STATUS 0x0036U -#define CHIP_ANA_TEST2 0x003AU -#define CHIP_SHORT_CTRL 0x003CU -#define SGTL5000_DAP_CONTROL 0x0100U -#define SGTL5000_DAP_PEQ 0x0102U -#define SGTL5000_DAP_BASS_ENHANCE 0x0104U -#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106U -#define SGTL5000_DAP_AUDIO_EQ 0x0108U -#define SGTL5000_DAP_SGTL_SURROUND 0x010AU -#define SGTL5000_DAP_FILTER_COEF_ACCESS 0x010CU -#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010EU -#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110U -#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0 0x0116U -#define SGTL5000_DAP_AUDIO_EQ_BAND1 0x0118U -#define SGTL5000_DAP_AUDIO_EQ_BAND2 0x011AU -#define SGTL5000_DAP_AUDIO_EQ_BAND3 0x011CU -#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011EU -#define SGTL5000_DAP_MAIN_CHAN 0x0120U -#define SGTL5000_DAP_MIX_CHAN 0x0122U -#define SGTL5000_DAP_AVC_CTRL 0x0124U -#define SGTL5000_DAP_AVC_THRESHOLD 0x0126U -#define SGTL5000_DAP_AVC_ATTACK 0x0128U -#define SGTL5000_DAP_AVC_DECAY 0x012AU -#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012CU -#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012EU -#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130U -#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132U -#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134U -#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136U -#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138U -#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013AU - -/* - * Field Definitions. - */ - -/* - * SGTL5000_CHIP_DIG_POWER - */ -#define SGTL5000_ADC_ENABLE_CLR_MASK 0xFFBFU -#define SGTL5000_ADC_ENABLE_GET_MASK 0x0040U -#define SGTL5000_ADC_ENABLE_SHIFT 0x6U -#define SGTL5000_DAC_ENABLE_CLR_MASK 0xFFDFU -#define SGTL5000_DAC_ENABLE_GET_MASK 0x0020U -#define SGTL5000_DAC_ENABLE_SHIFT 0x5U -#define SGTL5000_DAP_ENABLE_CLR_MASK 0xFFEFU -#define SGTL5000_DAP_ENABLE_GET_MASK 0x0010U -#define SGTL5000_DAP_ENABLE_SHIFT 0x4U -#define SGTL5000_I2S_OUT_ENABLE_CLR_MASK 0xFFFDU -#define SGTL5000_I2S_OUT_ENABLE_GET_MASK 0x0002U -#define SGTL5000_I2S_OUT_ENABLE_SHIFT 0x1U -#define SGTL5000_I2S_IN_ENABLE_CLR_MASK 0xFFFEU -#define SGTL5000_I2S_IN_ENABLE_GET_MASK 0x0001U -#define SGTL5000_I2S_IN_ENABLE_SHIFT 0x0U - -/* - * SGTL5000_CHIP_CLK_CTRL - */ -#define SGTL5000_RATE_MODE_CLR_MASK 0xFFCFU -#define SGTL5000_RATE_MODE_GET_MASK 0x0030U -#define SGTL5000_RATE_MODE_SHIFT 0x4U -#define SGTL5000_RATE_MODE_DIV_1 0x0000U -#define SGTL5000_RATE_MODE_DIV_2 0x0010U -#define SGTL5000_RATE_MODE_DIV_4 0x0020U -#define SGTL5000_RATE_MODE_DIV_6 0x0030U -#define SGTL5000_SYS_FS_CLR_MASK 0xFFF3U -#define SGTL5000_SYS_FS_GET_MASK 0x000CU -#define SGTL5000_SYS_FS_SHIFT 0x2U -#define SGTL5000_SYS_FS_32k 0x0000U -#define SGTL5000_SYS_FS_44_1k 0x0004U -#define SGTL5000_SYS_FS_48k 0x0008U -#define SGTL5000_SYS_FS_96k 0x000CU -#define SGTL5000_MCLK_FREQ_CLR_MASK 0xFFFCU -#define SGTL5000_MCLK_FREQ_GET_MASK 0x0003U -#define SGTL5000_MCLK_FREQ_SHIFT 0x0U -#define SGTL5000_MCLK_FREQ_256FS 0x0000U -#define SGTL5000_MCLK_FREQ_384FS 0x0001U -#define SGTL5000_MCLK_FREQ_512FS 0x0002U -#define SGTL5000_MCLK_FREQ_PLL 0x0003U - -/* - * SGTL5000_CHIP_I2S_CTRL - */ -#define SGTL5000_I2S_SLCKFREQ_CLR_MASK 0xFEFFU -#define SGTL5000_I2S_SCLKFREQ_GET_MASK 0x0100U -#define SGTL5000_I2S_SCLKFREQ_SHIFT 0x8U -#define SGTL5000_I2S_SCLKFREQ_64FS 0x0000U -#define SGTL5000_I2S_SCLKFREQ_32FS 0x0100U /* Not for RJ mode */ -#define SGTL5000_I2S_MS_CLR_MASK 0xFF7FU -#define SGTL5000_I2S_MS_GET_MASK 0x0080U -#define SGTL5000_I2S_MS_SHIFT 0x7U -#define SGTL5000_I2S_MASTER 0x0080U -#define SGTL5000_I2S_SLAVE 0x0000U -#define SGTL5000_I2S_SCLK_INV_CLR_MASK 0xFFBFU -#define SGTL5000_I2S_SCLK_INV_GET_MASK 0x0040U -#define SGTL5000_I2S_SCLK_INV_SHIFT 0x6U -#define SGTL5000_I2S_VAILD_FALLING_EDGE 0x0040U -#define SGTL5000_I2S_VAILD_RISING_EDGE 0x0000U -#define SGTL5000_I2S_DLEN_CLR_MASK 0xFFCFU -#define SGTL5000_I2S_DLEN_GET_MASK 0x0030U -#define SGTL5000_I2S_DLEN_SHIFT 0x4U -#define SGTL5000_I2S_DLEN_32 0x0000U -#define SGTL5000_I2S_DLEN_24 0x0010U -#define SGTL5000_I2S_DLEN_20 0x0020U -#define SGTL5000_I2S_DLEN_16 0x0030U -#define SGTL5000_I2S_MODE_CLR_MASK 0xFFF3U -#define SGTL5000_I2S_MODE_GET_MASK 0x000CU -#define SGTL5000_I2S_MODE_SHIFT 0x2U -#define SGTL5000_I2S_MODE_I2S_LJ 0x0000U -#define SGTL5000_I2S_MODE_RJ 0x0004U -#define SGTL5000_I2S_MODE_PCM 0x0008U -#define SGTL5000_I2S_LRALIGN_CLR_MASK 0xFFFDU -#define SGTL5000_I2S_LRALIGN_GET_MASK 0x0002U -#define SGTL5000_I2S_LRALIGN_SHIFT 0x1U -#define SGTL5000_I2S_ONE_BIT_DELAY 0x0000U -#define SGTL5000_I2S_NO_DELAY 0x0002U -#define SGTL5000_I2S_LRPOL_CLR_MASK 0xFFFEU -#define SGTL5000_I2S_LRPOL_GET_MASK 0x0001U -#define SGTL5000_I2S_LRPOL_SHIFT 0x0U -#define SGTL5000_I2S_LEFT_FIRST 0x0000U -#define SGTL5000_I2S_RIGHT_FIRST 0x0001U - -/* - * SGTL5000_CHIP_SSS_CTRL - */ -#define SGTL5000_DAP_MIX_LRSWAP_CLR_MASK 0xBFFFU -#define SGTL5000_DAP_MIX_LRSWAP_GET_MASK 0x4000U -#define SGTL5000_DAP_MIX_LRSWAP_SHIFT 0xEU -#define SGTL5000_DAP_LRSWAP_CLR_MASK 0xDFFFU -#define SGTL5000_DAP_LRSWAP_GET_MASK 0x2000U -#define SGTL5000_DAP_LRSWAP_SHIFT 0xDU -#define SGTL5000_DAC_LRSWAP_CLR_MASK 0xEFFFU -#define SGTL5000_DAC_LRSWAP_GET_MASK 0x1000U -#define SGTL5000_DAC_LRSWAP_SHIFT 0xCU -#define SGTL5000_I2S_LRSWAP_CLR_MASK 0xFBFFU -#define SGTL5000_I2S_LRSWAP_GET_MASK 0x0400U -#define SGTL5000_I2S_LRSWAP_SHIFT 0xAU -#define SGTL5000_DAP_MIX_SEL_CLR_MASK 0xFCFFU -#define SGTL5000_DAP_MIX_SEL_GET_MASK 0x0300U -#define SGTL5000_DAP_MIX_SEL_SHIFT 0x8U -#define SGTL5000_DAP_MIX_SEL_ADC 0x0000U -#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x0100U -#define SGTL5000_DAP_SEL_CLR_MASK 0xFF3FU -#define SGTL5000_DAP_SEL_GET_MASK 0x00C0U -#define SGTL5000_DAP_SEL_SHIFT 0x6U -#define SGTL5000_DAP_SEL_ADC 0x0000U -#define SGTL5000_DAP_SEL_I2S_IN 0x0040U -#define SGTL5000_DAC_SEL_CLR_MASK 0xFFCFU -#define SGTL5000_DAC_SEL_GET_MASK 0x0030U -#define SGTL5000_DAC_SEL_SHIFT 0x4U -#define SGTL5000_DAC_SEL_ADC 0x0000U -#define SGTL5000_DAC_SEL_I2S_IN 0x0010U -#define SGTL5000_DAC_SEL_DAP 0x0030U -#define SGTL5000_I2S_OUT_SEL_CLR_MASK 0xFFFCU -#define SGTL5000_I2S_OUT_SEL_GET_MASK 0x0003U -#define SGTL5000_I2S_OUT_SEL_SHIFT 0x0U -#define SGTL5000_I2S_OUT_SEL_ADC 0x0000U -#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x0001U -#define SGTL5000_I2S_OUT_SEL_DAP 0x0003U - -/* - * SGTL5000_CHIP_ADCDAC_CTRL - */ -#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000U -#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000U -#define SGTL5000_DAC_VOL_RAMP_EN_CLR_MASK 0xFDFFU -#define SGTL5000_DAC_VOL_RAMP_EN_GET_MASK 0x0200U -#define SGTL5000_DAC_VOL_RAMP_EN_SHIFT 0x9U -#define SGTL5000_DAC_VOL_RAMP_EXPO_CLR_MASK 0xFEFFU -#define SGTL5000_DAC_VOL_RAMP_EXPO_GET_MASK 0x0100U -#define SGTL5000_DAC_VOL_RAMP_EXPO_SHIFT 0x8U -#define SGTL5000_DAC_MUTE_RIGHT_CLR_MASK 0xFFF7U -#define SGTL5000_DAC_MUTE_RIGHT_GET_MASK 0x0008U -#define SGTL5000_DAC_MUTE_RIGHT_SHIFT 0x3U -#define SGTL5000_DAC_MUTE_LEFT_CLR_MASK 0xFFFBU -#define SGTL5000_DAC_MUTE_LEFT_GET_MASK 0x0004U -#define SGTL5000_DAC_MUTE_LEFT_SHIFT 0x2U -#define SGTL5000_ADC_HPF_FREEZE_CLR_MASK 0xFFFDU -#define SGTL5000_ADC_HPF_FREEZE_GET_MASK 0x0002U -#define SGTL5000_ADC_HPF_FREEZE_SHIFT 0x1U -#define SGTL5000_ADC_HPF_BYPASS_CLR_MASK 0xFFFEU -#define SGTL5000_ADC_HPF_BYPASS_GET_MASK 0x0001U -#define SGTL5000_ADC_HPF_BYPASS_SHIFT 0x0U - -/* - * SGTL5000_CHIP_DAC_VOL - */ -#define SGTL5000_DAC_VOL_RIGHT_CLR_MASK 0x00FFU -#define SGTL5000_DAC_VOL_RIGHT_GET_MASK 0xFF00U -#define SGTL5000_DAC_VOL_RIGHT_SHIFT 0x8U -#define SGTL5000_DAC_VOL_LEFT_CLR_MASK 0xFF00U -#define SGTL5000_DAC_VOL_LEFT_GET_MASK 0x00FFU -#define SGTL5000_DAC_VOL_LEFT_SHIFT 0x0U - -/* - * SGTL5000_CHIP_PAD_STRENGTH - */ -#define SGTL5000_PAD_I2S_LRCLK_CLR_MASK 0xFCFFU -#define SGTL5000_PAD_I2S_LRCLK_GET_MASK 0x0300U -#define SGTL5000_PAD_I2S_LRCLK_SHIFT 0x8U -#define SGTL5000_PAD_I2S_SCLK_CLR_MASK 0xFF3FU -#define SGTL5000_PAD_I2S_SCLK_GET_MASK 0x00C0U -#define SGTL5000_PAD_I2S_SCLK_SHIFT 0x6U -#define SGTL5000_PAD_I2S_DOUT_CLR_MASK 0xFFCFU -#define SGTL5000_PAD_I2S_DOUT_GET_MASK 0x0030U -#define SGTL5000_PAD_I2S_DOUT_SHIFT 0x4U -#define SGTL5000_PAD_I2C_SDA_CLR_MASK 0xFFF3U -#define SGTL5000_PAD_I2C_SDA_GET_MASK 0x000CU -#define SGTL5000_PAD_I2C_SDA_SHIFT 0x2U -#define SGTL5000_PAD_I2C_SCL_CLR_MASK 0xFFFCU -#define SGTL5000_PAD_I2C_SCL_GET_MASK 0x0003U -#define SGTL5000_PAD_I2C_SCL_SHIFT 0x0U - -/* - * SGTL5000_CHIP_ANA_ADC_CTRL - */ -#define SGTL5000_ADC_VOL_M6DB_CLR_MASK 0xFEFFU -#define SGTL5000_ADC_VOL_M6DB_GET_MASK 0x0100U -#define SGTL5000_ADC_VOL_M6DB_SHIFT 0x8U -#define SGTL5000_ADC_VOL_RIGHT_CLR_MASK 0xFF0FU -#define SGTL5000_ADC_VOL_RIGHT_GET_MASK 0x00F0U -#define SGTL5000_ADC_VOL_RIGHT_SHIFT 0x4U -#define SGTL5000_ADC_VOL_LEFT_CLR_MASK 0xFFF0U -#define SGTL5000_ADC_VOL_LEFT_GET_MASK 0x000FU -#define SGTL5000_ADC_VOL_LEFT_SHIFT 0x0U - -/* - * SGTL5000_CHIP_ANA_HP_CTRL - */ -#define SGTL5000_HP_VOL_RIGHT_CLR_MASK 0x80FFU -#define SGTL5000_HP_VOL_RIGHT_GET_MASK 0x7F00U -#define SGTL5000_HP_VOL_RIGHT_SHIFT 0x8U -#define SGTL5000_HP_VOL_LEFT_CLR_MASK 0xFF80U -#define SGTL5000_HP_VOL_LEFT_GET_MASK 0x007FU -#define SGTL5000_HP_VOL_LEFT_SHIFT 0x0U - -/* - * SGTL5000_CHIP_ANA_CTRL - */ -#define SGTL5000_MUTE_LO_GET_MASK 0x0100U -#define SGTL5000_MUTE_LO_CLR_MASK 0xFEFFU -#define SGTL5000_MUTE_LO_SHIFT 0x8U -#define SGTL5000_SEL_HP_GET_MASK 0x0040U -#define SGTL5000_SEL_HP_CLR_MASK 0xFFBFU -#define SGTL5000_SEL_HP_SHIFT 0x6U -#define SGTL5000_SEL_HP_DAC 0x0000U -#define SGTL5000_SEL_HP_LINEIN 0x0040U -#define SGTL5000_EN_ZCD_HP_GET_MASK 0x0020U -#define SGTL5000_EN_ZCD_HP_CLR_MASK 0xFFDFU -#define SGTL5000_EN_ZCD_HP_SHIFT 0x5U -#define SGTL5000_MUTE_HP_GET_MASK 0x0010U -#define SGTL5000_MUTE_HP_CLR_MASK 0xFFEFU -#define SGTL5000_MUTE_HP_SHIFT 0x4U -#define SGTL5000_SEL_ADC_GET_MASK 0x0004U -#define SGTL5000_SEL_ADC_CLR_MASK 0xFFFBU -#define SGTL5000_SEL_ADC_SHIFT 0x2U -#define SGTL5000_SEL_ADC_MIC 0x0000U -#define SGTL5000_SEL_ADC_LINEIN 0x0004U -#define SGTL5000_EN_ZCD_ADC_GET_MASK 0x0002U -#define SGTL5000_EN_ZCD_ADC_CLR_MASK 0xFFFDU -#define SGTL5000_EN_ZCD_ADC_SHIFT 0x1U -#define SGTL5000_MUTE_ADC_GET_MASK 0x0001U -#define SGTL5000_MUTE_ADC_CLR_MASK 0xFFFEU -#define SGTL5000_MUTE_ADC_SHIFT 0x0U - -/* - * SGTL5000_CHIP_LINREG_CTRL - */ -#define SGTL5000_VDDC_MAN_ASSN_CLR_MASK 0xFFBFU -#define SGTL5000_VDDC_MAN_ASSN_GET_MASK 0x0040U -#define SGTL5000_VDDC_MAN_ASSN_SHIFT 0x6U -#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0000U -#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x0040U -#define SGTL5000_VDDC_ASSN_OVRD 0x0020U -#define SGTL5000_LINREG_VDDD_CLR_MASK 0xFFF0U -#define SGTL5000_LINREG_VDDD_GET_MASK 0x000FU -#define SGTL5000_LINREG_VDDD_SHIFT 0x0U - -/* - * SGTL5000_CHIP_REF_CTRL - */ -#define SGTL5000_ANA_GND_MASK 0x01f0U -#define SGTL5000_ANA_GND_SHIFT 0x4U -#define SGTL5000_ANA_GND_WIDTH 0x5U -#define SGTL5000_ANA_GND_BASE 0x320U /* mv */ -#define SGTL5000_ANA_GND_STP 0x19U /*mv */ -#define SGTL5000_BIAS_CTRL_MASK 0x000eU -#define SGTL5000_BIAS_CTRL_SHIFT 0x1U -#define SGTL5000_BIAS_CTRL_WIDTH 0x3U -#define SGTL5000_SMALL_POP 0x0001U - -/* - * SGTL5000_CHIP_MIC_CTRL - */ -#define SGTL5000_BIAS_R__CLR_MASK 0xFCFFU -#define SGTL5000_BIAS_R_GET_MASK 0x0300U -#define SGTL5000_BIAS_R_SHIFT 0x8U -#define SGTL5000_BIAS_R_off 0x0000U -#define SGTL5000_BIAS_R_2K 0x0100U -#define SGTL5000_BIAS_R_4k 0x0200U -#define SGTL5000_BIAS_R_8k 0x0300U -#define SGTL5000_BIAS_VOLT_CLR_MASK 0xFF8FU -#define SGTL5000_BIAS_VOLT_GET_MASK 0x0070U -#define SGTL5000_BIAS_VOLT_SHIFT 0x4U -#define SGTL5000_MIC_GAIN_CLR_MASK 0xFFFCU -#define SGTL5000_MIC_GAIN_GET_MASK 0x0003U -#define SGTL5000_MIC_GAIN_SHIFT 0x0U - -/* - * SGTL5000_CHIP_LINE_OUT_CTRL - */ -#define SGTL5000_LINE_OUT_CURRENT_CLR_MASK 0xF0FFU -#define SGTL5000_LINE_OUT_CURRENT_GET_MASK 0x0F00U -#define SGTL5000_LINE_OUT_CURRENT_SHIFT 0x8U -#define SGTL5000_LINE_OUT_CURRENT_180u 0x0000U -#define SGTL5000_LINE_OUT_CURRENT_270u 0x0100U -#define SGTL5000_LINE_OUT_CURRENT_360u 0x0300U -#define SGTL5000_LINE_OUT_CURRENT_450u 0x0700U -#define SGTL5000_LINE_OUT_CURRENT_540u 0x0F00U -#define SGTL5000_LINE_OUT_GND_CLR_MASK 0xFFC0U -#define SGTL5000_LINE_OUT_GND_GET_MASK 0x003FU -#define SGTL5000_LINE_OUT_GND_SHIFT 0x0U -#define SGTL5000_LINE_OUT_GND_BASE 0x320U /* mv */ -#define SGTL5000_LINE_OUT_GND_STP 0x19U -#define SGTL5000_LINE_OUT_GND_MAX 0x23U - -/* - * SGTL5000_CHIP_LINE_OUT_VOL - */ -#define SGTL5000_LINE_OUT_VOL_RIGHT_CLR_MASK 0xE0FFU -#define SGTL5000_LINE_OUT_VOL_RIGHT_GET_MASK 0x1F00U -#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 0x8U -#define SGTL5000_LINE_OUT_VOL_LEFT_CLR_MASK 0xFFE0U -#define SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK 0x001FU -#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0x0U - -/* - * SGTL5000_CHIP_ANA_POWER - */ -#define SGTL5000_RIGHT_DAC_POWERUP_GET_MASK 0x4000U -#define SGTL5000_RIGHT_DAC_POWERUP_CLR_MASK 0xBFFFU -#define SGTL5000_RIGHT_DAC_POWERUP_SHIFT 0xEU -#define SGTL5000_LINREG_SIMPLE_POWERUP_GET_MASK 0x2000U -#define SGTL5000_LINREG_SIMPLE_POWERUP_CLR_MASK 0xDFFFU -#define SGTL5000_LINREG_SIMPLE_POWERUP_SHIFT 0xDU -#define SGTL5000_STARTUP_POWERUP_GET_MASK 0x1000U -#define SGTL5000_STARTUP_POWERUP_CLR_MASK 0xEFFFU -#define SGTL5000_STARTUP_POWERUP_SHIFT 0xCU -#define SGTL5000_VDDC_CHRGPMP_POWERUP_GET_MASK 0x0800U -#define SGTL5000_VDDC_CHRGPMP_POWERUP_CLR_MASK 0xF7FFU -#define SGTL5000_VDDC_CHRGPMP_POWERUP_SHIFT 0xBU -#define SGTL5000_PLL_POWERUP_GET_MASK 0x0400U -#define SGTL5000_PLL_POWERUP_CLR_MASK 0xFBFFU -#define SGTL5000_PLL_POWERUP_SHIFT 0xAU -#define SGTL5000_LINREG_D_POWERUP_GET_MASK 0x0200U -#define SGTL5000_LINREG_D_POWERUP_CLR_MASK 0xFDFFU -#define SGTL5000_LINREG_D_POWERUP_SHIFT 0x9U -#define SGTL5000_VCOAMP_POWERUP_GET_MASK 0x0100U -#define SGTL5000_VCOAMP_POWERUP_CLR_MASK 0xFEFFU -#define SGTL5000_VCOAMP_POWERUP_SHIFT 0x8U -#define SGTL5000_VAG_POWERUP_GET_MASK 0x0080U -#define SGTL5000_VAG_POWERUP_CLR_MASK 0xFF7FU -#define SGTL5000_VAG_POWERUP_SHIFT 0x7U -#define SGTL5000_RIGHT_ADC_POWERUP_GET_MASK 0x0040U -#define SGTL5000_RIGHT_ADC_POWERUP_CLR_MASK 0xFFBFU -#define SGTL5000_RIGHT_ADC_POWERUP_SHIFT 0x6U -#define SGTL5000_REFTOP_POWERUP_GET_MASK 0x0020U -#define SGTL5000_REFTOP_POWERUP_CLR_MASK 0xFFDFU -#define SGTL5000_REFTOP_POWERUP_SHIFT 0x5U -#define SGTL5000_HEADPHONE_POWERUP_GET_MASK 0x0010U -#define SGTL5000_HEADPHONE_POWERUP_CLR_MASK 0xFFEFU -#define SGTL5000_HEADPHONE_POWERUP_SHIFT 0x4U -#define SGTL5000_DAC_POWERUP_GET_MASK 0x0008U -#define SGTL5000_DAC_POWERUP_CLR_MASK 0xFFF7U -#define SGTL5000_DAC_POWERUP_SHIFT 0x3U -#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_GET_MASK 0x0004U -#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_CLR_MASK 0xFFFBU -#define SGTL5000_CAPLESS_HEADPHONE_POWERUP_SHIFT 0x2U -#define SGTL5000_ADC_POWERUP_GET_MASK 0x0002U -#define SGTL5000_ADC_POWERUP_CLR_MASK 0xFFFDU -#define SGTL5000_ADC_POWERUP_SHIFT 0x1U -#define SGTL5000_LINEOUT_POWERUP_GET_MASK 0x0001U -#define SGTL5000_LINEOUT_POWERUP_CLR_MASK 0xFFFEU -#define SGTL5000_LINEOUT_POWERUP_SHIFT 0x0U - -/* - * SGTL5000_CHIP_PLL_CTRL - */ -#define SGTL5000_PLL_INT_DIV_CLR_MASK 0x07FFU -#define SGTL5000_PLL_INT_DIV_GET_MASK 0xF800U -#define SGTL5000_PLL_INT_DIV_SHIFT 0xBU -#define SGTL5000_PLL_FRAC_DIV_CLR_MASK 0xF8FFU -#define SGTL5000_PLL_FRAC_DIV_GET_MASK 0x0700U -#define SGTL5000_PLL_FRAC_DIV_SHIFT 0x0U - -/* - * SGTL5000_CHIP_CLK_TOP_CTRL - */ -#define SGTL5000_ENABLE_INT_OSC_GET_MASK 0x0800U -#define SGTL5000_ENABLE_INT_OSC_CLR_MASK 0xF7FFU -#define SGTL5000_ENABLE_INT_OSC_SHIFT 0xBU -#define SGTL5000_INPUT_FREQ_DIV2_GET_MASK 0x0008U -#define SGTL5000_INPUT_FREQ_DIV2_CLR_MASK 0xFFF7U -#define SGTL5000_INPUT_FREQ_DIV2_SHIFT 0x3U - -/* - * SGTL5000_CHIP_ANA_STATUS - */ -#define SGTL5000_HP_LRSHORT 0x0200U -#define SGTL5000_CAPLESS_SHORT 0x0100U -#define SGTL5000_PLL_LOCKED 0x0010U - -/* - * SGTL5000_CHIP_SHORT_CTRL - */ -#define SGTL5000_LVLADJR_CLR_MASK 0x8FFFU -#define SGTL5000_LVLADJR_GET_MASK 0x7000U -#define SGTL5000_LVLADJR_SHIFT 0xCU -#define SGTL5000_LVLADJL_CLR_MASK 0xF8FFU -#define SGTL5000_LVLADJL_GET_MASK 0x0700U -#define SGTL5000_LVLADJL_SHIFT 0x8U -#define SGTL5000_LVLADJC_CLR_MASK 0xFF8FU -#define SGTL5000_LVLADJC_GET_MASK 0x0070U -#define SGTL5000_LVLADJC_SHIFT 0x4U -#define SGTL5000_LR_SHORT_MOD_CLR_MASK 0xFFF3U -#define SGTL5000_LR_SHORT_MOD_GET_MASK 0x000CU -#define SGTL5000_LR_SHORT_MOD_SHIFT 0x2U -#define SGTL5000_CM_SHORT_MOD_CLR_MASK 0xFFFCU -#define SGTL5000_CM_SHORT_MOD_GET_MASK 0x0003U -#define SGTL5000_CM_SHORT_MOD_SHIFT 0x0U - -/* DAP control register */ -#define SGTL5000_DAP_CONTROL_MIX_EN_GET_MASK 0x0010U -#define SGTL5000_DAP_CONTROL_MIX_EN_CLR_MASK 0xFFEFU -#define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT 0x4U -#define SGTL5000_DAP_CONTROL_DAP_EN_GET_MASK 0x0001U -#define SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK 0xFFFEU -#define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT 0x0U - -/* - * DAP_PEQ_REG - */ -#define SGTL5000_DAP_PEQ_EN_GET_MASK 0x0007U -#define SGTL5000_DAP_PEQ_EN_CLR_MASK 0xFFF8U -#define SGTL5000_DAP_PEQ_EN_SHIFT 0x0U - -/* - * DAP_BASS_ENHANCE_REG - */ -#define SGTL5000_DAP_BASS_ENHANCE_MULT_GET_MASK 0xC000U -#define SGTL5000_DAP_BASS_ENHANCE_MULT_CLR_MASK 0x3FFFU -#define SGTL5000_DAP_BASS_ENHANCE_MULT_SHIFT 0xEU -#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_GET_MASK 0x0E00U -#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_CLR_MASK 0xF1FFU -#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_SHIFT 0x9U -#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_GET_MASK 0x0100U -#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_CLR_MASK 0xFEFFU -#define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT 0x8U -#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_GET_MASK 0x0070U -#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_CLR_MASK 0xFF8FU -#define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT 0x4U -#define SGTL5000_DAP_BASS_ENHANCE_EN_GET_MASK 0x0001U -#define SGTL5000_DAP_BASS_ENHANCE_EN_CLR_MASK 0xFFFEU -#define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT 0x0U - -/* - * DAP_BASS_ENHANCE_CTRL_REG - */ -#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_GET_MASK 0x3F00U -#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_CLR_MASK 0xC0FFU -#define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT 0x8U -#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_GET_MASK 0x007FU -#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_CLR_MASK 0xFF80U -#define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_SHIFT 0x0U - -/* - * DAP_AUDIO_EQ_REG - */ -#define SGTL5000_DAP_AUDIO_EQ_EN_GET_MASK 0x0003U -#define SGTL5000_DAP_AUDIO_EQ_EN_CLR_MASK 0xFFFCU -#define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT 0x0U - -/* - * DAP_SGTL_SURROUND_REG - */ -#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_GET_MASK 0x0070U -#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_CLR_MASK 0xFF8FU -#define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT 0x4U -#define SGTL5000_DAP_SGTL_SURROUND_SEL_GET_MASK 0x0003U -#define SGTL5000_DAP_SGTL_SURROUND_SEL_CLR_MASK 0xFFFCU -#define SGTL5000_DAP_SGTL_SURROUND_SEL_SHIFT 0x0U - -/* - * DAP_FILTER_COEF_ACCESS_REG - */ -#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_GET_MASK 0x1000U -#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_CLR_MASK 0xEFFFU -#define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_SHIFT 0xCU -#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_GET_MASK 0x0200U -#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_CLR_MASK 0xFDFFU -#define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_SHIFT 0x9U -#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_GET_MASK 0x0100U -#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_CLR_MASK 0xFEFFU -#define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT 0x8U -#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_GET_MASK 0x00FFU -#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_CLR_MASK 0xFF00U -#define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT 0x0U - -/* - * DAP_COEF_WR_B0_MSB_REG - */ -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_GET_MASK 0x8000U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_CLR_MASK 0x7FFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_SHIFT 0xFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_GET_MASK 0x4000U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_CLR_MASK 0xBFFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_SHIFT 0xEU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_GET_MASK 0x2000U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_CLR_MASK 0xDFFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_SHIFT 0xDU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_GET_MASK 0x1000U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_CLR_MASK 0xEFFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_SHIFT 0xCU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_GET_MASK 0x0800U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_CLR_MASK 0xF7FFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_SHIFT 0xBU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_GET_MASK 0x0400U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_CLR_MASK 0xFBFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_SHIFT 0xAU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_GET_MASK 0x0200U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_CLR_MASK 0xFDFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_SHIFT 0x9U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_GET_MASK 0x0100U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_CLR_MASK 0xFEFFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_SHIFT 0x8U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_GET_MASK 0x0080U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_CLR_MASK 0xFF7FU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_SHIFT 0x7U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_GET_MASK 0x0040U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_CLR_MASK 0xFFBFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_SHIFT 0x6U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_GET_MASK 0x0020U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_CLR_MASK 0xFFDFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_SHIFT 0x5U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_GET_MASK 0x0010U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_CLR_MASK 0xFFEFU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_SHIFT 0x4U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_GET_MASK 0x0008U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_CLR_MASK 0xFFF7U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_SHIFT 0x3U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_GET_MASK 0x0004U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_CLR_MASK 0xFFFBU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_SHIFT 0x2U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_GET_MASK 0x0002U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_CLR_MASK 0xFFFDU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_SHIFT 0x1U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_GET_MASK 0x0001U -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_CLR_MASK 0xFFFEU -#define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_SHIFT 0x0U - -/* - * DAP_COEF_WR_B0_LSB_REG - */ -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_GET_MASK 0x0008U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_CLR_MASK 0xFFF7U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_SHIFT 0x3U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_GET_MASK 0x0004U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_CLR_MASK 0xFFFBU -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_SHIFT 0x2U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_GET_MASK 0x0002U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_CLR_MASK 0xFFFDU -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_SHIFT 0x1U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_GET_MASK 0x0001U -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_CLR_MASK 0xFFFEU -#define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_SHIFT 0x0U - -/* - * DAP_AUDIO_EQ_BASS_BAND0_REG - */ -#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_GET_MASK 0x007FU -#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_CLR_MASK 0xFF80U -#define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT 0x0U - -/* - * DAP_AUDIO_EQ_BAND1_REG - */ -#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_GET_MASK 0x007FU -#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_CLR_MASK 0xFF80U -#define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT 0x0U - -/* - * DAP_AUDIO_EQ_BAND2_REG - */ -#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_GET_MASK 0x007FU -#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_CLR_MASK 0xFF80U -#define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT 0x0U - -/* - * DAP_AUDIO_EQ_BAND3_REG - */ -#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_GET_MASK 0x007FU -#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_CLR_MASK 0xFF80U -#define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT 0x0U - -/* - * DAP_AUDIO_EQ_TREBLE_BAND4_REG - */ -#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_GET_MASK 0x007FU -#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_CLR_MASK 0xFF80U -#define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_SHIFT 0x0U - -/* - * DAP_MAIN_CHAN_REG - */ -#define SGTL5000_DAP_MAIN_CHAN_VOL_GET_MASK 0xFFFFU -#define SGTL5000_DAP_MAIN_CHAN_VOL_CLR_MASK 0x0000U -#define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT 0x0U - -/* - * DAP_MIX_CHAN_REG - */ -#define SGTL5000_DAP_MIX_CHAN_VOL_GET_MASK 0xFFFFU -#define SGTL5000_DAP_MIX_CHAN_VOL_CLR_MASK 0x0000U -#define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT 0x0U - -/* - * DAP_AVC_CTRL_REG - */ -#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_GET_MASK 0x4000U -#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_CLR_MASK 0xBFFFU -#define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_SHIFT 0xEU -#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_GET_MASK 0x3000U -#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_CLR_MASK 0xCFFFU -#define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT 0xCU -#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_GET_MASK 0x0300U -#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_CLR_MASK 0xFCFFU -#define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT 0x8U -#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_GET_MASK 0x0020U -#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_CLR_MASK 0xFFDFU -#define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT 0x5U -#define SGTL5000_DAP_AVC_CTRL_STOP_GET_MASK 0x0004U -#define SGTL5000_DAP_AVC_CTRL_STOP_SHIFT 0x2U -#define SGTL5000_DAP_AVC_CTRL_RUNNING_GET_MASK 0x0002U -#define SGTL5000_DAP_AVC_CTRL_RUNNING_SHIFT 0x1U -#define SGTL5000_DAP_AVC_CTRL_EN_GET_MASK 0x0001U -#define SGTL5000_DAP_AVC_CTRL_EN_CLR_MASK 0xFFFEU -#define SGTL5000_DAP_AVC_CTRL_EN_SHIFT 0x0U - -/* - * DAP_AVC_ATTACK_REG - */ -#define SGTL5000_DAP_AVC_ATTACK_RATE_GET_MASK 0x0FFFU -#define SGTL5000_DAP_AVC_ATTACK_RATE_CLR_MASK 0xF000U -#define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT 0x0U - -/* - * DAP_AVC_DECAY_REG - */ -#define SGTL5000_DAP_AVC_DECAY_RATE_GET_MASK 0x0FFFU -#define SGTL5000_DAP_AVC_DECAY_RATE_CLR_MASK 0xF000U -#define SGTL5000_DAP_AVC_DECAY_RATE_SHIFT 0x0U - -/* - * DAP_COEF_WR_B1_LSB_REG - */ -#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_GET_MASK 0x000FU -#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_CLR_MASK 0xFFF0U -#define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT 0x0U - -/* - * DAP_COEF_WR_B2_LSB_REG - */ -#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_GET_MASK 0x000FU -#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_CLR_MASK 0xFFF0U -#define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT 0x0U - -/* - * DAP_COEF_WR_A1_LSB_REG - */ -#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_GET_MASK 0x000FU -#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_CLR_MASK 0xFFF0U -#define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT 0x0U - -/* - * DAP_COEF_WR_A2_LSB_REG - */ -#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_GET_MASK 0x000FU -#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_CLR_MASK 0xFFF0U -#define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT 0x0U - -/*! @brief SGTL5000 volume setting range */ -#define SGTL5000_HEADPHONE_MAX_VOLUME_VALUE 0x7FU -#define SGTL5000_HEADPHONE_MIN_VOLUME_VALUE 0U -#define SGTL5000_LINE_OUT_MAX_VOLUME_VALUE 0x1FU -#define SGTL5000_LINE_OUT_MIN_VOLUME_VALUE 0U -#define SGTL5000_ADC_MAX_VOLUME_VALUE 0xFU -#define SGTL5000_ADC_MIN_VOLUME_VALUE 0U -#define SGTL5000_DAC_MAX_VOLUME_VALUE 0xF0U -#define SGTL5000_DAC_MIN_VOLUME_VALUE 0x3CU - -/*! @brief SGTL5000 I2C address. */ -#define SGTL5000_I2C_ADDR 0x0A - -/*! @brief sgtl i2c baudrate */ -#define SGTL_I2C_BITRATE 100000U - -/*! @brief Modules in Sgtl5000 board. */ -typedef enum _sgtl5000_module { - sgtl_module_adc = 0x0, /*!< ADC module in SGTL5000 */ - sgtl_module_dac, /*!< DAC module in SGTL5000 */ - sgtl_module_dap, /*!< DAP module in SGTL5000 */ - sgtl_module_hp, /*!< Headphone module in SGTL5000 */ - sgtl_module_i2sin, /*!< I2S-IN module in SGTL5000 */ - sgtl_module_i2sout, /*!< I2S-OUT module in SGTL5000 */ - sgtl_module_linein, /*!< Line-in moudle in SGTL5000 */ - sgtl_module_lineout, /*!< Line-out module in SGTL5000 */ - sgtl_module_micin /*!< Micphone module in SGTL5000 */ -} sgtl_module_t; - -/*! - * @brief Sgtl5000 data route. - * @note Only provide some typical data route, not all route listed. - * Users cannot combine any routes, once a new route is set, the precios one would be replaced. - */ -typedef enum _sgtl_route { - sgtl_route_bypass = 0x0, /*!< LINEIN->Headphone. */ - sgtl_route_playback, /*!< I2SIN->DAC->Headphone. */ - sgtl_route_playback_record, /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */ - sgtl_route_playback_with_dap, /*!< I2SIN->DAP->DAC->Headphone. */ - sgtl_route_playback_with_dap_record, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */ - sgtl_route_record /*!< LINEIN->ADC->I2SOUT. */ -} sgtl_route_t; - -/*! - * @brief The audio data transfer protocol choice. - * Sgtl5000 only supports I2S format and PCM format. - */ -typedef enum _sgtl_protocol { - sgtl_bus_i2s = 0x0, /*!< I2S Type */ - sgtl_bus_left_justified, /*!< Left justified */ - sgtl_bus_right_justified, /*!< Right Justified */ - sgtl_bus_pcma, /*!< PCMA */ - sgtl_bus_pcmb /*!< PCMB */ -} sgtl_protocol_t; - -/*! @brief sgtl play channel - * @anchor _sgtl_play_channel - */ -enum { - sgtl_headphone_left = 0, /*!< headphone left channel */ - sgtl_headphone_right = 1, /*!< headphone right channel */ - sgtl_lineout_left = 2, /*!< lineout left channel */ - sgtl_lineout_right = 3, /*!< lineout right channel */ -}; - -/*! @brief sgtl record source - * _sgtl_record_source - */ -enum { - sgtl_record_source_linein = 0U, /*!< record source line in */ - sgtl_record_source_mic = 1U, /*!< record source single end */ -}; - -/*! @brief sgtl play source - * _stgl_play_source - */ -enum { - sgtl_play_source_linein = 0U, /*!< play source line in */ - sgtl_play_source_dac = 1U, /*!< play source line in */ -}; - -/*! @brief SGTL SCLK valid edge */ -typedef enum _sgtl_sclk_edge { - sgtl_sclk_valid_edge_rising = 0U, /*!< SCLK valid edge */ - sgtl_sclk_valid_edge_failing = 1U, /*!< SCLK failling edge */ -} sgtl_sclk_edge_t; - -/*! @brief Audio format configuration. */ -typedef struct _sgtl_audio_format { - uint32_t mclk_hz; /*!< master clock */ - uint32_t sample_rate; /*!< Sample rate */ - uint32_t bit_width; /*!< Bit width */ - sgtl_sclk_edge_t sclk_edge; /*!< sclk valid edge */ -} sgtl_audio_format_t; - -/*! @brief Initailize structure of sgtl5000 */ -typedef struct _sgtl_config { - sgtl_route_t route; /*!< Audio data route.*/ - sgtl_protocol_t bus; /*!< Audio transfer protocol */ - bool master; /*!< Master or slave. True means master, false means slave. */ - sgtl_audio_format_t format; /*!< audio format */ -} sgtl_config_t; - -typedef struct { - I2C_Type *ptr; /*!< sgtl I2C pointer */ - uint8_t slave_address; /*!< code device slave address */ -} sgtl_context_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief sgtl5000 initialize function. - * - * In this function, some configurations are fixed. - * The second parameter can be NULL. If users want to change the SGTL5000 settings, - * a configure structure should be prepared. - * @note If the codec_config is NULL, it would initialize sgtl5000 using default settings. - * The default setting: - * @code - * sgtl_init_t codec_config - * codec_config.route = sgtl_route_playback_record - * codec_config.bus = sgtl_bus_i2s - * codec_config.master = slave - * @endcode - * - * @param context Sgtl5000 context structure. - * @param config sgtl5000 configuration structure. If this pointer equals to NULL, - * it means using the default configuration. - * @return Initialization status - */ -hpm_stat_t sgtl_init(sgtl_context_t *context, sgtl_config_t *config); - -/*! - * @brief Set audio data route in sgtl5000. - * - * This function would set the data route according to route. The route cannot be combined, - * as all route would enable different modules. - * - * @note If a new route is set, the previous route would not work. - * @param context Sgtl5000 context structure. - * @param route Audio data route in sgtl5000. - */ -hpm_stat_t sgtl_set_data_route(sgtl_context_t *context, sgtl_route_t route); - -/*! - * @brief Set the audio transfer protocol. - * - * Sgtl5000 only supports I2S, I2S left, I2S right, PCM A, PCM B format. - * @param context Sgtl5000 context structure. - * @param protocol Audio data transfer protocol. - */ -hpm_stat_t sgtl_set_protocol(sgtl_context_t *context, sgtl_protocol_t protocol); - -/*! - * @brief Set sgtl5000 as master or slave. - * - * @param context Sgtl5000 context structure. - * @param master 1 represent master, 0 represent slave. - */ -void sgtl_set_master_mode(sgtl_context_t *context, bool master); - -/*! - * @brief Set the volume of different modules in sgtl5000. - * - * This function would set the volume of sgtl5000 modules. This interface set module volume. - * The function assume that left channel and right channel has the same volume. - * - * sgtl_module_adc volume range: 0 - 0xF, 0dB - 22.5dB - * sgtl_module_dac volume range: 0x3C - 0xF0, 0dB - -90dB - * sgtl_module_hp volume range: 0 - 0x7F, 12dB - -51.5dB - * sgtl_module_lineout volume range: 0 - 0x1F, 0.5dB steps - * - * @param context Sgtl5000 context structure. - * @param module Sgtl5000 module, such as DAC, ADC and etc. - * @param volume Volume value need to be set. The value is the exact value in register. - */ -hpm_stat_t sgtl_set_volume(sgtl_context_t *context, sgtl_module_t module, uint32_t volume); - -/*! - * @brief Get the volume of different modules in sgtl5000. - * - * This function gets the volume of sgtl5000 modules. This interface get DAC module volume. - * The function assume that left channel and right channel has the same volume. - * @param context Sgtl5000 context structure. - * @param module Sgtl5000 module, such as DAC, ADC and etc. - * @return Module value, the value is exact value in register. - */ -uint32_t sgtl_get_volume(sgtl_context_t *context, sgtl_module_t module); - -/*! - * @brief Mute/unmute modules in sgtl5000. - * - * @param context Sgtl5000 context structure. - * @param module Sgtl5000 module, such as DAC, ADC and etc. - * @param mute True means mute, and false means unmute. - */ -hpm_stat_t sgtl_set_mute(sgtl_context_t *context, sgtl_module_t module, bool mute); - -/*! - * @brief Enable expected devices. - * @param context Sgtl5000 context structure. - * @param module Module expected to enable. - */ -hpm_stat_t sgtl_enable_module(sgtl_context_t *context, sgtl_module_t module); - -/*! - * @brief Disable expected devices. - * @param context Sgtl5000 context structure. - * @param module Module expected to enable. - */ -hpm_stat_t sgtl_disable_module(sgtl_context_t *context, sgtl_module_t module); - -/*! - * @brief Deinit the sgtl5000 codec. Shut down Sgtl5000 modules. - * @param context Sgtl5000 context structure pointer. - */ -hpm_stat_t sgtl_deint(sgtl_context_t *context); - -/*! - * @brief Configure the data format of audio data. - * - * This function would configure the registers about the sample rate, bit depths. - * @param context Sgtl5000 context structure pointer. - * @param mclk Master clock frequency of I2S. - * @param sample_rate Sample rate of audio file running in sgtl5000. Sgtl5000 now - * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate. - * @param bits Bit depth of audio file (Sgtl5000 only supports 16bit, 20bit, 24bit - * and 32 bit in HW). - */ -hpm_stat_t sgtl_config_data_format(sgtl_context_t *context, uint32_t mclk, uint32_t sample_rate, uint32_t bits); - -/*! - * @brief select SGTL codec play source. - * - * @param context Sgtl5000 context structure pointer. - * @param playSource play source value, reference _sgtl_play_source. - * - * @return kStatus_Success, else failed. - */ -hpm_stat_t sgtl_set_play(sgtl_context_t *context, uint32_t playSource); - -/*! - * @brief select SGTL codec record source. - * - * @param context Sgtl5000 context structure pointer. - * @param recordSource record source value, reference _sgtl_record_source. - * - * @return kStatus_Success, else failed. - */ -hpm_stat_t sgtl_set_record(sgtl_context_t *context, uint32_t recordSource); - -/*! - * @brief Write register to sgtl using I2C. - * @param context Sgtl5000 context structure. - * @param reg The register address in sgtl. - * @param val Value needs to write into the register. - */ -hpm_stat_t sgtl_write_reg(sgtl_context_t *context, uint16_t reg, uint16_t val); - -/*! - * @brief Read register from sgtl using I2C. - * @param context Sgtl5000 context structure. - * @param reg The register address in sgtl. - * @param val Value written to. - */ -hpm_stat_t sgtl_read_reg(sgtl_context_t *context, uint16_t reg, uint16_t *val); - -/*! - * @brief Modify some bits in the register using I2C. - * @param context Sgtl5000 context structure. - * @param reg The register address in sgtl. - * @param clr_mask The mask code for the bits want to write. The bit you want to write should be 0. - * @param val Value needs to write into the register. - */ -hpm_stat_t sgtl_modify_reg(sgtl_context_t *context, uint16_t reg, uint16_t clr_mask, uint16_t val); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _HPM_SGTL5000_H_ */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.c b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.c deleted file mode 100644 index 7548399616f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.c +++ /dev/null @@ -1,405 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_wm8978.h" - -#define WM8978_I2C_SLAVE_ADDRESS1 (0x1A) -#define WM8978_I2C_SLAVE_ADDRESS2 (0x1A) - -/* store reg value */ -static volatile uint16_t wm8978_reg_val[] = { - 0x000, 0x000, 0x000, 0x000, 0x050, 0x000, 0x140, 0x000, - 0x000, 0x000, 0x000, 0x0FF, 0x0FF, 0x000, 0x100, 0x0FF, - 0x0FF, 0x000, 0x12C, 0x02C, 0x02C, 0x02C, 0x02C, 0x000, - 0x032, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, - 0x038, 0x00B, 0x032, 0x000, 0x008, 0x00C, 0x093, 0x0E9, - 0x000, 0x000, 0x000, 0x000, 0x003, 0x010, 0x010, 0x100, - 0x100, 0x002, 0x001, 0x001, 0x039, 0x039, 0x039, 0x039, -}; -; - -hpm_stat_t wm8979_init(wm8978_context_t *control) -{ - hpm_stat_t stat; - uint8_t i; - for (i = 0; i < 0x7F; i++) { - if (i2c_master_write(control->ptr, i, NULL, 0) == status_success) { - if ((i == WM8978_I2C_SLAVE_ADDRESS1) || (i == WM8978_I2C_SLAVE_ADDRESS2)) { - control->device_address = i; - break; - } - } - } - if (i == 0x7F) { - return status_fail; - } - stat = wm8978_reset(control); - return stat; -} - -hpm_stat_t wm8978_reset(wm8978_context_t *control) -{ - hpm_stat_t stat = status_success; - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RESET, 0)); - return stat; -} - -hpm_stat_t wm8978_set_out_volume(wm8978_context_t *control, wm8978_out_channel_t channel, uint8_t volume) -{ - hpm_stat_t stat = status_success; - uint8_t l_out_reg; - uint8_t r_out_reg; - if (volume > WM8978_OUT_VOLUME_MASK) { - volume = WM8978_OUT_VOLUME_MASK; - } - if (channel == wm8978_out1_channel) { - l_out_reg = WM8978_LOUT1_VOLUME_CTRL; - r_out_reg = WM8978_ROUT1_VOLUME_CTRL; - } else if (channel == wm8978_out2_channel) { - l_out_reg = WM8978_LOUT2_VOLUME_CTRL; - r_out_reg = WM8978_ROUT2_VOLUME_CTRL; - } else { - return status_invalid_argument; - } - HPM_CHECK_RET(wm8978_write_reg(control, l_out_reg, WM8978_OUT_VOLUME_SET(volume) | WM8978_OUT_SPKVU_SET(0))); - /* LOUT1/2 and ROUT1/2 volumes do not update untila 1 is written to SPKkVU */ - HPM_CHECK_RET(wm8978_write_reg(control, r_out_reg, WM8978_OUT_VOLUME_SET(volume) | WM8978_OUT_SPKVU_SET(1))); - return stat; -} - -hpm_stat_t wm8978_get_out_volume(wm8978_context_t *control, wm8978_out_channel_t channel, uint8_t *volume) -{ - hpm_stat_t stat = status_success; - uint8_t out_reg; - uint16_t val; - if (channel == wm8978_out1_channel) { - out_reg = WM8978_LOUT1_VOLUME_CTRL; - } else if (channel == wm8978_out2_channel) { - out_reg = WM8978_LOUT2_VOLUME_CTRL; - } else { - return status_invalid_argument; - } - HPM_CHECK_RET(wm8978_read_reg(control, out_reg, &val)); - *volume = WM8978_OUT_VOLUME_GET(val); - return stat; -} - -hpm_stat_t wm8978_set_out_mute(wm8978_context_t *control, wm8978_out_channel_t channel, bool mute) -{ - hpm_stat_t stat = status_success; - uint16_t val; - uint8_t l_out_reg; - uint8_t r_out_reg; - if (channel == wm8978_out1_channel) { - l_out_reg = WM8978_LOUT1_VOLUME_CTRL; - r_out_reg = WM8978_ROUT1_VOLUME_CTRL; - } else if (channel == wm8978_out2_channel) { - l_out_reg = WM8978_LOUT2_VOLUME_CTRL; - r_out_reg = WM8978_ROUT2_VOLUME_CTRL; - } else { - return status_invalid_argument; - } - if (mute == true) { - HPM_CHECK_RET(wm8978_read_reg(control, l_out_reg, &val)); - val |= WM8978_OUT_MUTE_MASK; - HPM_CHECK_RET(wm8978_write_reg(control, l_out_reg, val)); - HPM_CHECK_RET(wm8978_read_reg(control, r_out_reg, &val)); - val |= WM8978_OUT_MUTE_MASK; - HPM_CHECK_RET(wm8978_write_reg(control, r_out_reg, val)); - } else { - HPM_CHECK_RET(wm8978_read_reg(control, l_out_reg, &val)); - val &= ~WM8978_OUT_MUTE_MASK; - HPM_CHECK_RET(wm8978_write_reg(control, l_out_reg, val)); - HPM_CHECK_RET(wm8978_read_reg(control, r_out_reg, &val)); - val &= ~WM8978_OUT_MUTE_MASK; - HPM_CHECK_RET(wm8978_write_reg(control, r_out_reg, val)); - } - return stat; -} - -hpm_stat_t wm8978_set_mic_gain(wm8978_context_t *control, uint8_t gain) -{ - hpm_stat_t stat = status_success; - if (gain > WM8978_INPPGA_VOL_MASK) { - gain = WM8978_INPPGA_VOL_MASK; - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LINP_PGA_GAIM_CTRL, WM8978_INPPGA_VOL_SET(gain))); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LINP_PGA_GAIM_CTRL, WM8978_INPPGA_VOL_SET(gain) | WM8978_INPGA_UPDATE_SET(1))); - return stat; -} - -hpm_stat_t wm8978_set_line_gain(wm8978_context_t *control, uint8_t gain) -{ - uint16_t val; - hpm_stat_t stat = status_success; - if (gain > WM8978_AUXL2BOOSTVOL_MASK) { - gain = WM8978_AUXL2BOOSTVOL_MASK; - } - HPM_CHECK_RET(wm8978_read_reg(control, WM8978_LADC_BOOST_CTRL, &val)); - val &= (~WM8978_2_2_BOOSTVOL_MASK); - val |= WM8978_2_2_BOOSTVOL_SET(gain); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LADC_BOOST_CTRL, val)); - - HPM_CHECK_RET(wm8978_read_reg(control, WM8978_RADC_BOOST_CTRL, &val)); - val &= ~WM8978_2_2_BOOSTVOL_MASK; - val |= WM8978_2_2_BOOSTVOL_SET(gain); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RADC_BOOST_CTRL, val)); - return stat; -} - -hpm_stat_t wm8978_power_down(wm8978_context_t *control) -{ - return wm8978_reset(control); -} - -hpm_stat_t wm8978_cfg_audio_interface(wm8978_context_t *control, wm8978_audio_interface_t standard, wm8978_word_length_t word_len) -{ - hpm_stat_t stat = status_success; - uint16_t usReg = 0; - usReg |= WM8978_FMT_SET(standard) | WM8978_WL_SET(word_len); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_AUDIO_INTERFACE, usReg)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_CLOCK_GEN_CTRL, 0x000)); - return stat; -} - -hpm_stat_t wm8978_cfg_audio_channel(wm8978_context_t *control, input_channel_flags_t in_flags, output_channel_flag_t out_flags) -{ - uint16_t reg_val = 0; - hpm_stat_t stat = status_success; - if ((in_flags == input_off) && (out_flags == output_off)) { - wm8978_power_down(control); - return stat; - } - - reg_val = WM8978_BIASEN_R1_MASK | WM8978_VMIDSEL_R1_SET(3); - if (out_flags & out_3_4_on) { - reg_val |= (WM8978_OUT4MIXEN_R1_MASK | WM8978_OUT3MIXEN_R1_MASK); - } - if ((in_flags & mic_left_on) || (in_flags & mic_right_on)) { - reg_val |= WM8978_MICBEN_R1_MASK; - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_POWER_MANAGET_1, reg_val)); - - reg_val = 0; - if (out_flags & earphone_left_on) { - reg_val |= WM8978_LOUT1EN_R2_MASK; - } - if (out_flags & earphone_right_on) { - reg_val |= WM8978_ROUT1EN_R2_MASK; - } - if (in_flags & mic_left_on) { - reg_val |= (WM8978_BOOSTENL_R2_MASK | WM8978_INPPGAENL_R2_MASK); - } - if (in_flags & mic_right_on) { - reg_val |= (WM8978_BOOSTENR_R2_MASK | WM8978_INPPGAENR_R2_MASK); - } - if (in_flags & line_on) { - reg_val |= (WM8978_BOOSTENL_R2_MASK | WM8978_BOOSTENR_R2_MASK); - } - if (in_flags & adc_on) { - reg_val |= (WM8978_ADCENR_R2_MASK | WM8978_ADCENL_R2_MASK); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_POWER_MANAGET_2, reg_val)); - - reg_val = 0; - if (out_flags & out_3_4_on) { - reg_val |= (WM8978_OUT4EN_R3_MASK | WM8978_OUT3EN_R3_MASK); - } - if (out_flags & spk_on) { - reg_val |= (WM8978_LOUT2EN_R3_MASK | WM8978_ROUT2EN_R3_MASK); - } - if (out_flags != output_off) { - reg_val |= (WM8978_RMIXEN_R3_MASK | WM8978_LMIXEN_R3_MASK); - } - if (in_flags & dac_on) { - reg_val |= (WM8978_DACENR_R3_MASK | WM8978_DACENL_R3_MASK); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_POWER_MANAGET_3, reg_val)); - - reg_val = 0 << 8; - if (in_flags & line_on) { - reg_val |= (WM8978_R2_2INPPGA_R44_MASK | WM8978_L2_2INPPGA_R44_MASK); - } - if (in_flags & mic_right_on) { - reg_val |= (WM8978_RIN2INPPGA_R44_MASK | WM8978_RIP2INPPGA_R44_MASK); - } - if (in_flags & mic_left_on) { - reg_val |= (WM8978_LIN2INPPGA_R44_MASK | WM8978_LIP2INPPGA_R44_MASK); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_INPUT_CTRL, reg_val)); - reg_val = 0; - if (in_flags & adc_on) { - reg_val |= (WM8978_ADCOSR128_R14_MASK) | (0 << 8) | (4 << 0); - } else { - reg_val = 0; - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_ADC_CONTROL, reg_val)); - - if (in_flags & adc_on) { - reg_val = (0 << 7); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER1, reg_val)); - reg_val = 0; - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER2, reg_val)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER3, reg_val)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER4, reg_val)); - } - reg_val = 0; - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_ALC_CONTROL1, reg_val)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_ALC_CONTROL2, reg_val)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_ALC_CONTROL3, reg_val)); - - /* Disable automatic gain control */ - reg_val = (3 << 1) | (7 << 0); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOISE_GATE, reg_val)); - - reg_val = 0; - if ((in_flags & mic_left_on) || (in_flags & mic_right_on)) { - reg_val |= (1 << 8); /* MIC gain = +20dB */ - } - if (in_flags & aux_on) { - reg_val |= (3 << 0); /* Aux = 3*/ - } - if (in_flags & line_on) { - reg_val |= (3 << 4); /* Line gain = 3 */ - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LADC_BOOST_CTRL, reg_val)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RADC_BOOST_CTRL, reg_val)); - - reg_val = 0xFF; - /* Select 0dB to cache the left channel first */ - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LEFT_ADC_VOL, reg_val)); - reg_val = 0x1FF; - /* Update left and right channels simultaneously */ - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RIGHT_ADC_VOL, reg_val)); - - reg_val = 0; - if (out_flags & spk_on) { - /* ROUT2 is inverted and used to drive the speaker */ - reg_val |= (1 << 4); - } - if (in_flags & aux_on) { - reg_val |= ((7 << 1) | (1 << 0)); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_BEEP_CONTROL, reg_val)); - - reg_val = 0; - if (in_flags & dac_on) { - reg_val |= ((1 << 6) | (1 << 5)); - } - if (out_flags & spk_on) { - /* SPK 1.5x gain, thermal protection enabled */ - reg_val |= ((1 << 2) | (1 << 1)); - } - if (out_flags & out_3_4_on) { - /* BOOT3 BOOT4 1.5x gain */ - reg_val |= ((1 << 4) | (1 << 3)); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_OUTPUT_CTRL, reg_val)); - - reg_val = 0; - if (in_flags & aux_on) { - reg_val |= ((7 << 6) | (1 << 5)); - } - if ((in_flags & line_on) || (in_flags & mic_left_on) || (in_flags & mic_right_on)) { - reg_val |= ((7 << 2) | (1 << 1)); - } - if (in_flags & dac_on) { - reg_val |= (1 << 0); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LEFT_MIXER_CTRL, reg_val)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RIGHT_MIXER_CTRL, reg_val)); - - reg_val = 0; - if (out_flags & out_3_4_on) { - reg_val |= (1 << 3); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_OUT3_MIXER_CTRL, reg_val)); - - reg_val = 0; - if (out_flags & out_3_4_on) { - reg_val |= ((1 << 4) | (1 << 1)); - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_OUT4_MIXER_CTRL, reg_val)); - - if (in_flags & dac_on) { - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LEFT_DAC_VOL, 0xFF)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RIGHT_DAC_VOL, 0x1FF)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_DAC_CTRL, 0)); - } else { - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_LEFT_DAC_VOL, 0)); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_RIGHT_DAC_VOL, 0x100)); - } - return stat; -} - -hpm_stat_t wm8978_notch_filter(wm8978_context_t *control, uint16_t nfa0, uint16_t nfa1) -{ - hpm_stat_t stat = status_success; - uint16_t reg_val; - reg_val = (1 << 7) | (nfa0 & 0x3F); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER1, reg_val)); - - reg_val = ((nfa0 >> 7) & 0x3F); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER2, reg_val)); - - reg_val = (nfa1 & 0x3F); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER3, reg_val)); - - reg_val = (1 << 8) | ((nfa1 >> 7) & 0x3F); - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_NOTCH_FILTER4, reg_val)); - return stat; -} - -hpm_stat_t wm8978_ctrl_gpio1(wm8978_context_t *control, bool value) -{ - hpm_stat_t stat = status_success; - uint16_t reg_val; - if (value == false) { - reg_val = 6; /* B2:0 = 110 */ - } else { - reg_val = 7; /* B2:0 = 111 */ - } - HPM_CHECK_RET(wm8978_write_reg(control, WM8978_GPIO_CTRL, reg_val)); - return stat; -} - -hpm_stat_t wm8978_write_reg(wm8978_context_t *control, uint8_t reg, uint16_t val) -{ - uint8_t buff[2]; - /* The first 7 bits (B15 to B9) are address bits that select which control register */ - /* is accessed. The remaining 9 bits (B8 to B0) are data bits */ - buff[0] = (reg << 1) | (uint8_t)((val >> 8U) & 0x0001U); - buff[1] = (uint8_t)(val & 0xFFU); - - /* record reg val */ - wm8978_reg_val[reg] = val; - return i2c_master_write(control->ptr, control->device_address, buff, 2U); -} - -hpm_stat_t wm8978_read_reg(wm8978_context_t *control, uint8_t reg, uint16_t *val) -{ - (void)control; - *val = wm8978_reg_val[reg]; - return status_success; -} - -hpm_stat_t wm8978_modify_reg(wm8978_context_t *control, uint8_t reg, uint16_t mask, uint16_t val) -{ - hpm_stat_t stat = status_success; - uint16_t reg_val; - /* Read the register value out */ - HPM_CHECK_RET(wm8978_read_reg(control, reg, ®_val)); - /* Modify the value */ - reg_val &= (uint16_t)~mask; - reg_val |= val; - /* Write the data to register */ - HPM_CHECK_RET(wm8978_write_reg(control, reg, reg_val)); - if (stat != status_success) { - return status_fail; - } - return stat; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.h deleted file mode 100644 index e9b474ba366..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_W8978_H_ -#define _HPM_W8978_H_ - -#include "hpm_i2c_drv.h" -#include "hpm_wm8978_regs.h" - -typedef enum wm8978_audio_interface { - wm8978_right_justified = 0, /* Right Justified */ - wm8978_left_justified, /* Left Justified */ - wm8978_philips_i2s, /* I2S format */ - wm8978_pcm_mode, /* DSP/PCM mode */ -} wm8978_audio_interface_t; - -typedef enum wm8978_word_length { - wm8978_16bits_length = 0, /* 16bits */ - wm8978_20bits_length, /* 20bits */ - wm8978_24bits_length, /* 24bits */ - wm8978_32bits_length, /* 32bits */ -} wm8978_word_length_t; - -typedef enum wm8978_out_channel { - wm8978_out1_channel = 0, /* R/LOUT1 channel. */ - wm8978_out2_channel = 1, /* R/LOUT2 channel. */ -} wm8978_out_channel_t; - -typedef enum input_channel_flag { - input_off = 0x00, /* no input */ - mic_left_on = 0x01, /* LIN,LIP pin，MIC left input */ - mic_right_on = 0x02, /* RIN,RIP pin，MIC right input */ - line_on = 0x04, /* L2,R2 pin input */ - aux_on = 0x08, /* AUXL,AUXR pins input */ - dac_on = 0x10, /* dac for i2s */ - adc_on = 0x20 /* input fed into the WM8978 internal ADC */ -} input_channel_flags_t; - -/* WM8978 音频输出通道控制选项, 可以选择多路 */ -typedef enum output_channel_flag { - output_off = 0x00, /* no output */ - earphone_left_on = 0x01, /* LOUT1 earphone */ - earphone_right_on = 0x02, /* ROUT1 earphone */ - spk_on = 0x04, /* LOUT2 and ROUT2 Inverting output mono*/ - out_3_4_on = 0x08, /* OUT3 and OUT4 output mono audio*/ -} output_channel_flag_t; - -typedef struct { - I2C_Type *ptr; /* I2C bus */ - uint8_t device_address; /* code device address */ -} wm8978_context_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - * @brief WM8979 initialize function. - * - * @param [in] control WM8979 control structure. - * @retval hpm_stat_t status_success if init without any error - */ -hpm_stat_t wm8979_init(wm8978_context_t *control); - -/** - * @brief WM8979 set out volume function. - * - * @param [in] control WM8979 control structure. - * @param [in] channel out channel - * @param [in] volume volume value - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_set_out_volume(wm8978_context_t *control, wm8978_out_channel_t channel, uint8_t volume); - -/** - * @brief WM8979 read out volume function. - * - * @param [in] control WM8979 control structure. - * @param [in] channel out channel - * @param [out] volume volume points value - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_get_out_volume(wm8978_context_t *control, wm8978_out_channel_t channel, uint8_t *volume); - -/** - * @brief WM8979 set out mute. - * - * @param [in] control WM8979 control structure. - * @param [in] channel out channel - * @param [in] mute if mute is set to true - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_set_out_mute(wm8978_context_t *control, wm8978_out_channel_t channel, bool mute); - -/** - * @brief WM8979 set gain of mic. - * - * @param [in] control WM8979 control structure. - * @param [in] gain gain value, range: 0 ~ 63 - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_set_mic_gain(wm8978_context_t *control, uint8_t gain); - -/** - * @brief WM8979 set the gain of the Line input channel - * - * @param [in] control WM8979 control structure. - * @param [in] gain volume value, range: 0 ~ 7 - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_set_line_gain(wm8978_context_t *control, uint8_t gain); - -/** - * @brief WM8979 enter power down mode - * - * @param [in] control WM8979 control structure. - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_power_down(wm8978_context_t *control); - -/** - * @brief Control the GPIO1 pin of WM8978 to output high or low - * - * @param [in] control WM8979 control structure. - * @param [in] value output high or low. if true, it's high - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_ctrl_gpio1(wm8978_context_t *control, bool value); - -/** - * @brief Configuring the audio interface of WM8978 - * - * @param [in] control WM8979 control structure. - * @param [in] standard wm8978_audio_interface_t structure - * @param [in] word_len wm8978_word_length_t structure - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_cfg_audio_interface(wm8978_context_t *control, - wm8978_audio_interface_t standard, - wm8978_word_length_t word_len); - -/** - * @brief Configure wm8978 audio channel - * - * @param [in] control WM8979 control structure. - * @param [in] in_flags input_channel_flags_t structure - * @param [in] out_flags output_channel_flag_t structure - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_cfg_audio_channel(wm8978_context_t *control, - input_channel_flags_t in_flags, - output_channel_flag_t out_flags); - -/** - * @brief setting the Notch Filter for WM8978 - * - * @note used to suppress positive feedback of microphone sound waves to avoid howling - * @param [in] control WM8979 control structure. - * @param [in] nfa0 Notch Filter0 value - * @param [in] nfa1 Notch Filter1 value - * @retval hpm_stat_t status_success if set without any error - */ -hpm_stat_t wm8978_notch_filter(wm8978_context_t *control, uint16_t nfa0, uint16_t nfa1); - -/** - * @brief Write register to WM8978 using I2C. - * - * @param [in] control WM8978 control structure. - * @retval hpm_stat_t status_success if reset without any error - */ -hpm_stat_t wm8978_reset(wm8978_context_t *control); - -/** - * @brief Write register to WM8978 using I2C. - * - * @param [in] control WM8978 control structure. - * @param [in] reg The register address in WM8978. - * @param [in] val Value needs to write into the register. - * @retval hpm_stat_t status_success if write reg without any error - */ -hpm_stat_t wm8978_write_reg(wm8978_context_t *control, uint8_t reg, uint16_t val); - -/** - * @brief Read register from WM8978 using I2C. - * @param [in] reg The register address in WM8978. - * @param [in] reg The register address in WM8978. - * @param [out] val Value point read to. - * @retval hpm_stat_t status_success if read reg without any error - */ -hpm_stat_t wm8978_read_reg(wm8978_context_t *control, uint8_t reg, uint16_t *val); - -/** - * @brief Modify some bits in the register using I2C. - * @param [in] control WM8978 control structure. - * @param [in] reg The register address in WM8978. - * @param [in] mask The mask code for the bits want to write. The bit you want to write should be 0. - * @param [in] val Value needs to write into the register. - * @retval hpm_stat_t status_success if modify reg without any error - */ -hpm_stat_t wm8978_modify_reg(wm8978_context_t *control, uint8_t reg, uint16_t mask, uint16_t val); - -#ifdef __cplusplus -} -#endif - -/** - * @} - * - */ - -#endif /* HPM_WM8978_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978_regs.h deleted file mode 100644 index 5635c4bfb4b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978_regs.h +++ /dev/null @@ -1,549 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_WM8978_REG_H_ -#define _HPM_WM8978_REG_H_ - -/* Define the register address of WM8978 */ -#define WM8978_RESET 0x00U /* software reset */ -#define WM8978_POWER_MANAGET_1 0x01U /* power managet 1 */ -#define WM8978_POWER_MANAGET_2 0x02U /* power managet 2 */ -#define WM8978_POWER_MANAGET_3 0x03U /* power managet 3 */ -#define WM8978_AUDIO_INTERFACE 0x04U /* audio interface */ -#define WM8978_CLOCK_GEN_CTRL 0x06U /* clock gen ctrl */ -#define WM8978_GPIO_CTRL 0x08U /* GPIO ctrl */ -#define WM8978_DAC_CTRL 0x0AU /* DAC ctrl */ -#define WM8978_LEFT_DAC_VOL 0x0BU /* Left DAC digital vol */ -#define WM8978_RIGHT_DAC_VOL 0x0CU /* Right DAC digital vol */ -#define WM8978_ADC_CONTROL 0x0EU /* ADC control */ -#define WM8978_LEFT_ADC_VOL 0x0FU /* Left ADC digital vol */ -#define WM8978_RIGHT_ADC_VOL 0x10U /* Right ADC digital vol */ -#define WM8978_NOTCH_FILTER1 0x1BU /* notch filter1 */ -#define WM8978_NOTCH_FILTER2 0x1CU /* notch filter2 */ -#define WM8978_NOTCH_FILTER3 0x1DU /* notch filter3 */ -#define WM8978_NOTCH_FILTER4 0x1EU /* notch filter4 */ -#define WM8978_ALC_CONTROL1 0x20U /* ALC control1 */ -#define WM8978_ALC_CONTROL2 0x21U /* ALC control2 */ -#define WM8978_ALC_CONTROL3 0x22U /* ALC control3 */ -#define WM8978_NOISE_GATE 0x23U /* noise Gate */ -#define WM8978_BEEP_CONTROL 0x2BU /* beep control */ -#define WM8978_INPUT_CTRL 0x2CU /* input ctrl */ -#define WM8978_LOUT1_VOLUME_CTRL 0x34U /* LOUT1 (HP)volume ctrl */ -#define WM8978_ROUT1_VOLUME_CTRL 0x35U /* ROUT1 (HP)volume ctrl */ -#define WM8978_LOUT2_VOLUME_CTRL 0x36U /* LOUT2 (SPK)volume ctrl */ -#define WM8978_ROUT2_VOLUME_CTRL 0x37U /* ROUT2 (SPK)volume ctrl */ -#define WM8978_LINP_PGA_GAIM_CTRL 0x2DU /* Left INP PGA gain ctrl */ -#define WM8978_RINP_PGA_GAIM_CTRL 0x2EU /* Right INP PGA gain ctrl */ -#define WM8978_LADC_BOOST_CTRL 0x2FU /* Left INP PGA gain ctrl */ -#define WM8978_RADC_BOOST_CTRL 0x30U /* Right INP PGA gain ctrl */ -#define WM8978_OUTPUT_CTRL 0x31U /* Output ctrl */ -#define WM8978_LEFT_MIXER_CTRL 0x32U /* left mixer ctrl */ -#define WM8978_RIGHT_MIXER_CTRL 0x33U /* right mixer ctrl */ -#define WM8978_OUT3_MIXER_CTRL 0x38U /* out3 mixer ctrl */ -#define WM8978_OUT4_MIXER_CTRL 0x39U /* out4 mixer ctrl */ - -/* - * BUFDCOPEN (RW) - * Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration - */ -#define WM8978_BUFDCOPEN_R1_MASK (0x100U) -#define WM8978_BUFDCOPEN_R1_SHIFT (8U) -#define WM8978_BUFDCOPEN_R1_SET(x) (((uint16_t)(x) << WM8978_BUFDCOPEN_R1_SHIFT) & WM8978_BUFDCOPEN_R1_MASK) -#define WM8978_BUFDCOPEN_R1_GET(x) (((uint16_t)(x) & WM8978_BUFDCOPEN_R1_MASK) >> WM8978_BUFDCOPEN_R1_SHIFT) - -/* - * OUT4MIXEN (RW) - * OUT4 mixer enable - */ -#define WM8978_OUT4MIXEN_R1_MASK (0x80U) -#define WM8978_OUT4MIXEN_R1_SHIFT (7U) -#define WM8978_OUT4MIXEN_R1_SET(x) (((uint16_t)(x) << WM8978_OUT4MIXEN_R1_SHIFT) & WM8978_OUT4MIXEN_R1_MASK) -#define WM8978_OUT4MIXEN_R1_GET(x) (((uint16_t)(x) & WM8978_OUT4MIXEN_R1_MASK) >> WM8978_OUT4MIXEN_R1_SHIFT) - -/* - * OUT3MIXEN (RW) - * OUT3 mixer enable - */ -#define WM8978_OUT3MIXEN_R1_MASK (0x40U) -#define WM8978_OUT3MIXEN_R1_SHIFT (6U) -#define WM8978_OUT3MIXEN_R1_SET(x) (((uint16_t)(x) << WM8978_OUT3MIXEN_R1_SHIFT) & WM8978_OUT3MIXEN_R1_MASK) -#define WM8978_OUT3MIXEN_R1_GET(x) (((uint16_t)(x) & WM8978_OUT3MIXEN_R1_MASK) >> WM8978_OUT3MIXEN_R1_SHIFT) - -/* - * PLLEN (RW) - * PLL enable - */ -#define WM8978_PLLEN_R1_MASK (0x20U) -#define WM8978_PLLEN_R1_SHIFT (5U) -#define WM8978_PLLEN_R1_SET(x) (((uint16_t)(x) << WM8978_PLLEN_R1_SHIFT) & WM8978_PLLEN_R1_MASK) -#define WM8978_PLLEN_R1_GET(x) (((uint16_t)(x) & WM8978_PLLEN_R1_MASK) >> WM8978_PLLEN_R1_SHIFT) - -/* - * MICBEN (RW) - * Microphone Bias Enable - */ -#define WM8978_MICBEN_R1_MASK (0x10U) -#define WM8978_MICBEN_R1_SHIFT (4U) -#define WM8978_MICBEN_R1_SET(x) (((uint16_t)(x) << WM8978_MICBEN_R1_SHIFT) & WM8978_MICBEN_R1_MASK) -#define WM8978_MICBEN_R1_GET(x) (((uint16_t)(x) & WM8978_MICBEN_R1_MASK) >> WM8978_MICBEN_R1_SHIFT) - -/* - * BIASEN (RW) - * Analogue amplifier bias control - */ -#define WM8978_BIASEN_R1_MASK (0x08U) -#define WM8978_BIASEN_R1_SHIFT (3U) -#define WM8978_BIASEN_R1_SET(x) (((uint16_t)(x) << WM8978_BIASEN_R1_SHIFT) & WM8978_BIASEN_R1_MASK) -#define WM8978_BIASEN_R1_GET(x) (((uint16_t)(x) & WM8978_BIASEN_R1_MASK) >> WM8978_BIASEN_R1_SHIFT) - - -/* - * BUFIOEN (RW) - * Unused input/output tie off buffer enable - */ -#define WM8978_BUFIOEN_R1_MASK (0x04U) -#define WM8978_BUFIOEN_R1_SHIFT (2U) -#define WM8978_BUFIOEN_R1_SET(x) (((uint16_t)(x) << WM8978_BUFIOEN_R1_SHIFT) & WM8978_BUFIOEN_R1_MASK) -#define WM8978_BUFIOEN_R1_GET(x) (((uint16_t)(x) & WM8978_BUFIOEN_R1_MASK) >> WM8978_BUFIOEN_R1_SHIFT) - -/* - * VMIDSEL (RW) - * Reference string impedance to VMID pin - */ -#define WM8978_VMIDSEL_R1_MASK (0x03U) -#define WM8978_VMIDSEL_R1_SHIFT (0U) -#define WM8978_VMIDSEL_R1_SET(x) (((uint16_t)(x) << WM8978_VMIDSEL_R1_SHIFT) & WM8978_VMIDSEL_R1_MASK) -#define WM8978_VMIDSEL_R1_GET(x) (((uint16_t)(x) & WM8978_VMIDSEL_R1_MASK) >> WM8978_VMIDSEL_R1_SHIFT) - -/* - * ROUT1EN (RW) - * ROUT1 output enable - */ -#define WM8978_ROUT1EN_R2_MASK (0x100U) -#define WM8978_ROUT1EN_R2_SHIFT (8U) -#define WM8978_ROUT1EN_R2_SET(x) (((uint16_t)(x) << WM8978_ROUT1EN_R2_SHIFT) & WM8978_ROUT1EN_R2_MASK) -#define WM8978_ROUT1EN_R2_GET(x) (((uint16_t)(x) & WM8978_ROUT1EN_R2_MASK) >> WM8978_ROUT1EN_R2_SHIFT) - -/* - * LOUT1EN (RW) - * LOUT1 output enable - */ -#define WM8978_LOUT1EN_R2_MASK (0x80U) -#define WM8978_LOUT1EN_R2_SHIFT (7U) -#define WM8978_LOUT1EN_R2_SET(x) (((uint16_t)(x) << WM8978_LOUT1EN_R2_SHIFT) & WM8978_LOUT1EN_R2_MASK) -#define WM8978_LOUT1EN_R2_GET(x) (((uint16_t)(x) & WM8978_LOUT1EN_R2_MASK) >> WM8978_LOUT1EN_R2_SHIFT) - -/* - * SLEEP (RW) - * residual current reduced in device standby mode if 1 - */ -#define WM8978_SLEEP_R2_MASK (0x40U) -#define WM8978_SLEEP_R2_SHIFT (6U) -#define WM8978_SLEEP_R2_SET(x) (((uint16_t)(x) << WM8978_SLEEP_R2_SHIFT) & WM8978_SLEEP_R2_MASK) -#define WM8978_SLEEP_R2_GET(x) (((uint16_t)(x) & WM8978_SLEEP_R2_MASK) >> WM8978_SLEEP_R2_SHIFT) - -/* - * BOOSTENR (RW) - * Right channel Input BOOST enable - */ -#define WM8978_BOOSTENR_R2_MASK (0x20U) -#define WM8978_BOOSTENR_R2_SHIFT (5U) -#define WM8978_BOOSTENR_R2_SET(x) (((uint16_t)(x) << WM8978_BOOSTENR_R2_SHIFT) & WM8978_BOOSTENR_R2_MASK) -#define WM8978_BOOSTENR_R2_GET(x) (((uint16_t)(x) & WM8978_BOOSTENR_R2_MASK) >> WM8978_BOOSTENR_R2_SHIFT) - -/* - * BOOSTENL (RW) - * Left channel Input BOOST enable - */ -#define WM8978_BOOSTENL_R2_MASK (0x10U) -#define WM8978_BOOSTENL_R2_SHIFT (4U) -#define WM8978_BOOSTENL_R2_SET(x) (((uint16_t)(x) << WM8978_BOOSTENL_R2_SHIFT) & WM8978_BOOSTENL_R2_MASK) -#define WM8978_BOOSTENL_R2_GET(x) (((uint16_t)(x) & WM8978_BOOSTENL_R2_MASK) >> WM8978_BOOSTENL_R2_SHIFT) - -/* - * INPPGAENR (RW) - * Right channel input PGA enable - */ -#define WM8978_INPPGAENR_R2_MASK (0x08U) -#define WM8978_INPPGAENR_R2_SHIFT (3U) -#define WM8978_INPPGAENR_R2_SET(x) (((uint16_t)(x) << WM8978_INPPGAENR_R2_SHIFT) & WM8978_INPPGAENR_R2_MASK) -#define WM8978_INPPGAENR_R2_GET(x) (((uint16_t)(x) & WM8978_INPPGAENR_R2_MASK) >> WM8978_INPPGAENR_R2_SHIFT) - - -/* - * INPPGAENL (RW) - * Left channel input PGA enable - */ -#define WM8978_INPPGAENL_R2_MASK (0x04U) -#define WM8978_INPPGAENL_R2_SHIFT (2U) -#define WM8978_INPPGAENL_R2_SET(x) (((uint16_t)(x) << WM8978_INPPGAENL_R2_SHIFT) & WM8978_INPPGAENL_R2_MASK) -#define WM8978_INPPGAENL_R2_GET(x) (((uint16_t)(x) & WM8978_INPPGAENL_R2_MASK) >> WM8978_INPPGAENL_R2_SHIFT) - -/* - * ADCENR (RW) - * Enable ADC right channel - */ -#define WM8978_ADCENR_R2_MASK (0x02U) -#define WM8978_ADCENR_R2_SHIFT (1U) -#define WM8978_ADCENR_R2_SET(x) (((uint16_t)(x) << WM8978_ADCENR_R2_SHIFT) & WM8978_ADCENR_R2_MASK) -#define WM8978_ADCENR_R2_GET(x) (((uint16_t)(x) & WM8978_ADCENR_R2_MASK) >> WM8978_ADCENR_R2_SHIFT) - -/* - * ADCENL (RW) - * Enable ADC left channel - */ -#define WM8978_ADCENL_R2_MASK (0x01U) -#define WM8978_ADCENL_R2_SHIFT (0U) -#define WM8978_ADCENL_R2_SET(x) (((uint16_t)(x) << WM8978_ADCENL_R2_SHIFT) & WM8978_ADCENL_R2_MASK) -#define WM8978_ADCENL_R2_GET(x) (((uint16_t)(x) & WM8978_ADCENL_R2_MASK) >> WM8978_ADCENL_R2_SHIFT) - -/* - * MBVSEL (RW) - * Microphone Bias Voltage Control - */ -#define WM8978_OUT4EN_R3_MASK (0x100U) -#define WM8978_OUT4EN_R3_SHIFT (8U) -#define WM8978_OUT4EN_R3_SET(x) (((uint16_t)(x) << WM8978_OUT4EN_R3_SHIFT) & WM8978_OUT4EN_R3_MASK) -#define WM8978_OUT4EN_R3_GET(x) (((uint16_t)(x) & WM8978_OUT4EN_R3_MASK) >> WM8978_OUT4EN_R3_SHIFT) - -/* - * OUT3EN (RW) - * OUT3 enable - */ -#define WM8978_OUT3EN_R3_MASK (0x80U) -#define WM8978_OUT3EN_R3_SHIFT (7U) -#define WM8978_OUT3EN_R3_SET(x) (((uint16_t)(x) << WM8978_OUT3EN_R3_SHIFT) & WM8978_OUT3EN_R3_MASK) -#define WM8978_OUT3EN_R3_GET(x) (((uint16_t)(x) & WM8978_OUT3EN_R3_MASK) >> WM8978_OUT3EN_R3_SHIFT) - -/* - * LOUT2EN (RW) - * LOUT2 enable - */ -#define WM8978_LOUT2EN_R3_MASK (0x40U) -#define WM8978_LOUT2EN_R3_SHIFT (6U) -#define WM8978_LOUT2EN_R3_SET(x) (((uint16_t)(x) << WM8978_LOUT2EN_R3_SHIFT) & WM8978_LOUT2EN_R3_MASK) -#define WM8978_LOUT2EN_R3_GET(x) (((uint16_t)(x) & WM8978_LOUT2EN_R3_MASK) >> WM8978_LOUT2EN_R3_SHIFT) - -/* - * ROUT2EN (RW) - * ROUT2 enable - */ -#define WM8978_ROUT2EN_R3_MASK (0x20U) -#define WM8978_ROUT2EN_R3_SHIFT (5U) -#define WM8978_ROUT2EN_R3_SET(x) (((uint16_t)(x) << WM8978_ROUT2EN_R3_SHIFT) & WM8978_ROUT2EN_R3_MASK) -#define WM8978_ROUT2EN_R3_GET(x) (((uint16_t)(x) & WM8978_ROUT2EN_R3_MASK) >> WM8978_ROUT2EN_R3_SHIFT) - -/* - * RMIXEN (RW) - * Right output channel mixer enable - */ -#define WM8978_RMIXEN_R3_MASK (0x08U) -#define WM8978_RMIXEN_R3_SHIFT (3U) -#define WM8978_RMIXEN_R3_SET(x) (((uint16_t)(x) << WM8978_RMIXEN_R3_SHIFT) & WM8978_RMIXEN_R3_MASK) -#define WM8978_RMIXEN_R3_GET(x) (((uint16_t)(x) & WM8978_RMIXEN_R3_MASK) >> WM8978_RMIXEN_R3_SHIFT) - -/* - * LMIXEN (RW) - * Left output channel mixer enable - */ -#define WM8978_LMIXEN_R3_MASK (0x04U) -#define WM8978_LMIXEN_R3_SHIFT (2U) -#define WM8978_LMIXEN_R3_SET(x) (((uint16_t)(x) << WM8978_LMIXEN_R3_SHIFT) & WM8978_LMIXEN_R3_MASK) -#define WM8978_LMIXEN_R3_GET(x) (((uint16_t)(x) & WM8978_LMIXEN_R3_MASK) >> WM8978_LMIXEN_R3_SHIFT) - -/* - * DACENR (RW) - * Right channel DAC enable - */ -#define WM8978_DACENR_R3_MASK (0x02U) -#define WM8978_DACENR_R3_SHIFT (1U) -#define WM8978_DACENR_R3_SET(x) (((uint16_t)(x) << WM8978_DACENR_R3_SHIFT) & WM8978_DACENR_R3_MASK) -#define WM8978_DACENR_R3_GET(x) (((uint16_t)(x) & WM8978_DACENR_R3_MASK) >> WM8978_DACENR_R3_SHIFT) - -/* - * DACENL (RW) - * Left channel DAC enable - */ -#define WM8978_DACENL_R3_MASK (0x01U) -#define WM8978_DACENL_R3_SHIFT (0U) -#define WM8978_DACENL_R3_SET(x) (((uint16_t)(x) << WM8978_DACENL_R3_SHIFT) & WM8978_DACENL_R3_MASK) -#define WM8978_DACENL_R3_GET(x) (((uint16_t)(x) & WM8978_DACENL_R3_MASK) >> WM8978_DACENL_R3_SHIFT) - -/* - * HPFEN (RW) - * High Pass Filter Enable - */ -#define WM8978_HPFEN_R14_MASK (0x100U) -#define WM8978_HPFEN_R14_SHIFT (8U) -#define WM8978_HPFEN_R14_SET(x) (((uint16_t)(x) << WM8978_HPFEN_R14_SHIFT) & WM8978_HPFEN_R14_MASK) -#define WM8978_HPFEN_R14_GET(x) (((uint16_t)(x) & WM8978_HPFEN_R14_MASK) >> WM8978_HPFEN_R14_SHIFT) - -/* - * ADCOSR128 (RW) - * ADC oversample rate select - */ -#define WM8978_ADCOSR128_R14_MASK (0x08U) -#define WM8978_ADCOSR128_R14_SHIFT (3U) -#define WM8978_ADCOSR128_R14_SET(x) (((uint16_t)(x) << WM8978_ADCOSR128_R14_SHIFT) & WM8978_ADCOSR128_R14_MASK) -#define WM8978_ADCOSR128_R14_GET(x) (((uint16_t)(x) & WM8978_ADCOSR128_R14_MASK) >> WM8978_ADCOSR128_R14_SHIFT) - -/* - * ADCRPOL (RW) - * ADC right channel polarity adjust - */ -#define WM8978_ADCRPOL_R14_MASK (0x02U) -#define WM8978_ADCRPOL_R14_SHIFT (1U) -#define WM8978_ADCRPOL_R14_SET(x) (((uint16_t)(x) << WM8978_ADCRPOL_R14_SHIFT) & WM8978_ADCRPOL_R14_MASK) -#define WM8978_ADCRPOL_R14_GET(x) (((uint16_t)(x) & WM8978_ADCRPOL_R14_MASK) >> WM8978_ADCRPOL_R14_SHIFT) - -/* - * ADCLPOL (RW) - * ADC left channel polarity adjust - */ -#define WM8978_ADCLPOL_R14_MASK (0x01U) -#define WM8978_ADCLPOL_R14_SHIFT (0U) -#define WM8978_ADCLPOL_R14_SET(x) (((uint16_t)(x) << WM8978_ADCLPOL_R14_SHIFT) & WM8978_ADCLPOL_R14_MASK) -#define WM8978_ADCLPOL_R14_GET(x) (((uint16_t)(x) & WM8978_ADCLPOL_R14_MASK) >> WM8978_ADCLPOL_R14_SHIFT) - -/* - * MBVSEL (RW) - * Microphone Bias Voltage Control - */ -#define WM8978_MBVSEL_R44_MASK (0x100U) -#define WM8978_MBVSEL_R44_SHIFT (8U) -#define WM8978_MBVSEL_R44_SET(x) (((uint16_t)(x) << WM8978_MBVSEL_R44_SHIFT) & WM8978_MBVSEL_R44_MASK) -#define WM8978_MBVSEL_R44_GET(x) (((uint16_t)(x) & WM8978_MBVSEL_R44_MASK) >> WM8978_MBVSEL_R44_SHIFT) - -/* - * R2_2INPPGA (RW) - * Connect R2 pin to right channel input PGA positive terminal - */ -#define WM8978_R2_2INPPGA_R44_MASK (0x40U) -#define WM8978_R2_2INPPGA_R44_SHIFT (6U) -#define WM8978_R2_2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_R2_2INPPGA_R44_SHIFT) & WM8978_R2_2INPPGA_R44_MASK) -#define WM8978_R2_2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_R2_2INPPGA_R44_MASK) >> WM8978_R2_2INPPGA_R44_SHIFT) - -/* - * RIN2INPPGA (RW) - * Connect RIN pin to right channel input PGA negative terminaL - */ -#define WM8978_RIN2INPPGA_R44_MASK (0x20U) -#define WM8978_RIN2INPPGA_R44_SHIFT (5U) -#define WM8978_RIN2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_RIN2INPPGA_R44_SHIFT) & WM8978_RIN2INPPGA_R44_MASK) -#define WM8978_RIN2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_RIN2INPPGA_R44_MASK) >> WM8978_RIN2INPPGA_R44_SHIFT) - -/* - * RIP2INPPGA (RW) - * Connect RIP pin to right channel input PGA amplifier positive terminal - */ -#define WM8978_RIP2INPPGA_R44_MASK (0x10U) -#define WM8978_RIP2INPPGA_R44_SHIFT (4U) -#define WM8978_RIP2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_RIP2INPPGA_R44_SHIFT) & WM8978_RIP2INPPGA_R44_MASK) -#define WM8978_RIP2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_RIP2INPPGA_R44_MASK) >> WM8978_RIP2INPPGA_R44_SHIFT) - -/* - * L2_2INPPGA (RW) - * Connect L2 pin to left channel input PGA positive terminal - */ -#define WM8978_L2_2INPPGA_R44_MASK (0x04U) -#define WM8978_L2_2INPPGA_R44_SHIFT (2U) -#define WM8978_L2_2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_L2_2INPPGA_R44_SHIFT) & WM8978_L2_2INPPGA_R44_MASK) -#define WM8978_L2_2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_L2_2INPPGA_R44_MASK) >> WM8978_L2_2INPPGA_R44_SHIFT) - -/* - * LIN2INPPGA (RW) - * Connect LIN pin to left channel input PGA negative terminal - */ -#define WM8978_LIN2INPPGA_R44_MASK (0x02U) -#define WM8978_LIN2INPPGA_R44_SHIFT (1U) -#define WM8978_LIN2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_LIN2INPPGA_R44_SHIFT) & WM8978_LIN2INPPGA_R44_MASK) -#define WM8978_LIN2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_LIN2INPPGA_R44_MASK) >> WM8978_LIN2INPPGA_R44_SHIFT) - -/* - * DACENL (RW) - * Connect LIP pin to left channel input PGA amplifier positive terminal - */ -#define WM8978_LIP2INPPGA_R44_MASK (0x01U) -#define WM8978_LIP2INPPGA_R44_SHIFT (0U) -#define WM8978_LIP2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_LIP2INPPGA_R44_SHIFT) & WM8978_LIP2INPPGA_R44_MASK) -#define WM8978_LIP2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_LIP2INPPGA_R44_MASK) >> WM8978_LIP2INPPGA_R44_SHIFT) - -/* - * BCP (RW) - * BCLK polarity - * for 0x04 reg - */ -#define WM8978_BCP_MASK (0x100U) -#define WM8978_BCP_SHIFT (8U) -#define WM8978_BCP_SET(x) (((uint16_t)(x) << WM8978_BCP_SHIFT) & WM8978_BCP_MASK) -#define WM8978_BCP_GET(x) (((uint16_t)(x) & WM8978_BCP_MASK) >> WM8978_BCP_SHIFT) - -/* - * LRP (RW) - * LRC clock polarity - * for 0x04 reg - */ -#define WM8978_LRP_MASK (0x80U) -#define WM8978_LRP_SHIFT (7U) -#define WM8978_LRP_SET(x) (((uint16_t)(x) << WM8978_LRP_SHIFT) & WM8978_LRP_MASK) -#define WM8978_LRP_GET(x) (((uint16_t)(x) & WM8978_LRP_MASK) >> WM8978_LRP_SHIFT) - -/* - * WL (RW) - * word length - * for 0x04 reg - */ -#define WM8978_WL_MASK (0x60U) -#define WM8978_WL_SHIFT (5U) -#define WM8978_WL_SET(x) (((uint16_t)(x) << WM8978_WL_SHIFT) & WM8978_WL_MASK) -#define WM8978_WL_GET(x) (((uint16_t)(x) & WM8978_WL_MASK) >> WM8978_WL_SHIFT) - -/* - * FMT (RW) - * addio interface data format select - * for 0x04 reg - */ -#define WM8978_FMT_MASK (0x18U) -#define WM8978_FMT_SHIFT (3U) -#define WM8978_FMT_SET(x) (((uint16_t)(x) << WM8978_FMT_SHIFT) & WM8978_FMT_MASK) -#define WM8978_FMT_GET(x) (((uint16_t)(x) & WM8978_FMT_MASK) >> WM8978_FMT_SHIFT) - -/* - * DACLRSWAP (RW) - * Controls whether DAC data appears in 'right'orleft’ phases of LRC clock - * for 0x04 reg - */ -#define WM8978_DACLRSWAP_MASK (0x04U) -#define WM8978_DACLRSWAP_SHIFT (2U) -#define WM8978_DACLRSWAP_SET(x) (((uint16_t)(x) << WM8978_DACLRSWAP_SHIFT) & WM8978_DACLRSWAP_MASK) -#define WM8978_DACLRSWAP_GET(x) (((uint16_t)(x) & WM8978_DACLRSWAP_MASK) >> WM8978_DACLRSWAP_SHIFT) - -/* - * ADCLRSWAP (RW) - * Controls whether ADC data appears in 'right' orleft’ phases of LRC clock - * for 0x04 reg - */ -#define WM8978_ADCLRSWAP_MASK (0x02U) -#define WM8978_ADCLRSWAP_SHIFT (1U) -#define WM8978_ADCLRSWAP_SET(x) (((uint16_t)(x) << WM8978_ADCLRSWAP_SHIFT) & WM8978_ADCLRSWAP_MASK) -#define WM8978_ADCLRSWAP_GET(x) (((uint16_t)(x) & WM8978_ADCLRSWAP_MASK) >> WM8978_ADCLRSWAP_SHIFT) - -/* - * MONO (RW) - * Selects between stereo and mono deviceoperation - * for 0x04 reg - */ -#define WM8978_MONO_MASK (0x01U) -#define WM8978_MONO_SHIFT (0U) -#define WM8978_MONO_SET(x) (((uint16_t)(x) << WM8978_MONO_SHIFT) & WM8978_MONO_MASK) -#define WM8978_MONO_GET(x) (((uint16_t)(x) & WM8978_MONO_MASK) >> WM8978_MONO_SHIFT) - -/* - * ROUTVOL (RW) - * - * OUT Volume - * 000000 = -57dB - * 111001 = 0dB - * 111111 = 6dB - * for 0x34/0x35/0x36/0x37 regs - */ -#define WM8978_OUT_VOLUME_MASK (0x7FU) -#define WM8978_OUT_VOLUME_SHIFT (0U) -#define WM8978_OUT_VOLUME_SET(x) (((uint16_t)(x) << WM8978_OUT_VOLUME_SHIFT) & WM8978_OUT_VOLUME_MASK) -#define WM8978_OUT_VOLUME_GET(x) (((uint16_t)(x) & WM8978_OUT_VOLUME_MASK) >> WM8978_OUT_VOLUME_SHIFT) - -/* - * OUT_SPKVU (RW) - * LOUT1/2 and ROUT1/2 volumes do not update untila 1 is written to SPKkVU - * for 0x34/0x35/0x36/0x37 regs - */ -#define WM8978_OUT_SPKVU_MASK (0x100U) -#define WM8978_OUT_SPKVU_SHIFT (8U) -#define WM8978_OUT_SPKVU_SET(x) (((uint16_t)(x) << WM8978_OUT_SPKVU_SHIFT) & WM8978_OUT_SPKVU_MASK) -#define WM8978_OUT_SPKVU_GET(x) (((uint16_t)(x) & WM8978_OUT_SPKVU_MASK) >> WM8978_OUT_SPKVU_SHIFT) - -/* - * OUT_MUTE (RW) - * LOUT1/2 and ROUT1/2 headphone output mute - * for 0x34/0x35/0x36/0x37 regs - */ -#define WM8978_OUT_MUTE_MASK (0x40U) -#define WM8978_OUT_MUTE_SHIFT (6U) -#define WM8978_OUT_MUTE_SET(x) (((uint16_t)(x) << WM8978_OUT_MUTE_SHIFT) & WM8978_OUT_MUTE_MASK) -#define WM8978_OUT_MUTE_GET(x) (((uint16_t)(x) & WM8978_OUT_MUTE_MASK) >> WM8978_OUT_MUTE_SHIFT) - -/* - * INPGA_UPDATE (RW) - * inpga update - * for 0x45/0x46 regs - */ -#define WM8978_INPGA_UPDATE_MASK (0x100U) -#define WM8978_INPGA_UPDATE_SHIFT (8U) -#define WM8978_INPGA_UPDATE_SET(x) (((uint16_t)(x) << WM8978_INPGA_UPDATE_SHIFT) & WM8978_INPGA_UPDATE_MASK) -#define WM8978_INPGA_UPDATE_GET(x) (((uint16_t)(x) & WM8978_INPGA_UPDATE_MASK) >> WM8978_INPGA_UPDATE_SHIFT) - -/* - * NPPGAZCR/L (RW) - * Left/Right channel input PGA zero cross enable - * for 0x45/0x46 regs - */ -#define WM8978_NP_PGA_ZC_MASK (0x80U) -#define WM8978_NP_PGA_ZC_SHIFT (7U) -#define WM8978_NP_PGA_ZC_SET(x) (((uint16_t)(x) << WM8978_NP_PGA_ZC_SHIFT) & WM8978_NP_PGA_ZC_MASK) -#define WM8978_NP_PGA_ZC_GET(x) (((uint16_t)(x) & WM8978_NP_PGA_ZC_MASK) >> WM8978_NP_PGA_ZC_SHIFT) - -/* - * NPPGA_MUTEL (RW) - * Mute control for left/right channel input PGA - * for 0x45/0x46 regs - */ -#define WM8978_INPPGA_MUTEL_MASK (0x40U) -#define WM8978_INPPGA_MUTEL_SHIFT (6U) -#define WM8978_INPPGA_MUTEL_SET(x) (((uint16_t)(x) << WM8978_INPPGA_MUTEL_SHIFT) & WM8978_INPPGA_MUTEL_MASK) -#define WM8978_INPPGA_MUTEL_GET(x) (((uint16_t)(x) & WM8978_INPPGA_MUTEL_MASK) >> WM8978_INPPGA_MUTEL_SHIFT) - -/* - * INPPGA_VOL (RW) - * Left/Right channel input PGA volume - * for 0x2d/0x2e regs - */ -#define WM8978_INPPGA_VOL_MASK (0x3FU) -#define WM8978_INPPGA_VOL_SHIFT (0U) -#define WM8978_INPPGA_VOL_SET(x) (((uint16_t)(x) << WM8978_INPPGA_VOL_SHIFT) & WM8978_INPPGA_VOL_MASK) -#define WM8978_INPPGA_VOL_GET(x) (((uint16_t)(x) & WM8978_INPPGA_VOL_MASK) >> WM8978_INPPGA_VOL_SHIFT) - -/* - * PGABOOST (RW) - * Boost enable for left/right channel input PGA - * for 0x2f/0x30 regs - */ -#define WM8978_PGABOOST_MASK (0x100U) -#define WM8978_PGABOOST_SHIFT (8U) -#define WM8978_PGABOOST_SET(x) (((uint16_t)(x) << WM8978_PGABOOST_SHIFT) & WM8978_PGABOOST_MASK) -#define WM8978_PGABOOST_GET(x) (((uint16_t)(x) & WM8978_PGABOOST_MASK) >> WM8978_PGABOOST_SHIFT) - -/* - * LR2_2BOOSTVOL (RW) - * Controls the L2 pin to the left/right channel input - * for 0x2f/0x30 regs - */ -#define WM8978_2_2_BOOSTVOL_MASK (0x70U) -#define WM8978_2_2_BOOSTVOL_SHIFT (4U) -#define WM8978_2_2_BOOSTVOL_SET(x) (((uint16_t)(x) << WM8978_2_2_BOOSTVOL_SHIFT) & WM8978_2_2_BOOSTVOL_MASK) -#define WM8978_2_2_BOOSTVOL_GET(x) (((uint16_t)(x) & WM8978_2_2_BOOSTVOL_MASK) >> WM8978_2_2_BOOSTVOL_SHIFT) - -/* - * AUXL2BOOSTVOL (RW) - * Controls the auxiliary amplifer to the left/right channelinput boost stage - * for 0x2f/0x30 regs - */ -#define WM8978_AUXL2BOOSTVOL_MASK (0x07U) -#define WM8978_AUXL2BOOSTVOL_SHIFT (0U) -#define WM8978_AUXL2BOOSTVOL_SET(x) (((uint16_t)(x) << WM8978_AUXL2BOOSTVOL_SHIFT) & WM8978_AUXL2BOOSTVOL_MASK) -#define WM8978_AUXL2BOOSTVOL_GET(x) (((uint16_t)(x) & WM8978_AUXL2BOOSTVOL_MASK) >> WM8978_AUXL2BOOSTVOL_SHIFT) -#endif - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c deleted file mode 100644 index 6683a23e59e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef __ICCRISCV__ -#include -#endif -#include "hpm_debug_console.h" -#include "hpm_uart_drv.h" - -static UART_Type* g_console_uart = NULL; - -hpm_stat_t console_init(console_config_t *cfg) -{ - hpm_stat_t stat = status_fail; - - if (cfg->type == CONSOLE_TYPE_UART) { - uart_config_t config = {0}; - uart_default_config((UART_Type *)cfg->base, &config); - config.src_freq_in_hz = cfg->src_freq_in_hz; - config.baudrate = cfg->baudrate; - stat = uart_init((UART_Type *)cfg->base, &config); - if (status_success == stat) { - g_console_uart = (UART_Type *)cfg->base; - } - } - - return stat; -} - -uint8_t console_receive_byte(void) -{ - uint8_t c; - while (status_success != uart_receive_byte(g_console_uart, &c)) { - }; - return c; -} - -uint8_t console_try_receive_byte(void) -{ - uint8_t c = 0; - - uart_try_receive_byte(g_console_uart, &c); - - return c; -} - -void console_send_byte(uint8_t c) -{ - while (status_success != uart_send_byte(g_console_uart, c)) { - } -} - -#ifdef __SEGGER_RTL_VERSION -#include -#include "__SEGGER_RTL_Int.h" -static int _stdin_ungot = EOF; -struct __SEGGER_RTL_FILE_impl { /* NOTE: Provides implementation for FILE */ - int stub; /* only needed so impl has size != 0. */ -}; - -static FILE __SEGGER_RTL_stdin_file = { 0 }; /* stdin reads from UART */ -static FILE __SEGGER_RTL_stdout_file = { 0 }; /* stdout writes to UART */ -static FILE __SEGGER_RTL_stderr_file = { 0 }; /* stderr writes to UART */ - -FILE *stdin = &__SEGGER_RTL_stdin_file; /* NOTE: Provide implementation of stdin for RTL. */ -FILE *stdout = &__SEGGER_RTL_stdout_file; /* NOTE: Provide implementation of stdout for RTL. */ -FILE *stderr = &__SEGGER_RTL_stderr_file; /* NOTE: Provide implementation of stderr for RTL. */ - -int __SEGGER_RTL_X_file_write(__SEGGER_RTL_FILE *file, const char *data, unsigned int size) -{ - unsigned int count; - (void)file; - for (count = 0; count < size; count++) { - if (data[count] == '\n') { - while (status_success != uart_send_byte(g_console_uart, '\r')) { - } - } - while (status_success != uart_send_byte(g_console_uart, data[count])) { - } - } - while (status_success != uart_flush(g_console_uart)) { - } - return count; - -} - -int __SEGGER_RTL_X_file_read(__SEGGER_RTL_FILE *file, char *s, unsigned int size) -{ - (void)file; - (void) size; - while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { - } - return 1; -} - -int __SEGGER_RTL_X_file_stat(__SEGGER_RTL_FILE *stream) -{ - (void) stream; - return 0; -} - -int __SEGGER_RTL_X_file_bufsize(__SEGGER_RTL_FILE *stream) -{ - (void) stream; - return 1; -} - -int __SEGGER_RTL_X_file_unget(__SEGGER_RTL_FILE *stream, int c) -{ - if (stream == stdin) { - if (c != EOF && _stdin_ungot == EOF) { - _stdin_ungot = c; - } else { - c = EOF; - } - } else { - c = EOF; - } - return c; -} - -int __SEGGER_RTL_X_file_flush(__SEGGER_RTL_FILE *__stream) -{ - (void) __stream; - return 1; -} - -#endif - -int _write(int file, char *data, int size) -{ - int count; - (void)file; - for (count = 0; count < size; count++) { - if (data[count] == '\n') { - while (status_success != uart_send_byte(g_console_uart, '\r')) { - } - } - while (status_success != uart_send_byte(g_console_uart, data[count])) { - } - } - while (status_success != uart_flush(g_console_uart)) { - } - return count; -} - -int _read(int file, char *s, int size) -{ - (void)file; - (void) size; - while (status_success != uart_receive_byte(g_console_uart, (uint8_t *)s)) { - } - return 1; -} - -#ifndef __ICCRISCV__ -int _fstat(int file, struct stat *s) -{ - (void) file; - s->st_mode = S_IFCHR; - return 0; -} -#else - -#ifndef _DLIB_FILE_DESCRIPTOR -#define _DLIB_FILE_DESCRIPTOR 0 -#endif - -int __write(int file, char *data, int size) -{ - return _write(file, data, size); -} - -int __read(int file, char *s, int size) -{ - return _read(file, s, size); -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h b/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h deleted file mode 100644 index fd4944ae348..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_DEBUG_CONSOLE_H -#define _HPM_DEBUG_CONSOLE_H -#include "hpm_common.h" - -#define CONSOLE_TYPE_UART 0 - -typedef struct { - uint32_t type; - uint32_t base; - uint32_t src_freq_in_hz; - uint32_t baudrate; -} console_config_t; - - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -hpm_stat_t console_init(console_config_t *cfg); - -uint8_t console_receive_byte(void); -uint8_t console_try_receive_byte(void); -void console_send_byte(uint8_t c); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif /* _HPM_CONSOLE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c b/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c deleted file mode 100644 index 32f3f629bd4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c +++ /dev/null @@ -1,878 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include -#include "hpm_dma_mgr.h" -#include "hpm_soc.h" - -/***************************************************************************************************************** - * - * Definitions - * - *****************************************************************************************************************/ - -typedef struct _dma_instance_info { - DMA_Type *base; - int32_t irq_num; -} dma_chn_info_t; - -/** - * @brief DMA Channel Context Structure - */ -typedef struct _dma_channel_context { - bool is_allocated; /**< Whether DMA channel was allocated */ - void *tc_cb_data_ptr; /**< User data required by transfer complete callback */ - void *half_tc_cb_data_ptr; /**< User data required by half transfer complete callback */ - void *error_cb_data_ptr; /**< User data required by error callback */ - void *abort_cb_data_ptr; /**< User data required by abort callback */ - dma_mgr_chn_cb_t tc_cb; /**< DMA channel transfer complete callback */ - dma_mgr_chn_cb_t half_tc_cb; /**< DMA channel half transfer complete callback */ - dma_mgr_chn_cb_t error_cb; /**< DMA channel error callback */ - dma_mgr_chn_cb_t abort_cb; /**< DMA channel abort callback */ -} dma_chn_context_t; - -/** - * @brief DMA Manager Context Structure - * - */ -typedef struct _dma_mgr_context { - dma_chn_info_t dma_instance[DMA_SOC_MAX_COUNT]; /**< DMA instances */ - dma_chn_context_t channels[DMA_SOC_MAX_COUNT][DMA_SOC_CHANNEL_NUM]; /**< Array of DMA channels */ -} dma_mgr_context_t; - - -/***************************************************************************************************************** - * - * Prototypes - * - *****************************************************************************************************************/ - -/** - * @brief Search DMA channel context for specified DMA channel resource - * - * @param [in] resource DMA Channel resource - * @return The request DMA channel context if resource is valid or NULL if resource in invalid - */ -static dma_chn_context_t *dma_mgr_search_chn_context(const dma_resource_t *resource); - -static uint32_t dma_mgr_enter_critical(void); -static void dma_mgr_exit_critical(uint32_t level); - -static void dma0_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_HDMA, dma0_isr); - -#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) -static void dma1_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_XDMA, dma1_isr); -#endif - -/***************************************************************************************************************** - * - * Variables - * - *****************************************************************************************************************/ -static dma_mgr_context_t s_dma_mngr_ctx; -#define HPM_DMA_MGR (&s_dma_mngr_ctx) - -/***************************************************************************************************************** - * - * Codes - * - *****************************************************************************************************************/ -void dma_mgr_isr_handler(DMA_Type *ptr, uint32_t instance) -{ - uint32_t int_disable_mask; - uint32_t chn_int_stat; - dma_chn_context_t *chn_ctx; - - for (uint8_t channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { - int_disable_mask = dma_check_channel_interrupt_mask(ptr, channel); - chn_int_stat = dma_check_transfer_status(ptr, channel); - chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; - - if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_TC) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_TC) != 0)) { - if (chn_ctx->tc_cb != NULL) { - chn_ctx->tc_cb(ptr, channel, chn_ctx->tc_cb_data_ptr); - } - } - if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_HALF_TC) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_HALF_TC) != 0)) { - if (chn_ctx->half_tc_cb != NULL) { - chn_ctx->half_tc_cb(ptr, channel, chn_ctx->half_tc_cb_data_ptr); - } - } - if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_ERROR) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_ERROR) != 0)) { - if (chn_ctx->error_cb != NULL) { - chn_ctx->error_cb(ptr, channel, chn_ctx->error_cb_data_ptr); - } - } - if (((int_disable_mask & DMA_MGR_INTERRUPT_MASK_ABORT) == 0) && ((chn_int_stat & DMA_MGR_CHANNEL_STATUS_ABORT) != 0)) { - if (chn_ctx->abort_cb != NULL) { - chn_ctx->abort_cb(ptr, channel, chn_ctx->abort_cb_data_ptr); - } - } - } -} - -void dma0_isr(void) -{ - dma_mgr_isr_handler(HPM_HDMA, 0); -} - -#if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) -void dma1_isr(void) -{ - dma_mgr_isr_handler(HPM_XDMA, 1); -} -#endif - -static uint32_t dma_mgr_enter_critical(void) -{ - return disable_global_irq(CSR_MSTATUS_MIE_MASK); -} - -static void dma_mgr_exit_critical(uint32_t level) -{ - restore_global_irq(level); -} - -void dma_mgr_init(void) -{ - (void) memset(HPM_DMA_MGR, 0, sizeof(*HPM_DMA_MGR)); - HPM_DMA_MGR->dma_instance[0].base = HPM_HDMA, - HPM_DMA_MGR->dma_instance[0].irq_num = IRQn_HDMA; - #if defined(DMA_SOC_MAX_COUNT) && (DMA_SOC_MAX_COUNT > 1) - HPM_DMA_MGR->dma_instance[1].base = HPM_XDMA; - HPM_DMA_MGR->dma_instance[1].irq_num = IRQn_XDMA; - #endif -} - -hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource) -{ - hpm_stat_t status; - - if (resource == NULL) { - status = status_invalid_argument; - } else { - uint32_t instance; - uint32_t channel; - bool has_found = false; - uint32_t level = dma_mgr_enter_critical(); - for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { - for (channel = 0; channel < DMA_SOC_CHANNEL_NUM; channel++) { - if (!HPM_DMA_MGR->channels[instance][channel].is_allocated) { - has_found = true; - break; - } - } - if (has_found) { - break; - } - } - - if (has_found) { - HPM_DMA_MGR->channels[instance][channel].is_allocated = true; - resource->base = HPM_DMA_MGR->dma_instance[instance].base; - resource->channel = channel; - resource->irq_num = HPM_DMA_MGR->dma_instance[instance].irq_num; - status = status_success; - } else { - status = status_dma_mgr_no_resource; - } - - dma_mgr_exit_critical(level); - } - - return status; -} - -static dma_chn_context_t *dma_mgr_search_chn_context(const dma_resource_t *resource) -{ - dma_chn_context_t *chn_ctx = NULL; - - if ((resource != NULL) && (resource->channel < DMA_SOC_CHANNEL_NUM)) { - uint32_t instance; - uint32_t channel; - bool has_found = false; - for (instance = 0; instance < DMA_SOC_MAX_COUNT; instance++) { - if (resource->base == HPM_DMA_MGR->dma_instance[instance].base) { - has_found = true; - break; - } - } - - channel = resource->channel; - if (has_found) { - if (HPM_DMA_MGR->channels[instance][channel].is_allocated) { - chn_ctx = &HPM_DMA_MGR->channels[instance][channel]; - } - } - } - - return chn_ctx; -} - -hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - uint32_t level = dma_mgr_enter_critical(); - chn_ctx->is_allocated = false; - chn_ctx->tc_cb_data_ptr = NULL; - chn_ctx->half_tc_cb_data_ptr = NULL; - chn_ctx->error_cb_data_ptr = NULL; - chn_ctx->abort_cb_data_ptr = NULL; - chn_ctx->tc_cb = NULL; - chn_ctx->half_tc_cb = NULL; - chn_ctx->error_cb = NULL; - chn_ctx->abort_cb = NULL; - status = status_success; - dma_mgr_exit_critical(level); - } - return status; -} - -hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - intc_m_enable_irq_with_priority(resource->irq_num, priority); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - intc_m_disable_irq(resource->irq_num); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - chn_ctx->tc_cb_data_ptr = user_data; - chn_ctx->tc_cb = callback; - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - chn_ctx->half_tc_cb_data_ptr = user_data; - chn_ctx->half_tc_cb = callback; - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - chn_ctx->error_cb_data_ptr = user_data; - chn_ctx->error_cb = callback; - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - chn_ctx->abort_cb_data_ptr = user_data; - chn_ctx->abort_cb = callback; - status = status_success; - } - return status; -} - -void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config) -{ - config->en_dmamux = false; - config->dmamux_src = 0; - config->priority = DMA_MGR_CHANNEL_PRIORITY_LOW; - config->src_burst_size = DMA_MGR_NUM_TRANSFER_PER_BURST_1T; - config->src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; - config->dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; - config->src_width = DMA_MGR_TRANSFER_WIDTH_BYTE; - config->dst_width = DMA_MGR_TRANSFER_WIDTH_BYTE; - config->src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; - config->dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; - config->src_addr = 0; - config->dst_addr = 0; - config->size_in_byte = 0; - config->linked_ptr = 0; - config->interrupt_mask = DMA_MGR_INTERRUPT_MASK_ALL; - config->en_infiniteloop = false; - config->handshake_opt = DMA_MGR_HANDSHAKE_OPT_ONE_BURST; - config->burst_opt = DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE; - config->en_src_burst_in_fixed_trans = false; - config->en_dst_burst_in_fixed_trans = false; - config->swap_mode = DMA_MGR_SWAP_MODE_TABLE; - config->swap_table = 0; -} - -hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config) -{ - hpm_stat_t status; - uint32_t dmamux_ch; - dma_channel_config_t dma_config; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dmamux_ch = DMA_SOC_CHN_TO_DMAMUX_CHN(resource->base, resource->channel); - dmamux_config(HPM_DMAMUX, dmamux_ch, config->dmamux_src, config->en_dmamux); - dma_config.priority = config->priority; - dma_config.src_burst_size = config->src_burst_size; - dma_config.src_mode = config->src_mode; - dma_config.dst_mode = config->dst_mode; - dma_config.src_width = config->src_width; - dma_config.dst_width = config->dst_width; - dma_config.src_addr_ctrl = config->src_addr_ctrl; - dma_config.dst_addr_ctrl = config->dst_addr_ctrl; - dma_config.src_addr = config->src_addr; - dma_config.dst_addr = config->dst_addr; - dma_config.size_in_byte = config->size_in_byte; - dma_config.linked_ptr = config->linked_ptr; - dma_config.interrupt_mask = config->interrupt_mask; -#if defined(DMA_MGR_HAS_INFINITE_LOOP) && DMA_MGR_HAS_INFINITE_LOOP - dma_config.en_infiniteloop = config->en_infiniteloop; -#endif -#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT - dma_config.handshake_opt = config->handshake_opt; -#endif -#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT - dma_config.burst_opt = config->burst_opt; -#endif -#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS - dma_config.en_src_burst_in_fixed_trans = config->en_src_burst_in_fixed_trans; - dma_config.en_dst_burst_in_fixed_trans = config->en_dst_burst_in_fixed_trans; -#endif -#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP - dma_config.swap_mode = config->swap_mode; - dma_config.swap_table = config->swap_table; -#endif - status = dma_setup_channel(resource->base, resource->channel, &dma_config, false); - } - return status; -} - -hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor) -{ - hpm_stat_t status; - dma_channel_config_t dma_config; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_config.priority = config->priority; - dma_config.src_burst_size = config->src_burst_size; - dma_config.src_mode = config->src_mode; - dma_config.dst_mode = config->dst_mode; - dma_config.src_width = config->src_width; - dma_config.dst_width = config->dst_width; - dma_config.src_addr_ctrl = config->src_addr_ctrl; - dma_config.dst_addr_ctrl = config->dst_addr_ctrl; - dma_config.src_addr = config->src_addr; - dma_config.dst_addr = config->dst_addr; - dma_config.size_in_byte = config->size_in_byte; - dma_config.linked_ptr = config->linked_ptr; - dma_config.interrupt_mask = config->interrupt_mask; -#if defined(DMA_MGR_HAS_INFINITE_LOOP) && DMA_MGR_HAS_INFINITE_LOOP - dma_config.en_infiniteloop = config->en_infiniteloop; -#endif -#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT - dma_config.handshake_opt = config->handshake_opt; -#endif -#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT - dma_config.burst_opt = config->burst_opt; -#endif -#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS - dma_config.en_src_burst_in_fixed_trans = config->en_src_burst_in_fixed_trans; - dma_config.en_dst_burst_in_fixed_trans = config->en_dst_burst_in_fixed_trans; -#endif -#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP - dma_config.swap_mode = config->swap_mode; - dma_config.swap_table = config->swap_table; -#endif - status = dma_config_linked_descriptor(resource->base, (dma_linked_descriptor_t *)descriptor, resource->channel, &dma_config); - } - return status; -} - -hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - status = dma_enable_channel(resource->base, resource->channel); - } - return status; -} - -hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_disable_channel(resource->base, resource->channel); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - *enable = dma_channel_is_enable(resource->base, resource->channel); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_enable_channel_interrupt(resource->base, resource->channel, irq_mask); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_disable_channel_interrupt(resource->base, resource->channel, irq_mask); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_priority(resource->base, resource->channel, priority); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_source_work_mode(resource->base, resource->channel, mode); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_destination_work_mode(resource->base, resource->channel, mode); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_source_burst_size(resource->base, resource->channel, burstsize); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - *size = dma_get_remaining_transfer_size(resource->base, resource->channel); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_transfer_size(resource->base, resource->channel, size); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_source_width(resource->base, resource->channel, width); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_destination_width(resource->base, resource->channel, width); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_source_address(resource->base, resource->channel, addr); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_destination_address(resource->base, resource->channel, addr); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_source_address_ctrl(resource->base, resource->channel, addr_ctrl); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_set_destination_address_ctrl(resource->base, resource->channel, addr_ctrl); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_INFINITE_LOOP) && DMA_MGR_HAS_INFINITE_LOOP - dma_set_infinite_loop_mode(resource->base, resource->channel, infinite_loop); - status = status_success; -#else - (void)infinite_loop; - status = status_fail; -#endif - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT - dma_set_src_busrt_option(resource->base, resource->channel, burst_opt); - status = status_success; -#else - (void)burst_opt; - status = status_fail; -#endif - } - return status; -} - -hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT - dma_set_handshake_option(resource->base, resource->channel, handshake_opt); - status = status_success; -#else - (void)handshake_opt; - status = status_fail; -#endif - } - return status; -} - -hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { - dma_abort_channel(resource->base, 1u << resource->channel); - status = status_success; - } - return status; -} - -hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status) -{ - hpm_stat_t stat; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - stat = status_invalid_argument; - } else { - *status = dma_check_transfer_status(resource->base, resource->channel); - stat = status_success; - } - return stat; -} - -hpm_stat_t dma_mgr_set_source_burst_in_fixed_transize_enable(const dma_resource_t *resource, bool enable) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS - dma_set_source_burst_in_fixed_transize_enable(resource->base, resource->channel, enable); - status = status_success; -#else - (void)enable; - status = status_fail; -#endif - } - return status; -} - -hpm_stat_t dma_mgr_set_destination_burst_in_fix_transize_enable(const dma_resource_t *resource, bool enable) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS - dma_set_destination_burst_in_fixed_transize_enable(resource->base, resource->channel, enable); - status = status_success; -#else - (void)enable; - status = status_fail; -#endif - } - return status; -} - -hpm_stat_t dma_mgr_set_swap_mode(const dma_resource_t *resource, uint8_t swap_mode) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP - dma_set_swap_mode(resource->base, resource->channel, swap_mode); - status = status_success; -#else - (void)swap_mode; - status = status_fail; -#endif - } - return status; -} - -hpm_stat_t dma_mgr_set_swap_table(const dma_resource_t *resource, uint32_t swap_table) -{ - hpm_stat_t status; - - dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource); - - if (chn_ctx == NULL) { - status = status_invalid_argument; - } else { -#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP - dma_set_swap_table(resource->base, resource->channel, swap_table); - status = status_success; -#else - (void)swap_table; - status = status_fail; -#endif - } - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h b/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h deleted file mode 100644 index e2106609b88..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h +++ /dev/null @@ -1,623 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DMA_MGR_H -#define HPM_DMA_MGR_H - -#include "hpm_common.h" -#include "hpm_dmamux_drv.h" -#include "hpm_dmamux_src.h" -#ifdef HPMSOC_HAS_HPMSDK_DMAV2 -#include "hpm_dmav2_drv.h" -#else -#include "hpm_dma_drv.h" -#endif -#include "hpm_soc_feature.h" - -#ifdef HPMSOC_HAS_HPMSDK_DMAV2 -#define DMA_MGR_HAS_INFINITE_LOOP (1U) -#define DMA_MGR_HAS_HALF_TC_INT (1U) -#define DMA_MGR_HAS_HANDSHAKE_OPT (1U) -#define DMA_MGR_HAS_BURST_OPT (1U) -#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) -#define DMA_MGR_HAS_BURST_IN_FIXED_TRANS HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS -#else -#define DMA_MGR_HAS_BURST_IN_FIXED_TRANS 0 -#endif -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) -#define DMA_MGR_HAS_BYTE_ORDER_SWAP HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP -#else -#define DMA_MGR_HAS_BYTE_ORDER_SWAP 0 -#endif -#endif - -#define DMA_MGR_CHANNEL_PRIORITY_LOW DMA_CHANNEL_PRIORITY_LOW -#define DMA_MGR_CHANNEL_PRIORITY_HIGH DMA_CHANNEL_PRIORITY_HIGH - -#define DMA_MGR_NUM_TRANSFER_PER_BURST_1T DMA_NUM_TRANSFER_PER_BURST_1T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_2T DMA_NUM_TRANSFER_PER_BURST_2T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_4T DMA_NUM_TRANSFER_PER_BURST_4T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_8T DMA_NUM_TRANSFER_PER_BURST_8T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_16T DMA_NUM_TRANSFER_PER_BURST_16T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_32T DMA_NUM_TRANSFER_PER_BURST_32T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_64T DMA_NUM_TRANSFER_PER_BURST_64T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_128T DMA_NUM_TRANSFER_PER_BURST_128T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_256T DMA_NUM_TRANSFER_PER_BURST_256T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_512T DMA_NUM_TRANSFER_PER_BURST_512T -#define DMA_MGR_NUM_TRANSFER_PER_BURST_1024T DMA_NUM_TRANSFER_PER_BURST_1024T - -#define DMA_MGR_TRANSFER_WIDTH_BYTE DMA_TRANSFER_WIDTH_BYTE -#define DMA_MGR_TRANSFER_WIDTH_HALF_WORD DMA_TRANSFER_WIDTH_HALF_WORD -#define DMA_MGR_TRANSFER_WIDTH_WORD DMA_TRANSFER_WIDTH_WORD -#define DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD DMA_TRANSFER_WIDTH_DOUBLE_WORD - -#define DMA_MGR_HANDSHAKE_MODE_NORMAL DMA_HANDSHAKE_MODE_NORMAL -#define DMA_MGR_HANDSHAKE_MODE_HANDSHAKE DMA_HANDSHAKE_MODE_HANDSHAKE - -#define DMA_MGR_ADDRESS_CONTROL_INCREMENT DMA_ADDRESS_CONTROL_INCREMENT -#define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT -#define DMA_MGR_ADDRESS_CONTROL_FIXED DMA_ADDRESS_CONTROL_FIXED - -#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT -#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE -#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE DMA_SRC_BURST_OPT_CUSTOM_SIZE -#else -#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 0 -#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 0 -#endif - -#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT -#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST DMA_HANDSHAKE_OPT_ONE_BURST -#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE -#else -#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST 0 -#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE 0 -#endif - -#define DMA_MGR_CHANNEL_STATUS_ONGOING DMA_CHANNEL_STATUS_ONGOING -#define DMA_MGR_CHANNEL_STATUS_ERROR DMA_CHANNEL_STATUS_ERROR -#define DMA_MGR_CHANNEL_STATUS_ABORT DMA_CHANNEL_STATUS_ABORT -#define DMA_MGR_CHANNEL_STATUS_TC DMA_CHANNEL_STATUS_TC -#if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT -#define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC -#else -#define DMA_MGR_CHANNEL_STATUS_HALF_TC 0 -#endif -#define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE -#define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR -#define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT -#define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT -#if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT -#define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC -#else -#define DMA_MGR_INTERRUPT_MASK_HALF_TC 0 -#endif -#define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL - -#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP -#define DMA_MGR_SWAP_MODE_TABLE DMA_SWAP_MODE_TABLE -#define DMA_MGR_SWAP_MODE_BYTE DMA_SWAP_MODE_BYTE -#define DMA_MGR_SWAP_MODE_HALF_WORD DMA_SWAP_MODE_HALF_WORD -#define DMA_MGR_SWAP_MODE_WORD DMA_SWAP_MODE_WORD -#else -#define DMA_MGR_SWAP_MODE_TABLE 0 -#define DMA_MGR_SWAP_MODE_BYTE 0 -#define DMA_MGR_SWAP_MODE_HALF_WORD 0 -#define DMA_MGR_SWAP_MODE_WORD 0 -#endif - -#ifdef __cplusplus - -extern "C" { -#endif - -/** - * @brief DMA Manager status codes - */ -enum { - status_dma_mgr_no_resource = MAKE_STATUS(status_group_dma_manager, 0), /**< No DMA resource available */ -}; - -/** - * @brief DMA Channel Interrupt callback - * - * @param [in] DMA base address - * @param [in] channel DMA channel index - * @param [in/out] cb_data_ptr callback Data pointer - */ -typedef void (*dma_mgr_chn_cb_t)(DMA_Type *base, uint32_t channel, void *cb_data_ptr); - -/** - * @brief DMA Resource Structure - */ -typedef struct _dma_resource { - DMA_Type *base; /**< The DMA intance that the allocated channel belongs to */ - uint32_t channel; /**< Channel index */ - int32_t irq_num; /**< DMA IRQ number */ -} dma_resource_t; - -typedef struct hpm_dma_mgr_chn_conf { - bool en_dmamux; /**< DMAMUX enable */ - uint8_t dmamux_src; /**< DMAMUX source */ - uint8_t priority; /**< Channel priority */ - uint8_t src_burst_size; /**< Source burst size */ - uint8_t src_mode; /**< Source work mode: 0-Normal, 1-Handshake */ - uint8_t dst_mode; /**< Destination work mode: 0-Normal, 1-Handshake */ - uint8_t src_width; /**< Source width */ - uint8_t dst_width; /**< Destination width */ - uint8_t src_addr_ctrl; /**< Source address control: 0-inc, 1-dec, 2-fix */ - uint8_t dst_addr_ctrl; /**< Destination address control: 0-inc, 1-dec, 2-fix */ - uint16_t interrupt_mask; /**< Interrupt mask */ - uint32_t src_addr; /**< Source address */ - uint32_t dst_addr; /**< Destination address */ - uint32_t linked_ptr; /**< Next linked descriptor */ - uint32_t size_in_byte; /**< Total size to be transferred in byte */ - bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ - uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ - uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ - bool en_src_burst_in_fixed_trans; /**< Source address burst in fix transfer size enable, discard src_addr_ctrl setting. Attention: only DMAV2 support */ - bool en_dst_burst_in_fixed_trans; /**< Destination address burst in fix transfer size enable, discard dst_addr_ctrl setting. Attention: only DMAV2 support */ - uint8_t swap_mode; /**< Swap Mode. Attention: only DMAV2 support */ - uint32_t swap_table; /**< Swap Table. Attention: only DMAV2 support */ -} dma_mgr_chn_conf_t; - -typedef struct hpm_dma_mgr_linked_descriptor { - uint32_t descriptor[8]; -} dma_mgr_linked_descriptor_t; - -/** - * @brief DMA Manager ISR handler - */ -void dma_mgr_isr_handler(DMA_Type *ptr, uint32_t instance); - -/** - * @brief Initialize DMA Manager Context - */ -void dma_mgr_init(void); - -/** - * @brief Request DMA resource from DMA Manager - * - * @param [out] resource DMA resource - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - * @retval status_dma_mgr_no_resource if all DMA channels are occupied; - */ -hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource); - -/** - * @brief Release DMA resource - * - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - */ -hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource); - -/** - * @brief Enable DMA interrupt with priority - * @param [in] resource DMA resource - * @param [in] priority Interrupt Priority - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority); - -/** - * @brief Disable DMA interrupt - * NOTE: Each DMA instance consists of several DMA channels, disabling the DMA interrupt - * will disable the global DMA interrupt for all DMA channels. Please be aware of the - * impact - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource); - -/** - * @brief Install Interrupt Callback for DMA channel transfer complete - * - * @param [in] resource DMA resource - * @param [in] callback Interrupt callback for DMA resource - * @param [in] user_data User data used in the callback - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); - -/** - * @brief Install Interrupt Callback for DMA channel half transfer complete - * - * @param [in] resource DMA resource - * @param [in] callback Interrupt callback for DMA resource - * @param [in] user_data User data used in the callback - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); - -/** - * @brief Install Interrupt Callback for DMA channel transfer error - * - * @param [in] resource DMA resource - * @param [in] callback Interrupt callback for DMA resource - * @param [in] user_data User data used in the callback - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); - -/** - * @brief Install Interrupt Callback for DMA channel transfer abort - * - * @param [in] resource DMA resource - * @param [in] callback Interrupt callback for DMA resource - * @param [in] user_data User data used in the callback - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data); - -/** - * @brief Get DMA channel default config - * - * @param [out] config config data pointer - */ -void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config); - -/** - * @brief Setup channel config - * - * @param [in] resource DMA resource - * @param [in] config DMA channel config - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config); - -/** - * @brief Setup chain linked descriptor config - * - * @param [in] resource DMA resource - * @param [in] config DMA channel config - * @param [out] descriptor linked descriptor config data pointer - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor); - -/** - * @brief Enable DMA channel, start transfer - * - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource); - -/** - * @brief Disable DMA channel - * - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource); - -/** - * @brief Check DMA channel enable status - * - * @param [in] resource DMA resource - * @param [out] enable enable status - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable); - -/** - * @brief Enable DMA channel interrupt - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); - -/** - * @brief Disable DMA channel interrupt - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask); - -/** - * @brief Set DMA channel priority - * - * @param [in] resource DMA resource - * @param [in] priority DMA channel priority - * @arg @ref DMA_MGR_PRIORITY_LOW - * @arg @ref DMA_MGR_PRIORITY_HIGH - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority); - -/** - * @brief Set DMA channel source work mode - * - * @param [in] resource DMA resource - * @param [in] mode DMA source work mode - * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL - * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode); - -/** - * @brief Set DMA channel destination work mode - * - * @param [in] resource DMA resource - * @param [in] mode DMA destination work mode - * @arg @ref DMA_MGR_HANDSHAKE_MODE_NORMAL - * @arg @ref DMA_MGR_HANDSHAKE_MODE_HANDSHAKE - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode); - -/** - * @brief Set DMA channel source burst size - * - * @param [in] resource DMA resource - * @param [in] burstsize DMA source burst size - * when BURSTOPT is 0, please reference follows: - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_2T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_4T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_8T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_16T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_32T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_64T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_128T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_256T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_512T - * @arg @ref DMA_MGR_NUM_TRANSFER_PER_BURST_1024T - * when BURSTOPT is 1, burst size is (burstsize + 1). Attention: only DMAV2 support - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize); - -/** - * @brief Get DMA channel remaining transfer size - * - * @param [in] resource DMA resource - * @param [out] size remaining transfer size of the channel. - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size); - -/** - * @brief Set DMA channel transfer size - * - * @param [in] resource DMA resource - * @param [in] size transfer size of the channel. - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size); - -/** - * @brief Set DMA channel source width - * - * @param [in] resource DMA resource - * @param [in] width transfer source width of the channel - * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD - * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width); - -/** - * @brief Set DMA channel destination width - * - * @param [in] resource DMA resource - * @param [in] width transfer destination width of the channel - * @arg @ref DMA_MGR_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_MGR_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_MGR_TRANSFER_WIDTH_WORD - * @arg @ref DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width); - -/** - * @brief Set DMA channel source address - * - * @param [in] resource DMA resource - * @param [in] addr source address - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr); - -/** - * @brief Set DMA channel destination address - * - * @param [in] resource DMA resource - * @param [in] addr destination address - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr); - -/** - * @brief Set DMA channel source address control mode - * - * @param [in] resource DMA resource - * @param [in] addr_ctrl source address control mode - * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT - * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT - * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); - -/** - * @brief Set DMA channel destination address control mode - * - * @param [in] resource DMA resource - * @param [in] addr_ctrl destination address control mode - * @arg @ref DMA_MGR_ADDRESS_CONTROL_INCREMENT - * @arg @ref DMA_MGR_ADDRESS_CONTROL_DECREMENT - * @arg @ref DMA_MGR_ADDRESS_CONTROL_FIXED - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl); - -/** - * @brief Set DMA channel infinite loop mode. Attention: only DMAV2 support - * - * @param [in] resource DMA resource - * @param [in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop); - -/** - * @brief Set DMA channel source burst option. Attention: only DMAV2 support - * - * @param [in] resource DMA resource - * @param [in] burst_opt burst option - * @arg @ref DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE - * @arg @ref DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt); - -/** - * @brief Set DMA channel handshake option. Attention: only DMAV2 support - * - * @param [in] resource DMA resource - * @param [in] handshake_opt handshake option - * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST - * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt); - -/** - * @brief Abort DMA channel transfer - * - * @param [in] resource DMA resource - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource); - -/** - * @brief Check DMA channel transfer status - * - * @param [in] resource DMA resource - * @param [out] sts transfer status - * DMA_MGR_CHANNEL_STATUS_ONGOING if transfer is still ongoing - * DMA_MGR_CHANNEL_STATUS_ERROR if any error occurred during transferring - * DMA_MGR_CHANNEL_STATUS_ABORT if transfer is aborted - * DMA_MGR_CHANNEL_STATUS_TC if transfer is finished without error - * DMA_MGR_CHANNEL_STATUS_HALF_TC if half transfer complete without error. Attention: only DMAV2 support - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status); - -/** - * @brief Set DMA channel source burst in fixed transfer size enable or disable - * - * @param [in] resource DMA resource - * @param[in] enable false - disable; true - enable - * - */ -hpm_stat_t dma_mgr_set_source_burst_in_fixed_transize_enable(const dma_resource_t *resource, bool enable); - -/** - * @brief Set DMA channel destination burst in fixed transfer size enable or disable - * - * @param [in] resource DMA resource - * @param[in] enable false - disable; true - enable - * - */ -hpm_stat_t dma_mgr_set_destination_burst_in_fix_transize_enable(const dma_resource_t *resource, bool enable); - -/** - * @brief Set DMA channel swap mode - * - * @param [in] resource DMA resource - * @param[in] swap_mode swap mode - * @arg @ref DMA_MGR_SWAP_MODE_TABLE - * @arg @ref DMA_MGR_SWAP_MODE_BYTE - * @arg @ref DMA_MGR_SWAP_MODE_HALF_WORD - * @arg @ref DMA_MGR_SWAP_MODE_WORD - * - */ -hpm_stat_t dma_mgr_set_swap_mode(const dma_resource_t *resource, uint8_t swap_mode); - -/** - * @brief Set DMA channel swap table - * - * @param [in] resource DMA resource - * @param[in] swap_table swap table - * - */ -hpm_stat_t dma_mgr_set_swap_table(const dma_resource_t *resource, uint32_t swap_table); - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_DMA_MGR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c deleted file mode 100644 index b48617bda26..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_dp83848_regs.h" -#include "hpm_dp83848.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -static bool dp83848_check_id(ENET_Type *ptr) -{ - uint16_t id1, id2; - - id1 = enet_read_phy(ptr, DP83848_ADDR, DP83848_PHYIDR1); - id2 = enet_read_phy(ptr, DP83848_ADDR, DP83848_PHYIDR2); - - if (DP83848_PHYIDR1_OUI_MSB_GET(id1) == DP83848_ID1 && DP83848_PHYIDR2_OUI_LSB_GET(id2) == DP83848_ID2) { - return true; - } else { - return false; - } -} - -/*--------------------------------------------------------------------- - * API - *--------------------------------------------------------------------- - */ -void dp83848_reset(ENET_Type *ptr) -{ - uint16_t data; - - /* PHY reset */ - enet_write_phy(ptr, DP83848_ADDR, DP83848_BMCR, DP83848_BMCR_RESET_SET(1)); - - /* wait until the reset is completed */ - do { - data = enet_read_phy(ptr, DP83848_ADDR, DP83848_BMCR); - } while (DP83848_BMCR_RESET_GET(data)); -} - -void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config) -{ - (void)ptr; - - config->loopback = false; /* Disable PCS loopback mode */ - #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) - config->auto_negotiation = false; /* Disable Auto-Negotiation */ - config->speed = enet_phy_port_speed_100mbps; - config->duplex = enet_phy_duplex_full; - #else - config->auto_negotiation = true; /* Enable Auto-Negotiation */ - #endif -} - -bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config) -{ - uint16_t data = 0; - - data |= DP83848_BMCR_RESET_SET(0) /* Normal operation */ - | DP83848_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ - | DP83848_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ - | DP83848_BMCR_PWD_SET(0) /* Normal operation */ - | DP83848_BMCR_ISOLATE_SET(0) /* Normal operation */ - | DP83848_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | DP83848_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - - if (config->auto_negotiation == false) { - data |= DP83848_BMCR_SPEED0_SET(config->speed); /* Set port speed */ - data |= DP83848_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ - } - - /* check the id of dp83848 */ - if (dp83848_check_id(ptr) == false) { - return false; - } - - enet_write_phy(ptr, DP83848_ADDR, DP83848_BMCR, data); - - return true; -} - -void dp83848_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) -{ - uint16_t data; - - data = enet_read_phy(ptr, DP83848_ADDR, DP83848_PHYSTS); - status->enet_phy_link = DP83848_PHYSTS_LINK_STATUS_GET(data); - status->enet_phy_speed = DP83848_PHYSTS_SPEED_STATUS_GET(data) ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; - status->enet_phy_duplex = DP83848_PHYSTS_DUPLEX_STATUS_GET(data); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h deleted file mode 100644 index d00d57e6869..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DP83848_H -#define HPM_DP83848_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_phy.h" -#include "hpm_common.h" -#include "hpm_enet_regs.h" -/*--------------------------------------------------------------------- - * Macro Const Definitions - *--------------------------------------------------------------------- - */ -#ifndef DP83848_ADDR -#define DP83848_ADDR (1U) -#endif - -#define DP83848_ID1 (0x2000U) -#define DP83848_ID2 (0x17U) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -typedef struct { - bool loopback; - uint8_t speed; - bool auto_negotiation; - uint8_t duplex; -} dp83848_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -void dp83848_reset(ENET_Type *ptr); -void dp83848_basic_mode_default_config(ENET_Type *ptr, dp83848_config_t *config); -bool dp83848_basic_mode_init(ENET_Type *ptr, dp83848_config_t *config); -void dp83848_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_DP83848_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h deleted file mode 100644 index e99228e8478..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83848/hpm_dp83848_regs.h +++ /dev/null @@ -1,1524 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DP83848_REGS_H -#define HPM_DP83848_REGS_H - -typedef enum { - DP83848_BMCR = 0, /* 0x0: Basic Mode Control Register */ - DP83848_BMSR = 1, /* 0x1: Basic Mode Status Register */ - DP83848_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */ - DP83848_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */ - DP83848_ANAR = 4, /* 0x4: Auto-Negotiation Advertisement Register */ - DP83848_ANLPAR_BP = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ - DP83848_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */ - DP83848_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */ - DP83848_PHYSTS = 16, /* 0x10: PHY Status Register */ - DP83848_FCSCR = 20, /* 0x14: False Carrier Sense Counter Register */ - DP83848_RECR = 21, /* 0x15: Receiver Error Counter Register */ - DP83848_PCSR = 22, /* 0x16: 100 Mb/s PCS Configuration and Status Register */ - DP83848_RBR = 23, /* 0x17: RMII and Bypass Register */ - DP83848_LEDCR = 24, /* 0x18: LED Direct Control Register */ - DP83848_PHYCR = 25, /* 0x19: PHY Control Register */ - DP83848_10BTSCR = 26, /* 0x1A: 10BASE-T Status/Control Register */ - DP83848_CDCTRL1 = 27, /* 0x1B: CD Test and BIST Extensions Register */ - DP83848_EDCR = 29, /* 0x1D: Energy Detect Control */ -} DP83848_REG_Type; - - -/* Bitfield definition for register: BMCR */ -/* - * RESET (RW/SC) - * - * Reset: - * 1 = Initiate software Reset / Reset in Process. - * 0 = Normal operation. - * This bit, which is self-clearing, returns a value of one until the reset process is complete. The - * configuration is re-strapped. - */ -#define DP83848_BMCR_RESET_MASK (0x8000U) -#define DP83848_BMCR_RESET_SHIFT (15U) -#define DP83848_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESET_SHIFT) & DP83848_BMCR_RESET_MASK) -#define DP83848_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESET_MASK) >> DP83848_BMCR_RESET_SHIFT) - -/* - * LOOPBACK (RW) - * - * Loopback: - * 1 = Loopback enabled. - * 0 = Normal operation. - * The loopback function enables MII transmit data to be routed to the MII receive data path. - * Setting this bit may cause the descrambler to lose synchronization and produce a 500 µs “dead - * time” before any valid data will appear at the MII receive outputs. - */ -#define DP83848_BMCR_LOOPBACK_MASK (0x4000U) -#define DP83848_BMCR_LOOPBACK_SHIFT (14U) -#define DP83848_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83848_BMCR_LOOPBACK_SHIFT) & DP83848_BMCR_LOOPBACK_MASK) -#define DP83848_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83848_BMCR_LOOPBACK_MASK) >> DP83848_BMCR_LOOPBACK_SHIFT) - -/* - * SPEED0 (RW) - * - * Speed Select: - * When auto-negotiation is disabled writing to this bit allows the port speed to be selected. - * 1 = 100 Mb/s. - * 0 = 10 Mb/s. - */ -#define DP83848_BMCR_SPEED0_MASK (0x2000U) -#define DP83848_BMCR_SPEED0_SHIFT (13U) -#define DP83848_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83848_BMCR_SPEED0_SHIFT) & DP83848_BMCR_SPEED0_MASK) -#define DP83848_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83848_BMCR_SPEED0_MASK) >> DP83848_BMCR_SPEED0_SHIFT) - -/* - * ANE (RW) - * - * Auto-Negotiation Enable: - * Strap controls initial value at reset. - * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored when this bit is set. - * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode. - */ -#define DP83848_BMCR_ANE_MASK (0x1000U) -#define DP83848_BMCR_ANE_SHIFT (12U) -#define DP83848_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ANE_SHIFT) & DP83848_BMCR_ANE_MASK) -#define DP83848_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ANE_MASK) >> DP83848_BMCR_ANE_SHIFT) - -/* - * PWD (RW) - * - * Power Down: - * 1 = Power down. - * 0 = Normal operation. - * Setting this bit powers down the PHY. Only the register block is enabled during a power-down - * condition. - */ -#define DP83848_BMCR_PWD_MASK (0x800U) -#define DP83848_BMCR_PWD_SHIFT (11U) -#define DP83848_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83848_BMCR_PWD_SHIFT) & DP83848_BMCR_PWD_MASK) -#define DP83848_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83848_BMCR_PWD_MASK) >> DP83848_BMCR_PWD_SHIFT) - -/* - * ISOLATE (RW) - * - * Isolate: - * 1 = Isolates the Port from the MII with the exception of the serial management. - * 0 = Normal operation. - */ -#define DP83848_BMCR_ISOLATE_MASK (0x400U) -#define DP83848_BMCR_ISOLATE_SHIFT (10U) -#define DP83848_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83848_BMCR_ISOLATE_SHIFT) & DP83848_BMCR_ISOLATE_MASK) -#define DP83848_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83848_BMCR_ISOLATE_MASK) >> DP83848_BMCR_ISOLATE_SHIFT) - -/* - * RESTART_AN (RW/SC) - * - * Restart Auto-Negotiation: - * 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is - * disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until - * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation - * process is not affected by the management entity clearing this bit. - * 0 = Normal operation. - */ -#define DP83848_BMCR_RESTART_AN_MASK (0x200U) -#define DP83848_BMCR_RESTART_AN_SHIFT (9U) -#define DP83848_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83848_BMCR_RESTART_AN_SHIFT) & DP83848_BMCR_RESTART_AN_MASK) -#define DP83848_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83848_BMCR_RESTART_AN_MASK) >> DP83848_BMCR_RESTART_AN_SHIFT) - -/* - * DUPLEX (RW) - * - * Duplex Mode: - * When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be - * selected. - * 1 = Full Duplex operation. - * 0 = Half Duplex operation. - */ -#define DP83848_BMCR_DUPLEX_MASK (0x100U) -#define DP83848_BMCR_DUPLEX_SHIFT (8U) -#define DP83848_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83848_BMCR_DUPLEX_SHIFT) & DP83848_BMCR_DUPLEX_MASK) -#define DP83848_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMCR_DUPLEX_MASK) >> DP83848_BMCR_DUPLEX_SHIFT) - -/* - * COLLISION_TEST (RW) - * - * Collision Test: - * 1 = Collision test enabled. - * 0 = Normal operation. - * When set, this bit will cause the COL signal to be asserted in response to the assertion of - * TX_EN within 512-bit times. The COL signal will be deasserted within 4-bit times in response to - * the deassertion of TX_EN. - */ -#define DP83848_BMCR_COLLISION_TEST_MASK (0x80U) -#define DP83848_BMCR_COLLISION_TEST_SHIFT (7U) -#define DP83848_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83848_BMCR_COLLISION_TEST_SHIFT) & DP83848_BMCR_COLLISION_TEST_MASK) -#define DP83848_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83848_BMCR_COLLISION_TEST_MASK) >> DP83848_BMCR_COLLISION_TEST_SHIFT) - -/* Bitfield definition for register: BMSR */ -/* - * 100BASE_TX_FULL_DUPLEX (RO) - * - * 100BASE-TX Full Duplex Capable: - * 1 = Device able to perform 100BASE-TX in full duplex mode. - */ -#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) -#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) -#define DP83848_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83848_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) - -/* - * 100BASE_TX_HALF (RO) - * - * 100BASE-TX Half Duplex Capable: - * 1 = Device able to perform 100BASE-TX in half duplex mode. - */ -#define DP83848_BMSR_100BASE_TX_HALF_MASK (0x2000U) -#define DP83848_BMSR_100BASE_TX_HALF_SHIFT (13U) -#define DP83848_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & DP83848_BMSR_100BASE_TX_HALF_MASK) >> DP83848_BMSR_100BASE_TX_HALF_SHIFT) - -/* - * 10BASE_T_FULL_DUPLEX (RO) - * - * 10BASE-T Full Duplex Capable: - * 1 = Device able to perform 10BASE-T in full duplex mode. - */ -#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK (0x1000U) -#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT (12U) -#define DP83848_BMSR_10BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_FULL_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_FULL_DUPLEX_SHIFT) - -/* - * 10BASE_T_HALF_DUPLEX (RO) - * - * 10BASE-T Half Duplex Capable: - * 1 = Device able to perform 10BASE-T in half duplex mode. - */ -#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK (0x800U) -#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT (11U) -#define DP83848_BMSR_10BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83848_BMSR_10BASE_T_HALF_DUPLEX_MASK) >> DP83848_BMSR_10BASE_T_HALF_DUPLEX_SHIFT) - -/* - * MF_PREAMBLE_SUPPRESSION (RO) - * - * Preamble suppression Capable: - * 1 = Device able to perform management transaction with preamble suppressed, 32-bits of - * preamble needed only once after reset, invalid opcode or invalid turnaround. - * 0 = Normal management operation. - */ -#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) -#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) -#define DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83848_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) - -/* - * AUTO_NEGOTIATION_COMPLETE (RO) - * - * Auto-Negotiation Complete: - * 1 = Auto-Negotiation process complete. - * 0 = Auto-Negotiation process not complete. - */ -#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) -#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) -#define DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) - -/* - * REMOTE_FAULT (RO) - * - * Remote Fault: - * 1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Notification from - * Link Partner of Remote Fault. - * 0 = No remote fault condition detected. - */ -#define DP83848_BMSR_REMOTE_FAULT_MASK (0x10U) -#define DP83848_BMSR_REMOTE_FAULT_SHIFT (4U) -#define DP83848_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_BMSR_REMOTE_FAULT_MASK) >> DP83848_BMSR_REMOTE_FAULT_SHIFT) - -/* - * AUTO_NEGOTIATION_ABILITY (RO) - * - * Auto Negotiation Ability: - * 1 = Device is able to perform Auto-Negotiation. - * 0 = Device is not able to perform Auto-Negotiation. - */ -#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) -#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) -#define DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83848_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) - -/* - * LINK_STATUS (RO) - * - * Link Status: - * 1 = Valid link established (for either 10 or 100 Mb/s operation). - * 0 = Link not established. - * The criteria for link validity is implementation specific. The occurrence of a link failure condition - * will causes the Link Status bit to clear. Once cleared, this bit may only be set by establishing a - * good link condition and a read through the management interface. - */ -#define DP83848_BMSR_LINK_STATUS_MASK (0x4U) -#define DP83848_BMSR_LINK_STATUS_SHIFT (2U) -#define DP83848_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_BMSR_LINK_STATUS_MASK) >> DP83848_BMSR_LINK_STATUS_SHIFT) - -/* - * JABBER_DETECT (RO) - * - * Jabber Detect: This bit only has meaning in 10 Mb/s mode. - * 1 = Jabber condition detected. - * 0 = No Jabber. - * This bit is implemented with a latching function, such that the occurrence of a jabber condition - * causes it to set until it is cleared by a read to this register by the management interface or by a - * reset. - */ -#define DP83848_BMSR_JABBER_DETECT_MASK (0x2U) -#define DP83848_BMSR_JABBER_DETECT_SHIFT (1U) -#define DP83848_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_BMSR_JABBER_DETECT_MASK) >> DP83848_BMSR_JABBER_DETECT_SHIFT) - -/* - * EXTENDED_CAPABILITY (RO) - * - * Extended Capability: - * 1 = Extended register capabilities. - * 0 = Basic register set capabilities only. - */ -#define DP83848_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) -#define DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) -#define DP83848_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83848_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83848_BMSR_EXTENDED_CAPABILITY_SHIFT) - -/* Bitfield definition for register: PHYIDR1 */ -/* - * OUI_MSB (RO) - * - * OUI Most Significant Bits: - * Bits 3 to 18 of the OUI (080017h) are stored in bits 15 to 0 of this register. The most - * significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and - * 2). - */ -#define DP83848_PHYIDR1_OUI_MSB_MASK (0xFFFFU) -#define DP83848_PHYIDR1_OUI_MSB_SHIFT (0U) -#define DP83848_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR1_OUI_MSB_MASK) >> DP83848_PHYIDR1_OUI_MSB_SHIFT) - -/* Bitfield definition for register: PHYIDR2 */ -/* - * OUI_LSB (RO) - * - * OUI Least Significant Bits: - * Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of this register - * respectively. - */ -#define DP83848_PHYIDR2_OUI_LSB_MASK (0xFC00U) -#define DP83848_PHYIDR2_OUI_LSB_SHIFT (10U) -#define DP83848_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_OUI_LSB_MASK) >> DP83848_PHYIDR2_OUI_LSB_SHIFT) - -/* - * VNDR_MDL (RO) - * - * Vendor Model Number: - * The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit - * 9). - */ -#define DP83848_PHYIDR2_VNDR_MDL_MASK (0x3F0U) -#define DP83848_PHYIDR2_VNDR_MDL_SHIFT (4U) -#define DP83848_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_VNDR_MDL_MASK) >> DP83848_PHYIDR2_VNDR_MDL_SHIFT) - -/* - * MDL_REV (RO) - * - * Model Revision Number: - * Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant - * bit to bit 3). This field will be incremented for all major device changes. - */ -#define DP83848_PHYIDR2_MDL_REV_MASK (0xFU) -#define DP83848_PHYIDR2_MDL_REV_SHIFT (0U) -#define DP83848_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83848_PHYIDR2_MDL_REV_MASK) >> DP83848_PHYIDR2_MDL_REV_SHIFT) - -/* Bitfield definition for register: ANAR */ -/* - * NP (RW) - * - * Next Page Indication: - * 0 = Next Page Transfer not desired. - * 1 = Next Page Transfer desired. - */ -#define DP83848_ANAR_NP_MASK (0x8000U) -#define DP83848_ANAR_NP_SHIFT (15U) -#define DP83848_ANAR_NP_SET(x) (((uint16_t)(x) << DP83848_ANAR_NP_SHIFT) & DP83848_ANAR_NP_MASK) -#define DP83848_ANAR_NP_GET(x) (((uint16_t)(x) & DP83848_ANAR_NP_MASK) >> DP83848_ANAR_NP_SHIFT) - -/* - * RF (RW) - * - * Remote Fault: - * 1 = Advertises that this device has detected a Remote Fault. - * 0 = No Remote Fault detected. - */ -#define DP83848_ANAR_RF_MASK (0x2000U) -#define DP83848_ANAR_RF_SHIFT (13U) -#define DP83848_ANAR_RF_SET(x) (((uint16_t)(x) << DP83848_ANAR_RF_SHIFT) & DP83848_ANAR_RF_MASK) -#define DP83848_ANAR_RF_GET(x) (((uint16_t)(x) & DP83848_ANAR_RF_MASK) >> DP83848_ANAR_RF_SHIFT) - -/* - * ASM_DIR (RW) - * - * Asymmetric PAUSE Support for Full Duplex Links: - * The ASM_DIR bit indicates that asymmetric PAUSE is supported. - * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and - * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. - * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer - * and the pause function as specified in clause 31 and annex 31B of 802.3. - * 0= No MAC based full duplex flow control. - */ -#define DP83848_ANAR_ASM_DIR_MASK (0x800U) -#define DP83848_ANAR_ASM_DIR_SHIFT (11U) -#define DP83848_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83848_ANAR_ASM_DIR_SHIFT) & DP83848_ANAR_ASM_DIR_MASK) -#define DP83848_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANAR_ASM_DIR_MASK) >> DP83848_ANAR_ASM_DIR_SHIFT) - -/* - * PAUSE (RW) - * - * PAUSE Support for Full Duplex Links: - * The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE - * functions as defined in Annex 31B. - * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and - * 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12]. - * 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer - * and the pause function as specified in clause 31 and annex 31B of 802.3. - * 0= No MAC based full duplex flow control. - */ -#define DP83848_ANAR_PAUSE_MASK (0x400U) -#define DP83848_ANAR_PAUSE_SHIFT (10U) -#define DP83848_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83848_ANAR_PAUSE_SHIFT) & DP83848_ANAR_PAUSE_MASK) -#define DP83848_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANAR_PAUSE_MASK) >> DP83848_ANAR_PAUSE_SHIFT) - -/* - * T4 (RO) - * - * 100BASE-T4 Support: - * 1= 100BASE-T4 is supported by the local device. - * 0 = 100BASE-T4 not supported. - */ -#define DP83848_ANAR_T4_MASK (0x200U) -#define DP83848_ANAR_T4_SHIFT (9U) -#define DP83848_ANAR_T4_GET(x) (((uint16_t)(x) & DP83848_ANAR_T4_MASK) >> DP83848_ANAR_T4_SHIFT) - -/* - * TX_FD (RW) - * - * 100BASE-TX Full Duplex Support: - * 1 = 100BASE-TX Full Duplex is supported by the local device. - * 0 = 100BASE-TX Full Duplex not supported. - */ -#define DP83848_ANAR_TX_FD_MASK (0x100U) -#define DP83848_ANAR_TX_FD_SHIFT (8U) -#define DP83848_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_FD_SHIFT) & DP83848_ANAR_TX_FD_MASK) -#define DP83848_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_FD_MASK) >> DP83848_ANAR_TX_FD_SHIFT) - -/* - * TX (RW) - * - * 100BASE-TX Support: - * 1 = 100BASE-TX is supported by the local device. - * 0 = 100BASE-TX not supported. - */ -#define DP83848_ANAR_TX_MASK (0x80U) -#define DP83848_ANAR_TX_SHIFT (7U) -#define DP83848_ANAR_TX_SET(x) (((uint16_t)(x) << DP83848_ANAR_TX_SHIFT) & DP83848_ANAR_TX_MASK) -#define DP83848_ANAR_TX_GET(x) (((uint16_t)(x) & DP83848_ANAR_TX_MASK) >> DP83848_ANAR_TX_SHIFT) - -/* - * 10_FD (RW) - * - * 10BASE-T Full Duplex Support: - * 1 = 10BASE-T Full Duplex is supported by the local device. - * 0 = 10BASE-T Full Duplex not supported. - */ -#define DP83848_ANAR_10_FD_MASK (0x40U) -#define DP83848_ANAR_10_FD_SHIFT (6U) -#define DP83848_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_FD_SHIFT) & DP83848_ANAR_10_FD_MASK) -#define DP83848_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_FD_MASK) >> DP83848_ANAR_10_FD_SHIFT) - -/* - * 10 (RW) - * - * 10BASE-T Support: - * 1 = 10BASE-T is supported by the local device. - * 0 = 10BASE-T not supported. - */ -#define DP83848_ANAR_10_MASK (0x20U) -#define DP83848_ANAR_10_SHIFT (5U) -#define DP83848_ANAR_10_SET(x) (((uint16_t)(x) << DP83848_ANAR_10_SHIFT) & DP83848_ANAR_10_MASK) -#define DP83848_ANAR_10_GET(x) (((uint16_t)(x) & DP83848_ANAR_10_MASK) >> DP83848_ANAR_10_SHIFT) - -/* - * SELECTOR (RW) - * - * Protocol Selection Bits: - * These bits contain the binary encoded protocol selector supported by this port. <00001> - * indicates that this device supports IEEE 802.3. - */ -#define DP83848_ANAR_SELECTOR_MASK (0x1FU) -#define DP83848_ANAR_SELECTOR_SHIFT (0U) -#define DP83848_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83848_ANAR_SELECTOR_SHIFT) & DP83848_ANAR_SELECTOR_MASK) -#define DP83848_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANAR_SELECTOR_MASK) >> DP83848_ANAR_SELECTOR_SHIFT) - -/* Bitfield definition for register: ANLPAR_BP */ -/* - * NP (RO) - * - * Next Page Indication: - * 0 = Link Partner does not desire Next Page Transfer. - * 1 = Link Partner desires Next Page Transfer. - */ -#define DP83848_ANLPAR_BP_NP_MASK (0x8000U) -#define DP83848_ANLPAR_BP_NP_SHIFT (15U) -#define DP83848_ANLPAR_BP_NP_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_NP_MASK) >> DP83848_ANLPAR_BP_NP_SHIFT) - -/* - * ACK (RO) - * - * Acknowledge: - * 1 = Link Partner acknowledges reception of the ability data word. - * 0 = Not acknowledged. - * The Auto-Negotiation state machine will automatically control the this bit based on the incoming - * FLP bursts. - */ -#define DP83848_ANLPAR_BP_ACK_MASK (0x4000U) -#define DP83848_ANLPAR_BP_ACK_SHIFT (14U) -#define DP83848_ANLPAR_BP_ACK_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ACK_MASK) >> DP83848_ANLPAR_BP_ACK_SHIFT) - -/* - * RF (RO) - * - * Remote Fault: - * 1 = Remote Fault indicated by Link Partner. - * 0 = No Remote Fault indicated by Link Partner. - */ -#define DP83848_ANLPAR_BP_RF_MASK (0x2000U) -#define DP83848_ANLPAR_BP_RF_SHIFT (13U) -#define DP83848_ANLPAR_BP_RF_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_RF_MASK) >> DP83848_ANLPAR_BP_RF_SHIFT) - -/* - * ASM_DIR (RO) - * - * ASYMMETRIC PAUSE: - * 1 = Asymmetric pause is supported by the Link Partner. - * 0 = Asymmetric pause is not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_ASM_DIR_MASK (0x800U) -#define DP83848_ANLPAR_BP_ASM_DIR_SHIFT (11U) -#define DP83848_ANLPAR_BP_ASM_DIR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_ASM_DIR_MASK) >> DP83848_ANLPAR_BP_ASM_DIR_SHIFT) - -/* - * PAUSE (RO) - * - * PAUSE: - * 1 = Pause function is supported by the Link Partner. - * 0 = Pause function is not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_PAUSE_MASK (0x400U) -#define DP83848_ANLPAR_BP_PAUSE_SHIFT (10U) -#define DP83848_ANLPAR_BP_PAUSE_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_PAUSE_MASK) >> DP83848_ANLPAR_BP_PAUSE_SHIFT) - -/* - * T4 (RO) - * - * 100BASE-T4 Support: - * 1 = 100BASE-T4 is supported by the Link Partner. - * 0 = 100BASE-T4 not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_T4_MASK (0x200U) -#define DP83848_ANLPAR_BP_T4_SHIFT (9U) -#define DP83848_ANLPAR_BP_T4_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_T4_MASK) >> DP83848_ANLPAR_BP_T4_SHIFT) - -/* - * TX_FD (RO) - * - * 100BASE-TX Full Duplex Support: - * 1 = 100BASE-TX Full Duplex is supported by the Link Partner. - * 0 = 100BASE-TX Full Duplex not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_TX_FD_MASK (0x100U) -#define DP83848_ANLPAR_BP_TX_FD_SHIFT (8U) -#define DP83848_ANLPAR_BP_TX_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_FD_MASK) >> DP83848_ANLPAR_BP_TX_FD_SHIFT) - -/* - * TX (RO) - * - * 100BASE-TX Support: - * 1 = 100BASE-TX is supported by the Link Partner. - * 0 = 100BASE-TX not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_TX_MASK (0x80U) -#define DP83848_ANLPAR_BP_TX_SHIFT (7U) -#define DP83848_ANLPAR_BP_TX_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_TX_MASK) >> DP83848_ANLPAR_BP_TX_SHIFT) - -/* - * 10_FD (RO) - * - * 10BASE-T Full Duplex Support: - * 1 = 10BASE-T Full Duplex is supported by the Link Partner. - * 0 = 10BASE-T Full Duplex not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_10_FD_MASK (0x40U) -#define DP83848_ANLPAR_BP_10_FD_SHIFT (6U) -#define DP83848_ANLPAR_BP_10_FD_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_FD_MASK) >> DP83848_ANLPAR_BP_10_FD_SHIFT) - -/* - * 10 (RO) - * - * 10BASE-T Support: - * 1 = 10BASE-T is supported by the Link Partner. - * 0 = 10BASE-T not supported by the Link Partner. - */ -#define DP83848_ANLPAR_BP_10_MASK (0x20U) -#define DP83848_ANLPAR_BP_10_SHIFT (5U) -#define DP83848_ANLPAR_BP_10_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_10_MASK) >> DP83848_ANLPAR_BP_10_SHIFT) - -/* - * SELECTOR (RO) - * - * Protocol Selection Bits: - * Link Partner’s binary encoded protocol selector. - */ -#define DP83848_ANLPAR_BP_SELECTOR_MASK (0x1FU) -#define DP83848_ANLPAR_BP_SELECTOR_SHIFT (0U) -#define DP83848_ANLPAR_BP_SELECTOR_GET(x) (((uint16_t)(x) & DP83848_ANLPAR_BP_SELECTOR_MASK) >> DP83848_ANLPAR_BP_SELECTOR_SHIFT) - -/* Bitfield definition for register: ANER */ -/* - * PDF (RO) - * - * Parallel Detection Fault: - * 1 = A fault has been detected through the Parallel Detection function. - * 0 = A fault has not been detected. - */ -#define DP83848_ANER_PDF_MASK (0x10U) -#define DP83848_ANER_PDF_SHIFT (4U) -#define DP83848_ANER_PDF_GET(x) (((uint16_t)(x) & DP83848_ANER_PDF_MASK) >> DP83848_ANER_PDF_SHIFT) - -/* - * LP_NP_ABLE (RO) - * - * Link Partner Next Page Able: - * 1 = Link Partner does support Next Page. - * 0 = Link Partner does not support Next Page. - */ -#define DP83848_ANER_LP_NP_ABLE_MASK (0x8U) -#define DP83848_ANER_LP_NP_ABLE_SHIFT (3U) -#define DP83848_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_NP_ABLE_MASK) >> DP83848_ANER_LP_NP_ABLE_SHIFT) - -/* - * NP_ABLE (RO) - * - * Next Page Able: - * 1 = Indicates local device is able to send additional “Next Pages”. - */ -#define DP83848_ANER_NP_ABLE_MASK (0x4U) -#define DP83848_ANER_NP_ABLE_SHIFT (2U) -#define DP83848_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_NP_ABLE_MASK) >> DP83848_ANER_NP_ABLE_SHIFT) - -/* - * PAGE_RX (RO) - * - * Link Code Word Page Received: - * 1 = Link Code Word has been received, cleared on a read. - * 0 = Link Code Word has not been received. - */ -#define DP83848_ANER_PAGE_RX_MASK (0x2U) -#define DP83848_ANER_PAGE_RX_SHIFT (1U) -#define DP83848_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83848_ANER_PAGE_RX_MASK) >> DP83848_ANER_PAGE_RX_SHIFT) - -/* - * LP_AN_ABLE (RO) - * - * Link Partner Auto-Negotiation Able: - * 1 = indicates that the Link Partner supports Auto-Negotiation. - * 0 = indicates that the Link Partner does not support Auto-Negotiation. - */ -#define DP83848_ANER_LP_AN_ABLE_MASK (0x1U) -#define DP83848_ANER_LP_AN_ABLE_SHIFT (0U) -#define DP83848_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83848_ANER_LP_AN_ABLE_MASK) >> DP83848_ANER_LP_AN_ABLE_SHIFT) - -/* Bitfield definition for register: ANNPTR */ -/* - * NP (RW) - * - * Next Page Indication: - * 0 = No other Next Page Transfer desired. - * 1 = Another Next Page desired. - */ -#define DP83848_ANNPTR_NP_MASK (0x8000U) -#define DP83848_ANNPTR_NP_SHIFT (15U) -#define DP83848_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_NP_SHIFT) & DP83848_ANNPTR_NP_MASK) -#define DP83848_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_NP_MASK) >> DP83848_ANNPTR_NP_SHIFT) - -/* - * MP (RW) - * - * Message Page: - * 1 = Message Page. - * 0 = Unformatted Page. - */ -#define DP83848_ANNPTR_MP_MASK (0x2000U) -#define DP83848_ANNPTR_MP_SHIFT (13U) -#define DP83848_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_MP_SHIFT) & DP83848_ANNPTR_MP_MASK) -#define DP83848_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_MP_MASK) >> DP83848_ANNPTR_MP_SHIFT) - -/* - * ACK2 (RW) - * - * Acknowledge2: - * 1 = Will comply with message. - * 0 = Cannot comply with message. - * Acknowledge2 is used by the next page function to indicate that Local Device has the ability - * to comply with the message received. - */ -#define DP83848_ANNPTR_ACK2_MASK (0x1000U) -#define DP83848_ANNPTR_ACK2_SHIFT (12U) -#define DP83848_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_ACK2_SHIFT) & DP83848_ANNPTR_ACK2_MASK) -#define DP83848_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_ACK2_MASK) >> DP83848_ANNPTR_ACK2_SHIFT) - -/* - * TOG_TX (RW) - * - * Toggle: - * 1 = Value of toggle bit in previously transmitted Link Code Word was 0. - * 0 = Value of toggle bit in previously transmitted Link Code Word was 1. - * Toggle is used by the Arbitration function within Auto-Negotiation to ensure synchronization - * with the Link Partner during Next Page exchange. This bit shall always take the opposite - * value of the Toggle bit in the previously exchanged Link Code Word. - */ -#define DP83848_ANNPTR_TOG_TX_MASK (0x800U) -#define DP83848_ANNPTR_TOG_TX_SHIFT (11U) -#define DP83848_ANNPTR_TOG_TX_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_TOG_TX_SHIFT) & DP83848_ANNPTR_TOG_TX_MASK) -#define DP83848_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_TOG_TX_MASK) >> DP83848_ANNPTR_TOG_TX_SHIFT) - -/* - * CODE (RW) - * - * This field represents the code field of the next page transmission. If the MP bit is set (bit 13 - * of this register), then the code shall be interpreted as a "Message Page”, as defined in annex - * 28C of IEEE 802.3. Otherwise, the code shall be interpreted as an "Unformatted Page”, and - * the interpretation is application specific. - * The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE - * 802.3. - */ -#define DP83848_ANNPTR_CODE_MASK (0x400U) -#define DP83848_ANNPTR_CODE_SHIFT (10U) -#define DP83848_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83848_ANNPTR_CODE_SHIFT) & DP83848_ANNPTR_CODE_MASK) -#define DP83848_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83848_ANNPTR_CODE_MASK) >> DP83848_ANNPTR_CODE_SHIFT) - -/* Bitfield definition for register: PHYSTS */ -/* - * MDI_X_MODE (RO) - * - * MDI-X mode as reported by the Auto-Negotiation logic: - * This bit will be affected by the settings of the MDIX_EN and FORCE_MDIX bits in the - * PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as - * the Auto-MDIX algorithm swaps between MDI and MDI-X configurations. - * 1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair) - * 0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair) - */ -#define DP83848_PHYSTS_MDI_X_MODE_MASK (0x4000U) -#define DP83848_PHYSTS_MDI_X_MODE_SHIFT (14U) -#define DP83848_PHYSTS_MDI_X_MODE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_MDI_X_MODE_MASK) >> DP83848_PHYSTS_MDI_X_MODE_SHIFT) - -/* - * RECEIVE_ERRORLATCH (RO) - * - * Receive Error Latch: - * This bit will be cleared upon a read of the RECR register. - * 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0). - * 0 = No receive error event has occurred. - */ -#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK (0x2000U) -#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT (13U) -#define DP83848_PHYSTS_RECEIVE_ERRORLATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_RECEIVE_ERRORLATCH_MASK) >> DP83848_PHYSTS_RECEIVE_ERRORLATCH_SHIFT) - -/* - * POLARITY_STATUS (RO) - * - * Polarity Status: - * This bit is a duplication of bit 4 in the 10BTSCR register. This bit will be cleared upon a read - * of the 10BTSCR register, but not upon a read of the PHYSTS register. - * 1 = Inverted Polarity detected. - * 0 = Correct Polarity detected. - */ -#define DP83848_PHYSTS_POLARITY_STATUS_MASK (0x1000U) -#define DP83848_PHYSTS_POLARITY_STATUS_SHIFT (12U) -#define DP83848_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_POLARITY_STATUS_MASK) >> DP83848_PHYSTS_POLARITY_STATUS_SHIFT) - -/* - * FALSE_CARRIER_SENSE_LATCH (RO) - * - * False Carrier Sense Latch: - * This bit will be cleared upon a read of the FCSR register. - * 1 = False Carrier event has occurred since last read of FCSCR (address 0x14). - * 0 = No False Carrier event has occurred. - */ -#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK (0x800U) -#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT (11U) -#define DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_MASK) >> DP83848_PHYSTS_FALSE_CARRIER_SENSE_LATCH_SHIFT) - -/* - * SIGNAL_DETECT (RO) - * - * 100Base-TX unconditional Signal Detect from PMD. - */ -#define DP83848_PHYSTS_SIGNAL_DETECT_MASK (0x400U) -#define DP83848_PHYSTS_SIGNAL_DETECT_SHIFT (10U) -#define DP83848_PHYSTS_SIGNAL_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SIGNAL_DETECT_MASK) >> DP83848_PHYSTS_SIGNAL_DETECT_SHIFT) - -/* - * DESCRAMBLER_LOCK (RO) - * - * 100Base-TX Descrambler Lock from PMD. - */ -#define DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK (0x200U) -#define DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT (9U) -#define DP83848_PHYSTS_DESCRAMBLER_LOCK_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DESCRAMBLER_LOCK_MASK) >> DP83848_PHYSTS_DESCRAMBLER_LOCK_SHIFT) - -/* - * PAGE_RECEIVED (RO) - * - * Link Code Word Page Received: - * This is a duplicate of the Page Received bit in the ANER register, but this bit will not be - * cleared upon a read of the PHYSTS register. - * 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address - * 0x06, bit 1). - * 0 = Link Code Word Page has not been received. - */ -#define DP83848_PHYSTS_PAGE_RECEIVED_MASK (0x100U) -#define DP83848_PHYSTS_PAGE_RECEIVED_SHIFT (8U) -#define DP83848_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_PAGE_RECEIVED_MASK) >> DP83848_PHYSTS_PAGE_RECEIVED_SHIFT) - -/* - * REMOTE_FAULT (RO) - * - * Remote Fault: - * 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by - * reset). Fault criteria: notification from Link Partner of Remote Fault through Auto-Negotiation. - * 0 = No remote fault condition detected. - */ -#define DP83848_PHYSTS_REMOTE_FAULT_MASK (0x40U) -#define DP83848_PHYSTS_REMOTE_FAULT_SHIFT (6U) -#define DP83848_PHYSTS_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_REMOTE_FAULT_MASK) >> DP83848_PHYSTS_REMOTE_FAULT_SHIFT) - -/* - * JABBER_DETECT (RO) - * - * Jabber Detect: This bit only has meaning in 10 Mb/s mode - * This bit is a duplicate of the Jabber Detect bit in the BMSR register, except that it is not - * cleared upon a read of the PHYSTS register. - * 1 = Jabber condition detected. - * 0 = No Jabber. - */ -#define DP83848_PHYSTS_JABBER_DETECT_MASK (0x20U) -#define DP83848_PHYSTS_JABBER_DETECT_SHIFT (5U) -#define DP83848_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_JABBER_DETECT_MASK) >> DP83848_PHYSTS_JABBER_DETECT_SHIFT) - -/* - * AUTO_NEG_COMPLETE (RO) - * - * Auto-Negotiation Complete: - * 1 = Auto-Negotiation complete. - * 0 = Auto-Negotiation not complete. - */ -#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK (0x10U) -#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT (4U) -#define DP83848_PHYSTS_AUTO_NEG_COMPLETE_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_AUTO_NEG_COMPLETE_MASK) >> DP83848_PHYSTS_AUTO_NEG_COMPLETE_SHIFT) - -/* - * LOOPBACK_STATUS (RO) - * - * Loopback: - * 1 = Loopback enabled. - * 0 = Normal operation. - */ -#define DP83848_PHYSTS_LOOPBACK_STATUS_MASK (0x8U) -#define DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT (3U) -#define DP83848_PHYSTS_LOOPBACK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LOOPBACK_STATUS_MASK) >> DP83848_PHYSTS_LOOPBACK_STATUS_SHIFT) - -/* - * DUPLEX_STATUS (RO) - * - * Duplex: - * This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. - * 1 = Full duplex mode. - * 0 = Half duplex mode. - * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid - * link or if Auto-Negotiation is disabled and there is a valid link. - */ -#define DP83848_PHYSTS_DUPLEX_STATUS_MASK (0x4U) -#define DP83848_PHYSTS_DUPLEX_STATUS_SHIFT (2U) -#define DP83848_PHYSTS_DUPLEX_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_DUPLEX_STATUS_MASK) >> DP83848_PHYSTS_DUPLEX_STATUS_SHIFT) - -/* - * SPEED_STATUS (RO) - * - * Speed10: - * This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced - * Modes. - * 1 = 10 Mb/s mode. - * 0 = 100 Mb/s mode. - * Note: This bit is only valid if Auto-Negotiation is enabled and complete and there is a valid - * link or if Auto-Negotiation is disabled and there is a valid link. - */ -#define DP83848_PHYSTS_SPEED_STATUS_MASK (0x2U) -#define DP83848_PHYSTS_SPEED_STATUS_SHIFT (1U) -#define DP83848_PHYSTS_SPEED_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_SPEED_STATUS_MASK) >> DP83848_PHYSTS_SPEED_STATUS_SHIFT) - -/* - * LINK_STATUS (RO) - * - * Link Status: - * This bit is a duplicate of the Link Status bit in the BMSR register, except that it will not be - * cleared upon a read of the PHYSTS register. - * 1 = Valid link established (for either 10 or 100 Mb/s operation) - * 0 = Link not established. - */ -#define DP83848_PHYSTS_LINK_STATUS_MASK (0x1U) -#define DP83848_PHYSTS_LINK_STATUS_SHIFT (0U) -#define DP83848_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYSTS_LINK_STATUS_MASK) >> DP83848_PHYSTS_LINK_STATUS_SHIFT) - -/* Bitfield definition for register: FCSCR */ -/* - * FCSCNT_7_0 (RO) - * - * False Carrier Event Counter: - * This 8-bit counter increments on every false carrier event. This counter sticks when it - * reaches its max count (FFh). - */ -#define DP83848_FCSCR_FCSCNT_7_0_MASK (0xFFU) -#define DP83848_FCSCR_FCSCNT_7_0_SHIFT (0U) -#define DP83848_FCSCR_FCSCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_FCSCR_FCSCNT_7_0_MASK) >> DP83848_FCSCR_FCSCNT_7_0_SHIFT) - -/* Bitfield definition for register: RECR */ -/* - * RXERCNT_7_0 (RO) - * - * RX_ER Counter: - * When a valid carrier is present and there is at least one occurrence of an invalid data - * symbol, this 8-bit counter increments for each receive error detected. This event can - * increment only once per valid carrier event. If a collision is present, the attribute will not - * increment. The counter sticks when it reaches its max count. - */ -#define DP83848_RECR_RXERCNT_7_0_MASK (0xFFU) -#define DP83848_RECR_RXERCNT_7_0_SHIFT (0U) -#define DP83848_RECR_RXERCNT_7_0_GET(x) (((uint16_t)(x) & DP83848_RECR_RXERCNT_7_0_MASK) >> DP83848_RECR_RXERCNT_7_0_SHIFT) - -/* Bitfield definition for register: PCSR */ -/* - * TQ_EN (RW) - * - * 100Mbs True Quiet Mode Enable: - * 1 = Transmit True Quiet Mode. - * 0 = Normal Transmit Mode. - */ -#define DP83848_PCSR_TQ_EN_MASK (0x400U) -#define DP83848_PCSR_TQ_EN_SHIFT (10U) -#define DP83848_PCSR_TQ_EN_SET(x) (((uint16_t)(x) << DP83848_PCSR_TQ_EN_SHIFT) & DP83848_PCSR_TQ_EN_MASK) -#define DP83848_PCSR_TQ_EN_GET(x) (((uint16_t)(x) & DP83848_PCSR_TQ_EN_MASK) >> DP83848_PCSR_TQ_EN_SHIFT) - -/* - * SD_FORCE_PMA (RW) - * - * Signal Detect Force PMA: - * 1 = Forces Signal Detection in PMA. - * 0 = Normal SD operation. - */ -#define DP83848_PCSR_SD_FORCE_PMA_MASK (0x200U) -#define DP83848_PCSR_SD_FORCE_PMA_SHIFT (9U) -#define DP83848_PCSR_SD_FORCE_PMA_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_FORCE_PMA_SHIFT) & DP83848_PCSR_SD_FORCE_PMA_MASK) -#define DP83848_PCSR_SD_FORCE_PMA_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_FORCE_PMA_MASK) >> DP83848_PCSR_SD_FORCE_PMA_SHIFT) - -/* - * SD_OPTION (RW) - * - * Signal Detect Option: - * 1 = Enhanced signal detect algorithm. - * 0 = Reduced signal detect algorithm. - */ -#define DP83848_PCSR_SD_OPTION_MASK (0x100U) -#define DP83848_PCSR_SD_OPTION_SHIFT (8U) -#define DP83848_PCSR_SD_OPTION_SET(x) (((uint16_t)(x) << DP83848_PCSR_SD_OPTION_SHIFT) & DP83848_PCSR_SD_OPTION_MASK) -#define DP83848_PCSR_SD_OPTION_GET(x) (((uint16_t)(x) & DP83848_PCSR_SD_OPTION_MASK) >> DP83848_PCSR_SD_OPTION_SHIFT) - -/* - * DESC_TIME (RW) - * - * Descrambler Timeout: - * Increase the descrambler timeout. When set this should allow the device to receive larger - * packets (>9k bytes) without loss of synchronization. - * 1 = 2ms - * 0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e) - */ -#define DP83848_PCSR_DESC_TIME_MASK (0x80U) -#define DP83848_PCSR_DESC_TIME_SHIFT (7U) -#define DP83848_PCSR_DESC_TIME_SET(x) (((uint16_t)(x) << DP83848_PCSR_DESC_TIME_SHIFT) & DP83848_PCSR_DESC_TIME_MASK) -#define DP83848_PCSR_DESC_TIME_GET(x) (((uint16_t)(x) & DP83848_PCSR_DESC_TIME_MASK) >> DP83848_PCSR_DESC_TIME_SHIFT) - -/* - * FORCE_100_OK (RW) - * - * Force 100Mb/s Good Link: - * 1 = Forces 100Mb/s Good Link. - * 0 = Normal 100Mb/s operation. - */ -#define DP83848_PCSR_FORCE_100_OK_MASK (0x20U) -#define DP83848_PCSR_FORCE_100_OK_SHIFT (5U) -#define DP83848_PCSR_FORCE_100_OK_SET(x) (((uint16_t)(x) << DP83848_PCSR_FORCE_100_OK_SHIFT) & DP83848_PCSR_FORCE_100_OK_MASK) -#define DP83848_PCSR_FORCE_100_OK_GET(x) (((uint16_t)(x) & DP83848_PCSR_FORCE_100_OK_MASK) >> DP83848_PCSR_FORCE_100_OK_SHIFT) - -/* - * NRZI_BYPASS (RW) - * - * NRZI Bypass Enable: - * 1 = NRZI Bypass Enabled. - * 0 = NRZI Bypass Disabled. - */ -#define DP83848_PCSR_NRZI_BYPASS_MASK (0x4U) -#define DP83848_PCSR_NRZI_BYPASS_SHIFT (2U) -#define DP83848_PCSR_NRZI_BYPASS_SET(x) (((uint16_t)(x) << DP83848_PCSR_NRZI_BYPASS_SHIFT) & DP83848_PCSR_NRZI_BYPASS_MASK) -#define DP83848_PCSR_NRZI_BYPASS_GET(x) (((uint16_t)(x) & DP83848_PCSR_NRZI_BYPASS_MASK) >> DP83848_PCSR_NRZI_BYPASS_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RMII_MODE (RW) - * - * Reduced MII Mode: - * 0 = Standard MII Mode - * 1 = Reduced MII Mode - */ -#define DP83848_RBR_RMII_MODE_MASK (0x20U) -#define DP83848_RBR_RMII_MODE_SHIFT (5U) -#define DP83848_RBR_RMII_MODE_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_MODE_SHIFT) & DP83848_RBR_RMII_MODE_MASK) -#define DP83848_RBR_RMII_MODE_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_MODE_MASK) >> DP83848_RBR_RMII_MODE_SHIFT) - -/* - * RMII_REV1_0 (RW) - * - * Reduce MII Revision 1.0: - * 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of - * CRS. - * 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV - * will not toggle at the end of a packet. - */ -#define DP83848_RBR_RMII_REV1_0_MASK (0x10U) -#define DP83848_RBR_RMII_REV1_0_SHIFT (4U) -#define DP83848_RBR_RMII_REV1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_RMII_REV1_0_SHIFT) & DP83848_RBR_RMII_REV1_0_MASK) -#define DP83848_RBR_RMII_REV1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_RMII_REV1_0_MASK) >> DP83848_RBR_RMII_REV1_0_SHIFT) - -/* - * RX_OVF_STS (RO) - * - * RX FIFO Over Flow Status: - * 0 = Normal - * 1 = Overflow detected - */ -#define DP83848_RBR_RX_OVF_STS_MASK (0x8U) -#define DP83848_RBR_RX_OVF_STS_SHIFT (3U) -#define DP83848_RBR_RX_OVF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_OVF_STS_MASK) >> DP83848_RBR_RX_OVF_STS_SHIFT) - -/* - * RX_UNF_STS (RO) - * - * RX FIFO Under Flow Status: - * 0 = Normal - * 1 = Underflow detected - */ -#define DP83848_RBR_RX_UNF_STS_MASK (0x4U) -#define DP83848_RBR_RX_UNF_STS_SHIFT (2U) -#define DP83848_RBR_RX_UNF_STS_GET(x) (((uint16_t)(x) & DP83848_RBR_RX_UNF_STS_MASK) >> DP83848_RBR_RX_UNF_STS_SHIFT) - -/* - * ELAST_BUF_1_0 (RW) - * - * Receive Elasticity Buffer. This field controls the Receive Elasticity Buffer which allows for - * frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The - * following value indicate the tolerance in bits for a single packet. The minimum setting allows - * for standard Ethernet frame sizes at ±50 ppm accuracy for both RMII and Receive clocks. For - * greater frequency tolerance the packet lengths may be scaled (that is, for ±100 ppm, the - * packet lengths need to be divided by 2). - * 00 = 14 bit tolerance (up to 16800 byte packets) - * 01 = 2 bit tolerance (up to 2400 byte packets) - * 10 = 6 bit tolerance (up to 7200 byte packets) - * 11 = 10 bit tolerance (up to 12000 byte packets) - */ -#define DP83848_RBR_ELAST_BUF_1_0_MASK (0x3U) -#define DP83848_RBR_ELAST_BUF_1_0_SHIFT (0U) -#define DP83848_RBR_ELAST_BUF_1_0_SET(x) (((uint16_t)(x) << DP83848_RBR_ELAST_BUF_1_0_SHIFT) & DP83848_RBR_ELAST_BUF_1_0_MASK) -#define DP83848_RBR_ELAST_BUF_1_0_GET(x) (((uint16_t)(x) & DP83848_RBR_ELAST_BUF_1_0_MASK) >> DP83848_RBR_ELAST_BUF_1_0_SHIFT) - -/* Bitfield definition for register: LEDCR */ -/* - * DRV_SPDLED (RW) - * - * 1 = Drive value of SPDLED bit onto LED_SPEED output - * 0 = Normal operation - */ -#define DP83848_LEDCR_DRV_SPDLED_MASK (0x20U) -#define DP83848_LEDCR_DRV_SPDLED_SHIFT (5U) -#define DP83848_LEDCR_DRV_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_SPDLED_SHIFT) & DP83848_LEDCR_DRV_SPDLED_MASK) -#define DP83848_LEDCR_DRV_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_SPDLED_MASK) >> DP83848_LEDCR_DRV_SPDLED_SHIFT) - -/* - * DRV_LNKLED (RW) - * - * 1 = Drive value of LNKLED bit onto LED_LINK output - * 0 = Normal operation - */ -#define DP83848_LEDCR_DRV_LNKLED_MASK (0x10U) -#define DP83848_LEDCR_DRV_LNKLED_SHIFT (4U) -#define DP83848_LEDCR_DRV_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_DRV_LNKLED_SHIFT) & DP83848_LEDCR_DRV_LNKLED_MASK) -#define DP83848_LEDCR_DRV_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_DRV_LNKLED_MASK) >> DP83848_LEDCR_DRV_LNKLED_SHIFT) - -/* - * SPDLED (RW) - * - * Value to force on LED_SPEED output - */ -#define DP83848_LEDCR_SPDLED_MASK (0x4U) -#define DP83848_LEDCR_SPDLED_SHIFT (2U) -#define DP83848_LEDCR_SPDLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_SPDLED_SHIFT) & DP83848_LEDCR_SPDLED_MASK) -#define DP83848_LEDCR_SPDLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_SPDLED_MASK) >> DP83848_LEDCR_SPDLED_SHIFT) - -/* - * LNKLED (RW) - * - * Value to force on LED_LINK output - */ -#define DP83848_LEDCR_LNKLED_MASK (0x2U) -#define DP83848_LEDCR_LNKLED_SHIFT (1U) -#define DP83848_LEDCR_LNKLED_SET(x) (((uint16_t)(x) << DP83848_LEDCR_LNKLED_SHIFT) & DP83848_LEDCR_LNKLED_MASK) -#define DP83848_LEDCR_LNKLED_GET(x) (((uint16_t)(x) & DP83848_LEDCR_LNKLED_MASK) >> DP83848_LEDCR_LNKLED_SHIFT) - -/* Bitfield definition for register: PHYCR */ -/* - * MDIX_EN (RW) - * - * Auto-MDIX Enable: - * 1 = Enable Auto-neg Auto-MDIX capability. - * 0 = Disable Auto-neg Auto-MDIX capability. - * The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit in the BMCR register - * to be set. If Auto-Negotiation is not enabled, Auto-MDIX should be disabled as well. - */ -#define DP83848_PHYCR_MDIX_EN_MASK (0x8000U) -#define DP83848_PHYCR_MDIX_EN_SHIFT (15U) -#define DP83848_PHYCR_MDIX_EN_SET(x) (((uint16_t)(x) << DP83848_PHYCR_MDIX_EN_SHIFT) & DP83848_PHYCR_MDIX_EN_MASK) -#define DP83848_PHYCR_MDIX_EN_GET(x) (((uint16_t)(x) & DP83848_PHYCR_MDIX_EN_MASK) >> DP83848_PHYCR_MDIX_EN_SHIFT) - -/* - * FORCE_MDIX (RW) - * - * Force MDIX: - * 1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair) - * 0 = Normal operation. - */ -#define DP83848_PHYCR_FORCE_MDIX_MASK (0x4000U) -#define DP83848_PHYCR_FORCE_MDIX_SHIFT (14U) -#define DP83848_PHYCR_FORCE_MDIX_SET(x) (((uint16_t)(x) << DP83848_PHYCR_FORCE_MDIX_SHIFT) & DP83848_PHYCR_FORCE_MDIX_MASK) -#define DP83848_PHYCR_FORCE_MDIX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_FORCE_MDIX_MASK) >> DP83848_PHYCR_FORCE_MDIX_SHIFT) - -/* - * PAUSE_RX (RO) - * - * Pause Receive Negotiated: - * Indicates that pause receive should be enabled in the MAC. Based on ANAR[11:10] and - * ANLPAR[11:10] settings. - * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause - * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex - * technology. - */ -#define DP83848_PHYCR_PAUSE_RX_MASK (0x2000U) -#define DP83848_PHYCR_PAUSE_RX_SHIFT (13U) -#define DP83848_PHYCR_PAUSE_RX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_RX_MASK) >> DP83848_PHYCR_PAUSE_RX_SHIFT) - -/* - * PAUSE_TX (RO) - * - * Pause Transmit Negotiated: - * Indicates that pause transmit should be enabled in the MAC. Based on ANAR[11:10] and - * ANLPAR[11:10] settings. - * This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause - * Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex - * technology. - */ -#define DP83848_PHYCR_PAUSE_TX_MASK (0x1000U) -#define DP83848_PHYCR_PAUSE_TX_SHIFT (12U) -#define DP83848_PHYCR_PAUSE_TX_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PAUSE_TX_MASK) >> DP83848_PHYCR_PAUSE_TX_SHIFT) - -/* - * BIST_FE (RW) - * - * BIST Force Error: - * 1 = Force BIST Error. - * 0 = Normal operation. - * This bit forces a single error, and is self clearing. - */ -#define DP83848_PHYCR_BIST_FE_MASK (0x800U) -#define DP83848_PHYCR_BIST_FE_SHIFT (11U) -#define DP83848_PHYCR_BIST_FE_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_FE_SHIFT) & DP83848_PHYCR_BIST_FE_MASK) -#define DP83848_PHYCR_BIST_FE_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_FE_MASK) >> DP83848_PHYCR_BIST_FE_SHIFT) - -/* - * PSR_15 (RW) - * - * BIST Sequence select: - * 1 = PSR15 selected. - * 0 = PSR9 selected. - */ -#define DP83848_PHYCR_PSR_15_MASK (0x400U) -#define DP83848_PHYCR_PSR_15_SHIFT (10U) -#define DP83848_PHYCR_PSR_15_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PSR_15_SHIFT) & DP83848_PHYCR_PSR_15_MASK) -#define DP83848_PHYCR_PSR_15_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PSR_15_MASK) >> DP83848_PHYCR_PSR_15_SHIFT) - -/* - * BIST_STATUS (RO) - * - * BIST Test Status: - * 1 = BIST pass. - * 0 = BIST fail. Latched, cleared when BIST is stopped. - * For a count number of BIST errors, see the BIST Error Count in the CDCTRL1 register. - */ -#define DP83848_PHYCR_BIST_STATUS_MASK (0x200U) -#define DP83848_PHYCR_BIST_STATUS_SHIFT (9U) -#define DP83848_PHYCR_BIST_STATUS_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_STATUS_MASK) >> DP83848_PHYCR_BIST_STATUS_SHIFT) - -/* - * BIST_START (RW) - * - * BIST Start: - * 1 = BIST start. - * 0 = BIST stop. - */ -#define DP83848_PHYCR_BIST_START_MASK (0x100U) -#define DP83848_PHYCR_BIST_START_SHIFT (8U) -#define DP83848_PHYCR_BIST_START_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BIST_START_SHIFT) & DP83848_PHYCR_BIST_START_MASK) -#define DP83848_PHYCR_BIST_START_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BIST_START_MASK) >> DP83848_PHYCR_BIST_START_SHIFT) - -/* - * BP_STRETCH (RW) - * - * Bypass LED Stretching: - * This will bypass the LED stretching and the LEDs will reflect the internal value. - * 1 = Bypass LED stretching. - * 0 = Normal operation. - */ -#define DP83848_PHYCR_BP_STRETCH_MASK (0x80U) -#define DP83848_PHYCR_BP_STRETCH_SHIFT (7U) -#define DP83848_PHYCR_BP_STRETCH_SET(x) (((uint16_t)(x) << DP83848_PHYCR_BP_STRETCH_SHIFT) & DP83848_PHYCR_BP_STRETCH_MASK) -#define DP83848_PHYCR_BP_STRETCH_GET(x) (((uint16_t)(x) & DP83848_PHYCR_BP_STRETCH_MASK) >> DP83848_PHYCR_BP_STRETCH_SHIFT) - -/* - * LED_CNFG_0 (RW) - * - * LED Configuration - * LED_ CNFG[0] Mode Description - * 1 Mode 1 - * 0 Mode2 - * In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link - * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s - * In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity - * LED_SPEED = ON in 100Mb/s, OFF in 10Mb/s - */ -#define DP83848_PHYCR_LED_CNFG_0_MASK (0x20U) -#define DP83848_PHYCR_LED_CNFG_0_SHIFT (5U) -#define DP83848_PHYCR_LED_CNFG_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_LED_CNFG_0_SHIFT) & DP83848_PHYCR_LED_CNFG_0_MASK) -#define DP83848_PHYCR_LED_CNFG_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_LED_CNFG_0_MASK) >> DP83848_PHYCR_LED_CNFG_0_SHIFT) - -/* - * PHYADDR_4_0 (RW) - * - * PHY Address: PHY address for port. - */ -#define DP83848_PHYCR_PHYADDR_4_0_MASK (0x1FU) -#define DP83848_PHYCR_PHYADDR_4_0_SHIFT (0U) -#define DP83848_PHYCR_PHYADDR_4_0_SET(x) (((uint16_t)(x) << DP83848_PHYCR_PHYADDR_4_0_SHIFT) & DP83848_PHYCR_PHYADDR_4_0_MASK) -#define DP83848_PHYCR_PHYADDR_4_0_GET(x) (((uint16_t)(x) & DP83848_PHYCR_PHYADDR_4_0_MASK) >> DP83848_PHYCR_PHYADDR_4_0_SHIFT) - -/* Bitfield definition for register: 10BTSCR */ -/* - * SQUELCH (RW) - * - * Squelch Configuration: - * Used to set the Squelch ‘ON’ threshold for the receiver. - * Default Squelch ON is 330-mV peak. - */ -#define DP83848_10BTSCR_SQUELCH_MASK (0xE00U) -#define DP83848_10BTSCR_SQUELCH_SHIFT (9U) -#define DP83848_10BTSCR_SQUELCH_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_SQUELCH_SHIFT) & DP83848_10BTSCR_SQUELCH_MASK) -#define DP83848_10BTSCR_SQUELCH_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_SQUELCH_MASK) >> DP83848_10BTSCR_SQUELCH_SHIFT) - -/* - * LOOPBACK_10_DIS (RW) - * - * In half-duplex mode, default 10BASE-T operation loops Transmit data to the Receive data - * in addition to transmitting the data on the physical medium. This is for consistency with - * earlier 10BASE2 and 10BASE5 implementations which used a shared medium. Setting - * this bit disables the loopback function. - * This bit does not affect loopback due to setting BMCR[14]. - */ -#define DP83848_10BTSCR_LOOPBACK_10_DIS_MASK (0x100U) -#define DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT (8U) -#define DP83848_10BTSCR_LOOPBACK_10_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) -#define DP83848_10BTSCR_LOOPBACK_10_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LOOPBACK_10_DIS_MASK) >> DP83848_10BTSCR_LOOPBACK_10_DIS_SHIFT) - -/* - * LP_DIS (RW) - * - * Normal Link Pulse Disable: - * 1 = Transmission of NLPs is disabled. - * 0 = Transmission of NLPs is enabled. - */ -#define DP83848_10BTSCR_LP_DIS_MASK (0x80U) -#define DP83848_10BTSCR_LP_DIS_SHIFT (7U) -#define DP83848_10BTSCR_LP_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_LP_DIS_SHIFT) & DP83848_10BTSCR_LP_DIS_MASK) -#define DP83848_10BTSCR_LP_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_LP_DIS_MASK) >> DP83848_10BTSCR_LP_DIS_SHIFT) - -/* - * FORCE_LINK_10 (RW) - * - * Force 10Mb Good Link: - * 1 = Forced Good 10 Mb Link. - * 0 = Normal Link Status. - */ -#define DP83848_10BTSCR_FORCE_LINK_10_MASK (0x40U) -#define DP83848_10BTSCR_FORCE_LINK_10_SHIFT (6U) -#define DP83848_10BTSCR_FORCE_LINK_10_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_FORCE_LINK_10_SHIFT) & DP83848_10BTSCR_FORCE_LINK_10_MASK) -#define DP83848_10BTSCR_FORCE_LINK_10_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_FORCE_LINK_10_MASK) >> DP83848_10BTSCR_FORCE_LINK_10_SHIFT) - -/* - * POLARITY (RO) - * - * 10Mb Polarity Status: - * This bit is a duplication of bit 12 in the PHYSTS register. Both bits will be cleared upon a - * read of 10BTSCR register, but not upon a read of the PHYSTS register. - * 1 = Inverted Polarity detected. - * 0 = Correct Polarity detected. - */ -#define DP83848_10BTSCR_POLARITY_MASK (0x10U) -#define DP83848_10BTSCR_POLARITY_SHIFT (4U) -#define DP83848_10BTSCR_POLARITY_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_POLARITY_MASK) >> DP83848_10BTSCR_POLARITY_SHIFT) - -/* - * HEARTBEAT_DIS (RW) - * - * Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. - * 1 = Heartbeat function disabled. - * 0 = Heartbeat function enabled. - * When the device is operating at 100 Mb or configured for full duplex operation, this - * bit will be ignored - the heartbeat function is disabled. - */ -#define DP83848_10BTSCR_HEARTBEAT_DIS_MASK (0x2U) -#define DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT (1U) -#define DP83848_10BTSCR_HEARTBEAT_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) -#define DP83848_10BTSCR_HEARTBEAT_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_HEARTBEAT_DIS_MASK) >> DP83848_10BTSCR_HEARTBEAT_DIS_SHIFT) - -/* - * JABBER_DIS (RW) - * - * Jabber Disable: - * Applicable only in 10BASE-T. - * 1 = Jabber function disabled. - * 0 = Jabber function enabled. - */ -#define DP83848_10BTSCR_JABBER_DIS_MASK (0x1U) -#define DP83848_10BTSCR_JABBER_DIS_SHIFT (0U) -#define DP83848_10BTSCR_JABBER_DIS_SET(x) (((uint16_t)(x) << DP83848_10BTSCR_JABBER_DIS_SHIFT) & DP83848_10BTSCR_JABBER_DIS_MASK) -#define DP83848_10BTSCR_JABBER_DIS_GET(x) (((uint16_t)(x) & DP83848_10BTSCR_JABBER_DIS_MASK) >> DP83848_10BTSCR_JABBER_DIS_SHIFT) - -/* Bitfield definition for register: CDCTRL1 */ -/* - * BIST_ERROR_COUNT (RO) - * - * BIST ERROR Counter: - * Counts number of errored data nibbles during Packet BIST. This value will reset when - * Packet BIST is restarted. The counter sticks when it reaches its max count. - */ -#define DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK (0xFF00U) -#define DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT (8U) -#define DP83848_CDCTRL1_BIST_ERROR_COUNT_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_ERROR_COUNT_MASK) >> DP83848_CDCTRL1_BIST_ERROR_COUNT_SHIFT) - -/* - * BIST_CONT_MODE (RW) - * - * Packet BIST Continuous Mode: - * Allows continuous pseudo random data transmission without any break in transmission. This - * can be used for transmit VOD testing. This is used in conjunction with the BIST controls in - * the PHYCR Register (0x19h). For 10 Mb operation, jabber function must be disabled, bit 0 of - * the 10BTSCR (0x1Ah), JABBER_DIS = 1. - */ -#define DP83848_CDCTRL1_BIST_CONT_MODE_MASK (0x20U) -#define DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT (5U) -#define DP83848_CDCTRL1_BIST_CONT_MODE_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) -#define DP83848_CDCTRL1_BIST_CONT_MODE_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_BIST_CONT_MODE_MASK) >> DP83848_CDCTRL1_BIST_CONT_MODE_SHIFT) - -/* - * CDPATTEN_10 (RW) - * - * CD Pattern Enable for 10Mb: - * 1 = Enabled. - * 0 = Disabled. - */ -#define DP83848_CDCTRL1_CDPATTEN_10_MASK (0x10U) -#define DP83848_CDCTRL1_CDPATTEN_10_SHIFT (4U) -#define DP83848_CDCTRL1_CDPATTEN_10_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTEN_10_SHIFT) & DP83848_CDCTRL1_CDPATTEN_10_MASK) -#define DP83848_CDCTRL1_CDPATTEN_10_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTEN_10_MASK) >> DP83848_CDCTRL1_CDPATTEN_10_SHIFT) - -/* - * 10MEG_PATT_GAP ( RW) - * - * Defines gap between data or NLP test sequences: - * 1 = 15 µs. - * 0 = 10 µs. - */ -#define DP83848_CDCTRL1_10MEG_PATT_GAP_MASK (0x4U) -#define DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT (2U) -#define DP83848_CDCTRL1_10MEG_PATT_GAP_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) -#define DP83848_CDCTRL1_10MEG_PATT_GAP_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_10MEG_PATT_GAP_MASK) >> DP83848_CDCTRL1_10MEG_PATT_GAP_SHIFT) - -/* - * CDPATTSEL_1_0 (RW) - * - * CD Pattern Select[1:0]: - * If CDPATTEN_10 = 1: - * 00 = Data, EOP0 sequence - * 01 = Data, EOP1 sequence - * 10 = NLPs - * 11 = Constant Manchester 1 s (10-MHz sine wave) for harmonic distortion testing. - */ -#define DP83848_CDCTRL1_CDPATTSEL_1_0_MASK (0x3U) -#define DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT (0U) -#define DP83848_CDCTRL1_CDPATTSEL_1_0_SET(x) (((uint16_t)(x) << DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) -#define DP83848_CDCTRL1_CDPATTSEL_1_0_GET(x) (((uint16_t)(x) & DP83848_CDCTRL1_CDPATTSEL_1_0_MASK) >> DP83848_CDCTRL1_CDPATTSEL_1_0_SHIFT) - -/* Bitfield definition for register: EDCR */ -/* - * ED_EN (RW) - * - * Energy Detect Enable: - * Allow Energy Detect Mode. - * When Energy Detect is enabled and Auto-Negotiation is disabled through the BMCR - * register, Auto-MDIX should be disabled through the PHYCR register. - */ -#define DP83848_EDCR_ED_EN_MASK (0x8000U) -#define DP83848_EDCR_ED_EN_SHIFT (15U) -#define DP83848_EDCR_ED_EN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_EN_SHIFT) & DP83848_EDCR_ED_EN_MASK) -#define DP83848_EDCR_ED_EN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_EN_MASK) >> DP83848_EDCR_ED_EN_SHIFT) - -/* - * ED_AUTO_UP (RW) - * - * Energy Detect Automatic Power Up: - * Automatically begin power-up sequence when Energy Detect Data Threshold value - * (EDCR[3:0]) is reached. Alternatively, device could be powered up manually using the - * ED_MAN bit (ECDR[12]). - */ -#define DP83848_EDCR_ED_AUTO_UP_MASK (0x4000U) -#define DP83848_EDCR_ED_AUTO_UP_SHIFT (14U) -#define DP83848_EDCR_ED_AUTO_UP_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_UP_SHIFT) & DP83848_EDCR_ED_AUTO_UP_MASK) -#define DP83848_EDCR_ED_AUTO_UP_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_UP_MASK) >> DP83848_EDCR_ED_AUTO_UP_SHIFT) - -/* - * ED_AUTO_DOWN (RW) - * - * Energy Detect Automatic Power Down: - * Automatically begin power-down sequence when no energy is detected. Alternatively, - * device could be powered down using the ED_MAN bit (EDCR[12]). - */ -#define DP83848_EDCR_ED_AUTO_DOWN_MASK (0x2000U) -#define DP83848_EDCR_ED_AUTO_DOWN_SHIFT (13U) -#define DP83848_EDCR_ED_AUTO_DOWN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_AUTO_DOWN_SHIFT) & DP83848_EDCR_ED_AUTO_DOWN_MASK) -#define DP83848_EDCR_ED_AUTO_DOWN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_AUTO_DOWN_MASK) >> DP83848_EDCR_ED_AUTO_DOWN_SHIFT) - -/* - * ED_MAN (RW) - * - * Energy Detect Manual Power Up/Down: - * Begin power-up/down sequence when this bit is asserted. When set, the Energy Detect - * algorithm will initiate a change of Energy Detect state regardless of threshold (error or - * data) and timer values. - */ -#define DP83848_EDCR_ED_MAN_MASK (0x1000U) -#define DP83848_EDCR_ED_MAN_SHIFT (12U) -#define DP83848_EDCR_ED_MAN_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_MAN_SHIFT) & DP83848_EDCR_ED_MAN_MASK) -#define DP83848_EDCR_ED_MAN_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_MAN_MASK) >> DP83848_EDCR_ED_MAN_SHIFT) - -/* - * ED_BURST_DIS (RW) - * - * Energy Detect Bust Disable: - * Disable bursting of energy detect data pulses. By default, Energy Detect (ED) transmits - * a burst of 4 ED data pulses each time the CD is powered up. When bursting is - * disabled, only a single ED data pulse will be send each time the CD is powered up. - */ -#define DP83848_EDCR_ED_BURST_DIS_MASK (0x800U) -#define DP83848_EDCR_ED_BURST_DIS_SHIFT (11U) -#define DP83848_EDCR_ED_BURST_DIS_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_BURST_DIS_SHIFT) & DP83848_EDCR_ED_BURST_DIS_MASK) -#define DP83848_EDCR_ED_BURST_DIS_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_BURST_DIS_MASK) >> DP83848_EDCR_ED_BURST_DIS_SHIFT) - -/* - * ED_PWR_STATE (RO) - * - * Energy Detect Power State: - * Indicates current Energy Detect Power state. When set, Energy Detect is in the - * powered up state. When cleared, Energy Detect is in the powered down state. This bit - * is invalid when Energy Detect is not enabled. - */ -#define DP83848_EDCR_ED_PWR_STATE_MASK (0x400U) -#define DP83848_EDCR_ED_PWR_STATE_SHIFT (10U) -#define DP83848_EDCR_ED_PWR_STATE_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_PWR_STATE_MASK) >> DP83848_EDCR_ED_PWR_STATE_SHIFT) - -/* - * ED_ERR_MET (RO) - * - * Energy Detect Error Threshold Met: - * No action is automatically taken upon receipt of error events. This bit is informational - * only and would be cleared on a read. - */ -#define DP83848_EDCR_ED_ERR_MET_MASK (0x200U) -#define DP83848_EDCR_ED_ERR_MET_SHIFT (9U) -#define DP83848_EDCR_ED_ERR_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_MET_MASK) >> DP83848_EDCR_ED_ERR_MET_SHIFT) - -/* - * ED_DATA_MET (RO) - * - * Energy Detect Data Threshold Met: - * The number of data events that occurred met or surpassed the Energy Detect Data - * Threshold. This bit is cleared on a read. - */ -#define DP83848_EDCR_ED_DATA_MET_MASK (0x100U) -#define DP83848_EDCR_ED_DATA_MET_SHIFT (8U) -#define DP83848_EDCR_ED_DATA_MET_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_MET_MASK) >> DP83848_EDCR_ED_DATA_MET_SHIFT) - -/* - * ED_ERR_COUNT (RW) - * - * Energy Detect Error Threshold: - * Threshold to determine the number of energy detect error events that should cause the - * device to take action. Intended to allow averaging of noise that may be on the line. - * Counter will reset after approximately 2 seconds without any energy detect data - * events. - */ -#define DP83848_EDCR_ED_ERR_COUNT_MASK (0xF0U) -#define DP83848_EDCR_ED_ERR_COUNT_SHIFT (4U) -#define DP83848_EDCR_ED_ERR_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_ERR_COUNT_SHIFT) & DP83848_EDCR_ED_ERR_COUNT_MASK) -#define DP83848_EDCR_ED_ERR_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_ERR_COUNT_MASK) >> DP83848_EDCR_ED_ERR_COUNT_SHIFT) - -/* - * ED_DATA_COUNT (RW) - * - * Energy Detect Data Threshold: - * Threshold to determine the number of energy detect events that should cause the - * device to take actions. Intended to allow averaging of noise that may be on the line. - * Counter will reset after approximately 2 seconds without any energy detect data - * events. - */ -#define DP83848_EDCR_ED_DATA_COUNT_MASK (0xFU) -#define DP83848_EDCR_ED_DATA_COUNT_SHIFT (0U) -#define DP83848_EDCR_ED_DATA_COUNT_SET(x) (((uint16_t)(x) << DP83848_EDCR_ED_DATA_COUNT_SHIFT) & DP83848_EDCR_ED_DATA_COUNT_MASK) -#define DP83848_EDCR_ED_DATA_COUNT_GET(x) (((uint16_t)(x) & DP83848_EDCR_ED_DATA_COUNT_MASK) >> DP83848_EDCR_ED_DATA_COUNT_SHIFT) - - - - -#endif /* HPM_DP83848_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c deleted file mode 100644 index 97c069326de..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_dp83867_regs.h" -#include "hpm_dp83867.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -bool dp83867_check_id(ENET_Type *ptr) -{ - uint16_t id1, id2; - - id1 = enet_read_phy(ptr, DP83867_ADDR, DP83867_PHYIDR1); - id2 = enet_read_phy(ptr, DP83867_ADDR, DP83867_PHYIDR2); - - if (DP83867_PHYIDR1_OUI_MSB_GET(id1) == DP83867_ID1 && DP83867_PHYIDR2_OUI_LSB_GET(id2) == DP83867_ID2) { - return true; - } else { - return false; - } -} - -static void dp83867_write_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) -{ - /* set the control register for register address */ - enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_SET(0x1f)); - - /* write the specified register address */ - enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); - - /* set the control register for register data */ - enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_SET(0x1f)); - - /* write the specified register data */ - enet_write_phy(ptr, phy_addr, DP83867_ADDAR, data); -} - -static uint16_t dp83867_read_phy_ext(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) -{ - /* set the control register for register address */ - enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(0) | DP83867_REGCR_DEVAD_SET(0x1f)); - - /* write the specified register address */ - enet_write_phy(ptr, phy_addr, DP83867_ADDAR, addr); - - /* set the control register for register data */ - enet_write_phy(ptr, phy_addr, DP83867_REGCR, DP83867_REGCR_FUNCTION_SET(1) | DP83867_REGCR_DEVAD_SET(0x1f)); - - /* read the specified register data */ - return enet_read_phy(ptr, phy_addr, DP83867_ADDAR); -} -/*--------------------------------------------------------------------- - * API - *--------------------------------------------------------------------- - */ -void dp83867_reset(ENET_Type *ptr) -{ - uint16_t data; - - /* PHY reset */ - enet_write_phy(ptr, DP83867_ADDR, DP83867_BMCR, DP83867_BMCR_RESET_SET(1)); - - /* wait until the reset is completed */ - do { - data = enet_read_phy(ptr, DP83867_ADDR, DP83867_BMCR); - } while (DP83867_BMCR_RESET_GET(data)); -} - -void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config) -{ - (void)ptr; - - config->loopback = false; /* Disable PCS loopback mode */ - #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) - config->auto_negotiation = false; /* Disable Auto-Negotiation */ - config->speed = enet_phy_port_speed_100mbps; - config->duplex = enet_phy_duplex_full; - #else - config->auto_negotiation = true; /* Enable Auto-Negotiation */ - #endif -} - -bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config) -{ - uint16_t data = 0; - - data |= DP83867_BMCR_RESET_SET(0) /* Normal operation */ - | DP83867_BMCR_LOOPBACK_SET(config->loopback) /* Configure PCS loopback mode */ - | DP83867_BMCR_ANE_SET(config->auto_negotiation) /* Configure Auto-Negotiation */ - | DP83867_BMCR_PWD_SET(0) /* Normal operation */ - | DP83867_BMCR_ISOLATE_SET(0) /* Normal operation */ - | DP83867_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | DP83867_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - - if (config->auto_negotiation == false) { - data |= DP83867_BMCR_SPEED0_SET(config->speed) | DP83867_BMCR_SPEED1_SET(config->speed >> 1); /* Set port speed */ - data |= DP83867_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ - } - - /* check the id of dp83867 */ - if (dp83867_check_id(ptr) == false) { - return false; - } - - enet_write_phy(ptr, DP83867_ADDR, DP83867_BMCR, data); - data = enet_read_phy(ptr, DP83867_ADDR, DP83867_BMCR); - - return true; -} - -void dp83867_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) -{ - uint16_t data; - - data = enet_read_phy(ptr, DP83867_ADDR, DP83867_PHYSTS); - status->enet_phy_link = DP83867_PHYSTS_LINK_STATUS_GET(data); - status->enet_phy_speed = DP83867_PHYSTS_SPEED_SELECTION_GET(data) == 0 ? enet_phy_port_speed_10mbps : DP83867_PHYSTS_SPEED_SELECTION_GET(data) == 1 ? enet_phy_port_speed_100mbps : enet_phy_port_speed_1000mbps; - status->enet_phy_duplex = DP83867_PHYSTS_DUPLEX_MODE_GET(data); -} - -void dp83867_set_mdi_crossover_mode(ENET_Type *ptr, enet_phy_crossover_mode_t mode) -{ - uint16_t data; - - data = dp83867_read_phy_ext(ptr, DP83867_ADDR, DP83867_PHYCR); - data &= ~DP83867_PHYCR_MDI_CROSSOVER_MASK; - data |= DP83867_PHYCR_MDI_CROSSOVER_SET(mode); - dp83867_write_phy_ext(ptr, DP83867_ADDR, DP83867_PHYCR, data); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h deleted file mode 100644 index 14950e468f5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DP83867_H -#define HPM_DP83867_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_phy.h" -#include "hpm_common.h" -#include "hpm_enet_regs.h" -/*--------------------------------------------------------------------- - * Macro Const Definitions - *--------------------------------------------------------------------- - */ -#ifndef DP83867_ADDR -#define DP83867_ADDR (0U) -#endif - -#define DP83867_ID1 (0x2000U) -#define DP83867_ID2 (0x28U) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -typedef struct { - bool loopback; - uint8_t speed; - bool auto_negotiation; - uint8_t duplex; -} dp83867_config_t; - -typedef enum { - DP83867_RX_DELAY_0P25_NS = 0, - DP83867_RX_DELAY_0P50_NS, - DP83867_RX_DELAY_0P75_NS, - DP83867_RX_DELAY_1P00_NS, - DP83867_RX_DELAY_1P25_NS, - DP83867_RX_DELAY_1P50_NS, - DP83867_RX_DELAY_1P75_NS, - DP83867_RX_DELAY_2P00_NS, - DP83867_RX_DELAY_2P25_NS, - DP83867_RX_DELAY_2P50_NS, - DP83867_RX_DELAY_2P75_NS, - DP83867_RX_DELAY_3P00_NS, - DP83867_RX_DELAY_3P25_NS, - DP83867_RX_DELAY_3P50_NS, - DP83867_RX_DELAY_3P75_NS, - DP83867_RX_DELAY_4P00_NS -} dp83867_rgmii_rx_delay_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -void dp83867_reset(ENET_Type *ptr); -void dp83867_basic_mode_default_config(ENET_Type *ptr, dp83867_config_t *config); -bool dp83867_basic_mode_init(ENET_Type *ptr, dp83867_config_t *config); -void dp83867_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); -void dp83867_set_mdi_crossover_mode(ENET_Type *ptr, enet_phy_crossover_mode_t mode); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_DP83867_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h deleted file mode 100644 index 52a6e8a319d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/dp83867/hpm_dp83867_regs.h +++ /dev/null @@ -1,2488 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DP83867_REGS_H -#define HPM_DP83867_REGS_H - -typedef enum { - DP83867_BMCR = 0, /* 0x0: Basic Mode Control Register */ - DP83867_BMSR = 1, /* 0x1: Basic Mode Status Register */ - DP83867_PHYIDR1 = 2, /* 0x2: PHY Identifier Register #1 */ - DP83867_PHYIDR2 = 3, /* 0x3: PHY Identifier Register #2 */ - DP83867_ANAR = 4, /* 0x4: MII Interrupt Control Register */ - DP83867_ANLPAR = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ - DP83867_ANER = 6, /* 0x6: Auto-Negotiate Expansion Register */ - DP83867_ANNPTR = 7, /* 0x7: Auto-Negotiation Next Page Transmit Register */ - DP83867_ANNPRR = 8, /* 0x8: Auto-Negotiation Next Page Receive Register */ - DP83867_CFG1 = 9, /* 0x9: Configuration Register 1 */ - DP83867_STS1 = 10, /* 0xA: Status Register 1 */ - DP83867_REGCR = 13, /* 0xD: Register Control Register */ - DP83867_ADDAR = 14, /* 0xE: Address or Data Register */ - DP83867_1KSCR = 15, /* 0xF: 1000BASE-T Status Register */ - DP83867_PHYCR = 16, /* 0x10: PHY Control Register */ - DP83867_PHYSTS = 17, /* 0x11: PHY Status Register */ - DP83867_MICR = 18, /* 0x12: MII Interrupt Control Register */ - DP83867_ISR = 19, /* 0x13: Interrupt Status Register */ - DP83867_CRG2 = 20, /* 0x14: Configuration Register 2 */ - DP83867_RECR = 21, /* 0x15: Receiver Error Counter Register */ - DP83867_STS2 = 23, /* 0x17: Status Register 2 */ - DP83867_LEDCR1 = 24, /* 0x18: LED Configuration Register 1 */ - DP83867_LEDCR2 = 25, /* 0x19: LED Configuration Register 2 */ - DP83867_LEDCR3 = 26, /* 0x1A: LED Configuration Register 3 */ - DP83867_CFG3 = 30, /* 0x1E: Configuration Register 3 */ - DP83867_CTRL = 31, /* 0x1F: Control Register */ - DP83867_RGMIIDCTL = 134, /* 0x86: RGMII Delay Control Register */ -} DP83867_REG_Type; - - -/* Bitfield definition for register: BMCR */ -/* - * RESET (RW/SC) - * - * Reset: - * 1 = Initiate software Reset / Reset in Process. - * 0 = Normal operation. - * This bit, which is self-clearing, returns a value of one until the reset - * process is complete. The configuration is restrapped. - */ -#define DP83867_BMCR_RESET_MASK (0x8000U) -#define DP83867_BMCR_RESET_SHIFT (15U) -#define DP83867_BMCR_RESET_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESET_SHIFT) & DP83867_BMCR_RESET_MASK) -#define DP83867_BMCR_RESET_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESET_MASK) >> DP83867_BMCR_RESET_SHIFT) - -/* - * LOOPBACK (RW) - * - * Loopback: - * 1 = Loopback enabled. - * 0 = Normal operation. - * The loopback function enables MAC transmit data to be routed to - * the MAC receive data path. - * Setting this bit may cause the descrambler to lose synchronization - * and produce a 500-µs dead time before any valid data will appear at - * the MII receive outputs. - */ -#define DP83867_BMCR_LOOPBACK_MASK (0x4000U) -#define DP83867_BMCR_LOOPBACK_SHIFT (14U) -#define DP83867_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << DP83867_BMCR_LOOPBACK_SHIFT) & DP83867_BMCR_LOOPBACK_MASK) -#define DP83867_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & DP83867_BMCR_LOOPBACK_MASK) >> DP83867_BMCR_LOOPBACK_SHIFT) - -/* - * SPEED0 (RW) - * - * Speed Select (Bits 6, 13): - * When auto-negotiation is disabled writing to this bit allows the port - * speed to be selected. - * 11 = Reserved - * 10 = 1000 Mbps - * 1 = 100 Mbps - * 0 = 10 Mbps - */ -#define DP83867_BMCR_SPEED0_MASK (0x2000U) -#define DP83867_BMCR_SPEED0_SHIFT (13U) -#define DP83867_BMCR_SPEED0_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED0_SHIFT) & DP83867_BMCR_SPEED0_MASK) -#define DP83867_BMCR_SPEED0_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED0_MASK) >> DP83867_BMCR_SPEED0_SHIFT) - -/* - * ANE (STRAP, RW) - * - * Auto-Negotiation Enable: - * Strap controls initial value at reset. - * 1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are - * ignored when this bit is set. - * 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port - * speed and duplex mode. - */ -#define DP83867_BMCR_ANE_MASK (0x1000U) -#define DP83867_BMCR_ANE_SHIFT (12U) -#define DP83867_BMCR_ANE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ANE_SHIFT) & DP83867_BMCR_ANE_MASK) -#define DP83867_BMCR_ANE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ANE_MASK) >> DP83867_BMCR_ANE_SHIFT) - -/* - * PWD (RW) - * - * Power Down: - * 1 = Power down. - * 0 = Normal operation. - * Setting this bit powers down the PHY. Only the register block is - * enabled during a power down condition. This bit is ORd with the - * input from the PWRDOWN_INT pin. When the active low - * PWRDOWN_INT pin is asserted, this bit will be set. - */ -#define DP83867_BMCR_PWD_MASK (0x800U) -#define DP83867_BMCR_PWD_SHIFT (11U) -#define DP83867_BMCR_PWD_SET(x) (((uint16_t)(x) << DP83867_BMCR_PWD_SHIFT) & DP83867_BMCR_PWD_MASK) -#define DP83867_BMCR_PWD_GET(x) (((uint16_t)(x) & DP83867_BMCR_PWD_MASK) >> DP83867_BMCR_PWD_SHIFT) - -/* - * ISOLATE (RW) - * - * Isolate: - * 1 = Isolates the Port from the MII with the exception of the serial - * management. - * 0 = Normal operation. - */ -#define DP83867_BMCR_ISOLATE_MASK (0x400U) -#define DP83867_BMCR_ISOLATE_SHIFT (10U) -#define DP83867_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << DP83867_BMCR_ISOLATE_SHIFT) & DP83867_BMCR_ISOLATE_MASK) -#define DP83867_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & DP83867_BMCR_ISOLATE_MASK) >> DP83867_BMCR_ISOLATE_SHIFT) - -/* - * RESTART_AN (RW/SC) - * - * Restart Auto-Negotiation: - * 1 = Restart Auto-Negotiation. Reinitiates the Auto-Negotiation - * process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is - * ignored. This bit is self-clearing and will return a value of 1 until - * Auto-Negotiation is initiated, whereupon it will self-clear. Operation of - * the Auto-Negotiation process is not affected by the management - * entity clearing this bit. - * 0 = Normal operation. - */ -#define DP83867_BMCR_RESTART_AN_MASK (0x200U) -#define DP83867_BMCR_RESTART_AN_SHIFT (9U) -#define DP83867_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << DP83867_BMCR_RESTART_AN_SHIFT) & DP83867_BMCR_RESTART_AN_MASK) -#define DP83867_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & DP83867_BMCR_RESTART_AN_MASK) >> DP83867_BMCR_RESTART_AN_SHIFT) - -/* - * DUPLEX (STRAP, RW) - * - * Duplex Mode: - * When auto-negotiation is disabled writing to this bit allows the port - * Duplex capability to be selected. - * 1 = Full Duplex operation. - * 0 = Half Duplex operation. - */ -#define DP83867_BMCR_DUPLEX_MASK (0x100U) -#define DP83867_BMCR_DUPLEX_SHIFT (8U) -#define DP83867_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_BMCR_DUPLEX_SHIFT) & DP83867_BMCR_DUPLEX_MASK) -#define DP83867_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMCR_DUPLEX_MASK) >> DP83867_BMCR_DUPLEX_SHIFT) - -/* - * COLLISION_TEST (RW) - * - * Collision Test: - * 1 = Collision test enabled. - * 0 = Normal operation. - * When set, this bit will cause the COL signal to be asserted in - * response to the assertion of TX_EN within 512-bit times. The COL - * signal will be deasserted within 4-bit times in response to the - * deassertion of TX_EN. - */ -#define DP83867_BMCR_COLLISION_TEST_MASK (0x80U) -#define DP83867_BMCR_COLLISION_TEST_SHIFT (7U) -#define DP83867_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << DP83867_BMCR_COLLISION_TEST_SHIFT) & DP83867_BMCR_COLLISION_TEST_MASK) -#define DP83867_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & DP83867_BMCR_COLLISION_TEST_MASK) >> DP83867_BMCR_COLLISION_TEST_SHIFT) - -/* - * SPEED1 (RW) - * - * Speed Select: See description for bit 13. - */ -#define DP83867_BMCR_SPEED1_MASK (0x40U) -#define DP83867_BMCR_SPEED1_SHIFT (6U) -#define DP83867_BMCR_SPEED1_SET(x) (((uint16_t)(x) << DP83867_BMCR_SPEED1_SHIFT) & DP83867_BMCR_SPEED1_MASK) -#define DP83867_BMCR_SPEED1_GET(x) (((uint16_t)(x) & DP83867_BMCR_SPEED1_MASK) >> DP83867_BMCR_SPEED1_SHIFT) - -/* Bitfield definition for register: BMSR */ -/* - * 100BASE_T4 (RO/P) - * - * 100BASE-T4 Capable: - * 0 = Device not able to perform 100BASE-T4 mode. - */ -#define DP83867_BMSR_100BASE_T4_MASK (0x8000U) -#define DP83867_BMSR_100BASE_T4_SHIFT (15U) -#define DP83867_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T4_MASK) >> DP83867_BMSR_100BASE_T4_SHIFT) - -/* - * 100BASE_TX_FULL_DUPLEX (RO/P) - * - * 100BASE-TX Full Duplex Capable: - * 1 = Device able to perform 100BASE-TX in full duplex mode. - */ -#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK (0x4000U) -#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT (14U) -#define DP83867_BMSR_100BASE_TX_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_FULL_DUPLEX_SHIFT) - -/* - * 100BASE_TX_HALF_DUPLEX (RO/P) - * - * 100BASE-TX Half Duplex Capable: - * 1 = Device able to perform 100BASE-TX in half duplex mode. - */ -#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK (0x2000U) -#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT (13U) -#define DP83867_BMSR_100BASE_TX_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_TX_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_TX_HALF_DUPLEX_SHIFT) - -/* - * 10BASE_TE_FULL_DUPLEX (RO/P) - * - * 10BASE-Te Full Duplex Capable: - * 1 = Device able to perform 10BASE-Te in full duplex mode. - */ -#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK (0x1000U) -#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT (12U) -#define DP83867_BMSR_10BASE_TE_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_FULL_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_FULL_DUPLEX_SHIFT) - -/* - * 10BASE_TE_HALF_DUPLEX (RO/P) - * - * 10BASE-Te Half Duplex Capable: - * 1 = Device able to perform 10BASE-Te in half duplex mode. - */ -#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK (0x800U) -#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT (11U) -#define DP83867_BMSR_10BASE_TE_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_10BASE_TE_HALF_DUPLEX_MASK) >> DP83867_BMSR_10BASE_TE_HALF_DUPLEX_SHIFT) - -/* - * 100BASE_T2_FULL_DUPLEX (RO/P) - * - * 100BASE-T2 Full Duplex Capable: - * 0 = Device not able to perform 100BASE-T2 in full duplex mode. - */ -#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK (0x400U) -#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT (10U) -#define DP83867_BMSR_100BASE_T2_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_FULL_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_FULL_DUPLEX_SHIFT) - -/* - * 100BASE_T2_HALF_DUPLEX (RO/P) - * - * 100BASE-T2 Half Duplex Capable: - * 0 = Device not able to perform 100BASE-T2 in half duplex mode. - */ -#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK (0x200U) -#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT (9U) -#define DP83867_BMSR_100BASE_T2_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_BMSR_100BASE_T2_HALF_DUPLEX_MASK) >> DP83867_BMSR_100BASE_T2_HALF_DUPLEX_SHIFT) - -/* - * EXTENDED_STATUS (RO/P) - * - * 1000BASE-T Extended Status Register: - * 1 = Device supports Extended Status Register 0x0F. - */ -#define DP83867_BMSR_EXTENDED_STATUS_MASK (0x100U) -#define DP83867_BMSR_EXTENDED_STATUS_SHIFT (8U) -#define DP83867_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_STATUS_MASK) >> DP83867_BMSR_EXTENDED_STATUS_SHIFT) - -/* - * MF_PREAMBLE_SUPPRESSION (RO/P) - * - * Preamble Suppression Capable: - * 1 = Device able to perform management transaction with preamble - * suppressed, 32-bits of preamble needed only once after reset, - * invalid opcode or invalid turnaround. - * 0 = Normal management operation. - */ -#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK (0x40U) -#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT (6U) -#define DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_MASK) >> DP83867_BMSR_MF_PREAMBLE_SUPPRESSION_SHIFT) - -/* - * AUTO_NEGOTIATION_COMPLETE (RO) - * - * Auto-Negotiation Complete: - * 1 = Auto-Negotiation process complete. - * 0 = Auto-Negotiation process not complete. - */ -#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) -#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) -#define DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) - -/* - * REMOTE_FAULT (RO/LH) - * - * Remote Fault: - * 1 = Remote Fault condition detected (cleared on read or by reset). - * Fault criteria: Far-End Fault Indication or notification from Link - * Partner of Remote Fault. - * 0 = No remote fault condition detected. - */ -#define DP83867_BMSR_REMOTE_FAULT_MASK (0x10U) -#define DP83867_BMSR_REMOTE_FAULT_SHIFT (4U) -#define DP83867_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & DP83867_BMSR_REMOTE_FAULT_MASK) >> DP83867_BMSR_REMOTE_FAULT_SHIFT) - -/* - * AUTO_NEGOTIATION_ABILITY ( RO/P ) - * - * Auto Negotiation Ability: - * 1 = Device is able to perform Auto-Negotiation. - * 0 = Device is not able to perform Auto-Negotiation. - */ -#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) -#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) -#define DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> DP83867_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) - -/* - * LINK_STATUS ( RO/LL) - * - * Link Status: - * 1 = Valid link established. - * 0 = Link not established. - * The criteria for link validity is implementation specific. The - * occurrence of a link failure condition will causes the Link Status bit - * to clear. Once cleared, this bit may only be set by establishing a - * good link condition and a read through the management interface. - */ -#define DP83867_BMSR_LINK_STATUS_MASK (0x4U) -#define DP83867_BMSR_LINK_STATUS_SHIFT (2U) -#define DP83867_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_BMSR_LINK_STATUS_MASK) >> DP83867_BMSR_LINK_STATUS_SHIFT) - -/* - * JABBER_DETECT ( RO/LH) - * - * Jabber Detect: This bit only has meaning in 10-Mbps mode. - * 1 = Jabber condition detected. - * 0 = No Jabber. - * This bit is implemented with a latching function, such that the - * occurrence of a jabber condition causes it to set until it is cleared by - * a read to this register by the management interface or by a reset. - */ -#define DP83867_BMSR_JABBER_DETECT_MASK (0x2U) -#define DP83867_BMSR_JABBER_DETECT_SHIFT (1U) -#define DP83867_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_BMSR_JABBER_DETECT_MASK) >> DP83867_BMSR_JABBER_DETECT_SHIFT) - -/* - * EXTENDED_CAPABILITY (RO/P) - * - * Extended Capability: - * 1 = Extended register capabilities. - * 0 = Basic register set capabilities only. - */ -#define DP83867_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) -#define DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) -#define DP83867_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & DP83867_BMSR_EXTENDED_CAPABILITY_MASK) >> DP83867_BMSR_EXTENDED_CAPABILITY_SHIFT) - -/* Bitfield definition for register: PHYIDR1 */ -/* - * OUI_MSB (RO/P) - * - * OUI Most Significant Bits: Bits 3 to 18 of the OUI (080028h,) are - * stored in bits 15 to 0 of this register. The most significant two bits of - * the OUI are ignored (the IEEE standard refers to these as bits 1 and - * 2). - */ -#define DP83867_PHYIDR1_OUI_MSB_MASK (0xFFFFU) -#define DP83867_PHYIDR1_OUI_MSB_SHIFT (0U) -#define DP83867_PHYIDR1_OUI_MSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR1_OUI_MSB_MASK) >> DP83867_PHYIDR1_OUI_MSB_SHIFT) - -/* Bitfield definition for register: PHYIDR2 */ -/* - * OUI_LSB (RO/P) - * - * OUI Least Significant Bits: - * Bits 19 to 24 of the OUI (080028h) are mapped from bits 15 to 10 of - * this register respectively. - */ -#define DP83867_PHYIDR2_OUI_LSB_MASK (0xFC00U) -#define DP83867_PHYIDR2_OUI_LSB_SHIFT (10U) -#define DP83867_PHYIDR2_OUI_LSB_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_OUI_LSB_MASK) >> DP83867_PHYIDR2_OUI_LSB_SHIFT) - -/* - * VNDR_MDL (RO/P) - * - * Vendor Model Number: - * The six bits of vendor model number are mapped from bits 9 to 4 - * (most significant bit to bit 9). - */ -#define DP83867_PHYIDR2_VNDR_MDL_MASK (0x3F0U) -#define DP83867_PHYIDR2_VNDR_MDL_SHIFT (4U) -#define DP83867_PHYIDR2_VNDR_MDL_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_VNDR_MDL_MASK) >> DP83867_PHYIDR2_VNDR_MDL_SHIFT) - -/* - * MDL_REV (RO/P) - * - * Model Revision Number: - * Four bits of the vendor model revision number are mapped from bits - * 3 to 0 (most significant bit to bit 3). This field will be incremented for - * all major device changes. - */ -#define DP83867_PHYIDR2_MDL_REV_MASK (0xFU) -#define DP83867_PHYIDR2_MDL_REV_SHIFT (0U) -#define DP83867_PHYIDR2_MDL_REV_GET(x) (((uint16_t)(x) & DP83867_PHYIDR2_MDL_REV_MASK) >> DP83867_PHYIDR2_MDL_REV_SHIFT) - -/* Bitfield definition for register: ANAR */ -/* - * NP (RW) - * - * Next Page Indication: - * 0 = Next Page Transfer not desired. - * 1 = Next Page Transfer desired. - */ -#define DP83867_ANAR_NP_MASK (0x8000U) -#define DP83867_ANAR_NP_SHIFT (15U) -#define DP83867_ANAR_NP_SET(x) (((uint16_t)(x) << DP83867_ANAR_NP_SHIFT) & DP83867_ANAR_NP_MASK) -#define DP83867_ANAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANAR_NP_MASK) >> DP83867_ANAR_NP_SHIFT) - -/* - * RF (RW) - * - * Remote Fault: - * 1 = Advertises that this device has detected a Remote Fault. - * 0 = No Remote Fault detected. - */ -#define DP83867_ANAR_RF_MASK (0x2000U) -#define DP83867_ANAR_RF_SHIFT (13U) -#define DP83867_ANAR_RF_SET(x) (((uint16_t)(x) << DP83867_ANAR_RF_SHIFT) & DP83867_ANAR_RF_MASK) -#define DP83867_ANAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANAR_RF_MASK) >> DP83867_ANAR_RF_SHIFT) - -/* - * ASM_DIR (RW) - * - * Asymmetric PAUSE Support for Full Duplex Links: - * The ASM_DIR bit indicates that asymmetric PAUSE is supported. - * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 - * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution - * status is reported in PHYCR[13:12]. - * 1 = Advertise that the DTE (MAC) has implemented both the - * optional MAC control sublayer and the pause function as specified - * in clause 31 and annex 31B of 802.3u. - * 0 = No MAC based full duplex flow control. - */ -#define DP83867_ANAR_ASM_DIR_MASK (0x800U) -#define DP83867_ANAR_ASM_DIR_SHIFT (11U) -#define DP83867_ANAR_ASM_DIR_SET(x) (((uint16_t)(x) << DP83867_ANAR_ASM_DIR_SHIFT) & DP83867_ANAR_ASM_DIR_MASK) -#define DP83867_ANAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANAR_ASM_DIR_MASK) >> DP83867_ANAR_ASM_DIR_SHIFT) - -/* - * PAUSE (RW) - * - * PAUSE Support for Full Duplex Links: - * The PAUSE bit indicates that the device is capable of providing the - * symmetric PAUSE functions as defined in Annex 31B. - * Encoding and resolution of PAUSE bits is defined in IEEE 802.3 - * Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution - * status is reported in PHYCR[13:12]. - * 1 = Advertise that the DTE (MAC) has implemented both the - * optional MAC control sublayer and the pause function as specified - * in clause 31 and annex 31B of 802.3u. - * 0 = No MAC based full duplex flow control. - */ -#define DP83867_ANAR_PAUSE_MASK (0x400U) -#define DP83867_ANAR_PAUSE_SHIFT (10U) -#define DP83867_ANAR_PAUSE_SET(x) (((uint16_t)(x) << DP83867_ANAR_PAUSE_SHIFT) & DP83867_ANAR_PAUSE_MASK) -#define DP83867_ANAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANAR_PAUSE_MASK) >> DP83867_ANAR_PAUSE_SHIFT) - -/* - * T4 (RO/P) - * - * 100BASE-T4 Support: - * 1 = 100BASE-T4 is supported by the local device. - * 0 = 100BASE-T4 not supported. - */ -#define DP83867_ANAR_T4_MASK (0x200U) -#define DP83867_ANAR_T4_SHIFT (9U) -#define DP83867_ANAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANAR_T4_MASK) >> DP83867_ANAR_T4_SHIFT) - -/* - * TX_FD (STRAP, RW) - * - * 100BASE-TX Full Duplex Support: - * 1 = 100BASE-TX Full Duplex is supported by the local device. - * 0 = 100BASE-TX Full Duplex not supported. - */ -#define DP83867_ANAR_TX_FD_MASK (0x100U) -#define DP83867_ANAR_TX_FD_SHIFT (8U) -#define DP83867_ANAR_TX_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_FD_SHIFT) & DP83867_ANAR_TX_FD_MASK) -#define DP83867_ANAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_FD_MASK) >> DP83867_ANAR_TX_FD_SHIFT) - -/* - * TX (STRAP, RW) - * - * 100BASE-TX Support: - * 1 = 100BASE-TX is supported by the local device. - * 0 = 100BASE-TX not supported. - */ -#define DP83867_ANAR_TX_MASK (0x80U) -#define DP83867_ANAR_TX_SHIFT (7U) -#define DP83867_ANAR_TX_SET(x) (((uint16_t)(x) << DP83867_ANAR_TX_SHIFT) & DP83867_ANAR_TX_MASK) -#define DP83867_ANAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANAR_TX_MASK) >> DP83867_ANAR_TX_SHIFT) - -/* - * 10_FD (STRAP, RW) - * - * 10BASE-Te Full Duplex Support: - * 1 = 10BASE-Te Full Duplex is supported by the local device. - * 0 = 10BASE-Te Full Duplex not supported. - */ -#define DP83867_ANAR_10_FD_MASK (0x40U) -#define DP83867_ANAR_10_FD_SHIFT (6U) -#define DP83867_ANAR_10_FD_SET(x) (((uint16_t)(x) << DP83867_ANAR_10_FD_SHIFT) & DP83867_ANAR_10_FD_MASK) -#define DP83867_ANAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANAR_10_FD_MASK) >> DP83867_ANAR_10_FD_SHIFT) - -/* - * 10BASETE_EN (STRAP, RW) - * - * 10BASE-Te Support: - * 1 = 10BASE-Te is supported by the local device. - * 0 = 10BASE-Te not supported. - */ -#define DP83867_ANAR_10BASETE_EN_MASK (0x20U) -#define DP83867_ANAR_10BASETE_EN_SHIFT (5U) -#define DP83867_ANAR_10BASETE_EN_SET(x) (((uint16_t)(x) << DP83867_ANAR_10BASETE_EN_SHIFT) & DP83867_ANAR_10BASETE_EN_MASK) -#define DP83867_ANAR_10BASETE_EN_GET(x) (((uint16_t)(x) & DP83867_ANAR_10BASETE_EN_MASK) >> DP83867_ANAR_10BASETE_EN_SHIFT) - -/* - * SELECTOR (RW) - * - * Protocol Selection Bits: - * These bits contain the binary encoded protocol selector supported - * by this port. <00001> indicates that this device supports IEEE - * 802.3u. - */ -#define DP83867_ANAR_SELECTOR_MASK (0x1FU) -#define DP83867_ANAR_SELECTOR_SHIFT (0U) -#define DP83867_ANAR_SELECTOR_SET(x) (((uint16_t)(x) << DP83867_ANAR_SELECTOR_SHIFT) & DP83867_ANAR_SELECTOR_MASK) -#define DP83867_ANAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANAR_SELECTOR_MASK) >> DP83867_ANAR_SELECTOR_SHIFT) - -/* Bitfield definition for register: ANLPAR */ -/* - * NP (RO) - * - * Next Page Indication: - * 0 = Link Partner does not desire Next Page Transfer. - * 1 = Link Partner desires Next Page Transfer. - */ -#define DP83867_ANLPAR_NP_MASK (0x8000U) -#define DP83867_ANLPAR_NP_SHIFT (15U) -#define DP83867_ANLPAR_NP_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_NP_MASK) >> DP83867_ANLPAR_NP_SHIFT) - -/* - * ACK (RO) - * - * Acknowledge: - * 1 = Link Partner acknowledges reception of the ability data word. - * 0 = Not acknowledged. - * The Auto-Negotiation state machine will automatically control this bit - * based on the incoming FLP bursts. - */ -#define DP83867_ANLPAR_ACK_MASK (0x4000U) -#define DP83867_ANLPAR_ACK_SHIFT (14U) -#define DP83867_ANLPAR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ACK_MASK) >> DP83867_ANLPAR_ACK_SHIFT) - -/* - * RF (RO) - * - * Remote Fault: - * 1 = Remote Fault indicated by Link Partner. - * 0 = No Remote Fault indicated by Link Partner. - */ -#define DP83867_ANLPAR_RF_MASK (0x2000U) -#define DP83867_ANLPAR_RF_SHIFT (13U) -#define DP83867_ANLPAR_RF_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_RF_MASK) >> DP83867_ANLPAR_RF_SHIFT) - -/* - * ASM_DIR (RO) - * - * ASYMMETRIC PAUSE: - * 1 = Asymmetric pause is supported by the Link Partner. - * 0 = Asymmetric pause is not supported by the Link Partner. - */ -#define DP83867_ANLPAR_ASM_DIR_MASK (0x800U) -#define DP83867_ANLPAR_ASM_DIR_SHIFT (11U) -#define DP83867_ANLPAR_ASM_DIR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_ASM_DIR_MASK) >> DP83867_ANLPAR_ASM_DIR_SHIFT) - -/* - * PAUSE (RO) - * - * PAUSE: - * 1 = Pause function is supported by the Link Partner. - * 0 = Pause function is not supported by the Link Partner. - */ -#define DP83867_ANLPAR_PAUSE_MASK (0x400U) -#define DP83867_ANLPAR_PAUSE_SHIFT (10U) -#define DP83867_ANLPAR_PAUSE_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_PAUSE_MASK) >> DP83867_ANLPAR_PAUSE_SHIFT) - -/* - * T4 (RO) - * - * 100BASE-T4 Support: - * 1 = 100BASE-T4 is supported by the Link Partner. - * 0 = 100BASE-T4 not supported by the Link Partner. - */ -#define DP83867_ANLPAR_T4_MASK (0x200U) -#define DP83867_ANLPAR_T4_SHIFT (9U) -#define DP83867_ANLPAR_T4_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_T4_MASK) >> DP83867_ANLPAR_T4_SHIFT) - -/* - * TX_FD (RO) - * - * 100BASE-TX Full Duplex Support: - * 1 = 100BASE-TX Full Duplex is supported by the Link Partner. - * 0 = 100BASE-TX Full Duplex not supported by the Link Partner. - */ -#define DP83867_ANLPAR_TX_FD_MASK (0x100U) -#define DP83867_ANLPAR_TX_FD_SHIFT (8U) -#define DP83867_ANLPAR_TX_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_FD_MASK) >> DP83867_ANLPAR_TX_FD_SHIFT) - -/* - * TX (RO) - * - * 100BASE-TX Support: - * 1 = 100BASE-TX is supported by the Link Partner. - * 0 = 100BASE-TX not supported by the Link Partner. - */ -#define DP83867_ANLPAR_TX_MASK (0x80U) -#define DP83867_ANLPAR_TX_SHIFT (7U) -#define DP83867_ANLPAR_TX_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_TX_MASK) >> DP83867_ANLPAR_TX_SHIFT) - -/* - * 10_FD (RO) - * - * 10BASE-Te Full Duplex Support: - * 1 = 10BASE-Te Full Duplex is supported by the Link Partner. - * 0 = 10BASE-Te Full Duplex not supported by the Link Partner. - */ -#define DP83867_ANLPAR_10_FD_MASK (0x40U) -#define DP83867_ANLPAR_10_FD_SHIFT (6U) -#define DP83867_ANLPAR_10_FD_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_FD_MASK) >> DP83867_ANLPAR_10_FD_SHIFT) - -/* - * 10 (RO) - * - * 10BASE-Te Support: - * 1 = 10BASE-Te is supported by the Link Partner. - * 0 = 10BASE-Te not supported by the Link Partner. - */ -#define DP83867_ANLPAR_10_MASK (0x20U) -#define DP83867_ANLPAR_10_SHIFT (5U) -#define DP83867_ANLPAR_10_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_10_MASK) >> DP83867_ANLPAR_10_SHIFT) - -/* - * SELECTOR (RO) - * - * Protocol Selection Bits: - * Link Partner's binary encoded protocol selector. - */ -#define DP83867_ANLPAR_SELECTOR_MASK (0x1FU) -#define DP83867_ANLPAR_SELECTOR_SHIFT (0U) -#define DP83867_ANLPAR_SELECTOR_GET(x) (((uint16_t)(x) & DP83867_ANLPAR_SELECTOR_MASK) >> DP83867_ANLPAR_SELECTOR_SHIFT) - -/* Bitfield definition for register: ANER */ -/* - * RX_NEXT_PAGE_LOC_ABLE (RO) - * - * Receive Next Page Location Able: - * 1 = Received Next Page storage location is specified by bit 6.5. - * 0 = Received Next Page storage location is not specified by bit 6.5. - */ -#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK (0x40U) -#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT (6U) -#define DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_MASK) >> DP83867_ANER_RX_NEXT_PAGE_LOC_ABLE_SHIFT) - -/* - * RX_NEXT_PAGE_STOR_LOC (RO) - * - * Receive Next Page Storage Location: - * 1 = Link Partner Next Pages are stored in register 8. - * 0 = Link Partner Next Pages are stored in register 5. - */ -#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK (0x20U) -#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT (5U) -#define DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_GET(x) (((uint16_t)(x) & DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_MASK) >> DP83867_ANER_RX_NEXT_PAGE_STOR_LOC_SHIFT) - -/* - * PDF (RO) - * - * Parallel Detection Fault: - * 1 = A fault has been detected via the Parallel Detection function. - * 0 = A fault has not been detected. - */ -#define DP83867_ANER_PDF_MASK (0x10U) -#define DP83867_ANER_PDF_SHIFT (4U) -#define DP83867_ANER_PDF_GET(x) (((uint16_t)(x) & DP83867_ANER_PDF_MASK) >> DP83867_ANER_PDF_SHIFT) - -/* - * LP_NP_ABLE (RO) - * - * Link Partner Next Page Able: - * 1 = Link Partner does support Next Page. - * 0 = Link Partner does not support Next Page. - */ -#define DP83867_ANER_LP_NP_ABLE_MASK (0x8U) -#define DP83867_ANER_LP_NP_ABLE_SHIFT (3U) -#define DP83867_ANER_LP_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_NP_ABLE_MASK) >> DP83867_ANER_LP_NP_ABLE_SHIFT) - -/* - * NP_ABLE (RO/P) - * - * Next Page Able: - * 1 = Indicates local device is able to send additional Next Pages. - */ -#define DP83867_ANER_NP_ABLE_MASK (0x4U) -#define DP83867_ANER_NP_ABLE_SHIFT (2U) -#define DP83867_ANER_NP_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_NP_ABLE_MASK) >> DP83867_ANER_NP_ABLE_SHIFT) - -/* - * PAGE_RX (RO/COR) - * - * Link Code Word Page Received: - * 1 = Link Code Word has been received, cleared on a read. - * 0 = Link Code Word has not been received. - */ -#define DP83867_ANER_PAGE_RX_MASK (0x2U) -#define DP83867_ANER_PAGE_RX_SHIFT (1U) -#define DP83867_ANER_PAGE_RX_GET(x) (((uint16_t)(x) & DP83867_ANER_PAGE_RX_MASK) >> DP83867_ANER_PAGE_RX_SHIFT) - -/* - * LP_AN_ABLE (RO) - * - * Link Partner Auto-Negotiation Able: - * 1 = Indicates that the Link Partner supports Auto-Negotiation. - * 0 = Indicates that the Link Partner does not support Auto- - * Negotiation. - */ -#define DP83867_ANER_LP_AN_ABLE_MASK (0x1U) -#define DP83867_ANER_LP_AN_ABLE_SHIFT (0U) -#define DP83867_ANER_LP_AN_ABLE_GET(x) (((uint16_t)(x) & DP83867_ANER_LP_AN_ABLE_MASK) >> DP83867_ANER_LP_AN_ABLE_SHIFT) - -/* Bitfield definition for register: ANNPTR */ -/* - * NP (RW) - * - * Next Page Indication: - * 0 = No other Next Page Transfer desired. - * 1 = Another Next Page desired. - */ -#define DP83867_ANNPTR_NP_MASK (0x8000U) -#define DP83867_ANNPTR_NP_SHIFT (15U) -#define DP83867_ANNPTR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_NP_SHIFT) & DP83867_ANNPTR_NP_MASK) -#define DP83867_ANNPTR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_NP_MASK) >> DP83867_ANNPTR_NP_SHIFT) - -/* - * ACK (RO) - * - * Acknowledge: - * 1 = Acknowledge reception of link code word - * 0 = Do not acknowledge of link code word. - */ -#define DP83867_ANNPTR_ACK_MASK (0x4000U) -#define DP83867_ANNPTR_ACK_SHIFT (14U) -#define DP83867_ANNPTR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK_MASK) >> DP83867_ANNPTR_ACK_SHIFT) - -/* - * MP (RW) - * - * Message Page: - * 1 = Current page is a Message Page. - * 0 = Current page is an Unformatted Page. - */ -#define DP83867_ANNPTR_MP_MASK (0x2000U) -#define DP83867_ANNPTR_MP_SHIFT (13U) -#define DP83867_ANNPTR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_MP_SHIFT) & DP83867_ANNPTR_MP_MASK) -#define DP83867_ANNPTR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_MP_MASK) >> DP83867_ANNPTR_MP_SHIFT) - -/* - * ACK2 (RW) - * - * Acknowledge2: - * 1 = Will comply with message. - * 0 = Cannot comply with message. - * Acknowledge2 is used by the next page function to indicate that - * Local Device has the ability to comply with the message received. - */ -#define DP83867_ANNPTR_ACK2_MASK (0x1000U) -#define DP83867_ANNPTR_ACK2_SHIFT (12U) -#define DP83867_ANNPTR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_ACK2_SHIFT) & DP83867_ANNPTR_ACK2_MASK) -#define DP83867_ANNPTR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_ACK2_MASK) >> DP83867_ANNPTR_ACK2_SHIFT) - -/* - * TOG_TX (RO) - * - * Toggle: - * 1 = Value of toggle bit in previously transmitted Link Code Word - * was 0. - * 0 = Value of toggle bit in previously transmitted Link Code Word - * was 1. - * Toggle is used by the Arbitration function within Auto-Negotiation to - * ensure synchronization with the Link Partner during Next Page - * exchange. This bit shall always take the opposite value of the - * Toggle bit in the previously exchanged Link Code Word. - */ -#define DP83867_ANNPTR_TOG_TX_MASK (0x800U) -#define DP83867_ANNPTR_TOG_TX_SHIFT (11U) -#define DP83867_ANNPTR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_TOG_TX_MASK) >> DP83867_ANNPTR_TOG_TX_SHIFT) - -/* - * CODE (RW) - * - * Code: - * This field represents the code field of the next page transmission. If - * the MP bit is set (bit 13 of this register), then the code shall be - * interpreted as a "Message Page”, as defined in Annex 28C of IEEE - * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted - * Page”, and the interpretation is application specific. - * The default value of the CODE represents a Null Page as defined in - * Annex 28C of IEEE 802.3u. - */ -#define DP83867_ANNPTR_CODE_MASK (0x7FFU) -#define DP83867_ANNPTR_CODE_SHIFT (0U) -#define DP83867_ANNPTR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPTR_CODE_SHIFT) & DP83867_ANNPTR_CODE_MASK) -#define DP83867_ANNPTR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPTR_CODE_MASK) >> DP83867_ANNPTR_CODE_SHIFT) - -/* Bitfield definition for register: ANNPRR */ -/* - * NP (RW) - * - * Next Page Indication: - * 0 = No other Next Page Transfer desired by the link partner. - * 1 = Another Next Page desired by the link partner. - */ -#define DP83867_ANNPRR_NP_MASK (0x8000U) -#define DP83867_ANNPRR_NP_SHIFT (15U) -#define DP83867_ANNPRR_NP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_NP_SHIFT) & DP83867_ANNPRR_NP_MASK) -#define DP83867_ANNPRR_NP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_NP_MASK) >> DP83867_ANNPRR_NP_SHIFT) - -/* - * ACK (RO) - * - * Acknowledge: - * 1 = Acknowledge reception of link code word by the link partner. - * 0 = Link partner does not acknowledge reception of link code word. - */ -#define DP83867_ANNPRR_ACK_MASK (0x4000U) -#define DP83867_ANNPRR_ACK_SHIFT (14U) -#define DP83867_ANNPRR_ACK_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK_MASK) >> DP83867_ANNPRR_ACK_SHIFT) - -/* - * MP (RW) - * - * Message Page: - * 1 = Received page is a Message Page. - * 0 = Received page is an Unformatted Page. - */ -#define DP83867_ANNPRR_MP_MASK (0x2000U) -#define DP83867_ANNPRR_MP_SHIFT (13U) -#define DP83867_ANNPRR_MP_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_MP_SHIFT) & DP83867_ANNPRR_MP_MASK) -#define DP83867_ANNPRR_MP_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_MP_MASK) >> DP83867_ANNPRR_MP_SHIFT) - -/* - * ACK2 (RW) - * - * Acknowledge2: - * 1 = Link partner sets the ACK2 bit. - * 0 = Link partner coes not set the ACK2 bit. - * Acknowledge2 is used by the next page function to indicate that link - * partner has the ability to comply with the message received. - */ -#define DP83867_ANNPRR_ACK2_MASK (0x1000U) -#define DP83867_ANNPRR_ACK2_SHIFT (12U) -#define DP83867_ANNPRR_ACK2_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_ACK2_SHIFT) & DP83867_ANNPRR_ACK2_MASK) -#define DP83867_ANNPRR_ACK2_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_ACK2_MASK) >> DP83867_ANNPRR_ACK2_SHIFT) - -/* - * TOG_TX (RO) - * - * Toggle: - * 1 = Value of toggle bit in previously transmitted Link Code Word - * was 0. - * 0 = Value of toggle bit in previously transmitted Link Code Word - * was 1. - * Toggle is used by the Arbitration function within Auto-Negotiation to - * ensure synchronization with the Link Partner during Next Page - * exchange. This bit shall always take the opposite value of the - * Toggle bit in the previously exchanged Link Code Word. - */ -#define DP83867_ANNPRR_TOG_TX_MASK (0x800U) -#define DP83867_ANNPRR_TOG_TX_SHIFT (11U) -#define DP83867_ANNPRR_TOG_TX_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_TOG_TX_MASK) >> DP83867_ANNPRR_TOG_TX_SHIFT) - -/* - * CODE (RW) - * - * Code: - * This field represents the code field of the next page transmission. If - * the MP bit is set (bit 13 of this register), then the code shall be - * interpreted as a "Message Page”, as defined in Annex 28C of IEEE - * 802.3u. Otherwise, the code shall be interpreted as an "Unformatted - * Page”, and the interpretation is application specific. - * The default value of the CODE represents a Null Page as defined in - * Annex 28C of IEEE 802.3u. - */ -#define DP83867_ANNPRR_CODE_MASK (0x7FFU) -#define DP83867_ANNPRR_CODE_SHIFT (0U) -#define DP83867_ANNPRR_CODE_SET(x) (((uint16_t)(x) << DP83867_ANNPRR_CODE_SHIFT) & DP83867_ANNPRR_CODE_MASK) -#define DP83867_ANNPRR_CODE_GET(x) (((uint16_t)(x) & DP83867_ANNPRR_CODE_MASK) >> DP83867_ANNPRR_CODE_SHIFT) - -/* Bitfield definition for register: CFG1 */ -/* - * TEST_MODE (RW) - * - * Test Mode Select: - * 111 = Test Mode 7 - Repetitive {Pulse, 63 zeros} - * 110 = Test Mode 6 - Repetitive 0001 sequence - * 101 = Test Mode 5 - Scrambled MLT3 Idles - * 100 = Test Mode 4 - Transmit Distortion Test - * 011 = Test Mode 3 - Transmit Jitter Test (Slave Mode) - * 010 = Test Mode 2 - Transmit Jitter Test (Master Mode) - * 001 = Test Mode 1 - Transmit Waveform Test - * 000 = Normal Mode - */ -#define DP83867_CFG1_TEST_MODE_MASK (0xE000U) -#define DP83867_CFG1_TEST_MODE_SHIFT (13U) -#define DP83867_CFG1_TEST_MODE_SET(x) (((uint16_t)(x) << DP83867_CFG1_TEST_MODE_SHIFT) & DP83867_CFG1_TEST_MODE_MASK) -#define DP83867_CFG1_TEST_MODE_GET(x) (((uint16_t)(x) & DP83867_CFG1_TEST_MODE_MASK) >> DP83867_CFG1_TEST_MODE_SHIFT) - -/* - * MASTER_SLAVE_MANUAL_CONFIGURATION (RW) - * - * Enable Manual Master / Slave Configuration: - * 1 = Enable Manual Master/Slave Configuration control. - * 0 = Disable Manual Master/Slave Configuration control. - * Using the manual configuration feature may prevent the PHY from - * establishing link in 1000Base-T mode if a conflict with the link - * partner’s setting exists. - */ -#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK (0x1000U) -#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT (12U) -#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) -#define DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_MASK) >> DP83867_CFG1_MASTER_SLAVE_MANUAL_CONFIGURATION_SHIFT) - -/* - * MASTER_SLAVE_CONFIGURATION_VALUE (RW) - * - * Manual Master / Slave Configuration Value: - * 1 = Set PHY as MASTER when register 09h bit 12 = 1. - * 0 = Set PHY as SLAVE when register 09h bit 12 = 1. - * Using the manual configuration feature may prevent the PHY from - * establishing link in 1000Base-T mode if a conflict with the link - * partner’s setting exists. - */ -#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK (0x800U) -#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT (11U) -#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SET(x) (((uint16_t)(x) << DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) -#define DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_GET(x) (((uint16_t)(x) & DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_MASK) >> DP83867_CFG1_MASTER_SLAVE_CONFIGURATION_VALUE_SHIFT) - -/* - * PORT_TYPE (RW) - * - * Advertise Device Type: Multi or single port: - * 1 = Multi-port device. - * 0 = Single-port device. - */ -#define DP83867_CFG1_PORT_TYPE_MASK (0x400U) -#define DP83867_CFG1_PORT_TYPE_SHIFT (10U) -#define DP83867_CFG1_PORT_TYPE_SET(x) (((uint16_t)(x) << DP83867_CFG1_PORT_TYPE_SHIFT) & DP83867_CFG1_PORT_TYPE_MASK) -#define DP83867_CFG1_PORT_TYPE_GET(x) (((uint16_t)(x) & DP83867_CFG1_PORT_TYPE_MASK) >> DP83867_CFG1_PORT_TYPE_SHIFT) - -/* - * 1000BASE_T_FULL_DUPLEX (RW) - * - * Advertise 1000BASE-T Full Duplex Capable: - * 1 = Advertise 1000Base-T Full Duplex ability. - * 0 = Do not advertise 1000Base-T Full Duplex ability. - */ -#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK (0x200U) -#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT (9U) -#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) -#define DP83867_CFG1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_FULL_DUPLEX_SHIFT) - -/* - * 1000BASE_T_HALF_DUPLEX (RW) - * - * Advertise 1000BASE-T Half Duplex Capable: - * 1 = Advertise 1000Base-T Half Duplex ability. - * 0 = Do not advertise 1000Base-T Half Duplex ability. - */ -#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK (0x100U) -#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT (8U) -#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SET(x) (((uint16_t)(x) << DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) -#define DP83867_CFG1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_CFG1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_CFG1_1000BASE_T_HALF_DUPLEX_SHIFT) - -/* - * TDR_AUTO_RUN (RW) - * - * Automatic TDR on Link Down: - * 1 = Enable execution of TDR procedure after link down event. - * 0 = Disable automatic execution of TDR. - */ -#define DP83867_CFG1_TDR_AUTO_RUN_MASK (0x80U) -#define DP83867_CFG1_TDR_AUTO_RUN_SHIFT (7U) -#define DP83867_CFG1_TDR_AUTO_RUN_SET(x) (((uint16_t)(x) << DP83867_CFG1_TDR_AUTO_RUN_SHIFT) & DP83867_CFG1_TDR_AUTO_RUN_MASK) -#define DP83867_CFG1_TDR_AUTO_RUN_GET(x) (((uint16_t)(x) & DP83867_CFG1_TDR_AUTO_RUN_MASK) >> DP83867_CFG1_TDR_AUTO_RUN_SHIFT) - -/* Bitfield definition for register: STS1 */ -/* - * MASTER_SLAVE_CONFIGURATION_FAULT (RO, LH, COR) - * - * Master / Slave Manual Configuration Fault Detected: - * 1 = Manual Master/Slave Configuration fault detected. - * 0 = No Manual Master/Slave Configuration fault detected. - */ -#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK (0x8000U) -#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT (15U) -#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_FAULT_SHIFT) - -/* - * MASTER_SLAVE_CONFIGURATION_RESOLUTION (RO) - * - * Master / Slave Configuration Results: - * 1 = Configuration resolved to MASTER. - * 0 = Configuration resolved to SLAVE. - */ -#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK (0x4000U) -#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT (14U) -#define DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_GET(x) (((uint16_t)(x) & DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_MASK) >> DP83867_STS1_MASTER_SLAVE_CONFIGURATION_RESOLUTION_SHIFT) - -/* - * LOCAL_RECEIVER_STATUS (RO) - * - * Local Receiver Status: - * 1 = Local receiver is OK. - * 0 = Local receiver is not OK. - */ -#define DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK (0x2000U) -#define DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT (13U) -#define DP83867_STS1_LOCAL_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_LOCAL_RECEIVER_STATUS_MASK) >> DP83867_STS1_LOCAL_RECEIVER_STATUS_SHIFT) - -/* - * REMOTE_RECEIVER_STATUS (RO) - * - * Remote Receiver Status: - * 1 = Remote receiver is OK. - * 0 = Remote receiver is not OK. - */ -#define DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK (0x1000U) -#define DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT (12U) -#define DP83867_STS1_REMOTE_RECEIVER_STATUS_GET(x) (((uint16_t)(x) & DP83867_STS1_REMOTE_RECEIVER_STATUS_MASK) >> DP83867_STS1_REMOTE_RECEIVER_STATUS_SHIFT) - -/* - * 1000BASE_T_FULL_DUPLEX (RO) - * - * Link Partner 1000BASE-T Full Duplex Capable: - * 1 = Link Partner capable of 1000Base-T Full Duplex. - * 0 = Link partner not capable of 1000Base-T Full Duplex. - */ -#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK (0x800U) -#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT (11U) -#define DP83867_STS1_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_FULL_DUPLEX_SHIFT) - -/* - * 1000BASE_T_HALF_DUPLEX (RO) - * - * Link Partner 1000BASE-T Half Duplex Capable: - * 1 = Link Partner capable of 1000Base-T Half Duplex. - * 0 = Link partner not capable of 1000Base-T Half Duplex. - */ -#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK (0x400U) -#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT (10U) -#define DP83867_STS1_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_STS1_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_STS1_1000BASE_T_HALF_DUPLEX_SHIFT) - -/* - * IDLE_ERROR_COUNTER (RO,COR) - * - * 1000BASE-T Idle Error Counter - */ -#define DP83867_STS1_IDLE_ERROR_COUNTER_MASK (0xFFU) -#define DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT (0U) -#define DP83867_STS1_IDLE_ERROR_COUNTER_GET(x) (((uint16_t)(x) & DP83867_STS1_IDLE_ERROR_COUNTER_MASK) >> DP83867_STS1_IDLE_ERROR_COUNTER_SHIFT) - -/* Bitfield definition for register: REGCR */ -/* - * FUNCTION (RW) - * - * 00 = Address - * 01 = Data, no post increment - * 10 = Data, post increment on read and write - * 11 = Data, post increment on write only - */ -#define DP83867_REGCR_FUNCTION_MASK (0xC000U) -#define DP83867_REGCR_FUNCTION_SHIFT (14U) -#define DP83867_REGCR_FUNCTION_SET(x) (((uint16_t)(x) << DP83867_REGCR_FUNCTION_SHIFT) & DP83867_REGCR_FUNCTION_MASK) -#define DP83867_REGCR_FUNCTION_GET(x) (((uint16_t)(x) & DP83867_REGCR_FUNCTION_MASK) >> DP83867_REGCR_FUNCTION_SHIFT) - -/* - * DEVAD (RW) - * - * Device Address: In general, these bits [4:0] are the device address - * DEVAD that directs any accesses of ADDAR register (0x000E) to - * the appropriate MMD. Specifically, the DP83867 uses the vendor - * specific DEVAD [4:0] = 11111 for accesses. All accesses through - * registers REGCR and ADDAR should use this DEVAD. - * Transactions with other DEVAD are ignored. - */ -#define DP83867_REGCR_DEVAD_MASK (0x1FU) -#define DP83867_REGCR_DEVAD_SHIFT (0U) -#define DP83867_REGCR_DEVAD_SET(x) (((uint16_t)(x) << DP83867_REGCR_DEVAD_SHIFT) & DP83867_REGCR_DEVAD_MASK) -#define DP83867_REGCR_DEVAD_GET(x) (((uint16_t)(x) & DP83867_REGCR_DEVAD_MASK) >> DP83867_REGCR_DEVAD_SHIFT) - -/* Bitfield definition for register: ADDAR */ -/* - * ADDRESS_OR_DATA_REGISTER (RW) - * - * If REGCR register 15:14 = 00, holds the MMD DEVAD's address - * register, otherwise holds the MMD DEVAD's data register - */ -#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK (0xFFFFU) -#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT (0U) -#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SET(x) (((uint16_t)(x) << DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) -#define DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_GET(x) (((uint16_t)(x) & DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_MASK) >> DP83867_ADDAR_ADDRESS_OR_DATA_REGISTER_SHIFT) - -/* Bitfield definition for register: 1KSCR */ -/* - * 1000BASE_X_FULL_DUPLEX (RO/P) - * - * 1000BASE-X Full Duplex Support: - * 1 = 1000BASE-X Full Duplex is supported by the local device. - * 0 = 1000BASE-X Full Duplex is not supported by the local device. - */ -#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK (0x8000U) -#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT (15U) -#define DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_FULL_DUPLEX_SHIFT) - -/* - * 1000BASE_X_HALF_DUPLEX (RO/P) - * - * 1000BASE-X Half Duplex Support: - * 1 = 1000BASE-X Half Duplex is supported by the local device. - * 0 = 1000BASE-X Half Duplex is not supported by the local device. - */ -#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK (0x4000U) -#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT (14U) -#define DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_X_HALF_DUPLEX_SHIFT) - -/* - * 1000BASE_T_FULL_DUPLEX (RO/P) - * - * 1000BASE-T Full Duplex Support: - * 1 = 1000BASE-T Full Duplex is supported by the local device. - * 0 = 1000BASE-T Full Duplex is not supported by the local device. - */ -#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK (0x2000U) -#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT (13U) -#define DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_FULL_DUPLEX_SHIFT) - -/* - * 1000BASE_T_HALF_DUPLEX (RO/P) - * - * 1000BASE-T Half Duplex Support: - * 1 = 1000BASE-T Half Duplex is supported by the local device. - * 0 = 1000BASE-T Half Duplex is not supported by the local device. - */ -#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK (0x1000U) -#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT (12U) -#define DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_GET(x) (((uint16_t)(x) & DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_MASK) >> DP83867_1KSCR_1000BASE_T_HALF_DUPLEX_SHIFT) - -/* Bitfield definition for register: PHYCR */ -/* - * TX_FIFO_DEPTH (RW) - * - * TX FIFO Depth: - * 11 = 8 bytes/nibbles (1000Mbps/Other Speeds) - * 10 = 6 bytes/nibbles (1000Mbps/Other Speeds) - * 01 = 4 bytes/nibbles (1000Mbps/Other Speeds) - * 00 = 3 bytes/nibbles (1000Mbps/Other Speeds) - * Note: FIFO is enabled only in the following modes: - * 1000BaseT + GMII - * 10BaseT/100BaseTX/1000BaseT + SGMII - */ -#define DP83867_PHYCR_TX_FIFO_DEPTH_MASK (0xC000U) -#define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT (14U) -#define DP83867_PHYCR_TX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) -#define DP83867_PHYCR_TX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_TX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT) - -/* - * RX_FIFO_DEPTH (RW) - * - * RX FIFO Depth: - * 11 = 8 bytes/nibbles (1000 Mbps/Other Speeds) - * 10 = 6 bytes/nibbles (1000 Mbps/Other Speeds) - * 01 = 4 bytes/nibbles (1000 Mbps/Other Speeds) - * 00 = 3 bytes/nibbles (1000 Mbps/Other Speeds) - * Note: FIFO is enabled only in SGMII - */ -#define DP83867_PHYCR_RX_FIFO_DEPTH_MASK (0x3000U) -#define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT (12U) -#define DP83867_PHYCR_RX_FIFO_DEPTH_SET(x) (((uint16_t)(x) << DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) -#define DP83867_PHYCR_RX_FIFO_DEPTH_GET(x) (((uint16_t)(x) & DP83867_PHYCR_RX_FIFO_DEPTH_MASK) >> DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT) - -/* - * SGMII_EN (RW) - * - * SGMII Enable: - * 1 = Enable SGMII - * 0 = Disable SGMII - */ -#define DP83867_PHYCR_SGMII_EN_MASK (0x800U) -#define DP83867_PHYCR_SGMII_EN_SHIFT (11U) -#define DP83867_PHYCR_SGMII_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_SGMII_EN_SHIFT) & DP83867_PHYCR_SGMII_EN_MASK) -#define DP83867_PHYCR_SGMII_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_SGMII_EN_MASK) >> DP83867_PHYCR_SGMII_EN_SHIFT) - -/* - * FORCE_LINK_GOOD (RW) - * - * Force Link Good: - * 1 = Force link good according to the selected speed. - * 0 = Normal operation - */ -#define DP83867_PHYCR_FORCE_LINK_GOOD_MASK (0x400U) -#define DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT (10U) -#define DP83867_PHYCR_FORCE_LINK_GOOD_SET(x) (((uint16_t)(x) << DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) -#define DP83867_PHYCR_FORCE_LINK_GOOD_GET(x) (((uint16_t)(x) & DP83867_PHYCR_FORCE_LINK_GOOD_MASK) >> DP83867_PHYCR_FORCE_LINK_GOOD_SHIFT) - -/* - * POWER_SAVE_MODE (RW) - * - * Power-Saving Modes: - * 11 = Passive Sleep mode: Power down all digital and analog - * blocks. - * 10 =Active Sleep mode: Power down all digital and analog blocks. - * Automatic power-up is performed when link partner is detected. Link - * pulses are transmitted approximately once per 1.4 Sec in this mode - * to wake up any potential link partner. - * 01 = IEEE mode: power down all digital and analog blocks. - * Note: If DISABLE_CLK_125 (bit [4]of this register) is set to zero, the - * PLL is also powered down. - * 00 = Normal mode - */ -#define DP83867_PHYCR_POWER_SAVE_MODE_MASK (0x300U) -#define DP83867_PHYCR_POWER_SAVE_MODE_SHIFT (8U) -#define DP83867_PHYCR_POWER_SAVE_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) -#define DP83867_PHYCR_POWER_SAVE_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_POWER_SAVE_MODE_MASK) >> DP83867_PHYCR_POWER_SAVE_MODE_SHIFT) - -/* - * DEEP_POWER_DOWN_EN (RW) - * - * Deep power-down mode enable - * 1 = When power down is initiated through assertion of the external - * power-down pin or through the POWER_DOWN bit in the BMCR, - * the device enters a deep power-down mode. - * 0 = Normal operation. - */ -#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK (0x80U) -#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT (7U) -#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) -#define DP83867_PHYCR_DEEP_POWER_DOWN_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DEEP_POWER_DOWN_EN_MASK) >> DP83867_PHYCR_DEEP_POWER_DOWN_EN_SHIFT) - -/* - * MDI_CROSSOVER (RW) - * - * MDI Crosssover Mode: - * 1x = Enable automatic crossover - * 01 = Manual MDI-X configuration - * 00 = Manual MDI configuration - */ -#define DP83867_PHYCR_MDI_CROSSOVER_MASK (0x60U) -#define DP83867_PHYCR_MDI_CROSSOVER_SHIFT (5U) -#define DP83867_PHYCR_MDI_CROSSOVER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_MDI_CROSSOVER_SHIFT) & DP83867_PHYCR_MDI_CROSSOVER_MASK) -#define DP83867_PHYCR_MDI_CROSSOVER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_MDI_CROSSOVER_MASK) >> DP83867_PHYCR_MDI_CROSSOVER_SHIFT) - -/* - * DISABLE_CLK_125 (RW) - * - * Disable 125MHz Clock: - * This bit may be used in conjunction with POWER_SAVE_MODE - * (bits 9:8 of this register). - * 1 = Disable CLK125. - * 0 = Enable CLK125. - */ -#define DP83867_PHYCR_DISABLE_CLK_125_MASK (0x10U) -#define DP83867_PHYCR_DISABLE_CLK_125_SHIFT (4U) -#define DP83867_PHYCR_DISABLE_CLK_125_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_CLK_125_SHIFT) & DP83867_PHYCR_DISABLE_CLK_125_MASK) -#define DP83867_PHYCR_DISABLE_CLK_125_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_CLK_125_MASK) >> DP83867_PHYCR_DISABLE_CLK_125_SHIFT) - -/* - * STANDBY_MODE (RW) - * - * Standby Mode: - * 1 = Enable standby mode. Digital and analog circuitry are powered - * up, but no link can be established. - * 0 = Normal operation. - */ -#define DP83867_PHYCR_STANDBY_MODE_MASK (0x4U) -#define DP83867_PHYCR_STANDBY_MODE_SHIFT (2U) -#define DP83867_PHYCR_STANDBY_MODE_SET(x) (((uint16_t)(x) << DP83867_PHYCR_STANDBY_MODE_SHIFT) & DP83867_PHYCR_STANDBY_MODE_MASK) -#define DP83867_PHYCR_STANDBY_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYCR_STANDBY_MODE_MASK) >> DP83867_PHYCR_STANDBY_MODE_SHIFT) - -/* - * LINE_DRIVER_INV_EN (RW) - * - * Line Driver Inversion Enable: - * 1 = Invert Line Driver Transmission. - * 0 = Normal operation. - */ -#define DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK (0x2U) -#define DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT (1U) -#define DP83867_PHYCR_LINE_DRIVER_INV_EN_SET(x) (((uint16_t)(x) << DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) -#define DP83867_PHYCR_LINE_DRIVER_INV_EN_GET(x) (((uint16_t)(x) & DP83867_PHYCR_LINE_DRIVER_INV_EN_MASK) >> DP83867_PHYCR_LINE_DRIVER_INV_EN_SHIFT) - -/* - * DISABLE_JABBER (RW) - * - * Disable Jabber - * 1 = Disable Jabber function. - * 0 = Enable Jabber function. - */ -#define DP83867_PHYCR_DISABLE_JABBER_MASK (0x1U) -#define DP83867_PHYCR_DISABLE_JABBER_SHIFT (0U) -#define DP83867_PHYCR_DISABLE_JABBER_SET(x) (((uint16_t)(x) << DP83867_PHYCR_DISABLE_JABBER_SHIFT) & DP83867_PHYCR_DISABLE_JABBER_MASK) -#define DP83867_PHYCR_DISABLE_JABBER_GET(x) (((uint16_t)(x) & DP83867_PHYCR_DISABLE_JABBER_MASK) >> DP83867_PHYCR_DISABLE_JABBER_SHIFT) - -/* Bitfield definition for register: PHYSTS */ -/* - * SPEED_SELECTION (RO) - * - * Speed Select Status: - * These two bits indicate the speed of operation as determined by - * Auto-Negotiation or as set by manual configuration. - * 11 = Reserved - * 10 = 1000 Mbps - * 01 = 100 Mbps - * 00 = 10 Mbps - */ -#define DP83867_PHYSTS_SPEED_SELECTION_MASK (0xC000U) -#define DP83867_PHYSTS_SPEED_SELECTION_SHIFT (14U) -#define DP83867_PHYSTS_SPEED_SELECTION_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_SELECTION_MASK) >> DP83867_PHYSTS_SPEED_SELECTION_SHIFT) - -/* - * DUPLEX_MODE (RO) - * - * Duplex Mode Status: - * 1 = Full Duplex - * 0 = Half Duplex. - */ -#define DP83867_PHYSTS_DUPLEX_MODE_MASK (0x2000U) -#define DP83867_PHYSTS_DUPLEX_MODE_SHIFT (13U) -#define DP83867_PHYSTS_DUPLEX_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_DUPLEX_MODE_MASK) >> DP83867_PHYSTS_DUPLEX_MODE_SHIFT) - -/* - * PAGE_RECEIVED ( RO, LH, COR) - * - * Page Received: - * This bit is latched high and will be cleared upon a read. - * 1 = Page received. - * 0 = No page received. - */ -#define DP83867_PHYSTS_PAGE_RECEIVED_MASK (0x1000U) -#define DP83867_PHYSTS_PAGE_RECEIVED_SHIFT (12U) -#define DP83867_PHYSTS_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_PAGE_RECEIVED_MASK) >> DP83867_PHYSTS_PAGE_RECEIVED_SHIFT) - -/* - * SPEED_DUPLEX_RESOLVED (RO) - * - * Speed Duplex Resolution Status: - * 1 = Auto-Negotiation has completed or is disabled. - * 0 = Auto-Negotiation is enabled and has not completed. - */ -#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK (0x800U) -#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT (11U) -#define DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_MASK) >> DP83867_PHYSTS_SPEED_DUPLEX_RESOLVED_SHIFT) - -/* - * LINK_STATUS (RO) - * - * Link Status: - * 1 = Link is up. - * 0 = Link is down. - */ -#define DP83867_PHYSTS_LINK_STATUS_MASK (0x400U) -#define DP83867_PHYSTS_LINK_STATUS_SHIFT (10U) -#define DP83867_PHYSTS_LINK_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_LINK_STATUS_MASK) >> DP83867_PHYSTS_LINK_STATUS_SHIFT) - -/* - * MDI_X_MODE_CD (RO) - * - * MDI/MDIX Resolution Status for C and D Line Driver Pairs: - * 1 = Resolved as MDIX - * 0 = Resolved as MDI. - */ -#define DP83867_PHYSTS_MDI_X_MODE_CD_MASK (0x200U) -#define DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT (9U) -#define DP83867_PHYSTS_MDI_X_MODE_CD_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_CD_MASK) >> DP83867_PHYSTS_MDI_X_MODE_CD_SHIFT) - -/* - * MDI_X_MODE_AB (RO) - * - * MDI/MDIX Resolution Status for A and B Line Driver Pairs: - * 1 = Resolved as MDIX - * 0 = Resolved as MDI. - */ -#define DP83867_PHYSTS_MDI_X_MODE_AB_MASK (0x100U) -#define DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT (8U) -#define DP83867_PHYSTS_MDI_X_MODE_AB_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_MDI_X_MODE_AB_MASK) >> DP83867_PHYSTS_MDI_X_MODE_AB_SHIFT) - -/* - * SPEED_OPT_STATUS (RO) - * - * Speed Optimization Status: - * 1 = Auto-Negotiation is currently being performed with Speed - * Optimization masking 1000BaseT abilities (Valid only during Auto- - * Negotiation). - * 0 = Auto-Negotiation is currently being performed without Speed - * Optimization. - */ -#define DP83867_PHYSTS_SPEED_OPT_STATUS_MASK (0x80U) -#define DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT (7U) -#define DP83867_PHYSTS_SPEED_OPT_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SPEED_OPT_STATUS_MASK) >> DP83867_PHYSTS_SPEED_OPT_STATUS_SHIFT) - -/* - * SLEEP_MODE (RO) - * - * Sleep Mode Status: - * 1 = Device currently in sleep mode. - * 0 = Device currently in active mode. - */ -#define DP83867_PHYSTS_SLEEP_MODE_MASK (0x40U) -#define DP83867_PHYSTS_SLEEP_MODE_SHIFT (6U) -#define DP83867_PHYSTS_SLEEP_MODE_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_SLEEP_MODE_MASK) >> DP83867_PHYSTS_SLEEP_MODE_SHIFT) - -/* - * WIRE_CROSS (RO) - * - * Crossed Wire Indication: - * Indicates channel polarity in 1000BASE-T linked status. Bits [5:2] - * correspond to channels [D,C,B,A], respectively. - * 1 = Channel polarity is reversed. - * 0 = Channel polarity is normal. - */ -#define DP83867_PHYSTS_WIRE_CROSS_MASK (0x3CU) -#define DP83867_PHYSTS_WIRE_CROSS_SHIFT (2U) -#define DP83867_PHYSTS_WIRE_CROSS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_WIRE_CROSS_MASK) >> DP83867_PHYSTS_WIRE_CROSS_SHIFT) - -/* - * POLARITY_STATUS (RO) - * - * 10BASE-Te Polarity Status: - * 1 = Correct Polarity detected. - * 0 = Inverted Polarity detected. - */ -#define DP83867_PHYSTS_POLARITY_STATUS_MASK (0x2U) -#define DP83867_PHYSTS_POLARITY_STATUS_SHIFT (1U) -#define DP83867_PHYSTS_POLARITY_STATUS_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_POLARITY_STATUS_MASK) >> DP83867_PHYSTS_POLARITY_STATUS_SHIFT) - -/* - * JABBER_DETECT (RO) - * - * Jabber Detect: This bit only has meaning in 10 Mbps mode. - * This bit is a duplicate of the Jabber Detect bit in the BMSR register, - * except that it is not cleared upon a read of the PHYSTS register. - * 1 = Jabber condition detected. - * 0 = No Jabber. - */ -#define DP83867_PHYSTS_JABBER_DETECT_MASK (0x1U) -#define DP83867_PHYSTS_JABBER_DETECT_SHIFT (0U) -#define DP83867_PHYSTS_JABBER_DETECT_GET(x) (((uint16_t)(x) & DP83867_PHYSTS_JABBER_DETECT_MASK) >> DP83867_PHYSTS_JABBER_DETECT_SHIFT) - -/* Bitfield definition for register: MICR */ -/* - * AUTONEG_ERR_INT_EN (RW) - * - * Enable Auto-Negotiation Error Interrupt: - * 1 = Enable Auto-Negotiation Error interrupt. - * 0 = Disable Auto-Negotiation Error interrupt. - */ -#define DP83867_MICR_AUTONEG_ERR_INT_EN_MASK (0x8000U) -#define DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT (15U) -#define DP83867_MICR_AUTONEG_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) -#define DP83867_MICR_AUTONEG_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_ERR_INT_EN_MASK) >> DP83867_MICR_AUTONEG_ERR_INT_EN_SHIFT) - -/* - * SPEED_CHNG_INT_EN (RW) - * - * Enable Speed Change Interrupt: - * 1 = Enable Speed Change interrupt. - * 0 = Disable Speed Change interrupt. - */ -#define DP83867_MICR_SPEED_CHNG_INT_EN_MASK (0x4000U) -#define DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT (14U) -#define DP83867_MICR_SPEED_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) -#define DP83867_MICR_SPEED_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_CHNG_INT_EN_MASK) >> DP83867_MICR_SPEED_CHNG_INT_EN_SHIFT) - -/* - * DUPLEX_MODE_CHNG_INT_EN (RW) - * - * Enable Duplex Mode Change Interrupt: - * 1 = Enable Duplex Mode Change interrupt. - * 0 = Disable Duplex Mode Change interrupt. - */ -#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK (0x2000U) -#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT (13U) -#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) -#define DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_DUPLEX_MODE_CHNG_INT_EN_SHIFT) - -/* - * PAGE_RECEIVED_INT_EN (RW) - * - * Enable Page Received Interrupt: - * 1 = Enable Page Received Interrupt. - * 0 = Disable Page Received Interrupt. - */ -#define DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK (0x1000U) -#define DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT (12U) -#define DP83867_MICR_PAGE_RECEIVED_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) -#define DP83867_MICR_PAGE_RECEIVED_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_PAGE_RECEIVED_INT_EN_MASK) >> DP83867_MICR_PAGE_RECEIVED_INT_EN_SHIFT) - -/* - * AUTONEG_COMP_INT_EN (RW) - * - * Enable Auto-Negotiation Complete Interrupt: - * 1 = Enable Auto-Negotiation Complete Interrupt. - * 0 = Disable Auto-Negotiation Complete Interrupt. - */ -#define DP83867_MICR_AUTONEG_COMP_INT_EN_MASK (0x800U) -#define DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT (11U) -#define DP83867_MICR_AUTONEG_COMP_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) -#define DP83867_MICR_AUTONEG_COMP_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_AUTONEG_COMP_INT_EN_MASK) >> DP83867_MICR_AUTONEG_COMP_INT_EN_SHIFT) - -/* - * LINK_STATUS_CHNG_INT_EN (RW) - * - * Enable Link Status Change Interrupt: - * 1 = Enable Link Status Change interrupt. - * 0 = Disable Link Status Change interrupt. - */ -#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK (0x400U) -#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT (10U) -#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) -#define DP83867_MICR_LINK_STATUS_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_LINK_STATUS_CHNG_INT_EN_MASK) >> DP83867_MICR_LINK_STATUS_CHNG_INT_EN_SHIFT) - -/* - * FALSE_CARRIER_INT_EN (RW) - * - * Enable False Carrier Interrupt: - * 1 = Enable False Carrier interrupt. - * 0 = Disable False Carrier interrupt. - */ -#define DP83867_MICR_FALSE_CARRIER_INT_EN_MASK (0x100U) -#define DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT (8U) -#define DP83867_MICR_FALSE_CARRIER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) -#define DP83867_MICR_FALSE_CARRIER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_FALSE_CARRIER_INT_EN_MASK) >> DP83867_MICR_FALSE_CARRIER_INT_EN_SHIFT) - -/* - * MDI_CROSSOVER_CHNG_INT_EN (RW) - * - * Enable MDI Crossover Change Interrupt: - * 1 = Enable MDI Crossover Change interrupt. - * 0 = Disable MDI Crossover Change interrupt. - */ -#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK (0x40U) -#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT (6U) -#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) -#define DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_MASK) >> DP83867_MICR_MDI_CROSSOVER_CHNG_INT_EN_SHIFT) - -/* - * SPEED_OPT_EVENT_INT_EN (RW) - * - * Enable Speed Optimization Event Interrupt: - * 1 = Enable Speed Optimization Event Interrupt. - * 0 = Disable Speed Optimization Event Interrupt. - */ -#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK (0x20U) -#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT (5U) -#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) -#define DP83867_MICR_SPEED_OPT_EVENT_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SPEED_OPT_EVENT_INT_EN_MASK) >> DP83867_MICR_SPEED_OPT_EVENT_INT_EN_SHIFT) - -/* - * SLEEP_MODE_CHNG_INT_EN (RW) - * - * Enable Sleep Mode Change Interrupt: - * 1 = Enable Sleep Mode Change Interrupt. - * 0 = Disable Sleep Mode Change Interrupt. - */ -#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK (0x10U) -#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT (4U) -#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) -#define DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_MASK) >> DP83867_MICR_SLEEP_MODE_CHNG_INT_EN_SHIFT) - -/* - * WOL_INT_EN (RW) - * - * Enable Wake-on-LAN Interrupt: - * 1 = Enable Wake-on-LAN Interrupt. - * 0 = Disable Wake-on-LAN Interrupt. - */ -#define DP83867_MICR_WOL_INT_EN_MASK (0x8U) -#define DP83867_MICR_WOL_INT_EN_SHIFT (3U) -#define DP83867_MICR_WOL_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_WOL_INT_EN_SHIFT) & DP83867_MICR_WOL_INT_EN_MASK) -#define DP83867_MICR_WOL_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_WOL_INT_EN_MASK) >> DP83867_MICR_WOL_INT_EN_SHIFT) - -/* - * XGMII_ERR_INT_EN (RW) - * - * Enable xGMII Error Interrupt: - * 1 = Enable xGMII Error Interrupt. - * 0 = Disable xGMII Error Interrupt. - */ -#define DP83867_MICR_XGMII_ERR_INT_EN_MASK (0x4U) -#define DP83867_MICR_XGMII_ERR_INT_EN_SHIFT (2U) -#define DP83867_MICR_XGMII_ERR_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) -#define DP83867_MICR_XGMII_ERR_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_XGMII_ERR_INT_EN_MASK) >> DP83867_MICR_XGMII_ERR_INT_EN_SHIFT) - -/* - * POLARITY_CHNG_INT_EN (RW) - * - * Enable Polarity Change Interrupt: - * 1 = Enable Polarity Change interrupt. - * 0 = Disable Polarity Change interrupt. - */ -#define DP83867_MICR_POLARITY_CHNG_INT_EN_MASK (0x2U) -#define DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT (1U) -#define DP83867_MICR_POLARITY_CHNG_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) -#define DP83867_MICR_POLARITY_CHNG_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_POLARITY_CHNG_INT_EN_MASK) >> DP83867_MICR_POLARITY_CHNG_INT_EN_SHIFT) - -/* - * JABBER_INT_EN (RW) - * - * Enable Jabber Interrupt: - * 1 = Enable Jabber interrupt. - * 0 = Disable Jabber interrupt. - */ -#define DP83867_MICR_JABBER_INT_EN_MASK (0x1U) -#define DP83867_MICR_JABBER_INT_EN_SHIFT (0U) -#define DP83867_MICR_JABBER_INT_EN_SET(x) (((uint16_t)(x) << DP83867_MICR_JABBER_INT_EN_SHIFT) & DP83867_MICR_JABBER_INT_EN_MASK) -#define DP83867_MICR_JABBER_INT_EN_GET(x) (((uint16_t)(x) & DP83867_MICR_JABBER_INT_EN_MASK) >> DP83867_MICR_JABBER_INT_EN_SHIFT) - -/* Bitfield definition for register: ISR */ -/* - * AUTONEG_ERR_INT (RO, LH, COR) - * - * Auto-Negotiation Error Interrupt: - * 1 = Auto-Negotiation Error interrupt is pending and is cleared by the - * current read. - * 0 = No Auto-Negotiation Error interrupt. - */ -#define DP83867_ISR_AUTONEG_ERR_INT_MASK (0x8000U) -#define DP83867_ISR_AUTONEG_ERR_INT_SHIFT (15U) -#define DP83867_ISR_AUTONEG_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_ERR_INT_MASK) >> DP83867_ISR_AUTONEG_ERR_INT_SHIFT) - -/* - * SPEED_CHNG_INT (RO, LH, COR) - * - * Speed Change Interrupt: - * 1 = Speed Change interrupt is pending and is cleared by the current - * read. - * 0 = No Speed Change interrupt. - */ -#define DP83867_ISR_SPEED_CHNG_INT_MASK (0x4000U) -#define DP83867_ISR_SPEED_CHNG_INT_SHIFT (14U) -#define DP83867_ISR_SPEED_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_CHNG_INT_MASK) >> DP83867_ISR_SPEED_CHNG_INT_SHIFT) - -/* - * DUPLEX_MODE_CHNG_INT (RO, LH, COR) - * - * Duplex Mode Change Interrupt: - * 1 = Duplex Mode Change interrupt is pending and is cleared by the - * current read. - * 0 = No Duplex Mode Change interrupt. - */ -#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK (0x2000U) -#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT (13U) -#define DP83867_ISR_DUPLEX_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_DUPLEX_MODE_CHNG_INT_MASK) >> DP83867_ISR_DUPLEX_MODE_CHNG_INT_SHIFT) - -/* - * PAGE_RECEIVED_INT (RO, LH, COR) - * - * Page Received Interrupt: - * 1 = Page Received Interrupt is pending and is cleared by the - * current read. - * 0 = No Page Received Interrupt is pending. - */ -#define DP83867_ISR_PAGE_RECEIVED_INT_MASK (0x1000U) -#define DP83867_ISR_PAGE_RECEIVED_INT_SHIFT (12U) -#define DP83867_ISR_PAGE_RECEIVED_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_PAGE_RECEIVED_INT_MASK) >> DP83867_ISR_PAGE_RECEIVED_INT_SHIFT) - -/* - * AUTONEG_COMP_INT (RO, LH, COR) - * - * Auto-Negotiation Complete Interrupt: - * 1 = Auto-Negotiation Complete Interrupt is pending and is cleared - * by the current read. - * 0 = No Auto-Negotiation Complete Interrupt is pending. - */ -#define DP83867_ISR_AUTONEG_COMP_INT_MASK (0x800U) -#define DP83867_ISR_AUTONEG_COMP_INT_SHIFT (11U) -#define DP83867_ISR_AUTONEG_COMP_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_AUTONEG_COMP_INT_MASK) >> DP83867_ISR_AUTONEG_COMP_INT_SHIFT) - -/* - * LINK_STATUS_CHNG_INT (RO, LH, COR) - * - * Link Status Change Interrupt: - * 1 = Link Status Change interrupt is pending and is cleared by the - * current read. - * 0 = No Link Status Change interrupt is pending. - */ -#define DP83867_ISR_LINK_STATUS_CHNG_INT_MASK (0x400U) -#define DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT (10U) -#define DP83867_ISR_LINK_STATUS_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_LINK_STATUS_CHNG_INT_MASK) >> DP83867_ISR_LINK_STATUS_CHNG_INT_SHIFT) - -/* - * FALSE_CARRIER_INT ( RO, LH, COR) - * - * False Carrier Interrupt: - * 1 = False Carrier interrupt is pending and is cleared by the current - * read. - * 0 = No False Carrier interrupt is pending. - */ -#define DP83867_ISR_FALSE_CARRIER_INT_MASK (0x100U) -#define DP83867_ISR_FALSE_CARRIER_INT_SHIFT (8U) -#define DP83867_ISR_FALSE_CARRIER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_FALSE_CARRIER_INT_MASK) >> DP83867_ISR_FALSE_CARRIER_INT_SHIFT) - -/* - * MDI_CROSSOVER_CHNG_INT (RO, LH, COR) - * - * MDI Crossover Change Interrupt: - * 1 = MDI Crossover Change interrupt is pending and is cleared by - * the current read. - * 0 = No MDI Crossover Change interrupt is pending. - */ -#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK (0x40U) -#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT (6U) -#define DP83867_ISR_MDI_CROSSOVER_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_MDI_CROSSOVER_CHNG_INT_MASK) >> DP83867_ISR_MDI_CROSSOVER_CHNG_INT_SHIFT) - -/* - * SPEED_OPT_EVENT_INT (RO, LH, COR) - * - * Speed Optimization Event Interrupt: - * 1 = Speed Optimization Event Interrupt is pending and is cleared by - * the current read. - * 0 = No Speed Optimization Event Interrupt is pending. - */ -#define DP83867_ISR_SPEED_OPT_EVENT_INT_MASK (0x20U) -#define DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT (5U) -#define DP83867_ISR_SPEED_OPT_EVENT_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SPEED_OPT_EVENT_INT_MASK) >> DP83867_ISR_SPEED_OPT_EVENT_INT_SHIFT) - -/* - * SLEEP_MODE_CHNG_INT (RO, LH, COR) - * - * Sleep Mode Change Interrupt: - * 1 = Sleep Mode Change Interrupt is pending and is cleared by the - * current read. - * 0 = No Sleep Mode Change Interrupt is pending. - */ -#define DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK (0x10U) -#define DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT (4U) -#define DP83867_ISR_SLEEP_MODE_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_SLEEP_MODE_CHNG_INT_MASK) >> DP83867_ISR_SLEEP_MODE_CHNG_INT_SHIFT) - -/* - * WOL_INT (RO, LH, COR) - * - * Wake-on-LAN Interrupt: - * 1 = Wake-on-LAN Interrupt is pending. - * 0 = No Wake-on-LAN Interrupt is pending. - */ -#define DP83867_ISR_WOL_INT_MASK (0x8U) -#define DP83867_ISR_WOL_INT_SHIFT (3U) -#define DP83867_ISR_WOL_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_WOL_INT_MASK) >> DP83867_ISR_WOL_INT_SHIFT) - -/* - * XGMII_ERR_INT (RO, LH, COR) - * - * xGMII Error Interrupt: - * 1 = xGMII Error Interrupt is pending and is cleared by the current - * read. - * 0 = No xGMII Error Interrupt is pending. - */ -#define DP83867_ISR_XGMII_ERR_INT_MASK (0x4U) -#define DP83867_ISR_XGMII_ERR_INT_SHIFT (2U) -#define DP83867_ISR_XGMII_ERR_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_XGMII_ERR_INT_MASK) >> DP83867_ISR_XGMII_ERR_INT_SHIFT) - -/* - * POLARITY_CHNG_INT (RO, LH, COR) - * - * Polarity Change Interrupt: - * 1 = Polarity Change interrupt is pending and is cleared by the - * current read. - * 0 = No Polarity Change interrupt is pending. - */ -#define DP83867_ISR_POLARITY_CHNG_INT_MASK (0x2U) -#define DP83867_ISR_POLARITY_CHNG_INT_SHIFT (1U) -#define DP83867_ISR_POLARITY_CHNG_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_POLARITY_CHNG_INT_MASK) >> DP83867_ISR_POLARITY_CHNG_INT_SHIFT) - -/* - * JABBER_INT (RO, LH, COR) - * - * Jabber Interrupt: - * 1 = Jabber interrupt is pending and is cleared by the current read. - * 0 = No Jabber interrupt is pending. - */ -#define DP83867_ISR_JABBER_INT_MASK (0x1U) -#define DP83867_ISR_JABBER_INT_SHIFT (0U) -#define DP83867_ISR_JABBER_INT_GET(x) (((uint16_t)(x) & DP83867_ISR_JABBER_INT_MASK) >> DP83867_ISR_JABBER_INT_SHIFT) - -/* Bitfield definition for register: CRG2 */ -/* - * INTERRUPT_POLARITY (RW) - * - * Configure Interrupt Polarity: - * 1 = Interrupt pin is active low. - * 0 = Interrupt pin is active high. - */ -#define DP83867_CRG2_INTERRUPT_POLARITY_MASK (0x2000U) -#define DP83867_CRG2_INTERRUPT_POLARITY_SHIFT (13U) -#define DP83867_CRG2_INTERRUPT_POLARITY_SET(x) (((uint16_t)(x) << DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) -#define DP83867_CRG2_INTERRUPT_POLARITY_GET(x) (((uint16_t)(x) & DP83867_CRG2_INTERRUPT_POLARITY_MASK) >> DP83867_CRG2_INTERRUPT_POLARITY_SHIFT) - -/* - * SPEED_OPT_ATTEMPT_CNT (RO) - * - * Speed Optimization Attempt Count: - * Selects the number of 1000BASE-T link establishment attempt - * failures prior to performing Speed Optimization. - * 11 = 8 - * 10 = 4 - * 01 = 2 - * 00 = 1 - */ -#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK (0xC00U) -#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT (10U) -#define DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_MASK) >> DP83867_CRG2_SPEED_OPT_ATTEMPT_CNT_SHIFT) - -/* - * SPEED_OPT_EN (RW) - * - * Speed Optimization Enable: - * 1 = Enable Speed Optimization. - * 0 = Disable Speed Optimization. - */ -#define DP83867_CRG2_SPEED_OPT_EN_MASK (0x200U) -#define DP83867_CRG2_SPEED_OPT_EN_SHIFT (9U) -#define DP83867_CRG2_SPEED_OPT_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_EN_MASK) -#define DP83867_CRG2_SPEED_OPT_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_EN_MASK) >> DP83867_CRG2_SPEED_OPT_EN_SHIFT) - -/* - * SPEED_OPT_ENHANCED_EN (RW) - * - * Speed Optimization Enhanced Mode Enable: - * In enhanced mode, speed is optimized if energy is not detected in - * channels C and D. - * 1 = Enable Speed Optimization enhanced mode. - * 0 = Disable Speed Optimization enhanced mode. - */ -#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK (0x100U) -#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT (8U) -#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) -#define DP83867_CRG2_SPEED_OPT_ENHANCED_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_ENHANCED_EN_MASK) >> DP83867_CRG2_SPEED_OPT_ENHANCED_EN_SHIFT) - -/* - * SGMII_AUTONEG_EN (RW) - * - * SGMII Auto-Negotiation Enable: - * 1 = Enable SGMII Auto-Negotaition. - * 0 = Disable SGMII Auto-Negotaition. - */ -#define DP83867_CRG2_SGMII_AUTONEG_EN_MASK (0x80U) -#define DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT (7U) -#define DP83867_CRG2_SGMII_AUTONEG_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) -#define DP83867_CRG2_SGMII_AUTONEG_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SGMII_AUTONEG_EN_MASK) >> DP83867_CRG2_SGMII_AUTONEG_EN_SHIFT) - -/* - * SPEED_OPT_10M_EN (RW) - * - * Enable Speed Optimization to 10BASE-Te: - * 1 = Enable speed optimization to 10BASE-Te if link establishment - * fails in 1000BASE-T and 100BASE-TX . - * 0 = Disable speed optimization to 10BASE-Te. - */ -#define DP83867_CRG2_SPEED_OPT_10M_EN_MASK (0x40U) -#define DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT (6U) -#define DP83867_CRG2_SPEED_OPT_10M_EN_SET(x) (((uint16_t)(x) << DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) -#define DP83867_CRG2_SPEED_OPT_10M_EN_GET(x) (((uint16_t)(x) & DP83867_CRG2_SPEED_OPT_10M_EN_MASK) >> DP83867_CRG2_SPEED_OPT_10M_EN_SHIFT) - -/* Bitfield definition for register: RECR */ -/* - * RXERCNT_15_0 (RO, WSC) - * - * RX_ER Counter: - * Receive error counter. This register saturates at the maximum value - * of 0xFFFF. It is cleared by dummy write to this register. - */ -#define DP83867_RECR_RXERCNT_15_0_MASK (0xFFFFU) -#define DP83867_RECR_RXERCNT_15_0_SHIFT (0U) -#define DP83867_RECR_RXERCNT_15_0_SET(x) (((uint16_t)(x) << DP83867_RECR_RXERCNT_15_0_SHIFT) & DP83867_RECR_RXERCNT_15_0_MASK) -#define DP83867_RECR_RXERCNT_15_0_GET(x) (((uint16_t)(x) & DP83867_RECR_RXERCNT_15_0_MASK) >> DP83867_RECR_RXERCNT_15_0_SHIFT) - -/* Bitfield definition for register: STS2 */ -/* - * PRBS_LOCK (RO) - * - * PRBS Lock Status: - * 1 = PRBS checker is locked to the received byte stream. - * 0 = PRBS checker is not locked. - */ -#define DP83867_STS2_PRBS_LOCK_MASK (0x800U) -#define DP83867_STS2_PRBS_LOCK_SHIFT (11U) -#define DP83867_STS2_PRBS_LOCK_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_MASK) >> DP83867_STS2_PRBS_LOCK_SHIFT) - -/* - * PRBS_LOCK_LOST (RO, LH, COR) - * - * PRBS Lock Lost: - * 1 = PRBS checker has lost lock. - * 0 = PRBS checker has not lost lock. - */ -#define DP83867_STS2_PRBS_LOCK_LOST_MASK (0x400U) -#define DP83867_STS2_PRBS_LOCK_LOST_SHIFT (10U) -#define DP83867_STS2_PRBS_LOCK_LOST_GET(x) (((uint16_t)(x) & DP83867_STS2_PRBS_LOCK_LOST_MASK) >> DP83867_STS2_PRBS_LOCK_LOST_SHIFT) - -/* - * PKT_GEN_BUSY (RO) - * - * Packet Generator Busy: - * 1 = Packet generation is in process. - * 0 = Packet generation is not in process. - */ -#define DP83867_STS2_PKT_GEN_BUSY_MASK (0x200U) -#define DP83867_STS2_PKT_GEN_BUSY_SHIFT (9U) -#define DP83867_STS2_PKT_GEN_BUSY_GET(x) (((uint16_t)(x) & DP83867_STS2_PKT_GEN_BUSY_MASK) >> DP83867_STS2_PKT_GEN_BUSY_SHIFT) - -/* - * SCR_MODE_MASTER_1G (RO) - * - * Gigabit Master Scramble Mode: - * 1 = 1G PCS (master) is in legacy encoding mode. - * 0 = 1G PCS (master) is in normal encoding mode.. - */ -#define DP83867_STS2_SCR_MODE_MASTER_1G_MASK (0x100U) -#define DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT (8U) -#define DP83867_STS2_SCR_MODE_MASTER_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_MASTER_1G_MASK) >> DP83867_STS2_SCR_MODE_MASTER_1G_SHIFT) - -/* - * SCR_MODE_SLAVE_1G (RO) - * - * Gigabit Slave Scramble Mode: - * 1 = 1G PCS (slave) is in legacy encoding mode. - * 0 = 1G PCS (slave) is in normal encoding mode.. - */ -#define DP83867_STS2_SCR_MODE_SLAVE_1G_MASK (0x80U) -#define DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT (7U) -#define DP83867_STS2_SCR_MODE_SLAVE_1G_GET(x) (((uint16_t)(x) & DP83867_STS2_SCR_MODE_SLAVE_1G_MASK) >> DP83867_STS2_SCR_MODE_SLAVE_1G_SHIFT) - -/* - * CORE_PWR_MODE (RO) - * - * Core Power Mode: - * 1 = Core is in normal power mode. - * 0 = Core is power-down mode or in sleep mode. - */ -#define DP83867_STS2_CORE_PWR_MODE_MASK (0x40U) -#define DP83867_STS2_CORE_PWR_MODE_SHIFT (6U) -#define DP83867_STS2_CORE_PWR_MODE_GET(x) (((uint16_t)(x) & DP83867_STS2_CORE_PWR_MODE_MASK) >> DP83867_STS2_CORE_PWR_MODE_SHIFT) - -/* Bitfield definition for register: LEDCR1 */ -/* - * LED_GPIO_SEL (RW) - * - * Source of the GPIO LED_3: - * 1111: Reserved - * 1110: Receive Error - * 1101: Receive Error or Transmit Error - * 1100: RESERVED - * 1011: Link established, blink for transmit or receive activity - * 1010: Full duplex - * 1001: 100/1000BT link established - * 1000: 10/100BT link established - * 0111: 10BT link established - * 0110: 100 BTX link established - * 0101: 1000BT link established - * 0100: Collision detected - * 0011: Receive activity - * 0010: Transmit activity - * 0001: Receive or Transmit activity - * 0000: Link established - */ -#define DP83867_LEDCR1_LED_GPIO_SEL_MASK (0xF000U) -#define DP83867_LEDCR1_LED_GPIO_SEL_SHIFT (12U) -#define DP83867_LEDCR1_LED_GPIO_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) -#define DP83867_LEDCR1_LED_GPIO_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_GPIO_SEL_MASK) >> DP83867_LEDCR1_LED_GPIO_SEL_SHIFT) - -/* - * LED_2_SEL (RW) - * - * Source of LED_2: - * 1111: Reserved - * 1110: Receive Error - * 1101: Receive Error or Transmit Error - * 1100: RESERVED - * 1011: Link established, blink for transmit or receive activity - * 1010: Full duplex - * 1001: 100/1000BT link established - * 1000: 10/100BT link established - * 0111: 10BT link established - * 0110: 100 BTX link established - * 0101: 1000BT link established - * 0100: Collision detected - * 0011: Receive activity - * 0010: Transmit activity - * 0001: Receive or Transmit activity - * 0000: Link established - */ -#define DP83867_LEDCR1_LED_2_SEL_MASK (0xF00U) -#define DP83867_LEDCR1_LED_2_SEL_SHIFT (8U) -#define DP83867_LEDCR1_LED_2_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_2_SEL_SHIFT) & DP83867_LEDCR1_LED_2_SEL_MASK) -#define DP83867_LEDCR1_LED_2_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_2_SEL_MASK) >> DP83867_LEDCR1_LED_2_SEL_SHIFT) - -/* - * LED_1_SEL (RW) - * - * Source of LED_1: - * 1111: Reserved - * 1110: Receive Error - * 1101: Receive Error or Transmit Error - * 1100: RESERVED - * 1011: Link established, blink for transmit or receive activity - * 1010: Full duplex - * 1001: 100/1000BT link established - * 1000: 10/100BT link established - * 0111: 10BT link established - * 0110: 100 BTX link established - * 0101: 1000BT link established - * 0100: Collision detected - * 0011: Receive activity - * 0010: Transmit activity - * 0001: Receive or Transmit activity - * 0000: Link established - */ -#define DP83867_LEDCR1_LED_1_SEL_MASK (0xF0U) -#define DP83867_LEDCR1_LED_1_SEL_SHIFT (4U) -#define DP83867_LEDCR1_LED_1_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_1_SEL_SHIFT) & DP83867_LEDCR1_LED_1_SEL_MASK) -#define DP83867_LEDCR1_LED_1_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_1_SEL_MASK) >> DP83867_LEDCR1_LED_1_SEL_SHIFT) - -/* - * LED_0_SEL (RW) - * - * Source of LED_0: - * 1111: Reserved - * 1110: Receive Error - * 1101: Receive Error or Transmit Error - * 1100: RESERVED - * 1011: Link established, blink for transmit or receive activity - * 1010: Full duplex - * 1001: 100/1000BT link established - * 1000: 10/100BT link established - * 0111: 10BT link established - * 0110: 100 BTX link established - * 0101: 1000BT link established - * 0100: Collision detected - * 0011: Receive activity - * 0010: Transmit activity - * 0001: Receive or Transmit activity - * 0000: Link established - */ -#define DP83867_LEDCR1_LED_0_SEL_MASK (0xFU) -#define DP83867_LEDCR1_LED_0_SEL_SHIFT (0U) -#define DP83867_LEDCR1_LED_0_SEL_SET(x) (((uint16_t)(x) << DP83867_LEDCR1_LED_0_SEL_SHIFT) & DP83867_LEDCR1_LED_0_SEL_MASK) -#define DP83867_LEDCR1_LED_0_SEL_GET(x) (((uint16_t)(x) & DP83867_LEDCR1_LED_0_SEL_MASK) >> DP83867_LEDCR1_LED_0_SEL_SHIFT) - -/* Bitfield definition for register: LEDCR2 */ -/* - * LED_GPIO_POLARITY (RW) - * - * GPIO LED Polarity: - * 1 = Active high - * 0 = Active low - */ -#define DP83867_LEDCR2_LED_GPIO_POLARITY_MASK (0x4000U) -#define DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT (14U) -#define DP83867_LEDCR2_LED_GPIO_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) -#define DP83867_LEDCR2_LED_GPIO_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_POLARITY_MASK) >> DP83867_LEDCR2_LED_GPIO_POLARITY_SHIFT) - -/* - * LED_GPIO_DRV_VAL (RW) - * - * GPIO LED Drive Value: - * Value to force on GPIO LED - * This bit is only valid if enabled through LED_GPIO_DRV_EN. - */ -#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK (0x2000U) -#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT (13U) -#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) -#define DP83867_LEDCR2_LED_GPIO_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_VAL_SHIFT) - -/* - * LED_GPIO_DRV_EN (RW) - * - * GPIO LED Drive Enable: - * 1 = Force the value of the LED_GPIO_DRV_VAL bit onto the GPIO - * LED. - * 0 = Normal operation - */ -#define DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK (0x1000U) -#define DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT (12U) -#define DP83867_LEDCR2_LED_GPIO_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) -#define DP83867_LEDCR2_LED_GPIO_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_GPIO_DRV_EN_MASK) >> DP83867_LEDCR2_LED_GPIO_DRV_EN_SHIFT) - -/* - * LED_2_POLARITY (RW) - * - * LED_2 Polarity: - * 1 = Active high - * 0 = Active low - */ -#define DP83867_LEDCR2_LED_2_POLARITY_MASK (0x400U) -#define DP83867_LEDCR2_LED_2_POLARITY_SHIFT (10U) -#define DP83867_LEDCR2_LED_2_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_POLARITY_SHIFT) & DP83867_LEDCR2_LED_2_POLARITY_MASK) -#define DP83867_LEDCR2_LED_2_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_POLARITY_MASK) >> DP83867_LEDCR2_LED_2_POLARITY_SHIFT) - -/* - * LED_2_DRV_VAL (RW) - * - * LED_2 Drive Value: - * Value to force on LED_2 - * This bit is only valid if enabled through LED_2_DRV_EN. - */ -#define DP83867_LEDCR2_LED_2_DRV_VAL_MASK (0x200U) -#define DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT (9U) -#define DP83867_LEDCR2_LED_2_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) -#define DP83867_LEDCR2_LED_2_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_2_DRV_VAL_SHIFT) - -/* - * LED_2_DRV_EN (RW) - * - * LED_2 Drive Enable: - * 1 = Force the value of the LED_2_DRV_VAL bit onto LED_2. - * 0 = Normal operation - */ -#define DP83867_LEDCR2_LED_2_DRV_EN_MASK (0x100U) -#define DP83867_LEDCR2_LED_2_DRV_EN_SHIFT (8U) -#define DP83867_LEDCR2_LED_2_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) -#define DP83867_LEDCR2_LED_2_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_2_DRV_EN_MASK) >> DP83867_LEDCR2_LED_2_DRV_EN_SHIFT) - -/* - * LED_1_POLARITY (RW) - * - * LED_1 Polarity: - * 1 = Active high - * 0 = Active low - */ -#define DP83867_LEDCR2_LED_1_POLARITY_MASK (0x40U) -#define DP83867_LEDCR2_LED_1_POLARITY_SHIFT (6U) -#define DP83867_LEDCR2_LED_1_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_POLARITY_SHIFT) & DP83867_LEDCR2_LED_1_POLARITY_MASK) -#define DP83867_LEDCR2_LED_1_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_POLARITY_MASK) >> DP83867_LEDCR2_LED_1_POLARITY_SHIFT) - -/* - * LED_1_DRV_VAL (RW) - * - * LED_1 Drive Value: - * Value to force on LED_1 - * This bit is only valid if enabled through LED_1_DRV_EN. - */ -#define DP83867_LEDCR2_LED_1_DRV_VAL_MASK (0x20U) -#define DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT (5U) -#define DP83867_LEDCR2_LED_1_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) -#define DP83867_LEDCR2_LED_1_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_1_DRV_VAL_SHIFT) - -/* - * LED_1_DRV_EN (RW) - * - * LED_1 Drive Enable: - * 1 = Force the value of the LED_1_DRV_VAL bit onto LED_1. - * 0 = Normal operation - */ -#define DP83867_LEDCR2_LED_1_DRV_EN_MASK (0x10U) -#define DP83867_LEDCR2_LED_1_DRV_EN_SHIFT (4U) -#define DP83867_LEDCR2_LED_1_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) -#define DP83867_LEDCR2_LED_1_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_1_DRV_EN_MASK) >> DP83867_LEDCR2_LED_1_DRV_EN_SHIFT) - -/* - * LED_0_POLARITY (RW) - * - * LED_0 Polarity: - * 1 = Active high - * 0 = Active low - */ -#define DP83867_LEDCR2_LED_0_POLARITY_MASK (0x4U) -#define DP83867_LEDCR2_LED_0_POLARITY_SHIFT (2U) -#define DP83867_LEDCR2_LED_0_POLARITY_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_POLARITY_SHIFT) & DP83867_LEDCR2_LED_0_POLARITY_MASK) -#define DP83867_LEDCR2_LED_0_POLARITY_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_POLARITY_MASK) >> DP83867_LEDCR2_LED_0_POLARITY_SHIFT) - -/* - * LED_0_DRV_VAL (RW) - * - * LED_0 Drive Value: - * Value to force on LED_0 - * This bit is only valid if enabled through LED_0_DRV_EN. - */ -#define DP83867_LEDCR2_LED_0_DRV_VAL_MASK (0x2U) -#define DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT (1U) -#define DP83867_LEDCR2_LED_0_DRV_VAL_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) -#define DP83867_LEDCR2_LED_0_DRV_VAL_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_VAL_MASK) >> DP83867_LEDCR2_LED_0_DRV_VAL_SHIFT) - -/* - * LED_0_DRV_EN (RW) - * - * LED_0 Drive Enable: - * 1 = Force the value of the LED_0_DRV_VAL bit onto LED_0. - * 0 = Normal operation - */ -#define DP83867_LEDCR2_LED_0_DRV_EN_MASK (0x1U) -#define DP83867_LEDCR2_LED_0_DRV_EN_SHIFT (0U) -#define DP83867_LEDCR2_LED_0_DRV_EN_SET(x) (((uint16_t)(x) << DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) -#define DP83867_LEDCR2_LED_0_DRV_EN_GET(x) (((uint16_t)(x) & DP83867_LEDCR2_LED_0_DRV_EN_MASK) >> DP83867_LEDCR2_LED_0_DRV_EN_SHIFT) - -/* Bitfield definition for register: LEDCR3 */ -/* - * LEDS_BYPASS_STRETCHING (RW) - * - * Bypass LED Stretching: - * 1 = Bypass LED Stretching - * 0 = Normal operation - */ -#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK (0x4U) -#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT (2U) -#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) -#define DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_MASK) >> DP83867_LEDCR3_LEDS_BYPASS_STRETCHING_SHIFT) - -/* - * LEDS_BLINK_RATE (RW) - * - * LED Blink Rate: - * 11: 2 Hz (500 ms) - * 10: 5 Hz (200 ms) - * 01: 10 Hz (100 ms) - * 00 = 20 Hz (50 ms) - */ -#define DP83867_LEDCR3_LEDS_BLINK_RATE_MASK (0x3U) -#define DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT (0U) -#define DP83867_LEDCR3_LEDS_BLINK_RATE_SET(x) (((uint16_t)(x) << DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) -#define DP83867_LEDCR3_LEDS_BLINK_RATE_GET(x) (((uint16_t)(x) & DP83867_LEDCR3_LEDS_BLINK_RATE_MASK) >> DP83867_LEDCR3_LEDS_BLINK_RATE_SHIFT) - -/* Bitfield definition for register: CFG3 */ -/* - * FAST_LINK_UP_IN_PARALLEL_DETECT (RW) - * - * Fast Link-Up in Parallel Detect Mode: - * 1 = Enable Fast Link-Up time During Parallel Detection - * 0 = Normal Parallel Detection link establishment - * In Fast Auto MDI-X this bit is automatically set. - */ -#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK (0x8000U) -#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT (15U) -#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) -#define DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_MASK) >> DP83867_CFG3_FAST_LINK_UP_IN_PARALLEL_DETECT_SHIFT) - -/* - * FAST_AN_ENABLE (RW) - * - * Fast Auto-Negotiation Enable: - * 1 = Enable Fast Auto-Negotiation mode – The PHY auto- - * negotiates using Timer setting according to Fast AN Sel bits - * 0 = Disable Fast Auto-Negotiation mode – The PHY auto- - * negotiates using normal Timer setting - * Adjusting these bits reduces the time it takes to Auto-negotiate - * between two PHYs. Note: When using this option care must be - * taken to maintain proper operation of the system. While shortening - * these timer intervals may not cause problems in normal operation, - * there are certain situations where this may lead to problems. - */ -#define DP83867_CFG3_FAST_AN_ENABLE_MASK (0x4000U) -#define DP83867_CFG3_FAST_AN_ENABLE_SHIFT (14U) -#define DP83867_CFG3_FAST_AN_ENABLE_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_ENABLE_SHIFT) & DP83867_CFG3_FAST_AN_ENABLE_MASK) -#define DP83867_CFG3_FAST_AN_ENABLE_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_ENABLE_MASK) >> DP83867_CFG3_FAST_AN_ENABLE_SHIFT) - -/* - * FAST_AN_SEL (RW) - * - * Fast Auto-Negotiation Select bits: - * Fast AN Select Break Link Timer(ms) Link Fail Inhibit TImer(ms) Auto-Neg Wait Timer(ms) - * <00> 80 50 35 - * <01> 120 75 50 - * <10> 240 150 100 - * <11> NA NA NA - * Adjusting these bits reduces the time it takes to auto-negotiate - * between two PHYs. In Fast AN mode, both PHYs should be - * configured to the same configuration. These 2 bits define the - * duration for each state of the Auto-Negotiation process according - * to the table above. The new duration time must be enabled by - * setting Fast AN En - bit 4 of this register. Note: Using this mode in - * cases where both link partners are not configured to the same - * Fast Auto-Negotiation configuration might produce scenarios with - * unexpected behavior. - */ -#define DP83867_CFG3_FAST_AN_SEL_MASK (0x3000U) -#define DP83867_CFG3_FAST_AN_SEL_SHIFT (12U) -#define DP83867_CFG3_FAST_AN_SEL_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AN_SEL_SHIFT) & DP83867_CFG3_FAST_AN_SEL_MASK) -#define DP83867_CFG3_FAST_AN_SEL_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AN_SEL_MASK) >> DP83867_CFG3_FAST_AN_SEL_SHIFT) - -/* - * EXTENDED_FD_ABILITY (RW) - * - * Extended Full-Duplex Ability: - * 1 = Force Full-Duplex while working with link partner in forced - * 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B- - * TX and the link partner is operated in Force 100B-TX, the link is - * always Full Duplex - * 0 = Disable Extended Full Duplex Ability. Decision to work in Full - * Duplex or Half Duplex mode follows IEEE specification. - */ -#define DP83867_CFG3_EXTENDED_FD_ABILITY_MASK (0x800U) -#define DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT (11U) -#define DP83867_CFG3_EXTENDED_FD_ABILITY_SET(x) (((uint16_t)(x) << DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) -#define DP83867_CFG3_EXTENDED_FD_ABILITY_GET(x) (((uint16_t)(x) & DP83867_CFG3_EXTENDED_FD_ABILITY_MASK) >> DP83867_CFG3_EXTENDED_FD_ABILITY_SHIFT) - -/* - * ROBUST_AUTO_MDIX (RW) - * - * Robust Auto-MDIX: - * 1 =Enable Robust Auto MDI/MDIX resolution - * 0 = Normal Auto MDI/MDIX mode - * If link partners are configured to operational modes that are not - * supported by normal Auto MDI/MDIX mode (like Auto-Neg versus - * Force 100Base-TX or Force 100Base-TX versus Force 100Base- - * TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX - * resolution and prevents deadlock. - */ -#define DP83867_CFG3_ROBUST_AUTO_MDIX_MASK (0x200U) -#define DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT (9U) -#define DP83867_CFG3_ROBUST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) -#define DP83867_CFG3_ROBUST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_ROBUST_AUTO_MDIX_MASK) >> DP83867_CFG3_ROBUST_AUTO_MDIX_SHIFT) - -/* - * FAST_AUTO_MDIX (RW) - * - * Fast Auto MDI/MDIX: - * 1 = Enable Fast Auto MDI/MDIX mode - * 0 = Normal Auto MDI/MDIX mode - * If both link partners are configured to work in Force 100Base-TX - * mode (Auto-Negotiation is disabled), this mode enables Automatic - * MDI/MDIX resolution in a short time. - */ -#define DP83867_CFG3_FAST_AUTO_MDIX_MASK (0x100U) -#define DP83867_CFG3_FAST_AUTO_MDIX_SHIFT (8U) -#define DP83867_CFG3_FAST_AUTO_MDIX_SET(x) (((uint16_t)(x) << DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) -#define DP83867_CFG3_FAST_AUTO_MDIX_GET(x) (((uint16_t)(x) & DP83867_CFG3_FAST_AUTO_MDIX_MASK) >> DP83867_CFG3_FAST_AUTO_MDIX_SHIFT) - -/* - * INT_OE (RW) - * - * Interrupt Output Enable: - * 1 = INTN/PWDNN Pad is an Interrupt Output. - * 0 = INTN/PWDNN Pad in a Power-Down Input. - */ -#define DP83867_CFG3_INT_OE_MASK (0x80U) -#define DP83867_CFG3_INT_OE_SHIFT (7U) -#define DP83867_CFG3_INT_OE_SET(x) (((uint16_t)(x) << DP83867_CFG3_INT_OE_SHIFT) & DP83867_CFG3_INT_OE_MASK) -#define DP83867_CFG3_INT_OE_GET(x) (((uint16_t)(x) & DP83867_CFG3_INT_OE_MASK) >> DP83867_CFG3_INT_OE_SHIFT) - -/* - * FORCE_INTERRUPT (RW) - * - * Force Interrupt: - * 1 = Assert interrupt pin. - * 0 = Normal interrupt mode. - */ -#define DP83867_CFG3_FORCE_INTERRUPT_MASK (0x40U) -#define DP83867_CFG3_FORCE_INTERRUPT_SHIFT (6U) -#define DP83867_CFG3_FORCE_INTERRUPT_SET(x) (((uint16_t)(x) << DP83867_CFG3_FORCE_INTERRUPT_SHIFT) & DP83867_CFG3_FORCE_INTERRUPT_MASK) -#define DP83867_CFG3_FORCE_INTERRUPT_GET(x) (((uint16_t)(x) & DP83867_CFG3_FORCE_INTERRUPT_MASK) >> DP83867_CFG3_FORCE_INTERRUPT_SHIFT) - -/* - * TDR_FAIL (RO) - * - * TDR Failure: - * 1 = TDR failed. - * 0 = Normal TDR operation. - */ -#define DP83867_CFG3_TDR_FAIL_MASK (0x4U) -#define DP83867_CFG3_TDR_FAIL_SHIFT (2U) -#define DP83867_CFG3_TDR_FAIL_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_FAIL_MASK) >> DP83867_CFG3_TDR_FAIL_SHIFT) - -/* - * TDR_DONE (RO) - * - * TDR Done: - * 1 = TDR has completed. - * 0 = TDR has not completed. - */ -#define DP83867_CFG3_TDR_DONE_MASK (0x2U) -#define DP83867_CFG3_TDR_DONE_SHIFT (1U) -#define DP83867_CFG3_TDR_DONE_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_DONE_MASK) >> DP83867_CFG3_TDR_DONE_SHIFT) - -/* - * TDR_START (RW) - * - * TDR Start: - * 1 = Start TDR. - * 0 = Normal operation - */ -#define DP83867_CFG3_TDR_START_MASK (0x1U) -#define DP83867_CFG3_TDR_START_SHIFT (0U) -#define DP83867_CFG3_TDR_START_SET(x) (((uint16_t)(x) << DP83867_CFG3_TDR_START_SHIFT) & DP83867_CFG3_TDR_START_MASK) -#define DP83867_CFG3_TDR_START_GET(x) (((uint16_t)(x) & DP83867_CFG3_TDR_START_MASK) >> DP83867_CFG3_TDR_START_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * SW_RESET (RW,SC) - * - * Software Reset: - * 1 = Perform a full reset, including registers. - * 0 = Normal operation. - */ -#define DP83867_CTRL_SW_RESET_MASK (0x8000U) -#define DP83867_CTRL_SW_RESET_SHIFT (15U) -#define DP83867_CTRL_SW_RESET_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESET_SHIFT) & DP83867_CTRL_SW_RESET_MASK) -#define DP83867_CTRL_SW_RESET_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESET_MASK) >> DP83867_CTRL_SW_RESET_SHIFT) - -/* - * SW_RESTART (RW,SC) - * - * Software Restart: - * 1 = Perform a full reset, not including registers. . - * 0 = Normal operation. - */ -#define DP83867_CTRL_SW_RESTART_MASK (0x4000U) -#define DP83867_CTRL_SW_RESTART_SHIFT (14U) -#define DP83867_CTRL_SW_RESTART_SET(x) (((uint16_t)(x) << DP83867_CTRL_SW_RESTART_SHIFT) & DP83867_CTRL_SW_RESTART_MASK) -#define DP83867_CTRL_SW_RESTART_GET(x) (((uint16_t)(x) & DP83867_CTRL_SW_RESTART_MASK) >> DP83867_CTRL_SW_RESTART_SHIFT) - -/* Bitfield definition for register: RGMIIDCTL */ -/* - * RGMII_TX_DELAY_CTRL (RW) - * - * RGMII Transmit Clock Delay: - * 1111: 4.00 ns - * 1110: 3.75 ns - * 1101: 3.50 ns - * 1100: 3.25 ns - * 1011: 3.00 ns - * 1010: 2.75 ns - * 1001: 2.50 ns - * 1000: 2.25 ns - * 0111: 2.00 ns - * 0110: 1.75 ns - * 0101: 1.50 ns - * 0100: 1.25 ns - * 0011: 1.00 ns - * 0010: 0.75 ns - * 0001: 0.50 ns - * 0000: 0.25 ns - */ -#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK (0xF0U) -#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT (4U) -#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) -#define DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_TX_DELAY_CTRL_SHIFT) - -/* - * RGMII_RX_DELAY_CTRL (RW) - * - * RGMII Receive Clock Delay: - * 1111: 4.00 ns - * 1110: 3.75 ns - * 1101: 3.50 ns - * 1100: 3.25 ns - * 1011: 3.00 ns - * 1010: 2.75 ns - * 1001: 2.50 ns - * 1000: 2.25 ns - * 0111: 2.00 ns - * 0110: 1.75 ns - * 0101: 1.50 ns - * 0100: 1.25 ns - * 0011: 1.00 ns - * 0010: 0.75 ns - * 0001: 0.50 ns - * 0000: 0.25 ns - */ -#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK (0xFU) -#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT (0U) -#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SET(x) (((uint16_t)(x) << DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) -#define DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_GET(x) (((uint16_t)(x) & DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_MASK) >> DP83867_RGMIIDCTL_RGMII_RX_DELAY_CTRL_SHIFT) - - - - -#endif /* HPM_DP83867_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h deleted file mode 100644 index 5047258dbc4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ENET_PHY_H -#define HPM_ENET_PHY_H -#include - -typedef enum { - enet_phy_link_down = 0, - enet_phy_link_up -} enet_phy_link_status_t; - -typedef enum { - enet_phy_port_speed_10mbps = 0, - enet_phy_port_speed_100mbps, - enet_phy_port_speed_1000mbps -} enet_phy_port_speed_t; - -typedef enum { - enet_phy_duplex_half = 0, - enet_phy_duplex_full -} enet_phy_duplex_mode_t; - -typedef enum { - enet_phy_mdi_crossover_manual_mdi = 0, - enet_phy_mdi_crossover_manual_mdix, - enet_phy_mdi_crossover_automatic -} enet_phy_crossover_mode_t; - -typedef struct { - uint8_t enet_phy_link; - uint8_t enet_phy_speed; - uint8_t enet_phy_duplex; -} enet_phy_status_t; - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h deleted file mode 100644 index 0996a0e692a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ENET_PHY_COMMON_H -#define HPM_ENET_PHY_COMMON_H - -#if defined(__USE_DP83867) && __USE_DP83867 - #include "hpm_dp83867.h" - #include "hpm_dp83867_regs.h" -#endif - -#if defined(__USE_RTL8211) && __USE_RTL8211 - #include "hpm_rtl8211.h" - #include "hpm_rtl8211_regs.h" -#endif - -#if defined(__USE_DP83848) && __USE_DP83848 - #include "hpm_dp83848.h" - #include "hpm_dp83848_regs.h" -#endif - -#if defined(__USE_RTL8201) && __USE_RTL8201 - #include "hpm_rtl8201.h" - #include "hpm_rtl8201_regs.h" -#endif - -#if defined(__USE_LAN8720) && __USE_LAN8720 - #include "hpm_lan8720.h" - #include "hpm_lan8720_regs.h" -#endif - -#if defined(__USE_JL1111) && __USE_JL1111 - #include "hpm_jl1111.h" - #include "hpm_jl1111_regs.h" -#endif - - -#endif /* HPM_ENET_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.c deleted file mode 100644 index e66efff2e5d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_jl1111_regs.h" -#include "hpm_jl1111.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -static bool jl1111_check_id(ENET_Type *ptr) -{ - uint16_t id1, id2; - - id1 = enet_read_phy(ptr, JL1111_ADDR, JL1111_PHYID1); - id2 = enet_read_phy(ptr, JL1111_ADDR, JL1111_PHYID2); - - if (JL1111_PHYID1_OUI_MSB_GET(id1) == JL1111_ID1 && JL1111_PHYID2_OUI_LSB_GET(id2) == JL1111_ID2) { - return true; - } else { - return false; - } -} - -/*--------------------------------------------------------------------- - * API - *--------------------------------------------------------------------- - */ -void jl1111_reset(ENET_Type *ptr) -{ - uint16_t data; - - /* PHY reset */ - enet_write_phy(ptr, JL1111_ADDR, JL1111_BMCR, JL1111_BMCR_RESET_SET(1)); - - /* wait until the reset is completed */ - do { - data = enet_read_phy(ptr, JL1111_ADDR, JL1111_BMCR); - } while (JL1111_BMCR_RESET_GET(data)); -} - -void jl1111_basic_mode_default_config(ENET_Type *ptr, jl1111_config_t *config) -{ - (void)ptr; - - config->loopback = false; /* Disable PCS loopback mode */ - #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) - config->auto_negotiation = false; /* Disable Auto-Negotiation */ - config->speed = enet_phy_port_speed_100mbps; - config->duplex = enet_phy_duplex_full; - #else - config->auto_negotiation = true; /* Enable Auto-Negotiation */ - #endif -} - -bool jl1111_basic_mode_init(ENET_Type *ptr, jl1111_config_t *config) -{ - uint16_t data = 0; - - data |= JL1111_BMCR_RESET_SET(0) /* Normal operation */ - | JL1111_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ - | JL1111_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ - | JL1111_BMCR_PWD_SET(0) /* Normal operation */ - | JL1111_BMCR_ISOLATE_SET(0) /* Normal operation */ - | JL1111_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | JL1111_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - - if (config->auto_negotiation == 0) { - data |= JL1111_BMCR_SPEED0_SET(config->speed); /* Set port speed */ - data |= JL1111_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ - } - - /* check the id of jl1111 */ - if (jl1111_check_id(ptr) == false) { - return false; - } - - enet_write_phy(ptr, JL1111_ADDR, JL1111_BMCR, data); - - return true; -} - -void jl1111_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) -{ - uint16_t data, anar, anlpar; - - data = enet_read_phy(ptr, JL1111_ADDR, JL1111_BMSR); - status->enet_phy_link = JL1111_BMSR_LINK_STATUS_GET(data); - - anar = enet_read_phy(ptr, JL1111_ADDR, JL1111_ANAR); - anlpar = enet_read_phy(ptr, JL1111_ADDR, JL1111_ANLPAR); - data = anar & anlpar; - - if (JL1111_ANAR_100BASE_TX_GET(data)) { - if (JL1111_ANAR_100BASE_TX_FD_GET(data)) { - status->enet_phy_speed = enet_phy_port_speed_100mbps; - status->enet_phy_duplex = enet_phy_duplex_full; - } else { - status->enet_phy_speed = enet_phy_port_speed_100mbps; - status->enet_phy_duplex = enet_phy_duplex_half; - } - } else if (JL1111_ANAR_10BASE_T_GET(data)) { - if (JL1111_ANAR_10BASE_T_FD_GET(data)) { - status->enet_phy_speed = enet_phy_port_speed_10mbps; - status->enet_phy_duplex = enet_phy_duplex_full; - } else { - status->enet_phy_speed = enet_phy_port_speed_10mbps; - status->enet_phy_duplex = enet_phy_duplex_half; - } - } else { - - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.h deleted file mode 100644 index b16e6c28e20..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_JL1111_H -#define HPM_JL1111_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_phy.h" -#include "hpm_common.h" -#include "hpm_enet_regs.h" -/*--------------------------------------------------------------------- - * Macro Const Definitions - *--------------------------------------------------------------------- - */ -#ifndef JL1111_ADDR -#define JL1111_ADDR (0U) -#endif - -#define JL1111_ID1 (0x937CU) -#define JL1111_ID2 (0x10U) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -typedef struct { - bool loopback; - uint8_t speed; - bool auto_negotiation; - uint8_t duplex; -} jl1111_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -void jl1111_reset(ENET_Type *ptr); -void jl1111_basic_mode_default_config(ENET_Type *ptr, jl1111_config_t *config); -bool jl1111_basic_mode_init(ENET_Type *ptr, jl1111_config_t *config); -void jl1111_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_JL1111_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111_regs.h deleted file mode 100644 index 4866d7ade1d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111_regs.h +++ /dev/null @@ -1,734 +0,0 @@ -/* - * Copyright (c) 2021-2024 hpmicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_JL1111_REGS_H -#define HPM_JL1111_REGS_H - -typedef enum { - JL1111_BMCR = 0, /* 0x0: Basic Mode Control Register */ - JL1111_BMSR = 1, /* 0x1: Basic Mode Status Register */ - JL1111_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ - JL1111_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ - JL1111_ANAR = 4, /* 0x4: Auto-Negotiation Advertisement Register */ - JL1111_ANLPAR = 5, /* 0x5: Auto-Negotiation Link Partner Ability Register */ - JL1111_MMDAC = 19, /* 0x13: MMD Access Control Register */ - JL1111_MMDAAD = 20, /* 0x14: MMD Access Address Data Register */ - JL1111_RMSR_P7 = 22, /* 0x16: RMII Mode Setting Register */ - JL1111_INTSQI = 48, /* 0x30: Interrupt Indicators and Signal Quality Indicator Register */ - JL1111_PAGESEL = 49, /* 0x31: Page Select Register */ -} JL1111_REG_Type; - - -/* Bitfield definition for register: BMCR */ -/* - * RESET (RW/SC) - * - * 1: PHY reset - * 0: normal operation - * After software reset, need to delay 10ms de-assert time for chip steady. - */ -#define JL1111_BMCR_RESET_MASK (0x8000U) -#define JL1111_BMCR_RESET_SHIFT (15U) -#define JL1111_BMCR_RESET_SET(x) (((uint16_t)(x) << JL1111_BMCR_RESET_SHIFT) & JL1111_BMCR_RESET_MASK) -#define JL1111_BMCR_RESET_GET(x) (((uint16_t)(x) & JL1111_BMCR_RESET_MASK) >> JL1111_BMCR_RESET_SHIFT) - -/* - * LOOPBACK (RW) - * - * This bit enables loopback of transmit data nibbles TXD3:0 to the - * receive data path. - * 1: Enable loopback 0: Normal operation - */ -#define JL1111_BMCR_LOOPBACK_MASK (0x4000U) -#define JL1111_BMCR_LOOPBACK_SHIFT (14U) -#define JL1111_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << JL1111_BMCR_LOOPBACK_SHIFT) & JL1111_BMCR_LOOPBACK_MASK) -#define JL1111_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & JL1111_BMCR_LOOPBACK_MASK) >> JL1111_BMCR_LOOPBACK_SHIFT) - -/* - * SPEED0 (RW) - * - * This bit sets the network speed. - * 1: 100Mbps 0: 10Mbps - */ -#define JL1111_BMCR_SPEED0_MASK (0x2000U) -#define JL1111_BMCR_SPEED0_SHIFT (13U) -#define JL1111_BMCR_SPEED0_SET(x) (((uint16_t)(x) << JL1111_BMCR_SPEED0_SHIFT) & JL1111_BMCR_SPEED0_MASK) -#define JL1111_BMCR_SPEED0_GET(x) (((uint16_t)(x) & JL1111_BMCR_SPEED0_MASK) >> JL1111_BMCR_SPEED0_SHIFT) - -/* - * ANE (RW) - * - * This bit enables/disables the NWay auto-negotiation function. - * 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored - * 0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the - * link speed and the data transfer mode - */ -#define JL1111_BMCR_ANE_MASK (0x1000U) -#define JL1111_BMCR_ANE_SHIFT (12U) -#define JL1111_BMCR_ANE_SET(x) (((uint16_t)(x) << JL1111_BMCR_ANE_SHIFT) & JL1111_BMCR_ANE_MASK) -#define JL1111_BMCR_ANE_GET(x) (((uint16_t)(x) & JL1111_BMCR_ANE_MASK) >> JL1111_BMCR_ANE_SHIFT) - -/* - * PWD (RW) - * - * This bit turns down the power of the PHY chip - * The MDC, MDIO is still alive for accessing the MAC. - * 1: Power down 0: Normal operation - */ -#define JL1111_BMCR_PWD_MASK (0x800U) -#define JL1111_BMCR_PWD_SHIFT (11U) -#define JL1111_BMCR_PWD_SET(x) (((uint16_t)(x) << JL1111_BMCR_PWD_SHIFT) & JL1111_BMCR_PWD_MASK) -#define JL1111_BMCR_PWD_GET(x) (((uint16_t)(x) & JL1111_BMCR_PWD_MASK) >> JL1111_BMCR_PWD_SHIFT) - -/* - * ISOLATE (RW) - * - * 1: Electrically isolate the PHY from MII/RMII - * PHY is still able to respond to MDC/MDIO. - * 0: Normal operation - */ -#define JL1111_BMCR_ISOLATE_MASK (0x400U) -#define JL1111_BMCR_ISOLATE_SHIFT (10U) -#define JL1111_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << JL1111_BMCR_ISOLATE_SHIFT) & JL1111_BMCR_ISOLATE_MASK) -#define JL1111_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & JL1111_BMCR_ISOLATE_MASK) >> JL1111_BMCR_ISOLATE_SHIFT) - -/* - * RESTART_AN (RW/SC) - * - * This bit allows the NWay auto-negotiation function to be reset. - * 1: Re-start auto-negotiation 0: Normal operation - */ -#define JL1111_BMCR_RESTART_AN_MASK (0x200U) -#define JL1111_BMCR_RESTART_AN_SHIFT (9U) -#define JL1111_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << JL1111_BMCR_RESTART_AN_SHIFT) & JL1111_BMCR_RESTART_AN_MASK) -#define JL1111_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & JL1111_BMCR_RESTART_AN_MASK) >> JL1111_BMCR_RESTART_AN_SHIFT) - -/* - * DUPLEX (RW) - * - * This bit sets the duplex mode if auto-negotiation is disabled (bit - * 0:12=0). - * 1: Full duplex 0: Half duplex - */ -#define JL1111_BMCR_DUPLEX_MASK (0x100U) -#define JL1111_BMCR_DUPLEX_SHIFT (8U) -#define JL1111_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << JL1111_BMCR_DUPLEX_SHIFT) & JL1111_BMCR_DUPLEX_MASK) -#define JL1111_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & JL1111_BMCR_DUPLEX_MASK) >> JL1111_BMCR_DUPLEX_SHIFT) - -/* - * COLLISION_TEST (RW) - * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in - * response to the TXEN assertion within 512-bit times. The COL - * signal will be de-asserted within 4-bit times in response to the - * TXEN de-assertion. - */ -#define JL1111_BMCR_COLLISION_TEST_MASK (0x80U) -#define JL1111_BMCR_COLLISION_TEST_SHIFT (7U) -#define JL1111_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << JL1111_BMCR_COLLISION_TEST_SHIFT) & JL1111_BMCR_COLLISION_TEST_MASK) -#define JL1111_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & JL1111_BMCR_COLLISION_TEST_MASK) >> JL1111_BMCR_COLLISION_TEST_SHIFT) - -/* - * SPEED1 (RW) - * - * Speed Select Bit 1. - * Refer to bit 13. - */ -#define JL1111_BMCR_SPEED1_MASK (0x40U) -#define JL1111_BMCR_SPEED1_SHIFT (6U) -#define JL1111_BMCR_SPEED1_SET(x) (((uint16_t)(x) << JL1111_BMCR_SPEED1_SHIFT) & JL1111_BMCR_SPEED1_MASK) -#define JL1111_BMCR_SPEED1_GET(x) (((uint16_t)(x) & JL1111_BMCR_SPEED1_MASK) >> JL1111_BMCR_SPEED1_SHIFT) - -/* Bitfield definition for register: BMSR */ -/* - * BASE100_T4_1 (RO) - * - * 1: Enable 100Base-T4 support - * 0: Suppress 100Base-T4 support - */ -#define JL1111_BMSR_BASE100_T4_1_MASK (0x8000U) -#define JL1111_BMSR_BASE100_T4_1_SHIFT (15U) -#define JL1111_BMSR_BASE100_T4_1_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE100_T4_1_MASK) >> JL1111_BMSR_BASE100_T4_1_SHIFT) - -/* - * BASE100_TX_FD_1 (RO) - * - * 1: Enable 100Base-TX full duplex support - * 0: Suppress 100Base-TX full duplex support - */ -#define JL1111_BMSR_BASE100_TX_FD_1_MASK (0x4000U) -#define JL1111_BMSR_BASE100_TX_FD_1_SHIFT (14U) -#define JL1111_BMSR_BASE100_TX_FD_1_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE100_TX_FD_1_MASK) >> JL1111_BMSR_BASE100_TX_FD_1_SHIFT) - -/* - * BASE100_TX_HD_1 (RO) - * - * 1: Enable 100Base-TX half duplex support - * 0: Suppress 100Base-TX half duplex support - */ -#define JL1111_BMSR_BASE100_TX_HD_1_MASK (0x2000U) -#define JL1111_BMSR_BASE100_TX_HD_1_SHIFT (13U) -#define JL1111_BMSR_BASE100_TX_HD_1_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE100_TX_HD_1_MASK) >> JL1111_BMSR_BASE100_TX_HD_1_SHIFT) - -/* - * BASE10_TX_FD (RO) - * - * 1: Enable 10Base-T full duplex support - * 0: Suppress 10Base-T full duplex support - */ -#define JL1111_BMSR_BASE10_TX_FD_MASK (0x1000U) -#define JL1111_BMSR_BASE10_TX_FD_SHIFT (12U) -#define JL1111_BMSR_BASE10_TX_FD_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE10_TX_FD_MASK) >> JL1111_BMSR_BASE10_TX_FD_SHIFT) - -/* - * BASE10_TX_HD (RO) - * - * 1: Enable 10Base-T half duplex support - * 0: Suppress 10Base-T half duplex support - */ -#define JL1111_BMSR_BASE10_TX_HD_MASK (0x800U) -#define JL1111_BMSR_BASE10_TX_HD_SHIFT (11U) -#define JL1111_BMSR_BASE10_TX_HD_GET(x) (((uint16_t)(x) & JL1111_BMSR_BASE10_TX_HD_MASK) >> JL1111_BMSR_BASE10_TX_HD_SHIFT) - -/* - * MDIO_MFPS (RO) - * - */ -#define JL1111_BMSR_MDIO_MFPS_MASK (0x40U) -#define JL1111_BMSR_MDIO_MFPS_SHIFT (6U) -#define JL1111_BMSR_MDIO_MFPS_GET(x) (((uint16_t)(x) & JL1111_BMSR_MDIO_MFPS_MASK) >> JL1111_BMSR_MDIO_MFPS_SHIFT) - -/* - * AUTO_NEGOTIATION_COMPLETE (RO) - * - * 1: Auto-negotiation process completed - * 0: Auto-negotiation process not completed - */ -#define JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) -#define JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) -#define JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> JL1111_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) - -/* - * REMOTE_FAULT (RC) - * - * 1: Remote fault condition detected (cleared on read) - * 0: No remote fault condition detected - */ -#define JL1111_BMSR_REMOTE_FAULT_MASK (0x10U) -#define JL1111_BMSR_REMOTE_FAULT_SHIFT (4U) -#define JL1111_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & JL1111_BMSR_REMOTE_FAULT_MASK) >> JL1111_BMSR_REMOTE_FAULT_SHIFT) - -/* - * AUTO_NEGOTIATION_ABILITY (RO) - * - * 1: PHY is able to perform auto-negotiation - * 0: PHY is not able to perform auto-negotiation - */ -#define JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) -#define JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) -#define JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> JL1111_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) - -/* - * LINK_STATUS (RO) - * - * 1: Valid link established - * 0: No valid link established - */ -#define JL1111_BMSR_LINK_STATUS_MASK (0x4U) -#define JL1111_BMSR_LINK_STATUS_SHIFT (2U) -#define JL1111_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & JL1111_BMSR_LINK_STATUS_MASK) >> JL1111_BMSR_LINK_STATUS_SHIFT) - -/* - * JABBER_DETECT (RO) - * - * 1: Jabber condition detected - * 0: No jabber condition detected - */ -#define JL1111_BMSR_JABBER_DETECT_MASK (0x2U) -#define JL1111_BMSR_JABBER_DETECT_SHIFT (1U) -#define JL1111_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & JL1111_BMSR_JABBER_DETECT_MASK) >> JL1111_BMSR_JABBER_DETECT_SHIFT) - -/* - * EXTENDED_CAPABILITY (RO) - * - * 1: Extended register capable (permanently=1) - * 0: Not extended register capable - */ -#define JL1111_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) -#define JL1111_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) -#define JL1111_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & JL1111_BMSR_EXTENDED_CAPABILITY_MASK) >> JL1111_BMSR_EXTENDED_CAPABILITY_SHIFT) - -/* Bitfield definition for register: PHYID1 */ -/* - * OUI_MSB (RO) - * - * JLSemi OUI is 0x24DF10 - * 0010 0100 1101 1111 0001 0000 - * BIT1.......................................................BIT24 - * Register 2.[15:0] show bit3 to 18 of OUI - * 1001 0011 0111 1100 - * BIT3................................BIT18 - */ -#define JL1111_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define JL1111_PHYID1_OUI_MSB_SHIFT (0U) -#define JL1111_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & JL1111_PHYID1_OUI_MSB_MASK) >> JL1111_PHYID1_OUI_MSB_SHIFT) - -/* Bitfield definition for register: PHYID2 */ -/* - * OUI_LSB (RO) - * - * Organizationally Unique Identifier bits 19:24 - * 01 0000 - * bit19....bit24 - */ -#define JL1111_PHYID2_OUI_LSB_MASK (0xFC00U) -#define JL1111_PHYID2_OUI_LSB_SHIFT (10U) -#define JL1111_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & JL1111_PHYID2_OUI_LSB_MASK) >> JL1111_PHYID2_OUI_LSB_SHIFT) - -/* - * MODEL_NUMBER (RO) - * - * Model Number - */ -#define JL1111_PHYID2_MODEL_NUMBER_MASK (0x3F0U) -#define JL1111_PHYID2_MODEL_NUMBER_SHIFT (4U) -#define JL1111_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & JL1111_PHYID2_MODEL_NUMBER_MASK) >> JL1111_PHYID2_MODEL_NUMBER_SHIFT) - -/* - * REVISION_NUMBER (RO) - * - * Contact JLSemi FAEs for information on the device revision number - */ -#define JL1111_PHYID2_REVISION_NUMBER_MASK (0xFU) -#define JL1111_PHYID2_REVISION_NUMBER_SHIFT (0U) -#define JL1111_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & JL1111_PHYID2_REVISION_NUMBER_MASK) >> JL1111_PHYID2_REVISION_NUMBER_SHIFT) - -/* Bitfield definition for register: ANAR */ -/* - * NEXT_PAGE (RW) - * - * Next Page Bit. - * 0: Transmitting the primary capability data page - * 1: Transmitting the protocol specific data page - */ -#define JL1111_ANAR_NEXT_PAGE_MASK (0x8000U) -#define JL1111_ANAR_NEXT_PAGE_SHIFT (15U) -#define JL1111_ANAR_NEXT_PAGE_SET(x) (((uint16_t)(x) << JL1111_ANAR_NEXT_PAGE_SHIFT) & JL1111_ANAR_NEXT_PAGE_MASK) -#define JL1111_ANAR_NEXT_PAGE_GET(x) (((uint16_t)(x) & JL1111_ANAR_NEXT_PAGE_MASK) >> JL1111_ANAR_NEXT_PAGE_SHIFT) - -/* - * ACKNOWLEDGE (RO) - * - * 1: Acknowledge reception of link partner capability data world - * 0: Do not acknowledge reception - */ -#define JL1111_ANAR_ACKNOWLEDGE_MASK (0x4000U) -#define JL1111_ANAR_ACKNOWLEDGE_SHIFT (14U) -#define JL1111_ANAR_ACKNOWLEDGE_GET(x) (((uint16_t)(x) & JL1111_ANAR_ACKNOWLEDGE_MASK) >> JL1111_ANAR_ACKNOWLEDGE_SHIFT) - -/* - * REMOTE_FAULT (RO) - * - * 1: Advertise remote fault detection capability - * 0: Do not advertise remote fault detection capability - */ -#define JL1111_ANAR_REMOTE_FAULT_MASK (0x2000U) -#define JL1111_ANAR_REMOTE_FAULT_SHIFT (13U) -#define JL1111_ANAR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & JL1111_ANAR_REMOTE_FAULT_MASK) >> JL1111_ANAR_REMOTE_FAULT_SHIFT) - -/* - * ASYMMETRIC_PAUSE (RW) - * - * Asymmetric Pause Support For Full-Duplex Links - * 1: Advertise asymmetric pause ability - * 0: Do not advertise asymmetric pause ability - */ -#define JL1111_ANAR_ASYMMETRIC_PAUSE_MASK (0x800U) -#define JL1111_ANAR_ASYMMETRIC_PAUSE_SHIFT (11U) -#define JL1111_ANAR_ASYMMETRIC_PAUSE_SET(x) (((uint16_t)(x) << JL1111_ANAR_ASYMMETRIC_PAUSE_SHIFT) & JL1111_ANAR_ASYMMETRIC_PAUSE_MASK) -#define JL1111_ANAR_ASYMMETRIC_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANAR_ASYMMETRIC_PAUSE_MASK) >> JL1111_ANAR_ASYMMETRIC_PAUSE_SHIFT) - -/* - * PAUSE (RW) - * - * Pause Support For Full-Duplex Links - * 1: Advertise pause ability - * 0: Do not advertise pause ability - */ -#define JL1111_ANAR_PAUSE_MASK (0x400U) -#define JL1111_ANAR_PAUSE_SHIFT (10U) -#define JL1111_ANAR_PAUSE_SET(x) (((uint16_t)(x) << JL1111_ANAR_PAUSE_SHIFT) & JL1111_ANAR_PAUSE_MASK) -#define JL1111_ANAR_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANAR_PAUSE_MASK) >> JL1111_ANAR_PAUSE_SHIFT) - -/* - * 100BASE_T4 (RO) - * - * 1: 100Base-T4 is supported by local node - * 0: 100Base-T4 not supported by local node - */ -#define JL1111_ANAR_100BASE_T4_MASK (0x200U) -#define JL1111_ANAR_100BASE_T4_SHIFT (9U) -#define JL1111_ANAR_100BASE_T4_GET(x) (((uint16_t)(x) & JL1111_ANAR_100BASE_T4_MASK) >> JL1111_ANAR_100BASE_T4_SHIFT) - -/* - * 100BASE_TX_FD (RW) - * - * 1: 100Base-TX full duplex is supported by local node - * 0: 100Base-TX full duplex not supported by local node - */ -#define JL1111_ANAR_100BASE_TX_FD_MASK (0x100U) -#define JL1111_ANAR_100BASE_TX_FD_SHIFT (8U) -#define JL1111_ANAR_100BASE_TX_FD_SET(x) (((uint16_t)(x) << JL1111_ANAR_100BASE_TX_FD_SHIFT) & JL1111_ANAR_100BASE_TX_FD_MASK) -#define JL1111_ANAR_100BASE_TX_FD_GET(x) (((uint16_t)(x) & JL1111_ANAR_100BASE_TX_FD_MASK) >> JL1111_ANAR_100BASE_TX_FD_SHIFT) - -/* - * 100BASE_TX (RW) - * - * 1: 100Base-TX is supported by local node - * 0: 100Base-TX not supported by local node - */ -#define JL1111_ANAR_100BASE_TX_MASK (0x80U) -#define JL1111_ANAR_100BASE_TX_SHIFT (7U) -#define JL1111_ANAR_100BASE_TX_SET(x) (((uint16_t)(x) << JL1111_ANAR_100BASE_TX_SHIFT) & JL1111_ANAR_100BASE_TX_MASK) -#define JL1111_ANAR_100BASE_TX_GET(x) (((uint16_t)(x) & JL1111_ANAR_100BASE_TX_MASK) >> JL1111_ANAR_100BASE_TX_SHIFT) - -/* - * 10BASE_T_FD (RW) - * - * 1: 10Base-T full duplex supported by local node - * 0: 10Base-T full duplex not supported by local node - */ -#define JL1111_ANAR_10BASE_T_FD_MASK (0x40U) -#define JL1111_ANAR_10BASE_T_FD_SHIFT (6U) -#define JL1111_ANAR_10BASE_T_FD_SET(x) (((uint16_t)(x) << JL1111_ANAR_10BASE_T_FD_SHIFT) & JL1111_ANAR_10BASE_T_FD_MASK) -#define JL1111_ANAR_10BASE_T_FD_GET(x) (((uint16_t)(x) & JL1111_ANAR_10BASE_T_FD_MASK) >> JL1111_ANAR_10BASE_T_FD_SHIFT) - -/* - * 10BASE_T (RW) - * - * 1: 10Base-T is supported by local node - * 0: 10Base-T not supported by local node - */ -#define JL1111_ANAR_10BASE_T_MASK (0x20U) -#define JL1111_ANAR_10BASE_T_SHIFT (5U) -#define JL1111_ANAR_10BASE_T_SET(x) (((uint16_t)(x) << JL1111_ANAR_10BASE_T_SHIFT) & JL1111_ANAR_10BASE_T_MASK) -#define JL1111_ANAR_10BASE_T_GET(x) (((uint16_t)(x) & JL1111_ANAR_10BASE_T_MASK) >> JL1111_ANAR_10BASE_T_SHIFT) - -/* - * SELECTOR_FIELD (RO) - * - * Binary Encoded Selector Supported by This Node. Currently only CSMA/CD 00001 is specified. No other protocols are supported. - */ -#define JL1111_ANAR_SELECTOR_FIELD_MASK (0x1FU) -#define JL1111_ANAR_SELECTOR_FIELD_SHIFT (0U) -#define JL1111_ANAR_SELECTOR_FIELD_GET(x) (((uint16_t)(x) & JL1111_ANAR_SELECTOR_FIELD_MASK) >> JL1111_ANAR_SELECTOR_FIELD_SHIFT) - -/* Bitfield definition for register: ANLPAR */ -/* - * NEXT_PAGE (RO) - * - * Next Page Bit. - * 0: Transmitting the primary capability data page - * 1: Transmitting the protocol specific data page - */ -#define JL1111_ANLPAR_NEXT_PAGE_MASK (0x8000U) -#define JL1111_ANLPAR_NEXT_PAGE_SHIFT (15U) -#define JL1111_ANLPAR_NEXT_PAGE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_NEXT_PAGE_MASK) >> JL1111_ANLPAR_NEXT_PAGE_SHIFT) - -/* - * ACKNOWLEDGE (RO) - * - * 1: Link partner acknowledges reception of local node's capability data word - * 0: No acknowledgement - */ -#define JL1111_ANLPAR_ACKNOWLEDGE_MASK (0x4000U) -#define JL1111_ANLPAR_ACKNOWLEDGE_SHIFT (14U) -#define JL1111_ANLPAR_ACKNOWLEDGE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_ACKNOWLEDGE_MASK) >> JL1111_ANLPAR_ACKNOWLEDGE_SHIFT) - -/* - * REMOTE_FAULT (RO) - * - * 1: Link partner is indicating a remote fault - * 0: Link partner is not indicating a remote fault - */ -#define JL1111_ANLPAR_REMOTE_FAULT_MASK (0x2000U) -#define JL1111_ANLPAR_REMOTE_FAULT_SHIFT (13U) -#define JL1111_ANLPAR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_REMOTE_FAULT_MASK) >> JL1111_ANLPAR_REMOTE_FAULT_SHIFT) - -/* - * ASYMMETRIC_PAUSE (RO) - * - * Asymmetric Pause Support For Full-Duplex Links - * 1: Advertise asymmetric pause ability - * 0: Do not advertise asymmetric puase ability - */ -#define JL1111_ANLPAR_ASYMMETRIC_PAUSE_MASK (0x800U) -#define JL1111_ANLPAR_ASYMMETRIC_PAUSE_SHIFT (11U) -#define JL1111_ANLPAR_ASYMMETRIC_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_ASYMMETRIC_PAUSE_MASK) >> JL1111_ANLPAR_ASYMMETRIC_PAUSE_SHIFT) - -/* - * PAUSE (RO) - * - * Pause Support For Full-Duplex Links - * 1: Advertise pause ability - * 0: Do not advertise pause ability - */ -#define JL1111_ANLPAR_PAUSE_MASK (0x400U) -#define JL1111_ANLPAR_PAUSE_SHIFT (10U) -#define JL1111_ANLPAR_PAUSE_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_PAUSE_MASK) >> JL1111_ANLPAR_PAUSE_SHIFT) - -/* - * 100BASE_T4 (RO) - * - * 1: 100Base-T4 is supported by link partner - * 0: 100Base-T4 not supported by link partner - */ -#define JL1111_ANLPAR_100BASE_T4_MASK (0x200U) -#define JL1111_ANLPAR_100BASE_T4_SHIFT (9U) -#define JL1111_ANLPAR_100BASE_T4_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_100BASE_T4_MASK) >> JL1111_ANLPAR_100BASE_T4_SHIFT) - -/* - * 100BASE_TX_FD (RO) - * - * 1: 100Base-TX full duplex is supported by link partner - * 0: 100Base-TX full duplex not supported by link partner - */ -#define JL1111_ANLPAR_100BASE_TX_FD_MASK (0x100U) -#define JL1111_ANLPAR_100BASE_TX_FD_SHIFT (8U) -#define JL1111_ANLPAR_100BASE_TX_FD_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_100BASE_TX_FD_MASK) >> JL1111_ANLPAR_100BASE_TX_FD_SHIFT) - -/* - * 100BASE_TX (RO) - * - * 1: 100Base-TX is supported by link partner - * 0: 100Base-TX not supported by link partner - */ -#define JL1111_ANLPAR_100BASE_TX_MASK (0x80U) -#define JL1111_ANLPAR_100BASE_TX_SHIFT (7U) -#define JL1111_ANLPAR_100BASE_TX_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_100BASE_TX_MASK) >> JL1111_ANLPAR_100BASE_TX_SHIFT) - -/* - * 10BASE_T_FD (RO) - * - * 1: 10Base-T full duplex is supported by link partner - * 0: 10Base-T full duplex not supported by link partner - */ -#define JL1111_ANLPAR_10BASE_T_FD_MASK (0x40U) -#define JL1111_ANLPAR_10BASE_T_FD_SHIFT (6U) -#define JL1111_ANLPAR_10BASE_T_FD_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_10BASE_T_FD_MASK) >> JL1111_ANLPAR_10BASE_T_FD_SHIFT) - -/* - * 10BASE_T (RO) - * - * 1: 10Base-T is supported by link partner - * 0: 10Base-T not supported by link partner - */ -#define JL1111_ANLPAR_10BASE_T_MASK (0x20U) -#define JL1111_ANLPAR_10BASE_T_SHIFT (5U) -#define JL1111_ANLPAR_10BASE_T_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_10BASE_T_MASK) >> JL1111_ANLPAR_10BASE_T_SHIFT) - -/* - * SELECTOR_FIELD (RO) - * - * Link Partner's Binary Encoded Node Selector. - * Currently only CSMA/CD 00001 is specified. - */ -#define JL1111_ANLPAR_SELECTOR_FIELD_MASK (0x1FU) -#define JL1111_ANLPAR_SELECTOR_FIELD_SHIFT (0U) -#define JL1111_ANLPAR_SELECTOR_FIELD_GET(x) (((uint16_t)(x) & JL1111_ANLPAR_SELECTOR_FIELD_MASK) >> JL1111_ANLPAR_SELECTOR_FIELD_SHIFT) - -/* Bitfield definition for register: MMDAC */ -/* - * MMD_FUNCTION (RW) - * - * 00: address - * 01: data, no post increment - * 10: data, post increment on reads and writes - * 11: data, post increment on writes only - */ -#define JL1111_MMDAC_MMD_FUNCTION_MASK (0xC000U) -#define JL1111_MMDAC_MMD_FUNCTION_SHIFT (14U) -#define JL1111_MMDAC_MMD_FUNCTION_SET(x) (((uint16_t)(x) << JL1111_MMDAC_MMD_FUNCTION_SHIFT) & JL1111_MMDAC_MMD_FUNCTION_MASK) -#define JL1111_MMDAC_MMD_FUNCTION_GET(x) (((uint16_t)(x) & JL1111_MMDAC_MMD_FUNCTION_MASK) >> JL1111_MMDAC_MMD_FUNCTION_SHIFT) - -/* - * RESERVERD (RW) - * - * Write as 0, ignore on read - */ -#define JL1111_MMDAC_RESERVERD_MASK (0x3FE0U) -#define JL1111_MMDAC_RESERVERD_SHIFT (5U) -#define JL1111_MMDAC_RESERVERD_SET(x) (((uint16_t)(x) << JL1111_MMDAC_RESERVERD_SHIFT) & JL1111_MMDAC_RESERVERD_MASK) -#define JL1111_MMDAC_RESERVERD_GET(x) (((uint16_t)(x) & JL1111_MMDAC_RESERVERD_MASK) >> JL1111_MMDAC_RESERVERD_SHIFT) - -/* - * MMD_DEVAD (RW) - * - * Device address - */ -#define JL1111_MMDAC_MMD_DEVAD_MASK (0x1FU) -#define JL1111_MMDAC_MMD_DEVAD_SHIFT (0U) -#define JL1111_MMDAC_MMD_DEVAD_SET(x) (((uint16_t)(x) << JL1111_MMDAC_MMD_DEVAD_SHIFT) & JL1111_MMDAC_MMD_DEVAD_MASK) -#define JL1111_MMDAC_MMD_DEVAD_GET(x) (((uint16_t)(x) & JL1111_MMDAC_MMD_DEVAD_MASK) >> JL1111_MMDAC_MMD_DEVAD_SHIFT) - -/* Bitfield definition for register: MMDAAD */ -/* - * MMD_ADDRESS_DATA (RW) - * - * If MMDAC[15:14]=00, MMD DEVAD's address register. Otherwise, MMD DEVAD's data register as indicated by the contents of its address register - */ -#define JL1111_MMDAAD_MMD_ADDRESS_DATA_MASK (0xFFFFU) -#define JL1111_MMDAAD_MMD_ADDRESS_DATA_SHIFT (0U) -#define JL1111_MMDAAD_MMD_ADDRESS_DATA_SET(x) (((uint16_t)(x) << JL1111_MMDAAD_MMD_ADDRESS_DATA_SHIFT) & JL1111_MMDAAD_MMD_ADDRESS_DATA_MASK) -#define JL1111_MMDAAD_MMD_ADDRESS_DATA_GET(x) (((uint16_t)(x) & JL1111_MMDAAD_MMD_ADDRESS_DATA_MASK) >> JL1111_MMDAAD_MMD_ADDRESS_DATA_SHIFT) - -/* Bitfield definition for register: RMSR_P7 */ -/* - * RMII_TX_LPI_ENABLE (RW) - * - * Enable transmition LPI signal of RMII - * TX_EN=0 and TXD=1 will represent MII LPI - */ -#define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_MASK (0x8000U) -#define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SHIFT (15U) -#define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SHIFT) & JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_MASK) -#define JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_MASK) >> JL1111_RMSR_P7_RMII_TX_LPI_ENABLE_SHIFT) - -/* - * RMII_RX_LPI_ENABLE (RW) - * - * Enable reception LPI signal of RMII - * CRS_DV=0 and RXD=1 will represent MII LPI - */ -#define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_MASK (0x4000U) -#define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SHIFT (14U) -#define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SHIFT) & JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_MASK) -#define JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_MASK) >> JL1111_RMSR_P7_RMII_RX_LPI_ENABLE_SHIFT) - -/* - * RMII_RX_ER_IN_RXD (RW) - * - * For Non-Bad-SSD rx_er, RXD will be 1 - */ -#define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_MASK (0x2000U) -#define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SHIFT (13U) -#define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SHIFT) & JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_MASK) -#define JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_MASK) >> JL1111_RMSR_P7_RMII_RX_ER_IN_RXD_SHIFT) - -/* - * RMII_CLOCK_DIRECTION (RW) - * - * Clock Direction of TX_CLK in RMII Mode. - * 0: 50MHz Output - * 1: 50MHz Input - */ -#define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_MASK (0x1000U) -#define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SHIFT (12U) -#define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SHIFT) & JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_MASK) -#define JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_MASK) >> JL1111_RMSR_P7_RMII_CLOCK_DIRECTION_SHIFT) - -/* - * RMII_TX_SKEW (RW) - * - * Adjust RMII TX Interface Timing - */ -#define JL1111_RMSR_P7_RMII_TX_SKEW_MASK (0xF00U) -#define JL1111_RMSR_P7_RMII_TX_SKEW_SHIFT (8U) -#define JL1111_RMSR_P7_RMII_TX_SKEW_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_TX_SKEW_SHIFT) & JL1111_RMSR_P7_RMII_TX_SKEW_MASK) -#define JL1111_RMSR_P7_RMII_TX_SKEW_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_TX_SKEW_MASK) >> JL1111_RMSR_P7_RMII_TX_SKEW_SHIFT) - -/* - * RMII_RX_SKEW (RW) - * - * Adjust RMII RX Interface Timing - */ -#define JL1111_RMSR_P7_RMII_RX_SKEW_MASK (0xF0U) -#define JL1111_RMSR_P7_RMII_RX_SKEW_SHIFT (4U) -#define JL1111_RMSR_P7_RMII_RX_SKEW_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RX_SKEW_SHIFT) & JL1111_RMSR_P7_RMII_RX_SKEW_MASK) -#define JL1111_RMSR_P7_RMII_RX_SKEW_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RX_SKEW_MASK) >> JL1111_RMSR_P7_RMII_RX_SKEW_SHIFT) - -/* - * MII_RMII_MODE_SELECTION (RW) - * - * 0: RMII Mode - * 1: RMII Mode - */ -#define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_MASK (0x8U) -#define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SHIFT (3U) -#define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SHIFT) & JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_MASK) -#define JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_MASK) >> JL1111_RMSR_P7_MII_RMII_MODE_SELECTION_SHIFT) - -/* - * RMII_CRS_DV_FUNCTIONAL (RW) - * - * 0: CRS_DV pin is CRS_DV signal - * 1: CRS_DV pin is RXDV signal - */ -#define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_MASK (0x4U) -#define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SHIFT (2U) -#define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SHIFT) & JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_MASK) -#define JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_MASK) >> JL1111_RMSR_P7_RMII_CRS_DV_FUNCTIONAL_SHIFT) - -/* - * RMII_RXD_BAD_SSD_ENABLE (RW) - * - * 0: RMII data only - * 1: RMII data with SSD Error - */ -#define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_MASK (0x2U) -#define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SHIFT (1U) -#define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SET(x) (((uint16_t)(x) << JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SHIFT) & JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_MASK) -#define JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_GET(x) (((uint16_t)(x) & JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_MASK) >> JL1111_RMSR_P7_RMII_RXD_BAD_SSD_ENABLE_SHIFT) - -/* Bitfield definition for register: INTSQI */ -/* - * AUTONEG_ERROR (RC) - * - * Auto-Negotiation Error Interrupt - */ -#define JL1111_INTSQI_AUTONEG_ERROR_MASK (0x8000U) -#define JL1111_INTSQI_AUTONEG_ERROR_SHIFT (15U) -#define JL1111_INTSQI_AUTONEG_ERROR_GET(x) (((uint16_t)(x) & JL1111_INTSQI_AUTONEG_ERROR_MASK) >> JL1111_INTSQI_AUTONEG_ERROR_SHIFT) - -/* - * LINK_STATUS_CHANGE (RC) - * - * Link_Status_Change_Interrupt - * 1: Enable - * 0: Disable - */ -#define JL1111_INTSQI_LINK_STATUS_CHANGE_MASK (0x800U) -#define JL1111_INTSQI_LINK_STATUS_CHANGE_SHIFT (11U) -#define JL1111_INTSQI_LINK_STATUS_CHANGE_GET(x) (((uint16_t)(x) & JL1111_INTSQI_LINK_STATUS_CHANGE_MASK) >> JL1111_INTSQI_LINK_STATUS_CHANGE_SHIFT) - -/* - * SIGNAL_QUALITY_INDICATOR (RO) - * - * Signal Quality Indicator, lower is better. The value is only valid in 100Base-TX mode and its link status is ON - */ -#define JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_MASK (0x1FU) -#define JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_SHIFT (0U) -#define JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_GET(x) (((uint16_t)(x) & JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_MASK) >> JL1111_INTSQI_SIGNAL_QUALITY_INDICATOR_SHIFT) - -/* Bitfield definition for register: PAGESEL */ -/* - * PAGE_SELECTION (RW) - * - */ -#define JL1111_PAGESEL_PAGE_SELECTION_MASK (0xFFU) -#define JL1111_PAGESEL_PAGE_SELECTION_SHIFT (0U) -#define JL1111_PAGESEL_PAGE_SELECTION_SET(x) (((uint16_t)(x) << JL1111_PAGESEL_PAGE_SELECTION_SHIFT) & JL1111_PAGESEL_PAGE_SELECTION_MASK) -#define JL1111_PAGESEL_PAGE_SELECTION_GET(x) (((uint16_t)(x) & JL1111_PAGESEL_PAGE_SELECTION_MASK) >> JL1111_PAGESEL_PAGE_SELECTION_SHIFT) - - - - -#endif /* HPM_JL1111_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.c deleted file mode 100644 index e487972eb12..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_lan8720_regs.h" -#include "hpm_lan8720.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -static bool lan8720_check_id(ENET_Type *ptr) -{ - uint16_t id1, id2; - - id1 = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_PHYID1); - id2 = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_PHYID2); - - if (LAN8720_PHYID1_OUI_MSB_GET(id1) == LAN8720_ID1 && LAN8720_PHYID2_OUI_LSB_GET(id2) == LAN8720_ID2) { - return true; - } else { - return false; - } -} - -/*--------------------------------------------------------------------- - * API - *--------------------------------------------------------------------- - */ -void lan8720_reset(ENET_Type *ptr) -{ - uint16_t data; - - /* PHY reset */ - enet_write_phy(ptr, LAN8720_ADDR, LAN8720_BMCR, LAN8720_BMCR_RESET_SET(1)); - - /* wait until the reset is completed */ - do { - data = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_BMCR); - } while (LAN8720_BMCR_RESET_GET(data)); -} - -void lan8720_basic_mode_default_config(ENET_Type *ptr, lan8720_config_t *config) -{ - config->loopback = false; /* Disable PCS loopback mode */ - #if defined(__DISABLE_AUTO_NEGO) && __DISABLE_AUTO_NEGO - config->auto_negotiation = false; /* Disable Auto-Negotiation */ - config->speed = enet_phy_port_speed_100mbps; - config->duplex = enet_phy_duplex_full; - #else - config->auto_negotiation = true; /* Enable Auto-Negotiation */ - #endif -} - -bool lan8720_basic_mode_init(ENET_Type *ptr, lan8720_config_t *config) -{ - uint16_t data = 0; - - data |= LAN8720_BMCR_RESET_SET(0) /* Normal operation */ - | LAN8720_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ - | LAN8720_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ - | LAN8720_BMCR_PWD_SET(0) /* Normal operation */ - | LAN8720_BMCR_ISOLATE_SET(0) /* Normal operation */ - | LAN8720_BMCR_RESTART_AN_SET(0); /* Normal operation (ignored when Auto-Negotiation is disabled) */ - - if (config->auto_negotiation == 0) { - data |= LAN8720_BMCR_SPEED_SET(config->speed); /* Set port speed */ - data |= LAN8720_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ - } - - /* check the id of lan8720 */ - if (lan8720_check_id(ptr) == false) { - return false; - } - - enet_write_phy(ptr, LAN8720_ADDR, LAN8720_BMCR, data); - - return true; -} - -void lan8720_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) -{ - uint16_t data; - - data = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_BMSR); - status->enet_phy_link = LAN8720_BMSR_LINK_STATUS_GET(data); - - data = enet_read_phy(ptr, LAN8720_ADDR, LAN8720_PSCSR); - status->enet_phy_speed = LAN8720_PSCSR_SPEED_GET(data) == 1 ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; - status->enet_phy_duplex = LAN8720_PSCSR_DUPLEX_GET(data); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.h deleted file mode 100644 index 2f31ca906e1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_LAN8720_H -#define HPM_LAN8720_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_phy.h" -#include "hpm_common.h" -#include "hpm_enet_regs.h" -/*--------------------------------------------------------------------- - * Macro Const Definitions - *--------------------------------------------------------------------- - */ -#ifndef LAN8720_ADDR -#define LAN8720_ADDR (0U) -#endif - -#define LAN8720_ID1 (0x0007U) -#define LAN8720_ID2 (0x30U) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -typedef struct { - bool loopback; - uint8_t speed; - bool auto_negotiation; - uint8_t duplex; -} lan8720_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -void lan8720_reset(ENET_Type *ptr); -void lan8720_basic_mode_default_config(ENET_Type *ptr, lan8720_config_t *config); -bool lan8720_basic_mode_init(ENET_Type *ptr, lan8720_config_t *config); -void lan8720_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_LAN8720_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720_regs.h deleted file mode 100644 index 522057ccea0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/lan8720/hpm_lan8720_regs.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LAN8720_REGS_H -#define HPM_LAN8720_REGS_H - -typedef enum { - LAN8720_BMCR = 0, /* 0x0: Basic Mode Control Register */ - LAN8720_BMSR = 1, /* 0x1: Basic Mode Status Register */ - LAN8720_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ - LAN8720_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ - LAN8720_SMR = 18, /* 0x12: Special Modes Register */ - LAN8720_SECR = 26, /* 0x1A: Symbol Error Counter Register */ - LAN8720_ISFR = 29, /* 0x1D: Interrupt Source Flag Register */ - LAN8720_IMR = 30, /* 0x1E: Interrupt Mask Register */ - LAN8720_PSCSR = 31, /* 0x1F: PHY Special Control/Status Register */ -} LAN8720_REG_Type; - - -/* Bitfield definition for register: BMCR */ -/* - * RESET (RW/SC) - * - * 1 = software reset. Bit is self-clearing. When setting this bit do not set other - * bits in this register. The configuration is set from the register bit values, and not - * from the mode pins. - */ -#define LAN8720_BMCR_RESET_MASK (0x8000U) -#define LAN8720_BMCR_RESET_SHIFT (15U) -#define LAN8720_BMCR_RESET_SET(x) (((uint16_t)(x) << LAN8720_BMCR_RESET_SHIFT) & LAN8720_BMCR_RESET_MASK) -#define LAN8720_BMCR_RESET_GET(x) (((uint16_t)(x) & LAN8720_BMCR_RESET_MASK) >> LAN8720_BMCR_RESET_SHIFT) - -/* - * LOOPBACK (RW) - * - * 0 = normal operation - * 1 = loopback mode - */ -#define LAN8720_BMCR_LOOPBACK_MASK (0x4000U) -#define LAN8720_BMCR_LOOPBACK_SHIFT (14U) -#define LAN8720_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << LAN8720_BMCR_LOOPBACK_SHIFT) & LAN8720_BMCR_LOOPBACK_MASK) -#define LAN8720_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & LAN8720_BMCR_LOOPBACK_MASK) >> LAN8720_BMCR_LOOPBACK_SHIFT) - -/* - * SPEED (RW) - * - * 0 = 10Mbps - * 1 = 100Mbps - * Ignored if Auto-negotiation is enabled (0.12 = 1). - */ -#define LAN8720_BMCR_SPEED_MASK (0x2000U) -#define LAN8720_BMCR_SPEED_SHIFT (13U) -#define LAN8720_BMCR_SPEED_SET(x) (((uint16_t)(x) << LAN8720_BMCR_SPEED_SHIFT) & LAN8720_BMCR_SPEED_MASK) -#define LAN8720_BMCR_SPEED_GET(x) (((uint16_t)(x) & LAN8720_BMCR_SPEED_MASK) >> LAN8720_BMCR_SPEED_SHIFT) - -/* - * ANE (RW) - * - * Auto-Negotiation Enable - * 0 = disable auto-negotiate process - * 1 = enable auto-negotiate process (overrides 0.13 and 0.8) - */ -#define LAN8720_BMCR_ANE_MASK (0x1000U) -#define LAN8720_BMCR_ANE_SHIFT (12U) -#define LAN8720_BMCR_ANE_SET(x) (((uint16_t)(x) << LAN8720_BMCR_ANE_SHIFT) & LAN8720_BMCR_ANE_MASK) -#define LAN8720_BMCR_ANE_GET(x) (((uint16_t)(x) & LAN8720_BMCR_ANE_MASK) >> LAN8720_BMCR_ANE_SHIFT) - -/* - * PWD (RW) - * - * 0 = normal operation - * 1 = General power down mode - * The Auto-Negotiation Enable must be cleared before setting the Power - * Down. - */ -#define LAN8720_BMCR_PWD_MASK (0x800U) -#define LAN8720_BMCR_PWD_SHIFT (11U) -#define LAN8720_BMCR_PWD_SET(x) (((uint16_t)(x) << LAN8720_BMCR_PWD_SHIFT) & LAN8720_BMCR_PWD_MASK) -#define LAN8720_BMCR_PWD_GET(x) (((uint16_t)(x) & LAN8720_BMCR_PWD_MASK) >> LAN8720_BMCR_PWD_SHIFT) - -/* - * ISOLATE (RW) - * - * 0 = normal operation - * 1 = electrical isolation of PHY from the RMII - */ -#define LAN8720_BMCR_ISOLATE_MASK (0x400U) -#define LAN8720_BMCR_ISOLATE_SHIFT (10U) -#define LAN8720_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << LAN8720_BMCR_ISOLATE_SHIFT) & LAN8720_BMCR_ISOLATE_MASK) -#define LAN8720_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & LAN8720_BMCR_ISOLATE_MASK) >> LAN8720_BMCR_ISOLATE_SHIFT) - -/* - * RESTART_AN (RW/SC) - * - * 0 = normal operation - * 1 = restart auto-negotiate process - * Bit is self-clearing. - */ -#define LAN8720_BMCR_RESTART_AN_MASK (0x200U) -#define LAN8720_BMCR_RESTART_AN_SHIFT (9U) -#define LAN8720_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << LAN8720_BMCR_RESTART_AN_SHIFT) & LAN8720_BMCR_RESTART_AN_MASK) -#define LAN8720_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & LAN8720_BMCR_RESTART_AN_MASK) >> LAN8720_BMCR_RESTART_AN_SHIFT) - -/* - * DUPLEX (RW) - * - * 0 = half duplex - * 1 = full duplex - * Ignored if Auto-Negotiation is enabled (0.12 = 1). - */ -#define LAN8720_BMCR_DUPLEX_MASK (0x100U) -#define LAN8720_BMCR_DUPLEX_SHIFT (8U) -#define LAN8720_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << LAN8720_BMCR_DUPLEX_SHIFT) & LAN8720_BMCR_DUPLEX_MASK) -#define LAN8720_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & LAN8720_BMCR_DUPLEX_MASK) >> LAN8720_BMCR_DUPLEX_SHIFT) - -/* Bitfield definition for register: BMSR */ -/* - * 100BASE_T4 (RO) - * - * 0 = no T4 ability - * 1 = T4 able - */ -#define LAN8720_BMSR_100BASE_T4_MASK (0x8000U) -#define LAN8720_BMSR_100BASE_T4_SHIFT (15U) -#define LAN8720_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T4_MASK) >> LAN8720_BMSR_100BASE_T4_SHIFT) - -/* - * 100BASE_TX_FULL (RO) - * - * 0 = no TX full duplex ability - * 1 = TX with full duplex - */ -#define LAN8720_BMSR_100BASE_TX_FULL_MASK (0x4000U) -#define LAN8720_BMSR_100BASE_TX_FULL_SHIFT (14U) -#define LAN8720_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_TX_FULL_MASK) >> LAN8720_BMSR_100BASE_TX_FULL_SHIFT) - -/* - * 100BASE_TX_HALF (RO) - * - * 0 = no TX half duplex ability - * 1 = TX with half duplex - */ -#define LAN8720_BMSR_100BASE_TX_HALF_MASK (0x2000U) -#define LAN8720_BMSR_100BASE_TX_HALF_SHIFT (13U) -#define LAN8720_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_TX_HALF_MASK) >> LAN8720_BMSR_100BASE_TX_HALF_SHIFT) - -/* - * 10BASE_T_FULL (RO) - * - * 0 = no 10Mbps with full duplex ability - * 1 = 10Mbps with full duplex - */ -#define LAN8720_BMSR_10BASE_T_FULL_MASK (0x1000U) -#define LAN8720_BMSR_10BASE_T_FULL_SHIFT (12U) -#define LAN8720_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_10BASE_T_FULL_MASK) >> LAN8720_BMSR_10BASE_T_FULL_SHIFT) - -/* - * 10BASE_T_HALF (RO) - * - * 0 = no 10Mbps with half duplex ability - * 1 = 10Mbps with half duplex - */ -#define LAN8720_BMSR_10BASE_T_HALF_MASK (0x800U) -#define LAN8720_BMSR_10BASE_T_HALF_SHIFT (11U) -#define LAN8720_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_10BASE_T_HALF_MASK) >> LAN8720_BMSR_10BASE_T_HALF_SHIFT) - -/* - * 100BASE_T2_FULL (RO) - * - * 0 = PHY not able to perform full duplex 100BASE-T2 - * 1 = PHY able to perform full duplex 100BASE-T2 - */ -#define LAN8720_BMSR_100BASE_T2_FULL_MASK (0x400U) -#define LAN8720_BMSR_100BASE_T2_FULL_SHIFT (10U) -#define LAN8720_BMSR_100BASE_T2_FULL_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T2_FULL_MASK) >> LAN8720_BMSR_100BASE_T2_FULL_SHIFT) - -/* - * 100BASE_T2_HALF (RO) - * - * 0 = PHY not able to perform half duplex 100BASE-T2 - * 1 = PHY able to perform half duplex 100BASE-T2 - */ -#define LAN8720_BMSR_100BASE_T2_HALF_MASK (0x200U) -#define LAN8720_BMSR_100BASE_T2_HALF_SHIFT (9U) -#define LAN8720_BMSR_100BASE_T2_HALF_GET(x) (((uint16_t)(x) & LAN8720_BMSR_100BASE_T2_HALF_MASK) >> LAN8720_BMSR_100BASE_T2_HALF_SHIFT) - -/* - * EXTENDED_STATUS (RO) - * - * 0 = no extended status information in register 15 - * 1 = extended status information in register 15 - */ -#define LAN8720_BMSR_EXTENDED_STATUS_MASK (0x100U) -#define LAN8720_BMSR_EXTENDED_STATUS_SHIFT (8U) -#define LAN8720_BMSR_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & LAN8720_BMSR_EXTENDED_STATUS_MASK) >> LAN8720_BMSR_EXTENDED_STATUS_SHIFT) - -/* - * AUTO_NEGOTIATION_COMPLETE (RO) - * - * 0 = auto-negotiate process not completed - * 1 = auto-negotiate process completed - */ -#define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) -#define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) -#define LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> LAN8720_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) - -/* - * REMOTE_FAULT (RC) - * - * 1 = remote fault condition detected - * 0 = no remote fault - */ -#define LAN8720_BMSR_REMOTE_FAULT_MASK (0x10U) -#define LAN8720_BMSR_REMOTE_FAULT_SHIFT (4U) -#define LAN8720_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & LAN8720_BMSR_REMOTE_FAULT_MASK) >> LAN8720_BMSR_REMOTE_FAULT_SHIFT) - -/* - * AUTO_NEGOTIATION_ABILITY (RO) - * - * 0 = unable to perform auto-negotiation function - * 1 = able to perform auto-negotiation function - */ -#define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) -#define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) -#define LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> LAN8720_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) - -/* - * LINK_STATUS (RO) - * - * 0 = link is down - * 1 = link is up - */ -#define LAN8720_BMSR_LINK_STATUS_MASK (0x4U) -#define LAN8720_BMSR_LINK_STATUS_SHIFT (2U) -#define LAN8720_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & LAN8720_BMSR_LINK_STATUS_MASK) >> LAN8720_BMSR_LINK_STATUS_SHIFT) - -/* - * JABBER_DETECT (RO) - * - * 0 = no jabber condition detected - * 1 = jabber condition detected - */ -#define LAN8720_BMSR_JABBER_DETECT_MASK (0x2U) -#define LAN8720_BMSR_JABBER_DETECT_SHIFT (1U) -#define LAN8720_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & LAN8720_BMSR_JABBER_DETECT_MASK) >> LAN8720_BMSR_JABBER_DETECT_SHIFT) - -/* - * EXTENDED_CAPABILITY (RO) - * - * 0 = does not support extended capabilities registers - * 1 = supports extended capabilities registers - */ -#define LAN8720_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) -#define LAN8720_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) -#define LAN8720_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & LAN8720_BMSR_EXTENDED_CAPABILITY_MASK) >> LAN8720_BMSR_EXTENDED_CAPABILITY_SHIFT) - -/* Bitfield definition for register: PHYID1 */ -/* - * OUI_MSB (RO) - * - * Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier - * (OUI), respectively. - */ -#define LAN8720_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define LAN8720_PHYID1_OUI_MSB_SHIFT (0U) -#define LAN8720_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & LAN8720_PHYID1_OUI_MSB_MASK) >> LAN8720_PHYID1_OUI_MSB_SHIFT) - -/* Bitfield definition for register: PHYID2 */ -/* - * OUI_LSB (RO) - * - * Assigned to the 19th through 24th bits of the OUI. - */ -#define LAN8720_PHYID2_OUI_LSB_MASK (0xFC00U) -#define LAN8720_PHYID2_OUI_LSB_SHIFT (10U) -#define LAN8720_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_OUI_LSB_MASK) >> LAN8720_PHYID2_OUI_LSB_SHIFT) - -/* - * MODEL_NUMBER (RO) - * - * Six-bit manufacturer’s model number. - */ -#define LAN8720_PHYID2_MODEL_NUMBER_MASK (0x3F0U) -#define LAN8720_PHYID2_MODEL_NUMBER_SHIFT (4U) -#define LAN8720_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_MODEL_NUMBER_MASK) >> LAN8720_PHYID2_MODEL_NUMBER_SHIFT) - -/* - * REVISION_NUMBER (RO) - * - * Four-bit manufacturer’s revision number. - */ -#define LAN8720_PHYID2_REVISION_NUMBER_MASK (0xFU) -#define LAN8720_PHYID2_REVISION_NUMBER_SHIFT (0U) -#define LAN8720_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & LAN8720_PHYID2_REVISION_NUMBER_MASK) >> LAN8720_PHYID2_REVISION_NUMBER_SHIFT) - -/* Bitfield definition for register: SMR */ -/* - * MODE (R/W) - * - * Transceiver mode of operation - */ -#define LAN8720_SMR_MODE_MASK (0xE0U) -#define LAN8720_SMR_MODE_SHIFT (5U) -#define LAN8720_SMR_MODE_SET(x) (((uint16_t)(x) << LAN8720_SMR_MODE_SHIFT) & LAN8720_SMR_MODE_MASK) -#define LAN8720_SMR_MODE_GET(x) (((uint16_t)(x) & LAN8720_SMR_MODE_MASK) >> LAN8720_SMR_MODE_SHIFT) - -/* - * PHYAD (R/W) - * - * PHY Address. The PHY Address is used for the SMI address and for initial- - * ization of the Cipher (Scrambler) key. - */ -#define LAN8720_SMR_PHYAD_MASK (0x1FU) -#define LAN8720_SMR_PHYAD_SHIFT (0U) -#define LAN8720_SMR_PHYAD_SET(x) (((uint16_t)(x) << LAN8720_SMR_PHYAD_SHIFT) & LAN8720_SMR_PHYAD_MASK) -#define LAN8720_SMR_PHYAD_GET(x) (((uint16_t)(x) & LAN8720_SMR_PHYAD_MASK) >> LAN8720_SMR_PHYAD_SHIFT) - -/* Bitfield definition for register: SECR */ -/* - * SYM_ERR_CNT (RO) - * - * The symbol error counter increments whenever an invalid code symbol is - * received (including IDLE symbols) in 100BASE-TX mode. The counter is - * incremented only once per packet, even when the received packet contains - * more than one symbol error. This counter increments up to 65,536 (2^16) and - * rolls over to 0 after reaching the maximum value. - * Note: This register is cleared on reset, but is not cleared by reading the - * register. This register does not increment in 10BASE-T mode. - */ -#define LAN8720_SECR_SYM_ERR_CNT_MASK (0xFFFFU) -#define LAN8720_SECR_SYM_ERR_CNT_SHIFT (0U) -#define LAN8720_SECR_SYM_ERR_CNT_GET(x) (((uint16_t)(x) & LAN8720_SECR_SYM_ERR_CNT_MASK) >> LAN8720_SECR_SYM_ERR_CNT_SHIFT) - -/* Bitfield definition for register: ISFR */ -/* - * INT7 (RO) - * - * 0 = not source of interrupt - * 1 = ENERGYON generated - */ -#define LAN8720_ISFR_INT7_MASK (0x80U) -#define LAN8720_ISFR_INT7_SHIFT (7U) -#define LAN8720_ISFR_INT7_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT7_MASK) >> LAN8720_ISFR_INT7_SHIFT) - -/* - * INT6 (RO) - * - * 0 = not source of interrupt - * 1 = Auto-Negotiation complete - */ -#define LAN8720_ISFR_INT6_MASK (0x40U) -#define LAN8720_ISFR_INT6_SHIFT (6U) -#define LAN8720_ISFR_INT6_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT6_MASK) >> LAN8720_ISFR_INT6_SHIFT) - -/* - * INT5 (RO) - * - * 0 = not source of interrupt - * 1 = Remote Fault Detected - */ -#define LAN8720_ISFR_INT5_MASK (0x20U) -#define LAN8720_ISFR_INT5_SHIFT (5U) -#define LAN8720_ISFR_INT5_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT5_MASK) >> LAN8720_ISFR_INT5_SHIFT) - -/* - * INT4 (RO) - * - * 0 = not source of interrupt - * 1 = Link Down (link status negated) - */ -#define LAN8720_ISFR_INT4_MASK (0x10U) -#define LAN8720_ISFR_INT4_SHIFT (4U) -#define LAN8720_ISFR_INT4_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT4_MASK) >> LAN8720_ISFR_INT4_SHIFT) - -/* - * INT3 (RO) - * - * 0 = not source of interrupt - * 1 = Auto-Negotiation LP Acknowledge - */ -#define LAN8720_ISFR_INT3_MASK (0x8U) -#define LAN8720_ISFR_INT3_SHIFT (3U) -#define LAN8720_ISFR_INT3_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT3_MASK) >> LAN8720_ISFR_INT3_SHIFT) - -/* - * INT2 (RO) - * - * 0 = not source of interrupt - * 1 = Parallel Detection Fault - */ -#define LAN8720_ISFR_INT2_MASK (0x4U) -#define LAN8720_ISFR_INT2_SHIFT (2U) -#define LAN8720_ISFR_INT2_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT2_MASK) >> LAN8720_ISFR_INT2_SHIFT) - -/* - * INT1 (RO) - * - * 0 = not source of interrupt - * 1 = Auto-Negotiation Page Received - */ -#define LAN8720_ISFR_INT1_MASK (0x2U) -#define LAN8720_ISFR_INT1_SHIFT (1U) -#define LAN8720_ISFR_INT1_GET(x) (((uint16_t)(x) & LAN8720_ISFR_INT1_MASK) >> LAN8720_ISFR_INT1_SHIFT) - -/* Bitfield definition for register: IMR */ -/* - * MASK (R/W) - * - * 0 = interrupt source is masked - * 1 = interrupt source is enabled - */ -#define LAN8720_IMR_MASK_MASK (0xFEU) -#define LAN8720_IMR_MASK_SHIFT (1U) -#define LAN8720_IMR_MASK_SET(x) (((uint16_t)(x) << LAN8720_IMR_MASK_SHIFT) & LAN8720_IMR_MASK_MASK) -#define LAN8720_IMR_MASK_GET(x) (((uint16_t)(x) & LAN8720_IMR_MASK_MASK) >> LAN8720_IMR_MASK_SHIFT) - -/* Bitfield definition for register: PSCSR */ -/* - * AUTODONE (RO) - * - * 0 = Auto-negotiation is not done or disabled (or not active) - * 1 = Auto-negotiation is done - */ -#define LAN8720_PSCSR_AUTODONE_MASK (0x1000U) -#define LAN8720_PSCSR_AUTODONE_SHIFT (12U) -#define LAN8720_PSCSR_AUTODONE_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_AUTODONE_MASK) >> LAN8720_PSCSR_AUTODONE_SHIFT) - -/* - * DUPLEX (RO) - * - * 0: Half duplex - * 1: Full duplex - */ -#define LAN8720_PSCSR_DUPLEX_MASK (0x10U) -#define LAN8720_PSCSR_DUPLEX_SHIFT (4U) -#define LAN8720_PSCSR_DUPLEX_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_DUPLEX_MASK) >> LAN8720_PSCSR_DUPLEX_SHIFT) - -/* - * SPEED (RO) - * - * HCDSPEED value: - * 01 = 10BASE-T - * 10 = 100BASE-TX - */ -#define LAN8720_PSCSR_SPEED_MASK (0xCU) -#define LAN8720_PSCSR_SPEED_SHIFT (2U) -#define LAN8720_PSCSR_SPEED_GET(x) (((uint16_t)(x) & LAN8720_PSCSR_SPEED_MASK) >> LAN8720_PSCSR_SPEED_SHIFT) - - - - -#endif /* HPM_LAN8720_REGS_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c deleted file mode 100644 index 63d70432cc5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_rtl8201_regs.h" -#include "hpm_rtl8201.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -static bool rtl8201_check_id(ENET_Type *ptr) -{ - uint16_t id1, id2; - - id1 = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_PHYID1); - id2 = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_PHYID2); - - if (RTL8201_PHYID1_OUI_MSB_GET(id1) == RTL8201_ID1 && RTL8201_PHYID2_OUI_LSB_GET(id2) == RTL8201_ID2) { - return true; - } else { - return false; - } -} - -/*--------------------------------------------------------------------- - * API - *--------------------------------------------------------------------- - */ -void rtl8201_reset(ENET_Type *ptr) -{ - uint16_t data; - - /* PHY reset */ - enet_write_phy(ptr, RTL8201_ADDR, RTL8201_BMCR, RTL8201_BMCR_RESET_SET(1)); - - /* wait until the reset is completed */ - do { - data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_BMCR); - } while (RTL8201_BMCR_RESET_GET(data)); -} - -void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config) -{ - (void)ptr; - - config->loopback = false; /* Disable PCS loopback mode */ - #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) - config->auto_negotiation = false; /* Disable Auto-Negotiation */ - config->speed = enet_phy_port_speed_100mbps; - config->duplex = enet_phy_duplex_full; - #else - config->auto_negotiation = true; /* Enable Auto-Negotiation */ - #endif - config->txc_input = true; /* Set TXC as input mode */ -} - -bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config) -{ - uint16_t data = 0; - - data |= RTL8201_BMCR_RESET_SET(0) /* Normal operation */ - | RTL8201_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ - | RTL8201_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ - | RTL8201_BMCR_PWD_SET(0) /* Normal operation */ - | RTL8201_BMCR_ISOLATE_SET(0) /* Normal operation */ - | RTL8201_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | RTL8201_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - - if (config->auto_negotiation == 0) { - data |= RTL8201_BMCR_SPEED0_SET(config->speed); /* Set port speed */ - data |= RTL8201_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ - } - - /* check the id of rtl8201 */ - if (rtl8201_check_id(ptr) == false) { - return false; - } - - enet_write_phy(ptr, RTL8201_ADDR, RTL8201_BMCR, data); - - /* select page 7 */ - enet_write_phy(ptr, RTL8201_ADDR, RTL8201_PAGESEL, 7); - - /* set txc direction */ - data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_RMSR_P7); - data &= ~RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK; - data |= RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(config->txc_input); - enet_write_phy(ptr, RTL8201_ADDR, RTL8201_RMSR_P7, data); - - return true; -} - -void rtl8201_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) -{ - uint16_t data; - - data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_BMSR); - status->enet_phy_link = RTL8201_BMSR_LINK_STATUS_GET(data); - - data = enet_read_phy(ptr, RTL8201_ADDR, RTL8201_BMCR); - status->enet_phy_speed = RTL8201_BMCR_SPEED0_GET(data) == 0 ? enet_phy_port_speed_10mbps : enet_phy_port_speed_100mbps; - status->enet_phy_duplex = RTL8201_BMCR_DUPLEX_GET(data); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h deleted file mode 100644 index c48957efefd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_RTL8201_H -#define HPM_RTL8201_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_phy.h" -#include "hpm_common.h" -#include "hpm_enet_regs.h" -/*--------------------------------------------------------------------- - * Macro Const Definitions - *--------------------------------------------------------------------- - */ -#ifndef RTL8201_ADDR -#define RTL8201_ADDR (2U) -#endif - -#define RTL8201_ID1 (0x001CU) -#define RTL8201_ID2 (0x32U) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -typedef struct { - bool loopback; - uint8_t speed; - bool auto_negotiation; - uint8_t duplex; - bool txc_input; -} rtl8201_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -void rtl8201_reset(ENET_Type *ptr); -void rtl8201_basic_mode_default_config(ENET_Type *ptr, rtl8201_config_t *config); -bool rtl8201_basic_mode_init(ENET_Type *ptr, rtl8201_config_t *config); -void rtl8201_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_RTL8201_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h deleted file mode 100644 index 17e237806a7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8201/hpm_rtl8201_regs.h +++ /dev/null @@ -1,407 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTL8201_REGS_H -#define HPM_RTL8201_REGS_H - -typedef enum { - RTL8201_BMCR = 0, /* 0x0: Basic Mode Control Register */ - RTL8201_BMSR = 1, /* 0x1: Basic Mode Status Register */ - RTL8201_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ - RTL8201_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ - RTL8201_RMSR_P7 = 16, /* 0x10: RMII Mode Setting Register */ - RTL8201_PAGESEL = 31, /* 0x1F: Page Select Register */ -} RTL8201_REG_Type; - - -/* Bitfield definition for register: BMCR */ -/* - * RESET (RW/SC) - * - * This bit sets the status and control registers of the PHY in the - * default state. This bit is self-clearing. - * 1: Software reset 0: Normal operation - * Register 0 and register 1 will return to default values after a - * software reset (set Bit15 to 1). - * This action may change the internal PHY state and the state of the - * physical link associated with the PHY. - */ -#define RTL8201_BMCR_RESET_MASK (0x8000U) -#define RTL8201_BMCR_RESET_SHIFT (15U) -#define RTL8201_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESET_SHIFT) & RTL8201_BMCR_RESET_MASK) -#define RTL8201_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESET_MASK) >> RTL8201_BMCR_RESET_SHIFT) - -/* - * LOOPBACK (RW) - * - * This bit enables loopback of transmit data nibbles TXD3:0 to the - * receive data path. - * 1: Enable loopback 0: Normal operation - */ -#define RTL8201_BMCR_LOOPBACK_MASK (0x4000U) -#define RTL8201_BMCR_LOOPBACK_SHIFT (14U) -#define RTL8201_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8201_BMCR_LOOPBACK_SHIFT) & RTL8201_BMCR_LOOPBACK_MASK) -#define RTL8201_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8201_BMCR_LOOPBACK_MASK) >> RTL8201_BMCR_LOOPBACK_SHIFT) - -/* - * SPEED0 (RW) - * - * This bit sets the network speed. - * 1: 100Mbps 0: 10Mbps - * After completing auto negotiation, this bit will reflect the speed - * status. - * 1: 100Base-T 0: 10Base-T - * When 100Base-FX mode is enabled, this bit=1 and is read only. - */ -#define RTL8201_BMCR_SPEED0_MASK (0x2000U) -#define RTL8201_BMCR_SPEED0_SHIFT (13U) -#define RTL8201_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED0_SHIFT) & RTL8201_BMCR_SPEED0_MASK) -#define RTL8201_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED0_MASK) >> RTL8201_BMCR_SPEED0_SHIFT) - -/* - * ANE (RW) - * - * This bit enables/disables the NWay auto-negotiation function. - * 1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored - * 0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the - * link speed and the data transfer mode, respectively - * When 100Base-FX mode is enabled, this bit=0 and is read only. - */ -#define RTL8201_BMCR_ANE_MASK (0x1000U) -#define RTL8201_BMCR_ANE_SHIFT (12U) -#define RTL8201_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ANE_SHIFT) & RTL8201_BMCR_ANE_MASK) -#define RTL8201_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ANE_MASK) >> RTL8201_BMCR_ANE_SHIFT) - -/* - * PWD (RW) - * - * This bit turns down the power of the PHY chip, including the - * internal crystal oscillator circuit. - * The MDC, MDIO is still alive for accessing the MAC. - * 1: Power down 0: Normal operation - */ -#define RTL8201_BMCR_PWD_MASK (0x800U) -#define RTL8201_BMCR_PWD_SHIFT (11U) -#define RTL8201_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8201_BMCR_PWD_SHIFT) & RTL8201_BMCR_PWD_MASK) -#define RTL8201_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8201_BMCR_PWD_MASK) >> RTL8201_BMCR_PWD_SHIFT) - -/* - * ISOLATE (RW) - * - * 1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII. - * PHY is still able to respond to MDC/MDIO. - * 0: Normal operation - */ -#define RTL8201_BMCR_ISOLATE_MASK (0x400U) -#define RTL8201_BMCR_ISOLATE_SHIFT (10U) -#define RTL8201_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8201_BMCR_ISOLATE_SHIFT) & RTL8201_BMCR_ISOLATE_MASK) -#define RTL8201_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8201_BMCR_ISOLATE_MASK) >> RTL8201_BMCR_ISOLATE_SHIFT) - -/* - * RESTART_AN (RW/SC) - * - * This bit allows the NWay auto-negotiation function to be reset. - * 1: Re-start auto-negotiation 0: Normal operation - */ -#define RTL8201_BMCR_RESTART_AN_MASK (0x200U) -#define RTL8201_BMCR_RESTART_AN_SHIFT (9U) -#define RTL8201_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8201_BMCR_RESTART_AN_SHIFT) & RTL8201_BMCR_RESTART_AN_MASK) -#define RTL8201_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8201_BMCR_RESTART_AN_MASK) >> RTL8201_BMCR_RESTART_AN_SHIFT) - -/* - * DUPLEX (RW) - * - * This bit sets the duplex mode if auto-negotiation is disabled (bit - * 0:12=0). - * 1: Full duplex 0: Half duplex - * After completing auto-negotiation, this bit will reflect the duplex - * status. - * 1: Full duplex 0: Half duplex - */ -#define RTL8201_BMCR_DUPLEX_MASK (0x100U) -#define RTL8201_BMCR_DUPLEX_SHIFT (8U) -#define RTL8201_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8201_BMCR_DUPLEX_SHIFT) & RTL8201_BMCR_DUPLEX_MASK) -#define RTL8201_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8201_BMCR_DUPLEX_MASK) >> RTL8201_BMCR_DUPLEX_SHIFT) - -/* - * COLLISION_TEST (RW) - * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - * When set, this bit will cause the COL signal to be asserted in - * response to the TXEN assertion within 512-bit times. The COL - * signal will be de-asserted within 4-bit times in response to the - * TXEN de-assertion. - */ -#define RTL8201_BMCR_COLLISION_TEST_MASK (0x80U) -#define RTL8201_BMCR_COLLISION_TEST_SHIFT (7U) -#define RTL8201_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8201_BMCR_COLLISION_TEST_SHIFT) & RTL8201_BMCR_COLLISION_TEST_MASK) -#define RTL8201_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8201_BMCR_COLLISION_TEST_MASK) >> RTL8201_BMCR_COLLISION_TEST_SHIFT) - -/* - * SPEED1 (RW) - * - * Speed Select Bit 1. - * Refer to bit 13. - */ -#define RTL8201_BMCR_SPEED1_MASK (0x40U) -#define RTL8201_BMCR_SPEED1_SHIFT (6U) -#define RTL8201_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8201_BMCR_SPEED1_SHIFT) & RTL8201_BMCR_SPEED1_MASK) -#define RTL8201_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8201_BMCR_SPEED1_MASK) >> RTL8201_BMCR_SPEED1_SHIFT) - -/* Bitfield definition for register: BMSR */ -/* - * 100BASE_T4 (RO) - * - * 1: Enable 100Base-T4 support - * 0: Suppress 100Base-T4 support - */ -#define RTL8201_BMSR_100BASE_T4_MASK (0x8000U) -#define RTL8201_BMSR_100BASE_T4_SHIFT (15U) -#define RTL8201_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_T4_MASK) >> RTL8201_BMSR_100BASE_T4_SHIFT) - -/* - * 100BASE_TX_FULL (RO) - * - * 1: Enable 100Base-TX full duplex support - * 0: Suppress 100Base-TX full duplex support - */ -#define RTL8201_BMSR_100BASE_TX_FULL_MASK (0x4000U) -#define RTL8201_BMSR_100BASE_TX_FULL_SHIFT (14U) -#define RTL8201_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_FULL_MASK) >> RTL8201_BMSR_100BASE_TX_FULL_SHIFT) - -/* - * 100BASE_TX_HALF (RO) - * - * 1: Enable 100Base-TX half duplex support - * 0: Suppress 100Base-TX half duplex support - */ -#define RTL8201_BMSR_100BASE_TX_HALF_MASK (0x2000U) -#define RTL8201_BMSR_100BASE_TX_HALF_SHIFT (13U) -#define RTL8201_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_100BASE_TX_HALF_MASK) >> RTL8201_BMSR_100BASE_TX_HALF_SHIFT) - -/* - * 10BASE_T_FULL (RO) - * - * 1: Enable 10Base-T full duplex support - * 0: Suppress 10Base-T full duplex support - */ -#define RTL8201_BMSR_10BASE_T_FULL_MASK (0x1000U) -#define RTL8201_BMSR_10BASE_T_FULL_SHIFT (12U) -#define RTL8201_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_FULL_MASK) >> RTL8201_BMSR_10BASE_T_FULL_SHIFT) - -/* - * 10BASE_T_HALF (RO) - * - * 1: Enable 10Base-T half duplex support - * 0: Suppress 10Base-T half duplex support - */ -#define RTL8201_BMSR_10BASE_T_HALF_MASK (0x800U) -#define RTL8201_BMSR_10BASE_T_HALF_SHIFT (11U) -#define RTL8201_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8201_BMSR_10BASE_T_HALF_MASK) >> RTL8201_BMSR_10BASE_T_HALF_SHIFT) - -/* - * PREAMBLE_SUPPRESSION (RO) - * - * The RTL8201F/FL/FN will accept management frames - * with preamble suppressed. - * A minimum of 32 preamble bits are required for the first - * management interface read/write transaction after reset. - * One idle bit is required between any two management - * transactions as per IEEE 802.3u specifications. - */ -#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U) -#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U) -#define RTL8201_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8201_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8201_BMSR_PREAMBLE_SUPPRESSION_SHIFT) - -/* - * AUTO_NEGOTIATION_COMPLETE (RO) - * - * 1: Auto-negotiation process completed - * 0: Auto-negotiation process not completed - */ -#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) -#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) -#define RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) - -/* - * REMOTE_FAULT (RC) - * - * 1: Remote fault condition detected (cleared on read) - * 0: No remote fault condition detected - * When in 100Base-FX mode, this bit means an in-band - * signal Far-End-Fault has been detected (see 8.10 Far End - * Fault Indication, page 39). - */ -#define RTL8201_BMSR_REMOTE_FAULT_MASK (0x10U) -#define RTL8201_BMSR_REMOTE_FAULT_SHIFT (4U) -#define RTL8201_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_REMOTE_FAULT_MASK) >> RTL8201_BMSR_REMOTE_FAULT_SHIFT) - -/* - * AUTO_NEGOTIATION_ABILITY (RO) - * - * 1: PHY is able to perform auto-negotiation - * 0: PHY is not able to perform auto-negotiation - */ -#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) -#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) -#define RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8201_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) - -/* - * LINK_STATUS (RO) - * - * 1: Valid link established - * 0: No valid link established - * This bit indicates whether the link was lost since the last - * read. For the current link status, read this register twice. - */ -#define RTL8201_BMSR_LINK_STATUS_MASK (0x4U) -#define RTL8201_BMSR_LINK_STATUS_SHIFT (2U) -#define RTL8201_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8201_BMSR_LINK_STATUS_MASK) >> RTL8201_BMSR_LINK_STATUS_SHIFT) - -/* - * JABBER_DETECT (RO) - * - * 1: Jabber condition detected - * 0: No jabber condition detected - */ -#define RTL8201_BMSR_JABBER_DETECT_MASK (0x2U) -#define RTL8201_BMSR_JABBER_DETECT_SHIFT (1U) -#define RTL8201_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8201_BMSR_JABBER_DETECT_MASK) >> RTL8201_BMSR_JABBER_DETECT_SHIFT) - -/* - * EXTENDED_CAPABILITY (RO) - * - * 1: Extended register capable (permanently=1) - * 0: Not extended register capable - */ -#define RTL8201_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) -#define RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) -#define RTL8201_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8201_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8201_BMSR_EXTENDED_CAPABILITY_SHIFT) - -/* Bitfield definition for register: PHYID1 */ -/* - * OUI_MSB (RO) - * - * Composed of the 6 th to 21 st bits of the Organizationally Unique - * Identifier (OUI), respectively. - */ -#define RTL8201_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define RTL8201_PHYID1_OUI_MSB_SHIFT (0U) -#define RTL8201_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID1_OUI_MSB_MASK) >> RTL8201_PHYID1_OUI_MSB_SHIFT) - -/* Bitfield definition for register: PHYID2 */ -/* - * OUI_LSB (RO) - * - * Assigned to the 0 through 5 th bits of the OUI. RO 110010 - */ -#define RTL8201_PHYID2_OUI_LSB_MASK (0xFC00U) -#define RTL8201_PHYID2_OUI_LSB_SHIFT (10U) -#define RTL8201_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_OUI_LSB_MASK) >> RTL8201_PHYID2_OUI_LSB_SHIFT) - -/* - * MODEL_NUMBER (RO) - * - * Model Number - */ -#define RTL8201_PHYID2_MODEL_NUMBER_MASK (0x3F0U) -#define RTL8201_PHYID2_MODEL_NUMBER_SHIFT (4U) -#define RTL8201_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_MODEL_NUMBER_MASK) >> RTL8201_PHYID2_MODEL_NUMBER_SHIFT) - -/* - * REVISION_NUMBER (RO) - * - * Revision Number - */ -#define RTL8201_PHYID2_REVISION_NUMBER_MASK (0xFU) -#define RTL8201_PHYID2_REVISION_NUMBER_SHIFT (0U) -#define RTL8201_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8201_PHYID2_REVISION_NUMBER_MASK) >> RTL8201_PHYID2_REVISION_NUMBER_SHIFT) - -/* Bitfield definition for register: RMSR_P7 */ -/* - * RG_RMII_CLKDIR (RW) - * - * This Bit Sets the Type of TXC in RMII Mode. - * 0: Output - * 1: Input - */ -#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK (0x1000U) -#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT (12U) -#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) -#define RTL8201_RMSR_P7_RG_RMII_CLKDIR_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_CLKDIR_MASK) >> RTL8201_RMSR_P7_RG_RMII_CLKDIR_SHIFT) - -/* - * RG_RMII_TX_OFFSET (RW) - * - * Adjust RMII TX Interface Timing. - */ -#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK (0xF00U) -#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT (8U) -#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) -#define RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_TX_OFFSET_SHIFT) - -/* - * RG_RMII_RX_OFFSET (RW) - * - * Adjust RMII RX Interface Timing. - */ -#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK (0xF0U) -#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT (4U) -#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) -#define RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_MASK) >> RTL8201_RMSR_P7_RG_RMII_RX_OFFSET_SHIFT) - -/* - * RMII_MODE (RW) - * - * 0: MII Mode - * 1: RMII Mode - */ -#define RTL8201_RMSR_P7_RMII_MODE_MASK (0x8U) -#define RTL8201_RMSR_P7_RMII_MODE_SHIFT (3U) -#define RTL8201_RMSR_P7_RMII_MODE_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RMII_MODE_SHIFT) & RTL8201_RMSR_P7_RMII_MODE_MASK) -#define RTL8201_RMSR_P7_RMII_MODE_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RMII_MODE_MASK) >> RTL8201_RMSR_P7_RMII_MODE_SHIFT) - -/* - * RG_RMII_RXDV_SEL (RW) - * - * 0: CRS/CRS_DV pin is CRS_DV signal - * 1: CRS/CRS_DV pin is RXDV signal - */ -#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK (0x4U) -#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT (2U) -#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) -#define RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDV_SEL_SHIFT) - -/* - * RG_RMII_RXDSEL (RW) - * - * 0: RMII data only - * 1: RMII data with SSD Error - */ -#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK (0x2U) -#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT (1U) -#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_SET(x) (((uint16_t)(x) << RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) -#define RTL8201_RMSR_P7_RG_RMII_RXDSEL_GET(x) (((uint16_t)(x) & RTL8201_RMSR_P7_RG_RMII_RXDSEL_MASK) >> RTL8201_RMSR_P7_RG_RMII_RXDSEL_SHIFT) - -/* Bitfield definition for register: PAGESEL */ -/* - * PAGE_SEL (RW) - * - * Select Page Address: 00000000~11111111. - */ -#define RTL8201_PAGESEL_PAGE_SEL_MASK (0xFFU) -#define RTL8201_PAGESEL_PAGE_SEL_SHIFT (0U) -#define RTL8201_PAGESEL_PAGE_SEL_SET(x) (((uint16_t)(x) << RTL8201_PAGESEL_PAGE_SEL_SHIFT) & RTL8201_PAGESEL_PAGE_SEL_MASK) -#define RTL8201_PAGESEL_PAGE_SEL_GET(x) (((uint16_t)(x) & RTL8201_PAGESEL_PAGE_SEL_MASK) >> RTL8201_PAGESEL_PAGE_SEL_SHIFT) - - - - -#endif /* HPM_RTL8201_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c deleted file mode 100644 index d7422f22b05..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_rtl8211_regs.h" -#include "hpm_rtl8211.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -static bool rtl8211_check_id(ENET_Type *ptr) -{ - uint16_t id1, id2; - - id1 = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_PHYID1); - id2 = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_PHYID2); - - if (RTL8211_PHYID1_OUI_MSB_GET(id1) == RTL8211_ID1 && RTL8211_PHYID2_OUI_LSB_GET(id2) == RTL8211_ID2) { - return true; - } else { - return false; - } -} - -/*--------------------------------------------------------------------- - * API - *--------------------------------------------------------------------- - */ -void rtl8211_reset(ENET_Type *ptr) -{ - uint16_t data; - - /* PHY reset */ - enet_write_phy(ptr, RTL8211_ADDR, RTL8211_BMCR, RTL8211_BMCR_RESET_SET(1)); - - /* wait until the reset is completed */ - do { - data = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_BMCR); - } while (RTL8211_BMCR_RESET_GET(data)); -} - -void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config) -{ - (void)ptr; - - config->loopback = false; /* Disable PCS loopback mode */ - #if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO) - config->auto_negotiation = false; /* Disable Auto-Negotiation */ - config->speed = enet_phy_port_speed_100mbps; - config->duplex = enet_phy_duplex_full; - #else - config->auto_negotiation = true; /* Enable Auto-Negotiation */ - #endif -} - -bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config) -{ - uint16_t data = 0; - - data |= RTL8211_BMCR_RESET_SET(0) /* Normal operation */ - | RTL8211_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */ - | RTL8211_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */ - | RTL8211_BMCR_PWD_SET(0) /* Normal operation */ - | RTL8211_BMCR_ISOLATE_SET(0) /* Normal operation */ - | RTL8211_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */ - | RTL8211_BMCR_COLLISION_TEST_SET(0); /* Normal operation */ - - if (config->auto_negotiation == 0) { - data |= RTL8211_BMCR_SPEED0_SET(config->speed) | RTL8211_BMCR_SPEED1_SET(config->speed >> 1); /* Set port speed */ - data |= RTL8211_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */ - } - - enet_write_phy(ptr, RTL8211_ADDR, RTL8211_BMCR, data); - - /* check the id of rtl8211 */ - if (rtl8211_check_id(ptr) == false) { - return false; - } - - return true; -} - - -void rtl8211_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status) -{ - uint16_t data; - - data = enet_read_phy(ptr, RTL8211_ADDR, RTL8211_PHYSR); - status->enet_phy_link = RTL8211_PHYSR_LINK_REAL_TIME_GET(data); - status->enet_phy_speed = RTL8211_PHYSR_SPEED_GET(data) == 0 ? enet_phy_port_speed_10mbps : RTL8211_PHYSR_SPEED_GET(data) == 1 ? enet_phy_port_speed_100mbps : enet_phy_port_speed_1000mbps; - status->enet_phy_duplex = RTL8211_PHYSR_DUPLEX_GET(data); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h deleted file mode 100644 index c9914ab7a0c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_RTL8211_H -#define HPM_RTL8211_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_phy.h" -#include "hpm_common.h" -#include "hpm_enet_regs.h" -/*--------------------------------------------------------------------- - * - * Macro Const Definitions - *--------------------------------------------------------------------- - */ -#ifndef RTL8211_ADDR -#define RTL8211_ADDR (2U) -#endif - -#define RTL8211_ID1 (0x001CU) -#define RTL8211_ID2 (0x32U) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -typedef struct { - bool loopback; - uint8_t speed; - bool auto_negotiation; - uint8_t duplex; -} rtl8211_config_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -void rtl8211_reset(ENET_Type *ptr); -void rtl8211_basic_mode_default_config(ENET_Type *ptr, rtl8211_config_t *config); -bool rtl8211_basic_mode_init(ENET_Type *ptr, rtl8211_config_t *config); -void rtl8211_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_RTL8211_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h b/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h deleted file mode 100644 index ac2343579de..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/rtl8211/hpm_rtl8211_regs.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTL8211_REGS_H -#define HPM_RTL8211_REGS_H - -typedef enum { - RTL8211_BMCR = 0, /* 0x0: Basic Mode Control Register */ - RTL8211_BMSR = 1, /* 0x1: Basic Mode Status Register */ - RTL8211_PHYID1 = 2, /* 0x2: PHY Identifier Register 1 */ - RTL8211_PHYID2 = 3, /* 0x3: PHY Identifier Register 2 */ - RTL8211_PHYSR = 17, /* 0x11: PHY Specific Status Register */ -} RTL8211_REG_Type; - - -/* Bitfield definition for register: BMCR */ -/* - * RESET (RW/SC) - * - * Reset. - * 1: PHY reset - * 0: Normal operation - * Register 0 (BMCR) and register 1 (BMSR) will return to default - * values after a software reset (set Bit15 to 1). - * This action may change the internal PHY state and the state of the - * physical link associated with the PHY. - */ -#define RTL8211_BMCR_RESET_MASK (0x8000U) -#define RTL8211_BMCR_RESET_SHIFT (15U) -#define RTL8211_BMCR_RESET_SET(x) (((uint16_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) -#define RTL8211_BMCR_RESET_GET(x) (((uint16_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) - -/* - * LOOPBACK (RW) - * - * Loopback Mode. - * 1: Enable PCS loopback mode - * 0: Disable PCS loopback mode - */ -#define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) -#define RTL8211_BMCR_LOOPBACK_SHIFT (14U) -#define RTL8211_BMCR_LOOPBACK_SET(x) (((uint16_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) -#define RTL8211_BMCR_LOOPBACK_GET(x) (((uint16_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) - -/* - * SPEED0 (RW) - * - * Speed Select (Bits 6, 13): - * When auto-negotiation is disabled writing to this bit allows the port - * speed to be selected. - * 11 = Reserved - * 10 = Reserved - * 1 = 100 Mbps - * 0 = 10 Mbps - */ -#define RTL8211_BMCR_SPEED0_MASK (0x2000U) -#define RTL8211_BMCR_SPEED0_SHIFT (13U) -#define RTL8211_BMCR_SPEED0_SET(x) (((uint16_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) -#define RTL8211_BMCR_SPEED0_GET(x) (((uint16_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) - -/* - * ANE (RW) - * - * Auto-Negotiation Enable. - * 1: Enable Auto-Negotiation - * 0: Disable Auto-Negotiation - */ -#define RTL8211_BMCR_ANE_MASK (0x1000U) -#define RTL8211_BMCR_ANE_SHIFT (12U) -#define RTL8211_BMCR_ANE_SET(x) (((uint16_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) -#define RTL8211_BMCR_ANE_GET(x) (((uint16_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) - -/* - * PWD (RW) - * - * Power Down. - * 1: Power down (only Management Interface and logic are active; link - * is down) - * 0: Normal operation - */ -#define RTL8211_BMCR_PWD_MASK (0x800U) -#define RTL8211_BMCR_PWD_SHIFT (11U) -#define RTL8211_BMCR_PWD_SET(x) (((uint16_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) -#define RTL8211_BMCR_PWD_GET(x) (((uint16_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) - -/* - * ISOLATE (RW) - * - * Isolate. - * 1: RGMII/GMII interface is isolated; the serial management interface - * (MDC, MDIO) is still active. When this bit is asserted, the - * RTL8211E-VB(VL)/RTL8211EG-VB ignores TXD[7:0], and TXCLT - * inputs, and presents a high impedance on TXC, RXC, RXCLT, - * RXD[7:0]. - * 0: Normal operation - */ -#define RTL8211_BMCR_ISOLATE_MASK (0x400U) -#define RTL8211_BMCR_ISOLATE_SHIFT (10U) -#define RTL8211_BMCR_ISOLATE_SET(x) (((uint16_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) -#define RTL8211_BMCR_ISOLATE_GET(x) (((uint16_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) - -/* - * RESTART_AN (RW/SC) - * - * Restart Auto-Negotiation. - * 1: Restart Auto-Negotiation - * 0: Normal operation - */ -#define RTL8211_BMCR_RESTART_AN_MASK (0x200U) -#define RTL8211_BMCR_RESTART_AN_SHIFT (9U) -#define RTL8211_BMCR_RESTART_AN_SET(x) (((uint16_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) -#define RTL8211_BMCR_RESTART_AN_GET(x) (((uint16_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) - -/* - * DUPLEX (RW) - * - * Duplex Mode. - * 1: Full Duplex operation - * 0: Half Duplex operation - * This bit is valid only in force mode, i.e., NWay is disabled. - */ -#define RTL8211_BMCR_DUPLEX_MASK (0x100U) -#define RTL8211_BMCR_DUPLEX_SHIFT (8U) -#define RTL8211_BMCR_DUPLEX_SET(x) (((uint16_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) -#define RTL8211_BMCR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) - -/* - * COLLISION_TEST (RW) - * - * Collision Test. - * 1: Collision test enabled - * 0: Normal operation - */ -#define RTL8211_BMCR_COLLISION_TEST_MASK (0x80U) -#define RTL8211_BMCR_COLLISION_TEST_SHIFT (7U) -#define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint16_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) -#define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint16_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) - -/* - * SPEED1 (RW) - * - * Speed Select Bit 1. - * Refer to bit 13. - */ -#define RTL8211_BMCR_SPEED1_MASK (0x40U) -#define RTL8211_BMCR_SPEED1_SHIFT (6U) -#define RTL8211_BMCR_SPEED1_SET(x) (((uint16_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) -#define RTL8211_BMCR_SPEED1_GET(x) (((uint16_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) - -/* Bitfield definition for register: BMSR */ -/* - * 100BASE_T4 (RO) - * - * 100Base-T4 Capability. - * The RTL8211E-VB(VL)/RTL8211EG-VB does not support - * 100Base-T4 mode. This bit should always be 0. - */ -#define RTL8211_BMSR_100BASE_T4_MASK (0x8000U) -#define RTL8211_BMSR_100BASE_T4_SHIFT (15U) -#define RTL8211_BMSR_100BASE_T4_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_T4_MASK) >> RTL8211_BMSR_100BASE_T4_SHIFT) - -/* - * 100BASE_TX_FULL (RO) - * - * 100Base-TX Full Duplex Capability. - * 1: Device is able to perform 100Base-TX in full duplex mode - * 0: Device is not able to perform 100Base-TX in full duplex mode - */ -#define RTL8211_BMSR_100BASE_TX_FULL_MASK (0x4000U) -#define RTL8211_BMSR_100BASE_TX_FULL_SHIFT (14U) -#define RTL8211_BMSR_100BASE_TX_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_TX_FULL_MASK) >> RTL8211_BMSR_100BASE_TX_FULL_SHIFT) - -/* - * 100BASE_TX_HALF (RO) - * - * 100Base-TX Half Duplex Capability. - * 1: Device is able to perform 100Base-TX in half duplex mode - * 0: Device is not able to perform 100Base-TX in half duplex mode - */ -#define RTL8211_BMSR_100BASE_TX_HALF_MASK (0x2000U) -#define RTL8211_BMSR_100BASE_TX_HALF_SHIFT (13U) -#define RTL8211_BMSR_100BASE_TX_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_100BASE_TX_HALF_MASK) >> RTL8211_BMSR_100BASE_TX_HALF_SHIFT) - -/* - * 10BASE_T_FULL (RO) - * - * 10Base-T Full Duplex Capability. - * 1: Device is able to perform 10Base-T in full duplex mode. - * 0: Device is not able to perform 10Base-T in full duplex mode. - */ -#define RTL8211_BMSR_10BASE_T_FULL_MASK (0x1000U) -#define RTL8211_BMSR_10BASE_T_FULL_SHIFT (12U) -#define RTL8211_BMSR_10BASE_T_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T_FULL_MASK) >> RTL8211_BMSR_10BASE_T_FULL_SHIFT) - -/* - * 10BASE_T_HALF (RO) - * - * 10Base-T Half Duplex Capability. - * 1: Device is able to perform 10Base-T in half duplex mode - * 0: Device is not able to perform 10Base-T in half duplex mode - */ -#define RTL8211_BMSR_10BASE_T_HALF_MASK (0x800U) -#define RTL8211_BMSR_10BASE_T_HALF_SHIFT (11U) -#define RTL8211_BMSR_10BASE_T_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T_HALF_MASK) >> RTL8211_BMSR_10BASE_T_HALF_SHIFT) - -/* - * 10BASE_T2_FULL (RO) - * - * 10Base-T2 Full Duplex Capability. - * The RTL8211E-VB(VL)/RTL8211EG-VB does not support - * 10Base-T2 mode and this bit should always be 0. - */ -#define RTL8211_BMSR_10BASE_T2_FULL_MASK (0x400U) -#define RTL8211_BMSR_10BASE_T2_FULL_SHIFT (10U) -#define RTL8211_BMSR_10BASE_T2_FULL_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T2_FULL_MASK) >> RTL8211_BMSR_10BASE_T2_FULL_SHIFT) - -/* - * 10BASE_T2_HALF (RO) - * - * 10Base-T2 Half Duplex Capability. - * The RTL8211E-VB(VL)/RTL8211EG-VB does not support - * 10Base-T2 mode. This bit should always be 0. - */ -#define RTL8211_BMSR_10BASE_T2_HALF_MASK (0x200U) -#define RTL8211_BMSR_10BASE_T2_HALF_SHIFT (9U) -#define RTL8211_BMSR_10BASE_T2_HALF_GET(x) (((uint16_t)(x) & RTL8211_BMSR_10BASE_T2_HALF_MASK) >> RTL8211_BMSR_10BASE_T2_HALF_SHIFT) - -/* - * 1000BASE_T_EXTENDED_STATUS (RO) - * - * 1000Base-T Extended Status Register. - * 1: Device supports Extended Status Register 0x0F (15) - * 0: Device does not support Extended Status Register 0x0F - * This register is read-only and is always set to 1. - */ -#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_MASK (0x100U) -#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_SHIFT (8U) -#define RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_GET(x) (((uint16_t)(x) & RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_MASK) >> RTL8211_BMSR_1000BASE_T_EXTENDED_STATUS_SHIFT) - -/* - * PREAMBLE_SUPPRESSION (RO) - * - * Preamble Suppression Capability (Permanently On). - * The RTL8211E-VB(VL)/RTL8211EG-VB always accepts - * transactions with preamble suppressed. - */ -#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_MASK (0x40U) -#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_SHIFT (6U) -#define RTL8211_BMSR_PREAMBLE_SUPPRESSION_GET(x) (((uint16_t)(x) & RTL8211_BMSR_PREAMBLE_SUPPRESSION_MASK) >> RTL8211_BMSR_PREAMBLE_SUPPRESSION_SHIFT) - -/* - * AUTO_NEGOTIATION_COMPLETE (RO) - * - * Auto-Negotiation Complete. - * 1: Auto-Negotiation process complete, and contents of registers - * 5, 6, 8, and 10 are valid - * 0: Auto-Negotiation process not complete - */ -#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK (0x20U) -#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT (5U) -#define RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_GET(x) (((uint16_t)(x) & RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_MASK) >> RTL8211_BMSR_AUTO_NEGOTIATION_COMPLETE_SHIFT) - -/* - * REMOTE_FAULT (RC) - * - * Remote Fault. - * 1: Remote fault condition detected (cleared on read or by reset). - * Indication or notification of remote fault from Link Partner - * 0: No remote fault condition detected - */ -#define RTL8211_BMSR_REMOTE_FAULT_MASK (0x10U) -#define RTL8211_BMSR_REMOTE_FAULT_SHIFT (4U) -#define RTL8211_BMSR_REMOTE_FAULT_GET(x) (((uint16_t)(x) & RTL8211_BMSR_REMOTE_FAULT_MASK) >> RTL8211_BMSR_REMOTE_FAULT_SHIFT) - -/* - * AUTO_NEGOTIATION_ABILITY (RO) - * - * Auto Configured Link. - * 1: Device is able to perform Auto-Negotiation - * 0: Device is not able to perform Auto-Negotiation - */ -#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_MASK (0x8U) -#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT (3U) -#define RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_GET(x) (((uint16_t)(x) & RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_MASK) >> RTL8211_BMSR_AUTO_NEGOTIATION_ABILITY_SHIFT) - -/* - * LINK_STATUS (RO) - * - * Link Status. - * 1: Linked - * 0: Not Linked - * This register indicates whether the link was lost since the last read. - * For the current link status, either read this register twice or read - * register bit 17.10 Link Real Time. - */ -#define RTL8211_BMSR_LINK_STATUS_MASK (0x4U) -#define RTL8211_BMSR_LINK_STATUS_SHIFT (2U) -#define RTL8211_BMSR_LINK_STATUS_GET(x) (((uint16_t)(x) & RTL8211_BMSR_LINK_STATUS_MASK) >> RTL8211_BMSR_LINK_STATUS_SHIFT) - -/* - * JABBER_DETECT (RC) - * - * Jabber Detect. - * 1: Jabber condition detected - * 0: No Jabber occurred - */ -#define RTL8211_BMSR_JABBER_DETECT_MASK (0x2U) -#define RTL8211_BMSR_JABBER_DETECT_SHIFT (1U) -#define RTL8211_BMSR_JABBER_DETECT_GET(x) (((uint16_t)(x) & RTL8211_BMSR_JABBER_DETECT_MASK) >> RTL8211_BMSR_JABBER_DETECT_SHIFT) - -/* - * EXTENDED_CAPABILITY (RO) - * - * 1: Extended register capabilities, always 1 - */ -#define RTL8211_BMSR_EXTENDED_CAPABILITY_MASK (0x1U) -#define RTL8211_BMSR_EXTENDED_CAPABILITY_SHIFT (0U) -#define RTL8211_BMSR_EXTENDED_CAPABILITY_GET(x) (((uint16_t)(x) & RTL8211_BMSR_EXTENDED_CAPABILITY_MASK) >> RTL8211_BMSR_EXTENDED_CAPABILITY_SHIFT) - -/* Bitfield definition for register: PHYID1 */ -/* - * OUI_MSB (RO) - * - * Organizationally Unique Identifier Bit 3:18. - * Always 0000000000011100. - */ -#define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) -#define RTL8211_PHYID1_OUI_MSB_SHIFT (0U) -#define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint16_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) - -/* Bitfield definition for register: PHYID2 */ -/* - * OUI_LSB (RO) - * - * Organizationally Unique Identifier Bit 19:24. - * Always 110010. - */ -#define RTL8211_PHYID2_OUI_LSB_MASK (0xFC00U) -#define RTL8211_PHYID2_OUI_LSB_SHIFT (10U) -#define RTL8211_PHYID2_OUI_LSB_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_OUI_LSB_MASK) >> RTL8211_PHYID2_OUI_LSB_SHIFT) - -/* - * MODEL_NUMBER (RO) - * - * Manufacture’s Model Number - */ -#define RTL8211_PHYID2_MODEL_NUMBER_MASK (0x3F0U) -#define RTL8211_PHYID2_MODEL_NUMBER_SHIFT (4U) -#define RTL8211_PHYID2_MODEL_NUMBER_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_MODEL_NUMBER_MASK) >> RTL8211_PHYID2_MODEL_NUMBER_SHIFT) - -/* - * REVISION_NUMBER (RO) - * - * Revision Number - */ -#define RTL8211_PHYID2_REVISION_NUMBER_MASK (0xFU) -#define RTL8211_PHYID2_REVISION_NUMBER_SHIFT (0U) -#define RTL8211_PHYID2_REVISION_NUMBER_GET(x) (((uint16_t)(x) & RTL8211_PHYID2_REVISION_NUMBER_MASK) >> RTL8211_PHYID2_REVISION_NUMBER_SHIFT) - -/* Bitfield definition for register: PHYSR */ -/* - * SPEED (RO) - * - * Link Speed. - * 11: Reserved 10: 1000Mbps - * 01: 100Mbps 00: 10Mbps - */ -#define RTL8211_PHYSR_SPEED_MASK (0xC000U) -#define RTL8211_PHYSR_SPEED_SHIFT (14U) -#define RTL8211_PHYSR_SPEED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_SPEED_MASK) >> RTL8211_PHYSR_SPEED_SHIFT) - -/* - * DUPLEX (RO) - * - * Full/Half Duplex Mode. - * 1: Full duplex 0: Half duplex - */ -#define RTL8211_PHYSR_DUPLEX_MASK (0x2000U) -#define RTL8211_PHYSR_DUPLEX_SHIFT (13U) -#define RTL8211_PHYSR_DUPLEX_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_DUPLEX_MASK) >> RTL8211_PHYSR_DUPLEX_SHIFT) - -/* - * PAGE_RECEIVED (RC) - * - * New Page Received. - * 1: Page received 0: Page not received - */ -#define RTL8211_PHYSR_PAGE_RECEIVED_MASK (0x1000U) -#define RTL8211_PHYSR_PAGE_RECEIVED_SHIFT (12U) -#define RTL8211_PHYSR_PAGE_RECEIVED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_PAGE_RECEIVED_MASK) >> RTL8211_PHYSR_PAGE_RECEIVED_SHIFT) - -/* - * SPEED_AND_DUPLEX_RESOLVED (RO) - * - * Speed and Duplex Mode Resolved. - * 1: Resolved 0: Not resolved - */ -#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_MASK (0x800U) -#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_SHIFT (11U) -#define RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_MASK) >> RTL8211_PHYSR_SPEED_AND_DUPLEX_RESOLVED_SHIFT) - -/* - * LINK_REAL_TIME (RO) - * - * Real Time Link Status. - * 1: Link OK 0: Link not OK - */ -#define RTL8211_PHYSR_LINK_REAL_TIME_MASK (0x400U) -#define RTL8211_PHYSR_LINK_REAL_TIME_SHIFT (10U) -#define RTL8211_PHYSR_LINK_REAL_TIME_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_LINK_REAL_TIME_MASK) >> RTL8211_PHYSR_LINK_REAL_TIME_SHIFT) - -/* - * MDI_CROSSOVER_STATUS (RO) - * - * MDI/MDI Crossover Status. - * 1: MDI Crossover 0: MDI - */ -#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_MASK (0x40U) -#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_SHIFT (6U) -#define RTL8211_PHYSR_MDI_CROSSOVER_STATUS_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_MDI_CROSSOVER_STATUS_MASK) >> RTL8211_PHYSR_MDI_CROSSOVER_STATUS_SHIFT) - -/* - * PRE_LINKOK (RO) - * - * Reflects Local Receiver is OK. - * 0: Receiver is not OK - * 1: Receiver is OK - */ -#define RTL8211_PHYSR_PRE_LINKOK_MASK (0x2U) -#define RTL8211_PHYSR_PRE_LINKOK_SHIFT (1U) -#define RTL8211_PHYSR_PRE_LINKOK_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_PRE_LINKOK_MASK) >> RTL8211_PHYSR_PRE_LINKOK_SHIFT) - -/* - * JABBER_REAL_TIME (RO) - * - * Real Time Jabber Indication. - * 1: Jabber Indication 0: No jabber Indication - */ -#define RTL8211_PHYSR_JABBER_REAL_TIME_MASK (0x1U) -#define RTL8211_PHYSR_JABBER_REAL_TIME_SHIFT (0U) -#define RTL8211_PHYSR_JABBER_REAL_TIME_GET(x) (((uint16_t)(x) & RTL8211_PHYSR_JABBER_REAL_TIME_MASK) >> RTL8211_PHYSR_JABBER_REAL_TIME_SHIFT) - - - - -#endif /* HPM_RTL8211_REGS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c deleted file mode 100644 index 100c1db7b95..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_common.h" -#include "hpm_ipc_event_mgr.h" -#include "hpm_ipc_event_mgr_mbx_internal.h" - -/***************************************************************************************************************** - * - * Definitions - * - *****************************************************************************************************************/ - -/***************************************************************************************************************** - * - * Prototypes - * - *****************************************************************************************************************/ - -/***************************************************************************************************************** - * - * Variables - * - *****************************************************************************************************************/ -static ipc_event_t s_ipc_event_table[ipc_event_table_len]; - -/***************************************************************************************************************** - * - * Codes - * - *****************************************************************************************************************/ -void ipc_init(void) -{ - ipc_init_internal(); -} - -void ipc_enable_event_interrupt(uint32_t priority) -{ - ipc_enable_event_interrupt_internal(priority); -} - -void ipc_disable_event_interrupt(void) -{ - ipc_disable_event_interrupt_internal(); -} - -hpm_stat_t ipc_register_event(ipc_event_type_t type, ipc_event_callback_t callback, void *callback_data) -{ - hpm_stat_t status; - - if ((type >= ipc_event_table_len) || (callback == NULL)) { - status = status_invalid_argument; - } else { - s_ipc_event_table[type].callback = callback; - s_ipc_event_table[type].callback_data = callback_data; - status = status_success; - } - - return status; -} - -hpm_stat_t ipc_tigger_event(ipc_event_type_t type, uint16_t event_data) -{ - hpm_stat_t status; - uint32_t remote_data; - - if (type >= ipc_event_table_len) { - status = status_invalid_argument; - } else { - remote_data = (((uint32_t)type) << 16) | event_data; - ipc_tigger_event_internal(remote_data); - status = status_success; - } - - return status; -} - -void ipc_event_handler(uint32_t data) -{ - uint16_t event_type; - uint16_t event_data; - - if (0U != data) { - event_type = (uint16_t)(data >> 16u); - event_data = (uint16_t)(data & 0x0000FFFFu); - - if (((ipc_event_type_t)event_type >= ipc_remote_start_event) && ((ipc_event_type_t)event_type < ipc_event_table_len)) { - if (s_ipc_event_table[(ipc_event_type_t)event_type].callback != NULL) { - s_ipc_event_table[(ipc_event_type_t)event_type].callback( - event_data, s_ipc_event_table[(ipc_event_type_t)event_type].callback_data); - } - } - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h deleted file mode 100644 index a4c6e4e9365..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/hpm_ipc_event_mgr.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_IPC_EVENT_MGR_H -#define HPM_IPC_EVENT_MGR_H - -#ifdef __cplusplus - -extern "C" { -#endif - -/** - * @brief Type definition of event callback function pointer. - * - * @param [in] event data - * @param [in] callback context data - */ -typedef void (*ipc_event_callback_t)(uint16_t event_data, void *context); - -/** - * @brief Type definition of structure with event handler and data. - */ -typedef struct { - ipc_event_callback_t callback; /**< Pointer to callback function.*/ - void *callback_data; /**< Context data for callback.*/ -} ipc_event_t; - -/** - * @brief Type definition of event types. - */ -typedef enum { - ipc_remote_start_event = 1, - ipc_remote_rpmsg_event, - ipc_event_table_len -} ipc_event_type_t; - -/** - * @brief IPC Init. - */ -void ipc_init(void); - -/** - * @brief Enbale IPC event interrupt. - * - * @param [in] interrupt priority - */ -void ipc_enable_event_interrupt(uint32_t priority); - -/** - * @brief Disbale IPC event interrupt. - */ -void ipc_disable_event_interrupt(void); - -/** - * @brief Register IPC event - * - * @param [in] event type - * @param [in] event callback function - * @param [in] event callback data - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if the parameter is invalid - */ -hpm_stat_t ipc_register_event(ipc_event_type_t type, ipc_event_callback_t callback, void *callback_data); - -/** - * @brief Trigger IPC event - * - * @param [in] event type - * @param [in] event data - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t ipc_tigger_event(ipc_event_type_t type, uint16_t event_data); - -/*! - * @brief event handler - * - * This function is called when event received - * - * @param [in] event type and data. - */ -void ipc_event_handler(uint32_t data); - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_IPC_EVENT_MGR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h deleted file mode 100644 index f71116127ee..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_config.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_IPC_EVENT_MGR_MBX_CONFIG_H -#define HPM_IPC_EVENT_MGR_MBX_CONFIG_H - - -#if defined(HPM_FEATURE_MBX_SIDE_A) -#define HPM_MBX HPM_MBX0A -#define IRQn_MBX IRQn_MBX0A -#elif defined(HPM_FEATURE_MBX_SIDE_B) -#define HPM_MBX HPM_MBX0B -#define IRQn_MBX IRQn_MBX0B -#endif - - -#endif /* HPM_IPC_EVENT_MGR_MBX_CONFIG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c deleted file mode 100644 index ebdb0e6c514..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_soc.h" -#include "hpm_mbx_drv.h" -#include "hpm_ipc_event_mgr.h" -#include "hpm_ipc_event_mgr_mbx_config.h" -#include "hpm_ipc_event_mgr_mbx_internal.h" - -/***************************************************************************************************************** - * - * Definitions - * - *****************************************************************************************************************/ - -/***************************************************************************************************************** - * - * Prototypes - * - *****************************************************************************************************************/ -static void mbx_isr(void); -SDK_DECLARE_EXT_ISR_M(IRQn_MBX, mbx_isr) - -/***************************************************************************************************************** - * - * Variables - * - *****************************************************************************************************************/ - -/***************************************************************************************************************** - * - * Codes - * - *****************************************************************************************************************/ -void ipc_init_internal(void) -{ - mbx_init(HPM_MBX); -} - -void ipc_enable_event_interrupt_internal(uint32_t priority) -{ - mbx_enable_intr(HPM_MBX, MBX_CR_RWMVIE_MASK); - intc_m_enable_irq_with_priority(IRQn_MBX, priority); -} - -void ipc_disable_event_interrupt_internal(void) -{ - mbx_disable_intr(HPM_MBX, MBX_CR_RWMVIE_MASK); - intc_m_disable_irq(IRQn_MBX); -} - -hpm_stat_t ipc_tigger_event_internal(uint32_t remote_data) -{ - return mbx_send_message(HPM_MBX, remote_data); -} - -/*! - * @brief ISR handler - * - * This function is called when data from MBX is received - */ -static void mbx_isr(void) -{ - uint32_t data; - hpm_stat_t state; - - state = mbx_retrieve_message(HPM_MBX, &data); - - if (state == status_success) { - ipc_event_handler(data); - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h b/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h deleted file mode 100644 index cb22df04b33..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ipc_event_mgr/mbx/hpm_ipc_event_mgr_mbx_internal.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_IPC_EVENT_MGR_MBX_INTERNAL_H -#define HPM_IPC_EVENT_MGR_MBX_INTERNAL_H - -#ifdef __cplusplus - -extern "C" { -#endif - -/** - * @brief Initial MBX. - */ -void ipc_init_internal(void); - -/** - * @brief Enbale MBX event interrupt - * - * @param [in] interrupt priority - */ -void ipc_enable_event_interrupt_internal(uint32_t priority); - -/** - * @brief Disbale MBX event interrupt - */ -void ipc_disable_event_interrupt_internal(void); - -/** - * @brief Trigger MBX event - * - * @param [in] remote data - * - * @retval status_success if no error occurred - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t ipc_tigger_event_internal(uint32_t remote_data); - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_IPC_EVENT_MGR_MBX_INTERNAL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.c b/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.c deleted file mode 100644 index 02d55c97b9f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.c +++ /dev/null @@ -1,122 +0,0 @@ - -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_panel.h" -#include "hpm_clock_drv.h" - -extern hpm_panel_t panel_tm070rdh13; -extern hpm_panel_t panel_cc10128007; -extern hpm_panel_t panel_mc10128007_31b; -extern hpm_panel_t panel_tm103xdgp01; - -static hpm_panel_t *panel_list[] = { -#if defined(CONFIG_PANEL_RGB_TM070RDH13) && CONFIG_PANEL_RGB_TM070RDH13 - &panel_tm070rdh13, -#endif - -#if defined(CONFIG_PANEL_LVDS_CC10128007) && CONFIG_PANEL_LVDS_CC10128007 - &panel_cc10128007, -#endif - -#if defined(CONFIG_PANEL_MIPI_MC10128007_31B) && CONFIG_PANEL_MIPI_MC10128007_31B - &panel_mc10128007_31b, -#endif - -#if defined(CONFIG_PANEL_LVDS_TM103XDGP01) && CONFIG_PANEL_LVDS_TM103XDGP01 - &panel_tm103xdgp01, -#endif -}; - -hpm_panel_t *hpm_panel_find_device_default(void) -{ - if (sizeof(panel_list) > 0) - return panel_list[0]; - return NULL; -} - -hpm_panel_t *hpm_panel_find_device(const char *name) -{ - int n = sizeof(panel_list) / sizeof(panel_list[0]); - - for (int i = 0; i < n; i++) - if (!strcmp(panel_list[i]->name, name)) - return panel_list[i]; - - return NULL; -} - -const char *hpm_panel_get_name(hpm_panel_t *panel) -{ - return panel->name; -} - -const hpm_panel_timing_t *hpm_panel_get_timing(hpm_panel_t *panel) -{ - return &panel->timing; -} - -hpm_panel_if_type_t hpm_panel_get_if_type(hpm_panel_t *panel) -{ - return panel->if_type; -} - -void hpm_panel_register_interface(hpm_panel_t *panel, hpm_panel_hw_interface_t *hw_if) -{ - if (hw_if) - memcpy(&panel->hw_if, hw_if, sizeof(*hw_if)); -} - -void hpm_panel_reset(hpm_panel_t *panel) -{ - if (panel->funcs.reset) - panel->funcs.reset(panel); -} - -void hpm_panel_init(hpm_panel_t *panel) -{ - if (panel->funcs.init) - panel->funcs.init(panel); -} - -void hpm_panel_power_on(hpm_panel_t *panel) -{ - if (panel->funcs.power_on) - panel->funcs.power_on(panel); -} - -void hpm_panel_power_off(hpm_panel_t *panel) -{ - if (panel->funcs.power_off) - panel->funcs.power_off(panel); -} - -void hpm_panel_set_backlight(hpm_panel_t *panel, uint16_t percent) -{ - if (percent > 100) - percent = 100; - - if (panel->hw_if.set_backlight && - panel->state.backlight_percent != percent) { - panel->hw_if.set_backlight(percent); - panel->state.backlight_percent = percent; - } -} - -uint8_t hpm_panel_get_backlight(hpm_panel_t *panel) -{ - return panel->state.backlight_percent; -} - -void hpm_panel_delay_ms(uint32_t ms) -{ - clock_cpu_delay_ms(ms); -} - -void hpm_panel_delay_us(uint32_t us) -{ - clock_cpu_delay_us(us); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.h b/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.h deleted file mode 100644 index d5acf271296..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/panel/hpm_panel.h +++ /dev/null @@ -1,213 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_PANEL_H -#define _HPM_PANEL_H - -#include -#include -#include - -struct hpm_panel; -typedef struct hpm_panel hpm_panel_t; - -typedef struct hpm_panel_timing { - uint32_t pixel_clock_khz; /*!< pixel clocl,UINT: KHz */ - uint32_t hactive; /*!< Horizontal active video */ - uint32_t hfront_porch; /*!< Horizontal Front Porch */ - uint32_t hback_porch; /*!< Horizontal Back Porch */ - uint32_t hsync_len; /*!< Horizontal sync len */ - - uint32_t vactive; /*!< Vertical active video */ - uint32_t vfront_porch; /*!< Vertical Front Porch */ - uint32_t vback_porch; /*!< Vertical Back Porch */ - uint32_t vsync_len; /*!< Vertical sync len */ - uint32_t hsync_pol :1; /*!< Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active */ - uint32_t vsync_pol :1; /*!< Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active */ - uint32_t de_pol :1; /*!< Data Enable Signal Polarity, 0: High Active, 1: Low Active */ - uint32_t pixel_clk_pol :1; /*!< Pixel Clock Signal Polarity, 0: High Active, 1: Low Active */ - uint32_t pixel_data_pol :1;/*!< Pixel Data Signal Polarity, 0: High Active, 1: Low Active */ -} hpm_panel_timing_t; - -typedef enum hpm_panel_mipi_format { - HPM_PANEL_MIPI_FORMAT_RGB888, - HPM_PANEL_MIPI_FORMAT_RGB666, - HPM_PANEL_MIPI_FORMAT_RGB666_PACKED, - HPM_PANEL_MIPI_FORMAT_RGB565 -} hpm_panel_mipi_format; - -typedef struct hpm_panel_hw_interface { - uint32_t lcdc_pixel_clk_khz; - void (*set_reset_pin_level)(uint8_t level); - void (*set_backlight)(uint16_t percent); - void (*set_video_router)(void); - union { - struct { - hpm_panel_mipi_format format; - void *mipi_host_base; - void *mipi_phy_base; - } mipi; - struct { - uint32_t channel_di_index :8; - uint32_t channel_index :8; - void *lvb_base; - } lvds; - } video; -} hpm_panel_hw_interface_t; - -typedef struct hpm_panel_funcs { - void (*reset)(hpm_panel_t *panel); - void (*init)(hpm_panel_t *panel); - void (*power_on)(hpm_panel_t *panel); - void (*power_off)(hpm_panel_t *panel); -} hpm_panel_funcs_t; - -typedef enum hpm_panel_if_type { - HPM_PANEL_IF_TYPE_RGB, - HPM_PANEL_IF_TYPE_LVDS_SINGLE, - HPM_PANEL_IF_TYPE_LVDS_SPLIT, - HPM_PANEL_IF_TYPE_MIPI, -} hpm_panel_if_type_t; - -typedef enum hpm_panel_state_power { - HPM_PANEL_STATE_POWER_OFF, - HPM_PANEL_STATE_POWER_ON -} hpm_panel_power_state_t; - -typedef struct hpm_panel_state { - uint8_t backlight_percent; - uint8_t power_state; -} hpm_panel_state_t; - -struct hpm_panel { - const char *name; - hpm_panel_if_type_t if_type; - const hpm_panel_timing_t timing; - hpm_panel_state_t state; - hpm_panel_hw_interface_t hw_if; - hpm_panel_funcs_t funcs; -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Find default panel - * - * @return pointer of panel instance - */ -hpm_panel_t *hpm_panel_find_device_default(void); - -/** - * @brief Find panel for name - * - * @param [in] name of panel - * - * @return pointer of panel instance - */ -hpm_panel_t *hpm_panel_find_device(const char *name); - -/** - * @brief Get panel name - * - * @param panel pointer of panel instance - * - * @return panel name - */ -const char *hpm_panel_get_name(hpm_panel_t *panel); - -/** - * @brief Get panel timing - * - * @param panel pointer of panel instance - * - * @return pointer of timing - */ -const hpm_panel_timing_t *hpm_panel_get_timing(hpm_panel_t *panel); - -/** - * @brief Get panel interface type - * - * @param [in] panel pointer of panel instance - * - * @return panel interface type @ref hpm_panel_if_type_t - */ -hpm_panel_if_type_t hpm_panel_get_if_type(hpm_panel_t *panel); - -/** - * @brief Register platform level hardware interface - * - * @param [in] panel pointer of panel instance - * @param [in] hw_if pointer of hardware interface - */ -void hpm_panel_register_interface(hpm_panel_t *panel, hpm_panel_hw_interface_t *hw_if); - -/** - * @brief Reset the panel - * - * @param [in] panel pointer of panel instance - */ -void hpm_panel_reset(hpm_panel_t *panel); - -/** - * @brief Initialize the panel - * - * @param [in] panel pointer of panel instance - */ -void hpm_panel_init(hpm_panel_t *panel); - -/** - * @brief Power on the panel - * - * @param [in] panel pointer of panel instance - */ -void hpm_panel_power_on(hpm_panel_t *panel); - -/** - * @brief Power off the panel - * - * @param [in] panel pointer of panel instance - */ -void hpm_panel_power_off(hpm_panel_t *panel); - -/** - * @brief Set backlight value - * - * @param [in] panel pointer of panel instance - * @param [in] percent percent of backlight [0 - 100] - */ -void hpm_panel_set_backlight(hpm_panel_t *panel, uint16_t percent); - -/** - * - * @brief Get backlight value - * - * @param [in] panel pointer of panel instance - * @return percent of backlight [0 - 100] - */ -uint8_t hpm_panel_get_backlight(hpm_panel_t *panel); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void hpm_panel_delay_ms(uint32_t ms); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void hpm_panel_delay_us(uint32_t us); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPM_PANEL_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/cc10128007.c b/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/cc10128007.c deleted file mode 100644 index 4a38137b1d5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/cc10128007.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_panel.h" -#include "hpm_pixelmux_drv.h" -#include "hpm_lvb_drv.h" - -static void lvds_panel_lvb_init(hpm_panel_t *panel) -{ - LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base; - lvb_config_t lvb_config; - lvb_get_default_config(&lvb_config); - - lvb_config.split_mode_en = false; - lvb_config.txclk_shift = lvb_txclk_shift_1100011; - lvb_init(lvb_base, &lvb_config); - - lvb_ch_config_t lvb_ch_cfg; - lvb_ch_cfg.map = lvb_ch_mapping_vesa; - - if (panel->hw_if.video.lvds.channel_di_index == 0) - lvb_ch_cfg.data_src = lvb_ch_data_source_di0; - else - lvb_ch_cfg.data_src = lvb_ch_data_source_di1; - - if (panel->hw_if.video.lvds.channel_index == 0) { - lvb_ch_config(lvb_base, lvb_ch_num_0, &lvb_ch_cfg); - lvb_ch_enable(lvb_base, lvb_ch_num_0); - } else { - lvb_ch_config(lvb_base, lvb_ch_num_1, &lvb_ch_cfg); - lvb_ch_enable(lvb_base, lvb_ch_num_1); - } -} - -static void lvds_panel_phy_init(hpm_panel_t *panel) -{ - LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base; - lvds_phy_clk_param_t param; - uint32_t pixel_clk = panel->hw_if.lcdc_pixel_clk_khz * 1000; - pixelmux_lvds_phy_calc_pll_cfg(pixel_clk, false, ¶m); - - lvb_lvds_phy_lane_config_t lvds_lane_cfg; - lvb_lvds_phy_lane_get_default_config(&lvds_lane_cfg); - lvds_lane_cfg.fvco_div4 = param.reg.data_rate_div4; - - if (panel->hw_if.video.lvds.channel_index == 0) { - pixelmux_config_lvds_tx_phy0_clk(¶m.reg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx0, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx1, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx2, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx3, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_txck, &lvds_lane_cfg); - lvb_lvds_phy0_poweron(lvb_base); - - while (lvb_lvds_phy0_pll_is_lock(lvb_base) == false) { - } - } else { - pixelmux_config_lvds_tx_phy1_clk(¶m.reg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx0, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx1, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx2, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx3, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_txck, &lvds_lane_cfg); - lvb_lvds_phy1_poweron(lvb_base); - - while (lvb_lvds_phy1_pll_is_lock(lvb_base) == false) { - } - } -} - -static void reset(hpm_panel_t *panel) -{ - if (!panel->hw_if.set_reset_pin_level) - return; - - panel->hw_if.set_reset_pin_level(0); - hpm_panel_delay_us(2000); - - panel->hw_if.set_reset_pin_level(1); - hpm_panel_delay_us(2000); -} - -static void init(hpm_panel_t *panel) -{ - if (panel->hw_if.set_video_router) - panel->hw_if.set_video_router(); - - lvds_panel_lvb_init(panel); - lvds_panel_phy_init(panel); -} - -static void power_on(hpm_panel_t *panel) -{ - if (panel->state.power_state != HPM_PANEL_STATE_POWER_ON && - panel->hw_if.set_backlight) { - if (panel->state.backlight_percent == 0) - panel->state.backlight_percent = 100; - - panel->hw_if.set_backlight(panel->state.backlight_percent); - panel->state.power_state = HPM_PANEL_STATE_POWER_ON; - } -} - -static void power_off(hpm_panel_t *panel) -{ - if (panel->state.power_state != HPM_PANEL_STATE_POWER_OFF && - panel->hw_if.set_backlight) { - - panel->hw_if.set_backlight(0); - panel->state.power_state = HPM_PANEL_STATE_POWER_OFF; - } -} - -hpm_panel_t panel_cc10128007 = { - .name = "cc10128007", - .if_type = HPM_PANEL_IF_TYPE_LVDS_SINGLE, - .timing = { - .pixel_clock_khz = 74250, - .hactive = 800, - .hfront_porch = 60, - .hback_porch = 60, - .hsync_len = 40, - - .vactive = 1280, - .vfront_porch = 18, - .vback_porch = 18, - .vsync_len = 6, - }, - .funcs = { - .reset = reset, - .init = init, - .power_on = power_on, - .power_off = power_off, - }, -}; - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/mc10128007_31b.c b/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/mc10128007_31b.c deleted file mode 100644 index 1f9b5bf3180..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/mc10128007_31b.c +++ /dev/null @@ -1,354 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_panel.h" -#include "hpm_pixelmux_drv.h" -#include "hpm_mipi_dsi_drv.h" -#include "hpm_mipi_dsi_phy_drv.h" -#include - -typedef struct mipi_cmd_list { - uint16_t len; - uint8_t cmd[4]; -} mipi_cmd_list_t; - -static const mipi_cmd_list_t mipi_panel_cmd[] = { - {4, {0xFF, 0x98, 0x81, 0x03}}, - {2, {0x01, 0x00}}, - {2, {0x02, 0x00}}, - {2, {0x03, 0x55}}, - {2, {0x04, 0x55}}, - {2, {0x05, 0x03}}, - {2, {0x06, 0x06}}, - {2, {0x07, 0x00}}, - {2, {0x08, 0x07}}, - {2, {0x09, 0x00}}, - {2, {0x0A, 0x00}}, - {2, {0x0B, 0x00}}, - {2, {0x0C, 0x00}}, - {2, {0x0D, 0x00}}, - {2, {0x0E, 0x00}}, - {2, {0x0F, 0x00}}, - {2, {0x10, 0x00}}, - {2, {0x11, 0x00}}, - {2, {0x12, 0x00}}, - {2, {0x13, 0x00}}, - {2, {0x14, 0x00}}, - {2, {0x15, 0x00}}, - {2, {0x16, 0x00}}, - {2, {0x17, 0x00}}, - {2, {0x18, 0x00}}, - {2, {0x19, 0x00}}, - {2, {0x1A, 0x00}}, - {2, {0x1B, 0x00}}, - {2, {0x1C, 0x00}}, - {2, {0x1D, 0x00}}, - {2, {0x1E, 0xC0}}, - {2, {0x1F, 0x80}}, - {2, {0x20, 0x04}}, - {2, {0x21, 0x03}}, - {2, {0x22, 0x00}}, - {2, {0x23, 0x00}}, - {2, {0x24, 0x00}}, - {2, {0x25, 0x00}}, - {2, {0x26, 0x00}}, - {2, {0x27, 0x00}}, - {2, {0x28, 0x33}}, - {2, {0x29, 0x33}}, - {2, {0x2A, 0x00}}, - {2, {0x2B, 0x00}}, - {2, {0x2C, 0x00}}, - {2, {0x2D, 0x00}}, - {2, {0x2E, 0x00}}, - {2, {0x2F, 0x00}}, - {2, {0x30, 0x00}}, - {2, {0x31, 0x00}}, - {2, {0x32, 0x00}}, - {2, {0x33, 0x00}}, - {2, {0x34, 0x04}}, - {2, {0x35, 0x00}}, - {2, {0x36, 0x00}}, - {2, {0x37, 0x00}}, - {2, {0x38, 0x3C}}, - {2, {0x39, 0x00}}, - {2, {0x3A, 0x00}}, - {2, {0x3B, 0x00}}, - {2, {0x3C, 0x00}}, - {2, {0x3D, 0x00}}, - {2, {0x3E, 0x00}}, - {2, {0x3F, 0x00}}, - {2, {0x40, 0x00}}, - {2, {0x41, 0x00}}, - {2, {0x42, 0x00}}, - {2, {0x43, 0x00}}, - {2, {0x44, 0x00}}, - {2, {0x50, 0x00}}, - {2, {0x51, 0x11}}, - {2, {0x52, 0x44}}, - {2, {0x53, 0x55}}, - {2, {0x54, 0x88}}, - {2, {0x55, 0xAB}}, - {2, {0x56, 0x00}}, - {2, {0x57, 0x11}}, - {2, {0x58, 0x22}}, - {2, {0x59, 0x33}}, - {2, {0x5A, 0x44}}, - {2, {0x5B, 0x55}}, - {2, {0x5C, 0x66}}, - {2, {0x5D, 0x77}}, - {2, {0x5E, 0x00}}, - {2, {0x5F, 0x02}}, - {2, {0x60, 0x02}}, - {2, {0x61, 0x0A}}, - {2, {0x62, 0x09}}, - {2, {0x63, 0x08}}, - {2, {0x64, 0x13}}, - {2, {0x65, 0x12}}, - {2, {0x66, 0x11}}, - {2, {0x67, 0x10}}, - {2, {0x68, 0x0F}}, - {2, {0x69, 0x0E}}, - {2, {0x6A, 0x0D}}, - {2, {0x6B, 0x0C}}, - {2, {0x6C, 0x06}}, - {2, {0x6D, 0x07}}, - {2, {0x6E, 0x02}}, - {2, {0x6F, 0x02}}, - {2, {0x70, 0x02}}, - {2, {0x71, 0x02}}, - {2, {0x72, 0x02}}, - {2, {0x73, 0x02}}, - {2, {0x74, 0x02}}, - {2, {0x75, 0x02}}, - {2, {0x76, 0x02}}, - {2, {0x77, 0x0A}}, - {2, {0x78, 0x06}}, - {2, {0x79, 0x07}}, - {2, {0x7A, 0x10}}, - {2, {0x7B, 0x11}}, - {2, {0x7C, 0x12}}, - {2, {0x7D, 0x13}}, - {2, {0x7E, 0x0C}}, - {2, {0x7F, 0x0D}}, - {2, {0x80, 0x0E}}, - {2, {0x81, 0x0F}}, - {2, {0x82, 0x09}}, - {2, {0x83, 0x08}}, - {2, {0x84, 0x02}}, - {2, {0x85, 0x02}}, - {2, {0x86, 0x02}}, - {2, {0x87, 0x02}}, - {2, {0x88, 0x02}}, - {2, {0x89, 0x02}}, - {2, {0x8A, 0x02}}, - {4, {0xFF, 0x98, 0x81, 0x04}}, - {2, {0x6E, 0x2A}}, - {2, {0x6F, 0x37}}, - {2, {0x3A, 0x24}}, - {2, {0x8D, 0x19}}, - {2, {0x87, 0xBA}}, - {2, {0xB2, 0xD1}}, - {2, {0x88, 0x0B}}, - {2, {0x38, 0x01}}, - {2, {0x39, 0x00}}, - {2, {0xB5, 0x02}}, - {2, {0x31, 0x25}}, - {2, {0x3B, 0x98}}, - {4, {0xFF, 0x98, 0x81, 0x01}}, - {2, {0x22, 0x0A}}, - {2, {0x31, 0x0C}}, - {2, {0x53, 0x40}}, - {2, {0x55, 0x45}}, - {2, {0x50, 0xB7}}, - {2, {0x51, 0xB2}}, - {2, {0x60, 0x07}}, - {2, {0xA0, 0x22}}, - {2, {0xA1, 0x3F}}, - {2, {0xA2, 0x4E}}, - {2, {0xA3, 0x17}}, - {2, {0xA4, 0x1A}}, - {2, {0xA5, 0x2D}}, - {2, {0xA6, 0x21}}, - {2, {0xA7, 0x22}}, - {2, {0xA8, 0xC4}}, - {2, {0xA9, 0x1B}}, - {2, {0xAA, 0x25}}, - {2, {0xAB, 0xA7}}, - {2, {0xAC, 0x1A}}, - {2, {0xAD, 0x19}}, - {2, {0xAE, 0x4B}}, - {2, {0xAF, 0x1F}}, - {2, {0xB0, 0x2A}}, - {2, {0xB1, 0x59}}, - {2, {0xB2, 0x64}}, - {2, {0xB3, 0x3F}}, - {2, {0xC0, 0x22}}, - {2, {0xC1, 0x48}}, - {2, {0xC2, 0x59}}, - {2, {0xC3, 0x15}}, - {2, {0xC4, 0x15}}, - {2, {0xC5, 0x28}}, - {2, {0xC6, 0x1C}}, - {2, {0xC7, 0x1E}}, - {2, {0xC8, 0xC4}}, - {2, {0xC9, 0x1C}}, - {2, {0xCA, 0x2B}}, - {2, {0xCB, 0xA3}}, - {2, {0xCC, 0x1F}}, - {2, {0xCD, 0x1E}}, - {2, {0xCE, 0x52}}, - {2, {0xCF, 0x24}}, - {2, {0xD0, 0x2A}}, - {2, {0xD1, 0x58}}, - {2, {0xD2, 0x68}}, - {2, {0xD3, 0x3F}}, - {4, {0xFF, 0x98, 0x81, 0x00}}, - {1, {0x11}}, - {1, {0x29}}, -}; - -static void mipi_panel_init_cmd_send(hpm_panel_t *panel) -{ - int ret; - uint8_t page_cmd[4] = {0xFF, 0x98, 0x81, 0x01}; - uint8_t panel_id[2] = {0x98, 0x81}; - uint8_t rdata; - MIPI_DSI_Type *mipi_host = panel->hw_if.video.mipi.mipi_host_base; - - mipi_dsi_dcs_write_buffer(mipi_host, 0, page_cmd, 4); - - for (int i = 0; i < 2; i++) { - mipi_dsi_set_maximum_return_packet_size(mipi_host, 0, 1); - ret = mipi_dsi_dcs_read(mipi_host, 0, i, &rdata, 1); - if (ret <= 0 || rdata != panel_id[i]) { - printf("read id[%d]: 0x%02X -- failed\n", i, rdata); - while (1) { - } - } else { - printf("read id[%d]: 0x%02X -- ok\n", i, rdata); - } - hpm_panel_delay_ms(10); - } - - int mipi_cmd_num = sizeof(mipi_panel_cmd) / sizeof(mipi_panel_cmd[0]); - for (int i = 0; i < mipi_cmd_num; i++) { - ret = mipi_dsi_dcs_write_buffer(mipi_host, 0, mipi_panel_cmd[i].cmd, mipi_panel_cmd[i].len); - if (ret <= 0) - printf("mipi_cmd[%d].cmd: 0x%02X -- failed\n", i, mipi_panel_cmd[i].cmd[0]); - } - - hpm_panel_delay_ms(10); -} - -static void mipi_panel_host_init(hpm_panel_t *panel) -{ - MIPI_DSI_Type *mipi_host = panel->hw_if.video.mipi.mipi_host_base; - const hpm_panel_timing_t *timing = &panel->timing; - mipi_dsi_config_t mipi_cfg; - mipi_dsi_get_defconfig_on_video(&mipi_cfg); - - mipi_cfg.channel = 0; - mipi_cfg.lanes = 4; - mipi_cfg.video_para.pixel_clock_khz = panel->hw_if.lcdc_pixel_clk_khz; - mipi_cfg.video_para.hactive = timing->hactive; - mipi_cfg.video_para.hsync_len = timing->hsync_len; - mipi_cfg.video_para.hback_porch = timing->hback_porch; - mipi_cfg.video_para.hfront_porch = timing->hfront_porch; - mipi_cfg.video_para.vsync_len = timing->vsync_len; - mipi_cfg.video_para.vactive = timing->vactive; - mipi_cfg.video_para.vback_porch = timing->vback_porch; - mipi_cfg.video_para.vfront_porch = timing->vfront_porch; - - mipi_dsi_init(mipi_host, &mipi_cfg); -} - -static void mipi_panel_phy_init(hpm_panel_t *panel) -{ - MIPI_DSI_Type *mipi_host = panel->hw_if.video.mipi.mipi_host_base; - MIPI_DSI_PHY_Type *mipi_phy = panel->hw_if.video.mipi.mipi_phy_base; - - mipi_dsi_phy_config_t mipi_phy_cfg = { - .lanes = 4, - .lane_mbps = 500 - }; - mipi_dsi_phy_powerdown(mipi_host); - mipi_dsi_phy_init(mipi_phy, &mipi_phy_cfg); - mipi_dsi_phy_poweron(mipi_host); -} - -static void reset(hpm_panel_t *panel) -{ - if (!panel->hw_if.set_reset_pin_level) - return; - - panel->hw_if.set_reset_pin_level(0); - hpm_panel_delay_ms(20); - - panel->hw_if.set_reset_pin_level(1); - hpm_panel_delay_ms(15); -} - -static void init(hpm_panel_t *panel) -{ - if (panel->hw_if.set_video_router) - panel->hw_if.set_video_router(); - - mipi_panel_host_init(panel); - mipi_panel_phy_init(panel); - mipi_panel_init_cmd_send(panel); -} - -static void power_on(hpm_panel_t *panel) -{ - MIPI_DSI_Type *mipi_host = panel->hw_if.video.mipi.mipi_host_base; - - if (panel->state.power_state != HPM_PANEL_STATE_POWER_ON) { - mipi_dsi_video_mode_hs_transfer_enable(mipi_host); - - if (panel->hw_if.set_backlight) { - if (panel->state.backlight_percent == 0) - panel->state.backlight_percent = 100; - panel->hw_if.set_backlight(panel->state.backlight_percent); - } - panel->state.power_state = HPM_PANEL_STATE_POWER_ON; - } -} - -static void power_off(hpm_panel_t *panel) -{ - MIPI_DSI_Type *mipi_host = panel->hw_if.video.mipi.mipi_host_base; - - if (panel->state.power_state != HPM_PANEL_STATE_POWER_OFF) { - if (panel->hw_if.set_backlight) - panel->hw_if.set_backlight(0); - mipi_dsi_video_mode_hs_transfer_disable(mipi_host); - panel->state.power_state = HPM_PANEL_STATE_POWER_OFF; - } -} - -hpm_panel_t panel_mc10128007_31b = { - .name = "mc10128007_31b", - .if_type = HPM_PANEL_IF_TYPE_MIPI, - .timing = { - .pixel_clock_khz = 60000, - .hactive = 800, - .hfront_porch = 52, - .hback_porch = 48, - .hsync_len = 8, - - .vactive = 1280, - .vfront_porch = 15, - .vback_porch = 16, - .vsync_len = 6, - }, - .funcs = { - .reset = reset, - .init = init, - .power_on = power_on, - .power_off = power_off, - }, -}; - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm070rdh13.c b/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm070rdh13.c deleted file mode 100644 index 6734234663c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm070rdh13.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_panel.h" - -static void reset(hpm_panel_t *panel) -{ - if (!panel->hw_if.set_reset_pin_level) - return; - - panel->hw_if.set_reset_pin_level(0); - hpm_panel_delay_ms(20); - - panel->hw_if.set_reset_pin_level(1); - hpm_panel_delay_ms(20); -} - -static void init(hpm_panel_t *panel) -{ - if (panel->hw_if.set_video_router) - panel->hw_if.set_video_router(); -} - -static void power_on(hpm_panel_t *panel) -{ - if (panel->state.power_state != HPM_PANEL_STATE_POWER_ON && - panel->hw_if.set_backlight) { - if (panel->state.backlight_percent == 0) - panel->state.backlight_percent = 100; - - panel->hw_if.set_backlight(panel->state.backlight_percent); - panel->state.power_state = HPM_PANEL_STATE_POWER_ON; - } -} - -static void power_off(hpm_panel_t *panel) -{ - if (panel->state.power_state != HPM_PANEL_STATE_POWER_OFF && - panel->hw_if.set_backlight) { - - panel->hw_if.set_backlight(0); - panel->state.power_state = HPM_PANEL_STATE_POWER_OFF; - } -} - -hpm_panel_t panel_tm070rdh13 = { - .name = "tm070rdh13", - .if_type = HPM_PANEL_IF_TYPE_RGB, - .timing = { - .pixel_clock_khz = 60000, - .hactive = 800, - .hfront_porch = 50, - .hback_porch = 36, - .hsync_len = 10, - .hsync_pol = 1, - - .vactive = 480, - .vfront_porch = 10, - .vback_porch = 20, - .vsync_len = 3, - .vsync_pol = 1, - }, - .funcs = { - .reset = reset, - .init = init, - .power_on = power_on, - .power_off = power_off, - }, -}; - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm103xdgp01.c b/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm103xdgp01.c deleted file mode 100644 index 934f92ccf19..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm103xdgp01.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_panel.h" -#include "hpm_pixelmux_drv.h" -#include "hpm_lvb_drv.h" - -static void lvds_panel_lvb_init(hpm_panel_t *panel) -{ - LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base; - lvb_config_t lvb_config; - lvb_get_default_config(&lvb_config); - - lvb_config.split_mode_en = true; - lvb_config.txclk_shift = lvb_txclk_shift_1100011; - lvb_init(lvb_base, &lvb_config); - - lvb_ch_config_t lvb_ch_cfg; - lvb_ch_cfg.map = lvb_ch_mapping_vesa; - - if (panel->hw_if.video.lvds.channel_di_index == 0) - lvb_ch_cfg.data_src = lvb_ch_data_source_di0; - else - lvb_ch_cfg.data_src = lvb_ch_data_source_di1; - - lvb_ch_config(lvb_base, lvb_ch_num_0, &lvb_ch_cfg); - lvb_ch_config(lvb_base, lvb_ch_num_1, &lvb_ch_cfg); - - lvb_ch_enable(lvb_base, lvb_ch_num_0); - lvb_ch_enable(lvb_base, lvb_ch_num_1); -} - -static void lvds_panel_phy_init(hpm_panel_t *panel) -{ - LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base; - lvds_phy_clk_param_t param; - uint32_t pixel_clk = panel->hw_if.lcdc_pixel_clk_khz * 1000; - pixelmux_lvds_phy_calc_pll_cfg(pixel_clk, true, ¶m); - pixelmux_config_lvds_tx_phy0_clk(¶m.reg); - pixelmux_config_lvds_tx_phy1_clk(¶m.reg); - - lvb_lvds_phy_lane_config_t lvds_lane_cfg; - lvb_lvds_phy_lane_get_default_config(&lvds_lane_cfg); - lvds_lane_cfg.fvco_div4 = param.reg.data_rate_div4; - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx0, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx1, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx2, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx3, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_txck, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx0, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx1, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx2, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx3, &lvds_lane_cfg); - lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_txck, &lvds_lane_cfg); - - lvb_lvds_phy0_poweron(lvb_base); - lvb_lvds_phy1_poweron(lvb_base); - - while (lvb_lvds_phy_split_pll_is_lock(lvb_base) == false) { - } -} - -static void reset(hpm_panel_t *panel) -{ - if (!panel->hw_if.set_reset_pin_level) - return; - - panel->hw_if.set_reset_pin_level(0); - hpm_panel_delay_us(2000); - - panel->hw_if.set_reset_pin_level(1); - hpm_panel_delay_us(2000); -} - -static void init(hpm_panel_t *panel) -{ - if (panel->hw_if.set_video_router) - panel->hw_if.set_video_router(); - - lvds_panel_lvb_init(panel); - lvds_panel_phy_init(panel); -} - -hpm_panel_t panel_tm103xdgp01 = { - .name = "tm103xdgp01", - .if_type = HPM_PANEL_IF_TYPE_LVDS_SPLIT, - .timing = { - .pixel_clock_khz = 45000, - .hactive = 1920, - .hfront_porch = 32, - .hback_porch = 32, - .hsync_len = 64, - - .vactive = 720, - .vfront_porch = 2, - .vback_porch = 2, - .vsync_len = 4, - }, - .funcs = { - .reset = reset, - .init = init, - }, -}; - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.c b/bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.c deleted file mode 100644 index 1449eaa9e3d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.c +++ /dev/null @@ -1,271 +0,0 @@ - -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Include - *--------------------------------------------------------------------- - */ -#include "hpm_ppi.h" -#include "hpm_clock_drv.h" - -static uint32_t ppi_ns2cycle(uint32_t ns) -{ - uint32_t ppi_freq = clock_get_frequency(clock_ppi0); - uint32_t max_cycle = PPI_CMD_CMD_CFG_CYCLE_NUM_MASK >> PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT; - uint32_t ns_per_cycle; - uint32_t cycle; - - ns_per_cycle = 1000000000 / ppi_freq; - cycle = ns / ns_per_cycle; - if (cycle > max_cycle) { - cycle = max_cycle; - } - - return cycle; -} - -/* API */ -void ppi_config_async_sram(PPI_Type *ppi, uint8_t cs_index, uint8_t cmd_start_index, ppi_async_sram_config_t *config) -{ - ppi_cs_pin_config_t cs_config; - ppi_cmd_config_t cmd_config; - - assert(!config->ad_mux_mode && (config->port_size != ppi_port_size_32bits)); - assert(((config->base_address & 0xFFFFF) == 0) && (config->size_in_byte > 0)); /* Addr should be aligned by 1MB */ - - /* - * Pin polarity Config - */ - if (config->cs_valid_polarity) { - ppi_config_cs_pin_polarity(ppi, cs_index, ppi_cs_idle_pol_low); - } else { - ppi_config_cs_pin_polarity(ppi, cs_index, ppi_cs_idle_pol_high); - } - - if (config->ad_mux_mode) { - ppi_set_ctrl_pin_dir(ppi, config->adv_ctrl_pin, ppi_ctrl_pin_dir_output); - ppi_config_ctrl_pin_polarity(ppi, config->adv_ctrl_pin, ppi_ctrl_pol_low); - } - ppi_set_ctrl_pin_dir(ppi, config->rel_ctrl_pin, ppi_ctrl_pin_dir_output); - ppi_config_ctrl_pin_polarity(ppi, config->rel_ctrl_pin, ppi_ctrl_pol_low); - ppi_set_ctrl_pin_dir(ppi, config->wel_ctrl_pin, ppi_ctrl_pin_dir_output); - ppi_config_ctrl_pin_polarity(ppi, config->wel_ctrl_pin, ppi_ctrl_pol_low); - - /* - * Read Cmd - */ - /* common */ - cmd_config.cs_pin_value = config->cs_valid_polarity; - cmd_config.clk_output = false; - if (config->ad_mux_mode) { - cmd_config.byte_sel[0] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[1] = ppi_byte_sel_8_15_bits; - cmd_config.byte_sel[2] = ppi_byte_sel_16_23_bits; - cmd_config.byte_sel[3] = ppi_byte_sel_24_31_bits; - } else { - if (config->port_size == ppi_port_size_8bits) { - cmd_config.ad_func_sel[0] = ppi_ad_func_data; - cmd_config.ad_pin_dir[0] = ppi_ad_pin_dir_input; - cmd_config.byte_sel[0] = ppi_byte_sel_0_7_bits; - for (uint8_t i = 1; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.byte_sel[1] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[2] = ppi_byte_sel_8_15_bits; - cmd_config.byte_sel[3] = ppi_byte_sel_16_23_bits; - } else if (config->port_size == ppi_port_size_16bits) { - for (uint8_t i = 0; i < 2; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_data; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_input; - } - cmd_config.byte_sel[0] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[1] = ppi_byte_sel_8_15_bits; - for (uint8_t i = 2; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.byte_sel[2] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[3] = ppi_byte_sel_8_15_bits; - } else { - ; /* Not Support */ - } - } - cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; - - /* AS Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->as_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; - ppi_config_cmd(ppi, cmd_start_index, &cmd_config); - - /* AH Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->ah_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = !config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; - ppi_config_cmd(ppi, cmd_start_index + 1, &cmd_config); - - /* REL Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->rel_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_data; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_input; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = !config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = false; - ppi_config_cmd(ppi, cmd_start_index + 2, &cmd_config); - - /* REH Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->reh_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_data; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_input; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = !config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; - ppi_config_cmd(ppi, cmd_start_index + 3, &cmd_config); - - /* - * Write Cmd - */ - /* common */ - cmd_config.cs_pin_value = config->cs_valid_polarity; - cmd_config.clk_output = false; - if (config->ad_mux_mode) { - cmd_config.byte_sel[0] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[1] = ppi_byte_sel_8_15_bits; - cmd_config.byte_sel[2] = ppi_byte_sel_16_23_bits; - cmd_config.byte_sel[3] = ppi_byte_sel_24_31_bits; - } else { - if (config->port_size == ppi_port_size_8bits) { - cmd_config.ad_func_sel[0] = ppi_ad_func_data; - cmd_config.ad_pin_dir[0] = ppi_ad_pin_dir_output; - cmd_config.byte_sel[0] = ppi_byte_sel_0_7_bits; - for (uint8_t i = 1; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.byte_sel[1] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[2] = ppi_byte_sel_8_15_bits; - cmd_config.byte_sel[3] = ppi_byte_sel_16_23_bits; - } else if (config->port_size == ppi_port_size_16bits) { - for (uint8_t i = 0; i < 2; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_data; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.byte_sel[0] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[1] = ppi_byte_sel_8_15_bits; - for (uint8_t i = 2; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.byte_sel[2] = ppi_byte_sel_0_7_bits; - cmd_config.byte_sel[3] = ppi_byte_sel_8_15_bits; - } else { - ; /* Not Support */ - } - } - cmd_config.ctrl_pin_value[config->rel_ctrl_pin] = true; - - /* AS Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->as_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; - ppi_config_cmd(ppi, cmd_start_index + 4, &cmd_config); - - /* AH Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->ah_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_addr; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = !config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; - ppi_config_cmd(ppi, cmd_start_index + 5, &cmd_config); - - /* WEL Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->wel_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_data; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = !config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = false; - ppi_config_cmd(ppi, cmd_start_index + 6, &cmd_config); - - /* WEH Stage */ - cmd_config.cmd_cycle = ppi_ns2cycle(config->weh_in_ns); - if (config->ad_mux_mode) { - for (uint8_t i = 0; i < 4; i++) { - cmd_config.ad_func_sel[i] = ppi_ad_func_data; - cmd_config.ad_pin_dir[i] = ppi_ad_pin_dir_output; - } - cmd_config.ctrl_pin_value[config->adv_ctrl_pin] = !config->addr_valid_polarity; - } - cmd_config.ctrl_pin_value[config->wel_ctrl_pin] = true; - ppi_config_cmd(ppi, cmd_start_index + 7, &cmd_config); - - /* - * CS Config - */ - cs_config.addr_start_high_12bits = (config->base_address & 0xFFF00000u) >> 20u; - cs_config.addr_end_high_12bits = ((config->base_address + (config->size_in_byte - 1u)) & 0xFFF00000u) >> 20u; - cs_config.port_size = config->port_size; - cs_config.addr_mask = 0xFFFFu; - cs_config.sync_clk_en = false; - cs_config.sync_clk_sel = 0; - cs_config.interval_cycle = 2; - cs_config.rcmd_start0 = cmd_start_index; - cs_config.rcmd_end0 = cmd_start_index + 3; - cs_config.rcmd_start1 = cmd_start_index; - cs_config.rcmd_end1 = cmd_start_index + 3; - cs_config.wcmd_start0 = cmd_start_index + 4; - cs_config.wcmd_end0 = cmd_start_index + 7; - cs_config.wcmd_start1 = cmd_start_index + 4; - cs_config.wcmd_end1 = cmd_start_index + 7; -#if defined(HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS) && HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS - if (config->dm_valid_polarity) { - cs_config.dm_polarity = ppi_dm_valid_pol_high; - } else { - cs_config.dm_polarity = ppi_dm_valid_pol_low; - } -#else - if (config->dm_valid_polarity) { - ppi_config_dm_pin_polarity(ppi, cs_index, ppi_dm_valid_pol_high); - } else { - ppi_config_dm_pin_polarity(ppi, cs_index, ppi_dm_valid_pol_low); - } -#endif - ppi_config_cs_pin(ppi, cs_index, &cs_config); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.h b/bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.h deleted file mode 100644 index cf0eb3416fb..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_PPI_H -#define _HPM_PPI_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_ppi_drv.h" - -/** - * @brief ppi async sram config structure - * - */ -typedef struct { - uint32_t base_address; /**< external SRAM base address, should be 1MB aligned */ - uint32_t size_in_byte; /**< external SRAM size in byte */ - ppi_port_size_t port_size; /**< port size */ - bool ad_mux_mode; /**< addr and data mux mode */ - bool cs_valid_polarity; /**< cs valid polarity */ - bool dm_valid_polarity; /**< dm valid polarity */ - bool addr_valid_polarity; /**< addr valid polarity */ - uint8_t adv_ctrl_pin; /**< adv ctrl pin number, 0 - 7 */ - uint8_t rel_ctrl_pin; /**< rel ctrl pin number, 0 - 7 */ - uint8_t wel_ctrl_pin; /**< wel ctrl pin number, 0 - 7 */ - uint8_t as_in_ns; /**< address setup time */ - uint8_t ah_in_ns; /**< address hold time */ - uint8_t rel_in_ns; /**< RE low time */ - uint8_t reh_in_ns; /**< RE high time */ - uint8_t wel_in_ns; /**< WE low time */ - uint8_t weh_in_ns; /**< WE high time */ -} ppi_async_sram_config_t; - - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief config async sram - * - * @param[in] ppi PPI base address - * @param[in] cs_index cs index, value: 0 - 3 - * @param[in] cmd_index cmd start index - * @param[in] config async sram config structure pointer, @ref ppi_async_sram_config_t - */ -void ppi_config_async_sram(PPI_Type *ppi, uint8_t cs_index, uint8_t cmd_start_index, ppi_async_sram_config_t *config); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* _HPM_PPI_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c b/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c deleted file mode 100644 index 3c011648891..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sccb.h" - -hpm_stat_t sccb_master_init(sccb_type sccb) -{ - /*TODO*/ - return status_success; -} - -uint8_t sccb_master_scan(sccb_type sccb) -{ - for (uint8_t addr = 0x01, rxdata; addr < 0xff; addr++) { - if (i2c_master_read(sccb, addr, &rxdata, 1) == status_success) { - return addr; - } - } - return 0; -} - -hpm_stat_t sccb_master_gencall(sccb_type sccb, uint8_t cmd) -{ - uint8_t reg_data = 0; - return i2c_master_address_write(sccb, 0x00, &cmd, 1, ®_data, 1); -} - -hpm_stat_t sccb_master_readb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t *reg_data) -{ - return i2c_master_address_read(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, 1, reg_data, 1); -} - -hpm_stat_t sccb_master_writeb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t reg_data) -{ - return i2c_master_address_write(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, 1, (uint8_t *)®_data, 1); -} - -hpm_stat_t sccb_master_readb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t *reg_data) -{ - uint8_t r[2]; - r[0] = reg_addr >> 8; - r[1] = reg_addr & 0xFF; - return i2c_master_address_read(sccb, (uint16_t)slv_addr, r, sizeof(r), reg_data, 1); -} - -hpm_stat_t sccb_master_writeb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t reg_data) -{ - int ret = 0; - uint8_t r[2]; - r[0] = reg_addr >> 8; - r[1] = reg_addr & 0xFF; - return i2c_master_address_write(sccb, (uint16_t)slv_addr, r, sizeof(r), (uint8_t *)®_data, 1); -} - -hpm_stat_t sccb_master_readw(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t *reg_data) -{ - hpm_stat_t ret = status_success; - ret = i2c_master_address_read(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, - 1, (uint8_t *)reg_data, 2); - if (ret == status_success) { - *reg_data = (*reg_data >> 8) | (*reg_data << 8); - } - return ret; -} - -hpm_stat_t sccb_master_writew(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t reg_data) -{ - reg_data = (reg_data >> 8) | (reg_data << 8); - return i2c_master_address_write(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, 1, (uint8_t *)®_data, 2); -} - -hpm_stat_t sccb_master_readw2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t *reg_data) -{ - hpm_stat_t ret = status_success; - ret = i2c_master_address_read(sccb, (uint16_t)slv_addr, (uint8_t *)®_addr, - 2, (uint8_t *)reg_data, 2); - if (ret == status_success) { - *reg_data = (*reg_data >> 8) | (*reg_data << 8); - } - return ret; -} - -hpm_stat_t sccb_master_writew2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t reg_data) -{ - int ret = 0; - reg_data = (reg_data >> 8) | (reg_data << 8); - return i2c_master_address_write(sccb, (uint16_t)slv_addr, - (uint8_t *)®_addr, 2, - (uint8_t *)®_data, 2); -} - -hpm_stat_t sccb_master_read_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags) -{ - return i2c_master_read(sccb, (uint16_t)slv_addr, buf, len); -} - -hpm_stat_t cambus_write_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags) -{ - int ret = 0; - hpm_stat_t sta = status_success; - int _len = len; - int remain = 0; - int offset = 0; - while (_len > 0) { - remain = (_len > 100) ? 100 : _len; - sta = i2c_master_write(sccb, (uint16_t)slv_addr, &buf[offset], remain); - if (sta != status_success) { - return status_fail; - } - offset += remain; - _len -= remain; - } - return sta; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h b/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h deleted file mode 100644 index 888c6b3e0ad..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/sccb/hpm_sccb.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SCCB_H -#define HPM_SCCB_H - -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_i2c_drv.h" - -typedef I2C_Type *sccb_type; - -typedef enum _sccb_xfer_flag { - /*Normal transfer with start condition, address, data and stop condition.*/ - sccb_xfer_no_flags, - /*This flag allows the next transfer to change direction with repeated start*/ - sccb_xfer_no_stop, - /*This flag allows chaining multiple writes or reads with the same direction*/ - sccb_xfer_suspend, -} sccb_xfer_flags_t; - -typedef struct _sccb_bus { - uint8_t initialzed; - sccb_type sccb; -} hpm_sccb_bus_t; - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** - * @brief sccb master initialization - * - * @details Initialized sccb working at master mode - * - * @param [in] sccb sccb base address - * @retval hpm_stat_t: status_success if initialization is completed without any error - */ -hpm_stat_t sccb_master_init(sccb_type sccb); - -/** - * @brief sccb master scan slave addr - * - * @details master scan the slave - * - * @param [in] sccb sccb base address - * @retval uint8_t: the slave address val is zero if scan slave fail - */ -uint8_t sccb_master_scan(sccb_type sccb); - -/** - * @brief sccb master gen call slave - * - * @details the controller sends the command to determine whether the slave responds - * - * @param [in] sccb sccb base address - * @param [in] cmd sccb master sends command - * @retval hpm_stat_t: status_success if the slave responds - */ -hpm_stat_t sccb_master_gencall(sccb_type sccb, uint8_t cmd); - -/** - * @brief sccb master read 8bit data of specify 8bit register from certain slave device - * - * @details the function used to access 8 bit register address,read 8bit data - * @note the register address must be 8bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 8bit register address of sccb slave device - * @param [out] reg_data point of the buffer to store 8bit data from device the number of bytes is 1 - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t sccb_master_readb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t *reg_data); - -/** - * @brief sccb master write 8bit data of specify 8bit register from certain slave device - * - * @details the function used to access 8 bit register address,write 8bit data - * @note the register address must be 8bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 8bit register address of sccb slave device - * @param [out] reg_data write 8bit data - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t sccb_master_writeb(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint8_t reg_data); - -/** - * @brief sccb master read 8bit data of specify 16bit register from certain slave device - * - * @details the function used to access 16 bit register address,read 8bit data - * @note the register address must be 16bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 16bit register address of sccb slave device - * @param [out] reg_data point of the buffer to store 8bit data from device the number of bytes is 1 - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t sccb_master_readb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t *reg_data); - -/** - * @brief sccb master write 8bit data of specify 16bit register from certain slave device - * - * @details the function used to access 16 bit register address,write 8bit data - * @note the register address must be 8bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 16bit register address of sccb slave device - * @param [out] reg_data wirite 8bit data - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t sccb_master_writeb2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint8_t reg_data); - -/** - * @brief sccb master read 16bit data of specify 8bit register from certain slave device - * - * @details the function used to access 8 bit register address,read 16bit data - * @note the register address must be 8bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 8bit register address of sccb slave device - * @param [out] reg_data point of the buffer to store 16bit data from device the number of bytes is 1 - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t sccb_master_readw(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t *reg_data); - -/** - * @brief sccb master write 16bit data of specify 8bit register from certain slave device - * - * @details the function used to access 8 bit register address,write 16bit data - * @note the register address must be 8bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 8bit register address of sccb slave device - * @param [out] reg_data wirite 16bit data - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t sccb_master_writew(sccb_type sccb, uint8_t slv_addr, uint8_t reg_addr, uint16_t reg_data); - -/** - * @brief sccb master read 16bit data of specify 16it register from certain slave device - * - * @details the function used to access 16 bit register address,read 16bit data - * @note the register address must be 16bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 16bit register address of sccb slave device - * @param [out] reg_data point of the buffer to store 16bit data from device the number of bytes is 1 - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t sccb_master_readw2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t *reg_data); - -/** - * @brief sccb master write 16bit data of specify 16bit register from certain slave device - * - * @details the function used to access 16bit register address,write 16bit data - * @note the register address must be 16bit - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] reg_addr 16bit register address of sccb slave device - * @param [out] reg_data wirite 16bit data - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t sccb_master_writew2(sccb_type sccb, uint8_t slv_addr, uint16_t reg_addr, uint16_t reg_data); - -/** - * @brief sccb master reads the specified number of bytes continuously at the specified flag - * - * @details the size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] buf point of the buffer to store 8bit data from device - * @param [out] len size of data to be read in bytes - * @param [in] len size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t sccb_master_read_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags); - -/** - * @brief sccb master weite the specified number of bytes continuously at the specified flag - * - * @details the size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] sccb sccb base address - * @param [in] slv_addr sccb slave address - * @param [out] buf point of the buffer to store 8bit data from device - * @param [out] len size of data to be write in bytes - * @param [in] len size of data to be write in bytes - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t cambus_write_bytes(sccb_type sccb, uint8_t slv_addr, uint8_t *buf, const uint32_t len, uint8_t flags); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c deleted file mode 100644 index 014aec1dcfd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.c +++ /dev/null @@ -1,1170 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_serial_nor.h" -#include "hpm_clock_drv.h" - -#ifndef SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B -#define SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B (0x32U) -#endif - -#ifndef SERIALNOR_CMD_READ_SDR_1_2_2_4B -#define SERIALNOR_CMD_READ_SDR_1_2_2_4B (0xBCU) -#endif - -#ifndef SERIALNOR_CMD_READ_SDR_1_2_2_3B -#define SERIALNOR_CMD_READ_SDR_1_2_2_3B (0xBBU) -#endif - -#ifndef SERIALNOR_CMD_READ_SDR_1_1_2_3B -#define SERIALNOR_CMD_READ_SDR_1_1_2_3B (0x3BU) -#endif - -#ifndef SERIALNOR_CMD_READ_SDR_1_1_2_4B -#define SERIALNOR_CMD_READ_SDR_1_1_2_4B (0x3CU) -#endif - -#ifndef SERIALNOR_CMD_WRITE_STATUS_REG3 -#define SERIALNOR_CMD_WRITE_STATUS_REG3 (0x11U) -#endif - -#ifndef SERIALNOR_CMD_READ_STATUS_REG3 -#define SERIALNOR_CMD_READ_STATUS_REG3 (0x15U) -#endif - -#ifndef kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31 -#define kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31 (0x31U) -#endif - - -#ifndef kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31 -#define kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31 (0x35U) -#endif - - -#define MAX_24BIT_ADDRESSING_SIZE ((1UL << 24)) -#define MAX_24BIT_ADDR_SIZE_IN_KBYTES ((1UL << 24) / SIZE_1KB) - -#define SPI_READ_SFDP_FREQUENCY (10000000U) - -/** - * @brief QE bit enable sequence option - */ -typedef enum { - spi_nor_quad_en_auto_or_ignore = 0U, /**< Auto enable or ignore */ - spi_nor_quad_en_set_bit6_in_status_reg1 = 1U, /**< QE bit is at bit6 in Status register 1 */ - spi_nor_quad_en_set_bit1_in_status_reg2 = 2U, /**< QE bit is at bit1 in Status register 2 register 2 */ - spi_nor_quad_en_set_bit7_in_status_reg2 = 3U, /**< QE bit is at bit7 in Status register 2 */ - spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U, /**< QE bit is in status register 2 and configured by CMD 0x31 */ -} spi_nor_quad_enable_seq_t; - -static hpm_stat_t hpm_serial_nor_read_sfdp_info(hpm_serial_nor_t *flash, jedec_info_table_t *tbl, bool address_shift_enable); -static hpm_stat_t hpm_spi_get_read_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); -static hpm_stat_t hpm_spi_get_program_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); -static hpm_stat_t hpm_spi_nor_read_sfdp(hpm_serial_nor_t *flash, uint32_t addr, - uint32_t *buffer, uint32_t bytes); -static hpm_stat_t hpm_spi_nor_set_command(hpm_serial_nor_t *flash, uint8_t cmd); -static hpm_stat_t get_page_sector_block_size_from_sfdp(hpm_serial_nor_info_t *config, jedec_info_table_t *tbl); -static hpm_stat_t hpm_spi_nor_read_status_register(hpm_serial_nor_t *flash, uint8_t *reg_data, uint8_t status_reg); -static hpm_stat_t hpm_spi_nor_write_status_register(hpm_serial_nor_t *flash, uint8_t reg_data, uint8_t status_reg); -static hpm_stat_t prepare_quad_mode_enable_sequence(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info); - -__attribute__((weak)) void hpm_spi_nor_udelay(uint32_t us) -{ - clock_cpu_delay_us(us); -} - -static hpm_stat_t hpm_spi_get_read_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) -{ - uint32_t address_bits; - uint32_t dummy_cycles = 0; - uint8_t mode_cycles = 0; - uint8_t dummy_count = 0; - jedec_flash_param_table_t *param_tbl = &jedec_info->flash_param_tbl; - jedec_4byte_addressing_inst_table_t *flash_4b_tbl = &jedec_info->flash_4b_inst_tbl; - flash->nor_read_para.data_phase_format = quad_io_mode; - flash->nor_read_para.addr_phase_format = single_io_mode; - flash->nor_read_para.data_dummy_count = 1; - address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - if (address_bits == 32) { - flash->nor_read_para.addr_bit = flash_addrlen_32bit; - } else { - flash->nor_read_para.addr_bit = flash_addrlen_24bit; - } - - if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { - if (address_bits == 24U) { - if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { - flash->nor_read_para.read_cmd = param_tbl->read_1_4_info.inst_1_4_4_read; - } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { - flash->nor_read_para.read_cmd = param_tbl->read_1_4_info.inst_1_1_4_read; - } else { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_3B; - dummy_cycles = 0; - mode_cycles = 0; - } - } else { - if (jedec_info->has_4b_addressing_inst_table) { - if (flash_4b_tbl->cmd_4byte_support_info.support_1_4_4_fast_read != 0U) { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_4_4_4B; - flash->nor_read_para.addr_phase_format = quad_io_mode; - } else if (flash_4b_tbl->cmd_4byte_support_info.support_1_1_4_fast_read != 0U) { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_4_4B; - } else { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; - dummy_cycles = 0; - mode_cycles = 0; - } - } else if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { /* For device that is only compliant with JESD216 */ - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_4_4_4B; - } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_4_4B; - } else { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; - dummy_cycles = 0; - mode_cycles = 0; - } - } - } else if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { - if (address_bits == 24U) { - if (param_tbl->misc.support_1_2_2_fast_read != 0U) { - flash->nor_read_para.read_cmd = param_tbl->read_1_2_info.inst_1_2_2_read; - flash->nor_read_para.data_phase_format = dual_io_mode; - } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { - flash->nor_read_para.read_cmd = param_tbl->read_1_2_info.inst_1_1_2_read; - } else { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_3B; - dummy_cycles = 0; - mode_cycles = 0; - } - } else { - if (jedec_info->has_4b_addressing_inst_table) { - if (flash_4b_tbl->cmd_4byte_support_info.support_1_2_2_fast_read != 0U) { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_2_2_4B; - flash->nor_read_para.data_phase_format = dual_io_mode; - } else if (flash_4b_tbl->cmd_4byte_support_info.support_1_1_2_fast_read != 0U) { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_2_4B; - flash->nor_read_para.data_phase_format = dual_io_mode; - } else { - flash->nor_read_para.data_phase_format = single_io_mode; - flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; - dummy_cycles = 0; - mode_cycles = 0; - } - } else if (param_tbl->misc.support_1_2_2_fast_read != 0U) { /* For device that is only compliant with JESD216 */ - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_2_2_4B; - flash->nor_read_para.data_phase_format = dual_io_mode; - } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { - flash->nor_read_para.read_cmd = SERIALNOR_CMD_READ_SDR_1_1_2_4B; - flash->nor_read_para.data_phase_format = dual_io_mode; - } else { - flash->nor_read_para.data_phase_format = single_io_mode; - flash->nor_read_para.read_cmd = SERIALNOR_CMD_BASICREAD_4B; - dummy_cycles = 0; - mode_cycles = 0; - } - } - - } else { - flash->nor_read_para.read_cmd = (address_bits == 32U) ? SERIALNOR_CMD_BASICREAD_4B : SERIALNOR_CMD_BASICREAD_3B; - flash->nor_read_para.data_phase_format = single_io_mode; - flash->nor_read_para.data_dummy_count = 0; - dummy_cycles = 0; - mode_cycles = 0; - } - - /* Determine Read command based on SFDP */ - if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { - if (param_tbl->misc.supports_1_4_4_fast_read != 0U) { - flash->nor_read_para.addr_phase_format = quad_io_mode; - mode_cycles = param_tbl->read_1_4_info.mode_clocks_1_4_4_read; - dummy_cycles = param_tbl->read_1_4_info.dummy_clocks_1_4_4_read; - } else if (param_tbl->misc.support_1_1_4_fast_read != 0U) { - mode_cycles = param_tbl->read_1_4_info.mode_clocks_1_1_4_read; - dummy_cycles = param_tbl->read_1_4_info.dummy_clocks_1_1_4_read; - } else { - /* Reserved for future use */ - } - } else if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { - if (param_tbl->misc.support_1_2_2_fast_read != 0U) { - flash->nor_read_para.addr_phase_format = dual_io_mode; - mode_cycles = param_tbl->read_1_2_info.mode_clocks_1_2_2_read; - dummy_cycles = param_tbl->read_1_2_info.dummy_clocks_1_2_2_read; - } else if (param_tbl->misc.support_1_1_2_fast_read != 0U) { - flash->nor_read_para.addr_phase_format = single_io_mode; - mode_cycles = param_tbl->read_1_2_info.mode_clocks_1_1_2_read; - dummy_cycles = param_tbl->read_1_2_info.dummy_clocks_1_1_2_read; - } else { - /* Reserved for future use */ - } - } - - if ((dummy_cycles) && (!(flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE))) { - if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE) { - dummy_count = ((dummy_cycles + mode_cycles) / 4); - } else { - dummy_count = ((dummy_cycles + mode_cycles) / 2); - } - /* SPI is only support 4 dummy count*/ - if (dummy_count > 5) { - flash->nor_read_para.data_phase_format = single_io_mode; - flash->nor_read_para.addr_phase_format = single_io_mode; - flash->nor_read_para.read_cmd = (address_bits == 32U) ? SERIALNOR_CMD_BASICREAD_4B : SERIALNOR_CMD_BASICREAD_3B; - } else { - flash->nor_read_para.data_dummy_count = dummy_count; - } - } - return status_success; -} - -static hpm_stat_t hpm_spi_get_program_para(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) -{ - jedec_4byte_addressing_inst_table_t *flash_4b_tbl; - flash_4b_tbl = &jedec_info->flash_4b_inst_tbl; - flash->nor_program_para.has_4b_addressing_inst_table = jedec_info->has_4b_addressing_inst_table; - flash->nor_program_para.support_1_1_4_page_program = flash_4b_tbl->cmd_4byte_support_info.support_1_1_4_page_program; - flash->nor_program_para.support_1_4_4_page_program = flash_4b_tbl->cmd_4byte_support_info.support_1_4_4_page_program; - return status_success; -} - -static hpm_stat_t hpm_spi_nor_read_sfdp(hpm_serial_nor_t *flash, uint32_t addr, uint32_t *buffer, uint32_t bytes) -{ - hpm_serial_nor_transfer_seq_t command_seq = {0}; - command_seq.use_dma = false; - command_seq.cmd_phase.cmd = SERIAL_FLASH_READ_SFDP; - command_seq.addr_phase.addr = addr; - command_seq.addr_phase.enable = true; - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.dummy_phase.dummy_count = 1; - command_seq.data_phase.direction = read_direction; - command_seq.data_phase.data_io_mode = single_io_mode; - command_seq.data_phase.buf = (uint8_t *)buffer; - command_seq.data_phase.len = bytes; - return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); -} - -static hpm_stat_t hpm_spi_nor_set_command(hpm_serial_nor_t *flash, uint8_t cmd) -{ - hpm_serial_nor_transfer_seq_t command_seq = {0}; - command_seq.use_dma = false; - command_seq.cmd_phase.cmd = cmd; - return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); -} - -static hpm_stat_t get_page_sector_block_size_from_sfdp(hpm_serial_nor_info_t *config, jedec_info_table_t *tbl) -{ - hpm_stat_t status = status_invalid_argument; - jedec_flash_param_table_t *param_tbl = &tbl->flash_param_tbl; - jedec_4byte_addressing_inst_table_t *flash_4b_tbl = &tbl->flash_4b_inst_tbl; - - /* Calculate Flash Size */ - uint32_t flash_size; - uint32_t flash_density = tbl->flash_param_tbl.flash_density; - uint32_t page_size; - uint32_t sector_size = 0xFFFFFFUL; - uint32_t block_size = 0U; - uint32_t block_erase_type = 0U; - uint32_t sector_erase_type = 0U; - - if (IS_HPM_BIT_SET(flash_density, 31)) { - /* Flash size >= 4G bits */ - flash_size = 1UL << ((flash_density & ~(1UL << 0x1F)) - 3U); - } else { - /* Flash size < 4G bits */ - flash_size = (flash_density + 1U) >> 3; - } - - do { - HPM_BREAK_IF(flash_size < 1U); - config->size_in_kbytes = flash_size / SIZE_1KB; - /* Calculate Page size */ - if (tbl->flash_param_tbl_size < SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA) { - config->page_size = 256U; - } else { - page_size = 1UL << (param_tbl->chip_erase_progrm_info.page_size); - config->page_size = (page_size == (1UL << 15)) ? 256U : page_size; - } - /* Calculate Sector Size */ - for (uint32_t index = 0; index < 4U; index++) { - if (param_tbl->erase_info[index].size != 0U) { - uint32_t current_erase_size = 1UL << param_tbl->erase_info[index].size; - if (current_erase_size < SIZE_1KB) { - continue; - } - if (current_erase_size < sector_size) { - sector_size = current_erase_size; - sector_erase_type = index; - } - if ((current_erase_size > block_size) && (current_erase_size < (1024U * 1024U))) { - block_size = current_erase_size; - block_erase_type = index; - } - } - } - - config->sector_size_kbytes = sector_size / SIZE_1KB; - - config->block_size_kbytes = block_size / SIZE_1KB; - - if (flash_size > MAX_24BIT_ADDRESSING_SIZE) { - if (tbl->has_4b_addressing_inst_table) { - config->sector_erase_cmd = flash_4b_tbl->erase_inst_info.erase_inst[sector_erase_type]; - config->block_erase_cmd = flash_4b_tbl->erase_inst_info.erase_inst[block_erase_type]; - } else { - switch (param_tbl->erase_info[sector_erase_type].inst) { - case SERIALNOR_CMD_SE4K_3B: - config->sector_erase_cmd = SERIALNOR_CMD_SE4K_4B; - break; - case SERIALNOR_CMD_SE64K_3B: - config->sector_erase_cmd = SERIALNOR_CMD_SE64K_4B; - break; - default: - /* Reserved for future use */ - break; - } - switch (param_tbl->erase_info[block_erase_type].inst) { - case SERIALNOR_CMD_SE4K_3B: - config->block_erase_cmd = SERIALNOR_CMD_SE4K_4B; - break; - case SERIALNOR_CMD_SE64K_3B: - config->block_erase_cmd = SERIALNOR_CMD_SE64K_4B; - break; - default: - /* Reserved for future use */ - break; - } - } - } else { - config->sector_erase_cmd = param_tbl->erase_info[sector_erase_type].inst; - config->block_erase_cmd = param_tbl->erase_info[block_erase_type].inst; - } - - status = status_success; - - } while (false); - - return status; -} - -static hpm_stat_t hpm_spi_nor_read_status_register(hpm_serial_nor_t *flash, uint8_t *reg_data, uint8_t status_reg) -{ - hpm_serial_nor_transfer_seq_t command_seq = {0}; - command_seq.use_dma = false; - command_seq.cmd_phase.cmd = status_reg; - command_seq.data_phase.direction = read_direction; - command_seq.data_phase.buf = reg_data; - command_seq.data_phase.data_io_mode = single_io_mode; - command_seq.data_phase.len = sizeof(uint8_t); - return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); -} - -static hpm_stat_t hpm_spi_nor_write_status_register(hpm_serial_nor_t *flash, uint8_t reg_data, uint8_t status_reg) -{ - hpm_stat_t stat; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - } - - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - command_seq.use_dma = false; - command_seq.cmd_phase.cmd = status_reg; - command_seq.data_phase.direction = write_direction; - command_seq.data_phase.buf = (uint8_t *)®_data; - command_seq.data_phase.data_io_mode = single_io_mode; - command_seq.data_phase.len = sizeof(uint8_t); - return flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); -} - -static hpm_stat_t prepare_quad_mode_enable_sequence(hpm_serial_nor_t *flash, jedec_info_table_t *jedec_info) -{ - hpm_stat_t status = status_success; - uint8_t status_val = 0; - uint8_t read_status_reg = 0; - uint8_t write_status_reg = 0; - /* See JESD216B 6.4.18 for more details. */ - do { - /* Enter Quad mode */ - spi_nor_quad_enable_seq_t enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; - /* Ideally, we only need one condition here, however, for some Flash devices that actually support JESD216A - * before the standard is publicly released, the JESD minor revision is still the initial version. That is why - * we use two conditions to handle below logic. - */ - if ((jedec_info->standard_version >= SFDP_VERSION_MINOR_A) || - (jedec_info->flash_param_tbl_size >= SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA)) { - switch (jedec_info->flash_param_tbl.mode_4_4_info.quad_enable_requirement) { - case 1: - case 4: - case 5: - enter_quad_mode_option = spi_nor_quad_en_set_bit1_in_status_reg2; - break; - case 6: - enter_quad_mode_option = spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd; - break; - case 2: - enter_quad_mode_option = spi_nor_quad_en_set_bit6_in_status_reg1; - break; - case 3: - enter_quad_mode_option = spi_nor_quad_en_set_bit7_in_status_reg2; - break; - default: - enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; - flash->flash_info.en_dev_mode_cfg = 0; - break; - } - } else { - /* Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 reads based on instruction */ - enter_quad_mode_option = spi_nor_quad_en_auto_or_ignore; - status = status_spi_nor_flash_not_qe_bit_in_sfdp; - } - /* Retrieve the read status command */ - if (enter_quad_mode_option != spi_nor_quad_en_auto_or_ignore) { - - switch (enter_quad_mode_option) { - case spi_nor_quad_en_set_bit1_in_status_reg2: - case spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd: - read_status_reg = kSERIALNOR_CMD_READ_STATUS_REG2_VIA_0X31; - break; - case spi_nor_quad_en_set_bit6_in_status_reg1: - read_status_reg = SERIALNOR_CMD_READ_STATUS_REG1; - break; - case spi_nor_quad_en_set_bit7_in_status_reg2: - read_status_reg = SERIALNOR_CMD_READ_STATUS_REG2; - break; - default: - /* Reserved for future use */ - break; - } - status = hpm_spi_nor_read_status_register(flash, &status_val, read_status_reg); - HPM_BREAK_IF(status != status_success); - - /* Do modify-after-read status and then create Quad mode Enable sequence - * Enable QE bit only if it is not enabled. - */ - flash->flash_info.en_dev_mode_cfg = 0; - switch (enter_quad_mode_option) { - case spi_nor_quad_en_set_bit6_in_status_reg1: - if (!IS_HPM_BIT_SET(status_val, 6)) { - write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG1; - status_val &= (uint8_t) ~0x3cU; /* Clear Block protection */ - status_val |= HPM_BITSMASK(1U, 6); - status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); - HPM_BREAK_IF(status != status_success); - flash->flash_info.en_dev_mode_cfg = 1U; - } - break; - case spi_nor_quad_en_set_bit1_in_status_reg2: - if (!IS_HPM_BIT_SET(status_val, 1)) { - write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG1; - status_val |= HPM_BITSMASK(1U, 1); - /* QE bit will be programmed after status1 register, so need to left shit 8 bit */ - status_val <<= 8; - status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); - HPM_BREAK_IF(status != status_success); - flash->flash_info.en_dev_mode_cfg = 1U; - } - break; - case spi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd: - if (!IS_HPM_BIT_SET(status_val, 1)) { - write_status_reg = kSERIALNOR_CMD_WRITE_STATUS_REG2_VIA_0X31; - status_val |= HPM_BITSMASK(1U, 1); - status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); - HPM_BREAK_IF(status != status_success); - flash->flash_info.en_dev_mode_cfg = 1U; - } - break; - case spi_nor_quad_en_set_bit7_in_status_reg2: - if (!IS_HPM_BIT_SET(status_val, 7)) { - write_status_reg = SERIALNOR_CMD_WRITE_STATUS_REG2; - status_val |= HPM_BITSMASK(1U, 7); - status = hpm_spi_nor_write_status_register(flash, status_val, write_status_reg); - HPM_BREAK_IF(status != status_success); - flash->flash_info.en_dev_mode_cfg = 1U; - } - break; - default: - flash->flash_info.en_dev_mode_cfg = 0U; - break; - } - } - } while (false); - - return status; -} - -static hpm_stat_t hpm_serial_nor_read_sfdp_info(hpm_serial_nor_t *flash, jedec_info_table_t *tbl, bool address_shift_enable) -{ - hpm_stat_t status = status_spi_nor_sfdp_not_found; - do { - sfdp_header_t sfdp_header; - uint32_t address; - uint32_t parameter_header_number; - uint32_t max_hdr_count; - uint32_t parameter_id; - uint32_t table_size; - - status = hpm_spi_nor_read_sfdp(flash, 0, &sfdp_header.words[0], sizeof(sfdp_header)); - HPM_BREAK_IF(status != status_success); - - if (sfdp_header.signature != SFDP_SIGNATURE) { - status = status_spi_nor_sfdp_not_found; - break; - } - - parameter_header_number = (uint32_t) sfdp_header.param_hdr_num + 1U; - - sfdp_parameter_header_t sfdp_param_hdrs[10]; - (void) memset(&sfdp_param_hdrs, 0, sizeof(sfdp_param_hdrs)); - max_hdr_count = parameter_header_number > 10U ? 10U : parameter_header_number; - address = 0x08U; - if (address_shift_enable) { - address <<= 8; - } - status = hpm_spi_nor_read_sfdp(flash, address, &sfdp_param_hdrs[0].words[0], - max_hdr_count * sizeof(sfdp_parameter_header_t)); - HPM_BREAK_IF(status != status_success); - - (void) memset(tbl, 0, sizeof(*tbl)); - - /* Save the standard version for later use. */ - tbl->standard_version = sfdp_header.minor_rev; - - for (uint32_t i = 0; i < max_hdr_count; i++) { - parameter_id = sfdp_param_hdrs[i].parameter_id_lsb + ((uint32_t) sfdp_param_hdrs[i].parameter_id_msb << 8); - - if ((parameter_id == PARAMETER_ID_BASIC_SPIPROTOCOL) || - (parameter_id == PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE) || - (parameter_id == PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR) || - (parameter_id == PARAMETER_ID_XSPIPROFILE1_0) || (parameter_id == PARAMETER_ID_STACTRLCFGREGMAP)) { - address = 0; - for (int32_t index = 2; index >= 0; index--) { - address <<= 8; - address |= sfdp_param_hdrs[i].parameter_table_pointer[index]; - } - table_size = (uint32_t) sfdp_param_hdrs[i].table_length_in_32bit * sizeof(uint32_t); - - if (address_shift_enable) { - address <<= 8; - } - - if (parameter_id == PARAMETER_ID_BASIC_SPIPROTOCOL) { - /* Limit table size to the max supported standard */ - if (table_size > sizeof(jedec_flash_param_table_t)) { - table_size = sizeof(jedec_flash_param_table_t); - } - status = hpm_spi_nor_read_sfdp(flash, address, &tbl->flash_param_tbl.words[0], table_size); - HPM_BREAK_IF(status != status_success); - - tbl->flash_param_tbl_size = table_size; - } else if (parameter_id == PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE) { - status = hpm_spi_nor_read_sfdp(flash, address, &tbl->flash_4b_inst_tbl.words[0], table_size); - HPM_BREAK_IF(status != status_success); - - tbl->has_4b_addressing_inst_table = true; - } else if (parameter_id == PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR) { - status = hpm_spi_nor_read_sfdp(flash, address, &tbl->otcal_ddr_mode_enable_sequence.words[0], - sizeof(jedec_cmd_sequence_change_to_octal_mode_t)); - HPM_BREAK_IF(status != status_success); - - tbl->has_otcal_ddr_mode_enable_sequence_table = true; - } else if (parameter_id == PARAMETER_ID_XSPIPROFILE1_0) { - status = hpm_spi_nor_read_sfdp(flash, address, &tbl->profile1_0_table.words[0], - sizeof(jedec_x_spi_profile1_0_table_t)); - HPM_BREAK_IF(status != status_success); - - tbl->has_spi_profile1_0_table = true; - } else if (parameter_id == PARAMETER_ID_STACTRLCFGREGMAP) { - status = hpm_spi_nor_read_sfdp(flash, address, &tbl->sccr_map.words[0], - sizeof(jedec_status_control_configuration_reg_map_t)); - HPM_BREAK_IF(status != status_success); - - tbl->has_sccr_map = true; - } else { - /* Reserved for future use */ - } - } else { - /* Unsupported parameter type, ignore */ - } - } - - } while (false); - - return status; -} - -hpm_stat_t hpm_serial_nor_is_busy(hpm_serial_nor_t *flash) -{ - uint8_t sr = 0; - hpm_stat_t stat; - if (flash == NULL) { - return status_invalid_argument; - } - stat = hpm_spi_nor_read_status_register(flash, &sr, SERIALNOR_CMD_READ_STATUS_REG1); - if (stat != status_success) { - return stat; - } - return (sr & 0b1) ? status_spi_nor_flash_is_busy : status_success; -} - -hpm_stat_t hpm_serial_nor_write_enable(hpm_serial_nor_t *flash) -{ - hpm_stat_t stat; - uint8_t cmd; - if (flash == NULL) { - return status_invalid_argument; - } - cmd = SERIALNOR_CMD_WRITEENABLE; - stat = hpm_spi_nor_set_command(flash, cmd); - if (stat != status_success) { - return stat; - } - hpm_spi_nor_udelay(1); - return stat; -} - -hpm_stat_t hpm_serial_nor_erase_chip(hpm_serial_nor_t *flash) -{ - hpm_stat_t stat; - uint8_t cmd; - if (flash == NULL) { - return status_invalid_argument; - } - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - - cmd = SERIALNOR_CMD_CHIPERASE; - stat = hpm_spi_nor_set_command(flash, cmd); - if (stat != status_success) { - return stat; - } - - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - return stat; -} - -hpm_stat_t hpm_serial_nor_erase_block_blocking(hpm_serial_nor_t *flash, uint32_t block_addr) -{ - hpm_stat_t stat; - uint8_t cmd; - uint32_t addr; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - - if (flash == NULL) { - return status_invalid_argument; - } - - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - cmd = flash->flash_info.block_erase_cmd; - addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - if (addr == 32) { - command_seq.addr_phase.addr_bit = flash_addrlen_32bit; - } else { - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - } - command_seq.addr_phase.enable = true; - command_seq.cmd_phase.cmd = cmd; - command_seq.addr_phase.addr = block_addr; - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.dummy_phase.dummy_count = 0; - command_seq.use_dma = false; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - - if (stat != status_success) { - return stat; - } - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - return stat; -} - -hpm_stat_t hpm_serial_nor_erase_sector_blocking(hpm_serial_nor_t *flash, uint32_t sector_addr) -{ - hpm_stat_t stat; - uint32_t addr; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - if (flash == NULL) { - return status_invalid_argument; - } - - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - - addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - command_seq.cmd_phase.cmd = flash->flash_info.sector_erase_cmd; - if (addr == 32) { - command_seq.addr_phase.addr_bit = flash_addrlen_32bit; - } else { - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - } - command_seq.addr_phase.enable = true; - command_seq.addr_phase.addr = sector_addr; - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.use_dma = false; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - if (stat != status_success) { - return stat; - } - - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - return stat; -} - -hpm_stat_t hpm_serial_nor_erase_block_noblocking(hpm_serial_nor_t *flash, uint32_t block_addr) -{ - hpm_stat_t stat; - uint32_t addr; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - - if (flash == NULL) { - return status_invalid_argument; - } - - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - - addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - if (addr == 32) { - command_seq.addr_phase.addr_bit = flash_addrlen_32bit; - } else { - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - } - command_seq.addr_phase.enable = true; - command_seq.addr_phase.addr = block_addr; - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.cmd_phase.cmd = flash->flash_info.block_erase_cmd; - command_seq.use_dma = false; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - if (stat != status_success) { - return stat; - } - return stat; -} - -hpm_stat_t hpm_serial_nor_erase_sector_noblocking(hpm_serial_nor_t *flash, uint32_t sector_addr) -{ - hpm_stat_t stat; - uint32_t addr; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - - if (flash == NULL) { - return status_invalid_argument; - } - - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - - addr = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - if (addr == 32) { - command_seq.addr_phase.addr_bit = flash_addrlen_32bit; - } else { - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - } - command_seq.addr_phase.enable = true; - command_seq.addr_phase.addr = sector_addr; - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.cmd_phase.cmd = flash->flash_info.sector_erase_cmd; - command_seq.use_dma = false; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - if (stat != status_success) { - return stat; - } - - return stat; -} - -hpm_stat_t hpm_serial_nor_erase_blocking(hpm_serial_nor_t *flash, uint32_t start, uint32_t length) -{ - hpm_stat_t status = status_invalid_argument; - uint32_t sector_size; - uint32_t block_size; - uint32_t aligned_start; - uint32_t aligned_len; - uint32_t remaining_len; - if (flash == NULL) { - return status_invalid_argument; - } - do { - sector_size = flash->flash_info.sector_size_kbytes * 1024U; - block_size = flash->flash_info.block_size_kbytes * 1024U; - aligned_start = HPM_ALIGN_DOWN(start, sector_size); - aligned_len = HPM_ALIGN_UP(start + length, sector_size) - aligned_start; - - /* If erase address is not block aligned */ - remaining_len = aligned_len; - while (remaining_len > 0U) { - if ((aligned_start % block_size != 0U) || (remaining_len < block_size)) { - status = hpm_serial_nor_erase_sector_blocking(flash, aligned_start); - HPM_BREAK_IF(status != status_success); - aligned_start += sector_size; - remaining_len -= sector_size; - } else { - status = hpm_serial_nor_erase_block_blocking(flash, aligned_start); - HPM_BREAK_IF(status != status_success); - aligned_start += block_size; - remaining_len -= block_size; - } - } - } while (false); - return status; -} - -hpm_stat_t hpm_serial_nor_program_blocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, uint32_t address) -{ - hpm_stat_t stat = status_success; - uint32_t program_size = 0; - uint32_t offset_in_page; - uint32_t remaining_page_size; - uint8_t *src_8; - uint32_t address_bits; - uint32_t offset; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - - if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { - return status_invalid_argument; - } - - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.data_phase.data_io_mode = quad_io_mode; - do { - HPM_BREAK_IF(data_len > (flash->flash_info.size_in_kbytes * SIZE_1KB)); - - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - - offset_in_page = address % flash->flash_info.page_size; - remaining_page_size = flash->flash_info.page_size - offset_in_page; - address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - if (address_bits == 32) { - command_seq.addr_phase.addr_bit = flash_addrlen_32bit; - if ((flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) && (flash->nor_program_para.has_4b_addressing_inst_table)) { - if (flash->nor_program_para.support_1_4_4_page_program == true) { - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B; - command_seq.addr_phase.addr_io_mode = dual_io_mode; - } else if (flash->nor_program_para.support_1_1_4_page_program == true) { - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B; - } else { - /* 1_1_1_page_program */ - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; - command_seq.data_phase.data_io_mode = single_io_mode; - } - } else { /* Only consider 1-1-1 Program */ - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; - command_seq.data_phase.data_io_mode = single_io_mode; - } - } else { - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - flash->nor_program_para.page_program_cmd = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? - SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B : SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B; - - command_seq.data_phase.data_io_mode = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? - quad_io_mode : single_io_mode; - } - command_seq.cmd_phase.cmd = flash->nor_program_para.page_program_cmd; - command_seq.data_phase.direction = write_direction; - command_seq.use_dma = true; - command_seq.addr_phase.enable = true; - while (data_len > 0) { - /* Send page program command */ - program_size = MIN(data_len, remaining_page_size); - /* Ensure the address doesn't across page boundary */ - offset = address % flash->flash_info.page_size; - HPM_BREAK_IF((offset + program_size) > flash->flash_info.page_size); - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - command_seq.addr_phase.addr = address; - command_seq.data_phase.buf = buf; - command_seq.data_phase.len = program_size; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - - HPM_BREAK_IF(stat != status_success); - stat = status_spi_nor_flash_is_busy; - while (stat == status_spi_nor_flash_is_busy) { - stat = hpm_serial_nor_is_busy(flash); - if ((stat != status_success) && (stat != status_spi_nor_flash_is_busy)) { - return stat; - } else { - if (stat == status_success) { - break; - } else { - if (stat == status_success) { - break; - } else { - hpm_spi_nor_udelay(1); - } - } - } - } - /* Get the new address and length for next iteration */ - address += program_size; - data_len -= program_size; - remaining_page_size = flash->flash_info.page_size; - src_8 = (uint8_t *) buf + program_size; - buf = (uint8_t *) src_8; - } - } while (false); - return stat; -} - -hpm_stat_t hpm_serial_nor_page_program_noblocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, uint32_t address) -{ - hpm_stat_t stat = status_success; - uint32_t program_size = 0; - uint32_t offset_in_page; - uint32_t remaining_page_size; - uint32_t address_bits; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - - if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { - return status_invalid_argument; - } - - command_seq.addr_phase.addr_io_mode = single_io_mode; - command_seq.data_phase.data_io_mode = quad_io_mode; - offset_in_page = address % flash->flash_info.page_size; - remaining_page_size = flash->flash_info.page_size - offset_in_page; - program_size = MIN(data_len, remaining_page_size); - if ((data_len > flash->flash_info.page_size) || - ((offset_in_page + program_size) > flash->flash_info.page_size)) { - return status_invalid_argument; - } - - do { - offset_in_page = address % flash->flash_info.page_size; - remaining_page_size = flash->flash_info.page_size - offset_in_page; - address_bits = (flash->flash_info.size_in_kbytes > MAX_24BIT_ADDR_SIZE_IN_KBYTES) ? 32U : 24U; - if (address_bits == 32) { - command_seq.addr_phase.addr_bit = flash_addrlen_32bit; - if ((flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) && (flash->nor_program_para.has_4b_addressing_inst_table)) { - if (flash->nor_program_para.support_1_4_4_page_program > 0U) { - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B; - command_seq.addr_phase.addr_io_mode = dual_io_mode; - } else if (flash->nor_program_para.support_1_1_4_page_program > 0U) { - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B; - } else { - /* 1_1_1_page_program */ - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; - command_seq.data_phase.data_io_mode = single_io_mode; - } - } else { /* Only consider 1-1-1 Program */ - flash->nor_program_para.page_program_cmd = SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B; - command_seq.data_phase.data_io_mode = single_io_mode; - } - } else { - command_seq.addr_phase.addr_bit = flash_addrlen_24bit; - flash->nor_program_para.page_program_cmd = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? - SERIALNOR_CMD_PAGE_PROGRAM_1_1_4_3B : SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B; - - command_seq.data_phase.data_io_mode = (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) ? - quad_io_mode : single_io_mode; - } - command_seq.cmd_phase.cmd = flash->nor_program_para.page_program_cmd; - stat = hpm_serial_nor_write_enable(flash); - if (stat != status_success) { - return stat; - } - command_seq.use_dma = true; - command_seq.addr_phase.addr = address; - command_seq.data_phase.buf = buf; - command_seq.data_phase.len = program_size; - command_seq.data_phase.direction = write_direction; - command_seq.addr_phase.enable = true; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - HPM_BREAK_IF(stat != status_success); - } while (false); - - return stat; -} - -hpm_stat_t hpm_serial_nor_read(hpm_serial_nor_t *flash, uint8_t *buf, uint16_t data_len, uint32_t address) -{ - hpm_stat_t stat; - hpm_serial_nor_transfer_seq_t command_seq = {0}; - uint32_t read_start = address; - - if ((buf == NULL) || (data_len == 0) || (flash == NULL)) { - return status_invalid_argument; - } - - command_seq.addr_phase.addr = read_start; - command_seq.addr_phase.addr_bit = flash->nor_read_para.addr_bit; - command_seq.addr_phase.addr_io_mode = flash->nor_read_para.addr_phase_format; - command_seq.dummy_phase.dummy_count = flash->nor_read_para.data_dummy_count; - command_seq.data_phase.data_io_mode = flash->nor_read_para.data_phase_format; - command_seq.data_phase.buf = buf; - command_seq.data_phase.len = data_len; - command_seq.cmd_phase.cmd = flash->nor_read_para.read_cmd; - command_seq.data_phase.direction = read_direction; - command_seq.use_dma = true; - command_seq.addr_phase.enable = true; - stat = flash->host.host_ops.transfer(flash->host.host_ops.user_data, &command_seq); - return stat; -} - - -hpm_stat_t hpm_serial_nor_init(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info) -{ - jedec_info_table_t jedec_info; - hpm_stat_t stat; - if (flash == NULL) { - return status_invalid_argument; - } - if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_SPI_INTERFACE) { - serial_nor_host_ops_use_spi(flash); - } else { - /* Reserved for use by other interfaces */ - } - flash->host.host_ops.user_data = &flash->host; - flash->host.host_ops.init(flash->host.host_ops.user_data); - /* in order to ensure read sfdp parameter are correct, spi frequency must be less than 50M, and here,default value is 20M */ - flash->host.host_ops.set_frequency(flash->host.host_ops.user_data, SPI_READ_SFDP_FREQUENCY); - stat = hpm_serial_nor_read_sfdp_info(flash, &jedec_info, false); - if (stat != status_success) { - return stat; - } - flash->host.host_ops.set_frequency(flash->host.host_ops.user_data, flash->host.host_param.param.frequency); - get_page_sector_block_size_from_sfdp(&flash->flash_info, &jedec_info); - memcpy(info, &flash->flash_info, sizeof(hpm_serial_nor_info_t)); - if (flash->host.host_param.flags & SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE) { - stat = prepare_quad_mode_enable_sequence(flash, &jedec_info); - flash->flash_info.sfdp_version = jedec_info.standard_version; - info->sfdp_version = jedec_info.standard_version; - if (stat != status_success) { - flash->host.host_param.flags &= ~SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE | SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE; - } - } - hpm_spi_get_read_para(flash, &jedec_info); - hpm_spi_get_program_para(flash, &jedec_info); - return stat; -} - -hpm_stat_t hpm_serial_nor_get_info(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info) -{ - if (flash == NULL) { - return status_invalid_argument; - } - memcpy(info, &flash->flash_info, sizeof(hpm_serial_nor_info_t)); - return status_success; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h deleted file mode 100644 index bcd81e4f788..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_SERIAL_NOR_H -#define _HPM_SERIAL_NOR_H - -#include "hpm_serial_nor_host.h" - -/** - * @brief spi nor API error codes - */ -enum { - status_spi_nor_sfdp_not_found = MAKE_STATUS(status_group_spi_nor_flash, 0), /**< SFDP table was not found */ - status_spi_nor_ddr_read_dummy_cycle_probe_failed = MAKE_STATUS(status_group_spi_nor_flash, 1), /**< Probing Dummy cyles for DDR read failed */ - status_spi_nor_flash_not_found = MAKE_STATUS(status_group_spi_nor_flash, 2), /**< FLASH was not detected */ - status_spi_nor_flash_para_err = MAKE_STATUS(status_group_spi_nor_flash, 3), - status_spi_nor_flash_is_busy = MAKE_STATUS(status_group_spi_nor_flash, 4), - status_spi_nor_flash_not_qe_bit_in_sfdp = MAKE_STATUS(status_group_spi_nor_flash, 5), -}; - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @brief determine whether the serial nor flash is busy - * @param [in] host the serial nor context - * @return hpm_stat_t: status_spi_nor_flash_is_busy if the serial nor flash is busy - */ -hpm_stat_t hpm_serial_nor_is_busy(hpm_serial_nor_t *flash); - -/** - * @brief set serial nor flash write enable - * @param [in] channel serial nor flash channel - * @return hpm_stat_t: status_success if write enable success - */ -hpm_stat_t hpm_serial_nor_write_enable(hpm_serial_nor_t *flash); - -/** - * @brief erase the serial nor flash chip - * @param [in] host the serial nor context - * @return hpm_stat_t: status_success if erase chip success - */ -hpm_stat_t hpm_serial_nor_erase_chip(hpm_serial_nor_t *flash); - -/** - * @brief erase the serial nor flash block using blocking transfer - * - * @note the erase block address must be block alignment - * - * @param [in] host the serial nor context - * @param [in] block_addr the serial nor flash block address - * @return hpm_stat_t: status_success if erase block success - */ -hpm_stat_t hpm_serial_nor_erase_block_blocking(hpm_serial_nor_t *flash, uint32_t block_addr); - -/** - * @brief erase the serial nor flash block using noblocking transfer - * - * @note the erase block address must be block alignment, it'not wait flash busy status. - * - * @param [in] host the serial nor context - * @param [in] block_addr the serial nor flash block address - * @return hpm_stat_t: status_success if erase block success - */ -hpm_stat_t hpm_serial_nor_erase_block_noblocking(hpm_serial_nor_t *flash, uint32_t block_addr); - -/** - * @brief erase the serial nor flash sector using blocking transfer - * - * @note the erase sector address must be sector alignment - * - * @param [in] host the serial nor context - * @param [in] sector_addr the serial nor flash sector address - * @return hpm_stat_t: status_success if erase sector success - */ -hpm_stat_t hpm_serial_nor_erase_sector_blocking(hpm_serial_nor_t *flash, uint32_t sector_addr); - -/** - * @brief erase the serial nor flash sector using noblocking transfer - * - * @note the erase sector address must be sector alignment, it'not wait flash busy status. - * - * @param [in] host the serial nor context - * @param [in] sector_addr the serial nor flash sector address - * @return hpm_stat_t: status_success if erase sector success - */ -hpm_stat_t hpm_serial_nor_erase_sector_noblocking(hpm_serial_nor_t *flash, uint32_t sector_addr); - -/** - * @brief erase the serial nor flash specified start address and length using blocking transfer - * - * @note the erase sector address must be sector alignment - * - * @param [in] host the serial nor context - * @param [in] sector_addr the serial nor flash sector address - * @return hpm_stat_t: status_success if erase success - */ -hpm_stat_t hpm_serial_nor_erase_blocking(hpm_serial_nor_t *flash, uint32_t start, uint32_t length); - -/** - * @brief program data to the specified serial nor flash address using blocking transfer - * @param [in] host the serial nor context - * @param [in] buf the data source pointer - * @param [in] data_len the data length - * @param [in] address the serial nor flash programming address - * @return hpm_stat_t: status_success if program success - */ -hpm_stat_t hpm_serial_nor_program_blocking(hpm_serial_nor_t *flash, uint8_t *buf, uint32_t data_len, - uint32_t address); - -/** - * @brief program data to the page nor flash address using noblocking transfer - * @param [in] host the serial nor context - * @param [in] buf the data source pointer - * @param [in] data_len the data length - * @param [in] address the serial nor flash programming address - * @return hpm_stat_t: status_success if program success - */ -hpm_stat_t hpm_serial_nor_page_program_noblocking(hpm_serial_nor_t *flash, uint8_t *buf, - uint32_t data_len, - uint32_t address); - -/** - * @brief read the data of specified serial nor flash address - * @param [in] host the serial nor context - * @param [in] buf the data source pointer - * @param [in] data_len the data length - * @param [in] address the serial nor flash reading address - * @return hpm_stat_t: status_success if read success - */ -hpm_stat_t hpm_serial_nor_read(hpm_serial_nor_t *flash, uint8_t *buf, uint16_t data_len, - uint32_t address); - -/** - * @brief the serial nor flash initialization - * @param [in] host the serial nor context - * @param [out] info serial_nor_flash_info_t - * @return hpm_stat_t: status_success if initialization success - */ -hpm_stat_t hpm_serial_nor_init(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info); - -/** - * @brief get the serial nor flash information - * @param [in] host the serial nor context - * @param [out] info serial_nor_flash_info_t - * @return hpm_stat_t: status_success if get information success - */ -hpm_stat_t hpm_serial_nor_get_info(hpm_serial_nor_t *flash, hpm_serial_nor_info_t *info); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h deleted file mode 100644 index 78c2246099c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/hpm_serial_nor_host.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_SERIAL_NOR_HOST_H -#define _HPM_SERIAL_NOR_HOST_H -#include "hpm_common.h" -#include "sfdp_def.h" - -#define SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE (1UL << 0) -#define SERIAL_NOR_HOST_SUPPORT_DUAL_IO_MODE (1UL << 1) -#define SERIAL_NOR_HOST_SUPPORT_QUAD_IO_MODE (1UL << 2) -#define SERIAL_NOR_HOST_SUPPORT_SPI_INTERFACE (1UL << 3) -#define SERIAL_NOR_HOST_SUPPORT_DMA (1UL << 8) -#define SERIAL_NOR_HOST_CS_CONTROL_AUTO (1UL << 9) - -/** - * @brief IO mode of serial nor flash sequence - */ -typedef enum { - single_io_mode = 0, - dual_io_mode, - quad_io_mode -} hpm_serial_nor_seq_io_mode_t; - -/** - * @brief number of address bits of serial nor flash sequence - */ -typedef enum { - flash_addrlen_24bit = 0, - flash_addrlen_32bit -} hpm_serial_nor_seq_addr_bit_t; - -/** - * @brief transfer direction serial nor flash sequence - */ -typedef enum { - write_direction = 0, - read_direction -} hpm_serial_nor_seq_direction_t; - -/** - * @brief information of serial nor flash - */ -typedef struct { - uint8_t en_dev_mode_cfg; - uint8_t sfdp_version; - uint8_t sector_erase_cmd; - uint8_t block_erase_cmd; - uint32_t size_in_kbytes; - uint16_t page_size; - uint16_t sector_size_kbytes; - uint16_t block_size_kbytes; -} hpm_serial_nor_info_t; - -/** - * @brief dma control param of serial nor flash host - */ -typedef struct { - uint8_t rx_dma_ch; - uint8_t tx_dma_ch; - uint8_t rx_dma_req; - uint8_t tx_dma_req; - void *dma_base; - void *dmamux_base; -} hpm_nor_host_dma_control_t; - -/** - * @brief param and operation of serial nor flash host - */ -typedef struct { - uint8_t pin_or_cs_index; - hpm_nor_host_dma_control_t dma_control; - uint32_t clock_name; - uint32_t frequency; - uint32_t transfer_max_size; - void *host_base; - void (*set_cs)(uint32_t cs_pin, uint8_t state); - void (*set_frequency)(void *host, uint32_t freq); -} hpm_nor_host_param_t; - -/** - * @brief spi nor read parameters structure - */ -typedef struct { - uint8_t read_cmd; - uint8_t data_dummy_count; - hpm_serial_nor_seq_addr_bit_t addr_bit; - hpm_serial_nor_seq_io_mode_t data_phase_format; - hpm_serial_nor_seq_io_mode_t addr_phase_format; -} hpm_sfdp_read_para_t; - -/** - * @brief spi nor program parameters structure - */ -typedef struct { - bool has_4b_addressing_inst_table; - bool support_1_4_4_page_program; - bool support_1_1_4_page_program; - uint8_t page_program_cmd; -} hpm_sfdp_program_para_t; - -/** - * @brief param of serial nor flash host - */ -typedef struct { - uint32_t flags; - hpm_nor_host_param_t param; - void *user_data; -} hpm_serial_nor_host_param_t; - -/** - * @brief operation sequence of serial nor flash - * - * @note it's include command + address(optional) + dummy(optional) + data(optional) - * - */ -typedef struct { - /* can choose whether to use DMA in a transfer, even if the flags has DMA*/ - uint8_t use_dma; - - struct { - uint8_t cmd; - } cmd_phase; - - struct { - bool enable; - hpm_serial_nor_seq_addr_bit_t addr_bit; - hpm_serial_nor_seq_io_mode_t addr_io_mode; - uint32_t addr; - } addr_phase; - - struct { - uint8_t dummy_count; - } dummy_phase; - - struct { - /* the operation direction of the data phase, it's include write and read */ - hpm_serial_nor_seq_direction_t direction; - /* the SPI operation mode of the data phase, it's include SPI/DUAL SPI/QUAD SPI and so on */ - hpm_serial_nor_seq_io_mode_t data_io_mode; - uint32_t len; - uint8_t *buf; - } data_phase; - -} hpm_serial_nor_transfer_seq_t; - -/** - * @brief operation of serial nor flash host - */ -typedef struct { - hpm_stat_t (*init)(void *host); - - hpm_stat_t (*transfer)(void *host, hpm_serial_nor_transfer_seq_t *command_seq); - - void (*set_cs)(uint32_t cs_pin, uint8_t state); - - void (*set_frequency)(void *host, uint32_t freq); - - void *user_data; -} serial_nor_host_ops_t; - -/** - * @brief serial nor flash host parameters structure - */ -typedef struct { - hpm_serial_nor_host_param_t host_param; - serial_nor_host_ops_t host_ops; - void *user_data; -} hpm_serial_nor_host_t; - -/** - * @brief serial nor flash parameters structure - */ -typedef struct { - hpm_serial_nor_host_t host; - hpm_sfdp_read_para_t nor_read_para; - hpm_sfdp_program_para_t nor_program_para; - hpm_serial_nor_info_t flash_info; -} hpm_serial_nor_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief serial nor host operation is use spi operation - * @param [in] dev serial nor device - * @return hpm_stat_t: status_success if success - */ -hpm_stat_t serial_nor_host_ops_use_spi(hpm_serial_nor_t *dev); -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c deleted file mode 100644 index 6512d6e4d6e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/interface/spi/hpm_serial_nor_host_spi.c +++ /dev/null @@ -1,369 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifdef HPMSOC_HAS_HPMSDK_DMAV2 -#include "hpm_dmav2_drv.h" -#else -#include "hpm_dma_drv.h" -#endif -#include "hpm_dmamux_drv.h" -#include "hpm_spi_drv.h" -#include "hpm_l1c_drv.h" -#include "board.h" -#include "hpm_serial_nor_host.h" - -static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, - uint32_t dst, uint8_t data_width, uint32_t size, uint8_t burst_size); - -static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, - uint8_t data_width, uint32_t size, uint8_t burst_size); - -static void hpm_config_cmd_addr_format(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq, spi_control_config_t *control_config); - -static hpm_stat_t hpm_spi_transfer_via_dma(hpm_serial_nor_host_t *host, spi_control_config_t *control_config, - uint8_t cmd, uint32_t addr, - uint8_t *buf, uint32_t len, bool is_read); - -static hpm_stat_t transfer(void *host, hpm_serial_nor_transfer_seq_t *command_seq); - -static hpm_stat_t init(void *ops); - -static hpm_stat_t write(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq); - -static hpm_stat_t read(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq); - -ATTR_WEAK hpm_stat_t serial_nor_host_ops_use_spi(hpm_serial_nor_t *dev) -{ - if (dev == NULL) { - return status_invalid_argument; - } - dev->host.host_ops.init = init; - dev->host.host_ops.transfer = transfer; - dev->host.host_ops.set_cs = dev->host.host_param.param.set_cs; - dev->host.host_ops.set_frequency = dev->host.host_param.param.set_frequency; - return status_success; -} - -static hpm_stat_t transfer(void *host, hpm_serial_nor_transfer_seq_t *command_seq) -{ - hpm_stat_t stat = status_success; - if (command_seq->data_phase.direction == read_direction) { - stat = read(host, command_seq); - } else { - stat = write(host, command_seq); - } - return stat; -} - -static hpm_stat_t spi_nor_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, - uint32_t src, uint8_t data_width, uint32_t size, uint8_t burst_size) -{ - hpm_stat_t stat; - dma_channel_config_t config; - if (ch_num >= DMA_SOC_CHANNEL_NUM) { - return status_invalid_argument; - } - dma_default_channel_config(dma_ptr, &config); - config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - config.src_width = data_width; - config.dst_width = data_width; - config.src_addr = src; - config.dst_addr = (uint32_t)&spi_ptr->DATA; - config.size_in_byte = size; - config.src_burst_size = burst_size; - stat = dma_setup_channel(dma_ptr, ch_num, &config, true); - if (stat != status_success) { - return stat; - } - return stat; -} - -static hpm_stat_t spi_nor_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, - uint8_t data_width, uint32_t size, uint8_t burst_size) -{ - hpm_stat_t stat; - dma_channel_config_t config; - if (ch_num >= DMA_SOC_CHANNEL_NUM) { - return status_invalid_argument; - } - dma_default_channel_config(dma_ptr, &config); - config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - config.src_width = data_width; - config.dst_width = data_width; - config.src_addr = (uint32_t)&spi_ptr->DATA; - config.dst_addr = dst; - config.size_in_byte = size; - config.src_burst_size = burst_size; - stat = dma_setup_channel(dma_ptr, ch_num, &config, true); - if (stat != status_success) { - return stat; - } - return stat; -} - -static void hpm_config_cmd_addr_format(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq, spi_control_config_t *control_config) -{ - spi_trans_mode_t _trans_mode; - hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; - control_config->master_config.cmd_enable = true; - - /* judge the valid of addr */ - if (cmd_seq->addr_phase.enable == true) { - control_config->master_config.addr_enable = true; - if (cmd_seq->addr_phase.addr_io_mode == single_io_mode) { - control_config->master_config.addr_phase_fmt = spi_address_phase_format_single_io_mode; - } else { - control_config->master_config.addr_phase_fmt = spi_address_phase_format_dualquad_io_mode; - } - if (cmd_seq->addr_phase.addr_bit == flash_addrlen_24bit) { - spi_set_address_len((SPI_Type *)host->host_param.param.host_base, addrlen_24bit); - } else { - spi_set_address_len((SPI_Type *)host->host_param.param.host_base, addrlen_32bit); - } - } else { - control_config->master_config.addr_enable = false; - } - - /* judge the valid of buf */ - if ((cmd_seq->data_phase.buf != NULL) || (cmd_seq->data_phase.len != 0)) { - if (cmd_seq->dummy_phase.dummy_count == 0) { - _trans_mode = (cmd_seq->data_phase.direction == read_direction) ? spi_trans_read_only : spi_trans_write_only; - } else { - control_config->common_config.dummy_cnt = cmd_seq->dummy_phase.dummy_count - 1; - _trans_mode = (cmd_seq->data_phase.direction == read_direction) ? spi_trans_dummy_read : spi_trans_dummy_write; - } - control_config->common_config.trans_mode = _trans_mode; - - if ((cmd_seq->data_phase.data_io_mode == single_io_mode) - || (host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_SINGLE_IO_MODE)) { - control_config->common_config.data_phase_fmt = spi_single_io_mode; - } else if (cmd_seq->data_phase.data_io_mode == dual_io_mode) { - control_config->common_config.data_phase_fmt = spi_dual_io_mode; - } else { - control_config->common_config.data_phase_fmt = spi_quad_io_mode; - } - } else { - control_config->common_config.trans_mode = spi_trans_no_data; - } -} - -static hpm_stat_t init(void *ops) -{ - spi_format_config_t format_config = {0}; - hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; - if ((host == NULL) || (host->host_param.param.host_base == NULL)) { - return status_invalid_argument; - } - spi_master_get_default_format_config(&format_config); - format_config.common_config.data_len_in_bits = 8; - format_config.common_config.mode = spi_master_mode; - format_config.common_config.cpol = spi_sclk_low_idle; - format_config.common_config.cpha = spi_sclk_sampling_odd_clk_edges; - format_config.common_config.data_merge = false; - spi_format_init(host->host_param.param.host_base, &format_config); - if (host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) { - if ((host->host_param.param.dma_control.dma_base == NULL) || (host->host_param.param.dma_control.dmamux_base == NULL)) { - return status_invalid_argument; - } - dmamux_config(host->host_param.param.dma_control.dmamux_base, - DMA_SOC_CHN_TO_DMAMUX_CHN(host->host_param.param.dma_control.dma_base, - host->host_param.param.dma_control.rx_dma_ch), - host->host_param.param.dma_control.rx_dma_req, true); - - dmamux_config(host->host_param.param.dma_control.dmamux_base, - DMA_SOC_CHN_TO_DMAMUX_CHN(host->host_param.param.dma_control.dma_base, - host->host_param.param.dma_control.tx_dma_ch), - host->host_param.param.dma_control.tx_dma_req, true); - } - return status_success; -} - -static hpm_stat_t hpm_spi_transfer_via_dma(hpm_serial_nor_host_t *host, spi_control_config_t *control_config, - uint8_t cmd, uint32_t addr, - uint8_t *buf, uint32_t len, bool is_read) -{ - hpm_stat_t stat; - uint32_t data_width = 0; - uint8_t burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - uint32_t timeout_count = 0; - uint16_t dma_send_size; - if (is_read) { - /*The supplement of the byte less than the integer multiple of four bytes is an integer multiple of four bytes to DMA*/ - data_width = DMA_TRANSFER_WIDTH_WORD; - if ((len % 4) == 0) { - dma_send_size = len; - } else { - dma_send_size = ((len >> 2) + 1) << 2; - } - stat = spi_setup_dma_transfer((SPI_Type *)host->host_param.param.host_base, control_config, &cmd, &addr, 0, len); - stat = spi_nor_rx_trigger_dma((DMA_Type *)host->host_param.param.dma_control.dma_base, - host->host_param.param.dma_control.rx_dma_ch, - (SPI_Type *)host->host_param.param.host_base, - core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)buf), - data_width, - dma_send_size, burst_size); - while (spi_is_active((SPI_Type *)host->host_param.param.host_base)) { - timeout_count++; - if (timeout_count >= 0xFFFFFF) { - stat = status_timeout; - break; - } - } - timeout_count = 0; - if ((dma_check_transfer_status( - (DMA_Type *)host->host_param.param.dma_control.dma_base, - host->host_param.param.dma_control.rx_dma_ch) && - DMA_CHANNEL_STATUS_TC) == 0) { - dma_disable_channel((DMA_Type *)host->host_param.param.dma_control.dma_base, host->host_param.param.dma_control.rx_dma_ch); - dma_reset((DMA_Type *)host->host_param.param.dma_control.dma_base); - } - } else { - if ((len % 4) == 0) { - spi_enable_data_merge((SPI_Type *)host->host_param.param.host_base); - data_width = DMA_TRANSFER_WIDTH_WORD; - } else { - data_width = DMA_TRANSFER_WIDTH_BYTE; - } - spi_set_tx_fifo_threshold((SPI_Type *)host->host_param.param.host_base, 3); - burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - stat = spi_setup_dma_transfer((SPI_Type *)host->host_param.param.host_base, control_config, &cmd, &addr, len, 0); - - stat = spi_nor_tx_trigger_dma((DMA_Type *)host->host_param.param.dma_control.dma_base, - host->host_param.param.dma_control.tx_dma_ch, - (SPI_Type *)host->host_param.param.host_base, - core_local_mem_to_sys_address(BOARD_RUNNING_CORE, (uint32_t)buf), - data_width, len, burst_size); - - while (spi_is_active((SPI_Type *)host->host_param.param.host_base)) { - timeout_count++; - if (timeout_count >= 0xFFFFFF) { - stat = status_timeout; - break; - } - } - timeout_count = 0; - spi_disable_data_merge((SPI_Type *)host->host_param.param.host_base); - } - return stat; -} -static hpm_stat_t write(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq) -{ - hpm_stat_t stat = status_success; - spi_control_config_t control_config = {0}; - hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; - uint32_t aligned_start; - uint32_t aligned_end; - uint32_t aligned_size; - if ((cmd_seq->data_phase.len > host->host_param.param.transfer_max_size) || (host == NULL) - || (host->host_param.param.host_base == NULL)) { - return status_invalid_argument; - } - - if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { - if (host->host_param.param.set_cs == NULL) { - return status_fail; - } - host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, false); - } - - spi_master_get_default_control_config(&control_config); - hpm_config_cmd_addr_format(ops, cmd_seq, &control_config); - - if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { - control_config.common_config.tx_dma_enable = true; - control_config.common_config.rx_dma_enable = false; - if (l1c_dc_is_enabled()) { - /* cache writeback for sent buff */ - aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)cmd_seq->data_phase.buf); - aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)cmd_seq->data_phase.buf + cmd_seq->data_phase.len); - aligned_size = aligned_end - aligned_start; - l1c_dc_writeback(aligned_start, aligned_size); - } - stat = hpm_spi_transfer_via_dma(host, &control_config, cmd_seq->cmd_phase.cmd, cmd_seq->addr_phase.addr, - (uint8_t *)cmd_seq->data_phase.buf, cmd_seq->data_phase.len, false); - } else { - stat = spi_transfer((SPI_Type *)host->host_param.param.host_base, &control_config, - &cmd_seq->cmd_phase.cmd, &cmd_seq->addr_phase.addr, - cmd_seq->data_phase.buf, cmd_seq->data_phase.len, NULL, 0); - } - if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { - host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, true); - } - return stat; -} - -static hpm_stat_t read(void *ops, hpm_serial_nor_transfer_seq_t *cmd_seq) -{ - hpm_stat_t stat = status_success; - uint32_t aligned_start; - uint32_t aligned_end; - uint32_t aligned_size; - spi_control_config_t control_config = {0}; - hpm_serial_nor_host_t *host = (hpm_serial_nor_host_t *)ops; - uint32_t read_size = 0; - uint32_t read_start = cmd_seq->addr_phase.addr; - uint8_t *dst_8 = (uint8_t *) cmd_seq->data_phase.buf; - uint32_t remaining_len = cmd_seq->data_phase.len; - - if ((host == NULL) || (host->host_param.param.host_base == NULL)) { - return status_invalid_argument; - } - if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { - if (host->host_param.param.set_cs == NULL) { - return status_fail; - } - } - - spi_master_get_default_control_config(&control_config); - hpm_config_cmd_addr_format(ops, cmd_seq, &control_config); - - if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { - if (host->host_param.param.dma_control.dma_base == NULL) { - return status_fail; - } - if (((uint32_t)dst_8 % HPM_L1C_CACHELINE_SIZE) != 0) { - return status_invalid_argument; - } - control_config.common_config.tx_dma_enable = false; - control_config.common_config.rx_dma_enable = true; - } - while (remaining_len > 0U) { - if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { - host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, false); - } - read_size = MIN(remaining_len, host->host_param.param.transfer_max_size); - if ((host->host_param.flags & SERIAL_NOR_HOST_SUPPORT_DMA) && (cmd_seq->use_dma == 1)) { - spi_enable_data_merge((SPI_Type *)host->host_param.param.host_base); - stat = hpm_spi_transfer_via_dma(host, &control_config, cmd_seq->cmd_phase.cmd, read_start, dst_8, read_size, true); - } else { - stat = spi_transfer((SPI_Type *)host->host_param.param.host_base, &control_config, &cmd_seq->cmd_phase.cmd, - &read_start, NULL, 0, dst_8, read_size); - } - HPM_BREAK_IF(stat != status_success); - if (l1c_dc_is_enabled()) { - /* cache invalidate for receive buff */ - aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)dst_8); - aligned_end = HPM_L1C_CACHELINE_ALIGN_UP(read_size); - aligned_size = aligned_end - aligned_start; - l1c_dc_invalidate(aligned_start, aligned_size); - } - read_start += read_size; - remaining_len -= read_size; - dst_8 += read_size; - if (!(host->host_param.flags & SERIAL_NOR_HOST_CS_CONTROL_AUTO)) { - host->host_param.param.set_cs(host->host_param.param.pin_or_cs_index, true); - } - } - spi_disable_data_merge((SPI_Type *)host->host_param.param.host_base); - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h b/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h deleted file mode 100644 index 20184cef132..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/serial_nor/sfdp_def.h +++ /dev/null @@ -1,402 +0,0 @@ -/* */ -/* Created by hpm15 on 3/11/21. */ -/* */ - -#ifndef SFDP_DEF_H -#define SFDP_DEF_H - -#include -#include "hpm_common.h" - -/* ! @brief Commands for probing the FLASH device */ -#define SERIAL_FLASH_READ_SFDP (0x5AU) -#define SERIAL_FLASH_READ_MANUFACTURE_ID (0x9FU) - -/* !@brief SFDP related definitions */ -#define SFDP_SIGNATURE (0x50444653UL) /* ASCII: SFDP */ -#define SFDP_VERSION_MAJOR_1_0 (1U) -#define SFDP_VERSION_MINOR_0 (0U) /* JESD216 */ -#define SFDP_VERSION_MINOR_A (5U) /* JESD216A */ -#define SFDP_VERSION_MINOR_B (6U) /* JESD216B */ -#define SFDP_VERSION_MINOR_C (7U) /* JESD216C */ -#define SFDP_VERSION_MINOR_D (8U) /* JESD216D */ -#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REV0 (36U) -#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA (64U) -#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVB SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVA -#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVC (80U) -#define SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVD SFDP_BASIC_PROTOCOL_TABLE_SIZE_REVC - -typedef union _sfdp_header { - uint32_t words[2]; - struct { - uint32_t signature; - uint8_t minor_rev; - uint8_t major_rev; - uint8_t param_hdr_num; - uint8_t sfdp_access_protocol; /* Defined in JESD216C, reserved for older version */ - }; - -} sfdp_header_t; - -/* !@brief SFDP parameter Type ID definitions */ -#define PARAMETER_ID_BASIC_SPIPROTOCOL (0xFF00U) -/* New Table added in JESD216B */ -#define PARAMETER_ID_SECTOR_MAP (0xFF81U) -#define PARAMETER_ID_4BYTEADDRESS_INSTRUCTION_TABLE (0xFF84U) -/* New Table added in JESD216C */ -#define PARAMETER_ID_XSPIPROFILE1_0 (0xFF05U) -#define PARAMETER_ID_XSPIOROFILE2_0 (0xFF06U) -#define PARAMETER_ID_STACTRLCFGREGMAP (0xFF87U) -#define PARAMETER_ID_OPIENABLESEQ (0xFF09U) -#define PARAMETER_ID_CMDSEQ_CHANGE_TO_OCTAL_DDR (0xFF0AU) - -#define NORFLASH_ADDRESSBITS_3B (0U) -#define NORFLASH_ADDRESSBITS_3B_4B (1U) -#define NORFLASH_ADDRESSBITS_4B (2U) - -#define COMMAND_EXTENSION_SAME_AS_COMMAND (0U) -#define COMMAND_EXTENSION_INVERSE_OF_COMMAND (1U) -#define COMMAND_AND_COMMANDEXTENSION_16BITWORD (2U) - -/* !@brief Supported methods to enter 8-8-8 mode from 1-1-1 mode, More details please refer to JESD216C/D */ -#define ENTER_OCTAL_MODE_OPTION0 HPM_BITSMASK(1U, 1) -#define ENTER_OCTAL_MODE_OPTION1 HPM_BITSMASK(1U, 2) - -/* !@brief SFDP Parameter Header, see JESD216D doc for more details */ -typedef union _sfdp_parameter_header { - uint32_t words[2]; - struct { - uint8_t parameter_id_lsb; - uint8_t minor_rev; - uint8_t major_rev; - uint8_t table_length_in_32bit; - uint8_t parameter_table_pointer[3]; - uint8_t parameter_id_msb; - }; - -} sfdp_parameter_header_t; - -/* !@brief Basic Flash Parameter Table, see JESD216D doc for more details */ -typedef union _jedec_flash_param_table { - uint32_t words[20]; - struct { - struct { - uint32_t erase_size : 2; - uint32_t write_granularity : 1; - uint32_t reserved0 : 2; - uint32_t unused0 : 3; - uint32_t erase4k_inst : 8; - uint32_t support_1_1_2_fast_read : 1; - uint32_t address_bits : 2; - uint32_t support_ddr_clocking : 1; - uint32_t support_1_2_2_fast_read : 1; - uint32_t supports_1_4_4_fast_read : 1; - uint32_t support_1_1_4_fast_read : 1; - uint32_t unused1 : 9; - } misc; /* 1st word */ - uint32_t flash_density; /* 2nd word */ - struct { - uint32_t dummy_clocks_1_4_4_read : 5; - uint32_t mode_clocks_1_4_4_read : 3; - uint32_t inst_1_4_4_read : 8; - uint32_t dummy_clocks_1_1_4_read : 5; - uint32_t mode_clocks_1_1_4_read : 3; - uint32_t inst_1_1_4_read : 8; - } read_1_4_info; /* 3rd word */ - struct { - uint32_t dummy_clocks_1_1_2_read : 5; - uint32_t mode_clocks_1_1_2_read : 3; - uint32_t inst_1_1_2_read : 8; - uint32_t dummy_clocks_1_2_2_read : 5; - uint32_t mode_clocks_1_2_2_read : 3; - uint32_t inst_1_2_2_read : 8; - } read_1_2_info; /* 4th word */ - - struct { - uint32_t support_2_2_2_fast_read : 1; - uint32_t reserved0 : 3; - uint32_t support_4_4_4_fast_read : 1; - uint32_t reserved1 : 27; - } read_22_44_check; /* 5th word */ - - struct { - uint32_t reserved0 : 16; - uint32_t dummy_clocks_2_2_2_read : 5; - uint32_t mode_clocks_2_2_2_read : 3; - uint32_t inst_2_2_2_read : 8; - } read_2_2_info; /* 6th word */ - struct { - uint32_t reserved0 : 16; - uint32_t dummy_clocks_4_4_4_read : 5; - uint32_t mode_clocks_4_4_4_read : 3; - uint32_t inst_4_4_4_read : 8; - } read_4_4_info; /* 7th word */ - - struct { - uint8_t size; - uint8_t inst; - } erase_info[4]; /* 8th,9th word */ - - uint32_t erase_timing; /* 10th word */ - struct { - uint32_t reserved0 : 4; - uint32_t page_size : 4; - uint32_t reserved1 : 24; - } chip_erase_progrm_info; /* 11th word */ - - struct { - uint32_t suspend_resume_spec; - uint32_t suspend_resume_inst; - } suspend_resume_info; /* 12th, 13th word */ - - struct { - uint32_t reserved0 : 2; - uint32_t busy_status_polling : 6; - uint32_t reserved1 : 24; - } busy_status_info; /* 14th word */ - - struct { - uint32_t mode_4_4_4_disable_seq : 4; - uint32_t mode_4_4_4_enable_seq : 5; - uint32_t support_mode_0_4_4 : 1; - uint32_t mode_0_4_4_exit_method : 6; - uint32_t mode_0_4_4_entry_method : 4; - uint32_t quad_enable_requirement : 3; - uint32_t hold_reset_disable : 1; - uint32_t reserved0 : 8; - } mode_4_4_info; /* 15th word */ - - struct { - uint32_t status_reg_write_enable : 7; - uint32_t reserved0 : 1; - uint32_t soft_reset_rescue_support : 6; - uint32_t exit_4_byte_addressing : 10; - uint32_t enter_4_byte_addrssing : 8; - } mode_config_info; /* 16th word */ - - struct { - uint32_t dummy_clocks_1_8_8_read : 5; - uint32_t mode_clocks_1_8_8_read : 3; - uint32_t inst_1_8_8_read : 8; - uint32_t dummy_clocks_1_1_8_read : 5; - uint32_t mode_clocks_1_1_8_read : 3; - uint32_t inst_1_1_8_read : 8; - } read_1_8_info; /* 17th word */ - - struct { - uint32_t reserved : 18; - uint32_t output_driver_strength : 5; - uint32_t jedec_spi_protocol_reset : 1; - uint32_t dqs_waveform_type_sdr : 2; - uint32_t dqs_support_in_qpi_sdr : 1; - uint32_t dqs_support_in_qpi_ddr : 1; - uint32_t dqs_support_in_opi_str : 1; - uint32_t cmd_and_extension_in_opi_ddr : 2; - uint32_t byte_order_in_opi_ddr : 1; - } xpi_misc_info; /* 18th word */ - - struct { - uint32_t opi_sdr_disable_seq : 4; - uint32_t opi_sdr_enable_seq : 5; - uint32_t support_mode_0_8_8 : 1; - uint32_t mode_0_8_8_exit_method : 6; - uint32_t mode_0_8_8_entry_method : 4; - uint32_t octal_enable_requirement : 3; - uint32_t reserved : 9; - } mode_octal_info; /* 19th word */ - - struct { - uint32_t qpi_sdr_no_dqs : 4; - uint32_t qpi_sdr_with_dqs : 4; - uint32_t qpi_ddr_no_dqs : 4; - uint32_t qpi_ddr_with_dqs : 4; - uint32_t opi_sdr_no_dqs : 4; - uint32_t opi_sdr_with_dqs : 4; - uint32_t opi_ddr_no_dqs : 4; - uint32_t opi_ddr_with_dqs : 4; - } max_speed_info_xpi; /* 20th word */ - }; - -} jedec_flash_param_table_t; - -/* !@brief 4Byte Addressing Instruction Table, see JESD216D doc for more details */ -typedef union _jedec_4byte_addressing_inst_table { - uint32_t words[2]; - struct { - struct { - uint32_t support_1_1_1_read : 1; - uint32_t support_1_1_1_fast_read : 1; - uint32_t support_1_1_2_fast_read : 1; - uint32_t support_1_2_2_fast_read : 1; - uint32_t support_1_1_4_fast_read : 1; - uint32_t support_1_4_4_fast_read : 1; - uint32_t support_1_1_1_page_program : 1; - uint32_t support_1_1_4_page_program : 1; - uint32_t support_1_4_4_page_program : 1; - uint32_t support_erase_type1_size : 1; - uint32_t support_erase_type2_size : 1; - uint32_t support_erase_type3_size : 1; - uint32_t support_erase_type4_size : 1; - uint32_t support_1_1_1_dtr_read : 1; - uint32_t support_1_2_2_dtr_read : 1; - uint32_t support_1_4_4_dtr_read : 1; - uint32_t support_volatile_sector_lock_read_cmd : 1; - uint32_t support_volatile_sector_lock_write_cmd : 1; - uint32_t support_nonvolatile_sector_lock_read_cmd : 1; - uint32_t support_nonvolatile_sector_lock_write_cmd : 1; - uint32_t reserved : 12; - } cmd_4byte_support_info; - - struct { - uint8_t erase_inst[4]; - } erase_inst_info; - }; -} jedec_4byte_addressing_inst_table_t; - -typedef union _jedec_cmd_sequence_change_to_octal_mode { - uint32_t words[8]; - - struct { - struct { - uint32_t byte3_of_1st_command_seq : 8; - uint32_t byte2_of_1st_command_seq : 8; - uint32_t byte1_of_1st_command_seq : 8; - uint32_t length_of_1st_command_seq : 8; - } first_command_sequence_low; /* 1st command sequence */ - - struct { - uint32_t byte7_of_first_command_seq : 8; - uint32_t byte6_of_first_command_seq : 8; - uint32_t byte5_of_first_command_seq : 8; - uint32_t byte4_of_first_command_seq : 8; - } first_command_sequence_high; /* 1st command sequence */ - - struct { - uint32_t byte3_of_2nd_command_seq : 8; - uint32_t byte2_of_2nd_command_seq : 8; - uint32_t byte1_of_2nd_command_seq : 8; - uint32_t length_of_2nd_command_seq : 8; - } second_command_sequence_low; /* 2nd command sequence */ - - struct { - uint32_t byte7_of_2nd_command_seq : 8; - uint32_t byte6_of_2nd_command_seq : 8; - uint32_t byte5_of_2nd_command_seq : 8; - uint32_t byte4_of_2md_command_seq : 8; - } second_command_sequence_high; /* 2nd command sequence */ - - struct { - uint32_t byte3_of_3rd_command_seq : 8; - uint32_t byte2_of_3rd_command_seq : 8; - uint32_t byte1_of_3rd_command_seq : 8; - uint32_t length_of_3rd_command_seq : 8; - } third_command_sequence_low; /* 3rd command sequence */ - - struct { - uint32_t byte7_of_3rd_command_seq : 8; - uint32_t byte6_of_3rd_command_seq : 8; - uint32_t byte5_of_3rd_command_seq : 8; - uint32_t byte4_of_3rd_command_seq : 8; - } third_command_sequence_high; /* 3rd command sequence */ - - struct { - uint32_t byte3_of_4th_command_seq : 8; - uint32_t byte2_of_4th_command_seq : 8; - uint32_t byte1_of_4th_command_seq : 8; - uint32_t length_of_4th_command_seq : 8; - } fourth_command_sequence_low; /* 4th command sequence */ - - struct { - uint32_t byte7_of_4th_command_seq : 8; - uint32_t byte6_of_4th_command_seq : 8; - uint32_t byte5_of_4th_command_seq : 8; - uint32_t byte4_of_4th_command_seq : 8; - } fourth_command_sequence_high; /* 4th command sequence */ - }; - -} jedec_cmd_sequence_change_to_octal_mode_t; - -typedef union _jedec_x_spi_profile1_0_table_t { - uint32_t words[5]; - - struct { - struct { - uint32_t fast_read_wrapped_cmd : 8; - uint32_t fast_read_cmd : 8; - uint32_t reserved : 16; - } table1; - - struct { - uint32_t write_nv_register_cmd : 8; - uint32_t write_v_register_cmd : 8; - uint32_t reserved : 16; - } table2; - - uint32_t unused_tables[3]; - }; - -} jedec_x_spi_profile1_0_table_t; - -typedef union _jedec_status_control_configuration_reg_map { - uint32_t words[28]; - struct { - uint32_t unused_table[2]; - struct { - uint32_t dummy_cycles_1s_1s_1s : 4; - uint32_t reserved0 : 2; - uint32_t dummy_cycles_8d_8d_8d : 4; - uint32_t dummy_cycles_8s_8s_8s : 4; - uint32_t dummy_cycles_4s_4d_4d : 4; - uint32_t dummy_cycles_4s_4s_4s : 4; - uint32_t dummy_cycles_2s_2s_2s : 4; - uint32_t dummy_cycles_1s_1s_1s_select : 2; - uint32_t addr_bytes_address_status_register : 2; - uint32_t unused0 : 2; - }; - uint32_t unused_table1[25]; - }; -} jedec_status_control_configuration_reg_map_t; - -typedef struct _jdec_query_table { - uint32_t standard_version; /* JESD216 version */ - uint32_t flash_param_tbl_size; - jedec_flash_param_table_t flash_param_tbl; - bool has_4b_addressing_inst_table; - jedec_4byte_addressing_inst_table_t flash_4b_inst_tbl; - bool has_otcal_ddr_mode_enable_sequence_table; - jedec_cmd_sequence_change_to_octal_mode_t otcal_ddr_mode_enable_sequence; /* JESD216C/D */ - jedec_x_spi_profile1_0_table_t profile1_0_table; - bool has_spi_profile1_0_table; - jedec_status_control_configuration_reg_map_t sccr_map; - bool has_sccr_map; -} jedec_info_table_t; - - -/* !@brief Typical Serial NOR commands supported by most Serial NOR devices */ -#define SERIALNOR_CMD_BASICREAD_3B (0x03U) -#define SERIALNOR_CMD_BASICREAD_4B (0x13U) -#define SERIALNOR_CMD_PAGEPROGRAM_1_1_1_3B (0x02U) -#define SERIALNOR_CMD_PAGEPROGRAM_1_1_1_4B (0x12U) -#define SERIALNOR_CMD_PAGEPROGRAM_1_4_4_4B (0x3EU) -#define SERIALNOR_CMD_PAGEPROGRAM_1_1_4_4B (0x34U) -#define SERIALNOR_CMD_READ_SDR_1_4_4_3B (0xEBU) -#define SERIALNOR_CMD_READ_DDR_1_4_4_3B (0xEDU) -#define SERIALNOR_CMD_READ_SDR_1_4_4_4B (0xECU) -#define SERIALNOR_CMD_READ_SDR_1_1_4_4B (0x6CU) -#define SERIALNOR_CMD_READ_DDR_1_4_4_4B (0xEEU) -#define SERIALNOR_CMD_CHIPERASE (0x60U) -#define SERIALNOR_CMD_WRITEENABLE (0x06U) -#define SERIALNOR_CMD_WRITE_STATUS_REG1 (0x01U) -#define SERIALNOR_CMD_READ_STATUS_REG1 (0x05U) -#define SERIALNOR_CMD_WRITE_STATUS_REG2 (0x3EU) -#define SERIALNOR_CMD_READ_STATUS_REG2 (0x3FU) -#define SERIALNOR_CMD_READ_FLAGREG (0x70U) -#define SERIALNOR_CMD_READID (0x9FU) -#define SERIALNOR_CMD_READ_DDR_4B (0x0CU) -#define SERIALNOR_CMD_READ_DDR_3B (0x0BU) -#define SERIALNOR_CMD_SE4K_3B (0x20U) -#define SERIALNOR_CMD_SE4K_4B (0x21U) -#define SERIALNOR_CMD_SE64K_3B (0xD8U) -#define SERIALNOR_CMD_SE64K_4B (0xDCU) - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c deleted file mode 100644 index 8b7633c1567..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_smbus.h" - -static uint8_t hpm_smbus_pec_crc8(uint8_t *data, uint32_t len); - - -hpm_stat_t hpm_smbus_master_write_byte(I2C_Type *ptr, uint8_t slave_address, uint8_t data) -{ - hpm_stat_t stat; - uint8_t buf[3]; - /* addr + rw bit*/ - buf[0] = slave_address << 1; - buf[1] = data; - buf[2] = hpm_smbus_pec_crc8(buf, 2); - stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); - return stat; -} - -hpm_stat_t hpm_smbus_master_read_byte(I2C_Type *ptr, uint8_t slave_address, uint8_t *data) -{ - uint8_t buf[3]; - hpm_stat_t stat; - uint8_t pec; - /* addr + rw bit*/ - buf[0] = (slave_address << 1); - stat = i2c_master_read(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); - if (stat == status_success) { - pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); - if (pec == buf[2]) { - *data = buf[1]; - } else { - stat = status_fail; - } - } - return stat; -} - -hpm_stat_t hpm_smbus_master_write_byte_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t data) -{ - hpm_stat_t stat; - uint8_t buf[4]; - /* addr + rw bit*/ - buf[0] = slave_address << 1; - buf[1] = command; - buf[2] = data; - buf[3] = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); - stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); - return stat; -} - -hpm_stat_t hpm_smbus_master_write_word_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint16_t data) -{ - hpm_stat_t stat; - uint8_t buf[5]; - /* addr + rw bit*/ - buf[0] = slave_address << 1; - buf[1] = command; - *(uint16_t *)(&buf[2]) = data; - buf[4] = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); - stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], sizeof(buf) - 1); - return stat; -} - -hpm_stat_t hpm_smbus_master_read_byte_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data) -{ - hpm_stat_t stat; - uint8_t pec; - uint8_t buf[5]; - /* addr + rw bit*/ - buf[0] = (slave_address << 1); - buf[1] = command; - /* write command code in smbus spec*/ - stat = i2c_master_seq_transmit(ptr, (const uint16_t)slave_address, &command, sizeof(uint8_t), i2c_frist_frame); - if (stat == status_success) { - /* read */ - buf[2] = (slave_address << 1) | 0x01; - /* now change dir,restart, read the byte */ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[3], 1, i2c_frist_frame); - /* read the pec */ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[4], 1, i2c_last_frame); - if (stat == status_success) { - pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); - if (pec == buf[4]) { - *data = buf[3]; - } else { - stat = status_fail; - } - } - } - return stat; -} - -hpm_stat_t hpm_smbus_master_read_word_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint16_t *data) -{ - hpm_stat_t stat; - uint8_t pec; - uint8_t buf[6]; - /* addr + rw bit*/ - buf[0] = (slave_address << 1); - buf[1] = command; - /* write command code in smbus spec*/ - stat = i2c_master_seq_transmit(ptr, (const uint16_t)slave_address, &command, sizeof(uint8_t), i2c_frist_frame); - if (stat == status_success) { - /* read */ - buf[2] = (slave_address << 1) | 0x01; - /* now change dir,restart, read the word (16 bits)*/ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[3], 2, i2c_frist_frame); - /* read the pec */ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[5], 1, i2c_last_frame); - if (stat == status_success) { - pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); - if (pec == buf[5]) { - *data = *(uint16_t *)(&buf[3]); - } else { - stat = status_fail; - } - } - } - return stat; -} - -hpm_stat_t hpm_smbus_master_write_block_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data, uint32_t size) -{ - hpm_stat_t stat; - uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; - /* frame included addr, command, data, and pec */ - assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 3)); - /* addr + rw bit*/ - buf[0] = slave_address << 1; - buf[1] = command; - buf[2] = size; - memcpy(&buf[3], data, size); - buf[size + 3] = hpm_smbus_pec_crc8(buf, size + 3); - buf_size = size + 4; - stat = i2c_master_write(ptr, (const uint16_t)slave_address, buf, buf_size); - return stat; -} - -hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_address, uint8_t command, uint8_t *data, uint32_t size) -{ - hpm_stat_t stat; - uint8_t pec; - uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - /* frame included addr, command, data, and pec */ - assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 3)); - /* addr + rw bit*/ - buf[0] = (slave_address << 1); - buf[1] = command; - /* write command code in smbus spec*/ - stat = i2c_master_seq_transmit(ptr, (const uint16_t)slave_address, &command, sizeof(uint8_t), i2c_frist_frame); - /* read */ - buf[2] = (slave_address << 1) | 0x01; - if (stat == status_success) { - /* now change dir,restart, read the block count*/ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[3], 1, i2c_frist_frame); - /* read data*/ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[4], size, i2c_next_frame); - /* read pec */ - stat = i2c_master_seq_receive(ptr, (const uint16_t)slave_address, &buf[size + 4], 1, i2c_last_frame); - if (stat == status_success) { - pec = hpm_smbus_pec_crc8(buf, sizeof(buf) - 1); - if (pec == buf[size + 4]) { - memcpy(data, &buf[4], size); - } else { - stat = status_fail; - } - } - } - return stat; -} - -hpm_stat_t hpm_smbus_master_write(I2C_Type *ptr, uint8_t slave_address, uint8_t *data, uint32_t size) -{ - hpm_stat_t stat; - uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; - /* frame included addr, data, and pec */ - assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 1)); - /* addr + rw bit*/ - buf[0] = (slave_address << 1) | 0x01; - memcpy(&buf[1], data, size); - buf[size + 1] = hpm_smbus_pec_crc8(buf, size + 1); - buf_size = size + 1; - stat = i2c_master_write(ptr, (const uint16_t)slave_address, &buf[1], buf_size); - return stat; -} - -hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, uint8_t *data, uint32_t size) -{ - hpm_stat_t stat; - uint8_t pec; - uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - /* frame included addr, data, and pec */ - assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); - buf[0] = (slave_address << 1); - stat = i2c_master_read(ptr, slave_address, &buf[1], size + 1); - if (stat == status_success) { - pec = hpm_smbus_pec_crc8(buf, size + 1); - if (pec == buf[size + 1]) { - memcpy(data, &buf[1], size); - } else { - stat = status_fail; - } - } - return stat; -} - -hpm_stat_t hpm_smbus_slave_write(I2C_Type *ptr, uint8_t *data, uint32_t size) -{ - hpm_stat_t stat; - uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint16_t buf_size; - uint8_t slave_address; - /* frame included addr, data, and pec */ - assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 1)); - slave_address = ptr->ADDR; - /* addr + rw bit*/ - buf[0] = (slave_address << 1); - memcpy(&buf[1], data, size); - buf[size + 1] = hpm_smbus_pec_crc8(buf, size + 1); - buf_size = size + 1; - stat = i2c_slave_write(ptr, &buf[1], buf_size); - return stat; -} - -hpm_stat_t hpm_smbus_slave_read(I2C_Type *ptr, uint8_t *data, uint32_t size) -{ - hpm_stat_t stat; - uint8_t pec; - uint8_t buf[I2C_SOC_TRANSFER_COUNT_MAX]; - uint8_t slave_address; - /* frame included addr, data, and pec */ - assert(size > 0 && size <= (I2C_SOC_TRANSFER_COUNT_MAX - 2)); - /* addr + rw bit*/ - slave_address = ptr->ADDR; - buf[0] = (slave_address << 1) | 0x01; - stat = i2c_slave_read(ptr, &buf[1], size + 1); - if (stat == status_success) { - pec = hpm_smbus_pec_crc8(buf, size + 1); - if (pec == buf[size + 1]) { - memcpy(data, &buf[1], size); - } else { - stat = status_fail; - } - } - return stat; -} - -static uint8_t hpm_smbus_pec_crc8(uint8_t *data, uint32_t len) -{ - /* The PEC is a CRC-8 error-checking byte, calculated on all the message bytes (including addresses and read/write bits) */ - uint32_t i; - uint8_t crc = 0x00; - while (len--) { - crc ^= *data++; - for (i = 0; i < 8; i++) { - if (crc & 0x80) { - crc = (crc << 1) ^ 0x07; - } else { - crc <<= 1; - } - } - } - return crc; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h b/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h deleted file mode 100644 index c29ef583053..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/smbus/hpm_smbus.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SMBUS_H -#define HPM_SMBUS_H - -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_i2c_drv.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** - * @brief SMbus master write data - * - * @details write data at slave mode - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] data byte to be writed - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t hpm_smbus_master_write_byte(I2C_Type *ptr, uint8_t slave_address, - uint8_t data); - -/** - * @brief SMbus master read byte from certain slave device - * - * @details Read byte from SMbus device - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [out] data pointer of the byte read from device - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t hpm_smbus_master_read_byte(I2C_Type *ptr, uint8_t slave_address, - uint8_t *data); - -/** - * @brief SMbus master write byte from certain slave device in command code - * - * @details write byte from SMbus device in command code - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] command command code - * @param [in] data byte to be writed - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t hpm_smbus_master_write_byte_in_command(I2C_Type *ptr, uint8_t slave_address, - uint8_t command, uint8_t data); - -/** - * @brief SMbus master write word(16bits) from certain slave device in command code - * - * @details write word(16bits) from SMbus device in command code - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] command command code - * @param [in] data word to be writed - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t hpm_smbus_master_write_word_in_command(I2C_Type *ptr, uint8_t slave_address, - uint8_t command, uint16_t data); - -/** - * @brief SMbus master read byte from certain slave device in command code - * - * @details read byte from SMbus device in command code - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] command command code - * @param [in] data byte to be read - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t hpm_smbus_master_read_byte_in_command(I2C_Type *ptr, uint8_t slave_address, - uint8_t command, uint8_t *data); - -/** - * @brief SMbus master read word(16bits) from certain slave device in command code - * - * @details read word from SMbus device in command code - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] command command code - * @param [in] data word to be read - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t hpm_smbus_master_read_word_in_command(I2C_Type *ptr, uint8_t slave_address, - uint8_t command, uint16_t *data); - -/** - * @brief SMbus master block write from certain slave device in command code - * - * @details block write from SMbus device in command code - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] command command code - * @param [in] data pointer of the buffer to store data read from device - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t hpm_smbus_master_write_block_in_command(I2C_Type *ptr, uint8_t slave_address, - uint8_t command, uint8_t *data, uint32_t size); - -/** - * @brief SMbus master block read from certain slave device in command code - * - * @details block read from SMbus device in command code - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] command command code - * @param [out] data pointer of the buffer to store data read from device - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t hpm_smbus_master_read_block_in_command(I2C_Type *ptr, uint8_t slave_address, - uint8_t command, uint8_t *data, uint32_t size); - -/** - * @brief SMbus master write data to certain slave device - * - * @details Write data to SMbus device - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [in] data pointer of the data to be sent - * @param [in] size size of data to be sent in bytes - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t hpm_smbus_master_write(I2C_Type *ptr, uint8_t slave_address, - uint8_t *data, uint32_t size); - -/** - * @brief SMbus master read data from certain slave device - * - * @details Read data from SMbus device - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address SMbus slave address - * @param [out] data pointer of the buffer to store data read from device - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t hpm_smbus_master_read(I2C_Type *ptr, uint8_t slave_address, - uint8_t *data, uint32_t size); - -/** - * @brief SMbus slave write data - * - * @details Write data at SMbus slave mode. - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] buf pointer of the buffer to store data sent from device - * @param [in] size size of data to be sent in bytes - * @retval hpm_stat_t status_success if writing is completed without any error - */ -hpm_stat_t hpm_smbus_slave_write(I2C_Type *ptr, uint8_t *data, uint32_t size); - -/** - * @brief SMbus slave read data - * - * @details Read data at SMbus slave mode - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] buf pointer of the buffer to store data read from device - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t hpm_smbus_slave_read(I2C_Type *ptr, uint8_t *data, uint32_t size); - -#ifdef __cplusplus -} -#endif - -#endif - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c deleted file mode 100644 index f5b2a9a877e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c +++ /dev/null @@ -1,1254 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_spi.h" -#include "hpm_clock_drv.h" -#include - -#if USE_DMA_MGR -#include "hpm_dma_mgr.h" -#endif -typedef struct { - SPI_Type *spi_ptr; - clock_name_t spi_clock_name; -#if USE_DMA_MGR - uint8_t tx_dmamux_src; - uint8_t rx_dmamux_src; - dma_resource_t txdma_resource; - dma_resource_t rxdma_resource; - spi_dma_complete_cb tx_dma_complete; - spi_dma_complete_cb rx_dma_complete; -#endif -} hpm_spi_cfg_t; - -static hpm_spi_cfg_t spi_dma_cfg_table[] = { -#if defined(HPM_SPI0) - { - .spi_ptr = HPM_SPI0, - .spi_clock_name = clock_spi0, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI0_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI0_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL -#endif - }, -#endif - -#if defined(HPM_SPI1) - { - .spi_ptr = HPM_SPI1, - .spi_clock_name = clock_spi1, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI1_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI1_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI2) - { - .spi_ptr = HPM_SPI2, - .spi_clock_name = clock_spi2, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI2_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI2_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI3) - { - .spi_ptr = HPM_SPI3, - .spi_clock_name = clock_spi3, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI3_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI3_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI4) - { - .spi_ptr = HPM_SPI4, - .spi_clock_name = clock_spi4, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI4_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI4_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI5) - { - .spi_ptr = HPM_SPI5, - .spi_clock_name = clock_spi5, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI5_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI5_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI6) - { - .spi_ptr = HPM_SPI6, - .spi_clock_name = clock_spi6, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI6_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI6_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI7) - { - .spi_ptr = HPM_SPI7, - .spi_clock_name = clock_spi7, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI7_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI7_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI8) - { - .spi_ptr = HPM_SPI8, - .spi_clock_name = clock_spi8, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI8_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI8_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI9) - { - .spi_ptr = HPM_SPI9, - .spi_clock_name = clock_spi9, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI9_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI9_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif - -#if defined(HPM_SPI10) - { - .spi_ptr = HPM_SPI10, - .spi_clock_name = clock_spi10, -#if USE_DMA_MGR - .tx_dmamux_src = HPM_DMA_SRC_SPI10_TX, - .rx_dmamux_src = HPM_DMA_SRC_SPI10_RX, - .rx_dma_complete = NULL, - .tx_dma_complete = NULL, -#endif - }, -#endif -}; - - -static hpm_stat_t hpm_spi_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t src, uint8_t data_width, uint32_t size) -{ - dma_handshake_config_t config; - - dma_default_handshake_config(dma_ptr, &config); - config.ch_index = ch_num; - config.dst = (uint32_t)&spi_ptr->DATA; - config.dst_fixed = true; - config.src = src; - config.src_fixed = false; - config.data_width = data_width; - config.size_in_byte = size; - - return dma_setup_handshake(dma_ptr, &config, true); -} - -static hpm_stat_t hpm_spi_rx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, SPI_Type *spi_ptr, uint32_t dst, uint8_t data_width, uint32_t size) -{ - dma_handshake_config_t config; - - dma_default_handshake_config(dma_ptr, &config); - config.ch_index = ch_num; - config.dst = dst; - config.dst_fixed = false; - config.src = (uint32_t)&spi_ptr->DATA; - config.src_fixed = true; - config.data_width = data_width; - config.size_in_byte = size; - - return dma_setup_handshake(dma_ptr, &config, true); -} - - -void hpm_spi_prepare_dma_tx_descriptors(spi_context_t *context, spi_control_config_t *config, uint32_t trans_count, - uint32_t *spi_transctrl, dma_linked_descriptor_t *tx_dma_descriptors) -{ - SPI_Type *ptr = context->ptr; - uint32_t dma_transfer_size[trans_count]; - uint32_t tx_count = context->tx_count; - uint32_t per_trans_size = context->per_trans_max; - uint32_t dma_ch = context->dma_context.tx_dma_ch; - uint8_t *tx_buff = context->tx_buff; - dma_channel_config_t dma_ch_config; - - static uint8_t dummy_cmd = 0xff; - - uint32_t temp32; - uint32_t tx_buff_index = 0; - - dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); - for (uint32_t i = 0; i < trans_count; i++) { - if (tx_count > per_trans_size) { - temp32 = per_trans_size; - tx_count -= per_trans_size; - } else { - temp32 = tx_count; - } - - *(spi_transctrl + i) = SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode == spi_trans_write_read_together ? - spi_trans_write_read_together : spi_trans_write_only) - | SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) - | SPI_TRANSCTRL_WRTRANCNT_SET(temp32 - 1) - | SPI_TRANSCTRL_RDTRANCNT_SET(temp32 - 1); - - if (i == 0) { - /* Set the count of data transferred by dma to be one more than that of spi */ - /* when dma transfer finished, there are data in SPI fifo, dma should not execute the dma descriptor which changes SPI CTRL register */ - temp32 = temp32 + 1; - } - if (i == trans_count - 1) { - temp32 = temp32 - 1; - } - dma_transfer_size[i] = temp32; - - /* SPI CTRL */ - dma_ch_config.size_in_byte = 4; - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); - dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; - dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); - dma_config_linked_descriptor(context->dma_context.dma_ptr, tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS, dma_ch, &dma_ch_config); - - /* SPI CMD */ - dma_ch_config.size_in_byte = 1; - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); - dma_ch_config.src_width = DMA_TRANSFER_WIDTH_BYTE; - dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); - dma_config_linked_descriptor(context->dma_context.dma_ptr, tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1, dma_ch, &dma_ch_config); - - /* SPI DATA */ - dma_ch_config.size_in_byte = dma_transfer_size[i] << context->dma_context.data_width; - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_buff + tx_buff_index)); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); - dma_ch_config.src_width = context->dma_context.data_width; - dma_ch_config.dst_width = context->dma_context.data_width; - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - if (i == trans_count - 1) { - dma_ch_config.linked_ptr = 0; - } else { - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(tx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); - } - dma_config_linked_descriptor(context->dma_context.dma_ptr, tx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2, dma_ch, &dma_ch_config); - - tx_buff_index += temp32 * context->data_len_in_byte; - } -} - -void hpm_prepare_dma_rx_descriptors(spi_context_t *context, spi_control_config_t *config, uint32_t trans_count, - uint32_t *spi_transctrl, dma_linked_descriptor_t *rx_dma_descriptors) -{ - SPI_Type *ptr = context->ptr; - uint32_t dma_transfer_size[trans_count]; - uint32_t rx_count = context->rx_count; - uint32_t per_trans_size = context->per_trans_max; - uint32_t dma_ch = context->dma_context.rx_dma_ch; - uint8_t *rx_buff = context->rx_buff; - dma_channel_config_t dma_ch_config; - - static uint8_t dummy_cmd = 0xff; - - uint32_t temp32; - uint32_t rx_buff_index = 0; - - dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); - for (uint32_t i = 0; i < trans_count; i++) { - if (rx_count > per_trans_size) { - temp32 = per_trans_size; - rx_count -= per_trans_size; - } else { - temp32 = rx_count; - } - - *(spi_transctrl + i) = SPI_TRANSCTRL_TRANSMODE_SET(spi_trans_read_only) | - SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | - SPI_TRANSCTRL_WRTRANCNT_SET(temp32 - 1) | - SPI_TRANSCTRL_RDTRANCNT_SET(temp32 - 1); - dma_transfer_size[i] = temp32; - - /* SPI CTRL */ - dma_ch_config.size_in_byte = 4; - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(spi_transctrl + i)); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->TRANSCTRL); - dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; - dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1)); - dma_config_linked_descriptor(context->dma_context.dma_ptr, rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS, dma_ch, &dma_ch_config); - - /* SPI CMD */ - dma_ch_config.size_in_byte = 1; - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_cmd); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->CMD); - dma_ch_config.src_width = DMA_TRANSFER_WIDTH_BYTE; - dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_BYTE; - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2)); - dma_config_linked_descriptor(context->dma_context.dma_ptr, rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 1, dma_ch, &dma_ch_config); - - /* SPI DATA */ - dma_ch_config.size_in_byte = dma_transfer_size[i] << context->dma_context.data_width; - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&ptr->DATA); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_buff + rx_buff_index)); - dma_ch_config.src_width = context->dma_context.data_width; - dma_ch_config.dst_width = context->dma_context.data_width; - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - dma_ch_config.dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - dma_ch_config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - dma_ch_config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - if (i == trans_count - 1) { - dma_ch_config.linked_ptr = 0; - } else { - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(rx_dma_descriptors + (i + 1) * SPI_DMA_DESC_COUNT_PER_TRANS)); - } - dma_config_linked_descriptor(context->dma_context.dma_ptr, rx_dma_descriptors + i * SPI_DMA_DESC_COUNT_PER_TRANS + 2, dma_ch, &dma_ch_config); - - rx_buff_index += temp32 * context->data_len_in_byte; - } -} - -static uint32_t hpm_spi_get_trans_count(spi_context_t *context, spi_control_config_t *config) -{ - uint32_t total_trans_count, per_trans_count, trans_count; - - per_trans_count = context->per_trans_max; - if (config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write) { - total_trans_count = context->tx_count; - } else if (config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read) { - total_trans_count = context->rx_count; - } else { - /* write read together */ - assert(context->tx_count == context->rx_count); - total_trans_count = context->tx_count; - } - trans_count = (total_trans_count + per_trans_count - 1) / per_trans_count; - - return trans_count; -} - -/** - * spi with dma chain workflow - * - * 1. call spi_setup_dma_transfer to config SPI for first transmission - * 2. execute data transmission phase in dma chain descriptor - * 3. execute setting SPI CTRL register phase in dma chain descriptor - * 4. execute writing SPI CMD register phase in dma chain descriptor - * 5. Repeat steps 2-4 until finish the transmission - */ -static hpm_stat_t spi_setup_trans_with_dma_chain(spi_context_t *context, spi_control_config_t *config) -{ - hpm_stat_t stat = status_success; - SPI_Type *spi_ptr = context->ptr; - DMA_Type *dma_ptr = context->dma_context.dma_ptr; - DMAMUX_Type *dmamux_ptr = context->dma_context.dmamux_ptr; - dma_linked_descriptor_t *dma_linked_descriptor = context->dma_linked_descriptor; - uint32_t *spi_transctrl = context->spi_transctrl; - uint32_t dma_channel = 0; - uint32_t trans_count; - dma_channel_config_t dma_ch_config = {0}; - - /* use a dummy dma transfer to start SPI trans dma chain */ - static uint32_t dummy_data1 = 0xff, dummy_data2 = 0xff; - - trans_count = hpm_spi_get_trans_count(context, config); - - /* active spi cs pin */ - context->write_cs(context->cs_pin, SPI_CS_ACTIVE); - - /* config SPI for first dma transmission */ - stat = spi_setup_dma_transfer(spi_ptr, - config, - &context->cmd, - &context->addr, - MIN(context->tx_count, context->per_trans_max), - MIN(context->rx_count, context->per_trans_max)); - if (stat != status_success) { - return stat; - } - - if (config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write) { - /* write only */ - hpm_spi_prepare_dma_tx_descriptors(context, config, trans_count, spi_transctrl, dma_linked_descriptor); - dma_channel = context->dma_context.tx_dma_ch; - dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); - } else if (config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read) { - /* read only */ - hpm_prepare_dma_rx_descriptors(context, config, trans_count, spi_transctrl, dma_linked_descriptor); - dma_channel = context->dma_context.rx_dma_ch; - dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); - } else if (config->common_config.trans_mode == spi_trans_write_read_together) { - /* write and read together */ - hpm_spi_prepare_dma_tx_descriptors(context, config, trans_count, spi_transctrl, dma_linked_descriptor); - dma_channel = context->dma_context.tx_dma_ch; - dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); - dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); - /* spi tx use chained dma descriptor, spi rx use unchained dma */ - stat = hpm_spi_rx_trigger_dma(dma_ptr, - context->dma_context.rx_dma_ch, - spi_ptr, - core_local_mem_to_sys_address(context->running_core, (uint32_t)context->rx_buff), - context->dma_context.data_width, - context->rx_size); - if (stat != status_success) { - return stat; - } - } else { - return status_invalid_argument; - } - - dma_default_channel_config(context->dma_context.dma_ptr, &dma_ch_config); - dma_ch_config.src_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data1); - dma_ch_config.dst_addr = core_local_mem_to_sys_address(context->running_core, (uint32_t)&dummy_data2); - dma_ch_config.src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - dma_ch_config.src_width = DMA_TRANSFER_WIDTH_WORD; - dma_ch_config.dst_width = DMA_TRANSFER_WIDTH_WORD; - dma_ch_config.size_in_byte = 4; - /* start data transmission phase in dma chain */ - dma_ch_config.linked_ptr = core_local_mem_to_sys_address(context->running_core, (uint32_t)(dma_linked_descriptor + SPI_DMA_DESC_COUNT_PER_TRANS - 1)); - - stat = dma_setup_channel(dma_ptr, dma_channel, &dma_ch_config, true); - if (stat != status_success) { - return stat; - } - - return stat; -} - -static hpm_stat_t spi_setup_trans_with_dma(spi_context_t *context, spi_control_config_t *config) -{ - hpm_stat_t stat = status_success; - SPI_Type *spi_ptr = context->ptr; - DMA_Type *dma_ptr = context->dma_context.dma_ptr; - DMAMUX_Type *dmamux_ptr = context->dma_context.dmamux_ptr; - uint32_t trans_mode = config->common_config.trans_mode; - - if (context->write_cs != NULL) { - context->write_cs(context->cs_pin, SPI_CS_ACTIVE); - } - stat = spi_setup_dma_transfer(spi_ptr, config, - &context->cmd, &context->addr, - context->tx_count, context->rx_count); - if (stat != status_success) { - return stat; - } - - if (trans_mode != spi_trans_write_only && trans_mode != spi_trans_dummy_write && trans_mode != spi_trans_no_data) { - dmamux_config(dmamux_ptr, context->dma_context.rx_dmamux_ch, context->dma_context.rx_req, true); - stat = hpm_spi_rx_trigger_dma(dma_ptr, - context->dma_context.rx_dma_ch, - spi_ptr, - core_local_mem_to_sys_address(context->running_core, (uint32_t)context->rx_buff), - context->dma_context.data_width, - context->rx_size); - if (stat != status_success) { - return stat; - } - } - if (trans_mode != spi_trans_read_only && trans_mode != spi_trans_dummy_read && trans_mode != spi_trans_no_data) { - dmamux_config(dmamux_ptr, context->dma_context.tx_dmamux_ch, context->dma_context.tx_req, true); - stat = hpm_spi_tx_trigger_dma(dma_ptr, - context->dma_context.tx_dma_ch, - spi_ptr, - core_local_mem_to_sys_address(context->running_core, (uint32_t)context->tx_buff), - context->dma_context.data_width, - context->tx_size); - if (stat != status_success) { - return stat; - } - } - - return stat; -} - -hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config_t *config) -{ - assert(context != NULL || config != NULL); - /* use dma */ - assert(&context->dma_context != NULL); - /* spi per trans data size not zero */ - assert(context->per_trans_max); - - hpm_stat_t stat = status_success; - - if (l1c_dc_is_enabled()) { - /* cache writeback for tx buff */ - if (context->tx_buff != NULL && context->tx_size != 0) { - uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)context->tx_buff); - uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)context->tx_buff + context->tx_size); - uint32_t aligned_size = aligned_end - aligned_start; - l1c_dc_writeback(aligned_start, aligned_size); - } - /* cache invalidate for receive buff */ - if (context->rx_buff != NULL && context->rx_size != 0) { - uint32_t aligned_start = HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)context->rx_buff); - uint32_t aligned_end = HPM_L1C_CACHELINE_ALIGN_UP((uint32_t)context->rx_buff + context->rx_size); - uint32_t aligned_size = aligned_end - aligned_start; - l1c_dc_invalidate(aligned_start, aligned_size); - } - } - - if ((context->rx_count > context->per_trans_max) || (context->tx_count > context->per_trans_max)) { - /* multiple SPI transmissions with chained DMA */ - assert(config->common_config.trans_mode == spi_trans_read_only || config->common_config.trans_mode == spi_trans_dummy_read - || config->common_config.trans_mode == spi_trans_write_only || config->common_config.trans_mode == spi_trans_dummy_write - || config->common_config.trans_mode == spi_trans_write_read_together); - /* master mode */ - assert((context->ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) != SPI_TRANSFMT_SLVMODE_MASK); - /* GPIO should be used to replace SPI CS pin for SPI chained DMA transmissions */ - assert(context->write_cs != NULL); - - stat = spi_setup_trans_with_dma_chain(context, config); - } else { - /* one SPI transmissions with chained DMA */ - stat = spi_setup_trans_with_dma(context, config); - } - - return stat; -} - -/* Using GPIO as SPI CS pin */ -/* When SPI trans completed, GPIO cs pin should be released manually */ -hpm_stat_t hpm_spi_release_gpio_cs(spi_context_t *context) -{ - hpm_stat_t stat; - SPI_Type *ptr = context->ptr; - assert(context->write_cs != NULL); - - stat = spi_wait_for_idle_status(ptr); - if (stat != status_success) { - return stat; - } - - context->write_cs(context->cs_pin, !SPI_CS_ACTIVE); - return status_success; -} - -static hpm_stat_t wait_spi_slave_active(SPI_Type *ptr, bool active_status, uint32_t timeout) -{ - uint32_t ticks_per_us = (hpm_core_clock + 1000000 - 1U) / 1000000; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * timeout; - do { - if (hpm_csr_get_core_cycle() > expected_ticks) { - return status_timeout; - } - } while (spi_is_active(ptr) == !active_status); - return status_success; -} - -static hpm_spi_cfg_t *hpm_spi_get_cfg_obj(SPI_Type *ptr) -{ - hpm_spi_cfg_t *obj; - uint8_t i = 0; - for (i = 0; i < (sizeof(spi_dma_cfg_table) / sizeof(hpm_spi_cfg_t)); i++) { - obj = &spi_dma_cfg_table[i]; - if (obj->spi_ptr == ptr) { - return obj; - } - } - return NULL; -} - -static void hpm_spi_transfer_init(SPI_Type *ptr, spi_trans_mode_t mode, uint32_t size) -{ - uint32_t slv_mode = SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT); - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; - } - if (slv_mode == spi_master_mode) { - spi_set_transfer_mode(ptr, mode); - } else { - /* for slave mode, only support trans_write_read_together mode in only_data_mode */ - spi_set_transfer_mode(ptr, spi_trans_write_read_together); - } - if ((mode == spi_trans_write_read_together) || (slv_mode == spi_slave_mode)) { - spi_set_write_data_count(ptr, size / data_len_in_bytes); - spi_set_read_data_count(ptr, size / data_len_in_bytes); - } else if (mode == spi_trans_write_only) { - spi_set_write_data_count(ptr, size / data_len_in_bytes); - } else { - spi_set_read_data_count(ptr, size / data_len_in_bytes); - } - /* start new transmission, reset spi for slave*/ - if (slv_mode == spi_slave_mode) { - spi_reset(ptr); - } - spi_transmit_fifo_reset(ptr); - spi_receive_fifo_reset(ptr); - while (ptr->CTRL & (SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK)) { - } -} - -static hpm_stat_t write_read_data_together(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wsize, - uint8_t *rbuff, uint32_t rsize, uint32_t timeout) -{ - uint8_t txfifo_size = spi_get_tx_fifo_size(ptr); - uint32_t rx_index = 0, tx_index = 0; - uint8_t rxfifo_valid_size, txfifo_valid_size, j; - uint32_t ticks_per_us = (hpm_core_clock + 1000000 - 1U) / 1000000; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * timeout; - while ((rx_index < rsize) || (tx_index < wsize)) { - if (tx_index < wsize) { - txfifo_valid_size = spi_get_tx_fifo_valid_data_size(ptr); - if ((txfifo_size - txfifo_valid_size) > 0) { - for (j = 0; j < (txfifo_size - txfifo_valid_size); j++) { - if (tx_index >= wsize) { - break; - } - switch (data_len_in_bytes) { - case 1: - ptr->DATA = *(uint8_t *)wbuff; - break; - case 2: - ptr->DATA = *(uint16_t *)wbuff; - break; - default: - ptr->DATA = *(uint32_t *)wbuff; - break; - } - wbuff += data_len_in_bytes; - tx_index++; - } - } - } - if (rx_index < rsize) { - rxfifo_valid_size = spi_get_rx_fifo_valid_data_size(ptr); - if (rxfifo_valid_size > 0) { - for (j = 0; j < rxfifo_valid_size; j++) { - if (rx_index >= rsize) { - break; - } - switch (data_len_in_bytes) { - case 1: - *(uint8_t *)rbuff = (uint8_t)ptr->DATA; - break; - case 2: - *(uint16_t *)rbuff = (uint16_t)ptr->DATA; - break; - default: - *(uint32_t *)rbuff = ptr->DATA; - break; - } - rbuff += data_len_in_bytes; - rx_index++; - } - } - } - if (hpm_csr_get_core_cycle() > expected_ticks) { - return status_timeout; - } - } - return status_success; -} - -static hpm_stat_t read_data_single(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *rbuff, uint32_t rsize, uint32_t timeout) -{ - uint32_t rx_index = 0; - uint8_t rxfifo_valid_size, j; - uint32_t ticks_per_us = (hpm_core_clock + 1000000 - 1U) / 1000000; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * timeout; - while (rx_index < rsize) { - rxfifo_valid_size = spi_get_rx_fifo_valid_data_size(ptr); - if (rxfifo_valid_size > 0) { - for (j = 0; j < rxfifo_valid_size; j++) { - if (rx_index >= rsize) { - break; - } - switch (data_len_in_bytes) { - case 1: - *(uint8_t *)rbuff = (uint8_t)ptr->DATA; - break; - case 2: - *(uint16_t *)rbuff = (uint16_t)ptr->DATA; - break; - default: - *(uint32_t *)rbuff = ptr->DATA; - break; - } - rbuff += data_len_in_bytes; - rx_index++; - } - } - if (hpm_csr_get_core_cycle() > expected_ticks) { - return status_timeout; - } - } - return status_success; -} - -static hpm_stat_t write_data_single(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wsize, uint32_t timeout) -{ - uint8_t txfifo_size = spi_get_tx_fifo_size(ptr); - uint32_t tx_index = 0; - uint8_t txfifo_valid_size, j; - uint32_t ticks_per_us = (hpm_core_clock + 1000000 - 1U) / 1000000; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * timeout; - while (tx_index < wsize) { - txfifo_valid_size = spi_get_tx_fifo_valid_data_size(ptr); - if ((txfifo_size - txfifo_valid_size) > 0) { - for (j = 0; j < (txfifo_size - txfifo_valid_size); j++) { - if (tx_index >= wsize) { - break; - } - switch (data_len_in_bytes) { - case 1: - ptr->DATA = *(uint8_t *)wbuff; - break; - case 2: - ptr->DATA = *(uint16_t *)wbuff; - break; - default: - ptr->DATA = *(uint32_t *)wbuff; - break; - } - wbuff += data_len_in_bytes; - tx_index++; - } - } - if (hpm_csr_get_core_cycle() > expected_ticks) { - return status_timeout; - } - } - return status_success; -} - -void hpm_spi_get_default_init_config(spi_initialize_config_t *config) -{ - config->mode = spi_master_mode; - config->io_mode = spi_single_io_mode; - config->clk_polarity = spi_sclk_low_idle; - config->clk_phase = spi_sclk_sampling_odd_clk_edges; - config->data_len = 8; - config->data_merge = false; - config->direction = msb_first; -} - -hpm_stat_t hpm_spi_initialize(SPI_Type *ptr, spi_initialize_config_t *config) -{ - if (config->data_len == 0) { - return status_invalid_argument; - } - /* frist init TRANSFMT reg*/ - ptr->TRANSFMT = SPI_TRANSFMT_DATALEN_SET(config->data_len - 1) | - SPI_TRANSFMT_DATAMERGE_SET(config->data_merge) | - SPI_TRANSFMT_LSB_SET(config->direction) | - SPI_TRANSFMT_SLVMODE_SET(config->mode) | - SPI_TRANSFMT_CPOL_SET(config->clk_polarity) | - SPI_TRANSFMT_CPHA_SET(config->clk_phase); - /* second init TRANSCTRL reg - * default phase: disable command/address/token phase, - * default Transfer mode: write and read at the same time - */ - ptr->TRANSCTRL = SPI_TRANSCTRL_SLVDATAONLY_SET(1) | /* it's only data anyway for slave*/ - SPI_TRANSCTRL_DUALQUAD_SET(config->io_mode); - - /* third: init TIMING reg */ - ptr->TIMING = SPI_TIMING_CS2SCLK_SET(spi_cs2sclk_half_sclk_1) | - SPI_TIMING_CSHT_SET(spi_csht_half_sclk_1) | - SPI_TIMING_SCLK_DIV_SET(0x10); - return status_success; -} - -hpm_stat_t hpm_spi_set_sclk_frequency(SPI_Type *ptr, uint32_t freq) -{ - int freq_list[clock_source_general_source_end] = {0}; - int _freq = freq; - uint8_t i = 0; - int min_diff_freq; - int current_diff_freq; - int best_freq; - hpm_stat_t stat; - uint32_t div; - clock_source_t clock_source; - clk_src_t clk_src; - static spi_timing_config_t timing_config = {0}; - uint32_t pll_clk = 0; - hpm_spi_cfg_t *obj = hpm_spi_get_cfg_obj(ptr); - if (obj == NULL) { - return status_invalid_argument; - } - spi_master_get_default_timing_config(&timing_config); - timing_config.master_config.clk_src_freq_in_hz = clock_get_frequency(obj->spi_clock_name); - timing_config.master_config.sclk_freq_in_hz = freq; - timing_config.master_config.cs2sclk = spi_cs2sclk_half_sclk_1; - timing_config.master_config.csht = spi_csht_half_sclk_1; - stat = spi_master_timing_init(ptr, &timing_config); - if (stat != status_success) { - spi_master_set_sclk_div(ptr, 0xFF); - for (clock_source = (clock_source_t)0; clock_source < clock_source_general_source_end; clock_source++) { - pll_clk = get_frequency_for_source(clock_source); - div = pll_clk / freq; - /* The division factor ranges from 1 to 256 as any integer */ - if ((div > 0) && (div <= 0x100)) { - freq_list[clock_source] = pll_clk / div; - } - } - /* Find the best sclk frequency */ - min_diff_freq = abs(freq_list[0] - _freq); - best_freq = freq_list[0]; - for (i = 1; i < clock_source_general_source_end; i++) { - current_diff_freq = abs(freq_list[i] - _freq); - if (current_diff_freq < min_diff_freq) { - min_diff_freq = current_diff_freq; - best_freq = freq_list[i]; - } - } - /* Find the best spi clock frequency */ - for (i = 0; i < clock_source_general_source_end; i++) { - if (best_freq == freq_list[i]) { - pll_clk = get_frequency_for_source((clock_source_t)i); - clk_src = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, i); - div = pll_clk / best_freq; - clock_set_source_divider(obj->spi_clock_name, clk_src, div); - break; - } - } - stat = status_success; - } - return stat; -} - -hpm_stat_t hpm_spi_transmit_receive_blocking(SPI_Type *ptr, uint8_t *wbuff, uint8_t *rbuff, uint32_t size, uint32_t timeout) -{ - hpm_stat_t stat = status_success; - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - uint8_t txfifo_size = spi_get_tx_fifo_size(ptr); - uint8_t remain_size = 0, j = 0; - uint32_t temp, count; - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - } - if ((wbuff == NULL) || (rbuff == NULL) || (size == 0) || - ((SPI_SOC_TRANSFER_COUNT_MAX == 512) && (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes))) || - (spi_master_get_data_phase_format(ptr) != spi_single_io_mode)) { - return status_invalid_argument; - } - count = (size / data_len_in_bytes); - hpm_spi_transfer_init(ptr, spi_trans_write_read_together, size); - /* for master mode, This CMD register must be written with a dummy value - * to start a SPI transfer even when the command phase is not enabled - */ - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - ptr->CMD = 0xFF; - stat = write_read_data_together(ptr, data_len_in_bytes, wbuff, count, rbuff, count, timeout); - if (stat == status_success) { - /* waiting....in master mode, becomes 0 after the transfer is finished */ - stat = wait_spi_slave_active(ptr, false, timeout); - } - } else { - /* Before receiving the host to start transmission, fill the TX FIFO */ - remain_size = txfifo_size - spi_get_tx_fifo_valid_data_size(ptr); - for (j = 0; j < remain_size; j++) { - temp = 0; - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - temp += *(wbuff++) << i * 8; - } - ptr->DATA = temp; - } - count -= remain_size; - /* waiting....in slave mode, becomes 1 after the SPI CS signal is asserted */ - stat = wait_spi_slave_active(ptr, true, timeout); - /* no need to read RXFIFO because no effect SPI bus for slave mode */ - if (((size - remain_size) > 0) && (stat == status_success)) { - stat = write_read_data_together(ptr, data_len_in_bytes, wbuff, count, rbuff, count + remain_size, timeout); - } - } - return stat; -} - -hpm_stat_t hpm_spi_receive_blocking(SPI_Type *ptr, uint8_t *buff, uint32_t size, uint32_t timeout) -{ - hpm_stat_t stat = status_success; - uint32_t count; - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - } - if ((buff == NULL) || (size == 0) || - ((SPI_SOC_TRANSFER_COUNT_MAX == 512) && (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)))) { - return status_invalid_argument; - } - count = (size / data_len_in_bytes); - hpm_spi_transfer_init(ptr, spi_trans_read_only, size); - /* for master mode, This CMD register must be written with a dummy value - * to start a SPI transfer even when the command phase is not enabled - */ - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - ptr->CMD = 0xFF; - } else { - /* waiting....in slave mode, becomes 1 after the SPI CS signal is asserted */ - stat = wait_spi_slave_active(ptr, true, timeout); - } - /* no need to write TXFIFO because no effect SPI bus for slave mode */ - if (stat == status_success) { - stat = read_data_single(ptr, data_len_in_bytes, buff, count, timeout); - } - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - /* waiting....in master mode, becomes 0 after the transfer is finished */ - if (stat == status_success) { - stat = wait_spi_slave_active(ptr, false, timeout); - } - } - return stat; -} - -hpm_stat_t hpm_spi_transmit_blocking(SPI_Type *ptr, uint8_t *buff, uint32_t size, uint32_t timeout) -{ - hpm_stat_t stat = status_success; - uint8_t txfifo_size = spi_get_tx_fifo_size(ptr); - uint8_t remain_size = 0, j = 0; - uint32_t temp, count; - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - } - if ((buff == NULL) || (size == 0) || - ((SPI_SOC_TRANSFER_COUNT_MAX == 512) && (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)))) { - return status_invalid_argument; - } - count = (size / data_len_in_bytes); - hpm_spi_transfer_init(ptr, spi_trans_write_only, size); - /* for master mode, This CMD register must be written with a dummy value - * to start a SPI transfer even when the command phase is not enabled - */ - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - ptr->CMD = 0xFF; - stat = write_data_single(ptr, data_len_in_bytes, buff, count, timeout); - if (stat == status_success) { - /* waiting....in master mode, becomes 0 after the transfer is finished */ - stat = wait_spi_slave_active(ptr, false, timeout); - } - } else { - /* Before receiving the host to start transmission, fill the TX FIFO */ - remain_size = txfifo_size - spi_get_tx_fifo_valid_data_size(ptr); - for (j = 0; j < remain_size; j++) { - temp = 0; - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - temp += *(buff++) << i * 8; - } - ptr->DATA = temp; - } - count -= remain_size; - /* waiting....in slave mode, becomes 1 after the SPI CS signal is asserted */ - stat = wait_spi_slave_active(ptr, true, timeout); - /* no need to read RXFIFO because no effect SPI bus for slave mode */ - if ((count > 0) && (stat == status_success)) { - stat = write_data_single(ptr, data_len_in_bytes, buff, count, timeout); - } - } - return stat; -} - -hpm_stat_t hpm_spi_transmit_receive_setup_dma(SPI_Type *ptr, uint32_t size) -{ - hpm_stat_t stat = status_success; - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - } - if ((size == 0) || - ((SPI_SOC_TRANSFER_COUNT_MAX == 512) && (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)))) { - return status_invalid_argument; - } - hpm_spi_transfer_init(ptr, spi_trans_write_read_together, size); - spi_enable_tx_dma(ptr); - spi_enable_rx_dma(ptr); - /* for master mode, This CMD register must be written with a dummy value - * to start a SPI transfer even when the command phase is not enabled - */ - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - ptr->CMD = 0xFF; - } - return stat; -} - -hpm_stat_t hpm_spi_receive_setup_dma(SPI_Type *ptr, uint32_t size) -{ - hpm_stat_t stat = status_success; - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - } - if ((size == 0) || - ((SPI_SOC_TRANSFER_COUNT_MAX == 512) && (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)))) { - return status_invalid_argument; - } - hpm_spi_transfer_init(ptr, spi_trans_read_only, size); - spi_disable_tx_dma(ptr); - spi_enable_rx_dma(ptr); - /* for master mode, This CMD register must be written with a dummy value - to start a SPI transfer even when the command phase is not enabled - */ - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - ptr->CMD = 0xFF; - } - return stat; -} - -hpm_stat_t hpm_spi_transmit_setup_dma(SPI_Type *ptr, uint32_t size) -{ - hpm_stat_t stat = status_success; - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - } - if ((size == 0) || - ((SPI_SOC_TRANSFER_COUNT_MAX == 512) && (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)))) { - return status_invalid_argument; - } - hpm_spi_transfer_init(ptr, spi_trans_write_only, size); - spi_enable_tx_dma(ptr); - spi_disable_rx_dma(ptr); - /* for master mode, This CMD register must be written with a dummy value - * to start a SPI transfer even when the command phase is not enabled - */ - if (SPI_TRANSFMT_SLVMODE_GET(ptr->TRANSFMT) == spi_master_mode) { - ptr->CMD = 0xFF; - } - return stat; -} - -#if USE_DMA_MGR -void dma_channel_tc_callback(DMA_Type *ptr, uint32_t channel, void *user_data) -{ - hpm_spi_cfg_t *obj = (hpm_spi_cfg_t *)user_data; - if ((obj->rxdma_resource.channel == channel) && - (obj->rxdma_resource.base == ptr) && - (obj->rx_dma_complete != NULL)) { - obj->rx_dma_complete(channel); - } - if ((obj->txdma_resource.channel == channel) && - (obj->txdma_resource.base == ptr) && - (obj->tx_dma_complete != NULL)) { - obj->tx_dma_complete(channel); - } -} - -hpm_stat_t hpm_spi_dma_install_callback(SPI_Type *ptr, spi_dma_complete_cb tx_complete, spi_dma_complete_cb rx_complete) -{ - dma_mgr_chn_conf_t chg_config; - dma_resource_t *resource = NULL; - hpm_spi_cfg_t *obj = hpm_spi_get_cfg_obj(ptr); - if (obj == NULL) { - return status_invalid_argument; - } - dma_mgr_get_default_chn_config(&chg_config); - chg_config.src_width = DMA_MGR_TRANSFER_WIDTH_BYTE; - chg_config.dst_width = DMA_MGR_TRANSFER_WIDTH_BYTE; - /* spi rx dma config */ - resource = &obj->rxdma_resource; - if (dma_mgr_request_resource(resource) == status_success) { - chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; - chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; - chg_config.src_addr = (uint32_t)&ptr->DATA; - chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; - chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; - chg_config.en_dmamux = true; - chg_config.dmamux_src = obj->rx_dmamux_src; - dma_mgr_setup_channel(resource, &chg_config); - dma_mgr_install_chn_tc_callback(resource, dma_channel_tc_callback, (void *)obj); - dma_mgr_enable_chn_irq(resource, DMA_MGR_INTERRUPT_MASK_TC); - dma_mgr_enable_dma_irq_with_priority(resource, 1); - obj->rx_dma_complete = rx_complete; - } - /* spi tx dma config */ - resource = &obj->txdma_resource; - if (dma_mgr_request_resource(resource) == status_success) { - chg_config.src_mode = DMA_MGR_HANDSHAKE_MODE_NORMAL; - chg_config.src_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_INCREMENT; - chg_config.dst_mode = DMA_MGR_HANDSHAKE_MODE_HANDSHAKE; - chg_config.dst_addr_ctrl = DMA_MGR_ADDRESS_CONTROL_FIXED; - chg_config.dst_addr = (uint32_t)&ptr->DATA; - chg_config.en_dmamux = true; - chg_config.dmamux_src = obj->tx_dmamux_src; - dma_mgr_setup_channel(resource, &chg_config); - dma_mgr_install_chn_tc_callback(resource, dma_channel_tc_callback, (void *)obj); - dma_mgr_enable_chn_irq(resource, DMA_MGR_INTERRUPT_MASK_TC); - dma_mgr_enable_dma_irq_with_priority(resource, 1); - obj->tx_dma_complete = tx_complete; - } - return status_success; -} - -hpm_stat_t hpm_spi_transmit_receive_nonblocking(SPI_Type *ptr, uint8_t *wbuff, uint8_t *rbuff, uint32_t size) -{ - hpm_stat_t stat = status_success; - uint8_t transfer_width; - dma_resource_t *resource; - uint32_t buf_addr; - hpm_spi_cfg_t *obj = hpm_spi_get_cfg_obj(ptr); - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - /* word */ - transfer_width = DMA_MGR_TRANSFER_WIDTH_WORD; - data_len_in_bytes = 4; /* must be 4 aglin */ - } else { - /* byte or half_word*/ - transfer_width = data_len_in_bytes - 1; - } - if ((obj == NULL) || - (spi_master_get_data_phase_format(ptr) != spi_single_io_mode) || - (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes))) { - return status_invalid_argument; - } - spi_disable_rx_dma(ptr); - spi_disable_tx_dma(ptr); - spi_transmit_fifo_reset(ptr); - spi_receive_fifo_reset(ptr); - resource = &obj->rxdma_resource; - buf_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)rbuff); - dma_mgr_set_chn_dst_width(resource, transfer_width); - dma_mgr_set_chn_src_width(resource, transfer_width); - dma_mgr_set_chn_dst_addr(resource, buf_addr); - dma_mgr_set_chn_transize(resource, size / data_len_in_bytes); - dma_mgr_enable_channel(resource); - resource = &obj->txdma_resource; - buf_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)wbuff); - dma_mgr_set_chn_dst_width(resource, transfer_width); - dma_mgr_set_chn_src_width(resource, transfer_width); - dma_mgr_set_chn_src_addr(resource, buf_addr); - dma_mgr_set_chn_transize(resource, size / data_len_in_bytes); - dma_mgr_enable_channel(resource); - stat = hpm_spi_transmit_receive_setup_dma(ptr, size); - return stat; -} - -hpm_stat_t hpm_spi_receive_nonblocking(SPI_Type *ptr, uint8_t *buff, uint32_t size) -{ - hpm_stat_t stat = status_success; - uint8_t transfer_width; - dma_resource_t *resource; - uint32_t buf_addr; - hpm_spi_cfg_t *obj = hpm_spi_get_cfg_obj(ptr); - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - /* word */ - transfer_width = DMA_MGR_TRANSFER_WIDTH_WORD; - } else { - /* byte or half_word*/ - transfer_width = data_len_in_bytes - 1; - } - if ((obj == NULL) || - ((size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes)))) { - return status_invalid_argument; - } - spi_disable_rx_dma(ptr); - spi_disable_tx_dma(ptr); - spi_transmit_fifo_reset(ptr); - spi_receive_fifo_reset(ptr); - resource = &obj->rxdma_resource; - buf_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)buff); - dma_mgr_set_chn_dst_width(resource, transfer_width); - dma_mgr_set_chn_src_width(resource, transfer_width); - dma_mgr_set_chn_dst_addr(resource, buf_addr); - dma_mgr_set_chn_transize(resource, size / data_len_in_bytes); - dma_mgr_enable_channel(resource); - stat = hpm_spi_receive_setup_dma(ptr, size); - return stat; -} - -hpm_stat_t hpm_spi_transmit_nonblocking(SPI_Type *ptr, uint8_t *buff, uint32_t size) -{ - hpm_stat_t stat = status_success; - uint8_t transfer_width; - dma_resource_t *resource; - uint32_t buf_addr; - hpm_spi_cfg_t *obj = hpm_spi_get_cfg_obj(ptr); - uint8_t data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - if (data_len_in_bytes > 2) { - data_len_in_bytes = 4; /* must be 4 aglin */ - /* word */ - transfer_width = DMA_MGR_TRANSFER_WIDTH_WORD; - } else { - /* byte or half_word*/ - transfer_width = data_len_in_bytes - 1; - } - if ((obj == NULL) || - (size > (SPI_SOC_TRANSFER_COUNT_MAX * data_len_in_bytes))) { - return status_invalid_argument; - } - resource = &obj->txdma_resource; - buf_addr = core_local_mem_to_sys_address(HPM_CORE0, (uint32_t)buff); - spi_disable_rx_dma(ptr); - spi_disable_tx_dma(ptr); - spi_transmit_fifo_reset(ptr); - spi_receive_fifo_reset(ptr); - dma_mgr_set_chn_src_addr(resource, buf_addr); - dma_mgr_set_chn_dst_width(resource, transfer_width); - dma_mgr_set_chn_src_width(resource, transfer_width); - dma_mgr_set_chn_transize(resource, size / data_len_in_bytes); - dma_mgr_enable_channel(resource); - stat = hpm_spi_transmit_setup_dma(ptr, size); - return stat; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h b/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h deleted file mode 100644 index 0e1e14a0141..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_COMPONENT_SPI_H -#define HPM_COMPONENT_SPI_H - -#include "hpm_common.h" -#include "hpm_spi_drv.h" -#ifdef HPMSOC_HAS_HPMSDK_DMAV2 -#include "hpm_dmav2_drv.h" -#else -#include "hpm_dma_drv.h" -#endif -#include "hpm_dmamux_drv.h" -#include "hpm_misc.h" -#include "hpm_l1c_drv.h" - -#ifndef SPI_CS_ACTIVE -#define SPI_CS_ACTIVE 0 -#endif - -#ifndef USE_DMA_MGR -#define USE_DMA_MGR (0U) -#endif - -/* Every transaction can be delineated by 3 dma descriptions: SPI control, SPI cmd, SPI data */ -#define SPI_DMA_DESC_COUNT_PER_TRANS (3U) - -typedef struct { - DMA_Type *dma_ptr; - DMAMUX_Type *dmamux_ptr; - uint8_t rx_dma_ch; - uint8_t tx_dma_ch; - uint8_t rx_dmamux_ch; - uint8_t tx_dmamux_ch; - uint8_t rx_req; - uint8_t tx_req; - uint8_t data_width; -} spi_dma_context_t; - -typedef struct { - SPI_Type *ptr; - uint32_t cs_pin; - uint8_t cmd; - uint8_t *rx_buff; - uint8_t *tx_buff; - uint8_t running_core; - uint32_t addr; - uint32_t rx_size; - uint32_t rx_count; - uint32_t tx_size; - uint32_t tx_count; - uint32_t data_len_in_byte; - uint32_t per_trans_max; - uint32_t *spi_transctrl; - void (*write_cs)(uint32_t cs_pin, uint8_t state); - spi_dma_context_t dma_context; - dma_linked_descriptor_t *dma_linked_descriptor; -} spi_context_t; - -/** - * @brief spi configuration init structure - */ -typedef struct { - spi_mode_selection_t mode; /*!< the spi operating mode */ - spi_data_phase_format_t io_mode; /*!< the spi data line mode */ - spi_sclk_idle_state_t clk_polarity; /*!< CPOL */ - spi_sclk_sampling_clk_edges_t clk_phase; /*!< CPHA */ - spi_shift_direction_t direction; /*!< MSB or LSB data shift direction */ - uint8_t data_len; /*!< the unit is bit (1~32bit) */ - bool data_merge; /*!< data Merge mode*/ -} spi_initialize_config_t; - -#if USE_DMA_MGR -typedef void (*spi_dma_complete_cb)(uint32_t channel); -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief hpm_spi setup dma transfer - * - * @note if the transferred data count more than SPI_SOC_TRANSFER_COUNT_MAX, this API will using - * DMA chain descriptors to link SPI transmission. - * - * @param[in] spi_context A pointer to the struct of "spi_context_t" - * @param[in] spi_config A pointer to the struct of "spi_control_config_t" - * @retval status_success if SPI transfers data successfully. - */ -hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config_t *config); - -/* - * SPI release gpio pin if gpio use for SPI CS function - */ -/** - * @brief hpm_spi releases gpio cs pin after SPI transfer completed - * - * @param[in] spi_context A pointer to the struct of "spi_context_t" - * @retval status_success if SPI releases gpio cs pin successfully. - */ -hpm_stat_t hpm_spi_release_gpio_cs(spi_context_t *context); - - -/** - * @brief spi get default init config - * - * @note it's no command/address/token phase, only data phase. - * - * @param [out] config spi_init_config_t - */ -void hpm_spi_get_default_init_config(spi_initialize_config_t *config); - -/** - * @brief initialize for spi - * - * @note it's no command/address/token phase, only data phase. - * - * @param [in] ptr SPI base address - * @param [in] config spi_init_config_t struct - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_initialize(SPI_Type *ptr, spi_initialize_config_t *config); - -/** - * @brief set spi sclk frequency for spi master - * - * @param [in] ptr SPI base address - * @param [in] freq spi sclk frequency - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_set_sclk_frequency(SPI_Type *ptr, uint32_t freq); - -/** - * @brief transmit and receive block for spi - * - * @note it's no command/address/token phase, only data phase. - * - * @param [in] ptr SPI base address - * @param [in] wbuff spi sent data buff address - * @param [out] rbuff spi receive data buff address - * @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [in] timeout wait time. unit is millisecond - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_transmit_receive_blocking(SPI_Type *ptr, uint8_t *wbuff, uint8_t *rbuff, uint32_t size, uint32_t timeout); - -/** - * @brief receive block for spi - * - * @note it's no command/address/token phase, only data phase. - * - * @param [in] ptr SPI base address - * @param [out] buff spi receive data buff address - * @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [in] timeout wait time. unit is millisecond - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_receive_blocking(SPI_Type *ptr, uint8_t *buff, uint32_t size, uint32_t timeout); - -/** - * @brief transmit block for spi - * - * @note it's no command/address/token phase, only data phase. - * - * @param [in] ptr SPI base address - * @param [in] buff spi sent data buff address - * @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [in] timeout wait time. unit is millisecond - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_transmit_blocking(SPI_Type *ptr, uint8_t *buff, uint32_t size, uint32_t timeout); - -/** - * @brief transmit and receive setup dma for spi - * - * @note it's no command/address/token phase, only data phase. - * main configuration spi dma related, call this API after configuring DMA best - * - * @param [in] ptr SPI base address - * @param [in] size spi sent and receive data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_transmit_receive_setup_dma(SPI_Type *ptr, uint32_t size); - -/** - * @brief receive setup dma for spi - * - * @note it's no command/address/token phase, only data phase. - * main configuration spi dma related, call this API after configuring DMA best - * - * @param [in] ptr SPI base address - * @param [in] size spi receive data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_receive_setup_dma(SPI_Type *ptr, uint32_t size); - -/** - * @brief transmit setup dma for spi - * - * @note it's no command/address/token phase, only data phase. - * main configuration spi dma related, call this API after configuring DMA best - * - * @param [in] ptr SPI base address - * @param [in] size spi transmit data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_transmit_setup_dma(SPI_Type *ptr, uint32_t size); - -#if USE_DMA_MGR -/** - * @brief Install callback for SPI DMA channel transmit and receive complete - * - * @note it's no command/address/token phase, only data phase. - * - * @param [in] ptr SPI base address - * @param [in] tx_complete callback for SPI TX DMA - * @param [in] rx_complete callback for SPI RX DMA - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_dma_install_callback(SPI_Type *ptr, - spi_dma_complete_cb tx_complete, - spi_dma_complete_cb rx_complete); - -/** - * @brief transmit and receive noblock for spi - * - * @note it's no command/address/token phase, only data phase. use dma - * - * @param [in] ptr SPI base address - * @param [in] wbuff spi sent data buff address - * @param [out] rbuff spi receive data buff address - * @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_transmit_receive_nonblocking(SPI_Type *ptr, uint8_t *wbuff, uint8_t *rbuff, uint32_t size); - -/** - * @brief receive noblock for spi - * - * @note it's no command/address/token phase, only data phase. use dma - * - * @param [in] ptr SPI base address - * @param [out] buff spi receive data buff address - * @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_receive_nonblocking(SPI_Type *ptr, uint8_t *buff, uint32_t size); - -/** - * @brief transmit noblock for spi - * - * @note it's no command/address/token phase, only data phase. use dma - * - * @param [in] ptr SPI base address - * @param [in] buff spi sent data buff address - * @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t hpm_spi_transmit_nonblocking(SPI_Type *ptr, uint8_t *buff, uint32_t size); - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_COMPONENT_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c deleted file mode 100644 index d42fd6eb38c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ft5406.h" - -hpm_stat_t ft5406_read_register(ft5406_context_t *context, uint8_t reg, uint8_t *buf) -{ - return i2c_master_address_read(context->ptr, FT5406_I2C_ADDR, ®, 1, buf, 1); -} - -hpm_stat_t ft5406_write_register(ft5406_context_t *context, uint8_t reg, uint8_t val) -{ - return i2c_master_address_write(context->ptr, FT5406_I2C_ADDR, ®, 1, &val, 1); -} - -hpm_stat_t ft5406_set_mode(ft5406_context_t *context, uint8_t mode) -{ - return ft5406_write_register(context, FT5406_DEVICE_MODE, 1); -} - -hpm_stat_t ft5406_init(ft5406_context_t *context) -{ - return ft5406_set_mode(context, FT5406_DEVICE_MODE_NORMAL); -} - -hpm_stat_t ft5406_get_sys_info(ft5406_context_t *context, ft5406_sys_info_t *info) -{ - hpm_stat_t stat = status_success; - uint8_t reg_addr = FT5406_DEVICE_MODE; - - stat = ft5406_set_mode(context, FT5406_DEVICE_MODE_SYS_INFO); - if (stat != status_success) { - return stat; - } - return i2c_master_address_read(context->ptr, FT5406_I2C_ADDR, ®_addr, 1, (uint8_t *)info, sizeof(ft5406_sys_info_t)); -} - -hpm_stat_t ft5406_read_data(ft5406_context_t *context, uint8_t addr, uint8_t *buf, uint32_t size) -{ - return i2c_master_address_read(context->ptr, FT5406_I2C_ADDR, &addr, 1, buf, size); -} - -hpm_stat_t ft5406_read_touch_data(ft5406_context_t *context, ft5406_touch_data_t *touch_data) -{ - return ft5406_read_data(context, FT5406_GEST_ID, (uint8_t *)touch_data, sizeof(ft5406_touch_data_t)); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h deleted file mode 100644 index 3cc2fe29392..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_ft5406.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_FT5406_H -#define HPM_FT5406_H -#include "hpm_common.h" -#include "hpm_i2c_drv.h" - -#define FT5406_I2C_ADDR (0x38U) - -/* - * FT5406 registers at operation mode - */ -#define FT5406_DEVICE_MODE (0U) -#define FT5406_GEST_ID (0x1U) -#define FT5406_TD_STATUS (0x2U) -#define FT5406_TOUCH1_XH (0x3U) -#define FT5406_TOUCH1_XL (0x4U) -#define FT5406_TOUCH1_YH (0x5U) -#define FT5406_TOUCH1_YL (0x6U) - -#define FT5406_TOUCH2_XH (0x9U) -#define FT5406_TOUCH2_XL (0xAU) -#define FT5406_TOUCH2_YH (0xBU) -#define FT5406_TOUCH2_YL (0xCU) - -#define FT5406_TOUCH3_XH (0xFU) -#define FT5406_TOUCH3_XL (0x10U) -#define FT5406_TOUCH3_YH (0x11U) -#define FT5406_TOUCH3_YL (0x12U) - -#define FT5406_TOUCH4_XH (0x15U) -#define FT5406_TOUCH4_XL (0x16U) -#define FT5406_TOUCH4_YH (0x17U) -#define FT5406_TOUCH4_YL (0x18U) - -#define FT5406_TOUCH5_XH (0x1BU) -#define FT5406_TOUCH5_XL (0x1CU) -#define FT5406_TOUCH5_YH (0x1DU) -#define FT5406_TOUCH5_YL (0x1EU) - -#define FT5406_ID_G_THGROUP (0x80U) -#define FT5406_ID_G_THPEAK (0x81U) -#define FT5406_ID_G_THCAL (0x82U) -#define FT5406_ID_G_THWARTER (0x83U) -#define FT5406_ID_G_THTEMP (0x84U) - -#define FT5406_ID_G_CTRL (0x86U) -#define FT5406_ID_G_TIME_ENTER_MONITOR (0x87U) -#define FT5406_ID_G_PERIODACTIVE (0x88U) -#define FT5406_ID_G_PERIODMONITOR (0x89U) - -#define FT5406_ID_G_AUTO_CLB_MODE (0xA0U) -#define FT5406_ID_G_LIB_VERSION_H (0xA1U) -#define FT5406_ID_G_LIB_VERSION_L (0xA2U) -#define FT5406_ID_G_CIPHER (0xA3U) -#define FT5406_ID_G_MODE (0xA4U) -#define FT5406_ID_G_PMODE (0xA5U) -#define FT5406_ID_G_FIRM_ID (0xA6U) -#define FT5406_ID_G_STATE (0xA7U) -#define FT5406_ID_G_FT5201ID (0xA8U) -#define FT5406_ID_G_ERR (0xA9U) -#define FT5406_ID_G_CLB (0xAAU) -#define FT5406_ID_G_B_AREA_TH (0xAEU) - -#define FT5406_DEVICE_MODE_NORMAL (0) -#define FT5406_DEVICE_MODE_SYS_INFO (1U) -#define FT5406_DEVICE_MODE_TEST (2U) - -#define FT5406_STATUS_CONFIGURE (0) -#define FT5406_STATUS_WORK (1U) -#define FT5406_STATUS_CALIBRATION (2U) -#define FT5406_STATUS_FACTORY (3U) -#define FT5406_STATUS_AUTO_CALIBRATION (4U) - -#define FT5406_GESTURE_NO_GESTURE (0) -#define FT5406_GESTURE_MOVE_UP (0x10U) -#define FT5406_GESTURE_MOVE_LEFT (0x14U) -#define FT5406_GESTURE_MOVE_DOWN (0x18U) -#define FT5406_GESTURE_MOVE_RIGHT (0x1CU) -#define FT5406_GESTURE_ZOOM_IN (0x48U) -#define FT5406_GESTURE_ZOOM_OUT (0x49U) - -#define FT5406_MAX_TOUCH_POINTS (5U) - -typedef struct { - uint8_t x_h; - uint8_t x_l; - uint8_t y_h; - uint8_t y_l; - uint16_t reserved; -} ft5406_touch_point_t; - -typedef struct { - uint8_t gesture; - uint8_t status; - ft5406_touch_point_t points[FT5406_MAX_TOUCH_POINTS]; -} ft5406_touch_data_t; - -typedef struct { - I2C_Type *ptr; -} ft5406_context_t; - -typedef struct { - uint8_t mode; - uint8_t bist_comm; - uint8_t bist_stat; - uint8_t reserved0[4]; - uint8_t uid[8]; - uint8_t bl_verh; - uint8_t bl_verl; - uint8_t fts_ic_verh; - uint8_t fts_ic_verl; - uint8_t app_idh; - uint8_t app_idl; - uint8_t app_verh; - uint8_t app_verl; - uint8_t reserved1[4]; - uint8_t cid[5]; -} ft5406_sys_info_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * ft5406 initialization routine - */ -hpm_stat_t ft5406_init(ft5406_context_t *context); - -/* - * ft5406 set working mode - */ -hpm_stat_t ft5406_set_mode(ft5406_context_t *context, uint8_t mode); - -/* - * ft5406 get system information - */ -hpm_stat_t ft5406_get_sys_info(ft5406_context_t *context, - ft5406_sys_info_t *info); - -/* - * ft5406 read touch data - */ -hpm_stat_t ft5406_read_touch_data(ft5406_context_t *context, - ft5406_touch_data_t *touch_data); - -/* - * ft5406 read data - */ -hpm_stat_t ft5406_read_data(ft5406_context_t *context, uint8_t addr, - uint8_t *buf, uint32_t size); - -/* - * ft5406 write value to given register - */ -hpm_stat_t ft5406_write_register(ft5406_context_t *context, - uint8_t reg, uint8_t val); - -/* - * ft5406 read value of given register - */ -hpm_stat_t ft5406_read_register(ft5406_context_t *context, uint8_t reg, uint8_t *buf); - -#ifdef __cplusplus -} -#endif -#endif /* HPM_FT5406_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c deleted file mode 100644 index b7d0296355e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_touch.h" -ft5406_context_t ft5406 = {0}; - -hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) -{ - hpm_stat_t stat = status_success; - uint8_t i = 0; - ft5406_touch_data_t touch_data = {0}; - - stat = ft5406_read_touch_data(&ft5406, &touch_data); - if (stat != status_success) { - return stat; - } - - if ((touch_data.status < FT5406_MAX_TOUCH_POINTS) && (touch_data.status)) { - for (i = 0; touch_data.points[i].x_h > 0 && touch_data.points[i].x_h < 0xFF; i++) { - points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; - points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; - } - } - - *num_of_points = i; - return stat; -} - -hpm_stat_t touch_init(I2C_Type *i2c_ptr) -{ - hpm_stat_t stat; - - ft5406.ptr = i2c_ptr; - stat = ft5406_init(&ft5406); - if (stat != status_success) { - return stat; - } - -#ifdef USE_CAP_INT - stat = ft5406_write_register(&ft5406, FT5406_ID_G_MODE, 0); - if (stat != status_success) { - return stat; - } - cap_int_setup(); -#endif - return stat; -} - -hpm_stat_t touch_config(bool exchange_xy, bool reverse_x, bool reverse_y) -{ - return status_fail; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c deleted file mode 100644 index 26fdabfc706..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_gt911.h" -static uint8_t g_i2c_addr; - -hpm_stat_t gt911_read_data(gt911_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) -{ - uint8_t r[2]; - r[0] = addr >> 8; - r[1] = addr & 0xFF; - return i2c_master_address_read(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); -} - -hpm_stat_t gt911_write_data(gt911_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) -{ - uint8_t r[2]; - r[0] = addr >> 8; - r[1] = addr & 0xFF; - - return i2c_master_address_write(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); -} - -hpm_stat_t gt911_read_register(gt911_context_t *context, uint16_t reg, uint8_t *buf) -{ - return gt911_read_data(context, reg, buf, 1); -} - -hpm_stat_t gt911_write_register(gt911_context_t *context, uint16_t reg, uint8_t val) -{ - return gt911_write_data(context, reg, &val, 1); -} - -hpm_stat_t gt911_soft_reset(gt911_context_t *context) -{ - return gt911_write_register(context, GT911_CMD, 0); -} - -static uint8_t gt911_calcualte_config_data_checksum(uint8_t *config) -{ - uint8_t checksum = 0; - for (uint32_t i = 0; i < GT911_CONFIG_DATA_SIZE - 2; i++) { - checksum += config[i]; - } - return (~checksum + 1); -} - -hpm_stat_t gt911_read_config(gt911_context_t *context, uint8_t *buf, uint8_t size) -{ - return gt911_read_data(context, GT911_CONFIG, buf, size); -} - -hpm_stat_t gt911_init(gt911_context_t *context, uint16_t width, uint16_t height) -{ - hpm_stat_t stat = status_success; - uint8_t config[GT911_CONFIG_DATA_SIZE] = {0}; - -#ifdef GT911_I2C_ADDR - g_i2c_addr = GT911_I2C_ADDR; - stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); - if (stat != status_success) { - return stat; - } -#elif !GT911_NO_AUTO_PROBE - g_i2c_addr = GT911_I2C_ADDR0; - stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); - if (stat != status_success) { - printf("0x%x failed to init GT911", g_i2c_addr); - g_i2c_addr = GT911_I2C_ADDR1; - printf(", try 0x%x\n", g_i2c_addr); - stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); - } - if (stat != status_success) { - return stat; - } -#else - g_i2c_addr = GT911_I2C_ADDR0; - stat = gt911_read_data(context, GT911_CONFIG, config, sizeof(config)); - if (stat != status_success) { - return stat; - } -#endif - - if (config[GT911_CONFIG_DATA_SIZE - 2] != gt911_calcualte_config_data_checksum(config)) { - return status_fail; - } - - /* stat = gt911_read_data(context, GT911_ID_B0, (uint8_t*)&val, sizeof(val)); */ - /* if (stat != status_success) { */ - /* return stat; */ - /* } */ - - /* if (val != GT911_PRODUCT_ID) { */ - /* return status_fail; */ - /* } */ - - config[GT911_CONFIG_DATA_RESOLUTION_XL] = width & 0xFF; - config[GT911_CONFIG_DATA_RESOLUTION_XH] = width >> 8; - config[GT911_CONFIG_DATA_RESOLUTION_YL] = height & 0xFF; - config[GT911_CONFIG_DATA_RESOLUTION_YH] = height >> 8; - config[GT911_CONFIG_DATA_TOUCH_NUMBER] = 5; - config[GT911_CONFIG_DATA_MODULE_SWITCH1] = (config[GT911_CONFIG_DATA_MODULE_SWITCH1] & ~0x3); - - config[GT911_CONFIG_DATA_SIZE - 2] = gt911_calcualte_config_data_checksum(config); - config[GT911_CONFIG_DATA_SIZE - 1] = 1; - /* - * for (uint8_t i = 0; i < 5; i++) { - * gt911_write_data(context, GT911_CONFIG, config, GT911_CONFIG_DATA_SIZE); - * } - */ - gt911_write_register(context, GT911_CMD, GT911_CMD_SOFT_RESET); - return status_success; -} - -hpm_stat_t gt911_read_touch_data(gt911_context_t *context, - gt911_touch_data_t *touch_data) -{ - hpm_stat_t stat = status_success; - - stat = gt911_read_data(context, GT911_STATUS, - (uint8_t *)touch_data, sizeof(gt911_touch_data_t)); - if (stat != status_success) { - return stat; - } - - gt911_write_register(context, GT911_STATUS, 0); - - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h deleted file mode 100644 index 4d91f1d52bf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_gt911.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GT911_H -#define HPM_GT911_H -#include "board.h" -#include "hpm_common.h" -#include "hpm_i2c_drv.h" - -#ifdef BOARD_GT911_ADDR -/* if i2c addres is specified by board, use it */ -#define GT911_I2C_ADDR BOARD_GT911_ADDR -/* no auto probe in this case */ -#define GT911_NO_AUTO_PROBE 1 -#else -#undef GT911_I2C_ADDR - -/* enable auto probe */ -#ifndef GT911_NO_AUTO_PROBE -#define GT911_NO_AUTO_PROBE 0 -#endif - -/* i2c device address candidates */ -#define GT911_I2C_ADDR0 (0x14U) -#define GT911_I2C_ADDR1 (0x5DU) -#endif - -#define GT911_PRODUCT_ID (0x313139U) -/* - * GT911 registers at operation mode - */ - -#define GT911_CMD (0x8040U) -#define GT911_CMD_READ_COORD_STAT (0U) -#define GT911_CMD_READ_RAW_DATA (1U) -#define GT911_CMD_SOFT_RESET (2U) -#define GT911_CMD_READ_SCREEN_OFF (5U) - -#define GT911_CONFIG (0x8047U) - -#define GT911_ID_B0 (0x8140U) -#define GT911_ID_B1 (0x8141U) -#define GT911_ID_B2 (0x8142U) -#define GT911_ID_B4 (0x8143U) -#define GT911_FW_VERSION_L (0x8144U) -#define GT911_FW_VERSION_H (0x8145U) -#define GT911_TOUCH_XL (0x8146U) -#define GT911_TOUCH_XH (0x8147U) -#define GT911_TOUCH_YL (0x8148U) -#define GT911_TOUCH_YH (0x8149U) -#define GT911_VENDOR_ID (0x814AU) -#define GT911_STATUS (0x814EU) -#define GT911_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) -#define GT911_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) -#define GT911_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) -#define GT911_FIRST_POINT (0x814FU) - -#define GT911_MAX_TOUCH_POINTS (5U) -#define GT911_CONFIG_DATA_SIZE (186U) -#define GT911_CONFIG_DATA_RESOLUTION_XL (1U) -#define GT911_CONFIG_DATA_RESOLUTION_XH (2U) -#define GT911_CONFIG_DATA_RESOLUTION_YL (3U) -#define GT911_CONFIG_DATA_RESOLUTION_YH (4U) -#define GT911_CONFIG_DATA_TOUCH_NUMBER (5U) -#define GT911_CONFIG_DATA_MODULE_SWITCH1 (6U) - -typedef struct { - uint8_t track_id; - uint8_t x_l; - uint8_t x_h; - uint8_t y_l; - uint8_t y_h; - uint8_t size_l; - uint8_t size_h; - uint8_t reserved; -} gt911_touch_point_t; - -typedef struct { - uint8_t status; - gt911_touch_point_t points[GT911_MAX_TOUCH_POINTS]; -} gt911_touch_data_t; - -typedef struct { - I2C_Type *ptr; -} gt911_context_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * gt911 initialization routine - */ -hpm_stat_t gt911_init(gt911_context_t *context, uint16_t width, uint16_t height); - -/* - * gt911 read touch data - */ -hpm_stat_t gt911_read_touch_data(gt911_context_t *context, - gt911_touch_data_t *touch_data); - -/* - * gt911 read data - */ -hpm_stat_t gt911_read_data(gt911_context_t *context, uint16_t addr, - uint8_t *buf, uint32_t size); - -/* - * gt911 write value to given register - */ -hpm_stat_t gt911_write_register(gt911_context_t *context, - uint16_t reg, uint8_t val); - -/* - * gt911 read value of given register - */ -hpm_stat_t gt911_read_register(gt911_context_t *context, uint16_t reg, uint8_t *buf); - -/* - * gt911 read config data - */ -hpm_stat_t gt911_read_config(gt911_context_t *context, uint8_t *buf, uint8_t size); -#ifdef __cplusplus -} -#endif -#endif /* HPM_GT911_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c deleted file mode 100644 index 6543b7e9829..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt911/hpm_touch_gt911.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "board.h" -#include "hpm_touch.h" -#include "hpm_gpio_drv.h" -#include "hpm_gt911.h" -#include "hpm_touch.h" - -gt911_context_t gt911 = {0}; - -hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) -{ - hpm_stat_t stat = status_success; - gt911_touch_data_t touch_data = {0}; - uint8_t num, i; - - stat = gt911_read_touch_data(>911, &touch_data); - if (stat != status_success) { - printf("gt911 read data failed\n"); - return stat; - } - /* the buffer status is ready*/ - if (GT911_GET_STATUS_BUFFER_STAT(touch_data.status) == 1) { - num = GT911_GET_STATUS_NUM_OF_POINTS(touch_data.status); - *num_of_points = num; - if (num > 0 && num <= GT911_MAX_TOUCH_POINTS) { - for (i = 0; i < num; i++) { - points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; - points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; - } - } else { - stat = status_touch_points_over_number; - } - } else { - stat = status_touch_buffer_no_ready; - } - gt911_write_register(>911, GT911_STATUS, 0); - return stat; -} - -void pull_int_pin(bool high) -{ - gpio_set_pin_output(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); - gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, high); -} - -void float_int_pin(void) -{ - gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); -} - -hpm_stat_t touch_init(I2C_Type *i2c_ptr) -{ - hpm_stat_t stat = status_success; - - gt911.ptr = i2c_ptr; - - stat = gt911_init(>911, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT); - if (stat != status_success) { - return stat; - } - gt911_write_register(>911, GT911_CMD, GT911_CMD_READ_COORD_STAT); - - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.c deleted file mode 100644 index ed400432725..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_gt9xx.h" -static uint8_t g_i2c_addr; - -hpm_stat_t gt9xx_read_data(gt9xx_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) -{ - uint8_t r[2]; - r[0] = addr >> 8; - r[1] = addr & 0xFF; - return i2c_master_address_read(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); -} - -hpm_stat_t gt9xx_write_data(gt9xx_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size) -{ - uint8_t r[2]; - r[0] = addr >> 8; - r[1] = addr & 0xFF; - - return i2c_master_address_write(context->ptr, g_i2c_addr, r, sizeof(r), buf, size); -} - -hpm_stat_t gt9xx_read_register(gt9xx_context_t *context, uint16_t reg, uint8_t *buf) -{ - return gt9xx_read_data(context, reg, buf, 1); -} - -hpm_stat_t gt9xx_write_register(gt9xx_context_t *context, uint16_t reg, uint8_t val) -{ - return gt9xx_write_data(context, reg, &val, 1); -} - -hpm_stat_t gt9xx_soft_reset(gt9xx_context_t *context) -{ - return gt9xx_write_register(context, GT9XX_CMD, 0); -} - -static uint8_t gt9xx_calcualte_config_data_checksum(uint8_t *config) -{ - uint8_t checksum = 0; - for (uint32_t i = 0; i < GT9XX_CONFIG_DATA_SIZE - 2; i++) { - checksum += config[i]; - } - return (~checksum + 1); -} - -hpm_stat_t gt9xx_read_config(gt9xx_context_t *context, uint8_t *buf, uint8_t size) -{ - return gt9xx_read_data(context, GT9XX_CONFIG, buf, size); -} - -hpm_stat_t gt9xx_init(gt9xx_context_t *context, uint16_t width, uint16_t height) -{ - hpm_stat_t stat = status_success; - uint8_t config[GT9XX_CONFIG_DATA_SIZE] = {0}; - -#ifdef GT9XX_I2C_ADDR - g_i2c_addr = GT9XX_I2C_ADDR; - stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config)); - if (stat != status_success) { - return stat; - } -#elif !GT9XX_NO_AUTO_PROBE - g_i2c_addr = GT9XX_I2C_ADDR0; - stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config)); - if (stat != status_success) { - printf("0x%x failed to init GT9XX", g_i2c_addr); - g_i2c_addr = GT9XX_I2C_ADDR1; - printf(", try 0x%x\n", g_i2c_addr); - stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config)); - } - if (stat != status_success) { - return stat; - } -#else - g_i2c_addr = GT9XX_I2C_ADDR0; - stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config)); - if (stat != status_success) { - return stat; - } -#endif - - if (config[GT9XX_CONFIG_DATA_SIZE - 2] != gt9xx_calcualte_config_data_checksum(config)) { - return status_fail; - } - - /* < 90: fixed config; >=90 custom config */ - if (config[GT9XX_CONFIG_DATA_CONFIG_VERSION] < 90) { - printf("ERR: GTXXX custom config can't be supported\n"); - return status_fail; - } else { - context->abs_x_max = config[GT9XX_CONFIG_DATA_RESOLUTION_XH]; - context->abs_x_max <<= 8; - context->abs_x_max |= config[GT9XX_CONFIG_DATA_RESOLUTION_XL]; - - context->abs_y_max = config[GT9XX_CONFIG_DATA_RESOLUTION_YH]; - context->abs_y_max <<= 8; - context->abs_y_max |= config[GT9XX_CONFIG_DATA_RESOLUTION_YL]; - } - /* stat = gt9xx_read_data(context, GT9XX_ID_B0, (uint8_t*)&val, sizeof(val)); */ - /* if (stat != status_success) { */ - /* return stat; */ - /* } */ - - /* if (val != GT9XX_PRODUCT_ID) { */ - /* return status_fail; */ - /* } */ - - config[GT9XX_CONFIG_DATA_RESOLUTION_XL] = width & 0xFF; - config[GT9XX_CONFIG_DATA_RESOLUTION_XH] = width >> 8; - config[GT9XX_CONFIG_DATA_RESOLUTION_YL] = height & 0xFF; - config[GT9XX_CONFIG_DATA_RESOLUTION_YH] = height >> 8; - config[GT9XX_CONFIG_DATA_TOUCH_NUMBER] = 5; - config[GT9XX_CONFIG_DATA_MODULE_SWITCH1] = (config[GT9XX_CONFIG_DATA_MODULE_SWITCH1] & ~0x3); - - config[GT9XX_CONFIG_DATA_SIZE - 2] = gt9xx_calcualte_config_data_checksum(config); - config[GT9XX_CONFIG_DATA_SIZE - 1] = 1; - /* - * for (uint8_t i = 0; i < 5; i++) { - * gt9xx_write_data(context, GT9XX_CONFIG, config, GT9XX_CONFIG_DATA_SIZE); - * } - */ - gt9xx_write_register(context, GT9XX_CMD, GT9XX_CMD_SOFT_RESET); - return status_success; -} - -hpm_stat_t gt9xx_read_touch_data(gt9xx_context_t *context, - gt9xx_touch_data_t *touch_data) -{ - hpm_stat_t stat = status_success; - - stat = gt9xx_read_data(context, GT9XX_STATUS, - (uint8_t *)touch_data, sizeof(gt9xx_touch_data_t)); - if (stat != status_success) { - return stat; - } - - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.h deleted file mode 100644 index 6bf937abc13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GT9XX_H -#define HPM_GT9XX_H -#include "board.h" -#include "hpm_common.h" -#include "hpm_i2c_drv.h" - -#ifdef BOARD_GT9XX_ADDR -/* if i2c addres is specified by board, use it */ -#define GT9XX_I2C_ADDR BOARD_GT9XX_ADDR -/* no auto probe in this case */ -#define GT9XX_NO_AUTO_PROBE 1 -#else -#undef GT9XX_I2C_ADDR - -/* enable auto probe */ -#ifndef GT9XX_NO_AUTO_PROBE -#define GT9XX_NO_AUTO_PROBE 0 -#endif - -/* i2c device address candidates */ -#define GT9XX_I2C_ADDR0 (0x14U) -#define GT9XX_I2C_ADDR1 (0x5DU) -#endif - -#define GT9XX_PRODUCT_ID (0x313139U) -/* - * GT9XX registers at operation mode - */ - -#define GT9XX_CMD (0x8040U) -#define GT9XX_CMD_READ_COORD_STAT (0U) -#define GT9XX_CMD_READ_RAW_DATA (1U) -#define GT9XX_CMD_SOFT_RESET (2U) -#define GT9XX_CMD_READ_SCREEN_OFF (5U) - -#define GT9XX_CONFIG (0x8047U) - -#define GT9XX_ID_B0 (0x8140U) -#define GT9XX_ID_B1 (0x8141U) -#define GT9XX_ID_B2 (0x8142U) -#define GT9XX_ID_B4 (0x8143U) -#define GT9XX_FW_VERSION_L (0x8144U) -#define GT9XX_FW_VERSION_H (0x8145U) -#define GT9XX_TOUCH_XL (0x8146U) -#define GT9XX_TOUCH_XH (0x8147U) -#define GT9XX_TOUCH_YL (0x8148U) -#define GT9XX_TOUCH_YH (0x8149U) -#define GT9XX_VENDOR_ID (0x814AU) -#define GT9XX_STATUS (0x814EU) -#define GT9XX_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU) -#define GT9XX_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6) -#define GT9XX_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7) -#define GT9XX_FIRST_POINT (0x814FU) - -#define GT9XX_MAX_TOUCH_POINTS (5U) -#define GT9XX_CONFIG_DATA_SIZE (186U) -#define GT9XX_CONFIG_DATA_CONFIG_VERSION (0U) -#define GT9XX_CONFIG_DATA_RESOLUTION_XL (1U) -#define GT9XX_CONFIG_DATA_RESOLUTION_XH (2U) -#define GT9XX_CONFIG_DATA_RESOLUTION_YL (3U) -#define GT9XX_CONFIG_DATA_RESOLUTION_YH (4U) -#define GT9XX_CONFIG_DATA_TOUCH_NUMBER (5U) -#define GT9XX_CONFIG_DATA_MODULE_SWITCH1 (6U) - -typedef struct { - uint8_t track_id; - uint8_t x_l; - uint8_t x_h; - uint8_t y_l; - uint8_t y_h; - uint8_t size_l; - uint8_t size_h; - uint8_t reserved; -} gt9xx_touch_point_t; - -typedef struct { - uint8_t status; - gt9xx_touch_point_t points[GT9XX_MAX_TOUCH_POINTS]; -} gt9xx_touch_data_t; - -typedef struct { - I2C_Type *ptr; - uint16_t abs_x_max; - uint16_t abs_y_max; - bool exchange_xy; - bool reverse_x; - bool reverse_y; -} gt9xx_context_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * gt9xx initialization routine - */ -hpm_stat_t gt9xx_init(gt9xx_context_t *context, uint16_t width, uint16_t height); - -/* - * gt9xx read touch data - */ -hpm_stat_t gt9xx_read_touch_data(gt9xx_context_t *context, - gt9xx_touch_data_t *touch_data); - -/* - * gt9xx read data - */ -hpm_stat_t gt9xx_read_data(gt9xx_context_t *context, uint16_t addr, - uint8_t *buf, uint32_t size); - -/* - * gt9xx write value to given register - */ -hpm_stat_t gt9xx_write_register(gt9xx_context_t *context, - uint16_t reg, uint8_t val); - -/* - * gt9xx read value of given register - */ -hpm_stat_t gt9xx_read_register(gt9xx_context_t *context, uint16_t reg, uint8_t *buf); - -/* - * gt9xx read config data - */ -hpm_stat_t gt9xx_read_config(gt9xx_context_t *context, uint8_t *buf, uint8_t size); -#ifdef __cplusplus -} -#endif -#endif /* HPM_GT9XX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_touch_gt9xx.c b/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_touch_gt9xx.c deleted file mode 100644 index 879aab78d7d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_touch_gt9xx.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "board.h" -#include "hpm_touch.h" -#include "hpm_gpio_drv.h" -#include "hpm_gt9xx.h" -#include "hpm_touch.h" - -gt9xx_context_t gt9xx = {0}; - -hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points) -{ - hpm_stat_t stat = status_success; - gt9xx_touch_data_t touch_data = {0}; - uint8_t num, i; - uint16_t tmp; - - stat = gt9xx_read_touch_data(>9xx, &touch_data); - if (stat != status_success) { - printf("gt9xx read data failed\n"); - return stat; - } - /* the buffer status is ready*/ - if (GT9XX_GET_STATUS_BUFFER_STAT(touch_data.status) == 1) { - num = GT9XX_GET_STATUS_NUM_OF_POINTS(touch_data.status); - *num_of_points = num; - if (num > 0 && num <= GT9XX_MAX_TOUCH_POINTS) { - for (i = 0; i < num; i++) { - points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l; - points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l; - - if (gt9xx.reverse_x) - points[i].x = gt9xx.abs_x_max - points[i].x; - - if (gt9xx.reverse_y) - points[i].y = gt9xx.abs_y_max - points[i].y; - - if (gt9xx.exchange_xy) { - tmp = points[i].x; - points[i].x = points[i].y; - points[i].y = tmp; - } - } - } else { - stat = status_touch_points_over_number; - } - gt9xx_write_register(>9xx, GT9XX_STATUS, 0); - } else { - stat = status_touch_buffer_no_ready; - } - - return stat; -} - -void pull_int_pin(bool high) -{ - gpio_set_pin_output(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); - gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, high); -} - -void float_int_pin(void) -{ - gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN); -} - -hpm_stat_t touch_init(I2C_Type *i2c_ptr) -{ - hpm_stat_t stat = status_success; - - gt9xx.ptr = i2c_ptr; - - stat = gt9xx_init(>9xx, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT); - if (stat != status_success) { - return stat; - } - gt9xx_write_register(>9xx, GT9XX_CMD, GT9XX_CMD_READ_COORD_STAT); - - return stat; -} - -hpm_stat_t touch_config(bool exchange_xy, bool reverse_x, bool reverse_y) -{ - gt9xx.exchange_xy = exchange_xy; - gt9xx.reverse_x = reverse_x; - gt9xx.reverse_y = reverse_y; - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h b/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h deleted file mode 100644 index ddffc41bed1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_TOUCH_H -#define HPM_TOUCH_H - -#include "hpm_common.h" - -#if defined(CONFIG_TOUCH_FT5406) && (CONFIG_TOUCH_FT5406 == 1) -#include "hpm_ft5406.h" -#define HPM_TOUCH_MAX_POINTS (FT5406_MAX_TOUCH_POINTS) -#elif defined(CONFIG_TOUCH_GT9XX) && (CONFIG_TOUCH_GT9XX == 1) -#include "hpm_gt9xx.h" -#define HPM_TOUCH_MAX_POINTS (GT9XX_MAX_TOUCH_POINTS) -#else -#error "unknown touch type, either have CONFIG_FT5406 or CONFIG_GT9XX defined" -#endif - -enum { - status_touch_buffer_no_ready = MAKE_STATUS(status_group_touch, 0), - status_touch_points_over_number = MAKE_STATUS(status_group_touch, 1), -}; - -typedef struct { - uint16_t x; - uint16_t y; -} touch_point_t; - -#ifdef __cplusplus -extern "C" { -#endif - -hpm_stat_t touch_init(I2C_Type *i2c_ptr); -hpm_stat_t touch_config(bool exchange_xy, bool reverse_x, bool reverse_y); -hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points); - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_TOUCH_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c deleted file mode 100644 index 8367d282321..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_uart_lin.h" - -#ifndef HPM_UART_LIN_RETRY_COUNT -#define HPM_UART_LIN_RETRY_COUNT (50000U) -#endif - -#ifndef HPM_UART_LIN_BREAK_LENGTH -#define HPM_UART_LIN_BREAK_LENGTH (13U) /* bits */ -#endif - -#ifndef HPM_UART_LIN_WAKEUP_LENGTH -#define HPM_UART_LIN_WAKEUP_LENGTH (400U) /* us */ -#endif - - -uint8_t hpm_uart_lin_calculate_protected_id(uint8_t id) -{ - uint8_t id0, id1, id2, id3, id4, id5, p0, p1, pid; - - /* P0 = ID0 @ ID1 @ ID2 @ ID3 @ ID4 */ - /* P1 = !(ID1 @ ID2 @ ID3 @ ID4 @ ID5) */ - id0 = (id >> 0U) & 0x1U; - id1 = (id >> 1U) & 0x1U; - id2 = (id >> 2U) & 0x1U; - id3 = (id >> 3U) & 0x1U; - id4 = (id >> 4U) & 0x1U; - id5 = (id >> 5U) & 0x1U; - - p0 = id0 ^ id1 ^ id2 ^ id4; - p1 = !(id1 ^ id3 ^ id4 ^ id5); - pid = (p1 << 7) | (p0 << 6) | id; - return pid; -} - -static uint8_t hpm_uart_lin_calculate_checksum(uint8_t id, uint8_t *data, uint8_t length, bool enhanced_checksum) -{ - assert(length <= 8U); - uint8_t checksum = 0; - uint16_t temp; - for (uint8_t i = 0; i < length; i++) { - temp = checksum + data[i]; - checksum += data[i] + (temp >> 8U); - } - - if (enhanced_checksum) { - temp = checksum + id; - checksum += id + (temp >> 8U); - } - - checksum = ~checksum; - return checksum; -} - -static bool hpm_uart_lin_check_checksum(uint8_t id, uint8_t *data, uint8_t length, bool enhanced_checksum, uint8_t checksum) -{ - uint8_t cal_checksum; - cal_checksum = hpm_uart_lin_calculate_checksum(id, data, length, enhanced_checksum); - - if (cal_checksum != checksum) { - return false; - } - return true; -} - - -static void hpm_uart_lin_send_break(UART_Type *ptr, uart_lin_master_pin_ctrl_t *pin_ctrl) -{ - assert(pin_ctrl->baudrate <= 20000); - - uint32_t bit_period_us = 1000000 / pin_ctrl->baudrate; - uint32_t break_period_us = bit_period_us * HPM_UART_LIN_BREAK_LENGTH; - pin_ctrl->config_uart_pin_as_gpio(ptr); - gpio_set_pin_output(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin); - gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 0); - pin_ctrl->delay_us(break_period_us); - gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 1); - pin_ctrl->delay_us(bit_period_us); - pin_ctrl->config_uart_pin(ptr); -} - -static void hpm_uart_lin_send_sync(UART_Type *ptr) -{ - uart_write_byte(ptr, 0x55); /* sync phase */ -} - -void hpm_uart_lin_send_wakeup(UART_Type *ptr, uart_lin_master_pin_ctrl_t *pin_ctrl) -{ - pin_ctrl->config_uart_pin_as_gpio(ptr); - gpio_set_pin_output(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin); - gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 0); - pin_ctrl->delay_us(HPM_UART_LIN_WAKEUP_LENGTH); - gpio_write_pin(pin_ctrl->ptr, pin_ctrl->tx_port, pin_ctrl->tx_pin, 1); - pin_ctrl->config_uart_pin(ptr); -} - -uart_lin_stat_t hpm_uart_lin_master_send_frame(uart_lin_master_config_t *config) -{ - uint32_t retry; - UART_Type *ptr = config->ptr; - uart_lin_data_t data = config->data; - uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); - uint8_t checksum = hpm_uart_lin_calculate_checksum(pid, data.buff, data.length, data.enhance_checksum); - uint8_t send_data[11] = {0}; /* max 8 data bytes + 1 byte 0x55 + 1 byte pid + 1byte checksum */ - uint8_t length = data.length + 3; - - assert(data.length > 0); - - /* 0x55 - pid - data - checksum */ - send_data[0] = 0x55; - send_data[1] = pid; - memcpy(&send_data[2], data.buff, data.length); - send_data[data.length + 2] = checksum; - - hpm_uart_lin_send_break(ptr, &(config->pin_ctrl)); - - for (uint8_t i = 0; i < length; i++) { - retry = 0; - while (!uart_check_status(ptr, uart_stat_tx_slot_avail)) { - if (retry > HPM_UART_LIN_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_UART_LIN_RETRY_COUNT) { - return uart_lin_timeout; - } - - uart_write_byte(ptr, send_data[i]); - } - - return uart_lin_success; -} - - -uart_lin_stat_t hpm_uart_lin_master_receive_frame(uart_lin_master_config_t *config) -{ - uint32_t retry = 0; - UART_Type *ptr = config->ptr; - uart_lin_data_t data = config->data; - uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); - uint8_t checksum; - uint8_t *buff = data.buff; - - assert(data.length > 0); - - /* clear data in rx fifo */ - uart_clear_rx_fifo(ptr); - - hpm_uart_lin_send_break(ptr, &(config->pin_ctrl)); - - hpm_uart_lin_send_sync(ptr); - - uart_write_byte(ptr, pid); - - /* wait for send 0x55 and pid */ - while (!uart_check_status(ptr, uart_stat_tx_slot_avail)) { - if (retry > HPM_UART_LIN_RETRY_COUNT * 2) { - break; - } - retry++; - } - - if (retry > HPM_UART_LIN_RETRY_COUNT * 2) { - return uart_lin_timeout; - } - - /* wait for receive complete */ - for (uint8_t i = 0; i < data.length + 3; i++) { - retry = 0; - while (!uart_check_status(ptr, uart_stat_data_ready)) { - if (retry > HPM_UART_LIN_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_UART_LIN_RETRY_COUNT) { - return uart_lin_timeout; - } - - if (i < 2) { - uart_read_byte(ptr); - } else if (i < data.length + 2) { - *(buff++) = uart_read_byte(ptr); - } else { - checksum = uart_read_byte(ptr); - } - } - - if (!hpm_uart_lin_check_checksum(pid, data.buff, data.length, data.enhance_checksum, checksum)) { - return uart_lin_checksum_error; - } - - return uart_lin_success; -} - -/* generate break with gpio then write 0x55 and pid into uart tx fifo */ -void hpm_uart_lin_master_send_head(uart_lin_master_config_t *config) -{ - UART_Type *ptr = config->ptr; - uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); - - /* clear data in rx fifo */ - uart_clear_rx_fifo(ptr); - - hpm_uart_lin_send_break(ptr, &(config->pin_ctrl)); - - hpm_uart_lin_send_sync(ptr); - - uart_write_byte(ptr, pid); -} - -/* write data into uart tx fifo including data and checksum */ -void hpm_uart_lin_master_send_data(uart_lin_master_config_t *config) -{ - UART_Type *ptr = config->ptr; - uart_lin_data_t data = config->data; - - assert(data.length > 0); - - uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); - uint8_t checksum = hpm_uart_lin_calculate_checksum(pid, data.buff, data.length, data.enhance_checksum); - - for (uint8_t i = 0; i < data.length; i++) { - uart_write_byte(ptr, *(data.buff++)); - } - - uart_write_byte(ptr, checksum); -} - -/* call this function in rx timeout isr */ -/* read data from uart rx fifo */ -uart_lin_stat_t hpm_uart_lin_master_receive_data(uart_lin_master_config_t *config) -{ - UART_Type *ptr = config->ptr; - uart_lin_data_t data = config->data; - uint8_t pid = hpm_uart_lin_calculate_protected_id(config->id); - uint8_t checksum = 0; - uint8_t index = 0; - uint8_t *buff = data.buff; - - assert(data.length > 0); - - while (uart_check_status(ptr, uart_stat_data_ready)) { - if (index >= data.length + 3) { - break; - } - if (index < 2) { - uart_read_byte(ptr); /* read 0x55 and pid */ - } else if (index < data.length + 2) { - *(buff++) = uart_read_byte(ptr); - } else { - checksum = uart_read_byte(ptr); - } - index++; - } - - if (index != data.length + 3) { - return uart_lin_frame_error; - } - - if (!hpm_uart_lin_check_checksum(pid, data.buff, data.length, data.enhance_checksum, checksum)) { - return uart_lin_checksum_error; - } - - return uart_lin_success; -} - -/* write data into uart tx fifo including data and checksum */ -void hpm_uart_lin_slave_send_data(uart_lin_slave_config_t *config) -{ - UART_Type *ptr = config->ptr; - uart_lin_data_t data = config->data; - - assert(data.length > 0); - - uint8_t checksum = hpm_uart_lin_calculate_checksum(config->pid, data.buff, data.length, data.enhance_checksum); - - for (uint8_t i = 0; i < data.length; i++) { - uart_write_byte(ptr, *(data.buff++)); - } - - uart_write_byte(ptr, checksum); -} - -/* read data and checksum */ -uart_lin_stat_t hpm_uart_lin_slave_receive_data(uart_lin_slave_config_t *config) -{ - UART_Type *ptr = config->ptr; - uart_lin_data_t data = config->data; - - assert(data.length > 0); - - uint8_t index = 0; - uint8_t checksum = 0; - - /* receive data and checksum */ - while (uart_check_status(ptr, uart_stat_data_ready)) { - if (index == data.length) { - checksum = uart_read_byte(ptr); - break; - } - *(data.buff + index++) = uart_read_byte(ptr); - } - - if (index != data.length) { - return uart_lin_frame_error; - } - - if (!hpm_uart_lin_check_checksum(config->pid, data.buff, data.length, data.enhance_checksum, checksum)) { - return uart_lin_checksum_error; - } - - return uart_lin_success; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h b/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h deleted file mode 100644 index f79790b5d0a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/uart_lin/hpm_uart_lin.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef UART_LIN_H -#define UART_LIN_H - -#include "hpm_clock_drv.h" -#include "hpm_gpio_drv.h" -#include "hpm_uart_drv.h" - -/** - * - * @brief UART Lin component APIs - * @defgroup uart_lin_interface UART component APIs - * @ingroup io_interfaces - * @{ - */ - -typedef struct uart_lin_pin { - GPIO_Type *ptr; - uint32_t baudrate; - void (*config_uart_pin)(UART_Type *ptr); - void (*config_uart_pin_as_gpio)(UART_Type *ptr); - void (*delay_us)(uint32_t us); - uint8_t tx_port; - uint8_t tx_pin; -} uart_lin_master_pin_ctrl_t; - -typedef struct { - uint8_t *buff; - uint8_t length; - bool enhance_checksum; -} uart_lin_data_t; - -typedef enum { - uart_lin_success = 0, - uart_lin_fail = 1, - uart_lin_invalid_argument = 2, - uart_lin_timeout = 3, - uart_lin_id_parity_error = 4, - uart_lin_checksum_error = 5, - uart_lin_frame_error = 6, /*next = USB_SOC_DCD_QTD_NEXT_INVALID; - p_qtd->active = 1; - p_qtd->total_bytes = p_qtd->expected_bytes = total_bytes; - - if (data_ptr != NULL) { - p_qtd->buffer[0] = (uint32_t)data_ptr; - for (uint8_t i = 1; i < USB_SOC_DCD_QHD_BUFFER_COUNT; i++) { - p_qtd->buffer[i] |= ((p_qtd->buffer[i-1]) & 0xFFFFF000UL) + 4096U; - } - } -} - -/*--------------------------------------------------------------------- - * Device API - *--------------------------------------------------------------------- - */ -dcd_qhd_t *usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx) -{ - return &handle->dcd_data->qhd[ep_idx]; -} - -dcd_qtd_t *usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx) -{ - return &handle->dcd_data->qtd[ep_idx * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT]; -} - -void usb_device_bus_reset(usb_device_handle_t *handle, uint16_t ep0_max_packet_size) -{ - dcd_data_t *dcd_data = handle->dcd_data; - - usb_dcd_bus_reset(handle->regs, ep0_max_packet_size); - - /* Queue Head & Queue TD */ - memset(dcd_data, 0, sizeof(dcd_data_t)); - - /* Set up Control Endpoints (0 OUT, 1 IN) */ - dcd_data->qhd[0].zero_length_termination = dcd_data->qhd[1].zero_length_termination = 1; - dcd_data->qhd[0].max_packet_size = dcd_data->qhd[1].max_packet_size = ep0_max_packet_size; - dcd_data->qhd[0].qtd_overlay.next = dcd_data->qhd[1].qtd_overlay.next = USB_SOC_DCD_QTD_NEXT_INVALID; - - /* OUT only */ - dcd_data->qhd[0].int_on_setup = 1; -} - -bool usb_device_init(usb_device_handle_t *handle, uint32_t int_mask) -{ - /* Clear memroy */ - if (handle->dcd_data == NULL) { - return false; - } - - memset(handle->dcd_data, 0, sizeof(dcd_data_t)); - - /* Initialize controller in device mode */ - usb_dcd_init(handle->regs); - - /* Set endpoint list address */ - usb_dcd_set_edpt_list_addr(handle->regs, core_local_mem_to_sys_address(0, (uint32_t)handle->dcd_data->qhd)); - - /* Clear status */ - usb_clear_status_flags(handle->regs, usb_get_status_flags(handle->regs)); - - /* Enable interrupt mask */ - usb_enable_interrupts(handle->regs, int_mask); - - /* Connect */ - usb_dcd_connect(handle->regs); - - return true; -} - -void usb_device_deinit(usb_device_handle_t *handle) -{ - /* Clear memroy */ - memset(handle->dcd_data, 0, sizeof(dcd_data_t)); - - usb_dcd_deinit(handle->regs); - - for (uint32_t i = 0; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { - usb_dcd_edpt_close(handle->regs, (i | (usb_dir_in << 0x07))); - usb_dcd_edpt_close(handle->regs, (i | (usb_dir_out << 0x07))); - } -} - -uint32_t usb_device_status_flags(usb_device_handle_t *handle) -{ - return usb_get_status_flags(handle->regs); -} - -void usb_device_clear_status_flags(usb_device_handle_t *handle, uint32_t mask) -{ - usb_clear_status_flags(handle->regs, mask); -} - -uint32_t usb_device_interrupts(usb_device_handle_t *handle) -{ - return usb_get_interrupts(handle->regs); -} - -uint8_t usb_device_get_port_speed(usb_device_handle_t *handle) -{ - return usb_get_port_speed(handle->regs); -} - -uint8_t usb_device_get_suspend_status(usb_device_handle_t *handle) -{ - return usb_get_suspend_status(handle->regs); -} - -void usb_device_set_address(usb_device_handle_t *handle, uint8_t dev_addr) -{ - /* Response with status first before changing device address */ - usb_device_edpt_xfer(handle, 0 | usb_dir_in_mask, NULL, 0); - - usb_dcd_set_address(handle->regs, dev_addr); -} - -uint8_t usb_device_get_address(usb_device_handle_t *handle) -{ - return usb_dcd_get_device_addr(handle->regs); -} - -void usb_device_remote_wakeup(usb_device_handle_t *handle) -{ - usb_dcd_remote_wakeup(handle->regs); -} - -void usb_device_connect(usb_device_handle_t *handle) -{ - usb_dcd_connect(handle->regs); -} - -void usb_device_disconnect(usb_device_handle_t *handle) -{ - usb_dcd_disconnect(handle->regs); -} - -bool usb_device_get_port_ccs(usb_device_handle_t *handle) -{ - return usb_get_port_ccs(handle->regs); -} - -bool usb_device_get_port_reset_status(usb_device_handle_t *handle) -{ - return usb_get_port_reset_status(handle->regs); -} - -uint32_t usb_device_get_edpt_complete_status(usb_device_handle_t *handle) -{ - return usb_dcd_get_edpt_complete_status(handle->regs); -} - -void usb_device_clear_edpt_complete_status(usb_device_handle_t *handle, uint32_t mask) -{ - usb_dcd_clear_edpt_complete_status(handle->regs, mask); -} - -uint32_t usb_device_get_setup_status(usb_device_handle_t *handle) -{ - return usb_dcd_get_edpt_setup_status(handle->regs); -} - -void usb_device_clear_setup_status(usb_device_handle_t *handle, uint32_t mask) -{ - usb_dcd_clear_edpt_setup_status(handle->regs, mask); -} - -/*--------------------------------------------------------------------- - * Endpoint API - *--------------------------------------------------------------------- - */ -bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *config) -{ - uint8_t const epnum = config->ep_addr & 0x0f; - uint8_t const dir = (config->ep_addr & 0x80) >> 7; - uint8_t const ep_idx = 2 * epnum + dir; - - dcd_qhd_t *p_qhd; - - /* Must not exceed max endpoint number */ - if (epnum >= USB_SOC_DCD_MAX_ENDPOINT_COUNT) { - return false; - } - - /* Prepare Queue Head */ - p_qhd = &handle->dcd_data->qhd[ep_idx]; - memset(p_qhd, 0, sizeof(dcd_qhd_t)); - - p_qhd->zero_length_termination = 1; - p_qhd->max_packet_size = config->max_packet_size & 0x7FFu; - p_qhd->qtd_overlay.next = USB_SOC_DCD_QTD_NEXT_INVALID; - if (config->xfer == usb_xfer_isochronous) { - p_qhd->iso_mult = ((config->max_packet_size >> 11u) & 0x3u) + 1u; - } - - usb_dcd_edpt_open(handle->regs, config); - - return true; -} - -bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint32_t total_bytes) -{ - uint8_t const epnum = ep_addr & 0x0f; - uint8_t const dir = (ep_addr & 0x80) >> 7; - uint8_t const ep_idx = 2 * epnum + dir; - uint8_t qtd_num; - uint8_t i; - uint32_t xfer_len; - dcd_qhd_t *p_qhd; - dcd_qtd_t *p_qtd; - dcd_qtd_t *first_p_qtd = NULL; - dcd_qtd_t *prev_p_qtd = NULL; - - if (epnum == 0) { - /* follows UM Setup packet handling using setup lockout mechanism - * wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out - */ - while (usb_dcd_get_edpt_setup_status(handle->regs) & HPM_BITSMASK(1, 0)) { - } - } - - qtd_num = (total_bytes + 0x3fff) / 0x4000; - if (qtd_num > USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) { - return false; - } - - if (buffer != NULL) { - buffer = (uint8_t *)core_local_mem_to_sys_address(0, (uint32_t)buffer); - } - p_qhd = &handle->dcd_data->qhd[ep_idx]; - i = 0; - do { - p_qtd = &handle->dcd_data->qtd[ep_idx * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT + i]; - i++; - - if (total_bytes > 0x4000) { - xfer_len = 0x4000; - total_bytes -= 0x4000; - } else { - xfer_len = total_bytes; - total_bytes = 0; - } - - usb_qtd_init(p_qtd, (void *)buffer, xfer_len); - if (total_bytes == 0) { - p_qtd->int_on_complete = true; - } - buffer += xfer_len; - - if (prev_p_qtd) { - prev_p_qtd->next = (uint32_t)p_qtd; - } else { - first_p_qtd = p_qtd; - } - prev_p_qtd = p_qtd; - } while (total_bytes > 0); - - p_qhd->qtd_overlay.next = core_local_mem_to_sys_address(0, (uint32_t) first_p_qtd); /* link qtd to qhd */ - - usb_dcd_edpt_xfer(handle->regs, ep_idx); - - return true; -} - -void usb_device_edpt_stall(usb_device_handle_t *handle, uint8_t ep_addr) -{ - usb_dcd_edpt_stall(handle->regs, ep_addr); -} - -void usb_device_edpt_clear_stall(usb_device_handle_t *handle, uint8_t ep_addr) -{ - usb_dcd_edpt_clear_stall(handle->regs, ep_addr); -} - -bool usb_device_edpt_check_stall(usb_device_handle_t *handle, uint8_t ep_addr) -{ - return usb_dcd_edpt_check_stall(handle->regs, ep_addr); -} - -void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr) -{ - usb_dcd_edpt_close(handle->regs, ep_addr); -} - -void usb_device_edpt_close_all(usb_device_handle_t *handle) -{ - for (uint32_t i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { - usb_device_edpt_close(handle, i); - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h deleted file mode 100644 index 71142f6af14..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.h +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_USB_DEVICE_H -#define HPM_USB_DEVICE_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_usb_drv.h" -#include "hpm_soc_feature.h" -/*--------------------------------------------------------------------- - * Macro Constant Declarations - *--------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------- - * Macro Typedef Declaration - *--------------------------------------------------------------------- - */ - -/* Queue Transfer Descriptor */ -typedef struct { - /* Word 0: Next QTD Pointer */ - volatile uint32_t next; /* Next link pointer This field contains the physical memory address of the next dTD to be processed */ - - /* Word 1: qTQ Token */ - volatile uint32_t : 3; - volatile uint32_t xact_err : 1; - volatile uint32_t : 1; - volatile uint32_t buffer_err : 1; - volatile uint32_t halted : 1; - volatile uint32_t active : 1; - volatile uint32_t : 2; - volatile uint32_t iso_mult_override : 2 ; /* This field can be used for transmit ISOs to override the MULT field in the dQH. This field must be zero for all packet types that are not transmit-ISO. */ - volatile uint32_t : 3; - volatile uint32_t int_on_complete : 1; - volatile uint32_t total_bytes : 15; - volatile uint32_t : 0; - - /* Word 2-6: Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ - volatile uint32_t buffer[USB_SOC_DCD_QHD_BUFFER_COUNT]; - - /*------------- DCD Area -------------*/ - volatile uint16_t expected_bytes; - volatile uint8_t reserved[2]; -} dcd_qtd_t; - -/* Queue Head */ -typedef struct { - /* Word 0: Capabilities and Characteristics */ - - volatile uint32_t : 15 ; /* Number of packets executed per transaction descriptor 00 - Execute N transactions as demonstrated by the USB variable length protocol where N is computed using Max_packet_length and the Total_bytes field in the dTD. 01 - Execute one transaction 10 - Execute two transactions 11 - Execute three transactions Remark: Non-isochronous endpoints must set MULT = 00. Remark: Isochronous endpoints must set MULT = 01, 10, or 11 as needed. */ - volatile uint32_t int_on_setup : 1 ; /* Interrupt on setup This bit is used on control type endpoints to indicate if USBINT is set in response to a setup being received. */ - volatile uint32_t max_packet_size : 11 ; /* This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize) */ - volatile uint32_t : 2; - volatile uint32_t zero_length_termination : 1 ; /* This bit is used for non-isochronous endpoints to indicate when a zero-length packet is received to terminate transfers in case the total transfer length is “multiple”. 0 - Enable zero-length packet to terminate transfers equal to a multiple of Max_packet_length (default). 1 - Disable zero-length packet on transfers that are equal in length to a multiple Max_packet_length. */ - volatile uint32_t iso_mult : 2; - volatile uint32_t : 0; - - /* Word 1: Current qTD Pointer */ - volatile uint32_t qtd_addr; - - /* Word 2-9: Transfer Overlay */ - volatile dcd_qtd_t qtd_overlay; - - /* Word 10-11: Setup request (control OUT only) */ - volatile usb_control_request_t setup_request; - - /*-------------------------------------------------------------------- - * Due to the fact QHD is 64 bytes aligned but occupies only 48 bytes - * thus there are 16 bytes padding free that we can make use of. - *-------------------------------------------------------------------- - */ - volatile uint8_t reserved[16]; -} dcd_qhd_t; - -typedef struct { - dcd_qhd_t qhd[USB_SOS_DCD_MAX_QHD_COUNT]; - dcd_qtd_t qtd[USB_SOC_DCD_MAX_QTD_COUNT]; -} dcd_data_t; - -typedef struct { - USB_Type *regs; - dcd_data_t *dcd_data; -} usb_device_handle_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/*--------------------------------------------------------------------- - * Exported Function Declarations - *--------------------------------------------------------------------- - */ -/* Get a qhd of the specifed endpoint */ -dcd_qhd_t *usb_device_qhd_get(usb_device_handle_t *handle, uint8_t ep_idx); - -/* Get a qtd of the specifed endpoint */ -dcd_qtd_t *usb_device_qtd_get(usb_device_handle_t *handle, uint8_t ep_idx); - -/* USB bus reset */ -void usb_device_bus_reset(usb_device_handle_t *handle, uint16_t ep0_max_packet_size); - -/* Initialize controller to device mode */ -bool usb_device_init(usb_device_handle_t *handle, uint32_t int_mask); - -/* De-initialize controller */ -void usb_device_deinit(usb_device_handle_t *handle); - -/* Set Address request */ -void usb_device_set_address(usb_device_handle_t *handle, uint8_t dev_addr); - -/* Get device address */ -uint8_t usb_device_get_address(usb_device_handle_t *handle); - -/* Wake up host */ -void usb_device_remote_wakeup(usb_device_handle_t *handle); - -/* Connect by enabling internal pull-up resistor on D+/D- */ -void usb_device_connect(usb_device_handle_t *handle); - -/* Disconnect by disabling internal pull-up resistor on D+/D- */ -void usb_device_disconnect(usb_device_handle_t *handle); - -/* Configure an endpoint */ -bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *config); - -/* Submit a transfe */ -bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t *buffer, uint32_t total_bytes); - -/* Stall endpoint */ -void usb_device_edpt_stall(usb_device_handle_t *handle, uint8_t ep_addr); - -/* clear stall */ -void usb_device_edpt_clear_stall(usb_device_handle_t *handle, uint8_t ep_addr); - -/* check stall */ -bool usb_device_edpt_check_stall(usb_device_handle_t *handle, uint8_t ep_addr); - -/* close a specified endpoint */ -void usb_device_edpt_close(usb_device_handle_t *handle, uint8_t ep_addr); - -void usb_device_edpt_close_all(usb_device_handle_t *handle); - -uint32_t usb_device_status_flags(usb_device_handle_t *handle); - -void usb_device_clear_status_flags(usb_device_handle_t *handle, uint32_t mask); - -uint32_t usb_device_interrupts(usb_device_handle_t *handle); - -uint8_t usb_device_get_port_speed(usb_device_handle_t *handle); - -uint8_t usb_device_get_suspend_status(usb_device_handle_t *handle); - -bool usb_device_get_port_ccs(usb_device_handle_t *handle); - -bool usb_device_get_port_reset_status(usb_device_handle_t *handle); - -uint32_t usb_device_get_edpt_complete_status(usb_device_handle_t *handle); - -void usb_device_clear_edpt_complete_status(usb_device_handle_t *handle, uint32_t mask); - -uint32_t usb_device_get_setup_status(usb_device_handle_t *handle); - -void usb_device_clear_setup_status(usb_device_handle_t *handle, uint32_t mask); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_USB_DEVICE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c deleted file mode 100644 index d74cb9cc9db..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_usb_host.h" -#include "hpm_misc.h" -#include "hpm_common.h" -#include "board.h" - -/*--------------------------------------------------------------------- - * Macros - *--------------------------------------------------------------------- - */ - -#define USB_QHD_TYP_SHIFT (1U) - -#define USB_PERIOD_1MS (1U) -#define USB_PERIOD_2MS (2U) -#define USB_PERIOD_4MS (4U) -#define USB_PERIOD_8MS (8U) - -#define USB_DEFAULT_ADDR (0U) -#define USB_HIGH_SPPED_INTERVAL_MAX (16) -#define USB_SETUP_PACKET_LEN (8U) - -#define USB_BIN8(x) ((uint8_t) (0b##x)) -#define USB_BIN16(b1, b2) ((uint16_t) (0b##b1##b2)) -#define USB_BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4)) - -/* helper functions */ -static uint8_t usb_log2(uint32_t value) -{ - uint8_t result = 0; - - while (value >>= 1) { - result++; - } - - return result; -} - -/*****************************************************************************/ -/* list functions */ -/*****************************************************************************/ -static void usb_host_list_insert(hcd_link_t *current, hcd_link_t *new, uint8_t new_type) -{ - new->address = current->address; - current->address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)new) | (new_type << USB_QHD_TYP_SHIFT); -} - -static void usb_host_list_remove_qhd_by_addr(hcd_link_t *list_head, uint8_t dev_addr) -{ - hcd_qhd_t *qhd; - - for (hcd_link_t *prev = list_head; - !prev->terminate && (sys_address_to_core_local_mem(USB_HOST_MCU_CORE, usb_host_align32(prev->address)) != (uint32_t)list_head); - prev = (hcd_link_t *)sys_address_to_core_local_mem(USB_HOST_MCU_CORE, (uint32_t)usb_host_list_next(prev))) { - - /* TODO check type for ISO iTD and siTD */ - qhd = (hcd_qhd_t *)sys_address_to_core_local_mem(USB_HOST_MCU_CORE, (uint32_t)usb_host_list_next(prev)); - - if (qhd->dev_addr == dev_addr) { - /* TODO deactive all TD, wait for QHD to inactive before removal */ - prev->address = qhd->next.address; - - /* EHCI link the removed qhd to async head (which always reachable by Host Controller) */ - qhd->next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)list_head) | (usb_qtype_qhd << USB_QHD_TYP_SHIFT); - - if (qhd->int_smask) { - /* period list queue element is guarantee to be free in the next frame (1 ms) */ - qhd->used = 0; - } else { - /* async list use async advance handshake */ - /* mark as removing, will completely re-usable when async advance isr occurs */ - qhd->removing = 1; - } - } - } -} - -hcd_link_t *usb_host_list_next(hcd_link_t *p_link_pointer) -{ - return (hcd_link_t *)usb_host_align32(p_link_pointer->address); -} - -/*************************************************************/ -/* qhd functions */ -/*************************************************************/ -static hcd_qhd_t *usb_host_qhd_control(usb_host_handle_t *handle, uint8_t dev_addr) -{ - return &handle->hcd_data->control[dev_addr].qhd; -} - -hcd_qhd_t *usb_host_qhd_next(hcd_qhd_t const *p_qhd) -{ - return (hcd_qhd_t *)usb_host_align32(p_qhd->next.address); -} - -static hcd_qhd_t *usb_host_qhd_find_free(usb_host_handle_t *handle) -{ - for (uint32_t i = 0; i < USB_HCD_MAX_QHD_COUNT; i++) { - if (!handle->hcd_data->qhd_pool[i].used) { - return &handle->hcd_data->qhd_pool[i]; - } - } - - return NULL; -} - -static hcd_qhd_t *usb_host_qhd_get_from_addr(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) -{ - hcd_qhd_t *qhd_pool = handle->hcd_data->qhd_pool; - - for (uint32_t i = 0; i < USB_HCD_MAX_QHD_COUNT; i++) { - if ((qhd_pool[i].dev_addr == dev_addr) && - ep_addr == usb_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid)) { - return &qhd_pool[i]; - } - } - - return NULL; -} - -static bool usb_host_qhd_init(usb_host_handle_t *handle, hcd_qhd_t *p_qhd, uint8_t dev_addr, usb_desc_endpoint_t const *ep_desc) -{ - uint8_t const xfer_type = ep_desc->bmAttributes.xfer; - uint8_t const interval = ep_desc->bInterval; - - /* address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise) */ - if (dev_addr != 0) { - memset(p_qhd, 0, sizeof(hcd_qhd_t)); - } - - p_qhd->dev_addr = dev_addr; - p_qhd->fl_inactive_next_xact = 0; - p_qhd->ep_number = usb_edpt_number(ep_desc->bEndpointAddress); - p_qhd->ep_speed = handle->ep_speed; - p_qhd->data_toggle_control = (xfer_type == usb_xfer_control) ? 1 : 0; - p_qhd->head_list_flag = (dev_addr == USB_DEFAULT_ADDR) ? 1 : 0; /* addr0's endpoint is the static async list head */ - p_qhd->max_packet_size = ep_desc->wMaxPacketSize.size; - p_qhd->fl_ctrl_ep_flag = ((xfer_type == usb_xfer_control) && (p_qhd->ep_speed != usb_speed_high)) ? 1 : 0; - p_qhd->nak_reload = 0; - - if (usb_xfer_interrupt == xfer_type) { - if (usb_speed_high == p_qhd->ep_speed) { - if (interval > USB_HIGH_SPPED_INTERVAL_MAX) { - return false; - } - - if (interval < 4) { /* sub millisecond interval */ - p_qhd->interval_ms = 0; - p_qhd->int_smask = (interval == 1) ? USB_BIN8(11111111) : - (interval == 2) ? USB_BIN8(10101010) : USB_BIN8(01000100); - } else { - p_qhd->interval_ms = (uint8_t)MIN(1 << (interval - 4), 255); - p_qhd->int_smask = HPM_BITSMASK(1, interval % 8); - } - } else { - if (interval == 0) { - return false; - } - - /* Full/Low:(EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes */ - p_qhd->int_smask = 0x01; - p_qhd->fl_int_cmask = USB_BIN8(11100); - p_qhd->interval_ms = interval; - } - } else { - /* Bulk/Control -> smask = cmask = 0 */ - p_qhd->int_smask = p_qhd->fl_int_cmask = 0; - } - - p_qhd->fl_hub_addr = handle->hub_addr; - p_qhd->fl_hub_port = handle->hub_port; - p_qhd->mult = 1; - - /* HCD Management Data */ - p_qhd->used = 1; - p_qhd->removing = 0; - p_qhd->p_qtd_list_head = NULL; - p_qhd->p_qtd_list_tail = NULL; - p_qhd->pid = usb_edpt_dir(ep_desc->bEndpointAddress) ? usb_pid_in : usb_pid_out; /* PID for TD under this endpoint */ - - /* Active, but no TD list */ - p_qhd->qtd_overlay.halted = 0; - p_qhd->qtd_overlay.next.terminate = 1; - p_qhd->qtd_overlay.alternate.terminate = 1; - - if (usb_xfer_bulk == xfer_type && p_qhd->ep_speed == usb_speed_high && p_qhd->pid == usb_pid_out) { - p_qhd->qtd_overlay.ping_err = 1; /* Do PING for Highspeed Bulk OUT, EHCI */ - } - - return true; -} - -hcd_qhd_t *usb_host_qhd_async_head(usb_host_handle_t *handle) -{ - /* control qhd of dev0 is used as async head */ - return usb_host_qhd_control(handle, 0); -} - -bool usb_host_qhd_has_xact_error(hcd_qhd_t *p_qhd) -{ - return (p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err); -} - -hcd_link_t *usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms) -{ - return (hcd_link_t *)&handle->hcd_data->period_head_arr[usb_log2(MIN(USB_HOST_FRAMELIST_SIZE, interval_ms))]; -} - -/*************************************************************/ -/* qtd functions */ -/*************************************************************/ -static hcd_qtd_t *usb_host_qtd_find_free(usb_host_handle_t *handle) -{ - for (uint32_t i = 0; i < USB_HCD_MAX_QTD_COUNT; i++) { - if (!handle->hcd_data->qtd_pool[i].used) { - return &handle->hcd_data->qtd_pool[i]; - } - } - - return NULL; -} - -static hcd_qtd_t *usb_host_qtd_next(hcd_qtd_t const *p_qtd) -{ - return (hcd_qtd_t *)usb_host_align32(p_qtd->next.address); -} - -static void usb_host_qtd_insert_to_qhd(hcd_qhd_t *p_qhd, hcd_qtd_t *p_qtd_new) -{ - if (p_qhd->p_qtd_list_head == NULL) { /* empty list */ - p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = p_qtd_new; - } else { - p_qhd->p_qtd_list_tail->next.address = (uint32_t)p_qtd_new; - p_qhd->p_qtd_list_tail = p_qtd_new; - } -} - -static void usb_host_qtd_init(hcd_qtd_t *p_qtd, void *buffer, uint16_t total_bytes) -{ - memset(p_qtd, 0, sizeof(hcd_qtd_t)); - - p_qtd->used = 1; - p_qtd->next.terminate = 1; /* init to null */ - p_qtd->alternate.terminate = 1; /* not used, always set to terminated */ - p_qtd->active = 1; - p_qtd->err_count = 3; - p_qtd->data_toggle = 0; - p_qtd->total_bytes = total_bytes; - p_qtd->expected_bytes = total_bytes; - - if (buffer != NULL) { - p_qtd->buffer[0] = (uint32_t)buffer; - - for (uint8_t i = 1; i < USB_SOC_DCD_QHD_BUFFER_COUNT; i++) { - p_qtd->buffer[i] |= usb_host_align4k(p_qtd->buffer[i-1]) + 4096UL; - } - } -} - -void usb_host_qtd_remove_1st_from_qhd(hcd_qhd_t *p_qhd) -{ - if (p_qhd->p_qtd_list_head == p_qhd->p_qtd_list_tail) { /* last TD --> make it NULL */ - p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = NULL; - } else { - p_qhd->p_qtd_list_head = usb_host_qtd_next(p_qhd->p_qtd_list_head); - } -} - -hcd_qtd_t *usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr) -{ - return &handle->hcd_data->control[dev_addr].qtd; -} - -static void usb_host_init_async_list(usb_host_handle_t *handle) -{ - hcd_qhd_t *async_head = usb_host_qhd_async_head(handle); - - memset(async_head, 0, sizeof(hcd_qhd_t)); - - async_head->next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)async_head); /* circular list, next is itself */ - async_head->next.type = usb_qtype_qhd; - async_head->head_list_flag = 1; - async_head->qtd_overlay.halted = 1; - async_head->qtd_overlay.next.terminate = 1; - - usb_hcd_set_async_list_addr(handle->regs, core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)async_head)); -} - -static void usb_host_init_periodic_list(usb_host_handle_t *handle) -{ - hcd_link_t *framelist; - hcd_link_t *period_1ms; - - /* Build the polling interval tree with 1 ms, 2 ms, 4 ms and 8 ms (framesize) only */ - for (uint32_t i = 0; i < 4; i++) { - handle->hcd_data->period_head_arr[i].int_smask = 1; /* queue head in period list must have non-zero smask */ - handle->hcd_data->period_head_arr[i].qtd_overlay.halted = 1; /* dummy node, always inactive */ - } - - framelist = handle->hcd_data->period_framelist; - period_1ms = usb_host_get_period_head(handle, USB_PERIOD_1MS); - - /* all links --> period_head_arr[0] (1ms) - * 0, 2, 4, 6 etc --> period_head_arr[1] (2ms) - * 1, 5 --> period_head_arr[2] (4ms) - * 3 --> period_head_arr[3] (8ms) - */ - for (uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i++) { - framelist[i].address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)period_1ms); - framelist[i].type = usb_qtype_qhd; - } - - for (uint32_t i = 0; i < USB_HOST_FRAMELIST_SIZE; i += 2) { - usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_2MS), usb_qtype_qhd); - } - - for (uint32_t i = 1; i < USB_HOST_FRAMELIST_SIZE; i += 4) { - usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_4MS), usb_qtype_qhd); - } - - for (uint32_t i = 3; i < USB_HOST_FRAMELIST_SIZE; i += 8) { - usb_host_list_insert(framelist + i, usb_host_get_period_head(handle, USB_PERIOD_8MS), usb_qtype_qhd); - } - - period_1ms->terminate = 1; - - usb_hcd_set_periodic_list_addr(handle->regs, core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)framelist)); -} - -/* enable vbus output */ -static void usb_host_vbus_ctrl(usb_host_handle_t *handle) -{ - handle->hcd_vbus_ctrl_cb(handle->rhport, 1); -} - -bool usb_host_init(usb_host_handle_t *handle, uint32_t int_mask, uint16_t framelist_size) -{ - usb_hcd_init(handle->regs, int_mask, framelist_size); - memset(handle->hcd_data, 0, sizeof(hcd_data_t)); - usb_host_init_async_list(handle); - usb_host_init_periodic_list(handle); - usb_host_vbus_ctrl(handle); - usb_hcd_run(handle->regs); - usb_hcd_enable_port_power(handle->regs); - return true; -} - -void usb_host_port_reset(usb_host_handle_t *handle) -{ - usb_hcd_port_reset(handle->regs); -} - -uint32_t usb_host_uframe_number(usb_host_handle_t *handle) -{ - return handle->hcd_data->uframe_number + usb_hcd_get_frame_index(handle->regs); -} - -bool usb_host_get_port_ccs(usb_host_handle_t *handle) -{ - return usb_get_port_ccs(handle->regs); -} - -bool usb_host_port_csc(usb_host_handle_t *handle) -{ - return usb_hcd_get_port_csc(handle->regs); -} - -uint32_t usb_host_status_flags(usb_host_handle_t *handle) -{ - return usb_get_status_flags(handle->regs); -} - -uint32_t usb_host_interrupts(usb_host_handle_t *handle) -{ - return usb_get_interrupts(handle->regs); -} - -void usb_host_clear_status_flags(usb_host_handle_t *handle, uint32_t status) -{ - usb_clear_status_flags(handle->regs, status); -} - -uint8_t usb_host_get_port_speed(usb_host_handle_t *handle) -{ - return usb_get_port_speed(handle->regs); -} - -/* Close all opened endpoint belong to this device */ -void usb_host_device_close(usb_host_handle_t *handle, uint8_t dev_addr) -{ - /* skip dev0 */ - if (dev_addr == USB_DEFAULT_ADDR) { - return; - } - - /* Remove from async list */ - usb_host_list_remove_qhd_by_addr((hcd_link_t *) usb_host_qhd_async_head(handle), dev_addr); - - /* Remove from all interval period list */ - for (uint8_t i = 0; i < ARRAY_SIZE(handle->hcd_data->period_head_arr); i++) { - usb_host_list_remove_qhd_by_addr((hcd_link_t *)&handle->hcd_data->period_head_arr[i], dev_addr); - } - - /* Async doorbell (EHCI for operational details) */ - usb_hcd_set_command(handle->regs, USB_USBCMD_IAA_MASK); -} - -/*--------------------------------------------------------------------- - * Control Pipe API - *--------------------------------------------------------------------- - */ -bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) -{ - uint8_t const epnum = usb_edpt_number(ep_addr); - uint8_t const dir = usb_edpt_dir(ep_addr); - hcd_qhd_t *qhd; - hcd_qtd_t *qtd; - hcd_qhd_t *p_qhd; - hcd_qtd_t *p_qtd; - - if (buffer != NULL) { - buffer = (uint8_t *)core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)buffer); - } - - if (epnum == 0) { - qhd = usb_host_qhd_control(handle, dev_addr); - qtd = usb_host_qtd_control(handle, dev_addr); - - usb_host_qtd_init(qtd, buffer, buflen); - - /* first first data toggle is always 1 (data & setup stage) */ - qtd->data_toggle = 1; - qtd->pid = dir ? usb_pid_in : usb_pid_out; - - qtd->int_on_complete = 1; - qtd->next.terminate = 1; - - /* sw region */ - qhd->p_qtd_list_head = qtd; - qhd->p_qtd_list_tail = qtd; - - /* attach TD */ - qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)qtd); - } else { - p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); - p_qtd = usb_host_qtd_find_free(handle); - - if (p_qhd == NULL || p_qtd == NULL) { - return false; - } - - usb_host_qtd_init(p_qtd, buffer, buflen); - p_qtd->pid = p_qhd->pid; - - /* Insert TD to QH */ - usb_host_qtd_insert_to_qhd(p_qhd, p_qtd); - p_qhd->p_qtd_list_tail->int_on_complete = 1; - - /* attach head QTD to QHD start transferring */ - p_qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)p_qhd->p_qtd_list_head); - } - - return true; -} - -bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint8_t *setup_packet) -{ - uint32_t *p = NULL; - - hcd_qhd_t *qhd = &handle->hcd_data->control[dev_addr].qhd; - hcd_qtd_t *td = &handle->hcd_data->control[dev_addr].qtd; - - if (setup_packet != NULL) { - p = (uint32_t *)core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)setup_packet); - } - - usb_host_qtd_init(td, (void *)p, USB_SETUP_PACKET_LEN); - td->pid = usb_pid_setup; - td->int_on_complete = 1; - td->next.terminate = 1; - - /* sw region */ - qhd->p_qtd_list_head = td; - qhd->p_qtd_list_tail = td; - - /* attach TD */ - qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)td); - - return true; -} - -bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const *ep_desc) -{ - hcd_qhd_t *p_qhd = NULL; - hcd_link_t *list_head = NULL; - - if (ep_desc->bmAttributes.xfer == usb_xfer_isochronous) { - return false; - } - - /* Prepare Queue Head */ - if (ep_desc->bEndpointAddress == 0) { - p_qhd = usb_host_qhd_control(handle, dev_addr); - } else { - p_qhd = usb_host_qhd_find_free(handle); - } - - /* Initialize Qhd */ - usb_host_qhd_init(handle, p_qhd, dev_addr, ep_desc); - - switch (ep_desc->bmAttributes.xfer) { - case usb_xfer_control: - case usb_xfer_bulk: - list_head = (hcd_link_t *)usb_host_qhd_async_head(handle); /* control of dev0 is always present as async head */ - break; - - case usb_xfer_interrupt: - list_head = usb_host_get_period_head(handle, p_qhd->interval_ms); - break; - - case usb_xfer_isochronous: - break; - - default: - break; - } - - /* Insert to list */ - usb_host_list_insert(list_head, (hcd_link_t *)p_qhd, usb_qtype_qhd); - - return true; -} - -bool usb_host_pipe_queue_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes) -{ - hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); - hcd_qtd_t *p_qtd = usb_host_qtd_find_free(handle); - - if (p_qhd == NULL || p_qtd == NULL) { - return false; - } - - /* Initialize QTD */ - usb_host_qtd_init(p_qtd, buffer, total_bytes); - p_qtd->pid = p_qhd->pid; - - /* Insert TD to TD list */ - usb_host_qtd_insert_to_qhd(p_qhd, p_qtd); - - return true; -} - -bool usb_host_pipe_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete) -{ - hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); - - if (usb_host_pipe_queue_xfer(handle, dev_addr, ep_addr, buffer, total_bytes) == false) { - return false; - } - - if (int_on_complete) { - /* the just added qtd is pointed by list_tail */ - p_qhd->p_qtd_list_tail->int_on_complete = 1; - } - - /* attach head QTD to QHD start transferring */ - p_qhd->qtd_overlay.next.address = core_local_mem_to_sys_address(USB_HOST_MCU_CORE, (uint32_t)p_qhd->p_qtd_list_head); - - return true; -} - -bool usb_host_edpt_busy(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) -{ - hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); - - return ((!p_qhd->qtd_overlay.halted) && (p_qhd->p_qtd_list_head != NULL)); -} - -bool usb_host_edpt_stalled(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) -{ - hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); - - return p_qhd->qtd_overlay.halted && !usb_host_qhd_has_xact_error(p_qhd); -} - -bool usb_host_edpt_clear_stall(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr) -{ - hcd_qhd_t *p_qhd = usb_host_qhd_get_from_addr(handle, dev_addr, ep_addr); - - p_qhd->qtd_overlay.halted = 0; - - return true; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h b/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h deleted file mode 100644 index b948938342e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/components/usb/host/hpm_usb_host.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_USB_HOST_H -#define HPM_USB_HOST_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_usb_drv.h" -#include "hpm_common.h" -#include "hpm_soc_feature.h" - -/*--------------------------------------------------------------------- - * Macros - *--------------------------------------------------------------------- - */ - - -#ifndef USB_HCD_PERIODIC_ARR_COUNT -#define USB_HCD_PERIODIC_ARR_COUNT (4U) -#endif - -#ifndef USB_HCD_MAX_CONNECTED_DEVICES -#define USB_HCD_MAX_CONNECTED_DEVICES (5U) -#endif - -#ifndef USB_HCD_MAX_QHD_COUNT -#define USB_HCD_MAX_QHD_COUNT (USB_HCD_MAX_CONNECTED_DEVICES * 16U * 2U) -#endif - -#ifndef USB_HCD_MAX_QTD_COUNT -#define USB_HCD_MAX_QTD_COUNT (USB_HCD_MAX_QHD_COUNT * 2U) -#endif -/*--------------------------------------------------------------------- - * Enum Declarations - *--------------------------------------------------------------------- - */ -typedef enum { - usb_max_itd = 4, - usb_max_sitd = 16 -} usb_max_xtd_t; - -typedef enum { - usb_qtype_itd = 0, - usb_qtype_qhd, - usb_qtype_sitd, - usb_qtype_fstn -} usb_qtype_t; - -typedef enum { - usb_pid_out = 0, - usb_pid_in, - usb_pid_setup -} usb_pid_t; - -typedef enum { - usb_speed_full = 0, - usb_speed_low, - usb_speed_high, - usb_speed_invalid = 0xff, -} usb_speed_t; - -typedef enum { - usb_cmd_pos_run_stop = 0, - usb_cmd_pos_framelist_szie = 2, - usb_cmd_pos_period_enable = 4, - usb_cmd_pos_async_enable = 5, - usb_cmd_pos_framelist_size_msb = 15, - usb_cmd_pos_interrupt_threshold = 16 -} usb_cmd_pos_t; - -typedef enum { - usb_portsc_mask_current_connect_status = HPM_BITSMASK(1, 0), - usb_portsc_mask_connect_status_change = HPM_BITSMASK(1, 1), - usb_portsc_mask_port_eanbled = HPM_BITSMASK(1, 2), - usb_portsc_mask_port_enable_chagne = HPM_BITSMASK(1, 3), - usb_portsc_mask_over_current_change = HPM_BITSMASK(1, 5), - usb_portsc_mask_port_reset = HPM_BITSMASK(1, 8), - - usb_portsc_mask_all = usb_portsc_mask_connect_status_change - | usb_portsc_mask_port_enable_chagne - | usb_portsc_mask_over_current_change -} usb_portsc_change_mask_t; - -/* Link pointer */ -typedef union { - volatile uint32_t address; - struct { - volatile uint32_t terminate : 1; - volatile uint32_t type : 2; - }; -} hcd_link_t; - -/* Queue Element Transfer Descriptor */ -/* Qtd is used to declare overlay in hcd_qhd_t */ -typedef struct { - /* Word 0: Next QTD Pointer */ - volatile hcd_link_t next; - - /* Word 1: Alternate Next QTD Pointer (not used) */ - union{ - volatile hcd_link_t alternate; - struct { - volatile uint32_t : 5; - volatile uint32_t used : 1; - volatile uint32_t : 10; - volatile uint32_t expected_bytes : 16; - }; - }; - - /* Word 2: qTQ Token */ - volatile uint32_t ping_err : 1 ; /* For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator */ - volatile uint32_t non_hs_split_state : 1 ; /* Used by HC to track the state of slipt transaction */ - volatile uint32_t non_hs_missed_uframe : 1 ; /* HC misses a complete slip transaction */ - volatile uint32_t xact_err : 1 ; /* Error (Timeout, CRC, Bad PID ... ) */ - volatile uint32_t babble_err : 1 ; /* Babble detected, also set Halted bit to 1 */ - volatile uint32_t buffer_err : 1 ; /* Data overrun/underrun error */ - volatile uint32_t halted : 1 ; /* Serious error or STALL received */ - volatile uint32_t active : 1 ; /* Start transfer, clear by HC when complete */ - volatile uint32_t pid : 2 ; /* 0: OUT, 1: IN, 2 Setup */ - volatile uint32_t err_count : 2 ; /* Error Counter of consecutive errors */ - volatile uint32_t current_page : 3 ; /* Index into the qTD buffer pointer list */ - volatile uint32_t int_on_complete : 1 ; /* Interrupt on complete */ - volatile uint32_t total_bytes : 15 ; /* Transfer bytes, decreased during transaction */ - volatile uint32_t data_toggle : 1 ; /* Data Toggle bit */ - - /* Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page */ - volatile uint32_t buffer[USB_SOC_DCD_QHD_BUFFER_COUNT]; -} hcd_qtd_t; - -/* Queue Head */ -typedef struct { - /* Word 0: Next QHD */ - hcd_link_t next; - - /* Word 1: Endpoint Characteristics */ - volatile uint32_t dev_addr : 7 ; /* device address */ - volatile uint32_t fl_inactive_next_xact : 1 ; /* Only valid for Periodic with Full/Slow speed */ - volatile uint32_t ep_number : 4 ; /* EP number */ - volatile uint32_t ep_speed : 2 ; /* 0: Full, 1: Low, 2: High */ - volatile uint32_t data_toggle_control : 1 ; /* 0: use DT in qHD, 1: use DT in qTD */ - volatile uint32_t head_list_flag : 1 ; /* Head of the queue */ - volatile uint32_t max_packet_size : 11 ; /* Max packet size */ - volatile uint32_t fl_ctrl_ep_flag : 1 ; /* 1 if is Full/Low speed control endpoint */ - volatile uint32_t nak_reload : 4 ; /* Used by HC */ - - /* Word 2: Endpoint Capabilities */ - volatile uint32_t int_smask : 8 ; /* Interrupt Schedule Mask */ - volatile uint32_t fl_int_cmask : 8 ; /* Split Completion Mask for Full/Slow speed */ - volatile uint32_t fl_hub_addr : 7 ; /* Hub Address for Full/Slow speed */ - volatile uint32_t fl_hub_port : 7 ; /* Hub Port for Full/Slow speed */ - volatile uint32_t mult : 2 ; /* Transaction per micro frame */ - - /* Word 3: Current qTD Pointer */ - volatile uint32_t qtd_addr; - - /* Word 4-11: Transfer Overlay */ - volatile hcd_qtd_t qtd_overlay; - - /*-------------------------------------------------------------------- - * Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes - * thus there are 16 bytes padding free that we can make use of. - *-------------------------------------------------------------------- - */ - uint8_t used; - uint8_t removing; /* removed from async list, waiting for async advance */ - uint8_t pid; - uint8_t interval_ms; /* polling interval in frames (or millisecond) */ - - uint16_t total_xferred_bytes; /* number of bytes xferred until a qtd with ioc bit set */ - uint8_t reserved2[2]; - - hcd_qtd_t * volatile p_qtd_list_head; /* head of the scheduled TD list */ - hcd_qtd_t * volatile p_qtd_list_tail; /* tail of the scheduled TD list */ -} hcd_qhd_t; - -typedef struct { - hcd_link_t period_framelist[USB_HOST_FRAMELIST_SIZE]; - - /* for ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) - * [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms - */ - hcd_qhd_t period_head_arr[USB_HCD_PERIODIC_ARR_COUNT]; - - /* Note control qhd of dev0 is used as head of async list */ - struct { - hcd_qhd_t qhd; - hcd_qtd_t qtd; - } control[USB_HCD_MAX_CONNECTED_DEVICES + 1]; - - hcd_qhd_t qhd_pool[USB_HCD_MAX_QHD_COUNT]; - hcd_qtd_t qtd_pool[USB_HCD_MAX_QTD_COUNT]; - - uint32_t uframe_number; -} hcd_data_t; - -typedef struct { - uint8_t rhport; - uint8_t ep_speed; - uint8_t hub_addr; - uint8_t hub_port; - USB_Type *regs; - hcd_data_t *hcd_data; - void (*hcd_vbus_ctrl_cb)(uint8_t rhport, uint8_t level); -} usb_host_handle_t; - -/* USB Endpoint Descriptor */ -typedef struct __attribute__ ((packed)) -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - - struct __attribute__ ((packed)) { - uint8_t xfer : 2; - uint8_t sync : 2; - uint8_t usage : 2; - uint8_t : 2; - } bmAttributes; - - struct __attribute__ ((packed)) { - uint16_t size : 11; - uint16_t hs_period_mult : 2; - uint16_t : 3; - } wMaxPacketSize; - - uint8_t bInterval; -} usb_desc_endpoint_t; - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/* Get direction from Endpoint address */ -static inline usb_dir_t usb_edpt_dir(uint8_t addr) -{ - return (addr & usb_dir_in_mask) ? usb_dir_in : usb_dir_out; -} - -/* Get Endpoint number from address */ -static inline uint8_t usb_edpt_number(uint8_t addr) -{ - return (uint8_t)(addr & (~usb_dir_in_mask)); -} - -/* Get Endpoint address */ -static inline uint8_t usb_edpt_addr(uint8_t num, uint8_t dir) -{ - return (uint8_t)(num | (dir ? usb_dir_in_mask : 0)); -} - -static inline uint32_t usb_host_align16(uint32_t value) { return (value & 0xFFFFFFF0UL); } -static inline uint32_t usb_host_align32(uint32_t value) { return (value & 0xFFFFFFE0UL); } -static inline uint32_t usb_host_align4k(uint32_t value) { return (value & 0xFFFFF000UL); } -static inline uint32_t usb_host_offset4k(uint32_t value) { return (value & 0xFFFUL); } - -bool usb_host_qhd_has_xact_error(hcd_qhd_t *p_qhd); -bool usb_host_qhd_has_xact_error(hcd_qhd_t *p_qhd); -void usb_host_qtd_remove_1st_from_qhd(hcd_qhd_t *p_qhd); -hcd_link_t *usb_host_list_next(hcd_link_t *p_link_pointer); -hcd_link_t *usb_host_get_period_head(usb_host_handle_t *handle, uint8_t interval_ms); -hcd_qhd_t *usb_host_qhd_async_head(usb_host_handle_t *handle); -hcd_qhd_t *usb_host_qhd_next(hcd_qhd_t const *p_qhd); -hcd_qtd_t *usb_host_qtd_control(usb_host_handle_t *handle, uint8_t dev_addr); -uint32_t usb_host_uframe_number(usb_host_handle_t *handle); -uint32_t usb_host_status_flags(usb_host_handle_t *handle); -uint32_t usb_host_interrupts(usb_host_handle_t *handle); -void usb_host_clear_status_flags(usb_host_handle_t *handle, uint32_t status); -uint8_t usb_host_get_port_speed(usb_host_handle_t *handle); -void usb_host_port_reset(usb_host_handle_t *handle); -bool usb_host_init(usb_host_handle_t *handle, uint32_t int_mask, uint16_t framelist_size); -bool usb_host_get_port_ccs(usb_host_handle_t *handle); -bool usb_host_port_csc(usb_host_handle_t *handle); -void usb_host_device_close(usb_host_handle_t *handle, uint8_t dev_addr); -bool usb_host_edpt_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen); -bool usb_host_setup_send(usb_host_handle_t *handle, uint8_t dev_addr, const uint8_t *setup_packet); -bool usb_host_edpt_open(usb_host_handle_t *handle, uint8_t dev_addr, usb_desc_endpoint_t const *ep_desc); -bool usb_host_pipe_queue_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes); -bool usb_host_pipe_xfer(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete); -bool usb_host_edpt_busy(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); -bool usb_host_edpt_stalled(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); -bool usb_host_edpt_clear_stall(usb_host_handle_t *handle, uint8_t dev_addr, uint8_t ep_addr); - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_USB_HOST_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h deleted file mode 100644 index 39e9e48c797..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_acmp_drv.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ACMP_DRV_H -#define HPM_ACMP_DRV_H - -#include "hpm_common.h" -#include "hpm_acmp_regs.h" - -/** - * @brief ACMP driver APIs - * @defgroup acmp_interface ACMP driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ - -/** - * @brief ACMP hysteresis level - */ -#define ACMP_HYST_LEVEL_0 (0U) -#define ACMP_HYST_LEVEL_1 (1U) -#define ACMP_HYST_LEVEL_2 (2U) -#define ACMP_HYST_LEVEL_3 (3U) - -/** - * @brief ACMP input channel number - */ -#define ACMP_INPUT_DAC_OUT (0U) -#define ACMP_INPUT_ANALOG_1 (1U) -#define ACMP_INPUT_ANALOG_2 (2U) -#define ACMP_INPUT_ANALOG_3 (3U) -#define ACMP_INPUT_ANALOG_4 (4U) -#define ACMP_INPUT_ANALOG_5 (5U) -#define ACMP_INPUT_ANALOG_6 (6U) -#define ACMP_INPUT_ANALOG_7 (7U) - -/** - * @brief ACMP output digital filter mode - */ -#define ACMP_FILTER_MODE_BYPASS (0U) -#define ACMP_FILTER_MODE_CHANGE_IMMEDIATELY (4U) -#define ACMP_FILTER_MODE_CHANGE_AFTER_FILTER (5U) -#define ACMP_FILTER_MODE_STABLE_LOW (6U) -#define ACMP_FILTER_MODE_STABLE_HIGH (7U) - -/** - * @brief ACMP rising/falling flage mask - */ -#define ACMP_EVENT_RISING_EDGE (1U) -#define ACMP_EVENT_FALLING_EDGE (2U) - -/** - * @brief ACMP channel config - */ - -typedef struct acmp_channel_config { - uint8_t plus_input; - uint8_t minus_input; - uint8_t filter_mode; - uint8_t hyst_level; - bool enable_cmp_output; - bool enable_window_mode; - bool invert_output; - bool enable_clock_sync; - bool bypass_filter; - bool enable_dac; - bool enable_hpmode; - uint16_t filter_length; /* ACMP output digital filter length in ACMP clock cycle */ -} acmp_channel_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief ACMP channel config DAC output value - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] value DAC output value - */ -static inline void acmp_channel_config_dac(ACMP_Type *ptr, uint8_t ch, uint32_t value) -{ - ptr->CHANNEL[ch].DACCFG = ACMP_CHANNEL_DACCFG_DACCFG_SET(value); -} - -/** - * @brief ACMP channel clear status - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] mask : - * @arg ACMP_EVENT_RISING_EDGE: ACMP output rising flag - * @arg ACMP_EVENT_FALLING_EDGE: ACMP output fall flag - */ -static inline void acmp_channel_clear_status(ACMP_Type *ptr, uint8_t ch, uint32_t mask) -{ - ptr->CHANNEL[ch].SR = mask; -} - -/** - * @brief ACMP channel get status - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @retval ACMP channel's status - */ -static inline uint32_t acmp_channel_get_status(ACMP_Type *ptr, uint8_t ch) -{ - return ptr->CHANNEL[ch].SR; -} - -/** - * @brief ACMP channel enable DMA request - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] mask : - * @arg ACMP_EVENT_RISING_EDGE: ACMP output rising flag - * @arg ACMP_EVENT_FALLING_EDGE: ACMP output fall flag - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_dma_request_enable(ACMP_Type *ptr, uint8_t ch, - uint32_t mask, bool enable) -{ - ptr->CHANNEL[ch].DMAEN = (ptr->CHANNEL[ch].DMAEN & ~mask) - | (enable ? mask : 0); -} - -/** - * @brief ACMP channel enable IRQ - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] mask : - * @arg ACMP_EVENT_RISING_EDGE: ACMP output rising flag - * @arg ACMP_EVENT_FALLING_EDGE: ACMP output fall flag - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_irq(ACMP_Type *ptr, uint8_t ch, - uint32_t mask, bool enable) -{ - ptr->CHANNEL[ch].IRQEN = (ptr->CHANNEL[ch].IRQEN & ~mask) - | (enable ? mask : 0); -} - -/** - * @brief ACMP channel enable DAC - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_dac(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_DACEN_MASK) - | ACMP_CHANNEL_CFG_DACEN_SET(enable); -} - -/** - * @brief ACMP channel enable high performance mode - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_hpmode(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HPMODE_MASK) - | ACMP_CHANNEL_CFG_HPMODE_SET(enable); -} - -/** - * @brief ACMP channel enable hysteresis level - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] level: ACMP hysteresis level - */ -static inline void acmp_channel_set_hyst(ACMP_Type *ptr, uint8_t ch, uint8_t level) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_HYST_MASK) - | ACMP_CHANNEL_CFG_HYST_SET(level); -} - -/** - * @brief ACMP channel enable comparator - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_cmp(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPEN_MASK) - | ACMP_CHANNEL_CFG_CMPEN_SET(enable); -} - -/** - * @brief ACMP channel enable comparator output - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_cmp_output(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_CMPOEN_MASK) - | ACMP_CHANNEL_CFG_CMPOEN_SET(enable); -} - -/** - * @brief ACMP channel bypass comparator output filter - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: bypass - * @arg false: not bypass - */ -static inline void acmp_channel_cmp_output_bypass_filter(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTBYPS_MASK) - | ACMP_CHANNEL_CFG_FLTBYPS_SET(!enable); -} - -/** - * @brief ACMP channel enable comparator window mode - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_cmp_window_mode(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_WINEN_MASK) - | ACMP_CHANNEL_CFG_WINEN_SET(enable); -} - -/** - * @brief ACMP channel invert comparator output - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: invert - * @arg false: not invert - */ -static inline void acmp_channel_invert_output(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_OPOL_MASK) - | ACMP_CHANNEL_CFG_OPOL_SET(enable); -} - -/** - * @brief ACMP channel set comparator output filter mode - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] filter: ACMP output digital filter mode definition - */ -static inline void acmp_channel_set_filter_mode(ACMP_Type *ptr, uint8_t ch, uint8_t filter) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTMODE_MASK) - | ACMP_CHANNEL_CFG_FLTMODE_SET(filter); -} - -/** - * @brief ACMP channel enable comparator output sync with clock - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] enable: - * @arg true: enable - * @arg false: disable - */ -static inline void acmp_channel_enable_sync(ACMP_Type *ptr, uint8_t ch, bool enable) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_SYNCEN_MASK) - | ACMP_CHANNEL_CFG_SYNCEN_SET(enable); -} - -/** - * @brief ACMP channel set comparator output filter length - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] filter_length: filter length in clock cycles - */ -static inline void acmp_channel_set_filter_length(ACMP_Type *ptr, uint8_t ch, uint16_t filter_length) -{ - ptr->CHANNEL[ch].CFG = (ptr->CHANNEL[ch].CFG & ~ACMP_CHANNEL_CFG_FLTLEN_MASK) - | ACMP_CHANNEL_CFG_FLTLEN_SET(filter_length); -} - -/** - * @brief ADC channel config - * - * @param [in] ptr ACMP base address - * @param [in] ch ACMP channel number - * @param [in] config: acmp_channel_config_t - * @param [in] enable: - * @arg true: enable comparator - * @arg false: disable comparator - * - * @retval hpm_stat_t - */ -hpm_stat_t acmp_channel_config(ACMP_Type *ptr, uint8_t ch, acmp_channel_config_t *config, bool enable); - -/** - * @brief ADC channel get default config setting - * - * @param [in] ptr ACMP base address - * @param [out] config: acmp_channel_config_t - */ -void acmp_channel_get_default_config(ACMP_Type *ptr, acmp_channel_config_t *config); - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_ACMP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h deleted file mode 100644 index ad49a8bcc61..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc12_drv.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ADC12_DRV_H -#define HPM_ADC12_DRV_H - -#include "hpm_common.h" -#include "hpm_adc12_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief ADC12 driver APIs - * @defgroup adc12_interface ADC12 driver APIs - * @ingroup adc_interfaces - * @{ - */ - -/** @brief Define ADC12 validity check for the signal type */ -#define ADC12_IS_SIGNAL_TYPE_INVALID(TYPE) (TYPE > (uint32_t)adc12_sample_signal_count) - -/** @brief Define ADC12 validity check for the channel number */ -#define ADC12_IS_CHANNEL_INVALID(CH) (CH > ADC12_SOC_MAX_CH_NUM) - -/** @brief Define ADC12 validity check for the channel sample cycle */ -#define ADC12_IS_CHANNEL_SAMPLE_CYCLE_INVALID(CYC) (CYC == 0) - -/** @brief Define ADC12 validity check for the trigger number */ -#define ADC12_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM) - -/** @brief Define ADC12 validity check for the trigger length */ -#define ADC12_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN) - -/** @brief Define ADC12 validity check for the sequence length */ -#define ADC12_IS_SEQ_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_LEN)) - -/** @brief Define ADC12 validity check for the DMA buffer length in the sequence mode */ -#define ADC12_IS_SEQ_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES)) - -/** @brief Define ADC12 validity check for the DMA buffer length in the preemption mode */ -#define ADC12_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)) - -/** @brief Define ADC12 sample signal types. */ -typedef enum { - adc12_sample_signal_single_ended = 0, - adc12_sample_signal_differential = 1, - adc12_sample_signal_count = 2 -} adc12_sample_signal_t; - -/** @brief Define ADC12 resolutions. */ -typedef enum { - adc12_res_6_bits = 0, - adc12_res_8_bits, - adc12_res_10_bits, - adc12_res_12_bits -} adc12_resolution_t; - -/** @brief Define ADC12 conversion modes. */ -typedef enum { - adc12_conv_mode_oneshot = 0, - adc12_conv_mode_period, - adc12_conv_mode_sequence, - adc12_conv_mode_preemption -} adc12_conversion_mode_t; - -/** @brief Define ADC12 Clock Divider */ -typedef enum { - adc12_clock_divider_1 = 1, - adc12_clock_divider_2, - adc12_clock_divider_3, - adc12_clock_divider_4, - adc12_clock_divider_5, - adc12_clock_divider_6, - adc12_clock_divider_7, - adc12_clock_divider_8, - adc12_clock_divider_9, - adc12_clock_divider_10, - adc12_clock_divider_11, - adc12_clock_divider_12, - adc12_clock_divider_13, - adc12_clock_divider_14, - adc12_clock_divider_15, - adc12_clock_divider_16, -} adc12_clock_divider_t; - -/** @brief Define ADC12 irq events. */ -typedef enum { - /** This mask indicates that a trigger conversion is complete. */ - adc12_event_trig_complete = ADC12_INT_STS_TRIG_CMPT_MASK, - - /** This mask indicates that a conflict caused by software-triggered conversions. */ - adc12_event_trig_sw_conflict = ADC12_INT_STS_TRIG_SW_CFLCT_MASK, - - /** This mask indicates that a conflict caused by hardware-triggered conversions. */ - adc12_event_trig_hw_conflict = ADC12_INT_STS_TRIG_HW_CFLCT_MASK, - - /** This mask indicates that a conflict caused when bus reading from different channels. */ - adc12_event_read_conflict = ADC12_INT_STS_READ_CFLCT_MASK, - - /** This mask indicates that a conflict caused by sequence-triggered conversions. */ - adc12_event_seq_sw_conflict = ADC12_INT_STS_SEQ_SW_CFLCT_MASK, - - /** This mask indicates that a conflict caused by hardware-triggered conversions. */ - adc12_event_seq_hw_conflict = ADC12_INT_STS_SEQ_HW_CFLCT_MASK, - - /** This mask indicates that DMA is stopped currently. */ - adc12_event_seq_dma_abort = ADC12_INT_STS_SEQ_DMAABT_MASK, - - /** This mask indicates that all of the configured conversion(s) in a queue is(are) complete. */ - adc12_event_seq_full_complete = ADC12_INT_STS_SEQ_CMPT_MASK, - - /** This mask indicates that one of the configured conversion(s) in a queue is complete. */ - adc12_event_seq_single_complete = ADC12_INT_STS_SEQ_CVC_MASK, - - /** This mask indicates that DMA FIFO is full currently. */ - adc12_event_dma_fifo_full = ADC12_INT_STS_DMA_FIFO_FULL_MASK -} adc12_irq_event_t; - -/** @brief ADC12 common configuration struct. */ -typedef struct { - uint8_t res; - uint8_t conv_mode; - uint32_t adc_clk_div; - bool wait_dis; - bool sel_sync_ahb; - bool adc_ahb_en; -} adc12_config_t; - -/** @brief ADC12 channel configuration struct. */ -typedef struct { - uint8_t ch; - uint8_t diff_sel; - uint16_t thshdh; - uint16_t thshdl; - bool wdog_int_en; - uint8_t sample_cycle_shift; - uint32_t sample_cycle; -} adc12_channel_config_t; - -/** @brief ADC12 channel configuration struct. */ -typedef struct { - uint8_t ch; - uint16_t thshdh; - uint16_t thshdl; -} adc12_channel_threshold_t; - -/** @brief ADC12 DMA configuration struct. */ -typedef struct { - uint32_t *start_addr; - uint32_t buff_len_in_4bytes; - uint32_t stop_pos; - bool stop_en; -} adc12_dma_config_t; - -/** @brief ADC12 DMA configuration struct for the sequence mode. */ -typedef struct { - uint32_t :4; - uint32_t result :12; - uint32_t seq_num :4; - uint32_t :4; - uint32_t adc_ch :5; - uint32_t :2; - uint32_t cycle_bit :1; -} adc12_seq_dma_data_t; - -/** @brief ADC12 DMA configuration struct for the preemption mode. */ -typedef struct { - uint32_t :4; - uint32_t result :12; - uint32_t seq_num :2; - uint32_t :2; - uint32_t trig_ch :4; - uint32_t adc_ch :5; - uint32_t :2; - uint32_t cycle_bit :1; -} adc12_pmt_dma_data_t; - -/** @brief ADC12 configuration struct for the period mode. */ -typedef struct { - uint8_t ch; - uint8_t prescale; - uint8_t period_count; -} adc12_prd_config_t; - -/** @brief ADC12 queue configuration struct for the sequence mode. */ -typedef struct { - bool seq_int_en; - uint8_t ch; -} adc12_seq_queue_config_t; - -/** @brief ADC12 configuration struct for the sequence mode. */ -typedef struct { - adc12_seq_queue_config_t queue[ADC_SOC_SEQ_MAX_LEN]; - bool restart_en; - bool cont_en; - bool sw_trig_en; - bool hw_trig_en; - uint8_t seq_len; -} adc12_seq_config_t; - -/** @brief ADC12 trigger configuration struct for the preemption mode. */ -typedef struct { - bool inten[ADC_SOC_MAX_TRIG_CH_LEN]; - uint8_t adc_ch[ADC_SOC_MAX_TRIG_CH_LEN]; - uint8_t trig_ch; - uint8_t trig_len; -} adc12_pmt_config_t; - -#ifdef __cplusplus -extern "C" { -#endif -/** - * @name Initialization and Deinitialization - * @{ - */ - -/** - * @brief Get a default configuration for an ADC12 instance. - * - * @param[out] config A pointer to the configuration struct of @ref adc12_config_t. - */ -void adc12_get_default_config(adc12_config_t *config); - -/** - * @brief Get a default configuration for an ADC12 channel. - * - * @param[out] config A pointer to the configuration struct of @ref adc12_channel_config_t. - */ -void adc12_get_channel_default_config(adc12_channel_config_t *config); - -/** - * @brief De-initialize an ADC12 instance. - * - * @param[in] ptr An ADC12 peripheral base address. - * @return A result of de-initializing an ADC12 instance. - * @retval status_success De-initialize an ADC12 instance successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument De-initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_deinit(ADC12_Type *ptr); - -/** - * @brief Initialize an ADC12 instance. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] config A pointer to the configuration struct of @ref adc12_config_t. - * @return A result of initializing an ADC12 instance. - * @retval status_success Initialize an ADC12 instance successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC12 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config); - -/** - * @brief Initialize an ADC12 channel. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] config A pointer to the configuration struct of @ref adc12_channel_config_t. - * @return A result of initializing an ADC12 channel. - * @retval status_success Initialize an ADC12 channel successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config); - -/** - * @brief Get thresholds of an ADC12 channel - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] ch An ADC12 channel number - * @param[out] config A pointer to the structure of channel threshold - * @return A result of getting thresholds of an ADC12 channel . - * @retval status_success Initialize an ADC12 channel successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC12 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config); - -/** - * @brief Configure the the period mode for an ADC12 instance. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] config A pointer to the configuration struct of @ref adc12_prd_config_t. - * @return A result of configuring the the period mode for an ADC12 instance. - * @retval status_success Configure the the period mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config); - -/** - * @brief Configure the the sequence mode for an ADC12 instance. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] config A pointer to configuration struct of @ref adc12_seq_config_t. - * @return A result of configuring the the sequence mode for an ADC12 instance. - * @retval status_success Configure the the sequence mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config); - -/** - * @brief Configure the preemption mode for an ADC12 instance. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] config A pointer to configuration struct of @ref adc12_pmt_config_t. - * @return A result of configuring the preemption mode for an ADC12 instance. - * @retval status_success Configure the preemption mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config); - -/** @} */ - -/** - * @name DMA Control - * @{ - */ - -/** - * @brief Configure the stop position offset in the specified memory of DMA write operation for the sequence mode. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] stop_pos A stop position offset. - */ -static inline void adc12_set_seq_stop_pos(ADC12_Type *ptr, uint16_t stop_pos) -{ - ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_STOP_POS_MASK) - | ADC12_SEQ_DMA_CFG_STOP_POS_SET(stop_pos); -} - -/** - * @brief Configure the start address of DMA write operation for the preemption mode. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] addr A start address of DMA write operation. - */ -static inline void adc12_init_pmt_dma(ADC12_Type *ptr, uint32_t addr) -{ - ptr->TRG_DMA_ADDR = addr & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK; -} - -/** - * @brief Configure the start address of DMA write operation for the sequence mode. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] config A pointer to configuration struct of @ref adc12_dma_config_t. - * @return An implementation result of DMA initializing for the sequence mode - * @retval status_success ADC12 initialize in sequence mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument ADC12 initialize in sequence mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. - */ -hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *config); - -/** @} */ - -/** - * @name Status - * @{ - */ - -/** - * @brief Get all ADC12 status flags. - * - * @param[in] ptr An ADC12 peripheral base address. - * @return A mask indicating all corresponding interrupt statuses. - * @retval A mask. Please refer to @ref adc12_irq_event_t. - */ -static inline uint32_t adc12_get_status_flags(ADC12_Type *ptr) -{ - return ptr->INT_STS; -} - -/** - * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus - * until the ADC has completed its conversion. * - * - * @param[in] ptr An ADC12 peripheral base address. - * @deprecated This API will be removed from V2.0.x - */ -static inline void adc12_disable_busywait(ADC12_Type *ptr) -{ - ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_SET(1); -} - -/** - * @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus - * until the ADC completes the conversion. - * - * @param[in] ptr An ADC12 peripheral base address. - * @deprecated This API will be removed from V2.0.x - */ -static inline void adc12_enable_busywait(ADC12_Type *ptr) -{ - ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; -} - -/** - * @brief Set nonblocking read in oneshot mode. - * @note An ADC does not block access to the associated peripheral whether it completes a conversion or not. - * - * @param[in] ptr An ADC12 peripheral base address. - */ -static inline void adc12_set_nonblocking_read(ADC12_Type *ptr) -{ - ptr->BUF_CFG0 |= ADC12_BUF_CFG0_WAIT_DIS_MASK; -} - -/** - * @brief Set blocking read in oneshot mode. - * @note An ADC blocks access to the associated peripheral bus until it completes a conversion. - * - * @param[in] ptr An ADC12 peripheral base address. - */ -static inline void adc12_set_blocking_read(ADC12_Type *ptr) -{ - ptr->BUF_CFG0 &= ~ADC12_BUF_CFG0_WAIT_DIS_MASK; -} - -/** - * @brief Judge whether the current setting is none-blocking mode or not. - * - * @param[in] ptr An ADC12 peripheral base address. - * @return A result indicating the status of bus waiting. - * @retval True means that nonblocking reading. - * @retval False means that blocking reading. - * - */ -static inline bool adc12_is_nonblocking_mode(ADC12_Type *ptr) -{ - return (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0) ? true : false); -} - -/** - * @brief Get the status of a conversion validity. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] ch An ADC12 peripheral channel. - * @return Status indicating the validity of the current conversion result. - * - * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. - */ -static inline bool adc12_get_conv_valid_status(ADC12_Type *ptr, uint8_t ch) -{ - return ADC12_BUS_RESULT_VALID_GET(ptr->BUS_RESULT[ch]); -} - -/** - * @brief Clear the status flags. - * - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] mask A mask that means the specified flags to be cleared. Please refer to @ref adc12_irq_event_t. - * - * @note Only the specified flags can be cleared by writing the INT_STS register. - */ -static inline void adc12_clear_status_flags(ADC12_Type *ptr, uint32_t mask) -{ - ptr->INT_STS = mask; -} - -/** @} */ - -/** - * @name Interrupts - * @{ - */ - -/** - * @brief Enable interrupts. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] mask A mask indicating the specified ADC interrupt events. Please refer to @ref adc12_irq_event_t. - */ -static inline void adc12_enable_interrupts(ADC12_Type *ptr, uint32_t mask) -{ - ptr->INT_EN |= mask; -} - -/** - * @brief Disable interrupts. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] mask A mask indicating the specified interrupt events. Please refer to @ref adc12_irq_event_t. - */ -static inline void adc12_disable_interrupts(ADC12_Type *ptr, uint32_t mask) -{ - ptr->INT_EN &= ~mask; -} - -/** @} */ - -/** - * @name Trigger and Conversion - * @{ - */ - -/** - * @brief Trigger ADC conversions by software in sequence mode - * - * @param[in] ptr An ADC12 peripheral base address. - * @return An implementation result of getting an ADC12 software trigger. - * @retval status_success ADC12 software triggers successfully. Please refer to @ref hpm_stat_t. - * @retval status_fail ADC12 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_trigger_seq_by_sw(ADC12_Type *ptr); - -/** - * @brief Trigger ADC conversions by software in preemption mode - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] trig_ch A trigger channel number(e.g. TRIG0A,TRIG0B,TRIG0C...). - * @return An implementation result of getting an ADC12 software trigger. - * @retval status_success ADC12 software triggers successfully. Please refer to @ref hpm_stat_t. - * @retval status_fail ADC12 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch); - -/** - * @brief Get the result in oneshot mode. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] ch An ADC12 peripheral channel. - * @param[out] result A pointer to an ADC12 conversion result. - * @return An implementation result of getting an ADC12 conversion result in oneshot mode. - * @retval status_success Get the result of an ADC12 conversion in oneshot mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC12 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result); - -/** - * @brief Get the result in the period mode. - * - * @param[in] ptr An ADC12 peripheral base address. - * @param[in] ch An ADC12 peripheral channel. - * @param[out] result A pointer to a specified ADC12 conversion result - * @return An implementation of getting an ADC12 conversion result in the period mode. - * @retval status_success Get the result of an ADC12 conversion in the period mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC12 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* HPM_ADC12_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h deleted file mode 100644 index 0901fab3041..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h +++ /dev/null @@ -1,643 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ADC16_DRV_H -#define HPM_ADC16_DRV_H - -#include "hpm_common.h" -#include "hpm_adc16_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief ADC16 driver APIs - * @defgroup adc16_interface ADC16 driver APIs - * @ingroup adc_interfaces - * @{ - */ - -/** @brief Define ADC16 validity check for the channel number */ -#if defined (ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN -#define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM && CH != ADC16_SOC_TEMP_CH_NUM) -#else -#define ADC16_IS_CHANNEL_INVALID(CH) (CH > ADC16_SOC_MAX_CH_NUM) -#endif - -/** @brief Define ADC16 validity check for the channel sample cycle */ -#define ADC16_IS_CHANNEL_SAMPLE_CYCLE_INVALID(CYC) (CYC == 0) - -/** @brief Define ADC16 validity check for the trigger number */ -#define ADC16_IS_TRIG_CH_INVLAID(CH) (CH > ADC_SOC_MAX_TRIG_CH_NUM) - -/** @brief Define ADC16 validity check for the trigger length */ -#define ADC16_IS_TRIG_LEN_INVLAID(TRIG_LEN) (TRIG_LEN > ADC_SOC_MAX_TRIG_CH_LEN) - -/** @brief Define ADC16 validity check for the sequence length */ -#define ADC16_IS_SEQ_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_LEN)) - -/** @brief Define ADC16 validity check for the DMA buffer length in the sequence mode */ -#define ADC16_IS_SEQ_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES)) - -/** @brief Define ADC16 validity check for the DMA buffer length in the preemption mode */ -#define ADC16_IS_PMT_DMA_BUFF_LEN_INVLAID(LEN) ((LEN == 0) || (LEN > ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES)) - -/** @brief Define ADC16 resolutions. */ -typedef enum { - adc16_res_8_bits = 9, - adc16_res_10_bits = 11, - adc16_res_12_bits = 14, - adc16_res_16_bits = 21 -} adc16_resolution_t; - -/** @brief Define ADC16 conversion modes. */ -typedef enum { - adc16_conv_mode_oneshot = 0, - adc16_conv_mode_period, - adc16_conv_mode_sequence, - adc16_conv_mode_preemption -} adc16_conversion_mode_t; - -/** @brief Define ADC16 Clock Divider */ -typedef enum { - adc16_clock_divider_1 = 1, - adc16_clock_divider_2, - adc16_clock_divider_3, - adc16_clock_divider_4, - adc16_clock_divider_5, - adc16_clock_divider_6, - adc16_clock_divider_7, - adc16_clock_divider_8, - adc16_clock_divider_9, - adc16_clock_divider_10, - adc16_clock_divider_11, - adc16_clock_divider_12, - adc16_clock_divider_13, - adc16_clock_divider_14, - adc16_clock_divider_15, - adc16_clock_divider_16, -} adc16_clock_divider_t; - -/** @brief Define ADC16 irq events. */ -typedef enum { - /** This mask indicates that a trigger conversion is complete. */ - adc16_event_trig_complete = ADC16_INT_STS_TRIG_CMPT_MASK, - - /** This mask indicates that a conflict caused by software-triggered conversions. */ - adc16_event_trig_sw_conflict = ADC16_INT_STS_TRIG_SW_CFLCT_MASK, - - /** This mask indicates that a conflict caused by hardware-triggered conversions. */ - adc16_event_trig_hw_conflict = ADC16_INT_STS_TRIG_HW_CFLCT_MASK, - - /** This mask indicates that a conflict caused when bus reading from different channels. */ - adc16_event_read_conflict = ADC16_INT_STS_READ_CFLCT_MASK, - - /** This mask indicates that a conflict caused by sequence-triggered conversions. */ - adc16_event_seq_sw_conflict = ADC16_INT_STS_SEQ_SW_CFLCT_MASK, - - /** This mask indicates that a conflict caused by hardware-triggered conversions. */ - adc16_event_seq_hw_conflict = ADC16_INT_STS_SEQ_HW_CFLCT_MASK, - - /** This mask indicates that DMA is stopped currently. */ - adc16_event_seq_dma_abort = ADC16_INT_STS_SEQ_DMAABT_MASK, - - /** This mask indicates that all of the configured conversion(s) in a queue is(are) complete. */ - adc16_event_seq_full_complete = ADC16_INT_STS_SEQ_CMPT_MASK, - - /** This mask indicates that one of the configured conversion(s) in a queue is complete. */ - adc16_event_seq_single_complete = ADC16_INT_STS_SEQ_CVC_MASK, - - /** This mask indicates that DMA FIFO is full currently. */ - adc16_event_dma_fifo_full = ADC16_INT_STS_DMA_FIFO_FULL_MASK -} adc16_irq_event_t; - -/** @brief ADC16 common configuration struct. */ -typedef struct { - uint8_t res; - uint8_t conv_mode; - uint32_t adc_clk_div; - bool port3_realtime; - bool wait_dis; - bool sel_sync_ahb; - bool adc_ahb_en; -} adc16_config_t; - -/** @brief ADC16 channel configuration struct. */ -typedef struct { - uint8_t ch; - uint16_t thshdh; - uint16_t thshdl; - bool wdog_int_en; - uint8_t sample_cycle_shift; - uint32_t sample_cycle; -} adc16_channel_config_t; - -/** @brief ADC16 channel configuration struct. */ -typedef struct { - uint8_t ch; - uint16_t thshdh; - uint16_t thshdl; -} adc16_channel_threshold_t; - -/** @brief ADC16 DMA configuration struct. */ -typedef struct { - uint32_t *start_addr; - uint32_t buff_len_in_4bytes; - uint32_t stop_pos; - bool stop_en; -} adc16_dma_config_t; - -/** @brief ADC16 DMA configuration struct for the sequence mode. */ -#if defined(ADC_SOC_IP_VERSION) && (ADC_SOC_IP_VERSION < 2) -typedef struct { - uint32_t result :16; - uint32_t seq_num :4; - uint32_t :4; - uint32_t adc_ch :5; - uint32_t :2; - uint32_t cycle_bit :1; -} adc16_seq_dma_data_t; -#else -typedef struct { - uint32_t result :16; - uint32_t seq_num :4; - uint32_t adc_ch :5; - uint32_t :6; - uint32_t cycle_bit :1; -} adc16_seq_dma_data_t; -#endif - -/** @brief ADC16 DMA configuration struct for the preemption mode. */ -#if defined(ADC_SOC_IP_VERSION) && (ADC_SOC_IP_VERSION < 2) -typedef struct { - uint32_t result :16; - uint32_t seq_num :2; - uint32_t :2; - uint32_t trig_ch :4; - uint32_t adc_ch :5; - uint32_t :2; - uint32_t cycle_bit :1; -} adc16_pmt_dma_data_t; -#else -typedef struct { - uint32_t result :16; - uint32_t :4; - uint32_t adc_ch :5; - uint32_t trig_ch :4; - uint32_t seq_num :2; - uint32_t cycle_bit :1; -} adc16_pmt_dma_data_t; -#endif - -/** @brief ADC16 configuration struct for the period mode. */ -typedef struct { - uint8_t ch; - uint8_t prescale; - uint8_t period_count; -} adc16_prd_config_t; - -/** @brief ADC16 queue configuration struct for the sequence mode. */ -typedef struct { - bool seq_int_en; - uint8_t ch; -} adc16_seq_queue_config_t; - -/** @brief ADC16 configuration struct for the sequence mode. */ -typedef struct { - adc16_seq_queue_config_t queue[ADC_SOC_SEQ_MAX_LEN]; - bool restart_en; - bool cont_en; - bool sw_trig_en; - bool hw_trig_en; - uint8_t seq_len; -} adc16_seq_config_t; - -/** @brief ADC16 trigger configuration struct for the preemption mode. */ -typedef struct { - bool inten[ADC_SOC_MAX_TRIG_CH_LEN]; - uint8_t adc_ch[ADC_SOC_MAX_TRIG_CH_LEN]; - uint8_t trig_ch; - uint8_t trig_len; -} adc16_pmt_config_t; - -#ifdef __cplusplus -extern "C" { -#endif -/** - * @name Initialization and Deinitialization - * @{ - */ - -/** - * @brief Get a default configuration for an ADC16 instance. - * - * @param[out] config A pointer to the configuration struct of @ref adc16_config_t. - * - */ -void adc16_get_default_config(adc16_config_t *config); - -/** - * @brief Get a default configuration for an ADC16 Channel. - * - * @param[out] config A pointer to the configuration struct of @ref adc16_channel_config_t. - */ -void adc16_get_channel_default_config(adc16_channel_config_t *config); - -/** - * @brief De-initialize an ADC16 instance. - * - * @param[in] ptr An ADC16 peripheral base address. - * @return A result of de-initializing an ADC16 instance. - * @retval status_success De-initialize an ADC16 instance successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument De-initialize an ADC16 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_deinit(ADC16_Type *ptr); - -/** - * @brief Initialize an ADC16 instance. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] config A pointer to the configuration struct of @ref adc16_config_t. - * @return A result of initializing an ADC16 instance. - * @retval status_success Initialize an ADC16 instance successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC16 instance unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config); - -/** - * @brief Initialize an ADC16 channel - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] config A pointer to the configuration struct of @ref adc16_channel_config_t. - * @return A result of initializing an ADC16 channel. - * @retval status_success Initialize an ADC16 channel successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config); - -/** - * @brief Get thresholds of an ADC16 channel - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] ch An ADC16 channel number - * @param[out] config A pointer to the structure of channel threshold - * @return A result of getting thresholds of an ADC16 channel . - * @retval status_success Initialize an ADC16 channel successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Initialize an ADC16 channel unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_get_channel_threshold(ADC16_Type *ptr, uint8_t ch, adc16_channel_threshold_t *config); - -#if defined (ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT -/** - * @brief Enable oneshot mode (bus mode) - * - * @param[in] ptr An ADC16 peripheral base address. - */ -void adc16_enable_oneshot_mode(ADC16_Type *ptr); - -/** - * @brief Disable oneshot mode (bus mode) - * - * @param[in] ptr An ADC16 peripheral base address. - */ -void adc16_disable_oneshot_mode(ADC16_Type *ptr); -#endif - -/** - * @brief Configure the the period mode for an ADC16 instance. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] config A pointer to the configuration struct of @ref adc16_prd_config_t. - * @return A result of configuring the the period mode for an ADC16 instance. - * @retval status_success Configure the the period mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the the period mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config); - -/** - * @brief Configure the sequence mode for an ADC16 instance. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] config A pointer to configuration struct of @ref adc16_seq_config_t. - * @return A result of configuring the sequence mode for an ADC16 instance. - * @retval status_success Configure the sequence mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the sequence mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config); - -/** - * @brief Configure the preemption mode for an ADC16 instance. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] config A pointer to configuration struct of @ref adc16_pmt_config_t. - * @return A result of configuring the preemption mode for an ADC16 instance. - * @retval status_success Configure the preemption mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Configure the preemption mode unsuccessfully due to passing one or more invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config); - -/** - * @brief Set the queue enable control. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] trig_ch An ADC16 peripheral trigger channel. - * @param[in] enable Set true to enable and false to disable. - * @return A result of setting queue enable in preemption. - * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. - * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. - */ -hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable); - -/** @} */ - -/** - * @name Enablement Control - * @{ - */ -/** - * @brief Enable the hw trigger control for the sequence mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * - */ -static inline void adc16_seq_enable_hw_trigger(ADC16_Type *ptr) -{ - ptr->SEQ_CFG0 |= ADC16_SEQ_CFG0_HW_TRIG_EN_MASK; -} -/** - * @brief Disable the hw trigger control for the sequence mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * - */ -static inline void adc16_seq_disable_hw_trigger(ADC16_Type *ptr) -{ - ptr->SEQ_CFG0 &= ~ADC16_SEQ_CFG0_HW_TRIG_EN_MASK; -} -/** @} */ - -/** - * @name DMA Control - * @{ - */ - -/** - * @brief Configure the stop position offset in the specified memory of DMA write operation for the sequence mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] stop_pos A stop position offset. - */ -static inline void adc16_set_seq_stop_pos(ADC16_Type *ptr, uint16_t stop_pos) -{ - ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_STOP_POS_MASK) - | ADC16_SEQ_DMA_CFG_STOP_POS_SET(stop_pos); -} - -/** - * @brief Configure the start address of DMA write operation for the preemption mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] addr A start address of DMA write operation. - */ -static inline void adc16_init_pmt_dma(ADC16_Type *ptr, uint32_t addr) -{ - ptr->TRG_DMA_ADDR = addr & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK; -} - -/** - * @brief Configure the start address of DMA write operation for the sequence mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] config A pointer to configuration struct of @ref adc16_dma_config_t. - * @return An implementation result of DMA initializing for the sequence mode - * @retval status_success ADC16 initialize in sequence mode successfully. Please refert to @ref hpm_stat_t. - * @retval status_invalid_argument ADC16 initialize in sequence mode unsuccessfully due to passing invalid arguments. Please refert to @ref hpm_stat_t. - */ -hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *config); - -/** @} */ - -/** - * @name Status - * @{ - */ - -/** - * @brief Get all ADC16 status flags. - * - * @param[in] ptr An ADC16 peripheral base address. - * @return A mask indicating all corresponding interrupt statuses. - * @retval A mask. Please refer to @ref adc16_irq_event_t. - */ -static inline uint32_t adc16_get_status_flags(ADC16_Type *ptr) -{ - return ptr->INT_STS; -} - -/** - * @brief Set value of the WAIT_DIS bit. The ADC does not block access to the associated peripheral bus - * until the ADC has completed its conversion. - * - * @param[in] ptr An ADC16 peripheral base address. - * @deprecated This API will be removed from V2.0.x - */ -static inline void adc16_disable_busywait(ADC16_Type *ptr) -{ - ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_SET(1); -} - -/** - * @brief Set value of the WAIT_DIS bit. ADC blocks access to the associated peripheral bus - * until the ADC completes the conversion. - * - * @param[in] ptr An ADC16 peripheral base address. - * @deprecated This API will be removed from V2.0.x - */ -static inline void adc16_enable_busywait(ADC16_Type *ptr) -{ - ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; -} - -/** - * @brief Set nonblocking read in oneshot mode. - * @note An ADC does not block access to the associated peripheral whether it completes a conversion or not. - * - * @param[in] ptr An ADC16 peripheral base address. - */ -static inline void adc16_set_nonblocking_read(ADC16_Type *ptr) -{ - ptr->BUF_CFG0 |= ADC16_BUF_CFG0_WAIT_DIS_MASK; -} - -/** - * @brief Set blocking read in oneshot mode. - * @note An ADC blocks access to the associated peripheral bus until it completes a conversion. - * - * @param[in] ptr An ADC16 peripheral base address. - */ -static inline void adc16_set_blocking_read(ADC16_Type *ptr) -{ - ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_WAIT_DIS_MASK; -} - -/** - * @brief Judge whether the current setting is none-blocking mode or not. - * - * @param[in] ptr An ADC16 peripheral base address. - * @return A result indicating the status of bus waiting. - * @retval True means that nonblocking reading. - * @retval False means that blocking reading. - * - */ -static inline bool adc16_is_nonblocking_mode(ADC16_Type *ptr) -{ - return (ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0) ? true : false); -} - -/** - * @brief Get the status of a conversion validity. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] ch An ADC16 peripheral channel. - * @return Status indicating the validity of the current conversion result. - * - * @note This function is only used when the WAIT_DIS bit in the BUF_RESULT register is 1. - */ -static inline bool adc16_get_conv_valid_status(ADC16_Type *ptr, uint8_t ch) -{ - return ADC16_BUS_RESULT_VALID_GET(ptr->BUS_RESULT[ch]); -} - -/** - * @brief Clear the status flags. - * - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] mask A mask that means the specified flags to be cleared. Please refer to @ref adc16_irq_event_t. - * - * @note Only the specified flags can be cleared by writing the INT_STS register. - */ -static inline void adc16_clear_status_flags(ADC16_Type *ptr, uint32_t mask) -{ - ptr->INT_STS = mask; -} - -/** @} */ - -/** - * @name Interrupts - * @{ - */ - -/** - * @brief Enable interrupts. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] mask A mask indicating the specified ADC interrupt events. Please refer to @ref adc16_irq_event_t. - */ -static inline void adc16_enable_interrupts(ADC16_Type *ptr, uint32_t mask) -{ - ptr->INT_EN |= mask; -} - -/** - * @brief Disable interrupts. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] mask A mask indicating the specified interrupt events. Please refer to @ref adc16_irq_event_t. - */ -static inline void adc16_disable_interrupts(ADC16_Type *ptr, uint32_t mask) -{ - ptr->INT_EN &= ~mask; -} - -/** @} */ - -/** - * @name Trigger and Conversion - * @{ - */ - -/** - * @brief Trigger ADC conversions by software in sequence mode - * - * @param[in] ptr An ADC16 peripheral base address. - * @return An implementation result of getting an ADC16 software trigger. - * @retval status_success ADC16 software triggers successfully. Please refer to @ref hpm_stat_t. - * @retval status_fail ADC16 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_trigger_seq_by_sw(ADC16_Type *ptr); - -/** - * @brief Trigger ADC conversions by software in preemption mode - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] trig_ch A trigger channel number(e.g. TRIG0A,TRIG0B,TRIG0C...). - * @return An implementation result of getting an ADC16 software trigger. - * @retval status_success ADC16 software triggers successfully. Please refer to @ref hpm_stat_t. - * @retval status_fail ADC16 software triggers unsuccessfully. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_trigger_pmt_by_sw(ADC16_Type *ptr, uint8_t trig_ch); - -/** - * @brief Get the result in oneshot mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] ch An ADC16 peripheral channel. - * @param[out] result A pointer to an ADC16 conversion result. - * @return An implementation result of getting an ADC16 conversion result in oneshot mode. - * @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); - -/** - * @brief Get the result in the period mode. - * - * @param[in] ptr An ADC16 peripheral base address. - * @param[in] ch An ADC16 peripheral channel. - * @param[out] result A pointer to a specified ADC16 conversion result - * @return An implementation of getting an ADC16 conversion result in the period mode. - * @retval status_success Get the result of an ADC16 conversion in the period mode successfully. Please refer to @ref hpm_stat_t. - * @retval status_invalid_argument Get the result of an ADC16 conversion in the period mode unsuccessfully due to passing invalid arguments. Please refer to @ref hpm_stat_t. - */ -hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result); - -#if defined(ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN -/** - * @brief Enable the temperature sensor - * - * @param[in] ptr An ADC16 peripheral base address. - */ -void adc16_enable_temp_sensor(ADC16_Type *ptr); - -/** - * @brief Disable the temperature sensor - * - * @param[in] ptr An ADC16 peripheral base address. - */ -void adc16_disable_temp_sensor(ADC16_Type *ptr); -#endif - -/** - * @brief enable the transmission of adc data to the motor sensor unit. - * - * @param[in] ptr An ADC16 peripheral base address. - */ -#if defined(HPM_IP_FEATURE_ADC16_HAS_MOT_EN) && HPM_IP_FEATURE_ADC16_HAS_MOT_EN -static inline void adc16_enable_motor(ADC16_Type *ptr) -{ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_MOTO_EN_MASK; -} -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* HPM_ADC16_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h deleted file mode 100644 index b95da752a18..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bacc_drv.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BACC_DRV_H -#define HPM_BACC_DRV_H - -#include "hpm_common.h" -#include "hpm_bacc_regs.h" - -/** - * - * @brief BACC driver APIs - * @defgroup bacc_interface BACC driver APIs - * @ingroup io_interfaces - * @{ - */ - -/* @brief Timing gap ratios */ -typedef enum { - bacc_ratio_0 = 0, - bacc_ratio_1_32768 = 1, - bacc_ratio_1_16384 = 2, - bacc_ratio_1_8192 = 3, - bacc_ratio_1_4096 = 4, - bacc_ratio_1_2048 = 5, - bacc_ratio_1_1024 = 6, - bacc_ratio_1_512 = 7, - bacc_ratio_1_256 = 8, - bacc_ratio_1_128 = 9, - bacc_ratio_1_64 = 10, - bacc_ratio_1_32 = 11, - bacc_ratio_1_16 = 12, - bacc_ratio_1_8 = 13, - bacc_ratio_1_4 = 14, - bacc_ratio_1_2 = 15, -} bacc_ratio_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * brief set timing gap after rising edge - * - * @param[in] ptr BACC base address - * @param[in] ratio Ratio of guard band after rising edge - * @param[in] offset Guard band after rising edge (16 bits) - */ -static inline void bacc_timing_gap_post(BACC_Type *ptr, bacc_ratio_t ratio, uint16_t offset) -{ - ptr->PRE_TIME = BACC_PRE_TIME_POST_RATIO_SET(ratio) - | BACC_PRE_TIME_POST_OFFSET_SET(offset); -} - -/* - * brief set timing gap before rising edge - * - * @param[in] ptr BACC base address - * @param[in] ratio Ratio of guard band before rising edge - * @param[in] offset Guard band before rising edge (16 bits) - */ -static inline void bacc_timing_gap_pre(BACC_Type *ptr, bacc_ratio_t ratio, uint16_t offset) -{ - ptr->PRE_TIME = BACC_PRE_TIME_PRE_RATIO_SET(ratio) - | BACC_PRE_TIME_PRE_OFFSET_SET(offset); -} - -/* - * brief disable fast read - * - * @param[in] ptr BACC base address - */ -static inline void bacc_disable_fast_read(BACC_Type *ptr) -{ - ptr->CONFIG &= ~BACC_CONFIG_FAST_READ_MASK; -} - -/* - * brief enable fast read - * - * @param[in] ptr BACC base address - */ -static inline void bacc_enable_fast_read(BACC_Type *ptr) -{ - ptr->CONFIG |= BACC_CONFIG_FAST_READ_MASK; -} - -/* - * brief disable fast wirte - * - * @param[in] ptr BACC base address - */ -static inline void bacc_disable_fast_write(BACC_Type *ptr) -{ - ptr->CONFIG &= ~BACC_CONFIG_FAST_WRITE_MASK; -} - -/* - * brief enable fast wirte - * - * @param[in] ptr BACC base address - */ -static inline void bacc_enable_fast_write(BACC_Type *ptr) -{ - ptr->CONFIG |= BACC_CONFIG_FAST_WRITE_MASK; -} - -/* - * brief set timing of access - * - * @param[in] ptr BACC base address - * @param[in] timing Time in APB clock cycles (16 bits) - */ -static inline void bacc_set_timing(BACC_Type *ptr, uint16_t timing) -{ - ptr->CONFIG = (ptr->CONFIG & ~(BACC_CONFIG_TIMING_MASK)) - | BACC_CONFIG_TIMING_SET(timing); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_BACC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h deleted file mode 100644 index 83d9b67a280..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bgpr_drv.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BGPR_DRV_H -#define HPM_BGPR_DRV_H - -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_bgpr_regs.h" - -/** - * - * @brief BGPR driver APIs - * @defgroup bgpr_interfaces BGPR driver APIs - * @ingroup io_interfaces - * @{ - */ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief read BGPR value - * - * @note the bgpr_index range is 0 ~ (GPR count of BGPR - 1) - * - * @param ptr BGPR base address - * @param bgpr_index BGPR GPR index - * @param bgpr_val the BGPR GPR value pointer - * - * @return hpm_stat_t status_success if read bgpr without any error - */ -static inline hpm_stat_t bgpr_read32(BGPR_Type *ptr, uint8_t bgpr_index, uint32_t *bgpr_val) -{ - hpm_stat_t stat = status_invalid_argument; - uint8_t gpr_count = sizeof(ptr->GPR) / sizeof(uint32_t); - if (bgpr_index < gpr_count) { - (*bgpr_val) = ptr->GPR[bgpr_index]; - stat = status_success; - } - return stat; -} - -/** - * @brief write BGPR value - * - * @note the bgpr_index range is 0 ~ (GPR count of BGPR - 1) - * - * @param ptr BGPR base address - * @param bgpr_index BGPR GPR index - * @param bgpr_val the BGPR GPR value - * - * @return hpm_stat_t status_success if write bgpr without any error - */ -static inline hpm_stat_t bgpr_write32(BGPR_Type *ptr, uint8_t bgpr_index, uint32_t bgpr_val) -{ - hpm_stat_t stat = status_invalid_argument; - uint8_t gpr_count = sizeof(ptr->GPR) / sizeof(uint32_t); - if (bgpr_index < gpr_count) { - ptr->GPR[bgpr_index] = bgpr_val; - stat = status_success; - } - return stat; -} - -/** - * @} - */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h deleted file mode 100644 index 2319a996935..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_bkey_drv.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BKEY_DRV_H -#define HPM_BKEY_DRV_H - -#include "hpm_common.h" -#include "hpm_bkey_regs.h" - -/** - * - * @brief BKEY driver APIs - * @defgroup bkey_interface BKEY driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Lock type - */ -typedef enum bkey_lock_type { - bkey_lock_write = BKEY_ECC_WLOCK_MASK, - bkey_lock_read = BKEY_ECC_RLOCK_MASK, - bkey_lock_both = BKEY_ECC_RLOCK_MASK | BKEY_ECC_WLOCK_MASK, -} bkey_lock_type_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief bkey set key content - * - * Program key content - * - * @param[in] ptr BKEY base address - * @param[in] key Key index - * @param[in] start Key content data start index - * @param[in] data pointer of actual data to be programmed - * @param[in] size data total size in 32-bit - */ -static inline void bkey_set_key_data(BKEY_Type *ptr, uint8_t key, uint8_t start, uint32_t *data, uint8_t size) -{ - for (uint8_t i = 0; i < size; i++) { - ptr->KEY[key].DATA[start + i] = *(data + i); - } -} - -/** - * @brief bkey fetch key content - * - * Fetch key content - * - * @param[in] ptr BKEY base address - * @param[in] key key index - * @param[in] start key content data start index - * @param[in] data pointer of buffer to received key content - * @param[in] size data total size in 32-bit - */ -static inline void bkey_get_key_data(BKEY_Type *ptr, uint8_t key, uint8_t start, uint32_t *data, uint8_t size) -{ - for (uint8_t i = 0; i < size; i++) { - *(data + i) = ptr->KEY[key].DATA[start + i]; - } -} - -/** - * @brief bkey lock key - * - * Feed correct ecc data of current key content and lock it - * - * @param[in] ptr BKEY base address - * @param[in] key key index - * @param[in] lock lock type - * @param[in] ecc ecc value of current key content - */ -static inline void bkey_lock(BKEY_Type *ptr, uint8_t key, bkey_lock_type_t lock, uint16_t ecc) -{ - ptr->ECC[key] = BKEY_ECC_ECC_SET(ecc) | lock; -} - -/** - * @brief bkey select key - * - * Select which key to use - * - * @param[in] ptr BKEY base address - * @param[in] key key index - * @arg 0 select key0 in secure mode, key1 in non-secure mode - * @arg 1 select key1 in secure or non-secure mode - */ -static inline void bkey_select_key(BKEY_Type *ptr, uint8_t key) -{ - ptr->SELECT = BKEY_SELECT_SELECT_SET(key); -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BKEY_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h deleted file mode 100644 index 490384fba66..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_butn_drv.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BUTN_DRV_H -#define HPM_BUTN_DRV_H - -#include "hpm_common.h" -#include "hpm_butn_regs.h" - -/** - * - * @brief BUTN driver APIs - * @defgroup butn_interface BUTN driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -#define BUTN_EVENT_POWER_PRESSED (BUTN_BTN_STATUS_PBTN_SET(1)) -#define BUTN_EVENT_POWER_PRESSED_HOLD_0_5_S (BUTN_BTN_STATUS_PBTN_SET(2)) -#define BUTN_EVENT_POWER_PRESSED_HOLD_8_S (BUTN_BTN_STATUS_PBTN_SET(4)) -#define BUTN_EVENT_POWER_PRESSED_HOLD_16_S (BUTN_BTN_STATUS_PBTN_SET(8)) - -#define BUTN_EVENT_WAKE_PRESSED (BUTN_BTN_STATUS_WBTN_SET(1)) -#define BUTN_EVENT_WAKE_PRESSED_HOLD_0_5_S (BUTN_BTN_STATUS_WBTN_SET(2)) -#define BUTN_EVENT_WAKE_PRESSED_HOLD_8_S (BUTN_BTN_STATUS_WBTN_SET(4)) -#define BUTN_EVENT_WAKE_PRESSED_HOLD_16_S (BUTN_BTN_STATUS_WBTN_SET(8)) - -#define BUTN_EVENT_WAKE_POWER_PRESSED (BUTN_BTN_STATUS_DBTN_SET(1)) -#define BUTN_EVENT_WAKE_POWER_PRESSED_HOLD_0_5_S (BUTN_BTN_STATUS_DBTN_SET(2)) -#define BUTN_EVENT_WAKE_POWER_PRESSED_HOLD_8_S (BUTN_BTN_STATUS_DBTN_SET(4)) -#define BUTN_EVENT_WAKE_POWER_PRESSED_HOLD_16_S (BUTN_BTN_STATUS_DBTN_SET(8)) - -#define BUTN_EVENT_POWER_CLICKED (BUTN_BTN_STATUS_PCLICK_SET(1)) -#define BUTN_EVENT_POWER_CLICKED_X2 (BUTN_BTN_STATUS_PCLICK_SET(2)) -#define BUTN_EVENT_POWER_CLICKED_X3 (BUTN_BTN_STATUS_PCLICK_SET(4)) - -#define BUTN_EVENT_POWER_CLICKED_WAKE_HELD (BUTN_BTN_STATUS_XPCLICK_SET(1)) -#define BUTN_EVENT_POWER_CLICKED_X2_WAKE_HELD (BUTN_BTN_STATUS_XPCLICK_SET(2)) -#define BUTN_EVENT_POWER_CLICKED_X3_WAKE_HELD (BUTN_BTN_STATUS_XPCLICK_SET(4)) - -#define BUTN_EVENT_WAKE_CLICKED (BUTN_BTN_STATUS_WCLICK_SET(1)) -#define BUTN_EVENT_WAKE_CLICKED_X2 (BUTN_BTN_STATUS_WCLICK_SET(2)) -#define BUTN_EVENT_WAKE_CLICKED_X3 (BUTN_BTN_STATUS_WCLICK_SET(4)) - -#define BUTN_EVENT_WAKE_CLICKED_POWER_HELD (BUTN_BTN_STATUS_XWCLICK_SET(1)) -#define BUTN_EVENT_WAKE_CLICKED_X2_POWER_HELD (BUTN_BTN_STATUS_XWCLICK_SET(2)) -#define BUTN_EVENT_WAKE_CLICKED_X3_POWER_HELD (BUTN_BTN_STATUS_XWCLICK_SET(4)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get status - * - * @param[in] ptr BUTN base address - * @retval status mask in 32 bits, please refer to BUTN_EVENT_* macros - */ -static inline uint32_t butn_get_status(BUTN_Type *ptr) -{ - return ptr->BTN_STATUS; -} - -/** - * @brief Enable interrupt with mask - * - * @param[in] ptr BUTN base address - * @param[in] mask Mask of interrupts to be enabled, please refer to BUTN_EVENT_* macros - */ -static inline void butn_enable_irq(BUTN_Type *ptr, uint32_t mask) -{ - ptr->BTN_IRQ_MASK |= mask; -} - -/** - * @brief Disable interrupt with mask - * - * @param[in] ptr BUTN base address - * @param[in] mask Mask of interrupts to be disabled, please refer to BUTN_EVENT_* macros - */ -static inline void butn_disable_irq(BUTN_Type *ptr, uint32_t mask) -{ - ptr->BTN_IRQ_MASK &= ~mask; -} - -/** - * @brief Set intense of PLED and RLED/WLED - * - * @param[in] ptr BUTN base address - * @param[in] intense Intense value (0~15) - */ -static inline void butn_set_intense(BUTN_Type *ptr, uint8_t intense) -{ - ptr->LED_INTENSE = BUTN_LED_INTENSE_PLED_SET(intense) - | BUTN_LED_INTENSE_RLED_SET(intense); -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BUTN_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h deleted file mode 100644 index 4f1b4ca3878..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_CAM_DRV_H -#define HPM_CAM_DRV_H - -#include "hpm_common.h" -#include "hpm_display_common.h" -#include "hpm_cam_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief CAM driver APIs - * @defgroup cam_interface CAM driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief CAM data store mode - */ -#define CAM_DATA_STORE_MODE_NORMAL (0U) -#define CAM_DATA_STORE_MODE_Y_UV_PLANES (CAM_CR1_STORAGE_MODE_SET(1)) -#define CAM_DATA_STORE_MODE_Y_ONLY (CAM_CR1_STORAGE_MODE_SET(2)) -#define CAM_DATA_STORE_MODE_BINARY (CAM_CR1_STORAGE_MODE_SET(3)) - -/** - * @brief CAM sensor bitwidth - */ -#define CAM_SENSOR_BITWIDTH_8BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(0)) -#define CAM_SENSOR_BITWIDTH_10BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(1)) -#define CAM_SENSOR_BITWIDTH_24BITS (CAM_CR1_SENSOR_BIT_WIDTH_SET(3)) - -/** - * @brief CAM IRQ mask - */ -typedef enum { - cam_irq_unsupported_configuration = CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK, - cam_irq_hist_calculation_done = CAM_INT_EN_HIST_DONE_INT_EN_MASK, - cam_irq_hresponse_error = CAM_INT_EN_HRESP_ERR_EN_MASK, - cam_irq_end_of_frame = CAM_INT_EN_EOF_INT_EN_MASK, - cam_irq_rx_fifo_overrun = CAM_INT_EN_RF_OR_INTEN_MASK, - cam_irq_fb2_dma_transfer_done = CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK, - cam_irq_fb1_dma_transfer_done = CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK, - cam_irq_start_of_frame = CAM_INT_EN_SOF_INT_EN_MASK -} cam_irq_mask_t; - -/** - * @brief CAM status mask - */ -typedef enum { - cam_status_unsupported_configuration = CAM_STA_ERR_CL_BWID_CFG_MASK, - cam_status_hist_calculation_done = CAM_STA_HIST_DONE_MASK, - cam_status_rx_fifo_overrun = CAM_STA_RF_OR_INT_MASK, - cam_status_fb2_dma_transfer_done = CAM_STA_DMA_TSF_DONE_FB2_MASK, - cam_status_fb1_dma_transfer_done = CAM_STA_DMA_TSF_DONE_FB1_MASK, - cam_status_end_of_frame = CAM_STA_EOF_INT_MASK, - cam_status_start_of_frame = CAM_STA_SOF_INT_MASK, - cam_status_hresponse_error = CAM_STA_HRESP_ERR_INT_MASK -} cam_status_mask_t; - -/** - * @brief CAM input color format - */ -#define CAM_COLOR_FORMAT_RGB888 (CAM_CR1_COLOR_FORMATS_SET(2)) -#define CAM_COLOR_FORMAT_RGB565 (CAM_CR1_COLOR_FORMATS_SET(4)) -#define CAM_COLOR_FORMAT_RGB555 (CAM_CR1_COLOR_FORMATS_SET(6)) -#define CAM_COLOR_FORMAT_YCBCR422 (CAM_CR1_COLOR_FORMATS_SET(7)) -#define CAM_COLOR_FORMAT_YUV444 (CAM_CR1_COLOR_FORMATS_SET(8)) -#define CAM_COLOR_FORMAT_RAW8 (CAM_CR1_COLOR_FORMATS_SET(0xf)) -#define CAM_COLOR_FORMAT_UNSUPPORTED (1) - -/** - * @brief CAM config - */ -typedef struct { - uint32_t width; - uint32_t height; - bool pixclk_sampling_falling; -#if defined(HPM_IP_FEATURE_CAM_INV_DEN) && (HPM_IP_FEATURE_CAM_INV_DEN == 1) - bool de_active_low; /* de_active_low must is same with hsync_active_low when dvp be used */ -#endif - bool hsync_active_low; - bool vsync_active_low; - bool color_ext; - bool data_pack_msb; - uint16_t data_store_mode; - uint8_t color_format; - uint8_t sensor_bitwidth; - uint32_t buffer1; - uint32_t buffer2; - display_yuv2rgb_config_t csc_config; -} cam_config_t; - -/** - * @brief cam input pixel byte order - */ -typedef enum { - cam_input_pixel_yuv444 = 0, /* Y[23:16] U[15:8] V[7:0] */ - cam_input_pixel_yvu444 = 1, /* Y[23:16] V[15:8] U[7:0] */ - cam_input_pixel_uyv444 = 2, /* U[23:16] Y[15:8] V[7:0] */ - cam_input_pixel_vyu444 = 3, /* V[23:16] Y[15:8] U[7:0] */ - cam_input_pixel_uvy444 = 4, /* U[23:16] V[15:8] Y[7:0] */ - cam_input_pixel_vuy444 = 5, /* V[23:16] U[15:8] Y[7:0] */ - cam_input_pixel_yuyv422 = 0, /* Y0[31:24] U0[23:16] Y1[15:8] V0[7:0] */ - cam_input_pixel_yvyu422 = 1, /* Y0[31:24] V0[23:16] Y1[15:8] U0[7:0] */ - cam_input_pixel_uyvy422 = 2, /* U0[31:24] Y0[23:16] V0[15:8] Y1[7:0] */ - cam_input_pixel_vyuy422 = 3, /* V0[31:24] Y0[23:16] U0[15:8] Y1[7:0] */ - cam_input_pixel_rgb565 = 0, /* R[15:11] G[10:8] G[7:5] B[4:0] */ - cam_input_pixel_bgr565 = 1, /* B[15:11] G[10:8] G[7:5] R[4:0] */ - cam_input_pixel_gbr888 = 0, /* G[23:16] B[15:8] R[7:0] */ - cam_input_pixel_grb888 = 1, /* G[23:16] R[15:8] B[7:0] */ - cam_input_pixel_bgr888 = 2, /* B[23:16] G[15:8] R[7:0] */ - cam_input_pixel_rgb888 = 3, /* R[23:16] G[15:8] B[7:0] */ - cam_input_pixel_brg888 = 4, /* B[23:16] R[15:8] G[7:0] */ - cam_input_pixel_rbg888 = 5, /* R[23:16] B[15:8] G[7:0] */ -} cam_input_pixel_byte_order_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief cam get pixel format value - * - * @param format display_pixel_format_t - * @return uint32_t cam color format, like CAM_COLOR_FORMAT_RGB565 - */ -static inline uint32_t cam_get_pixel_format(display_pixel_format_t format) -{ - switch (format) { - case display_pixel_format_rgb565: - return CAM_COLOR_FORMAT_RGB565; - case display_pixel_format_ycbcr422: - return CAM_COLOR_FORMAT_YCBCR422; - case display_pixel_format_raw8: - return CAM_COLOR_FORMAT_RAW8; - default: - return CAM_COLOR_FORMAT_UNSUPPORTED; - } -} - -/** - * @brief CAM set high and low limits of color key - * - * @param [in] ptr CAM base address - * @param [in] high color key high limits - * @param [in] low color key low limits - */ -static inline void cam_set_color_key(CAM_Type *ptr, uint32_t high, uint32_t low) -{ - ptr->CLRKEY_LOW = CAM_CLRKEY_LOW_LIMIT_SET(low); - ptr->CLRKEY_HIGH = CAM_CLRKEY_HIGH_LIMIT_SET(high); -} - -/** - * @brief CAM get default config - * - * @param [in] ptr CAM base address - * @param [out] config cam_config_t - * @param [in] pixel_format display_pixel_format_t - */ -void cam_get_default_config(CAM_Type *ptr, cam_config_t *config, display_pixel_format_t pixel_format); - -/** - * @brief CAM init - * - * @param [in] ptr CAM base address - * @param [in] config cam_config_t - * - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config); - -/** - * @brief CAM start - * - * @param [in] ptr CAM base address - */ -void cam_start(CAM_Type *ptr); - -/** - * @brief CAM stop - * - * @note this API will stop CAM immediately no matter there's any frame is being processed or not - * - * @param [in] ptr CAM base address - */ -void cam_stop(CAM_Type *ptr); - -/** - * @brief CAM update DMASA_FB1 buffer - * - * @param [in] ptr CAM base address - * @param [in] buffer buffer point address - */ -static inline void cam_update_buffer(CAM_Type *ptr, uint32_t buffer) -{ - ptr->DMASA_FB1 = buffer; -} - -/** - * @brief CAM update DMASA_FB2 buffer - * - * @param [in] ptr CAM base address - * @param [in] buffer buffer point address - */ -static inline void cam_update_buffer2(CAM_Type *ptr, uint32_t buffer) -{ - ptr->DMASA_FB2 = buffer; -} - -/** - * @brief CAM enable binary output - * - * This function is used to enable CAM binary output after - * the CAM is initialized by the cam_init. - * - * @param [in] ptr CAM base address - */ -static inline void cam_enable_binary_output(CAM_Type *ptr) -{ - ptr->CR20 |= CAM_CR20_BINARY_EN_MASK; -} - -/** - * @brief CAM disable binary output - * - * @param [in] ptr CAM base address - */ -static inline void cam_disable_binary_output(CAM_Type *ptr) -{ - ptr->CR20 &= ~CAM_CR20_BINARY_EN_MASK; -} - -/** - * @brief CAM set binary threshold - * - * @param [in] ptr CAM base address - * @param [in] threshold threshold value of binary output - */ -static inline void cam_set_binary_threshold(CAM_Type *ptr, uint8_t threshold) -{ - ptr->CR20 = (ptr->CR20 & (~CAM_CR20_THRESHOLD_MASK)) | CAM_CR20_THRESHOLD_SET(threshold); -} - -/** - * @brief CAM enable argb8888 output - * - * This function is used to enable CAM argb8888 pixel output after the CAM is initialized by - * the cam_init and input pixel byte order is configured by the cam_set_input_pixel_byte_order. - * - * @param [in] ptr CAM base address - */ -static inline void cam_enable_argb8888_output(CAM_Type *ptr) -{ - ptr->CR1 |= CAM_CR1_COLOR_EXT_MASK; -} - -/** - * @brief CAM disable argb8888 output - * - * @param [in] ptr CAM base address - */ -static inline void cam_disable_argb8888_output(CAM_Type *ptr) -{ - ptr->CR1 &= ~CAM_CR1_COLOR_EXT_MASK; -} - -/** - * @brief CAM set input pixel byte order - * - * @param [in] ptr CAM base address - * @param [in] order cam_input_pixel_byte_order_t - */ -static inline void cam_set_input_pixel_byte_order(CAM_Type *ptr, cam_input_pixel_byte_order_t order) -{ - ptr->CR2 = (ptr->CR2 & (~CAM_CR2_CLRBITFORMAT_MASK)) | CAM_CR2_CLRBITFORMAT_SET(order); -} - -/** - * @brief CAM enable irq - * - * @param [in] ptr CAM base address - * @param [in] irq_mask irq mask value - */ -static inline void cam_enable_irq(CAM_Type *ptr, cam_irq_mask_t irq_mask) -{ - ptr->INT_EN |= irq_mask; -} - - -/** - * @brief CAM disable irq - * - * @param [in] ptr CAM base address - * @param [in] irq_mask irq mask value - */ -static inline void cam_disable_irq(CAM_Type *ptr, cam_irq_mask_t irq_mask) -{ - ptr->INT_EN &= ~irq_mask; -} - -/** - * @brief Check CAM status according to the given status mask - * - * @param [in] ptr CAM base address - * @param sta_mask sta_mask refer to cam_status_mask_t - * @retval true if any bit in given mask is set - * @retval false if none of any bit in given mask is set - */ -static inline bool cam_check_status(CAM_Type *ptr, cam_status_mask_t sta_mask) -{ - return ((ptr->STA & sta_mask) != 0U) ? true : false; -} - -/** - * @brief Clear CAM status according to the given status mask - * - * @param [in] ptr CAM base address - * @param sta_mask sta_mask refer to cam_status_mask_t - */ -static inline void cam_clear_status(CAM_Type *ptr, cam_status_mask_t sta_mask) -{ - ptr->STA = sta_mask; -} - -/** - * @brief CAM safety stop - * - * @note this API will wait for end-of-frame event before stopping CAM - * - * @param [in] ptr CAM base address - */ -void cam_stop_safely(CAM_Type *ptr); - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CAM_DRV_H */ - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h deleted file mode 100644 index 8756eae6cb3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h +++ /dev/null @@ -1,973 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_CAN_DRV_H -#define HPM_CAN_DRV_H - -#include "hpm_common.h" -#include "hpm_can_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief CAN driver APIs - * @defgroup can_interface CAN driver APIs - * @ingroup can_interfaces - * @{ - * - */ - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ - -/** - * @brief CAN error codes - */ -enum { - status_can_bit_error = MAKE_STATUS(status_group_can, 0), /**< CAN bit error */ - status_can_form_error = MAKE_STATUS(status_group_can, 1), /**< CAN Form error */ - status_can_stuff_error = MAKE_STATUS(status_group_can, 2), /**< CAN stuff error */ - status_can_ack_error = MAKE_STATUS(status_group_can, 3), /**< CAN ACK error */ - status_can_crc_error = MAKE_STATUS(status_group_can, 4), /**< CAN CRC error */ - status_can_other_error = MAKE_STATUS(status_group_can, 5), /**< CAN other error */ - status_can_tx_fifo_full = MAKE_STATUS(status_group_can, 6), /**< CAN TX fifo full */ - status_can_filter_index_invalid = MAKE_STATUS(status_group_can, 7), /**< CAN filter index is invalid */ - status_can_filter_num_invalid = MAKE_STATUS(status_group_can, 8), /**< CAN filter number is invalid */ - status_can_invalid_bit_timing = MAKE_STATUS(status_group_can, 9), /**< Invalid CAN bit timing parameter */ -}; - -/** - * @brief CAN Event definitions - */ -#define CAN_EVENT_RECEIVE (CAN_RTIF_RIF_MASK) /**< CAN Receive event */ -#define CAN_EVENT_RX_BUF_OVERRUN (CAN_RTIF_ROIF_MASK) /**< CAN RX buffer overrun event */ -#define CAN_EVENT_RX_BUF_FULL (CAN_RTIF_RFIF_MASK) /**< CAN RX buffer full event */ -#define CAN_EVENT_RX_BUF_ALMOST_FULL (CAN_RTIF_RAFIF_MASK) /**< CAN RX buffer almost full event */ -#define CAN_EVENT_TX_PRIMARY_BUF (CAN_RTIF_TPIF_MASK) /**< CAN TX primary buffer event */ -#define CAN_EVENT_TX_SECONDARY_BUF (CAN_RTIF_TSIF_MASK) /**< CAN TX secondary buffer event */ -#define CAN_EVENT_ERROR (CAN_RTIF_EIF_MASK) /**< CAN error event */ -#define CAN_EVENT_ABORT (CAN_RTIF_AIF_MASK) /**< CAN abort event */ - -/** - * @brief CAN Secondary Transmit buffer Status - */ -#define CAN_STB_IS_EMPTY (0U) /**< CAN Secondary Transmit buffer is empty */ -#define CAN_STB_LESS_EQUAL_HALF_FULL (1U) /**< CAN Secondary Transmit buffer <= 1/2 * FULL */ -#define CAN_STB_MORE_THAN_HALF_FULL (2U) /**< CAN Secondary Transmit buffer > 1/2 * FULL */ -#define CAN_STB_IS_FULL (3U) /**< CAN Secondary Transmit buffer is full */ - -/** - * @brief CAN Receive Buffer States - */ -#define CAN_RXBUF_IS_EMPTY (0U) /**< CAN Receive buffer is empty */ -#define CAN_RXBUF_HAS_DATA (1U) /**< CAN Receive buffer has data */ -#define CAN_RXBUF_ALMOST_FULL (2U) /**< CAN Receive buffer is almost full */ -#define CAN_RXBUF_IS_FULL (3U) /**< CAN Receive buffer is full */ - -/** - * @brief CAN Error interrupts/flags - * - */ -#define CAN_ERROR_WARNING_LIMIT_FLAG (CAN_ERRINT_EWARN_MASK) /**< CAN Error Limit reached */ -#define CAN_ERROR_PASSIVE_MODE_ACTIVE_FLAG (CAN_ERRINT_EPASS_MASK) /**< CAN Passive mode active */ -#define CAN_ERROR_PASSIVE_INT_ENABLE (CAN_ERRINT_EPIE_MASK) /**< CAN Passive Interrupt Enable */ -#define CAN_ERROR_PASSIVE_INT_FLAG (CAN_ERRINT_EPIF_MASK) /**< CAN Passive Interrupt Flag */ -#define CAN_ERROR_ARBITRATION_LOST_INT_ENABLE (CAN_ERRINT_ALIE_MASK) /**< CAN Arbitration Lost Interrupt Enable */ -#define CAN_ERROR_ARBITRATION_LOST_INT_FLAG (CAN_ERRINT_ALIE_MASK) /**< CAN arbitration Lost Interrupt Flag */ -#define CAN_ERROR_BUS_ERROR_INT_ENABLE (CAN_ERRINT_BEIE_MASK) /**< CAN BUS error Interrupt Enable */ -#define CAN_ERROR_BUS_ERROR_INT_FLAG (CAN_ERRINT_BEIF_MASK) /**< CAN BUS error Interrupt flag */ - -/** - * @brief CAN Error Kinds - * - */ -#define CAN_KIND_OF_ERROR_NO_ERROR (0U) /**< No error */ -#define CAN_KIND_OF_ERROR_BIT_ERROR (1U) /**< Bit error */ -#define CAN_KIND_OF_ERROR_FORM_ERROR (2U) /**< Form error */ -#define CAN_KIND_OF_ERROR_STUFF_ERROR (3U) /**< Stuff error */ -#define CAN_KIND_OF_ERROR_ACK_ERROR (4U) /**< Acknowledgment error */ -#define CAN_KIND_OF_ERROR_CRC_ERROR (5U) /**< CRC error */ -#define CAN_KIND_OF_ERROR_OTHER_ERROR (6U) /**< Other errors */ -#define CAN_KIND_OF_ERROR_BUS_OFF (7U) /**< BUS off error */ - -/** - * @brief CAN loopback types - */ -typedef enum _can_mode { - can_mode_normal, /**< Non-loopback mode */ - can_mode_loopback_internal, /**< Internal loopback mode */ - can_mode_loopback_external, /**< External loopback mode */ - can_mode_listen_only, /**< CAN listen mode */ -} can_node_mode_t; - -/** - * @brief CAN bit timing options - */ -typedef enum _can_bit_timing_option { - can_bit_timing_can2_0, /**< CAN 2.0 bit timing option */ - can_bit_timing_canfd_nominal, /**< CANFD nominal timing option */ - can_bit_timing_canfd_data, /**< CANFD data timing option */ -} can_bit_timing_option_t; - -/** - * @brief CAN DLC definitions - */ -enum { - can_payload_size_0 = 0, /**< Payload size is 0 */ - can_payload_size_1, /**< Payload size is 1 */ - can_payload_size_2, /**< Payload size is 2 */ - can_payload_size_3, /**< Payload size is 3 */ - can_payload_size_4, /**< Payload size is 4 */ - can_payload_size_5, /**< Payload size is 5 */ - can_payload_size_6, /**< Payload size is 6 */ - can_payload_size_7, /**< Payload size is 7 */ - can_payload_size_8, /**< Payload size is 8 */ - can_payload_size_12, /**< Payload size is 12 */ - can_payload_size_16, /**< Payload size is 16 */ - can_payload_size_20, /**< Payload size is 20 */ - can_payload_size_24, /**< Payload size is 24 */ - can_payload_size_32, /**< Payload size is 32 */ - can_payload_size_48, /**< Payload size is 48 */ - can_payload_size_64, /**< Payload size is 64 */ - can_payload_size_max = can_payload_size_64, -}; - -/** - * @brief CAN Bit timing parameters - */ -typedef struct { - uint16_t prescaler; /**< Prescaler value */ - uint16_t num_seg1; /**< Seg1 value */ - uint16_t num_seg2; /**< Seg2 value */ - uint16_t num_sjw; /**< SJW value */ -} can_bit_timing_param_t; - -/** - * @brief CAN receive buffer data structure - */ -typedef union _can_rx_buf { - uint32_t buffer[20]; /**< CAN buffer size */ - struct { - struct { - uint32_t id: 29; /**< CAN ID */ - uint32_t : 1; - uint32_t error_state_indicator: 1; /**< Error state indicator */ - }; - struct { - uint32_t dlc: 4; /**< Data length option */ - uint32_t bitrate_switch: 1; /**< bitrate switch flag */ - uint32_t canfd_frame: 1; /**< CANFD frame flag */ - uint32_t remote_frame: 1; /**< Remote frame flag */ - uint32_t extend_id: 1; /**< Extended ID flag */ - uint32_t : 4; - uint32_t loopback_message: 1; /**< Loopback message flag */ - uint32_t error_type: 3; /**< Error type */ - uint32_t cycle_time: 16; /**< Cycle time */ - }; - uint8_t data[]; /**< Data pointer */ - }; -} can_receive_buf_t; - -/** - * @brief CAN transmit buffer data structure - */ -typedef union _can_tx_buf { - uint32_t buffer[18]; /**< CAN transmit buffer */ - struct { - struct { - uint32_t id: 29; /**< CAN ID */ - uint32_t : 2; - uint32_t transmit_timestamp_enable: 1; /**< Timestamp enable flag */ - }; - struct { - uint32_t dlc: 4; /**< Data length option */ - uint32_t bitrate_switch: 1; /**< bitrate switch flag */ - uint32_t canfd_frame: 1; /**< CANFD frame flag */ - uint32_t remote_frame: 1; /**< remote_frame flag */ - uint32_t extend_id: 1; /**< Extended ID flag */ - uint32_t : 24; - }; - uint8_t data[]; /**< Data pointer */ - }; -} can_transmit_buf_t; - -/** - * @brief CAN acceptance filter modes - */ -typedef enum _can_filter_id_mode { - can_filter_id_mode_both_frames, /**< Accept both standard frame and extended frame */ - can_filter_id_mode_standard_frames, /**< Accept standard frame only */ - can_filter_id_mode_extended_frames, /**< Accept extended frame only */ -} can_filter_id_mode_t; - -/** - * @brief CAN acceptance filter configuration - */ -typedef struct { - uint16_t index; /**< CAN filter index */ - can_filter_id_mode_t id_mode; /**< CAN filter id mode */ - bool enable; /**< CAN filter enable flag */ - uint32_t code; /**< CAN filter code */ - uint32_t mask; /**< CAN filter mask */ -} can_filter_config_t; - -/** - * @brief CAN configuration - */ -typedef struct { - union { - struct { - uint32_t baudrate; /**< CAN2.0 baudrate / CANFD nominal baudrate */ - uint32_t baudrate_fd; /**< CANFD data baudrate */ - /**< minimum sampling point, value range (0-1000), samplepoint_min/1000 will be used in driver */ - uint16_t can20_samplepoint_min; - /**< maximum sampling point, value range (0-1000), samplepoint_max/1000 will be used in driver */ - uint16_t can20_samplepoint_max; - /**< minimum sampling point, value range (0-1000), samplepoint_min/1000 will be used in driver */ - uint16_t canfd_samplepoint_min; - /**< maximum sampling point, value range (0-1000), samplepoint_max/1000 will be used in driver */ - uint16_t canfd_samplepoint_max; - }; - struct { - can_bit_timing_param_t can_timing; /**< CAN2.0 /CANFD nominal low-level bit timing parameters */ - can_bit_timing_param_t canfd_timing;/**< CANFD low-level bit timing parameters */ - }; - }; - - can_node_mode_t mode; /**< CAN work mode */ - bool use_lowlevel_timing_setting; /**< Use low-level timing setting */ - bool enable_canfd; /**< Enable CAN FD */ - bool enable_self_ack; /**< CAN self-ack flag */ - bool disable_ptb_retransmission; /**< disable re-transmission for primary transmit buffer */ - bool disable_stb_retransmission; /**< disable re-transmission for secondary transmit buffer */ - bool enable_tdc; /**< Enable transmitter delay compensation */ - - uint8_t filter_list_num; /**< element number of CAN filters in filter list */ - can_filter_config_t *filter_list; /**< CAN filter list pointer */ - - uint8_t irq_txrx_enable_mask; /**< CAN TX and RX IRQ Enable Mask */ - uint8_t irq_error_enable_mask; /**< CAN Error IRQ Enable Mask */ - bool enable_tx_buffer_priority_mode; /**< Enable Priority-based priority */ - bool enable_can_fd_iso_mode; /**< Enable CAN-FD ISO mode */ -} can_config_t; - - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @brief Reset CAN controller - * - * @param [in] base CAN base address - * @param [in] enable reset flag for CAN controller - * @arg true reset the CAN controller - * @arg false clear the CAN controller reset flag - */ -static inline void can_reset(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RESET_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_RESET_MASK; - } -} - -/** - * @brief Force CAN controller to Bus-off mode - * @param [in] base CAN base address - */ -static inline void can_force_bus_off(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL = CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK; -} - -/** - * @brief Set CAN mode - * - * @param [in] base CAN base address - * @param [in] mode CAN loopback mode - * @arg can_mode_normal Normal work mode - * @arg can_mode_loopback_internal internal loopback mode - * @arg can_mode_loopback_external external loopback mode - * @arg can_mode_listen_only CAN listen-only mode - */ -static inline void can_set_node_mode(CAN_Type *base, can_node_mode_t mode) -{ - uint32_t cfg_stat = base->CMD_STA_CMD_CTRL & ~(CAN_CMD_STA_CMD_CTRL_LBME_MASK | CAN_CMD_STA_CMD_CTRL_LBMI_MASK | CAN_CMD_STA_CMD_CTRL_LOM_MASK); - if (mode == can_mode_loopback_internal) { - cfg_stat |= CAN_CMD_STA_CMD_CTRL_LBMI_MASK; - } else if (mode == can_mode_loopback_external) { - cfg_stat |= CAN_CMD_STA_CMD_CTRL_LBME_MASK; - } else if (mode == can_mode_listen_only) { - cfg_stat |= CAN_CMD_STA_CMD_CTRL_LOM_MASK; - } else { - /* CAN normal work mode, no change needed here */ - } - base->CMD_STA_CMD_CTRL = cfg_stat; -} - -/** - * @brief Enable CAN listen-only mode - * @param [in] base CAN base address - * @param [in] enable CAN listen-only mode enable flag - * @arg true enable listen-only mode - * @arg false disable listen-only mode - */ -static inline void can_enable_listen_only_mode(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_LOM_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_LOM_MASK; - } -} - -/** - * @brief Enter CAN standby mode - * @param [in] base CAN base address - * @param [in] enable Can standby mode enable flag - * @arg true enable standby mode - * @arg false disable standby mode - */ -static inline void can_enter_standby_mode(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_STBY_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_STBY_MASK; - } -} - -/** - * @brief Disable the re-transmission for the primary transmission buffer - * - * @param [in] base CAN base address - * @param [in] enable Flag for disabling re-transmission for PTB - */ -static inline void can_disable_ptb_retransmission(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPSS_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TPSS_MASK; - } -} - -/** - * @brief Check whether re-transmission is disabled for PTB or not - * - * @param [in] base CAN base address - * @return true Re-transmission is disabled for PTB - * @return false Re-transmission is enabled for PTB - */ -static inline bool can_is_ptb_retransmission_disabled(CAN_Type *base) -{ - return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) != 0); -} - -/** - * @brief Disable the re-transmission for the secondary transmission buffer - * - * @param [in] base CAN base address - * @param [in] enable Flag for disabling re-transmission for STB - */ -static inline void can_disable_stb_retransmission(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSSS_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSSS_MASK; - } -} - -/** - * @brief Check whether re-transmission is disabled for STB or not - * - * @param [in] base CAN base address - * @return true Re-transmission is disabled for STB - * @return false Re-transmission is enabled for STB - */ -static inline bool can_is_stb_retransmission_disabled(CAN_Type *base) -{ - return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) != 0); -} - - -/** - * @brief Select CAN TX buffer - * @param [in] base CAN base address - * @param [in] select_secondary_buffer CAN secondary transmit buffer selection flag - * @arg true Select the secondary transmit buffer - * @arg false Select the primary transmit buffer - */ -static inline void can_select_tx_buffer(CAN_Type *base, bool select_secondary_buffer) -{ - if (select_secondary_buffer) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; - } -} - -/** - * @brief Start CAN high priority message transmit - * @param [in] base CAN base address - * - */ -static inline void can_start_high_priority_message_transmit(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPE_MASK; -} - -/** - * @brief Abort CAN high priority message transmit - * @param [in] base CAN base address - */ -static inline void can_abort_high_priority_message_transmit(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPA_MASK; -} - -/** - * @brief Start CAN message transmit - * @param [in] base CAN base address - */ -static inline void can_start_message_transmit(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSONE_MASK; -} - -/** - * @brief Start CAN all messages transmit - * @param [in] base CAN base address - */ -static inline void can_start_all_message_transmit(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSALL_MASK; -} - -/** - * @brief Abort CAN message transmit - * @param [in] base CAN base address - */ -static inline void can_abort_message_transmit(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSA_MASK; -} - -/** - * @brief Switch to next CAN tx buffer - * @param [in] base CAN base address - */ -static inline void can_switch_to_next_tx_buffer(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK; -} - -/** - * @brief Select CAN tx buffer priority mode - * @param [in] base CAN base address - * @param [in] enable_priority_decision CAN tx buffer priority mode selection flag - * @arg true priority decision mode - * @arg false FIFO mode - */ -static inline void can_select_tx_buffer_priority_mode(CAN_Type *base, bool enable_priority_decision) -{ - if (enable_priority_decision) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSMODE_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TSMODE_MASK; - } -} - -/** - * @brief Get CAN secondary transmit buffer status - * @param [in] base CAN base address - * @retval secondary transmit buffer status, 0: empty, 1: <= 1/2 full, 2: > 1/2 full, 3: full - * - */ -static inline uint8_t can_get_secondary_transmit_buffer_status(CAN_Type *base) -{ - return CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL); -} - -/** - * @brief Check whether the primary transmit buffer is full - * @param [in] base CAN base address - * @return true for full - */ -static inline bool can_is_primary_transmit_buffer_full(CAN_Type *base) -{ - return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_TPE_MASK) != 0U); -} - -/** - * @brief Check whether the secondary transmit buffer is full - * @param [in] base CAN base address - * @return true for full - */ -static inline bool can_is_secondary_transmit_buffer_full(CAN_Type *base) -{ - return (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_STB_IS_FULL); -} - -/** - * @brief Check whether the CAN is in BUS off mode - * - * @param [in] base CAN base address - * @return true for bus off mode - * @return false for non-bus off mode - */ -static inline bool can_is_in_bus_off_mode(CAN_Type *base) -{ - return ((base->CMD_STA_CMD_CTRL & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) != 0U); -} - -/** - * @brief Enable can self ack - * @param [in] base CAN base address - * @param [in] enable Self-ack enable flag, true or false - * - */ -static inline void can_enable_self_ack(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_SACK_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_SACK_MASK; - } -} - -/** - * @brief Set CAN receive buffer overflow mode - * @param [in] base CAN base address - * @param [in] override_enable receive buffer overflow mode option - * @arg true the oldest message will be overwritten - * @arg false the new message will not be stored - */ -static inline void can_set_receive_buffer_overflow_mode(CAN_Type *base, bool override_enable) -{ - if (override_enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_ROM_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_ROM_MASK; - } -} - -/** - * @brief Check whether CAN receive buffer is overflow - * @param [in] base CAN base address - * @retval true or false - */ -static inline bool can_is_receive_buffer_overflow(CAN_Type *base) -{ - return IS_HPM_BITMASK_SET(base->CMD_STA_CMD_CTRL, CAN_CMD_STA_CMD_CTRL_ROV_MASK); -} - -/** - * @brief Release CAN receive buffer - * - * @param [in] base CAN base address - */ -static inline void can_release_receive_buffer(CAN_Type *base) -{ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RREL_MASK; -} - -/** - * @brief Allow can store all date in receive buffer - * @param [in] base CAN base address - * @param [in] allow flag to determine whether to store error data frame - */ -static inline void can_allow_store_all_data_in_receive_buffer(CAN_Type *base, bool allow) -{ - if (allow) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RBALL_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_RBALL_MASK; - } -} - -/** - * @brief Get CAN receive buffer status - * @param [in] base CAN base address - * @retval Receive buffer status, 0: empty, 1: > empty, < almost full, 2: >= almost full, 3: full - */ -static inline uint8_t can_get_receive_buffer_status(CAN_Type *base) -{ - return CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL); -} - -/** - * @brief Check whether there are data available in receive buffer - * @param [in] base CAN base address - * @return true if the receive buffer is not empty - */ -static inline bool can_is_data_available_in_receive_buffer(CAN_Type *base) -{ - return (CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL) != CAN_RXBUF_IS_EMPTY); -} - - -/** - * @brief Enable CAN FD ISO mode - * @param [in] base CAN base address - * @param enable CAN-FD ISO mode enable flag - */ -static inline void can_enable_can_fd_iso_mode(CAN_Type *base, bool enable) -{ - if (enable) { - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK; - } else { - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK; - } -} - -/** - * @brief Enable CAN TX/RX interrupt - * @param [in] base CAN base address - * @param [in] mask CAN interrupt mask - */ -static inline void can_enable_tx_rx_irq(CAN_Type *base, uint8_t mask) -{ - base->RTIE |= mask; -} - -/** - * @brief Disable CAN TX/RX interrupt - * @param [in] base CAN base address - * @param [in] mask CAN interrupt mask - */ -static inline void can_disable_tx_rx_irq(CAN_Type *base, uint8_t mask) -{ - base->RTIE &= ~mask; -} - -/** - * @brief Clear CAN TX/RX flags - * @param [in] base CAN base address - * @param [in] flags CAN TX/RX interrupt flags - */ -static inline void can_clear_tx_rx_flags(CAN_Type *base, uint8_t flags) -{ - base->RTIF = flags; -} - -/** - * @brief Get CAN TX/RX flags - * - * @param [in] base CAN base address - * @retval CAN Tx/RX interrupt flags - */ -static inline uint8_t can_get_tx_rx_flags(CAN_Type *base) -{ - return base->RTIF; -} - -/** - * @brief Enable CAN error interrupt - * @param [in] base CAN base address - * @param [in] mask CAN error interrupt mask - */ -static inline void can_enable_error_irq(CAN_Type *base, uint8_t mask) -{ - base->ERRINT |= mask; -} - -/** - * @brief Disable CAN error interrupt - * - * @param [in] base CAN base address - * @param [in] mask CAN error interrupt mask - */ -static inline void can_disable_error_irq(CAN_Type *base, uint8_t mask) -{ - base->ERRINT &= ~mask; -} - -/** - * @brief Get CAN error interrupt flags - * @param [in] base CAN base address - * @retval CAN error interrupt flags - */ -static inline uint8_t can_get_error_interrupt_flags(CAN_Type *base) -{ - return (base->ERRINT & (uint8_t) ~(CAN_ERRINT_EPIE_MASK | CAN_ERRINT_ALIE_MASK | CAN_ERRINT_BEIE_MASK)); -} - -/** - * @brief Get CAN clear interrupt flags - * @param [in] base CAN base address - * @param [in] flags CAN error interrupt flags - */ -static inline void can_clear_error_interrupt_flags(CAN_Type *base, uint8_t flags) -{ - flags &= (uint8_t)~(CAN_ERRINT_EPIE_MASK | CAN_ERRINT_ALIE_MASK | CAN_ERRINT_BEIE_MASK); - base->ERRINT |= flags; -} - -/** - * @brief Get last CAN error kind - * @param [in] base CAN base address - * @retval CAN last error kind - */ -static inline uint8_t can_get_last_error_kind(CAN_Type *base) -{ - return CAN_EALCAP_KOER_GET(base->EALCAP); -} - -/** - * @brief Get CAN last arbitrary lost position - * @param [in] base CAN base address - * @retval CAN last arbitrary lost position - */ -static inline uint8_t can_get_last_arbitration_lost_position(CAN_Type *base) -{ - return CAN_EALCAP_ALC_GET(base->EALCAP); -} - -/** - * @brief Set CAN transmitter delay compensation - * - * @param [in] base CAN base address - * @param [in] sample_point delay compensation sample point - * @param [in] enable delay compensation enable flag - */ -static inline void can_set_transmitter_delay_compensation(CAN_Type *base, uint8_t sample_point, bool enable) -{ -#if defined(CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND) && (CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND == 1) - (void) sample_point; - (void) enable; - base->TDC = CAN_TDC_TDCEN_SET((uint8_t) enable); -#else - base->TDC = CAN_TDC_SSPOFF_SET(sample_point) | CAN_TDC_TDCEN_SET((uint8_t) enable); -#endif -} - -/** - * @brief Set CAN warning limits - * @param [in] base CAN base address - * @param [in] almost_full_limit - * @param [in] error_warning_limit - */ -static inline void can_set_warning_limits(CAN_Type *base, uint8_t almost_full_limit, uint8_t error_warning_limit) -{ - base->LIMIT = CAN_LIMIT_AFWL_SET(almost_full_limit) | CAN_LIMIT_EWL_SET(error_warning_limit); -} - -/** - * @brief Get CAN receive error count - * @param [in] base CAN base address - * @retval CAN receive error count - */ -static inline uint8_t can_get_receive_error_count(CAN_Type *base) -{ - return base->RECNT; -} - -/** - * @brief Get CAN transmit error count - * @param [in] base CAN base address - * @retval CAN transmit error count - */ -static inline uint8_t can_get_transmit_error_count(CAN_Type *base) -{ - return base->TECNT; -} - -/** - * @brief Enable a specified CAN filter - * - * @param [in] base CAN base address - * @param index CAN filter index - */ -static inline void can_enable_filter(CAN_Type *base, uint32_t index) -{ - base->ACF_EN |= (uint16_t) (1U << index); -} - -/** - * @brief Disable a specified CAN filter - * - * @param [in] base CAN base address - * @param index CAN filter index - */ -static inline void can_disable_filter(CAN_Type *base, uint32_t index) -{ - base->ACF_EN &= (uint16_t) ~(1U << index); -} - -/** - * @brief Get default CAN configuration parameters - * @param [out] config CAN configuration structure - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_get_default_config(can_config_t *config); - -/** - * @brief Initialize the CAN controller - * @param [in] base CAN base address - * @param [in] config CAN configuration - * @param [in] src_clk_freq CAN IP source clock frequency - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq); - -/** - * @brief De-initialize the CAN controller - * @param [in] base CAN base address - */ -void can_deinit(CAN_Type *base); - - -/** - * @brief Configure the Slow Speed Bit timing using low-level interface - * @param [in] base CAN base address - * @param [in] param CAN bit timing parameter - */ -static inline void can_set_slow_speed_timing(CAN_Type *base, const can_bit_timing_param_t *param) -{ - base->S_PRESC = CAN_S_PRESC_S_PRESC_SET(param->prescaler - 1U) | CAN_S_PRESC_S_SEG_1_SET(param->num_seg1 - 2U) | - CAN_S_PRESC_S_SEG_2_SET(param->num_seg2 - 1U) | CAN_S_PRESC_S_SJW_SET(param->num_sjw - 1U); -} - -/** - * @brief Configure the Fast Speed Bit timing using low-level interface - * @param [in] base CAN base address - * @param [in] param CAN bit timing parameter - */ -static inline void can_set_fast_speed_timing(CAN_Type *base, const can_bit_timing_param_t *param) -{ - base->F_PRESC = CAN_F_PRESC_F_PRESC_SET(param->prescaler - 1U) | CAN_F_PRESC_F_SEG_1_SET(param->num_seg1 - 2U) | - CAN_F_PRESC_F_SEG_2_SET(param->num_seg2 - 1U) | CAN_F_PRESC_F_SJW_SET(param->num_sjw - 1U); -} - -/** - * @brief Configure the CAN bit timing for CAN BUS - * @param [in] base CAN base address - * @param [in] option CAN bit timing option - * @param [in] src_clk_freq CAN IP source clock frequency - * @param [in] baudrate CAN baudrate in MHz - * @param [in] samplepoint_min Minimum Sample point, range(0-1000), samplepoint_min / 1000 will be used in calculation - * @param [in] samplepoint_max Maximum Sample point, range(0-1000), samplepoint_max / 1000 will be used in calculation - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_set_bit_timing(CAN_Type *base, can_bit_timing_option_t option, - uint32_t src_clk_freq, uint32_t baudrate, - uint16_t samplepoint_min, uint16_t samplepoint_max); - - -/** - * @brief Calculate the CAN bit timing for CAN BUS - * @param [in] src_clk_freq CAN IP source clock frequency - * @param [in] option CAN bit timing option - * @param [in] baudrate CAN baudrate in MHz - * @param [in] samplepoint_min Minimum Sample point, range(0-1000), samplepoint_min / 1000 will be used in calculation - * @param [in] samplepoint_max Maximum Sample point, range(0-1000), samplepoint_max / 1000 will be used in calculation - * @param [out] timing_param Calculated CAN bit timing parameter - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_calculate_bit_timing(uint32_t src_clk_freq, can_bit_timing_option_t option, uint32_t baudrate, - uint16_t samplepoint_min, uint16_t samplepoint_max, - can_bit_timing_param_t *timing_param); - - - -/** - * @brief Configure the acceptable filter - * @param [in] base CAN base address - * @param [in] config CAN filter configuration - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_set_filter(CAN_Type *base, const can_filter_config_t *config); - -/** - * @brief Send CAN message using blocking transfer - * @param [in] base CAN base address - * @param [in] message CAN message to be sent out - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_send_message_blocking(CAN_Type *base, const can_transmit_buf_t *message); - -/** - * @brief Send high-priority message using blocking transfer - * @param [in] base CAN base address - * @param [in] message CAN message to be sent out - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_send_high_priority_message_blocking(CAN_Type *base, const can_transmit_buf_t *message); - - -/** - * @brief Send CAN message using non-blocking transfer - * @param [in] base CAN base address - * @param [in] message CAN message to be sent out - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_send_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message); - -/** - * @brief Send high-priority message using non-blocking transfer - * @param [in] base CAN base address - * @param [in] message CAN message to be sent out - * @retval API execution status, status_success or status_invalid_argument - */ -hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message); - -/** - * @brief Receive CAN message using blocking transfer - * - * @param [in] base CAN base address - * @param [out] message CAN message buffer - * - * @retval status_success API execution is successful - * @retval status_invalid_argument Invalid parameters - * @retval status_can_bit_error CAN bit error happened during receiving message - * @retval status_can_form_error CAN form error happened during receiving message - * @retval status_can_stuff_error CAN stuff error happened during receiving message - * @retval status_can_ack_error CAN ack error happened during receiving message - * @retval status_can_crc_error CAN crc error happened during receiving message - * @retval status_can_other_error Other error happened during receiving message - */ -hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *message); - - -/** - * @brief Read Received CAN message - * - * @note This API assumes that the received CAN message is available. - * It can be used in the interrupt handler - * @param [in] base CAN base address - * @param [out] message CAN message buffer - * - * @retval status_success API execution is successful - * @retval status_invalid_argument Invalid parameters - * @retval status_can_bit_error CAN bit error happened during receiving message - * @retval status_can_form_error CAN form error happened during receiving message - * @retval status_can_stuff_error CAN stuff error happened during receiving message - * @retval status_can_ack_error CAN ack error happened during receiving message - * @retval status_can_crc_error CAN crc error happened during receiving message - * @retval status_can_other_error Other error happened during receiving message - */ -hpm_stat_t can_read_received_message(CAN_Type *base, can_receive_buf_t *message); - -/** - * @} - * - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* HPM_CAN_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_clc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_clc_drv.h deleted file mode 100644 index 9528ec7204d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_clc_drv.h +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_CLC_DRV_H -#define HPM_CLC_DRV_H - -#include "hpm_common.h" -#include "hpm_clc_regs.h" - -/** - * @brief CLC driver APIs - * @defgroup clc_interface CLC driver APIs - * @ingroup motor_interfaces - * @{ - */ - -/** - * @brief clc channel - */ -typedef enum { - clc_vd_chn = CLC_VDVQ_CHAN_VD, - clc_vq_chn = CLC_VDVQ_CHAN_VQ, -} clc_chn_t; /**< clc_chn_t */ - -/** - * @brief clc coefficient zone - */ -typedef enum { - clc_coeff_zone_0 = CLC_COEFF_0, - clc_coeff_zone_1 = CLC_COEFF_1, - clc_coeff_zone_2 = CLC_COEFF_2, -} clc_coeff_zone_t; /**< clc_coeff_zone_t */ - -/** - * @brief clc irq mask bit - */ -typedef enum { - clc_irq_calc_done = BIT0_MASK, - clc_irq_eadc_setting_err = BIT1_MASK, - clc_irq_2p2z_clamp_setting_err = BIT2_MASK, - clc_irq_2p2z_over_hi = BIT3_MASK, - clc_irq_2p2z_over_lo = BIT4_MASK, - clc_irq_2p2z_over_sf = BIT5_MASK, - clc_irq_3p3z_clamp_setting_err = BIT6_MASK, - clc_irq_3p3z_over_hi = BIT7_MASK, - clc_irq_3p3z_over_lo = BIT8_MASK, - clc_irq_forb_setting_err = BIT9_MASK, - clc_irq_data_in_forbid = BIT10_MASK -} clc_irq_mask_t; - -/** - * @brief clc parameter configuration - */ -typedef struct { - int32_t eadc_lowth; - int32_t eadc_mid_lowth; - int32_t eadc_mid_highth; - int32_t eadc_highth; - int32_t _2p2z_clamp_lowth; - int32_t _2p2z_clamp_highth; - int32_t _3p3z_clamp_lowth; - int32_t _3p3z_clamp_highth; - int32_t output_forbid_lowth; - int32_t output_forbid_mid; - int32_t output_forbid_highth; -} clc_param_config_t; /**< clc_param_config_t */ - -/** - * @brief clc coefficient configuration - */ -typedef struct { - float b0; - float b1; - float b2; - float b3; - float a0; - float a1; - float a2; -} clc_coeff_config_t; /**< clc_coeff_config_t */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief CLC enable or disable - * - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] enable true-enable, false-disable - */ -static inline void clc_set_enable(CLC_Type *clc, clc_chn_t chn, bool enable) -{ - if (enable) { - clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK; - } else { - clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK; - } -} - -/** - * @brief CLC keep working even if bad irq status ocurred - * - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] enable true-enable, false-disable - */ -static inline void clc_set_mask_mode_enable(CLC_Type *clc, clc_chn_t chn, bool enable) -{ - if (enable) { - clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK; - } else { - clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK; - } -} - -/** - * @brief CLC set software inject dq work mode - * - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] enable true-if the ADC value comes from software injection and the VD/VQ channel is required for joint use. - */ -static inline void clc_set_sw_inject_dq_mode_enable(CLC_Type *clc, clc_chn_t chn, bool enable) -{ - if (enable) { - clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK; - } else { - clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK; - } -} - -/** - * @brief CLC set irq enable or disable - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] irq_mask irq mask, @ref clc_irq_mask_t - * @param[in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void clc_set_irq_enable(CLC_Type *clc, clc_chn_t chn, uint32_t irq_mask, bool enable) -{ - if (enable) { - clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(irq_mask); - } else { - clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(irq_mask); - } -} - -/** - * @brief CLC get irq status - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - - * @retval irq status. - */ -static inline uint32_t clc_get_irq_status(CLC_Type *clc, clc_chn_t chn) -{ - return CLC_VDVQ_CHAN_STATUS_STATUS_GET(clc->VDVQ_CHAN[chn].STATUS); -} - -/** - * @brief CLC clear irq status - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] irq_mask irq mask, @ref clc_irq_mask_t - */ -static inline void clc_clear_irq_status(CLC_Type *clc, clc_chn_t chn, uint32_t irq_mask) -{ - clc->VDVQ_CHAN[chn].STATUS = CLC_VDVQ_CHAN_STATUS_STATUS_SET(irq_mask); -} - -/** - * @brief CLC check irq request flag - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] irq_mask irq mask, @ref clc_irq_mask_t - - * @retval true-has irq req, false-no irq req. - */ -static inline bool clc_get_irq_flag(CLC_Type *clc, clc_chn_t chn, uint32_t irq_mask) -{ - return ((clc->VDVQ_CHAN[chn].STATUS & irq_mask) == irq_mask) ? true : false; -} - -/** - * @brief CLC set adc channel - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] adc_chn adc channel for ADC0~3 or SDM_ADC0~7, adc from VSC must be set to 0. - * @param[in] adc_offset adc offset for ADC0~3 or SDM_ADC0~7, adc from VSC must be set to 0. - */ -static inline void clc_set_adc_chn_offset(CLC_Type *clc, clc_chn_t chn, uint32_t adc_chn, uint32_t adc_offset) -{ - clc->VDVQ_CHAN[chn].ADC_CHAN = adc_chn; - clc->VDVQ_CHAN[chn].ADC_OFFSET = adc_offset; -} - -/** - * @brief CLC set pwm period - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] pwm_period 0-clc dac output pwm duty ratio, else-clc dac output pwm period, number of clock cycles. - */ -static inline void clc_set_pwm_period(CLC_Type *clc, clc_chn_t chn, uint32_t pwm_period) -{ - clc->VDVQ_CHAN[chn].PWM_PERIOD = pwm_period; -} - -/** - * @brief CLC set pwm period - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval pwm period - */ -static inline uint32_t clc_get_pwm_period(CLC_Type *clc, clc_chn_t chn) -{ - return clc->VDVQ_CHAN[chn].PWM_PERIOD; -} - -/** - * @brief CLC get output caculated value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC output caculated value - */ -static inline uint32_t clc_get_output_value(CLC_Type *clc, clc_chn_t chn) -{ - return clc->VDVQ_CHAN[chn].OUTPUT_VALUE; -} - -/** - * @brief CLC get timestamp - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC adc timestamp - */ -static inline uint32_t clc_get_timestamp(CLC_Type *clc, clc_chn_t chn) -{ - return clc->VDVQ_CHAN[chn].TIMESTAMP; -} - -/** - * @brief CLC get error adc latest value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC error adc latest value - */ -static inline int32_t clc_get_eadc_current_value(CLC_Type *clc, clc_chn_t chn) -{ - return (int32_t)clc->VDVQ_CHAN[chn].EADC_CURR; -} - -/** - * @brief CLC get error adc previous0 value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC error adc previous0 value - */ -static inline int32_t clc_get_eadc_previous0_value(CLC_Type *clc, clc_chn_t chn) -{ - return (int32_t)clc->VDVQ_CHAN[chn].EADC_PRE0; -} - -/** - * @brief CLC software inject error adc previous0 value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] value CLC error adc previous0 value - */ -static inline void clc_sw_inject_eadc_previous0_value(CLC_Type *clc, clc_chn_t chn, int32_t value) -{ - clc->VDVQ_CHAN[chn].EADC_PRE0 = (uint32_t)value; -} - -/** - * @brief CLC get error adc previous1 value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC error adc previous1 value - */ -static inline int32_t clc_get_eadc_previous1_value(CLC_Type *clc, clc_chn_t chn) -{ - return (int32_t)clc->VDVQ_CHAN[chn].EADC_PRE1; -} - -/** - * @brief CLC software inject error adc previous1 value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] value CLC error adc previous1 value - */ -static inline void clc_sw_inject_eadc_previous1_value(CLC_Type *clc, clc_chn_t chn, int32_t value) -{ - clc->VDVQ_CHAN[chn].EADC_PRE1 = (uint32_t)value; -} - -/** - * @brief CLC get 2p2z last value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC 2p2z last value - */ -static inline int32_t clc_get_2p2z_current_value(CLC_Type *clc, clc_chn_t chn) -{ - return (int32_t)clc->VDVQ_CHAN[chn].P2Z2_CURR; -} - -/** - * @brief CLC software inject 2p2z last value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] value CLC 2p2z last value - */ -static inline void clc_sw_inject_2p2z_current_value(CLC_Type *clc, clc_chn_t chn, int32_t value) -{ - clc->VDVQ_CHAN[chn].P2Z2_CURR = (uint32_t)value; -} - -/** - * @brief CLC get 2p2z previous0 value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC 2p2z previous0 value - */ -static inline int32_t clc_get_2p2z_previous0_value(CLC_Type *clc, clc_chn_t chn) -{ - return (int32_t)clc->VDVQ_CHAN[chn].P2Z2_PRE0; -} - -/** - * @brief CLC software inject 2p2z previous0 value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] value CLC 2p2z previous0 value - */ -static inline void clc_sw_inject_2p2z_previous0_value(CLC_Type *clc, clc_chn_t chn, int32_t value) -{ - clc->VDVQ_CHAN[chn].P2Z2_PRE0 = (uint32_t)value; -} - -/** - * @brief CLC get 3p3z last value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @retval CLC 3p3z last value - */ -static inline int32_t clc_get_3p3z_current_value(CLC_Type *clc, clc_chn_t chn) -{ - return (int32_t)clc->VDVQ_CHAN[chn].P3Z3_CURR; -} - -/** - * @brief CLC software inject 3p3z last value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] value CLC 3p3z last value - */ -static inline void clc_sw_inject_3p3z_current_value(CLC_Type *clc, clc_chn_t chn, int32_t value) -{ - clc->VDVQ_CHAN[chn].P3Z3_CURR = (uint32_t)value; -} - -/** - * @brief CLC set expected adc value - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] expect expected adc value - */ -static inline void clc_set_expect_adc_value(CLC_Type *clc, clc_chn_t chn, int32_t expect) -{ - clc->VDVQ_CHAN[chn].ADC_EXPECT = (uint32_t)expect; -} - -/** - * @brief CLC software inject adc value. If it's not dq mode, this will trig clc calculation. - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] value CLC adc value - */ -static inline void clc_sw_inject_adc_value(CLC_Type *clc, clc_chn_t chn, uint32_t value) -{ - clc->VDVQ_CHAN[chn].ADC_SW = value; -} - -/** - * @brief CLC set software inject dq adc value ready, this will trig clc calculation. - * @param[in] clc CLC base address - */ -static inline void clc_set_sw_inject_dq_adc_value_ready(CLC_Type *clc) -{ - clc->DQ_ADC_SW_READY = CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK; -} - -/** - * @brief CLC parameter configuration - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] param @ref clc_param_config_t. - */ -void clc_config_param(CLC_Type *clc, clc_chn_t chn, clc_param_config_t *param); - -/** - * @brief CLC coefficient configuration - * @param[in] clc CLC base address - * @param[in] chn CLC channel, @ref clc_chn_t - * @param[in] zone CLC coefficient zone, @ref clc_coeff_zone_t - * @param[in] coeff @ref clc_param_config_t. - * - * @retval status_invalid_argument some parameters are invalid - * @retval status_success operation is successful - */ -hpm_stat_t clc_config_coeff(CLC_Type *clc, clc_chn_t chn, clc_coeff_zone_t zone, clc_coeff_config_t *coeff); - -/** - * @brief CLC software inject dq adc value - * @param[in] clc CLC base address - * @param[in] d_value CLC d adc value - * @param[in] q_value CLC q adc value - */ -void clc_sw_inject_dq_adc_value(CLC_Type *clc, uint32_t d_value, uint32_t q_value); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_CLC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h deleted file mode 100644 index c18a4c724b2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_COMMON_H -#define _HPM_COMMON_H - -#include -#include -#include -#include -#include - -/** - * - * @brief COMMON driver APIs - * @defgroup common_interface COMMON driver APIs - * @{ - * - */ - -#define __R volatile const /* Define "read-only" permission */ -#define __RW volatile /* Define "read-write" permission */ -#define __W volatile /* Define "write-only" permission */ - -#ifndef __I -#define __I __R -#endif - -#ifndef __IO -#define __IO __RW -#endif - -#ifndef __O -#define __O __W -#endif - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#endif - -#ifndef MAX -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#endif -#ifndef MIN -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#endif - -#ifndef HPM_ALIGN_DOWN -#define HPM_ALIGN_DOWN(a, n) ((uint32_t)(a) & ~(n-1U)) -#endif - -#ifndef HPM_ALIGN_UP -#define HPM_ALIGN_UP(a, n) (((uint32_t)(a) + (n-1U)) & ~(n-1U)) -#endif - -#define HPM_BITSMASK(val, offset) ((uint32_t)(val) << (offset)) -#define IS_HPM_BITMASK_SET(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U) -#define IS_HPM_BIT_SET(val, offset) (((uint32_t)(val) & (1UL << (offset))) != 0U) -#define IS_HPM_BITMASK_CLR(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) == 0U) -#define IS_HPM_BIT_CLR(val, offset) (((uint32_t)(val) & (1UL << (offset))) == 0U) - -#define HPM_BREAK_IF(cond) if (cond) { break; } -#define HPM_CONTINUE_IF(cond) if (cond) { continue; } - -#define HPM_DIV_ROUND_CLOSEST(x, div) (((x) + (div) / 2) / (div)) -#define HPM_DIV_ROUND_UP(x, div) (((x) + (div) - 1) / (div)) - -#define HPM_NUM_TO_EVEN_CEILING(x) ((x + 1) & 0xFFFFFFFEUL) -#define HPM_NUM_TO_EVEN_FLOOR(x) ((x) & 0xFFFFFFFEUL) - -#define HPM_CHECK_RET(x) \ - do { \ - stat = (x); \ - if (status_success != stat) { \ - return stat; \ - } \ - } while (false) - -#define SIZE_1KB (1024UL) -#define SIZE_1MB (1048576UL) - -#define BIT0_MASK (0x00000001UL) -#define BIT1_MASK (0x00000002UL) -#define BIT2_MASK (0x00000004UL) -#define BIT3_MASK (0x00000008UL) -#define BIT4_MASK (0x00000010UL) -#define BIT5_MASK (0x00000020UL) -#define BIT6_MASK (0x00000040UL) -#define BIT7_MASK (0x00000080UL) -#define BIT8_MASK (0x00000100UL) -#define BIT9_MASK (0x00000200UL) -#define BIT10_MASK (0x00000400UL) -#define BIT11_MASK (0x00000800UL) -#define BIT12_MASK (0x00001000UL) -#define BIT13_MASK (0x00002000UL) -#define BIT14_MASK (0x00004000UL) -#define BIT15_MASK (0x00008000UL) -#define BIT16_MASK (0x00010000UL) -#define BIT17_MASK (0x00020000UL) -#define BIT18_MASK (0x00040000UL) -#define BIT19_MASK (0x00080000UL) -#define BIT20_MASK (0x00100000UL) -#define BIT21_MASK (0x00200000UL) -#define BIT22_MASK (0x00400000UL) -#define BIT23_MASK (0x00800000UL) -#define BIT24_MASK (0x01000000UL) -#define BIT25_MASK (0x02000000UL) -#define BIT26_MASK (0x04000000UL) -#define BIT27_MASK (0x08000000UL) -#define BIT28_MASK (0x10000000UL) -#define BIT29_MASK (0x20000000UL) -#define BIT30_MASK (0x40000000UL) -#define BIT31_MASK (0x80000000UL) - -typedef uint32_t hpm_stat_t; - -/* @brief Enum definition for the Status group - * Rule: - * [Group] 0-999 for the SoC driver and the corresponding components - * 1000 or above for the application status group - * [Code] Valid value: 0-999 - * - */ -#define MAKE_STATUS(group, code) ((uint32_t)(group)*1000U + (uint32_t)(code)) -/* @brief System status group definitions */ -enum { - status_group_common = 0, - status_group_uart = 1, - status_group_i2c = 2, - status_group_spi = 3, - status_group_usb = 4, - status_group_i2s = 5, - status_group_xpi = 6, - status_group_l1c, - status_group_dma, - status_group_femc, - status_group_sdp, - status_group_xpi_nor, - status_group_otp, - status_group_lcdc, - status_group_mbx, - status_group_rng, - status_group_pdma, - status_group_wdg, - status_group_pmic_sec, - status_group_can, - status_group_sdxc, - status_group_pcfg, - status_group_clk, - status_group_pllctl, - status_group_pllctlv2, - status_group_ffa, - status_group_mcan, - status_group_ewdg, - status_group_esc, - - status_group_middleware_start = 500, - status_group_sdmmc = status_group_middleware_start, - status_group_audio_codec, - status_group_dma_manager, - status_group_spi_nor_flash, - status_group_touch, -}; - -/* @brief Common status code definitions */ -enum { - status_success = MAKE_STATUS(status_group_common, 0), - status_fail = MAKE_STATUS(status_group_common, 1), - status_invalid_argument = MAKE_STATUS(status_group_common, 2), - status_timeout = MAKE_STATUS(status_group_common, 3), -}; - -#if defined(__GNUC__) -/* weak */ -#define ATTR_WEAK __attribute__((weak)) - -#define HPM_ATTR_MACHINE_INTERRUPT __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4))) -#define HPM_ATTR_SUPERVISOR_INTERRUPT __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4))) - -#elif defined(__ICCRISCV__) -/* weak */ -#define ATTR_WEAK __weak - -#define HPM_ATTR_MACHINE_INTERRUPT __machine __interrupt -#define HPM_ATTR_SUPERVISOR_INTERRUPT __supervisor __interrupt - -#ifndef __TIMEVAL_DEFINED -#define __TIMEVAL_DEFINED 1 -struct timeval { - long tv_sec; /* Seconds since the Epoch */ - long tv_usec; /* Microseconds */ -}; -#endif - -#else -#error Unknown toolchain -#endif - -#if defined(__GNUC__) || defined(__ICCRISCV__) - -/* alway_inline */ -#define ATTR_ALWAYS_INLINE __attribute__((always_inline)) - -/* alignment */ -#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment))) -#define ATTR_PACKED __attribute__((packed, aligned(1))) - -/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */ -#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name))) - -#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \ -ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment) - -#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable") -#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \ - ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment) - -#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss") -#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \ - ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment) - -/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */ -#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init") -#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \ - ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment) - -/* .fast_ram section */ -#define ATTR_PLACE_AT_FAST_RAM ATTR_PLACE_AT(".fast_ram") -#define ATTR_PLACE_AT_FAST_RAM_WITH_ALIGNMENT(alignment) \ - ATTR_PLACE_AT_FAST_RAM ATTR_ALIGN(alignment) - -#define ATTR_PLACE_AT_FAST_RAM_BSS ATTR_PLACE_AT(".fast_ram.bss") -#define ATTR_PLACE_AT_FAST_RAM_BSS_WITH_ALIGNMENT(alignment) \ - ATTR_PLACE_AT_FAST_RAM_BSS ATTR_ALIGN(alignment) - -#define ATTR_PLACE_AT_FAST_RAM_INIT ATTR_PLACE_AT(".fast_ram.init") -#define ATTR_PLACE_AT_FAST_RAM_INIT_WITH_ALIGNMENT(alignment) \ - ATTR_PLACE_AT_FAST_RAM_INIT ATTR_ALIGN(alignment) - -#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast") -#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \ - ATTR_RAMFUNC ATTR_ALIGN(alignment) - -#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem") - -#define NOP() __asm volatile("nop") -#define WFI() __asm volatile("wfi") - -#endif - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @brief Count bits set to 1 - * - * @param value Data to be counted - * - * @return number of bits set to 1 - */ -static inline uint32_t count_set_bits(uint32_t value) -{ - if (value == 0) { - return 0; - } - return 1 + count_set_bits(value & (value - 1)); -} - -/** - * @brief Count bits set to 1 from least significant bit - * - * @param value Data to be counted - * - * @return number of bits set to 1 - * @return 0xFFFFFFFF if no bit was set to 1 - */ -static inline uint32_t get_first_set_bit_from_lsb(uint32_t value) -{ - uint32_t i = 0; - if (!value) { - return 0xFFFFFFFFUL; - } - while (value && !(value & 0x1)) { - value >>= 1; - i++; - } - return i; -} - -/** - * @brief Count bits set to 1 from most significant bit - * - * @param value Data to be counted - * - * @return number of bits set to 1 - * @return 0xFFFFFFFF if no bit was set to 1 - */ -static inline uint32_t get_first_set_bit_from_msb(uint32_t value) -{ - uint32_t i = 31; - if (!value) { - return 0xFFFFFFFFUL; - } - while (value && !(value & 0x80000000)) { - value <<= 1; - value &= ~1; - i--; - } - return i; -} - -/** - * @brief Convert the elapsed ticks to microseconds according to the source clock frequency - * @param [in] ticks elapsed ticks - * @param [in] src_clk_freq The Frequency of the source - * - * @return elapsed microseconds - */ -static inline uint32_t hpm_convert_ticks_to_us(uint32_t ticks, uint32_t src_clk_freq) -{ - uint32_t ticks_per_us = (src_clk_freq + 1000000UL - 1UL) / 1000000UL; - return (ticks + ticks_per_us - 1UL) / ticks_per_us; -} - -/** - * @brief Convert the elapsed ticks to milliseconds according to the source clock frequency - * @param [in] ticks elapsed ticks - * @param [in] src_clk_freq The Frequency of the source - * - * @return elapsed milliseconds - */ -static inline uint32_t hpm_convert_ticks_to_ms(uint32_t ticks, uint32_t src_clk_freq) -{ - uint32_t ticks_per_ms = (src_clk_freq + 1000UL - 1UL) / 1000UL; - return (ticks + ticks_per_ms - 1UL) / ticks_per_ms; -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* _HPM_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h deleted file mode 100644 index a4d91124f07..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_crc_drv.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_CRC_DRV_H -#define HPM_CRC_DRV_H - -/** - * @brief CRC APIs - * @defgroup crc_interface CRC driver APIs - * @ingroup crc_interfaces - * @{ - */ - - -#include "hpm_common.h" -#include "hpm_crc_regs.h" - -/** - * @brief CRC preset definitions - */ -typedef enum crc_preset_enum { - crc_preset_none = 0, - crc_preset_crc32, /*!< Poly: 0x04C11DB7, Init: 0xFFFFFFFF, Refin: True, Refout: True, Xorout: 0xFFFFFFFF */ - crc_preset_crc32_autosar, /*!< Poly: 0xF4ACFB13, Init: 0xFFFFFFFF, Refin: True, Refout: True, Xorout: 0xFFFFFFFF */ - crc_preset_crc16_ccitt, /*!< Poly: 0x1021, Init: 0x0000, Refin: True, Refout: True, Xorout: 0x0000 */ - crc_preset_crc16_xmodem, /*!< Poly: 0x1021, Init: 0x0000, Refin: False, Refout: False, Xorout: 0x0000 */ - crc_preset_crc16_modbus, /*!< Poly: 0x8005, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0x0000 */ - crc_preset_crc16_dnp, /*!< Poly: 0x3D65, Init: 0x0000, Refin: True, Refout: True, Xorout: 0xFFFF */ - crc_preset_crc16_x25, /*!< Poly: 0x1021, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0xFFFF */ - crc_preset_crc16_usb, /*!< Poly: 0x8005, Init: 0xFFFF, Refin: True, Refout: True, Xorout: 0xFFFF */ - crc_preset_crc16_maxim, /*!< Poly: 0x8005, Init: 0x0000, Refin: True, Refout: True, Xorout: 0xFFFF */ - crc_preset_crc16_ibm, /*!< Poly: 0x8005, Init: 0x0000, Refin: True, Refout: True, Xorout: 0x0000 */ - crc_preset_crc8_maxim, /*!< Poly: 0x31, Init: 0x00, Refin: True, Refout: True, Xorout: 0x00 */ - crc_preset_crc8_rohc, /*!< Poly: 0x07, Init: 0xFF, Refin: True, Refout: True, Xorout: 0x00 */ - crc_preset_crc8_itu, /*!< Poly: 0x07, Init: 0x00, Refin: False, Refout: False, Xorout: 0x55 */ - crc_preset_crc8, /*!< Poly: 0x07, Init: 0x00, Refin: False, Refout: False, Xorout: 0x00 */ - crc_preset_crc5_usb, /*!< Poly: 0x05, Init: 0x1F, Refin: True, Refout: True, Xorout: 0x1F */ -} crc_preset_t; - -/** - * @brief CRC Refin definitions. - */ -typedef enum crc_refin_enum { - crc_refin_false = 0, /*!< Do not manipulate input data stream. */ - crc_refin_true = 1, /*!< Reflect each byte in the input stream bitwise. */ -} crc_refin_t; - -/** - * @brief CRC Refout definitions. - */ -typedef enum crc_refout_enum { - crc_refout_false = 0, /*!< Do not manipulate output data stream. */ - crc_refout_true = 1, /*!< Reflect each byte in the output stream bitwise. */ -} crc_refout_t; - -/** - * @brief crc input data stream byte order definitions. - */ -typedef enum crc_in_byte_order_enum { - crc_in_byte_order_lsb = 0, /*!< Byte order of the CRC DATA LS Byte first. */ - crc_in_byte_order_msb = 1, /*!< Byte order of the CRC DATA MS Byte first. */ -} crc_in_byte_order_t; - -#define CRC_POLY_WIDTH_4 (4U) -#define CRC_POLY_WIDTH_5 (5U) -#define CRC_POLY_WIDTH_6 (6U) -#define CRC_POLY_WIDTH_7 (7U) -#define CRC_POLY_WIDTH_8 (8U) -#define CRC_POLY_WIDTH_16 (16U) -#define CRC_POLY_WIDTH_24 (24U) -#define CRC_POLY_WIDTH_32 (32U) - -/** - * @brief Channel config - */ -typedef struct crc_channel_config { - crc_preset_t preset; /*!< Preset CRC. See "crc_preset_t". */ - uint32_t init; /*!< Initial value for CRC. */ - uint32_t poly; /*!< Poly for CRC. */ - uint32_t poly_width; /*!< CRC poly width. See "CRC_POLY_WIDTH_x". */ - crc_in_byte_order_t in_byte_order; /*!< CRC intput byte order. See "crc_in_byte_order_t". */ - crc_refout_t refout; /*!< CRC reflect output. See "crc_refout_t". */ - crc_refin_t refin; /*!< CRC reflect iutput. See "crc_refin_t". */ - uint32_t xorout; /*!< XOR mask for CRC result (for no mask, should be 0). */ -} crc_channel_config_t; - -#define CRC_REG_WRITE8(addr, data)\ -{\ - uint32_t addr32 = (uint32_t)(addr);\ - (*(volatile uint8_t *)(addr32) = (data));\ -} - -#define CRC_REG_WRITE16(addr, data)\ -{\ - uint32_t addr32 = (uint32_t)(addr);\ - (*(volatile uint16_t *)(addr32) = (data));\ -} - -#define CRC_REG_WRITE32(addr, data)\ -{\ - uint32_t addr32 = (uint32_t)(addr);\ - (*(volatile uint32_t *)(addr32) = (data));\ -} - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get default channel config - * - * @param[in] cfg Channel config - */ -void crc_get_default_channel_config(crc_channel_config_t *cfg); - -/** - * @brief Setup CRC channel - * - * @param[in] ptr CRC base address - * @param[in] ch_index Target channel index to be configured - * @param[in] cfg Channel config - * - * @return status_success if everything is okay - */ -hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, - crc_channel_config_t *cfg); - -/** - * @brief Calculate one byte data crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] data Data that to be calculate - */ -static inline void crc_calc_byte(CRC_Type *ptr, uint32_t ch_index, uint8_t data) -{ - CRC_REG_WRITE8(&ptr->CHN[ch_index].DATA, data); -} - -/** - * @brief Calculate length bytes data block crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] pbuffer Data to be calculate buffer - * @param[in] length Number of pbuffer, unit is byte - */ -void crc_calc_block_bytes(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length); - -/** - * @brief Calculate half-word data crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] data Data that to be calculate - */ -static inline void crc_calc_half_word(CRC_Type *ptr, uint32_t ch_index, uint16_t data) -{ - CRC_REG_WRITE16(&ptr->CHN[ch_index].DATA, data); -} - -/** - * @brief Calculate length half-words data block crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] pbuffer Data to be calculate buffer - * @param[in] length Number of pbuffer, unit is half word(2 bytes) - */ -void crc_calc_block_half_words(CRC_Type *ptr, uint32_t ch_index, uint16_t *pbuffer, uint32_t length); - -/** - * @brief Calculate word data crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] data Data that to be calculate - */ -static inline void crc_calc_word(CRC_Type *ptr, uint32_t ch_index, uint32_t data) -{ - CRC_REG_WRITE32(&ptr->CHN[ch_index].DATA, data); -} - -/** - * @brief Calculate length words data block crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] pbuffer Data to be calculate buffer - * @param[in] length Number of pbuffer, unit is word(4 bytes) - */ -void crc_calc_block_words(CRC_Type *ptr, uint32_t ch_index, uint32_t *pbuffer, uint32_t length); - -/** - * @brief Fast calculate length bytes large data block crc - * - * @param[in] ptr CRC base address - * @param[in] ch_index CRC channel index - * @param[in] pbuffer Data to be calculate buffer - * @param[in] length Number of pbuffer, unit is byte - */ -void crc_calc_large_block_fast(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length); - -/** - * @brief Get CRC result - * - * @param[in] ptr CRC base address - * @param[in] ch_index Index of the channel to be get - * @return CRC result - */ -static inline uint32_t crc_get_result(CRC_Type *ptr, uint32_t ch_index) -{ - return ptr->CHN[ch_index].RESULT; -} -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_CRC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h deleted file mode 100644 index acec7c6d762..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_csr_drv.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CSR_DRV_H -#define HPM_CSR_DRV_H - -#include "hpm_csr_regs.h" -#include "riscv/riscv_core.h" - - -/** - * @brief CSR driver APIs - * @defgroup csr_interface CSR driver APIs - * @ingroup csr_interfaces - * @{ - * - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Enable access to CSR_CYCLE and CSR_MCYCLEH - * @note This Function can be called in Machine mode only - * - */ -static inline void hpm_csr_enable_access_to_csr_cycle(void) -{ - uint32_t mcounter_en = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounter_en | CSR_MCOUNTEREN_CY_MASK); -} - -/** - * @brief Disable access to CSR_CYCLE and CSR_MCYCLEH - * @note This Function can be called in Machine mode only - * - */ -static inline void hpm_csr_disable_access_to_csr_cycle(void) -{ - uint32_t mcounter_en = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounter_en & ~CSR_MCOUNTEREN_CY_MASK); -} - -/** - * @brief Get the core cycle value - * @note The CY bit in MCOUNTEREN must be enabled before using this API whendevice is : - * - in supervisor mode if the device supports M/S/U mode, or - * - in user mode if the device supports M/U mode - * - * @return CSR cycle value in 64-bit - */ -static inline uint64_t hpm_csr_get_core_cycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_CYCLE); - uint32_t resulth = read_csr(CSR_CYCLEH); - uint32_t resultl_second = read_csr(CSR_CYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if CYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_CYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if CYCLE rolled over, need to get the CYCLEH again */ - } - return result; - } - -/** - * @brief Get the core mcycle value - * @note This function can be called in machine mode only - * - * @return CSR mcycle value in 64-bit - */ -static inline uint64_t hpm_csr_get_core_mcycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_MCYCLE); - uint32_t resulth = read_csr(CSR_MCYCLEH); - uint32_t resultl_second = read_csr(CSR_MCYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_MCYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ - } - return result; - } - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_CSR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h deleted file mode 100644 index 7bd26403c2a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dac_drv.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_DAC_DRV_H -#define HPM_DAC_DRV_H - -#include "hpm_common.h" -#include "hpm_dac_regs.h" -#include "hpm_soc_feature.h" - -/* The range of DAC output value setting is from 0.0 to 10000.0, which is mapped to 0 to 100 in percentage. */ -#define DAC_OUTPUT(PERCENT) (PERCENT / 10000.0f * DAC_SOC_MAX_DATA) - -#define DAC_AHB_ERROR_EVENT DAC_IRQ_EN_AHB_ERROR_MASK -#define DAC_FIFO_EMPTY_EVENT DAC_IRQ_EN_FIFO_EMPTY_MASK -#define DAC_BUF1_COMPLETE_EVENT DAC_IRQ_EN_BUF1_CMPT_MASK -#define DAC_BUF0_COMPLETE_EVENT DAC_IRQ_EN_BUF0_CMPT_MASK - - -typedef enum { - dac_mode_direct = 0, - dac_mode_step, - dac_mode_buffer, - dac_mode_trig -} dac_mode_t; - -typedef enum { - dac_ana_div_2 = 0, - dac_ana_div_4, - dac_ana_div_6, - dac_ana_div_8 -} dac_ana_div_t; - -typedef struct { - bool sync_mode; - uint8_t dac_mode; - uint8_t ana_div; -} dac_config_t; - -typedef enum { - dac_step_up = 0, - dac_step_down -} dac_step_direction_t; - -typedef enum { - dac_round_mode_oneshot = 0, - dac_round_mode_loop -} dac_round_mode_t; - -typedef struct { - uint16_t start_point; - uint16_t end_point; - uint8_t round_mode; - uint8_t up_down; - uint8_t step_num; -} dac_step_config_t; - -typedef enum { - dac_data_stru_2_point = 0, - dac_data_stru_1_point -} dac_data_structure_t; - -typedef enum { - dac_burst_single = 0, - dac_burst_incr4 = 3, - dac_burst_incr8 = 5 -} dac_burst_type_t; - -typedef struct { - uint32_t start_addr; - uint8_t stop; - uint16_t len; -} dac_buffer_t; - -typedef struct { - uint8_t buf_data_mode; - uint8_t burst; - dac_buffer_t buf0; - dac_buffer_t buf1; -} dac_buffer_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -void dac_get_default_config(dac_config_t *config); -hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config); -hpm_stat_t dac_set_direct_config(DAC_Type *ptr, uint16_t data); -hpm_stat_t dac_set_step_config(DAC_Type *ptr, uint8_t step_cfg_idx, dac_step_config_t *config); -hpm_stat_t dac_set_buffer_config(DAC_Type *ptr, dac_buffer_config_t *config); -hpm_stat_t dac_set_output_frequency(DAC_Type *ptr, uint32_t dac_input_freq, uint32_t dac_output_freq); -hpm_stat_t dac_set_step_sw_trigger(DAC_Type *ptr, uint8_t step_sw_trig_idx); -void dac_set_buffer_sw_trigger(DAC_Type *ptr); -void dac_set_hw_trigger_enable(DAC_Type *ptr, bool enable); -hpm_stat_t dac_external_dma_request_enable(DAC_Type *ptr, uint8_t buf_idx, bool enable); -void dac_set_buffer_dma_reset(DAC_Type *ptr); -void dac_enable_conversion(DAC_Type *ptr, bool enable); -void dac_enable_interrupts(DAC_Type *ptr, uint32_t mask); -uint32_t dac_get_status_flags(DAC_Type *ptr); -void dac_set_status_flags(DAC_Type *ptr, uint32_t mask); -uint8_t dac_get_current_buffer_index(DAC_Type *ptr); -uint16_t dac_get_current_buffer_offset(DAC_Type *ptr); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h deleted file mode 100644 index bd58a1ca452..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAO_DRV_H -#define HPM_DAO_DRV_H - -#include "hpm_common.h" -#include "hpm_dao_regs.h" -#include "hpm_i2s_common.h" -#include "hpm_soc_feature.h" - -/** - * @brief DAO driver APIs - * @defgroup dao_interface DAO driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief DAO channel selection - */ -#define DAO_CHANNEL_LEFT_ONLY DAO_CTRL_LEFT_EN_MASK -#define DAO_CHANNEL_RIGHT_ONLY DAO_CTRL_RIGHT_EN_MASK -#define DAO_CHANNEL_BOTH \ - (DAO_CTRL_RIGHT_EN_MASK | DAO_CTRL_LEFT_EN_MASK) - -/** - * @brief DAO default output - */ -#define DAO_DEFAULT_OUTPUT_ALL_LOW (0U) -#define DAO_DEFAULT_OUTPUT_ALL_HIGH (1U) -#define DAO_DEFAULT_OUTPUT_P_HIGH_N_LOW (2U) -#define DAO_DEFAULT_OUTPUT_DISABLED (3U) - -/** - * @brief DAO config - */ -typedef struct dao_config { - bool enable_mono_output; - uint8_t default_output_level; - uint8_t channel_count; -#if defined(HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG) && (HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG == 1) - bool enable_tdm_mode; - bool frame_start_at_rising_edge; - uint8_t protocol; - uint8_t channel_length; - uint8_t audio_depth; -#endif - uint8_t channel_slot_mask; -} dao_config_t; - -typedef enum { - dao_right_channel = DAO_CTRL_RIGHT_EN_MASK, - dao_left_channel = DAO_CTRL_LEFT_EN_MASK, -} dao_channel_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief config high pass filter - * - * @param [in] ptr DAO base address - * @param [in] hpf_coef_ma high pass filter a coefficient's complement - * @param [in] hpf_coef_b high pass filter b coefficient - * @param [in] enable - * @arg true: enable - * @arg false: disable - */ -static inline void dao_config_hpf(DAO_Type *ptr, - uint32_t hpf_coef_ma, - uint32_t hpf_coef_b, - bool enable) -{ - ptr->HPF_MA = DAO_HPF_MA_COEF_SET(hpf_coef_ma); - ptr->HPF_B = DAO_HPF_B_COEF_SET(hpf_coef_b); - ptr->CTRL = (ptr->CTRL & ~DAO_CTRL_HPF_EN_MASK) - | (enable ? DAO_CTRL_HPF_EN_MASK : 0); -} - -/** - * @brief enable high pass filter - * - * @param [in] ptr DAO base address - */ -static inline void dao_enable_hpf(DAO_Type *ptr) -{ - ptr->CTRL |= DAO_CTRL_HPF_EN_MASK; -} - -/** - * @brief disable high pass filter - * - * @param [in] ptr DAO base address - */ -static inline void dao_disable_hpf(DAO_Type *ptr) -{ - ptr->CTRL &= ~DAO_CTRL_HPF_EN_MASK; -} - -/** - * @brief enable channel - * - * @param [in] ptr DAO base address - * @param [in] ch channel defined in dao_channel_t - */ -static inline void dao_enable_channel(DAO_Type *ptr, uint32_t ch) -{ - ptr->CTRL |= ch; -} - -/** - * @brief disable channel - * - * @param [in] ptr DAO base address - * @param [in] ch channel defined in dao_channel_t - */ -static inline void dao_disable_channel(DAO_Type *ptr, uint32_t ch) -{ - ptr->CTRL &= ~ch; -} - -/** - * @brief enable mono output - * - * @param [in] ptr DAO base address - */ -static inline void dao_enable_mono_output(DAO_Type *ptr) -{ - ptr->CTRL |= DAO_CTRL_MONO_MASK; -} - -/** - * @brief disable mono output - * - * @param [in] ptr DAO base address - */ -static inline void dao_disable_mono_output(DAO_Type *ptr) -{ - ptr->CTRL &= ~DAO_CTRL_MONO_MASK; -} - -/** - * @brief enable remap - * - * @param [in] ptr DAO base address - */ -static inline void dao_enable_remap(DAO_Type *ptr) -{ - ptr->CTRL |= DAO_CTRL_REMAP_MASK; -} - -/** - * @brief disable remap - * - * @param [in] ptr DAO base address - */ -static inline void dao_disable_remap(DAO_Type *ptr) -{ - ptr->CTRL &= ~DAO_CTRL_REMAP_MASK; -} - -/** - * @brief invert output - * - * @param [in] ptr DAO base address - * @param [in] invert - * @arg true: invert output - * @arg false: not invert output - */ -static inline void dao_invert_output(DAO_Type *ptr, bool invert) -{ - ptr->CTRL = (ptr->CTRL & DAO_CTRL_INVERT_MASK) - | DAO_CTRL_INVERT_SET(invert); -} - -/** - * @brief force pads output with certain level - * - * @param [in] ptr DAO base address - * @param [in] output output level - */ -static inline void dao_force_output(DAO_Type *ptr, uint8_t output) -{ - ptr->CTRL = (ptr->CTRL & DAO_CTRL_FALSE_LEVEL_MASK) - | DAO_CTRL_FALSE_LEVEL_SET(output); -} - -/** - * @brief enable false run - * when false run mode is enabled, the module continues to consume data, no actual output on pads. - * @param [in] ptr DAO base address - * @param [in] enable - * @arg true: enable - * @arg false: disable - */ -static inline void dao_enable_false_run(DAO_Type *ptr, bool enable) -{ - ptr->CTRL = (ptr->CTRL & DAO_CTRL_FALSE_RUN_MASK) - | DAO_CTRL_FALSE_RUN_SET(enable); -} - -/** - * @brief software reset - * - * @param [in] ptr DAO base address - */ -static inline void dao_software_reset(DAO_Type *ptr) -{ - ptr->CMD |= DAO_CMD_SFTRST_MASK; - ptr->CMD &= ~DAO_CMD_SFTRST_MASK; -} - -/** - * @brief check whether DAO is running - * - * @param [in] ptr DAO base address - * @retval true if dao is running - */ -static inline bool dao_is_running(DAO_Type *ptr) -{ - return ptr->CMD & DAO_CMD_RUN_MASK; -} - -/** - * @brief start - * - * @param [in] ptr DAO base address - */ -static inline void dao_start(DAO_Type *ptr) -{ - ptr->CMD |= DAO_CMD_RUN_MASK; -} - -/** - * @brief stop - * - * @param [in] ptr DAO base address - */ -static inline void dao_stop(DAO_Type *ptr) -{ - ptr->CMD &= ~DAO_CMD_RUN_MASK; -} - -/** - * @brief initlization - * - * @param [in] ptr DAO base address - * @param [in] config dao_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t dao_init(DAO_Type *ptr, dao_config_t *config); - -/** - * @brief get default config - * - * @param [in] ptr DAO base address - * @param [out] config dao_config_t - */ -void dao_get_default_config(DAO_Type *ptr, dao_config_t *config); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_DAO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h deleted file mode 100644 index 0e576e25c6b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_display_common.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DISPLAY_COMMON_H -#define HPM_DISPLAY_COMMON_H - -#include "hpm_common.h" - -/** - * @brief Display_common driver APIs - * @defgroup Display_common_interface Display_common driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief display alphablend mode - */ -typedef enum display_alphablend_mode { - display_alphablend_mode_clear = 0, - display_alphablend_mode_src = 1, - display_alphablend_mode_dst = 2, - display_alphablend_mode_src_over = 3, - display_alphablend_mode_dst_over = 4, - display_alphablend_mode_src_in = 5, - display_alphablend_mode_dst_in = 6, - display_alphablend_mode_src_out = 7, - display_alphablend_mode_dst_out = 8, - display_alphablend_mode_src_at_top = 9, - display_alphablend_mode_dst_at_top = 10, - display_alphablend_mode_xor = 11, - display_alphablend_mode_plus = 12, - display_alphablend_mode_modulate = 13, - display_alphablend_mode_src_org = 14, - display_alphablend_mode_dst_org = 15, -} display_alphablend_mode_t; - -/** - * @brief display pixel format - */ -typedef enum display_pixel_format { - display_pixel_format_argb8888, - display_pixel_format_rgb565, - display_pixel_format_rgb555, - display_pixel_format_rgb444, - display_pixel_format_gbr422, - display_pixel_format_yuv422, - display_pixel_format_ycbcr422, - display_pixel_format_y8, - display_pixel_format_raw8, -} display_pixel_format_t; - -/** - * @brief display data byte order - */ -typedef enum display_byteorder { - display_byteorder_a3a2a1a0 = 0, - display_byteorder_a2a3a0a1 = 1, - display_byteorder_a1a0a3a2 = 2, - display_byteorder_a0a1a2a3 = 3, -} display_byteorder_t; - -/** - * @brief display yuv format - */ -typedef enum display_yuv_format { - display_yuv_mode_422_u1y1v1y2 = 0, - display_yuv_mode_422_v1y1u1y2, - display_yuv_mode_422_y1u1y2v1, - display_yuv_mode_422_y1v1y2u1, -} display_yuv_format_t; - -/** - * @brief display data 32 bits argb - */ -typedef union display_color_32b { - uint32_t u; - struct { - uint8_t b; - uint8_t g; - uint8_t r; - uint8_t alpha; - }; -} display_color_32b_t; - -/** - * @brief display data alpha value usage option - */ -typedef enum display_alpha_op { - display_alpha_op_invalid = 0, - display_alpha_op_override = 1, - display_alpha_op_scale = 2, -} display_alpha_op_t; - -/** - * @brief display data alphablend option - */ -typedef struct dispaly_alphablend_option { - uint8_t dst_alpha; - uint8_t src_alpha; - display_alpha_op_t dst_alpha_op; - display_alpha_op_t src_alpha_op; - display_alphablend_mode_t mode; -} display_alphablend_option_t; - -/** - * @brief display yuv to rgb format conversion coefficient - */ -typedef struct dispaly_yuv2rgb_coef { - uint16_t c0; - uint16_t c1; - uint16_t c2; - uint16_t c3; - uint16_t c4; - uint16_t uv_offset; - uint16_t y_offset; -} display_yuv2rgb_coef_t; - -/** - * @brief display yuv to rgb format conversion config - */ -typedef struct display_yuv2rgb_config { - bool enable; - bool ycbcr_mode; - display_yuv2rgb_coef_t yuv2rgb_coef; -} display_yuv2rgb_config_t; - -/** - * @brief display rgb to yuv format conversion config - */ -typedef struct display_rgb2yuv_config { - bool enable; - bool ycbcr_mode; - uint16_t c0; - uint16_t c1; - uint16_t c2; - uint16_t c3; - uint16_t c4; - uint16_t c5; - uint16_t c6; - uint16_t c7; - uint16_t c8; - uint16_t uv_offset; - uint16_t y_offset; -} display_rgb2yuv_config_t; - -typedef enum display_buf_format { - display_buf_format_argb8888, /*!< memory layout in byte(low->high): b0[7:0], g0[7:0], r0[7:0], a0[7:0], b1[7:1], g1[7:1], r1[7:0], a1[7:0], ... */ - display_buf_format_bgra8888, /*!< memory layout in byte(low->high): a0[7:0], r0[7:0], g0[7:0], b0[7:0], a1[7:1], r1[7:1], g1[7:0], b1[7:0], ... */ - display_buf_format_rgb565, /*!< memory layout in byte(low->high): g0[2:0]:b0[4:0], r0[4:0]:g0[5:3], g1[2:0]:b1[4:0], r1[4:0]:g1[5:3], ... */ - display_buf_format_rgb565_swap, /*!< memory layout in byte(low->high): r0[4:0]:g0[5:3], g0[2:0]:b0[4:0], r2[4:0]:g2[5:3], g1[2:0]:b1[4:0], ... */ - display_buf_format_yuyv, /*!< memory layout in byte(low->high): y0, u0, y1, v0, y2, u2, y3, v2, ... */ - display_buf_format_uyvy, /*!< memory layout in byte(low->high): u0, y0, v0, y1, u2, y2, v2, y3, ... */ - display_buf_format_y8, /*!< memory layout in byte(low->high): y0, y1, y2, y3, y4, y5, ... */ - display_buf_format_max, -} display_buf_format_t; - -typedef struct display_buf { - void *buf; /*!< point pixel memory */ - uint16_t width; /*!< width in pixel */ - uint16_t height; /*!< height in pixel */ - uint32_t stride; /*!< stride each line, in byte */ - display_buf_format_t format; - struct { - display_alpha_op_t op; - uint8_t val; - } alpha; -} display_buf_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Display get pixel size in bit - * - * @param [in] format display_pixel_format_t - * - * @retval pixel size in bit - */ -static inline - uint8_t display_get_pixel_size_in_bit(display_pixel_format_t format) -{ - switch (format) { - case display_pixel_format_argb8888: - return 32; - case display_pixel_format_rgb565: - return 16; - case display_pixel_format_yuv422: - return 16; - case display_pixel_format_ycbcr422: - return 16; - case display_pixel_format_y8: - return 8; - case display_pixel_format_raw8: - return 8; - default: - return 0; - } -} - -/** - * @brief Check whether the pixel data is yuv format - * - * @param [in] format display_pixel_format_t - * - * @retval bool: true or false - */ -static inline bool display_pixel_format_is_yuv_format(display_pixel_format_t format) -{ - switch (format) { - case display_pixel_format_yuv422: - return true; - case display_pixel_format_ycbcr422: - return true; - default: - return false; - } -} - -/** - * @brief Display get pixel size in byte - * - * @param [in] format display_pixel_format_t - * - * @retval pixel size in byte - */ -static inline - uint8_t display_get_pixel_size_in_byte(display_pixel_format_t format) -{ - return display_get_pixel_size_in_bit(format) >> 3; -} - -/** - * @brief Display get pitch length in byte - * - * @param [in] format display_pixel_format_t - * @param [in] width_in_pixel pixel width - * - * @retval pitch length in byte - */ -static inline - uint32_t display_get_pitch_length_in_byte(display_pixel_format_t format, - uint32_t width_in_pixel) -{ - return width_in_pixel * (display_get_pixel_size_in_bit(format) >> 3); -} - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif -#endif /* HPM_DISPLAY_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h deleted file mode 100644 index 7e7770eb59e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAV1_DRV_H -#define HPM_DMAV1_DRV_H -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_dma_regs.h" - -/** - * - * @brief DMA driver APIs - * @defgroup dma_interface DMA driver APIs - * @ingroup io_interfaces - * @{ - */ - -#define DMA_CHANNEL_PRIORITY_LOW (0U) -#define DMA_CHANNEL_PRIORITY_HIGH (1U) - -#define DMA_NUM_TRANSFER_PER_BURST_1T (0U) -#define DMA_NUM_TRANSFER_PER_BURST_2T (1U) -#define DMA_NUM_TRANSFER_PER_BURST_4T (2U) -#define DMA_NUM_TRANSFER_PER_BURST_8T (3U) -#define DMA_NUM_TRANSFER_PER_BURST_16T (4U) -#define DMA_NUM_TRANSFER_PER_BURST_32T (5U) -#define DMA_NUM_TRANSFER_PER_BURST_64T (6U) -#define DMA_NUM_TRANSFER_PER_BURST_128T (7U) -#define DMA_NUM_TRANSFER_PER_BURST_256T (8U) -#define DMA_NUM_TRANSFER_PER_BURST_512T (9U) -#define DMA_NUM_TRANSFER_PER_BURST_1024T (10U) - -#define DMA_TRANSFER_WIDTH_BYTE (0U) -#define DMA_TRANSFER_WIDTH_HALF_WORD (1U) -#define DMA_TRANSFER_WIDTH_WORD (2U) -#define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) - -#define DMA_ALIGN_HALF_WORD(x) (x & ~(1u)) -#define DMA_ALIGN_WORD(x) (x & ~(3u)) -#define DMA_ALIGN_DOUBLE_WORD(x) (x & ~(7u)) - -#define DMA_STATUS_ERROR_SHIFT (0U) -#define DMA_STATUS_ABORT_SHIFT (8U) -#define DMA_STATUS_TC_SHIFT (16U) - -#define DMA_CHANNEL_STATUS_ONGOING (1U) -#define DMA_CHANNEL_STATUS_ERROR (2U) -#define DMA_CHANNEL_STATUS_ABORT (4U) -#define DMA_CHANNEL_STATUS_TC (8U) - -#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x)) -#define DMA_CHANNEL_IRQ_STATUS(x) (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \ - DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \ - DMA_CHANNEL_IRQ_STATUS_ERROR(x)) - -#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_TC(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_TC_SHIFT)) -#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ABORT(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ABORT_SHIFT)) -#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ERROR(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ERROR_SHIFT)) - -#define DMA_HANDSHAKE_MODE_NORMAL (0U) -#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) - -#define DMA_ADDRESS_CONTROL_INCREMENT (0U) -#define DMA_ADDRESS_CONTROL_DECREMENT (1U) -#define DMA_ADDRESS_CONTROL_FIXED (2U) - -#define DMA_INTERRUPT_MASK_NONE (0U) -#define DMA_INTERRUPT_MASK_ERROR DMA_CHCTRL_CTRL_INTERRMASK_MASK -#define DMA_INTERRUPT_MASK_ABORT DMA_CHCTRL_CTRL_INTABTMASK_MASK -#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMA_CHCTRL_CTRL_INTTCMASK_MASK -#define DMA_INTERRUPT_MASK_ALL \ - (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \ - | DMA_INTERRUPT_MASK_ABORT \ - | DMA_INTERRUPT_MASK_ERROR) - -#ifndef DMA_SUPPORT_64BIT_ADDR -#define DMA_SUPPORT_64BIT_ADDR (0) -#endif - -/** - * @brief Linked descriptor - * - * It is consumed by DMA controlled directly - */ -typedef struct dma_linked_descriptor { - uint32_t ctrl; /**< Control */ - uint32_t trans_size; /**< Transfer size in source width */ - uint32_t src_addr; /**< Source address */ - uint32_t src_addr_high; /**< Source address high 32-bit, only valid when bus width > 32bits */ - uint32_t dst_addr; /**< Destination address */ - uint32_t dst_addr_high; /**< Destination address high 32-bit, only valid when bus width > 32bits */ - uint32_t linked_ptr; /**< Linked descriptor address */ - uint32_t linked_ptr_high; /**< Linked descriptor address high 32-bit, , only valid when bus width > 32bits */ -} dma_linked_descriptor_t; - -/* @brief Channel config */ -typedef struct dma_channel_config { - uint8_t priority; /**< Channel priority */ - uint8_t src_burst_size; /**< Source burst size */ - uint8_t src_mode; /**< Source work mode */ - uint8_t dst_mode; /**< Destination work mode */ - uint8_t src_width; /**< Source width */ - uint8_t dst_width; /**< Destination width */ - uint8_t src_addr_ctrl; /**< Source address control */ - uint8_t dst_addr_ctrl; /**< Destination address control */ - uint16_t interrupt_mask; /**< Interrupt mask */ - uint32_t src_addr; /**< Source address */ - uint32_t dst_addr; /**< Destination address */ - uint32_t linked_ptr; /**< Next linked descriptor */ - uint32_t size_in_byte; /**< Total size to be transferred in byte */ -#if DMA_SUPPORT_64BIT_ADDR - uint32_t src_addr_high; /**< Source address high 32bits */ - uint32_t dst_addr_high; /**< Destination address high 32bits */ - uint32_t linked_ptr_high; /**< Linked descriptor high 32bits */ -#endif -} dma_channel_config_t; - - -/* @brief Channel config */ -typedef struct dma_handshake_config { - uint32_t dst; - uint32_t src; - uint32_t size_in_byte; - uint8_t data_width; /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */ - uint8_t ch_index; - bool dst_fixed; - bool src_fixed; -} dma_handshake_config_t; - - -/* @brief DMA specific status */ -enum { - status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0), - status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1), - status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2), - status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3), - status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4), -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Reset DMA - * - * @param[in] ptr DMA base address - */ -static inline void dma_reset(DMA_Type *ptr) -{ - ptr->DMACTRL |= DMA_DMACTRL_RESET_MASK; -} - -/** - * @brief Enable DMA channel - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel to be enabled - * - * @return status_success if everything's okay - */ -static inline hpm_stat_t dma_enable_channel(DMA_Type *ptr, uint32_t ch_index) -{ - ptr->CHCTRL[ch_index].CTRL |= DMA_CHCTRL_CTRL_ENABLE_MASK; - - if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) { - return status_fail; - } - return status_success; -} - -/** - * @brief Disable DMA channel - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel to be disabled - * - */ -static inline void dma_disable_channel(DMA_Type *ptr, uint32_t ch_index) -{ - ptr->CHCTRL[ch_index].CTRL &= ~DMA_CHCTRL_CTRL_ENABLE_MASK; -} - -/** - * @brief Check whether DMA channel is enable - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * - * @return true if DMA channel is enable - * - */ -static inline bool dma_channel_is_enable(DMA_Type *ptr, uint32_t ch_index) -{ - return (ptr->CHCTRL[ch_index].CTRL & DMA_CHCTRL_CTRL_ENABLE_MASK) ? true : false; -} - -/** - * @brief Set DMA channel priority - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] priority dma priority - * @arg @ref DMA_CHANNEL_PRIORITY_LOW - * @arg @ref DMA_CHANNEL_PRIORITY_HIGH - * - */ -static inline void dma_set_priority(DMA_Type *ptr, uint32_t ch_index, uint8_t priority) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_PRIORITY_MASK) | DMA_CHCTRL_CTRL_PRIORITY_SET(priority); -} - -/** - * @brief Set DMA channel source work mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] mode source work mode - * @arg @ref DMA_HANDSHAKE_MODE_NORMAL - * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE - * - */ -static inline void dma_set_source_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCMODE_MASK) | DMA_CHCTRL_CTRL_SRCMODE_SET(mode); -} - -/** - * @brief Set DMA channel destination work mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] mode destination work mode - * @arg @ref DMA_HANDSHAKE_MODE_NORMAL - * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE - * - */ -static inline void dma_set_destination_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTMODE_MASK) | DMA_CHCTRL_CTRL_DSTMODE_SET(mode); -} - -/** - * @brief Set DMA channel source burst size - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] burstsize source burst size - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_2T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_4T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_8T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_16T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_32T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_64T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_128T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_256T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_512T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1024T - * - */ -static inline void dma_set_source_burst_size(DMA_Type *ptr, uint32_t ch_index, uint8_t burstsize) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize); -} - -/** - * @brief Get DMA channel remaining transfer size - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * - * @return remaining transfer size - * - */ -static inline uint32_t dma_get_remaining_transfer_size(DMA_Type *ptr, uint32_t ch_index) -{ - return ptr->CHCTRL[ch_index].TRANSIZE; -} - -/** - * @brief Set DMA channel transfer size - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] size_in_width transfer size of the channel. The width is current dma channel configured source width. - * Transfer total bytes are (size_in_width * source width). - * - */ -static inline void dma_set_transfer_size(DMA_Type *ptr, uint32_t ch_index, uint32_t size_in_width) -{ - ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); -} - -/** - * @brief Set DMA channel source width - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] width transfer source width of the channel - * @arg @ref DMA_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_TRANSFER_WIDTH_WORD - * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD - */ -static inline void dma_set_source_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(width); -} - -/** - * @brief Set DMA channel destination width - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] width transfer destination width of the channel - * @arg @ref DMA_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_TRANSFER_WIDTH_WORD - * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD - */ -static inline void dma_set_destination_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTWIDTH_MASK) | DMA_CHCTRL_CTRL_DSTWIDTH_SET(width); -} - -/** - * @brief Set DMA channel transfer width and size in byte - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] src_width transfer source width of the channel - * @arg @ref DMA_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_TRANSFER_WIDTH_WORD - * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD - * @param[in] size_in_byte transfer size in byte of the channel. The dma transfer size is (size_in_byte >> src_width). - * - */ -static inline void dma_set_transfer_src_width_byte_size(DMA_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte) -{ - assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD) - || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD)); - - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(src_width); - ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width); -} - -/** - * @brief Set DMA channel source address - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr source address - * - */ -static inline void dma_set_source_address(DMA_Type *ptr, uint32_t ch_index, uint32_t addr) -{ - ptr->CHCTRL[ch_index].SRCADDR = addr; -} - -/** - * @brief Set DMA channel destination address - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr destination address - * - */ -static inline void dma_set_destination_address(DMA_Type *ptr, uint32_t ch_index, uint32_t addr) -{ - ptr->CHCTRL[ch_index].DSTADDR = addr; -} - -/** - * @brief Set DMA channel source address control mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr_ctrl source address control mode - * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT - * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT - * @arg @ref DMA_ADDRESS_CONTROL_FIXED - * - */ -static inline void dma_set_source_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl); -} - -/** - * @brief Set DMA channel destination address control mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr_ctrl destination address control mode - * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT - * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT - * @arg @ref DMA_ADDRESS_CONTROL_FIXED - * - */ -static inline void dma_set_destination_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl); -} - -/** - * @brief Abort channel transfer with mask - * - * @param[in] ptr DMA base address - * @param[in] ch_index_mask Mask of channels to be aborted - */ -static inline void dma_abort_channel(DMA_Type *ptr, uint32_t ch_index_mask) -{ - ptr->CHABORT |= DMA_CHABORT_CHABORT_SET(ch_index_mask); -} - -/** - * @brief Check if channels are enabled with mask - * - * @param[in] ptr DMA base address - * @param[in] ch_index_mask Mask of channels to be checked - * - * @return Enabled channel mask - */ -static inline uint32_t dma_check_enabled_channel(DMA_Type *ptr, - uint32_t ch_index_mask) -{ - return (ch_index_mask & ptr->CHEN); -} - -/** - * @brief Check if linked pointer has been configured - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be checked - * - * @return true if linked pointer has been configured - */ -static inline bool dma_has_linked_pointer_configured(DMA_Type *ptr, uint32_t ch_index) -{ - return ptr->CHCTRL[ch_index].LLPOINTER != 0; -} - -/** - * @brief Check transfer status - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be checked - * - * @retval DMA_CHANNEL_STATUS_ONGOING if transfer is still ongoing - * @retval DMA_CHANNEL_STATUS_ERROR if any error occurred during transferring - * @retval DMA_CHANNEL_STATUS_ABORT if transfer is aborted - * @retval DMA_CHANNEL_STATUS_TC if transfer is finished without error - */ -static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index) -{ - volatile uint32_t tmp = ptr->INTSTATUS; - volatile uint32_t tmp_channel; - uint32_t dma_status; - - dma_status = 0; - tmp_channel = tmp & (1 << (DMA_STATUS_TC_SHIFT + ch_index)); - if (tmp_channel) { - dma_status |= DMA_CHANNEL_STATUS_TC; - ptr->INTSTATUS = tmp_channel; - } - tmp_channel = tmp & (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)); - if (tmp_channel) { - dma_status |= DMA_CHANNEL_STATUS_ERROR; - ptr->INTSTATUS = tmp_channel; - } - tmp_channel = tmp & (1 << (DMA_STATUS_ABORT_SHIFT + ch_index)); - if (tmp_channel) { - dma_status |= DMA_CHANNEL_STATUS_ABORT; - ptr->INTSTATUS = tmp_channel; - } - if (dma_status == 0) { - dma_status = DMA_CHANNEL_STATUS_ONGOING; - } - return dma_status; -} - -/** - * @brief Clear transfer status - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index - * - */ -static inline void dma_clear_transfer_status(DMA_Type *ptr, uint8_t ch_index) -{ - ptr->INTSTATUS = ((1 << (DMA_STATUS_TC_SHIFT + ch_index)) | (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)) | (1 << (DMA_STATUS_ABORT_SHIFT + ch_index))); -} - -/** - * @brief Enable DMA Channel interrupt - * - * @param [in] ptr DMA base address - * @param [in] ch_index Target channel index - * @param [in] interrupt_mask Interrupt mask - */ -static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) -{ - ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL); -} - -/** - * @brief Disable DMA Channel interrupt - * - * @param [in] ptr DMA base address - * @param [in] ch_index Target channel index - * @param [in] interrupt_mask Interrupt mask - */ -static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) -{ - ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL); -} - - -/** - * @brief Check Channel interrupt master - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be checked - * @return uint32_t Interrupt mask - */ -static inline uint32_t dma_check_channel_interrupt_mask(DMA_Type *ptr, uint8_t ch_index) -{ - return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL; -} - -/** - * @brief Get clear IRQ status - * - * @param[in] ptr DMA base address - * @param[in] mask irq mask to be cleared - */ -static inline void dma_clear_irq_status(DMA_Type *ptr, uint32_t mask) -{ - ptr->INTSTATUS = mask; /* Write-1-Clear */ -} - -/** - * @brief Get IRQ status - * - * @param[in] ptr DMA base address - */ -static inline uint32_t dma_get_irq_status(DMA_Type *ptr) -{ - return ptr->INTSTATUS; -} - -/** - * @brief Get default channel config - * - * @param[in] ptr DMA base address - * @param[in] ch Channel config - */ -void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch); - -/** - * @brief Setup DMA channel - * - * @param[in] ptr DMA base address - * @param[in] ch_num Target channel index to be configured - * @param[in] ch Channel config - * @param[in] start_transfer Set true to start transfer - * - * @return status_success if everything is okay - */ -hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num, - dma_channel_config_t *ch, bool start_transfer); - -/** - * @brief Config linked descriptor function - * - * @param[in] ptr DMA base address - * @param[in] descriptor Linked descriptor pointer - * @param[in] ch_num Target channel index to be configured - * @param[in] config Descriptor config pointer - * - * @return status_success if everything is okay - */ -hpm_stat_t dma_config_linked_descriptor(DMA_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config); - -/** - * @brief Start DMA copy - * - * @param[in] ptr DMA base address - * @param[in] ch_num Target channel index - * @param[in] dst Destination address - * @param[in] src Source Address - * @param[in] size_in_byte Size in byte - * @param[in] burst_len_in_byte Burst length in byte - * - * @return status_success if everthing is okay - * @note: dst, src, size should be aligned with burst_len_in_byte - */ -hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, - uint32_t dst, uint32_t src, - uint32_t size_in_byte, uint32_t burst_len_in_byte); - -/** - * @brief Get default handshake config - * - * @param[in] ptr DMA base address - * @param[in] config default config - */ -void dma_default_handshake_config(DMA_Type *ptr, dma_handshake_config_t *config); - -/** - * @brief config dma handshake function - * - * @param[in] ptr DMA base address - * @param[in] pconfig dma handshake config pointer - * @param[in] start_transfer Set true to start transfer - * - * @return status_success if everything is okay - */ -hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer); - - -#if defined(DMA_SOC_HAS_IDLE_FLAG) && (DMA_SOC_HAS_IDLE_FLAG == 1) -/** - * @brief Check whether DMA is idle - * @param [in] ptr DMA base address - * @return true DMA is idle - * @return false DMA is busy - */ -static inline bool dma_is_idle(DMA_Type *ptr) -{ - return ((ptr->IDMISC & DMA_IDMISC_IDLE_FLAG_MASK) != 0U); -} -#endif - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_DMAV1_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h deleted file mode 100644 index a4e350e2b10..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmamux_drv.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_DMAMUX_DRV_H -#define HPM_DMAMUX_DRV_H -#include "hpm_common.h" -#include "hpm_dmamux_regs.h" - -/** - * - * @brief DMAMUX driver APIs - * @defgroup dmamux_interface DMAMUX driver APIs - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - - -#if !defined(DMAMUX_SOC_WRITEONLY) || !DMAMUX_SOC_WRITEONLY - -/** - * @brief Enable dmamux channel - * - * @param ptr DMAMUX base address - * @param ch_index channel to be enabled - */ -static inline void dmamux_enable_channel(DMAMUX_Type *ptr, uint8_t ch_index) -{ - ptr->MUXCFG[ch_index] |= DMAMUX_MUXCFG_ENABLE_MASK; -} - -/** - * @brief Disable dmamux channel - * - * @param ptr DMAMUX base address - * @param ch_index channel to be disabled - */ -static inline void dmamux_disable_channel(DMAMUX_Type *ptr, uint8_t ch_index) -{ - ptr->MUXCFG[ch_index] &= ~DMAMUX_MUXCFG_ENABLE_MASK; -} - -#endif - -/** - * @brief Config DMAMUX - * - * @param[in] ptr DMAMUX base address - * @param[in] ch_index channel to be configured - * @param[in] src DMAMUX source - * @param[in] enable Set true to enable the channel - */ -static inline void dmamux_config(DMAMUX_Type *ptr, uint8_t ch_index, uint8_t src, bool enable) -{ - ptr->MUXCFG[ch_index] = DMAMUX_MUXCFG_SOURCE_SET(src) - | DMAMUX_MUXCFG_ENABLE_SET(enable); -} - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_DMAMUX_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h deleted file mode 100644 index d1e279b6555..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h +++ /dev/null @@ -1,759 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAV2_DRV_H -#define HPM_DMAV2_DRV_H -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_dmav2_regs.h" - -/** - * - * @brief DMA driver APIs - * @defgroup dma_interface DMA driver APIs - * @ingroup io_interfaces - * @{ - */ - -#define DMA_Type DMAV2_Type - -#define DMA_CHANNEL_PRIORITY_LOW (0U) -#define DMA_CHANNEL_PRIORITY_HIGH (1U) - -#define DMA_NUM_TRANSFER_PER_BURST_1T (0U) -#define DMA_NUM_TRANSFER_PER_BURST_2T (1U) -#define DMA_NUM_TRANSFER_PER_BURST_4T (2U) -#define DMA_NUM_TRANSFER_PER_BURST_8T (3U) -#define DMA_NUM_TRANSFER_PER_BURST_16T (4U) -#define DMA_NUM_TRANSFER_PER_BURST_32T (5U) -#define DMA_NUM_TRANSFER_PER_BURST_64T (6U) -#define DMA_NUM_TRANSFER_PER_BURST_128T (7U) -#define DMA_NUM_TRANSFER_PER_BURST_256T (8U) -#define DMA_NUM_TRANSFER_PER_BURST_512T (9U) -#define DMA_NUM_TRANSFER_PER_BURST_1024T (10U) - -#define DMA_TRANSFER_WIDTH_BYTE (0U) -#define DMA_TRANSFER_WIDTH_HALF_WORD (1U) -#define DMA_TRANSFER_WIDTH_WORD (2U) -#define DMA_TRANSFER_WIDTH_DOUBLE_WORD (3U) - -#define DMA_ALIGN_HALF_WORD(x) (x & ~(1u)) -#define DMA_ALIGN_WORD(x) (x & ~(3u)) -#define DMA_ALIGN_DOUBLE_WORD(x) (x & ~(7u)) - -#define DMA_CHANNEL_STATUS_ONGOING (1U) -#define DMA_CHANNEL_STATUS_ERROR (2U) -#define DMA_CHANNEL_STATUS_ABORT (4U) -#define DMA_CHANNEL_STATUS_TC (8U) -#define DMA_CHANNEL_STATUS_HALF_TC (16U) - -#define DMA_CHANNEL_IRQ_STATUS_ERROR(x) (uint32_t)(1 << x) -#define DMA_CHANNEL_IRQ_STATUS_ABORT(x) (uint32_t)(1 << x) -#define DMA_CHANNEL_IRQ_STATUS_TC(x) (uint32_t)(1 << x) -#define DMA_CHANNEL_IRQ_STATUS_HALF_TC(x) (uint32_t)(1 << x) - -#define DMA_HANDSHAKE_MODE_NORMAL (0U) -#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U) - -#define DMA_ADDRESS_CONTROL_INCREMENT (0U) -#define DMA_ADDRESS_CONTROL_DECREMENT (1U) -#define DMA_ADDRESS_CONTROL_FIXED (2U) - -#define DMA_SRC_BURST_OPT_STANDAND_SIZE (0U) -#define DMA_SRC_BURST_OPT_CUSTOM_SIZE (1U) - -#define DMA_HANDSHAKE_OPT_ONE_BURST (0U) -#define DMA_HANDSHAKE_OPT_ALL_TRANSIZE (1U) - -#define DMA_SWAP_MODE_TABLE (0U) -#define DMA_SWAP_MODE_BYTE (1U) -#define DMA_SWAP_MODE_HALF_WORD (2U) -#define DMA_SWAP_MODE_WORD (3U) - -#define DMA_INTERRUPT_MASK_NONE (0U) -#define DMA_INTERRUPT_MASK_ERROR DMAV2_CHCTRL_CTRL_INTERRMASK_MASK -#define DMA_INTERRUPT_MASK_ABORT DMAV2_CHCTRL_CTRL_INTABTMASK_MASK -#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMAV2_CHCTRL_CTRL_INTTCMASK_MASK -#define DMA_INTERRUPT_MASK_HALF_TC DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK -#define DMA_INTERRUPT_MASK_ALL \ - (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \ - | DMA_INTERRUPT_MASK_ABORT \ - | DMA_INTERRUPT_MASK_ERROR \ - | DMA_INTERRUPT_MASK_HALF_TC) - -#define DMA_SUPPORT_64BIT_ADDR (0) - - -enum { - dmav2_state_idle = 0, - dmav2_state_read, - dmav2_state_read_ack, - dmav2_state_write, - dmav2_state_write_ack, - dmav2_state_ll, - dmav2_state_end, - dmav2_state_end_wait, -}; - -/** - * @brief Linked descriptor - * - * It is consumed by DMA controlled directly - */ -typedef struct dma_linked_descriptor { - uint32_t ctrl; /**< Control */ - uint32_t trans_size; /**< Transfer size in source width */ - uint32_t src_addr; /**< Source address */ - uint32_t req_ctrl; /**< Request select */ - uint32_t dst_addr; /**< Destination address */ - uint32_t swap_table; /**< Swap table */ - uint32_t linked_ptr; /**< Linked descriptor address */ - uint32_t reserved0; /**< not used on dmav2 */ -} dma_linked_descriptor_t; - -/* @brief Channel config */ -typedef struct dma_channel_config { - uint8_t priority; /**< Channel priority */ - uint8_t src_burst_size; /**< Source burst size */ - uint8_t src_mode; /**< Source work mode */ - uint8_t dst_mode; /**< Destination work mode */ - uint8_t src_width; /**< Source width */ - uint8_t dst_width; /**< Destination width */ - uint8_t src_addr_ctrl; /**< Source address control */ - uint8_t dst_addr_ctrl; /**< Destination address control */ - uint16_t interrupt_mask; /**< Interrupt mask */ - uint32_t src_addr; /**< Source address */ - uint32_t dst_addr; /**< Destination address */ - uint32_t linked_ptr; /**< Next linked descriptor */ - uint32_t size_in_byte; /**< Total size to be transferred in byte */ - bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */ - uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */ - uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */ -#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) - bool en_src_burst_in_fixed_trans; /**< Source burst in fix transfer size enable, discard src_addr_ctrl setting. Attention: only DMAV2 support */ - bool en_dst_burst_in_fixed_trans; /**< Destination burst in fix transfer size enable, discard dst_addr_ctrl setting. Attention: only DMAV2 support */ -#endif -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) - uint8_t swap_mode; /**< Swap Mode. Attention: only DMAV2 support */ - uint32_t swap_table; /**< Swap Table. Attention: only DMAV2 support */ -#endif -} dma_channel_config_t; - -/* @brief Channel config */ -typedef struct dma_handshake_config { - uint32_t dst; - uint32_t src; - uint32_t size_in_byte; - uint8_t data_width; /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */ - uint8_t ch_index; - bool dst_fixed; - bool src_fixed; - bool en_infiniteloop; - uint16_t interrupt_mask; -} dma_handshake_config_t; - - -/* @brief DMA specific status */ -enum { - status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0), - status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1), - status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2), - status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3), - status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4), - status_dma_transfer_half_done = MAKE_STATUS(status_group_dma, 5), -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Reset DMA - * - * @param[in] ptr DMA base address - */ -static inline void dma_reset(DMAV2_Type *ptr) -{ - ptr->DMACTRL |= DMAV2_DMACTRL_RESET_MASK; -} - -/** - * @brief Enable DMA channel - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel to be enabled - * - * @return status_success if everything's okay - */ -static inline hpm_stat_t dma_enable_channel(DMAV2_Type *ptr, uint32_t ch_index) -{ - ptr->CHCTRL[ch_index].CTRL |= DMAV2_CHCTRL_CTRL_ENABLE_MASK; - - if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) { - return status_fail; - } - return status_success; -} - -/** - * @brief Disable DMA channel - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel to be disabled - * - */ -static inline void dma_disable_channel(DMAV2_Type *ptr, uint32_t ch_index) -{ - ptr->CHCTRL[ch_index].CTRL &= ~DMAV2_CHCTRL_CTRL_ENABLE_MASK; -} - -/** - * @brief Check whether DMA channel is enable - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * - * @return true if DMA channel is enable - * - */ -static inline bool dma_channel_is_enable(DMAV2_Type *ptr, uint32_t ch_index) -{ - return (ptr->CHCTRL[ch_index].CTRL & DMAV2_CHCTRL_CTRL_ENABLE_MASK) ? true : false; -} - -/** - * @brief Set DMA channel priority - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] priority dma priority - * @arg @ref DMA_CHANNEL_PRIORITY_LOW - * @arg @ref DMA_CHANNEL_PRIORITY_HIGH - * - */ -static inline void dma_set_priority(DMAV2_Type *ptr, uint32_t ch_index, uint8_t priority) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_PRIORITY_MASK) | DMAV2_CHCTRL_CTRL_PRIORITY_SET(priority); -} - -/** - * @brief Set DMA channel source work mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] mode source work mode - * @arg @ref DMA_HANDSHAKE_MODE_NORMAL - * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE - * - */ -static inline void dma_set_source_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCMODE_MASK) | DMAV2_CHCTRL_CTRL_SRCMODE_SET(mode); -} - -/** - * @brief Set DMA channel destination work mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] mode destination work mode - * @arg @ref DMA_HANDSHAKE_MODE_NORMAL - * @arg @ref DMA_HANDSHAKE_MODE_HANDSHAKE - * - */ -static inline void dma_set_destination_work_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t mode) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTMODE_MASK) | DMAV2_CHCTRL_CTRL_DSTMODE_SET(mode); -} - -/** - * @brief Set DMA channel source burst size - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] burstsize source burst size - * when BURSTOPT is 0, please reference follows: - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_2T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_4T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_8T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_16T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_32T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_64T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_128T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_256T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_512T - * @arg @ref DMA_NUM_TRANSFER_PER_BURST_1024T - * when BURSTOPT is 1, burst size is (burstsize + 1). - * - */ -static inline void dma_set_source_burst_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burstsize) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize); -} - -/** - * @brief Get DMA channel remaining transfer size - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * - * @return remaining transfer size - * - */ -static inline uint32_t dma_get_remaining_transfer_size(DMAV2_Type *ptr, uint32_t ch_index) -{ - return ptr->CHCTRL[ch_index].TRANSIZE; -} - -/** - * @brief Set DMA channel transfer size - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] size_in_width transfer size of the channel. The width is current dma channel configured source width. - * Transfer total bytes are (size_in_width * source width). - * - */ -static inline void dma_set_transfer_size(DMAV2_Type *ptr, uint32_t ch_index, uint32_t size_in_width) -{ - ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width); -} - -/** - * @brief Set DMA channel source width - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] width transfer source width of the channel - * @arg @ref DMA_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_TRANSFER_WIDTH_WORD - * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD - */ -static inline void dma_set_source_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(width); -} - -/** - * @brief Set DMA channel destination width - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] width transfer destination width of the channel - * @arg @ref DMA_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_TRANSFER_WIDTH_WORD - * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD - */ -static inline void dma_set_destination_width(DMAV2_Type *ptr, uint32_t ch_index, uint8_t width) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(width); -} - -/** - * @brief Set DMA channel transfer width and size in byte - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] src_width transfer source width of the channel - * @arg @ref DMA_TRANSFER_WIDTH_BYTE - * @arg @ref DMA_TRANSFER_WIDTH_HALF_WORD - * @arg @ref DMA_TRANSFER_WIDTH_WORD - * @arg @ref DMA_TRANSFER_WIDTH_DOUBLE_WORD - * @param[in] size_in_byte transfer size in byte of the channel. The dma transfer size is (size_in_byte >> src_width). - * - */ -static inline void dma_set_transfer_src_width_byte_size(DMAV2_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte) -{ - assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD) - || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD)); - - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(src_width); - ptr->CHCTRL[ch_index].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width); -} - -/** - * @brief Set DMA channel source address - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr source address - * - */ -static inline void dma_set_source_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr) -{ - ptr->CHCTRL[ch_index].SRCADDR = addr; -} - -/** - * @brief Set DMA channel destination address - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr destination address - * - */ -static inline void dma_set_destination_address(DMAV2_Type *ptr, uint32_t ch_index, uint32_t addr) -{ - ptr->CHCTRL[ch_index].DSTADDR = addr; -} - -/** - * @brief Set DMA channel source address control mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr_ctrl source address control mode - * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT - * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT - * @arg @ref DMA_ADDRESS_CONTROL_FIXED - * - */ -static inline void dma_set_source_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl); -} - -/** - * @brief Set DMA channel destination address control mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] addr_ctrl destination address control mode - * @arg @ref DMA_ADDRESS_CONTROL_INCREMENT - * @arg @ref DMA_ADDRESS_CONTROL_DECREMENT - * @arg @ref DMA_ADDRESS_CONTROL_FIXED - * - */ -static inline void dma_set_destination_address_ctrl(DMAV2_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl); -} - -/** - * @brief Set DMA channel infinite loop mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] infinite_loop false - normal mode(single times mode); true - infinite loop mode(cycle mode) - * - */ -static inline void dma_set_infinite_loop_mode(DMAV2_Type *ptr, uint32_t ch_index, bool infinite_loop) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) | DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(infinite_loop); -} - -/** - * @brief Set DMA channel source burst option - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] burst_opt burst option - * @arg @ref DMA_SRC_BURST_OPT_STANDAND_SIZE - * @arg @ref DMA_SRC_BURST_OPT_CUSTOM_SIZE - * - */ -static inline void dma_set_src_busrt_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t burst_opt) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(burst_opt); -} - -/** - * @brief Set DMA channel handshake option - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] handshake_opt handshake option - * @arg @ref DMA_HANDSHAKE_OPT_ONE_BURST - * @arg @ref DMA_HANDSHAKE_OPT_ALL_TRANSIZE - * - */ -static inline void dma_set_handshake_option(DMAV2_Type *ptr, uint32_t ch_index, uint8_t handshake_opt) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(handshake_opt); -} - -#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) -/** - * @brief Set DMA channel source burst in fixed transfer size enable or disable - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] enable false - disable; true - enable - * - */ -static inline void dma_set_source_burst_in_fixed_transize_enable(DMAV2_Type *ptr, uint32_t ch_index, bool enable) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRC_FIXBURST_MASK) | DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SET(enable); -} - -/** - * @brief Set DMA channel destination burst in fixed transfer size enable or disable - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] enable false - disable; true - enable - * - */ -static inline void dma_set_destination_burst_in_fixed_transize_enable(DMAV2_Type *ptr, uint32_t ch_index, bool enable) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DST_FIXBURST_MASK) | DMAV2_CHCTRL_CTRL_DST_FIXBURST_SET(enable); -} -#endif - -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) -/** - * @brief Set DMA channel swap mode - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] swap_mode swap mode - * @arg @ref DMA_SWAP_MODE_TABLE - * @arg @ref DMA_SWAP_MODE_BYTE - * @arg @ref DMA_SWAP_MODE_HALF_WORD - * @arg @ref DMA_SWAP_MODE_WORD - * - */ -static inline void dma_set_swap_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t swap_mode) -{ - ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SWAP_CTL_MASK) | DMAV2_CHCTRL_CTRL_SWAP_CTL_SET(swap_mode); -} - -/** - * @brief Set DMA channel swap table - * - * @param[in] ptr DMA base address - * @param[in] ch_index Index of the channel - * @param[in] swap_table swap table - * - */ -static inline void dma_set_swap_table(DMAV2_Type *ptr, uint32_t ch_index, uint32_t swap_table) -{ - ptr->CHCTRL[ch_index].SWAPTABLE = swap_table; -} -#endif - -/** - * @brief Abort channel transfer with mask - * - * @param[in] ptr DMA base address - * @param[in] ch_index_mask Mask of channels to be aborted - */ -static inline void dma_abort_channel(DMAV2_Type *ptr, uint32_t ch_index_mask) -{ - ptr->CHABORT |= DMAV2_CHABORT_CHABORT_SET(ch_index_mask); -} - -/** - * @brief Check if channels are enabled with mask - * - * @param[in] ptr DMA base address - * @param[in] ch_index_mask Mask of channels to be checked - * - * @return Enabled channel mask - */ -static inline uint32_t dma_check_enabled_channel(DMAV2_Type *ptr, - uint32_t ch_index_mask) -{ - return (ch_index_mask & ptr->CHEN); -} - -/** - * @brief Check if linked pointer has been configured - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be checked - * - * @return true if linked pointer has been configured - */ -static inline bool dma_has_linked_pointer_configured(DMAV2_Type *ptr, uint32_t ch_index) -{ - return ptr->CHCTRL[ch_index].LLPOINTER != 0; -} - -/** - * @brief Check transfer status - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be checked - * - * @retval DMA_CHANNEL_STATUS_ONGOING if transfer is still ongoing - * @retval DMA_CHANNEL_STATUS_ERROR if any error occurred during transferring - * @retval DMA_CHANNEL_STATUS_ABORT if transfer is aborted - * @retval DMA_CHANNEL_STATUS_TC if transfer is finished without error - * @retval DMA_CHANNEL_STATUS_HALF_TC if half transfer complete without error - */ -static inline uint32_t dma_check_transfer_status(DMAV2_Type *ptr, uint8_t ch_index) -{ - uint32_t dma_status = 0; - - if (ptr->INTTCSTS & (1 << ch_index)) { - dma_status |= DMA_CHANNEL_STATUS_TC; - ptr->INTTCSTS = (1 << ch_index); /* W1C clear status*/ - } - if (ptr->INTHALFSTS & (1 << ch_index)) { - dma_status |= DMA_CHANNEL_STATUS_HALF_TC; - ptr->INTHALFSTS = (1 << ch_index); /* W1C clear status*/ - } - if (ptr->INTERRSTS & (1 << ch_index)) { - dma_status |= DMA_CHANNEL_STATUS_ERROR; - ptr->INTERRSTS = (1 << ch_index); /* W1C clear status*/ - } - if (ptr->INTABORTSTS & (1 << ch_index)) { - dma_status |= DMA_CHANNEL_STATUS_ABORT; - ptr->INTABORTSTS = (1 << ch_index); /* W1C clear status*/ - } - if (dma_status == 0) { - dma_status = DMA_CHANNEL_STATUS_ONGOING; - } - return dma_status; -} - -/** - * @brief Clear transfer status - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index - * - */ -static inline void dma_clear_transfer_status(DMAV2_Type *ptr, uint8_t ch_index) -{ - /* W1C */ - ptr->INTHALFSTS = (1 << ch_index); - ptr->INTTCSTS = (1 << ch_index); - ptr->INTABORTSTS = (1 << ch_index); - ptr->INTERRSTS = (1 << ch_index); -} - -/** - * @brief Enable DMA Channel interrupt - * - * @param [in] ptr DMA base address - * @param [in] ch_index Target channel index - * @param [in] interrupt_mask Interrupt mask - */ -static inline void dma_enable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) -{ - ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL); -} - -/** - * @brief Disable DMA Channel interrupt - * - * @param [in] ptr DMA base address - * @param [in] ch_index Target channel index - * @param [in] interrupt_mask Interrupt mask - */ -static inline void dma_disable_channel_interrupt(DMAV2_Type *ptr, uint8_t ch_index, int32_t interrupt_mask) -{ - ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL); -} - - -/** - * @brief Check Channel interrupt master - * - * @param[in] ptr DMA base address - * @param[in] ch_index Target channel index to be checked - * @return uint32_t Interrupt mask - */ -static inline uint32_t dma_check_channel_interrupt_mask(DMAV2_Type *ptr, uint8_t ch_index) -{ - return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL; -} - -/** - * @brief Get default channel config - * - * @param[in] ptr DMA base address - * @param[in] ch Channel config - */ -void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch); - -/** - * @brief Setup DMA channel - * - * @param[in] ptr DMA base address - * @param[in] ch_num Target channel index to be configured - * @param[in] ch Channel config - * @param[in] start_transfer Set true to start transfer - * - * @return status_success if everything is okay - */ -hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num, - dma_channel_config_t *ch, bool start_transfer); - -/** - * @brief Config linked descriptor function - * - * @param[in] ptr DMA base address - * @param[in] descriptor Linked descriptor pointer - * @param[in] ch_num Target channel index to be configured - * @param[in] config Descriptor config pointer - * - * @return status_success if everything is okay - */ -hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config); - -/** - * @brief Start DMA copy - * - * @param[in] ptr DMA base address - * @param[in] ch_num Target channel index - * @param[in] dst Destination address - * @param[in] src Source Address - * @param[in] size_in_byte Size in byte - * @param[in] burst_len_in_byte Burst length in byte - * - * @return status_success if everthing is okay - * @note: dst, src, size should be aligned with burst_len_in_byte - */ -hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num, - uint32_t dst, uint32_t src, - uint32_t size_in_byte, uint32_t burst_len_in_byte); - -/** - * @brief Get default handshake config - * - * @param[in] ptr DMA base address - * @param[in] config default config - */ -void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config); - -/** - * @brief config dma handshake function - * - * @param[in] ptr DMA base address - * @param[in] pconfig dma handshake config pointer - * @param[in] start_transfer Set true to start transfer - * - * @return status_success if everything is okay - */ -hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer); - -/** - * @brief Check whether DMA is idle - * @param [in] ptr DMA base address - * @return true DMA is idle - * @return false DMA is busy - */ -static inline bool dma_is_idle(DMAV2_Type *ptr) -{ - return (DMAV2_IDMISC_DMASTATE_GET(ptr->IDMISC) == dmav2_state_idle) ? true : false; -} - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_DMAV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h deleted file mode 100644 index 677c3943309..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enc_pos_drv.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ENC_POS_COMMON_H -#define HPM_ENC_POS_COMMON_H - -#include "hpm_common.h" - -/** - * - * @brief enc pos driver APIs - * @defgroup enc_pos_interface Encode Position driver APIs - * @ingroup io_interface - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief caculate degree of angle from pos - * - * @param[in] pos position value - * @return degree of angle. - */ -float encoder_position_to_deg(uint32_t pos); - -/** - * @brief caculate posistion from degree of angle - * - * @param[in] deg degree of angle - * @return position value. - */ -uint32_t encoder_deg_to_position(float deg); - -/** - * @brief caculate radian of angle from pos - * - * @param[in] pos position value - * @return radian of angle. - */ -float encoder_position_to_rad(uint32_t pos); - -/** - * @brief caculate posistion from radian of angle - * - * @param[in] rad radian of angle - * @return position value. - */ -uint32_t encoder_rad_to_position(float rad); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_ENC_POS_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h deleted file mode 100644 index 61f1d14de66..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h +++ /dev/null @@ -1,851 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ENET_DRV_H -#define HPM_ENET_DRV_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_common.h" -#include "hpm_enet_regs.h" -#include "hpm_soc_feature.h" -#include "hpm_enet_soc_drv.h" - -/** - * @brief Enet driver APIs - * @defgroup enet_interface Enet driver APIs - * @ingroup communication_interfaces - * @{ - */ - -/*--------------------------------------------------------------------- - * Macro Constant Declarations - *--------------------------------------------------------------------- - */ -#define ENET_HEADER (14U) /**< 6-byte Dest addr, 6-byte Src addr, 2-byte type */ -#define ENET_EXTRA (2U) /**< Extra bytes in some cases */ -#define ENET_VLAN_TAG (4U) /**< optional 802.1q VLAN Tag */ -#define ENET_CRC (4U) /**< Ethernet CRC */ -#define ENET_MIN_PAYLOAD (46U) /**< Minimum Ethernet payload size */ -#define ENET_MAX_PAYLOAD (1500U) /**< Maximum Ethernet payload size */ -#define ENET_MAX_FRAME_SIZE (1524U) /**< ENET_HEADER + ENET_EXTRA + VLAN_TAG + MAX_ENET_PAYLOAD + ENET_CRC */ -#define ENET_JUMBO_FRAME_PAYLOAD (9000U) /**< Jumbo frame payload size */ -#define ENET_MAC (6) /**< Ethernet MAC size */ -#define ENET_ERROR (0) /**< ENET error */ -#define ENET_SUCCESS (1) /**< ENET success */ - -#define ENET_ADJ_FREQ_BASE_ADDEND (0x80000000UL) /**< PTP base adjustment addend */ -#define ENET_ONE_SEC_IN_NANOSEC (1000000000UL) /**< one second in nanoseconds */ - -#define ENET_PPS_CMD_MASK (0x07UL) /**< Enet PPS CMD Mask */ -#define ENET_PPS_CMD_OFS_FAC (3U) /**< Enet PPS CMD OFS Factor */ - -#ifndef ENET_RETRY_CNT -#define ENET_RETRY_CNT (10000UL) /**< Enet retry count for PTP */ -#endif - -/*--------------------------------------------------------------------- - * Typedef Enum Declarations - *--------------------------------------------------------------------- - */ - -/** @brief interrupt enable type */ -typedef enum { - enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK, - enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK, - enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK, - enet_transmit_int_en = ENET_DMA_INTR_EN_TIE_MASK -} enet_interrupt_enable_t; - -/** @brief interrupt mask type */ -typedef enum { - enet_lpi_int_mask = ENET_INTR_MASK_LPIIM_MASK, - enet_rgsmii_int_mask = ENET_INTR_MASK_RGSMIIIM_MASK -} enet_interrupt_mask_t; - - -/** @brief Programmable burst length selections */ -typedef enum { - enet_pbl_1 = 1, - enet_pbl_2 = 2, - enet_pbl_4 = 4, - enet_pbl_8 = 8, - enet_pbl_16 = 16, - enet_pbl_32 = 32 -} enet_pbl_t; - -/** @brief Checksum insertion control selections */ -typedef enum { - enet_cic_disable = 0, - enet_cic_ip = 1, - enet_cic_ip_no_pseudoheader = 2, - enet_cic_ip_pseudoheader = 3 -} enet_cic_insertion_control_t; - -/** @brief VLAN insertion control selections */ -typedef enum { - enet_vlic_disable = 0, - enet_vlic_remove_vlan_tag = 1, - enet_vlic_insert_vlan_tag = 2, - enet_vlic_replace_vlan_tag = 3 -} enet_vlan_insertion_control_t; - -/** @brief SA insertion or replacement control selections for any selective frames */ -typedef enum { - enet_saic_disable = 0, - enet_saic_insert_mac0 = 1, - enet_saic_replace_mac0 = 2, - enet_saic_insert_mac1 = 5, - enet_saic_replace_mac1 = 6 -} enet_saic_insertion_replacement_control_t; - -/** @brief SA insertion or replacement control selections for all transmit frames */ -typedef enum { - enet_sarc_disable = 0, - enet_sarc_insert_mac0 = 2, - enet_sarc_replace_mac0 = 3, - enet_sarc_insert_mac1 = 6, - enet_sarc_replace_mac1 = 7 -} enet_sarc_insertion_replacement_control_t; - -/** @brief PHY operation selections */ -typedef enum { - enet_phy_op_read = 0, - enet_phy_op_write -} enet_phy_op_t; - - -/** @brief PHY status */ -typedef enum { - enet_gmii_idle = 0, - enet_gmii_busy -} enet_gmii_status_t; - -/** @brief CSR clock range and MDC clock selections */ -/** @note The suggested range of CSR clock is approximately - * between the frequency range 1.0MHz-2.5MHz. - * You can achieve higher frequency of the MDC clock than the frequency limit of 2.5MHz(specified in the IEEE Std 802.3) - * and program a clock divider of lower value. Program the value which is no less than enet_csr_60m_to_100m_mdc_csr_div_4 - * only if the interfacing chips support faster MDC clocks. - */ -typedef enum { - enet_csr_60m_to_100m_mdc_csr_div_42 = 0, /**< CSR clock range: 60-100MHz <==> MDC clock: CSR clock / 42 */ - enet_csr_100m_to_150m_mdc_csr_div_62, /**< CSR clock range: 100-150MHz <==> MDC clock: CSR clock / 62 */ - enet_csr_20m_to_35m_mdc_csr_div_16, /**< CSR clock range: 20-35MHz <==> MDC clock: CSR clock / 16 */ - enet_csr_35m_to_60m_mdc_csr_div_26, /**< CSR clock range: 35-60MHz <==> MDC clock: CSR clock / 26 */ - enet_csr_150m_to_250m_mdc_csr_div_102, /**< CSR clock range: 150-250MHz <==> MDC clock: CSR clock / 102 */ - enet_csr_250m_to_300m_mdc_csr_div_124, /**< CSR clock range: 250-300MHz <==> MDC clock: CSR clock / 124 */ - - enet_csr_60m_to_100m_mdc_csr_div_4 = 8, /**< CSR clock / 4 */ - enet_csr_60m_to_100m_mdc_csr_div_6, /**< CSR clock / 6 */ - enet_csr_60m_to_100m_mdc_csr_div_8, /**< CSR clock / 8 */ - enet_csr_60m_to_100m_mdc_csr_div_10, /**< CSR clock / 10 */ - enet_csr_60m_to_100m_mdc_csr_div_12, /**< CSR clock / 12 */ - enet_csr_60m_to_100m_mdc_csr_div_14, /**< CSR clock / 14 */ - enet_csr_60m_to_100m_mdc_csr_div_16, /**< CSR clock / 16 */ - enet_csr_60m_to_100m_mdc_csr_div_18 /**< CSR clock / 18 */ -} enet_csr_clk_range_t; - -/** @brief enet interface selections */ -typedef enum { - enet_inf_mii = 0, - enet_inf_rmii = 4, - enet_inf_rgmii = 1 -} enet_inf_type_t; - -/** @brief enet line speed */ -typedef enum { - enet_line_speed_1000mbps = 0, - enet_line_speed_10mbps = 2, - enet_line_speed_100mbps = 3 -} enet_line_speed_t; - -/** @brief enet duplex mode */ -typedef enum { - enet_half_duplex = 0, - enet_full_duplex -} enet_duplex_mode_t; - -/** @brief enet timestamp update methods */ -typedef enum { - enet_ptp_time_coarse_update = 0, - enet_ptp_time_fine_update -} enet_ptp_time_update_method_t; - -/** @brief PTP versions */ -typedef enum { - enet_ptp_v1 = 0, - enet_ptp_v2 -} enet_ptp_version_t; - -/** @brief PTP frame types */ -typedef enum { - enet_ptp_frame_ipv4 = 0, - enet_ptp_frame_ipv6, - enet_ptp_frame_ethernet -} enet_ptp_frame_type_t; - -/** @brief PTP message type for snapshots */ -typedef enum { - enet_ts_ss_ptp_msg_0 = 0, /* SYNC, Follow_Up, Delay_Req, Delay_Resp */ - enet_ts_ss_ptp_msg_1 = 1, /* SYNC */ - enet_ts_ss_ptp_msg_2 = 3, /* Delay_Req */ - enet_ts_ss_ptp_msg_3 = 4, /* SYNC, Follow_Up, Delay_Req, Delay_Resp, Pdelay_Req, Pdelay_Resp, Pdelay_Resp_Follow_Up */ - enet_ts_ss_ptp_msg_4 = 5, /* SYNC, Pdelay_Req, Pdelay_Resp */ - enet_ts_ss_ptp_msg_5 = 7, /* Delay_Req, Pdelay_Req, Pdelay_Resp */ - enet_ts_ss_ptp_msg_6 = 8, /* SYNC, Delay_Req */ - enet_ts_ss_ptp_msg_7 = 12 /* Pdelay_Req, Pdelay_Resp */ -} enet_ts_ss_ptp_msg_t; - -/** @brief PTP timer rollover modes */ -typedef enum { - enet_ts_bin_rollover_control = 0, /* timestamp rolls over after 0x7fffffff */ - enet_ts_dig_rollover_control /* timestamp rolls over after 0x3b9ac9ff */ -} enet_ts_rollover_control_t; - -/** @brief PPS indexes */ -typedef enum { - enet_pps_0 = -1, - enet_pps_1 = 0, - enet_pps_2 = 1, - enet_pps_3 = 2 -} enet_pps_idx_t; - -/** @brief PPS0 control for output frequency selections */ -typedef enum { - enet_pps_ctrl_pps = 0, - enet_pps_ctrl_bin_2hz_digital_1hz, - enet_pps_ctrl_bin_4hz_digital_2hz, - enet_pps_ctrl_bin_8hz_digital_4hz, - enet_pps_ctrl_bin_16hz_digital_8hz, - enet_pps_ctrl_bin_32hz_digital_16hz, - enet_pps_ctrl_bin_64hz_digital_32hz, - enet_pps_ctrl_bin_128hz_digital_64hz, - enet_pps_ctrl_bin_256hz_digital_128hz, - enet_pps_ctrl_bin_512hz_digital_256hz, - enet_pps_ctrl_bin_1024hz_digital_512hz, - enet_pps_ctrl_bin_2048hz_digital_1024hz, - enet_pps_ctrl_bin_4096hz_digital_2048hz, - enet_pps_ctrl_bin_8192hz_digital_4096hz, - enet_pps_ctrl_bin_16384hz_digital_8192hz, - enet_pps_ctrl_bin_32768hz_digital_16384hz -} enet_pps_ctrl_t; - -/** @brief PPS0 commands */ -typedef enum { - enet_pps_cmd_no_command = 0, - enet_pps_cmd_start_single_pulse, - enet_pps_cmd_start_pulse_train, - enet_pps_cmd_cancel_start, - enet_pps_cmd_stop_pulse_train_at_time, - enet_pps_cmd_stop_pulse_train_immediately, - enet_pps_cmd_cancel_stop_pulse_train -} enet_pps_cmd_t; - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *--------------------------------------------------------------------- - */ -/** @brief enet buffer config struct */ -typedef struct { - uint32_t buffer; - uint32_t count; - uint16_t size; -} enet_buff_config_t; - -/** @brief enet mac config struct */ -typedef struct { - uint32_t mac_addr_high[ENET_SOC_ADDR_MAX_COUNT]; - uint32_t mac_addr_low[ENET_SOC_ADDR_MAX_COUNT]; - uint8_t valid_max_count; - uint8_t dma_pbl; - uint8_t sarc; -} enet_mac_config_t; - -/** @brief transmission descriptor struct */ -typedef struct { - union { - uint32_t tdes0; - struct { - uint32_t db: 1; /**< * Deferred Bit*/ - uint32_t uf: 1; /**< * Underflow Error */ - uint32_t ed: 1; /**< * Excessive Deferral */ - uint32_t cc: 4; /**< * Collision Count */ - uint32_t vf: 1; /**< * VLAN Frame */ - uint32_t ec: 1; /**< * Excessive Collision */ - uint32_t lc: 1; /**< * Late Collision */ - uint32_t nc: 1; /**< * No Carrier */ - uint32_t loc: 1; /**< * Loss of Carrier */ - uint32_t ipe: 1; /**< * IP Payload Error */ - uint32_t ff: 1; /**< * Frame Flushed */ - uint32_t jt: 1; /**< * Jabber Timeout */ - uint32_t es: 1; /**< * Error Summary */ - uint32_t ihe: 1; /**< * IP Header Error */ - uint32_t ttss: 1; /**< * Transmit Timestamp Status */ - uint32_t vlic: 2; /**< * VLAN Insertion Control */ - uint32_t tch: 1; /**< * Second Address Chained */ - uint32_t ter: 1; /**< * Transmit End of Ring */ - uint32_t cic: 2; /**< * Checksum Insertion Control */ - uint32_t crcr: 1; /**< * CRC Replacement Control */ - uint32_t ttse: 1; /**< * Transmit Timestamp Enable */ - uint32_t dp: 1; /**< * Disable Pad */ - uint32_t dc: 1; /**< * Disable CRC */ - uint32_t fs: 1; /**< * First Segment */ - uint32_t ls: 1; /**< * Last Segment */ - uint32_t ic: 1; /**< * Interrupt on Completion */ - uint32_t own: 1; /**< * Own Bit */ - } tdes0_bm; - }; - - union { - uint32_t tdes1; - struct { - uint32_t tbs1 : 13; /**< Transmit Buffer 1 Size */ - uint32_t reserved: 3; /**< Reserved */ - uint32_t tbs2 : 13; /**< Transmit Buffer 2 Size */ - uint32_t saic : 3; /**< SA Insertion Control */ - } tdes1_bm; - }; - - union { - uint32_t tdes2; - struct { - uint32_t buffer1; /**< Buffer 1 Address */ - } tdes2_bm; - }; - - union { - uint32_t tdes3; - union { - uint32_t buffer2; /**< Buffer 2 Address */ - uint32_t next_desc; /**< Next Descriptor Address */ - } tdes3_bm; - }; - -#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN - struct { - uint32_t reserved; - } tdes4_bm; - - struct { - uint32_t reserved; - } tdes5_bm; - - struct { - uint32_t ttsl; /**< Transmit Frame Timestamp Low */ - } tdes6_bm; - - struct { - uint32_t ttsh; /**< Transmit Frame Timestamp High */ - } tdes7_bm; -#endif -} enet_tx_desc_t; - -/** @brief reception descriptor struct */ -typedef struct { - union { - uint32_t rdes0; - - struct { - uint32_t ex_sta_rx_addr : 1; /**< Extended Status Available or Rx MAC Address*/ - uint32_t ce : 1; /**< CRC Error */ - uint32_t dbe : 1; /**< Dribble Bit Error */ - uint32_t re : 1; /**< Receive Error */ - uint32_t rwt : 1; /**< Receive Watchdog Timeout */ - uint32_t ft : 1; /**< Frame Type */ - uint32_t lc : 1; /**< Late Collision */ - uint32_t ts_ip_gf : 1; /**< Timestamp Available, IP Checksum Error or Giant Frame*/ - uint32_t ls : 1; /**< Last Descriptor */ - uint32_t fs : 1; /**< First Descriptor */ - uint32_t vlan : 1; /**< VLAN Tag */ - uint32_t oe : 1; /**< Overflow Error */ - uint32_t le : 1; /**< Length Error */ - uint32_t saf : 1; /**< Source Address Filter Fail */ - uint32_t dse : 1; /**< Descriptor Error */ - uint32_t es : 1; /**< Error Summary */ - uint32_t fl : 14; /**< Frame Length */ - uint32_t afm : 1; /**< Destination Address Filter Fail */ - uint32_t own : 1; /**< Own Bit */ - } rdes0_bm; - }; - - union { - uint32_t rdes1; - struct { - uint32_t rbs1 : 13; /**< Receive Buffer 1 Size */ - uint32_t reserved0: 1; /**< Reserved */ - uint32_t rch : 1; /**< Second Address Chained */ - uint32_t rer : 1; /**< Receive End of Ring */ - uint32_t rbs2 : 13; /**< Receive Buffer 2 Size */ - uint32_t reserved1: 2; /**< Reserved */ - uint32_t dic : 1; /**< Disable Interrupt on Completion */ - } rdes1_bm; - }; - - union { - uint32_t rdes2; - struct { - uint32_t buffer1; /**< Buffer 1 Address */ - } rdes2_bm; - }; - - union { - uint32_t rdes3; - union { - uint32_t buffer2; /**< Buffer 2 Address */ - uint32_t next_desc; /**< Next Descriptor Address */ - } rdes3_bm; - }; - -#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN - union { - uint32_t rdes4; - struct { - uint32_t ip_payload_type : 3; /**< IP Payload Type */ - uint32_t ip_header_err : 1; /**< IP Header Error */ - uint32_t ip_payload_err : 1; /**< IP Payload Error */ - uint32_t ip_chksum_bypassed : 1; /**< IP Checksum Bypassed */ - uint32_t ipv4_pkt_received : 1; /**< IPv4 Packet Received */ - uint32_t ipv6_pkt_received : 1; /**< IPv6 Packet Received */ - uint32_t msg_type : 4; /**< Message Type */ - uint32_t ptp_frame_type : 1; /**< PTP Frame Type */ - uint32_t ptp_version : 1; /**< PTP Version */ - uint32_t ts_dp : 1; /**< Timestamp Dropped */ - uint32_t reserved0 : 1; /**< Reserved */ - uint32_t av_pkt_recv : 1; /**< AV Packet Received */ - uint32_t av_tagged_pkt_recv : 1; /**< AV Tagged Packet Received */ - uint32_t vlan_tag_pri_value : 3; /**< VLAN Tag Priority Value */ - uint32_t reserved1 : 3; /**< Reserved */ - uint32_t l3_fm : 1; /**< Layer 3 Filter Matched */ - uint32_t l4_fm : 1; /**< Layer 4 Filter Matched */ - uint32_t l3_l4_fnl : 2; /**< Layer 3 and Layer 4 Filter Number Matched */ - uint32_t reserved2 : 4; /**< Reserved */ - } rdes4_bm; - }; - - struct { - uint32_t reserved; - } rdes5_bm; - - struct { - uint32_t rtsl; /**< Receive Frame Timestamp Low */ - } rdes6_bm; - - struct { - uint32_t rtsh; /**< Receive Frame Timestamp High */ - } rdes7_bm; -#endif -} enet_rx_desc_t; - -/** @brief enet frame struct */ -typedef struct{ - uint32_t length; - uint32_t buffer; - enet_rx_desc_t *rx_desc; -} enet_frame_t; - -/** @brief enet reception frame info struct */ -typedef struct { - enet_rx_desc_t *fs_rx_desc; - enet_rx_desc_t *ls_rx_desc; - uint32_t seg_count; -} enet_rx_frame_info_t; - -/** @brief enet control config struct for transmission */ -typedef struct { - bool enable_ioc; /* interrupt on completion */ - bool disable_crc; /* disable CRC */ - bool disable_pad; /* disable Pad */ - bool enable_ttse; /* enable transmit timestamp */ - bool enable_crcr; /* CRC replacement control */ - uint8_t cic; /* checksum insertion control */ - uint8_t vlic; /* VLAN insertion control */ - uint8_t saic; /* SA insertion control */ -} enet_tx_control_config_t; - -/** @brief enet description struct */ -typedef struct { - enet_tx_desc_t *tx_desc_list_head; - enet_rx_desc_t *rx_desc_list_head; - enet_tx_desc_t *tx_desc_list_cur; - enet_rx_desc_t *rx_desc_list_cur; - enet_buff_config_t tx_buff_cfg; - enet_buff_config_t rx_buff_cfg; - enet_rx_frame_info_t rx_frame_info; - enet_tx_control_config_t tx_control_config; -} enet_desc_t; - -/** @brief PTP system timestamp struct */ -typedef struct { - uint32_t sec; - uint32_t nsec; -} enet_ptp_ts_system_t; - -/** @brief PTP update timestamp struct */ -typedef struct { - uint32_t sec; - uint32_t nsec; - uint8_t sign; -} enet_ptp_ts_update_t; - -/** @brief PTP target timestamp struct */ -typedef struct { - uint32_t sec; - uint32_t nsec; -} enet_ptp_ts_target_t; - -/** @brief PTP config strcut */ -typedef struct { - uint8_t ssinc; - uint8_t timestamp_rollover_mode; - uint8_t update_method; - uint32_t addend; -} enet_ptp_config_t; - -/** @brief PTP PPS command output config strcut */ -typedef struct { - uint32_t pps_interval; - uint32_t pps_width; - uint32_t target_sec; - uint32_t target_nsec; -} enet_pps_cmd_config_t; - -/** @brief Enet interrupt config struct */ -typedef struct { - uint32_t int_enable; /* DMA_INTR_EN */ - uint32_t int_mask; /* INTR MASK */ - uint32_t mmc_intr_rx; - uint32_t mmc_intr_mask_rx; - uint32_t mmc_intr_tx; - uint32_t mmc_intr_mask_tx; -} enet_int_config_t; - -/* - * @brief Bit definition of TDES1 - */ -#define ENET_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /**< Transmit Buffer2 Size */ -#define ENET_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /**< Transmit Buffer1 Size */ - -#if defined __cplusplus -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *--------------------------------------------------------------------- - */ -/** - * @brief Get a default control config for tranmission - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] config A pointer to a control config structure for tranmission - */ -void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config); - -/** - * @brief Get a default interrupt config - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] config A pointer to a interrupt config structure - */ -void enet_get_default_interrupt_config(ENET_Type *ptr, enet_int_config_t *config); - -/** - * @brief Get interrupt status - * - * @param[in] ptr An Ethernet peripheral base address - * @return A result of interrupt status - */ -uint32_t enet_get_interrupt_status(ENET_Type *ptr); - -/** - * @brief Mask the specified mmc interrupt evenets of received frames - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] mask A mask of the specified evenets - */ -void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask); - -/** - * @brief Mask the specified mmc interrupt evenets of transmitted frames - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] mask A mask of the specified evenets - */ -void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask); - -/** - * @brief Get a staus of mmc receive interrupt events - * - * @param[in] ptr An Ethernet peripheral base address - * @return A result of interrupt status - */ -uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr); -/** - * @brief et a staus of mmc transmission interrupt events - * - * @param[in] ptr An Ethernet peripheral base address - * @return A result of interrupt status - */ -uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr); - -/** - * @brief Initialize controller - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] inf_type the specified interface - * @param[in] desc A pointer to descriptor config - * @param[in] cfg A pointer to mac config - * @param[in] int_config A pointer to the masks of the specified enabled interrupts and the specified masked interrupts - * @return A result of the specified controller initialization - */ -hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *cfg, enet_int_config_t *int_config); - -/** - * @brief Set port line speed - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] speed An enum variable of @ref enet_line_speed_t - */ -void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed); - -/** - * @brief Set duplex mode - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] mode An enum variable of @ref enet_duplex_mode_t - */ -void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode); - -/** - * @brief Read phy - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] phy_addr the specified address of phy - * @param[in] addr the specified address of register - * @retval A value corresponding to the specified register address - */ -uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr); - -/** - * @brief Write phy - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] phy_addr a specified address of phy - * @param[in] addr a specified address of the register - * @param[in] data a specified data to be written - */ -void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data); - -/** - * @brief Resume reception process - * - * @param[in] ptr An Ethernet peripheral base address - * - */ -void enet_rx_resume(ENET_Type *ptr); - -/** - * @brief Check if there is a received frame - * - * @param[out] parent_rx_desc_list_cur a parent pointer to the current reception description list - * @param[in] rx_frame_info A pointer to the information of the reception frames - * @retval A result of reception frame. - * 1 means that a reception of frame is successful. - * 0 means that a reception of frame is unsuccessful. - */ -uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); - -/** - * @brief get a received frame - * - * @param[out] parent_rx_desc_list_cur A parent pointer to the current reception description list - * @param[in] rx_frame_info A pointer to the information of the reception frames - * @retval A struct of the current reception frame - */ -enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info); - -/** - * @brief get a received frame from interrupt - * - * @param[out] parent_rx_desc_list_cur the parent pointer to the current reception description list - * @param[in] rx_frame_info A pointer to the information of the reception frames - * @param[in] rx_desc_count A total count of the reception descriptors - * @retval A struct of the current reception frame - */ -enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count); - -/** - * @brief prepare for the transmission descriptors (It will be deprecated.) - * - * @param[in] ptr An Ethernet peripheral base address - * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames - * @param[in] frame_length the length of the transmission - * @param[in] tx_buff_size the size of the transmission buffer - * @retval a result of the transmission preparation. - * 1 means that the preparation is successful. - * 0 means that the preparation is unsuccessful. - */ -uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size); - -/** - * @brief prepare for the transmission descriptors - * - * @param[in] ptr An Ethernet peripheral base address - * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames - * @param[in] config a pointer to the control configuration for the transmission frames - * @param[in] frame_length the length of the transmission - * @param[in] tx_buff_size the size of the transmission buffer - * @retval a result of the transmission preparation. - * 1 means that the preparation is successful. - * 0 means that the preparation is unsuccessful. - */ -uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size); - -/** - * @brief prepare for the transmission descriptors with a timestamp record - * - * @param[in] ptr An Ethernet peripheral base address - * @param[out] parent_tx_desc_list_cur a pointer to the information of the reception frames - * @param[in] config a pointer to the control configuration for the transmission frames - * @param[in] frame_length the length of the transmission - * @param[in] tx_buff_size the size of the transmission buffer - * @param[out] timestamp a pointer to the timestamp record of a transmitted frame - * @retval a result of the transmission preparation. - * 1 means that the preparation is successful. - * 0 means that the preparation is unsuccessful. - */ -uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr, - enet_tx_desc_t **parent_tx_desc_list_cur, - enet_tx_control_config_t *config, - uint16_t frame_length, uint16_t tx_buff_size, - enet_ptp_ts_system_t *timestamp); - -/** - * @brief Initialize DMA transmission descriptors in chain mode - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] desc A pointer to transmission descriptors - */ -void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); - -/** - * @brief Initialize DMA reception descriptors in chain mode - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] desc A pointer to reception descriptors - */ -void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc); - -/** - * @brief Flush DMA - * - * @param[in] ptr An Ethernet peripheral base address - */ -void enet_dma_flush(ENET_Type *ptr); - -/** - * @brief Initialize a PTP timer - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] config A pointer to an enet_ptp_config struct instance - */ -void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config); - -/** - * @brief Set a timestamp to the PTP timer - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] timestamp A pointer to a update timestamp structure instance - */ -void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp); - -/** - * @brief Get a timestamp from the PTP timer - * - * @param[in] ptr An Ethernet peripheral base address - * @param[out] timestamp A pointer to a system timestamp structure instance - */ -void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp); - -/** - * @brief Update a timestamp to the PTP timer - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] timeoffset A pointer to a update timestamp structure instance - */ -void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset); - -/** - * @brief Adjust the count frequency of the PTP timer - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] adj An adjustment value for the count frequency of the PTP timer - */ -void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj); - -/** - * @brief Set the PTP version - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] ptp_ver An enum value indicating the PTP protocol - */ -void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver); - -/** - * @brief Enable the specified ptp frame type for MAC process - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] ptp_frame_type An enum value indicating the transport protocol of PTP frames - * @param[in] enable A value to enable or disable the transport protocol of PTP frames which is specified by ptp_frame_type parameter - * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success - */ -hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable); - -/** - * @brief Set the ptp message type for snapshots - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] ts_ss_ptp_msg An enum value indicating the specified ptp message type for snapshots - */ -void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg); - -/** - * @brief Set the pps0 control output - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] freq An enum value indicating the specified pps frequency - */ -void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq); - -/** - * @brief Set a pps command for ppsx - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] cmd An enum value indicating the specified pps command - * @param[in] idx An enum value indicating the index of pps instance - * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success - */ -hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx); - -/** - * @brief Set a pps config for ppsx - * - * @param[in] ptr An Ethernet peripheral base address - * @param[in] cmd_cfg An enum value indicating the specified pps config - * @param[in] idx An enum value indicating the index of pps instance - * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success - */ -hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx); - -#if defined __cplusplus -} -#endif /* __cplusplus */ - -/** @} */ -#endif /* HPM_ENET_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_esc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_esc_drv.h deleted file mode 100644 index c8d33b8a21a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_esc_drv.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ESC_DRV_H -#define HPM_ESC_DRV_H - -#include "hpm_common.h" -#include "hpm_esc_regs.h" - -/** - * - * @brief ESC driver APIs - * @defgroup esc_interface ESC driver APIs - * @ingroup esc_interfaces - * @{ - */ - - /** - * @brief ESC error codes - */ -enum { - status_esc_eeprom_ack_error = MAKE_STATUS(status_group_esc, 0), /**< ESC EEPROM ack error */ - status_esc_eeprom_checksum_error = MAKE_STATUS(status_group_esc, 1), /**< ESC EEPROM checksum error */ -}; - - -typedef enum { - latch_source_from_ntm = 0, - latch_source_from_trigger_mux = 1, -} esc_latch_source_t; - -typedef enum { - esc_eeprom_idle_cmd = 0, /* clear error bits */ - esc_eeprom_read_cmd = 1, - esc_eeprom_write_cmd = 2, - esc_eeprom_reload_cmd = 4, -} esc_eeprom_cmd_t; - -typedef enum { - esc_ctrl_signal_func_alt_nmii_link0 = 0, - esc_ctrl_signal_func_alt_nmii_link1 = 1, - esc_ctrl_signal_func_alt_nmii_link2 = 2, - esc_ctrl_signal_func_alt_link_act0 = 3, - esc_ctrl_signal_func_alt_link_act1 = 4, - esc_ctrl_signal_func_alt_link_act2 = 5, - esc_ctrl_signal_func_alt_led_run = 6, - esc_ctrl_signal_func_alt_led_err = 7, - esc_ctrl_signal_func_alt_reset_out = 8, -} esc_ctrl_signal_function_t; - - -typedef struct { - bool eeprom_emulation; - bool eeprom_size_over_16kbit; - bool core_clock_en; - bool phy_refclk_en; -} esc_eeprom_clock_config_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief ESC peripheral clock - * - * @param[in] ptr ESC base address - * @param[in] enable Set true to enable or false to disable - */ -static inline void esc_core_enable_clock(ESC_Type *ptr, bool enable) -{ - if (enable) { - ptr->GPR_CFG0 |= ESC_GPR_CFG0_CLK100_EN_MASK; - } else { - ptr->GPR_CFG0 &= ~ESC_GPR_CFG0_CLK100_EN_MASK; - } -} - -/** - * @brief ESC PHY clock - * - * @param[in] ptr ESC base address - * @param[in] enable Set true to enable or false to disable - */ -static inline void esc_phy_enable_clock(ESC_Type *ptr, bool enable) -{ - if (enable) { - ptr->PHY_CFG1 |= ESC_PHY_CFG1_REFCK_25M_OE_MASK; /*!< enable PHY 25M refck */ - } else { - ptr->PHY_CFG1 &= ~ESC_PHY_CFG1_REFCK_25M_OE_MASK; /*!< disable PHY 25M refck */ - } -} - -/** - * @brief ESC config eeprom attributes(emulation and size) and peripheral clock - * - * @param[in] ptr ESC base address - * @param[in] config esc_eeprom_clock_config_t - */ -static inline void esc_config_eeprom_and_clock(ESC_Type *ptr, esc_eeprom_clock_config_t *config) -{ - uint32_t gpr_cfg0 = ptr->GPR_CFG0; - - if (config->eeprom_emulation) { - gpr_cfg0 |= ESC_GPR_CFG0_EEPROM_EMU_MASK; - gpr_cfg0 &= ~(ESC_GPR_CFG0_PROM_SIZE_MASK | ESC_GPR_CFG0_I2C_SCLK_EN_MASK); - } else { - gpr_cfg0 &= ~ESC_GPR_CFG0_EEPROM_EMU_MASK; - gpr_cfg0 |= ESC_GPR_CFG0_I2C_SCLK_EN_MASK; - if (config->eeprom_size_over_16kbit) { - gpr_cfg0 |= ESC_GPR_CFG0_PROM_SIZE_MASK; - } else { - gpr_cfg0 &= ~ESC_GPR_CFG0_PROM_SIZE_MASK; - } - } - ptr->GPR_CFG0 = gpr_cfg0; - esc_core_enable_clock(ptr, config->core_clock_en); - esc_phy_enable_clock(ptr, config->phy_refclk_en); -} - -/** - * @brief ESC assign specific function to CTRL signal - * - * @param[in] ptr ESC base address - * @param[in] index CTRL signal index(0-8) - * @param[in] func specific function - * @param[in] invert invert signal - */ -static inline void esc_config_ctrl_signal_function(ESC_Type *ptr, uint8_t index, esc_ctrl_signal_function_t func, bool invert) -{ - ptr->IO_CFG[index] = ESC_IO_CFG_FUNC_ALT_SET(func) | ESC_IO_CFG_INVERT_SET(invert); -} - -/** - * @brief ESC config nmii_link signal source - * - * @param[in] ptr ESC base address - * @param[in] link0_from_io true for signal from configured IO; false for signal from register(GPR_CFG2) value - * @param[in] link1_from_io true for signal from configured IO; false for signal from register(GPR_CFG2) value - * @param[in] link2_from_io true for signal from configured IO; false for signal from register(GPR_CFG2) value - */ -static inline void esc_config_nmii_link_source(ESC_Type *ptr, bool link0_from_io, bool link1_from_io, bool link2_from_io) -{ - if (link0_from_io) { - ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK; - } else { - ptr->GPR_CFG2 &= ~ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK; - ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK0_GPR_MASK; /* config GRP to indicate LINK0 is invalid by default */ - } - - if (link1_from_io) { - ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK; - } else { - ptr->GPR_CFG2 &= ~ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK; - ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK1_GPR_MASK; /* config GRP to indicate LINK1 is invalid by default */ - } - - if (link2_from_io) { - ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK; - } else { - ptr->GPR_CFG2 &= ~ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK; - ptr->GPR_CFG2 |= ESC_GPR_CFG2_NMII_LINK2_GPR_MASK; /* config GRP to indicate LINK2 is invalid by default */ - } -} - -/* config ESC reset request source: ESC core or GRP_REG value */ -/** - * @brief ESC config reset signal source - * - * @param[in] ptr ESC base address - * @param[in] reset_from_ecat_core true for reset signal from ecat core; false for reset signal from register(GPR_CFG1) value - */ -static inline void esc_config_reset_source(ESC_Type *ptr, bool reset_from_ecat_core) -{ - if (reset_from_ecat_core) { - ptr->GPR_CFG1 |= ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK; - } else { - ptr->GPR_CFG1 &= ~ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK; - } -} - -/** - * @brief ESC generate reset signal to ESC_RESET interrupt and RESET_OUT pin - * @note the reset signal source should be configured in esc_config_reset_source before - * - * @param[in] ptr ESC base address - */ -static inline void esc_pdi_reset(ESC_Type *ptr) -{ - ptr->ESC_RST_PDI = 0x52; /* R */ - ptr->ESC_RST_PDI = 0x45; /* E */ - ptr->ESC_RST_PDI = 0x53; /* S */ -} - -/*! - * @brief ESC read PHY register via ESC MII Management Interface - * - * @param[in] ptr ESC base address - * @param[in] phy_addr PHY address. - * @param[in] reg_addr Register address. - * @param[in] data PHY data returned. - */ - -hpm_stat_t esc_mdio_read(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); - -/*! - * @brief ESc write PHY register via ESC MII Management Interface - * - * @param[in] ptr ESC base address - * @param[in] phy_addr PHY address. - * @param[in] reg_addr Register address. - * @param[in] data Write to PHY register. - */ -hpm_stat_t esc_mdio_write(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t data); - -/*! - * @brief ESC check eeprom loading data status - * @note EtherCAT communication is possible even if the EEPROM is blank - * - * @param[in] ptr ESC base address. - * @retval status_success: loding data successfully and correctlly. - * @retval status_esc_eeprom_ack_error: loding data checksum error(eeprom blank). - * @retval status_esc_eeprom_checksum_error: no ack error. - * @retval status_timeout: loding data timeout. - */ -hpm_stat_t esc_check_eeprom_loading(ESC_Type *ptr); - -/*! - * @brief ESC get eeprom cmd, this using in eeprom emulation function - * - * @param[in] ptr ESC base address - * @return uint8_t esc_eeprom_cmd_t. - */ -static inline uint8_t esc_get_eeprom_cmd(ESC_Type *ptr) -{ - return ESC_EEPROM_CTRL_STAT_CMD_GET(ptr->EEPROM_CTRL_STAT); -} - -/*! - * @brief ESC ack eeprom cmd in eeprom emualtion function - * - * @param[in] ptr ESC base address - * @param[in] cmd esc_eeprom_cmd_t - * @param[in] ack_err eeprom ack error occurrred - * @param[in] crc_err eeprom checksum error occurrred - */ -static inline void esc_eeprom_emulation_ack(ESC_Type *ptr, esc_eeprom_cmd_t cmd, bool ack_err, bool crc_err) -{ - uint16_t temp = ESC_EEPROM_CTRL_STAT_CMD_SET(cmd); - if (ack_err) { - temp |= ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK; - } - if (crc_err) { - temp |= ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK; - } - - ptr->EEPROM_CTRL_STAT = temp; -} - -/*! - * @brief ESC get eeprom byte address - * - * @param[in] ptr ESC base address - * @return byte address - */ -static inline uint32_t esc_get_eeprom_byte_address(ESC_Type *ptr) -{ - return (ptr->EEPROM_ADDR) << 1U; -} - -/*! - * @brief ESC get eeprom word(2 bytes) address - * - * @param[in] ptr ESC base address - * @return word address - */ -static inline uint32_t esc_get_eeprom_word_address(ESC_Type *ptr) -{ - return ptr->EEPROM_ADDR; -} - -/*! - * @brief ESC read eeprom data from register, this function is using in eeprom emulation function - * - * @param[in] ptr ESC base address - * @return eeprom data - */ -static inline uint64_t esc_read_eeprom_data(ESC_Type *ptr) -{ - return ptr->EEPROM_DATA; -} - -/*! - * @brief ESC write eeprom data to register, this function is using in eeprom emulation function - * - * @param[in] ptr ESC base address - * @param[in] data eeprom data - */ -static inline void esc_write_eeprom_data(ESC_Type *ptr, uint64_t data) -{ - ptr->EEPROM_DATA = data; -} - -/*! - * @brief ESC config latch0 signal source - * - * @param[in] ptr ESC base address - * @param[in] latch0_from_ntm true for signal from ntm system, false for signal from IO - */ -static inline void esc_config_latch0_source(ESC_Type *ptr, bool latch0_from_ntm) -{ - if (latch0_from_ntm) { - ptr->GPR_CFG1 &= ~ESC_GPR_CFG1_LATCH0_FROM_IO_MASK; - } else { - ptr->GPR_CFG1 |= ESC_GPR_CFG1_LATCH0_FROM_IO_MASK; - } -} - -/*! - * @brief ESC config latch1 signal source - * - * @param[in] ptr ESC base address - * @param[in] latch0_from_trigmux true for signal from trigmux system, false for signal from IO - */ -static inline void esc_config_latch1_source(ESC_Type *ptr, bool latch0_from_trigmux) -{ - if (latch0_from_trigmux) { - ptr->GPR_CFG1 &= ~ESC_GPR_CFG1_LATCH1_FROM_IO_MASK; - } else { - ptr->GPR_CFG1 |= ESC_GPR_CFG1_LATCH1_FROM_IO_MASK; - } -} - - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_ESC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h deleted file mode 100644 index 2c11126c43a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h +++ /dev/null @@ -1,518 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_EWDG_DRV_H -#define HPM_EWDG_DRV_H - -#include "hpm_common.h" -#include "hpm_ewdg_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief EWDG driver APIs - * @defgroup ewdg_interface EWDG driver APIs - * @addtogroup ewdg_interface - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief EWDG error codes - */ -enum { - status_ewdg_tick_out_of_range = MAKE_STATUS(status_group_ewdg, 0), /*!< The tick is out of range */ - status_ewdg_div_out_of_range = MAKE_STATUS(status_group_ewdg, 1), /*!< Clock Divider is out of range */ - status_ewdg_feature_unsupported = MAKE_STATUS(status_group_ewdg, 2), /*!< Feature is not supported */ -}; - -/** - * @brief EWDG Password Definitions - * - * @defgroup ewdg_password_def EWDG Password definitions - * @{ - */ -#define EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT (0xED09U) /*!< Default EWDG Refresh Password */ -#define EWDG_UPDATE_PASSWORD_DEFAULT (0xECF9U) /*!< Default EWDG Update Password */ -#define EWDG_REFRESH_UNLOCK_FIXED_KEY (0x55AAU) /*!< EWDG Unlock Fixed key */ -#define EWDG_REFRESH_KEY (0x5A45524FUL) /*!< EWDG Refresh key */ -/** - * @} - */ - -/** - * @brief EWDG Events - * - * @defgroup ewdg_event EWDG Event definitions - * @{ - */ -#define EWDG_EVENT_PARITY_ERROR (1UL << 6) /*!< Parity Error Event */ -#define EWDG_EVENT_TIMEOUT_RESET (1UL << 5) /*!< Timeout Reset Event */ -#define EWDG_EVENT_TIMEOUT_INTERRUPT (1UL << 4) /*!< Timeout Interrupt Event */ -#define EWDG_EVENT_CFG_REG_UPDATE_UNLOCK_FAIL (1UL << 3) /*!< Update Unlock Fail Event */ -#define EWDG_EVENT_CFG_REG_UPDATE_VIOLATION (1UL << 2) /*!< Update Violation Event */ -#define EWDG_EVENT_REFRESH_UNLOCK_FAIL (1UL << 1) /*!< Refresh Unlock Fail Event */ -#define EWDG_EVENT_REFRESH_VIOLATION (1UL << 0) /*!< Refresh Violation Event */ -/** - * @} - */ - -/** - * @brief EWDG Interrupts - * @defgroup ewdg_interrupt EWDG interrupt definitions - * @{ - */ -#define EWDG_INT_PARITY_FAIL (1UL << 2) /*!< Parity Error Interrupt */ -#define EWDG_INT_CTRL_REG_UNLOCK_FAIL (1UL << 4) /*!< Unlock Control Register Fail Interrupt */ -#define EWDG_INT_CTRL_REG_UPDATE_FAIL (1UL << 6) /*!< Update Control Register Violation Interrupt */ -#define EWDG_INT_TIMEOUT (1UL << 16) /*!< Watchdog Timeout Interrupt */ -#define EWDG_INT_REFRESH_UNLOCK_FAIL (1UL << 20) /*!< Refresh Register Unlock Fail interrupt */ -#define EWDG_INT_REFRESH_VIOLATION (1UL << 22) /*!< Refresh Register Violation interrupt */ -/*! All Interrupt masks */ -#define EWDG_INT_ALL (EWDG_INT_PARITY_FAIL | EWDG_INT_CTRL_REG_UNLOCK_FAIL | EWDG_INT_CTRL_REG_UPDATE_FAIL | \ - EWDG_INT_TIMEOUT | EWDG_INT_REFRESH_UNLOCK_FAIL | EWDG_INT_REFRESH_VIOLATION) -/** - * @} - */ - -/** - * @brief EWDG Resets - * - * @defgroup ewdg_reset_source EWDG reset source definitions - * @{ - */ -#define EWDG_RST_PARITY_FAIL (1UL << 3) /*!< Parity Error Reset */ -#define EWDG_RST_CTRL_REG_UNLOCK_FAIL (1UL << 5) /*!< Unlock Control Register Fail Reset */ -#define EWDG_RST_CTRL_REG_UPDATE_FAIL (1UL << 7) /*!< Update Control Register Violation Reset */ -#define EWDG_RST_TIMEOUT (1UL << 17) /*!< Watchdog Timeout Reset */ -#define EWDG_RST_REFRESH_UNLOCK_FAIL (1UL << 21) /*!< Refresh Register Unlock Fail Reset */ -#define EWDG_RST_REFRESH_VIOLATION (1UL << 23) /*!< Refresh Register Violation Reset */ -/*! All Reset masks */ -#define EWDG_RST_ALL (EWDG_RST_PARITY_FAIL | EWDG_RST_CTRL_REG_UNLOCK_FAIL | EWDG_RST_CTRL_REG_UPDATE_FAIL | \ - EWDG_RST_TIMEOUT | EWDG_RST_REFRESH_UNLOCK_FAIL | EWDG_RST_REFRESH_VIOLATION) -/** - * @} - */ - - - -/** - * @brief EWDG Refresh Unlock Methods - */ -typedef enum { - /*! Use the Unlock Password directly */ - ewdg_refresh_unlock_method_password = 0, - /*! Use password[14:0] | password[15] */ - ewdg_refresh_unlock_method_ring_left_shift_password_by_1 = 1, - /*! Use fixed key: 0x55AA */ - ewdg_refresh_unlock_method_fixed_key = 2, - /*! Use last_password[14:0] | (last_password[15] ^ password[0]) */ - ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 = 3, - /*! Max allowed range */ - ewdg_refresh_unlock_method_max = ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0 -} ewdg_refresh_unlock_method_t; - -/** - * @brief EWDG Clock source for internal counter - */ -typedef enum { - ewdg_cnt_clk_src_bus_clk, /*!< Clock is from BUS clock */ - ewdg_cnt_clk_src_ext_osc_clk, /*!< Clock is from External OSC */ -} ewdg_cnt_clk_sel_t; - -/** - * @brief EWDG Lower Window Limitations - */ -typedef enum { - /*! Refresh should be issued after 8/16 of timeout period */ - ewdg_window_lower_timeout_period_8_div_16 = 0, - /*! Refresh should be issued after 10/16 of timeout period */ - ewdg_window_lower_timeout_period_10_div_16 = 1, - /*! Refresh should be issued after 12/16 of timeout period */ - ewdg_window_lower_timeout_period_12_div_16 = 2, - /*! Refresh should be issued after 14/16 of timeout period */ - ewdg_window_lower_timeout_period_14_div_16 = 3, - /*! Maximum allowed limit value */ - ewdg_window_lower_timeout_period_max = ewdg_window_lower_timeout_period_14_div_16 -} ewdg_window_low_limit_t; - -/** - * @brief EWDG Upper Window Limitations - * - * The Actual Upper Window = Lower Window + Upper Window Limit - */ -typedef enum { - ewdg_window_upper_timeout_period_8_div_16 = 0, /*!< 8/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_1_div_16 = 1, /*!< 1/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_2_div_16 = 2, /*!< 2/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_3_div_16 = 3, /*!< 3/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_4_div_16 = 4, /*!< 4/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_5_div_16 = 5, /*!< 5/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_6_div_16 = 6, /*!< 6/16 of timeout_reset_val */ - ewdg_window_upper_timeout_period_7_div_16 = 8, /*!< 7/16 of timeout_reset_val */ - /*! Maximum allowed upper limit */ - ewdg_window_upper_timeout_period_max = ewdg_window_upper_timeout_period_7_div_16 -} ewdg_window_upper_limit_t; - -typedef enum { - ewdg_low_power_mode_halt = 0, /*!< Watchdog is halted in low power mode */ - ewdg_low_power_mode_work_clock_normal = 1, /*!< Watchdog is will work with normal clock in low power mode */ -} ewdg_low_power_mode_t; - -/*** - * @brief EWDG Function Control Configurations - */ -typedef struct { - ewdg_cnt_clk_sel_t cnt_clk_sel; /*!< Clock source for counter */ - bool enable_window_mode; /*!< Enable window mode */ - ewdg_window_low_limit_t window_lower_limit; /*!< Lower limit of the window */ - /*! Upper limit of the window - * The real upper window = (window_lower_limit/8 + window_upper_limit/16) * timeout_reset_val - */ - ewdg_window_upper_limit_t window_upper_limit; - - bool enable_config_lock; /*!< Enable Lock for the Configuration Registers */ - - bool enable_refresh_period; /*!< Enable Refresh period */ - bool enable_refresh_lock; /*!< Enable Refresh lock */ - ewdg_refresh_unlock_method_t refresh_unlock_method; /*!< Method to unlock REFRESH_REG */ - - bool enable_overtime_self_clear; /*!< Enable Over time self clear */ - - bool keep_running_in_debug_mode; /*!< Keep running even in debug mode */ - ewdg_low_power_mode_t low_power_mode; /*!< Watchdog behavior in low power mode */ - /*! - * Select timeout value type - * - true: use the IP-level value (in terms of EWDG counter ticks) - * - false: Use the user friendly timeout value (in terms of microseconds) - */ - bool use_lowlevel_timeout; - union { - struct { - uint32_t timeout_interrupt_us; /*!< Timeout value for interrupt (in terms of microseconds) */ - uint32_t timeout_reset_us; /*!< Timeout value for reset (in terms of microseconds */ - }; - struct { - uint32_t timeout_interrupt_val; /*!< Timeout value for interrupt (in terms of counter ticks) */ - /*! Timeout value for reset (in terms of counter ticks - * Note: timeout_reset_val must > timeout_interrupt_val - */ - uint32_t timeout_reset_val; - uint32_t clock_div_by_power_of_2; /*!< Power of 2 Divider */ - }; - }; - - uint16_t refresh_period_in_bus_cycles; /*!< Refresh period */ - uint16_t refresh_unlock_password; /*!< Password for unlocking write to REFRESH_REG */ - - uint16_t ctrl_reg_update_password; /*!< Update Password */ - uint16_t ctrl_reg_update_period_bus_clk_x_128; /*!< Update Period */ -} ewdg_func_ctrl_config_t; - -/** - * @brief EWDG Reset and Interrupt Configurations - */ -typedef struct { - bool enable_ctrl_parity_fail_interrupt; /*!< Enable Parity Fail Interrupt */ - bool enable_ctrl_parity_fail_reset; /*!< Enable Parity Fail Reset */ - bool enable_ctrl_unlock_fail_interrupt; /*!< Enable Control Register Unlock Fail Interrupt */ - bool enable_ctrl_unlock_fail_reset; /*!< Enable Control Register Unlock Fail Reset */ - bool enable_ctrl_update_violation_interrupt; /*!< Enable Control Register Update Violation Interrupt */ - bool enable_ctrl_update_violation_reset; /*!< Enable Control Register Update Violation Reset */ - bool enable_timeout_interrupt; /*!< Enable Timeout Interrupt */ - bool enable_timeout_reset; /*!< Enable Timeout Reset */ - bool enable_refresh_unlock_fail_interrupt; /*!< Enable Refresh Unlock Fail Interrupt */ - bool enable_refresh_unlock_fail_reset; /*!< Enable Refresh Unlock Fail Reset */ - bool enable_refresh_violation_interrupt; /*!< Enable Refresh Violation Interrupt */ - bool enable_refresh_violation_reset; /*!< Enable Refresh Violation Reset */ -} ewdg_interrupt_reset_config_t; - -/** - * @brief Enhanced Watchdog Configuration Structure - */ -typedef struct { - ewdg_interrupt_reset_config_t int_rst_config; /*!< Error Control Configuration */ - ewdg_func_ctrl_config_t ctrl_config; /*!< Function Control Configuration */ - bool enable_watchdog; /*!< Enable Watchdog */ - uint32_t cnt_src_freq; /*!< Frequency for the clock used as the counter clock source */ -} ewdg_config_t; - -/** - * @brief Check whether the Control Registers are locked - * - * @param [in] ptr EWDG base - * - * @retval true Control Registers are locked - * @retval false Control Registers are unlocked - */ -static inline bool ewdg_is_ctrl_reg_locked(EWDG_Type *ptr) -{ - return ((ptr->CTRL0 & EWDG_CTRL0_CFG_LOCK_MASK) != 0U); -} - -/** - * @brief Get the Divider for Counter Clock - * - * @param [in] ptr EWDG base - * - * @return divider value - */ -static inline uint32_t ewdg_get_count_clk_divider(EWDG_Type *ptr) -{ - return (1UL << EWDG_CTRL0_DIV_VALUE_GET(ptr->CTRL0)); -} - -/** - * @brief Check whether the Refresh register is locked - * - * @param [in] ptr EWDG base - * - * @retval true Control Registers are locked - * @retval false Control Registers are unlocked - */ -static inline bool ewdg_is_refresh_locked(EWDG_Type *ptr) -{ - return ((ptr->CTRL0 & EWDG_CTRL0_REF_LOCK_MASK) != 0U); -} - -/** - * @brief Unlock Write to Control Registers - * - * @param [in] ptr EWDG base - */ -static inline void ewdg_unlock_ctrl_regs(EWDG_Type *ptr) -{ - uint32_t ctrl_update_prot = ptr->CFG_PROT; - ptr->CFG_PROT = ctrl_update_prot; -} - -/** - * @brief Write Refresh Magic Number to EWDG Refresh register - * @param [in] ptr EWDG base - */ -static inline void ewdg_write_refresh_reg(EWDG_Type *ptr) -{ - ptr->WDT_REFRESH_REG = EWDG_REFRESH_KEY; -} - -/** - * @brief Get the Timeout Reset ticks - * @param [in] ptr EWDG base - * @return Timeout Reset ticks - */ -static inline uint32_t ewdg_get_timeout_reset_ticks(EWDG_Type *ptr) -{ - return ptr->OT_RST_VAL; -} - -#if !defined(EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) || (EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1) -/** - * @brief Get the Timeout Interrupt ticks - * @param [in] ptr EWDG base - * @return Timeout Interrupt ticks - */ -static inline uint32_t ewdg_get_timeout_interrupt_ticks(EWDG_Type *ptr) -{ - return ptr->OT_INT_VAL; -} -#endif - -/** - * @brief Clear Interrupt Status for EWDG - * - * @note The TIMEOUT_INT_EVENT cannot be cleared directly, it needs to be cleared by the refresh sequence - * - * @param [in] ptr EWDG base - * @param [in] mask Status Mask Bits, @ref ewdg_event - */ -static inline void ewdg_clear_status_flags(EWDG_Type *ptr, uint32_t mask) -{ - ptr->WDT_STATUS = mask; -} - -/** - * @brief Get the Status of EWDG - * - * @param [in] ptr EWDG base - * - * @return STATUS register value - */ -static inline uint32_t ewdg_get_status_flags(EWDG_Type *ptr) -{ - return ptr->WDT_STATUS; -} - -/** - * @brief Get the Refresh Unlock Mechanism - * @param [in] ptr EWDG base - * @return EWDG refresh unlock method - */ -static inline ewdg_refresh_unlock_method_t ewdg_get_refresh_unlock_method(EWDG_Type *ptr) -{ - return (ewdg_refresh_unlock_method_t) (EWDG_CTRL0_REF_UNLOCK_MEC_GET(ptr->CTRL0)); -} - -/** - * @brief Enable EWDG - * - * This function enables the functionality of the EWDG and start the watchdog timer - * - * @param [in] ptr EWDG base - * - * @note Once the EWDG is enabled, - * - if the software needs to update the control register, the update unlock must be - * performed first if the control register lock is enabled. - * - */ -void ewdg_enable(EWDG_Type *ptr); - - -/** - * @brief Disable EWDG - * @param [in] ptr EWDG base - */ -void ewdg_disable(EWDG_Type *ptr); - -/** - * @brief Initialize the Control function for EWDG - * - * @param [in] ptr EWDG base - * @param [in] config Control Function Configuration - * @param [in] cnt_src_freq Source frequency for EWDG counter - * - * @retval status_invalid_argument Invalid argument was detected - * @retval status_success No error happened - */ -hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq); - -/** - * @brief Initialize the Error function for EWDG - * - * @param [in] ptr EWDG base - * @param [in] config Error Function Configuration - * - * @retval status_invalid_argument Invalid argument was detected - * @retval status_success No error happened - */ -hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config); - -/** - * @brief Get default configuration for EWDG - * @param [in] ptr EWDG base - * @param [out] config EWDG Configuration - */ -void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config); - -/** - * @brief Initialize the EWDG module - * - * @param [in] ptr EWDG base - * @param [in] config EWDG configuration - * - * @retval status_invalid_argument Invalid argument was detected - * @retval status_success No error happened - */ -hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config); - -/** - * @brief Unlock the write to refresh register - * - * @param [in] ptr EWDG base - * - * @retval status_invalid_argument Invalid argument was detected - * @retval status_success No error happened - */ -hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr); - -/** - * @brief Refresh EWDG - * - * @param [in] ptr EWDG base - * - * @retval status_invalid_argument Invalid argument was detected - * @retval status_success No error happened - */ -hpm_stat_t ewdg_refresh(EWDG_Type *ptr); - -/** - * @brief Get the Divided Counter Clock Frequency for EWDG - * - * @param [in] ptr EWDG base - * @param [in] src_clk_freq Source clock of the Counter clock - * - * @return divided Counter clock Frequency - */ -uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq); - -/** - * @brief Convert the timeout in terms of microseconds to the timeout in terms of timeout ticks - * - * @param [in] src_clk_freq Clock Frequency of the counter clock source - * @param [in] timeout_us Timeout in terms of microseconds - * - * @return timeout in terms of counter clock ticks - */ -uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us); - -/** - * @brief Convert the timeout in terms of timeout ticks to the timeout in terms of microseconds - * - * @param [in] ptr EWDG base - * @param [in] src_clk_freq Clock Frequency of the counter clock source - * @param [in] timeout_ticks Timeout in terms of ticks - * - * @return timeout in terms of counter clock ticks - */ -uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t src_clk_freq, uint32_t timeout_ticks); - -/** - * @brief Enable EWDG interrupt - * @param [in] ptr EWDG base - * @param [in] mask Interrupt Mask, valid value refer to @ref ewdg_interrupt - */ -void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask); - -/** - * @brief Disable EWDG interrupt - * @param [in] ptr EWDG base - * @param [in] mask Interrupt Mask, valid value refer to @ref ewdg_interrupt - */ -void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask); - -/** - * @brief Enable EWDG Reset - * @param [in] ptr EWDG base - * @param [in] mask Reset Mask, valid value refer to @ref ewdg_reset_source - */ -void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask); - -/** - * @brief Disable EWDG Reset - * @param [in] ptr EWDG base - * @param [in] mask Reset Mask, valid value refer to @ref ewdg_reset_source - */ -void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask); - -/** - * @brief Switch the EWDG clock source - * @param [in] ptr EWDG base - * @param [in] clk_sel Clock source selection for EWDG counter - */ -void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel); - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_EWDG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h deleted file mode 100644 index 15de4c69be7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_FEMC_DRV_H -#define _HPM_FEMC_DRV_H -#include "hpm_femc_regs.h" - -/** - * @brief femc driver APIs - * @defgroup dram_interface femc driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -#define FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE (8UL) -/* @brief femc sdram column address bit width */ -#define FEMC_SDRAM_COLUMN_ADDR_12_BITS (0U) -#define FEMC_SDRAM_COLUMN_ADDR_11_BITS (1U) -#define FEMC_SDRAM_COLUMN_ADDR_10_BITS (2U) -#define FEMC_SDRAM_COLUMN_ADDR_9_BITS (3U) -#define FEMC_SDRAM_COLUMN_ADDR_8_BITS (4U) -/* @brief cas latency */ -#define FEMC_SDRAM_CAS_LATENCY_1 (1U) -#define FEMC_SDRAM_CAS_LATENCY_2 (2U) -#define FEMC_SDRAM_CAS_LATENCY_3 (3U) -/* @brief iomux options */ -#define FEMC_IO_MUX_NOT_USED (0U) -#define FEMC_IO_MUX_CSX0 (1U) -#define FEMC_IO_MUX_CSX1 (2U) -#define FEMC_IO_MUX_CSX2 (3U) -#define FEMC_IO_MUX_CSX3 (4U) -#define FEMC_IO_MUX_RDY (5U) -/* @brief sdram bank number */ -#define FEMC_SDRAM_BANK_NUM_4 (0U) -#define FEMC_SDRAM_BANK_NUM_2 (1U) -/* @brief chip select */ -#define FEMC_SDRAM_CS0 (0U) -#define FEMC_SDRAM_CS1 (1U) -/* @brief sdram port size */ -#define FEMC_SDRAM_PORT_SIZE_8_BITS (0U) -#define FEMC_SDRAM_PORT_SIZE_16_BITS (1U) -#define FEMC_SDRAM_PORT_SIZE_32_BITS (2U) - -#define FEMC_AXI_Q_COUNT (2U) -#define FEMC_AXI_Q_A (0U) -#define FEMC_AXI_Q_B (1U) -/* @brief DQS option */ -#define FEMC_DQS_INTERNAL (0U) -#define FEMC_DQS_FROM_PAD (1U) - -#define FEMC_BR_COUNT (2U) - -#define FEMC_CMD_KEY FEMC_IPCMD_KEY_SET(0xA55A) -#define FEMC_CMD_WRITE_FLAG (1UL << 31) -#define FEMC_CMD_SDRAM_READ (0x8U) -#define FEMC_CMD_SDRAM_WRITE (FEMC_CMD_WRITE_FLAG | 0x9U) -#define FEMC_CMD_SDRAM_MODE_SET (FEMC_CMD_WRITE_FLAG | 0xAU) -#define FEMC_CMD_SDRAM_ACTIVE (0xBU) -#define FEMC_CMD_SDRAM_AUTO_REFRESH (0xCU) -#define FEMC_CMD_SDRAM_SELF_REFRESH (0xDU) -#define FEMC_CMD_SDRAM_PRECHARGE (0xEU) -#define FEMC_CMD_SDRAM_PRECHARGE_ALL (0xFU) - -/* @brief sram address mode */ -#define FEMC_SRAM_AD_MUX_MODE (0U) -#define FEMC_SRAM_AD_NONMUX_MODE (3U) - -/* @brief sram adv hold state */ -#define FEMC_SRAM_ADV_HOLD_HIGH (0U) -#define FEMC_SRAM_ADV_HOLD_LOW (1U) - -/* @brief sram adv polarity */ -#define FEMC_SRAM_ADV_ACTIVE_LOW (0U) -#define FEMC_SRAM_ADV_ACTIVE_HIGH (1U) - -/* @brief sram port size */ -#define FEMC_SRAM_PORT_SIZE_8_BITS (0U) -#define FEMC_SRAM_PORT_SIZE_16_BITS (1U) - -/* @brief IO_CSX selection */ -#define FEMC_IO_CSX_SDRAM_CS1 (1U) -#define FEMC_IO_CSX_SRAM_CE (6U) - -/** - * @brief Structure for specifying the configuration of AXI queue weight - */ -typedef struct { - bool enable; /**< Enable AXI weight setting flag */ - uint8_t qos; - uint8_t age; - uint8_t slave_hit_wo_rw; - uint8_t slave_hit; /**< only available for queue A */ - uint8_t page_hit; /**< only available for queue B */ - uint8_t bank_rotation; /**< only available for queue B */ -} femc_axi_q_weight_t; - -/** - * @brief Structure for specifying the configuration of SDRAM - */ -typedef struct { - uint32_t base_address; /**< external SDRAM base address */ - uint32_t size_in_byte; /**< external SDRAM size in byte */ - uint32_t refresh_count; /**< referesh count */ - uint8_t col_addr_bits; /**< column address bit count */ - uint8_t cas_latency; /**< CAS latency */ - uint8_t cs; /**< chip select */ - uint8_t cs_mux_pin; /**< chip select mux */ - uint8_t bank_num; /**< bank number */ - uint8_t prescaler; /**< presecaler */ - uint8_t port_size; /**< SDRAM port size */ - uint8_t burst_len_in_byte; /**< 1/2/4/8 bytes */ - uint8_t cke_off_in_ns; - uint8_t act_to_precharge_in_ns; /**< Tras */ - uint8_t precharge_to_act_in_ns; /**< Trp */ - uint8_t act_to_rw_in_ns; /**< Trcd */ - uint8_t act_to_act_in_ns; /**< Trrd */ - uint8_t refresh_to_refresh_in_ns; /**< Trc */ - uint8_t write_recover_in_ns; /**< Twr */ - uint8_t self_refresh_recover_in_ns; /**< Txsr */ - uint8_t refresh_recover_in_ns; /**< Trc */ - uint8_t refresh_in_ms; /**< Tref */ - uint8_t idle_timeout_in_ns; - uint8_t cmd_data_width; - uint8_t auto_refresh_count_in_one_burst; - bool delay_cell_disable; /**< Delay cell disable */ - uint8_t delay_cell_value; /**< Delay cell value */ -} femc_sdram_config_t; - -/** - * @brief Structure for specifying the configuration of SRAM - */ -typedef struct { - uint32_t base_address; /**< external SRAM base address */ - uint32_t size_in_byte; /**< external SRAM size in byte */ - uint8_t address_mode; /**< address mode */ - uint8_t port_size; /**< port size */ - uint8_t adv_hold_state; /**< adv hold level */ - uint8_t adv_polarity; /**< adv polarity */ - uint8_t oeh_in_ns; /**< OE high time */ - uint8_t oel_in_ns; /**< OE low time */ - uint8_t weh_in_ns; /**< WE high time */ - uint8_t wel_in_ns; /**< WE low time */ - uint8_t ah_in_ns; /**< address hold time */ - uint8_t as_in_ns; /**< address setup time */ - uint8_t ceh_in_ns; /**< chip enable hold time */ - uint8_t ces_in_ns; /**< chip enable setup time */ -} femc_sram_config_t; - -/** - * @brief Structure for specifying the configuration of FEMC - */ -typedef struct { - uint8_t dqs; /**< DQS setting */ - uint8_t cmd_timeout; /**< command timeout */ - uint8_t bus_timeout; /**< bus timeout */ - femc_axi_q_weight_t axi_q_weight[FEMC_AXI_Q_COUNT]; -} femc_config_t; - -/** - * @brief Structure for FEMC command - */ -typedef struct { - uint32_t opcode; - uint32_t data; -} femc_cmd_t; - -/* - * @brief FEMC specific status - */ -enum { - status_femc_cmd_err = MAKE_STATUS(status_group_femc, 1), -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief femc enable - * - * Enable FEMC - * - * @param[in] ptr FEMC base address - */ -static inline void femc_enable(FEMC_Type *ptr) -{ - ptr->CTRL &= ~FEMC_CTRL_DIS_MASK; -} - -/** - * @brief femc disable - * - * Disable FEMC - * - * @param[in] ptr FEMC base address - */ -static inline void femc_disable(FEMC_Type *ptr) -{ - while ((ptr->STAT0 & (uint32_t) FEMC_STAT0_IDLE_MASK) == 0) { - } - ptr->CTRL |= FEMC_CTRL_DIS_MASK; -} - -/** - * @brief femc software reset - * - * Perform software reset - * - * @param[in] ptr FEMC base address - */ -static inline void femc_sw_reset(FEMC_Type *ptr) -{ - ptr->CTRL = FEMC_CTRL_RST_MASK; - while ((ptr->CTRL & (uint32_t) FEMC_CTRL_RST_MASK) != 0) { - } -} - -/** - * @brief femc get default config - * - * Get FEMC default parameters - * - * @param[in] ptr FEMC base address - * @param[out] config femc_config_t address - */ -void femc_default_config(FEMC_Type *ptr, femc_config_t *config); - -/** - * @brief femc init controller - * - * Initialize FEMC with give femc_config_t - * - * @param[in] ptr FEMC base address - * @param[in] config femc_config_t to initialize femc - */ -void femc_init(FEMC_Type *ptr, femc_config_t *config); - -/** - * @brief femc get typical sdram config - * - * Fill out the structure of femc_sdram_config_t with typical SDRAM parameters which should work - * with most SDRAMs. - * - * @param[in] ptr FEMC base address - * @param[out] config femc_sdram_config_t sdram configuration struction to config femc - */ -void femc_get_typical_sdram_config(FEMC_Type *ptr, femc_sdram_config_t *config); - -/** - * @brief femc config sdram - * - * Configure FEMC controlling external SDRAM using parameters specified in femc_sdram_config_t - * - * @param[in] ptr FEMC base address - * @param[in] clk_in_hz femc source clock frequency in Hz - * @param[in] config femc_sdram_config_t sdram configuration struction to config femc - */ -hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_config_t *config); - -/** - * @brief femc get typical sram config - * - * Fill out the structure of femc_sram_config_t with typical SRAM parameters which should work - * with most SRAMs. - * - * @param[in] ptr FEMC base address - * @param[out] config femc_sdram_config_t sdram configuration struction to config femc - */ -void femc_get_typical_sram_config(FEMC_Type *ptr, femc_sram_config_t *config); - -/** - * @brief femc config sram - * - * Configure FEMC controlling external SRAM using parameters specified in femc_sram_config_t - * - * @param[in] ptr FEMC base address - * @param[in] clk_in_hz femc source clock frequency in Hz - * @param[in] config femc_sram_config_t sram configuration struction to config femc - */ -hpm_stat_t femc_config_sram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sram_config_t *config); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* _HPM_FEMC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h deleted file mode 100644 index 93e5b671a07..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_FFA_DRV_H -#define HPM_FFA_DRV_H - -#include "hpm_common.h" -#include "hpm_ffa_regs.h" -#include "hpm_soc_ip_feature.h" - -/** - * @brief FFA driver APIs - * @defgroup ffa_interface FFA driver APIs - * @ingroup ffa_interfaces - * @{ - * - */ - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ -/** - * @brief Operation commands supported by FFA - */ -#define FFA_OPCMD_FIR (0U) /* !< FIR operation command index */ -#define FFA_OPCMD_FFT (2U) /* !< FFT operation command index */ - -/** - * @brief Data type supported by FFA - */ -#define FFA_DATA_TYPE_REAL_Q31 (0U) /* !< FFA Data type: Real Q31 */ -#define FFA_DATA_TYPE_REAL_Q15 (1U) /* !< FFA Data type: Real Q15 */ -#define FFA_DATA_TYPE_COMPLEX_Q31 (2U) /* !< FFA Data type: Complex Q31 */ -#define FFA_DATA_TYPE_COMPLEX_Q15 (3U) /* !< FFA Data type: Complex Q15 */ -#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32 -#define FFA_DATA_TYPE_COMPLEX_FP32 (4U) /* !< FFA Data type: Complex Q15 */ -#define FFA_DATA_TYPE_REAL_FP32 (5U) /* !< FFA Data type: Complex Q15 */ -#endif - -/** - * @brief FFA Q31 data type definition - */ -typedef int32_t ffa_q31_t; - -/** - * @brief FFA Q15 data type definition - */ -typedef int16_t ffa_q15_t; - -/** - * @brief FFA complex Q31 data type definition - */ -typedef struct { - ffa_q31_t real; - ffa_q31_t image; -} ffa_complex_q31_t; - -/** - * @brief FFA complex Q15 data type definition - */ -typedef struct { - ffa_q15_t real; - ffa_q15_t image; -} ffa_complex_q15_t; - -/** - * @brief FFT transform context - */ -typedef struct { - uint16_t is_ifft; /* !< Is Inverse FFT transform */ - uint8_t src_data_type; /* !< Source data type */ - uint8_t dst_data_type; /* !< Destination date type */ - uint32_t num_points; /* !< Number of points */ - const void *src; /* !< Source data buffer */ - void *dst; /* !< Destination Data buffer */ - uint32_t interrupt_mask; /* !< Interrupt mask */ -} fft_xfer_t; - -/** - * @brief FIR transform context - */ -typedef struct { - uint16_t data_type; /* !< Data type */ - uint16_t coef_taps; /* !< Coefficient taps */ - uint32_t input_taps; /* !< Input data taps */ - const void *src; /* !< Source data buffer */ - const void *coeff; /* !< Coefficient data buffer */ - void *dst; /* !< Destination data buffer */ - uint32_t interrupt_mask; /* !< Interrupt mask */ -} fir_xfer_t; - -/** - * @brief FFA error codes - */ -enum { - status_ffa_fir_overflow = MAKE_STATUS(status_group_ffa, 0), /* !< FIR overflow */ - status_ffa_fft_overflow = MAKE_STATUS(status_group_ffa, 1), /* !< FFR overflow */ - status_ffa_write_error = MAKE_STATUS(status_group_ffa, 2), /* !< FFA write error */ - status_ffa_read_next_error = MAKE_STATUS(status_group_ffa, 3), /* !< FFA read next data error */ - status_ffa_read_error = MAKE_STATUS(status_group_ffa, 4), /*!< FFA read error */ -}; - -#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32 -typedef enum { - input_data = 0, - output_data = 1, - coeff_data = 2 -} ffa_fp32_status_source_t; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Enable FFA module and start an specified FFA operation - * - * @param [in] ptr FFA base address - */ -static inline void ffa_enable(FFA_Type *ptr) -{ - ptr->CTRL = (ptr->CTRL & ~FFA_CTRL_SFTRST_MASK) | FFA_CTRL_EN_MASK; -} - -/** - * @brief Stop FFA module - * - * @param [in] ptr FFA base address - */ -static inline void ffa_disable(FFA_Type *ptr) -{ - ptr->CTRL = (ptr->CTRL & ~FFA_CTRL_EN_MASK) | FFA_CTRL_SFTRST_MASK; -} - -/** - * @brief Get FFA status - * - * @param [in] ptr FFA base address - * @return FFA status register value - */ -static inline uint32_t ffa_get_status(FFA_Type *ptr) -{ - return ptr->STATUS; -} - -/** - * @brief Enable FFA Interrupt - * - * @param [in] ptr FFA base address - * @param [in] mask FFA interrupt mask - */ -static inline void ffa_enable_interrupt(FFA_Type *ptr, uint32_t mask) -{ - ptr->INT_EN |= mask; -} - -/** - * @brief Disable FFA interrupt - * - * @param [in] ptr FFA base address - * @param [in] mask FFA interrupt mask - */ -static inline void ffa_disable_interrupt(FFA_Type *ptr, uint32_t mask) -{ - ptr->INT_EN &= ~mask; -} - -#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32 - -static inline void ffa_enable_fp32_interrupt(FFA_Type *ptr, uint32_t mask) -{ - ptr->FP_CTRL |= mask; -} - -static inline void ffa_disable_fp32_interrupt(FFA_Type *ptr, uint32_t mask) -{ - ptr->FP_CTRL &= ~mask; -} - -static inline void ffa_set_fp_status_source(FFA_Type *ptr, ffa_fp32_status_source_t source) -{ - ptr->FP_CTRL = FFA_FP_CTRL_EXP_ST_SEL_SET(source); -} - -static inline void ffa_enable_fp_bias(FFA_Type *ptr) -{ - ptr->FP_CTRL |= FFA_FP_CTRL_OPT_BIAS_EXP_MASK; -} - -static inline void ffa_disable_fp_bias(FFA_Type *ptr) -{ - ptr->FP_CTRL &= ~FFA_FP_CTRL_OPT_BIAS_EXP_MASK; -} - -static inline void ffa_set_coef_max_index(FFA_Type *ptr, uint8_t max) -{ - ptr->FP_CTRL = (ptr->FP_CTRL & ~FFA_FP_CTRL_COEF_MAX_MASK) | FFA_FP_CTRL_COEF_MAX_SET(max); -} - -static inline void ffa_set_output_max_index(FFA_Type *ptr, uint8_t max) -{ - ptr->FP_CTRL = (ptr->FP_CTRL & ~FFA_FP_CTRL_OUT_MAX_MASK) | FFA_FP_CTRL_OUT_MAX_SET(max); -} - -static inline void ffa_set_input_max_index(FFA_Type *ptr, uint8_t max) -{ - ptr->FP_CTRL = (ptr->FP_CTRL & ~FFA_FP_CTRL_IN_MAX_MASK) | FFA_FP_CTRL_IN_MAX_SET(max); -} - -static inline uint32_t ffa_get_fp_status(FFA_Type *ptr) -{ - return ptr->FP_ST; -} - -#endif - -/** - * @brief Start an FFT operation - * - * @param [in] ptr FFA base address - * @param [in] fft_xfer FFT transform context - */ -void ffa_start_fft(FFA_Type *ptr, fft_xfer_t *fft_xfer); - -/** - * @brief Start an FIR operation - * - * @param [in] ptr FFA base address - * @param [in] fir_xfer FIR transform context - */ -void ffa_start_fir(FFA_Type *ptr, fir_xfer_t *fir_xfer); - -/** - * @brief Perform FFT transformation in blocking mode - * - * @param [in] ptr FFA base address - * @param [in, out] fft_xfer FFT transform context - * @return FFT operation result - */ -hpm_stat_t ffa_calculate_fft_blocking(FFA_Type *ptr, fft_xfer_t *fft_xfer); - -/** - * @brief Perform FIR transform in blocking mode - * - * @param [in] ptr FFA base address - * @param [in, out] fir_xfer FIR transform context - * @return FIR operation result - */ -hpm_stat_t ffa_calculate_fir_blocking(FFA_Type *ptr, fir_xfer_t *fir_xfer); - - -#ifdef __cplusplus -} -#endif -/** - * @} - * - */ - - -#endif /* HPM_FFA_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h deleted file mode 100644 index d0be414a14e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpio_drv.h +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIO_DRV_H -#define HPM_GPIO_DRV_H - -#include "hpm_common.h" -#include "hpm_gpio_regs.h" -#include "hpm_soc_feature.h" - -#ifndef PORT_PIN_COUNT -#define PORT_PIN_COUNT (32U) -#endif -#define GPIO_GET_PORT_INDEX(x) (x / PORT_PIN_COUNT) -#define GPIO_GET_PIN_INDEX(x) (x % PORT_PIN_COUNT) - -/** - * - * @brief GPIO driver APIs - * @defgroup gpio_interface GPIO driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Interrupt trigger type - */ -typedef enum gpio_interrupt_trigger { - gpio_interrupt_trigger_level_high = 0, - gpio_interrupt_trigger_level_low, - gpio_interrupt_trigger_edge_rising, - gpio_interrupt_trigger_edge_falling, -#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) - gpio_interrupt_trigger_edge_both, -#endif -} gpio_interrupt_trigger_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Read target pin level - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * - * @return Pin status mask - */ -static inline uint8_t gpio_read_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - return (ptr->DI[port].VALUE & (1 << pin)) >> pin; -} - -/** - * @brief Read target pin output state - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * - * @return Pin output state - */ -static inline uint32_t gpio_get_pin_output_status(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - return (ptr->DO[port].VALUE & (1 << pin)) >> pin; -} - -/** - * @brief Toggle pin level - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -static inline void gpio_toggle_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - ptr->DO[port].TOGGLE = 1 << pin; -} - -/** - * @brief Write pin level - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * @param high Pin level set to high when it is set to true - */ -static inline void gpio_write_pin(GPIO_Type *ptr, uint32_t port, uint8_t pin, uint8_t high) -{ - if (high) { - ptr->DO[port].SET = 1 << pin; - } else { - ptr->DO[port].CLEAR = 1 << pin; - } -} - -/** - * @brief Set pin to input mode - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -static inline void gpio_set_pin_input(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - ptr->OE[port].CLEAR = 1 << pin; -} - -/** - * @brief Set pin to output mode - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -static inline void gpio_set_pin_output(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - ptr->OE[port].SET = 1 << pin; -} - -/** - * @brief Set pin to output mode with initial value - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * @param initial Initial value - */ -void gpio_set_pin_output_with_initial(GPIO_Type *ptr, uint32_t port, uint8_t pin, uint8_t initial); - -/** - * @brief Check specific pin interrupt status - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * - * @return true if interrupt flag is set - */ -static inline bool gpio_check_pin_interrupt_flag(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - return ptr->IF[port].VALUE & (1 << pin); -} - -/** - * @brief Clear specific pin interrupt flag - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -static inline void gpio_clear_pin_interrupt_flag(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - ptr->IF[port].VALUE = 1 << pin; -} - -/** - * @brief Check if specific pin interrupt is enabled or not - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * - * @return true if interrupt is enabled - */ -static inline bool gpio_check_pin_interrupt_enabled(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - return (ptr->IE[port].VALUE & (1 << pin)) == (uint32_t) (1 << pin); -} - -/** - * @brief Enable interrupt for specific pin - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -static inline void gpio_enable_pin_interrupt(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - ptr->IE[port].SET = 1 << pin; -} - -/** - * @brief Disable interrupt for specific pin - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -static inline void gpio_disable_pin_interrupt(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - ptr->IE[port].CLEAR = 1 << pin; -} - -/** - * @brief Check interrupt flag of specific pin and clear if it is set - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * - * @return true if the interrupt flag is set and cleared - * @return false if the interrupt flag is not set - */ -static inline bool gpio_check_clear_interrupt_flag(GPIO_Type *ptr, uint32_t port, uint8_t pin) -{ - if (!gpio_check_pin_interrupt_flag(ptr, port, pin)) { - return false; - } - gpio_clear_pin_interrupt_flag(ptr, port, pin); - return true; -} - - -/** - * @brief Read all pins level on specific port - * - * @param ptr GPIO base address - * @param port Port index - * - * @return Port pin level status - */ -static inline uint32_t gpio_read_port(GPIO_Type *ptr, uint32_t port) -{ - return ptr->DI[port].VALUE; -} - -/** - * @brief Toggle port with specific pin mask - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask pins to be toggled - */ -static inline void gpio_toggle_port_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) -{ - ptr->DO[port].TOGGLE = mask; -} - -/** - * @brief Write specific port with value - * - * @param ptr GPIO base address - * @param port Port index - * @param value Value to be written - */ -static inline void gpio_write_port(GPIO_Type *ptr, uint32_t port, uint32_t value) -{ - ptr->DO[port].VALUE = value; -} - -/** - * @brief Set spcific port pin high according to the given mask - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of pins to be set to low - */ -static inline void gpio_set_port_low_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) -{ - ptr->DO[port].CLEAR = mask; -} - -/** - * @brief Set spcific port pin high according to the given mask - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of pins to be set to high - */ -static inline void gpio_set_port_high_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) -{ - ptr->DO[port].SET = mask; -} - -/** - * @brief Enable pins output of specific port according to the given mask - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of pins to be enabled - */ -static inline void gpio_enable_port_output_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) -{ - ptr->OE[port].SET = mask; -} - -/** - * @brief Disable pins output of specific port according to the given mask - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of pins to be disabled - */ -static inline void gpio_disable_port_output_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) -{ - ptr->OE[port].CLEAR = mask; -} - -/** - * @brief Get current interrupt flags on specific port - * - * @param ptr GPIO base address - * @param port Port index - * - * @return Current interrupt flags on specific port - */ -static inline uint32_t gpio_get_port_interrupt_flags(GPIO_Type *ptr, uint32_t port) -{ - return ptr->IF[port].VALUE; -} - - -/** - * @brief Clear interrupt flags with given mask on specific port - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of interrupts to be cleared - */ -static inline void gpio_clear_port_interrupt_flags_with_mask(GPIO_Type *ptr, uint32_t port, uint32_t mask) -{ - ptr->IF[port].VALUE |= mask; -} - -/** - * @brief Enable interrupts with given mask on specific port - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of interrupts to be enabled - */ -static inline void gpio_enable_port_interrupt_with_mask(GPIO_Type *ptr, uint32_t port, uint8_t mask) -{ - ptr->IE[port].SET = mask; -} - -/** - * @brief Disable interrupts with given mask on specific port - * - * @param ptr GPIO base address - * @param port Port index - * @param mask Mask of interrupts to be disabled - */ -static inline void gpio_disable_port_interrupt_with_mask(GPIO_Type *ptr, uint32_t port, uint8_t mask) -{ - ptr->IE[port].CLEAR = mask; -} - - -/** - * @brief Config pin interrupt - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - * @param trigger Trigger type - */ -void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t port, uint8_t pin, gpio_interrupt_trigger_t trigger); - - -/** - * @brief Toggle pin interrupt trigger polarity - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -void gpio_toggle_pin_interrupt_trigger_polarity(GPIO_Type *ptr, uint32_t port, uint8_t pin); - -/** - * @brief Toggle pin interrupt trigger type - * - * @param ptr GPIO base address - * @param port Port index - * @param pin Pin index - */ -void gpio_toggle_pin_interrupt_trigger_type(GPIO_Type *ptr, uint32_t port, uint8_t pin); -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_GPIO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h deleted file mode 100644 index e24c96c8dd9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gpiom_drv.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_DRV_H -#define HPM_GPIOM_DRV_H - -#include "hpm_gpiom_regs.h" -#include "hpm_gpiom_soc_drv.h" - -/** - * - * @brief GPIOM driver APIs - * @defgroup gpiom_interface GPIOM driver APIs - * @ingroup io_interfaces - * @{ - */ - -/* @brief pin visibility */ -typedef enum gpiom_pin_visibility { - gpiom_pin_visible = 0, - gpiom_pin_invisible = 1, -} gpiom_pin_visibility_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get pin's controller - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - * - * @retval pin control module - */ -static inline gpiom_gpio_t gpiom_get_pin_controller(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index) -{ - return (gpiom_gpio_t)((ptr->ASSIGN[gpio_index].PIN[pin_index] - & (GPIOM_ASSIGN_PIN_SELECT_MASK)) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT); -} - -/** - * @brief set pin's controller - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - * @param gpio gpio module index - */ -static inline void gpiom_set_pin_controller(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index, - gpiom_gpio_t gpio) -{ - ptr->ASSIGN[gpio_index].PIN[pin_index] = - (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~(GPIOM_ASSIGN_PIN_SELECT_MASK)) - | GPIOM_ASSIGN_PIN_SELECT_SET(gpio); -} - -/** - * @brief Check if pin is visibility for specified module - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - * @param gpio gpio module index - * - * @retval true if pin is visible by specified module - * @retval false if pin is not visible by specified module - */ -static inline bool gpiom_check_pin_visibility(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index, - gpiom_gpio_t gpio) -{ - return (ptr->ASSIGN[gpio_index].PIN[pin_index] & ((1 << gpio) << GPIOM_ASSIGN_PIN_HIDE_SHIFT)) - >> GPIOM_ASSIGN_PIN_HIDE_SHIFT >> gpio == gpiom_pin_visible; -} - -/** - * @brief enable pin visibility for specified module - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - * @param gpio gpio module index - */ -static inline void gpiom_enable_pin_visibility(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index, - gpiom_gpio_t gpio) -{ - ptr->ASSIGN[gpio_index].PIN[pin_index] = - (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_ASSIGN_PIN_HIDE_SHIFT)); -} - -/** - * @brief disable pin visibility for specified module - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - * @param gpio gpio module index - */ -static inline void gpiom_disable_pin_visibility(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index, - gpiom_gpio_t gpio) -{ - ptr->ASSIGN[gpio_index].PIN[pin_index] = - (ptr->ASSIGN[gpio_index].PIN[pin_index] & ~((1 << gpio) << GPIOM_ASSIGN_PIN_HIDE_SHIFT)) - | GPIOM_ASSIGN_PIN_HIDE_SET(1 << gpio); -} - -/** - * @brief Check if pin management is locked - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - * - * @retval true if pin management is locked - * @retval false if pin management is not locked - */ -static inline bool gpiom_pin_is_locked(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index) -{ - return (ptr->ASSIGN[gpio_index].PIN[pin_index] & GPIOM_ASSIGN_PIN_LOCK_MASK) - == GPIOM_ASSIGN_PIN_LOCK_MASK; -} - -/** - * @brief lock pin management - * - * @param ptr GPIOM base address - * @param gpio_index gpio port index - * @param pin_index pin index - */ -static inline void gpiom_lock_pin(GPIOM_Type *ptr, - uint8_t gpio_index, - uint8_t pin_index) -{ - ptr->ASSIGN[gpio_index].PIN[pin_index] |= GPIOM_ASSIGN_PIN_LOCK_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_GPIOM_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h deleted file mode 100644 index c560067bfa9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPTMR_DRV_H -#define HPM_GPTMR_DRV_H -#include "hpm_common.h" -#include "hpm_gptmr_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief GPTMR driver APIs - * @defgroup gptmr_interface GPTMR driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief GPTMR channel IRQ mask - */ -#define GPTMR_CH_CMP_IRQ_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp)) -#define GPTMR_CH_CAP_IRQ_MASK(ch) (1 << (ch * 4 + 1)) -#define GPTMR_CH_RLD_IRQ_MASK(ch) (1 << (ch * 4)) - -/** - * @brief GPTMR channel status - */ -#define GPTMR_CH_CMP_STAT_MASK(ch, cmp) (1 << (ch * 4 + 2 + cmp)) -#define GPTMR_CH_CAP_STAT_MASK(ch) (1 << (ch * 4 + 1)) -#define GPTMR_CH_RLD_STAT_MASK(ch) (1 << (ch * 4)) - -/** - * @brief GPTMR channel swsynct mask - */ -#define GPTMR_CH_GCR_SWSYNCT_MASK(ch) (1 << ch) - -/** - * @brief GPTMR one channel support output comparator count - */ -#define GPTMR_CH_CMP_COUNT (2U) - -/** - * @brief GPTMR synci valid edge - */ -typedef enum gptmr_synci_edge { - gptmr_synci_edge_none = 0, - gptmr_synci_edge_falling = GPTMR_CHANNEL_CR_SYNCIFEN_MASK, - gptmr_synci_edge_rising = GPTMR_CHANNEL_CR_SYNCIREN_MASK, - gptmr_synci_edge_both = gptmr_synci_edge_falling | gptmr_synci_edge_rising, -} gptmr_synci_edge_t; - -/** - * @brief GPTMR work mode - */ -typedef enum gptmr_work_mode { - gptmr_work_mode_no_capture = 0, - gptmr_work_mode_capture_at_rising_edge = 1, - gptmr_work_mode_capture_at_falling_edge = 2, - gptmr_work_mode_capture_at_both_edge = 3, - gptmr_work_mode_measure_width = 4, -} gptmr_work_mode_t; - -/** - * @brief GPTMR DMA request event - */ -typedef enum gptmr_dma_request_event { - gptmr_dma_request_on_cmp0 = 0, - gptmr_dma_request_on_cmp1 = 1, - gptmr_dma_request_on_input_signal_toggle = 2, - gptmr_dma_request_on_reload = 3, - gptmr_dma_request_disabled = 0xFF, -} gptmr_dma_request_event_t; - -/** - * @brief GPTMR counter type - */ -typedef enum gptmr_counter_type { - gptmr_counter_type_rising_edge, - gptmr_counter_type_falling_edge, - gptmr_counter_type_measured_period, - gptmr_counter_type_measured_duty_cycle, - gptmr_counter_type_normal, -} gptmr_counter_type_t; - -/** - * @brief GPTMR counter mode - */ - -#if defined(HPM_IP_FEATURE_GPTMR_CNT_MODE) && (HPM_IP_FEATURE_GPTMR_CNT_MODE == 1) -typedef enum gptmr_counter_mode { - gptmr_counter_mode_internal = 0, - gptmr_counter_mode_external, -} gptmr_counter_mode_t; -#endif - -/** - * @brief GPTMR channel config - */ -typedef struct gptmr_channel_config { - gptmr_work_mode_t mode; - gptmr_dma_request_event_t dma_request_event; - gptmr_synci_edge_t synci_edge; - uint32_t cmp[GPTMR_CH_CMP_COUNT]; - uint32_t reload; - bool cmp_initial_polarity_high; - bool enable_cmp_output; - bool enable_sync_follow_previous_channel; - bool enable_software_sync; - bool debug_mode; -} gptmr_channel_config_t; - -#if defined(HPM_IP_FEATURE_GPTMR_MONITOR) && (HPM_IP_FEATURE_GPTMR_MONITOR == 1) -typedef enum gptmr_channel_monitor_type { - monitor_signal_period = 0, - monitor_signal_high_level_time, -} gptmr_channel_monitor_type_t; - -typedef struct gptmr_channel_monitor_config { - gptmr_channel_monitor_type_t monitor_type; - uint32_t max_value; /**< The unit is the gptmr clock source period */ - uint32_t min_value; /**< The unit is the gptmr clock source period */ -} gptmr_channel_monitor_config_t; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief gptmr channel enable - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] enable - * @arg true: enable - * @arg false: disable - */ -static inline void gptmr_channel_enable(GPTMR_Type *ptr, uint8_t ch_index, bool enable) -{ - ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR - & ~(GPTMR_CHANNEL_CR_CNTRST_MASK | GPTMR_CHANNEL_CR_CMPEN_MASK)) - | GPTMR_CHANNEL_CR_CMPEN_SET(enable); -} - -/** - * @brief gptmr channel reset counter - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_channel_reset_count(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTRST_MASK; - ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CNTRST_MASK; -} - -/** - * @brief gptmr channel update counter - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] value updated vaue - */ -static inline void gptmr_channel_update_count(GPTMR_Type *ptr, - uint8_t ch_index, - uint32_t value) -{ - if (value > 0) { - value--; - } - ptr->CHANNEL[ch_index].CNTUPTVAL = GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(value); - ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CNTUPT_MASK; -} - -/** - * @brief gptmr channel slect synci valid edge - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] edge gptmr_synci_edge_t - */ -static inline void gptmr_channel_select_synci_valid_edge(GPTMR_Type *ptr, - uint8_t ch_index, - gptmr_synci_edge_t edge) -{ - ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR - & ~(GPTMR_CHANNEL_CR_SYNCIFEN_MASK - | GPTMR_CHANNEL_CR_SYNCIREN_MASK)) | edge; -} - -/** - * @brief gptmr channel enable dma request - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] enable - * @arg true: enable - * @arg false: disable - */ -static inline void gptmr_channel_enable_dma_request(GPTMR_Type *ptr, - uint8_t ch_index, - bool enable) -{ - ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR - & ~(GPTMR_CHANNEL_CR_DMAEN_MASK)) | GPTMR_CHANNEL_CR_DMAEN_SET(enable); -} - -/** - * @brief gptmr channel get counter value - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] capture gptmr_counter_type_t - */ -static inline uint32_t gptmr_channel_get_counter(GPTMR_Type *ptr, - uint8_t ch_index, - gptmr_counter_type_t capture) -{ - uint32_t value; - switch (capture) { - case gptmr_counter_type_rising_edge: - value = (ptr->CHANNEL[ch_index].CAPPOS & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT; - break; - case gptmr_counter_type_falling_edge: - value = (ptr->CHANNEL[ch_index].CAPNEG & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT; - break; - case gptmr_counter_type_measured_period: - value = (ptr->CHANNEL[ch_index].CAPPRD & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT; - break; - case gptmr_counter_type_measured_duty_cycle: - value = (ptr->CHANNEL[ch_index].CAPDTY & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT; - break; - default: - value = (ptr->CHANNEL[ch_index].CNT & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT; - break; - } - return value; -} - -/** - * @brief gptmr trigger channel software sync - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index_mask channel index mask - */ -static inline void gptmr_trigger_channel_software_sync(GPTMR_Type *ptr, uint32_t ch_index_mask) -{ - ptr->GCR = ch_index_mask; -} - -/** - * @brief gptmr enable irq - * - * @param [in] ptr GPTMR base address - * @param [in] irq_mask irq mask - */ -static inline void gptmr_enable_irq(GPTMR_Type *ptr, uint32_t irq_mask) -{ - ptr->IRQEN |= irq_mask; -} - -/** - * @brief gptmr disable irq - * - * @param [in] ptr GPTMR base address - * @param [in] irq_mask irq mask - */ -static inline void gptmr_disable_irq(GPTMR_Type *ptr, uint32_t irq_mask) -{ - ptr->IRQEN &= ~irq_mask; -} - -/** - * @brief gptmr check status - * - * @param [in] ptr GPTMR base address - * @param [in] mask channel flag mask - */ -static inline bool gptmr_check_status(GPTMR_Type *ptr, uint32_t mask) -{ - return (ptr->SR & mask) == mask; -} - -/** - * @brief gptmr clear status - * - * @param [in] ptr GPTMR base address - * @param [in] mask channel flag mask - */ -static inline void gptmr_clear_status(GPTMR_Type *ptr, uint32_t mask) -{ - ptr->SR = mask; -} - -/** - * @brief gptmr get status - * - * @param [in] ptr GPTMR base address - * @retval SR register value - */ -static inline uint32_t gptmr_get_status(GPTMR_Type *ptr) -{ - return ptr->SR; -} - -/** - * @brief gptmr channel start counter - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_start_counter(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CEN_MASK; -} - -/** - * @brief gptmr channel stop counter - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_stop_counter(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CEN_MASK; -} - -/** - * @brief gptmr channel enable compare output - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_enable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_CMPEN_MASK; -} - -/** - * @brief gptmr channel disable compare output - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_disable_cmp_output(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_CMPEN_MASK; -} - -/** - * @brief gptmr channel set capmode - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] mode enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge and so on - */ -static inline void gptmr_channel_set_capmode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_work_mode_t mode) -{ - ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CAPMODE_MASK) | GPTMR_CHANNEL_CR_CAPMODE_SET(mode); -} - -/** - * @brief gptmr channel get capmode - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @retval gptmr_work_mode_t enum gptmr_work_mode_capture_at_rising_edge or gptmr_work_mode_capture_at_falling_edge - */ -static inline gptmr_work_mode_t gptmr_channel_get_capmode(GPTMR_Type *ptr, uint8_t ch_index) -{ - return (gptmr_work_mode_t)GPTMR_CHANNEL_CR_CAPMODE_GET(ptr->CHANNEL[ch_index].CR); -} - -/** - * @brief gptmr channel update comparator - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] cmp_index comparator index - * @param [in] cmp comparator value - */ -static inline void gptmr_update_cmp(GPTMR_Type *ptr, uint8_t ch_index, uint8_t cmp_index, uint32_t cmp) -{ - if (cmp > 0) { - cmp--; - } - ptr->CHANNEL[ch_index].CMP[cmp_index] = GPTMR_CHANNEL_CMP_CMP_SET(cmp); -} - -/** - * @brief gptmr channel get reload - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @retval RLD register value - */ -static inline uint32_t gptmr_channel_get_reload(GPTMR_Type *ptr, uint8_t ch_index) -{ - return ptr->CHANNEL[ch_index].RLD; -} - -/** - * @brief gptmr channel update reload - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] reload reload value - */ -static inline void gptmr_channel_config_update_reload(GPTMR_Type *ptr, uint8_t ch_index, uint32_t reload) -{ - if (reload > 0) { - reload--; - } - ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(reload); -} - -/** - * @brief gptmr channel get dma request event - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @retval gptmr_dma_request_event_t gptmr_dma_request_on_cmp0 or gptmr_dma_request_on_reload - */ -static inline gptmr_dma_request_event_t gptmr_channel_get_dma_request_event(GPTMR_Type *ptr, uint8_t ch_index) -{ - return (gptmr_dma_request_event_t)GPTMR_CHANNEL_CR_DMASEL_GET(ptr->CHANNEL[ch_index].CR); -} - -/** - * @brief gptmr channel config - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] config gptmr_channel_config_t - * @param [in] enable - * @arg true: enable - * @arg false: disable - * - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, - uint8_t ch_index, - gptmr_channel_config_t *config, - bool enable); - -/** - * @brief gptmr channel get default config - * - * @param [in] ptr GPTMR base address - * @param [out] config gptmr_channel_config_t - */ -void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config); - - -#if defined(HPM_IP_FEATURE_GPTMR_CNT_MODE) && (HPM_IP_FEATURE_GPTMR_CNT_MODE == 1) -/** - * @brief gptmr set counter mode. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] mode gptmr_counter_mode_t, gptmr_counter_mode_external for gptmr enable external counting mode - */ -static inline void gptmr_channel_set_counter_mode(GPTMR_Type *ptr, uint8_t ch_index, gptmr_counter_mode_t mode) -{ - ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_CNT_MODE_MASK) | GPTMR_CHANNEL_CR_CNT_MODE_SET(mode); -} - -/** - * @brief gptmr channel get external trigger input counting mode. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @retval gptmr_counter_mode_external for external counting mode, gptmr_counter_mode_internal for internal counting mode - */ -static inline gptmr_counter_mode_t gptmr_channel_get_counter_mode(GPTMR_Type *ptr, uint8_t ch_index) -{ - return ((ptr->CHANNEL[ch_index].CR & GPTMR_CHANNEL_CR_CNT_MODE_MASK) == - GPTMR_CHANNEL_CR_CNT_MODE_MASK) ? - gptmr_counter_mode_external : gptmr_counter_mode_internal; -} - -#endif - -#if defined(HPM_IP_FEATURE_GPTMR_OP_MODE) && (HPM_IP_FEATURE_GPTMR_OP_MODE == 1) -/** - * @brief gptmr channel enable opmode, it's one-shot mode, timer will stopped at reload point. - * - * @note reload irq will be always set at one-shot mode at end - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_channel_enable_opmode(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_OPMODE_MASK; -} - -/** - * @brief gptmr channel disable opmode, it's round mode. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_channel_disable_opmode(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_OPMODE_MASK; -} - -/** - * @brief gptmr channel get opmode. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @retval bool true for opmode, false for normal mode - */ -static inline bool gptmr_channel_is_opmode(GPTMR_Type *ptr, uint8_t ch_index) -{ - return ((ptr->CHANNEL[ch_index].CR & GPTMR_CHANNEL_CR_OPMODE_MASK) == GPTMR_CHANNEL_CR_OPMODE_MASK) ? true : false; -} -#endif - -#if defined(HPM_IP_FEATURE_GPTMR_MONITOR) && (HPM_IP_FEATURE_GPTMR_MONITOR == 1) -/** - * @brief gptmr channel enable monitor, set to monitor input signal period or high level time. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_channel_enable_monitor(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR |= GPTMR_CHANNEL_CR_MONITOR_EN_MASK; -} - -/** - * @brief gptmr channel disable monitor - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - */ -static inline void gptmr_channel_disable_monitor(GPTMR_Type *ptr, uint8_t ch_index) -{ - ptr->CHANNEL[ch_index].CR &= ~GPTMR_CHANNEL_CR_MONITOR_EN_MASK; -} - -/** - * @brief gptmr channel set to monitor input signal period or high level time. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] type gptmr_channel_monitor_type_t - */ -static inline void gptmr_channel_set_monitor_type(GPTMR_Type *ptr, uint8_t ch_index, gptmr_channel_monitor_type_t type) -{ - ptr->CHANNEL[ch_index].CR = (ptr->CHANNEL[ch_index].CR & ~GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) | GPTMR_CHANNEL_CR_MONITOR_SEL_SET(type); -} - -/** - * @brief gptmr channel get to monitor input signal period or high level time. - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @retval gptmr_channel_monitor_type_t monitor_signal_high_level_time or monitor_signal_period - */ -static inline gptmr_channel_monitor_type_t gptmr_channel_get_monitor_type(GPTMR_Type *ptr, uint8_t ch_index) -{ - return (gptmr_channel_monitor_type_t)GPTMR_CHANNEL_CR_MONITOR_SEL_GET(ptr->CHANNEL[ch_index].CR); -} -/** - * @brief gptmr channel get default monitor config - * - * @param [in] ptr GPTMR base address - * @param [out] config gptmr_channel_monitor_config_t - */ -void gptmr_channel_get_default_monitor_config(GPTMR_Type *ptr, gptmr_channel_monitor_config_t *config); - -/** - * @brief gptmr channel monitor config - * - * @param [in] ptr GPTMR base address - * @param [in] ch_index channel index - * @param [in] config gptmr_channel_monitor_config_t - * @param [in] enable - * @arg true: enable monitor and reset reload count - * @arg false: disable monitor - * - * @retval hpm_stat_t status_invalid_argument or status_success - */ - -hpm_stat_t gptmr_channel_monitor_config(GPTMR_Type *ptr, uint8_t ch_index, - gptmr_channel_monitor_config_t *config, - bool enable); - -#endif - - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_GPTMR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h deleted file mode 100644 index dc4da1278f1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gwc_drv.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GWC_DRV_H -#define HPM_GWC_DRV_H - -/** - * @brief GWC APIs - * @defgroup gwc_interface GWC driver APIs - * @ingroup gwc_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_gwc_regs.h" - -/** - * @brief gwc channel config - * - * @note area of channel do not overlap. in other words, eache pixel belongs to a single channel at most. - */ -typedef struct gwc_ch_config { - bool freeze; /*!< freeze the channel configuration except reference CRC32 value setting. */ - uint16_t start_col; /*!< start col is X of upper left corner. Range: 0 to 2^13-1. */ - uint16_t start_row; /*!< start row is Y of upper left corner. Range: 0 to 2^12-1. */ - uint16_t end_col; /*!< end col is X of lower right corner. Range: 0 to 2^13-1. */ - uint16_t end_row; /*!< end row is Y of lower right corner. Range: 0 to 2^12-1. */ - uint32_t ref_crc; /*!< Reference CRC32 value.*/ -} gwc_ch_config_t; - -/** - * @brief gwc clk polarity - */ -typedef enum gwc_clk_pol { - gwc_clk_pol_normal = 0, - gwc_clk_pol_invert -} gwc_clk_pol_t; - -/** - * @brief gwc config - */ -typedef struct gwc_config { - gwc_clk_pol_t clk_pol; -} gwc_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief init the gwc - * - * @param[in] cfg GWC config @ref gwc_config_t - */ -void gwc_get_default_config(gwc_config_t *cfg); - -/** - * @brief init the gwc - * - * @param[in] ptr GWC base address - * @param[in] cfg GWC config @ref gwc_config_t - * - * @note the function is called while gwc is disable only - */ -void gwc_init(GWC_Type *ptr, gwc_config_t *cfg); - -/** - * @brief enable the gwc - * - * @param[in] ptr GWC base address - */ -void gwc_enable(GWC_Type *ptr); - -/** - * @brief disable the gwc - * - * @param[in] ptr GWC base address - */ -void gwc_disable(GWC_Type *ptr); - -/** - * @brief enable interrupts - * - * @param[in] ptr GWC base address - * @param[in] mask Mask of interrupt events that would be enabled - * @ref GWC_IRQ_MASK_ERR_MASK_MASK - * @ref GWC_IRQ_MASK_FUNC_MASK_MASK - */ -static inline void gwc_enable_interrupt(GWC_Type *ptr, uint32_t mask) -{ - ptr->IRQ_MASK &= ~mask; -} - -/** - * @brief disable interrupts. - * - * @param[in] ptr GWC base address - * @param[in] mask mask of interrupt events that would be enabled. - * @ref GWC_IRQ_MASK_ERR_MASK_MASK - * @ref GWC_IRQ_MASK_FUNC_MASK_MASK - */ -static inline void gwc_disable_interrupt(GWC_Type *ptr, uint32_t mask) -{ - ptr->IRQ_MASK |= mask; -} - -/** - * @brief get gwc status flag - * - * @param[in] ptr GWC base address - * @return gwc status - */ -static inline uint32_t gwc_get_status(GWC_Type *ptr) -{ - return ptr->IRQ_STS; -} - -/** - * @brief clear gwc status flag - * - * @param[in] ptr GWC base address - * @param[in] mask logical OR'ed of GWC_IRQ_STS_XXX_STS_MASK - */ -static inline void gwc_clear_status(GWC_Type *ptr, uint32_t mask) -{ - ptr->IRQ_STS = mask; -} - -/** - * @brief disable change of interrupt masks - * - * Once this function is called, the interrupt enabled status could not be changed - * until reset. - * - * @param[in] ptr GWC base address - */ -void gwc_freeze_interrupt_control(GWC_Type *ptr); - -/** - * @brief init gwc channel - * - * @param[in] ptr GWC base address - * @param[in] ch_index channel index ref GWC_CHANNEL_CHn - * @param[in] cfg config of gwc channel - * - * @note the function is called while gwc channel is disable only - */ -void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg); - -/** - * @brief enable gwc channel - * - * @param[in] ptr GWC base address - * @param[in] ch_index channel index ref GWC_CHANNEL_CHn - */ -static inline void gwc_ch_enable(GWC_Type *ptr, uint8_t ch_index) -{ - assert(ch_index <= GWC_CHANNEL_CH15); - ptr->CHANNEL[ch_index].CFG0 |= GWC_CHANNEL_CFG0_ENABLE_MASK; -} - -/** - * @brief disable gwc channel - * - * @param[in] ptr GWC base address - * @param[in] ch_index channel index ref GWC_CHANNEL_CHn - */ -static inline void gwc_ch_disable(GWC_Type *ptr, uint8_t ch_index) -{ - assert(ch_index <= GWC_CHANNEL_CH15); - ptr->CHANNEL[ch_index].CFG0 &= ~GWC_CHANNEL_CFG0_ENABLE_MASK; -} - -/** - * @brief get gwc channel calc crc - * - * @param[in] ptr GWC base address - * @param[in] ch_index channel index ref GWC_CHANNEL_CHn - */ -static inline uint32_t gwc_ch_get_crc(GWC_Type *ptr, uint8_t ch_index) -{ - assert(ch_index <= GWC_CHANNEL_CH15); - return ptr->CHANNEL[ch_index].CALCRC; -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_GWC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h deleted file mode 100644 index d62c2a100b7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_hall_drv.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_HALL_DRV_H -#define HPM_HALL_DRV_H - -#include "hpm_common.h" -#include "hpm_hall_regs.h" - -/** - * @brief HALL driver APIs - * @defgroup hall_interface HALL driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -#define HALL_EVENT_WDOG_FLAG_MASK (1U << 31) /**< wdg flag */ -#define HALL_EVENT_PHUPT_FLAG_MASK (1U << 30) /**< phupt flag */ -#define HALL_EVENT_PHPRE_FLAG_MASK (1U << 29) /**< phpre flag */ -#define HALL_EVENT_PHDLYEN_FLAG_MASK (1U << 28) /**< phdly flag */ -#define HALL_EVENT_U_FLAG_MASK (1U << 23) /**< u flag */ -#define HALL_EVENT_V_FLAG_MASK (1U << 22) /**< v flag */ -#define HALL_EVENT_W_FLAG_MASK (1U << 21) /**< w flag */ -#define HALL_UVW_STAT_MASK (HALL_COUNT_U_USTAT_MASK | HALL_COUNT_U_VSTAT_MASK | HALL_COUNT_U_WSTAT_MASK) -#define HALL_U_STAT_MASK HALL_COUNT_U_USTAT_MASK -#define HALL_V_STAT_MASK HALL_COUNT_U_VSTAT_MASK -#define HALL_W_STAT_MASK HALL_COUNT_U_WSTAT_MASK - -/** - * @brief select delay start time - * - */ -typedef enum hall_count_delay_start { - hall_count_delay_start_after_uvw_toggle = 0, /**< start counting delay after u,v,w toggle */ - hall_count_delay_start_after_pre_trigger = 1, /**< start counting delay after pre-trigger */ -} hall_count_delay_start_t; - -/** - * @brief return value of motor movement direction - * - */ -typedef enum hall_rotate_direction { - hall_rotate_direction_forward = 0, /**< direction forward */ - hall_rotate_direction_reversed = 1 /**< direction reversed */ -} hall_rotate_direction_t; - -/** - * @brief counter type config - * - */ -typedef enum hall_counter_type { - hall_counter_type_w = 0, /**< type w */ - hall_counter_type_v = 1, /**< type v */ - hall_counter_type_u = 2, /**< type u */ - hall_counter_type_timer = 3, /**< type timer */ -} hall_counter_type_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable the watchdog - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] timeout watch dog timeout value , unit is HALL system clock - */ -static inline void hall_wdog_enable(HALL_Type *hall_x, uint32_t timeout) -{ - hall_x->WDGCFG = HALL_WDGCFG_WDGTO_SET(timeout) - | HALL_WDGCFG_WDGEN_SET(true); -} - -/** - * @brief disable the watchdog - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - */ -static inline void hall_wdog_disable(HALL_Type *hall_x) -{ - hall_x->WDGCFG = HALL_WDGCFG_WDGEN_SET(false); -} - -/** - * @brief delay a certain number of clock cycles after receiving a trigger event - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] delay_count delay clock cycles number - * @param[in] delay_start select the trigger moment - */ -static inline void hall_phase_config(HALL_Type *hall_x, uint32_t delay_count, - hall_count_delay_start_t delay_start) -{ - hall_x->PHCFG = HALL_PHCFG_DLYSEL_SET(delay_start) - | HALL_PHCFG_DLYCNT_SET(delay_count); -} - -/** - * @brief early trigger configuration - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] counter the clock cycle number - */ -static inline void hall_pre_uvw_transition_config(HALL_Type *hall_x, uint32_t counter) -{ - hall_x->UVWCFG = HALL_UVWCFG_PRECNT_SET(counter); -} - -/** - * @brief enable trigger event mask - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] event_mask event mask to be checked - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_trigger_output_event_enable(HALL_Type *hall_x, - uint32_t event_mask) -{ - hall_x->TRGOEN = (hall_x->TRGOEN & ~event_mask) | event_mask; -} - -/** - * @brief disable trigger event mask - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] event_mask event mask to bo checked - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_trigger_output_event_disable(HALL_Type *hall_x, - uint32_t event_mask) -{ - hall_x->TRGOEN &= ~event_mask; -} - -/** - * @brief enable hardware read event - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] event_mask read registers flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_load_read_trigger_event_enable(HALL_Type *hall_x, - uint32_t event_mask) -{ - hall_x->READEN = (hall_x->READEN & ~event_mask) | event_mask; -} - -/** - * @brief disable hardware read event - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] event_mask read registers flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_load_read_trigger_event_disable(HALL_Type *hall_x, - uint32_t event_mask) -{ - hall_x->READEN &= ~event_mask; -} - -/** - * @brief clear status register - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] mask hall event flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_clear_status(HALL_Type *hall_x, uint32_t mask) -{ - hall_x->SR = mask; -} - -/** - * @brief get status register - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval uint32_t value: - * @retval HALL_EVENT_WDOG_FLAG_MASK if watchdog counter timeout - * @retval HALL_EVENT_PHUPT_FLAG_MASK if U/V/W Flip any input signal - * @retval HALL_EVENT_PHPRE_FLAG_MASK if early trigger events occur - * @retval HALL_EVENT_PHDLYEN_FLAG_MASK if time delay events occur - * @retval HALL_EVENT_U_FLAG_MASK if U signal flip - * @retval HALL_EVENT_V_FLAG_MASK if V signal flip - * @retval HALL_EVENT_W_FLAG_MASK if W signal flip - */ -static inline uint32_t hall_get_status(HALL_Type *hall_x) -{ - return hall_x->SR; -} - -/** - * @brief enable irq - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] mask hall event flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_irq_enable(HALL_Type *hall_x, uint32_t mask) -{ - hall_x->IRQEN = (hall_x->IRQEN & ~mask) | mask; -} - -/** - * @brief disable irq - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] mask hall event flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_irq_disable(HALL_Type *hall_x, uint32_t mask) -{ - hall_x->IRQEN &= ~mask; -} - -/** - * @brief enable dma request - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] mask hall event flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_dma_request_enable(HALL_Type *hall_x, uint32_t mask) -{ - hall_x->DMAEN = (hall_x->DMAEN & ~mask) | mask; -} - -/** - * @brief disable dma request - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] mask hall event flag - * @arg @ref HALL_EVENT_WDOG_FLAG_MASK - * @arg @ref HALL_EVENT_PHUPT_FLAG_MASK - * @arg @ref HALL_EVENT_PHPRE_FLAG_MASK - * @arg @ref HALL_EVENT_PHDLYEN_FLAG_MASK - * @arg @ref HALL_EVENT_U_FLAG_MASK - * @arg @ref HALL_EVENT_V_FLAG_MASK - * @arg @ref HALL_EVENT_W_FLAG_MASK - */ -static inline void hall_dma_request_disable(HALL_Type *hall_x, uint32_t mask) -{ - hall_x->DMAEN &= ~mask; -} - -/** - * @brief get rotate direction - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval hall_rotate_direction_t - */ -static inline hall_rotate_direction_t hall_get_rotate_direction(HALL_Type *hall_x) -{ - return (hall_rotate_direction_t)HALL_COUNT_U_DIR_GET(hall_x->COUNT[HALL_COUNT_CURRENT].U); -} - -/** - * @brief get three bits indicate UVW state - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval three bits UVW state - */ -static inline uint32_t hall_get_current_uvw_stat(HALL_Type *hall_x) -{ - return (hall_x->COUNT[HALL_COUNT_CURRENT].U & (HALL_UVW_STAT_MASK)) >> HALL_COUNT_U_WSTAT_SHIFT; -} - -/** - * @brief get current count U or V or W - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] type @ref hall_counter_type_t - * @retval count value - */ -static inline uint32_t hall_get_current_count(HALL_Type *hall_x, - hall_counter_type_t type) -{ - return *(&hall_x->COUNT[HALL_COUNT_CURRENT].W + type) & HALL_COUNT_U_UCNT_MASK; -} - -/** - * @brief get count when read event generated - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] type hall_counter_type_t - * @retval count value - */ -static inline uint32_t hall_get_count_on_read_event(HALL_Type *hall_x, - hall_counter_type_t type) -{ - return *(&hall_x->COUNT[HALL_COUNT_READ].W + type); -} - -/** - * @brief get count when snap0 event generated - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] type @ref hall_counter_type_t - * @retval count value - */ -static inline uint32_t hall_get_count_on_snap0_event(HALL_Type *hall_x, - hall_counter_type_t type) -{ - return *(&hall_x->COUNT[HALL_COUNT_SNAP0].W + type); -} - -/** - * @brief get count when snap1 event generated - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @param[in] type @ref hall_counter_type_t - * @retval count value - */ -static inline uint32_t hall_get_count_on_snap1_event(HALL_Type *hall_x, - hall_counter_type_t type) -{ - return *(&hall_x->COUNT[HALL_COUNT_SNAP1].W + type); -} - -/** - * @brief get the history count of u when u signal transition from 0 to 1 - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval count value - */ -static inline uint32_t hall_get_u_history0(HALL_Type *hall_x) -{ - return hall_x->HIS[0].HIS0; -} - -/** - * @brief get the history count of u when u signal transition from 1 to 0 - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval count value - */ -static inline uint32_t hall_get_u_history1(HALL_Type *hall_x) -{ - return hall_x->HIS[0].HIS1; -} - -/** - * @brief get the history count of v when v signal transition from 0 to 1 - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval count value - */ -static inline uint32_t hall_get_v_history0(HALL_Type *hall_x) -{ - return hall_x->HIS[1].HIS0; -} - -/** - * @brief get the history count of v when v signal transition from 1 to 0 - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval count value - */ -static inline uint32_t hall_get_v_history1(HALL_Type *hall_x) -{ - return hall_x->HIS[1].HIS1; -} - -/** - * @brief get the history count of w when w signal transition from 0 to 1 - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval count value - */ -static inline uint32_t hall_get_w_history0(HALL_Type *hall_x) -{ - return hall_x->HIS[2].HIS0; -} - -/** - * @brief get the history count of w when w signal transition from 1 to 0 - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - * @retval count value - */ -static inline uint32_t hall_get_w_history1(HALL_Type *hall_x) -{ - return hall_x->HIS[2].HIS1; -} - -/** - * @brief load ucnt, vcnt, wcnt and tmrcnt into their read registers. - * Hardware auto-clear; - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - */ -static inline void hall_load_count_to_read_registers(HALL_Type *hall_x) -{ - hall_x->CR |= HALL_CR_READ_MASK; -} - -/** - * @brief enable hall snap - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - */ -static inline void hall_snap_enable(HALL_Type *hall_x) -{ - hall_x->CR |= HALL_CR_SNAPEN_SET(1); -} - -/** - * @brief disable hall snap - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - */ -static inline void hall_snap_disable(HALL_Type *hall_x) -{ - hall_x->CR &= ~HALL_CR_SNAPEN_MASK; -} - -/** - * @brief reset all counter and related snapshots assert - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - */ -static inline void hall_counter_reset_assert(HALL_Type *hall_x) -{ - hall_x->CR |= HALL_CR_RSTCNT_MASK; -} - -/** - * @brief reset all counter and related snapshots release - * - * @param[in] hall_x HALL base address HPM_HALLx(x=0..n) - */ -static inline void hall_counter_reset_release(HALL_Type *hall_x) -{ - hall_x->CR &= ~HALL_CR_RSTCNT_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_HALL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h deleted file mode 100644 index 715a78bcf62..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h +++ /dev/null @@ -1,672 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_I2C_DRV_H -#define HPM_I2C_DRV_H -#include "hpm_common.h" -#include "hpm_i2c_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief I2C driver APIs - * @defgroup i2c_interface I2C driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief I2C status - */ -enum { - status_i2c_no_ack = MAKE_STATUS(status_group_i2c, 1), - status_i2c_invalid_data = MAKE_STATUS(status_group_i2c, 2), - status_i2c_no_addr_hit = MAKE_STATUS(status_group_i2c, 3), - status_i2c_transmit_not_completed = MAKE_STATUS(status_group_i2c, 4), - status_i2c_not_supported = MAKE_STATUS(status_group_i2c, 9), -}; - -/* convert data count value into register(CTRL[DATACNT] and CTRL[DATACNT_HIGH] if exist) */ -/* x range from 1 to I2C_SOC_TRANSFER_COUNT_MAX */ -/* 0 for I2C_SOC_TRANSFER_COUNT_MAX */ -#define I2C_DATACNT_MAP(x) (((x) == I2C_SOC_TRANSFER_COUNT_MAX) ? 0 : x) - -/** - * @brief I2C CMD - */ -#define I2C_CMD_NO_ACTION (I2C_CMD_CMD_SET(0)) -#define I2C_CMD_ISSUE_DATA_TRANSMISSION (I2C_CMD_CMD_SET(1)) -#define I2C_CMD_ACK (I2C_CMD_CMD_SET(2)) -#define I2C_CMD_NACK (I2C_CMD_CMD_SET(3)) -#define I2C_CMD_CLEAR_FIFO (I2C_CMD_CMD_SET(4)) -#define I2C_CMD_RESET (I2C_CMD_CMD_SET(5)) - -/** - * @brief I2C data direction - */ -#define I2C_DIR_MASTER_WRITE (0U) -#define I2C_DIR_MASTER_READ (1U) -#define I2C_DIR_SLAVE_READ (0U) -#define I2C_DIR_SLAVE_WRITE (1U) - -/** - * @brief I2C events for interrupt enable and status check - */ -#define I2C_EVENT_TRANSACTION_COMPLETE I2C_INTEN_CMPL_MASK -#define I2C_EVENT_BYTE_RECEIVED I2C_INTEN_BYTERECV_MASK -#define I2C_EVENT_BYTE_TRANSMIT I2C_INTEN_BYTETRANS_MASK -#define I2C_EVENT_START_CONDITION I2C_INTEN_START_MASK -#define I2C_EVENT_STOP_CONDITION I2C_INTEN_STOP_MASK -#define I2C_EVENT_LOSS_ARBITRATION I2C_INTEN_ARBLOSE_MASK -#define I2C_EVENT_ADDRESS_HIT I2C_INTEN_ADDRHIT_MASK -#define I2C_EVENT_FIFO_HALF I2C_INTEN_FIFOHALF_MASK -#define I2C_EVENT_FIFO_FULL I2C_INTEN_FIFOFULL_MASK -#define I2C_EVENT_FIFO_EMPTY I2C_INTEN_FIFOEMPTY_MASK - -#define I2C_EVENT_ALL_MASK (I2C_INTEN_CMPL_MASK \ - | I2C_INTEN_BYTERECV_MASK \ - | I2C_INTEN_BYTETRANS_MASK \ - | I2C_INTEN_START_MASK \ - | I2C_INTEN_STOP_MASK \ - | I2C_INTEN_ARBLOSE_MASK \ - | I2C_INTEN_ADDRHIT_MASK \ - | I2C_INTEN_FIFOHALF_MASK \ - | I2C_INTEN_FIFOFULL_MASK \ - | I2C_INTEN_FIFOEMPTY_MASK) -/** - * @brief I2C status for status check only - */ -#define I2C_STATUS_LINE_SDA I2C_STATUS_LINESDA_MASK -#define I2C_STATUS_LINE_SCL I2C_STATUS_LINESCL_MASK -#define I2C_STATUS_GENERAL_CALL I2C_STATUS_GENCALL_MASK -#define I2C_STATUS_BUS_BUSY I2C_STATUS_BUSBUSY_MASK -#define I2C_STATUS_ACK I2C_STATUS_ACK_MASK - -#define I2C_WR 0x0000 /* not operable with read flags*/ -#define I2C_RD (1u << 0) /* not operable with write flags*/ -#define I2C_ADDR_10BIT (1u << 2) /* this is a ten bit chip address */ -#define I2C_NO_START (1u << 4) /* no start */ -#define I2C_NO_READ_ACK (1u << 6) /* when I2C reading, we do not ACK */ -#define I2C_NO_STOP (1u << 7) /* no stop */ - -/** - * @brief I2C config - */ -typedef struct { - bool is_10bit_addressing; - uint8_t i2c_mode; -} i2c_config_t; - -/** - * @brief I2C mode - */ -typedef enum i2c_mode { - i2c_mode_normal, - i2c_mode_fast, - i2c_mode_fast_plus, -} i2c_mode_t; - -/** - * @brief I2c sequential transfer options - * @arg: i2c_frist_frame: has start signal - * @arg: i2c_next_frame: middle transfer - * @arg: i2c_last_frame: has stop signal - */ -typedef enum i2c_seq_transfer_opt { - i2c_frist_frame = 0, - i2c_next_frame, - i2c_last_frame, -} i2c_seq_transfer_opt_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief respond NACK - * - * @param [in] ptr I2C base address - */ -static inline void i2c_respond_Nack(I2C_Type *ptr) -{ - ptr->CMD = I2C_CMD_NACK; -} - -/** - * @brief respond ACK - * - * @param [in] ptr I2C base address - */ -static inline void i2c_respond_ack(I2C_Type *ptr) -{ - ptr->CMD = I2C_CMD_ACK; -} - -/** - * @brief clear I2C fifo - * - * @param [in] ptr I2C base address - */ -static inline void i2c_clear_fifo(I2C_Type *ptr) -{ - ptr->CMD = I2C_CMD_CLEAR_FIFO; -} - -/** - * @brief check data count - * - * @details It indicates number of bytes to transfer - * - * @param [in] ptr I2C base address - * @retval data count value in byte - */ -static inline uint16_t i2c_get_data_count(I2C_Type *ptr) -{ - uint32_t i2c_ctrl = ptr->CTRL; -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - return (I2C_CTRL_DATACNT_HIGH_GET(i2c_ctrl) << 8U) + I2C_CTRL_DATACNT_GET(i2c_ctrl); -#else - return I2C_CTRL_DATACNT_GET(i2c_ctrl); -#endif -} - -/** - * @brief check if I2C FIFO is full - * - * @param [in] ptr I2C base address - * @retval true if FIFO is full - */ -static inline bool i2c_fifo_is_full(I2C_Type *ptr) -{ - return ptr->STATUS & I2C_STATUS_FIFOFULL_MASK; -} - -/** - * @brief check if I2C FIFO is half - * - * @note When I2C is transmitting data, it indicates if fifo is half-empty; - * @note When I2C is receiving data, it indicates if fifo is half full. - * - * @param [in] ptr I2C base address - * @retval true if FIFO is half empty or full - */ -static inline bool i2c_fifo_is_half(I2C_Type *ptr) -{ - return ptr->STATUS & I2C_STATUS_FIFOHALF_MASK; -} - -/** - * @brief check if I2C FIFO is empty - * - * @param [in] ptr I2C base address - * @retval true if FIFO is empty - */ -static inline bool i2c_fifo_is_empty(I2C_Type *ptr) -{ - return ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK; -} - -/** - * @brief check if I2C is writing - * - * @param [in] ptr I2C base address - * @retval bool value - * @arg true: receive data if master mode, send data in slave mode - * @arg false: send data if master mode, reveive data in slave mode - * - */ -static inline bool i2c_is_writing(I2C_Type *ptr) -{ - return (ptr->CTRL & I2C_CTRL_DIR_MASK); -} - -/** - * @brief check if I2C is reading - * - * @param [in] ptr I2C base address - * @retval bool value - * @arg true: send data if master mode, receive data in slave mode - * @arg false: receive data if master mode, send data in slave mode - * - */ -static inline bool i2c_is_reading(I2C_Type *ptr) -{ - return !i2c_is_writing(ptr); -} - -/** - * @brief get i2c sda line status - * - * @param [in] ptr I2C base address - * @retval bool value - * @arg true: the sda line is high - * @arg false: the sda line is low - * - */ -static inline bool i2c_get_line_sda_status(I2C_Type *ptr) -{ - return I2C_STATUS_LINESDA_GET(ptr->STATUS); -} - -/** - * @brief get i2c scl line status - * - * @param [in] ptr I2C base address - * @retval bool value - * @arg true: the scl line is high - * @arg false: the scl line is low - * - */ -static inline bool i2c_get_line_scl_status(I2C_Type *ptr) -{ - return I2C_STATUS_LINESCL_GET(ptr->STATUS); -} - -/** - * @brief clear status - * - * @details Clear status based on mask - * - * @param [in] ptr I2C base address - * @param [in] mask mask to clear status - */ -static inline void i2c_clear_status(I2C_Type *ptr, uint32_t mask) -{ - ptr->STATUS = mask; -} - -/** - * @brief get status - * - * @details Get current I2C status bits - * - * @param [in] ptr I2C base address - * @retval current I2C status - */ -static inline uint32_t i2c_get_status(I2C_Type *ptr) -{ - return ptr->STATUS; -} - -/** - * @brief i2c get interrupts setting - * - * @details Get interrupt setting register value - * - * @param [in] ptr I2C base address - * @retval [out] uint32_t interrupt setting register value - */ -static inline uint32_t i2c_get_irq_setting(I2C_Type *ptr) -{ - return ptr->INTEN; -} - -/** - * @brief disable interrupts - * - * @details Disable interrupts based on given mask - * - * @param [in] ptr I2C base address - * @param [in] mask interrupt mask to be disabled - */ -static inline void i2c_disable_irq(I2C_Type *ptr, uint32_t mask) -{ - ptr->INTEN &= ~mask; -} - -/** - * @brief enable interrupts - * - * @details Enable interrupts based on given mask - * - * @param [in] ptr I2C base address - * @param [in] mask interrupt mask to be enabled - */ -static inline void i2c_enable_irq(I2C_Type *ptr, uint32_t mask) -{ - ptr->INTEN |= mask; -} - -/** - * @brief disable auto ack - * - * @details Disable I2C auto generates proper acknowledgements for each byte received - * - * @param [in] ptr I2C base address - */ -static inline void i2c_disable_auto_ack(I2C_Type *ptr) -{ - ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; -} - -/** - * @brief enable auto ack - * - * @details Enable I2C auto generates proper acknowledgements for each byte received - * - * @param [in] ptr I2C base address - */ -static inline void i2c_enable_auto_ack(I2C_Type *ptr) -{ - ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; -} - -/** - * @brief enable 10 bit address mode - * - * @details enable 10 bit address mode, if not, address is 7 bit mode - * - * @param [in] ptr I2C base address - * @param [in] enable - * @arg true: enable 10 bit address mode - * @arg false: enable 7 bit address mode - */ -static inline void i2c_enable_10bit_address_mode(I2C_Type *ptr, bool enable) -{ - ptr->SETUP |= I2C_SETUP_ADDRESSING_SET(enable); -} - -/** - * @brief I2C master initialization - * - * @details Initialized I2C controller working at master mode - * - * @param [in] ptr I2C base address - * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz - * @param [in] config i2c_config_t - * @retval hpm_stat_t: status_success if initialization is completed without any error - */ -hpm_stat_t i2c_init_master(I2C_Type *ptr, - uint32_t src_clk_in_hz, - i2c_config_t *config); - -/** - * @brief I2C master write data to specific address of certain slave device - * - * @details Write to certain I2C device at specific address within that device - * @note the sum of addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] addr address in that I2C device - * @param [in] addr_size_in_byte I2C address in byte - * @param [in] buf pointer of the data to be sent - * @param [in] size_in_byte size of data to be sent in bytes - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t i2c_master_address_write(I2C_Type *ptr, - const uint16_t device_address, - uint8_t *addr, - uint32_t addr_size_in_byte, - uint8_t *buf, - const uint32_t size_in_byte); - -/** - * @brief I2C master read data from specific address of certain slave device - * - * @details Read fram certain I2C device at specific address within that device - * @note both addr_size_in_byte and size_in_byte should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] addr address in that I2C device - * @param [in] addr_size_in_byte I2C address in byte - * @param [out] buf pointer of the buffer to receive data read from the device - * @param [in] size_in_byte size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t i2c_master_address_read(I2C_Type *ptr, - const uint16_t device_address, - uint8_t *addr, - uint32_t addr_size_in_byte, - uint8_t *buf, - const uint32_t size_in_byte); - -/** - * @brief I2C master write data to certain slave device - * - * @details Write data to I2C device - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] buf pointer of the data to be sent - * @param [in] size size of data to be sent in bytes - * @retval hpm_stat_t: status_success if writing is completed without any error - */ -hpm_stat_t i2c_master_write(I2C_Type *ptr, - const uint16_t device_address, - uint8_t *buf, - const uint32_t size); - -/** - * @brief I2C master start write data by DMA - * - * @details Write data to I2C device by DMA - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] i2c_ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] size size of data to be sent in bytes - * @retval hpm_stat_t status_success if starting transmission without any error - */ -hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); - -/** - * @brief I2C master start read data by DMA - * - * @details Read data to I2C device by DMA - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] i2c_ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t status_success if starting transmission without any error - */ -hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size); - -/** - * @brief I2C master read data from certain slave device - * - * @details Read data from I2C device - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] device_address I2C slave address - * @param [out] buf pointer of the buffer to store data read from device - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t i2c_master_read(I2C_Type *ptr, - const uint16_t device_address, - uint8_t *buf, - const uint32_t size); -/** - * @brief I2C slave initialization - * - * @details Initialize I2C controller working at slave mode - * - * @param [in] ptr I2C base address - * @param [in] src_clk_in_hz I2C controller source clock source frequency in Hz - * @param [in] config I2C configuration structure - * @param [in] slave_address I2C address to be used at slave mode - * @retval hpm_stat_t: status_success if initialization is completed without any error - */ -hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, - i2c_config_t *config, const uint16_t slave_address); - -/** - * @brief I2C slave read data - * - * @details Read data at slave mode - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] buf pointer of the buffer to store data read from device - * @param [in] size size of data to be read in bytes - * @retval hpm_stat_t: status_success if reading is completed without any error - */ -hpm_stat_t i2c_slave_read(I2C_Type *ptr, uint8_t *buf, const uint32_t size); - -/** - * @brief I2C slave write data - * - * @details Write data at slave mode. - * @note size should not not greater than I2C_SOC_TRANSFER_COUNT_MAX - * - * @param [in] ptr I2C base address - * @param [in] buf pointer of the buffer to store data sent from device - * @param [in] size size of data to be sent in bytes - * @retval hpm_stat_t status_success if writing is completed without any error - */ -hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size); - -/** - * @brief reset I2C - * - * @param [in] ptr I2C base address - */ -void i2c_reset(I2C_Type *ptr); - -/** - * @brief Enable i2c DMA - * - * @param [in] ptr I2C base address - */ -static inline void i2c_dma_enable(I2C_Type *ptr) -{ - ptr->SETUP |= I2C_SETUP_DMAEN_MASK; -} - -/** - * @brief Disable i2c DMA - * - * @param [in] ptr I2C base address - */ -static inline void i2c_dma_disable(I2C_Type *ptr) -{ - ptr->SETUP &= ~I2C_SETUP_DMAEN_MASK; -} - -/** - * @brief I2C slave dma transfer data - * - * @note The direction of data transmission depends on Master setting - * - * @param [in] ptr I2C base address - * @param [in] size size of data in bytes - * @retval hpm_stat_t status_success if configuring transmission without any error - */ -hpm_stat_t i2c_slave_dma_transfer(I2C_Type *ptr, const uint32_t size); - -/** - * @brief I2C write byte into FIFO - * - * @param ptr [in] ptr I2C base address - * @param data [in] byte to ne sent - */ -static inline void i2c_write_byte(I2C_Type *ptr, uint8_t data) -{ - ptr->DATA = I2C_DATA_DATA_SET(data); -} - -/** - * @brief I2C read byte into FIFO - * - * @param ptr [in] ptr I2C base address - * @return uint8_t read byte - */ -static inline uint8_t i2c_read_byte(I2C_Type *ptr) -{ - return (uint8_t)I2C_DATA_DATA_GET(ptr->DATA); -} - -/** - * @brief I2C get direction - * - * @note The same value has different meanings in master and slave modes - * - * @param ptr [in] ptr I2C base address - * @return uint8_t direction value - */ -static inline uint8_t i2c_get_direction(I2C_Type *ptr) -{ - return (uint8_t)I2C_CTRL_DIR_GET(ptr->CTRL); -} - -/** - * @brief I2C master configure transfer setting - * - * @param i2c_ptr [in] ptr I2C base address - * @param device_address [in] I2C slave address - * @param size [in] size of data to be transferred in bytes - * @param read [in] true for receive, false for transmit - * @retval hpm_stat_t status_success if configuring transmission without any error - */ -hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read); - -/** - * @brief sequential transmit in master I2C mode an amount of data in blocking - * - * @param [in] ptr ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] buf pointer of the buffer to store data sent from device - * @param [in] size size of data to be sent in bytes - * @param [in] opt I2c sequential transfer options - * @retval hpm_stat_t status_success if transmit is completed without any error - */ -hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt); - -/** - * @brief sequential receive in master I2C mode an amount of data in blocking - * - * @param [in] ptr ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] buf pointer of the buffer to store data sent from device - * @param [in] size size of data to be sent in bytes - * @param [in] opt I2c sequential transfer options - * @retval hpm_stat_t status_success if receive is completed without any error - */ -hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt); - -#if defined(HPM_IP_FEATURE_I2C_SUPPORT_RESET) && (HPM_IP_FEATURE_I2C_SUPPORT_RESET == 1) -/** - * @brief generate SCL clock as reset signal - * - * @param ptr [in] ptr I2C base address - * @param [in] clk_len SCL clock length - */ -static inline void i2s_gen_reset_signal(I2C_Type *ptr, uint8_t clk_len) -{ - ptr->CTRL = (ptr->CTRL & ~I2C_CTRL_RESET_LEN_MASK) | I2C_CTRL_RESET_LEN_SET(clk_len) \ - | I2C_CTRL_RESET_HOLD_SCKIN_MASK | I2C_CTRL_RESET_ON_MASK; -} -#endif - -/** - * @brief data transfer on master I2C mode in blocking - * - * @param [in] ptr ptr I2C base address - * @param [in] device_address I2C slave address - * @param [in] buf pointer of the buffer to store data sent from device - * @param [in] size size of data to be sent in bytes - * @param [in] flags flag bit, which can be other flag bits except I2C_WR I2C_RD, and can perform "|" operation - * @retval hpm_stat_t status_success if receive is completed without any error - */ -hpm_stat_t i2c_master_transfer(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, uint16_t flags); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_I2C_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h deleted file mode 100644 index 146e494c999..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_common.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_I2S_COMMON_H -#define HPM_I2S_COMMON_H - -/** - * @brief I2S common driver APIs - * @defgroup i2s_common_interface I2S common driver APIs - * @ingroup io_interfaces - * @{ - */ - -#define I2S_PROTOCOL_I2S_PHILIPS (0U) -#define I2S_PROTOCOL_MSB_JUSTIFIED (1U) -#define I2S_PROTOCOL_LEFT_JUSTIFIED (1U) -#define I2S_PROTOCOL_LSB_JUSTIFIED (2U) -#define I2S_PROTOCOL_RIGHT_JUSTIFIED (2U) -#define I2S_PROTOCOL_PCM (3U) - -/* i2s channel slot mask */ -#define I2S_CHANNEL_SLOT_MASK(x) (1U << (x)) -/* convert audio depth value into CFGR[DATASIZ] value map */ -#define I2S_CFGR_DATASIZ(x) ((x - 16) >> 3) -/* convert channel length value into CFGR[CHSIZ] value map */ -#define I2S_CFGR_CHSIZ(x) ((x - 16) >> 4) - -/** - * @brief I2S audio depth - */ -enum { - i2s_audio_depth_16_bits = 16, - i2s_audio_depth_24_bits = 24, - i2s_audio_depth_32_bits = 32, -}; - -/** - * @brief I2S channel length - */ -enum { - i2s_channel_length_16_bits = 16, - i2s_channel_length_32_bits = 32, -}; - -/** - * @brief I2S stereo/mono channel - */ -enum { - i2s_mono_left = 0, - i2s_mono_right = 1, - i2s_stereo = 2, -}; - -/** - * @} - */ - -#endif /* HPM_I2S_COMMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h deleted file mode 100644 index 10fbf56312a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2s_drv.h +++ /dev/null @@ -1,682 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_I2S_DRV_H -#define HPM_I2S_DRV_H -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_i2s_regs.h" -#include "hpm_i2s_common.h" - -/** - * @brief I2S driver APIs - * @defgroup i2s_interface I2S driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief I2S data line - */ -#define I2S_DATA_LINE_0 (0U) -#define I2S_DATA_LINE_1 (1U) -#define I2S_DATA_LINE_2 (2U) -#define I2S_DATA_LINE_3 (3U) -#define I2S_DATA_LINE_MAX I2S_DATA_LINE_3 - -/** - * @brief I2S config - */ -typedef struct i2s_config { - bool invert_mclk_out; - bool invert_mclk_in; - bool use_external_mclk; - bool invert_bclk_out; - bool invert_bclk_in; - bool use_external_bclk; - bool invert_fclk_out; - bool invert_fclk_in; - bool use_external_fclk; - bool enable_mclk_out; - bool frame_start_at_rising_edge; - uint16_t tx_fifo_threshold; - uint16_t rx_fifo_threshold; -} i2s_config_t; - -/** - * @brief I2S transfer config - */ -typedef struct i2x_transfer_config { - uint32_t sample_rate; - bool enable_tdm_mode; - uint8_t channel_num_per_frame; - uint8_t channel_length; /* 16-bit or 32-bit */ - uint8_t audio_depth; /* 16-bit, 24-bit, 32-bit */ - bool master_mode; - uint8_t protocol; - uint8_t data_line; - uint32_t channel_slot_mask; -} i2s_transfer_config_t; - -typedef enum { - i2s_tx_fifo_threshold_irq_mask = I2S_CTRL_TXDNIE_MASK, - i2s_rx_fifo_threshold_irq_mask = I2S_CTRL_RXDAIE_MASK, - i2s_fifo_error_irq_mask = I2S_CTRL_ERRIE_MASK, /*CFGR |= I2S_CFGR_TDM_EN_MASK; -} - -/** - * @brief disable TDM - * - * @param [in] ptr I2S base address - */ -static inline void i2s_disable_tdm(I2S_Type *ptr) -{ - ptr->CFGR &= ~I2S_CFGR_TDM_EN_MASK; -} - -/** - * @brief update rx fifo threshold - * - * @param [in] ptr I2S base address - * @param [in] threshold fifo threshold value - */ -static inline void i2s_update_rx_fifo_threshold(I2S_Type *ptr, uint8_t threshold) -{ - ptr->FIFO_THRESH = (ptr->FIFO_THRESH & ~I2S_FIFO_THRESH_RX_MASK) - | I2S_FIFO_THRESH_RX_SET(threshold); -} - -/** - * @brief update tx fifo threshold - * - * @param [in] ptr I2S base address - * @param [in] threshold fifo threshold value - */ -static inline void i2s_update_tx_fifo_threshold(I2S_Type *ptr, uint8_t threshold) -{ - ptr->FIFO_THRESH = (ptr->FIFO_THRESH & ~I2S_FIFO_THRESH_TX_MASK) - | I2S_FIFO_THRESH_TX_SET(threshold); -} - -/** - * @brief open BCLK - * - * @param [in] ptr I2S base address - */ -static inline void i2s_ungate_bclk(I2S_Type *ptr) -{ - ptr->CFGR &= ~I2S_CFGR_BCLK_GATEOFF_MASK; -} - -/** - * @brief gete off BCLK - * - * @param [in] ptr I2S base address - */ -static inline void i2s_gate_bclk(I2S_Type *ptr) -{ - ptr->CFGR |= I2S_CFGR_BCLK_GATEOFF_MASK; -} - -/** - * @brief open MCLK - * - * @param [in] ptr I2S base address - */ -static inline void i2s_ungate_mclk(I2S_Type *ptr) -{ - ptr->MISC_CFGR &= ~I2S_MISC_CFGR_MCLK_GATEOFF_MASK; -} - -/** - * @brief gate off MCLK - * - * @param [in] ptr I2S base address - */ -static inline void i2s_gate_mclk(I2S_Type *ptr) -{ - ptr->MISC_CFGR |= I2S_MISC_CFGR_MCLK_GATEOFF_MASK; -} - -/** - * @brief enable TX dma request - * - * @param [in] ptr I2S base address - */ -static inline void i2s_enable_tx_dma_request(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_TX_DMA_EN_MASK; -} - -/** - * @brief disable TX dma request - * - * @param [in] ptr I2S base address - */ -static inline void i2s_disable_tx_dma_request(I2S_Type *ptr) -{ - ptr->CTRL &= ~I2S_CTRL_TX_DMA_EN_MASK; -} - -/** - * @brief enable RX dma request - * - * @param [in] ptr I2S base address - */ -static inline void i2s_enable_rx_dma_request(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_RX_DMA_EN_MASK; -} - -/** - * @brief disable RX dma request - * - * @param [in] ptr I2S base address - */ -static inline void i2s_disable_rx_dma_request(I2S_Type *ptr) -{ - ptr->CTRL &= ~I2S_CTRL_RX_DMA_EN_MASK; -} - -/** - * @brief enable IRQ - * - * @param [in] ptr I2S base address - * @param [in] mask irq bit mask - */ -static inline void i2s_enable_irq(I2S_Type *ptr, uint32_t mask) -{ - ptr->CTRL |= mask; -} - -/** - * @brief disable IRQ - * - * @param [in] ptr I2S base address - * @param [in] mask irq bit mask - */ -static inline void i2s_disable_irq(I2S_Type *ptr, uint32_t mask) -{ - ptr->CTRL &= ~mask; -} - -/** - * @brief I2S enable - * - * @note dropped API, please use i2s_start - * - * @param [in] ptr I2S base address - */ -static inline void i2s_enable(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_I2S_EN_MASK; -} - -/** - * @brief I2S disable - * - * @note dropped API, please use i2s_stop - * - * @param [in] ptr I2S base address - */ -static inline void i2s_disable(I2S_Type *ptr) -{ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; -} - -/** - * @brief I2S start - * - * @param [in] ptr I2S base address - */ -static inline void i2s_start(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_I2S_EN_MASK; -} - -/** - * @brief I2S stop - * - * @param [in] ptr I2S base address - */ -static inline void i2s_stop(I2S_Type *ptr) -{ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; -} - -/** - * @brief I2S enable rx function - * - * @param [in] ptr I2S base address - * @param [in] rx_mask rx data line mask - */ -static inline void i2s_enable_rx(I2S_Type *ptr, uint8_t rx_mask) -{ - ptr->CTRL |= I2S_CTRL_RX_EN_SET(rx_mask); -} - -/** - * @brief I2S disable rx function - * - * @param [in] ptr I2S base address - * @param [in] rx_mask rx data line mask - */ -static inline void i2s_disable_rx(I2S_Type *ptr, uint8_t rx_mask) -{ - ptr->CTRL &= ~I2S_CTRL_RX_EN_SET(rx_mask); -} - -/** - * @brief I2S enable tx function - * - * @param [in] ptr I2S base address - * @param [in] tx_mask tx data line mask - */ -static inline void i2s_enable_tx(I2S_Type *ptr, uint8_t tx_mask) -{ - ptr->CTRL |= I2S_CTRL_TX_EN_SET(tx_mask); -} - -/** - * @brief I2S disbale tx function - * - * @param [in] ptr I2S base address - * @param [in] tx_mask tx data line mask - */ -static inline void i2s_disable_tx(I2S_Type *ptr, uint8_t tx_mask) -{ - ptr->CTRL &= ~I2S_CTRL_TX_EN_SET(tx_mask); -} - -/** - * @brief I2S reset clock generator - * - * @param [in] ptr I2S base address - */ -static inline void i2s_reset_clock_gen(I2S_Type *ptr) -{ - ptr->CTRL |= I2S_CTRL_SFTRST_CLKGEN_MASK; - ptr->CTRL &= ~I2S_CTRL_SFTRST_CLKGEN_MASK; -} - -/** - * @brief I2S reset tx function - * - * @note This API will disable I2S, reset tx function - * Please ensure that there is a valid BCLK when calling this function - * - * @param [in] ptr I2S base address - */ -static inline void i2s_reset_tx(I2S_Type *ptr) -{ - /* disable I2S */ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; - - /* reset tx and clear fifo */ - ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK); - ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK); -} - -/** - * @brief I2S reset rx function - * - * @note This API will disable I2S, reset rx function - * Please ensure that there is a valid BCLK when calling this function - * - * @param [in] ptr I2S base address - */ -static inline void i2s_reset_rx(I2S_Type *ptr) -{ - /* disable I2S */ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; - - /* reset rx and clear fifo */ - ptr->CTRL |= (I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_RX_MASK); - ptr->CTRL &= ~(I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_RX_MASK); -} - -/** - * @brief I2S reset tx and rx function - * - * @note This API will disable I2S, reset tx/rx function - * Please ensure that there is a valid BCLK when calling this function - * - * @param [in] ptr I2S base address - */ -static inline void i2s_reset_tx_rx(I2S_Type *ptr) -{ - /* disable I2S */ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; - - /* reset tx/rx and clear fifo */ - ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); - ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); -} - -/** - * @brief I2S reset tx/rx and clock generator module - * - * @note This API will disable I2S, reset tx/rx and clock generator module - * This function uses an internal clock to generate BCLK, then do reset operation, - * and finally restores the previous clock settings - * - * @param [in] ptr I2S base address - */ -void i2s_reset_all(I2S_Type *ptr); - -/** - * @brief I2S get tx fifo level - * - * @param [in] ptr I2S base address - * - * @retval I2S tx fifo level - */ -static inline uint32_t i2s_get_tx_fifo_level(I2S_Type *ptr) -{ - return ptr->TFIFO_FILLINGS; -} - -/** - * @brief I2S get data line tx fifo level - * - * @param [in] ptr I2S base address - * @param [in] line I2S data line - * - * @retval I2S data line tx fifo level - */ -static inline uint32_t i2s_get_tx_line_fifo_level(I2S_Type *ptr, uint8_t line) -{ - return (i2s_get_tx_fifo_level(ptr) & (0xFF << (line << 3))) >> (line << 3); -} - -/** - * @brief I2S get rx fifo level - * - * @param [in] ptr I2S base address - * - * @retval I2S rx fifo level - */ -static inline uint32_t i2s_get_rx_fifo_level(I2S_Type *ptr) -{ - return ptr->RFIFO_FILLINGS; -} - -/** - * @brief I2S get data line rx fifo level - * - * @param [in] ptr I2S base address - * @param [in] line I2S data line - * - * @retval I2S data line rx fifo level - */ -static inline uint32_t i2s_get_rx_line_fifo_level(I2S_Type *ptr, uint8_t line) -{ - return (i2s_get_rx_fifo_level(ptr) & (0xFF << (line << 3))) >> (line << 3); -} - -/** - * @brief Check I2S data line status - * - * @param[in] ptr I2S base address - * @param[in] line I2S data line - * - * @retval i2s_data_line_rx_fifo_avail data in rx fifo >= threshold - * @retval i2s_data_line_tx_fifo_avail data in tx fifo <= threshold - * @retval i2s_data_line_rx_fifo_overrun rx fifo overrun occured - * @retval i2s_data_line_tx_fifo_underrun tx fifo underrun occured - */ -static inline uint32_t i2s_check_data_line_status(I2S_Type *ptr, uint8_t line) -{ - volatile uint32_t reg_val = ptr->STA; - uint32_t bit_mask; - uint32_t stat = 0; - - bit_mask = 1 << (I2S_STA_RX_DA_SHIFT + line); - if ((bit_mask & reg_val) != 0) { - stat |= i2s_data_line_rx_fifo_avail; - } - - bit_mask = 1 << (I2S_STA_TX_DN_SHIFT + line); - if ((bit_mask & reg_val) != 0) { - stat |= i2s_data_line_tx_fifo_avail; - } - - bit_mask = 1 << (I2S_STA_RX_OV_SHIFT + line); - if ((bit_mask & reg_val) != 0) { - stat |= i2s_data_line_rx_fifo_overrun; - ptr->STA = bit_mask; /* clear flag: W1C*/ - } - - bit_mask = 1 << (I2S_STA_TX_UD_SHIFT + line); - if ((bit_mask & reg_val) != 0) { - stat |= i2s_data_line_tx_fifo_underrun; - ptr->STA = bit_mask; /* clear flag: W1C*/ - } - - return stat; -} - -/** - * @brief I2S get IRQ status - * - * @param [in] ptr I2S base address - * - * @retval I2S STA register value - */ -static inline uint32_t i2s_get_irq_status(I2S_Type *ptr) -{ - return ptr->STA; -} - -/** - * @brief I2S stop transfer - * - * @param [in] ptr I2S base address - */ -static inline void i2s_stop_transfer(I2S_Type *ptr) -{ - i2s_disable(ptr); -} - -/** - * @brief I2S config tx - * - * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S - * - * @param [in] ptr I2S base address - * @param [in] mclk_in_hz mclk frequency in Hz - * @param [in] config i2s_transfer_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); - -/** - * @brief I2S config tx for slave - * - * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S - * - * @param [in] ptr I2S base address - * @param [in] config i2s_transfer_config_t - */ -hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); - -/** - * @brief I2S config rx - * - * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S - * - * @param [in] ptr I2S base address - * @param [in] mclk_in_hz mclk frequency in Hz - * @param [in] config i2s_transfer_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); - -/** - * @brief I2S config rx for slave - * - * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S - * - * @param [in] ptr I2S base address - * @param [in] config i2s_transfer_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config); - -/** - * @brief I2S config transfer - * - * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S - * - * @param [in] ptr I2S base address - * @param [in] mclk_in_hz mclk frequency in Hz - * @param [in] config i2s_transfer_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config); - -/** - * @brief I2S config transfer for slave - * - * @note This API will disable I2S and configure parameters, could call i2s_enable() to enable I2S - * - * @param [in] ptr I2S base address - * @param [in] config i2s_transfer_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t i2s_config_transfer_slave(I2S_Type *ptr, i2s_transfer_config_t *config); - -/** - * @brief I2S send data - * - * @param [in] ptr I2S base address - * @param [in] tx_line_index data line - * @param [in] data data to be written - */ -static inline void i2s_send_data(I2S_Type *ptr, uint8_t tx_line_index, uint32_t data) -{ - ptr->TXD[tx_line_index] = data; -} - -/** - * @brief I2S receive data - * - * @param [in] ptr I2S base address - * @param [in] rx_line_index data line - * @param [out] data point to store data address - */ -static inline void i2s_receive_data(I2S_Type *ptr, uint8_t rx_line_index, uint32_t *data) -{ - *data = ptr->RXD[rx_line_index]; -} - -/** - * @brief I2S send data in buff - * - * @param [in] ptr I2S base address - * @param [in] tx_line_index data line - * @param [in] samplebits audio data width - * @param [in] src source data buff - * @param [in] size data size - * - * @retval I2S sent data size in byte - */ -uint32_t i2s_send_buff(I2S_Type *ptr, uint8_t tx_line_index, uint8_t samplebits, uint8_t *src, uint32_t size); - -/** - * @brief I2S receive data in buff - * - * @param [in] ptr I2S base address - * @param [in] rx_line_index data line - * @param [in] samplebits audio data width - * @param [out] dst target data buff - * @param [in] size data size - * - * @retval I2S sent data size in byte - */ -uint32_t i2s_receive_buff(I2S_Type *ptr, uint8_t rx_line_index, uint8_t samplebits, uint8_t *dst, uint32_t size); - -/** - * @brief I2S get default config - * - * @param [in] ptr I2S base address - * @param [out] config i2s_config_t - */ -void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config); - -/** - * @brief I2S initialization - * - * @param [in] ptr I2S base address - * @param [in] config i2s_config_t - */ -void i2s_init(I2S_Type *ptr, i2s_config_t *config); - -/** - * @brief I2S get default transfer config for pdm - * - * @param [out] transfer i2s_transfer_config_t - */ -void i2s_get_default_transfer_config_for_pdm(i2s_transfer_config_t *transfer); - -/** - * @brief I2S get default transfer config for dao - * - * @param [out] transfer i2s_transfer_config_t - */ -void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer); - -/** - * @brief I2S get default transfer config - * - * @param [out] transfer i2s_transfer_config_t - */ -void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer); - -/** - * @brief I2S fill dummy data into TX fifo - * - * @note workaround: fill dummy data into TX fifo to avoid TX underflow during tx start - * - * @param [in] ptr I2S base address - * @param [in] data_line data line - * @param [in] data_count dummy data count, This value should be the same as the number of audio channels - * - * @retval status_success if no error occurred - */ -hpm_stat_t i2s_fill_tx_dummy_data(I2S_Type *ptr, uint8_t data_line, uint8_t data_count); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_I2S_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h deleted file mode 100644 index f7e3ed9e207..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_jpeg_drv.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_JPEG_DRV_H -#define HPM_JPEG_DRV_H - -#include "hpm_common.h" -#include "hpm_jpeg_regs.h" - -/** - * @brief Jpeg driver APIs - * @defgroup Jpeg_interface JPEG driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Define events of the jpeg module - */ -#define JPEG_EVENT_BUSY JPEG_STAT_BUSY_MASK -#define JPEG_EVENT_OUT_DMA_FINISH JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK -#define JPEG_EVENT_IN_DMA_FINISH JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK -#define JPEG_EVENT_ERROR (JPEG_STAT_RESTART_MARKER_ERROR_MASK | (0xF << 7)) - -/** - * @brief byte order in a word - */ -#define JPEG_BYTE_ORDER_3210 (0U) /**< no order change, {A3, A2, A1, A0} */ -#define JPEG_BYTE_ORDER_2301 (1U) /**< order change, {A2, A3, A0, A1} */ -#define JPEG_BYTE_ORDER_1032 (2U) /**< order change, {A1, A0, A2, A3} */ -#define JPEG_BYTE_ORDER_0123 (3U) /**< order change, {A0, A1, A2, A3} */ - -/** - * @brief jpeg pixel conversion format - */ - - -/** - * @brief jpeg data format definition - */ -#define JPEG_SUPPORTED_FORMAT_420 (0U) /**< hy=2, vy=2, hc=1, vc=1 */ -#define JPEG_SUPPORTED_FORMAT_422H (1U) /**< hy=2, vy=1, hc=1, vc=1 */ -#define JPEG_SUPPORTED_FORMAT_422V (2U) /**< hy=1, vy=2, hc=1, vc=1 */ -#define JPEG_SUPPORTED_FORMAT_444 (3U) /**< hy=1, vy=1, hc=1, vc=1 */ -#define JPEG_SUPPORTED_FORMAT_400 (4U) /**< hy=2, vy=2, hc=0, vc=0 */ - -/** - * @brief data format definition - */ -typedef struct { - uint8_t hy:2; /**< bit: 1-0 --> horizontal y component */ - uint8_t vy:2; /**< bit: 3-2 --> Vertical y component */ - uint8_t hc:2; /**< bit: bit: 5-4 --> horizontal c component */ - uint8_t vc:2; /**< bit: 7-6 --> Vertical c component */ -} jpeg_sampling_t; - -typedef struct { - uint8_t pixel_width; - uint8_t ipath; - uint8_t opath; - bool is_rgb; -} jpeg_pixel_t; - -/** - * @brief jpeg encoding and decoding configuration parameters - * @arg bit: 31-27 --> name - * @arg bit: 26-23 --> WIDTH IN BYTE - * @arg bit: 22-3 --> ELEMENT COUNT - * @arg bit: 2-0 --> TYPE - */ -typedef enum jpeg_table { - jpeg_table_qmem = 0x201002, /**< definition Decoder and Encoder Q. values */ - jpeg_table_huffenc = 0x201803, /**< definition Huffman Encoder table */ - jpeg_table_huffmin = 0x400104, /**< definition Huffman min values */ - jpeg_table_huffbase = 0x200405, /**< definition Huffman BASE mem values */ - jpeg_table_huffsymb = 0x101506, /**< definition Huffman SYMB mem values */ -} jpeg_table_t; - -typedef enum jpeg_pixel_format { - jpeg_pixel_format_argb8888 = 0, - jpeg_pixel_format_rgb565, - jpeg_pixel_format_yuv422h1p, - jpeg_pixel_format_yuv422h2p, - jpeg_pixel_format_yuv420, - jpeg_pixel_format_y8, -} jpeg_pixel_format_t; - -/** - * @brief jpeg encoding and decoding configuration parameters - */ -typedef struct { - uint8_t jpeg_format; /**< supported jpeg format */ - jpeg_pixel_format_t in_pixel_format; - jpeg_pixel_format_t out_pixel_format; - uint8_t in_byte_order; /**< byte order */ - uint8_t out_byte_order; /**< byte order */ - bool enable_ycbcr; /**< enable YCbCr or YUV */ - uint16_t width_in_pixel; /**< Image width register*/ - uint16_t height_in_pixel; /**< Image height register*/ - uint32_t in_buffer; /**< input buffer */ - uint32_t out_buffer; /**< output buffer */ -} jpeg_job_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief clear jpeg cfg Register - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -static inline void jpeg_clear_cfg(JPEG_Type *ptr) -{ - ptr->CFG = 0; -} - -/** - * @brief jpeg function disable - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -static inline void jpeg_disable(JPEG_Type *ptr) -{ - ptr->CFG &= ~JPEG_CFG_JPEG_EN_MASK; -} - -/** - * @brief jpeg function enable - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -static inline void jpeg_enable(JPEG_Type *ptr) -{ - ptr->CFG |= JPEG_CFG_JPEG_EN_MASK; -} - -/** - * @brief stop a encoder/decoder conversion - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -static inline void jpeg_stop(JPEG_Type *ptr) -{ - ptr->CFG &= ~JPEG_CFG_START_MASK; -} - -/** - * @brief start a new encoder/decoder conversion - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -static inline void jpeg_start(JPEG_Type *ptr) -{ - ptr->CFG |= JPEG_CFG_START_MASK; -} - -/** - * @brief obtain jpeg Status Register - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @retval jpeg register's status - */ -static inline uint32_t jpeg_get_status(JPEG_Type *ptr) -{ - return ptr->STAT; -} - -/** - * @brief clear jpeg Status Register - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @param [in] mask - * @arg JPEG_EVENT_BUSY: the module is busy doing conversion and data transfer - * @arg JPEG_EVENT_OUT_DMA_FINISH: OutDMA process done - * @arg JPEG_EVENT_IN_DMA_FINISH: InDMA process done - * @arg JPEG_EVENT_ERROR: the axi err - * - */ -static inline void jpeg_clear_status(JPEG_Type *ptr, uint32_t mask) -{ - ptr->STAT |= mask; -} - -/** - * @brief Out DMA Bytes Counter - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @retval The out DMA counter - */ -static inline uint32_t jpeg_get_encoded_length(JPEG_Type *ptr) -{ - return JPEG_OUTDMACNT_VAL_GET(ptr->OUTDMACNT); -} - -/** - * @brief jpeg Software Reset - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -static inline void jpeg_software_reset(JPEG_Type *ptr) -{ - ptr->CFG |= JPEG_CFG_JPEG_SFTRST_MASK; - ptr->CFG &= ~JPEG_CFG_JPEG_SFTRST_MASK; -} - -/** - * @brief stop a encoder/decoder conversion and Software Reset - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -void jpeg_reset(JPEG_Type *ptr); - -/** - * @brief jpeg enable interrupt - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @param [in] mask - * @arg JPEG_EVENT_IN_DMA_FINISH: In DMA Done enable - * @arg JPEG_EVENT_OUT_DMA_FINISH: interrupt enable for all interrupt sources of In DMA module - * @arg JPEG_EVENT_ERROR: The jpg endec restart error interrupt enable - * - */ -void jpeg_enable_irq(JPEG_Type *ptr, uint32_t mask); - -/** - * @brief jpeg disable interrupt - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @param [in] mask - * @arg JPEG_EVENT_IN_DMA_FINISH: In DMA Done disable - * @arg JPEG_EVENT_OUT_DMA_FINISH: interrupt disable for all interrupt sources of In DMA module - * @arg JPEG_EVENT_ERROR: The jpg endec restart error interrupt disable - * - */ -void jpeg_disable_irq(JPEG_Type *ptr, uint32_t mask); - -/** - * @brief stop a encoder/decoder conversion and Software Reset - * - * @param [in] ptr JPEG base address, HPM_JPEG - */ -void jpeg_init(JPEG_Type *ptr); - -/** - * @brief fill tables for jpeg controller - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @param [in] table - * @arg jpeg_table_qmem: file describe for Decoder and Encoder Q. values - * @arg jpeg_table_huffenc: file describe for Huffman Encoder table - * @arg jpeg_table_huffmin: file describe for Huffman min values - * @arg jpeg_table_huffbase: file describe for Huffman BASE mem values - * @arg jpeg_table_huffsymb: file describe for Huffman SYMB mem values - * @param [in] data - * @arg huffenc: data for Huffman Encoder table - * @arg huffmin: data for Huffman min values - * @arg huffbase: data for Huffman BASE mem values - * @arg huffsymb: data for Huffman SYMB mem values - * @arg qetable: data for Encoder Q. values - * @arg qdtable: data for Decoder Q. values - * @param [in] count data length - * @retval fill tables's status - * - */ -hpm_stat_t jpeg_fill_table(JPEG_Type *ptr, jpeg_table_t table, uint8_t *data, uint32_t count); - -/** - * @brief it will start decoding, and the process status needs to be checked by - * querying JPEG_EVENT - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @param [in] config config A pointer to the configuration struct of "jpeg_job_config_t" - * @param [in] length Decoded data length - * @retval jpeg decoding's status - * - */ -hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, jpeg_job_config_t *config, uint32_t length); - -/** - * @brief * it will start encoding, and the process status needs to be checked by - * querying JPEG_EVENT - * - * @param [in] ptr JPEG base address, HPM_JPEG - * @param [in] config config A pointer to the configuration struct of "jpeg_job_config_t" - * @retval jpeg encoding's status - * - */ -hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config); - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif -#endif /* HPM_JPEG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcb_drv.h deleted file mode 100644 index 2dae9197cfc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcb_drv.h +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_LCB_DRV_H -#define HPM_LCB_DRV_H - -/** - * @brief LCB APIs - * @defgroup lcb_interface LCB driver APIs - * @ingroup lcb_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_lcb_regs.h" - -typedef enum lcb_rxclk_sel { - lcb_rxclk_sel_phy0 = 0, - lcb_rxclk_sel_phy1 = 1, -} lcb_rxclk_sel_t; - -typedef enum lcb_mode { - lcb_mode_display = 0, - lcb_mode_cam_link = 1, -} lcb_mode_t; - -typedef enum lcb_display_mode_mapping { - lcb_display_mode_mapping_vesa = 0, - lcb_display_mode_mapping_jeida = 1, -} lcb_display_mode_mapping_t; - -typedef enum lcb_display_mode_data_width { - lcb_display_mode_data_width_18bit = 0, - lcb_display_mode_data_width_24bit = 1, -} lcb_display_mode_data_width_t; - -typedef struct lcb_display_mode_config { - lcb_display_mode_mapping_t map; - lcb_display_mode_data_width_t data_width; -} lcb_display_mode_config_t; - -typedef enum lcb_cam_link_mode_data_width { - lcb_cam_link_mode_data_width_24bit = 0, - lcb_cam_link_mode_data_width_30bit = 1, - lcb_cam_link_mode_data_width_36bit = 1, -} lcb_cam_link_mode_data_width_t; - -typedef struct lcb_cam_link_mode_config { - lcb_cam_link_mode_data_width_t data_width; -} lcb_cam_link_mode_config_t; - -typedef struct lcb_config { - lcb_rxclk_sel_t rxclk_sel; - lcb_mode_t mode; - union { - lcb_display_mode_config_t display; - lcb_cam_link_mode_config_t cam_link; - }; -} lcb_config_t; - -/** - * @brief Terminal impedance regulation - */ -typedef enum lcb_lvds_phy_rterm { - lcb_lvds_phy_rterm_hi_z = 0, - lcb_lvds_phy_rterm_150_ohm = 1, - lcb_lvds_phy_rterm_100_ohm = 8, - lcb_lvds_phy_rterm_75_ohm = 15, -} lcb_lvds_phy_rterm_t; - -typedef struct lcb_lvds_phy_data_lane_config { - uint8_t dline_adj; /*!< Lane N skew adjustment value between data and clock. 0000000: max; 1111111: min */ - lcb_lvds_phy_rterm_t rterm; /*!< Terminal impedance regulation */ -} lcb_lvds_phy_data_lane_config_t; - -/** - * @brief DLL loop delay adjustment minimum frequency - */ -typedef enum lcb_lvds_phy_dll_delay_adj_min_freq { - lcb_lvds_phy_dll_delay_adj_min_freq_40_70mhz = 0, - lcb_lvds_phy_dll_delay_adj_min_freq_70_110mhz = 0, -} lcb_lvds_phy_dll_delay_adj_min_freq_t; - -typedef struct lcb_lvds_phy_clk_lane_config { - lcb_lvds_phy_dll_delay_adj_min_freq_t min_adj; - uint16_t dll_tuning_int; /*!< DLL loop delay coarse adjustment initial value. 00000000: min ; 11111111: max */ - lcb_lvds_phy_rterm_t rterm; /*!< Terminal impedance regulation */ -} lcb_lvds_phy_clk_lane_config_t; - -typedef enum lcb_lvds_phy_data_lane_id { - lcb_lvds_phy_data_lane_id_0 = 0, - lcb_lvds_phy_data_lane_id_1 = 1, -} lcb_lvds_phy_data_lane_id_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief get LCB of default config - * - * @param[out] cfg config of LCB - */ -void lcb_get_default_config(lcb_config_t *cfg); - -/** - * @brief LCB init - * - * @param[in] ptr LCB base address - * @param[in] cfg config of LCB - */ -void lcb_init(LCB_Type *ptr, lcb_config_t *cfg); - -/** - * @brief get LCB clk_lane of default config - * - * @param[out] cfg config of clk_lane - */ -void lcb_get_phy_clk_lane_default_config(lcb_lvds_phy_clk_lane_config_t *cfg); - -/** - * @brief get LCB data_lane of default config - * - * @param[out] cfg config of data_lane - */ -void lcb_get_phy_data_lane_default_config(lcb_lvds_phy_data_lane_config_t *cfg); - -/** - * @brief LCB phy0 data lane config - * - * @param[in] ptr LCB base address - * @param[in] cfg config of phy0 data lane - * @param[in] lane_id data lane id - */ -void lcb_lvds_phy0_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id); - -/** - * @brief LCB phy0 clk lane config - * - * @param[in] ptr LCB base address - * @param[in] cfg config of phy0 clk lane - */ -void lcb_lvds_phy0_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg); - -/** - * @brief LCB phy1 data lane config - * - * @param[in] ptr LCB base address - * @param[in] cfg config of phy1 data lane - * @param[in] lane_id data lane id - */ -void lcb_lvds_phy1_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id); - -/** - * @brief LCB phy1 clk lane config - * - * @param[in] ptr LCB base address - * @param[in] cfg config of phy1 clk lane - */ -void lcb_lvds_phy1_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg); - -/** - * @brief power on LCB phy0 - * - * @param[in] ptr LCB base address - */ -void lcb_lvds_phy0_poweron(LCB_Type *ptr); - -/** - * @brief power on LCB phy1 - * - * @param[in] ptr LCB base address - */ -void lcb_lvds_phy1_poweron(LCB_Type *ptr); - -/** - * @brief power down LCB phy0 - * - * @param[in] ptr LCB base address - */ -void lcb_lvds_phy0_powerdown(LCB_Type *ptr); - -/** - * @brief power on LCB phy1 - * - * @param[in] ptr LCB base address - */ -void lcb_lvds_phy1_powerdown(LCB_Type *ptr); - -/** - * @brief check LCB phy0 is lock - * - * @param[in] ptr LCB base address - */ -static inline bool lcb_lvds_phy0_dll_is_lock(LCB_Type *ptr) -{ - return !!LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT); -} - -/** - * @brief check LCB phy1 is lock - * - * @param[in] ptr LCB base address - */ -static inline bool lcb_lvds_phy1_dll_is_lock(LCB_Type *ptr) -{ - return !!LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT); -} - -/** - * @brief check LCB display phy is lock - * - * @param[in] ptr LCB base address - */ -static inline bool lcb_lvds_display_phy_dll_is_lock(LCB_Type *ptr) -{ - return !!LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT) && - !!LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(ptr->PHY_STAT); -} - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_LCB_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h deleted file mode 100644 index 6f51010acca..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h +++ /dev/null @@ -1,477 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LCDC_DRV_H -#define HPM_LCDC_DRV_H -#include "hpm_display_common.h" -#include "hpm_soc_feature.h" -#include "hpm_lcdc_regs.h" - -/** - * - * @brief LCD driver APIs - * @defgroup lcd_interface LCD driver APIs - * @ingroup io_interfaces - * @{ - */ - -#define LCDC_TEST_MODE_DISABLE (0U) -#define LCDC_TEST_MODE_BACKGROUND (1U) -#define LCDC_TEST_MODE_COLOR_BAR_COL (2U) -#define LCDC_TEST_MODE_COLOR_BAR_ROW (3U) - -/* @brief LCD driver specific status */ -enum { - status_lcdc_no_active_layer_yet = MAKE_STATUS(status_group_lcdc, 1), - status_lcdc_layer_not_supported = MAKE_STATUS(status_group_lcdc, 2), -}; - -/* @brief LCD line pattern */ -typedef enum lcdc_line_pattern { - lcdc_line_pattern_rgb = 0, - lcdc_line_pattern_rbg, - lcdc_line_pattern_gbr, - lcdc_line_pattern_grb, - lcdc_line_pattern_brg, - lcdc_line_pattern_bgr, -} lcdc_line_pattern_t; - -/* @brief LCD display mode */ -typedef enum lcdc_display_mode { - lcdc_display_mode_normal = 0, - lcdc_display_mode_test_mode_1, - lcdc_display_mode_test_mode_2, - lcdc_display_mode_test_mode_3, -} lcdc_display_mode_t; - -/* @brief LCD layer transfer max bytes */ -typedef enum lcdc_layer_max_bytes_per_transfer { - lcdc_layer_max_bytes_64 = 0, - lcdc_layer_max_bytes_128, - lcdc_layer_max_bytes_256, - lcdc_layer_max_bytes_512, - lcdc_layer_max_bytes_1024, -} lcdc_layer_max_bytes_per_transfer_t; - -/* @brief LCD control */ -typedef struct lcdc_control { - lcdc_line_pattern_t line_pattern; /**< Line pattern setting */ - lcdc_display_mode_t display_mode; /**< Display mode setting */ - bool invert_pixel_data; /**< Invert pixel data level */ - bool invert_pixel_clock; /**< Invert pixel clock level */ - bool invert_href; /**< Invert href level */ - bool invert_vsync; /**< Invert vsync level */ - bool invert_hsync; /**< Invert hsync level */ -} lcdc_control_t; - -/* @brief LCD hsync/vsync config */ -typedef struct lcdc_xsync_config { - uint16_t front_porch_pulse; /**< Front porch pulse */ - uint16_t back_porch_pulse; /**< Back porch pulse */ - uint16_t pulse_width; /**< Pulse width */ -} lcdc_xsync_config_t; - -/* @brief LCD config */ -typedef struct lcdc_config { - uint16_t resolution_x; /**< Horizontal resolution in pixel */ - uint16_t resolution_y; /**< Vertial resolution in pixel */ - lcdc_xsync_config_t hsync; /**< Hsync config */ - lcdc_xsync_config_t vsync; /**< Vsync config */ - display_color_32b_t background; /**< Background color */ - lcdc_control_t control; /**< LCD control */ -} lcdc_config_t; - -/* @brief LCD layer config */ -typedef struct lcdc_layer_config { - uint8_t max_ot; /**< Maximum outstanding transfer */ - display_byteorder_t byteorder; /**< Byte order */ - display_yuv_format_t yuv; /**< YUV format */ - display_pixel_format_t pixel_format; /**< Pixel format */ - display_alphablend_option_t alphablend; /**< Alphablending option */ - display_yuv2rgb_config_t csc_config; /**< Color space conversion config */ - lcdc_layer_max_bytes_per_transfer_t max_bytes; /**< Layer max transfer bytes */ - uint16_t height; /**< Layer height in pixel */ - uint16_t width; /**< Layer width in pixel */ - uint16_t position_x; /**< Layer output position X coord */ - uint16_t position_y; /**< Layer output position Y coord */ - display_color_32b_t background; /**< Background color */ - uint32_t buffer; /**< Pointer of layer display buffer */ - uint32_t stride; /**< stride of lines in bytes. stride is calculated by driver if stride == 0. */ -} lcdc_layer_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * - * @brief Layer config - * - * @param[in] ptr LCD base address - */ -static inline void lcdc_software_reset(LCDC_Type *ptr) -{ - ptr->CTRL |= LCDC_CTRL_SW_RST_MASK; - ptr->CTRL &= ~LCDC_CTRL_SW_RST_MASK; -} - -/** - * - * @brief Enable interrupt according to the given mask - * - * @param[in] ptr LCD base address - * @param[in] interrupt_mask Mask of interrupts to be enabled - */ -static inline void lcdc_enable_interrupt(LCDC_Type *ptr, uint32_t interrupt_mask) -{ - ptr->INT_EN |= interrupt_mask; -} - -/** - * - * @brief Disable interrupt according to the given mask - * - * @param[in] ptr LCD base address - * @param[in] interrupt_mask Mask of interrupts to be disabled - */ -static inline void lcdc_disable_interrupt(LCDC_Type *ptr, uint32_t interrupt_mask) -{ - ptr->INT_EN &= ~interrupt_mask; -} - -/** - * - * @brief Clear specific status according to the given mask - * - * @param[in] ptr LCD base address - * @param[in] mask Status mask of status to be cleared - */ -static inline void lcdc_clear_status(LCDC_Type *ptr, uint32_t mask) -{ - ptr->ST = mask; -} - -/** - * - * @brief Make layer control shadow registers take effect - * - * @param[in] ptr LCD base address - * @param[in] layer_index Index of layer to be controlled - */ -static inline bool lcdc_layer_control_shadow_loaded(LCDC_Type *ptr, uint8_t layer_index) -{ - return !(ptr->LAYER[layer_index].LAYCTRL & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK); -} - -/** - * - * @brief Get DMA status - * - * @param[in] ptr LCD base address - * @retval DMA status - */ -static inline uint32_t lcdc_get_dma_status(LCDC_Type *ptr) -{ - return ptr->DMA_ST; -} - -/** - * - * @brief Check DMA status against the given mask - * - * @param[in] ptr LCD base address - * @param[in] mask Mask of expected DMA status - * @retval true if all bits set to 1 in mask are set - * @retval false if any bit set to 1 in mask is not set - */ -static inline bool lcdc_check_dma_status(LCDC_Type *ptr, uint32_t mask) -{ - return ((ptr->DMA_ST & mask) == mask); -} - -/** - * - * @brief Clear DMA status according to the given mask - * - * @param[in] ptr LCD base address - * @param[in] mask Mask of expected DMA status - */ -static inline void lcdc_clear_dma_status(LCDC_Type *ptr, uint32_t mask) -{ - ptr->DMA_ST = mask; -} - -/** - * - * @brief Get status - * - * @param[in] ptr LCD base address - * @retval current status - */ -static inline uint32_t lcdc_get_status(LCDC_Type *ptr) -{ - return ptr->ST; -} - -/** - * - * @brief Check status against the given mask - * - * @param[in] ptr LCD base address - * @param[in] mask Mask of expected status - * @retval true if all bits set to 1 in mask are set - * @retval false if any bit set to 1 in mask is not set - */ -static inline bool lcdc_check_status(LCDC_Type *ptr, uint32_t mask) -{ - return (ptr->ST & mask) == mask; -} - -/** - * - * @brief Set next buffer for certain layer - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - * @param[in] buffer display buffer to be set - */ -static inline void lcdc_layer_set_next_buffer(LCDC_Type *ptr, uint32_t layer_index, uint32_t buffer) -{ - ptr->LAYER[layer_index].START0 = LCDC_LAYER_START0_ADDR0_SET(buffer); - ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Update specific layer background - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - * @param[in] background color to be set as background - */ -static inline void lcdc_layer_update_background(LCDC_Type *ptr, - uint8_t layer_index, display_color_32b_t background) -{ - ptr->LAYER[layer_index].BG_CL = LCDC_LAYER_BG_CL_ARGB_SET(background.u); - ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Update specific layer position - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - * @param[in] x Position X coord - * @param[in] y Position Y coord - */ -static inline void lcdc_layer_update_position(LCDC_Type *ptr, - uint8_t layer_index, uint16_t x, uint32_t y) -{ - ptr->LAYER[layer_index].LAYPOS = LCDC_LAYER_LAYPOS_X_SET(x) - | LCDC_LAYER_LAYPOS_Y_SET(y); - ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Update specific layer dimension - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - * @param[in] width Width in pixel - * @param[in] height Height in pixel - */ -static inline void lcdc_layer_update_dimension(LCDC_Type *ptr, - uint8_t layer_index, uint8_t width, uint8_t height) -{ - ptr->LAYER[layer_index].LAYSIZE = LCDC_LAYER_LAYSIZE_WIDTH_SET(width) - | LCDC_LAYER_LAYSIZE_HEIGHT_SET(height); - ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Update specific layer region - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - * @param[in] x1 X coord of the top left pixel - * @param[in] y1 Y coord of the top left pixel - * @param[in] x2 X coord of the bottom right pixel - * @param[in] y2 Y coord of the bottom right pixel - */ -static inline void lcdc_layer_set_region(LCDC_Type *ptr, uint8_t layer_index, - uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2) -{ - ptr->LAYER[layer_index].LAYPOS = LCDC_LAYER_LAYPOS_X_SET(x1) - | LCDC_LAYER_LAYPOS_Y_SET(y1); - ptr->LAYER[layer_index].LAYSIZE = LCDC_LAYER_LAYSIZE_WIDTH_SET(x2 - x1 + 1) - | LCDC_LAYER_LAYSIZE_HEIGHT_SET(y2 - y1 + 1); - ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Update specific layer configuration - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - */ -static inline void lcdc_layer_update(LCDC_Type *ptr, uint8_t layer_index) -{ - ptr->LAYER[layer_index].LAYCTRL |= LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Enable specific layer - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - */ -static inline void lcdc_layer_enable(LCDC_Type *ptr, uint32_t layer_index) -{ - ptr->LAYER[layer_index].LAYCTRL |= - (LCDC_LAYER_LAYCTRL_EN_MASK | LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK); -} - -/** - * - * @brief Disable specific layer - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - */ -static inline void lcdc_layer_disable(LCDC_Type *ptr, uint32_t layer_index) -{ - ptr->LAYER[layer_index].LAYCTRL = - (ptr->LAYER[layer_index].LAYCTRL & (~LCDC_LAYER_LAYCTRL_EN_MASK)) - | LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; -} - -/** - * - * @brief Set test mode - * - * @param[in] ptr LCD base address - * @param[in] test_mode target test mode to be enabled - */ -static inline void lcdc_set_testmode(LCDC_Type *ptr, uint8_t test_mode) -{ - ptr->CTRL = ((ptr->CTRL & ~LCDC_CTRL_DISP_MODE_MASK)) - | LCDC_CTRL_DISP_MODE_SET(test_mode) - | LCDC_CTRL_DISP_ON_MASK; -} - -/** - * - * @brief Set background - * - * @param[in] ptr LCD base address - * @param[in] color background color - */ -static inline void lcdc_set_background(LCDC_Type *ptr, - display_color_32b_t color) -{ - ptr->BGND_CL = LCDC_BGND_CL_R_SET(color.r) - | LCDC_BGND_CL_G_SET(color.g) - | LCDC_BGND_CL_B_SET(color.b); -} - -/** - * - * @brief enable background on alpha blender - * - * @note it not depend the background color of the layer itself. it can be used with lcdc_set_background API - * - * @param[in] ptr LCD base address - */ -static inline void lcdc_enable_background_in_alpha_blender(LCDC_Type *ptr) -{ - ptr->CTRL |= LCDC_CTRL_BGDCL4CLR_MASK; -} - -/** - * - * @brief disable background on alpha blender - * - * @note if not use background but want depend the the background color of the layer itself, can be use the API - * - * @param[in] ptr LCD base address - */ -static inline void lcdc_disable_background_in_alpha_blender(LCDC_Type *ptr) -{ - ptr->CTRL &= ~LCDC_CTRL_BGDCL4CLR_MASK; -} -/** - * - * @brief Get default layer configuration value - * - * @param[in] ptr LCD base address - * @param[out] layer Pointer of layer configuration struct buffer - * @param[in] pixel_format Pixel format to be used for this layer - * @param[in] layer_index target layer to be configured - */ -void lcdc_get_default_layer_config(LCDC_Type *ptr, - lcdc_layer_config_t *layer, display_pixel_format_t pixel_format, uint8_t layer_index); - -/** - * - * @brief Get default configuration value - * - * @param[in] ptr LCD base address - * @param[out] config Pointer of configuration struct buffer - */ -void lcdc_get_default_config(LCDC_Type *ptr, lcdc_config_t *config); - -/** - * - * @brief Initialize LCD controller - * - * @param[in] ptr LCD base address - * @param[in] config Pointer of configuration struct buffer - */ -void lcdc_init(LCDC_Type *ptr, lcdc_config_t *config); - -/** - * - * @brief Configure specific layer - * - * @param[in] ptr LCD base address - * @param[in] layer_index target layer to be configured - * @param[in] layer_config Pointer of layer configuration struct buffer - * @param[in] enable_layer Set true if the layer needs to be enabled right after being configured - */ -hpm_stat_t lcdc_config_layer(LCDC_Type *ptr, uint8_t layer_index, - lcdc_layer_config_t *layer_config, bool enable_layer); - -/** - * - * @brief Turn on display - * - * @param[in] ptr LCD base address - */ -void lcdc_turn_on_display(LCDC_Type *ptr); - -/** - * - * @brief Turn off display - * - * @param[in] ptr LCD base address - */ -void lcdc_turn_off_display(LCDC_Type *ptr); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_LCDC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h deleted file mode 100644 index b9cf437a79b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lin_drv.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_LIN_DRV_H -#define HPM_LIN_DRV_H - -#include -#include "hpm_common.h" -#include "hpm_lin_regs.h" -#include "hpm_soc_feature.h" - -/** bit4 and bit5 encode data length in ID */ -#define LIN_ID_DATA_LEN_SHIFT 4U -#define LIN_ID_DATA_LEN_MASK 0x30U -#define LIN_ID_DATA_LEN_GET(x) (((uint8_t)(x) & LIN_ID_DATA_LEN_MASK) >> LIN_ID_DATA_LEN_SHIFT) - -/** - * @brief LIN driver APIs - * @defgroup lin_interface LIN driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief data length in ID bit4 and bit5 - */ -typedef enum { - id_data_length_2bytes, - id_data_length_2bytes_2, /**< both 0 and 1 represent 2 bytes */ - id_data_length_4bytes, - id_data_length_8bytes -} lin_id_data_length_t; - -/** - * @brief bus inactivity tome to go to sleep - */ -typedef enum { - bus_inactivity_time_4s, - bus_inactivity_time_6s, - bus_inactivity_time_8s, - bus_inactivity_time_10s -} lin_bus_inactivity_time_t; - -/** - * @brief wakeup repeat time - */ -typedef enum { - wakeup_repeat_time_180ms, - wakeup_repeat_time_200ms, - wakeup_repeat_time_220ms, - wakeup_repeat_time_240ms -} lin_wakeup_repeat_time_t; - -typedef struct { - uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ - uint32_t baudrate; /**< Baudrate */ -} lin_timing_t; - -/** - * @brief LIN config - */ -typedef struct { - uint8_t id; /**< ID */ - uint8_t *data_buff; /**< data buff */ - bool data_length_from_id; /**< data length should be decoded from the identifier or not) */ - uint8_t data_length; /**< used when data_length_from_id is false */ - bool enhanced_checksum; /**< true for enhanced checksum; false for classic checksum */ - bool transmit; /**< true for transmit operation; false for receive operation */ - /* bool start; */ /**< true for start operation; false for only configuration */ -} lin_trans_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief lin get STATE register value - * - * @param [in] ptr lin base address - * @return uint8_t STATE register value - */ -static inline uint8_t lin_get_status(LIN_Type *ptr) -{ - return ptr->STATE; -} - -/** - * @brief lin reset interrupt - * - * @param ptr lin base address - */ -static inline void lin_reset_interrupt(LIN_Type *ptr) -{ - ptr->CONTROL |= LIN_CONTROL_RESET_INT_MASK; -} - -/** - * @brief lin reset error - * - * @param ptr lin base address - */ -static inline void lin_reset_error(LIN_Type *ptr) -{ - ptr->CONTROL |= LIN_CONTROL_RESET_ERROR_MASK; -} - -/** - * @brief lin wakeup - * - * @param ptr lin base address - */ -static inline void lin_wakeup(LIN_Type *ptr) -{ - ptr->CONTROL |= LIN_CONTROL_WAKEUP_REQ_MASK; -} - -/** - * @brief lin sleep - * - * @param ptr lin base address - */ -static inline void lin_sleep(LIN_Type *ptr) -{ - ptr->CONTROL |= LIN_CONTROL_SLEEP_MASK; -} - -/** - * @brief lin slave stop - * - * @param ptr lin base address - */ -static inline void lin_slave_stop(LIN_Type *ptr) -{ - ptr->CONTROL |= LIN_CONTROL_STOP_MASK; -} - -/** - * @brief lin slave ack - * - * @param ptr lin base address - */ -static inline void lin_slave_ack(LIN_Type *ptr) -{ - ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; -} - -/** - * @brief lin slave set bus inactivity time - * - * @param ptr lin base address - * @param time lin_bus_inactivity_time_t - */ -static inline void lin_slave_set_bus_inactivity_time(LIN_Type *ptr, lin_bus_inactivity_time_t time) -{ - ptr->TV |= LIN_TV_BUS_INACTIVITY_TIME_SET(time); -} - -/** - * @brief lin slave set wakeup repeat time - * - * @param ptr lin base address - * @param time lin_wakeup_repeat_time_t - */ -static inline void lin_slave_set_wakeup_repeat_time(LIN_Type *ptr, lin_wakeup_repeat_time_t time) -{ - ptr->TV |= LIN_TV_WUP_REPEAT_TIME_SET(time); -} - -/** - * @brief lin set mode - * - * @param ptr lin base address - * @param master true for master mode, false for slave mode - */ -static inline void lin_set_mode(LIN_Type *ptr, bool master) -{ - if (master) { - ptr->TV |= LIN_TV_MASTER_MODE_MASK; - } else { - ptr->TV &= ~LIN_TV_MASTER_MODE_MASK; - } -} - -/** - * @brief lin get data value in byte - * - * @param ptr lin base address - * @param index byte index - * @return uint8_t byte value - */ -static inline uint8_t lin_get_data_byte(LIN_Type *ptr, uint8_t index) -{ - return ptr->DATABYTE[index]; -} - -/** - * @brief lin write data value in byte - * - * @param ptr lin base address - * @param index byte index - * @param data byte value - */ -static inline void lin_write_data_byte(LIN_Type *ptr, uint8_t index, uint8_t data) -{ - ptr->DATABYTE[index] = data; -} - -/** - * @brief lin active status - * - * @param ptr lin base address - * @return bool true for active, false for inactive - */ -static inline bool lin_is_active(LIN_Type *ptr) -{ - return ((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK) ? true : false; -} - -/** - * @brief lin complete status - * - * @param ptr lin base address - * @return bool true for complete, false for incomplete - */ -static inline bool lin_is_complete(LIN_Type *ptr) -{ - return ((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK) ? true : false; -} - -/** - * @brief lin get ID - * - * @param ptr lin base address - * @return uint8_t ID value - */ -static inline uint8_t lin_get_id(LIN_Type *ptr) -{ - return ptr->ID; -} - -/** - * @brief lin configure timing on master mode - * - * @param ptr lin base address - * @param timing lin_timing_t - * @return hpm_stat_t - */ -hpm_stat_t lin_master_configure_timing(LIN_Type *ptr, lin_timing_t *timing); - -/** - * @brief lin config timing on slave mode - * - * @param ptr lin base address - * @param src_freq_in_hz source frequency - * @return hpm_stat_t - */ -hpm_stat_t lin_slave_configure_timing(LIN_Type *ptr, uint32_t src_freq_in_hz); - -/** - * @brief lin transfer on master mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - */ -void lin_master_transfer(LIN_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin transfer on slave mode - * - * @note call this function after lin generate data request interrupt - * - * @param ptr lin base address - * @param config lin_trans_config_t - */ -void lin_slave_transfer(LIN_Type *ptr, lin_trans_config_t *config); - -/** - * @brief get data length - * - * @note data length is determined by DATA_LEN register and ID - * - * @param ptr lin base address - * @return uint8_t data length - */ -uint8_t lin_get_data_length(LIN_Type *ptr); - -/** - * @brief lin send data on master mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_master_sent(LIN_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin receive data on master mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_master_receive(LIN_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin send data on slave mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_slave_sent(LIN_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin receive data on slave mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_slave_receive(LIN_Type *ptr, lin_trans_config_t *config); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_LIN_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h deleted file mode 100644 index 57ce9e6371d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_linv2_drv.h +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_LINV2_DRV_H -#define HPM_LINV2_DRV_H - -#include -#include "hpm_common.h" -#include "hpm_linv2_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief LINV2 driver APIs - * @defgroup linv2_interface LINV2 driver APIs - * @ingroup linv2_interfaces - * @{ - */ - -/** bit4 and bit5 encode data length in ID */ -#define LIN_ID_DATA_LEN_SHIFT 4U -#define LIN_ID_DATA_LEN_MASK 0x30U -#define LIN_ID_DATA_LEN_GET(x) (((uint8_t)(x) & LIN_ID_DATA_LEN_MASK) >> LIN_ID_DATA_LEN_SHIFT) - -/** - * @brief data length in ID bit4 and bit5 - */ -typedef enum { - id_data_length_2bytes, - id_data_length_2bytes_2, /**< both 0 and 1 represent 2 bytes */ - id_data_length_4bytes, - id_data_length_8bytes -} lin_id_data_length_t; - -/** - * @brief bus inactivity tome to go to sleep - */ -typedef enum { - bus_inactivity_time_4s, - bus_inactivity_time_6s, - bus_inactivity_time_8s, - bus_inactivity_time_10s -} lin_bus_inactivity_time_t; - -/** - * @brief wakeup repeat time - */ -typedef enum { - wakeup_repeat_time_180ms, - wakeup_repeat_time_200ms, - wakeup_repeat_time_220ms, - wakeup_repeat_time_240ms -} lin_wakeup_repeat_time_t; - -typedef struct { - uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ - uint32_t baudrate; /**< Baudrate */ -} lin_timing_t; - -/** - * @brief LIN config - */ -typedef struct { - uint8_t id; /**< ID */ - uint8_t *data_buff; /**< data buff */ - bool data_length_from_id; /**< data length should be decoded from the identifier or not, dma mode not use this config */ - uint8_t data_length; /**< used when data_length_from_id is false or dma mode */ - bool enhanced_checksum; /**< true for enhanced checksum; false for classic checksum */ - bool transmit; /**< true for transmit operation; false for receive operation */ - /* bool start; */ /**< true for start operation; false for only configuration */ -} lin_trans_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief lin get control and status register value - * - * @param [in] ptr lin base address - * @return uint32_t control and status register value - */ -static inline uint32_t lin_get_control_and_status(LINV2_Type *ptr) -{ - return ptr->CONTROL_STATUS; -} - -/** - * @brief lin reset interrupt - * - * @param ptr lin base address - */ -static inline void lin_reset_interrupt(LINV2_Type *ptr) -{ - ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_RESET_INT_MASK; -} - -/** - * @brief lin reset error - * - * @param ptr lin base address - */ -static inline void lin_reset_error(LINV2_Type *ptr) -{ - ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_RESET_ERROR_MASK; -} - -/** - * @brief lin wakeup - * - * @param ptr lin base address - */ -static inline void lin_wakeup(LINV2_Type *ptr) -{ - ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK; -} - -/** - * @brief lin sleep - * - * @param ptr lin base address - */ -static inline void lin_sleep(LINV2_Type *ptr) -{ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_SLEEP_MASK; -} - -/** - * @brief lin slave stop - * - * @param ptr lin base address - */ -static inline void lin_slave_stop(LINV2_Type *ptr) -{ - ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_STOP_MASK; -} - -/** - * @brief lin slave ack - * - * @param ptr lin base address - */ -static inline void lin_slave_ack(LINV2_Type *ptr) -{ - ptr->CONTROL_STATUS = ((ptr->CONTROL_STATUS) & ~LINV2_CONTROL_STATUS_SLEEP_MASK) | LINV2_CONTROL_STATUS_DATA_ACK_MASK; -} - -/** - * @brief lin slave set bus inactivity time - * - * @param ptr lin base address - * @param time lin_bus_inactivity_time_t - */ -static inline void lin_slave_set_bus_inactivity_time(LINV2_Type *ptr, lin_bus_inactivity_time_t time) -{ - ptr->TIMING_CONTROL = (ptr->TIMING_CONTROL & (~LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK)) - | LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(time); -} - -/** - * @brief lin slave set wakeup repeat time - * - * @param ptr lin base address - * @param time lin_wakeup_repeat_time_t - */ -static inline void lin_slave_set_wakeup_repeat_time(LINV2_Type *ptr, lin_wakeup_repeat_time_t time) -{ - ptr->TIMING_CONTROL = (ptr->TIMING_CONTROL & (~LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK)) - | LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(time); -} - -/** - * @brief lin set mode - * - * @param ptr lin base address - * @param master true for master mode, false for slave mode - */ -static inline void lin_set_mode(LINV2_Type *ptr, bool master) -{ - if (master) { - ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_MASTER_MODE_MASK; - } else { - ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_MASTER_MODE_MASK; - } -} - -/** - * @brief lin set checksum mode - * - * @param ptr lin base address - * @param enhance_checksum true for enhance checksum mode, false for normal checksum mode - */ -static inline void lin_set_checksum_mode(LINV2_Type *ptr, bool enhance_checksum) -{ - if (enhance_checksum) { - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_MASK; - } else { - ptr->DATA_LEN_ID &= ~LINV2_DATA_LEN_ID_ENH_CHECK_MASK; - } -} - -/** - * @brief lin get data value in byte - * - * @param ptr lin base address - * @param index byte index - * @return uint8_t byte value - */ -static inline uint8_t lin_get_data_byte(LINV2_Type *ptr, uint8_t index) -{ - return ptr->DATA_BYTE[index]; -} - -/** - * @brief lin write data value in byte - * - * @param ptr lin base address - * @param index byte index - * @param data byte value - */ -static inline void lin_write_data_byte(LINV2_Type *ptr, uint8_t index, uint8_t data) -{ - ptr->DATA_BYTE[index] = data; -} - -/** - * @brief lin get ID - * - * @param ptr lin base address - * @return uint8_t ID value - */ -static inline uint8_t lin_get_id(LINV2_Type *ptr) -{ - return (uint8_t)LINV2_DATA_LEN_ID_ID_GET(ptr->DATA_LEN_ID); -} - -/** - * @brief lin get checksum value - * - * @param ptr lin base address - * @return uint8_t checksum value - */ -static inline uint8_t lin_get_checksum(LINV2_Type *ptr) -{ - return (uint8_t)LINV2_DATA_LEN_ID_CHECKSUM_GET(ptr->DATA_LEN_ID); -} - -/** - * @brief lin active status - * - * @param ptr lin base address - * @return bool true for active, false for inactive - */ -static inline uint8_t lin_is_active(LINV2_Type *ptr) -{ - return ((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) == LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) ? true : false; -} - -/** - * @brief lin complete status - * - * @param ptr lin base address - * @return bool true for complete, false for incomplete - */ -static inline uint8_t lin_is_complete(LINV2_Type *ptr) -{ - return ((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_COMPLETE_MASK) == LINV2_CONTROL_STATUS_COMPLETE_MASK) ? true : false; -} - -/** - * @brief lin configure timing on master mode - * - * @param ptr lin base address - * @param timing lin_timing_t - * @return hpm_stat_t - */ -hpm_stat_t lin_master_configure_timing(LINV2_Type *ptr, lin_timing_t *timing); - -/** - * @brief lin config timing on slave mode - * - * @param ptr lin base address - * @param src_freq_in_hz source frequency - * @return hpm_stat_t - */ -hpm_stat_t lin_slave_configure_timing(LINV2_Type *ptr, uint32_t src_freq_in_hz); - -/** - * @brief lin transfer on master mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - */ -void lin_master_transfer(LINV2_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin transfer on slave mode - * - * @note call this function after lin generate data request interrupt - * - * @param ptr lin base address - * @param config lin_trans_config_t - */ -void lin_slave_transfer(LINV2_Type *ptr, lin_trans_config_t *config); - -/** - * @brief get data length - * - * @note data length is determined by DATA_LEN register and ID - * - * @param ptr lin base address - * @return uint8_t data length - */ -uint8_t lin_get_data_length(LINV2_Type *ptr); - -/** - * @brief lin send data on master mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_master_sent(LINV2_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin receive data on master mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_master_receive(LINV2_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin send data on slave mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_slave_sent(LINV2_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin receive data on slave mode - * - * @param ptr lin base address - * @param config lin_trans_config_t - * @return status_timeout - * @return status_success - */ -hpm_stat_t lin_slave_receive(LINV2_Type *ptr, lin_trans_config_t *config); - -/** - * @brief lin slave dma transfer - * - * @param ptr lin base address - * @param config lin_trans_config_t - */ -void lin_slave_dma_transfer(LINV2_Type *ptr, lin_trans_config_t *config); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_LINV2_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lobs_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lobs_drv.h deleted file mode 100644 index e683c4e2aa5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lobs_drv.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_LOBS_DRV_H -#define HPM_LOBS_DRV_H - -#include "hpm_common.h" -#include "hpm_soc_ip_feature.h" -#include "hpm_lobs_regs.h" - -/** - * @brief LOBS driver APIs - * @defgroup lobs_interface LOBS driver APIs - * @ingroup lobs_interfaces - * @{ - */ - -#define LOBS_UNLOCK_KEY 0xc5acce55u - -#define LOBS_PIN_DO(x) (x * 3) -#define LOBS_PIN_OE(x) (x * 3 + 1) -#define LOBS_PIN_DI(x) (x * 3 + 2) - -/** - * @brief group mode selection - * - */ -typedef enum { - lobs_one_group_128_bits = 0, - lobs_two_group_8_bits -} lobs_group_mode_t; /**< lobs_group_mode_t */ - -/** - * @brief sample rate selection - * - */ -typedef enum { - lobs_sample_1_per_5 = 4, - lobs_sample_1_per_6 = 5, - lobs_sample_1_per_7 = 6, -} lobs_sample_rate_t; /**< lobs_sample_rate_t */ - -/** - * @brief burst selection - * - */ -typedef enum { - lobs_burst_4 = 3, - lobs_burst_8 = 5, - lobs_burst_16 = 7, -} lobs_burst_t; /**< lobs_burst_t */ - -/** - * @brief two group selection - * - */ -typedef enum { - lobs_two_group_1 = 0, - lobs_two_group_2, -} lobs_two_group_sel_t; /**< lobs_two_group_sel_t */ - -/** - * @brief state selection - * - */ -typedef enum { - lobs_state_0 = 0, - lobs_state_1, - lobs_state_2, - lobs_state_3, - lobs_state_4, -} lobs_state_sel_t; /**< lobs_state_sel_t */ - -/** - * @brief compare mode - * - */ -typedef enum { - lobs_sig_cmp_mode = 0, - lobs_cnt_cmp_mode, -} lobs_cmp_mode_t; /**< lobs_cmp_mode_t */ - -/** - * @brief compare condition - * - */ -typedef enum { - lobs_cnt_matched = 0, - lobs_sig_equal_golden, - lobs_sig_greater_golden, - lobs_sig_greater_equal_golden, - lobs_sig_not_equal_golden, - lobs_sig_less_golden, - lobs_sig_less_equal_golden, -} lobs_state_chg_condition_t; /**< lobs_state_chg_condition_t */ - -/** - * @brief next state - * - */ -typedef enum { - lobs_next_state_finish = 0x00, - lobs_next_state_0 = 0x01, - lobs_next_state_1 = 0x02, - lobs_next_state_2 = 0x04, - lobs_next_state_3 = 0x08, - lobs_next_state_4 = 0x10, -} lobs_next_state_t; /**< lobs_next_state_t */ - -/** - * @brief ctrl config structure - * - */ -typedef struct { - lobs_group_mode_t group_mode; - lobs_sample_rate_t sample_rate; - uint32_t start_addr; - uint32_t end_addr; -} lobs_ctrl_config_t; /**< lobs_ctrl_config_t */ - -/** - * @brief two group mode config structure - * - */ -typedef struct { - bool group_enable; - uint8_t sig_group_num; - uint8_t sample_sig_bit[4]; - bool sample_sig_en[4]; -} lobs_two_group_mode_config_t; /**< lobs_two_group_mode_config_t */ - -/** - * @brief two group mode config structure - * - */ -typedef struct { - uint8_t sig_group_num; - lobs_cmp_mode_t cmp_mode; - lobs_state_chg_condition_t state_chg_condition; - lobs_next_state_t next_state; - uint32_t cmp_counter; - uint8_t cmp_sig_bit[4]; - bool cmp_sig_en[4]; - bool cmp_golden_value[4]; -} lobs_state_config_t; /**< lobs_state_config_t */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief set lobs unlock - * - * @param[in] lobs LOBS base address - */ -static inline void lobs_unlock(LOBS_Type *lobs) -{ - lobs->LAR = LOBS_UNLOCK_KEY; -} - -/** - * @brief set lobs lock - * - * @param[in] lobs LOBS base address - */ -static inline void lobs_lock(LOBS_Type *lobs) -{ - lobs->LAR = 0; -} - -/** - * @brief set lobs enable or disable - * - * @param[in] lobs LOBS base address - * @param[in] enable true - enable; false - disable. - */ -static inline void lobs_set_enable(LOBS_Type *lobs, bool enable) -{ - lobs->CTRL = (lobs->CTRL & ~LOBS_CTRL_RUN_MASK) | LOBS_CTRL_RUN_SET(enable); -} - -/** - * @brief set lobs pre-trig enable or disable - * - * @param[in] lobs LOBS base address - * @param[in] enable true - enable; false - disable. - */ -static inline void lobs_set_pre_trig_enable(LOBS_Type *lobs, bool enable) -{ - lobs->PTACTION = (lobs->PTACTION & ~LOBS_PTACTION_TRACE_MASK) | LOBS_PTACTION_TRACE_SET(enable); -} - -/** - * @brief set lobs state enable or disable - * - * @param[in] lobs LOBS base address - * @param[in] state one of state, @ref lobs_state_sel_t - * @param[in] enable true - enable; false - disable. - */ -static inline void lobs_set_state_enable(LOBS_Type *lobs, lobs_state_sel_t state, bool enable) -{ - lobs->STATE[state].ACTION = (lobs->STATE[state].ACTION & ~LOBS_STATE_ACTION_TRACE_MASK) | LOBS_STATE_ACTION_TRACE_SET(enable); -} - -/** - * @brief get lobs final address - * - * @param[in] lobs LOBS base address - * - * @return uint32_t trace final address - */ -static inline uint32_t lobs_get_final_address(LOBS_Type *lobs) -{ - return lobs->FINALADDR; -} - -/** - * @brief check lobs trace finish - * - * @param[in] lobs LOBS base address - * - * @return bool true - trace finish; false - trace not finish - */ -static inline bool lobs_is_trace_finish(LOBS_Type *lobs) -{ - return (LOBS_CTSR_FINALSTATE_GET(lobs->CTSR) != 0) ? true : false; -} - -/** - * @brief clear lobs fifo overflow flag - * - * @param[in] lobs LOBS base address - * - */ -static inline void lobs_clear_fifo_overflow_flag(LOBS_Type *lobs) -{ - lobs->STREAMCTRL |= LOBS_STREAMCTRL_FULL_CLEAR_MASK; -} - -/** - * @brief lobs deinit - * - * @param[in] lobs LOBS base address - */ -void lobs_deinit(LOBS_Type *lobs); - -/** - * @brief lobs control config - * - * @param[in] lobs LOBS base address - * @param[in] config control config structure pointer - */ -void lobs_ctrl_config(LOBS_Type *lobs, lobs_ctrl_config_t *config); - -/** - * @brief lobs two group mode config - * - * @param[in] lobs LOBS base address - * @param[in] group one of the two group, @ref lobs_two_group_sel_t - * @param[in] config two group mode config structure pointer - */ -void lobs_two_group_mode_config(LOBS_Type *lobs, lobs_two_group_sel_t group, lobs_two_group_mode_config_t *config); - -/** - * @brief lobs state config - * - * @param[in] lobs LOBS base address - * @param[in] state one of state, @ref lobs_state_sel_t - * @param[in] config state config structure pointer - */ -void lobs_state_config(LOBS_Type *lobs, lobs_state_sel_t state, lobs_state_config_t *config); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_LOBS_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lvb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lvb_drv.h deleted file mode 100644 index efc5f7b33e9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lvb_drv.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_LVB_DRV_H -#define HPM_LVB_DRV_H - -/** - * @brief LVB APIs - * @defgroup lvb_interface LVB driver APIs - * @ingroup lvb_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_lvb_regs.h" - -/** - * @brief LVB DI vsync polarity - */ -typedef enum lvb_di_vsync_polarity { - lvb_di_vsync_polarity_active_high = 0, - lvb_di_vsync_polarity_active_low -} lvb_di_vsync_polarity_t; - -/** - * @brief Shift the LVDS TX PHY clock in relation to the data - */ -typedef enum lvb_txclk_shift { - lvb_txclk_shift_1100011 = 0, - lvb_txclk_shift_1110001, - lvb_txclk_shift_1111000, - lvb_txclk_shift_1000111, - lvb_txclk_shift_0001111, - lvb_txclk_shift_0011110, - lvb_txclk_shift_0111100, -} lvb_txclk_shift_t; - -/** - * @brief LVB config - */ -typedef struct lvb_config { - bool split_ch_is_reverse; /*!< Just for split mode, reverse two channel data */ - bool split_ch_data_is_unaligned; /*!< Just for split mode, two channel pixel data are aligned */ - bool split_hswhbp_width_is_even; /*!< Just for split mode, the sum of HSW and HBP width is even */ - bool split_mode_en; /*!< Note: when using split mode, ch0/1 should be enabled, and should select same DI */ - lvb_di_vsync_polarity_t di1_vsync_polarity; /*!< lvb di1 vsync polarity */ - lvb_di_vsync_polarity_t di0_vsync_polarity; /*!< lvb di0 vsync polarity */ - lvb_txclk_shift_t txclk_shift; /*!< Shift the LVDS TX PHY clock in relation to the data */ -} lvb_config_t; - -/** - * @brief LVB channel pixel data mapping - */ -typedef enum lvb_ch_mapping { - lvb_ch_mapping_vesa = 0, - lvb_ch_mapping_jeida, -} lvb_ch_mapping_t; - -/** - * @brief LVB channel pixel data source - */ -typedef enum lvb_ch_data_source { - lvb_ch_data_source_di0 = 0, - lvb_ch_data_source_di1, -} lv_ch_data_source_t; - -/** - * @brief LVB channel number - */ -typedef enum lvb_ch_num { - lvb_ch_num_0 = 0, - lvb_ch_num_1 = 1 -} lvb_ch_num_t; - -/** - * @brief LVB channel config - */ -typedef struct lvb_ch_config { - lvb_ch_mapping_t map; - lv_ch_data_source_t data_src; -} lvb_ch_config_t; - -typedef enum lvb_lvds_lane_phase_sel { - lvb_lvds_lane_phase_sel_0_ui = 0, - lvb_lvds_lane_phase_sel_1_16_ui, - lvb_lvds_lane_phase_sel_2_16_ui, - lvb_lvds_lane_phase_sel_3_16_ui, - lvb_lvds_lane_phase_sel_4_16_ui, - lvb_lvds_lane_phase_sel_5_16_ui, - lvb_lvds_lane_phase_sel_6_16_ui, - lvb_lvds_lane_phase_sel_7_16_ui, - lvb_lvds_lane_phase_sel_8_16_ui, - lvb_lvds_lane_phase_sel_9_16_ui, - lvb_lvds_lane_phase_sel_10_16_ui, - lvb_lvds_lane_phase_sel_11_16_ui, - lvb_lvds_lane_phase_sel_12_16_ui, - lvb_lvds_lane_phase_sel_13_16_ui, - lvb_lvds_lane_phase_sel_14_16_ui, - lvb_lvds_lane_phase_sel_15_16_ui, -} lvb_lvds_lane_phase_sel_t; - -typedef enum lvb_lvds_lane_amp { - lvb_lvds_lane_amp_50_mv = 0, - lvb_lvds_lane_amp_100_mv, - lvb_lvds_lane_amp_150_mv, - lvb_lvds_lane_amp_200_mv, - lvb_lvds_lane_amp_250_mv, - lvb_lvds_lane_amp_300_mv, - lvb_lvds_lane_amp_350_mv, - lvb_lvds_lane_amp_400_mv, - lvb_lvds_lane_amp_450_mv, - lvb_lvds_lane_amp_500_mv, - lvb_lvds_lane_amp_550_mv, - lvb_lvds_lane_amp_600_mv -} lvb_lvds_lane_amp_t; - -typedef enum lvb_lvds_lane_vcom { - lvb_lvds_lane_vcom_0_7_v = 0, - lvb_lvds_lane_vcom_0_8_v, - lvb_lvds_lane_vcom_0_9_v, - lvb_lvds_lane_vcom_1_0_v, - lvb_lvds_lane_vcom_1_1_v, - lvb_lvds_lane_vcom_1_2_v, - lvb_lvds_lane_vcom_1_3_v, - lvb_lvds_lane_vcom_1_4_v, - lvb_lvds_lane_vcom_1_5_v, -} lvb_lvds_lane_vcom_t; - -typedef struct lvb_lvds_phy_lane_config { - bool rterm_enable; - bool tx_idle; - lvb_lvds_lane_phase_sel_t phase_sel; - lvb_lvds_lane_amp_t amp; - lvb_lvds_lane_vcom_t vcom; - bool fvco_div4; -} lvb_lvds_phy_lane_config_t; - -typedef enum lvb_lvds_lane_idx { - lvb_lvds_lane_idx_lvds0_tx0 = LVB_TX_PHY_LVDS0_TX0, - lvb_lvds_lane_idx_lvds0_tx1 = LVB_TX_PHY_LVDS0_TX1, - lvb_lvds_lane_idx_lvds0_tx2 = LVB_TX_PHY_LVDS0_TX2, - lvb_lvds_lane_idx_lvds0_tx3 = LVB_TX_PHY_LVDS0_TX3, - lvb_lvds_lane_idx_lvds0_txck = LVB_TX_PHY_LVDS0_TXCK, - lvb_lvds_lane_idx_lvds1_tx0 = LVB_TX_PHY_LVDS1_TX0, - lvb_lvds_lane_idx_lvds1_tx1 = LVB_TX_PHY_LVDS1_TX1, - lvb_lvds_lane_idx_lvds1_tx2 = LVB_TX_PHY_LVDS1_TX2, - lvb_lvds_lane_idx_lvds1_tx3 = LVB_TX_PHY_LVDS1_TX3, - lvb_lvds_lane_idx_lvds1_txck = LVB_TX_PHY_LVDS1_TXCK, -} lvb_lvds_lane_idx_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief get LVB of default config - * - * @param[out] cfg config of LVB - */ -void lvb_get_default_config(lvb_config_t *cfg); - -/** - * @brief LVB init - * - * @param[in] ptr LVB base address - * @param[in] cfg config of LVB - */ -void lvb_init(LVB_Type *ptr, lvb_config_t *cfg); - -/** - * @brief get LVB channel of default config - * - * @param[out] ch_cfg config of LVB - */ -void lvb_get_ch_default_config(lvb_ch_config_t *ch_cfg); - -/** - * @brief LVB channel config - * - * @param[in] ptr LVB base address - * @param[in] ch_num LVB channel number - * @param[in] ch_cfg config of LVB channel - */ -void lvb_ch_config(LVB_Type *ptr, lvb_ch_num_t ch_num, lvb_ch_config_t *ch_cfg); - -/** - * @brief LVB channel enable - * - * @param[in] ptr LVB base address - * @param[in] ch_num LVB channel number - */ -void lvb_ch_enable(LVB_Type *ptr, lvb_ch_num_t ch_num); - -/** - * @brief LVB channel disable - * - * @param[in] ptr LVB base address - * @param[in] ch_num LVB channel number - */ -void lvb_ch_disable(LVB_Type *ptr, lvb_ch_num_t ch_num); - -/** - * @brief check LVB phy0 is lock - * - * @param[in] ptr LVB base address - */ -static inline bool lvb_lvds_phy0_pll_is_lock(LVB_Type *ptr) -{ - return !!LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT); -} - -/** - * @brief check LVB phy1 is lock - * - * @param[in] ptr LVB base address - */ -static inline bool lvb_lvds_phy1_pll_is_lock(LVB_Type *ptr) -{ - return !!LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT); -} - -/** - * @brief check LVB phy0 and phy1 is lock - * - * @param[in] ptr LVB base address - */ -static inline bool lvb_lvds_phy_split_pll_is_lock(LVB_Type *ptr) -{ - return !!LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT) && - !!LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(ptr->PHY_STAT); -} - -/** - * @brief lvb lvds lane get default config - * - * @param[out] cfg lvds lane config @ref lvb_lvds_phy_lane_config_t - */ -void lvb_lvds_phy_lane_get_default_config(lvb_lvds_phy_lane_config_t *cfg); - -/** - * @brief lvb lvds lane init and config - * - * @param[in] ptr LVB base address - * @param[in] tx_index lvds phy lane index @ref lvb_lvds_lane_idx_t - * @param[in] cfg lvds lane config @ref lvb_lvds_phy_lane_config_t - */ -void lvb_lvds_phy_lane_init(LVB_Type *ptr, lvb_lvds_lane_idx_t tx_index, lvb_lvds_phy_lane_config_t *cfg); - -/** - * @brief power on LVB phy0 - * - * @param[in] ptr LVB base address - */ -void lvb_lvds_phy0_poweron(LVB_Type *ptr); - -/** - * @brief power on LVB phy1 - * - * @param[in] ptr LVB base address - */ -void lvb_lvds_phy1_poweron(LVB_Type *ptr); - -/** - * @brief power down LVB phy0 - * - * @param[in] ptr LVB base address - */ -void lvb_lvds_phy0_powerdown(LVB_Type *ptr); - -/** - * @brief power down LVB phy0 - * - * @param[in] ptr LVB base address - */ -void lvb_lvds_phy1_powerdown(LVB_Type *ptr); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_LVB_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h deleted file mode 100644 index 362dc61c905..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_DRV_H -#define HPM_MBX_DRV_H -#include "hpm_common.h" -#include "hpm_mbx_regs.h" - -/** - * @brief MBX driver APIs - * @defgroup mbx_interface MBX driver APIs - * @ingroup io_interfaces - * @{ - */ - -/* - * @brief Bus access responses - */ -typedef enum { - no_bus_error_no_wait = 0, - generate_bus_error = 1, -} mbx_bus_access_resp_t; - -/* - * @brief MBX specific status - */ -enum { - status_mbx_not_available = MAKE_STATUS(status_group_mbx, 2), -}; - -#define MBX_CR_ALL_INTERRUPTS_MASK (MBX_CR_TFMAIE_MASK | MBX_CR_RFMAIE_MASK \ - | MBX_CR_RFMFIE_MASK | MBX_CR_TWMEIE_MASK) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Set bus access response - * - * @param[in] ptr MBX base address - * @param[in] resp response value type - */ -static inline void mbx_set_bus_access_response(MBX_Type *ptr, mbx_bus_access_resp_t resp) -{ - ptr->CR = (ptr->CR & ~(MBX_CR_BARCTL_MASK)) | MBX_CR_BARCTL_SET(resp); -} - -/** - * @brief Enable interrupt with mask - * - * @param[in] ptr MBX base address - * @param[in] mask Mask of interrupts to be enabled - */ -static inline void mbx_enable_intr(MBX_Type *ptr, uint32_t mask) -{ - ptr->CR |= mask; -} - -/** - * @brief Disable interrupt with mask - * - * @param[in] ptr MBX base address - * @param[in] mask Mask of interrupts to be disabled - */ -static inline void mbx_disable_intr(MBX_Type *ptr, uint32_t mask) -{ - ptr->CR &= ~mask; -} - -/** - * @brief Empty fifo - * - * @param[in] ptr MBX base address - */ -static inline void mbx_empty_txfifo(MBX_Type *ptr) -{ - ptr->CR |= MBX_CR_TXRESET_MASK; -} - -/** - * @brief Initialization - * - * @param[in] ptr MBX base address - */ -static inline void mbx_init(MBX_Type *ptr) -{ - mbx_empty_txfifo(ptr); - mbx_disable_intr(ptr, MBX_CR_ALL_INTERRUPTS_MASK); -} - -/** - * @brief Send message - * - * @param[in] ptr MBX base address - * @param[in] msg Message data in 32 bits - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t mbx_send_message(MBX_Type *ptr, uint32_t msg) -{ - if (ptr->SR & MBX_SR_TWME_MASK) { - ptr->TXREG = msg; - return status_success; - } - return status_mbx_not_available; -} - - -/** - * @brief Retrieve message - * - * @param[in] ptr MBX base address - * @param[out] msg Pointer to buffer to save message data - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t mbx_retrieve_message(MBX_Type *ptr, uint32_t *msg) -{ - if (ptr->SR & MBX_SR_RWMV_MASK) { - *msg = ptr->RXREG; - return status_success; - } - return status_mbx_not_available; -} - -/** - * @brief Send message to fifo - * - * @param[in] ptr MBX base address - * @param[in] msg Pointer to message array to be sent - * @param[in] count Number of 32-bit data to be sent - * - * @return status_success if everything is okay - * @return status_not_available if fifo is full - */ -static inline hpm_stat_t mbx_send_fifo(MBX_Type *ptr, uint32_t *msg, uint32_t count) -{ - uint32_t i; - hpm_stat_t status = status_success; - for (i = 0; i < 4; i++) { - if (ptr->SR & MBX_SR_TFMA_MASK) { - ptr->TXWRD[0] = MBX_TXWRD_TXFIFO_SET(*(msg + i)); - count--; - if (!count) { - break; - } - } else { - status = status_mbx_not_available; - break; - } - } - return status; -} - - - -/** - * @brief Retrieve data from fifo - * - * @param[in] ptr MBX base address - * @param[out] msg Pointer of buffer to receive data - * @param[in] count Number of 32-bit data to be retrieved - * - * @return status_success if everything is okay - * @return status_mbx_not_available if fifo is empty - */ -static inline hpm_stat_t mbx_retrieve_fifo(MBX_Type *ptr, uint32_t *msg, uint32_t count) -{ - uint32_t i; - hpm_stat_t status = status_success; - for (i = 0; i < 4; i++) { - if (ptr->SR & MBX_SR_RFMA_MASK) { - *(msg + i) = (ptr->RXWRD[0] & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT; - count--; - if (!count) { - break; - } - } else { - status = status_mbx_not_available; - break; - } - } - return status; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_MBX_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h deleted file mode 100644 index 59f3dd556db..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h +++ /dev/null @@ -1,1815 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_MCAN_DRV_H -#define HPM_MCAN_DRV_H - -#include "hpm_common.h" -#include "hpm_mcan_regs.h" -#include "hpm_mcan_soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** -* @brief MCAN driver APIs -* @defgroup mcan_interface MCAN driver APIs -* @ingroup mcan_interfaces -* @{ -* -*/ - - -enum { - status_mcan_filter_index_out_of_range = MAKE_STATUS(status_group_mcan, 0), - status_mcan_rxfifo_empty = MAKE_STATUS(status_group_mcan, 1), - status_mcan_rxfifo_full = MAKE_STATUS(status_group_mcan, 2), - status_mcan_txbuf_full = MAKE_STATUS(status_group_mcan, 3), - status_mcan_txfifo_full = MAKE_STATUS(status_group_mcan, 4), - status_mcan_rxfifo0_busy = MAKE_STATUS(status_group_mcan, 5), - status_mcan_rxfifo1_busy = MAKE_STATUS(status_group_mcan, 6), - status_mcan_txbuf_index_out_of_range = MAKE_STATUS(status_group_mcan, 7), - status_mcan_rxbuf_index_out_of_range = MAKE_STATUS(status_group_mcan, 8), - status_mcan_rxbuf_empty = MAKE_STATUS(status_group_mcan, 9), - status_mcan_tx_evt_fifo_empty = MAKE_STATUS(status_group_mcan, 10), - status_mcan_timestamp_not_exist = MAKE_STATUS(status_group_mcan, 11), - status_mcan_ram_out_of_range = MAKE_STATUS(status_group_mcan, 12), - status_mcan_timeout = MAKE_STATUS(status_group_mcan, 13), - status_mcan_invalid_bit_timing = MAKE_STATUS(status_group_mcan, 14), -}; - -/** - * @brief CAN Interrupt Mask - */ -#define MCAN_INT_ACCESS_TO_RESERVED_ADDR MCAN_IR_ARA_MASK /*!< Access to Reserved Address */ -#define MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE MCAN_IR_PED_MASK /*!< Protocol Error Happened at Data Phase */ -#define MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE MCAN_IR_PEA_MASK /*!< Protocol Error Happened at Arbitration Phase */ -#define MCAN_INT_WATCHDOG_INT MCAN_IR_WDI_MASK /*!< Watchdog interrupt */ - -#define MCAN_INT_BUS_OFF_STATUS MCAN_IR_BO_MASK /*!< Bus-off State Change */ -#define MCAN_INT_WARNING_STATUS MCAN_IR_EW_MASK /*!< Error Warning State Change */ -#define MCAN_INT_ERROR_PASSIVE MCAN_IR_EP_MASK /*!< Error Passive State Change */ -#define MCAN_INT_ERROR_LOGGING_OVERFLOW MCAN_IR_ELO_MASK /*!< Error Logging Overflow */ -#define MCAN_INT_BIT_ERROR_UNCORRECTED MCAN_IR_BEU_MASK /*!< Bit Error was not corrected */ -#define MCAN_INT_BIT_ERROR_CORRECTED MCAN_IR_BEC_MASK /*!< Bit Error was corrected */ - -#define MCAN_INT_MSG_STORE_TO_RXBUF MCAN_IR_DRX_MASK /*!< Message was stored to RX Buffer */ -#define MCAN_INT_TIMEOUT_OCCURRED MCAN_IR_TOO_MASK /*!< Timeout Interrupt */ -#define MCAN_INT_MSG_RAM_ACCESS_FAILURE MCAN_IR_MRAF_MASK /*!< Message RAM Access Failure */ -#define MCAN_INT_TIMESTAMP_WRAPAROUND MCAN_IR_TSW_MASK /*!< Timestamp Counter Wrap Around */ - -#define MCAN_INT_TX_EVT_FIFO_EVT_LOST MCAN_IR_TEFL_MASK /*!< TX Event FIFO Element Lost */ -#define MCAN_INT_TX_EVT_FIFO_FULL MCAN_IR_TEFF_MASK /*!< TX Event FIFO Full */ -#define MCAN_INT_TX_EVT_FIFO_WMK_REACHED MCAN_IR_TEFW_MASK /*!< TX Event FIFO Watermark Reached */ -#define MCAN_INT_TX_EVT_FIFO_NEW_ENTRY MCAN_IR_TEFN_MASK /*!< TX Event FIFO New Entry */ - -#define MCAN_INT_TXFIFO_EMPTY MCAN_IR_TFE_MASK /*!< TX FIFO Empty */ -#define MCAN_INT_TX_CANCEL_FINISHED MCAN_IR_TCF_MASK /*!< Transmission Cancellation Finished */ -#define MCAN_INT_TX_COMPLETED MCAN_IR_TC_MASK /*!< Transmission Completed */ -#define MCAN_INT_HIGH_PRIORITY_MSG MCAN_IR_HPM_MASK /*!< High Priority Message */ - -#define MCAN_INT_RXFIFO1_MSG_LOST MCAN_IR_RF1L_MASK /*!< RX FIFO0 Message Lost */ -#define MCAN_INT_RXFIFO1_FULL MCAN_IR_RF1F_MASK /*!< RX FIFO1 Full */ -#define MCAN_INT_RXFIFO1_WMK_REACHED MCAN_IR_RF1W_MASK /*!< RX FIFO1 Watermark Reached */ -#define MCAN_INT_RXFIFO1_NEW_MSG MCAN_IR_RF1N_MASK /*!< RX FIFO1 New Message */ - -#define MCAN_INT_RXFIFO0_MSG_LOST MCAN_IR_RF0L_MASK /*!< RX FIFO0 Message Lost */ -#define MCAN_INT_RXFIFO0_FULL MCAN_IR_RF0F_MASK /*!< RX FIFO0 Full */ -#define MCAN_INT_RXFIFO0_WMK_REACHED MCAN_IR_RF0W_MASK /*!< RX FIFO0 Watermark Reached */ -#define MCAN_INT_RXFIFO0_NEW_MSG MCAN_IR_RF0N_MASK /*!< RX FIFO0 New Message */ - -/** - * @brief MCAN Receive Event Flags - */ -#define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFO0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF) - -/** - * @brief MCAN Transmit Event Flags - */ -#define MCAN_EVENT_TRANSMIT (MCAN_INT_TX_COMPLETED) -/** - * @brief MCAN Error Event Flags - */ -#define MCAN_EVENT_ERROR (MCAN_INT_BUS_OFF_STATUS | MCAN_INT_WARNING_STATUS \ - | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED \ - | MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE | MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE) - -/** - * @brief Maximum Transmission Retry Count - */ -#define MCAN_TX_RETRY_COUNT_MAX (10000000UL) -/** - * @brief Maximum Receive Wait Retry Count - */ -#define MCAN_RX_RETRY_COUNT_MAX (80000000UL) - -/** - * @brief MCAN Last Error Code - */ -typedef enum mcan_last_error_code { - mcan_last_error_code_no_error = 0, /*!< No error happened */ - mcan_last_error_code_stuff_error, /*!< Stuff Error */ - mcan_last_error_code_format_error, /*!< Format Error */ - mcan_last_error_code_ack_error, /*!< Acknowledge Error */ - mcan_last_error_code_bit1_error, /*!< Sent logic 1 but monitored value is logic 0 */ - mcan_last_error_code_bit0_error, /*!< Sent logic 0 but monitored value is logic 1 */ - mcan_last_error_code_crc_error, /*!< CRC checksum for received message is wrong */ - mcan_last_error_code_no_change, /*!< Error code was not changed */ -} mcan_last_err_code_t; - -/** - * @brief MCAN Communication State - */ -typedef enum mcan_activity_enum { - mcan_activity_sync = 0, /*!< Node is synchronizing on CAN communication */ - mcan_activity_idle, /*!< Node is neither receiver nor transmitter */ - mcan_activity_receiver, /*!< Node is operating as receiver */ - mcan_activity_transmitter, /*!< Node is operating as transmitter */ -} mcan_activity_state_t; - -/*********************************************************************************************************************** - * @brief Default CAN RAM definitions - **********************************************************************************************************************/ -#define MCAN_RAM_WORD_SIZE (640U) /*!< RAM WORD Size */ -/* CAN Filter Element Size Definitions */ -#define MCAN_FILTER_ELEM_STD_ID_SIZE (4U) /*!< Standard Filter Element Size in Bytes */ -#define MCAN_FILTER_ELEM_EXT_ID_SIZE (8U) /*!< Extended Filter Element SIze in Bytes */ -#define MCAN_STD_FILTER_ELEM_SIZE_MAX (128U) /*!< Maximum Standard Filter Element Count */ -#define MCAN_EXT_FILTER_ELEM_SIZE_MAX (64U) /*!< Maximum Extended Filter Element Count */ -/* MCAN Default Field Size Definitions for CAN2.0 */ -#define MCAN_TXRX_ELEM_SIZE_CAN_MAX (4U * sizeof(uint32_t)) -#define MCAN_FILTER_SIZE_CAN_DEFAULT (32U) -#define MCAN_TXBUF_SIZE_CAN_DEFAULT (32U) -#define MCAN_RXFIFO_SIZE_CAN_DEFAULT (32U) -#define MCAN_RXBUF_SIZE_CAN_DEFAULT (16U) -/* MCAN Default Field Size Definitions for CANFD */ -#define MCAN_TXRX_ELEM_SIZE_CANFD_MAX (18U * sizeof(uint32_t)) -#define MCAN_FILTER_SIZE_CANFD_DEFAULT (16U) -#define MCAN_TXBUF_SIZE_CANFD_DEFAULT (8U) -#define MCAN_RXFIFO_SIZE_CANFD_DEFAULT (8U) -#define MCAN_RXBUF_SIZE_CANFD_DEFAULT (4U) - -#define MCAN_TXEVT_ELEM_SIZE (8U) - -/** - * @brief CAN Bit Timing Parameters - */ -typedef struct mcan_bit_timing_param_struct { - uint16_t prescaler; /*!< Data Bit Rate Prescaler */ - uint16_t num_seg1; /*!< Time segment before sample point (including prop_seg and phase_sge1 */ - uint16_t num_seg2; /*!< Time segment after sample point */ - uint8_t num_sjw; /*!< Data (Re)Synchronization Jump Width */ - bool enable_tdc; /*!< Enable TDC flag, for CANFD data bit timing only */ -} mcan_bit_timing_param_t; - -/** - * @brief CAN Bit Timing Options - */ -typedef enum mcan_bit_timing_option { - mcan_bit_timing_can2_0, /**< CAN 2.0 bit timing option */ - mcan_bit_timing_canfd_nominal, /**< CANFD nominal timing option */ - mcan_bit_timing_canfd_data, /**< CANFD data timing option */ -} mcan_bit_timing_option_t; - -/** - * @brief CAN Message Header Size - */ -#define MCAN_MESSAGE_HEADER_SIZE_IN_BYTES (8U) -#define MCAN_MESSAGE_HEADER_SIZE_IN_WORDS (2U) - -/** - * @brief CAN Transmit Message Frame - * - * @note Users need to pay attention to the CAN Identifier settings - * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used - * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used - */ -typedef struct mcan_tx_message_struct { - union { - struct { - uint32_t ext_id: 29; /*!< Extended CAN Identifier */ - uint32_t rtr: 1; /*!< Remote Transmission Request */ - uint32_t use_ext_id: 1; /*!< Extended Identifier */ - uint32_t error_state_indicator: 1; /*!< Error State Indicator */ - }; - struct { - uint32_t : 18; - uint32_t std_id: 11; /*!< Standard CAN Identifier */ - uint32_t : 3; - }; - }; - struct { - uint32_t : 8; - uint32_t message_marker_h: 8; /*!< Message Marker[15:8] */ - uint32_t dlc: 4; /*!< Data Length Code */ - uint32_t bitrate_switch: 1; /*!< Bit Rate Switch */ - uint32_t canfd_frame: 1; /*!< CANFD frame */ - uint32_t timestamp_capture_enable: 1; /*!< Timestamp Capture Enable for TSU */ - uint32_t event_fifo_control: 1; /*!< Event FIFO control */ - uint32_t message_marker_l: 8; /*!< Message Marker[7:0] */ - }; - union { - uint8_t data_8[64]; /*!< Data buffer as byte array */ - uint32_t data_32[16]; /*!< Data buffer as word array */ - }; -} mcan_tx_frame_t; - -/** - * @brief CAN Receive Message Frame - * - * @note Users need to pay attention to the CAN Identifier settings - * For standard identifier, the use_ext_id should be set to 0 and the std_id should be used - * For extended identifier, the use_ext_id should be set to 1 and the ext_id should be used - */ -typedef struct mcan_rx_message_struct { - union { - struct { - uint32_t ext_id: 29; /*!< Extended CAN Identifier */ - uint32_t rtr: 1; /*!< Remote Frame Flag */ - uint32_t use_ext_id: 1; /*!< Extended Identifier */ - uint32_t error_state_indicator: 1; /*!< Error State Indicator */ - }; - struct { - uint32_t : 18; - uint32_t std_id: 11; /*!< Standard CAN Identifier */ - uint32_t : 3; - }; - }; - struct { - union { - uint16_t rx_timestamp; /*!< Received timestamp */ - struct { - uint16_t rx_timestamp_pointer: 4; /*!< Timestamp Pointer */ - uint16_t rx_timestamp_captured: 1; /*!< Timestamp Captured flag */ - uint16_t : 11; - }; - }; - }; - struct { - uint16_t dlc: 4; /*!< Data Length Code */ - uint16_t bitrate_switch: 1; /*!< Bit rate switch flag */ - uint16_t canfd_frame: 1; /*!< CANFD Frame flag */ - uint16_t : 1; - uint16_t filter_index: 7; /*!< CAN filter index */ - uint16_t accepted_non_matching_frame: 1; /*!< Accept non-matching Frame flag */ - }; - union { - uint8_t data_8[64]; /*!< Data buffer as byte array */ - uint32_t data_32[16]; /*!< Data buffer as word array */ - }; -} mcan_rx_message_t; - -/** - * @brief TX Event Fifo Element Structure - */ -typedef union mcan_tx_event_fifo_elem_struct { - struct { - /* First word */ - union { - struct { - uint32_t ext_id: 29; /*!< CAN Identifier */ - uint32_t rtr: 1; /*!< Remote Transmission Request */ - uint32_t extend_id: 1; /*!< Extended Identifier */ - uint32_t error_state_indicator: 1; /*!< Error State Indicator */ - }; - struct { - uint32_t : 18; - uint32_t std_id: 11; - uint32_t : 3; - }; - }; - - /* first 16-bit of the 2nd word */ - union { - uint16_t tx_timestamp; /*!< Tx Timestamp */ - struct { - uint16_t tx_timestamp_pointer: 4; /*!< TX timestamp pointer */ - uint16_t tx_timestamp_captured: 1; /*!< TX timestamp captured flag */ - uint16_t : 11; - }; - }; - /* high-half 16-bit of the 2nd word */ - struct { - uint16_t dlc: 4; /*!< Data length code */ - uint16_t bitrate_switch: 1; /*!< Bitrate Switch flag */ - uint16_t canfd_frame: 1; /*!< CANFD frame */ - uint16_t event_type: 2; /*!< Event type */ - uint16_t message_marker: 8; /*!< Message Marker */ - }; - }; - uint32_t words[2]; -} mcan_tx_event_fifo_elem_t; - - - -/** - * @brief CAN Identifier Types - */ -#define MCAN_CAN_ID_TYPE_STANDARD (0U) /*!< Standard Identifier */ -#define MCAN_CAN_ID_TYPE_EXTENDED (1U) /*!< Extended Identifier */ - -/** - * @brief MCAN Filter Configuration - */ -typedef union mcan_filter_config_struct { - struct { - uint16_t list_start_addr; /*!< List Start address (CAN Message Buffer Offset) */ - uint16_t list_size; /*!< Element Count */ - }; - uint32_t reg_val; /*!< Register value */ -} mcan_filter_config_t; - -/** - * @brief MCAN RXFIFO Configuration - */ -typedef union mcan_rxfifo_config_struct { - struct { - uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */ - uint32_t fifo_size: 8; /*!< FIFO element count */ - uint32_t watermark: 7; /*!< FIFO watermark */ - uint32_t operation_mode: 1; /*!< Operation mode */ - }; - uint32_t reg_val; /*!< Register value */ -} mcan_rxfifo_config_t; - -/** - * @brief MCAN RXBUF Configuration - */ -typedef struct { - uint32_t start_addr; /*!< Start address (CAN Message Buffer Offset) */ -} mcan_rxbuf_config_t; - -/** - * @brief MCAN Data Field Size Definitions - */ -#define MCAN_DATA_FIELD_SIZE_8BYTES (0U) -#define MCAN_DATA_FIELD_SIZE_12BYTES (1U) -#define MCAN_DATA_FIELD_SIZE_16BYTES (2U) -#define MCAN_DATA_FIELD_SIZE_20BYTES (3U) -#define MCAN_DATA_FIELD_SIZE_24BYTES (4U) -#define MCAN_DATA_FIELD_SIZE_32BYTES (5U) -#define MCAN_DATA_FIELD_SIZE_48BYTES (6U) -#define MCAN_DATA_FIELD_SIZE_64BYTES (7U) - -/** - * @brief MCAN FIFO Operation Mode types - */ -#define MCAN_FIFO_OPERATION_MODE_BLOCKING (0U) -#define MCAN_FIFO_OPERATION_MODE_OVERWRITE (1U) - -/** - * @brief MCAN RXBUF or RXFIFO Element Configuration - */ -typedef union mcan_rx_fifo_or_buf_elem_config_struct { - struct { - uint32_t fifo0_data_field_size: 4; /*!< FIFO0 data field size option */ - uint32_t fifo1_data_field_size: 4; /*!< FIFO1 data field size option */ - uint32_t buf_data_field_size: 4; /*!< Buffer Data field size option */ - uint32_t : 20; - }; - uint32_t reg_val; /*!< Register value */ -} mcan_rx_fifo_or_buf_elem_config_t; - -/** - * @brief MCAN TXBUF operation mode types - */ -#define MCAN_TXBUF_OPERATION_MODE_FIFO (0U) -#define MCAN_TXBUF_OPERATION_MODE_QUEUE (1U) - - -typedef union mcan_txbuf_config_struct { - struct { - uint32_t start_addr: 16; /*!< Start address (CAN Message Buffer Offset) */ - uint32_t dedicated_tx_buf_size: 6; /*!< Dedicated TX buffer size */ - uint32_t : 2; - uint32_t fifo_queue_size: 6; /*!< FIFO or Queue Size */ - uint32_t tx_fifo_queue_mode: 1; /*!< FIFO or Queue mode selection */ - uint32_t : 1; - }; - uint32_t reg_val; /*!< register value */ -} mcan_txbuf_config_t; - -typedef struct mcan_txbuf_elem_config_struct { - uint32_t data_field_size; /*!< Data Field size option */ -} mcan_txbuf_elem_config_t; - -/** - * @brief MCAN TX Event FIFO Structure - */ -typedef union { - struct { - uint16_t start_addr; /*!< Start Address(CAN Message Buffer Offset */ - uint8_t fifo_size; /*!< FIFO element count */ - uint8_t fifo_watermark; /*!< FIFO watermark */ - }; - uint32_t reg_val; /*!< register value */ -} mcan_tx_evt_fifo_config_t; - -/** - * @brief MCAN RAM Flexible Configuration - * - * @note This Configuration provides the full MCAN RAM configuration, this configuration is recommended only for - * experienced developers who is skilled at the MCAN IP - */ -typedef struct mcan_ram_flexible_config_struct { - bool enable_std_filter; /*!< Enable Standard Identifier Filter */ - bool enable_ext_filter; /*!< Enable Extended Identifier Filter */ - bool enable_rxfifo0; /*!< Enable RXFIFO */ - bool enable_rxfifo1; /*!< Enable RXFIF1 */ - bool enable_rxbuf; /*!< Enable RXBUF */ - bool enable_txbuf; /*!< Enable TXBUF */ - bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */ - - mcan_filter_config_t std_filter_config; /*!< Standard Identifier Filter Configuration */ - mcan_filter_config_t ext_filter_config; /*!< Extended Identifier Filter Configuration */ - - mcan_txbuf_config_t txbuf_config; /*!< TXBUF Configuration */ - mcan_txbuf_elem_config_t txbuf_elem_config; /*!< TXBUF Element Configuration */ - mcan_tx_evt_fifo_config_t tx_evt_fifo_config; /*!< TX Event FIFO Configuration */ - - mcan_rxfifo_config_t rxfifo0_config; /*!< RXFIFO0 Configuration */ - mcan_rxfifo_config_t rxfifo1_config; /*!< RXFIFO1 Configuration */ - mcan_rxbuf_config_t rxbuf_config; /*!< RXBUF Configuration */ - mcan_rx_fifo_or_buf_elem_config_t rx_elem_config; /*!< RX Element Configuration */ -} mcan_ram_flexible_config_t; - -/** - * @brief MCAN RAM configuration - * - * @note: This Configuration focuses on the minimum required information for MCAN RAM configuration - * The Start address of each BUF/FIFO will be automatically calculated by the MCAN Driver API - * This RAM configuration is recommended for the most developers - */ -typedef struct mcan_ram_config_struct { - bool enable_std_filter; /*!< Enable Standard Identifier Filter */ - uint8_t std_filter_elem_count; /*!< Standard Identifier Filter Element Count */ - - bool enable_ext_filter; /*!< Enable Extended Identifier Filter */ - uint8_t ext_filter_elem_count; /*!< Extended Identifier Filter Element Count */ - - struct { - uint32_t enable: 4; /*!< Enable Flag for RXFIFO */ - uint32_t elem_count: 8; /*!< Element Count for RXFIFO */ - uint32_t watermark: 8; /*!< Watermark for RXFIFO */ - uint32_t operation_mode: 4; /*!< Operation Mode for RXFIFO */ - uint32_t data_field_size: 8; /*!< Data field size option for RXFIFO */ - } rxfifos[2]; - - bool enable_rxbuf; /*!< Enable RXBUF */ - uint8_t rxbuf_elem_count; /*!< RXBUF Element count */ - uint16_t rxbuf_data_field_size; /*!< RXBUF Data Field Size option */ - - bool enable_txbuf; /*!< Enable TXBUF */ - uint8_t txbuf_data_field_size; /*!< TXBUF Data Field Size option */ - uint8_t txbuf_dedicated_txbuf_elem_count; /*!< Dedicated TXBUF element count */ - uint8_t txbuf_fifo_or_queue_elem_count; /*!< FIFO/Queue element count */ - uint8_t txfifo_or_txqueue_mode; /*!< TXFIFO/QUEUE mode */ - - bool enable_tx_evt_fifo; /*!< Enable TX Event FIFO */ - uint8_t tx_evt_fifo_elem_count; /*!< TX Event FIFO Element count */ - uint8_t tx_evt_fifo_watermark; /*!< TX Event FIFO Watermark */ -} mcan_ram_config_t; - -/** - * @brief MCAN Accept Non-Matching Frame options - */ -#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0 (0U) /*!< Save non-matching frame to RXFIFO0 */ -#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO1 (1U) /*!< Save non-matching frame to RXFIFO1 */ -#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT (2U) /*!< Reject non-matching frame */ - -/** - * @brief MCAN Global CAN configuration - */ -typedef struct mcan_global_filter_config_struct { - uint8_t accept_non_matching_std_frame_option; /*!< Accept non-matching standard frame option */ - uint8_t accept_non_matching_ext_frame_option; /*!< Accept non-matching extended frame option */ - bool reject_remote_std_frame; /*!< Reject Remote Standard Frame */ - bool reject_remote_ext_frame; /*!< Reject Remote Extended Frame */ -} mcan_global_filter_config_t; - -/** - * @brief MCAN Filter type definitions - */ -#define MCAN_FILTER_TYPE_RANGE_FILTER (0U) /*!< CAN Identifier Range filter */ -#define MCAN_FILTER_TYPE_SPECIFIED_ID_FILTER (1U) /*!< CAN Identifier ID filter */ -#define MCAN_FILTER_TYPE_CLASSIC_FILTER (2U) /*!< CAN classic filter */ -#define MCAN_FILTER_TYPE_FILTER_DISABLED (3U) /*!< CAN filter disabled */ -#define MCAN_FILTER_TYPE_DUAL_ID_EXT_FILTER_IGNORE_MASK /*!< CAN Identifier Range filter, ignoring extended ID mask */ - -/** - * @brief MCAN Filter Configuration Options - */ -#define MCAN_FILTER_ELEM_CFG_DISABLED (0) /*!< Disable Filter Element */ -#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH (1U) /*!< Store data into RXFIFO0 if matching */ -#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO1_IF_MATCH (2U) /*!< Store data into RXFIFO1 if matching */ -#define MCAN_FILTER_ELEM_CFG_REJECT_ID_IF_MATCH (3U) /*!< Reject ID if matching */ -#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_IF_MATCH (4U) /*!< Set Priority if matching */ -/*!< Set Priority and store into RXFIFO0 if matching */ -#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO0_IF_MATCH (5U) -/*!< Set Priority and store into RXFIFO1 if matching */ -#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO1_IF_MATCH (6U) -#define MCAN_FILTER_ELEM_CFG_STORE_INTO_RX_BUFFER_OR_AS_DBG_MSG (7U) /*!< Store into RXBUF if matching */ - -/** - * @brief MCAN Filter Element definitions - */ -typedef struct mcan_std_id_filter_elem_struct { - uint8_t filter_type; /*!< Filter type */ - uint8_t filter_config; /*!< Filter configuration */ - uint8_t can_id_type; /*!< CAN ID type */ - uint8_t sync_message; /*!< Sync Message */ - union { - /* This definition takes effect if the filter type is range filter */ - struct { - uint32_t start_id; /*!< Start of ID range */ - uint32_t end_id; /*!< End of ID range */ - }; - /* This definition takes effect if the filter type is dual id filter */ - struct { - uint32_t id1; /*!< ID1 */ - uint32_t id2; /*!< ID2 */ - }; - /* This definition takes effect if the filter type is classic filter */ - struct { - uint32_t filter_id; /*!< Filter ID */ - uint32_t filter_mask; /*!< Filter Mask */ - }; - /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message" - * - * In this definition, only the exact ID matching mode is activated - */ - struct { - uint32_t match_id; /*!< Matching ID */ - uint32_t offset: 6; /*!< RX Buffer Index */ - uint32_t filter_event: 3; /*!< Filter event, set to 0 */ - uint32_t store_location: 2; /*!< Store location, 0 - RX buffer */ - uint32_t : 21; - }; - }; -} mcan_filter_elem_t; - -/** - * @brief MCAN Filter Element List structure - */ -typedef struct mcan_filter_elem_list_struct { - uint32_t mcan_filter_elem_count; /*!< Number of Filter element */ - const mcan_filter_elem_t *filter_elem_list; /*!< Filter element list */ -} mcan_filter_elem_list_t; - -/** - * @brief MCAN Configuration for all filters - * - * @note The MCAN RAM related settings are excluded - */ -typedef struct mcan_all_filters_config_struct { - mcan_global_filter_config_t global_filter_config; /*!< Global Filter configuration */ - uint32_t ext_id_mask; /*!< Extended ID mask */ - mcan_filter_elem_list_t std_id_filter_list; /*!< Standard Identifier Configuration List */ - mcan_filter_elem_list_t ext_id_filter_list; /*!< Extended Identifier Configuration List */ -} mcan_all_filters_config_t; - -/** - * @brief CAN Node Mode types - */ -typedef enum mcan_node_mode_enum { - mcan_mode_normal = 0, /*!< CAN works in normal mode */ - mcan_mode_loopback_internal = 1, /*!< CAN works in internal loopback mode */ - mcan_mode_loopback_external = 2, /*!< CAN works in external loopback mode */ - mcan_mode_listen_only = 3, /*!< CAN works in listen-only mode */ -} mcan_node_mode_t; - -/** - * @brief MCAN Timestamp Value - */ -typedef struct mcan_timestamp_value_struct { - bool is_16bit; /*!< Timestamp is 16-bit */ - bool is_32bit; /*!< Timestamp is 32-bit */ - bool is_64bit; /*!< Timestamp is 64-bit */ - bool is_empty; /*!< Timestamp is empty */ - union { - uint16_t ts_16bit; /*!< 16-bit timestamp value */ - uint32_t ts_32bit; /*!< 32-bit timestamp value */ - uint64_t ts_64bit; /*!< 64-bit timestamp value */ - uint32_t words[2]; /*!< timestamp words */ - }; -} mcan_timestamp_value_t; - -/** - * @brief MCAN TSU Configuration - */ -typedef struct mcan_tsu_config_struct { - uint16_t prescaler; /*!< Prescaler for MCAN clock, Clock source: AHB clock */ - bool capture_on_sof; /*!< Capture On SOF, true - Capture on SOF, false - Capture on EOF */ - bool use_ext_timebase; /*!< Use External Timebase */ - uint8_t ext_timebase_src; /*!< External Timebase source, see the hpm_mcan_soc.h for more details */ - uint8_t tbsel_option; /*!< Timebase selection option, see the hpm_mcan_soc.h for more details */ - bool enable_tsu; /*!< Enable Timestamp Unit */ - bool enable_64bit_timestamp; /*!< Enable 64bit Timestamp */ -} mcan_tsu_config_t; - -/** - * @brief MCAN Timestamp Select - */ -#define MCAN_TIMESTAMP_SEL_MIN (0U) -#define MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO (0U) /*!< Timestamp value always equal to 0 */ -#define MCAN_TIMESTAMP_SEL_VALUE_INCREMENT (1U) /*!< Timestamp value increments according to prescaler */ -#define MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED (2U) /*!< External Timestamp value used */ -#define MCAN_TIMESTAMP_SEL_MAX (MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED) - -/** - * @brief MCAN Internal timestamp configuration - */ -typedef struct mcan_internal_timestamp_config_struct { - uint8_t counter_prescaler; /*!< Timestamp Counter Prescaler, clock source: AHB clock */ - uint8_t timestamp_selection; /*!< Timestamp Select */ -} mcan_internal_timestamp_config_t; - -/** - * @brief MCAN Timeout Selection Options - */ -typedef enum mcan_timeout_sel_enum { - mcan_timeout_continuous_operation = 0, /*!< Continuously count down timeout after writing to TOCV register */ - mcan_timeout_triggered_by_tx_evt_fifo = 1, /*!< Count down if the TX EVT FIFO is not empty */ - mcan_timeout_triggered_by_rx_fifo0 = 2, /*!< Count down if the RX FIFO0 is not empty */ - mcan_timeout_triggered_by_rx_fifo1 = 3, /*!< Count down if the RX FIFO1 is not empty */ -} mcan_timeout_sel_t; - -/** - * @brief MCAN Timeout configuration structure - */ -typedef struct mcan_timeout_config_struct { - bool enable_timeout_counter; /*!< Enable Timeout Counter */ - mcan_timeout_sel_t timeout_sel; /*!< Timeout source selection */ - uint16_t timeout_period; /*!< Timeout period */ -} mcan_timeout_config_t; - -/** - * @brief MCAN Transmitter Delay Compensation Configuration - */ -typedef struct mcan_tdc_config_t { - uint8_t ssp_offset; /*!< SSP offset */ - uint8_t filter_window_length; /*!< Filter Window Length */ -} mcan_tdc_config_t; - - -/** - * @brief MCAN Configuration Structure - */ -typedef struct mcan_config_struct { - union { - /* This struct takes effect if "use_lowlevel_timing_setting = false" */ - struct { - uint32_t baudrate; /*!< CAN 2.0 baudrate/CAN-FD Nominal Baudrate, in terms of bps */ - uint32_t baudrate_fd; /*!< CANFD data baudrate, in terms of bps */ - uint16_t can20_samplepoint_min; /*!< Value = Minimum CAN2.0 sample point * 10 */ - uint16_t can20_samplepoint_max; /*!< Value = Maximum CAN2.0 sample point * 10 */ - uint16_t canfd_samplepoint_min; /*!< Value = Minimum CANFD sample point * 10 */ - uint16_t canfd_samplepoint_max; /*!< Value = Maximum CANFD sample point * 10 */ - }; - /* This struct takes effect if "use_lowlevel_timing_setting = true" */ - struct { - mcan_bit_timing_param_t can_timing; /*!< CAN2.0/CANFD nominal timing setting */ - mcan_bit_timing_param_t canfd_timing; /*!< CANFD data timing setting */ - }; - }; - bool use_lowlevel_timing_setting; /*!< Use Low-level timing setting */ - mcan_node_mode_t mode; /*!< CAN node mode */ - bool enable_non_iso_mode; /*!< Enable Non-ISO FD mode */ - bool enable_transmit_pause; /*!< Enable Transmit Pause */ - bool enable_edge_filtering; /*!< Enable Edge Filtering */ - bool disable_protocol_exception_handling; /*!< Disable Protocol Exception Handling */ - bool enable_wide_message_marker; /*!< Enable Wide Message Marker */ - bool use_timestamping_unit; /*!< Use external Timestamp Unit */ - bool enable_canfd; /*!< Enable CANFD mode */ - bool enable_tdc; /*!< Enable transmitter delay compensation */ - bool enable_restricted_operation_mode; /*!< Enable Restricted Operation Mode: Receive only */ - bool disable_auto_retransmission; /*!< Disable auto retransmission */ - mcan_tdc_config_t tdc_config; /*!< Transmitter Delay Compensation Configuration */ - mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */ - mcan_tsu_config_t tsu_config; /*!< TSU configuration */ - mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */ - mcan_all_filters_config_t all_filters_config; /*!< All Filter configuration */ - - mcan_timeout_config_t timeout_cfg; /*!< Timeout configuration */ - - uint32_t interrupt_mask; /*!< Interrupt Enable mask */ - uint32_t txbuf_trans_interrupt_mask; /*!< Tx Buffer Transmission Interrupt Enable mask */ - uint32_t txbuf_cancel_finish_interrupt_mask; /*!< TX Buffer Cancellation Finished Interrupt Enable Mask */ -} mcan_config_t; - -/** - * @brief MCAN Timeout Selection Options - */ -#define MCAN_TIMEOUT_SEL_TYPE_CONTINUOUS_OPERATION (0U) -#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_TX_EVT_FIFO (1U) -#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO0 (2U) -#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO1 (3U) - -/** - * @brief MCAN Timeout Counter Configuration - */ -typedef struct mcan_timeout_counter_config_struct { - bool enable_timeout_counter; /*!< Enable Timeout counter */ - uint8_t timeout_selection; /*!< Timeout source selection */ - uint16_t timeout_period; /*!< Timeout period */ -} mcan_timeout_counter_config_t; - -/** - * @brief MCAN Error Count Information - */ -typedef struct mcan_error_count_struct { - uint8_t transmit_error_count; /*!< Transmit Error Count */ - uint8_t receive_error_count; /*!< Receive Error Count */ - bool receive_error_passive; /*!< The Receive Error Counter has reached the error passive level */ - uint8_t can_error_logging_count; /*!< CAN Error Logging count */ -} mcan_error_count_t; - -/** - * @brief MCAN Protocol Status - */ -typedef struct mcan_protocol_status { - uint8_t tdc_val; /*!< Transmitter Delay Compensation Value */ - mcan_activity_state_t activity; /*!< Current communication state */ - mcan_last_err_code_t last_error_code; /*!< Last Error code */ - bool protocol_exception_evt_occurred; /*!< Protocol Exception Event occurred */ - bool canfd_msg_received; /*!< CANFD message was received */ - bool brs_flag_set_in_last_rcv_canfd_msg; /*!< Bitrate Switch bit is set in last received CANFD message */ - bool esi_flag_set_in_last_rcv_canfd_msg; /*!< Error State Indicator bit is set in last received CANFD message */ - bool in_bus_off_state; /*!< Node is in bus-off state */ - bool in_warning_state; /*!< Node is in warning state */ - bool in_error_passive_state; /*!< Node is in error passive state */ -} mcan_protocol_status_t; - -/** - * @brief MCAN Message Storage Indicator Types - */ -#define MCAN_MESSAGE_STORAGE_INDICATOR_NO_FIFO_SELECTED (0U) -#define MCAN_MESSAGE_STORAGE_INDICATOR_FIFO_MESSAGE_LOST (1U) -#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO0 (2U) -#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO1 (3U) - -/** - * @brief MCAN High Priority Message Status Information - */ -typedef struct mcan_high_priority_message_status_struct { - uint8_t filter_list_type; /*!< Filter List Type, 0 - STD filter, 1 - EXT filter */ - uint8_t filter_index; /*!< Filter Elem List */ - uint8_t message_storage_indicator; /*!< Message Storage Indicator */ - uint8_t buffer_index; -} mcan_high_priority_message_status_t; - -/** - * @brief Enable Transmit Pause - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_transmit_pause(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_TXP_MASK; -} - -/** - * @brief Disable Transmit Pause - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_transmit_pause(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_TXP_MASK; -} - -/** - * @brief Enable Edge Filtering - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_edge_filtering(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_EFBI_MASK; -} - -/** - * @brief Disable Edge Filtering - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_edge_filtering(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; -} - -/** - * @brief Enable Protocol Exception Handling - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_protocol_exception_handling(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK; -} - -/** - * @brief Disable Protocol Exception Handling - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_protocol_exception_handling(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_PXHD_MASK; -} - -/** - * @brief Enable Wide Message Marker - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_wide_message_marker(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_WMM_MASK; -} - -/** - * @brief Disable Wide Message Marker - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_wide_message_marker(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_WMM_MASK; -} - -/** - * @brief Enable External Timestamp Unit - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_tsu(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_UTSU_MASK; -} - -/** - * @brief Disable External Timestamp Unit - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_tsu(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK; -} - -/** - * @brief Check whether TSU is used - * @param [in] ptr MCAN base - * @retval true if TSU is used - * @retval false if TSU is not used - */ -static inline bool mcan_is_tsu_used(MCAN_Type *ptr) -{ - return ((ptr->CCCR & MCAN_CCCR_UTSU_MASK) != 0U); -} - -/** - * @brief Check whether 64-bit TSU timestamp is used - * @param [in] ptr MCAN base - * @retval true if 64-bit timestamp is used - * @retval false if 32-bit timestamp is used - */ -static inline bool mcan_is_64bit_tsu_timestamp_used(MCAN_Type *ptr) -{ - return ((ptr->TSCFG & MCAN_TSCFG_EN64_MASK) != 0U); -} - -/** - * @brief Enable Bit Rate Switch - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_bitrate_switch(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_BRSE_MASK; -} - -/** - * @brief Disable Bit Rate Switch - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_bitrate_switch(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_BRSE_MASK; -} - -/** - * @brief Enable Auto Retransmission - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_auto_retransmission(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_DAR_MASK; -} - -/** - * @brief Disable Auto Transmission - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_DAR_MASK; -} - -/** - * @brief Enable Bus monitoring Mode - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_bus_monitoring_mode(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_MON_MASK; -} - -/** - * @brief Stop MCAN clock - * @param [in] ptr MCAN base - */ -static inline void mcan_stop_clock(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_CSR_MASK; -} - -/** - * @brief Enable MCAN clock - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_clock(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_CSR_MASK; -} - -static inline bool mcan_is_clock_enabled(MCAN_Type *ptr) -{ - return ((ptr->CCCR & MCAN_CCCR_CSR_MASK) == 0UL); -} - -/** - * @brief Disable Bus monitoring Mode - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_MON_MASK; -} - -/** - * @brief Check whether CAN clock is stopped or not - * @param [in] ptr MCAN base - */ -static inline bool mcan_is_clock_stopped(MCAN_Type *ptr) -{ - return ((ptr->CCCR & MCAN_CCCR_CSA_MASK) != 0U); -} - -/** - * @brief Enable Restricted Operation Mode - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_restricted_operation_mode(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_ASM_MASK; -} - -/** - * @brief Disable Restricted Operation Mode - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; -} - -/** - * @brief Enable Write Access to Protected Configuration Registers - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_write_to_prot_config_registers(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_CCE_MASK; -} - -/** - * @brief Disable Write Access to Protected Configuration Registers - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_write_to_prot_config_registers(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_CCE_MASK; -} - -/** - * @brief Get Timestamp Counter Value - * @param [in] ptr MCAN base - * @return timestamp value - */ -static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr) -{ - return ptr->TSCV; -} - -/** - * @brief Switch MCAN to Initialization mode - * @param [in] ptr MCAN base - */ -static inline void mcan_enter_init_mode(MCAN_Type *ptr) -{ - ptr->CCCR |= MCAN_CCCR_INIT_MASK; -} - -/** - * @brief Switch MCAN to Normal mode - * @param [in] ptr MCAN base - */ -static inline void mcan_enter_normal_mode(MCAN_Type *ptr) -{ - ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; -} - -/** - * @brief Get Timeout value - * @param [in] ptr MCAN base - * @return timeout value - */ -static inline uint16_t mcan_get_timeout_counter_value(MCAN_Type *ptr) -{ - return ptr->TOCV; -} - -/** - * @brief Reset Timeout counter value - * - * @param [in] ptr MCAN base - */ -static inline void mcan_reset_timeout_counter_value(MCAN_Type *ptr) -{ - *((volatile uint32_t *) &ptr->TOCV) = 0; -} - -/** - * @brief Get Error Counter Information - * @param [in] ptr MCAN base - * @param [out] err_cnt Error Count buffer - */ -static inline void mcan_get_error_counter(MCAN_Type *ptr, mcan_error_count_t *err_cnt) -{ - uint32_t ecr = ptr->ECR; - err_cnt->transmit_error_count = MCAN_ECR_TEC_GET(ecr); - err_cnt->receive_error_count = MCAN_ECR_REC_GET(ecr); - err_cnt->receive_error_passive = (MCAN_ECR_RP_GET(ecr) == 1U); - err_cnt->can_error_logging_count = MCAN_ECR_CEL_GET(ecr); -} - -/** - * @brief Get Last Error Code - * @param [in] ptr MCAN base - * @return Last Error code - */ -static inline uint8_t mcan_get_last_error_code(MCAN_Type *ptr) -{ - return MCAN_PSR_LEC_GET(ptr->PSR); -} - -/** - * @brief Get Last Data Phase Error Code - * @param [in] ptr MCAN base - * @return Last Error Code in Data phase - */ -static inline uint8_t mcan_get_last_data_error_code(MCAN_Type *ptr) -{ - return MCAN_PSR_DLEC_GET(ptr->PSR); -} - -/** - * @brief Get CAN Activity - * @param [in] ptr MCAN base - * @return CAN IP activity - */ -static inline uint8_t mcan_get_activity(MCAN_Type *ptr) -{ - return MCAN_PSR_ACT_GET(ptr->PSR); -} - -/** - * @brief Check whether the CAN node is under error passive state - * @param [in] ptr MCAN base - * @return true is CAN is under error passive state - */ -static inline bool mcan_is_in_err_passive_state(MCAN_Type *ptr) -{ - return (MCAN_PSR_EP_GET(ptr->PSR) == 1U); -} - -/** - * @brief Check whether the CAN mode is under Warning State - * @param [in] ptr MCAN base - * @return true if the CAN node is under Error Warning State - */ -static inline bool mcan_is_in_error_warning_state(MCAN_Type *ptr) -{ - return (MCAN_PSR_EW_GET(ptr->PSR) == 1U); -} - -/** - * @brief Check whether the CAN node is under Bus-off state - * @param [in] ptr MCAN base - * @return true if the CAN node is under Bus-off state - */ -static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr) -{ - return (MCAN_PSR_BO_GET(ptr->PSR) == 1U); -} - -/** - * @brief Get the Last Data Phase Error - * @param [in] ptr MCAN base - * @deprecated This API will be removed in later SDK release - * @return The last Data Phase Error - */ -static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr) -{ - return MCAN_PSR_DLEC_GET(ptr->PSR); -} - -/** - * @brief Check Whether the Error Status Indicator Flag is set in the last received CANFD message - * @param [in] ptr MCAN base - * @return true if the Error Status Indicator Flag is set in the last received CANFD Message - */ -static inline bool mcan_is_error_state_indicator_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr) -{ - return (MCAN_PSR_RESI_GET(ptr->PSR) == 1U); -} - -/** - * @brief Check whether the Bitrate Switch Flag is set in the last received CANFD message - * @param [in] ptr MCAN base - * @return true if Bit rate switch flag is set in the last received CANFD message - */ -static inline bool mcan_is_bitrate_switch_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr) -{ - return (MCAN_PSR_RBRS_GET(ptr->PSR) == 1U); -} - -/** - * @brief Check whether CANFD messages were received - * @param [in] ptr MCAN base - * @return true if a CANFD message was received - */ -static inline bool mcan_is_canfd_message_received(MCAN_Type *ptr) -{ - return (MCAN_PSR_RFDF_GET(ptr->PSR) == 1U); -} - -/** - * @brief Check whether Protocol Exception Events were occurred - * @param [in] ptr MCAN base - * @return true if Protocol Exception Events were occurred - */ -static inline bool mcan_is_protocol_exception_event_occurred(MCAN_Type *ptr) -{ - return (MCAN_PSR_PXE_GET(ptr->PSR) == 1U); -} - -/** - * @brief Get the Transmitter Delay Compensation Value - * @param [in] ptr MCAN base - * @return Transmitter Delay Compensation value - */ -static inline uint8_t mcan_get_transmitter_delay_compensation_value(MCAN_Type *ptr) -{ - return MCAN_PSR_TDCV_GET(ptr->PSR); -} - -/** - * @brief Get Interrupt Flags - * @param [in] ptr MCAN base - * @return Interrupt Flags - */ -static inline uint32_t mcan_get_interrupt_flags(MCAN_Type *ptr) -{ - return ptr->IR; -} - -/** - * @brief Clear Interrupt Flags - * @param [in] ptr MCAN base - * @param [in] mask Interrupt Mask - */ -static inline void mcan_clear_interrupt_flags(MCAN_Type *ptr, uint32_t mask) -{ - ptr->IR = mask; -} - -/** - * @brief Enable Interrupts - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask) -{ - ptr->ILS &= ~mask; - ptr->IE |= mask; - ptr->ILE = 1U; -} - -/** - * @brief Enable TXBUF Interrupt - * @deprecated This API is deprecated, will be removed in later SDK release - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) -{ - ptr->TXBTIE |= mask; -} - -/** - * @brief Disable TXBUF Interrupt - * @deprecated This API is deprecated, will be removed in later SDK release - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_disable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask) -{ - ptr->TXBTIE &= ~mask; -} - -/** - * @brief Disable Interrupts - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_disable_interrupts(MCAN_Type *ptr, uint32_t mask) -{ - ptr->IE &= ~mask; -} - -/** - * @brief Enable TXBUF Transmission interrupt - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_enable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask) -{ - ptr->TXBTIE |= mask; -} - -/** - * @brief Disable TXBUF Transmission interrupt - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_disable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask) -{ - ptr->TXBTIE &= ~mask; -} - -/** - * @brief Enable TXBUF Cancellation Finish interrupt - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_enable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask) -{ - ptr->TXBCIE |= mask; -} - -/** - * @brief Disable TXBUF Cancellation Finish interrupt - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - */ -static inline void mcan_disable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask) -{ - ptr->TXBCIE &= ~mask; -} - -/** - * @brief Select Interrupt Line - * @param [in] ptr MCAN base - * @param [in] mask Interrupt mask - * @param [in] line_index Interrupt Line Index - */ -static inline void mcan_interrupt_line_select(MCAN_Type *ptr, uint32_t mask, uint8_t line_index) -{ - if (line_index == 0) { - ptr->ILS &= ~mask; - } else { - ptr->ILS |= mask; - } - ptr->ILE = (1UL << line_index); -} - -/** - * @brief Check whether a TXFIFO/TXBUF transmission request is pending - * @param [in] ptr CAN Base - * @param [in] index TXBUF/TXFIFO Index - * @return True is the specified TXFIFO/TXBUF Transmission request is pending - */ -static inline bool mcan_is_transmit_request_pending(MCAN_Type *ptr, uint32_t index) -{ - return ((ptr->TXBRP & ((1UL << index))) != 0U); -} - -/** - * @brief Check whether TXFIFO is full - * @param [in] ptr MCAN base - * @return true if TXFIFO is full - */ -static inline bool mcan_is_txfifo_full(MCAN_Type *ptr) -{ - return ((ptr->TXFQS & MCAN_TXFQS_TFQF_MASK) != 0U); -} - -/** - * @brief Get the TXFIFO Put Index - * @param [in] ptr MCAN base - * @return The TX FIFO Put Index - */ -static inline uint32_t mcan_get_txfifo_put_index(MCAN_Type *ptr) -{ - return MCAN_TXFQS_TFQPI_GET(ptr->TXFQS); -} - -/** - * @brief Request A Transmission via specified TXBUF Index - * @param [in] ptr MCAN Base - * @param [in] index TXBUF index - */ -static inline void mcan_send_add_request(MCAN_Type *ptr, uint32_t index) -{ - ptr->TXBAR = (1UL << index); -} - -/** - * @brief Request several transmission via specified TXBUF/FIFO Bit masks - * MCAN IP will transmit data in the buffer if corresponding bit in index_bitmask is asserted - * @param [in] ptr MCAN Base - * @param [in] index_bitmask TXFIFO/BUF bit masks - */ -static inline void mcan_send_add_multiple_requests(MCAN_Type *ptr, uint32_t index_bitmask) -{ - ptr->TXBAR = index_bitmask; -} - -/** - * @brief Cancel the TXBUF Send request - * @param [in] ptr MCAN Base - * @param [in] index TXBUF index - */ -static inline void mcan_cancel_tx_buf_send_request(MCAN_Type *ptr, uint32_t index) -{ - ptr->TXBCR = (1UL << index); -} - -/** - * @brief Check whether the Transmission completed via specified TXBUF/TXFIFO - * @param [in] ptr MCAN base - * @param [in] index TXBUF Index - * @return True is the Transmission completed via specified TXBUF - */ -static inline bool mcan_is_transmit_occurred(MCAN_Type *ptr, uint32_t index) -{ - return ((ptr->TXBTO & (1UL << index)) != 0U); -} - -/** - * @brief Check Whether there are data available in specified RXBUF - * @param [in] ptr MCAN Base - * @param [in] index RXBUF index - * @return True if there are data available - */ -static inline bool mcan_is_rxbuf_data_available(MCAN_Type *ptr, uint32_t index) -{ - bool result; - if (index < 32U) { - result = (ptr->NDAT1 & (1UL << index)) != 0U; - } else if (index < 64U) { - result = (ptr->NDAT2 & (1UL << (index - 32U))) != 0U; - } else { - result = false; - } - return result; -} - -/** - * @brief Clear RXBUF Data available Flag for specified RXBUF - * @param [in] ptr MCAN base - * @param [in] index RXBUF index - */ -static inline void mcan_clear_rxbuf_data_available_flag(MCAN_Type *ptr, uint32_t index) -{ - if (index < 32U) { - ptr->NDAT1 = (1UL << index); - } else if (index < 64U) { - ptr->NDAT2 = (1UL << (index - 32U)); - } else { - /* Do nothing */ - } -} - -/** - * @brief Check whether specified Interrupt is set - * @param [in] ptr MCAN Base - * @param [in] mask Interrupt Flags - * @retval true if corresponding bits are set - */ -static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask) -{ - return ((ptr->IR & mask) != 0U); -} - -/** - * @brief Check whether the TSU timestamp is available - * - * @param [in] ptr MCAN base - * @param [in] index Timestamp pointer - * @retval true TSU Timestamp is available - * @retval false TSU timestamp is unavailable - */ -static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index) -{ - bool is_available = false; - if (index < ARRAY_SIZE(ptr->TS_SEL)) { - is_available = ((ptr->TSS1 & (1UL << index)) != 0U); - } - return is_available; -} - -/** - * @brief Read 32bit Timestamp value from TSU - * @param [in] ptr MCAN Base - * @param [in] index Timestamp pointer - * @return Timestamp value - */ -uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index); - -/** - * @brief Read 64bit Timestamp value from TSU - * @param [in] ptr MCAN Base - * @param [in] index Timestamp pointer - * @return Timestamp value - */ -uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index); - -/** - * @brief Get High Priority Message Status - * @param [in] ptr MCAN base - * @param [out] status Pointer to High Priority Message Status Buffer - */ -void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status); - -/** - * @brief Get Default CAN configuration - * @param [in] ptr MCAN base - * @param [out] config CAN configuration - */ -void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config); - -/** - * @brief Get message Size from Data Length Code - * @param [in] dlc Data Length Code - * @return Message Size in Bytes - */ -uint8_t mcan_get_message_size_from_dlc(uint8_t dlc); - -/** - * @brief Get the Data field size from data field size option - * - * @param [in] data_field_size_option Data size option - * @return data field size in bytes - */ -uint8_t mcan_get_data_field_size(uint8_t data_field_size_option); - -/** - * @brief Get Default Full MCAN RAM configuration - * If the device is configured as classic CAN node, the default CAN RAM settings are as below: - * - Standard Identifier Filter Elements: 32 - * - Extended Identifier Filter Elements: 32 - * - TXBUF Elements Info: - * - Element Count:32 - * - Dedicated TXBUF element count: 16 - * - TXFIFO/QQueue element count: 16 - * - Data Field Size: 8 - * . - * - RXFIFO0 Elements Info: - * - Element Count :32 - * - Data Field Size: 8 - * . - * - RXFIFO1 Elements Info: - * - Element Count : 32 - * - Data Field Size: 8 - * . - * - RXBUF Element Info: - * - Element Count: 16 - * - Data Field Size : 8 - * . - * - TX Event FIFO Element Count: 32 - * . - * If the device is configured as CANFD node, the default CAN RAM settings are as below: - * - Standard Identifier Filter Elements: 16 - * - Extended Identifier Filter Elements: 16 - * - TXBUF Elements Info: - * - Element Count:8 - * - Dedicated TXBUF element count: 4 - * - TXFIFO/QQueue element count: 4 - * - Data Field Size: 64 - * . - * - RXFIFO0 Elements Info: - * - Element Count : 8 - * - Data Field Size: 64 - * . - * - RXFIFO1 Elements Info: - * - Element Count : 8 - * - Data Field Size: 64 - * . - * - RXBUF Element Info: - * - Element Count: 4 - * - Data Field Size : 64 - * . - * - TX Event FIFO Element Count: 8 - * . - * @param [in] ptr MCAN base - * @param [out] ram_config CAN RAM Configuration - * @param [in] enable_canfd CANFD enable flag - */ -void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd); - -/** - * @brief Get Default MCAN RAM configuration - * If the device is configured as classic CAN node, the default CAN RAM settings are as below: - * - Standard Identifier Filter Elements: 32 - * - Extended Identifier Filter Elements: 32 - * - TXBUF Elements Info: - * - Element Count:32 - * - Dedicated TXBUF element count: 16 - * - TXFIFO/QQueue element count: 16 - * - Data Field Size: 8 - * . - * - RXFIFO0 Elements Info: - * - Element Count :32 - * - Data Field Size: 8 - * . - * - RXFIFO1 Elements Info: - * - Element Count : 32 - * - Data Field Size: 8 - * . - * - RXBUF Element Info: - * - Element Count: 16 - * - Data Field Size : 8 - * . - * - TX Event FIFO Element Count: 32 - * . - * If the device is configured as CANFD node, the default CAN RAM settings are as below: - * - Standard Identifier Filter Elements: 16 - * - Extended Identifier Filter Elements: 16 - * - TXBUF Elements Info: - * - Element Count:8 - * - Dedicated TXBUF element count: 4 - * - TXFIFO/QQueue element count: 4 - * - Data Field Size: 64 - * . - * - RXFIFO0 Elements Info: - * - Element Count : 8 - * - Data Field Size: 64 - * . - * - RXFIFO1 Elements Info: - * - Element Count : 8 - * - Data Field Size: 64 - * . - * - RXBUF Element Info: - * - Element Count: 4 - * - Data Field Size : 64 - * . - * - TX Event FIFO Element Count: 8 - * . - * @param [in] ptr MCAN base - * @param [out] simple_config Simple CAN RAM Configuration - * @param [in] enable_canfd CANFD enable flag - */ -void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd); - -/** - * @brief Initialize CAN controller - * @param [in] ptr MCAN base - * @param [in] config CAN configuration - * @param [in] src_clk_freq CAN clock frequency - * @retval status_success if operation is successful - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq); - -/** - * @brief De-Initialize CAN controller - * - * @param [in] ptr MCAN base - */ -void mcan_deinit(MCAN_Type *ptr); - -/** - * @brief Configure MCAN RAM will Full RAM configuration - * @param [in] ptr MCAN base - * @param [in] config MCAN RAM Full Configuration - * @return status_success if no errors reported - */ -hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config); - -/** - * @brief Configure MCAN RAM will Simplified RAM configuration - * @param [in] ptr MCAN base - * @param [in] config MCAN RAM configuration - * @return status_success if no errors reported - */ -hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config); - -/** - * @brief Configure All CAN filters - * @param [in] ptr MCAN base - * @param [in] config All CAN Filter configuration - * @return status_success if no errors reported - */ -hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config); - -/** - * @brief Configure Transmitter Delay Compensation - * @param [in] ptr MCAN base - * @param [in] config Transmitter Delay compensation configure - * @return status_success if no errors reported - */ -hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config); - -/** - * @brief Configure Global Filter - * @param [in] ptr MCAN base - * @param [in] filter_config Global Filter Configuration - * @return status_success if no errors reported - */ -hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config); - -/** - * @brief Set CAN filter element - * @param [in] ptr MCAN base - * @param [in] filter_elem CAN filter element - * @param [in] index CAN Filter element index - * @return status_success if no errors reported - */ -hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index); - -/** - * @brief Write Frame to CAN TX Buffer - * @param [in] ptr MCAN base - * @param [in] index TX Buffer Index - * @param [in] tx_frame TX frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); - -/** - * @brief Write Frame CAN to TXFIFO - * @param [in] ptr MCAN base - * @param [in] tx_frame TX frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); - -/** - * @brief Read message from CAN RXBUF - * @param [in] ptr MCAN base - * @param [in] index Index of RXBUF - * @param [out] rx_frame Buffer to hold RX frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame); - -/** - * @brief Read message from CAN RXBUF - * @param [in] ptr MCAN base - * @param [in] fifo_index RXFIFO index, 0 - RXFO0, 1 - RXFIFO1 - * @param [out] rx_frame Buffer to hold RX frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame); - -/** - * @brief Read TX Event from CAN TX EVENT FIFO - * @param [in] ptr MCAN base - * @param [out] tx_evt TX Event Buffer - * @retval status_success if no errors happened - * @retval status_mcan_tx_evt_fifo_empty if there are no TX events available - * @retval status_invalid_argument if any parameters are invalid - */ -hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt); - -/** - * @brief Transmit CAN message in blocking way - * @param [in] ptr MCAN base - * @param [in] tx_frame CAN Transmit Message buffer - * @return status_success if no errors reported - */ -hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame); - -/** - * @brief Request TXFIFO and fill data into TXFIFO - * @note This API can be used to prepare the data for several CAN frames prior to transmission. - * After this operation, software can call `mcan_send_add_request(ptr, *fifo_index)` API to trigger a transmission - * or call `mcan_send_add_requests(ptr, fifo_index_masks)` to trigger several transmissions - * @param [in] ptr MCAN base - * @param [in] tx_frame CAN Transmit Message buffer - * @param [out] fifo_index The index of the element in FIFO assigned to the tx_frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_request_and_fill_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index); - -/** - * @brief Transmit CAN message via TX FIFO in non-blocking way - * @param [in] ptr MCAN base - * @param [in] tx_frame CAN Transmit Message buffer - * @param [out] fifo_index The index of the element in FIFO assigned to the tx_frame - * - * @return status_success if no errors reported - */ -hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index); - -/** - * @brief Transmit CAN message via TX in non-blocking way - * @param [in] ptr MCAN base - * @param [in] index Index of TX Buffer - * @param [in] tx_frame CAN Transmit Message buffer - * @return status_success if no errors reported - */ -hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame); - -/** - * @brief Receive CAN Frame from RXBUF in blocking way - * @param [in] ptr MCAN base - * @param [in] index RXBUF index - * @param [out] rx_frame Buffer to hold Received Frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame); - -/** - * @brief Receive CAN Frame from RXFIFO in blocking way - * @param [in] ptr MCAN base - * @param [in] fifo_index RXFIFO index, 0 - RXFIFO0, 1 - RXFIFO1 - * @param [out] rx_frame Buffer to hold Received Frame - * @return status_success if no errors reported - */ -hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame); - -/** - * @brief Get Timestamp from MCAN TX Event - * @param [in] ptr MCAN base - * @param [in] tx_evt TX Event Element - * @param [out] timestamp Timestamp value - * @retval status_success if no errors happened - * @retval status_invalid_argument if any parameters are invalid - * @retval status_mcan_timestamp_not_exist if no timestamp information is available - */ -hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr, - const mcan_tx_event_fifo_elem_t *tx_evt, - mcan_timestamp_value_t *timestamp); - -/** - * @brief Get Timestamp from MCAN RX frame - * @param [in] ptr MCAN base - * @param [in] rx_msg Received message - * @param [out] timestamp Timestamp value - * @retval status_success if no errors happened - * @retval status_invalid_argument if any parameters are invalid - * @retval status_mcan_timestamp_not_exist if no timestamp information is available - */ -hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, - const mcan_rx_message_t *rx_msg, - mcan_timestamp_value_t *timestamp); - -/** - * @brief Parse the Protocol Status register value - * @param [in] psr Protocol Status Register Value - * @param [out] protocol_status Translated Protocol Status - * - * @retval status_invalid_argument if any parameters are invalid - * @retval status_success if no errors happened - */ -hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status); - -/** - * @brief Get MCAN Protocol Status - * @param [in] ptr MCAN base - * @param [out] protocol_status Translated Protocol status - * - * @retval status_invalid_argument if any parameters are invalid - * @retval status_success if no errors happened - */ -hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status); - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* HPM_MCAN_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h deleted file mode 100644 index a64380ef74f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mchtmr_drv.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MCHTMR_DRV_H -#define HPM_MCHTMR_DRV_H -#include "hpm_common.h" -#include "hpm_mchtmr_regs.h" - -/** - * @brief MCHTMR driver APIs - * @defgroup mchtmr_interface MCHTMR driver APIs - * @ingroup io_interfaces - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief mchtmr get counter value - * - * @param [in] ptr MCHTMR base address - */ -static inline uint64_t mchtmr_get_count(MCHTMR_Type *ptr) -{ - return (ptr->MTIME & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT; -} - -/** - * @brief mchtmr set comparator value - * - * @param [in] ptr MCHTMR base address - * @param [in] target comparator target value - */ -static inline void mchtmr_set_compare_value(MCHTMR_Type *ptr, uint64_t target) -{ - ptr->MTIMECMP = MCHTMR_MTIMECMP_MTIMECMP_SET(target); -} - -/** - * @brief mchtmr set delay value - * - * @param [in] ptr MCHTMR base address - * @param [in] delay delay cycles - */ -static inline void mchtmr_delay(MCHTMR_Type *ptr, uint64_t delay) -{ - mchtmr_set_compare_value(ptr, mchtmr_get_count(ptr) + delay); -} - -/** - * @brief initialize mchtmr counter - * - * @param [in] ptr MCHTMR base address - * @param [in] v value to be set - */ -void mchtmr_init_counter(MCHTMR_Type *ptr, uint64_t v); - -/** - * @} - */ -#ifdef __cplusplus -} -#endif -#endif /* HPM_MCHTMR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_drv.h deleted file mode 100644 index e04d7feb0e1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_drv.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MIPI_CSI_DRV_H -#define HPM_MIPI_CSI_DRV_H - -/** - * @brief MIPI_CSI APIs - * @defgroup mipi_csi_interface MIPI_CSI driver APIs - * @ingroup mipi_csi_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_mipi_csi_regs.h" - -#define MIPI_CSI_PHY_STOP_MASK_CLK_LANE (0x01u<<16) -#define MIPI_CSI_PHY_STOP_MASK_DATA1_LANE (0x01u<<1) -#define MIPI_CSI_PHY_STOP_MASK_DATA0_LANE (0x01u<<0) - - -typedef enum mipi_csi_data_type { - mipi_csi_data_type_yuv420_8bit = 0x18, - mipi_csi_data_type_yuv422_8bit = 0x1e, - mipi_csi_data_type_rgb565 = 0x22, - mipi_csi_data_type_rgb666 = 0x23, - mipi_csi_data_type_rgb888 = 0x24, -} mipi_csi_data_type_t; - -typedef struct mipi_csi_config { - uint8_t lanes; /* !< max: 2. number of lane*/ - mipi_csi_data_type_t data_type; -} mipi_csi_config_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief get MIPI_CSI default config - * - * @param cfg: MIPI_CSI default config - */ -void mipi_csi_get_defconfig(mipi_csi_config_t *cfg); - -/** - * @brief MIPI_CSI init - * - * @param ptr MIPI_CSI base address - * @param cfg config of MIPI_CSI - */ -void mipi_csi_init(MIPI_CSI_Type *ptr, mipi_csi_config_t *cfg); - -/** - * @brief MIPI_CSI phy interface power on - * - * @param ptr MIPI_DCI base address - */ -void mipi_csi_phy_poweron(MIPI_CSI_Type *ptr); - -/** - * @brief MIPI_CSI phy interface power down - * - * @param ptr MIPI_CSI base address - */ -void mipi_csi_phy_powerdown(MIPI_CSI_Type *ptr); - -/** - * @brief MIPI_CSI check clklane whether on HS state - * - * @param ptr MIPI_DCI base address - * @return: true on HS or false not on HS. - */ -static inline bool mipi_csi_clklane_is_entry_hs(MIPI_CSI_Type *ptr) -{ - return !!(ptr->PHY_RX & MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK); -} - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_MIPI_CSI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_phy_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_phy_drv.h deleted file mode 100644 index 96f1378292b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_csi_phy_drv.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MIPI_CSI_PHY_DRV_H -#define HPM_MIPI_CSI_PHY_DRV_H - -/** - * @brief MIPI_CSI_PHY APIs - * @defgroup mipi_csi_phy_interface MIPI_CSI_PHY driver APIs - * @ingroup mipi_csi_phy_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_mipi_csi_phy_regs.h" - - -typedef struct mipi_csi_phy_clane_config { - uint16_t t_term_en_ns; /* !< unit: nanosecond. Time for the Clock Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX */ - uint16_t t_settle_ns; /* !< unit: nanosecond. Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of TCLK-PREPARE */ -} mipi_csi_phy_clane_config_t; - -typedef struct mipi_csi_phy_dlane_config { - uint16_t t_term_en_ns; /* !< unit: nanosecond. Time for the Data Lane receiver to enable the HS line termination, starting from the time point when Dn crosses VIL,MAX */ - uint16_t t_settle_ns; /* !< unit: nanosecond. Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of THS-PREPARE */ -} mipi_csi_phy_dlane_config_t; - -typedef struct mipi_csi_phy_config { - mipi_csi_phy_clane_config_t clane_cfg; /*!< clk lane config */ - mipi_csi_phy_dlane_config_t dlane_cfg; /*!< data lane config */ -} mipi_csi_phy_config_t; - - - -/** - * @brief get MIPI CSI PHY of default config - * - * @param[out] cfg config of MIPI CSI PHY - */ -void mipi_csi_phy_default_config(mipi_csi_phy_config_t *cfg); - -/** - * @brief MIPI_CSI_PHY init - * - * @param ptr MIPI_CSI_PHY base address - * @param cfg config of MIPI_CSI_PHY - */ -void mipi_csi_phy_init(MIPI_CSI_PHY_Type *ptr, mipi_csi_phy_config_t *cfg); - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_MIPI_CSI_PHY_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_drv.h deleted file mode 100644 index 6060aa45718..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_drv.h +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MIPI_DSI_DRV_H -#define HPM_MIPI_DSI_DRV_H - -/** - * @brief MIPI_DSI APIs - * @defgroup mipi_dsi_interface MIPI_DSI driver APIs - * @ingroup mipi_dsi_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_mipi_dsi_regs.h" - - -/* MIPI DSI Processor-to-Peripheral transaction types */ -typedef enum mipi_dsi_tx_cmd { - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - MIPI_DSI_DCS_READ = 0x06, - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39 -} mipi_dsi_tx_cmd_t; - -/* MIPI DCS commands */ -typedef enum mipi_dcs_cmd { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ - MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ - MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */ - MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */ - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -} mipi_dcs_cmd_t; - -typedef enum mipi_dsi_pixel_format { - MIPI_DSI_FMT_RGB888, - MIPI_DSI_FMT_RGB666, - MIPI_DSI_FMT_RGB666_PACKED, - MIPI_DSI_FMT_RGB565, -} mipi_dsi_pixel_format_t; - -typedef enum mipi_dsi_video_mode { - MIPI_DSI_VIDEO_MODE_SYNC_PULSE = 0x00, - MIPI_DSI_VIDEO_MODE_SYNC_EVENT = 0x01, - MIPI_DSI_VIDEO_MODE_BURST = 0x02, -} mipi_dsi_video_mode_t; - -/** - * mipi_dsi_msg_t - read/write DSI buffer - */ -typedef struct mipi_dsi_msg { - uint8_t channel; /*!< virtual channel id */ - uint8_t type; /*!< payload data type */ - uint16_t tx_len; /*!< length of tx_buf */ - const void *tx_buf; /*!< data to be written */ - uint16_t rx_len; /*!< length of rx_buf */ - void *rx_buf; /*!< data to be read, or NULL */ -} mipi_dsi_msg_t; - -typedef struct mipi_video_para { - uint32_t pixel_clock_khz; - uint32_t hactive; /*!< hor. active video */ - uint32_t hfront_porch; /*!< hor. front porch */ - uint32_t hback_porch; /*!< hor. back porch */ - uint32_t hsync_len; /*!< hor. sync len */ - - uint32_t vactive; /*!< ver. active video */ - uint32_t vfront_porch; /*!< ver. front porch */ - uint32_t vback_porch; /*!< ver. back porch */ - uint32_t vsync_len; /*!< ver. sync len */ -} mipi_video_para_t; - -typedef struct mipi_dsi_config { - uint32_t lane_mbps; - uint8_t channel; - uint8_t lanes; - bool disable_eotp; - mipi_dsi_pixel_format_t pixel_format; - mipi_video_para_t video_para; - mipi_dsi_video_mode_t video_mode; -} mipi_dsi_config_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief get MIPI_DSI default config on video mode - * - * @param cfg: MIPI_DSI default config - */ -void mipi_dsi_get_defconfig_on_video(mipi_dsi_config_t *cfg); - -/** - * @brief MIPI_DSI init - * - * @param ptr MIPI_DSI base address - * @param cfg config of MIPI_DSI - */ -void mipi_dsi_init(MIPI_DSI_Type *ptr, mipi_dsi_config_t *cfg); - -/** - * @brief MIPI_DSI phy interface power on - * - * @param ptr MIPI_DSI base address - */ -void mipi_dsi_phy_poweron(MIPI_DSI_Type *ptr); - -/** - * @brief MIPI_DSI phy interface power down - * - * @param ptr MIPI_DSI base address - */ -void mipi_dsi_phy_powerdown(MIPI_DSI_Type *ptr); - -/** - * @brief MIPI_DSI hs transfer start - * - * @param ptr MIPI_DSI base address - */ -void mipi_dsi_video_mode_hs_transfer_enable(MIPI_DSI_Type *ptr); - -/** - * @brief MIPI_DSI hs transfer stop - * - * @param ptr MIPI_DSI base address - */ -void mipi_dsi_video_mode_hs_transfer_disable(MIPI_DSI_Type *ptr); - -/** - * @brief transmit data using mipi dsi message in low power mode - * - * @param ptr MIPI_DSI base address - * @param msg MPI_DSI message - * - * @return The number of bytes transmitted on success or a negative error code - * on failure. - */ -int mipi_dsi_lp_cmd_transfer(MIPI_DSI_Type *ptr, const mipi_dsi_msg_t *msg); - -/** - * @brief specify the maximum size of the - * the payload in a long packet transmitted from the peripheral back to the - * host processor - * - * @param ptr: MIPI_DSI base address - * @param channel: virtual channel - * @param value: the maximum size of the payload - * - * @return: true on success or false on failure. - */ -int mipi_dsi_set_maximum_return_packet_size(MIPI_DSI_Type *ptr, uint8_t channel, uint16_t value); - -/** - * @brief transmit data using a generic write packet - * - * @param ptr: MIPI_DSI base address - * @param channel: virtual channel - * @param payload: buffer containing the payload - * @param size: size of payload buffer - * - * This function will automatically choose the right data type depending on - * the payload length. - * - * @return: The number of bytes transmitted on success or a negative error code - * on failure. - */ -int mipi_dsi_generic_write(MIPI_DSI_Type *ptr, uint8_t channel, const void *payload, - uint16_t size); - -/** - * @brief receive data using a generic read packet - * - * @param ptr: MIPI_DSI base address - * @param channel: virtual channel - * @param params: buffer containing the request parameters - * @param num_params: number of request parameters - * @param data: buffer in which to return the received data - * @param size: size of receive buffer - * - * This function will automatically choose the right data type depending on - * the number of parameters passed in. - * - * @return: The number of bytes successfully read or a negative error code on - * failure. - */ -int mipi_dsi_generic_read(MIPI_DSI_Type *ptr, uint8_t channel, const void *params, - uint16_t num_params, void *data, uint16_t size); - -/** - * @brief transmit a DCS command with payload - * - * @param ptr: MIPI_DSI base address - * @param channel: virtual channel - * @param data: buffer containing data to be transmitted - * @param len: size of transmission buffer - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * @return: The number of bytes successfully transmitted or a negative error - * code on failure. - */ -int mipi_dsi_dcs_write_buffer(MIPI_DSI_Type *ptr, uint8_t channel, - const void *data, uint16_t len); - -/** - * @brief send DCS write command - * - * @param ptr: MIPI_DSI base address - * @param channel: virtual channel - * @param cmd: DCS command - * @param data: buffer containing the command payload - * @param len: command payload length - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * @return: The number of bytes successfully transmitted or a negative error - * code on failure. - */ -int mipi_dsi_dcs_write(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, - const void *data, uint16_t len); - -/** - * @brief send DCS read request command - * - * @param ptr: MIPI_DSI base address - * @param channel: virtual channel - * @param cmd: DCS command - * @param data: buffer in which to receive data - * @param len: size of receive buffer - * - * @return: The number of bytes read or a negative error code on failure. - */ -int mipi_dsi_dcs_read(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, void *data, uint16_t len); - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_MIPI_DSI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_phy_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_phy_drv.h deleted file mode 100644 index 0cc0038ca83..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mipi_dsi_phy_drv.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MIPI_DSI_PHY_DRV_H -#define HPM_MIPI_DSI_PHY_DRV_H - -/** - * @brief MIPI_DSI_PHY APIs - * @defgroup mipi_dsi_phy_interface MIPI_DSI_PHY driver APIs - * @ingroup mipi_dsi_phy_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_mipi_dsi_phy_regs.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct mipi_dsi_phy_config { - uint32_t lane_mbps; /*!< lane speed */ - uint8_t lanes; /*!< number of lane */ -} mipi_dsi_phy_config_t; - -/** - * @brief MIPI_DSI_PHY init - * - * @param ptr MIPI_DSI_PHY base address - * @param cfg config of MIPI_DSI_PHY - */ -void mipi_dsi_phy_init(MIPI_DSI_PHY_Type *ptr, mipi_dsi_phy_config_t *cfg); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_MIPI_DSI_PHY_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h deleted file mode 100644 index aec551480e3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mmc_drv.h +++ /dev/null @@ -1,611 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MMC_DRV_H -#define HPM_MMC_DRV_H - -#include "hpm_common.h" -#include "hpm_mmc_regs.h" -/** - * @brief MMC driver APIs - * @defgroup mmc_interface MMC driver APIs - * @ingroup mmc_interfaces - * @{ - */ - -/* trigger source to update position parameter */ -typedef enum { - mmc_pos_update_by_timestamp = 0, - mmc_pos_update_by_intrgr0_rise_edge = 1, - mmc_pos_update_by_intrgr1_rise_edge = 2, - mmc_pos_update_by_outtrgr0_rise_edge = 3, - mmc_pos_update_by_outtrgr1_rise_edge = 4, - mmc_pos_update_by_self_pos_thr = 5, - mmc_pos_update_by_self_speed_thr = 6, -} mmc_pos_update_trigger_t; - - -/* cmd mask to update position parameter */ -typedef enum { - mmc_pos_update_none = 0, - mmc_pos_update_position = 1 << 0, - mmc_pos_update_revolution = 1 << 1, - mmc_pos_update_speed = 1 << 2, - mmc_pos_update_accel = 1 << 3, - mmc_pos_update_all = 0b1111, -} mmc_pos_update_cmd_mask_t; - -typedef enum { - mmc_coef_not_update = 0, - mmc_coef_p_update = 1 << 0, - mmc_coef_i_update = 1 << 1, - mmc_coef_a_update = 1 << 2, - mmc_coef_update_all = 0b111, -} mmc_coef_update_cmd_mask_t; - -typedef struct { - bool discrete_pos_mode; - uint32_t discrete_line; - uint32_t continuous_step_thr; - uint32_t continuous_circ_thr; - uint32_t oosync_theta_thr; -} mmc_track_pos_mode_t; - -typedef struct { - bool force_accel_to_zero; - bool en_ms_coef; - bool open_loop_mode; - bool pos_16bit_type; /* true for output 16bit position, false for output 32bit position */ - bool sync_new_pos; /* predictor base new track position data */ - mmc_track_pos_mode_t pos_mode; -} mmc_track_mode_t; - -typedef struct { - uint32_t pos_time; - uint32_t position; - int32_t revolution; - double speed; - double accel; - uint32_t cmd_mask; /*!< cmd to to select which parameters to update */ - uint32_t trigger; /*!< trigger source for when to update parameters */ -} mmc_pos_or_delta_pos_input_t; - -typedef struct { - uint32_t coef_time; - double coef_p; - double coef_i; - double coef_a; - uint32_t cmd_mask; /* cmd to select change which parameter */ -} mmc_coef_input_t; - -typedef struct { - uint32_t err_thr; - uint32_t hold_time; - double coef_p; - double coef_i; - double coef_a; -} mmc_coef_trig_config_t; - -typedef struct { - uint32_t time; - uint32_t position; - int32_t revolution; - double speed; - double accel; -} mmc_pos_out_t; - -typedef struct { - double coef_p; - double coef_i; - double coef_a; -} mmc_coef_out_t; - -/* track event, definition align with interrupt mask and status mask */ -typedef enum { - mmc_track_shadow_read_done = 1 << 0, - mmc_track_init_coefs_done = 1 << 1, - mmc_track_init_pos_done = 1 << 2, - mmc_track_oosync = 1 << 4, - mmc_track_idle = 1 << 5, /*!< no corresponding interrupt */ - mmc_pred1_init_pos_done = 1 << 6, - mmc_pred0_init_pos_done = 1 << 7, - mmc_track_init_delta_pos_done = 1 << 8, - mmc_track_pos_trig_valid = 1 << 9, - mmc_track_speed_trig_valid = 1 << 10, -} mmc_track_event_t; - -typedef enum { - mmc_pred_idle = MMC_BR_BR_ST_IDLE_MASK, - mmc_pred_init_delta_pos_done = MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK, - mmc_pred_pos_trig_valid = MMC_BR_BR_ST_POS_TRG_VLD_MASK, - mmc_pred_speed_trig_valid = MMC_BR_BR_ST_SPEED_TRG_VLD_MASK, - mmc_pred_open_loop = MMC_BR_BR_ST_OPEN_LOOP_ST_MASK, -} mmc_pred_event_t; - -typedef enum { - mmc_pred_pos_trig_valid_int = MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK, - mmc_pred_speed_trig_valid_int = MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK, - mmc_pred_init_delta_pos_done_int = MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK -} mmc_pred_int_t; - -typedef struct { - bool speed_trig_int; - bool position_trig_int; - bool delta_pos_done_trig_int; - bool open_loop_mode; - uint8_t pred_mode; - uint8_t not_first_pred_trig_type; - uint8_t first_pred_trig_type; -} mmc_pred_mode_t; - -typedef enum { - mmc_pred_not_reload_pos_cmd = 0, - mmc_pred_0_reload_pos_cmd = 2, - mmc_pred_1_reload_pos_cmd = 1, - mmc_pred_both_reload_pos_cmd = 3, -} mmc_pred_reload_pos_cmd_t; - -typedef enum { - mmc_pred_by_period = 0, - mmc_pred_continuously_repeat = 1, - mmc_pred_only_once = 2, -} mmc_pred_time_t; - -/* using for mmc_pred_by_period mode */ -typedef struct { - uint32_t offset_time; - uint32_t period_time; - uint32_t first_time; -} mmc_pred_period_time_t; - -typedef struct { - bool less_than; /*!< true for less than, false for greater than */ - bool enable; - uint32_t position_thr; /*!< position in a cycle */ - int32_t revolution_thr; /*!< cycle */ -} mmc_pos_trig_t; - -typedef struct { - bool absolute_compare; /*!< true for absolute value compare, false for signed value compare */ - bool less_than; /*!< true for less than, false for greater than */ - bool enable; - int32_t speed_thr; -} mmc_speed_trig_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief MMC set frequency - * @param [in] base MMC base address - * @param [in] freq the moto system freq - */ -static inline void mmc_set_sysclk_freq(MMC_Type *base, uint32_t freq) -{ - uint32_t period; - base->SYSCLK_FREQ = freq; - /* 1/freq *(2^24)*(2^20) */ - period = (uint32_t)((double)(1 << 20) * (1 << 24) / freq); - base->SYSCLK_PERIOD = period; -} - -/** - * @brief MMC software reset - * @param [in] base MMC base address - */ -static inline void mmc_software_reset(MMC_Type *base) -{ - base->CR |= MMC_CR_SFTRST_MASK; - base->CR &= ~MMC_CR_SFTRST_MASK; -} - -/** - * @brief MMC module enable - * @param [in] base MMC base address - */ -static inline void mmc_enable_module(MMC_Type *base) -{ - base->CR |= MMC_CR_MOD_EN_MASK; -} - -/** - * @brief MMC module disable - * @param [in] base MMC base address - */ -static inline void mmc_disable_module(MMC_Type *base) -{ - base->CR &= ~MMC_CR_MOD_EN_MASK; -} - -/** - * @brief MMC track set loop mode - * @param [in] base MMC base address - * @param [in] open_loop true for open loop, false for close loop - */ -static inline void mmc_track_set_open_loop_mode(MMC_Type *base, bool open_loop) -{ - if (open_loop) { - base->CR |= MMC_CR_OPEN_LOOP_MODE_MASK; - } else { - base->CR &= ~MMC_CR_OPEN_LOOP_MODE_MASK; - } -} - -/** - * @brief MMC track set adjop mode - * @param [in] base MMC base address - * @param [in] adjop true for adjop mode, false for normal mode - */ -static inline void mmc_track_set_adjop_mode(MMC_Type *base, bool adjop) -{ - if (adjop) { - base->CR |= MMC_CR_ADJOP_MASK; - } else { - base->CR &= ~MMC_CR_ADJOP_MASK; - } -} - -/** - * @brief MMC track request shadow read - * @param [in] base MMC base address - * - * @note request shadow before read mmc track resoult register - */ -static inline void mmc_track_enable_shadow_read(MMC_Type *base) -{ - base->CR |= MMC_CR_SHADOW_RD_REQ_MASK; - /* SHADOW_RD_REQ clear indicates that the shadow is complete */ - while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) { - } -} - -/** - * @brief MMC track enable interrupt - * @param [in] base MMC base address - * @param [in] int_mask interrupt_mask @ref mmc_track_event_t - */ -static inline void mmc_track_enable_interrupt(MMC_Type *base, uint32_t int_mask) -{ - base->INT_EN = int_mask; -} - -/** - * @brief MMC track disable interrupt - * @param [in] base MMC base address - * @param [in] int_mask interrupt_mask @ref mmc_track_event_t - */ -static inline void mmc_track_disable_interrupt(MMC_Type *base, uint32_t int_mask) -{ - base->INT_EN &= ~int_mask; -} - -/** - * @brief MMC track get status register value - * @param [in] base MMC base address - * @retval status register value - */ -static inline uint32_t mmc_track_get_status(MMC_Type *base) -{ - return base->STA; -} - -/** - * @brief MMC track clear status flag in status register - * @param [in] base MMC base address - * @param [in] clr_mask @ref mmc_track_event_t - */ -static inline void mmc_track_clear_status(MMC_Type *base, uint32_t clr_mask) -{ - base->STA = clr_mask; /* W1C */ -} - -/** - * @brief MMC track set the threshold of theta for out-of-sync - * @param [in] base MMC base address - * @param [in] threshold threshold value - */ -static inline void mmc_track_set_oosync_theta_threshold(MMC_Type *base, uint32_t threshold) -{ - base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(threshold); -} - -/** - * @brief MMC track config position mode - * @param [in] base MMC base address - * @param [in] mode mmc_track_pos_mode_t - */ -void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode); - -/** - * @brief MMC track get default mode config - * @param [in] base MMC base address - * @param [in] config mmc_track_mode_t - */ -void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config); - -/** - * @brief MMC track config mode - * @param [in] base MMC base address - * @param [in] config mmc_track_mode_t - */ -void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config); - -/** - * @brief MMC track config position parameter - * @param [in] base MMC base address - * @param [in] para mmc_pos_or_delta_pos_input_t - */ -void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); - -/** - * @brief MMC track config delta parameter - * @param [in] base MMC base address - * @param [in] para mmc_pos_or_delta_pos_input_t - */ -void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); - -/** - * @brief MMC track config coef parameter - * @param [in] base MMC base address - * @param [in] para mmc_coef_input_t - */ -void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para); - -/** - * @brief MMC track config position trigger - * @param [in] base MMC base address - * @param [in] trig mmc_pos_trig_t - */ -void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig); - -/** - * @brief MMC track config speed trigger - * @param [in] base MMC base address - * @param [in] trig mmc_speed_trig_t - */ -void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig); - -/** - * @brief MMC track disable position trigger - * @param [in] base MMC base address - */ -static inline void mmc_track_disable_position_trig(MMC_Type *base) -{ - base->POS_TRG_CFG &= ~MMC_POS_TRG_CFG_EN_MASK; -} - -/** - * @brief MMC track disable speed trigger - * @param [in] base MMC base address - */ -static inline void mmc_track_disable_speed_trig(MMC_Type *base) -{ - base->SPEED_TRG_CFG &= ~MMC_SPEED_TRG_CFG_EN_MASK; -} - -/** - * @brief MMC track config multiple coef trigger - * @param [in] base MMC base address - * @param [in] index coef trigger index(0/1/2) - * @param [in] config mmc_coef_trig_config_t - */ -void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config); - -/** - * @brief MMC track get result - * @param [in] base MMC base address - * @param [out] pos_out mmc_pos_out_t - * @param [out] coef_out mmc_coef_out_t - */ -void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out); - -/* predictor */ -/** - * @brief MMC enable predictor - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - */ -static inline void mmc_enable_pred(MMC_Type *base, uint8_t index) -{ - base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_BR_EN_MASK; -} - -/** - * @brief MMC disable predictor - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - */ -static inline void mmc_disable_pred(MMC_Type *base, uint8_t index) -{ - base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_BR_EN_MASK; -} - -/** - * @brief MMC predictor set loop mode - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] open_loop true for open loop, false for close loop - */ -static inline void mmc_pred_set_open_loop_mode(MMC_Type *base, uint8_t index, bool open_loop) -{ - if (open_loop) { - base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK; - } else { - base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK; - } -} - -/** - * @brief MMC predictor set pred time - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] time mmc_pred_time_t - */ -static inline void mmc_pred_set_pred_time(MMC_Type *base, uint8_t index, mmc_pred_time_t time) -{ - base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_PRED_MODE_MASK; - base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_PRED_MODE_SET(time); -} - -/** - * @brief MMC pred enable interrupt - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] int_mask interrupt_mask @ref mmc_pred_int_t - */ -static inline void mmc_pred_enable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask) -{ - base->BR[index].BR_CTRL |= int_mask; -} - -/** - * @brief MMC pred disable interrupt - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] int_mask interrupt_mask @ref mmc_pred_int_t - */ -static inline void mmc_pred_disable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask) -{ - base->BR[index].BR_CTRL &= ~int_mask; -} - -/** - * @brief MMC predictor get status register value - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @retval predictor status register value - */ -static inline uint32_t mmc_pred_get_status(MMC_Type *base, uint8_t index) -{ - return base->BR[index].BR_ST; -} - -/** - * @brief MMC predictor clear status bit in reigster - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] clr_mask bit mask @ref mmc_pred_event_t - */ -static inline void mmc_pred_clear_status(MMC_Type *base, uint8_t index, uint32_t clr_mask) -{ - base->BR[index].BR_ST = clr_mask; /*!< W1C */ -} - -/** - * @brief MMC predictor get default mode config - * @param [in] base MMC base address - * @param [in] config mmc_pred_mode_t - */ -void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config); - -/** - * @brief MMC predictor config mode - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] config mmc_pred_mode_t - */ -void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config); - -/** - * @brief MMC predictor config position parameter - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] para mmc_pos_or_delta_pos_input_t - * @param [in] req_reload request to update parameter cmd - * - * @note 2 predictors can be set simultaneously by call mmc_pred_reload_pos_cmd() - */ -void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload); - -/** - * @brief MMC predictor reload position parameter cmd - * @param [in] base MMC base address - * @param [in] cmd mmc_pred_reload_pos_cmd_t - */ -static inline void mmc_pred_reload_pos_cmd(MMC_Type *base, mmc_pred_reload_pos_cmd_t cmd) -{ - base->CR &= ~(MMC_CR_INI_BR0_POS_REQ_MASK | MMC_CR_INI_BR0_POS_REQ_MASK); - base->CR |= cmd << MMC_CR_INI_BR1_POS_REQ_SHIFT; -} - -/** - * @brief MMC predictor update delta parameter - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] para mmc_pos_or_delta_pos_input_t - */ -void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para); - -/** - * @brief MMC predictor config period time - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] time mmc_pred_period_time_t - */ -void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time); - -/** - * @brief MMC predictor config position trigger - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] trig mmc_pos_trig_t - */ -void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig); - -/** - * @brief MMC predictor config speed trigger - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [in] trig mmc_speed_trig_t - */ -void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig); - -/** - * @brief MMC predictor disable position trigger - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - */ -static inline void mmc_pred_disable_position_trig(MMC_Type *base, uint8_t index) -{ - base->BR[index].BR_TRG_POS_CFG &= ~MMC_BR_BR_TRG_POS_CFG_EN_MASK; -} - -/** - * @brief MMC predictor disable speed trigger - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - */ -static inline void mmc_pred_disable_speed_trig(MMC_Type *base, uint8_t index) -{ - base->BR[index].BR_TRG_SPEED_CFG &= ~MMC_BR_BR_TRG_SPEED_CFG_EN_MASK; -} - -/** - * @brief MMC predictor get result - * @param [in] base MMC base address - * @param [in] index predictor index(0/1) - * @param [out] pos_out mmc_pos_out_t - */ -void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out); - -/** - * @brief MMC predictor get result - * @param [in] base MMC base address - * @param [out] para mmc_pos_or_delta_pos_input_t - */ -void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_MMC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h deleted file mode 100644 index e711dcfb5bd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mono_drv.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MONO_DRV_H -#define HPM_MONO_DRV_H - -#include "hpm_common.h" -#include "hpm_mono_regs.h" - -/** - * - * @brief MONO driver APIs - * @defgroup mono_interface MONO driver APIs - * @ingroup io_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get counter - * - * @param[in] ptr MONO base address - * - * @return 64 bits counter value - */ -static inline uint64_t mono_get_counter(MONO_Type *ptr) -{ - return (uint64_t)((uint64_t)((ptr->MONOH) << 32)) - | (uint64_t)((ptr->MONOL)); -} - -/** - * @brief Update MONO counter by 1 - * - * @param[in] ptr MONO base - */ -static inline void mono_update(MONO_Type *ptr) -{ - ptr->MONOL = 1; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_MONO_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mtg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mtg_drv.h deleted file mode 100644 index 01450676f7c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mtg_drv.h +++ /dev/null @@ -1,726 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MMC_DRV_H -#define HPM_MMC_DRV_H - -#include "hpm_common.h" -#include "hpm_mtg_regs.h" -/** - * @brief MTG driver APIs - * @defgroup mtg_interface MTG driver APIs - * @ingroup motor_interfaces - * @{ - */ - -/** - * @brief define the struct of mtg lock values - * - */ -typedef struct mtg_result { - int32_t rev; /* revolution */ - uint32_t pos; /* postion */ - int32_t vel; /* velocity */ - int32_t acc; /* acceleration */ - uint32_t time_stamp; /* time stamp */ -} mtg_lock_value_t; - -/** - * @brief define the enum of the postion of the observed object - */ -typedef enum mtg_evnet_object_postion { - event_source_before_filter = 1 << 0, /* before filter, also treat as input of mtg */ - event_source_filter_output = 1 << 1, /* after filter, also treat as input of mtg's time compensation module */ - event_source_tra0_output = 1 << 2, /* output of mtg's trajectory predictor0 */ - event_source_tra1_output = 1 << 3, /* output of mtg's trajectory predictor1 */ -} mtg_evnet_object_postion_t; - -/** - * @brief define the enum of the observed object - */ -typedef enum mtg_event_object { - event_object_rev_pos = 1, /* location, revolution and position */ - event_object_vel = 2, /* velocity */ - event_object_acc = 4, /* acceleration */ - event_object_pos = 8, /* postion, ignore revolution */ -} mtg_event_object_t; - -/** - * @brief define the enum of the event detection mode - */ -typedef enum mtg_event_mode { - event_mode_across = 1, /* across mode, change from greater than to less than, or opposite */ - event_mode_hold = 2, /* hold mode, maintain within a range for a period of time */ - event_mode_over_protect = 4, /* over protect mode, greater than or less than */ - event_mode_time_match = 8, /* time match mode, when the synt's cnt value is equal to the preset */ -} mtg_event_mode_t; - -/** - * @brief define the enum of the event detection direction - */ -typedef enum mtg_event_dir { - event_dir_negative = 0, - event_dir_positive = 1, - event_dir_both = 2, -} mtg_event_dir_t; - -/** - * @brief define the enum of the event detection direction calculation mode - */ -typedef enum mtg_event_dir_mode { - event_dir_mode_dy = 0, /* use first derivative of object */ - event_dir_mode_y1_y0 = 1, /* use difference of current and previous */ -} mtg_event_dir_mode_t; - -/** - * @brief define the enum of the event detection over protect mode - */ -typedef enum mtg_event_over_mode_cmp { - event_over_cmp_mode_smaller = 0, - event_over_cmp_mode_bigger = 1, -} mtg_event_over_mode_cmp_t; - -/** - * @brief define the enum of the event trigger number - */ -typedef enum mtg_event_trig_num { - event_trig_once = 0, /* event can only be triggered once */ - event_trig_repeat = 1, /* event can be triggered multiple times */ -} mtg_event_trig_num_t; - -/** - * @brief define the struct of the event setup parameter - */ -typedef struct mtg_event_param { - bool enable; - bool irq_en; /* enable or disable the event irq */ - mtg_event_object_t obj; - mtg_evnet_object_postion_t obj_postion; - mtg_event_mode_t mode; - mtg_event_dir_t dir; - mtg_event_dir_mode_t dir_mode; - mtg_event_over_mode_cmp_t cmp_mode; - mtg_event_trig_num_t trig_num; - - /* union struct of event presets registers, different meaning when different event mode */ - union { - struct { - uint32_t cross_value_h; /* the high 32bit of cross_value, only need set when object is ${event_object_rev_pos} */ - uint32_t cross_value_l; /* the low 32bit of cross_value */ - } cross_param; - struct { - uint32_t hold_value_h; /* the high 32bit of hold_value, only need set when object is ${event_object_rev_pos} */ - uint32_t hold_value_l; /* the low 32bit of hold_value */ - uint32_t error_limit; /* the range is between ${hold value - error_limit} and ${hold value + error_limit} */ - uint32_t hold_clock_cnt; /* the event will be triggered when match the hold value and error_limit and last for &{hold_clock_cnt} clocks */ - } hold_param; - struct { - uint32_t limit_value_h; /* the high 32bit of limit_value */ - uint32_t limit_value_l; /* the low 32bit of limit_value */ - } over_protect_param; - struct { - uint32_t clock_count; /* the event will be triggered when synt clock match the value */ - } time_param; - uint32_t preset[4]; - } preset; -} mtg_event_param_t; - -/* - * @brief define the struct of the trajectory predictor limit - */ -typedef struct mtg_tra_limit_param { - bool vel_step_limit_en; /* velocity step limit enable, when enable, the velocity variation per clock will be limited by vel_step_max and vel_step_min */ - uint32_t vel_step_max; /* velocity step limit value max */ - uint32_t vel_step_min; /* velocity step limit value min */ - bool pos_step_limit_en; /* postion step limit enable, when enable, the postion variation per clock will be limited by pos_step_max and pos_step_min */ - uint32_t pos_step_max; /* postion step limit value max */ - uint32_t pos_step_min; /* postion step limit value min */ -} mtg_tra_limit_param_t; - -/** - * @brief define the enum of the software force one way mode - */ -typedef enum mtg_software_force_one_way_mode { - sw_force_negative = 0, - sw_force_positive = 1, -} mtg_software_force_one_way_mode_t; - -/** - * @brief define the enum of the hardware force one way mode - */ -typedef enum vel_one_way_mode { - bigger_or_eq_zero = 0, - smaller_or_eq_zero = 1, -} vel_one_way_mode_t; - -/** - * @brief define the struct of the hardware force one way mode - */ -typedef struct mtg_hardware_force_one_way_mode { - uint32_t vel_limit_p; - uint32_t vel_limit_n; -} mtg_hardware_force_one_way_mode_t; - -/** - * @brief define the enum of the filter initialization mode - */ -typedef enum mtg_filter_rev_init_mode { - rev_init_mode_from_first_input_value = 0, /* the first input value will be used by the mtg filter to initialize the filter */ - rev_init_mode_from_register = 1, /* the value in the register will be used by the mtg filter to initialize the filter */ -} mtg_filter_rev_init_mode_t; - -/** - * @brief define the enum of the filter judge mode - * It affects the judgment conditions for changes in the number of revolution - */ -typedef enum mtg_filter_rev_judge_mode { - mtg_rev_judge_mode_new_sub_old = 0, - mtg_rev_judge_mode_encoder_lines = 1, -} mtg_filter_rev_judge_mode_t; - -/** - * @brief define the enum of the filter ff mode - */ -typedef enum mtg_filter_ff_mode { - mtg_filter_ff_mode_from_register = 0, - mtg_filter_ff_mode_from_input = 1, -} mtg_filter_ff_mode_t; - -typedef struct mtg_filter_param { - bool enable; /* filter enable */ - bool ff_en; /* filter feedforward enable */ - bool init_en; /* filter first value initialization enable */ - bool err_bypass_en; /* filter error bypass enable. when difference between filter input and output beyond the limit, filter output will be bypassed */ - bool err_init; /* filter error reset enable. when difference between filter input and output beyond the limit, the filter will reset */ - bool timeout_en; /* filter timeout enable */ - bool err_bypass_i_f_en; - bool err_bypass_f_i_en; - bool multi_err_irq_en; - bool acceleration_en; /* filter acceleration enable. when enable, the filter will output acceleration value */ - mtg_filter_rev_init_mode_t rev_ini_mode; - mtg_filter_rev_judge_mode_t rev_judge_mode; - mtg_filter_ff_mode_t ff_mode; - int32_t rev_init_value; /* the initial value of revolution. only used when init_en == true */ - int32_t vel_init_value; /* the initial value of velocity. only used when init_en == true */ - int32_t acc_init_value; /* the initial value of acceleration. only used when init_en == true */ - uint32_t pos_init_value; /* the initial value of postion. only used when init_en == true */ - uint32_t filter_mot_sel; - uint32_t filter_stage_sel; - uint32_t filter_time_constant_tp; - uint32_t filter_time_constant_tz; - uint32_t filter_time_constant_tz_1; - uint32_t filter_zero_tz_sel; - uint32_t filter_gain; - uint32_t filter_stage_shift[2]; - uint32_t filter_param_shift; - uint32_t filter_time_shift; - uint32_t filter_ff_shift; - uint32_t filter_error_limit_l; - uint32_t filter_error_limit_h; -} mtg_filter_param_t; - -/** - * @brief define the enum of the trajectory predictor time input source - */ -typedef enum mtg_time_input_source { - mtg_time_input_from_filter = 1, /* the value in the filter will be used */ - mtg_time_input_from_input = 2, /* the value in the input will be used */ -} mtg_time_input_source_t; - -/** - * @brief define the struct of the trajectory predictor time initialization - */ -typedef struct mtg_time_init_param { - bool enable; - uint32_t adjust_value; /* time compensation clocks */ - uint8_t index; - mtg_time_input_source_t source; -} mtg_time_init_param_t; - -/** - * @brief define the struct of the trajectory predictor timeout - */ -typedef struct mtg_timeout_param { - bool enable; - uint32_t timeout_clock_count; -} mtg_timeout_param_t; - -/** - * @brief define the enum of the trajectory predictor link event - * link the trigger source and the cmd object, it describes the - * trigger source - */ -typedef enum mtg_link_cfg { - link_event0 = 0, - link_event1 = 1, - link_event2 = 2, - link_event3 = 3, - link_hw_trigger = 4, - link_sw_trigger = 5, - link_event_timeout = 6, -} mtg_link_cfg_t; - -/** - * @brief define the enum of the trajectory predictor command object - */ -typedef enum { - cmd_object_rev = 1 << 0, - cmd_object_pos = 1 << 1, - cmd_object_vel = 1 << 2, - cmd_object_acc = 1 << 3, - cmd_object_jer = 1 << 4, -} mtg_tra_cmd_object_t; - -/** - * @brief define the enum of the trajectory predictor command mode - */ -typedef enum { - cmd_mode_new_value = 0, /* when cmd exec, the preset value will replace the old value */ - cmd_mode_old_delta = 1, /* when cmd exec, the preset value will be added to the old value */ -} mtg_link_cmd_mode_t; - -/** - * @brief define the struct of the trajectory shift struct - */ -typedef struct mtg_tra_shift { - uint8_t jerk_shift; - uint8_t acc_shift; - uint8_t vel_shift; -} mtg_tra_shift_t; - -/** - * @brief define the struct of the trajectory predictor command - */ -typedef struct mtg_tra_cmd_cfg { - uint8_t index; - uint32_t object; /* cmd object, see ${mtg_tra_cmd_object_t} */ - mtg_link_cmd_mode_t mode; - uint32_t rev_preset; - uint32_t pos_preset; - uint32_t vel_preset; - uint32_t acc_preset; - uint32_t jer_preset; -} mtg_tra_cmd_cfg_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief MTG get trajectory predictor control register value - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - * @retval control register value - */ -static inline uint32_t mtg_get_tra_control_status(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - return base->TRA[tra_index].CONTROL; -} - -/** - * @brief MTG get trajectory predictor commond control register value - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - * @param [in] cmd_index - trajectory predicotr command index - * @retval control register value - */ -static inline uint32_t mtg_get_tra_cmd_control_status(MTG_Type *base, uint8_t tra_index, uint8_t cmd_index) -{ - assert((tra_index < 2) && (cmd_index < 4)); - return base->TRA[tra_index].CMD[cmd_index].CONTROL; -} - -/** - * @brief MTG trigger trajectory predictor lock current values - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - */ -static inline void mtg_trig_tra_lock(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - base->TRA[tra_index].CONTROL |= MTG_TRA_CONTROL_SW_LOCK_SET(1); -} - -/** - * @brief MTG clear trajectory predictor lock status - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - */ -static inline void mtg_clear_tra_lock(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - base->TRA[tra_index].CONTROL &= ~MTG_TRA_CONTROL_SW_LOCK_MASK; -} - -/** - * @brief MTG get trajectory predictor revolution lock value - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - * @retval trajectory predictor revolution value - */ -static inline int32_t mtg_get_tra_rev_lock_value(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - return base->TRA[tra_index].LOCK_REV; -} - -/** - * @brief MTG get trajectory predictor postion lock value - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - * @retval trajectory predictor postion value - */ -static inline uint32_t mtg_get_tra_pos_lock_value(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - return base->TRA[tra_index].LOCK_POS; -} - -/** - * @brief MTG get trajectory predictor velocity lock value - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - * @retval trajectory predictor velocity value - */ -static inline int32_t mtg_get_tra_vel_lock_value(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - return base->TRA[tra_index].LOCK_VEL; -} - -/** - * @brief MTG get trajectory predictor acceleration lock value - * @param [in] base - MTG base address - * @param [in] tra_index - trajectory predictor index - * @retval trajectory predictor acceleration value - */ -static inline int32_t mtg_get_tra_acc_lock_value(MTG_Type *base, uint8_t tra_index) -{ - assert(tra_index < 2); - return base->TRA[tra_index].LOCK_ACC; -} - -/** - * @brief MTG setup filter error bypass limit - * @param [in] base MTG base address - * @param [in] limit - bypass limit - */ -static inline void mtg_filter_set_err_bypass_limit(MTG_Type *base, uint32_t limit) -{ - base->FILTER_ERROR_LIMIT_H = limit; -} - -/** - * @brief MTG setup hardware switch from bypass status to filter status's limit - * When the difference between input and filter's pos result is smaller than the limit, - * the filter will use the filter's result inside of the input. - * @param [in] base MTG base address - * @param [in] param - filter params - */ -static inline void mtg_filter_set_bypass_switch_filter_limit(MTG_Type *base, uint32_t limit) -{ - base->FILTER_ERROR_LIMIT_L = limit; -} - -/** - * @brief MTG enable filter error bypass - * When difference between input and filter's pos result is bigger than the limit, - * the filter output will be bypass and input will be output to the filter's port. - * @param [in] base MTG base address - * @param [in] limit - bypass limit - */ -static inline void mtg_filter_enable_bypass(MTG_Type *base) -{ - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SET(1); - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_ERR_BYPASS_EN_SET(1); -} - -/** - * @brief MTG disable filter error bypass - * When difference between input and filter's pos result is bigger than the limit, - * the filter output will be bypass and input will be output to the filter's port. - * @param [in] base MTG base address - * @param [in] limit - bypass limit - */ -static inline void mtg_filter_disable_bypass(MTG_Type *base) -{ - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK; - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK; -} - -/** - * @brief MTG reset filter enable error reset - * @param [in] base MTG base address - */ -static inline void mtg_filter_enable_reset_init(MTG_Type *base) -{ - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_ERR_INI_SET(1); -} - -/** - * @brief MTG reset filter disable error reset - * @param [in] base MTG base address - */ -static inline void mtg_filter_disable_reset_init(MTG_Type *base) -{ - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_ERR_INI_MASK; -} - -/** - * @brief MTG enable hardware switch from bypass status to filter status's limit - * When the difference between input and filter's pos result is smaller than the limit, - * the filter will use the filter's result inside of the input. - * The switch result can be defined by reading the switch status register. - * @param [in] base MTG base address - * @param [in] param - filter params - */ -static inline void mtg_filter_switch_filter_result(MTG_Type *base) -{ - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SET(1); -} - -/** - * @brief MTG disable hardware switch from bypass status to filter status's limit - * When the difference between input and filter's pos result is smaller than the limit, - * the filter will use the filter's result inside of the input. - * The switch result can be defined by reading the switch status register. - * @param [in] base MTG base address - * @param [in] param - filter params - */ -static inline void mtg_filter_stop_auto_switch_filter_result(MTG_Type *base) -{ - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK; -} - -/** - * @brief MTG setup hardware switch from bypass status to filter status's limit - * When the difference between input and filter's pos result is smaller than the limit, - * the filter will use the filter's result inside of the input. - * @param [in] base - MTG base address - * @retval bypass status - */ -static inline bool mtg_get_err_bypass_status(MTG_Type *base) -{ - return MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_GET(base->FILTER_CONTROL) == 0 ? true : false; -} - -/** - * @brief MTG set time0 adjust value - * @param [in] base - MTG base address - * @param [in] value - adjust value - */ -static inline void mtg_set_time0_adjust_value(MTG_Type *base, uint32_t value) -{ - base->FILTER_TIME0_SW_ADJUST = value; -} - -/** - * @brief MTG set time1 adjust value - * @param [in] base - MTG base address - * @param [in] value - adjust value - */ -static inline void mtg_set_time1_adjust_value(MTG_Type *base, uint32_t value) -{ - base->FILTER_TIME1_SW_ADJUST = value; -} - -/** - * @brief MTG set time shift value - * @param [in] base - MTG base address - * @param [in] index - tra index - * @param [in] jer_shift - jerk shift - * @param [in] acc_shift - acceleration shift - * @param [in] vel_shift - velocity shift - */ -static inline void mtg_tra_set_shift(MTG_Type *base, uint8_t index, uint8_t jer_shift, uint8_t acc_shift, uint8_t vel_shift) -{ - assert(index < 2); - base->TRA[index].SHIFT = MTG_TRA_SHIFT_JER_SHIFT_SET(jer_shift) | - MTG_TRA_SHIFT_ACC_SHIFT_SET(acc_shift) | - MTG_TRA_SHIFT_VEL_SHIFT_SET(vel_shift); -} - -/** - * @brief MTG global reset - * @param [in] base - MTG base address - */ -static inline void mtg_set_global_reset(MTG_Type *base) -{ - base->SW_GLB_RESET = 1; -} - -/** - * @brief MTG stop global reset - */ -static inline void mtg_stop_global_reset(MTG_Type *base) -{ - base->SW_GLB_RESET = 0; -} - -/** - * @brief MTG predictor get lock result - * @param [in] base MTG base address - * @param [in] tra_index - trajectory predictor index - * @param [out] para mtg_lock_value_t - */ -void mtg_get_tra_lock_result(MTG_Type *base, uint8_t tra_index, mtg_lock_value_t *para); - -/** - * @brief MTG setup event params - * @param [in] base MTG base address - * @param [in] event_index - event index - * @param [in] param - event params - * @param [out] setup status - */ -hpm_stat_t mtg_setup_event(MTG_Type *base, uint8_t event_index, mtg_event_param_t *param); - -/** - * @brief MTG setup trajectory limit params - * @param [in] base MTG base address - * @param [in] tra_index - trajectory index - * @param [in] param - trajectory limit params - * @param [out] setup status - */ -hpm_stat_t mtg_setup_tra_limit(MTG_Type *base, uint8_t tra_index, mtg_tra_limit_param_t *param); - -/** - * @brief MTG setup trajectory software one_way mode - * @param [in] base MTG base address - * @param [in] tra_index - trajectory index - * @param [in] param - 0:force + , 1:force - - * @param [out] setup status - */ -void mtg_setup_tra_software_pos_one_way_mode(MTG_Type *base, uint8_t tra_index, mtg_software_force_one_way_mode_t param); - -/** - * @brief MTG setup trajectory hardware one_way mode - * @param [in] base MTG base address - * @param [in] tra_index - trajectory index - * @param [in] param - 0:force + , 1:force - - * @param [out] setup status - */ -void mtg_setup_tra_hardware_pos_one_way_mode(MTG_Type *base, uint8_t tra_index, mtg_hardware_force_one_way_mode_t *param); - -/** - * @brief MTG disable trajectory postion one_way mode - * @param [in] base MTG base address - * @param [in] tra_index - trajectory index - */ -void mtg_disable_tra_pos_one_way_mode(MTG_Type *base, uint8_t tra_index); - -/** - * @brief MTG setup trajectory velocity one_way mode - * @param [in] base MTG base address - * @param [in] tra_index - trajectory index - * @param [in] mode - 0:bigger_or_eq_zero , 1:smaller_or_eq_zero - */ -void mtg_setup_tra_vel_one_way(MTG_Type *base, uint8_t tra_index, vel_one_way_mode_t mode, bool enable); - -/** - * @brief MTG setup filter - * @param [in] base MTG base address - * @param [in] param - filter params - */ -void mtg_filter_get_default_filter_stage_param(mtg_filter_param_t *param); - -/** - * @brief MTG setup time compensation module - * @param [in] base MTG base address - * @param [in] param - time compensation params - */ -void mtg_setup_time(MTG_Type *base, mtg_time_init_param_t *param); - -/** - * @brief MTG setup filter - * @param [in] base MTG base address - * @param [in] param - filter params - */ -void mtg_setup_filter(MTG_Type *base, mtg_filter_param_t *param); - -/** - * @brief MTG setup timeout - * @param [in] base MTG base address - * @param [in] param - timeout params - */ -void mtg_setup_timeout(MTG_Type *base, mtg_timeout_param_t *param); - -/** - * @brief MTG link trigger source and trajectory command - * @param [in] base MTG base address - * @param [in] tra_index - trajectory index - * @param [in] link_cfg - link config - * @param [in] cmd_cfg - command config - */ -void mtg_setup_link_cfg(MTG_Type *base, uint8_t tra_index, mtg_link_cfg_t link_cfg, mtg_tra_cmd_cfg_t *cmd_cfg); - -/** - * @brief MTG software trigger trajectory command - * @param [in] base MTG base address - */ -void mtg_soft_event_trigger(MTG_Type *base); - -/** - * @brief Get default trajectory shift - * @param [out] cfg pointer to the tra shift var - */ -void mtg_get_default_tra_shift(mtg_tra_shift_t *cfg); - -/** - * @brief Get the event irq status - * @param [in] ptr the mtg base - * @param [in] idx the event index - */ -static inline bool mtg_get_irq_status(MTG_Type *ptr, uint8_t idx) -{ - return ((MTG_EVENT_CONTROL_EVENT_IRQ_GET(ptr->EVENT[idx].CONTROL) != 0) ? true : false); -} - -/** - * @brief Clear the event irq status - * @param [in] ptr the mtg base - * @param [in] idx the event index - */ -static inline void mtg_clear_irq_status(MTG_Type *ptr, uint8_t idx) -{ - ptr->EVENT[idx].CONTROL |= MTG_EVENT_CONTROL_EVENT_IRQ_MASK; -} - -/** - * @brief calculate the vel preset - * @param [in] base MTG base address - * @param [in] clock MTG clock name - * @param [in] tra_index - trajectory index - * @param [in] speed - speed in r/s - */ -int32_t mtg_calc_vel_preset(MTG_Type *base, clock_name_t clock, uint8_t tra_index, float speed); - -/** - * @brief calculate the acc preset - * @param [in] base MTG base address - * @param [in] clock MTG clock name - * @param [in] tra_index - trajectory index - * @param [in] acc - acc in r/s2 - */ -int32_t mtg_calc_acc_preset(MTG_Type *base, clock_name_t clock, uint8_t tra_index, float acc); - -/** - * @brief MTG link trigger source and trajectory command - * @param [in] base MTG base address - * @param [in] clock MTG clock name - * @param [in] tra_index - trajectory index - * @param [in] jer - jer in r/s3 - */ -int32_t mtg_calc_jer_preset(MTG_Type *base, clock_name_t clock, uint8_t tra_index, float jer); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_MTG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h deleted file mode 100644 index 329db9f02e5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_opamp_drv.h +++ /dev/null @@ -1,546 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_OPAMP_DRV_H -#define HPM_OPAMP_DRV_H - -#include "hpm_common.h" -#include "hpm_opamp_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief OPMAP driver APIs - * @defgroup opamp_interface OPAMP driver APIs - * @ingroup io_interfaces - * @{ - * - */ -#define OPAMP_MODE_FOLLOW_KEY (0x06) -#define OPAMP_MODE_INVERT_INDEX0_KEY (0x08) -#define OPAMP_MODE_INVERT_INDEX1_KEY (0x18) -#define OPAMP_MODE_NON_INVERT_INDEX0_KEY (0x01) -#define OPAMP_MODE_NON_INVERT_INDEX1_KEY (0x09) -#define OPAMP_MODE_NON_INVERT_INDEX2_KEY (0x11) -#define OPAMP_MODE_NON_INVERT_INDEX3_KEY (0x19) -#define OPAMP_MODE_NON_INVERT_INDEX4_KEY (0x09) -#define OPAMP_MODE_USER_DEFINE_KEY (0x04) - -/** - * @brief Reverse Input Pin Selection - * - */ -typedef enum { - inm_pad_vim0 = 0, /**< Connect pad vim0 */ - inm_pad_vim1 = 1, /**< Connect pad vim1 */ - inm_pad_vim2 = 2, /**< Connect pad vim2 */ - inm_pad_dac = 3, /**< Connect pad vim dac */ - inm_pad_floating = 4 /**< Connect inm floating */ -} opamp_inm_pad_t; - -/** - * @brief Gain multiplier selection - * - */ -typedef enum { - gain_x_2 = 0, /**< gain x2 */ - gain_x_4 = 1, - gain_x_8 = 2, - gain_x_16 = 3, - gain_x_32 = 4, - gain_x_64 = 5, - gain_x_128 = 6, /**< gain x128 */ -} opamp_gain_t; - -/** - * @brief Miller Capacitor Selection - * - */ -typedef enum { - miller_cap_x_7 = 0, /**< 7 unit cap */ - miller_cap_x_8 = 1, - miller_cap_x_10 = 2, - miller_cap_x_13 = 3, - miller_cap_x_15 = 4, /**< 15 unit cap */ - miller_cap_x_18 = 5, - miller_cap_x_5 = 6, - miller_cap_x_6 = 7, /**< 6 unit cap */ -} opamp_miller_cap_t; - -/** - * @brief Positive Input Pin Selection - * - */ -typedef enum { - inp_pad_vip0 = 0, /**< Connect pad vip0 */ - inp_pad_vip1 = 1, /**< Connect pad vip1 */ - inp_pad_vip2 = 2, /**< Connect pad vip2 */ - inp_pad_dac = 3, /**< Connect pad vip dac */ - inp_pad_vsupply_x_0_25 = 4, /**< Connect reference = 0.25 * vsupply */ - inp_pad_vsupply_x_0_5 = 5, /**< Connect reference = 0.5 * vsupply */ - inp_pad_vsupply_x_0_75 = 6, /**< Connect reference = 0.75 * vsupply */ - inp_pad_floating = 7 /**< Connect inp floating */ -} opamp_inp_pad_t; - -/** - * @brief opamp preset channel - * - */ -typedef enum { - cfg_preset_0 = OPAMP_CFG_PRESET0, - cfg_preset_1 = OPAMP_CFG_PRESET1, - cfg_preset_2 = OPAMP_CFG_PRESET2, - cfg_preset_3 = OPAMP_CFG_PRESET3, - cfg_preset_4 = OPAMP_CFG_PRESET4, - cfg_preset_5 = OPAMP_CFG_PRESET5, - cfg_preset_6 = OPAMP_CFG_PRESET6, - cfg_preset_7 = OPAMP_CFG_PRESET7, -} opamp_cfg_preset_chn_t; - -/** - * @brief operational amplifier - * - */ -typedef enum { - mode_follow = 0, /**< opamp follow mode */ - mode_invert_intern_vol = 1, /**< inverting opamp */ - mode_invert_extern_vol = 2, /**< inverted amplification mode, external reference voltage */ - mode_invert_dac_vol = 3, /**< inverted amplification mode, DAC output reference voltage */ - mode_non_invert_gnd_vol = 4, /**< forward amplification mode, GND is the reference voltage */ - mode_non_invert_extern_vol = 5, /**< forward amplification mode, external reference voltage */ - mode_non_invert_dac_vol = 6, /**< forward amplification mode, DAC output reference voltage */ - mode_user = 7, /**< custom Mode */ -} opamp_mode_t; - -/** - * @brief opamp configuration preset0 - * - */ -typedef union opamp_cfg_preset0 { - struct { - uint32_t vip_select: 3; - uint32_t vim_select: 3; - uint32_t vswitch_select: 3; - uint32_t cap_select: 4; - uint32_t reserve: 19; - }; - uint32_t val; -} opamp_ctrl_cfg_preset0_t; - -/** - * @brief opamp configuration preset1 - * - */ -typedef union opamp_cfg_preset1 { - struct { - uint32_t res_select: 3; - uint32_t function_mode: 5; - uint32_t iref_select: 2; - uint32_t opaout_select: 2; - uint32_t is_vssa_disconnect: 1; - uint32_t en_lv: 1; - uint32_t hw_trig_en: 1; - uint32_t reserve: 17; - }; - uint32_t val; -} opamp_ctrl_cfg_preset1_t; - -typedef struct opamp_cfg { - opamp_mode_t mode; - opamp_inm_pad_t negative_input_pin; - opamp_inp_pad_t positive_input_pin; - opamp_gain_t gain; - opamp_miller_cap_t miller_cap; - bool enable_extern_filter_cap; - bool enable_phase_margin_cap; -} opamp_cfg_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief opamp initialisation functions - * Use this function to initialise the op-amp to different modes - * @param opamp @ref OPAMP_Type - * @param cfg @ref opamp_cfg_t - * @return @ref hpm_stat_t - */ -hpm_stat_t opamp_init(OPAMP_Type *opamp, opamp_cfg_t *cfg); -/** - * @brief enable opamp function - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_enable(OPAMP_Type *opamp) -{ - opamp->CTRL0 |= OPAMP_CTRL0_EN_LV_MASK; -} - -/** - * @brief preset enable opamp function - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_opamp_enable(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_EN_LV_MASK; -} - -/** - * @brief disable opamp function - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_disable(OPAMP_Type *opamp) -{ - opamp->CTRL0 &= ~OPAMP_CTRL0_EN_LV_MASK; -} - -/** - * @brief preset disable opamp function - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_opamp_disable(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_EN_LV_MASK; -} - -/** - * @brief opamp miller cap selection - * - * @param opamp @ref OPAMP_Type - * @param select @ref opamp_miller_cap_t - */ -static inline void opamp_miller_cap_select(OPAMP_Type *opamp, opamp_miller_cap_t select) -{ - opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MILLER_SEL_MASK)) | OPAMP_CTRL0_MILLER_SEL_SET(select); -} - -/** - * @brief opamp miller cap selection preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param select @ref opamp_miller_cap_t - */ -static inline void opamp_preset_miller_cap_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_miller_cap_t select) -{ - opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_MILLER_SEL_MASK)) | OPAMP_CFG_CFG0_MILLER_SEL_SET(select); -} - -/** - * @brief enable phase margin compensation cap - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_phase_margin_cap_enable(OPAMP_Type *opamp) -{ - opamp->CTRL0 &= ~OPAMP_CTRL0_DISABLE_PM_CAP_MASK; -} - -/** - * @brief enable phase margin compensation cap preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_phase_margin_cap_enable(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG0 &= ~OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; -} - -/** - * @brief disable phase margin compensation cap - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_phase_margin_cap_disable(OPAMP_Type *opamp) -{ - opamp->CTRL0 |= OPAMP_CTRL0_DISABLE_PM_CAP_MASK; -} - -/** - * @brief disable phase margin compensation cap preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_phase_margin_cap_disable(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG0 |= OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK; -} - -/** - * @brief opamp core inm connect pad - * - * @param opamp @ref OPAMP_Type - * @param select @ref opamp_inm_pad_t - */ -static inline void opamp_inn_pad_select(OPAMP_Type *opamp, opamp_inm_pad_t select) -{ - opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIM_SEL_MASK)) | OPAMP_CTRL0_VIM_SEL_SET(select); -} - -/** - * @brief opamp core inm connect pad preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param select @ref opamp_inm_pad_t - */ -static inline void opamp_preset_inn_pad_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_inm_pad_t select) -{ - opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIM_SEL_MASK)) | OPAMP_CFG_CFG0_VIM_SEL_SET(select); -} - -/** - * @brief main string resistor selection - * - * @param opamp @ref OPAMP_Type - * @param select @ref opamp_gain_t - * - */ -static inline void opamp_gain_select(OPAMP_Type *opamp, opamp_gain_t select) -{ - opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_GAIN_SEL_MASK)) | OPAMP_CTRL0_GAIN_SEL_SET(select); -} - -/** - * @brief main string resistor selection preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param select @ref opamp_gain_t - * - */ -static inline void opamp_preset_gain_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_gain_t select) -{ - opamp->CFG[preset_chn].CFG1 = (opamp->CFG[preset_chn].CFG1 & (~OPAMP_CFG_CFG1_GAIN_SEL_MASK)) | OPAMP_CFG_CFG1_GAIN_SEL_SET(select); -} - -/** - * @brief disconnect the main series resistor and VSSA - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_disconnect_vssa(OPAMP_Type *opamp) -{ - opamp->CTRL0 |= OPAMP_CTRL0_VBYPASS_MASK; -} - -/** - * @brief disconnect the main series resistor and VSSA preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_disconnect_vssa(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_VBYPASS_LV_MASK; -} - -/** - * @brief connect the main series resistor and VSSA - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_connect_vssa(OPAMP_Type *opamp) -{ - opamp->CTRL0 &= ~OPAMP_CTRL0_VBYPASS_MASK; -} - -/** - * @brief connect the main series resistor and VSSA preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_connect_vssa(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_VBYPASS_LV_MASK; -} - -/** - * @brief opamp inp select - * - * @param opamp @ref OPAMP_Type - * @param select @ref opamp_inp_pad_t - */ -static inline void opamp_inp_pad_select(OPAMP_Type *opamp, opamp_inp_pad_t select) -{ - opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_VIP_SEL_MASK)) | OPAMP_CTRL0_VIP_SEL_SET(select); -} - -/** - * @brief opamp inp select preset - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param select @ref opamp_inp_pad_t - */ -static inline void opamp_preset_inp_pad_select(OPAMP_Type *opamp, uint8_t preset_chn, opamp_inp_pad_t select) -{ - opamp->CFG[preset_chn].CFG0 = (opamp->CFG[preset_chn].CFG0 & (~OPAMP_CFG_CFG0_VIP_SEL_MASK)) | OPAMP_CFG_CFG0_VIP_SEL_SET(select); -} - - -/** - * @brief opamp get current preset - * - * @param opamp @ref OPAMP_Type - * @return value - */ -static inline uint8_t opamp_get_cur_preset(OPAMP_Type *opamp) -{ - return OPAMP_STATUS_CUR_PRESET_GET(opamp->STATUS); -} - -/** - * @brief get the current preset value - * - * @param opamp @ref OPAMP_Type - * @return true one of cur_preset is selected for opamp - * @return false opamp use cfg0 parameters - */ -static inline bool opamp_get_is_preset(OPAMP_Type *opamp) -{ - return OPAMP_STATUS_PRESET_ACT_GET(opamp->STATUS); -} - -/** - * @brief Get the trigger conflict status - * - * @param opamp @ref OPAMP_Type - * @return if more than one hardware trigger is set, will put all trigger input there. - */ -static inline uint8_t opamp_get_trig_conflict_status(OPAMP_Type *opamp) -{ - return OPAMP_STATUS_TRIG_CONFLICT_GET(opamp->STATUS); -} - -/** - * @brief Clear the trigger conflict status - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_clear_conflict_status(OPAMP_Type *opamp) -{ - opamp->STATUS = OPAMP_STATUS_TRIG_CONFLICT_MASK; -} - -/** - * @brief Set opamp preset value - * - * @param opamp @ref OPAMP_Type - * @param val @ref opamp_cfg_preset_chn_t - */ -static inline void opamp_set_sw_preset_val(OPAMP_Type *opamp, opamp_cfg_preset_chn_t val) -{ - opamp->CTRL1 = (opamp->CTRL1 & (~OPAMP_CTRL1_SW_SEL_MASK)) | OPAMP_CTRL1_SW_SEL_SET(val); -} - -/** - * @brief Enable software preset - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_enable_sw_preset(OPAMP_Type *opamp) -{ - opamp->CTRL1 |= OPAMP_CTRL1_SW_PRESET_MASK; -} - -/** - * @brief Disable software preset - * - * @param opamp @ref OPAMP_Type - */ -static inline void opamp_disable_sw_preset(OPAMP_Type *opamp) -{ - opamp->CTRL1 &= ~OPAMP_CTRL1_SW_PRESET_MASK; -} - - -/** - * @brief Set preset x channel value - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param chn channel - */ -static inline void opamp_set_preset_x_chn(OPAMP_Type *opamp, uint8_t preset_chn, uint8_t chn) -{ - opamp->CFG[preset_chn].CFG2 = OPAMP_CFG_CFG2_CHANNEL_SET(chn); -} - -/** - * @brief Set preset cfg - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param cfg @ref opamp_cfg_t - * @return hpm_stat_t - */ -hpm_stat_t opamp_set_preset_cfg(OPAMP_Type *opamp, uint8_t preset_chn, opamp_cfg_t *cfg); - -/** - * @brief opamp enable preset hardware trig - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_enable_hw_trig(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG1 |= OPAMP_CFG_CFG1_HW_TRIG_EN_MASK; -} - -/** - * @brief opamp disable preset hardware trig - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - */ -static inline void opamp_preset_disable_hw_trig(OPAMP_Type *opamp, uint8_t preset_chn) -{ - opamp->CFG[preset_chn].CFG1 &= ~OPAMP_CFG_CFG1_HW_TRIG_EN_MASK; -} - -/** - * @brief opamp set mode - * - * @param opamp @ref OPAMP_Type - * @param mode OPAMP_MODE_XX - */ -static inline void opamp_mode_set(OPAMP_Type *opamp, uint8_t mode) -{ - opamp->CTRL0 = (opamp->CTRL0 & (~OPAMP_CTRL0_MODE_MASK)) | OPAMP_CTRL0_MODE_SET(mode); -} - -/** - * @brief opamp preset set mode - * - * @param opamp @ref OPAMP_Type - * @param preset_chn preset channel - * @param mode OPAMP_MODE_XX - */ -static inline void opamp_preset_mode_set(OPAMP_Type *opamp, uint8_t preset_chn, uint8_t mode) -{ - opamp->CFG[preset_chn].CFG1 = (opamp->CFG[preset_chn].CFG1 & (~OPAMP_CFG_CFG1_MODE_MASK)) | OPAMP_CFG_CFG1_MODE_SET(mode); -} - -/** - * @} - * - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_ACMP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h deleted file mode 100644 index d36edc9dc00..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdgo_drv.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PDGO_DRV_H -#define HPM_PDGO_DRV_H - -#include "hpm_common.h" -#include "hpm_pdgo_regs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define DGO_GPR_WORD_COUNT (4U) /*!< DGO GPR register count */ -#define DGO_WAKEUP_COUNTER_TICKS_PER_SEC (32768UL) /*!< DGO Wakeup Counter frequency */ -#define DGO_TURNOFF_COUNTER_TICKS_PER_SEC (24000000UL) /*!< DGO Turn-off counter frequency */ -#define DGO_WAKEUP_TICK_IN_US (1000000UL / DGO_WAKEUP_COUNTER_TICKS_PER_SEC) -#define DGO_TURNOFF_TICKS_PER_US (DGO_TURNOFF_COUNTER_TICKS_PER_SEC / 1000000UL) - -/** -* -* @brief PDGO driver APIs -* @defgroup pdgo_interface DGO driver APIs -* @ingroup pdgo_interfaces -* @{ -* -*/ - -/** - * @brief Set DGO turn-off counter - * @param [in] ptr DGO base address - * @param [in] counter Turn-off counter value. Clock source is 32K - */ -static inline void pdgo_set_turnoff_counter(PDGO_Type *ptr, uint32_t counter) -{ - ptr->DGO_TURNOFF = counter; -} - -/** - * @brief Enable Software Wake-up feature on DGO - * @param [in] ptr DGO base address - */ -static inline void pdgo_enable_software_wakeup(PDGO_Type *ptr) -{ - ptr->DGO_CTR1 |= PDGO_DGO_CTR1_WAKEUP_EN_MASK; -} - -/** - * @brief Disable Software Wake-up feature on DGO - * @param [in] ptr DGO base address - */ -static inline void pdgo_disable_software_wakeup(PDGO_Type *ptr) -{ - ptr->DGO_CTR1 &= ~PDGO_DGO_CTR1_WAKEUP_EN_MASK; -} - -/** - * @brief Set DGO to one-shot wakeup mode - * @param [in] ptr DGO base address - */ -static inline void pdgo_enable_oneshot_wakeup(PDGO_Type *ptr) -{ - ptr->DGO_CTR1 &= ~PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK; -} - -/** - * @brief Enable DGO register retention mode - * @param [in] ptr DGO base address - */ -static inline void pdgo_enable_retention_mode(PDGO_Type *ptr) -{ - ptr->DGO_CTR1 |= PDGO_DGO_CTR0_RETENTION_MASK; -} - -/** - * @brief Check whether the DGO retention mode is enabled or not - * @param [in] ptr DGO base address - * - * @retval true Retention mode is enabled - * @retval false Retention mode is disabled - */ -static inline bool pdgo_is_retention_mode_enabled(PDGO_Type *ptr) -{ - return ((ptr->DGO_CTR1 & PDGO_DGO_CTR0_RETENTION_MASK) != 0U); -} - -/** - * @brief Disable DGO register retention mode - * @param [in] ptr DGO base address - */ -static inline void pdgo_disable_retention_mode(PDGO_Type *ptr) -{ - ptr->DGO_CTR1 &= ~PDGO_DGO_CTR0_RETENTION_MASK; -} - -/** - * @brief Set DGO to automatic wakeup mode - * @param [in] ptr DGO base address - */ -static inline void pdgo_enable_auto_wakeup(PDGO_Type *ptr) -{ - ptr->DGO_CTR1 |= PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK; -} - -#if defined(PDGO_SUPPORT_SYS_WAKEUP_STATUS) && (PDGO_SUPPORT_SYS_WAKEUP_STATUS == 1) -/** - * @brief Check whether DGO is waked up by System/Software - * @param [in] ptr DGO base address - * - * @retval true if DGO is waked up by System/Software - */ -static inline bool pdgo_is_system_wakeup(PDGO_Type *ptr) -{ - return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_SYS_WAKEUP_STATUS_MASK) != 0U); -} -#endif - -/** - * @brief Check whether DGO is waked up by Wake-up/Reset Pin - * @param [in] ptr DGO base address - * - * @retval true if DGO is waked up by Wakeup/Reset pin - */ -static inline bool pdgo_is_pin_wakeup(PDGO_Type *ptr) -{ - return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) != 0U); -} - - -/** - * @brief Check whether Auto wake-up is enabled - * @param [in] ptr DGO base address - * - * @retval true - Auto wake-up is enabled - * @retval false - Auto wake-up is disabled - */ -static inline bool pdgo_is_auto_wakeup_enabled(PDGO_Type *ptr) -{ - return ((ptr->DGO_CTR1 & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) != 0U); -} - -/** - * @brief Enable pull-up resistor for Reset Pin - * [in] ptr DGO base address - */ -static inline void pdgo_enable_pullup_resistor_for_reset_pin(PDGO_Type *ptr) -{ - ptr->DGO_CTR2 &= ~PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK; -} - -/** - * @brief Disable pull-up resistor for Reset Pin - * [in] ptr DGO base address - */ -static inline void pdgo_disable_pullup_resistor_for_reset_pin(PDGO_Type *ptr) -{ - ptr->DGO_CTR2 |= PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK; -} - -/** - * Enable pull-down resistor for Wakeup pin - * [in] ptr DGO base address - */ -static inline void pdgo_enable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr) -{ - ptr->DGO_CTR2 &= ~PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK; -} - -/** - * Disable pull-down resistor for Wakeup pin - * [in] ptr DGO base address - */ -static inline void pdgo_disable_pulldown_resistor_for_wakeup_pin(PDGO_Type *ptr) -{ - ptr->DGO_CTR2 |= PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK; -} - -/** - * @brief Set DGO wakeup counter - * @param [in] ptr DGO base address - * @param [in] wakeup_ctr Wakeup counter value. clock source is 32K - */ -static inline void pdgo_set_wakeup_counter(PDGO_Type *ptr, uint32_t wakeup_ctr) -{ - ptr->DGO_CTR3 = wakeup_ctr; -} - -/** - * @brief Get DGO wakeup counter value - * @param [in] ptr DGO base address - * - * @return DGO wakeup counter value - */ -static inline uint32_t pdgo_get_wakeup_counter(PDGO_Type *ptr) -{ - return ptr->DGO_CTR3; -} - -/** - * @brief Write data to DGO GPR register - * @param [in] ptr DGO base address - * @param [in] index GPR register index - * @param [in] content Data to be written to DGO GPR register - */ -static inline void pdgo_write_gpr(PDGO_Type *ptr, uint32_t index, uint32_t content) -{ - if (index < DGO_GPR_WORD_COUNT) { - *(volatile uint32_t *) ((uint32_t) &ptr->DGO_GPR00 + index * 4) = content; - } -} - -/** - * @brief Read data from DGO GPR register - * @param [in] ptr DGO base address - * @param [in] index GPR register index - * - * @return DGO GPR register value - */ -static inline uint32_t pdgo_read_gpr(PDGO_Type *ptr, uint32_t index) -{ - uint32_t reg_val = 0; - if (index < DGO_GPR_WORD_COUNT) { - reg_val = *(volatile uint32_t *) ((uint32_t) &ptr->DGO_GPR00 + index * 4); - } - return reg_val; -} - -/** - * @brief Convert the microsecond to DGO Wake-up counter value - * @param [in] us microsecond to be converted - * - * @return Converted DGO Wake-up counter value - */ -static inline uint32_t pdgo_get_wakeup_counter_from_us(uint32_t us) -{ - return (us + DGO_WAKEUP_TICK_IN_US - 1U) / DGO_WAKEUP_TICK_IN_US; -} - -/** - * @brief Convert the DGO Wake-up counter to microseconds - * @param [in] counter DGO counter - * - * @return Converted microseconds - */ -static inline uint32_t pdgo_get_us_from_wakeup_counter(uint32_t counter) -{ - return (counter * DGO_WAKEUP_TICK_IN_US); -} - -/** - * @brief Convert the microsecond to DGO Turn-off counter value - * @param [in] us microsecond to be converted - * - * @return Converted DGO Turn-off counter value - */ -static inline uint32_t pdgo_get_turnoff_counter_from_us(uint32_t us) -{ - return (us * DGO_TURNOFF_TICKS_PER_US); -} - -/** - * @brief Convert the DGO Turn-off counter to microseconds - * @param [in] counter DGO Turn-off counter - * - * @return Converted microseconds - */ -static inline uint32_t pdgo_get_us_from_turnoff_counter(uint32_t counter) -{ - return (counter + DGO_TURNOFF_TICKS_PER_US - 1U) / DGO_TURNOFF_TICKS_PER_US; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* HPM_DGO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h deleted file mode 100644 index 1ddd718c973..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdm_drv.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PDM_DRV_H -#define HPM_PDM_DRV_H - -#include "hpm_common.h" -#include "hpm_pdm_regs.h" - -/** - * @brief PDM driver APIs - * @defgroup pdm_interface PDM driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief PDM event - */ -#define PDM_EVENT_FILT_CRX_ERROR (PDM_ST_FILT_CRX_ERR_MASK) -#define PDM_EVENT_OFIFO_OVERFLOW_ERROR (PDM_ST_OFIFO_OVFL_ERR_MASK) -#define PDM_EVENT_CIC_OVERLOAD_ERROR (PDM_ST_CIC_OVLD_ERR_MASK) -#define PDM_EVENT_CIC_SAT_ERROR (PDM_ST_CIC_SAT_ERR_MASK) - -/** - * @brief PDM CIC sidma-delta filter order - */ -#define PDM_CIC_SIGMA_DELTA_ORDER_5 (2U) -#define PDM_CIC_SIGMA_DELTA_ORDER_6 (1U) -#define PDM_CIC_SIGMA_DELTA_ORDER_7 (0U) - -/** - * @brief PDM config - */ -typedef struct pdm_config { - bool sof_at_ref_clk_falling_edge; - bool bypass_pdm_clk_div; - bool enable_pdm_clk_out; - bool enable_hpf; - uint8_t pdm_clk_div; - uint8_t capture_delay; - uint8_t dec_after_cic; - uint8_t post_scale; - uint8_t sigma_delta_order; - uint8_t cic_dec_ratio; -} pdm_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief config high pass filter - * - * @param [in] ptr PDM base address - * @param [in] hpf_coef_ma high pass filter a coefficient's complement - * @param [in] hpf_coef_b high pass filter b coefficient - */ -static inline void pdm_config_hpf(PDM_Type *ptr, - uint32_t hpf_coef_ma, - uint32_t hpf_coef_b) -{ - ptr->HPF_MA = PDM_HPF_MA_COEF_SET(hpf_coef_ma); - ptr->HPF_B = PDM_HPF_B_COEF_SET(hpf_coef_b); -} - -/** - * @brief enable high pass filter - * - * @param [in] ptr PDM base address - */ -static inline void pdm_enable_hpf(PDM_Type *ptr) -{ - ptr->CTRL |= PDM_CTRL_HPF_EN_MASK; -} - -/** - * @brief disable high pass filter - * - * @param [in] ptr PDM base address - */ -static inline void pdm_disable_hpf(PDM_Type *ptr) -{ - ptr->CTRL &= ~PDM_CTRL_HPF_EN_MASK; -} - -/** - * @brief check whether PDM is running - * - * @param [in] ptr PDM base address - * @retval true in PDM is running - */ -static inline bool pdm_is_running(PDM_Type *ptr) -{ - return ptr->RUN & PDM_RUN_PDM_EN_MASK; -} - -/** - * @brief stop pdm - * - * @param [in] ptr PDM base address - */ -static inline void pdm_stop(PDM_Type *ptr) -{ - ptr->RUN &= ~PDM_RUN_PDM_EN_MASK; -} - -/** - * @brief start pdm - * - * @param [in] ptr PDM base address - */ -static inline void pdm_start(PDM_Type *ptr) -{ - ptr->RUN |= PDM_RUN_PDM_EN_MASK; -} - -/** - * @brief disable channel - * - * @param [in] ptr PDM base address - * @param [in] channel_disable_mask channel mask - */ -static inline void pdm_disable_channel(PDM_Type *ptr, - uint16_t channel_disable_mask) -{ - ptr->CH_CTRL &= ~PDM_CH_CTRL_CH_EN_SET(channel_disable_mask); -} - -/** - * @brief enable channel - * - * @param [in] ptr PDM base address - * @param [in] capture_high_level_mask capture when PDM_CLK is high - * @param [in] channel_enable_mask channel mask - */ -static inline void pdm_enable_channel(PDM_Type *ptr, - uint16_t capture_high_level_mask, - uint16_t channel_enable_mask) -{ - ptr->CH_CTRL |= PDM_CH_CTRL_CH_POL_SET(capture_high_level_mask) - | PDM_CH_CTRL_CH_EN_SET(channel_enable_mask); -} - -/** - * @brief disable pdm clock out - * - * @param [in] ptr PDM base address - */ -static inline void pdm_disable_pdm_clock_out(PDM_Type *ptr) -{ - ptr->CTRL &= ~PDM_CTRL_PDM_CLK_OE_MASK; -} - -/** - * @brief enable pdm clock out - * - * @param [in] ptr PDM base address - */ -static inline void pdm_enable_pdm_clock_out(PDM_Type *ptr) -{ - ptr->CTRL |= PDM_CTRL_PDM_CLK_OE_MASK; -} - -/** - * @brief pdm config cic - * - * @param [in] ptr PDM base address - * @param [in] sigma_delta_order sidma-delta filter order - * @param [in] div Rate of down sampling - * @param [in] post_scale output value post scale - */ -static inline void pdm_config_cic(PDM_Type *ptr, - uint8_t sigma_delta_order, - uint8_t div, - uint8_t post_scale) -{ - ptr->CIC_CFG = PDM_CIC_CFG_POST_SCALE_SET(post_scale) - | PDM_CIC_CFG_SGD_SET(sigma_delta_order) - | PDM_CIC_CFG_CIC_DEC_RATIO_SET(div); -} - -/** - * @brief pdm software reset - * - * @param [in] ptr PDM base address - */ -static inline void pdm_software_reset(PDM_Type *ptr) -{ - ptr->CTRL |= PDM_CTRL_SFTRST_MASK; - ptr->CTRL &= ~PDM_CTRL_SFTRST_MASK; -} - -/** - * @brief pdm enable irq - * - * @param [in] ptr PDM base address - * @param [in] mask pdm irq mask in ST register - */ -static inline void pdm_enable_irq(PDM_Type *ptr, uint8_t mask) -{ - ptr->CTRL |= mask << (PDM_CTRL_CIC_SAT_ERR_IE_SHIFT - PDM_ST_CIC_SAT_ERR_SHIFT); -} - -/** - * @brief pdm disable irq - * - * @param [in] ptr PDM base address - * @param [in] mask pdm irq mask in ST register - */ -static inline void pdm_disable_irq(PDM_Type *ptr, uint8_t mask) -{ - ptr->CTRL &= ~(mask << (PDM_CTRL_CIC_SAT_ERR_IE_SHIFT - PDM_ST_CIC_SAT_ERR_SHIFT)); -} - -/** - * @brief pdm initialization - * - * @param [in] ptr PDM base address - * @param [in] config pdm_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t pdm_init(PDM_Type *ptr, pdm_config_t *config); - -/** - * @brief pdm get default config - * - * @param [in] ptr PDM base address - * @param [out] config pdm_config_t - */ -void pdm_get_default_config(PDM_Type *ptr, pdm_config_t *config); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_PDM_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h deleted file mode 100644 index 8917a26946a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pdma_drv.h +++ /dev/null @@ -1,460 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PDMA_DRV_H -#define HPM_PDMA_DRV_H -#include "hpm_soc_feature.h" -#include "hpm_display_common.h" -#include "hpm_pdma_regs.h" - -/** - * @brief PDMA driver APIs - * @defgroup pdma_interface PDMA driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief PDMA status - */ -enum { - status_pdma_done = status_success, - status_pdma_error = MAKE_STATUS(status_group_pdma, 1), - status_pdma_busy = MAKE_STATUS(status_group_pdma, 2), - status_pdma_idle = MAKE_STATUS(status_group_pdma, 3), -}; - -/** - * @brief PDMA plane - */ -typedef enum pdma_plane { - pdma_plane_src = 0, - pdma_plane_dst = 1, - pdma_plane_both, - pdma_plane_none, -} pdma_plane_t; - -/** - * @brief PDMA flip - */ -typedef enum pdma_flip { - pdma_flip_none = 0, - pdma_flip_horizontal = 1 << 0, - pdma_flip_vertical = 1 << 1, - pdma_flip_both = pdma_flip_horizontal | pdma_flip_vertical, -} pdma_flip_t; - -/** - * @brief PDMA rotate - */ -typedef enum pdma_rotate { - pdma_rotate_0_degree = 0, - pdma_rotate_90_degree = 1, - pdma_rotate_180_degree = 2, - pdma_rotate_270_degree = 3, -} pdma_rotate_t; - -/** - * @brief PDMA decimation - */ -typedef enum pdma_decimation { - pdma_decimation_by_1 = 0, - pdma_decimation_by_2 = 1, - pdma_decimation_by_4 = 2, - pdma_decimation_by_8 = 3, -} pdma_decimation_t; - -/** - * @brief PDMA block size - */ -typedef enum pdma_blocksize { - pdma_blocksize_16x16, - pdma_blocksize_8x8, -} pdma_blocksize_t; - -/** - * @brief PDMA make scale value - */ -#define PDMA_MAKE_SCALE_SET(integer, fractional) \ - (((integer) & 0x3) << 12 | ((fractional) & 0xFFF)) - -/** - * @brief PDMA plane config - */ -typedef struct pdma_plane_config { - bool swap_byte3_byte1; /**< set true to swap byte [31:24] and byte [15:8] */ - bool use_background_as_clear; /**< set true to use background color at blending clear mode */ - bool ycbcr_mode; /**< set true if it is YCbCr mode */ - bool bypass_colorspace_conversion; /**< set true to bypass color space conversion */ - bool byte_swap; /**< set true to swap [31:16] and [15:0] */ - display_byteorder_t byteorder; /**< packing byte order type */ - pdma_flip_t flip; /**< flip type */ - pdma_rotate_t rotate; /**< rotate type */ - pdma_decimation_t x_dec; /**< horizontal decimation */ - pdma_decimation_t y_dec; /**< vertical decimation */ - display_pixel_format_t pixel_format; /**< pixel format */ - uint32_t buffer; /**< buffer address */ - uint32_t background; /**< background color */ - uint32_t colorkey_high; /**< colorkey high limit */ - uint32_t colorkey_low; /**< colorkey low limit */ - uint16_t x_scale; /**< 14-bit horizontal scale */ - uint16_t y_scale; /**< 14-bit vertical scale */ - uint16_t pitch; /**< pitch value */ - uint16_t x_offset; /**< horizontal offset */ - uint16_t y_offset; /**< vertical offset */ - uint16_t width; /**< width */ - uint16_t height; /**< height */ -} pdma_plane_config_t; - -/** - * @brief PDMA output config - */ -typedef struct pdma_output_config { - display_alphablend_option_t alphablend; /**< alpha blending mode */ - display_pixel_format_t pixel_format; /**< pixel format */ - display_rgb2yuv_config_t rgb2yuv_config; /**< RGB to YUV config */ - uint32_t buffer; /**< buffer */ - struct { - uint16_t x; /**< plane origin X coord */ - uint16_t y; /**< plane origin Y coord */ - uint16_t width; /**< plane width */ - uint16_t height; /**< plane height */ - } plane[PDMA_SOC_PS_MAX_COUNT]; /**< plane config */ - uint16_t width; /**< output plane width */ - uint16_t height; /**< output plane height */ - uint16_t pitch; -} pdma_output_config_t; - -/** - * @brief PDMA config - */ -typedef struct pdma_config { - display_byteorder_t byteorder; /**< byte order */ - pdma_blocksize_t block_size; /**< block size */ - pdma_plane_t enable_plane; /**< plane to be enabled */ -} pdma_config_t; - -/** - * @brief PDMA plane info - */ -typedef struct pdma_plane_info { - uint32_t buffer; /**< buffer */ - uint32_t x; /**< plane origin X coord */ - uint32_t y; /**< plane origin Y coord */ - uint32_t width; /**< plane width */ - uint32_t height; /**< plane height */ - display_pixel_format_t format; /**< pixel format */ -} pdma_plane_info_t; - - -typedef struct pdma_blit_option { - display_alphablend_mode_t blend; - struct { - uint16_t x; - uint16_t y; - } translate; - pdma_flip_t flip; - pdma_rotate_t rotate; - struct { - float x; /* 0.0625 - 4095 */ - float y; /* 0.0625 - 4095 */ - } scale; -} pdma_blit_option_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get default configuration according to input pixel format - * - * @param [in] ptr PDMA base address - * @param [out] config pdma_config_t - * @param [in] pixel_format display_pixel_format_t - */ -void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixel_format_t pixel_format); - -/** - * @brief Get default plane configuration according input pixel format - * - * @param [in] ptr PDMA base address - * @param [out] config pdma_plane_config_t - * @param [in] pixel_format display_pixel_format_t - */ -void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, display_pixel_format_t pixel_format); - -/** - * @brief Get default YUV2RGB coefficient configuration according to input pixel format - * - * @note The two plane share one YUV2RGB_COEF, so not support convert one plane YUV422 format - * and another plane YCbCr422 format at same time - * - * @param [in] ptr PDMA base address - * @param [out] yuv2rgb_coef display_yuv2rgb_coef_t - * @param [in] source_format the YUV2RGB input source pixel format - */ -void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t *yuv2rgb_coef, display_pixel_format_t source_format); - -/** - * @brief Get default output configuration - * - * @param [in] ptr PDMA base address - * @param [out] config pdma_output_config_t - * @param [in] pixel_format output data pixel format - */ -void pdma_get_default_output_config(PDMA_Type *ptr, - pdma_output_config_t *config, display_pixel_format_t pixel_format); - -/** - * @brief PDMA enable/disable irq - * - * @param [in] ptr PDMA base address - * @param [in] mask irq mask - * @param [in] enable : - * @arg true: enable - * @arg false: disable - */ -void pdma_enable_irq(PDMA_Type *ptr, uint32_t mask, bool enable); - -/** - * @brief PDMA config output - * - * @param [in] ptr PDMA base address - * @param [in] config pdma_output_config_t - */ -void pdma_config_output(PDMA_Type *ptr, pdma_output_config_t *config); - -/** - * @brief Configure PDMA planes - * - * Note: The plane_src and plane_dst share one YUV2RGB_COEF, so not support convert one plane YUV422 format - * and another plane YCbCr422 format at same time - * - * @param [in] ptr PDMA base address - * @param [in] plane_src_config Pointer to plane_src configuration structure - * @param [in] plane_dst_config Pointer to plan_dst configuration structure - * @param [in] yuv2rgb_coef Pointer to yuv2rgb_coef configuration structure - */ -void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_config, void *yuv2rgb_coef); - -/** - * @brief PDMA initialization - * - * @param [in] ptr PDMA base address - * @param [in] config pdma_output_config_t - */ -void pdma_init(PDMA_Type *ptr, pdma_config_t *config); - -/** - * @brief PDMA check status - * - * @param [in] ptr PDMA base address - * @param [out] status pdma status - */ -hpm_stat_t pdma_check_status(PDMA_Type *ptr, uint32_t *status); - -/** - * @brief PDMA fill color - * - * @param [in] ptr PDMA base address - * @param [in] dst target buff address - * @param [in] dst_width target buff pixel width - * @param [in] width output image width - * @param [in] height output image height - * @param [in] color color value - * @param [in] alpha alpha value - * @param [in] format display_pixel_format_t - * @param [in] wait wait for execution to complete - * @param [out] status pdma status - * @retval hpm_stat_t: status_success if flip and rotate plane without any error - */ -hpm_stat_t pdma_fill_color(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, - uint32_t width, uint32_t height, - uint32_t color, uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status); - -/** - * @brief PDMA flip rotate plane - * - * @param [in] ptr PDMA base address - * @param [in] dst target buff address - * @param [in] dst_width target buff pixel width - * @param [in] src source buff address - * @param [in] src_width source buff pixel width - * @param [in] x x coordinate n buffer - * @param [in] y y coordinate n buffer - * @param [in] width output image width - * @param [in] height output image height - * @param [in] flip pdma_flip_t - * @param [in] rotate pdma_rotate_t - * @param [in] alpha alpha value - * @param [in] format display_pixel_format_t - * @param [in] wait wait for execution to complete - * @param [out] status pdma status - * @retval hpm_stat_t: status_success if flip and rotate plane without any error - */ -hpm_stat_t pdma_flip_rotate(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, - uint32_t src, uint32_t src_width, uint32_t x, uint32_t y, - uint32_t width, uint32_t height, - pdma_flip_t flip, pdma_rotate_t rotate, uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status); - -/** - * @brief PDMA blit plane - * - * @param [in] ptr PDMA base address - * @param [in] dst target buff address - * @param [in] dst_width target buff pixel width - * @param [in] src source buff address - * @param [in] src_width source buff pixel width - * @param [in] x x coordinate n buffer - * @param [in] y y coordinate n buffer - * @param [in] width output image width - * @param [in] height output image height - * @param [in] alpha alpha value - * @param [in] format display_pixel_format_t - * @param [in] wait wait for execution to complete - * @param [out] status pdma status - * @retval hpm_stat_t: status_success if flip and rotate plane without any error - */ -hpm_stat_t pdma_blit(PDMA_Type *ptr, - uint32_t dst, uint32_t dst_width, - uint32_t src, uint32_t src_width, - uint32_t x, uint32_t y, uint32_t width, uint32_t height, - uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status); - -/** - * @brief PDMA scale plane - * - * @param [in] ptr PDMA base address - * @param [in] dst target buff address - * @param [in] dst_width target buff pixel width - * @param [in] src source buff address - * @param [in] src_width source buff pixel width - * @param [in] x x coordinate n buffer - * @param [in] y y coordinate n buffer - * @param [in] width input image width - * @param [in] height input image height - * @param [in] target_width output image width - * @param [in] target_height output image height - * @param [in] alpha alpha value - * @param [in] format display_pixel_format_t - * @param [in] wait wait for execution to complete - * @param [out] status pdma status - * @retval hpm_stat_t: status_success if flip and rotate plane without any error - */ -hpm_stat_t pdma_scale(PDMA_Type *ptr, - uint32_t dst, uint32_t dst_width, - uint32_t src, uint32_t src_width, - uint32_t x, uint32_t y, uint32_t width, uint32_t height, - uint32_t target_width, uint32_t target_height, - uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status); -/** - * @brief PDMA get default blit option - * - * @param op option of blit - */ -void pdma_get_default_blit_option(pdma_blit_option_t *op); - -/** - * @brief PDMA blit plane by option - * - * @param ptr PDMA base address - * @param dst target buff address - * @param src source buff address - * @param op option of blit - * @param wait wait for execution to complete - * @param status pdma status - * @retval hpm_stat_t: status_success if flip and rotate plane without any error - */ -hpm_stat_t pdma_blit_ex(PDMA_Type *ptr, - display_buf_t *dst, - display_buf_t *src, - pdma_blit_option_t *op, - bool wait, uint32_t *status); - -/** - * @brief PDMA set block size - * - * @param [in] ptr PDMA base address - * @param [in] size pdma_blocksize_t - */ -void pdma_set_block_size(PDMA_Type *ptr, pdma_blocksize_t size); - -/** - * @brief PDMA stop - * - * @param [in] ptr PDMA base address - */ -void pdma_stop(PDMA_Type *ptr); - -/** - * @brief PDMA stop - * - * @param [in] ptr PDMA base address - * - * @retval STAT register value - */ -static inline uint32_t pdma_get_status(PDMA_Type *ptr) -{ - return ptr->STAT; -} - -/** - * @brief PDMA start - * - * @param [in] ptr PDMA base address - */ -static inline void pdma_start(PDMA_Type *ptr) -{ - ptr->CTRL |= PDMA_CTRL_PDMA_EN_MASK; - __asm volatile ("" : : "r" (ptr->CTRL)); -} - -/** - * @brief PDMA software reset - * - * @param [in] ptr PDMA base address - */ -static inline void pdma_software_reset(PDMA_Type *ptr) -{ - ptr->CTRL |= PDMA_CTRL_PDMA_SFTRST_MASK; - ptr->CTRL &= ~(PDMA_CTRL_PDMA_SFTRST_MASK); - __asm volatile ("" : : "r" (ptr->CTRL)); -} - -/** - * @brief PDMA set plane color key limits - * - * @param [in] ptr PDMA base address - * @param [in] plane_index plane index - * @param [in] key_high color key high limits - * @param [in] key_low color key low limits - */ -static inline void pdma_set_plane_colorkey(PDMA_Type *ptr, - uint8_t plane_index, - uint32_t key_high, - uint32_t key_low) -{ - ptr->PS[plane_index].CLRKEY_LOW = PDMA_PS_CLRKEY_LOW_LIMIT_SET(key_low); - ptr->PS[plane_index].CLRKEY_HIGH = PDMA_PS_CLRKEY_HIGH_LIMIT_SET(key_high); -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif -#endif /* HPM_PDMA_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h deleted file mode 100644 index db4fdaf0ede..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h +++ /dev/null @@ -1,336 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PIXELMUX_DRV_H -#define HPM_PIXELMUX_DRV_H - -/** - * @brief PIXELMUX APIs - * @defgroup pixelmux_interface PIXELMUX driver APIs - * @ingroup pixelmux_interfaces - * @{ - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_pixelmux_regs.h" - -/** - * @brief rgb interface pixel data source - */ -typedef enum { - pixelmux_rgb_sel_lcdc0 = 0, - pixelmux_rgb_sel_lcdc1 -} pixelmux_rgb_select_t; - -/** - * @brief gwc1 pixel data source - */ -typedef enum { - pixelmux_gwc1_sel_lcdc0 = 0, - pixelmux_gwc1_sel_lcdc1 -} pixelmux_gwc1_select_t; - -/** - * @brief gwc0 pixel data source - */ -typedef enum { - pixelmux_gwc0_sel_lcdc0 = 0, - pixelmux_gwc0_sel_lcdc1 -} pixelmux_gwc0_select_t; - -/** - * @brief lvb di1 pixel data source - */ -typedef enum { - pixelmux_lvb_di1_sel_lcdc0 = 0, - pixelmux_lvb_di1_sel_lcdc1 -} pixelmux_lvb_di1_select_t; - -/** - * @brief lvb di0 pixel data source - */ -typedef enum { - pixelmux_lvb_di0_sel_lcdc0 = 0, - pixelmux_lvb_di0_sel_lcdc1 -} pixelmux_lvb_di0_select_t; - -/** - * @brief mipi dsi1 pixel data source - */ -typedef enum { - pixelmux_mipi_dsi1_sel_lcdc0 = 0, - pixelmux_mipi_dsi1_sel_lcdc1 -} pixelmux_mipi_dsi1_select_t; - -/** - * @brief mipi dsi0 pixel data source - */ -typedef enum { - pixelmux_mipi_dsi0_sel_lcdc0 = 0, - pixelmux_mipi_dsi0_sel_lcdc1 -} pixelmux_mipi_dsi0_select_t; - -/** - * @brief mipi dsi pixel data type - */ -typedef enum { - pixelmux_mipi_dsi_data_type_rgb565 = 0, - pixelmux_mipi_dsi_data_type_rgb666 = 3, - pixelmux_mipi_dsi_data_type_rgb666_packed = 4, - pixelmux_mipi_dsi_data_type_rgb888 = 5, -} pixelmux_mipi_dsi_data_type_t; - -/** - * @brief cam1 pixel data source - */ -typedef enum { - pixelmux_cam1_sel_dvp = 0, - pixelmux_cam1_sel_mipi_csi0, - pixelmux_cam1_sel_mipi_csi1, - pixelmux_cam1_sel_lcdc0, - pixelmux_cam1_sel_lcdc1, - pixelmux_cam1_sel_lcb_do0, - pixelmux_cam1_sel_lcb_do1, -} pixelmux_cam1_select_t; - -/** - * @brief cam0 pixel data source - */ -typedef enum { - pixelmux_cam0_sel_dvp = 0, - pixelmux_cam0_sel_mipi_csi0, - pixelmux_cam0_sel_mipi_csi1, - pixelmux_cam0_sel_lcdc0, - pixelmux_cam0_sel_lcdc1, - pixelmux_cam0_sel_lcb_do0, - pixelmux_cam0_sel_lcb_do1, -} pixelmux_cam0_select_t; - -#define PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX 40000000UL -#define PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN 10000000UL - -#define PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MAX 4000000000UL -#define PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MIN 2000000000UL - -#define PIXELMUX_LVDS_TX_PHY_DATA_LANE_FREQ_MAX 1000000000UL - -typedef struct lvds_phy_clk_reg { - uint32_t rate_lvds; /*!< rate_lvds[1:0] */ - uint32_t data_rate_div4; - uint32_t refclk_div; /*!< refclk_div[3:0] */ - uint32_t pll_div; /*!< pll_div[14:0] */ -} lvds_phy_clk_reg_t; - -typedef struct lvds_phy_clk_param { - lvds_phy_clk_reg_t reg; - uint32_t fvco_freq_hz; - uint32_t pfd_freq_hz; - uint32_t lane_data_rate_hz; - uint32_t hsclk_freq_hz; -} lvds_phy_clk_param_t; - -typedef enum pixelmux_tx_phy_mode { - pixelmux_tx_phy_mode_gpio = 0, - pixelmux_tx_phy_mode_lvds = 1, - pixelmux_tx_phy_mode_mipi = 2 -} pixelmux_tx_phy_mode_t; - -typedef enum pixelmux_rx_phy_mode { - pixelmux_rx_phy_mode_gpio = 0, - pixelmux_rx_phy_mode_lvds = 1, - pixelmux_rx_phy_mode_mipi = 2, - pixelmux_rx_phy_mode_lvds_camera = 3 -} pixelmux_rx_phy_mode_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief select pixel data source and enable for rgb interface - * - * @param[in] src rgb pixel data source options - */ -void pixelmux_rgb_data_source_enable(pixelmux_rgb_select_t src); - -/** - * @brief disable rgb interface pixel data source - */ -void pixelmux_rgb_data_source_disable(void); - -/** - * @brief select pixel data source and enable for gwc1 - * - * @param[in] src gwc1 pixel data source options - */ -void pixelmux_gwc1_data_source_enable(pixelmux_gwc1_select_t src); - -/** - * @brief disable gwc1 pixel data source - */ -void pixelmux_gwc1_data_source_disable(void); - -/** - * @brief select pixel data source and enable for gwc0 - * - * @param[in] src gwc0 pixel data source options - */ -void pixelmux_gwc0_data_source_enable(pixelmux_gwc0_select_t src); - -/** - * @brief disable gwc0 pixel data source - */ -void pixelmux_gwc0_data_source_disable(void); - -/** - * @brief select pixel data source and enable for lvb di1 - * - * @param[in] src lvb di1 pixel data source options - */ -void pixelmux_lvb_di1_data_source_enable(pixelmux_lvb_di1_select_t src); - -/** - * @brief disable lvb di1 pixel data source - */ -void pixelmux_lvb_di1_data_source_disable(void); - -/** - * @brief select pixel data source and enable for lvb di0 - * - * @param[in] src lvb di0 pixel data source options - */ -void pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_select_t src); - -/** - * @brief disable lvb di0 pixel data source - */ -void pixelmux_lvb_di0_data_source_disable(void); - -/** - * @brief select pixel data source and enable for mipi dsi1 - * - * @param[in] src mipi dsi1 pixel data source options - */ -void pixelmux_mipi_dsi1_data_source_enable(pixelmux_mipi_dsi1_select_t src); - -/** - * @brief disable mipi dis1 pixel data source - */ -void pixelmux_mipi_dsi1_data_source_disable(void); - -/** - * @brief select pixel data source and enable for mipi dsi0 - * - * @param[in] src mipi dsi0 pixel data source options - */ -void pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_select_t src); - -/** - * @brief disable mipi dsi0 pixel data source - */ -void pixelmux_mipi_dsi0_data_source_disable(void); - -/** - * @brief set data type for mipi dsi1 - * - * @param[in] type mipi dsi data type - */ -void pixelmux_mipi_dsi1_set_data_type(pixelmux_mipi_dsi_data_type_t type); - -/** - * @brief set data type for mipi dsi0 - * - * @param[in] type mipi dsi data type - */ -void pixelmux_mipi_dsi0_set_data_type(pixelmux_mipi_dsi_data_type_t type); - -/** - * @brief select pixel data source and enable for camera1 - * - * @param[in] src camera1 pixel data source options - */ -void pixelmux_cam1_data_source_enable(pixelmux_cam1_select_t src); - -/** - * @brief disable camera1 pixel data source - */ -void pixelmux_cam1_data_source_disable(void); - -/** - * @brief select pixel data source and enable for camera0 - * - * @param[in] src camera0 pixel data source options - */ -void pixelmux_cam0_data_source_enable(pixelmux_cam0_select_t src); - -/** - * @brief disable camera0 pixel data source - */ -void pixelmux_cam0_data_source_disable(void); - -/** - * @brief calculate pll config base pixel frequency - * - * @param[in] pixel_freq_hz lcdc pixel frequency - * @param[in] is_split 1: enable split mode, 0: disable split mode - * @param[out] param use for lvds phy config - * @return status - */ -hpm_stat_t pixelmux_lvds_phy_calc_pll_cfg(uint32_t pixel_freq_hz, bool is_split, lvds_phy_clk_param_t *param); - -/** - * @brief config tx phy0 mode - * - * @param[in] mode phy mode - */ -void pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_t mode); - -/** - * @brief config tx phy1 mode - * - * @param[in] mode phy mode - */ -void pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_t mode); - -/** - * @brief config lvds tx phy0 clock - * - * @param[in] clk_reg phy register config - */ -void pixelmux_config_lvds_tx_phy0_clk(const lvds_phy_clk_reg_t *clk_reg); - -/** - * @brief config lvds tx phy1 clock - * - * @param[in] clk_reg phy register config - */ -void pixelmux_config_lvds_tx_phy1_clk(const lvds_phy_clk_reg_t *clk_reg); - -/** - * @brief config rx phy0 mode - * - * @param[in] mode phy mode - */ -void pixelmux_config_rx_phy0_mode(pixelmux_rx_phy_mode_t mode); - -/** - * @brief config rx phy1 mode - * - * @param[in] mode phy mode - */ -void pixelmux_config_rx_phy1_mode(pixelmux_rx_phy_mode_t mode); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_PIXELMUX_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h deleted file mode 100644 index 33f7f814d55..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pla_drv.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLA_DRV_H -#define HPM_PLA_DRV_H - -#include "hpm_common.h" -#include "hpm_pla_regs.h" - -/** - * @brief PLA driver APIs - * @defgroup pla_interface PLA driver APIs - * @ingroup io_interfaces - * @{ - */ - -#define PLA_AOI_16TO8_SIGNAL_NUM (16U) -#define PLA_AOI_8TO7_SIGNAL_NUM (8U) -#define PLA_CHN_CFG_ACTIVE_WORD (0xF00DU) - -#define PLA_AOI_16TO8_CONNECT_(input, value) \ - PLA_CHN_AOI_16TO8_AOI_16TO8_##input##_SET(value) -/** - * @brief Input signal configuration for synthetic aoi_16to8 - * - */ -#define PLA_AOI_16TO8_CONNECT(input_signal, operation) \ - PLA_AOI_16TO8_CONNECT_(input_signal, operation) - -/** - * @brief aoi_16to8 operation on input signals - * - */ -typedef enum pla_aoi_signal_operation_type { - pla_aoi_operation_and_0 = 0, /**< signal & 0 */ - pla_aoi_operation_and_1 = 1, /**< signal & 1 */ - pla_aoi_operation_xor_1 = 2, /**< signal xor 1 */ - pla_aoi_operation_or_1 = 3, /**< signal | 1 */ -} pla_aoi_signal_operation_type_t; - -typedef enum pla_filter_sw_inject_type { - pla_filter_sw_inject_low = 0, - pla_filter_sw_inject_height = 1, - pla_filter_sw_inject_disable = 2, -} pla_filter_sw_inject_type_t; - -/** - * @brief aoi channel index - * - */ -typedef enum pla_channel_type { - pla_chn_0 = PLA_CHN_0, /**< channel 0 */ - pla_chn_1 = PLA_CHN_1, /**< channel 1 */ - pla_chn_2 = PLA_CHN_2, /**< channel 2 */ - pla_chn_3 = PLA_CHN_3, /**< channel 3 */ - pla_chn_4 = PLA_CHN_4, /**< channel 4 */ - pla_chn_5 = PLA_CHN_5, /**< channel 5 */ - pla_chn_6 = PLA_CHN_6, /**< channel 6 */ - pla_chn_7 = PLA_CHN_7, /**< channel 7 */ -} pla_channel_type_t; - -/** - * @brief Raw input signal for aoi16to8 module - * - */ -typedef enum pla_aoi_16to8_input_signal_type { - pla_level1_filter_out_0 = 0, - pla_level1_filter_out_1 = 1, - pla_level1_filter_out_2 = 2, - pla_level1_filter_out_3 = 3, - pla_level1_filter_out_4 = 4, - pla_level1_filter_out_5 = 5, - pla_level1_filter_out_6 = 6, - pla_level1_filter_out_7 = 7, - pla_level1_filter_out_8 = 8, - pla_level1_filter_out_9 = 9, - pla_level1_filter_out_10 = 10, - pla_level1_filter_out_11 = 11, - pla_level1_filter_out_12 = 12, - pla_level1_filter_out_13 = 13, - pla_level1_filter_out_14 = 14, - pla_level1_filter_out_15 = 15, -} pla_aoi_16to8_input_signal_type_t; - -/** - * @brief aoi_16to8 channel index - * - */ -typedef enum pla_aoi_16to8_channel_type { - pla_aoi_16to8_chn_0 = PLA_CHN_AOI_16TO8_AOI_16TO8_00, /**< channel 0 */ - pla_aoi_16to8_chn_1 = PLA_CHN_AOI_16TO8_AOI_16TO8_01, /**< channel 1 */ - pla_aoi_16to8_chn_2 = PLA_CHN_AOI_16TO8_AOI_16TO8_02, /**< channel 2 */ - pla_aoi_16to8_chn_3 = PLA_CHN_AOI_16TO8_AOI_16TO8_03, /**< channel 3 */ - pla_aoi_16to8_chn_4 = PLA_CHN_AOI_16TO8_AOI_16TO8_04, /**< channel 4 */ - pla_aoi_16to8_chn_5 = PLA_CHN_AOI_16TO8_AOI_16TO8_05, /**< channel 5 */ - pla_aoi_16to8_chn_6 = PLA_CHN_AOI_16TO8_AOI_16TO8_06, /**< channel 6 */ - pla_aoi_16to8_chn_7 = PLA_CHN_AOI_16TO8_AOI_16TO8_07, /**< channel 7 */ -} pla_aoi_16to8_channel_type_t; - -/** - * @brief aoi_16to8 config unit - * - */ -typedef struct pla_aoi_16to8_cfg_unit { - pla_aoi_16to8_input_signal_type_t signal; - pla_aoi_signal_operation_type_t op; -} pla_aoi_16to8_cfg_unit_t; - -/** - * @brief aoi_16to8 channel config - * - */ -typedef struct pla_aoi_16to8_chn_cfg { - pla_channel_type_t chn; /**< pla channel */ - pla_aoi_16to8_channel_type_t aoi_16to8_chn; /**< aoi_16to8 channel */ - pla_aoi_16to8_cfg_unit_t input[PLA_AOI_16TO8_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */ -} pla_aoi_16to8_chn_cfg_t; - -/** - * @brief aoi_8_to_7 input signal - * - */ -typedef enum pla_aoi_8to7_input_signal_type { - pla_level2_filter_out_0 = 0, - pla_level2_filter_out_1 = 1, - pla_level2_filter_out_2 = 2, - pla_level2_filter_out_3 = 3, - pla_level2_filter_out_4 = 4, - pla_level2_filter_out_5 = 5, - pla_level2_filter_out_6 = 6, - pla_level2_filter_out_7 = 7, -} pla_aoi_8to7_input_signal_type_t; - -/** - * @brief aoi_8to7 channel number - * - */ -typedef enum pla_aoi_8to7_channel_type { - pla_aoi_8to7_chn_0 = 0, /**< channel 0 */ - pla_aoi_8to7_chn_1 = 1, /**< channel 1 */ - pla_aoi_8to7_chn_2 = 2, /**< channel 2 */ - pla_aoi_8to7_chn_3 = 3, /**< channel 3 */ - pla_aoi_8to7_chn_4 = 4, /**< channel 4 */ - pla_aoi_8to7_chn_5 = 5, /**< channel 5 */ - pla_aoi_8to7_chn_6 = 6, /**< channel 6 */ -} pla_aoi_8to7_channel_type_t; - - -/** - * @brief aoi_8to7 config unit - * - */ -typedef struct pla_aoi_8to7_cfg_unit { - pla_aoi_8to7_input_signal_type_t signal; - pla_aoi_signal_operation_type_t op; -} pla_aoi_8to7_cfg_unit_t; - -/** - * @brief aoi_8_to_7 channel config - * - */ -typedef struct pla_aoi_8to7_chn_cfg { - pla_channel_type_t chn; /**< pla channel */ - pla_aoi_8to7_channel_type_t aoi_8to7_chn; /**< aoi_16to8 channel */ - pla_aoi_8to7_cfg_unit_t input[PLA_AOI_8TO7_SIGNAL_NUM]; /**< Configuration of each aoi_16to8 input signal */ -} pla_aoi_8to7_chn_cfg_t; - -/** - * @brief pla filter config - * - */ -typedef union pla_filter_cfg { - struct { - uint32_t sync_edge_filter_disable:1; - uint32_t software_inject:2; - uint32_t filter_reverse:1; - uint32_t edge_dect_en:1; - uint32_t nege_edge_dect_en:1; - uint32_t pose_edge_dect_en:1; - uint32_t filter_sync_level:1; - uint32_t filter_ext_en:1; - uint32_t reserved0:3; - uint32_t filter_ext_type:3; - uint32_t reserved1:1; - uint32_t filter_ext_counter:16; - }; - uint32_t val; -} pla_filter_cfg_t; - -/** - * @brief pla function selection config - * - */ -typedef union pla_ff_cfg { - struct { - uint32_t sel_cfg_ff_type:3; - uint32_t sel_clk_source:1; - uint32_t sel_adder_minus:1; - uint32_t reserved0:11; - uint32_t dis_osc_loop_clamp:1; - uint32_t osc_loop_clamp_value:1; - uint32_t reserved1:14; - }; - uint32_t val; -} pla_ff_cfg_t; - -/** - * @brief pla configurable functions - * - */ -typedef enum pla_ff_type { - pla_ff_type_dff = 0, - pla_ff_type_level3_filter0 = 1, - pla_ff_type_dual_edge_DFF = 2, - pla_ff_type_trigger_ff = 3, - pla_ff_type_jk_ff = 4, - pla_ff_type_latch = 5, - pla_ff_type_adder_minus = 6 -} pla_ff_type_t; - - -typedef enum pla_filter1_inchannel_type { - pla_filter1_inchn0 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0, - pla_filter1_inchn1 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1, - pla_filter1_inchn2 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2, - pla_filter1_inchn3 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3, - pla_filter1_inchn4 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4, - pla_filter1_inchn5 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5, - pla_filter1_inchn6 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6, - pla_filter1_inchn7 = PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7, -} pla_filter1_inchannel_type_t; - -typedef enum pla_filter1_outchannel_type { - pla_filter1_outchn0 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0, - pla_filter1_outchn1 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1, - pla_filter1_outchn2 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2, - pla_filter1_outchn3 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3, - pla_filter1_outchn4 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4, - pla_filter1_outchn5 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5, - pla_filter1_outchn6 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6, - pla_filter1_outchn7 = PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7, -} pla_filter1_outchannel_type_t; - - -typedef enum pla_filter2_channel_type { - pla_filter2_chn0 = PLA_CHN_FILTER_2ND_SECOND_FILTER_0, - pla_filter2_chn1 = PLA_CHN_FILTER_2ND_SECOND_FILTER_1, - pla_filter2_chn2 = PLA_CHN_FILTER_2ND_SECOND_FILTER_2, - pla_filter2_chn3 = PLA_CHN_FILTER_2ND_SECOND_FILTER_3, - pla_filter2_chn4 = PLA_CHN_FILTER_2ND_SECOND_FILTER_4, - pla_filter2_chn5 = PLA_CHN_FILTER_2ND_SECOND_FILTER_5, - pla_filter2_chn6 = PLA_CHN_FILTER_2ND_SECOND_FILTER_6, - pla_filter2_chn7 = PLA_CHN_FILTER_2ND_SECOND_FILTER_7, -} pla_filter2_channel_type_t; - -typedef enum pla_filter3_channel_type { - pla_filter3_chn0 = PLA_CHN_FILTER_3RD_THIRD_FILTER_0, - pla_filter3_chn1 = PLA_CHN_FILTER_3RD_THIRD_FILTER_1, - pla_filter3_chn2 = PLA_CHN_FILTER_3RD_THIRD_FILTER_2, - pla_filter3_chn3 = PLA_CHN_FILTER_3RD_THIRD_FILTER_3, - pla_filter3_chn4 = PLA_CHN_FILTER_3RD_THIRD_FILTER_4, - pla_filter3_chn5 = PLA_CHN_FILTER_3RD_THIRD_FILTER_5, - pla_filter3_chn6 = PLA_CHN_FILTER_3RD_THIRD_FILTER_6, -} pla_filter3_channel_type_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Configure one channel of aoi_16to8 - * - * @param pla @ref PLA_Type - * @param cfg @ref pla_aoi_16to8_chn_cfg_t - */ -void pla_set_aoi_16to8_one_channel(PLA_Type * pla, - pla_aoi_16to8_chn_cfg_t *cfg); - -/** - * @brief Get one channel of aoi_16to8 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t - * @param cfg @ref pla_aoi_16to8_chn_cfg_t - */ -void pla_get_aoi_16to8_one_channel(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_16to8_channel_type_t aoi_16to8_chn, - pla_aoi_16to8_chn_cfg_t *cfg); - -/** - * @brief Set one signal of aoi_16to8 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t - * @param cfg @ref pla_aoi_16to8_cfg_unit_t - */ -static inline void pla_set_aoi_16to8_input_signal(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_16to8_channel_type_t aoi_16to8_chn, - pla_aoi_16to8_cfg_unit_t *cfg) -{ - pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] = pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] & - ~(((uint32_t)cfg->op) << (cfg->signal << 1)); -} - -/** - * @brief Get one signal of aoi_16to8 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param aoi_16to8_chn @ref pla_aoi_16to8_channel_type_t - * @param signal @ref pla_aoi_16to8_input_signal_type_t - * @param cfg @ref pla_aoi_16to8_cfg_unit_t - */ -static inline void pla_get_aoi_16to8_input_signal(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_16to8_channel_type_t aoi_16to8_chn, - pla_aoi_16to8_input_signal_type_t signal, - pla_aoi_16to8_cfg_unit_t *cfg) -{ - cfg->op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (signal << 1)) & 0x03; - cfg->signal = signal; -} - - -/** - * @brief Configure one channel of aoi_8to7 - * - * @param pla @ref PLA_Type - * @param cfg @ref pla_aoi_8to7_chn_cfg_t - */ -void pla_set_aoi_8to7_one_channel(PLA_Type *pla, - pla_aoi_8to7_chn_cfg_t *cfg); - -/** - * @brief Get one channel of aoi_8to7 - * - * @param pla @ref PLA_Type - * @param cfg @ref pla_aoi_8to7_chn_cfg_t - */ -void pla_get_aoi_8to7_one_channel(PLA_Type *pla, - pla_aoi_8to7_chn_cfg_t *cfg); - -/** - * @brief Configure one signal of aoi_8to7 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param aoi_8to7_chn @ref pla_aoi_8to7_channel_type_t - * @param cfg @ref pla_aoi_8to7_cfg_unit_t - */ -void pla_set_aoi_8to7_input_signal(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_8to7_channel_type_t aoi_8to7_chn, - pla_aoi_8to7_cfg_unit_t *cfg); - -/** - * @brief Get one signal of aoi_8to7 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param aoi_8to7_chn @ref pla_aoi_8to7_channel_type_t - * @param signal @ref pla_aoi_8to7_input_signal_type_t - * @param cfg @ref pla_aoi_8to7_cfg_unit_t - */ -void pla_get_aoi_8to7_input_signal(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_8to7_channel_type_t aoi_8to7_chn, - pla_aoi_8to7_input_signal_type_t signal, - pla_aoi_8to7_cfg_unit_t *cfg); - -/** - * @brief Configure filter1 out - * - * @param pla @ref PLA_Type - * @param filter1_out_chn @ref pla_filter1_outchannel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_set_filter1_out(PLA_Type *pla, - pla_filter1_outchannel_type_t filter1_out_chn, - pla_filter_cfg_t *cfg) -{ - pla->FILTER_1ST_PLA_OUT[filter1_out_chn] = cfg->val; -} - -/** - * @brief Get filter1 out - * - * @param pla @ref PLA_Type - * @param filter1_out_chn @ref pla_filter1_outchannel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_get_filter1_out(PLA_Type *pla, - pla_filter1_outchannel_type_t filter1_out_chn, - pla_filter_cfg_t *cfg) -{ - cfg->val = pla->FILTER_1ST_PLA_OUT[filter1_out_chn]; -} - -/** - * @brief Configure filter1 in - * - * @param pla @ref PLA_Type - * @param filter1_in_chn @ref pla_filter1_inchannel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_set_filter1_in(PLA_Type *pla, - pla_filter1_inchannel_type_t filter1_in_chn, - pla_filter_cfg_t *cfg) -{ - pla->FILTER_1ST_PLA_IN[filter1_in_chn] = cfg->val; -} - -/** - * @brief Get filter 1 - * - * @param pla @ref PLA_Type - * @param filter1_in_chn @ref pla_filter1_inchannel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_get_filter1_in(PLA_Type *pla, - pla_filter1_inchannel_type_t filter1_in_chn, - pla_filter_cfg_t *cfg) -{ - cfg->val = pla->FILTER_1ST_PLA_IN[filter1_in_chn]; -} - -/** - * @brief Configure filter 2 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param filter2_chn @ref pla_filter2_channel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_set_filter2(PLA_Type *pla, - pla_channel_type_t chn, - pla_filter2_channel_type_t filter2_chn, - pla_filter_cfg_t *cfg) -{ - pla->CHN[chn].FILTER_2ND[filter2_chn] = cfg->val; -} - -/** - * @brief Get filter2 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param filter2_chn @ref pla_filter2_channel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_get_filter2(PLA_Type *pla, - pla_channel_type_t chn, - pla_filter2_channel_type_t filter2_chn, - pla_filter_cfg_t *cfg) -{ - cfg->val = pla->CHN[chn].FILTER_2ND[filter2_chn]; -} - -/** - * @brief Configure filter3 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param filter3_chn @ref pla_filter3_channel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_set_filter3(PLA_Type *pla, - pla_channel_type_t chn, - pla_filter3_channel_type_t filter3_chn, - pla_filter_cfg_t *cfg) -{ - pla->CHN[chn].FILTER_3RD[filter3_chn] = cfg->val; -} - -/** - * @brief Get filter3 - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param filter3_chn @ref pla_filter3_channel_type_t - * @param cfg @ref pla_filter_cfg_t - */ -static inline void pla_get_filter3(PLA_Type *pla, - pla_channel_type_t chn, - pla_filter3_channel_type_t filter3_chn, - pla_filter_cfg_t *cfg) -{ - cfg->val = pla->CHN[chn].FILTER_3RD[filter3_chn]; -} - -/** - * @brief Set ff function - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param cfg @ref pla_ff_cfg_t - */ -static inline void pla_set_ff(PLA_Type *pla, - pla_channel_type_t chn, - pla_ff_cfg_t *cfg) -{ - pla->CHN[chn].CFG_FF = cfg->val; -} - -/** - * @brief Get ff function - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - * @param cfg @ref pla_ff_cfg_t - */ -static inline void pla_get_ff(PLA_Type *pla, - pla_channel_type_t chn, - pla_ff_cfg_t *cfg) -{ - cfg->val = pla->CHN[chn].CFG_FF; -} - -/** - * @brief enable pla channel - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - */ -static inline void pla_channel_enable(PLA_Type *pla, - pla_channel_type_t chn) -{ - pla->CHN_CFG_ACTIVE[chn] = PLA_CHN_CFG_ACTIVE_WORD; -} - -/** - * @brief disable pla channel - * - * @param pla @ref PLA_Type - * @param chn @ref pla_channel_type_t - */ -static inline void pla_channel_disable(PLA_Type *pla, - pla_channel_type_t chn) -{ - pla->CHN_CFG_ACTIVE[chn] = false; -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_PLA_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h deleted file mode 100644 index fce55f65d5d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLB_DRV_H -#define HPM_PLB_DRV_H - -#include "hpm_common.h" -#include "hpm_plb_regs.h" - -/** - * @brief PLB driver APIs - * @defgroup plb_interface PLB driver APIs - * @ingroup io_interfaces - * @{ - */ - -#define PLB_SLICE_MASK (0xf) -#define PLB_SLICE_HIGH_BIT_MASK_SET(slice) (PLB_SLICE_MASK << ((slice - plb_type_b_slice_8) << 2)) -#define PLB_SLICE_HIGH_BIT_SHIFT(slice) ((slice - plb_type_b_slice_8) << 2) -#define PLB_SLICE_LOW_BIT_MASK_SET(slice) (PLB_SLICE_MASK << (slice << 2)) -#define PLB_SLICE_LOW_BIT_SHIFT(slice) (slice << 2) - -/** - * @brief plb channels - * - */ -typedef enum plb_chn { -#ifdef PLB_TYPE_B_0 - plb_chn0 = PLB_TYPE_B_0, -#endif -#ifdef PLB_TYPE_B_1 - plb_chn1 = PLB_TYPE_B_1, -#endif -#ifdef PLB_TYPE_B_2 - plb_chn2 = PLB_TYPE_B_2, -#endif -#ifdef PLB_TYPE_B_3 - plb_chn3 = PLB_TYPE_B_3, -#endif -#ifdef PLB_TYPE_B_4 - plb_chn4 = PLB_TYPE_B_4, -#endif -#ifdef PLB_TYPE_B_5 - plb_chn5 = PLB_TYPE_B_5, -#endif -#ifdef PLB_TYPE_B_6 - plb_chn6 = PLB_TYPE_B_6, -#endif -#ifdef PLB_TYPE_B_7 - plb_chn7 = PLB_TYPE_B_7, -#endif -} plb_chn_t; - -/** - * @brief PLB look-up table unit - * - */ -typedef enum plb_type_a_lut_num { -#ifdef PLB_TYPE_A_0 - plb_type_a_table0 = PLB_TYPE_A_0, -#endif -#ifdef PLB_TYPE_A_1 - plb_type_a_table1 = PLB_TYPE_A_1, -#endif -#ifdef PLB_TYPE_A_2 - plb_type_a_table2 = PLB_TYPE_A_2, -#endif -#ifdef PLB_TYPE_A_3 - plb_type_a_table3 = PLB_TYPE_A_3, -#endif -#ifdef PLB_TYPE_A_4 - plb_type_a_table4 = PLB_TYPE_A_4, -#endif -#ifdef PLB_TYPE_A_5 - plb_type_a_table5 = PLB_TYPE_A_5, -#endif -#ifdef PLB_TYPE_A_6 - plb_type_a_table6 = PLB_TYPE_A_6, -#endif -#ifdef PLB_TYPE_A_7 - plb_type_a_table7 = PLB_TYPE_A_7, -#endif -} plb_type_a_lut_num_t; - -/** - * @brief PLB truth table configuration unit - * - */ -typedef union { - struct { - uint16_t index0_1bit_out: 1; - uint16_t index1_1bit_out: 1; - uint16_t index2_1bit_out: 1; - uint16_t index3_1bit_out: 1; - uint16_t index4_1bit_out: 1; - uint16_t index5_1bit_out: 1; - uint16_t index6_1bit_out: 1; - uint16_t index7_1bit_out: 1; - uint16_t index8_1bit_out: 1; - uint16_t index9_1bit_out: 1; - uint16_t index10_1bit_out: 1; - uint16_t index11_1bit_out: 1; - uint16_t index12_1bit_out: 1; - uint16_t index13_1bit_out: 1; - uint16_t index14_1bit_out: 1; - uint16_t index15_1bit_out: 1; - }; - uint16_t val; -} plb_type_a_truth_t; - -/** - * @brief Index of slice - * - */ -typedef enum plb_type_b_lut_slice { - plb_type_b_slice_0 = 0, - plb_type_b_slice_1 = 1, - plb_type_b_slice_2 = 2, - plb_type_b_slice_3 = 3, - plb_type_b_slice_4 = 4, - plb_type_b_slice_5 = 5, - plb_type_b_slice_6 = 6, - plb_type_b_slice_7 = 7, - plb_type_b_slice_8 = 8, - plb_type_b_slice_9 = 9, - plb_type_b_slice_10 = 10, - plb_type_b_slice_11 = 11, - plb_type_b_slice_12 = 12, - plb_type_b_slice_13 = 13, - plb_type_b_slice_14 = 14, - plb_type_b_slice_15 = 15, -} plb_type_b_lut_slice_t; - -/** - * @brief Configuration of slice - * - */ -typedef enum plb_type_b_slice_opt { - plb_slice_opt_keep = 0, /**< The data unit keeps the value of the previous cycle */ - plb_slice_opt_get_cmp0_val = 1, /**< The data unit will take the value of the cmp0 register as the value for the next cycle */ - plb_slice_opt_get_cmp1_val = 2, /**< The data unit will take the value of the cmp1 register as the value for the next cycle */ - plb_slice_opt_get_cmp2_val = 3, /**< The data unit will take the value of the cmp2 register as the value for the next cycle */ - plb_slice_opt_add_one = 4, /**< The next cycle value of the data cell is the current value plus 1 */ - plb_slice_opt_add_two = 5, /**< The next cycle value of the data cell is the current value plus 2 */ - plb_slice_opt_sub_one = 6, /**< The next cycle value of the data cell is the current value minus 1 */ - plb_slice_opt_sub_two = 7, /**< The next cycle value of the data cell is the current value minus 2 */ - plb_slice_opt_shift_left = 4 << 8, /**< The value of the next cycle of the data cell is shifted one place to the left of the current value */ - plb_slice_opt_shift_left_add_one = 5 << 8, /**< The next cycle value of the data cell is the current value shifted one place to the left, with the lower bit complemented by one */ - plb_slice_opt_shift_right = 6 << 8, /**< The value of the next cycle of the data cell is shifted one place to the right of the current value */ - plb_slice_opt_shift_right_add_one = 7 << 8, /**< The next cycle value of the data cell is the current value shifted one place to the right, with the lower bit complemented by one */ -} plb_type_b_slice_opt_t; - -/** - * @brief Comparator index - * - */ -typedef enum plb_type_b_cmp { - plb_type_b_cmp0 = PLB_TYPE_B_CMP_0, - plb_type_b_cmp1 = PLB_TYPE_B_CMP_1, - plb_type_b_cmp2 = PLB_TYPE_B_CMP_2, - plb_type_b_cmp3 = PLB_TYPE_B_CMP_3, -} plb_type_b_cmp_t; - -/** - * @brief Comparator operation - * - */ -typedef enum plb_type_b_cmp_mode { - plb_cmp_mode_out_zero = 0, /**< output zero */ - plb_cmp_mode_out_one = 1, /**< output one */ - plb_cmp_mode_gt = 2, /**< Data unit greater than cmp output one, otherwise output zero */ - plb_cmp_mode_lt = 3, /**< Data unit less than cmp output one, otherwise output zero */ - plb_cmp_mode_eq = 4, /**< Data unit equal to cmp output one, otherwise output zero */ - plb_cmp_mode_ne = 5, /**< Data unit not equal to cmp output one, otherwise output zero */ - plb_cmp_mode_ge = 6, /**< Data unit greater than or equal to cmp output one, otherwise output zero */ - plb_cmp_mode_le = 7, /**< Data unit less than or equal to cmp output one, otherwise output zero */ - plb_cmp_mode_and_mask = 10, /**< The data cell corresponding to the bit set to one by cmp is and */ - plb_cmp_mode_or_mask = 11, /**< The data cell corresponding to the bit set to one by cmp is or */ - plb_cmp_mode_xor_mask = 12, /**< The data cell corresponding to the bit set to one by cmp is xor */ - plb_cmp_mode_nand_mask = 13, /**< The data cell corresponding to the bit set to one by cmp is nand */ - plb_cmp_mode_nor_mask = 14, /**< The data cell corresponding to the bit set to one by cmp is nor */ - plb_cmp_mode_xnor_mask = 15, /**< The data cell corresponding to the bit set to one by cmp is xnor */ -} plb_type_b_cmp_mode_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Configuring the truth table for lookup tables - * - * @param plb @ref PLB_Type plb base - * @param chn @ref plb_chn_t - * @param lut_num @ref plb_type_a_lut_num_t - * @param truth @ref plb_type_a_truth_t - */ -static inline void plb_type_a_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_a_lut_num_t lut_num, plb_type_a_truth_t *truth) -{ - plb->TYPE_A[chn].LOOKUP_TABLE[lut_num] = PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(truth->val); -} - -/** - * @brief The software injects a cycle value into the TYPE A channel. - * - * @param plb @ref PLB_Type plb base - * @param chn @ref plb_chn_t - * @param inject_val Injected values - */ -static inline void plb_type_a_inject_by_sw(PLB_Type *plb, plb_chn_t chn, uint8_t inject_val) -{ - plb->TYPE_A[chn].SW_INJECT = PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(inject_val); -} - -/** - * @brief Configure the value of the CMP - * - * @param plb @ref PLB_Type plb base - * @param chn @ref plb_chn_t - * @param cmp_index @ref plb_type_b_cmp_t - * @param val CMP value - */ -static inline void plb_type_b_set_cmp_val(PLB_Type *plb, plb_chn_t chn, plb_type_b_cmp_t cmp_index, uint32_t val) -{ - plb->TYPE_B[chn].CMP[cmp_index] = PLB_TYPE_B_CMP_CMP_VALUE_SET(val); -} - -/** - * @brief Setting the mode of the CMP - * - * @param plb @ref PLB_Type plb base - * @param chn @ref plb_chn_t - * @param cmp_index @ref plb_type_b_cmp_t - * @param cmp_mode @ref plb_type_b_cmp_mode_t - */ -static inline void plb_type_b_set_cmp_mode(PLB_Type *plb, plb_chn_t chn, plb_type_b_cmp_t cmp_index, plb_type_b_cmp_mode_t cmp_mode) -{ - plb->TYPE_B[chn].MODE = (plb->TYPE_B[chn].MODE & (~(PLB_TYPE_B_MODE_OUT0_SEL_MASK << (cmp_index << 2)))) | - ((PLB_TYPE_B_MODE_OUT0_SEL_MASK & cmp_mode) << (cmp_index << 2)); -} - -/** - * @brief Software injection values - * - * @param plb @ref PLB_Type plb base - * @param chn @ref plb_chn_t - * @param val value - */ -static inline void plb_type_b_inject_by_sw(PLB_Type *plb, plb_chn_t chn, uint32_t val) -{ - plb->TYPE_B[chn].SW_INJECT = val; -} - -/** - * @brief Configuring the PLB type_b's lookup table - * - * @param plb @ref PLB_Type plb base - * @param chn @ref plb_chn_t - * @param slice @ref plb_type_b_lut_slice_t - * @param opt @ref plb_type_b_slice_opt_t - */ -void plb_type_b_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_b_lut_slice_t slice, plb_type_b_slice_opt_t opt); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_PLB_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h deleted file mode 100644 index c601e88f4db..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctl_drv.h +++ /dev/null @@ -1,458 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLLCTL_DRV_H -#define HPM_PLLCTL_DRV_H -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_pllctl_regs.h" - -/** - * - * @brief PLLCTL driver APIs - * @defgroup pllctl_interface PLLCTL driver APIs - * @{ - */ - -#define PLLCTL_PLL_VCO_FREQ_MIN (375000000U) -#define PLLCTL_PLL_VCO_FREQ_MAX (2200000000U) - -/* - * @brief PLL parts with lock - */ -#define PLLCTL_PLL_LOCK_SS_RESET PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK -#define PLLCTL_PLL_LOCK_REFDIV PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK -#define PLLCTL_PLL_LOCK_POSTDIV1 PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK -#define PLLCTL_PLL_LOCK_SS_SPREAD PLLCTL_PLL_LOCK_LOCK_SS_SPREAD_MASK -#define PLLCTL_PLL_LOCK_SS_DIVVAL PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK -#define PLLCTL_PLL_LOCK_ALL (PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK \ - | PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK \ - | PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK \ - | PLLCTL_PLL_LOCK_LOCK_SS_SPREAD_MASK \ - | PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK \ - | PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) - -/* - * @brief PLLCTL specific status - */ -enum { - status_pllctl_not_enabled = MAKE_STATUS(status_group_pllctl, 1), - status_pllctl_out_of_range = MAKE_STATUS(status_group_pllctl, 2), -}; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Unlock pll - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] lock_mask Mask of PLL parts to be unlocked - */ -static inline void pllctl_pll_unlock(PLLCTL_Type *ptr, uint8_t pll, uint32_t lock_mask) -{ - ptr->PLL[pll].LOCK &= ~lock_mask; -} - -/** - * @brief Lock pll - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] lock_mask Mask of PLL parts to be locked - */ - -static inline void pllctl_pll_lock(PLLCTL_Type *ptr, uint8_t pll, uint32_t lock_mask) -{ - ptr->PLL[pll].LOCK = lock_mask; -} - -/** - * @brief Disable spread spectrum - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_pll_ss_disable(PLLCTL_Type *ptr, uint8_t pll) -{ - if (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) { - return status_invalid_argument; - } - - ptr->PLL[pll].CFG0 |= (PLLCTL_PLL_CFG0_SS_RSTPTR_MASK - | PLLCTL_PLL_CFG0_SS_RESET_MASK); - ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; - return status_success; -} - -/** - * @brief Power down target PLL - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_pll_powerdown(PLLCTL_Type *ptr, uint8_t pll) -{ - if (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) { - return status_invalid_argument; - } - - ptr->PLL[pll].CFG1 = (ptr->PLL[pll].CFG1 & - ~(PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK | PLLCTL_PLL_CFG1_CLKEN_SW_MASK)) - | PLLCTL_PLL_CFG1_PLLPD_SW_MASK; - return status_success; -} - -/** - * @brief Power on target PLL - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_pll_poweron(PLLCTL_Type *ptr, uint8_t pll) -{ - uint32_t cfg; - if (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) { - return status_invalid_argument; - } - - cfg = ptr->PLL[pll].CFG1; - if (!(cfg & PLLCTL_PLL_CFG1_PLLPD_SW_MASK)) { - return status_success; - } - - if (cfg & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) { - ptr->PLL[pll].CFG1 &= ~PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK; - } - - ptr->PLL[pll].CFG1 &= ~PLLCTL_PLL_CFG1_PLLPD_SW_MASK; - - /* - * put back to hardware mode - */ - ptr->PLL[pll].CFG1 |= PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK; - return status_success; -} - -/** - * @brief Enable spread spectrum mode - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] spread Spread spectrum depth (1-31, from 0.1% to 3.1%) - * @param[in] div Spread spectrum divider (1-63, divide by 1 to 63) - * @param[in] down_spread Set true if need down-spread, otherwise center-spread - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_pll_ss_enable(PLLCTL_Type *ptr, uint8_t pll, - uint8_t spread, uint8_t div, - bool down_spread) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || (spread > (PLLCTL_PLL_CFG0_SS_SPREAD_MASK >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT)) - || (div > (PLLCTL_PLL_CFG0_SS_DIVVAL_MASK >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT))) { - return status_invalid_argument; - } - if (!(ptr->PLL[pll].CFG1 & PLLCTL_PLL_CFG1_PLLPD_SW_MASK)) { - pllctl_pll_powerdown(ptr, pll); - } - - ptr->PLL[pll].CFG0 &= ~(PLLCTL_PLL_CFG0_SS_RSTPTR_MASK - | PLLCTL_PLL_CFG0_SS_RESET_MASK); - ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK; - ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 - & ~(PLLCTL_PLL_CFG0_SS_SPREAD_MASK | PLLCTL_PLL_CFG0_SS_DIVVAL_MASK)) - | PLLCTL_PLL_CFG0_SS_SPREAD_SET(spread) - | PLLCTL_PLL_CFG0_SS_DIVVAL_SET(div) - | PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET(down_spread); - - pllctl_pll_poweron(ptr, pll); - return status_success; -} - -/** - * @brief Set postdiv1 for PLL - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] div Postdiv1 value (0x1~0x7) - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_set_postdiv1(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || (!div) - || ((div) > (PLLCTL_PLL_CFG0_POSTDIV1_MASK >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT))) { - return status_invalid_argument; - } - - ptr->PLL[pll].CFG0 = ((ptr->PLL[pll].CFG0 & ~(PLLCTL_PLL_CFG0_POSTDIV1_MASK))) | PLLCTL_PLL_CFG0_POSTDIV1_SET(div); - return status_success; -} - -/** - * @brief Set fbdiv for PLL integer mode - * - * Fout = Fref/refdiv * fbdiv / postdiv1 - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] fbdiv Fbdiv value (0x1~0x1000) - * @note fbdiv value can not set too large, if Fref/refdiv * fbdiv > 2GHz, it might cause irrecoverable damage to that PLL - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_set_fbdiv_int(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || ((fbdiv - 1) > (uint16_t)(PLLCTL_PLL_CFG2_FBDIV_INT_MASK >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT))) { - return status_invalid_argument; - } - - ptr->PLL[pll].CFG2 = ((ptr->PLL[pll].CFG2 & ~(PLLCTL_PLL_CFG2_FBDIV_INT_MASK))) | PLLCTL_PLL_CFG2_FBDIV_INT_SET(fbdiv - 1); - return status_success; -} - -/** - * @brief Set fbdiv for PLL fraction mode - * - * Fout = Fref/refdive * (fbdiv + frac/2^24)/postdiv1 - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] fbdiv Fbdiv value (0x1~0x1000) - * @note fbdiv value can not set too large, if Fref/refdiv * fbdiv > 2GHz, it might cause irrecoverable damage to that PLL - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_set_fbdiv_frac(PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || ((fbdiv - 1) > (uint16_t) (PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT))) { - return status_invalid_argument; - } - - ptr->PLL[pll].FREQ = (ptr->PLL[pll].FREQ & ~(PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK)) - | PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(fbdiv - 1); - return status_success; -} - -/** - * @brief Set fraction for PLL fraction mode - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] frac 24-bit fixed float point value - * - * @return - */ -static inline hpm_stat_t pllctl_set_frac(PLLCTL_Type *ptr, uint8_t pll, uint32_t frac) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || (frac > (PLLCTL_PLL_FREQ_FRAC_MASK >> PLLCTL_PLL_FREQ_FRAC_SHIFT))) { - return status_invalid_argument; - } - ptr->PLL[pll].FREQ = (ptr->PLL[pll].FREQ & ~(PLLCTL_PLL_FREQ_FRAC_MASK)) - | PLLCTL_PLL_FREQ_FRAC_SET(frac); - return status_success; -} - -/** - * @brief Get PLL divx value - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] div_index Target DIV to query - * - * @return Divider value of target DIV - */ -static inline hpm_stat_t pllctl_get_div(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || !(PLLCTL_SOC_PLL_HAS_DIV0(pll))) { - return status_invalid_argument; - } - if (div_index) { - return PLLCTL_PLL_DIV0_DIV_GET(ptr->PLL[pll].DIV1) + 1; - } else { - return PLLCTL_PLL_DIV0_DIV_GET(ptr->PLL[pll].DIV0) + 1; - } -} - -/** - * @brief Set divider - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] div_index DIV index - * @param[in] div Divider value (starting from 1) - * - * @return status_success if everything is okay - */ -static inline hpm_stat_t pllctl_set_div(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index, uint16_t div) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || !(PLLCTL_SOC_PLL_HAS_DIV0(pll)) - || ((div - 1) > (uint16_t) (PLLCTL_PLL_DIV0_DIV_MASK >> PLLCTL_PLL_DIV0_DIV_SHIFT))) { - return status_invalid_argument; - } - - if (div_index) { - ptr->PLL[pll].DIV1 = (ptr->PLL[pll].DIV1 & ~(PLLCTL_PLL_DIV1_DIV_MASK)) - | PLLCTL_PLL_DIV1_DIV_SET(div - 1); - } else { - ptr->PLL[pll].DIV0 = (ptr->PLL[pll].DIV0 & ~(PLLCTL_PLL_DIV0_DIV_MASK)) - | PLLCTL_PLL_DIV0_DIV_SET(div - 1); - } - return status_success; -} - -/** - * @brief Check if specific PLL DIV is stable - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] div_index Target DIV to check - * - * @return true if target PLL DIV is stable - */ -static inline bool pllctl_div_is_stable(PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) -{ - if ((pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) || !(PLLCTL_SOC_PLL_HAS_DIV0(pll))) { - return false; - } - if (div_index) { - return ptr->PLL[pll].DIV1 & PLLCTL_PLL_DIV0_RESPONSE_MASK; - } else { - return ptr->PLL[pll].DIV0 & PLLCTL_PLL_DIV0_RESPONSE_MASK; - } -} - -/** - * @brief Check if target PLL is enabled - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * - * @return true if target PLL is enabled - */ -static inline bool pllctl_pll_is_enabled(PLLCTL_Type *ptr, uint8_t pll) -{ - return (ptr->PLL[pll].STATUS & PLLCTL_PLL_STATUS_ENABLE_MASK); -} - -/** - * @brief Check if XTAL is stable - * - * @param[in] ptr PLLCTL base address - * - * @return true if XTAL is stable - */ -static inline bool pllctl_xtal_is_stable(PLLCTL_Type *ptr) -{ - return ptr->XTAL & PLLCTL_XTAL_RESPONSE_MASK; -} - -/** - * @brief Check if XTAL is enabled - * - * @param[in] ptr PLLCTL base address - * - * @return true if XTAL is enabled - */ -static inline bool pllctl_xtal_is_enabled(PLLCTL_Type *ptr) -{ - return ptr->XTAL & PLLCTL_XTAL_ENABLE_MASK; -} - -/* - * @brief set XTAL rampup time in cycles of IRC24M - * - * @param[in] ptr PLLCTL base address - */ -static inline void pllctl_xtal_set_rampup_time(PLLCTL_Type *ptr, uint32_t cycles) -{ - ptr->XTAL = (ptr->XTAL & ~PLLCTL_XTAL_RAMP_TIME_MASK) | PLLCTL_XTAL_RAMP_TIME_SET(cycles); -} - -/** - * @brief Set pll work mode - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] int_mode true: integer mode, false - fraction mode - * - * @return status_success if everything is okay - */ -hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode); - -/** - * @brief Set refdiv - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] div Divider value (0x1-0x3F) - * - * @return status_success if everything is okay - */ -hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div); - -/** - * @brief Initialize PLL working at integer mode with specific frequency - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] freq_in_hz Target frequency, expected >= 375000000Hz - * - * @return status_success if everything is okay - * - * @note The actual frequency might be slightly different from freq_in_hz due to calculation. - */ -hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, - uint32_t freq_in_hz); - -/** - * @brief Initialize PLL working at franction mode with specific frequency - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * @param[in] freq_in_hz Target frequency, expected >= 375000000Hz - * - * @return status_success if everything is okay - * @note The actual frequency might be slightly different from freq_in_hz due to calculation. - */ -hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, - uint32_t freq_in_hz); - -/** - * @brief Get frequency of target PLL - * - * @param[in] ptr PLLCTL base address - * @param[in] pll Target PLL index - * - * @return current frequency of target PLL in Hz - */ -uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_PLLCTL_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h deleted file mode 100644 index 7a010e80799..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLLCTLV2_DRV_H -#define HPM_PLLCTLV2_DRV_H - - -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_pllctlv2_regs.h" - -#define PLLCTLV2_CLK_SRC_XTAL24M (0U) -#define PLLCTLV2_CLK_SRC_IRC24M (1U) - -/** - * @brief PLLCTLV2 driver APIs - * @defgroup pllctlv2_interface PLLCTLV2 driver APIs - * @{ - */ - -/** - * @brief Check if external crystal is stable - * @param [in] ptr PLLCTLV2 base address - * @return true if external crystal is stable - */ -static inline bool pllctlv2_xtal_is_stable(PLLCTLV2_Type *ptr) -{ - return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_RESPONSE_MASK); -} - -/** - * @brief Check if external crystal is enabled - * @param [in] ptr PLLCTLV2 base address - * @return true if external crystal is enabled - */ -static inline bool pllctlv2_xtal_is_enabled(PLLCTLV2_Type *ptr) -{ - return IS_HPM_BITMASK_SET(ptr->XTAL, PLLCTLV2_XTAL_ENABLE_MASK); -} - -/** - * @brief Set external crystal ramp-up time - * @param [in] ptr PLLCTLV2 base address - * @param [in] rc24m_cycles Cycles of RC24M clock - */ -static inline void pllctlv2_xtal_set_rampup_time(PLLCTLV2_Type *ptr, uint32_t rc24m_cycles) -{ - ptr->XTAL = (ptr->XTAL & ~PLLCTLV2_XTAL_RAMP_TIME_MASK) | PLLCTLV2_XTAL_RAMP_TIME_SET(rc24m_cycles); -} - -/** - * @brief Check is PLL is stable - * @param [in] ptr PLLCTLv2 base address - * @param [in] pll PLL index - * @return true if PLL is stable - */ -static inline bool pllctlv2_pll_is_stable(PLLCTLV2_Type *ptr, uint8_t pll) -{ - return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_RESPONSE_MASK); -} - -/** - * @brief Check if PLL is enabled - * @param [in] ptr PLLCTLV2 base address - * @param [in] pll PLL index - * @return true if PLL is enabled - */ -static inline bool pllctlv2_pll_is_enabled(PLLCTLV2_Type *ptr, uint8_t pll) -{ - return IS_HPM_BITMASK_SET(ptr->PLL[pll].MFI, PLLCTLV2_PLL_MFI_ENABLE_MASK); -} - -/** - * @brief Select the PLL reference clock - * @param [in] ptr PLLCTLV2 base address - * @param [in] pll PLL index - * @param [in] src PLL reference lcock source - * @arg 0 - XTAL24M - * @arg 1 - IRC24M - */ -static inline void pllctlv2_select_reference_clock(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t src) -{ - ptr->PLL[pll].CONFIG = (ptr->PLL[pll].CONFIG & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) | PLLCTLV2_PLL_CONFIG_REFSEL_SET(src); -} - -/** - * @brief Enable PLL Spread Spectrum feature - * @param [in] ptr PLLCTLV2 base address - * @param [in] pll PLL index - * @param [in] step Step of spread spectrum modulator - * @param [in] stop Stop point of spread spectrum modulator - */ -void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop); - -/** - * @brief Disable PLL Spread spectrum - * @param [in] ptr PLLCTLV2 base address - * @param [in] pll PLL index - */ -static inline void pllctlv2_disable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll) -{ - ptr->PLL[pll].CONFIG &= ~PLLCTLV2_PLL_CONFIG_SPREAD_MASK; -} - -/** - * @brief Set PLL lock time - * @param [in] ptr PLLCTLV2 base address - * @param [in] pll PLL index - * @param [in] xtal_cycles external Crystal cycles - */ -static inline void pllctlv2_set_pll_lock_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles) -{ - ptr->PLL[pll].LOCKTIME = PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(xtal_cycles); -} - -/** - * @brief Set PLL step time - * @param [in] ptr PLLCTLV2 base address - * @param [in] pll PLL index - * @param [in] xtal_cycles external Crystal cycles - */ -static inline void pllctlv2_set_pll_step_time(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t xtal_cycles) -{ - ptr->PLL[pll].STEPTIME = PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(xtal_cycles); -} - -/** - * @brief Set PLL Post divider - * @param [in] ptr PLLCTLV2 base - * @param [in] pll PLL index - * @param [in] div_index Divider index - * @param [in] div_value divider value, divider factor is 1 + div_value / 5 - */ -void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value); - -/** - * @brief Set the PLL via the low-level MFI, MFD and MFN - * PLL frequency = REF CLOCK * (mfi + 1.0 * mfn / mfd) - * @param [in] ptr PLLCTLV2 base - * @param [in] pll PLL index - * @param [in] mfi MFI value - * @param [in] mfn MFN value - * @retval status_invalid_argument some parameters are invalid - * @retval status_success operation is successful - */ -hpm_stat_t pllctlv2_set_pll_with_mfi_mfn(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t mfi, uint32_t mfn); - -/** - * @brief Initialize PLL to specified frequency - * Note: the specified PLL clock needs to be enabled before being configured - * @param [in] ptr PLLCTLV2 base - * @param [in] pll PLL index - * @param [in] freq_in_hz expected PLL frequency - * @retval status_invalid_argument some parameters are invalid - * @retval status_success operation is successful - */ -hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz); - -/** - * @brief Get the specified PLl clock frequency - * @param [in] ptr PLLCTLV2 base - * @param [in] pll PLL index - * @return PLL frequency in Hz - */ -uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll); - -/** - * @brief Get the selected PLL post divider frequency - * @param [in] ptr PLLCTLV2 base - * @param [in] pll PLL index - * @param [in] div_index Post divider index - * @return PLL frequency in Hz - */ -uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index); - - -/** - * @} - */ -#endif /* HPM_PLLCTLV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h deleted file mode 100644 index 51f928f263e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmon_drv.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PMON_DRV_H -#define HPM_PMON_DRV_H -#include "hpm_common.h" -#include "hpm_pmon_regs.h" - -#define PMON_EVENT_GLITCH0 (1U << 0) -#define PMON_EVENT_GLITCH1 (1U << 1) -#define PMON_EVENT_CLOCK0 (1U << 2) -#define PMON_EVENT_CLOCK1 (1U << 3) - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void pmon_enable(PMON_Type *ptr, - uint8_t monitor_index, - bool enable) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL - & ~PMON_MONITOR_CONTROL_ENABLE_MASK) - | PMON_MONITOR_CONTROL_ENABLE_SET(enable); -} - -static inline void pmon_select_glitch_mode(PMON_Type *ptr, - uint8_t monitor_index, - bool active_mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL - & ~PMON_MONITOR_CONTROL_ACTIVE_MASK) - | PMON_MONITOR_CONTROL_ACTIVE_SET(active_mode); -} - -static inline bool pmon_glich_detected(PMON_Type *ptr, uint8_t monitor_index) -{ - return ptr->MONITOR[monitor_index].STATUS; -} - -static inline void pmon_test_mode_enable(PMON_Type *ptr, bool enable) -{ - ptr->TEST_MODE = (ptr->TEST_MODE & ~PMON_TEST_MODE_DISABLE_MASK) - | PMON_TEST_MODE_DISABLE_SET(!enable); -} - -static inline void pmon_irq_enable(PMON_Type *ptr, uint32_t mask, bool enable) -{ - ptr->IRQ_ENABLE = (ptr->IRQ_ENABLE & ~mask) | (enable ? mask : 0); -} - -static inline uint32_t pmon_irq_get_status(PMON_Type *ptr) -{ - return ptr->IRQ_FLAG; -} - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_PMON_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h deleted file mode 100644 index 2bb58051c00..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pmp_drv.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_PMP_DRV_H -#define HPM_PMP_DRV_H - -#include "hpm_common.h" -#include "hpm_soc_feature.h" - -/** - * @brief PMP Entry structure - */ -typedef struct pmp_entry_struct { - union { - struct { - uint8_t read_access_ctrl: 1; - uint8_t write_access_ctrl: 1; - uint8_t execution_ctrl: 1; - uint8_t addr_matching_mode: 2; - uint8_t reserved: 2; - uint8_t lock: 1; - }; - uint8_t val; - } pmp_cfg; - uint8_t reserved0[3]; - uint32_t pmp_addr; -#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) - union { - struct { - uint8_t entry_addr_matching_mode: 2; - uint8_t mem_type_attribute: 4; - uint8_t automic_mem_operation_ctrl: 1; - uint8_t reserved: 1; - }; - uint8_t val; - } pma_cfg; - uint8_t reserved1[3]; - uint32_t pma_addr; -#endif -} pmp_entry_t; - -/** - * @brief PMP Configuration definitions - */ -#define READ_EN (1U) -#define READ_DIS (0U) -#define WRITE_EN (1U) -#define WRITE_DIS (0U) -#define EXECUTE_EN (1U) -#define EXECUTE_DIS (0U) -#define ADDR_MATCH_MODE_OFF (0U) -#define ADDR_MATCH_TOR (1U) -#define ADDR_MATCH_NAPOT (3U) -#define REG_LOCK (1U) -#define REG_UNLOCK (0U) - -/** - * @brief PMA Configuration definitions - */ -#define MEM_TYPE_DEV_NON_BUF (0U) -#define MEM_TYPE_DEV_BUF (1U) -#define MEM_TYPE_MEM_NON_CACHE_NON_BUF (2U) -#define MEM_TYPE_MEM_NON_CACHE_BUF (3U) -#define MEM_TYPE_MEM_WT_NO_ALLOC (4U) -#define MEM_TYPE_MEM_WT_READ_ALLOC (5U) -#define MEM_TYPE_MEM_WB_NO_ALLOC (8U) -#define MEM_TYPE_MEM_WB_READ_ALLOC (9U) -#define MEM_TYPE_MEM_WB_WRITE_ALLOC (10U) -#define MEM_TYPE_MEM_WB_READ_WRITE_ALLOC (11U) -#define MEM_TYPE_EMPTY_HOLE (15U) - -#define AMO_EN (0U) -#define AMO_DIS (1U) - -/** - * @brief PMP Configuration - * @param r - READ Access control, valid value: READ_EN, READ_DIS - * @param w - Write access control, valid value: WRITE_EN, WRITE_DIS - * @param x - Instruction Execution control, valid value: EXECUTE_EN, EXECUTE_DIS - * @param m - Address matching mode, valid value: - * ADDR_MATCH_MODE_OFF - Null region - * ADDR_MATCH_TOR - Top of range. For pmp_addr0, any address < pmp_addr0 matches, for other regions, - * any address which meets ( pmp_addr[i-1] <= addr < pmp_addr) matches. - * ADDR_MATCH_NAPOT - Naturally aligned power-of-2 region, minimal size must be 8 bytes - * @param l - Write lock and permission enforcement bit for Machine mode, valid value: REG_LOCK, REG_UNLOCK - */ -#define PMP_CFG(r, w, x, m, l) ((r) | ((w) << 1) | ((x) << 2) | ((m) << 3) | ((l) << 7)) -/** - * @brief PMA Configuration - * @param m - Entry address matching mode, valid value: - * ADDR_MATCH_MODE_OFF - This PMA entry is disabled - * ADDR_MATCH_NAPOT - Naturally aligned power-of-2 region， the granularity is 4K bytes - * @param t - Memory type attributes, valid value: - * MEM_TYPE_DEV_NON_BUF - Device, Non-bufferable - * MEM_TYPE_DEV_BUF - Device, bufferable - * MEM_TYPE_MEM_NON_CACHE_NON_BUF - Memory, Non-cacheable, Non-bufferable - * MEM_TYPE_MEM_NON_CACHE_BUF - Memory, Non-cacheable, bufferable - * MEM_TYPE_MEM_WT_NO_ALLOC - Memory, Write-through, No-allocate - * MEM_TYPE_MEM_WT_READ_ALLOC - Memory, Write-through, read-allocate - * MEM_TYPE_MEM_WB_NO_ALLOC - Memory, Write-back, No-allocate - * MEM_TYPE_MEM_WB_READ_ALLOC - Memory, Write-back, Read-allocate - * MEM_TYPE_MEM_WB_READ_WRITE_ALLOC - Memory, Write-back, Write-Allocate, Read-Allocate - * MEM_TYPE_EMPTY_HOLE - Empty hole, nothing exists - * - * @param n - Indicate Whether Atomic Memory Operation instructions are not supported in this region, valid value: - * AMO_EN - Atomic Memory Operations are supported - * AMO_DIS - Atomic Memory Operations are not supported - */ -#define PMA_CFG(m, t, n) ((m) | ((t) << 2) | ((n) << 6)) -/** - * @brief Format Top Address Region - */ -#define PMP_TOR_ADDR(addr) ((addr) >> 2) -/** - * @brief Format PMP Natural Aligned Region - * @param x - start address - * @param n - power-of-2 aligned length - */ -#define PMP_NAPOT_ADDR(x, n) (((uint32_t)(x) >> 2) | (((uint32_t)(n)-1U) >> 3)) -/** - * @brief Format PMA Natural Aligned Region - * @param x - start address - * @param n - power-of-2 aligned length - */ -#define PMA_NAPOT_ADDR(x, n) (((uint32_t)(x) >> 2) | ((((uint32_t)(n)-1U) >> 3))) - -#ifdef __cplusplus -extern "C" { -#endif -/** - * @brief Write PMP Configuration to corresponding PMP_CFG register - * @param value PMP configuration - * @param idx PMP entry index, valid value is 0-15 - */ -void write_pmp_cfg(uint32_t value, uint32_t idx); - -/** - * @brief Read PMP configuration - * @param idx PMP entry index - * @return PMP configuration - */ -uint32_t read_pmp_cfg(uint32_t idx); - - -/** - * @brief Write PMP address to corresponding PMP_ADDR register - * @param value PMP address - * @param idx PMP address entry index, valid value is 0-15 - */ -void write_pmp_addr(uint32_t value, uint32_t idx); - -/** - * @brief Read PMP address entry - * @param idx PMP address entry index - * @return PMP address - */ -uint32_t read_pmp_addr(uint32_t idx); - -#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) -/** - * @brief Read PMA configuration - * @param idx PMA entry index - * @return PMA configuration - */ -uint32_t read_pma_cfg(uint32_t idx); - -/** - * @brief Write PMA Configuration to corresponding PMA_CFG register - * @param value PMA configuration - * @param idx PMA entry index, valid value is 0-15 - */ -void write_pma_cfg(uint32_t value, uint32_t idx); - -/** - * @brief Write PMA address to corresponding PMA_ADDR register - * @param value PMA address - * @param idx PMA address entry index, valid value is 0-15 - */ -void write_pma_addr(uint32_t value, uint32_t idx); - -/** - * @brief Read PMA address entry - * @param idx PMA address entry index, valid value is 0-15 - * @return PMA address - */ -uint32_t read_pma_addr(uint32_t idx); -#endif /* #if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) */ - -/** - * @brief Configure PMP and PMA for specified PMP/PMA entry - * - * @param[in] entry PMP entry - * @param entry_index PMP/PMA entry index - * @retval status_invalid_argument Invalid Arguments were detected - * @retval status_success Configuration completed without errors - */ -hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index); - -/** - * @brief Configure PMP and PMA based on the PMP entry list - * @param entry start of the PMP entry list - * @param num_of_entries Number of entries in the PMP entry list - * @retval status_invalid_argument Invalid Arguments were detected - * @retval status_success Configuration completed without errors - */ -hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries); - -/** - * @brief Disable PMP and PMA - */ -void pmp_disable(void); - -#ifdef __cplusplus -} -#endif - - -#endif /* HPM_PMP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppi_drv.h deleted file mode 100644 index 79701d4aaab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppi_drv.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPI_DRV_H -#define HPM_PPI_DRV_H - -#include "hpm_common.h" -#include "hpm_soc_ip_feature.h" -#include "hpm_ppi_regs.h" - -/** - * @brief PPI driver APIs - * @defgroup ppi_interface PPI driver APIs - * @ingroup ppi_interfaces - * @{ - */ - -/** - * @brief cs pin idle polarity - * - */ -typedef enum { - ppi_cs_idle_pol_low = 0, - ppi_cs_idle_pol_high -} ppi_cs_idle_polarity_t; /**< ppi_cs_idle_polarity_t */ - -/** - * @brief dm pin valid polarity - * - */ -typedef enum { - ppi_dm_valid_pol_high = 0, - ppi_dm_valid_pol_low -} ppi_dm_valid_polarity_t; /**< ppi_dm_valid_polarity_t */ - -/** - * @brief ctrl pin polarity - * - */ -typedef enum { - ppi_ctrl_pol_low = 0, - ppi_ctrl_pol_high -} ppi_ctrl_polarity_t; /**< ppi_ctrl_polarity_t */ - -/** - * @brief ctrl pin direction - * - */ -typedef enum { - ppi_ctrl_pin_dir_input = 0, - ppi_ctrl_pin_dir_output, -} ppi_ctrl_pin_dir_t; /**< ppi_ctrl_pin_dir_t */ - -/** - * @brief clock pin output mode - * - */ -typedef enum { - ppi_clk_output_by_cmd_clk_output = 0, - ppi_clk_always_output -} ppi_clk_output_mode_t; /**< ppi_clk_output_mode_t */ - -/** - * @brief irq mask - * - */ -typedef enum { - ppi_irq_tm_out_mask = PPI_IRQ_EN_IRQ_TMOUT_EN_MASK, -} ppi_irq_mask_t; /**< ppi_irq_mask_t */ - -/** - * @brief port size - * - */ -typedef enum { - ppi_port_size_8bits = 0, - ppi_port_size_16bits, - ppi_port_size_32bits, -} ppi_port_size_t; /**< ppi_port_size_t */ - -/** - * @brief cmd byte select - * - */ -typedef enum { - ppi_byte_sel_0_7_bits = 0, - ppi_byte_sel_8_15_bits, - ppi_byte_sel_16_23_bits, - ppi_byte_sel_24_31_bits -} ppi_byte_sel_t; /**< ppi_byte_sel_t */ - -/** - * @brief cmd address and data function - * - */ -typedef enum { - ppi_ad_func_data = 0, - ppi_ad_func_addr -} ppi_ad_func_t; /**< ppi_ad_func_t */ - -/** - * @brief cmd address and data pins direction - * - */ -typedef enum { - ppi_ad_pin_dir_output = 0, - ppi_ad_pin_dir_input -} ppi_ad_pin_dir_t; /**< ppi_ad_pin_dir_t */ - -/** - * @brief clock pin config structure - * - */ -typedef struct { - uint8_t cycle_num; - uint8_t high_num; - uint8_t low_num; - ppi_clk_output_mode_t mode; - bool revert; -} ppi_clk_pin_config_t; /**< ppi_clk_pin_config_t */ - -/** - * @brief cs pin config structure - * - */ -typedef struct { - ppi_port_size_t port_size; - uint16_t addr_start_high_12bits; /* address space: 0xF8000000 ~ 0xFFFFFFFF */ - uint16_t addr_end_high_12bits; /* address space: 0xF8000000 ~ 0xFFFFFFFF */ - uint16_t addr_mask; - bool sync_clk_en; - uint8_t sync_clk_sel; - uint8_t interval_cycle; - uint8_t rcmd_start0; - uint8_t rcmd_end0; - uint8_t rcmd_start1; - uint8_t rcmd_end1; - uint8_t wcmd_start0; - uint8_t wcmd_end0; - uint8_t wcmd_start1; - uint8_t wcmd_end1; -#if defined(HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS) && HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS - ppi_dm_valid_polarity_t dm_polarity; -#endif -} ppi_cs_pin_config_t; /**< ppi_cs_pin_config_t */ - -/** - * @brief cmd config structure - * - */ -typedef struct { - bool cs_pin_value; - bool clk_output; - uint8_t cmd_cycle; - ppi_ad_func_t ad_func_sel[4]; - ppi_ad_pin_dir_t ad_pin_dir[4]; - ppi_byte_sel_t byte_sel[4]; - bool ctrl_pin_value[8]; -} ppi_cmd_config_t; /**< ppi_cmd_config_t */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief set ppi software reset - * - * @param[in] ppi PPI base address - * @param[in] reset true - software reset; false - normal work. - */ -static inline void ppi_set_reset(PPI_Type *ppi, bool reset) -{ - if (reset) { - ppi->GLB_CFG |= PPI_GLB_CFG_SOFT_RESET_MASK; - } else { - ppi->GLB_CFG &= ~PPI_GLB_CFG_SOFT_RESET_MASK; - } -} - -/** - * @brief config cs pin work valid polarity - * - * @param[in] ppi PPI base address - * @param[in] index cs pin index, value: 0 - 3 - * @param[in] pol @ref ppi_cs_idle_polarity_t - */ -static inline void ppi_config_cs_pin_polarity(PPI_Type *ppi, uint8_t index, ppi_cs_idle_polarity_t pol) -{ - assert(index < 4); - ppi->PAD_CFG = (ppi->PAD_CFG & ~(((1u << PPI_PAD_CFG_CS_IDLE_ST_SHIFT) << index))) | (((pol << PPI_PAD_CFG_CS_IDLE_ST_SHIFT) << index)); -} - -/** - * @brief config dm pin work polarity - * - * @param[in] ppi PPI base address - * @param[in] index If has HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS feature, this is cs pin index, value: 0 - 3. Else, not use. - * @param[in] pol @ref ppi_dm_valid_polarity_t - */ -static inline void ppi_config_dm_pin_polarity(PPI_Type *ppi, uint8_t index, ppi_dm_valid_polarity_t pol) -{ -#if defined(HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS) && HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS - assert(index < 4); - ppi->CS[index].CFG2 = (ppi->CS[index].CFG2 & ~PPI_CS_CFG2_DM_POLARITY_MASK) | PPI_CS_CFG2_DM_POLARITY_SET(pol); -#else - (void)index; - if (pol == ppi_dm_valid_pol_high) { - ppi->PAD_CFG &= ~PPI_PAD_CFG_DM_PAD_POL_MASK; - } else { - ppi->PAD_CFG |= PPI_PAD_CFG_DM_PAD_POL_MASK; - } -#endif -} - -/** - * @brief config ctrl pin work polarity, output and input ctrl pin polarity has different meaning - * - * @param[in] ppi PPI base address - * @param[in] index Ctrl pin index, value: 0 - 7 - * @param[in] pol @ref ppi_ctrl_polarity_t - * [1] Output: ppi_ctrl_pol_low is output the value in cmd; ppi_ctrl_pol_high is output reversed value in cmd. - * [2] Input: ppi_ctrl_pol_low is input low valid; ppi_ctrl_pol_high is input high valid. - */ -static inline void ppi_config_ctrl_pin_polarity(PPI_Type *ppi, uint8_t index, ppi_ctrl_polarity_t pol) -{ - assert(index < 8); - ppi->PAD_CFG = (ppi->PAD_CFG & ~(((1u << PPI_PAD_CFG_CTRL_PAD_POL_SHIFT) << index))) | (((pol << PPI_PAD_CFG_CTRL_PAD_POL_SHIFT) << index)); -} - -/** - * @brief set ctrl pin direction - * - * @param[in] ppi PPI base address - * @param[in] index Ctrl pin index, value: 0 - 7 - * @param[in] dir Ctrl pin direction, @ref ppi_ctrl_pin_dir_t - */ -static inline void ppi_set_ctrl_pin_dir(PPI_Type *ppi, uint8_t index, ppi_ctrl_pin_dir_t dir) -{ - assert(index < 8); - ppi->PAD_CFG = (ppi->PAD_CFG & ~(((1u << PPI_PAD_CFG_CTRL_PAD_OE_SHIFT) << index))) | (((dir << PPI_PAD_CFG_CTRL_PAD_OE_SHIFT) << index)); -} - -/** - * @brief config timeout - * - * @param[in] ppi PPI base address - * @param[in] timeout_cnt timeout counter - * @param[in] enable true - enable; false - disable - */ -static inline void ppi_config_timeout(PPI_Type *ppi, uint16_t timeout_cnt, bool enable) -{ - ppi->TM_CFG = PPI_TM_CFG_TM_CFG_SET(timeout_cnt) | PPI_TM_CFG_TM_EN_SET(enable); -} - -/** - * @brief set irq enable - * - * @param[in] ppi PPI base address - * @param[in] mask irq mask, @ref ppi_irq_mask_t - */ -static inline void ppi_set_irq_enable(PPI_Type *ppi, uint32_t mask) -{ - ppi->IRQ_EN |= mask; -} - -/** - * @brief set irq disable - * - * @param[in] ppi PPI base address - * @param[in] mask irq mask, @ref ppi_irq_mask_t - */ -static inline void ppi_set_irq_disable(PPI_Type *ppi, uint32_t mask) -{ - ppi->IRQ_EN &= ~mask; -} - -/** - * @brief get irq enable status - * - * @param[in] ppi PPI base address - * @retval irq enable status, @ref ppi_irq_mask_t - */ -static inline uint32_t ppi_get_irq_enable_status(PPI_Type *ppi) -{ - return ppi->IRQ_EN; -} - -/** - * @brief get irq status - * - * @param[in] ppi PPI base address - * @retval irq status, @ref ppi_irq_mask_t - */ -static inline uint32_t ppi_get_irq_status(PPI_Type *ppi) -{ - return ppi->IRQ_STS; -} - -/** - * @brief clear irq flag - * - * @param[in] ppi PPI base address - * @param[in] mask irq mask, @ref ppi_irq_mask_t - */ -static inline void ppi_clear_irq_flag(PPI_Type *ppi, uint32_t mask) -{ - ppi->IRQ_STS = mask; -} - -/** - * @brief set clk pin enable - * - * @param[in] ppi PPI base address - */ -static inline void ppi_set_clk_pin_enable(PPI_Type *ppi) -{ - ppi->CLKPIN_CFG |= PPI_CLKPIN_CFG_EN_MASK; -} - -/** - * @brief set clk pin disable - * - * @param[in] ppi PPI base address - */ -static inline void ppi_set_clk_pin_disable(PPI_Type *ppi) -{ - ppi->CLKPIN_CFG &= ~PPI_CLKPIN_CFG_EN_MASK; -} - -/** - * @brief config clock pin output - * - * @param[in] ppi PPI base address - * @param[in] config clock pin config structure pointer, @ref ppi_clk_pin_config_t - */ -void ppi_config_clk_pin(PPI_Type *ppi, ppi_clk_pin_config_t *config); - -/** - * @brief config cs pin - * - * @param[in] ppi PPI base address - * @param[in] index cs pin index, value: 0 - 3 - * @param[in] config cs pin config structure pointer, @ref ppi_cs_pin_config_t - */ -void ppi_config_cs_pin(PPI_Type *ppi, uint8_t index, ppi_cs_pin_config_t *config); - -/** - * @brief config cmd - * - * @param[in] ppi PPI base address - * @param[in] index cmd index, value: 0 - 63 - * @param[in] config cmd config structure pointer, @ref ppi_cmd_config_t - */ -void ppi_config_cmd(PPI_Type *ppi, uint8_t index, ppi_cmd_config_t *config); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_PPI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h deleted file mode 100644 index 5ffa9295851..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_psec_drv.h +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PSEC_DRV_H -#define HPM_PSEC_DRV_H -#include "hpm_common.h" -#include "hpm_psec_regs.h" - -typedef enum psec_lifecycle { - psec_lifecycle_unknown = 1 << 0, - psec_lifecycle_create = 1 << 1, - psec_lifecycle_nonsecucre = 1 << 2, - psec_lifecycle_secucre = 1 << 3, - psec_lifecycle_return = 1 << 4, - psec_lifecycle_no_return = 1 << 5, - psec_lifecycle_scribe = 1 << 6, - psec_lifecycle_debate = 1 << 7, -} psec_lifecycle_t; - -typedef enum batt_sec_state { - batt_sec_state_ins = 0, - batt_sec_state_secure = 1, - batt_sec_state_non_secure = 2, - batt_sec_state_fail = 3, -} batt_sec_state_t; - -typedef enum psec_state { - psec_state_ins = 0, - psec_state_secure = 1, - psec_state_non_secure = 2, - psec_state_fail = 3, -} psec_state_t; - -enum { - status_psec_switch_state_not_allowed = MAKE_STATUS(status_group_psec, 1), -}; - -#define PSEC_PSECURE_STATE_MASK \ - (0xFU << PSEC_SECURE_STATE_PMIC_INS_SHIFT) -#define PSEC_BATT_SECURE_STATE_MASK \ - (0xFU << PSEC_SECURE_STATE_BATT_INS_SHIFT) - -#ifdef __cplusplus -extern "C" { -#endif - -static inline psec_lifecycle_t psec_get_pmic_lifecycle(PSEC_Type *ptr) -{ - return (psec_lifecycle_t) PSEC_LIFECYCLE_LIFECYCLE_GET(ptr->LIFECYCLE); -} - -static inline hpm_stat_t psec_switch_pmic_state(PSEC_Type *ptr, psec_state_t state) -{ - if (state == psec_state_secure) { - if (!PSEC_SECURE_STATE_ALLOW_SEC_GET(ptr->SECURE_STATE)) { - return status_psec_switch_state_not_allowed; - } - } else if (state == psec_state_non_secure) { - if (!PSEC_SECURE_STATE_ALLOW_NSC_GET(ptr->SECURE_STATE)) { - return status_psec_switch_state_not_allowed; - } - } - ptr->SECURE_STATE = (ptr->SECURE_STATE & ~PSEC_PSECURE_STATE_MASK) - | (1U << (PSEC_SECURE_STATE_PMIC_INS_SHIFT + state)); - return status_success; -} - -static inline void psec_allow_psecure_state_restart(PSEC_Type *ptr, bool allow) -{ - ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG - & ~PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) - | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow); -} - -static inline void psec_lock_psecure_state_restart(PSEC_Type *ptr, bool lock) -{ - ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG - & ~PSEC_SECURE_STATE_CONFIG_LOCK_MASK) - | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock); -} - -static inline void psec_pmic_rom_secrets_present(PSEC_Type *ptr, bool presented) -{ - ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG - & ~PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_MASK) - | PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(presented); -} - -static inline void psec_psec_secure_state_config(PSEC_Type *ptr, - bool rom_secrets_presented, - bool allow_secure_state_restart, - bool lock_secure_state_restart) -{ - ptr->SECURE_STATE_CONFIG = PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(rom_secrets_presented) - | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow_secure_state_restart) - | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock_secure_state_restart); -} - -static inline void psec_pmic_non_secure_violation_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG - & ~(PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK - | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)) - | PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(lock) - | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(violation_setting); -} - -static inline void psec_psecure_violation_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG - & ~(PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK - | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)) - | PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(lock) - | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(violation_setting); -} - -static inline void psec_pmic_non_secure_escalate_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG - & ~(PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK - | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)) - | PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(lock) - | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(violation_setting); -} - -static inline void psec_psecure_escalate_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG - & ~(PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK - | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)) - | PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(lock) - | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(violation_setting); -} - -static inline uint32_t psec_get_pmic_status(PSEC_Type *ptr) -{ - return ptr->EVENT; -} - -static inline psec_lifecycle_t psec_get_batt_lifecycle(PSEC_Type *ptr) -{ - return (psec_lifecycle_t) PSEC_LIFECYCLE_LIFECYCLE_GET(ptr->LIFECYCLE); -} - -static inline hpm_stat_t psec_switch_batt_state(PSEC_Type *ptr, batt_sec_state_t state) -{ - if (state == batt_sec_state_secure) { - if (!PSEC_SECURE_STATE_ALLOW_SEC_GET(ptr->SECURE_STATE)) { - return status_psec_switch_state_not_allowed; - } - } else if (state == batt_sec_state_non_secure) { - if (!PSEC_SECURE_STATE_ALLOW_NSC_GET(ptr->SECURE_STATE)) { - return status_psec_switch_state_not_allowed; - } - } - ptr->SECURE_STATE = (ptr->SECURE_STATE & ~PSEC_BATT_SECURE_STATE_MASK) - | (1U << (PSEC_SECURE_STATE_BATT_INS_SHIFT + state)); - return status_success; -} - -static inline void psec_allow_batt_secure_state_restart(PSEC_Type *ptr, bool allow) -{ - ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG - & ~PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) - | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow); -} - -static inline void psec_lock_batt_secure_state_restart(PSEC_Type *ptr, bool lock) -{ - ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG - & ~PSEC_SECURE_STATE_CONFIG_LOCK_MASK) - | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock); -} - -static inline void psec_batt_rom_secrets_present(PSEC_Type *ptr, bool presented) -{ - ptr->SECURE_STATE_CONFIG = (ptr->SECURE_STATE_CONFIG - & ~PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_MASK) - | PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(presented); -} - -static inline void psec_batt_set_secure_state_config(PSEC_Type *ptr, - bool rom_secrets_presented, - bool allow_secure_state_restart, - bool lock_secure_state_restart) -{ - ptr->SECURE_STATE_CONFIG = PSEC_SECURE_STATE_CONFIG_ROM_SECRETS_SET(rom_secrets_presented) - | PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(allow_secure_state_restart) - | PSEC_SECURE_STATE_CONFIG_LOCK_SET(lock_secure_state_restart); -} - -static inline void psec_batt_non_secure_violation_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG - & ~(PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK - | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)) - | PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(lock) - | PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(violation_setting); -} - -static inline void psec_batt_secure_violation_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->VIOLATION_CONFIG = (ptr->VIOLATION_CONFIG - & ~(PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK - | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)) - | PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(lock) - | PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(violation_setting); -} - -static inline void psec_batt_non_secure_escalate_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG - & ~(PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK - | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)) - | PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(lock) - | PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(violation_setting); -} - -static inline void psec_batt_secure_escalate_config(PSEC_Type *ptr, - uint32_t violation_setting, - bool lock) -{ - ptr->ESCALATE_CONFIG = (ptr->ESCALATE_CONFIG - & ~(PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK - | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)) - | PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(lock) - | PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(violation_setting); -} - -static inline uint32_t psec_get_batt_status(PSEC_Type *ptr) -{ - return ptr->EVENT; -} -#ifdef __cplusplus -} -#endif - -#endif /* HPM_PSEC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h deleted file mode 100644 index 2dce934fc43..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ptpc_drv.h +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PTPC_DRV_H -#define HPM_PTPC_DRV_H - -#include "hpm_common.h" -#include "hpm_ptpc_regs.h" - -/** - * @brief PTPC driver - * @defgroup ptpc_interface PTPC driver APIs - * @ingroup timer_interfaces Timers - * @{ - */ - -#define PTPC_EVENT_COMPARE0_MASK PTPC_INT_STS_COMP_INT_STS0_MASK -#define PTPC_EVENT_CAPTURE0_MASK PTPC_INT_STS_CAPTURE_INT_STS0_MASK -#define PTPC_EVENT_PPS0_MASK PTPC_INT_STS_PPS_INT_STS0_MASK -#define PTPC_EVENT_COMPARE1_MASK PTPC_INT_STS_COMP_INT_STS1_MASK -#define PTPC_EVENT_CAPTURE1_MASK PTPC_INT_STS_CAPTURE_INT_STS1_MASK -#define PTPC_EVENT_PPS1_MASK PTPC_INT_STS_PPS_INT_STS1_MASK - -#define PTPC_MAX_NS_COUNTER (0x3B9ACA00UL) - -/** - * @brief Counter types - */ -typedef enum ptpc_ns_counter_rollover_type { - ptpc_ns_counter_rollover_binary = 0, /**< binary mode, resolution ~0.466ns, overflow at 0x7FFFFFFF */ - ptpc_ns_counter_rollover_digital = 1, /**< digital mode, resolution 1ns, overflow at 0x3B9ACA00 */ -} ptpc_ns_counter_rollover_type_t; - -/** - * @brief Capture trigger types - */ -typedef enum ptpc_capture_trigger_type { - ptpc_capture_trigger_none = 0, - ptpc_capture_trigger_on_rising_edge = PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK, - ptpc_capture_trigger_on_failing_edge = PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK, - ptpc_capture_trigger_on_both_edges = PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK - | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK, -} ptpc_capture_trigger_type_t; - -/** - * @brief Capture trigger types - */ -typedef enum ptpc_counting_mode { - ptpc_counting_increment = 0, /**< Increment the counter */ - ptpc_counting_decrement = 1, /**< Decrement the counter */ -} ptpc_counting_mode; - -/** - * @brief Timer config - */ -typedef struct { - ptpc_capture_trigger_type_t capture_trigger; /**< Capture trigger */ - ptpc_ns_counter_rollover_type_t ns_rollover_mode; /**< Ns rollover mode */ - bool coarse_increment; /**< Set false to use fine increment */ - bool capture_keep; /**< Keep captured timer counter */ - uint32_t src_frequency; /**< Source frequency */ -} ptpc_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Configure ns counter rollover mode - * - * @param[in] ptr PTPC base address - * @param[in] index Index of target counter - * @param[in] rollover Rollover type - */ -static inline void ptpc_set_ns_counter_rollover(PTPC_Type *ptr, uint8_t index, - ptpc_ns_counter_rollover_type_t rollover) -{ - ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) - | PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(rollover); -} - -/** - * @brief Enable capture keep - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - */ -static inline void ptpc_enable_capture_keep(PTPC_Type *ptr, uint8_t index) -{ - ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; -} - -/** - * @brief Disable capture keep - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - */ -static inline void ptpc_disable_capture_keep(PTPC_Type *ptr, uint8_t index) -{ - ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK; -} - -/** - * @brief Update ns counter update type - * - * @param[in] ptr PTPC base address - * @param[in] index Index of target counter - * @param[in] coarse_update Counter will be increment by 1 on - */ -static inline void ptpc_set_ns_counter_update_type(PTPC_Type *ptr, uint8_t index, bool coarse_update) -{ - ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) - | PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(coarse_update); -} - -/** - * @brief Set ns counter increment step - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] ns_step Increment step - */ -static inline void ptpc_set_ns_counter_step(PTPC_Type *ptr, uint8_t index, uint32_t ns_step) -{ - ptr->PTPC[index].CTRL1 = PTPC_PTPC_CTRL1_SS_INCR_SET(ns_step); -} - -/** - * @brief Set Second portion update value - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] sec Second value - */ -static inline void ptpc_set_second_update(PTPC_Type *ptr, uint8_t index, uint32_t sec) -{ - ptr->PTPC[index].TS_UPDTH = PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(sec); -} - -/** - * @brief Set ns portion update value - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] ns Ns value (31 bits, 0x3B9ACA00 max) - * @param[in] mode Counting mode - * - * @return status_success if everything is okay - */ -hpm_stat_t ptpc_set_ns_update(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode); - -/** - * @brief Get current timestamp Second portion - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * - * @return Seconds value - */ -static inline uint32_t ptpc_get_timestamp_second(PTPC_Type *ptr, uint8_t index) -{ - return PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(ptr->PTPC[index].TIMEH); -} - -/** - * @brief Get timestamp ns portion - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * - * @return ns value - */ -static inline uint32_t ptpc_get_timestamp_ns(PTPC_Type *ptr, uint8_t index) -{ - return PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(ptr->PTPC[index].TIMEL); -} - -/** - * @brief Config compare - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] sec Target second - * @param[in] ns Target ns - */ -static inline void ptpc_config_compare(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns) -{ - ptr->PTPC[index].TARH = PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(sec); - ptr->PTPC[index].TARL = PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(ns); - ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_COMP_EN_MASK; -} - -/** - * @brief Update Second portion - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] sec Target second - */ -static inline void ptpc_update_timestamp_second(PTPC_Type *ptr, uint8_t index, uint32_t sec) -{ - ptr->PTPC[index].TS_UPDTH = PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(sec); -} - -/** - * @brief Update Ns portion - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] ns Target ns - * @param[in] mode Counting mode - */ -static inline void ptpc_update_timestamp_ns(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode) -{ - ptr->PTPC[index].TS_UPDTL = PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(ns) | PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(mode); -} - -/** - * @brief Enable timer - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - */ -static inline void ptpc_enable_timer(PTPC_Type *ptr, uint8_t index) -{ - ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; -} - -/** - * @brief Disable timer - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - */ -static inline void ptpc_disable_timer(PTPC_Type *ptr, uint8_t index) -{ - ptr->PTPC[index].CTRL0 &= ~PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK; -} - -/** - * @brief Config capture trigger event - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] trigger Capture trigger type - */ -static inline void ptpc_config_capture(PTPC_Type *ptr, uint8_t index, - ptpc_capture_trigger_type_t trigger) -{ - ptr->PTPC[index].CTRL0 = (ptr->PTPC[index].CTRL0 & ~(PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK - | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK)) | trigger; -} - -/** - * @brief Get snapped ns value - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * - * @return ns portion on capture - */ -static inline uint32_t ptpc_get_capture_ns(PTPC_Type *ptr, uint8_t index) -{ - return PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(ptr->PTPC[index].CAPT_SNAPL); -} - -/** - * @brief Get captured second - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * - * @return second portion on capture - */ -static inline uint32_t ptpc_get_capture_second(PTPC_Type *ptr, uint8_t index) -{ - return PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(ptr->PTPC[index].CAPT_SNAPH); -} - -/** - * @brief Clear interrupt status - * - * @param[in] ptr PTPC base address - * @param[in] mask Mask of interrupts to be cleared - */ -static inline void ptpc_clear_irq_status(PTPC_Type *ptr, uint32_t mask) -{ - ptr->INT_STS = mask; -} - -/** - * @brief Get interrupt status - * - * @param[in] ptr PTPC base address - * - * @return interrupt status mask - */ -static inline uint32_t ptpc_get_irq_status(PTPC_Type *ptr) -{ - return ptr->INT_STS; -} - -/** - * @brief Disable interrupt with mask - * - * @param[in] ptr PTPC base address - * @param[in] mask Mask of interrupts to be disabled - */ -static inline void ptpc_irq_disable(PTPC_Type *ptr, uint32_t mask) -{ - ptr->INT_EN &= ~mask; -} - -/** - * @brief Enable interrupt with mask - * - * @param[in] ptr PTPC base address - * @param[in] mask Mask of interrupts to be enabled - */ -static inline void ptpc_irq_enable(PTPC_Type *ptr, uint32_t mask) -{ - ptr->INT_EN |= mask; -} - -/** - * @brief Initialize PTPC module - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] config Pointer to configuration struct - * - * @return status_success if everything is okay - */ -hpm_stat_t ptpc_init(PTPC_Type *ptr, uint8_t index, ptpc_config_t *config); - -/** - * @brief Set PTPC output destination - * - * @param[in] ptr PTPC base address - * @param[in] can_index Target CAN instance - * @param[in] use_ptpc1 Use PTPC1 if set to true, otherwise PTPC0 - * - * @return status_success if everything is okay - */ -hpm_stat_t ptpc_set_timer_output(PTPC_Type *ptr, uint8_t can_index, bool use_ptpc1); - -/** - * @brief Get default config - * - * @param[in] ptr PTPC base address - * @param[out] config Pointer of config struct - */ -void ptpc_get_default_config(PTPC_Type *ptr, ptpc_config_t *config); - -/** - * @brief Initialize timer to count from 0 - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * - */ -void ptpc_init_timer(PTPC_Type *ptr, uint8_t index); - -/** - * @brief Initialize timer with initial values - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] sec Seconds - * @param[in] ns Ns - * @param[in] mode Counting mode - * - * @return status_success if everything is okay - */ -hpm_stat_t ptpc_init_timer_with_initial(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode); - -/** - * @brief Update timestamp counter - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] sec Seconds - * @param[in] ns Ns - * @param[in] mode Counting mode - * @return status_success if everything is okay - */ -hpm_stat_t ptpc_update_timer(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode); - -/** - * @brief Set period of pulse generated per second - * - * @param[in] ptr PTPC base address - * @param[in] index Target index - * @param[in] p (2^power Hz, from [0 - 15]) - * - * @return true if requested frequency can be set - * @return false if requested frequency can not be set - */ -hpm_stat_t ptpc_set_pps(PTPC_Type *ptr, uint8_t index, uint8_t p); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PTPC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h deleted file mode 100644 index 679cc915696..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h +++ /dev/null @@ -1,1145 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PWM_DRV_H -#define HPM_PWM_DRV_H - -#include "hpm_common.h" -#include "hpm_pwm_regs.h" -#include "hpm_soc_feature.h" -/** - * @brief PWM driver APIs - * @defgroup pwm_interface PWM driver APIs - * @ingroup motor_interfaces - * @{ - * - */ -#define PWM_UNLOCK_KEY (0xB0382607UL) - -/* IRQ enable bit mask */ -#define PWM_IRQ_FAULT PWM_IRQEN_FAULTIRQE_MASK -#define PWM_IRQ_EX_RELOAD PWM_IRQEN_XRLDIRQE_MASK -#define PWM_IRQ_HALF_RELOAD PWM_IRQEN_HALFRLDIRQE_MASK -#define PWM_IRQ_RELOAD PWM_IRQEN_RLDIRQE_MASK -#define PWM_IRQ_CMP(x) PWM_IRQEN_CMPIRQEX_SET((1 << x)) - -/* PWM force output mask */ -#define PWM_FORCE_OUTPUT(pwm_index, force_output) \ - (force_output << (pwm_index << 1)) - -#define PWM_DUTY_CYCLE_FP_MAX ((1U << 24) - 1) - -/** - * @brief pwm trigger mode - * - */ -typedef enum pwm_counter_type { - pwm_counter_type_capture_rising_edge, /**< rising edge trigger*/ - pwm_counter_type_capture_falling_edge, /**< falling edge trigger*/ -} pwm_counter_type_t; - -/** - * @brief pwm cmp mode - * - */ -typedef enum pwm_cmp_mode { - pwm_cmp_mode_output_compare = 0, /**< output compare*/ - pwm_cmp_mode_input_capture = 1, /**< input compare*/ -} pwm_cmp_mode_t; - -/** - * @brief update time of the shadow register - * - */ -typedef enum pwm_register_update { - pwm_shadow_register_update_on_shlk = 0, /**< after software set shlk bit of shlk register*/ - pwm_shadow_register_update_on_modify = 1, /**< immediately after the register being modified*/ - pwm_shadow_register_update_on_hw_event = 2, /**< after hardware event assert*/ - pwm_shadow_register_update_on_sh_synci = 3, /**< after SHSYNCI assert */ -} pwm_shadow_register_update_trigger_t; - -/** - * @brief configure the state of channel 0-7 outputs when the forced output is in effect - * - */ -typedef enum pwm_fault_mode { - pwm_fault_mode_force_output_0 = 0, /**< fault forced output logic 0 */ - pwm_fault_mode_force_output_1 = 1, /**< fault forced output logic 1 */ - pwm_fault_mode_force_output_highz = 2, /**< turn off output, pin becomes high resistance */ -} pwm_fault_mode_t; - -/** - * @brief select when to recover PWM output after fault - * - */ -typedef enum pwm_fault_recovery_trigger { - pwm_fault_recovery_immediately = 0, /**< immediately*/ - pwm_fault_recovery_on_reload = 1, /**< after pwm timer counter reload time*/ - pwm_fault_recovery_on_hw_event = 2, /**< after hardware event assert*/ - pwm_fault_recovery_on_fault_clear = 3, /**< after software write faultclr bit in GCR register*/ -} pwm_fault_recovery_trigger_t; - -/** - * @brief fault input signal - * - */ -typedef enum pwm_fault_source { - pwm_fault_source_internal_0 = PWM_GCR_FAULTI0EN_MASK, /**< FAULTI0 */ - pwm_fault_source_internal_1 = PWM_GCR_FAULTI1EN_MASK, /**< FAULTI1 */ - pwm_fault_source_internal_2 = PWM_GCR_FAULTI2EN_MASK, /**< FAULTI2 */ - pwm_fault_source_internal_3 = PWM_GCR_FAULTI3EN_MASK, /**< FAULTI3 */ - pwm_fault_source_external_0 = PWM_GCR_FAULTE0EN_MASK, /**< EXFAULTI0 */ - pwm_fault_source_external_1 = PWM_GCR_FAULTE1EN_MASK, /**< EXFAULTI1 */ - pwm_fault_source_debug = PWM_GCR_DEBUGFAULT_MASK, /**< Debug fault */ -} pwm_fault_source_t; - -/** - * @brief Select sources for force output - * - */ -typedef enum pwm_force_source { - pwm_force_source_force_input = 0, /**< force output is enabled when FRCI assert */ - pwm_force_source_software = 1, /**< force output is enabled by software write swfrc to 1 */ -} pwm_force_source_t; -/** - * @brief select when the FRCMD shadow register will be loaded to its work register - * - */ -typedef enum pwm_force_cmd_timing { - pwm_force_immediately = 0, /**< after software set shlk bit of shlk register */ - pwm_force_at_reload = 1, /**< immediately after the register being modified */ - pwm_force_at_synci = 2, /**< after hardware event assert */ - pwm_force_none = 3, /**< after SHSYNCI assert */ -} pwm_force_cmd_timing_t; - -/** - * @brief pwm output type - * - */ -typedef enum pwm_output_type { - pwm_output_0 = 0, /**< output 0 */ - pwm_output_1 = 1, /**< output 1 */ - pwm_output_high_z = 2, /**< output */ - pwm_output_no_force = 3, -} pwm_output_type_t; - -/** - * @brief pwm compare config - * - */ -typedef struct pwm_cmp_config { - uint32_t cmp; /**< compare value */ - bool enable_ex_cmp; /**< enable extended compare value */ -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - bool enable_hrcmp; /**< enable high precision pwm */ -#endif - uint8_t mode; /**< compare work mode: pwm_cmp_mode_output_compare or pwm_cmp_mode_input_capture */ - uint8_t update_trigger; /**< compare configuration update trigger */ - uint8_t ex_cmp; /**< extended compare value */ - uint8_t half_clock_cmp; /**< half clock compare value*/ - uint8_t jitter_cmp; /**< jitter compare value */ -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - uint8_t hrcmp; /**< high precision pwm */ -#endif -} pwm_cmp_config_t; - -/** - * @brief pwm output channel config - * - */ -typedef struct pwm_output_channel { - uint8_t cmp_start_index; /**< output channel compare start index */ - uint8_t cmp_end_index; /**< output channel compare end index */ - bool invert_output; /**< invert output */ -} pwm_output_channel_t; -/** - * @brief pwm fault source config - * - */ -typedef struct pwm_fault_source_config { - uint32_t source_mask; /**< fault source mask*/ - bool fault_recover_at_rising_edge; /**< recover fault at rising edge */ - bool fault_external_0_active_low; /**< active external fault0 by low */ - bool fault_external_1_active_low; /**< active external fault1 by low */ - uint8_t fault_output_recovery_trigger; /**< fault output recoverty trigger */ -} pwm_fault_source_config_t; - -/** - * @brief pwm config data - * - */ -typedef struct pwm_config { -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - bool hrpwm_update_mode; /**< mode one or zero, HR CMP update timing */ -#endif - bool enable_output; /**< enable pwm output */ - bool invert_output; /**< invert pwm output level */ - uint8_t update_trigger; /**< pwm config update trigger */ - uint8_t fault_mode; /**< fault mode */ - uint8_t fault_recovery_trigger; /**< fault recoverty trigger */ - uint8_t force_source; /**< fault source */ - uint32_t dead_zone_in_half_cycle; /**< dead zone in half cycle*/ -} pwm_config_t; - -/** - * @brief pair pwm config - * - */ -typedef struct pwm_pair_config { - pwm_config_t pwm[2]; /**< pwm config data */ -} pwm_pair_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief pwm deinitialize function - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * - */ -static inline void pwm_deinit(PWM_Type *pwm_x) -{ - pwm_x->IRQEN = 0; - pwm_x->DMAEN = 0; - pwm_x->SR |= pwm_x->SR; - pwm_x->STA = 0; - pwm_x->RLD = PWM_RLD_RLD_MASK; - for (uint8_t i = 0; i < PWM_SOC_CMP_MAX_COUNT; i++) { - pwm_x->CMP[i] = PWM_CMP_CMP_MASK; - pwm_x->CMPCFG[i] = 0; - pwm_x->CHCFG[i] = PWM_CHCFG_CMPSELEND_SET(PWM_SOC_CMP_MAX_COUNT - 1) | PWM_CHCFG_CMPSELBEG_SET(PWM_SOC_CMP_MAX_COUNT - 1); - } - pwm_x->FRCMD = 0; - pwm_x->GCR = 0; - pwm_x->SHCR = 0; -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - pwm_x->HRPWM_CFG = 0; -#endif - for (uint8_t i = 0; i < PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT; i++) { - pwm_x->PWMCFG[i] = 0; - } -} - -/** - * @brief issue all shawdow register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_issue_shadow_register_lock_event(PWM_Type *pwm_x) -{ - if (pwm_x->SHCR & PWM_SHCR_SHLKEN_MASK) { - /* - * if lock shadow register has been enabled in SHCR, it has to set - * the lock bit twice to issue shadow register lock event. - */ - pwm_x->SHLK = PWM_SHLK_SHLK_MASK; - } - pwm_x->SHLK = PWM_SHLK_SHLK_MASK; -} - -/** - * @brief lock all shawdow register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_shadow_register_lock(PWM_Type *pwm_x) -{ - pwm_x->SHCR |= PWM_SHCR_SHLKEN_MASK; - pwm_x->SHLK = PWM_SHLK_SHLK_MASK; -} - -/** - * @brief unlock all shadow register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_shadow_register_unlock(PWM_Type *pwm_x) -{ - pwm_x->UNLK = PWM_UNLOCK_KEY; -} - -/** - * @brief set counter start value and extended start value - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] ex_start pwm timer counter extended start value - * @param[in] start pwm timer counter start value - */ -static inline void pwm_set_start_count(PWM_Type *pwm_x, - uint8_t ex_start, - uint32_t start) -{ - pwm_x->STA = PWM_STA_XSTA_SET(ex_start) - | PWM_STA_STA_SET(start); -} - -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - -/** - * @brief set hrpwm counter start value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param start pwm timer counter start value - */ -static inline void pwm_set_hrpwm_start_count(PWM_Type *pwm_x, - uint32_t start) -{ - pwm_x->STA_HRPWM = PWM_STA_HRPWM_STA_SET(start); -} - -#endif - -/** - * @brief set the reload value - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] ex_reload pwm timer counter extended reload value - * @param[in] reload pwm timer counter reload value - */ -static inline void pwm_set_reload(PWM_Type *pwm_x, - uint8_t ex_reload, - uint32_t reload) -{ - pwm_shadow_register_unlock(pwm_x); - pwm_x->RLD = PWM_RLD_XRLD_SET(ex_reload) - | PWM_RLD_RLD_SET(reload); -} - -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - -/** - * @brief set the hr pwm reload value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param hr_reload pwm timer counter hrpwm reload value - * @param reload pwm timer counter reload value - */ -static inline void pwm_set_hrpwm_reload(PWM_Type *pwm_x, - uint16_t hrpwm_reload, - uint32_t reload) -{ - pwm_shadow_register_unlock(pwm_x); - pwm_x->RLD_HRPWM = PWM_RLD_HRPWM_RLD_HR_SET(hrpwm_reload) - | PWM_RLD_HRPWM_RLD_SET(reload); -} - -#endif - -/** - * @brief clear pwm status register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] mask : - * @arg PWM_IRQ_FAULT: fault condition flag - * @arg PWM_IRQ_EX_RELOAD : extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - * @arg PWM_IRQ_HALF_RELOAD: half reload flag, this flag set when cnt count to rld/2 - * @arg PWM_IRQ_RELOAD: reload flag, this flag set when cnt count to rld value or when SYNCI assert - * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag - */ -static inline void pwm_clear_status(PWM_Type *pwm_x, uint32_t mask) -{ - pwm_x->SR |= mask; -} - -#if defined(PWM_SOC_TIMER_RESET_SUPPORT) && PWM_SOC_TIMER_RESET_SUPPORT - -/** - * @brief Reset timer and extension timer - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_timer_reset(PWM_Type *pwm_x) -{ - pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_TIMERRESET_MASK)) | PWM_GCR_TIMERRESET_SET(1)); -} - -#endif - -/** - * @brief get pwm status register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @retval uint32_t SR register value - */ -static inline uint32_t pwm_get_status(PWM_Type *pwm_x) -{ - return pwm_x->SR; -} - -/** - * @brief disable pwm irq - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] mask : - * @arg PWM_IRQ_FAULT: fault condition interrupt enable - * @arg PWM_IRQ_EX_RELOAD: extended reload flag interrupt enable - * @arg PWM_IRQ_HALF_RELOAD: half reload flag interrupt enable - * @arg PWM_IRQ_RELOAD: reload flag interrupt enable - * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag interrupt enable - */ -static inline void pwm_disable_irq(PWM_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQEN &= ~mask; -} - -/** - * @brief enable pwm irq - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] mask : - * @arg PWM_IRQ_FAULT: fault condition interrupt enable - * @arg PWM_IRQ_EX_RELOAD: extended reload flag interrupt enable - * @arg PWM_IRQ_HALF_RELOAD: half reload flag interrupt enable - * @arg PWM_IRQ_RELOAD: reload flag interrupt enable - * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag interrupt enable - */ -static inline void pwm_enable_irq(PWM_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQEN |= mask; -} - -/** - * @brief disable pwm dma request - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] mask : - * @arg PWM_IRQ_FAULT: fault condition DMA request enable - * @arg PWM_IRQ_EX_RELOAD: extended reload flag DMA request enable - * @arg PWM_IRQ_HALF_RELOAD: half reload flag DMA request enable - * @arg PWM_IRQ_RELOAD: reload flag DMA request enable - * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag DMA request enable - * - */ -static inline void pwm_disable_dma_request(PWM_Type *pwm_x, uint32_t mask) -{ - pwm_x->DMAEN &= ~mask; -} - -/** - * @brief enable pwm dma request - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] mask : - * @arg PWM_IRQ_FAULT: fault condition DMA request enable - * @arg PWM_IRQ_EX_RELOAD: extended reload flag DMA request enable - * @arg PWM_IRQ_HALF_RELOAD: half reload flag DMA request enable - * @arg PWM_IRQ_RELOAD: reload flag DMA request enable - * @arg PWM_IRQ_CMP(x)(x=0...n): comparator output compare or input capture flag DMA request enable - * - */ -static inline void pwm_enable_dma_request(PWM_Type *pwm_x, uint32_t mask) -{ - pwm_x->DMAEN |= mask; -} - -/** - * @brief set target cmp as hardware event to trigger force cmd output - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] target_cmp_index cmp index select one of the cmp as hardware event time to load FRCMD shadow registers [0-23] - */ -static inline void pwm_set_force_cmd_shadow_register_hwevent(PWM_Type *pwm_x, - uint8_t target_cmp_index) -{ - pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_FRCSHDWSEL_MASK)) - | PWM_SHCR_FRCSHDWSEL_SET(target_cmp_index)); -} -/** - * @note if trigger is not set to hardware event, target_cmp_index can be - * passed with any value - * - */ - -/** - * @brief set shadow register control register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] trigger select when the counter related shadow registers @ref pwm_shadow_register_update_trigger_t - * @param[in] target_cmp_index select one of the comparators as hardware event (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_set_load_counter_shadow_register_trigger(PWM_Type *pwm_x, - pwm_shadow_register_update_trigger_t trigger, - uint8_t target_cmp_index) -{ - if (trigger == pwm_shadow_register_update_on_hw_event) { - pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_CNTSHDWSEL_MASK - | PWM_SHCR_CNTSHDWUPT_MASK)) - | PWM_SHCR_CNTSHDWSEL_SET(target_cmp_index) - | PWM_SHCR_CNTSHDWUPT_SET(trigger)); - } else { - pwm_x->SHCR = ((pwm_x->SHCR & ~(PWM_SHCR_CNTSHDWUPT_MASK)) - | PWM_SHCR_CNTSHDWUPT_SET(trigger)); - } -} - -/** - * @brief Configure input capture cmp to trigger shadow register updates - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] is_falling_edge which edge is used as shadow register hardware load event - * @arg 1- falling edge - * @arg 0- rising edge - */ -static inline void pwm_load_cmp_shadow_on_capture(PWM_Type *pwm_x, - uint8_t index, - bool is_falling_edge) -{ - pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; - pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK | PWM_GCR_HWSHDWEDG_MASK)) - | PWM_GCR_CMPSHDWSEL_SET(index) - | PWM_GCR_HWSHDWEDG_SET(is_falling_edge)); -} - -#if defined(PWM_SOC_SHADOW_TRIG_SUPPORT) && PWM_SOC_SHADOW_TRIG_SUPPORT - -/** - * @brief RLD, STA shadow registers take effect at the reload point - * - * @param pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param is_enable true or false - */ -static inline void pwm_set_cnt_shadow_trig_reload(PWM_Type *pwm_x, bool is_enable) -{ - pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_RELOAD_MASK) - | PWM_SHCR_CNT_UPDATE_RELOAD_SET(is_enable)); -} - -/** - * @brief Set the timer shadow register to update the trigger edge - * - * @param[in] pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] is_falling_edge which edge is used as shadow register hardware load event - * @arg 1- falling edge - * @arg 0- rising edge - */ -static inline void pwm_set_cnt_shadow_trig_edge(PWM_Type *pwm_x, - bool is_falling_edge) -{ - pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_CNT_UPDATE_EDGE_MASK) - | PWM_SHCR_CNT_UPDATE_EDGE_SET(is_falling_edge)); -} - -/** - * @brief Set the force output shadow register to update the trigger edge - * - * @param[in] pwm_x pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] is_falling_edge which edge is used as shadow register hardware load event - * @arg 1- falling edge - * @arg 0- rising edge - */ -static inline void pwm_set_force_shadow_trig_edge(PWM_Type *pwm_x, - bool is_falling_edge) -{ - pwm_x->SHCR = ((pwm_x->SHCR & ~PWM_SHCR_FORCE_UPDATE_EDGE_MASK) - | PWM_SHCR_FORCE_UPDATE_EDGE_SET(is_falling_edge)); -} - -#endif -/** - * @brief disable pwn cmp half clock - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_cmp_disable_half_clock(PWM_Type *pwm_x, uint8_t index) -{ - pwm_x->CMP[index] &= ~PWM_CMP_CMPHLF_MASK; -} - -/** - * @brief enable pwm cmp half clock - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_cmp_enable_half_clock(PWM_Type *pwm_x, uint8_t index) -{ - pwm_x->CMP[index] |= PWM_CMP_CMPHLF_MASK; -} - -/** - * @brief update pwm cmp jitter counter compare value - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] jitter jitter value - */ -static inline void pwm_cmp_update_jitter_value(PWM_Type *pwm_x, uint8_t index, uint8_t jitter) -{ - pwm_x->CMP[index] = (pwm_x->CMP[index] & ~PWM_CMP_CMPJIT_MASK) | PWM_CMP_CMPJIT_SET(jitter); -} - -/** - * @brief update pwm cmp value - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] cmp clock counter compare value - * @param[in] ex_cmp extended counter compare value - */ -static inline void pwm_cmp_update_cmp_value(PWM_Type *pwm_x, uint8_t index, - uint32_t cmp, uint16_t ex_cmp) -{ - pwm_x->CMP[index] = (pwm_x->CMP[index] & ~(PWM_CMP_CMP_MASK | PWM_CMP_XCMP_MASK)) - | PWM_CMP_CMP_SET(cmp) | PWM_CMP_XCMP_SET(ex_cmp); -} - -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT -/** - * @brief update high-precision cmp value - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] cmp clock counter compare value - * @param[in] hrcmp high-precision pwm - */ -static inline void pwm_cmp_update_hrcmp_value(PWM_Type *pwm_x, uint8_t index, - uint32_t cmp, uint16_t hrcmp) -{ - pwm_x->CMP_HRPWM[index] = (pwm_x->CMP_HRPWM[index] & ~(PWM_CMP_HRPWM_CMP_MASK | PWM_CMP_HRPWM_CMP_HR_MASK)) - | PWM_CMP_HRPWM_CMP_SET(cmp) | PWM_CMP_HRPWM_CMP_HR_SET(hrcmp); -} -#endif - -/** - * @brief Forced update of pwm cmp register value, cmp content guaranteed accurate by user - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] cmp cmp register data - */ -static inline void pwm_cmp_force_value(PWM_Type *pwm_x, uint8_t index, uint32_t cmp) -{ - pwm_x->CMP[index] = cmp; -} - -/** - * @brief config pwm cmp - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] config @ref pwm_cmp_config_t - */ -static inline void pwm_config_cmp(PWM_Type *pwm_x, uint8_t index, pwm_cmp_config_t *config) -{ - pwm_shadow_register_unlock(pwm_x); - if (config->mode == pwm_cmp_mode_output_compare) { -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - if (config->enable_hrcmp) { - pwm_x->CMPCFG[index] = PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); - pwm_x->CMP[index] = PWM_CMP_HRPWM_CMP_SET(config->cmp) - | PWM_CMP_HRPWM_CMP_HR_SET(config->hrcmp); - } else { -#endif - pwm_x->CMPCFG[index] = (config->enable_ex_cmp ? PWM_CMPCFG_XCNTCMPEN_MASK : 0) - | PWM_CMPCFG_CMPSHDWUPT_SET(config->update_trigger); - pwm_x->CMP[index] = PWM_CMP_CMP_SET(config->cmp) - | PWM_CMP_XCMP_SET(config->ex_cmp) - | PWM_CMP_CMPHLF_SET(config->half_clock_cmp) - | PWM_CMP_CMPJIT_SET(config->jitter_cmp); -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - } -#endif - } else { - pwm_x->CMPCFG[index] |= PWM_CMPCFG_CMPMODE_MASK; - } -} - -/** - * @brief config pwm output channel - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] config @ref pwm_output_channel_t - */ -static inline void pwm_config_output_channel(PWM_Type *pwm_x, uint8_t index, pwm_output_channel_t *config) -{ - pwm_x->CHCFG[index] = PWM_CHCFG_CMPSELBEG_SET(config->cmp_start_index) - | PWM_CHCFG_CMPSELEND_SET(config->cmp_end_index) - | PWM_CHCFG_OUTPOL_SET(config->invert_output); -} - -/** - * @brief config pwm fault source - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] config @ref pwm_fault_source_config_t - */ -static inline void pwm_config_fault_source(PWM_Type *pwm_x, pwm_fault_source_config_t *config) -{ - pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FAULTI0EN_MASK | PWM_GCR_FAULTI1EN_MASK - | PWM_GCR_FAULTI2EN_MASK | PWM_GCR_FAULTI3EN_MASK - | PWM_GCR_FAULTE0EN_MASK | PWM_GCR_FAULTE1EN_MASK - | PWM_GCR_FAULTRECEDG_MASK | PWM_GCR_FAULTEXPOL_MASK - | PWM_GCR_FAULTRECHWSEL_MASK)) - | config->source_mask - | PWM_GCR_FAULTEXPOL_SET((config->fault_external_0_active_low ? 0x1 : 0) | (config->fault_external_1_active_low ? 0x2 : 0)) - | PWM_GCR_FAULTRECEDG_SET(config->fault_recover_at_rising_edge) - | PWM_GCR_FAULTRECHWSEL_SET(config->fault_output_recovery_trigger); -} - -/** - * @brief clear pwm fault status - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_clear_fault(PWM_Type *pwm_x) -{ - pwm_x->GCR |= PWM_GCR_FAULTCLR_MASK; - pwm_x->GCR &= ~PWM_GCR_FAULTCLR_MASK; -} - -/** - * @brief stop the pwm timer counter - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_stop_counter(PWM_Type *pwm_x) -{ - pwm_x->GCR &= ~PWM_GCR_CEN_MASK; -} - -/** - * @brief start pwm timer counter - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_start_counter(PWM_Type *pwm_x) -{ - pwm_x->GCR |= PWM_GCR_CEN_MASK; -} - -/** - * @brief enable software force - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_enable_sw_force(PWM_Type *pwm_x) -{ - pwm_x->GCR |= PWM_GCR_SWFRC_MASK; -} - -/** - * @brief disable software force , force will take effect - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_disable_sw_force(PWM_Type *pwm_x) -{ - pwm_x->GCR &= ~PWM_GCR_SWFRC_MASK; -} - -/** - * @brief enable pwm reload value by synci - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwm_enable_reload_at_synci(PWM_Type *pwm_x) -{ - pwm_x->GCR |= PWM_GCR_XRLDSYNCEN_MASK | PWM_GCR_RLDSYNCEN_MASK; -} - -/** - * @brief disable pwm output - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index pwm index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_disable_output(PWM_Type *pwm_x, uint8_t index) -{ - pwm_x->PWMCFG[index] &= ~PWM_PWMCFG_OEN_MASK; -} - -/** - * @brief enable pwm output - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index pwm index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_enable_output(PWM_Type *pwm_x, uint8_t index) -{ - pwm_x->PWMCFG[index] |= PWM_PWMCFG_OEN_MASK; -} - -/** - * @brief config pwm force output level per output channel - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] output_mask PWM output channel force level, set it using the macro - * @arg PWM_FORCE_OUTPUT(pwm_index, force_output) - */ -static inline void pwm_set_force_output(PWM_Type *pwm_x, uint32_t output_mask) -{ - pwm_x->FRCMD = PWM_FRCMD_FRCMD_SET(output_mask); -} - -/** - * @brief config pwm force polarity - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] polarity polarity of input pwm_force - * @arg 1- active low - * @arg 0- active high - */ -static inline void pwm_config_force_polarity(PWM_Type *pwm_x, bool polarity) -{ - pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FRCPOL_MASK)) | PWM_GCR_FRCPOL_SET(polarity); -} - -/** - * @brief config the force effective time - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] timing @ref pwm_force_cmd_timing_t - */ -static inline void pwm_config_force_cmd_timing(PWM_Type *pwm_x, pwm_force_cmd_timing_t timing) -{ - pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_FRCTIME_MASK)) | PWM_GCR_FRCTIME_SET(timing); -} - -/** - * @brief enable pwm sw force output - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index pwm cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_enable_pwm_sw_force_output(PWM_Type *pwm_x, uint8_t index) -{ - pwm_x->PWMCFG[index] |= PWM_PWMCFG_OEN_MASK | PWM_PWMCFG_FRCSRCSEL_MASK - | PWM_PWMCFG_FRCSHDWUPT_SET(pwm_shadow_register_update_on_modify); -} - -/** - * @brief disable pwm sw force output - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index pwm cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - */ -static inline void pwm_disable_pwm_sw_force_output(PWM_Type *pwm_x, uint8_t index) -{ - pwm_x->PWMCFG[index] &= ~PWM_PWMCFG_FRCSRCSEL_MASK; -} - -/** - * @brief config PWM channel configure registe - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index pwm channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] config @ref pwm_config_t - * @param[in] enable_pair_mode enable pair mode - * @arg 1- PWM output is in pair mode - * @arg 0- PWM output is in indepandent mode - */ -static inline void pwm_config_pwm(PWM_Type *pwm_x, uint8_t index, - pwm_config_t *config, bool enable_pair_mode) -{ - pwm_x->PWMCFG[index] = PWM_PWMCFG_OEN_SET(config->enable_output) - | PWM_PWMCFG_FRCSHDWUPT_SET(config->update_trigger) - | PWM_PWMCFG_FAULTMODE_SET(config->fault_mode) - | PWM_PWMCFG_FAULTRECTIME_SET(config->fault_recovery_trigger) - | PWM_PWMCFG_FRCSRCSEL_SET(config->force_source) - | PWM_PWMCFG_PAIR_SET(enable_pair_mode) -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - | PWM_PWMCFG_HR_UPDATE_MODE_SET(config->hrpwm_update_mode) -#endif - | PWM_PWMCFG_DEADAREA_SET(config->dead_zone_in_half_cycle); -} - -/** - * @brief getting the counter reload value for a pwm timer - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @retval pwm reload value - */ -static inline uint32_t pwm_get_reload_val(PWM_Type *pwm_x) -{ - return PWM_RLD_RLD_GET(pwm_x->RLD); -} - -/** - * @brief getting the extended counter reload value for a pwm timer - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @retval pwm extended reload value - */ -static inline uint32_t pwm_get_ex_reload_val(PWM_Type *pwm_x) -{ - return PWM_RLD_XRLD_GET(pwm_x->RLD); -} - -/** - * @brief getting the value of the pwm counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @retval pwm counter value - */ -static inline uint32_t pwm_get_counter_val(PWM_Type *pwm_x) -{ - return PWM_CNT_CNT_GET(pwm_x->CNT); -} - -/** - * @brief getting the value of the pwm extended counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @retval pwm counter value - */ -static inline uint32_t pwm_get_ex_counter_val(PWM_Type *pwm_x) -{ - return PWM_CNT_XCNT_GET(pwm_x->CNT); -} - -/** - * @brief pwm load cmp shadow on match - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] index cmp index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] config @ref pwm_cmp_config_t - * @retval status_invalid_argument or status_success - */ -hpm_stat_t pwm_load_cmp_shadow_on_match(PWM_Type *pwm_x, - uint8_t index, - pwm_cmp_config_t *config); - -/** - * @brief pwm get captured count - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[out] buf count value - * @param[in] counter @ref pwm_counter_type_t - * @param[in] start_index start capture index (0..(PWM_SOC_CMP_MAX_COUNT-1)) - * @param[in] num capture num (1..PWM_SOC_CMP_MAX_COUNT) - */ -void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t counter, uint8_t start_index, uint8_t num); - -/** - * @brief get default cmp config - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[out] config @ref pwm_cmp_config_t - */ -void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config); - -/** - * @brief get default output channel config - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[out] config @ref pwm_output_channel_t - */ -void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t *config); - -/** - * @brief get default pwm config - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[out] config @ref pwm_config_t - */ -void pwm_get_default_pwm_config(PWM_Type *pwm_x, pwm_config_t *config); - -/** - * @brief get default pwm pair config - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[out] config @ref pwm_pair_config_t - */ -void pwm_get_default_pwm_pair_config(PWM_Type *pwm_x, pwm_pair_config_t *config); - -/** - * @brief setup waveform - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] pwm_index pwm channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] pwm_config @ref pwm_config_t - * @param[in] cmp_start_index pwm cmp index (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] cmp @ref pwm_cmp_config_t - * @param[in] cmp_num cmp num (1..PWM_SOC_CMP_MAX_COUNT), cmp[cmp_num-1] must not overflow - * @retval hpm_stat_t - */ -hpm_stat_t pwm_setup_waveform(PWM_Type *pwm_x, - uint8_t pwm_index, pwm_config_t *pwm_config, - uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num); -/** - * @brief setup pwm waveform in pair - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] pwm_index pwm channel index (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] pwm_pair_config @ref pwm_pair_config_t - * @param[in] cmp_start_index pwm cmp index (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] cmp @ref pwm_cmp_config_t - * @param[in] cmp_num cmp num (1..PWM_SOC_CMP_MAX_COUNT), cmp[cmp_num-1] must not overflow - * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success - */ -hpm_stat_t pwm_setup_waveform_in_pair(PWM_Type *pwm_x, - uint8_t pwm_index, pwm_pair_config_t *pwm_pair_config, - uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num); - -/** - * @brief update raw compare value for edge aligned waveform - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] cmp_index index of cmp to be adjusted (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] target_cmp target compare value - * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success - */ -hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, - uint32_t target_cmp); - -/** - * @brief update raw compare value for central aligned waveform - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must be even number) - * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must be odd number) - * @param[in] target_cmp1 target compare value for cmp1 - * @param[in] target_cmp2 target compare value for cmp2 - * @retval hpm_stat_t @ref status_invalid_argument or @ref status_success cmp1_index - */ -hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, - uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2); -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - -/** - * @brief recovery hrpwm output - * - * @param pwm_x @ref PWM_Type PWM base address - */ -static inline void pwm_recovery_hrpwm_output(PWM_Type *pwm_x) -{ - pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_SW_EN_MASK; - pwm_x->ANA_CFG0 |= PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK; - pwm_x->ANA_CFG0 &= ~PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK; - pwm_x->ANA_CFG0 |= PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK; - pwm_x->ANA_CFG0 &= ~PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK; - pwm_x->HRPWM_CFG &= ~PWM_HRPWM_CFG_CAL_SW_EN_MASK; -} - -/** - * @brief Enable high-precision pwm - * - * @param[in] pwm_x @ref PWM_Type PWM base address - */ -static inline void pwm_enable_hrpwm(PWM_Type *pwm_x) -{ - pwm_x->GCR = (pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK)) | PWM_GCR_HR_PWM_EN_SET(1); -} - -/** - * @brief Disable high-precision pwm - * - * @param[in] pwm_x @ref PWM_Type PWM base address - */ -static inline void pwm_disable_hrpwm(PWM_Type *pwm_x) -{ - pwm_x->GCR = pwm_x->GCR & ~(PWM_GCR_HR_PWM_EN_MASK); -} - -/** - * @brief Calibrate all channels of hrpwm - * - * @param[in] pwm_x @ref PWM_Type PWM base address - */ -static inline void pwm_cal_hrpwm_start(PWM_Type *pwm_x) -{ - pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_MASK; -} - -/** - * @brief Calibrate specified hrpwm channels - * - * @param[in] pwm_x @ref PWM_Type PWM base address - * @param[in] chn Channel number - */ -static inline void pwm_cal_hrpwm_chn_start(PWM_Type *pwm_x, uint8_t chn) -{ - pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_START_SET(chn); -} - -/** - * @brief Wait for the completion of calibration of the specified channel of high-precision PWM, blocking - * - * @param[in] pwm_x @ref PWM_Type PWM base address - * @param[in] chn Channel number - */ -static inline void pwm_cal_hrpwm_chn_wait(PWM_Type *pwm_x, uint8_t chn) -{ - while (PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn])) { - }; -} - -/** - * @brief get calibration status - * - * @param[in] pwm_x pwm_x @ref PWM_Type PWM base address - * @param[in] chn Channel number - * @return uint32_t finished will be set zero. - */ -static inline uint32_t pwm_get_cal_hrpwm_status(PWM_Type *pwm_x, uint8_t chn) -{ - return PWM_ANASTS_CALON_GET(pwm_x->ANASTS[chn]); -} - -/** - * @brief getting the counter reload value for hrpwm counter - * - * @param pwm_x pwm_x @ref PWM_Type PWM base address - * @return uint32_t hrpwm reload - */ -static inline uint32_t pwm_get_hrpwm_reload_val(PWM_Type *pwm_x) -{ - return PWM_RLD_HRPWM_RLD_GET(pwm_x->RLD_HRPWM); -} - -/** - * @brief getting the counter reload value for hrpwm hr counter - * - * @param pwm_x pwm_x @ref PWM_Type PWM base address - * @return uint32_t hrpwm hr reload - */ -static inline uint32_t pwm_get_hrpwm_hr_reload_val(PWM_Type *pwm_x) -{ - return PWM_RLD_HRPWM_RLD_HR_GET(pwm_x->RLD_HRPWM); -} - - -/** - * @brief update raw high-precision compare value for edge aligned waveform - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] cmp_index index of cmp to be adjusted (0..(PWM_SOC_PWM_MAX_COUNT-1)) - * @param[in] target_cmp target compare value - * @param[in] target_hrcmp target high-precision compare value - * @return hpm_stat_t - */ -hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, - uint16_t target_hrcmp); - -/** - * @brief update raw high-precision compare value for central aligned waveform - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param[in] cmp1_index index of cmp1 to be adjusted (cmp1_index must be even number) - * @param[in] cmp2_index index of cmp2 to be adjusted (cmp2_index must be odd number) - * @param[in] target_cmp1 target compare value for cmp1 - * @param[in] target_cmp2 target compare value for cmp2 - * @param[in] target_hrcmp1 target high-precision compare value for cmp1 - * @param[in] target_hrcmp2 target high-precision compare value for cmp2 - * @return hpm_stat_t - */ -hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, - uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2, - uint16_t target_hrcmp1, uint16_t target_hrcmp2); -#endif - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_PWM_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwmv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwmv2_drv.h deleted file mode 100644 index ac097d89e4b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwmv2_drv.h +++ /dev/null @@ -1,1958 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PWMV2_DRV_H -#define HPM_PWMV2_DRV_H - -#include "hpm_common.h" -#include "hpm_pwmv2_regs.h" -#include "hpm_soc_feature.h" - - -/** - * @brief PWM driver APIs - * @defgroup pwmv2_interface PWMV2 driver APIs - * @ingroup motor_interfaces - * @{ - * - */ -#define PWM_UNLOCK_KEY (0xB0382607UL) -#define PWM_CMP_UNABLE_OUTPUT_INDEX (16) - -/* IRQ enable bit mask */ -#define PWM_IRQ_FAULT PWM_IRQEN_FAULTIRQE_MASK -#define PWM_IRQ_EX_RELOAD PWM_IRQEN_XRLDIRQE_MASK -#define PWM_IRQ_HALF_RELOAD PWM_IRQEN_HALFRLDIRQE_MASK -#define PWM_IRQ_RELOAD PWM_IRQEN_RLDIRQE_MASK -#define PWM_IRQ_CMP(x) PWM_IRQEN_CMPIRQEX_SET((1 << x)) - -/* PWM force output mask */ -#define PWM_FORCE_OUTPUT(pwm_index, force_output) \ - (force_output << (pwm_index << 1)) - -#define PWM_DUTY_CYCLE_FP_MAX ((1U << 24) - 1) - -#ifndef PWMV2_SOC_CAL_COUNT_MAX - #define PWMV2_SOC_CAL_COUNT_MAX 8 -#endif - -#define PWMV2_SHADOW_INDEX(x) PWMV2_SHADOW_VAL_##x -#define PWMV2_CMP_INDEX(x) PWMV2_CMP_VAL_WORK_##x -#define PWMV2_CALCULATE_INDEX(x) PWMV2_CAL_##x -#define PWMV2_CAL_SHADOW_OFFSET_ZERO (31) - -typedef enum { - pwm_counter_0 = 0, - pwm_counter_1 = 1, - pwm_counter_2 = 2, - pwm_counter_3 = 3, -} pwm_counter_t; - -typedef enum { - pwm_channel_0 = 0, - pwm_channel_1 = 1, - pwm_channel_2 = 2, - pwm_channel_3 = 3, - pwm_channel_4 = 4, - pwm_channel_5 = 5, - pwm_channel_6 = 6, - pwm_channel_7 = 7, -} pwm_channel_t; - - -typedef enum { - pwm_reload_update_on_shlk = 0, - pwm_reload_update_on_compare_point = 1, - pwm_reload_update_on_reload = 2, - pwm_reload_update_on_trigger = 3, -} pwm_reload_update_time_t; - - -/** - * @brief pwm output type - * - */ -typedef enum { - pwm_force_output_0 = 0, /**< output 0 */ - pwm_force_output_1 = 1, /**< output 1 */ - pwm_force_output_high_z = 2, /**< output */ - pwm_force_output_no_force = 3, -} pwm_force_mode_t; - -typedef enum { - pwm_fault_output_0 = 0, /**< output 0 */ - pwm_fault_output_1 = 1, /**< output 1 */ - pwm_fault_output_high_z = 2, /**< output */ -} pwm_fault_mode_t; - -typedef enum { - pad_fault_active_low = 1, - pad_fault_active_high = 0, -} pwm_fault_pad_polarity_t; - -typedef enum { - pwm_shadow_register_output_polarity_on_shlk = 0, - pwm_shadow_register_output_polarity_on_reload = 1, -} pwm_shadow_register_output_polarity_t; - -typedef enum { - pwm_force_update_shadow_immediately = 0, /**< after software set shlk bit of shlk register */ - pwm_force_update_shadow_at_cmp_point = 1, - pwm_force_update_shadow_at_reload = 2, /**< immediately after the register being modified */ - pwm_force_update_shadow_none = 3, /**< after SHSYNCI assert */ -} pwm_force_shadow_trigger_t; - -typedef enum { - pwm_force_immediately = 0, /**< after software set shlk bit of shlk register */ - pwm_force_at_reload = 1, - pwm_force_at_trigmux = 2, - pwm_force_none = 3, /**< after SHSYNCI assert */ -} pwm_force_trigger_t; - - -typedef enum { - pwm_logic_four_cmp_or = 0, - pwm_logic_four_cmp_and = 1, - pwm_logic_four_cmp_xor = 2, - pwm_logic_four_cmp_cd = 3, -} pwm_logic_four_cmp_cfg_t; - -/** - * @brief select when to recover PWM output after fault - * - */ -typedef enum { - pwm_fault_recovery_immediately = 0, /**< immediately*/ - pwm_fault_recovery_on_reload = 1, /**< after pwm timer counter reload time*/ - pwm_fault_recovery_on_hw_event = 2, /**< after hardware event assert*/ - pwm_fault_recovery_on_fault_clear = 3, /**< after software write faultclr bit in GCR register*/ -} pwm_fault_recovery_trigger_t; - -typedef enum { - pwm_dac_channel_0 = 0, - pwm_dac_channel_1 = 1, - pwm_dac_channel_2 = 2, - pwm_dac_channel_3 = 3, -} pwm_dac_channel_t; - -typedef enum { - pwm_capture_from_trigmux = 0, - pwm_capture_from_gpio = 1 -} pwm_capture_input_select_t; - -typedef enum { - pwm_dma_0 = 0, - pwm_dma_1 = 1, - pwm_dma_2 = 2, - pwm_dma_3 = 3, -} pwm_dma_chn_t; - -typedef enum { - pwm_shadow_register_update_on_shlk = 0, /**< after software set shlk bit of shlk register*/ - pwm_shadow_register_update_on_modify = 1, /**< immediately after the register being modified*/ - pwm_shadow_register_update_on_reload = 2, - pwm_shadow_register_update_on_trigmux = 3, - pwm_shadow_register_update_on_rld_cmp_select0 = 4, - pwm_shadow_register_update_on_rld_cmp_select1 = 5, - pwm_shadow_register_update_on_none = 6 -} pwm_cmp_shadow_register_update_trigger_t; - -typedef enum { - cmp_value_from_shadow_val = 0, - cmp_value_from_calculate = 0x20, - cmp_value_from_capture_posedge = 0x30, - cmp_value_from_counters = 0x38, - cmp_value_fffff000 = 0x3e, - cmp_value_ffffff00 = 0x3f -} pwm_cmp_source_t; - -/** - * @brief pwm compare config - * - */ -typedef struct pwmv2_cmp_config { - uint32_t cmp; /**< compare value */ - bool enable_half_cmp; /**< enable half compare value */ - bool enable_hrcmp; /**< enable high precision pwm */ - pwm_cmp_source_t cmp_source; /**< @ref pwm_cmp_source_t */ - pwm_counter_t cmp_use_counter; /**< select one from 4 counters, only for CMP_N>=16 */ - uint8_t cmp_source_index; /**< soure index */ - uint8_t mode; /**< compare work mode: pwm_cmp_mode_output_compare or pwm_cmp_mode_input_capture */ - pwm_cmp_shadow_register_update_trigger_t update_trigger; /**< compare configuration update trigger, need update trigger use pwm_shadow_register_update_on_trigmux */ - uint8_t update_trigger_index; /**< select one trigger from 8, should set to pulse in trig_mux */ - uint8_t hrcmp; /**< high precision pwm */ -} pwmv2_cmp_config_t; - -/** - * @brief pwm fault source config - * - */ -typedef struct pwmv2_async_fault_source_config { - uint8_t async_signal_from_pad_index; /**< select from 16bit async fault from pad*/ - pwm_fault_pad_polarity_t fault_async_pad_level; /**< fault polarity for input fault from pad, 1-active low; 0-active high */ -} pwmv2_async_fault_source_config_t; - -/** - * @brief pwm config data - * - */ -typedef struct pwmv2_config { - bool enable_output; /**< enable pwm output */ - bool enable_async_fault; /**< enable the input async faults from pad directly */ - bool enable_sync_fault; /**< enable the input faults from trig_mux */ - bool invert_output; /**< invert pwm output level */ - bool enable_four_cmp; /**< Enable the four cmp functions */ - pwmv2_async_fault_source_config_t async_fault_source; - pwm_shadow_register_output_polarity_t update_polarity_time; - pwm_logic_four_cmp_cfg_t logic; /**< valid only for pwm0/2/4/6 when trig_sel4 is set */ - uint8_t update_trigger; /**< pwm config update trigger */ - uint8_t fault_mode; /**< fault mode */ - pwm_fault_recovery_trigger_t fault_recovery_trigger; /**< fault recoverty trigger */ - uint8_t fault_recovery_trigmux_index; /**< select one trigger from 8, should set to pulse in trig_mux */ - uint8_t force_shadow_trigmux_index; /**< select one trigger from 8, should set to pulse in trig_mux */ - pwm_force_shadow_trigger_t force_shadow_trigger; /**< will load shadow register(force)mode) to force_mode_work at this time */ - uint8_t force_trigmux_index; /**< select one trigger from 8 as force signal */ - pwm_force_trigger_t force_trigger; /**< @ref pwm_force_trigger_t */ - uint32_t dead_zone_in_half_cycle; /**< dead zone in half cycle*/ -} pwmv2_config_t; - -/** - * @brief pair pwm config - * - */ -typedef struct pwmv2_pair_config { - pwmv2_config_t pwm[2]; /**< pwm config data */ -} pwmv2_pair_config_t; - -typedef struct pwmv2_cmp_calculate_cfg { - uint8_t counter_index; /**< select one of 4 counter reload time */ - uint8_t in_index; /**< 0~3 to select one of the dac input value; 4~7 to select one of the current counter value */ - uint8_t in_offset_index; /**< from one of the shadow_val */ - int8_t t_param; /**< period parameter */ - int8_t d_param; /**< dac/counter value parameter */ - int8_t up_limit_param; - uint8_t up_limit_offset_index; /**< from one of the shadow_val */ - int8_t low_limit_param; - uint8_t low_limit_offset_index; /**< from one of the shadow_val */ - bool enable_up_limit; - bool enbale_low_limit; -} pwmv2_cmp_calculate_cfg_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief pwm deinitialize function - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - * - */ -void pwmv2_deinit(PWMV2_Type *pwm_x); - -/** - * @brief issue all shawdow register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_issue_shadow_register_lock_event(PWMV2_Type *pwm_x) -{ - pwm_x->WORK_CTRL1 |= PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK; -} - -/** - * @brief lock all shawdow register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_shadow_register_lock(PWMV2_Type *pwm_x) -{ - pwm_x->WORK_CTRL1 |= PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK; -} - -/** - * @brief select one trigger from 8, set to use input signal(selected by cnt_reload_trig) to reload timer - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param trig_index one trigger from 8 - */ -static inline void pwmv2_set_counter_reload_trigmux_index(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t trig_index) -{ - pwm_x->CNT[counter].CFG2 = (pwm_x->CNT[counter].CFG2 & ~PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) | PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET(trig_index); -} - -/** - * @brief Multiple counters are enabled at the same time - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask bit0 - cnt0, bit1 - cnt1, bitn - cntn, n==3 - */ -static inline void pwmv2_enable_multi_counter_sync(PWMV2_Type *pwm_x, uint8_t mask) -{ - pwm_x->CNT_GLBCFG &= ~(PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET(mask)); - fencerw(); - pwm_x->CNT_GLBCFG |= PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET(mask); -} - -/** - * @brief Multiple pwm out at the same time - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask bit0 - cnt0, bit1 - cnt1, bitn - cntn, n==3 - */ -static inline void pwmv2_start_pwm_output_sync(PWMV2_Type *pwm_x, uint8_t mask) -{ - pwm_x->CNT_GLBCFG |= PWMV2_CNT_GLBCFG_CNT_SW_START_SET(mask); -} - -/** - * @brief unlock all shadow register - * - * @param[in] pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_shadow_register_unlock(PWMV2_Type *pwm_x) -{ - pwm_x->WORK_CTRL0 = PWM_UNLOCK_KEY; -} - -/** - * @brief The shadow registers can be updated only when related unlock_bit is set. - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask bit2 to bit 29 for value_shadow, bit30 for force_mode, bit31 for polarity. - */ -static inline void pwmv2_shadow_unlock_bit_mask(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->UNLOCK = mask; -} - -/** - * @brief Set the value of the shadow register - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param index shadow index - * @param value normal value (24bit) - * @param high_resolution_tick High precision pwm values (0 -255) - * @param enable_half_cycle half-cycle pwm - */ -static inline void pwmv2_set_shadow_val(PWMV2_Type *pwm_x, uint8_t index, uint32_t value, uint8_t high_resolution_tick, bool enable_half_cycle) -{ - pwm_x->SHADOW_VAL[index] = PWMV2_SHADOW_VAL_VALUE_SET(((value << 8) | (enable_half_cycle << 7) | (high_resolution_tick))); -} - -/** - * @brief force pwm output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param mode @ref pwm_force_mode_t - * @param invert 0 - low level, 1 - high level - */ -static inline void pwmv2_force_output(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_force_mode_t mode, bool invert) -{ - pwm_x->FORCE_MODE = (pwm_x->FORCE_MODE & ~(PWMV2_FORCE_MODE_POLARITY_SET((1 << (chn << 1))) | PWMV2_FORCE_MODE_FORCE_MODE_SET((3 << (chn << 1))))) | - PWMV2_FORCE_MODE_POLARITY_SET((invert << (chn << 1))) | - PWMV2_FORCE_MODE_FORCE_MODE_SET((mode << (chn << 1))); -} - -/** - * @brief enable four pwm outputs - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_four_cmp(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 |= PWMV2_PWM_CFG0_TRIG_SEL4_MASK; -} - -/** - * @brief disable four pwm outputs - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_four_cmp(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 &= ~PWMV2_PWM_CFG0_TRIG_SEL4_MASK; -} - -/** - * @brief Direct selection of the fail signal from the pin - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param pad_index motor pad - */ -static inline void pwmv2_fault_signal_select_from_pad(PWMV2_Type *pwm_x, pwm_channel_t chn, uint8_t pad_index) -{ - pwm_x->PWM[chn].CFG0 = (pwm_x->PWM[chn].CFG0 & ~PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) | PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET(pad_index); -} - -/** - * @brief Configure the polarity of the fail signal - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param polarity @ref pwm_fault_pad_polarity_t - */ -static inline void pwmv2_fault_signal_polarity(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_fault_pad_polarity_t polarity) -{ - pwm_x->PWM[chn].CFG0 = (pwm_x->PWM[chn].CFG0 & ~PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) | PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET(polarity); -} - -/** - * @brief Enable the fault signal from the pin - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_fault_from_pad(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 |= PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK; -} - -/** - * @brief Disable the fault signal from the pin - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_fault_from_pad(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 &= ~PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK; -} - -/** - * @brief Enable the fault signal from the trigmux - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_fault_from_trigmux(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 |= PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK; -} - -/** - * @brief Disable the fault signal from the trigmux - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_fault_from_trigmux(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 &= ~PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK; -} - -/** - * @brief Enable pwm output invert - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_output_invert(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 |= PWMV2_PWM_CFG0_OUT_POLARITY_MASK; -} - -/** - * @brief Disable pwm output invert - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_output_invert(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 &= ~PWMV2_PWM_CFG0_OUT_POLARITY_MASK; -} - -/** - * @brief Enable invert operations via shadow registers - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param update_select @ref pwm_shadow_register_output_polarity_t - */ -static inline void pwmv2_enable_invert_by_shadow(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_shadow_register_output_polarity_t update_select) -{ - pwm_x->PWM[chn].CFG0 |= PWMV2_PWM_CFG0_POLARITY_OPT0_MASK; - pwm_x->PWM[chn].CFG0 = (pwm_x->PWM[chn].CFG0 & ~PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) | PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET(update_select); -} - -/** - * @brief Disable invert operations via shadow registers - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param update_select @ref pwm_shadow_register_output_polarity_t - */ -static inline void pwmv2_disable_invert_by_shadow(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG0 &= ~PWMV2_PWM_CFG0_POLARITY_OPT0_MASK; -} - -/** - * @brief Enable pwm output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_channel_enable_output(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 |= PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK; -} - -/** - * @brief Disable pwm output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_channel_disable_output(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 &= ~PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK; -} - -/** - * @brief Forces the output configuration to be updated from the time shadow hosting takes effect - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param update_time @ref pwm_force_shadow_trigger_t - */ -static inline void pwmv2_force_update_time_by_shadow(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_force_shadow_trigger_t update_time) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) | PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET(update_time); -} - -/** - * @brief set the fault mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param mode @ref pwm_fault_mode_t - */ -static inline void pwmv2_set_fault_mode(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_fault_mode_t mode) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FAULT_MODE_MASK) | PWMV2_PWM_CFG1_FAULT_MODE_SET(mode); -} - -/** - * @brief Set the fault mode recovery time - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param trig @ref pwm_fault_recovery_trigger_t - */ -static inline void pwmv2_set_fault_recovery_time(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_fault_recovery_trigger_t trig) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) | PWMV2_PWM_CFG1_FAULT_REC_TIME_SET(trig); -} - -/** - * @brief Trigger forced mode by hardware signal - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_force_by_hardware(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 &= ~PWMV2_PWM_CFG1_SW_FORCE_EN_MASK; -} - -/** - * @brief Enable force mode triggered by software - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_force_by_software(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 |= PWMV2_PWM_CFG1_SW_FORCE_EN_MASK; -} - -/** - * @brief Disable force mode triggered by software - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_force_by_software(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 &= ~PWMV2_PWM_CFG1_SW_FORCE_EN_MASK; -} - -/** - * @brief Enable pwm complementary mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_pair_mode(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 |= PWMV2_PWM_CFG1_PAIR_MODE_MASK; -} - -/** - * @brief Disable pwm complementary mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_pair_mode(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->PWM[chn].CFG1 &= ~PWMV2_PWM_CFG1_PAIR_MODE_MASK; -} - -/** - * @brief Configure the logic between the 4 cmp, valid only if the 4 cmp output is enabled - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param logic @ref pwm_logic_four_cmp_cfg_t - */ -static inline void pwmv2_set_four_cmp_logic(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_logic_four_cmp_cfg_t logic) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_PWM_LOGIC_MASK) | PWMV2_PWM_CFG1_PWM_LOGIC_SET(logic); -} - -/** - * @brief Setting the effective time of forced output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param time @ref pwm_force_trigger_t - */ -static inline void pwmv2_set_force_update_time(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_force_trigger_t time) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FORCE_TIME_MASK) | PWMV2_PWM_CFG1_FORCE_TIME_SET(time); -} - -/** - * @brief Selecting trigmux's signal as a forced mode trigger source - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param trigmux_index trigmux index - */ -static inline void pwmv2_trig_force_mode_select_trigmux_index(PWMV2_Type *pwm_x, pwm_channel_t chn, uint8_t trigmux_index) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) | PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET(trigmux_index); -} - -/** - * @brief Selection of trigger signals for software or hardware trigmux - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param trigmux_index select one trigger from 8 - */ -static inline void pwmv2_trig_force_hardware_or_software_select_trigmux_index(PWMV2_Type *pwm_x, pwm_channel_t chn, uint8_t trigmux_index) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) | PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET(trigmux_index); -} - -/** - * @brief Select the trigger source that forces the output to take effect - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param trigmux_index select one trigger from 8 - */ -static inline void pwmv2_select_force_trigmux_index(PWMV2_Type *pwm_x, pwm_channel_t chn, uint8_t trigmux_index) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) | PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET(trigmux_index); -} - -/** - * @brief Selection of trigger signal for fault recovery - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param trigmux_index select one trigger from 8 - */ -static inline void pwmv2_select_recovery_fault_trigmux_index(PWMV2_Type *pwm_x, pwm_channel_t chn, uint8_t trigmux_index) -{ - pwm_x->PWM[chn].CFG1 = (pwm_x->PWM[chn].CFG1 & ~PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) | PWMV2_PWM_CFG1_FAULT_REC_SEL_SET(trigmux_index); -} - -/** - * @brief set pwm dead area - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param dead dead area time - */ -static inline void pwmv2_set_dead_area(PWMV2_Type *pwm_x, pwm_channel_t chn, uint32_t dead) -{ - pwm_x->PWM[chn].DEAD_AREA = PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET((dead << 8)); -} - -/** - * @brief Setting the comparator as an input to trigmux - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param trigmux_chn @ref pwm_channel_t - * @param cmp_index cmp index - */ -static inline void pwmv2_set_trigout_cmp_index(PWMV2_Type *pwm_x, pwm_channel_t trigmux_chn, uint8_t cmp_index) -{ - pwm_x->TRIGGER_CFG[trigmux_chn] = (pwm_x->TRIGGER_CFG[trigmux_chn] & ~PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) | PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET(cmp_index); -} - -/** - * @brief Enable software forced output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_enable_software_force(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->GLB_CTRL |= PWMV2_GLB_CTRL_SW_FORCE_SET((1 << chn)); -} - -/** - * @brief Disable software forced output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_disable_software_force(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->GLB_CTRL &= ~(PWMV2_GLB_CTRL_SW_FORCE_SET((1 << chn))); -} - -#ifdef PWM_SOC_HRPWM_SUPPORT - -/** - * @brief Add a delay after deadband, 0-255ths of a clock cycle - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param delay_tick 0-255 - */ -static inline void pwmv2_add_delay_tick_after_dead_area(PWMV2_Type *pwm_x, uint8_t delay_tick) -{ - pwm_x->GLB_CTRL = (pwm_x->GLB_CTRL & ~PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) | PWMV2_GLB_CTRL_OUTPUT_DELAY_SET(delay_tick); -} - -/** - * @brief Enable high precision pwm - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_enable_hrpwm(PWMV2_Type *pwm_x) -{ - pwm_x->GLB_CTRL |= PWMV2_GLB_CTRL_HR_PWM_EN_MASK; -} - -/** - * @brief Disable high precision pwm - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_disable_hrpwm(PWMV2_Type *pwm_x) -{ - pwm_x->GLB_CTRL &= ~PWMV2_GLB_CTRL_HR_PWM_EN_MASK; -} - -#endif - -/** - * @brief Enable the software dac mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dac_index @ref pwm_dac_channel_t - */ -static inline void pwmv2_enable_software_dac_mode(PWMV2_Type *pwm_x, pwm_dac_channel_t dac_index) -{ - pwm_x->GLB_CTRL2 |= PWMV2_GLB_CTRL2_DAC_SW_MODE_SET((1 << dac_index)); -} - -/** - * @brief Disable the software dac mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dac_index @ref pwm_dac_channel_t - */ -static inline void pwmv2_disable_software_dac_mode(PWMV2_Type *pwm_x, pwm_dac_channel_t dac_index) -{ - pwm_x->GLB_CTRL2 &= ~PWMV2_GLB_CTRL2_DAC_SW_MODE_SET((1 << dac_index)); -} - -/** - * @brief Enable debug mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_enable_debug_mode(PWMV2_Type *pwm_x) -{ - pwm_x->GLB_CTRL2 |= PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK; -} - - -/** - * @brief Disable debug mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_disable_debug_mode(PWMV2_Type *pwm_x) -{ - pwm_x->GLB_CTRL2 &= ~PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK; -} - -/** - * @brief Clear fault event - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - */ -static inline void pwmv2_clear_fault_event(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - pwm_x->GLB_CTRL2 = (pwm_x->GLB_CTRL2 & ~(PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK)) | PWMV2_GLB_CTRL2_FAULT_CLEAR_SET((1 << chn)); -} - -/** - * @brief Using the Shadow Register Function - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_enable_shadow_lock_feature(PWMV2_Type *pwm_x) -{ - pwm_x->GLB_CTRL2 |= PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK; -} - -/** - * @brief Do not use the shadow register function - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_disable_shadow_lock_feature(PWMV2_Type *pwm_x) -{ - pwm_x->GLB_CTRL2 &= ~PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK; -} - -/** - * @brief Get counter work status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter_index @ref pwm_counter_t - * @return uint32_t status mask - */ -static inline uint32_t pwmv2_get_counter_working_status(PWMV2_Type *pwm_x, pwm_counter_t counter_index) -{ - return PWMV2_CNT_RELOAD_WORK_VALUE_GET(pwm_x->CNT_RELOAD_WORK[counter_index]); -} - -/** - * @brief Get cmp work status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - * @return uint32_t status mask - */ -static inline uint32_t pwmv2_get_cmp_working_status(PWMV2_Type *pwm_x, uint8_t cmp_index) -{ - return PWMV2_CMP_VAL_WORK_VALUE_GET(pwm_x->CMP_VAL_WORK[cmp_index]); -} - -/** - * @brief Get force mode work status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t status mask - */ -static inline uint32_t pwmv2_get_force_working_status(PWMV2_Type *pwm_x) -{ - return PWMV2_FORCE_WORK_FORCE_MODE_GET(pwm_x->FORCE_WORK); -} - -/** - * @brief Get the status of the output polarity - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t polarity - */ -static inline uint32_t pwmv2_get_force_work_out_polarity_status(PWMV2_Type *pwm_x) -{ - return PWMV2_FORCE_WORK_OUT_POLARITY_GET(pwm_x->FORCE_WORK); -} - -/** - * @brief Getting the value of a counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter_index @ref pwm_counter_t - * @return uint32_t counter value - */ -static inline uint32_t pwmv2_get_counter_value(PWMV2_Type *pwm_x, pwm_counter_t counter_index) -{ - return PWMV2_CNT_VAL_VALUE_GET(pwm_x->CNT_VAL[counter_index]); -} - -/** - * @brief set dac value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dac_index @ref pwm_dac_channel_t - * @param value dac value - */ -static inline void pwmv2_set_dac_value(PWMV2_Type *pwm_x, pwm_dac_channel_t dac_index, uint32_t value) -{ - pwm_x->DAC_VALUE_SV[dac_index] = PWMV2_DAC_VALUE_SV_VALUE_SET(value); -} - -/** - * @brief get capture posedge value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @return uint32_t posedge value - */ -static inline uint32_t pwmv2_get_capture_posedge_value(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - return PWMV2_CAPTURE_POS_CAPTURE_POS_GET(pwm_x->CAPTURE_POS[chn]); -} - -/** - * @brief Select the input source for the captured signal - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param select @ref pwm_capture_input_select_t - */ -static inline void pwmv2_capture_selection_input_source(PWMV2_Type *pwm_x, pwm_channel_t chn, pwm_capture_input_select_t select) -{ - pwm_x->CAPTURE_POS[chn] = (pwm_x->CAPTURE_POS[chn] & ~PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) | - PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET(select); -} - -/** - * @brief Set the counter to be used for the capture channel - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param counter_index counter index - */ -static inline void pwmv2_set_capture_counter_index(PWMV2_Type *pwm_x, pwm_channel_t chn, uint8_t counter_index) -{ - pwm_x->CAPTURE_POS[chn] = (pwm_x->CAPTURE_POS[chn] & ~PWMV2_CAPTURE_POS_CNT_INDEX_MASK) | - PWMV2_CAPTURE_POS_CNT_INDEX_SET(counter_index); -} - -/** - * @brief get capture negedge value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @return uint32_t posedge value - */ -static inline uint32_t pwmv2_get_capture_negedge_value(PWMV2_Type *pwm_x, pwm_channel_t chn) -{ - return PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET(pwm_x->CAPTURE_NEG[chn]); -} - -/** - * @brief Get all interrupt status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status mask - */ -static inline uint32_t pwmv2_get_irq_status_all(PWMV2_Type *pwm_x) -{ - return pwm_x->IRQ_STS; -} - -/** - * @brief clear calculate overflow irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_clear_calculate_overflow_irq_status(PWMV2_Type *pwm_x) -{ - pwm_x->IRQ_STS &= PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK; -} - -/** - * @brief enable calculate overflow irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_enable_calculate_overflow_irq(PWMV2_Type *pwm_x) -{ - pwm_x->IRQ_EN |= PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK; -} - -/** - * @brief Disable calculate overflow irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - */ -static inline void pwmv2_disable_calculate_overflow_irq(PWMV2_Type *pwm_x) -{ - pwm_x->IRQ_EN &= ~PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK; -} - -/** - * @brief Get cmp irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status - */ -static inline uint32_t pwmv2_get_cmp_irq_status(PWMV2_Type *pwm_x) -{ - return PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET(pwm_x->IRQ_STS_CMP); -} - -/** - * @brief Clear cmp irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask uint32_t irq status - */ -static inline void pwmv2_clear_cmp_irq_status(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQ_STS_CMP = PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET(mask); -} - -/** - * @brief Get reload irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t reload irq status - */ -static inline uint32_t pwmv2_get_reload_irq_status(PWMV2_Type *pwm_x) -{ - return PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET(pwm_x->IRQ_STS_RELOAD); -} - -/** - * @brief Clear reload irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask irq status mask - */ -static inline void pwmv2_clear_reload_irq_status(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQ_STS_RELOAD = PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET(mask); -} - -/** - * @brief Get capture posedge irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status - */ -static inline uint32_t pwmv2_get_capture_posedge_irq_status(PWMV2_Type *pwm_x) -{ - return PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET(pwm_x->IRQ_STS_CAP_POS); -} - -/** - * @brief Clear capture posedge irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask capture posedge irq mask - */ -static inline void pwmv2_clear_capture_posedge_irq_status(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQ_STS_CAP_POS = PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET(mask); -} - -/** - * @brief Get capture negedge irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status - */ -static inline uint32_t pwmv2_get_capture_negedge_irq_status(PWMV2_Type *pwm_x) -{ - return PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET(pwm_x->IRQ_STS_CAP_NEG); -} - -/** - * @brief Clear capture negedge irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask capture posedge irq mask - */ -static inline void pwmv2_clear_capture_negedge_irq_status(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQ_STS_CAP_NEG = PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET(mask); -} - -/** - * @brief Get fault irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status - */ -static inline uint32_t pwmv2_get_fault_irq_status(PWMV2_Type *pwm_x) -{ - return PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET(pwm_x->IRQ_STS_FAULT); -} - -/** - * @brief Clear fault irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status - */ -static inline void pwmv2_clear_fault_irq_status(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQ_STS_FAULT = PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET(mask); -} - -/** - * @brief Get burstend irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @return uint32_t irq status - */ -static inline uint32_t pwmv2_get_burstend_irq_status(PWMV2_Type *pwm_x) -{ - return PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET(pwm_x->IRQ_STS_BURSTEND); -} - -/** - * @brief Clear burstend irq status - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param mask mask status - */ -static inline void pwmv2_clear_burstend__irq_status(PWMV2_Type *pwm_x, uint32_t mask) -{ - pwm_x->IRQ_STS_BURSTEND = PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET(mask); -} - -/** - * @brief enable cmp irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - */ -static inline void pwmv2_enable_cmp_irq(PWMV2_Type *pwm_x, uint8_t cmp_index) -{ - pwm_x->IRQ_EN_CMP |= PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET(1 << cmp_index); -} - -/** - * @brief disable cmp irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - */ -static inline void pwmv2_disable_cmp_irq(PWMV2_Type *pwm_x, uint8_t cmp_index) -{ - pwm_x->IRQ_EN_CMP &= ~PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET(1 << cmp_index); -} - -/** - * @brief enable reload irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter_index @ref pwm_counter_t - */ -static inline void pwmv2_enable_reload_irq(PWMV2_Type *pwm_x, pwm_counter_t counter_index) -{ - pwm_x->IRQ_EN_RELOAD |= PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET(1 << counter_index); -} - -/** - * @brief disable reload irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter_index @ref pwm_counter_t - */ -static inline void pwmv2_disable_reload_irq(PWMV2_Type *pwm_x, pwm_counter_t counter_index) -{ - pwm_x->IRQ_EN_RELOAD &= ~PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET(1 << counter_index); -} - -/** - * @brief enable capture posedge irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param channel_index @ref pwm_counter_t - */ -static inline void pwmv2_enable_capture_posedge_irq(PWMV2_Type *pwm_x, pwm_channel_t channel_index) -{ - pwm_x->IRQ_EN_CAP_POS |= PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET(1 << channel_index); -} - -/** - * @brief disable capture posedge irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param channel_index @ref pwm_counter_t - */ -static inline void pwmv2_disable_capture_posedge_irq(PWMV2_Type *pwm_x, pwm_channel_t channel_index) -{ - pwm_x->IRQ_EN_CAP_POS &= ~PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET(1 << channel_index); -} - -/** - * @brief enable capture nedege irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param channel_index @ref pwm_channel_t - */ -static inline void pwmv2_enable_capture_nededge_irq(PWMV2_Type *pwm_x, pwm_channel_t channel_index) -{ - pwm_x->IRQ_EN_CAP_NEG |= PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET(1 << channel_index); -} - -/** - * @brief disable capture nedege irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param channel_index @ref pwm_channel_t - */ -static inline void pwmv2_disable_capture_nededge_irq(PWMV2_Type *pwm_x, pwm_channel_t channel_index) -{ - pwm_x->IRQ_EN_CAP_NEG &= ~PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET(1 << channel_index); -} - -/** - * @brief enable fault irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param channel_index @ref pwm_channel_t - */ -static inline void pwmv2_enable_fault_irq(PWMV2_Type *pwm_x, pwm_channel_t channel_index) -{ - pwm_x->IRQ_EN_FAULT |= PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(1 << channel_index); -} - -/** - * @brief disable fault irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param channel_index @ref pwm_channel_t - */ -static inline void pwmv2_disable_fault_irq(PWMV2_Type *pwm_x, pwm_channel_t channel_index) -{ - pwm_x->IRQ_EN_FAULT &= ~PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(1 << channel_index); -} - -/** - * @brief enable burstend irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter_index @ref pwm_counter_t - */ -static inline void pwmv2_enable_burstend_irq(PWMV2_Type *pwm_x, pwm_counter_t counter_index) -{ - pwm_x->IRQ_EN_BURSTEND |= PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(1 << counter_index); -} - -/** - * @brief disable burstend irq - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter_index @ref pwm_counter_t - */ -static inline void pwmv2_disable_burstend_irq(PWMV2_Type *pwm_x, pwm_counter_t counter_index) -{ - pwm_x->IRQ_EN_BURSTEND &= ~PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(1 << counter_index); -} - -/** - * @brief enable dma at compare point - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dma_channel @ref pwm_dma_chn_t - * @param cmp_index cmp index - */ -static inline void pwmv2_enable_dma_at_compare_point(PWMV2_Type *pwm_x, pwm_dma_chn_t dma_channel, uint8_t cmp_index) -{ - pwm_x->DMA_EN = (pwm_x->DMA_EN & ~((PWMV2_DMA_EN_DMA0_SEL_MASK | PWMV2_DMA_EN_DMA0_EN_MASK) << (PWMV2_DMA_EN_DMA1_SEL_SHIFT * dma_channel))) | - ((PWMV2_DMA_EN_DMA0_SEL_SET(cmp_index) | PWMV2_DMA_EN_DMA0_EN_MASK) << (PWMV2_DMA_EN_DMA1_SEL_SHIFT * dma_channel)); -} - -/** - * @brief disable dma at compare point - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dma_channel @ref pwm_dma_chn_t - */ -static inline void pwmv2_disable_dma_at_compare_point(PWMV2_Type *pwm_x, pwm_dma_chn_t dma_channel) -{ - pwm_x->DMA_EN &= ~((PWMV2_DMA_EN_DMA0_SEL_MASK | PWMV2_DMA_EN_DMA0_EN_MASK) << (PWMV2_DMA_EN_DMA1_SEL_SHIFT * dma_channel)); -} - -/** - * @brief enable dma at reload point - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dma_channel @ref pwm_dma_chn_t - * @param reload_index @ref pwm_counter_t - */ -static inline void pwmv2_enable_dma_at_reload_point(PWMV2_Type *pwm_x, pwm_dma_chn_t dma_channel, pwm_counter_t reload_index) -{ - pwm_x->DMA_EN = (pwm_x->DMA_EN & ~((PWMV2_DMA_EN_DMA0_SEL_MASK | PWMV2_DMA_EN_DMA0_EN_MASK) << (PWMV2_DMA_EN_DMA1_SEL_SHIFT * dma_channel))) | - ((PWMV2_DMA_EN_DMA0_SEL_SET(reload_index + 24) | PWMV2_DMA_EN_DMA0_EN_MASK) << (PWMV2_DMA_EN_DMA1_SEL_SHIFT * dma_channel)); -} - -/** - * @brief disable dma at reload point - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param dma_channel @ref pwm_dma_chn_t - */ -static inline void pwmv2_disable_dma_at_reload_point(PWMV2_Type *pwm_x, pwm_dma_chn_t dma_channel) -{ - pwm_x->DMA_EN &= ~((PWMV2_DMA_EN_DMA0_SEL_MASK | PWMV2_DMA_EN_DMA0_EN_MASK) << (PWMV2_DMA_EN_DMA1_SEL_SHIFT * dma_channel)); -} - -/** - * @brief select compare point 0 index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param cmp_index cmp index - */ -static inline void pwmv2_reload_select_compare_point0_index(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t cmp_index) -{ - pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK)) | PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET(cmp_index); -} - -/** - * @brief select compare point 1 index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param cmp_index cmp index - */ -static inline void pwmv2_reload_select_compare_point1_index(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t cmp_index) -{ - pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK)) | PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET(cmp_index); -} - -/** - * @brief Select the input trigger source for the reload point - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param trig_index trig index - */ -static inline void pwmv2_reload_select_input_trigger(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t trig_index) -{ - pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK)) | PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET(trig_index); -} - -/** - * @brief Set reload update time - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param update @ref pwm_reload_update_time_t - */ -static inline void pwmv2_set_reload_update_time(PWMV2_Type *pwm_x, pwm_counter_t counter, pwm_reload_update_time_t update) -{ - pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~(PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK)) | PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET(update); -} - -/** - * @brief Set dac data parameter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param dac_parameter dac parameter - */ -static inline void pwmv2_counter_set_dac_data_parameter(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t dac_parameter) -{ - pwm_x->CNT[counter].CFG0 = (pwm_x->CNT[counter].CFG0 & ~PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) | PWMV2_CNT_CFG0_CNT_D_PARAM_SET(dac_parameter); -} - -/** - * @brief Select dac index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param dac_index @ref pwm_dac_channel_t - */ -static inline void pwmv2_conuter_select_dac_index(PWMV2_Type *pwm_x, pwm_counter_t counter, pwm_dac_channel_t dac_index) -{ - pwm_x->CNT[counter].CFG1 = (pwm_x->CNT[counter].CFG1 & ~PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) | PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET(dac_index); -} - -/** - * @brief Enable the upper limit of the calculation unit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_up_limit_enable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG1 |= PWMV2_CNT_CFG1_CNT_LU_EN_MASK; -} - -/** - * @brief Disable the upper limit of the calculation unit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_up_limit_disable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG1 &= ~PWMV2_CNT_CFG1_CNT_LU_EN_MASK; -} - -/** - * @brief Select the upper limit from the shadow register - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param index shadow index - */ -static inline void pwmv2_counter_select_up_limit_from_shadow_value(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t index) -{ - pwm_x->CNT[counter].CFG1 = (pwm_x->CNT[counter].CFG1 & ~PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) | PWMV2_CNT_CFG1_CNT_LIM_UP_SET(index); -} - -/** - * @brief Enable the lower limit of the calculation unit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_low_limit_enable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG1 |= PWMV2_CNT_CFG1_CNT_LL_EN_MASK; -} - - -/** - * @brief Disable the lower limit of the calculation unit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_low_limit_disable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG1 &= ~PWMV2_CNT_CFG1_CNT_LL_EN_MASK; -} - -/** - * @brief Select the lower limit from the shadow register - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param index shadow index - */ -static inline void pwmv2_counter_select_low_limit_from_shadow_value(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t index) -{ - pwm_x->CNT[counter].CFG1 = (pwm_x->CNT[counter].CFG1 & ~PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) | PWMV2_CNT_CFG1_CNT_LIM_LO_SET(index); -} - -/** - * @brief Select data offset from shadow register - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param index shadow index - */ -static inline void pwmv2_counter_select_data_offset_from_shadow_value(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t index) -{ - pwm_x->CNT[counter].CFG1 = (pwm_x->CNT[counter].CFG1 & ~PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) | PWMV2_CNT_CFG1_CNT_IN_OFF_SET(index); -} - -/** - * @brief enable counter reload by trigmux - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_enable_reload_by_trig(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG2 |= PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK; -} - -/** - * @brief disable counter reload by trigmux - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_disable_reload_by_trig(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG2 &= ~PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK; -} - -/** - * @brief Select counter update by trigmux1 - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param trig_index trigmux index - */ -static inline void pwmv2_counter_update_trig1(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t trig_index) -{ - pwm_x->CNT[counter].CFG2 = (pwm_x->CNT[counter].CFG2 & ~PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) | PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET(trig_index); -} - -/** - * @brief Enable counter update by trigmux1 - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_enable_update_trig1(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG2 |= PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK; -} - -/** - * @brief Disable counter update by trigmux1 - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_disable_update_trig1(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG2 &= ~PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK; -} - -/** - * @brief Enable change counter value to one of the calculation cell output when cnt_update_triger1 issued - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param cal_index cal index - */ -static inline void pwmv2_counter_set_trig1_calculate_cell_index(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t cal_index) -{ - pwm_x->CNT[counter].CFG2 = (pwm_x->CNT[counter].CFG2 & ~PWMV2_CNT_CFG2_CNT_TRIG1_MASK) | PWMV2_CNT_CFG2_CNT_TRIG1_SET(cal_index); -} - -/** - * @brief Select counter update by trigmux0 - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param trig_index trigmux index - */ -static inline void pwmv2_counter_update_trig0(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t trig_index) -{ - pwm_x->CNT[counter].CFG2 = (pwm_x->CNT[counter].CFG2 & ~PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) | PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET(trig_index); -} - -/** - * @brief Enable counter update by trigmux0 - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_enable_update_trig0(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG2 |= PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK; -} - -/** - * @brief Disable counter update by trigmux0 - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_disable_update_trig0(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG2 &= ~PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK; -} - -/** - * @brief Enable change counter value to one of the calculation cell output when cnt_update_triger0 issued - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param cal_index cal index - */ -static inline void pwmv2_counter_set_trig0_calculate_cell_index(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t cal_index) -{ - pwm_x->CNT[counter].CFG2 = (pwm_x->CNT[counter].CFG2 & ~PWMV2_CNT_CFG2_CNT_TRIG0_MASK) | PWMV2_CNT_CFG2_CNT_TRIG0_SET(cal_index); -} - -/** - * @brief Set trigmux index to start counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param trig_index trig index - */ -static inline void pwmv2_counter_start_select_trigger_index(PWMV2_Type *pwm_x, pwm_counter_t counter, uint8_t trig_index) -{ - pwm_x->CNT[counter].CFG3 = (pwm_x->CNT[counter].CFG3 & ~PWMV2_CNT_CFG3_CNT_START_SEL_MASK) | PWMV2_CNT_CFG3_CNT_START_SEL_SET(trig_index); -} - -/** - * @brief Enable trigmux to trigger counter initiation - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_start_trigger_enable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG3 |= PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK; -} - -/** - * @brief Disable trigmux to trigger counter initiation - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_start_trigger_disable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG3 &= ~PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK; -} - -/** - * @brief Set counter burst value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - * @param burst burst value - */ -static inline void pwmv2_set_counter_burst(PWMV2_Type *pwm_x, pwm_counter_t counter, uint16_t burst) -{ - pwm_x->CNT[counter].CFG3 |= PWMV2_CNT_CFG3_CNT_BURST_SET(burst); -} - -/** - * @brief Disable counter burst function - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_counter_burst_disable(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT[counter].CFG3 |= PWMV2_CNT_CFG3_CNT_BURST_MASK; -} - -/** - * @brief start pwm output - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_start_pwm_output(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT_GLBCFG |= PWMV2_CNT_GLBCFG_CNT_SW_START_SET((1 << counter)); -} - -/** - * @brief Reset pwm counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_reset_counter(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT_GLBCFG |= PWMV2_CNT_GLBCFG_TIMER_RESET_SET((1 << counter)); -} - -/** - * @brief Enable pwm counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_enable_counter(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT_GLBCFG |= PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET((1 << counter)); -} - -/** - * @brief Disable pwm counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param counter @ref pwm_counter_t - */ -static inline void pwmv2_disable_counter(PWMV2_Type *pwm_x, pwm_counter_t counter) -{ - pwm_x->CNT_GLBCFG &= ~PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET((1 << counter)); -} - -/** - * @brief Set calculate up limit parameter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param value parameter - */ -static inline void pwmv2_calculate_set_up_limit_parameter(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t value) -{ - pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) | PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(value); -} - -/** - * @brief Set calculate low limit parameter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param value parameter - */ -static inline void pwmv2_calculate_set_low_limit_parameter(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t value) -{ - pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) | PWMV2_CAL_CFG0_CAL_LL_PARAM_SET(value); -} - -/** - * @brief Set calculate period parameter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param value parameter - */ -static inline void pwmv2_calculate_set_period_parameter(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t value) -{ - pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) | PWMV2_CAL_CFG0_CAL_T_PARAM_SET(value); -} - -/** - * @brief Set calculate dac value parameter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param value parameter - */ -static inline void pwmv2_calculate_set_dac_value_parameter(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t value) -{ - pwm_x->CAL[cal_index].CFG0 = (pwm_x->CAL[cal_index].CFG0 & ~PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) | PWMV2_CAL_CFG0_CAL_D_PARAM_SET(value); -} - -/** - * @brief Select calculate index to counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param counter_calculate counter index - */ -static inline void pwmv2_calculate_select_counter_calculate_index(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t counter_calculate) -{ - pwm_x->CAL[cal_index].CFG1 = (pwm_x->CAL[cal_index].CFG1 & ~PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) | PWMV2_CAL_CFG1_CAL_T_INDEX_SET(counter_calculate); -} - -/** - * @brief Select calculate input value - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param index shadow index - */ -static inline void pwmv2_calculate_select_in_value(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t index) -{ - pwm_x->CAL[cal_index].CFG1 = (pwm_x->CAL[cal_index].CFG1 & ~PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) | PWMV2_CAL_CFG1_CAL_IN_INDEX_SET(index); -} - -/** - * @brief enable calculate up limit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - */ -static inline void pwmv2_calculate_enable_up_limit(PWMV2_Type *pwm_x, uint8_t cal_index) -{ - pwm_x->CAL[cal_index].CFG1 |= PWMV2_CAL_CFG1_CAL_LU_EN_MASK; -} - -/** - * @brief disable calculate up limit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - */ -static inline void pwmv2_calculate_disable_up_limit(PWMV2_Type *pwm_x, uint8_t cal_index) -{ - pwm_x->CAL[cal_index].CFG1 &= ~PWMV2_CAL_CFG1_CAL_LU_EN_MASK; -} - -/** - * @brief Select up limit offset from shadow index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param shadow_index shadow index - */ -static inline void pwmv2_calculate_select_up_limit_offset(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t shadow_index) -{ - pwm_x->CAL[cal_index].CFG1 = (pwm_x->CAL[cal_index].CFG1 & ~PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) | PWMV2_CAL_CFG1_CAL_LIM_UP_SET(shadow_index); -} - -/** - * @brief Select low limit offset from shadow index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param shadow_index shadow index - */ -static inline void pwmv2_calculate_select_low_limit_offset(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t shadow_index) -{ - pwm_x->CAL[cal_index].CFG1 = (pwm_x->CAL[cal_index].CFG1 & ~PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) | PWMV2_CAL_CFG1_CAL_LIM_LO_SET(shadow_index); -} - -/** - * @brief Select offset from shadow index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param shadow_index shadow index - */ -static inline void pwmv2_calculate_select_in_offset(PWMV2_Type *pwm_x, uint8_t cal_index, uint8_t shadow_index) -{ - pwm_x->CAL[cal_index].CFG1 = (pwm_x->CAL[cal_index].CFG1 & ~PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) | PWMV2_CAL_CFG1_CAL_IN_OFF_SET(shadow_index); -} - -/** - * @brief enable low limit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - */ -static inline void pwmv2_calculate_enable_low_limit(PWMV2_Type *pwm_x, uint8_t cal_index) -{ - pwm_x->CAL[cal_index].CFG1 |= PWMV2_CAL_CFG1_CAL_LL_EN_MASK; -} - -/** - * @brief disable low limit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - */ -static inline void pwmv2_calculate_disable_low_limit(PWMV2_Type *pwm_x, uint8_t cal_index) -{ - pwm_x->CAL[cal_index].CFG1 &= ~PWMV2_CAL_CFG1_CAL_LL_EN_MASK; -} - -/** - * @brief Select cmp trigmux index - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - * @param trig_index trigmux index - */ -static inline void pwmv2_select_cmp_trigmux(PWMV2_Type *pwm_x, uint8_t cmp_index, uint8_t trig_index) -{ - pwm_x->CMP[cmp_index].CFG = (pwm_x->CMP[cmp_index].CFG & ~PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) | PWMV2_CMP_CFG_CMP_TRIG_SEL_SET(trig_index); -} - -/** - * @brief Select cmp update trigmux time - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - * @param trig_time @ref pwm_cmp_shadow_register_update_trigger_t - */ -static inline void pwmv2_cmp_update_trig_time(PWMV2_Type *pwm_x, uint8_t cmp_index, pwm_cmp_shadow_register_update_trigger_t trig_time) -{ - pwm_x->CMP[cmp_index].CFG = (pwm_x->CMP[cmp_index].CFG & ~PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) | PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET(trig_time); -} - -/** - * @brief Select cmp source - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - * @param cmp_sel @ref pwm_cmp_source_t - * @param index source index - */ -static inline void pwmv2_select_cmp_source(PWMV2_Type *pwm_x, uint8_t cmp_index, pwm_cmp_source_t cmp_sel, uint8_t index) -{ - pwm_x->CMP[cmp_index].CFG = (pwm_x->CMP[cmp_index].CFG & ~PWMV2_CMP_CFG_CMP_IN_SEL_MASK) | PWMV2_CMP_CFG_CMP_IN_SEL_SET((cmp_sel + index)); -} - -/** - * @brief Select cmp use counter - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cmp_index cmp index - * @param counter_index @ref pwm_counter_t - */ -static inline void pwmv2_cmp_select_counter(PWMV2_Type *pwm_x, uint8_t cmp_index, pwm_counter_t counter_index) -{ - if (cmp_index >= 16) { - pwm_x->CMP[cmp_index].CFG = (pwm_x->CMP[cmp_index].CFG & ~PWMV2_CMP_CFG_CMP_CNT_MASK) | PWMV2_CMP_CFG_CMP_CNT_SET((counter_index)); - } -} - -/** - * @brief config pwm cmp - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param index cmp index - * @param config @ref pwmv2_cmp_config_t - */ -void pwmv2_config_cmp(PWMV2_Type *pwm_x, uint8_t index, pwmv2_cmp_config_t *config); - -/** - * @brief config async fault source - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param index cmp index - * @param config @ref pwmv2_async_fault_source_config_t - */ -void pwmv2_config_async_fault_source(PWMV2_Type *pwm_x, pwm_channel_t index, pwmv2_async_fault_source_config_t *config); - -/** - * @brief config pwm - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param index @ref pwm_channel_t - * @param config @ref pwmv2_config_t - * @param enable_pair_mode bool - */ -void pwmv2_config_pwm(PWMV2_Type *pwm_x, pwm_channel_t index, pwmv2_config_t *config, bool enable_pair_mode); - -/** - * @brief Set pwm waveform - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param pwm_config @ref pwmv2_config_t - * @param cmp_start_index cmp start index - * @param cmp @ref pwmv2_cmp_config_t - * @param cmp_num cmp number - * @return hpm_stat_t @ref hpm_stat_t - */ -hpm_stat_t pwmv2_setup_waveform(PWMV2_Type *pwm_x, - pwm_channel_t chn, pwmv2_config_t *pwm_config, - uint8_t cmp_start_index, pwmv2_cmp_config_t *cmp, uint8_t cmp_num); - -/** - * @brief set the pwm waveform complementary mode - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param chn @ref pwm_channel_t - * @param pwm_pair_config @ref pwmv2_pair_config_t - * @param cmp_start_index cmp start index - * @param cmp @ref pwmv2_cmp_config_t - * @param cmp_num cmp number - * @return hpm_stat_t @ref hpm_stat_t - */ -hpm_stat_t pwmv2_setup_waveform_in_pair(PWMV2_Type *pwm_x, pwm_channel_t chn, - pwmv2_pair_config_t *pwm_pair_config, uint8_t cmp_start_index, - pwmv2_cmp_config_t *cmp, uint8_t cmp_num); - -/** - * @brief Configure the cmp calculate unit - * - * @param pwm_x PWM base address, HPM_PWMx(x=0..n) - * @param cal_index calculate index - * @param cal @ref pwmv2_cmp_calculate_cfg_t - */ -void pwmv2_setup_cmp_calculate(PWMV2_Type *pwm_x, uint8_t cal_index, pwmv2_cmp_calculate_cfg_t *cal); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_PWMV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h deleted file mode 100644 index 0388eb74e54..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qei_drv.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_QEI_DRV_H -#define HPM_QEI_DRV_H - -#include "hpm_common.h" -#include "hpm_qei_regs.h" -/** - * @brief QEI driver APIs - * @defgroup qei_interface QEI driver APIs - * @ingroup io_interfaces - * @{ - * - */ -#define QEI_EVENT_WDOG_FLAG_MASK (1U << 31) /**< watchdog flag */ -#define QEI_EVENT_HOME_FLAG_MASK (1U << 30) /**< home flag */ -#define QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK (1U << 29) /**< postion compare match flag */ -#define QEI_EVENT_Z_PHASE_FLAG_MASK (1U << 28) /**< z input flag */ - -/** - * @brief counting mode of Z-phase counter - * - */ -typedef enum qei_z_count_inc_mode { - qei_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */ - qei_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */ -} qei_z_count_inc_mode_t; - -/** - * @brief motor rotation direction - * - */ -typedef enum qei_rotation_dir_cmp { - qei_rotation_dir_cmp_positive = 0, /**< position compare need positive rotation */ - qei_rotation_dir_cmp_negative = 1, /**< position compare need negative rotation */ - qei_rotation_dir_cmp_ignore = 2, /**< ignore */ -} qei_rotation_dir_cmp_t; - -/** - * @brief counter type - * - */ -typedef enum qei_counter_type { - qei_counter_type_z = 0, /**< Z counter */ - qei_counter_type_phase = 1, /**< Phase counter */ - qei_counter_type_speed = 2, /**< Speed counter */ - qei_counter_type_timer = 3, /**< Timer counter */ -} qei_counter_type_t; - -/** - * @brief qei work mode - * - */ -typedef enum qei_work_mode { - qei_work_mode_abz = 0, /**< Orthogonal decoder mode */ - qei_work_mode_pd = 1, /**< Directional (PD) mode */ - qei_work_mode_ud = 2, /**< Up and Down (UD) mode */ -} qei_work_mode_t; - -/** - * @brief speed history type - * - */ -typedef enum qei_speed_his_type { - qei_speed_his0 = QEI_SPDHIS_SPDHIS0, /**< Speed history0 */ - qei_speed_his1 = QEI_SPDHIS_SPDHIS1, /**< Speed history1 */ - qei_speed_his2 = QEI_SPDHIS_SPDHIS2, /**< Speed history2 */ - qei_speed_his3 = QEI_SPDHIS_SPDHIS3, /**< Speed history3 */ -} qei_speed_his_type_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable qei watchdog - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_wdog_enable(QEI_Type *qei_x) -{ - qei_x->WDGCFG |= QEI_WDGCFG_WDGEN_MASK; -} - -/** - * @brief disable qei watchdog - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_wdog_disable(QEI_Type *qei_x) -{ - qei_x->WDGCFG &= ~QEI_WDGCFG_WDGEN_MASK; -} - -/** - * @brief config watchdog - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] timeout watchdog timeout time - * @param[in] enable - * @arg 1 - enable watchdog, You can use the @ref qei_wdog_disable open watchdog - * @arg 0 - disable watchdog, You can use the @ref qei_wdog_enable open watchdog - */ -static inline void qei_wdog_config(QEI_Type *qei_x, uint32_t timeout, bool enable) -{ - qei_x->WDGCFG = QEI_WDGCFG_WDGTO_SET(timeout) | QEI_WDGCFG_WDGEN_SET(enable); -} - -/** - * @brief - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] phase_count maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - * @param[in] mode - * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * @arg 0 zcnt will increment or decrement when Z input assert - * @param[in] z_calibrate 1- phcnt will set to phidx when Z input assert - */ -static inline void qei_phase_config(QEI_Type *qei_x, uint32_t phase_count, - qei_z_count_inc_mode_t mode, bool z_calibrate) -{ - qei_x->PHCFG = QEI_PHCFG_ZCNTCFG_SET(mode) | QEI_PHCFG_PHCALIZ_SET(z_calibrate) - | QEI_PHCFG_PHMAX_SET(phase_count - 1); -} - -/** - * @brief set phase index - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] phase_index phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - */ -static inline void qei_phase_set_index(QEI_Type *qei_x, uint32_t phase_index) -{ - qei_x->PHIDX = QEI_PHIDX_PHIDX_SET(phase_index); -} - -/** - * @brief enable trigger event - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] event_mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_output_trigger_event_enable(QEI_Type *qei_x, uint32_t event_mask) -{ - qei_x->TRGOEN |= event_mask; -} - -/** - * @brief disable trigger event - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] event_mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_output_trigger_event_disable(QEI_Type *qei_x, uint32_t event_mask) -{ - qei_x->TRGOEN &= ~event_mask; -} - -/** - * @brief enable load read trigger event - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] event_mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_load_read_trigger_event_enable(QEI_Type *qei_x, uint32_t event_mask) -{ - qei_x->READEN |= event_mask; -} - -/** - * @brief disable load read trigger event - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] event_mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_load_read_trigger_event_disable(QEI_Type *qei_x, uint32_t event_mask) -{ - qei_x->READEN &= ~event_mask; -} - -/** - * @brief set zcnt postion compare value - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] cmp zcnt postion compare value - */ -static inline void qei_z_cmp_set(QEI_Type *qei_x, uint32_t cmp) -{ - qei_x->ZCMP = QEI_ZCMP_ZCMP_SET(cmp); -} - -/** - * @brief set spdcnt position compare value - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] cmp spdcnt position compare value - */ -static inline void qei_speed_cmp_set(QEI_Type *qei_x, uint32_t cmp) -{ - qei_x->SPDCMP = QEI_SPDCMP_SPDCMP_SET(cmp); -} - -/** - * @brief set Phase comparator value - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] cmp phcnt position compare value - * @param[in] cmp_z 1- postion compare not include zcnt - * @param[in] rotation_dir @ref qei_rotation_dir_cmp_t - */ -static inline void qei_phase_cmp_set(QEI_Type *qei_x, uint32_t cmp, - bool cmp_z, qei_rotation_dir_cmp_t rotation_dir) -{ - qei_x->PHCMP = QEI_PHCMP_PHCMP_SET(cmp) - | QEI_PHCMP_ZCMPDIS_SET(!cmp_z) - | ((rotation_dir == qei_rotation_dir_cmp_ignore) - ? QEI_PHCMP_DIRCMPDIS_MASK : (QEI_PHCMP_DIRCMP_SET(rotation_dir))); -} - -/** - * @brief clear qei status register - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_clear_status(QEI_Type *qei_x, uint32_t mask) -{ - qei_x->SR = mask; -} - -/** - * @brief get qei status - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @retval qei status: - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline uint32_t qei_get_status(QEI_Type *qei_x) -{ - return qei_x->SR; -} - -/** - * @brief get qei bit status - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - * @retval true or false - */ -static inline bool qei_get_bit_status(QEI_Type *qei_x, uint32_t mask) -{ - if ((qei_x->SR & mask) == mask) { - return true; - } else { - return false; - } -} - -/** - * @brief enable qei irq - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_irq_enable(QEI_Type *qei_x, uint32_t mask) -{ - qei_x->IRQEN |= mask; -} - -/** - * @brief disable qei irq - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_irq_disable(QEI_Type *qei_x, uint32_t mask) -{ - qei_x->IRQEN &= ~mask; -} - -/** - * @brief enable dma request - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_dma_request_enable(QEI_Type *qei_x, uint32_t mask) -{ - qei_x->DMAEN |= mask; -} - -/** - * @brief disable qei dma - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mask - * @arg @ref QEI_EVENT_WDOG_FLAG_MASK - * @arg @ref QEI_EVENT_HOME_FLAG_MASK - * @arg @ref QEI_EVENT_POSITIVE_COMPARE_FLAG_MASK - * @arg @ref QEI_EVENT_Z_PHASE_FLAG_MASK - */ -static inline void qei_dma_request_disable(QEI_Type *qei_x, uint32_t mask) -{ - qei_x->DMAEN &= ~mask; -} - -/** - * @brief get current counter value - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] type @ref qei_counter_type_t - * @retval counter value - */ -static inline uint32_t qei_get_current_count(QEI_Type *qei_x, - qei_counter_type_t type) -{ - return *(&qei_x->COUNT[QEI_COUNT_CURRENT].Z + type); -} - -/** - * @brief get current phcnt value - * - * @param qei_x QEI base address, HPM_QEIx(x=0...n) - * @return phcnt value - */ -static inline uint32_t qei_get_current_phase_phcnt(QEI_Type *qei_x) -{ - return QEI_COUNT_PH_PHCNT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); -} - -/** - * @brief get current a phase status - * - * @param qei_x QEI base address, HPM_QEIx(x=0...n) - * @return a phase level - */ -static inline bool qei_get_current_phase_astat(QEI_Type *qei_x) -{ - return QEI_COUNT_PH_ASTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); -} - -/** - * @brief get current b phase status - * - * @param qei_x QEI base address, HPM_QEIx(x=0...n) - * @return b phase level - */ -static inline bool qei_get_current_phase_bstat(QEI_Type *qei_x) -{ - return QEI_COUNT_PH_BSTAT_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); -} - -/** - * @brief get current phase dir - * - * @param qei_x QEI base address, HPM_QEIx(x=0...n) - * @return dir - */ -static inline bool qei_get_current_phase_dir(QEI_Type *qei_x) -{ - return QEI_COUNT_PH_DIR_GET(qei_get_current_count(qei_x, qei_counter_type_phase)); -} - -/** - * @brief get read event count value - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] type @ref qei_counter_type_t - * @retval counter value - */ -static inline uint32_t qei_get_count_on_read_event(QEI_Type *qei_x, - qei_counter_type_t type) -{ - return *(&(qei_x->COUNT[QEI_COUNT_READ].Z) + type); -} - -/** - * @brief read the value of each phase snapshot 0 counter - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] type @ref qei_counter_type_t - * @retval counter value - */ -static inline uint32_t qei_get_count_on_snap0_event(QEI_Type *qei_x, - qei_counter_type_t type) -{ - return *(&qei_x->COUNT[QEI_COUNT_SNAP0].Z + type); -} - -/** - * @brief read the value of each phase snapshot 1 counter - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] type @ref qei_counter_type_t - * @retval counter value - */ -static inline uint32_t qei_get_count_on_snap1_event(QEI_Type *qei_x, - qei_counter_type_t type) -{ - return *(&qei_x->COUNT[QEI_COUNT_SNAP1].Z + type); -} - -/** - * @brief get speed history - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] hist_index @ref qei_speed_his_type_t - * @retval speed history value - * @arg counter value - */ -static inline uint32_t qei_get_speed_history(QEI_Type *qei_x, qei_speed_his_type_t hist_index) -{ - return QEI_SPDHIS_SPDHIS0_GET(qei_x->SPDHIS[hist_index]); -} - -/** - * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_load_counter_to_read_registers(QEI_Type *qei_x) -{ - qei_x->CR |= QEI_CR_READ_MASK; -} - -/** - * @brief reset spdcnt/phcnt/zcnt - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] counter_mask - * @arg 1 reset zcnt when H assert - * @arg (1<<1) reset phcnt when H assert - * @arg (1<<2) reset spdcnt when H assert - */ -static inline void qei_reset_counter_on_h_assert(QEI_Type *qei_x, - uint32_t counter_mask) -{ - qei_x->CR |= counter_mask << 16; -} - -/** - * @brief pause spdcnt when PAUSE assert - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] counter_mask - * @arg 1 pause spdcnt when PAUSE assert - * @arg (1<<1) pause spdcnt when PAUSE assert - * @arg (1<<2) pause spdcnt when PAUSE assert - */ -static inline void qei_pause_counter_on_pause(QEI_Type *qei_x, - uint32_t counter_mask) -{ - qei_x->CR |= counter_mask << 12; -} - -/** - * @brief load phcnt, zcnt, spdcnt and tmrcnt into their snap registers - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_snap_enable(QEI_Type *qei_x) -{ - qei_x->CR |= QEI_CR_SNAPEN_MASK; -} - -/** - * @brief disable snap - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_snap_disable(QEI_Type *qei_x) -{ - qei_x->CR &= ~QEI_CR_SNAPEN_MASK; -} - -/** - * @brief reset zcnt, spdcnt and tmrcnt to 0 - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_counter_reset_assert(QEI_Type *qei_x) -{ - qei_x->CR |= QEI_CR_RSTCNT_MASK; -} - -/** - * @brief qei counter reset release - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - */ -static inline void qei_counter_reset_release(QEI_Type *qei_x) -{ - qei_x->CR &= ~QEI_CR_RSTCNT_MASK; -} - -/** - * @brief set work mode - * - * @param[in] qei_x QEI base address, HPM_QEIx(x=0...n) - * @param[in] mode @ref qei_work_mode_t - */ -static inline void qei_set_work_mode(QEI_Type *qei_x, qei_work_mode_t mode) -{ - qei_x->CR = (qei_x->CR & ~QEI_CR_ENCTYP_MASK) | QEI_CR_ENCTYP_SET(mode); -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_QEI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h deleted file mode 100644 index a4348fae9c5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h +++ /dev/null @@ -1,1598 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_QEIV2_DRV_H -#define HPM_QEIV2_DRV_H - -#include "hpm_common.h" -#include "hpm_soc_ip_feature.h" -#include "hpm_qeiv2_regs.h" -/** - * @brief QEIV2 driver APIs - * @defgroup qeiv2_interface QEIV2 driver APIs - * @ingroup io_interfaces - * @{ - */ -#define QEIV2_EVENT_WDOG_FLAG_MASK (1U << 31U) /**< watchdog flag */ -#define QEIV2_EVENT_HOME_FLAG_MASK (1U << 30U) /**< home flag */ -#define QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK (1U << 29U) /**< postion compare match flag */ -#define QEIV2_EVENT_Z_PHASE_FLAG_MASK (1U << 28U) /**< z input flag */ -#define QEIV2_EVENT_Z_MISS_FLAG_MASK (1U << 27U) /**< z miss flag */ -#define QEIV2_EVENT_WIDTH_TIME_FLAG_MASK (1U << 26U) /**< width time flag */ -#define QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK (1U << 25U) /**< postion2 compare match flag */ -#define QEIV2_EVENT_DIR_CHG_FLAG_MASK (1U << 24U) /**< direction change flag */ -#define QEIV2_EVENT_CYCLE0_FLAG_MASK (1U << 23U) /**< cycle0 flag */ -#define QEIV2_EVENT_CYCLE1_FLAG_MASK (1U << 22U) /**< cycle1 flag */ -#define QEIV2_EVENT_PULSE0_FLAG_MASK (1U << 21U) /**< pulse0 flag */ -#define QEIV2_EVENT_PULSE1_FLAG_MASK (1U << 20U) /**< pulse1 flag */ -#define QEIV2_EVENT_HOME2_FLAG_MASK (1U << 19U) /**< home2 flag */ -#define QEIV2_EVENT_FAULT_FLAG_MASK (1U << 18U) /**< fault flag */ - -/** - * @brief qeiv2 work mode - * - */ -typedef enum qeiv2_work_mode { - qeiv2_work_mode_abz = 0, /**< Orthogonal decoder mode */ - qeiv2_work_mode_pd = 1, /**< Directional (PD) mode */ - qeiv2_work_mode_ud = 2, /**< Up and Down (UD) mode */ - qeiv2_work_mode_uvw = 3, /**< UVW mode */ - qeiv2_work_mode_single = 4, /**< Single-phase mode */ - qeiv2_work_mode_sin = 5, /**< Single sinewave mode */ - qeiv2_work_mode_sincos = 6, /**< Orthogonal sinewave mode */ -} qeiv2_work_mode_t; - -/** - * @brief spd and tmr read selection - * - */ -typedef enum qeiv2_spd_tmr_content { - qeiv2_spd_tmr_as_spd_tm = 0, /**< spd and timer register as spd and time */ - qeiv2_spd_tmr_as_pos_angle = 1, /**< spd and timer register as position and angle */ -} qeiv2_spd_tmr_content_t; - -/** - * @brief compare match rotate direction - * - */ -typedef enum qeiv2_rotate_dir { - qeiv2_rotate_dir_forward = 0, - qeiv2_rotate_dir_reverse = 1, -} qeiv2_rotate_dir_t; /**< compare match rotate direction */ - -/** - * @brief compare match position direction - * - */ -typedef enum qeiv2_position_dir { - qeiv2_pos_dir_decrease = 0, - qeiv2_pos_dir_increase = 1, -} qeiv2_position_dir_t; /**< compare match position direction */ - -/** - * @brief counting mode of Z-phase counter - * - */ -typedef enum qeiv2_z_count_work_mode { - qeiv2_z_count_inc_on_z_input_assert = 0, /**< zcnt will increment or decrement when Z input assert */ - qeiv2_z_count_inc_on_phase_count_max = 1, /**< zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 */ -} qeiv2_z_count_work_mode_t; - -/** - * @brief counter type - * - */ -typedef enum qeiv2_counter_type { - qeiv2_counter_type_z = 0, /**< Z counter */ - qeiv2_counter_type_phase = 1, /**< Phase counter */ - qeiv2_counter_type_speed = 2, /**< Speed counter */ - qeiv2_counter_type_timer = 3, /**< Timer counter */ -} qeiv2_counter_type_t; - -/** - * @brief filter mode - * - */ -typedef enum qeiv2_filter_mode { - qeiv2_filter_mode_bypass = 0, /**< bypass */ - qeiv2_filter_mode_burr = 4, /**< rapid change mode */ - qeiv2_filter_mode_delay, /**< delay filter mode */ - qeiv2_filter_mode_peak, /**< stable low mode */ - qeiv2_filter_mode_valley, /**< stable high mode */ -} qeiv2_filter_mode_t; - -/** - * @brief filter type - * - */ -typedef enum qeiv2_filter_phase { - qeiv2_filter_phase_a = 0, /**< filter phase a */ - qeiv2_filter_phase_b, /**< filter phase b */ - qeiv2_filter_phase_z, /**< filter phase z */ - qeiv2_filter_phase_h, /**< filter phase h */ - qeiv2_filter_phase_h2, /**< filter phase h2 */ - qeiv2_filter_phase_f, /**< filter phase f */ -} qeiv2_filter_phase_t; /**< qeiv2_filter_phase_t */ - -/** - * @brief uvw position option - * - */ -typedef enum qeiv2_uvw_pos_opt { - qeiv2_uvw_pos_opt_current = 0, /**< output exact point position, MMC use this */ - qeiv2_uvw_pos_opt_next, /**< output next area position, QEO use this */ -} qeiv2_uvw_pos_opt_t; - -typedef enum qeiv2_uvw_pos_sel { - qeiv2_uvw_pos_sel_low = 0, - qeiv2_uvw_pos_sel_high, - qeiv2_uvw_pos_sel_edge -} qeiv2_uvw_pos_sel_t; /**< qeiv2_uvw_pos_sel_t */ - -/** - * @brief qeiv2 uvw position selection - * - */ -#define QEIV2_UVW_POS_OPT_CUR_SEL_LOW 0u -#define QEIV2_UVW_POS_OPT_CUR_SEL_HIGH 1u -#define QEIV2_UVW_POS_OPT_CUR_SEL_EDGE 2u -#define QEIV2_UVW_POS_OPT_NEX_SEL_LOW 0u -#define QEIV2_UVW_POS_OPT_NEX_SEL_HIGH 3u - -typedef enum qeiv2_uvw_pos_idx { - qeiv2_uvw_pos0 = 0, - qeiv2_uvw_pos1, - qeiv2_uvw_pos2, - qeiv2_uvw_pos3, - qeiv2_uvw_pos4, - qeiv2_uvw_pos5, -} qeiv2_uvw_pos_idx_t; /**< qeiv2_uvw_pos_idx_t */ - -/** - * @brief phase counter compare match config structure - * - */ -typedef struct { - uint32_t phcnt_cmp_value; - bool ignore_rotate_dir; - qeiv2_rotate_dir_t rotate_dir; - bool ignore_zcmp; - uint32_t zcmp_value; -} qeiv2_phcnt_cmp_match_config_t; - -/** - * @brief position compare match config structure - * - */ -typedef struct { - uint32_t pos_cmp_value; - bool ignore_pos_dir; - qeiv2_position_dir_t pos_dir; -} qeiv2_pos_cmp_match_config_t; - -/** - * @brief uvw config structure - */ -typedef struct { - qeiv2_uvw_pos_opt_t pos_opt; - qeiv2_uvw_pos_sel_t u_pos_sel[6]; - qeiv2_uvw_pos_sel_t v_pos_sel[6]; - qeiv2_uvw_pos_sel_t w_pos_sel[6]; - uint32_t pos_cfg[6]; -} qeiv2_uvw_config_t; - -/** - * @brief adc config structure - */ -typedef struct { - uint8_t adc_select; - uint8_t adc_channel; - int16_t param0; - int16_t param1; - uint32_t offset; -} qeiv2_adc_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief load phcnt, zcnt, spdcnt and tmrcnt into their read registers - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_load_counter_to_read_registers(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->CR |= QEIV2_CR_READ_MASK; -} - -/** - * @brief config z phase counter increment and decrement mode - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mode - * @arg 1 zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * @arg 0 zcnt will increment or decrement when Z input assert - */ -static inline void qeiv2_config_z_phase_counter_mode(QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode) -{ - qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ZCNTCFG_MASK) | QEIV2_CR_ZCNTCFG_SET(mode); -} - -/** - * @brief config phase max value and phase param - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] phmax maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - */ -static inline void qeiv2_config_phmax_phparam(QEIV2_Type *qeiv2_x, uint32_t phmax) -{ - uint32_t tmp; - - if (phmax > 0u) { - phmax--; - } - qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax); - if (phmax == 0u) { - qeiv2_x->PHASE_PARAM = 0xFFFFFFFFu; - } else { - tmp = (0x80000000u / (phmax + 1u)); - tmp <<= 1u; - qeiv2_x->PHASE_PARAM = QEIV2_PHASE_PARAM_PHASE_PARAM_SET(tmp); - } -} - -/** - * @brief config phase calibration value trigged by z phase - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] enable phcnt will set to phidx when Z input assert - * @param[in] phidx phcnt reset value - * @param[in] mode qeiv2_work_mode_t - */ -static inline void qeiv2_config_z_phase_calibration(QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, qeiv2_work_mode_t mode) -{ - uint32_t tmp = qeiv2_x->CR; - qeiv2_x->PHIDX = QEIV2_PHIDX_PHIDX_SET(phidx); - if (enable) { - tmp |= QEIV2_CR_PHCALIZ_MASK; - } else { - tmp &= ~QEIV2_CR_PHCALIZ_MASK; - } - if (enable && ((mode == qeiv2_work_mode_sin) || (mode == qeiv2_work_mode_sincos))) { - tmp |= QEIV2_CR_Z_ONLY_EN_MASK; - } else { - tmp &= ~QEIV2_CR_Z_ONLY_EN_MASK; - } - qeiv2_x->CR = tmp; -} - -/** - * @brief pause counter when pause assert - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] counter_mask - * @arg QEIV2_CR_PAUSEPOS_MASK - * @arg QEIV2_CR_PAUSESPD_MASK - * @arg QEIV2_CR_PAUSEPH_MASK - * @arg QEIV2_CR_PAUSEZ_MASK - * @param[in] enable enable or disable pause - */ -static inline void qeiv2_pause_counter(QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable) -{ - if (enable) { - qeiv2_x->CR |= counter_mask; - } else { - qeiv2_x->CR &= ~counter_mask; - } -} - -/** - * @brief pause pos counter when fault assert - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] enable enable or disable pause - */ -static inline void qeiv2_pause_pos_counter_on_fault(QEIV2_Type *qeiv2_x, bool enable) -{ - if (enable) { - qeiv2_x->CR |= QEIV2_CR_FAULTPOS_MASK; - } else { - qeiv2_x->CR &= ~QEIV2_CR_FAULTPOS_MASK; - } -} - -/** - * @brief enable load phcnt, zcnt, spdcnt and tmrcnt into their snap registers - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_snap(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->CR |= QEIV2_CR_SNAPEN_MASK; -} - -/** - * @brief disable snap - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_snap(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->CR &= ~QEIV2_CR_SNAPEN_MASK; -} - -/** - * @brief reset zcnt, spdcnt and tmrcnt to 0, reset phcnt to phidx. - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_reset_counter(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->CR |= QEIV2_CR_RSTCNT_MASK; -} - -/** - * @brief release counter. - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_release_counter(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->CR &= ~QEIV2_CR_RSTCNT_MASK; -} - -/** - * @brief select spd and tmr register content - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] content @ref qeiv2_spd_tmr_content_t - */ -static inline void qeiv2_select_spd_tmr_register_content(QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content) -{ - qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_RD_SEL_MASK) | QEIV2_CR_RD_SEL_SET(content); -} - -/** - * @brief check spd and tmr register content as pos and angle - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @return true if spd and timer register as pos and angle register - */ -static inline bool qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type *qeiv2_x) -{ - return ((qeiv2_x->CR & QEIV2_CR_RD_SEL_MASK) != 0) ? true : false; -} - -/** - * @brief set qeiv2 work mode - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mode @ref qeiv2_work_mode_t - */ -static inline void qeiv2_set_work_mode(QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode) -{ - qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ENCTYP_MASK) | QEIV2_CR_ENCTYP_SET(mode); -} - -/** - * @brief config watchdog - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] timeout watchdog timeout time - * @param[in] clr_phcnt the phase_cnt time passed, then clear wdog counter - * @param[in] enable - * @arg 1 - enable watchdog - * @arg 0 - disable watchdog - */ -static inline void qeiv2_config_wdog(QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable) -{ - uint32_t tmp; - tmp = QEIV2_WDGCFG_WDGTO_SET(timeout) | QEIV2_WDGCFG_WDOG_CFG_SET(clr_phcnt); - if (enable) { - tmp |= QEIV2_WDGCFG_WDGEN_MASK; - } else { - tmp &= ~QEIV2_WDGCFG_WDGEN_MASK; - } - qeiv2_x->WDGCFG = tmp; -} - -/** - * @brief enable trig out trigger event - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] event_mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_enable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) -{ - qeiv2_x->TRGOEN |= event_mask; -} - -/** - * @brief disable trig out trigger event - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] event_mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_disable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) -{ - qeiv2_x->TRGOEN &= ~event_mask; -} - -/** - * @brief enable load read trigger event - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] event_mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_enable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) -{ - qeiv2_x->READEN |= event_mask; -} - -/** - * @brief disable load read trigger event - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] event_mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_disable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask) -{ - qeiv2_x->READEN &= ~event_mask; -} - -/** - * @brief enable dma request - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_enable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask) -{ - qeiv2_x->DMAEN |= mask; -} - -/** - * @brief disable qeiv2 dma - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_disable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask) -{ - qeiv2_x->DMAEN &= ~mask; -} - -/** - * @brief clear qeiv2 status register - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_clear_status(QEIV2_Type *qeiv2_x, uint32_t mask) -{ - qeiv2_x->SR = mask; -} - -/** - * @brief get qeiv2 status - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval qeiv2 status: - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline uint32_t qeiv2_get_status(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->SR; -} - -/** - * @brief get qeiv2 bit status - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - * @retval true or false - */ -static inline bool qeiv2_get_bit_status(QEIV2_Type *qeiv2_x, uint32_t mask) -{ - return ((qeiv2_x->SR & mask) == mask) ? true : false; -} - -/** - * @brief enable qeiv2 irq - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_enable_irq(QEIV2_Type *qeiv2_x, uint32_t mask) -{ - qeiv2_x->IRQEN |= mask; -} - -/** - * @brief disable qeiv2 irq - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] mask - * @arg @ref QEIV2_EVENT_WDOG_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_PHASE_FLAG_MASK - * @arg @ref QEIV2_EVENT_Z_MISS_FLAG_MASK - * @arg @ref QEIV2_EVENT_WIDTH_TIME_FLAG_MASK - * @arg @ref QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK - * @arg @ref QEIV2_EVENT_DIR_CHG_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_CYCLE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE0_FLAG_MASK - * @arg @ref QEIV2_EVENT_PULSE1_FLAG_MASK - * @arg @ref QEIV2_EVENT_HOME2_FLAG_MASK - * @arg @ref QEIV2_EVENT_FAULT_FLAG_MASK - */ -static inline void qeiv2_disable_irq(QEIV2_Type *qeiv2_x, uint32_t mask) -{ - qeiv2_x->IRQEN &= ~mask; -} - -/** - * @brief get current counter value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] type @ref qeiv2_counter_type_t - * @retval counter value - */ -static inline uint32_t qeiv2_get_current_count(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) -{ - return *(&qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z + type); -} - -/** - * @brief get current phcnt value - * - * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) - * @return phcnt value - */ -static inline uint32_t qeiv2_get_current_phase_phcnt(QEIV2_Type *qeiv2_x) -{ - return QEIV2_COUNT_PH_PHCNT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); -} - -/** - * @brief get current a phase level - * - * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) - * @return a phase level - */ -static inline bool qeiv2_get_current_phase_a_level(QEIV2_Type *qeiv2_x) -{ - return QEIV2_COUNT_PH_ASTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); -} - -/** - * @brief get current b phase level - * - * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) - * @return b phase level - */ -static inline bool qeiv2_get_current_phase_b_level(QEIV2_Type *qeiv2_x) -{ - return QEIV2_COUNT_PH_BSTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); -} - -/** - * @brief get current phase dir - * - * @param qeiv2_x QEI base address, HPM_QEIx(x=0...n) - * @return dir - */ -static inline bool qeiv2_get_current_phase_dir(QEIV2_Type *qeiv2_x) -{ - return QEIV2_COUNT_PH_DIR_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase)); -} - - -/** - * @brief get read event count value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] type @ref qeiv2_counter_type_t - * @retval counter value - */ -static inline uint32_t qeiv2_get_count_on_read_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) -{ - return *(&(qeiv2_x->COUNT[QEIV2_COUNT_READ].Z) + type); -} - -/** - * @brief read the value of each phase snapshot 0 counter - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] type @ref qeiv2_counter_type_t - * @retval counter value - */ -static inline uint32_t qeiv2_get_count_on_snap0_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) -{ - return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP0].Z + type); -} - -/** - * @brief read the value of each phase snapshot 1 counter - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] type @ref qeiv2_counter_type_t - * @retval counter value - */ -static inline uint32_t qeiv2_get_count_on_snap1_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type) -{ - return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP1].Z + type); -} - -/** - * @brief set zcnt compare value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cmp zcnt compare value - */ -static inline void qeiv2_set_z_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) -{ - qeiv2_x->ZCMP = QEIV2_ZCMP_ZCMP_SET(cmp); -} - -/** - * @brief set phcnt compare value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cmp phcnt compare value - */ -static inline void qeiv2_set_phcnt_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) -{ - qeiv2_x->PHCMP = QEIV2_PHCMP_PHCMP_SET(cmp); -} - -/** - * @brief set spdcnt or position compare value. It's selected by CR register rd_sel bit. - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cmp spdcnt or position compare value - * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) - * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) - */ -static inline void qeiv2_set_spd_pos_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp) -{ - qeiv2_x->SPDCMP = QEIV2_SPDCMP_SPDCMP_SET(cmp); -} - -/** - * @brief set compare match options - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] ignore_zcmp ignore zcmp - * @param[in] ignore_phcmp ignore phcmp - * @param[in] ignore_spdposcmp ignore spdposcmp - * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) - * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) - * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder) - * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder) - * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder) - * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder) - */ -static inline void qeiv2_set_cmp_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, - bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) -{ - qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & (~(QEIV2_MATCH_CFG_ZCMPDIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK | QEIV2_MATCH_CFG_SPDCMPDIS_MASK - | QEIV2_MATCH_CFG_DIRCMPDIS_MASK | QEIV2_MATCH_CFG_DIRCMP_MASK - | QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK))) - | QEIV2_MATCH_CFG_ZCMPDIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(ignore_phcmp) - | QEIV2_MATCH_CFG_SPDCMPDIS_SET(ignore_spdposcmp) - | QEIV2_MATCH_CFG_DIRCMPDIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP_SET(rotate_dir) - | QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(pos_dir); -} - -/** - * @brief set zcnt compare2 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cmp zcnt compare2 value - */ -static inline void qeiv2_set_z_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) -{ - qeiv2_x->ZCMP2 = QEIV2_ZCMP2_ZCMP2_SET(cmp); -} - -/** - * @brief set phcnt compare2 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cmp phcnt compare2 value - */ -static inline void qeiv2_set_phcnt_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) -{ - qeiv2_x->PHCMP2 = QEIV2_PHCMP2_PHCMP2_SET(cmp); -} - -/** - * @brief set spdcnt or position compare2 value. It's selected by CR register rd_sel bit. - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cmp spdcnt or position compare2 value - */ -static inline void qeiv2_set_spd_pos_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp) -{ - qeiv2_x->SPDCMP2 = QEIV2_SPDCMP2_SPDCMP2_SET(cmp); -} - -/** - * @brief set compare2 match options - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] ignore_zcmp ignore zcmp - * @param[in] ignore_phcmp ignore phcmp - * @param[in] ignore_spdposcmp ignore spdposcmp. - * when set @ref qeiv2_spd_tmr_as_spd_tm, this is spdcmp value. (ABZ encoder) - * when set @ref qeiv2_spd_tmr_as_pos_angle, this is poscmp value. (sin or sincos encoder) - * @param[in] ignore_rotate_dir ignore encoder rotation direction. (ABZ encoder) - * @param[in] rotate_dir when don't ignore rotation direction, match rotation direction. @ref qeiv2_rotate_dir_t. (ABZ encoder) - * @param[in] ignore_pos_dir ignore position increase or decrease direction. (sin or sincos encoder) - * @param[in] pos_dir when don't ignore position direction, match position direction. @ref qeiv2_position_dir_t. (sin or sincos encoder) - */ -static inline void qeiv2_set_cmp2_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp, - bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir) -{ - qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & ~(QEIV2_MATCH_CFG_ZCMP2DIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK | QEIV2_MATCH_CFG_SPDCMP2DIS_MASK - | QEIV2_MATCH_CFG_DIRCMP2DIS_MASK | QEIV2_MATCH_CFG_DIRCMP2_MASK - | QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)) - | QEIV2_MATCH_CFG_ZCMP2DIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(ignore_phcmp) - | QEIV2_MATCH_CFG_SPDCMP2DIS_SET(ignore_spdposcmp) - | QEIV2_MATCH_CFG_DIRCMP2DIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP2_SET(rotate_dir) - | QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(pos_dir); -} - -/** - * @brief config signal enablement and edge - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] siga_en enable signal A/U - * @param[in] sigb_en enable signal B/V - * @param[in] sigz_en enable signal Z/W - * @param[in] posedge_en enable rise edge - * @param[in] negedge_en enable fall edge - */ -static inline void qeiv2_config_abz_uvw_signal_edge(QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en) -{ - qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~(QEIV2_QEI_CFG_SIGA_EN_MASK | QEIV2_QEI_CFG_SIGB_EN_MASK | QEIV2_QEI_CFG_SIGZ_EN_MASK - | QEIV2_QEI_CFG_POSIDGE_EN_MASK | QEIV2_QEI_CFG_NEGEDGE_EN_MASK)) - | (QEIV2_QEI_CFG_SIGA_EN_SET(siga_en) | QEIV2_QEI_CFG_SIGB_EN_SET(sigb_en) | QEIV2_QEI_CFG_SIGZ_EN_SET(sigz_en) - | QEIV2_QEI_CFG_POSIDGE_EN_SET(posedge_en) | QEIV2_QEI_CFG_NEGEDGE_EN_SET(negedge_en)); -} - -/** - * @brief set pulse0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num - */ -static inline void qeiv2_set_pulse0_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num) -{ - qeiv2_x->PULSE0_NUM = QEIV2_PULSE0_NUM_PULSE0_NUM_SET(pulse_num); -} - -/** - * @brief get cycle0 snap0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval cycle0 snap0 value - */ -static inline uint32_t qeiv2_get_pulse0_cycle_snap0(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->CYCLE0_SNAP0; -} - -/** - * @brief get cycle0 snap1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval cycle0 snap1 value - */ -static inline uint32_t qeiv2_get_pulse0_cycle_snap1(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->CYCLE0_SNAP1; -} - -/** - * @brief set pulse1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] pulse_num for speed detection, will count the cycle number for configed pulse_num - */ -static inline void qeiv2_set_pulse1_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num) -{ - qeiv2_x->PULSE1_NUM = QEIV2_PULSE1_NUM_PULSE1_NUM_SET(pulse_num); -} - -/** - * @brief get cycle1 snap0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval cycle1 snap0 value - */ -static inline uint32_t qeiv2_get_pulse1_cycle_snap0(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->CYCLE1_SNAP0; -} - -/** - * @brief get cycle1 snap1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval cycle1 snap1 value - */ -static inline uint32_t qeiv2_get_pulse1_cycle_snap1(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->CYCLE1_SNAP1; -} - -/** - * @brief set cycle0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num - */ -static inline void qeiv2_set_cycle0_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num) -{ - qeiv2_x->CYCLE0_NUM = QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(cycle_num); -} - -/** - * @brief get pulse0 snap0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse0 snap0 value - */ -static inline uint32_t qeiv2_get_cycle0_pulse_snap0(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE0_SNAP0; -} - -/** - * @brief get pulse0 snap1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse0 snap1 value - */ -static inline uint32_t qeiv2_get_cycle0_pulse_snap1(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE0_SNAP1; -} - -/** - * @brief get pulse0cycle snap0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse0cycle snap0 value - */ -static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE0CYCLE_SNAP0; -} - -/** - * @brief get pulse0cycle snap1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse0cycle snap1 value - */ -static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE0CYCLE_SNAP1; -} - -/** - * @brief set cycle1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cycle_num for speed detection, will count the pulse number for configed cycle_num - */ -static inline void qeiv2_set_cycle1_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num) -{ - qeiv2_x->CYCLE1_NUM = QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(cycle_num); -} - -#if defined(HPM_IP_FEATURE_QEIV2_ONESHOT_MODE) && HPM_IP_FEATURE_QEIV2_ONESHOT_MODE -/** - * @brief disable cycle0 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_cycle0_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK; -} - -/** - * @brief enable cycle0 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_cycle0_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK; -} - -/** - * @brief disable cycle1 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_cycle1_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK; -} - -/** - * @brief enable cycle1 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_cycle1_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK; -} - -/** - * @brief disable pulse0 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_pulse0_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK; -} - -/** - * @brief enable pulse0 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_pulse0_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK; -} - -/** - * @brief disable pulse1 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_pulse1_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK; -} - -/** - * @brief enable pulse1 oneshot mode - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_pulse1_oneshot_mode(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK; -} -#endif - -#if defined(HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG) && HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG -/** - * @brief disable trigger cycle0 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_trig_cycle0(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK; -} - -/** - * @brief enable trigger cycle0 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_trig_cycle0(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK; -} - -/** - * @brief disable trigger cycle1 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_trig_cycle1(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK; -} - -/** - * @brief enable trigger cycle1 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_trig_cycle1(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK; -} - -/** - * @brief disable trigger pulse0 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_trig_pulse0(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK; -} - -/** - * @brief enable trigger pulse0 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_trig_pulse0(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK; -} - -/** - * @brief disable trigger pulse1 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_disable_trig_pulse1(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK; -} - -/** - * @brief enable trigger pulse1 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_enable_trig_pulse1(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK; -} - -/** - * @brief software restart cycle0 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_sw_restart_cycle0(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK; -} - -/** - * @brief software restart cycle1 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_sw_restart_cycle1(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK; -} - -/** - * @brief software restart pulse0 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_sw_restart_pulse0(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK; -} - -/** - * @brief software restart pulse1 - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - */ -static inline void qeiv2_sw_restart_pulse1(QEIV2_Type *qeiv2_x) -{ - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK; -} -#endif - -/** - * @brief get pulse1 snap0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse1 snap0 value - */ -static inline uint32_t qeiv2_get_cycle1_pulse_snap0(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE1_SNAP0; -} - -/** - * @brief get pulse1 snap1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse1 snap1 value - */ -static inline uint32_t qeiv2_get_cycle1_pulse_snap1(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE1_SNAP1; -} - -/** - * @brief get pulse1cycle snap0 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse1cycle snap0 value - */ -static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE1CYCLE_SNAP0; -} - -/** - * @brief get pulse1cycle snap1 value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval pulse01cycle snap1 value - */ -static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PULSE1CYCLE_SNAP1; -} - -/** - * @brief enable or disable clear counter if detect direction change - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] enable enable or disable clear counter if detect direction change - */ -static inline void qeiv2_clear_counter_when_dir_chg(QEIV2_Type *qeiv2_x, bool enable) -{ - if (enable) { - qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK; - } else { - qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK; - } -} - -/** - * @brief adcx config - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config qeiv2_adc_config_t - * @param[in] enable enable or disable adcx - */ -static inline void qeiv2_config_adcx(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) -{ - uint32_t tmp; - tmp = QEIV2_ADCX_CFG0_X_ADCSEL_SET(config->adc_select) | QEIV2_ADCX_CFG0_X_CHAN_SET(config->adc_channel); - qeiv2_x->ADCX_CFG1 = QEIV2_ADCX_CFG1_X_PARAM1_SET(config->param1) | QEIV2_ADCX_CFG1_X_PARAM0_SET(config->param0); - qeiv2_x->ADCX_CFG2 = QEIV2_ADCX_CFG2_X_OFFSET_SET(config->offset); - if (enable) { - tmp |= QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK; - } else { - tmp &= ~QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK; - } - qeiv2_x->ADCX_CFG0 = tmp; -} - -/** - * @brief adcy config - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config qeiv2_adc_config_t - * @param[in] enable enable or disable adcy - */ -static inline void qeiv2_config_adcy(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable) -{ - uint32_t tmp; - tmp = QEIV2_ADCY_CFG0_Y_ADCSEL_SET(config->adc_select) | QEIV2_ADCY_CFG0_Y_CHAN_SET(config->adc_channel); - qeiv2_x->ADCY_CFG1 = QEIV2_ADCY_CFG1_Y_PARAM1_SET(config->param1) | QEIV2_ADCY_CFG1_Y_PARAM0_SET(config->param0); - qeiv2_x->ADCY_CFG2 = QEIV2_ADCY_CFG2_Y_OFFSET_SET(config->offset); - if (enable) { - tmp |= QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK; - } else { - tmp &= ~QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK; - } - qeiv2_x->ADCY_CFG0 = tmp; -} - -/** - * @brief set adcx and adcy delay - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] delay x/y delay, default 1.25us@200MHz, max 80ms - */ -static inline void qeiv2_set_adc_xy_delay(QEIV2_Type *qeiv2_x, uint32_t delay) -{ - qeiv2_x->CAL_CFG = QEIV2_CAL_CFG_XY_DELAY_SET(delay); -} - -/** - * @brief set position threshold - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] threshold Position change threshold. When two position changes exceed this value, - * it will be considered as an invalid position and no valid signal will be output. - */ -static inline void qeiv2_set_position_threshold(QEIV2_Type *qeiv2_x, uint32_t threshold) -{ - qeiv2_x->POS_THRESHOLD = QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(threshold); -} - -/** - * @brief set uvw position option - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] opt qeiv2_uvw_pos_opt_t - */ -static inline void qeiv2_set_uvw_position_opt(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt) -{ - qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) | QEIV2_QEI_CFG_UVW_POS_OPT0_SET(opt); -} - -/** - * @brief set config uvw position - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] idx uvw position config index - * @arg @ref qeiv2_uvw_pos_idx_t - * @param[in] u_pos_sel U position selection based by uvw position option - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE - * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW - * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH - * @param[in] v_pos_sel V position selection based by uvw position option - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE - * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW - * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH - * @param[in] w_pos_sel W position selection based by uvw position option - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_LOW - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_HIGH - * @arg @ref QEIV2_UVW_POS_OPT_CUR_SEL_EDGE - * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_LOW - * @arg @ref QEIV2_UVW_POS_OPT_NEX_SEL_HIGH - * @param[in] enable enable this uvw config - */ -static inline void qeiv2_set_uvw_position_sel(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel, - uint8_t w_pos_sel, bool enable) -{ - uint32_t tmp; - tmp = QEIV2_UVW_POS_CFG_U_POS_SEL_SET(u_pos_sel) - | QEIV2_UVW_POS_CFG_V_POS_SEL_SET(v_pos_sel) - | QEIV2_UVW_POS_CFG_W_POS_SEL_SET(w_pos_sel); - if (enable) { - tmp |= QEIV2_UVW_POS_CFG_POS_EN_MASK; - } else { - tmp &= ~QEIV2_UVW_POS_CFG_POS_EN_MASK; - } - qeiv2_x->UVW_POS_CFG[idx] = tmp; -} - -/** - * @brief set uvw position - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] idx uvw position config index - * @arg @ref qeiv2_uvw_pos_idx_t - * @param[in] pos angle corresponding to UVW signal position - */ -static inline void qeiv2_set_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos) -{ - qeiv2_x->UVW_POS[idx] = pos; -} - -/** - * @brief set z phase counter value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cnt z phase counter value - */ -static inline void qeiv2_set_z_phase(QEIV2_Type *qeiv2_x, uint32_t cnt) -{ - qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z = cnt; -} - -/** - * @brief set phase counter value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] cnt phase counter value - */ -static inline void qeiv2_set_phase_cnt(QEIV2_Type *qeiv2_x, uint32_t cnt) -{ - qeiv2_x->PHASE_CNT = cnt; -} - -/** - * @brief get phase counter value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval phase counter value - */ -static inline uint32_t qeiv2_get_phase_cnt(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->PHASE_CNT; -} - -/** - * @brief update phase counter value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] inc set to add value to phase_cnt - * @param[in] dec set to minus value to phase_cnt (set inc and dec same time willl act inc) - * @param[in] value value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation. - */ -static inline void qeiv2_update_phase_cnt(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) -{ - qeiv2_x->PHASE_UPDATE = QEIV2_PHASE_UPDATE_INC_SET(inc) | QEIV2_PHASE_UPDATE_DEC_SET(dec) | QEIV2_PHASE_UPDATE_VALUE_SET(value); -} - -/** - * @brief set position value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] pos position - */ -static inline void qeiv2_set_position(QEIV2_Type *qeiv2_x, uint32_t pos) -{ - qeiv2_x->POSITION = pos; -} - -/** - * @brief get position value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval position value - */ -static inline uint32_t qeiv2_get_postion(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->POSITION; -} - -/** - * @brief update position value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] inc set to add value to position - * @param[in] dec set to minus cnt value to position (set inc and dec same time willl act inc) - * @param[in] value value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation. - */ -static inline void qeiv2_update_position(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value) -{ - qeiv2_x->POSITION_UPDATE = QEIV2_POSITION_UPDATE_INC_SET(inc) | QEIV2_POSITION_UPDATE_DEC_SET(dec) | QEIV2_POSITION_UPDATE_VALUE_SET(value); -} - -/** - * @brief get angle value - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @retval angle value - */ -static inline uint32_t qeiv2_get_angle(QEIV2_Type *qeiv2_x) -{ - return qeiv2_x->ANGLE; -} - -/** - * @brief config position timeout for mmc module - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] tm postion timeout value - * @param[in] enable enable position timeout feature. If timeout, send valid again. - */ -static inline void qeiv2_config_position_timeout(QEIV2_Type *qeiv2_x, uint32_t tm, bool enable) -{ - uint32_t tmp; - tmp = QEIV2_POS_TIMEOUT_TIMEOUT_SET(tm); - if (enable) { - tmp |= QEIV2_POS_TIMEOUT_ENABLE_MASK; - } else { - tmp &= ~QEIV2_POS_TIMEOUT_ENABLE_MASK; - } - qeiv2_x->POS_TIMEOUT = tmp; -} - -/** - * @brief config phcnt compare match condition - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t - * @return status_invalid_argument or status_success - */ -hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config); - -/** - * @brief config position compare match condition - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config @ref qeiv2_pos_cmp_match_config_t - * @return status_invalid_argument or status_success - */ -hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config); - -/** - * @brief config phcnt compare2 match condition - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config @ref qeiv2_phcnt_cmp_match_config_t - * @return status_invalid_argument or status_success - */ -hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config); - -/** - * @brief config position compare2 match condition - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config @ref qeiv2_pos_cmp_match_config_t - * @return status_invalid_argument or status_success - */ -hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config); - -/** - * @brief get uvw position default config - * - * @param[out] config uvw position default config structure pointer - */ -void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config); - -/** - * @brief config uvw position - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] config uvw position config structure pointer - * @return status_invalid_argument or status_success - */ -hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config); - -/** - * @brief config signal filter - * - * @param[in] qeiv2_x QEIV2 base address, HPM_QEIV2x(x=0...n) - * @param[in] phase filter phase - * @arg @ref qeiv2_filter_phase_t - * @param[in] outinv Filter will invert the output - * @param[in] mode qeiv2_filter_mode_t - * @param[in] sync set to enable sychronization input signal with TRGM clock - * @param[in] filtlen defines the filter counter length. - */ -void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_QEIV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h deleted file mode 100644 index e6f98b4dff1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeo_drv.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_QEO_DRV_H -#define HPM_QEO_DRV_H - -#include "hpm_common.h" -#include "hpm_qeo_regs.h" -/** - * @brief QEO driver APIs - * @defgroup qeo_interface QEO driver APIs - * @ingroup qeo_interfaces - * @{ - */ - -typedef enum { - qeo_wave_cosine = 0, - qeo_wave_saddle = 1, - qeo_wave_abs_cosine = 2, - qeo_wave_saw = 3, -} qeo_wave_type_t; - -typedef enum { - qeo_wave_above_max_limit_max_val = 0, - qeo_wave_above_max_limit_zero = 1, - qeo_wave_above_max_limit_max_level0_val = 2, - - qeo_wave_high_area_limit_max_val = 0, - qeo_wave_high_area_limit_max_level0_val = 1, - - qeo_wave_low_area_limit_zero = 0, - qeo_wave_low_area_limit_min_level1_val = 1, - - qeo_wave_below_min_limit_zero = 0, - qeo_wave_below_min_limit_max_val = 1, - qeo_wave_below_min_limit_min_level1_val = 2, -} qeo_wave_limit_t; - -typedef struct { - uint8_t above_max_limit; - uint8_t high_area0_limit; - uint8_t high_area1_limit; - uint8_t low_area0_limit; - uint8_t low_area1_limit; - uint8_t below_min_limit; -} qeo_wave_limit_config_t; - -typedef struct { - qeo_wave_limit_config_t wave0; - qeo_wave_limit_config_t wave1; - qeo_wave_limit_config_t wave2; - uint8_t wave_type; - uint8_t saddle_type; -} qeo_wave_mode_t; - -typedef enum { - qeo_abz_output_abz = 0, /*< A and B are orthogonal signals, Z is zero pulse */ - qeo_abz_output_pulse_revise = 1, /*< A is speed pulse, B is directional pulse, Z not used */ - qeo_abz_output_up_down = 2, /*< A is forward pulse, B is reverse pusle, Z not used */ - qeo_abz_output_three_phase = 3, /*< A/B/Z are 3-phase orthogonal pulse */ -} qeo_abz_type_t; - -/* take effect when output type is qeo_abz_output_abz */ -typedef enum { - qeo_z_pulse_25_percent = 0, - qeo_z_pulse_75_percent = 1, - qeo_z_pulse_100_percent = 2, -} qeo_z_pulse_period_t; - -typedef struct { - bool z_inv_pol; - bool b_inv_pol; - bool a_inv_pol; - uint8_t output_type; /*!< @ref qeo_abz_type_t */ - uint8_t z_pulse_period; /*!< @ref qeo_z_pulse_period_t */ -} qeo_abz_mode_t; - -typedef enum { - qeo_pwm_output_force_0 = 2, - qeo_pwm_output_force_1 = 3, - qeo_pwm_output_not_force = 0, -} qeo_pwm_force_output_t; - -typedef enum { - qeo_pwm_safety_output_0 = 0, - qeo_pwm_safety_output_1 = 1, - qeo_pwm_safety_output_highz = 2, -} qeo_pwm_safety_output_t; - -typedef struct { - uint8_t pwm0_output; /*!< @ref qeo_pwm_force_output_t */ - uint8_t pwm1_output; - uint8_t pwm2_output; - uint8_t pwm3_output; - uint8_t pwm4_output; - uint8_t pwm5_output; - uint8_t pwm6_output; - uint8_t pwm7_output; -} qeo_pwm_phase_output_table_t; - -typedef struct { - uint8_t pwm0_output; /*!< @ref qeo_pwm_safety_output_t */ - uint8_t pwm1_output; - uint8_t pwm2_output; - uint8_t pwm3_output; - uint8_t pwm4_output; - uint8_t pwm5_output; - uint8_t pwm6_output; - uint8_t pwm7_output; -} qeo_pwm_safety_output_table_t; - -typedef struct { - uint8_t phase_num; - bool shield_hardware_trig_safety; - bool revise_pairs_output; -} qeo_pwm_mode_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* WAVE API */ -/** - * @brief QEO set resolution lines for wave mode - * @param [in] base QEO base address - * @param [in] lines resolution lines - */ -static inline void qeo_wave_set_resolution_lines(QEO_Type *base, uint32_t lines) -{ - base->WAVE.RESOLUTION = QEO_WAVE_RESOLUTION_LINES_SET(lines); -} - -/** - * @brief QEO set output type for wave mode - * @param [in] base QEO base address - * @param [in] type qeo_wave_type_t - */ -static inline void qeo_wave_set_output_type(QEO_Type *base, qeo_wave_type_t type) -{ - base->WAVE.MODE = (base->WAVE.MODE & ~QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(type); -} - -/** - * @brief QEO set saddle type for wave mode - * @param [in] base QEO base address - * @param [in] standard true for standard saddle, false for triangular wave stacking - */ -static inline void qeo_wave_set_saddle_type(QEO_Type *base, bool standard) -{ - if (standard) { - base->WAVE.MODE &= ~QEO_WAVE_MODE_SADDLE_TYPE_MASK; - } else { - base->WAVE.MODE |= QEO_WAVE_MODE_SADDLE_TYPE_MASK; - } -} - -/** - * @brief QEO set phase shift for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] angle left shift angle - */ -static inline void qeo_wave_set_phase_shift(QEO_Type *base, uint8_t index, double angle) -{ - assert((angle >= 0) && (angle <= 360)); - uint32_t val = (uint32_t)(angle * 0x10000U / 360); - base->WAVE.PHASE_SHIFT[index] = QEO_WAVE_PHASE_SHIFT_VAL_SET(val); -} - -/** - * @brief QEO enable vd vq inject for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] vd_val vd value - * @param [in] vq_val vq value - */ -static inline void qeo_wave_enable_vd_vq_inject(QEO_Type *base, uint8_t index, int32_t vd_val, int32_t vq_val) -{ - (void) vd_val; - assert(index < 3); - base->WAVE.MODE |= (1U << (QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT + index)); - base->WAVE.VD_VQ_INJECT[index] = QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(vq_val) | QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(vq_val); -} - -/** - * @brief QEO disable vd vq inject for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - */ -static inline void qeo_wave_disable_vd_vq_inject(QEO_Type *base, uint8_t index) -{ - assert(index < 3); - base->WAVE.MODE &= ~(1U << (QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT + index)); -} - -/** - * @brief QEO load vd vq inject value for wave mode - * @param [in] base QEO base address - */ -static inline void qeo_wave_load_vd_vq(QEO_Type *base) -{ - base->WAVE.VD_VQ_LOAD = QEO_WAVE_VD_VQ_LOAD_LOAD_MASK; -} - -/** - * @brief QEO enable amplitude for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] amp amplitude value - */ -static inline void qeo_wave_enable_amplitude(QEO_Type *base, uint8_t index, double amp) -{ - assert(amp > 0); - uint32_t val = (uint32_t)(amp * (1U << 12U)); - base->WAVE.AMPLITUDE[index] = QEO_WAVE_AMPLITUDE_EN_SCAL_MASK | QEO_WAVE_AMPLITUDE_AMP_VAL_SET(val); -} - -/** - * @brief QEO disable amplitude for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - */ -static inline void qeo_wave_disable_amplitude(QEO_Type *base, uint8_t index) -{ - base->WAVE.AMPLITUDE[index] &= ~QEO_WAVE_AMPLITUDE_EN_SCAL_MASK; -} - -/** - * @brief QEO set mid point shift for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] shift mid point shift value - */ -static inline void qeo_wave_set_mid_point_shift(QEO_Type *base, uint8_t index, double shift) -{ - int32_t val = (int32_t)(shift * (1U << 27U)); - base->WAVE.MID_POINT[index] = QEO_WAVE_MID_POINT_VAL_SET(val); -} - -/** - * @brief QEO set max limmit for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] limit0 limit0 value - * @param [in] limit1 limit1 value - */ -static inline void qeo_wave_set_max_limit(QEO_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) -{ - base->WAVE.LIMIT[index].MAX = QEO_WAVE_LIMIT_MAX_LIMIT0_SET(limit0) | QEO_WAVE_LIMIT_MAX_LIMIT1_SET(limit1); -} - -/** - * @brief QEO set min limmit for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] limit0 limit0 value - * @param [in] limit1 limit1 value - */ -static inline void qeo_wave_set_min_limit(QEO_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) -{ - base->WAVE.LIMIT[index].MIN = QEO_WAVE_LIMIT_MIN_LIMIT0_SET(limit0) | QEO_WAVE_LIMIT_MIN_LIMIT1_SET(limit1); -} - -/** - * @brief QEO set deadzone shift for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] shift deadzone shift value - */ -static inline void qeo_wave_set_deadzone_shift(QEO_Type *base, uint8_t index, int16_t shift) -{ - base->WAVE.DEADZONE_SHIFT[index] = QEO_WAVE_DEADZONE_SHIFT_VAL_SET(shift); -} - -/** - * @brief QEO get wave output value - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @retval wave output value - */ -static inline uint16_t qeo_get_wave_output_val(QEO_Type *base, uint8_t index) -{ - if (index == 0) { - return QEO_DEBUG0_WAVE0_GET(base->DEBUG0); - } else if (index == 1) { - return QEO_DEBUG0_WAVE1_GET(base->DEBUG0); - } else if (index == 2) { - return QEO_DEBUG1_WAVE2_GET(base->DEBUG1); - } - return 0; -} - -/** - * @brief QEO wave get defalut mode config - * @param [in] base QEO base address - * @param [in] config qeo_wave_mode_t - */ -void qeo_wave_get_default_mode_config(QEO_Type *base, qeo_wave_mode_t *config); - -/** - * @brief QEO wave config mode - * @param [in] base QEO base address - * @param [in] config qeo_wave_mode_t - */ -void qeo_wave_config_mode(QEO_Type *base, qeo_wave_mode_t *config); - -/* ABZ API */ -/** - * @brief QEO set resolution lines for ABZ mode - * @param [in] base QEO base address - * @param [in] lines resolution lines - */ -static inline void qeo_abz_set_resolution_lines(QEO_Type *base, uint32_t lines) -{ - base->ABZ.RESOLUTION = QEO_ABZ_RESOLUTION_LINES_SET(lines); -} - -/** - * @brief QEO set phase shift for ABZ mode - * @param [in] base QEO base address - * @param [in] index ABZ index(0/1/2) - * @param [in] angle left shift angle - */ -static inline void qeo_abz_set_phase_shift(QEO_Type *base, uint8_t index, double angle) -{ - assert((angle >= 0) && (angle <= 360)); - uint32_t val = (uint32_t)(angle * 0x10000U / 360); - base->ABZ.PHASE_SHIFT[index] = QEO_ABZ_PHASE_SHIFT_VAL_SET(val); -} - -/** - * @brief QEO set max frequency for ABZ mode - * @param [in] base QEO base address - * @param [in] src_freq QEO(MOTO system) frequency - * @param [in] freq abz signal frequency (A pulse frequency) - * @retval status_success or status_invalid_argument - */ -hpm_stat_t qeo_abz_set_max_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq); - -/** - * @brief QEO set wdog frequency for ABZ mode - * @param [in] base QEO base address - * @param [in] src_freq QEO(MOTO system) frequency - * @param [in] freq wdog frequency - * @retval status_success or status_invalid_argument - */ -hpm_stat_t qeo_abz_set_wdog_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq); - -/** - * @brief QEO disable wdog for ABZ mode - * @param [in] base QEO base address - */ -static inline void qeo_abz_disable_wdog(QEO_Type *base) -{ - base->ABZ.MODE &= ~QEO_ABZ_MODE_EN_WDOG_MASK; -} - -/** - * @brief QEO config reverse edge for ABZ mode - * @param [in] base QEO base address - * @param [in] speed_pulse_negedge true for reverse edge point speed pulse's negedge - * false for reverse edge point between speed pulse's posedge and negedge, min period dedicated by the num line_width - * - * @note take effect when ABZ work on qeo_abz_output_pulse_revise mode - */ -static inline void qeo_abz_config_reverse_edge(QEO_Type *base, bool speed_pulse_negedge) -{ - if (speed_pulse_negedge) { - base->ABZ.MODE |= QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; - } else { - base->ABZ.MODE &= ~QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; - } -} - -/** - * @brief QEO sync position for ABZ mode - * @param [in] base QEO base address - * @param [in] lines ABZ line counter - * @param [in] sync_pos the position value to be synchronized - */ -void qeo_abz_position_sync(QEO_Type *base, uint32_t lines, uint32_t sync_pos); - -/** - * @brief QEO ABZ get default mode config - * @param [in] base QEO base address - * @param [in] config qeo_abz_mode_t - */ -void qeo_abz_get_default_mode_config(QEO_Type *base, qeo_abz_mode_t *config); - -/** - * @brief QEO ABZ config mode - * @param [in] base QEO base address - * @param [in] config qeo_abz_mode_t - */ -void qeo_abz_config_mode(QEO_Type *base, qeo_abz_mode_t *config); - -/* PWM API */ -/** - * @brief QEO set resolution lines for PWM mode - * @param [in] base QEO base address - * @param [in] lines resolution lines - */ -static inline void qeo_pwm_set_resolution_lines(QEO_Type *base, uint32_t lines) -{ - base->PWM.RESOLUTION = QEO_PWM_RESOLUTION_LINES_SET(lines); -} - -/** - * @brief QEO set phase shift for PWM mode - * @param [in] base QEO base address - * @param [in] index PWM index(0/1/2/3) - * @param [in] angle left shift angle - */ -static inline void qeo_pwm_set_phase_shift(QEO_Type *base, uint8_t index, double angle) -{ - assert((angle >= 0) && (angle <= 360)); - uint32_t val = (uint32_t)(angle * 0x10000U / 360); - base->PWM.PHASE_SHIFT[index] = QEO_PWM_PHASE_SHIFT_VAL_SET(val); -} - -/** - * @brief QEO PWM check if it is triggered by hardware to enter safety mode - * - * @note This bit is only valid if the hardware trigger source has not been cleared - * - * @param [in] base QEO base address - * @retval true or false - */ -static inline bool qeo_pwm_check_hardware_trig_safety(QEO_Type *base) -{ - return ((base->STATUS & QEO_STATUS_PWM_SAFETY_MASK) != 0) ? true : false; -} - -/** - * @brief QEO PWM select phase table - * @param [in] base QEO base address - * @param [in] positive true for using positive phase table, false for using negative phase table - */ -static inline void qeo_pwm_select_phase_table(QEO_Type *base, bool positive) -{ - if (positive) { - base->PWM.MODE &= ~QEO_PWM_MODE_REVISE_UP_DN_MASK; - } else { - base->PWM.MODE |= QEO_PWM_MODE_REVISE_UP_DN_MASK; - } -} - -/** - * @brief QEO PWM enter safety mode by software - * - * @note call qeo_pwm_software_exit_safety to exit safety mode - * - * @param [in] base QEO base address - */ -static inline void qeo_pwm_software_enter_safety(QEO_Type *base) -{ - base->PWM.MODE |= QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; -} - -/** - * @brief QEO PWM exit safety mode by software - * @param [in] base QEO base address - */ -static inline void qeo_pwm_software_exit_safety(QEO_Type *base) -{ - base->PWM.MODE &= ~QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; -} - -/** - * @brief QEO PWM get default mode config - * @param [in] base QEO base address - * @param [in] config qeo_pwm_mode_t - */ -void qeo_pwm_get_default_mode_config(QEO_Type *base, qeo_pwm_mode_t *config); - -/** - * @brief QEO PWM config mode - * @param [in] base QEO base address - * @param [in] config qeo_pwm_mode_t - */ -void qeo_pwm_config_mode(QEO_Type *base, qeo_pwm_mode_t *config); - -/** - * @brief QEO PWM get default safety table - * @param [in] base QEO base address - * @param [in] table qeo_pwm_safety_output_table_t - */ -void qeo_pwm_get_default_safety_table_config(QEO_Type *base, qeo_pwm_safety_output_table_t *table); - -/** - * @brief QEO PWM get default phase table - * @param [in] base QEO base address - * @param [in] table qeo_pwm_phase_output_table_t - */ -void qeo_pwm_get_default_phase_table_config(QEO_Type *base, qeo_pwm_phase_output_table_t *table); - -/** - * @brief QEO PWM config safety table - * @param [in] base QEO base address - * @param [in] table qeo_pwm_safety_output_table_t - */ -void qeo_pwm_config_safety_table(QEO_Type *base, qeo_pwm_safety_output_table_t *table); - -/** - * @brief QEO PWM onfig phase table - * @param [in] base QEO base address - * @param [in] index phase table index - * @param [in] table qeo_pwm_phase_output_table_t - */ -void qeo_pwm_config_phase_table(QEO_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table); - -/** - * @brief QEO enable software position inject - * @param [in] base QEO base address - */ -static inline void qeo_enable_software_position_inject(QEO_Type *base) -{ - base->POSTION_SEL |= QEO_POSTION_SEL_POSTION_SEL_MASK; -} - -/** - * @brief QEO software inject position - * @param [in] base QEO base address - * @param [in] position position value - */ -static inline void qeo_software_position_inject(QEO_Type *base, uint32_t position) -{ - base->POSTION_SOFTWARE = QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(position); -} - -/** - * @brief QEO disable software position inject, QEO will using position from hardware - * @param [in] base QEO base address - */ -static inline void qeo_disable_software_position_inject(QEO_Type *base) -{ - base->POSTION_SEL &= ~QEO_POSTION_SEL_POSTION_SEL_MASK; -} - -/** - * @brief QEO check calculate finish status - * @param [in] base QEO base address - * @retval true or false - */ -static inline bool qeo_check_calculate_finish(QEO_Type *base) -{ - return (QEO_DEBUG1_QEO_FINISH_GET(base->DEBUG1) != 0) ? true : false; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_QEO_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeov2_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeov2_drv.h deleted file mode 100644 index fd3127de3d5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeov2_drv.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_QEOV2_DRV_H -#define HPM_QEOV2_DRV_H - -#include "hpm_common.h" -#include "hpm_qeov2_regs.h" -/** - * @brief QEOV2 driver APIs - * @defgroup qeov2_interface QEOV2 driver APIs - * @ingroup qeov2_interfaces - * @{ - */ - -typedef enum { - qeo_wave_cosine = 0, - qeo_wave_saddle = 1, - qeo_wave_abs_cosine = 2, - qeo_wave_saw = 3, -} qeo_wave_type_t; - -typedef enum { - qeo_saddle_standard = 0, - qeo_saddle_triple -} qeo_saddle_type_t; - -typedef enum { - qeo_wave_above_max_limit_max_val = 0, - qeo_wave_above_max_limit_zero = 1, - qeo_wave_above_max_limit_max_level0_val = 2, - - qeo_wave_high_area_limit_max_val = 0, - qeo_wave_high_area_limit_max_level0_val = 1, - - qeo_wave_low_area_limit_zero = 0, - qeo_wave_low_area_limit_min_level1_val = 1, - - qeo_wave_below_min_limit_zero = 0, - qeo_wave_below_min_limit_max_val = 1, - qeo_wave_below_min_limit_min_level1_val = 2, -} qeo_wave_limit_t; - -typedef struct { - qeo_wave_limit_t above_max_limit; - qeo_wave_limit_t high_area0_limit; - qeo_wave_limit_t high_area1_limit; - qeo_wave_limit_t low_area0_limit; - qeo_wave_limit_t low_area1_limit; - qeo_wave_limit_t below_min_limit; -} qeo_wave_limit_config_t; - -typedef struct { - qeo_wave_limit_config_t wave0; - qeo_wave_limit_config_t wave1; - qeo_wave_limit_config_t wave2; - bool dq_valid_trig_enable; /*!< DQ valid trigger calculate */ - bool pos_valid_trig_enable; /*!< Position valid trigger calculate */ - bool vd_vq_inject_enable; - bool vd_vq_from_sw; /*!< true: DQ from register; false: DQ from CLC module */ - qeo_wave_type_t wave_type; - qeo_saddle_type_t saddle_type; -} qeo_wave_mode_t; - -typedef enum { - qeo_abz_output_abz = 0, /*!< A and B are orthogonal signals, Z is zero pulse */ - qeo_abz_output_pulse_revise = 1, /*!< A is speed pulse, B is directional pulse, Z not used */ - qeo_abz_output_up_down = 2, /*!< A is forward pulse, B is reverse pusle, Z not used */ - qeo_abz_output_three_phase = 3, /*!< A/B/Z are 3-phase orthogonal pulse */ -} qeo_abz_type_t; - -typedef enum { - qeo_z_as_zero_signal_mode0 = 0, - qeo_z_as_zero_signal_mode1 = 1, - qeo_z_as_no_output_signal = 2, - qeo_z_as_third_phase_signal = 3, -} qeo_z_pulse_type_t; - -typedef struct { - bool z_inv_pol; - bool b_inv_pol; - bool a_inv_pol; - bool enable_wdog; - bool sync_step_position; - bool reverse_align_clk_falling_edge; - qeo_abz_type_t output_type; /*!< @ref qeo_abz_type_t */ -} qeo_abz_mode_t; - -/*!< zero pusle legth mode */ -typedef struct { - uint8_t type; - uint32_t start_line; - uint32_t end_line; - uint8_t start_step; - uint8_t end_step; - uint32_t width; -} qeo_z_output_mode_t; - -typedef enum { - qeo_pwm_output_force_0 = 2, - qeo_pwm_output_force_1 = 3, - qeo_pwm_output_not_force = 0, -} qeo_pwm_force_output_t; - -typedef enum { - qeo_pwm_safety_output_0 = 0, - qeo_pwm_safety_output_1 = 1, - qeo_pwm_safety_output_highz = 2, -} qeo_pwm_safety_output_t; - -typedef struct { - qeo_pwm_force_output_t pwm0_output; /*!< @ref qeo_pwm_force_output_t */ - qeo_pwm_force_output_t pwm1_output; - qeo_pwm_force_output_t pwm2_output; - qeo_pwm_force_output_t pwm3_output; - qeo_pwm_force_output_t pwm4_output; - qeo_pwm_force_output_t pwm5_output; - qeo_pwm_force_output_t pwm6_output; - qeo_pwm_force_output_t pwm7_output; -} qeo_pwm_phase_output_table_t; - -typedef struct { - qeo_pwm_safety_output_t pwm0_output; /*!< @ref qeo_pwm_safety_output_t */ - qeo_pwm_safety_output_t pwm1_output; - qeo_pwm_safety_output_t pwm2_output; - qeo_pwm_safety_output_t pwm3_output; - qeo_pwm_safety_output_t pwm4_output; - qeo_pwm_safety_output_t pwm5_output; - qeo_pwm_safety_output_t pwm6_output; - qeo_pwm_safety_output_t pwm7_output; -} qeo_pwm_safety_output_table_t; - -typedef struct { - uint8_t phase_num; - bool shield_hardware_trig_safety; - bool revise_pairs_output; -} qeo_pwm_mode_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* WAVE API */ -/** - * @brief QEO set resolution lines for wave mode - * @param [in] base QEO base address - * @param [in] lines resolution lines - */ -static inline void qeo_wave_set_resolution_lines(QEOV2_Type *base, uint32_t lines) -{ - base->WAVE.RESOLUTION = QEOV2_WAVE_RESOLUTION_LINES_SET(lines); -} - -/** - * @brief QEO set output type for wave mode - * @param [in] base QEO base address - * @param [in] type qeo_wave_type_t - */ -static inline void qeo_wave_set_output_type(QEOV2_Type *base, qeo_wave_type_t type) -{ - base->WAVE.MODE = (base->WAVE.MODE & ~QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) | QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(type); -} - -/** - * @brief QEO set saddle type for wave mode - * @param [in] base QEO base address - * @param [in] standard true for standard saddle, false for triangular wave stacking - */ -static inline void qeo_wave_set_saddle_type(QEOV2_Type *base, bool standard) -{ - if (standard) { - base->WAVE.MODE &= ~QEOV2_WAVE_MODE_SADDLE_TYPE_MASK; - } else { - base->WAVE.MODE |= QEOV2_WAVE_MODE_SADDLE_TYPE_MASK; - } -} - -/** - * @brief QEO set phase shift for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] angle left shift angle - */ -static inline void qeo_wave_set_phase_shift(QEOV2_Type *base, uint8_t index, double angle) -{ - assert((angle >= 0) && (angle <= 360)); - uint32_t val = (uint32_t)(angle * 0x100000000UL / 360); - base->WAVE.PHASE_SHIFT[index] = QEOV2_WAVE_PHASE_SHIFT_VAL_SET(val); -} - -/** - * @brief QEO enable vd vq inject and select vq vq source for wave mode - * @param [in] base QEO base address - * @param [in] from_sw false for vd vq data from clc module, true for vd vq from software inject register - */ -static inline void qeo_wave_enable_vd_vq_inject(QEOV2_Type *base, bool from_sw) -{ - if (from_sw) { - base->WAVE.MODE |= QEOV2_WAVE_MODE_VD_VQ_SEL_MASK; - } else { - base->WAVE.MODE &= ~QEOV2_WAVE_MODE_VD_VQ_SEL_MASK; - } - base->WAVE.MODE |= QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK; -} - -/** - * @brief QEO disable vd vq inject for wave mode - * @param [in] base QEO base address - */ -static inline void qeo_wave_disable_vd_vq_inject(QEOV2_Type *base) -{ - base->WAVE.MODE &= ~QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK; -} - -/** - * @brief QEO config vd vq value when vd vq from register - * @param [in] base QEO base address - * @param [in] vd_val vd value - * @param [in] vq_val vq value - */ -static inline void qeo_wave_config_vd_vq_value(QEOV2_Type *base, int32_t vd_val, int32_t vq_val) -{ - base->WAVE.VD_INJECT = QEOV2_WAVE_VD_INJECT_VD_VAL_SET(vd_val); - base->WAVE.VQ_INJECT = QEOV2_WAVE_VQ_INJECT_VQ_VAL_SET(vq_val); -} - -/** - * @brief QEO load vd vq inject value when vd vq from register - * @param [in] base QEO base address - */ -static inline void qeo_wave_load_vd_vq(QEOV2_Type *base) -{ - base->WAVE.VD_VQ_LOAD = QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK; -} - -/** - * @brief QEO enable amplitude for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] amp amplitude value - */ -static inline void qeo_wave_enable_amplitude(QEOV2_Type *base, uint8_t index, double amp) -{ - assert(amp > 0); - uint32_t val = (uint32_t)(amp * (1U << 12U)); - base->WAVE.AMPLITUDE[index] = QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK | QEOV2_WAVE_AMPLITUDE_AMP_VAL_SET(val); -} - -/** - * @brief QEO disable amplitude for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - */ -static inline void qeo_wave_disable_amplitude(QEOV2_Type *base, uint8_t index) -{ - base->WAVE.AMPLITUDE[index] &= ~QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK; -} - -/** - * @brief QEO set mid point shift for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] shift mid point shift value - */ -static inline void qeo_wave_set_mid_point_shift(QEOV2_Type *base, uint8_t index, double shift) -{ - int32_t val = (int32_t)(shift * (1U << 27U)); - base->WAVE.MID_POINT[index] = QEOV2_WAVE_MID_POINT_VAL_SET(val); -} - -/** - * @brief QEO set max limmit for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] limit0 limit0 value - * @param [in] limit1 limit1 value - */ -static inline void qeo_wave_set_max_limit(QEOV2_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) -{ - base->WAVE.LIMIT0[index].MAX_LEVEL0 = QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SET(limit0); - base->WAVE.LIMIT1[index].MAX_LEVEL1 = QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SET(limit1); -} - -/** - * @brief QEO set min limmit for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] limit0 limit0 value - * @param [in] limit1 limit1 value - */ -static inline void qeo_wave_set_min_limit(QEOV2_Type *base, uint8_t index, uint32_t limit0, uint32_t limit1) -{ - base->WAVE.LIMIT0[index].MIN_LEVEL0 = QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SET(limit0); - base->WAVE.LIMIT1[index].MIN_LEVEL1 = QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SET(limit1); -} - -/** - * @brief QEO set deadzone shift for wave mode - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @param [in] shift deadzone shift value - */ -static inline void qeo_wave_set_deadzone_shift(QEOV2_Type *base, uint8_t index, int32_t shift) -{ - base->WAVE.DEADZONE_SHIFT[index] = QEOV2_WAVE_DEADZONE_SHIFT_VAL_SET(shift); -} - -/** - * @brief QEO wave set pwm cycle - * - * @note when cycle is 0, output value is 0 - 0xFFFFFFFF, others, output value is 0 - cycle - * - * @param [in] base QEO base address - * @param [in] cycle pwm period cycle - */ -static inline void qeo_wave_set_pwm_cycle(QEOV2_Type *base, uint32_t cycle) -{ - base->WAVE.PWM_CYCLE = QEOV2_WAVE_PWM_CYCLE_VAL_SET(cycle); -} - -/** - * @brief QEO get wave output value - * @param [in] base QEO base address - * @param [in] index wave index(0/1/2) - * @retval wave output value - */ -static inline uint32_t qeo_get_wave_output_val(QEOV2_Type *base, uint8_t index) -{ - if (index == 0) { - return QEOV2_DEBUG0_VALUE_DAC0_GET(base->DEBUG0); - } else if (index == 1) { - return QEOV2_DEBUG4_VALUE_DAC1_GET(base->DEBUG4); - } else if (index == 2) { - return QEOV2_DEBUG5_VALUE_DAC2_GET(base->DEBUG5); - } - return 0; -} - -/** - * @brief QEO wave get defalut mode config - * @param [in] base QEO base address - * @param [in] config qeo_wave_mode_t - */ -void qeo_wave_get_default_mode_config(QEOV2_Type *base, qeo_wave_mode_t *config); - -/** - * @brief QEO wave config mode - * @param [in] base QEO base address - * @param [in] config qeo_wave_mode_t - */ -void qeo_wave_config_mode(QEOV2_Type *base, qeo_wave_mode_t *config); - -/* ABZ API */ -/** - * @brief QEO set resolution lines for ABZ mode - * @param [in] base QEO base address - * @param [in] lines resolution lines - */ -static inline void qeo_abz_set_resolution_lines(QEOV2_Type *base, uint32_t lines) -{ - base->ABZ.RESOLUTION = QEOV2_ABZ_RESOLUTION_LINES_SET(lines); -} - -/** - * @brief QEO set phase shift for three phase output mode - * @param [in] base QEO base address - * @param [in] index ABZ index(0/1/2) - * @param [in] angle left shift angle - */ -static inline void qeo_abz_set_phase_shift(QEOV2_Type *base, uint8_t index, double angle) -{ - assert((angle >= 0) && (angle <= 360)); - uint32_t val = (uint32_t)(angle * 0x100000000U / 360); - base->ABZ.PHASE_SHIFT[index] = QEOV2_ABZ_PHASE_SHIFT_VAL_SET(val); -} - -/** - * @brief QEO set offset for output signal in ABZ mode - * @param [in] base QEO base address - * @param [in] physical_angle physical angle - */ -static inline void qeo_abz_set_offset(QEOV2_Type *base, double physical_angle) -{ - assert((physical_angle >= 0) && (physical_angle <= 360)); - uint32_t val = (uint32_t)(physical_angle * 0x100000000U / 360); - base->ABZ.OVERALL_OFFSET = QEOV2_ABZ_OVERALL_OFFSET_VAL_SET(val); -} - -/** - * @brief QEO set max frequency for ABZ mode - * @param [in] base QEO base address - * @param [in] src_freq QEO(MOTO system) frequency - * @param [in] freq abz signal frequency (A pulse frequency) - * @retval status_success or status_invalid_argument - */ -hpm_stat_t qeo_abz_set_max_frequency(QEOV2_Type *base, uint32_t src_freq, uint32_t freq); - -/** - * @brief QEO set wdog frequency for ABZ mode - * @param [in] base QEO base address - * @param [in] src_freq QEO(MOTO system) frequency - * @param [in] freq wdog frequency - * @retval status_success or status_invalid_argument - */ -hpm_stat_t qeo_abz_set_wdog_frequency(QEOV2_Type *base, uint32_t src_freq, uint32_t freq); - -/** - * @brief QEO disable wdog for ABZ mode - * @param [in] base QEO base address - */ -static inline void qeo_abz_disable_wdog(QEOV2_Type *base) -{ - base->ABZ.MODE &= ~QEOV2_ABZ_MODE_EN_WDOG_MASK; -} - -/** - * @brief QEO config reverse edge for ABZ mode - * @param [in] base QEO base address - * @param [in] speed_pulse_negedge true for reverse edge point speed pulse's negedge - * false for reverse edge point between speed pulse's posedge and negedge, min period dedicated by the num line_width - * - * @note take effect when ABZ work on qeo_abz_output_pulse_revise mode - */ -static inline void qeo_abz_config_reverse_edge(QEOV2_Type *base, bool speed_pulse_negedge) -{ - if (speed_pulse_negedge) { - base->ABZ.MODE |= QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; - } else { - base->ABZ.MODE &= ~QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK; - } -} - -/** - * @brief QEO ABZ get default mode config - * @param [in] base QEO base address - * @param [in] config qeo_abz_mode_t - */ -void qeo_abz_get_default_mode_config(QEOV2_Type *base, qeo_abz_mode_t *config); - -/** - * @brief QEO ABZ config mode - * @param [in] base QEO base address - * @param [in] config qeo_abz_mode_t - */ -void qeo_abz_config_mode(QEOV2_Type *base, qeo_abz_mode_t *config); - -/** - * @brief QEO ABZ mode enable output - * @param [in] base QEO base address - */ -static inline void qeo_abz_enable_output(QEOV2_Type *base) -{ - base->ABZ.MODE |= QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK; -} - -/** - * @brief QEO ABZ mode disable output - * @param [in] base QEO base address - */ -static inline void qeo_abz_disable_output(QEOV2_Type *base) -{ - base->ABZ.MODE &= ~QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK; -} - -/** - * @brief QEO ABZ mode enable and configure position sync mode - * @param [in] base QEO base address - * @param [in] sync_identical_pos true: sync identical posistion; false: sync step of position - */ -static inline void qeo_abz_enable_position_sync(QEOV2_Type *base, bool sync_identical_pos) -{ - if (sync_identical_pos) { - base->ABZ.MODE |= QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK; - } else { - base->ABZ.MODE &= ~QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK; - } - - base->ABZ.POSTION_SYNC = QEOV2_ABZ_POSTION_SYNC_POSTION_MASK; -} - -/** - * @brief QEO ABZ mode get default zero pulse output mode - * @param [in] base QEO base address - * @param [out] mode qeo_z_output_mode_t - */ -void qeo_abz_get_default_z_output_mode(QEOV2_Type *base, qeo_z_output_mode_t *mode); - -/** - * @brief QEO ABZ mode configure zero pulse output mode - * @param [in] base QEO base address - * @param [in] mode qeo_z_output_mode_t - */ -void qeo_abz_config_z_output_mode(QEOV2_Type *base, qeo_z_output_mode_t *mode); - -/* PWM API */ -/** - * @brief QEO set resolution lines for PWM mode - * @param [in] base QEO base address - * @param [in] lines resolution lines - */ -static inline void qeo_pwm_set_resolution_lines(QEOV2_Type *base, uint32_t lines) -{ - base->PWM.RESOLUTION = QEOV2_PWM_RESOLUTION_LINES_SET(lines); -} - -/** - * @brief QEO set phase shift for PWM mode - * @param [in] base QEO base address - * @param [in] index PWM index(0/1/2/3) - * @param [in] angle left shift angle - */ -static inline void qeo_pwm_set_phase_shift(QEOV2_Type *base, uint8_t index, double angle) -{ - assert((angle >= 0) && (angle <= 360)); - uint32_t val = (uint32_t)(angle * 0x1000010000U / 360); - base->PWM.PHASE_SHIFT[index] = QEOV2_PWM_PHASE_SHIFT_VAL_SET(val); -} - -/** - * @brief QEO PWM mode enable output - * @param [in] base QEO base address - */ -static inline void qeo_pwm_enable_output(QEOV2_Type *base) -{ - base->PWM.MODE |= QEOV2_PWM_MODE_ENABLE_PWM_MASK; -} - -/** - * @brief QEO PWM mode disable output - * @param [in] base QEO base address - */ -static inline void qeo_pwm_disable_output(QEOV2_Type *base) -{ - base->PWM.MODE &= ~QEOV2_PWM_MODE_ENABLE_PWM_MASK; -} - -/** - * @brief QEO PWM check if it is triggered by hardware to enter safety mode - * - * @note This bit is only valid if the hardware trigger source has not been cleared - * - * @param [in] base QEO base address - * @retval true or false - */ -static inline bool qeo_pwm_check_hardware_trig_safety(QEOV2_Type *base) -{ - return ((base->STATUS & QEOV2_STATUS_PWM_SAFETY_MASK) != 0) ? true : false; -} - -/** - * @brief QEO PWM select phase table - * @param [in] base QEO base address - * @param [in] positive true for using positive phase table, false for using negative phase table - */ -static inline void qeo_pwm_select_phase_table(QEOV2_Type *base, bool positive) -{ - if (positive) { - base->PWM.MODE &= ~QEOV2_PWM_MODE_REVISE_UP_DN_MASK; - } else { - base->PWM.MODE |= QEOV2_PWM_MODE_REVISE_UP_DN_MASK; - } -} - -/** - * @brief QEO PWM enter safety mode by software - * - * @note call qeo_pwm_software_exit_safety to exit safety mode - * - * @param [in] base QEO base address - */ -static inline void qeo_pwm_software_enter_safety(QEOV2_Type *base) -{ - base->PWM.MODE |= QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; -} - -/** - * @brief QEO PWM exit safety mode by software - * @param [in] base QEO base address - */ -static inline void qeo_pwm_software_exit_safety(QEOV2_Type *base) -{ - base->PWM.MODE &= ~QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK; -} - -/** - * @brief QEO PWM get default mode config - * @param [in] base QEO base address - * @param [in] config qeo_pwm_mode_t - */ -void qeo_pwm_get_default_mode_config(QEOV2_Type *base, qeo_pwm_mode_t *config); - -/** - * @brief QEO PWM config mode - * @param [in] base QEO base address - * @param [in] config qeo_pwm_mode_t - */ -void qeo_pwm_config_mode(QEOV2_Type *base, qeo_pwm_mode_t *config); - -/** - * @brief QEO PWM get default safety table - * @param [in] base QEO base address - * @param [in] table qeo_pwm_safety_output_table_t - */ -void qeo_pwm_get_default_safety_table_config(QEOV2_Type *base, qeo_pwm_safety_output_table_t *table); - -/** - * @brief QEO PWM get default phase table - * @param [in] base QEO base address - * @param [in] table qeo_pwm_phase_output_table_t - */ -void qeo_pwm_get_default_phase_table_config(QEOV2_Type *base, qeo_pwm_phase_output_table_t *table); - -/** - * @brief QEO PWM config safety table - * @param [in] base QEO base address - * @param [in] table qeo_pwm_safety_output_table_t - */ -void qeo_pwm_config_safety_table(QEOV2_Type *base, qeo_pwm_safety_output_table_t *table); - -/** - * @brief QEO PWM onfig phase table - * @param [in] base QEO base address - * @param [in] index phase table index - * @param [in] table qeo_pwm_phase_output_table_t - */ -void qeo_pwm_config_phase_table(QEOV2_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table); - -/** - * @brief QEO enable software position inject - * @param [in] base QEO base address - */ -static inline void qeo_enable_software_position_inject(QEOV2_Type *base) -{ - base->POSTION_SEL |= QEOV2_POSTION_SEL_POSTION_SEL_MASK; -} - -/** - * @brief QEO software inject position - * @param [in] base QEO base address - * @param [in] position position value - */ -static inline void qeo_software_position_inject(QEOV2_Type *base, uint32_t position) -{ - base->POSTION_SOFTWARE = QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(position); -} - -/** - * @brief QEO disable software position inject, QEO will using position from hardware - * @param [in] base QEO base address - */ -static inline void qeo_disable_software_position_inject(QEOV2_Type *base) -{ - base->POSTION_SEL &= ~QEOV2_POSTION_SEL_POSTION_SEL_MASK; -} - -/** - * @brief QEO check calculate finish status - * @param [in] base QEO base address - * @retval true or false - */ -static inline bool qeo_check_calculate_finish(QEOV2_Type *base) -{ - return (QEOV2_DEBUG1_QEO_FINISH_GET(base->DEBUG1) != 0) ? true : false; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_QEOV2_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h deleted file mode 100644 index 1e385b5eb92..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h +++ /dev/null @@ -1,797 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_RDC_DRV_H -#define HPM_RDC_DRV_H - -#include "hpm_common.h" -#include "hpm_rdc_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief RDC driver APIs - * @defgroup rdc_interface RDC driver APIs - * @ingroup rdc_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif -/** - * @name Initialization and Deinitialization - * @{ - */ - - -/** - * @brief Rdc output precision, use n points to form an excitation signal period. - * - */ -typedef enum rdc_output_precision { - rdc_output_precision_4_point = 0, - rdc_output_precision_8_point = 1, - rdc_output_precision_16_point = 2, - rdc_output_precision_32_point = 3, - rdc_output_precision_64_point = 4, - rdc_output_precision_128_point = 5, - rdc_output_precision_256_point = 6, - rdc_output_precision_512_point = 7, - rdc_output_precision_1024_point = 8, -} rdc_output_precision_t; - -/** - * @brief Pwm output period in samples - * - */ -typedef enum rdc_output_pwm_period { - rdc_output_pwm_period_1_sample = 0, - rdc_output_pwm_period_2_sample, - rdc_output_pwm_period_3_sample, - rdc_output_pwm_period_4_sample, - rdc_output_pwm_period_5_sample, - rdc_output_pwm_period_6_sample, - rdc_output_pwm_period_7_sample, - rdc_output_pwm_period_8_sample, - rdc_output_pwm_period_9_sample, - rdc_output_pwm_period_10_sample, - rdc_output_pwm_period_11_sample, - rdc_output_pwm_period_12_sample, - rdc_output_pwm_period_13_sample, - rdc_output_pwm_period_14_sample, - rdc_output_pwm_period_15_sample, - rdc_output_pwm_period_16_sample, -} rdc_output_pwm_period_t; - - - -/** - * @brief Rdc output mode - * - */ -typedef enum rdc_output_mode { - rdc_output_dac, - rdc_output_pwm -} rdc_output_mode_t; - -/** - * @brief Synchronize output trig adc position - * - */ -typedef enum rdc_sync_out_src { - rdc_sync_out_exc_0_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(0), - rdc_sync_out_exc_90_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(1), - rdc_sync_out_exc_180_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(2), - rdc_sync_out_exc_270_ph = RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(3), - rdc_sync_out_max = RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK, - rdc_sync_out_min = RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK, -} rdc_sync_out_src_t; - -/** - * @brief Select reference point of rectify signal - * - */ -typedef enum rdc_rectify_signal { - rdc_rectify_signal_exc_0_ph = 0, - rdc_rectify_signal_exc_90_ph = 1, - rdc_rectify_signal_exc_180_ph = 2, - rdc_rectify_signal_exc_270_ph = 3, - rdc_rectify_signal_external = 4, - rdc_rectify_signal_external_invert = 5, -} rdc_rectify_signal_t; - -/** - * @brief Time stamp selection for accumulation - * - */ -typedef enum rdc_acc_stamp_time { - rdc_acc_stamp_end_of_acc = 0, /**< End of accumulation */ - rdc_acc_stamp_start_of_acc = 1, /**< Start of accumulation */ - rdc_acc_stamp_center_of_acc = 2, /**< Center of accumulation */ -} rdc_acc_stamp_time_t; - -/** - * @brief Rdc trigger out channel 0 or channel 1 - * - */ -typedef enum rdc_output_trig_chn { - trigger_out_0 = 0, - trigger_out_1 = 1 -} rdc_output_trig_chn_t; - - -/** - * @brief Rdc input channel - * - */ -typedef enum rdc_input_acc_chn { - rdc_acc_chn_i = 0, - rdc_acc_chn_q = 1 -} rdc_input_acc_chn_t; - -typedef enum rdc_input_max_min_value_source { - rdc_value_at_adc = 0, - rdc_value_at_iir = 1 -} rdc_input_max_min_value_source_t; - -/** - * @brief Rdc status flags - * - */ -typedef enum rdc_interrupt_stat { - acc_vld_i_stat = RDC_INT_EN_ACC_VLD_I_EN_MASK, - acc_vld_q_stat = RDC_INT_EN_ACC_VLD_Q_EN_MASK, - rising_delay_i_stat = RDC_INT_EN_RISING_DELAY_I_EN_MASK, - falling_delay_i_stat = RDC_INT_EN_FALLING_DELAY_I_EN_MASK, - rising_delay_q_stat = RDC_INT_EN_RISING_DELAY_Q_EN_MASK, - falling_delay_q_stat = RDC_INT_EN_FALLING_DELAY_Q_EN_MASK, - sample_rising_i_stat = RDC_INT_EN_SAMPLE_RISING_I_EN_MASK, - sample_falling_i_stat = RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK, - sample_rising_q_stat = RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK, - sample_falling_q_stat = RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK, - acc_vld_i_ovh_stat = RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK, - acc_vld_q_ovh_stat = RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK, - acc_vld_i_ovl_stat = RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK, - acc_vld_q_ovl_stat = RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK, - acc_amp_ovh_stat = RDC_INT_EN_ACC_AMP_OVH_EN_MASK, - acc_amp_ovl_stat = RDC_INT_EN_ACC_AMP_OVL_EN_MASK, -} rdc_interrupt_stat_t; - -/** - * @brief Rdc output configuration - * - */ -typedef struct rdc_output_cfg { - rdc_output_mode_t mode; /**< pwm or dac */ - uint32_t excitation_period_cycle; /**< The period of the excitation signal, in cycles */ - rdc_output_precision_t excitation_precision; /**< Excitation signal precision */ - rdc_output_pwm_period_t pwm_period; /**< Pwm period in samples */ - bool output_swap; /**< Swap output of PWM and DAC */ - int32_t amp_offset; /**< Offset for excitation, signed value*/ - uint16_t amp_man; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */ - uint16_t amp_exp; /**< Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp */ - bool pwm_dither_enable; /**< Enable dither of pwm */ - bool pwm_exc_p_low_active; /**< Polarity of exc_p signal */ - bool pwm_exc_n_low_active; /**< Polarity of exc_n signal */ - bool trig_by_hw; /**< Hardware triggered excitation signal generation. Software triggering is required after shutdown */ - uint32_t hw_trig_delay; /**< Trigger in delay timming in bus cycle from rising edge of trigger signal */ - uint8_t dac_chn_i_sel; /**< Output channel selection for i_channel */ - uint8_t dac_chn_q_sel; /**< Output channel selection for q_channel */ - uint8_t pwm_deadzone_p; /**< Exc_p dead zone in clock cycle before swap */ - uint8_t pwm_deadzone_n; /**< Exc_n dead zone in clock cycle before swap */ -} rdc_output_cfg_t; - - -/** - * @brief Rdc input configuration - * - */ -typedef struct rdc_input_cfg { - rdc_rectify_signal_t rectify_signal_sel; /**< Select reference point of rectify signal */ -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) - bool acc_fast; /**< every adc value can be as one accumulate value, */ - rdc_input_max_min_value_source_t max_min_value_position; /**< max min value position */ -#endif - uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change, Only acc_fast is zero, this bit is available */ - rdc_acc_stamp_time_t acc_stamp; /**< Time stamp selection for accumulation */ - uint32_t acc_input_chn_i; /**< Input channel selection for i_channel */ - uint32_t acc_input_port_i; /**< Input port selection for i_channel */ - uint32_t acc_input_chn_q; /**< Input channel selection for q_channel */ - uint32_t acc_input_port_q; /**< Input port selection for q_channel */ -} rdc_input_cfg_t; - -/** - * @brief Accumulated configuration information - * - */ -typedef struct rdc_acc_cfg { - struct { - uint16_t continue_edge_num: 3; /**< Filtering val: 1 - 8 */ - uint16_t edge_distance: 6; /**< Minimum distance between two edges 0-63 */ - }; -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) - bool enable_i_thrs_data_for_acc; /**< enable thrs data for accumulate */ - bool enable_q_thrs_data_for_acc; /**< enable thrs data for accumulate */ -#endif - uint8_t right_shift_without_sign; /**< Right shift without sign bit */ - bool error_data_remove; /**< Toxic accumulation data be removed */ - uint32_t exc_carrier_period; /**< The num in clock cycle for period of excitation 0-NULL others-cycles */ - uint32_t sync_delay_i; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */ - uint32_t sync_delay_q; /**< Delay in clock cycle for synchronous signal, the value should less than half of exc_period.exc_period. */ - uint32_t amp_max; /**< The maximum of acc amplitude */ - uint32_t amp_min; /**< The minimum of acc amplitude */ -} rdc_acc_cfg_t; - -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) -/** - * @brief IIR Filter Configuration - * - */ -typedef struct rdc_iir_cfg { - float b; /**< IIR parameter for b branch */ - float a1; /**< IIR parameter a1 for a1 branch*/ - float a2; /**< IIR parameter a1 for a2 branch*/ - bool enable_lowpass; /**< IIR in lowpass mode */ -} rdc_iir_cfg_t; -#endif - -/** @} */ - -/** - * @name RDC Control - * @{ - */ - -/** - * @brief Rdc output configuration, can be configured pwm output or dac output - * - * @param ptr @ref RDC_Type base - * @param cfg @ref rdc_output_cfg_t - */ -void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg); - -/** - * @brief Rdc input configuration, configuration of adc signal source and calculation parameters - * - * @param ptr @ref RDC_Type base - * @param cfg @ref rdc_input_cfg_t - */ -void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg); - -/** - * @brief Configuration accumulate time, support on the fly change - * - * @param ptr @ref RDC_Type base - * @param len accumulate time 0-255 - */ -static inline void rdc_set_acc_len(RDC_Type *ptr, uint8_t len) -{ - ptr->RDC_CTL = (ptr->RDC_CTL & (~RDC_RDC_CTL_ACC_LEN_MASK)) - | RDC_RDC_CTL_ACC_LEN_SET(len); -} - -/** - * @brief Enable accumulate calculation function - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_acc_enable(RDC_Type *ptr) -{ - ptr->RDC_CTL |= RDC_RDC_CTL_ACC_EN_MASK; -} - -/** - * @brief Disable accumulate calculation function - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_acc_disable(RDC_Type *ptr) -{ - ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK; -} - -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) -/** - * @brief Enable IIR for adc input - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_irr_enable(RDC_Type *ptr) -{ - ptr->RDC_CTL |= RDC_RDC_CTL_IIR_EN_MASK; -} - -/** - * @brief Disable IIR for adc input - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_irr_disable(RDC_Type *ptr) -{ - ptr->RDC_CTL &= ~RDC_RDC_CTL_IIR_EN_MASK; -} - -/** - * @brief enable i thrs data for accumulate - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_enable_i_channel_thrs_data_for_acc(RDC_Type *ptr) -{ - ptr->THRS_I |= RDC_THRS_I_THRS4ACC_MASK; -} - -/** - * @brief disable i thrs data for accumulate - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_disable_i_channel_thrs_data_for_acc(RDC_Type *ptr) -{ - ptr->THRS_I &= ~RDC_THRS_I_THRS4ACC_MASK; -} - -/** - * @brief enable q thrs data for accumulate - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_enable_q_channel_thrs_data_for_acc(RDC_Type *ptr) -{ - ptr->THRS_Q |= RDC_THRS_Q_THRS4ACC_MASK; -} - -/** - * @brief disable q thrs data for accumulate - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_disable_q_channel_thrs_data_for_acc(RDC_Type *ptr) -{ - ptr->THRS_Q &= ~RDC_THRS_Q_THRS4ACC_MASK; -} - -#endif - -/** - * @brief Get the accumulate value - * - * @param ptr @ref RDC_Type base - * @param chn @ref rdc_input_acc_chn_t - * @return uint32_t accumulate value - */ -uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn); - -/** - * @brief Output trigger configuration - * Lead time for trigger out0 or out1 from center of low level , this is a signed value - * @param ptr @ref RDC_Type base - * @param chn @ref rdc_output_trig_chn_t - * @param offset lead_time - */ -void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset); - -/** - * @brief Enable output trigger configuration - * - * @param ptr @ref RDC_Type base - * @param chn @ref rdc_output_trig_chn_t - */ -void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn); - -/** - * @brief Disable rdc output trigger configuration - * - * @param ptr @ref RDC_Type base - * @param chn @ref rdc_output_trig_chn_t - */ -void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn); - -/** - * @brief Select output synchornize signal - * - * @param ptr @ref RDC_Type base - * @param sel @ref rdc_sync_out_src_t - */ -static inline void rdc_sync_output_trig_adc_cfg(RDC_Type *ptr, rdc_sync_out_src_t sel) -{ - ptr->SYNC_OUT_CTRL = sel; -} - -/** - * @brief Enable rdc excite signal - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_exc_enable(RDC_Type *ptr) -{ - ptr->RDC_CTL |= RDC_RDC_CTL_EXC_EN_MASK; -} - -/** - * @brief Disable rdc excite signal - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_exc_disable(RDC_Type *ptr) -{ - ptr->RDC_CTL &= ~RDC_RDC_CTL_EXC_EN_MASK; -} - -/** - * @brief Software triggered excitation signal output - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_output_trig_sw(RDC_Type *ptr) -{ - ptr->RDC_CTL |= RDC_RDC_CTL_EXC_START_MASK; -} - -/** - * @brief Get I-phase maximum - * - * @param ptr @ref RDC_Type base - * @retval - other max value - * - -1 illegal data - */ -int32_t rdc_get_i_maxval(RDC_Type *ptr); - -/** - * @brief Clear Maximum - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_clear_i_maxval(RDC_Type *ptr) -{ - ptr->MAX_I = 0; -} - -/** - * @brief Get I-phase minimum - * - * @param ptr @ref RDC_Type base - * @retval - other max value - * - -1 illegal data - */ -int32_t rdc_get_i_minval(RDC_Type *ptr); - -/** - * @brief Clear I-phase minimum - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_clear_i_minval(RDC_Type *ptr) -{ - ptr->MIN_I = 0; -} - -/** - * @brief Set Acc sync delay - * - * @param ptr @ref RDC_Type base - * @param chn @ref rdc_input_acc_chn_t - * @param delay delay tick - */ -void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay); - -/** - * @brief Delay bettween the delyed trigger and - * the first pwm pulse in clock cycle - * - * @param ptr @ref RDC_Type base - * @retval delay tick - */ -static inline uint32_t rdc_get_sync_output_delay(RDC_Type *ptr) -{ - return RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(ptr->SYNC_OUT_CTRL); -} - -/** - * @brief Get Q-phase maximum - * - * @param ptr @ref RDC_Type base - * @retval - other max value - * - -1 illegal data - */ -int32_t rdc_get_q_maxval(RDC_Type *ptr); - -/** - * @brief Clear Q-phase maxval - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_clear_q_maxval(RDC_Type *ptr) -{ - ptr->MAX_Q = 0; -} - -/** - * @brief Get Q-phase Minval - * - * @param ptr @ref RDC_Type base - * @retval - other max value - * - -1 illegal data - */ -int32_t rdc_get_q_minval(RDC_Type *ptr); - -/** - * @brief Clear Q-phase Minval - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_clear_q_minval(RDC_Type *ptr) -{ - ptr->MIN_Q = 0; -} - -/** - * @brief The offset setting for edge detection of the i_channel or q_channel - * - * @param ptr @ref RDC_Type base - * @param chn @ref rdc_input_acc_chn_t - * @param offset offset value - */ -void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset); - -/** - * @brief RDC set accumulate configuration - * - * @param ptr @ref RDC_Type base - * @param cfg @ref rdc_acc_cfg_t - */ -void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg); - -/** - * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data - * - * @param ptr @ref RDC_Type base - * @retval clock cycle - */ -static inline uint32_t rdc_get_rise_delay_i(RDC_Type *ptr) -{ - return RDC_RISE_DELAY_I_RISE_DELAY_GET(ptr->RISE_DELAY_I); -} - -/** - * @brief Get delay in clock cycle between excitation synchrnous signal and fall edge of i_channel data - * - * @param ptr @ref RDC_Type base - * @retval clock cycle - */ -static inline uint32_t rdc_get_fall_delay_i(RDC_Type *ptr) -{ - return RDC_FALL_DELAY_I_FALL_DELAY_GET(ptr->FALL_DELAY_I); -} - -/** - * @brief Get sample value on rising edge of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval clock cycle - */ -static inline uint32_t rdc_get_sample_rise_i(RDC_Type *ptr) -{ - return RDC_SAMPLE_RISE_I_VALUE_GET(ptr->SAMPLE_RISE_I); -} - -/** - * @brief Get sample value on falling edge of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval clock cycle - */ -static inline uint32_t rdc_get_sample_fall_i(RDC_Type *ptr) -{ - return RDC_SAMPLE_FALL_I_VALUE_GET(ptr->SAMPLE_FALL_I); -} - -/** - * @brief Get sample number during the positive of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval counter - */ -static inline uint32_t rdc_get_acc_cnt_positive_i(RDC_Type *ptr) -{ - return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I); -} - -/** - * @brief Get sample number during the negtive of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval counter - */ -static inline uint32_t rdc_get_acc_cnt_negative_i(RDC_Type *ptr) -{ - return RDC_ACC_CNT_I_CNT_POS_GET(ptr->ACC_CNT_I); -} - -/** - * @brief Get Negative sample counter during positive rectify signal - * - * @param ptr @ref RDC_Type base - * @retval counter - */ -static inline uint32_t rdc_get_sign_cnt_poitive_i(RDC_Type *ptr) -{ - return RDC_SIGN_CNT_I_CNT_POS_GET(ptr->SIGN_CNT_I); -} - -/** - * @brief Get Positive sample counter during negative rectify signal - * - * @param ptr @ref RDC_Type base - * @retval counter - */ -static inline uint32_t rdc_get_sign_cnt_negative_i(RDC_Type *ptr) -{ - return RDC_SIGN_CNT_I_CNT_NEG_GET(ptr->SIGN_CNT_I); -} - -/** - * @brief Get delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data - * - * @param ptr @ref RDC_Type base - * @retval cycles - */ -static inline uint32_t rdc_get_rise_delay_q(RDC_Type *ptr) -{ - return RDC_RISE_DELAY_Q_RISE_DELAY_GET(ptr->RISE_DELAY_Q); -} - -/** - * @brief Get delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data - * - * @param ptr @ref RDC_Type base - * @retval cycles - */ -static inline uint32_t rdc_get_fall_delay_q(RDC_Type *ptr) -{ - return RDC_FALL_DELAY_Q_FALL_DELAY_GET(ptr->FALL_DELAY_Q); -} - -/** - * @brief Get q channel sample value on rising edge of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval cycles - */ -static inline uint32_t rdc_get_sample_rise_q(RDC_Type *ptr) -{ - return RDC_SAMPLE_RISE_Q_VALUE_GET(ptr->SAMPLE_RISE_Q); -} - -/** - * @brief Get q channel sample value on falling edge of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval cycles - */ -static inline uint32_t rdc_get_sample_fall_q(RDC_Type *ptr) -{ - return RDC_SAMPLE_FALL_Q_VALUE_GET(ptr->SAMPLE_FALL_Q); -} - -/** - * @brief Get q channel sample number during the positive of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval number - */ -static inline uint32_t rdc_get_acc_cnt_positive_q(RDC_Type *ptr) -{ - return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q); -} - -/** - * @brief Get q channel sample number during the negtive of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval number - */ -static inline uint32_t rdc_get_acc_cnt_negative_q(RDC_Type *ptr) -{ - return RDC_ACC_CNT_Q_CNT_POS_GET(ptr->ACC_CNT_Q); -} - -/** - * @brief Get q channel negative sample counter during positive rectify signal - * - * @param ptr @ref RDC_Type base - * @retval counter - */ -static inline uint32_t rdc_get_sign_cnt_poitive_q(RDC_Type *ptr) -{ - return RDC_SIGN_CNT_Q_CNT_POS_GET(ptr->SIGN_CNT_Q); -} - -/** - * @brief Get q channel sample number during the negtive of rectify signal - * - * @param ptr @ref RDC_Type base - * @retval counter - */ -static inline uint32_t rdc_get_sign_cnt_negative_q(RDC_Type *ptr) -{ - return RDC_SIGN_CNT_Q_CNT_NEG_GET(ptr->SIGN_CNT_Q); -} - -/** - * @brief Enables configured interrupts - * - * @param ptr @ref RDC_Type base - * @param status @ref rdc_interrupt_stat_t - */ -static inline void rdc_interrupt_config(RDC_Type *ptr, uint32_t status) -{ - ptr->INT_EN |= status; -} - -/** - * @brief Clear interrupts configured - * - * @param ptr @ref RDC_Type base - * @param status @ref rdc_interrupt_stat_t - */ -static inline void rdc_interrupt_reset_config(RDC_Type *ptr, uint32_t status) -{ - ptr->INT_EN &= ~status; -} - -/** - * @brief Enable rdc interrupt - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_interrupt_enable(RDC_Type *ptr) -{ - ptr->INT_EN |= RDC_INT_EN_INT_EN_MASK; -} - -/** - * @brief Disable rdc interrupt - * - * @param ptr @ref RDC_Type base - */ -static inline void rdc_interrupt_disable(RDC_Type *ptr) -{ - ptr->INT_EN &= ~RDC_INT_EN_INT_EN_MASK; -} - -/** - * @brief Clear interrupt flag bits - * - * @param ptr @ref RDC_Type base - * @param mask @ref rdc_interrupt_stat_t - */ -static inline void rdc_interrupt_clear_flag_bits(RDC_Type *ptr, uint32_t mask) -{ - ptr->ADC_INT_STATE &= mask; -} - -/** - * @brief Get the interrupt status object - * - * @param ptr @ref RDC_Type base - * @return @ref rdc_interrupt_stat_t - */ -static inline uint32_t get_interrupt_status(RDC_Type *ptr) -{ - return ptr->ADC_INT_STATE; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ -#endif /* HPM_ADC12_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h deleted file mode 100644 index e35f01c5034..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rng_drv.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_RNG_DRV_H -#define HPM_RNG_DRV_H -#include "hpm_common.h" -#include "hpm_rng_regs.h" - -enum { - status_rng_busy = MAKE_STATUS(status_group_rng, 1), - status_rng_selftest_failed = MAKE_STATUS(status_group_rng, 2), - status_rng_not_available = MAKE_STATUS(status_group_rng, 3), -}; - -#ifdef __cplusplus -extern "C" { -#endif - -hpm_stat_t rng_init(RNG_Type *ptr); - -hpm_stat_t rng_rand_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte); - -hpm_stat_t rng_rand_no_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte); - -hpm_stat_t rng_feed_rand_to_sdp(RNG_Type *ptr); - -hpm_stat_t rng_run_selftest(RNG_Type *ptr); - -static inline void rng_sw_reset(RNG_Type *ptr) -{ - ptr->CMD |= RNG_CMD_SFTRST_MASK; -} - -static inline void rng_clear_interrupt_error(RNG_Type *ptr) -{ - ptr->CMD |= RNG_CMD_CLRERR_MASK; -} - -static inline void rng_clear_interrupt(RNG_Type *ptr) -{ - ptr->CMD |= RNG_CMD_CLRINT_MASK; -} - -static inline bool rng_is_busy(RNG_Type *ptr) -{ - return ((ptr->STA & RNG_STA_BUSY_MASK) == RNG_STA_BUSY_MASK) ? true : false; -} - -static inline bool rng_need_reseed(RNG_Type *ptr) -{ - return ((ptr->STA & RNG_STA_RSDREQ_MASK) == RNG_STA_RSDREQ_MASK) ? true : false; -} - -#ifdef __cplusplus -} -#endif -#endif /* HPM_RNG_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h deleted file mode 100644 index f99c0283bda..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ROMAPI_XPI_DEF_H -#define HPM_ROMAPI_XPI_DEF_H - -/** - * @brief XPI ROM APIs - * @defgroup xpi_interface XPI driver APIs - * @{ - */ - -#include "hpm_common.h" - -/** - * @brief XPI_Type definitions for - * @note For compatibility - */ -typedef uint32_t XPI_Type; - -/** - * @brief XPI Read Sample Clock source options - */ -typedef enum { - xpi_rxclksrc_internal_loopback = 0, /**< Internal loopback */ - xpi_rxclksrc_dqs_loopback = 1, /**< Loopback from DQS pad */ - xpi_rxclksrc_external_dqs = 3, /**< Read is driven by External DQS pad */ -} xpi_rxclksrc_type_t; - - -/** - * @brief XPI pad definitions - */ -#define XPI_1PAD (0U) /**< Single pad */ -#define XPI_2PADS (1U) /**< Dual pads */ -#define XPI_4PADS (2U) /**< Quad pads */ -#define XPI_8PADS (3U) /**< Octal pads */ - -/** - * @brief XPI IO pin group options - */ -typedef enum { - xpi_io_1st_group, /**< First/Primary group */ - xpi_io_2nd_group, /**< Second/Secondary group */ -} xpi_io_group_t; - -/** - * @brief XPI Transfer Channel type definitions - */ -typedef enum { - xpi_xfer_channel_a1, /**< The address is based on the device connected to Channel A1 */ - xpi_xfer_channel_a2, /**< The address is based on the device connected to Channel A2 */ - xpi_xfer_channel_b1, /**< The address is based on the device connected to Channel B1 */ - xpi_xfer_channel_b2, /**< The address is based on the device connected to Channel B2 */ - xpi_xfer_channel_auto, /**< The channel is auto determined */ -} xpi_xfer_channel_t; - -/** - * @brief XPI Channel definitions - */ -typedef enum { - xpi_channel_a1, /**< Port: Channel A1 */ - xpi_channel_a2, /**< Port: Channel A2 */ - xpi_channel_b1, /**< Port: Channel B1 */ - xpi_channel_b2, /**< Port: Channel B2 */ -} xpi_channel_t; - -/** - * @brief XPI APB Transfer type - */ -typedef enum { - xpi_apb_xfer_type_cmd, /**< APB Command Type: Command only */ - xpi_apb_xfer_type_config, /**< APB Command Type: Configuration */ - xpi_apb_xfer_type_read, /**< APB Command Type: Read */ - xpi_apb_xfer_type_write, /**< APB Command Type: Write */ -} xpi_apb_xfer_type_t; - -/** - * @brief XPI Xfer Mode - */ -typedef enum { - xpi_xfer_mode_polling, /**< Transfer mode: Polling */ - xpi_xfer_mode_dma, /**< Transfer mode: DMA */ - xpi_xfer_mode_interrupt, /**< Transfer mode: Interrupt */ -} xpi_xfer_mode_t; - -/** - * @brief XPI Xfer context - */ -typedef struct { - uint32_t addr; /**< device address for XPI transfer */ - uint8_t channel; /**< channel for XPI transfer */ - uint8_t cmd_type; /**< command type for XPI transfer */ - uint8_t seq_idx; /**< Sequence index for XPI transfer */ - uint8_t seq_num; /**< Sequence number for XPI transfer */ - uint32_t *buf; /**< Buffer for XPI transfer */ - uint32_t xfer_size; /**< Transfer size in bytes */ -} xpi_xfer_ctx_t; - -/** - * @brief XPI instruction sequence - */ -typedef struct { - uint32_t entry[4]; -} xpi_instr_seq_t; - -/** - * @brief XPI Phase definitions - */ -#define XPI_PHASE_STOP (0x00U) /**< Phase: Stop */ -#define XPI_PHASE_CMD_SDR (0x01U) /**< Phase: Send CMD in SDR mode */ -#define XPI_PHASE_RADDR_SDR (0x02U) /**< Phase: Send Row Address in SDR Mode */ -#define XPI_PHASE_CADDR_SDR (0x03U) /**< Phase: Send Column Address in SDR Mode */ -#define XPI_PHASE_MODE4_SDR (0x06U) /**< Phase: Send Mode 4 in SDR Mode */ -#define XPI_PHASE_MODE8_SDR (0x07U) /**< Phase: Send Mode 8 in SDR Mode */ -#define XPI_PHASE_WRITE_SDR (0x08U) /**< Phase: Write data in SDR Mode */ -#define XPI_PHASE_READ_SDR (0x09U) /**< Phase: Read data in SDR Mode */ -#define XPI_PHASE_DUMMY_SDR (0X0CU) /**< Phase: Send Dummy in SDR Mode */ -#define XPI_PHASE_DUMMY_RWDS_SDR (0x0DU) /**< Phase: Send Dummy RWDS in SDR Mode */ - -#define XPI_PHASE_CMD_DDR (0x21U) /**< Phase: Send CMD in DDR Mode */ -#define XPI_PHASE_RADDR_DDR (0x22U) /**< Phase: Send Raw Address in DDR Mode */ -#define XPI_PHASE_CADDR_DDR (0x23U) /**< Phase: Send Column address in DDR Mode */ -#define XPI_PHASE_MODE4_DDR (0x26U) /**< Phase: Send Mode 4 in DDR Mode */ -#define XPI_PHASE_MODE8_DDR (0x27U) /**< Phase: Send Mode 8 in DDR Mode */ -#define XPI_PHASE_WRITE_DDR (0x28U) /**< Phase: Write data in DDR Mode */ -#define XPI_PHASE_READ_DDR (0x29U) /**< Phase: Read data in SDR Mode */ -#define XPI_PHASE_DUMMY_DDR (0x2CU) /**< Phase: Send DUMMY in DDR Mode */ -#define XPI_PHASE_DUMMY_RWDS_DDR (0x2DU) /**< Phase: Send DUMMY RWDS in DDR Mode */ - -/** - * @brief XPI API command error codes - */ -enum { - status_xpi_apb_jump_on_cs = MAKE_STATUS(status_group_xpi, 1), - status_xpi_apb_unknown_inst = MAKE_STATUS(status_group_xpi, 2), - status_xpi_apb_dummy_sdr_in_ddr_seq = MAKE_STATUS(status_group_xpi, 3), - status_xpi_apb_dummy_ddr_in_sdr_seq = MAKE_STATUS(status_group_xpi, 4), - status_xpi_apb_exceed_addr_range = MAKE_STATUS(status_group_xpi, 5), - status_xpi_apb_seq_timeout = MAKE_STATUS(status_group_xpi, 6), - status_xpi_apb_cross_boundary = MAKE_STATUS(status_group_xpi, 7), -}; - -/** - * @brief Delay line definitions - */ -enum { - xpi_dll_half_cycle = 0xFU, - xpi_dll_quarter_cycle = 0x7U, - xpi_dll_sdr_default_cycle = xpi_dll_half_cycle, - xpi_dll_ddr_default_cycle = xpi_dll_quarter_cycle, -}; - -/** - * @brief XPI configuration structure - */ -typedef struct { - uint8_t rxclk_src; /**< Read sample clock source */ - uint8_t reserved0[7]; /**< Reserved */ - uint8_t tx_watermark_in_dwords; /**< Tx watermark in double words */ - uint8_t rx_watermark_in_dwords; /**< Rx watermark in double words */ - uint8_t enable_differential_clk; /**< Enable differential clock */ - uint8_t reserved1[5]; /**< Reserved */ - uint32_t access_flags; /**< Access flags */ -} xpi_config_t; - -/** - * @brief XPI Device Configuration structure - */ -typedef struct { - uint32_t size_in_kbytes; /**< Device size in kbytes */ - uint32_t serial_root_clk_freq; /**< XPI serial root clock frequency */ - - uint8_t enable_write_mask; /**< Enable write mask, typically for PSRAM/HyperRAM */ - uint8_t data_valid_time; /**< Data valid time, Unit 0.1ns */ - uint8_t reserved0[2]; - - uint8_t cs_hold_time; /**< CS hold time, cycles in terms of FLASH clock */ - uint8_t cs_setup_time; /**< CS setup time, cycles in terms of FLASH clock */ - uint16_t cs_interval; /**< CS interval, cycles in terms of FLASH clock */ - - uint8_t reserved1; - uint8_t column_addr_size; /**< Column address bits */ - uint8_t enable_word_address; /**< Enable word address, for HyperFLASH/HyperRAM */ - uint8_t dly_target; /**< Delay target */ - - uint8_t ahb_write_seq_idx; /**< AHB write sequence index */ - uint8_t ahb_write_seq_num; /**< AHB write sequence number */ - uint8_t ahb_read_seq_idx; /**< AHB read sequence index */ - uint8_t ahb_read_seq_num; /**< AHB read sequence number */ - - uint8_t ahb_write_wait_interval; /**< AHB write wait interval, in terms of FLASH clock */ - uint8_t reserved2[3]; -} xpi_device_config_t; - -/** - * @brief SUB Instruction - * @param [in] phase Phase - * @param [in] pad Pad for Phase - * @param [in] op Operand for Phase - */ -#define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | ((uint16_t)(op)))) -/** - * @brief Generate a single word INSTRUCTION sequence word - * @note Here intentionally use the MACRO because when the arguments are constant value, the compiler - * can generate the const entry word during pre-processing - */ -#define XPI_INSTR_SEQ(phase0, pad0, op0, phase1, pad1, op1) (SUB_INSTR(phase0, pad0, op0) | (SUB_INSTR(phase1, pad1, op1)<<16)) - - -/** - * @} - */ - -#endif /* HPM_ROMAPI_XPI_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h deleted file mode 100644 index 3a2dcf55479..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ROMAPI_XPI_NOR_DEF_H -#define HPM_ROMAPI_XPI_NOR_DEF_H - -/** - * @brief XPI NOR ROM APIs - * @defgroup xpi_nor_interface XPI NOR driver APIs - * @ingroup romapi_interfaces - * @{ - */ - - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -#define XPI_NOR_CFG_TAG 0x524f4E58U /**< ASCII: "XNOR" */ - -/** - * @brief XPI NOR properties - */ -enum { - xpi_nor_property_total_size, /**< Total size in bytes */ - xpi_nor_property_page_size, /**< Page size in bytes */ - xpi_nor_property_sector_size, /** -#endif -#include - -/** - * @brief RTC alarm configuration - */ -typedef struct { - uint16_t index; /**< RTC alarm index */ - uint16_t type; /**< Alarm type */ - time_t period; /**< Alarm period */ -} rtc_alarm_config_t; - -/** - * @brief RTC Alarm type - */ -#define RTC_ALARM_TYPE_ONE_SHOT (0U) /**< The RTC alarm will be triggered only once */ -#define RTC_ALARM_TYPE_PERIODIC (1U) /**< The RTC alarm will be triggered periodically */ -#define RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT (2U) /**< The RTC alarm will be triggered via the absolute time provided via period */ - -/** - * @brief Typical RTC alarm period definitions - */ -#define ALARM_PERIOD_ONE_SEC (1UL) /**< Alarm period: 1 second */ -#define ALARM_PERIOD_ONE_MIN (60UL) /**< Alarm period: 1 minute */ -#define ALARM_PERIOD_ONE_HOUR (3600U) /**< Alarm period: 1 hour */ -#define ALARM_PERIOD_ONE_DAY (ALARM_PERIOD_ONE_HOUR * 24UL) /**< Alarm period: 1 day */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Configure the RTC time - * @param [in] base RTC base address - * @param [in] time seconds since 1970.1.1, 0:0:0 - * @retval API execution status status_success or status_invalid_argument - */ -hpm_stat_t rtc_config_time(RTC_Type *base, time_t time); - -/** - * @brief Configure RTC Alarm - * @param [in] base RTC base address - * @param [in] config RTC alarm configuration pointer - * @retval API execution status status_success or status_invalid_argument; - */ -hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config); - -/** - * @brief Get the time returned by RTC module - * @param [in] base RTC base address - * @retval RTC time - */ -time_t rtc_get_time(RTC_Type *base); - - -/** - * @brief Get accurate time return by RTC module - * @param [in] base RTC base address - * - * @return accurate time(including second and subsecond) - */ -struct timeval rtc_get_timeval(RTC_Type *base); - -/** - * @brief Enable RTC alarm interrupt - * @param [in] base RTC base address - * @param [in] index RTC alarm index, valid value is 0 or 1 - * @param [in] enable RTC alarm enable flag - * @arg true Enable specified RTC alarm - * @arg false Disable specified RTC alarm - */ -static inline void rtc_enable_alarm_interrupt(RTC_Type *base, uint32_t index, bool enable) -{ - if (index > 1) { - return; - } - - uint32_t mask = (index == 0U) ? RTC_ALARM_EN_ENABLE0_MASK : RTC_ALARM_EN_ENABLE1_MASK; - - if (enable) { - base->ALARM_EN |= mask; - } else { - base->ALARM_EN &= ~mask; - } -} - -/** - * @brief Clear RTC alarm flag based on alarm index - * @param [in] base RTC base address - * @param [in] index RTC alarm index, valid value is 0 or 1 - */ -static inline void rtc_clear_alarm_flag(RTC_Type *base, uint32_t index) -{ - if (index > 1) { - return; - } - uint32_t mask = (index == 0U) ? RTC_ALARM_FLAG_ALARM0_MASK : RTC_ALARM_FLAG_ALARM1_MASK; - - base->ALARM_FLAG = mask; -} - -/** - * @brief Clear RTC alarm flags based on flag masks - * @param [in] base RTC base address - * @param [in] masks RTC alarm masks - */ -static inline void rtc_clear_alarm_flags(RTC_Type *base, uint32_t masks) -{ - base->ALARM_FLAG = masks; -} - -/** - * @brief Check whether RTC alarm flag is set or not - * @param [in] base RTC base address - * @param [in] index RTC alarm index, valid value is 0 or 1 - * @retval RTC alarm flag. Valid value is true or false - */ -static inline bool rtc_is_alarm_flag_asserted(RTC_Type *base, uint32_t index) -{ - if (index > 1) { - return false; - } - uint32_t mask = (index == 0U) ? RTC_ALARM_FLAG_ALARM0_MASK : RTC_ALARM_FLAG_ALARM1_MASK; - - return IS_HPM_BITMASK_SET(base->ALARM_FLAG, mask); -} - -/** - * @brief Get the RTC alarm flags - * @param [in] base RTC base address - * @return RTC alarm flags - */ -static inline uint32_t rtc_get_alarm_flags(RTC_Type *base) -{ - return base->ALARM_FLAG; -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - * - */ - -#endif /* HPM_RTC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h deleted file mode 100644 index 3c5f54b9254..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdm_drv.h +++ /dev/null @@ -1,475 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDM_DRV_H -#define HPM_SDM_DRV_H - -#include "hpm_common.h" -#include "hpm_sdm_regs.h" - -/** - * @brief SDM APIs - * @defgroup sdm_interface SDM driver APIs - * @ingroup sdm_interfaces - * @{ - */ - -/* defined channel mask macro */ -#define SAMPLING_MODE_MASK (0x7U) -#define CHN_SAMPLING_MODE_SHIFT(ch) ((ch) * 3U + SDM_CTRL_CHMD_SHIFT) -#define CHN_SAMPLING_MODE_MASK(ch) (SAMPLING_MODE_MASK << CHN_SAMPLING_MODE_SHIFT(ch)) - -#define CH0_EN_MASK (0x1U << SDM_CTRL_CH_EN_SHIFT) -#define CHN_EN_MASK(ch) (CH0_EN_MASK << (ch)) - -#define CHN_ERR_MASK(ch) (SDM_INT_EN_CH0ERR_MASK << (ch)) -#define CHN_DRY_MASK(ch) (SDM_INT_EN_CH0DRY_MASK << (ch)) - -typedef enum { - sdm_sampling_rising_clk_edge = 0, - sdm_sampling_every_clk_edge = 1, - sdm_sampling_manchester_mode = 2, - sdm_sampling_falling_clk_edge = 3, - sdm_sampling_rising_two_clk_edge = 4, - sdm_sampling_falling_two_clk_edge = 5 -} sdm_sampling_mode_t; - -typedef enum { - sdm_filter_sinc1 = 0, - sdm_filter_sinc2 = 1, - sdm_filter_sinc3 = 2, - sdm_filter_fast_sinc2 = 3 -} sdm_filter_type_t; - -typedef struct { - uint8_t clk_signal_sync; /* clk sync for channel */ - uint8_t data_signal_sync; /* data sync for channel */ - bool interrupt_en; -} sdm_control_t; - -typedef struct { - uint8_t sampling_mode; - bool enable_err_interrupt; - bool enable_data_ready_interrupt; -} sdm_channel_common_config_t; - -typedef struct { - uint16_t high_threshold; - uint16_t zero_cross_threshold; - uint16_t low_threshold; - - bool en_zero_cross_threshold_int; - bool en_clock_invalid_int; - bool en_high_threshold_int; - bool en_low_threshold_int; - uint8_t filter_type; /**< sdm_filter_type_t */ - uint8_t oversampling_rate; /**< 1 - 32 */ - uint8_t ignore_invalid_samples; - bool enable; -} sdm_comparator_config_t; - -typedef struct { - uint8_t fifo_threshold; - bool en_fifo_threshold_int; - uint8_t manchester_threshold :8; - uint8_t wdg_threshold :8; - uint8_t en_af_int :1; - uint8_t en_data_overflow_int :1; - uint8_t en_cic_data_saturation_int :1; - uint8_t en_data_ready_int :1; - uint8_t sync_source :6; - uint8_t fifo_clean_on_sync :1; /**< fifo clean by hardware when fifo interrupt occurred */ - uint8_t wtsynaclr :1; - uint8_t wtsynmclr :1; - uint8_t wtsyncen :1; - uint8_t output_32bit :1; - uint8_t data_ready_flag_by_fifo :1; - uint8_t enable :1; - - uint8_t filter_type; /**< sdm_filter_type_t */ - bool pwm_signal_sync; - uint8_t output_offset; /**< 16bit mode need configure this */ - uint16_t oversampling_rate; /**< 1-256 */ - uint8_t ignore_invalid_samples; -} sdm_filter_config_t; - -typedef struct { - uint32_t count; - uint8_t *buff; - uint8_t data_len_in_bytes; /* 16bit-2 32bit-4 */ - bool using_fifo; -} sdm_output_config_t; - -typedef enum { - sdm_comparator_no_event = 0, - sdm_comparator_event_out_high_threshold = SDM_CH_SCST_CMPH_MASK, - sdm_comparator_event_out_low_threshold = SDM_CH_SCST_CMPL_MASK, - sdm_comparator_event_hz = SDM_CH_SCST_HZ_MASK, - sdm_comparator_event_invalid_clk = SDM_CH_SCST_MF_MASK -} sdm_comparator_event_t; - -typedef enum { - sdm_chn0_error_mask = SDM_INT_EN_CH0ERR_MASK, - sdm_chn1_error_mask = SDM_INT_EN_CH1ERR_MASK, - sdm_chn2_error_mask = SDM_INT_EN_CH2ERR_MASK, - sdm_chn3_error_mask = SDM_INT_EN_CH3ERR_MASK, - sdm_chn0_data_ready_mask = SDM_INT_EN_CH0DRY_MASK, - sdm_chn1_data_ready_mask = SDM_INT_EN_CH1DRY_MASK, - sdm_chn2_data_ready_mask = SDM_INT_EN_CH2DRY_MASK, - sdm_chn3_data_ready_mask = SDM_INT_EN_CH3DRY_MASK -} sdm_channel_int_status_mask_t; - -typedef enum { - sdm_chn0_enable_mask = 1U << SDM_CTRL_CH_EN_SHIFT, - sdm_chn1_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 1U), - sdm_chn2_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 2U), - sdm_chn3_enable_mask = 1U << (SDM_CTRL_CH_EN_SHIFT + 3U) -} sdm_channel_enable_mask_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief sdm enable module interrupt - * - * @param ptr SDM base address - * @param enable true for enable, false for disable - */ -static inline void sdm_enable_module_interrupt(SDM_Type *ptr, bool enable) -{ - if (enable) { - ptr->CTRL |= SDM_CTRL_IE_MASK; - } else { - ptr->CTRL &= ~SDM_CTRL_IE_MASK; - } -} - -/** - * @brief sdm enable channel - * - * @param ptr SDM base address - * @param ch_index channel index - * @param enable true for enable, false for disable - */ -static inline void sdm_enable_channel(SDM_Type *ptr, uint8_t ch_index, bool enable) -{ - if (enable) { - ptr->CTRL |= CHN_EN_MASK(ch_index); - } else { - ptr->CTRL &= ~CHN_EN_MASK(ch_index); - } -} - -/** - * @brief sdm enable channel by mask - * - * @note ch_mask supports bitwise or operation, this API could enable multiple channels at the same time - * - * @param ptr SDM base address - * @param ch_mask sdm_channel_enable_mask_t - */ -static inline void sdm_enable_channel_by_mask(SDM_Type *ptr, uint32_t ch_mask) -{ - ptr->CTRL = (ptr->CTRL & (~SDM_CTRL_CH_EN_MASK)) | ch_mask; -} - -/** - * @brief sdm set channel sampling mode - * - * @param ptr SDM base address - * @param ch_index channel index - * @param mode sdm_sampling_mode_t - */ -static inline void sdm_set_channel_sampling_mode(SDM_Type *ptr, uint8_t ch_index, sdm_sampling_mode_t mode) -{ - ptr->CTRL &= ~CHN_SAMPLING_MODE_MASK(ch_index); - ptr->CTRL |= mode << (SDM_CTRL_CHMD_SHIFT + ch_index); -} - -/** - * @brief sdm enable channel interrupt - * - * @param ptr SDM base address - * @param mask sdm_channel_int_status_mask_t, support bitwise or operation - */ -static inline void sdm_enable_channel_interrupt(SDM_Type *ptr, uint32_t mask) -{ - ptr->INT_EN |= mask; -} - -/** - * @brief sdm get status register value - * - * @param ptr SDM base address - * @return uint32_t sdm status register value - */ -static inline uint32_t sdm_get_status(SDM_Type *ptr) -{ - return ptr->STATUS; -} - -/** - * @brief get channel data ready status - * - * @param ptr SDM base address - * @param ch channel - * @return true data ready - * @return false not ready - */ -static inline bool sdm_get_channel_data_ready_status(SDM_Type *ptr, uint8_t ch) -{ - return (((ptr->STATUS) & CHN_DRY_MASK(ch)) == CHN_DRY_MASK(ch)); -} - -/** - * @brief get channel error status - * - * @param ptr SDM base address - * @param ch channel - * @return true error occur - * @return false no error - */ -static inline bool sdm_get_channel_data_error_status(SDM_Type *ptr, uint8_t ch) -{ - return (((ptr->STATUS) & CHN_ERR_MASK(ch)) == CHN_ERR_MASK(ch)); -} - -/** - * @brief sdm set channel's fifo threshold - * - * @param ptr SDM base address - * @param ch channel index - * @param threshold threshold value - */ -static inline void sdm_set_ch_fifo_threshold(SDM_Type *ptr, uint8_t ch, uint8_t threshold) -{ - ptr->CH[ch].SDFIFOCTRL = SDM_CH_SDFIFOCTRL_THRSH_SET(threshold); -} - -/** - * @brief sdm get channel fifo threshold - * - * @param ptr SDM base address - * @param ch channel index - * @return uint8_t fifo threshold value - */ -static inline uint8_t sdm_get_ch_fifo_threshold(SDM_Type *ptr, uint8_t ch) -{ - return (uint8_t)(SDM_CH_SDFIFOCTRL_THRSH_GET(ptr->CH[ch].SDFIFOCTRL)); -} - -/** - * @brief sdm get channel filter status - * - * @param ptr SDM base address - * @param ch channel index - * @return uint32_t channel filter status register value - */ -static inline uint32_t sdm_get_channel_filter_status(SDM_Type *ptr, uint8_t ch) -{ - return ptr->CH[ch].SDST; -} - -/** - * @brief sdm get channel data count in fifo - * - * @param ptr SDM base address - * @param ch channel index - * @return uint8_t data count - */ -static inline uint8_t sdm_get_channel_fifo_data_count(SDM_Type *ptr, uint8_t ch) -{ - return (uint8_t)(SDM_CH_SDST_FILL_GET(ptr->CH[ch].SDST)); -} - -/** - * @brief sdm get channel filter output data in fifo - * - * @param ptr SDM base address - * @param ch channel index - * @return int32_t data - */ -static inline int32_t sdm_get_channel_fifo_data(SDM_Type *ptr, uint8_t ch) -{ - return ptr->CH[ch].SDFIFO; -} - -/** - * @brief sdm get channel input clock cycle count - * - * @param ptr SDM base address - * @param ch channel index - * @return uint8_t clock cycle count - */ -static inline uint8_t sdm_get_channel_clock_cycle_count(SDM_Type *ptr, uint8_t ch) -{ - return (uint8_t)(SDM_CH_SDST_PERIOD_MCLK_GET(ptr->CH[ch].SDST)); -} - -/** - * @brief sdm get channel comparator data - * - * @param ptr SDM base address - * @param ch channel index - * @return uint16_t comparator data - */ -static inline uint16_t sdm_get_channel_comparator_data(SDM_Type *ptr, uint8_t ch) -{ - return (uint16_t)(ptr->CH[ch].SCAMP); -} - -/** - * @brief sdm set channel comparator high threshold - * - * @param ptr SDM base address - * @param ch channel index - * @param value high threshold value - */ -static inline void sdm_set_channel_comparator_high_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) -{ - ptr->CH[ch].SCHTL = value; -} - -/** - * @brief sdm set channel comparator zero crossing threshold - * - * @param ptr SDM base address - * @param ch channel index - * @param value zero crossing threshold value - */ -static inline void sdm_set_channel_comparator_zero_crossing_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) -{ - ptr->CH[ch].SCHTLZ = value; -} - -/** - * @brief sdm set channel comparator low threshold - * - * @param ptr SDM base address - * @param ch channel index - * @param value low threshold value - */ -static inline void sdm_set_channel_comparator_low_threshold(SDM_Type *ptr, uint8_t ch, uint16_t value) -{ - ptr->CH[ch].SCLLT = value; -} - -/** - * @brief sdm get channel comparator status register value - * - * @param ptr SDM base address - * @param ch channel index - * @return uint32_t channel comparator status register value - */ -static inline uint32_t sdm_get_channel_comparator_status(SDM_Type *ptr, uint8_t ch) -{ - return ptr->CH[ch].SCST; -} - -/** - * @brief sdm get default module control - * - * @param ptr SDM base address - * @param control sdm_control_t - */ -void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control); - -/** - * @brief sdm init module - * - * @param ptr SDM base address - * @param control sdm_control_t - */ -void sdm_init_module(SDM_Type *ptr, sdm_control_t *control); - -/** - * @brief sdm get channel common setting - * - * @param ptr SDM base address - * @param config sdm_channel_common_config_t - */ -void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config); - -/** - * @brief sdm config channel's common setting - * - * @param ptr SDM base address - * @param ch_index channel index - * @param config sdm_channel_common_config_t - */ -void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_channel_common_config_t *config); - -/** - * @brief sdm get channel default filter config - * - * @param ptr SDM base address - * @param filter_config sdm_filter_config_t - */ -void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config); - -/** - * @brief sdm config channel filter - * - * @param ptr SDM base address - * @param ch_index channel index - * @param filter_config sdm_filter_config_t - */ -void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_config_t *filter_config); - -/** - * @brief sdm get channel default comparator config - * - * @param ptr SDM base address - * @param cmp_config sdm_comparator_config_t - */ -void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config); - -/** - * @brief sdm config channel comparator - * - * @param ptr SDM base address - * @param ch_index channel index - * @param cmp_config sdm_comparator_config_t - */ -void sdm_config_channel_comparator(SDM_Type *ptr, uint8_t ch_index, sdm_comparator_config_t *cmp_config); - -/** - * @brief sdm receive one filter data - * - * @param ptr SDM base address - * @param ch_index channel index - * @param using_fifo true for getting data from fifo, false for getting data from register - * @param data data buff - * @param data_len_in_bytes output data len in bytes - * @retval hpm_stat_t status_success only if it succeeds - */ -hpm_stat_t sdm_receive_one_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint8_t data_len_in_bytes); - -/** - * @brief sdm receive filter data - * - * @param ptr SDM base address - * @param ch_index channel index - * @param using_fifo true for getting data from fifo, false for getting data from register - * @param data data buff - * @param count data count - * @param data_len_in_bytes output data len in bytes - * @retval hpm_stat_t status_success only if it succeeds - */ -hpm_stat_t sdm_receive_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint32_t count, uint8_t data_len_in_bytes); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_SDM_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h deleted file mode 100644 index cdc442dd1dc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h +++ /dev/null @@ -1,690 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDP_DRV_H -#define HPM_SDP_DRV_H - -/** - * @brief SDP driver APIs - * @defgroup sdp_interface SDP driver APIs - * @ingroup sdp_interfaces - * @{ - * - */ - -#include "hpm_common.h" -#include "hpm_sdp_regs.h" -#include "hpm_soc_feature.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief SDP AES key bit options - */ -typedef enum { - sdp_aes_keybits_128 = 0, /**< 128 bit AES key */ - sdp_aes_keybits_256 = 1, /**< 256 bit AES key */ -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - sdp_sm4_keybits_128 = sdp_aes_keybits_128, /* SM4 Key bits */ -#endif -} sdp_crypto_key_bits_t; - -typedef sdp_crypto_key_bits_t sdp_aes_key_bits_t; - -typedef sdp_crypto_key_bits_t sdp_sm4_key_bits_t; - -/** - * @brief Crypto operation option - */ -typedef enum { - sdp_aes_op_encrypt, /**< AES Encrypt operation */ - sdp_aes_op_decrypt, /**< AES Decrypt operation */ -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - sdp_sm4_op_encrypt = sdp_aes_op_encrypt, /**< SM4 Encrypt operation */ - sdp_sm4_op_decrypt = sdp_aes_op_decrypt, /**< SM4 Decrypt operation */ -#endif -} sdp_crypto_op_t; - -typedef sdp_crypto_op_t sdp_aes_op_t; - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - -typedef sdp_crypto_op_t sdp_sm4_op_t; - -#endif - -/** - * @brief SDP Crypto algorithms - * - */ -typedef enum { - sdp_crypto_alg_aes = 0, /**< AES */ -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - sdp_crypto_alg_sm4 = 1, /**< SM4 */ -#endif -} sdp_crypto_alg_t; - -/** - * @brief SDP Crypto modes - */ -typedef enum { - sdp_crypto_mode_ecb = 0, /*!< ECB mode */ - sdp_crypto_mode_cbc = 1, /*!< CBC mode */ -} sdp_crypto_mode_t; - -/** - * @brief SDP Data Swap modes - */ -typedef enum { - sdp_swap_mode_none = 0, /*!< No data swap */ - sdp_swap_mode_bytes_in_word = 1, /*!< Swap bytes within one word */ - sdp_swap_mode_word_swap = 2, /*!< Swap words in one crypto block (16-bytes) */ - sdp_swap_mode_switch_endian = 3, /*!< Swap the data-endian in one crypto block (16-bytes) */ -} sdp_data_swap_mode_t; - -/** - * @brief SDP HASH calculation mode - */ -typedef enum { - sdp_calc_hash_for_input = 0, /*!< Calculate HASH before doing crypto operation */ - sdp_calc_hash_for_output = 1, /*!< Calculate HASH after doing crypto operation */ -} sdp_calc_hash_mode_t; - - -/** - * @brief SDP HASH algorithm definitions - */ -typedef enum { - sdp_hash_alg_sha1 = 0, /**< SDP SHA1 */ - sdp_hash_alg_crc32 = 1, /**< SDP CRC32 */ - sdp_hash_alg_sha256 = 2, /**< SDP SHA256 */ -#if defined(SDP_HAS_SM3_SUPPORT) && (SDP_HAS_SM3_SUPPORT == 1) - sdp_hash_alg_sm3 = 8, /**< SDP SM3 */ - sdp_hash_alg_max = sdp_hash_alg_sm3, -#else - sdp_hash_alg_max = sdp_hash_alg_sha256, -#endif -} sdp_hash_alg_t; - -#define HASH_BLOCK_SIZE (64U) /**< Hash block size in bytes */ -#define AES_BLOCK_SIZE (16U) /**< AES block size in bytes */ -#define AES_128_KEY_SIZE (0x10U) /**< AES 128-bit key size in bytes */ -#define AES_256_KEY_SIZE (0x20U) /**< AES 256-bit key size in bytes */ - -#define SM4_BLOCK_SIZE (AES_BLOCK_SIZE) /**< SM4 block size in bytes */ -#define SM4_KEY_SIZE (AES_128_KEY_SIZE) /**< SM4 Key size in bytes */ - -/** - * @brief Bitfield definitions for the PKT_CTRL - */ -#define SDP_PKT_CTRL_DERSEMA_MASK (1U << 2) -#define SDP_PKT_CTRL_CHAIN_MASK (1U << 3) -#define SDP_PKT_CTRL_HASHINIT_MASK (1U << 4) -#define SDP_PKT_CTRL_HASHFINISH_MASK (1U << 5) -#define SDP_PKT_CTRL_CIPHIV_MASK (1U << 6) - -/** - * @brief SDP Command Packet structure - */ -typedef struct _sdp_packet_struct { - struct _sdp_packet_struct *next_cmd; - union { - struct { - uint32_t RESERVED0: 1; - uint32_t PKTINT: 1; /**< Packet interrupt flag */ - uint32_t DCRSEMA: 1; /**< Decrement Semaphore flag */ - uint32_t CHAIN: 1; /**< Chain Packet flag */ - uint32_t HASHINIT: 1; /**< Hash initialize flag */ - uint32_t HASHFINISH: 1; /**< Hash finish flag */ - uint32_t CIPHIV: 1; /**< Cipher IV flag */ - uint32_t RESERVED1: 17; - uint32_t PKTTAG: 8; /**< Packet tag flag, not used */ - }; - uint32_t PKT_CTRL; /**< Packet control word */ - } pkt_ctrl; - uint32_t src_addr; /**< Source address */ - uint32_t dst_addr; /**< Destination address */ - uint32_t buf_size; /**< Data buffer size in bytes */ - uint32_t reserved[3]; -} sdp_pkt_struct_t; - -/** - * @brief SDP AES context structure - */ -typedef struct { - uint8_t key_idx; /**< AES key index */ - uint8_t key_bits; /**< AES key bits */ - uint16_t crypto_algo; - sdp_pkt_struct_t sdp_pkt; /**< SDP packet for AES operation */ - uint32_t buf0[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf0 */ - uint32_t buf1[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf1 */ - uint32_t buf2[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf2 */ - uint32_t buf3[AES_BLOCK_SIZE / sizeof(uint32_t)]; /**< buf3 */ -} sdp_crypto_ctx_t; - -typedef sdp_crypto_ctx_t sdp_aes_ctx_t; - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) -typedef sdp_crypto_ctx_t sdp_sm4_ctx_t; -#endif - -/** - * @brief SDP DMA context - */ -typedef struct { - sdp_pkt_struct_t sdp_pkt; /**< SDP packet for DMA operation (memset/memcpy) */ -} sdp_dma_ctx_t; - -/** - * @brief SDP HASH context - */ -typedef struct { - sdp_pkt_struct_t sdp_pkt; /**< SDP packet for HASH operation */ - uint32_t internal[64]; /**< internal buffer */ -} sdp_hash_ctx_t; - -/** - * @brief SDP error status definitions - */ -enum { - status_sdp_no_crypto_support = MAKE_STATUS(status_group_sdp, 0), /**< The crypto algorithm is not supported */ - status_sdp_no_hash_support = MAKE_STATUS(status_group_sdp, 1), /**< The hash algorithm is not supported */ - status_sdp_invalid_key_src = MAKE_STATUS(status_group_sdp, 2), /**< Invalid AES key source */ - status_sdp_error_packet = MAKE_STATUS(status_group_sdp, 3), /**< Error packet */ - status_sdp_aes_busy = MAKE_STATUS(status_group_sdp, 4), /**< AES engine is busy */ - status_sdp_hash_busy = MAKE_STATUS(status_group_sdp, 5), /**< HASH engine is busy */ - status_sdp_error_setup = MAKE_STATUS(status_group_sdp, 6), /**< Error setup in SDP IP */ - status_sdp_error_src = MAKE_STATUS(status_group_sdp, 7), /**< Error source address */ - status_sdp_error_dst = MAKE_STATUS(status_group_sdp, 8), /**< Error destination address */ - status_sdp_error_hash = MAKE_STATUS(status_group_sdp, 9), /**< Error Hash digest */ - status_sdp_error_chain = MAKE_STATUS(status_group_sdp, 10), /**< Error packet chain */ - status_sdp_error_invalid_mac = MAKE_STATUS(status_group_sdp, 11),/**< Invalid Message Authentication Code (MAC) */ - status_sdp_invalid_alg = MAKE_STATUS(status_group_sdp, 12), /**< Invalid algorithm */ - -}; - -/** - * @brief SDP Operations - */ -typedef enum { - sdp_op_invalid = 0, - sdp_op_cipher_only = SDP_SDPCR_CIPHEN_MASK, - sdp_op_hash_only = SDP_SDPCR_HASHEN_MASK, - sdp_op_memcpy_only = SDP_SDPCR_MCPEN_MASK, - sdp_op_memfill_only = SDP_SDPCR_CONFEN_MASK, - sdp_op_cipher_hash = SDP_SDPCR_CIPHEN_MASK | SDP_SDPCR_HASHEN_MASK, - sdp_op_copy_hash = SDP_SDPCR_MCPEN_MASK | SDP_SDPCR_HASHEN_MASK, -} sdp_operation_t; - -/** - * @brief SDP Action Structure - */ -typedef struct { - sdp_operation_t op; /*!< SDP operation */ - sdp_data_swap_mode_t input_swap_mode; /*!< SDP input data swap mode */ - sdp_data_swap_mode_t output_swap_mode; /*!< SDP output data swap mode */ - struct { - sdp_hash_alg_t hash_alg; /*!< SDP HASH algorithm */ - bool hash_check; /*!< Enable HASH verify mode */ - }; - struct { - sdp_crypto_alg_t crypto_alg; /*!< SDP Crypto Algorithm */ - sdp_crypto_mode_t crypto_mode; /*!< SDP Crypto mode */ - uint16_t key_bits; /*!< SDP crypto key bits */ - uint8_t key_index; /*!< SDP key index */ - sdp_crypto_op_t crypto_op; /*!< SDP Crypto operation mode */ - sdp_data_swap_mode_t key_swap_mode; /*!< SDP Key swap mode */ - sdp_calc_hash_mode_t hash_mode; /*!< SDP Hash calculation mode */ - }; -} sdp_action_t; - - -#ifdef __cplusplus -extern "C" -{ -#endif - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -/** - * @brief Enable SDP interrupt - * @param [in] base SDP base address - */ -static inline void sdp_enable_interrupt(SDP_Type *base) -{ - base->SDPCR |= SDP_SDPCR_INTEN_MASK; -} - -/** - * @brief Disable SDP interrupt - * @param [in] base SDP base address - */ -static inline void sdp_disable_interrupt(SDP_Type *base) -{ - base->SDPCR &= ~SDP_SDPCR_INTEN_MASK; -} - -/** - * @brief Set the Crypto Key Index in SDP - * @param [in] base SDP base address - * @param [in] key_index SDP key index - */ -static inline void sdp_set_key_index(SDP_Type *base, uint32_t key_index) -{ - base->KEYADDR = SDP_KEYADDR_INDEX_SET(key_index); -} - -/** - * @brief Write SDP key to specified SDP Key RAM - * @param [in] base SDP base address - * @param [in] key_index Key Index - * @param [in] key_bits Key bits, valid value: 128, 256 - * @param [in] crypto_key Crypto Key buffer - */ -static inline void sdp_write_key(SDP_Type *base, uint32_t key_index, uint32_t key_bits, const uint32_t *crypto_key) -{ - if (key_bits == 256) { - uint32_t actual_key_index = key_index * 2; - for (uint32_t i = 0; i < 2; i++) { - sdp_set_key_index(base, actual_key_index++); - for (uint32_t j = 0; j < 4; j++) { - base->KEYDAT = *crypto_key++; - } - } - } else { - sdp_set_key_index(base, key_index); - for (uint32_t j = 0; j < 4; j++) { - base->KEYDAT = *crypto_key++; - } - } -} - -/** - * @brief Write the HASH digest result to SDP - * @param [in] base SDP base address - * @param [in] digest HASH digest - * @param [in] num_words Digest size in words - */ -static inline void sdp_write_hash_digest(SDP_Type *base, const uint32_t *digest, uint32_t num_words) -{ - for (uint32_t i = 0; i < num_words; i++) { - base->HASWRD[i] = *digest++; - } -} - -/** - * @brief Read the HASH digest result from SDP - * @param [in] base SDP base address - * @param [out] digest HASH digest - * @param [in] num_words Digest size in words - */ -static inline void sdp_get_hash_digest(SDP_Type *base, uint32_t *digest, uint32_t num_words) -{ - for (uint32_t i = 0; i < num_words; i++) { - *digest++ = base->HASWRD[i]; - } -} - -/** - * @brief Write the cipher IV to SDP - * @param [in] base SDP base address - * @param [in] iv Initial vector - */ -static inline void sdp_write_cipher_iv(SDP_Type *base, const uint32_t *iv) -{ - for (uint32_t i = 0; i < 4; i++) { - base->CIPHIV[i] = *iv++; - } -} - -/** - * @brief Clear SDP status - * @param [in] base SDP base address - * @param [in] mask Status Mask - */ -static inline void sdp_clear_status(SDP_Type *base, uint32_t mask) -{ - base->STA = mask; -} - -/** - * @brief Get SDP status - * @param [in] base SDP base address - * - * @return SDP status - */ -static inline uint32_t sdp_get_status(SDP_Type *base) -{ - return base->STA; -} - -/** - * @brief Initialize the SDP controller - * @param [in] base SDP base address - * @return API execution status. - */ -hpm_stat_t sdp_init(SDP_Type *base); - -/** - * @brief De-initialize the SDP controller - * @param [in] base SDP base address - * @return API execution status. - */ -hpm_stat_t sdp_deinit(SDP_Type *base); - -/** - * @brief Set the AES key for the SDP AES operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] key AES key - * @param [in] key_bits AES key-bit option - * @param [in] key_idx AES key index - * @return API execution status. - */ -hpm_stat_t sdp_aes_set_key(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx); - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - -/** - * @brief Set the SM4 key for the SDP SM4 operation - * @param [in] base SDP base address - * @param [in] sm4_ctx AES operation context - * @param [in] key SM4 key - * @param [in] key_bits SM4 key-bit option - * @param [in] key_idx AES key index - * @return API execution status. - */ -hpm_stat_t sdp_sm4_set_key(SDP_Type *base, - sdp_sm4_ctx_t *sm4_ctx, - const uint8_t *key, - sdp_sm4_key_bits_t key_bits, - uint32_t key_idx); - -#endif - -/** - * @brief Perform the basic AES ECB operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] op AES operation option - * @param [in] len AES data length in bytes - * @param [in] in Input buffer - * @param [out] out Output buffer - * @return API execution status. - */ -hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out); - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) -/** - * @brief Perform the basic SM4 ECB operation - * @param [in] base SDP base address - * @param [in] sm4_ctx SM4 operation context - * @param [in] op SM4 operation option - * @param [in] len SM4 data length in bytes - * @param [in] in Input buffer - * @param [out] out Output buffer - * @return API execution status. - */ -#define sdp_sm4_crypt_ecb sdp_aes_crypt_ecb -#endif - -/** - * @brief Perform the AES CBC operation - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] op AES operation option - * @param [in] length AES data length in bytes - * @param [in] iv Initial vector/nonce - * @param [in] input Input buffer - * @param [out] output Output buffer - * @return API execution status. - */ -hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - const uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) -/** - * @brief Perform the SM4 CBC operation - * @param [in] base SM4 base address - * @param [in] sm4_ctx SM4 operation context - * @param [in] op SM4 operation option - * @param [in] length SM4 data length in bytes - * @param [in] iv Initial vector/nonce - * @param [in] input Input buffer - * @param [out] output Output buffer - * @return API execution status. - */ -#define sdp_sm4_crypt_cbc sdp_aes_crypt_cbc -#endif - -/** - * @brief Perform the AES-CTR operation - * See NIST Special Publication800-38A for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] nonce_counter AES-CTR nonce/counter - * @param [in] input Input buffer - * @param [out] output Output buffer - * @param [in] length Length of data for AES-CTR operation - * @return API execution status. - */ -hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - uint8_t *nonce_counter, - uint8_t *input, - uint8_t *output, - uint32_t length); - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) -/** - * @brief Perform the SM4-CTR operation - * @param [in] base SDP base address - * @param [in] sm4_ctx SM4 operation context - * @param [in] nonce_counter SM4-CTR nonce/counter - * @param [in] input Input buffer - * @param [out] output Output buffer - * @param [in] length Length of data for SM4-CTR operation - * @return API execution status. - */ -#define sdp_sm4_crypt_ctr sdp_aes_crypt_ctr -#endif - -/** - * @brief Perform the AES-CCM generate and encrypt - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [out] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @return API execution status. - */ -hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *iv, - uint32_t iv_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) -/** - * @brief Perform the SM4-CCM generate and encrypt - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] sm4_ctx SM4 operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [out] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @return API execution status. - */ -#define sdp_sm4_ccm_generate_encrypt sdp_aes_ccm_generate_encrypt -#endif - -/** - * @brief Perform the AES-CCM decrypt and verify - * See NIST Special Publication 800-38C for more details - * @param [in] base SDP base address - * @param [in] aes_ctx AES operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [in] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @return API execution status. - */ -hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *iv, - uint32_t iv_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) -/** - * @brief Perform the SM4-CCM decrypt and verify - * @param [in] base SDP base address - * @param [in] sm4_ctx SM4 operation context - * @param [in] input_len Input data length in bytes - * @param [in] iv Initial vector - * @param [in] iv_len Initial vector length in bytes - * @param [in] aad Additional Authentication data - * @param [in] aad_len Additional authentication data size - * @param [in] input Input data buffer - * @param [out] output Output buffer - * @param [in] tag MAC buffer - * @param [in] tag_len Tag/MAC size in bytes - * @return API execution status. - */ -#define sdp_sm4_ccm_decrypt_verify sdp_aes_ccm_decrypt_verify -#endif - -/** - * @brief Perform the DMA accelerated memcpy - * @param [in] base SDP base address - * @param [in] sdp_ctx SDP DMA context - * @param [out] dst Destination address for memcpy operation - * @param [in] src Source address for memcpy operation - * @param [in] length Length of the data to be copied - * @return API execution status. - */ -hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, const void *src, uint32_t length); - -/** - * @brief Perform the DMA accelerated memset - * @param [in] base SDP base address - * @param [in] sdp_ctx SDP DMA context - * @param [out] dst SDP destination address for memset operation - * @param [in] pattern pattern for memset operation - * @param [in] length length of the memory for memset operation - * @return API execution status. - */ -hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length); - -/** - * @brief Initialize the HASH engine - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [in] alg Hash algorithm - * @return API execution status. status_success or status_invalid_argument - */ -hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - -/** - * @brief Compute the HASH digest - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [in] data Data for HASH computing - * @param [in] length Data size for HASH computing - * - * @return API execution status. - */ -hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - -/** - * @brief Finish the HASH calculation and output the digest - * @param [in] base SDP base address - * @param [in] hash_ctx HASH operation context - * @param [out] digest Digest buffer - * - * @return API execution status. - */ -hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest); - -/** - * @brief Wait until the SDP operation gets done - * @param [in] base SDP base address - * - * @return API execution status. - */ -hpm_stat_t sdp_wait_done(SDP_Type *base); - - -/** - * @brief Trigger SDP operation via the specified SDP packet description - * @note 1. The Command Packet List should be in non-cacheable memory - * 2. This is a non-blocking API, users should confirm whether action completed or not by checking STA register - * in SDP - * @param [in] base SDP base address - * @param [in] action SDP action - * @param [in] cmd_pkt SDP Command packet description - * - * @return API execution status. - */ -hpm_stat_t sdp_trigger_action(SDP_Type *base, const sdp_action_t *action, const sdp_pkt_struct_t *cmd_pkt); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_SDP_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h deleted file mode 100644 index 5ebb18db6ea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdxc_drv.h +++ /dev/null @@ -1,1237 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDXC_DRV_H -#define HPM_SDXC_DRV_H - -/** - * - * @brief SDXC driver APIs - * @defgroup sdxc_interface SDXC driver APIs - * @ingroup sdxc_interfaces - * @{ - * - */ - -#include "hpm_common.h" -#include "hpm_sdxc_regs.h" -#include "hpm_sdxc_soc_drv.h" - -/** - * @brief Generic Definitions - * @note: - * If the Host support 1.8V, it means: - * 1. For SD card, it supports: - * - SDR12 - * - SDR25 - * - SDR50 - * - SDR104 - * - DDR50 - * 2. For eMMC, it supports: - * - DDR50 - * - HS200 - * - HS400 (if 8-bit is supported as well) - */ -#define SDXC_HOST_SUPPORT_1V8 (1UL << 0) /**< SDXC Host support 1.8v */ -#define SDXC_HOST_SUPPORT_4BIT (1UL << 1) /**< SDXC Host support 4bit */ -#define SDXC_HOST_SUPPORT_8BIT (1UL << 2) /**< SDXC Host support 8bit */ -#define SDXC_HOST_SUPPORT_EMMC (1UL << 3) /**< SDXC Host support EMMC */ - -/** - * @brief SDXC Pin features - */ -#define SDXC_HOST_SUPPORT_CD (1UL << 16) /**< SDXC Host support Card detection */ -#define SDXC_HOST_SUPPORT_VSEL (1UL << 17) /**< SDXC Host support Voltage Selection */ -#define SDXC_HOST_SUPPORT_PWR (1UL << 18) /**< SDXC Host support Power Switch */ -#define SDXC_HOST_SUPPORT_WP (1UL << 19) /**< SDXC Host support Write Protection */ -#define SDXC_HOST_SUPPORT_RST (1UL << 20) /**< SDXC Host support Reset Pin */ -#define SDXC_HOST_SUPPORT_DS (1UL << 21) /**< SDXC Host support Data Strobe */ - -/** - * @brief SDXC Pin is native or from GPIO - */ -#define SDXC_HOST_CD_IN_IP (SDXC_HOST_SUPPORT_CD << 8) /**< Card detection is controlled by IP */ -#define SDXC_HOST_VSEL_IN_IP (SDXC_HOST_SUPPORT_VSEL << 8) /**< Voltage selection is controlled by IP */ -#define SDXC_HOST_PWR_IN_IP (SDXC_HOST_SUPPORT_PWR << 8) /**< Power switch is controlled by IP */ -#define SDXC_HOST_WP_IN_IP (SDXC_HOST_SUPPORT_WP << 8) /**< Write protection is controlled by IP */ -#define SDXC_HOST_RST_IN_IP (SDXC_HOST_SUPPORT_RST << 8) /**< Reset Pin is controlled by IP */ - -/** - * @brief SDXC GPIO pin polarity - * If polarity is 0, it means: - * GPIO level 0 means disabled, 1 means enabled - * If polarity is 1, it meansL: - * GPIO level 0 means enabled, 1 means disabled - */ -#define SDXC_HOST_VSEL_PIN_POLARITY (SDXC_HOST_SUPPORT_CD << 16) -#define SDXC_HOST_CD_PIN_POLARITY (SDXC_HOST_VSEL_IN_IP << 16) -#define SDXC_HOST_PWR_PIN_POLARITY (SDXC_HOST_SUPPORT_PWR << 16) -#define SDXC_HOST_WP_PIN_POLARITY (SDXC_HOST_SUPPORT_WP << 16) -#define SDXC_HOST_RST_IN_POLARITY (SDXC_HOST_SUPPORT_DS << 16) - -/** - * @brief Command Response Type Selection - */ -#define SDXC_CMD_RESP_TYPE_NO_RESP (0U) /**< No Response */ -#define SDXC_CMD_RESP_TYPE_RESP_LEN_136 (1U) /**< Response Length 136 */ -#define SDXC_CMD_RESP_TYPE_RESP_LEN_48 (2U) /**< Response Length 48 */ -#define SDXC_CMD_RESP_TYPE_RESP_LEN_48B (3U) /**< Response Length 48; Check busy after response */ - - -#define SDXC_STS_CMD_ERR (SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK |\ - SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK | SDXC_INT_STAT_AUTO_CMD_ERR_MASK) -#define SDXC_STS_DATA_ERR (SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_DATA_CRC_ERR_MASK | \ - SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) -#define SDXC_STS_CARD_ERR (SDXC_INT_STAT_CARD_REMOVAL_MASK) -#define SDXC_STS_ERROR (SDXC_INT_STAT_ERR_INTERRUPT_MASK | SDXC_STS_CMD_ERR | SDXC_STS_DATA_ERR | SDXC_STS_CARD_ERR) -#define SDXC_STS_CMD_FLAGS (SDXC_STS_CMD_ERR | SDXC_INT_STAT_CMD_COMPLETE_MASK) - -#define SDXC_STS_ALL_FLAGS (SDXC_INT_STAT_ERR_INTERRUPT_MASK | SDXC_INT_STAT_CQE_EVENT_MASK | \ - SDXC_INT_STAT_FX_EVENT_MASK | SDXC_INT_STAT_RE_TUNE_EVENT_MASK | SDXC_INT_STAT_CARD_INTERRUPT_MASK | \ - SDXC_INT_STAT_CARD_REMOVAL_MASK | SDXC_INT_STAT_CARD_INSERTION_MASK | SDXC_INT_STAT_BUF_RD_READY_MASK | \ - SDXC_INT_STAT_BUF_WR_READY_MASK | SDXC_INT_STAT_DMA_INTERRUPT_MASK | SDXC_INT_STAT_BGAP_EVENT_MASK | \ - SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_INT_STAT_CMD_COMPLETE_MASK | SDXC_INT_STAT_BOOT_ACK_ERR_MASK | \ - SDXC_INT_STAT_RESP_ERR_MASK | SDXC_INT_STAT_TUNING_ERR_MASK | SDXC_INT_STAT_ADMA_ERR_MASK | \ - SDXC_INT_STAT_AUTO_CMD_ERR_MASK | SDXC_INT_STAT_CUR_LMT_ERR_MASK | SDXC_INT_STAT_DATA_END_BIT_ERR_MASK |\ - SDXC_INT_STAT_DATA_CRC_ERR_MASK | SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK |\ - SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK | SDXC_INT_STAT_CMD_TOUT_ERR_MASK) - - -/** - * @brief Software reset flag definitions - */ -typedef enum _sdxc_software_reset { - sdxc_reset_all, /**< Reset both command line and data line */ - sdxc_reset_cmd_line, /**< Reset command line */ - sdxc_reset_data_line, /**< Reset data line */ -} sdxc_sw_reset_type_t; - -/** - * @brief SDXC Bus voltage options - */ -typedef enum _sdxc_bus_voltage_option { - sdxc_bus_voltage_sd_1v8 = 0x01U, - sdxc_bus_voltage_sd_3v3 = 0x00U, - sdxc_bus_voltage_emmc_1v8 = 0x01U, - sdxc_bus_voltage_emmc_3v3 = 0x00U, -} sdxc_bus_voltage_option_t; - -/** - * @brief SDXC wakeup events - */ -typedef enum _sdxc_wakeup_event { - sdxc_wakeup_card_removal = 0x4U, /**< Wake-up event: Card removal */ - sdxc_wakeup_card_insert = 0x02U, /**< Wake-up event: Card insertion */ - sdxc_wakeup_card_interrupt = 0x01U, /**< Wake-up event: Card interrupt */ -} sdxc_wakeup_event_t; - -/** - * @brief SDXC DMA types - */ -typedef enum _sdxc_dma_type { - sdxc_dmasel_sdma = 0U, /**< SDXC DMA type: SDMA */ - sdxc_dmasel_adma2 = 2U, /**< SDXC DMA type: ADMA2 */ - sdxc_dmasel_adma2_or_3 = 3U, /**< SDXC DMA type: ADMA2 or ADMA3 */ - sdxc_dmasel_nodma = 0xFU, -} sdxc_dma_type_t; - -/** - * @brief SDXC Bus width options - */ -typedef enum _sdxc_bus_width { - sdxc_bus_width_1bit, /**< SDXC bus width: 1 bit */ - sdxc_bus_width_4bit, /**< SDXC bus width: 4 bits */ - sdxc_bus_width_8bit, /**< SDXC bus width: 8 bits */ -} sdxc_bus_width_t; - -/** - * @brief SDXC Speed mode options - */ -typedef enum _sdxc_speed_mode { - sdxc_sd_speed_sdr12 = 0U, /**< SDXC speed: SDR12 */ - sdxc_sd_speed_sdr25 = 1U, /**< SDXC speed: SDR25 */ - sdxc_sd_speed_sdr50 = 2U, /**< SDXC speed: SDR50 */ - sdxc_sd_speed_sdr104 = 3U, /**< SDXC speed: SDR104 */ - sdxc_sd_speed_ddr50 = 4U, /**< SDXC speed: DDR50 */ - sdxc_sd_speed_normal = sdxc_sd_speed_sdr12, /**< SDXC speed: Normal Speed */ - sdxc_sd_speed_high = sdxc_sd_speed_sdr25, /**< SDXC speed: High Speed */ - - sdxc_emmc_speed_legacy = 0U, /**< SDXC speed: MMC legacy speed */ - sdxc_emmc_speed_high_speed_sdr = 1U, /**< SDXC speed: MMC High Speed */ - sdxc_emmc_speed_hs200 = 3U, /**< SDXC speed: MMC HS200 speed */ - sdxc_emmc_speed_high_speed_ddr = 4U, /**< SDXC speed: MMC High Speed DDR */ - sdxc_emmc_speed_hs400 = 7U, /**< SDXC speed: MMC HS400 */ - - sdxc_sdmmc_speed_card_init = 0x10, - -} sdxc_speed_mode_t; - -/** - * @brief SDXC auto command types - */ -typedef enum _sdxc_auto_cmd_sel { - sdxc_auto_cmd_disabled = 0U, /**< Auto Command type: Disabled */ - sdxc_auto_cmd12_enabled = 1U, /**< Auto Command type: CMD12 enabled */ - sdxc_auto_cmd23_enabled = 2U, /**< Auto Command type: CMD23 enabled */ - sdxc_auto_cmd_auto_select = 3U, /**< Auto Command type: Auto selected */ -} sdxc_auto_cmd_sel_t; - -/** - * @brief SDXC transfer direction options - */ -typedef enum _sdxc_xfer_direction { - sdxc_xfer_dir_write = 0, - sdxc_xfer_dir_read = 1, -} sdxc_xfer_direction_t; - -/** - * @brief SDXC Command types - */ -typedef enum _sdxc_command_type { - sdxc_cmd_type_normal_cmd = 0U, - sdxc_cmd_type_suspend_cmd = 1U, - sdxc_cmd_tye_resume_cmd = 2U, - sdxc_cmd_type_abort_cmd = 3U, - sdxc_cmd_type_empty = 4U, -} sdxc_command_type_t; - -/** - * @brief Command Type - */ -#define SDXC_CMD_TYPE_NORMAL (0UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) -#define SDXC_CMD_TYPE_SUSPEND (1UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) -#define SDXC_CMD_TYPE_RESUME (2UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) -#define SDXC_CMD_TYPE_ABORT (3UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) - -/** - * @brief SDXC boot mode types - */ -typedef enum _sdxc_boot_mode { - sdxc_boot_mode_normal = 0, - sdxc_boot_mode_alternative = 1, -} sdxc_boot_mode_t; - -/** - * @brief SDXC response types - */ -typedef enum _sdxc_response_type { - sdxc_response_type_no_resp = 0, - sdxc_response_type_resp_len_136bit = 1, - sdxc_response_type_resp_len_48bit = 2, - sdxc_response_type_resp_len_48bit_check_busy = 3, -} sdxc_response_type_t; - -#define SDXC_CMD_RESP_NO_RESPONSE (0UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) -#define SDXC_CMD_RESP_LEN_136 (1UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) -#define SDXC_CMD_RESP_LEN_48 (2UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) -#define SDXC_CMD_RESP_LEN_48B (3UL << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) - -#define SDXC_CMD_CMD_IS_MAIN_CMD (0U) -#define SDXC_CMD_CMD_IS_SUB_CMD (SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) - -#define SDXC_CMD_CMD_CRC_CHK_EN (SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) -#define SDXC_CMD_CMD_CRC_CHK_DIS (0U) - -#define SDXC_CMD_CMD_IDX_CHK_EN (SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) -#define SDXC_CMD_CMD_IDX_CHK_DIS (0U) - -#define SDXC_CMD_DATA_PRESENT (SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) -#define SDXC_CMD_DATA_NO_PRESENT (0U) - -#define SDXC_CMD_CMD_TYPE_NORMAL (0U) -#define SDXC_CMD_CMD_TYPE_SUSPEND (1UL << SDXC_CMD_XFER_CMD_TYPE_SHIFT) -#define SDXC_CMD_CMD_TYPE_RESUME (2U << SDXC_CMD_XFER_CMD_TYPE_SHIFT) -#define SDXC_CMD_CMD_TYPE_ABORT (3U << SDXC_CMD_XFER_CMD_TYPE_SHIFT) - -/** - * @brief SDXC error codes - */ -enum { - status_sdxc_busy = MAKE_STATUS(status_group_sdxc, 0), /**< SDXC is busy */ - status_sdxc_error = MAKE_STATUS(status_group_sdxc, 1), /**< SDXC error */ - status_sdxc_send_cmd_failed = MAKE_STATUS(status_group_sdxc, 2), /**< SDXC command failed */ - status_sdxc_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 3), /**< SDXC command timed out */ - status_sdxc_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 4), /**< SDXC command CRC error */ - status_sdxc_cmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 5), /**< SDXC command end bit error */ - status_sdxc_cmd_index_error = MAKE_STATUS(status_group_sdxc, 6), /**< SDXC command index error */ - status_sdxc_data_timeout_error = MAKE_STATUS(status_group_sdxc, 7), /**< SDXC data timeout error */ - status_sdxc_data_crc_error = MAKE_STATUS(status_group_sdxc, 8), /**< SDXC data CRC error */ - status_sdxc_data_end_bit_error = MAKE_STATUS(status_group_sdxc, 9), /**< SDXC data end bit error */ - status_sdxc_auto_cmd_error = MAKE_STATUS(status_group_sdxc, 10), /**< SDXC auto command error */ - status_sdxc_adma_error = MAKE_STATUS(status_group_sdxc, 11), /**< SDXC ADMA error */ - status_sdxc_tuning_error = MAKE_STATUS(status_group_sdxc, 12), /**< SDXC tuning error */ - status_sdxc_response_error = MAKE_STATUS(status_group_sdxc, 13), /**< SDXC response error */ - status_sdxc_boot_ack_error = MAKE_STATUS(status_group_sdxc, 14), /**< SDXC boot ack error */ - status_sdxc_retuning_request = MAKE_STATUS(status_group_sdxc, 15), /**< SDXC retuning request */ - /* SDXC Auto CMD12 command not executed */ - status_sdxc_autocmd_cmd12_not_exec = MAKE_STATUS(status_group_sdxc, 16), - status_sdxc_autocmd_cmd_timeout_error = MAKE_STATUS(status_group_sdxc, 17), /**< SDXC Auto CMD timed out */ - status_sdxc_autocmd_cmd_crc_error = MAKE_STATUS(status_group_sdxc, 18), /**< SDXC Auto CMD crc error */ - status_sdxc_autocmd_end_bit_error = MAKE_STATUS(status_group_sdxc, 19), /**< SDXC Auto CMD end bit error */ - status_sdxc_autocmd_cmd_index_error = MAKE_STATUS(status_group_sdxc, 20), /**< SDXC Auto CMD index error */ - status_sdxc_autocmd_cmd_response_error = MAKE_STATUS(status_group_sdxc, 21), /**< SDXC Auto CMD response error */ - /* SDXC Auto CMD not issued auto CMD12 */ - status_sdxc_autocmd_cmd_not_issued_auto_cmd12 = MAKE_STATUS(status_group_sdxc, 22), - /**< SDXC unsupported operation */ - status_sdxc_unsupported = MAKE_STATUS(status_group_sdxc, 23), - status_sdxc_transfer_data_completed = MAKE_STATUS(status_group_sdxc, 24), /**< SDXC transfer data completed */ - status_sdxc_send_cmd_successful = MAKE_STATUS(status_group_sdxc, 25), /**< SDXC send command succeeded */ - status_sdxc_transfer_dma_completed = MAKE_STATUS(status_group_sdxc, 26), /**< SDXC transfer DMA completed */ - status_sdxc_transfer_data_failed = MAKE_STATUS(status_group_sdxc, 27), /**< SDXC transfer data failed */ - status_sdxc_dma_addr_unaligned = MAKE_STATUS(status_group_sdxc, 28), /**< SDXC DMA address unaligned */ - status_sdxc_tuning_failed = MAKE_STATUS(status_group_sdxc, 29), /**< SDXC tuning failed */ - status_sdxc_card_removed = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC Card removed */ - status_sdxc_non_recoverable_error = MAKE_STATUS(status_group_sdxc, 30), /**< SDXC non-recoverable error */ - status_sdxc_recoverable_error = MAKE_STATUS(status_group_sdxc, 31), /**< SDXC recoverable error */ -}; - -/** - * @brief SDXC Capacities - */ -typedef struct { - union { - struct { - uint32_t tout_clk_freq: 6; /**< Timeout clock frequency */ - uint32_t : 1; - uint32_t tout_clk_unit: 1; /**< Timeout clock unit */ - uint32_t base_clk_freq: 8; /**< Base clock frequency */ - uint32_t max_blk_len: 2; /**< Maximum Block length */ - uint32_t embedded_8_bit_support: 1; /**< Embedded 8-bit support */ - uint32_t adma2_support: 1; /**< ADMA2 support */ - uint32_t : 1; - uint32_t high_speed_support: 1; /**< High speed support */ - uint32_t sdma_support: 1; /**< SDMA support */ - uint32_t suspend_resume_support: 1; /**< Suspend resume support */ - uint32_t voltage_3v3_support: 1; /**< 3.3v support */ - uint32_t voltage_3v0_support: 1; /**< 3.0v support */ - uint32_t voltage_1v8_support: 1; /**< 1.8v support */ - uint32_t sys_addr_64_bit_v4_support: 1; /**< SD Host Version 4 support */ - uint32_t sys_addr_64_bit_v3_support: 1; /**< SD Host Version 3 support */ - uint32_t asysnc_interrupt_support: 1; /**< Asynchronous interrupt support */ - uint32_t slot_type_r: 2; /**< Slot type */ - }; - uint32_t U; - } capabilities1; - - union { - struct { - uint32_t sdr50_support: 1; /**< SDR50 support */ - uint32_t sdr104_support: 1; /**< SDR104 support */ - uint32_t ddr50_support: 1; /**< DDR50 support */ - uint32_t uhs2_support: 1; /**< UHS2 support */ - uint32_t drv_type_a: 1; /**< Drive TypeA support */ - uint32_t drv_type_c: 1; /**< Drive TypeC support */ - uint32_t drv_type_d: 1; /**< Drive TypeD support */ - uint32_t reserved0: 1; - uint32_t retune_cnt: 4; /**< Retune count support */ - uint32_t : 1; - uint32_t use_tuning_sdr50: 1; /**< Use tuning sdr50 support */ - uint32_t re_tuning_modes: 2; /**< Retune modes */ - uint32_t clk_mul: 8; /**< Clock multiplier */ - uint32_t : 3; - uint32_t adma3_support: 1; /**< ADMA3 support */ - uint32_t vdd2_1v8_support: 1; /**< VDD2 1v8 support */ - uint32_t : 3; - }; - uint32_t U; - } capabilities2; - - union { - struct { - uint32_t max_current_3v3: 8; /**< Maximum current at 3.3V */ - uint32_t max_current_3v0: 8; /**< Maximum current at 3.0V */ - uint32_t max_current_1v8: 8; /**< Maximum current at 1.8V */ - uint32_t reserved: 8; - }; - uint32_t U; - } curr_capabilities1; - - union { - struct { - uint32_t max_current_vdd2_1v8: 8; /**< Maximum current at VDD2 1.8V */ - uint32_t reserved: 24; - }; - uint32_t U; - } curr_capabilities2; - -} sdxc_capabilities_t; - -/** - * @brief SDXC Device response type - */ -typedef enum _sdxc_dev_resp_type { - sdxc_dev_resp_none = 0, - sdxc_dev_resp_r1, - sdxc_dev_resp_r1b, - sdxc_dev_resp_r2, - sdxc_dev_resp_r3, - sdxc_dev_resp_r4, - sdxc_dev_resp_r5, - sdxc_dev_resp_r5b, - sdxc_dev_resp_r6, - sdxc_dev_resp_r7, -} sdxc_dev_resp_type_t; - -/** - * @brief SDXC command structure - */ -typedef struct _sdxc_command { - uint32_t cmd_index; /**< Command index */ - uint32_t cmd_argument; /**< Command argument */ - uint32_t cmd_flags; /**< Command flags */ - sdxc_command_type_t cmd_type; /**< Command type */ - sdxc_dev_resp_type_t resp_type; /**< Command response type */ - uint32_t resp_error_flags; /**< Command response error flags */ - uint32_t response[4]; /**< Response buffer */ - uint32_t auto_cmd_resp; /**< Auto command response */ - uint32_t cmd_timeout_ms; /**< Command Timeout in ms, 0 - means use default short timeout */ -} sdxc_command_t; - -/** - * @brief SDXC data list - */ -typedef struct _sdxc_data_list { - uint32_t *data_addr; - uint32_t data_size; - struct _sdxc_data_list *data_list; -} sdxc_data_list_t; - -/** - * @brief SDXC data structure - */ -typedef struct _sdxc_data { - bool enable_auto_cmd12; - bool enable_auto_cmd23; - bool enable_ignore_error; - uint8_t data_type; - uint32_t block_size; - uint32_t block_cnt; - uint32_t *rx_data; - const uint32_t *tx_data; -} sdxc_data_t; - -/** - * @brief SDXC transfer data type - */ -enum { - sdxc_xfer_data_normal = 0U, /**< Transfer normal read/write data */ - sdxc_xfer_data_boot = 1U, /**< Transfer boot data */ - sdxc_xfer_data_boot_continuous = 2U, /**< Transfer boot data continuously */ -}; - -/** - * @brief SDXC transfer context - */ -typedef struct _sdxc_xfer { - sdxc_data_t *data; - sdxc_command_t *command; -} sdxc_xfer_t; - -/** - * @brief SDXC ADMA configuration - */ -typedef struct _sdxc_adma_config { - sdxc_dma_type_t dma_type; - uint32_t *adma_table; - uint32_t adma_table_words; -} sdxc_adma_config_t; - -enum { - sdxc_adma_desc_single_flag = 0U, - sdxc_adma_desc_multi_flag = 1U, -}; - -/** - * @brief SDXC configuration - */ -typedef struct _sdxc_config { - uint32_t data_timeout; /**< Data timeout in milliseconds */ -} sdxc_config_t; - -/** - * @brief SDXC ADMA2 descriptor - */ -typedef struct _sdxc_adma2_descriptor { - union { - struct { - uint32_t valid: 1; /**< Valid flag */ - uint32_t end: 1; /**< End flag */ - uint32_t interrupt: 1; /**< Interrupt flag */ - uint32_t act: 3; /**INT_STAT; -} - -/** - * @brief Check whether SD card is inserted - * @retval SD Card insertion status - * @arg true SD Card is inserted - * @arg false SD card is not inserted - */ -static inline bool sdxc_is_card_inserted(SDXC_Type *base) -{ - return IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CARD_INSERTED_MASK); -} - -/** - * @brief Check whether SD card is Write Protected - * @retval SD Card Write Protection status - * @arg true SD Card is Write protected - * @arg false SD card is not Write Protected - */ -static inline bool sdxc_is_write_protected(SDXC_Type *base) -{ - return IS_HPM_BITMASK_CLR(base->PSTATE, SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK); -} - -/** - * @brief Clear SDXC interrupt status - * @param [in] base SDXC base address - * @param [in] status_mask the status mask to be cleared - */ -static inline void sdxc_clear_interrupt_status(SDXC_Type *base, uint32_t status_mask) -{ - base->INT_STAT = status_mask; -} - -/** - * @brief Enable SDXC interrupt status - * @param [in] base SDXC base address - * @param [in] mask SDXC interrupt status mask - * @param [in] enable Interrupt status enable flag - */ -static inline void sdxc_enable_interrupt_status(SDXC_Type *base, uint32_t mask, bool enable) -{ - if (enable) { - base->INT_STAT_EN |= mask; - } else { - base->INT_STAT_EN &= ~mask; - } -} - -/** - * @brief Enable SDXC interrupt signal - * @param [in] base SDXC base address - * @param [in] mask SDXC interrupt signal mask - * @param [in] enable Interrupt signal enable flag - */ -static inline void sdxc_enable_interrupt_signal(SDXC_Type *base, uint32_t mask, bool enable) -{ - if (enable) { - base->INT_SIGNAL_EN |= mask; - } else { - base->INT_SIGNAL_EN &= ~mask; - } -} - -/** - * @brief Get SDXC capabilities - * @param [in] base SDXC base address - * @param [out] capabilities buffer - */ -hpm_stat_t sdxc_get_capabilities(SDXC_Type *base, sdxc_capabilities_t *capabilities); - - -/** - * @brief Get SDXC ADMA error status - * @param [in] base SDXC base address - * @retval AMDA error status register value - */ -static inline uint8_t sdxc_get_adma_error_status(SDXC_Type *base) -{ - return base->ADMA_ERR_STAT; -} - -/** - * @brief Configure SDXC data timeout internal - * @param [in] base SDXC base address - * @param [in] timeout SDXC data timeout option - */ -static inline void sdxc_configure_data_timeout(SDXC_Type *base, uint8_t timeout) -{ - base->SYS_CTRL = (base->SYS_CTRL & ~SDXC_SYS_CTRL_TOUT_CNT_MASK) | SDXC_SYS_CTRL_TOUT_CNT_SET(timeout); -} - -/** - * @brief Configure SDXC interrupt at block gap - * @param [in] base SDXC base address - * @param [in] enable Enable Interrupt_at_Block_Gap flag - */ -static inline void sdxc_interrupt_at_block_gap(SDXC_Type *base, bool enable) -{ - if (enable) { - base->PROT_CTRL |= SDXC_PROT_CTRL_INT_AT_BGAP_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_INT_AT_BGAP_MASK; - } -} - -/** - * @brief Enable or Disable SDXC Read Wait - * @param [in] base SDXC base address - * @param [in] enable Enable SDXC Read Wait flag - */ -static inline void sdxc_read_wait_control(SDXC_Type *base, bool enable) -{ - if (enable) { - base->PROT_CTRL |= SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK; - } -} - -/** - * @brief Configure SDXC continue request - * @param [in] base SDXC base address - * @param [in] enable Flag to enable/disable SDXC continue request - */ -static inline void sdxc_continue_request(SDXC_Type *base, bool enable) -{ - if (enable) { - base->PROT_CTRL |= SDXC_PROT_CTRL_CONTINUE_REQ_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_CONTINUE_REQ_MASK; - } -} - -/** - * @brief Configure SDXC StopAtBlockGap request - * @param [in] base SDXC base address - * @param [in] enable Flag to enable/disable StopAtBlockGap request - */ -static inline void sdxc_stop_at_block_gap_request(SDXC_Type *base, bool enable) -{ - if (enable) { - base->PROT_CTRL |= SDXC_PROT_CTRL_STOP_BG_REQ_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_STOP_BG_REQ_MASK; - } -} - -/** - * @brief Control the SDXC high-speed support - * @param [in] base SDXC base address - * @param [in] enable flag to Enable/disable SDXC high-speed support - */ -static inline void sdxc_enable_high_speed(SDXC_Type *base, bool enable) -{ - if (enable) { - base->PROT_CTRL |= SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; - } -} - -/** - * @brief Control the SDXC power pin - * - * @param [in] base SDXC base address - * @param [in] enable Flag to control the SDXC power pin - */ -static inline void sdxc_enable_power(SDXC_Type *base, bool enable) -{ - if (enable) { - base->PROT_CTRL |= SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK; - } -} - -/** - * @brief Enable SDXC asynchronous interrupt support - * @param [in] base SDXC base address - * @param [in] enable Flag to enable/disable SDXC asynchronous interrupt support - */ -static inline void sdxc_enable_async_interrupt(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK; - } else { - base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK; - } -} - -/** - * @brief Enable SDXC Preset support - * @param [in] base SDXC base address - * @param [in] enable flag to enable/disable SDXC Preset support - */ -static inline void sdxc_enable_preset(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK; - } else { - base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK; - } -} - -/** - * @brief Enable SD Host version 4 - * @param [in] base SDXC base address - * @param [in] enable flag to enable/disable SD Host version 4 support - */ -static inline void sdxc_enable_host_version4(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK; - } else { - base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK; - } -} - -/** - * @brief Start SDXC tuning process - * @param [in] base SDXC base address - */ -static inline void sdxc_execute_tuning(SDXC_Type *base) -{ - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK | SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK; -} - -/** - * @brief Enable SDXC software tuning process - * @param [in] base SDXC base address - * @param [in] enable flag to enable/disable SDXC software tuning - */ -static inline void sdxc_enable_software_tuning(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK; - } else { - base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK; - } -} - -/** - * @brief Reset SDXC tuning engine - * @param [in] base SDXC base address - */ -static inline void sdxc_reset_tuning_engine(SDXC_Type *base) -{ - base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK; -} - -/** - * @brief Switch SDXC to 1.8V signaling mode - * @param [in] base SDXC base address - * @param [in] enable Flag to switch to 1.8v signaling mode/stay at 3.0v signaling mode - */ -static inline void sdxc_switch_to_1v8_signal(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; - } else { - base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; - } -} - -/** - * @brief Enable/Disable SDXC internal clock - * @param[in] base SDXC base address - * @param [in] enable Flag to enable/disable SDXC internal clock - */ -static inline void sdxc_enable_internal_clock(SDXC_Type *base, bool enable) -{ - if (enable) { - base->SYS_CTRL |= SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; - } else { - base->SYS_CTRL &= ~SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; - } -} - -/** - * @brief Get Present status register value - * @param [in] base SDXC base address - * @retval SDXC PRESENT register value - */ -static inline uint32_t sdxc_get_present_status(SDXC_Type *base) -{ - return base->PSTATE; -} - -/** - * @brief Check whether the Data Buffer is writable or not - * @param [in] base SDXC base address - * @retval true Data buffer is writeable - * @retval false Data buffer write is disabled - */ -static inline bool sdxc_is_data_buf_writable(SDXC_Type *base) -{ - return ((base->PSTATE & SDXC_PSTATE_BUF_WR_ENABLE_MASK) != 0U); -} - -/** - * @brief Check whether the data buffer is readable - * @param [in] base SDXC base address - * @retval true There are data available in data buffer - * @retval false there is no data available in data buffer, read is disabled - */ -static inline bool sdxc_is_data_buf_readable(SDXC_Type *base) -{ - return ((base->PSTATE & SDXC_PSTATE_BUF_RD_ENABLE_MASK) != 0U); -} - -/** - * @brief Read data from SDXC using non-DMA mode - * @param [in] base SDXC base address - * @retval Data read from SDXC - */ -static inline uint32_t sdxc_read_data(SDXC_Type *base) -{ - return base->BUF_DATA; -} - -/** - * @brief Write data to SDXC using non-DMA mode - * @param [in] base SDXC base address - * @param [in] data Data to be written to SDXC - */ -static inline void sdxc_write_data(SDXC_Type *base, uint32_t data) -{ - base->BUF_DATA = data; -} - -/** - * @brief Get SDXC DATA3-DATA0 IO level - * @param [in] base SDXC base address - * @retval SDXC data3-data0 IO level - */ -static inline uint32_t sdxc_get_data3_0_level(SDXC_Type *base) -{ - return SDXC_PSTATE_DAT_3_0_GET(base->PSTATE); -} - -/** - * @brief Enable SDXC auto tuning - * @param [in] base SDXC base address - * @param [in] enable Flag to enable/disable SDXC auto tuning - */ -static inline void sdxc_enable_auto_tuning(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_AT_EN_MASK; - } else { - base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_AT_EN_MASK; - } -} - -/** - * @brief Stop Clock During Phase Code Change - * - * @param [in] base SDXC base address - * @param [in] enable Flag to determine whether stopping clock during phase code change - */ -static inline void sdxc_stop_clock_during_phase_code_change(SDXC_Type *base, bool enable) -{ - if (enable) { - base->AUTO_TUNING_CTRL |= SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK; - } else { - base->AUTO_TUNING_CTRL &= ~SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK; - } -} - -/** - * @brief Set The delay cycles during phase switching and stable clock out - * - * @param [in] base SDXC base address - * @param [in] delay_cnt Delay cycles - */ -static inline void sdxc_set_post_change_delay(SDXC_Type *base, uint8_t delay_cnt) -{ - base->AUTO_TUNING_CTRL = (base->AUTO_TUNING_CTRL & ~SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) \ - | SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(delay_cnt - 1U); -} - -/** - * @brief Enable EMMC support - * @param [in] base SDXC base address - * @param [in] enable Flag to enable/disable EMMC support - */ -static inline void sdxc_enable_emmc_support(SDXC_Type *base, bool enable) -{ - if (enable) { - base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK; - } else { - base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK; - } -} - -/** - * @brief Enable/Disable SDXC MMC boot - * @param [in] base SDXC base address - * @param [in] enable FLag to enable/disable SDXC MMC boot - */ -static inline void sdxc_enable_mmc_boot(SDXC_Type *base, bool enable) -{ - if (enable) { - base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK; - } else { - base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK; - } -} - -/** - * @brief Set SDXC force event - * @param [in] base SDXC base address - * @param [in] mask SDXC event mask - */ -static inline void sdxc_force_event(SDXC_Type *base, uint32_t mask) -{ - base->FORCE_EVENT = mask; -} - -/** - * @brief Enable/disable SDXC SD clock output - * @param [in] base SDXC base address - * @param [in] enable Flag to enable/disable SDXC SD clock output - */ -static inline void sdxc_enable_sd_clock(SDXC_Type *base, bool enable) -{ - if (enable) { - base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; - while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) { - } - } else { - base->SYS_CTRL &= ~SDXC_SYS_CTRL_SD_CLK_EN_MASK; - while (IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) { - } - } -} - -/** - * @brief Set SDXC center phase code - * @param [in] base SDXC base address - * @param [in] value SDXC center phase value - */ -static inline void sdxc_set_center_phase_code(SDXC_Type *base, uint32_t value) -{ - base->AUTO_TUNING_STAT = (base->AUTO_TUNING_STAT & ~SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) | - SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(value); -} - -/** - * @brief Enable SDXC enhanced strobe - * @param [in] base SDXC base address - * @param [in] enable flag to enable/disable SDXC enhanced strobe - */ -static inline void sdxc_enable_enhanced_strobe(SDXC_Type *base, bool enable) -{ - if (enable) { - base->EMMC_BOOT_CTRL |= SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK; - } else { - base->EMMC_BOOT_CTRL &= ~SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK; - } -} - -/** - * @brief Set MMC boot configuration - * @param [in] base SDXC base address - * @param [in] config MMC boot configuration - */ -void sdxc_set_mmc_boot_config(SDXC_Type *base, const sdxc_boot_config_t *config); - -/** - * @brief Send Command via SDXC - * @param [in] base SDXC base address - * @param [in] cmd Command - * @retval status_timeout Sending command timed out - * @retval status_success Command was sent out successfully - */ -hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd); - -/** - * @brief Receive command response - * @param [in] base SDXC base address - * @param [in,out] cmd Command - * @return status_success if no error happened - */ -hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd); - -/** - * @brief Parse the SDXC interrupt status to HPM encoded status - * @param [in] base SDXC base status - * @return status_success if no error happened - */ -hpm_stat_t sdxc_parse_interrupt_status(SDXC_Type *base); - -/** - * @brief Wait until SDXC command completes - * @param [in] base SDXC base address - * @param [in] cmd Command - * @param [out] polling_cmd_done flag to determine whether to use blocking wait - * @retval SDXC command execution status - */ -hpm_stat_t sdxc_wait_cmd_done(SDXC_Type *base, sdxc_command_t *cmd, bool polling_cmd_done); - -/** - * @brief Set Data transfer configuration - * @param [in] base SDXC base address - * @param [in] data_dir Data transfer direction - * @param [in] block_cnt Block count for data transfer - * @param [in] block_size Block size for data transfer - */ -void sdxc_set_data_config(SDXC_Type *base, sdxc_xfer_direction_t data_dir, uint32_t block_cnt, uint32_t block_size); - -/** - * @brief Set ADMA table configuration - * @param [in] base SDXC base address - * @param [in] dma_cfg DMA configuration - * @param [in] data_cfg Data configuration - * @param [in] flags Flags for AMDA transfer - * @retval API execution status - */ -hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, - sdxc_adma_config_t *dma_cfg, - sdxc_data_t *data_cfg, - uint32_t flags); - -/** - * @brief Set ADMA2 descriptor - * @param [in] adma_tbl ADMA2 table - * @param [in] adma_table_words ADMA2 table size in words - * @param [in] data_buf pointer to the Data to be transferred - * @param [in] data_bytes Data size for transfer - * @param [in] flags Flags for ADMA2 descriptor - * @retval API execution status - */ -hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, - uint32_t adma_table_words, - const uint32_t *data_buf, - uint32_t data_bytes, - uint32_t flags); - -/** - * @brief Set DMA configuration - * @param [in] base SDXC base address - * @param [in] dma_cfg DMA configuration data structure - * @param [in] data_addr Buffer holds incoming/outgoing data - * @param [in] enable_auto_cmd23 Flag to determine whether to enable auto CMD23 or not - * @retval API execution status - */ -hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, - sdxc_adma_config_t *dma_cfg, - const uint32_t *data_addr, - bool enable_auto_cmd23); - -/** - * @brief Initialize SDXC controller - * @param [in] base SDXC base address - * @param [in] config SDXC configuration - */ -void sdxc_init(SDXC_Type *base, const sdxc_config_t *config); - -/** - * @brief Set the Data Timeout Counter value for an SD/eMMC device - * @param [in] base SDXC base address - * @param [in] timeout_in_ms Required timeout value in milliseconds, maximum value is 131,072ms - * @param [out] actual_timeout_ms Actual timeout in milliseconds, reported by this API - */ -void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms); - -/** - * @brief Set SDXC speed mode - * @param [in] base SDXC base address - * @param [in] mode SDXC speed mode option - */ -void sdxc_set_speed_mode(SDXC_Type *base, sdxc_speed_mode_t mode); - - -/** - * @brief Set SDXC Data bus width - * @param [in] base SDXC base address - * @param [in] width SDXC bus width option - */ -void sdxc_set_data_bus_width(SDXC_Type *base, sdxc_bus_width_t width); - -/** - * @brief Get SDXC Data bus width - * @param [in] base SDXC base address - * @return Actual bus width, valid value: 1 / 4 / 8 - */ -uint32_t sdxc_get_data_bus_width(SDXC_Type *base); - -/** - * @brief Set SDXC IO voltage - * @param [in] base SDXC base address - * @param [option] SDXC voltage option - */ -void sdxc_select_voltage(SDXC_Type *base, sdxc_bus_voltage_option_t option); - -/** - * @brief Reset SDXC - * @param [in] base SDXC base address - * @param [in] reset_type SDXC reset type - * @param [in] timeout timeout ticks - * @retval SDXC reset result - */ -bool sdxc_reset(SDXC_Type *base, sdxc_sw_reset_type_t reset_type, uint32_t timeout); - -/** - * @brief Enable SDXC wakeup interrupt - * @param [in] base SDXC base address - * @param [in] evt SDXC wakeup interrupt - * @param [in] enable Flag to control whether to enable SDXC wakeup event - */ -void sdxc_enable_wakeup_event(SDXC_Type *base, sdxc_wakeup_event_t evt, bool enable); - -/** - * @brief Start SDXC transfer in blocking way - * @param [in] base SDXC base address - * @param [in] dma_config SDXC DMA configuration - * @param [in] xfer SDXC transfer context - * @retval SDXC transfer status - */ -hpm_stat_t sdxc_transfer_blocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); - -/** - * @brief Start SDXC transfer in nonblocking way - * @param [in] base SDXC base address - * @param [in] dma_config SDXC DMA configuration - * @param [in] xfer SDXC transfer context - * @retval SDXC transfer status - */ -hpm_stat_t sdxc_transfer_nonblocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer); - -/** - * @brief SDXC Error recovery - * @param [in] base SDXC base address - * @retval SDXC error recovery status - */ -hpm_stat_t sdxc_error_recovery(SDXC_Type *base); - -/** - * @brief Perform SDXC tuning flow sequence - * @param [in] base SDXC base address - * @param [in] tuning_cmd Tuning command - * @retval Tuning status - */ -hpm_stat_t sdxc_perform_tuning_flow_sequence(SDXC_Type *base, uint8_t tuning_cmd); - -/** - * @brief Perform SDXC software tuning - * @param [in] base SDXC base address - * @param [in] tuning_cmd Tuning command - * @retval Tuning status - */ -hpm_stat_t sdxc_perform_software_tuning(SDXC_Type *base, uint8_t tuning_cmd); - -/** - * @brief Perform SDXC auto tuning - * @param [in] base SDXC base address - * @param [in] tuning_cmd tuning command - * @retval Tuning status - */ -hpm_stat_t sdxc_perform_auto_tuning(SDXC_Type *base, uint8_t tuning_cmd); - -#if defined(__cplusplus) -} -#endif - -/** - * @} - */ - -#endif /*HPM_SDXC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h deleted file mode 100644 index 3e29e814192..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sei_drv.h +++ /dev/null @@ -1,1019 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SEI_DRV_H -#define HPM_SEI_DRV_H - -#include "hpm_common.h" -#include "hpm_sei_regs.h" -#include "hpm_soc_feature.h" -#include "hpm_soc_ip_feature.h" - -/** - * @brief sei arming action - */ -typedef enum { - sei_arming_direct_exec = 0, - sei_arming_wait_trigger -} sei_arming_mode_t; - -/** - * @brief sei watchdog action - */ -typedef enum { - sei_wdg_exec_next_instr = 0, - sei_wdg_exec_exception_instr -} sei_wdg_action_t; - -/** - * @brief sei transfer mode - */ -typedef enum { - sei_synchronous_master_mode = 0, - sei_synchronous_slave_mode, - sei_asynchronous_mode -} sei_tranceiver_mode_t; - -/** - * @brief sei asynchronous mode parity - */ -typedef enum { - sei_asynchronous_parity_even = 0, - sei_asynchronous_parity_odd -} sei_asynchronous_parity_t; - -/** - * @brief sei ilde state - */ -typedef enum { - sei_idle_low_state = 0, - sei_idle_high_state, -} sei_idle_state_t; - -/** - * @brief sei data mode - */ -typedef enum { - sei_data_mode = 0, - sei_check_mode, - sei_crc_mode -} sei_data_mode_t; - -/** - * @brief sei data bit order - */ -typedef enum { - sei_bit_lsb_first = 0, - sei_bit_msb_first -} sei_data_bit_order_t; - -/** - * @brief sei data word order - */ -typedef enum { - sei_word_nonreverse = 0, - sei_word_reverse -} sei_data_word_order_t; - -/** - * @brief sei state transition condition - */ -typedef enum { - sei_state_tran_condition_high_match = 0, - sei_state_tran_condition_low_dismatch, - sei_state_tran_condition_rise_entry, - sei_state_tran_condition_fall_leave -} sei_state_tran_condition_t; - -/** - * @brief sei trig in type - */ -typedef enum { - sei_trig_in0 = 0, - sei_trig_in1, - sei_trig_in_period, - sei_trig_in_soft -} sei_trig_in_type_t; /**< trig input type */ - -/** - * @brief sei irq event - */ -typedef enum { - sei_irq_stall_event = SEI_CTRL_IRQ_INT_FLAG_STALL_MASK, - sei_irq_execpt_event = SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK, - sei_irq_wdog_event = SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK, - sei_irq_instr_ptr0_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK, - sei_irq_instr_ptr1_start_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK, - sei_irq_instr_value0_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK, - sei_irq_instr_value1_start_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK, - sei_irq_instr_ptr0_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK, - sei_irq_instr_ptr1_end_event = SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK, - sei_irq_instr_value0_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK, - sei_irq_instr_value1_end_event = SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK, - sei_irq_trx_err_event = SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK, - sei_irq_timeout_event = SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK, - sei_irq_latch0_event = SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK, - sei_irq_latch1_event = SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK, - sei_irq_latch2_event = SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK, - sei_irq_latch3_event = SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK, - sei_irq_sample_err_event = SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK, - sei_irq_trig0_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK, - sei_irq_trig1_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK, - sei_irq_trig2_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK, - sei_irq_trig3_event = SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK, - sei_irq_trig0_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK, - sei_irq_trig1_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK, - sei_irq_trig2_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK, - sei_irq_trig3_err_event = SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK, -} sei_irq_event_t; /**< irq event type */ - -/** - * @brief sei select command or data - */ -#define SEI_SELECT_CMD true /**< select cmd */ -#define SEI_SELECT_DATA false /**< select data */ - -/** - * @brief sei const data register index - */ -#define SEI_DATA_CONST_0 (30UL) -#define SEI_DATA_CONST_1 (31UL) - -/** - * @brief sei instruction operation command - */ -#define SEI_INSTR_OP_HALT 0u /**< op halt */ -#define SEI_INSTR_OP_JUMP 1u /**< op jump */ -#define SEI_INSTR_OP_SEND_WDG 2u /**< op send with watchdog */ -#define SEI_INSTR_OP_SEND 3u /**< op send */ -#define SEI_INSTR_OP_WAIT_WDG 4u /**< op wait with watchdog */ -#define SEI_INSTR_OP_WAIT 5u /**< op wait */ -#define SEI_INSTR_OP_RECV_WDG 6u /**< op recv with watchdog */ -#define SEI_INSTR_OP_RECV 7u /**< op recv */ - -/** - * @brief sei instruction synchronous master clock type - */ -#define SEI_INSTR_M_CK_LOW 0u /**< clock low */ -#define SEI_INSTR_M_CK_RISE_FALL 1u /**< clock rise fall */ -#define SEI_INSTR_M_CK_FALL_RISE 2u /**< clock fall rise */ -#define SEI_INSTR_M_CK_HIGH 3u /**< clock high */ - -/** - * @brief sei instruction synchronous slave clock type - */ -#define SEI_INSTR_S_CK_DEFAULT 0u /**< default */ -#define SEI_INSTR_S_CK_TRX_EXCH 1u /**< rx tx exchange */ -#define SEI_INSTR_S_CK_TIMEOUT_EN 2u /**< enable timeout */ -#define SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN 3u /**< rx tx exchange and enable timeout */ - -/** - * @brief sei instruction jump intructions index - */ -#define SEI_JUMP_INIT_INSTR_IDX 0x00u /**< jump init instr index */ -#define SEI_JUMP_WDG_INSTR_IDX 0x01u /**< jump watchdog instr index */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX0 0x10u /**< jump command table instr ptr0 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX1 0x11u /**< jump command table instr ptr1 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX2 0x12u /**< jump command table instr ptr2 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX3 0x13u /**< jump command table instr ptr3 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX4 0x14u /**< jump command table instr ptr4 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX5 0x15u /**< jump command table instr ptr5 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX6 0x16u /**< jump command table instr ptr6 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX7 0x17u /**< jump command table instr ptr7 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX8 0x18u /**< jump command table instr ptr8 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX9 0x19u /**< jump command table instr ptr9 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX10 0x1Au /**< jump command table instr ptr10 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX11 0x1Bu /**< jump command table instr ptr11 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX12 0x1Cu /**< jump command table instr ptr12 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX13 0x1Du /**< jump command table instr ptr13 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX14 0x1Eu /**< jump command table instr ptr14 */ -#define SEI_JUMP_CMD_TABLE_INSTR_IDX15 0x1Fu /**< jump command table instr ptr15 */ - -/** - * @brief sei engine config structure - */ -typedef struct { - sei_arming_mode_t arming_mode; - uint8_t data_cdm_idx; - uint8_t data_base_idx; - uint8_t init_instr_idx; - bool wdg_enable; - sei_wdg_action_t wdg_action; - uint8_t wdg_instr_idx; - uint16_t wdg_time; -} sei_engine_config_t; /**< engine config struct */ - -/** - * @brief sei tranceiver synchronous master mode config structure - */ -typedef struct { - bool data_idle_high_z; - sei_idle_state_t data_idle_state; - bool clock_idle_high_z; - sei_idle_state_t clock_idle_state; - uint32_t baudrate; -} sei_tranceiver_synchronous_master_config_t; /**< tranceiver synchronous master config struct */ - -/** - * @brief sei tranceiver synchronous master mode config structure - */ -typedef struct { - bool data_idle_high_z; - sei_idle_state_t data_idle_state; - bool clock_idle_high_z; - sei_idle_state_t clock_idle_state; - uint32_t max_baudrate; - uint16_t ck0_timeout_us; - uint16_t ck1_timeout_us; -} sei_tranceiver_synchronous_slave_config_t; /**< tranceiver synchronous slave config struct */ - -/** - * @brief sei tranceiver asynchronous mode config structure - */ -typedef struct { - uint8_t wait_len; - uint8_t data_len; - bool parity_enable; - sei_asynchronous_parity_t parity; - bool data_idle_high_z; - sei_idle_state_t data_idle_state; - uint32_t baudrate; -} sei_tranceiver_asynchronous_config_t; /**< tranceiver asynchronous config struct */ - -/** - * @brief sei tranceiver config structure - */ -typedef struct { - sei_tranceiver_mode_t mode; - bool tri_sample; - uint32_t src_clk_freq; - sei_tranceiver_synchronous_master_config_t synchronous_master_config; - sei_tranceiver_synchronous_slave_config_t synchronous_slave_config; - sei_tranceiver_asynchronous_config_t asynchronous_config; -} sei_tranceiver_config_t; /**< tranceiver config struct */ - -/** - * @brief sei trigger input config structure - */ -typedef struct { - bool trig_in0_enable; - uint8_t trig_in0_select; - bool trig_in1_enable; - uint8_t trig_in1_select; - bool trig_period_enable; - sei_arming_mode_t trig_period_arming_mode; - bool trig_period_sync_enable; - uint8_t trig_period_sync_select; - uint32_t trig_period_time; -#if defined(HPM_IP_FEATURE_SEI_TIMEOUT_REWIND_FEATURE) && HPM_IP_FEATURE_SEI_TIMEOUT_REWIND_FEATURE - uint8_t rewind_enable; - uint8_t rewind_select; -#endif -} sei_trigger_input_config_t; /**< trigger input config struct */ - -/** - * @brief sei trigger output config structure - */ -typedef struct { - uint8_t src_latch_select; - bool trig_out_enable; - uint8_t trig_out_select; -} sei_trigger_output_config_t; /**< trigger output config struct */ - -/** - * @brief sei data format config structure - */ -typedef struct { - sei_data_mode_t mode; - bool signed_flag; - sei_data_bit_order_t bit_order; - sei_data_word_order_t word_order; - uint8_t word_len; - bool crc_invert; - bool crc_shift_mode; - uint8_t crc_len; - uint8_t last_bit; - uint8_t first_bit; - uint8_t max_bit; - uint8_t min_bit; - uint32_t gold_value; - uint32_t crc_init_value; - uint32_t crc_poly; -} sei_data_format_config_t; /**< cmd or data format config struct */ - -/** - * @brief sei command table config structure - */ -typedef struct { - uint32_t cmd_min_value; - uint32_t cmd_max_value; - uint32_t cmd_mask_value; - uint8_t instr_idx[16]; -} sei_command_table_config_t; /**< cmd table config struct */ - -/** - * @brief sei state transition config structure - */ -typedef struct { - bool disable_instr_ptr_check; - sei_state_tran_condition_t instr_ptr_cfg; - uint8_t instr_ptr_value; - bool disable_clk_check; - sei_state_tran_condition_t clk_cfg; - bool disable_txd_check; - sei_state_tran_condition_t txd_cfg; - bool disable_rxd_check; - sei_state_tran_condition_t rxd_cfg; - bool disable_timeout_check; - sei_state_tran_condition_t timeout_cfg; -} sei_state_transition_config_t; /**< state transition config struct */ - -/** - * @brief sei state transition latch config structure - */ -typedef struct { - bool enable; - uint8_t output_select; - uint16_t delay; -} sei_state_transition_latch_config_t; /**< state transition latch config struct */ - -/** - * @brief sei sample config structure - */ -typedef struct { - uint8_t acc_data_idx; - uint8_t spd_data_idx; - uint8_t rev_data_idx; - uint8_t pos_data_idx; - bool acc_data_use_rx; /**< true - use rx data, false - use override data */ - bool spd_data_use_rx; /**< true - use rx data, false - use override data */ - bool rev_data_use_rx; /**< true - use rx data, false - use override data */ - bool pos_data_use_rx; /**< true - use rx data, false - use override data */ - uint8_t latch_select; - bool sample_once; - uint16_t sample_window; - uint32_t data_register_select; -} sei_sample_config_t; /**< sample config struct */ - -/** - * @brief sei update config structure - */ -typedef struct { - uint8_t acc_data_idx; - uint8_t spd_data_idx; - uint8_t rev_data_idx; - uint8_t pos_data_idx; - bool acc_data_use_rx; /**< true - use rx data, false - use override data */ - bool spd_data_use_rx; /**< true - use rx data, false - use override data */ - bool rev_data_use_rx; /**< true - use rx data, false - use override data */ - bool pos_data_use_rx; /**< true - use rx data, false - use override data */ - bool time_use_override; /**< true - use override data, false - use timestamp data */ - bool update_on_err; - uint8_t latch_select; - uint32_t data_register_select; -} sei_update_config_t; /**< update config struct */ - - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Set the SEI engine enable or disable - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void sei_set_engine_enable(SEI_Type *ptr, uint8_t idx, bool enable) -{ - if (enable) { - ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_ENABLE_MASK; - } else { - ptr->CTRL[idx].ENGINE.CTRL &= ~SEI_CTRL_ENGINE_CTRL_ENABLE_MASK; - } -} - -/** - * @brief Rewind the SEI engine - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - */ -static inline void sei_set_engine_rewind(SEI_Type *ptr, uint8_t idx) -{ - ptr->CTRL[idx].ENGINE.CTRL |= SEI_CTRL_ENGINE_CTRL_REWIND_MASK; -} - -/** - * @brief Set the SEI trigger input trig in0 enable or disable - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void sei_set_trig_input_in0_enable(SEI_Type *ptr, uint8_t idx, bool enable) -{ - if (enable) { - ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK; - } else { - ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK; - } -} - -/** - * @brief Set the SEI trigger input trig in1 enable or disable - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void sei_set_trig_input_in1_enable(SEI_Type *ptr, uint8_t idx, bool enable) -{ - if (enable) { - ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK; - } else { - ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK; - } -} - -/** - * @brief Set the SEI trigger input period enable or disable - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void sei_set_trig_input_period_enable(SEI_Type *ptr, uint8_t idx, bool enable) -{ - if (enable) { - ptr->CTRL[idx].TRG.IN_CFG |= SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK; - } else { - ptr->CTRL[idx].TRG.IN_CFG &= ~SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK; - } -} - -/** - * @brief Set the SEI trigger input soft enable or disable - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @arg true enable - * @arg false disable - */ -static inline void sei_set_trig_input_soft_enable(SEI_Type *ptr, uint8_t idx) -{ - ptr->CTRL[idx].TRG.SW |= SEI_CTRL_TRG_SW_SOFT_MASK; -} - -/** - * @brief Set the SEI trigger input command value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] type trigger input type @ref sei_trig_in_type_t - * @param [in] data command data - */ -static inline void sei_set_trig_input_command_value(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type, uint32_t data) -{ - ptr->CTRL[idx].TRG_TABLE.CMD[type] = data; -} - -/** - * @brief Get the SEI trigger input time - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] type trigger input type @ref sei_trig_in_type_t - * @retval trigger input time - */ -static inline uint32_t sei_get_trig_input_time(SEI_Type *ptr, uint8_t idx, sei_trig_in_type_t type) -{ - return ptr->CTRL[idx].TRG_TABLE.TIME[type]; -} - -/** - * @brief Get the SEI latch time - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] latch_idx - * @arg SEI_LATCH_0 - * @arg SEI_LATCH_1 - * @arg SEI_LATCH_2 - * @arg SEI_LATCH_3 - * @retval latch time - */ -static inline uint32_t sei_get_latch_time(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx) -{ - return ptr->CTRL[idx].LATCH[latch_idx].TIME; -} - -/** - * @brief Set the SEI tranceiver rx point - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] point rx point value - */ -static inline void sei_set_xcvr_rx_point(SEI_Type *ptr, uint8_t idx, uint16_t point) -{ - uint32_t tmp; - - assert(point > 0); - tmp = ptr->CTRL[idx].XCVR.DATA_CFG; - tmp &= ~SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK; - tmp |= SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(point); - ptr->CTRL[idx].XCVR.DATA_CFG = tmp; -} - -/** - * @brief Set the SEI tranceiver tx point - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] point tx point value - */ -static inline void sei_set_xcvr_tx_point(SEI_Type *ptr, uint8_t idx, uint16_t point) -{ - uint32_t tmp; - - assert(point > 0); - tmp = ptr->CTRL[idx].XCVR.DATA_CFG; - tmp &= ~SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK; - tmp |= SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(point); - ptr->CTRL[idx].XCVR.DATA_CFG = tmp; -} - -/** - * @brief Set the SEI tranceiver ck0 point - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] point ck0 point value - */ -static inline void sei_set_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx, uint16_t point) -{ - uint32_t tmp; - - assert(point > 0); - tmp = ptr->CTRL[idx].XCVR.CLK_CFG; - tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK; - tmp |= SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(point); - ptr->CTRL[idx].XCVR.CLK_CFG = tmp; -} - -/** - * @brief Set the SEI tranceiver ck1 point - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] point ck1 point value - */ -static inline void sei_set_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx, uint16_t point) -{ - uint32_t tmp; - - assert(point > 0); - tmp = ptr->CTRL[idx].XCVR.CLK_CFG; - tmp &= ~SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK; - tmp |= SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(point); - ptr->CTRL[idx].XCVR.CLK_CFG = tmp; -} - -/** - * @brief Get the SEI tranceiver ck0 point - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @retval ck0 point value - */ -static inline uint16_t sei_get_xcvr_ck0_point(SEI_Type *ptr, uint8_t idx) -{ - return SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG); -} - -/** - * @brief Get the SEI tranceiver ck1 point - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @retval ck1 point value - */ -static inline uint16_t sei_get_xcvr_ck1_point(SEI_Type *ptr, uint8_t idx) -{ - return SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(ptr->CTRL[idx].XCVR.CLK_CFG); -} - -/** - * @brief Set the SEI command value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] cmd command value - */ -static inline void sei_set_command_value(SEI_Type *ptr, uint8_t idx, uint32_t cmd) -{ - ptr->CTRL[idx].CMD.CMD = cmd; -} - -/** - * @brief Get the SEI command value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @retval command value - */ -static inline uint32_t sei_get_command_value(SEI_Type *ptr, uint8_t idx) -{ - return ptr->CTRL[idx].CMD.CMD; -} - -/** - * @brief Rewind the SEI command - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - */ -static inline void sei_set_command_rewind(SEI_Type *ptr, uint8_t idx) -{ - ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK; -} - -/** - * @brief Set the SEI data value - * @param [in] ptr SEI base address - * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. - * @param [in] data data value - */ -static inline void sei_set_data_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->DAT[idx].DATA = data; -} - -/** - * @brief Get the SEI data value - * @param [in] ptr SEI base address - * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. - * @retval data value - */ -static inline uint32_t sei_get_data_value(SEI_Type *ptr, uint8_t idx) -{ - return ptr->DAT[idx].DATA; -} - -/** - * @brief Rewind the SEI data - * @param [in] ptr SEI base address - * @param [in] idx SEI data index, such as SEI_DAT_2, SEI_DAT_3, etc. - */ -static inline void sei_set_data_rewind(SEI_Type *ptr, uint8_t idx) -{ - ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK; -} - -/** - * @brief Set the SEI sample position (singleturn) override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data position (singleturn) override value - */ -static inline void sei_set_sample_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.SMP_POS = data; -} - -/** - * @brief Set the SEI sample revolution (multiturn) override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data revolution (multiturn) override value - */ -static inline void sei_set_sample_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.SMP_REV = data; -} - -/** - * @brief Set the SEI sample speed override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data speed override value - */ -static inline void sei_set_sample_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.SMP_SPD = data; -} - -/** - * @brief Set the SEI sample acceleration override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data acceleration override value - */ -static inline void sei_set_sample_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.SMP_ACC = data; -} - -/** - * @brief Set the SEI update position (singleturn) override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data position (singleturn) override value - */ -static inline void sei_set_update_pos_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.UPD_POS = data; -} - -/** - * @brief Set the SEI update revolution (multiturn) override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data revolution (multiturn) override value - */ -static inline void sei_set_update_rev_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.UPD_REV = data; -} - -/** - * @brief Set the SEI update speed override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data speed override value - */ -static inline void sei_set_update_spd_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.UPD_SPD = data; -} - -/** - * @brief Set the SEI update acceleration override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data acceleration override value - */ -static inline void sei_set_update_acc_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.UPD_ACC = data; -} - -/** - * @brief Set the SEI update time override value - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] data time override value - */ -static inline void sei_set_update_time_override_value(SEI_Type *ptr, uint8_t idx, uint32_t data) -{ - ptr->CTRL[idx].POS.UPD_TIME = data; -} - -/** - * @brief Set the SEI irq match pointer0 - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] instr_idx match instr0 index - */ -static inline void sei_set_irq_match_instr0_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx) -{ - ptr->CTRL[idx].IRQ.POINTER0 = SEI_CTRL_IRQ_POINTER0_POINTER_SET(instr_idx); -} - -/** - * @brief Set the SEI irq match pointer1 - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] instr_idx match instr1 index - */ -static inline void sei_set_irq_match_instr1_ptr(SEI_Type *ptr, uint8_t idx, uint8_t instr_idx) -{ - ptr->CTRL[idx].IRQ.POINTER1 = SEI_CTRL_IRQ_POINTER1_POINTER_SET(instr_idx); -} - -/** - * @brief Set the SEI irq match instr0 - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] instr_value match instr0 value - */ -static inline void sei_set_irq_match_instr0_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value) -{ - ptr->CTRL[idx].IRQ.INSTR0 = SEI_CTRL_IRQ_INSTR0_INSTR_SET(instr_value); -} - -/** - * @brief Set the SEI irq match instr1 - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] instr_value match instr1 value - */ -static inline void sei_set_irq_match_instr1_value(SEI_Type *ptr, uint8_t idx, uint32_t instr_value) -{ - ptr->CTRL[idx].IRQ.INSTR1 = SEI_CTRL_IRQ_INSTR1_INSTR_SET(instr_value); -} - -/** - * @brief Set the SEI irq enable or disable - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] irq_mask irq mask, @ref sei_irq_event_t - * @param [in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void sei_set_irq_enable(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask, bool enable) -{ - if (enable) { - ptr->CTRL[idx].IRQ.INT_EN |= irq_mask; - } else { - ptr->CTRL[idx].IRQ.INT_EN &= ~irq_mask; - } -} - -/** - * @brief Get the SEI irq status - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] irq_mask irq mask, @ref sei_irq_event_t - * - * @retval true-has irq req, false-no irq req. - */ -static inline bool sei_get_irq_status(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask) -{ - return ((ptr->CTRL[idx].IRQ.INT_FLAG & irq_mask) == irq_mask) ? true : false; -} - -/** - * @brief Clear the SEI irq flag - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] irq_mask irq mask, @ref sei_irq_event_t - */ -static inline void sei_clear_irq_flag(SEI_Type *ptr, uint8_t idx, uint32_t irq_mask) -{ - ptr->CTRL[idx].IRQ.INT_FLAG = irq_mask; -} - -/** - * @brief Init SEI tranceiver configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] config tranceiver configuration @ref sei_tranceiver_config_t - * @retval API execution status - */ -hpm_stat_t sei_tranceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_tranceiver_config_t *config); - -/** - * @brief Init SEI command or data format configuration - * @param [in] ptr SEI base address - * @param [in] cmd_data_select - * @arg @ref SEI_SELECT_CMD select command - * @arg @ref SEI_SELECT_DATA select data - * @param [in] idx SEI ctrl index or data index, decided by cmd_data_select, such as SEI_CTRL_0, SEI_CTRL_1, SEI_DAT_2, SEI_DAT_3, etc. - * @param [in] config command or data format configuration @ref sei_data_format_config_t - * @retval API execution status - */ -hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config); - -/** - * @brief Init SEI command table configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] table_idx command table index, 0 - 7 - * @param [in] config command table configuration @ref sei_command_table_config_t - * @retval API execution status - */ -hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config); - -/** - * @brief Init SEI state transition configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] latch_idx latch index - * @arg SEI_LATCH_0 - * @arg SEI_LATCH_1 - * @arg SEI_LATCH_2 - * @arg SEI_LATCH_3 - * @param [in] state transition state - * @arg SEI_CTRL_LATCH_TRAN_0_1 - * @arg SEI_CTRL_LATCH_TRAN_1_2 - * @arg SEI_CTRL_LATCH_TRAN_2_3 - * @arg SEI_CTRL_LATCH_TRAN_3_0 - * @param [in] config state transition configuration @ref sei_state_transition_config_t - * @retval API execution status - */ -hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config); - -/** - * @brief Init SEI state transition latch configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] latch_idx latch index - * @arg SEI_LATCH_0 - * @arg SEI_LATCH_1 - * @arg SEI_LATCH_2 - * @arg SEI_LATCH_3 - * @param [in] config state transition latch configuration @ref sei_state_transition_latch_config_t - * @retval API execution status - */ -hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config); - -/** - * @brief Init SEI sample configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] config sample configuration @ref sei_sample_config_t - * @retval API execution status - */ -hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config); - -/** - * @brief Init SEI update configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] config update configuration @ref sei_update_config_t - * @retval API execution status - */ -hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config); - -/** - * @brief Init SEI trigger input configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] config trigger input configuration @ref sei_trigger_input_config_t - * @retval API execution status - */ -hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config); - -/** - * @brief Init SEI trigger output configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] config trigger output configuration @ref sei_trigger_output_config_t - * @retval API execution status - */ -hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config); - -/** - * @brief Init SEI engine configuration - * @param [in] ptr SEI base address - * @param [in] idx SEI ctrl index, such as SEI_CTRL_0, SEI_CTRL_1, etc. - * @param [in] config engine configuration @ref sei_engine_config_t - * @retval API execution status - */ -hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config); - -/** - * @brief Set SEI Intsructions - * @param [in] ptr SEI base address - * @param [in] idx SEI instruction index. - * @param [in] op SEI instruction operation - * @arg @ref SEI_INSTR_OP_HALT - * @arg @ref SEI_INSTR_OP_JUMP - * @arg @ref SEI_INSTR_OP_SEND_WDG - * @arg @ref SEI_INSTR_OP_SEND - * @arg @ref SEI_INSTR_OP_WAIT_WDG - * @arg @ref SEI_INSTR_OP_WAIT - * @arg @ref SEI_INSTR_OP_RECV_WDG - * @arg @ref SEI_INSTR_OP_RECV - * @param [in] ck SEI instruction clock - * [1] synchronous master clock type - * @arg @ref SEI_INSTR_M_CK_LOW - * @arg @ref SEI_INSTR_M_CK_RISE_FALL - * @arg @ref SEI_INSTR_M_CK_FALL_RISE - * @arg @ref SEI_INSTR_M_CK_HIGH - * [2] synchronous slave clock type - * @arg @ref SEI_INSTR_S_CK_DEFAULT - * @arg @ref SEI_INSTR_S_CK_TRX_EXCH - * @arg @ref SEI_INSTR_S_CK_TIMEOUT_EN - * @arg @ref SEI_INSTR_S_CK_TRX_EXCH_TIMEOUT_EN - * @param [in] crc SEI instruction crc register, such as SEI_DAT_0, SEI_DAT_1, etc. - * @param [in] data SEI instruction data register, such as SEI_DAT_0, SEI_DAT_1, etc. - * @param [in] opr SEI instruction operand. - * [1] When OP is SEI_INSTR_OP_HALT, opr is the halt time in baudrate, 0 represents infinite time. - * [2] When OP is SEI_INSTR_OP_JUMP, opr is command table pointer, init pointer or wdg pointer. - * @arg @ref SEI_JUMP_INIT_INSTR_IDX - * @arg @ref SEI_JUMP_WDG_INSTR_IDX - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX0 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX1 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX2 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX3 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX4 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX5 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX6 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX7 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX8 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX9 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX10 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX11 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX12 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX13 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX14 - * @arg @ref SEI_JUMP_CMD_TABLE_INSTR_IDX15 - * [3] Other OP, this area is the data length. - */ -void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr); - - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_smix_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_smix_drv.h deleted file mode 100644 index 597741d05fd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_smix_drv.h +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SMIX_DRV_H -#define HPM_SMIX_DRV_H - -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_smix_regs.h" -#include - -/** - * @brief SMIX driver APIs - * @defgroup smix_interface SMIX driver APIs - * @ingroup smix_interfaces - * @{ - */ - -typedef enum { - smix_dma_transfer_burst_1t = 0U, - smix_dma_transfer_burst_2t = 1U, - smix_dma_transfer_burst_4t = 2U, - smix_dma_transfer_burst_8t = 3U, - smix_dma_transfer_burst_16t = 4U, - smix_dma_transfer_burst_32t = 5U, - smix_dma_transfer_burst_64t = 6U, - smix_dma_transfer_burst_128t = 7U, -} smix_dma_transfer_burst_t; - -typedef enum { - smix_dma_transfer_byte = 0U, - smix_dma_transfer_half_word = 1U, - smix_dma_transfer_word = 2U, -} smix_dma_transfer_width_t; - -typedef enum { - smix_dma_address_increment = 0U, - smix_dma_address_decrement = 1U, - smix_dma_address_fixed = 2U -} smix_dma_address_control_t; - -typedef enum { - smix_dma_mode_normal = 0, - smix_dma_mode_handshake = 1, -} smix_dma_handshake_mode_t; - -typedef enum { - smix_dma_req_i2s0_rx = 6, - smix_dma_req_i2s0_tx = 7, - smix_dma_req_i2s1_rx = 8, - smix_dma_req_i2s1_tx = 9, - smix_dma_req_i2s2_rx = 10, - smix_dma_req_i2s2_tx = 11, - smix_dma_req_i2s3_rx = 12, - smix_dma_req_i2s3_tx = 13, - - smix_dma_req_mixer_src_ch0 = 16, - smix_dma_req_mixer_src_ch1 = 17, - smix_dma_req_mixer_src_ch2 = 18, - smix_dma_req_mixer_src_ch3 = 19, - smix_dma_req_mixer_src_ch4 = 20, - smix_dma_req_mixer_src_ch5 = 21, - smix_dma_req_mixer_src_ch6 = 22, - smix_dma_req_mixer_src_ch7 = 23, - smix_dma_req_mixer_src_ch8 = 24, - smix_dma_req_mixer_src_ch9 = 25, - smix_dma_req_mixer_src_ch10 = 26, - smix_dma_req_mixer_src_ch11 = 27, - smix_dma_req_mixer_src_ch12 = 28, - smix_dma_req_mixer_src_ch13 = 29, - - smix_dma_req_mixer_dst_ch0 = 30, - smix_dma_req_mixer_dst_ch1 = 31, -} smix_dma_req_t; - - -typedef enum { - smix_src_clk_i2s0_bclk = 0, - smix_src_clk_i2s0_fclk = 1, - smix_src_clk_i2s0_mclk = 2, - smix_src_clk_i2s1_bclk = 3, - smix_src_clk_i2s1_fclk = 4, - smix_src_clk_i2s1_mclk = 5, - smix_src_clk_i2s2_bclk = 6, - smix_src_clk_i2s2_fclk = 7, - smix_src_clk_i2s2_mclk = 8, - smix_src_clk_i2s3_bclk = 9, - smix_src_clk_i2s3_fclk = 10, - smix_src_clk_i2s3_mclk = 11, - smix_src_clk_none = 15, -} smix_src_clk_source_t; - - -typedef struct { - uint32_t ctrl; /**< Control */ - uint32_t trans_size; /**< Transfer size in source width */ - uint32_t src_addr; /**< Source address */ - uint32_t reserved0; /**< reserved */ - uint32_t dst_addr; /**< Destination address */ - uint32_t reserved1; /**< reserved */ - uint32_t linked_ptr; /**< Linked descriptor address */ - uint32_t reserved2; /**< resetved */ -} smix_dma_linked_descriptor_t; - - -typedef struct { - uint8_t priority; /**< Channel priority */ - uint8_t src_burst_size; /**< Source burst size */ - uint8_t src_req_sel; - uint8_t dst_req_sel; - uint8_t src_mode; /**< Source work mode */ - uint8_t dst_mode; /**< Destination work mode */ - uint8_t src_width; /**< Source width */ - uint8_t dst_width; /**< Destination width */ - uint8_t src_addr_ctrl; /**< Source address control */ - uint8_t dst_addr_ctrl; /**< Destination address control */ - bool abort_int_en; /**< enable abort interrupt */ - bool error_int_en; /**< enable error interrupt */ - bool complete_int_en; /**< enable complete interrupt */ - uint32_t src_addr; /**< Source address */ - uint32_t dst_addr; /**< Destination address */ - uint32_t linked_ptr; /**< Next linked descriptor */ - uint32_t trans_bytes; /**< Total size to be transferred in byte */ -} smix_dma_ch_config_t; - -/* gain bit[14:0] */ -/* low 12 bits is fraction */ -/* high 3 bits: 1 - right shift 2; 2 - right shift 4 */ -typedef enum { - smix_mixer_gain_decrease_20db = 0x199, - smix_mixer_gain_decrease_19db = 0x1cb, - smix_mixer_gain_decrease_18db = 0x203, - smix_mixer_gain_decrease_17db = 0x242, - smix_mixer_gain_decrease_16db = 0x289, - smix_mixer_gain_decrease_15db = 0x2d8, - smix_mixer_gain_decrease_14db = 0x331, - smix_mixer_gain_decrease_13db = 0x395, - smix_mixer_gain_decrease_12db = 0x404, - smix_mixer_gain_decrease_11db = 0x482, - smix_mixer_gain_decrease_10db = 0x50f, - smix_mixer_gain_decrease_9db = 0x5ad, - smix_mixer_gain_decrease_8db = 0x65e, - smix_mixer_gain_decrease_7db = 0x725, - smix_mixer_gain_decrease_6db = 0x804, - smix_mixer_gain_decrease_5db = 0x8ff, - smix_mixer_gain_decrease_4db = 0xa18, - smix_mixer_gain_decrease_3db = 0xb53, - smix_mixer_gain_decrease_2db = 0xcb5, - smix_mixer_gain_decrease_1db = 0xe42, - smix_mixer_gain_0db = 0xfff, - smix_mixer_gain_increase_1db = 0x147c, - smix_mixer_gain_increase_2db = 0x1509, - smix_mixer_gain_increase_3db = 0x15a6, - smix_mixer_gain_increase_4db = 0x1657, - smix_mixer_gain_increase_5db = 0x171c, - smix_mixer_gain_increase_6db = 0x17fa, - smix_mixer_gain_increase_7db = 0x18f4, - smix_mixer_gain_increase_8db = 0x1a0c, - smix_mixer_gain_increase_9db = 0x1b45, - smix_mixer_gain_increase_10db = 0x1ca5, - smix_mixer_gain_increase_11db = 0x1e31, - smix_mixer_gain_increase_12db = 0x1fed, - smix_mixer_gain_increase_13db = 0x2477, - smix_mixer_gain_increase_14db = 0x2503, - smix_mixer_gain_increase_15db = 0x259f, - smix_mixer_gain_increase_16db = 0x264f, - smix_mixer_gain_increase_17db = 0x2714, - smix_mixer_gain_increase_18db = 0x27f1, - smix_mixer_gain_increase_19db = 0x28e9, - smix_mixer_gain_increase_20db = 0x2a00 -} smix_mixer_gain_t; - - -typedef enum { - smix_mixer_no_rate_convert, - smix_mixer_upper_2x_sample, - smix_mixer_upper_3x_sample, - smix_mixer_upper_4x_sample, - smix_mixer_upper_6x_sample, - smix_mixer_upper_8x_sample, - smix_mixer_upper_12x_sample, - smix_mixer_lower_2x_sample, -} smix_mixer_rate_convert_t; - -typedef struct { - bool underflow_int_en; - uint8_t fifo_thr; - bool calsat_int_en; - bool da_int_en; - bool auto_deactivate_en; - bool fadeout_done_int_en; - bool deactivate_en; - bool active_en; - bool fadeout_now_en; - bool fadeout_auto_en; - bool fadein_en; - bool channel_en; - bool mixer_en; - - uint16_t gain; - uint32_t length; - uint32_t fadein_delta; - uint32_t fadeout_delta; - uint8_t src_ch_mask; -} smix_mixer_dst_config_t; - - -typedef struct { - uint8_t fifo_thr; - bool calsat_int_en; - bool dn_int_en; - bool auto_deactivate_en; - bool fadeout_int_en; - uint8_t convert_rate; - - uint16_t gain; - uint32_t fadein_delta; - uint32_t fadeout_delta; - uint32_t length; -} smix_mixer_source_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief smix dma check transfer complete status - * - * @param [in] ptr SMIX base address - * @param [in] ch_index dma channel - * @retval true for transfer complete - */ -static inline bool smix_dma_check_transfer_complete(SMIX_Type *ptr, uint8_t ch_index) -{ - if ((SMIX_DMAC_TC_ST_CH_GET(ptr->DMAC_TC_ST) & (1U << ch_index)) != 0) { - ptr->DMAC_TC_ST = (1U << ch_index); /* W1C clear status*/ - return true; - } - return false; -} - -/** - * @brief smix dma check transfer abort status - * - * @param [in] ptr SMIX base address - * @param [in] ch_index dma channel - * @retval true for transfer abort - */ -static inline bool smix_dma_check_transfer_abort(SMIX_Type *ptr, uint8_t ch_index) -{ - if ((SMIX_DMAC_ABRT_ST_CH_GET(ptr->DMAC_ABRT_ST) & (1U << ch_index)) != 0) { - ptr->DMAC_ABRT_ST = (1U << ch_index); /* W1C clear status*/ - return true; - } - return false; -} - -/** - * @brief smix dma check transfer error status - * - * @param [in] ptr SMIX base address - * @param [in] ch_index dma channel - * @retval true for transfer error - */ -static inline bool smix_dma_check_transfer_error(SMIX_Type *ptr, uint8_t ch_index) -{ - if ((SMIX_DMAC_ERR_ST_CH_GET(ptr->DMAC_ERR_ST) & (1U << ch_index)) != 0) { - ptr->DMAC_ERR_ST = (1U << ch_index); /* W1C clear status*/ - return true; - } - return false; -} - -/** - * @brief smix mixer enable source channel for dst - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @param [in] source_ch_mask source channel mask - */ -static inline void smix_mixer_dst_enable_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) -{ - ptr->DST_CH[dst_ch].SOURCE_EN |= source_ch_mask; -} - -/** - * @brief smix mixer disable source channel for dst - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @param [in] source_ch_mask source channel mask - */ -static inline void smix_mixer_dst_disable_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) -{ - ptr->DST_CH[dst_ch].SOURCE_EN &= ~source_ch_mask; -} - -/** - * @brief smix mixer active source channel for dst - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @param [in] source_ch_mask source channel mask - */ -static inline void smix_mixer_dst_active_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) -{ - ptr->DST_CH[dst_ch].SOURCE_ACT |= source_ch_mask; -} - -/** - * @brief smix mixer deactive source channel for dst - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @param [in] source_ch_mask source channel mask - */ -static inline void smix_mixer_dst_deactive_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) -{ - ptr->DST_CH[dst_ch].SOURCE_DEACT |= source_ch_mask; -} - -/** - * @brief smix mixer fadein source channel for dst - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @param [in] source_ch_mask source channel mask - */ -static inline void smix_mixer_dst_fadein_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) -{ - ptr->DST_CH[dst_ch].SOURCE_FADEIN_CTRL |= source_ch_mask; -} - -/** - * @brief smix mixer fadeout source channel for dst - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @param [in] source_ch_mask source channel mask - */ -static inline void smix_mixer_dst_fadeout_source_channel(SMIX_Type *ptr, uint8_t dst_ch, uint32_t source_ch_mask) -{ - ptr->DST_CH[dst_ch].SOURCE_MFADEOUT_CTRL |= source_ch_mask; -} - -/** - * @brief smix mixer enable dst channel - * - * @param [in] ptr SMIX base address - * - * @note two dst channel share same enable bit in DST_CH[0].CTRL.MIXER_EN, DST_CH[1].CTRL.MIXER_EN should not be set - */ -static inline void smix_mixer_dst_enable(SMIX_Type *ptr) -{ - ptr->DST_CH[0].CTRL |= SMIX_DST_CH_CTRL_DST_EN_MASK; - ptr->DST_CH[1].CTRL &= ~SMIX_DST_CH_CTRL_DST_EN_MASK; -} - -/** - * @brief smix mixer disable dst channel - * - * @param [in] ptr SMIX base address - * - * @note two dst channel share same enable bit in DST_CH[0].CTRL.MIXER_EN, DST_CH[1].CTRL.MIXER_EN should not be set - */ -static inline void smix_mixer_dst_disable(SMIX_Type *ptr) -{ - ptr->DST_CH[0].CTRL &= ~SMIX_DST_CH_CTRL_DST_EN_MASK; -} - -/** - * @brief smix mixer get calculate saturation register value - * - * @param [in] ptr SMIX base address - * @retval calculate saturation register value - */ -static inline uint32_t smix_mixer_get_calsat_status(SMIX_Type *ptr) -{ - return ptr->CALSAT_ST; -} - -/** - * @brief smix mixer check dst channel calculate saturation error - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @retval true for calculate saturation error occurred - */ -static inline bool smix_mixer_check_dst_cal_saturation_error(SMIX_Type *ptr, uint8_t dst_ch) -{ - return ((SMIX_CALSAT_ST_DST_GET(ptr->CALSAT_ST) & (1U << dst_ch)) != 0) ? true : false; -} - -/** - * @brief smix mixer check source channel calculate saturation error - * - * @param [in] ptr SMIX base address - * @param [in] source_ch source channel - * @retval true for calculate saturation error occurred - */ -static inline bool smix_mixer_check_source_cal_saturation_error(SMIX_Type *ptr, uint8_t source_ch) -{ - return ((SMIX_CALSAT_ST_SRC_GET(ptr->CALSAT_ST) & (1U << source_ch)) != 0) ? true : false; -} - -/** - * @brief smix mixer check dst channel data ubderflew - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @retval true for data underflew - */ -static inline bool smix_mixer_check_dst_data_underflew(SMIX_Type *ptr, uint8_t dst_ch) -{ - return ((SMIX_DATA_ST_DST_UNDL_GET(ptr->DATA_ST) & (1U << dst_ch)) != 0) ? true : false; -} - -/** - * @brief smix mixer check dst channel data available - * - * @param [in] ptr SMIX base address - * @param [in] dst_ch dst channel - * @retval true for data available - */ -static inline bool smix_mixer_check_dst_data_available(SMIX_Type *ptr, uint8_t dst_ch) -{ - return ((SMIX_DATA_ST_DST_DA_GET(ptr->DATA_ST) & (1U << dst_ch)) != 0) ? true : false; -} - -/** - * @brief smix mixer check source channel data available - * - * @param [in] ptr SMIX base address - * @param [in] source_ch source channel - * @retval true for source channel need new data - */ -static inline bool smix_mixer_check_source_data_needed(SMIX_Type *ptr, uint8_t source_ch) -{ - return ((SMIX_DATA_ST_SRC_DN_GET(ptr->DATA_ST) & (1U << source_ch)) != 0) ? true : false; -} - -/** - * @brief smix mixer config dst channel fadein delta - * - * @param [in] ptr SMIX base address - * @param [in] ch dst channel - * @param [in] target_sample_rate target sample rate - * @param [in] ms fadein consumed time in ms - * @retval status_success if no error occurs - */ -hpm_stat_t smix_mixer_config_dst_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); - -/** - * @brief smix mixer config dst channel fadeout delta - * - * @param [in] ptr SMIX base address - * @param [in] ch dst channel - * @param [in] target_sample_rate target sample rate - * @param [in] ms fadeout consumed time in ms - * @retval status_success if no error occurs - */ -hpm_stat_t smix_mixer_config_dst_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); - -/** - * @brief smix mixer config source channel fadein delta - * - * @param [in] ptr SMIX base address - * @param [in] ch source channel - * @param [in] target_sample_rate target sample rate - * @param [in] ms fadein consumed time in ms - * @retval status_success if no error occurs - */ -hpm_stat_t smix_mixer_config_source_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); - -/** - * @brief smix mixer config source channel fadeout delta - * - * @param [in] ptr SMIX base address - * @param [in] ch source channel - * @param [in] target_sample_rate target sample rate - * @param [in] ms fadeout consumed time in ms - * @retval status_success if no error occurs - */ -hpm_stat_t smix_mixer_config_source_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms); - -/** - * @brief smix get dma channel default config - * - * @param [in] ptr SMIX base address - * @param [in] config smix_dma_ch_config_t - */ -void smix_get_dma_default_ch_config(SMIX_Type *ptr, smix_dma_ch_config_t *config); - -/** - * @brief smix get dst channel default config - * - * @param [in] ptr SMIX base address - * @param [in] config smix_mixer_dst_config_t - */ -void smix_get_mixer_dst_ch_default_config(SMIX_Type *ptr, smix_mixer_dst_config_t *config); - -/** - * @brief smix get source channel default config - * - * @param [in] ptr SMIX base address - * @param [in] config smix_mixer_source_config_t - */ -void smix_get_mixer_source_ch_default_config(SMIX_Type *ptr, smix_mixer_source_config_t *config); - -/** - * @brief smix config dma channel - * - * @param [in] ptr SMIX base address - * @param [in] ch dma channel - * @param [in] config smix_dma_ch_config_t - * @param [in] start true for start dma - * @retval status_success if no error occurs - */ -hpm_stat_t smix_config_dma_channel(SMIX_Type *ptr, uint8_t ch, smix_dma_ch_config_t *config, bool start); - -/** - * @brief smix mixer config source channel - * - * @param [in] ptr SMIX base address - * @param [in] ch source channel - * @param [in] src smix_mixer_source_config_t - * @retval status_success if no error occurs - */ -hpm_stat_t smix_mixer_config_source_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_source_config_t *src); - -/** - * @brief smix mixer config dst channel - * - * @param [in] ptr SMIX base address - * @param [in] ch dst channel - * @param [in] dst smix_mixer_dst_config_t - * @retval status_success if no error occurs - */ -hpm_stat_t smix_mixer_config_dst_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_dst_config_t *dst); - -/** - * @brief smix mixer config source channel gain - * - * @param [in] ptr SMIX base address - * @param [in] ch_index source channel - * @param [in] gain smix_mixer_gain_t - */ -static inline void smix_set_source_gain(SMIX_Type *ptr, uint8_t ch_index, smix_mixer_gain_t gain) -{ - ptr->SOURCE_CH[ch_index].GAIN = SMIX_SOURCE_CH_GAIN_VAL_SET(gain); -} - -/** - * @brief smix mixer config dst channel gain - * - * @param [in] ptr SMIX base address - * @param [in] ch_index dst channel - * @param [in] gain smix_mixer_gain_t - */ -static inline void smix_set_dst_gain(SMIX_Type *ptr, uint8_t ch_index, smix_mixer_gain_t gain) -{ - ptr->DST_CH[ch_index].GAIN = SMIX_DST_CH_GAIN_VAL_SET(gain); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_SMIX_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h deleted file mode 100644 index 39d171f2be2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_spi_drv.h +++ /dev/null @@ -1,1212 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SPI_DRV_H -#define HPM_SPI_DRV_H -#include "hpm_spi_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief SPI driver APIs - * @defgroup spi_interface SPI driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief spi dma enable - */ -typedef enum { - spi_tx_dma_enable = SPI_CTRL_TXDMAEN_MASK, - spi_rx_dma_enable = SPI_CTRL_RXDMAEN_MASK -} spi_dma_enable_t; - -/** - * @brief spi interrupt mask - */ -typedef enum { - spi_rx_fifo_overflow_int = SPI_INTREN_RXFIFOORINTEN_MASK, - spi_tx_fifo_underflow_int = SPI_INTREN_TXFIFOURINTEN_MASK, - spi_rx_fifo_threshold_int = SPI_INTREN_RXFIFOINTEN_MASK, - spi_tx_fifo_threshold_int = SPI_INTREN_TXFIFOINTEN_MASK, - spi_end_int = SPI_INTREN_ENDINTEN_MASK, - spi_slave_cmd_int = SPI_INTREN_SLVCMDEN_MASK, -} spi_interrupt_t; - -/** - * @brief spi mode selection - */ -typedef enum { - spi_master_mode = 0, - spi_slave_mode -} spi_mode_selection_t; - -/** - * @brief spi clock polarity - */ -typedef enum { - spi_sclk_low_idle = 0, - spi_sclk_high_idle -} spi_sclk_idle_state_t; - -/** - * @brief spi clock phase - */ -typedef enum { - spi_sclk_sampling_odd_clk_edges = 0, - spi_sclk_sampling_even_clk_edges -} spi_sclk_sampling_clk_edges_t; - -/** - * @brief spi cs to sclk edge duration - */ -typedef enum { - spi_cs2sclk_half_sclk_1 = 0, - spi_cs2sclk_half_sclk_2, - spi_cs2sclk_half_sclk_3, - spi_cs2sclk_half_sclk_4 -} spi_cs2sclk_duration_t; - -/** - * @brief spi cs high level duration - */ -typedef enum { - spi_csht_half_sclk_1 = 0, - spi_csht_half_sclk_2, - spi_csht_half_sclk_3, - spi_csht_half_sclk_4, - spi_csht_half_sclk_5, - spi_csht_half_sclk_6, - spi_csht_half_sclk_7, - spi_csht_half_sclk_8, - spi_csht_half_sclk_9, - spi_csht_half_sclk_10, - spi_csht_half_sclk_11, - spi_csht_half_sclk_12, - spi_csht_half_sclk_13, - spi_csht_half_sclk_14, - spi_csht_half_sclk_15, - spi_csht_half_sclk_16, -} spi_csht_duration_t; - -/** - * @brief spi address phase format - */ -typedef enum { - spi_address_phase_format_single_io_mode = 0, - spi_address_phase_format_dualquad_io_mode -} spi_addr_phase_format_t; - -/** - * @brief spi transfer mode - */ -typedef enum { - spi_trans_write_read_together = 0, - spi_trans_write_only, - spi_trans_read_only, - spi_trans_write_read, - spi_trans_read_write, - spi_trans_write_dummy_read, - spi_trans_read_dummy_write, - spi_trans_no_data, - spi_trans_dummy_write, - spi_trans_dummy_read -} spi_trans_mode_t; - -/** - * @brief spi data phase format - */ -typedef enum { - spi_single_io_mode = 0, - spi_dual_io_mode, - spi_quad_io_mode, -} spi_data_phase_format_t; - -/** - * @brief spi token value - */ -typedef enum { - spi_token_value_0x00 = 0, - spi_token_value_0x69 -} spi_token_value_t; - -/** - * @brief spi dummy count - */ -typedef enum { - spi_dummy_count_1 = 0, - spi_dummy_count_2, - spi_dummy_count_3, - spi_dummy_count_4 -} spi_dummy_count_t; - -typedef enum { - msb_first = 0, - lsb_first, -} spi_shift_direction_t; - -/** - * @brief spi master interface timing config structure - */ -typedef struct { - uint32_t clk_src_freq_in_hz; - uint32_t sclk_freq_in_hz; - uint8_t cs2sclk; - uint8_t csht; -} spi_master_timing_config_t; - -/** - * @brief spi interface timing config structure - */ -typedef struct { - spi_master_timing_config_t master_config; -} spi_timing_config_t; - -/** - * @brief spi master transfer format config structure - */ -typedef struct { - uint8_t addr_len_in_bytes; -} spi_master_format_config_t; - -/** - * @brief spi common format config structure - */ -typedef struct { - uint8_t data_len_in_bits; - bool data_merge; - bool mosi_bidir; - bool lsb; - uint8_t mode; - uint8_t cpol; - uint8_t cpha; -} spi_common_format_config_t; - -/** - * @brief spi format config structure - */ -typedef struct { - spi_master_format_config_t master_config; - spi_common_format_config_t common_config; -} spi_format_config_t; - -/** - * @brief spi master transfer control config structure - */ -typedef struct { - bool cmd_enable; - bool addr_enable; - uint8_t addr_phase_fmt; - bool token_enable; - uint8_t token_value; -} spi_master_control_config_t; - -/** - * @brief spi slave transfer control config structure - */ -typedef struct { - bool slave_data_only; -} spi_slave_control_config_t; - -/** - * @brief spi common transfer control config structure - */ -typedef struct { - bool tx_dma_enable; - bool rx_dma_enable; - uint8_t trans_mode; - uint8_t data_phase_fmt; - uint8_t dummy_cnt; -#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) - uint8_t cs_index; -#endif -} spi_common_control_config_t; /*!< value in spi_cs_index_t */ - -/** - * @brief spi control config structure - */ -typedef struct { - spi_master_control_config_t master_config; - spi_slave_control_config_t slave_config; - spi_common_control_config_t common_config; -} spi_control_config_t; - -#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) -typedef enum { - spi_cs_0 = 1, - spi_cs_1 = 2, - spi_cs_2 = 4, - spi_cs_3 = 8, -} spi_cs_index_t; -#endif - -typedef enum { - addrlen_8bit = 0, - addrlen_16bit, - addrlen_24bit, - addrlen_32bit -} spi_address_len_t; - -#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1) -typedef enum { - hold_pin = 0, - wp_pin, - miso_pin, - mosi_pin, - sclk_pin, - cs_pin -} spi_directio_pin_t; - -#endif - - - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief spi master get default timing config - * - * @param [out] config spi_timing_config_t - */ -void spi_master_get_default_timing_config(spi_timing_config_t *config); - -/** - * @brief spi master get default format config - * - * @param [out] config spi_format_config_t - */ -void spi_master_get_default_format_config(spi_format_config_t *config); - -/** - * @brief spi master get default control config - * - * @param [out] config spi_control_config_t - */ -void spi_master_get_default_control_config(spi_control_config_t *config); - -/** - * @brief spi slave get default format config - * - * @param [out] config spi_format_config_t - */ -void spi_slave_get_default_format_config(spi_format_config_t *config); - -/** - * @brief spi slave get default control config - * - * @param [out] config spi_control_config_t - */ -void spi_slave_get_default_control_config(spi_control_config_t *config); - -/** - * @brief spi master timing initialization - * - * @param [in] ptr SPI base address - * @param [in] config spi_timing_config_t - * @retval hpm_stat_t status_invalid_argument or status_success - */ -hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config); - -/** - * @brief spi format initialization - * - * @param [in] ptr SPI base address - * @param [in] config spi_format_config_t - */ -void spi_format_init(SPI_Type *ptr, spi_format_config_t *config); - -/** - * @brief spi transfer - * - * @param [in] ptr SPI base address - * @param [in] config spi_control_config_t - * @param [in,out] cmd spi transfer command address - * @param [in] addr spi transfer target address - * @param [in] wbuff spi sent data buff address - * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [out] rbuff spi receive data buff address - * @param [in] rcount spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_transfer(SPI_Type *ptr, - spi_control_config_t *config, - uint8_t *cmd, uint32_t *addr, - uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount); - -/** - * @brief spi setup dma transfer - * - * @param [in] ptr SPI base address - * @param [in] config spi_control_config_t - * @param [in] cmd spi transfer command address - * @param [in] addr spi transfer target address - * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [in] rcount spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi setup dma transfer without any error - */ -hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, - spi_control_config_t *config, - uint8_t *cmd, uint32_t *addr, - uint32_t wcount, uint32_t rcount); - -/** - * @brief spi wait for idle status - * - * @note on slave mode, if CS signal is asserted, take it as busy; if SPI CS signal is de-asserted, take it as idle. - * - * @param [in] ptr SPI base address - * @retval hpm_stat_t status_success if spi in idle status - */ -hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr); - -/** - * @brief spi wait for busy status - * - * @note on slave mode, if CS signal is asserted, take it as busy; if SPI CS signal is de-asserted, take it as idle. - * - * @param [in] ptr SPI base address - * @retval hpm_stat_t status_success if spi in busy status - */ -hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr); - -/** - * @brief SPI set TX FIFO threshold - * - * This function configures SPI TX FIFO threshold. - * - * @param ptr SPI base address. - * @param threshold The FIFO threshold value, the value should not greater than FIFO size. - */ -static inline void spi_set_tx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) -{ - ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_TXTHRES_MASK) | SPI_CTRL_TXTHRES_SET(threshold); -} - -/** - * @brief SPI set RX FIFO threshold - * - * This function configures SPI RX FIFO threshold. - * - * @param ptr SPI base address. - * @param threshold The FIFO threshold value, the value should not greater than FIFO size. - */ -static inline void spi_set_rx_fifo_threshold(SPI_Type *ptr, uint32_t threshold) -{ - ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_RXTHRES_MASK) | SPI_CTRL_RXTHRES_SET(threshold); -} - -/** - * @brief Enables the SPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the SPI. The parameters are base and a DMA mask. - * - * @param ptr SPI base address. - * @param mask The dma enable mask; Use the spi_dma_enable_t. - */ -static inline void spi_enable_dma(SPI_Type *ptr, uint32_t mask) -{ - ptr->CTRL |= mask; -} - -/*! - * @brief Disables the SPI DMA request. - * - * This function configures the Rx and Tx DMA mask of the SPI. The parameters are base and a DMA mask. - * - * @param ptr SPI base address. - * @param mask The dma enable mask; Use the spi_dma_enable_t. - */ -static inline void spi_disable_dma(SPI_Type *ptr, uint32_t mask) -{ - ptr->CTRL &= ~mask; -} - -/** - * @brief Get the SPI interrupt status. - * - * This function gets interrupt status of the SPI. - * - * @param ptr SPI base address. - * @retval SPI interrupt status register value - */ -static inline uint32_t spi_get_interrupt_status(SPI_Type *ptr) -{ - return ptr->INTRST; -} - -/** - * @brief Clear the SPI interrupt status. - * - * This function clears interrupt status of the SPI. - * - * @param ptr SPI base address. - * @param mask The interrupt mask; Use the spi_interrupt_t. - * - */ -static inline void spi_clear_interrupt_status(SPI_Type *ptr, uint32_t mask) -{ - /* write 1 to clear */ - ptr->INTRST = mask; -} - -/** - * @brief Enables the SPI interrupt. - * - * This function configures interrupt of the SPI. The parameters are base and a interrupt mask. - * - * @param ptr SPI base address. - * @param mask The interrupt mask; Use the spi_interrupt_t. - */ -static inline void spi_enable_interrupt(SPI_Type *ptr, uint32_t mask) -{ - ptr->INTREN |= mask; -} - -/*! - * @brief Disables the SPI interrupt. - * - * This function configures interrupt of the SPI. The parameters are base and a interrupt mask. - * - * @param ptr SPI base address. - * @param mask The interrupt mask; Use the spi_interrupt_t. - */ -static inline void spi_disable_interrupt(SPI_Type *ptr, uint32_t mask) -{ - ptr->INTREN &= ~mask; -} - -/** - * @brief spi write and read data - * - * @note Call this function after SPI CONTROL is configured by spi_control_init. - * The order of reading and writing is controlled by spi_control_init. - * - * @param [in] ptr SPI base address - * @param [in] data_len_in_bytes data length in bytes - * @param [in] wbuff spi sent data buff address - * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [out] rbuff spi receive data buff address - * @param [in] rcount spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount); - -/** - * @brief spi read data - * - * @note Call this function after SPI CONTROL is configured by spi_control_init. - * - * @param [in] ptr SPI base address - * @param [in] data_len_in_bytes data length in bytes - * @param [out] buff spi receive data buff address - * @param [in] count spi receive data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count); - -/** - * @brief spi write data - * - * @note Call this function after SPI CONTROL is configured by spi_control_init. - * - * @param [in] ptr SPI base address - * @param [in] data_len_in_bytes data length in bytes - * @param [in] buff spi sent data buff address - * @param [in] count spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count); - -/** - * @brief spi write command - * - * Writing operations on this register will trigger SPI transfers, call this function on master mode. - * - * @param [in] ptr SPI base address - * @param [in] mode spi mode, use the spi_mode_selection_t - * @param [in] config point to spi_control_config_t - * @param [in] cmd command data address - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd); - -/** - * @brief spi read command - * - * On slave mode, the command field of the last received SPI transaction is stored in this SPI Command Register - * - * @param [in] ptr SPI base address - * @param [in] mode spi mode, use the spi_mode_selection_t - * @param [in] config point to spi_control_config_t - * @param [out] cmd command data address - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd); - -/** - * @brief spi write address - * - * @note Call this function on master mode. - * - * @param [in] ptr SPI base address - * @param [in] mode spi mode, use the spi_mode_selection_t - * @param [in] config point to spi_control_config_t - * @param [in] addr point to address - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr); - -/** - * @brief spi control initialization - * - * @param [in] ptr SPI base address - * @param [in] config point to spi_control_config_t - * @param [in] wcount spi sent data count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @param [in] rcount spi receive count, not greater than SPI_SOC_TRANSFER_COUNT_MAX - * @retval hpm_stat_t status_success if spi transfer without any error - */ -hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_t wcount, uint32_t rcount); - -/** - * @brief Get the SPI data length in bits. - * - * @param ptr SPI base address. - * @retval SPI data length in bits - */ -static inline uint8_t spi_get_data_length_in_bits(SPI_Type *ptr) -{ - return ((ptr->TRANSFMT & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) + 1; -} - -/** - * @brief Get the SPI data length in bytes. - * - * @param ptr SPI base address. - * @retval SPI data length in bytes - */ -static inline uint8_t spi_get_data_length_in_bytes(SPI_Type *ptr) -{ - return ((spi_get_data_length_in_bits(ptr) + 7U) / 8U); -} - -/** - * @brief SPI get active status. - * - * @param ptr SPI base address. - * @retval bool true for active, false for inactive - */ -static inline bool spi_is_active(SPI_Type *ptr) -{ - return ((ptr->STATUS & SPI_STATUS_SPIACTIVE_MASK) == SPI_STATUS_SPIACTIVE_MASK) ? true : false; -} - -/** - * @brief SPI enable tx dma - * - * @param ptr SPI base address - */ -static inline void spi_enable_tx_dma(SPI_Type *ptr) -{ - ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK; -} - -/** - * @brief SPI disable tx dma - * - * @param ptr SPI base address - */ -static inline void spi_disable_tx_dma(SPI_Type *ptr) -{ - ptr->CTRL &= ~SPI_CTRL_TXDMAEN_MASK; -} - -/** - * @brief SPI enable rx dma - * - * @param ptr SPI base address - */ -static inline void spi_enable_rx_dma(SPI_Type *ptr) -{ - ptr->CTRL |= SPI_CTRL_RXDMAEN_MASK; -} - -/** - * @brief SPI disable rx dma - * - * @param ptr SPI base address - */ -static inline void spi_disable_rx_dma(SPI_Type *ptr) -{ - ptr->CTRL &= ~SPI_CTRL_RXDMAEN_MASK; -} - -/** - * @brief SPI slave get sent data count - * - * @param ptr SPI base address - * @retval uint32_t data count - */ -static inline uint32_t spi_slave_get_sent_data_count(SPI_Type *ptr) -{ -#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) - return ptr->SLVDATAWCNT; -#else - return SPI_SLVDATACNT_WCNT_GET(ptr->SLVDATACNT); -#endif -} - -/** - * @brief SPI slave get received data count - * - * @param ptr SPI base address - * @retval uint32_t data count - */ -static inline uint32_t spi_slave_get_received_data_count(SPI_Type *ptr) -{ -#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) - return ptr->SLVDATARCNT; -#else - return SPI_SLVDATACNT_RCNT_GET(ptr->SLVDATACNT); -#endif -} - -/** - * @brief set spi clock phase - * - * @param [in] ptr SPI base address - * @param [in] clock_phase clock phase enum - */ -static inline void spi_set_clock_phase(SPI_Type *ptr, spi_sclk_sampling_clk_edges_t clock_phase) -{ - ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_CPHA_MASK) | SPI_TRANSFMT_CPHA_SET(clock_phase); -} - -/** - * @brief get spi clock phase - * - * @param [in] ptr SPI base address - * @retval spi_sclk_sampling_clk_edges_t spi_sclk_sampling_odd_clk_edges if CPHA is 0 - */ -static inline spi_sclk_sampling_clk_edges_t spi_get_clock_phase(SPI_Type *ptr) -{ - return (spi_sclk_sampling_clk_edges_t)SPI_TRANSFMT_CPHA_GET(ptr->TRANSFMT); -} - -/** - * @brief set spi clock polarity - * - * @param [in] ptr SPI base address - * @param [in] clock_polarity clock polarity enum - */ -static inline void spi_set_clock_polarity(SPI_Type *ptr, spi_sclk_idle_state_t clock_polarity) -{ - ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_CPOL_MASK) | SPI_TRANSFMT_CPOL_SET(clock_polarity); -} - -/** - * @brief get spi clock phase - * - * @param [in] ptr SPI base address - * @retval spi_sclk_idle_state_t spi_sclk_low_idle if CPOL is 0 - */ -static inline spi_sclk_idle_state_t spi_get_clock_polarity(SPI_Type *ptr) -{ - return (spi_sclk_idle_state_t)SPI_TRANSFMT_CPOL_GET(ptr->TRANSFMT); -} - -/** - * @brief set spi the length of each data unit in bits - * - * @param [in] ptr SPI base address - * @param [in] nbits the actual bits number of a data - * @retval hpm_stat_t status_success if spi transfer without any error - */ -static inline hpm_stat_t spi_set_data_bits(SPI_Type *ptr, uint8_t nbits) -{ - if (nbits > 32) { - return status_invalid_argument; - } else { - ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_DATALEN_MASK) | SPI_TRANSFMT_DATALEN_SET(nbits - 1); - return status_success; - } -} - -/** - * @brief SPI transmit fifo reset - * - * @param ptr SPI base address - */ -static inline void spi_transmit_fifo_reset(SPI_Type *ptr) -{ - ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK; -} - -/** - * @brief SPI receive fifo reset - * - * @param ptr SPI base address - */ -static inline void spi_receive_fifo_reset(SPI_Type *ptr) -{ - ptr->CTRL |= SPI_CTRL_RXFIFORST_MASK; -} - -/** - * @brief SPI reset - * - * @param ptr SPI base address - */ -static inline void spi_reset(SPI_Type *ptr) -{ - ptr->CTRL |= SPI_CTRL_SPIRST_MASK; -} - -/** - * @brief set spi the length of address - * - * @param [in] ptr SPI base address - * @param [in] addrlen address lenth enum - */ -static inline void spi_set_address_len(SPI_Type *ptr, spi_address_len_t addrlen) -{ - ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_ADDRLEN_MASK) | SPI_TRANSFMT_ADDRLEN_SET(addrlen); -} - -/** - * @brief Enable SPI data merge - * - * @param [in] ptr SPI base address - */ -static inline void spi_enable_data_merge(SPI_Type *ptr) -{ - ptr->TRANSFMT |= SPI_TRANSFMT_DATAMERGE_MASK; -} - -/** - * @brief Disable SPI data merge - * - * @param [in] ptr SPI base address - */ -static inline void spi_disable_data_merge(SPI_Type *ptr) -{ - ptr->TRANSFMT &= ~SPI_TRANSFMT_DATAMERGE_MASK; -} - -#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1) -/** - * @brief enable specific pin output for spi directio - * - * @note must be used spi_enable_directio API before enable output function - * - * @param [in] ptr SPI base address - * @param [in] pin spi_directio_pin_t enum - */ -hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin); - -/** - * @brief disable specific pin output for spi directio - * - * @param [in] ptr SPI base address - * @param [in] pin spi_directio_pin_t enum - */ -hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin); - -/** - * @brief write specified pin level for spi directio - * - * @param [in] ptr SPI base address - * @param [in] pin spi_directio_pin_t enum - * @param [in] high Pin level set to high when it is set to true - */ -hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high); - -/** - * @brief Read specified pin level for spi directio - * - * @param [in] ptr SPI base address - * @param pin spi_directio_pin_t enum - * - * @return Pin status - */ -uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin); - -/** - * @brief Enable SPI directIO control function - * - * @note if SPI transmission is required, the function must be disable - * - * @param [in] ptr SPI base address - */ -static inline void spi_enable_directio(SPI_Type *ptr) -{ - ptr->DIRECTIO |= SPI_DIRECTIO_DIRECTIOEN_MASK; -} - -/** - * @brief Disable SPI directIO control function - * - * @param [in] ptr SPI base address - */ -static inline void spi_disable_directio(SPI_Type *ptr) -{ - ptr->DIRECTIO &= ~SPI_DIRECTIO_DIRECTIOEN_MASK; -} - -/** - * @brief get whether spi directio function is enabled - * - * @param [in] ptr SPI base address - * - * @return if pi directio function is enable, it will return 1 - */ -static inline uint8_t spi_get_directio_enable_status(SPI_Type *ptr) -{ - return SPI_DIRECTIO_DIRECTIOEN_GET(ptr->DIRECTIO); -} - -#endif - -/** - * @brief Get valid data size in receive FIFO - * - * @param [in] ptr SPI base address - * - * @return rx fifo valid data size - */ -static inline uint8_t spi_get_rx_fifo_valid_data_size(SPI_Type *ptr) -{ - return ((SPI_STATUS_RXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_RXNUM_5_0_GET(ptr->STATUS)); -} - -/** - * @brief Get valid data size in transmit FIFO - * - * @param [in] ptr SPI base address - * - * @return tx fifo valid data size - */ -static inline uint8_t spi_get_tx_fifo_valid_data_size(SPI_Type *ptr) -{ - return ((SPI_STATUS_TXNUM_7_6_GET(ptr->STATUS) << 5) | SPI_STATUS_TXNUM_5_0_GET(ptr->STATUS)); -} - -/** - * @brief Get SPI RXFIFO size - * - * @param [in] ptr SPI base address - * - * @return RXFIFO size, the unit is word - */ -static inline uint8_t spi_get_rx_fifo_size(SPI_Type *ptr) -{ - uint8_t size = SPI_CONFIG_RXFIFOSIZE_GET(ptr->CONFIG); - return (2 << size); -} - -/** - * @brief Get SPI TXFIFO size - * - * @param [in] ptr SPI base address - * - * @return TXFIFO size, the unit is word - */ -static inline uint8_t spi_get_tx_fifo_size(SPI_Type *ptr) -{ - uint8_t size = SPI_CONFIG_TXFIFOSIZE_GET(ptr->CONFIG); - return (2 << size); -} - -/** - * @brief SPI slave enable only date mode - * - * @note This mode only works in the uni-directional regular (single) mode - * @param [in] ptr SPI base address - */ -static inline void spi_slave_enable_data_only(SPI_Type *ptr) -{ - ptr->TRANSCTRL |= SPI_TRANSCTRL_SLVDATAONLY_MASK; -} - -/** - * @brief SPI slave disable only date mode - * - * @param [in] ptr SPI base address - */ -static inline void spi_slave_disable_data_only(SPI_Type *ptr) -{ - ptr->TRANSCTRL &= ~SPI_TRANSCTRL_SLVDATAONLY_MASK; -} - -/** - * @brief SPI master enable command phase - * - * @param [in] ptr SPI base address - */ -static inline void spi_master_enable_command_phase(SPI_Type *ptr) -{ - ptr->TRANSCTRL |= SPI_TRANSCTRL_CMDEN_MASK; -} - -/** - * @brief SPI master disable command phase - * - * @param [in] ptr SPI base address - */ -static inline void spi_master_disable_command_phase(SPI_Type *ptr) -{ - ptr->TRANSCTRL &= ~SPI_TRANSCTRL_CMDEN_MASK; -} - -/** - * @brief SPI master enable address phase - * - * @param [in] ptr SPI base address - */ -static inline void spi_master_enable_address_phase(SPI_Type *ptr) -{ - ptr->TRANSCTRL |= SPI_TRANSCTRL_ADDREN_MASK; -} - -/** - * @brief SPI master disable address phase - * - * @param [in] ptr SPI base address - */ -static inline void spi_master_disable_address_phase(SPI_Type *ptr) -{ - ptr->TRANSCTRL &= ~SPI_TRANSCTRL_ADDREN_MASK; -} - -/** - * @brief SPI master set address phase format - * - * @param [in] ptr SPI base address - * @param [in] format spi_addr_phase_format_t enum - */ -static inline void spi_master_set_address_phase_format(SPI_Type *ptr, spi_addr_phase_format_t format) -{ - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_ADDRFMT_MASK) | SPI_TRANSCTRL_ADDRFMT_SET(format); -} - -/** - * @brief SPI master set transfer mode - * - * @param [in] ptr SPI base address - * @param [in] mode spi_trans_mode_t enum - */ -static inline void spi_set_transfer_mode(SPI_Type *ptr, spi_trans_mode_t mode) -{ - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_TRANSMODE_MASK) | SPI_TRANSCTRL_TRANSMODE_SET(mode); -} - -/** - * @brief SPI master enable token transfer - * - * @param [in] ptr SPI base address - */ -static inline void spi_master_enable_token_transfer(SPI_Type *ptr) -{ - ptr->TRANSCTRL |= SPI_TRANSCTRL_TOKENEN_MASK; -} - -/** - * @brief SPI master disable token transfer - * - * @param [in] ptr SPI base address - */ -static inline void spi_master_disable_token_transfer(SPI_Type *ptr) -{ - ptr->TRANSCTRL &= ~SPI_TRANSCTRL_TOKENEN_MASK; -} - -/** - * @brief SPI master set transfer count for write data - * - * @param [in] ptr SPI base address - * @param [in] count the number of units of data to be transmitted to the SPI bus from the Data - */ -static inline void spi_set_write_data_count(SPI_Type *ptr, uint32_t count) -{ -#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) - ptr->WR_TRANS_CNT = (count - 1); -#else - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_WRTRANCNT_MASK) | SPI_TRANSCTRL_WRTRANCNT_SET(count - 1); -#endif -} - -/** - * @brief SPI master set transfer count for read data - * - * @param [in] ptr SPI base address - * @param [in] count the number of units of data to be received from SPI bus and stored to the Data - */ -static inline void spi_set_read_data_count(SPI_Type *ptr, uint32_t count) -{ -#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) - ptr->RD_TRANS_CNT = (count - 1); -#else - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_RDTRANCNT_MASK) | SPI_TRANSCTRL_RDTRANCNT_SET(count - 1); -#endif -} - -/** - * @brief SPI master set the value of the one-byte special token following the address phase for SPI read transfers - * - * @param [in] ptr SPI base address - * @param [in] value spi_token_value_t enum - */ -static inline void spi_master_set_token_value(SPI_Type *ptr, spi_token_value_t value) -{ - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_TOKENVALUE_MASK) | SPI_TRANSCTRL_TOKENVALUE_SET(value); -} - -/** - * @brief SPI master set dummy data count - * - * @param [in] ptr SPI base address - * @param [in] count spi_dummy_count_t enum - */ -static inline void spi_set_dummy_count(SPI_Type *ptr, spi_dummy_count_t count) -{ - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_DUMMYCNT_MASK) | SPI_TRANSCTRL_DUMMYCNT_SET(count); -} - -/** - * @brief SPI master set the minimum time between the edges of SPI CS and the edges of SCLK - * - * @param [in] ptr SPI base address - * @param [in] duration spi_cs2sclk_duration_t enum - */ -static inline void spi_master_set_cs2sclk_timing(SPI_Type *ptr, spi_cs2sclk_duration_t duration) -{ - ptr->TIMING = (ptr->TIMING & ~SPI_TIMING_CS2SCLK_MASK) | SPI_TIMING_CS2SCLK_SET(duration); -} - -/** - * @brief SPI master get the minimum time between the edges of SPI CS and the edges of SCLK - * - * @param [in] ptr SPI base address - * @retval spi_cs2sclk_duration_t enum - */ -static inline spi_cs2sclk_duration_t spi_master_get_cs2sclk_timing(SPI_Type *ptr) -{ - return (spi_cs2sclk_duration_t)SPI_TIMING_CS2SCLK_GET(ptr->TIMING); -} - -/** - * @brief SPI master set the minimum time that SPI CS should stay HIGH. - * - * @param [in] ptr SPI base address - * @param [in] duration spi_csht_duration_t enum - */ -static inline void spi_master_set_csht_timing(SPI_Type *ptr, spi_csht_duration_t duration) -{ - ptr->TIMING = (ptr->TIMING & ~SPI_TIMING_CSHT_MASK) | SPI_TIMING_CSHT_SET(duration); -} - -/** - * @brief SPI master get the minimum time that SPI CS should stay HIGH. - * - * @param [in] ptr SPI base address - * @retval spi_csht_duration_t enum - */ -static inline spi_csht_duration_t spi_master_get_csht_timing(SPI_Type *ptr) -{ - return (spi_csht_duration_t)SPI_TIMING_CSHT_GET(ptr->TIMING); -} - -/** - * @brief SPI master set the clock frequency ratio between the clock source and SPI SCLK - * - * @param [in] ptr SPI base address - * @param [in] div the frequency ratio value - */ -static inline void spi_master_set_sclk_div(SPI_Type *ptr, uint8_t div) -{ - ptr->TIMING = (ptr->TIMING & ~SPI_TIMING_SCLK_DIV_MASK) | SPI_TIMING_SCLK_DIV_SET(div); -} - -/** - * @brief SPI master get the clock frequency ratio between the clock source and SPI SCLK - * - * @param [in] ptr SPI base address - * - * @retval return the frequency ratio value - */ -static inline uint8_t spi_master_get_sclk_div(SPI_Type *ptr) -{ - return SPI_TIMING_SCLK_DIV_GET(ptr->TIMING); -} - -/** - * @brief SPI slave set the user defined status flags - * - * @note in Non-SlvDataOnly, the command is read status command, such as 0x05\0x15\0x25 command - * - * @param [in] ptr SPI base address - * @param [in] user_status user status value - */ -static inline void spi_slave_set_user_status(SPI_Type *ptr, uint16_t user_status) -{ - ptr->SLVST = (ptr->SLVST & ~SPI_SLVST_USR_STATUS_MASK) | SPI_SLVST_USR_STATUS_SET(user_status); -} - -/** - * @brief SPI master set data phase format - * - * @param [in] ptr SPI base address - * @param [in] format spi_data_phase_format_t enum - */ -static inline void spi_master_set_data_phase_format(SPI_Type *ptr, spi_data_phase_format_t format) -{ - ptr->TRANSCTRL = (ptr->TRANSCTRL & ~SPI_TRANSCTRL_DUALQUAD_MASK) | SPI_TRANSCTRL_DUALQUAD_SET(format); -} - -/** - * @brief SPI master get data phase format - * - * @param [in] ptr SPI base address - * - * @retval return the data phase format - */ -static inline spi_data_phase_format_t spi_master_get_data_phase_format(SPI_Type *ptr) -{ - return (spi_data_phase_format_t)SPI_TRANSCTRL_DUALQUAD_GET(ptr->TRANSCTRL); -} - -/** - * @brief set spi shift direction - * - * @param [in] ptr SPI base address - * @param [in] shift_direction shift direction enum - */ -static inline void spi_set_shift_direction(SPI_Type *ptr, spi_shift_direction_t shift_direction) -{ - ptr->TRANSFMT = (ptr->TRANSFMT & ~SPI_TRANSFMT_LSB_MASK) | SPI_TRANSFMT_LSB_SET(shift_direction); -} - -/** - * @brief get spi shift direction - * - * @param [in] ptr SPI base address - * @retval spi_shift_direction_t msb_first if frist MSB - */ -static inline spi_shift_direction_t spi_get_shift_direction(SPI_Type *ptr) -{ - return (spi_shift_direction_t)SPI_TRANSFMT_LSB_GET(ptr->TRANSFMT); -} - -/** - * @} - */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ -#endif /* HPM_SPI_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h deleted file mode 100644 index a2522ec70a8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_synt_drv.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYNT_DRV_H -#define HPM_SYNT_DRV_H -#include "hpm_common.h" -#include "hpm_synt_regs.h" - -#ifdef __cplusplus -extern "C" { -#endif - -static inline void synt_enable_counter(SYNT_Type *ptr, bool enable) -{ - ptr->GCR = (ptr->GCR & ~(SYNT_GCR_CEN_MASK)) | SYNT_GCR_CEN_SET(enable); -} - -static inline void synt_reset_counter(SYNT_Type *ptr) -{ - ptr->GCR |= SYNT_GCR_CRST_MASK; - ptr->GCR &= ~SYNT_GCR_CRST_MASK; -} - -static inline hpm_stat_t synt_set_comparator(SYNT_Type *ptr, - uint8_t cmp_index, - uint32_t count) -{ - if (cmp_index > SYNT_CMP_3) { - return status_invalid_argument; - } - ptr->CMP[cmp_index] = SYNT_CMP_CMP_SET(count); - return status_success; -} - -static inline void synt_set_reload(SYNT_Type *ptr, uint32_t reload_count) -{ - ptr->RLD = SYNT_RLD_RLD_SET(reload_count); -} - -static inline uint32_t synt_get_current_count(SYNT_Type *ptr) -{ - return (ptr->CNT & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT; -} - -#if defined(SYNT_SOC_HAS_TIMESTAMP) && SYNT_SOC_HAS_TIMESTAMP - -static inline void synt_enable_timestamp(SYNT_Type *ptr, bool enable) -{ - ptr->GCR = (ptr->GCR & ~(SYNT_GCR_TIMESTAMP_ENABLE_MASK)) | SYNT_GCR_TIMESTAMP_ENABLE_SET(enable); -} - -static inline void synt_enable_timestamp_debug_stop(SYNT_Type *ptr, bool enable) -{ - ptr->GCR = (ptr->GCR & ~(SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK)) | SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(enable); -} - -static inline void synt_reset_timestamp(SYNT_Type *ptr) -{ - ptr->GCR |= SYNT_GCR_TIMESTAMP_RESET_MASK; -} - -static inline void synt_update_timestamp_new(SYNT_Type *ptr) -{ - ptr->GCR |= SYNT_GCR_TIMESTAMP_SET_NEW_MASK; -} - -static inline void synt_update_timestamp_dec(SYNT_Type *ptr) -{ - ptr->GCR |= SYNT_GCR_TIMESTAMP_DEC_NEW_MASK; -} - -static inline void synt_update_timestamp_inc(SYNT_Type *ptr) -{ - ptr->GCR |= SYNT_GCR_TIMESTAMP_INC_NEW_MASK; -} - -static inline void synt_set_timestamp_new_value(SYNT_Type *ptr, uint32_t new_value) -{ - ptr->TIMESTAMP_NEW = SYNT_TIMESTAMP_NEW_VALUE_SET(new_value); -} - -static inline uint32_t synt_get_timestamp_save_value(SYNT_Type *ptr) -{ - return SYNT_TIMESTAMP_SAV_VALUE_GET(ptr->TIMESTAMP_SAV); -} - -static inline uint32_t synt_get_timestamp_current_value(SYNT_Type *ptr) -{ - return SYNT_TIMESTAMP_CUR_VALUE_GET(ptr->TIMESTAMP_CUR); -} - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_SYNT_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tamp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tamp_drv.h deleted file mode 100644 index 2dbc0d441f2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tamp_drv.h +++ /dev/null @@ -1,221 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_TAMP_DRV_H -#define HPM_TAMP_DRV_H - -#include "hpm_common.h" -#include "hpm_tamp_regs.h" - -/** - * - * @brief TAMPER driver APIs - * @defgroup tamper_interface TAMPER driver APIs - * @ingroup io_interfaces - * @{ - */ - -typedef enum { - spd_1_time_per_sec = 0, - spd_2_times_per_sec, - spd_4_times_per_sec, - spd_8_times_per_sec, - spd_16_times_per_sec, - spd_32_times_per_sec, - spd_64_times_per_sec, - spd_128_times_per_sec, - spd_256_times_per_sec, - spd_512_times_per_sec, - spd_1024_times_per_sec, - spd_2048_times_per_sec, - spd_4096_times_per_sec, - spd_8192_times_per_sec, - spd_16384_times_per_sec, - spd_32768_times_per_sec, -} tamper_speed_t; - -typedef enum { - filter_len_1_cycle = 0, - filter_len_2_cycles, - filter_len_4_cycles, - filter_len_8_cycles, - filter_len_16_cycles, - filter_len_32_cycles, - filter_len_64_cycles, - filter_len_128_cycles, - filter_len_256_cycles, - filter_len_512_cycles, - filter_len_1024_cycles, - filter_len_2048_cycles, - filter_len_4096_cycles, - filter_len_8192_cycles, - filter_len_16384_cycles, - filter_len_32768_cycles, -} tamper_filter_len_t; - - typedef struct { - bool enable; - bool active_mode; - bool filter_bypass; - bool expect_high_level; - tamper_speed_t speed; - tamper_filter_len_t filter_len; - bool auto_recover; /* used in active mode */ - uint32_t poly; /* used in active mode */ - uint32_t lfsr; /* used in active mode */ -} tamper_ch_config_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Init tamper channel config - * - * @param[in] ptr tamper base address - * @param[in] ch tamper channel - * @param[in] config tamper channel config struct pointer - * - */ -void tamp_init_ch_config(TAMP_Type *ptr, uint8_t ch, tamper_ch_config_t *config); - -/** - * @brief Get tamper default channel config - * - * @param[in] ptr tamper base address - * @param[in] config tamper default channel config struct pointer - * - */ -void tamp_get_default_ch_config(TAMP_Type *ptr, tamper_ch_config_t *config); - -/** - * @brief Set tamper channel enable or disable - * - * @param[in] ptr tamper base address - * @param[in] ch tamper channel - * @param[in] enable true - enable tamper, false - disable tamper - * - */ -static inline void tamp_set_ch_enable(TAMP_Type *ptr, uint8_t ch, bool enable) -{ - ch >>= 1u; - if (enable) { - ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_ENABLE_MASK; - } else { - ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_ENABLE_MASK; - } -} - -/** - * @brief Set tamper channel config lock or unlock - * - * @param[in] ptr tamper base address - * @param[in] ch tamper channel - * @param[in] lock true - config lock, false - config unlock - * - */ -static inline void tamp_set_ch_config_lock(TAMP_Type *ptr, uint8_t ch, bool lock) -{ - ch >>= 1u; - if (lock) { - ptr->TAMP[ch].CONTROL |= TAMP_TAMP_CONTROL_LOCK_MASK; - } else { - ptr->TAMP[ch].CONTROL &= ~TAMP_TAMP_CONTROL_LOCK_MASK; - } -} - -/** - * @brief Get tamper all channel flags - * - * @param[in] ptr tamper base address - * - * @return all channel flags - */ -static inline uint32_t tamp_get_flags(TAMP_Type *ptr) -{ - return TAMP_TAMP_FLAG_FLAG_GET(ptr->TAMP_FLAG); -} - -/** - * @brief Clear tamper flags - * - * @param[in] ptr tamper base address - * @param[in] flags clear channel flags - * - */ -static inline void tamp_clear_flags(TAMP_Type *ptr, uint32_t flags) -{ - ptr->TAMP_FLAG = TAMP_TAMP_FLAG_FLAG_SET(flags); -} - -/** - * @brief Check tamper channel flag - * - * @param[in] ptr TAMPER base address - * @param[in] ch tamper channel - * - * @return true - flag is set, false - falg is unset. - */ -static inline bool tamp_check_ch_flag(TAMP_Type *ptr, uint8_t ch) -{ - return ((TAMP_TAMP_FLAG_FLAG_GET(ptr->TAMP_FLAG) & (1u << ch)) != 0u) ? true : false; -} - -/** - * @brief Clear tamper channel flag - * - * @param[in] ptr TAMPER base address - * @param[in] ch tamper channel - * - */ -static inline void tamp_clear_ch_flag(TAMP_Type *ptr, uint8_t ch) -{ - ptr->TAMP_FLAG = TAMP_TAMP_FLAG_FLAG_SET(1u << ch); -} - -/** - * @brief Set tamper channel irq enable or disable - * - * @param[in] ptr TAMPER base address - * @param[in] ch tamper channel - * @param[in] enable true - irq enable, false - irq disable - * - */ -static inline void tamp_enable_ch_irq(TAMP_Type *ptr, uint8_t ch, bool enable) -{ - if (enable) { - ptr->IRQ_EN |= TAMP_IRQ_EN_IRQ_EN_SET(1u << ch); - } else { - ptr->IRQ_EN &= ~TAMP_IRQ_EN_IRQ_EN_SET(1u << ch); - } -} - -/** - * @brief Set tamper irq lock or unlock - * - * @param[in] ptr tamper base address - * @param[in] lock true - irq lock, false - irq unlock - * - */ -static inline void tamp_set_irq_lock(TAMP_Type *ptr, bool lock) -{ - if (lock) { - ptr->IRQ_EN |= TAMP_IRQ_EN_LOCK_MASK; - } else { - ptr->IRQ_EN &= ~TAMP_IRQ_EN_LOCK_MASK; - } -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_TAMP_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h deleted file mode 100644 index 8561ccb4dd7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_trgm_drv.h +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_TRGM_DRV_H -#define HPM_TRGM_DRV_H - -#include "hpm_common.h" -#include "hpm_trgm_regs.h" -#include "hpm_trgmmux_src.h" - -/** - * - * @brief TRGM driver APIs - * @defgroup trgm_interface TRGM driver APIs - * @{ - */ - -/** - * @brief Filter mode - */ -typedef enum trgm_filter_mode { - trgm_filter_mode_bypass = 0, - trgm_filter_mode_rapid_change = 4, - trgm_filter_mode_delay = 5, - trgm_filter_mode_stable_high = 6, - trgm_filter_mode_stable_low = 7, -} trgm_filter_mode_t; - -/** - * @brief Output type - */ -typedef enum trgm_output_type { - trgm_output_same_as_input = 0, - trgm_output_pulse_at_input_falling_edge = TRGM_TRGOCFG_FEDG2PEN_MASK, - trgm_output_pulse_at_input_rising_edge = TRGM_TRGOCFG_REDG2PEN_MASK, - trgm_output_pulse_at_input_both_edge = trgm_output_pulse_at_input_falling_edge - | trgm_output_pulse_at_input_rising_edge, -} trgm_output_type_t; - -/** - * @brief Input filter configuration - */ -typedef struct trgm_input_filter { - bool invert; /**< Invert output */ - bool sync; /**< Sync with TRGM clock */ - uint32_t filter_length; /**< Filter length in TRGM clock cycle */ - trgm_filter_mode_t mode; /**< Filter working mode */ -} trgm_input_filter_t; - -/** - * @brief Output configuration - */ -typedef struct trgm_output { - bool invert; /**< Invert output */ - trgm_output_type_t type; /**< Output type */ - uint8_t input; /**< Input selection */ -} trgm_output_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Enable IO output - * - * @param[in] ptr TRGM base address - * @param[in] mask Mask of IOs to be enabled - */ -static inline void trgm_enable_io_output(TRGM_Type *ptr, uint32_t mask) -{ - ptr->GCR |= mask; -} - -/** - * @brief Disable IO output - * - * @param[in] ptr TRGM base address - * @param[in] mask Mask of IOs to be disabled - */ -static inline void trgm_disable_io_output(TRGM_Type *ptr, uint32_t mask) -{ - ptr->GCR &= ~mask; -} - -/** - * @brief Set filter length - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - * @param[in] length Filter length in TRGM clock cycles - */ -static inline void trgm_input_filter_set_filter_length(TRGM_Type *ptr, uint8_t input, uint32_t length) -{ -#if defined(TRGM_SOC_HAS_FILTER_SHIFT) && TRGM_SOC_HAS_FILTER_SHIFT - uint32_t len = length; - uint8_t shift; - for (shift = 0; shift <= (TRGM_FILTCFG_FILTLEN_SHIFT_MASK >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT); shift++) { - if (shift > 0) { - len >>= 1u; - } - if (len <= (TRGM_FILTCFG_FILTLEN_BASE_MASK >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)) { - break; - } - } - if (len > (TRGM_FILTCFG_FILTLEN_BASE_MASK >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)) { - len = (TRGM_FILTCFG_FILTLEN_BASE_MASK >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT); - shift = (TRGM_FILTCFG_FILTLEN_SHIFT_MASK >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT); - } - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~(TRGM_FILTCFG_FILTLEN_BASE_MASK | TRGM_FILTCFG_FILTLEN_SHIFT_MASK)) - | TRGM_FILTCFG_FILTLEN_BASE_SET(len) | TRGM_FILTCFG_FILTLEN_SHIFT_SET(shift); -#else - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_FILTLEN_MASK) - | TRGM_FILTCFG_FILTLEN_SET(length); -#endif -} - -/** - * @brief Set filter length - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - * @param[in] shift Filter length shift - */ -static inline void trgm_input_filter_set_filter_shift(TRGM_Type *ptr, uint8_t input, uint8_t shift) -{ -#if defined(TRGM_SOC_HAS_FILTER_SHIFT) && TRGM_SOC_HAS_FILTER_SHIFT - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_FILTLEN_SHIFT_MASK) - | TRGM_FILTCFG_FILTLEN_SHIFT_SET(shift); -#else - (void) ptr; - (void) input; - (void) shift; -#endif -} - -/** - * @brief Enable sync input with TRGM clock - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - */ -static inline void trgm_input_filter_enable_sync(TRGM_Type *ptr, uint8_t input) -{ - ptr->FILTCFG[input] |= TRGM_FILTCFG_SYNCEN_MASK; -} - -/** - * @brief Disable sync input with TRGM clock - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - */ -static inline void trgm_input_filter_disable_sync(TRGM_Type *ptr, uint8_t input) -{ - ptr->FILTCFG[input] &= ~TRGM_FILTCFG_SYNCEN_MASK; -} - -/** - * @brief Set filter working mode - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - * @param[in] mode Working mode - */ -static inline void trgm_input_filter_set_mode(TRGM_Type *ptr, uint8_t input, trgm_filter_mode_t mode) -{ - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_MODE_MASK) - | TRGM_FILTCFG_MODE_SET(mode); -} - -/** - * @brief Invert filter output - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - * @param[in] invert Set true to invert output - */ -static inline void trgm_input_filter_invert(TRGM_Type *ptr, uint8_t input, bool invert) -{ - ptr->FILTCFG[input] = (ptr->FILTCFG[input] & ~TRGM_FILTCFG_OUTINV_MASK) - | TRGM_FILTCFG_OUTINV_SET(invert); -} - -/** - * @brief Configure filter - * - * @param[in] ptr TRGM base address - * @param[in] input Input selection - * @param[in] filter Pointer to filter configuration - */ -static inline void trgm_input_filter_config(TRGM_Type *ptr, uint8_t input, trgm_input_filter_t *filter) -{ - ptr->FILTCFG[input] = TRGM_FILTCFG_OUTINV_SET(filter->invert) - | TRGM_FILTCFG_MODE_SET(filter->mode) - | TRGM_FILTCFG_SYNCEN_SET(filter->sync); - trgm_input_filter_set_filter_length(ptr, input, filter->filter_length); -} - -/** - * @brief Update source for TRGM output - * - * @param[in] ptr TRGM base address - * @param[in] output Target output - * @param[in] source Source for output - */ -static inline void trgm_output_update_source(TRGM_Type *ptr, uint8_t output, uint8_t source) -{ - ptr->TRGOCFG[output] = (ptr->TRGOCFG[output] & ~TRGM_TRGOCFG_TRIGOSEL_MASK) - | TRGM_TRGOCFG_TRIGOSEL_SET(source); -} - -/** - * @brief Configure output - * - * @param[in] ptr TRGM base address - * @param[in] output Target output - * @param[in] config Pointer to output configuration - */ -static inline void trgm_output_config(TRGM_Type *ptr, uint8_t output, trgm_output_t *config) -{ - ptr->TRGOCFG[output] = TRGM_TRGOCFG_TRIGOSEL_SET(config->input) - | (config->type & TRGM_TRGOCFG_FEDG2PEN_MASK) - | (config->type & TRGM_TRGOCFG_REDG2PEN_MASK) - | TRGM_TRGOCFG_OUTINV_SET(config->invert); -} - -/** - * @brief Configure DMA request - * - * @param[in] ptr TRGM base address - * @param[in] dma_out Target DMA out - * @param[in] dma_src DMA source selection - */ -static inline void trgm_dma_request_config(TRGM_Type *ptr, uint8_t dma_out, uint8_t dma_src) -{ -#if defined(TRGM_SOC_HAS_DMAMUX_EN) && TRGM_SOC_HAS_DMAMUX_EN - ptr->DMACFG[dma_out] = TRGM_DMACFG_DMASRCSEL_SET(dma_src) | TRGM_DMACFG_DMAMUX_EN_MASK; -#else - ptr->DMACFG[dma_out] = TRGM_DMACFG_DMASRCSEL_SET(dma_src); -#endif -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_TRGM_DRV_H */ - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h deleted file mode 100644 index 4f0416cfd2f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsns_drv.h +++ /dev/null @@ -1,417 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSNS_DRV_H -#define HPM_TSNS_DRV_H - -#include "hpm_common.h" -#include "hpm_tsns_regs.h" - -/** - * @brief TSNS driver APIs - * @defgroup tsns_interface TSNS driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ -#define TSNS_TEMP_SCALE 256 - -typedef enum { - tsns_clear_min = TSNS_FLAG_RECORD_MIN_CLR_MASK, - tsns_clear_max = TSNS_FLAG_RECORD_MAX_CLR_MASK, - tsns_clear_under_temp = TSNS_FLAG_UNDER_TEMP_MASK, - tsns_clear_over_temp = TSNS_FLAG_OVER_TEMP_MASK, - tsns_clear_irq = TSNS_FLAG_IRQ_MASK, -} tsns_clear_type_mask_t; - -typedef enum { - tsns_event_irq = 0, - tsns_event_reset, -} tsns_event_t; - -#ifdef __cplusplus -extern "C" { -#endif - - -/** - * @brief Enable temperature sensor - * - * @param ptr base address - */ -static inline void tsns_enable(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_ENABLE_MASK; -} - -/** - * @brief Disable temperature sensor - * - * @param ptr base address - */ -static inline void tsns_disable(TSNS_Type *ptr) -{ - ptr->CONFIG &= ~TSNS_CONFIG_ENABLE_MASK; -} - -/** - * @brief Check if current temperature value is valid or not - * - * @param ptr base address - * - * @return true the value is valid - */ -static inline bool tsns_temperature_is_valid(TSNS_Type *ptr) -{ - return ptr->STATUS & TSNS_STATUS_VALID_MASK; -} - -/** - * @brief Get maximum measured temperature in raw - * - * @param ptr base address - * - * @return raw maximum temperature value scaled by TSNS_TEMP_SCALE - */ -static inline int32_t tsns_get_max_temp_raw(TSNS_Type *ptr) -{ - return TSNS_TMAX_T_GET(ptr->TMAX); -} - -/** - * @brief Get minimum measured temperature in raw - * - * @param ptr base address - * - * @return raw minimum temperature value scaled by TSNS_TEMP_SCALE - */ -static inline int32_t tsns_get_min_temp_raw(TSNS_Type *ptr) -{ - return TSNS_TMIN_T_GET(ptr->TMIN); -} - -/** - * @brief Get current temperature in raw - * - * @param ptr base address - * - * @return raw temperature value scaled by TSNS_TEMP_SCALE - */ -static inline int32_t tsns_get_current_temp_in_raw(TSNS_Type *ptr) -{ - while (!tsns_temperature_is_valid(ptr)) { - ; - } - return TSNS_T_T_GET(ptr->T); -} - -/** - * @brief Get current temperature in celsius degree - * - * @param ptr base address - * - * @return current temperature in celsius degree - */ -static inline float tsns_get_current_temp(TSNS_Type *ptr) -{ - return (float)(((int32_t)tsns_get_current_temp_in_raw(ptr) / TSNS_TEMP_SCALE)); -} - -/** - * @brief Get temperature age - * - * @param ptr base address - * - * @return temperature age - */ -static inline uint32_t tsns_get_temp_age(TSNS_Type *ptr) -{ - return TSNS_AGE_AGE_GET(ptr->AGE); -} - -/** - * @brief Set temperature high limit to trigger rest - * - * @param ptr base address - * @param high temperature value - */ -static inline void tsns_set_reset_threshold_high(TSNS_Type *ptr, uint32_t high) -{ - ptr->UPPER_LIM_IRQ = TSNS_UPPER_LIM_RST_T_SET(high); -} - -/** - * @brief Set temperature low limit to trigger reset - * - * @param ptr base address - * @param low temperature value - */ -static inline void tsns_set_reset_threshold_low(TSNS_Type *ptr, uint32_t low) -{ - ptr->LOWER_LIM_IRQ = TSNS_LOWER_LIM_RST_T_SET(low); -} - -/** - * @brief Enable temperature limit to trigger irq - * - * @param ptr base address - */ -static inline void tsns_enable_limit_trigger_reset(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK; -} - -/** - * @brief Disable temperature limit to trigger irq - * - * @param ptr base address - */ -static inline void tsns_disable_limit_trigger_irq(TSNS_Type *ptr) -{ - ptr->CONFIG &= ~TSNS_CONFIG_RST_EN_MASK; -} - -/** - * @brief Set temperature high limit to trigger irq - * - * @param ptr base address - * @param high temperature value - */ -static inline void tsns_set_irq_threshold_high(TSNS_Type *ptr, uint32_t high) -{ - ptr->UPPER_LIM_IRQ = TSNS_UPPER_LIM_IRQ_T_SET(high); -} - -/** - * @brief Set temperature low limit to trigger irq - * - * @param ptr base address - * @param low temperature value - */ -static inline void tsns_set_irq_threshold_low(TSNS_Type *ptr, uint32_t low) -{ - ptr->LOWER_LIM_IRQ = TSNS_LOWER_LIM_IRQ_T_SET(low); -} - -/** - * @brief Enable temperature limit to trigger irq - * - * @param ptr base address - */ -static inline void tsns_enable_limit_trigger_irq(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK; -} - -/** - * @brief Set validity of current measured temperature in 24Mhz clock cycles - * - * @param ptr base address - * @param validity clock cycle count - */ -static inline void tsns_set_validity(TSNS_Type *ptr, uint32_t validity) -{ - ptr->VALIDITY = TSNS_VALIDITY_VALIDITY_SET(validity); -} - -/** - * @brief Set temperature limit to trigger irq - * - * @param ptr base address - * @param high high temperature - * @param low low temperature - */ -static inline void tsns_config_irq_threshold(TSNS_Type *ptr, uint32_t high, uint32_t low) -{ - tsns_set_irq_threshold_low(ptr, low); - tsns_set_irq_threshold_high(ptr, high); -} - -/** - * @brief Set temperature limit to trigger reset - * - * @param ptr base address - * @param high high temperature - * @param low low temperature - */ -static inline void tsns_config_reset_threshold(TSNS_Type *ptr, uint32_t high, uint32_t low) -{ - tsns_set_reset_threshold_low(ptr, low); - tsns_set_reset_threshold_high(ptr, high); -} - -/** - * @brief Enable compare max temperature - * - * @param ptr base address - */ -static inline void tsns_enable_compare_max(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_COMPARE_MAX_EN_MASK; -} - -/** - * @brief Enable compare min temperature - * - * @param ptr base address - */ -static inline void tsns_enable_compare_min(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_COMPARE_MIN_EN_MASK; -} - -/** - * @brief Disable compare max temperature - * - * @param ptr base address - */ -static inline void tsns_disable_compare_max(TSNS_Type *ptr) -{ - ptr->CONFIG &= ~TSNS_CONFIG_COMPARE_MAX_EN_MASK; -} - -/** - * @brief Disable compare min temperature - * - * @param ptr base address - */ -static inline void tsns_disable_compare_min(TSNS_Type *ptr) -{ - ptr->CONFIG &= ~TSNS_CONFIG_COMPARE_MIN_EN_MASK; -} - -/** - * @brief Set measurement speed - * - * @param ptr base address - * @param speed speed from 24-255 - */ -static inline void tsns_set_speed(TSNS_Type *ptr, uint8_t speed) -{ - assert(speed >= 24); - ptr->CONFIG = (ptr->CONFIG & ~TSNS_CONFIG_SPEED_MASK) | TSNS_CONFIG_SPEED_SET(speed); -} - -/** - * @brief Set average - * - * @param ptr base address - * @param average range 0 - 7 (0: 2^0 = 1 means measure once and return ... 2: 2^2 = 4 means measure 4 times and average) - */ -static inline void tsns_set_average(TSNS_Type *ptr, uint8_t average) -{ - ptr->CONFIG = (ptr->CONFIG & ~TSNS_CONFIG_AVERAGE_MASK) | TSNS_CONFIG_AVERAGE_SET(average); -} - -/** - * @brief Enable Async mode - * - * @param ptr base address - */ -static inline void tsns_enable_async_mode(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_ASYNC_MASK; -} - -/** - * @brief Disable Async mode and switch to active mode - * - * @param ptr base address - */ -static inline void tsns_disable_async_mode(TSNS_Type *ptr) -{ - ptr->CONFIG &= ~TSNS_CONFIG_ASYNC_MASK; -} - -/** - * @brief Enable trigger mode - * - * @param ptr base address - */ -static inline void tsns_enable_trigger_mode(TSNS_Type *ptr) -{ - ptr->CONFIG &= ~TSNS_CONFIG_CONTINUOUS_MASK; -} - -/** - * @brief Enable continuous mode - * - * @param ptr base address - */ -static inline void tsns_enable_continuous_mode(TSNS_Type *ptr) -{ - ptr->CONFIG |= TSNS_CONFIG_CONTINUOUS_MASK; -} - -/** - * @brief trigger measurement - * - * @param ptr base address - */ -static inline void tsns_trigger_measurement(TSNS_Type *ptr) -{ - uint32_t tmp = ptr->CONFIG; - ptr->CONFIG &= ~TSNS_CONFIG_CONTINUOUS_MASK; - ptr->STATUS |= TSNS_STATUS_TRIGGER_MASK; - ptr->CONFIG = tmp; -} - -/** - * @brief clear tsns flag or recorded data - * - * @param ptr base address - * @param mask flag or data to be cleared - */ -static inline void tsns_clear_with_mask(TSNS_Type *ptr, tsns_clear_type_mask_t mask) -{ - ptr->FLAG |= mask; -} - - -/** - * @brief configure low temperature limite to trigger event - * - * @param ptr base address - * @param low temperature value - * @param e event type, tsns_event_irq or tsns_event_reset - */ -void tsns_configure_low_limit_event(TSNS_Type *ptr, int32_t low, tsns_event_t e); - -/** - * @brief configure high temperature limite to trigger event - * - * @param ptr base address - * @param high temperature value - * @param e event type, tsns_event_irq or tsns_event_reset - */ -void tsns_configure_high_limit_event(TSNS_Type *ptr, int32_t high, tsns_event_t e); - -/** - * @brief configure temperature limite to trigger event - * - * @param ptr base address - * @param high temperature value - * @param low temperature value - * @param e event type, tsns_event_irq or tsns_event_reset - */ -void tsns_configure_limit_event(TSNS_Type *ptr, int32_t high, int32_t low, tsns_event_t e); - -#ifdef __cplusplus -} -#endif -/** - * @} - * - */ -#endif /* HPM_TSNS_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsw_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsw_drv.h deleted file mode 100644 index 5b6db01b511..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_tsw_drv.h +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_TSW_DRV_H -#define HPM_TSW_DRV_H - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------*/ -#include "hpm_common.h" -#include "hpm_soc_feature.h" -#include "hpm_tsw_regs.h" - -/** - * @brief TSW driver APIs - * @defgroup tsw_interface TSW driver APIs - * @ingroup communication_interfaces - * @{ - */ - -/*--------------------------------------------------------------------- - * Macro Constant Declarations - *-------------------------------------------------------------------*/ -#define MAC_LO(mac) (uint32_t)(mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24)) -#define MAC_HI(mac) (uint32_t)(mac[4] | (mac[5] << 8)) - -#define MAC_MDIO_CTRL_OP_WR (0x01) -#define MAC_MDIO_CTRL_OP_RD (0x02) - -/*--------------------------------------------------------------------- - * Typedef Struct Declarations - *-------------------------------------------------------------------*/ -typedef struct { - union { - uint32_t tx_hdr0; - struct { - uint32_t dest_port: 8; /**< dest port */ - uint32_t : 8; /**< reserved */ - uint32_t queue : 3; /**< the priority queue for TSW TX */ - uint32_t utag : 3; /**< TSW-EP TX user sideband information */ - uint32_t : 6; /**< reserved */ - uint32_t htype : 4; /**< header type */ - } tx_hdr0_bm; - }; - - union { - uint32_t tx_hdr1; - struct { - uint32_t cb: 32; /**< CB field. Optionally used for external stream identification */ - } tx_hdr1_bm; - }; - - uint32_t tx_hdr2; /**< reserved */ - uint32_t tx_hdr3; /**< reserved */ -} tx_hdr_desc_t; - -/*--------------------------------------------------------------------- - * Typedef Enum Declarations - *-------------------------------------------------------------------*/ -typedef enum { - tsw_port_speed_10mbps = 2, - tsw_port_speed_100mbps = 3, - tsw_port_speed_1000mbps = 0 -} tsw_port_speed_t; - -typedef enum { - tsw_port_phy_itf_mii = 0, - tsw_port_phy_itf_rmii = 4, - tsw_port_phy_itf_rgmii = 1 -} tsw_port_phy_itf_t; - -typedef enum { - tsw_dst_port_null = 0, - tsw_dst_port_cpu = 1 << 0, - tsw_dst_port_1 = 1 << 1, - tsw_dst_port_2 = 1 << 2, - tsw_dst_port_3 = 1 << 3, -} tsw_dst_t; - -typedef enum { - tsw_mac_mode_mii = 0, - tsw_mac_mode_gmii -} tsw_mac_mode_t; - -#if defined __cplusplus -extern "C" { -#endif /* __cplusplus */ -/*--------------------------------------------------------------------- - * Exported Functions - *-------------------------------------------------------------------*/ -/** - * @brief Send a frame from CPU port - * - * @param[in] ptr TSW peripheral base address - * @param[in] length Frame length - * @param[in] id Frame index - * @return Result of the transmission - */ -hpm_stat_t tsw_send(TSW_Type *ptr, uint32_t *buffer, uint32_t length, uint8_t id); - -/** - * @brief Setup a receive description - * - * @param[in] ptr TSW peripheral base address - * @param[in] buffer Pointer to the specified receive buffer - * @param[in] length Frame length - * @param[in] id Frame index - * @return Result of the setup of a receive description - */ -hpm_stat_t tsw_recv_setup(TSW_Type *ptr, uint32_t *buffer, uint32_t length, uint8_t id); - -/** - * @brief Receive a frame - * - * @param[in] ptr TSW peripheral base address - * @param[in] buffer Pointer to the specified receive buffer - * @param[in] length Buffer length - * @param[in] id Frame index - * @return Result of the received frame - */ -uint32_t tsw_recv(TSW_Type *ptr, uint32_t *buffer, uint32_t length, uint8_t id); - -/** - * @brief Lookup Bypass Setting - * - * @param[in] ptr TSW peripheral base address - * @param[in] dst_port Destination port number - */ -void tsw_mac_lookup_bypass(TSW_Type *ptr, uint8_t dst_port); - -/** - * @brief CAM VLAN Setting - * - * @param[in] ptr TSW peripheral base address - * @param[in] dst_port Destination port number - */ -void tsw_set_cam_vlan_port(TSW_Type *ptr); - -/** - * @brief MDIO Interface Config - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] clk_div TSW clock division - * @return Result of MDIO interface config - */ -hpm_stat_t tsw_ep_set_mdio_config(TSW_Type *ptr, uint8_t port, uint8_t clk_div); - -/** - * @brief MDIO Read - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] phy_addr TSW clock division - * @param[in] reg_addr PHY register address - * @param[out] data Pointer to data memory - * @return Result of MDIO read - */ -hpm_stat_t tsw_ep_mdio_read(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint16_t *data); - -/** - * @brief MDIO Write - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] phy_addr TSW clock division - * @param[in] reg_addr PHY register address - * @param[in] data Data value - * @return Result of MDIO write - */ -hpm_stat_t tsw_ep_mdio_write(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint16_t data); - -/** - * @brief Enable MAC Controller - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] mac_type MAC type 0:EMAC/1:PMAC - * @param[in] enable Enable MAC Controller: Set true to enable; Set false to disable - * @return Result of controlling MAC controller - */ -hpm_stat_t tsw_ep_enable_mac_ctrl(TSW_Type *ptr, uint8_t port, uint8_t mac_type, bool enable); - -/** - * @brief Set MAC Address - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] mac_addr Pointer to MAC address - * @param[in] promisc Promiscuous Mode: Set true to enable; set false to disable - * @return Result of setting MAC address - */ -hpm_stat_t tsw_ep_set_mac_addr(TSW_Type *ptr, uint8_t port, uint8_t *mac_addr, bool promisc); - -/** - * @brief Set MAC Mode - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] mac_addr Pointer to MAC address - * @param[in] promisc Promiscuous Mode: Set true to enable; set false to disable - * @return Result of setting MAC address - */ -hpm_stat_t tsw_ep_set_mac_mode(TSW_Type *ptr, uint8_t port, uint8_t gmii); - -/** - * @brief Set Port GPR - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - * @param[in] speed Pointer to MAC address - * @param[in] itf Promiscuous Mode: Set true to enable; set false to disable - * @param[in] tx_dly Tx delay - * @param[in] rx_dlay Rx delay - */ -void tsw_port_gpr(TSW_Type *ptr, uint8_t port, uint8_t speed, uint8_t itf, uint8_t tx_dly, uint8_t rx_dly); - -/** - * @brief Set Internal Frame Action - * - * @param[in] ptr TSW peripheral base address - * @param[in] dest_port Destination port number - */ -void tsw_set_internal_frame_action(TSW_Type *ptr, uint8_t dest_port); - -/** - * @brief Set Broadcast Frame Action - * - * @param[in] ptr TSW peripheral base address - * @param[in] dest_port Destination port number - */ -void tsw_set_broadcast_frame_action(TSW_Type *ptr, uint8_t dest_port); - -/** - * @brief Set Unknow Frame Action - * - * @param[in] ptr TSW peripheral base address - * @param[in] dest_port Destination port number - */ -void tsw_set_unknown_frame_action(TSW_Type *ptr, uint8_t dest_port); - -/** - * @brief Set Lookup Table - * - * @param[in] ptr TSW peripheral base address - * @param[in] entry_num Entry number - * @param[in] dest_port Destination port number - * @param[in] dest_mac Destination MAC address - */ -void tsw_set_lookup_table(TSW_Type *ptr, uint16_t entry_num, uint8_t dest_port, uint64_t dest_mac); - -/** - * @brief Clear CAM - * - * @param[in] ptr TSW peripheral base address - */ -void tsw_clear_cam(TSW_Type *ptr); - -/** - * @brief Enable RXFIFO to store and forward mode - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - */ -void tsw_enable_store_forward_mode(TSW_Type *ptr, uint8_t port); - -/** - * @brief Disable RXFIFO to store and forward mode - * - * @param[in] ptr TSW peripheral base address - * @param[in] port TSW port number - */ -void tsw_disable_store_forward_mode(TSW_Type *ptr, uint8_t port); - -#if defined __cplusplus -} -#endif /* __cplusplus */ -/** @} */ -#endif /* HPM_TSW_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h deleted file mode 100644 index 079d1a94846..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_uart_drv.h +++ /dev/null @@ -1,919 +0,0 @@ -/* - * Copyright (c) 2021-2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_UART_DRV_H -#define HPM_UART_DRV_H -#include "hpm_common.h" -#include "hpm_uart_regs.h" -#include "hpm_soc_feature.h" - -/** - * - * @brief UART driver APIs - * @defgroup uart_interface UART driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief UART status - */ -enum { - status_uart_no_suitable_baudrate_parameter_found = MAKE_STATUS(status_group_uart, 1), -}; - -/* @brief Parity */ -typedef enum parity { - parity_none = 0, - parity_odd, - parity_even, - parity_always_1, - parity_always_0, -} parity_setting_t; - -/* @brief Stop bits */ -typedef enum num_of_stop_bits { - stop_bits_1 = 0, - stop_bits_1_5, - stop_bits_2, -} num_of_stop_bits_t; - -/* @brief Word length */ -typedef enum word_length { - word_length_5_bits = 0, - word_length_6_bits, - word_length_7_bits, - word_length_8_bits, -} word_length_t; - -/* @brief UART fifo trigger levels */ -typedef enum uart_fifo_trg_lvl { -#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1) - uart_fifo_1_byte = 0, - uart_fifo_2_bytes = 1, - uart_fifo_3_bytes = 2, - uart_fifo_4_bytes = 3, - uart_fifo_5_bytes = 4, - uart_fifo_6_bytes = 5, - uart_fifo_7_bytes = 6, - uart_fifo_8_bytes = 7, - uart_fifo_9_bytes = 8, - uart_fifo_10_bytes = 9, - uart_fifo_11_bytes = 10, - uart_fifo_12_bytes = 11, - uart_fifo_13_bytes = 12, - uart_fifo_14_bytes = 13, - uart_fifo_15_bytes = 14, - uart_fifo_16_bytes = 15, - - uart_rx_fifo_trg_not_empty = uart_fifo_1_byte, - uart_rx_fifo_trg_gt_one_quarter = uart_fifo_4_bytes, - uart_rx_fifo_trg_gt_half = uart_fifo_8_bytes, - uart_rx_fifo_trg_gt_three_quarters = uart_fifo_12_bytes, - - uart_tx_fifo_trg_not_full = uart_fifo_16_bytes, - uart_tx_fifo_trg_lt_three_quarters = uart_fifo_12_bytes, - uart_tx_fifo_trg_lt_half = uart_fifo_8_bytes, - uart_tx_fifo_trg_lt_one_quarter = uart_fifo_4_bytes, -#else - uart_rx_fifo_trg_not_empty = 0, - uart_rx_fifo_trg_gt_one_quarter = 1, - uart_rx_fifo_trg_gt_half = 2, - uart_rx_fifo_trg_gt_three_quarters = 3, - - uart_tx_fifo_trg_not_full = 0, - uart_tx_fifo_trg_lt_three_quarters = 1, - uart_tx_fifo_trg_lt_half = 2, - uart_tx_fifo_trg_lt_one_quarter = 3, -#endif -} uart_fifo_trg_lvl_t; - -/* @brief UART signals */ -typedef enum uart_signal { - uart_signal_rts = UART_MCR_RTS_MASK, -} uart_signal_t; - -/* @brief UART signal levels */ -typedef enum uart_signal_level { - uart_signal_level_high, - uart_signal_level_low, -} uart_signal_level_t; - -/* @brief UART modem status */ -typedef enum uart_modem_stat { - uart_modem_stat_cts = UART_MSR_CTS_MASK, - uart_modem_stat_dcts_changed = UART_MSR_DCTS_MASK, -} uart_modem_stat_t; - -/* @brief UART interrupt enable masks */ -typedef enum uart_intr_enable { - uart_intr_rx_data_avail_or_timeout = UART_IER_ERBI_MASK, - uart_intr_tx_slot_avail = UART_IER_ETHEI_MASK, - uart_intr_rx_line_stat = UART_IER_ELSI_MASK, - uart_intr_modem_stat = UART_IER_EMSI_MASK, -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - uart_intr_rx_line_idle = UART_IER_ERXIDLE_MASK, -#endif -#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) - uart_intr_tx_line_idle = UART_IER_ETXIDLE_MASK, -#endif -#if defined(HPM_IP_FEATURE_UART_ADDR_MATCH) && (HPM_IP_FEATURE_UART_ADDR_MATCH == 1) - uart_intr_addr_match = UART_IER_EADDRM_MASK, - uart_intr_addr_match_and_rxidle = UART_IER_EADDRM_IDLE_MASK, - uart_intr_addr_datalost = UART_IER_EDATLOST_MASK, -#endif -} uart_intr_enable_t; - -/* @brief UART interrupt IDs */ -typedef enum uart_intr_id { - uart_intr_id_modem_stat = 0x0, - uart_intr_id_tx_slot_avail = 0x2, - uart_intr_id_rx_data_avail = 0x4, - uart_intr_id_rx_line_stat = 0x6, - uart_intr_id_rx_timeout = 0xc, -} uart_intr_id_t; - -/* @brief UART status */ -typedef enum uart_stat { - uart_stat_data_ready = UART_LSR_DR_MASK, /* rx data ready in fifo */ - uart_stat_overrun_error = UART_LSR_OE_MASK, - uart_stat_parity_error = UART_LSR_PE_MASK, - uart_stat_framing_error = UART_LSR_FE_MASK, - uart_stat_line_break = UART_LSR_LBREAK_MASK, - uart_stat_tx_slot_avail = UART_LSR_THRE_MASK, - uart_stat_transmitter_empty = UART_LSR_TEMT_MASK, - uart_stat_rx_fifo_error = UART_LSR_ERRF_MASK, -} uart_stat_t; - -/** - * @brief UART modem config - */ -typedef struct uart_modem_config { - bool auto_flow_ctrl_en; /**< Auto flow control enable flag */ - bool loop_back_en; /**< Loop back enable flag */ - bool set_rts_high; /**< Set signal RTS level high flag */ -} uart_modem_config_t; - -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) -/** - * @brief UART Idle detection conditions， suitable for RX and TX - */ -typedef enum hpm_uart_rxline_idle_cond { - uart_rxline_idle_cond_rxline_logic_one = 0, /**< Treat as idle if the RX Line high duration exceeds threshold */ - uart_rxline_idle_cond_state_machine_idle = 1 /**< Treat as idle if the RX state machine idle state duration exceeds threshold */ -} uart_rxline_idle_cond_t; - -/** - * @brief UART Idle config， suitable for RX and TX - */ -typedef struct hpm_uart_rxline_idle_detect_config { - bool detect_enable; /**< RX Line Idle detection flag */ - bool detect_irq_enable; /**< Enable RX Line Idle detection interrupt */ - uart_rxline_idle_cond_t idle_cond; /**< RX Line Idle detection condition */ - uint8_t threshold; /**< UART RX Line Idle detection threshold, in terms of bits */ -} uart_rxline_idle_config_t; -#endif - -/** - * @brief UART config - */ -typedef struct hpm_uart_config { - uint32_t src_freq_in_hz; /**< Source clock frequency in Hz */ - uint32_t baudrate; /**< Baudrate */ - uint8_t num_of_stop_bits; /**< Number of stop bits */ - uint8_t word_length; /**< Word length */ - uint8_t parity; /**< Parity */ - uint8_t tx_fifo_level; /**< TX Fifo level */ - uint8_t rx_fifo_level; /**< RX Fifo level */ - bool dma_enable; /**< DMA Enable flag */ - bool fifo_enable; /**< Fifo Enable flag */ - uart_modem_config_t modem_config; /**< Modem config */ -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - uart_rxline_idle_config_t rxidle_config; /**< RX Idle configuration */ -#endif -#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) - uart_rxline_idle_config_t txidle_config; /**< TX Idle configuration */ -#endif -#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1) - bool rx_enable; /**< RX Enable configuration */ -#endif -} uart_config_t; - -#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1) -typedef struct { - uint16_t stop_bit_len; - bool en_stop_bit_insert; - bool hardware_trig; - bool trig_mode; - bool trig_clr_rxfifo; -} uart_trig_config_t; -#endif - -typedef struct { - uint8_t tx_fifo_level; /**< TX Fifo level */ - uint8_t rx_fifo_level; /**< RX Fifo level */ - bool reset_tx_fifo; /**< reset tx Fifo */ - bool reset_rx_fifo; /**< reset rx Fifo */ - bool dma_enable; /**< DMA Enable flag */ - bool fifo_enable; /**< Fifo Enable flag */ -} uart_fifo_ctrl_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get fifo size - * - * @param [in] ptr UART base address - * @retval size of Fifo - */ -static inline uint8_t uart_get_fifo_size(UART_Type *ptr) -{ - return 16 << ((ptr->CFG & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT); -} - -/** - * @brief uart config fifo control - * - * @note fifo control register(FCR) is WO access, if support FCCR register, it is RW access. - * - * @param [in] ptr UART base address - * @param [in] ctrl uart_fifo_ctrl_t - */ -void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl); - -/** - * @brief uart clear rx fifo by reading data - * - * @note read out all data in rx fifo, the uart_intr_rx_data_avail_or_timeout is cleared - * when RBR register is read - * - * @param [in] ptr UART base address - */ -static inline void uart_clear_rx_fifo(UART_Type *ptr) -{ - while (ptr->LSR & UART_LSR_DR_MASK) { - ptr->RBR; - } -} - -/** - * @brief Reset TX Fifo - * - * @param [in] ptr UART base address - */ -static inline void uart_reset_tx_fifo(UART_Type *ptr) -{ -#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1) - ptr->FCRR |= UART_FCRR_TFIFORST_MASK; -#else - ptr->FCR = UART_FCR_TFIFORST_MASK | (ptr->GPR); -#endif -} - -/** - * @brief Reset RX Fifo - * - * @param [in] ptr UART base address - */ -static inline void uart_reset_rx_fifo(UART_Type *ptr) -{ -#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1) - ptr->FCRR |= UART_FCRR_RFIFORST_MASK; -#else - ptr->FCR = UART_FCR_RFIFORST_MASK | (ptr->GPR); -#endif -} - -/** - * @brief [in] Reset both TX and RX Fifo - * - * @param [in] ptr UART base address - */ -static inline void uart_reset_all_fifo(UART_Type *ptr) -{ -#if defined(HPM_IP_FEATURE_UART_FCRR) && (HPM_IP_FEATURE_UART_FCRR == 1) - ptr->FCRR |= UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; -#else - ptr->FCR = UART_FCR_RFIFORST_MASK | UART_FCR_TFIFORST_MASK | (ptr->GPR); -#endif -} - -/** - * @brief Enable modem loopback - * - * @param [in] ptr UART base address - */ -static inline void uart_modem_enable_loopback(UART_Type *ptr) -{ - ptr->MCR |= UART_MCR_LOOP_MASK; -} - -/** - * @brief Disable modem loopback - * - * @param [in] ptr UART base address - */ -static inline void uart_modem_disable_loopback(UART_Type *ptr) -{ - ptr->MCR &= ~UART_MCR_LOOP_MASK; -} - -/** - * @brief Disable modem auto flow control - * - * @param [in] ptr UART base address - */ - -static inline void uart_modem_disable_auto_flow_control(UART_Type *ptr) -{ - ptr->MCR &= ~UART_MCR_AFE_MASK; -} - -/** - * @brief Enable modem auto flow control - * - * @param [in] ptr UART base address - */ -static inline void uart_modem_enable_auto_flow_control(UART_Type *ptr) -{ - ptr->MCR |= UART_MCR_AFE_MASK; -} - -/** - * @brief Configure modem - * - * @param [in] ptr UART base address - * @param config Pointer to modem config struct - */ -static inline void uart_modem_config(UART_Type *ptr, uart_modem_config_t *config) -{ - ptr->MCR = UART_MCR_AFE_SET(config->auto_flow_ctrl_en) - | UART_MCR_LOOP_SET(config->loop_back_en) - | UART_MCR_RTS_SET(!config->set_rts_high); -} - -/** - * @brief Get modem status - * - * @param [in] ptr UART base address - * @retval Current modem status - */ -static inline uint8_t uart_get_modem_status(UART_Type *ptr) -{ - return ptr->MSR; -} - -/** - * @brief Write byte to TX - * - * @param ptr UART base address - * @param c data to be sent - */ -static inline void uart_write_byte(UART_Type *ptr, uint8_t c) -{ - ptr->THR = UART_THR_THR_SET(c); -} - - -/** - * @brief Read byte from RX - * - * @param ptr UART base address - * @retval RX byte - */ -static inline uint8_t uart_read_byte(UART_Type *ptr) -{ - return (ptr->RBR & UART_RBR_RBR_MASK); -} - -/** - * @brief Check modem status with given mask - * - * @param [in] ptr UART base address - * @param mask Status mask value to be checked against - * @retval true if any bit in given mask is set - * @retval false if none of any bit in given mask is set - */ -static inline bool uart_check_modem_status(UART_Type *ptr, uart_modem_stat_t mask) -{ - return ((ptr->MSR & mask) != 0U) ? true : false; -} - -/** - * @brief Disable IRQ with mask - * - * @param [in] ptr UART base address - * @param irq_mask IRQ mask value to be disabled - */ -static inline void uart_disable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) -{ - ptr->IER &= ~irq_mask; -} - -/** - * @brief Enable IRQ with mask - * - * @param [in] ptr UART base address - * @param irq_mask IRQ mask value to be enabled - */ -static inline void uart_enable_irq(UART_Type *ptr, uart_intr_enable_t irq_mask) -{ - ptr->IER |= irq_mask; -} - -/** - * @brief Get Enabled IRQ - * - * @param [in] ptr UART base address - * @return enabled irq - */ -static inline uint32_t uart_get_enabled_irq(UART_Type *ptr) -{ - return ptr->IER; -} - -/** - * @brief Get interrupt identification - * - * @param [in] ptr UART base address - * @retval interrupt id - */ -static inline uint8_t uart_get_irq_id(UART_Type *ptr) -{ - return (ptr->IIR & UART_IIR_INTRID_MASK); -} - -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - -/* if HPM_IP_FEATURE_UART_E00018_FIX = 1, the IIR2 register exists, should use IIR2 to get/clear rx idle status */ -#if !defined(HPM_IP_FEATURE_UART_E00018_FIX) || (HPM_IP_FEATURE_UART_E00018_FIX == 0) -/** - * @brief Determine whether UART RX Line is idle - * @param [in] ptr UART base address - * @retval false if uart RX line is not idle - */ -static inline bool uart_is_rxline_idle(UART_Type *ptr) -{ - return ((ptr->IIR & UART_IIR_RXIDLE_FLAG_MASK) != 0U) ? true : false; -} - -/** - * @brief Clear UART RX Line Idle Flag - * @param [in] ptr UART base address - */ -static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) -{ - ptr->IIR = UART_IIR_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ - ptr->FCR = ptr->GPR; -} -#endif - -/** - * @brief Enable UART RX Idle Line detection logic - * @param [in] ptr UART base address - */ -static inline void uart_enable_rxline_idle_detection(UART_Type *ptr) -{ - ptr->IDLE_CFG |= UART_IDLE_CFG_RX_IDLE_EN_MASK; -} - -/** - * @brief Disable UART RX Idle Line detection logic - * - * @param [in] ptr UART base address - */ -static inline void uart_disable_rxline_idle_detection(UART_Type *ptr) -{ - ptr->IDLE_CFG &= ~UART_IDLE_CFG_RX_IDLE_EN_MASK; -} - -/** - * @brief Configure UART RX Line detection - * @param [in] ptr UART base address - * @param [in] rxidle_config RXLine IDLE detection configuration - * @retval status_success if no error occurs - */ -hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config); - -#endif - -#if defined(HPM_IP_FEATURE_UART_E00018_FIX) && (HPM_IP_FEATURE_UART_E00018_FIX == 1) -/** - * @brief Determine whether UART TX Line is idle - * @param [in] ptr UART base address - * @retval false if uart TX line is not idle - */ -static inline bool uart_is_txline_idle(UART_Type *ptr) -{ - return ((ptr->IIR2 & UART_IIR2_TXIDLE_FLAG_MASK) != 0U) ? true : false; -} - -/** - * @brief Clear UART TX Line Idle Flag - * @param [in] ptr UART base address - */ -static inline void uart_clear_txline_idle_flag(UART_Type *ptr) -{ - ptr->IIR2 = UART_IIR2_TXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ -} - -/** - * @brief Determine whether UART RX Line is idle - * @param [in] ptr UART base address - * @retval false if uart RX line is not idle - */ -static inline bool uart_is_rxline_idle(UART_Type *ptr) -{ - return ((ptr->IIR2 & UART_IIR2_RXIDLE_FLAG_MASK) != 0U) ? true : false; -} - -/** - * @brief Clear UART RX Line Idle Flag - * @param [in] ptr UART base address - */ -static inline void uart_clear_rxline_idle_flag(UART_Type *ptr) -{ - ptr->IIR2 = UART_IIR2_RXIDLE_FLAG_MASK; /* Write-1-Clear Logic */ -} -#endif - -#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) -/** - * @brief Enable UART TX Idle Line detection logic - * @param [in] ptr UART base address - */ -static inline void uart_enable_txline_idle_detection(UART_Type *ptr) -{ - ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_MASK; -} - -/** - * @brief Disable UART TX Idle Line detection logic - * - * @param [in] ptr UART base address - */ -static inline void uart_disable_txline_idle_detection(UART_Type *ptr) -{ - ptr->IDLE_CFG &= ~UART_IDLE_CFG_TX_IDLE_EN_MASK; -} - -/** - * @brief Configure UART TX Line detection - * @param [in] ptr UART base address - * @param [in] txidle_config TXLine IDLE detection configuration - * @retval status_success if no error occurs - */ -hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config); - -#endif - - - -/** - * @brief Get status - * - * @param [in] ptr UART base address - * @retval current status - */ -static inline uint32_t uart_get_status(UART_Type *ptr) -{ - return ptr->LSR; -} - -/** - * @brief Check uart status according to the given status mask - * - * @note maybe clear other bits, such as PE/OE/LBREAK/ERRF bit. use uart_get_status API if you need to get these bits - * @param [in] ptr UART base address - * @param mask Status mask value to be checked against - * @retval true if any bit in given mask is set - * @retval false if none of any bit in given mask is set - */ -static inline bool uart_check_status(UART_Type *ptr, uart_stat_t mask) -{ - return ((ptr->LSR & mask) != 0U) ? true : false; -} - -/** - * @brief Get default config - * - * @param [in] ptr UART base address - * @param config Pointer to the buffer to save default values - */ -void uart_default_config(UART_Type *ptr, uart_config_t *config); - -/** - * @brief Initialization - * - * @param [in] ptr UART base address - * @param config Pointer to config struct - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config); - -/** - * @brief Send one byte after checking thresh hold status - * - * @param [in] ptr UART base address - * @param c Byte to be sent - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c); - -/** - * @brief Receive one byte after checking data ready status - * - * @param [in] ptr UART base address - * @param c Pointer to buffer to save the byte received on UART - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *c); - -/** - * @brief Try to receive one byte without checking data ready status - * - * @param [in] ptr UART base address - * @param c Pointer to buffer to save the byte received on UART - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_try_receive_byte(UART_Type *ptr, uint8_t *c); - -/** - * @brief Set uart signal output level - * - * @param [in] ptr UART base address - * @param signal Target signal - * @param level Target signal level - */ -void uart_set_signal_level(UART_Type *ptr, - uart_signal_t signal, - uart_signal_level_t level); - -/** - * @brief Flush sending buffer/fifo - * - * @param [in] ptr UART base address - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_flush(UART_Type *ptr); - -/** - * @brief Receive bytes blocking - * - * @param [in] ptr UART base address - * @param buf Pointer to the buffer to save received data - * @param size_in_byte Size in byte to be sent - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); - -/** - * @brief Send bytes blocking - * - * @param [in] ptr UART base address - * @param buf Pointer to the buffer to be sent - * @param size_in_byte Size in byte to be sent - * @retval status_success only if it succeeds - */ -hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *buf, uint32_t size_in_byte); - -/** - * @brief Sets UART baudrate. - * - * This function configures the UART module baud rate. This function is used to update - * the UART module baud rate after the UART module is initialized by the uart_init. - * - * @param ptr UART base address - * @param baudrate UART baudrate to be set - * @param src_clock_hz UART clock source frequency in Hz. - * @retval status_uart_no_suitable_baudrate_parameter_found Baudrate is not supported in the current clock source - * @retval status_success Set baudrate succeeded. - */ -hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz); - - -#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1) -/** - * @brief uart configure transfer trigger mode - * - * This function can configure uart to send data in fifo after being triggered - * - * @param ptr UART base address - * @param config uart_trig_config_t config - */ -void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config); - -/** - * @brief uart software trigger transmit - * - * This function immediately triggers the transfer, the transfer configed by uart_config_transfer_trig_mode() - * - * @param ptr UART base address - */ -static inline void uart_software_trig_transfer(UART_Type *ptr) -{ - ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; - ptr->MOTO_CFG |= UART_MOTO_CFG_SWTRG_MASK; -} - -/** - * @brief uart enable hardware trigger mode - * - * This function enable hardware trigger the transfer, the transfer start when hardware event occured - * - * @param ptr UART base address - * @param enable true for enable, false for disable - */ -static inline void uart_enable_hardware_trig_transfer(UART_Type *ptr, bool enable) -{ - if (enable) { - ptr->MOTO_CFG |= UART_MOTO_CFG_HWTRG_EN_MASK; - } else { - ptr->MOTO_CFG &= ~UART_MOTO_CFG_HWTRG_EN_MASK; - } -} - -/** - * @brief UART get data count in rx fifo - * - * @param ptr UART base address - * @retval data count - */ -static inline uint8_t uart_get_data_count_in_rx_fifo(UART_Type *ptr) -{ - return UART_LSR_RFIFO_NUM_GET(ptr->LSR); -} - -/** - * @brief UART get data count in tx fifo - * - * @param ptr UART base address - * @retval data count - */ -static inline uint8_t uart_get_data_count_in_tx_fifo(UART_Type *ptr) -{ - return UART_LSR_TFIFO_NUM_GET(ptr->LSR); -} -#endif - -#if defined(HPM_IP_FEATURE_UART_ADDR_MATCH) && (HPM_IP_FEATURE_UART_ADDR_MATCH == 1) -/** - * @brief uart enable 9bit transmit mode - * - * @param ptr UART base address - * @param enable true for enable, false for disable - */ -static inline void uart_enable_9bit_transmit_mode(UART_Type *ptr, bool enable) -{ - if (enable) { - ptr->ADDR_CFG |= UART_ADDR_CFG_TXEN_9BIT_MASK - | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK - | UART_ADDR_CFG_RXEN_9BIT_MASK; - } else { - ptr->ADDR_CFG &= ~(UART_ADDR_CFG_TXEN_9BIT_MASK - | UART_ADDR_CFG_RXEN_ADDR_MSB_MASK - | UART_ADDR_CFG_RXEN_9BIT_MASK); - } -} - -/** - * @brief uart enable address0 match - * - * @param ptr UART base address - * @param addr address value - */ -static inline void uart_enable_address0_match(UART_Type *ptr, uint8_t addr) -{ - ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR0_MASK; - ptr->ADDR_CFG |= UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_ADDR0_SET(addr); -} - -/** - * @brief uart enable address1 match - * - * @param ptr UART base address - * @param addr address value - */ -static inline void uart_enable_address1_match(UART_Type *ptr, uint8_t addr) -{ - ptr->ADDR_CFG &= ~UART_ADDR_CFG_ADDR1_MASK; - ptr->ADDR_CFG |= UART_ADDR_CFG_A1_EN_MASK | UART_ADDR_CFG_ADDR1_SET(addr); -} - -/** - * @brief uart disable address0 match - * - * @param ptr UART base address - */ -static inline void uart_disable_address0_match(UART_Type *ptr) -{ - ptr->ADDR_CFG &= ~UART_ADDR_CFG_A0_EN_MASK; -} - -/** - * @brief uart disable address1 match - * - * @param ptr UART base address - */ -static inline void uart_disable_address1_match(UART_Type *ptr) -{ - ptr->ADDR_CFG &= ~UART_ADDR_CFG_A1_EN_MASK; -} - -/** - * @brief uart disable address match(address0 and address1) - * - * @param ptr UART base address - */ -static inline void uart_disable_address_match(UART_Type *ptr) -{ - ptr->ADDR_CFG &= ~(UART_ADDR_CFG_A0_EN_MASK | UART_ADDR_CFG_A1_EN_MASK); -} - -/** - * @brief Determine whether address match for 9bit mode - * @param [in] ptr UART base address - * @retval false if uart address is not match - */ -static inline bool uart_is_addr_match(UART_Type *ptr) -{ - return ((ptr->IIR2 & UART_IIR2_ADDR_MATCH_MASK) != 0U) ? true : false; -} - -/** - * @brief Clear UART address match Flag - * @param [in] ptr UART base address - */ -static inline void uart_clear_addr_match_flag(UART_Type *ptr) -{ - ptr->IIR2 = UART_IIR2_ADDR_MATCH_MASK; /* Write-1-Clear Logic */ -} - -/** - * @brief Determine whether address match and rx idle for 9bit mode - * @param [in] ptr UART base address - * @retval false if uart address is not match and not rx idle - */ -static inline bool uart_is_addr_match_and_rxidle(UART_Type *ptr) -{ - return ((ptr->IIR2 & UART_IIR2_ADDR_MATCH_IDLE_MASK) != 0U) ? true : false; -} - -/** - * @brief Clear UART address match and rxidle Flag - * @param [in] ptr UART base address - */ -static inline void uart_clear_addr_match_and_rxidle_flag(UART_Type *ptr) -{ - ptr->IIR2 = UART_IIR2_ADDR_MATCH_IDLE_MASK; /* Write-1-Clear Logic */ -} - -/** - * @brief Determine whether data lost for 9bit mode - * @param [in] ptr UART base address - * @retval false if uart data is not lost - */ -static inline bool uart_is_data_lost(UART_Type *ptr) -{ - return ((ptr->IIR2 & UART_IIR2_DATA_LOST_MASK) != 0U) ? true : false; -} - -/** - * @brief Clear UART data lost Flag - * @param [in] ptr UART base address - */ -static inline void uart_clear_data_lost_flag(UART_Type *ptr) -{ - ptr->IIR2 = UART_IIR2_DATA_LOST_MASK; /* Write-1-Clear Logic */ -} -#endif - -/** - * @brief Write RTS level for uart modem mode - * - * @param [in] ptr UART base address - * @param high RTS set to high when it is set to true - */ -static inline void uart_modem_write_rts_pin(UART_Type *ptr, uint8_t high) -{ - if (high == true) { - ptr->MCR &= ~UART_MCR_RTS_MASK; - } else { - ptr->MCR |= UART_MCR_RTS_MASK; - } -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_UART_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h deleted file mode 100644 index 80573aaea7a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_usb_drv.h +++ /dev/null @@ -1,794 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_USB_DRV_H -#define HPM_USB_DRV_H -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_common.h" -#include "hpm_usb_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief USB driver APIs - * @defgroup usb_interface USB driver APIs - * @ingroup communication_interfaces - * @{ - */ - -/*--------------------------------------------------------------------- - * Macro Constant Declarations - *--------------------------------------------------------------------- - */ -#define USB_PHY_INIT_DELAY_COUNT (16U) /**< a delay count for USB phy initialization */ -#define USB_HOST_FRAMELIST_SIZE (8U) /**< a frame list size in USB host mode */ - -/*--------------------------------------------------------------------- - * Macro Enum Declarations - *--------------------------------------------------------------------- - */ -/** - * @brief USB transfer direction types - */ -typedef enum { - usb_dir_out = 0, - usb_dir_in = 1, - usb_dir_in_mask = 0x80 -} usb_dir_t; /**< usb_dir_t */ - -/** - * @brief USB transfer types - */ -typedef enum { - usb_xfer_control = 0, - usb_xfer_isochronous, - usb_xfer_bulk, - usb_xfer_interrupt -} usb_xfer_type_t; /**< usb_xfer_type_t */ - -/** - * @brief USB controller work modes - */ -typedef enum { - usb_ctrl_mode_otg = 0, - usb_ctrl_mode_device = 2, - usb_ctrl_mode_host = 3 -} usb_controller_mode_t; /**< usb_controller_mode_t */ - -/** - * @brief USB line state - */ -typedef enum { - usb_line_state0 = 0, - usb_line_state1 = 1, - usb_line_state2 = 2 -} usb_line_state_t; /**< usb_line_state_t */ - -/** - * @brief USB transceiver - */ -typedef enum { - usb_tran_parallel = 0, - usb_tran_serial = 1 -} usb_transceiver_t; /**< usb_transceiver_t */ - -/** - * @brief USB test modes - */ -typedef enum { - usb_test_mode_disable = 0, - usb_test_j_state, - usb_test_k_state, - usb_test_se0_nak, - usb_test_packet, - usb_test_force_hs, - usb_test_force_fs, - usb_test_force_ls, -} usb_test_mode_t; /**< usb_test_mode_t */ - -/** - * @brief USB vbus wakeup source - */ -typedef enum { - usb_vbus_wakeup_vbus_valid = 0, - usb_vbus_wakeup_session_valid, -} usb_vbus_wakeup_source_t; /**< usb_vbus_wakeup_source_t */ - -/*--------------------------------------------------------------------- - * Structure Declarations - *--------------------------------------------------------------------- - */ -/** - * @brief Control request structure - */ -typedef struct __attribute__ ((packed)) { - union { - struct __attribute__ ((packed)) { - uint8_t recipient : 5; - uint8_t type : 2; - uint8_t direction : 1; - } bmRequestType_bit; - - uint8_t bmRequestType; - }; - - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} usb_control_request_t; - -/** - * @brief Endpoint config structure - */ -typedef struct { - uint8_t xfer; - uint8_t ep_addr; - uint16_t max_packet_size; -} usb_endpoint_config_t; - -#if defined __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/*--------------------------------------------------------------------- - * Common API - *--------------------------------------------------------------------- - */ - -/** - * @brief Get the mask of all enabled interrupts - * - * @param[in] ptr A USB peripheral base address. - * @retval Mask of all enabled interrupts. - */ -static inline uint32_t usb_get_interrupts(USB_Type *ptr) -{ - return ptr->USBINTR; -} - -/** - * @brief Enable interrupts - * - * @param[in] ptr A USB peripheral base address - * @param[in] mask Mask value for interrupt events - */ -static inline void usb_enable_interrupts(USB_Type *ptr, uint32_t mask) -{ - ptr->USBINTR |= mask; -} - -/** - * @brief Get all USB status flags - * - * @param[in] ptr A USB peripheral base address - * @retval The USB interrupt status flags - */ -static inline uint32_t usb_get_status_flags(USB_Type *ptr) -{ - return ptr->USBSTS; -} - -/** - * @brief Clear status flags - * - * Only the specified flags can be cleared by writing USBSTS register. - * - * @param[in] ptr A USB peripheral base address - * @param[in] mask Mask value for flags to be cleared. - */ - -static inline void usb_clear_status_flags(USB_Type *ptr, uint32_t mask) -{ - ptr->USBSTS = mask; -} - -/** - * @brief Enable otg vbus wakeup - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otg_enable_vbus_wakeup(USB_Type *ptr) -{ - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK; -} - -/** - * @brief Disbable otg vbus wakeup - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otg_disable_vbus_wakeup(USB_Type *ptr) -{ - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK; -} - -/** - * @brief Set otg vbus wakeup source - * - * @param[in] ptr A USB peripheral base address - * @param[in] src wakeup source, @ref usb_vbus_wakeup_source_t - */ -static inline void usb_otg_set_vbus_wakeup_source(USB_Type *ptr, usb_vbus_wakeup_source_t src) -{ - ptr->OTG_CTRL0 = (ptr->OTG_CTRL0 & ~USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) | USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(src); -} - -/** - * @brief Enable otg wakeup interrupt - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otg_enable_wakeup_int(USB_Type *ptr) -{ - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK; -} - -/** - * @brief Disable otg wakeup interrupt - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otg_disable_wakeup_int(USB_Type *ptr) -{ - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK; -} - -/** - * @brief Get otg wakeup status flags - * - * @param[in] ptr A USB peripheral base address - * @retval The USB otg wakeup interrupt status flag - */ -static inline bool usb_get_otg_wakeup_int_flag(USB_Type *ptr) -{ - return (USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(ptr->TOP_STATUS) != 0) ? true : false; -} - -/** - * @brief Get USB suspend status - * - * @param[in] ptr A USB peripheral base address - * @retval The USB controller suspend status - */ -static inline uint8_t usb_get_suspend_status(USB_Type *ptr) -{ - return USB_PORTSC1_SUSP_GET(ptr->PORTSC1); -} - -/** - * @brief Get USB reset status - * - * @param[in] ptr A USB peripheral base address - * @retval The USB controller reset status - */ -static inline bool usb_get_port_reset_status(USB_Type *ptr) -{ - return USB_PORTSC1_PR_GET(ptr->PORTSC1); -} - -/** - * @brief Get USB current connect status - * - * @param[in] ptr A USB peripheral base address - * @retval The USB controller reset status - */ -static inline bool usb_get_port_ccs(USB_Type *ptr) -{ - return USB_PORTSC1_CCS_GET(ptr->PORTSC1); -} - -/** - * @brief Get USB port speed status - * - * @param[in] ptr A USB peripheral base address - * @retval The USB controller port speed status - */ -static inline uint8_t usb_get_port_speed(USB_Type *ptr) -{ - return USB_PORTSC1_PSPD_GET(ptr->PORTSC1); -} - -/** - * @brief Set port test control mode - * - * @param[in] ptr A USB peripheral base address - * @param[in] test_mode usb test mode, @ref usb_test_mode_t - */ -static inline void usb_set_port_test_mode(USB_Type *ptr, usb_test_mode_t test_mode) -{ - ptr->PORTSC1 = (ptr->PORTSC1 & ~USB_PORTSC1_PTC_MASK) | USB_PORTSC1_PTC_SET(test_mode); -} - -/** - * @brief USB set port suspend - * - * @param[in] ptr A USB peripheral base address - * @param[in] suspend true - suspend, false - not suspend - */ -static inline void usb_set_port_suspend(USB_Type *ptr, bool suspend) -{ - ptr->PORTSC1 = (ptr->PORTSC1 & ~USB_PORTSC1_SUSP_MASK) | USB_PORTSC1_SUSP_SET(suspend); -} - -/** - * @brief USB force port resume - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_force_port_resume(USB_Type *ptr) -{ - ptr->PORTSC1 |= USB_PORTSC1_FPR_MASK; -} - -/** - * @brief USB phy enter low power suspend - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phy_enter_low_power_suspend(USB_Type *ptr) -{ - ptr->PORTSC1 |= USB_PORTSC1_PHCD_MASK; -} - -/** - * @brief USB phy exit low power suspend - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phy_exit_low_power_suspend(USB_Type *ptr) -{ - ptr->PORTSC1 &= ~USB_PORTSC1_PHCD_MASK; - /* otg utmi clock detection */ - ptr->PHY_STATUS |= USB_PHY_STATUS_UTMI_CLK_VALID_MASK; /* write 1 to clear valid status */ - while (USB_PHY_STATUS_UTMI_CLK_VALID_GET(ptr->PHY_STATUS) == 0) { /* get utmi clock status */ - ; - } -} - -/** - * @brief Get phy session valid flag - * - * @param[in] ptr A USB peripheral base address - * @retval The phy session valid flag - */ -static inline bool usb_phy_get_session_valid_flag(USB_Type *ptr) -{ - return (USB_PHY_STATUS_UTMI_SESS_VALID_GET(ptr->PHY_STATUS) != 0) ? true : false; -} - -/** - * @brief enable otgsc session valid change interrupt - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otgsc_enable_session_valid_chg_int(USB_Type *ptr) -{ - ptr->OTGSC |= USB_OTGSC_ASVIE_MASK; -} - -/** - * @brief disable otgsc session valid change interrupt - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otgsc_disable_session_valid_chg_int(USB_Type *ptr) -{ - ptr->OTGSC &= ~USB_OTGSC_ASVIE_MASK; -} - -/** - * @brief get otgsc session valid change flag - * - * @param[in] ptr A USB peripheral base address - * @retval The otgsc session valid flag - */ -static inline bool usb_otgsc_get_session_valid_chg_flag(USB_Type *ptr) -{ - return (USB_OTGSC_ASVIS_SET(ptr->OTGSC) != 0) ? true : false; -} - -/** - * @brief clear otgsc session valid change flag - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_otgsc_clear_session_valid_chg_flag(USB_Type *ptr) -{ - ptr->OTGSC |= USB_OTGSC_ASVIS_MASK; -} - -/** - * @brief Get otgsc session valid flag - * - * @param[in] ptr A USB peripheral base address - * @retval The otgsc session valid flag - */ -static inline bool usb_otgsc_get_session_valid_flag(USB_Type *ptr) -{ - return (USB_OTGSC_ASV_GET(ptr->OTGSC) != 0) ? true : false; -} - -/** - * @brief Initialize USB phy - * - * @param[in] ptr A USB peripheral base address - */ -void usb_phy_init(USB_Type *ptr); - -/** - * @brief USB phy get line status - * - * @param[in] ptr A USB peripheral base address - */ -static inline uint8_t usb_phy_get_line_state(USB_Type *ptr) -{ - return USB_PHY_STATUS_LINE_STATE_GET(ptr->PHY_STATUS); -} - -/** - * @brief USB phy using internal vbus - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phy_using_internal_vbus(USB_Type *ptr) -{ - ptr->PHY_CTRL0 |= (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) - | (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK); -} - -/** - * @brief USB phy using external vbus - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phy_using_external_vbus(USB_Type *ptr) -{ - ptr->PHY_CTRL0 &= ~((USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) - | (USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK | USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK)); -} - -/** - * @brief USB phy disconnect dp/dm pins pulldown resistance - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phy_disable_dp_dm_pulldown(USB_Type *ptr) -{ - ptr->PHY_CTRL0 |= 0x001000E0u; -} - -/** - * @brief USB phy connect dp/dm pins pulldown resistance - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phy_enable_dp_dm_pulldown(USB_Type *ptr) -{ - ptr->PHY_CTRL0 &= ~0x001000E0u; -} - -/** - * @brief Set phyctrl1 not utmi suspend - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_phyctrl1_set_not_utmi_suspend(USB_Type *ptr) -{ - ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; -} - -/*--------------------------------------------------------------------- - * Device API - *--------------------------------------------------------------------- - */ - -/** - * @brief USB device bus reset - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep0_max_packet_size The maximum packet size of endpoint 0 - */ -void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size); - -/** - * @brief Initialize controller to device mode - * - * @param[in] ptr A USB peripheral base address - */ -void usb_dcd_init(USB_Type *ptr); - -/** - * @brief Deinitialize controller to device - * - * @param[in] ptr A USB peripheral base address - */ -void usb_dcd_deinit(USB_Type *ptr); - -/** - * @brief Wakeup from host - * - * @param[in] ptr A USB peripheral base address - */ -void usb_dcd_remote_wakeup(USB_Type *ptr); - -/** - * @brief Open an endpoint - * - * @param[in] ptr A USB peripheral base address - * @param[in] config A pointer to the specified endpoint config struct - */ -void usb_dcd_edpt_open(USB_Type *ptr, usb_endpoint_config_t *config); - -/** - * @brief get a specified endpoint type - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep_addr Endpoint address - */ -uint8_t usb_dcd_edpt_get_type(USB_Type *ptr, uint8_t ep_addr); - -/** - * @brief Submit a transfer - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep_idx An index of the specified endpoint - */ -void usb_dcd_edpt_xfer(USB_Type *ptr, uint8_t ep_idx); - -/** - * @brief Stall endpoint - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep_addr An address of the specified endpoint - */ -void usb_dcd_edpt_stall(USB_Type *ptr, uint8_t ep_addr); - -/** - * @brief Clear stall - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep_addr An address of the specified endpoint - */ -void usb_dcd_edpt_clear_stall(USB_Type *ptr, uint8_t ep_addr); - -/** - * @brief Clear stall - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep_addr An address of the specified endpoint - * @retval The status of endpoint stall, true is stall, false is not stall - */ -bool usb_dcd_edpt_check_stall(USB_Type *ptr, uint8_t ep_addr); - -/** - * @brief Close a specified endpoint - * - * @param[in] ptr A USB peripheral base address - * @param[in] ep_addr An address of the specified endpoint - */ -void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr); - -/** - * @brief Connect by enabling internal pull-up resistor on D+/D- - * - * @param[in] ptr A USB peripheral base address - */ -void usb_dcd_connect(USB_Type *ptr); - -/** - * @brief Disconnect by disabling internal pull-up resistor on D+/D- - * - * @param[in] ptr A USB peripheral base address - */ -void usb_dcd_disconnect(USB_Type *ptr); - -/** - * @brief Get setup status of endpoint - * - * @param[in] ptr A USB peripheral base address - * @retval The status of setup endpoint - */ -static inline uint32_t usb_dcd_get_edpt_setup_status(USB_Type *ptr) -{ - return ptr->ENDPTSETUPSTAT; -} - -/** - * @brief Clear the setup status of all specified endpoints - * - * @param[in] ptr A USB peripheral base address - * @param[in] mask A mask of all specified endpoints - */ -static inline void usb_dcd_clear_edpt_setup_status(USB_Type *ptr, uint32_t mask) -{ - ptr->ENDPTSETUPSTAT = mask; -} - -/** - * @brief Set address - * - * @param[in] ptr A USB peripheral base address - * @param[in] dev_addr An assigned endpoint address from USB host - */ -static inline void usb_dcd_set_address(USB_Type *ptr, uint8_t dev_addr) -{ - ptr->DEVICEADDR = USB_DEVICEADDR_USBADR_SET(dev_addr) | USB_DEVICEADDR_USBADRA_MASK; -} - -/** - * @brief Set endpoint list address - * - * @param[in] ptr A USB peripheral base address - * @param[in] addr A start address of the endpoint qtd list - */ -static inline void usb_dcd_set_edpt_list_addr(USB_Type *ptr, uint32_t addr) -{ - ptr->ENDPTLISTADDR = addr & USB_ENDPTLISTADDR_EPBASE_MASK; -} - -/** - * @brief Get device address - * - * @param[in] ptr A USB peripheral base address - * @retval The endpoint address - */ -static inline uint8_t usb_dcd_get_device_addr(USB_Type *ptr) -{ - return USB_DEVICEADDR_USBADR_GET(ptr->DEVICEADDR); -} - -/** - * @brief Get complete status of endpoint - * - * @param[in] ptr A USB peripheral base address - * @retval The complete status od endpoint - */ -static inline uint32_t usb_dcd_get_edpt_complete_status(USB_Type *ptr) -{ - return ptr->ENDPTCOMPLETE; -} - -/** - * @brief Clear complete status of endpoint - * - * @param[in] ptr A USB peripheral base address - * @param[in] mask A mask of the specified endpoints - */ -static inline void usb_dcd_clear_edpt_complete_status(USB_Type *ptr, uint32_t mask) -{ - ptr->ENDPTCOMPLETE = mask; -} - -/*--------------------------------------------------------------------- - * Host API - *--------------------------------------------------------------------- - */ -/** - * @brief Initialize controller to host mode - * - * @param[in] ptr A USB peripheral base address - * @param[in] int_mask A mask of all required interrupts - * @param[in] framelist_size A size of the frame list - */ -bool usb_hcd_init(USB_Type *ptr, uint32_t int_mask, uint16_t framelist_size); - -/** - * @brief Initialize controller to host modeHost Reset port - * - * @param[in] ptr A USB peripheral base address - */ -void usb_hcd_port_reset(USB_Type *ptr); - -/** - * @brief Initialize controller to host modeHost set command register - * - * @param[in] ptr A USB peripheral base address - * @param[in] mask A mask of all required commands - */ -static inline void usb_hcd_set_command(USB_Type *ptr, uint32_t mask) -{ - ptr->USBCMD |= mask; -} - -/** - * @brief Get frame index - * - * @param[in] ptr A USB peripheral base address - * @retval A index of the current frame list - */ -static inline uint32_t usb_hcd_get_frame_index(USB_Type *ptr) -{ - return ptr->FRINDEX; -} - -/** - * @brief Get port connect status change - * - * @param[in] ptr A USB peripheral base address - * @retval A connect status change - */ -static inline bool usb_hcd_get_port_csc(USB_Type *ptr) -{ - return USB_PORTSC1_CSC_GET(ptr->PORTSC1); -} - -/** - * @brief Set power ctrl polarity - * - * @param[in] ptr A USB peripheral base address - * @param[in] high true - vbus high level enable, false - vbus low level enable - */ -static inline void usb_hcd_set_power_ctrl_polarity(USB_Type *ptr, bool high) -{ - if (high) { - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_POWER_MASK_MASK; - } else { - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_POWER_MASK_MASK; - } -} - -/** - * @brief Enable port power - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_hcd_enable_port_power(USB_Type *ptr) -{ - ptr->PORTSC1 |= USB_PORTSC1_PP_MASK; -} - -/** - * @brief Get port connect status changeSet async list address - * - * @param[in] ptr A USB peripheral base address - * @param[in] addr An the start address of the async endpoint list - */ -static inline void usb_hcd_set_async_list_addr(USB_Type *ptr, uint32_t addr) -{ - ptr->ASYNCLISTADDR = addr & USB_ASYNCLISTADDR_ASYBASE_MASK; -} - -/** - * @brief Set periodic list address - * - * @param[in] ptr A USB peripheral base address - * @param[in] addr An start address of the periodic endpoint list - */ -static inline void usb_hcd_set_periodic_list_addr(USB_Type *ptr, uint32_t addr) -{ - ptr->PERIODICLISTBASE = addr & USB_PERIODICLISTBASE_BASEADR_MASK; -} - -/** - * @brief Start hcd controller - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_hcd_run(USB_Type *ptr) -{ - ptr->USBCMD |= USB_USBCMD_RS_MASK; -} - -/** - * @brief Stop hcd controller - * - * @param[in] ptr A USB peripheral base address - */ -static inline void usb_hcd_stop(USB_Type *ptr) -{ - ptr->USBCMD &= ~USB_USBCMD_RS_MASK; -} - -#if defined __cplusplus -} -#endif /* __cplusplus */ - -/** @} */ -#endif /* HPM_USB_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h deleted file mode 100644 index 3c4dffb0d4f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vad_drv.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_VAD_DRV_H -#define HPM_VAD_DRV_H - -#include "hpm_common.h" -#include "hpm_vad_regs.h" - -/** - * @brief VAD driver APIs - * @defgroup vad_interface VAD driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief vad event - */ -#define VAD_EVENT_VAD (1U << 7) -#define VAD_EVENT_FIFO_DATA_AVAILABLE (1U << 6) -#define VAD_EVENT_MEMBUF_EMPTY (1U << 5) -#define VAD_EVENT_FIFO_OVERFLOW (1U << 4) -#define VAD_EVENT_IIR_OVERLOAD (1U << 3) -#define VAD_EVENT_IIR_OVERFLOW (1U << 2) -#define VAD_EVENT_CIC_OVERLOAD_ERROR (1U << 1) -#define VAD_EVENT_CIC_STA_ERROR (1U << 0) - -/** - * @brief vad config - */ -typedef struct vad_config { - bool enable_buffer; - bool enable_pdm_clock_out; - bool enable_two_channels; - uint8_t capture_delay; - uint8_t pdm_half_div; - uint8_t fifo_threshold; - uint8_t post_scale; - bool channel_polarity_high[2]; -} vad_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief set capture deplay cycle - * - * @param [in] ptr VAD base address - * @param [in] delay delay cycle value - */ -static inline void vad_set_capture_delay(VAD_Type *ptr, uint8_t delay) -{ - ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_CAPT_DLY_MASK) - | VAD_CTRL_CAPT_DLY_SET(delay); -} - -/** - * @brief set pdm clock hald_divider - * - * @param [in] ptr VAD base address - * @param [in] div divider value - */ -static inline void vad_set_pdm_clock_half_div(VAD_Type *ptr, uint8_t div) -{ - ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_PDM_CLK_HFDIV_MASK) - | VAD_CTRL_PDM_CLK_HFDIV_SET(div); -} - -/** - * @brief enable irq - * - * @param [in] ptr VAD base address - * @param [in] irq_mask irq mask value - */ -static inline void vad_enable_irq(VAD_Type *ptr, uint32_t irq_mask) -{ - ptr->CTRL |= irq_mask; -} - -/** - * @brief disable irq - * - * @param [in] ptr VAD base address - * @param [in] irq_mask irq mask value - */ -static inline void vad_disable_irq(VAD_Type *ptr, uint32_t irq_mask) -{ - ptr->CTRL &= ~irq_mask; -} - -/** - * @brief disable buffer - * - * @param [in] ptr VAD base address - */ -static inline void vad_disable_buffer(VAD_Type *ptr) -{ - ptr->CTRL |= VAD_CTRL_MEMBUF_DISABLE_MASK; -} - -/** - * @brief enable buffer - * - * @param [in] ptr VAD base address - */ -static inline void vad_enable_buffer(VAD_Type *ptr) -{ - ptr->CTRL &= ~VAD_CTRL_MEMBUF_DISABLE_MASK; -} - -/** - * @brief set fifo threshold - * - * @param [in] ptr VAD base address - * @param [in] threshold fifo threshold value - */ -static inline void vad_set_fifo_threshold(VAD_Type *ptr, uint8_t threshold) -{ - ptr->CTRL = (ptr->CTRL & ~(VAD_CTRL_FIFO_THRSH_MASK)) - | VAD_CTRL_FIFO_THRSH_SET(threshold); -} - -/** - * @brief enable pdm clock out - * - * @param [in] ptr VAD base address - */ -static inline void vad_enable_pdm_clock_out(VAD_Type *ptr) -{ - ptr->CTRL |= VAD_CTRL_PDM_CLK_OE_MASK; -} - -/** - * @brief disable pdm clock out - * - * @param [in] ptr VAD base address - */ -static inline void vad_disable_pdm_clock_out(VAD_Type *ptr) -{ - ptr->CTRL &= ~VAD_CTRL_PDM_CLK_OE_MASK; -} - -/** - * @brief set pdm clock polarity - * - * @param [in] ptr VAD base address - * @param [in] level clock polarity - */ -static inline void vad_set_pdm_clock_capture_level(VAD_Type *ptr, uint8_t level) -{ - ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_CH_POL_MASK) - | VAD_CTRL_CH_POL_SET(level); -} - -/** - * @brief set channel number - * - * @param [in] ptr VAD base address - * @param [in] two_channels: - * @arg true: set two channels - * @arg false: set one channel - */ -static inline void vad_set_channel_number(VAD_Type *ptr, bool two_channels) -{ - ptr->CTRL = (ptr->CTRL & ~VAD_CTRL_CHNUM_MASK) - | (two_channels ? VAD_CTRL_CHNUM_MASK : 0); -} - -/** - * @brief get status - * - * @param [in] ptr VAD base address - * @retval ST register value - */ -static inline uint32_t vad_get_status(VAD_Type *ptr) -{ - return ptr->ST; -} - -/** - * @brief slear status - * - * @param [in] ptr VAD base address - * @param [in] mask status mask value - */ -static inline void vad_clear_status(VAD_Type *ptr, uint32_t mask) -{ - ptr->ST |= mask; -} - -/** - * @brief get data - * - * @param [in] ptr VAD base address - * @retval OFIFO register value - */ -static inline uint32_t vad_get_data(VAD_Type *ptr) -{ - return ptr->OFIFO; -} - -/** - * @brief software reset - * - * @param [in] ptr VAD base address - */ -static inline void vad_software_reset(VAD_Type *ptr) -{ - ptr->RUN |= VAD_RUN_SFTRST_MASK; - ptr->RUN &= ~VAD_RUN_SFTRST_MASK; -} - -/** - * @brief start - * - * @param [in] ptr VAD base address - */ -static inline void vad_start(VAD_Type *ptr) -{ - ptr->RUN |= VAD_RUN_VAD_EN_MASK; -} - -/** - * @brief stop - * - * @param [in] ptr VAD base address - */ -static inline void vad_stop(VAD_Type *ptr) -{ - ptr->RUN &= ~VAD_RUN_VAD_EN_MASK; -} - -/** - * @brief check whether vad is running - * - * @param [in] ptr VAD base address - * @retval true if vad is running - */ -static inline bool vad_is_running(VAD_Type *ptr) -{ - return ptr->RUN & VAD_RUN_VAD_EN_MASK; -} - -/** - * @brief enable fifo - * - * @param [in] ptr VAD base address - */ -static inline void vad_enable_fifo(VAD_Type *ptr) -{ - ptr->OFIFO_CTRL |= VAD_OFIFO_CTRL_EN_MASK; -} - -/** - * @brief disable fifo - * - * @param [in] ptr VAD base address - */ -static inline void vad_disable_fifo(VAD_Type *ptr) -{ - ptr->OFIFO_CTRL &= ~VAD_OFIFO_CTRL_EN_MASK; -} - -/** - * @brief get coefficient value - * - * @param [in] ptr VAD base address - * @param [in] index coefficient index - */ -static inline uint32_t vad_get_coef_value(VAD_Type *ptr, uint32_t index) -{ - return ptr->COEF[index]; -} - -/** - * @brief set ouptput value post scale - * - * @param [in] ptr VAD base address - * @param [in] post_scale post scale value - */ -static inline void vad_set_post_scale(VAD_Type *ptr, uint8_t post_scale) -{ - ptr->CIC_CFG |= (ptr->CIC_CFG & ~VAD_CIC_CFG_POST_SCALE_MASK) - | VAD_CIC_CFG_POST_SCALE_SET(post_scale); -} - -/** - * @brief set sampling signal amplitude limits - * - * @param [in] ptr VAD base address - * @param [in] high high limit - * @param [in] low low limit - */ -static inline void vad_set_amplify(VAD_Type *ptr, uint16_t high, uint16_t low) -{ - ptr->DEC_CTRL2 = VAD_DEC_CTRL2_AMP_HIGH_SET(high) - | VAD_DEC_CTRL2_AMP_LOW_SET(low); -} - -/** - * @brief get default config - * - * @param [in] ptr VAD base address - * @param [out] config vad_config_t - */ -void vad_get_default_config(VAD_Type *ptr, vad_config_t *config); - -/** - * @brief initialization - * - * @param [in] ptr VAD base address - * @param [in] config vad_config_t - */ -void vad_init(VAD_Type *ptr, vad_config_t *config); - -/** - * @brief reset - * - * @param [in] ptr VAD base address - */ -void vad_reset(VAD_Type *ptr); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_VAD_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vsc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vsc_drv.h deleted file mode 100644 index f4fb5a81915..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_vsc_drv.h +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_VSC_DRV_H -#define HPM_VSC_DRV_H - -#include "hpm_common.h" -#include "hpm_vsc_regs.h" - -/** - * @brief VSC driver APIs - * @defgroup vsc_interface VSC driver APIs - * @ingroup motor_interfaces - * @{ - */ - -/** - * @brief vsc phase mode - * - */ -typedef enum vsc_phase_mode { - vsc_abc_phase = 0, - vsc_ab_phase = 1, -} vsc_phase_mode_t; /**< vsc_phase_mode_t */ - -/** - * @brief vsc data operation mode - * - */ -typedef enum vsc_data_opr_mode { - vsc_data_opr_plus_mul_1 = 0, - vsc_data_opr_plus_mul_2 = 1, - vsc_data_opr_plus_div_2 = 5, - vsc_data_opr_plus_div_3 = 6, - vsc_data_opr_plus_div_4 = 7, - vsc_data_opr_minus_mul_1 = 8, - vsc_data_opr_minus_mul_2 = 9, - vsc_data_opr_minus_div_2 = 13, - vsc_data_opr_minus_div_3 = 14, - vsc_data_opr_minus_div_4 = 15 -} vsc_data_opr_mode_t; /**< vsc_data_opr_mode_t */ - -/** - * @brief vsc select adc instance - * - */ -typedef enum vsc_adc_sel { - vsc_sel_adc0 = 1, - vsc_sel_adc1 = 2, - vsc_sel_adc2 = 3 -} vsc_adc_sel_t; /**< vsc_adc_sel_t */ - -/** - * @brief vsc position capture mode - * - */ -typedef enum vsc_pos_cap_mode { - vsc_pos_use_last_data_when_adc_sample_finish = 0, - vsc_pos_use_first_data_after_adc_sample_start = 1, - vsc_pos_use_last_data_before_adc_sample_start = 2 -} vsc_pos_cap_mode_t; /**< vsc_pos_cap_mode_t */ - -/** - * @brief vsc select adc timestamp - * - */ -typedef enum vsc_timestamp_sel { - vsc_timestamp_sel_value_a = 1, - vsc_timestamp_sel_value_b = 2, - vsc_timestamp_sel_value_c = 3 -} vsc_timestamp_sel_t; /**< vsc_timestamp_sel_t */ - -/** - * @brief vsc irq mask bit - * - */ -typedef enum vsc_irq_mask { - vsc_irq_convert_done = BIT0_MASK, - vsc_irq_abc_over_tolerate = BIT1_MASK, - vsc_irq_c_overflow = BIT2_MASK, - vsc_irq_b_overflow = BIT3_MASK, - vsc_irq_a_overflow = BIT4_MASK, - vsc_irq_adc2_cap_not_enough = BIT5_MASK, - vsc_irq_adc1_cap_not_enough = BIT6_MASK, - vsc_irq_adc0_cap_not_enough = BIT7_MASK, - vsc_irq_pos_timeout = BIT8_MASK, - vsc_irq_adc2_timeout = BIT9_MASK, - vsc_irq_adc1_timeout = BIT10_MASK, - vsc_irq_adc0_timeout = BIT11_MASK, - vsc_irq_convert_conflict = BIT12_MASK -} vsc_irq_mask_t; - -/** - * @brief adc config structure - */ -typedef struct { - vsc_adc_sel_t adc_sel; - uint8_t adc_chn; - uint32_t adc_offset; -} vsc_adc_config_t; - -/** - * @brief vsc config structure - */ -typedef struct { - vsc_data_opr_mode_t opr_0; - vsc_data_opr_mode_t opr_1; - vsc_data_opr_mode_t opr_2; - vsc_data_opr_mode_t opr_3; -} vsc_data_opr_config_t; - -/** - * @brief vsc config structure - */ -typedef struct { - vsc_phase_mode_t phase_mode; - uint8_t a_data_cnt; - uint8_t b_data_cnt; - uint8_t c_data_cnt; - vsc_data_opr_config_t a_data_opr_config; - vsc_data_opr_config_t b_data_opr_config; - vsc_data_opr_config_t c_data_opr_config; - vsc_adc_config_t a_adc_config; - vsc_adc_config_t b_adc_config; - vsc_adc_config_t c_adc_config; - vsc_pos_cap_mode_t pos_cap_mode; - uint16_t pole_pairs; -} vsc_config_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief vsc enable or disable - * - * @param[in] vsc VSC base address - * @param[in] enable true-enable, false-disable - */ -static inline void vsc_set_enable(VSC_Type *vsc, bool enable) -{ - if (enable) { - vsc->ABC_MODE |= VSC_ABC_MODE_ENABLE_VSC_MASK; - } else { - vsc->ABC_MODE &= ~VSC_ABC_MODE_ENABLE_VSC_MASK; - } -} - -/** - * @brief vsc config position capture mode - * - * @param[in] vsc VSC base address - * @param[in] mode @ref vsc_pos_cap_mode_t - */ -static inline void vsc_config_pos_capture_mode(VSC_Type *vsc, vsc_pos_cap_mode_t mode) -{ - vsc->TIMELOCK = (vsc->TIMELOCK & ~(VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK)) - | VSC_TIMELOCK_POSITION_CAPTURE_MODE_SET(mode); -} - -/** - * @brief vsc config adc timestamp - * - * @param[in] vsc VSC base address - * @param[in] select timestamp select from value a/b/c. @ref vsc_timestamp_sel_t - * @param[in] num timestamp use which number index of @ref vsc_timestamp_sel_t used. - */ -static inline void vsc_config_adc_timestamp(VSC_Type *vsc, vsc_timestamp_sel_t select, uint8_t num) -{ - vsc->TIMELOCK = (vsc->TIMELOCK & ~(VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK | VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK)) - | VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SET(select) | VSC_TIMELOCK_VALUE_COUNTER_SEL_SET(num); -} - -/** - * @brief vsc set irq enable or disable - * @param [in] vsc CLC base address - * @param [in] irq_mask irq mask, @ref vsc_irq_mask_t - * @param [in] enable enable or disable - * @arg true enable - * @arg false disable - */ -static inline void vsc_set_irq_enable(VSC_Type *vsc, uint32_t irq_mask, bool enable) -{ - if (enable) { - vsc->IRQ_ENABLE |= irq_mask; - } else { - vsc->IRQ_ENABLE &= ~irq_mask; - } -} - -/** - * @brief vsc get irq status - * @param [in] vsc CLC base address - - * @retval irq status. - */ -static inline uint32_t vsc_get_irq_status(VSC_Type *vsc) -{ - return vsc->IRQ_STATUS; -} - -/** - * @brief vsc clear irq status - * @param [in] vsc CLC base address - * @param [in] irq_mask irq mask, @ref vsc_irq_mask_t - */ -static inline void vsc_clear_irq_status(VSC_Type *vsc, uint32_t irq_mask) -{ - vsc->IRQ_STATUS = irq_mask; -} - -/** - * @brief vsc check irq request flag - * @param [in] vsc CLC base address - * @param [in] irq_mask irq mask, @ref vsc_irq_mask_t - - * @retval true-has irq req, false-no irq req. - */ -static inline bool vsc_get_irq_flag(VSC_Type *vsc, uint32_t irq_mask) -{ - return ((vsc->IRQ_STATUS & irq_mask) == irq_mask) ? true : false; -} - -/** - * @brief vsc set adc wait cycles - * @param [in] vsc CLC base address - * @param [in] wait_cycle adc wait cycle for exception - */ -static inline void vsc_set_adc_wait_cycle(VSC_Type *vsc, uint32_t wait_cycle) -{ - vsc->ADC_WAIT_CYCLE = VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SET(wait_cycle); -} - -/** - * @brief vsc set position wait cycles - * @param [in] vsc CLC base address - * @param [in] wait_cycle position wait cycle for exception - */ -static inline void vsc_set_pos_wait_cycle(VSC_Type *vsc, uint32_t wait_cycle) -{ - vsc->POS_WAIT_CYCLE = VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SET(wait_cycle); -} - -/** - * @brief vsc set abc phase value tolerate - * @param [in] vsc CLC base address - * @param [in] tolerate value a/b/c total value tolerate - */ -static inline void vsc_set_adc_tolerate(VSC_Type *vsc, uint32_t tolerate) -{ - vsc->ADC_PHASE_TOLERATE = VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SET(tolerate); -} - -/** - * @brief vsc set position pole pairs - * @param [in] vsc CLC base address - * @param [in] pole_pairs pole pairs number - */ -static inline void vsc_set_pos_pole_pairs(VSC_Type *vsc, uint32_t pole_pairs) -{ - vsc->POS_POLE = (vsc->POS_POLE & ~VSC_POS_POLE_POS_POLE_MASK) | VSC_POS_POLE_POS_POLE_SET(pole_pairs); -} - -/** - * @brief vsc set software trigger in - * @param [in] vsc CLC base address - */ -static inline void vsc_set_sw_trig_in(VSC_Type *vsc) -{ - vsc->TRIGGER_SW = VSC_TRIGGER_SW_TRIGGER_SW_MASK; -} - -/** - * @brief vsc get d-axis value - * @param [in] vsc CLC base address - * @param [in] positive_seq true - positive order; false - reverse order - * @retval d-axis value - */ -static inline int32_t vsc_get_d_axis_value(VSC_Type *vsc, bool positive_seq) -{ - if (positive_seq) { - return (int32_t)vsc->ID_POSEDGE; - } else { - return (int32_t)vsc->ID_NEGEDGE; - } -} - -/** - * @brief vsc get q-axis value - * @param [in] vsc CLC base address - * @param [in] positive_seq true - positive order; false - reverse order - * @retval q-axis value - */ -static inline int32_t vsc_get_q_axis_value(VSC_Type *vsc, bool positive_seq) -{ - if (positive_seq) { - return (int32_t)vsc->IQ_POSEDGE; - } else { - return (int32_t)vsc->IQ_NEGEDGE; - } -} - -/** - * @brief vsc get alpha-axis value - * @param [in] vsc CLC base address - * @param [in] positive_seq true - positive order; false - reverse order - * @retval alpha-axis value - */ -static inline int32_t vsc_get_alpha_axis_value(VSC_Type *vsc, bool positive_seq) -{ - if (positive_seq) { - return (int32_t)vsc->ALPHA_POSEDGE; - } else { - return (int32_t)vsc->ALPHA_NEGEDGE; - } -} - -/** - * @brief vsc get beta-axis value - * @param [in] vsc CLC base address - * @param [in] positive_seq true - positive order; false - reverse order - * @retval beta-axis value - */ -static inline int32_t vsc_get_beta_axis_value(VSC_Type *vsc, bool positive_seq) -{ - if (positive_seq) { - return (int32_t)vsc->BETA_POSEDGE; - } else { - if (vsc->BETA_NEGEDGE == 0x80000000) { - return 0x7FFFFFFF; - } else { - return (int32_t)vsc->BETA_NEGEDGE; - } - } -} - -/** - * @brief vsc get adc timestamp value - * @param [in] vsc CLC base address - * @retval adc timestamp value - */ -static inline uint32_t vsc_get_adc_timestamp(VSC_Type *vsc) -{ - return vsc->TIMESTAMP_LOCKED; -} - -/** - * @brief vsc get default config - * - * @param[in] vsc VSC base address - * @param[out] config vsc default config - */ -void vsc_get_default_config(VSC_Type *vsc, vsc_config_t *config); - -/** - * @brief vsc config initialization - * - * @param[in] vsc VSC base address - * @param[in] config vsc config struct - */ -void vsc_config_init(VSC_Type *vsc, vsc_config_t *config); - -/** - * @brief vsc software inject phase a/b/c value - * - * @param[in] vsc VSC base address - * @param[in] value_a phase a value - * @param[in] value_b phase b value - * @param[in] value_c phase c value - */ -void vsc_sw_inject_abc_value(VSC_Type *vsc, int32_t value_a, int32_t value_b, int32_t value_c); - -/** - * @brief vsc software inject position value - * - * @param[in] vsc VSC base address - * @param[in] pos position value - */ -void vsc_sw_inject_pos_value(VSC_Type *vsc, uint32_t pos); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_VSC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h deleted file mode 100644 index 51e81cb30f7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_wdg_drv.h +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_WDG_DRV_H -#define HPM_WDG_DRV_H - -/** - * @brief WDG APIs - * @defgroup wdg_interface WDG driver APIs - * @ingroup wdg_interfaces - * @{ - */ - - -#include "hpm_common.h" -#include "hpm_wdg_regs.h" - -/** - * @brief WDG Reset Interval definitions - */ -typedef enum reset_interval_enum { - reset_interval_clock_period_mult_128 = 0, - reset_interval_clock_period_mult_256 = 1, - reset_interval_clock_period_mult_512 = 2, - reset_interval_clock_period_mult_1k = 3, - reset_interval_clock_period_mult_2k = 4, - reset_interval_clock_period_mult_4k = 5, - reset_interval_clock_period_mult_8k = 6, - reset_interval_clock_period_mult_16k = 7, - reset_interval_max = reset_interval_clock_period_mult_16k, - reset_interval_out_of_range, -} reset_interval_t; - -/** - * @brief WDG Interrupt interval definitions - */ -typedef enum interrupt_interval_enum { - interrupt_interval_clock_period_multi_64 = 0, - interrupt_interval_clock_period_multi_256 = 1, - interrupt_interval_clock_period_multi_1k = 2, - interrupt_interval_clock_period_multi_2k = 3, - interrupt_interval_clock_period_multi_4k = 4, - interrupt_interval_clock_period_multi_8k = 5, - interrupt_interval_clock_period_multi_16k = 6, - interrupt_interval_clock_period_multi_32k = 7, - interrupt_interval_clock_period_multi_128k = 8, - interrupt_interval_clock_period_multi_512k = 9, - interrupt_interval_clock_period_multi_2m = 10, - interrupt_interval_clock_period_multi_8m = 11, - interrupt_interval_clock_period_multi_32m = 12, - interrupt_interval_clock_period_multi_128m = 13, - interrupt_interval_clock_period_multi_512m = 14, - interrupt_interval_clock_period_multi_2g = 15, - interrupt_interval_max = interrupt_interval_clock_period_multi_2g, - interrupt_interval_out_of_range, -} interrupt_interval_t; - -/** - * @brief WDG clock source definitions - */ -typedef enum wdg_clksrc_enum { - wdg_clksrc_extclk, /**< WDG clock source: external clock */ - wdg_clksrc_pclk, /**< WDG clock source: Peripheral clock */ - wdg_clksrc_max = wdg_clksrc_pclk -} wdg_clksrc_t; - -/** - * @brief WDG Control configuration structure - * @note WDG reset time = reset_interval + interrupt interval - */ -typedef struct wdg_control_struct { - reset_interval_t reset_interval; /**< WDG reset interval */ - interrupt_interval_t interrupt_interval; /**< WDG interrupt interval */ - bool reset_enable; /**< WDG reset enable */ - bool interrupt_enable; /**< WDG interrupt enable */ - wdg_clksrc_t clksrc; /**< WDG clock source */ - bool wdg_enable; /**< WDG enable */ -} wdg_control_t; - -#define WDG_WRITE_ENABLE_MAGIC_NUM (0x5AA5UL) /**< WDG enable magic number */ -#define WDG_RESTART_MAGIC_NUM (0xCAFEUL) /**< WDG restart magic number */ - -#define WDG_EXT_CLK_FREQ (32768UL) /**< WDG External CLock frequency: 32768 Hz */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief WDG write enable function - * - * @param [in] base WDG base address - */ -static inline void wdg_write_enable(WDG_Type *base) -{ - base->WREN = WDG_WRITE_ENABLE_MAGIC_NUM; -} - -/** - * @brief WDG Enable function - * - * @param [in] base WDG base address - */ -static inline void wdg_enable(WDG_Type *base) -{ - wdg_write_enable(base); - base->CTRL |= WDG_CTRL_EN_MASK; -} - -/** - * @brief WDG Disable function - * - * @param [in] base WDG base address - */ -static inline void wdg_disable(WDG_Type *base) -{ - wdg_write_enable(base); - base->CTRL &= ~WDG_CTRL_EN_MASK; -} - -/** - * @brief WDG reset enable function - * - * @param [in] base WDG base address - */ -static inline void wdg_reset_enable(WDG_Type *base) -{ - wdg_write_enable(base); - base->CTRL |= WDG_CTRL_RSTEN_MASK; -} - -/** - * @brief WDG reset disable function - * - * @param [in] base WDG base address - */ -static inline void wdg_reset_disable(WDG_Type *base) -{ - wdg_write_enable(base); - base->CTRL &= ~WDG_CTRL_RSTEN_MASK; -} - - -/** - * @brief WDG interrupt enable function - * - * @param [in] base WDG base address - */ -static inline void wdg_interrupt_enable(WDG_Type *base) -{ - wdg_write_enable(base); - base->CTRL |= WDG_CTRL_INTEN_MASK; -} - -/** - * @brief WDG interrupt disable function - * - * @param [in] base WDG base address - */ -static inline void wdg_interrupt_disable(WDG_Type *base) -{ - wdg_write_enable(base); - base->CTRL &= ~WDG_CTRL_INTEN_MASK; -} - -/** - * @brief WDG Clock Source selection function - * - * @param [in] base WDG base address - * @param [in] clksrc WDG clock source - * @arg wdg_clksrc_extclk External clock - * @arg wdg_clksrc_pclk Peripheral clock - */ -static inline void wdg_clksrc_select(WDG_Type *base, wdg_clksrc_t clksrc) -{ - if (clksrc == wdg_clksrc_extclk) { - base->CTRL &= ~WDG_CTRL_CLKSEL_MASK; - } else { - base->CTRL |= WDG_CTRL_CLKSEL_MASK; - } -} - -/** - * @brief WDG restart function - * - * @param [in] base WDG base address - */ -static inline void wdg_restart(WDG_Type *base) -{ - wdg_write_enable(base); - base->RESTART = WDG_RESTART_MAGIC_NUM; -} - -/** - * @brief WDG Get Status function - * - * @param [in] base WDG base address - * @retval WDG status register value - */ -static inline uint32_t wdg_get_status(WDG_Type *base) -{ - return base->ST; -} - -/** - * @brief WDG clear status function - * - * @param [in] base WDG base address - * @param [in] status_mask WDG status mask value - */ -static inline void wdg_clear_status(WDG_Type *base, uint32_t status_mask) -{ - base->ST = status_mask; -} - -/** - * @brief WDG initialization function - * - * @param [in] base WDG base address - * @param [in] wdg_ctrl WDG control structure - * @retval API execution status - */ -hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl); - -/** - * @brief Convert the Reset interval value based on the WDG source clock frequency and the expected reset interval - * in terms of microseconds - * - * @param [in] src_freq WDG source clock frequency - * @param [in] reset_us Expected Reset interval in terms of microseconds - * @retval Converted WDG reset interval - */ -reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us); - -/** - * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval - * in terms of microseconds - * - * @param [in] src_freq WDG source clock frequency - * @param [in] interval Expected Interrupt interval - * @retval Converted WDG interrupt interval in us - */ - uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval); - -/** - * @brief Convert the Reset interval value based on the WDG source clock frequency and the expected reset interval - * in terms of microseconds - * - * @param [in] src_freq WDG source clock frequency - * @param [in] interval Expected Reset interval - * @retval Converted WDG reset interval in us - */ -uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval); - -/** - * @brief Convert the interrupt interval value based on the WDG source clock frequency and the expected interrupt interval - * in terms of microseconds - * - * @param [in] src_freq WDG source clock frequency - * @param [in] interval_us Expected Interrupt interval in terms of microseconds - * @retval Converted WDG interrupt interval - */ -interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_freq, uint32_t interval_us); - -/** - * @brief Get Actual WDG Interrupt Interval in terms of microseconds - * - * @param [in] base WDG base address - * @param [in] src_freq WDG source clock frequency - * @return Converted WDG interrupt interval in terms of microseconds - */ -uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq); - -/** - * @brief Get Actual WDG Reset Interval in terms of microseconds - * - * @param [in] base WDG base address - * @param [in] src_freq WDG source clock frequency - * @return Converted WDG total reset interval in terms of microseconds - */ -uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_WDG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c deleted file mode 100644 index 60ab4693ee3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_acmp_drv.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_acmp_drv.h" - -hpm_stat_t acmp_channel_config(ACMP_Type *ptr, uint8_t ch, acmp_channel_config_t *config, bool enable) -{ - acmp_channel_enable_cmp(ptr, ch, false); - ptr->CHANNEL[ch].CFG = ACMP_CHANNEL_CFG_CMPEN_SET(enable) - | ACMP_CHANNEL_CFG_MINSEL_SET(config->minus_input) - | ACMP_CHANNEL_CFG_PINSEL_SET(config->plus_input) - | ACMP_CHANNEL_CFG_FLTMODE_SET(config->filter_mode) - | ACMP_CHANNEL_CFG_HYST_SET(config->hyst_level) - | ACMP_CHANNEL_CFG_CMPOEN_SET(config->enable_cmp_output) - | ACMP_CHANNEL_CFG_WINEN_SET(config->enable_window_mode) - | ACMP_CHANNEL_CFG_OPOL_SET(config->invert_output) - | ACMP_CHANNEL_CFG_SYNCEN_SET(config->enable_clock_sync) - | ACMP_CHANNEL_CFG_FLTBYPS_SET(config->bypass_filter) - | ACMP_CHANNEL_CFG_DACEN_SET(config->enable_dac) - | ACMP_CHANNEL_CFG_HPMODE_SET(config->enable_hpmode) - | ACMP_CHANNEL_CFG_FLTLEN_SET(config->filter_length); - if (enable) { - acmp_channel_enable_cmp(ptr, ch, true); - } - return status_success; -} - -void acmp_channel_get_default_config(ACMP_Type *ptr, acmp_channel_config_t *config) -{ - (void) ptr; - config->plus_input = ACMP_INPUT_DAC_OUT; - config->minus_input = ACMP_INPUT_DAC_OUT; - config->filter_mode = ACMP_FILTER_MODE_BYPASS; - config->hyst_level = ACMP_HYST_LEVEL_0; - config->enable_cmp_output = false; - config->enable_window_mode = false; - config->invert_output = false; - config->enable_clock_sync = false; - config->bypass_filter = true; - config->enable_dac = false; - config->enable_hpmode = false; - config->filter_length = 0; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c deleted file mode 100644 index c433e01d2c3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc12_drv.c +++ /dev/null @@ -1,376 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_adc12_drv.h" -#include "hpm_soc_feature.h" - -void adc12_get_default_config(adc12_config_t *config) -{ - config->res = adc12_res_12_bits; - config->conv_mode = adc12_conv_mode_oneshot; - config->adc_clk_div = adc12_clock_divider_1; - config->wait_dis = true; - config->sel_sync_ahb = true; - config->adc_ahb_en = false; -} - -void adc12_get_channel_default_config(adc12_channel_config_t *config) -{ - config->ch = 0; - config->diff_sel = adc12_sample_signal_single_ended; - config->sample_cycle = 10; - config->sample_cycle_shift = 0; - config->thshdh = 0xfff; - config->thshdl = 0x000; - config->wdog_int_en = false; -} - -static hpm_stat_t adc12_do_calibration(ADC12_Type *ptr, adc12_sample_signal_t diff_sel) -{ - uint8_t cal_out; - uint32_t loop_cnt = ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT; - - if (ADC12_IS_SIGNAL_TYPE_INVALID(diff_sel)) { - return status_invalid_argument; - } - - /*Set diff_sel temporarily */ - ptr->SAMPLE_CFG[0] &= ~ADC12_SAMPLE_CFG_DIFF_SEL_MASK; - ptr->SAMPLE_CFG[0] |= ADC12_SAMPLE_CFG_DIFF_SEL_SET(diff_sel); - - /* Set resetcal and resetadc */ - ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_RESETCAL_MASK | ADC12_ANA_CTRL0_RESETADC_MASK; - - /* Clear resetcal and resetadc */ - ptr->ANA_CTRL0 &= ~(ADC12_ANA_CTRL0_RESETCAL_MASK | ADC12_ANA_CTRL0_RESETADC_MASK); - - /* Set startcal */ - ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_STARTCAL_MASK; - - /* Clear startcal */ - ptr->ANA_CTRL0 &= ~ADC12_ANA_CTRL0_STARTCAL_MASK; - - /* Set HW rearm_en */ - ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_REARM_EN_MASK; - - /* Polling calibration status */ - while (ADC12_ANA_STATUS_CALON_GET(ptr->ANA_STATUS) && loop_cnt--) { - /* TODO: Call a common delay function */ - } - - /* Check if the calibration is timeout */ - if (loop_cnt == 0) { - return status_timeout; - } - - /* Read calculation result */ - cal_out = ADC12_ANA_STATUS_CAL_OUT_GET(ptr->ANA_STATUS); - - /* Update cal_out */ - if (diff_sel == adc12_sample_signal_single_ended) { - ptr->ANA_CTRL0 = (ptr->ANA_CTRL0 & ~ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) - | ADC12_ANA_CTRL0_CAL_VAL_SE_SET(cal_out); - } else { - ptr->ANA_CTRL0 = (ptr->ANA_CTRL0 & ~ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) - | ADC12_ANA_CTRL0_CAL_VAL_DIFF_SET(cal_out); - } - - return status_success; -} - -hpm_stat_t adc12_deinit(ADC12_Type *ptr) -{ - /* disable all interrupts */ - ptr->INT_EN = 0; - - return status_success; -} - -hpm_stat_t adc12_init(ADC12_Type *ptr, adc12_config_t *config) -{ - uint32_t adc_clk_div; - - /** - * disable adc - * When the adc is processing data, it will generate an error to initialize the adc again, - * so you need to shut down the adc before initializing it. - */ - - ptr->ANA_CTRL0 &= ~(ADC12_ANA_CTRL0_ENADC_MASK); - - /* Check the resolution */ - if (config->res > adc12_res_12_bits) { - return status_invalid_argument; - } - - /* Set resolution */ - ptr->ANA_CTRL1 = (ptr->ANA_CTRL1 & ~ADC12_ANA_CTRL1_SELRES_MASK) - | ADC12_ANA_CTRL1_SELRES_SET(config->res); - - /* Set convert clock number and clock period */ - if ((config->adc_clk_div - 1) > ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) { - return status_invalid_argument; - } - - /* Set ADC minimum conversion cycle and ADC clock divider */ - ptr->CONV_CFG1 = ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(2 * config->res + 7) - | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div - 1); - - /* Set ADC Config0 */ - ptr->ADC_CFG0 = ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) - | ADC12_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en); - - /* Set wait_dis */ - ptr->BUF_CFG0 = ADC12_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); - - /*------------------------------------------------------------------------------- - * Calibration - *------------------------------------------------------------------------------ - */ - /* Set enldo */ - ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_ENLDO_MASK; - - /* TODO: wait 20us after setting enlado for adc0~adc2 */ - - adc_clk_div = config->adc_clk_div; - - if (adc_clk_div == ADC12_SOC_CLOCK_CLK_DIV) { - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div + 1); - } - - /* Set enadc */ - ptr->ANA_CTRL0 |= ADC12_ANA_CTRL0_ENADC_MASK; - - /* Do a calibration for single-ended mode */ - adc12_do_calibration(ptr, adc12_sample_signal_single_ended); - - /* Do a calibration for differential mode */ - adc12_do_calibration(ptr, adc12_sample_signal_differential); - - /* Set ADC clock divider */ - if (adc_clk_div == ADC12_SOC_CLOCK_CLK_DIV) { - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div); - } - - /*------------------------------------------------------------------------------- - * End of calibration - *------------------------------------------------------------------------------ - */ - - return status_success; -} - -hpm_stat_t adc12_init_channel(ADC12_Type *ptr, adc12_channel_config_t *config) -{ - /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(config->ch)) { - return status_invalid_argument; - } - - /* Check sample cycle */ - if (ADC12_IS_CHANNEL_SAMPLE_CYCLE_INVALID(config->sample_cycle)) { - return status_invalid_argument; - } - - /* Set warning threshold */ - ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) - | ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(config->thshdl); - - /* Select single-ended mode or differential mode */ - /* Set ADC sample cycles multiple */ - /* Set ADC sample cycles */ - ptr->SAMPLE_CFG[config->ch] = ADC12_SAMPLE_CFG_DIFF_SEL_SET(config->diff_sel) - | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) - | ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); - - /* Enable watchdog interrupt */ - if (config->wdog_int_en) { - ptr->INT_EN |= 1 << config->ch; - } - - return status_success; -} - -hpm_stat_t adc12_get_channel_threshold(ADC12_Type *ptr, uint8_t ch, adc12_channel_threshold_t *config) -{ - /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ch)) { - return status_invalid_argument; - } - - config->ch = ch; - config->thshdh = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); - config->thshdl = ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); - - return status_success; -} - -hpm_stat_t adc12_init_seq_dma(ADC12_Type *ptr, adc12_dma_config_t *dma_config) -{ - /* Check the DMA buffer length */ - if (ADC12_IS_SEQ_DMA_BUFF_LEN_INVLAID(dma_config->buff_len_in_4bytes)) { - return status_invalid_argument; - } - - /* Reset ADC DMA */ - ptr->SEQ_DMA_CFG |= ADC12_SEQ_DMA_CFG_DMA_RST_MASK; - - /* Reset memory to clear all of cycle bits */ - memset(dma_config->start_addr, 0x00, dma_config->buff_len_in_4bytes * sizeof(uint32_t)); - - /* De-reset ADC DMA */ - ptr->SEQ_DMA_CFG &= ~ADC12_SEQ_DMA_CFG_DMA_RST_MASK; - - /* Set ADC DMA target address which should be 4-byte aligned */ - ptr->SEQ_DMA_ADDR = (uint32_t)dma_config->start_addr & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK; - - /* Set ADC DMA memory dword length */ - ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) - | ADC12_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes - 1); - - /* Set stop_en and stop_pos */ - if (dma_config->stop_en) { - ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC12_SEQ_DMA_CFG_STOP_POS_MASK) - | ADC12_SEQ_DMA_CFG_STOP_EN_MASK - | ADC12_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); - } - - return status_success; -} - -hpm_stat_t adc12_set_prd_config(ADC12_Type *ptr, adc12_prd_config_t *config) -{ - /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(config->ch)) { - return status_invalid_argument; - } - - /* Check the prescale */ - if (config->prescale > (ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK >> ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)) { - return status_invalid_argument; - } - - /* Set periodic prescale */ - ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) - | ADC12_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); - - /* Set period count */ - ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC12_PRD_CFG_PRD_CFG_PRD_MASK) - | ADC12_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); - - return status_success; -} - -hpm_stat_t adc12_trigger_seq_by_sw(ADC12_Type *ptr) -{ - if (ADC12_INT_STS_SEQ_SW_CFLCT_GET(ptr->INT_STS)) { - return status_fail; - } - ptr->SEQ_CFG0 |= ADC12_SEQ_CFG0_SW_TRIG_MASK; - - return status_success; -} - -/* Note: the sequence length can not be larger or equal than 2 in HPM6750EVK Revision A0 */ -hpm_stat_t adc12_set_seq_config(ADC12_Type *ptr, adc12_seq_config_t *config) -{ - /* Check sequence length */ - if (ADC12_IS_SEQ_LEN_INVLAID(config->seq_len)) { - return status_invalid_argument; - } - - ptr->SEQ_CFG0 = ADC12_SEQ_CFG0_SEQ_LEN_SET(config->seq_len - 1) - | ADC12_SEQ_CFG0_RESTART_EN_SET(config->restart_en) - | ADC12_SEQ_CFG0_CONT_EN_SET(config->cont_en) - | ADC12_SEQ_CFG0_SW_TRIG_EN_SET(config->sw_trig_en) - | ADC12_SEQ_CFG0_HW_TRIG_EN_SET(config->hw_trig_en); - - /* Set sequence queue */ - for (int i = 0; i < config->seq_len; i++) { - /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(config->queue[i].ch)) { - return status_invalid_argument; - } - - ptr->SEQ_QUE[i] = ADC12_SEQ_QUE_SEQ_INT_EN_SET(config->queue[i].seq_int_en) - | ADC12_SEQ_QUE_CHAN_NUM_4_0_SET(config->queue[i].ch); - } - - return status_success; -} - -hpm_stat_t adc12_trigger_pmt_by_sw(ADC12_Type *ptr, uint8_t trig_ch) -{ - ptr->TRG_SW_STA = ADC12_TRG_SW_STA_TRG_SW_STA_MASK | ADC12_TRG_SW_STA_TRIG_SW_INDEX_SET(trig_ch); - - return status_success; -} - -hpm_stat_t adc12_set_pmt_config(ADC12_Type *ptr, adc12_pmt_config_t *config) -{ - uint32_t temp = 0; - - /* Check the specified trigger length */ - if (ADC12_IS_TRIG_LEN_INVLAID(config->trig_len)) { - return status_invalid_argument; - } - - /* Check the triggier channel */ - if (ADC12_IS_TRIG_CH_INVLAID(config->trig_ch)) { - return status_invalid_argument; - } - - temp |= ADC12_CONFIG_TRIG_LEN_SET(config->trig_len - 1); - - for (int i = 0; i < config->trig_len; i++) { - if (ADC12_IS_CHANNEL_INVALID(config->adc_ch[i])) { - return status_invalid_argument; - } - - temp |= config->inten[i] << (ADC12_CONFIG_INTEN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE) - | config->adc_ch[i] << (ADC12_CONFIG_CHAN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE); - } - - ptr->CONFIG[config->trig_ch] = temp; - - return status_success; -} - -hpm_stat_t adc12_get_oneshot_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) -{ - uint32_t bus_res; - - /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ch)) { - return status_invalid_argument; - } - - bus_res = ptr->BUS_RESULT[ch]; - *result = ADC12_BUS_RESULT_CHAN_RESULT_GET(bus_res); - - if (ADC12_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) { - if (!ADC12_BUS_RESULT_VALID_GET(bus_res)) { - return status_fail; - } - } - - return status_success; -} - -hpm_stat_t adc12_get_prd_result(ADC12_Type *ptr, uint8_t ch, uint16_t *result) -{ - /* Check the specified channel number */ - if (ADC12_IS_CHANNEL_INVALID(ch)) { - return status_invalid_argument; - } - - *result = ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(ptr->PRD_CFG[ch].PRD_RESULT); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c deleted file mode 100644 index 20d759528e2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_adc16_drv.c +++ /dev/null @@ -1,503 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_adc16_drv.h" -#include "hpm_soc_feature.h" - -void adc16_get_default_config(adc16_config_t *config) -{ - config->res = adc16_res_16_bits; - config->conv_mode = adc16_conv_mode_oneshot; - config->adc_clk_div = adc16_clock_divider_1; - config->wait_dis = true; - config->sel_sync_ahb = true; - config->port3_realtime = false; - config->adc_ahb_en = false; -} - -void adc16_get_channel_default_config(adc16_channel_config_t *config) -{ - config->ch = 0; - config->sample_cycle = 10; - config->sample_cycle_shift = 0; - config->thshdh = 0xffff; - config->thshdl = 0x0000; - config->wdog_int_en = false; -} - -static hpm_stat_t adc16_do_calibration(ADC16_Type *ptr) -{ - uint32_t i, j; - uint32_t clk_div_temp; - uint32_t adc16_params[ADC16_SOC_PARAMS_LEN]; - int32_t param01; - uint32_t param02; - uint64_t param64; - uint32_t param32; - uint32_t temp; - - /* Get input clock divider */ - clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); - - /* Set input clock divider temporarily */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - - /* Enable ADC config clock */ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { - adc16_params[i] = 0; - } - - /* Enable reg_en */ - /* Enable bandgap_en */ - ptr->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_REG_EN_MASK - | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK; - - /* Set cal_avg_cfg for 32 loops */ - ptr->ADC16_CONFIG0 = (ptr->ADC16_CONFIG0 & ~ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) - | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(5); - - /* Enable ahb_en */ - ptr->ADC_CFG0 |= ADC16_ADC_CFG0_ADC_AHB_EN_MASK | (1 << 2); - - /* Disable ADC config clock */ - ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Recover input clock divider */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - - for (j = 0; j < 4; j++) { - /* Set startcal */ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_STARTCAL_MASK; - - /* Clear startcal */ - ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_STARTCAL_MASK; - - /* Polling calibration status */ - while (ADC16_ANA_STATUS_CALON_GET(ptr->ANA_STATUS)) { - } - - /* Read parameters */ - for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { - adc16_params[i] += ADC16_ADC16_PARAMS_PARAM_VAL_GET(ptr->ADC16_PARAMS[i]); - } - } - - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33] -= 0x800; - param01 = adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32] - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33]; - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32] = adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA00] - - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33]; - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA00] = 0; - - for (i = 1; i < ADC16_SOC_PARAMS_LEN - 2; i++) { - adc16_params[i] = adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32] + adc16_params[i] - - adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA33] + adc16_params[i - 1]; - } - - param02 = (param01 + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA31] + adc16_params[ADC16_ADC16_PARAMS_ADC16_PARA32]) >> 6; - param64 = 0x10000ll * param02; - param64 = param64 / (0x20000 - param02 / 2); - param32 = (uint32_t)param64; - - for (i = 0; i < ADC16_SOC_PARAMS_LEN; i++) { - adc16_params[i] >>= 6; - } - - /* Enable ADC config clock */ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - - /* Write parameters */ - for (i = 0; i < ADC16_SOC_PARAMS_LEN ; i++) { - ptr->ADC16_PARAMS[i] = (uint16_t)(adc16_params[i]); - } - - /* Set ADC16 Config0 */ - temp = ptr->ADC16_CONFIG0; - - temp &= ~(ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK | ADC16_ADC16_CONFIG0_CONV_PARAM_MASK); - - temp |= ADC16_ADC16_CONFIG0_REG_EN_MASK - | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK - | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK - | ADC16_ADC16_CONFIG0_CONV_PARAM_SET(param32); - - ptr->ADC16_CONFIG0 = temp; - - /* Recover input clock divider */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - - /* Disable ADC config clock */ - ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - return status_success; -} - -hpm_stat_t adc16_deinit(ADC16_Type *ptr) -{ - /* disable all interrupts */ - ptr->INT_EN = 0; - - return status_success; -} - -hpm_stat_t adc16_init(ADC16_Type *ptr, adc16_config_t *config) -{ - uint32_t clk_div_temp; - - /* Set convert clock number and clock period */ - if (config->adc_clk_div - 1 > ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) { - return status_invalid_argument; - } - - /* Set ADC minimum conversion cycle and ADC clock divider */ - ptr->CONV_CFG1 = ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(config->res) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(config->adc_clk_div - 1); - - /* Set ahb_en */ - /* Set the duration of the conversion */ - ptr->ADC_CFG0 = ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(config->sel_sync_ahb) - | ADC16_ADC_CFG0_ADC_AHB_EN_SET(config->adc_ahb_en) - | ADC16_ADC_CFG0_PORT3_REALTIME_SET(config->port3_realtime); - - /* Set wait_dis */ - ptr->BUF_CFG0 = ADC16_BUF_CFG0_WAIT_DIS_SET(config->wait_dis); - - /* Get input clock divider */ - clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); - - /* Set input clock divider temporarily */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - - /* Enable ADC config clock */ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Set end count */ - ptr->ADC16_CONFIG1 &= ~ADC16_ADC16_CONFIG1_COV_END_CNT_MASK; - ptr->ADC16_CONFIG1 |= ADC16_ADC16_CONFIG1_COV_END_CNT_SET(ADC16_SOC_MAX_CONV_CLK_NUM - config->res + 1); - - /* Disable ADC config clock */ - ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Recover input clock divider */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - - /* Do a calibration */ - adc16_do_calibration(ptr); - - return status_success; -} - -hpm_stat_t adc16_init_channel(ADC16_Type *ptr, adc16_channel_config_t *config) -{ - /* Check the specified channel number */ - if (ADC16_IS_CHANNEL_INVALID(config->ch)) { - return status_invalid_argument; - } - - /* Check sample cycle */ - if (ADC16_IS_CHANNEL_SAMPLE_CYCLE_INVALID(config->sample_cycle)) { - return status_invalid_argument; - } - - /* Set warning threshold */ - ptr->PRD_CFG[config->ch].PRD_THSHD_CFG = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(config->thshdh) - | ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(config->thshdl); - - /* Set ADC sample cycles multiple */ - /* Set ADC sample cycles */ - ptr->SAMPLE_CFG[config->ch] = ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(config->sample_cycle_shift) - | ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(config->sample_cycle); - - /* Enable watchdog interrupt */ - if (config->wdog_int_en) { - ptr->INT_EN |= 1 << config->ch; - } - - return status_success; -} - -hpm_stat_t adc16_get_channel_threshold(ADC16_Type *ptr, uint8_t ch, adc16_channel_threshold_t *config) -{ - /* Check the specified channel number */ - if (ADC16_IS_CHANNEL_INVALID(ch)) { - return status_invalid_argument; - } - - config->ch = ch; - config->thshdh = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); - config->thshdl = ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(ptr->PRD_CFG[ch].PRD_THSHD_CFG); - - return status_success; -} - -#if defined(ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT) && ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT -void adc16_enable_oneshot_mode(ADC16_Type *ptr) -{ - ptr->BUF_CFG0 |= ADC16_BUF_CFG0_BUS_MODE_EN_MASK; -} - -void adc16_disable_oneshot_mode(ADC16_Type *ptr) -{ - ptr->BUF_CFG0 &= ~ADC16_BUF_CFG0_BUS_MODE_EN_MASK; -} -#endif - -hpm_stat_t adc16_init_seq_dma(ADC16_Type *ptr, adc16_dma_config_t *dma_config) -{ - /* Check the DMA buffer length */ - if (ADC16_IS_SEQ_DMA_BUFF_LEN_INVLAID(dma_config->buff_len_in_4bytes)) { - return status_invalid_argument; - } - - /* Reset ADC DMA */ - ptr->SEQ_DMA_CFG |= ADC16_SEQ_DMA_CFG_DMA_RST_MASK; - - /* Reset memory to clear all of cycle bits */ - memset(dma_config->start_addr, 0x00, dma_config->buff_len_in_4bytes * sizeof(uint32_t)); - - /* De-reset ADC DMA */ - ptr->SEQ_DMA_CFG &= ~ADC16_SEQ_DMA_CFG_DMA_RST_MASK; - - /* Set ADC DMA target address which should be 4-byte aligned */ - ptr->SEQ_DMA_ADDR = (uint32_t)dma_config->start_addr & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK; - - /* Set ADC DMA memory dword length */ - ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) - | ADC16_SEQ_DMA_CFG_BUF_LEN_SET(dma_config->buff_len_in_4bytes - 1); - - #if defined(ADC_SOC_SEQ_HCFG_EN) && ADC_SOC_SEQ_HCFG_EN - /* Set high-half buffer length */ - ptr->SEQ_HIGH_CFG = (ptr->SEQ_HIGH_CFG & ~ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) - | ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(((dma_config->buff_len_in_4bytes - 1) >> 12)); - #endif - - /* Set stop_en and stop_pos */ - if (dma_config->stop_en) { - ptr->SEQ_DMA_CFG = (ptr->SEQ_DMA_CFG & ~ADC16_SEQ_DMA_CFG_STOP_POS_MASK) - | ADC16_SEQ_DMA_CFG_STOP_EN_MASK - | ADC16_SEQ_DMA_CFG_STOP_POS_SET(dma_config->stop_pos); - - #if defined(ADC_SOC_SEQ_HCFG_EN) && ADC_SOC_SEQ_HCFG_EN - ptr->SEQ_HIGH_CFG = (ptr->SEQ_HIGH_CFG & ~ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) - | ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(((dma_config->stop_pos) >> 12)); - #endif - } - - return status_success; -} - -hpm_stat_t adc16_set_prd_config(ADC16_Type *ptr, adc16_prd_config_t *config) -{ - /* Check the specified channel number */ - if (ADC16_IS_CHANNEL_INVALID(config->ch)) { - return status_invalid_argument; - } - - /* Check the prescale */ - if (config->prescale > (ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT)) { - return status_invalid_argument; - } - - /* Set periodic prescale */ - ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) - | ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(config->prescale); - - /* Set period count */ - ptr->PRD_CFG[config->ch].PRD_CFG = (ptr->PRD_CFG[config->ch].PRD_CFG & ~ADC16_PRD_CFG_PRD_CFG_PRD_MASK) - | ADC16_PRD_CFG_PRD_CFG_PRD_SET(config->period_count); - - return status_success; -} - -hpm_stat_t adc16_trigger_seq_by_sw(ADC16_Type *ptr) -{ - if (ADC16_INT_STS_SEQ_SW_CFLCT_GET(ptr->INT_STS)) { - return status_fail; - } - ptr->SEQ_CFG0 |= ADC16_SEQ_CFG0_SW_TRIG_MASK; - - return status_success; -} - -/* Note: the sequence length can not be larger or equal than 2 in HPM6750EVK Revision A0 */ -hpm_stat_t adc16_set_seq_config(ADC16_Type *ptr, adc16_seq_config_t *config) -{ - /* Check sequence length */ - if (ADC16_IS_SEQ_LEN_INVLAID(config->seq_len)) { - return status_invalid_argument; - } - - ptr->SEQ_CFG0 = ADC16_SEQ_CFG0_SEQ_LEN_SET(config->seq_len - 1) - | ADC16_SEQ_CFG0_RESTART_EN_SET(config->restart_en) - | ADC16_SEQ_CFG0_CONT_EN_SET(config->cont_en) - | ADC16_SEQ_CFG0_SW_TRIG_EN_SET(config->sw_trig_en) - | ADC16_SEQ_CFG0_HW_TRIG_EN_SET(config->hw_trig_en); - - /* Set sequence queue */ - for (int i = 0; i < config->seq_len; i++) { - /* Check the specified channel number */ - if (ADC16_IS_CHANNEL_INVALID(config->queue[i].ch)) { - return status_invalid_argument; - } - - ptr->SEQ_QUE[i] = ADC16_SEQ_QUE_SEQ_INT_EN_SET(config->queue[i].seq_int_en) - | ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(config->queue[i].ch); - } - - return status_success; -} - -hpm_stat_t adc16_trigger_pmt_by_sw(ADC16_Type *ptr, uint8_t trig_ch) -{ - ptr->TRG_SW_STA = ADC16_TRG_SW_STA_TRG_SW_STA_MASK | ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(trig_ch); - - return status_success; -} - -hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config) -{ - uint32_t temp = 0; - - /* Check the specified trigger length */ - if (ADC16_IS_TRIG_LEN_INVLAID(config->trig_len)) { - return status_invalid_argument; - } - - /* Check the triggier channel */ - if (ADC16_IS_TRIG_CH_INVLAID(config->trig_ch)) { - return status_invalid_argument; - } - - temp |= ADC16_CONFIG_TRIG_LEN_SET(config->trig_len - 1); - - for (int i = 0; i < config->trig_len; i++) { - if (ADC16_IS_CHANNEL_INVALID(config->adc_ch[i])) { - return status_invalid_argument; - } - - temp |= config->inten[i] << (ADC16_CONFIG_INTEN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE) - | config->adc_ch[i] << (ADC16_CONFIG_CHAN0_SHIFT + i * ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE); - } - - ptr->CONFIG[config->trig_ch] = temp; - - return status_success; -} - -hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool enable) -{ - (void) ptr; - /* Check the specified trigger channel */ - if (ADC16_IS_TRIG_CH_INVLAID(trig_ch)) { - return status_invalid_argument; - } - -#if defined(ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT) && ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT - /* Set queue enable control */ - ptr->CONFIG[trig_ch] &= ~ADC16_CONFIG_QUEUE_EN_MASK; - ptr->CONFIG[trig_ch] |= ADC16_CONFIG_QUEUE_EN_SET(enable); - return status_success; -#else - (void) enable; - return status_success; -#endif -} - -/* one shot mode */ -hpm_stat_t adc16_get_oneshot_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) -{ - uint32_t bus_res; - - /* Check the specified channel number */ - if (ADC16_IS_CHANNEL_INVALID(ch)) { - return status_invalid_argument; - } - - bus_res = ptr->BUS_RESULT[ch]; - *result = ADC16_BUS_RESULT_CHAN_RESULT_GET(bus_res); - - if (ADC16_BUF_CFG0_WAIT_DIS_GET(ptr->BUF_CFG0)) { - if (!ADC16_BUS_RESULT_VALID_GET(bus_res)) { - return status_fail; - } - } - - return status_success; -} - -/* period mode */ -hpm_stat_t adc16_get_prd_result(ADC16_Type *ptr, uint8_t ch, uint16_t *result) -{ - /* Check the specified channel number */ - if (ADC16_IS_CHANNEL_INVALID(ch)) { - return status_invalid_argument; - } - - *result = ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(ptr->PRD_CFG[ch].PRD_RESULT); - - return status_success; -} - -#if defined(ADC16_SOC_TEMP_CH_EN) && ADC16_SOC_TEMP_CH_EN -void adc16_enable_temp_sensor(ADC16_Type *ptr) -{ - uint32_t clk_div_temp; - - /* Get input clock divider */ - clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); - - /* Set input clock divider temporarily */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - - /* Enable ADC config clock */ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Enable the temperature sensor */ - ptr->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK | ADC16_ADC16_CONFIG0_REG_EN_MASK - | ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK | ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(5); - - /* Disable ADC config clock */ - ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Recover input clock divider */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); -} - -void adc16_disable_temp_sensor(ADC16_Type *ptr) -{ - uint32_t clk_div_temp; - - /* Get input clock divider */ - clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(ptr->CONV_CFG1); - - /* Set input clock divider temporarily */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - - /* Enable ADC config clock */ - ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Disable the temp sensor */ - ptr->ADC16_CONFIG0 &= ~ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK; - - /* Disable ADC config clock */ - ptr->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Recover input clock divider */ - ptr->CONV_CFG1 = (ptr->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c deleted file mode 100644 index c6a6c3babb1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_cam_drv.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_cam_drv.h" - -#define CAM_RX_FIFO_THRESHOLD (6U) - -void cam_get_default_config(CAM_Type *ptr, cam_config_t *config, display_pixel_format_t pixel_format) -{ - (void) ptr; - config->width = 320; - config->height = 240; - config->buffer1 = -1; - config->buffer2 = -1; - config->pixclk_sampling_falling = false; - config->hsync_active_low = false; - config->vsync_active_low = false; -#if defined(HPM_IP_FEATURE_CAM_INV_DEN) && (HPM_IP_FEATURE_CAM_INV_DEN == 1) - config->de_active_low = false; -#endif - config->color_ext = false; - config->data_pack_msb = false; - config->data_store_mode = CAM_DATA_STORE_MODE_NORMAL; - config->color_format = pixel_format; - config->sensor_bitwidth = CAM_SENSOR_BITWIDTH_10BITS; - - switch (pixel_format) { - case display_pixel_format_yuv422: - config->csc_config.enable = true; - config->csc_config.ycbcr_mode = false; - config->csc_config.yuv2rgb_coef.c0 = 0x100; - config->csc_config.yuv2rgb_coef.uv_offset = 0; - config->csc_config.yuv2rgb_coef.y_offset = 0; - config->csc_config.yuv2rgb_coef.c1 = 0x123; - config->csc_config.yuv2rgb_coef.c2 = 0x76B; - config->csc_config.yuv2rgb_coef.c3 = 0x79C; - config->csc_config.yuv2rgb_coef.c4 = 0x208; - break; - case display_pixel_format_ycbcr422: - config->csc_config.enable = true; - config->csc_config.ycbcr_mode = true; - config->csc_config.yuv2rgb_coef.c0 = 0x12A; - config->csc_config.yuv2rgb_coef.uv_offset = 0x180; - config->csc_config.yuv2rgb_coef.y_offset = 0x1F0; - config->csc_config.yuv2rgb_coef.c1 = 0x198; - config->csc_config.yuv2rgb_coef.c2 = 0x730; - config->csc_config.yuv2rgb_coef.c3 = 0x79C; - config->csc_config.yuv2rgb_coef.c4 = 0x204; - break; - default: - config->csc_config.enable = false; - config->csc_config.ycbcr_mode = false; - config->csc_config.yuv2rgb_coef.c0 = 0; - config->csc_config.yuv2rgb_coef.uv_offset = 0; - config->csc_config.yuv2rgb_coef.y_offset = 0; - config->csc_config.yuv2rgb_coef.c1 = 0; - config->csc_config.yuv2rgb_coef.c2 = 0; - config->csc_config.yuv2rgb_coef.c3 = 0; - config->csc_config.yuv2rgb_coef.c4 = 0; - break; - } -} - -void cam_reset(CAM_Type *ptr) -{ - cam_stop(ptr); - ptr->CR1 = CAM_CR1_ASYNC_RXFIFO_CLR_MASK; - ptr->INT_EN = 0; - ptr->CR2 = CAM_CR2_FRMCNT_RST_MASK; - ptr->STA = 0xFFFFFFFF; - ptr->CR20 = 0; -} - -hpm_stat_t cam_init(CAM_Type *ptr, cam_config_t *config) -{ - hpm_stat_t stat = status_success; - uint32_t pixel_format, width; - - pixel_format = config->color_format; - width = config->width; - - if ((int)config->buffer1 < 0) { - return status_invalid_argument; - } - - if (pixel_format == CAM_COLOR_FORMAT_RAW8) { - if ((width % 2) != 0) { - return status_invalid_argument; - } - /* use rgb565 format to receive raw8 data and adjust the width to half */ - pixel_format = CAM_COLOR_FORMAT_RGB565; - width /= 2; - } - - cam_reset(ptr); - - /* - * In DVP mode, de_active_low and hsync_active_low are same. - */ -#if defined(HPM_IP_FEATURE_CAM_INV_DEN) && (HPM_IP_FEATURE_CAM_INV_DEN == 1) - if (config->sensor_bitwidth != CAM_SENSOR_BITWIDTH_24BITS) { - config->de_active_low = config->hsync_active_low; - } -#endif - - ptr->CR1 = CAM_CR1_INV_PIXCLK_SET(config->pixclk_sampling_falling) - | CAM_CR1_INV_HSYNC_SET(config->hsync_active_low) - | CAM_CR1_INV_VSYNC_SET(config->vsync_active_low) -#if defined(HPM_IP_FEATURE_CAM_INV_DEN) && (HPM_IP_FEATURE_CAM_INV_DEN == 1) - | CAM_CR1_INV_DEN_SET(config->de_active_low) -#endif - | CAM_CR1_RESTART_BUSPTR_MASK - | CAM_CR1_COLOR_EXT_SET(config->color_ext) - | CAM_CR1_PACK_DIR_SET(config->data_pack_msb) - | config->data_store_mode - | pixel_format - | config->sensor_bitwidth; - - ptr->IDEAL_WN_SIZE = CAM_IDEAL_WN_SIZE_HEIGHT_SET(config->height) - | CAM_IDEAL_WN_SIZE_WIDTH_SET(width); - - ptr->CR2 = CAM_CR2_DMA_REQ_EN_RFF_MASK - | CAM_CR2_RXFF_LEVEL_SET(CAM_RX_FIFO_THRESHOLD); - ptr->DMASA_FB1 = config->buffer1; - if ((int)config->buffer2 < 0) { - ptr->DMASA_FB2 = config->buffer1; - } else { - ptr->DMASA_FB2 = config->buffer2; - } - - ptr->CSC_COEF0 = CAM_CSC_COEF0_ENABLE_SET(config->csc_config.enable) - | CAM_CSC_COEF0_YCBCR_MODE_SET(config->csc_config.ycbcr_mode) - | CAM_CSC_COEF0_C0_SET(config->csc_config.yuv2rgb_coef.c0) - | CAM_CSC_COEF0_UV_OFFSET_SET(config->csc_config.yuv2rgb_coef.uv_offset) - | CAM_CSC_COEF0_Y_OFFSET_SET(config->csc_config.yuv2rgb_coef.y_offset); - ptr->CSC_COEF1 = CAM_CSC_COEF1_C1_SET(config->csc_config.yuv2rgb_coef.c1) - | CAM_CSC_COEF1_C4_SET(config->csc_config.yuv2rgb_coef.c4); - ptr->CSC_COEF2 = CAM_CSC_COEF2_C2_SET(config->csc_config.yuv2rgb_coef.c2) - | CAM_CSC_COEF2_C3_SET(config->csc_config.yuv2rgb_coef.c3); - - return stat; -} - -void cam_stop(CAM_Type *ptr) -{ - ptr->CR18 &= ~CAM_CR18_CAM_ENABLE_MASK; -} - -void cam_start(CAM_Type *ptr) -{ - ptr->CR18 |= CAM_CR18_CAM_ENABLE_MASK; -} - -void cam_stop_safely(CAM_Type *ptr) -{ - /* - * waiting for capture frame to complete - */ - cam_clear_status(ptr, cam_status_end_of_frame); - while (cam_check_status(ptr, cam_status_end_of_frame) == false) { - } - cam_stop(ptr); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c deleted file mode 100644 index b7fe320531a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_can_drv.c +++ /dev/null @@ -1,785 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_can_drv.h" -#include - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ -#define TSEG1_MIN_FOR_CAN2_0 (2U) -#define TSEG1_MAX_FOR_CAN2_0 (65U) - -#define TSEG1_MIN_FOR_CANFD_NOMINAL (2U) -#define TSEG1_MAX_FOR_CANFD_NOMINAL (65U) - -#define TSEG1_MIN_FOR_CANFD_DATA (2U) -#define TSEG1_MAX_FOR_CANFD_DATA (17U) - -#define TSEG2_MIN_FOR_CAN2_0 (1U) -#define TSEG2_MAX_FOR_CAN2_0 (8U) - -#define TSEG2_MIN_FOR_CANFD_NOMINAL (1U) -#define TSEG2_MAX_FOR_CANFD_NOMINAL (32U) - -#define TSEG2_MIN_FOR_CANFD_DATA (1U) -#define TSEG2_MAX_FOR_CANFD_DATA (8U) - -#define TSJW_MIN_FOR_CAN2_0 (1U) -#define TSJW_MAX_FOR_CAN2_0 (16U) - -#define TSJW_MIN_FOR_CANFD_NOMINAL (1U) -#define TSJW_MAX_FOR_CANFD_NOMINAL (16U) - -#define TSJW_MIN_FOR_CANFD_DATA (1U) -#define TSJW_MAX_FOR_CANFD_DATA (8U) - -#define NUM_TQ_MIN_FOR_CAN2_0 (8U) -#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) - -#define NUM_TQ_MIN_FOR_CANFD_NOMINAL (8U) -#define NUM_TQ_MAX_FOR_CANFD_NOMINAL (TSEG1_MAX_FOR_CANFD_NOMINAL + TSEG2_MAX_FOR_CANFD_NOMINAL) - -#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) -#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) - -#define MIN_TQ_MUL_PRESCALE (10U) - -#define NUM_PRESCALE_MAX (256U) - -#define CAN_FILTER_INDEX_MAX (15U) -#define CAN_FILTER_NUM_MAX (16U) - -#define CAN_TIMEOUT_CNT (0xFFFFFFUL) - -#define CAN_SAMPLEPOINT_MIN (750U) -#define CAN_SAMPLEPOINT_MAX (875U) - - -#define CAN_DEFAULT_FILTER_SETTING {0, can_filter_id_mode_both_frames, true, 0, (1UL << 29) - 1U } - -/* - * @brief CAN bit-timing table - */ -typedef struct { - uint8_t tq_min; - uint8_t tq_max; - uint8_t seg1_min; - uint8_t seg1_max; - uint8_t seg2_min; - uint8_t seg2_max; - uint8_t sjw_min; - uint8_t sjw_max; - uint8_t min_diff_seg1_minus_seg2; -} can_bit_timing_table_t; - -/** - * @brief CAN bit timing list for all supported bit timing modes - */ -static const can_bit_timing_table_t s_can_bit_timing_tbl[3] = { - { - .tq_min = NUM_TQ_MIN_FOR_CAN2_0, - .tq_max = NUM_TQ_MAX_FOR_CAN2_0, - .seg1_min = TSEG1_MIN_FOR_CAN2_0, - .seg1_max = TSEG1_MAX_FOR_CAN2_0, - .seg2_min = TSEG2_MIN_FOR_CAN2_0, - .seg2_max = TSEG2_MAX_FOR_CAN2_0, - .sjw_min = TSJW_MIN_FOR_CAN2_0, - .sjw_max = TSJW_MAX_FOR_CAN2_0, - .min_diff_seg1_minus_seg2 = 2, - }, - { - .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, - .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, - .seg1_min = TSEG1_MIN_FOR_CANFD_NOMINAL, - .seg1_max = TSEG1_MAX_FOR_CANFD_NOMINAL, - .seg2_min = TSEG2_MIN_FOR_CANFD_NOMINAL, - .seg2_max = TSEG2_MAX_FOR_CANFD_NOMINAL, - .sjw_min = TSJW_MIN_FOR_CANFD_NOMINAL, - .sjw_max = TSJW_MAX_FOR_CANFD_NOMINAL, - .min_diff_seg1_minus_seg2 = 2, - }, - { - .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, - .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, - .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, - .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, - .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, - .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, - .sjw_min = TSJW_MIN_FOR_CANFD_DATA, - .sjw_max = TSJW_MAX_FOR_CANFD_DATA, - .min_diff_seg1_minus_seg2 = 1, - } -}; - -/*********************************************************************************************************************** - * - * Prototypes - */ -static uint32_t find_optimal_prescaler(uint32_t num_tq_mul_prescaler, uint32_t start_prescaler, - uint32_t max_tq, uint32_t min_tq); - -static uint8_t can_get_data_words_from_dlc(uint32_t dlc); - -static void can_fill_tx_buffer(CAN_Type *base, const can_transmit_buf_t *message); - -static bool is_can_bit_timing_param_valid(can_bit_timing_option_t option, const can_bit_timing_param_t *param); - - -/*********************************************************************************************************************** - * - * Codes - */ -static uint32_t find_optimal_prescaler(uint32_t num_tq_mul_prescaler, uint32_t start_prescaler, - uint32_t max_tq, uint32_t min_tq) -{ - bool has_found = false; - - uint32_t prescaler = start_prescaler; - - while (!has_found) { - - if ((num_tq_mul_prescaler / prescaler > max_tq) || (num_tq_mul_prescaler % prescaler != 0)) { - ++prescaler; - continue; - } else { - uint32_t tq = num_tq_mul_prescaler / prescaler; - if (tq * prescaler == num_tq_mul_prescaler) { - has_found = true; - break; - } else if (tq < min_tq) { - has_found = false; - break; - } else { - ++prescaler; - } - } - } - - return has_found ? prescaler : 0U; -} - - -hpm_stat_t can_calculate_bit_timing(uint32_t src_clk_freq, can_bit_timing_option_t option, uint32_t baudrate, - uint16_t samplepoint_min, uint16_t samplepoint_max, - can_bit_timing_param_t *timing_param) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((option > can_bit_timing_canfd_data) || (baudrate == 0U) || - (src_clk_freq / baudrate < MIN_TQ_MUL_PRESCALE) || (timing_param == NULL)) { - break; - } - - const can_bit_timing_table_t *tbl = &s_can_bit_timing_tbl[(uint8_t) option]; - - /* According to the CAN specification 2.0, - * the Tq must be in range specified in the above CAN bit-timing table - */ - if (src_clk_freq / baudrate < tbl->tq_min) { - break; - } - - uint32_t num_tq_mul_prescaler = src_clk_freq / baudrate; - uint32_t start_prescaler = 1U; - uint32_t num_seg1, num_seg2; - bool has_found = false; - - /* Find out the minimum prescaler */ - uint32_t current_prescaler; - while (!has_found) { - current_prescaler = find_optimal_prescaler(num_tq_mul_prescaler, start_prescaler, - tbl->tq_max, - tbl->tq_min); - if ((current_prescaler < start_prescaler) || (current_prescaler > NUM_PRESCALE_MAX)) { - break; - } - uint32_t num_tq = num_tq_mul_prescaler / current_prescaler; - - num_seg2 = (num_tq - tbl->min_diff_seg1_minus_seg2) / 2U; - num_seg1 = num_tq - num_seg2; - while (num_seg2 > tbl->seg2_max) { - num_seg2--; - num_seg1++; - } - - /* Recommended sample point is 75% - 87.5% */ - while ((num_seg1 * 1000U) / num_tq < samplepoint_min) { - ++num_seg1; - --num_seg2; - } - - if ((num_seg1 * 1000U) / num_tq > samplepoint_max) { - break; - } - - if ((num_seg2 >= tbl->seg2_min) && (num_seg1 <= tbl->seg1_max)) { - has_found = true; - } else { - start_prescaler = current_prescaler + 1U; - } - } - - if (has_found) { - uint32_t num_sjw = MIN(tbl->sjw_max, num_seg2); - timing_param->num_seg1 = num_seg1; - timing_param->num_seg2 = num_seg2; - timing_param->num_sjw = num_sjw; - timing_param->prescaler = current_prescaler; - status = status_success; - } - } while (false); - - return status; -} - -static bool is_can_bit_timing_param_valid(can_bit_timing_option_t option, const can_bit_timing_param_t *param) -{ - bool result = false; - const can_bit_timing_table_t *tbl = &s_can_bit_timing_tbl[(uint8_t) option]; - do { - if ((param->num_seg1 < tbl->seg1_min) || (param->num_seg1 > tbl->seg1_max)) { - break; - } - if ((param->num_seg2 < tbl->seg2_min) || (param->num_seg2 > tbl->seg2_max)) { - break; - } - if ((param->num_sjw < tbl->sjw_min) || (param->num_sjw > tbl->sjw_max)) { - break; - } - if (param->prescaler > NUM_PRESCALE_MAX) { - break; - } - result = true; - } while (false); - - return result; -} - -hpm_stat_t can_set_bit_timing(CAN_Type *base, can_bit_timing_option_t option, - uint32_t src_clk_freq, uint32_t baudrate, - uint16_t samplepoint_min, uint16_t samplepoint_max) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if (base == NULL) { - break; - } - - can_bit_timing_param_t timing_param; - status = can_calculate_bit_timing(src_clk_freq, option, baudrate, samplepoint_min, samplepoint_max, &timing_param); - - if (status == status_success) { - if (option < can_bit_timing_canfd_data) { - base->S_PRESC = CAN_S_PRESC_S_PRESC_SET(timing_param.prescaler - 1U) | CAN_S_PRESC_S_SEG_1_SET(timing_param.num_seg1 - 2U) | - CAN_S_PRESC_S_SEG_2_SET(timing_param.num_seg2 - 1U) | CAN_S_PRESC_S_SJW_SET(timing_param.num_sjw - 1U); - } else { - base->F_PRESC = CAN_F_PRESC_F_PRESC_SET(timing_param.prescaler - 1U) | CAN_F_PRESC_F_SEG_1_SET(timing_param.num_seg1 - 2U) | - CAN_F_PRESC_F_SEG_2_SET(timing_param.num_seg2 - 1U) | CAN_F_PRESC_F_SJW_SET(timing_param.num_sjw - 1U); - - } - status = status_success; - } - - } while (false); - - return status; -} - -hpm_stat_t can_set_filter(CAN_Type *base, const can_filter_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((base == NULL) || (config == NULL)) { - break; - } - if (config->index > CAN_FILTER_INDEX_MAX) { - status = status_can_filter_index_invalid; - break; - } - - /* Configure acceptance code */ - base->ACFCTRL = CAN_ACFCTRL_ACFADR_SET(config->index); - base->ACF = CAN_ACF_CODE_MASK_SET(config->code); - - /* Configure acceptance mask */ - uint32_t acf_value = CAN_ACF_CODE_MASK_SET(config->mask); - if (config->id_mode == can_filter_id_mode_standard_frames) { - acf_value |= CAN_ACF_AIDEE_MASK; - } else if (config->id_mode == can_filter_id_mode_extended_frames) { - acf_value |= CAN_ACF_AIDEE_MASK | CAN_ACF_AIDE_MASK; - } else { - /* Treat it as the default mode */ - acf_value |= 0; - } - - base->ACFCTRL = CAN_ACFCTRL_SELMASK_MASK | CAN_ACFCTRL_ACFADR_SET(config->index); - base->ACF = acf_value; - - if (config->enable) { - base->ACF_EN |= (1U << config->index); - } else { - base->ACF_EN &= (uint16_t) ~(1U << config->index); - } - status = status_success; - } while (false); - - return status; -} - -static uint8_t can_get_data_words_from_dlc(uint32_t dlc) -{ - uint32_t copy_words = 0; - - dlc &= 0xFU; - if (dlc <= 8U) { - copy_words = (dlc + 3U) / sizeof(uint32_t); - } else { - switch (dlc) { - case can_payload_size_12: - copy_words = 3U; - break; - case can_payload_size_16: - copy_words = 4U; - break; - case can_payload_size_20: - copy_words = 5U; - break; - case can_payload_size_24: - copy_words = 6U; - break; - case can_payload_size_32: - copy_words = 8U; - break; - case can_payload_size_48: - copy_words = 12U; - break; - case can_payload_size_64: - copy_words = 16U; - break; - default: - /* Code should never touch here */ - break; - } - } - - return copy_words; -} - -static void can_fill_tx_buffer(CAN_Type *base, const can_transmit_buf_t *message) -{ - base->TBUF[0] = message->buffer[0]; - base->TBUF[1] = message->buffer[1]; - - uint32_t copy_words = can_get_data_words_from_dlc(message->dlc); - for (uint32_t i = 0U; i < copy_words; i++) { - base->TBUF[2U + i] = message->buffer[2U + i]; - } -} - -hpm_stat_t can_send_message_blocking(CAN_Type *base, const can_transmit_buf_t *message) -{ - hpm_stat_t status = status_invalid_argument; - - do { - - if ((base == NULL) || (message == NULL)) { - break; - } - - status = status_success; - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; - - can_fill_tx_buffer(base, message); - - /* Wait until STB is not full */ - int32_t timeout_cnt = CAN_TIMEOUT_CNT; - while (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_STB_IS_FULL) { - timeout_cnt--; - if (timeout_cnt <= 0) { - status = status_timeout; - break; - } - } - if (status != status_success) { - break; - } - - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK | CAN_CMD_STA_CMD_CTRL_TSONE_MASK; - timeout_cnt = CAN_TIMEOUT_CNT; - while (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) != CAN_STB_IS_EMPTY) { - timeout_cnt--; - if (timeout_cnt <= 0) { - status = status_timeout; - break; - } - } - - } while (false); - - return status; -} - -hpm_stat_t can_send_high_priority_message_blocking(CAN_Type *base, const can_transmit_buf_t *message) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((base == NULL) || (message == NULL)); - status = status_success; - - /* Select the high-priority buffer */ - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; - - can_fill_tx_buffer(base, message); - - /* Send the data out */ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPE_MASK; - /* Wait until the data is sent out */ - int32_t timeout_cnt = CAN_TIMEOUT_CNT; - while (IS_HPM_BITMASK_SET(base->CMD_STA_CMD_CTRL, CAN_CMD_STA_CMD_CTRL_TPE_MASK)) { - timeout_cnt--; - if (timeout_cnt <= 0) { - status = status_timeout; - break; - } - } - } while (false); - - return status; -} - -hpm_stat_t can_send_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message) -{ - hpm_stat_t status = status_invalid_argument; - - do { - - if ((base == NULL) || (message == NULL)) { - break; - } - - if (CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_STB_IS_FULL) { - status = status_can_tx_fifo_full; - break; - } - - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; - can_fill_tx_buffer(base, message); - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK | CAN_CMD_STA_CMD_CTRL_TSONE_MASK; - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_transmit_buf_t *message) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((base == NULL) || (message == NULL)); - status = status_success; - - if (IS_HPM_BITMASK_SET(base->CMD_STA_CMD_CTRL, CAN_CMD_STA_CMD_CTRL_TPE_MASK)) { - status = status_can_tx_fifo_full; - break; - } - /* Select the high-priority buffer */ - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TBSEL_MASK; - - can_fill_tx_buffer(base, message); - - /* Send the data out */ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_TPE_MASK; - } while (false); - - return status; -} - -hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *message) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((base == NULL) || (message == NULL)); - - while (CAN_CMD_STA_CMD_CTRL_RSTAT_GET(base->CMD_STA_CMD_CTRL) == CAN_RXBUF_IS_EMPTY) { - - } - - /* Get the first 2 words (including CAN ID, Data length and other control bits) */ - message->buffer[0] = base->RBUF[0]; - message->buffer[1] = base->RBUF[1]; - - if (message->error_type != 0U) { - switch (message->error_type) { - case 1: - status = status_can_bit_error; - break; - case 2: - status = status_can_form_error; - break; - case 3: - status = status_can_stuff_error; - break; - case 4: - status = status_can_ack_error; - break; - case 5: - status = status_can_crc_error; - break; - default: - status = status_can_other_error; - break; - } - break; - } - - if (message->remote_frame == 0U) { - uint32_t copy_words = can_get_data_words_from_dlc(message->dlc); - - for (uint32_t i = 0; i < copy_words; i++) { - message->buffer[2U + i] = base->RBUF[2U + i]; - } - } - /* Release the current buffer */ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RREL_MASK; - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t can_read_received_message(CAN_Type *base, can_receive_buf_t *message) -{ - hpm_stat_t status; - - assert((base != NULL) && (message != NULL)); - - do { - /* Get the first 2 words (including CAN ID, Data length and other control bits) */ - message->buffer[0] = base->RBUF[0]; - message->buffer[1] = base->RBUF[1]; - - if (message->error_type != 0U) { - switch (message->error_type) { - case 1: - status = status_can_bit_error; - break; - case 2: - status = status_can_form_error; - break; - case 3: - status = status_can_stuff_error; - break; - case 4: - status = status_can_ack_error; - break; - case 5: - status = status_can_crc_error; - break; - default: - status = status_can_other_error; - break; - } - break; - } - - if (message->remote_frame == 0U) { - uint32_t copy_words = can_get_data_words_from_dlc(message->dlc); - - for (uint32_t i = 0; i < copy_words; i++) { - message->buffer[2U + i] = base->RBUF[2U + i]; - } - } - /* Release the current buffer */ - base->CMD_STA_CMD_CTRL |= CAN_CMD_STA_CMD_CTRL_RREL_MASK; - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t can_get_default_config(can_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - if (config != NULL) { - - /* Default timing mode */ - config->baudrate = 1000000UL; /* 1Mbit/s */ - config->baudrate_fd = 0U; - config->use_lowlevel_timing_setting = false; - config->can20_samplepoint_min = CAN_SAMPLEPOINT_MIN; - config->can20_samplepoint_max = CAN_SAMPLEPOINT_MAX; - config->canfd_samplepoint_min = CAN_SAMPLEPOINT_MIN; - config->canfd_samplepoint_max = CAN_SAMPLEPOINT_MAX; - config->enable_canfd = false; - config->enable_can_fd_iso_mode = true; - - config->mode = can_mode_normal; - config->enable_self_ack = false; - config->disable_stb_retransmission = false; - config->disable_ptb_retransmission = false; - config->enable_tx_buffer_priority_mode = false; - config->enable_tdc = false; - - /* Default filter settings */ - config->filter_list_num = 0; - config->filter_list = NULL; - - /* Default Interrupt enable settings */ - config->irq_txrx_enable_mask = 0; - config->irq_error_enable_mask = 0; - - status = status_success; - } - - return status; -} - -hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq) -{ - hpm_stat_t status = status_invalid_argument; - - do { - - HPM_BREAK_IF((base == NULL) || (config == NULL) || (src_clk_freq == 0U) || (config->filter_list_num > 16U)); - - can_reset(base, true); - - base->TTCFG &= ~CAN_TTCFG_TTEN_MASK; - base->CMD_STA_CMD_CTRL &= ~CAN_CMD_STA_CMD_CTRL_TTTBM_MASK; - - if (!config->use_lowlevel_timing_setting) { - if (config->enable_canfd) { - status = can_set_bit_timing(base, - can_bit_timing_canfd_nominal, - src_clk_freq, - config->baudrate, - config->can20_samplepoint_min, - config->can20_samplepoint_max); - HPM_BREAK_IF(status != status_success); - status = can_set_bit_timing(base, - can_bit_timing_canfd_data, - src_clk_freq, - config->baudrate_fd, - config->canfd_samplepoint_min, - config->canfd_samplepoint_max); - } else { - status = can_set_bit_timing(base, - can_bit_timing_can2_0, - src_clk_freq, - config->baudrate, - config->can20_samplepoint_min, - config->can20_samplepoint_max); - } - } else { - if (config->enable_canfd) { - bool param_valid = is_can_bit_timing_param_valid(can_bit_timing_canfd_nominal, &config->can_timing); - if (!param_valid) { - status = status_can_invalid_bit_timing; - break; - } - param_valid = is_can_bit_timing_param_valid(can_bit_timing_canfd_data, &config->canfd_timing); - if (!param_valid) { - status = status_can_invalid_bit_timing; - break; - } - can_set_slow_speed_timing(base, &config->can_timing); - can_set_fast_speed_timing(base, &config->canfd_timing); - } else { - bool param_valid = is_can_bit_timing_param_valid(can_bit_timing_can2_0, &config->can_timing); - if (!param_valid) { - status = status_can_invalid_bit_timing; - break; - } - can_set_slow_speed_timing(base, &config->can_timing); - } - status = status_success; - } - - /* Enable Transmitter Delay Compensation as needed */ - uint32_t ssp_offset = CAN_F_PRESC_F_SEG_1_GET(base->F_PRESC) + 2U; - can_set_transmitter_delay_compensation(base, ssp_offset, config->enable_tdc); - - HPM_BREAK_IF(status != status_success); - - - /* Configure the CAN filters */ - if (config->filter_list_num > CAN_FILTER_NUM_MAX) { - status = status_can_filter_num_invalid; - break; - } else if (config->filter_list_num == 0) { - can_filter_config_t default_filter = CAN_DEFAULT_FILTER_SETTING; - for (uint32_t i = 0; i < CAN_FILTER_NUM_MAX; i++) { - can_disable_filter(base, i); - } - (void) can_set_filter(base, &default_filter); - } else { - for (uint32_t i = 0; i < CAN_FILTER_NUM_MAX; i++) { - can_disable_filter(base, i); - } - for (uint32_t i = 0; i < config->filter_list_num; i++) { - status = can_set_filter(base, &config->filter_list[i]); - if (status != status_success) { - return status; - } - } - } - - /* Set CAN FD standard */ - can_enable_can_fd_iso_mode(base, config->enable_can_fd_iso_mode); - - can_reset(base, false); - - /* The following mode must be set when the CAN controller is not in reset mode */ - - /* Disable re-transmission on PTB on demand */ - can_disable_ptb_retransmission(base, config->disable_ptb_retransmission); - /* Disable re-transmission on STB on demand */ - can_disable_stb_retransmission(base, config->disable_stb_retransmission); - - /* Set Self-ack mode*/ - can_enable_self_ack(base, config->enable_self_ack); - - /* Set CAN work mode */ - can_set_node_mode(base, config->mode); - - /* Configure TX Buffer priority mode */ - can_select_tx_buffer_priority_mode(base, config->enable_tx_buffer_priority_mode); - - /* Configure interrupt */ - can_disable_tx_rx_irq(base, 0xFFU); - can_disable_error_irq(base, 0xFFU); - can_enable_tx_rx_irq(base, config->irq_txrx_enable_mask); - can_enable_error_irq(base, config->irq_error_enable_mask); - - status = status_success; - } while (false); - - return status; -} - -void can_deinit(CAN_Type *base) -{ - do { - HPM_BREAK_IF(base == NULL); - can_force_bus_off(base); - can_reset(base, true); - } while (false); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c deleted file mode 100644 index 2f13957821a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_clc_drv.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_clc_drv.h" -#include "math.h" - -void clc_config_param(CLC_Type *clc, clc_chn_t chn, clc_param_config_t *param) -{ - clc->VDVQ_CHAN[chn].EADC_LOWTH = (uint32_t)param->eadc_lowth; - clc->VDVQ_CHAN[chn].EADC_HIGHTH = (uint32_t)param->eadc_highth; - clc->VDVQ_CHAN[chn].EADC_MIDLOWTH = (uint32_t)param->eadc_mid_lowth; - clc->VDVQ_CHAN[chn].EADC_MIDHIGHTH = (uint32_t)param->eadc_mid_highth; - clc->VDVQ_CHAN[chn].P2Z2_CLAMP_LO = (uint32_t)param->_2p2z_clamp_lowth; - clc->VDVQ_CHAN[chn].P2Z2_CLAMP_HI = (uint32_t)param->_2p2z_clamp_highth; - clc->VDVQ_CHAN[chn].P3Z3_CLAMP_LO = (uint32_t)param->_3p3z_clamp_lowth; - clc->VDVQ_CHAN[chn].P3Z3_CLAMP_HI = (uint32_t)param->_3p3z_clamp_highth; - clc->VDVQ_CHAN[chn].P3Z3_FORBID_LO = (uint32_t)param->output_forbid_lowth; - clc->VDVQ_CHAN[chn].P3Z3_FORBID_MD = (uint32_t)param->output_forbid_mid; - clc->VDVQ_CHAN[chn].P3Z3_FORBID_HI = (uint32_t)param->output_forbid_highth; -} - -hpm_stat_t clc_config_coeff(CLC_Type *clc, clc_chn_t chn, clc_coeff_zone_t zone, clc_coeff_config_t *coeff) -{ - float coeff_abs[7]; - float f_max; - float f_coeff; - uint32_t u_max; - uint32_t coeff_ks; - uint32_t shift; - - coeff_abs[0] = fabsf(coeff->b0); - coeff_abs[1] = fabsf(coeff->b1); - coeff_abs[2] = fabsf(coeff->b2); - coeff_abs[3] = fabsf(coeff->b3); - coeff_abs[4] = fabsf(coeff->a0); - coeff_abs[5] = fabsf(coeff->a1); - coeff_abs[6] = fabsf(coeff->a2); - - if ((coeff_abs[0] > 0x7FFFFFFFFu) || (coeff_abs[1] > 0x7FFFFFFFFu) || (coeff_abs[2] > 0x7FFFFFFFFu) || (coeff_abs[3] >= 1.0f) - || (coeff_abs[4] > 0x7FFFFFFFFu) || (coeff_abs[5] > 0x7FFFFFFFFu) || (coeff_abs[6] >= 1.0f)) { - return status_invalid_argument; - } - - f_max = coeff_abs[0]; - for (uint8_t i = 1; i < 7u; i++) { - if (f_max < coeff_abs[i]) { - f_max = coeff_abs[i]; - } - } - u_max = (uint32_t)f_max; - - coeff_ks = 0; - for (uint8_t i = 0; i < 32u; i++) { - if (u_max == 0) { - coeff_ks = i; - break; - } - u_max >>= 1u; - } - - shift = 31u - coeff_ks; - f_coeff = (float)(uint32_t)(1u << shift); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_KS = coeff_ks; - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_B0 = (uint32_t)(int32_t)(coeff->b0 * f_coeff); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_B1 = (uint32_t)(int32_t)(coeff->b1 * f_coeff); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_B2 = (uint32_t)(int32_t)(coeff->b2 * f_coeff); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_B3 = (uint32_t)(int32_t)(coeff->b3 * (float)(0x80000000u)); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_A0 = (uint32_t)(int32_t)(coeff->a0 * f_coeff); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_A1 = (uint32_t)(int32_t)(coeff->a1 * f_coeff); - clc->VDVQ_CHAN[chn].COEFF[zone].COEFF_A2 = (uint32_t)(int32_t)(coeff->a2 * (float)(0x80000000u)); - - return status_success; -} - -void clc_sw_inject_dq_adc_value(CLC_Type *clc, uint32_t d_value, uint32_t q_value) -{ - clc_sw_inject_adc_value(clc, clc_vd_chn, d_value); - clc_sw_inject_adc_value(clc, clc_vq_chn, q_value); - clc_set_sw_inject_dq_adc_value_ready(clc); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c deleted file mode 100644 index f329c1b9788..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_crc_drv.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_crc_drv.h" - -void crc_get_default_channel_config(crc_channel_config_t *cfg) -{ - cfg->preset = crc_preset_crc32; - cfg->poly = 0x4C11DB7ul; - cfg->init = 0xFFFFFFFul; - cfg->in_byte_order = crc_in_byte_order_lsb; - cfg->refout = crc_refout_true; - cfg->refin = crc_refin_true; - cfg->poly_width = CRC_POLY_WIDTH_32; - cfg->xorout = 0xFFFFFFF; -} - -hpm_stat_t crc_setup_channel_config(CRC_Type *ptr, uint32_t ch_index, - crc_channel_config_t *cfg) -{ - ptr->CHN[ch_index].PRE_SET = cfg->preset; - - if (!ptr->CHN[ch_index].PRE_SET) { - ptr->CHN[ch_index].POLY = cfg->poly; - ptr->CHN[ch_index].INIT_DATA = cfg->init; - ptr->CHN[ch_index].XOROUT = cfg->xorout; - ptr->CHN[ch_index].MISC_SETTING = CRC_CHN_MISC_SETTING_REV_OUT_SET(cfg->refout) | - CRC_CHN_MISC_SETTING_REV_IN_SET(cfg->refin) | - CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(cfg->poly_width); - } - - ptr->CHN[ch_index].MISC_SETTING |= CRC_CHN_MISC_SETTING_BYTE_REV_SET(cfg->in_byte_order); - return status_success; -} - -void crc_calc_block_bytes(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length) -{ - uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; - - for (uint32_t i = 0; i < length; i++) { - CRC_REG_WRITE8(addr, pbuffer[i]); - } -} - -void crc_calc_block_half_words(CRC_Type *ptr, uint32_t ch_index, uint16_t *pbuffer, uint32_t length) -{ - uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; - - for (uint32_t i = 0; i < length; i++) { - CRC_REG_WRITE16(addr, pbuffer[i]); - } -} - -void crc_calc_block_words(CRC_Type *ptr, uint32_t ch_index, uint32_t *pbuffer, uint32_t length) -{ - uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; - - for (uint32_t i = 0; i < length; i++) { - CRC_REG_WRITE32(addr, pbuffer[i]); - } -} - -void crc_calc_large_block_fast(CRC_Type *ptr, uint32_t ch_index, uint8_t *pbuffer, uint32_t length) -{ - if (length < 16) { - crc_calc_block_bytes(ptr, ch_index, pbuffer, length); - return; - } - - uint32_t addr = (uint32_t)&ptr->CHN[ch_index].DATA; - uint32_t start_byte_addr = (uint32_t)pbuffer; - uint32_t start_byte_len = 4ul - (start_byte_addr & 0x03ul); - uint32_t word_addr = start_byte_addr + start_byte_len; - uint32_t word_len = (length - start_byte_len) & (~0x03ul); - uint32_t end_byte_addr = word_addr + word_len; - uint32_t end_byte_len = (length - start_byte_len - word_len); - - for (uint32_t i = 0; i < start_byte_len; i++) { - CRC_REG_WRITE8(addr, *(volatile uint8_t *)(start_byte_addr + i)); - } - - for (uint32_t i = 0; i < word_len; i += 4) { - CRC_REG_WRITE32(addr, *(volatile uint32_t *)(word_addr + i)); - } - - for (uint32_t i = 0; i < end_byte_len; i++) { - CRC_REG_WRITE8(addr, *(volatile uint8_t *)(end_byte_addr + i)); - } -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c deleted file mode 100644 index 1e312f18e89..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dac_drv.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_dac_drv.h" - -void dac_get_default_config(dac_config_t *config) -{ - config->sync_mode = false; - config->dac_mode = dac_mode_direct; - config->ana_div = dac_ana_div_2; -} - -hpm_stat_t dac_init(DAC_Type *ptr, dac_config_t *config) -{ - if (config->dac_mode > dac_mode_trig) { - return status_invalid_argument; - } - - if (config->ana_div > dac_ana_div_8) { - return status_invalid_argument; - } - - /* reset DAC output data */ - ptr->CFG0_BAK &= ~DAC_CFG0_SW_DAC_DATA_MASK; - - /* set sync mode */ - ptr->CFG0_BAK &= ~DAC_CFG0_SYNC_MODE_MASK; - ptr->CFG0_BAK |= DAC_CFG0_SYNC_MODE_SET(config->sync_mode); - - /* set DAC mode */ - ptr->CFG0_BAK &= ~DAC_CFG0_DAC_MODE_MASK; - ptr->CFG0_BAK |= DAC_CFG0_DAC_MODE_SET(config->dac_mode); - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; - - /* set DAC clock config */ - ptr->CFG1 &= ~DAC_CFG1_ANA_DIV_CFG_MASK; - ptr->CFG1 |= DAC_CFG1_ANA_DIV_CFG_SET(config->ana_div); - - if (config->dac_mode == dac_mode_direct || config->dac_mode == dac_mode_trig) { - /* set ANA_CLK_EN */ - ptr->CFG1 |= DAC_CFG1_ANA_CLK_EN_MASK; - } - - return status_success; -} - -hpm_stat_t dac_set_step_config(DAC_Type *ptr, uint8_t step_cfg_idx, dac_step_config_t *config) -{ - uint16_t temp; - - /* check the validity */ - if (step_cfg_idx > DAC_STEP_CFG_STEP3) { - return status_invalid_argument; - } - - if (config->up_down == dac_step_up) { - if (config->start_point > config->end_point) { - return status_invalid_argument; - } - } else { - if (config->start_point < config->end_point) { - return status_invalid_argument; - } - } - - /* check if the output data can reach the end point */ - if (config->step_num != 0) { - if (config->start_point <= config->end_point) { - temp = config->end_point - config->start_point; - } else { - temp = config->start_point - config->end_point; - } - - if (temp % config->step_num != 0) { - return status_invalid_argument; - } - } - - /* set the round mode */ - ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_ROUND_MODE_MASK; - ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_ROUND_MODE_SET(config->round_mode); - - /* set the step direction */ - ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_UP_DOWN_MASK; - ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_UP_DOWN_SET(config->up_down); - - /* set the start point */ - ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_START_POINT_MASK; - ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_START_POINT_SET(config->start_point); - - /* set the end point */ - ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_END_POINT_MASK; - ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_END_POINT_SET(config->end_point); - - /* set the step value */ - ptr->STEP_CFG[step_cfg_idx] &= ~DAC_STEP_CFG_STEP_NUM_MASK; - ptr->STEP_CFG[step_cfg_idx] |= DAC_STEP_CFG_STEP_NUM_SET(config->step_num); - - return status_success; -} - -hpm_stat_t dac_set_buffer_config(DAC_Type *ptr, dac_buffer_config_t *config) -{ - if (config->buf0.len == 0) { - return status_invalid_argument; - } - - /* disable the internal DMA */ - ptr->CFG0_BAK &= ~DAC_CFG0_DMA_AHB_EN_MASK; - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; - - /* set buffer data mode */ - ptr->CFG0_BAK &= ~DAC_CFG0_BUF_DATA_MODE_MASK; - ptr->CFG0_BAK |= DAC_CFG0_BUF_DATA_MODE_SET(config->buf_data_mode); - - /* set burst type */ - ptr->CFG0_BAK &= ~DAC_CFG0_HBURST_CFG_MASK; - ptr->CFG0_BAK |= DAC_CFG0_HBURST_CFG_SET(config->burst); - - /* reset DMA and FIFO */ - ptr->CFG2 |= DAC_CFG2_DMA_RST1_MASK | DAC_CFG2_DMA_RST0_MASK | DAC_CFG2_FIFO_CLR_MASK; - - /* set buffer 0 start address for DMA */ - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] &= ~DAC_BUF_ADDR_BUF_START_ADDR_MASK; - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] |= config->buf0.start_addr & DAC_BUF_ADDR_BUF_START_ADDR_MASK; - - /* set buffer 0 stop */ - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] &= ~DAC_BUF_ADDR_BUF_STOP_MASK; - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF0] |= DAC_BUF_ADDR_BUF_STOP_SET(config->buf0.stop); - - /* set buffer 0 length */ - ptr->BUF_LENGTH &= ~DAC_BUF_LENGTH_BUF0_LEN_MASK; - ptr->BUF_LENGTH |= DAC_BUF_LENGTH_BUF0_LEN_SET(config->buf0.len - 1); - - /* set buffer 1 start address for DMA */ - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] &= ~DAC_BUF_ADDR_BUF_START_ADDR_MASK; - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] |= config->buf1.start_addr & DAC_BUF_ADDR_BUF_START_ADDR_MASK; - - /* set buffer 1 stop */ - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] &= ~DAC_BUF_ADDR_BUF_STOP_MASK; - ptr->BUF_ADDR[DAC_BUF_ADDR_BUF1] |= DAC_BUF_ADDR_BUF_STOP_SET(config->buf1.stop); - - /* set buffer 1 length */ - ptr->BUF_LENGTH &= ~DAC_BUF_LENGTH_BUF1_LEN_MASK; - ptr->BUF_LENGTH |= DAC_BUF_LENGTH_BUF1_LEN_SET(config->buf1.len - 1); - - /* enable the internal DMA */ - ptr->CFG0_BAK |= DAC_CFG0_DMA_AHB_EN_MASK; - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; - - return status_success; -} - -hpm_stat_t dac_set_direct_config(DAC_Type *ptr, uint16_t data) -{ - if (data > DAC_SOC_MAX_DATA) { - return status_invalid_argument; - } - - /* set dac data to analog output */ - ptr->CFG0_BAK &= ~DAC_CFG0_SW_DAC_DATA_MASK; - ptr->CFG0_BAK |= DAC_CFG0_SW_DAC_DATA_SET(data); - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; - - return status_success; -} - -hpm_stat_t dac_set_output_frequency(DAC_Type *ptr, uint32_t dac_input_freq, uint32_t dac_output_freq) -{ - if (dac_output_freq > DAC_SOC_MAX_OUTPUT_FREQ) { - return status_invalid_argument; - } - - /* set output frequency config */ - ptr->CFG1 &= ~DAC_CFG1_DIV_CFG_MASK; - ptr->CFG1 |= DAC_CFG1_DIV_CFG_SET(dac_input_freq % dac_output_freq ? (dac_input_freq / dac_output_freq + 1) : (dac_input_freq / dac_output_freq)); - - return status_success; -} - -hpm_stat_t dac_set_step_sw_trigger(DAC_Type *ptr, uint8_t step_sw_trig_idx) -{ - if (step_sw_trig_idx > DAC_STEP_CFG_STEP3) { - return status_invalid_argument; - } - - /* disable hw trigger */ - ptr->CFG0_BAK &= ~DAC_CFG0_HW_TRIG_EN_MASK; - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; - - /* enable sw trigger */ - ptr->CFG2 |= 1 << step_sw_trig_idx; - - return status_success; -} - -void dac_set_buffer_sw_trigger(DAC_Type *ptr) -{ - /* disable hw trigger */ - ptr->CFG0_BAK &= ~DAC_CFG0_HW_TRIG_EN_MASK; - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; - - /* enable sw trigger */ - ptr->CFG2 |= DAC_CFG2_BUF_SW_TRIG_MASK; -} - -void dac_set_buffer_DMA_reset(DAC_Type *ptr) -{ - ptr->CFG2 |= DAC_CFG2_DMA_RST1_MASK | DAC_CFG2_DMA_RST0_MASK | DAC_CFG2_FIFO_CLR_MASK; -} - -void dac_set_hw_trigger_enable(DAC_Type *ptr, bool enable) -{ - ptr->CFG0_BAK &= ~DAC_CFG0_HW_TRIG_EN_MASK; - ptr->CFG0_BAK |= DAC_CFG0_HW_TRIG_EN_SET(enable); - - /* refresh the CFG0 */ - ptr->CFG0 = ptr->CFG0_BAK; -} - -void dac_enable_conversion(DAC_Type *ptr, bool enable) -{ - ptr->ANA_CFG0 &= ~DAC_ANA_CFG0_DAC12BIT_EN_MASK; - ptr->ANA_CFG0 |= DAC_ANA_CFG0_DAC12BIT_EN_SET(enable); -} - -hpm_stat_t dac_external_DMA_request_enable(DAC_Type *ptr, uint8_t buf_idx, bool enable) -{ - if (buf_idx > DAC_BUF_ADDR_BUF1) { - return status_invalid_argument; - } - - ptr->DMA_EN &= ~(1 << buf_idx); - ptr->DMA_EN |= enable << buf_idx; - - return status_success; -} - -void dac_enable_interrupts(DAC_Type *ptr, uint32_t mask) -{ - ptr->IRQ_EN |= mask; -} - -uint32_t dac_get_status_flags(DAC_Type *ptr) -{ - return ptr->IRQ_STS; -} - -void dac_set_status_flags(DAC_Type *ptr, uint32_t mask) -{ - ptr->IRQ_STS = mask; -} - -uint8_t dac_get_current_buffer_index(DAC_Type *ptr) -{ - return DAC_STATUS0_CUR_BUF_INDEX_GET(ptr->STATUS0); -} - -uint16_t dac_get_current_buffer_offset(DAC_Type *ptr) -{ - return DAC_STATUS0_CUR_BUF_OFFSET_GET(ptr->STATUS0); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c deleted file mode 100644 index 11f70a65a2b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dao_drv.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_dao_drv.h" -#include "hpm_i2s_common.h" - -void dao_get_default_config(DAO_Type *ptr, dao_config_t *config) -{ - (void) ptr; - config->enable_mono_output = false; - config->default_output_level = DAO_DEFAULT_OUTPUT_ALL_LOW; - config->channel_count = 2; -#if defined(HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG) && (HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG == 1) - config->enable_tdm_mode = false; - config->frame_start_at_rising_edge = false; - config->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; - config->channel_length = i2s_channel_length_32_bits; - config->audio_depth = i2s_audio_depth_32_bits; -#endif - config->channel_slot_mask = 0x3; /* 2 channel mask */ -} - -hpm_stat_t dao_init(DAO_Type *ptr, dao_config_t *config) -{ - if (dao_is_running(ptr)) { - dao_stop(ptr); - } - dao_software_reset(ptr); - - ptr->CTRL = DAO_CTRL_MONO_SET(config->enable_mono_output) - | DAO_CHANNEL_BOTH - | DAO_CTRL_REMAP_MASK - | DAO_CTRL_FALSE_LEVEL_SET(config->default_output_level); - -#if defined(HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG) && (HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG == 1) - ptr->RX_CFGR = DAO_RX_CFGR_FRAME_EDGE_SET(config->frame_start_at_rising_edge) - | DAO_RX_CFGR_CH_MAX_SET(config->channel_count) - | DAO_RX_CFGR_TDM_EN_SET(config->enable_tdm_mode) - | DAO_RX_CFGR_STD_SET(config->protocol) - | DAO_RX_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) - | DAO_RX_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); -#else - ptr->RX_CFGR = DAO_RX_CFGR_CH_MAX_SET(config->channel_count); -#endif - - ptr->RXSLT = config->channel_slot_mask; - - return status_success; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c deleted file mode 100644 index c46bc11291c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dma_drv.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_dma_drv.h" - -hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num, dma_channel_config_t *ch, bool start_transfer) -{ - uint32_t tmp; - - if ((ch->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch_num >= DMA_SOC_CHANNEL_NUM) - || ((ch->dst_mode == DMA_HANDSHAKE_MODE_HANDSHAKE) && (ch->src_mode == DMA_HANDSHAKE_MODE_HANDSHAKE))) { - return status_invalid_argument; - } - if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) - || (ch->src_addr & ((1 << ch->src_width) - 1)) - || (ch->dst_addr & ((1 << ch->dst_width) - 1)) - || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) - || ((ch->linked_ptr & 0x7))) { - return status_dma_alignment_error; - } - ptr->CHCTRL[ch_num].SRCADDR = DMA_CHCTRL_SRCADDR_SRCADDRL_SET(ch->src_addr); - ptr->CHCTRL[ch_num].DSTADDR = DMA_CHCTRL_DSTADDR_DSTADDRL_SET(ch->dst_addr); - ptr->CHCTRL[ch_num].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); - ptr->CHCTRL[ch_num].LLPOINTER = DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); - -#if DMA_SUPPORT_64BIT_ADDR - ptr->CHCTRL[ch_num].SRCADDRH = DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(ch->src_addr_high); - ptr->CHCTRL[ch_num].DSTADDRH = DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(ch->dst_addr_high); - ptr->CHCTRL[ch_num].LLPOINTERH = DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(ch->linked_ptr_high); -#endif - - ptr->INTSTATUS = (DMA_INTSTATUS_TC_SET(1) | DMA_INTSTATUS_ABORT_SET(1) | DMA_INTSTATUS_ERROR_SET(1)) << ch_num; - tmp = DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(0) - | DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(0) - | DMA_CHCTRL_CTRL_PRIORITY_SET(ch->priority) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(ch->src_burst_size) - | DMA_CHCTRL_CTRL_SRCWIDTH_SET(ch->src_width) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(ch->dst_width) - | DMA_CHCTRL_CTRL_SRCMODE_SET(ch->src_mode) - | DMA_CHCTRL_CTRL_DSTMODE_SET(ch->dst_mode) - | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(ch->src_addr_ctrl) - | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(ch->dst_addr_ctrl) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(ch_num) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(ch_num) - | ch->interrupt_mask; - - if (start_transfer) { - tmp |= DMA_CHCTRL_CTRL_ENABLE_MASK; - } - ptr->CHCTRL[ch_num].CTRL = tmp; - - return status_success; -} - - -void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch) -{ - (void) ptr; - ch->priority = DMA_CHANNEL_PRIORITY_LOW; - ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; - ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - ch->src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - ch->dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - ch->interrupt_mask = DMA_INTERRUPT_MASK_NONE; - ch->linked_ptr = 0; -#if DMA_SUPPORT_64BIT_ADDR - ch->linked_ptr_high = 0; -#endif -} - -hpm_stat_t dma_config_linked_descriptor(DMA_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config) -{ - uint32_t tmp; - - if ((config->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (config->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch_num >= DMA_SOC_CHANNEL_NUM) - || ((config->dst_mode == DMA_HANDSHAKE_MODE_HANDSHAKE) && (config->src_mode == DMA_HANDSHAKE_MODE_HANDSHAKE))) { - return status_invalid_argument; - } - - if ((config->size_in_byte & ((1 << config->dst_width) - 1)) - || (config->src_addr & ((1 << config->src_width) - 1)) - || (config->dst_addr & ((1 << config->dst_width) - 1)) - || ((1 << config->src_width) & ((1 << config->dst_width) - 1)) - || ((config->linked_ptr & 0x7))) { - return status_dma_alignment_error; - } - - descriptor->src_addr = DMA_CHCTRL_SRCADDR_SRCADDRL_SET(config->src_addr); - descriptor->dst_addr = DMA_CHCTRL_DSTADDR_DSTADDRL_SET(config->dst_addr); - descriptor->trans_size = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(config->size_in_byte >> config->src_width); - descriptor->linked_ptr = DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(config->linked_ptr >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); - -#if DMA_SUPPORT_64BIT_ADDR - descriptor->src_addr_high = DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(config->src_addr_high); - descriptor->dst_addr_high = DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(config->dst_addr_high); - descriptor->linked_ptr_high = DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(config->linked_ptr_high); -#endif - - tmp = DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(0) - | DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(0) - | DMA_CHCTRL_CTRL_PRIORITY_SET(config->priority) - | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(config->src_burst_size) - | DMA_CHCTRL_CTRL_SRCWIDTH_SET(config->src_width) - | DMA_CHCTRL_CTRL_DSTWIDTH_SET(config->dst_width) - | DMA_CHCTRL_CTRL_SRCMODE_SET(config->src_mode) - | DMA_CHCTRL_CTRL_DSTMODE_SET(config->dst_mode) - | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(config->src_addr_ctrl) - | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(config->dst_addr_ctrl) - | DMA_CHCTRL_CTRL_SRCREQSEL_SET(ch_num) - | DMA_CHCTRL_CTRL_DSTREQSEL_SET(ch_num) - | config->interrupt_mask - | DMA_CHCTRL_CTRL_ENABLE_MASK; - descriptor->ctrl = tmp; - - return status_success; -} - -hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num, - uint32_t dst, uint32_t src, - uint32_t size, uint32_t burst_len_in_byte) -{ - hpm_stat_t stat = status_success; - uint32_t width, count; - int32_t burst_size; - dma_channel_config_t config = {0}; - dma_default_channel_config(ptr, &config); - - /* burst size checking (1-byte burst length will cause heavy overhead */ - if (!burst_len_in_byte || burst_len_in_byte == 1 || burst_len_in_byte > size - || burst_len_in_byte > - (uint32_t) ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { - return status_invalid_argument; - } - - count = count_set_bits(burst_len_in_byte); - if ((count > 1) || (burst_len_in_byte & 0x1)) { - /* dma only supports 2^n bytes as burst size */ - return status_invalid_argument; - } - - if ((size & (burst_len_in_byte - 1))) { - return status_dma_alignment_error; - } - burst_size = get_first_set_bit_from_lsb(burst_len_in_byte); - - config.src_width = DMA_TRANSFER_WIDTH_HALF_WORD; - config.dst_width = DMA_TRANSFER_WIDTH_HALF_WORD; - for (width = DMA_SOC_TRANSFER_WIDTH_MAX(ptr); width > DMA_TRANSFER_WIDTH_HALF_WORD; width--) { - if (!(burst_len_in_byte & ((1 << width) - 1)) - && !(dst & ((1 << width) - 1)) - && !(src & ((1 << width) - 1)) - && !(size & ((1 << width) - 1))) { - config.src_width = width; - config.dst_width = width; - break; - } - } - - burst_size -= config.src_width; - do { - if (!(src & (((1 << config.src_width) << burst_size) - 1))) { - break; - } - burst_size--; - } while (burst_size > 0); - - config.src_addr = src; - config.dst_addr = dst; - config.size_in_byte = size; - - config.src_burst_size = burst_size; - stat = dma_setup_channel(ptr, ch_num, &config, true); - if (stat != status_success) { - return stat; - } - - return stat; -} - -void dma_default_handshake_config(DMA_Type *ptr, dma_handshake_config_t *config) -{ - (void) ptr; - memset(config, 0, sizeof(dma_handshake_config_t)); -} - -hpm_stat_t dma_setup_handshake(DMA_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer) -{ - hpm_stat_t stat = status_success; - dma_channel_config_t config = {0}; - dma_default_channel_config(ptr, &config); - - if (true == pconfig->dst_fixed) { - config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - } - if (true == pconfig->src_fixed) { - config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - } - - if (pconfig->ch_index >= DMA_SOC_CHANNEL_NUM) { - return status_invalid_argument; - } - - config.src_width = pconfig->data_width; - config.dst_width = pconfig->data_width; - config.src_addr = pconfig->src; - config.dst_addr = pconfig->dst; - config.size_in_byte = pconfig->size_in_byte; - /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ - config.src_burst_size = 0; - stat = dma_setup_channel(ptr, pconfig->ch_index, &config, start_transfer); - if (stat != status_success) { - return stat; - } - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c deleted file mode 100644 index 643afe61597..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_dmav2_drv.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_dmav2_drv.h" - -void dma_default_channel_config(DMAV2_Type *ptr, dma_channel_config_t *ch) -{ - (void) ptr; - ch->en_infiniteloop = false; - ch->handshake_opt = DMA_HANDSHAKE_OPT_ONE_BURST; - ch->burst_opt = DMA_SRC_BURST_OPT_STANDAND_SIZE; - ch->priority = DMA_CHANNEL_PRIORITY_LOW; - ch->src_mode = DMA_HANDSHAKE_MODE_NORMAL; - ch->dst_mode = DMA_HANDSHAKE_MODE_NORMAL; - ch->src_burst_size = DMA_NUM_TRANSFER_PER_BURST_1T; - ch->src_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - ch->dst_addr_ctrl = DMA_ADDRESS_CONTROL_INCREMENT; - ch->interrupt_mask = DMA_INTERRUPT_MASK_HALF_TC; /* disable half complete interrupt to keep align with dma */ - ch->linked_ptr = 0; -#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) - ch->en_src_burst_in_fixed_trans = false; - ch->en_dst_burst_in_fixed_trans = false; -#endif -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) - ch->swap_mode = DMA_SWAP_MODE_TABLE; - ch->swap_table = 0; -#endif -} - -hpm_stat_t dma_setup_channel(DMAV2_Type *ptr, uint8_t ch_num, dma_channel_config_t *ch, bool start_transfer) -{ - uint32_t tmp; - - if ((ch->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch_num >= DMA_SOC_CHANNEL_NUM) - || (ch->en_infiniteloop && (ch->linked_ptr != 0)) - || ((ch->dst_mode == DMA_HANDSHAKE_MODE_HANDSHAKE) && (ch->src_mode == DMA_HANDSHAKE_MODE_HANDSHAKE))) { - return status_invalid_argument; - } - - if ((ch->size_in_byte & ((1 << ch->dst_width) - 1)) - || (ch->src_addr & ((1 << ch->src_width) - 1)) - || (ch->dst_addr & ((1 << ch->dst_width) - 1)) - || ((1 << ch->src_width) & ((1 << ch->dst_width) - 1)) - || ((ch->linked_ptr & 0x7))) { - return status_dma_alignment_error; - } - - ptr->CHCTRL[ch_num].SRCADDR = DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(ch->src_addr); - ptr->CHCTRL[ch_num].DSTADDR = DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(ch->dst_addr); - ptr->CHCTRL[ch_num].TRANSIZE = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(ch->size_in_byte >> ch->src_width); - ptr->CHCTRL[ch_num].LLPOINTER = DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(ch->linked_ptr >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); - ptr->CHCTRL[ch_num].CHANREQCTRL = DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(ch_num) | DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(ch_num); -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) - ptr->CHCTRL[ch_num].SWAPTABLE = ch->swap_table; -#endif - - dma_clear_transfer_status(ptr, ch_num); - tmp = DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(ch->en_infiniteloop) - | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(ch->handshake_opt) - | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(ch->burst_opt) - | DMAV2_CHCTRL_CTRL_PRIORITY_SET(ch->priority) - | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(ch->src_burst_size) - | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(ch->src_width) - | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(ch->dst_width) - | DMAV2_CHCTRL_CTRL_SRCMODE_SET(ch->src_mode) - | DMAV2_CHCTRL_CTRL_DSTMODE_SET(ch->dst_mode) - | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(ch->src_addr_ctrl) - | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(ch->dst_addr_ctrl) -#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) - | DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SET(ch->en_src_burst_in_fixed_trans) - | DMAV2_CHCTRL_CTRL_DST_FIXBURST_SET(ch->en_dst_burst_in_fixed_trans) -#endif -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) - | DMAV2_CHCTRL_CTRL_SWAP_CTL_SET(ch->swap_mode) -#endif - | ch->interrupt_mask; - - if (start_transfer) { - tmp |= DMAV2_CHCTRL_CTRL_ENABLE_MASK; - } - ptr->CHCTRL[ch_num].CTRL = tmp; - - return status_success; -} - -hpm_stat_t dma_config_linked_descriptor(DMAV2_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config) -{ - (void) ptr; - uint32_t tmp; - - if ((config->dst_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (config->src_width > DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) - || (ch_num >= DMA_SOC_CHANNEL_NUM) - || (config->en_infiniteloop) - || ((config->dst_mode == DMA_HANDSHAKE_MODE_HANDSHAKE) && (config->src_mode == DMA_HANDSHAKE_MODE_HANDSHAKE))) { - return status_invalid_argument; - } - - if ((config->size_in_byte & ((1 << config->dst_width) - 1)) - || (config->src_addr & ((1 << config->src_width) - 1)) - || (config->dst_addr & ((1 << config->dst_width) - 1)) - || ((1 << config->src_width) & ((1 << config->dst_width) - 1)) - || ((config->linked_ptr & 0x7))) { - return status_dma_alignment_error; - } - - descriptor->src_addr = DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(config->src_addr); - descriptor->dst_addr = DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(config->dst_addr); - descriptor->trans_size = DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(config->size_in_byte >> config->src_width); - descriptor->linked_ptr = DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(config->linked_ptr >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT); - descriptor->req_ctrl = DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(ch_num) | DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(ch_num); -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) - descriptor->swap_table = config->swap_table; -#endif - - tmp = DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(false) - | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(config->handshake_opt) - | DMAV2_CHCTRL_CTRL_BURSTOPT_SET(config->burst_opt) - | DMAV2_CHCTRL_CTRL_PRIORITY_SET(config->priority) - | DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(config->src_burst_size) - | DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(config->src_width) - | DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(config->dst_width) - | DMAV2_CHCTRL_CTRL_SRCMODE_SET(config->src_mode) - | DMAV2_CHCTRL_CTRL_DSTMODE_SET(config->dst_mode) - | DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(config->src_addr_ctrl) - | DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(config->dst_addr_ctrl) -#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1) - | DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SET(config->en_src_burst_in_fixed_trans) - | DMAV2_CHCTRL_CTRL_DST_FIXBURST_SET(config->en_dst_burst_in_fixed_trans) -#endif -#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1) - | DMAV2_CHCTRL_CTRL_SWAP_CTL_SET(config->swap_mode) -#endif - | config->interrupt_mask - | DMAV2_CHCTRL_CTRL_ENABLE_MASK; - descriptor->ctrl = tmp; - - return status_success; -} - -hpm_stat_t dma_start_memcpy(DMAV2_Type *ptr, uint8_t ch_num, - uint32_t dst, uint32_t src, - uint32_t size, uint32_t burst_len_in_byte) -{ - hpm_stat_t stat = status_success; - uint32_t width, count; - uint32_t burst_size; - dma_channel_config_t config = {0}; - dma_default_channel_config(ptr, &config); - - /* burst size checking (1-byte burst length will cause heavy overhead */ - if (!burst_len_in_byte || burst_len_in_byte == 1 || burst_len_in_byte > size - || burst_len_in_byte > - (uint32_t) ((1 << DMA_SOC_TRANSFER_WIDTH_MAX(ptr)) << DMA_SOC_TRANSFER_PER_BURST_MAX(ptr))) { - return status_invalid_argument; - } - - count = count_set_bits(burst_len_in_byte); - if ((count > 1) || (burst_len_in_byte & 0x1)) { - /* dma only supports 2^n bytes as burst size */ - return status_invalid_argument; - } - - if ((size & (burst_len_in_byte - 1))) { - return status_dma_alignment_error; - } - burst_size = get_first_set_bit_from_lsb(burst_len_in_byte); - - config.src_width = DMA_TRANSFER_WIDTH_HALF_WORD; - config.dst_width = DMA_TRANSFER_WIDTH_HALF_WORD; - for (width = DMA_SOC_TRANSFER_WIDTH_MAX(ptr); width > DMA_TRANSFER_WIDTH_HALF_WORD; width--) { - if (!(burst_len_in_byte & ((1 << width) - 1)) - && !(dst & ((1 << width) - 1)) - && !(src & ((1 << width) - 1)) - && !(size & ((1 << width) - 1))) { - config.src_width = width; - config.dst_width = width; - break; - } - } - - burst_size -= config.src_width; - do { - if (!(src & (((1 << config.src_width) << burst_size) - 1))) { - break; - } - burst_size--; - } while (burst_size > 0); - - config.src_addr = src; - config.dst_addr = dst; - config.size_in_byte = size; - - config.src_burst_size = burst_size; - stat = dma_setup_channel(ptr, ch_num, &config, true); - if (stat != status_success) { - return stat; - } - - return stat; -} - -void dma_default_handshake_config(DMAV2_Type *ptr, dma_handshake_config_t *config) -{ - (void) ptr; - memset(config, 0, sizeof(dma_handshake_config_t)); - config->en_infiniteloop = false; - config->interrupt_mask = DMA_INTERRUPT_MASK_HALF_TC; -} - -hpm_stat_t dma_setup_handshake(DMAV2_Type *ptr, dma_handshake_config_t *pconfig, bool start_transfer) -{ - hpm_stat_t stat = status_success; - dma_channel_config_t config = {0}; - dma_default_channel_config(ptr, &config); - - if (true == pconfig->dst_fixed) { - config.dst_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - config.dst_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - } - if (true == pconfig->src_fixed) { - config.src_addr_ctrl = DMA_ADDRESS_CONTROL_FIXED; - config.src_mode = DMA_HANDSHAKE_MODE_HANDSHAKE; - } - - if (pconfig->ch_index >= DMA_SOC_CHANNEL_NUM) { - return status_invalid_argument; - } - - config.en_infiniteloop = pconfig->en_infiniteloop; - config.interrupt_mask = pconfig->interrupt_mask; - config.src_width = pconfig->data_width; - config.dst_width = pconfig->data_width; - config.src_addr = pconfig->src; - config.dst_addr = pconfig->dst; - config.size_in_byte = pconfig->size_in_byte; - /* In DMA handshake case, source burst size must be 1 transfer, that is 0. */ - config.src_burst_size = 0; - stat = dma_setup_channel(ptr, pconfig->ch_index, &config, start_transfer); - if (stat != status_success) { - return stat; - } - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c deleted file mode 100644 index 3a437a03e52..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enc_pos_drv.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_enc_pos_drv.h" - - -float encoder_position_to_deg(uint32_t pos) -{ - double tmp; - - tmp = ((double)pos / (double)0xFFFFFFFF) * (double)360.0; - - return (float)tmp; -} - -uint32_t encoder_deg_to_position(float deg) -{ - double tmp; - - while (deg < 0) { - deg += 360; - } - while (deg > 360) { - deg -= 360; - } - - tmp = ((double)deg / (double)360.0) * (double)0xFFFFFFFF; - - return (uint32_t)tmp; -} - -float encoder_position_to_rad(uint32_t pos) -{ - double tmp; - const double _2pi = 6.283185307179586; - - tmp = ((double)pos / (double)0xFFFFFFFF) * _2pi; - - return (float)tmp; -} - -uint32_t encoder_rad_to_position(float rad) -{ - double tmp; - const double _2pi = 6.283185307179586; - - while (rad < 0) { - rad += _2pi; - } - while (rad > _2pi) { - rad -= _2pi; - } - - tmp = ((double)rad / _2pi) * (double)0xFFFFFFFF; - - return (uint32_t)tmp; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c deleted file mode 100644 index 65bc39a91de..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_enet_drv.c +++ /dev/null @@ -1,955 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Includes - *--------------------------------------------------------------------- - */ -#include "hpm_enet_drv.h" -#include "hpm_enet_soc_drv.h" - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ -static void enet_mode_init(ENET_Type *ptr, uint32_t intr) -{ - /* receive and transmit store and forward */ - ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_RSF_MASK | ENET_DMA_OP_MODE_TSF_MASK; - - /* enalbe hardware flow control */ - ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_EFC_MASK; - - /* enable error frame and undersized good frame forwarding */ - ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_FEF_MASK; - - /* disable osf mode */ - ptr->DMA_OP_MODE &= ~ENET_DMA_OP_MODE_OSF_MASK; - - ptr->DMA_INTR_EN |= intr; - - while (ENET_DMA_BUS_STATUS_AXIRDSTS_GET(ptr->DMA_BUS_STATUS) || ENET_DMA_BUS_STATUS_AXWHSTS_GET(ptr->DMA_BUS_STATUS)) { - } - - /* start the receive and transmit dma */ - ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_ST_MASK | ENET_DMA_OP_MODE_SR_MASK; -} - -static int enet_dma_init(ENET_Type *ptr, enet_desc_t *desc, uint32_t intr, uint8_t pbl) -{ - /* generate software reset */ - ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_SWR_MASK; - - /* wait for the completion of reset process */ - while (ENET_DMA_BUS_MODE_SWR_GET(ptr->DMA_BUS_MODE)) { - } - - /* initialize bus mode register */ - ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_AAL_MASK; - - ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_FB_MASK; - - /* enable pblx8 mode */ - ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBLX8_MASK; - - /* set programmable burst length */ - ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_PBL_MASK; - ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_PBL_SET(pbl); - - /* disable separate pbl */ - ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_USP_MASK; - - /* descriptor length */ -#if ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MIN_LEN - ptr->DMA_BUS_MODE &= ~ENET_DMA_BUS_MODE_ATDS_MASK; -#elif ENET_SOC_ALT_EHD_DES_LEN == ENET_SOC_ALT_EHD_DES_MAX_LEN - ptr->DMA_BUS_MODE |= ENET_DMA_BUS_MODE_ATDS_MASK; - #endif - - /* set the maximum enabled burst length */ - if (ENET_DMA_BUS_MODE_FB_GET(ptr->DMA_BUS_MODE) == 0) { - ptr->DMA_AXI_MODE |= ENET_DMA_AXI_MODE_BLEN4_MASK | ENET_DMA_AXI_MODE_BLEN8_MASK | ENET_DMA_AXI_MODE_BLEN16_MASK; - } else { - /* TODO: set BLENX_MASK */ - } - - /* initialize Tx descriptors list: chain mode */ - enet_dma_tx_desc_chain_init(ptr, desc); - - /* initialize Rx descriptors list: Chain Mode */ - enet_dma_rx_desc_chain_init(ptr, desc); - - enet_mode_init(ptr, intr); - - enet_dma_flush(ptr); - - return true; -} - -static int enet_mac_init(ENET_Type *ptr, enet_mac_config_t *config, enet_inf_type_t inf_type) -{ - for (int i = 0; i < config->valid_max_count; i++) { - if (i == 0) { - ptr->MAC_ADDR_0_HIGH &= ~ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK; - ptr->MAC_ADDR_0_LOW &= ~ENET_MAC_ADDR_0_LOW_ADDRLO_MASK; - ptr->MAC_ADDR_0_HIGH |= ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(config->mac_addr_high[i]); - ptr->MAC_ADDR_0_LOW |= ENET_MAC_ADDR_0_LOW_ADDRLO_SET(config->mac_addr_low[i]); - } else { - ptr->MAC_ADDR[i-1].HIGH &= ~ENET_MAC_ADDR_HIGH_ADDRHI_MASK; - ptr->MAC_ADDR[i-1].LOW &= ~ENET_MAC_ADDR_LOW_ADDRLO_MASK; - ptr->MAC_ADDR[i-1].HIGH |= ENET_MAC_ADDR_HIGH_AE_MASK | ENET_MAC_ADDR_HIGH_ADDRHI_SET(config->mac_addr_high[i]); - ptr->MAC_ADDR[i-1].LOW |= ENET_MAC_ADDR_LOW_ADDRLO_SET(config->mac_addr_low[i]); - } - } - - /* set the appropriate filters for the incoming frames */ - ptr->MACFF |= ENET_MACFF_RA_SET(1); /* receive all */ - - /* replace the content of the mac address 0 in the sa field of all transmitted frames */ - ptr->MACCFG &= ~ENET_MACCFG_SARC_MASK; - ptr->MACCFG |= ENET_MACCFG_SARC_SET(config->sarc); - - ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; - - if (inf_type == enet_inf_rgmii) { - ptr->MACCFG &= ~ENET_MACCFG_PS_MASK; - } else if (inf_type == enet_inf_rmii) { - ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; - } -#if defined(HPM_IP_FEATURE_ENET_HAS_MII_MODE) && HPM_IP_FEATURE_ENET_HAS_MII_MODE - else if (inf_type == enet_inf_mii) { - ptr->MACCFG |= ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK; - } -#endif - else { - return status_invalid_argument; - } - - ptr->MACCFG |= ENET_MACCFG_DM_MASK; - - if (ENET_MACCFG_DM_GET(ptr->MACCFG) == 0) { - ptr->MACCFG |= ENET_MACCFG_IFG_SET(4); - } else { - ptr->MACCFG |= ENET_MACCFG_IFG_SET(2); - } - - - /* enable transmitter enable and receiver */ - ptr->MACCFG |= ENET_MACCFG_TE_MASK | ENET_MACCFG_RE_MASK; - - return true; -} - -static void enet_mask_interrupt_event(ENET_Type *ptr, uint32_t mask) -{ - /* mask the specified interrupts */ - ptr->INTR_MASK |= mask; -} - -/*--------------------------------------------------------------------- - * Driver API - *--------------------------------------------------------------------- - */ -uint32_t enet_get_interrupt_status(ENET_Type *ptr) -{ - return ptr->INTR_STATUS; -} - -void enet_mask_mmc_rx_interrupt_event(ENET_Type *ptr, uint32_t mask) -{ - ptr->MMC_INTR_MASK_RX |= mask; -} - -uint32_t enet_get_mmc_rx_interrupt_status(ENET_Type *ptr) -{ - return ptr->MMC_INTR_RX; -} - -void enet_mask_mmc_tx_interrupt_event(ENET_Type *ptr, uint32_t mask) -{ - ptr->MMC_INTR_MASK_TX |= mask; -} - -uint32_t enet_get_mmc_tx_interrupt_status(ENET_Type *ptr) -{ - return ptr->MMC_INTR_TX; -} - -void enet_dma_flush(ENET_Type *ptr) -{ - /* flush DMA transmit FIFO */ - ptr->DMA_OP_MODE |= ENET_DMA_OP_MODE_FTF_MASK; - while (ENET_DMA_OP_MODE_FTF_GET(ptr->DMA_OP_MODE)) { - - } -} - -void enet_write_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr, uint32_t data) -{ - /* set data to be written */ - ptr->GMII_DATA = ENET_GMII_DATA_GD_SET(data); - - /* set phy address , register address, write operation and busy flag */ - ptr->GMII_ADDR = ENET_GMII_ADDR_PA_SET(phy_addr) - | ENET_GMII_ADDR_GR_SET(addr) - | ENET_GMII_ADDR_CR_SET(enet_csr_150m_to_250m_mdc_csr_div_102) - | ENET_GMII_ADDR_GW_SET(enet_phy_op_write) - | ENET_GMII_ADDR_GB_SET(enet_gmii_busy); - - /* wait until the write operation is completed */ - while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) { - } -} - -uint16_t enet_read_phy(ENET_Type *ptr, uint32_t phy_addr, uint32_t addr) -{ - /* set phy address, register address, read operation and busy flag */ - ptr->GMII_ADDR = ENET_GMII_ADDR_PA_SET(phy_addr) - | ENET_GMII_ADDR_GR_SET(addr) - | ENET_GMII_ADDR_CR_SET(enet_csr_150m_to_250m_mdc_csr_div_102) - | ENET_GMII_ADDR_GW_SET(enet_phy_op_read) - | ENET_GMII_ADDR_GB_SET(enet_gmii_busy); - - /* wait until the write operation is completed */ - while (ENET_GMII_ADDR_GB_GET(ptr->GMII_ADDR)) { - } - - /* read and return data */ - return (uint16_t)ENET_GMII_DATA_GD_GET(ptr->GMII_DATA); -} - -void enet_set_line_speed(ENET_Type *ptr, enet_line_speed_t speed) -{ - ptr->MACCFG &= ~(ENET_MACCFG_PS_MASK | ENET_MACCFG_FES_MASK); - ptr->MACCFG |= speed << ENET_MACCFG_FES_SHIFT; -} - -void enet_set_duplex_mode(ENET_Type *ptr, enet_duplex_mode_t mode) -{ - ptr->MACCFG &= ~ENET_MACCFG_DM_MASK; - ptr->MACCFG |= ENET_MACCFG_DM_SET(mode); -} - -hpm_stat_t enet_controller_init(ENET_Type *ptr, enet_inf_type_t inf_type, enet_desc_t *desc, enet_mac_config_t *config, enet_int_config_t *int_config) -{ - /* select an interface */ - enet_intf_selection(ptr, inf_type); - - /* initialize DMA */ - enet_dma_init(ptr, desc, int_config->int_enable, config->dma_pbl); - - /* initialize MAC */ - enet_mac_init(ptr, config, inf_type); - - /* mask the specified interrupts */ - enet_mask_interrupt_event(ptr, int_config->int_mask); - - /* mask the mmc rx interrupts */ - enet_mask_mmc_rx_interrupt_event(ptr, int_config->mmc_intr_mask_rx); - - /* mask the mmc tx interrupts */ - enet_mask_mmc_tx_interrupt_event(ptr, int_config->mmc_intr_mask_tx); - - return status_success; -} - -/***************************************************************************** - * DMA API - ****************************************************************************/ -void enet_rx_resume(ENET_Type *ptr) -{ - if (ENET_DMA_STATUS_RU_GET(ptr->DMA_STATUS)) { - ptr->DMA_STATUS = ENET_DMA_STATUS_RU_MASK; - ptr->DMA_RX_POLL_DEMAND = 1; - } -} - -uint32_t enet_check_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) -{ - enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; - - /* check if the last segment */ - if ((rx_desc_list_cur->rdes0_bm.own == 0) && - (rx_desc_list_cur->rdes0_bm.ls == 1)) { - rx_frame_info->seg_count++; - if (rx_frame_info->seg_count == 1) { - rx_frame_info->fs_rx_desc = rx_desc_list_cur; - } - rx_frame_info->ls_rx_desc = rx_desc_list_cur; - return 1; - } - /* check if the first segment */ - else if ((rx_desc_list_cur->rdes0_bm.own == 0) && - (rx_desc_list_cur->rdes0_bm.fs == 1) && - (rx_desc_list_cur->rdes0_bm.ls == 0)) { - rx_frame_info->fs_rx_desc = rx_desc_list_cur; - rx_frame_info->ls_rx_desc = NULL; - rx_frame_info->seg_count = 1; - rx_desc_list_cur = (enet_rx_desc_t *)rx_desc_list_cur->rdes3_bm.next_desc; - *parent_rx_desc_list_cur = rx_desc_list_cur; - } - - /* check if intermediate segments */ - else if ((rx_desc_list_cur->rdes0_bm.own == 0) && - (rx_desc_list_cur->rdes0_bm.fs == 0) && - (rx_desc_list_cur->rdes0_bm.ls == 0)) { - rx_frame_info->seg_count++; - rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); - *parent_rx_desc_list_cur = rx_desc_list_cur; - } - - return 0; -} - -enet_frame_t enet_get_received_frame(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info) -{ - uint32_t frame_length = 0; - enet_frame_t frame = {0, 0, 0}; - enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; - - /* get the frame length of the received packet: substruct 4 bytes of the CRC */ - frame_length = rx_desc_list_cur->rdes0_bm.fl - 4; - frame.length = frame_length; - - /* get the address of the first frame descriptor and the buffer start address */ - frame.rx_desc = rx_frame_info->fs_rx_desc; - frame.buffer = rx_frame_info->fs_rx_desc->rdes2_bm.buffer1; - - /* update the Ethernet dma global Rx descriptor with next Rx descriptor */ - /* chained mode */ - /* selects the next dma Rx descriptor list for next buffer to read */ - rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); - *parent_rx_desc_list_cur = rx_desc_list_cur; - - return frame; -} - -enet_frame_t enet_get_received_frame_interrupt(enet_rx_desc_t **parent_rx_desc_list_cur, enet_rx_frame_info_t *rx_frame_info, uint32_t rx_desc_count) -{ - enet_frame_t frame = {0, 0, 0}; - uint32_t desc_scan_counter = 0; - enet_rx_desc_t *rx_desc_list_cur = *parent_rx_desc_list_cur; - - /* scan descriptors owned by CPU */ - while ((rx_desc_list_cur->rdes0_bm.own == 0) && - (desc_scan_counter < rx_desc_count)) { - - desc_scan_counter++; - - /* check if first segment in frame */ - if ((rx_desc_list_cur->rdes0_bm.fs == 1) && - (rx_desc_list_cur->rdes0_bm.ls == 0)) { - rx_frame_info->fs_rx_desc = rx_desc_list_cur; - rx_frame_info->seg_count = 1; - rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); - *parent_rx_desc_list_cur = rx_desc_list_cur; - } - - /* check if intermediate segment */ - else if ((rx_desc_list_cur->rdes0_bm.ls == 0) && - (rx_desc_list_cur->rdes0_bm.fs == 0)) { - rx_frame_info->seg_count++; - rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); - *parent_rx_desc_list_cur = rx_desc_list_cur; - } - - /* should be last segment */ - else { - /* last segment */ - rx_frame_info->ls_rx_desc = rx_desc_list_cur; - - rx_frame_info->seg_count++; - - /* first segment is last segment */ - if (rx_frame_info->seg_count == 1) { - rx_frame_info->fs_rx_desc = rx_desc_list_cur; - } - - /* get the frame length of the received packet: substruct 4 bytes of the crc */ - frame.length = rx_desc_list_cur->rdes0_bm.fl - 4; - - /* get the address of the buffer start address */ - /* check if more than one segment in the frame */ - if (rx_frame_info->seg_count > 1) { - frame.buffer = rx_frame_info->fs_rx_desc->rdes2_bm.buffer1; - } else { - frame.buffer = rx_desc_list_cur->rdes2_bm.buffer1; - } - - frame.rx_desc = rx_frame_info->fs_rx_desc; - - rx_desc_list_cur = (enet_rx_desc_t *)(rx_desc_list_cur->rdes3_bm.next_desc); - *parent_rx_desc_list_cur = rx_desc_list_cur; - - return frame; - } - } - - return frame; -} - -void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config) -{ - (void) ptr; - config->enable_ioc = false; - config->disable_crc = true; - config->disable_pad = false; - config->enable_ttse = false; - config->enable_crcr = true; - config->cic = enet_cic_ip_pseudoheader; - config->vlic = enet_vlic_disable; - config->saic = enet_saic_disable; -} - -void enet_get_default_interrupt_config(ENET_Type *ptr, enet_int_config_t *config) -{ - (void) ptr; - - config->int_enable = enet_normal_int_sum_en /* Enable normal interrupt summary */ - | enet_receive_int_en; /* Enable receive interrupt */ - - config->int_mask = enet_rgsmii_int_mask /* Disable RGSMII interrupt */ - | enet_lpi_int_mask; /* Disable LPI interrupt */ - - config->mmc_intr_mask_rx = 0x03ffffff; /* Disable all mmc rx interrupt events */ - config->mmc_intr_mask_tx = 0x03ffffff; /* Disable all mmc tx interrupt events */ -} - -uint32_t enet_prepare_tx_desc_with_ts_record(ENET_Type *ptr, - enet_tx_desc_t **parent_tx_desc_list_cur, - enet_tx_control_config_t *config, - uint16_t frame_length, uint16_t tx_buff_size, - enet_ptp_ts_system_t *timestamp) -{ - uint32_t buf_count = 0, size = 0, i = 0; - uint32_t retry_cnt = ENET_RETRY_CNT; - enet_tx_desc_t *dma_tx_desc; - enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; - - if (tx_buff_size == 0) { - return ENET_ERROR; - } - /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ - - dma_tx_desc = tx_desc_list_cur; - - if (frame_length > tx_buff_size) { - buf_count = frame_length / tx_buff_size; - if (frame_length % tx_buff_size) { - buf_count++; - } - } else { - buf_count = 1; - } - - if (buf_count == 1) { - /*set the last and the first segment */ - dma_tx_desc->tdes0_bm.own = 0; - dma_tx_desc->tdes0_bm.fs = 1; - dma_tx_desc->tdes0_bm.ls = 1; - dma_tx_desc->tdes0_bm.ic = config->enable_ioc; - dma_tx_desc->tdes0_bm.dc = config->disable_crc; - dma_tx_desc->tdes0_bm.dp = config->disable_pad; - dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; - dma_tx_desc->tdes0_bm.cic = config->cic; - dma_tx_desc->tdes0_bm.vlic = config->vlic; - dma_tx_desc->tdes0_bm.ttse = config->enable_ttse; - dma_tx_desc->tdes1_bm.saic = config->saic; - /* set the frame size */ - dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); - /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ - dma_tx_desc->tdes0 |= 1 << 31; - ptr->DMA_TX_POLL_DEMAND = 1; - - if (dma_tx_desc->tdes0_bm.ttse == true) { - do { - - } while (dma_tx_desc->tdes0_bm.own == 1 && retry_cnt-- > 0); - - if (retry_cnt == 0) { - return ENET_ERROR; - } - - timestamp->sec = dma_tx_desc->tdes7_bm.ttsh; - timestamp->nsec = dma_tx_desc->tdes6_bm.ttsl; - } - - dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); - } else { - for (i = 0; i < buf_count; i++) { - /* get the next available tx descriptor */ - dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); - - /* clear first and last segment bits */ - dma_tx_desc->tdes0_bm.fs = 0; - dma_tx_desc->tdes0_bm.ls = 0; - - if (i == 0) { - /* setting the first segment bit */ - dma_tx_desc->tdes0_bm.fs = 1; - dma_tx_desc->tdes0_bm.dc = config->disable_crc; - dma_tx_desc->tdes0_bm.dp = config->disable_pad; - dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; - dma_tx_desc->tdes0_bm.cic = config->cic; - dma_tx_desc->tdes0_bm.vlic = config->vlic; - dma_tx_desc->tdes0_bm.ttse = config->enable_ttse; - dma_tx_desc->tdes1_bm.saic = config->saic; - - if (dma_tx_desc->tdes0_bm.ttse == true) { - do { - - } while (dma_tx_desc->tdes0_bm.own == 1 && retry_cnt-- > 0); - - if (retry_cnt == 0) { - return ENET_ERROR; - } - - timestamp->sec = dma_tx_desc->tdes7_bm.ttsh; - timestamp->nsec = dma_tx_desc->tdes6_bm.ttsl; - } - } - - /* set the buffer 1 size */ - dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); - - if (i == (buf_count - 1)) { - /* set the last segment bit */ - dma_tx_desc->tdes0_bm.ls = 1; - dma_tx_desc->tdes0_bm.ic = config->enable_ioc; - size = frame_length - (buf_count - 1) * tx_buff_size; - dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); - - /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ - dma_tx_desc->tdes0 |= 1 << 31; - ptr->DMA_TX_POLL_DEMAND = 1; - } - } - } - - tx_desc_list_cur = dma_tx_desc; - *parent_tx_desc_list_cur = tx_desc_list_cur; - - return ENET_SUCCESS; -} - -uint32_t enet_prepare_tx_desc(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, enet_tx_control_config_t *config, uint16_t frame_length, uint16_t tx_buff_size) -{ - uint32_t buf_count = 0, size = 0, i = 0; - enet_tx_desc_t *dma_tx_desc; - enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; - - if (tx_buff_size == 0) { - return ENET_ERROR; - } - /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ - dma_tx_desc = tx_desc_list_cur; - if (frame_length > tx_buff_size) { - buf_count = frame_length / tx_buff_size; - if (frame_length % tx_buff_size) { - buf_count++; - } - } else { - buf_count = 1; - } - - if (buf_count == 1) { - /*set the last and the first segment */ - dma_tx_desc->tdes0_bm.own = 0; - dma_tx_desc->tdes0_bm.fs = 1; - dma_tx_desc->tdes0_bm.ls = 1; - dma_tx_desc->tdes0_bm.ic = config->enable_ioc; - dma_tx_desc->tdes0_bm.dc = config->disable_crc; - dma_tx_desc->tdes0_bm.dp = config->disable_pad; - dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; - dma_tx_desc->tdes0_bm.cic = config->cic; - dma_tx_desc->tdes0_bm.vlic = config->vlic; - dma_tx_desc->tdes1_bm.saic = config->saic; - /* set the frame size */ - dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); - /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ - dma_tx_desc->tdes0 |= 1 << 31; - ptr->DMA_TX_POLL_DEMAND = 1; - - dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); - } else { - for (i = 0; i < buf_count; i++) { - /* clear first and last segment bits */ - dma_tx_desc->tdes0_bm.fs = 0; - dma_tx_desc->tdes0_bm.ls = 0; - - if (i == 0) { - /* setting the first segment bit */ - dma_tx_desc->tdes0_bm.fs = 1; - dma_tx_desc->tdes0_bm.dc = config->disable_crc; - dma_tx_desc->tdes0_bm.dp = config->disable_pad; - dma_tx_desc->tdes0_bm.crcr = config->enable_crcr; - dma_tx_desc->tdes0_bm.cic = config->cic; - dma_tx_desc->tdes0_bm.vlic = config->vlic; - dma_tx_desc->tdes1_bm.saic = config->saic; - } - - /* set the buffer 1 size */ - dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); - - if (i == (buf_count - 1)) { - /* set the last segment bit */ - dma_tx_desc->tdes0_bm.ls = 1; - dma_tx_desc->tdes0_bm.ic = config->enable_ioc; - size = frame_length - (buf_count - 1) * tx_buff_size; - dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); - - /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ - dma_tx_desc->tdes0 |= 1 << 31; - ptr->DMA_TX_POLL_DEMAND = 1; - } - - dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); - } - } - - tx_desc_list_cur = dma_tx_desc; - *parent_tx_desc_list_cur = tx_desc_list_cur; - - return ENET_SUCCESS; -} - -uint32_t enet_prepare_transmission_descriptors(ENET_Type *ptr, enet_tx_desc_t **parent_tx_desc_list_cur, uint16_t frame_length, uint16_t tx_buff_size) -{ - uint32_t buf_count = 0, size = 0, i = 0; - enet_tx_desc_t *dma_tx_desc; - enet_tx_desc_t *tx_desc_list_cur = *parent_tx_desc_list_cur; - - if (tx_buff_size == 0) { - return ENET_ERROR; - } - /* check if the descriptor is owned by the Ethernet DMA (when set) or CPU (when reset) */ - dma_tx_desc = tx_desc_list_cur; - if (frame_length > tx_buff_size) { - buf_count = frame_length / tx_buff_size; - if (frame_length % tx_buff_size) { - buf_count++; - } - } else { - buf_count = 1; - } - - if (buf_count == 1) { - /*set the last and the first segment */ - dma_tx_desc->tdes0_bm.own = 0; - dma_tx_desc->tdes0_bm.ic = 0; - dma_tx_desc->tdes0_bm.fs = 1; - dma_tx_desc->tdes0_bm.ls = 1; - dma_tx_desc->tdes0_bm.dc = 1; - dma_tx_desc->tdes0_bm.dp = 0; - dma_tx_desc->tdes0_bm.crcr = 1; - dma_tx_desc->tdes0_bm.cic = 3; - dma_tx_desc->tdes1_bm.saic = 2; - - /* set the frame size */ - dma_tx_desc->tdes1_bm.tbs1 = (frame_length & ENET_DMATxDesc_TBS1); - /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ - dma_tx_desc->tdes0 |= 1 << 31; - ptr->DMA_TX_POLL_DEMAND = 1; - - dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); - } else { - for (i = 0; i < buf_count; i++) { - /* clear first and last segment bits */ - dma_tx_desc->tdes0_bm.fs = 0; - dma_tx_desc->tdes0_bm.ls = 0; - - if (i == 0) { - /* setting the first segment bit */ - dma_tx_desc->tdes0_bm.fs = 1; - } - - /* set the buffer 1 size */ - dma_tx_desc->tdes1_bm.tbs1 = (tx_buff_size & ENET_DMATxDesc_TBS1); - - if (i == (buf_count - 1)) { - /* set the last segment bit */ - dma_tx_desc->tdes0_bm.ls = 1; - size = frame_length - (buf_count - 1) * tx_buff_size; - dma_tx_desc->tdes1_bm.tbs1 = (size & ENET_DMATxDesc_TBS1); - - /* set own bit of the Tx descriptor status: gives the buffer back to Ethernet DMA */ - dma_tx_desc->tdes0 |= 1 << 31; - ptr->DMA_TX_POLL_DEMAND = 1; - } - - dma_tx_desc = (enet_tx_desc_t *)(dma_tx_desc->tdes3_bm.next_desc); - } - } - - tx_desc_list_cur = dma_tx_desc; - *parent_tx_desc_list_cur = tx_desc_list_cur; - - return ENET_SUCCESS; -} - -void enet_dma_tx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc) -{ - uint32_t i = 0; - enet_tx_desc_t *dma_tx_desc; - - /* set the tx_desc_list_cur pointer with the first one of the dma_tx_desc_tab list */ - desc->tx_desc_list_cur = desc->tx_desc_list_head; - - /* fill each dma_tx_desc descriptor with the right values */ - for (i = 0; i < desc->tx_buff_cfg.count; i++) { - - /* get the pointer on the ith member of the Tx desc list */ - dma_tx_desc = desc->tx_desc_list_head + i; - - /* set second address chained bit */ - dma_tx_desc->tdes0_bm.tch = 1; - - /* set buffer 1 address pointer */ - dma_tx_desc->tdes2_bm.buffer1 = (uint32_t)(&((uint8_t *)desc->tx_buff_cfg.buffer)[i * desc->tx_buff_cfg.size]); - - /* link all Tx descriptors */ - if (i < desc->tx_buff_cfg.count - 1) { - /* set next descriptor address register with the next descriptor base address */ - dma_tx_desc->tdes3_bm.next_desc = (uint32_t)(desc->tx_desc_list_head + i + 1); - } else { - /* for last descriptor, set next descriptor address register equal to the first descriptor base address */ - dma_tx_desc->tdes3_bm.next_desc = (uint32_t)desc->tx_desc_list_head; - } - } - - /* set transmit descriptor list address register */ - ptr->DMA_TX_DESC_LIST_ADDR = (uint32_t)desc->tx_desc_list_head; -} - -void enet_dma_rx_desc_chain_init(ENET_Type *ptr, enet_desc_t *desc) -{ - uint32_t i = 0; - enet_rx_desc_t *dma_rx_desc; - - /* set the rx_desc_list_cur pointer with the first one of the dma_rx_desc_tab list */ - desc->rx_desc_list_cur = desc->rx_desc_list_head; - /* fill each dma_rx_desc descriptor with the right values */ - for (i = 0; i < desc->rx_buff_cfg.count; i++) { - /* get the pointer on the ith member of the Rx desc list */ - dma_rx_desc = desc->rx_desc_list_head + i; - /* set own bit of the rx descriptor status */ - dma_rx_desc->rdes0_bm.own = 1; - - /* set buffer 1 size and second address chained bit */ - dma_rx_desc->rdes1_bm.rch = 1; - dma_rx_desc->rdes1_bm.rbs1 = desc->rx_buff_cfg.size; - - /* set buffer 1 address pointer */ - dma_rx_desc->rdes2_bm.buffer1 = (uint32_t)(&((uint8_t *)desc->rx_buff_cfg.buffer)[i * desc->rx_buff_cfg.size]); - - /* link all Rx descriptors */ - if (i < desc->rx_buff_cfg.count - 1) { - /* set next descriptor address register with next descriptor base address */ - dma_rx_desc->rdes3_bm.next_desc = (uint32_t)(desc->rx_desc_list_head + i + 1); - } else { - /* for last descriptor, set next descriptor address register equal to the first descriptor base address */ - dma_rx_desc->rdes3_bm.next_desc = (uint32_t)desc->rx_desc_list_head; - } - } - /* set receive descriptor list address register */ - ptr->DMA_RX_DESC_LIST_ADDR = (uint32_t)desc->rx_desc_list_head; -} - -void enet_timestamp_enable(ENET_Type *ptr, bool enable) -{ - /* enable the timestamp */ - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSENA_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSENA_SET(enable); -} - -void enet_set_subsecond_increment(ENET_Type *ptr, uint8_t ssinc) -{ - ptr->SUB_SEC_INCR &= ~ENET_SUB_SEC_INCR_SSINC_MASK; - ptr->SUB_SEC_INCR |= ENET_SUB_SEC_INCR_SSINC_SET(ssinc); -} - -void enet_set_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_update_t *timestamp) -{ - ptr->SYST_SEC_UPD = timestamp->sec; - ptr->SYST_NSEC_UPD = timestamp->nsec; - ptr->TS_CTRL |= ENET_TS_CTRL_TSINIT_MASK; - - while (ENET_TS_CTRL_TSINIT_GET(ptr->TS_CTRL) == 1) { - - } -} - -void enet_get_ptp_timestamp(ENET_Type *ptr, enet_ptp_ts_system_t *timestamp) -{ - timestamp->sec = ptr->SYST_SEC; - timestamp->nsec = ptr->SYST_NSEC; -} - -void enet_update_ptp_timeoffset(ENET_Type *ptr, enet_ptp_ts_update_t *timeoffset) -{ - /* write the offset (positive or negative ) in the timestamp update high and low registers */ - ptr->SYST_SEC_UPD = ENET_SYST_SEC_UPD_TSS_SET(timeoffset->sec); - ptr->SYST_NSEC_UPD = ENET_SYST_NSEC_UPD_ADDSUB_SET(timeoffset->sign) | ENET_SYST_NSEC_UPD_TSSS_SET(timeoffset->nsec); - - /* update the timestamp */ - ptr->TS_CTRL |= ENET_TS_CTRL_TSUPDT_MASK; - - /* wait for the updating to finish */ - while (ENET_TS_CTRL_TSUPDT_GET(ptr->TS_CTRL)) { - - } -} - -void enet_adjust_ptp_time_freq(ENET_Type *ptr, int32_t adj) -{ - ptr->TS_ADDEND = (uint32_t)((int64_t)adj * ENET_ADJ_FREQ_BASE_ADDEND / (ENET_ONE_SEC_IN_NANOSEC - adj) + ENET_ADJ_FREQ_BASE_ADDEND); - - ptr->TS_CTRL |= ENET_TS_CTRL_TSADDREG_MASK; - - while (ENET_TS_CTRL_TSADDREG_GET(ptr->TS_CTRL)) { - - } -} - -void enet_set_ptp_version(ENET_Type *ptr, enet_ptp_version_t ptp_ver) -{ - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSVER2ENA_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSVER2ENA_SET(ptp_ver); -} - -hpm_stat_t enet_enable_ptp_frame_type(ENET_Type *ptr, enet_ptp_frame_type_t ptp_frame_type, bool enable) -{ - hpm_stat_t stat = status_success; - - if (ptp_frame_type == enet_ptp_frame_ipv4) { - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSIPV4ENA_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSIPV4ENA_SET(enable); - } else if (ptp_frame_type == enet_ptp_frame_ipv6) { - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSIPV6ENA_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSIPV6ENA_SET(enable); - } else if (ptp_frame_type == enet_ptp_frame_ethernet) { - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSIPENA_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSIPENA_SET(enable); - } else { - return status_invalid_argument; - } - - return stat; -} - -void enet_set_snapshot_ptp_message_type(ENET_Type *ptr, enet_ts_ss_ptp_msg_t ts_ss_ptp_msg) -{ - /* set ptp message type for snapshots */ - ptr->TS_CTRL &= ~ENET_TS_CTRL_SNAPTYPSEL_MASK; - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSMSTRENA_MASK; - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSEVNTENA_MASK; - ptr->TS_CTRL |= ts_ss_ptp_msg << ENET_TS_CTRL_TSEVNTENA_SHIFT; -} - -void enet_init_ptp(ENET_Type *ptr, enet_ptp_config_t *config) -{ - enet_mask_interrupt_event(ptr, ENET_INTR_STATUS_TSIS_MASK); - - /* select the resolution of nanosecond */ - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSCTRLSSR_MASK; - ptr->TS_CTRL |= ENET_TS_CTRL_TSCTRLSSR_SET(config->timestamp_rollover_mode); - - /* enable timestamping */ - ptr->TS_CTRL |= ENET_TS_CTRL_TSENALL_MASK | ENET_TS_CTRL_TSENA_MASK; - - /* set sub-second increment */ - ptr->SUB_SEC_INCR &= ~ENET_SUB_SEC_INCR_SSINC_MASK; - ptr->SUB_SEC_INCR |= ENET_SUB_SEC_INCR_SSINC_SET(config->ssinc); - - if (config->update_method == enet_ptp_time_fine_update) { - /* set the addend */ - ptr->TS_ADDEND = config->addend; - - /* update the addend */ - ptr->TS_CTRL |= ENET_TS_CTRL_TSADDREG_MASK; - - /* poll the status of updating the addend */ - while (ENET_TS_CTRL_TSADDREG_GET(ptr->TS_CTRL)) { - - } - - /* fine update */ - ptr->TS_CTRL |= ENET_TS_CTRL_TSCFUPDT_MASK; - } else { - /* coarse update */ - ptr->TS_CTRL &= ~ENET_TS_CTRL_TSCFUPDT_MASK; - } -} - -void enet_set_pps0_control_output(ENET_Type *ptr, enet_pps_ctrl_t freq) -{ - ptr->PPS_CTRL &= ~ENET_PPS_CTRL_PPSEN0_MASK; - ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSCTRLCMD0_SET(freq); -} - -hpm_stat_t enet_set_ppsx_command(ENET_Type *ptr, enet_pps_cmd_t cmd, enet_pps_idx_t idx) -{ - if (idx >= ENET_SOC_PPS_MAX_COUNT) { - return status_invalid_argument; - } - - /* Wait the last command to complete */ - while (ptr->PPS_CTRL & (ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC))) { - - } - - /* Set the specified pps output with a specified command */ - ptr->PPS_CTRL |= cmd << ((idx + 1) << ENET_PPS_CMD_OFS_FAC); - - return status_success; -} - -hpm_stat_t enet_set_ppsx_config(ENET_Type *ptr, enet_pps_cmd_config_t *cmd_cfg, enet_pps_idx_t idx) -{ - if (idx >= ENET_SOC_PPS_MAX_COUNT) { - return status_invalid_argument; - } - - /* Set the interval and width for PPSx */ - if (idx == enet_pps_0) { - ptr->PPS0_INTERVAL = cmd_cfg->pps_interval - 1; - ptr->PPS0_WIDTH = cmd_cfg->pps_width - 1; - } else { - ptr->PPS[idx].INTERVAL = cmd_cfg->pps_interval - 1; - ptr->PPS[idx].WIDTH = cmd_cfg->pps_width - 1; - } - - /* Set the target timestamp */ - if (idx == enet_pps_0) { - ptr->TGTTM_SEC = cmd_cfg->target_sec; - ptr->TGTTM_NSEC = cmd_cfg->target_nsec; - } else { - ptr->PPS[idx].TGTTM_SEC = cmd_cfg->target_sec; - ptr->PPS[idx].TGTTM_NSEC = cmd_cfg->target_nsec; - } - - /* Set PPS0 as the command function */ - if (idx == enet_pps_0) { - ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN0_MASK; - } - -#if ENET_SOC_PPS1_EN - if (idx == enet_pps_1) { - ptr->PPS_CTRL |= ENET_PPS_CTRL_PPSEN1_MASK; - } -#endif - - /* Wait the last command to complete */ - while (ptr->PPS_CTRL & (ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC))) { - - } - - /* Initialize with the No Command */ - ptr->PPS_CTRL &= ~(ENET_PPS_CMD_MASK << ((idx + 1) << ENET_PPS_CMD_OFS_FAC)); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c deleted file mode 100644 index b0a943d55c7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_esc_drv.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_esc_drv.h" - -#ifndef HPM_ESC_DRV_DEFAULT_RETRY_COUNT -#define HPM_ESC_DRV_DEFAULT_RETRY_COUNT (0xA0000000U) -#endif - -hpm_stat_t esc_mdio_read(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) -{ - uint32_t retry; - - ptr->MIIM_PDI_ACC_STAT = 1; /* PDI access MII management interface */ - - /* wait for MII idle */ - retry = 0; - while ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_BUSY_MASK) != 0) { - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* set PHY address and register address */ - ptr->PHY_ADDR = phy_addr; - ptr->PHY_REG_ADDR = reg_addr; - - /* read command */ - ptr->MII_MNG_CS = (ptr->MII_MNG_CS & ~ESC_MII_MNG_CS_CMD_MASK) | ESC_MII_MNG_CS_CMD_SET(1); - - /* wait command done */ - retry = 0; - while ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_BUSY_MASK) != 0) { - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* check error status */ - if ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_CMD_ERR_MASK) != 0) { - return status_fail; - } - - /* check error status */ - if ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_CMD_ERR_MASK) != 0) { - return status_fail; - } - - *data = ptr->PHY_DATA; - - return status_success; -} - -hpm_stat_t esc_mdio_write(ESC_Type *ptr, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) -{ - uint32_t retry; - - ptr->MIIM_PDI_ACC_STAT = 1; /* PDI access MII management interface */ - - /* wait for MII idle */ - retry = 0; - while ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_BUSY_MASK) != 0) { - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - - /* set PHY address, register address and register value */ - ptr->PHY_ADDR = phy_addr; - ptr->PHY_REG_ADDR = reg_addr; - ptr->PHY_DATA = data; - - /* write command */ - ptr->MII_MNG_CS = (ptr->MII_MNG_CS & ~ESC_MII_MNG_CS_CMD_MASK) | ESC_MII_MNG_CS_WEN_MASK | ESC_MII_MNG_CS_CMD_SET(2); - - /* wait command done */ - retry = 0; - while ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_BUSY_MASK) != 0) { - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* check error status */ - if ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_CMD_ERR_MASK) != 0) { - return status_fail; - } - - /* check error status */ - if ((ptr->MII_MNG_CS & ESC_MII_MNG_CS_CMD_ERR_MASK) != 0) { - return status_fail; - } - - return status_success; -} - -/* Loding ESC EEPROM, EtherCAT communication is possible even if the EEPROM is blank */ -hpm_stat_t esc_check_eeprom_loading(ESC_Type *ptr) -{ - hpm_stat_t stat = status_success; - uint32_t retry = 0; - - while (1) { - /* 0x110 bit0 eeprom load correctly */ - if ((ptr->ESC_DL_STAT & ESC_ESC_DL_STAT_EPLC_MASK) == ESC_ESC_DL_STAT_EPLC_MASK) { - stat = status_success; /* Loading successful, PDI operations */ - break; - } - - /* 0x502 bit13 ack or cmd error */ - if ((ptr->EEPROM_CTRL_STAT & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) == ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) { /* ACMDERR = 1 */ - stat = status_esc_eeprom_ack_error; /* I2C bus error */ - break; - } else { - if ((ptr->EEPROM_CTRL_STAT & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) == ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) { /* ACMDERR,CKSUMERR = 01 */ - stat = status_esc_eeprom_checksum_error; /* EEPROM is loaded, but it is blank and cause checksum error */ - break; - } - } - - if (retry > HPM_ESC_DRV_DEFAULT_RETRY_COUNT) { - stat = status_timeout; - break; - } - retry++; - } - - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c deleted file mode 100644 index d18894f98db..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ewdg_drv.c +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_ewdg_drv.h" - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ -#define EWDG_CTRL_REG_PARITY_BIT_MASK (1UL << 31) /*!< Parity bit for Control Register */ - -#ifdef EWDG_SOC_CLK_DIV_VAL_MAX -#define EWDG_CTRL_DIV_VAL_MAX EWDG_SOC_CLK_DIV_VAL_MAX -#else -#define EWDG_CTRL_DIV_VAL_MAX (EWDG_CTRL0_DIV_VALUE_MASK >> EWDG_CTRL0_DIV_VALUE_SHIFT) -#endif -#define EWDG_CTRL_WIN_UPPER_MAX (EWDG_CTRL0_WIN_UPPER_MASK >> EWDG_CTRL0_WIN_UPPER_SHIFT) - -#define EWDG_CTRL_REG_UPDATE_PERIOD_DEFAULT (4UL) /* 512 Bus clock */ - -#define EWDG_RING_LEFT_SHIFT_1(val) (((uint16_t)(val) << 1) | ((uint16_t)(val) >> 15)) - -#define EWDG_REFRESH_PERIOD_DEFAULT (10000U) - -#define EWDG_INTERRUPT_TIMEOUT_TICKS_DEFAULT (0UL) -#define EWDG_RESET_TIMEOUT_TICKS_DEFAULT (65535UL) - -#if defined(EWDG_SOC_OVERTIME_REG_WIDTH) && (EWDG_SOC_OVERTIME_REG_WIDTH == 16) -#define EWDG_TIMEOUT_TICK_MAX (65535) -#else -#define EWDG_TIMEOUT_TICK_MAX (0xFFFFFFFFUL) -#endif - -/*********************************************************************************************************************** - * - * Prototypes - * - **********************************************************************************************************************/ -static bool ewdg_need_set_parity_bit(uint32_t reg_val); - -/*********************************************************************************************************************** - * - * Codes - * - **********************************************************************************************************************/ -static bool ewdg_need_set_parity_bit(uint32_t reg_val) -{ - uint32_t non_zero_bits = 0; - while (reg_val > 0) { - reg_val &= (reg_val - 1UL); - ++non_zero_bits; - } - return ((non_zero_bits & 1UL) != 0); -} - -void ewdg_get_default_config(EWDG_Type *ptr, ewdg_config_t *config) -{ - if ((ptr != NULL) && (config != NULL)) { - - (void) memset(config, 0, sizeof(ewdg_config_t)); - - config->ctrl_config.cnt_clk_sel = ewdg_cnt_clk_src_ext_osc_clk; - config->ctrl_config.use_lowlevel_timeout = true; - - config->ctrl_config.refresh_unlock_method = ewdg_refresh_unlock_method_password; - config->ctrl_config.enable_overtime_self_clear = false; - - config->ctrl_config.timeout_interrupt_val = EWDG_INTERRUPT_TIMEOUT_TICKS_DEFAULT; - config->ctrl_config.timeout_reset_val = EWDG_RESET_TIMEOUT_TICKS_DEFAULT; - config->ctrl_config.clock_div_by_power_of_2 = 0; - - config->ctrl_config.refresh_unlock_password = EWDG_REFRESH_UNLOCK_PASSWORD_DEFAULT; - config->ctrl_config.ctrl_reg_update_password = EWDG_UPDATE_PASSWORD_DEFAULT; - config->ctrl_config.ctrl_reg_update_period_bus_clk_x_128 = EWDG_CTRL_REG_UPDATE_PERIOD_DEFAULT; - - config->ctrl_config.low_power_mode = ewdg_low_power_mode_work_clock_normal; - - config->ctrl_config.refresh_period_in_bus_cycles = EWDG_REFRESH_PERIOD_DEFAULT; - } -} - -hpm_stat_t ewdg_init_ctrl_func(EWDG_Type *ptr, ewdg_func_ctrl_config_t *config, uint32_t cnt_src_freq) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (config == NULL) || (cnt_src_freq == 0)) { - break; - } - if (config->window_lower_limit > ewdg_window_lower_timeout_period_max) { - break; - } - if (config->window_upper_limit > ewdg_window_upper_timeout_period_max) { - break; - } - if (config->refresh_unlock_method > ewdg_refresh_unlock_method_max) { - break; - } - - uint32_t ctrl0 = 0; - - uint32_t ot_int_ticks; - uint32_t ot_reset_ticks; - uint32_t clock_div_by_pwr_2 = 0; - if (!config->use_lowlevel_timeout) { - uint64_t timeout_interrupt_ticks = ewdg_convert_timeout_us_to_timeout_ticks(config->timeout_interrupt_us, - cnt_src_freq); - uint64_t timeout_reset_ticks = ewdg_convert_timeout_us_to_timeout_ticks(config->timeout_reset_us, - cnt_src_freq); - clock_div_by_pwr_2 = 0; - while ((timeout_interrupt_ticks > EWDG_TIMEOUT_TICK_MAX) || (timeout_reset_ticks > EWDG_TIMEOUT_TICK_MAX)) { - ++clock_div_by_pwr_2; - timeout_interrupt_ticks >>= 1; - timeout_reset_ticks >>= 1; - } - if (clock_div_by_pwr_2 > EWDG_SOC_CLK_DIV_VAL_MAX) { - status = status_ewdg_div_out_of_range; - /* Cannot get the expected EWDG setting via the specified timeout input */ - break; - } - ot_int_ticks = (uint32_t) (timeout_interrupt_ticks & 0xFFFFFFFFUL); - ot_reset_ticks = (uint32_t) (timeout_reset_ticks & 0xFFFFFFFFUL); - - } else { - clock_div_by_pwr_2 = config->clock_div_by_power_of_2; - ot_int_ticks = config->timeout_interrupt_val; - ot_reset_ticks = config->timeout_reset_val; - - if (clock_div_by_pwr_2 > EWDG_SOC_CLK_DIV_VAL_MAX) { - status = status_ewdg_div_out_of_range; - /* Cannot get the expected EWDG setting via the specified timeout input */ - break; - } - if ((ot_int_ticks > EWDG_TIMEOUT_TICK_MAX) || (ot_reset_ticks > EWDG_TIMEOUT_TICK_MAX)) { - status = status_ewdg_tick_out_of_range; - break; - } - } - - if (config->cnt_clk_sel == ewdg_cnt_clk_src_ext_osc_clk) { - ctrl0 |= EWDG_CTRL0_CLK_SEL_MASK; - } - ctrl0 |= EWDG_CTRL0_DIV_VALUE_SET(clock_div_by_pwr_2); - if (config->enable_window_mode) { - ctrl0 |= EWDG_CTRL0_WIN_EN_MASK; - - ctrl0 |= EWDG_CTRL0_WIN_LOWER_SET(config->window_lower_limit); - ctrl0 |= EWDG_CTRL0_WIN_UPPER_SET(config->window_upper_limit); - } - - if (config->enable_config_lock) { - ctrl0 |= EWDG_CTRL0_CFG_LOCK_MASK; - } - - if (config->enable_refresh_period) { - ctrl0 |= EWDG_CTRL0_REF_OT_REQ_MASK; - } - if (config->enable_refresh_lock) { - ctrl0 |= EWDG_CTRL0_REF_LOCK_MASK; - } - ctrl0 |= EWDG_CTRL0_REF_UNLOCK_MEC_SET(config->refresh_unlock_method); - - if (config->enable_overtime_self_clear) { - ctrl0 |= EWDG_CTRL0_OT_SELF_CLEAR_MASK; - } - if (config->keep_running_in_debug_mode) { - ctrl0 |= EWDG_CTRL0_EN_DBG_MASK; - } - ctrl0 |= EWDG_CTRL0_EN_LP_SET(config->low_power_mode); - - /* Set Parity bit if necessary */ - if (ewdg_need_set_parity_bit(ctrl0)) { - ctrl0 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL0 = ctrl0; - - ptr->CFG_PROT = EWDG_CFG_PROT_UPD_OT_TIME_SET(config->ctrl_reg_update_period_bus_clk_x_128) | - EWDG_CFG_PROT_UPD_PSD_SET(config->ctrl_reg_update_password); - - ptr->REF_TIME = config->refresh_period_in_bus_cycles; - ptr->REF_PROT = EWDG_REF_PROT_REF_UNL_PSD_SET(config->refresh_unlock_password); - - -#if !defined(EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT) || (EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT == 1) - ptr->OT_INT_VAL = ot_int_ticks; -#endif - ptr->OT_RST_VAL = ot_reset_ticks; - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t ewdg_init_interrupt_reset(EWDG_Type *ptr, ewdg_interrupt_reset_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (config == NULL)) { - break; - } - - uint32_t ctrl1 = 0; - if (config->enable_ctrl_parity_fail_reset) { - ctrl1 |= EWDG_RST_PARITY_FAIL; - } - if (config->enable_ctrl_unlock_fail_reset) { - ctrl1 |= EWDG_RST_CTRL_REG_UNLOCK_FAIL; - } - if (config->enable_refresh_unlock_fail_reset) { - ctrl1 |= EWDG_RST_REFRESH_UNLOCK_FAIL; - } - if (config->enable_ctrl_update_violation_reset) { - ctrl1 |= EWDG_RST_CTRL_REG_UPDATE_FAIL; - } - if (config->enable_timeout_reset) { - ctrl1 |= EWDG_RST_TIMEOUT; - } - if (config->enable_refresh_violation_reset) { - ctrl1 |= EWDG_RST_REFRESH_VIOLATION; - } - -#if defined(EWDG_SOC_SUPPORT_INTERRUPT) && (EWDG_SOC_SUPPORT_INTERRUPT == 0) - if (config->enable_timeout_interrupt) { - status = status_ewdg_feature_unsupported; - break; - } -#else - if (config->enable_timeout_interrupt) { - ctrl1 |= EWDG_INT_TIMEOUT; - } -#endif - if (config->enable_ctrl_parity_fail_interrupt) { - ctrl1 |= EWDG_INT_PARITY_FAIL; - } - if (config->enable_ctrl_unlock_fail_interrupt) { - ctrl1 |= EWDG_INT_CTRL_REG_UNLOCK_FAIL; - } - if (config->enable_refresh_unlock_fail_interrupt) { - ctrl1 |= EWDG_INT_REFRESH_UNLOCK_FAIL; - } - if (config->enable_ctrl_update_violation_interrupt) { - ctrl1 |= EWDG_INT_CTRL_REG_UPDATE_FAIL; - } - if (config->enable_refresh_violation_interrupt) { - ctrl1 |= EWDG_INT_REFRESH_VIOLATION; - } - - /* Set Parity bit if necessary */ - if (ewdg_need_set_parity_bit(ctrl1)) { - ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL1 = ctrl1; - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t ewdg_init(EWDG_Type *ptr, ewdg_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (config == NULL)) { - break; - } - - status = ewdg_init_ctrl_func(ptr, &config->ctrl_config, config->cnt_src_freq); - if (status != status_success) { - break; - } - status = ewdg_init_interrupt_reset(ptr, &config->int_rst_config); - if (status != status_success) { - break; - } - - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->WDT_EN = (config->enable_watchdog) ? 1UL : 0UL; - - } while (false); - - return status; -} - -hpm_stat_t ewdg_unlock_refresh(EWDG_Type *ptr) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if (ptr == NULL) { - break; - } - - if (!ewdg_is_refresh_locked(ptr)) { - status = status_success; - break; - } - - ewdg_refresh_unlock_method_t unlock_method = ewdg_get_refresh_unlock_method(ptr); - uint32_t unlock_password; - uint32_t reg_unlock_password = EWDG_REF_PROT_REF_UNL_PSD_GET(ptr->REF_PROT); - if (unlock_method == ewdg_refresh_unlock_method_password) { - unlock_password = reg_unlock_password; - } else if (unlock_method == ewdg_refresh_unlock_method_fixed_key) { - unlock_password = EWDG_REFRESH_UNLOCK_FIXED_KEY; - } else if (unlock_method == ewdg_refresh_unlock_method_ring_left_shift_password_by_1) { - unlock_password = EWDG_RING_LEFT_SHIFT_1(reg_unlock_password); - } else if (unlock_method == ewdg_refresh_unlock_method_ring_left_shift_password_by_1_bit0_xor_password_bit0) { - uint16_t high_15 = (reg_unlock_password << 1) & 0xFFFFU; - uint16_t low_0 = reg_unlock_password >> 15; - low_0 ^= reg_unlock_password; - unlock_password = high_15 | (low_0 & 0x1UL); - } else { - /* Should never reach this branch */ - break; - } - - ptr->REF_PROT = unlock_password; - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t ewdg_refresh(EWDG_Type *ptr) -{ - hpm_stat_t status = ewdg_unlock_refresh(ptr); - if (status == status_success) { - ewdg_write_refresh_reg(ptr); - } - return status; -} - -uint32_t ewdg_get_count_clock_freq(EWDG_Type *ptr, uint32_t src_clk_freq) -{ - uint32_t divided_freq = 0; - if (ptr != NULL) { - uint32_t divider = ewdg_get_count_clk_divider(ptr); - divided_freq = src_clk_freq / divider; - } - return divided_freq; -} - -uint64_t ewdg_convert_timeout_us_to_timeout_ticks(uint32_t src_clk_freq, uint32_t timeout_us) -{ - uint64_t timeout_ticks = 0; - if (src_clk_freq != 0U) { - uint32_t ns_per_tick = 1000000000UL / src_clk_freq; - uint64_t timeout_ns = (uint64_t) timeout_us * 1000UL; - timeout_ticks = (timeout_ns + ns_per_tick - 1U) / ns_per_tick; - } - return timeout_ticks; -} - -uint32_t ewdg_convert_timeout_ticks_to_timeout_us(EWDG_Type *ptr, uint32_t src_clk_freq, uint32_t timeout_ticks) -{ - uint32_t timeout_us; - if (src_clk_freq == 0U) { - timeout_us = 0; - } else { - uint32_t actual_clk_freq = src_clk_freq / ewdg_get_count_clk_divider(ptr); - uint32_t ns_per_tick = 1000000000UL / actual_clk_freq; - uint64_t timeout_ns = (uint64_t) timeout_ticks * ns_per_tick; - timeout_us = timeout_ns / 1000UL; - } - return timeout_us; -} - -void ewdg_enable_interrupt(EWDG_Type *ptr, uint32_t mask) -{ - uint32_t interrupt_mask = mask & EWDG_INT_ALL; - if (ptr != NULL) { - uint32_t ctrl1 = ptr->CTRL1 | interrupt_mask; - /* Set Parity bit if necessary */ - if (ewdg_need_set_parity_bit(ctrl1)) { - ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL1 = ctrl1; - } -} - -void ewdg_disable_interrupt(EWDG_Type *ptr, uint32_t mask) -{ - uint32_t interrupt_mask = mask & EWDG_INT_ALL; - if (ptr != NULL) { - uint32_t ctrl1 = ptr->CTRL1 & ~interrupt_mask; - /* Set Parity bit if necessary */ - if (ewdg_need_set_parity_bit(ctrl1)) { - ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL1 = ctrl1; - } -} - -void ewdg_enable_reset(EWDG_Type *ptr, uint32_t mask) -{ - uint32_t reset_mask = mask & EWDG_RST_ALL; - if (ptr != NULL) { - uint32_t ctrl1 = ptr->CTRL1 | reset_mask; - /* Set Parity bit if necessary */ - if (ewdg_need_set_parity_bit(ctrl1)) { - ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL1 = ctrl1; - } -} - -void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask) -{ - uint32_t reset_mask = mask & EWDG_RST_ALL; - if (ptr != NULL) { - uint32_t ctrl1 = ptr->CTRL1 & ~reset_mask; - /* Set Parity bit if necessary */ - if (ewdg_need_set_parity_bit(ctrl1)) { - ctrl1 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL1 = ctrl1; - } -} - -void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel) -{ - if (ptr != NULL) { - uint32_t ctrl0 = ptr->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK; - /* Set Parity bit if necessary */ - if (clk_sel == ewdg_cnt_clk_src_ext_osc_clk) { - ctrl0 |= EWDG_CTRL0_CLK_SEL_MASK; - } - if (ewdg_need_set_parity_bit(ctrl0)) { - ctrl0 |= EWDG_CTRL_REG_PARITY_BIT_MASK; - } - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->CTRL0 = ctrl0; - } -} - -void ewdg_enable(EWDG_Type *ptr) -{ - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->WDT_EN = 1; -} - -void ewdg_disable(EWDG_Type *ptr) -{ - if (ewdg_is_ctrl_reg_locked(ptr)) { - ewdg_unlock_ctrl_regs(ptr); - } - ptr->WDT_EN = 0; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c deleted file mode 100644 index fc0631870bf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_femc_drv.c +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_femc_drv.h" - -#ifndef HPM_FEMC_DRV_DEFAULT_PRESCALER -#define HPM_FEMC_DRV_DEFAULT_PRESCALER (0x3UL) -#endif - -#ifndef HPM_FEMC_DRV_RETRY_COUNT -#define HPM_FEMC_DRV_RETRY_COUNT (5000U) -#endif - -#define FEMC_PRESCALER_MAX (256UL) - -static void femc_config_delay_cell(FEMC_Type *ptr, bool delay_cell_en, uint32_t delay_cell_value) -{ - ptr->DLYCFG &= ~FEMC_DLYCFG_OE_MASK; - ptr->DLYCFG = FEMC_DLYCFG_DLYSEL_SET(delay_cell_value) | FEMC_DLYCFG_DLYEN_SET(delay_cell_en); - ptr->DLYCFG |= FEMC_DLYCFG_OE_MASK; -} - -static hpm_stat_t femc_ip_cmd_done(FEMC_Type *ptr) -{ - uint32_t intr_status = 0; - uint32_t retry = 0; - do { - if (retry > HPM_FEMC_DRV_RETRY_COUNT) { - break; - } - retry++; - intr_status = ptr->INTR - & (uint32_t)(FEMC_INTR_IPCMDDONE_MASK | FEMC_INTR_IPCMDERR_MASK); - } while (intr_status == 0); - - if (retry > HPM_FEMC_DRV_RETRY_COUNT) { - return status_timeout; - } - - ptr->INTR |= FEMC_INTR_IPCMDDONE_MASK | FEMC_INTR_IPCMDERR_MASK; - if (intr_status & FEMC_INTR_IPCMDERR_MASK) { - return status_femc_cmd_err; - } - return status_success; -} - -static uint32_t femc_make_cmd(uint32_t opcode) -{ - return (opcode & ~FEMC_CMD_WRITE_FLAG) | FEMC_CMD_KEY; -} - -static bool femc_is_write_cmd(uint32_t opcode) -{ - return ((opcode & FEMC_CMD_WRITE_FLAG) == FEMC_CMD_WRITE_FLAG); -} - -uint32_t femc_issue_ip_cmd(FEMC_Type *ptr, uint32_t base_address, femc_cmd_t *cmd) -{ - bool read_data = !femc_is_write_cmd(cmd->opcode); - ptr->SADDR = base_address; - if (!read_data) { - ptr->IPTX = cmd->data; - } - ptr->IPCMD = femc_make_cmd(cmd->opcode); - - if (femc_ip_cmd_done(ptr) != status_success) { - return status_femc_cmd_err; - } - - if (read_data) { - cmd->data = ptr->IPRX; - } - return status_success; -} - -void femc_default_config(FEMC_Type *ptr, femc_config_t *config) -{ - (void) ptr; - femc_axi_q_weight_t *q; - config->dqs = FEMC_DQS_FROM_PAD; - config->cmd_timeout = 0; - config->bus_timeout = 0x10; - q = &config->axi_q_weight[FEMC_AXI_Q_A]; - q->enable = true; - q->qos = 4; - q->age = 2; - q->slave_hit = 0x5; - q->slave_hit_wo_rw = 0x3; - - q = &config->axi_q_weight[FEMC_AXI_Q_B]; - q->enable = true; - q->qos = 4; - q->age = 2; - q->page_hit = 0x5; - q->slave_hit_wo_rw = 0x3; - q->bank_rotation = 0x6; -} - -void femc_get_typical_sdram_config(FEMC_Type *ptr, femc_sdram_config_t *config) -{ - (void) ptr; - config->col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS; - config->cas_latency = FEMC_SDRAM_CAS_LATENCY_3; - config->bank_num = FEMC_SDRAM_BANK_NUM_4; - config->prescaler = HPM_FEMC_DRV_DEFAULT_PRESCALER; - config->burst_len_in_byte = 8; - config->auto_refresh_count_in_one_burst = 1; - config->precharge_to_act_in_ns = 18; - config->act_to_rw_in_ns = 18; - config->refresh_recover_in_ns = 60; - config->write_recover_in_ns = 12; - config->cke_off_in_ns = 42; - config->act_to_precharge_in_ns = 42; - - config->self_refresh_recover_in_ns = 72; - config->refresh_to_refresh_in_ns = 60; - config->act_to_act_in_ns = 12; - config->idle_timeout_in_ns = 6; - config->cs_mux_pin = FEMC_IO_MUX_NOT_USED; - - config->cmd_data_width = 4; -} - -void femc_init(FEMC_Type *ptr, femc_config_t *config) -{ - uint32_t i; - femc_axi_q_weight_t *q; - for (i = 0; i < FEMC_BR_COUNT; i++) { - ptr->BR[i] = 0; - } - - femc_sw_reset(ptr); - femc_disable(ptr); - ptr->CTRL |= FEMC_CTRL_BTO_SET(config->bus_timeout) - | FEMC_CTRL_CTO_SET(config->cmd_timeout) - | FEMC_CTRL_DQS_SET(config->dqs); - - q = &config->axi_q_weight[FEMC_AXI_Q_A]; - if (q->enable) { - ptr->BMW0 = FEMC_BMW0_QOS_SET(q->qos) - | FEMC_BMW0_AGE_SET(q->age) - | FEMC_BMW0_SH_SET(q->slave_hit) - | FEMC_BMW0_RWS_SET(q->slave_hit_wo_rw); - } else { - ptr->BMW0 = 0; - } - - q = &config->axi_q_weight[FEMC_AXI_Q_B]; - if (q->enable) { - ptr->BMW1 = FEMC_BMW1_QOS_SET(q->qos) - | FEMC_BMW1_AGE_SET(q->age) - | FEMC_BMW1_PH_SET(q->page_hit) - | FEMC_BMW1_BR_SET(q->bank_rotation) - | FEMC_BMW1_RWS_SET(q->slave_hit_wo_rw); - } else { - ptr->BMW1 = 0; - } - - femc_enable(ptr); -} - -static uint8_t femc_convert_actual_size_to_memory_size(uint32_t size_in_kb) -{ - uint8_t size = 0; - if (size_in_kb == 4) { - return 0; - } - - if (size_in_kb > 2 * 1 << 20) { - return 0x1F; - } - - size = 1; - size_in_kb >>= 3; - while (size_in_kb > 1) { - size_in_kb >>= 1; - size++; - } - return size; -} - -static uint8_t femc_convert_burst_len(uint8_t burst_len_in_byte) -{ - if ((burst_len_in_byte == 0) - || (burst_len_in_byte > FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE)) { - return FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; - } - - switch (burst_len_in_byte) { - case 1: - case 2: - case 4: - return burst_len_in_byte >> 1; - case 8: - return (burst_len_in_byte - 1) >> 1; - default: - return FEMC_SDRAM_MAX_BURST_LENGTH_IN_BYTE + 1; - } -} - -static uint32_t ns2cycle(uint32_t freq_in_hz, uint32_t ns, uint32_t max_cycle) -{ - uint32_t ns_per_cycle; - uint32_t cycle; - - ns_per_cycle = 1000000000 / freq_in_hz; - cycle = ns / ns_per_cycle; - if (cycle > max_cycle) { - cycle = max_cycle; - } - return cycle; -} - -hpm_stat_t femc_config_sdram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sdram_config_t *config) -{ - hpm_stat_t err; - uint32_t prescaler; - uint32_t refresh_cycle; - uint32_t clk_in_khz = clk_in_hz / 1000; - femc_cmd_t cmd = {0}; - uint8_t size = femc_convert_actual_size_to_memory_size(config->size_in_byte >> 10); - uint8_t burst_len = femc_convert_burst_len(config->burst_len_in_byte); - - prescaler = ((config->prescaler == 0) ? FEMC_PRESCALER_MAX : config->prescaler); - refresh_cycle = clk_in_khz * config->refresh_in_ms / config->refresh_count / (prescaler << 4); - - if ((prescaler == 0) || (prescaler > FEMC_PRESCALER_MAX) - || (refresh_cycle == 0) || (refresh_cycle > FEMC_PRESCALER_MAX)) { - return status_invalid_argument; - } - - if (prescaler == FEMC_PRESCALER_MAX) { - prescaler = 0; - } - - if (refresh_cycle == FEMC_PRESCALER_MAX) { - refresh_cycle = 0; - } - - ptr->BR[config->cs] = FEMC_BR_BASE_SET(config->base_address >> FEMC_BR_BASE_SHIFT) - | FEMC_BR_SIZE_SET(size) | FEMC_BR_VLD_MASK; - - ptr->SDRCTRL0 = FEMC_SDRCTRL0_PORTSZ_SET(config->port_size) - | FEMC_SDRCTRL0_BURSTLEN_SET(burst_len) - | FEMC_SDRCTRL0_COL_SET(config->col_addr_bits) - | FEMC_SDRCTRL0_COL8_SET(config->col_addr_bits == FEMC_SDRAM_COLUMN_ADDR_8_BITS) - | FEMC_SDRCTRL0_CAS_SET(config->cas_latency) - | FEMC_SDRCTRL0_BANK2_SET(config->bank_num); - - ptr->SDRCTRL1 = FEMC_SDRCTRL1_PRE2ACT_SET(ns2cycle(clk_in_hz, config->precharge_to_act_in_ns, FEMC_SDRCTRL1_PRE2ACT_MASK >> FEMC_SDRCTRL1_PRE2ACT_SHIFT)) - | FEMC_SDRCTRL1_ACT2RW_SET(ns2cycle(clk_in_hz, config->act_to_rw_in_ns, FEMC_SDRCTRL1_ACT2RW_MASK >> FEMC_SDRCTRL1_ACT2RW_SHIFT)) - | FEMC_SDRCTRL1_RFRC_SET(ns2cycle(clk_in_hz, config->refresh_recover_in_ns, FEMC_SDRCTRL1_RFRC_MASK >> FEMC_SDRCTRL1_RFRC_SHIFT)) - | FEMC_SDRCTRL1_WRC_SET(ns2cycle(clk_in_hz, config->write_recover_in_ns, FEMC_SDRCTRL1_WRC_MASK >> FEMC_SDRCTRL1_WRC_SHIFT)) - | FEMC_SDRCTRL1_CKEOFF_SET(ns2cycle(clk_in_hz, config->cke_off_in_ns, FEMC_SDRCTRL1_CKEOFF_MASK >> FEMC_SDRCTRL1_CKEOFF_SHIFT)) - | FEMC_SDRCTRL1_ACT2PRE_SET(ns2cycle(clk_in_hz, config->act_to_precharge_in_ns, FEMC_SDRCTRL1_ACT2PRE_MASK >> FEMC_SDRCTRL1_ACT2PRE_SHIFT)); - - ptr->SDRCTRL2 = FEMC_SDRCTRL2_SRRC_SET(ns2cycle(clk_in_hz, config->self_refresh_recover_in_ns, FEMC_SDRCTRL2_SRRC_MASK >> FEMC_SDRCTRL2_SRRC_SHIFT)) - | FEMC_SDRCTRL2_REF2REF_SET(ns2cycle(clk_in_hz, config->refresh_to_refresh_in_ns, FEMC_SDRCTRL2_REF2REF_MASK >> FEMC_SDRCTRL2_REF2REF_SHIFT)) - | FEMC_SDRCTRL2_ACT2ACT_SET(ns2cycle(clk_in_hz, config->act_to_act_in_ns, FEMC_SDRCTRL2_ACT2ACT_MASK >> FEMC_SDRCTRL2_ACT2ACT_SHIFT)) - | FEMC_SDRCTRL2_ITO_SET(ns2cycle(clk_in_hz, config->idle_timeout_in_ns, FEMC_SDRCTRL2_ITO_MASK >> FEMC_SDRCTRL2_ITO_SHIFT)); - - ptr->SDRCTRL3 = FEMC_SDRCTRL3_PRESCALE_SET(prescaler) - | FEMC_SDRCTRL3_RT_SET(refresh_cycle) - | FEMC_SDRCTRL3_UT_SET(refresh_cycle) - | FEMC_SDRCTRL3_REBL_SET(config->auto_refresh_count_in_one_burst - 1); - - /* - * config delay cell - */ - femc_config_delay_cell(ptr, !config->delay_cell_disable, config->delay_cell_value); - - /* - * - * DATSZ[2:0]: Data size in byte - * 0b - 4 - * 1b - 1 - * 2b - 2 - * 3b - 3 - * > 3b - 4 - */ - ptr->DATSZ = FEMC_DATSZ_DATSZ_SET((config->cmd_data_width & (0x3UL))); - ptr->BYTEMSK = 0; - - cmd.opcode = FEMC_CMD_SDRAM_PRECHARGE_ALL; - cmd.data = 0; - err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - - cmd.opcode = FEMC_CMD_SDRAM_AUTO_REFRESH; - err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - - cmd.opcode = FEMC_CMD_SDRAM_MODE_SET; - /* FIXME: the mode register layout definition better to be passed in? */ - cmd.data = (uint32_t)(burst_len | config->cas_latency << 4); - err = femc_issue_ip_cmd(ptr, config->base_address, &cmd); - if (status_success != err) { - return err; - } - ptr->SDRCTRL3 |= FEMC_SDRCTRL3_REN_MASK; - - return status_success; -} - -void femc_get_typical_sram_config(FEMC_Type *ptr, femc_sram_config_t *config) -{ - (void) ptr; - config->base_address = 0x48000000; - config->size_in_byte = 4096; - config->address_mode = FEMC_SRAM_AD_NONMUX_MODE; - config->port_size = FEMC_SRAM_PORT_SIZE_8_BITS; - config->adv_hold_state = FEMC_SRAM_ADV_HOLD_LOW; - config->adv_polarity = FEMC_SRAM_ADV_ACTIVE_HIGH; - config->oeh_in_ns = 0; - config->oel_in_ns = 50; - config->weh_in_ns = 0; - config->wel_in_ns = 50; - config->ah_in_ns = 50; - config->as_in_ns = 0; - config->ceh_in_ns = 0; - config->ces_in_ns = 0; -} - -hpm_stat_t femc_config_sram(FEMC_Type *ptr, uint32_t clk_in_hz, femc_sram_config_t *config) -{ - uint8_t size = femc_convert_actual_size_to_memory_size(config->size_in_byte >> 10); - - ptr->IOCTRL = FEMC_IOCTRL_IO_CSX_SET(FEMC_IO_CSX_SRAM_CE); - - ptr->BR[FEMC_BR_BASE6] = FEMC_BR_BASE_SET(config->base_address >> FEMC_BR_BASE_SHIFT) - | FEMC_BR_SIZE_SET(size) - | FEMC_BR_VLD_MASK; - - ptr->SRCTRL0 = FEMC_SRCTRL0_ADVH_SET(config->adv_hold_state) - | FEMC_SRCTRL0_ADVP_SET(config->adv_polarity) - | FEMC_SRCTRL0_ADM_SET(config->address_mode) - | FEMC_SRCTRL0_PORTSZ_SET(config->port_size); - - ptr->SRCTRL1 = FEMC_SRCTRL1_OEH_SET(ns2cycle(clk_in_hz, config->oeh_in_ns, FEMC_SRCTRL1_OEH_MASK >> FEMC_SRCTRL1_OEH_SHIFT)) - | FEMC_SRCTRL1_OEL_SET(ns2cycle(clk_in_hz, config->oel_in_ns, FEMC_SRCTRL1_OEL_MASK >> FEMC_SRCTRL1_OEL_SHIFT)) - | FEMC_SRCTRL1_WEH_SET(ns2cycle(clk_in_hz, config->weh_in_ns, FEMC_SRCTRL1_WEH_MASK >> FEMC_SRCTRL1_WEH_SHIFT)) - | FEMC_SRCTRL1_WEL_SET(ns2cycle(clk_in_hz, config->wel_in_ns, FEMC_SRCTRL1_WEL_MASK >> FEMC_SRCTRL1_WEL_SHIFT)) - | FEMC_SRCTRL1_AH_SET(ns2cycle(clk_in_hz, config->ah_in_ns, FEMC_SRCTRL1_AH_MASK >> FEMC_SRCTRL1_AH_SHIFT)) - | FEMC_SRCTRL1_AS_SET(ns2cycle(clk_in_hz, config->as_in_ns, FEMC_SRCTRL1_AS_MASK >> FEMC_SRCTRL1_AS_SHIFT)) - | FEMC_SRCTRL1_CEH_SET(ns2cycle(clk_in_hz, config->ceh_in_ns, FEMC_SRCTRL1_CEH_MASK >> FEMC_SRCTRL1_CEH_SHIFT)) - | FEMC_SRCTRL1_CES_SET(ns2cycle(clk_in_hz, config->ces_in_ns, FEMC_SRCTRL1_CES_MASK >> FEMC_SRCTRL1_CES_SHIFT)); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c deleted file mode 100644 index 38f0e80fe2f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ffa_drv.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ffa_drv.h" -#include - -#define FFA_ERROR_MASKS (FFA_STATUS_FIR_OV_MASK | FFA_STATUS_FFT_OV_MASK | FFA_STATUS_WR_ERR_MASK | FFA_STATUS_RD_NXT_ERR_MASK | FFA_STATUS_RD_ERR_MASK) - -static bool is_point_num_valid(uint16_t num_point); -static uint32_t get_fft_misc_reg_fft_len(uint16_t num_point); -static hpm_stat_t get_fft_error_kind(uint32_t ffa_status); - -static bool is_point_num_valid(uint16_t num_point) -{ - return ((num_point & (num_point - 1U)) == 0U) && (num_point >= 8U); -} - -static uint32_t get_fft_misc_reg_fft_len(uint16_t num_point) -{ - uint32_t count = 0U; - num_point /= 8; - while (num_point > 0) { - count++; - num_point >>= 1U; - } - - return (count - 1U); -} - -void ffa_start_fft(FFA_Type *ptr, fft_xfer_t *fft_xfer) -{ - - assert((ptr != NULL) && (fft_xfer != NULL) && is_point_num_valid(fft_xfer->num_points)); - - ffa_disable(ptr); - - ffa_enable_interrupt(ptr, fft_xfer->interrupt_mask); - - ptr->OP_CTRL = FFA_OP_CTRL_EN_MASK; - - uint32_t op_cmd = FFA_OP_CMD_CMD_SET(FFA_OPCMD_FFT) | FFA_OP_CMD_IND_TYPE_SET(fft_xfer->src_data_type) | - FFA_OP_CMD_OUTD_TYPE_SET(fft_xfer->dst_data_type); - ptr->OP_CMD = op_cmd; - - uint32_t fft_len = get_fft_misc_reg_fft_len(fft_xfer->num_points); - uint32_t fft_misc = - FFA_OP_FFT_MISC_FFT_LEN_SET(fft_len) | FFA_OP_FFT_MISC_TMP_BLK_SET(1) | FFA_OP_FFT_MISC_IND_BLK_SET(0); - if (fft_xfer->is_ifft) { - fft_misc |= FFA_OP_FFT_MISC_IFFT_MASK; - } - ptr->OP_REG0 = fft_misc; - - ptr->OP_REG1 = 0; - ptr->OP_REG2 = (uint32_t) fft_xfer->src; - ptr->OP_REG4 = (uint32_t) fft_xfer->dst; - - ffa_enable(ptr); -} - -void ffa_start_fir(FFA_Type *ptr, fir_xfer_t *fir_xfer) -{ - assert((ptr != NULL) && (fir_xfer != NULL)); - - ffa_disable(ptr); - - ffa_enable_interrupt(ptr, fir_xfer->interrupt_mask); - - ptr->OP_CTRL = FFA_OP_CTRL_EN_MASK; - - uint32_t op_cmd = FFA_OP_CMD_CMD_SET(FFA_OPCMD_FIR) | FFA_OP_CMD_IND_TYPE_SET(fir_xfer->data_type) | - FFA_OP_CMD_OUTD_TYPE_SET(fir_xfer->data_type) | FFA_OP_CMD_COEF_TYPE_SET(fir_xfer->data_type); - ptr->OP_CMD = op_cmd; - - uint32_t fir_misc = FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(fir_xfer->coef_taps); - ptr->OP_REG0 = fir_misc; -#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32 - uint32_t fir_misc1 = FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(0) | FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(0) | - FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(1) | FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(fir_xfer->input_taps); -#else - uint32_t fir_misc1 = FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(0) | FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(1) | - FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(2) | FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(fir_xfer->input_taps); -#endif - - ptr->OP_REG1 = fir_misc1; - ptr->OP_REG2 = 0xFFFFFFFFUL; - ptr->OP_REG3 = (uint32_t) fir_xfer->src; - ptr->OP_REG4 = (uint32_t) fir_xfer->coeff; - ptr->OP_REG5 = (uint32_t) fir_xfer->dst; - - ffa_enable(ptr); -} - -static hpm_stat_t get_fft_error_kind(uint32_t ffa_status) -{ - hpm_stat_t status; - if (IS_HPM_BITMASK_SET(ffa_status, FFA_ERROR_MASKS)) { - if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_FIR_OV_MASK)) { - status = status_ffa_fir_overflow; - } else if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_FFT_OV_MASK)) { - status = status_ffa_fft_overflow; - } else if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_WR_ERR_MASK)) { - status = status_ffa_write_error; - } else if (IS_HPM_BITMASK_SET(ffa_status, FFA_STATUS_RD_NXT_ERR_MASK)) { - status = status_ffa_read_next_error; - } else { - status = status_ffa_read_error; - } - } else { - status = status_success; - } - return status; -} - -hpm_stat_t ffa_calculate_fft_blocking(FFA_Type *ptr, fft_xfer_t *fft_xfer) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF((ptr == NULL) || (fft_xfer == NULL) || !is_point_num_valid(fft_xfer->num_points)); - - fft_xfer->interrupt_mask = 0; - - ffa_start_fft(ptr, fft_xfer); - - while (!IS_HPM_BITMASK_SET(ptr->STATUS, FFA_STATUS_OP_CMD_DONE_MASK)) { - } - - uint32_t ffa_status = ptr->STATUS; - status = get_fft_error_kind(ffa_status); - } while (false); - - return status; -} - -hpm_stat_t ffa_calculate_fir_blocking(FFA_Type *ptr, fir_xfer_t *fir_xfer) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF((ptr == NULL) || (fir_xfer == NULL)); - - fir_xfer->interrupt_mask = 0; - - ffa_start_fir(ptr, fir_xfer); - - while (!IS_HPM_BITMASK_SET(ptr->STATUS, FFA_STATUS_OP_CMD_DONE_MASK)) { - } - - uint32_t ffa_status = ptr->STATUS; - status = get_fft_error_kind(ffa_status); - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c deleted file mode 100644 index 0247e280b14..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gpio_drv.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_gpio_drv.h" - -void gpio_toggle_pin_interrupt_trigger_polarity(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index) -{ - bool intr_was_enabled = gpio_check_pin_interrupt_enabled(ptr, gpio_index, pin_index); - gpio_disable_pin_interrupt(ptr, gpio_index, pin_index); - ptr->PL[gpio_index].TOGGLE = 1 << pin_index; - if (intr_was_enabled) { - gpio_enable_pin_interrupt(ptr, gpio_index, pin_index); - } -} - -void gpio_toggle_pin_interrupt_trigger_type(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index) -{ - bool intr_was_enabled = gpio_check_pin_interrupt_enabled(ptr, gpio_index, pin_index); - gpio_disable_pin_interrupt(ptr, gpio_index, pin_index); - ptr->TP[gpio_index].TOGGLE = 1 << pin_index; - if (intr_was_enabled) { - gpio_enable_pin_interrupt(ptr, gpio_index, pin_index); - } -} - - -void gpio_config_pin_interrupt(GPIO_Type *ptr, uint32_t gpio_index, uint8_t pin_index, gpio_interrupt_trigger_t trigger) -{ - switch (trigger) { - case gpio_interrupt_trigger_level_high: - case gpio_interrupt_trigger_level_low: - ptr->TP[gpio_index].CLEAR = 1 << pin_index; - if (trigger == gpio_interrupt_trigger_level_high) { - ptr->PL[gpio_index].CLEAR = 1 << pin_index; - } else { - ptr->PL[gpio_index].SET = 1 << pin_index; - } - break; - case gpio_interrupt_trigger_edge_falling: - case gpio_interrupt_trigger_edge_rising: -#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) - ptr->PD[gpio_index].CLEAR = 1 << pin_index; -#endif - ptr->TP[gpio_index].SET = 1 << pin_index; - if (trigger == gpio_interrupt_trigger_edge_rising) { - ptr->PL[gpio_index].CLEAR = 1 << pin_index; - } else { - ptr->PL[gpio_index].SET = 1 << pin_index; - } - break; -#if defined(GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT) && (GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT == 1) - case gpio_interrupt_trigger_edge_both: - ptr->TP[gpio_index].SET = 1 << pin_index; - ptr->PD[gpio_index].SET = 1 << pin_index; - break; -#endif - default: - return; - } -} - -void gpio_set_pin_output_with_initial(GPIO_Type *ptr, uint32_t port, uint8_t pin, uint8_t initial) -{ - if (initial & 1) { - ptr->DO[port].SET = 1 << pin; - } else { - ptr->DO[port].CLEAR = 1 << pin; - } - ptr->OE[port].SET = 1 << pin; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c deleted file mode 100644 index 51cab7b3619..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gptmr_drv.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_gptmr_drv.h" - -void gptmr_channel_get_default_config(GPTMR_Type *ptr, gptmr_channel_config_t *config) -{ - (void) ptr; - config->mode = gptmr_work_mode_no_capture; - config->dma_request_event = gptmr_dma_request_disabled; - config->synci_edge = gptmr_synci_edge_none; - for (uint8_t i = 0; i < GPTMR_CH_CMP_COUNT; i++) { - config->cmp[i] = 0; - } - config->reload = 0xFFFFFFFFUL; - config->cmp_initial_polarity_high = true; - config->enable_cmp_output = true; - config->enable_sync_follow_previous_channel = false; - config->enable_software_sync = false; - config->debug_mode = true; -} - -hpm_stat_t gptmr_channel_config(GPTMR_Type *ptr, - uint8_t ch_index, - gptmr_channel_config_t *config, - bool enable) -{ - uint32_t v = 0; - uint32_t tmp_value; - - if (config->enable_sync_follow_previous_channel && !ch_index) { - return status_invalid_argument; - } - - if (config->dma_request_event != gptmr_dma_request_disabled) { - v |= GPTMR_CHANNEL_CR_DMAEN_MASK - | GPTMR_CHANNEL_CR_DMASEL_SET(config->dma_request_event); - } - v |= GPTMR_CHANNEL_CR_CAPMODE_SET(config->mode) - | GPTMR_CHANNEL_CR_DBGPAUSE_SET(config->debug_mode) - | GPTMR_CHANNEL_CR_SWSYNCIEN_SET(config->enable_software_sync) - | GPTMR_CHANNEL_CR_CMPINIT_SET(config->cmp_initial_polarity_high) - | GPTMR_CHANNEL_CR_SYNCFLW_SET(config->enable_sync_follow_previous_channel) - | GPTMR_CHANNEL_CR_CMPEN_SET(config->enable_cmp_output) - | GPTMR_CHANNEL_CR_CEN_SET(enable) - | config->synci_edge; - - for (uint8_t i = GPTMR_CH_CMP_COUNT; i > 0; i--) { - tmp_value = config->cmp[i - 1]; - if (tmp_value > 0) { - tmp_value--; - } - ptr->CHANNEL[ch_index].CMP[i - 1] = GPTMR_CHANNEL_CMP_CMP_SET(tmp_value); - } - tmp_value = config->reload; - if (tmp_value > 0) { - tmp_value--; - } - ptr->CHANNEL[ch_index].RLD = GPTMR_CHANNEL_RLD_RLD_SET(tmp_value); - ptr->CHANNEL[ch_index].CR = v; - return status_success; -} - -#if defined(HPM_IP_FEATURE_GPTMR_MONITOR) && (HPM_IP_FEATURE_GPTMR_MONITOR == 1) -void gptmr_channel_get_default_monitor_config(GPTMR_Type *ptr, gptmr_channel_monitor_config_t *config) -{ - (void) ptr; - config->max_value = 0; - config->min_value = 0; - config->monitor_type = monitor_signal_high_level_time; -} - -hpm_stat_t gptmr_channel_monitor_config(GPTMR_Type *ptr, uint8_t ch_index, gptmr_channel_monitor_config_t *config, bool enable) -{ - if ((ptr == NULL) || (config->max_value < config->min_value)) { - return status_invalid_argument; - } - gptmr_channel_set_monitor_type(ptr, ch_index, config->monitor_type); - gptmr_update_cmp(ptr, ch_index, 0, config->min_value + 1); - gptmr_update_cmp(ptr, ch_index, 1, config->max_value + 1); - gptmr_channel_config_update_reload(ptr, ch_index, 0xFFFFFFFF); - gptmr_channel_set_capmode(ptr, ch_index, gptmr_work_mode_measure_width); - if (enable == true) { - gptmr_channel_reset_count(ptr, ch_index); - gptmr_channel_enable_monitor(ptr, ch_index); - } else { - gptmr_channel_disable_monitor(ptr, ch_index); - } - return status_success; -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c deleted file mode 100644 index cde3d8b3383..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_gwc_drv.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_gwc_drv.h" - -void gwc_get_default_config(gwc_config_t *cfg) -{ - cfg->clk_pol = gwc_clk_pol_normal; -} - -void gwc_init(GWC_Type *ptr, gwc_config_t *cfg) -{ - ptr->GLB_CTRL = cfg->clk_pol; -} - -void gwc_enable(GWC_Type *ptr) -{ - ptr->GLB_CTRL |= GWC_GLB_CTRL_GWC_EN_MASK; -} - -void gwc_disable(GWC_Type *ptr) -{ - ptr->GLB_CTRL &= ~GWC_GLB_CTRL_GWC_EN_MASK; -} - -void gwc_freeze_interrupt_control(GWC_Type *ptr) -{ - ptr->IRQ_MASK |= GWC_IRQ_MASK_MASK_RREEZ_MASK; -} - -void gwc_ch_init(GWC_Type *ptr, uint8_t ch_index, gwc_ch_config_t *cfg) -{ - assert(ch_index <= GWC_CHANNEL_CH15); - ptr->CHANNEL[ch_index].CFG0 = GWC_CHANNEL_CFG0_START_ROW_SET(cfg->start_row) | - GWC_CHANNEL_CFG0_START_COL_SET(cfg->start_col) | - (cfg->freeze ? GWC_CHANNEL_CFG0_FREEZE_MASK : 0); - ptr->CHANNEL[ch_index].CFG1 = GWC_CHANNEL_CFG1_END_ROW_SET(cfg->end_row) | - GWC_CHANNEL_CFG1_END_COL_SET(cfg->end_col); - ptr->CHANNEL[ch_index].REFCRC = cfg->ref_crc; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c deleted file mode 100644 index 1f0d9b24346..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2c_drv.c +++ /dev/null @@ -1,1124 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_i2c_drv.h" - -#ifndef HPM_I2C_DRV_DEFAULT_TPM -#define HPM_I2C_DRV_DEFAULT_TPM (0U) -#endif - -#ifndef HPM_I2C_DRV_DEFAULT_RETRY_COUNT -#define HPM_I2C_DRV_DEFAULT_RETRY_COUNT (5000U) -#endif - -#define period_in_100ps(freq) (10000000000UL / (freq)) - -typedef struct { - uint32_t t_high; - uint32_t t_low; - uint16_t t_sp; - uint16_t t_sudat; - uint16_t t_hddat; - uint16_t t_sclhi; - uint16_t t_sclratio; -} i2c_timing_t; - -static hpm_stat_t i2c_configure_timing(uint32_t src_clk_in_hz, - i2c_mode_t i2c_mode, - i2c_timing_t *timing) -{ - int32_t setup_time, hold_time, period; - int32_t temp1, temp2, temp3; - int32_t tpclk = period_in_100ps(src_clk_in_hz); - - switch (i2c_mode) { - /* - * |Standard mode | Fast mode | Fast mode plus | Uint - * ---------+--------------+-----------+----------------+------- - * t_high | 4.0 | 0.6 | 0.26 | us - * t_low | 4.7 | 1.3 | 0.5 | us - * - */ - /* time uint: 100ps */ - case i2c_mode_fast: - timing->t_high = 6000; - timing->t_low = 13000; - timing->t_sclratio = 2; - setup_time = 1000; - hold_time = 3000; - period = period_in_100ps(400000); /**< baudrate 400KHz */ - break; - case i2c_mode_fast_plus: - timing->t_high = 2600; - timing->t_low = 5000; - timing->t_sclratio = 2; - setup_time = 500; - hold_time = 0; - period = period_in_100ps(1000000); /**< baudrate 1MHz */ - break; - case i2c_mode_normal: - timing->t_high = 40000; - timing->t_low = 47000; - timing->t_sclratio = 1; - setup_time = 2500; - hold_time = 3000; - period = period_in_100ps(100000); /**< baudrate 100KHz */ - break; - default: - return status_i2c_not_supported; - } - - /* - * Spike Suppression | Standard | Fast mode | Fast mode plus | Uint - * | mode | | | - * ------------------+----------+-----------+----------------+------- - * t_sp (min) | - | 0 - 50 | 0 - 50 | ns - * - * T_SP = 50ns / (tpclk * (TPM + 1)) - */ - timing->t_sp = 500 / period_in_100ps(src_clk_in_hz) / (HPM_I2C_DRV_DEFAULT_TPM + 1); - - /* - * Setup time |Standard mode | Fast mode | Fast mode plus | Uint - * -----------------+--------------+-----------+----------------+------- - * t_sudat (min) | 250 | 100 | 50 | ns - * - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk * (TPM + 1) - */ - temp1 = (setup_time - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; - timing->t_sudat = MAX(temp1, 0); - /* - * Hold time |Standard mode | Fast mode | Fast mode plus | Uint - * ----------------+--------------+-----------+----------------+------- - * t_hddata (min) | 300 | 300 | 0 | ns - * - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk * (TPM + 1) - */ - temp1 = (hold_time - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; - timing->t_hddat = MAX(temp1, 0); - - /* - * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > t_high; - */ - temp1 = (timing->t_high - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; - - /* - * SCLK High period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk * (TPM + 1) > period / (1 + ratio); - */ - temp2 = (period / (1 + timing->t_sclratio) - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp; - - /* - * SCLK Low period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM + 1) > t_low; - */ - temp3 = ((timing->t_low - 2 * tpclk) / tpclk / (HPM_I2C_DRV_DEFAULT_TPM + 1) - 2 - timing->t_sp) / (timing->t_sclratio); - - timing->t_sclhi = MAX(MAX(temp1, temp2), temp3); - - /* update high_period and low_period to calculated value */ - timing->t_high = 2 * tpclk + (2 + timing->t_sp + timing->t_sclhi) * tpclk; - timing->t_low = timing->t_high * timing->t_sclratio; - - return status_success; -} - -void i2c_reset(I2C_Type *ptr) -{ - ptr->CTRL = 0; - ptr->CMD = I2C_CMD_RESET; - ptr->SETUP &= ~I2C_SETUP_IICEN_MASK; -} - -hpm_stat_t i2c_init_master(I2C_Type *ptr, uint32_t src_clk_in_hz, i2c_config_t *config) -{ - hpm_stat_t stat = status_success; - i2c_timing_t timing = {0}; - - i2c_reset(ptr); - - stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); - if (status_success != stat) { - return stat; - } - - ptr->TPM = I2C_TPM_TPM_SET(HPM_I2C_DRV_DEFAULT_TPM); - - ptr->SETUP = I2C_SETUP_T_SP_SET(timing.t_sp) - | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) - | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) - | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) - | I2C_SETUP_T_SCLHI_SET(timing.t_sclhi) - | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) - | I2C_SETUP_IICEN_MASK - | I2C_SETUP_MASTER_MASK; - - return status_success; -} - -hpm_stat_t i2c_master_address_read(I2C_Type *ptr, const uint16_t device_address, - uint8_t *addr, uint32_t addr_size_in_byte, - uint8_t *buf, const uint32_t size_in_byte) -{ - hpm_stat_t stat = status_success; - uint32_t left; - uint32_t retry; - if (((addr_size_in_byte == 0) || (addr_size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || - ((size_in_byte == 0) || (size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - retry = 0; - while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(addr_size_in_byte) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(addr_size_in_byte)); - - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - - left = addr_size_in_byte; - while (left) { - ptr->DATA = *(addr++); - left--; - } - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - /* the address misses, a stop needs to be added to prevent the bus from being busy. */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - ptr->CTRL = I2C_CTRL_PHASE_STOP_MASK; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - return status_i2c_no_addr_hit; - } - ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(addr_size_in_byte) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte)); - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - retry = 0; - left = size_in_byte; - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { - *(buf++) = ptr->DATA; - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - return stat; -} - -hpm_stat_t i2c_master_address_write(I2C_Type *ptr, const uint16_t device_address, - uint8_t *addr, uint32_t addr_size_in_byte, - uint8_t *buf, const uint32_t size_in_byte) -{ - hpm_stat_t stat = status_success; - uint32_t left; - uint32_t retry; - - if (((addr_size_in_byte == 0) || (addr_size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || - ((size_in_byte == 0) || (size_in_byte > I2C_SOC_TRANSFER_COUNT_MAX)) || - ((addr_size_in_byte + size_in_byte) > I2C_SOC_TRANSFER_COUNT_MAX)) { - return status_invalid_argument; - } - - retry = 0; - while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size_in_byte + addr_size_in_byte)); - - left = addr_size_in_byte; - while (left) { - ptr->DATA = *(addr++); - left--; - } - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_i2c_no_addr_hit; - } - ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; - - retry = 0; - left = size_in_byte; - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { - ptr->DATA = *(buf++); - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } else { - retry++; - } - } - - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - return stat; -} - -hpm_stat_t i2c_master_read(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size) -{ - hpm_stat_t stat = status_success; - uint32_t left; - uint32_t retry; - if (size > I2C_SOC_TRANSFER_COUNT_MAX) { - return status_invalid_argument; - } - - retry = 0; - while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ); - if (size > 0) { - ptr->CTRL |= I2C_CTRL_PHASE_DATA_MASK -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - } - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_i2c_no_addr_hit; - } - ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; - /* when size is zero, it's probe slave device, so directly return success */ - if (size == 0) { - return status_success; - } - - retry = 0; - left = size; - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { - *(buf++) = ptr->DATA; - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - }; - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - if (i2c_get_data_count(ptr) && (size)) { - return status_i2c_transmit_not_completed; - } - - return stat; -} - -hpm_stat_t i2c_master_write(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size) -{ - hpm_stat_t stat = status_success; - uint32_t retry; - uint32_t left; - - if (size > I2C_SOC_TRANSFER_COUNT_MAX) { - return status_invalid_argument; - } - - retry = 0; - while (ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE); - if (size > 0) { - ptr->CTRL |= I2C_CTRL_PHASE_DATA_MASK -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - } - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - /* Before starting to transmit data, judge addrhit to ensure that the slave address exists on the bus. */ - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_i2c_no_addr_hit; - } - ptr->STATUS = I2C_STATUS_ADDRHIT_MASK; - /* when size is zero, it's probe slave device, so directly return success */ - if (size == 0) { - return status_success; - } - - retry = 0; - left = size; - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { - ptr->DATA = *(buf++); - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - if (i2c_get_data_count(ptr) && (size)) { - return status_i2c_transmit_not_completed; - } - - return stat; -} - -hpm_stat_t i2c_init_slave(I2C_Type *ptr, uint32_t src_clk_in_hz, - i2c_config_t *config, const uint16_t slave_address) -{ - hpm_stat_t stat = status_success; - i2c_timing_t timing = {0}; - - i2c_reset(ptr); - - ptr->ADDR = I2C_ADDR_ADDR_SET(slave_address); - - stat = i2c_configure_timing(src_clk_in_hz, config->i2c_mode, &timing); - if (status_success != stat) { - return stat; - } - - ptr->TPM = I2C_TPM_TPM_SET(HPM_I2C_DRV_DEFAULT_TPM); - - ptr->SETUP = I2C_SETUP_T_SP_SET(timing.t_sp) - | I2C_SETUP_T_SUDAT_SET(timing.t_sudat) - | I2C_SETUP_T_HDDAT_SET(timing.t_hddat) - | I2C_SETUP_T_SCLRADIO_SET(timing.t_sclratio - 1) - | I2C_SETUP_T_SCLHI_SET(timing.t_sclhi) - | I2C_SETUP_ADDRESSING_SET(config->is_10bit_addressing) - | I2C_SETUP_IICEN_MASK; - - return stat; -} - -hpm_stat_t i2c_slave_write(I2C_Type *ptr, uint8_t *buf, const uint32_t size) -{ - volatile uint32_t status; - uint32_t retry; - uint32_t left; - - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - /* wait for address hit */ - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_fail; - } - - /* W1C, clear CMPL bit and clear ADDRHIT bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; - ptr->CMD = I2C_CMD_CLEAR_FIFO; - - retry = 0; - left = size; - while (left) { - status = ptr->STATUS; - if (!(status & I2C_STATUS_FIFOFULL_MASK)) { - ptr->DATA = *(buf++); - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - /* clear status, CMPL must to be cleared at slave mode before next transaction */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - if (i2c_get_data_count(ptr) != size) { - return status_i2c_transmit_not_completed; - } - - return status_success; -} - -hpm_stat_t i2c_slave_read(I2C_Type *ptr, - uint8_t *buf, - const uint32_t size) -{ - volatile uint32_t status; - uint32_t retry; - uint32_t left; - - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - /* wait for address hit */ - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_ADDRHIT_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_fail; - } - - /* W1C, clear CMPL bit and clear ADDRHIT bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK | I2C_STATUS_ADDRHIT_MASK; - ptr->CMD = I2C_CMD_CLEAR_FIFO; - - retry = 0; - left = size; - while (left) { - status = ptr->STATUS; - if (!(status & I2C_STATUS_FIFOEMPTY_MASK)) { - *(buf++) = ptr->DATA; - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - /* clear status, CMPL must to be cleared at slave mode before next transaction */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - - if (i2c_get_data_count(ptr) != size) { - return status_i2c_transmit_not_completed; - } - - return status_success; -} - -hpm_stat_t i2c_master_start_dma_write(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) -{ - uint32_t retry = 0; - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; - - i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - - i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; - - i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - return status_success; -} - -hpm_stat_t i2c_master_start_dma_read(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size) -{ - uint32_t retry = 0; - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - /* W1C, clear CMPL bit to avoid blocking the transmission */ - i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; - - i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - - i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; - - i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - return status_success; -} - -hpm_stat_t i2c_slave_dma_transfer(I2C_Type *i2c_ptr, uint32_t size) -{ - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; - -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - i2c_ptr->CTRL &= ~(I2C_CTRL_DATACNT_HIGH_MASK | I2C_CTRL_DATACNT_MASK); - i2c_ptr->CTRL |= I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); -#else - i2c_ptr->CTRL &= ~I2C_CTRL_DATACNT_MASK; - i2c_ptr->CTRL |= I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); -#endif - - i2c_ptr->SETUP |= I2C_SETUP_DMAEN_MASK; - - return status_success; -} - -hpm_stat_t i2c_master_configure_transfer(I2C_Type *i2c_ptr, const uint16_t device_address, uint32_t size, bool read) -{ - uint32_t retry = 0; - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - while (i2c_ptr->STATUS & I2C_STATUS_BUSBUSY_MASK) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - /* W1C, clear CMPL bit to avoid blocking the transmission */ - i2c_ptr->STATUS = I2C_STATUS_CMPL_MASK; - i2c_ptr->CMD = I2C_CMD_CLEAR_FIFO; - i2c_ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - i2c_ptr->CTRL = I2C_CTRL_PHASE_START_MASK - | I2C_CTRL_PHASE_STOP_MASK - | I2C_CTRL_PHASE_ADDR_MASK - | I2C_CTRL_PHASE_DATA_MASK - | I2C_CTRL_DIR_SET(read) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - - i2c_ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - return status_success; -} - -hpm_stat_t i2c_master_seq_transmit(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt) -{ - uint32_t ctrl; - uint32_t retry = 0; - uint32_t left = 0; - - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - - switch (opt) { - case i2c_frist_frame: - ctrl = I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(false) \ - | I2C_CTRL_PHASE_ADDR_SET(true); - break; - case i2c_next_frame: - ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(false) \ - | I2C_CTRL_PHASE_ADDR_SET(false); - break; - case i2c_last_frame: - ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(true) \ - | I2C_CTRL_PHASE_ADDR_SET(false); - break; - default: - return status_invalid_argument; - } - - ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - /* enable auto ack */ - ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - retry = 0; - left = size; - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { - ptr->DATA = *(buf++); - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - /* clear status, CMPL must to be cleared at slave mode before next transaction */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - return status_success; -} - -hpm_stat_t i2c_master_seq_receive(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, i2c_seq_transfer_opt_t opt) -{ - uint32_t ctrl; - uint32_t retry = 0; - uint32_t left = 0; - - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - - switch (opt) { - case i2c_frist_frame: - ctrl = I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(false) \ - | I2C_CTRL_PHASE_ADDR_SET(true); - break; - case i2c_next_frame: - ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(false) \ - | I2C_CTRL_PHASE_ADDR_SET(false); - break; - case i2c_last_frame: - ctrl = I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(true) \ - | I2C_CTRL_PHASE_ADDR_SET(false); - break; - default: - return status_invalid_argument; - } - - ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) - | I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - - /* disable auto ack */ - ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - - retry = 0; - left = size; - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { - *(buf++) = ptr->DATA; - left--; - if ((left == 0) && (opt == i2c_last_frame)) { - ptr->CMD = I2C_CMD_NACK; - } else { - ptr->CMD = I2C_CMD_ACK; - } - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - if (opt == i2c_last_frame) { - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - } - /* clear status, CMPL must to be cleared at slave mode before next transaction */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - /* default auto ack */ - ptr->INTEN &= ~I2C_EVENT_BYTE_RECEIVED; - - return status_success; -} - -hpm_stat_t i2c_master_transfer(I2C_Type *ptr, const uint16_t device_address, - uint8_t *buf, const uint32_t size, uint16_t flags) -{ - uint32_t ctrl = 0; - uint32_t retry = 0; - uint32_t left = 0; - if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) { - return status_invalid_argument; - } - if (flags & I2C_ADDR_10BIT) { - i2c_enable_10bit_address_mode(ptr, true); - } else { - i2c_enable_10bit_address_mode(ptr, false); - } - /* W1C, clear CMPL bit to avoid blocking the transmission */ - ptr->STATUS = I2C_STATUS_CMPL_MASK; - ptr->CMD = I2C_CMD_CLEAR_FIFO; - ptr->ADDR = I2C_ADDR_ADDR_SET(device_address); - - if (flags & I2C_RD) { - ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ); - } else { - ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE);/* is write flag */ - } - /* start signal */ - if (flags & I2C_NO_START) { - ctrl |= I2C_CTRL_PHASE_START_SET(false); - } else { - ctrl |= I2C_CTRL_PHASE_START_SET(true); - } - /* end signal*/ - if (flags & I2C_NO_STOP) { - ctrl |= I2C_CTRL_PHASE_STOP_SET(false); - } else { - ctrl |= I2C_CTRL_PHASE_STOP_SET(true); - } - - ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) - | I2C_CTRL_PHASE_ADDR_SET(true) -#ifdef I2C_CTRL_DATACNT_HIGH_MASK - | I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) -#endif - | I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size)); - /* disable auto ack */ - ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED; - ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION; - retry = 0; - left = size; - if (flags & I2C_RD) { - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) { - *(buf++) = ptr->DATA; - left--; - if (left == 0) { - ptr->CMD = I2C_CMD_NACK; - } else { - /* ACK is sent when reading */ - if (!(flags & I2C_NO_READ_ACK)) { - ptr->CMD = I2C_CMD_ACK; - } - } - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - } else { - while (left) { - if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) { - ptr->DATA = *(buf++); - left--; - retry = 0; - } else { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - } - retry = 0; - while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) { - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - if (i2c_get_data_count(ptr) && (size)) { - return status_i2c_transmit_not_completed; - } - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c deleted file mode 100644 index 73e93c179df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_i2s_drv.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_i2s_drv.h" - -#define HPM_I2S_DRV_DEFAULT_RETRY_COUNT 5000U - -#ifndef HPM_I2S_BCLK_TOLERANCE -#define HPM_I2S_BCLK_TOLERANCE (4U) -#endif - -#define HPM_I2S_SLOT_MASK I2S_TXDSLOT_EN_MASK /* TX/RX has same SLOT MASK */ - - -static bool i2s_audio_depth_is_valid(uint8_t bits) -{ - /* i2s audio depth only support 16bits, 24bits, 32bits */ - if (bits == i2s_audio_depth_16_bits || bits == i2s_audio_depth_24_bits || bits == i2s_audio_depth_32_bits) { - return true; - } - return false; -} - -static bool i2s_channel_length_is_valid(uint8_t bits) -{ - /* i2s channel length only support 16bits or 32bits */ - if (bits == i2s_channel_length_16_bits || bits == i2s_channel_length_32_bits) { - return true; - } - return false; -} - -/* work around: fill dummy data into TX fifo to avoid TX underflow during tx start */ -hpm_stat_t i2s_fill_tx_dummy_data(I2S_Type *ptr, uint8_t data_line, uint8_t data_count) -{ - uint32_t retry = 0; - - if (data_count > I2S_SOC_MAX_TX_FIFO_DEPTH) { - return status_invalid_argument; - } - - /* check dummy data count in TX FIFO */ - while (i2s_get_tx_line_fifo_level(ptr, data_line) < data_count) { - ptr->TXD[data_line] = 0; - if (retry > HPM_I2S_DRV_DEFAULT_RETRY_COUNT * data_count) { - return status_timeout; - } - retry++; - } - - return status_success; -} - -/* The I2S software reset function relies on a working BCLK */ -void i2s_reset_all(I2S_Type *ptr) -{ - uint32_t cfgr_temp, misc_cfgr_temp; - - /* disable I2S */ - ptr->CTRL &= ~I2S_CTRL_I2S_EN_MASK; - - /* enable internal clock for software reset function */ - cfgr_temp = ptr->CFGR; - ptr->CFGR |= I2S_CFGR_BCLK_DIV_SET(1); - ptr->CFGR &= ~(I2S_CFGR_MCK_SEL_OP_MASK | I2S_CFGR_BCLK_SEL_OP_MASK | I2S_CFGR_FCLK_SEL_OP_MASK | I2S_CFGR_BCLK_GATEOFF_MASK); - misc_cfgr_temp = ptr->MISC_CFGR; - ptr->MISC_CFGR &= ~I2S_MISC_CFGR_MCLK_GATEOFF_MASK; - - /* reset function block and clear fifo */ - ptr->CTRL |= (I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); - ptr->CTRL &= ~(I2S_CTRL_TXFIFOCLR_MASK | I2S_CTRL_RXFIFOCLR_MASK | I2S_CTRL_SFTRST_CLKGEN_MASK | I2S_CTRL_SFTRST_TX_MASK | I2S_CTRL_SFTRST_RX_MASK); - - /* Restore the value of the register */ - ptr->CFGR = cfgr_temp; - ptr->MISC_CFGR = misc_cfgr_temp; -} - -void i2s_get_default_config(I2S_Type *ptr, i2s_config_t *config) -{ - (void) ptr; - config->invert_mclk_out = false; - config->invert_mclk_in = false; - config->use_external_mclk = false; - config->invert_bclk_out = false; - config->invert_bclk_in = false; - config->use_external_bclk = false; - config->invert_fclk_out = false; - config->invert_fclk_in = false; - config->use_external_fclk = false; - config->enable_mclk_out = false; - config->frame_start_at_rising_edge = false; - config->tx_fifo_threshold = 4; - config->rx_fifo_threshold = 4; -} - -void i2s_init(I2S_Type *ptr, i2s_config_t *config) -{ - i2s_reset_all(ptr); - - ptr->CFGR = I2S_CFGR_INV_MCLK_OUT_SET(config->invert_mclk_out) - | I2S_CFGR_INV_MCLK_IN_SET(config->invert_mclk_in) - | I2S_CFGR_MCK_SEL_OP_SET(config->use_external_mclk) - | I2S_CFGR_INV_BCLK_OUT_SET(config->invert_bclk_out) - | I2S_CFGR_INV_BCLK_IN_SET(config->invert_bclk_in) - | I2S_CFGR_BCLK_SEL_OP_SET(config->use_external_bclk) - | I2S_CFGR_INV_FCLK_OUT_SET(config->invert_fclk_out) - | I2S_CFGR_INV_FCLK_IN_SET(config->invert_fclk_in) - | I2S_CFGR_FCLK_SEL_OP_SET(config->use_external_fclk) - | I2S_CFGR_FRAME_EDGE_SET(config->frame_start_at_rising_edge); - ptr->MISC_CFGR = (ptr->MISC_CFGR - & ~(I2S_MISC_CFGR_MCLKOE_MASK - | I2S_MISC_CFGR_MCLK_GATEOFF_MASK)) - | I2S_MISC_CFGR_MCLKOE_SET(config->enable_mclk_out); - ptr->FIFO_THRESH = I2S_FIFO_THRESH_TX_SET(config->tx_fifo_threshold) - | I2S_FIFO_THRESH_RX_SET(config->rx_fifo_threshold); -} - -static void i2s_config_cfgr(I2S_Type *ptr, - uint32_t bclk_div, - i2s_transfer_config_t *config) -{ - i2s_gate_bclk(ptr); - ptr->CFGR = (ptr->CFGR & ~(I2S_CFGR_BCLK_DIV_MASK | I2S_CFGR_TDM_EN_MASK | I2S_CFGR_CH_MAX_MASK | I2S_CFGR_STD_MASK | I2S_CFGR_DATSIZ_MASK | I2S_CFGR_CHSIZ_MASK)) - | I2S_CFGR_BCLK_DIV_SET(bclk_div) - | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) - | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) - | I2S_CFGR_STD_SET(config->protocol) - | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) - | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); - i2s_ungate_bclk(ptr); -} - -static void i2s_config_cfgr_slave(I2S_Type *ptr, - i2s_transfer_config_t *config) -{ - ptr->CFGR = (ptr->CFGR & ~(I2S_CFGR_TDM_EN_MASK | I2S_CFGR_CH_MAX_MASK | I2S_CFGR_STD_MASK | I2S_CFGR_DATSIZ_MASK | I2S_CFGR_CHSIZ_MASK)) - | I2S_CFGR_TDM_EN_SET(config->enable_tdm_mode) - | I2S_CFGR_CH_MAX_SET(config->channel_num_per_frame) - | I2S_CFGR_STD_SET(config->protocol) - | I2S_CFGR_DATSIZ_SET(I2S_CFGR_DATASIZ(config->audio_depth)) - | I2S_CFGR_CHSIZ_SET(I2S_CFGR_CHSIZ(config->channel_length)); -} - -static bool i2s_calculate_bclk_divider(uint32_t mclk_in_hz, uint32_t bclk_in_hz, uint32_t *div_out) -{ - uint32_t bclk_div; - uint32_t delta1, delta2; - - bclk_div = mclk_in_hz / bclk_in_hz; - - if ((bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { - return false; - } - - delta1 = mclk_in_hz - bclk_in_hz * bclk_div; - delta2 = bclk_in_hz * (bclk_div + 1) - mclk_in_hz; - if (delta2 < delta1) { - bclk_div++; - if ((bclk_div > (I2S_CFGR_BCLK_DIV_MASK >> I2S_CFGR_BCLK_DIV_SHIFT))) { - return false; - } - } - - if (MIN(delta1, delta2) && ((MIN(delta1, delta2) * 100 / bclk_in_hz) > HPM_I2S_BCLK_TOLERANCE)) { - return false; - } - - *div_out = bclk_div; - return true; -} - -static hpm_stat_t _i2s_config_tx(I2S_Type *ptr, i2s_transfer_config_t *config) -{ - /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ - uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - if (!i2s_audio_depth_is_valid(config->audio_depth) - || !i2s_channel_length_is_valid(config->channel_length) - || !config->sample_rate - || !channel_num_per_frame - || (channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || ((!config->enable_tdm_mode) && (channel_num_per_frame > 2)) - || ((config->channel_slot_mask & HPM_I2S_SLOT_MASK) == 0)) { - return status_invalid_argument; - } - - ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; - - /* work around: fill dummy data into TX fifo to avoid TX underflow during tx start */ - if (i2s_fill_tx_dummy_data(ptr, config->data_line, config->channel_num_per_frame) != status_success) { - return status_invalid_argument; - } - - ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_TX_EN_MASK)) - | I2S_CTRL_TX_EN_SET(1 << config->data_line); - - return status_success; -} - -static hpm_stat_t _i2s_config_rx(I2S_Type *ptr, i2s_transfer_config_t *config) -{ - /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ - uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - if (!i2s_audio_depth_is_valid(config->audio_depth) - || !i2s_channel_length_is_valid(config->channel_length) - || !config->sample_rate - || !channel_num_per_frame - || (channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || ((!config->enable_tdm_mode) && (channel_num_per_frame > 2)) - || ((config->channel_slot_mask & HPM_I2S_SLOT_MASK) == 0)) { - return status_invalid_argument; - } - - ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; - ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK)) - | I2S_CTRL_RX_EN_SET(1 << config->data_line); - - return status_success; -} - -static hpm_stat_t _i2s_config_transfer(I2S_Type *ptr, i2s_transfer_config_t *config) -{ - /* channel_num_per_frame has to even. non TDM mode, it has be 2 */ - uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - if (!i2s_audio_depth_is_valid(config->audio_depth) - || !i2s_channel_length_is_valid(config->channel_length) - || !config->sample_rate - || !channel_num_per_frame - || (channel_num_per_frame > I2S_SOC_MAX_CHANNEL_NUM) - || ((!config->enable_tdm_mode) && (channel_num_per_frame > 2)) - || ((config->channel_slot_mask & HPM_I2S_SLOT_MASK) == 0)) { - return status_invalid_argument; - } - - /* Suppose RX and TX use same channel */ - ptr->RXDSLOT[config->data_line] = config->channel_slot_mask; - ptr->TXDSLOT[config->data_line] = config->channel_slot_mask; - - /* work around: fill dummy data into TX fifo to avoid TX underflow during tx start */ - if (i2s_fill_tx_dummy_data(ptr, config->data_line, config->channel_num_per_frame) != status_success) { - return status_invalid_argument; - } - - ptr->CTRL = (ptr->CTRL & ~(I2S_CTRL_RX_EN_MASK | I2S_CTRL_TX_EN_MASK)) - | I2S_CTRL_RX_EN_SET(1 << config->data_line) - | I2S_CTRL_TX_EN_SET(1 << config->data_line); - - return status_success; -} - -hpm_stat_t i2s_config_tx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) -{ - uint32_t bclk_in_hz; - uint32_t bclk_div; - uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - - bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; - if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { - return status_invalid_argument; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - - return _i2s_config_tx(ptr, config); -} - -hpm_stat_t i2s_config_tx_slave(I2S_Type *ptr, i2s_transfer_config_t *config) -{ - i2s_disable(ptr); - i2s_config_cfgr_slave(ptr, config); - - return _i2s_config_tx(ptr, config); -} - -hpm_stat_t i2s_config_rx(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) -{ - uint32_t bclk_in_hz; - uint32_t bclk_div; - - uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; - if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { - return status_invalid_argument; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - - return _i2s_config_rx(ptr, config); -} - -hpm_stat_t i2s_config_rx_slave(I2S_Type *ptr, i2s_transfer_config_t *config) -{ - i2s_disable(ptr); - i2s_config_cfgr_slave(ptr, config); - - return _i2s_config_rx(ptr, config); -} - -hpm_stat_t i2s_config_transfer(I2S_Type *ptr, uint32_t mclk_in_hz, i2s_transfer_config_t *config) -{ - uint32_t bclk_in_hz; - uint32_t bclk_div; - - uint8_t channel_num_per_frame = HPM_NUM_TO_EVEN_CEILING(config->channel_num_per_frame); - bclk_in_hz = config->sample_rate * config->channel_length * channel_num_per_frame; - if (!i2s_calculate_bclk_divider(mclk_in_hz, bclk_in_hz, &bclk_div)) { - return status_invalid_argument; - } - - i2s_disable(ptr); - i2s_config_cfgr(ptr, bclk_div, config); - - return _i2s_config_transfer(ptr, config); -} - -hpm_stat_t i2s_config_transfer_slave(I2S_Type *ptr, i2s_transfer_config_t *config) -{ - i2s_disable(ptr); - i2s_config_cfgr_slave(ptr, config); - - return _i2s_config_transfer(ptr, config); -} - -uint32_t i2s_send_buff(I2S_Type *ptr, uint8_t tx_line_index, uint8_t samplebits, uint8_t *src, uint32_t size) -{ - uint32_t data; - uint32_t retry = 0; - uint8_t bytes = samplebits / 8U; - uint32_t left; - - if (!i2s_audio_depth_is_valid(samplebits)) { - return 0; - } - - if ((size % bytes) != 0) { - return 0; - } - - left = size; - while (left) { - /* check fifo status */ - if (i2s_get_tx_line_fifo_level(ptr, tx_line_index) < I2S_FIFO_THRESH_TX_GET(ptr->FIFO_THRESH)) { - /* Move valid data to high position */ - data = *((uint32_t *)(src)) << (32 - samplebits); - ptr->TXD[tx_line_index] = data; - src += bytes; - left -= bytes; - retry = 0; - } else { - if (retry > HPM_I2S_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - - return size - left; -} - -uint32_t i2s_receive_buff(I2S_Type *ptr, uint8_t rx_line_index, uint8_t samplebits, uint8_t *dst, uint32_t size) -{ - uint32_t data; - uint32_t left; - uint32_t retry = 0; - uint8_t bytes = samplebits / 8U; - - if (!i2s_audio_depth_is_valid(samplebits)) { - return 0; - } - - if ((size % bytes) != 0) { - return 0; - } - - left = size; - while (left) { - /* check fifo status */ - if (i2s_get_rx_line_fifo_level(ptr, rx_line_index) < I2S_FIFO_THRESH_RX_GET(ptr->FIFO_THRESH)) { - /* valid data on high position */ - data = ptr->RXD[rx_line_index] >> (32 - samplebits); - for (uint8_t n = 0; n < bytes; n++) { - *dst = (uint8_t)(data >> (8U * n)) & 0xFFU; - dst++; - left--; - retry = 0; - } - } else { - if (retry > HPM_I2S_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - - return size - left; -} - -void i2s_get_default_transfer_config_for_pdm(i2s_transfer_config_t *transfer) -{ - transfer->sample_rate = PDM_SOC_SAMPLE_RATE_IN_HZ; - transfer->channel_num_per_frame = 8; - transfer->channel_length = i2s_channel_length_32_bits; - transfer->audio_depth = i2s_audio_depth_32_bits; - transfer->enable_tdm_mode = true; - transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; -} - -void i2s_get_default_transfer_config_for_dao(i2s_transfer_config_t *transfer) -{ - transfer->sample_rate = DAO_SOC_SAMPLE_RATE_IN_HZ; - transfer->channel_num_per_frame = 2; - transfer->channel_length = i2s_channel_length_32_bits; - transfer->audio_depth = i2s_audio_depth_32_bits; - transfer->enable_tdm_mode = false; - transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; - transfer->data_line = I2S_DATA_LINE_0; - transfer->channel_slot_mask = 0x3; -} - -void i2s_get_default_transfer_config(i2s_transfer_config_t *transfer) -{ - transfer->sample_rate = 48000U; - transfer->channel_num_per_frame = 2; - transfer->channel_length = i2s_channel_length_32_bits; - transfer->audio_depth = i2s_audio_depth_32_bits; - transfer->enable_tdm_mode = false; - transfer->protocol = I2S_PROTOCOL_MSB_JUSTIFIED; - transfer->data_line = I2S_DATA_LINE_0; - transfer->channel_slot_mask = 0x3; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c deleted file mode 100644 index 90cf0df7924..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_jpeg_drv.c +++ /dev/null @@ -1,326 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_jpeg_drv.h" - -#define HPM_JPEG_DEFAULT_MAX_OT (2) - -const jpeg_sampling_t jpeg_supported_sampling[5] = { - {2, 2, 1, 1}, /* 420 */ - {2, 1, 1, 1}, /* 422H */ - {1, 2, 1, 1}, /* 422V */ - {1, 1, 1, 1}, /* 444 */ - {1, 1, 0, 0}, /* 400 */ -}; - -const jpeg_pixel_t jpeg_supported_pixel_format[6] = { - {4, 1, 1, true}, /* JPEG_PIXEL_FORMAT_ARGB8888 */ - {2, 2, 2, true}, /* JPEG_PIXEL_FORMAT_RGB565 */ - {2, 3, 0, false}, /* JPEG_PIXEL_FORMAT_YUV422H1P */ - {1, 0, 0, false}, /* JPEG_PIXEL_FORMAT_YUV422H2P */ - {1, 0, 0, false}, /* JPEG_PIXEL_FORMAT_YUV420 */ - {1, 0, 0, false}, /* JPEG_PIXEL_FORMAT_Y8 */ -}; - -void jpeg_disable_irq(JPEG_Type *ptr, uint32_t mask) -{ - if (mask & JPEG_EVENT_IN_DMA_FINISH) { - ptr->INDMA_MISC &= ~(JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK - | JPEG_INDMA_MISC_IRQ_EN_MASK); - } - if (mask & JPEG_EVENT_OUT_DMA_FINISH) { - ptr->OUTDMA_MISC &= ~(JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK - | JPEG_OUTDMA_MISC_IRQ_EN_MASK); - } - if (mask & JPEG_EVENT_ERROR) { - ptr->CFG &= ~(JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK); - } -} - -void jpeg_enable_irq(JPEG_Type *ptr, uint32_t mask) -{ - if (mask & JPEG_EVENT_IN_DMA_FINISH) { - ptr->INDMA_MISC |= JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK - | JPEG_INDMA_MISC_IRQ_EN_MASK; - } - if (mask & JPEG_EVENT_OUT_DMA_FINISH) { - ptr->OUTDMA_MISC |= JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK - | JPEG_OUTDMA_MISC_IRQ_EN_MASK; - } - if (mask & JPEG_EVENT_ERROR) { - ptr->CFG |= JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK; - } -} - -void jpeg_reset(JPEG_Type *ptr) -{ - jpeg_stop(ptr); - jpeg_software_reset(ptr); - ptr->STAT = 0xFFFFFFFFUL; - -} - -void jpeg_init(JPEG_Type *ptr) -{ - jpeg_reset(ptr); - jpeg_clear_cfg(ptr); -} - -static bool jpeg_need_csc(jpeg_pixel_format_t in, jpeg_pixel_format_t out) -{ - return (jpeg_supported_pixel_format[in].is_rgb != jpeg_supported_pixel_format[out].is_rgb); -} - -static bool jpeg_is_valid_size(uint8_t format, uint32_t width, uint32_t height) -{ - uint32_t align; - if (format > ARRAY_SIZE(jpeg_supported_sampling)) { - return false; - } - align = jpeg_supported_sampling[format].hy * 8; - if (width % align) { - return false; - } - align = jpeg_supported_sampling[format].vy * 8; - if (height % align) { - return false; - } - return true; -} - -#define JPEG_HY(x) ((x)->hy) -#define JPEG_VY(x) ((x)->vy) -#define JPEG_HC(x) ((x)->hc) -#define JPEG_VC(x) ((x)->vc) - -static uint32_t jpeg_calculate_macro_block_count(uint32_t width, uint32_t height, jpeg_sampling_t *sampling) -{ - return (width / (JPEG_HY(sampling) << 3)) * (height / (JPEG_VY(sampling) << 3)); -} - -static void jpeg_config_interal_regs(JPEG_Type *ptr, - bool decoding, - uint32_t macro_block_count, - uint8_t format) -{ - (void) decoding; - uint8_t hy, vy, hc, vc; - hy = JPEG_HY(&jpeg_supported_sampling[format]); - vy = JPEG_VY(&jpeg_supported_sampling[format]); - hc = JPEG_HC(&jpeg_supported_sampling[format]); - vc = JPEG_VC(&jpeg_supported_sampling[format]); - - if (format != JPEG_SUPPORTED_FORMAT_400) { - ptr->IMGREG1 = JPEG_IMGREG1_NCOL_SET(2); - } else { - ptr->IMGREG1 = 8; - } - ptr->IMGREG2 = JPEG_IMGREG2_NMCU_SET(macro_block_count - 1); - ptr->IMGREG3 = 0; - ptr->IMGREG[0] = JPEG_IMGREG_NBLOCK_SET(hy * vy - 1); - if (format == JPEG_SUPPORTED_FORMAT_400) { - ptr->IMGREG[1] = 0; - ptr->IMGREG[2] = 0; - } else { - ptr->IMGREG[1] = JPEG_IMGREG_NBLOCK_SET(hc * vc - 1) - | JPEG_IMGREG_QT_SET(1) - | JPEG_IMGREG_HA_SET(1) - | JPEG_IMGREG_HD_SET(1); - ptr->IMGREG[2] = JPEG_IMGREG_NBLOCK_SET(hc * vc - 1) - | JPEG_IMGREG_QT_SET(1) - | JPEG_IMGREG_HA_SET(1) - | JPEG_IMGREG_HD_SET(1); - } - ptr->IMGREG[3] = 0; -} - -hpm_stat_t jpeg_start_encode(JPEG_Type *ptr, jpeg_job_config_t *config) -{ - uint32_t macro_block_count; - uint32_t macro_block_bytes; - uint32_t total_bytes; - jpeg_sampling_t *sampling; - - if (!jpeg_is_valid_size(config->jpeg_format, config->width_in_pixel, config->height_in_pixel)) { - return status_invalid_argument; - } - - jpeg_disable(ptr); - jpeg_software_reset(ptr); - - sampling = (jpeg_sampling_t *)&jpeg_supported_sampling[config->jpeg_format]; - macro_block_count = jpeg_calculate_macro_block_count(config->width_in_pixel, config->height_in_pixel, sampling); - macro_block_bytes = (JPEG_HY(sampling) * JPEG_VY(sampling) - + 2 * JPEG_HC(sampling) * JPEG_VC(sampling)) << 6; - total_bytes = macro_block_count * macro_block_bytes; - - /* input DMA setting */ - ptr->INDMA_MISC = JPEG_INDMA_MISC_IN_DMA_ID_SET(0) - | JPEG_INDMA_MISC_MAX_OT_SET(HPM_JPEG_DEFAULT_MAX_OT) - | JPEG_INDMA_MISC_INDMA2D_MASK - | JPEG_INDMA_MISC_IN_DMA_REQ_MASK - | JPEG_INDMA_MISC_PACK_DIR_SET(config->in_byte_order); - ptr->INDMABASE = JPEG_INDMABASE_ADDR_SET(config->in_buffer); - ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(total_bytes) - | JPEG_INDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_supported_pixel_format[config->in_pixel_format].pixel_width); - ptr->INDMA_CTRL1 = JPEG_INDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); - - ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(5) | JPEG_INXT_CMD_OP_VALID_MASK; - - /* output DMA setting */ - ptr->OUTDMA_MISC = JPEG_OUTDMA_MISC_EN_OUTCNT_MASK - | JPEG_OUTDMA_MISC_INI_OUTCNT_MASK - | JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(1) - | JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK - | JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK - | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->out_byte_order); - ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); - ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes); - ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); - - ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(5) | JPEG_ONXT_CMD_OP_VALID_MASK; - - jpeg_config_interal_regs(ptr, false, macro_block_count, config->jpeg_format); - - ptr->WIDTH = config->width_in_pixel - 1; - ptr->HEIGHT = config->height_in_pixel - 1; - - if (jpeg_need_csc(config->in_pixel_format, config->out_pixel_format)) { - if (config->enable_ycbcr) { - ptr->RGB2YUV_COEF0 = JPEG_RGB2YUV_COEF0_C0_SET(0x42) - | JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(0x80) - | JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(0x10) - | JPEG_RGB2YUV_COEF0_ENABLE_MASK - | JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK; - ptr->RGB2YUV_COEF1 = JPEG_RGB2YUV_COEF1_C1_SET(0x81) - | JPEG_RGB2YUV_COEF1_C4_SET(0x7B5); - ptr->RGB2YUV_COEF2 = JPEG_RGB2YUV_COEF2_C2_SET(0x19) - | JPEG_RGB2YUV_COEF2_C3_SET(0x7DA); - ptr->RGB2YUV_COEF3 = JPEG_RGB2YUV_COEF3_C6_SET(0x70) - | JPEG_RGB2YUV_COEF3_C5_SET(0x70); - ptr->RGB2YUV_COEF4 = JPEG_RGB2YUV_COEF4_C8_SET(0x7EE) - | JPEG_RGB2YUV_COEF4_C7_SET(0x7A2); - } else { - ptr->RGB2YUV_COEF0 = JPEG_RGB2YUV_COEF0_C0_SET(0x4D) - | JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(0) - | JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(0x0) - | JPEG_RGB2YUV_COEF0_ENABLE_MASK; - ptr->RGB2YUV_COEF1 = JPEG_RGB2YUV_COEF1_C1_SET(0x96) - | JPEG_RGB2YUV_COEF1_C4_SET(0x7B6); - ptr->RGB2YUV_COEF2 = JPEG_RGB2YUV_COEF2_C2_SET(0x1D) - | JPEG_RGB2YUV_COEF2_C3_SET(0x7DA); - ptr->RGB2YUV_COEF3 = JPEG_RGB2YUV_COEF3_C6_SET(0x9D) - | JPEG_RGB2YUV_COEF3_C5_SET(0x70); - ptr->RGB2YUV_COEF4 = JPEG_RGB2YUV_COEF4_C8_SET(0x7E6) - | JPEG_RGB2YUV_COEF4_C7_SET(0x77C); - } - } else { - ptr->RGB2YUV_COEF0 = 0x04030000; - } - - ptr->CFG = JPEG_CFG_CFG_IPATH_SEL_SET(jpeg_supported_pixel_format[config->in_pixel_format].ipath) - | JPEG_CFG_CFG_OPATH_SEL_SET(jpeg_supported_pixel_format[config->out_pixel_format].opath) - | JPEG_CFG_CLKGATE_MASK - | JPEG_CFG_JDATA_FORMAT_SET(config->jpeg_format) - | JPEG_CFG_JPEG_EN_MASK - | JPEG_CFG_START_MASK; - - return status_success; -} - - -hpm_stat_t jpeg_start_decode(JPEG_Type *ptr, - jpeg_job_config_t *config, - uint32_t length) -{ - uint32_t macro_block_count; - uint32_t macro_block_bytes; - uint32_t total_bytes; - jpeg_sampling_t *sampling; - - if (!jpeg_is_valid_size(config->jpeg_format, config->width_in_pixel, config->height_in_pixel)) { - return status_invalid_argument; - } - - jpeg_disable(ptr); - jpeg_software_reset(ptr); - - sampling = (jpeg_sampling_t *)&jpeg_supported_sampling[config->jpeg_format]; - macro_block_count = jpeg_calculate_macro_block_count(config->width_in_pixel, config->height_in_pixel, sampling); - macro_block_bytes = (JPEG_HY(sampling) * JPEG_VY(sampling) - + 2 * JPEG_HC(sampling) * JPEG_VC(sampling)) << 6; - total_bytes = macro_block_count * macro_block_bytes; - - /* input DMA setting */ - ptr->INDMA_MISC = JPEG_INDMA_MISC_IN_DMA_ID_SET(1) - | JPEG_INDMA_MISC_IN_DMA_REQ_MASK - | JPEG_INDMA_MISC_MAX_OT_SET(2) - | JPEG_INDMA_MISC_PACK_DIR_SET(config->in_byte_order); - ptr->INDMABASE = JPEG_INDMABASE_ADDR_SET(config->in_buffer); - /* TODO: check if it has to use the compressed length */ - ptr->INDMA_CTRL0 = JPEG_INDMA_CTRL0_TTLEN_SET(length); - ptr->INDMA_CTRL1 = JPEG_INDMA_CTRL1_ROWLEN_SET(length >> 16); - ptr->INXT_CMD = JPEG_INXT_CMD_ADDR_SET(5) | JPEG_INXT_CMD_OP_VALID_MASK; - - /* output DMA setting */ - ptr->OUTDMA_MISC = JPEG_OUTDMA_MISC_EN_OUTCNT_MASK - | JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(0) - | JPEG_OUTDMA_MISC_INI_OUTCNT_MASK - | JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK - | JPEG_OUTDMA_MISC_OUTDMA2D_MASK - | JPEG_OUTDMA_MISC_PACK_DIR_SET(config->out_byte_order); - ptr->OUTDMABASE = JPEG_OUTDMABASE_ADDR_SET(config->out_buffer); - ptr->OUTDMA_CTRL0 = JPEG_OUTDMA_CTRL0_TTLEN_SET(total_bytes) - | JPEG_OUTDMA_CTRL0_PITCH_SET(config->width_in_pixel * jpeg_supported_pixel_format[config->out_pixel_format].pixel_width); - ptr->OUTDMA_CTRL1 = JPEG_OUTDMA_CTRL1_ROWLEN_SET(total_bytes >> 16); - ptr->ONXT_CMD = JPEG_ONXT_CMD_ADDR_SET(5) | JPEG_ONXT_CMD_OP_VALID_MASK; - - jpeg_config_interal_regs(ptr, true, macro_block_count, config->jpeg_format); - - ptr->WIDTH = config->width_in_pixel - 1; - ptr->HEIGHT = config->height_in_pixel - 1; - - ptr->CSC_COEF0 = 0x4ab01f0 - | JPEG_CSC_COEF0_YCBCR_MODE_SET(config->enable_ycbcr) - | JPEG_CSC_COEF0_ENABLE_SET(jpeg_need_csc(config->in_pixel_format, config->out_pixel_format)); - ptr->CSC_COEF1 = 0x01980204; - ptr->CSC_COEF2 = 0x0730079C; - - ptr->CFG = JPEG_CFG_CFG_OPATH_SEL_SET(jpeg_supported_pixel_format[config->out_pixel_format].opath) - | JPEG_CFG_JDATA_FORMAT_SET(config->jpeg_format) - | JPEG_CFG_JPEG_EN_MASK - | JPEG_CFG_START_MASK - | JPEG_CFG_CLKGATE_MASK - | JPEG_CFG_MODE_MASK; - return status_success; -} - -#define JPEG_TABLE_WIDTH(x) (((x) & 0xF00000UL) >> 20) -#define JPEG_TABLE_LENGTH(x) (((x) & 0xFFFF0UL) >> 4) -#define JPEG_TABLE_TYPE(x) (((x) & 0xFUL)) -#define JPEG_TABLE_VALUE_MASK(x) (((x) == 4) ? (0xFFFFFFFFUL) : (uint32_t) ((1 << ((x) << 3)) - 1)) - -hpm_stat_t jpeg_fill_table(JPEG_Type *ptr, jpeg_table_t table, uint8_t *data, uint32_t count) -{ - uint32_t i = 0; - uint32_t width = JPEG_TABLE_WIDTH(table); - uint32_t length = JPEG_TABLE_LENGTH(table); - uint32_t type = JPEG_TABLE_TYPE(table); - uint32_t *p; - - if (length != count) { - return status_invalid_argument; - } - - ptr->BUFADDR = type << 28; - for (i = 0; i < count; i++) { - p = (uint32_t *) &data[i * width]; - ptr->BUFDATA = JPEG_BUFADDR_ADDR_SET(*p & JPEG_TABLE_VALUE_MASK(width)); - } - return status_success; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c deleted file mode 100644 index 5f4f4b3be64..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcb_drv.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_lcb_drv.h" - -void lcb_get_default_config(lcb_config_t *cfg) -{ - cfg->mode = lcb_mode_display; - cfg->rxclk_sel = lcb_rxclk_sel_phy0; - cfg->display.data_width = lcb_display_mode_data_width_24bit; - cfg->display.map = lcb_display_mode_mapping_vesa; -} - -void lcb_init(LCB_Type *ptr, lcb_config_t *cfg) -{ - uint32_t reg_val; - - if (cfg->mode == lcb_mode_display) - reg_val = (ptr->CTRL & ~(LCB_CTRL_LVDS_RXCK_SEL_MASK | - LCB_CTRL_MODE_MASK | - LCB_CTRL_DATA_WIDTH_MASK | - LCB_CTRL_BIT_MAPPING_MASK)) | - LCB_CTRL_MODE_SET(cfg->mode) | - LCB_CTRL_LVDS_RXCK_SEL_SET(cfg->rxclk_sel) | - LCB_CTRL_DATA_WIDTH_SET(cfg->display.data_width) | - LCB_CTRL_BIT_MAPPING_SET(cfg->display.map); - else - reg_val = (ptr->CTRL & ~(LCB_CTRL_LVDS_RXCK_SEL_MASK | - LCB_CTRL_MODE_MASK | - LCB_CTRL_CAM_LINK_WIDTH_MASK)) | - LCB_CTRL_MODE_SET(cfg->mode) | - LCB_CTRL_LVDS_RXCK_SEL_SET(cfg->rxclk_sel) | - LCB_CTRL_CAM_LINK_WIDTH_SET(cfg->cam_link.data_width); - - ptr->CTRL = reg_val; -} - -void lcb_get_phy_clk_lane_default_config(lcb_lvds_phy_clk_lane_config_t *cfg) -{ - cfg->rterm = lcb_lvds_phy_rterm_100_ohm; - cfg->min_adj = lcb_lvds_phy_dll_delay_adj_min_freq_70_110mhz; - cfg->dll_tuning_int = 0x1FFU; -} - -void lcb_get_phy_data_lane_default_config(lcb_lvds_phy_data_lane_config_t *cfg) -{ - cfg->rterm = lcb_lvds_phy_rterm_100_ohm; - cfg->dline_adj = 0x41; -} - -void lcb_lvds_phy0_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id) -{ - ptr->PHY_D_CTRL[lane_id] = (ptr->PHY_D_CTRL[lane_id] & ~(LCB_PHY_D_CTRL_RX_RTERM_MASK)) | - LCB_PHY_D_CTRL_RX_RTERM_SET(cfg->rterm); - - if (lane_id == lcb_lvds_phy_data_lane_id_0) - ptr->PHY_ADJ_CTRL[0] = (ptr->PHY_ADJ_CTRL[0] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK)) | - LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(cfg->dline_adj); - else if (lane_id == lcb_lvds_phy_data_lane_id_1) - ptr->PHY_ADJ_CTRL[0] = (ptr->PHY_ADJ_CTRL[0] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK)) | - LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(cfg->dline_adj); -} - -void lcb_lvds_phy0_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg) -{ - ptr->PHY_CK_CTRL[0] = (ptr->PHY_CK_CTRL[0] & ~(LCB_PHY_CK_CTRL_RX_RTERM_MASK | 0x0001)) | - LCB_PHY_CK_CTRL_RX_RTERM_SET(cfg->rterm) | - (uint32_t)cfg->min_adj; - - ptr->PHY_ADJ_CTRL[0] = (ptr->PHY_ADJ_CTRL[0] & ~(LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK)) | - LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(cfg->dll_tuning_int); -} - -void lcb_lvds_phy1_data_lane_config(LCB_Type *ptr, lcb_lvds_phy_data_lane_config_t *cfg, lcb_lvds_phy_data_lane_id_t lane_id) -{ - ptr->PHY_D_CTRL[lane_id + 2] = (ptr->PHY_D_CTRL[lane_id + 2] & ~(LCB_PHY_D_CTRL_RX_RTERM_MASK)) | - LCB_PHY_D_CTRL_RX_RTERM_SET(cfg->rterm); - - if (lane_id == lcb_lvds_phy_data_lane_id_0) - ptr->PHY_ADJ_CTRL[1] = (ptr->PHY_ADJ_CTRL[1] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK)) | - LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(cfg->dline_adj); - else if (lane_id == lcb_lvds_phy_data_lane_id_1) - ptr->PHY_ADJ_CTRL[1] = (ptr->PHY_ADJ_CTRL[1] & ~(LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK)) | - LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(cfg->dline_adj); -} - -void lcb_lvds_phy1_clk_lane_config(LCB_Type *ptr, lcb_lvds_phy_clk_lane_config_t *cfg) -{ - ptr->PHY_CK_CTRL[1] = (ptr->PHY_CK_CTRL[1] & ~(LCB_PHY_CK_CTRL_RX_RTERM_MASK | 0x0001)) | - LCB_PHY_CK_CTRL_RX_RTERM_SET(cfg->rterm) | - (uint32_t)cfg->min_adj; - - ptr->PHY_ADJ_CTRL[1] = (ptr->PHY_ADJ_CTRL[1] & ~(LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK)) | - LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(cfg->dll_tuning_int); -} - -void lcb_lvds_phy0_poweron(LCB_Type *ptr) -{ - ptr->PHY_POW_CTRL[0] &= ~(LCB_PHY_POW_CTRL_IDDQ_EN_MASK | - LCB_PHY_POW_CTRL_RXCK_PD_MASK | - LCB_PHY_POW_CTRL_RX1_PD_MASK | - LCB_PHY_POW_CTRL_RX0_PD_MASK); -} - -void lcb_lvds_phy1_poweron(LCB_Type *ptr) -{ - ptr->PHY_POW_CTRL[1] &= ~(LCB_PHY_POW_CTRL_IDDQ_EN_MASK | - LCB_PHY_POW_CTRL_RXCK_PD_MASK | - LCB_PHY_POW_CTRL_RX1_PD_MASK | - LCB_PHY_POW_CTRL_RX0_PD_MASK); -} - -void lcb_lvds_phy0_powerdown(LCB_Type *ptr) -{ - ptr->PHY_POW_CTRL[0] |= (LCB_PHY_POW_CTRL_IDDQ_EN_MASK | - LCB_PHY_POW_CTRL_RXCK_PD_MASK | - LCB_PHY_POW_CTRL_RX1_PD_MASK | - LCB_PHY_POW_CTRL_RX0_PD_MASK); -} - -void lcb_lvds_phy1_powerdown(LCB_Type *ptr) -{ - ptr->PHY_POW_CTRL[1] |= (LCB_PHY_POW_CTRL_IDDQ_EN_MASK | - LCB_PHY_POW_CTRL_RXCK_PD_MASK | - LCB_PHY_POW_CTRL_RX1_PD_MASK | - LCB_PHY_POW_CTRL_RX0_PD_MASK); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c deleted file mode 100644 index 6ce29f861a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lcdc_drv.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_lcdc_drv.h" - -#define LCDC_FIFO_THRESHOLD (0x70) - -static uint32_t lcdc_pixel_format(display_pixel_format_t format) -{ - switch (format) { - case display_pixel_format_argb8888: - return 9; - case display_pixel_format_rgb565: - return 4; - case display_pixel_format_yuv422: - return 7; - case display_pixel_format_ycbcr422: - return 7; - case display_pixel_format_y8: - return 0xb; - case display_pixel_format_raw8: - return 0xb; - default: - return 9; - } -} - -/*! - * @brief Get LCDC byteorder value. - * - * @param byteorder Dispaly byteorder value. - * @return LCDC byteorder value. - */ -static uint8_t lcdc_byteorder(display_byteorder_t byteorder) -{ - switch (byteorder) { - case display_byteorder_a3a2a1a0: /* LSB */ - return 0; - case display_byteorder_a0a1a2a3: /* MSB */ - return 1; - default: - return 0; - } -} - -void lcdc_get_default_layer_config(LCDC_Type *ptr, lcdc_layer_config_t *layer, display_pixel_format_t pixel_format, uint8_t layer_index) -{ - (void) ptr; - layer->max_bytes = lcdc_layer_max_bytes_64; - /* different layer has different max_ot configuration */ - if (layer_index < LCDC_SOC_MAX_CSC_LAYER_COUNT) { - layer->max_ot = 0; - } else { - layer->max_ot = 2; - } - layer->byteorder = display_byteorder_a3a2a1a0; - if (display_pixel_format_is_yuv_format(pixel_format)) { - layer->yuv = display_yuv_mode_422_y1u1y2v1; /* If YUV format, change byte sequence to YUYV */ - } else { - layer->yuv = display_yuv_mode_422_u1y1v1y2; /* Not change byte sequence */ - } - layer->pixel_format = pixel_format; - - layer->alphablend.src_alpha = 0; - layer->alphablend.dst_alpha = 0; - layer->alphablend.src_alpha_op = display_alpha_op_invalid; - layer->alphablend.dst_alpha_op = display_alpha_op_invalid; - layer->alphablend.mode = display_alphablend_mode_clear; - layer->stride = 0; - - switch (pixel_format) { - case display_pixel_format_yuv422: - layer->csc_config.enable = true; - layer->csc_config.ycbcr_mode = false; - layer->csc_config.yuv2rgb_coef.c0 = 0x100; - layer->csc_config.yuv2rgb_coef.uv_offset = 0; - layer->csc_config.yuv2rgb_coef.y_offset = 0; - layer->csc_config.yuv2rgb_coef.c1 = 0x123; - layer->csc_config.yuv2rgb_coef.c2 = 0x76B; - layer->csc_config.yuv2rgb_coef.c3 = 0x79C; - layer->csc_config.yuv2rgb_coef.c4 = 0x208; - break; - case display_pixel_format_ycbcr422: - layer->csc_config.enable = true; - layer->csc_config.ycbcr_mode = true; - layer->csc_config.yuv2rgb_coef.c0 = 0x12A; - layer->csc_config.yuv2rgb_coef.uv_offset = 0x180; - layer->csc_config.yuv2rgb_coef.y_offset = 0x1F0; - layer->csc_config.yuv2rgb_coef.c1 = 0x198; - layer->csc_config.yuv2rgb_coef.c2 = 0x730; - layer->csc_config.yuv2rgb_coef.c3 = 0x79C; - layer->csc_config.yuv2rgb_coef.c4 = 0x204; - break; - default: - layer->csc_config.enable = false; - layer->csc_config.ycbcr_mode = false; - layer->csc_config.yuv2rgb_coef.c0 = 0; - layer->csc_config.yuv2rgb_coef.uv_offset = 0; - layer->csc_config.yuv2rgb_coef.y_offset = 0; - layer->csc_config.yuv2rgb_coef.c1 = 0; - layer->csc_config.yuv2rgb_coef.c2 = 0; - layer->csc_config.yuv2rgb_coef.c3 = 0; - layer->csc_config.yuv2rgb_coef.c4 = 0; - break; - } -} - -void lcdc_get_default_config(LCDC_Type *ptr, lcdc_config_t *config) -{ - (void) ptr; - config->resolution_x = 480; - config->resolution_y = 272; - config->hsync.front_porch_pulse = 40; - config->hsync.back_porch_pulse = 50; - config->hsync.pulse_width = 30; - config->vsync.front_porch_pulse = 20; - config->vsync.back_porch_pulse = 20; - config->vsync.pulse_width = 10; - config->background.u = 0x0; - - config->control.display_mode = lcdc_display_mode_normal; - config->control.line_pattern = lcdc_line_pattern_rgb; - config->control.invert_pixel_clock = false; - config->control.invert_pixel_data = false; - config->control.invert_href = false; - config->control.invert_vsync = false; - config->control.invert_hsync = false; -} - -void lcdc_reset_register_values(LCDC_Type *ptr) -{ - uint8_t i = 0; - - lcdc_turn_off_display(ptr); - - ptr->DISP_WN_SIZE = 0; - ptr->INT_EN = 0; - ptr->ST = 0xFFFFFFFFU; - ptr->DMA_ST = 0xFFFFFFFFU; - ptr->VSYNC_PARA = 0x00C01803U; - ptr->HSYNC_PARA = 0x00C01803U; - - for (i = 0; i < LCDC_SOC_MAX_LAYER_COUNT; i++) { - ptr->LAYER[i].LAYCTRL = 0; - ptr->LAYER[i].ALPHAS = 0; - ptr->LAYER[i].LAYSIZE = 0; - ptr->LAYER[i].LAYPOS = 0; - ptr->LAYER[i].START0 = 0; - ptr->LAYER[i].LINECFG = 0; - ptr->LAYER[i].BG_CL = 0; - } - - for (i = 0; i < LCDC_SOC_MAX_CSC_LAYER_COUNT; i++) { - ptr->LAYER[i].CSC_COEF0 = 0; - ptr->LAYER[i].CSC_COEF1 = 0; - ptr->LAYER[i].CSC_COEF2 = 0; - } -} - -void lcdc_init(LCDC_Type *ptr, lcdc_config_t *config) -{ - lcdc_reset_register_values(ptr); - - ptr->DISP_WN_SIZE = LCDC_DISP_WN_SIZE_X_SET(config->resolution_x) | - LCDC_DISP_WN_SIZE_Y_SET(config->resolution_y); - ptr->HSYNC_PARA = - LCDC_HSYNC_PARA_FP_SET(config->hsync.front_porch_pulse) - | LCDC_HSYNC_PARA_BP_SET(config->hsync.back_porch_pulse) - | LCDC_HSYNC_PARA_PW_SET(config->hsync.pulse_width); - ptr->BGND_CL = LCDC_BGND_CL_B_SET(config->background.b) - | LCDC_BGND_CL_G_SET(config->background.g) - | LCDC_BGND_CL_R_SET(config->background.r); - ptr->VSYNC_PARA = - LCDC_VSYNC_PARA_FP_SET(config->vsync.front_porch_pulse) - | LCDC_VSYNC_PARA_BP_SET(config->vsync.back_porch_pulse) - | LCDC_VSYNC_PARA_PW_SET(config->vsync.pulse_width); - ptr->TXFIFO = LCDC_TXFIFO_THRSH_SET(LCDC_FIFO_THRESHOLD); - ptr->CTRL = LCDC_CTRL_DISP_MODE_SET(config->control.display_mode) - | LCDC_CTRL_LINE_PATTERN_SET(config->control.line_pattern) - | LCDC_CTRL_INV_PXDATA_SET(config->control.invert_pixel_data) - | LCDC_CTRL_INV_PXCLK_SET(config->control.invert_pixel_clock) - | LCDC_CTRL_INV_HREF_SET(config->control.invert_href) - | LCDC_CTRL_INV_VSYNC_SET(config->control.invert_vsync) - | LCDC_CTRL_INV_HSYNC_SET(config->control.invert_hsync); -} - -hpm_stat_t lcdc_config_layer(LCDC_Type *ptr, - uint8_t layer_index, - lcdc_layer_config_t *layer, - bool enable_layer) -{ - uint8_t byteorder; - uint32_t pitch; - uint32_t format; - uint32_t ctrl = ptr->LAYER[layer_index].LAYCTRL; - - if ((!LCDC_SOC_LAYER_SUPPORTS_CSC(layer_index) && layer->csc_config.enable) - || (!LCDC_SOC_LAYER_SUPPORTS_YUV(layer_index) - && (display_pixel_format_is_yuv_format(layer->pixel_format)))) { - return status_lcdc_layer_not_supported; - } - - ptr->LAYER[layer_index].LAYSIZE = - LCDC_LAYER_LAYSIZE_HEIGHT_SET(layer->height) - | LCDC_LAYER_LAYSIZE_WIDTH_SET(layer->width); - ptr->LAYER[layer_index].LAYPOS = - LCDC_LAYER_LAYPOS_X_SET(layer->position_x) - | LCDC_LAYER_LAYPOS_Y_SET(layer->position_y); - ptr->LAYER[layer_index].START0 = LCDC_LAYER_START0_ADDR0_SET((uint32_t)layer->buffer); - ptr->LAYER[layer_index].ALPHAS = LCDC_LAYER_ALPHAS_LOCD_SET(layer->alphablend.src_alpha) - | LCDC_LAYER_ALPHAS_IND_SET(layer->alphablend.dst_alpha); - - pitch = layer->stride > 0 ? layer->stride : display_get_pitch_length_in_byte(layer->pixel_format, layer->width); - ptr->LAYER[layer_index].LINECFG = LCDC_LAYER_LINECFG_MPT_SIZE_SET(layer->max_bytes) - | LCDC_LAYER_LINECFG_MAX_OT_SET(layer->max_ot) - | LCDC_LAYER_LINECFG_PITCH_SET(pitch); - ptr->LAYER[layer_index].BG_CL = LCDC_LAYER_BG_CL_ARGB_SET(layer->background.u); - - ptr->LAYER[layer_index].CSC_COEF0 = - LCDC_LAYER_CSC_COEF0_ENABLE_SET(layer->csc_config.enable) - | LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(layer->csc_config.ycbcr_mode) - | LCDC_LAYER_CSC_COEF0_C0_SET(layer->csc_config.yuv2rgb_coef.c0) - | LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(layer->csc_config.yuv2rgb_coef.uv_offset) - | LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(layer->csc_config.yuv2rgb_coef.y_offset); - ptr->LAYER[layer_index].CSC_COEF1 = - LCDC_LAYER_CSC_COEF1_C1_SET(layer->csc_config.yuv2rgb_coef.c1) - | LCDC_LAYER_CSC_COEF1_C4_SET(layer->csc_config.yuv2rgb_coef.c4); - ptr->LAYER[layer_index].CSC_COEF2 = - LCDC_LAYER_CSC_COEF2_C2_SET(layer->csc_config.yuv2rgb_coef.c2) - | LCDC_LAYER_CSC_COEF2_C3_SET(layer->csc_config.yuv2rgb_coef.c3); - - /* bit18 is reserved but has to be set to 1 */ - ctrl |= 1 << 18; - - byteorder = lcdc_byteorder(layer->byteorder); - format = lcdc_pixel_format(layer->pixel_format); - ctrl = (ctrl & ~(LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK - | LCDC_LAYER_LAYCTRL_AB_MODE_MASK - | LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK - | LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK - | LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK)) - | LCDC_LAYER_LAYCTRL_PACK_DIR_SET(byteorder) - | LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(format) - | LCDC_LAYER_LAYCTRL_AB_MODE_SET(layer->alphablend.mode) - | LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(layer->alphablend.src_alpha_op) - | LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(layer->alphablend.dst_alpha_op) - | LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(layer->yuv); - - if (enable_layer) { - ctrl |= LCDC_LAYER_LAYCTRL_EN_MASK; - } - ptr->LAYER[layer_index].LAYCTRL = ctrl | LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK; - return status_success; -} - -void lcdc_turn_off_display(LCDC_Type *ptr) -{ - if (ptr->CTRL & LCDC_CTRL_DISP_ON_MASK) { - ptr->INT_EN = 0; - - /* 1. wait for current frame end */ - ptr->ST = 0xFFFFFFFF; - while ((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0) { - } - - /* 2. issue display off */ - ptr->ST = 0xFFFFFFFF; - lcdc_software_reset(ptr); - ptr->CTRL &= ~LCDC_CTRL_DISP_ON_MASK; - while ((ptr->ST & LCDC_ST_VS_BLANK_MASK) == 0) { - } - } - return; -} - -void lcdc_turn_on_display(LCDC_Type *ptr) -{ - if (!(ptr->CTRL & LCDC_CTRL_DISP_ON_MASK)) { - ptr->CTRL |= LCDC_CTRL_DISP_ON_MASK; - } -} - -void lcdc_layer_update_pixel_format(LCDC_Type *ptr, uint8_t layer_index, - uint8_t pixel_format) -{ - uint32_t pitch; - uint32_t width = (ptr->LAYER[layer_index].LAYSIZE & LCDC_LAYER_LAYSIZE_WIDTH_MASK) - >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT; - pitch = display_get_pitch_length_in_byte(pixel_format, width); - ptr->LAYER[layer_index].LINECFG = (ptr->LAYER[layer_index].LINECFG & ~LCDC_LAYER_LINECFG_PITCH_MASK) - | LCDC_LAYER_LINECFG_PITCH_SET(pitch); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c deleted file mode 100644 index 9411fb3da5d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lin_drv.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_lin_drv.h" - -#define HPM_LIN_DRV_RETRY_COUNT (50000U) - -hpm_stat_t lin_master_configure_timing(LIN_Type *ptr, lin_timing_t *timing) -{ - assert(timing->src_freq_in_hz >= 8000000U); - assert((timing->baudrate >= 1000U) && (timing->baudrate <= 20000U)); - - uint8_t prescaler, bt_mul; - uint16_t bt_div; - - /** set master mode */ - ptr->TV |= LIN_TV_MASTER_MODE_MASK; - ptr->TV |= LIN_TV_INITIAL_MODE_MASK; - ptr->TV &= ~LIN_TV_INITIAL_MODE_MASK; - - bt_mul = 20000U / timing->baudrate - 1U; - prescaler = log((timing->src_freq_in_hz / ((bt_mul + 1U) * timing->baudrate * 200U))) / log(2U) - 1U; - bt_div = timing->src_freq_in_hz / ((1U << (prescaler + 1U)) * (bt_mul + 1U) * timing->baudrate); - - if ((bt_div < 200) || (bt_div > 512)) { - return status_invalid_argument; - } - - /** src =20MHz baudrate = 19.2KHz */ - /** bt_div = 260, scaler = 1, bt_mul = 0 */ - ptr->BAUDRATE_CTL_LOW = bt_div & 0xFF; - ptr->BARDRATE_CTL_HIGH = LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(bt_div >> 8U) - | LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(bt_mul) - | LIN_BARDRATE_CTL_HIGH_PRESCL_SET(prescaler); - - return status_success; -} - -hpm_stat_t lin_slave_configure_timing(LIN_Type *ptr, uint32_t src_freq_in_hz) -{ - assert(src_freq_in_hz >= 8000000U); - - uint8_t prescaler; - uint16_t bt_div; - - /** set slave mode */ - ptr->TV &= ~LIN_TV_MASTER_MODE_MASK; - ptr->TV |= LIN_TV_INITIAL_MODE_MASK; - ptr->TV &= ~LIN_TV_INITIAL_MODE_MASK; - - prescaler = log((src_freq_in_hz / (20000U * 200U))) / log(2U) - 1U; - bt_div = src_freq_in_hz / ((1U << (prescaler + 1U)) * 20000U); - - if ((bt_div < 200) || (bt_div > 512)) { - return status_invalid_argument; - } - - /** src = 20MHz, prescaler = 1, bt_div = 250 */ - ptr->BAUDRATE_CTL_LOW = bt_div & 0xFF; - ptr->BARDRATE_CTL_HIGH = LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(bt_div >> 8U) - | LIN_BARDRATE_CTL_HIGH_PRESCL_SET(prescaler); - - return status_success; -} - -uint8_t lin_get_data_length_from_id(uint8_t id) -{ - switch (LIN_ID_DATA_LEN_GET(id)) { - case id_data_length_2bytes: - return 2; - case id_data_length_2bytes_2: - return 2; - case id_data_length_4bytes: - return 4; - case id_data_length_8bytes: - return 8; - default: - return 8; - } -} - -uint8_t lin_get_data_length(LIN_Type *ptr) -{ - uint8_t data_length = 0; - if (((ptr->DATA_LEN) & LIN_DATA_LEN_DATA_LENGTH_MASK) == LIN_DATA_LEN_DATA_LENGTH_MASK) { - data_length = lin_get_data_length_from_id(ptr->ID); - } else { - data_length = LIN_DATA_LEN_DATA_LENGTH_GET(ptr->DATA_LEN); - } - return data_length; -} - -void lin_master_transfer(LIN_Type *ptr, lin_trans_config_t *config) -{ - uint8_t data_length; - - ptr->ID = config->id; - - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(ptr->ID); - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); - } - - /** sent or receive */ - ptr->CONTROL = 0U; - if (config->transmit) { - ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; - } - - if (config->transmit) { - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATABYTE[i] = *((config->data_buff)++); - } - } - - /** start */ - ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; -} - -hpm_stat_t lin_master_sent(LIN_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length = 0; - - /** lin active */ - while (((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - ptr->ID = config->id; - - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(ptr->ID); - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); - } - - ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; - - /** load data into registers */ - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATABYTE[i] = *((config->data_buff)++); - } - - /** start */ - ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; - - /** lin complete */ - retry = 0; - while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_timeout; - } - return status_success; -} - -hpm_stat_t lin_master_receive(LIN_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length; - - /** lin active */ - while (((ptr->STATE & LIN_STATE_LIN_ACTIVE_MASK) == LIN_STATE_LIN_ACTIVE_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - ptr->ID = config->id; - - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(ptr->ID); - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); - } - - /** receive */ - ptr->CONTROL = 0U; - /** start */ - ptr->CONTROL |= LIN_CONTROL_START_REQ_MASK; - - /** waiting for receive complete */ - retry = 0; - while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_fail; - } - - /** load register data into buffer */ - for (uint8_t i = 0; i < data_length; i++) { - *((config->data_buff)++) = ptr->DATABYTE[i]; - } - - return status_success; -} - -void lin_slave_transfer(LIN_Type *ptr, lin_trans_config_t *config) -{ - uint8_t data_length; - - /** transmit or receive */ - ptr->CONTROL = LIN_CONTROL_TRANSMIT_SET(config->transmit); - - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(ptr->ID); - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); - } - - if (config->transmit) { - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATABYTE[i] = *((config->data_buff)++); - } - } - - /** data ack */ - ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; -} - -hpm_stat_t lin_slave_sent(LIN_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length; - - /** lin data_req */ - /** lin active? */ - while (((ptr->STATE & LIN_STATE_DATA_REQ_MASK) == LIN_STATE_DATA_REQ_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - /** transmit */ - ptr->CONTROL = LIN_CONTROL_TRANSMIT_MASK; - - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(ptr->ID); - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); - } - - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATABYTE[i] = *((config->data_buff)++); - } - - /** data ack */ - ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; - - /** lin complete */ - retry = 0; - while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_timeout; - } - return status_success; -} - -hpm_stat_t lin_slave_receive(LIN_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length; - - /** lin data_req */ - while (((ptr->STATE & LIN_STATE_DATA_REQ_MASK) == LIN_STATE_DATA_REQ_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - /** receive */ - ptr->CONTROL = 0U; - - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(ptr->ID); - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN = LIN_DATA_LEN_ENH_CHECK_SET(config->enhanced_checksum) | LIN_DATA_LEN_DATA_LENGTH_SET(data_length); - } - - /** data ack */ - ptr->CONTROL |= LIN_CONTROL_DATA_ACK_MASK; - - /** lin complete */ - retry = 0; - while (!((ptr->STATE & LIN_STATE_COMPLETE_MASK) == LIN_STATE_COMPLETE_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_timeout; - } - - for (uint8_t i = 0; i < data_length; i++) { - *((config->data_buff)++) = ptr->DATABYTE[i]; - } - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c deleted file mode 100644 index ea299d68372..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_linv2_drv.c +++ /dev/null @@ -1,373 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_linv2_drv.h" - -#define HPM_LIN_DRV_RETRY_COUNT (50000U) - -hpm_stat_t lin_master_configure_timing(LINV2_Type *ptr, lin_timing_t *timing) -{ - assert(timing->src_freq_in_hz >= 8000000U); - assert((timing->baudrate >= 1000U) && (timing->baudrate <= 20000U)); - - uint8_t prescaler, bt_mul; - uint16_t bt_div; - - /** set master mode */ - ptr->TIMING_CONTROL = LINV2_TIMING_CONTROL_MASTER_MODE_MASK; - ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; - ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; - - bt_mul = 20000U / timing->baudrate - 1U; - prescaler = (uint8_t)(log((timing->src_freq_in_hz / ((bt_mul + 1U) * timing->baudrate * 200U))) / log(2U) - 1U); - bt_div = timing->src_freq_in_hz / ((1U << (prescaler + 1U)) * (bt_mul + 1U) * timing->baudrate); - - if ((bt_div < 200) || (bt_div > 512)) { - return status_invalid_argument; - } - - /** src =20MHz baudrate = 19.2KHz */ - /** bt_div = 260, scaler = 1, bt_mul = 0 */ - ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_BT_DIV_SET(bt_div) - | LINV2_TIMING_CONTROL_BT_MUL_SET(bt_mul) - | LINV2_TIMING_CONTROL_PRESCL_SET(prescaler); - - return status_success; -} - -hpm_stat_t lin_slave_configure_timing(LINV2_Type *ptr, uint32_t src_freq_in_hz) -{ - assert(src_freq_in_hz >= 8000000U); - - uint8_t prescaler; - uint16_t bt_div; - - /** set slave mode, clean bt_div, bit_mul, prescl */ - ptr->TIMING_CONTROL = 0; - ptr->TIMING_CONTROL |= LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; - ptr->TIMING_CONTROL &= ~LINV2_TIMING_CONTROL_LIN_INITIAL_MASK; - - prescaler = (uint8_t)(log((src_freq_in_hz / (20000U * 200U))) / log(2U) - 1U); - bt_div = src_freq_in_hz / ((1U << (prescaler + 1U)) * 20000U); - - if ((bt_div < 200) || (bt_div >= 512)) { - return status_invalid_argument; - } - - /** src = 20MHz, prescaler = 1, bt_div = 250 */ - /* TODO: set wakeup_len */ - ptr->TIMING_CONTROL = LINV2_TIMING_CONTROL_BT_DIV_SET(bt_div) - | LINV2_TIMING_CONTROL_PRESCL_SET(prescaler); - - /* disable break_err detect */ - ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK; - - return status_success; -} - -uint8_t lin_get_data_length_from_id(uint8_t id) -{ - switch (LIN_ID_DATA_LEN_GET(id)) { - case id_data_length_2bytes: - return 2; - case id_data_length_2bytes_2: - return 2; - case id_data_length_4bytes: - return 4; - case id_data_length_8bytes: - return 8; - default: - return 8; - } -} - -uint8_t lin_get_data_length(LINV2_Type *ptr) -{ - uint8_t data_length = 0; - if (((ptr->DATA_LEN_ID) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) == LINV2_DATA_LEN_ID_DATA_LEN_MASK) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - } else { - data_length = LINV2_DATA_LEN_ID_DATA_LEN_GET(ptr->DATA_LEN_ID); - } - return data_length; -} - -void lin_master_transfer(LINV2_Type *ptr, lin_trans_config_t *config) -{ - uint8_t data_length; - - /** config id */ - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); - } else { - data_length = config->data_length; - ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); - } - - /** sent or receive */ - ptr->CONTROL_STATUS = 0U; - if (config->transmit) { - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_TRANSMIT_MASK; - } - - if (config->transmit) { - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATA_BYTE[i] = *((config->data_buff)++); - } - } - - /** start */ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; -} - -hpm_stat_t lin_master_sent(LINV2_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length = 0; - - /** wait for lin inactive */ - while (lin_is_active(ptr)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - /** config id */ - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); - } else { - data_length = config->data_length; - ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); - } - - ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_TRANSMIT_MASK; - - /** load data into registers */ - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATA_BYTE[i] = *((config->data_buff)++); - } - - /** start */ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; - - /** waiting for lin complete */ - retry = 0; - while (!lin_is_complete(ptr)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_timeout; - } - return status_success; -} - -hpm_stat_t lin_master_receive(LINV2_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length; - - /** waiting for lin inactive */ - while (lin_is_active(ptr)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - /** config id */ - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK | LINV2_DATA_LEN_ID_ID_SET(config->id); - } else { - data_length = config->data_length; - ptr->DATA_LEN_ID = LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length) | LINV2_DATA_LEN_ID_ID_SET(config->id); - } - - /** receive */ - ptr->CONTROL_STATUS = 0U; - /** start */ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_START_REQ_MASK; - - /** waiting for receive complete */ - retry = 0; - while (!lin_is_complete(ptr)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_fail; - } - - /** load register data into buffer */ - for (uint8_t i = 0; i < data_length; i++) { - *((config->data_buff)++) = ptr->DATA_BYTE[i]; - } - - return status_success; -} - -void lin_slave_transfer(LINV2_Type *ptr, lin_trans_config_t *config) -{ - uint8_t data_length; - - /** transmit or receive */ - ptr->CONTROL_STATUS &= ~LINV2_CONTROL_STATUS_TRANSMIT_MASK; - if (config->transmit) { - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_TRANSMIT_MASK; - } - - /* clean enh_check and data_len */ - ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); - } - - if (config->transmit) { - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATA_BYTE[i] = *((config->data_buff)++); - } - } - - /** data ack */ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; -} - -hpm_stat_t lin_slave_sent(LINV2_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length; - - /** waiting for lin data_req */ - while (!((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_DATA_REQ_MASK) == LINV2_CONTROL_STATUS_DATA_REQ_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - /** transmit */ - ptr->CONTROL_STATUS = LINV2_CONTROL_STATUS_TRANSMIT_MASK; - - /* clean enh_check and data_len */ - ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); - } - - for (uint8_t i = 0; i < data_length; i++) { - ptr->DATA_BYTE[i] = *((config->data_buff)++); - } - - /** data ack */ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; - - /** waiting for lin complete */ - retry = 0; - while (!lin_is_complete(ptr)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_timeout; - } - return status_success; -} - -hpm_stat_t lin_slave_receive(LINV2_Type *ptr, lin_trans_config_t *config) -{ - uint32_t retry = 0; - uint8_t data_length; - - /** waiting for lin data_req */ - while (!((ptr->CONTROL_STATUS & LINV2_CONTROL_STATUS_DATA_REQ_MASK) == LINV2_CONTROL_STATUS_DATA_REQ_MASK)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - /** receive */ - ptr->CONTROL_STATUS = 0U; - - /* clean enh_check and data_len */ - ptr->DATA_LEN_ID &= ~(LINV2_DATA_LEN_ID_ENH_CHECK_MASK | LINV2_DATA_LEN_ID_DATA_LEN_MASK); - if (config->data_length_from_id) { - data_length = lin_get_data_length_from_id(lin_get_id(ptr)); - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_MASK; - } else { - data_length = config->data_length; - ptr->DATA_LEN_ID |= LINV2_DATA_LEN_ID_ENH_CHECK_SET(config->enhanced_checksum) | LINV2_DATA_LEN_ID_DATA_LEN_SET(data_length); - } - - /** data ack */ - ptr->CONTROL_STATUS |= LINV2_CONTROL_STATUS_DATA_ACK_MASK; - - /** waiting for lin complete */ - retry = 0; - while (!lin_is_complete(ptr)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT * 8) { - return status_timeout; - } - - for (uint8_t i = 0; i < data_length; i++) { - *((config->data_buff)++) = ptr->DATA_BYTE[i]; - } - - return status_success; -} - -void lin_slave_dma_transfer(LINV2_Type *ptr, lin_trans_config_t *config) -{ - ptr->DMA_CONTROL = LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK - | LINV2_DMA_CONTROL_DMA_REQ_ID_SET(config->id) - | LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(config->transmit) - | LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(config->data_length) - | LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(config->enhanced_checksum); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c deleted file mode 100644 index d6bf1d4509e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lobs_drv.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include -#include "hpm_lobs_drv.h" - -void lobs_deinit(LOBS_Type *lobs) -{ - lobs_set_state_enable(lobs, lobs_state_0, false); - lobs_set_state_enable(lobs, lobs_state_1, false); - lobs_set_state_enable(lobs, lobs_state_2, false); - lobs_set_state_enable(lobs, lobs_state_3, false); - lobs_set_state_enable(lobs, lobs_state_4, false); - lobs_set_pre_trig_enable(lobs, false); - lobs_set_enable(lobs, false); -} - -void lobs_ctrl_config(LOBS_Type *lobs, lobs_ctrl_config_t *config) -{ - uint8_t burst_len; - - assert((config->start_addr & 0x03) == 0); - assert((config->end_addr & 0x03) == 0); - - if (config->sample_rate == lobs_sample_1_per_5) { - burst_len = lobs_burst_16; - } else if (config->sample_rate == lobs_sample_1_per_6) { - burst_len = lobs_burst_8; - } else { - burst_len = lobs_burst_4; - } - lobs->STREAMCTRL = LOBS_STREAMCTRL_SEL_SET(config->group_mode) - | LOBS_STREAMCTRL_SAMPLE_SET(config->sample_rate) - | LOBS_STREAMCTRL_BURST_SET(burst_len); - lobs->STARTADDR = config->start_addr; - lobs->ENDADDR = config->end_addr - 4u; -} - -void lobs_two_group_mode_config(LOBS_Type *lobs, lobs_two_group_sel_t group, lobs_two_group_mode_config_t *config) -{ - assert(config->sig_group_num < 12); - - if (group == lobs_two_group_1) { - lobs->GRPSELA = (lobs->GRPSELA & ~LOBS_GRPSELA_NUM1_MASK) | LOBS_GRPSELA_NUM1_SET(config->sig_group_num); - lobs->SIGSELA1 = LOBS_SIGSELA1_NUM1_SET(config->sample_sig_bit[0]) | LOBS_SIGSELA1_NUM2_SET(config->sample_sig_bit[1]) - | LOBS_SIGSELA1_NUM3_SET(config->sample_sig_bit[2]) | LOBS_SIGSELA1_NUM4_SET(config->sample_sig_bit[3]); - lobs->SIGENA = (lobs->SIGENA & ~LOBS_SIGENA_EN1_MASK) - | LOBS_SIGENA_EN1_SET((config->sample_sig_en[0]) | (config->sample_sig_en[1] << 1) - | (config->sample_sig_en[2] << 2) | (config->sample_sig_en[3] << 3)); - lobs->GRPENA = (lobs->GRPENA & ~LOBS_GRPENA_EN1_MASK) | LOBS_GRPENA_EN1_SET(config->group_enable); - } else if (group == lobs_two_group_2) { - lobs->GRPSELA = (lobs->GRPSELA & ~LOBS_GRPSELA_NUM2_MASK) | LOBS_GRPSELA_NUM2_SET(config->sig_group_num); - lobs->SIGSELA2 = LOBS_SIGSELA2_NUM1_SET(config->sample_sig_bit[0]) | LOBS_SIGSELA2_NUM2_SET(config->sample_sig_bit[1]) - | LOBS_SIGSELA2_NUM3_SET(config->sample_sig_bit[2]) | LOBS_SIGSELA2_NUM4_SET(config->sample_sig_bit[3]); - lobs->SIGENA = (lobs->SIGENA & ~LOBS_SIGENA_EN2_MASK) - | LOBS_SIGENA_EN2_SET((config->sample_sig_en[0]) | (config->sample_sig_en[1] << 1) - | (config->sample_sig_en[2] << 2) | (config->sample_sig_en[3] << 3)); - lobs->GRPENA = (lobs->GRPENA & ~LOBS_GRPENA_EN2_MASK) | LOBS_GRPENA_EN2_SET(config->group_enable); - } else { - ; - } -} - -void lobs_state_config(LOBS_Type *lobs, lobs_state_sel_t state, lobs_state_config_t *config) -{ - uint8_t cmp_reg_index; - uint8_t cmp_bit_index; - uint8_t sample_rate; - - assert(config->sig_group_num < 12); - assert((config->cmp_sig_en[0] && (config->cmp_sig_bit[0] < 128)) || (!config->cmp_sig_en[0])); - assert((config->cmp_sig_en[1] && (config->cmp_sig_bit[1] < 128)) || (!config->cmp_sig_en[1])); - assert((config->cmp_sig_en[2] && (config->cmp_sig_bit[2] < 128)) || (!config->cmp_sig_en[2])); - assert((config->cmp_sig_en[3] && (config->cmp_sig_bit[3] < 128)) || (!config->cmp_sig_en[3])); - assert(((config->cmp_mode == lobs_cnt_cmp_mode) && (config->state_chg_condition == lobs_cnt_matched)) || (config->cmp_mode != lobs_cnt_cmp_mode)); - - lobs->STATE[state].SIGSEL = LOBS_STATE_SIGSEL_EN_SET(1u << (config->sig_group_num)); - lobs->STATE[state].TRIGCTRL = LOBS_STATE_TRIGCTRL_TRACE_SET(2) - | LOBS_STATE_TRIGCTRL_COMPSEL_SET(config->cmp_mode) - | LOBS_STATE_TRIGCTRL_COMP_SET(config->state_chg_condition); - lobs->STATE[state].NEXTSTATE = LOBS_STATE_NEXTSTATE_NEXTSTATE_SET(config->next_state); - - sample_rate = LOBS_STREAMCTRL_SAMPLE_GET(lobs->STREAMCTRL); - if (sample_rate == lobs_sample_1_per_7) { - lobs->STATE[state].COUNTCOMP = LOBS_STATE_COUNTCOMP_VALUE_SET(config->cmp_counter * 7u); - } else if (sample_rate == lobs_sample_1_per_6) { - lobs->STATE[state].COUNTCOMP = LOBS_STATE_COUNTCOMP_VALUE_SET(config->cmp_counter * 6u); - } else if (sample_rate == lobs_sample_1_per_5) { - lobs->STATE[state].COUNTCOMP = LOBS_STATE_COUNTCOMP_VALUE_SET(config->cmp_counter * 5u); - } else { - assert(0); - } - - lobs->STATE[state].SIGMASK = LOBS_STATE_SIGMASK_NUM0_SET(config->cmp_sig_bit[0]) | LOBS_STATE_SIGMASK_NUM1_SET(config->cmp_sig_bit[1]) - | LOBS_STATE_SIGMASK_NUM2_SET(config->cmp_sig_bit[2]) | LOBS_STATE_SIGMASK_NUM3_SET(config->cmp_sig_bit[3]); - lobs->STATE[state].COMPEN = LOBS_STATE_COMPEN_EN_SET((config->cmp_sig_en[0]) | (config->cmp_sig_en[1] << 1) - | (config->cmp_sig_en[2] << 2) | (config->cmp_sig_en[3] << 3)); - lobs->STATE[state].EXTMASK = 0; - lobs->STATE[state].EXTCOMP = 0; - - for (uint8_t i = 0; i < 4; i++) { - if (config->cmp_sig_en[i]) { - cmp_reg_index = config->cmp_sig_bit[i] / 32; - cmp_bit_index = config->cmp_sig_bit[i] % 32; - if (cmp_reg_index == 0) { - lobs->STATE[state].SIGCOMP0 = (lobs->STATE[state].SIGCOMP0 & ~(1u << cmp_bit_index)) | (config->cmp_golden_value[i] << cmp_bit_index); - } else if (cmp_reg_index == 1) { - lobs->STATE[state].SIGCOMP1 = (lobs->STATE[state].SIGCOMP1 & ~(1u << cmp_bit_index)) | (config->cmp_golden_value[i] << cmp_bit_index); - } else if (cmp_reg_index == 2) { - lobs->STATE[state].SIGCOMP2 = (lobs->STATE[state].SIGCOMP2 & ~(1u << cmp_bit_index)) | (config->cmp_golden_value[i] << cmp_bit_index); - } else if (cmp_reg_index == 3) { - lobs->STATE[state].SIGCOMP3 = (lobs->STATE[state].SIGCOMP3 & ~(1u << cmp_bit_index)) | (config->cmp_golden_value[i] << cmp_bit_index); - } else { - ; - } - } - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c deleted file mode 100644 index 4cd59fa20a0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_lvb_drv.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_lvb_drv.h" - -void lvb_get_default_config(lvb_config_t *cfg) -{ - cfg->split_ch_is_reverse = false; - cfg->split_ch_data_is_unaligned = false; - cfg->split_hswhbp_width_is_even = true; - cfg->split_mode_en = false; - cfg->di0_vsync_polarity = lvb_di_vsync_polarity_active_high; - cfg->di1_vsync_polarity = lvb_di_vsync_polarity_active_high; - cfg->txclk_shift = lvb_txclk_shift_1100011; -} - -void lvb_init(LVB_Type *ptr, lvb_config_t *cfg) -{ - ptr->CTRL = (ptr->CTRL & ~(LVB_CTRL_SPLIT_CH_REVERSE_MASK | - LVB_CTRL_SPLIT_CH_MODE_MASK | - LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK | - LVB_CTRL_SPLIT_MODE_EN_MASK | - LVB_CTRL_DI1_VSYNC_POLARITY_MASK | - LVB_CTRL_DI0_VSYNC_POLARITY_MASK | - LVB_CTRL_LVDS_TXCLK_SHIFT_MASK)) | - LVB_CTRL_SPLIT_CH_REVERSE_SET(cfg->split_ch_is_reverse) | - LVB_CTRL_SPLIT_CH_MODE_SET(cfg->split_ch_data_is_unaligned) | - LVB_CTRL_SPLIT_HSWHBP_WIDTH_SET(cfg->split_hswhbp_width_is_even) | - LVB_CTRL_SPLIT_MODE_EN_SET(cfg->split_mode_en) | - LVB_CTRL_DI1_VSYNC_POLARITY_SET(cfg->di1_vsync_polarity) | - LVB_CTRL_DI0_VSYNC_POLARITY_SET(cfg->di0_vsync_polarity) | - LVB_CTRL_LVDS_TXCLK_SHIFT_SET(cfg->txclk_shift); -} - -void lvb_get_ch_default_config(lvb_ch_config_t *ch_cfg) -{ - ch_cfg->data_src = lvb_ch_data_source_di0; - ch_cfg->map = lvb_ch_mapping_vesa; -} - -void lvb_ch_config(LVB_Type *ptr, lvb_ch_num_t ch_num, lvb_ch_config_t *ch_cfg) -{ - uint32_t reg_val; - - if (ch_num == lvb_ch_num_0) { - reg_val = (ptr->CTRL & ~(LVB_CTRL_CH0_BIT_MAPPING_MASK | LVB_CTRL_CH0_SEL_MASK)) | - LVB_CTRL_CH0_BIT_MAPPING_SET(ch_cfg->map) | - LVB_CTRL_CH0_SEL_SET(ch_cfg->data_src); - } else { - reg_val = (ptr->CTRL & ~(LVB_CTRL_CH1_BIT_MAPPING_MASK | LVB_CTRL_CH1_SEL_MASK)) | - LVB_CTRL_CH1_BIT_MAPPING_SET(ch_cfg->map) | - LVB_CTRL_CH1_SEL_SET(ch_cfg->data_src); - } - - ptr->CTRL = reg_val; -} - -void lvb_ch_enable(LVB_Type *ptr, lvb_ch_num_t ch_num) -{ - if (ch_num == lvb_ch_num_0) { - ptr->CTRL |= LVB_CTRL_CH0_EN_MASK; - } else { - ptr->CTRL |= LVB_CTRL_CH1_EN_MASK; - } -} - -void lvb_ch_disable(LVB_Type *ptr, lvb_ch_num_t ch_num) -{ - if (ch_num == lvb_ch_num_0) { - ptr->CTRL &= ~LVB_CTRL_CH0_EN_MASK; - } else { - ptr->CTRL &= ~LVB_CTRL_CH1_EN_MASK; - } -} - -void lvb_lvds_phy_lane_get_default_config(lvb_lvds_phy_lane_config_t *cfg) -{ - cfg->tx_idle = false; - cfg->rterm_enable = true; - cfg->phase_sel = lvb_lvds_lane_phase_sel_4_16_ui; - cfg->amp = lvb_lvds_lane_amp_300_mv; - cfg->vcom = lvb_lvds_lane_vcom_1_2_v; - cfg->fvco_div4 = true; -} - -void lvb_lvds_phy_lane_init(LVB_Type *ptr, lvb_lvds_lane_idx_t tx_index, lvb_lvds_phy_lane_config_t *cfg) -{ - ptr->TX_PHY[tx_index].CTL0 = (ptr->TX_PHY[tx_index].CTL0 & ~(LVB_TX_PHY_CTL0_TX_IDLE_MASK | - LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK | - LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK | - LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK | - LVB_TX_PHY_CTL0_TX_VCOM_MASK | - LVB_TX_PHY_CTL0_TX_AMP_MASK)) | - (cfg->tx_idle ? LVB_TX_PHY_CTL0_TX_IDLE_MASK : 0) | - (cfg->rterm_enable ? LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK : 0) | - LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET(2) | /* only 7bit */ - LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET(cfg->phase_sel) | - LVB_TX_PHY_CTL0_TX_VCOM_SET(cfg->vcom) | - LVB_TX_PHY_CTL0_TX_AMP_SET(cfg->amp); - - if (cfg->fvco_div4) { - ptr->TX_PHY[tx_index].CTL0 |= (1ul<<7); - } else { - ptr->TX_PHY[tx_index].CTL0 &= ~(1ul<<7); - } -} - -void lvb_lvds_phy0_poweron(LVB_Type *ptr) -{ - ptr->PHY_POW_CTRL[0] = (ptr->PHY_POW_CTRL[0] & ~(LVB_PHY_POW_CTRL_TXCK_PD_MASK | - LVB_PHY_POW_CTRL_TX3_PD_MASK | LVB_PHY_POW_CTRL_TX2_PD_MASK | - LVB_PHY_POW_CTRL_TX1_PD_MASK | LVB_PHY_POW_CTRL_TX0_PD_MASK)) | - LVB_PHY_POW_CTRL_PWON_PLL_MASK; -} - -void lvb_lvds_phy1_poweron(LVB_Type *ptr) -{ - ptr->PHY_POW_CTRL[1] = (ptr->PHY_POW_CTRL[1] & ~(LVB_PHY_POW_CTRL_TXCK_PD_MASK | - LVB_PHY_POW_CTRL_TX3_PD_MASK | LVB_PHY_POW_CTRL_TX2_PD_MASK | - LVB_PHY_POW_CTRL_TX1_PD_MASK | LVB_PHY_POW_CTRL_TX0_PD_MASK)) | - LVB_PHY_POW_CTRL_PWON_PLL_MASK; -} - -void lvb_lvds_phy0_powerdown(LVB_Type *ptr) -{ - ptr->PHY_POW_CTRL[0] = (ptr->PHY_POW_CTRL[0] & ~LVB_PHY_POW_CTRL_PWON_PLL_MASK) | - LVB_PHY_POW_CTRL_TXCK_PD_MASK | LVB_PHY_POW_CTRL_TX3_PD_MASK | - LVB_PHY_POW_CTRL_TX2_PD_MASK | LVB_PHY_POW_CTRL_TX1_PD_MASK | - LVB_PHY_POW_CTRL_TX0_PD_MASK; -} - -void lvb_lvds_phy1_powerdown(LVB_Type *ptr) -{ - ptr->PHY_POW_CTRL[1] = (ptr->PHY_POW_CTRL[1] & ~LVB_PHY_POW_CTRL_PWON_PLL_MASK) | - LVB_PHY_POW_CTRL_TXCK_PD_MASK | LVB_PHY_POW_CTRL_TX3_PD_MASK | - LVB_PHY_POW_CTRL_TX2_PD_MASK | LVB_PHY_POW_CTRL_TX1_PD_MASK | - LVB_PHY_POW_CTRL_TX0_PD_MASK; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c deleted file mode 100644 index 1c3707bc9b6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mcan_drv.c +++ /dev/null @@ -1,2007 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_mcan_drv.h" -#include -#include - -/*********************************************************************************************************************** - * - * Definitions - * - **********************************************************************************************************************/ - -#define MCAN_CAN_BAUDRATE_DEFAULT (500UL * 1000UL) /*!< Default CAN2.0 baudrate:500 kbps */ -#define MCAN_CANFD_BAUDRATE_DEFAULT (2UL * 1000UL * 1000UL) /*!< Default CANFD baudrate: 2 Mbps */ - -/* Hardware restriction of each types of element for MCAN */ -#define MCAN_STD_FILTER_ELEM_CNT_MAX (128U) -#define MCAN_EXT_FILTER_ELEM_CNT_MAX (64U) -#define MCAN_RXFIFO_ELEM_CNT_MAX (64U) -#define MCAN_RXBUF_ELEM_CNT_MAX (64U) -#define MCAN_TXEVT_FIFO_ELEM_CNT_MAX (32U) -#define MCAN_TXBUF_ELEM_CNT_MAX (32U) - - -#define NUM_TQ_SYNC_SEG (1U) - -/** - * @brief CAN2.0 Timing related definitions - */ -#define TSEG1_MIN_FOR_CAN2_0 (2U) -#define TSEG1_MAX_FOR_CAN2_0 (256U) -#define TSEG2_MIN_FOR_CAN2_0 (2U) -#define TSEG2_MAX_FOR_CAN2_0 (128U) -#define TSJW_MIN_FOR_CAN2_0 (1U) -#define TSJW_MAX_FOR_CAN2_0 (128U) -#define PRESCALER_MIN_FOR_CAN2_0 (1U) -#define PRESCALER_MAX_FOR_CAN2_0 (512U) -#define NUM_TQ_MIN_FOR_CAN2_0 (8U) -#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) - -/** - * @brief CANFD Nominal Timing related definitions - */ -#define TSEG1_MIN_FOR_CANFD_NOMINAL (2U) -#define TSEG1_MAX_FOR_CANFD_NOMINAL (256U) -#define TSEG2_MIN_FOR_CANFD_NOMINAL (1U) -#define TSEG2_MAX_FOR_CANFD_NOMINAL (32U) -#define TSJW_MIN_FOR_CANFD_NOMINAL (1U) -#define TSJW_MAX_FOR_CANFD_NOMINAL (128U) -#define NUM_TQ_MIN_FOR_CANFD_NOMINAL (8U) -#define NUM_TQ_MAX_FOR_CANFD_NOMINAL (TSEG1_MAX_FOR_CANFD_NOMINAL + TSEG2_MAX_FOR_CANFD_NOMINAL) -#define PRESCALER_MIN_FOR_CANFD_NOMINAL (1U) -#define PRESCALER_MAX_FOR_CANFD_NOMINAL (512U) - -/** - * @brief CANFD Data Timing related definitions - */ -#define TSEG1_MIN_FOR_CANFD_DATA (2U) -#define TSEG1_MAX_FOR_CANFD_DATA (31U) -#define TSEG2_MIN_FOR_CANFD_DATA (0U) -#define TSEG2_MAX_FOR_CANFD_DATA (15U) -#define TSJW_MIN_FOR_CANFD_DATA (0U) -#define TSJW_MAX_FOR_CANFD_DATA (15U) -#define PRESCALER_MIN_FOR_CANFD_DATA (1U) -#define PRESCALER_MAX_FOR_CANFD_DATA (32U) - -#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) -#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) - -#define MIN_TQ_MUL_PRESCALE (8U) -#define NUM_PRESCALE_MAX (256U) - -#define CAN_SAMPLEPOINT_MIN (750U) -#define CAN_SAMPLEPOINT_MAX (875U) - -/* Invalid start address of MCAN RAM */ -#define MCAN_RAM_ADDR_INVALID ((1UL << 16) - 1U) - -/* Maximum CAN TDC offset value */ -#define MCAN_MAX_TDC_OFFSET ((uint32_t)(MCAN_TDCR_TDCO_MASK >> MCAN_TDCR_TDCO_SHIFT)) -/* Maximum CAN TDC Filter Window value */ -#define MCAN_MAX_TDC_FILTER_WIN ((uint32_t)(MCAN_TDCR_TDCF_MASK >> MCAN_TDCR_TDCF_SHIFT)) - -/** - * @brief MCAN bit timing table - */ -typedef struct mcan_bit_timing_table_struct { - uint16_t tq_min; /*!< Minimum Tq */ - uint16_t tq_max; /*!< Maximum Tq */ - uint16_t seg1_min; /*!< Minimum TSEG1 */ - uint16_t seg1_max; /*!< Maximum TSEG1 */ - uint8_t seg2_min; /*!< Minimum TSEG2 */ - uint8_t seg2_max; /*!< Maximum TSEG2 */ - uint8_t sjw_min; /*!< Minimum SJW */ - uint8_t sjw_max; /*!< Maximum SJW */ - uint8_t min_diff_seg1_minus_seg2; /*!< Minimum value of (TSEG1 - TSEG2 ) */ - uint8_t prescaler_min; /*!< Minimum Prescaler value */ - uint16_t prescaler_max; /*!< Maximum Prescaler value */ -} mcan_bit_timing_table_t; - -/*********************************************************************************************************************** - * - * Variables - * - **********************************************************************************************************************/ - -#if defined(MCAN_SOC_MSG_BUF_IN_AHB_RAM) && (MCAN_SOC_MSG_BUF_IN_AHB_RAM == 1) -ATTR_PLACE_AT(".ahb_sram") uint32_t mcan_soc_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS * MCAN_SOC_MAX_COUNT]; -#endif - -static const mcan_bit_timing_table_t k_mcan_bit_timing_tbl[3] = { - /* CAN2.0 bit timing requirement */ - { - /* TQ range */ - .tq_min = NUM_TQ_MIN_FOR_CAN2_0, .tq_max = NUM_TQ_MAX_FOR_CAN2_0, - /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg1 */ - .seg1_min = TSEG1_MIN_FOR_CAN2_0, .seg1_max = TSEG1_MAX_FOR_CAN2_0, - /* SEG2 Range */ - .seg2_min = TSEG2_MIN_FOR_CAN2_0, .seg2_max = TSEG2_MAX_FOR_CAN2_0, - /* SJW range */ - .sjw_min = TSJW_MIN_FOR_CAN2_0, .sjw_max = TSJW_MAX_FOR_CAN2_0, .min_diff_seg1_minus_seg2 = 2, - /* Prescaler range */ - .prescaler_min = PRESCALER_MIN_FOR_CAN2_0, .prescaler_max = PRESCALER_MAX_FOR_CAN2_0, - }, - /* CANFD Nominal Bit timing requirement */ - { - /* TQ range */ - .tq_min = NUM_TQ_MIN_FOR_CANFD_NOMINAL, .tq_max = NUM_TQ_MAX_FOR_CANFD_NOMINAL, - /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg1 */ - .seg1_min = TSEG1_MIN_FOR_CANFD_NOMINAL, .seg1_max = TSEG1_MAX_FOR_CANFD_NOMINAL, - /* SEG2 range */ - .seg2_min = TSEG2_MIN_FOR_CANFD_NOMINAL, .seg2_max = TSEG2_MAX_FOR_CANFD_NOMINAL, - /* SJW range */ - .sjw_min = TSJW_MIN_FOR_CANFD_NOMINAL, .sjw_max = TSJW_MAX_FOR_CANFD_NOMINAL, .min_diff_seg1_minus_seg2 = 2, - /* Prescaler range */ - .prescaler_min = PRESCALER_MIN_FOR_CANFD_NOMINAL, .prescaler_max = PRESCALER_MAX_FOR_CANFD_NOMINAL - }, - /* CANFD Data Bit timing requirement */ - { - /* TQ range */ - .tq_min = NUM_TQ_MIN_FOR_CANFD_DATA, .tq_max = NUM_TQ_MAX_FOR_CANFD_DATA, - /* SEG1 range(Including Sync_Seg + Prop_Seg + Phase_Seg2 */ - .seg1_min = TSEG1_MIN_FOR_CANFD_DATA, .seg1_max = TSEG1_MAX_FOR_CANFD_DATA, - /* SEG2 range */ - .seg2_min = TSEG2_MIN_FOR_CANFD_DATA, .seg2_max = TSEG2_MAX_FOR_CANFD_DATA, - /* SJW range */ - .sjw_min = TSJW_MIN_FOR_CANFD_DATA, .sjw_max = TSJW_MAX_FOR_CANFD_DATA, .min_diff_seg1_minus_seg2 = 1, - /* Prescaler range */ - .prescaler_min = PRESCALER_MIN_FOR_CANFD_DATA, .prescaler_max = PRESCALER_MAX_FOR_CANFD_DATA - } -}; - -static const mcan_filter_elem_t k_default_std_id_filter = { - /* Use classic filter */ - .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, - /* Store message into RXFIFO0 if matching */ - .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, - /* For Standard Identify only */ - .can_id_type = MCAN_CAN_ID_TYPE_STANDARD, - /* Sync Message, only evaluated when "CCCR.UTSU" is set */ - .sync_message = 0U, - /* Don't care if mask is set to all 1s */ - .filter_id = 0U, - /* Accept all messages */ - .filter_mask = 0x7FFU, -}; - -static const mcan_filter_elem_t k_default_ext_id_filter = { - /* Use classic filter */ - .filter_type = MCAN_FILTER_TYPE_CLASSIC_FILTER, - /* Store message into RXFIFO0 if matching */ - .filter_config = MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH, - /* For Standard Identify only */ - .can_id_type = MCAN_CAN_ID_TYPE_EXTENDED, - /* Sync Message, only evaluated when "CCCR.UTSU" is set */ - .sync_message = 0, - /* Don't care if mask is set to all 1s */ - .filter_id = 0, - /* Accept all messages */ - .filter_mask = 0x1FFFFFFFUL, -}; - -/*********************************************************************************************************************** - * - * Prototypes - * - **********************************************************************************************************************/ -/** - * @brief Set Nominal Bit timing - * - * @param [in] ptr MCAN base - * @param [in] bit_timing Bit timing parameter - */ -static void mcan_set_can_nominal_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing); - -/** - * @brief Set CANFD Data Bit timing - * - * @param [in] ptr MCAN base - * - * @param [in] bit_timing Bit timing parameter - */ -static void mcan_set_can_data_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing); - -/** - * @brief Calculate the closest prescaler - * - * @param [in] num_tq_mul_prescaler Number of TQ * Prescaler - * @param [in] start_prescaler Start of Prescaler value - * @param [in] max_tq Maximum Timing Quantum - * @param [in] min_tq Minimum Timing Quantum - * - * @return Calculated prescaler value - */ -static uint32_t mcan_find_optimal_prescaler(uint32_t num_tq_mul_prescaler, - uint32_t start_prescaler, - uint32_t max_tq, - uint32_t min_tq); - -/** - * @brief Calculate Bit timing from baudrate - * - * @param [in] src_clk_freq CAN IP clock used for generating bit timing - * @param [in] option CAN bit timing option - * @param [in] baudrate CAN baudrate in bps - * @param [in] samplepoint_min Minimum sample point, value = actual sample point * 1000 - * @param [in] samplepoint_max Maximum sample point, value = actual sample point * 1000 - * @param [out] timing_param Calculated Bit timing parameter - * - * @retval status_success if no errors happened - * @retval status_invalid_argument if the timing parameters cannot be calculated from specified baudrate - */ -static hpm_stat_t mcan_calc_bit_timing_from_baudrate(uint32_t src_clk_freq, - mcan_bit_timing_option_t option, - uint32_t baudrate, - uint16_t samplepoint_min, - uint16_t samplepoint_max, - mcan_bit_timing_param_t *timing_param); - -/** - * @brief Set MCAN bit timing from Baudrate - * - * @param [in] ptr MCAN base - * @param [in] option MCAN bit timing option - * @param [in] src_clk_freq CAN IP clock used for generating bit timing - * @param [in] baudrate Baudrate in bps - * @param [in] samplepoint_min Minimum sample point, value = actual sample point * 1000 - * @param [in] samplepoint_max Maximum sample point, value = actual sample point * 1000 - * - * @retval status_success if no errors happened - * @retval status_invalid_argument if the timing parameters cannot be calculated from specified baudrate - */ -static hpm_stat_t mcan_set_bit_timing_from_baudrate(MCAN_Type *ptr, - mcan_bit_timing_option_t option, - uint32_t src_clk_freq, - uint32_t baudrate, - uint16_t samplepoint_min, - uint16_t samplepoint_max); - -/** - * @brief Configure MCAN TSU - * - * @param [in] ptr MCAN base - * @param [in] config TSU configuration - * @retval status_success if no errors happened - * - * @retval status_invalid_argument if any parameters are invalid - */ -static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config); - -/** - * @brief Configure MCAN internal timestamp - * - * @param [in] ptr MCAN base - * @param [in] config Internal Timestamp Configuration - * @retval status_success if no errors happened - * - * @retval status_invalid_argument if any parameters are invalid - */ -static hpm_stat_t mcan_set_internal_timestamp(MCAN_Type *ptr, mcan_internal_timestamp_config_t *config); - -/** - * @brief Check whether the MCAN bit timing parameter is valid - * @param [in] option MCAN bit timing option - * @param [in] param MCAN bit timing parameter - * - * @retval true MCAN bit timing parameter is valid - * @retval false MCAN bit timing parameter is invalid - */ -static bool is_mcan_bit_timing_param_valid(mcan_bit_timing_option_t option, const mcan_bit_timing_param_t *param); - -/*********************************************************************************************************************** - * - * Codes - */ -static void mcan_set_can_nominal_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing) -{ - ptr->NBTP = MCAN_NBTP_NBRP_SET(bit_timing->prescaler - 1U) | MCAN_NBTP_NTSEG1_SET(bit_timing->num_seg1 - 1U) | - MCAN_NBTP_NTSEG2_SET(bit_timing->num_seg2 - 1U) | MCAN_NBTP_NSJW_SET(bit_timing->num_sjw - 1U); -} - -static void mcan_set_can_data_bit_timing(MCAN_Type *ptr, const mcan_bit_timing_param_t *bit_timing) -{ - ptr->DBTP = MCAN_DBTP_DBRP_SET(bit_timing->prescaler - 1U) | MCAN_DBTP_DTSEG1_SET(bit_timing->num_seg1 - 1U) | - MCAN_DBTP_DTSEG2_SET(bit_timing->num_seg2 - 1U) | MCAN_DBTP_DSJW_SET(bit_timing->num_sjw - 1U) | - MCAN_DBTP_TDC_SET((uint32_t) bit_timing->enable_tdc); -} - -static uint32_t mcan_find_optimal_prescaler(uint32_t num_tq_mul_prescaler, - uint32_t start_prescaler, - uint32_t max_tq, - uint32_t min_tq) -{ - bool has_found = false; - - uint32_t prescaler = start_prescaler; - - while (!has_found) { - if ((num_tq_mul_prescaler / prescaler > max_tq) || (num_tq_mul_prescaler % prescaler != 0)) { - ++prescaler; - continue; - } else { - uint32_t tq = num_tq_mul_prescaler / prescaler; - if (tq * prescaler == num_tq_mul_prescaler) { - has_found = true; - break; - } else if (tq < min_tq) { - has_found = false; - break; - } else { - ++prescaler; - } - } - } - - return has_found ? prescaler : 0U; -} - -static hpm_stat_t mcan_calc_bit_timing_from_baudrate(uint32_t src_clk_freq, - mcan_bit_timing_option_t option, - uint32_t baudrate, - uint16_t samplepoint_min, - uint16_t samplepoint_max, - mcan_bit_timing_param_t *timing_param) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((option > mcan_bit_timing_canfd_data) || (baudrate == 0U) || - (src_clk_freq / baudrate < MIN_TQ_MUL_PRESCALE) || (timing_param == NULL)) { - break; - } - - const mcan_bit_timing_table_t *tbl = &k_mcan_bit_timing_tbl[(uint8_t) option]; - - /* According to the CAN specification 2.0, - * the Tq must be in range specified in the above CAN bit-timing table - */ - if (src_clk_freq / baudrate < tbl->tq_min) { - break; - } - - uint32_t num_tq_mul_prescaler = src_clk_freq / baudrate; - uint32_t start_prescaler = 1U; - uint32_t num_seg1, num_seg2; - bool has_found = false; - - /* Find out the minimum prescaler */ - uint32_t current_prescaler; - while (!has_found) { - current_prescaler = mcan_find_optimal_prescaler(num_tq_mul_prescaler, - start_prescaler, - tbl->tq_max, - tbl->tq_min); - if ((current_prescaler < start_prescaler) || (current_prescaler > NUM_PRESCALE_MAX)) { - break; - } - uint32_t num_tq = num_tq_mul_prescaler / current_prescaler; - - num_seg2 = (num_tq - tbl->min_diff_seg1_minus_seg2) / 2U; - num_seg1 = num_tq - num_seg2; - while (num_seg2 > tbl->seg2_max) { - num_seg2--; - num_seg1++; - } - - /* Recommended sample point is 75% - 87.5% */ - while ((num_seg1 * 1000U) / num_tq < samplepoint_min) { - ++num_seg1; - --num_seg2; - } - - if ((num_seg1 * 1000U) / num_tq > samplepoint_max) { - break; - } - - if ((num_seg2 >= tbl->seg2_min) && (num_seg1 <= tbl->seg1_max)) { - has_found = true; - } else { - start_prescaler = current_prescaler + 1U; - } - } - - if (has_found) { - uint32_t num_sjw = MIN(tbl->sjw_max, num_seg2); - timing_param->num_seg1 = num_seg1 - NUM_TQ_SYNC_SEG; /* Should exclude the Sync_Reg */ - timing_param->num_seg2 = num_seg2; - timing_param->num_sjw = num_sjw; - timing_param->prescaler = current_prescaler; - status = status_success; - } - } while (false); - - return status; -} - -static hpm_stat_t mcan_set_bit_timing_from_baudrate(MCAN_Type *ptr, - mcan_bit_timing_option_t option, - uint32_t src_clk_freq, - uint32_t baudrate, - uint16_t samplepoint_min, - uint16_t samplepoint_max) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if (ptr == NULL) { - break; - } - - mcan_bit_timing_param_t timing_param = { 0 }; - status = mcan_calc_bit_timing_from_baudrate(src_clk_freq, - option, - baudrate, - samplepoint_min, - samplepoint_max, - &timing_param); - - if (status == status_success) { - if (option < mcan_bit_timing_canfd_data) { - mcan_set_can_nominal_bit_timing(ptr, &timing_param); - } else { - mcan_set_can_data_bit_timing(ptr, &timing_param); - } - status = status_success; - } - - } while (false); - - return status; -} - -static bool is_mcan_bit_timing_param_valid(mcan_bit_timing_option_t option, const mcan_bit_timing_param_t *param) -{ - bool result = false; - const mcan_bit_timing_table_t *tbl = &k_mcan_bit_timing_tbl[(uint8_t) option]; - do { - uint32_t actual_num_seg1 = param->num_seg1 + 1U; - if ((actual_num_seg1 < tbl->seg1_min) || (actual_num_seg1 > tbl->seg1_max)) { - break; - } - if ((param->num_seg2 < tbl->seg2_min) || (param->num_seg2 > tbl->seg2_max)) { - break; - } - if ((param->num_sjw < tbl->sjw_min) || (param->num_sjw > tbl->sjw_max)) { - break; - } - if ((param->prescaler < tbl->prescaler_min) || (param->prescaler > tbl->prescaler_max)) { - break; - } - result = true; - } while (false); - - return result; -} - -void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd) -{ - (void) memset(simple_config, 0, sizeof(mcan_ram_config_t)); - uint32_t start_addr = mcan_get_ram_offset(ptr); - - if (!enable_canfd) { - simple_config->enable_std_filter = true; - simple_config->std_filter_elem_count = MCAN_FILTER_SIZE_CAN_DEFAULT; - start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; - - simple_config->enable_ext_filter = true; - simple_config->ext_filter_elem_count = MCAN_FILTER_SIZE_CAN_DEFAULT; - start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; - - simple_config->enable_txbuf = true; - simple_config->txbuf_dedicated_txbuf_elem_count = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; - simple_config->txbuf_fifo_or_queue_elem_count = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; - simple_config->txfifo_or_txqueue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; - simple_config->txbuf_data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; - start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - - for (uint32_t i = 0; i < ARRAY_SIZE(simple_config->rxfifos); i++) { - simple_config->rxfifos[i].enable = true; - simple_config->rxfifos[i].elem_count = MCAN_RXFIFO_SIZE_CAN_DEFAULT; - simple_config->rxfifos[i].operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; - simple_config->rxfifos[i].watermark = 1U; - simple_config->rxfifos[i].data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; - start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - } - simple_config->enable_rxbuf = true; - simple_config->rxbuf_elem_count = MCAN_RXBUF_SIZE_CAN_DEFAULT; - simple_config->rxbuf_data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; - start_addr += MCAN_RXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - } else { - simple_config->enable_std_filter = true; - simple_config->std_filter_elem_count = MCAN_FILTER_SIZE_CANFD_DEFAULT; - start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; - - simple_config->enable_ext_filter = true; - simple_config->ext_filter_elem_count = MCAN_FILTER_SIZE_CANFD_DEFAULT; - start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; - - simple_config->enable_txbuf = true; - simple_config->txbuf_dedicated_txbuf_elem_count = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; - simple_config->txbuf_fifo_or_queue_elem_count = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; - simple_config->txfifo_or_txqueue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; - simple_config->txbuf_data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; - start_addr += MCAN_TXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; - - for (uint32_t i = 0; i < ARRAY_SIZE(simple_config->rxfifos); i++) { - simple_config->rxfifos[i].enable = true; - simple_config->rxfifos[i].elem_count = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; - simple_config->rxfifos[i].operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; - simple_config->rxfifos[i].watermark = 1U; - simple_config->rxfifos[i].data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; - start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; - } - simple_config->enable_rxbuf = true; - simple_config->rxbuf_elem_count = MCAN_RXBUF_SIZE_CANFD_DEFAULT; - simple_config->rxbuf_data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; - start_addr += MCAN_RXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; - } - simple_config->enable_tx_evt_fifo = true; - uint32_t tx_fifo_elem_count = - simple_config->txbuf_dedicated_txbuf_elem_count + simple_config->txbuf_fifo_or_queue_elem_count; - simple_config->tx_evt_fifo_elem_count = tx_fifo_elem_count; - simple_config->tx_evt_fifo_watermark = 1U; - - start_addr += MCAN_TXEVT_ELEM_SIZE * tx_fifo_elem_count; - - assert((start_addr - mcan_get_ram_offset(ptr)) <= mcan_get_ram_size(ptr)); -} - -void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd) -{ - (void) memset(ram_config, 0, sizeof(mcan_ram_config_t)); - uint32_t start_addr = mcan_get_ram_offset(ptr); - - if (!enable_canfd) { - ram_config->enable_std_filter = true; - ram_config->std_filter_config.list_start_addr = start_addr; - ram_config->std_filter_config.list_size = MCAN_FILTER_SIZE_CAN_DEFAULT; - start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; - - ram_config->enable_ext_filter = true; - ram_config->ext_filter_config.list_start_addr = start_addr; - ram_config->ext_filter_config.list_size = MCAN_FILTER_SIZE_CAN_DEFAULT; - start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CAN_DEFAULT; - - ram_config->enable_txbuf = true; - ram_config->txbuf_config.start_addr = start_addr; - ram_config->txbuf_config.dedicated_tx_buf_size = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; - ram_config->txbuf_config.fifo_queue_size = MCAN_TXBUF_SIZE_CAN_DEFAULT / 2; - ram_config->txbuf_config.tx_fifo_queue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; - ram_config->txbuf_elem_config.data_field_size = MCAN_DATA_FIELD_SIZE_8BYTES; - start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - - ram_config->enable_rxfifo0 = true; - ram_config->rxfifo0_config.start_addr = start_addr; - ram_config->rxfifo0_config.fifo_size = MCAN_RXFIFO_SIZE_CAN_DEFAULT; - ram_config->rxfifo0_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; - ram_config->rxfifo0_config.watermark = 1U; - start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - - ram_config->enable_rxfifo1 = true; - ram_config->rxfifo1_config.start_addr = start_addr; - ram_config->rxfifo1_config.fifo_size = MCAN_RXFIFO_SIZE_CAN_DEFAULT; - ram_config->rxfifo1_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; - ram_config->rxfifo1_config.watermark = 1U; - start_addr += MCAN_RXFIFO_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - - ram_config->enable_rxbuf = true; - ram_config->rxbuf_config.start_addr = start_addr; - start_addr += MCAN_RXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - } else { - ram_config->enable_std_filter = true; - ram_config->std_filter_config.list_start_addr = start_addr; - ram_config->std_filter_config.list_size = MCAN_FILTER_SIZE_CANFD_DEFAULT; - start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; - - ram_config->enable_ext_filter = true; - ram_config->ext_filter_config.list_start_addr = start_addr; - ram_config->ext_filter_config.list_size = MCAN_FILTER_SIZE_CANFD_DEFAULT; - start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * MCAN_FILTER_SIZE_CANFD_DEFAULT; - - ram_config->enable_txbuf = true; - ram_config->txbuf_config.start_addr = start_addr; - ram_config->txbuf_config.dedicated_tx_buf_size = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; - ram_config->txbuf_config.fifo_queue_size = MCAN_TXBUF_SIZE_CANFD_DEFAULT / 2; - ram_config->txbuf_config.tx_fifo_queue_mode = MCAN_TXBUF_OPERATION_MODE_FIFO; - ram_config->txbuf_elem_config.data_field_size = MCAN_DATA_FIELD_SIZE_64BYTES; - start_addr += MCAN_TXBUF_SIZE_CAN_DEFAULT * MCAN_TXRX_ELEM_SIZE_CAN_MAX; - - ram_config->enable_rxfifo0 = true; - ram_config->rxfifo0_config.start_addr = start_addr; - ram_config->rxfifo0_config.fifo_size = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; - ram_config->rxfifo0_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; - ram_config->rxfifo0_config.watermark = 1U; - start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; - - ram_config->enable_rxfifo1 = true; - ram_config->rxfifo1_config.start_addr = start_addr; - ram_config->rxfifo1_config.fifo_size = MCAN_RXFIFO_SIZE_CANFD_DEFAULT; - ram_config->rxfifo1_config.operation_mode = MCAN_FIFO_OPERATION_MODE_BLOCKING; - ram_config->rxfifo1_config.watermark = 1U; - start_addr += MCAN_RXFIFO_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; - - ram_config->enable_rxbuf = true; - ram_config->rxbuf_config.start_addr = start_addr; - start_addr += MCAN_RXBUF_SIZE_CANFD_DEFAULT * MCAN_TXRX_ELEM_SIZE_CANFD_MAX; - } - ram_config->enable_tx_evt_fifo = true; - ram_config->tx_evt_fifo_config.start_addr = start_addr; - uint32_t tx_fifo_size = ram_config->txbuf_config.dedicated_tx_buf_size + ram_config->txbuf_config.fifo_queue_size; - ram_config->tx_evt_fifo_config.fifo_size = tx_fifo_size; - ram_config->tx_evt_fifo_config.fifo_watermark = 1U; - - start_addr += MCAN_TXEVT_ELEM_SIZE * tx_fifo_size; - - /* Ensure the requested MCAN RAM size is less than or equal to the total MCAN RAM size */ - assert((start_addr - mcan_get_ram_offset(ptr)) <= mcan_get_ram_size(ptr)); -} - -void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config) -{ - (void) memset(config, 0, sizeof(mcan_config_t)); - config->baudrate = MCAN_CAN_BAUDRATE_DEFAULT; - config->baudrate_fd = MCAN_CANFD_BAUDRATE_DEFAULT; - config->can20_samplepoint_max = CAN_SAMPLEPOINT_MAX; - config->can20_samplepoint_min = CAN_SAMPLEPOINT_MIN; - config->canfd_samplepoint_max = CAN_SAMPLEPOINT_MAX; - config->canfd_samplepoint_min = CAN_SAMPLEPOINT_MIN; - - config->mode = mcan_mode_normal; - config->enable_canfd = false; - - /* Default Filter settings */ - mcan_all_filters_config_t *filters_config = &config->all_filters_config; - filters_config->global_filter_config.reject_remote_ext_frame = false; - filters_config->global_filter_config.reject_remote_std_frame = false; - filters_config->global_filter_config.accept_non_matching_std_frame_option = - MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; - filters_config->global_filter_config.accept_non_matching_ext_frame_option = - MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0; - filters_config->ext_id_mask = 0x1FFFFFFFUL; - filters_config->std_id_filter_list.filter_elem_list = &k_default_std_id_filter; - filters_config->std_id_filter_list.mcan_filter_elem_count = 1; - filters_config->ext_id_filter_list.filter_elem_list = &k_default_ext_id_filter; - filters_config->ext_id_filter_list.mcan_filter_elem_count = 1; - - /* Default MCAN RAM Configuration */ - mcan_ram_config_t *ram_config = &config->ram_config; - mcan_get_default_ram_config(ptr, ram_config, false); - - /* Default Internal Timestamp Configuration */ - mcan_internal_timestamp_config_t *ts_config = &config->timestamp_cfg; - ts_config->counter_prescaler = 1U; - ts_config->timestamp_selection = MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO; - - /* Default TSU configuration */ - mcan_tsu_config_t *tsu_config = &config->tsu_config; - tsu_config->prescaler = 1U; -#if defined(MCAN_SOC_TSU_SRC_TWO_STAGES) && (MCAN_SOC_TSU_SRC_TWO_STAGES == 1) - tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0; - tsu_config->tbsel_option = MCAN_TSU_TBSEL_PTPC0; -#else - tsu_config->ext_timebase_src = MCAN_TSU_EXT_TIMEBASE_SRC_PTPC; -#endif - tsu_config->use_ext_timebase = false; - tsu_config->capture_on_sof = false; - tsu_config->enable_tsu = false; - - config->timeout_cfg.enable_timeout_counter = false; - config->timeout_cfg.timeout_period = 0xFFFFU; - config->timeout_cfg.timeout_sel = mcan_timeout_continuous_operation; -} - -static void mcan_config_rxfifo(MCAN_Type *ptr, uint32_t index, uint32_t reg_val) -{ - if (index == 0U) { - ptr->RXF0C = reg_val; - } else { - ptr->RXF1C = reg_val; - } -} - -hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t elem_bytes; - uint32_t elem_count; - uint32_t start_addr = mcan_get_ram_offset(ptr); - if (config->enable_std_filter) { - if (config->std_filter_elem_count > MCAN_STD_FILTER_ELEM_CNT_MAX) { - break; - } - mcan_filter_config_t filter_config = { .reg_val = 0 }; - filter_config.list_size = config->std_filter_elem_count; - filter_config.list_start_addr = start_addr; - ptr->SIDFC = filter_config.reg_val; - start_addr += MCAN_FILTER_ELEM_STD_ID_SIZE * (uint32_t) config->std_filter_elem_count; - } else { - ptr->SIDFC = MCAN_RAM_ADDR_INVALID; - } - - if (config->enable_ext_filter) { - if (config->ext_filter_elem_count > MCAN_EXT_FILTER_ELEM_CNT_MAX) { - break; - } - mcan_filter_config_t filter_config = { .reg_val = 0 }; - filter_config.list_size = config->ext_filter_elem_count; - filter_config.list_start_addr = start_addr; - ptr->XIDFC = filter_config.reg_val; - start_addr += MCAN_FILTER_ELEM_EXT_ID_SIZE * (uint32_t) config->std_filter_elem_count; - } else { - ptr->XIDFC = MCAN_RAM_ADDR_INVALID; - } - - mcan_rx_fifo_or_buf_elem_config_t rx_fifo_buf_elem_config = { .reg_val = 0U }; - - for (uint32_t i = 0; i < ARRAY_SIZE(config->rxfifos); i++) { - if (config->rxfifos[i].enable) { - elem_bytes = mcan_get_data_field_size(config->rxfifos[i].data_field_size) - + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; - elem_count = config->rxfifos[i].elem_count; - if (elem_count > MCAN_RXFIFO_ELEM_CNT_MAX) { - return status_invalid_argument; - } - mcan_rxfifo_config_t rxfifo_config = { .reg_val = 0 }; - rxfifo_config.start_addr = start_addr; - rxfifo_config.watermark = 1U; - rxfifo_config.operation_mode = config->rxfifos[i].operation_mode; - rxfifo_config.fifo_size = elem_count; - mcan_config_rxfifo(ptr, i, rxfifo_config.reg_val); - - if (i == 0) { - rx_fifo_buf_elem_config.fifo0_data_field_size = config->rxfifos[i].data_field_size; - } else { - rx_fifo_buf_elem_config.fifo1_data_field_size = config->rxfifos[i].data_field_size; - } - - start_addr += elem_bytes * elem_count; - } else { - mcan_config_rxfifo(ptr, i, MCAN_RAM_ADDR_INVALID); - if (i == 0) { - rx_fifo_buf_elem_config.fifo0_data_field_size = 0; - } else { - rx_fifo_buf_elem_config.fifo1_data_field_size = 0; - } - } - } - - if (config->enable_rxbuf) { - elem_bytes = mcan_get_data_field_size(config->rxbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; - elem_count = config->rxbuf_elem_count; - if (elem_count > MCAN_RXFIFO_ELEM_CNT_MAX) { - break; - } - ptr->RXBC = start_addr; - rx_fifo_buf_elem_config.buf_data_field_size = config->rxbuf_data_field_size; - - start_addr += elem_bytes * elem_count; - } else { - rx_fifo_buf_elem_config.buf_data_field_size = 0; - ptr->RXBC = MCAN_RAM_ADDR_INVALID; - } - ptr->RXESC = rx_fifo_buf_elem_config.reg_val; - - mcan_txbuf_config_t txbuf_config = { .reg_val = 0 }; - if (config->enable_txbuf) { - txbuf_config.start_addr = start_addr; - txbuf_config.fifo_queue_size = config->txbuf_fifo_or_queue_elem_count; - txbuf_config.dedicated_tx_buf_size = config->txbuf_dedicated_txbuf_elem_count; - txbuf_config.tx_fifo_queue_mode = config->txfifo_or_txqueue_mode; - - elem_count = config->txbuf_fifo_or_queue_elem_count + config->txbuf_dedicated_txbuf_elem_count; - if (elem_count > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { - break; - } - - elem_bytes = mcan_get_data_field_size(config->txbuf_data_field_size) + MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; - - start_addr += elem_count * elem_bytes; - ptr->TXESC = (uint32_t) config->txbuf_data_field_size; - } else { - ptr->TXESC = MCAN_RAM_ADDR_INVALID; - } - - ptr->TXBC = txbuf_config.reg_val; - - mcan_tx_evt_fifo_config_t txevt_fifo_config = { .reg_val = 0 }; - if (config->enable_tx_evt_fifo) { - elem_bytes = sizeof(mcan_tx_event_fifo_elem_t); - elem_count = config->tx_evt_fifo_elem_count; - if (elem_count > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { - break; - } - - txevt_fifo_config.start_addr = start_addr; - txevt_fifo_config.fifo_size = elem_count; - txevt_fifo_config.fifo_watermark = 1U; - ptr->TXEFC = txevt_fifo_config.reg_val; - - start_addr += elem_bytes * elem_count; - } else { - ptr->TXEFC = MCAN_RAM_ADDR_INVALID; - } - - /* Check whether the requested RAM space exceeds the valid RAM range */ - uint32_t requested_ram_size = start_addr - mcan_get_ram_offset(ptr); - if (requested_ram_size > mcan_get_ram_size(ptr)) { - status = status_mcan_ram_out_of_range; - break; - } - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - do { - if (config->enable_std_filter) { - if (config->std_filter_config.list_size > MCAN_STD_FILTER_ELEM_CNT_MAX) { - break; - } - ptr->SIDFC = config->std_filter_config.reg_val; - } else { - ptr->SIDFC = MCAN_RAM_ADDR_INVALID; - } - - if (config->enable_ext_filter) { - if (config->std_filter_config.list_size > MCAN_EXT_FILTER_ELEM_CNT_MAX) { - break; - } - ptr->XIDFC = config->ext_filter_config.reg_val; - } else { - ptr->XIDFC = MCAN_RAM_ADDR_INVALID; - } - - if (config->enable_rxfifo0) { - if (config->rxfifo0_config.fifo_size > MCAN_RXFIFO_ELEM_CNT_MAX) { - break; - } - ptr->RXF0C = config->rxfifo0_config.reg_val; - } else { - ptr->RXF0C = MCAN_RAM_ADDR_INVALID; - } - - if (config->enable_rxfifo1) { - if (config->rxfifo1_config.fifo_size > MCAN_RXFIFO_ELEM_CNT_MAX) { - break; - } - ptr->RXF1C = config->rxfifo1_config.reg_val; - } else { - ptr->RXF1C = MCAN_RAM_ADDR_INVALID; - } - - if (config->enable_rxbuf) { - /* NOTE: There is no register field for SW to validate the rxbuf element count, - * users should ensure the parameters are in valid range. - */ - ptr->RXBC = config->rxbuf_config.start_addr; - } else { - ptr->RXBC = MCAN_RAM_ADDR_INVALID; - } - - ptr->RXESC = config->rx_elem_config.reg_val; - if (config->enable_txbuf) { - uint32_t tx_fifo_size = config->txbuf_config.fifo_queue_size + config->txbuf_config.dedicated_tx_buf_size; - if (tx_fifo_size > MCAN_TXBUF_ELEM_CNT_MAX) { - break; - } - ptr->TXESC = config->txbuf_elem_config.data_field_size; - } else { - ptr->TXESC = MCAN_RAM_ADDR_INVALID; - } - - ptr->TXBC = config->txbuf_config.reg_val; - - if (config->enable_tx_evt_fifo) { - if (config->tx_evt_fifo_config.fifo_size > MCAN_TXEVT_FIFO_ELEM_CNT_MAX) { - break; - } - ptr->TXEFC = config->tx_evt_fifo_config.reg_val; - } else { - ptr->TXEFC = MCAN_RAM_ADDR_INVALID; - } - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (config == NULL)) { - break; - } - - ptr->XIDAM = config->ext_id_mask; - - ptr->GFC = MCAN_GFC_RRFE_SET(config->global_filter_config.reject_remote_ext_frame) | - MCAN_GFC_RRFS_SET(config->global_filter_config.reject_remote_std_frame) | - MCAN_GFC_ANFE_SET(config->global_filter_config.accept_non_matching_ext_frame_option) | - MCAN_GFC_ANFS_SET(config->global_filter_config.accept_non_matching_std_frame_option); - - uint32_t elem_count = 0; - const mcan_filter_elem_t *elem = NULL; - if (config->ext_id_filter_list.mcan_filter_elem_count > 0) { - elem_count = config->ext_id_filter_list.mcan_filter_elem_count; - elem = config->ext_id_filter_list.filter_elem_list; - for (uint32_t i = 0; i < elem_count; i++) { - if (elem->can_id_type != MCAN_CAN_ID_TYPE_EXTENDED) { - status = status_invalid_argument; - break; - } - - status = mcan_set_filter_element(ptr, elem, i); - if (status != status_success) { - break; - } - ++elem; - } - if (status != status_success) { - break; - } - } - if (config->std_id_filter_list.mcan_filter_elem_count > 0) { - elem_count = config->std_id_filter_list.mcan_filter_elem_count; - elem = config->std_id_filter_list.filter_elem_list; - for (uint32_t i = 0; i < elem_count; i++) { - if (elem->can_id_type != MCAN_CAN_ID_TYPE_STANDARD) { - status = status_invalid_argument; - break; - } - status = mcan_set_filter_element(ptr, elem, i); - if (status != status_success) { - break; - } - ++elem; - } - if (status != status_success) { - break; - } - } - status = status_success; - - } while (false); - - return status; -} - -static hpm_stat_t mcan_set_tsu(MCAN_Type *ptr, mcan_tsu_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t tscfg = 0; - - if ((config->prescaler < 1U) || (config->prescaler > 256U) || - (config->ext_timebase_src > MCAN_TSU_EXT_TIMEBASE_SRC_MAX)) { - break; - } - - if (config->enable_tsu) { - tscfg |= MCAN_TSCFG_TSUE_MASK; - } - if (config->capture_on_sof) { - tscfg |= MCAN_TSCFG_SCP_MASK; - } - if (config->use_ext_timebase) { - tscfg |= MCAN_TSCFG_TBCS_MASK; - mcan_set_tsu_ext_timebase_src(ptr, config->ext_timebase_src); -#if defined(MCAN_SOC_TSU_SRC_TWO_STAGES) && (MCAN_SOC_TSU_SRC_TWO_STAGES == 1) - mcan_set_tsu_tbsel_option(ptr, config->ext_timebase_src, config->tbsel_option); -#endif - } - if (config->enable_64bit_timestamp) { - tscfg |= MCAN_TSCFG_EN64_MASK; - } - - tscfg |= MCAN_TSCFG_TBPRE_SET(config->prescaler - 1U); - - ptr->TSCFG = tscfg; - - status = status_success; - } while (false); - - return status; -} - -static hpm_stat_t mcan_set_internal_timestamp(MCAN_Type *ptr, mcan_internal_timestamp_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((config->counter_prescaler < 1U) || (config->counter_prescaler > 16) || - (config->timestamp_selection > MCAN_TIMESTAMP_SEL_MAX)) { - break; - } - - ptr->TSCC = MCAN_TSCC_TCP_SET(config->counter_prescaler - 1U) | MCAN_TSCC_TSS_SET(config->timestamp_selection); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((ptr == NULL) || (config == NULL)) { - break; - } - - mcan_enable_clock(ptr); - uint32_t retry_cnt = 10000UL; - do { - retry_cnt--; - if (retry_cnt == 0UL) { - break; - } - } while (!mcan_is_clock_enabled(ptr)); - if (retry_cnt == 0UL) { - status = status_timeout; - break; - } - - ptr->CCCR |= MCAN_CCCR_INIT_MASK; - retry_cnt = 10000UL; - while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) == 0U) { - retry_cnt--; - if (retry_cnt == 0UL) { - break; - } - } - if (retry_cnt == 0UL) { - status = status_timeout; - break; - } - - ptr->CCCR |= MCAN_CCCR_CCE_MASK; - - if (!config->use_lowlevel_timing_setting) { - if (config->enable_canfd) { - status = mcan_set_bit_timing_from_baudrate(ptr, - mcan_bit_timing_canfd_nominal, - src_clk_freq, - config->baudrate, - config->can20_samplepoint_min, - config->can20_samplepoint_max); - HPM_BREAK_IF(status != status_success); - status = mcan_set_bit_timing_from_baudrate(ptr, - mcan_bit_timing_canfd_data, - src_clk_freq, - config->baudrate_fd, - config->canfd_samplepoint_min, - config->canfd_samplepoint_max); - } else { - status = mcan_set_bit_timing_from_baudrate(ptr, - mcan_bit_timing_can2_0, - src_clk_freq, - config->baudrate, - config->can20_samplepoint_min, - config->can20_samplepoint_max); - } - HPM_BREAK_IF(status != status_success); - } else { - bool param_valid; - if (config->enable_canfd) { - param_valid = is_mcan_bit_timing_param_valid(mcan_bit_timing_canfd_nominal, &config->can_timing); - if (!param_valid) { - status = status_mcan_invalid_bit_timing; - break; - } - param_valid = is_mcan_bit_timing_param_valid(mcan_bit_timing_canfd_data, &config->canfd_timing); - if (!param_valid) { - status = status_mcan_invalid_bit_timing; - break; - } - mcan_set_can_nominal_bit_timing(ptr, &config->can_timing); - mcan_set_can_data_bit_timing(ptr, &config->canfd_timing); - } else { - param_valid = is_mcan_bit_timing_param_valid(mcan_bit_timing_can2_0, &config->can_timing); - if (!param_valid) { - status = status_mcan_invalid_bit_timing; - break; - } - mcan_set_can_nominal_bit_timing(ptr, &config->can_timing); - } - } - - switch (config->mode) { - default: - case mcan_mode_normal: - ptr->CCCR &= ~(MCAN_CCCR_MON_MASK | MCAN_CCCR_TEST_MASK); - break; - case mcan_mode_loopback_internal: - ptr->CCCR |= MCAN_CCCR_MON_MASK | MCAN_CCCR_TEST_MASK; - ptr->TEST |= MCAN_TEST_LBCK_MASK; - break; - case mcan_mode_loopback_external: - ptr->CCCR |= MCAN_CCCR_TEST_MASK; - ptr->TEST |= MCAN_TEST_LBCK_MASK; - break; - case mcan_mode_listen_only: - ptr->CCCR |= MCAN_CCCR_MON_MASK; - break; - } - - if (config->enable_canfd) { - ptr->CCCR |= MCAN_CCCR_FDOE_MASK | MCAN_CCCR_BRSE_MASK; - } else { - ptr->CCCR &= ~(MCAN_CCCR_FDOE_MASK | MCAN_CCCR_BRSE_MASK); - } - if (config->enable_non_iso_mode) { - ptr->CCCR |= MCAN_CCCR_NISO_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_NISO_MASK; - } - - if (config->enable_transmit_pause) { - ptr->CCCR |= MCAN_CCCR_TXP_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_TXP_MASK; - } - - if (config->disable_protocol_exception_handling) { - ptr->CCCR |= MCAN_CCCR_PXHD_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK; - } - - if (config->enable_wide_message_marker) { - ptr->CCCR |= MCAN_CCCR_WMM_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_WMM_MASK; - } - - if (config->enable_edge_filtering) { - ptr->CCCR |= MCAN_CCCR_EFBI_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK; - } - - if (config->disable_auto_retransmission) { - ptr->CCCR |= MCAN_CCCR_DAR_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_DAR_MASK; - } - - if (config->enable_restricted_operation_mode) { - ptr->CCCR |= MCAN_CCCR_ASM_MASK; - } else { - ptr->CCCR &= ~MCAN_CCCR_ASM_MASK; - } - - /* Configure Transmitter Delay Compensation */ - if (config->enable_tdc) { - uint32_t tdc_offset; - uint32_t tdc_filter; - if (config->tdc_config.ssp_offset == 0) { - /* Set default TDC Offset to the Data Seg1 */ - tdc_offset = MCAN_DBTP_DTSEG1_GET(ptr->DBTP) + 1; - tdc_filter = tdc_offset; - } else { - tdc_offset = config->tdc_config.ssp_offset; - tdc_filter = config->tdc_config.filter_window_length; - } - tdc_offset = MIN(tdc_offset, MCAN_MAX_TDC_OFFSET); - tdc_filter = MIN(tdc_filter, MCAN_MAX_TDC_FILTER_WIN); - ptr->TDCR = MCAN_TDCR_TDCF_SET(tdc_filter) | MCAN_TDCR_TDCO_SET(tdc_offset); - ptr->DBTP |= MCAN_DBTP_TDC_MASK; - } else { - ptr->DBTP &= ~MCAN_DBTP_TDC_MASK; - } - - /* Configure TSU */ - if (config->use_timestamping_unit) { - ptr->CCCR |= MCAN_CCCR_UTSU_MASK; - status = mcan_set_tsu(ptr, &config->tsu_config); - HPM_BREAK_IF(status != status_success); - } else { - ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK; - } - - /* Configure Internal Timestamp */ - status = mcan_set_internal_timestamp(ptr, &config->timestamp_cfg); - HPM_BREAK_IF(status != status_success); - - /* Initialize CAN RAM */ - uint32_t can_ram_size = mcan_get_ram_size(ptr); - uint32_t *ram_base = (uint32_t *) (mcan_get_ram_base(ptr) + mcan_get_ram_offset(ptr)); - for (uint32_t i = 0U; i < can_ram_size / sizeof(uint32_t); i++) { - ram_base[i] = 0UL; - } - status = mcan_config_ram(ptr, &config->ram_config); - HPM_BREAK_IF(status != status_success); - - /* Configure Filters */ - status = mcan_config_all_filters(ptr, &config->all_filters_config); - HPM_BREAK_IF(status != status_success); - - /* Disable all interrupts by default */ - mcan_disable_interrupts(ptr, ~0UL); - mcan_disable_txbuf_transmission_interrupt(ptr, ~0UL); - mcan_disable_txbuf_cancel_finish_interrupt(ptr, ~0UL); - /* Enable interrupts on demand */ - mcan_enable_interrupts(ptr, config->interrupt_mask); - mcan_enable_txbuf_transmission_interrupt(ptr, config->txbuf_trans_interrupt_mask); - mcan_enable_txbuf_cancel_finish_interrupt(ptr, config->txbuf_cancel_finish_interrupt_mask); - - /* Clear all Interrupt Flags */ - mcan_clear_interrupt_flags(ptr, ~0UL); - - /* Configure timeout */ - const mcan_timeout_config_t *timeout_cfg = &config->timeout_cfg; - ptr->TOCC = MCAN_TOCC_RP_SET(timeout_cfg->enable_timeout_counter) | - MCAN_TOCC_TOP_SET(timeout_cfg->timeout_period) | - MCAN_TOCC_TOS_SET(timeout_cfg->timeout_sel); - - ptr->CCCR &= ~MCAN_CCCR_INIT_MASK; - while ((ptr->CCCR & MCAN_CCCR_INIT_MASK) != 0U) { - } - - status = status_success; - - } while (false); - - return status; -} - -void mcan_deinit(MCAN_Type *ptr) -{ - if (ptr != NULL) { - - mcan_enter_init_mode(ptr); /* Stop MCAN function */ - - /* Enable write access to protected configuration registers */ - mcan_enable_write_to_prot_config_registers(ptr); - - /* Restore critical registers to default values */ - ptr->RWD = 0UL; - ptr->TSCC = 0UL; - ptr->GFC = 0UL; - ptr->SIDFC = 0UL; - ptr->XIDAM = 0UL; - ptr->XIDAM = 0x1FFFFFFFUL; - ptr->RXBC = 0UL; - ptr->RXF1C = 0UL; - ptr->RXESC = 0UL; - ptr->TXBC = 0UL; - ptr->TXESC = 0UL; - ptr->TXEFC = 0UL; - - ptr->TSCFG = 0UL; - - /* Disable all interrupts and clear all flags */ - mcan_disable_interrupts(ptr, ~0UL); - mcan_clear_interrupt_flags(ptr, ~0UL); - mcan_disable_txbuf_transmission_interrupt(ptr, ~0UL); - mcan_disable_txbuf_cancel_finish_interrupt(ptr, ~0UL); - - /* Restore CCCR to default value */ - ptr->CCCR = MCAN_CCCR_INIT_MASK; - } -} - -hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (filter_elem == NULL)) { - break; - } - bool is_ext_id = (filter_elem->can_id_type == MCAN_CAN_ID_TYPE_EXTENDED); - - uint32_t ram_offset; - uint32_t filter_elem_size; - uint32_t size_max; - if (is_ext_id) { - ram_offset = MCAN_XIDFC_FLESA_GET(ptr->XIDFC) << MCAN_XIDFC_FLESA_SHIFT; - filter_elem_size = MCAN_FILTER_ELEM_EXT_ID_SIZE; - size_max = MCAN_XIDFC_LSE_GET(ptr->XIDFC); - } else { - ram_offset = MCAN_SIDFC_FLSSA_GET(ptr->SIDFC) << MCAN_SIDFC_FLSSA_SHIFT; - filter_elem_size = MCAN_FILTER_ELEM_STD_ID_SIZE; - size_max = MCAN_SIDFC_LSS_GET(ptr->SIDFC); - } - - if (index >= size_max) { - status = status_mcan_filter_index_out_of_range; - break; - } - - volatile uint32_t *config_start; - config_start = (volatile uint32_t *) (mcan_get_ram_base(ptr) + ram_offset + filter_elem_size * index); - - uint32_t config_words[2] = { 0, 0 }; - if (is_ext_id) { - /* EFEC + EFID1 */ - config_words[0] = ((uint32_t) (filter_elem->filter_config) << 29) | filter_elem->id1; - - /* EFT + ESYNC + EFFID2 */ - config_words[1] = filter_elem->id2; - config_words[1] |= (filter_elem->sync_message != 0) ? (1UL << 29) : 0; - config_words[1] |= ((uint32_t) filter_elem->filter_type) << 30; - - config_start[0] = config_words[0]; - config_start[1] = config_words[1]; - } else { - config_words[0] = (filter_elem->id2 & 0x7FFUL) | ((filter_elem->id1 & 0x7FFU) << 16); - config_words[0] |= (filter_elem->sync_message != 0) ? (1UL << 15) : 0; - config_words[0] |= ((uint32_t) filter_elem->filter_config) << 27; - config_words[0] |= ((uint32_t) filter_elem->filter_type) << 30; - - config_start[0] = config_words[0]; - } - - status = status_success; - - } while (false); - - return status; -} - -static uint32_t mcan_get_rxfifo0_base(MCAN_Type *ptr) -{ - uint32_t rxfifo0_buf_offset = MCAN_RXF0C_F0SA_GET(ptr->RXF0C) << 2; - uint32_t fifo_addr_base = mcan_get_ram_base(ptr) + rxfifo0_buf_offset; - return fifo_addr_base; -} - -static uint32_t mcan_get_rxfifo1_base(MCAN_Type *ptr) -{ - uint32_t rxfifo1_buf_offset = MCAN_RXF1C_F1SA_GET(ptr->RXF1C) << 2; - uint32_t fifo_addr_base = mcan_get_ram_base(ptr) + rxfifo1_buf_offset; - return fifo_addr_base; -} - -static uint32_t mcan_get_rxbuf_elem_addr(MCAN_Type *ptr, uint32_t index) -{ - uint32_t elem_size; - uint32_t elem_size_option = MCAN_RXESC_RBDS_GET(ptr->RXESC); - if (elem_size_option < 5U) { - elem_size = 8U + 4U * elem_size_option; - } else { - elem_size = 32U + (elem_size_option - 5U) * 16U; - } - elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; - - uint32_t rxbuf_offset = MCAN_RXBC_RBSA_GET(ptr->RXBC) << MCAN_RXBC_RBSA_SHIFT; - - uint32_t rxbuf_addr_base = mcan_get_ram_base(ptr) + rxbuf_offset; - - uint32_t elem_addr = rxbuf_addr_base + elem_size * index; - - return elem_addr; -} - -static uint32_t mcan_get_txbuf_elem_addr(MCAN_Type *ptr, uint32_t index) -{ - uint32_t elem_size; - uint32_t elem_size_option = MCAN_TXESC_TBDS_GET(ptr->TXESC); - if (elem_size_option < 5U) { - elem_size = 8U + 4U * elem_size_option; - } else { - elem_size = 32U + (elem_size_option - 5U) * 16U; - } - elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; - - uint32_t txbuf_offset = MCAN_TXBC_TBSA_GET(ptr->TXBC) << MCAN_TXBC_TBSA_SHIFT; - - uint32_t txbuf_addr_base = mcan_get_ram_base(ptr) + txbuf_offset; - - uint32_t elem_addr = txbuf_addr_base + elem_size * index; - - return elem_addr; -} - -uint8_t mcan_get_message_size_from_dlc(uint8_t dlc) -{ - uint32_t msg_size; - if (dlc <= 8U) { - msg_size = dlc; - } else if (dlc <= 12U) { - msg_size = 8 + (dlc - 8) * 4; - } else { - msg_size = 32 + (dlc - 13) * 16U; - } - return msg_size; -} - -uint8_t mcan_get_data_field_size(uint8_t data_field_size_option) -{ - uint8_t size_in_bytes = 0; - - switch (data_field_size_option) { - case MCAN_DATA_FIELD_SIZE_8BYTES: - size_in_bytes = 8U; - break; - case MCAN_DATA_FIELD_SIZE_12BYTES: - size_in_bytes = 12U; - break; - case MCAN_DATA_FIELD_SIZE_16BYTES: - size_in_bytes = 16U; - break; - case MCAN_DATA_FIELD_SIZE_20BYTES: - size_in_bytes = 20U; - break; - case MCAN_DATA_FIELD_SIZE_24BYTES: - size_in_bytes = 24U; - break; - case MCAN_DATA_FIELD_SIZE_32BYTES: - size_in_bytes = 32U; - break; - case MCAN_DATA_FIELD_SIZE_48BYTES: - size_in_bytes = 48U; - break; - case MCAN_DATA_FIELD_SIZE_64BYTES: - size_in_bytes = 64U; - break; - default: - /* Invalid option */ - break; - } - return size_in_bytes; -} - -hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (tx_frame == NULL)) { - break; - } - - uint32_t txbuf_index_max = MCAN_TXBC_NDTB_GET(ptr->TXBC); - if (index >= txbuf_index_max) { - status = status_mcan_txbuf_index_out_of_range; - break; - } - - if (!mcan_is_transmit_request_pending(ptr, index)) { - uint32_t *msg_hdr = (uint32_t *) mcan_get_txbuf_elem_addr(ptr, index); - uint32_t *msg_data = msg_hdr + 2; - uint8_t msg_size_words = (mcan_get_message_size_from_dlc(tx_frame->dlc) + 3U) / sizeof(uint32_t); - uint32_t *tx_frame_u32 = (uint32_t *) tx_frame; - msg_hdr[0] = tx_frame_u32[0]; - msg_hdr[1] = tx_frame_u32[1]; - - for (uint32_t i = 0; i < msg_size_words; i++) { - msg_data[i] = tx_frame->data_32[i]; - } - - status = status_success; - } else { - status = status_fail; - } - } while (false); - - return status; -} - -hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (tx_frame == NULL)) { - break; - } - if (!mcan_is_txfifo_full(ptr)) { - uint32_t put_index = mcan_get_txfifo_put_index(ptr); - uint32_t *msg_hdr = (uint32_t *) mcan_get_txbuf_elem_addr(ptr, put_index); - uint32_t *msg_data = msg_hdr + 2; - uint8_t msg_size_words = (mcan_get_message_size_from_dlc(tx_frame->dlc) + 3U) / sizeof(uint32_t); - uint32_t *tx_frame_u32 = (uint32_t *) tx_frame; - msg_hdr[0] = tx_frame_u32[0]; - msg_hdr[1] = tx_frame_u32[1]; - - for (uint32_t i = 0; i < msg_size_words; i++) { - msg_data[i] = tx_frame->data_32[i]; - } - status = status_success; - } else { - status = status_mcan_txfifo_full; - } - } while (false); - - return status; -} - -hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (rx_frame == NULL)) { - break; - } - - if (!mcan_is_rxbuf_data_available(ptr, index)) { - status = status_mcan_rxbuf_empty; - break; - } - - uint32_t *msg_hdr = (uint32_t *) mcan_get_rxbuf_elem_addr(ptr, index); - uint32_t *msg_data = msg_hdr + 2; - uint32_t *rx_frame_u32 = (uint32_t *) rx_frame; - rx_frame_u32[0] = msg_hdr[0]; - rx_frame_u32[1] = msg_hdr[1]; - uint8_t msg_size_words = (mcan_get_message_size_from_dlc(rx_frame->dlc) + 3) / 4; - for (uint32_t i = 0; i < msg_size_words; i++) { - rx_frame->data_32[i] = msg_data[i]; - } - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (rx_frame == NULL)) { - break; - } - - uint32_t base_addr; - uint32_t elem_index; - uint32_t elem_size; - uint32_t elem_size_option; - if (fifo_index == 0) { - uint32_t rxf0s = ptr->RXF0S; - if (MCAN_RXF0S_F0FL_GET(rxf0s) == 0) { - status = status_mcan_rxfifo_empty; - break; - } - base_addr = mcan_get_rxfifo0_base(ptr); - elem_size_option = MCAN_RXESC_F0DS_GET(ptr->RXESC); - elem_index = MCAN_RXF0S_F0GI_GET(rxf0s); - } else { - uint32_t rxf1s = ptr->RXF1S; - if (MCAN_RXF1S_F1FL_GET(rxf1s) == 0) { - status = status_mcan_rxfifo_empty; - break; - } - base_addr = mcan_get_rxfifo1_base(ptr); - elem_size_option = MCAN_RXESC_F1DS_GET(ptr->RXESC); - elem_index = MCAN_RXF1S_F1GI_GET(rxf1s); - } - - - if (elem_size_option < 5U) { - elem_size = 8U + 4U * elem_size_option; - } else { - elem_size = 32U + (elem_size_option - 5U) * 16U; - } - elem_size += MCAN_MESSAGE_HEADER_SIZE_IN_BYTES; - - uint32_t elem_addr = base_addr + elem_size * elem_index; - uint32_t *msg_hdr = (uint32_t *) elem_addr; - uint32_t *msg_data = msg_hdr + 2; - uint32_t *rx_frame_u32 = (uint32_t *) rx_frame; - rx_frame_u32[0] = msg_hdr[0]; - rx_frame_u32[1] = msg_hdr[1]; - uint8_t msg_size_words = (mcan_get_message_size_from_dlc(rx_frame->dlc) + 3) / 4; - for (uint32_t i = 0; i < msg_size_words; i++) { - rx_frame->data_32[i] = msg_data[i]; - } - - if (fifo_index == 0) { - ptr->RXF0A = elem_index; - } else { - ptr->RXF1A = elem_index; - } - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (tx_evt == NULL)) { - break; - } - - uint32_t txefs = ptr->TXEFS; - - if (MCAN_TXEFS_EFFL_GET(txefs) == 0U) { - status = status_mcan_tx_evt_fifo_empty; - break; - } - - uint32_t base_addr = mcan_get_ram_base(ptr) + (MCAN_TXEFC_EFSA_GET(ptr->TXEFC) << MCAN_TXEFC_EFSA_SHIFT); - uint32_t elem_size = sizeof(mcan_tx_event_fifo_elem_t); - uint32_t elem_index = MCAN_TXEFS_EFGI_GET(txefs); - - uint32_t elem_addr = base_addr + elem_size * elem_index; - uint32_t *tx_evt_buf = (uint32_t *) elem_addr; - - tx_evt->words[0] = tx_evt_buf[0]; - tx_evt->words[1] = tx_evt_buf[1]; - - ptr->TXEFA = MCAN_TXEFA_EFAI_SET(elem_index); - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((ptr == NULL) || (tx_frame == NULL)) { - break; - } - - status = mcan_write_txbuf(ptr, index, tx_frame); - HPM_BREAK_IF(status != status_success); - -#if defined(CAN_SOC_TX_RX_BUFFER_ACCESS_WORKAROUND) && (CAN_SOC_TX_RX_BUFFER_ACCESS_WORKAROUND == 1) - uint32_t wait_cnt = 1000000UL; - while (mcan_get_activity(ptr) == mcan_activity_receiver) { - wait_cnt--; - if (wait_cnt < 1) { - return status_timeout; - } - } -#endif - - mcan_send_add_request(ptr, index); - status = status_success; - - } while (false); - return status; -} - -hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t put_index = 0; - status = mcan_transmit_via_txfifo_nonblocking(ptr, tx_frame, &put_index); - if (status != status_success) { - break; - } - - uint32_t retry_cnt = 0; - while (!mcan_is_transmit_occurred(ptr, put_index)) { - retry_cnt++; - if (retry_cnt >= MCAN_TX_RETRY_COUNT_MAX) { - break; - } - } - if (retry_cnt >= MCAN_TX_RETRY_COUNT_MAX) { - status = status_timeout; - } else { - status = status_success; - } - } while (false); - return status; -} - -hpm_stat_t mcan_request_and_fill_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((ptr == NULL) || (tx_frame == NULL)) { - break; - } - if (mcan_is_txfifo_full(ptr)) { - status = status_mcan_txfifo_full; - break; - } - - status = mcan_write_txfifo(ptr, tx_frame); - HPM_BREAK_IF(status != status_success); - - uint32_t put_index = mcan_get_txfifo_put_index(ptr); - - if (fifo_index != NULL) { - *fifo_index = put_index; - } - } while (false); - return status; -} - -hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index) -{ - hpm_stat_t status; - do { - uint32_t put_index; - status = mcan_request_and_fill_txfifo(ptr, tx_frame, &put_index); - HPM_BREAK_IF(status != status_success); - -#if defined(CAN_SOC_TX_RX_BUFFER_ACCESS_WORKAROUND) && (CAN_SOC_TX_RX_BUFFER_ACCESS_WORKAROUND == 1) - uint32_t wait_cnt = 1000000UL; - while (mcan_get_activity(ptr) == mcan_activity_receiver) { - wait_cnt--; - if (wait_cnt < 1) { - return status_timeout; - } - } -#endif - mcan_send_add_request(ptr, put_index); - - if (fifo_index != NULL) { - *fifo_index = put_index; - } - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t retry_cnt = 0; - - while (!mcan_is_rxbuf_data_available(ptr, index)) { - retry_cnt++; - if (retry_cnt >= MCAN_RX_RETRY_COUNT_MAX) { - status = status_timeout; - break; - } - } - if (status == status_timeout) { - break; - } - - mcan_clear_rxbuf_data_available_flag(ptr, index); - status = mcan_read_rxbuf(ptr, index, rx_frame); - } while (false); - - return status; -} - -hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t retry_cnt = 0; - uint32_t interrupt_flag = (fifo_index == 0U) ? MCAN_IR_RF0N_MASK : MCAN_IR_RF1N_MASK; - - while (!mcan_is_interrupt_flag_set(ptr, interrupt_flag)) { - retry_cnt++; - if (retry_cnt >= MCAN_RX_RETRY_COUNT_MAX) { - status = status_timeout; - break; - } - } - if (status == status_timeout) { - break; - } - - mcan_clear_interrupt_flags(ptr, interrupt_flag); - status = mcan_read_rxfifo(ptr, fifo_index, rx_frame); - } while (false); - - return status; -} - -void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status) -{ - uint32_t hpms = ptr->HPMS; - status->buffer_index = MCAN_HPMS_BIDX_GET(hpms); - status->filter_index = MCAN_HPMS_FIDX_GET(hpms); - status->filter_list_type = MCAN_HPMS_FLST_GET(hpms); - status->message_storage_indicator = MCAN_HPMS_MSI_GET(hpms); -} - -hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (filter_config == NULL)) { - break; - } - - ptr->GFC = MCAN_GFC_ANFE_SET(filter_config->accept_non_matching_ext_frame_option) | - MCAN_GFC_ANFS_SET(filter_config->accept_non_matching_std_frame_option) | - MCAN_GFC_RRFS_SET(filter_config->reject_remote_std_frame) | - MCAN_GFC_RRFE_SET(filter_config->reject_remote_ext_frame); - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((ptr == NULL) || (config == NULL)) { - break; - } - - ptr->TDCR = MCAN_TDCR_TDCO_SET(config->ssp_offset) | MCAN_TDCR_TDCF_SET(config->filter_window_length); - status = status_success; - - } while (false); - return status; -} - -uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index) -{ - uint32_t ts_val = 0U; - if (index < ARRAY_SIZE(ptr->TS_SEL)) { - ts_val = ptr->TS_SEL[index]; - } - return ts_val; -} - -uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index) -{ - uint64_t ts_val = 0U; - uint32_t real_index = index & 0x7U; /* Clear bit3 according to IP design */ - if (index < ARRAY_SIZE(ptr->TS_SEL)) { - ts_val = ((uint64_t) (ptr->TS_SEL[2U * real_index + 1]) << 32U); - ts_val |= ptr->TS_SEL[2U * real_index]; - /* Workaround: dummy read to clear the corresponding bits in TSS1 if the index is equal to/greater than 8 */ - if (index >= 8U) { - (void) ptr->TS_SEL[index]; - } - } - - return ts_val; -} - -hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr, - const mcan_tx_event_fifo_elem_t *tx_evt, - mcan_timestamp_value_t *timestamp) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((ptr == NULL) || (tx_evt == NULL) || (timestamp == NULL)); - - (void) memset(timestamp, 0, sizeof(mcan_timestamp_value_t)); - - bool is_tsu_used = mcan_is_tsu_used(ptr); - if (!is_tsu_used) { - timestamp->is_16bit = true; - timestamp->ts_16bit = tx_evt->tx_timestamp; - } else if (tx_evt->tx_timestamp_captured != 0U) { - bool is_64bit_ts = mcan_is_64bit_tsu_timestamp_used(ptr); - uint32_t ts_index = tx_evt->tx_timestamp_pointer; - if (!is_64bit_ts) { - timestamp->is_32bit = true; - timestamp->ts_32bit = mcan_read_32bit_tsu_timestamp(ptr, ts_index); - } else { - timestamp->is_64bit = true; - timestamp->ts_64bit = mcan_read_64bit_tsu_timestamp(ptr, ts_index); - } - status = status_success; - } else { - status = status_mcan_timestamp_not_exist; - } - - } while (false); - - return status; -} - -hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr, - const mcan_rx_message_t *rx_msg, - mcan_timestamp_value_t *timestamp) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((ptr == NULL) || (rx_msg == NULL) || (timestamp == NULL)); - - (void) memset(timestamp, 0, sizeof(mcan_timestamp_value_t)); - - bool is_tsu_used = mcan_is_tsu_used(ptr); - if (!is_tsu_used) { - timestamp->is_16bit = true; - timestamp->ts_16bit = rx_msg->rx_timestamp; - } else if (rx_msg->rx_timestamp_captured != 0U) { - bool is_64bit_ts = mcan_is_64bit_tsu_timestamp_used(ptr); - uint32_t ts_index = rx_msg->rx_timestamp_pointer; - if (!is_64bit_ts) { - timestamp->is_32bit = true; - timestamp->ts_32bit = mcan_read_32bit_tsu_timestamp(ptr, ts_index); - } else { - timestamp->is_64bit = true; - timestamp->ts_64bit = mcan_read_64bit_tsu_timestamp(ptr, ts_index); - } - status = status_success; - } else { - status = status_mcan_timestamp_not_exist; - } - } while (false); - - return status; -} - -hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status) -{ - if (protocol_status == NULL) { - return status_invalid_argument; - } - memset(protocol_status, 0, sizeof(mcan_protocol_status_t)); - uint32_t psr_val = psr; - if (MCAN_PSR_PXE_GET(psr_val) != 0U) { - protocol_status->protocol_exception_evt_occurred = true; - } - if (MCAN_PSR_RFDF_GET(psr_val) != 0U) { - protocol_status->canfd_msg_received = true; - } - if (MCAN_PSR_RBRS_GET(psr_val) != 0U) { - protocol_status->brs_flag_set_in_last_rcv_canfd_msg = true; - } - if (MCAN_PSR_RESI_GET(psr_val) != 0U) { - protocol_status->esi_flag_set_in_last_rcv_canfd_msg = true; - } - if (MCAN_PSR_BO_GET(psr_val) != 0U) { - protocol_status->in_bus_off_state = true; - } - if (MCAN_PSR_EW_GET(psr_val) != 0U) { - protocol_status->in_warning_state = true; - } - if (MCAN_PSR_EP_GET(psr_val) != 0U) { - protocol_status->in_error_passive_state = true; - } - protocol_status->activity = (mcan_activity_state_t) MCAN_PSR_ACT_GET(psr_val); - protocol_status->tdc_val = MCAN_PSR_TDCV_GET(psr_val); - - if (protocol_status->brs_flag_set_in_last_rcv_canfd_msg) { - protocol_status->last_error_code = (mcan_last_err_code_t) MCAN_PSR_DLEC_GET(psr_val); - } else { - protocol_status->last_error_code = (mcan_last_err_code_t) MCAN_PSR_LEC_GET(psr_val); - } - return status_success; -} - -hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((ptr == NULL) || (protocol_status == NULL)); - status = mcan_parse_protocol_status(ptr->PSR, protocol_status); - - } while (false); - - return status; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c deleted file mode 100644 index b606cc6a3d6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mchtmr_drv.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mchtmr_drv.h" - -void mchtmr_init_counter(MCHTMR_Type *ptr, uint64_t v) -{ - volatile uint32_t *p = (volatile uint32_t *) &ptr->MTIME; - /* - * When [31:29] == 7, low 32 bits need to be set to 0 first, - * then set high 32 bits and low 32 bits; otherwise, - * low 32 bit can be set firstly then high 32 bits. - */ - if ((v & 0xE0000000) == 0xE0000000) { - *p = 0; - *(p + 1) = v >> 32; - *p = v & 0xFFFFFFFF; - } else { - *p = v & 0xFFFFFFFF; - *(p + 1) = v >> 32; - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c deleted file mode 100644 index ffdfd6e190f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_drv.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mipi_csi_drv.h" - - -void mipi_csi_get_defconfig(mipi_csi_config_t *cfg) -{ - cfg->data_type = mipi_csi_data_type_rgb565; - cfg->lanes = 2; -} - -void mipi_csi_init(MIPI_CSI_Type *ptr, mipi_csi_config_t *cfg) -{ - ptr->CSI2_RESETN = 0x01; - ptr->IPI_SOFTRSTN = 0x01; - - if (cfg->lanes < 1 || cfg->lanes > 2) - cfg->lanes = 2; - ptr->N_LANES = MIPI_CSI_N_LANES_N_LANES_SET(cfg->lanes - 1); - - /* - * only camera mode - */ - ptr->IPI_MODE = MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK; - ptr->IPI_DATA_TYPE = (ptr->IPI_DATA_TYPE & ~(MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK)) | - MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SET(cfg->data_type); - - ptr->IPI_MEM_FLASH |= MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK; - - /* - * [16]: 0: Controller selects it automatically - */ - ptr->IPI_ADV_FEATURES = 0; - - ptr->IPI_HSD_TIME = 20; - ptr->IPI_HSA_TIME = 0; -} - -void mipi_csi_phy_poweron(MIPI_CSI_Type *ptr) -{ - /* - * MIPI CSI : PHY - * ---------------------------- - * PHY_SHUTDOWNZ : ~iddqen - * DPHY_RSTZ : hw_rst_n - */ - ptr->DPHY_RSTZ = 0x01; - ptr->PHY_SHUTDOWNZ = 0x01; -} - -void mipi_csi_phy_powerdown(MIPI_CSI_Type *ptr) -{ - /* - * MIPI CSI : PHY - * ---------------------------- - * PHY_SHUTDOWNZ : ~iddqen - * DPHY_RSTZ : hw_rst_n - */ - ptr->DPHY_RSTZ = 0x00; - ptr->PHY_SHUTDOWNZ = 0x00; -} - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c deleted file mode 100644 index 41fd9b84541..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_csi_phy_drv.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mipi_csi_phy_drv.h" - -void mipi_csi_phy_default_config(mipi_csi_phy_config_t *cfg) -{ - cfg->clane_cfg.t_settle_ns = 140; - cfg->clane_cfg.t_term_en_ns = 30; - - cfg->dlane_cfg.t_settle_ns = 100; - cfg->dlane_cfg.t_term_en_ns = 30; -} - -void mipi_csi_phy_init(MIPI_CSI_PHY_Type *ptr, mipi_csi_phy_config_t *cfg) -{ - ptr->SOFT_RST = 0x03; - ptr->SOFT_RST = 0x00; - - ptr->CLANE_PARA = (ptr->CLANE_PARA & ~(MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK | - MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK)) | - MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SET(cfg->clane_cfg.t_term_en_ns / 10) | - MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SET(cfg->clane_cfg.t_settle_ns / 10); - - - ptr->T_HS_TERMEN = (ptr->T_HS_TERMEN & ~(MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK | - MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK)) | - MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SET(cfg->dlane_cfg.t_term_en_ns / 10) | - MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SET(cfg->dlane_cfg.t_term_en_ns / 10); - - ptr->T_HS_SETTLE = (ptr->T_HS_SETTLE & ~(MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK | - MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK)) | - MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SET(cfg->dlane_cfg.t_settle_ns / 10) | - MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SET(cfg->dlane_cfg.t_settle_ns / 10); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c deleted file mode 100644 index 798c425e9ce..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_drv.c +++ /dev/null @@ -1,548 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mipi_dsi_drv.h" - -#define MIPI_WAIT_COND(cond, timeout_us) \ -({ \ - volatile uint32_t timeout_cycle = 1000UL * (timeout_us); \ - for (;;) { \ - if (cond) \ - break; \ - if (timeout_us && timeout_cycle == 0) { \ - break; \ - } \ - timeout_cycle--; \ - } \ - (cond) ? true : false; \ -}) - -typedef struct mipi_dsi_packet { - uint8_t header[4]; /*!< the four bytes that make up the header (Data ID, Word Count or Packet Data, and ECC) */ - uint16_t payload_length; /*!< number of bytes in the payload */ - const uint8_t *payload; /*!< a pointer to a buffer containing the payload, if any */ -} mipi_dsi_packet_t; - -/** - * mipi_dsi_packet_format_is_short - check if a packet is of the short format - * @param type: MIPI DSI data type of the packet - * - * @return: true if the packet for the given data type is a short packet, false - * otherwise. - */ -static bool mipi_dsi_packet_format_is_short(uint8_t type) -{ - switch (type) { - case MIPI_DSI_SHUTDOWN_PERIPHERAL: - case MIPI_DSI_TURN_ON_PERIPHERAL: - case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: - case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: - case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: - case MIPI_DSI_DCS_SHORT_WRITE: - case MIPI_DSI_DCS_SHORT_WRITE_PARAM: - case MIPI_DSI_DCS_READ: - case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: - return true; - } - - return false; -} - -/** - * mipi_dsi_packet_format_is_long - check if a packet is of the long format - * @param type: MIPI DSI data type of the packet - * - * @return: true if the packet for the given data type is a long packet, false - * otherwise. - */ -static bool mipi_dsi_packet_format_is_long(uint8_t type) -{ - switch (type) { - case MIPI_DSI_GENERIC_LONG_WRITE: - case MIPI_DSI_DCS_LONG_WRITE: - return true; - } - - return false; -} - -/** - * mipi_dsi_create_packet - create a packet from a message according to the - * DSI protocol - * @param packet: pointer to a DSI packet structure - * @param msg: message to translate into a packet - * - * @return: true on success or false on failure. - */ -static bool mipi_dsi_create_packet(mipi_dsi_packet_t *packet, const mipi_dsi_msg_t *msg) -{ - if (!packet || !msg) - return false; - - /* do some minimum sanity checking */ - if (!mipi_dsi_packet_format_is_short(msg->type) && - !mipi_dsi_packet_format_is_long(msg->type)) - return false; - - if (msg->channel > 3) - return false; - - memset(packet, 0, sizeof(*packet)); - packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); - if (mipi_dsi_packet_format_is_long(msg->type)) { - packet->header[1] = (msg->tx_len >> 0) & 0xff; - packet->header[2] = (msg->tx_len >> 8) & 0xff; - - packet->payload_length = msg->tx_len; - packet->payload = (const uint8_t *)msg->tx_buf; - } else { - const uint8_t *tx = (const uint8_t *)msg->tx_buf; - - packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0; - packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0; - } - - return true; -} - -static void mipi_dsi_config_format(MIPI_DSI_Type *ptr, mipi_dsi_pixel_format_t format) -{ - uint32_t val = 0; - - switch ((uint8_t)format) { - case MIPI_DSI_FMT_RGB888: - val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x05); - break; - case MIPI_DSI_FMT_RGB666: - val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x04) | - MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x04); - break; - case MIPI_DSI_FMT_RGB565: - val = MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(0x00); - break; - } - - ptr->DPI_COLOR_CODING = val; -} - -/* Get lane byte clock cycles. */ -static int mipi_dsi_get_hcomponent_lbcc(uint32_t lane_mbps, uint32_t pixel_clock_khz, uint32_t hcomponent) -{ - uint32_t lbcc = hcomponent * lane_mbps * 1000 / 8; - - if (!pixel_clock_khz) - return 0; - - return HPM_DIV_ROUND_CLOSEST(lbcc, pixel_clock_khz); -} - -static void mipi_dsi_video_para_config(MIPI_DSI_Type *ptr, mipi_dsi_config_t *cfg) -{ - mipi_video_para_t *video_para = &cfg->video_para; - int htotal, lbcc; - - /* VID_HXXXX_TIME uint is lbcc(lane byte clock = lane_mbps / 8) */ - htotal = video_para->hactive + video_para->hsync_len + - video_para->hback_porch + video_para->hfront_porch; - lbcc = mipi_dsi_get_hcomponent_lbcc(cfg->lane_mbps, video_para->pixel_clock_khz, htotal); - ptr->VID_HLINE_TIME = lbcc; - lbcc = mipi_dsi_get_hcomponent_lbcc(cfg->lane_mbps, video_para->pixel_clock_khz, video_para->hsync_len); - ptr->VID_HSA_TIME = lbcc; - lbcc = mipi_dsi_get_hcomponent_lbcc(cfg->lane_mbps, video_para->pixel_clock_khz, video_para->hback_porch); - ptr->VID_HBP_TIME = lbcc; - - ptr->VID_VACTIVE_LINES = video_para->vactive; - ptr->VID_VSA_LINES = video_para->vsync_len; - ptr->VID_VBP_LINES = video_para->vback_porch; - ptr->VID_VFP_LINES = video_para->vfront_porch; -} - -static bool mipi_dsi_genif_wait_w_pld_fifo_not_full(MIPI_DSI_Type *ptr) -{ - uint32_t mask = MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK; - return MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); -} - -static bool mipi_dsi_genif_wait_cmd_fifo_not_full(MIPI_DSI_Type *ptr) -{ - uint32_t mask = MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK; - return MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); -} - -static bool mipi_dsi_genif_wait_write_fifo_empty(MIPI_DSI_Type *ptr) -{ - uint32_t mask = MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK | - MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK; - - return MIPI_WAIT_COND((ptr->CMD_PKT_STATUS & mask) == mask, 10000); -} - -static bool dw_mipi_dsi_read_from_fifo(MIPI_DSI_Type *ptr, - const struct mipi_dsi_msg *msg) -{ - uint8_t *payload = (uint8_t *)msg->rx_buf; - uint16_t length; - uint32_t val; - uint32_t mask; - bool ret = true; - - mask = MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK; - ret = MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); - if (ret == false) { - return ret; - } - - /* Receive payload */ - for (length = msg->rx_len; length; length -= 4) { - mask = MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK; - ret = MIPI_WAIT_COND(!(ptr->CMD_PKT_STATUS & mask), 10000); - if (ret == false) { - return ret; - } - - val = ptr->GEN_PLD_DATA; - - switch (length) { - case 3: - payload[2] = (val >> 16) & 0xff; - /* Fall through */ - case 2: - payload[1] = (val >> 8) & 0xff; - /* Fall through */ - case 1: - payload[0] = val & 0xff; - return ret; - } - - payload[0] = (val >> 0) & 0xff; - payload[1] = (val >> 8) & 0xff; - payload[2] = (val >> 16) & 0xff; - payload[3] = (val >> 24) & 0xff; - payload += 4; - } - - return ret; -} - -static uint32_t get_le32(const uint8_t *p) -{ - return p[0] | p[1] << 8 | p[2] << 16 | p[3] << 24; -} - -void mipi_dsi_get_defconfig_on_video(mipi_dsi_config_t *cfg) -{ - mipi_video_para_t video_para = { - .pixel_clock_khz = 59400, - .hactive = 800, - .hsync_len = 8, - .hback_porch = 48, - .hfront_porch = 52, - .vsync_len = 6, - .vactive = 1280, - .vback_porch = 16, - .vfront_porch = 15 - }; - - cfg->lanes = 4; - cfg->channel = 0; - cfg->lane_mbps = 500; - cfg->disable_eotp = false; - cfg->pixel_format = MIPI_DSI_FMT_RGB888; - cfg->video_mode = MIPI_DSI_VIDEO_MODE_BURST; - cfg->video_para = video_para; -} - -void mipi_dsi_init(MIPI_DSI_Type *ptr, mipi_dsi_config_t *cfg) -{ - uint32_t val; - - /* PWR need reset when config register */ - ptr->PWR_UP &= ~MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; - - /* escclk config about 20MHz and esc_clk_div > 1*/ - uint32_t esc_clk_div = HPM_DIV_ROUND_UP(cfg->lane_mbps / 8, 20); - esc_clk_div = esc_clk_div <= 1 ? 2 : esc_clk_div; - - ptr->CLKMGR_CFG = MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(10) | - MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(esc_clk_div); - - mipi_dsi_config_format(ptr, cfg->pixel_format); - ptr->DPI_VCID = MIPI_DSI_DPI_VCID_DPI_VCID_SET(cfg->channel); - ptr->DPI_LP_CMD_TIM = MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(4) | - MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(4); - - val = MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK | - MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK | - MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK | - MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK; - if (cfg->disable_eotp) - val &= ~MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK; - ptr->PCKHDL_CFG = val; - - val = MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK | - MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK | - MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK | - MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK | - MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK | - MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK | - MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(cfg->video_mode); - ptr->VID_MODE_CFG = val; - - ptr->VID_PKT_SIZE = cfg->video_para.hactive; - - ptr->TO_CNT_CFG = MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(1000) | - MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(1000); - - ptr->BTA_TO_CNT = MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(0xd00); - - mipi_dsi_video_para_config(ptr, cfg); - - ptr->PHY_TMR_CFG = MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(0x40) | - MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(0x40); - ptr->PHY_TMR_RD = 10000; - ptr->PHY_TMR_LPCLK_CFG = MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(0x40) | - MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(0x40); - ptr->PHY_IF_CFG = MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(0x20) | - MIPI_DSI_PHY_IF_CFG_N_LANES_SET(cfg->lanes - 1); - ptr->PWR_UP |= MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; -} - -void mipi_dsi_phy_poweron(MIPI_DSI_Type *ptr) -{ - ptr->PHY_RSTZ |= MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK; - ptr->PHY_RSTZ |= MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK; -} - -void mipi_dsi_phy_powerdown(MIPI_DSI_Type *ptr) -{ - ptr->PHY_RSTZ &= ~(MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK | - MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK); -} - -void mipi_dsi_video_mode_hs_transfer_enable(MIPI_DSI_Type *ptr) -{ - ptr->PWR_UP &= ~MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; - ptr->LPCLK_CTRL |= MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK; - ptr->MODE_CFG = MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(0); - ptr->PWR_UP |= MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; -} - -void mipi_dsi_video_mode_hs_transfer_disable(MIPI_DSI_Type *ptr) -{ - ptr->PWR_UP &= ~MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK; - ptr->LPCLK_CTRL &= ~MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK; -} - -int mipi_dsi_lp_cmd_transfer(MIPI_DSI_Type *ptr, const mipi_dsi_msg_t *msg) -{ - struct mipi_dsi_packet packet; - int ret = -1; - int val; - - /* do some minimum sanity checking */ - if (!mipi_dsi_packet_format_is_short(msg->type) && - !mipi_dsi_packet_format_is_long(msg->type)) - return ret; - - ptr->VID_MODE_CFG |= MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK; - ptr->LPCLK_CTRL &= ~MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK; - - /* create a packet to the DSI protocol */ - if (mipi_dsi_create_packet(&packet, msg) == false) { - return ret; - } - - ptr->CMD_MODE_CFG = 1u<<24 | 1u<<19 | 1u<<18 | 1u<<17 | - 1u<<16 | 1u<<14 | 1u<<13 | 1u<<12 | - 1u<<11 | 1u<<10 | 1u<<9 | 1u<<8; - - /* config to cmd mode */ - ptr->MODE_CFG = MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(1); - - /* Send payload */ - while (packet.payload_length > 0) { - /* - * Alternatively, you can always keep the FIFO - * nearly full by monitoring the FIFO state until - * it is not full, and then writea single word of data. - * This solution is more resource consuming - * but it simultaneously avoids FIFO starvation, - * making it possible to use FIFO sizes smaller than - * the amount of data of the longest packet to be written. - */ - if (mipi_dsi_genif_wait_w_pld_fifo_not_full(ptr) == false) - return ret; - - if (packet.payload_length < 4) { - /* send residu payload */ - val = 0; - memcpy(&val, packet.payload, packet.payload_length); - packet.payload_length = 0; - } else { - val = get_le32(packet.payload); - packet.payload += 4; - packet.payload_length -= 4; - } - ptr->GEN_PLD_DATA = val; - } - - if (mipi_dsi_genif_wait_cmd_fifo_not_full(ptr) == false) - return ret; - - /* Send packet header */ - val = get_le32(packet.header); - ptr->GEN_HDR = val; - - if (mipi_dsi_genif_wait_write_fifo_empty(ptr) == false) - return ret; - - if (msg->rx_len) { - if (dw_mipi_dsi_read_from_fifo(ptr, msg) == false) - return ret; - } - - return msg->rx_len ? msg->rx_len : msg->tx_len; -} - -int mipi_dsi_set_maximum_return_packet_size(MIPI_DSI_Type *ptr, uint8_t channel, uint16_t value) -{ - uint8_t tx[2] = {value & 0xff, value >> 8}; - struct mipi_dsi_msg msg = { - .channel = channel, - .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, - .tx_len = sizeof(tx), - .tx_buf = tx, - }; - - int ret = mipi_dsi_lp_cmd_transfer(ptr, &msg); - - return (ret < 0) ? false : true; -} - -int mipi_dsi_generic_write(MIPI_DSI_Type *ptr, uint8_t channel, const void *payload, - uint16_t size) -{ - struct mipi_dsi_msg msg = { - .channel = channel, - .tx_buf = payload, - .tx_len = size - }; - - switch (size) { - case 0: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; - break; - case 1: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; - break; - case 2: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; - break; - default: - msg.type = MIPI_DSI_GENERIC_LONG_WRITE; - break; - } - - return mipi_dsi_lp_cmd_transfer(ptr, &msg); -} - - -int mipi_dsi_generic_read(MIPI_DSI_Type *ptr, uint8_t channel, const void *params, - uint16_t num_params, void *data, uint16_t size) -{ - struct mipi_dsi_msg msg = { - .channel = channel, - .tx_len = num_params, - .tx_buf = params, - .rx_len = size, - .rx_buf = data - }; - - switch (num_params) { - case 0: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; - break; - case 1: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; - break; - case 2: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; - break; - default: - return -1; - } - - return mipi_dsi_lp_cmd_transfer(ptr, &msg); -} - - -int mipi_dsi_dcs_write_buffer(MIPI_DSI_Type *ptr, uint8_t channel, - const void *data, uint16_t len) -{ - struct mipi_dsi_msg msg = { - .channel = channel, - .tx_buf = data, - .tx_len = len - }; - - switch (len) { - case 0: - return -1; - case 1: - msg.type = MIPI_DSI_DCS_SHORT_WRITE; - break; - case 2: - msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - default: - msg.type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - - return mipi_dsi_lp_cmd_transfer(ptr, &msg); -} - -int mipi_dsi_dcs_write(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, - const void *data, uint16_t len) -{ - int err; - uint16_t size; - uint8_t tx[128]; - - if (len < sizeof(tx)) { - size = 1 + len; - tx[0] = cmd; - if (len > 0) - memcpy(&tx[1], data, len); - } else { - return -1; - } - - err = mipi_dsi_dcs_write_buffer(ptr, channel, tx, size); - - return err; -} - -int mipi_dsi_dcs_read(MIPI_DSI_Type *ptr, uint8_t channel, uint8_t cmd, void *data, uint16_t len) -{ - struct mipi_dsi_msg msg = { - .channel = channel, - .type = MIPI_DSI_DCS_READ, - .tx_buf = &cmd, - .tx_len = 1, - .rx_buf = data, - .rx_len = len - }; - - return mipi_dsi_lp_cmd_transfer(ptr, &msg); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c deleted file mode 100644 index e07f6568757..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mipi_dsi_phy_drv.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mipi_dsi_phy_drv.h" - -typedef struct mipi_phy_clk_reg { - uint32_t rate; /*!< rate[2:0] */ - uint32_t pll_div; /*!< pll_div[14:0] */ -} mipi_phy_clk_reg_t; - -#define MIPI_DSI_PHY_RATE_MAX 4 -#define MIPI_DSI_PHY_REFCLK_FREQ_MHZ 24UL -#define MIPI_DSI_PHY_VCO_FREQ_MAX 4000UL -#define MIPI_DSI_PHY_PHY_VCO_FREQ_MIN 1600UL - -hpm_stat_t mipi_pll_get_cfg(uint32_t lane_mbps, mipi_phy_clk_reg_t *reg) -{ - uint32_t fvco_freq_mhz = lane_mbps; - uint32_t fvco_fraction_freq_mhz; - uint32_t rate = 0; - uint32_t pll_div_integer; /*pll_div[14:10]*/ - uint32_t pll_div_fraction; /*pll_div[9:0]*/ - - while (fvco_freq_mhz < MIPI_DSI_PHY_PHY_VCO_FREQ_MIN) { - rate++; - fvco_freq_mhz = lane_mbps * (1< 4) { - return status_invalid_argument; - } - - pll_div_integer = fvco_freq_mhz / 8 / MIPI_DSI_PHY_REFCLK_FREQ_MHZ; - fvco_fraction_freq_mhz = fvco_freq_mhz - (pll_div_integer * 8 * MIPI_DSI_PHY_REFCLK_FREQ_MHZ); - pll_div_fraction = (fvco_fraction_freq_mhz * 1024 + (8 * MIPI_DSI_PHY_REFCLK_FREQ_MHZ) / 2) /\ - (8 * MIPI_DSI_PHY_REFCLK_FREQ_MHZ); - - reg->rate = rate; - reg->pll_div = pll_div_integer<<10 | pll_div_fraction; - - return status_success; -} - -static bool mipi_dsi_phy_pll_init(MIPI_DSI_PHY_Type *ptr, uint32_t lane_mbps) -{ - hpm_stat_t state; - mipi_phy_clk_reg_t reg; - state = mipi_pll_get_cfg(lane_mbps, ®); - if (state == status_invalid_argument) - return false; - - - ptr->PLL_CTRL_PARA0 = (HPM_MIPI_DSI_PHY0->PLL_CTRL_PARA0 &\ - ~(MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK | - MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK | - MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK)) | - MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET(reg.rate) | - MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET(0) | - MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET(reg.pll_div); - return true; -} - -void mipi_dsi_phy_init(MIPI_DSI_PHY_Type *ptr, mipi_dsi_phy_config_t *cfg) -{ - uint32_t byteclk_period_ps = 1000000u / (cfg->lane_mbps / 8); - uint32_t ui_ps = 1000000u / cfg->lane_mbps; - - ptr->TEST_PARA0 |= 1u<<3; - mipi_dsi_phy_pll_init(ptr, cfg->lane_mbps); - ptr->MISC_PARA = (ptr->MISC_PARA & ~(MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK)) | - MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET(cfg->lanes - 1); - - uint32_t tlpx_ps = 50 * 1000; /* min: 50ns */ - ptr->COMMON_PARA0 = HPM_DIV_ROUND_UP(tlpx_ps, byteclk_period_ps) - 1; - - uint32_t tclk_prepare_ps = (38 + 95) * 1000 / 2; /* min: 38ns, max: 95ns */ - uint32_t tclk_zero_ps = 300 * 1000 - tclk_prepare_ps; /* min: 300ns */ - uint32_t tclk_pre_ps = 8* ui_ps; /* min: 8 * UI */ - uint32_t t_clk_post_ps = 60 * 1000 + 52 * ui_ps; /* min: 60ns + 52 * UI */ - uint32_t t_clk_trail_ps = 60 * 1000; /* min: 60ns */ - uint32_t t_hs_exit_ps = 100 * 1000; /* min: 100ns */ - - ptr->CLANE_PARA2 = MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET(HPM_DIV_ROUND_UP(tclk_prepare_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET(HPM_DIV_ROUND_UP(tclk_zero_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET(HPM_DIV_ROUND_UP(tclk_pre_ps, byteclk_period_ps) - 1); - - ptr->CLANE_PARA3 = MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET(HPM_DIV_ROUND_UP(t_clk_post_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET(HPM_DIV_ROUND_UP(t_clk_trail_ps, byteclk_period_ps) - 1); - - - uint32_t dlane0_para2; - uint32_t ths_prepare_ps = (40 + 85) / 2 * 1000 + (4 + 6) / 2 * ui_ps; /* min: 40ns + 4 * UI, max: 85ns + 6 * UI */ - uint32_t ths_zero_ps = 145 * 1000 + 10 * ui_ps - ths_prepare_ps; /* min: 145ns + 10 * UI */ - uint32_t ths_trail_ps0 = 8 * ui_ps; - uint32_t ths_trail_ps1 = 60 * 1000 * 4 * ui_ps; - uint32_t ths_trail_ps = ths_trail_ps0 > ths_trail_ps1 ? ths_trail_ps0 : ths_trail_ps1; - - dlane0_para2 = MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET(HPM_DIV_ROUND_UP(ths_prepare_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET(HPM_DIV_ROUND_UP(ths_zero_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET(HPM_DIV_ROUND_UP(ths_trail_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET(HPM_DIV_ROUND_UP(t_hs_exit_ps, byteclk_period_ps) - 1); - - ptr->DLANE0_PARA2 = dlane0_para2; - ptr->DLANE1_PARA2 = dlane0_para2; - ptr->DLANE2_PARA2 = dlane0_para2; - ptr->DLANE3_PARA2 = dlane0_para2; - - uint32_t ta_go_ps = 4 * tlpx_ps; /* 4 * Tlpx */ - uint32_t ta_sure_ps = tlpx_ps; /* min: Tlpx, max: 2 * Tlpx */ - uint32_t ta_get_ps = 5 * tlpx_ps; /* 4 * Tlpx */ - - ptr->DLANE0_PARA4 = MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET(HPM_DIV_ROUND_UP(ta_go_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET(HPM_DIV_ROUND_UP(ta_sure_ps, byteclk_period_ps) - 1) | - MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET(HPM_DIV_ROUND_UP(ta_get_ps, byteclk_period_ps) - 1); - -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c deleted file mode 100644 index 41d7bd83e5c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mmc_drv.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_mmc_drv.h" - -void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode) -{ - if (mode->discrete_pos_mode) { - base->CR |= MMC_CR_DISCRETETRC_MASK; - base->DISCRETECFG0 = MMC_DISCRETECFG0_POSMAX_SET(mode->discrete_line); - uint32_t inv_line = (uint32_t)(100000000UL / mode->discrete_line); - base->DISCRETECFG1 = MMC_DISCRETECFG1_INV_POSMAX_SET(inv_line); - } else { - base->CR &= ~MMC_CR_DISCRETETRC_MASK; - base->DISCRETECFG1 = MMC_DISCRETECFG1_INV_POSMAX_SET(mode->continuous_step_thr); - base->CONTCFG0 = MMC_CONTCFG0_HALF_CIRC_THETA_SET(mode->continuous_circ_thr); - } - - base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(mode->oosync_theta_thr); -} - -void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config) -{ - (void) base; - config->force_accel_to_zero = false; - config->en_ms_coef = false; - config->open_loop_mode = false; - config->pos_16bit_type = false; - config->sync_new_pos = false; - - config->pos_mode.discrete_pos_mode = false; - config->pos_mode.discrete_line = 0x10000; - config->pos_mode.continuous_step_thr = 0x1000000; - config->pos_mode.continuous_circ_thr = 0x1000000; - config->pos_mode.oosync_theta_thr = 0x1000000; -} - -void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config) -{ - base->CR &= ~(MMC_CR_FRCACCELZERO_MASK - | MMC_CR_MS_COEF_EN_MASK - | MMC_CR_OPEN_LOOP_MODE_MASK - | MMC_CR_POS_TYPE_MASK - | MMC_CR_ADJOP_MASK); - - base->CR |= MMC_CR_FRCACCELZERO_SET(config->force_accel_to_zero) - | MMC_CR_MS_COEF_EN_SET(config->en_ms_coef) - | MMC_CR_OPEN_LOOP_MODE_SET(config->open_loop_mode) - | MMC_CR_POS_TYPE_SET(config->pos_16bit_type) - | MMC_CR_ADJOP_SET(config->sync_new_pos); - - mmc_track_config_pos_mode(base, &config->pos_mode); -} - -void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) -{ - (void) base; - para->pos_time = 0; - para->position = 0; - para->revolution = 0; - para->speed = 0; - para->accel = 0; - para->cmd_mask = mmc_pos_update_all; - para->trigger = mmc_pos_update_by_timestamp; -} - -void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) -{ - /* speed and accel has 19bit decimal */ - int32_t speed = (int32_t)(para->speed * (1 << 19U)); - int32_t accel = (int32_t)(para->accel * (1 << 19U)); - - base->INI_SPEED = speed; - base->INI_ACCEL = accel; - base->INI_POS = para->position; - base->INI_REV = para->revolution; - base->INI_POS_TIME = para->pos_time; - - base->CR &= ~(MMC_CR_INI_POS_TRG_TYPE_MASK | MMC_CR_INI_POS_CMD_MSK_MASK | MMC_CR_INI_POS_REQ_MASK); - base->CR |= MMC_CR_INI_POS_TRG_TYPE_SET((para->trigger)) - | MMC_CR_INI_POS_CMD_MSK_SET(para->cmd_mask) - | MMC_CR_INI_POS_REQ_MASK; -} - -void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para) -{ - int32_t speed = (int32_t)(para->speed * (1 << 19U)); - int32_t accel = (int32_t)(para->accel * (1 << 19U)); - - base->INI_DELTA_SPEED = speed; - base->INI_DELTA_ACCEL = accel; - base->INI_DELTA_POS = para->position; - base->INI_DELTA_REV = para->revolution; - base->INI_DELTA_POS_TIME = para->pos_time; - - base->CR &= ~(MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK | MMC_CR_INI_DELTA_POS_CMD_MSK_MASK | MMC_CR_INI_DELTA_POS_REQ_MASK); - base->CR |= MMC_CR_INI_DELTA_POS_TRG_TYPE_SET((para->trigger)) - | MMC_CR_INI_DELTA_POS_CMD_MSK_SET(para->cmd_mask) - | MMC_CR_INI_DELTA_POS_REQ_MASK; -} - -void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para) -{ - int32_t coef_p = (int32_t)(para->coef_p * (1 << 15U)); - int32_t coef_i = (int32_t)(para->coef_i * (1 << 21U)); - int32_t coef_a = (int32_t)(para->coef_a * (1 << 19U)); - - base->INI_PCOEF = coef_p; - base->INI_ICOEF = coef_i; - base->INI_ACOEF = coef_a; - base->INI_COEF_TIME = para->coef_time; - - base->CR &= ~(MMC_CR_INI_COEFS_CMD_MSK_MASK | MMC_CR_INI_COEFS_CMD_MASK); - base->CR |= MMC_CR_INI_COEFS_CMD_MSK_SET(para->cmd_mask) - | MMC_CR_INI_COEFS_CMD_MASK; -} - -void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config) -{ - int32_t coef_p = (int32_t)(config->coef_p * (1 << 15U)); - int32_t coef_i = (int32_t)(config->coef_i * (1 << 21U)); - int32_t coef_a = (int32_t)(config->coef_a * (1 << 19U)); - - base->COEF_TRG_CFG[index].P = coef_p; - base->COEF_TRG_CFG[index].I = coef_i; - base->COEF_TRG_CFG[index].A = coef_a; - base->COEF_TRG_CFG[index].TIME = config->hold_time; - base->COEF_TRG_CFG[index].ERR_THR = config->err_thr; -} - -void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out) -{ - /* mmc_track_enable_shadow_read(base); */ - - base->CR |= MMC_CR_SHADOW_RD_REQ_MASK; - while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) { - } - - if (pos_out != NULL) { - pos_out->time = base->ESTM_TIM; - pos_out->position = base->ESTM_POS; - pos_out->revolution = (int32_t)base->ESTM_REV; - - int32_t speed = base->ESTM_SPEED; - int32_t accel = base->ESTM_ACCEL; - - pos_out->speed = (double)speed / (1 << 19U); - pos_out->accel = (double)accel / (1 << 19U); - } - - if (coef_out != NULL) { - int32_t coef_p = base->CUR_PCOEF; - int32_t coef_i = base->CUR_ICOEF; - int32_t coef_a = base->CUR_ACOEF; - - coef_out->coef_p = (double)coef_p / (1 << 15U); - coef_out->coef_i = (double)coef_i / (1 << 21U); - coef_out->coef_a = (double)coef_a / (1 << 19U); - } -} - - -void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config) -{ - (void) base; - config->speed_trig_int = false; - config->position_trig_int = false; - config->delta_pos_done_trig_int = false; - - - config->open_loop_mode = false; - config->pred_mode = 0; - config->not_first_pred_trig_type = 0; - config->first_pred_trig_type = 0; -} - -void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config) -{ - base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK - | MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK - | MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK - | MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK - | MMC_BR_BR_CTRL_PRED_MODE_MASK - | MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK - | MMC_BR_BR_CTRL_F_TRG_TYPE_MASK); - - base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(config->speed_trig_int) - | MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(config->position_trig_int) - | MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(config->delta_pos_done_trig_int) - | MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(config->open_loop_mode) - | MMC_BR_BR_CTRL_PRED_MODE_SET(config->pred_mode) - | MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(config->not_first_pred_trig_type) - | MMC_BR_BR_CTRL_F_TRG_TYPE_SET(config->first_pred_trig_type); -} - -void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload) -{ - /* speed and accel has 19bit decimal */ - int32_t speed = (int32_t)(para->speed * (1 << 19U)); - int32_t accel = (int32_t)(para->accel * (1 << 19U)); - - base->BR[index].BR_INI_SPEED = speed; - base->BR[index].BR_INI_ACCEL = accel; - base->BR[index].BR_INI_POS = para->position; - base->BR[index].BR_INI_REV = para->revolution; - base->BR[index].BR_INI_POS_TIME = para->pos_time; - - base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK | MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK); - base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET((para->trigger)) - | MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(para->cmd_mask); - - if (req_reload) { - base->CR |= (1U << (MMC_CR_INI_BR0_POS_REQ_SHIFT - index)); - } -} - -void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para) -{ - int32_t speed = (int32_t)(para->speed * (1 << 19U)); - int32_t accel = (int32_t)(para->accel * (1 << 19U)); - - base->BR[index].BR_INI_DELTA_SPEED = speed; - base->BR[index].BR_INI_DELTA_ACCEL = accel; - base->BR[index].BR_INI_DELTA_POS = para->position; - base->BR[index].BR_INI_DELTA_REV = para->revolution; - base->BR[index].BR_INI_DELTA_POS_TIME = para->pos_time; - - base->BR[index].BR_CTRL &= ~(MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK - | MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK - | MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK); - - base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(para->trigger) - | MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(para->cmd_mask) - | MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK; -} - -/* 不需要shadow吗 */ -void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out) -{ - pos_out->time = base->BR[index].BR_CUR_POS_TIME; - pos_out->position = base->BR[index].BR_CUR_POS; - pos_out->revolution = (int32_t)base->BR[index].BR_CUR_REV; - - int32_t speed = base->BR[index].BR_CUR_SPEED; - int32_t accel = base->BR[index].BR_CUR_ACCEL; - - pos_out->speed = (double)speed / (1 << 19U); - pos_out->accel = (double)accel / (1 << 19U); -} - -void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time) -{ - base->BR[index].BR_TIMEOFF = time->offset_time; - base->BR[index].BR_TRG_PERIOD = time->period_time; - base->BR[index].BR_TRG_F_TIME = time->first_time; -} - -void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig) -{ - base->BR[index].BR_TRG_POS_THR = trig->position_thr; - base->BR[index].BR_TRG_REV_THR = trig->revolution_thr; - - base->BR[index].BR_TRG_POS_CFG = MMC_BR_BR_TRG_POS_CFG_EDGE_SET(trig->less_than) - | MMC_BR_BR_TRG_POS_CFG_EN_SET(trig->enable); -} - -void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig) -{ - /* speed has 19bit decimal */ - int32_t speed = (int32_t)(trig->speed_thr * (1 << 19U)); - - base->BR[index].BR_TRG_SPEED_THR = speed; - base->BR[index].BR_TRG_SPEED_CFG = MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(trig->absolute_compare) - | MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(trig->less_than) - | MMC_BR_BR_TRG_SPEED_CFG_EN_SET(trig->enable); -} - -void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig) -{ - base->POS_TRG_POS_THR = trig->position_thr; - base->POS_TRG_REV_THR = trig->revolution_thr; - - base->POS_TRG_CFG = MMC_POS_TRG_CFG_EDGE_SET(trig->less_than) - | MMC_POS_TRG_CFG_EN_SET(trig->enable); -} - -void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig) -{ - /* speed has 19bit decimal */ - int32_t speed = (int32_t)(trig->speed_thr * (1 << 19U)); - base->SPEED_TRG_THR = speed; - base->SPEED_TRG_CFG = MMC_SPEED_TRG_CFG_COMP_TYPE_SET(trig->absolute_compare) - | MMC_SPEED_TRG_CFG_EDGE_SET(trig->less_than) - | MMC_SPEED_TRG_CFG_EN_SET(trig->enable); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c deleted file mode 100644 index 5c2785ba41a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_mtg_drv.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_mtg_drv.h" - -int32_t mtg_calc_vel_preset(MTG_Type *base, clock_name_t clock, uint8_t tra_index, float speed) -{ - assert(tra_index < 2); - uint32_t mtg_clock_fre = clock_get_frequency(clock); - uint32_t shift_vel = MTG_TRA_SHIFT_VEL_SHIFT_GET(base->TRA[tra_index].SHIFT); - assert(shift_vel <= 8); - uint32_t rev_vel_shift = 12 - shift_vel; - return (int32_t)(speed * ((uint64_t)1 << (rev_vel_shift * 8)) / mtg_clock_fre); -} - -int32_t mtg_calc_acc_preset(MTG_Type *base, clock_name_t clock, uint8_t tra_index, float acc) -{ - assert(tra_index < 2); - uint32_t mtg_clock_fre = clock_get_frequency(clock); - uint32_t shift_vel = MTG_TRA_SHIFT_VEL_SHIFT_GET(base->TRA[tra_index].SHIFT); - uint32_t shift_acc = MTG_TRA_SHIFT_ACC_SHIFT_GET(base->TRA[tra_index].SHIFT); - assert(shift_acc <= shift_vel); - uint32_t vel_acc_shift = shift_vel - shift_acc; - return (int32_t)(acc * ((uint64_t)mtg_calc_vel_preset(base, clock, tra_index, 1) << (vel_acc_shift * 8)) / mtg_clock_fre); -} - -int32_t mtg_calc_jer_preset(MTG_Type *base, clock_name_t clock, uint8_t tra_index, float jer) -{ - assert(tra_index < 2); - uint32_t mtg_clock_fre = clock_get_frequency(clock); - uint32_t shift_jerk = MTG_TRA_SHIFT_JER_SHIFT_GET(base->TRA[tra_index].SHIFT); - uint32_t shift_acc = MTG_TRA_SHIFT_ACC_SHIFT_GET(base->TRA[tra_index].SHIFT); - assert(shift_jerk <= shift_acc); - uint32_t acc_jer_shift = shift_acc - shift_jerk; - int32_t temp = mtg_calc_acc_preset(base, clock, tra_index, 1); - return (int32_t)(jer * ((uint64_t)temp << (acc_jer_shift * 8)) / mtg_clock_fre); -} - -void mtg_get_tra_lock_result(MTG_Type *base, uint8_t tra_index, mtg_lock_value_t *para) -{ - base->TRA[tra_index].CONTROL |= MTG_TRA_CONTROL_SW_LOCK_SET(1); - base->TRA[tra_index].CONTROL &= ~MTG_TRA_CONTROL_SW_LOCK_MASK; - para->rev = base->TRA[tra_index].LOCK_REV; - para->pos = base->TRA[tra_index].LOCK_POS; - para->vel = base->TRA[tra_index].LOCK_VEL; - para->acc = base->TRA[tra_index].LOCK_ACC; - para->time_stamp = base->TRA[tra_index].LOCK_TIME; -} - -hpm_stat_t mtg_setup_event(MTG_Type *base, uint8_t event_index, mtg_event_param_t *param) -{ - assert(event_index < 4); - - switch (param->mode) { - case event_mode_across: - base->EVENT[event_index].PRESET_0 = param->preset.cross_param.cross_value_h; - base->EVENT[event_index].PRESET_1 = param->preset.cross_param.cross_value_l; - break; - case event_mode_hold: - base->EVENT[event_index].PRESET_0 = param->preset.hold_param.hold_value_h; - base->EVENT[event_index].PRESET_1 = param->preset.hold_param.hold_value_l; - base->EVENT[event_index].PRESET_2 = param->preset.hold_param.error_limit; - base->EVENT[event_index].PRESET_3 = param->preset.hold_param.hold_clock_cnt; - break; - case event_mode_over_protect: - base->EVENT[event_index].PRESET_0 = param->preset.over_protect_param.limit_value_h; - base->EVENT[event_index].PRESET_1 = param->preset.over_protect_param.limit_value_l; - break; - case event_mode_time_match: - base->EVENT[event_index].PRESET_0 = param->preset.time_param.clock_count; - break; - default: - return status_invalid_argument; - } - - uint32_t tmp = MTG_EVENT_CONTROL_ENABLE_SET(param->enable == true ? 1 : 0) | - MTG_EVENT_CONTROL_SOURCE_MUX_SET(param->obj_postion) | - MTG_EVENT_CONTROL_OBJECT_SET(param->obj) | - MTG_EVENT_CONTROL_MODE_SET(param->mode) | - MTG_EVENT_CONTROL_DIR_SET(param->dir) | - MTG_EVENT_CONTROL_DIR_MODE_SET(param->dir_mode) | - MTG_EVENT_CONTROL_OVER_MODE_CMP_SET(param->cmp_mode) | - MTG_EVENT_CONTROL_TRIG_NUM_SET(param->trig_num) | - MTG_EVENT_CONTROL_EVENT_IRQ_EN_SET(param->irq_en); - base->EVENT[event_index].CONTROL = tmp; - - return status_success; -} - -hpm_stat_t mtg_setup_tra_limit(MTG_Type *base, uint8_t tra_index, mtg_tra_limit_param_t *param) -{ - assert(tra_index < 2); - if (param->pos_step_limit_en) { - base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SET(1); - base->TRA[tra_index].POS_STEP_MAX = param->pos_step_max; - base->TRA[tra_index].POS_STEP_MIN = param->pos_step_min; - } else { - base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK; - } - if (param->vel_step_limit_en) { - base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SET(1); - base->TRA[tra_index].VEL_STEP_MAX = param->vel_step_max; - base->TRA[tra_index].VEL_STEP_MIN = param->vel_step_min; - } else { - base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK; - } - return status_success; -} - -void mtg_setup_tra_software_pos_one_way_mode(MTG_Type *base, uint8_t tra_index, mtg_software_force_one_way_mode_t param) -{ - assert(tra_index < 2); - - base->TRA[tra_index].STEP_LIMIT_CTRL |= MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SET(1) | - MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SET(1) | - MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SET(param); -} - -void mtg_setup_tra_hardware_pos_one_way_mode(MTG_Type *base, uint8_t tra_index, mtg_hardware_force_one_way_mode_t *param) -{ - assert(tra_index < 2); - base->TRA[tra_index].STEP_LIMIT_CTRL |= MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SET(1) | - MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SET(0); - base->TRA[tra_index].VEL_LIMIT_P = param->vel_limit_p; - base->TRA[tra_index].VEL_LIMIT_N = param->vel_limit_n; -} - -void mtg_disable_tra_pos_one_way_mode(MTG_Type *base, uint8_t tra_index) -{ - base->TRA[tra_index].STEP_LIMIT_CTRL &= ~MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK; -} - -void mtg_setup_tra_vel_one_way(MTG_Type *base, uint8_t tra_index, vel_one_way_mode_t mode, bool enable) -{ - assert(tra_index < 2); - if (enable) { - switch (mode) { - case bigger_or_eq_zero: - base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET(1) | - MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SET(1); - break; - case smaller_or_eq_zero: - base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK; - base->TRA[tra_index].CONTROL |= MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET(1); - break; - } - } else { - base->TRA[tra_index].CONTROL &= ~MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK; - } -} - -void mtg_filter_get_default_filter_stage_param(mtg_filter_param_t *param) -{ - param->filter_stage_sel = MTG_FILTER_STAGE_SEL_STAGE5_SEL_SET(2)/* acc1 */ | \ - MTG_FILTER_STAGE_SEL_STAGE4_SEL_SET(1)/* acc0 */ | \ - MTG_FILTER_STAGE_SEL_STAGE3_SEL_SET(8)/* zero */ | \ - MTG_FILTER_STAGE_SEL_STAGE2_SEL_SET(4)/* pole */ | \ - MTG_FILTER_STAGE_SEL_STAGE1_SEL_SET(16)/* bypass */ | \ - MTG_FILTER_STAGE_SEL_STAGE0_SEL_SET(16) /* bypass */; - - param->filter_mot_sel = MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SET(16)/* stage4 */ | \ - MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SET(4)/* stage2 */ | \ - MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SET(16)/* stage4 */ | \ - MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SET(4)/* stage2 */; - - param->filter_time_constant_tp = 50000 / 5; - param->filter_time_constant_tz = 1000000 / 5; - param->filter_time_constant_tz_1 = 1000000 / 5; - param->filter_zero_tz_sel = 0; - param->filter_gain = MTG_FILTER_GAIN_GAIN_T0_EN_SET(1) | - MTG_FILTER_GAIN_GAIN_T1_EN_SET(0) | - MTG_FILTER_GAIN_K_SET(256); - - param->filter_stage_shift[0] = MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SET(5) | - MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SET(5) | - MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SET(5) | - MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SET(5) | - MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SET(0) | - MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SET(0) | - MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SET(0) | - MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SET(0); - - param->filter_stage_shift[1] = MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SET(7) | - MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SET(7) | - MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SET(7) | - MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SET(7); - - param->filter_param_shift = MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SET(0) | - MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SET(7) | - MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SET(6) | - MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SET(4) | - MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SET(3) | - MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SET(3) | - MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SET(5) | - MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SET(5); - - param->filter_time_shift = MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SET(7) | - MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SET(7) | - MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SET(7) | - MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SET(7); - - param->filter_ff_shift = MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SET(3) | - MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SET(3) | - MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SET(3) | - MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SET(3); - - param->rev_init_value = 0; - param->pos_init_value = 0; - param->vel_init_value = 0; - param->acc_init_value = 0; - param->err_bypass_f_i_en = true; - param->err_bypass_i_f_en = true; - param->timeout_en = true; - param->filter_error_limit_l = 0x38E38E0; - param->filter_error_limit_h = 0x38E38E0; -} - -void mtg_setup_filter(MTG_Type *base, mtg_filter_param_t *param) -{ - base->FILTER_STAGE_SEL = param->filter_stage_sel; - base->FILTER_STAGE_SHIFT0 = param->filter_stage_shift[0]; - base->FILTER_STAGE_SHIFT1 = param->filter_stage_shift[1]; - base->FILTER_MOT_SEL = param->filter_mot_sel; - base->FILTER_TIME_CONSTANT_TP = param->filter_time_constant_tp; - base->FILTER_TIME_CONSTANT_TZ = param->filter_time_constant_tz; - base->FILTER_TIME_CONSTANT_TZ_1 = param->filter_time_constant_tz_1; - base->FILTER_ZERO_TZ_SEL = param->filter_zero_tz_sel; - base->FILTER_GAIN = param->filter_gain; - base->FILTER_PARAM_SHIFT = param->filter_param_shift; - base->FILTER_TIME_SHIFT = param->filter_time_shift; - base->FILTER_FF_SHIFT = param->filter_ff_shift; - base->FILTER_REV_VALUE = param->rev_init_value; - base->FILTER_POS_VALUE = param->pos_init_value; - base->FILTER_ACC_VALUE = param->acc_init_value; - base->FILTER_VEL_VALUE = param->vel_init_value; - base->FILTER_ERROR_LIMIT_L = param->filter_error_limit_l; - base->FILTER_ERROR_LIMIT_H = param->filter_error_limit_h; - uint32_t mask = MTG_FILTER_CONTROL_ENABLE_MASK | MTG_FILTER_CONTROL_INIT_EN_MASK | MTG_FILTER_CONTROL_FF_EN_MASK | \ - MTG_FILTER_CONTROL_FF_MODE_MASK | MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK | MTG_FILTER_CONTROL_ERR_INI_MASK | \ - MTG_FILTER_CONTROL_A_EN_MASK | MTG_FILTER_CONTROL_REV_INI_MODE_MASK | MTG_FILTER_CONTROL_TIMEOUT_EN_MASK | \ - MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK | MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK | \ - MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK; - - uint32_t tmp = MTG_FILTER_CONTROL_ENABLE_SET(param->enable) | - MTG_FILTER_CONTROL_INIT_EN_SET(param->init_en) | - MTG_FILTER_CONTROL_FF_EN_SET(param->ff_en) | - MTG_FILTER_CONTROL_FF_MODE_SET(param->ff_mode) | - MTG_FILTER_CONTROL_ERR_BYPASS_EN_SET(param->err_bypass_en) | - MTG_FILTER_CONTROL_ERR_INI_SET(param->err_init) | - MTG_FILTER_CONTROL_A_EN_SET(param->acceleration_en) | - MTG_FILTER_CONTROL_REV_INI_MODE_SET(param->rev_init_value) | - MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SET(param->err_bypass_i_f_en) | - MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SET(param->err_bypass_f_i_en) | - MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SET(param->multi_err_irq_en); - base->FILTER_CONTROL &= ~mask; - base->FILTER_CONTROL |= tmp; -} - -void mtg_setup_time(MTG_Type *base, mtg_time_init_param_t *param) -{ - if (param->enable) { - if (param->index == 0) { - base->FILTER_TIME0_SW_ADJUST = param->adjust_value; - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_SEL_TIME0_MASK; - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_SEL_TIME0_SET(param->source); - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_EN_TIME0_SET(1); - } else if (param->index == 1) { - base->FILTER_TIME1_SW_ADJUST = param->adjust_value; - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_SEL_TIME1_MASK; - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_SEL_TIME1_SET(param->source); - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_EN_TIME1_SET(1); - } - } else { - if (param->index == 0) { - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_EN_TIME0_MASK; - } else if (param->index == 1) { - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_EN_TIME1_MASK; - } - } -} - -void mtg_setup_timeout(MTG_Type *base, mtg_timeout_param_t *param) -{ - if (param->enable) { - base->FILTER_TIMEOUT_CNT = param->timeout_clock_count; - base->FILTER_CONTROL |= MTG_FILTER_CONTROL_TIMEOUT_EN_SET(1); - } else { - base->FILTER_CONTROL &= ~MTG_FILTER_CONTROL_TIMEOUT_EN_MASK; - } -} - -void mtg_setup_link_cfg(MTG_Type *base, uint8_t tra_index, mtg_link_cfg_t link_cfg, mtg_tra_cmd_cfg_t *cmd_cfg) -{ - assert((tra_index < 2) && (cmd_cfg->index < 4)); - switch (cmd_cfg->index) { - case 0: - base->TRA[tra_index].LINK &= ~MTG_TRA_LINK_LINK_CFG_0_MASK; - base->TRA[tra_index].LINK |= MTG_TRA_LINK_LINK_CFG_0_SET(link_cfg); - break; - case 1: - base->TRA[tra_index].LINK &= ~MTG_TRA_LINK_LINK_CFG_1_MASK; - base->TRA[tra_index].LINK |= MTG_TRA_LINK_LINK_CFG_1_SET(link_cfg); - break; - case 2: - base->TRA[tra_index].LINK &= ~MTG_TRA_LINK_LINK_CFG_2_MASK; - base->TRA[tra_index].LINK |= MTG_TRA_LINK_LINK_CFG_2_SET(link_cfg); - break; - case 3: - base->TRA[tra_index].LINK &= ~MTG_TRA_LINK_LINK_CFG_3_MASK; - base->TRA[tra_index].LINK |= MTG_TRA_LINK_LINK_CFG_3_SET(link_cfg); - break; - } - - base->TRA[tra_index].CMD[cmd_cfg->index].JER_PRESET = cmd_cfg->jer_preset; - base->TRA[tra_index].CMD[cmd_cfg->index].ACC_PRESET = cmd_cfg->acc_preset; - base->TRA[tra_index].CMD[cmd_cfg->index].VEL_PRESET = cmd_cfg->vel_preset; - base->TRA[tra_index].CMD[cmd_cfg->index].POS_PRESET = cmd_cfg->pos_preset; - base->TRA[tra_index].CMD[cmd_cfg->index].REV_PRESET = cmd_cfg->rev_preset; - base->TRA[tra_index].CMD[cmd_cfg->index].CONTROL &= ~MTG_TRA_CMD_CONTROL_MODE_MASK; - base->TRA[tra_index].CMD[cmd_cfg->index].CONTROL &= ~MTG_TRA_CMD_CONTROL_OBJECT_MASK; - base->TRA[tra_index].CMD[cmd_cfg->index].CONTROL |= MTG_TRA_CMD_CONTROL_OBJECT_SET(cmd_cfg->object) | - MTG_TRA_CMD_CONTROL_MODE_SET(cmd_cfg->mode); -} - -void mtg_soft_event_trigger(MTG_Type *base) -{ - base->SW_EVENT = 1; - base->SW_EVENT = 0; -} - -void mtg_get_default_tra_shift(mtg_tra_shift_t *cfg) -{ - cfg->jerk_shift = 0; - cfg->acc_shift = 4; - cfg->vel_shift = 8; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c deleted file mode 100644 index 4f41e295162..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_opamp_drv.c +++ /dev/null @@ -1,218 +0,0 @@ -#include "hpm_opamp_drv.h" - -hpm_stat_t opamp_init(OPAMP_Type *opamp, opamp_cfg_t *cfg) -{ - opamp_disable(opamp); - opamp->CTRL0 = 0; - opamp_inn_pad_select(opamp, cfg->negative_input_pin); - opamp_inp_pad_select(opamp, cfg->positive_input_pin); - opamp_gain_select(opamp, cfg->gain); - opamp_miller_cap_select(opamp, cfg->miller_cap); - if (cfg->enable_phase_margin_cap) { - opamp_phase_margin_cap_enable(opamp); - } else { - opamp_phase_margin_cap_disable(opamp); - } - switch (cfg->mode) { - case mode_follow: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) == 0) { - return status_invalid_argument; - } - opamp_disconnect_vssa(opamp); - opamp_phase_margin_cap_enable(opamp); - opamp_mode_set(opamp, OPAMP_MODE_FOLLOW_KEY); - break; - case mode_invert_intern_vol: - if ((cfg->positive_input_pin & 0x04) == 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_connect_vssa(opamp); - opamp_phase_margin_cap_disable(opamp); - opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); - break; - case mode_invert_extern_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if (cfg->enable_extern_filter_cap) { - opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX1_KEY); - } else { - opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); - } - break; - case mode_invert_dac_vol: - opamp_inp_pad_select(opamp, 0x02); - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_connect_vssa(opamp); - opamp_mode_set(opamp, OPAMP_MODE_INVERT_INDEX0_KEY); - break; - case mode_non_invert_gnd_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_connect_vssa(opamp); - if (!cfg->enable_extern_filter_cap) { - if ((cfg->negative_input_pin & 0x04) == 0) { - return status_invalid_argument; - } - opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX0_KEY); - } else { - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX2_KEY); - } - break; - case mode_non_invert_extern_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_connect_vssa(opamp); - if (!cfg->enable_extern_filter_cap) { - opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX1_KEY); - } else { - opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX3_KEY); - } - break; - case mode_non_invert_dac_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_inn_pad_select(opamp, 0x02); - opamp_connect_vssa(opamp); - opamp_mode_set(opamp, OPAMP_MODE_NON_INVERT_INDEX4_KEY); - break; - case mode_user: - opamp_mode_set(opamp, OPAMP_MODE_USER_DEFINE_KEY); - break; - default: - return status_invalid_argument; - break; - } - return status_success; -} - - -hpm_stat_t opamp_set_preset_cfg(OPAMP_Type *opamp, uint8_t preset_chn, opamp_cfg_t *cfg) -{ - if (preset_chn > OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM) { - return status_invalid_argument; - } - opamp->CFG[preset_chn].CFG0 = 0; - opamp->CFG[preset_chn].CFG1 = 0; - opamp_preset_inn_pad_select(opamp, preset_chn, cfg->negative_input_pin); - opamp_preset_inp_pad_select(opamp, preset_chn, cfg->positive_input_pin); - opamp_preset_gain_select(opamp, preset_chn, cfg->gain); - opamp_preset_miller_cap_select(opamp, preset_chn, cfg->miller_cap); - if (cfg->enable_phase_margin_cap) { - opamp_preset_phase_margin_cap_enable(opamp, preset_chn); - } else { - opamp_preset_phase_margin_cap_disable(opamp, preset_chn); - } - switch (cfg->mode) { - case mode_follow: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) == 0) { - return status_invalid_argument; - } - opamp_preset_disconnect_vssa(opamp, preset_chn); - opamp_preset_phase_margin_cap_enable(opamp, preset_chn); - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_FOLLOW_KEY); - break; - case mode_invert_intern_vol: - if ((cfg->positive_input_pin & 0x04) == 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_preset_disconnect_vssa(opamp, preset_chn); - opamp_preset_phase_margin_cap_disable(opamp, preset_chn); - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); - break; - case mode_invert_extern_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if (cfg->enable_extern_filter_cap) { - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX1_KEY); - } else { - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); - } - break; - case mode_invert_dac_vol: - opamp_preset_inp_pad_select(opamp, preset_chn, 0x02); - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_preset_disconnect_vssa(opamp, preset_chn); - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_INVERT_INDEX0_KEY); - break; - case mode_non_invert_gnd_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_preset_disconnect_vssa(opamp, preset_chn); - if (!cfg->enable_extern_filter_cap) { - if ((cfg->negative_input_pin & 0x04) == 0) { - return status_invalid_argument; - } - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX0_KEY); - } else { - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX2_KEY); - } - break; - case mode_non_invert_extern_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - if ((cfg->negative_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_preset_disconnect_vssa(opamp, preset_chn); - if (!cfg->enable_extern_filter_cap) { - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX1_KEY); - } else { - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX3_KEY); - } - break; - case mode_non_invert_dac_vol: - if ((cfg->positive_input_pin & 0x04) != 0) { - return status_invalid_argument; - } - opamp_preset_inn_pad_select(opamp, preset_chn, 0x02); - opamp_preset_disconnect_vssa(opamp, preset_chn); - opamp_preset_mode_set(opamp, preset_chn, OPAMP_MODE_NON_INVERT_INDEX4_KEY); - break; - case mode_user: - return status_success; - break; - default: - return status_invalid_argument; - break; - } - return status_success; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c deleted file mode 100644 index 669649e9f24..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pcfg_drv.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_pcfg_drv.h" -#include "hpm_soc_feature.h" - -#define PCFG_CURRENT_MEASUREMENT_STEP (50U) -#define HPM_PMU_DRV_RETRY_COUNT (5000U) - -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv) -{ - if ((mv < PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV) - || (mv > PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV)) { - return status_pcfg_ldo_out_of_range; - } - ptr->LDO1P1 = (ptr->LDO1P1 & ~PCFG_LDO1P1_VOLT_MASK) | PCFG_LDO1P1_VOLT_SET(mv); - return status_success; -} - -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv) -{ - uint32_t retry = 0; - if ((mv < PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV) - || (mv > PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV)) { - return status_pcfg_ldo_out_of_range; - } - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - ptr->LDO2P5 = PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(mv); - - while (!PCFG_LDO2P5_READY_GET(ptr->LDO2P5)) { - if (retry > HPM_PMU_DRV_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_PMU_DRV_RETRY_COUNT) { - return status_timeout; - } - - return status_success; -} - -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr) -{ - uint32_t retry = 0; - while (!pcfg_dcdc_is_measure_current_valid(ptr)) { - if (retry > HPM_PMU_DRV_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_PMU_DRV_RETRY_COUNT) { - return 0; - } - - return PCFG_DCDC_CURRENT_LEVEL_GET(ptr->DCDC_CURRENT) * PCFG_CURRENT_MEASUREMENT_STEP; -} - -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv) -{ - hpm_stat_t stat = status_success; - if ((mv < PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV) || (mv > PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV)) { - return status_invalid_argument; - } - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_VOLT_MASK) | PCFG_DCDC_MODE_VOLT_SET(mv); - return stat; -} - -#define PCFG_RC24M_FREQ (24000000UL) -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config) -{ - uint32_t calculated_freq; - uint16_t mul = 1; - uint16_t div = 1; - - if (!(config->freq_in_hz < PCFG_RC24M_FREQ)) { - /* calculate div */ - div = PCFG_RC24M_FREQ / config->freq_in_hz; - } - calculated_freq = PCFG_RC24M_FREQ / div; - while (calculated_freq < config->freq_in_hz) { - calculated_freq *= (mul++); - } - ptr->TRACK_TARGET = PCFG_TRACK_TARGET_PRE_DIV_SET(div - 1) - | PCFG_TRACK_TARGET_TARGET_SET(mul - 1); - ptr->RC24M_TRACK = PCFG_RC24M_TRACK_SEL24M_SET(config->reference) - | PCFG_RC24M_TRACK_RETURN_SET(config->return_to_default_on_xtal_loss) - | PCFG_RC24M_TRACK_TRACK_SET(config->free_run); -} - -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv) -{ - hpm_stat_t stat = status_success; - if ((mv < PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV) || (mv > PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV)) { - return status_invalid_argument; - } - ptr->DCDC_LPMODE = (ptr->DCDC_LPMODE & ~PCFG_DCDC_LPMODE_STBY_VOLT_MASK) | PCFG_DCDC_LPMODE_STBY_VOLT_SET(mv); - return stat; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c deleted file mode 100644 index c712f4fce42..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdm_drv.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_pdm_drv.h" -#define PDM_WORKING_CLOCK_FREQ_IN_HZ (48000UL) - -void pdm_get_default_config(PDM_Type *ptr, pdm_config_t *config) -{ - (void) ptr; - config->sof_at_ref_clk_falling_edge = true; - config->bypass_pdm_clk_div = false; - config->enable_pdm_clk_out = true; - config->pdm_clk_div = 3; - config->capture_delay = 1; - config->dec_after_cic = 3; - config->post_scale = 12; - config->sigma_delta_order = PDM_CIC_SIGMA_DELTA_ORDER_6; - config->cic_dec_ratio = 64; - config->enable_hpf = true; -} - -hpm_stat_t pdm_init(PDM_Type *ptr, pdm_config_t *config) -{ - if (pdm_is_running(ptr)) { - pdm_stop(ptr); - } - /* pdm_software_reset(ptr); */ - - /* ptr->CTRL = PDM_CTRL_DIS_CLK_GATE_MASK; */ - ptr->CTRL = PDM_CTRL_SOF_FEDGE_SET(config->sof_at_ref_clk_falling_edge) - | PDM_CTRL_DEC_AFT_CIC_SET(config->dec_after_cic) - | PDM_CTRL_CAPT_DLY_SET(config->capture_delay) - | PDM_CTRL_PDM_CLK_HFDIV_SET(config->pdm_clk_div) - | PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(config->bypass_pdm_clk_div) - | PDM_CTRL_PDM_CLK_OE_SET(config->enable_pdm_clk_out) - | PDM_CTRL_HPF_EN_SET(config->enable_hpf); - - ptr->CH_CTRL = 0xF000FF; - ptr->CH_CFG = 0x50000; - ptr->CIC_CFG = PDM_CIC_CFG_POST_SCALE_SET(config->post_scale) - | PDM_CIC_CFG_SGD_SET(config->sigma_delta_order) - | PDM_CIC_CFG_CIC_DEC_RATIO_SET(config->cic_dec_ratio); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c deleted file mode 100644 index 5980406a66a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pdma_drv.c +++ /dev/null @@ -1,926 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_pdma_drv.h" - -#define PDMA_SCALE_FRAC_BITS 12 -/* x_offset might need to be adjusted when scaling YUV format */ -#define PDMA_YUV_SCALE_DEFAULT_X_OFFSET (0x800) - -void pdma_set_block_size(PDMA_Type *ptr, pdma_blocksize_t size) -{ - ptr->CTRL = (ptr->CTRL & ~PDMA_CTRL_BS16_MASK) - | ((size == pdma_blocksize_16x16) ? PDMA_CTRL_BS16_MASK : 0); -} - -void pdma_enable_plane(PDMA_Type *ptr, pdma_plane_t enable_plane, bool enable) -{ - uint32_t mask; - switch (enable_plane) { - case pdma_plane_both: - mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); - break; - case pdma_plane_src: - mask = PDMA_CTRL_P0_EN_MASK; - break; - case pdma_plane_dst: - mask = PDMA_CTRL_P1_EN_MASK; - break; - default: - mask = 0; - break; - } - if (!mask) { - return; - } - if (enable) { - ptr->CTRL |= mask; - } else { - ptr->CTRL &= ~mask; - } -} - -void pdma_enable_irq(PDMA_Type *ptr, uint32_t mask, bool enable) -{ - mask &= PDMA_CTRL_AXIERR_IRQ_EN_MASK | PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK; - if (enable) { - ptr->CTRL |= mask | PDMA_CTRL_IRQ_EN_MASK; - } else { - ptr->CTRL &= ~mask; - } -} - -void pdma_get_default_config(PDMA_Type *ptr, pdma_config_t *config, display_pixel_format_t pixel_format) -{ - (void) ptr; - config->block_size = pdma_blocksize_16x16; - config->enable_plane = pdma_plane_src; - - if (display_pixel_format_is_yuv_format(pixel_format)) { - if (pixel_format == display_pixel_format_ycbcr422) { - config->byteorder = display_byteorder_a2a3a0a1; - } else { - config->byteorder = display_byteorder_a0a1a2a3; - } - } else { - config->byteorder = display_byteorder_a3a2a1a0; - } -} - -void pdma_get_default_plane_config(PDMA_Type *ptr, pdma_plane_config_t *config, display_pixel_format_t pixel_format) -{ - (void) ptr; - config->swap_byte3_byte1 = false; - config->byteorder = display_byteorder_a3a2a1a0; - config->use_background_as_clear = true; - config->flip = pdma_flip_none; - config->rotate = pdma_rotate_0_degree; - config->x_dec = pdma_decimation_by_1; - config->y_dec = pdma_decimation_by_1; - config->byte_swap = false; - config->pixel_format = pixel_format; - config->buffer = 0; - config->background = 0xFFFFFFFF; - config->x_scale = PDMA_MAKE_SCALE_SET(1, 0); - config->y_scale = PDMA_MAKE_SCALE_SET(1, 0); - config->x_offset = 0; - config->y_offset = 0; - config->colorkey_high = 0; - config->colorkey_low = 0xFFFFFF; - config->width = 0; - config->height = 0; - config->pitch = 0; - - switch (pixel_format) { - case display_pixel_format_yuv422: - config->ycbcr_mode = false; - config->bypass_colorspace_conversion = false; - break; - case display_pixel_format_ycbcr422: - config->ycbcr_mode = true; - config->bypass_colorspace_conversion = false; - break; - default: - config->ycbcr_mode = false; - config->bypass_colorspace_conversion = true; - break; - } -} - -void pdma_get_default_yuv2rgb_coef_config(PDMA_Type *ptr, display_yuv2rgb_coef_t *yuv2rgb_coef, display_pixel_format_t source_format) -{ - (void) ptr; - /* Two plane share one YUV2RGB_COEF, not support one plane format is yuv422 and another is ycbcr422 */ - - switch (source_format) { - case display_pixel_format_yuv422: - yuv2rgb_coef->c0 = 0x100; - yuv2rgb_coef->uv_offset = 0; - yuv2rgb_coef->y_offset = 0; - yuv2rgb_coef->c1 = 0x123; - yuv2rgb_coef->c2 = 0x76B; - yuv2rgb_coef->c3 = 0x79C; - yuv2rgb_coef->c4 = 0x208; - break; - case display_pixel_format_ycbcr422: - yuv2rgb_coef->c0 = 0x12A; - yuv2rgb_coef->uv_offset = 0x180; - yuv2rgb_coef->y_offset = 0x1F0; - yuv2rgb_coef->c1 = 0x198; - yuv2rgb_coef->c2 = 0x730; - yuv2rgb_coef->c3 = 0x79C; - yuv2rgb_coef->c4 = 0x204; - break; - default: - yuv2rgb_coef->c0 = 0; - yuv2rgb_coef->uv_offset = 0; - yuv2rgb_coef->y_offset = 0; - yuv2rgb_coef->c1 = 0; - yuv2rgb_coef->c2 = 0; - yuv2rgb_coef->c3 = 0; - yuv2rgb_coef->c4 = 0; - break; - } -} - -void pdma_get_default_output_config(PDMA_Type *ptr, pdma_output_config_t *config, display_pixel_format_t pixel_format) -{ - (void) ptr; - uint8_t i; - config->alphablend.dst_alpha = 0x0; - config->alphablend.src_alpha = 0x0; - config->alphablend.src_alpha_op = display_alpha_op_invalid; - config->alphablend.dst_alpha_op = display_alpha_op_invalid; - config->alphablend.mode = display_alphablend_mode_plus; - config->pixel_format = pixel_format; - config->buffer = 0; - for (i = 0; i < PDMA_SOC_PS_MAX_COUNT; i++) { - config->plane[i].x = 0; - config->plane[i].y = 0; - config->plane[i].width = 0; - config->plane[i].height = 0; - } - config->width = 0; - config->height = 0; - config->pitch = 0; - - switch (pixel_format) { - case display_pixel_format_yuv422: - config->rgb2yuv_config.enable = true; - config->rgb2yuv_config.ycbcr_mode = false; - config->rgb2yuv_config.c0 = 0x4D; - config->rgb2yuv_config.uv_offset = 0; - config->rgb2yuv_config.y_offset = 0; - config->rgb2yuv_config.c1 = 0x96; - config->rgb2yuv_config.c2 = 0x1D; - config->rgb2yuv_config.c3 = 0x7DA; - config->rgb2yuv_config.c4 = 0x7B6; - config->rgb2yuv_config.c5 = 0x70; - config->rgb2yuv_config.c6 = 0x9D; - config->rgb2yuv_config.c7 = 0x77C; - config->rgb2yuv_config.c8 = 0x7E6; - break; - case display_pixel_format_ycbcr422: - config->rgb2yuv_config.enable = true; - config->rgb2yuv_config.ycbcr_mode = true; - config->rgb2yuv_config.c0 = 0x42; - config->rgb2yuv_config.uv_offset = 0x80; - config->rgb2yuv_config.y_offset = 0x10; - config->rgb2yuv_config.c1 = 0x81; - config->rgb2yuv_config.c2 = 0x19; - config->rgb2yuv_config.c3 = 0x7DA; - config->rgb2yuv_config.c4 = 0x7B5; - config->rgb2yuv_config.c5 = 0x70; - config->rgb2yuv_config.c6 = 0x70; - config->rgb2yuv_config.c7 = 0x7A2; - config->rgb2yuv_config.c8 = 0x7EE; - break; - default: - config->rgb2yuv_config.enable = false; - config->rgb2yuv_config.ycbcr_mode = false; - config->rgb2yuv_config.c0 = 0; - config->rgb2yuv_config.uv_offset = 0; - config->rgb2yuv_config.y_offset = 0; - config->rgb2yuv_config.c1 = 0; - config->rgb2yuv_config.c2 = 0; - config->rgb2yuv_config.c3 = 0; - config->rgb2yuv_config.c4 = 0; - config->rgb2yuv_config.c5 = 0; - config->rgb2yuv_config.c6 = 0; - config->rgb2yuv_config.c7 = 0; - config->rgb2yuv_config.c8 = 0; - break; - } -} - -void pdma_stop(PDMA_Type *ptr) -{ - ptr->CTRL &= ~PDMA_CTRL_PDMA_EN_MASK; - pdma_software_reset(ptr); - ptr->STAT = 0x21F; -} - -void pdma_init(PDMA_Type *ptr, pdma_config_t *config) -{ - uint32_t mask; - pdma_stop(ptr); - switch (config->enable_plane) { - case pdma_plane_both: - mask = (PDMA_CTRL_P0_EN_MASK | PDMA_CTRL_P1_EN_MASK); - break; - case pdma_plane_dst: - mask = PDMA_CTRL_P1_EN_MASK; - break; - case pdma_plane_src: - mask = PDMA_CTRL_P0_EN_MASK; - break; - default: - mask = 0; - break; - } -#if defined(PDMA_SOC_SUPPORT_BS16) && (PDMA_SOC_SUPPORT_BS16 == 1) - if (config->block_size == pdma_blocksize_16x16) { - mask |= PDMA_CTRL_BS16_MASK; - } -#endif - - ptr->CTRL = PDMA_CTRL_PACK_DIR_SET(config->byteorder) | mask; -} - -static uint32_t pdma_pixel_format(display_pixel_format_t display_format, bool is_out_plane) -{ - switch (display_format) { - case display_pixel_format_rgb565: - return 0xE; - case display_pixel_format_argb8888: - return 0; - case display_pixel_format_yuv422: - return 0x13; - case display_pixel_format_ycbcr422: - return is_out_plane ? 0x12 : 0x13; - default: - return 0; - } -} - -void pdma_config_planes(PDMA_Type *ptr, void *plane_src_config, void *plane_dst_config, void *yuv2rgb_coef) -{ - uint32_t pitch; - uint32_t format; - - assert((plane_src_config != NULL) || (plane_dst_config != NULL)); - - pdma_plane_config_t *plane_src = (pdma_plane_config_t *)plane_src_config; - pdma_plane_config_t *plane_dst = (pdma_plane_config_t *)plane_dst_config; - display_yuv2rgb_coef_t *yuv2rgb = (display_yuv2rgb_coef_t *)yuv2rgb_coef; - - if (plane_src != NULL) { - assert((plane_src->bypass_colorspace_conversion) || (yuv2rgb != NULL)); - } - if (plane_dst != NULL) { - assert((plane_dst->bypass_colorspace_conversion) || (yuv2rgb != NULL)); - } - if ((plane_src != NULL) && (plane_dst != NULL)) { - assert(!(display_pixel_format_is_yuv_format(plane_src->pixel_format) && display_pixel_format_is_yuv_format(plane_dst->pixel_format)) - || (plane_src->pixel_format == plane_dst->pixel_format)); - } - - if (plane_src != NULL) { - if (plane_src->pitch == 0) { - pitch = display_get_pitch_length_in_byte(plane_src->pixel_format, plane_src->width); - } else { - pitch = plane_src->pitch; - } - format = pdma_pixel_format(plane_src->pixel_format, false); - ptr->PS[pdma_plane_src].BUF = PDMA_PS_BUF_ADDR_SET((uint32_t) plane_src->buffer); - ptr->PS[pdma_plane_src].PITCH = PDMA_PS_PITCH_BYTELEN_SET(pitch); - ptr->PS[pdma_plane_src].BKGD = PDMA_PS_BKGD_COLOR_SET(plane_src->background); - ptr->PS[pdma_plane_src].SCALE = PDMA_PS_SCALE_X_SET(plane_src->x_scale) - | PDMA_PS_SCALE_Y_SET(plane_src->y_scale); - ptr->PS[pdma_plane_src].OFFSET = PDMA_PS_OFFSET_X_SET(plane_src->x_offset) - | PDMA_PS_OFFSET_Y_SET(plane_src->y_offset); - ptr->PS[pdma_plane_src].CLRKEY_LOW = PDMA_PS_CLRKEY_LOW_LIMIT_SET(plane_src->colorkey_low); - ptr->PS[pdma_plane_src].CLRKEY_HIGH = PDMA_PS_CLRKEY_HIGH_LIMIT_SET(plane_src->colorkey_high); - ptr->PS[pdma_plane_src].ORG = PDMA_PS_ORG_HIGHT_SET(plane_src->height) - | PDMA_PS_ORG_WIDTH_SET(plane_src->width); - ptr->PS[pdma_plane_src].CTRL = PDMA_PS_CTRL_INB13_SWAP_SET(plane_src->swap_byte3_byte1) - | PDMA_PS_CTRL_PACK_DIR_SET(plane_src->byteorder) - | PDMA_PS_CTRL_BKGCL4CLR_SET(plane_src->use_background_as_clear) - | PDMA_PS_CTRL_YCBCR_MODE_SET(plane_src->ycbcr_mode) - | PDMA_PS_CTRL_BYPASS_SET(plane_src->bypass_colorspace_conversion) - | ((plane_src->flip << PDMA_PS_CTRL_HFLIP_SHIFT) - & (PDMA_PS_CTRL_VFLIP_MASK | PDMA_PS_CTRL_HFLIP_MASK)) - | PDMA_PS_CTRL_ROTATE_SET(plane_src->rotate) - | PDMA_PS_CTRL_DECY_SET(plane_src->y_dec) - | PDMA_PS_CTRL_DECX_SET(plane_src->x_dec) - | PDMA_PS_CTRL_HW_BYTE_SWAP_SET(plane_src->byte_swap) - | PDMA_PS_CTRL_FORMAT_SET(format); - } - - if (plane_dst != NULL) { - if (plane_dst->pitch == 0) { - pitch = display_get_pitch_length_in_byte(plane_src->pixel_format, plane_src->width); - } else { - pitch = plane_dst->pitch; - } - format = pdma_pixel_format(plane_dst->pixel_format, false); - ptr->PS[pdma_plane_dst].BUF = PDMA_PS_BUF_ADDR_SET((uint32_t) plane_dst->buffer); - ptr->PS[pdma_plane_dst].PITCH = PDMA_PS_PITCH_BYTELEN_SET(pitch); - ptr->PS[pdma_plane_dst].BKGD = PDMA_PS_BKGD_COLOR_SET(plane_dst->background); - ptr->PS[pdma_plane_dst].SCALE = PDMA_PS_SCALE_X_SET(plane_dst->x_scale) - | PDMA_PS_SCALE_Y_SET(plane_dst->y_scale); - ptr->PS[pdma_plane_dst].OFFSET = PDMA_PS_OFFSET_X_SET(plane_dst->x_offset) - | PDMA_PS_OFFSET_Y_SET(plane_dst->y_offset); - ptr->PS[pdma_plane_dst].CLRKEY_LOW = PDMA_PS_CLRKEY_LOW_LIMIT_SET(plane_dst->colorkey_low); - ptr->PS[pdma_plane_dst].CLRKEY_HIGH = PDMA_PS_CLRKEY_HIGH_LIMIT_SET(plane_dst->colorkey_high); - ptr->PS[pdma_plane_dst].ORG = PDMA_PS_ORG_HIGHT_SET(plane_dst->height) - | PDMA_PS_ORG_WIDTH_SET(plane_dst->width); - ptr->PS[pdma_plane_dst].CTRL = PDMA_PS_CTRL_INB13_SWAP_SET(plane_dst->swap_byte3_byte1) - | PDMA_PS_CTRL_PACK_DIR_SET(plane_dst->byteorder) - | PDMA_PS_CTRL_BKGCL4CLR_SET(plane_dst->use_background_as_clear) - | PDMA_PS_CTRL_YCBCR_MODE_SET(plane_dst->ycbcr_mode) - | PDMA_PS_CTRL_BYPASS_SET(plane_dst->bypass_colorspace_conversion) - | ((plane_dst->flip << PDMA_PS_CTRL_HFLIP_SHIFT) - & (PDMA_PS_CTRL_VFLIP_MASK | PDMA_PS_CTRL_HFLIP_MASK)) - | PDMA_PS_CTRL_ROTATE_SET(plane_dst->rotate) - | PDMA_PS_CTRL_DECY_SET(plane_dst->y_dec) - | PDMA_PS_CTRL_DECX_SET(plane_dst->x_dec) - | PDMA_PS_CTRL_HW_BYTE_SWAP_SET(plane_dst->byte_swap) - | PDMA_PS_CTRL_FORMAT_SET(format); - } - - if (yuv2rgb != NULL) { - ptr->YUV2RGB_COEF0 = PDMA_YUV2RGB_COEF0_C0_SET(yuv2rgb->c0) - | PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(yuv2rgb->uv_offset) - | PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(yuv2rgb->y_offset); - ptr->YUV2RGB_COEF1 = PDMA_YUV2RGB_COEF1_C1_SET(yuv2rgb->c1) - | PDMA_YUV2RGB_COEF1_C4_SET(yuv2rgb->c4); - ptr->YUV2RGB_COEF2 = PDMA_YUV2RGB_COEF2_C2_SET(yuv2rgb->c2) - | PDMA_YUV2RGB_COEF2_C3_SET(yuv2rgb->c3); - } -} - -void pdma_config_output(PDMA_Type *ptr, pdma_output_config_t *config) -{ - uint32_t pitch; - uint32_t format; - - if (config->pitch == 0) { - pitch = display_get_pitch_length_in_byte(config->pixel_format, - config->width); - } else { - pitch = config->pitch; - } - format = pdma_pixel_format(config->pixel_format, true); - ptr->OUT_BUF = PDMA_OUT_BUF_ADDR_SET((uint32_t) config->buffer); - ptr->OUT_PITCH = PDMA_OUT_PITCH_BYTELEN_SET(pitch); - ptr->OUT_LRC = PDMA_OUT_LRC_X_SET(config->width) - | PDMA_OUT_LRC_Y_SET(config->height); - ptr->OUT_PS[0].ULC = PDMA_OUT_PS_ULC_X_SET(config->plane[0].x) - | PDMA_OUT_PS_ULC_Y_SET(config->plane[0].y); - ptr->OUT_PS[0].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[0].x + config->plane[0].width - 1) - | PDMA_OUT_PS_LRC_Y_SET(config->plane[0].y + config->plane[0].height - 1); - ptr->OUT_PS[1].ULC = PDMA_OUT_PS_ULC_X_SET(config->plane[1].x) - | PDMA_OUT_PS_ULC_Y_SET(config->plane[1].y); - ptr->OUT_PS[1].LRC = PDMA_OUT_PS_LRC_X_SET(config->plane[1].x + config->plane[1].width - 1) - | PDMA_OUT_PS_LRC_Y_SET(config->plane[1].y + config->plane[1].height - 1); - ptr->OUT_CTRL = PDMA_OUT_CTRL_DSTALPHA_SET(config->alphablend.dst_alpha) - | PDMA_OUT_CTRL_SRCALPHA_SET(config->alphablend.src_alpha) - | PDMA_OUT_CTRL_DSTALPHA_OP_SET(config->alphablend.dst_alpha_op) - | PDMA_OUT_CTRL_SRCALPHA_OP_SET(config->alphablend.src_alpha_op) - | PDMA_OUT_CTRL_ABLEND_MODE_SET(config->alphablend.mode) - | PDMA_OUT_CTRL_FORMAT_SET(format); - - ptr->RGB2YUV_COEF0 = PDMA_RGB2YUV_COEF0_ENABLE_SET(config->rgb2yuv_config.enable) - | PDMA_RGB2YUV_COEF0_YCBCR_MODE_SET(config->rgb2yuv_config.ycbcr_mode) - | PDMA_RGB2YUV_COEF0_C0_SET(config->rgb2yuv_config.c0) - | PDMA_RGB2YUV_COEF0_UV_OFFSET_SET(config->rgb2yuv_config.uv_offset) - | PDMA_RGB2YUV_COEF0_Y_OFFSET_SET(config->rgb2yuv_config.y_offset); - ptr->RGB2YUV_COEF1 = PDMA_RGB2YUV_COEF1_C1_SET(config->rgb2yuv_config.c1) - | PDMA_RGB2YUV_COEF1_C4_SET(config->rgb2yuv_config.c4); - ptr->RGB2YUV_COEF2 = PDMA_RGB2YUV_COEF2_C2_SET(config->rgb2yuv_config.c2) - | PDMA_RGB2YUV_COEF2_C3_SET(config->rgb2yuv_config.c3); - ptr->RGB2YUV_COEF3 = PDMA_RGB2YUV_COEF3_C6_SET(config->rgb2yuv_config.c6) - | PDMA_RGB2YUV_COEF3_C5_SET(config->rgb2yuv_config.c5); - ptr->RGB2YUV_COEF4 = PDMA_RGB2YUV_COEF4_C8_SET(config->rgb2yuv_config.c8) - | PDMA_RGB2YUV_COEF4_C7_SET(config->rgb2yuv_config.c7); -} - -#define PDMA_ERROR_STATUS_MASK (PDMA_STAT_AXI_0_WRITE_ERR_MASK \ - | PDMA_STAT_AXI_1_READ_ERR_MASK \ - | PDMA_STAT_AXI_0_READ_ERR_MASK) -#define PDMA_BUSY_STATUS_MASK (PDMA_STAT_BLOCKY_MASK \ - | PDMA_STAT_BLOCKX_MASK) - -hpm_stat_t pdma_check_status(PDMA_Type *ptr, uint32_t *status) -{ - uint32_t stat = ptr->STAT; - if (stat & PDMA_BUSY_STATUS_MASK) { - if (status) { - *status = stat; - } - return status_pdma_busy; - } - if (stat & PDMA_ERROR_STATUS_MASK) { - if (status) { - *status = stat; - } - ptr->STAT = PDMA_ERROR_STATUS_MASK; - return status_pdma_error; - } - if ((stat & PDMA_STAT_PDMA_DONE_MASK) == PDMA_STAT_PDMA_DONE_MASK) { - return status_pdma_done; - } - return status_pdma_idle; -} - -hpm_stat_t pdma_fill_color(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, - uint32_t width, uint32_t height, - uint32_t color, uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status) -{ - pdma_config_t config; - pdma_plane_config_t plane_src; - pdma_plane_config_t plane_dst; - display_yuv2rgb_coef_t yuv2rgb_coef; - pdma_output_config_t output; - - if (((display_pixel_format_is_yuv_format(format)) && (width & 1)) - || !(width > 8 || height > 8)) { - return status_invalid_argument; - } - - pdma_get_default_config(ptr, &config, format); - pdma_get_default_plane_config(ptr, &plane_src, format); - pdma_get_default_plane_config(ptr, &plane_dst, format); - pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); - pdma_get_default_output_config(ptr, &output, format); - - config.enable_plane = pdma_plane_both; - if (width <= 16) { - config.block_size = pdma_blocksize_8x8; - } else { - config.block_size = pdma_blocksize_16x16; - } - pdma_init(ptr, &config); - - plane_src.buffer = dst; - plane_src.width = 1; - plane_src.height = 1; - plane_src.background = 0; - - plane_dst.buffer = dst; - plane_dst.width = 1; - plane_dst.height = 1; - plane_dst.background = (alpha << 24) | (color & ~(0xFF << 24)); - pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); - - output.buffer = dst; - output.plane[pdma_plane_dst].x = 0; - output.plane[pdma_plane_dst].y = 0; - output.plane[pdma_plane_dst].width = width; - output.plane[pdma_plane_dst].height = height; - output.pitch = display_get_pitch_length_in_byte(format, dst_width); - - output.alphablend.mode = display_alphablend_mode_clear; - - output.width = width; - output.height = height; - - pdma_config_output(ptr, &output); - pdma_start(ptr); - if (wait) { - hpm_stat_t stat; - do { - stat = pdma_check_status(ptr, status); - } while ((stat != status_pdma_done) && (stat != status_pdma_error)); - pdma_stop(ptr); - return stat; - } - return status_success; -} - -hpm_stat_t pdma_flip_rotate(PDMA_Type *ptr, uint32_t dst, uint32_t dst_width, - uint32_t src, uint32_t src_width, uint32_t x, uint32_t y, - uint32_t width, uint32_t height, - pdma_flip_t flip, pdma_rotate_t rotate, uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status) -{ - pdma_config_t config; - pdma_plane_config_t plane_src; - pdma_plane_config_t plane_dst; - display_yuv2rgb_coef_t yuv2rgb_coef; - pdma_output_config_t output; - - if ((width + x > dst_width) - /* YUV422 requires width to be 2-pixel aligned */ - || ((display_pixel_format_is_yuv_format(format)) && (width & 1)) - || !(width > 8 || height > 8)) { - return status_invalid_argument; - } - - pdma_get_default_config(ptr, &config, format); - pdma_get_default_plane_config(ptr, &plane_src, format); - pdma_get_default_plane_config(ptr, &plane_dst, format); - pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); - pdma_get_default_output_config(ptr, &output, format); - - config.enable_plane = pdma_plane_both; - if (width <= 16) { - config.block_size = pdma_blocksize_8x8; - } else { - config.block_size = pdma_blocksize_16x16; - } - pdma_init(ptr, &config); - - plane_src.buffer = src; - plane_src.height = height; - plane_src.width = width; - plane_src.pitch = display_get_pitch_length_in_byte(format, src_width); - plane_src.flip = flip; - plane_src.rotate = rotate; - - plane_dst.buffer = src; - plane_dst.height = 1; - plane_dst.width = 1; - plane_dst.pitch = display_get_pitch_length_in_byte(format, dst_width); - plane_dst.flip = pdma_flip_none; - plane_dst.rotate = pdma_rotate_0_degree; - pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); - - output.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); - - output.alphablend.src_alpha = alpha; - output.alphablend.src_alpha_op = display_alpha_op_override; - output.alphablend.mode = display_alphablend_mode_src_over; - - output.plane[pdma_plane_src].x = 0; - output.plane[pdma_plane_src].y = 0; - output.pitch = display_get_pitch_length_in_byte(format, dst_width); - - if ((rotate == pdma_rotate_90_degree) - || (rotate == pdma_rotate_270_degree)) { - output.width = height; - output.height = width; - output.plane[pdma_plane_src].width = height; - output.plane[pdma_plane_src].height = width; - } else { - output.plane[pdma_plane_src].width = width; - output.plane[pdma_plane_src].height = height; - output.width = width; - output.height = height; - } - - pdma_config_output(ptr, &output); - pdma_start(ptr); - if (wait) { - hpm_stat_t stat; - do { - stat = pdma_check_status(ptr, status); - } while ((stat != status_pdma_done) && (stat != status_pdma_error)); - pdma_stop(ptr); - return stat; - } - return status_success; -} - -hpm_stat_t pdma_blit(PDMA_Type *ptr, - uint32_t dst, uint32_t dst_width, - uint32_t src, uint32_t src_width, - uint32_t x, uint32_t y, uint32_t width, uint32_t height, - uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status) -{ - pdma_config_t config; - pdma_plane_config_t plane_src; - pdma_plane_config_t plane_dst; - display_yuv2rgb_coef_t yuv2rgb_coef; - pdma_output_config_t output; - - if ((width + x > dst_width) - /* YUV422 requires width to be 2-pixel aligned */ - || ((display_pixel_format_is_yuv_format(format)) && (width & 1)) - || !(width > 8 || height > 8)) { - return status_invalid_argument; - } - - pdma_get_default_config(ptr, &config, format); - pdma_get_default_plane_config(ptr, &plane_src, format); - pdma_get_default_plane_config(ptr, &plane_dst, format); - pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); - pdma_get_default_output_config(ptr, &output, format); - - config.enable_plane = pdma_plane_both; - if (width <= 16) { - config.block_size = pdma_blocksize_8x8; - } else { - config.block_size = pdma_blocksize_16x16; - } - pdma_init(ptr, &config); - - plane_src.buffer = src; - plane_src.width = width; - plane_src.height = height; - plane_src.pitch = display_get_pitch_length_in_byte(format, src_width); - plane_src.background = 0x00FFFFFF; - - plane_dst.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); - plane_dst.width = width; - plane_dst.height = height; - plane_dst.pitch = display_get_pitch_length_in_byte(format, dst_width); - pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); - - output.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); - - output.plane[pdma_plane_src].x = 0; - output.plane[pdma_plane_src].y = 0; - output.plane[pdma_plane_src].width = width; - output.plane[pdma_plane_src].height = height; - - output.plane[pdma_plane_dst].x = 0; - output.plane[pdma_plane_dst].y = 0; - output.plane[pdma_plane_dst].width = width; - output.plane[pdma_plane_dst].height = height; - - output.alphablend.src_alpha = alpha; - output.alphablend.src_alpha_op = display_alpha_op_override; - output.alphablend.mode = display_alphablend_mode_src_over; - - output.width = width; - output.height = height; - output.pitch = display_get_pitch_length_in_byte(format, dst_width); - - pdma_config_output(ptr, &output); - pdma_start(ptr); - if (wait) { - hpm_stat_t stat; - do { - stat = pdma_check_status(ptr, status); - } while ((stat != status_pdma_done) && (stat != status_pdma_error)); - pdma_stop(ptr); - return stat; - } - return status_success; -} - -static void pdma_calculate_scale(uint32_t t, uint32_t target_t, - pdma_decimation_t *dec, uint32_t *scale) -{ - uint32_t tmp; - tmp = ((t << PDMA_SCALE_FRAC_BITS) / target_t) >> PDMA_SCALE_FRAC_BITS; - if (tmp >= 16) { - *dec = pdma_decimation_by_8; - *scale = 2U << PDMA_SCALE_FRAC_BITS; - return; - } - if (tmp > 8) { - *dec = pdma_decimation_by_8; - } else if (tmp > 4) { - *dec = pdma_decimation_by_4; - } else if (tmp > 2) { - *dec = pdma_decimation_by_2; - } else { - *dec = pdma_decimation_by_1; - } - - *scale = (((t >> *dec) << PDMA_SCALE_FRAC_BITS) / target_t); - return; -} - -hpm_stat_t pdma_scale(PDMA_Type *ptr, - uint32_t dst, uint32_t dst_width, - uint32_t src, uint32_t src_width, - uint32_t x, uint32_t y, uint32_t width, uint32_t height, - uint32_t target_width, uint32_t target_height, - uint8_t alpha, - display_pixel_format_t format, - bool wait, uint32_t *status) -{ - uint32_t scale; - pdma_decimation_t dec; - - pdma_config_t config; - pdma_plane_config_t plane_src; - pdma_plane_config_t plane_dst; - display_yuv2rgb_coef_t yuv2rgb_coef; - pdma_output_config_t output; - - if ((target_width + x > dst_width) - /* YUV422 requires width to be 2-pixel aligned */ - || ((display_pixel_format_is_yuv_format(format)) && (width & 1)) - || !(width > 8 || height > 8)) { - return status_invalid_argument; - } - - pdma_get_default_config(ptr, &config, format); - pdma_get_default_plane_config(ptr, &plane_src, format); - pdma_get_default_plane_config(ptr, &plane_dst, format); - pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, format); - pdma_get_default_output_config(ptr, &output, format); - - config.enable_plane = pdma_plane_both; - if (width <= 16) { - config.block_size = pdma_blocksize_8x8; - } else { - config.block_size = pdma_blocksize_16x16; - } - pdma_init(ptr, &config); - - plane_src.buffer = src; - plane_src.width = width; - plane_src.height = height; - plane_src.pitch = display_get_pitch_length_in_byte(format, src_width); - - pdma_calculate_scale(width, target_width, &dec, &scale); - plane_src.x_scale = scale; - plane_src.x_dec = dec; - pdma_calculate_scale(height, target_height, &dec, &scale); - plane_src.y_scale = scale; - plane_src.y_dec = dec; - plane_src.background = 0x00FFFFFF; - - if (display_pixel_format_is_yuv_format(format)) { - plane_src.x_offset = PDMA_YUV_SCALE_DEFAULT_X_OFFSET; - } - - plane_dst.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); - plane_dst.width = width; - plane_dst.height = height; - plane_dst.pitch = display_get_pitch_length_in_byte(format, dst_width); - pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); - - output.buffer = dst + (y * dst_width + x) * display_get_pixel_size_in_byte(format); - - output.plane[pdma_plane_src].x = 0; - output.plane[pdma_plane_src].y = 0; - output.plane[pdma_plane_src].width = target_width; - output.plane[pdma_plane_src].height = target_height; - - output.plane[pdma_plane_dst].x = 0; - output.plane[pdma_plane_dst].y = 0; - output.plane[pdma_plane_dst].width = target_width; - output.plane[pdma_plane_dst].height = target_height; - - output.alphablend.src_alpha = alpha; - output.alphablend.src_alpha_op = display_alpha_op_override; - output.alphablend.mode = display_alphablend_mode_src_over; - - output.width = target_width; - output.height = target_height; - output.pitch = display_get_pitch_length_in_byte(format, dst_width); - - pdma_config_output(ptr, &output); - pdma_start(ptr); - if (wait) { - hpm_stat_t stat; - do { - stat = pdma_check_status(ptr, status); - } while ((stat != status_pdma_done) && (stat != status_pdma_error)); - pdma_stop(ptr); - return stat; - } - return status_success; - -} - -typedef struct pdma_buf2plane_format { - display_pixel_format_t format; - display_byteorder_t byteorder; -} pdma_buf2plane_format_t; - -static const pdma_buf2plane_format_t plane_format_tab[display_buf_format_max] = { - [display_buf_format_argb8888] = {display_pixel_format_argb8888, display_byteorder_a3a2a1a0}, - [display_buf_format_bgra8888] = {display_pixel_format_argb8888, display_byteorder_a0a1a2a3}, - [display_buf_format_rgb565] = {display_pixel_format_rgb565, display_byteorder_a3a2a1a0}, - [display_buf_format_rgb565_swap] = {display_pixel_format_rgb565, display_byteorder_a2a3a0a1}, - [display_buf_format_yuyv] = {display_pixel_format_ycbcr422, display_byteorder_a3a2a1a0}, - [display_buf_format_uyvy] = {display_pixel_format_ycbcr422, display_byteorder_a2a3a0a1}, - [display_buf_format_y8] = {display_pixel_format_y8, display_byteorder_a3a2a1a0}, -}; - -static const pdma_buf2plane_format_t out_format_tab[display_buf_format_max] = { - [display_buf_format_argb8888] = {display_pixel_format_argb8888, display_byteorder_a3a2a1a0}, - [display_buf_format_bgra8888] = {display_pixel_format_argb8888, display_byteorder_a0a1a2a3}, - [display_buf_format_rgb565] = {display_pixel_format_rgb565, display_byteorder_a3a2a1a0}, - [display_buf_format_rgb565_swap] = {display_pixel_format_rgb565, display_byteorder_a2a3a0a1}, - [display_buf_format_yuyv] = {display_pixel_format_ycbcr422, display_byteorder_a2a3a0a1}, - [display_buf_format_uyvy] = {display_pixel_format_ycbcr422, display_byteorder_a3a2a1a0}, - [display_buf_format_y8] = {display_pixel_format_y8, display_byteorder_a3a2a1a0}, -}; - -void pdma_get_default_blit_option(pdma_blit_option_t *op) -{ - op->blend = display_alphablend_mode_src_over; - op->flip = pdma_flip_none; - op->rotate = pdma_rotate_0_degree; - op->scale.x = 1.0; - op->scale.y = 1.0; - op->translate.x = 0; - op->translate.y = 0; -} - -hpm_stat_t pdma_blit_ex(PDMA_Type *ptr, - display_buf_t *dst, - display_buf_t *src, - pdma_blit_option_t *op, - bool wait, uint32_t *status) -{ - if ((!dst) || (!src) || (!src->buf) || (!dst->buf) || - (op->scale.x > 4096) || (op->scale.y > 4096) || - /* YUV422 requires width to be 2-pixel aligned */ - ((display_pixel_format_is_yuv_format(plane_format_tab[src->format].format)) && (src->width & 1)) || - ((display_pixel_format_is_yuv_format(plane_format_tab[dst->format].format)) && (dst->width & 1))) { - return status_invalid_argument; - } - - pdma_decimation_t x_dec; - pdma_decimation_t y_dec; - uint32_t x_scale; - uint32_t y_scale; - - pdma_config_t config; - pdma_plane_config_t plane_src; - pdma_plane_config_t plane_dst; - display_yuv2rgb_coef_t yuv2rgb_coef; - pdma_output_config_t output; - - pdma_calculate_scale(65536, (uint32_t)(65536 * op->scale.x), &x_dec, &x_scale); - pdma_calculate_scale(65536, (uint32_t)(65536 * op->scale.y), &y_dec, &y_scale); - - pdma_get_default_plane_config(ptr, &plane_src, plane_format_tab[src->format].format); - pdma_get_default_plane_config(ptr, &plane_dst, plane_format_tab[dst->format].format); - pdma_get_default_yuv2rgb_coef_config(ptr, &yuv2rgb_coef, plane_format_tab[src->format].format); - pdma_get_default_output_config(ptr, &output, out_format_tab[dst->format].format); - - config.enable_plane = pdma_plane_both; - config.block_size = pdma_blocksize_8x8; - config.byteorder = out_format_tab[dst->format].byteorder; - pdma_init(ptr, &config); - - plane_src.buffer = (uint32_t)src->buf; - plane_src.byteorder = plane_format_tab[src->format].byteorder; - plane_src.width = src->width; - plane_src.height = src->height; - plane_src.pitch = src->stride; - plane_src.x_scale = x_scale; - plane_src.x_dec = x_dec; - plane_src.y_scale = y_scale; - plane_src.y_dec = y_dec; - plane_src.background = 0x00000000; /* alpha must be 0 */ - plane_src.x_offset = PDMA_YUV_SCALE_DEFAULT_X_OFFSET; - plane_src.flip = op->flip; - plane_src.rotate = op->rotate; - - plane_dst.buffer = (uint32_t)dst->buf; - plane_dst.byteorder = plane_format_tab[dst->format].byteorder; - plane_dst.width = dst->width; - plane_dst.height = dst->height; - plane_dst.pitch = dst->stride; - pdma_config_planes(ptr, &plane_src, &plane_dst, &yuv2rgb_coef); - - output.buffer = plane_dst.buffer; - output.plane[pdma_plane_src].x = op->translate.x; - output.plane[pdma_plane_src].y = op->translate.y; - - /* - * aligned to lower right of dst window and non-overlapping area is filled by background of src. - * so alpha that background of src must be 0. - */ - output.plane[pdma_plane_src].width = dst->width - op->translate.x; - output.plane[pdma_plane_src].height = dst->height - op->translate.y; - - output.plane[pdma_plane_dst].x = 0; - output.plane[pdma_plane_dst].y = 0; - output.plane[pdma_plane_dst].width = plane_dst.width; - output.plane[pdma_plane_dst].height = plane_dst.height; - - output.alphablend.src_alpha = src->alpha.val; - output.alphablend.src_alpha_op = src->alpha.op; - output.alphablend.dst_alpha = dst->alpha.val; - output.alphablend.dst_alpha_op = dst->alpha.op; - output.alphablend.mode = op->blend; - - output.width = plane_dst.width; - output.height = plane_dst.height; - output.pitch = plane_dst.pitch; - - pdma_config_output(ptr, &output); - pdma_start(ptr); - if (wait) { - hpm_stat_t stat; - do { - stat = pdma_check_status(ptr, status); - } while ((stat != status_pdma_done) && (stat != status_pdma_error)); - pdma_stop(ptr); - return stat; - } - return status_success; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c deleted file mode 100644 index 74b959b0d30..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pixelmux_drv.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_pixelmux_drv.h" - -void pixelmux_rgb_data_source_enable(pixelmux_rgb_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_RGB_SEL_MASK) | - PIXELMUX_PIXMUX_RGB_EN_MASK | PIXELMUX_PIXMUX_RGB_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_rgb_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_RGB_SEL_MASK; -} - -void pixelmux_gwc1_data_source_enable(pixelmux_gwc1_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_GWC1_SEL_MASK) | - PIXELMUX_PIXMUX_GWC1_EN_MASK | PIXELMUX_PIXMUX_GWC1_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_gwc1_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_GWC1_EN_MASK; -} - -void pixelmux_gwc0_data_source_enable(pixelmux_gwc0_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_GWC0_SEL_MASK) | - PIXELMUX_PIXMUX_GWC0_EN_MASK | PIXELMUX_PIXMUX_GWC0_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_gwc0_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_GWC0_EN_MASK; -} - -void pixelmux_lvb_di1_data_source_enable(pixelmux_lvb_di1_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) | - PIXELMUX_PIXMUX_LVB_DI1_EN_MASK | PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_lvb_di1_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_LVB_DI1_EN_MASK; -} - -void pixelmux_lvb_di0_data_source_enable(pixelmux_lvb_di0_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) | - PIXELMUX_PIXMUX_LVB_DI0_EN_MASK | PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_lvb_di0_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_LVB_DI0_EN_MASK; -} - -void pixelmux_mipi_dsi1_data_source_enable(pixelmux_mipi_dsi1_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_DSI1_SEL_MASK) | - PIXELMUX_PIXMUX_DSI1_EN_MASK | PIXELMUX_PIXMUX_DSI1_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_mipi_dsi1_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_DSI1_EN_MASK; -} - -void pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_DSI0_SEL_MASK) | - PIXELMUX_PIXMUX_DSI0_EN_MASK | PIXELMUX_PIXMUX_DSI0_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_mipi_dsi0_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_DSI0_EN_MASK; -} - -void pixelmux_mipi_dsi1_set_data_type(pixelmux_mipi_dsi_data_type_t type) -{ - - HPM_PIXEL_MUX->DSI_SETTING[1] = PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(0x01u<DSI_SETTING[0] = PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(0x01u<PIXMUX & ~PIXELMUX_PIXMUX_CAM1_SEL_MASK) | - PIXELMUX_PIXMUX_CAM1_EN_MASK | PIXELMUX_PIXMUX_CAM1_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_cam1_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_CAM1_EN_MASK; -} - -void pixelmux_cam0_data_source_enable(pixelmux_cam0_select_t src) -{ - uint32_t reg_val = (HPM_PIXEL_MUX->PIXMUX & ~PIXELMUX_PIXMUX_CAM0_SEL_MASK) | - PIXELMUX_PIXMUX_CAM0_EN_MASK | PIXELMUX_PIXMUX_CAM0_SEL_SET(src); - HPM_PIXEL_MUX->PIXMUX = reg_val; -} - -void pixelmux_cam0_data_source_disable(void) -{ - HPM_PIXEL_MUX->PIXMUX &= ~PIXELMUX_PIXMUX_CAM0_EN_MASK; -} - -hpm_stat_t pixelmux_lvds_phy_calc_pll_cfg(uint32_t pixel_freq_hz, bool is_split, lvds_phy_clk_param_t *param) -{ - uint32_t hsclk_freq_hz; - uint32_t data_rate_div4; - uint64_t fvco_freq_hz; - uint32_t fvco_fraction_freq_hz; - uint32_t lvds_rpck = is_split ? pixel_freq_hz / 2 : pixel_freq_hz; - uint32_t lane_data_rate_hz = lvds_rpck * 7; - uint32_t rate_lvds; - uint32_t pfd_freq_hz; - uint32_t pll_div_integer; /*pll_div[14:10]*/ - uint32_t pll_div_fraction; /*pll_div[9:0]*/ - int refclk_div; - - if (lvds_rpck / 16 > PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX || - lvds_rpck < PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN) { - return status_invalid_argument; - } - - if (lane_data_rate_hz < PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MIN / (8 * 4) || - lane_data_rate_hz > PIXELMUX_LVDS_TX_PHY_DATA_LANE_FREQ_MAX) { - return status_invalid_argument; - } - - data_rate_div4 = 1; - if (lane_data_rate_hz > PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MAX / 4) { - data_rate_div4 = 0; - } - - hsclk_freq_hz = data_rate_div4 ? lane_data_rate_hz * 4 : lane_data_rate_hz; - rate_lvds = 0; - fvco_freq_hz = 0; - while (rate_lvds <= 3) { - fvco_freq_hz = (uint64_t)hsclk_freq_hz * (1<= PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MIN) { - break; - } - rate_lvds++; - } - - if (rate_lvds > 3 || fvco_freq_hz > PIXELMUX_LVDS_TX_PHY_VCO_FREQ_MAX) { - return status_invalid_argument; - } - - refclk_div = 15; - pfd_freq_hz = 0; - while (refclk_div >= 0) { - pfd_freq_hz = lvds_rpck / (refclk_div + 1); - if (pfd_freq_hz >= PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN) { - break; - } - refclk_div--; - } - - if (refclk_div < 0 || pfd_freq_hz < PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MIN) { - return status_invalid_argument; - } - - while (refclk_div >= 0 && pfd_freq_hz < PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX) { - pfd_freq_hz = lvds_rpck / (refclk_div + 1); - if (fvco_freq_hz / 8 / pfd_freq_hz <= 23) { - break; - } - refclk_div--; - } - - if (refclk_div < 0 || pfd_freq_hz > PIXELMUX_LVDS_TX_PHY_PFD_FREQ_MAX || - (fvco_freq_hz / 8 / pfd_freq_hz) > 23 || (fvco_freq_hz / 8 / pfd_freq_hz) < 6) { - return status_invalid_argument; - } - - pll_div_integer = fvco_freq_hz / 8 / pfd_freq_hz; - fvco_fraction_freq_hz = fvco_freq_hz - pfd_freq_hz * pll_div_integer * 8; - pll_div_fraction = (fvco_fraction_freq_hz * 1024) / 8 / pfd_freq_hz; - - param->reg.rate_lvds = rate_lvds; - param->reg.data_rate_div4 = data_rate_div4; - param->reg.refclk_div = refclk_div; - param->reg.pll_div = pll_div_integer<<10 | pll_div_fraction; - param->fvco_freq_hz = fvco_freq_hz; - param->pfd_freq_hz = pfd_freq_hz; - param->lane_data_rate_hz = lane_data_rate_hz; - param->hsclk_freq_hz = hsclk_freq_hz; - - return status_success; -} - -void pixelmux_config_tx_phy0_mode(pixelmux_tx_phy_mode_t mode) -{ - HPM_PIXEL_MUX->GPR_WR_D2 = (HPM_PIXEL_MUX->GPR_WR_D2 & - ~PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) | - PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(mode); -} - -void pixelmux_config_tx_phy1_mode(pixelmux_tx_phy_mode_t mode) -{ - HPM_PIXEL_MUX->GPR_WR_D5 = (HPM_PIXEL_MUX->GPR_WR_D5 & - ~PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) | - PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(mode); -} - -void pixelmux_config_lvds_tx_phy0_clk(const lvds_phy_clk_reg_t *clk_reg) -{ - HPM_PIXEL_MUX->GPR_WR_D2 = (HPM_PIXEL_MUX->GPR_WR_D2 & - ~(PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK | - PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK | - PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK | - PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK)) | - PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(clk_reg->rate_lvds) | - PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(clk_reg->refclk_div) | - PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(clk_reg->pll_div); - - /* - * lvds_rpck/refclk control signal - * 0: normal - * 1: inverter - */ - HPM_PIXEL_MUX->GPR_WR_D3 &= ~(0x01ul<<29); - - /* - * ckphy_ctl[2:0]:CLK_PHY divide ratio select, must be 010:div7 - * ckphy_ctl[8]:div4 enable signal - */ - HPM_PIXEL_MUX->GPR_WR_D4 = (HPM_PIXEL_MUX->GPR_WR_D4 & ~PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) | - PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET((clk_reg->data_rate_div4 & 0x01)<<8 | 0x02); -} - -void pixelmux_config_lvds_tx_phy1_clk(const lvds_phy_clk_reg_t *clk_reg) -{ - HPM_PIXEL_MUX->GPR_WR_D5 = (HPM_PIXEL_MUX->GPR_WR_D5 & - ~(PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK | - PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK | - PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK | - PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK)) | - PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(clk_reg->rate_lvds) | - PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(clk_reg->refclk_div) | - PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(clk_reg->pll_div); - /* - * lvds_rpck/refclk control signal - * 0: normal - * 1: inverter - */ - HPM_PIXEL_MUX->GPR_WR_D6 &= ~(0x01ul<<29); - - /* - * ckphy_ctl[2:0]:CLK_PHY divide ratio select, must be 010:div7 - * ckphy_ctl[8]:div4 enable signal - */ - HPM_PIXEL_MUX->GPR_WR_D7 = (HPM_PIXEL_MUX->GPR_WR_D7 & ~PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) | - PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET((clk_reg->data_rate_div4 & 0x01)<<8 | 0x02); -} - -void pixelmux_config_rx_phy0_mode(pixelmux_rx_phy_mode_t mode) -{ - HPM_PIXEL_MUX->GPR_WR_D8 = (HPM_PIXEL_MUX->GPR_WR_D8 & - ~PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) | - PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(mode); -} - -void pixelmux_config_rx_phy1_mode(pixelmux_rx_phy_mode_t mode) -{ - HPM_PIXEL_MUX->GPR_WR_D9 = (HPM_PIXEL_MUX->GPR_WR_D9 & - ~PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) | - PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(mode); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c deleted file mode 100644 index ef835894aac..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pla_drv.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_soc_feature.h" -#include "hpm_pla_drv.h" - -void pla_set_aoi_16to8_one_channel(PLA_Type *pla, - pla_aoi_16to8_chn_cfg_t *cfg) -{ - uint8_t i; - uint32_t value; - - value = 0; - for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) { - value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1); - } - pla->CHN[cfg->chn].AOI_16TO8[cfg->aoi_16to8_chn] = value; -} - -void pla_get_aoi_16to8_one_channel(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_16to8_channel_type_t aoi_16to8_chn, - pla_aoi_16to8_chn_cfg_t *cfg) -{ - uint8_t i; - - for (i = 0; i < PLA_AOI_16TO8_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[chn].AOI_16TO8[aoi_16to8_chn] >> (i << 1)) & 0x03; - } -} - -void pla_set_aoi_8to7_one_channel(PLA_Type *pla, - pla_aoi_8to7_chn_cfg_t *cfg) -{ - uint8_t i; - uint32_t value; - - value = 0; - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - value |= ((uint32_t)cfg->input[i].op) << (cfg->input[i].signal << 1); - } - switch (cfg->aoi_8to7_chn) { - case pla_aoi_8to7_chn_0: - pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0xffff0000) | value; - break; - case pla_aoi_8to7_chn_1: - pla->CHN[cfg->chn].AOI_8TO7_00_01 = (pla->CHN[cfg->chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16); - break; - case pla_aoi_8to7_chn_2: - pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0xffff0000) | value; - break; - case pla_aoi_8to7_chn_3: - pla->CHN[cfg->chn].AOI_8TO7_02_03 = (pla->CHN[cfg->chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16); - break; - case pla_aoi_8to7_chn_4: - pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0xffff0000) | value; - break; - case pla_aoi_8to7_chn_5: - pla->CHN[cfg->chn].AOI_8TO7_04_05 = (pla->CHN[cfg->chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16); - break; - case pla_aoi_8to7_chn_6: - pla->CHN[cfg->chn].AOI_8TO7_06 = value; - break; - default: - break; - } -} - -void pla_get_aoi_8to7_one_channel(PLA_Type *pla, - pla_aoi_8to7_chn_cfg_t *cfg) -{ - uint8_t i; - - switch (cfg->aoi_8to7_chn) { - case pla_aoi_8to7_chn_0: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 1)) & 0x03; - } - break; - case pla_aoi_8to7_chn_1: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_00_01 >> (i << 17)) & 0x03; - } - break; - case pla_aoi_8to7_chn_2: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 1)) & 0x03; - } - break; - case pla_aoi_8to7_chn_3: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_02_03 >> (i << 17)) & 0x03; - } - break; - case pla_aoi_8to7_chn_4: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 1)) & 0x03; - } - break; - case pla_aoi_8to7_chn_5: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_04_05 >> (i << 17)) & 0x03; - } - break; - case pla_aoi_8to7_chn_6: - for (i = 0; i < PLA_AOI_8TO7_SIGNAL_NUM; i++) { - cfg->input[i].signal = i; - cfg->input[i].op = (pla->CHN[cfg->chn].AOI_8TO7_06 >> (i << 1)) & 0x03; - } - break; - default: - break; - } -} - -void pla_set_aoi_8to7_input_signal(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_8to7_channel_type_t aoi_8to7_chn, - pla_aoi_8to7_cfg_unit_t *cfg) -{ - uint32_t value; - - value = ((uint32_t)cfg->op) << (cfg->signal << 1); - switch (aoi_8to7_chn) { - case pla_aoi_8to7_chn_0: - pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0xffff0000) | value; - break; - case pla_aoi_8to7_chn_1: - pla->CHN[chn].AOI_8TO7_00_01 = (pla->CHN[chn].AOI_8TO7_00_01 & 0x0000ffff) | (value << 16); - break; - case pla_aoi_8to7_chn_2: - pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0xffff0000) | value; - break; - case pla_aoi_8to7_chn_3: - pla->CHN[chn].AOI_8TO7_02_03 = (pla->CHN[chn].AOI_8TO7_02_03 & 0x0000ffff) | (value << 16); - break; - case pla_aoi_8to7_chn_4: - pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0xffff0000) | value; - break; - case pla_aoi_8to7_chn_5: - pla->CHN[chn].AOI_8TO7_04_05 = (pla->CHN[chn].AOI_8TO7_04_05 & 0x0000ffff) | (value << 16); - break; - case pla_aoi_8to7_chn_6: - pla->CHN[chn].AOI_8TO7_06 = value; - break; - default: - break; - } -} - -void pla_get_aoi_8to7_input_signal(PLA_Type *pla, - pla_channel_type_t chn, - pla_aoi_8to7_channel_type_t aoi_8to7_chn, - pla_aoi_8to7_input_signal_type_t signal, - pla_aoi_8to7_cfg_unit_t *cfg) -{ - - switch (aoi_8to7_chn) { - case pla_aoi_8to7_chn_0: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 1)) & 0x03; - break; - case pla_aoi_8to7_chn_1: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_00_01 >> (signal << 17)) & 0x03; - break; - case pla_aoi_8to7_chn_2: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 1)) & 0x03; - break; - case pla_aoi_8to7_chn_3: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_02_03 >> (signal << 17)) & 0x03; - break; - case pla_aoi_8to7_chn_4: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 1)) & 0x03; - break; - case pla_aoi_8to7_chn_5: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_04_05 >> (signal << 17)) & 0x03; - break; - case pla_aoi_8to7_chn_6: - cfg->signal = signal; - cfg->op = (pla->CHN[chn].AOI_8TO7_06 >> (signal << 1)) & 0x03; - break; - default: - break; - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c deleted file mode 100644 index 60f8066a675..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_plb_drv.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_soc_feature.h" -#include "hpm_plb_drv.h" - -void plb_type_b_set_lut(PLB_Type *plb, plb_chn_t chn, plb_type_b_lut_slice_t slice, plb_type_b_slice_opt_t opt) -{ - if (opt >= plb_slice_opt_shift_left) { - opt = opt >> 8; - plb->TYPE_B[chn].MODE |= PLB_TYPE_B_MODE_OPT_SEL_SET(1); - } else { - plb->TYPE_B[chn].MODE &= ~PLB_TYPE_B_MODE_OPT_SEL_MASK; - } - if (slice >= plb_type_b_slice_8) { - plb->TYPE_B[chn].LUT[1] = (plb->TYPE_B[chn].LUT[1] & (~PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(PLB_SLICE_HIGH_BIT_MASK_SET(slice)))) | PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(opt << PLB_SLICE_HIGH_BIT_SHIFT(slice)); - } else { - plb->TYPE_B[chn].LUT[0] = (plb->TYPE_B[chn].LUT[0] & (~PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(PLB_SLICE_LOW_BIT_MASK_SET(slice)))) | PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(opt << PLB_SLICE_LOW_BIT_SHIFT(slice)); - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c deleted file mode 100644 index 3b6fe2e436d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctl_drv.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_pllctl_drv.h" - -#define PLLCTL_INT_PLL_MAX_FBDIV (2400U) -#define PLLCTL_INT_PLL_MIN_FBDIV (16U) - -#define PLLCTL_FRAC_PLL_MAX_FBDIV (240U) -#define PLLCTL_FRAC_PLL_MIN_FBDIV (20U) - -#define PLLCTL_PLL_MAX_REFDIV (63U) -#define PLLCTL_PLL_MIN_REFDIV (1U) - -#define PLLCTL_PLL_MAX_POSTDIV1 (7U) -#define PLLCTL_PLL_MIN_POSTDIV1 (1U) - -#define PLLCTL_FRAC_PLL_MIN_REF (10000000U) -#define PLLCTL_INT_PLL_MIN_REF (1000000U) - - -hpm_stat_t pllctl_set_pll_work_mode(PLLCTL_Type *ptr, uint8_t pll, bool int_mode) -{ - if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - return status_invalid_argument; - } - if (int_mode) { - if (!(ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK)) { - /* it was at frac mode, then it needs to be power down */ - pllctl_pll_powerdown(ptr, pll); - ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; - pllctl_pll_poweron(ptr, pll); - } - } else { - if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { - /* pll has to be powered down to configure frac mode */ - pllctl_pll_powerdown(ptr, pll); - ptr->PLL[pll].CFG0 &= ~PLLCTL_PLL_CFG0_DSMPD_MASK; - pllctl_pll_poweron(ptr, pll); - } - } - - return status_success; -} - -hpm_stat_t pllctl_set_refdiv(PLLCTL_Type *ptr, uint8_t pll, uint8_t div) -{ - uint32_t min_ref; - - if ((ptr == NULL) - || (pll > (PLLCTL_SOC_PLL_MAX_COUNT - 1)) - || (div == 0U) - || (div > (PLLCTL_PLL_CFG0_REFDIV_MASK >> PLLCTL_PLL_CFG0_REFDIV_SHIFT))) { - return status_invalid_argument; - } - - if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { - min_ref = PLLCTL_INT_PLL_MIN_REF; - } else { - min_ref = PLLCTL_FRAC_PLL_MIN_REF; - } - - if ((PLLCTL_SOC_PLL_REFCLK_FREQ / div) < min_ref) { - return status_pllctl_out_of_range; - } - - if (PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0) != div) { - /* if div is different, it needs to be power down */ - pllctl_pll_powerdown(ptr, pll); - ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) - | PLLCTL_PLL_CFG0_REFDIV_SET(div); - pllctl_pll_poweron(ptr, pll); - } - return status_success; -} - -hpm_stat_t pllctl_init_int_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, - uint32_t freq_in_hz) -{ - if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - return status_invalid_argument; - } - uint32_t freq, fbdiv, refdiv, postdiv; - if ((freq_in_hz < PLLCTL_PLL_VCO_FREQ_MIN) - || (freq_in_hz > PLLCTL_PLL_VCO_FREQ_MAX)) { - return status_invalid_argument; - } - - freq = freq_in_hz; - refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); - postdiv = PLLCTL_PLL_CFG0_POSTDIV1_GET(ptr->PLL[pll].CFG0); - fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - if (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) { - /* current refdiv can't be used for the given frequency */ - refdiv--; - do { - fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - if (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) { - refdiv--; - } else { - break; - } - } while (refdiv > PLLCTL_PLL_MIN_REFDIV); - } else if (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) { - /* current refdiv can't be used for the given frequency */ - refdiv++; - do { - fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - if (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) { - refdiv++; - } else { - break; - } - } while (refdiv < PLLCTL_PLL_MAX_REFDIV); - } - - if ((refdiv > PLLCTL_PLL_MAX_REFDIV) - || (refdiv < PLLCTL_PLL_MIN_REFDIV) - || (fbdiv > PLLCTL_INT_PLL_MAX_FBDIV) - || (fbdiv < PLLCTL_INT_PLL_MIN_FBDIV) - || (((PLLCTL_SOC_PLL_REFCLK_FREQ / refdiv) < PLLCTL_INT_PLL_MIN_REF))) { - return status_pllctl_out_of_range; - } - - if (!(ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK)) { - /* it was at frac mode, then it needs to be power down */ - pllctl_pll_powerdown(ptr, pll); - ptr->PLL[pll].CFG0 |= PLLCTL_PLL_CFG0_DSMPD_MASK; - } - - if (PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0) != refdiv) { - /* if refdiv is different, it needs to be power down */ - pllctl_pll_powerdown(ptr, pll); - ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 & ~PLLCTL_PLL_CFG0_REFDIV_MASK) - | PLLCTL_PLL_CFG0_REFDIV_SET(refdiv); - } - - ptr->PLL[pll].CFG2 = (ptr->PLL[pll].CFG2 & ~(PLLCTL_PLL_CFG2_FBDIV_INT_MASK)) | PLLCTL_PLL_CFG2_FBDIV_INT_SET(fbdiv); - - pllctl_pll_poweron(ptr, pll); - return status_success; -} - -hpm_stat_t pllctl_init_frac_pll_with_freq(PLLCTL_Type *ptr, uint8_t pll, - uint32_t freq_in_hz) -{ - if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - return status_invalid_argument; - } - uint32_t frac, refdiv, fbdiv, freq, postdiv; - double div; - if ((freq_in_hz < PLLCTL_PLL_VCO_FREQ_MIN) - || (freq_in_hz > PLLCTL_PLL_VCO_FREQ_MAX)) { - return status_invalid_argument; - } - - freq = freq_in_hz; - refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); - postdiv = PLLCTL_PLL_CFG0_POSTDIV1_GET(ptr->PLL[pll].CFG0); - fbdiv = (freq / postdiv) / (PLLCTL_SOC_PLL_REFCLK_FREQ / refdiv); - - if (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) { - /* current refdiv can't be used for the given frequency */ - refdiv--; - do { - fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - if (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) { - refdiv--; - } else { - break; - } - } while (refdiv > PLLCTL_PLL_MIN_REFDIV); - } else if (fbdiv < PLLCTL_FRAC_PLL_MIN_FBDIV) { - /* current refdiv can't be used for the given frequency */ - refdiv++; - do { - fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - if (fbdiv < PLLCTL_FRAC_PLL_MIN_FBDIV) { - refdiv++; - } else { - break; - } - } while (refdiv < PLLCTL_PLL_MAX_REFDIV); - } - - if ((refdiv > PLLCTL_PLL_MAX_REFDIV) - || (refdiv < PLLCTL_PLL_MIN_REFDIV) - || (fbdiv > PLLCTL_FRAC_PLL_MAX_FBDIV) - || (fbdiv < PLLCTL_FRAC_PLL_MIN_FBDIV) - || (((PLLCTL_SOC_PLL_REFCLK_FREQ / refdiv) < PLLCTL_FRAC_PLL_MIN_REF))) { - return status_pllctl_out_of_range; - } - - div = (double) freq / PLLCTL_SOC_PLL_REFCLK_FREQ * (refdiv * postdiv); - fbdiv = freq / (PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv)); - frac = (uint32_t)((div - fbdiv) * (1 << 24)); - - /* - * pll has to be powered down to configure frac mode - */ - pllctl_pll_powerdown(ptr, pll); - - ptr->PLL[pll].CFG0 = (ptr->PLL[pll].CFG0 - & ~(PLLCTL_PLL_CFG0_REFDIV_MASK | PLLCTL_PLL_CFG0_DSMPD_MASK)) - | PLLCTL_PLL_CFG0_REFDIV_SET(refdiv); - - pllctl_pll_ss_disable(ptr, pll); - ptr->PLL[pll].FREQ = (ptr->PLL[pll].FREQ - & ~(PLLCTL_PLL_FREQ_FRAC_MASK | PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK)) - | PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(fbdiv) | PLLCTL_PLL_FREQ_FRAC_SET(frac); - - pllctl_pll_poweron(ptr, pll); - return status_success; -} - -uint32_t pllctl_get_pll_freq_in_hz(PLLCTL_Type *ptr, uint8_t pll) -{ - if ((ptr == NULL) || (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - return status_invalid_argument; - } - uint32_t fbdiv, frac, refdiv, postdiv, refclk, freq; - if (ptr->PLL[pll].CFG1 & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) { - /* pll is powered down */ - return 0; - } - - refdiv = PLLCTL_PLL_CFG0_REFDIV_GET(ptr->PLL[pll].CFG0); - postdiv = PLLCTL_PLL_CFG0_POSTDIV1_GET(ptr->PLL[pll].CFG0); - refclk = PLLCTL_SOC_PLL_REFCLK_FREQ / (refdiv * postdiv); - - if (ptr->PLL[pll].CFG0 & PLLCTL_PLL_CFG0_DSMPD_MASK) { - /* pll int mode */ - fbdiv = PLLCTL_PLL_CFG2_FBDIV_INT_GET(ptr->PLL[pll].CFG2); - freq = refclk * fbdiv; - } else { - /* pll frac mode */ - fbdiv = PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(ptr->PLL[pll].FREQ); - frac = PLLCTL_PLL_FREQ_FRAC_GET(ptr->PLL[pll].FREQ); - freq = (uint32_t)((refclk * (fbdiv + ((double) frac / (1 << 24)))) + 0.5); - } - return freq; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c deleted file mode 100644 index 4f4f6b427bc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pllctlv2_drv.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_pllctlv2_drv.h" - - -#define PLLCTLV2_PLL_MFN_FACTOR (10U) /*!< PLLCTLV2 PLL MFN Factor */ -#define PLLCTLV2_PLL_MFD_DEFAULT (240UL * 1000000UL) /*!< PLLCTLV2 PLL Default MFD value */ - -#define PLLCTLV2_PLL_MFI_MIN (16U) -#define PLLCTLV2_PLL_MFI_MAX (42U) -#define PLLCTLV2_PLL_XTAL_FREQ (24000000UL) - -#define PLLCTLV2_PLL_FREQ_MIN (PLLCTLV2_PLL_MFI_MIN * PLLCTLV2_PLL_XTAL_FREQ) -#define PLLCTLV2_PLL_FREQ_MAX ((PLLCTLV2_PLL_MFI_MAX + 1U) * PLLCTLV2_PLL_XTAL_FREQ) - -hpm_stat_t pllctlv2_set_pll_with_mfi_mfn(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t mfi, uint32_t mfn) -{ - hpm_stat_t status; - if ((ptr == NULL) || (mfi < PLLCTLV2_PLL_MFI_MIN) || (mfi > PLLCTLV2_PLL_MFI_MAX) || - (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - status = status_invalid_argument; - } else { - if (PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI) == mfi) { - ptr->PLL[pll].MFI = mfi - 1U; - } - ptr->PLL[pll].MFI = mfi; - ptr->PLL[pll].MFN = mfn; - - status = status_success; - } - return status; -} - -hpm_stat_t pllctlv2_init_pll_with_freq(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t freq_in_hz) -{ - hpm_stat_t status; - if ((ptr == NULL) || (freq_in_hz < PLLCTLV2_PLL_FREQ_MIN) || (freq_in_hz > PLLCTLV2_PLL_FREQ_MAX) || - (pll >= PLLCTL_SOC_PLL_MAX_COUNT)) { - status = status_invalid_argument; - } else { - uint32_t mfn = freq_in_hz % PLLCTLV2_PLL_XTAL_FREQ; - uint32_t mfi = freq_in_hz / PLLCTLV2_PLL_XTAL_FREQ; - - if (PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI) == mfi) { - ptr->PLL[pll].MFI = mfi - 1U; - } - - ptr->PLL[pll].MFI = mfi; - /* - * NOTE: Default MFD value is 240M - */ - ptr->PLL[pll].MFN = mfn * PLLCTLV2_PLL_MFN_FACTOR; - - status = status_success; - } - return status; -} - -void pllctlv2_enable_spread_spectrum(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t step, uint32_t stop) -{ - /* - * NOTE: The spread spectrum related registers cannot be configured under below conditions: - * 1. PLL is enabled - * 2. spread spectrum is enabled - */ - if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { - - ptr->PLL[pll].CONFIG &= ~PLLCTLV2_PLL_CONFIG_SPREAD_MASK; - - ptr->PLL[pll].SS_STEP = step; - ptr->PLL[pll].SS_STOP = stop; - - ptr->PLL[pll].CONFIG |= PLLCTLV2_PLL_CONFIG_SPREAD_MASK; - } -} - -void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value) -{ - if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { - ptr->PLL[pll].DIV[div_index] = - (ptr->PLL[pll].DIV[div_index] & ~PLLCTLV2_PLL_DIV_DIV_MASK) | PLLCTLV2_PLL_DIV_DIV_SET(div_value) | - PLLCTLV2_PLL_DIV_ENABLE_MASK; - } -} - -uint32_t pllctlv2_get_pll_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll) -{ - uint32_t freq = 0; - if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { - uint32_t mfi = PLLCTLV2_PLL_MFI_MFI_GET(ptr->PLL[pll].MFI); - uint32_t mfn = PLLCTLV2_PLL_MFN_MFN_GET(ptr->PLL[pll].MFN); - uint32_t mfd = PLLCTLV2_PLL_MFD_MFD_GET(ptr->PLL[pll].MFD); - freq = (uint32_t) (PLLCTLV2_PLL_XTAL_FREQ * (mfi + 1.0 * mfn / mfd)); - } - return freq; -} - -uint32_t pllctlv2_get_pll_postdiv_freq_in_hz(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index) -{ - uint32_t postdiv_freq = 0; - if ((ptr != NULL) && (pll < PLLCTL_SOC_PLL_MAX_COUNT)) { - uint32_t postdiv = PLLCTLV2_PLL_DIV_DIV_GET(ptr->PLL[pll].DIV[div_index]); - uint32_t pll_freq = pllctlv2_get_pll_freq_in_hz(ptr, pll); - postdiv_freq = (uint32_t) (pll_freq / (1U + postdiv * 1.0 / 5U)); - } - - return postdiv_freq; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c deleted file mode 100644 index 975ba64647a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pmp_drv.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_pmp_drv.h" -#include "hpm_csr_drv.h" - -uint32_t read_pmp_cfg(uint32_t idx) -{ - uint32_t pmp_cfg = 0; - switch (idx) { - case 0: - pmp_cfg = read_csr(CSR_PMPCFG0); - break; - case 1: - pmp_cfg = read_csr(CSR_PMPCFG1); - break; - case 2: - pmp_cfg = read_csr(CSR_PMPCFG2); - break; - case 3: - pmp_cfg = read_csr(CSR_PMPCFG3); - break; - default: - /* Do nothing */ - break; - } - return pmp_cfg; -} - -void write_pmp_cfg(uint32_t value, uint32_t idx) -{ - switch (idx) { - case 0: - write_csr(CSR_PMPCFG0, value); - break; - case 1: - write_csr(CSR_PMPCFG1, value); - break; - case 2: - write_csr(CSR_PMPCFG2, value); - break; - case 3: - write_csr(CSR_PMPCFG3, value); - break; - default: - /* Do nothing */ - break; - } -} - -void write_pmp_addr(uint32_t value, uint32_t idx) -{ - switch (idx) { - case 0: - write_csr(CSR_PMPADDR0, value); - break; - case 1: - write_csr(CSR_PMPADDR1, value); - break; - case 2: - write_csr(CSR_PMPADDR2, value); - break; - case 3: - write_csr(CSR_PMPADDR3, value); - break; - case 4: - write_csr(CSR_PMPADDR4, value); - break; - case 5: - write_csr(CSR_PMPADDR5, value); - break; - case 6: - write_csr(CSR_PMPADDR6, value); - break; - case 7: - write_csr(CSR_PMPADDR7, value); - break; - case 8: - write_csr(CSR_PMPADDR8, value); - break; - case 9: - write_csr(CSR_PMPADDR9, value); - break; - case 10: - write_csr(CSR_PMPADDR10, value); - break; - case 11: - write_csr(CSR_PMPADDR11, value); - break; - case 12: - write_csr(CSR_PMPADDR12, value); - break; - case 13: - write_csr(CSR_PMPADDR13, value); - break; - case 14: - write_csr(CSR_PMPADDR14, value); - break; - case 15: - write_csr(CSR_PMPADDR15, value); - break; - default: - /* Do nothing */ - break; - } -} - -uint32_t read_pmp_addr(uint32_t idx) -{ - uint32_t ret_val = 0; - switch (idx) { - case 0: - ret_val = read_csr(CSR_PMPADDR0); - break; - case 1: - ret_val = read_csr(CSR_PMPADDR1); - break; - case 2: - ret_val = read_csr(CSR_PMPADDR2); - break; - case 3: - ret_val = read_csr(CSR_PMPADDR3); - break; - case 4: - ret_val = read_csr(CSR_PMPADDR4); - break; - case 5: - ret_val = read_csr(CSR_PMPADDR5); - break; - case 6: - ret_val = read_csr(CSR_PMPADDR6); - break; - case 7: - ret_val = read_csr(CSR_PMPADDR7); - break; - case 8: - ret_val = read_csr(CSR_PMPADDR8); - break; - case 9: - ret_val = read_csr(CSR_PMPADDR9); - break; - case 10: - ret_val = read_csr(CSR_PMPADDR10); - break; - case 11: - ret_val = read_csr(CSR_PMPADDR11); - break; - case 12: - ret_val = read_csr(CSR_PMPADDR12); - break; - case 13: - ret_val = read_csr(CSR_PMPADDR13); - break; - case 14: - ret_val = read_csr(CSR_PMPADDR14); - break; - case 15: - ret_val = read_csr(CSR_PMPADDR15); - break; - default: - /* Do nothing */ - break; - } - return ret_val; -} - -#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) -uint32_t read_pma_cfg(uint32_t idx) -{ - uint32_t pma_cfg = 0; - switch (idx) { - case 0: - pma_cfg = read_csr(CSR_PMACFG0); - break; - case 1: - pma_cfg = read_csr(CSR_PMACFG1); - break; - case 2: - pma_cfg = read_csr(CSR_PMACFG2); - break; - case 3: - pma_cfg = read_csr(CSR_PMACFG3); - break; - default: - /* Do nothing */ - break; - } - return pma_cfg; -} - -void write_pma_cfg(uint32_t value, uint32_t idx) -{ - switch (idx) { - case 0: - write_csr(CSR_PMACFG0, value); - break; - case 1: - write_csr(CSR_PMACFG1, value); - break; - case 2: - write_csr(CSR_PMACFG2, value); - break; - case 3: - write_csr(CSR_PMACFG3, value); - break; - default: - /* Do nothing */ - break; - } -} -void write_pma_addr(uint32_t value, uint32_t idx) -{ - switch (idx) { - case 0: - write_csr(CSR_PMAADDR0, value); - break; - case 1: - write_csr(CSR_PMAADDR1, value); - break; - case 2: - write_csr(CSR_PMAADDR2, value); - break; - case 3: - write_csr(CSR_PMAADDR3, value); - break; - case 4: - write_csr(CSR_PMAADDR4, value); - break; - case 5: - write_csr(CSR_PMAADDR5, value); - break; - case 6: - write_csr(CSR_PMAADDR6, value); - break; - case 7: - write_csr(CSR_PMAADDR7, value); - break; - case 8: - write_csr(CSR_PMAADDR8, value); - break; - case 9: - write_csr(CSR_PMAADDR9, value); - break; - case 10: - write_csr(CSR_PMAADDR10, value); - break; - case 11: - write_csr(CSR_PMAADDR11, value); - break; - case 12: - write_csr(CSR_PMAADDR12, value); - break; - case 13: - write_csr(CSR_PMAADDR13, value); - break; - case 14: - write_csr(CSR_PMAADDR14, value); - break; - case 15: - write_csr(CSR_PMAADDR15, value); - break; - default: - /* Do nothing */ - break; - } -} - -uint32_t read_pma_addr(uint32_t idx) -{ - uint32_t ret_val = 0; - switch (idx) { - case 0: - ret_val = read_csr(CSR_PMAADDR0); - break; - case 1: - ret_val = read_csr(CSR_PMAADDR1); - break; - case 2: - ret_val = read_csr(CSR_PMAADDR2); - break; - case 3: - ret_val = read_csr(CSR_PMAADDR3); - break; - case 4: - ret_val = read_csr(CSR_PMAADDR4); - break; - case 5: - ret_val = read_csr(CSR_PMAADDR5); - break; - case 6: - ret_val = read_csr(CSR_PMAADDR6); - break; - case 7: - ret_val = read_csr(CSR_PMAADDR7); - break; - case 8: - ret_val = read_csr(CSR_PMAADDR8); - break; - case 9: - ret_val = read_csr(CSR_PMAADDR9); - break; - case 10: - ret_val = read_csr(CSR_PMAADDR10); - break; - case 11: - ret_val = read_csr(CSR_PMAADDR11); - break; - case 12: - ret_val = read_csr(CSR_PMAADDR12); - break; - case 13: - ret_val = read_csr(CSR_PMAADDR13); - break; - case 14: - ret_val = read_csr(CSR_PMAADDR14); - break; - case 15: - ret_val = read_csr(CSR_PMAADDR15); - break; - default: - /* Do nothing */ - break; - } - return ret_val; -} -#endif /* #if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) */ - -hpm_stat_t pmp_config_entry(const pmp_entry_t *entry, uint32_t entry_index) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF((entry == NULL) || (entry_index > 15U)); - - uint32_t idx = entry_index / 4; - uint32_t offset = (entry_index * 8) & 0x1F; - - uint32_t pmp_cfg = read_pmp_cfg(idx); - pmp_cfg &= ~(0xFFUL << offset); - pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; - write_pmp_addr(entry->pmp_addr, entry_index); - write_pmp_cfg(pmp_cfg, idx); -#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) - uint32_t pma_cfg = read_pma_cfg(idx); - pma_cfg &= ~(0xFFUL << offset); - pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; - write_pma_cfg(pma_cfg, idx); - write_pma_addr(entry->pma_addr, entry_index); -#endif - fencei(); - - status = status_success; - - } while (false); - - return status; -} - -hpm_stat_t pmp_config(const pmp_entry_t *entry, uint32_t num_of_entries) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF((entry == NULL) || (num_of_entries < 1U) || (num_of_entries > 15U)); - - for (uint32_t i = 0; i < num_of_entries; i++) { - uint32_t idx = i / 4; - uint32_t offset = (i * 8) & 0x1F; - uint32_t pmp_cfg = read_pmp_cfg(idx); - pmp_cfg &= ~(0xFFUL << offset); - pmp_cfg |= ((uint32_t) entry->pmp_cfg.val) << offset; - write_pmp_addr(entry->pmp_addr, i); - write_pmp_cfg(pmp_cfg, idx); -#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) - uint32_t pma_cfg = read_pma_cfg(idx); - pma_cfg &= ~(0xFFUL << offset); - pma_cfg |= ((uint32_t) entry->pma_cfg.val) << offset; - write_pma_cfg(pma_cfg, idx); - write_pma_addr(entry->pma_addr, i); -#endif - ++entry; - } - fencei(); - - status = status_success; - - } while (false); - - return status; -} - -void pmp_disable(void) -{ - /* Disable caches */ - fencei(); - uint32_t mcache_ctl = read_csr(CSR_MCACHE_CTL); - write_csr(CSR_MCACHE_CTL, 0x0); - fencei(); - - write_csr(CSR_PMPCFG0, 0); - write_csr(CSR_PMPCFG1, 0); - write_csr(CSR_PMPCFG2, 0); - write_csr(CSR_PMPCFG3, 0); - write_csr(CSR_PMPADDR0, 0); - write_csr(CSR_PMPADDR1, 0); - write_csr(CSR_PMPADDR2, 0); - write_csr(CSR_PMPADDR3, 0); - write_csr(CSR_PMPADDR4, 0); - write_csr(CSR_PMPADDR5, 0); - write_csr(CSR_PMPADDR6, 0); - write_csr(CSR_PMPADDR7, 0); - write_csr(CSR_PMPADDR8, 0); - write_csr(CSR_PMPADDR9, 0); - write_csr(CSR_PMPADDR10, 0); - write_csr(CSR_PMPADDR11, 0); - write_csr(CSR_PMPADDR12, 0); - write_csr(CSR_PMPADDR13, 0); - write_csr(CSR_PMPADDR14, 0); - write_csr(CSR_PMPADDR15, 0); -#if (!defined(PMP_SUPPORT_PMA)) || (defined(PMP_SUPPORT_PMA) && (PMP_SUPPORT_PMA == 1)) - write_csr(CSR_PMACFG0, 0); - write_csr(CSR_PMACFG1, 0); - write_csr(CSR_PMACFG2, 0); - write_csr(CSR_PMACFG3, 0); - write_csr(CSR_PMAADDR0, 0); - write_csr(CSR_PMAADDR1, 0); - write_csr(CSR_PMAADDR2, 0); - write_csr(CSR_PMAADDR3, 0); - write_csr(CSR_PMAADDR4, 0); - write_csr(CSR_PMAADDR5, 0); - write_csr(CSR_PMAADDR6, 0); - write_csr(CSR_PMAADDR7, 0); - write_csr(CSR_PMAADDR8, 0); - write_csr(CSR_PMAADDR9, 0); - write_csr(CSR_PMAADDR10, 0); - write_csr(CSR_PMAADDR11, 0); - write_csr(CSR_PMAADDR12, 0); - write_csr(CSR_PMAADDR13, 0); - write_csr(CSR_PMAADDR14, 0); - write_csr(CSR_PMAADDR15, 0); -#endif - fencei(); - write_csr(CSR_MCACHE_CTL, mcache_ctl); - fencei(); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c deleted file mode 100644 index 41ff66f8379..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ppi_drv.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_ppi_drv.h" - -void ppi_config_clk_pin(PPI_Type *ppi, ppi_clk_pin_config_t *config) -{ - uint32_t tmp; - - tmp = PPI_CLKPIN_CFG_CYCLE_SET(config->cycle_num) - | PPI_CLKPIN_CFG_HIGH_SET(config->high_num) - | PPI_CLKPIN_CFG_LOW_SET(config->low_num) - | PPI_CLKPIN_CFG_INVERT_SET(config->revert) - | PPI_CLKPIN_CFG_AON_SET(config->mode) - | PPI_CLKPIN_CFG_EN_MASK; - - ppi->CLKPIN_CFG = tmp; -} - -void ppi_config_cs_pin(PPI_Type *ppi, uint8_t index, ppi_cs_pin_config_t *config) -{ - uint32_t tmp; - uint8_t shift; - - assert(index < 4); - assert((config->addr_start_high_12bits >= 0xF80) && (config->addr_start_high_12bits <= 0xFFF)); - assert((config->addr_end_high_12bits >= 0xF80) && (config->addr_end_high_12bits <= 0xFFF)); - - tmp = PPI_CS_CFG0_ADDR_START_SET(config->addr_start_high_12bits) | PPI_CS_CFG0_ADDR_END_SET(config->addr_end_high_12bits); - ppi->CS[index].CFG0 = tmp; - - if (config->port_size == ppi_port_size_16bits) { - shift = 1; - } else if (config->port_size == ppi_port_size_32bits) { - shift = 2; - } else { - shift = 0; - } - tmp = PPI_CS_CFG1_ADDR_MASK_SET(config->addr_mask) | PPI_CS_CFG1_ADDR_SHIFT_SET(shift); - ppi->CS[index].CFG1 = tmp; - - tmp = PPI_CS_CFG3_RCMD_END1_SET(config->rcmd_end1) - | PPI_CS_CFG3_RCMD_START1_SET(config->rcmd_start1) - | PPI_CS_CFG3_RCMD_END0_SET(config->rcmd_end0) - | PPI_CS_CFG3_RCMD_START0_SET(config->rcmd_start0); - ppi->CS[index].CFG3 = tmp; - - tmp = PPI_CS_CFG4_WCMD_END1_SET(config->wcmd_end1) - | PPI_CS_CFG4_WCMD_START1_SET(config->wcmd_start1) - | PPI_CS_CFG4_WCMD_END0_SET(config->wcmd_end0) - | PPI_CS_CFG4_WCMD_START0_SET(config->wcmd_start0); - ppi->CS[index].CFG4 = tmp; - - tmp = PPI_CS_CFG2_CS_SYNC_EN_SET(config->sync_clk_en) - | PPI_CS_CFG2_SYNC_CLK_SEL_SET(config->sync_clk_sel) - | PPI_CS_CFG2_INTER_CMD_DLY_SET(config->interval_cycle) -#if defined(HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS) && HPM_IP_FEATURE_PPI_DM_POLARITY_EACH_CS - | PPI_CS_CFG2_DM_POLARITY_SET(config->dm_polarity) -#endif - | PPI_CS_CFG2_PORT_SIZE_SET(config->port_size) - | PPI_CS_CFG2_ENABLE_MASK; - ppi->CS[index].CFG2 = tmp; -} - -void ppi_config_cmd(PPI_Type *ppi, uint8_t index, ppi_cmd_config_t *config) -{ - uint32_t tmp; - - assert(index < 64); - - tmp = PPI_CMD_CMD_CFG_CS_VAL_SET(config->cs_pin_value) - | PPI_CMD_CMD_CFG_CLK_GATE_SET(config->clk_output) - | PPI_CMD_CMD_CFG_CYCLE_NUM_SET(config->cmd_cycle); - ppi->CMD[index].CMD_CFG = tmp; - - tmp = PPI_CMD_AD_CFG_DIR3_SET(config->ad_pin_dir[3]) - | PPI_CMD_AD_CFG_AD_SEL3_SET(config->ad_func_sel[3]) - | PPI_CMD_AD_CFG_BYTE_SEL3_SET(config->byte_sel[3]) - | PPI_CMD_AD_CFG_DIR2_SET(config->ad_pin_dir[2]) - | PPI_CMD_AD_CFG_AD_SEL2_SET(config->ad_func_sel[2]) - | PPI_CMD_AD_CFG_BYTE_SEL2_SET(config->byte_sel[2]) - | PPI_CMD_AD_CFG_DIR1_SET(config->ad_pin_dir[1]) - | PPI_CMD_AD_CFG_AD_SEL1_SET(config->ad_func_sel[1]) - | PPI_CMD_AD_CFG_BYTE_SEL1_SET(config->byte_sel[1]) - | PPI_CMD_AD_CFG_DIR0_SET(config->ad_pin_dir[0]) - | PPI_CMD_AD_CFG_AD_SEL0_SET(config->ad_func_sel[0]) - | PPI_CMD_AD_CFG_BYTE_SEL0_SET(config->byte_sel[0]); - ppi->CMD[index].AD_CFG = tmp; - - tmp = PPI_CMD_CTRL_CFG_IO_CFG7_SET(config->ctrl_pin_value[7]) - | PPI_CMD_CTRL_CFG_IO_CFG6_SET(config->ctrl_pin_value[6]) - | PPI_CMD_CTRL_CFG_IO_CFG5_SET(config->ctrl_pin_value[5]) - | PPI_CMD_CTRL_CFG_IO_CFG4_SET(config->ctrl_pin_value[4]) - | PPI_CMD_CTRL_CFG_IO_CFG3_SET(config->ctrl_pin_value[3]) - | PPI_CMD_CTRL_CFG_IO_CFG2_SET(config->ctrl_pin_value[2]) - | PPI_CMD_CTRL_CFG_IO_CFG1_SET(config->ctrl_pin_value[1]) - | PPI_CMD_CTRL_CFG_IO_CFG0_SET(config->ctrl_pin_value[0]); - ppi->CMD[index].CTRL_CFG = tmp; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c deleted file mode 100644 index 57c5ac2cd58..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_ptpc_drv.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_soc_feature.h" -#include "hpm_ptpc_drv.h" - -#define PTPC_SS_INCR_UINT_AT_BIN_MODE_IN_PS (446U) - -void ptpc_get_default_config(PTPC_Type *ptr, ptpc_config_t *config) -{ - (void) ptr; - config->capture_trigger = ptpc_capture_trigger_none; - config->ns_rollover_mode = ptpc_ns_counter_rollover_digital; - config->capture_keep = true; - config->coarse_increment = false; - config->src_frequency = 0; -} - -hpm_stat_t ptpc_init(PTPC_Type *ptr, uint8_t index, ptpc_config_t *config) -{ - uint8_t ss_incr; - if (!config || (index > PTPC_SOC_TIMER_MAX_COUNT) || !config->src_frequency) { - return status_invalid_argument; - } - - if (config->ns_rollover_mode == ptpc_ns_counter_rollover_digital) { - ss_incr = 1000000000 / config->src_frequency; - } else { - ss_incr = 1000000000 / config->src_frequency * 1000 / PTPC_SS_INCR_UINT_AT_BIN_MODE_IN_PS; - } - if (!ss_incr) { - return status_invalid_argument; - } - ptpc_disable_timer(ptr, index); - ptr->PTPC[index].CTRL0 = PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(config->ns_rollover_mode) - | PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(config->capture_keep) - | PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(config->coarse_increment) - | (config->capture_trigger & - ((PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK - | PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT); - ptpc_set_ns_counter_step(ptr, index, ss_incr); - ptpc_enable_timer(ptr, index); - return status_success; -} - -hpm_stat_t ptpc_set_timer_output(PTPC_Type *ptr, uint8_t can_index, bool use_ptpc1) -{ - if (can_index > CAN_SOC_MAX_COUNT) { - return status_invalid_argument; - } - ptr->TIME_SEL = (ptr->TIME_SEL & ~(1 << can_index)) | (use_ptpc1 ? (1 << can_index) : 0); - return status_success; -} - -hpm_stat_t ptpc_set_ns_update(PTPC_Type *ptr, uint8_t index, uint32_t ns, ptpc_counting_mode mode) -{ - if ((PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(ptr->PTPC[index].CTRL0) == ptpc_ns_counter_rollover_digital) - && (ns > PTPC_MAX_NS_COUNTER)) { - return status_invalid_argument; - } - ptr->PTPC[index].TS_UPDTL = PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(ns) | PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(mode); - return status_success; -} - -hpm_stat_t ptpc_update_timer(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode) -{ - if (status_success != ptpc_set_ns_update(ptr, index, ns, mode)) { - return status_invalid_argument; - } - ptpc_set_second_update(ptr, index, sec); - ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK; - return status_success; -} - -void ptpc_init_timer(PTPC_Type *ptr, uint8_t index) -{ - ptpc_set_second_update(ptr, index, 0); - ptpc_set_ns_update(ptr, index, 0, ptpc_counting_increment); - ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; -} - -hpm_stat_t ptpc_init_timer_with_initial(PTPC_Type *ptr, uint8_t index, uint32_t sec, uint32_t ns, ptpc_counting_mode mode) -{ - if (status_success != ptpc_set_ns_update(ptr, index, ns, mode)) { - return status_invalid_argument; - } - ptpc_set_second_update(ptr, index, sec); - ptr->PTPC[index].CTRL0 |= PTPC_PTPC_CTRL0_INIT_TIMER_MASK; - return status_success; -} - -hpm_stat_t ptpc_set_pps(PTPC_Type *ptr, uint8_t index, uint8_t p) -{ - if (p > 15) { - return status_invalid_argument; - } else if (p > 0) { - if (PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(ptr->PTPC[index].CTRL0) == ptpc_ns_counter_rollover_digital) { - if (p == 15) { - /* At digital mode, it can only generate interrupt at 16.384 KHz maximum */ - return status_invalid_argument; - } - } else { - if (p == 1) { - /* At binary mode, it can only generate interrupt at 2 Hz minimum, when p > 0 */ - return status_invalid_argument; - } - p--; - } - } - ptr->PTPC[index].PPS_CTRL = PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(p); - return status_success; -} - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c deleted file mode 100644 index 4b9e7d7a8e4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwm_drv.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_soc_feature.h" -#include "hpm_pwm_drv.h" - -hpm_stat_t pwm_load_cmp_shadow_on_match(PWM_Type *pwm_x, - uint8_t index, - pwm_cmp_config_t *config) -{ - if (config->mode != pwm_cmp_mode_output_compare) { - return status_invalid_argument; - } - pwm_config_cmp(pwm_x, index, config); - pwm_issue_shadow_register_lock_event(pwm_x); - pwm_x->GCR = ((pwm_x->GCR & ~(PWM_GCR_CMPSHDWSEL_MASK)) | PWM_GCR_CMPSHDWSEL_SET(index)); - return status_success; -} - -void pwm_get_captured_count(PWM_Type *pwm_x, uint32_t *buf, pwm_counter_type_t counter, uint8_t start_index, uint8_t num) -{ - uint32_t i; - if (counter == pwm_counter_type_capture_falling_edge) { - for (i = start_index; i < start_index + num; i++) { - *buf = pwm_x->CAPNEG[i]; - } - } else { - for (i = start_index; i < start_index + num; i++) { - *buf = pwm_x->CAPPOS[i]; - } - } -} - -void pwm_get_default_cmp_config(PWM_Type *pwm_x, pwm_cmp_config_t *config) -{ - (void) pwm_x; - config->mode = pwm_cmp_mode_output_compare; - config->update_trigger = pwm_shadow_register_update_on_modify; - config->enable_ex_cmp = false; -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - config->enable_hrcmp = false; - config->hrcmp = 0; -#endif - config->cmp = 0; - config->ex_cmp = 0; - config->half_clock_cmp = 0; - config->jitter_cmp = 0; -} - -void pwm_get_default_output_channel_config(PWM_Type *pwm_x, pwm_output_channel_t *config) -{ - (void) pwm_x; - config->cmp_start_index = 0; - config->cmp_end_index = 0; - config->invert_output = false; -} - -void pwm_get_default_pwm_config(PWM_Type *pwm_x, pwm_config_t *config) -{ - (void) pwm_x; - config->enable_output = false; - config->update_trigger = pwm_shadow_register_update_on_modify; - config->fault_mode = pwm_fault_mode_force_output_highz; - config->fault_recovery_trigger = pwm_fault_recovery_on_fault_clear; - config->force_source = pwm_force_source_software; - config->dead_zone_in_half_cycle = 0; -} - -void pwm_get_default_pwm_pair_config(PWM_Type *pwm_x, pwm_pair_config_t *config) -{ - pwm_get_default_pwm_config(pwm_x, &config->pwm[0]); - pwm_get_default_pwm_config(pwm_x, &config->pwm[1]); -} - -hpm_stat_t pwm_setup_waveform_in_pair(PWM_Type *pwm_x, uint8_t pwm_index, - pwm_pair_config_t *pwm_pair_config, uint8_t cmp_start_index, - pwm_cmp_config_t *cmp, uint8_t cmp_num) -{ - uint8_t i; - pwm_output_channel_t ch_config; - - if ((pwm_index > PWM_SOC_PWM_MAX_COUNT) - || !cmp_num - || (cmp_start_index > PWM_SOC_CMP_MAX_COUNT) - || (cmp_start_index + cmp_num > PWM_SOC_CMP_MAX_COUNT) - || ((pwm_index > (PWM_SOC_PWM_MAX_COUNT - 1)) - || (pwm_index & 0x1))) { - return status_invalid_argument; - } - - pwm_x->PWMCFG[pwm_index] &= ~PWM_PWMCFG_OEN_MASK; - pwm_x->PWMCFG[pwm_index + 1] &= ~PWM_PWMCFG_OEN_MASK; - - for (i = 0; i < cmp_num; i++) { - pwm_config_cmp(pwm_x, cmp_start_index + i, &cmp[i]); - } - ch_config.cmp_start_index = cmp_start_index; - ch_config.cmp_end_index = cmp_start_index + cmp_num - 1; - ch_config.invert_output = pwm_pair_config->pwm[0].invert_output; - pwm_config_output_channel(pwm_x, pwm_index, &ch_config); - - ch_config.invert_output = pwm_pair_config->pwm[1].invert_output; - pwm_config_output_channel(pwm_x, pwm_index + 1, &ch_config); - - pwm_config_pwm(pwm_x, pwm_index, &pwm_pair_config->pwm[0], true); - pwm_config_pwm(pwm_x, pwm_index + 1, &pwm_pair_config->pwm[1], true); - - return status_success; -} - -hpm_stat_t pwm_setup_waveform(PWM_Type *pwm_x, - uint8_t pwm_index, pwm_config_t *pwm_config, - uint8_t cmp_start_index, pwm_cmp_config_t *cmp, uint8_t cmp_num) -{ - uint8_t i; - pwm_output_channel_t ch_config; - if (!cmp_num - || (cmp_start_index > PWM_SOC_CMP_MAX_COUNT) - || (cmp_start_index + cmp_num > PWM_SOC_CMP_MAX_COUNT)) { - return status_invalid_argument; - } - - for (i = 0; i < cmp_num; i++) { - pwm_config_cmp(pwm_x, cmp_start_index + i, &cmp[i]); - } - ch_config.cmp_start_index = cmp_start_index; - ch_config.cmp_end_index = cmp_start_index + cmp_num - 1; - ch_config.invert_output = pwm_config->invert_output; - pwm_config_output_channel(pwm_x, pwm_index, &ch_config); - if (pwm_index < PWM_SOC_PWM_MAX_COUNT) { - pwm_config_pwm(pwm_x, pwm_index, pwm_config, false); - } - return status_success; -} - -hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp) -{ - pwm_shadow_register_unlock(pwm_x); - pwm_cmp_update_cmp_value(pwm_x, cmp_index, target_cmp, 0); - return status_success; -} - -hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, - uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2) -{ - uint32_t reload = PWM_RLD_RLD_GET(pwm_x->RLD); - if (!target_cmp1) { - target_cmp1 = reload + 1; - } - if (!target_cmp2) { - target_cmp2 = reload + 1; - } - pwm_shadow_register_unlock(pwm_x); - pwm_cmp_update_cmp_value(pwm_x, cmp1_index, target_cmp1, 0); - pwm_cmp_update_cmp_value(pwm_x, cmp2_index, target_cmp2, 0); - return status_success; -} -#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT - -hpm_stat_t pwm_update_raw_hrcmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index, uint32_t target_cmp, - uint16_t target_hrcmp) -{ - pwm_shadow_register_unlock(pwm_x); - pwm_cmp_update_hrcmp_value(pwm_x, cmp_index, target_cmp, target_hrcmp); - return status_success; -} - -hpm_stat_t pwm_update_raw_hrcmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index, - uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2, - uint16_t target_hrcmp1, uint16_t target_hrcmp2) -{ - uint32_t reload = PWM_RLD_RLD_GET(pwm_x->RLD); - if (!target_cmp1) { - target_cmp1 = reload + 1; - } - if (!target_cmp2) { - target_cmp2 = reload + 1; - } - pwm_shadow_register_unlock(pwm_x); - pwm_cmp_update_hrcmp_value(pwm_x, cmp1_index, target_cmp1, target_hrcmp1); - pwm_cmp_update_hrcmp_value(pwm_x, cmp2_index, target_cmp2, target_hrcmp2); - return status_success; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c deleted file mode 100644 index 011ae5874fa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_pwmv2_drv.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_soc_feature.h" -#include "hpm_pwmv2_drv.h" - -void pwmv2_deinit(PWMV2_Type *pwm_x) -{ - pwm_x->IRQ_EN_CMP = 0; - pwm_x->IRQ_EN_RELOAD = 0; - pwm_x->IRQ_EN_CAP_POS = 0; - pwm_x->IRQ_EN_CAP_NEG = 0; - pwm_x->IRQ_EN_FAULT = 0; - pwm_x->IRQ_EN_BURSTEND = 0; - pwm_x->IRQ_EN = 0; - pwm_x->DMA_EN = 0; - pwm_x->IRQ_STS |= pwm_x->IRQ_STS; - pwm_x->IRQ_STS_CMP = 0; - pwm_x->IRQ_STS_RELOAD = 0; - pwm_x->IRQ_STS_CAP_POS = 0; - pwm_x->IRQ_STS_CAP_NEG = 0; - pwm_x->IRQ_STS_FAULT = 0; - pwm_x->IRQ_STS_BURSTEND = 0; - for (uint8_t i = 0; i < PWM_SOC_CMP_MAX_COUNT; i++) { - pwm_x->CMP[i].CFG = 0; - } - for (uint8_t i = 0; i < PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT; i++) { - pwm_x->PWM[i].CFG0 = 0; - pwm_x->PWM[i].CFG1 = 0; - pwm_x->PWM[i].DEAD_AREA = 0; - } - for (uint8_t i = 0; i < PWMV2_SOC_CAL_COUNT_MAX; i++) { - pwm_x->CAL[i].CFG0 = 0; - pwm_x->CAL[i].CFG1 = 0; - } -} - -void pwmv2_config_cmp(PWMV2_Type *pwm_x, uint8_t index, pwmv2_cmp_config_t *config) -{ - pwmv2_select_cmp_source(pwm_x, index, config->cmp_source, config->cmp_source_index); - pwmv2_cmp_update_trig_time(pwm_x, index, config->update_trigger); - if (config->update_trigger == pwm_shadow_register_update_on_trigmux) { - pwmv2_select_cmp_trigmux(pwm_x, index, config->update_trigger_index); - } - if (index >= PWM_CMP_UNABLE_OUTPUT_INDEX) { - pwmv2_cmp_select_counter(pwm_x, index, config->cmp_source_index); - } - if (config->cmp_source == cmp_value_from_shadow_val) { - pwmv2_shadow_register_unlock(pwm_x); - if (config->enable_hrcmp) { - pwmv2_set_shadow_val(pwm_x, config->cmp_source_index, config->cmp, config->hrcmp, config->enable_half_cmp); - } else { - pwmv2_set_shadow_val(pwm_x, config->cmp_source_index, config->cmp, 0, config->enable_half_cmp); - } - pwmv2_shadow_register_lock(pwm_x); - } -} - -void pwmv2_config_async_fault_source(PWMV2_Type *pwm_x, pwm_channel_t index, pwmv2_async_fault_source_config_t *config) -{ - pwm_x->PWM[index].CFG0 = (pwm_x->PWM[index].CFG0 & ~(PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK | PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK)) - | PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET(config->async_signal_from_pad_index) - | PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET(config->fault_async_pad_level); -} - -void pwmv2_config_pwm(PWMV2_Type *pwm_x, pwm_channel_t index, - pwmv2_config_t *config, bool enable_pair_mode) -{ - pwm_x->PWM[index].CFG0 = PWMV2_PWM_CFG0_TRIG_SEL4_SET(config->enable_four_cmp) | - PWMV2_PWM_CFG0_OUT_POLARITY_SET(config->invert_output) | - PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET(config->update_polarity_time); - pwm_x->PWM[index].CFG1 = PWMV2_PWM_CFG1_HIGHZ_EN_N_SET(config->enable_output) | - PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET(config->force_shadow_trigger) | - PWMV2_PWM_CFG1_FAULT_MODE_SET(config->fault_mode) | - PWMV2_PWM_CFG1_FAULT_REC_TIME_SET(config->fault_recovery_trigger) | - PWMV2_PWM_CFG1_PAIR_MODE_SET(enable_pair_mode) | - PWMV2_PWM_CFG1_PWM_LOGIC_SET(config->logic) | - PWMV2_PWM_CFG1_FORCE_TIME_SET(config->force_trigger) | - PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET(config->force_shadow_trigmux_index) | - PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET(config->force_trigmux_index) | - PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET(config->fault_recovery_trigmux_index); - pwmv2_config_async_fault_source(pwm_x, index, &config->async_fault_source); - if (enable_pair_mode) { - pwmv2_set_dead_area(pwm_x, index, config->dead_zone_in_half_cycle); - } -} - -hpm_stat_t pwmv2_setup_waveform(PWMV2_Type *pwm_x, - pwm_channel_t chn, pwmv2_config_t *pwm_config, - uint8_t cmp_start_index, pwmv2_cmp_config_t *cmp, uint8_t cmp_num) -{ - uint8_t i; - - for (i = 0; i < cmp_num; i++) { - pwmv2_config_cmp(pwm_x, cmp_start_index + i, &cmp[i]); - } - pwmv2_config_pwm(pwm_x, chn, pwm_config, false); - - return status_success; -} - -hpm_stat_t pwmv2_setup_waveform_in_pair(PWMV2_Type *pwm_x, pwm_channel_t chn, - pwmv2_pair_config_t *pwm_pair_config, uint8_t cmp_start_index, - pwmv2_cmp_config_t *cmp, uint8_t cmp_num) -{ - uint8_t i; - - for (i = 0; i < cmp_num; i++) { - pwmv2_config_cmp(pwm_x, cmp_start_index + i, &cmp[i]); - } - pwmv2_config_pwm(pwm_x, chn, &pwm_pair_config->pwm[0], true); - pwmv2_config_pwm(pwm_x, chn + 1, &pwm_pair_config->pwm[1], true); - - return status_success; -} - -void pwmv2_setup_cmp_calculate(PWMV2_Type *pwm_x, uint8_t cal_index, pwmv2_cmp_calculate_cfg_t *cal) -{ - pwm_x->CAL[cal_index].CFG0 = PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(cal->up_limit_param) | - PWMV2_CAL_CFG0_CAL_LL_PARAM_SET(cal->low_limit_param) | - PWMV2_CAL_CFG0_CAL_T_PARAM_SET(cal->t_param) | - PWMV2_CAL_CFG0_CAL_D_PARAM_SET(cal->d_param); - pwm_x->CAL[cal_index].CFG1 = PWMV2_CAL_CFG1_CAL_T_INDEX_SET(cal->counter_index) | - PWMV2_CAL_CFG1_CAL_IN_INDEX_SET(cal->in_index) | - PWMV2_CAL_CFG1_CAL_LU_EN_SET(cal->enable_up_limit) | - PWMV2_CAL_CFG1_CAL_LIM_UP_SET(cal->up_limit_offset_index) | - PWMV2_CAL_CFG1_CAL_LL_EN_SET(cal->enbale_low_limit) | - PWMV2_CAL_CFG1_CAL_LIM_LO_SET (cal->low_limit_offset_index) | - PWMV2_CAL_CFG1_CAL_IN_OFF_SET(cal->in_offset_index); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c deleted file mode 100644 index 0c0ff8237ba..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeiv2_drv.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_qeiv2_drv.h" -#include "hpm_enc_pos_drv.h" - -hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) -{ - if (qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { - return status_fail; - } - qeiv2_set_phcnt_cmp_value(qeiv2_x, config->phcnt_cmp_value); - qeiv2_set_spd_pos_cmp_value(qeiv2_x, 0); - qeiv2_set_z_cmp_value(qeiv2_x, config->zcmp_value); - qeiv2_set_cmp_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, config->rotate_dir, true, qeiv2_pos_dir_decrease); - return status_success; -} - -hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) -{ - if (!qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { - return status_fail; - } - qeiv2_set_spd_pos_cmp_value(qeiv2_x, config->pos_cmp_value); - qeiv2_set_cmp_match_option(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_dir); - return status_success; -} - -hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config) -{ - if (qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { - return status_fail; - } - qeiv2_set_phcnt_cmp2_value(qeiv2_x, config->phcnt_cmp_value); - qeiv2_set_spd_pos_cmp2_value(qeiv2_x, 0); - qeiv2_set_z_cmp2_value(qeiv2_x, config->zcmp_value); - qeiv2_set_cmp2_match_option(qeiv2_x, config->ignore_zcmp, false, false, config->ignore_rotate_dir, config->rotate_dir, true, qeiv2_pos_dir_decrease); - return status_success; -} - -hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config) -{ - if (!qeiv2_check_spd_tmr_as_pos_angle(qeiv2_x)) { - return status_fail; - } - qeiv2_set_spd_pos_cmp2_value(qeiv2_x, config->pos_cmp_value); - qeiv2_set_cmp2_match_option(qeiv2_x, true, true, false, true, qeiv2_rotate_dir_forward, config->ignore_pos_dir, config->pos_dir); - return status_success; -} - -void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config) -{ - config->pos_opt = qeiv2_uvw_pos_opt_current; - - config->u_pos_sel[0] = qeiv2_uvw_pos_sel_high; - config->v_pos_sel[0] = qeiv2_uvw_pos_sel_low; - config->w_pos_sel[0] = qeiv2_uvw_pos_sel_high; - - config->u_pos_sel[1] = qeiv2_uvw_pos_sel_high; - config->v_pos_sel[1] = qeiv2_uvw_pos_sel_low; - config->w_pos_sel[1] = qeiv2_uvw_pos_sel_low; - - config->u_pos_sel[2] = qeiv2_uvw_pos_sel_high; - config->v_pos_sel[2] = qeiv2_uvw_pos_sel_high; - config->w_pos_sel[2] = qeiv2_uvw_pos_sel_low; - - config->u_pos_sel[3] = qeiv2_uvw_pos_sel_low; - config->v_pos_sel[3] = qeiv2_uvw_pos_sel_high; - config->w_pos_sel[3] = qeiv2_uvw_pos_sel_low; - - config->u_pos_sel[4] = qeiv2_uvw_pos_sel_low; - config->v_pos_sel[4] = qeiv2_uvw_pos_sel_high; - config->w_pos_sel[4] = qeiv2_uvw_pos_sel_high; - - config->u_pos_sel[5] = qeiv2_uvw_pos_sel_low; - config->v_pos_sel[5] = qeiv2_uvw_pos_sel_low; - config->w_pos_sel[5] = qeiv2_uvw_pos_sel_high; - - config->pos_cfg[0] = encoder_deg_to_position(30); - config->pos_cfg[1] = encoder_deg_to_position(90); - config->pos_cfg[2] = encoder_deg_to_position(150); - config->pos_cfg[3] = encoder_deg_to_position(210); - config->pos_cfg[4] = encoder_deg_to_position(270); - config->pos_cfg[5] = encoder_deg_to_position(330); -} - -hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config) -{ - qeiv2_set_uvw_position_opt(qeiv2_x, config->pos_opt); - for (uint8_t i = 0; i < 6; i++) { - if (config->pos_opt == qeiv2_uvw_pos_opt_next) { - if ((config->u_pos_sel[i] == qeiv2_uvw_pos_sel_edge) - || (config->v_pos_sel[i] == qeiv2_uvw_pos_sel_edge) - || (config->w_pos_sel[i] == qeiv2_uvw_pos_sel_edge)) { - return status_invalid_argument; - } - } - } - - for (uint8_t i = 0; i < 6; i++) { - if (config->pos_opt == qeiv2_uvw_pos_opt_next) { - qeiv2_set_uvw_position_sel(qeiv2_x, i, - (config->u_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, - (config->v_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, - (config->w_pos_sel[i] == qeiv2_uvw_pos_sel_high) ? QEIV2_UVW_POS_OPT_NEX_SEL_HIGH : QEIV2_UVW_POS_OPT_NEX_SEL_LOW, - true); - } else { - qeiv2_set_uvw_position_sel(qeiv2_x, i, config->u_pos_sel[i], config->v_pos_sel[i], config->w_pos_sel[i], true); - } - qeiv2_set_uvw_position(qeiv2_x, i, config->pos_cfg[i]); - } - - return status_success; -} - -void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen) -{ - uint32_t len = filtlen; - uint8_t shift; - for (shift = 0; shift <= 7u; shift++) { - if (shift > 0) { - len >>= 1u; - } - if (len <= 0x1FFu) { - break; - } - } - if (len > 0x1FFu) { - len = 0x1FFu; - shift = 7u; - } - - qeiv2_x->FILT_CFG[phase] = - QEIV2_FILT_CFG_OUTINV_SET(outinv) | QEIV2_FILT_CFG_MODE_SET(mode) | QEIV2_FILT_CFG_SYNCEN_SET(sync) | QEIV2_FILT_CFG_FILTLEN_SET(((shift << 9u) | len)); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c deleted file mode 100644 index 279f093a56a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeo_drv.c +++ /dev/null @@ -1,239 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_qeo_drv.h" - -void qeo_wave_get_default_mode_config(QEO_Type *base, qeo_wave_mode_t *config) -{ - (void) base; - config->wave0.above_max_limit = qeo_wave_above_max_limit_max_val; - config->wave0.high_area0_limit = qeo_wave_high_area_limit_max_val; - config->wave0.high_area1_limit = qeo_wave_high_area_limit_max_val; - config->wave0.low_area0_limit = qeo_wave_low_area_limit_zero; - config->wave0.low_area1_limit = qeo_wave_low_area_limit_zero; - config->wave0.below_min_limit = qeo_wave_below_min_limit_zero; - - config->wave1.above_max_limit = qeo_wave_above_max_limit_max_val; - config->wave1.high_area0_limit = qeo_wave_high_area_limit_max_val; - config->wave1.high_area1_limit = qeo_wave_high_area_limit_max_val; - config->wave1.low_area0_limit = qeo_wave_low_area_limit_zero; - config->wave1.low_area1_limit = qeo_wave_low_area_limit_zero; - config->wave1.below_min_limit = qeo_wave_below_min_limit_zero; - - config->wave2.above_max_limit = qeo_wave_above_max_limit_max_val; - config->wave2.high_area0_limit = qeo_wave_high_area_limit_max_val; - config->wave2.high_area1_limit = qeo_wave_high_area_limit_max_val; - config->wave2.low_area0_limit = qeo_wave_low_area_limit_zero; - config->wave2.low_area1_limit = qeo_wave_low_area_limit_zero; - config->wave2.below_min_limit = qeo_wave_below_min_limit_zero; - - config->saddle_type = 0; - config->wave_type = qeo_wave_cosine; -} - -void qeo_wave_config_mode(QEO_Type *base, qeo_wave_mode_t *config) -{ - /* clear other bit except EN_WAVEx_VD_VQ_INJECT in MODE register */ - base->WAVE.MODE &= QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK - | QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK - | QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK; - - base->WAVE.MODE |= QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(config->wave2.above_max_limit) - | QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(config->wave2.high_area1_limit) - | QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(config->wave2.high_area0_limit) - | QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(config->wave2.low_area1_limit) - | QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(config->wave2.low_area0_limit) - | QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(config->wave2.below_min_limit) - - | QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(config->wave1.above_max_limit) - | QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(config->wave1.high_area1_limit) - | QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(config->wave1.high_area0_limit) - | QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(config->wave1.low_area1_limit) - | QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(config->wave1.low_area0_limit) - | QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(config->wave1.below_min_limit) - - | QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(config->wave0.above_max_limit) - | QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(config->wave0.high_area1_limit) - | QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(config->wave0.high_area0_limit) - | QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(config->wave0.low_area1_limit) - | QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(config->wave0.low_area0_limit) - | QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(config->wave0.below_min_limit) - | QEO_WAVE_MODE_SADDLE_TYPE_SET(config->saddle_type) - | QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(config->wave_type); -} - -void qeo_abz_get_default_mode_config(QEO_Type *base, qeo_abz_mode_t *config) -{ - (void) base; - config->a_inv_pol = false; - config->b_inv_pol = false; - config->z_inv_pol = false; - config->output_type = qeo_abz_output_abz; - config->z_pulse_period = qeo_z_pulse_100_percent; -} - -void qeo_abz_config_mode(QEO_Type *base, qeo_abz_mode_t *config) -{ - base->ABZ.MODE &= ~(QEO_ABZ_MODE_Z_POLARITY_MASK - | QEO_ABZ_MODE_B_POLARITY_MASK - | QEO_ABZ_MODE_A_POLARITY_MASK - | QEO_ABZ_MODE_Z_TYPE_MASK - | QEO_ABZ_MODE_B_TYPE_MASK - | QEO_ABZ_MODE_A_TYPE_MASK); - - base->ABZ.MODE = QEO_ABZ_MODE_Z_POLARITY_SET(config->z_inv_pol) - | QEO_ABZ_MODE_B_POLARITY_SET(config->b_inv_pol) - | QEO_ABZ_MODE_A_POLARITY_SET(config->a_inv_pol); - - if ((config->output_type == qeo_abz_output_pulse_revise) || (config->output_type == qeo_abz_output_up_down)) { - base->ABZ.MODE |= QEO_ABZ_MODE_B_TYPE_SET(config->output_type) - | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); - } else if (config->output_type == qeo_abz_output_three_phase) { - base->ABZ.MODE |= QEO_ABZ_MODE_Z_TYPE_SET(config->output_type) - | QEO_ABZ_MODE_B_TYPE_SET(config->output_type) - | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); - } else { - base->ABZ.MODE |= QEO_ABZ_MODE_Z_TYPE_SET(config->z_pulse_period) - | QEO_ABZ_MODE_B_TYPE_SET(config->output_type) - | QEO_ABZ_MODE_A_TYPE_SET(config->output_type); - } -} - -hpm_stat_t qeo_abz_set_max_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq) -{ - uint32_t count; - - if ((freq > 0xffffffffU / 4U) || ((src_freq % (freq * 4U)) != 0)) { - return status_invalid_argument; - } - count = src_freq / (freq * 4U); - base->ABZ.LINE_WIDTH = QEO_ABZ_LINE_WIDTH_LINE_SET(count); - - return status_success; -} - -hpm_stat_t qeo_abz_set_wdog_frequency(QEO_Type *base, uint32_t src_freq, uint32_t freq) -{ - uint32_t count; - - if ((src_freq % freq) != 0) { - return status_invalid_argument; - } - count = src_freq / freq; - base->ABZ.WDOG_WIDTH = QEO_ABZ_WDOG_WIDTH_WIDTH_SET(count); - base->ABZ.MODE |= QEO_ABZ_MODE_EN_WDOG_MASK; - - return status_success; -} - -void qeo_pwm_get_default_safety_table_config(QEO_Type *base, qeo_pwm_safety_output_table_t *table) -{ - (void) base; - table->pwm7_output = qeo_pwm_safety_output_highz; - table->pwm6_output = qeo_pwm_safety_output_highz; - table->pwm5_output = qeo_pwm_safety_output_highz; - table->pwm4_output = qeo_pwm_safety_output_highz; - table->pwm3_output = qeo_pwm_safety_output_highz; - table->pwm2_output = qeo_pwm_safety_output_highz; - table->pwm1_output = qeo_pwm_safety_output_highz; - table->pwm0_output = qeo_pwm_safety_output_highz; -} - -void qeo_pwm_get_default_phase_table_config(QEO_Type *base, qeo_pwm_phase_output_table_t *table) -{ - (void) base; - table->pwm7_output = qeo_pwm_output_force_0; - table->pwm6_output = qeo_pwm_output_force_0; - table->pwm5_output = qeo_pwm_output_force_0; - table->pwm4_output = qeo_pwm_output_force_0; - table->pwm3_output = qeo_pwm_output_force_0; - table->pwm2_output = qeo_pwm_output_force_0; - table->pwm1_output = qeo_pwm_output_force_0; - table->pwm0_output = qeo_pwm_output_force_0; -} - -void qeo_pwm_get_default_mode_config(QEO_Type *base, qeo_pwm_mode_t *config) -{ - (void) base; - config->phase_num = 4; - config->shield_hardware_trig_safety = false; - config->revise_pairs_output = false; -} - -void qeo_pwm_config_mode(QEO_Type *base, qeo_pwm_mode_t *config) -{ - base->PWM.MODE &= ~(QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK - | QEO_PWM_MODE_REVISE_UP_DN_MASK - | QEO_PWM_MODE_PHASE_NUM_MASK); - base->PWM.MODE |= QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(config->shield_hardware_trig_safety) - | QEO_PWM_MODE_REVISE_UP_DN_SET(config->revise_pairs_output) - | QEO_PWM_MODE_PHASE_NUM_SET(config->phase_num); -} - -void qeo_pwm_config_phase_table(QEO_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table) -{ - base->PWM.PHASE_TABLE[index] = QEO_PWM_PHASE_TABLE_PWM7_SET(table->pwm7_output) - | QEO_PWM_PHASE_TABLE_PWM6_SET(table->pwm6_output) - | QEO_PWM_PHASE_TABLE_PWM5_SET(table->pwm5_output) - | QEO_PWM_PHASE_TABLE_PWM4_SET(table->pwm4_output) - | QEO_PWM_PHASE_TABLE_PWM3_SET(table->pwm3_output) - | QEO_PWM_PHASE_TABLE_PWM2_SET(table->pwm2_output) - | QEO_PWM_PHASE_TABLE_PWM1_SET(table->pwm1_output) - | QEO_PWM_PHASE_TABLE_PWM0_SET(table->pwm0_output); -} - -void qeo_pwm_config_safety_table(QEO_Type *base, qeo_pwm_safety_output_table_t *table) -{ - /*< clear safety table */ - base->PWM.MODE &= ~(QEO_PWM_MODE_PWM7_SAFETY_MASK - | QEO_PWM_MODE_PWM6_SAFETY_MASK - | QEO_PWM_MODE_PWM5_SAFETY_MASK - | QEO_PWM_MODE_PWM4_SAFETY_MASK - | QEO_PWM_MODE_PWM3_SAFETY_MASK - | QEO_PWM_MODE_PWM2_SAFETY_MASK - | QEO_PWM_MODE_PWM1_SAFETY_MASK - | QEO_PWM_MODE_PWM0_SAFETY_MASK); - /*< set safety table */ - base->PWM.MODE |= QEO_PWM_MODE_PWM7_SAFETY_SET(table->pwm7_output) - | QEO_PWM_MODE_PWM6_SAFETY_SET(table->pwm6_output) - | QEO_PWM_MODE_PWM5_SAFETY_SET(table->pwm5_output) - | QEO_PWM_MODE_PWM4_SAFETY_SET(table->pwm4_output) - | QEO_PWM_MODE_PWM3_SAFETY_SET(table->pwm3_output) - | QEO_PWM_MODE_PWM2_SAFETY_SET(table->pwm2_output) - | QEO_PWM_MODE_PWM1_SAFETY_SET(table->pwm1_output) - | QEO_PWM_MODE_PWM0_SAFETY_SET(table->pwm0_output); -} - -/** - * If the line step of the position to be synchronized after position value - * to ABZ value conversion is the same as the current position, will hang the ABZ. - * ABZ value = m lines + n line_steps(0 <= m <= 3) - * This API will check the sync_pos and shift it if needed - */ -void qeo_abz_position_sync(QEO_Type *base, uint32_t lines, uint32_t sync_pos) -{ - uint32_t line_width; - uint32_t line_step_width; - uint32_t shift_pos; - uint32_t current_line_step; - uint32_t temp; - - line_width = (uint32_t)(0x100000000UL / lines); - line_step_width = line_width / 4U; - current_line_step = base->DEBUG2 & 0x3; /* get the lowest two bits */ - temp = (sync_pos % line_width) / line_step_width; - if (temp == current_line_step) { - shift_pos = sync_pos - line_step_width; - } else { - shift_pos = sync_pos; - } - - base->ABZ.POSTION_SYNC = QEO_ABZ_POSTION_SYNC_POSTION_MASK; - qeo_enable_software_position_inject(base); - qeo_software_position_inject(base, shift_pos); - qeo_disable_software_position_inject(base); -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c deleted file mode 100644 index 65be47060b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_qeov2_drv.c +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_qeov2_drv.h" - -void qeo_wave_get_default_mode_config(QEOV2_Type *base, qeo_wave_mode_t *config) -{ - (void)base; - - config->wave0.above_max_limit = qeo_wave_above_max_limit_max_val; - config->wave0.high_area0_limit = qeo_wave_high_area_limit_max_val; - config->wave0.high_area1_limit = qeo_wave_high_area_limit_max_val; - config->wave0.low_area0_limit = qeo_wave_low_area_limit_zero; - config->wave0.low_area1_limit = qeo_wave_low_area_limit_zero; - config->wave0.below_min_limit = qeo_wave_below_min_limit_zero; - - config->wave1.above_max_limit = qeo_wave_above_max_limit_max_val; - config->wave1.high_area0_limit = qeo_wave_high_area_limit_max_val; - config->wave1.high_area1_limit = qeo_wave_high_area_limit_max_val; - config->wave1.low_area0_limit = qeo_wave_low_area_limit_zero; - config->wave1.low_area1_limit = qeo_wave_low_area_limit_zero; - config->wave1.below_min_limit = qeo_wave_below_min_limit_zero; - - config->wave2.above_max_limit = qeo_wave_above_max_limit_max_val; - config->wave2.high_area0_limit = qeo_wave_high_area_limit_max_val; - config->wave2.high_area1_limit = qeo_wave_high_area_limit_max_val; - config->wave2.low_area0_limit = qeo_wave_low_area_limit_zero; - config->wave2.low_area1_limit = qeo_wave_low_area_limit_zero; - config->wave2.below_min_limit = qeo_wave_below_min_limit_zero; - - config->dq_valid_trig_enable = false; - config->pos_valid_trig_enable = true; - config->vd_vq_inject_enable = false; - config->vd_vq_from_sw = false; - - config->saddle_type = 0; - config->wave_type = qeo_wave_cosine; -} - -void qeo_wave_config_mode(QEOV2_Type *base, qeo_wave_mode_t *config) -{ - base->WAVE.MODE = QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(config->wave2.above_max_limit) - | QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(config->wave2.high_area1_limit) - | QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(config->wave2.high_area0_limit) - | QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(config->wave2.low_area1_limit) - | QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(config->wave2.low_area0_limit) - | QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(config->wave2.below_min_limit) - - | QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(config->wave1.above_max_limit) - | QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(config->wave1.high_area1_limit) - | QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(config->wave1.high_area0_limit) - | QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(config->wave1.low_area1_limit) - | QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(config->wave1.low_area0_limit) - | QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(config->wave1.below_min_limit) - - | QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(config->wave0.above_max_limit) - | QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(config->wave0.high_area1_limit) - | QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(config->wave0.high_area0_limit) - | QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(config->wave0.low_area1_limit) - | QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(config->wave0.low_area0_limit) - | QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(config->wave0.below_min_limit) - | QEOV2_WAVE_MODE_SADDLE_TYPE_SET(config->saddle_type) - | QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(config->wave_type) - | QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SET(config->dq_valid_trig_enable) - | QEOV2_WAVE_MODE_ENABLE_POS_VALID_SET(config->pos_valid_trig_enable) - | QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SET(config->vd_vq_inject_enable) - | QEOV2_WAVE_MODE_VD_VQ_SEL_SET(config->vd_vq_from_sw); -} - -void qeo_abz_get_default_mode_config(QEOV2_Type *base, qeo_abz_mode_t *config) -{ - (void)base; - - config->a_inv_pol = false; - config->b_inv_pol = false; - config->z_inv_pol = false; - config->enable_wdog = false; - config->sync_step_position = true; - config->reverse_align_clk_falling_edge = false; - config->output_type = qeo_abz_output_abz; -} - -void qeo_abz_config_mode(QEOV2_Type *base, qeo_abz_mode_t *config) -{ - base->ABZ.MODE &= ~(QEOV2_ABZ_MODE_Z_POLARITY_MASK - | QEOV2_ABZ_MODE_B_POLARITY_MASK - | QEOV2_ABZ_MODE_A_POLARITY_MASK - | QEOV2_ABZ_MODE_Z_TYPE_MASK - | QEOV2_ABZ_MODE_B_TYPE_MASK - | QEOV2_ABZ_MODE_A_TYPE_MASK - | QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK - | QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK - | QEOV2_ABZ_MODE_EN_WDOG_MASK); - - base->ABZ.MODE = QEOV2_ABZ_MODE_Z_POLARITY_SET(config->z_inv_pol) - | QEOV2_ABZ_MODE_B_POLARITY_SET(config->b_inv_pol) - | QEOV2_ABZ_MODE_A_POLARITY_SET(config->a_inv_pol) - | QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SET(config->reverse_align_clk_falling_edge) - | QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SET(config->sync_step_position) - | QEOV2_ABZ_MODE_EN_WDOG_SET(config->enable_wdog) - | QEOV2_ABZ_MODE_B_TYPE_SET(config->output_type) - | QEOV2_ABZ_MODE_A_TYPE_SET(config->output_type); - - if ((config->output_type == qeo_abz_output_pulse_revise) || (config->output_type == qeo_abz_output_up_down)) { - base->ABZ.MODE |= QEOV2_ABZ_MODE_Z_TYPE_SET(qeo_z_as_no_output_signal); - } else if (config->output_type == qeo_abz_output_three_phase) { - base->ABZ.MODE |= QEOV2_ABZ_MODE_Z_TYPE_SET(qeo_z_as_third_phase_signal); - } else { - base->ABZ.MODE |= QEOV2_ABZ_MODE_Z_TYPE_SET(qeo_z_as_zero_signal_mode0); - } -} - -void qeo_abz_get_default_z_output_mode(QEOV2_Type *base, qeo_z_output_mode_t *mode) -{ - (void)base; - - /* z output width 1/4 ab period */ - mode->type = qeo_z_as_zero_signal_mode0; - mode->start_line = 0; - mode->end_line = 0; - mode->start_step = 0; - mode->end_step = 0; - mode->width = 0; /* used for qeo_z_as_zero_signal_mode1 */ -} - -void qeo_abz_config_z_output_mode(QEOV2_Type *base, qeo_z_output_mode_t *mode) -{ - if (mode->type == qeo_z_as_zero_signal_mode0) { - base->ABZ.Z_START = mode->start_line; - base->ABZ.Z_END = mode->end_line; - base->ABZ.Z_OFFSET = QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SET(mode->start_step) | QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SET(mode->end_step); - } else if (mode->type == qeo_z_as_zero_signal_mode1) { - base->ABZ.Z_START = mode->start_line; - base->ABZ.Z_PULSE_WIDTH = mode->width; - } - - base->ABZ.MODE = (base->ABZ.MODE & ~QEOV2_ABZ_MODE_Z_TYPE_MASK) | QEOV2_ABZ_MODE_Z_TYPE_SET(mode->type); -} - -hpm_stat_t qeo_abz_set_max_frequency(QEOV2_Type *base, uint32_t src_freq, uint32_t freq) -{ - uint32_t count; - - if ((freq > 0xffffffffU / 4U) || ((src_freq % (freq * 4U)) != 0)) { - return status_invalid_argument; - } - count = src_freq / (freq * 4U); - base->ABZ.LINE_WIDTH = QEOV2_ABZ_LINE_WIDTH_LINE_SET(count); - - return status_success; -} - -hpm_stat_t qeo_abz_set_wdog_frequency(QEOV2_Type *base, uint32_t src_freq, uint32_t freq) -{ - uint32_t count; - - if ((src_freq % freq) != 0) { - return status_invalid_argument; - } - count = src_freq / freq; - base->ABZ.WDOG_WIDTH = QEOV2_ABZ_WDOG_WIDTH_WIDTH_SET(count); - base->ABZ.MODE |= QEOV2_ABZ_MODE_EN_WDOG_MASK; - - return status_success; -} - -void qeo_pwm_get_default_safety_table_config(QEOV2_Type *base, qeo_pwm_safety_output_table_t *table) -{ - (void)base; - - table->pwm7_output = qeo_pwm_safety_output_highz; - table->pwm6_output = qeo_pwm_safety_output_highz; - table->pwm5_output = qeo_pwm_safety_output_highz; - table->pwm4_output = qeo_pwm_safety_output_highz; - table->pwm3_output = qeo_pwm_safety_output_highz; - table->pwm2_output = qeo_pwm_safety_output_highz; - table->pwm1_output = qeo_pwm_safety_output_highz; - table->pwm0_output = qeo_pwm_safety_output_highz; -} - -void qeo_pwm_get_default_phase_table_config(QEOV2_Type *base, qeo_pwm_phase_output_table_t *table) -{ - (void)base; - - table->pwm7_output = qeo_pwm_output_force_0; - table->pwm6_output = qeo_pwm_output_force_0; - table->pwm5_output = qeo_pwm_output_force_0; - table->pwm4_output = qeo_pwm_output_force_0; - table->pwm3_output = qeo_pwm_output_force_0; - table->pwm2_output = qeo_pwm_output_force_0; - table->pwm1_output = qeo_pwm_output_force_0; - table->pwm0_output = qeo_pwm_output_force_0; -} - -void qeo_pwm_get_default_mode_config(QEOV2_Type *base, qeo_pwm_mode_t *config) -{ - (void)base; - - config->phase_num = 4; - config->shield_hardware_trig_safety = false; - config->revise_pairs_output = false; -} - -void qeo_pwm_config_mode(QEOV2_Type *base, qeo_pwm_mode_t *config) -{ - base->PWM.MODE &= ~(QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK - | QEOV2_PWM_MODE_REVISE_UP_DN_MASK - | QEOV2_PWM_MODE_PHASE_NUM_MASK); - base->PWM.MODE |= QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SET(config->shield_hardware_trig_safety) - | QEOV2_PWM_MODE_REVISE_UP_DN_SET(config->revise_pairs_output) - | QEOV2_PWM_MODE_PHASE_NUM_SET(config->phase_num); -} - -void qeo_pwm_config_phase_table(QEOV2_Type *base, uint8_t index, qeo_pwm_phase_output_table_t *table) -{ - base->PWM.PHASE_TABLE[index] = QEOV2_PWM_PHASE_TABLE_PWM7_SET(table->pwm7_output) - | QEOV2_PWM_PHASE_TABLE_PWM6_SET(table->pwm6_output) - | QEOV2_PWM_PHASE_TABLE_PWM5_SET(table->pwm5_output) - | QEOV2_PWM_PHASE_TABLE_PWM4_SET(table->pwm4_output) - | QEOV2_PWM_PHASE_TABLE_PWM3_SET(table->pwm3_output) - | QEOV2_PWM_PHASE_TABLE_PWM2_SET(table->pwm2_output) - | QEOV2_PWM_PHASE_TABLE_PWM1_SET(table->pwm1_output) - | QEOV2_PWM_PHASE_TABLE_PWM0_SET(table->pwm0_output); -} - -void qeo_pwm_config_safety_table(QEOV2_Type *base, qeo_pwm_safety_output_table_t *table) -{ - /*< clear safety table */ - base->PWM.MODE &= ~(QEOV2_PWM_MODE_PWM7_SAFETY_MASK - | QEOV2_PWM_MODE_PWM6_SAFETY_MASK - | QEOV2_PWM_MODE_PWM5_SAFETY_MASK - | QEOV2_PWM_MODE_PWM4_SAFETY_MASK - | QEOV2_PWM_MODE_PWM3_SAFETY_MASK - | QEOV2_PWM_MODE_PWM2_SAFETY_MASK - | QEOV2_PWM_MODE_PWM1_SAFETY_MASK - | QEOV2_PWM_MODE_PWM0_SAFETY_MASK); - /*< set safety table */ - base->PWM.MODE |= QEOV2_PWM_MODE_PWM7_SAFETY_SET(table->pwm7_output) - | QEOV2_PWM_MODE_PWM6_SAFETY_SET(table->pwm6_output) - | QEOV2_PWM_MODE_PWM5_SAFETY_SET(table->pwm5_output) - | QEOV2_PWM_MODE_PWM4_SAFETY_SET(table->pwm4_output) - | QEOV2_PWM_MODE_PWM3_SAFETY_SET(table->pwm3_output) - | QEOV2_PWM_MODE_PWM2_SAFETY_SET(table->pwm2_output) - | QEOV2_PWM_MODE_PWM1_SAFETY_SET(table->pwm1_output) - | QEOV2_PWM_MODE_PWM0_SAFETY_SET(table->pwm0_output); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c deleted file mode 100644 index fae443fedfa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rdc_drv.c +++ /dev/null @@ -1,234 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_rdc_drv.h" - -void rdc_output_config(RDC_Type *ptr, rdc_output_cfg_t *cfg) -{ - uint32_t rate; - - rate = cfg->excitation_period_cycle >> (cfg->excitation_precision + 2); - ptr->EXC_TIMMING = RDC_EXC_TIMMING_SMP_RATE_SET(rate) | - RDC_EXC_TIMMING_SMP_NUM_SET(cfg->excitation_precision) | - RDC_EXC_TIMMING_PWM_PRD_SET(cfg->pwm_period)| - RDC_EXC_TIMMING_SWAP_SET(cfg->output_swap); - if (cfg->mode == rdc_output_dac) { - ptr->EXC_SCALING = RDC_EXC_SCALING_AMP_MAN_SET(cfg->amp_man) | - RDC_EXC_SCALING_AMP_EXP_SET(cfg->amp_exp); - ptr->EXC_OFFSET = RDC_EXC_OFFSET_AMP_OFFSET_SET(cfg->amp_offset + 0x800000); - ptr->OUT_CTL = RDC_OUT_CTL_CH_I_SEL_SET(cfg->dac_chn_i_sel) | - RDC_OUT_CTL_CH_Q_SEL_SET(cfg->dac_chn_q_sel); - } else if (cfg->mode == rdc_output_pwm) { - ptr->PWM_SCALING = RDC_EXC_SCALING_AMP_MAN_SET(cfg->amp_man) | - RDC_EXC_SCALING_AMP_EXP_SET(cfg->amp_exp) | - RDC_PWM_SCALING_DITHER_SET(cfg->pwm_dither_enable) | - RDC_PWM_SCALING_P_POL_SET(cfg->pwm_exc_p_low_active) | - RDC_PWM_SCALING_N_POL_SET(cfg->pwm_exc_n_low_active); - ptr->PWM_OFFSET = RDC_PWM_OFFSET_AMP_OFFSET_SET(cfg->amp_offset + (rate >> 1)); - ptr->PWM_DZ = RDC_PWM_DZ_DZ_N_SET(cfg->pwm_deadzone_n) | - RDC_PWM_DZ_DZ_P_SET(cfg->pwm_deadzone_p); - } - if (cfg->trig_by_hw) { - ptr->EXC_SYNC_DLY = RDC_EXC_SYNC_DLY_DELAY_SET(cfg->hw_trig_delay); - } else { - ptr->EXC_SYNC_DLY = RDC_EXC_SYNC_DLY_DISABLE_MASK; - } -} - - -void rdc_input_config(RDC_Type *ptr, rdc_input_cfg_t *cfg) -{ - ptr->RDC_CTL = (ptr->RDC_CTL & (~(RDC_RDC_CTL_RECTIFY_SEL_MASK | RDC_RDC_CTL_ACC_LEN_MASK -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) - | RDC_RDC_CTL_ACC_FAST_MASK -#endif - | RDC_RDC_CTL_TS_SEL_MASK))) - | RDC_RDC_CTL_RECTIFY_SEL_SET(cfg->rectify_signal_sel) - | RDC_RDC_CTL_ACC_LEN_SET(cfg->acc_cycle_len) -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) - | RDC_RDC_CTL_ACC_FAST_SET(cfg->acc_fast) -#endif - | RDC_RDC_CTL_TS_SEL_SET(cfg->acc_stamp); - ptr->IN_CTL = RDC_IN_CTL_PORT_I_SEL_SET(cfg->acc_input_port_i) | - RDC_IN_CTL_CH_I_SEL_SET(cfg->acc_input_chn_i) | - RDC_IN_CTL_PORT_Q_SEL_SET(cfg->acc_input_port_q) | - RDC_IN_CTL_CH_Q_SEL_SET(cfg->acc_input_chn_q); -} - -uint32_t rdc_get_acc_avl(RDC_Type *ptr, rdc_input_acc_chn_t chn) -{ - if (chn == rdc_acc_chn_i) { - return RDC_ACC_I_ACC_GET(ptr->ACC_I); - } else { - return RDC_ACC_Q_ACC_GET(ptr->ACC_Q); - } -} - -void rdc_output_trig_offset_config(RDC_Type *ptr, rdc_output_trig_chn_t chn, int32_t offset) -{ - if (chn == trigger_out_0) { - ptr->TRIG_OUT0_CFG = (ptr->TRIG_OUT0_CFG & (~RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK)) | - RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(offset + RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK + 1); - } else if (chn == trigger_out_1) { - ptr->TRIG_OUT1_CFG = (ptr->TRIG_OUT1_CFG & (~RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK)) | - RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(offset + RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK + 1); - } -} - -void rdc_output_trig_enable(RDC_Type *ptr, rdc_output_trig_chn_t chn) -{ - if (chn == trigger_out_0) { - ptr->TRIG_OUT0_CFG |= RDC_TRIG_OUT0_CFG_ENABLE_MASK; - } else if (chn == trigger_out_1) { - ptr->TRIG_OUT1_CFG |= RDC_TRIG_OUT1_CFG_ENABLE_MASK; - } -} - -void rdc_output_trig_disable(RDC_Type *ptr, rdc_output_trig_chn_t chn) -{ - if (chn == trigger_out_0) { - ptr->TRIG_OUT0_CFG &= ~RDC_TRIG_OUT0_CFG_ENABLE_MASK; - } else if (chn == trigger_out_1) { - ptr->TRIG_OUT1_CFG &= ~RDC_TRIG_OUT1_CFG_ENABLE_MASK; - } -} - -int32_t rdc_get_i_maxval(RDC_Type *ptr) -{ - uint32_t val; - - val = ptr->MAX_I; - if (RDC_MAX_I_VALID_GET(val)) { - return RDC_MAX_I_MAX_GET(val); - } else { - return -1; - } - -} - -int32_t rdc_get_i_minval(RDC_Type *ptr) -{ - uint32_t val; - - val = ptr->MIN_I; - if (RDC_MIN_I_VALID_GET(val)) { - return RDC_MIN_I_MIN_GET(val); - } else { - return -1; - } -} - -int32_t rdc_get_q_maxval(RDC_Type *ptr) -{ - uint32_t val; - - val = ptr->MAX_Q; - if (RDC_MAX_Q_VALID_GET(val)) { - return RDC_MAX_Q_MAX_GET(val); - } else { - return -1; - } -} - -int32_t rdc_get_q_minval(RDC_Type *ptr) -{ - uint32_t val; - - val = ptr->MIN_Q; - if (RDC_MIN_Q_VALID_GET(val)) { - return RDC_MIN_Q_MIN_GET(val); - } else { - return -1; - } -} - -void rdc_set_edge_detection_offset(RDC_Type *ptr, rdc_input_acc_chn_t chn, int32_t offset) -{ - if (chn == rdc_acc_chn_i) { - ptr->THRS_I = RDC_THRS_I_THRS_SET(offset); - } else { - ptr->THRS_Q = RDC_THRS_Q_THRS_SET(offset); - } -} - -void rdc_set_acc_config(RDC_Type *ptr, rdc_acc_cfg_t *cfg) -{ - ptr->EDG_DET_CTL = RDC_EDG_DET_CTL_FILTER_SET(cfg->continue_edge_num) | - RDC_EDG_DET_CTL_HOLD_SET(cfg->edge_distance); - if (cfg->right_shift_without_sign < 9) { - ptr->ACC_SCALING = RDC_ACC_SCALING_ACC_SHIFT_SET(8 - cfg->right_shift_without_sign); - } else { - ptr->ACC_SCALING = RDC_ACC_SCALING_ACC_SHIFT_SET(cfg->right_shift_without_sign); - } - if (cfg->error_data_remove) { - ptr->ACC_SCALING |= RDC_ACC_SCALING_TOXIC_LK_MASK; - } else { - ptr->ACC_SCALING &= ~RDC_ACC_SCALING_TOXIC_LK_MASK; - } - ptr->EXC_PERIOD = RDC_EXC_PERIOD_EXC_PERIOD_SET(cfg->exc_carrier_period); - ptr->SYNC_DELAY_I = RDC_SYNC_DELAY_I_DELAY_SET(cfg->sync_delay_i); - ptr->SYNC_DELAY_Q = RDC_SYNC_DELAY_Q_DELAY_SET(cfg->sync_delay_q); - ptr->AMP_MAX = RDC_AMP_MAX_MAX_SET(cfg->amp_max); - ptr->AMP_MIN = RDC_AMP_MIN_MIN_SET(cfg->amp_min); -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) - ptr->THRS_I = (ptr->THRS_I & ~RDC_THRS_I_THRS4ACC_MASK) | RDC_THRS_I_THRS4ACC_SET(cfg->enable_i_thrs_data_for_acc); - ptr->THRS_Q = (ptr->THRS_Q & ~RDC_THRS_Q_THRS4ACC_MASK) | RDC_THRS_Q_THRS4ACC_SET(cfg->enable_q_thrs_data_for_acc); -#endif -} - -void rdc_set_acc_sync_delay(RDC_Type *ptr, rdc_input_acc_chn_t chn, uint32_t delay) -{ - if (chn == rdc_acc_chn_i) { - ptr->SYNC_DELAY_I = RDC_SYNC_DELAY_I_DELAY_SET(delay); - } else { - ptr->SYNC_DELAY_Q = RDC_SYNC_DELAY_Q_DELAY_SET(delay); - } -} - -#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR) - -#define RDC_IIR_LOG2 (0.301029995663f) -static float rdc_iir_log(float x) -{ - if (x <= 0) { - return 0.0 / 0.0; - } - - float result = 0; - float term = (x - 1) / (x + 1); - float power = term; - for (int n = 1; n <= 100; n += 2) { - result += power / n; - power *= term * term; - } - - return 2 * result; -} - -hpm_stat_t rdc_config_iir_parameter(RDC_Type *ptr, rdc_iir_cfg_t *iir_cfg) -{ - int32_t b_val, a1_val, a2_val; - - b_val = (rdc_iir_log(1.0f / iir_cfg->b) / RDC_IIR_LOG2) - 5; - if ((b_val < 0) || ((uint32_t)b_val > RDC_IIR_B_IIR_B_MASK)) { - return status_invalid_argument; - } - a1_val = iir_cfg->a1 * 256; - if ((a1_val < 0) || ((uint32_t)a1_val > RDC_IIR_A_IIR_A1_MASK)) { - return status_invalid_argument; - } - a2_val = iir_cfg->a2 * 256; - if ((a2_val < 0) || ((uint32_t)a2_val > (RDC_IIR_A_IIR_A2_MASK >> RDC_IIR_A_IIR_A2_SHIFT))) { - return status_invalid_argument; - } - ptr->IIR_B = RDC_IIR_B_IIR_B_SET(b_val) | RDC_IIR_B_LOWPASS_SET(iir_cfg->enable_lowpass); - ptr->IIR_A = RDC_IIR_A_IIR_A1_SET(a1_val) | RDC_IIR_A_IIR_A2_SET(a2_val); - - return status_success; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c deleted file mode 100644 index c3a0565a505..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rng_drv.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_rng_drv.h" - -hpm_stat_t rng_run_selftest(RNG_Type *ptr) -{ - uint32_t status; - - ptr->CMD |= RNG_CMD_SLFCHK_MASK; - do { - status = ptr->STA; - } while (!(status & (RNG_STA_FUNCERR_MASK | RNG_STA_SCDN_MASK))); - - if ((status & (RNG_STA_SCPF_MASK | RNG_STA_FUNCERR_MASK))) { - return status; - } - - return status_success; -} - -hpm_stat_t rng_feed_rand_to_sdp(RNG_Type *ptr) -{ - uint32_t i = 0; - uint32_t status; - uint32_t fifo_level; - hpm_stat_t stat = status_success; - - for (i = 0; i < ARRAY_SIZE(ptr->R2SK); i++) { - status = ptr->STA; - if (status & RNG_STA_FUNCERR_MASK) { - stat = status_fail; - break; - } - - do { - fifo_level = (ptr->STA & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT; - } while (!fifo_level); - - __asm volatile ("" : : "r" (ptr->R2SK[i])); - } - return stat; -} - -static hpm_stat_t rng_rand(RNG_Type *ptr, void *buf, uint32_t count_in_byte, bool wait) -{ - uint32_t i; - uint32_t status; - volatile uint32_t fifo_level; - hpm_stat_t stat = status_success; - - if (count_in_byte < 4) { - return status_invalid_argument; - } - - for (i = 0; i < (count_in_byte / 4); i++) { - status = ptr->STA; - if (status & RNG_STA_FUNCERR_MASK) { - stat = status_fail; - break; - } - - do { - fifo_level = (ptr->STA & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT; - } while (!fifo_level && wait); - - if (fifo_level) { - *(uint32_t *)((uint32_t)buf + i * sizeof(uint32_t)) = ptr->FO2B; - } else { - stat = status_rng_not_available; - break; - } - } - - return stat; -} - -hpm_stat_t rng_rand_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte) -{ - return rng_rand(ptr, buf, count_in_byte, true); -} - -hpm_stat_t rng_rand_no_wait(RNG_Type *ptr, void *buf, uint32_t count_in_byte) -{ - return rng_rand(ptr, buf, count_in_byte, false); -} - -hpm_stat_t rng_init(RNG_Type *ptr) -{ - hpm_stat_t stat = status_success; - - /* clear interrupt and error */ - ptr->CMD |= RNG_CMD_CLRERR_MASK; - - /* generating seed */ - ptr->CMD |= RNG_CMD_GENSD_MASK; - while (!(ptr->STA & RNG_STA_FSDDN_MASK)) { - if (ptr->STA & RNG_STA_FUNCERR_MASK) { - stat = status_fail; - break; - } - } - if (stat != status_success) { - return stat; - } - - /* enable auto seeding */ - ptr->CTRL |= RNG_CTRL_AUTRSD_MASK; - - return stat; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c deleted file mode 100644 index d5ba5325765..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_rtc_drv.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_rtc_drv.h" - - -hpm_stat_t rtc_config_time(RTC_Type *base, time_t time) -{ - base->SECOND = (uint32_t)time; - return status_success; -} - -time_t rtc_get_time(RTC_Type *base) -{ - time_t time = (time_t)base->SECOND; - return time; -} - -struct timeval rtc_get_timeval(RTC_Type *base) -{ - struct timeval tm; - - base->SUB_SNAP = 0; /* Lock shadow registers first */ - - /* Convert sub-second ticks into micro-second */ - uint32_t sub_sec = (uint32_t)((base->SUB_SNAP >> 17) * 1.0 * 1000000 / 32768); - - tm.tv_sec = base->SEC_SNAP; - tm.tv_usec = sub_sec; - - return tm; -} - -hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((config == NULL) || (config->index > 1U) || (config->type > RTC_ALARM_TYPE_ABSOLUTE_TIME_ONE_SHOT)) { - break; - } - uint32_t alarm_inc = 0; - uint32_t alarm; - if (config->type == RTC_ALARM_TYPE_ONE_SHOT) { - uint32_t current_sec = base->SECOND; - alarm = current_sec + config->period; - if (alarm < current_sec) { - break; - } - } else if (config->type == RTC_ALARM_TYPE_PERIODIC) { - uint32_t current_sec = base->SECOND; - alarm_inc = config->period; - alarm = current_sec + config->period; - if (alarm < current_sec) { - break; - } - } else { - alarm = config->period; - } - - if (config->index == 0U) { - base->ALARM0 = alarm; - base->ALARM0_INC = alarm_inc; - } else { - base->ALARM1 = alarm; - base->ALARM1_INC = alarm_inc; - } - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c deleted file mode 100644 index 14dd1462c77..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdm_drv.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sdm_drv.h" - -#ifndef HPM_LIN_DRV_RETRY_COUNT -#define HPM_LIN_DRV_RETRY_COUNT (5000U) -#endif - - -void sdm_get_default_module_control(SDM_Type *ptr, sdm_control_t *control) -{ - (void) ptr; - control->clk_signal_sync = 0xf; /*!< configure clk sync for all channels */ - control->data_signal_sync = 0xf; /*!< configure data sync for all channels */ - control->interrupt_en = false; -} - -void sdm_init_module(SDM_Type *ptr, sdm_control_t *control) -{ - /* software reset */ - ptr->CTRL |= SDM_CTRL_SFTRST_MASK; - ptr->CTRL &= ~SDM_CTRL_SFTRST_MASK; - - ptr->CTRL |= SDM_CTRL_SYNC_MCLK_SET(control->clk_signal_sync) - | SDM_CTRL_SYNC_MDAT_SET(control->data_signal_sync) - | SDM_CTRL_IE_SET(control->interrupt_en); -} - -void sdm_get_channel_common_setting(SDM_Type *ptr, sdm_channel_common_config_t *config) -{ - (void) ptr; - config->sampling_mode = sdm_sampling_rising_clk_edge; - config->enable_err_interrupt = false; - config->enable_data_ready_interrupt = false; -} - -void sdm_config_channel_common_setting(SDM_Type *ptr, uint8_t ch_index, sdm_channel_common_config_t *config) -{ - if (config->enable_err_interrupt) { - ptr->INT_EN |= CHN_ERR_MASK(ch_index); - } - - if (config->enable_data_ready_interrupt) { - ptr->INT_EN |= CHN_DRY_MASK(ch_index); - } - - ptr->CTRL &= ~CHN_SAMPLING_MODE_MASK(ch_index); - ptr->CTRL |= config->sampling_mode << CHN_SAMPLING_MODE_SHIFT(ch_index); -} - -void sdm_get_channel_default_filter_config(SDM_Type *ptr, sdm_filter_config_t *filter_config) -{ - (void) ptr; - filter_config->fifo_threshold = 8; - filter_config->en_fifo_threshold_int = true; - filter_config->manchester_threshold = 0; - filter_config->wdg_threshold = 255; - filter_config->en_af_int = 0; - filter_config->en_data_overflow_int = 1; - filter_config->en_cic_data_saturation_int = 1; - filter_config->en_data_ready_int = 1; - filter_config->sync_source = 0; - filter_config->fifo_clean_on_sync = 0; - filter_config->wtsynaclr = 0; - filter_config->wtsynmclr = 0; - filter_config->wtsyncen = 0; - filter_config->output_32bit = 1; - filter_config->data_ready_flag_by_fifo = 1; - filter_config->enable = 1; - - filter_config->filter_type = sdm_filter_sinc1; - filter_config->pwm_signal_sync = 0; - filter_config->output_offset = 0; - filter_config->oversampling_rate = 32; /**< 1- 256 */ - filter_config->ignore_invalid_samples = 0; -} - -void sdm_get_channel_default_comparator_config(SDM_Type *ptr, sdm_comparator_config_t *cmp_config) -{ - (void) ptr; - cmp_config->high_threshold = 0xffff; - cmp_config->zero_cross_threshold = 0xffff; - cmp_config->low_threshold = 0x0; - - cmp_config->en_zero_cross_threshold_int = false; - cmp_config->en_clock_invalid_int = false; - cmp_config->en_high_threshold_int = false; - cmp_config->en_low_threshold_int = false; - cmp_config->filter_type = sdm_filter_sinc1; - cmp_config->oversampling_rate = 32; /**< 1-32, when 32, write 0 into bitfield */ - cmp_config->ignore_invalid_samples = 0; - cmp_config->enable = true; -} - -void sdm_config_channel_filter(SDM_Type *ptr, uint8_t ch_index, sdm_filter_config_t *filter_config) -{ - /* fifo setting */ - ptr->CH[ch_index].SDFIFOCTRL = SDM_CH_SDFIFOCTRL_THRSH_SET(filter_config->fifo_threshold) - | SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(filter_config->en_fifo_threshold_int); - - ptr->CH[ch_index].SDCTRLE = SDM_CH_SDCTRLE_SGD_ORDR_SET(filter_config->filter_type) - | SDM_CH_SDCTRLE_PWMSYNC_SET(filter_config->pwm_signal_sync) - | SDM_CH_SDCTRLE_CIC_SCL_SET(filter_config->output_offset) - | SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(filter_config->oversampling_rate) - | SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(filter_config->ignore_invalid_samples); - - ptr->CH[ch_index].SDCTRLP = SDM_CH_SDCTRLP_MANCH_THR_SET(filter_config->manchester_threshold) - | SDM_CH_SDCTRLP_WDOG_THR_SET(filter_config->wdg_threshold) - | SDM_CH_SDCTRLP_AF_IE_SET(filter_config->en_af_int) - | SDM_CH_SDCTRLP_DFFOVIE_SET(filter_config->en_data_overflow_int) - | SDM_CH_SDCTRLP_DSATIE_SET(filter_config->en_cic_data_saturation_int) - | SDM_CH_SDCTRLP_DRIE_SET(filter_config->en_data_ready_int) - | SDM_CH_SDCTRLP_SYNCSEL_SET(filter_config->sync_source) - | SDM_CH_SDCTRLP_FFSYNCCLREN_SET(filter_config->fifo_clean_on_sync) - | SDM_CH_SDCTRLP_WTSYNACLR_SET(filter_config->wtsynaclr) - | SDM_CH_SDCTRLP_WTSYNMCLR_SET(filter_config->wtsynmclr) - | SDM_CH_SDCTRLP_WTSYNCEN_SET(filter_config->wtsyncen) - | SDM_CH_SDCTRLP_D32_SET(filter_config->output_32bit) - | SDM_CH_SDCTRLP_DR_OPT_SET(filter_config->data_ready_flag_by_fifo); - - ptr->CH[ch_index].SDCTRLP |= SDM_CH_SDCTRLP_EN_SET(filter_config->enable); -} - -void sdm_config_channel_comparator(SDM_Type *ptr, uint8_t ch_index, sdm_comparator_config_t *cmp_config) -{ - ptr->CH[ch_index].SCHTL = cmp_config->high_threshold; - ptr->CH[ch_index].SCLLT = cmp_config->low_threshold; - ptr->CH[ch_index].SCHTLZ = cmp_config->zero_cross_threshold; - - ptr->CH[ch_index].SCCTRL = SDM_CH_SCCTRL_HZ_EN_SET(cmp_config->en_zero_cross_threshold_int) - | SDM_CH_SCCTRL_MF_IE_SET(cmp_config->en_clock_invalid_int) - | SDM_CH_SCCTRL_HL_IE_SET(cmp_config->en_high_threshold_int) - | SDM_CH_SCCTRL_LL_IE_SET(cmp_config->en_low_threshold_int) - | SDM_CH_SCCTRL_SGD_ORDR_SET(cmp_config->filter_type) - | SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(cmp_config->oversampling_rate) - | SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(cmp_config->ignore_invalid_samples); - - ptr->CH[ch_index].SCCTRL |= SDM_CH_SCCTRL_EN_SET(cmp_config->enable); -} - -hpm_stat_t sdm_receive_one_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint8_t data_len_in_bytes) -{ - uint32_t retry = 0; - int32_t output; - - while (!sdm_get_channel_data_ready_status(ptr, ch_index)) { - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_LIN_DRV_RETRY_COUNT) { - return status_timeout; - } - - if (using_fifo) { - output = ptr->CH[ch_index].SDFIFO; - } else { - output = ptr->CH[ch_index].SDATA; - } - - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - *(data++) = (int8_t)(output >> (i * 8)); - } - - return status_success; -} - -hpm_stat_t sdm_receive_filter_data(SDM_Type *ptr, uint8_t ch_index, bool using_fifo, int8_t *data, uint32_t count, uint8_t data_len_in_bytes) -{ - for (uint32_t i = 0; i < count; i++) { - if (status_success != sdm_receive_one_filter_data(ptr, ch_index, using_fifo, data, data_len_in_bytes)) { - return status_fail; - } - - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - data++; - } - } - return status_success; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c deleted file mode 100644 index ad531c8ef98..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdp_drv.c +++ /dev/null @@ -1,1081 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_sdp_drv.h" -#include "hpm_soc_feature.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * AES Key source definition - */ -#define AES_KEY_SRC_SDP_START_IDX 0U -#define AES128_KEY_SRC_SDP_END_IDX 0xFU -#define AES256_KEY_SRC_SDP_END_IDX 0x7U -#define AES_KEY_SRC_KEYMAN_START_IDX 0x20U -#define AES128_KEY_SRC_KEYMAN_END_IDX 0x2FU -#define AES256_KEY_SRC_KEYMAN_END_IDX 0x2FU -#define AES_KEY_SRC_UNIQUE_KEY_START_IDX 0x3EU -#define AES_KEY_SRC_OTP_KEY_START_IDX 0x3FU - -#define AES_256_KEY_SIZE_IN_WORDS (8U) -#define AES_256_KEY_SIZE_IN_BYTES (32U) - -#define CRC32_DIGEST_SIZE_IN_BYTES (4U) -#define SHA1_DIGEST_SIZE_IN_BYTES (20U) -#define SHA256_DIGEST_SIZE_IN_BYTES (32U) - -#define AES_CTR_BLOCK_UNIT (16U) - -typedef enum { - sdp_state_hash_init, sdp_state_hash_update, -} sdp_hash_alg_state_t; - -#define AES_BLOCK_SIZE (16U) -#define HASH_BLOCK_SIZE (64U) -#define HASH_DIGEST_SIZE_MAX (32) - -#define SDP_CRYPTO_ALG_IDX_AES128 (0U) -#define SDP_CRYPTO_ALG_IDX_AES256 (1U) -#define SDP_CRYPTO_ALG_IDX_SM4 (8U) - -typedef struct { - union { - uint32_t words[HASH_BLOCK_SIZE / sizeof(uint32_t)]; - uint8_t bytes[HASH_BLOCK_SIZE]; - } block; - uint32_t blk_size; - uint32_t full_msg_size; - uint32_t running_hash[HASH_DIGEST_SIZE_MAX / sizeof(uint32_t)]; - sdp_hash_alg_t alg; - sdp_hash_alg_state_t state; - bool hash_init; - bool hash_finish; -} sdp_hash_internal_ctx_t; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx); - -static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size); - -static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size); - -static hpm_stat_t sdp_hash_finalize(SDP_Type *base, sdp_hash_ctx_t *hash_ctx); - -static inline void sdp_clear_error_status(SDP_Type *base) -{ - base->STA = 0xFFFFFFFFUL; -} - -static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes); - -static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num); - -static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t input_len, - const uint8_t *iv, - uint32_t iv_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *mac, - uint32_t mac_len); - -static void aes_ccm_format_b0(uint8_t *block, - const uint8_t *iv, - uint32_t iv_len, - uint32_t mac_len, - uint32_t aad_len, - uint32_t input_len); - -static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len); - -static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len); - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -hpm_stat_t sdp_wait_done(SDP_Type *base) -{ - hpm_stat_t status; - uint32_t sdp_sta; - do { - sdp_sta = base->STA; - if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSET_MASK)) { - status = status_sdp_error_setup; - } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRPKT_MASK)) { - status = status_sdp_error_packet; - } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRSRC_MASK)) { - status = status_sdp_error_src; - } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRDST_MASK)) { - status = status_sdp_error_dst; - } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRHAS_MASK)) { - status = status_sdp_error_hash; - } else if (IS_HPM_BITMASK_SET(sdp_sta, SDP_STA_ERRCHAIN_MASK)) { - status = status_sdp_error_chain; - } else { - status = status_success; - } - } while (IS_HPM_BITMASK_CLR(sdp_sta, SDP_STA_PKTCNT0_MASK)); - - return status; -} - -hpm_stat_t sdp_init(SDP_Type *base) -{ - hpm_stat_t status = status_invalid_argument; - if (base != NULL) { - base->SDPCR &= ~(SDP_SDPCR_CLKGAT_MASK | SDP_SDPCR_SFTRST_MASK); - - status = status_success; - } - - return status; -} - -hpm_stat_t sdp_deinit(SDP_Type *base) -{ - hpm_stat_t status = status_invalid_argument; - if (base != NULL) { - base->SDPCR |= SDP_SDPCR_CLKGAT_MASK; - status = status_success; - } - return status; -} - -hpm_stat_t sdp_aes_set_key(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx) -{ - union { - uint32_t words[AES_256_KEY_SIZE_IN_WORDS]; - uint8_t bytes[AES_256_KEY_SIZE_IN_BYTES]; - } aes_key; - - assert((base != NULL) && (aes_ctx != NULL) && (key_bits <= sdp_aes_keybits_256)); - - hpm_stat_t status = status_invalid_argument; - do { - aes_ctx->crypto_algo = sdp_crypto_alg_aes; - - if (IS_HPM_BITMASK_SET(base->SDPCR, SDP_SDPCR_CIPDIS_MASK)) { - status = status_sdp_no_crypto_support; - break; - } - - HPM_BREAK_IF((key_bits != sdp_aes_keybits_128) && (key_bits != sdp_aes_keybits_256)); - - aes_ctx->key_bits = key_bits; - - uint32_t key128_idx = key_idx; - if (key_bits == sdp_aes_keybits_256) { - if (key_idx <= AES256_KEY_SRC_SDP_END_IDX) { - (void) memcpy(aes_key.bytes, key, 32); - key128_idx = key_idx * 2U; - uint32_t idx = 0; - for (uint32_t i = 0; i < 2; i++) { - base->KEYADDR = SDP_KEYADDR_INDEX_SET(key128_idx + i); - for (uint32_t j = 0; j < 4; j++) { - base->KEYDAT = aes_key.words[idx++]; - } - } - } else if ((key_idx >= AES_KEY_SRC_KEYMAN_START_IDX) && (key_idx <= AES256_KEY_SRC_KEYMAN_END_IDX)) { - key128_idx = (key_idx - AES_KEY_SRC_KEYMAN_START_IDX) * 2U + AES_KEY_SRC_KEYMAN_START_IDX; - } - } else { - if (key_idx <= AES128_KEY_SRC_SDP_END_IDX) { - (void) memcpy(aes_key.bytes, key, 16); - base->KEYADDR = SDP_KEYADDR_INDEX_SET(key_idx); - for (uint32_t j = 0; j < 4; j++) { - base->KEYDAT = aes_key.words[j]; - } - } - } - - aes_ctx->key_idx = key128_idx; - aes_ctx->key_bits = key_bits; - status = status_success; - - } while (false); - - return status; -} - -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - -hpm_stat_t sdp_sm4_set_key(SDP_Type *base, - sdp_sm4_ctx_t *sm4_ctx, - const uint8_t *key, - sdp_sm4_key_bits_t key_bits, - uint32_t key_idx) -{ - hpm_stat_t status = status_invalid_argument; - if (key_bits != sdp_sm4_keybits_128) { - return status; - } - status = sdp_aes_set_key(base, sm4_ctx, key, (sdp_aes_key_bits_t) key_bits, key_idx); - if (status != status_success) { - return status; - } - sm4_ctx->crypto_algo = sdp_crypto_alg_sm4; - - return status; -} - -#endif - -hpm_stat_t sdp_aes_crypt_ecb(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - assert((base != NULL) && (aes_ctx != NULL)); - - hpm_stat_t status; - - base->SDPCR = SDP_SDPCR_CIPHEN_MASK; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->SDPCR |= HPM_BITSMASK(1, 8); - base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; - base->PKTSRC = (uint32_t) in; - base->PKTDST = (uint32_t) out; - base->PKTBUF = len; -#else - sdp_pkt_struct_t *pkt_desc = &aes_ctx->sdp_pkt; - pkt_desc->next_cmd = NULL; - pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK; - pkt_desc->src_addr = (uint32_t) in; - pkt_desc->dst_addr = (uint32_t) out; - pkt_desc->buf_size = len; - -#endif - sdp_clear_error_status(base); - - if (aes_ctx->crypto_algo == sdp_crypto_alg_aes) { - if (aes_ctx->key_bits == sdp_aes_keybits_128) { - base->MODCTRL = - SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES128) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | - SDP_MODCTRL_AESDIR_SET(op); - } else { - base->MODCTRL = - SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES256) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | - SDP_MODCTRL_AESDIR_SET(op); - } - } -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - else if (aes_ctx->crypto_algo == sdp_crypto_alg_sm4) { - base->MODCTRL = SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_SM4) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | - SDP_MODCTRL_AESDIR_SET(op); - } -#endif - else { - return status_sdp_invalid_alg; - } - -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->CMDPTR = 0; -#else - base->CMDPTR = (uint32_t) pkt_desc; -#endif - base->PKTCNT = 1U; - - status = sdp_wait_done(base); - - return status; -} - -hpm_stat_t sdp_aes_crypt_cbc(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - const uint8_t iv[16], - const uint8_t *input, - uint8_t *output) -{ - assert((base != NULL) && (aes_ctx != NULL)); - assert((op <= sdp_aes_op_decrypt) && (input != NULL) && (output != NULL)); - - hpm_stat_t status; - - base->SDPCR = SDP_SDPCR_CIPHEN_MASK; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->SDPCR |= HPM_BITSMASK(1, 8); - base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKT_CTRL_CIPHIV_MASK; - base->PKTSRC = (uint32_t) input; - base->PKTDST = (uint32_t) output; - base->PKTBUF = length; -#else - sdp_pkt_struct_t *pkt_desc = &aes_ctx->sdp_pkt; - pkt_desc->next_cmd = NULL; - pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKT_CTRL_CIPHIV_MASK; - pkt_desc->src_addr = (uint32_t) input; - pkt_desc->dst_addr = (uint32_t) output; - pkt_desc->buf_size = length; -#endif - - sdp_clear_error_status(base); - - if (aes_ctx->crypto_algo == sdp_crypto_alg_aes) { - if (aes_ctx->key_bits == sdp_aes_keybits_128) { - base->MODCTRL = - SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES128) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | - SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); - } else { - base->MODCTRL = - SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_AES256) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | - SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); - } - } -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - else if (aes_ctx->crypto_algo == sdp_crypto_alg_sm4) { - base->MODCTRL = SDP_MODCTRL_AESALG_SET(SDP_CRYPTO_ALG_IDX_SM4) | SDP_MODCTRL_AESKS_SET(aes_ctx->key_idx) | - SDP_MODCTRL_AESDIR_SET(op) | SDP_MODCTRL_AESMOD_SET(1); - } -#endif - else { - return status_sdp_invalid_alg; - } - - /* Set IV, copy the IV to the context first in case the IV address is not 32-bit aligned */ - uint32_t iv_32[4]; - (void) memcpy(iv_32, iv, 16); - for (uint32_t i = 0; i < 4; i++) { - base->CIPHIV[i] = iv_32[i]; - } - (void) memset(iv_32, 0, sizeof(iv_32)); -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->CMDPTR = 0; -#else - base->CMDPTR = (uint32_t) pkt_desc; -#endif - base->PKTCNT = 1U; - - status = sdp_wait_done(base); - - return status; -} - -/* - * In the AES-CTR algorithm, all the numbers are represented in big-endian format, namely, LSB is in last byte - */ -static void sdp_increment_bn(uint8_t *big_num, uint32_t bytes) -{ - for (uint32_t i = bytes - 1; i > 0u; i--) { - big_num[i]++; - if (big_num[i] != 0) { - break; - } - } -} - -hpm_stat_t sdp_aes_crypt_ctr(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - uint8_t *nonce_counter, - uint8_t *input, - uint8_t *output, - uint32_t length) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF( - (base == NULL) || (aes_ctx == NULL) || (nonce_counter == NULL) || (input == NULL) || (output == NULL)); - - uint32_t calc_len; - uint8_t *cipher_nonce = (uint8_t *) &aes_ctx->buf3; - while (length > 0) { - calc_len = (length < 16U) ? length : 16U; - status = sdp_aes_crypt_ecb(base, aes_ctx, sdp_aes_op_encrypt, 16, nonce_counter, cipher_nonce); - HPM_BREAK_IF(status != status_success); - uint8_t tmp; - for (uint32_t i = 0; i < calc_len; i++) { - tmp = *input++; - *output++ = (uint8_t) (tmp ^ cipher_nonce[i]); - } - - length -= calc_len; - /* Increment counter, (128-bit big-endian */ - sdp_increment_bn(nonce_counter, AES_CTR_BLOCK_UNIT); - } - - } while (false); - - return status; -} - -static void uint32_to_be(uint8_t *dst, uint32_t len, uint32_t num) -{ - uint32_t i = 0; - - (void) memset(dst, 0, len); - - while (num > 0) { - dst[len - 1 - i] = num & 0xFF; - num >>= 8; - i++; - } -} - -/* - * See section A2.1 in NIST Special Publication 800-38C - * q + n = 15 - * n - nonce / iv - * byte0 = FLAG - * bit[2:0] - (q-1) - * bit[5:3] - (t-2/2 - * bit[6] - adata - * bit[7] - reserved - * - * byte (1... 15-q) nonce - * byte (16-q...15) input length - * - */ -static void aes_ccm_format_b0(uint8_t *block, - const uint8_t *iv, - uint32_t iv_len, - uint32_t mac_len, - uint32_t aad_len, - uint32_t input_len) -{ - uint8_t q = 15U - iv_len; - block[0] = 0; - block[0] |= (aad_len > 0) ? (1U << 6) : 0U; - block[0] |= ((mac_len - 2U) / 2U) << 3; - block[0] |= q - 1U; - - (void) memcpy(block + 1U, iv, iv_len); - - uint32_to_be(block + 1U + iv_len, q, input_len); - -} - -/* - * See section A2.3 in NIST Special Publication 800-38C - * q + n = 15 - * n - nonce/iv - * byte 0 = FLAG - * bit[2:0] : (q - 1) - * bit[5:3] : 0 - * bit[7:6] : 0 - * - * byte (1...15-q) nonce - * byte (16-q ...15) i - */ -static void aes_ccm_format_ctr0(uint8_t *ctr, const uint8_t *iv, uint8_t iv_len) -{ - uint8_t q = 15U - iv_len; - (void) memset(ctr, 0, 16); - ctr[0] |= q - 1U; - (void) memcpy(ctr + 1U, iv, iv_len); -} - -static hpm_stat_t aes_ccm_auth_crypt(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t input_len, - const uint8_t *iv, - uint32_t iv_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF((base == NULL) || (aes_ctx == NULL) || (input == NULL) || (output == NULL) || (tag == NULL)); - - - /*See section A.1 in NIST Special Publication 800-38C */ - - /* Valid Tlen is 4, 6, 8, 10, 12, 14, 16 */ - HPM_BREAK_IF((tag_len % 2U != 0U) || (tag_len / 2U < 2) || (tag_len / 2U > 8)); - /* Valid Nonce length is 7, 8, 9, 10, 11, 12, 13 */ - HPM_BREAK_IF((iv_len < 7U) || (iv_len > 13U)); - - /* Note, this API supports maximum 2^32 - 1 bytes of data, so the valid q value should be 2, 3, or 4 */ - uint8_t *b = (uint8_t *) &aes_ctx->buf0; - uint8_t *y = (uint8_t *) &aes_ctx->buf1; - uint8_t *ctr = (uint8_t *) &aes_ctx->buf2; - - /* Format B0 */ - aes_ccm_format_b0(b, iv, iv_len, tag_len, aad_len, input_len); - - /* Calculate Y0 */ - sdp_aes_crypt_ecb(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y); - - - /* - * Follow A2.2.2 in NIST Special Publication 800-38C, only supports up to 2^32 bytes - */ - if (aad_len > 0U) { - uint32_t calc_len = 0U; - const uint8_t *aad_src = aad; - uint32_t remaining_len = aad_len; - (void) memset(b, 0, 16); - /* format B1 - * Follow A2.2.2 in NIST Special Publication 800-38C, only supports up to 2^32 bytes - */ - if (aad_len < ((1UL << 16) - (1U << 8))) { - uint32_to_be(b, 2, aad_len); - calc_len = MIN(remaining_len, 14U); - (void) memcpy(&b[2], aad_src, calc_len); - } else { - b[0] = 0xFFU; - b[1] = 0xFEU; - uint32_to_be(&b[6], 4, calc_len); - calc_len = 10U; - (void) memcpy(&b[2], aad_src, calc_len); - } - aad_src += calc_len; - remaining_len -= calc_len; - /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ - sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); - - while (remaining_len > 0U) { - calc_len = MIN(remaining_len, 16U); - (void) memcpy(b, aad_src, calc_len); - if (calc_len < 16U) { - (void) memset(&b[calc_len], 0, 16U - calc_len); - } - aad_src += calc_len; - remaining_len -= calc_len; - /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ - sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); - } - } - - aes_ccm_format_ctr0(ctr, iv, iv_len); - /* Encryption/Decryption starts from CTR1 */ - sdp_increment_bn(ctr, 16); - /* Continue CBC-MAC calculation + Encryption/Decryption */ - uint32_t remaining_len = input_len; - uint8_t *src = (uint8_t *) input; - uint8_t *dst = output; - while (remaining_len > 0U) { - uint32_t calc_len = MIN(remaining_len, 16U); - if (op == sdp_aes_op_encrypt) { - (void) memcpy(b, src, calc_len); - if (calc_len < 16U) { - (void) memset(&b[calc_len], 0, 16U - calc_len); - } - /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ - sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); - } - sdp_aes_crypt_ctr(base, aes_ctx, ctr, src, dst, calc_len); - if (op == sdp_aes_op_decrypt) { - (void) memcpy(b, dst, calc_len); - if (calc_len < 16U) { - (void) memset(&b[calc_len], 0, 16U - calc_len); - } - /* Calculate Y(i) = CIPHk(B(i) ^ Y(i-1)) */ - sdp_aes_crypt_cbc(base, aes_ctx, sdp_aes_op_encrypt, 16, b, y, y); - } - src += calc_len; - dst += calc_len; - remaining_len -= calc_len; - } - - /* Get CTR0 */ - aes_ccm_format_ctr0(ctr, iv, iv_len); - /* Get MAC */ - sdp_aes_crypt_ctr(base, aes_ctx, ctr, y, b, 16); - /* Copy mac to the destination */ - (void) memcpy(tag, b, tag_len); - - /* Wipe-out temporary data */ - (void) memset(b, 0, 16U); - (void) memset(y, 0, 16); - (void) memset(ctr, 0, 16); - - status = status_success; - - } while (false); - return status; -} - -hpm_stat_t sdp_aes_ccm_generate_encrypt(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *iv, - uint32_t iv_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len) -{ - return aes_ccm_auth_crypt(base, - aes_ctx, - sdp_aes_op_encrypt, - input_len, - iv, - iv_len, - aad, - aad_len, - input, - output, - tag, - tag_len); -} - -static uint8_t sdp_constant_time_cmp(const void *dst, const void *src, uint32_t len) -{ - uint8_t result = 0U; - - const uint8_t *dst_8 = (const uint8_t *) dst; - const uint8_t *src_8 = (const uint8_t *) src; - - while (len-- > 0U) { - result |= *dst_8 ^ *src_8; - ++dst_8; - ++src_8; - - } - return result; -} - -hpm_stat_t sdp_aes_ccm_decrypt_verify(SDP_Type *base, - sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *iv, - uint32_t iv_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len) -{ - hpm_stat_t status; - - do { - - uint32_t calc_mac[4]; - - status = aes_ccm_auth_crypt(base, - aes_ctx, - sdp_aes_op_decrypt, - input_len, - iv, - iv_len, - aad, - aad_len, - input, - output, - (uint8_t *) &calc_mac, - tag_len); - HPM_BREAK_IF(status != status_success); - if (sdp_constant_time_cmp(calc_mac, tag, tag_len) != 0U) { - status = status_sdp_error_invalid_mac; - } else { - status = status_success; - } - - } while (false); - - return status; -} - -hpm_stat_t sdp_hash_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - hpm_stat_t status = status_invalid_argument; - do { - if (IS_HPM_BITMASK_SET(base->SDPCR, SDP_SDPCR_HASDIS_MASK)) { - status = status_sdp_no_hash_support; - break; - } - - /* Initialize the SDP HASH context */ - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; - (void) memset(ctx_internal, 0, sizeof(*ctx_internal)); - ctx_internal->alg = alg; - ctx_internal->blk_size = 0; - ctx_internal->state = sdp_state_hash_init; - ctx_internal->full_msg_size = 0; - - status = status_success; - - } while (false); - - return status; -} - -static void sdp_hash_internal_engine_init(SDP_Type *base, sdp_hash_ctx_t *hash_ctx) -{ - (void) base; - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; - - ctx_internal->hash_init = true; - ctx_internal->hash_finish = false; -} - -static hpm_stat_t sdp_hash_internal_update(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size) -{ - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; - sdp_pkt_struct_t *pkt_desc = (sdp_pkt_struct_t *) &ctx->sdp_pkt; - - pkt_desc->next_cmd = NULL; - uint32_t pkt_ctrl = SDP_PKT_CTRL_DERSEMA_MASK; - if (ctx_internal->hash_init) { - pkt_ctrl |= SDP_PKT_CTRL_HASHINIT_MASK; - ctx_internal->hash_init = false; - } - if (ctx_internal->hash_finish) { - pkt_ctrl |= SDP_PKT_CTRL_HASHFINISH_MASK; - ctx_internal->hash_finish = false; - } - - base->SDPCR = SDP_SDPCR_HASHEN_MASK; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->SDPCR |= HPM_BITSMASK(1, 8); - base->NPKTPTR = 0UL; - base->PKTCTL = pkt_ctrl; - base->PKTSRC = (uint32_t) msg; - base->PKTDST = (uint32_t) 0; - base->PKTBUF = msg_size; -#else - pkt_desc->pkt_ctrl.PKT_CTRL = pkt_ctrl; - pkt_desc->src_addr = (uint32_t) msg; - pkt_desc->dst_addr = 0; - pkt_desc->buf_size = msg_size; - pkt_desc->reserved[0] = 0; - pkt_desc->reserved[1] = 0; - pkt_desc->reserved[2] = 0; -#endif - - sdp_clear_error_status(base); - base->MODCTRL = SDP_MODCTRL_HASALG_SET(ctx_internal->alg); -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->CMDPTR = 0; -#else - base->CMDPTR = (uint32_t) pkt_desc; -#endif - base->PKTCNT = 1; - - hpm_stat_t status = sdp_wait_done(base); - - return status; -} - -static hpm_stat_t sdp_hash_process_message(SDP_Type *base, sdp_hash_ctx_t *ctx, const uint8_t *msg, uint32_t msg_size) -{ - hpm_stat_t status = status_invalid_argument; - - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &ctx->internal; - /* If there is partially filled internal buffer, fill it to full block */ - if (ctx_internal->blk_size > 0U) { - uint32_t size_to_copy = HASH_BLOCK_SIZE - ctx_internal->blk_size; - (void) memcpy(&ctx_internal->block.bytes[ctx_internal->blk_size], msg, size_to_copy); - msg += size_to_copy; - msg_size -= size_to_copy; - - /* process the full internal block */ - status = sdp_hash_internal_update(base, ctx, &ctx_internal->block.bytes[0], HASH_BLOCK_SIZE); - if (status != status_success) { - return status; - } - } - - /* Process all full blocks in message */ - uint32_t full_blk_size = (msg_size >> 6) << 6; - if (full_blk_size > 0U) { - status = sdp_hash_internal_update(base, ctx, msg, full_blk_size); - if (status != status_success) { - return status; - } - msg += full_blk_size; - msg_size -= full_blk_size; - } - - (void) memcpy(&ctx_internal->block.bytes[0], msg, msg_size); - ctx_internal->blk_size = msg_size; - - return status; -} - -hpm_stat_t sdp_hash_update(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - assert((base != NULL) && (hash_ctx != NULL) && (data != NULL)); - hpm_stat_t status = status_invalid_argument; - do { - if (length == 0) { - status = status_success; - break; - } - - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; - uint32_t block_size = HASH_BLOCK_SIZE; - ctx_internal->full_msg_size += length; - /* If the data is still less than HASH_BLOCK_SIZE, keep them only in the buffer */ - if ((ctx_internal->blk_size + length) <= block_size) { - (void) memcpy(&ctx_internal->block.bytes[0] + ctx_internal->blk_size, data, length); - ctx_internal->blk_size += length; - status = status_success; - break; - } else { - if (ctx_internal->state != sdp_state_hash_update) { - sdp_hash_internal_engine_init(base, hash_ctx); - ctx_internal->state = sdp_state_hash_update; - } - } - - /* Process input data */ - status = sdp_hash_process_message(base, hash_ctx, data, length); - } while (false); - - return status; -} - -static hpm_stat_t sdp_hash_finalize(SDP_Type *base, sdp_hash_ctx_t *hash_ctx) -{ - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; - hpm_stat_t status; - ctx_internal->hash_finish = true; - - status = sdp_hash_internal_update(base, hash_ctx, &ctx_internal->block.bytes[0], ctx_internal->blk_size); - - return status; -} - -hpm_stat_t sdp_hash_finish(SDP_Type *base, sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - assert((base != NULL) && (hash_ctx != NULL) && (digest != NULL)); - - hpm_stat_t status = status_invalid_argument; - do { - sdp_hash_internal_ctx_t *ctx_internal = (sdp_hash_internal_ctx_t *) &hash_ctx->internal; - if (ctx_internal->state == sdp_state_hash_init) { - sdp_hash_internal_engine_init(base, hash_ctx); - } - status = sdp_hash_finalize(base, hash_ctx); - HPM_BREAK_IF(status != status_success); - - uint32_t copy_bytes = 0; - uint32_t digest_words = 0; - switch (ctx_internal->alg) { - case sdp_hash_alg_crc32: - copy_bytes = CRC32_DIGEST_SIZE_IN_BYTES; - ctx_internal->running_hash[0] = base->HASWRD[0]; - break; - case sdp_hash_alg_sha1: - copy_bytes = SHA1_DIGEST_SIZE_IN_BYTES; - digest_words = copy_bytes / sizeof(uint32_t); - for (uint32_t i = 0; i < digest_words; i++) { - ctx_internal->running_hash[i] = base->HASWRD[i]; - } - break; - case sdp_hash_alg_sha256: -#if defined(SDP_HAS_SM3_SUPPORT) && (SDP_HAS_SM3_SUPPORT == 1) - case sdp_hash_alg_sm3: -#endif - copy_bytes = SHA256_DIGEST_SIZE_IN_BYTES; - digest_words = copy_bytes / sizeof(uint32_t); - for (uint32_t i = 0; i < digest_words; i++) { - ctx_internal->running_hash[i] = base->HASWRD[i]; - } - break; - default: - /* Never reach here */ - break; - } - (void) memcpy(digest, ctx_internal->running_hash, copy_bytes); - } while (false); - - return status; -} - -hpm_stat_t sdp_memcpy(SDP_Type *base, sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - (void) dma_ctx; - hpm_stat_t status = status_invalid_argument; - - if (length == 0) { - status = status_success; - return status; - } - - base->SDPCR = SDP_SDPCR_MCPEN_MASK; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->SDPCR |= HPM_BITSMASK(1, 8); - base->NPKTPTR = 0; - base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK | SDP_PKTCTL_PKTTAG_SET(1); - base->PKTSRC = (uint32_t) src; - base->PKTDST = (uint32_t) dst; - base->PKTBUF = length; -#else - sdp_pkt_struct_t *pkt_desc = &dma_ctx->sdp_pkt; - pkt_desc->next_cmd = NULL; - pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK; - pkt_desc->src_addr = (uint32_t) src; - pkt_desc->dst_addr = (uint32_t) dst; - pkt_desc->buf_size = length; -#endif - - sdp_clear_error_status(base); - - base->MODCTRL = 0; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->CMDPTR = 0; -#else - base->CMDPTR = (uint32_t) pkt_desc; -#endif - base->PKTCNT = 1; - - status = sdp_wait_done(base); - - return status; -} - -hpm_stat_t sdp_memset(SDP_Type *base, sdp_dma_ctx_t *sdp_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - (void) sdp_ctx; - hpm_stat_t status; - - uint32_t - pattern_32 = (pattern) | ((uint32_t) pattern << 8) | ((uint32_t) pattern << 16) | ((uint32_t) pattern << 24); - - base->SDPCR = SDP_SDPCR_CONFEN_MASK; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->SDPCR |= HPM_BITSMASK(1, 8); - base->PKTCTL = SDP_PKT_CTRL_DERSEMA_MASK; - base->PKTSRC = (uint32_t) pattern_32; - base->PKTDST = (uint32_t) dst; - base->PKTBUF = length; -#else - sdp_pkt_struct_t *pkt_desc = &sdp_ctx->sdp_pkt; - pkt_desc->next_cmd = NULL; - pkt_desc->pkt_ctrl.PKT_CTRL = SDP_PKT_CTRL_DERSEMA_MASK; - pkt_desc->src_addr = pattern_32; - pkt_desc->dst_addr = (uint32_t) dst; - pkt_desc->buf_size = length; -#endif - - sdp_clear_error_status(base); - base->MODCTRL = 0; -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && SDP_REGISTER_DESCRIPTOR_COUNT - base->CMDPTR = 0; -#else - base->CMDPTR = (uint32_t) pkt_desc; -#endif - base->PKTCNT = 1; - - status = sdp_wait_done(base); - - return status; -} - -hpm_stat_t sdp_trigger_action(SDP_Type *base, const sdp_action_t *action, const sdp_pkt_struct_t *cmd_pkt) -{ - hpm_stat_t status = status_invalid_argument; - - do { - if ((action == NULL) || (cmd_pkt == NULL) || (action->op == sdp_op_invalid)) { - break; - } - - bool has_cipher = false; - bool hash_hash = false; - uint32_t sdp_cr = action->op; - uint32_t sdp_mode_ctrl = 0; - switch (action->op) { - case sdp_op_cipher_only: - has_cipher = true; - break; - case sdp_op_hash_only: - hash_hash = true; - break; - case sdp_op_cipher_hash: - has_cipher = true; - hash_hash = true; - break; - case sdp_op_copy_hash: - hash_hash = true; - break; - default: - break; - } - - if (has_cipher) { - sdp_mode_ctrl |= SDP_MODCTRL_AESDIR_SET(action->crypto_op) | SDP_MODCTRL_AESMOD_SET(action->crypto_mode) | - SDP_MODCTRL_AESKS_SET(action->key_index); - uint32_t crypto_alg_idx = SDP_CRYPTO_ALG_IDX_AES128; -#if defined(SDP_HAS_SM4_SUPPORT) && (SDP_HAS_SM4_SUPPORT == 1) - if (action->crypto_alg == sdp_crypto_alg_sm4) { - crypto_alg_idx = SDP_CRYPTO_ALG_IDX_SM4; - } else -#endif - { - if (action->key_bits == 256) { - crypto_alg_idx = SDP_CRYPTO_ALG_IDX_AES256; - } - } - sdp_mode_ctrl |= SDP_MODCTRL_AESALG_SET(crypto_alg_idx); - sdp_mode_ctrl |= SDP_MODCTRL_KEYSWP_SET(action->key_swap_mode); - } - if (hash_hash) { - sdp_mode_ctrl |= SDP_MODCTRL_HASALG_SET(action->hash_alg) | SDP_MODCTRL_HASCHK_SET(action->hash_check); - } - if (has_cipher && hash_hash) { - sdp_mode_ctrl |= SDP_MODCTRL_HASOUT_SET(action->hash_mode); - } - - sdp_mode_ctrl |= SDP_MODCTRL_DINSWP_SET(action->input_swap_mode); - sdp_mode_ctrl |= SDP_MODCTRL_DOUTSWP_SET(action->output_swap_mode); - - base->SDPCR = (base->SDPCR & ~(SDP_SDPCR_CONFEN_MASK | SDP_SDPCR_HASHEN_MASK | SDP_SDPCR_CIPHEN_MASK | - SDP_SDPCR_MCPEN_MASK)) | sdp_cr; - base->MODCTRL = sdp_mode_ctrl; - - sdp_clear_status(HPM_SDP, ~0UL); - base->CMDPTR = (uint32_t) cmd_pkt; - - /* Calculate the count of command packet in the command packet linked list */ - uint32_t pkt_cnt = 0; - sdp_pkt_struct_t *pkt_list = (sdp_pkt_struct_t *) cmd_pkt; - while (pkt_list != NULL) { - if (pkt_list->pkt_ctrl.DCRSEMA != 0) { - ++pkt_cnt; - if (pkt_list->pkt_ctrl.CHAIN != 0) { - pkt_list = pkt_list->next_cmd; - } else { - break; - } - } else { - break; - } - } -#if defined(SDP_REGISTER_DESCRIPTOR_COUNT) && (SDP_REGISTER_DESCRIPTOR_COUNT == 1) - if (pkt_cnt == 1) { - base->SDPCR |= HPM_BITSMASK(1, 8); - base->CMDPTR = 0; - base->PKTCTL = cmd_pkt->pkt_ctrl.PKT_CTRL; - base->PKTSRC = cmd_pkt->src_addr; - base->PKTDST = cmd_pkt->dst_addr; - base->PKTBUF = cmd_pkt->buf_size; - } -#endif - - base->PKTCNT = pkt_cnt; /* Start Action */ - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c deleted file mode 100644 index 59bec24681a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sdxc_drv.c +++ /dev/null @@ -1,1105 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_sdxc_drv.h" - - -#define SDXC_TMCLK_IN_MHZ (1UL) - -#define SDXC_DMA_MAX_XFER_LEN_26BIT ((1UL << 26) - 4U) -#define SDXC_DMA_MAX_XFER_LEN_16BIT ((1UL << 16) - 4U) - -#define SDXC_SYS_DMA_ALIGN_LEN (4U) - -enum { - sdxc_cmd_only = (1UL << 0), - sdxc_cmd_and_tx_data = (1UL << 1), - sdxc_cmd_and_rx_data = (1UL << 2), - sdxc_data_with_auto_cmd12 = (1UL << 3), - sdxc_data_with_auto_cmd23 = (1UL << 4), - sdxc_boot_data = (1UL << 5), - sdxc_boot_data_continuous = (1UL << 6), -}; - -static const uint32_t s_sdxc_boot_dummy = 0; - - -static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, - uint32_t xfer_flags, - uint32_t block_size, - uint32_t block_cnt, - uint32_t *new_flags); - -static void sdxc_read_data_buf(SDXC_Type *base, uint32_t *data, uint32_t num_of_words); - -static hpm_stat_t sdxc_read_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data); - -static void sdxc_write_data_buf(SDXC_Type *base, const uint32_t *data, uint32_t num_of_words); - -static hpm_stat_t sdxc_write_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data); - -static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data, bool enable_dma); - -static hpm_stat_t sdxc_tuning_error_recovery(SDXC_Type *base); - -static bool sdxc_is_bus_idle(SDXC_Type *base); - -static hpm_stat_t sdxc_set_transfer_config(SDXC_Type *base, - uint32_t xfer_flags, - uint32_t block_size, - uint32_t block_cnt, - uint32_t *new_flags) -{ - uint32_t flags = base->CMD_XFER & ~(SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | - SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK | - SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | - SDXC_CMD_XFER_DMA_ENABLE_MASK); - if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK)) { - return status_sdxc_busy; - } else { - if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_boot_data_continuous)) { - - base->PROT_CTRL &= ~SDXC_PROT_CTRL_STOP_BG_REQ_MASK; - base->PROT_CTRL |= SDXC_PROT_CTRL_CONTINUE_REQ_MASK; - return status_success; - } - - if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_DAT_INHIBIT_MASK)) { - return status_sdxc_busy; - } - - if (block_cnt > SDXC_BLK_ATTR_BLOCK_CNT_GET(SDXC_BLK_ATTR_BLOCK_CNT_MASK)) { - return status_invalid_argument; - } - - if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_cmd_and_rx_data)) { - flags |= SDXC_CMD_XFER_DATA_XFER_DIR_MASK; - } - if (block_cnt > 1U) { - flags |= SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK; - if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_data_with_auto_cmd12)) { - flags |= SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(sdxc_auto_cmd12_enabled); - } - } - - if (IS_HPM_BITMASK_SET(xfer_flags, sdxc_data_with_auto_cmd23)) { - flags |= SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(sdxc_auto_cmd23_enabled); - } - - if (IS_HPM_BITMASK_CLR(xfer_flags, sdxc_boot_data)) { - base->BLK_ATTR = block_size; - base->SDMASA = block_cnt; - } else { - flags |= SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK; - } - } - - *new_flags = flags; - - return status_success; -} - - -hpm_stat_t sdxc_receive_cmd_response(SDXC_Type *base, sdxc_command_t *cmd) -{ - hpm_stat_t status = status_success; - - if (cmd->resp_type != sdxc_dev_resp_none) { - - cmd->response[0] = base->RESP[0]; - if (cmd->resp_type == sdxc_dev_resp_r2) { - - /* R3-R2-R1-R0 (lowest 8 bits are invalid bits) has the same format as R2 format in SD spec - * after removing internal CRC7 and end bit - */ - uint32_t resp0 = base->RESP[0]; - uint32_t resp1 = base->RESP[1]; - uint32_t resp2 = base->RESP[2]; - uint32_t resp3 = base->RESP[3]; - cmd->response[0] = (resp0 << 8); - cmd->response[1] = (resp1 << 8) | (resp0 >> 24); - cmd->response[2] = (resp2 << 8) | (resp1 >> 24); - cmd->response[3] = (resp3 << 8) | (resp2 >> 24); - } - - if (SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(base->CMD_XFER) == sdxc_auto_cmd12_enabled) { - cmd->auto_cmd_resp = base->RESP[3]; - } - } - - /* check response flag */ - if ((cmd->resp_error_flags != 0U) && - ((cmd->resp_type == sdxc_dev_resp_r1) || (cmd->resp_type == sdxc_dev_resp_r1b) || - (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r5))) { - if ((cmd->resp_error_flags & cmd->response[0]) != 0U) { - status = status_sdxc_send_cmd_failed; - } - } - - return status; -} - -static void sdxc_read_data_buf(SDXC_Type *base, uint32_t *data, uint32_t num_of_words) -{ - if (sdxc_is_data_buf_readable(base)) { - for (uint32_t i = 0; i < num_of_words; i++) { - data[i] = sdxc_read_data(base); - } - } -} - -static hpm_stat_t sdxc_read_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data) -{ - uint32_t interrupt_status = 0; - hpm_stat_t status = status_success; - do { - /* For multi-block transfer, the block size must be 4-byte aligned */ - if ((data->block_cnt > 1) && (data->block_size % sizeof(uint32_t) != 0)) { - status = status_invalid_argument; - break; - } - if (data->block_size % sizeof(uint32_t) != 0U) { - data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); - } - - uint32_t words_per_block = data->block_size / sizeof(uint32_t); - uint32_t remaining_blocks = data->block_cnt; - uint32_t *read_buf = data->rx_data; - while (remaining_blocks > 0) { - uint32_t status_flags = SDXC_INT_STAT_BUF_RD_READY_MASK | SDXC_STS_DATA_ERR; - /* Wait until data is ready or timeout event occurs */ - do { - interrupt_status = sdxc_get_interrupt_status(base); - } while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)); - - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_CRC_ERR_MASK)) { - /* Handle Data CRC error */ - if (!data->enable_ignore_error) { - status = status_sdxc_data_crc_error; - break; - } - sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { - /* Handle Data timeout error */ - status = status_sdxc_data_timeout_error; - break; - } else { - /* Receive data block by block */ - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); - sdxc_read_data_buf(base, read_buf, words_per_block); - read_buf += words_per_block; - remaining_blocks--; - } - } - - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK); - - } while (false); - - return status; -} - -static void sdxc_write_data_buf(SDXC_Type *base, const uint32_t *data, uint32_t num_of_words) -{ - if (sdxc_is_data_buf_writable(base)) { - for (uint32_t i = 0; i < num_of_words; i++) { - sdxc_write_data(base, data[i]); - } - } -} - -static hpm_stat_t sdxc_write_via_data_buf_blocking(SDXC_Type *base, sdxc_data_t *data) -{ - uint32_t interrupt_status = 0; - hpm_stat_t status = status_success; - do { - /* For multi-block transfer, the block size must be 4-byte aligned */ - if ((data->block_cnt > 1) && (data->block_size % sizeof(uint32_t) != 0)) { - status = status_invalid_argument; - break; - } - if (data->block_size % sizeof(uint32_t) != 0U) { - data->block_size += sizeof(uint32_t) - (data->block_size % sizeof(uint32_t)); - } - - uint32_t words_per_block = data->block_size / sizeof(uint32_t); - uint32_t remaining_blocks = data->block_cnt; - const uint32_t *write_buf = data->tx_data; - while (remaining_blocks > 0) { - uint32_t status_flags = SDXC_INT_STAT_BUF_WR_READY_MASK | SDXC_STS_DATA_ERR; - /* Wait until write data is allowed or timeout event occurs */ - do { - interrupt_status = sdxc_get_interrupt_status(base); - } while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)); - - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_CRC_ERR_MASK)) { - /* Handle Data CRC error */ - if (!data->enable_ignore_error) { - status = status_sdxc_data_crc_error; - break; - } - sdxc_clear_interrupt_status(base, SDXC_STS_DATA_ERR); - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { - /* Handle Data timeout error */ - status = status_sdxc_data_timeout_error; - break; - } else { - /* Receive data block by block */ - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_WR_READY_MASK); - sdxc_write_data_buf(base, write_buf, words_per_block); - write_buf += words_per_block; - remaining_blocks--; - } - } - - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_XFER_COMPLETE_MASK); - - } while (false); - - return status; -} - -static bool sdxc_is_bus_idle(SDXC_Type *base) -{ - uint32_t busy_mask = SDXC_PSTATE_CMD_INHIBIT_MASK | SDXC_PSTATE_DAT_INHIBIT_MASK; - - return IS_HPM_BITMASK_CLR(base->PSTATE, busy_mask); -} - -hpm_stat_t sdxc_get_capabilities(SDXC_Type *base, sdxc_capabilities_t *capabilities) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF((base == NULL) || (capabilities == NULL)); - - capabilities->capabilities1.U = base->CAPABILITIES1; - capabilities->capabilities2.U = base->CAPABILITIES2; - capabilities->curr_capabilities1.U = base->CURR_CAPABILITIES1; - capabilities->curr_capabilities2.U = base->CURR_CAPABILITIES2; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t sdxc_send_command(SDXC_Type *base, sdxc_command_t *cmd) -{ - sdxc_clear_interrupt_status(base, ~0U); - - uint32_t cmd_xfer = SDXC_CMD_XFER_CMD_INDEX_SET(cmd->cmd_index); - uint32_t flags = cmd->cmd_flags; - - /* Wait a while until the BUS is idle after the previous command */ - uint32_t wait_cnt = 100L; - while (!sdxc_is_bus_idle(base) && (wait_cnt > 0U)) { - wait_cnt--; - } - - if (wait_cnt == 0) { - return status_timeout; - } - - if (cmd->cmd_type != sdxc_cmd_type_empty) { - flags &= ~SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK; - uint32_t cmd_check_flags = SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK; - if ((cmd->resp_type == sdxc_dev_resp_r1) || (cmd->resp_type == sdxc_dev_resp_r5) || - (cmd->resp_type == sdxc_dev_resp_r6) || (cmd->resp_type == sdxc_dev_resp_r7)) { - flags |= SDXC_CMD_RESP_LEN_48 | cmd_check_flags; - } else if ((cmd->resp_type == sdxc_dev_resp_r1b) || (cmd->resp_type == sdxc_dev_resp_r5b)) { - flags |= SDXC_CMD_RESP_LEN_48B | cmd_check_flags; - } else if (cmd->resp_type == sdxc_dev_resp_r2) { - flags |= SDXC_CMD_RESP_LEN_136 | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK; - } else if ((cmd->resp_type == sdxc_dev_resp_r3) || (cmd->resp_type == sdxc_dev_resp_r4)) { - flags |= SDXC_CMD_RESP_LEN_48; - } else { - /* do nothing */ - } - if (IS_HPM_BITMASK_SET(flags, SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK)) { - flags |= SDXC_CMD_XFER_RESP_INT_DISABLE_MASK; - } - } - - switch (cmd->cmd_type) { - case sdxc_cmd_type_abort_cmd: - flags |= SDXC_CMD_TYPE_ABORT; - break; - case sdxc_cmd_type_suspend_cmd: - flags |= SDXC_CMD_TYPE_SUSPEND; - break; - case sdxc_cmd_tye_resume_cmd: - flags |= SDXC_CMD_TYPE_RESUME; - break; - default: - flags |= SDXC_CMD_TYPE_NORMAL; - break; - } - - cmd_xfer |= ((flags & (SDXC_CMD_XFER_CMD_TYPE_MASK | SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK | - SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK | SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK | - SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK | - SDXC_CMD_XFER_DATA_XFER_DIR_MASK | SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK | - SDXC_CMD_XFER_MULTI_BLK_SEL_MASK | SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK | - SDXC_CMD_XFER_RESP_TYPE_MASK | SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK))); - - base->CMD_ARG = cmd->cmd_argument; - base->CMD_XFER = cmd_xfer; - - return status_success; -} - - -hpm_stat_t sdxc_parse_interrupt_status(SDXC_Type *base) -{ - uint32_t interrupt_status = sdxc_get_interrupt_status(base); - hpm_stat_t status = status_success; - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_ERROR)) { - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_TOUT_ERR_MASK)) { - status = status_sdxc_cmd_timeout_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_CRC_ERR_MASK)) { - status = status_sdxc_cmd_crc_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_END_BIT_ERR_MASK)) { - status = status_sdxc_cmd_end_bit_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_IDX_ERR_MASK)) { - status = status_sdxc_cmd_index_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { - status = status_sdxc_data_timeout_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_CRC_ERR_MASK)) { - status = status_sdxc_data_crc_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_END_BIT_ERR_MASK)) { - status = status_sdxc_data_end_bit_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_AUTO_CMD_ERR_MASK)) { - uint32_t auto_cmd_err_mask = base->AC_HOST_CTRL & 0xFFFFUL; - if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK)) { - status = status_sdxc_autocmd_cmd12_not_exec; - } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK)) { - status = status_sdxc_autocmd_cmd_timeout_error; - } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK)) { - status = status_sdxc_autocmd_cmd_crc_error; - } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK)) { - status = status_sdxc_autocmd_cmd_index_error; - } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK)) { - status = status_sdxc_autocmd_end_bit_error; - } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK)) { - status = status_sdxc_autocmd_cmd_response_error; - } else if (IS_HPM_BITMASK_SET(auto_cmd_err_mask, SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK)) { - status = status_sdxc_autocmd_cmd_not_issued_auto_cmd12; - } else { - status = status_sdxc_auto_cmd_error; - } - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_ADMA_ERR_MASK)) { - status = status_sdxc_adma_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { - status = status_sdxc_tuning_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_RESP_ERR_MASK)) { - status = status_sdxc_response_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_BOOT_ACK_ERR_MASK)) { - status = status_sdxc_boot_ack_error; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CARD_REMOVAL_MASK)) { - status = status_sdxc_card_removed; - } else { - status = status_sdxc_error; - } - } else { - status = status_success; - } - return status; -} - -hpm_stat_t sdxc_wait_cmd_done(SDXC_Type *base, sdxc_command_t *cmd, bool polling_cmd_done) -{ - hpm_stat_t status = status_success; - uint32_t interrupt_status = 0U; - - if (polling_cmd_done) { - while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK)) { - interrupt_status = sdxc_get_interrupt_status(base); - if ((interrupt_status & SDXC_STS_CMD_ERR) != 0) { - status = sdxc_parse_interrupt_status(base); - HPM_BREAK_IF(status != status_success); - } - } - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_CMD_COMPLETE_MASK); - - if (status == status_success) { - status = sdxc_receive_cmd_response(base, cmd); - } - } - - return status; -} - - -static hpm_stat_t sdxc_transfer_data_blocking(SDXC_Type *base, sdxc_data_t *data, bool enable_dma) -{ - hpm_stat_t status = status_success; - - uint32_t interrupt_status = 0; - - if (enable_dma) { - uint32_t status_flags = SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_STS_ERROR; - while (!IS_HPM_BITMASK_SET(interrupt_status, status_flags)) { - interrupt_status = sdxc_get_interrupt_status(base); - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DMA_INTERRUPT_MASK)) { - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_DMA_INTERRUPT_MASK); - if (SDXC_PROT_CTRL_DMA_SEL_GET(base->PROT_CTRL) == (uint32_t) sdxc_dmasel_sdma) { - base->ADMA_SYS_ADDR += data->block_size; - } - } - } - - if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_TUNING_ERR_MASK)) { - status = status_sdxc_transfer_data_failed; - } else if (IS_HPM_BITMASK_SET(interrupt_status, SDXC_STS_DATA_ERR | SDXC_INT_STAT_ADMA_ERR_MASK)) { - if ((!data->enable_ignore_error) || - IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_DATA_TOUT_ERR_MASK)) { - status = status_sdxc_transfer_data_failed; - } - } else { - /* Do nothing */ - } - - if ((data->data_type == (uint8_t) sdxc_xfer_data_boot_continuous) && (status == status_success)) { - *(data->rx_data) = s_sdxc_boot_dummy; - } - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_DMA_INTERRUPT_MASK | SDXC_INT_STAT_TUNING_ERR_MASK); - - } else { - if (data->rx_data != NULL) { - status = sdxc_read_via_data_buf_blocking(base, data); - if (status != status_success) { - return status; - } - } else { - status = sdxc_write_via_data_buf_blocking(base, data); - if (status != status_success) { - return status; - } - } - } - - return status; -} - - -void sdxc_init(SDXC_Type *base, const sdxc_config_t *config) -{ - sdxc_reset(base, sdxc_reset_all, 0x10000U); - - uint32_t prot_ctrl = base->PROT_CTRL; - - prot_ctrl &= ~(SDXC_PROT_CTRL_DMA_SEL_MASK | SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK); - - prot_ctrl |= SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK; - - sdxc_enable_tm_clock(base); - sdxc_set_data_timeout(base, config->data_timeout, NULL); - - base->PROT_CTRL = prot_ctrl; - - /* Enable SD internal clock and the output clock */ - base->SYS_CTRL |= SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK; - while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)) { - - } - base->SYS_CTRL |= SDXC_SYS_CTRL_PLL_ENABLE_MASK; - while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK)) { - - } - - base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; - - base->INT_STAT_EN = SDXC_STS_ALL_FLAGS; - base->INT_SIGNAL_EN = 0UL; - base->INT_STAT = SDXC_STS_ALL_FLAGS; - - /* Set Host to version 4, enable 26-bit ADMA2 length mode */ - base->AC_HOST_CTRL &= ~(SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK | SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK); - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK | SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK; -} - -void sdxc_set_data_timeout(SDXC_Type *base, uint32_t timeout_in_ms, uint32_t *actual_timeout_ms) -{ - uint32_t field_value = 0xE; - /* - * Timeout calculation logic: - * the base timeout tick is (1UL << 13), - * assuming TMCLK is 24MHz, then the timeout_in_us = (1UL << 13) / 24 - */ - uint32_t timeout_in_us_unit = (1UL << 13U) / SDXC_TMCLK_IN_MHZ; - uint32_t timeout_in_us = timeout_in_ms * 1000UL; - for (uint32_t i = 0; i < 0xFU; i++) { - uint32_t timeout_us_using_value_i = (timeout_in_us_unit << i); - if (timeout_in_us < timeout_us_using_value_i) { - field_value = i; - break; - } - } - sdxc_enable_interrupt_status(base, SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK, false); - base->SYS_CTRL = (base->SYS_CTRL & ~SDXC_SYS_CTRL_TOUT_CNT_MASK) | SDXC_SYS_CTRL_TOUT_CNT_SET(field_value); - sdxc_enable_interrupt_status(base, SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK, true); - - if (actual_timeout_ms != NULL) { - *actual_timeout_ms = (timeout_in_us_unit << field_value) / 1000UL; - } -} - -void sdxc_set_mmc_boot_config(SDXC_Type *base, const sdxc_boot_config_t *config) -{ - uint32_t emmc_boot_reg = base->EMMC_BOOT_CTRL; - - emmc_boot_reg &= ~(SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK | SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK); - - if (config->enable_boot_ack) { - emmc_boot_reg |= SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK; - } - - /* TODO: Auto stop at block gap, how to handle this? */ - - uint32_t block_attr_reg = base->BLK_ATTR & ~(SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK | SDXC_BLK_ATTR_BLOCK_CNT_MASK); - - block_attr_reg |= - SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(config->block_size) | SDXC_BLK_ATTR_BLOCK_CNT_SET(config->block_cnt); - - base->BLK_ATTR = block_attr_reg; - base->EMMC_BOOT_CTRL = emmc_boot_reg; -} - -void sdxc_set_data_config(SDXC_Type *base, sdxc_xfer_direction_t data_dir, uint32_t block_cnt, uint32_t block_size) -{ - uint32_t block_attr_reg = base->BLK_ATTR & ~(SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK | SDXC_BLK_ATTR_BLOCK_CNT_MASK); - - block_attr_reg |= SDXC_BLK_ATTR_BLOCK_CNT_SET(block_cnt) | SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(block_size); - - base->BLK_ATTR = block_attr_reg; - - if (data_dir == sdxc_xfer_dir_write) { - base->CMD_XFER &= ~SDXC_CMD_XFER_DATA_XFER_DIR_MASK; - } else { - base->CMD_XFER |= SDXC_CMD_XFER_DATA_XFER_DIR_MASK; - } -} - -hpm_stat_t sdxc_set_dma_config(SDXC_Type *base, - sdxc_adma_config_t *dma_cfg, - const uint32_t *data_addr, - bool enable_auto_cmd23) -{ - (void) enable_auto_cmd23; - if (dma_cfg->dma_type == sdxc_dmasel_sdma) { - - if (((uint32_t) data_addr % SDXC_SYS_DMA_ALIGN_LEN) != 0U) { - return status_sdxc_dma_addr_unaligned; - } - - base->ADMA_SYS_ADDR = (uint32_t) data_addr; - } else { - base->ADMA_SYS_ADDR = (uint32_t) dma_cfg->adma_table; - } - - /* Set DMA mode */ - uint32_t sys_ctl = base->SYS_CTRL; - base->PROT_CTRL = (base->PROT_CTRL & ~SDXC_PROT_CTRL_DMA_SEL_MASK) | SDXC_PROT_CTRL_DMA_SEL_SET(dma_cfg->dma_type); - base->SYS_CTRL = sys_ctl; - return status_success; -} - - -hpm_stat_t sdxc_set_adma2_desc(uint32_t *adma_tbl, - uint32_t adma_table_words, - const uint32_t *data_buf, - uint32_t data_bytes, - uint32_t flags) -{ - hpm_stat_t status = status_invalid_argument; - do { - if ((adma_tbl == NULL) || (data_buf == NULL)) { - break; - } - if ((uint32_t) data_buf % 4U != 0U) { - status = status_sdxc_dma_addr_unaligned; - break; - } - - uint32_t start_idx = 0; - uint32_t min_entries; - uint32_t max_entries = adma_table_words * sizeof(uint32_t) / sizeof(sdxc_adma2_descriptor_t); - sdxc_adma2_descriptor_t *adma2_desc = (sdxc_adma2_descriptor_t *) adma_tbl; - - /* Ensure that the data_bytes is 4-byte aligned. */ - data_bytes += (data_bytes % sizeof(uint32_t)); - - min_entries = data_bytes / SDXC_DMA_MAX_XFER_LEN_26BIT; - if (data_bytes % SDXC_DMA_MAX_XFER_LEN_26BIT != 0U) { - min_entries += 1U; - } - - uint32_t i; - if (flags == (uint32_t) sdxc_adma_desc_multi_flag) { - - for (i = 0; i < max_entries; i++) { - if (adma2_desc[i].valid == 0U) { - break; - } - } - - start_idx = i; - - /* add one entry as dummy entry */ - min_entries += 1U; - } - - if ((min_entries + start_idx) > max_entries) { - return status_invalid_argument; - } - - uint32_t dma_buf_len = 0U; - const uint32_t *data = data_buf; - for (i = start_idx; i < (min_entries + start_idx); i++) { - if (data_bytes > SDXC_DMA_MAX_XFER_LEN_26BIT) { - dma_buf_len = SDXC_DMA_MAX_XFER_LEN_26BIT; - } else { - dma_buf_len = (data_bytes == 0U) ? sizeof(uint32_t) : data_bytes; - } - - /* Format each adma2 descriptor entry */ - adma2_desc[i].addr = (data_bytes == 0U) ? &s_sdxc_boot_dummy : data; - adma2_desc[i].len_attr = 0U; - adma2_desc[i].len_lower = dma_buf_len & 0xFFFFU; - adma2_desc[i].len_upper = dma_buf_len >> 16; - adma2_desc[i].len_attr |= SDXC_ADMA2_DESC_VALID_FLAG; - if (data_bytes != 0U) { - adma2_desc[i].act = SDXC_ADMA2_DESC_TYPE_TRANS; - } - - data = (uint32_t *) ((uint32_t) data + dma_buf_len); - if (data_bytes != 0U) { - data_bytes -= dma_buf_len; - } - } - - if (flags == (uint32_t) sdxc_adma_desc_multi_flag) { - adma2_desc[i + 1U].len_attr |= SDXC_ADMA2_DESC_TYPE_TRANS; - } else { - adma2_desc[i - 1U].len_attr |= SDXC_ADMA2_DESC_END_FLAG; - } - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t sdxc_set_adma_table_config(SDXC_Type *base, - sdxc_adma_config_t *dma_cfg, - sdxc_data_t *data_cfg, - uint32_t flags) -{ - hpm_stat_t status = status_fail; - - uint32_t boot_dummy_offset = (data_cfg->data_type == (uint8_t) sdxc_xfer_data_boot_continuous) ? sizeof(uint32_t) - : 0; - const uint32_t *data; - - if (data_cfg->rx_data == NULL) { - data = (const uint32_t *) data_cfg->tx_data; - } else { - data = (const uint32_t *) data_cfg->rx_data; - } - if (boot_dummy_offset > 0) { - data++; - } - - uint32_t block_size = data_cfg->block_size * data_cfg->block_cnt - boot_dummy_offset; - - if (dma_cfg->dma_type == sdxc_dmasel_sdma) { - status = status_success; - } else if (dma_cfg->dma_type == sdxc_dmasel_adma2) { - status = sdxc_set_adma2_desc(dma_cfg->adma_table, dma_cfg->adma_table_words, data, block_size, flags); - - } else if (dma_cfg->dma_type == sdxc_dmasel_adma2_or_3) { - /* TODO: To be implemented */ - - } else { - status = status_invalid_argument; - } - - if ((status == status_success) && (data_cfg->data_type != (uint8_t) sdxc_xfer_data_boot_continuous)) { - status = sdxc_set_dma_config(base, dma_cfg, data, data_cfg->enable_auto_cmd23); - } - - return status; -} - -bool sdxc_reset(SDXC_Type *base, sdxc_sw_reset_type_t reset_type, uint32_t timeout) -{ - uint32_t reset_mask = 0U; - - switch (reset_type) { - case sdxc_reset_all: - reset_mask = SDXC_SYS_CTRL_SW_RST_ALL_MASK; - break; - case sdxc_reset_cmd_line: - reset_mask = SDXC_SYS_CTRL_SW_RST_CMD_MASK; - break; - case sdxc_reset_data_line: - reset_mask = SDXC_SYS_CTRL_SW_RST_DAT_MASK; - break; - default: - /* Do nothing */ - break; - } - base->SYS_CTRL |= reset_mask; - while (IS_HPM_BITMASK_SET(base->SYS_CTRL, reset_mask)) { - if (timeout == 0U) { - return false; - } - timeout--; - } - - return true; -} - -void sdxc_select_voltage(SDXC_Type *base, sdxc_bus_voltage_option_t option) -{ - uint32_t option_u32 = (uint32_t) option; - - base->PROT_CTRL = - (base->PROT_CTRL & ~SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) | SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(option_u32); - - if (option == sdxc_bus_voltage_sd_1v8) { - base->AC_HOST_CTRL |= SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; - } else { - base->AC_HOST_CTRL &= ~SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK; - } -} - -void sdxc_enable_wakeup_event(SDXC_Type *base, sdxc_wakeup_event_t evt, bool enable) -{ - uint32_t evt_u32 = (uint32_t) evt; - - if (enable) { - base->PROT_CTRL |= evt_u32; - } else { - base->PROT_CTRL &= ~evt_u32; - } -} - -void sdxc_set_data_bus_width(SDXC_Type *base, sdxc_bus_width_t width) -{ - uint32_t host_ctrl = base->PROT_CTRL & ~(SDXC_PROT_CTRL_EXT_DAT_XFER_MASK | SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK); - - if (width == sdxc_bus_width_1bit) { - host_ctrl |= SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(0U); - } else if (width == sdxc_bus_width_4bit) { - host_ctrl |= SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(1U); - } else if (width == sdxc_bus_width_8bit) { - host_ctrl |= SDXC_PROT_CTRL_EXT_DAT_XFER_SET(1U); - } else { - /* Do nothing */ - } - base->PROT_CTRL = host_ctrl; - - sdxc_enable_sd_clock(base, true); -} - -uint32_t sdxc_get_data_bus_width(SDXC_Type *base) -{ - uint32_t bus_width; - uint32_t bus_width_mask = base->PROT_CTRL & (SDXC_PROT_CTRL_EXT_DAT_XFER_MASK | SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK); - - if (IS_HPM_BITMASK_SET(bus_width_mask, SDXC_PROT_CTRL_EXT_DAT_XFER_MASK)) { - bus_width = 8; - } else if (IS_HPM_BITMASK_SET(bus_width_mask, SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK)) { - bus_width = 4; - } else { - bus_width = 1; - } - return bus_width; -} - -void sdxc_set_speed_mode(SDXC_Type *base, sdxc_speed_mode_t mode) -{ - uint32_t mode_u32 = (uint32_t) mode; - - base->AC_HOST_CTRL = - (base->AC_HOST_CTRL & ~SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) | SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(mode_u32); - if ((mode_u32 & 0xFU) > sdxc_sd_speed_sdr12) { - base->PROT_CTRL |= SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; - } else { - base->PROT_CTRL &= ~SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK; - } -} - -hpm_stat_t sdxc_transfer_nonblocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) -{ - hpm_stat_t status = status_invalid_argument; - sdxc_command_t *cmd = xfer->command; - sdxc_data_t *data = xfer->data; - uint32_t xfer_flags = (uint32_t) sdxc_cmd_only; - - uint32_t block_size = 0U; - uint32_t block_cnt = 0U; - do { - if (IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_RE_TUNE_EVENT_MASK)) { - base->INT_STAT = SDXC_INT_STAT_RE_TUNE_EVENT_MASK; - status = status_sdxc_retuning_request; - break; - } - - uint32_t new_xfer_flags = 0; - if (data != NULL) { - if ((dma_config != NULL) && (dma_config->dma_type != sdxc_dmasel_nodma)) { - uint32_t flags = IS_HPM_BITMASK_SET(data->data_type, sdxc_xfer_data_boot) ? sdxc_adma_desc_multi_flag - : sdxc_adma_desc_single_flag; - status = sdxc_set_adma_table_config(base, dma_config, data, flags); - if (status != status_success) { - break; - } - cmd->cmd_flags |= SDXC_CMD_XFER_DMA_ENABLE_MASK; - } else { - cmd->cmd_flags &= ~SDXC_CMD_XFER_DMA_ENABLE_MASK; - } - block_size = data->block_size; - block_cnt = data->block_cnt; - xfer_flags = data->enable_auto_cmd12 ? (uint32_t) sdxc_data_with_auto_cmd12 : 0; - xfer_flags |= (data->enable_auto_cmd23) ? (uint32_t) sdxc_data_with_auto_cmd23 : 0; - xfer_flags |= (data->tx_data != NULL) ? (uint32_t) sdxc_cmd_and_tx_data : 0; - xfer_flags |= (data->rx_data != NULL) ? (uint32_t) sdxc_cmd_and_rx_data : 0; - xfer_flags |= (data->data_type == sdxc_xfer_data_boot) ? (uint32_t) sdxc_boot_data : 0; - xfer_flags |= (data->data_type == sdxc_xfer_data_boot_continuous) ? (uint32_t) sdxc_boot_data_continuous - : 0; - cmd->cmd_flags |= SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK; - - status = sdxc_set_transfer_config(base, xfer_flags, block_size, block_cnt, &new_xfer_flags); - if (status != status_success) { - break; - } - } else { - cmd->cmd_flags &= ~(SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DMA_ENABLE_MASK); - } - - cmd->cmd_flags |= new_xfer_flags; - status = sdxc_send_command(base, cmd); - } while (false); - - return status; -} - -hpm_stat_t sdxc_transfer_blocking(SDXC_Type *base, sdxc_adma_config_t *dma_config, sdxc_xfer_t *xfer) -{ - hpm_stat_t status = status_invalid_argument; - sdxc_command_t *cmd = xfer->command; - sdxc_data_t *data = xfer->data; - bool enable_dma = true; - do { - status = sdxc_transfer_nonblocking(base, dma_config, xfer); - HPM_BREAK_IF(status != status_success); - - bool polling_cmd_done = (data == NULL) || (data->data_type == sdxc_xfer_data_normal); - status = sdxc_wait_cmd_done(base, cmd, polling_cmd_done); - if (status != status_success) { - status = status_sdxc_send_cmd_failed; - break; - } - if (data != NULL) { - status = sdxc_transfer_data_blocking(base, data, enable_dma); - } - } while (false); - - return status; -} - -hpm_stat_t sdxc_error_recovery(SDXC_Type *base) -{ - hpm_stat_t status = status_success; - /* D8, D3-D0 of ERROR_INT_STAT */ - uint32_t cmdline_err_mask = - SDXC_INT_STAT_AUTO_CMD_ERR_MASK | SDXC_INT_STAT_CMD_TOUT_ERR_MASK | SDXC_INT_STAT_CMD_CRC_ERR_MASK | - SDXC_INT_STAT_CMD_END_BIT_ERR_MASK | SDXC_INT_STAT_CMD_IDX_ERR_MASK; - - if ((base->INT_STAT & cmdline_err_mask) != 0U) { - status = status_sdxc_send_cmd_failed; - /* Only Auto Command error */ - if ((base->INT_STAT & cmdline_err_mask) == SDXC_INT_STAT_AUTO_CMD_ERR_MASK) { - /* Will reset command line */ - } else { - if (((base->CMD_XFER & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) != 0U) || - ((base->AC_HOST_CTRL & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK))) { - /* Will reset command line */ - } else { - /* Wait until command completes */ - uint32_t timeout = 1000000UL; - while (!IS_HPM_BITMASK_SET(base->CMD_XFER, SDXC_INT_STAT_CMD_COMPLETE_MASK)) { - --timeout; - if (timeout < 1U) { - status = status_timeout; - break; - } - } - } - } - - sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFFFU); - } - - /* Check D9, D6-D4 in ERR_INT_STAT */ - uint32_t dataline_err_mask = - SDXC_INT_STAT_ADMA_ERR_MASK | SDXC_INT_STAT_DATA_TOUT_ERR_MASK | SDXC_INT_STAT_DATA_CRC_ERR_MASK | - SDXC_INT_STAT_DATA_END_BIT_ERR_MASK; - - if ((base->INT_STAT & dataline_err_mask) != 0U) { - status = status_sdxc_transfer_data_failed; - sdxc_reset(base, sdxc_reset_data_line, 0xFFFFFFU); - } - sdxc_clear_interrupt_status(base, ~0UL); - - if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_CMD_INHIBIT_MASK)) { - sdxc_reset(base, sdxc_reset_cmd_line, 10000U); - } - if (IS_HPM_BITMASK_SET(base->PSTATE, SDXC_PSTATE_DAT_INHIBIT_MASK)) { - sdxc_reset(base, sdxc_reset_data_line, 10000U); - } - - return status; -} - -hpm_stat_t sdxc_tuning_error_recovery(SDXC_Type *base) -{ - sdxc_reset_tuning_engine(base); - sdxc_reset(base, sdxc_reset_data_line, 0xFFFFFFUL); - sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFFFUL); - - return status_success; -} - -hpm_stat_t sdxc_perform_tuning_flow_sequence(SDXC_Type *base, uint8_t tuning_cmd) -{ - hpm_stat_t status = status_success; - - /* Turn off Sampling clock */ - sdxc_enable_sd_clock(base, false); - sdxc_execute_tuning(base); - uint32_t block_size = SDXC_PROT_CTRL_EXT_DAT_XFER_GET(base->PROT_CTRL) ? 128U : 64U; - sdxc_command_t cmd; - (void) memset(&cmd, 0, sizeof(cmd)); - cmd.cmd_index = tuning_cmd; - cmd.cmd_argument = 0; - cmd.cmd_flags = SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK; - cmd.resp_type = sdxc_dev_resp_r1; - sdxc_enable_sd_clock(base, true); - do { - base->BLK_ATTR = block_size; - base->SDMASA = 1; - status = sdxc_send_command(base, &cmd); - while (!IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) { - } - sdxc_clear_interrupt_status(base, SDXC_INT_STAT_BUF_RD_READY_MASK); - } while (IS_HPM_BITMASK_SET(base->AC_HOST_CTRL, SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK)); - - if (!IS_HPM_BITMASK_SET(base->AC_HOST_CTRL, SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK)) { - sdxc_tuning_error_recovery(base); - status = status_sdxc_tuning_failed; - } - - return status; -} - -hpm_stat_t sdxc_perform_software_tuning(SDXC_Type *base, uint8_t tuning_cmd) -{ - hpm_stat_t status; - - sdxc_tuning_error_recovery(base); - - /* Turn off Sampling clock */ - sdxc_enable_sd_clock(base, false); - sdxc_reset_tuning_engine(base); - uint32_t block_size = SDXC_PROT_CTRL_EXT_DAT_XFER_GET(base->PROT_CTRL) ? 128U : 64U; - sdxc_command_t cmd; - (void) memset(&cmd, 0, sizeof(cmd)); - cmd.cmd_index = tuning_cmd; - cmd.cmd_argument = 0; - cmd.cmd_flags = SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK | SDXC_CMD_XFER_DATA_XFER_DIR_MASK; - cmd.resp_type = sdxc_dev_resp_r1; - base->BLK_ATTR = block_size; - base->SDMASA = 0; - uint32_t tuning_cclk_sel = 0; - sdxc_enable_software_tuning(base, true); - sdxc_set_center_phase_code(base, 0); - sdxc_enable_sd_clock(base, true); - - bool center_phase_codes_valid[255]; - (void) memset(¢er_phase_codes_valid, 0, sizeof(center_phase_codes_valid)); - - do { - - sdxc_send_command(base, &cmd); - - uint32_t timeout_cnt = 0xFFFFFUL; - while (!IS_HPM_BITMASK_SET(base->INT_STAT, - SDXC_INT_STAT_BUF_RD_READY_MASK | SDXC_INT_STAT_ERR_INTERRUPT_MASK)) { - timeout_cnt--; - if (timeout_cnt < 1U) { - break; - } - } - - if (IS_HPM_BITMASK_SET(base->INT_STAT, SDXC_INT_STAT_BUF_RD_READY_MASK)) { - center_phase_codes_valid[tuning_cclk_sel] = true; - } - sdxc_clear_interrupt_status(base, ~0UL); - - sdxc_reset(base, sdxc_reset_cmd_line, 0xFFFFFFU); - sdxc_reset(base, sdxc_reset_data_line, 0xFFFFFFU); - - tuning_cclk_sel++; - - sdxc_enable_sd_clock(base, false); - sdxc_set_center_phase_code(base, tuning_cclk_sel); - sdxc_enable_sd_clock(base, true); - - } while (tuning_cclk_sel < SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK)); - - int32_t first_window_idx = -1; - int32_t last_window_idx = -1; - for (int32_t i = 0; i < (int32_t) ARRAY_SIZE(center_phase_codes_valid); i++) { - if (center_phase_codes_valid[i]) { - first_window_idx = i; - break; - } - } - - for (int32_t i = ARRAY_SIZE(center_phase_codes_valid) - 1; i >= 0; i--) { - if (center_phase_codes_valid[i]) { - last_window_idx = i; - break; - } - } - - if ((first_window_idx >= 0) && (last_window_idx >= 0)) { - - uint32_t center_window = (first_window_idx + last_window_idx) / 2; - sdxc_set_center_phase_code(base, center_window); - - status = status_success; - } else { - status = status_sdxc_tuning_failed; - } - - return status; -} - -hpm_stat_t sdxc_perform_auto_tuning(SDXC_Type *base, uint8_t tuning_cmd) -{ - bool need_inverse = sdxc_is_inverse_clock_enabled(base); - sdxc_enable_inverse_clock(base, false); - sdxc_enable_sd_clock(base, false); - sdxc_enable_auto_tuning(base, true); - sdxc_enable_inverse_clock(base, need_inverse); - sdxc_enable_sd_clock(base, true); - - return sdxc_perform_tuning_flow_sequence(base, tuning_cmd); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c deleted file mode 100644 index 0054580ebbf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_sei_drv.c +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sei_drv.h" - -hpm_stat_t sei_tranceiver_config_init(SEI_Type *ptr, uint8_t idx, sei_tranceiver_config_t *config) -{ - uint32_t tmp; - uint32_t baudrate; - uint32_t baud_div; - uint32_t sync_point; - uint8_t data_len; - uint32_t ck0_point; - uint32_t ck1_point; - uint32_t txd_point; - uint32_t rxd_point; - - tmp = SEI_CTRL_XCVR_CTRL_TRISMP_SET(config->tri_sample) - | SEI_CTRL_XCVR_CTRL_MODE_SET(config->mode); - ptr->CTRL[idx].XCVR.CTRL = tmp; - - switch (config->mode) { - case sei_synchronous_master_mode: - tmp = SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->synchronous_master_config.data_idle_high_z) - | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->synchronous_master_config.data_idle_state) - | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(config->synchronous_master_config.clock_idle_high_z) - | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(config->synchronous_master_config.clock_idle_state); - ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; - - baud_div = (config->src_clk_freq + (config->synchronous_master_config.baudrate >> 1u)) / config->synchronous_master_config.baudrate; - sync_point = baud_div >> 1u; - tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) - | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); - ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; - - ck0_point = baud_div >> 2u; - ck1_point = ck0_point * 3u; - tmp = SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(ck0_point) - | SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(ck1_point); - ptr->CTRL[idx].XCVR.CLK_CFG = tmp; - break; - - case sei_synchronous_slave_mode: - tmp = SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->synchronous_slave_config.data_idle_high_z) - | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->synchronous_slave_config.data_idle_state) - | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(config->synchronous_slave_config.clock_idle_high_z) - | SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(config->synchronous_slave_config.clock_idle_state); - ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; - - baud_div = (config->src_clk_freq + (config->synchronous_slave_config.max_baudrate >> 1u)) / config->synchronous_slave_config.max_baudrate; - sync_point = (baud_div * 3u) >> 3u; - tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) - | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); - ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; - - ck0_point = config->synchronous_slave_config.ck0_timeout_us * (config->src_clk_freq / 1000000u); - if (ck0_point > 0x7FFFu) { - ck0_point = 0x7FFFu; - } - ck1_point = config->synchronous_slave_config.ck1_timeout_us * (config->src_clk_freq / 1000000u); - if (ck1_point > 0x7FFFu) { - ck1_point = 0x7FFFu; - } - ck1_point += 0x8000u; - tmp = SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(ck0_point) - | SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(ck1_point); - ptr->CTRL[idx].XCVR.CLK_CFG = tmp; - break; - - case sei_asynchronous_mode: - default: - data_len = config->asynchronous_config.data_len; - if (data_len > 0u) { - data_len--; - } - tmp = SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(config->asynchronous_config.wait_len) - | SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(data_len) - | SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(config->asynchronous_config.parity) - | SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(config->asynchronous_config.parity_enable) - | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(config->asynchronous_config.data_idle_high_z) - | SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(config->asynchronous_config.data_idle_state); - ptr->CTRL[idx].XCVR.TYPE_CFG = tmp; - -#if defined(HPM_IP_FEATURE_SEI_ASYNCHRONOUS_MODE_V2) && HPM_IP_FEATURE_SEI_ASYNCHRONOUS_MODE_V2 - baudrate = config->asynchronous_config.baudrate; - baud_div = (config->src_clk_freq + (baudrate >> 1u)) / baudrate; - sync_point = baud_div >> 1u; -#else - baudrate = (config->asynchronous_config.baudrate / 100) * 102; - baud_div = (config->src_clk_freq + (baudrate >> 1u)) / baudrate; - sync_point = (baud_div + 2u); -#endif - tmp = SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(sync_point) - | SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(baud_div - 1u); - ptr->CTRL[idx].XCVR.BAUD_CFG = tmp; - - txd_point = 0; - rxd_point = baud_div >> 1u; - tmp = SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(txd_point) - | SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(rxd_point); - ptr->CTRL[idx].XCVR.DATA_CFG = tmp; - break; - } - - return status_success; -} - -hpm_stat_t sei_cmd_data_format_config_init(SEI_Type *ptr, bool cmd_data_select, uint8_t idx, sei_data_format_config_t *config) -{ - uint32_t tmp; - uint8_t word_len; - uint8_t crc_len; - - if (cmd_data_select) -#if defined(HPM_IP_FEATURE_SEI_HAVE_CTRL2_12) && HPM_IP_FEATURE_SEI_HAVE_CTRL2_12 - assert(idx < 13); -#else - assert(idx < 2); -#endif - else -#if defined(HPM_IP_FEATURE_SEI_HAVE_DAT10_31) && HPM_IP_FEATURE_SEI_HAVE_DAT10_31 - assert(idx < 32); -#else - assert(idx < 10); -#endif - - word_len = config->word_len; - if (word_len > 0u) { - word_len--; - } - crc_len = config->crc_len; - if (crc_len > 0u) { - crc_len--; - } - tmp = SEI_DAT_MODE_MODE_SET(config->mode) - | SEI_DAT_MODE_SIGNED_SET(config->signed_flag) - | SEI_DAT_MODE_BORDER_SET(config->bit_order) - | SEI_DAT_MODE_WORDER_SET(config->word_order) - | SEI_DAT_MODE_CRC_INV_SET(config->crc_invert) - | SEI_DAT_MODE_CRC_SHIFT_SET(config->crc_shift_mode) - | SEI_DAT_MODE_WLEN_SET(word_len) - | SEI_DAT_MODE_CRC_LEN_SET(crc_len); - if (cmd_data_select) { - ptr->CTRL[idx].CMD.MODE = tmp; - } else { - ptr->DAT[idx].MODE = tmp; - } - - tmp = SEI_DAT_IDX_LAST_BIT_SET(config->last_bit) - | SEI_DAT_IDX_FIRST_BIT_SET(config->first_bit) - | SEI_DAT_IDX_MAX_BIT_SET(config->max_bit) - | SEI_DAT_IDX_MIN_BIT_SET(config->min_bit); - if (cmd_data_select) { - ptr->CTRL[idx].CMD.IDX = tmp; - } else { - ptr->DAT[idx].IDX = tmp; - } - - tmp = SEI_DAT_GOLD_GOLD_VALUE_SET(config->gold_value); - if (!cmd_data_select) { - ptr->DAT[idx].GOLD = tmp; - } - - tmp = SEI_DAT_CRCINIT_CRC_INIT_SET(config->crc_init_value); - if (!cmd_data_select) { - ptr->DAT[idx].CRCINIT = tmp; - } - - tmp = SEI_DAT_CRCPOLY_CRC_POLY_SET(config->crc_poly); - if (!cmd_data_select) { - ptr->DAT[idx].CRCPOLY = tmp; - } - - if (cmd_data_select) { - ptr->CTRL[idx].CMD.MODE |= SEI_CTRL_CMD_MODE_REWIND_MASK; - } else { - ptr->DAT[idx].MODE |= SEI_DAT_MODE_REWIND_MASK; - } - - return status_success; -} - -hpm_stat_t sei_cmd_table_config_init(SEI_Type *ptr, uint8_t idx, uint8_t table_idx, sei_command_table_config_t *config) -{ - uint32_t tmp; - - tmp = SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(config->cmd_min_value); - ptr->CTRL[idx].CMD_TABLE[table_idx].MIN = tmp; - - tmp = SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(config->cmd_max_value); - ptr->CTRL[idx].CMD_TABLE[table_idx].MAX = tmp; - - tmp = SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(config->cmd_mask_value); - ptr->CTRL[idx].CMD_TABLE[table_idx].MSK = tmp; - - tmp = SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(config->instr_idx[3]) - | SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(config->instr_idx[2]) - | SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(config->instr_idx[1]) - | SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(config->instr_idx[0]); - ptr->CTRL[idx].CMD_TABLE[table_idx].PTA = tmp; - - tmp = SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(config->instr_idx[7]) - | SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(config->instr_idx[6]) - | SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(config->instr_idx[5]) - | SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(config->instr_idx[4]); - ptr->CTRL[idx].CMD_TABLE[table_idx].PTB = tmp; -#if defined(HPM_IP_FEATURE_SEI_HAVE_PTCD) && HPM_IP_FEATURE_SEI_HAVE_PTCD - tmp = SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(config->instr_idx[11]) - | SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(config->instr_idx[10]) - | SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(config->instr_idx[9]) - | SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(config->instr_idx[8]); - ptr->CTRL[idx].CMD_TABLE[table_idx].PTC = tmp; - - tmp = SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(config->instr_idx[15]) - | SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(config->instr_idx[14]) - | SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(config->instr_idx[13]) - | SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(config->instr_idx[12]); - ptr->CTRL[idx].CMD_TABLE[table_idx].PTD = tmp; -#endif - - return status_success; -} - -hpm_stat_t sei_state_transition_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, uint8_t state, sei_state_transition_config_t *config) -{ -#if defined(HPM_IP_FEATURE_SEI_RX_LATCH_FEATURE) && HPM_IP_FEATURE_SEI_RX_LATCH_FEATURE - uint32_t tmp; - tmp = SEI_CTRL_LATCH_TRAN_POINTER_SET(config->instr_ptr_value) - | SEI_CTRL_LATCH_TRAN_CFG_TM_SET(config->timeout_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(config->txd_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_RXD_SET(config->rxd_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(config->clk_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(config->instr_ptr_cfg) - | SEI_CTRL_LATCH_TRAN_OV_TM_SET(config->disable_timeout_check) - | SEI_CTRL_LATCH_TRAN_OV_TXD_SET(config->disable_txd_check) - | SEI_CTRL_LATCH_TRAN_OV_RXD_SET(config->disable_rxd_check) - | SEI_CTRL_LATCH_TRAN_OV_CLK_SET(config->disable_clk_check) - | SEI_CTRL_LATCH_TRAN_OV_PTR_SET(config->disable_instr_ptr_check); -#else - uint32_t tmp = 0x08u; - tmp |= SEI_CTRL_LATCH_TRAN_POINTER_SET(config->instr_ptr_value) - | SEI_CTRL_LATCH_TRAN_CFG_TM_SET(config->timeout_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(config->txd_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(config->clk_cfg) - | SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(config->instr_ptr_cfg) - | SEI_CTRL_LATCH_TRAN_OV_TM_SET(config->disable_timeout_check) - | SEI_CTRL_LATCH_TRAN_OV_TXD_SET(config->disable_txd_check) - | SEI_CTRL_LATCH_TRAN_OV_CLK_SET(config->disable_clk_check) - | SEI_CTRL_LATCH_TRAN_OV_PTR_SET(config->disable_instr_ptr_check); -#endif - ptr->CTRL[idx].LATCH[latch_idx].TRAN[state] = tmp; - return status_success; -} - -hpm_stat_t sei_state_transition_latch_config_init(SEI_Type *ptr, uint8_t idx, uint8_t latch_idx, sei_state_transition_latch_config_t *config) -{ - uint32_t tmp; - - tmp = SEI_CTRL_LATCH_CFG_DELAY_SET(config->delay) - | SEI_CTRL_LATCH_CFG_SELECT_SET(config->output_select) - | SEI_CTRL_LATCH_CFG_EN_SET(config->enable); - ptr->CTRL[idx].LATCH[latch_idx].CFG = tmp; - - return status_success; -} - -hpm_stat_t sei_sample_config_init(SEI_Type *ptr, uint8_t idx, sei_sample_config_t *config) -{ - uint32_t tmp; - - tmp = SEI_CTRL_POS_SMP_CFG_ONCE_SET(config->sample_once) - | SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(config->latch_select) - | SEI_CTRL_POS_SMP_CFG_WINDOW_SET(config->sample_window); - ptr->CTRL[idx].POS.SMP_CFG = tmp; - - ptr->CTRL[idx].POS.SMP_DAT = SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(config->data_register_select); - - tmp = SEI_CTRL_POS_SMP_EN_ACC_EN_SET(config->acc_data_use_rx) - | SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(config->acc_data_idx) - | SEI_CTRL_POS_SMP_EN_SPD_EN_SET(config->spd_data_use_rx) - | SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(config->spd_data_idx) - | SEI_CTRL_POS_SMP_EN_REV_EN_SET(config->rev_data_use_rx) - | SEI_CTRL_POS_SMP_EN_REV_SEL_SET(config->rev_data_idx) - | SEI_CTRL_POS_SMP_EN_POS_EN_SET(config->pos_data_use_rx) - | SEI_CTRL_POS_SMP_EN_POS_SEL_SET(config->pos_data_idx); - ptr->CTRL[idx].POS.SMP_EN = tmp; - - return status_success; -} - -hpm_stat_t sei_update_config_init(SEI_Type *ptr, uint8_t idx, sei_update_config_t *config) -{ - uint32_t tmp; - - tmp = SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(config->time_use_override) - | SEI_CTRL_POS_UPD_CFG_ONERR_SET(config->update_on_err) - | SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(config->latch_select); - ptr->CTRL[idx].POS.UPD_CFG = tmp; - - ptr->CTRL[idx].POS.UPD_DAT = SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(config->data_register_select); - - tmp = SEI_CTRL_POS_UPD_EN_ACC_EN_SET(config->acc_data_use_rx) - | SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(config->acc_data_idx) - | SEI_CTRL_POS_UPD_EN_SPD_EN_SET(config->spd_data_use_rx) - | SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(config->spd_data_idx) - | SEI_CTRL_POS_UPD_EN_REV_EN_SET(config->rev_data_use_rx) - | SEI_CTRL_POS_UPD_EN_REV_SEL_SET(config->rev_data_idx) - | SEI_CTRL_POS_UPD_EN_POS_EN_SET(config->pos_data_use_rx) - | SEI_CTRL_POS_UPD_EN_POS_SEL_SET(config->pos_data_idx); - ptr->CTRL[idx].POS.UPD_EN = tmp; - - return status_success; -} - -hpm_stat_t sei_trigger_input_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_input_config_t *config) -{ - uint32_t tmp; - uint32_t period; - - tmp = SEI_CTRL_TRG_PRD_CFG_ARMING_SET(config->trig_period_arming_mode) - | SEI_CTRL_TRG_PRD_CFG_SYNC_SET(config->trig_period_sync_enable); - ptr->CTRL[idx].TRG.PRD_CFG = tmp; - - period = config->trig_period_time; - if (period > 0) { - period--; - } - ptr->CTRL[idx].TRG.PRD = SEI_CTRL_TRG_PRD_PERIOD_SET(period); - - tmp = SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(config->trig_period_enable) - | SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(config->trig_period_sync_select) - | SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(config->trig_in1_enable) - | SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(config->trig_in1_select) - | SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(config->trig_in0_enable) - | SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(config->trig_in0_select) -#if defined(HPM_IP_FEATURE_SEI_TIMEOUT_REWIND_FEATURE) && HPM_IP_FEATURE_SEI_TIMEOUT_REWIND_FEATURE - | SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(config->rewind_enable) - | SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(config->rewind_select) -#endif - ; - ptr->CTRL[idx].TRG.IN_CFG = tmp; - - return status_success; -} - -hpm_stat_t sei_trigger_output_config_init(SEI_Type *ptr, uint8_t idx, sei_trigger_output_config_t *config) -{ - uint32_t tmp; - - tmp = ptr->CTRL[idx].TRG.OUT_CFG; - if (config->src_latch_select == SEI_LATCH_0) { - tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK); - tmp |= SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(config->trig_out_select); - } else if (config->src_latch_select == SEI_LATCH_1) { - tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK); - tmp |= SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(config->trig_out_select); - } else if (config->src_latch_select == SEI_LATCH_2) { - tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK); - tmp |= SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(config->trig_out_select); - } else if (config->src_latch_select == SEI_LATCH_3) { - tmp &= ~(SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK | SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK); - tmp |= SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(config->trig_out_enable) | SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(config->trig_out_select); - } else { - return status_invalid_argument; - } - ptr->CTRL[idx].TRG.OUT_CFG = tmp; - - return status_success; -} - -hpm_stat_t sei_engine_config_init(SEI_Type *ptr, uint8_t idx, sei_engine_config_t *config) -{ - uint32_t tmp; - - tmp = SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(config->data_cdm_idx) - | SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(config->data_base_idx) - | SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(config->wdg_instr_idx) - | SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(config->init_instr_idx); - ptr->CTRL[idx].ENGINE.PTR_CFG = tmp; - - ptr->CTRL[idx].ENGINE.WDG_CFG = SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(config->wdg_time); - - tmp = SEI_CTRL_ENGINE_CTRL_WATCH_SET(config->wdg_enable) - | SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(config->wdg_action) - | SEI_CTRL_ENGINE_CTRL_ARMING_SET(config->arming_mode); - ptr->CTRL[idx].ENGINE.CTRL = tmp; - - return status_success; -} - -void sei_set_instr(SEI_Type *ptr, uint8_t idx, uint8_t op, uint8_t ck, uint8_t crc, uint8_t data, uint8_t opr) -{ - uint32_t tmp; - -#if !defined(HPM_IP_FEATURE_SEI_HAVE_INTR64_255) || !HPM_IP_FEATURE_SEI_HAVE_INTR64_255 - assert(idx < 64); -#endif - if ((op != SEI_INSTR_OP_HALT) && (op != SEI_INSTR_OP_JUMP) && (opr > 0)) { - opr--; - } - if (opr > 0x1F) { - opr = 0x1F; - } - tmp = SEI_INSTR_OP_SET(op) - | SEI_INSTR_CK_SET(ck) - | SEI_INSTR_CRC_SET(crc) - | SEI_INSTR_DAT_SET(data) - | SEI_INSTR_OPR_SET(opr); - - ptr->INSTR[idx] = tmp; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c deleted file mode 100644 index 1128f4db1e8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_smix_drv.c +++ /dev/null @@ -1,261 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_smix_drv.h" - -static uint8_t smix_get_fir_shift(smix_mixer_rate_convert_t rate) -{ - uint8_t shift = 0; - - switch (rate) { - case smix_mixer_no_rate_convert: - case smix_mixer_upper_2x_sample: - case smix_mixer_upper_3x_sample: - shift = 0; - break; - case smix_mixer_upper_4x_sample: - case smix_mixer_upper_6x_sample: - shift = 1; - break; - case smix_mixer_upper_8x_sample: - case smix_mixer_upper_12x_sample: - shift = 2; - break; - case smix_mixer_lower_2x_sample: - shift = 7; - break; - default: - shift = 0; - break; - } - - return shift; -} - -void smix_get_dma_default_ch_config(SMIX_Type *ptr, smix_dma_ch_config_t *config) -{ - (void) ptr; - config->priority = 0; - config->src_mode = smix_dma_mode_normal; - config->dst_mode = smix_dma_mode_normal; - config->src_width = smix_dma_transfer_half_word; - config->dst_width = smix_dma_transfer_half_word; - config->src_addr_ctrl = smix_dma_address_increment; - config->dst_addr_ctrl = smix_dma_address_increment; - config->src_burst_size = smix_dma_transfer_burst_1t; - config->trans_bytes = 0; - config->linked_ptr = 0; - config->src_req_sel = 0; - config->dst_req_sel = 0; - - config->abort_int_en = false; - config->error_int_en = false; - config->complete_int_en = false; -} - - -void smix_get_mixer_dst_ch_default_config(SMIX_Type *ptr, smix_mixer_dst_config_t *config) -{ - (void) ptr; - config->underflow_int_en = false; - config->fifo_thr = 8; /* Must be greater than or equal to 8 */ - config->calsat_int_en = false; - config->da_int_en = false; - config->auto_deactivate_en = false; - config->fadeout_done_int_en = false; - config->deactivate_en = false; - config->active_en = true; - config->fadeout_now_en = false; - config->fadeout_auto_en = false; - config->fadein_en = false; - config->channel_en = true; - config->mixer_en = true; - - config->gain = smix_mixer_gain_0db; - config->length = 0; /* 0 = infinite length */ - config->fadein_delta = 6; /* 48K sample rate, need 3s */ - config->fadeout_delta = 14; /* 48K sample rate, need 1/3s */ - config->src_ch_mask = 0x1; -} - -void smix_get_mixer_source_ch_default_config(SMIX_Type *ptr, smix_mixer_source_config_t *config) -{ - (void) ptr; - config->fifo_thr = 4; /* Must be greater than or equal to 4 */ - config->calsat_int_en = false; - config->dn_int_en = false; - config->auto_deactivate_en = true; - config->fadeout_int_en = false; - - config->convert_rate = smix_mixer_no_rate_convert; - config->gain = smix_mixer_gain_0db; - config->fadein_delta = 6; /* 48K sample rate, need 3s */ - config->fadeout_delta = 14; /* 48K sample rate, need 1/3s */ - config->length = 0; /* 0 = infinite length */ -} - -hpm_stat_t smix_config_dma_channel(SMIX_Type *ptr, uint8_t ch, smix_dma_ch_config_t *config, bool start) -{ - uint32_t tmp; - - if ((config->trans_bytes & ((1 << config->dst_width) - 1)) - || (config->src_addr & ((1 << config->src_width) - 1)) - || (config->dst_addr & ((1 << config->dst_width) - 1)) - || (config->linked_ptr & 0x7)) { - return status_invalid_argument; - } - - ptr->DMA_CH[ch].SRCADDR = SMIX_DMA_CH_SRCADDR_PTR_SET(config->src_addr); - ptr->DMA_CH[ch].DSTADDR = SMIX_DMA_CH_DSTADDR_PTR_SET(config->dst_addr); - ptr->DMA_CH[ch].BURST_COUNT = SMIX_DMA_CH_BURST_COUNT_NUM_SET(config->trans_bytes >> config->src_width); - ptr->DMA_CH[ch].LLP = SMIX_DMA_CH_LLP_PTR_SET(config->linked_ptr); - - /* clear status bit, W1C */ - ptr->DMAC_ERR_ST = 1 << ch; - ptr->DMAC_ABRT_ST = 1 << ch; - ptr->DMAC_TC_ST = 1 << ch; - - tmp = SMIX_DMA_CH_CTL_SRCREQSEL_SET(config->src_req_sel) - | SMIX_DMA_CH_CTL_DSTREQSEL_SET(config->dst_req_sel) - | SMIX_DMA_CH_CTL_PRIORITY_SET(config->priority) - | SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(config->src_burst_size) - | SMIX_DMA_CH_CTL_SRCWIDTH_SET(config->src_width) - | SMIX_DMA_CH_CTL_DSTWIDTH_SET(config->dst_width) - | SMIX_DMA_CH_CTL_SRCMODE_SET(config->src_mode) - | SMIX_DMA_CH_CTL_DSTMODE_SET(config->dst_mode) - | SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(config->src_addr_ctrl) - | SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(config->dst_addr_ctrl) - | SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(config->abort_int_en) - | SMIX_DMA_CH_CTL_ERR_INT_EN_SET(config->error_int_en) - | SMIX_DMA_CH_CTL_TC_INT_EN_SET(config->complete_int_en); - - if (start) { - tmp |= SMIX_DMA_CH_CTL_EN_MASK; - } - ptr->DMA_CH[ch].CTL = tmp; - - return status_success; -} - -hpm_stat_t smix_mixer_config_source_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_source_config_t *src) -{ - /* reset fifo */ - ptr->SOURCE_CH[ch].CTRL |= SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK; - ptr->SOURCE_CH[ch].CTRL &= ~SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK; - - ptr->SOURCE_CH[ch].CTRL = SMIX_SOURCE_CH_CTRL_THRSH_SET(src->fifo_thr) - | SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(src->calsat_int_en) - | SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(src->dn_int_en) - | SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(smix_get_fir_shift(src->convert_rate)) - | SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(src->auto_deactivate_en) - | SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(src->fadeout_int_en) - | SMIX_SOURCE_CH_CTRL_RATECONV_SET(src->convert_rate); - - ptr->SOURCE_CH[ch].GAIN = SMIX_SOURCE_CH_GAIN_VAL_SET(src->gain); - - ptr->SOURCE_CH[ch].FADEIN = SMIX_SOURCE_CH_FADEIN_DELTA_SET(src->fadein_delta); - - ptr->SOURCE_CH[ch].FADEOUT = SMIX_SOURCE_CH_FADEOUT_DELTA_SET(src->fadeout_delta); - - if (src->length == 0) { - ptr->SOURCE_CH[ch].BUFSIZE = SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(0); - } else { - ptr->SOURCE_CH[ch].BUFSIZE = SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(src->length - 1); - } - - return status_success; -} - - -hpm_stat_t smix_mixer_config_dst_ch(SMIX_Type *ptr, uint8_t ch, smix_mixer_dst_config_t *dst) -{ - /* Reset */ - ptr->DST_CH[ch].CTRL |= SMIX_DST_CH_CTRL_SOFTRST_MASK; - ptr->DST_CH[ch].CTRL &= ~SMIX_DST_CH_CTRL_SOFTRST_MASK; - - ptr->DST_CH[ch].GAIN = SMIX_DST_CH_GAIN_VAL_SET(dst->gain); - - if (dst->length == 0) { - ptr->DST_CH[ch].BUFSIZE = SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(0); - } else { - ptr->DST_CH[ch].BUFSIZE = SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(dst->length - 1); - } - - ptr->DST_CH[ch].FADEIN = SMIX_DST_CH_FADEIN_DELTA_SET(dst->fadein_delta); - - ptr->DST_CH[ch].FADEOUT = SMIX_DST_CH_FADEOUT_DELTA_SET(dst->fadeout_delta); - - ptr->DST_CH[ch].SOURCE_EN = dst->src_ch_mask; - ptr->DST_CH[ch].SOURCE_ACT = dst->src_ch_mask; - - ptr->DST_CH[ch].CTRL = SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(dst->underflow_int_en) - | SMIX_DST_CH_CTRL_THRSH_SET(dst->fifo_thr) - | SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(dst->calsat_int_en) - | SMIX_DST_CH_CTRL_DA_INT_EN_SET(dst->da_int_en) - | SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(dst->auto_deactivate_en) - | SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(dst->fadeout_done_int_en) - | SMIX_DST_CH_CTRL_DST_DEACT_SET(dst->deactivate_en) - | SMIX_DST_CH_CTRL_DST_ACT_SET(dst->active_en) - | SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(dst->fadeout_now_en) - | SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(dst->fadeout_auto_en) - | SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(dst->fadein_en) - | SMIX_DST_CH_CTRL_DST_EN_SET(dst->channel_en); - - /* Workaround: DST_CH[0].CTRL.MIXER_EN bit controls mixer module enable or disable, DST_CH[1].CTRL.MIXER_EN should not be set */ - if (dst->mixer_en) { - ptr->DST_CH[0].CTRL |= SMIX_DST_CH_CTRL_MIXER_EN_MASK; - ptr->DST_CH[1].CTRL &= ~SMIX_DST_CH_CTRL_MIXER_EN_MASK; - } - - return status_success; -} - -hpm_stat_t smix_mixer_config_dst_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) -{ - uint32_t delta = SMIX_DST_CH_FADEIN_DELTA_MASK * 1000 / target_sample_rate / ms; - - if (delta == 0) { - return status_invalid_argument; - } - ptr->DST_CH[ch].FADEIN = SMIX_DST_CH_FADEIN_DELTA_SET(delta); - return status_success; -} - -hpm_stat_t smix_mixer_config_dst_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) -{ - uint32_t delta = (uint32_t)log2(target_sample_rate * ms / 1000); - - /* fadeout delta valid bit: 14 */ - if (delta > 0x3fff) { - return status_invalid_argument; - } - ptr->DST_CH[ch].FADEOUT = SMIX_DST_CH_FADEOUT_DELTA_SET(delta); - return status_success; -} - -hpm_stat_t smix_mixer_config_source_fadein_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) -{ - uint32_t delta = SMIX_DST_CH_FADEIN_DELTA_MASK * 1000 / target_sample_rate / ms; - - if (delta == 0) { - return status_invalid_argument; - } - ptr->SOURCE_CH[ch].FADEIN = SMIX_SOURCE_CH_FADEIN_DELTA_SET(delta); - return status_success; -} - -hpm_stat_t smix_mixer_config_source_fadeout_delta(SMIX_Type *ptr, uint8_t ch, uint32_t target_sample_rate, uint32_t ms) -{ - uint32_t delta = (uint32_t)log2(target_sample_rate * ms / 1000); - - /* fadeout delta valid bit: 14 */ - if (delta > 0x3fff) { - return status_invalid_argument; - } - ptr->SOURCE_CH[ch].FADEOUT = SMIX_SOURCE_CH_FADEOUT_DELTA_SET(delta); - return status_success; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c deleted file mode 100644 index c5f2ff43d74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_spi_drv.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_spi_drv.h" - -#ifndef HPM_SPI_DRV_DEFAULT_RETRY_COUNT -/* the waiting time of timeout status is related to retry count and CPU frequency */ -#define HPM_SPI_DRV_DEFAULT_RETRY_COUNT (5000U) -#endif - -hpm_stat_t spi_wait_for_idle_status(SPI_Type *ptr) -{ - uint32_t status; - uint32_t retry = 0; - - do { - status = ptr->STATUS; - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } while (status & SPI_STATUS_SPIACTIVE_MASK); - - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - return status_success; -} - -hpm_stat_t spi_wait_for_busy_status(SPI_Type *ptr) -{ - uint32_t status; - uint32_t retry = 0; - - do { - status = ptr->STATUS; - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } while (!(status & SPI_STATUS_SPIACTIVE_MASK)); - - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - return status_timeout; - } - - return status_success; -} - -hpm_stat_t spi_write_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd) -{ - if (mode == spi_master_mode) { - if (config->master_config.cmd_enable == true) { - if (cmd == NULL) { - return status_invalid_argument; - } - ptr->CMD = SPI_CMD_CMD_SET(*cmd); - } else { - ptr->CMD = SPI_CMD_CMD_SET(0xff); /* Write a dummy byte */ - } - } - - return status_success; -} - -hpm_stat_t spi_read_command(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint8_t *cmd) -{ - if (mode == spi_slave_mode) { - if (config->slave_config.slave_data_only == false) { - if (cmd == NULL) { - return status_invalid_argument; - } - *cmd = (uint8_t)(ptr->CMD & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT; - } - } - - return status_success; -} - -hpm_stat_t spi_write_address(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config, uint32_t *addr) -{ - if (mode == spi_master_mode) { - if (config->master_config.addr_enable == true) { - if (addr == NULL) { - return status_invalid_argument; - } - ptr->ADDR = SPI_ADDR_ADDR_SET(*addr); - } - } - - return status_success; -} - -hpm_stat_t spi_write_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count) -{ - uint32_t status; - uint32_t transferred = 0; - uint32_t retry = 0; - uint32_t temp; - - /* check parameter validity */ - if (buff == NULL || count == 0) { - return status_invalid_argument; - } - - if (data_len_in_bytes > 4 || data_len_in_bytes < 1) { - return status_invalid_argument; - } - - /* data transfer */ - while (transferred < count) { - status = ptr->STATUS; - if (!(status & SPI_STATUS_TXFULL_MASK)) { - /* write data into the txfifo */ - temp = 0; - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - temp += *(buff++) << i * 8; - } - ptr->DATA = temp; - /* transfer count increment */ - transferred++; - retry = 0; - } else { - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - /* dummy state may triggers timeout if dummy count, retry count, spi rate and cpu frequency are inappropriate */ - return status_timeout; - } - - return status_success; -} - -hpm_stat_t spi_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *buff, uint32_t count) -{ - uint32_t transferred = 0; - uint32_t retry = 0; - uint32_t temp; - uint8_t rx_valid_size = 0; - uint8_t j = 0; - /* check parameter validity */ - if (buff == NULL || count == 0) { - return status_invalid_argument; - } - - if (data_len_in_bytes > 4 || data_len_in_bytes < 1) { - return status_invalid_argument; - } - - /* data transfer */ - while (transferred < count) { - rx_valid_size = spi_get_rx_fifo_valid_data_size(ptr); - if (rx_valid_size > 0) { - for (j = 0; j < rx_valid_size; j++) { - temp = ptr->DATA; - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - *(buff++) = (uint8_t)(temp >> (i * 8)); - } - } - /* transfer count increment */ - transferred += rx_valid_size; - retry = 0; - } else { - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - /* dummy state may triggers timeout if dummy count, retry count, spi rate and cpu frequency are inappropriate */ - return status_timeout; - } - - return status_success; -} - -hpm_stat_t spi_write_read_data(SPI_Type *ptr, uint8_t data_len_in_bytes, uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount) -{ - uint32_t status; - uint32_t wtransferred = 0; - uint32_t rtransferred = 0; - uint32_t retry = 0; - uint32_t temp; - - /* check parameter validity */ - if (wbuff == NULL || wcount == 0 || rbuff == NULL || rcount == 0) { - return status_invalid_argument; - } - - if (data_len_in_bytes > 4 || data_len_in_bytes < 1) { - return status_invalid_argument; - } - - /* data transfer */ - while (wtransferred < wcount || rtransferred < rcount) { - status = ptr->STATUS; - - if (wtransferred < wcount) { - /* write data into the txfifo */ - if (!(status & SPI_STATUS_TXFULL_MASK)) { - temp = 0; - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - temp += *(wbuff++) << i * 8; - } - ptr->DATA = temp; - /* transfer count increment */ - wtransferred++; - retry = 0; - } else { - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - - if (rtransferred < rcount) { - /* read data from the txfifo */ - if (!(status & SPI_STATUS_RXEMPTY_MASK)) { - temp = ptr->DATA; - for (uint8_t i = 0; i < data_len_in_bytes; i++) { - *(rbuff++) = (uint8_t)(temp >> (i * 8)); - } - /* transfer count increment */ - rtransferred++; - retry = 0; - } else { - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - break; - } - retry++; - } - } - } - - if (retry > HPM_SPI_DRV_DEFAULT_RETRY_COUNT) { - /* dummy state may triggers timeout if dummy count, retry count, spi rate and cpu frequency are inappropriate */ - return status_timeout; - } - - return status_success; -} - -static hpm_stat_t spi_no_data(SPI_Type *ptr, spi_mode_selection_t mode, spi_control_config_t *config) -{ - (void) ptr; - if (mode == spi_master_mode) { - if (config->master_config.cmd_enable == false && config->master_config.addr_enable == false) { - return status_invalid_argument; - } - } - return status_success; -} - -void spi_master_get_default_timing_config(spi_timing_config_t *config) -{ - config->master_config.cs2sclk = spi_cs2sclk_half_sclk_4; - config->master_config.csht = spi_csht_half_sclk_12; -} - -void spi_master_get_default_format_config(spi_format_config_t *config) -{ - config->master_config.addr_len_in_bytes = 1; - config->common_config.data_len_in_bits = 32; - config->common_config.data_merge = false; - config->common_config.mosi_bidir = false; - config->common_config.lsb = false; - config->common_config.mode = spi_master_mode; - config->common_config.cpol = spi_sclk_high_idle; - config->common_config.cpha = spi_sclk_sampling_even_clk_edges; -} - -void spi_slave_get_default_format_config(spi_format_config_t *config) -{ - config->common_config.data_len_in_bits = 32; - config->common_config.data_merge = false; - config->common_config.mosi_bidir = false; - config->common_config.lsb = false; - config->common_config.mode = spi_master_mode; - config->common_config.cpol = spi_sclk_high_idle; - config->common_config.cpha = spi_sclk_sampling_even_clk_edges; -} - -void spi_master_get_default_control_config(spi_control_config_t *config) -{ - config->master_config.cmd_enable = false; - config->master_config.addr_enable = false; - config->master_config.token_enable = false; - config->master_config.token_value = spi_token_value_0x00; - config->master_config.addr_phase_fmt = spi_address_phase_format_single_io_mode; - config->common_config.tx_dma_enable = false; - config->common_config.rx_dma_enable = false; - config->common_config.trans_mode = spi_trans_write_only; - config->common_config.data_phase_fmt = spi_single_io_mode; - config->common_config.dummy_cnt = spi_dummy_count_2; -#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) - config->common_config.cs_index = spi_cs_0; -#endif -} - -void spi_slave_get_default_control_config(spi_control_config_t *config) -{ - config->slave_config.slave_data_only = false; - config->common_config.tx_dma_enable = false; - config->common_config.rx_dma_enable = false; - config->common_config.trans_mode = spi_trans_read_only; - config->common_config.data_phase_fmt = spi_single_io_mode; - config->common_config.dummy_cnt = spi_dummy_count_2; -#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) - config->common_config.cs_index = spi_cs_0; -#endif -} - -hpm_stat_t spi_master_timing_init(SPI_Type *ptr, spi_timing_config_t *config) -{ - uint8_t sclk_div; - uint8_t div_remainder; - uint8_t div_integer; - if (config->master_config.sclk_freq_in_hz == 0) { - return status_invalid_argument; - } - - if (config->master_config.clk_src_freq_in_hz > config->master_config.sclk_freq_in_hz) { - div_remainder = (config->master_config.clk_src_freq_in_hz % config->master_config.sclk_freq_in_hz); - div_integer = (config->master_config.clk_src_freq_in_hz / config->master_config.sclk_freq_in_hz); - if ((div_remainder != 0) || ((div_integer % 2) != 0)) { - return status_invalid_argument; - } - sclk_div = (div_integer / 2) - 1; - } else { - sclk_div = 0xff; - } - - ptr->TIMING = SPI_TIMING_CS2SCLK_SET(config->master_config.cs2sclk) | - SPI_TIMING_CSHT_SET(config->master_config.csht) | - SPI_TIMING_SCLK_DIV_SET(sclk_div); - - return status_success; -} - -void spi_format_init(SPI_Type *ptr, spi_format_config_t *config) -{ - ptr->TRANSFMT = SPI_TRANSFMT_ADDRLEN_SET(config->master_config.addr_len_in_bytes - 1) | - SPI_TRANSFMT_DATALEN_SET(config->common_config.data_len_in_bits - 1) | - SPI_TRANSFMT_DATAMERGE_SET(config->common_config.data_merge) | - SPI_TRANSFMT_MOSIBIDIR_SET(config->common_config.mosi_bidir) | - SPI_TRANSFMT_LSB_SET(config->common_config.lsb) | - SPI_TRANSFMT_SLVMODE_SET(config->common_config.mode) | - SPI_TRANSFMT_CPOL_SET(config->common_config.cpol) | - SPI_TRANSFMT_CPHA_SET(config->common_config.cpha); -} - -hpm_stat_t spi_control_init(SPI_Type *ptr, spi_control_config_t *config, uint32_t wcount, uint32_t rcount) -{ -#if defined (SPI_SOC_TRANSFER_COUNT_MAX) && (SPI_SOC_TRANSFER_COUNT_MAX == 512) - if ((wcount > SPI_SOC_TRANSFER_COUNT_MAX) || (rcount > SPI_SOC_TRANSFER_COUNT_MAX)) { - return status_invalid_argument; - } -#endif - /* slave data only mode only works on write read together transfer mode */ - if (config->slave_config.slave_data_only == true && config->common_config.trans_mode != spi_trans_write_read_together) { - return status_invalid_argument; - } - - ptr->TRANSCTRL = SPI_TRANSCTRL_SLVDATAONLY_SET(config->slave_config.slave_data_only) | - SPI_TRANSCTRL_CMDEN_SET(config->master_config.cmd_enable) | - SPI_TRANSCTRL_ADDREN_SET(config->master_config.addr_enable) | - SPI_TRANSCTRL_ADDRFMT_SET(config->master_config.addr_phase_fmt) | - SPI_TRANSCTRL_TRANSMODE_SET(config->common_config.trans_mode) | - SPI_TRANSCTRL_DUALQUAD_SET(config->common_config.data_phase_fmt) | - SPI_TRANSCTRL_TOKENEN_SET(config->master_config.token_enable) | - SPI_TRANSCTRL_WRTRANCNT_SET(wcount - 1) | - SPI_TRANSCTRL_TOKENVALUE_SET(config->master_config.token_value) | - SPI_TRANSCTRL_DUMMYCNT_SET(config->common_config.dummy_cnt) | - SPI_TRANSCTRL_RDTRANCNT_SET(rcount - 1); - -#if defined(HPM_IP_FEATURE_SPI_CS_SELECT) && (HPM_IP_FEATURE_SPI_CS_SELECT == 1) - ptr->CTRL = (ptr->CTRL & ~SPI_CTRL_CS_EN_MASK) | SPI_CTRL_CS_EN_SET(config->common_config.cs_index); -#endif - -#if defined(HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT) && (HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT == 1) - ptr->WR_TRANS_CNT = wcount - 1; - ptr->RD_TRANS_CNT = rcount - 1; -#endif - - /* reset txfifo, rxfifo and control */ - ptr->CTRL |= SPI_CTRL_TXFIFORST_MASK | SPI_CTRL_RXFIFORST_MASK | SPI_CTRL_SPIRST_MASK; - - return status_success; -} - -hpm_stat_t spi_transfer(SPI_Type *ptr, - spi_control_config_t *config, - uint8_t *cmd, uint32_t *addr, - uint8_t *wbuff, uint32_t wcount, uint8_t *rbuff, uint32_t rcount) -{ - hpm_stat_t stat = status_fail; - uint8_t mode, data_len_in_bytes, trans_mode; - - stat = spi_control_init(ptr, config, wcount, rcount); - if (stat != status_success) { - return stat; - } - - /* read data length */ - data_len_in_bytes = spi_get_data_length_in_bytes(ptr); - - /* read spi control mode */ - mode = (ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT; - - /* read spi transfer mode */ - trans_mode = config->common_config.trans_mode; - - /* write address on master mode */ - stat = spi_write_address(ptr, mode, config, addr); - if (stat != status_success) { - return stat; - } - - /* write command on master mode */ - stat = spi_write_command(ptr, mode, config, cmd); - if (stat != status_success) { - return stat; - } - - /* data phase */ - if (trans_mode == spi_trans_write_read_together) { - stat = spi_write_read_data(ptr, data_len_in_bytes, wbuff, wcount, rbuff, rcount); - } else if (trans_mode == spi_trans_write_only || trans_mode == spi_trans_dummy_write) { - stat = spi_write_data(ptr, data_len_in_bytes, wbuff, wcount); - } else if (trans_mode == spi_trans_read_only || trans_mode == spi_trans_dummy_read) { - stat = spi_read_data(ptr, data_len_in_bytes, rbuff, rcount); - } else if (trans_mode == spi_trans_write_read || trans_mode == spi_trans_write_dummy_read) { - stat = spi_write_read_data(ptr, data_len_in_bytes, wbuff, wcount, rbuff, rcount); - } else if (trans_mode == spi_trans_read_write || trans_mode == spi_trans_read_dummy_write) { - stat = spi_write_read_data(ptr, data_len_in_bytes, wbuff, wcount, rbuff, rcount); - } else if (trans_mode == spi_trans_no_data) { - stat = spi_no_data(ptr, mode, config); - } else { - stat = status_invalid_argument; - } - - if (stat != status_success) { - return stat; - } - - /* read command on slave mode */ - stat = spi_read_command(ptr, mode, config, cmd); - if (stat != status_success) { - return stat; - } - /* on the slave mode, if master keeps asserting the cs signal, it's maybe timeout */ - stat = spi_wait_for_idle_status(ptr); - return stat; -} - -hpm_stat_t spi_setup_dma_transfer(SPI_Type *ptr, - spi_control_config_t *config, - uint8_t *cmd, uint32_t *addr, - uint32_t wcount, uint32_t rcount) -{ - hpm_stat_t stat = status_fail; - uint8_t mode; - - stat = spi_control_init(ptr, config, wcount, rcount); - if (stat != status_success) { - return stat; - } - - if (config->common_config.tx_dma_enable) { - ptr->CTRL |= SPI_CTRL_TXDMAEN_MASK; - } - if (config->common_config.rx_dma_enable) { - ptr->CTRL |= SPI_CTRL_RXDMAEN_MASK; - } - - /* read spi control mode */ - mode = (ptr->TRANSFMT & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT; - - /* address phase */ - stat = spi_write_address(ptr, mode, config, addr); - if (stat != status_success) { - return stat; - } - - /* command phase */ - stat = spi_write_command(ptr, mode, config, cmd); - if (stat != status_success) { - return stat; - } - - return stat; -} - - -#if defined(HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO) && (HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO == 1) -hpm_stat_t spi_directio_enable_output(SPI_Type *ptr, spi_directio_pin_t pin) -{ - hpm_stat_t stat = status_success; - switch (pin) { - case hold_pin: - ptr->DIRECTIO |= SPI_DIRECTIO_HOLD_OE_MASK; - break; - case wp_pin: - ptr->DIRECTIO |= SPI_DIRECTIO_WP_OE_MASK; - break; - case miso_pin: - ptr->DIRECTIO |= SPI_DIRECTIO_MISO_OE_MASK; - break; - case mosi_pin: - ptr->DIRECTIO |= SPI_DIRECTIO_MOSI_OE_MASK; - break; - case sclk_pin: - ptr->DIRECTIO |= SPI_DIRECTIO_SCLK_OE_MASK; - break; - case cs_pin: - ptr->DIRECTIO |= SPI_DIRECTIO_CS_OE_MASK; - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t spi_directio_disable_output(SPI_Type *ptr, spi_directio_pin_t pin) -{ - hpm_stat_t stat = status_success; - switch (pin) { - case hold_pin: - ptr->DIRECTIO &= ~SPI_DIRECTIO_HOLD_OE_MASK; - break; - case wp_pin: - ptr->DIRECTIO &= ~SPI_DIRECTIO_WP_OE_MASK; - break; - case miso_pin: - ptr->DIRECTIO &= ~SPI_DIRECTIO_MISO_OE_MASK; - break; - case mosi_pin: - ptr->DIRECTIO &= ~SPI_DIRECTIO_MOSI_OE_MASK; - break; - case sclk_pin: - ptr->DIRECTIO &= ~SPI_DIRECTIO_SCLK_OE_MASK; - break; - case cs_pin: - ptr->DIRECTIO &= ~SPI_DIRECTIO_CS_OE_MASK; - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -hpm_stat_t spi_directio_write(SPI_Type *ptr, spi_directio_pin_t pin, bool high) -{ - hpm_stat_t stat = status_success; - switch (pin) { - case hold_pin: - (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_HOLD_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_HOLD_O_MASK); - break; - case wp_pin: - (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_WP_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_WP_O_MASK); - break; - case miso_pin: - (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_MISO_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_MISO_O_MASK); - break; - case mosi_pin: - (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_MOSI_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_MOSI_O_MASK); - break; - case sclk_pin: - (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_SCLK_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_SCLK_O_MASK); - break; - case cs_pin: - (high == true) ? (ptr->DIRECTIO |= SPI_DIRECTIO_CS_O_MASK) : (ptr->DIRECTIO &= ~SPI_DIRECTIO_CS_O_MASK); - break; - default: - stat = status_invalid_argument; - break; - } - return stat; -} - -uint8_t spi_directio_read(SPI_Type *ptr, spi_directio_pin_t pin) -{ - uint8_t io_sta = 0; - switch (pin) { - case hold_pin: - io_sta = SPI_DIRECTIO_HOLD_I_GET(ptr->DIRECTIO); - break; - case wp_pin: - io_sta = SPI_DIRECTIO_WP_I_GET(ptr->DIRECTIO); - break; - case miso_pin: - io_sta = SPI_DIRECTIO_MISO_I_GET(ptr->DIRECTIO); - break; - case mosi_pin: - io_sta = SPI_DIRECTIO_MOSI_I_GET(ptr->DIRECTIO); - break; - case sclk_pin: - io_sta = SPI_DIRECTIO_SCLK_I_GET(ptr->DIRECTIO); - break; - case cs_pin: - io_sta = SPI_DIRECTIO_CS_I_GET(ptr->DIRECTIO); - break; - default: - break; - } - return io_sta; -} -#endif - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c deleted file mode 100644 index ffb838dda68..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tamp_drv.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_tamp_drv.h" - -void tamp_init_ch_config(TAMP_Type *ptr, uint8_t ch, tamper_ch_config_t *config) -{ - ch >>= 1u; - ptr->TAMP[ch].CONTROL = TAMP_TAMP_CONTROL_BYPASS_SET(config->filter_bypass) - | TAMP_TAMP_CONTROL_FILTER_SET(config->filter_len) - | TAMP_TAMP_CONTROL_VALUE_SET(config->expect_high_level) - | TAMP_TAMP_CONTROL_SPEED_SET(config->speed) - | TAMP_TAMP_CONTROL_RECOVER_SET(config->auto_recover) - | TAMP_TAMP_CONTROL_ACTIVE_SET(config->active_mode) - | TAMP_TAMP_CONTROL_ENABLE_SET(config->enable); - ptr->TAMP[ch].POLY = config->poly; - ptr->TAMP[ch].LFSR = config->lfsr; -} - -void tamp_get_default_ch_config(TAMP_Type *ptr, tamper_ch_config_t *config) -{ - (void) ptr; - config->enable = false; - config->active_mode = false; - config->expect_high_level = false; - config->filter_bypass = false; - config->filter_len = filter_len_128_cycles; - config->speed = spd_1_time_per_sec; - config->auto_recover = false; - config->poly = 0; - config->lfsr = 0; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c deleted file mode 100644 index 3db13a698ed..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsns_drv.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_tsns_drv.h" - -void tsns_configure_low_limit_event(TSNS_Type *ptr, int32_t low, tsns_event_t e) -{ - switch (e) { - case tsns_event_irq: - tsns_set_irq_threshold_low(ptr, low); - ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; - break; - case tsns_event_reset: - tsns_set_reset_threshold_low(ptr, low); - ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; - break; - default: - assert(NULL); - } -} - -void tsns_configure_high_limit_event(TSNS_Type *ptr, int32_t high, tsns_event_t e) -{ - switch (e) { - case tsns_event_irq: - tsns_set_irq_threshold_high(ptr, high); - ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK; - break; - case tsns_event_reset: - tsns_set_reset_threshold_high(ptr, high); - ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK; - break; - default: - assert(NULL); - } -} - -void tsns_configure_limit_event(TSNS_Type *ptr, int32_t high, int32_t low, tsns_event_t e) -{ - assert(high > low); - switch (e) { - case tsns_event_irq: - tsns_config_irq_threshold(ptr, high, low); - ptr->CONFIG |= TSNS_CONFIG_IRQ_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; - break; - case tsns_event_reset: - tsns_config_reset_threshold(ptr, high, low); - ptr->CONFIG |= TSNS_CONFIG_RST_EN_MASK | TSNS_CONFIG_COMPARE_MAX_EN_MASK | TSNS_CONFIG_COMPARE_MIN_EN_MASK; - break; - default: - assert(NULL); - } -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c deleted file mode 100644 index 0f1be9ac22b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_tsw_drv.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_tsw_drv.h" -#include "hpm_swap.h" - -hpm_stat_t tsw_ep_set_mdio_config(TSW_Type *ptr, uint8_t port, uint8_t clk_div) -{ - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_CFG = TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK | TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(clk_div); - - return status_success; -} - -hpm_stat_t tsw_ep_mdio_read(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint16_t *data) -{ - if (data == NULL) { - return status_invalid_argument; - } - - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_CTRL = TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(MAC_MDIO_CTRL_OP_RD) - | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(phy_addr) - | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(reg_addr) - | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(1); - - do { - - } while (TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_CTRL) == 0); - - - *data = TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET(ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_RD_DATA); - - return status_success; -} - -hpm_stat_t tsw_ep_mdio_write(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint16_t data) -{ - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_WR_DATA = data; - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_CTRL = TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(MAC_MDIO_CTRL_OP_WR) - | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(phy_addr) - | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(reg_addr) - | TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(1); - - do { - - } while (TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MDIO_CTRL) == 0); - - return status_success; -} - -hpm_stat_t tsw_ep_enable_mac_ctrl(TSW_Type *ptr, uint8_t port, uint8_t mac_type, bool enable) -{ - uint32_t temp; - - temp = ptr->TSNPORT[port].MAC[mac_type].MAC_MAC_CTRL; - temp &= ~(TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK | TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK); - temp |= TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET(enable) | TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET(enable); - - ptr->TSNPORT[port].MAC[mac_type].MAC_MAC_CTRL = temp; - - if (!enable) { - do { - temp = ptr->TSNPORT[port].MAC[mac_type].MAC_MAC_CTRL; - } while (TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(temp) || TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(temp)); - } - - return status_success; -} - -hpm_stat_t tsw_ep_set_mac_addr(TSW_Type *ptr, uint8_t port, uint8_t *mac_addr, bool promisc) -{ - uint32_t temp; - - if (mac_addr == NULL) { - return status_invalid_argument; - } - - /* MAC must be disabled when changing mode */ - temp = ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MAC_CTRL; - if (TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(temp) || TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(temp)) { - return status_fail; - } - - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MACADDR_L = MAC_LO(mac_addr); - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MACADDR_H = MAC_HI(mac_addr) | TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET(promisc); - - return status_success; -} - -hpm_stat_t tsw_ep_set_mac_mode(TSW_Type *ptr, uint8_t port, uint8_t gmii) -{ - uint32_t temp; - - /* MAC must be disabled when changing mode */ - temp = ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MAC_CTRL; - if (TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(temp) || TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(temp)) { - return status_fail; - } - - temp &= ~(TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK | TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK | TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK); - temp &= ~TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK; - - temp |= TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET(1) - | TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET(1) - | TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET(gmii); - - ptr->TSNPORT[port].MAC[TSW_RXFIFO_E1].MAC_MAC_CTRL = temp; - - return status_success; -} - -/* data: the start address of data buffer must be aligned with 4 bytes */ -/* length in bytes */ -hpm_stat_t tsw_send(TSW_Type *ptr, uint32_t *buffer, uint32_t length, uint8_t id) -{ - uint32_t resp; - - /* Enable DMA: Write MM2S DMA CR (Run=1, SOE=0, IRQEN=0) */ - ptr->MM2S_DMA_CR |= TSW_MM2S_DMA_CR_RUN_MASK | TSW_MM2S_DMA_CR_MXLEN_SET(0xff); - - /* Set ADDRL */ - ptr->MM2S_ADDRLO = (uint32_t)buffer; - - /* Set Length */ - ptr->MM2S_LENGTH = length; - - /* Set Ctrl */ - ptr->MM2S_CTRL &= ~TSW_MM2S_CTRL_ID_MASK; - ptr->MM2S_CTRL |= TSW_MM2S_CTRL_GO_MASK | TSW_MM2S_CTRL_ID_SET(id); - - /* Wait for DMA to finish transmission */ - do { - - } while (TSW_MM2S_DMA_SR_RBUFE_GET(ptr->MM2S_DMA_SR)); - - /* Read response */ - resp = ptr->MM2S_RESP; - - if (TSW_MM2S_RESP_ID_GET(resp) == id) { - - - /* Check decode error */ - if (TSW_MM2S_RESP_DECERR_GET(resp)) { - - } - - /* check slave error */ - if (TSW_MM2S_RESP_SLVERR_GET(resp)) { - - } - } - - return status_success; -} - -hpm_stat_t tsw_recv_setup(TSW_Type *ptr, uint32_t *buffer, uint32_t length, uint8_t id) -{ - /* Enable DMA-CTRL: Write S2MM_DMA_CR (Run=1, SOE=0, IRQEN=1) */ - ptr->S2MM_DMA_CR &= ~TSW_S2MM_DMA_CR_SOE_MASK; /* SOE=0 */ - - ptr->S2MM_DMA_CR |= TSW_S2MM_DMA_CR_RUN_MASK; - - /* Set ADDRL */ - ptr->S2MM_ADDRLO = (uint32_t)buffer; - - /* Set Length */ - ptr->S2MM_LENGTH = length; - - /* Set Ctrl */ - ptr->S2MM_CTRL &= ~TSW_S2MM_CTRL_ID_MASK; - ptr->S2MM_CTRL |= TSW_S2MM_CTRL_GO_MASK | TSW_S2MM_CTRL_ID_SET(id); - - return status_success; -} - -uint32_t tsw_recv(TSW_Type *ptr, uint32_t *buffer, uint32_t length, uint8_t id) -{ - uint32_t resp; - - /* Wait for DMA to finish transmission */ - do { - - } while (TSW_S2MM_DMA_SR_RBUFE_GET(ptr->S2MM_DMA_SR)); - - HPM_TSW->S2MM_DMA_SR = TSW_S2MM_DMA_SR_IRQ_MASK; - - /* Read response */ - resp = ptr->S2MM_RESP; - - if (TSW_S2MM_RESP_ID_GET(resp) == id) { - - /* Check decode error */ - if (TSW_S2MM_RESP_DECERR_GET(resp)) { - /* printf("decode error\n"); */ - } - - /* check slave error */ - if (TSW_S2MM_RESP_SLVERR_GET(resp)) { - /* printf("slave error\n"); */ - } - } - - HPM_TSW->S2MM_CTRL |= TSW_S2MM_CTRL_GO_MASK; - - return ptr->S2MM_LENGTH; -} - -void tsw_mac_lookup_bypass(TSW_Type *ptr, uint8_t dst_port) -{ - ptr->LU_MAIN_BYPASS &= ~TSW_LU_MAIN_BYPASS_DEST_MASK; - ptr->LU_MAIN_BYPASS |= TSW_LU_MAIN_BYPASS_HIT_MASK | TSW_LU_MAIN_BYPASS_DEST_SET(dst_port); - ptr->LU_MAIN_CTRL |= TSW_LU_MAIN_CTRL_BYP_EN_MASK; -} - -void tsw_set_cam_vlan_port(TSW_Type *ptr) -{ - ptr->APB2AXI_CAM_REQDATA_1 = 0x0f; - ptr->APB2AXI_CAM_REQDATA_0 = (1 << 16) /* VID = 1 */ - | (1 << 8) /* 1: Set one VLAN_PORT entry */ - | (1 << 0); /* CAM APB2AXIS channel selection. Always 1 for writing to VLAN_PORT table. */ - -} - -/** - * speed: 00 1000mbps, 11 100mbps, 10 10mpbs - * itf: 000 MII; 001 RGMII; 100 RMII - */ -void tsw_port_gpr(TSW_Type *ptr, uint8_t port, uint8_t speed, uint8_t itf, uint8_t tx_dly, uint8_t rx_dly) -{ - ptr->TSNPORT[port].GPR_CTRL0 = TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET(rx_dly) | TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET(tx_dly); - ptr->TSNPORT[port].GPR_CTRL2 = TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET(speed) | TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET(itf); -} - -void tsw_set_lookup_table(TSW_Type *ptr, uint16_t entry_num, uint8_t dest_port, uint64_t dest_mac) -{ - uint64_t dest_mac_temp; - - /* Create a new ALMEM entry. This will specify what will be done with those detected frames */ - if (TSW_APB2AXIS_ALMEM_STS_RDY_GET(ptr->APB2AXIS_ALMEM_STS)) { - - ptr->APB2AXIS_ALMEM_REQDATA_1 = TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET(1) | TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET(entry_num); - - /* set forward to destination port, use PCP field, UTAG 1 and trigger the interface for sending the data */ - ptr->APB2AXIS_ALMEM_REQDATA_0 = TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET(1) | - TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET(0) | - TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET(0) | - TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET(0) | - TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET(dest_port); - } - - /* Create a new CAM entry */ - dest_mac_temp = __bswapdi2(dest_mac) >> 16; - - ptr->APB2AXI_CAM_REQDATA_2 = TSW_APB2AXI_CAM_REQDATA_2_VID_SET(1) | TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET((dest_mac_temp >> 32)); - ptr->APB2AXI_CAM_REQDATA_1 = TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET(dest_mac_temp); - ptr->APB2AXI_CAM_REQDATA_0 = TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET(entry_num) | - TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET(1) | /* Set one DEST_MAC/VLAN_ID entry */ - TSW_APB2AXI_CAM_REQDATA_0_CH_SET(0); /* CAM APB2AXIS channel selection. Always 0 for writing to DEST_MAC/VLAN_ID */ - - - /* Add a new VLAN_PORT entry (VID 1) */ - ptr->APB2AXI_CAM_REQDATA_1 = 0x0f; - ptr->APB2AXI_CAM_REQDATA_0 = (1 << 16) /* VID = 1 */ - | (1 << 8) /* 1: Set one VLAN_PORT entry */ - | (1 << 0); /* CAM APB2AXIS channel selection. Always 1 for writing to VLAN_PORT table. */ - -} - -void tsw_set_internal_frame_action(TSW_Type *ptr, uint8_t dest_port) -{ - ptr->LU_MAIN_INTF_ACTION &= ~TSW_LU_MAIN_INTF_ACTION_DEST_MASK; - ptr->LU_MAIN_INTF_ACTION |= TSW_LU_MAIN_INTF_ACTION_DEST_SET(dest_port); -} - -void tsw_set_broadcast_frame_action(TSW_Type *ptr, uint8_t dest_port) -{ - ptr->LU_MAIN_BC_ACTION &= ~TSW_LU_MAIN_BC_ACTION_DEST_MASK; - ptr->LU_MAIN_BC_ACTION |= TSW_LU_MAIN_BC_ACTION_DEST_SET(dest_port); -} - -void tsw_set_unknown_frame_action(TSW_Type *ptr, uint8_t dest_port) -{ - ptr->LU_MAIN_NN_ACTION &= ~TSW_LU_MAIN_NN_ACTION_DEST_MASK; - ptr->LU_MAIN_NN_ACTION |= TSW_LU_MAIN_NN_ACTION_DEST_SET(dest_port); -} - -void tsw_clear_cam(TSW_Type *ptr) -{ - ptr->LU_MAIN_HITMEM &= ~TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK; - ptr->LU_MAIN_HITMEM |= TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK; -} - -void tsw_enable_store_forward_mode(TSW_Type *ptr, uint8_t port) -{ - ptr->TSNPORT[port].RXFIFO[TSW_RXFIFO_E1].SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG |= TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK; -} - -void tsw_disable_store_forward_mode(TSW_Type *ptr, uint8_t port) -{ - ptr->TSNPORT[port].RXFIFO[TSW_RXFIFO_E1].SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG &= ~TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK; -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c deleted file mode 100644 index 72f4a3e7832..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_uart_drv.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_uart_drv.h" - -#define HPM_UART_DRV_RETRY_COUNT (5000U) -#define HPM_UART_MINIMUM_BAUDRATE (200U) - -#ifndef HPM_UART_BAUDRATE_TOLERANCE -#define HPM_UART_BAUDRATE_TOLERANCE (3) -#endif - -#define HPM_UART_OSC_MAX (32U) -#define HPM_UART_OSC_MIN (8U) -#define HPM_UART_BAUDRATE_DIV_MAX (0xFFFFU) -#define HPM_UART_BAUDRATE_DIV_MIN (1U) - -#ifndef UART_SOC_OVERSAMPLE_MAX -#define UART_SOC_OVERSAMPLE_MAX HPM_UART_OSC_MAX -#endif - -void uart_default_config(UART_Type *ptr, uart_config_t *config) -{ - (void) ptr; - config->baudrate = 115200; - config->word_length = word_length_8_bits; - config->parity = parity_none; - config->num_of_stop_bits = stop_bits_1; - config->fifo_enable = true; - config->rx_fifo_level = uart_rx_fifo_trg_not_empty; - config->tx_fifo_level = uart_tx_fifo_trg_not_full; - config->dma_enable = false; - config->modem_config.auto_flow_ctrl_en = false; - config->modem_config.loop_back_en = false; - config->modem_config.set_rts_high = false; -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - config->rxidle_config.detect_enable = false; - config->rxidle_config.detect_irq_enable = false; - config->rxidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; - config->rxidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ -#endif - /* if have 9bit_mode function, it's has be tx_idle function */ -#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) - config->txidle_config.detect_enable = false; - config->txidle_config.detect_irq_enable = false; - config->txidle_config.idle_cond = uart_rxline_idle_cond_rxline_logic_one; - config->txidle_config.threshold = 10; /* 10-bit for typical UART configuration (8-N-1) */ -#endif -#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1) - config->rx_enable = true; -#endif -} - -static bool uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, uint16_t *div_out, uint8_t *osc_out) -{ - uint16_t div, osc, delta; - float tmp; - if ((div_out == NULL) || (!freq) || (!baudrate) - || (baudrate < HPM_UART_MINIMUM_BAUDRATE) - || (freq / HPM_UART_BAUDRATE_DIV_MIN < baudrate * HPM_UART_OSC_MIN) - || (freq / HPM_UART_BAUDRATE_DIV_MAX > (baudrate * HPM_UART_OSC_MAX))) { - return 0; - } - - tmp = (float) freq / baudrate; - - for (osc = HPM_UART_OSC_MIN; osc <= UART_SOC_OVERSAMPLE_MAX; osc += 2) { - /* osc range: HPM_UART_OSC_MIN - UART_SOC_OVERSAMPLE_MAX, even number */ - delta = 0; - div = (uint16_t)(tmp / osc); - if (div < HPM_UART_BAUDRATE_DIV_MIN) { - /* invalid div */ - continue; - } - if (div * osc > tmp) { - delta = (uint16_t)(div * osc - tmp); - } else if (div * osc < tmp) { - delta = (uint16_t)(tmp - div * osc); - } - if (delta && ((delta * 100 / tmp) > HPM_UART_BAUDRATE_TOLERANCE)) { - continue; - } else { - *div_out = div; - *osc_out = (osc == HPM_UART_OSC_MAX) ? 0 : osc; /* osc == 0 in bitfield, oversample rate is 32 */ - return true; - } - } - return false; -} - -hpm_stat_t uart_init(UART_Type *ptr, uart_config_t *config) -{ - uint32_t tmp; - uint8_t osc; - uint16_t div; - - /* disable all interrupts */ - ptr->IER = 0; - /* Set DLAB to 1 */ - ptr->LCR |= UART_LCR_DLAB_MASK; - - if (!uart_calculate_baudrate(config->src_freq_in_hz, config->baudrate, &div, &osc)) { - return status_uart_no_suitable_baudrate_parameter_found; - } - - ptr->OSCR = (ptr->OSCR & ~UART_OSCR_OSC_MASK) - | UART_OSCR_OSC_SET(osc); - ptr->DLL = UART_DLL_DLL_SET(div >> 0); - ptr->DLM = UART_DLM_DLM_SET(div >> 8); - - /* DLAB bit needs to be cleared once baudrate is configured */ - tmp = ptr->LCR & (~UART_LCR_DLAB_MASK); - - tmp &= ~(UART_LCR_SPS_MASK | UART_LCR_EPS_MASK | UART_LCR_PEN_MASK); - switch (config->parity) { - case parity_none: - break; - case parity_odd: - tmp |= UART_LCR_PEN_MASK; - break; - case parity_even: - tmp |= UART_LCR_PEN_MASK | UART_LCR_EPS_MASK; - break; - case parity_always_1: - tmp |= UART_LCR_PEN_MASK | UART_LCR_SPS_MASK; - break; - case parity_always_0: - tmp |= UART_LCR_EPS_MASK | UART_LCR_PEN_MASK - | UART_LCR_SPS_MASK; - break; - default: - /* invalid configuration */ - return status_invalid_argument; - } - - tmp &= ~(UART_LCR_STB_MASK | UART_LCR_WLS_MASK); - switch (config->num_of_stop_bits) { - case stop_bits_1: - break; - case stop_bits_1_5: - tmp |= UART_LCR_STB_MASK; - break; - case stop_bits_2: - if (config->word_length < word_length_6_bits) { - /* invalid configuration */ - return status_invalid_argument; - } - tmp |= UART_LCR_STB_MASK; - break; - default: - /* invalid configuration */ - return status_invalid_argument; - } - - ptr->LCR = tmp | UART_LCR_WLS_SET(config->word_length); - -#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1) - /* reset TX and RX fifo */ - ptr->FCRR = UART_FCRR_TFIFORST_MASK | UART_FCRR_RFIFORST_MASK; - /* Enable FIFO */ - ptr->FCRR = UART_FCRR_FIFOT4EN_MASK - | UART_FCRR_FIFOE_SET(config->fifo_enable) - | UART_FCRR_TFIFOT4_SET(config->tx_fifo_level) - | UART_FCRR_RFIFOT4_SET(config->rx_fifo_level) - | UART_FCRR_DMAE_SET(config->dma_enable); - -#else - /* reset TX and RX fifo */ - ptr->FCR = UART_FCR_TFIFORST_MASK | UART_FCR_RFIFORST_MASK; - /* Enable FIFO */ - tmp = UART_FCR_FIFOE_SET(config->fifo_enable) - | UART_FCR_TFIFOT_SET(config->tx_fifo_level) - | UART_FCR_RFIFOT_SET(config->rx_fifo_level) - | UART_FCR_DMAE_SET(config->dma_enable); - ptr->FCR = tmp; - /* store FCR register value */ - ptr->GPR = tmp; -#endif - - uart_modem_config(ptr, &config->modem_config); - -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) - uart_init_rxline_idle_detection(ptr, config->rxidle_config); -#endif -#if defined(HPM_IP_FEATURE_UART_RX_EN) && (HPM_IP_FEATURE_UART_RX_EN == 1) - if (config->rx_enable) { - ptr->IDLE_CFG |= UART_IDLE_CFG_RXEN_MASK; - } -#endif - return status_success; -} - -hpm_stat_t uart_set_baudrate(UART_Type *ptr, uint32_t baudrate, uint32_t src_clock_hz) -{ - uint8_t osc; - uint16_t div; - - /* Set DLAB to 1 */ - ptr->LCR |= UART_LCR_DLAB_MASK; - - if (!uart_calculate_baudrate(src_clock_hz, baudrate, &div, &osc)) { - return status_uart_no_suitable_baudrate_parameter_found; - } - - ptr->OSCR = (ptr->OSCR & ~UART_OSCR_OSC_MASK) | UART_OSCR_OSC_SET(osc); - ptr->DLL = UART_DLL_DLL_SET(div >> 0); - ptr->DLM = UART_DLM_DLM_SET(div >> 8); - - /* DLAB bit needs to be cleared once baudrate is configured */ - ptr->LCR &= ~UART_LCR_DLAB_MASK; - - return status_success; -} - -hpm_stat_t uart_send_byte(UART_Type *ptr, uint8_t c) -{ - uint32_t retry = 0; - - while (!(ptr->LSR & UART_LSR_THRE_MASK)) { - if (retry > HPM_UART_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_UART_DRV_RETRY_COUNT) { - return status_timeout; - } - - ptr->THR = UART_THR_THR_SET(c); - return status_success; -} - -hpm_stat_t uart_flush(UART_Type *ptr) -{ - uint32_t retry = 0; - - while (!(ptr->LSR & UART_LSR_TEMT_MASK)) { - if (retry > HPM_UART_DRV_RETRY_COUNT) { - break; - } - retry++; - } - if (retry > HPM_UART_DRV_RETRY_COUNT) { - return status_timeout; - } - - return status_success; -} - -hpm_stat_t uart_receive_byte(UART_Type *ptr, uint8_t *byte) -{ - uint32_t retry = 0; - - while (!(ptr->LSR & UART_LSR_DR_MASK)) { - if (retry > HPM_UART_DRV_RETRY_COUNT) { - break; - } - retry++; - } - - if (retry > HPM_UART_DRV_RETRY_COUNT) { - return status_timeout; - } - - *byte = ptr->RBR & UART_RBR_RBR_MASK; - return status_success; -} - -hpm_stat_t uart_try_receive_byte(UART_Type *ptr, uint8_t *byte) -{ - if (!(ptr->LSR & UART_LSR_DR_MASK)) { - return status_fail; - } else { - *byte = ptr->RBR & UART_RBR_RBR_MASK; - return status_success; - } -} - -void uart_set_signal_level(UART_Type *ptr, uart_signal_t signal, uart_signal_level_t level) -{ - if (level == uart_signal_level_low) { - ptr->MCR = (ptr->MCR | signal); - } else { - ptr->MCR = (ptr->MCR & ~signal); - } -} - -hpm_stat_t uart_receive_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte) -{ - for (uint32_t i = 0; i < size_in_byte; i++) { - if (status_success != uart_receive_byte(ptr, source + i)) { - return status_fail; - } - } - return status_success; -} - -hpm_stat_t uart_send_data(UART_Type *ptr, uint8_t *source, uint32_t size_in_byte) -{ - for (uint32_t i = 0; i < size_in_byte; i++) { - if (status_success != uart_send_byte(ptr, *(source + i))) { - return status_fail; - } - } - return status_success; -} - - -#if defined(HPM_IP_FEATURE_UART_RX_IDLE_DETECT) && (HPM_IP_FEATURE_UART_RX_IDLE_DETECT == 1) -hpm_stat_t uart_init_rxline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t rxidle_config) -{ - ptr->IDLE_CFG &= ~(UART_IDLE_CFG_RX_IDLE_EN_MASK - | UART_IDLE_CFG_RX_IDLE_THR_MASK - | UART_IDLE_CFG_RX_IDLE_COND_MASK); - ptr->IDLE_CFG |= UART_IDLE_CFG_RX_IDLE_EN_SET(rxidle_config.detect_enable) - | UART_IDLE_CFG_RX_IDLE_THR_SET(rxidle_config.threshold) - | UART_IDLE_CFG_RX_IDLE_COND_SET(rxidle_config.idle_cond); - - if (rxidle_config.detect_irq_enable) { - uart_enable_irq(ptr, uart_intr_rx_line_idle); - } else { - uart_disable_irq(ptr, uart_intr_rx_line_idle); - } - - return status_success; -} -#endif - -/* if have 9bit_mode function, it's has be tx_idle function */ -#if defined(HPM_IP_FEATURE_UART_9BIT_MODE) && (HPM_IP_FEATURE_UART_9BIT_MODE == 1) -hpm_stat_t uart_init_txline_idle_detection(UART_Type *ptr, uart_rxline_idle_config_t txidle_config) -{ - ptr->IDLE_CFG &= ~(UART_IDLE_CFG_TX_IDLE_EN_MASK - | UART_IDLE_CFG_TX_IDLE_THR_MASK - | UART_IDLE_CFG_TX_IDLE_COND_MASK); - ptr->IDLE_CFG |= UART_IDLE_CFG_TX_IDLE_EN_SET(txidle_config.detect_enable) - | UART_IDLE_CFG_TX_IDLE_THR_SET(txidle_config.threshold) - | UART_IDLE_CFG_TX_IDLE_COND_SET(txidle_config.idle_cond); - - if (txidle_config.detect_irq_enable) { - uart_enable_irq(ptr, uart_intr_tx_line_idle); - } else { - uart_disable_irq(ptr, uart_intr_tx_line_idle); - } - - return status_success; -} -#endif - -#if defined(HPM_IP_FEATURE_UART_TRIG_MODE) && (HPM_IP_FEATURE_UART_TRIG_MODE == 1) -void uart_config_transfer_trig_mode(UART_Type *ptr, uart_trig_config_t *config) -{ - ptr->MOTO_CFG = UART_MOTO_CFG_TXSTP_BITS_SET(config->stop_bit_len) - | UART_MOTO_CFG_HWTRG_EN_SET(config->hardware_trig) - | UART_MOTO_CFG_TRG_MODE_SET(config->trig_mode) - | UART_MOTO_CFG_TRG_CLR_RFIFO_SET(config->trig_clr_rxfifo) - | UART_MOTO_CFG_TXSTOP_INSERT_SET(config->en_stop_bit_insert); -} -#endif - -/* fifo control register(FCR) is WO access, if support FCCR register, it is RW access. */ -void uart_config_fifo_ctrl(UART_Type *ptr, uart_fifo_ctrl_t *ctrl) -{ -#if defined(HPM_IP_FEATURE_UART_FINE_FIFO_THRLD) && (HPM_IP_FEATURE_UART_FINE_FIFO_THRLD == 1) - ptr->FCRR = UART_FCRR_FIFOT4EN_MASK - | UART_FCRR_TFIFOT4_SET(ctrl->tx_fifo_level) - | UART_FCRR_RFIFOT4_SET(ctrl->rx_fifo_level) - | UART_FCRR_DMAE_SET(ctrl->dma_enable) - | UART_FCRR_TFIFORST_SET(ctrl->reset_tx_fifo) - | UART_FCRR_RFIFORST_SET(ctrl->reset_rx_fifo) - | UART_FCRR_FIFOE_SET(ctrl->fifo_enable); -#else - ptr->FCR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) - | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) - | UART_FCR_TFIFORST_SET(ctrl->reset_tx_fifo) - | UART_FCR_RFIFORST_SET(ctrl->reset_rx_fifo) - | UART_FCR_DMAE_SET(ctrl->dma_enable) - | UART_FCR_FIFOE_SET(ctrl->fifo_enable); - /* store FCR to GPR */ - ptr->GPR = UART_FCR_TFIFOT_SET(ctrl->tx_fifo_level) - | UART_FCR_RFIFOT_SET(ctrl->rx_fifo_level) - | UART_FCR_DMAE_SET(ctrl->dma_enable) - | UART_FCR_FIFOE_SET(ctrl->fifo_enable); -#endif -} \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c deleted file mode 100644 index 5490c46c513..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_usb_drv.c +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -/*--------------------------------------------------------------------- - * Include - *--------------------------------------------------------------------- - */ -#include "hpm_usb_drv.h" -#include "hpm_misc.h" -#include "hpm_soc_feature.h" -#include "hpm_common.h" -/*--------------------------------------------------------------------- - * Macro Enum Declaration - *--------------------------------------------------------------------- - */ - -/* ENDPTCTRL */ -enum { - ENDPTCTRL_STALL = HPM_BITSMASK(1, 0), - ENDPTCTRL_TYPE = HPM_BITSMASK(3, 2), - ENDPTCTRL_TOGGLE_INHIBIT = HPM_BITSMASK(1, 5), - ENDPTCTRL_TOGGLE_RESET = HPM_BITSMASK(1, 6), - ENDPTCTRL_ENABLE = HPM_BITSMASK(1, 7), -}; - -/*--------------------------------------------------------------------- - * Internal API - *--------------------------------------------------------------------- - */ - -/* De-initialize USB phy */ -static void usb_phy_deinit(USB_Type *ptr) -{ - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ - - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ - - ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clear cfg_rst_n */ - - ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* clear otg_suspendm */ -} - -/*--------------------------------------------------------------------- - * Driver API - *--------------------------------------------------------------------- - */ -/* Initialize USB phy */ -void usb_phy_init(USB_Type *ptr) -{ - uint32_t status; - - usb_phy_enable_dp_dm_pulldown(ptr); - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* set otg_utmi_reset_sw for naneng usbphy */ - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* clr otg_utmi_suspend_m for naneng usbphy */ - ptr->PHY_CTRL1 &= ~USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* clr cfg_rst_n */ - - do { - status = USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(ptr->OTG_CTRL0); /* wait for reset status */ - } while (status == 0); - - ptr->OTG_CTRL0 |= USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK; /* set otg_utmi_suspend_m for naneng usbphy */ - - for (volatile uint32_t i = 0; i < USB_PHY_INIT_DELAY_COUNT; i++) { - (void)ptr->PHY_CTRL1; /* used for delay */ - } - - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK; /* Disable dp/dm wakeup */ - - ptr->OTG_CTRL0 &= ~USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK; /* clear otg_utmi_reset_sw for naneng usbphy */ - - /* otg utmi clock detection */ - ptr->PHY_STATUS |= USB_PHY_STATUS_UTMI_CLK_VALID_MASK; /* write 1 to clear valid status */ - do { - status = USB_PHY_STATUS_UTMI_CLK_VALID_GET(ptr->PHY_STATUS); /* get utmi clock status */ - } while (status == 0); - - ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK; /* set cfg_rst_n */ - - ptr->PHY_CTRL1 |= USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK; /* set otg_suspendm */ -} - -void usb_dcd_bus_reset(USB_Type *ptr, uint16_t ep0_max_packet_size) -{ - (void) ep0_max_packet_size; - /* The reset value for all endpoint types is the control endpoint. If one endpoint - * direction is enabled and the paired endpoint of opposite direction is disabled, then the - * endpoint type of the unused direction must be changed from the control type to any other - * type (e.g. bulk). Leaving an un-configured endpoint control will cause undefined behavior - * for the data PID tracking on the active endpoint. - */ - - for (uint32_t i = 1; i < USB_SOC_DCD_MAX_ENDPOINT_COUNT; i++) { - ptr->ENDPTCTRL[i] = USB_ENDPTCTRL_TXT_SET(usb_xfer_bulk) | USB_ENDPTCTRL_RXT_SET(usb_xfer_bulk); - } - - /* Clear All Registers */ - ptr->ENDPTNAK = ptr->ENDPTNAK; - ptr->ENDPTNAKEN = 0; - ptr->USBSTS = ptr->USBSTS; - ptr->ENDPTSETUPSTAT = ptr->ENDPTSETUPSTAT; - ptr->ENDPTCOMPLETE = ptr->ENDPTCOMPLETE; - - while (ptr->ENDPTPRIME) { - } - ptr->ENDPTFLUSH = 0xFFFFFFFF; - while (ptr->ENDPTFLUSH) { - } -} - -void usb_dcd_init(USB_Type *ptr) -{ - /* Initialize USB phy */ - usb_phy_init(ptr); - - /* Reset controller */ - ptr->USBCMD |= USB_USBCMD_RST_MASK; - while (USB_USBCMD_RST_GET(ptr->USBCMD)) { - } - - /* Set mode to device, must be set immediately after reset */ - ptr->USBMODE &= ~USB_USBMODE_CM_MASK; - ptr->USBMODE |= USB_USBMODE_CM_SET(2); - - /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ - ptr->USBMODE &= ~USB_USBMODE_SLOM_MASK; - - /* Set the endian */ - ptr->USBMODE &= ~USB_USBMODE_ES_MASK; - - /* TODO Force fullspeed on non-highspeed port */ - /* ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; */ - - /* Set parallel interface signal */ - ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; - - /* Set parallel transceiver width */ - ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; - -#ifdef CONFIG_USB_DEVICE_FS - /* Set usb forced to full speed mode */ - ptr->PORTSC1 |= USB_PORTSC1_PFSC_MASK; -#endif - - /* Not use interrupt threshold. */ - ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; - - /* Enable VBUS discharge */ - ptr->OTGSC |= USB_OTGSC_VD_MASK; -} - -void usb_dcd_deinit(USB_Type *ptr) -{ - /* Stop */ - ptr->USBCMD &= ~USB_USBCMD_RS_MASK; - - /* Reset controller */ - ptr->USBCMD |= USB_USBCMD_RST_MASK; - while (USB_USBCMD_RST_GET(ptr->USBCMD)) { - } - - /* De-initialize USB phy */ - usb_phy_deinit(ptr); - - /* Reset endpoint list address register */ - ptr->ENDPTLISTADDR = 0; - - /* Reset status register */ - ptr->USBSTS = ptr->USBSTS; - - /* Reset interrupt enable register */ - ptr->USBINTR = 0; -} - -/* Connect by enabling internal pull-up resistor on D+/D- */ -void usb_dcd_connect(USB_Type *ptr) -{ - ptr->USBCMD |= USB_USBCMD_RS_MASK; -} - -/* Disconnect by disabling internal pull-up resistor on D+/D- */ -void usb_dcd_disconnect(USB_Type *ptr) -{ - /* Stop */ - ptr->USBCMD &= ~USB_USBCMD_RS_MASK; - - /* Pullup DP to make the phy switch into full speed mode */ - ptr->USBCMD |= USB_USBCMD_RS_MASK; - - /* Clear the sof flag */ - ptr->USBSTS |= USB_USBSTS_SRI_MASK; - - /* Wait a SOF (It will not be a dead loop even usb cable is not connected.) */ - while (USB_USBSTS_SRI_GET(ptr->USBSTS) == 0) { - } - - /* Disconnect */ - ptr->USBCMD &= ~USB_USBCMD_RS_MASK; -} - -/*--------------------------------------------------------------------- - * Endpoint API - *--------------------------------------------------------------------- - */ -void usb_dcd_edpt_open(USB_Type *ptr, usb_endpoint_config_t *config) -{ - uint8_t const epnum = config->ep_addr & 0x0f; - uint8_t const dir = (config->ep_addr & 0x80) >> 7; - - /* Enable EP Control */ - uint32_t temp = ptr->ENDPTCTRL[epnum]; - temp &= ~((0x03 << 2) << (dir ? 16 : 0)); - temp |= ((config->xfer << 2) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET) << (dir ? 16 : 0); - ptr->ENDPTCTRL[epnum] = temp; -} - -uint8_t usb_dcd_edpt_get_type(USB_Type *ptr, uint8_t ep_addr) -{ - uint8_t const epnum = ep_addr & 0x0f; - uint8_t const dir = (ep_addr & 0x80) >> 7; - uint32_t temp = ptr->ENDPTCTRL[epnum]; - - return dir ? USB_ENDPTCTRL_TXT_GET(temp) : USB_ENDPTCTRL_RXT_GET(temp); -} - -void usb_dcd_edpt_xfer(USB_Type *ptr, uint8_t ep_idx) -{ - uint32_t offset = ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); - - /* Start transfer */ - ptr->ENDPTPRIME = 1 << offset; -} - -void usb_dcd_edpt_stall(USB_Type *ptr, uint8_t ep_addr) -{ - uint8_t const epnum = ep_addr & 0x0f; - uint8_t const dir = (ep_addr & 0x80) >> 7; - - ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_STALL << (dir ? 16 : 0); -} - -void usb_dcd_edpt_clear_stall(USB_Type *ptr, uint8_t ep_addr) -{ - uint8_t const epnum = ep_addr & 0x0f; - uint8_t const dir = (ep_addr & 0x80) >> 7; - - /* data toggle also need to be reset */ - ptr->ENDPTCTRL[epnum] |= ENDPTCTRL_TOGGLE_RESET << (dir ? 16 : 0); - ptr->ENDPTCTRL[epnum] &= ~(ENDPTCTRL_STALL << (dir ? 16 : 0)); -} - -bool usb_dcd_edpt_check_stall(USB_Type *ptr, uint8_t ep_addr) -{ - uint8_t const epnum = ep_addr & 0x0f; - uint8_t const dir = (ep_addr & 0x80) >> 7; - - return (ptr->ENDPTCTRL[epnum] & (ENDPTCTRL_STALL << (dir ? 16 : 0))) ? true : false; -} - -void usb_dcd_edpt_close(USB_Type *ptr, uint8_t ep_addr) -{ - uint8_t const epnum = ep_addr & 0x0f; - uint8_t const dir = (ep_addr & 0x80) >> 7; - - uint32_t primebit = HPM_BITSMASK(1, epnum) << (dir ? 16 : 0); - - /* Flush the endpoint to stop a transfer. */ - do { - /* Set the corresponding bit(s) in the ENDPTFLUSH register */ - ptr->ENDPTFLUSH |= primebit; - - /* Wait until all bits in the ENDPTFLUSH register are cleared. */ - while (0U != (ptr->ENDPTFLUSH & primebit)) { - } - /* - * Read the ENDPTSTAT register to ensure that for all endpoints - * commanded to be flushed, that the corresponding bits - * are now cleared. - */ - } while (0U != (ptr->ENDPTSTAT & primebit)); - - /* Disable the endpoint */ - ptr->ENDPTCTRL[epnum] &= ~((ENDPTCTRL_TYPE | ENDPTCTRL_ENABLE | ENDPTCTRL_STALL) << (dir ? 16 : 0)); - ptr->ENDPTCTRL[epnum] |= (usb_xfer_bulk << 2) << (dir ? 16 : 0); -} - -void usb_dcd_remote_wakeup(USB_Type *ptr) -{ - (void) ptr; -} - -bool usb_hcd_init(USB_Type *ptr, uint32_t int_mask, uint16_t framelist_size) -{ - uint8_t framelist_size_bf = 0; - - if (framelist_size > USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS || framelist_size == 0) { - return false; - } - - framelist_size_bf = 10 - get_first_set_bit_from_lsb(framelist_size); - - if (framelist_size != (1 << get_first_set_bit_from_lsb(framelist_size))) { - return false; - } - - usb_phy_init(ptr); - - /* Reset controller */ - ptr->USBCMD |= USB_USBCMD_RST_MASK; - while (USB_USBCMD_RST_GET(ptr->USBCMD)) { - } - - /* Set mode to host, must be set immediately after reset */ - ptr->USBMODE &= ~USB_USBMODE_CM_MASK; - ptr->USBMODE |= USB_USBMODE_CM_SET(usb_ctrl_mode_host); - - /* Set the endian */ - ptr->USBMODE &= ~USB_USBMODE_ES_MASK; - - /* Set parallel interface signal */ - ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; - - /* Set parallel transceiver width */ - ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; - - /* Not use interrupt threshold. */ - ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; - - /* USB INT Register */ - ptr->USBSTS = ptr->USBSTS; - ptr->USBINTR |= int_mask; - - /* USB CMD Register */ - ptr->USBCMD = USB_USBCMD_ASE_MASK | USB_USBCMD_PSE_MASK - | USB_USBCMD_FS_2_SET(framelist_size_bf >> 2) - | USB_USBCMD_FS_1_SET(framelist_size_bf); - - return true; -} - -void usb_hcd_port_reset(USB_Type *ptr) -{ - if (usb_phy_get_line_state(ptr) == usb_line_state2) { - ptr->PORTSC1 |= USB_PORTSC1_STS_MASK; - } else { - ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; - } - - ptr->PORTSC1 &= ~USB_PORTSC1_PE_MASK; - ptr->PORTSC1 |= USB_PORTSC1_PR_MASK; - - /* wait until port reset sequence is completed */ - while (USB_PORTSC1_PR_GET(ptr->PORTSC1)) { - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c deleted file mode 100644 index 0f342da2372..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vad_drv.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_vad_drv.h" - -void vad_get_default_config(VAD_Type *ptr, vad_config_t *config) -{ - (void) ptr; - config->enable_buffer = true; - config->enable_pdm_clock_out = true; - config->enable_two_channels = true; - config->capture_delay = 1; - config->pdm_half_div = 3; - config->fifo_threshold = 4; - config->channel_polarity_high[0] = false; - config->channel_polarity_high[1] = true; - config->post_scale = 20; -} - -void vad_init(VAD_Type *ptr, vad_config_t *config) -{ - vad_reset(ptr); - ptr->CTRL = VAD_CTRL_PDM_CLK_HFDIV_SET(config->pdm_half_div) - | VAD_CTRL_PDM_CLK_OE_SET(config->enable_pdm_clock_out) - | VAD_CTRL_MEMBUF_DISABLE_SET(!config->enable_buffer) - | VAD_CTRL_FIFO_THRSH_SET(config->fifo_threshold) - | VAD_CTRL_CAPT_DLY_SET(config->capture_delay) - | VAD_CTRL_CHNUM_SET(config->enable_two_channels) - | VAD_CTRL_CH_POL_SET((config->channel_polarity_high[1] << 1) - | config->channel_polarity_high[0]); - ptr->FILTCTRL = VAD_FILTCTRL_DECRATIO_SET(2) - | VAD_FILTCTRL_IIR_SLOT_EN_SET(0xff); - ptr->CIC_CFG = (ptr->CIC_CFG & ~VAD_CIC_CFG_POST_SCALE_MASK) - | VAD_CIC_CFG_POST_SCALE_SET(config->post_scale); - - vad_enable_fifo(ptr); -} - -void vad_reset(VAD_Type *ptr) -{ - if (vad_is_running(ptr)) { - vad_stop(ptr); - } - vad_software_reset(ptr); -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c deleted file mode 100644 index 40a0ce642d6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_vsc_drv.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_vsc_drv.h" - -void vsc_get_default_config(VSC_Type *vsc, vsc_config_t *config) -{ - (void)vsc; - - config->phase_mode = vsc_abc_phase; - config->a_adc_config.adc_sel = vsc_sel_adc0; - config->b_adc_config.adc_sel = vsc_sel_adc1; - config->c_adc_config.adc_sel = vsc_sel_adc2; - config->a_adc_config.adc_chn = 0; - config->b_adc_config.adc_chn = 0; - config->c_adc_config.adc_chn = 0; - config->a_adc_config.adc_offset = 0x80000000; - config->b_adc_config.adc_offset = 0x80000000; - config->c_adc_config.adc_offset = 0x80000000; - - config->a_data_cnt = 1; - config->a_data_opr_config.opr_0 = vsc_data_opr_plus_mul_1; - config->a_data_opr_config.opr_1 = vsc_data_opr_plus_mul_1; - config->a_data_opr_config.opr_2 = vsc_data_opr_plus_mul_1; - config->a_data_opr_config.opr_3 = vsc_data_opr_plus_mul_1; - config->b_data_cnt = 1; - config->b_data_opr_config.opr_0 = vsc_data_opr_plus_mul_1; - config->b_data_opr_config.opr_1 = vsc_data_opr_plus_mul_1; - config->b_data_opr_config.opr_2 = vsc_data_opr_plus_mul_1; - config->b_data_opr_config.opr_3 = vsc_data_opr_plus_mul_1; - config->c_data_cnt = 1; - config->c_data_opr_config.opr_0 = vsc_data_opr_plus_mul_1; - config->c_data_opr_config.opr_1 = vsc_data_opr_plus_mul_1; - config->c_data_opr_config.opr_2 = vsc_data_opr_plus_mul_1; - config->c_data_opr_config.opr_3 = vsc_data_opr_plus_mul_1; - - config->pos_cap_mode = vsc_pos_use_last_data_when_adc_sample_finish; - config->pole_pairs = 1; -} - -void vsc_config_init(VSC_Type *vsc, vsc_config_t *config) -{ - vsc->ABC_MODE = VSC_ABC_MODE_PHASE_ABSENT_MODE_SET(config->phase_mode) - | VSC_ABC_MODE_VALUE_C_WIDTH_SET(config->c_data_cnt) - | VSC_ABC_MODE_VALUE_B_WIDTH_SET(config->b_data_cnt) - | VSC_ABC_MODE_VALUE_A_WIDTH_SET(config->a_data_cnt) - | VSC_ABC_MODE_VALUE_C_LOC_SET(config->c_adc_config.adc_sel) - | VSC_ABC_MODE_VALUE_B_LOC_SET(config->b_adc_config.adc_sel) - | VSC_ABC_MODE_VALUE_A_LOC_SET(config->a_adc_config.adc_sel); - - vsc->ADC_CHAN_ASSIGN = VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SET(config->c_adc_config.adc_chn) - | VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SET(config->b_adc_config.adc_chn) - | VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SET(config->a_adc_config.adc_chn); - - vsc->VALUE_A_DATA_OPT = VSC_VALUE_A_DATA_OPT_OPT_3_SET(config->a_data_opr_config.opr_3) - | VSC_VALUE_A_DATA_OPT_OPT_2_SET(config->a_data_opr_config.opr_2) - | VSC_VALUE_A_DATA_OPT_OPT_1_SET(config->a_data_opr_config.opr_1) - | VSC_VALUE_A_DATA_OPT_OPT_0_SET(config->a_data_opr_config.opr_0); - - vsc->VALUE_B_DATA_OPT = VSC_VALUE_B_DATA_OPT_OPT_3_SET(config->b_data_opr_config.opr_3) - | VSC_VALUE_B_DATA_OPT_OPT_2_SET(config->b_data_opr_config.opr_2) - | VSC_VALUE_B_DATA_OPT_OPT_1_SET(config->b_data_opr_config.opr_1) - | VSC_VALUE_B_DATA_OPT_OPT_0_SET(config->b_data_opr_config.opr_0); - - vsc->VALUE_C_DATA_OPT = VSC_VALUE_C_DATA_OPT_OPT_3_SET(config->c_data_opr_config.opr_3) - | VSC_VALUE_C_DATA_OPT_OPT_2_SET(config->c_data_opr_config.opr_2) - | VSC_VALUE_C_DATA_OPT_OPT_1_SET(config->c_data_opr_config.opr_1) - | VSC_VALUE_C_DATA_OPT_OPT_0_SET(config->c_data_opr_config.opr_0); - - vsc->VALUE_A_OFFSET = VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SET(config->a_adc_config.adc_offset); - vsc->VALUE_B_OFFSET = VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SET(config->b_adc_config.adc_offset); - vsc->VALUE_C_OFFSET = VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SET(config->c_adc_config.adc_offset); - - vsc_config_pos_capture_mode(vsc, config->pos_cap_mode); - vsc_set_pos_pole_pairs(vsc, config->pole_pairs); -} - -void vsc_sw_inject_abc_value(VSC_Type *vsc, int32_t value_a, int32_t value_b, int32_t value_c) -{ - vsc->TRIGGER_SW = VSC_TRIGGER_SW_TRIGGER_SW_MASK; - vsc->VALUE_A_SW = VSC_VALUE_A_SW_VALUE_A_SW_SET((uint32_t)value_a); - vsc->VALUE_B_SW = VSC_VALUE_B_SW_VALUE_B_SW_SET((uint32_t)value_b); - vsc->VALUE_C_SW = VSC_VALUE_C_SW_VALUE_C_SW_SET((uint32_t)value_c); - vsc->VALUE_SW_READY = VSC_VALUE_SW_READY_VALUE_SW_READY_MASK; -} - -void vsc_sw_inject_pos_value(VSC_Type *vsc, uint32_t pos) -{ - vsc->POSITION_SW = VSC_POSITION_SW_POSITION_SW_SET(pos); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c b/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c deleted file mode 100644 index 111b77ea2d6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/drivers/src/hpm_wdg_drv.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_wdg_drv.h" - -#define TICKS_1K (1024UL) -#define TICKS_1M (1024UL * TICKS_1K) -#define TICKS_1G (1024UL * TICKS_1M) -#define ONE_SECOND_TICKS_IN_NS (1000UL * 1000UL * 1000UL) - -typedef struct { - uint32_t top; - reset_interval_t interval; -} reset_interval_map_t; - -typedef struct { - uint32_t top; - interrupt_interval_t interval; -} interrupt_interval_map_t; - -static const reset_interval_map_t k_reset_interval_map[reset_interval_out_of_range + 1U] = { - {128UL, reset_interval_clock_period_mult_128}, - {256UL, reset_interval_clock_period_mult_256}, - {512UL, reset_interval_clock_period_mult_512}, - {1UL * TICKS_1K, reset_interval_clock_period_mult_1k}, - {2UL * TICKS_1K, reset_interval_clock_period_mult_2k}, - {4UL * TICKS_1K, reset_interval_clock_period_mult_4k}, - {8UL * TICKS_1K, reset_interval_clock_period_mult_8k}, - {16UL * TICKS_1K, reset_interval_clock_period_mult_16k}, - {0xFFFFFFFFUL, reset_interval_out_of_range}, -}; - -static const interrupt_interval_map_t k_interrupt_interval_map[interrupt_interval_out_of_range + 1U] = { - {64UL, interrupt_interval_clock_period_multi_64}, - {256UL, interrupt_interval_clock_period_multi_256}, - {1UL * TICKS_1K, interrupt_interval_clock_period_multi_1k}, - {2UL * TICKS_1K, interrupt_interval_clock_period_multi_2k}, - {4UL * TICKS_1K, interrupt_interval_clock_period_multi_4k}, - {8UL * TICKS_1K, interrupt_interval_clock_period_multi_8k}, - {16UL * TICKS_1K, interrupt_interval_clock_period_multi_16k}, - {32UL * TICKS_1K, interrupt_interval_clock_period_multi_32k}, - {128UL * TICKS_1K, interrupt_interval_clock_period_multi_128k}, - {512UL * TICKS_1K, interrupt_interval_clock_period_multi_512k}, - {2UL * TICKS_1M, interrupt_interval_clock_period_multi_2m}, - {8UL * TICKS_1M, interrupt_interval_clock_period_multi_8m}, - {32UL * TICKS_1M, interrupt_interval_clock_period_multi_32m}, - {128UL * TICKS_1M, interrupt_interval_clock_period_multi_128m}, - {512UL * TICKS_1M, interrupt_interval_clock_period_multi_512m}, - {2UL * TICKS_1G, interrupt_interval_clock_period_multi_2g}, - {0xFFFFFFFFUL, interrupt_interval_out_of_range} - -}; - -/* See hpm_wdg_drv.h for more details */ -hpm_stat_t wdg_init(WDG_Type *base, wdg_control_t *wdg_ctrl) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF((base == NULL) || (wdg_ctrl == NULL)); - - HPM_BREAK_IF((wdg_ctrl->reset_interval > reset_interval_max) || - (wdg_ctrl->interrupt_interval > interrupt_interval_max) || - (wdg_ctrl->clksrc > wdg_clksrc_pclk)); - - uint32_t rst_time = (uint32_t) wdg_ctrl->reset_interval; - uint32_t int_time = (uint32_t) wdg_ctrl->interrupt_interval; - uint32_t reset_en = wdg_ctrl->reset_enable ? 1UL : 0UL; - uint32_t int_en = wdg_ctrl->interrupt_enable ? 1UL : 0UL; - uint32_t clk_src = (wdg_ctrl->clksrc == wdg_clksrc_pclk) ? 1UL : 0UL; - uint32_t wdg_en = wdg_ctrl->wdg_enable ? 1UL : 0UL; - - uint32_t wdg_ctrl = WDG_CTRL_RSTTIME_SET(rst_time) - | WDG_CTRL_INTTIME_SET(int_time) - | WDG_CTRL_CLKSEL_SET(clk_src) - | WDG_CTRL_RSTEN_SET(reset_en) - | WDG_CTRL_INTEN_SET(int_en) - | WDG_CTRL_EN_SET(wdg_en); - - wdg_write_enable(base); - - base->CTRL = wdg_ctrl; - - status = status_success; - - } while (false); - - return status; -} - -/* See hpm_wdg_drv.h for more details */ -reset_interval_t wdg_convert_reset_interval_from_us(const uint32_t src_freq, const uint32_t reset_us) -{ - reset_interval_t reset_interval = reset_interval_out_of_range; - - uint32_t src_clk_one_tick_in_ns = ONE_SECOND_TICKS_IN_NS / src_freq; - if (src_clk_one_tick_in_ns < 1U) { - src_clk_one_tick_in_ns = 1U; - } - - uint32_t reset_interval_ticks = (reset_us * 1000UL) / src_clk_one_tick_in_ns; - - for (uint32_t i = 0; i < ARRAY_SIZE(k_reset_interval_map); i++) { - if (reset_interval_ticks <= k_reset_interval_map[i].top) { - reset_interval = k_reset_interval_map[i].interval; - break; - } - } - - return reset_interval; -} - -/* See hpm_wdg_drv.h for more details */ -interrupt_interval_t wdg_convert_interrupt_interval_from_us(const uint32_t src_freq, uint32_t interval_us) -{ - interrupt_interval_t interrupt_interval = interrupt_interval_out_of_range; - - uint32_t src_clk_one_tick_in_ns = ONE_SECOND_TICKS_IN_NS / src_freq; - if (src_clk_one_tick_in_ns < 1U) { - src_clk_one_tick_in_ns = 1U; - } - - uint32_t interrupt_interval_ticks = ((uint64_t) interval_us * 1000L) / src_clk_one_tick_in_ns; - for (uint32_t i = 0; i < ARRAY_SIZE(k_interrupt_interval_map); i++) { - if (interrupt_interval_ticks <= k_interrupt_interval_map[i].top) { - interrupt_interval = k_interrupt_interval_map[i].interval; - break; - } - } - - return interrupt_interval; -} - -uint64_t wdg_convert_interrupt_interval_to_us(const uint32_t src_freq, interrupt_interval_t interval) -{ - uint64_t time_in_us = 0; - if ((src_freq != 0) && (interval < interrupt_interval_out_of_range)) { - uint32_t interrupt_interval_in_reg = (uint32_t) interval; - - double tick_in_ns = 1.0 * ONE_SECOND_TICKS_IN_NS / src_freq; - uint64_t - total_interval_in_ns = (uint64_t)(tick_in_ns * k_interrupt_interval_map[interrupt_interval_in_reg].top); - - time_in_us = total_interval_in_ns / 1000UL; - } - - return time_in_us; -} - -uint32_t wdg_convert_reset_interval_to_us(const uint32_t src_freq, reset_interval_t interval) -{ - uint32_t time_in_us = 0; - if ((src_freq != 0) && (interval < reset_interval_out_of_range)) { - uint32_t reset_interval_in_reg = (uint32_t) interval; - double tick_in_ns = 1.0 * ONE_SECOND_TICKS_IN_NS / src_freq; - uint64_t total_interval_in_ns = (uint64_t)(tick_in_ns * k_reset_interval_map[reset_interval_in_reg].top); - - time_in_us = (uint32_t)(total_interval_in_ns / 1000UL); - } - - return time_in_us; -} - -uint64_t wdg_get_interrupt_interval_in_us(WDG_Type *base, const uint32_t src_freq) -{ - uint64_t time_in_us = 0; - if ((base != NULL) && (src_freq != 0)) { - interrupt_interval_t interval = (interrupt_interval_t) WDG_CTRL_INTTIME_GET(base->CTRL); - - time_in_us = wdg_convert_interrupt_interval_to_us(src_freq, interval); - } - - return time_in_us; -} - -uint64_t wdg_get_total_reset_interval_in_us(WDG_Type *base, const uint32_t src_freq) -{ - uint64_t time_in_us = 0; - if ((base != NULL) && (src_freq != 0)) { - reset_interval_t reset_interval = (reset_interval_t) WDG_CTRL_RSTTIME_GET(base->CTRL); - interrupt_interval_t interrupt_interval = (interrupt_interval_t) WDG_CTRL_INTTIME_GET(base->CTRL); - time_in_us = wdg_convert_reset_interval_to_us(src_freq, reset_interval) + - wdg_convert_interrupt_interval_to_us(src_freq, interrupt_interval); - } - - return time_in_us; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/HPM5301_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/HPM5301_svd.xml deleted file mode 100644 index ed566eab7cd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/HPM5301_svd.xml +++ /dev/null @@ -1,13471 +0,0 @@ - - - HPMICRO - HPM5301 - HPM5300 - 1.0 - HPM5300 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x8f0 - registers - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - PD[%s] - no description available - 0x800 - - VALUE - GPIO dual edge interrupt enable value - 0x0 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable -0: single edge interrupt -1: dual edge interrupt enable - 0 - 1 - read-write - - - - - SET - GPIO dual edge interrupt enable set - 0x4 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable set -0: keep original edge interrupt type -1: dual edge interrupt enable - 0 - 1 - read-write - - - - - CLEAR - GPIO dual edge interrupt enable clear - 0x8 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable clear -0: keep original edge interrupt type -1: single edge interrupt enable - 0 - 1 - read-write - - - - - TOGGLE - GPIO dual edge interrupt enable toggle - 0xc - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable toggle -0: keep original edge interrupt type -1: change original edge interrupt type to another one. - 0 - 1 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf00d0000 - - - PGPIO - PGPIO - GPIO - 0xf411c000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x201000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 1 - 0x80 - target0 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 1 - 0x1000 - target0 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPTMR0 - GPTMR0 - GPTMR - 0xf0000000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x8003FFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - OPMODE - 0: round mode -1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. -NOTE: reload irq will be always set at one-shot mode at end - 17 - 1 - read-write - - - MONITOR_SEL - set to monitor input signal high level time(chan_meas_high) -clr to monitor input signal period(chan_meas_prd) - 16 - 1 - read-write - - - MONITOR_EN - set to monitor input signal period or high level time. -When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts -* only can be used when trig_mode is selected as measure mode(100) -* the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. -if no posedge after reload for more than val_1, will also assert irq_capt - 15 - 1 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - GPTMR1 - GPTMR1 - GPTMR - 0xf0004000 - - - PTMR - PTMR - GPTMR - 0xf4120000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x4 - 0x3c - registers - - - - IDLE_CFG - Idle Configuration Register - 0x4 - 32 - 0x00000000 - 0x03FF0BFF - - - TX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if TX pin is logic one -1 - Treat as idle if UART state machine state is idle - 25 - 1 - read-write - - - TX_IDLE_EN - UART TX Idle Detect Enable -0 - Disable -1 - Enable - 24 - 1 - read-write - - - TX_IDLE_THR - Threshold for UART transmit Idle detection (in terms of bits) - 16 - 8 - read-write - - - RXEN - UART receive enable. -0 - hold RX input to high, avoide wrong data input when config pinmux -1 - bypass RX input from PIN -software should set it after config pinmux - 11 - 1 - read-write - - - RX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if RX pin is logic one -1 - Treat as idle if UART state machine state is idle - 9 - 1 - read-write - - - RX_IDLE_EN - UART Idle Detect Enable -0 - Disable -1 - Enable -it should be enabled if enable address match feature - 8 - 1 - read-write - - - RX_IDLE_THR - Threshold for UART Receive Idle detection (in terms of bits) - 0 - 8 - read-write - - - - - ADDR_CFG - address match config register - 0x8 - 32 - 0x00000000 - 0x001FFFFF - - - TXEN_9BIT - set to use 9bit mode for transmitter, -will set the MSB for the first character as address flag, keep 0 for others. - 20 - 1 - read-write - - - RXEN_ADDR_MSB - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). -Clr to use first character as address. -Only needed if enable address match feature - 19 - 1 - read-write - - - RXEN_9BIT - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set - 18 - 1 - read-write - - - A1_EN - enable addr1 compare for the first character. -If a1_en OR a0_en, then do not receive data if address not match. -If ~a1_en AND ~a0_en, the receive all data like before. -NOTE: should set idle_tmout_en if enable address match feature - 17 - 1 - read-write - - - A0_EN - enable addr0 compare for the first character - 16 - 1 - read-write - - - ADDR1 - address 1 fileld. -in 9bit mode, this is the full address byte. -For other mode(8/7/6/5bit), MSB should be set for address flag. -If want address==0 to be matched at 8bit mode, should set addr1=0x80 - 8 - 8 - read-write - - - ADDR0 - address 0 field. - 0 - 8 - read-write - - - - - IIR2 - Interrupt Identification Register2 - 0xc - 32 - 0x00000001 - 0xF80000CF - - - RXIDLE_FLAG - UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear -0 - UART RX is busy -1 - UART RX is idle - 31 - 1 - write-only - - - TXIDLE_FLAG - UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear -0 - UART TX is busy -1 - UART TX is idle - 30 - 1 - write-only - - - ADDR_MATCH - address match irq status, assert if either address match(and enabled). Write one clear -NOTE: the address byte may not moved by DMA at this point. -User can wait next addr_match_idle irq for the whole data include address - 29 - 1 - write-only - - - ADDR_MATCH_IDLE - address match and idle irq status, assert at rx bus idle if address match event triggered. -Write one clear; - 28 - 1 - write-only - - - DATA_LOST - assert if data lost before address match status, write one clear; -It will not assert if no address match occurs - 27 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - FCRR - FIFO Control Register config - 0x18 - 32 - 0x00000000 - 0x008F0FFF - - - FIFOT4EN - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) -clr to use 2bit(TFIFOT and RFIFOT) - 23 - 1 - read-write - - - TFIFOT4 - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. - 16 - 4 - read-write - - - RFIFOT4 - rxfifo threshold(0 for 1byte, 0xF for 16bytes). -Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled - 8 - 4 - read-write - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - read-write - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - read-write - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - read-write - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - read-write - - - - - MOTO_CFG - moto system control register - 0x1c - 32 - 0x00000000 - 0x8000FFF0 - - - SWTRG - software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. -Hardware auto reset. - 31 - 1 - write-only - - - TXSTP_BITS - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits - 8 - 8 - read-write - - - HWTRG_EN - set to enable hardware trigger(trigger from moto is shared by other UART) - 7 - 1 - read-write - - - TRG_MODE - set to enable trigger mode. -software should push needed data into txbuffer frist, uart will not start transmission at this time. -User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty -NOTE: the hw_trigger should be pulse signal from trig mux. - 6 - 1 - read-write - - - TRG_CLR_RFIFO - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. - 5 - 1 - read-write - - - TXSTOP_INSERT - set to insert STOP bits between each tx byte till tx fifo empty. -NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set - 4 - 1 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0xF800000F - - - ERXIDLE - Enable Receive Idle interrupt -0 - Disable Idle interrupt -1 - Enable Idle interrupt - 31 - 1 - read-write - - - ETXIDLE - enable transmit idle interrupt - 30 - 1 - read-write - - - EADDRM - enable ADDR_MATCH interrupt - 29 - 1 - read-write - - - EADDRM_IDLE - enable ADDR_MATCH_IDLE interrupt - 28 - 1 - read-write - - - EDATLOST - enable DATA_LOST interrupt - 27 - 1 - read-write - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x800000CF - - - RXIDLE_FLAG - UART IDLE Flag -0 - UART is busy -1 - UART is idle -NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - 31 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0xC01F1FFF - - - RXIDLE - rxidle after timeout, clear after rx idle condition not match - 31 - 1 - read-only - - - TXIDLE - txidle after timeout, clear after tx idle condition not match - 30 - 1 - read-only - - - RFIFO_NUM - data bytes in rxfifo not read - 16 - 5 - read-only - - - TFIFO_NUM - data bytes in txfifo not sent - 8 - 5 - read-only - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - PUART - PUART - UART - 0xf4124000 - - - I2C0 - I2C0 - I2C - 0xf0060000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00905E00 - 0xFFFFFFFF - - - DATACNT_HIGH - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 24 - 8 - read-write - - - RESET_LEN - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - 20 - 4 - read-write - - - RESET_HOLD_SCKIN - set to hold input clock to high when reset is active - 14 - 1 - read-write - - - RESET_ON - set to send reset signals(just toggle clock bus defined by reset_len). -this register is clered when reset is end, can't be cleared by software - 13 - 1 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf0064000 - - - I2C2 - I2C2 - I2C - 0xf0068000 - - - I2C3 - I2C3 - I2C - 0xf006c000 - - - SPI0 - SPI0 - SPI - 0xf0070000 - - 0x4 - 0x7c - registers - - - - wr_trans_cnt - Transfer count for write data - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 0 - 32 - read-write - - - - - rd_trans_cnt - Transfer count for read data - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 32 - read-write - - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - DirectIO - Direct IO Control Register - 0x14 - 32 - 0x00003100 - 0x013F3F3F - - - DIRECTIOEN - Enable Direct IO -0x0: Disable -0x1: Enable - 24 - 1 - read-write - - - HOLD_OE - Output enable for the SPI Flash hold signal - 21 - 1 - read-write - - - WP_OE - Output enable for the SPI Flash write protect signal - 20 - 1 - read-write - - - MISO_OE - Output enable fo the SPI MISO signal - 19 - 1 - read-write - - - MOSI_OE - Output enable for the SPI MOSI signal - 18 - 1 - read-write - - - SCLK_OE - Output enable for the SPI SCLK signal - 17 - 1 - read-write - - - CS_OE - Output enable for SPI CS (chip select) signal - 16 - 1 - read-write - - - HOLD_O - Output value for the SPI Flash hold signal - 13 - 1 - read-write - - - WP_O - Output value for the SPI Flash write protect signal - 12 - 1 - read-write - - - MISO_O - Output value for the SPI MISO signal - 11 - 1 - read-write - - - MOSI_O - Output value for the SPI MOSI signal - 10 - 1 - read-write - - - SCLK_O - Output value for the SPI SCLK signal - 9 - 1 - read-write - - - CS_O - Output value for the SPI CS (chip select) signal - 8 - 1 - read-write - - - HOLD_I - Status of the SPI Flash hold signal - 5 - 1 - read-only - - - WP_I - Status of the SPI Flash write protect signal - 4 - 1 - read-only - - - MISO_I - Status of the SPI MISO signal - 3 - 1 - read-only - - - MOSI_I - Status of the SPI MOSI signal - 2 - 1 - read-only - - - SCLK_I - Status of the SPI SCLK signal - 1 - 1 - read-only - - - CS_I - Status of the SPI CS (chip select) signal - 0 - 1 - read-only - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x0FFFFF1F - - - CS_EN - No description available - 24 - 4 - read-write - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - SlvDataWCnt - WCnt - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - SlvDataRCnt - RCnt - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0074000 - - - SPI2 - SPI2 - SPI - 0xf0078000 - - - SPI3 - SPI3 - SPI - 0xf007c000 - - - CRC - CRC - CRC - 0xf0080000 - - 0x0 - 0x200 - registers - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - pre_set - &index0 pre set for crc setting - 0x0 - 32 - 0x00000000 - 0x000000FF - - - PRE_SET - 0: no pre set -1: CRC32 -2: CRC32-AUTOSAR -3: CRC16-CCITT -4: CRC16-XMODEM -5: CRC16-MODBUS -1: CRC32 -2: CRC32-autosar -3: CRC16-ccitt -4: CRC16-xmodem -5: CRC16-modbus -6: crc16_dnp -7: crc16_x25 -8: crc16_usb -9: crc16_maxim -10: crc16_ibm -11: crc8_maxim -12: crc8_rohc -13: crc8_itu -14: crc8 -15: crc5_usb - 0 - 8 - read-write - - - - - clr - chn&index0 clear crc result and setting - 0x4 - 32 - 0x00000000 - 0x00000001 - - - CLR - write 1 to clr crc setting and result for its channel. -always read 0. - 0 - 1 - read-write - - - - - poly - chn&index0 poly - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - poly setting - 0 - 32 - read-write - - - - - init_data - chn&index0 init_data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INIT_DATA - initial data of CRC - 0 - 32 - read-write - - - - - xorout - chn&index0 xorout - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XOROUT - XOR for CRC result - 0 - 32 - read-write - - - - - misc_setting - chn&index0 misc_setting - 0x14 - 32 - 0x00000000 - 0x0101013F - - - BYTE_REV - 0: no wrap input byte order -1: wrap input byte order - 24 - 1 - read-write - - - REV_OUT - 0: no wrap output bit order -1: wrap output bit order - 16 - 1 - read-write - - - REV_IN - 0: no wrap input bit order -1: wrap input bit order - 8 - 1 - read-write - - - POLY_WIDTH - crc data length - 0 - 6 - read-write - - - - - data - chn&index0 data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data for crc - 0 - 32 - read-write - - - - - result - chn&index0 result - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - crc result - 0 - 32 - read-write - - - - - - - - TSNS - TSNS - TSNS - 0xf0090000 - - 0x0 - 0x3c - registers - - - - T - Temperature - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - Maximum Temperature - 0x4 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - Minimum Temperature - 0x8 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - Sample age - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - Status - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - write-only - - - - - CONFIG - Configuration - 0x14 - 32 - 0x00600300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valid from 24-255, default 96 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, default in 3 -0: measure and return -1: twice and average -2: 4 times and average -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - Sample validity - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - Temperature flag - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - Maximum temperature to interrupt - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - Minimum temperature to interrupt - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - Maximum temperature to reset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - Minimum temperature to reset - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - Configuration in asynchronous mode - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - Polarity of internal comparator - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - Advance configuration - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - EWDG0 - EWDG0 - EWDG - 0xf00b0000 - - 0x0 - 0x28 - registers - - - - CTRL0 - wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x0 - 32 - 0x00000000 - 0x2FE2F03F - - - CLK_SEL - clock select -0：bus clock -1：ext clock - 29 - 1 - read-write - - - DIV_VALUE - clock divider, the clock divider works as 2 ^ div_value for wdt counter - 25 - 3 - read-write - - - WIN_EN - window mode enable - 24 - 1 - read-write - - - WIN_LOWER - Once window mode is opened, the lower counter value to refresh wdt -00: 4/8 overtime value -01: 5/8 of overtime value -10: 6/8 of overtime value -11: 7/8 of overtime value - 22 - 2 - read-write - - - CFG_LOCK - The register is locked and unlock is needed before re-config registers -Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. -The register update needs to be finished in the required period defined by UPD_OT_TIME register - 21 - 1 - read-write - - - OT_SELF_CLEAR - overtime reset can be self released after 32 function cycles - 17 - 1 - read-write - - - REF_OT_REQ - If refresh event has to be limited into a period after refresh unlocked. -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 15 - 1 - read-write - - - WIN_UPPER - The upper threshold of window value -The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value -If this register value is zero, then no upper level limitation - 12 - 3 - read-write - - - REF_LOCK - WDT refresh has to be unlocked firstly once refresh lock is enable. - 5 - 1 - read-write - - - REF_UNLOCK_MEC - Unlock refresh mechanism -00: the required unlock password is the same with refresh_psd_register -01: the required unlock password is a ring shift left value of refresh_psd_register -10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is -11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - 3 - 2 - read-write - - - EN_DBG - WTD enable or not in debug mode - 2 - 1 - read-write - - - EN_LP - WDT enable or not in low power mode -2'b00: wdt is halted once in low power mode -2'b01: wdt will work with 1/4 normal clock freq in low power mode -2'b10: wdt will work with 1/2 normal clock freq in low power mode -2'b11: wdt will work with normal clock freq in low power mode - 0 - 2 - read-write - - - - - CTRL1 - wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x4 - 32 - 0x00000000 - 0x00F300FC - - - REF_FAIL_RST_EN - Refresh violation will trigger an reset. -These event will be taken as a refresh violation: -1) Not refresh in the window once window mode is enabled -2) Not unlock refresh firstly if unlock is required -3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. -4) Not write the required word to refresh wdt. - 23 - 1 - read-write - - - REF_FAIL_INT_EN - Refresh violation will trigger an interrupt - 22 - 1 - read-write - - - UNL_REF_FAIL_RST_EN - Refresh unlock fail will trigger a reset - 21 - 1 - read-write - - - UNL_REF_FAIL_INT_EN - Refresh unlock fail will trigger a interrupt - 20 - 1 - read-write - - - OT_RST_EN - WDT overtime will generate a reset - 17 - 1 - read-write - - - OT_INT_EN - WDT can generate an interrupt warning before timeout - 16 - 1 - read-write - - - CTL_VIO_RST_EN - Ctrl update violation will trigger a reset -The violation event is to try updating the locked register before unlock them - 7 - 1 - read-write - - - CTL_VIO_INT_EN - Ctrl update violation will trigger a interrupt - 6 - 1 - read-write - - - UNL_CTL_FAIL_RST_EN - Unlock register update failure will trigger a reset - 5 - 1 - read-write - - - UNL_CTL_FAIL_INT_EN - Unlock register update failure will trigger a interrupt - 4 - 1 - read-write - - - PARITY_FAIL_RST_EN - Parity error will trigger a reset -A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - 3 - 1 - read-write - - - PARITY_FAIL_INT_EN - Parity error will trigger a interrupt - 2 - 1 - read-write - - - - - OT_INT_VAL - wdog timeout interrupt counter value - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - OT_INT_VAL - WDT timeout interrupt value - 0 - 16 - read-write - - - - - OT_RST_VAL - wdog timeout reset counter value - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - OT_RST_VAL - WDT timeout reset value - 0 - 16 - read-write - - - - - WDT_REFRESH_REG - wdog refresh register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDT_REFRESH_REG - Write this register by 32'h5A45_524F to refresh wdog -Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - 0 - 32 - write-only - - - - - WDT_STATUS - wdog status register - 0x14 - 32 - 0x00000000 - 0x0000007F - - - PARITY_ERROR - parity error -Write one to clear the bit - 6 - 1 - write-only - - - OT_RST - Timeout happens, a reset will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 5 - 1 - write-only - - - OT_INT - Timeout happens, a interrupt will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 4 - 1 - write-only - - - CTL_UNL_FAIL - Unlock ctrl reg update protection fail -Write one to clear the bit - 3 - 1 - write-only - - - CTL_VIO - Violate register update protection mechanism -Write one to clear the bit - 2 - 1 - write-only - - - REF_UNL_FAIL - Refresh unlock fail -Write one to clear the bit - 1 - 1 - write-only - - - REF_VIO - Refresh fail -Write one to clear the bit - 0 - 1 - write-only - - - - - CFG_PROT - ctrl register protection register - 0x18 - 32 - 0x00000000 - 0x000FFFFF - - - UPD_OT_TIME - The period in which register update has to be in after unlock -The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - 16 - 4 - read-write - - - UPD_PSD - The password of unlocking register update - 0 - 16 - read-write - - - - - REF_PROT - refresh protection register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - REF_UNL_PSD - The password to unlock refreshing - 0 - 16 - read-write - - - - - WDT_EN - Wdog enable - 0x20 - 32 - 0x00000000 - 0x00000001 - - - WDOG_EN - Wdog is enabled, the re-written of this register is impacted by enable lock function - 0 - 1 - read-write - - - - - REF_TIME - Refresh period value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - REFRESH_PERIOD - The refresh period after refresh unlocked -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 0 - 16 - read-write - - - - - - - EWDG1 - EWDG1 - EWDG - 0xf00b4000 - - - PEWDG - PEWDG - EWDG - 0xf4128000 - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c4000 - - 0x0 - 0x80 - registers - - - - 32 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - write-only - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - write-only - - - - - - - HDMA - HDMA - DMAV2 - 0xf00c8000 - - 0x4 - 0x43c - registers - - - - IDMisc - ID Misc - 0x4 - 32 - 0x00000000 - 0x0000FF00 - - - DMASTATE - DMA state machine -localparam ST_IDLE = 3'b000; -localparam ST_READ = 3'b001; -localparam ST_READ_ACK = 3'b010; -localparam ST_WRITE = 3'b011; -localparam ST_WRITE_ACK = 3'b100; -localparam ST_LL = 3'b101; -localparam ST_END = 3'b110; -localparam ST_END_WAIT = 3'b111; - 13 - 3 - read-only - - - CURCHAN - current channel in used - 8 - 5 - read-only - - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. -The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, -which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x14 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. -Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - INTHALFSTS - Harlf Complete Interrupt Status - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - half transfer done irq status - 0 - 32 - read-write - - - - - INTTCSTS - Trans Complete Interrupt Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 0 - 32 - write-only - - - - - INTABORTSTS - Abort Interrupt Status Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 0 - 32 - write-only - - - - - INTERRSTS - Error Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 32 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 32 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel &index0 Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFF01F - - - INFINITELOOP - set to loop current config infinitely - 31 - 1 - read-write - - - HANDSHAKEOPT - 0: one request to transfer one burst -1: one request to transfer all the data defined in ch_tts - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - BURSTOPT - set to change burst_size definition - 28 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; -otherwise the error event will be triggered. -For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -Normal mode is enabled and started by software set Enable bit; -Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -the difference bewteen Source/Destination handshake mode is: -the dma block will response hardware request after read in Source handshake mode; -the dma block will response hardware request after write in Destination handshake mode; -NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - INTHALFCNTMASK - Channel half interrupt mask -0x0: Allow the half interrupt to be triggered -0x1: Disable the half interrupt - 4 - 1 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel &index0Transfer Size Register - 0x4 - 32 - 0x00000000 - 0x0FFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 28 - read-write - - - - - SrcAddr - Channel &index0 Source Address Low Part Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - ChanReqCtrl - Channel &index0 DMA Request Control Register - 0xc - 32 - 0x00000000 - 0x1F1F0000 - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 24 - 5 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 16 - 5 - read-write - - - - - DstAddr - Channel &index0 Destination Address Low Part Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - LLPointer - Channel &index0 Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF8 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - - - - - - GPIOM - GPIOM - GPIOM - 0xf00d8000 - - 0x0 - 0x780 - registers - - - - 15 - 0x80 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -2: cpu0 fastgpio - 0 - 2 - read-write - - - - - - - - USB0 - USB0 - USB - 0xf300c000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFFB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - PRM - Asynchronous Schedule start- Write only， host mode only。 -this bit is used to notify hostcontroller to start async schedule immediately. - 12 - 1 - write-only - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 16 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - SEC - SEC - SEC - 0xf3044000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - MON - MON - MON - 0xf3048000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - OTP - OTP - OTP - 0xf3050000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - KEYM - KEYM - KEYM - 0xf3054000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - ADC0 - ADC0 - ADC16 - 0xf3080000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000003 - - - BUS_MODE_EN - bus mode enable - 1 - 1 - read-write - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - seq_high_cfg - No description available - 0x850 - 32 - 0x00000000 - 0x00FFFFFF - - - STOP_POS_HIGH - No description available - 12 - 12 - read-write - - - BUF_LEN_HIGH - No description available - 0 - 12 - read-write - - - - - 16 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x80001004 - - - MOTO_EN - "set to enable moto_soc and moto_valid. -Should use AHB clock for adc, this bit can be used avoid async output" - 31 - 1 - read-write - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x01F07FFF - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ACMP - ACMP - ACMP - 0xf30b0000 - - 0x0 - 0x40 - registers - - - - 2 - 0x20 - chn0,chn1 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - DAC_TRIG_EN - if set, the dac value is from moto system when valid -if clr, use dac_cfg value - 23 - 1 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x2c00 - registers - - - - 105 - 0x4 - cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_clk3_pll1,clk_src_pll0_ref,clk_src_pll1_ref,rsv44,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv70,rsv71,rsv72,rsv73,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1,clk_top_adc0,clk_top_adc1,clk_top_dac0,clk_top_dac1,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahb0,lmm0,mct0,rom0,can0,can1,can2,can3,ptpc,rsv265,rsv266,rsv267,rsv268,tmr0,tmr1,tmr2,tmr3,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,tsns,crc0,adc0,adc1,dac0,dac1,acmp,opa0,opa1,mot0,rng0,sdp0,kman,gpio,hdma,xpi0,usb0,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 2 - 0x10 - link0,link1 - GROUP0[%s] - no description available - 0x800 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 1 - 0x10 - cpu0 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - - 1 - 0x10 - cpu0 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu0 stop -bit01: soc_ctx is kept on while cpu0 stop -bit02: cpu0_mem is kept on while cpu0 stop -bit03: cpu0_ctx is kept on while cpu0 stop -bit04: xtal_hold is kept on while cpu0 stop -bit05: pll0_hold is kept on while cpu0 stop -bit06: pll1_hold is kept on while cpu0 stop - 0 - 15 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 15 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 15 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 15 - read-write - - - - - - 1 - 0x14 - cpu0 - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0031100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - MEM_RET_N - memory info retention control signal -0: memory enter retention mode -1: memory exit retention mode - 17 - 1 - read-only - - - MEM_RET_P - memory info retention control signal -0: memory not enterexitretention mode -1: memory enter retention mode - 16 - 1 - read-only - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x000000FF - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x0000000F - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - ret_wait - Power Setting - 0x10 - 32 - 0x0000000F - 0x000FFFFF - - - WAIT - wait time for memory retention mode transition, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 2 - 0x10 - soc,cpu0 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00402003 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 1 - 0x4 - clk_top_cpu0 - CLOCK_CPU[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xD00F07FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - SUB0_DIV - ahb bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 16 - 4 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll1_clk2 -7:pll1_clk3 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 32 - 0x4 - clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv5,rsv6,rsv7,rsv8,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1 - CLOCK[%s] - no description available - 0x1804 - 32 - 0x00000000 - 0xD00007FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll1_clk2 -7:pll1_clk3 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 2 - 0x4 - clk_top_adc0,clk_top_adc1 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ahb0 clock -1: ana clock N - 8 - 1 - read-write - - - - - 2 - 0x4 - clk_top_dac0,clk_top_dac1 - DACCLK[%s] - no description available - 0x1c08 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ahb0 clock -1: ana clock N - 8 - 1 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x000000FF - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 -bit4: override to preset4 -bit5: override to preset5 -bit6: override to preset6 -bit7: override to preset7 - 0 - 8 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 1 - 0x400 - cpu0 - CPU[%s] - no description available - 0x2800 - - LP - CPU0 LP control - 0x0 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - CPU0 Lock GPR - 0x4 - 32 - 0x00000000 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 4 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 4 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xe40 - registers - - - - 456 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,rsv64,rsv65,rsv66,rsv67,rsv68,rsv69,rsv70,rsv71,rsv72,rsv73,rsv74,rsv75,rsv76,rsv77,rsv78,rsv79,rsv80,rsv81,rsv82,rsv83,rsv84,rsv85,rsv86,rsv87,rsv88,rsv89,rsv90,rsv91,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -... -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf4118000 - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf40c0000 - - 0x0 - 0x180 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 2 - 0x80 - pll0,pll1 - PLL[%s] - no description available - 0x80 - - MFI - PLL0 multiple register - 0x0 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - MFN - PLL0 fraction numerator register - 0x4 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - MFD - PLL0 fraction demoninator register - 0x8 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - SS_STEP - PLL0 spread spectrum step register - 0xc - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - SS_STOP - PLL0 spread spectrum stop register - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - CONFIG - PLL0 confguration register - 0x14 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - LOCKTIME - PLL0 lock time register - 0x18 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - STEPTIME - PLL0 step time register - 0x1c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - ADVANCED - PLL0 advance configuration register - 0x20 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - 3 - 0x4 - DIV0,DIV1,DIV2 - DIV[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - - PPOR - PPOR - PPOR - 0xf4100000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-only - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HOLD - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_TYPE - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf4104000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x801F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x0001047E - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: trun off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00000384 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000010 - 0x11018191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - ouput over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x03120040 - 0x073F007F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_AUTOLP - enable auto enter low power mode -0: do not enter low power mode -1: enter low power mode if current is detected low - 4 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00006E1C - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit31: pin wakeup - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit31: pin wakeup - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart - 0 - 32 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000310 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PGPR0 - PGPR0 - PGPR - 0xf4110000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PGPR1 - PGPR1 - PGPR - 0xf4114000 - - - PDGO - PDGO - PDGO - 0xf4134000 - - 0x0 - 0x714 - registers - - - - DGO_TURNOFF - trunoff control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. - 0 - 32 - write-only - - - - - DGO_RC32K_CFG - RC32K CLOCK - 0x4 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - DGO_GPR00 - Generic control 0 - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR01 - Generic control 1 - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR02 - Generic control 2 - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR03 - Generic control 3 - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_CTR0 - control register 0 - 0x700 - 32 - 0x00000000 - 0x00010000 - - - RETENTION - dgo register status retenion - 16 - 1 - read-write - - - - - DGO_CTR1 - control register 1 - 0x704 - 32 - 0x00000000 - 0x80010001 - - - AOTO_SYS_WAKEUP - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously - 31 - 1 - read-write - - - WAKEUP_EN - permit wakeup pin or software wakeup - 16 - 1 - read-write - - - PIN_WAKEUP_STATUS - wakeup pin status - 0 - 1 - read-only - - - - - DGO_CTR2 - control register 2 - 0x708 - 32 - 0x00000000 - 0x01010000 - - - RESETN_PULLUP_DISABLE - resetn pin pull up disable - 24 - 1 - read-write - - - WAKEUP_PULLDN_DISABLE - wakeup pin pull down disable - 16 - 1 - read-write - - - - - DGO_CTR3 - control register 3 - 0x70c - 32 - 0x00000000 - 0xFFFFFFFF - - - WAKEUP_COUNTER - software wakeup counter - 0 - 32 - read-write - - - - - DGO_CTR4 - control register 4 - 0x710 - 32 - 0x00000000 - 0x00000003 - - - BANDGAP_LESS_POWER - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 1 - 1 - read-write - - - BANDGAP_LP_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 0 - 1 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/SConscript deleted file mode 100644 index dd355f33b20..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/SConscript +++ /dev/null @@ -1,24 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_clock_drv.c deleted file mode 100644 index 394f001caea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_clock_drv.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_soc.h" -#include "hpm_common.h" -#include "hpm_pllctlv2_drv.h" -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (720000000UL) -#define FREQ_PRESET1_PLL0_CLK1 (450000000UL) -#define FREQ_PRESET1_PLL0_CLK2 (300000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (666666666UL) -#define FREQ_PRESET1_PLL1_CLK2 (500000000UL) -#define FREQ_PRESET1_PLL1_CLK3 (266666666UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) -#define WDG_INSTANCE_NUM (2U) -#define BUS_FREQ_MAX (200000000UL) -#define FREQ_1MHz (1000000UL) - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ - -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for ADC - */ -static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); - -/** - * @brief Get Clock frequency for WDG - */ -static uint32_t get_frequency_for_ewdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PWDG - */ -static uint32_t get_frequency_for_pewdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - -static uint32_t get_frequency_for_cpu(void); -static uint32_t get_frequency_for_ahb(void); - - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ahb, - clock_node_ana0 -}; - -static EWDG_Type *const s_wdgs[] = { HPM_EWDG0, HPM_EWDG1}; - -uint32_t hpm_core_clock; - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq = 0UL; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); - break; - case CLK_SRC_GROUP_EWDG: - clk_freq = get_frequency_for_ewdg(node_or_instance); - break; - case CLK_SRC_GROUP_PEWDG: - clk_freq = get_frequency_for_pewdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_CPU0: - clk_freq = get_frequency_for_cpu(); - break; - case CLK_SRC_GROUP_AHB: - clk_freq = get_frequency_for_ahb(); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq = 0UL; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); - break; - case clock_source_pll0_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); - break; - case clock_source_pll0_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); - break; - case clock_source_pll1_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); - break; - case clock_source_pll1_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); - break; - case clock_source_pll1_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 2U); - break; - case clock_source_pll1_clk3: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 3U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - uint32_t adc_index = instance; - - (void) clk_src_type; - - if (adc_index < ADC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); - if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { - node = s_adc_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node != clock_node_ahb) { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } else { - clk_freq = get_frequency_for_ahb(); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_ewdg(uint32_t instance) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { - freq_in_hz = get_frequency_for_ahb(); - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_pewdg(void) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_cpu(void) -{ - uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_source(mux) / div); -} - -static uint32_t get_frequency_for_ahb(void) -{ - uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_cpu() / div); -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_EWDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_EWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); - } - break; - case CLK_SRC_GROUP_PEWDG: - clk_src_group = CLK_SRC_GROUP_PEWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_CPU0: - case CLK_SRC_GROUP_AHB: - clk_src_group = CLK_SRC_GROUP_CPU0; - clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -uint32_t clock_get_divider(clock_name_t clock_name) -{ - uint32_t clk_divider = CLOCK_DIV_INVALID; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_EWDG: - clk_divider = 1; - break; - case CLK_SRC_GROUP_PEWDG: - clk_divider = 1; - break; - case CLK_SRC_GROUP_PMIC: - clk_divider = 1; - break; - case CLK_SRC_GROUP_CPU0: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_AHB: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - default: - clk_divider = CLOCK_DIV_INVALID; - break; - } - return clk_divider; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana1)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_EWDG) && (clk_src_grp != CLK_SRC_GROUP_PEWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_EWDG: - case CLK_SRC_GROUP_PEWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AHB: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_CPU0: - if (node_or_instance == clock_node_cpu0) { - /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency - * changes, the AXI and AHB clock changes accordingly, here the driver ensures the - * AXI and AHB bus clock frequency is in valid range. - */ - uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; - uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, ahb_sub_div); - } else { - status = status_clk_shared_cpu0; - } - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu == 0U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu == 0U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_update_core_clock(void) -{ - hpm_core_clock = clock_get_frequency(clock_cpu0); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_clock_drv.h deleted file mode 100644 index c1c39625a6c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_clock_drv.h +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" -#include "hpm_csr_drv.h" - - -#define CLOCK_DIV_INVALID (~0UL) - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), - status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), - status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), - status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), - status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), - status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), - status_clk_fixed = MAKE_STATUS(status_group_clk, 10), -}; - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_EWDG (3U) -#define CLK_SRC_GROUP_PMIC (4U) -#define CLK_SRC_GROUP_AHB (5U) -#define CLK_SRC_GROUP_CPU0 (9U) -#define CLK_SRC_GROUP_SRC (10U) -#define CLK_SRC_GROUP_PEWDG (11U) -#define CLK_SRC_GROUP_INVALID (15U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll1_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll1_clk3 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - - -#define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_CPU0 (0xFFFDU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), - - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - - clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), - - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PEWDG, 0), - - clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), - - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 0), - clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 1), - clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 2), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 8), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 9), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_hdma, CLK_SRC_GROUP_AHB, 10), - clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AHB, 11), - clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_AHB, 12), - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AHB, 13), - - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), - clock_pgpio = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 2), - - /* For ADC, there are 2-stage clock source and divider configurations */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), - - /* For DAC, there are 2-stage clock source and divider configurations */ - clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), - clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), - clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), - clk_pll1clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll1, CLK_SRC_GROUP_SRC, 6), - clk_pll1clk3 = MAKE_CLOCK_NAME(sysctl_resource_clk3_pll1, CLK_SRC_GROUP_SRC, 7), -} clock_name_t; - -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @param [in] clock_name clock name - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Get the IP clock divider - * Note:This API return the direct clock divider - * @param [in] clock_name clock name - * @return IP clock divider - */ -uint32_t clock_get_divider(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @return #status_success Setting ADC clock source is successful - * #status_clk_invalid Invalid ADC clock - * #status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set DAC clock source - * @param[in] clock_name DAC clock name - * @param[in] src DAC clock source - * - * @return #status_success Setting DAC clock source is successful - * #status_clk_invalid Invalid DAC clock - * #status_clk_src_invalid Invalid DAC clock source - */ -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @return #status_success Setting Clock source and divider is successful. - * #status_clk_src_invalid clock source is invalid. - * #status_clk_fixed clock source and divider is a fixed value - * #status_clk_shared_ahb Clock is shared with the AHB clock - * #status_clk_shared_axi0 Clock is shared with the AXI0 clock - * #status_clk_shared_axi1 CLock is shared with the AXI1 clock - * #status_clk_shared_axi2 Clock is shared with the AXI2 clock - * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_csr_regs.h deleted file mode 100644 index 09c7fc113ff..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_csr_regs.h +++ /dev/null @@ -1,4276 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PIME (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PIME_MASK (0x8U) -#define CSR_MXSTATUS_PIME_SHIFT (3U) -#define CSR_MXSTATUS_PIME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK) -#define CSR_MXSTATUS_PIME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT) - -/* - * IME (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_IME_MASK (0x4U) -#define CSR_MXSTATUS_IME_SHIFT (2U) -#define CSR_MXSTATUS_IME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK) -#define CSR_MXSTATUS_IME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_dmamux_src.h deleted file mode 100644 index 90a7738d26b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_dmamux_src.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_GPTMR0_0 (0x0UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x1UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x2UL) -#define HPM_DMA_SRC_GPTMR0_3 (0x3UL) -#define HPM_DMA_SRC_GPTMR1_0 (0x4UL) -#define HPM_DMA_SRC_GPTMR1_1 (0x5UL) -#define HPM_DMA_SRC_GPTMR1_2 (0x6UL) -#define HPM_DMA_SRC_GPTMR1_3 (0x7UL) -#define HPM_DMA_SRC_UART0_RX (0x14UL) -#define HPM_DMA_SRC_UART0_TX (0x15UL) -#define HPM_DMA_SRC_UART1_RX (0x16UL) -#define HPM_DMA_SRC_UART1_TX (0x17UL) -#define HPM_DMA_SRC_UART2_RX (0x18UL) -#define HPM_DMA_SRC_UART2_TX (0x19UL) -#define HPM_DMA_SRC_UART3_RX (0x1AUL) -#define HPM_DMA_SRC_UART3_TX (0x1BUL) -#define HPM_DMA_SRC_I2C0 (0x24UL) -#define HPM_DMA_SRC_I2C1 (0x25UL) -#define HPM_DMA_SRC_I2C2 (0x26UL) -#define HPM_DMA_SRC_I2C3 (0x27UL) -#define HPM_DMA_SRC_SPI0_RX (0x28UL) -#define HPM_DMA_SRC_SPI0_TX (0x29UL) -#define HPM_DMA_SRC_SPI1_RX (0x2AUL) -#define HPM_DMA_SRC_SPI1_TX (0x2BUL) -#define HPM_DMA_SRC_SPI2_RX (0x2CUL) -#define HPM_DMA_SRC_SPI2_TX (0x2DUL) -#define HPM_DMA_SRC_SPI3_RX (0x2EUL) -#define HPM_DMA_SRC_SPI3_TX (0x2FUL) -#define HPM_DMA_SRC_MOT_0 (0x34UL) -#define HPM_DMA_SRC_MOT_1 (0x35UL) -#define HPM_DMA_SRC_MOT_2 (0x36UL) -#define HPM_DMA_SRC_MOT_3 (0x37UL) -#define HPM_DMA_SRC_MOT_4 (0x38UL) -#define HPM_DMA_SRC_MOT_5 (0x39UL) -#define HPM_DMA_SRC_MOT_6 (0x3AUL) -#define HPM_DMA_SRC_MOT_7 (0x3BUL) -#define HPM_DMA_SRC_XPI0_RX (0x3CUL) -#define HPM_DMA_SRC_XPI0_TX (0x3DUL) -#define HPM_DMA_SRC_ACMP0 (0x40UL) -#define HPM_DMA_SRC_ACMP1 (0x41UL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_gpiom_soc_drv.h deleted file mode 100644 index 01e0f0a5cd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_core0_fast = 2, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_interrupt.h deleted file mode 100644 index ac37b20a52d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_interrupt.h +++ /dev/null @@ -1,876 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; - -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */ -#define CONTEXT_REG_NUM (4*(16 + 4 + 20*2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS */ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define HPM_EXTERN_C extern "C" -#else -#define HPM_EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} -#endif -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - isr(); \ -} -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) \ -{ \ - isr();\ -} - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_iomux.h deleted file mode 100644 index 5051d4ab60f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_iomux.h +++ /dev/null @@ -1,423 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA11_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA14_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA26_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA26_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA27_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA27_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA28_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA28_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA29_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA29_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA30_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA30_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA31_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB08_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB09_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB10_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX03_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX05_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PY01_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY02_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PY02_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY05_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY06_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_l1c_drv.h deleted file mode 100644 index e3034e6e831..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 16KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(16 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 32B */ -#define HPM_L1C_CACHELINE_SIZE (32) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_misc.h deleted file mode 100644 index 367c61138a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_misc.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define ILM_LOCAL_BASE (0x0U) -#define ILM_SIZE_IN_BYTE (0x20000U) -#define DLM_LOCAL_BASE (0x80000U) -#define DLM_SIZE_IN_BYTE (0x20000U) -#define CORE0_ILM_SYSTEM_BASE (0x1040000U) -#define CORE0_DLM_SYSTEM_BASE (0x1060000U) - -#define ADDRESS_IN_ILM(address) \ - ((ILM_LOCAL_BASE) <= (address)) && \ - ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_DLM(address) \ - ((DLM_LOCAL_BASE) <= (address)) && \ - ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) - -#define DLM_TO_SYSTEM(address) \ - (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) -#define ILM_TO_SYSTEM(address) \ - (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) -#define SYSTEM_TO_DLM(address) \ - ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) - -#define HPM_CORE0 (0U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_otp_drv.c deleted file mode 100644 index a68fc69c0e0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - /* Wait until LDO is ready */ - while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { - } - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = HPM_OTP; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_otp_drv.h deleted file mode 100644 index b61c805a1df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_otp_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - -/** - * @brief Initialize OTP controller - */ -void otp_init(void); - -/** - * @brief De-initialize OTP controller - */ -void otp_deinit(void); - -/** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_shadow(uint32_t addr); - -/** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_ip(uint32_t addr); - -/** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - -/** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ -hpm_stat_t otp_reload(otp_region_t region); - -/** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - -/** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [in] val Data to be written - * @return API execution status - */ -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_pcfg_drv.h deleted file mode 100644 index 1920823cebd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_pcfg_drv.h +++ /dev/null @@ -1,497 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) -{ - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_plic_drv.h deleted file mode 100644 index 4c96737ece4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_plic_drv.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -#define HPM_PLIC_TRIGGER_TYPE_OFFSET (0x00001080UL) -#define HPM_PLIC_TRIGGER_TYPE_SHIFT_PER_SORUCE 1 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *) (base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *) (base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *) (base + - HPM_PLIC_PRIORITY_OFFSET + - ((irq - 1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Set interrupt trigger type to edge-triggerred - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_edge_trigger(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); - *current_ptr |= (1UL << (irq & 0x1F)); -} - -/** - * @brief Set interrupt trigger type to level-triggerred - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_level_trigger(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); - *current_ptr &= ~(1UL << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *) (base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *) (base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} - -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_pmic_iomux.h deleted file mode 100644 index a95ce61e50f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_pmic_iomux.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ppor_drv.h deleted file mode 100644 index bc7ee37f6ad..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ppor_drv.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_pmic_wdog = 1 << 24, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE &= ~mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE |= mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE |= mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE &= ~mask; -} - - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_romapi.h deleted file mode 100644 index 34fa7447366..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_romapi.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_soc_feature.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -typedef struct { - uint32_t region_start; - uint32_t region_end; - uint8_t aes_key[16]; - uint8_t nonce[8]; - uint8_t index; - bool enable; - bool valid; - bool lock; -} exip_region_context_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, - uint32_t serial_root_clk_freq, - uint32_t data_valid_time, - xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t - (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t - (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t - (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t - (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t - (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t - (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief EXIP driver interface - */ -typedef struct { - uint32_t version; - hpm_stat_t (*enable)(XPI_Type *base); - hpm_stat_t (*disable)(XPI_Type *base); - hpm_stat_t (*lock_reg_access)(XPI_Type *base); - hpm_stat_t (*configure_region)(XPI_Type *base, const exip_region_context_t *ctx); - - bool (*remap_config)(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset); - bool (*remap_enabled)(XPI_Type *base); - void (*remap_disable)(XPI_Type *base); - bool (*exip_region_config)(XPI_Type *base, uint32_t index, exip_region_param_t *param); - void (*exip_region_disable)(XPI_Type *base, uint32_t index); -} exip_driver_interface_t; - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const uint32_t reserved0; - const uint32_t reserved[4]; - const exip_driver_interface_t *exip_api_if; - const uint32_t family_id; -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); - fencei(); - return status; -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); - fencei(); - return status; -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if - ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API execution address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, - xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - return ROM_API_TABLE_ROOT->exip_api_if->remap_config(base, start, len, offset); -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->remap_disable(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - return ROM_API_TABLE_ROOT->exip_api_if->remap_enabled(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - bool result = ROM_API_TABLE_ROOT->exip_api_if->exip_region_config(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - ROM_API_TABLE_ROOT->exip_api_if->exip_region_disable(base, index); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->enable(base); - fencei(); -} - -/** - * @brief Disable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->disable(base); - fencei(); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ea3ba9e8f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union { - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ses_reg.xml deleted file mode 100644 index 6b799545949..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ses_reg.xml +++ /dev/null @@ -1,11684 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ses_riscv_cpu_regs.xml deleted file mode 100644 index 7e693311ca5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_ses_riscv_cpu_regs.xml +++ /dev/null @@ -1,808 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc.h deleted file mode 100644 index 7d922fb2b87..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc.h +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_X 3 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 4 /* GPIO0_Y IRQ */ -#define IRQn_GPTMR0 5 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 6 /* GPTMR1 IRQ */ -#define IRQn_UART0 13 /* UART0 IRQ */ -#define IRQn_UART1 14 /* UART1 IRQ */ -#define IRQn_UART2 15 /* UART2 IRQ */ -#define IRQn_UART3 16 /* UART3 IRQ */ -#define IRQn_I2C0 21 /* I2C0 IRQ */ -#define IRQn_I2C1 22 /* I2C1 IRQ */ -#define IRQn_I2C2 23 /* I2C2 IRQ */ -#define IRQn_I2C3 24 /* I2C3 IRQ */ -#define IRQn_SPI0 25 /* SPI0 IRQ */ -#define IRQn_SPI1 26 /* SPI1 IRQ */ -#define IRQn_SPI2 27 /* SPI2 IRQ */ -#define IRQn_SPI3 28 /* SPI3 IRQ */ -#define IRQn_TSNS 29 /* TSNS IRQ */ -#define IRQn_MBX0A 30 /* MBX0A IRQ */ -#define IRQn_MBX0B 31 /* MBX0B IRQ */ -#define IRQn_EWDG0 32 /* EWDG0 IRQ */ -#define IRQn_EWDG1 33 /* EWDG1 IRQ */ -#define IRQn_HDMA 34 /* HDMA IRQ */ -#define IRQn_USB0 51 /* USB0 IRQ */ -#define IRQn_XPI0 52 /* XPI0 IRQ */ -#define IRQn_PSEC 54 /* PSEC IRQ */ -#define IRQn_SECMON 55 /* SECMON IRQ */ -#define IRQn_FUSE 57 /* FUSE IRQ */ -#define IRQn_ADC0 58 /* ADC0 IRQ */ -#define IRQn_ACMP_0 62 /* ACMP_0 IRQ */ -#define IRQn_ACMP_1 63 /* ACMP_1 IRQ */ -#define IRQn_SYSCTL 64 /* SYSCTL IRQ */ -#define IRQn_PGPIO 65 /* PGPIO IRQ */ -#define IRQn_PTMR 66 /* PTMR IRQ */ -#define IRQn_PUART 67 /* PUART IRQ */ -#define IRQn_PEWDG 68 /* PEWDG IRQ */ -#define IRQn_BROWNOUT 69 /* BROWNOUT IRQ */ -#define IRQn_PAD_WAKEUP 70 /* PAD_WAKEUP IRQ */ -#define IRQn_DEBUG0 71 /* DEBUG0 IRQ */ -#define IRQn_DEBUG1 72 /* DEBUG1 IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0xC0000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF00D0000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF411C000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF0000000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF0004000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF4120000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF4124000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF0060000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF0064000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF0068000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF006C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0070000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0074000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0078000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF007C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) - -#include "hpm_crc_regs.h" -/* Address of CRC instances */ -/* CRC base address */ -#define HPM_CRC_BASE (0xF0080000UL) -/* CRC base pointer */ -#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) - -#include "hpm_tsns_regs.h" -/* Address of TSNS instances */ -/* TSNS base address */ -#define HPM_TSNS_BASE (0xF0090000UL) -/* TSNS base pointer */ -#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) - -#include "hpm_ewdg_regs.h" -/* Address of EWDG instances */ -/* EWDG0 base address */ -#define HPM_EWDG0_BASE (0xF00B0000UL) -/* EWDG0 base pointer */ -#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) -/* EWDG1 base address */ -#define HPM_EWDG1_BASE (0xF00B4000UL) -/* EWDG1 base pointer */ -#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) -/* PEWDG base address */ -#define HPM_PEWDG_BASE (0xF4128000UL) -/* PEWDG base pointer */ -#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C4000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dmav2_regs.h" -/* Address of DMAV2 instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C8000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF00D8000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF300C000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) - -/* Address of ROMC instances */ -/* ROMC base address */ -#define HPM_ROMC_BASE (0xF3014000UL) - -#include "hpm_sec_regs.h" -/* Address of SEC instances */ -/* SEC base address */ -#define HPM_SEC_BASE (0xF3044000UL) -/* SEC base pointer */ -#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) - -#include "hpm_mon_regs.h" -/* Address of MON instances */ -/* MON base address */ -#define HPM_MON_BASE (0xF3048000UL) -/* MON base pointer */ -#define HPM_MON ((MON_Type *) HPM_MON_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTP base address */ -#define HPM_OTP_BASE (0xF3050000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF3054000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF3080000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) - -#include "hpm_acmp_regs.h" -/* Address of ACMP instances */ -/* ACMP base address */ -#define HPM_ACMP_BASE (0xF30B0000UL) -/* ACMP base pointer */ -#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF4118000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) - -#include "hpm_pllctlv2_regs.h" -/* Address of PLLCTLV2 instances */ -/* PLLCTLV2 base address */ -#define HPM_PLLCTLV2_BASE (0xF40C0000UL) -/* PLLCTLV2 base pointer */ -#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF4100000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF4104000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR0 base address */ -#define HPM_PGPR0_BASE (0xF4110000UL) -/* PGPR0 base pointer */ -#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) -/* PGPR1 base address */ -#define HPM_PGPR1_BASE (0xF4114000UL) -/* PGPR1 base pointer */ -#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) - -#include "hpm_pdgo_regs.h" -/* Address of PDGO instances */ -/* PDGO base address */ -#define HPM_PDGO_BASE (0xF4134000UL) -/* PDGO base pointer */ -#define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc_feature.h deleted file mode 100644 index 5fac641a3c0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc_feature.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" -#include "hpm_soc_ip_feature.h" - -/* - * PLIC feature - */ -#define PLIC_SUPPORT_EDGE_TRIGGER (1) - -/* - * PMP/PMA Feature - */ -#define PMP_SUPPORT_PMA (0) - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (2U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (24U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (32U) -#define DMA_SOC_MAX_COUNT (1U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n) -#define DMA_SOC_HAS_IDLE_FLAG (1U) - -/* - * DMAMUX Section - */ -#define DMAMUX_SOC_WRITEONLY (1U) - -/* - * USB Section - */ -#define USB_SOC_MAX_COUNT (1U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* - * ADC Section - */ -#define ADC_SOC_IP_VERSION (3U) -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_SEQ_HCFG_EN (1U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) -#define ADC_SOC_NO_HW_TRIG_SRC (1U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * SDP Section - */ -#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) -#define SDP_HAS_SM3_SUPPORT (1U) -#define SDP_HAS_SM4_SUPPORT (1U) - -/* - * SOC Privilege mode - */ -#define SOC_HAS_S_MODE (0U) - -/* - * UART Section - */ -#define UART_SOC_FIFO_SIZE (16U) -#define UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */ - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) -#define SPI_SOC_FIFO_DEPTH (8U) - -/* - * OTP Section - */ -#define OTP_SOC_UUID_IDX (88U) -#define OTP_SOC_UUID_LEN (16U) /* in bytes */ - -/* - * PWM Section - */ -#define PWM_SOC_HRPWM_SUPPORT (0U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) -#define PWM_SOC_TIMER_RESET_SUPPORT (1U) - -/* - * TRGM section - */ -#define TRGM_SOC_HAS_FILTER_SHIFT (1U) -#define TRGM_SOC_HAS_DMAMUX_EN (1U) -#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U) -#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U) -#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U) - -/* - * MCAN Section - */ -#define MCAN_SOC_MAX_COUNT (0U) -#define MCAN_SOC_MSG_BUF_IN_IP (0U) -#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) -#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT - -/* - * EWDG Section - */ -#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) -#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) -#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1) -#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1) - -/* - * Sync Timer - */ -#define SYNT_SOC_HAS_TIMESTAMP (1U) - -/* - * GPIO - */ -#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U) - - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc_ip_feature.h deleted file mode 100644 index c6631fce221..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_soc_ip_feature.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* GPTMR related feature */ -#define HPM_IP_FEATURE_GPTMR_MONITOR 1 -#define HPM_IP_FEATURE_GPTMR_OP_MODE 1 - -/* UART related feature */ -#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 -#define HPM_IP_FEATURE_UART_FCRR 1 -#define HPM_IP_FEATURE_UART_RX_EN 1 -#define HPM_IP_FEATURE_UART_E00018_FIX 1 -#define HPM_IP_FEATURE_UART_9BIT_MODE 1 -#define HPM_IP_FEATURE_UART_ADDR_MATCH 1 -#define HPM_IP_FEATURE_UART_TRIG_MODE 1 -#define HPM_IP_FEATURE_UART_FINE_FIFO_THRLD 1 -#define HPM_IP_FEATURE_UART_IIR2 1 - -/* I2C related feature */ -#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 - -/* SPI related feature */ -#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 -#define HPM_IP_FEATURE_SPI_CS_SELECT 1 -#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 - -/* ADC16 related feature */ -#define HPM_IP_FEATURE_ADC16_HAS_MOT_EN 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_sysctl_drv.c deleted file mode 100644 index fee1b756cde..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_sysctl_drv.c +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) - -static inline bool sysctl_valid_cpu_index(uint8_t cpu) -{ - if (cpu != SYSCTL_CPU_CPU0) { - return false; - } - return true; -} - -hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) -{ - uint32_t i; - if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { - return status_invalid_argument; - } - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i]; - } - return status_success; -} - -static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[cpu].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); -} - -hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); -} - -static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[cpu].GPR[start + i] = *(data + i); - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) -{ - ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & - ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | - SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | - (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | - SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | - SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | - SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | - SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | - SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = { 0 }; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].GPR[0] = entry; - ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); - return status_success; -} - -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 0, entry); -} - -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable) -{ - uint32_t index, offset; - if (resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource) -{ - uint32_t index, offset; - bool enable; - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | - (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, - clock_source_t source, - uint32_t cpu_div, - uint32_t ahb_sub_div) -{ - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - - uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; - if (origin_cpu_div == cpu_div) { - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - } - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); - - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - - return status_success; -} - -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) -{ - if (source >= clock_source_adc_clk_end) { - return status_invalid_argument; - } - uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); - if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { - return status_invalid_argument; - } - - ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); - - return status_success; -} - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_sysctl_drv.h deleted file mode 100644 index 591602d8a10..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/hpm_sysctl_drv.h +++ /dev/null @@ -1,1175 +0,0 @@ -/** - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - - sysctl_retention_domain_xtal24m = 4, - sysctl_retention_domain_pll0 = 5, - sysctl_retention_domain_pll1 = 6, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_cpu0, -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = 0, - sysctl_resource_cpx0 = 1, - sysctl_resource_pow_cpu0 = 21, - sysctl_resource_rst_soc = 22, - sysctl_resource_rst_cpu0 = 23, - sysctl_resource_xtal = 32, - sysctl_resource_pll0 = 33, - sysctl_resource_clk0_pll0 = 34, - sysctl_resource_clk1_pll0 = 35, - sysctl_resource_clk2_pll0 = 36, - sysctl_resource_pll1 = 37, - sysctl_resource_clk0_pll1 = 38, - sysctl_resource_clk1_pll1 = 39, - sysctl_resource_clk2_pll1 = 40, - sysctl_resource_clk3_pll1 = 41, - sysctl_resource_pll0_ref = 42, - sysctl_resource_pll1_ref = 43, - sysctl_resource_clk_top_cpu0 = 64, - sysctl_resource_clk_top_mchtmr0 = 65, - sysctl_resource_clk_top_gptmr0 = 74, - sysctl_resource_clk_top_gptmr1 = 75, - sysctl_resource_clk_top_i2c0 = 78, - sysctl_resource_clk_top_i2c1 = 79, - sysctl_resource_clk_top_i2c2 = 80, - sysctl_resource_clk_top_i2c3 = 81, - sysctl_resource_clk_top_spi0 = 82, - sysctl_resource_clk_top_spi1 = 83, - sysctl_resource_clk_top_spi2 = 84, - sysctl_resource_clk_top_spi3 = 85, - sysctl_resource_clk_top_uart0 = 86, - sysctl_resource_clk_top_uart1 = 87, - sysctl_resource_clk_top_uart2 = 88, - sysctl_resource_clk_top_uart3 = 89, - sysctl_resource_clk_top_uart4 = 90, - sysctl_resource_clk_top_xip0 = 94, - sysctl_resource_clk_top_ana0 = 95, - sysctl_resource_clk_top_ana1 = 96, - sysctl_resource_clk_top_ana2 = 97, - sysctl_resource_clk_top_ana3 = 98, - sysctl_resource_clk_top_ref0 = 99, - sysctl_resource_clk_top_ref1 = 100, - sysctl_resource_clk_top_adc0 = 101, - - sysctl_resource_linkable_start = 256, - sysctl_resource_ahb0 = 256, - sysctl_resource_lmm0 = 257, - sysctl_resource_mchtmr0 = 258, - sysctl_resource_rom0 = 259, - sysctl_resource_ptpc = 264, - sysctl_resource_gptmr0 = 269, - sysctl_resource_gptmr1 = 270, - sysctl_resource_i2c0 = 273, - sysctl_resource_i2c1 = 274, - sysctl_resource_i2c2 = 275, - sysctl_resource_i2c3 = 276, - sysctl_resource_spi0 = 277, - sysctl_resource_spi1 = 278, - sysctl_resource_spi2 = 279, - sysctl_resource_spi3 = 280, - sysctl_resource_uart0 = 281, - sysctl_resource_uart1 = 282, - sysctl_resource_uart2 = 283, - sysctl_resource_uart3 = 284, - sysctl_resource_uart4 = 285, - sysctl_resource_wdg0 = 289, - sysctl_resource_wdg1 = 290, - sysctl_resource_mbx0 = 291, - sysctl_resource_tsns = 292, - sysctl_resource_crc0 = 293, - sysctl_resource_adc0 = 294, - sysctl_resource_acmp = 298, - sysctl_resource_kman = 304, - sysctl_resource_gpio = 305, - sysctl_resource_hdma = 306, - sysctl_resource_xpi0 = 307, - sysctl_resource_usb0 = 308, - sysctl_resource_ref0 = 309, - sysctl_resource_ref1 = 310, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ - sysctl_resource_mode_force_on, /*!< Force the resource clock on */ - sysctl_resource_mode_force_off, /*!< Force the resource clock off */ -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, - clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, - clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, - clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, - clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, - clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, - clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, - clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, - clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, - clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, - clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, - clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, - clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, - clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, - clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, - clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, - clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, - clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, - clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, - clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, - clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, - clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, - clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, - - clock_node_adc_start, - clock_node_adc0 = clock_node_adc_start, - clock_node_adc1, - - clock_node_dac_start, - clock_node_dac0 = clock_node_dac_start, - clock_node_dac1, - clock_node_end, - - clock_node_core_start = 0xfc, - clock_node_cpu0 = clock_node_core_start, - clock_node_axi, - clock_node_ahb, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll0_clk1 = 2, - clock_source_pll0_clk2 = 3, - clock_source_pll1_clk0 = 4, - clock_source_pll1_clk1 = 5, - clock_source_pll1_clk2 = 6, - clock_source_pll1_clk3 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC/I2S clock sources - */ -typedef enum { - clock_source_adc_ana_clock = 0, - clock_source_adc_ahb_clock = 1, - clock_source_adc_clk_end, -} clock_source_adc_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -typedef enum { - monitor_target_clk_32k = 1, - monitor_target_clk_irc24m = 2, - monitor_target_clk_xtal_24m = 3, - monitor_target_clk_usb0_phy = 4, - monitor_target_clk0_osc0 = 20, - monitor_target_clk0_pll0 = 21, - monitor_target_clk0_pll1 = 22, - monitor_target_clk0_pll2 = 23, - monitor_target_clk1_pll0 = 24, - monitor_target_clk1_pll1 = 25, - monitor_target_clk1_pll2 = 26, - monitor_target_clk1_pll3 = 27, - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_gptmr0 = 138, - monitor_target_clk_top_gptmr1 = 139, - monitor_target_clk_top_i2c0 = 142, - monitor_target_clk_top_i2c1 = 143, - monitor_target_clk_top_i2c2 = 144, - monitor_target_clk_top_i2c3 = 145, - monitor_target_clk_top_spi0 = 146, - monitor_target_clk_top_spi1 = 147, - monitor_target_clk_top_spi2 = 148, - monitor_target_clk_top_spi3 = 149, - monitor_target_clk_top_uart0 = 150, - monitor_target_clk_top_uart1 = 151, - monitor_target_clk_top_uart2 = 152, - monitor_target_clk_top_uart3 = 153, - monitor_target_clk_top_uart4 = 154, - monitor_target_clk_top_xpi0 = 158, - monitor_target_clk_top_ana0 = 159, - monitor_target_clk_top_ana1 = 160, - monitor_target_clk_top_ana2 = 161, - monitor_target_clk_top_ana3 = 162, - monitor_target_clk_top_ref0 = 163, - monitor_target_clk_top_ref1 = 164, -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | - (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit_high, - uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = - (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | - SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Disable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, - uint8_t cpu_index, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - uint8_t set_mask = 0x1; - if (domain < sysctl_retention_domain_xtal24m) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Retain target domain for specific CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); -} - -/** - * @brief Check if cpu clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; -} - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Preserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Unpreserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Get target CPU0 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 0, status_index); -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index, - uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Check CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); -} - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Disable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); -} - - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Lock CPU gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); -} - -/** - * @brief Lock CPU lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 0); -} - -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) -{ - ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); -} - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 0, mode); -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Get CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); -} - -/** - * @brief Get CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 0); -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); - -/** - * @brief Configure CPU domain clock - * @param ptr SYSCTL base address - * @param source clock source to be used - * @param cpu_div CPU divider - * @param ahb_sub_div AHB BUS divider based on divided CPU clock - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, uint32_t ahb_sub_div); - -/** - * @brief Set ADC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); - - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); - -/** - * @brief Save data to GPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved from GPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/soc_modules.list deleted file mode 100644 index 30100a8a071..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/soc_modules.list +++ /dev/null @@ -1,37 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_CRC=y -HPMSOC_HAS_HPMSDK_TSNS=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_EWDG=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMAV2=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_SEC=y -HPMSOC_HAS_HPMSDK_MON=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_ACMP=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_PLLCTLV2=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_PDGO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/system.c deleted file mode 100644 index 3ea422c42ea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/system.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif - -#ifdef USE_S_MODE_IRQ - disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#else - disable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - - disable_irq_from_intc(); -#ifdef USE_S_MODE_IRQ - disable_s_irq_from_intc(); -#endif - - enable_plic_feature(); - enable_irq_from_intc(); - -#ifdef USE_S_MODE_IRQ - delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); - enable_s_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#endif -#else -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash.ld deleted file mode 100644 index ec881b8787c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash.ld +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index 9ddbfc987b4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/ram.ld deleted file mode 100644 index 01c381d9677..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/ram.ld +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/start.S deleted file mode 100644 index 2f803b378aa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/gcc/start.S +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - la tp, __thread_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/flash_uf2.icf deleted file mode 100644 index 460c9efbb4b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { - block RW_DATA - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/flash_xip.icf deleted file mode 100644 index 1a15d12848d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { - block RW_DATA - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .nor_cfg_option, - section .boot_header, - section .fw_info_table, - section .dc_info - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/ram.icf deleted file mode 100644 index c8c79f20fe8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/ram.icf +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { - block RW_DATA - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/startup.s deleted file mode 100644 index 073436a68d9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/iar/startup.s +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/reset.c deleted file mode 100644 index ed406e64ff4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash.icf deleted file mode 100644 index d2ed190b152..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash.icf +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 58c892e704f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash_xip.icf deleted file mode 100644 index 5c33e331637..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xf0400000 size 32k]; /* AHB_SRAM */ - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/ram.icf deleted file mode 100644 index b5f384d7204..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/ram.icf +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/startup.s deleted file mode 100644 index 8a7036e137d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/segger/startup.s +++ /dev/null @@ -1,419 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/trap.c deleted file mode 100644 index 9c084c3af17..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/trap.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ -#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ -#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ -#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ -#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ -#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : : "t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : : "a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : : "r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/vectors.h deleted file mode 100644 index 00004c044ca..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5301/toolchains/vectors.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(9) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* Reserved */ - IRQ_DEFAULT_HANDLER 8 /* Reserved */ - IRQ_DEFAULT_HANDLER 9 /* Reserved */ - IRQ_DEFAULT_HANDLER 10 /* Reserved */ - IRQ_DEFAULT_HANDLER 11 /* Reserved */ - IRQ_DEFAULT_HANDLER 12 /* Reserved */ - IRQ_DEFAULT_HANDLER 13 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* Reserved */ - IRQ_DEFAULT_HANDLER 18 /* Reserved */ - IRQ_DEFAULT_HANDLER 19 /* Reserved */ - IRQ_DEFAULT_HANDLER 20 /* Reserved */ - IRQ_DEFAULT_HANDLER 21 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 22 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 23 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 24 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* TSNS IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* EWDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* EWDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* Reserved */ - IRQ_DEFAULT_HANDLER 36 /* Reserved */ - IRQ_DEFAULT_HANDLER 37 /* Reserved */ - IRQ_DEFAULT_HANDLER 38 /* Reserved */ - IRQ_DEFAULT_HANDLER 39 /* Reserved */ - IRQ_DEFAULT_HANDLER 40 /* Reserved */ - IRQ_DEFAULT_HANDLER 41 /* Reserved */ - IRQ_DEFAULT_HANDLER 42 /* Reserved */ - IRQ_DEFAULT_HANDLER 43 /* Reserved */ - IRQ_DEFAULT_HANDLER 44 /* Reserved */ - IRQ_DEFAULT_HANDLER 45 /* Reserved */ - IRQ_DEFAULT_HANDLER 46 /* Reserved */ - IRQ_DEFAULT_HANDLER 47 /* Reserved */ - IRQ_DEFAULT_HANDLER 48 /* Reserved */ - IRQ_DEFAULT_HANDLER 49 /* Reserved */ - IRQ_DEFAULT_HANDLER 50 /* Reserved */ - IRQ_DEFAULT_HANDLER 51 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* Reserved */ - IRQ_DEFAULT_HANDLER 54 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* Reserved */ - IRQ_DEFAULT_HANDLER 57 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* Reserved */ - IRQ_DEFAULT_HANDLER 60 /* Reserved */ - IRQ_DEFAULT_HANDLER 61 /* Reserved */ - IRQ_DEFAULT_HANDLER 62 /* ACMP_0 IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* ACMP_1 IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* PEWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* PAD_WAKEUP IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* DEBUG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* DEBUG1 IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(9) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 7 /* Reserved */ - IRQ_HANDLER 8 /* Reserved */ - IRQ_HANDLER 9 /* Reserved */ - IRQ_HANDLER 10 /* Reserved */ - IRQ_HANDLER 11 /* Reserved */ - IRQ_HANDLER 12 /* Reserved */ - IRQ_HANDLER 13 /* UART0 IRQ handler */ - IRQ_HANDLER 14 /* UART1 IRQ handler */ - IRQ_HANDLER 15 /* UART2 IRQ handler */ - IRQ_HANDLER 16 /* UART3 IRQ handler */ - IRQ_HANDLER 17 /* Reserved */ - IRQ_HANDLER 18 /* Reserved */ - IRQ_HANDLER 19 /* Reserved */ - IRQ_HANDLER 20 /* Reserved */ - IRQ_HANDLER 21 /* I2C0 IRQ handler */ - IRQ_HANDLER 22 /* I2C1 IRQ handler */ - IRQ_HANDLER 23 /* I2C2 IRQ handler */ - IRQ_HANDLER 24 /* I2C3 IRQ handler */ - IRQ_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_HANDLER 29 /* TSNS IRQ handler */ - IRQ_HANDLER 30 /* MBX0A IRQ handler */ - IRQ_HANDLER 31 /* MBX0B IRQ handler */ - IRQ_HANDLER 32 /* EWDG0 IRQ handler */ - IRQ_HANDLER 33 /* EWDG1 IRQ handler */ - IRQ_HANDLER 34 /* HDMA IRQ handler */ - IRQ_HANDLER 35 /* Reserved */ - IRQ_HANDLER 36 /* Reserved */ - IRQ_HANDLER 37 /* Reserved */ - IRQ_HANDLER 38 /* Reserved */ - IRQ_HANDLER 39 /* Reserved */ - IRQ_HANDLER 40 /* Reserved */ - IRQ_HANDLER 41 /* Reserved */ - IRQ_HANDLER 42 /* Reserved */ - IRQ_HANDLER 43 /* Reserved */ - IRQ_HANDLER 44 /* Reserved */ - IRQ_HANDLER 45 /* Reserved */ - IRQ_HANDLER 46 /* Reserved */ - IRQ_HANDLER 47 /* Reserved */ - IRQ_HANDLER 48 /* Reserved */ - IRQ_HANDLER 49 /* Reserved */ - IRQ_HANDLER 50 /* Reserved */ - IRQ_HANDLER 51 /* USB0 IRQ handler */ - IRQ_HANDLER 52 /* XPI0 IRQ handler */ - IRQ_HANDLER 53 /* Reserved */ - IRQ_HANDLER 54 /* PSEC IRQ handler */ - IRQ_HANDLER 55 /* SECMON IRQ handler */ - IRQ_HANDLER 56 /* Reserved */ - IRQ_HANDLER 57 /* FUSE IRQ handler */ - IRQ_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_HANDLER 59 /* Reserved */ - IRQ_HANDLER 60 /* Reserved */ - IRQ_HANDLER 61 /* Reserved */ - IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ - IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ - IRQ_HANDLER 64 /* SYSCTL IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PTMR IRQ handler */ - IRQ_HANDLER 67 /* PUART IRQ handler */ - IRQ_HANDLER 68 /* PEWDG IRQ handler */ - IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 7 /* Reserved */ - IRQ_HANDLER 8 /* Reserved */ - IRQ_HANDLER 9 /* Reserved */ - IRQ_HANDLER 10 /* Reserved */ - IRQ_HANDLER 11 /* Reserved */ - IRQ_HANDLER 12 /* Reserved */ - IRQ_HANDLER 13 /* UART0 IRQ handler */ - IRQ_HANDLER 14 /* UART1 IRQ handler */ - IRQ_HANDLER 15 /* UART2 IRQ handler */ - IRQ_HANDLER 16 /* UART3 IRQ handler */ - IRQ_HANDLER 17 /* Reserved */ - IRQ_HANDLER 18 /* Reserved */ - IRQ_HANDLER 19 /* Reserved */ - IRQ_HANDLER 20 /* Reserved */ - IRQ_HANDLER 21 /* I2C0 IRQ handler */ - IRQ_HANDLER 22 /* I2C1 IRQ handler */ - IRQ_HANDLER 23 /* I2C2 IRQ handler */ - IRQ_HANDLER 24 /* I2C3 IRQ handler */ - IRQ_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_HANDLER 29 /* TSNS IRQ handler */ - IRQ_HANDLER 30 /* MBX0A IRQ handler */ - IRQ_HANDLER 31 /* MBX0B IRQ handler */ - IRQ_HANDLER 32 /* EWDG0 IRQ handler */ - IRQ_HANDLER 33 /* EWDG1 IRQ handler */ - IRQ_HANDLER 34 /* HDMA IRQ handler */ - IRQ_HANDLER 35 /* Reserved */ - IRQ_HANDLER 36 /* Reserved */ - IRQ_HANDLER 37 /* Reserved */ - IRQ_HANDLER 38 /* Reserved */ - IRQ_HANDLER 39 /* Reserved */ - IRQ_HANDLER 40 /* Reserved */ - IRQ_HANDLER 41 /* Reserved */ - IRQ_HANDLER 42 /* Reserved */ - IRQ_HANDLER 43 /* Reserved */ - IRQ_HANDLER 44 /* Reserved */ - IRQ_HANDLER 45 /* Reserved */ - IRQ_HANDLER 46 /* Reserved */ - IRQ_HANDLER 47 /* Reserved */ - IRQ_HANDLER 48 /* Reserved */ - IRQ_HANDLER 49 /* Reserved */ - IRQ_HANDLER 50 /* Reserved */ - IRQ_HANDLER 51 /* USB0 IRQ handler */ - IRQ_HANDLER 52 /* XPI0 IRQ handler */ - IRQ_HANDLER 53 /* Reserved */ - IRQ_HANDLER 54 /* PSEC IRQ handler */ - IRQ_HANDLER 55 /* SECMON IRQ handler */ - IRQ_HANDLER 56 /* Reserved */ - IRQ_HANDLER 57 /* FUSE IRQ handler */ - IRQ_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_HANDLER 59 /* Reserved */ - IRQ_HANDLER 60 /* Reserved */ - IRQ_HANDLER 61 /* Reserved */ - IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ - IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ - IRQ_HANDLER 64 /* SYSCTL IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PTMR IRQ handler */ - IRQ_HANDLER 67 /* PUART IRQ handler */ - IRQ_HANDLER 68 /* PEWDG IRQ handler */ - IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/HPM5361_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/HPM5361_svd.xml deleted file mode 100644 index cb3c9ab3298..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/HPM5361_svd.xml +++ /dev/null @@ -1,29216 +0,0 @@ - - - HPMICRO - HPM5361 - HPM5300 - 1.0 - HPM5300 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x8f0 - registers - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - 15 - 0x10 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - PD[%s] - no description available - 0x800 - - VALUE - GPIO dual edge interrupt enable value - 0x0 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable -0: single edge interrupt -1: dual edge interrupt enable - 0 - 1 - read-write - - - - - SET - GPIO dual edge interrupt enable set - 0x4 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable set -0: keep original edge interrupt type -1: dual edge interrupt enable - 0 - 1 - read-write - - - - - CLEAR - GPIO dual edge interrupt enable clear - 0x8 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable clear -0: keep original edge interrupt type -1: single edge interrupt enable - 0 - 1 - read-write - - - - - TOGGLE - GPIO dual edge interrupt enable toggle - 0xc - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable toggle -0: keep original edge interrupt type -1: change original edge interrupt type to another one. - 0 - 1 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf00d0000 - - - PGPIO - PGPIO - GPIO - 0xf411c000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x201000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 1 - 0x80 - target0 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 1 - 0x1000 - target0 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPTMR0 - GPTMR0 - GPTMR - 0xf0000000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x8003FFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - OPMODE - 0: round mode -1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. -NOTE: reload irq will be always set at one-shot mode at end - 17 - 1 - read-write - - - MONITOR_SEL - set to monitor input signal high level time(chan_meas_high) -clr to monitor input signal period(chan_meas_prd) - 16 - 1 - read-write - - - MONITOR_EN - set to monitor input signal period or high level time. -When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts -* only can be used when trig_mode is selected as measure mode(100) -* the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. -if no posedge after reload for more than val_1, will also assert irq_capt - 15 - 1 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - GPTMR1 - GPTMR1 - GPTMR - 0xf0004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf0008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf000c000 - - - PTMR - PTMR - GPTMR - 0xf4120000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x4 - 0x3c - registers - - - - IDLE_CFG - Idle Configuration Register - 0x4 - 32 - 0x00000000 - 0x03FF0BFF - - - TX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if TX pin is logic one -1 - Treat as idle if UART state machine state is idle - 25 - 1 - read-write - - - TX_IDLE_EN - UART TX Idle Detect Enable -0 - Disable -1 - Enable - 24 - 1 - read-write - - - TX_IDLE_THR - Threshold for UART transmit Idle detection (in terms of bits) - 16 - 8 - read-write - - - RXEN - UART receive enable. -0 - hold RX input to high, avoide wrong data input when config pinmux -1 - bypass RX input from PIN -software should set it after config pinmux - 11 - 1 - read-write - - - RX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if RX pin is logic one -1 - Treat as idle if UART state machine state is idle - 9 - 1 - read-write - - - RX_IDLE_EN - UART Idle Detect Enable -0 - Disable -1 - Enable -it should be enabled if enable address match feature - 8 - 1 - read-write - - - RX_IDLE_THR - Threshold for UART Receive Idle detection (in terms of bits) - 0 - 8 - read-write - - - - - ADDR_CFG - address match config register - 0x8 - 32 - 0x00000000 - 0x001FFFFF - - - TXEN_9BIT - set to use 9bit mode for transmitter, -will set the MSB for the first character as address flag, keep 0 for others. - 20 - 1 - read-write - - - RXEN_ADDR_MSB - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). -Clr to use first character as address. -Only needed if enable address match feature - 19 - 1 - read-write - - - RXEN_9BIT - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set - 18 - 1 - read-write - - - A1_EN - enable addr1 compare for the first character. -If a1_en OR a0_en, then do not receive data if address not match. -If ~a1_en AND ~a0_en, the receive all data like before. -NOTE: should set idle_tmout_en if enable address match feature - 17 - 1 - read-write - - - A0_EN - enable addr0 compare for the first character - 16 - 1 - read-write - - - ADDR1 - address 1 fileld. -in 9bit mode, this is the full address byte. -For other mode(8/7/6/5bit), MSB should be set for address flag. -If want address==0 to be matched at 8bit mode, should set addr1=0x80 - 8 - 8 - read-write - - - ADDR0 - address 0 field. - 0 - 8 - read-write - - - - - IIR2 - Interrupt Identification Register2 - 0xc - 32 - 0x00000001 - 0xF80000CF - - - RXIDLE_FLAG - UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear -0 - UART RX is busy -1 - UART RX is idle - 31 - 1 - write-only - - - TXIDLE_FLAG - UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear -0 - UART TX is busy -1 - UART TX is idle - 30 - 1 - write-only - - - ADDR_MATCH - address match irq status, assert if either address match(and enabled). Write one clear -NOTE: the address byte may not moved by DMA at this point. -User can wait next addr_match_idle irq for the whole data include address - 29 - 1 - write-only - - - ADDR_MATCH_IDLE - address match and idle irq status, assert at rx bus idle if address match event triggered. -Write one clear; - 28 - 1 - write-only - - - DATA_LOST - assert if data lost before address match status, write one clear; -It will not assert if no address match occurs - 27 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - FCRR - FIFO Control Register config - 0x18 - 32 - 0x00000000 - 0x008F0FFF - - - FIFOT4EN - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) -clr to use 2bit(TFIFOT and RFIFOT) - 23 - 1 - read-write - - - TFIFOT4 - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. - 16 - 4 - read-write - - - RFIFOT4 - rxfifo threshold(0 for 1byte, 0xF for 16bytes). -Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled - 8 - 4 - read-write - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - read-write - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - read-write - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - read-write - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - read-write - - - - - MOTO_CFG - moto system control register - 0x1c - 32 - 0x00000000 - 0x8000FFF0 - - - SWTRG - software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. -Hardware auto reset. - 31 - 1 - write-only - - - TXSTP_BITS - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits - 8 - 8 - read-write - - - HWTRG_EN - set to enable hardware trigger(trigger from moto is shared by other UART) - 7 - 1 - read-write - - - TRG_MODE - set to enable trigger mode. -software should push needed data into txbuffer frist, uart will not start transmission at this time. -User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty -NOTE: the hw_trigger should be pulse signal from trig mux. - 6 - 1 - read-write - - - TRG_CLR_RFIFO - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. - 5 - 1 - read-write - - - TXSTOP_INSERT - set to insert STOP bits between each tx byte till tx fifo empty. -NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set - 4 - 1 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0xF800000F - - - ERXIDLE - Enable Receive Idle interrupt -0 - Disable Idle interrupt -1 - Enable Idle interrupt - 31 - 1 - read-write - - - ETXIDLE - enable transmit idle interrupt - 30 - 1 - read-write - - - EADDRM - enable ADDR_MATCH interrupt - 29 - 1 - read-write - - - EADDRM_IDLE - enable ADDR_MATCH_IDLE interrupt - 28 - 1 - read-write - - - EDATLOST - enable DATA_LOST interrupt - 27 - 1 - read-write - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x800000CF - - - RXIDLE_FLAG - UART IDLE Flag -0 - UART is busy -1 - UART is idle -NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - 31 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0xC01F1FFF - - - RXIDLE - rxidle after timeout, clear after rx idle condition not match - 31 - 1 - read-only - - - TXIDLE - txidle after timeout, clear after tx idle condition not match - 30 - 1 - read-only - - - RFIFO_NUM - data bytes in rxfifo not read - 16 - 5 - read-only - - - TFIFO_NUM - data bytes in txfifo not sent - 8 - 5 - read-only - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - PUART - PUART - UART - 0xf4124000 - - - I2C0 - I2C0 - I2C - 0xf0060000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00905E00 - 0xFFFFFFFF - - - DATACNT_HIGH - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 24 - 8 - read-write - - - RESET_LEN - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - 20 - 4 - read-write - - - RESET_HOLD_SCKIN - set to hold input clock to high when reset is active - 14 - 1 - read-write - - - RESET_ON - set to send reset signals(just toggle clock bus defined by reset_len). -this register is clered when reset is end, can't be cleared by software - 13 - 1 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf0064000 - - - I2C2 - I2C2 - I2C - 0xf0068000 - - - I2C3 - I2C3 - I2C - 0xf006c000 - - - SPI0 - SPI0 - SPI - 0xf0070000 - - 0x4 - 0x7c - registers - - - - wr_trans_cnt - Transfer count for write data - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 0 - 32 - read-write - - - - - rd_trans_cnt - Transfer count for read data - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 32 - read-write - - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - DirectIO - Direct IO Control Register - 0x14 - 32 - 0x00003100 - 0x013F3F3F - - - DIRECTIOEN - Enable Direct IO -0x0: Disable -0x1: Enable - 24 - 1 - read-write - - - HOLD_OE - Output enable for the SPI Flash hold signal - 21 - 1 - read-write - - - WP_OE - Output enable for the SPI Flash write protect signal - 20 - 1 - read-write - - - MISO_OE - Output enable fo the SPI MISO signal - 19 - 1 - read-write - - - MOSI_OE - Output enable for the SPI MOSI signal - 18 - 1 - read-write - - - SCLK_OE - Output enable for the SPI SCLK signal - 17 - 1 - read-write - - - CS_OE - Output enable for SPI CS (chip select) signal - 16 - 1 - read-write - - - HOLD_O - Output value for the SPI Flash hold signal - 13 - 1 - read-write - - - WP_O - Output value for the SPI Flash write protect signal - 12 - 1 - read-write - - - MISO_O - Output value for the SPI MISO signal - 11 - 1 - read-write - - - MOSI_O - Output value for the SPI MOSI signal - 10 - 1 - read-write - - - SCLK_O - Output value for the SPI SCLK signal - 9 - 1 - read-write - - - CS_O - Output value for the SPI CS (chip select) signal - 8 - 1 - read-write - - - HOLD_I - Status of the SPI Flash hold signal - 5 - 1 - read-only - - - WP_I - Status of the SPI Flash write protect signal - 4 - 1 - read-only - - - MISO_I - Status of the SPI MISO signal - 3 - 1 - read-only - - - MOSI_I - Status of the SPI MOSI signal - 2 - 1 - read-only - - - SCLK_I - Status of the SPI SCLK signal - 1 - 1 - read-only - - - CS_I - Status of the SPI CS (chip select) signal - 0 - 1 - read-only - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x0FFFFF1F - - - CS_EN - No description available - 24 - 4 - read-write - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - SlvDataWCnt - WCnt - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - SlvDataRCnt - RCnt - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0074000 - - - SPI2 - SPI2 - SPI - 0xf0078000 - - - SPI3 - SPI3 - SPI - 0xf007c000 - - - CRC - CRC - CRC - 0xf0080000 - - 0x0 - 0x200 - registers - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - pre_set - &index0 pre set for crc setting - 0x0 - 32 - 0x00000000 - 0x000000FF - - - PRE_SET - 0: no pre set -1: CRC32 -2: CRC32-AUTOSAR -3: CRC16-CCITT -4: CRC16-XMODEM -5: CRC16-MODBUS -1: CRC32 -2: CRC32-autosar -3: CRC16-ccitt -4: CRC16-xmodem -5: CRC16-modbus -6: crc16_dnp -7: crc16_x25 -8: crc16_usb -9: crc16_maxim -10: crc16_ibm -11: crc8_maxim -12: crc8_rohc -13: crc8_itu -14: crc8 -15: crc5_usb - 0 - 8 - read-write - - - - - clr - chn&index0 clear crc result and setting - 0x4 - 32 - 0x00000000 - 0x00000001 - - - CLR - write 1 to clr crc setting and result for its channel. -always read 0. - 0 - 1 - read-write - - - - - poly - chn&index0 poly - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - poly setting - 0 - 32 - read-write - - - - - init_data - chn&index0 init_data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INIT_DATA - initial data of CRC - 0 - 32 - read-write - - - - - xorout - chn&index0 xorout - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XOROUT - XOR for CRC result - 0 - 32 - read-write - - - - - misc_setting - chn&index0 misc_setting - 0x14 - 32 - 0x00000000 - 0x0101013F - - - BYTE_REV - 0: no wrap input byte order -1: wrap input byte order - 24 - 1 - read-write - - - REV_OUT - 0: no wrap output bit order -1: wrap output bit order - 16 - 1 - read-write - - - REV_IN - 0: no wrap input bit order -1: wrap input bit order - 8 - 1 - read-write - - - POLY_WIDTH - crc data length - 0 - 6 - read-write - - - - - data - chn&index0 data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data for crc - 0 - 32 - read-write - - - - - result - chn&index0 result - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - crc result - 0 - 32 - read-write - - - - - - - - TSNS - TSNS - TSNS - 0xf0090000 - - 0x0 - 0x3c - registers - - - - T - Temperature - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - Maximum Temperature - 0x4 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - Minimum Temperature - 0x8 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - Sample age - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - Status - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - write-only - - - - - CONFIG - Configuration - 0x14 - 32 - 0x00600300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valid from 24-255, default 96 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, default in 3 -0: measure and return -1: twice and average -2: 4 times and average -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - Sample validity - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - Temperature flag - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - Maximum temperature to interrupt - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - Minimum temperature to interrupt - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - Maximum temperature to reset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - Minimum temperature to reset - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - Configuration in asynchronous mode - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - Polarity of internal comparator - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - Advance configuration - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - EWDG0 - EWDG0 - EWDG - 0xf00b0000 - - 0x0 - 0x28 - registers - - - - CTRL0 - wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x0 - 32 - 0x00000000 - 0x2FE2F03F - - - CLK_SEL - clock select -0：bus clock -1：ext clock - 29 - 1 - read-write - - - DIV_VALUE - clock divider, the clock divider works as 2 ^ div_value for wdt counter - 25 - 3 - read-write - - - WIN_EN - window mode enable - 24 - 1 - read-write - - - WIN_LOWER - Once window mode is opened, the lower counter value to refresh wdt -00: 4/8 overtime value -01: 5/8 of overtime value -10: 6/8 of overtime value -11: 7/8 of overtime value - 22 - 2 - read-write - - - CFG_LOCK - The register is locked and unlock is needed before re-config registers -Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. -The register update needs to be finished in the required period defined by UPD_OT_TIME register - 21 - 1 - read-write - - - OT_SELF_CLEAR - overtime reset can be self released after 32 function cycles - 17 - 1 - read-write - - - REF_OT_REQ - If refresh event has to be limited into a period after refresh unlocked. -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 15 - 1 - read-write - - - WIN_UPPER - The upper threshold of window value -The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value -If this register value is zero, then no upper level limitation - 12 - 3 - read-write - - - REF_LOCK - WDT refresh has to be unlocked firstly once refresh lock is enable. - 5 - 1 - read-write - - - REF_UNLOCK_MEC - Unlock refresh mechanism -00: the required unlock password is the same with refresh_psd_register -01: the required unlock password is a ring shift left value of refresh_psd_register -10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is -11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - 3 - 2 - read-write - - - EN_DBG - WTD enable or not in debug mode - 2 - 1 - read-write - - - EN_LP - WDT enable or not in low power mode -2'b00: wdt is halted once in low power mode -2'b01: wdt will work with 1/4 normal clock freq in low power mode -2'b10: wdt will work with 1/2 normal clock freq in low power mode -2'b11: wdt will work with normal clock freq in low power mode - 0 - 2 - read-write - - - - - CTRL1 - wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x4 - 32 - 0x00000000 - 0x00F300FC - - - REF_FAIL_RST_EN - Refresh violation will trigger an reset. -These event will be taken as a refresh violation: -1) Not refresh in the window once window mode is enabled -2) Not unlock refresh firstly if unlock is required -3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. -4) Not write the required word to refresh wdt. - 23 - 1 - read-write - - - REF_FAIL_INT_EN - Refresh violation will trigger an interrupt - 22 - 1 - read-write - - - UNL_REF_FAIL_RST_EN - Refresh unlock fail will trigger a reset - 21 - 1 - read-write - - - UNL_REF_FAIL_INT_EN - Refresh unlock fail will trigger a interrupt - 20 - 1 - read-write - - - OT_RST_EN - WDT overtime will generate a reset - 17 - 1 - read-write - - - OT_INT_EN - WDT can generate an interrupt warning before timeout - 16 - 1 - read-write - - - CTL_VIO_RST_EN - Ctrl update violation will trigger a reset -The violation event is to try updating the locked register before unlock them - 7 - 1 - read-write - - - CTL_VIO_INT_EN - Ctrl update violation will trigger a interrupt - 6 - 1 - read-write - - - UNL_CTL_FAIL_RST_EN - Unlock register update failure will trigger a reset - 5 - 1 - read-write - - - UNL_CTL_FAIL_INT_EN - Unlock register update failure will trigger a interrupt - 4 - 1 - read-write - - - PARITY_FAIL_RST_EN - Parity error will trigger a reset -A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - 3 - 1 - read-write - - - PARITY_FAIL_INT_EN - Parity error will trigger a interrupt - 2 - 1 - read-write - - - - - OT_INT_VAL - wdog timeout interrupt counter value - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - OT_INT_VAL - WDT timeout interrupt value - 0 - 16 - read-write - - - - - OT_RST_VAL - wdog timeout reset counter value - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - OT_RST_VAL - WDT timeout reset value - 0 - 16 - read-write - - - - - WDT_REFRESH_REG - wdog refresh register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDT_REFRESH_REG - Write this register by 32'h5A45_524F to refresh wdog -Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - 0 - 32 - write-only - - - - - WDT_STATUS - wdog status register - 0x14 - 32 - 0x00000000 - 0x0000007F - - - PARITY_ERROR - parity error -Write one to clear the bit - 6 - 1 - write-only - - - OT_RST - Timeout happens, a reset will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 5 - 1 - write-only - - - OT_INT - Timeout happens, a interrupt will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 4 - 1 - write-only - - - CTL_UNL_FAIL - Unlock ctrl reg update protection fail -Write one to clear the bit - 3 - 1 - write-only - - - CTL_VIO - Violate register update protection mechanism -Write one to clear the bit - 2 - 1 - write-only - - - REF_UNL_FAIL - Refresh unlock fail -Write one to clear the bit - 1 - 1 - write-only - - - REF_VIO - Refresh fail -Write one to clear the bit - 0 - 1 - write-only - - - - - CFG_PROT - ctrl register protection register - 0x18 - 32 - 0x00000000 - 0x000FFFFF - - - UPD_OT_TIME - The period in which register update has to be in after unlock -The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - 16 - 4 - read-write - - - UPD_PSD - The password of unlocking register update - 0 - 16 - read-write - - - - - REF_PROT - refresh protection register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - REF_UNL_PSD - The password to unlock refreshing - 0 - 16 - read-write - - - - - WDT_EN - Wdog enable - 0x20 - 32 - 0x00000000 - 0x00000001 - - - WDOG_EN - Wdog is enabled, the re-written of this register is impacted by enable lock function - 0 - 1 - read-write - - - - - REF_TIME - Refresh period value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - REFRESH_PERIOD - The refresh period after refresh unlocked -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 0 - 16 - read-write - - - - - - - EWDG1 - EWDG1 - EWDG - 0xf00b4000 - - - PEWDG - PEWDG - EWDG - 0xf4128000 - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c4000 - - 0x0 - 0x80 - registers - - - - 32 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - write-only - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - write-only - - - - - - - HDMA - HDMA - DMAV2 - 0xf00c8000 - - 0x4 - 0x43c - registers - - - - IDMisc - ID Misc - 0x4 - 32 - 0x00000000 - 0x0000FF00 - - - DMASTATE - DMA state machine -localparam ST_IDLE = 3'b000; -localparam ST_READ = 3'b001; -localparam ST_READ_ACK = 3'b010; -localparam ST_WRITE = 3'b011; -localparam ST_WRITE_ACK = 3'b100; -localparam ST_LL = 3'b101; -localparam ST_END = 3'b110; -localparam ST_END_WAIT = 3'b111; - 13 - 3 - read-only - - - CURCHAN - current channel in used - 8 - 5 - read-only - - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. -The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, -which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x14 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. -Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - INTHALFSTS - Harlf Complete Interrupt Status - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - half transfer done irq status - 0 - 32 - read-write - - - - - INTTCSTS - Trans Complete Interrupt Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 0 - 32 - write-only - - - - - INTABORTSTS - Abort Interrupt Status Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 0 - 32 - write-only - - - - - INTERRSTS - Error Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 32 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 32 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel &index0 Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFF01F - - - INFINITELOOP - set to loop current config infinitely - 31 - 1 - read-write - - - HANDSHAKEOPT - 0: one request to transfer one burst -1: one request to transfer all the data defined in ch_tts - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - BURSTOPT - set to change burst_size definition - 28 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; -otherwise the error event will be triggered. -For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -Normal mode is enabled and started by software set Enable bit; -Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -the difference bewteen Source/Destination handshake mode is: -the dma block will response hardware request after read in Source handshake mode; -the dma block will response hardware request after write in Destination handshake mode; -NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - INTHALFCNTMASK - Channel half interrupt mask -0x0: Allow the half interrupt to be triggered -0x1: Disable the half interrupt - 4 - 1 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel &index0Transfer Size Register - 0x4 - 32 - 0x00000000 - 0x0FFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 28 - read-write - - - - - SrcAddr - Channel &index0 Source Address Low Part Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - ChanReqCtrl - Channel &index0 DMA Request Control Register - 0xc - 32 - 0x00000000 - 0x1F1F0000 - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 24 - 5 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 16 - 5 - read-write - - - - - DstAddr - Channel &index0 Destination Address Low Part Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - LLPointer - Channel &index0 Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF8 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - - - - - - GPIOM - GPIOM - GPIOM - 0xf00d8000 - - 0x0 - 0x780 - registers - - - - 15 - 0x80 - gpioa,gpiob,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -2: cpu0 fastgpio - 0 - 2 - read-write - - - - - - - - MCAN0 - MCAN0 - MCAN - 0xf0280000 - - 0x4 - 0x408 - registers - - - - ENDN - endian register - 0x4 - 32 - 0x87654321 - 0xFFFFFFFF - - - EVT - Endianness Test Value -The endianness test value is 0x87654321. - 0 - 32 - read-only - - - - - DBTP - data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set - 0xc - 32 - 0x00000A33 - 0x009F1FFF - - - TDC - transmitter delay compensation enable -0= Transmitter Delay Compensation disabled -1= Transmitter Delay Compensation enabled - 23 - 1 - read-write - - - DBRP - Data Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. -When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 5 - read-write - - - DTSEG1 - Data time segment before sample point -Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 5 - read-write - - - DTSEG2 - Data time segment after sample point -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 4 - 4 - read-write - - - DSJW - Data (Re)Synchronization Jump Width -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 0 - 4 - read-write - - - - - TEST - test register - 0x10 - 32 - 0x00000000 - 0x003F3FF0 - - - SVAL - Started Valid -0= Value of TXBNS not valid -1= Value of TXBNS valid - 21 - 1 - read-only - - - TXBNS - Tx Buffer Number Started -Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - 16 - 5 - read-only - - - PVAL - Prepared Valid -0= Value of TXBNP not valid -1= Value of TXBNP valid - 13 - 1 - read-only - - - TXBNP - Tx Buffer Number Prepared -Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - 8 - 5 - read-only - - - RX - Receive Pin -Monitors the actual value of pin m_can_rx -0= The CAN bus is dominant (m_can_rx = ‘0’) -1= The CAN bus is recessive (m_can_rx = ‘1’) - 7 - 1 - read-only - - - TX - Control of Transmit Pin -00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time -01 Sample Point can be monitored at pin m_can_tx -10 Dominant (‘0’) level at pin m_can_tx -11 Recessive (‘1’) at pin m_can_tx - 5 - 2 - read-write - - - LBCK - Loop Back Mode -0= Reset value, Loop Back Mode is disabled -1= Loop Back Mode is enabled - 4 - 1 - read-write - - - - - RWD - ram watchdog - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - WDV - Watchdog Value -Actual Message RAM Watchdog Counter Value. - 8 - 8 - read-only - - - WDC - Watchdog Configuration -Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - 0 - 8 - read-write - - - - - CCCR - CC control register - 0x18 - 32 - 0x00000001 - 0x0000FFFF - - - NISO - Non ISO Operation -If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD -Specification V1.0. -0= CAN FD frame format according to ISO 11898-1:2015 -1= CAN FD frame format according to Bosch CAN FD Specification V1.0 -Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - 15 - 1 - read-write - - - TXP - Transmit Pause -If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after -itself has successfully transmitted a frame (see Section 3.5). -0= Transmit pause disabled -1= Transmit pause enabled - 14 - 1 - read-write - - - EFBI - Edge Filtering during Bus Integration -0= Edge filtering disabled -1= Two consecutive dominant tq required to detect an edge for hard synchronization - 13 - 1 - read-write - - - PXHD - Protocol Exception Handling Disable -0= Protocol exception handling enabled -1= Protocol exception handling disabled -Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - 12 - 1 - read-write - - - WMM - Wide Message Marker -Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. -0= 8-bit Message Marker used -1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - 11 - 1 - read-write - - - UTSU - Use Timestamping Unit -When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. -0= Internal time stamping -1= External time stamping by TSU -Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. -In this case bit UTSU is fixed to zero by synthesis. - 10 - 1 - read-write - - - BRSE - Bit Rate Switch Enable -0= Bit rate switching for transmissions disabled -1= Bit rate switching for transmissions enabled -Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - 9 - 1 - read-write - - - FDOE - FD Operation Enable -0= FD operation disabled -1= FD operation enabled - 8 - 1 - read-write - - - TEST - Test Mode Enable -0= Normal operation, register TEST holds reset values -1= Test Mode, write access to register TEST enabled - 7 - 1 - read-write - - - DAR - Disable Automatic Retransmission -0= Automatic retransmission of messages not transmitted successfully enabled -1= Automatic retransmission disabled - 6 - 1 - read-write - - - MON - Bus Monitoring Mode -Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. -0= Bus Monitoring Mode is disabled -1= Bus Monitoring Mode is enabled - 5 - 1 - read-write - - - CSR - Clock Stop Request -0= No clock stop is requested -1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - 4 - 1 - read-write - - - CSA - Clock Stop Acknowledge -0= No clock stop acknowledged -1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - 3 - 1 - read-only - - - ASM - Restricted Operation Mode -Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. -0= Normal CAN operation -1= Restricted Operation Mode active - 2 - 1 - read-write - - - CCE - Configuration Change Enable -0= The CPU has no write access to the protected configuration registers -1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - 1 - 1 - read-write - - - INIT - Initialization -0= Normal Operation -1= Initialization is started - 0 - 1 - read-write - - - - - NBTP - nominal bit timing and prescaler register - 0x1c - 32 - 0x06000A03 - 0xFFFFFF7F - - - NSJW - Nominal (Re)Synchronization Jump Width -Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 25 - 7 - read-write - - - NBRP - Nominal Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is -such that one more than the value programmed here is used. - 16 - 9 - read-write - - - NTSEG1 - Nominal Time segment before sample point -Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 8 - read-write - - - NTSEG2 - Nominal Time segment after sample point -Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 0 - 7 - read-write - - - - - TSCC - timestamp counter configuration - 0x20 - 32 - 0x00000000 - 0x000F0003 - - - TCP - Timestamp Counter Prescaler -Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 4 - read-write - - - TSS - timestamp Select -00= Timestamp counter value always 0x0000 -01= Timestamp counter value incremented according to TCP -10= External timestamp counter value used -11= Same as “00” - 0 - 2 - read-write - - - - - TSCV - timestamp counter value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - TSC - Timestamp Counter -The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - 0 - 16 - read-only - - - - - TOCC - timeout counter configuration - 0x28 - 32 - 0xFFFF0000 - 0xFFFF0007 - - - TOP - Timeout Period -Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - 16 - 16 - read-write - - - TOS - Timeout Select -When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. -When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. -00= Continuous operation -01= Timeout controlled by Tx Event FIFO -10= Timeout controlled by Rx FIFO 0 -11= Timeout controlled by Rx FIFO 1 - 1 - 2 - read-write - - - RP - Enable Timeout Counter -0= Timeout Counter disabled -1= Timeout Counter enabled - 0 - 1 - read-write - - - - - TOCV - timeout counter value - 0x2c - 32 - 0x0000FFFF - 0x0000FFFF - - - TOC - Timeout Counter -The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. -Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - 0 - 16 - read-only - - - - - ECR - error counter register - 0x40 - 32 - 0x00000000 - 0x00FFFFFF - - - CEL - CAN Error Logging -The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. -The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. -The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. -Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - 16 - 8 - read-only - - - RP - Receive Error Passive -0= The Receive Error Counter is below the error passive level of 128 -1= The Receive Error Counter has reached the error passive level of 128 - 15 - 1 - read-only - - - REC - Receive Error Counter -Actual state of the Receive Error Counter, values between 0 and 127 - 8 - 7 - read-only - - - TEC - Transmit Error Counter -Actual state of the Transmit Error Counter, values between 0 and 255 -Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - 0 - 8 - read-only - - - - - PSR - protocol status register - 0x44 - 32 - 0x00000707 - 0x007F7FFF - - - TDCV - Transmitter Delay Compensation Value -Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. -The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - 16 - 7 - read-only - - - PXE - Protocol Exception Event -0= No protocol exception event occurred since last read access -1= Protocol exception event occurred -Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - 14 - 1 - read-only - - - RFDF - Received a CAN FD Message -This bit is set independent of acceptance filtering. -0= Since this bit was reset by the CPU, no CAN FD message has been received -1= Message in CAN FD format with FDF flag set has been received -Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - 13 - 1 - read-only - - - RBRS - BRS flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its BRS flag set -1= Last received CAN FD message had its BRS flag set -Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - 12 - 1 - read-only - - - RESI - ESI flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its ESI flag set -1= Last received CAN FD message had its ESI flag set -Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - 11 - 1 - read-only - - - DLEC - Data Phase Last Error Code -Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with -its BRS flag set has been transferred (reception or transmission) without error. -Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - 8 - 3 - read-only - - - BO - Bus_Off Status -0= The M_CAN is not Bus_Off -1= The M_CAN is in Bus_Off state - 7 - 1 - read-only - - - EW - Warning Status -0= Both error counters are below the Error_Warning limit of 96 -1= At least one of error counter has reached the Error_Warning limit of 96 - 6 - 1 - read-only - - - EP - Error Passive -0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected -1= The M_CAN is in the Error_Passive state - 5 - 1 - read-only - - - ACT - Activity -Monitors the module’s CAN communication state. -00= Synchronizing - node is synchronizing on CAN communication -01= Idle - node is neither receiver nor transmitter -10= Receiver - node is operating as receiver -11= Transmitter - node is operating as transmitter -Note: ACT is set to “00” by a Protocol Exception Event. - 3 - 2 - read-only - - - LEC - Last Error Code -The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. -0= No Error: No error occurred since LEC has been reset by successful reception or transmission. -1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. -2= Form Error: A fixed format part of a received frame has the wrong format. -3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. -4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), -the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus -value was dominant. -5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at -dominant or continuously disturbed). -6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. -7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. -Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. -Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. -At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, -enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. -Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - 0 - 3 - read-only - - - - - TDCR - transmitter delay compensation - 0x48 - 32 - 0x00000000 - 0x00007F7F - - - TDCO - Transmitter Delay Compensation SSP Offset -Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - 8 - 7 - read-write - - - TDCF - Transmitter Delay Compensation Filter Window Length -Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. -The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - 0 - 7 - read-write - - - - - IR - interrupt register - 0x50 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARA - Access to Reserved Address -0= No access to reserved address occurred -1= Access to reserved address occurred - 29 - 1 - read-write - - - PED - Protocol Error in Data Phase (Data Bit Time is used) -0= No protocol error in data phase -1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - 28 - 1 - read-write - - - PEA - Protocol Error in Arbitration Phase (Nominal Bit Time is used) -0= No protocol error in arbitration phase -1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - 27 - 1 - read-write - - - WDI - Watchdog Interrupt -0= No Message RAM Watchdog event occurred -1= Message RAM Watchdog event due to missing READY - 26 - 1 - read-write - - - BO - Bus_Off Status -0= Bus_Off status unchanged -1= Bus_Off status changed - 25 - 1 - read-write - - - EW - Warning Status -0= Error_Warning status unchanged -1= Error_Warning status changed - 24 - 1 - read-write - - - EP - Error Passive -0= Error_Passive status unchanged -1= Error_Passive status changed - 23 - 1 - read-write - - - ELO - Error Logging Overflow -0= CAN Error Logging Counter did not overflow -1= Overflow of CAN Error Logging Counter occurred - 22 - 1 - read-write - - - BEU - Bit Error Uncorrected -Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. -An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. -0= No bit error detected when reading from Message RAM -1= Bit error detected, uncorrected (e.g. parity logic) - 21 - 1 - read-write - - - BEC - Bit Error Corrected -Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. -0= No bit error detected when reading from Message RAM -1= Bit error detected and corrected (e.g. ECC) - 20 - 1 - read-write - - - DRX - Message stored to Dedicated Rx Buffer -The flag is set whenever a received message has been stored into a dedicated Rx Buffer. -0= No Rx Buffer updated -1= At least one received message stored into an Rx Buffer - 19 - 1 - read-write - - - TOO - Timeout Occurred -0= No timeout -1= Timeout reached - 18 - 1 - read-write - - - MRAF - Message RAM Access Failure -The flag is set, when the Rx Handler -.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message -storage is aborted and the Rx Handler starts processing of the following message. -.was not able to write a message to the Message RAM. In this case message storage is aborted. -In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. -The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the -M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. -0= No Message RAM access failure occurred -1= Message RAM access failure occurred - 17 - 1 - read-write - - - TSW - Timestamp Wraparound -0= No timestamp counter wrap-around -1= Timestamp counter wrapped around - 16 - 1 - read-write - - - TEFL - Tx Event FIFO Element Lost -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - 15 - 1 - read-write - - - TEFF - Tx Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 14 - 1 - read-write - - - TEFW - Tx Event FIFO Watermark Reached -0= Tx Event FIFO fill level below watermark -1= Tx Event FIFO fill level reached watermark - 13 - 1 - read-write - - - TEFN - Tx Event FIFO New Entry -0= Tx Event FIFO unchanged -1= Tx Handler wrote Tx Event FIFO element - 12 - 1 - read-write - - - TFE - Tx FIFO Empty -0= Tx FIFO non-empty -1= Tx FIFO empty - 11 - 1 - read-write - - - TCF - Transmission Cancellation Finished -0= No transmission cancellation finished -1= Transmission cancellation finished - 10 - 1 - read-write - - - TC - Transmission Completed -0= No transmission completed -1= Transmission completed - 9 - 1 - read-write - - - HPM - High Priority Message -0= No high priority message received -1= High priority message received - 8 - 1 - read-write - - - RF1L - Rx FIFO 1 Message Lost -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - 7 - 1 - read-write - - - RF1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 6 - 1 - read-write - - - RF1W - Rx FIFO 1 Watermark Reached -0= Rx FIFO 1 fill level below watermark -1= Rx FIFO 1 fill level reached watermark - 5 - 1 - read-write - - - RF1N - Rx FIFO 1 New Message -0= No new message written to Rx FIFO 1 -1= New message written to Rx FIFO 1 - 4 - 1 - read-write - - - RF0L - Rx FIFO 0 Message Lost -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - 3 - 1 - read-write - - - RF0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 2 - 1 - read-write - - - RF0W - Rx FIFO 0 Watermark Reached -0= Rx FIFO 0 fill level below watermark -1= Rx FIFO 0 fill level reached watermark - 1 - 1 - read-write - - - RF0N - Rx FIFO 0 New Message -0= No new message written to Rx FIFO 0 -1= New message written to Rx FIFO 0 - 0 - 1 - read-write - - - - - IE - interrupt enable - 0x54 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAE - Access to Reserved Address Enable - 29 - 1 - read-write - - - PEDE - Protocol Error in Data Phase Enable - 28 - 1 - read-write - - - PEAE - Protocol Error in Arbitration Phase Enable - 27 - 1 - read-write - - - WDIE - Watchdog Interrupt Enable - 26 - 1 - read-write - - - BOE - Bus_Off Status Interrupt Enable - 25 - 1 - read-write - - - EWE - Warning Status Interrupt Enable - 24 - 1 - read-write - - - EPE - Error Passive Interrupt Enable - 23 - 1 - read-write - - - ELOE - Error Logging Overflow Interrupt Enable - 22 - 1 - read-write - - - BEUE - Bit Error Uncorrected Interrupt Enable - 21 - 1 - read-write - - - BECE - Bit Error Corrected Interrupt Enable - 20 - 1 - read-write - - - DRXE - Message stored to Dedicated Rx Buffer Interrupt Enable - 19 - 1 - read-write - - - TOOE - Timeout Occurred Interrupt Enable - 18 - 1 - read-write - - - MRAFE - Message RAM Access Failure Interrupt Enable - 17 - 1 - read-write - - - TSWE - Timestamp Wraparound Interrupt Enable - 16 - 1 - read-write - - - TEFLE - Tx Event FIFO Event Lost Interrupt Enable - 15 - 1 - read-write - - - TEFFE - Tx Event FIFO Full Interrupt Enable - 14 - 1 - read-write - - - TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - 13 - 1 - read-write - - - TEFNE - Tx Event FIFO New Entry Interrupt Enable - 12 - 1 - read-write - - - TFEE - Tx FIFO Empty Interrupt Enable - 11 - 1 - read-write - - - TCFE - Transmission Cancellation Finished Interrupt Enable - 10 - 1 - read-write - - - TCE - Transmission Completed Interrupt Enable - 9 - 1 - read-write - - - HPME - High Priority Message Interrupt Enable - 8 - 1 - read-write - - - RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - 7 - 1 - read-write - - - RF1FE - Rx FIFO 1 Full Interrupt Enable - 6 - 1 - read-write - - - RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - 5 - 1 - read-write - - - RF1NE - Rx FIFO 1 New Message Interrupt Enable - 4 - 1 - read-write - - - RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - 3 - 1 - read-write - - - RF0FE - Rx FIFO 0 Full Interrupt Enable - 2 - 1 - read-write - - - RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - 1 - 1 - read-write - - - RF0NE - Rx FIFO 0 New Message Interrupt Enable - 0 - 1 - read-write - - - - - ILS - interrupt line select - 0x58 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAL - Access to Reserved Address Line - 29 - 1 - read-write - - - PEDL - Protocol Error in Data Phase Line - 28 - 1 - read-write - - - PEAL - Protocol Error in Arbitration Phase Line - 27 - 1 - read-write - - - WDIL - Watchdog Interrupt Line - 26 - 1 - read-write - - - BOL - Bus_Off Status Interrupt Line - 25 - 1 - read-write - - - EWL - Warning Status Interrupt Line - 24 - 1 - read-write - - - EPL - Error Passive Interrupt Line - 23 - 1 - read-write - - - ELOL - Error Logging Overflow Interrupt Line - 22 - 1 - read-write - - - BEUL - Bit Error Uncorrected Interrupt Line - 21 - 1 - read-write - - - BECL - Bit Error Corrected Interrupt Line - 20 - 1 - read-write - - - DRXL - Message stored to Dedicated Rx Buffer Interrupt Line - 19 - 1 - read-write - - - TOOL - Timeout Occurred Interrupt Line - 18 - 1 - read-write - - - MRAFL - Message RAM Access Failure Interrupt Line - 17 - 1 - read-write - - - TSWL - Timestamp Wraparound Interrupt Line - 16 - 1 - read-write - - - TEFLL - Tx Event FIFO Event Lost Interrupt Line - 15 - 1 - read-write - - - TEFFL - Tx Event FIFO Full Interrupt Line - 14 - 1 - read-write - - - TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - 13 - 1 - read-write - - - TEFNL - Tx Event FIFO New Entry Interrupt Line - 12 - 1 - read-write - - - TFEL - Tx FIFO Empty Interrupt Line - 11 - 1 - read-write - - - TCFL - Transmission Cancellation Finished Interrupt Line - 10 - 1 - read-write - - - TCL - Transmission Completed Interrupt Line - 9 - 1 - read-write - - - HPML - High Priority Message Interrupt Line - 8 - 1 - read-write - - - RF1LL - Rx FIFO 1 Message Lost Interrupt Line - 7 - 1 - read-write - - - RF1FL - Rx FIFO 1 Full Interrupt Line - 6 - 1 - read-write - - - RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - 5 - 1 - read-write - - - RF1NL - Rx FIFO 1 New Message Interrupt Line - 4 - 1 - read-write - - - RF0LL - Rx FIFO 0 Message Lost Interrupt Line - 3 - 1 - read-write - - - RF0FL - Rx FIFO 0 Full Interrupt Line - 2 - 1 - read-write - - - RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - 1 - 1 - read-write - - - RF0NL - Rx FIFO 0 New Message Interrupt Line - 0 - 1 - read-write - - - - - ILE - interrupt line enable - 0x5c - 32 - 0x00000000 - 0x00000003 - - - EINT1 - Enable Interrupt Line 1 -0= Interrupt line m_can_int1 disabled -1= Interrupt line m_can_int1 enabled - 1 - 1 - read-write - - - EINT0 - Enable Interrupt Line 0 -0= Interrupt line m_can_int0 disabled -1= Interrupt line m_can_int0 enabled - 0 - 1 - read-write - - - - - GFC - global filter configuration - 0x80 - 32 - 0x00000000 - 0x0000003F - - - ANFS - Accept Non-matching Frames Standard -Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 4 - 2 - read-write - - - ANFE - Accept Non-matching Frames Extended -Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 2 - 2 - read-write - - - RRFS - Reject Remote Frames Standard -0= Filter remote frames with 11-bit standard IDs -1= Reject all remote frames with 11-bit standard IDs - 1 - 1 - read-write - - - RRFE - Reject Remote Frames Extended -0= Filter remote frames with 29-bit extended IDs -1= Reject all remote frames with 29-bit extended IDs - 0 - 1 - read-write - - - - - SIDFC - standard ID filter configuration - 0x84 - 32 - 0x00000000 - 0x00FFFFFC - - - LSS - List Size Standard -0= No standard Message ID filter -1-128= Number of standard Message ID filter elements ->128= Values greater than 128 are interpreted as 128 - 16 - 8 - read-write - - - FLSSA - Filter List Standard Start Address -Start address of standard Message ID filter list (32-bit word address) - 2 - 14 - read-write - - - - - XIDFC - extended ID filter configuration - 0x88 - 32 - 0x00000000 - 0x007FFFFC - - - LSE - List Size Extended -0= No extended Message ID filter -1-64= Number of extended Message ID filter elements ->64= Values greater than 64 are interpreted as 64 - 16 - 7 - read-write - - - FLESA - Filter List Extended Start Address -Start address of extended Message ID filter list (32-bit word address). - 2 - 14 - read-write - - - - - XIDAM - extended id and mask - 0x90 - 32 - 0x1FFFFFFF - 0x1FFFFFFF - - - EIDM - Extended ID Mask -For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - 0 - 29 - read-write - - - - - HPMS - high priority message status - 0x94 - 32 - 0x00000000 - 0x0000FFFF - - - FLST - Filter List -Indicates the filter list of the matching filter element. -0= Standard Filter List -1= Extended Filter List - 15 - 1 - read-only - - - FIDX - Filter Index -Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - 8 - 7 - read-only - - - MSI - Message Storage Indicator -00= No FIFO selected -01= FIFO message lost -10= Message stored in FIFO 0 -11= Message stored in FIFO 1 - 6 - 2 - read-only - - - BIDX - Buffer Index -Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - 0 - 6 - read-only - - - - - NDAT1 - new data1 - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - ND1 - New Data[31:0] -The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - NDAT2 - new data2 - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - ND2 - New Data[63:32] -The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - RXF0C - rx fifo 0 configuration - 0xa0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F0OM - FIFO 0 Operation Mode -FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 0 blocking mode -1= FIFO 0 overwrite mode - 31 - 1 - read-write - - - F0WM - Rx FIFO 0 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F0S - Rx FIFO 0 Size -0= No Rx FIFO 0 -1-64= Number of Rx FIFO 0 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 0 elements are indexed from 0 to F0S-1 - 16 - 7 - read-write - - - F0SA - Rx FIFO 0 Start Address -Start address of Rx FIFO 0 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF0S - rx fifo 0 status - 0xa4 - 32 - 0x00000000 - 0x033F3F7F - - - RF0L - Rx FIFO 0 Message Lost -This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero -Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 24 - 1 - read-only - - - F0PI - Rx FIFO 0 Put Index -Rx FIFO 0 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F0GI - Rx FIFO 0 Get Index -Rx FIFO 0 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F0FL - Rx FIFO 0 Fill Level -Number of elements stored in Rx FIFO 0, range 0 to 64. - 0 - 7 - read-only - - - - - RXF0A - rx fifo0 acknowledge - 0xa8 - 32 - 0x00000000 - 0x0000003F - - - F0AI - Rx FIFO 0 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. -This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - 0 - 6 - read-write - - - - - RXBC - rx buffer configuration - 0xac - 32 - 0x00000000 - 0x0000FFFC - - - RBSA - Rx Buffer Start Address -Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - 2 - 14 - read-write - - - - - RXF1C - rx fifo1 configuration - 0xb0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F1OM - FIFO 1 Operation Mode -FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 1 blocking mode -1= FIFO 1 overwrite mode - 31 - 1 - read-write - - - F1WM - Rx FIFO 1 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F1S - Rx FIFO 1 Size -0= No Rx FIFO 1 -1-64= Number of Rx FIFO 1 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - 16 - 7 - read-write - - - F1SA - Rx FIFO 1 Start Address -Start address of Rx FIFO 1 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF1S - rx fifo1 status - 0xb4 - 32 - 0x00000000 - 0xC33F3F7F - - - DMS - Debug Message Status -00= Idle state, wait for reception of debug messages, DMA request is cleared -01= Debug message A received -10= Debug messages A, B received -11= Debug messages A, B, C received, DMA request is set - 30 - 2 - read-only - - - RF1L - Rx FIFO 1 Message Lost -This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero -Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 24 - 1 - read-only - - - F1PI - Rx FIFO 1 Put Index -Rx FIFO 1 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F1GI - Rx FIFO 1 Get Index -Rx FIFO 1 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F1FL - Rx FIFO 1 Fill Level -Number of elements stored in Rx FIFO 1, range 0 to 64. - 0 - 7 - read-only - - - - - RXF1A - rx fifo 1 acknowledge - 0xb8 - 32 - 0x00000000 - 0x0000003F - - - F1AI - Rx FIFO 1 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. -This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - 0 - 6 - read-write - - - - - RXESC - rx buffer/fifo element size configuration - 0xbc - 32 - 0x00000000 - 0x00000777 - - - RBDS - Rx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 8 - 3 - read-write - - - F1DS - Rx FIFO 1 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 4 - 3 - read-write - - - F0DS - Rx FIFO 0 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, -only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - 0 - 3 - read-write - - - - - TXBC - tx buffer configuration - 0xc0 - 32 - 0x00000000 - 0x7F3FFFFC - - - TFQM - Tx FIFO/Queue Mode -0= Tx FIFO operation -1= Tx Queue operation - 30 - 1 - read-write - - - TFQS - Transmit FIFO/Queue Size -0= No Tx FIFO/Queue -1-32= Number of Tx Buffers used for Tx FIFO/Queue ->32= Values greater than 32 are interpreted as 32 - 24 - 6 - read-write - - - NDTB - Number of Dedicated Transmit Buffers -0= No Dedicated Tx Buffers -1-32= Number of Dedicated Tx Buffers ->32= Values greater than 32 are interpreted as 32 - 16 - 6 - read-write - - - TBSA - Tx Buffers Start Address -Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). -Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - 2 - 14 - read-write - - - - - TXFQS - tx fifo/queue status - 0xc4 - 32 - 0x00000000 - 0x003F1F3F - - - TFQF - Tx FIFO/Queue Full -0= Tx FIFO/Queue not full -1= Tx FIFO/Queue full - 21 - 1 - read-only - - - TFQPI - Tx FIFO/Queue Put Index -Tx FIFO/Queue write index pointer, range 0 to 31. - 16 - 5 - read-only - - - TFGI - Tx FIFO Get Index -Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured -(TXBC.TFQM = ‘1’). - 8 - 5 - read-only - - - TFFL - Tx FIFO Free Level -Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) -Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with -the first dedicated Tx Buffers. -Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - 0 - 6 - read-only - - - - - TXESC - tx buffer element size configuration - 0xc8 - 32 - 0x00000000 - 0x00000007 - - - TBDS - Tx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - 0 - 3 - read-write - - - - - TXBRP - tx buffer request pending - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - TRP - Transmission Request Pending -Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register -TXBCR. -TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the -highest priority (Tx Buffer with lowest Message ID). -A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, -this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. -After a cancellation has been requested, a finished cancellation is signalled via TXBCF -? after successful transmission together with the corresponding TXBTO bit -? when the transmission has not yet been started at the point of cancellation -? when the transmission has been aborted due to lost arbitration -? when an error occurred during frame transmission -In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. -0= No transmission request pending -1= Transmission request pending -Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - 0 - 32 - read-only - - - - - TXBAR - tx buffer add request - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - AR - Add Request -Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx -Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. -When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. -0= No transmission request added -1= Transmission requested added -Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - 0 - 32 - read-write - - - - - TXBCR - tx buffer cancellation request - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR - Cancellation Request -Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. -This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. -0= No cancellation pending -1= Cancellation pending - 0 - 32 - read-write - - - - - TXBTO - tx buffer transmission occurred - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TO - Transmission Occurred -Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmission occurred -1= Transmission occurred - 0 - 32 - read-only - - - - - TXBCF - tx buffer cancellation finished - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - CF - Cancellation Finished -Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. -In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmit buffer cancellation -1= Transmit buffer cancellation finished - 0 - 32 - read-only - - - - - TXBTIE - tx buffer transmission interrupt enable - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIE - Transmission Interrupt Enable -Each Tx Buffer has its own Transmission Interrupt Enable bit. -0= Transmission interrupt disabled -1= Transmission interrupt enable - 0 - 32 - read-write - - - - - TXBCIE - tx buffer cancellation finished interrupt enable - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFIE - Cancellation Finished Interrupt Enable -Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. -0= Cancellation finished interrupt disabled -1= Cancellation finished interrupt enabled - 0 - 32 - read-write - - - - - TXEFC - tx event fifo configuration - 0xf0 - 32 - 0x00000000 - 0x3F3FFFFC - - - EFWM - Event FIFO Watermark -0= Watermark interrupt disabled -1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) ->32= Watermark interrupt disabled - 24 - 6 - read-write - - - EFS - Event FIFO Size -0= Tx Event FIFO disabled -1-32= Number of Tx Event FIFO elements ->32= Values greater than 32 are interpreted as 32 -The Tx Event FIFO elements are indexed from 0 to EFS - 1 - 16 - 6 - read-write - - - EFSA - Event FIFO Start Address -Start address of Tx Event FIFO in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - TXEFS - tx event fifo status - 0xf4 - 32 - 0x00000000 - 0x031F1F3F - - - TEFL - Tx Event FIFO Element Lost -This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - 25 - 1 - read-only - - - EFF - Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 24 - 1 - read-only - - - EFPI - Event FIFO Put Index -Tx Event FIFO write index pointer, range 0 to 31. - 16 - 5 - read-only - - - EFGI - Event FIFO Get Index -Tx Event FIFO read index pointer, range 0 to 31. - 8 - 5 - read-only - - - EFFL - Event FIFO Fill Level -Number of elements stored in Tx Event FIFO, range 0 to 32. - 0 - 6 - read-only - - - - - TXEFA - tx event fifo acknowledge - 0xf8 - 32 - 0x00000000 - 0x0000001F - - - EFAI - Event FIFO Acknowledge Index -After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get -Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - 0 - 5 - read-write - - - - - 16 - 0x4 - TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 - TS_SEL[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - TS - Timestamp Word TS -default can save 16 timestamps with 32bit; -if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - 0 - 32 - read-only - - - - - CREL - core release register - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - REL - Core Release -One digit, BCD-coded - 28 - 4 - read-only - - - STEP - Step of Core Release -One digit, BCD-coded. - 24 - 4 - read-only - - - SUBSTEP - Sub-step of Core Release -One digit, BCD-coded - 20 - 4 - read-only - - - YEAR - Timestamp Year -One digit, BCD-coded. This field is set by generic parameter on -synthesis. - 16 - 4 - read-only - - - MON - Timestamp Month -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 8 - 8 - read-only - - - DAY - Timestamp Day -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 0 - 8 - read-only - - - - - TSCFG - timestamp configuration - 0x244 - 32 - 0x00000000 - 0x0000FF0F - - - TBPRE - Timebase Prescaler -0x00 to 0xFF -The value by which the oscillator frequency is divided for -generating the timebase counter clock. Valid values for the -Timebase Prescaler are 0 to 255. The actual interpretation by -the hardware of this value is such that one more than the value -programmed here is used. Affects only the TSU internal -timebase. When the internal timebase is excluded by synthesis, -TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not -used. - 8 - 8 - read-write - - - EN64 - set to use 64bit timestamp. -when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. -TSP can be used to select different one - 3 - 1 - read-write - - - SCP - Select Capturing Position -0: Capture Timestamp at EOF -1: Capture Timestamp at SOF - 2 - 1 - read-write - - - TBCS - Timebase Counter Select -When the internal timebase is excluded by synthesis, TBCS is -fixed to ‘1’. -0: Timestamp value captured from internal timebase counter, - ATB.TB[31:0] is the internal timbase counter -1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - 1 - 1 - read-write - - - TSUE - Timestamp Unit Enable -0: TSU disabled -1: TSU enabled - 0 - 1 - read-write - - - - - TSS1 - timestamp status1 - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSL - Timestamp Lost -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. -Reading a Timestamp register resets the related bit. - 16 - 16 - read-only - - - TSN - Timestamp New -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related -Timestamp register. Reading a Timestamp register resets the related bit. - 0 - 16 - read-only - - - - - TSS2 - timestamp status2 - 0x24c - 32 - 0x00000000 - 0x0000000F - - - TSP - Timestamp Pointer -The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 -depending on number_ts_g), it is incremented to 0. -Value also signalled on output m_can_tsp[3:0]. - 0 - 4 - read-only - - - - - ATB - actual timebase - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - TB - timebase for timestamp generation 31-0 - 0 - 32 - read-only - - - - - ATBH - actual timebase high - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBH - timebase for timestamp generation 63-32 - 0 - 32 - read-only - - - - - GLB_CTL - global control - 0x400 - 32 - 0x00000000 - 0xE0000003 - - - M_CAN_STBY - m_can standby control - 31 - 1 - read-write - - - STBY_CLR_EN - m_can standby clear control -0:controlled by software by standby bit[bit31] -1:auto clear standby by hardware when rx data is 0 - 30 - 1 - read-write - - - STBY_POL - standby polarity selection - 29 - 1 - read-write - - - TSU_TBIN_SEL - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - 0 - 2 - read-write - - - - - GLB_STATUS - global status - 0x404 - 32 - 0x00000000 - 0x0000000C - - - M_CAN_INT1 - m_can interrupt status1 - 3 - 1 - read-only - - - M_CAN_INT0 - m_can interrupt status0 - 2 - 1 - read-only - - - - - - - MCAN1 - MCAN1 - MCAN - 0xf0284000 - - - MCAN2 - MCAN2 - MCAN - 0xf0288000 - - - MCAN3 - MCAN3 - MCAN - 0xf028c000 - - - PTPC - PTPC - PTPC - 0xf02fc000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - QEI0 - QEI0 - QEIV2 - 0xf0300000 - - 0x0 - 0x298 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x807FFF7F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert(for abz digital signsl) - 21 - 1 - read-write - - - Z_ONLY_EN - 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) - 20 - 1 - read-write - - - H2FDIR0 - No description available - 19 - 1 - read-write - - - H2FDIR1 - No description available - 18 - 1 - read-write - - - H2RDIR0 - No description available - 17 - 1 - read-write - - - H2RDIR1 - No description available - 16 - 1 - read-write - - - PAUSEPOS - 1- pause position output valid when PAUSE assert - 15 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - FAULTPOS - No description available - 6 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - RD_SEL - define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, -width_snap0,width_snap1, timer_snap0, timer_snap1) -0 : same as hpm1000/500/500s; -1: use width for position; use timer for angle - 3 - 1 - read-write - - - ENCTYP - 000-abz; 001-pd; 010-ud; 011-UVW(hal) -100-single A; 101-single sin; 110: sin&cos - 0 - 3 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 32 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDOG_CFG - define as stop if phase_cnt change is less than it -if 0, then each change of phase_cnt will clear wdog counter; -if 2, then phase_cnt change larger than 2 will clear wdog counter - 28 - 3 - read-write - - - WDGTO - watch dog timeout value - 0 - 28 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 32 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - ZMISSFEN - No description available - 27 - 1 - read-write - - - WIDTHTMFEN - No description available - 26 - 1 - read-write - - - POS2CMPFEN - No description available - 25 - 1 - read-write - - - DIRCHGFEN - No description available - 24 - 1 - read-write - - - CYCLE0FEN - No description available - 23 - 1 - read-write - - - CYCLE1FEN - No description available - 22 - 1 - read-write - - - PULSE0FEN - No description available - 21 - 1 - read-write - - - PULSE1FEN - No description available - 20 - 1 - read-write - - - HOME2FEN - No description available - 19 - 1 - read-write - - - FAULTFEN - No description available - 18 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - ZMISSFEN - No description available - 27 - 1 - read-write - - - WIDTHTMFEN - No description available - 26 - 1 - read-write - - - POS2CMPFEN - No description available - 25 - 1 - read-write - - - DIRCHGFEN - No description available - 24 - 1 - read-write - - - CYCLE0FEN - No description available - 23 - 1 - read-write - - - CYCLE1FEN - No description available - 22 - 1 - read-write - - - PULSE0FEN - No description available - 21 - 1 - read-write - - - PULSE1FEN - No description available - 20 - 1 - read-write - - - HOME2FEN - No description available - 19 - 1 - read-write - - - FAULTFEN - No description available - 18 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x80000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x80000000 - 0xFFFFFFFF - - - PHCMP - phcnt position compare value - 0 - 32 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x80000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - ZMISSFEN - No description available - 27 - 1 - read-write - - - WIDTHTMFEN - No description available - 26 - 1 - read-write - - - POS2CMPFEN - No description available - 25 - 1 - read-write - - - DIRCHGFEN - No description available - 24 - 1 - read-write - - - CYCLE0FEN - No description available - 23 - 1 - read-write - - - CYCLE1FEN - No description available - 22 - 1 - read-write - - - PULSE0FEN - No description available - 21 - 1 - read-write - - - PULSE1FEN - No description available - 20 - 1 - read-write - - - HOME2FEN - No description available - 19 - 1 - read-write - - - FAULTFEN - No description available - 18 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - ZMISSF - No description available - 27 - 1 - read-write - - - WIDTHTMF - No description available - 26 - 1 - read-write - - - POS2CMPF - No description available - 25 - 1 - read-write - - - DIRCHGF - No description available - 24 - 1 - read-write - - - CYCLE0F - No description available - 23 - 1 - read-write - - - CYCLE1F - No description available - 22 - 1 - read-write - - - PULSE0F - No description available - 21 - 1 - read-write - - - PULSE1F - No description available - 20 - 1 - read-write - - - HOME2F - No description available - 19 - 1 - read-write - - - FAULTF - No description available - 18 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xFFFC0000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - ZMISSE - No description available - 27 - 1 - read-write - - - WIDTHTME - No description available - 26 - 1 - read-write - - - POS2CMPE - No description available - 25 - 1 - read-write - - - DIRCHGE - No description available - 24 - 1 - read-write - - - CYCLE0E - No description available - 23 - 1 - read-write - - - CYCLE1E - No description available - 22 - 1 - read-write - - - PULSE0E - No description available - 21 - 1 - read-write - - - PULSE1E - No description available - 20 - 1 - read-write - - - HOME2E - No description available - 19 - 1 - read-write - - - FAULTE - No description available - 18 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - zcmp2 - Z comparator - 0x80 - 32 - 0x80000000 - 0xFFFFFFFF - - - ZCMP2 - No description available - 0 - 32 - read-write - - - - - phcmp2 - Phase comparator - 0x84 - 32 - 0x80000000 - 0xFFFFFFFF - - - PHCMP2 - No description available - 0 - 32 - read-write - - - - - spdcmp2 - Speed comparator - 0x88 - 32 - 0x80000000 - 0xFFFFFFFF - - - SPDCMP2 - No description available - 0 - 32 - read-write - - - - - match_cfg - No description available - 0x8c - 32 - 0x00000000 - 0xFE00FE00 - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - SPDCMPDIS - No description available - 28 - 1 - read-write - - - PHASE_MATCH_DIS - No description available - 27 - 1 - read-write - - - POS_MATCH_DIR - No description available - 26 - 1 - read-write - - - POS_MATCH_OPT - No description available - 25 - 1 - read-write - - - ZCMP2DIS - No description available - 15 - 1 - read-write - - - DIRCMP2DIS - No description available - 14 - 1 - read-write - - - DIRCMP2 - No description available - 13 - 1 - read-write - - - SPDCMP2DIS - No description available - 12 - 1 - read-write - - - PHASE_MATCH_DIS2 - No description available - 11 - 1 - read-write - - - POS_MATCH2_DIR - No description available - 10 - 1 - read-write - - - POS_MATCH2_OPT - No description available - 9 - 1 - read-write - - - - - 6 - 0x4 - filt_cfg_a,filt_cfg_b,filt_cfg_z,filt_cfg_h,filt_cfg_h2,filt_cfg_f - FILT_CFG[%s] - no description available - 0x90 - 32 - 0x00001000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stable low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - qei_cfg - qei config register - 0x100 - 32 - 0x00000000 - 0x0000103F - - - SPEED_DIR_CHG_EN - clear counter if detect direction change - 12 - 1 - read-write - - - UVW_POS_OPT0 - set to output next area position for QEO use; -clr to output exact point position for MMC use - 5 - 1 - read-write - - - NEGEDGE_EN - bit4: negedge enable -bit3: posedge enable -bit2: W in hal enable -bit1: signal b(or V in hal) enable -bit0: signal a(or U in hal) enable -such as: -01001: use posedge A -11010: use both edge of signal B -11111: use both edge of all HAL siganls - 4 - 1 - read-write - - - POSIDGE_EN - No description available - 3 - 1 - read-write - - - SIGZ_EN - No description available - 2 - 1 - read-write - - - SIGB_EN - No description available - 1 - 1 - read-write - - - SIGA_EN - No description available - 0 - 1 - read-write - - - - - pulse0_num - pulse0_num - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_NUM - for speed detection, will count the cycle number for configed pulse_num - 0 - 32 - read-write - - - - - pulse1_num - pulse1_num - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_NUM - No description available - 0 - 32 - read-write - - - - - cycle0_cnt - cycle0_cnt - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_CNT - No description available - 0 - 32 - read-only - - - - - cycle0pulse_cnt - cycle0pulse_cnt - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0PULSE_CNT - No description available - 0 - 32 - read-only - - - - - cycle1_cnt - cycle1_cnt - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_CNT - No description available - 0 - 32 - read-only - - - - - cycle1pulse_cnt - cycle1pulse_cnt - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1PULSE_CNT - No description available - 0 - 32 - read-only - - - - - cycle0_snap0 - cycle0_snap0 - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_SNAP0 - No description available - 0 - 32 - read-only - - - - - cycle0_snap1 - cycle0_snap1 - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_SNAP1 - No description available - 0 - 32 - read-only - - - - - cycle1_snap0 - cycle1_snap0 - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_SNAP0 - No description available - 0 - 32 - read-only - - - - - cycle1_snap1 - cycle1_snap1 - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_SNAP1 - No description available - 0 - 32 - read-only - - - - - cycle0_num - cycle0_num - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_NUM - No description available - 0 - 32 - read-write - - - - - cycle1_num - cycle1_num - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_NUM - No description available - 0 - 32 - read-write - - - - - pulse0_cnt - pulse0_cnt - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_CNT - No description available - 0 - 32 - read-only - - - - - pulse0cycle_cnt - pulse0cycle_cnt - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0CYCLE_CNT - No description available - 0 - 32 - read-only - - - - - pulse1_cnt - pulse1_cnt - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_CNT - No description available - 0 - 32 - read-only - - - - - pulse1cycle_cnt - pulse1cycle_cnt - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1CYCLE_CNT - No description available - 0 - 32 - read-only - - - - - pulse0_snap0 - pulse0_snap0 - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse0cycle_snap0 - pulse0cycle_snap0 - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0CYCLE_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse0_snap1 - pulse0_snap1 - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_SNAP1 - No description available - 0 - 32 - read-only - - - - - pulse0cycle_snap1 - pulse0cycle_snap1 - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0CYCLE_SNAP1 - No description available - 0 - 32 - read-only - - - - - pulse1_snap0 - pulse1_snap0 - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse1cycle_snap0 - pulse1cycle_snap0 - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1CYCLE_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse1_snap1 - pulse1_snap1 - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_SNAP1 - No description available - 0 - 32 - read-only - - - - - pulse1cycle_snap1 - pulse1cycle_snap1 - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1CYCLE_SNAP1 - No description available - 0 - 32 - read-only - - - - - adcx_cfg0 - adcx_cfg0 - 0x200 - 32 - 0x00000000 - 0x0000019F - - - X_ADCSEL - No description available - 8 - 1 - read-write - - - X_ADC_ENABLE - No description available - 7 - 1 - read-write - - - X_CHAN - No description available - 0 - 5 - read-write - - - - - adcx_cfg1 - adcx_cfg1 - 0x204 - 32 - 0x00004000 - 0xFFFFFFFF - - - X_PARAM1 - No description available - 16 - 16 - read-write - - - X_PARAM0 - No description available - 0 - 16 - read-write - - - - - adcx_cfg2 - adcx_cfg2 - 0x208 - 32 - 0x80000000 - 0xFFFFFFFF - - - X_OFFSET - No description available - 0 - 32 - read-write - - - - - adcy_cfg0 - adcy_cfg0 - 0x210 - 32 - 0x00000000 - 0x0000019F - - - Y_ADCSEL - No description available - 8 - 1 - read-write - - - Y_ADC_ENABLE - No description available - 7 - 1 - read-write - - - Y_CHAN - No description available - 0 - 5 - read-write - - - - - adcy_cfg1 - adcy_cfg1 - 0x214 - 32 - 0x40000000 - 0xFFFFFFFF - - - Y_PARAM1 - No description available - 16 - 16 - read-write - - - Y_PARAM0 - No description available - 0 - 16 - read-write - - - - - adcy_cfg2 - adcy_cfg2 - 0x218 - 32 - 0x80000000 - 0xFFFFFFFF - - - Y_OFFSET - No description available - 0 - 32 - read-write - - - - - cal_cfg - cal_cfg - 0x220 - 32 - 0x00000100 - 0x00FFFFFF - - - XY_DELAY - valid x/y delay, larger than this delay will be treated as invalid data. -Default 1.25us@200MHz; max 80ms; - 0 - 24 - read-write - - - - - phase_param - phase_param - 0x230 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - PHASE_PARAM - No description available - 0 - 32 - read-write - - - - - pos_threshold - pos_threshold - 0x238 - 32 - 0x80000000 - 0xFFFFFFFF - - - POS_THRESHOLD - No description available - 0 - 32 - read-write - - - - - 6 - 0x4 - uvw_pos0,uvw_pos1,uvw_pos2,uvw_pos3,uvw_pos4,uvw_pos5 - UVW_POS[%s] - no description available - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - UVW_POS0 - No description available - 0 - 32 - read-write - - - - - 6 - 0x4 - uvw_pos0_cfg,uvw_pos1_cfg,uvw_pos2_cfg,uvw_pos3_cfg,uvw_pos4_cfg,uvw_pos5_cfg - UVW_POS_CFG[%s] - no description available - 0x258 - 32 - 0x00000000 - 0x0000007F - - - POS_EN - No description available - 6 - 1 - read-write - - - U_POS_SEL - No description available - 4 - 2 - read-write - - - V_POS_SEL - No description available - 2 - 2 - read-write - - - W_POS_SEL - No description available - 0 - 2 - read-write - - - - - phase_cnt - phase_cnt - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - PHASE_CNT - No description available - 0 - 32 - read-write - - - - - phase_update - phase_update - 0x284 - 32 - 0x00000000 - 0xFFFFFFFF - - - INC - set to add value to phase_cnt - 31 - 1 - write-only - - - DEC - set to minus value from phase_cnt(set inc and dec same time willl act inc) - 30 - 1 - write-only - - - VALUE - value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation - 0 - 30 - write-only - - - - - position - position - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSITION - No description available - 0 - 32 - read-write - - - - - position_update - position_update - 0x28c - 32 - 0x00000000 - 0xFFFFFFFF - - - INC - set to add value to position - 31 - 1 - write-only - - - DEC - set to minus value from position(set inc and dec same time willl act inc) - 30 - 1 - write-only - - - VALUE - value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation - 0 - 30 - write-only - - - - - angle - No description available - 0x290 - 32 - 0x00000000 - 0xFFFFFFFF - - - ANGLE - No description available - 0 - 32 - read-only - - - - - pos_timeout - pos_timeout - 0x294 - 32 - 0x7FFFFFFF - 0xFFFFFFFF - - - ENABLE - enable position timeout feature, if timeout, send valid again - 31 - 1 - read-write - - - TIMEOUT - postion timeout value - 0 - 31 - read-write - - - - - - - QEI1 - QEI1 - QEIV2 - 0xf0304000 - - - QEO0 - QEO0 - QEO - 0xf0308000 - - 0x0 - 0x114 - registers - - - - WAVE_mode - analog waves mode - 0x0 - 32 - 0x00000000 - 0xFFFFFFF3 - - - WAVE2_ABOVE_MAX_LIMIT - wave2 above max limit mode. -0: output 0xffff. -1: output 0x0. -2: output as level_max_limit2.level0_max_limit - 30 - 2 - read-write - - - WAVE2_HIGH_AREA1_LIMIT - wave2 high area1 limit mode. -0: output 0xffff. -1: output as level_max_limit2.level0_max_limit - 29 - 1 - read-write - - - WAVE2_HIGH_AREA0_LIMIT - wave2 high area0 limit mode. -0: output 0xffff. -1: output as level_max_limit2.level0_max_limit - 28 - 1 - read-write - - - WAVE2_LOW_AREA1_LIMIT - wave2 low area1 limit mode. -0: output 0. -1: output as level_min_limit2.level1_min_limit - 27 - 1 - read-write - - - WAVE2_LOW_AREA0_LIMIT - wave2 low area0 limit mode. -0: output 0. -1: output as level_min_limit2.level1_min_limit - 26 - 1 - read-write - - - WAVE2_BELOW_MIN_LIMIT - wave2 below min limit mode. -0: output 0. -1: output 0xffff. -2: output as level_min_limit2.level1_min_limit - 24 - 2 - read-write - - - WAVE1_ABOVE_MAX_LIMIT - wave1 above max limit mode. -0: output 0xffff. -1: output 0x0. -2: output as level_max_limit1.level0_max_limit - 22 - 2 - read-write - - - WAVE1_HIGH_AREA1_LIMIT - wave1 high area1 limit mode. -0: output 0xffff. -1: output as level_max_limit1.level0_max_limit - 21 - 1 - read-write - - - WAVE1_HIGH_AREA0_LIMIT - wave1 high area0 limit mode. -0: output 0xffff. -1: output as level_max_limit1.level0_max_limit - 20 - 1 - read-write - - - WAVE1_LOW_AREA1_LIMIT - wave1 low area1 limit mode. -0: output 0. -1: output as level_min_limit1.level1_min_limit - 19 - 1 - read-write - - - WAVE1_LOW_AREA0_LIMIT - wave1 low area0 limit mode. -0: output 0. -1: output as level_min_limit1.level1_min_limit - 18 - 1 - read-write - - - WAVE1_BELOW_MIN_LIMIT - wave1 below min limit mode. -0: output 0. -1: output 0xffff. -2: output as level_min_limit1.level1_min_limit - 16 - 2 - read-write - - - WAVE0_ABOVE_MAX_LIMIT - wave0 above max limit mode. -0: output 0xffff. -1: output 0x0. -2: output as level_max_limit0.level0_max_limit - 14 - 2 - read-write - - - WAVE0_HIGH_AREA1_LIMIT - wave0 high area1 limit mode. -0: output 0xffff. -1: output as level_max_limit0.level0_max_limit - 13 - 1 - read-write - - - WAVE0_HIGH_AREA0_LIMIT - wave0 high area0 limit mode. -0: output 0xffff. -1: output as level_max_limit0.level0_max_limit - 12 - 1 - read-write - - - WAVE0_LOW_AREA1_LIMIT - wave0 low area1 limit mode. -0: output 0. -1: output as level_min_limit0.level1_min_limit - 11 - 1 - read-write - - - WAVE0_LOW_AREA0_LIMIT - wave0 low area0 limit mode. -0: output 0. -1: output as level_min_limit0.level1_min_limit - 10 - 1 - read-write - - - WAVE0_BELOW_MIN_LIMIT - wave0 below min limit mode. -0: output 0. -1: output 0xffff. -2: output as level_min_limit0.level1_min_limit - 8 - 2 - read-write - - - SADDLE_TYPE - saddle type seclect; -0:standard saddle. -1: triple-cos saddle. - 7 - 1 - read-write - - - EN_WAVE2_VD_VQ_INJECT - wave2 VdVq inject enable. -0: disable VdVq inject. -1: enable VdVq inject. - 6 - 1 - read-write - - - EN_WAVE1_VD_VQ_INJECT - wave1 VdVq inject enable. -0: disable VdVq inject. -1: enable VdVq inject. - 5 - 1 - read-write - - - EN_WAVE0_VD_VQ_INJECT - wave0 VdVq inject enable. -0: disable VdVq inject. -1: enable VdVq inject. - 4 - 1 - read-write - - - WAVES_OUTPUT_TYPE - wave0/1/2 output mode. -0: cosine wave. -1: saddle wave. -2. abs cosine wave. -3. saw wave - 0 - 2 - read-write - - - - - WAVE_resolution - resolution of wave0/1/2 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINES - wave0/1/2 resolution - 0 - 32 - read-write - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_PHASE_SHIFT[%s] - no description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - VAL - wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period - 0 - 16 - read-write - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_VD_VQ_INJECT[%s] - no description available - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VQ_VAL - Vq inject value - 16 - 16 - read-write - - - VD_VAL - Vd inject value - 0 - 16 - read-write - - - - - WAVE_vd_vq_load - load wave0/1/2 vd vq value - 0x20 - 32 - 0x00000000 - 0x00000001 - - - LOAD - load wave0/1/2 vd vq value. always read 0 -0: vd vq keep previous value. -1: load wave0/1/2 vd vq value at sametime. - 0 - 1 - write-only - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_AMPLITUDE[%s] - no description available - 0x24 - 32 - 0x00000000 - 0x0001FFFF - - - EN_SCAL - enable wave amplitude scaling. 0: disable; 1: enable - 16 - 1 - read-write - - - AMP_VAL - amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. - 0 - 16 - read-write - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_MID_POINT[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. - 0 - 32 - read-write - - - - - 3 - 0x8 - wave0,wave1,wave2 - WAVE_LIMIT[%s] - no description available - 0x3c - - min - wave0 low area limit value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT1 - low area limit level1 - 16 - 16 - read-write - - - LIMIT0 - low area limit level0 - 0 - 16 - read-write - - - - - max - wave0 high area limit value - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - LIMIT1 - high area limit level1 - 16 - 16 - read-write - - - LIMIT0 - high area limit level0 - 0 - 16 - read-write - - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_DEADZONE_SHIFT[%s] - no description available - 0x54 - 32 - 0x00000000 - 0x0000FFFF - - - VAL - wave0 deadzone shifter value - 0 - 16 - read-write - - - - - ABZ_mode - wave_a/b/z output mode - 0x60 - 32 - 0x00000000 - 0x11111333 - - - REVERSE_EDGE_TYPE - pulse reverse wave，reverse edge point: -0: between pulse's posedge and negedge, min period dedicated by the num line_width -1: edge change point flow pulse's negedge. - 28 - 1 - read-write - - - EN_WDOG - enable abz wdog: -0: disable abz wdog. -1: enable abz wdog. - 24 - 1 - read-write - - - Z_POLARITY - wave_z polarity. -0: normal output. -1: invert normal output - 20 - 1 - read-write - - - B_POLARITY - wave_b polarity. -0: normal output. -1: invert normal output - 16 - 1 - read-write - - - A_POLARITY - wave_a polarity. -0: normal output. -1: invert normal output - 12 - 1 - read-write - - - Z_TYPE - wave_z type: -0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. -1: zero pulse output high about 75% period. start from 0 to 75% period. -2: zero pulse output high about 100% period. -3: wave_z output as tree-phase wave same as wave_a/wave_b - 8 - 2 - read-write - - - B_TYPE - wave_b type: -0: Two-phase orthogonality wave_b. -1: reverse wave of pulse/reverse type. -2: down wave of up/down type. -3: Three-phase orthogonality wave_b. - 4 - 2 - read-write - - - A_TYPE - wave_a type: -0: Two-phase orthogonality wave_a. -1: pulse wave of pulse/reverse type. -2: up wave of up/down type. -3: Three-phase orthogonality wave_a. - 0 - 2 - read-write - - - - - ABZ_resolution - resolution of wave_a/b/z - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINES - wave_a/b/z resolution - 0 - 32 - read-write - - - - - 3 - 0x4 - a,b,z - ABZ_PHASE_SHIFT[%s] - no description available - 0x68 - 32 - 0x00000000 - 0x0000FFFF - - - VAL - wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period. - 0 - 16 - read-write - - - - - ABZ_line_width - Two-phase orthogonality wave 1/4 period - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINE - the num of system clk by 1/4 period when using as Two-phase orthogonality. - 0 - 32 - read-write - - - - - ABZ_wdog_width - wdog width of qeo - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - WIDTH - wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. - 0 - 32 - read-write - - - - - ABZ_postion_sync - sync abz owned postion - 0x7c - 32 - 0x00000000 - 0x00000001 - - - POSTION - load next valid postion into abz owned postion. always read 0 -0: sync abz owned postion with next valid postion. -1: not sync. - 0 - 1 - write-only - - - - - PWM_mode - pwm mode - 0x80 - 32 - 0x00000000 - 0xFFFF031F - - - PWM7_SAFETY - PWM safety mode phase table - 30 - 2 - read-write - - - PWM6_SAFETY - PWM safety mode phase table - 28 - 2 - read-write - - - PWM5_SAFETY - PWM safety mode phase table - 26 - 2 - read-write - - - PWM4_SAFETY - PWM safety mode phase table - 24 - 2 - read-write - - - PWM3_SAFETY - PWM safety mode phase table - 22 - 2 - read-write - - - PWM2_SAFETY - PWM safety mode phase table - 20 - 2 - read-write - - - PWM1_SAFETY - PWM safety mode phase table - 18 - 2 - read-write - - - PWM0_SAFETY - PWM safety mode phase table - 16 - 2 - read-write - - - PWM_ENTER_SAFETY_MODE - PWM enter safety mode -0: not enter -1: enter - 9 - 1 - read-write - - - PWM_SAFETY_BYPASS - PWM safety mode bypass -0: not bypass -1: bypass - 8 - 1 - read-write - - - REVISE_UP_DN - exchange PWM pairs’ output -0: not exchange. -1: exchange. - 4 - 1 - read-write - - - PHASE_NUM - pwm force phase number. - 0 - 4 - read-write - - - - - PWM_resolution - resolution of pwm - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINES - pwm resolution - 0 - 32 - read-write - - - - - 4 - 0x4 - a,b,c,d - PWM_PHASE_SHIFT[%s] - no description available - 0x88 - 32 - 0x00000000 - 0x0000FFFF - - - VAL - pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period - 0 - 16 - read-write - - - - - 24 - 0x4 - posedge0,posedge1,posedge2,posedge3,posedge4,posedge5,posedge6,posedge7,posedge8,posedge9,posedge10,posedge11,negedge0,negedge1,negedge2,negedge3,negedge4,negedge5,negedge6,negedge7,negedge8,negedge9,negedge10,negedge11 - PWM_PHASE_TABLE[%s] - no description available - 0x98 - 32 - 0x00000000 - 0x0000FFFF - - - PWM7 - pwm phase table value - 14 - 2 - read-write - - - PWM6 - pwm phase table value - 12 - 2 - read-write - - - PWM5 - pwm phase table value - 10 - 2 - read-write - - - PWM4 - pwm phase table value - 8 - 2 - read-write - - - PWM3 - pwm phase table value - 6 - 2 - read-write - - - PWM2 - pwm phase table value - 4 - 2 - read-write - - - PWM1 - pwm phase table value - 2 - 2 - read-write - - - PWM0 - pwm phase table value - 0 - 2 - read-write - - - - - PWM_postion_software - softwave inject postion - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSTION_SOFTWAVE - softwave inject postion - 0 - 32 - read-write - - - - - PWM_postion_sel - select softwave inject postion - 0xfc - 32 - 0x00000000 - 0x00000001 - - - POSTION_SEL - enable softwave inject postion. -0: disable. -1: enable. - 0 - 1 - read-write - - - - - PWM_status - qeo status - 0x100 - 32 - 0x00000000 - 0xFFFF0001 - - - PWM_FOURCE - qeo_pwm_force observe - 16 - 16 - read-only - - - PWM_SAFETY - pwm_fault status - 0 - 1 - read-only - - - - - PWM_debug0 - qeo debug 0 - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - WAVE1 - wave1 observe - 16 - 16 - read-only - - - WAVE0 - wave0 observe - 0 - 16 - read-only - - - - - PWM_debug1 - qeo debug 1 - 0x108 - 32 - 0x00000000 - 0x1111FFFF - - - QEO_FINISH - qeo finish observe - 28 - 1 - read-only - - - WAVE_Z - wave_z observe - 24 - 1 - read-only - - - WAVE_B - wave_b observe - 20 - 1 - read-only - - - WAVE_A - wave_a observe - 16 - 1 - read-only - - - WAVE2 - wave2 observe - 0 - 16 - read-only - - - - - PWM_debug2 - qeo debug 2 - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - ABZ_OWN_POSTION - abz_own_postion observe - 0 - 32 - read-only - - - - - PWM_debug3 - qeo debug 3 - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - ABZ_OWN_POSTION - abz_own_postion observe - 0 - 32 - read-only - - - - - - - QEO1 - QEO1 - QEO - 0xf030c000 - - - MMC0 - MMC0 - MMC - 0xf0310000 - - 0x0 - 0x334 - registers - - - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0xBFFFFFFF - - - SFTRST - Software reset, high active. When write 1 ,all internal logical will be reset. -0b - No action -1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. - 31 - 1 - read-write - - - INI_BR0_POS_REQ - Auto clear. Only effective in open_loop mode. - 29 - 1 - read-write - - - INI_BR1_POS_REQ - Auto clear. Only effective in open_loop mode. - 28 - 1 - read-write - - - FRCACCELZERO - Zeroise the accelerator calculation. - 27 - 1 - read-write - - - MS_COEF_EN - Multiple Coefficients Enable - 26 - 1 - read-write - - - INI_DELTA_POS_TRG_TYPE - 0: Time Stamp in the configuration -1: Risedge of In Trg[0] -2: Risedge of In Trg[1] -3: Risedge of out trg[0] -4: Risedge of out trg[1] -5: triggered by self position trigger -6: triggered by self speed trigger -Otherser: no function - 23 - 3 - read-write - - - INI_POS_TRG_TYPE - 0: Time Stamp in the configuration -1: Risedge of In Trg[0] -2: Risedge of In Trg[1] -3: Risedge of out trg[0] -4: Risedge of out trg[1] -5: triggered by self position trigger -6: triggered by self speed trigger -Otherser: no function - 20 - 3 - read-write - - - INI_DELTA_POS_CMD_MSK - 1: change -0: won't change -bit 3: for delta accel -bit 2: for delta speed -bit 1: for delta revolution -bit 0: for delta position - 16 - 4 - read-write - - - INI_DELTA_POS_REQ - 1: Command to reload the delta pos. Auto clear -0: - 15 - 1 - read-write - - - OPEN_LOOP_MODE - 1: in open loop mode -0: not in open loop mode - 14 - 1 - read-write - - - POS_TYPE - 1: 32-bit for rev+pos, with each element occupying 16 bits -0: 32-bit for rev, and 32 bit for pos -When CR[MANUAL_IO]==1, -1: means that the INI_POS is acting as INI_POS cmds -0: means that the INI_POS is simulating the input of iposition and itimestamp - 13 - 1 - read-write - - - INI_POS_CMD_MSK - 1: change -0: won't change -bit 3: for accel -bit 2: for speed -bit 1: for revolution -bit 0: for position - 9 - 4 - read-write - - - INI_POS_REQ - 1: Command to reload the positions. Auto clear -0: - 8 - 1 - read-write - - - INI_COEFS_CMD_MSK - 1: change -0: won't change -bit 2: for ACOEF -bit 1: for ICOEF -bit 0: for PCOEF - 5 - 3 - read-write - - - INI_COEFS_CMD - 1: Command to reload the coefs. Auto clear -0: - 4 - 1 - read-write - - - SHADOW_RD_REQ - 1: Shadow Request for read of tracking parameters. Auto clear -0: - 3 - 1 - read-write - - - ADJOP - 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. -0: Continuous tracking mode, without any boundary check - 2 - 1 - read-write - - - DISCRETETRC - 1: Discrete position input -0: Continuous position input - 1 - 1 - read-write - - - MOD_EN - Module Enable - 0 - 1 - read-write - - - - - STA - Status Register - 0x4 - 32 - 0x00000020 - 0xF00007F7 - - - ERR_ID - Tracking ERR_ID - 28 - 4 - read-only - - - SPEED_TRG_VALID - W1C - 10 - 1 - write-only - - - POS_TRG_VALID - W1C - 9 - 1 - write-only - - - INI_DELTA_POS_REQ_CMD_DONE - W1C - 8 - 1 - write-only - - - INI_BR0_POS_REQ_CMD_DONE - W1C - 7 - 1 - write-only - - - INI_BR1_POS_REQ_CMD_DONE - W1C - 6 - 1 - write-only - - - IDLE - Tracking Module in Idle status - 5 - 1 - read-only - - - OOSYNC - Tracking module out-of sync. W1C - 4 - 1 - write-only - - - INI_POS_REQ_CMD_DONE - W1C - 2 - 1 - write-only - - - INI_COEFS_CMD_DONE - W1C - 1 - 1 - write-only - - - SHADOW_RD_DONE - Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 - 0 - 1 - read-only - - - - - INT_EN - Interrupt Enable Register - 0x8 - 32 - 0x00000000 - 0x000007D7 - - - SPEED_TRG_VLD_IE - Interrupt Enable for SPEED_TRG_VALID - 10 - 1 - read-write - - - POS_TRG_VLD_IE - Interrupt Enable for POS_TRG_VALID - 9 - 1 - read-write - - - INI_DELTA_POS_REQ_CMD_DONE_IE - Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE - 8 - 1 - read-write - - - INI_BR0_POS_REQ_CMD_DONE_IE - Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE - 7 - 1 - read-write - - - INI_BR1_POS_REQ_CMD_DONE_IE - Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE - 6 - 1 - read-write - - - OOSYNC_IE - Interrupt Enable for OOSYNC - 4 - 1 - read-write - - - INI_POS_REQ_CMD_DONE_IE - Interrupt Enable for INI_POS_REQ_CMD_DONE - 2 - 1 - read-write - - - INI_COEFS_CMD_DONE_IE - Interrupt Enable for INI_COEFS_CMD_DONE - 1 - 1 - read-write - - - SHADOW_RD_DONE_IE - Interrupt Enable for SHADOW_RD_DONE - 0 - 1 - read-write - - - - - SYSCLK_FREQ - System Clock Frequency Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - system clock frequency, ufix<32, 0> - 0 - 32 - read-write - - - - - SYSCLK_PERIOD - System Clock Period Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> - 0 - 32 - read-write - - - - - OOSYNC_THETA_THR - Position Out-Of-Sync Threshold Regster - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> - 0 - 32 - read-write - - - - - DiscreteCfg0 - Discrete Mode Configuration 0 Register - 0x18 - 32 - 0x00000000 - 0x000FFFFF - - - POSMAX - Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> - 0 - 20 - read-write - - - - - DiscreteCfg1 - Discrete Mode Configuration 1 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INV_POSMAX - discrete mode: ufix<32, 0> of 1/(Number Of Lines) -continuous mode: the max delta for tracking from the last received position, ufix<32, 32> - 0 - 32 - read-write - - - - - ContCfg0 - Continuous Mode Configuration 0 Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - HALF_CIRC_THETA - the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> - 0 - 32 - read-write - - - - - INI_POS_TIME - The destined timestamp register for position initialization - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - indicate the time to change the values. -0: instant change - 0 - 32 - read-write - - - - - INI_POS - The destined position register for position initialization - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value； -continuous mode: ufix<32, 32> - 0 - 32 - read-write - - - - - INI_REV - The destined revolution register for position initialization - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value； -continuous mode: ufix<32, 0> - 0 - 32 - read-write - - - - - INI_SPEED - The destined speed register for position initialization - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value; -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - INI_ACCEL - The destined accelerator register for position initialization - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - INI_COEF_TIME - The destined timestamp register for coefficients initialization - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - indicate the time to change the values. -0: instant change - 0 - 32 - read-write - - - - - INI_PCOEF - The destined coefficient P register for coefficients initialization - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value, fix<32, 15> - 0 - 32 - read-write - - - - - INI_ICOEF - The destined coefficient I register for coefficients initialization - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value, fix<32, 21> - 0 - 32 - read-write - - - - - INI_ACOEF - The destined coefficient A register for coefficients initialization - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value, fix<32, 19> - 0 - 32 - read-write - - - - - ESTM_TIM - The timestamp register for internal estimation - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - ESTM_POS - The position register for the internal estimation - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - ESTM_REV - The revolution register for the internal estimation - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - ESTM_SPEED - The speed register for the internal estimation - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - ESTM_ACCEL - The accelerator register for theinternal estimation - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - CUR_PCOEF - The coefficient P register for the internal estimation - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - CUR_ICOEF - The coefficient I register for the internal estimation - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - CUR_ACOEF - The coefficient A register for the internal estimation - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - INI_DELTA_POS_TIME - The destined timestamp register for delta position initialization - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - indicate the time to change the values. -0: instant change - 0 - 32 - read-write - - - - - INI_DELTA_POS - The destined delta position register for delta position initialization - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: ufix <32, 32> - 0 - 32 - read-write - - - - - INI_DELTA_REV - The destined delta revolution register for delta position initialization - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 0> - 0 - 32 - read-write - - - - - INI_DELTA_SPEED - The destined delta speed register for delta position initialization - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value； -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - INI_DELTA_ACCEL - The destined delta accelerator register for delta position initialization - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - pos_trg_cfg - Tracking Configuration pos trigger cfg - 0x80 - 32 - 0x00000000 - 0x00000003 - - - EDGE - 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than - 1 - 1 - read-write - - - EN - 1-trigger valid; 0-Trigger not valid" - 0 - 1 - read-write - - - - - pos_trg_pos_thr - Tracking Configuration position threshold - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - For pos out trigger (pos). -ufix<32, 32> - 0 - 32 - read-write - - - - - pos_trg_rev_thr - Tracking Configuration revolution threshold - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - For pos out trigger (rev) -fix<32, 0> - 0 - 32 - read-write - - - - - speed_trg_cfg - Tracking Configuration speed trigger cfg - 0x8c - 32 - 0x00000000 - 0x00000007 - - - COMP_TYPE - 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) - 2 - 1 - read-write - - - EDGE - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than - 1 - 1 - read-write - - - EN - 1-trigger valid; 0-Trigger not valid -Normally it means either the max pos speed, or the min negative speed. - 0 - 1 - read-write - - - - - speed_trg_thr - Tracking Configuration speed threshold - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - For speed trigger. -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - 3 - 0x14 - 0,1,2 - COEF_TRG_CFG[%s] - no description available - 0xa0 - - err_thr - Tracking Configuration coef trigger cfg&index0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) -Note: ErrThr0>ErrThr1>ErrThr2 -ufix<31, 28> - 0 - 32 - read-write - - - - - P - Tracking Configuration coef trigger cfg&index0 P - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - P0_Coef, fix<32, 15> - 0 - 32 - read-write - - - - - I - Tracking Configuration coef trigger cfg&index0 I - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - I0_Coef, fix<32, 21> - 0 - 32 - read-write - - - - - A - Tracking Configuration coef trigger cfg&index0 A - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - A0_Coef，fix<32, 19> - 0 - 32 - read-write - - - - - TIME - Tracking Configuration coef trigger cfg&index0 time - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> - 0 - 32 - read-write - - - - - - 2 - 0x100 - 0,1 - BR[%s] - no description available - 0x100 - - BR_CTRL - Prediction Control Register - 0x0 - 32 - 0x00000000 - 0x63BDFFB7 - - - SPEED_TRG_VALID_IE - Interrupt Enable for SPEED_TRG_VALID - 30 - 1 - read-write - - - POS_TRG_VALID_IE - Interrupt Enable for POS_TRG_VALID - 29 - 1 - read-write - - - INI_POS_TRG_TYPE - 0: Time Stamp in the configuration -1: Risedge of In Trg[0] -2: Risedge of In Trg[1] -3: Risedge of out trg[0] -4: Risedge of out trg[1] -5: Risedge of self pos trigger -6: Risedge of self speed trigger -Others: no function - 23 - 3 - read-write - - - INI_POS_CMD_MSK - 1: change -0: won't change -bit 3: for accel -bit 2: for speed -bit 1: for revolution -bit 0: for position - 18 - 4 - read-write - - - INI_DELTA_POS_TRG_TYPE - 0: Time Stamp in the configuration -1: Risedge of In Trg[0] -2: Risedge of In Trg[1] -3: Risedge of out trg[0] -4: Risedge of out trg[1] -5: Risedge of self pos trigger -6: Risedge of self speed trigger -Others: no function - 14 - 3 - read-write - - - INI_DELTA_POS_DONE_IE - Interrupt Enable for INI_DELTA_POS_DONE - 13 - 1 - read-write - - - INI_DELTA_POS_CMD_MSK - 1: change -0: won't change -bit 3: for delta accel -bit 2: for delta speed -bit 1: for delta revolution -bit 0: for delta position - 9 - 4 - read-write - - - INI_DELTA_POS_REQ - 1: Command to reload the delta pos. Auto clear -0: - 8 - 1 - read-write - - - OPEN_LOOP_MODE - 1: in open loop mode -0: not in open loop mode - 7 - 1 - read-write - - - PRED_MODE - 1:continuously repeat pred, -0:cal the pred based on a definite time-stamp offset, -2:programed one-shot prediction mode - 4 - 2 - read-write - - - NF_TRG_TYPE - 1. Each non-first trigger by external trigger pin -0. Each non-first trigger by the timer - 2 - 1 - read-write - - - F_TRG_TYPE - 1. First trigger by external trigger pin -0. First trigger by the timer -When in CR[MANUAL_IO]=1 mode, it is the prediction trigger - 1 - 1 - read-write - - - BR_EN - Branch Enable - 0 - 1 - read-write - - - - - BR_TIMEOFF - Prediction Timing Offset Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - ufix<32, 0> time offset incycles from the trigger time - 0 - 32 - read-write - - - - - BR_TRG_PERIOD - Prediction Triggering Period Offset Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - uifx<32, 0>, time offset incycles between each trigger time - 0 - 32 - read-write - - - - - BR_TRG_F_TIME - Prediction Triggering First Offset Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - uifx<32, 0> the time for the first trigger - 0 - 32 - read-write - - - - - BR_ST - Prediction Status Register - 0x10 - 32 - 0x00000000 - 0x0000076F - - - OPEN_LOOP_ST - 1：in open loop mode -0：in closed loop mode - 10 - 1 - read-only - - - SPEED_TRG_VLD - 1：self speed trigger event found -0：self speed trigger event not found yet - 9 - 1 - write-only - - - POS_TRG_VLD - 1：self position trigger event found -0：self position trigger event not found yet - 8 - 1 - write-only - - - INI_DELTA_POS_DONE - 1: the initialization of delta position command is done -0: the initialization of delta position command is not done - 6 - 1 - write-only - - - IDLE - 1: The prediction module is idle. -0: The prediction module is not idle. - 5 - 1 - read-only - - - ERR_ID - The module's error ID output - 0 - 4 - read-only - - - - - BR_TRG_pos_cfg - Prediction Configuration postion trigger cfg - 0x40 - 32 - 0x00000000 - 0x00000003 - - - EDGE - bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than - 1 - 1 - read-write - - - EN - 1-trigger valid; 0-Trigger not valid - 0 - 1 - read-write - - - - - BR_TRG_pos_thr - Prediction Configuration postion threshold - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - For pos out trigger (pos). -ufix<32, 32> - 0 - 32 - read-write - - - - - BR_TRG_rev_thr - Prediction Configuration revolutiom threshold - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - For pos out trigger (rev) -ufix<32, 0> - 0 - 32 - read-write - - - - - BR_TRG_speed_cfg - Prediction Configuration speed trigger cfg - 0x4c - 32 - 0x00000000 - 0x00000007 - - - COMP_TYPE - Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) - 2 - 1 - read-write - - - EDGE_SEL - 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than - 1 - 1 - read-write - - - EN - 1-trigger valid; 0-Trigger not valid -Normally it means either the max pos speed, or the min negative speed. - 0 - 1 - read-write - - - - - BR_TRG_speed_thr - Prediction Configuration speed threshold - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - For speed trigger. -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - BR_INI_POS_TIME - Initialization timestamp for open-loop mode - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - indicate the time to change the values. -0: instant change - 0 - 32 - read-write - - - - - BR_INI_POS - Initialization position for open-loop mode - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -ufix<32, 32> - 0 - 32 - read-write - - - - - BR_INI_REV - Initialization revolution for open-loop mode - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -ufix<32, 0> - 0 - 32 - read-write - - - - - BR_INI_SPEED - Initialization speed for open-loop mode - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -fix<32, 19> - 0 - 32 - read-write - - - - - BR_INI_ACCEL - Initialization acceleration for open-loop mode - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - BR_INI_DELTA_POS_TIME - Initialization timestamp for delta mode in prediction mode - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - indicate the time to change the values. -0: instant change - 0 - 32 - read-write - - - - - BR_INI_DELTA_POS - Initialization delta position for delta mode in prediction mode - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: ufix<32, 32> - 0 - 32 - read-write - - - - - BR_INI_DELTA_REV - Initialization delta revolution for delta mode in prediction mode - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 0> - 0 - 32 - read-write - - - - - BR_INI_DELTA_SPEED - Initialization delta speed for delta mode in prediction mode - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - BR_INI_DELTA_ACCEL - Initialization delta acceleration for delta mode in prediction mode - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value -continuous mode: fix<32, 19> - 0 - 32 - read-write - - - - - BR_CUR_POS_TIME - Monitor of the output timestamp - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BR_CUR_POS - Monitor of the output position - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BR_CUR_REV - Monitor of the output revolution - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BR_CUR_SPEED - Monitor of the output speed - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BR_CUR_ACCEL - Monitor of the output acceleration - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - - BK0_TIMESTAMP - Monitor of the just received input timestamp for tracing logic - 0x300 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK0_POSITION - Monitor of the just received input position for tracing logic - 0x304 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK0_REVOLUTION - Monitor of the just received input revolution for tracing logic - 0x308 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK0_SPEED - Monitor of the just received input speed for tracing logic - 0x30c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK0_ACCELERATOR - Monitor of the just received input acceleration for tracing logic - 0x310 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK1_TIMESTAMP - Monitor of the previous received input timestamp for tracing logic - 0x320 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK1_POSITION - Monitor of the previous received input position for tracing logic - 0x324 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK1_REVOLUTION - Monitor of the previous received input revolution for tracing logic - 0x328 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK1_SPEED - Monitor of the previous received input speed for tracing logic - 0x32c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - BK1_ACCELERATOR - Monitor of the previous received input acceleration for tracing logic - 0x330 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - the value - 0 - 32 - read-only - - - - - - - MMC1 - MMC1 - MMC - 0xf0314000 - - - PWM0 - PWM0 - PWM - 0xf0318000 - - 0x0 - 0x290 - registers - - - - unlk - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, -otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - sta - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - - - rld - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, -and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - frcmd - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0-7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - shlk - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, write access is not permitted - 31 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CHCFG[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - - - gcr - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFEF - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as compare shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. -This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. -User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - TIMERRESET - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear - 3 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - write-only - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - shcr - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPPOS[%s] - no description available - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - cnt - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPNEG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - cntcopy - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - PWMCFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - sr - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - write-only - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - write-only - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - write-only - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - write-only - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - write-only - - - - - irqen - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - dmaen - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - 24 - 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMPCFG[%s] - no description available - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - - - - - PWM1 - PWM1 - PWM - 0xf031c000 - - - RDC - RDC - RDC - 0xf0320000 - - 0x0 - 0xf0 - registers - - - - rdc_ctl - rdc control - 0x0 - 32 - 0x00000000 - 0x003FF077 - - - TS_SEL - Time stamp selection for accumulation -0: end of accumulation -1: start of accumulation -2: center of accumulation - 20 - 2 - read-write - - - ACC_LEN - Accumulate time, support on the fly change -0：1 cycle -1：2 cycles -… -255: 256 cycles - 12 - 8 - read-write - - - RECTIFY_SEL - Select reference point of rectify signal -0: 0 phase of internal exciting signal -1: 90 phase of internal exciting signal -2: 180 phase of internal exciting signal -3: 270 phase of internal exciting signal -4: use value on external pin -5: use invert value on external pin - 4 - 3 - read-write - - - ACC_EN - Enable rdc accumulate -0: rdc disable -1: rdc enable - 2 - 1 - read-write - - - EXC_START - Write 1 start excite signal, always read 0 -0: no effect -1: start excite signal - 1 - 1 - read-write - - - EXC_EN - Enable rdc excite signal -0: rdc disable -1: rdc enable - 0 - 1 - read-write - - - - - acc_i - accumulate result of i_channel - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - accumulate result of i_channel, this is a signed number - 0 - 32 - read-only - - - - - acc_q - accumulate result of q_channel - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - accumulate result of q_channel, this is a signed number - 0 - 32 - read-only - - - - - in_ctl - input channel selection - 0xc - 32 - 0x00000000 - 0x0011F11F - - - PORT_Q_SEL - Input port selection for q_channel, -0:sel port0 -1:sel port1 - 20 - 1 - read-write - - - CH_Q_SEL - Input channel selection for q_channel -0: channel 0 selected -1: channel 1 selected -… -31: channel 31 selected - 12 - 5 - read-write - - - PORT_I_SEL - Input port selection for i_channel, -0:sel port0 -1:sel port1 - 8 - 1 - read-write - - - CH_I_SEL - Input channel selection for i_channel -0: channel 0 selected -1: channel 1 selected -… -31: channel 31 selected - 0 - 5 - read-write - - - - - out_ctl - output channel selection - 0x10 - 32 - 0x00000000 - 0x00001F1F - - - CH_Q_SEL - Output channel selection for q_channel - 8 - 5 - read-write - - - CH_I_SEL - Output channel selection for i_channel - 0 - 5 - read-write - - - - - exc_timming - excitation signal timming setting - 0x34 - 32 - 0x000400C8 - 0x01FFFFFF - - - SWAP - Swap output of PWM and DAC -0: disable swap -1: swap output - 24 - 1 - read-write - - - PWM_PRD - Pwm period in samples， -0：1 sample period -1: 2 sample period -... -15: 16 sample period - 20 - 4 - read-write - - - SMP_NUM - Number of sample every excitation period -0: 4 point -1: 8 point -… -8: 1024 point - 16 - 4 - read-write - - - SMP_RATE - The period for excitation sample in clock cycle， -0: not allowed -1: 1 cycle -2: 2 cycles -… -65535 : 65535 cycles - 0 - 16 - read-write - - - - - exc_scaling - amplitude scaling for excitation - 0x38 - 32 - 0x00000011 - 0x000000FF - - - AMP_EXP - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 4 - 4 - read-write - - - AMP_MAN - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 0 - 4 - read-write - - - - - exc_offset - amplitude offset setting - 0x3c - 32 - 0x00800000 - 0x00FFFFFF - - - AMP_OFFSET - Offset for excitation - 0 - 24 - read-write - - - - - pwm_scaling - amplitude scaling for excitation - 0x40 - 32 - 0x00000111 - 0x000031FF - - - N_POL - Polarity of exc_n signal -0: high active -1: low active - 13 - 1 - read-write - - - P_POL - Polarity of exc_p signal -0: high active -1: low active - 12 - 1 - read-write - - - DITHER - Enable dither of pwm -0: disable -1: enable - 8 - 1 - read-write - - - AMP_EXP - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 4 - 4 - read-write - - - AMP_MAN - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 0 - 4 - read-write - - - - - pwm_offset - amplitude offset setting - 0x44 - 32 - 0x00000064 - 0x00FFFFFF - - - AMP_OFFSET - Offset for excitation - 0 - 24 - read-write - - - - - trig_out0_cfg - Configuration for trigger out 0 in clock cycle - 0x48 - 32 - 0x00100019 - 0x001FFFFF - - - ENABLE - Enable trigger out0 -0: disable -1: enable - 20 - 1 - read-write - - - LEAD_TIM - Lead time for trigger out0 from center of low level , this is a signed value -… -2: 2 cycle befor center of low level -1: 1 cycle before center of low level -0: center of low level --1: 1cycle after center of low level --2: 2cycle after center of low level - 0 - 20 - read-write - - - - - trig_out1_cfg - Configuration for trigger out 1 in clock cycle - 0x4c - 32 - 0x0010004B - 0x001FFFFF - - - ENABLE - Enable trigger out1 -0: disable -1: enable - 20 - 1 - read-write - - - LEAD_TIM - Lead time for trigger out0 from center of hight level , this is a signed value -… -2: 2 cycle befor center of hight level -1: 1 cycle before center of hight level -0: center of hight level --1: 1cycle after center of hight level --2: 2cycle after center of hight level - 0 - 20 - read-write - - - - - pwm_dz - pwm dead zone control in clock cycle - 0x50 - 32 - 0x00000000 - 0x0000FFFF - - - DZ_N - Exc_n dead zone in clock cycle before swap -0: no dead zone -1: 1 cycle dead zone -2: 2 cycle dead zone -… - 8 - 8 - read-write - - - DZ_P - Exc_p dead zone in clock cycle before swap -0: no dead zone -1: 1 cycle dead zone -2: 2 cycle dead zone -… - 0 - 8 - read-write - - - - - sync_out_ctrl - synchronize output signal control - 0x54 - 32 - 0x00000000 - 0xFFFF0033 - - - PWM_OUT_DLY - Delay bettween the delyed trigger and the first pwm pulse in clock cycle -1: 1 cycle -2: 2 cycle -… - 16 - 16 - read-only - - - MIN2TRIG_EN - Enable trigger out from the min point of exciting signal -1: enable -0: disable - 5 - 1 - read-write - - - MAX2TRIG_EN - Enable trigger out from the max point of exciting signal -1: enable -0: disable - 4 - 1 - read-write - - - SYNC_OUT_SEL - Select output synchornize signal -0: 0 phase of internal exciting signal -1: 90 phase of internal exciting signal -2: 180 phase of internal exciting signal -3: 270 phase of internal exciting signal - 0 - 2 - read-write - - - - - exc_sync_dly - trigger in delay timming in soc bus cycle - 0x58 - 32 - 0x01000001 - 0x01FFFFFF - - - DISABLE - Disable hardware trigger input -0: enable -1: disable - 24 - 1 - read-write - - - DELAY - Trigger in delay timming in bus cycle from rising edge of trigger signal -0: 1 cycle -1: 2 cycle -… -0xffffff: 2^24 cycle - 0 - 24 - read-write - - - - - max_i - max value of i_channel - 0x70 - 32 - 0x00000000 - 0xFFFFFF01 - - - MAX - Max value of i_channel, write clear - 8 - 24 - read-write - - - VALID - Max value valid, write clear -0: max value is not valid -1: max value is valid - 0 - 1 - read-write - - - - - min_i - min value of i_channel - 0x74 - 32 - 0x00000000 - 0xFFFFFF01 - - - MIN - Min value of i_channel, write clear - 8 - 24 - read-write - - - VALID - Min value valid, write clear -0: min value is not valid -1: min value is valid - 0 - 1 - read-write - - - - - max_q - max value of q_channel - 0x78 - 32 - 0x00000000 - 0xFFFFFF01 - - - MAX - Max value of q_channel, write clear - 8 - 24 - read-write - - - VALID - Max value valid, write clear -0: max value is not valid -1: max value is valid - 0 - 1 - read-write - - - - - min_q - min value of q_channel - 0x7c - 32 - 0x00000000 - 0xFFFFFF01 - - - MIN - Min value of q_channel, write clear - 8 - 24 - read-write - - - VALID - Min value valid, write clear -0: min value is not valid -1: min value is valid - 0 - 1 - read-write - - - - - thrs_i - the offset setting for edge detection of the i_channel - 0x80 - 32 - 0x00000000 - 0xFFFFFF00 - - - THRS - The offset setting for edge detection of the i_channel, signed number -… -2: the offset is 0x800000+2 -1: the offset is 0x800000+1 -0: the offset is 0x800000 --1: the offset is 0x800000-1 --2: the offset is 0x800000-2 -… - 8 - 24 - read-write - - - - - thrs_q - the offset setting for edge detection of the q_channel - 0x84 - 32 - 0x00000000 - 0xFFFFFF00 - - - THRS - The offset setting for edge detection of the q_channel, signed number -… -2: the offset is 0x800000+2 -1: the offset is 0x800000+1 -0: the offset is 0x800000 --1: the offset is 0x800000-1 --2: the offset is 0x800000-2 -… - 8 - 24 - read-write - - - - - edg_det_ctl - the control for edge detection - 0x88 - 32 - 0x00000080 - 0x000003F7 - - - HOLD - The minimum edge distance in sample -0:1 sample -1:2 sample -2:3 samples -… -63:64 samples - 4 - 6 - read-write - - - FILTER - The continuous positive or negative number for edge detection -0: 1 -1: 2 -… -7: 8 - 0 - 3 - read-write - - - - - acc_scaling - scaling for accumulation result - 0x8c - 32 - 0x00000000 - 0x0000010F - - - TOXIC_LK - Toxic accumulation data be removed control -1: enable -0: disable - 8 - 1 - read-write - - - ACC_SHIFT - Accumulation value shift control, this is a sign number. -0: {acc[39],acc[38:8]} -1: {acc[39],acc[37:7]} -2: {acc[39],acc[36:6]} -… -7: {acc[39],acc[31:1]} -8: {acc[39],acc[30:0]} -9: acc/2^9 -10: acc/2^10 -… -15:acc/2^15 - 0 - 4 - read-write - - - - - exc_period - period of excitation - 0x90 - 32 - 0x00001770 - 0xFFFFFFFF - - - EXC_PERIOD - The num in clock cycle for period of excitation -0: invalid value -1:1 cycle -2:2 cycles -… - 0 - 32 - read-write - - - - - sync_delay_i - delay setting in clock cycle for synchronous signal - 0xa0 - 32 - 0x00000008 - 0xFFFFFFFF - - - DELAY - Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. -0: invalid value -1: 1 cycles -2: 2 cycles -... - 0 - 32 - read-write - - - - - rise_delay_i - delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RISE_DELAY - Delay value on rising edge of i_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - fall_delay_i - delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - FALL_DELAY - Delay value on falling edge of i_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - sample_rise_i - sample value on rising edge of rectify signal - 0xb0 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on rising edge of rectify signal - 8 - 24 - read-only - - - - - sample_fall_i - sample value on falling edge of rectify signal - 0xb4 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on falling edge of rectify signal - 8 - 24 - read-only - - - - - acc_cnt_i - number of accumulation - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - sample number during the negtive of rectify signal -1: 1 -2: 2 -… - 16 - 16 - read-only - - - CNT_POS - sample number during the positive of rectify signal -1: 1 -2: 2 -… - 0 - 16 - read-only - - - - - sign_cnt_i - sample counter of opposite sign with rectify signal - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - Positive sample counter during negative rectify signal - 16 - 16 - read-only - - - CNT_POS - Negative sample counter during positive rectify signal - 0 - 16 - read-only - - - - - sync_delay_q - delay setting in clock cycle for synchronous signal - 0xc0 - 32 - 0x00000008 - 0xFFFFFFFF - - - DELAY - Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. -0: invalid value -1: 1 cycles -2: 2 cycles -... - 0 - 32 - read-write - - - - - rise_delay_q - delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RISE_DELAY - Delay value on rising edge of q_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - fall_delay_q - delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - FALL_DELAY - Delay value on falling edge of q_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - sample_rise_q - sample value on rising edge of rectify signal - 0xd0 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on rising edge of rectify signal - 8 - 24 - read-only - - - - - sample_fall_q - sample value on falling edge of rectify signal - 0xd4 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on falling edge of rectify signal - 8 - 24 - read-only - - - - - acc_cnt_q - number of accumulation - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - sample number during the negtive of rectify signal -1: 1 -2: 2 -… - 16 - 16 - read-only - - - CNT_POS - sample number during the positive of rectify signal -1: 1 -2: 2 -… - 0 - 16 - read-only - - - - - sign_cnt_q - sample counter of opposite sign with rectify signal - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - Positive sample counter during negative rectify signal - 16 - 16 - read-only - - - CNT_POS - Negative sample counter during positive rectify signal - 0 - 16 - read-only - - - - - amp_max - the maximum of acc amplitude - 0xe0 - 32 - 0x01000000 - 0xFFFFFFFF - - - MAX - the maximum of acc amplitude - 0 - 32 - read-write - - - - - amp_min - the minimum of acc amplitude - 0xe4 - 32 - 0x00400000 - 0xFFFFFFFF - - - MIN - the minimum of acc amplitude - 0 - 32 - read-write - - - - - int_en - the interrupt mask control - 0xe8 - 32 - 0x00000000 - 0x8000FFFF - - - INT_EN - enable interrupt output - 31 - 1 - read-write - - - ACC_VLD_I_EN - i_channel accumulate valid interrupt enable for i_channel - 15 - 1 - read-write - - - ACC_VLD_Q_EN - q_channel accumulate valid interrupt enable for i_channel - 14 - 1 - read-write - - - RISING_DELAY_I_EN - i_channel delayed rectify signal rising edge interrupt enable - 13 - 1 - read-write - - - FALLING_DELAY_I_EN - i_channel delayed rectify signal falling edge interrupt enable - 12 - 1 - read-write - - - RISING_DELAY_Q_EN - q_channel delayed rectify signal rising edge interrupt enable - 11 - 1 - read-write - - - FALLING_DELAY_Q_EN - q_channel delayed rectify signal falling edge interrupt enable - 10 - 1 - read-write - - - SAMPLE_RISING_I_EN - i_channel rising edge interrupt enable - 9 - 1 - read-write - - - SAMPLE_FALLING_I_EN - i_channel falling edge interrupt enable - 8 - 1 - read-write - - - SAMPLE_RISING_Q_EN - q_channel rising edge interrupt enable - 7 - 1 - read-write - - - SAMPLE_FALLING_Q_EN - q_channel falling edge interrupt enable - 6 - 1 - read-write - - - ACC_VLD_I_OVH_EN - i_channel accumulate overflow interrupt enable - 5 - 1 - read-write - - - ACC_VLD_Q_OVH_EN - q_channel accumulate overflow interrupt enable - 4 - 1 - read-write - - - ACC_VLD_I_OVL_EN - i_channel accumulate underflow interrupt enable - 3 - 1 - read-write - - - ACC_VLD_Q_OVL_EN - q_channel accumulate underflow interrupt enable - 2 - 1 - read-write - - - ACC_AMP_OVH_EN - accumulate ample overflow interrupt enable - 1 - 1 - read-write - - - ACC_AMP_OVL_EN - accumulate ample underflow interrupt enable - 0 - 1 - read-write - - - - - adc_int_state - the interrupt state - 0xec - 32 - 0x00000000 - 0x0000FFFF - - - ACC_VLD_I_STA - i_channel accumulate valid interrupt status for i_channel - 15 - 1 - write-only - - - ACC_VLD_Q_STA - q_channel accumulate valid interrupt status for i_channel - 14 - 1 - write-only - - - RISING_DELAY_I_STA - i_channel delayed rectify signal rising edge interrupt status - 13 - 1 - write-only - - - FALLING_DELAY_I_STA - i_channel delayed rectify signal falling edge interrupt status - 12 - 1 - write-only - - - RISING_DELAY_Q_STA - q_channel delayed rectify signal rising edge interrupt status - 11 - 1 - write-only - - - FALLING_DELAY_Q_STA - q_channel delayed rectify signal falling edge interrupt status - 10 - 1 - write-only - - - SAMPLE_RISING_I_STA - i_channel rising edge interrupt status - 9 - 1 - write-only - - - SAMPLE_FALLING_I_STA - i_channel falling edge interrupt status - 8 - 1 - write-only - - - SAMPLE_RISING_Q_STA - q_channel rising edge interrupt status - 7 - 1 - write-only - - - SAMPLE_FALLING_Q_STA - q_channel falling edge interrupt status - 6 - 1 - write-only - - - ACC_VLD_I_OVH_STA - i_channel accumulate overflow interrupt status - 5 - 1 - write-only - - - ACC_VLD_Q_OVH_STA - q_channel accumulate overflow interrupt status - 4 - 1 - write-only - - - ACC_VLD_I_OVL_STA - i_channel accumulate underflow interrupt status - 3 - 1 - write-only - - - ACC_VLD_Q_OVL_STA - q_channel accumulate underflow interrupt status - 2 - 1 - write-only - - - ACC_AMP_OVH_STA - accumulate ample overflow interrupt status - 1 - 1 - write-only - - - ACC_AMP_OVL_STA - accumulate ample underflow interrupt status - 0 - 1 - write-only - - - - - - - PLB - PLB - PLB - 0xf0324000 - - 0x0 - 0x480 - registers - - - - 4 - 0x20 - 0,1,2,3 - TYPE_A[%s] - no description available - 0x0 - - 4 - 0x4 - 0,1,2,3 - LOOKUP_TABLE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0000FFFF - - - LOOKUP_TABLE - using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. - 0 - 16 - read-write - - - - - sw_inject - TYPE A CHN&index0 software inject - 0x10 - 32 - 0x00000000 - 0x0000000F - - - SW_INJECT - software can inject value to TYPEA's output - 0 - 4 - read-write - - - - - - 4 - 0x20 - 0,1,2,3 - TYPE_B[%s] - no description available - 0x400 - - 2 - 0x4 - 0,1 - LUT[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOOKUP_TABLE - lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in - 0 - 32 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_VALUE - cmp value, using as data unit operation - 0 - 32 - read-write - - - - - mode - TYPE B CHN&index0 mode ctrl - 0x18 - 32 - 0x00000000 - 0x0001FFFF - - - OPT_SEL - operation selection in data unit. - 16 - 1 - read-write - - - OUT3_SEL - trig out 3 output type in current channel - 12 - 4 - read-write - - - OUT2_SEL - trig out 2 output type in current channel - 8 - 4 - read-write - - - OUT1_SEL - trig out 1 output type in current channel - 4 - 4 - read-write - - - OUT0_SEL - trig out 0 output type in current channel - 0 - 4 - read-write - - - - - sw_inject - TYPE B CHN&index0 software inject - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - SOFTWARE_INJECT - data unit value can be changed if program this register - 0 - 32 - read-write - - - - - - - - SYNT - SYNT - SYNT - 0xf0328000 - - 0x0 - 0x30 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0xF0000037 - - - TIMESTAMP_INC_NEW - set to increase the timesamp with new value, auto clr - 31 - 1 - write-only - - - TIMESTAMP_DEC_NEW - set to decrease the timesamp with new value, auto clr - 30 - 1 - write-only - - - TIMESTAMP_SET_NEW - set the timesamp to new value, auto clr - 29 - 1 - write-only - - - TIMESTAMP_RESET - reset timesamp to 0, auto clr - 28 - 1 - write-only - - - TIMESTAMP_DEBUG_EN - set to enable cpu_debug_mode to stop the timesamp - 5 - 1 - read-write - - - TIMESTAMP_ENABLE - set to enable the timesamp , clr to stop - 4 - 1 - read-write - - - COUNTER_DEBUG_EN - set to enable cpu_debug_mode to stop the counter - 2 - 1 - read-write - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - timestamp_new - timestamp new value register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - new value for timesamp , can be used as set/inc/dec - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - timestamp_sav - timestamp trig save value - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - use the trigger to save timesamp here - 0 - 32 - read-only - - - - - timestamp_cur - timestamp read value - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - current timesamp value - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - SEI - SEI - SEI - 0xf032c000 - - 0x0 - 0x3a80 - registers - - - - 2 - 0x400 - 0,1 - CTRL[%s] - no description available - 0x0 - - ENGINE_CTRL - Engine control register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WATCH - Enable watch dog -0: Watch dog disabled -1: Watch dog enabled - 24 - 1 - read-write - - - ARMING - Wait for trigger before excuting -0: Execute on enable -1: Wait trigger before exection after enabled - 16 - 1 - read-write - - - EXCEPT - Explain timout as exception -0: when timeout, pointer move to next instruction -1: when timeout, pointer jump to timeout vector - 8 - 1 - read-write - - - REWIND - Rewind execution pointer -0: run -1: clean status and rewind - 4 - 1 - read-write - - - ENABLE - Enable -0: disable -1: enable - 0 - 1 - read-write - - - - - ENGINE_PTR_CFG - Pointer configuration register - 0x4 - 32 - 0x00000000 - 0xFF1FFFFF - - - DAT_CDM - Select DATA register to receive CDM bit in BiSSC slave mode -0: ignore -1: command -2: data register 2 -3: data register 3 -... -29:data register 29 -30: value 0 when send, ignore in receive -31: value1 when send, ignore in receive - 24 - 5 - read-write - - - DAT_BASE - Bias for data register access, if calculated index bigger than 32, index will wrap around -0: real data index -1: access index is 1 greater than instruction address -2: access index is 2 greater than instruction address -... -31: access index is 31 greater than instruction address - 16 - 5 - read-write - - - POINTER_WDOG - Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME - 8 - 8 - read-write - - - POINTER_INIT - Initial execute pointer - 0 - 8 - read-write - - - - - ENGINE_WDG_CFG - Watch dog configuration register - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - WDOG_TIME - Time out count for each instruction, counter in bit time. - 0 - 16 - read-write - - - - - ENGINE_EXE_STA - Execution status - 0x10 - 32 - 0x00000000 - 0x00110101 - - - TRIGERED - Execution has been triggered -0: Execution not triggered -1: Execution triggered - 20 - 1 - read-only - - - ARMED - Waiting for trigger for execution -0: Not in waiting status -1: In waiting status - 16 - 1 - read-only - - - EXPIRE - Watchdog timer expired -0: Not expired -1: Expired - 8 - 1 - read-only - - - STALL - Program finished -0: Program is executing -1: Program finished - 0 - 1 - read-only - - - - - ENGINE_EXE_PTR - Execution pointer - 0x14 - 32 - 0x00000000 - 0x1F1F00FF - - - HALT_CNT - Halt count in halt instrution - 24 - 5 - read-only - - - BIT_CNT - Bit count in send and receive instruction execution - 16 - 5 - read-only - - - POINTER - Current program pointer - 0 - 8 - read-only - - - - - ENGINE_EXE_INST - Execution instruction - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - INST - Current instruction - 0 - 32 - read-only - - - - - ENGINE_WDG_STA - Watch dog status - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - WDOG_CNT - Current watch dog counter value - 0 - 16 - read-only - - - - - XCVR_CTRL - Transceiver control register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRISMP - Tipple sampe -0: sample 1 time for data transition -1: sample 3 times in receive and result in 2oo3 - 12 - 1 - read-write - - - PAR_CLR - Clear parity error, this is a self clear bit -0: no effect -1: clear parity error - 8 - 1 - write-only - - - RESTART - Restart tranceiver, this is a self clear bit -0: no effect -1: reset tranceiver - 4 - 1 - write-only - - - MODE - Tranceiver mode -0: synchronous maaster -1: synchronous slave -2: asynchronous mode -3: asynchronous mode - 0 - 2 - read-write - - - - - XCVR_TYPE_CFG - Transceiver configuration register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - WAIT_LEN - Number of extra stop bit for asynchronous mode -0: 1 bit -1: 2 bit -... -255: 256 bit - 24 - 8 - read-write - - - DATA_LEN - Number of data bit for asynchronous mode -0: 1 bit -1: 2 bit -... -31: 32 bit - 16 - 5 - read-write - - - PAR_POL - Polarity of parity for asynchronous mode -0: even -1: odd - 9 - 1 - read-write - - - PAR_EN - enable parity check for asynchronous mode -0: disable -1: enable - 8 - 1 - read-write - - - DA_IDLEZ - Idle state driver of data line -0: output -1: high-Z - 3 - 1 - read-write - - - CK_IDLEZ - Idle state driver of clock line -0: output -1: high-Z - 2 - 1 - read-write - - - DA_IDLEV - Idle state value of data line -0: data'0' -1: data'1' - 1 - 1 - read-write - - - CK_IDLEV - Idle state value of clock line -0: data'0' -1: data'1' - 0 - 1 - read-write - - - - - XCVR_BAUD_CFG - Transceiver baud rate register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYNC_POINT - Baud synchronous time, minmum bit time - 16 - 16 - read-write - - - BAUD_DIV - Baud rate, bit time in system clock cycle - 0 - 16 - read-write - - - - - XCVR_DATA_CFG - Transceiver data timing configuration - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TXD_POINT - data transmit point in system clcok cycle - 16 - 16 - read-write - - - RXD_POINT - data receive point in system clcok cycle - 0 - 16 - read-write - - - - - XCVR_CLK_CFG - Transceiver clock timing configuration - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CK1_POINT - clock point 1 in system clcok cycle - 16 - 16 - read-write - - - CK0_POINT - clock point 0 in system clcok cycle - 0 - 16 - read-write - - - - - XCVR_PIN - Transceiver pin status - 0x38 - 32 - 0x00000000 - 0x07070707 - - - OE_CK - CK drive state -0: input -1: output - 26 - 1 - read-only - - - DI_CK - CK state -0: data 0 -1: data 1 - 25 - 1 - read-only - - - DO_CK - CK output -0: data 0 -1: data 1 - 24 - 1 - read-only - - - OE_RX - RX drive state -0: input -1: output - 18 - 1 - read-only - - - DI_RX - RX state -0: data 0 -1: data 1 - 17 - 1 - read-only - - - DO_RX - RX output -0: data 0 -1: data 1 - 16 - 1 - read-only - - - OE_DE - DE drive state -0: input -1: output - 10 - 1 - read-only - - - DI_DE - DE state -0: data 0 -1: data 1 - 9 - 1 - read-only - - - DO_DE - DE output -0: data 0 -1: data 1 - 8 - 1 - read-only - - - OE_TX - TX drive state -0: input -1: output - 2 - 1 - read-only - - - DI_TX - TX state -0: data 0 -1: data 1 - 1 - 1 - read-only - - - DO_TX - TX output -0: data 0 -1: data 1 - 0 - 1 - read-only - - - - - XCVR_STATE - FSM of asynchronous - 0x3c - 32 - 0x00000000 - 0x07070000 - - - RECV_STATE - FSM of asynchronous receive - 24 - 3 - read-only - - - SEND_STATE - FSM of asynchronous transmit - 16 - 3 - read-only - - - - - TRG_IN_CFG - Trigger input configuration - 0x40 - 32 - 0x00000000 - 0x00878787 - - - PRD_EN - Enable period trigger (tigger 2) -0: periodical trigger disabled -1: periodical trigger enabled - 23 - 1 - read-write - - - SYNC_SEL - Synchronize sigal selection (tigger 2) -0: trigger in 0 -1: trigger in 1 -... -7: trigger in 7 - 16 - 3 - read-write - - - IN1_EN - Enable trigger 1 -0: disable trigger 1 -1: enable trigger 1 - 15 - 1 - read-write - - - IN1_SEL - Trigger 1 sigal selection -0: trigger in 0 -1: trigger in 1 -... -7: trigger in 7 - 8 - 3 - read-write - - - IN0_EN - Enable trigger 0 -0: disable trigger 1 -1: enable trigger 1 - 7 - 1 - read-write - - - IN0_SEL - Trigger 0 sigal selection -0: trigger in 0 -1: trigger in 1 -... -7: trigger in 7 - 0 - 3 - read-write - - - - - TRG_SW - Software trigger - 0x44 - 32 - 0x00000000 - 0x00000001 - - - SOFT - Software trigger (tigger 3). this bit is self-clear -0: trigger source disabled -1: trigger source enabled - 0 - 1 - write-only - - - - - TRG_PRD_CFG - Period trigger configuration - 0x48 - 32 - 0x00000000 - 0xFFFF0001 - - - ARMING - Wait for trigger synchronous before trigger -0: Trigger directly -1: Wait trigger source before period trigger - 16 - 1 - read-write - - - SYNC - Synchronous -0: Not synchronous -1: Synchronous every trigger source - 0 - 1 - read-write - - - - - TRG_PRD - Trigger period - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - PERIOD - Trigger period - 0 - 32 - read-write - - - - - TRG_OUT_CFG - Trigger output configuration - 0x50 - 32 - 0x00000000 - 0x87878787 - - - OUT3_EN - Enable trigger 3 -0: disable trigger 3 -1: enable trigger 3 - 31 - 1 - read-write - - - OUT3_SEL - Trigger 3 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 24 - 3 - read-write - - - OUT2_EN - Enable trigger 2 -0: disable trigger 2 -1: enable trigger 2 - 23 - 1 - read-write - - - OUT2_SEL - Trigger 2 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 16 - 3 - read-write - - - OUT1_EN - Enable trigger 1 -0: disable trigger 1 -1: enable trigger 1 - 15 - 1 - read-write - - - OUT1_SEL - Trigger 1 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 8 - 3 - read-write - - - OUT0_EN - Enable trigger 0 -0: disable trigger 1 -1: enable trigger 1 - 7 - 1 - read-write - - - OUT0_SEL - Trigger 0 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 0 - 3 - read-write - - - - - TRG_PRD_STS - Period trigger status - 0x60 - 32 - 0x00000000 - 0x00110000 - - - TRIGERED - Period has been triggered -0: Not triggered -1: Triggered - 20 - 1 - read-only - - - ARMED - Waiting for trigger -0: Not in waiting status -1: In waiting status - 16 - 1 - read-only - - - - - TRG_PRD_CNT - Period trigger counter - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - PERIOD_CNT - Trigger period counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - TRG_TABLE_CMD[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_TRIGGER0 - Trigger command - 0 - 32 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - TRG_TABLE_TIME[%s] - no description available - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRIGGER0_TIME - Trigger time - 0 - 32 - read-only - - - - - CMD_MODE - command register mode - 0xc0 - 32 - 0x00000000 - 0xE0FFCFFF - - - WLEN - word length -0: 1 bit -1: 2 bit -... -31: 32 bit - 16 - 5 - read-write - - - WORDER - word order -0: sample as bit order -1: different from bit order - 11 - 1 - read-write - - - BORDER - bit order -0: LSB first -1: MSB first - 10 - 1 - read-write - - - SIGNED - Signed -0: unsigned value -1: signed value - 9 - 1 - read-write - - - REWIND - Write 1 to rewind read/write pointer, this is a self clear bit - 8 - 1 - write-only - - - MODE - Data mode(CMD register only support data mode) -0: data mode -1: check mode -2: CRC mode - 0 - 2 - read-write - - - - - CMD_IDX - command register configuration - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LAST_BIT - Last bit index for tranceive - 24 - 5 - read-write - - - FIRST_BIT - First bit index for tranceive - 16 - 5 - read-write - - - MAX_BIT - Highest bit index - 8 - 5 - read-write - - - MIN_BIT - Lowest bit index - 0 - 5 - read-write - - - - - CMD_CMD - command - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - DATA - 0 - 32 - read-write - - - - - CMD_SET - command bit set register - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_SET - DATA bit set - 0 - 32 - read-write - - - - - CMD_CLR - command bit clear register - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_CLR - DATA bit clear - 0 - 32 - read-write - - - - - CMD_INV - command bit invert register - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_TGL - DATA bit toggle - 0 - 32 - read-write - - - - - CMD_IN - Commad input - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_IN - Commad input - 0 - 32 - read-only - - - - - CMD_OUT - Command output - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_OUT - Command output - 0 - 32 - read-only - - - - - CMD_STS - Command status - 0xf8 - 32 - 0x00000000 - 0xE0FFFFFF - - - WORD_IDX - Word index - 16 - 5 - read-only - - - WORD_CNT - Word counter - 8 - 5 - read-only - - - BIT_IDX - Bit index - 0 - 5 - read-only - - - - - 8 - 0x20 - 0,1,2,3,4,5,6,7 - CMD_CMD_TABLE[%s] - no description available - 0x100 - - MIN - command start value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_MIN - minimum command value - 0 - 32 - read-write - - - - - MAX - command end value - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_MAX - maximum command value - 0 - 32 - read-write - - - - - MSK - command compare bit enable - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_MASK - compare mask - 0 - 32 - read-write - - - - - PTA - command pointer 0 - 3 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR3 - pointer3 - 24 - 8 - read-write - - - PTR2 - pointer2 - 16 - 8 - read-write - - - PTR1 - pointer1 - 8 - 8 - read-write - - - PTR0 - pointer0 - 0 - 8 - read-write - - - - - PTB - command pointer 4 - 7 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR7 - pointer7 - 24 - 8 - read-write - - - PTR6 - pointer6 - 16 - 8 - read-write - - - PTR5 - pointer5 - 8 - 8 - read-write - - - PTR4 - pointer4 - 0 - 8 - read-write - - - - - - 4 - 0x20 - 0,1,2,3 - CMD_LATCH[%s] - no description available - 0x200 - - 4 - 0x4 - 0_1,1_2,2_3,3_0 - TRAN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF0F3FF7 - - - POINTER - pointer - 24 - 8 - read-write - - - CFG_TM - timeout -0: high -1: low -2: rise -3: fall - 16 - 2 - read-write - - - CFG_TXD - data send -0: high -1: low -2: rise -3: fall - 12 - 2 - read-write - - - CFG_CLK - clock(only support master mode) -0: high -1: low -2: rise -3: fall - 10 - 2 - read-write - - - CFG_PTR - pointer -0: match -1: not match -2:entry -3:leave - 8 - 2 - read-write - - - OV_TM - override timeout check - 4 - 1 - read-write - - - OV_TXD - override TX data check - 2 - 1 - read-write - - - OV_CLK - override clock check - 1 - 1 - read-write - - - OV_PTR - override pointer check - 0 - 1 - read-write - - - - - CFG - Latch configuration - 0x10 - 32 - 0x00000000 - 0x8700FFFF - - - EN - Enable latch -0: disable -1: enable - 31 - 1 - read-write - - - SELECT - Output select -0: state0-state1 -1: state1-state2 -2: state2-state3 -3: state3-state0 - 24 - 3 - read-write - - - DELAY - Delay in system clock cycle, for state transition - 0 - 16 - read-write - - - - - TIME - Latch time - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - LAT_TIME - Latch time - 0 - 32 - read-only - - - - - STS - Latch status - 0x1c - 32 - 0x00000000 - 0x0700FFFF - - - STATE - State - 24 - 3 - read-only - - - LAT_CNT - Latch counter - 0 - 16 - read-only - - - - - - POS_SMP_EN - Sample selection register - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_EN - Position include acceleration -0: use acceleration from sample override acceleration register -1: use acceleration from motor group - 31 - 1 - read-write - - - ACC_SEL - Data register for acceleration transfer - 24 - 5 - read-write - - - SPD_EN - Position include speed -0: use speed from sample override speed register -1: use speed from motor group - 23 - 1 - read-write - - - SPD_SEL - Data register for speed transfer - 16 - 5 - read-write - - - REV_EN - Position include revolution -0: use revolution from sample override revolution register -1: use revolution from motor group - 15 - 1 - read-write - - - REV_SEL - Data register for revolution transfer - 8 - 5 - read-write - - - POS_EN - Position include position -0: use position from sample override position register -1: use position from motor group - 7 - 1 - read-write - - - POS_SEL - Data register for position transfer - 0 - 5 - read-write - - - - - POS_SMP_CFG - Sample configuration - 0x284 - 32 - 0x00000000 - 0x0103FFFF - - - ONCE - Sample one time -0: Sample during windows time -1: Close sample window after first sample - 24 - 1 - read-write - - - LAT_SEL - Latch selection -0: latch 0 -1: latch 1 -2: latch 2 -3: latch 3 - 16 - 2 - read-write - - - WINDOW - Sample window, in clock cycle - 0 - 16 - read-write - - - - - POS_SMP_DAT - Sample data - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT_SEL - Data register sampled, each bit represent a data register - 0 - 32 - read-write - - - - - POS_SMP_POS - Sample override position - 0x290 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS - Sample override position - 0 - 32 - read-write - - - - - POS_SMP_REV - Sample override revolution - 0x294 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - Sample override revolution - 0 - 32 - read-write - - - - - POS_SMP_SPD - Sample override speed - 0x298 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPD - Sample override speed - 0 - 32 - read-write - - - - - POS_SMP_ACC - Sample override accelerate - 0x29c - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - Sample override accelerate - 0 - 32 - read-write - - - - - POS_UPD_EN - Update configuration - 0x2a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_EN - Position include acceleration -0: use acceleration from update override acceleration register -1: use acceleration from data register - 31 - 1 - read-write - - - ACC_SEL - Data register for acceleration transfer - 24 - 5 - read-write - - - SPD_EN - Position include speed -0: use speed from update override speed register -1: use speed from data register - 23 - 1 - read-write - - - SPD_SEL - Data register for speed transfer - 16 - 5 - read-write - - - REV_EN - Position include revolution -0: use revolution from update override revolution register -1: use revolution from data register - 15 - 1 - read-write - - - REV_SEL - Data register for revolution transfer - 8 - 5 - read-write - - - POS_EN - Position include position -0: use position from update override position register -1: use position from data register - 7 - 1 - read-write - - - POS_SEL - Data register for position transfer - 0 - 5 - read-write - - - - - POS_UPD_CFG - Update configuration - 0x2a4 - 32 - 0x00000000 - 0x81030000 - - - TIME_OVRD - Use override time -0: use time sample from motor group -1: use override time - 31 - 1 - read-write - - - ONERR - Sample one time -0: Sample during windows time -1: Close sample window after first sample - 24 - 1 - read-write - - - LAT_SEL - Latch selection -0: latch 0 -1: latch 1 -2: latch 2 -3: latch 3 - 16 - 2 - read-write - - - - - POS_UPD_DAT - Update data - 0x2a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT_SEL - Data register sampled, each bit represent a data register - 0 - 32 - read-write - - - - - POS_UPD_TIME - Update overide time - 0x2ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - Update override time - 0 - 32 - read-write - - - - - POS_UPD_POS - Update override position - 0x2b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS - Update override position - 0 - 32 - read-write - - - - - POS_UPD_REV - Update override revolution - 0x2b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - Update override revolution - 0 - 32 - read-write - - - - - POS_UPD_SPD - Update override speed - 0x2b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPD - Update override speed - 0 - 32 - read-write - - - - - POS_UPD_ACC - Update override accelerate - 0x2bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - Update override accelerate - 0 - 32 - read-write - - - - - POS_SMP_VAL - Sample valid - 0x2c0 - 32 - 0x00000000 - 0x80808080 - - - ACC - Position include acceleration - 31 - 1 - read-only - - - SPD - Position include speed - 23 - 1 - read-only - - - REV - Position include revolution - 15 - 1 - read-only - - - POS - Position include position - 7 - 1 - read-only - - - - - POS_SMP_STS - Sample status - 0x2c4 - 32 - 0x00000000 - 0x0100FFFF - - - OCCUR - Sample occured -0: Sample not happened -1: Sample occured - 24 - 1 - read-only - - - WIN_CNT - Sample window counter - 0 - 16 - read-only - - - - - POS_TIME_IN - input time - 0x2cc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - input time - 0 - 32 - read-only - - - - - POS_POS_IN - Input position - 0x2d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS - Input position - 0 - 32 - read-only - - - - - POS_REV_IN - Input revolution - 0x2d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - Input revolution - 0 - 32 - read-only - - - - - POS_SPD_IN - Input speed - 0x2d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPD - Input speed - 0 - 32 - read-only - - - - - POS_ACC_IN - Input accelerate - 0x2dc - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - Input accelerate - 0 - 32 - read-only - - - - - POS_UPD_STS - Update status - 0x2e4 - 32 - 0x00000000 - 0x01000000 - - - UPD_ERR - Update error -0: data receive normally -1: data receive error - 24 - 1 - read-only - - - - - IRQ_INT_EN - Interrupt Enable - 0x300 - 32 - 0x00000000 - 0xFF1F3FF7 - - - TRG_ERR3 - Trigger3 failed - 31 - 1 - read-write - - - TRG_ERR2 - Trigger2 failed - 30 - 1 - read-write - - - TRG_ERR1 - Trigger1 failed - 29 - 1 - read-write - - - TRG_ERR0 - Trigger0 failed - 28 - 1 - read-write - - - TRIGER3 - Trigger3 - 27 - 1 - read-write - - - TRIGER2 - Trigger2 - 26 - 1 - read-write - - - TRIGER1 - Trigger1 - 25 - 1 - read-write - - - TRIGER0 - Trigger0 - 24 - 1 - read-write - - - SMP_ERR - Sample error - 20 - 1 - read-write - - - LATCH3 - Latch3 - 19 - 1 - read-write - - - LATCH2 - Latch2 - 18 - 1 - read-write - - - LATCH1 - Latch1 - 17 - 1 - read-write - - - LATCH0 - Latch0 - 16 - 1 - read-write - - - TIMEOUT - Timeout - 13 - 1 - read-write - - - TRX_ERR - Transfer error - 12 - 1 - read-write - - - INSTR1_END - Instruction 1 end - 11 - 1 - read-write - - - INSTR0_END - Instruction 0 end - 10 - 1 - read-write - - - PTR1_END - Pointer 1 end - 9 - 1 - read-write - - - PTR0_END - Pointer 0 end - 8 - 1 - read-write - - - INSTR1_ST - Instruction 1 start - 7 - 1 - read-write - - - INSTR0_ST - Instruction 0 start - 6 - 1 - read-write - - - PTR1_ST - Pointer 1 start - 5 - 1 - read-write - - - PTR0_ST - Pointer 0 start - 4 - 1 - read-write - - - WDOG - Watch dog - 2 - 1 - read-write - - - EXCEPT - Exception - 1 - 1 - read-write - - - STALL - Stall - 0 - 1 - read-write - - - - - IRQ_INT_FLAG - Interrupt flag - 0x304 - 32 - 0x00000000 - 0xFF1F3FF7 - - - TRG_ERR3 - Trigger3 failed - 31 - 1 - write-only - - - TRG_ERR2 - Trigger2 failed - 30 - 1 - write-only - - - TRG_ERR1 - Trigger1 failed - 29 - 1 - write-only - - - TRG_ERR0 - Trigger0 failed - 28 - 1 - write-only - - - TRIGER3 - Trigger3 - 27 - 1 - write-only - - - TRIGER2 - Trigger2 - 26 - 1 - write-only - - - TRIGER1 - Trigger1 - 25 - 1 - write-only - - - TRIGER0 - Trigger0 - 24 - 1 - write-only - - - SMP_ERR - Sample error - 20 - 1 - write-only - - - LATCH3 - Latch3 - 19 - 1 - write-only - - - LATCH2 - Latch2 - 18 - 1 - write-only - - - LATCH1 - Latch1 - 17 - 1 - write-only - - - LATCH0 - Latch0 - 16 - 1 - write-only - - - TIMEOUT - Timeout - 13 - 1 - write-only - - - TRX_ERR - Transfer error - 12 - 1 - write-only - - - INSTR1_END - Instruction 1 end - 11 - 1 - write-only - - - INSTR0_END - Instruction 0 end - 10 - 1 - write-only - - - PTR1_END - Pointer 1 end - 9 - 1 - write-only - - - PTR0_END - Pointer 0 end - 8 - 1 - write-only - - - INSTR1_ST - Instruction 1 start - 7 - 1 - write-only - - - INSTR0_ST - Instruction 0 start - 6 - 1 - write-only - - - PTR1_ST - Pointer 1 start - 5 - 1 - write-only - - - PTR0_ST - Pointer 0 start - 4 - 1 - write-only - - - WDOG - Watch dog - 2 - 1 - write-only - - - EXCEPT - Exception - 1 - 1 - write-only - - - STALL - Stall - 0 - 1 - write-only - - - - - IRQ_INT_STS - Interrupt status - 0x308 - 32 - 0x00000000 - 0xFF1F3FF7 - - - TRG_ERR3 - Trigger3 failed - 31 - 1 - read-only - - - TRG_ERR2 - Trigger2 failed - 30 - 1 - read-only - - - TRG_ERR1 - Trigger1 failed - 29 - 1 - read-only - - - TRG_ERR0 - Trigger0 failed - 28 - 1 - read-only - - - TRIGER3 - Trigger3 - 27 - 1 - read-only - - - TRIGER2 - Trigger2 - 26 - 1 - read-only - - - TRIGER1 - Trigger1 - 25 - 1 - read-only - - - TRIGER0 - Trigger0 - 24 - 1 - read-only - - - SMP_ERR - Sample error - 20 - 1 - read-only - - - LATCH3 - Latch3 - 19 - 1 - read-only - - - LATCH2 - Latch2 - 18 - 1 - read-only - - - LATCH1 - Latch1 - 17 - 1 - read-only - - - LATCH0 - Latch0 - 16 - 1 - read-only - - - TIMEOUT - Timeout - 13 - 1 - read-only - - - TRX_ERR - Transfer error - 12 - 1 - read-only - - - INSTR1_END - Instruction 1 end - 11 - 1 - read-only - - - INSTR0_END - Instruction 0 end - 10 - 1 - read-only - - - PTR1_END - Pointer 1 end - 9 - 1 - read-only - - - PTR0_END - Pointer 0 end - 8 - 1 - read-only - - - INSTR1_ST - Instruction 1 start - 7 - 1 - read-only - - - INSTR0_ST - Instruction 0 start - 6 - 1 - read-only - - - PTR1_ST - Pointer 1 start - 5 - 1 - read-only - - - PTR0_ST - Pointer 0 start - 4 - 1 - read-only - - - WDOG - Watch dog - 2 - 1 - read-only - - - EXCEPT - Exception - 1 - 1 - read-only - - - STALL - Stall - 0 - 1 - read-only - - - - - IRQ_POINTER0 - Match pointer 0 - 0x310 - 32 - 0x00000000 - 0x000000FF - - - POINTER - Match pointer 0 - 0 - 8 - read-write - - - - - IRQ_POINTER1 - Match pointer 1 - 0x314 - 32 - 0x00000000 - 0x000000FF - - - POINTER - Match pointer 1 - 0 - 8 - read-write - - - - - IRQ_INSTR0 - Match instruction 0 - 0x318 - 32 - 0x00000000 - 0xFFFFFFFF - - - INSTR - Match instruction 0 - 0 - 32 - read-write - - - - - IRQ_INSTR1 - Match instruction 1 - 0x31c - 32 - 0x00000000 - 0xFFFFFFFF - - - INSTR - Match instruction 1 - 0 - 32 - read-write - - - - - - 64 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 - INSTR[%s] - no description available - 0x3400 - 32 - 0x00000000 - 0xFFFFFFFF - - - OP - operation -0: halt -1: jump -2: send with timeout check -3: send without timout check -4: wait with timeout check -5: wait without timout check -6: receive with timeout check -7: receive without timout check - 26 - 3 - read-write - - - CK - clock -0: low -1: rise-fall -2: fall-rise -3: high - 24 - 2 - read-write - - - CRC - CRC register -0: don't calculate CRC -1: do not set this value -2: data register 2 -3: data register 3 -... -29: data register 29 -30: value 0 when send, wait 0 in receive -31: value1 when send, wait 1 in receive - 16 - 5 - read-write - - - DAT - DATA register -0: ignore data -1: command -2: data register 2 -3: data register 3 -... -29: data register 29 -30: value 0 when send, wait 0 in receive -31: value1 when send, wait 1 in receive - 8 - 5 - read-write - - - OPR - [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. -[2] When OP is 1, this area is the the pointer to the command table. -OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; -OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; -OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. -[3] When OP is 2-7, this area is the data length as fellow: -0: 1 bit -1: 2 bit - ... -31: 32 bit - 0 - 5 - read-write - - - - - 10 - 0x40 - 0,1,2,3,4,5,6,7,8,9 - DAT[%s] - no description available - 0x3800 - - MODE - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_LEN - CRC length -0: 1 bit -1: 2 bit -... -31: 32 bit - 24 - 5 - read-write - - - WLEN - word length -0: 1 bit -1: 2 bit -... -31: 32 bit - 16 - 5 - read-write - - - CRC_SHIFT - CRC shift mode, this mode is used to perform repeat code check -0: CRC -1: shift mode - 13 - 1 - read-write - - - CRC_INV - CRC invert -0: use CRC -1: use inverted CRC - 12 - 1 - read-write - - - WORDER - word order -0: sample as bit order -1: different from bit order - 11 - 1 - read-write - - - BORDER - bit order -0: LSB first -1: MSB first - 10 - 1 - read-write - - - SIGNED - Signed -0: unsigned value -1: signed value - 9 - 1 - read-write - - - REWIND - Write 1 to rewind read/write pointer, this is a self clear bit - 8 - 1 - read-write - - - MODE - Data mode -0: data mode -1: check mode -2: CRC mode - 0 - 2 - read-write - - - - - IDX - Data register bit index - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LAST_BIT - Last bit index for tranceive - 24 - 5 - read-write - - - FIRST_BIT - First bit index for tranceive - 16 - 5 - read-write - - - MAX_BIT - Highest bit index - 8 - 5 - read-write - - - MIN_BIT - Lowest bit index - 0 - 5 - read-write - - - - - GOLD - Gold data for data check - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GOLD_VALUE - Gold value for check mode - 0 - 32 - read-write - - - - - CRCINIT - CRC calculation initial vector - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_INIT - CRC initial value - 0 - 32 - read-write - - - - - CRCPOLY - CRC calculation polynomial - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_POLY - CRC polymonial - 0 - 32 - read-write - - - - - DATA - Data value - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - DATA - 0 - 32 - read-write - - - - - SET - Data bit set - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_SET - DATA bit set - 0 - 32 - read-write - - - - - CLR - Data bit clear - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_CLR - DATA bit clear - 0 - 32 - read-write - - - - - INV - Data bit invert - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_INV - DATA bit toggle - 0 - 32 - read-write - - - - - IN - Data input - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_IN - Data input - 0 - 32 - read-only - - - - - OUT - Data output - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_OUT - Data output - 0 - 32 - read-only - - - - - STS - Data status - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_IDX - CRC index - 24 - 5 - read-only - - - WORD_IDX - Word index - 16 - 5 - read-only - - - WORD_CNT - Word counter - 8 - 5 - read-only - - - BIT_IDX - Bit index - 0 - 5 - read-only - - - - - - - - TRGM0 - TRGM0 - TRGM - 0xf033c000 - - 0x0 - 0x634 - registers - - - - 28 - 0x4 - PWM0_IN0,PWM0_IN1,PWM0_IN2,PWM0_IN3,PWM0_IN4,PWM0_IN5,PWM0_IN6,PWM0_IN7,PWM1_IN0,PWM1_IN1,PWM1_IN2,PWM1_IN3,PWM1_IN4,PWM1_IN5,PWM1_IN6,PWM1_IN7,MOTO_GPIO_IN0,MOTO_GPIO_IN1,MOTO_GPIO_IN2,MOTO_GPIO_IN3,MOTO_GPIO_IN4,MOTO_GPIO_IN5,MOTO_GPIO_IN6,MOTO_GPIO_IN7,PWM0_FAULT0,PWM0_FAULT1,PWM1_FAULT0,PWM1_FAULT1 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN_SHIFT - No description available - 9 - 3 - read-write - - - FILTLEN_BASE - This bitfields defines the filter counter length. - 0 - 9 - read-write - - - - - 137 - 0x4 - MOT2OPAMP0_0,MOT2OPAMP0_1,MOT2OPAMP0_2,MOT2OPAMP0_3,MOT2OPAMP0_4,MOT2OPAMP0_5,MOT2OPAMP0_6,MOT2OPAMP0_7,MOT2OPAMP1_0,MOT2OPAMP1_1,MOT2OPAMP1_2,MOT2OPAMP1_3,MOT2OPAMP1_4,MOT2OPAMP1_5,MOT2OPAMP1_6,MOT2OPAMP1_7,GPTMR0_IN2,GPTMR0_IN3,GPTMR0_SYNCI,GPTMR1_IN2,GPTMR1_IN3,GPTMR1_SYNCI,GPTMR2_IN2,GPTMR2_IN3,GPTMR2_SYNCI,GPTMR3_IN2,GPTMR3_IN3,GPTMR3_SYNCI,CMP0_WIN,CMP1_WIN,DAC0_BUFTRG,DAC1_BUFTRG,ADC0_STRGI,ADC1_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,ADCx_PTRGI1A,ADCx_PTRGI1B,ADCx_PTRGI1C,ADCx_PTRGI2A,ADCx_PTRGI2B,ADCx_PTRGI2C,ADCx_PTRGI3A,ADCx_PTRGI3B,ADCx_PTRGI3C,CAN_PTPC0_CAP,CAN_PTPC1_CAP,QEO0_TRIG_IN0,QEO0_TRIG_IN1,QEO1_TRIG_IN0,QEO1_TRIG_IN1,SEI_TRIG_IN0,SEI_TRIG_IN1,SEI_TRIG_IN2,SEI_TRIG_IN3,SEI_TRIG_IN4,SEI_TRIG_IN5,SEI_TRIG_IN6,SEI_TRIG_IN7,MMC0_TRIG_IN0,MMC0_TRIG_IN1,MMC1_TRIG_IN0,MMC1_TRIG_IN1,PLB_IN_00,PLB_IN_01,PLB_IN_02,PLB_IN_03,PLB_IN_04,PLB_IN_05,PLB_IN_06,PLB_IN_07,PLB_IN_08,PLB_IN_09,PLB_IN_10,PLB_IN_11,PLB_IN_12,PLB_IN_13,PLB_IN_14,PLB_IN_15,PLB_IN_16,PLB_IN_17,PLB_IN_18,PLB_IN_19,PLB_IN_20,PLB_IN_21,PLB_IN_22,PLB_IN_23,PLB_IN_24,PLB_IN_25,PLB_IN_26,PLB_IN_27,PLB_IN_28,PLB_IN_29,PLB_IN_30,PLB_IN_31,MOT_GPIO0,MOT_GPIO1,MOT_GPIO2,MOT_GPIO3,MOT_GPIO4,MOT_GPIO5,MOT_GPIO6,MOT_GPIO7,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM0_FRCI,PWM0_FRCSYNCI,PWM0_SYNCI,PWM0_SHRLDSYNCI,PWM0_FAULTI0,PWM0_FAULTI1,PWM1_FRCI,PWM1_FRCSYNCI,PWM1_SYNCI,PWM1_SHRLDSYNCI,PWM1_FAULTI0,PWM1_FAULTI1,RDC_TRIG_IN0,RDC_TRIG_IN1,SYNCTIMER_TRIG,QEI0_TRIG_IN,QEI1_TRIG_IN,QEI0_PAUSE,QEI1_PAUSE,UART_TRIG0,UART_TRIG1,TRGM_IRQ0,TRGM_IRQ1,TRGM_DMA0,TRGM_DMA1 - TRGOCFG[%s] - no description available - 0x100 - 32 - 0x00000000 - 0x00000E7F - - - OUTINV - 1- Invert the output - 11 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 10 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 9 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 7 - read-write - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DMACFG[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x8000003F - - - DMAMUX_EN - No description available - 31 - 1 - read-write - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 6 - read-write - - - - - GCR - General Control Register - 0x500 - 32 - 0x00000000 - 0x000000FF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 8 - read-write - - - - - ADC_MATRIX_SEL - adc matrix select register - 0x510 - 32 - 0x00000000 - 0xFFFFFFFF - - - QEI1_ADC1_SEL - 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; -bit7 is used to invert adc_value; -others reserved - 24 - 8 - read-write - - - QEI1_ADC0_SEL - No description available - 16 - 8 - read-write - - - QEI0_ADC1_SEL - No description available - 8 - 8 - read-write - - - QEI0_ADC0_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL - dac matrix select register - 0x514 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAC1_DAC_SEL - 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; -3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; -6-rdc_dac0; 7-rdc_dac1; -bit7 is used to invert dac_value; -others reserved - 24 - 8 - read-write - - - DAC0_DAC_SEL - No description available - 16 - 8 - read-write - - - ACMP1_DAC_SEL - No description available - 8 - 8 - read-write - - - ACMP0_DAC_SEL - No description available - 0 - 8 - read-write - - - - - POS_MATRIX_SEL0 - position matrix select register0 - 0x518 - 32 - 0x00000000 - 0xFFFFFFFF - - - MMC1_POSIN_SEL - 0-sei_pos_out0; 1-sei_pos_out1; -2-qei0_pos; 3-qei1_pos; -4-mmc0_pos_out0; 5-mmc0_pos_out1; -6-mmc1_pos_out0; 7-mmc1_pos_out1; -bit7 is used to invert position value; - others reserved - 24 - 8 - read-write - - - MMC0_POSIN_SEL - No description available - 16 - 8 - read-write - - - SEI_POSIN1_SEL - No description available - 8 - 8 - read-write - - - SEI_POSIN0_SEL - No description available - 0 - 8 - read-write - - - - - POS_MATRIX_SEL1 - position matrix select register1 - 0x51c - 32 - 0x00000000 - 0x0000FFFF - - - QEO1_POS_SEL - No description available - 8 - 8 - read-write - - - QEO0_POS_SEL - No description available - 0 - 8 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - TRGM_IN[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGM_IN - mmc1_trig_out[1:0], mmc0_trig_out[1:0],sync_pulse[3:0],moto_gpio_in_sync[7:0],//31:16 - gtmr3_to_motor_sync[1:0],gtmr2_to_motor_sync[1:0],gtmr1_to_motor_sync[1:0],gtmr0_to_motor_sync[1:0], //15:8 - acmp_out_sync[1:0],can2mot_event_sync[1:0],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0 - 0 - 32 - read-only - - - - - 5 - 0x4 - 0,1,2,3,4 - TRGM_OUT[%s] - no description available - 0x620 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGM_OUT - motor_to_opamp0[7:0] = trig_mux_out[7:0]; -motor_to_opamp1[7:0] = trig_mux_out[15:8]; -motor_to_gtmr0_capt[1:0] = trig_mux_out[17:16]; -motor_to_gtmr0_sync = trig_mux_out[18]; -motor_to_gtmr1_capt[1:0] = trig_mux_out[20:19]; -motor_to_gtmr1_sync = trig_mux_out[21]; -motor_to_gtmr2_capt[1:0] = trig_mux_out[23:22]; -motor_to_gtmr2_sync = trig_mux_out[24]; -motor_to_gtmr3_capt[1:0] = trig_mux_out[26:25]; -motor_to_gtmr3_sync = trig_mux_out[27]; -acmp_window[1:0] = trig_mux_out[29:28]; -dac0_buf_trigger = trig_mux_out[30]; -dac1_buf_trigger = trig_mux_out[31]; -dac0_step_trigger[3:0] = {trig_mux_out[24:22],trig_mux_out[30]};//use same buf_trig, and gtmr2 -dac1_step_trigger[3:0] = {trig_mux_out[27:25],trig_mux_out[31]}; //use same buf_trig, and gtmr3 - 0 - 32 - read-only - - - - - - - USB0 - USB0 - USB - 0xf300c000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFFB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - PRM - Asynchronous Schedule start- Write only， host mode only。 -this bit is used to notify hostcontroller to start async schedule immediately. - 12 - 1 - write-only - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 16 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - SDP - SDP - SDP - 0xf3040000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - SEC - SEC - SEC - 0xf3044000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - MON - MON - MON - 0xf3048000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - RNG - RNG - RNG - 0xf304c000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - OTP - OTP - OTP - 0xf3050000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - KEYM - KEYM - KEYM - 0xf3054000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - ADC0 - ADC0 - ADC16 - 0xf3080000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000003 - - - BUS_MODE_EN - bus mode enable - 1 - 1 - read-write - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - seq_high_cfg - No description available - 0x850 - 32 - 0x00000000 - 0x00FFFFFF - - - STOP_POS_HIGH - No description available - 12 - 12 - read-write - - - BUF_LEN_HIGH - No description available - 0 - 12 - read-write - - - - - 16 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x80001004 - - - MOTO_EN - "set to enable moto_soc and moto_valid. -Should use AHB clock for adc, this bit can be used avoid async output" - 31 - 1 - read-write - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x01F07FFF - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ADC1 - ADC1 - ADC16 - 0xf3084000 - - - DAC0 - DAC0 - DAC - 0xf3090000 - - 0x0 - 0x4c - registers - - - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - write-only - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - write-only - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - write-only - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - write-only - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - write-only - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; -11: trigger mode, DAC output from external trigger signals -Note: -Trigger mode is not supported in hpm63xx and hpm62xx families. - 4 - 2 - write-only - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - write-only - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - write-only - - - - - cfg1 - No description available - 0x4 - 32 - 0x00010000 - 0x0007FFFF - - - ANA_CLK_EN - set to enable analog clock(divided by ana_div_cfg) -need to be set in direct mode and trigger mode - 18 - 1 - read-write - - - ANA_DIV_CFG - clock divider config for ana_clk to dac analog; -00: div2 -01: div4 -10: div6 -11: div8 - 16 - 2 - read-write - - - DIV_CFG - step mode and buffer mode: - defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. -Direct mode and trigger mode: - defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. -Note: -For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. - 0 - 16 - read-write - - - - - cfg2 - No description available - 0x8 - 32 - 0x00000000 - 0x000000FF - - - DMA_RST1 - set to reset dma read pointer to buf1_start_addr; -if set both dma_rst0&dma_rst1, will set to buf0_start_addr -user can set fifo_clr bit when use dma_rst* - 7 - 1 - write-only - - - DMA_RST0 - set to reset dma read pointer to buf0_start_addr - 6 - 1 - write-only - - - FIFO_CLR - set to clear FIFO content(set both read/write pointer to 0) - 5 - 1 - write-only - - - BUF_SW_TRIG - software trigger for buffer mode, -W1C in single mode. -RW in continual mode - 4 - 1 - read-write - - - STEP_SW_TRIG3 - No description available - 3 - 1 - read-write - - - STEP_SW_TRIG2 - No description available - 2 - 1 - read-write - - - STEP_SW_TRIG1 - No description available - 1 - 1 - read-write - - - STEP_SW_TRIG0 - software trigger0 for step mode, -W1C in single mode. -RW in continual mode - 0 - 1 - read-write - - - - - 4 - 0x4 - step0,step1,step2,step3 - STEP_CFG[%s] - no description available - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description available - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description available - 0 - 12 - read-write - - - - - 2 - 0x4 - buf0,buf1 - BUF_ADDR[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFD - - - BUF_START_ADDR - buffer start address, should be 4-byte aligned -AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - 2 - 30 - read-write - - - BUF_STOP - set to stop read point at end of bufffer0 - 0 - 1 - read-write - - - - - buf_length - No description available - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF1_LEN - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - 16 - 16 - read-write - - - BUF0_LEN - No description available - 0 - 16 - read-write - - - - - irq_sts - No description available - 0x30 - 32 - 0x00000000 - 0x0000001F - - - STEP_CMPT - No description available - 4 - 1 - write-only - - - AHB_ERROR - set if hresp==2'b01(ERROR) - 3 - 1 - write-only - - - FIFO_EMPTY - No description available - 2 - 1 - write-only - - - BUF1_CMPT - No description available - 1 - 1 - write-only - - - BUF0_CMPT - No description available - 0 - 1 - write-only - - - - - irq_en - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - STEP_CMPT - No description available - 4 - 1 - read-write - - - AHB_ERROR - No description available - 3 - 1 - read-write - - - FIFO_EMPTY - No description available - 2 - 1 - read-write - - - BUF1_CMPT - No description available - 1 - 1 - read-write - - - BUF0_CMPT - No description available - 0 - 1 - read-write - - - - - dma_en - No description available - 0x38 - 32 - 0x00000000 - 0x00000013 - - - STEP_CMPT - No description available - 4 - 1 - read-write - - - BUF1_CMPT - No description available - 1 - 1 - read-write - - - BUF0_CMPT - No description available - 0 - 1 - read-write - - - - - ana_cfg0 - No description available - 0x40 - 32 - 0x00000030 - 0x000001FF - - - DAC12BIT_LP_MODE - No description available - 8 - 1 - read-write - - - DAC_CONFIG - No description available - 4 - 4 - read-write - - - CALI_DELTA_V_CFG - No description available - 2 - 2 - read-write - - - BYPASS_CALI_GM - No description available - 1 - 1 - read-write - - - DAC12BIT_EN - No description available - 0 - 1 - read-write - - - - - cfg0_bak - No description available - 0x44 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - read-write - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - read-write - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - read-write - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - read-write - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - read-write - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - 4 - 2 - read-write - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - read-write - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - read-write - - - - - status0 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFF80 - - - CUR_BUF_OFFSET - No description available - 8 - 16 - read-write - - - CUR_BUF_INDEX - No description available - 7 - 1 - read-write - - - - - - - DAC1 - DAC1 - DAC - 0xf3094000 - - - OPAMP0 - OPAMP0 - OPAMP - 0xf30a0000 - - 0x0 - 0x90 - registers - - - - ctrl0 - control reg - 0x0 - 32 - 0x00000000 - 0x0407FFFF - - - EN_LV - No description available - 26 - 1 - read-write - - - VIM_SEL - No description available - 16 - 3 - read-write - - - MODE - No description available - 11 - 5 - read-write - - - GAIN_SEL - No description available - 8 - 3 - read-write - - - DISABLE_PM_CAP - No description available - 7 - 1 - read-write - - - MILLER_SEL - No description available - 4 - 3 - read-write - - - VBYPASS - No description available - 3 - 1 - read-write - - - VIP_SEL - No description available - 0 - 3 - read-write - - - - - status - status reg - 0x4 - 32 - 0x00000000 - 0x0FFF0000 - - - TRIG_CONFLICT - if more than one hardware trigger is set, will put all trigger input here; -write any value to clear - 20 - 8 - read-write - - - PRESET_ACT - 1 for preset active; one of cur_preset is selected for OPAMP; -0 for no preset, OPAMP use cfg0 parameters - 19 - 1 - read-only - - - CUR_PRESET - current selected preset - 16 - 3 - read-only - - - - - ctrl1 - control reg1 - 0x8 - 32 - 0x00000000 - 0x80000007 - - - SW_PRESET - set to use preset defined by sw_sel. -NOTE: when set, the hardware trigger will not be used - 31 - 1 - read-write - - - SW_SEL - No description available - 0 - 3 - read-write - - - - - 8 - 0x10 - preset0,preset1,preset2,preset3,preset4,preset5,preset6,preset7 - CFG[%s] - no description available - 0x10 - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x0F000707 - - - DISABLE_PM_CAP - No description available - 27 - 1 - read-write - - - MILLER_SEL - No description available - 24 - 3 - read-write - - - VIM_SEL - No description available - 8 - 3 - read-write - - - VIP_SEL - No description available - 0 - 3 - read-write - - - - - cfg1 - No description available - 0x4 - 32 - 0x00000000 - 0xE00000FF - - - HW_TRIG_EN - set to enable hardware trigger from moto system. -NOTE: when sw_preset is enabled, this bit will not take effert - 31 - 1 - read-write - - - EN_LV - No description available - 30 - 1 - read-write - - - VBYPASS_LV - No description available - 29 - 1 - read-write - - - MODE - No description available - 3 - 5 - read-write - - - GAIN_SEL - No description available - 0 - 3 - read-write - - - - - cfg2 - No description available - 0x8 - 32 - 0x00000000 - 0x07000000 - - - CHANNEL - No description available - 24 - 3 - read-write - - - - - - - - OPAMP1 - OPAMP1 - OPAMP - 0xf30a4000 - - - ACMP - ACMP - ACMP - 0xf30b0000 - - 0x0 - 0x40 - registers - - - - 2 - 0x20 - chn0,chn1 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - DAC_TRIG_EN - if set, the dac value is from moto system when valid -if clr, use dac_cfg value - 23 - 1 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x2c00 - registers - - - - 105 - 0x4 - cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_clk3_pll1,clk_src_pll0_ref,clk_src_pll1_ref,rsv44,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv70,rsv71,rsv72,rsv73,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1,clk_top_adc0,clk_top_adc1,clk_top_dac0,clk_top_dac1,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahb0,lmm0,mct0,rom0,can0,can1,can2,can3,ptpc,rsv265,rsv266,rsv267,rsv268,tmr0,tmr1,tmr2,tmr3,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,tsns,crc0,adc0,adc1,dac0,dac1,acmp,opa0,opa1,mot0,rng0,sdp0,kman,gpio,hdma,xpi0,usb0,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 2 - 0x10 - link0,link1 - GROUP0[%s] - no description available - 0x800 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 1 - 0x10 - cpu0 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - - 1 - 0x10 - cpu0 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu0 stop -bit01: soc_ctx is kept on while cpu0 stop -bit02: cpu0_mem is kept on while cpu0 stop -bit03: cpu0_ctx is kept on while cpu0 stop -bit04: xtal_hold is kept on while cpu0 stop -bit05: pll0_hold is kept on while cpu0 stop -bit06: pll1_hold is kept on while cpu0 stop - 0 - 15 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 15 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 15 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 15 - read-write - - - - - - 1 - 0x14 - cpu0 - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0031100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - MEM_RET_N - memory info retention control signal -0: memory enter retention mode -1: memory exit retention mode - 17 - 1 - read-only - - - MEM_RET_P - memory info retention control signal -0: memory not enterexitretention mode -1: memory enter retention mode - 16 - 1 - read-only - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x000000FF - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x0000000F - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - ret_wait - Power Setting - 0x10 - 32 - 0x0000000F - 0x000FFFFF - - - WAIT - wait time for memory retention mode transition, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 2 - 0x10 - soc,cpu0 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00402003 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 1 - 0x4 - clk_top_cpu0 - CLOCK_CPU[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xD00F07FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - SUB0_DIV - ahb bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 16 - 4 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll1_clk2 -7:pll1_clk3 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 32 - 0x4 - clk_top_mct0,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,rsv5,rsv6,rsv7,rsv8,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_xpi0,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ref0,clk_top_ref1 - CLOCK[%s] - no description available - 0x1804 - 32 - 0x00000000 - 0xD00007FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll1_clk2 -7:pll1_clk3 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 2 - 0x4 - clk_top_adc0,clk_top_adc1 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ahb0 clock -1: ana clock N - 8 - 1 - read-write - - - - - 2 - 0x4 - clk_top_dac0,clk_top_dac1 - DACCLK[%s] - no description available - 0x1c08 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ahb0 clock -1: ana clock N - 8 - 1 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x000000FF - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 -bit4: override to preset4 -bit5: override to preset5 -bit6: override to preset6 -bit7: override to preset7 - 0 - 8 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 1 - 0x400 - cpu0 - CPU[%s] - no description available - 0x2800 - - LP - CPU0 LP control - 0x0 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - CPU0 Lock GPR - 0x4 - 32 - 0x00000000 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 4 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 4 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xe40 - registers - - - - 456 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,rsv64,rsv65,rsv66,rsv67,rsv68,rsv69,rsv70,rsv71,rsv72,rsv73,rsv74,rsv75,rsv76,rsv77,rsv78,rsv79,rsv80,rsv81,rsv82,rsv83,rsv84,rsv85,rsv86,rsv87,rsv88,rsv89,rsv90,rsv91,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -... -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf4118000 - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf40c0000 - - 0x0 - 0x180 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 2 - 0x80 - pll0,pll1 - PLL[%s] - no description available - 0x80 - - MFI - PLL0 multiple register - 0x0 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - MFN - PLL0 fraction numerator register - 0x4 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - MFD - PLL0 fraction demoninator register - 0x8 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - SS_STEP - PLL0 spread spectrum step register - 0xc - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - SS_STOP - PLL0 spread spectrum stop register - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - CONFIG - PLL0 confguration register - 0x14 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - LOCKTIME - PLL0 lock time register - 0x18 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - STEPTIME - PLL0 step time register - 0x1c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - ADVANCED - PLL0 advance configuration register - 0x20 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - 3 - 0x4 - DIV0,DIV1,DIV2 - DIV[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - - PPOR - PPOR - PPOR - 0xf4100000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-only - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HOLD - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_TYPE - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf4104000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x801F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x0001047E - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: trun off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00000384 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000010 - 0x11018191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - ouput over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x03120040 - 0x073F007F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_AUTOLP - enable auto enter low power mode -0: do not enter low power mode -1: enter low power mode if current is detected low - 4 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00006E1C - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit31: pin wakeup - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit31: pin wakeup - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart - 0 - 32 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000310 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PGPR0 - PGPR0 - PGPR - 0xf4110000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PGPR1 - PGPR1 - PGPR - 0xf4114000 - - - PDGO - PDGO - PDGO - 0xf4134000 - - 0x0 - 0x714 - registers - - - - DGO_TURNOFF - trunoff control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. - 0 - 32 - write-only - - - - - DGO_RC32K_CFG - RC32K CLOCK - 0x4 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - DGO_GPR00 - Generic control 0 - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR01 - Generic control 1 - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR02 - Generic control 2 - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR03 - Generic control 3 - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_CTR0 - control register 0 - 0x700 - 32 - 0x00000000 - 0x00010000 - - - RETENTION - dgo register status retenion - 16 - 1 - read-write - - - - - DGO_CTR1 - control register 1 - 0x704 - 32 - 0x00000000 - 0x80010001 - - - AOTO_SYS_WAKEUP - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously - 31 - 1 - read-write - - - WAKEUP_EN - permit wakeup pin or software wakeup - 16 - 1 - read-write - - - PIN_WAKEUP_STATUS - wakeup pin status - 0 - 1 - read-only - - - - - DGO_CTR2 - control register 2 - 0x708 - 32 - 0x00000000 - 0x01010000 - - - RESETN_PULLUP_DISABLE - resetn pin pull up disable - 24 - 1 - read-write - - - WAKEUP_PULLDN_DISABLE - wakeup pin pull down disable - 16 - 1 - read-write - - - - - DGO_CTR3 - control register 3 - 0x70c - 32 - 0x00000000 - 0xFFFFFFFF - - - WAKEUP_COUNTER - software wakeup counter - 0 - 32 - read-write - - - - - DGO_CTR4 - control register 4 - 0x710 - 32 - 0x00000000 - 0x00000003 - - - BANDGAP_LESS_POWER - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 1 - 1 - read-write - - - BANDGAP_LP_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 0 - 1 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/SConscript deleted file mode 100644 index dd355f33b20..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/SConscript +++ /dev/null @@ -1,24 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_clock_drv.c deleted file mode 100644 index fb8d71629c2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_clock_drv.c +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_soc.h" -#include "hpm_common.h" -#include "hpm_pllctlv2_drv.h" -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (720000000UL) -#define FREQ_PRESET1_PLL0_CLK1 (600000000UL) -#define FREQ_PRESET1_PLL0_CLK2 (400000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (666000000UL) -#define FREQ_PRESET1_PLL1_CLK2 (500000000UL) -#define FREQ_PRESET1_PLL1_CLK3 (266000000UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) -#define WDG_INSTANCE_NUM (2U) -#define BUS_FREQ_MAX (200000000UL) -#define FREQ_1MHz (1000000UL) - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ - -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for ADC - */ -static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); - -/** - * @brief Get Clock frequency for DAC - */ -static uint32_t get_frequency_for_dac(uint32_t instance); - -/** - * @brief Get Clock frequency for WDG - */ -static uint32_t get_frequency_for_ewdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PWDG - */ -static uint32_t get_frequency_for_pewdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - -static uint32_t get_frequency_for_cpu(void); -static uint32_t get_frequency_for_ahb(void); - - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ahb, - clock_node_ana0 -}; - -static const clock_node_t s_dac_clk_mux_node[] = { - clock_node_ahb, - clock_node_ana2 -}; - -static EWDG_Type *const s_wdgs[] = { HPM_EWDG0, HPM_EWDG1}; - -uint32_t hpm_core_clock; - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq = 0UL; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); - break; - case CLK_SRC_GROUP_DAC: - clk_freq = get_frequency_for_dac(node_or_instance); - break; - case CLK_SRC_GROUP_EWDG: - clk_freq = get_frequency_for_ewdg(node_or_instance); - break; - case CLK_SRC_GROUP_PEWDG: - clk_freq = get_frequency_for_pewdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_CPU0: - clk_freq = get_frequency_for_cpu(); - break; - case CLK_SRC_GROUP_AHB: - clk_freq = get_frequency_for_ahb(); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq = 0UL; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); - break; - case clock_source_pll0_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); - break; - case clock_source_pll0_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); - break; - case clock_source_pll1_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); - break; - case clock_source_pll1_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); - break; - case clock_source_pll1_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 2U); - break; - case clock_source_pll1_clk3: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 3U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - uint32_t adc_index = instance; - - (void) clk_src_type; - - if (adc_index < ADC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); - if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { - node = s_adc_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node != clock_node_ahb) { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } else { - clk_freq = get_frequency_for_ahb(); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_dac(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - if (instance < DAC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); - if (mux_in_reg < ARRAY_SIZE(s_dac_clk_mux_node)) { - node = s_dac_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node == clock_node_ahb) { - clk_freq = get_frequency_for_ahb(); - } else { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ewdg(uint32_t instance) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { - freq_in_hz = get_frequency_for_ahb(); - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_pewdg(void) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_cpu(void) -{ - uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_source(mux) / div); -} - -static uint32_t get_frequency_for_ahb(void) -{ - uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_cpu() / div); -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_DAC: - if (node_or_instance < DAC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_DAC; - clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_EWDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_EWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); - } - break; - case CLK_SRC_GROUP_PEWDG: - clk_src_group = CLK_SRC_GROUP_PEWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_CPU0: - case CLK_SRC_GROUP_AHB: - clk_src_group = CLK_SRC_GROUP_CPU0; - clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -uint32_t clock_get_divider(clock_name_t clock_name) -{ - uint32_t clk_divider = CLOCK_DIV_INVALID; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_EWDG: - clk_divider = 1; - break; - case CLK_SRC_GROUP_PEWDG: - clk_divider = 1; - break; - case CLK_SRC_GROUP_PMIC: - clk_divider = 1; - break; - case CLK_SRC_GROUP_CPU0: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_AHB: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - default: - clk_divider = CLOCK_DIV_INVALID; - break; - } - return clk_divider; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana1)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_dac_src_ahb0) || (src > clk_dac_src_ana3)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->DACCLK[node_or_instance] = - (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_EWDG) && (clk_src_grp != CLK_SRC_GROUP_PEWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_DAC: - case CLK_SRC_GROUP_EWDG: - case CLK_SRC_GROUP_PEWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AHB: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_CPU0: - if (node_or_instance == clock_node_cpu0) { - /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency - * changes, the AXI and AHB clock changes accordingly, here the driver ensures the - * AXI and AHB bus clock frequency is in valid range. - */ - uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; - uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, ahb_sub_div); - } else { - status = status_clk_shared_cpu0; - } - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu == 0U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu == 0U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_update_core_clock(void) -{ - hpm_core_clock = clock_get_frequency(clock_cpu0); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_clock_drv.h deleted file mode 100644 index 22b721cb891..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_clock_drv.h +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" -#include "hpm_csr_drv.h" - - -#define CLOCK_DIV_INVALID (~0UL) - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), - status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), - status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), - status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), - status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), - status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), - status_clk_fixed = MAKE_STATUS(status_group_clk, 10), -}; - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_EWDG (3U) -#define CLK_SRC_GROUP_PMIC (4U) -#define CLK_SRC_GROUP_AHB (5U) -#define CLK_SRC_GROUP_DAC (7U) -#define CLK_SRC_GROUP_CPU0 (9U) -#define CLK_SRC_GROUP_SRC (10U) -#define CLK_SRC_GROUP_PEWDG (11U) -#define CLK_SRC_GROUP_INVALID (15U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll1_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll1_clk3 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - - clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), - clk_dac_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), - clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - - -#define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_CPU0 (0xFFFDU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), - - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), - clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), - clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), - clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), - clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), - clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), - clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - - clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), - - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PEWDG, 0), - - clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), - - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 0), - clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 1), - clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 2), - clock_opa0 = MAKE_CLOCK_NAME(sysctl_resource_opa0, CLK_SRC_GROUP_AHB, 3), - clock_opa1 = MAKE_CLOCK_NAME(sysctl_resource_opa1, CLK_SRC_GROUP_AHB, 4), - clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), - clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 6), - clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AHB, 7), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 8), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 9), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_hdma, CLK_SRC_GROUP_AHB, 10), - clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AHB, 11), - clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_AHB, 12), - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AHB, 13), - clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_AHB, 14), - - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), - clock_pgpio = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 2), - - /* For ADC, there are 2-stage clock source and divider configurations */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), - clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), - - /* For DAC, there are 2-stage clock source and divider configurations */ - clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), - clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), - clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), - clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), - clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), - clk_pll1clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll1, CLK_SRC_GROUP_SRC, 6), - clk_pll1clk3 = MAKE_CLOCK_NAME(sysctl_resource_clk3_pll1, CLK_SRC_GROUP_SRC, 7), -} clock_name_t; - -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @param [in] clock_name clock name - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Get the IP clock divider - * Note:This API return the direct clock divider - * @param [in] clock_name clock name - * @return IP clock divider - */ -uint32_t clock_get_divider(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @return #status_success Setting ADC clock source is successful - * #status_clk_invalid Invalid ADC clock - * #status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set DAC clock source - * @param[in] clock_name DAC clock name - * @param[in] src DAC clock source - * - * @return #status_success Setting DAC clock source is successful - * #status_clk_invalid Invalid DAC clock - * #status_clk_src_invalid Invalid DAC clock source - */ -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @return #status_success Setting Clock source and divider is successful. - * #status_clk_src_invalid clock source is invalid. - * #status_clk_fixed clock source and divider is a fixed value - * #status_clk_shared_ahb Clock is shared with the AHB clock - * #status_clk_shared_axi0 Clock is shared with the AXI0 clock - * #status_clk_shared_axi1 CLock is shared with the AXI1 clock - * #status_clk_shared_axi2 Clock is shared with the AXI2 clock - * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_csr_regs.h deleted file mode 100644 index 09c7fc113ff..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_csr_regs.h +++ /dev/null @@ -1,4276 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PIME (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PIME_MASK (0x8U) -#define CSR_MXSTATUS_PIME_SHIFT (3U) -#define CSR_MXSTATUS_PIME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PIME_SHIFT) & CSR_MXSTATUS_PIME_MASK) -#define CSR_MXSTATUS_PIME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PIME_MASK) >> CSR_MXSTATUS_PIME_SHIFT) - -/* - * IME (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_IME_MASK (0x4U) -#define CSR_MXSTATUS_IME_SHIFT (2U) -#define CSR_MXSTATUS_IME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_IME_SHIFT) & CSR_MXSTATUS_IME_MASK) -#define CSR_MXSTATUS_IME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_IME_MASK) >> CSR_MXSTATUS_IME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_dmamux_src.h deleted file mode 100644 index 285bf648e26..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_dmamux_src.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_GPTMR0_0 (0x0UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x1UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x2UL) -#define HPM_DMA_SRC_GPTMR0_3 (0x3UL) -#define HPM_DMA_SRC_GPTMR1_0 (0x4UL) -#define HPM_DMA_SRC_GPTMR1_1 (0x5UL) -#define HPM_DMA_SRC_GPTMR1_2 (0x6UL) -#define HPM_DMA_SRC_GPTMR1_3 (0x7UL) -#define HPM_DMA_SRC_GPTMR2_0 (0x8UL) -#define HPM_DMA_SRC_GPTMR2_1 (0x9UL) -#define HPM_DMA_SRC_GPTMR2_2 (0xAUL) -#define HPM_DMA_SRC_GPTMR2_3 (0xBUL) -#define HPM_DMA_SRC_GPTMR3_0 (0xCUL) -#define HPM_DMA_SRC_GPTMR3_1 (0xDUL) -#define HPM_DMA_SRC_GPTMR3_2 (0xEUL) -#define HPM_DMA_SRC_GPTMR3_3 (0xFUL) -#define HPM_DMA_SRC_UART0_RX (0x14UL) -#define HPM_DMA_SRC_UART0_TX (0x15UL) -#define HPM_DMA_SRC_UART1_RX (0x16UL) -#define HPM_DMA_SRC_UART1_TX (0x17UL) -#define HPM_DMA_SRC_UART2_RX (0x18UL) -#define HPM_DMA_SRC_UART2_TX (0x19UL) -#define HPM_DMA_SRC_UART3_RX (0x1AUL) -#define HPM_DMA_SRC_UART3_TX (0x1BUL) -#define HPM_DMA_SRC_UART4_RX (0x1CUL) -#define HPM_DMA_SRC_UART4_TX (0x1DUL) -#define HPM_DMA_SRC_UART5_RX (0x1EUL) -#define HPM_DMA_SRC_UART5_TX (0x1FUL) -#define HPM_DMA_SRC_UART6_RX (0x20UL) -#define HPM_DMA_SRC_UART6_TX (0x21UL) -#define HPM_DMA_SRC_UART7_RX (0x22UL) -#define HPM_DMA_SRC_UART7_TX (0x23UL) -#define HPM_DMA_SRC_I2C0 (0x24UL) -#define HPM_DMA_SRC_I2C1 (0x25UL) -#define HPM_DMA_SRC_I2C2 (0x26UL) -#define HPM_DMA_SRC_I2C3 (0x27UL) -#define HPM_DMA_SRC_SPI0_RX (0x28UL) -#define HPM_DMA_SRC_SPI0_TX (0x29UL) -#define HPM_DMA_SRC_SPI1_RX (0x2AUL) -#define HPM_DMA_SRC_SPI1_TX (0x2BUL) -#define HPM_DMA_SRC_SPI2_RX (0x2CUL) -#define HPM_DMA_SRC_SPI2_TX (0x2DUL) -#define HPM_DMA_SRC_SPI3_RX (0x2EUL) -#define HPM_DMA_SRC_SPI3_TX (0x2FUL) -#define HPM_DMA_SRC_MCAN0 (0x30UL) -#define HPM_DMA_SRC_MCAN1 (0x31UL) -#define HPM_DMA_SRC_MCAN2 (0x32UL) -#define HPM_DMA_SRC_MCAN3 (0x33UL) -#define HPM_DMA_SRC_MOT_0 (0x34UL) -#define HPM_DMA_SRC_MOT_1 (0x35UL) -#define HPM_DMA_SRC_MOT_2 (0x36UL) -#define HPM_DMA_SRC_MOT_3 (0x37UL) -#define HPM_DMA_SRC_MOT_4 (0x38UL) -#define HPM_DMA_SRC_MOT_5 (0x39UL) -#define HPM_DMA_SRC_MOT_6 (0x3AUL) -#define HPM_DMA_SRC_MOT_7 (0x3BUL) -#define HPM_DMA_SRC_XPI0_RX (0x3CUL) -#define HPM_DMA_SRC_XPI0_TX (0x3DUL) -#define HPM_DMA_SRC_DAC0 (0x3EUL) -#define HPM_DMA_SRC_DAC1 (0x3FUL) -#define HPM_DMA_SRC_ACMP0 (0x40UL) -#define HPM_DMA_SRC_ACMP1 (0x41UL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_gpiom_soc_drv.h deleted file mode 100644 index 01e0f0a5cd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_core0_fast = 2, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_interrupt.h deleted file mode 100644 index aee210fdd6d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_interrupt.h +++ /dev/null @@ -1,876 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; - -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */ -#define CONTEXT_REG_NUM (4*(16 + 4 + 20*2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS */ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define HPM_EXTERN_C extern "C" -#else -#define HPM_EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} -#endif -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - isr(); \ -} -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) \ -{ \ - isr();\ -} - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_iomux.h deleted file mode 100644 index 34efe492b21..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_iomux.h +++ /dev/null @@ -1,777 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA00_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA00_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA00_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA01_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA01_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA01_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA02_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA02_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA03_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA03_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA03_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA04_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA04_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA04_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA04_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA04_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA04_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA05_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA05_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA05_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA05_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA05_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA05_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA06_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA06_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA06_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA06_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA06_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA07_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA07_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA07_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA07_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA08_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA08_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA09_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA09_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA10_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA10_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA10_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA10_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA10_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA11_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA11_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA11_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA11_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA11_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA11_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA12_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA12_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA12_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA12_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA12_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA12_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA13_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA13_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA13_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA13_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA13_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA14_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA14_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA15_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA16_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA16_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA16_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA16_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA16_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA17_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA17_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA17_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA17_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA17_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA18_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA18_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA18_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA18_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA18_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA18_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA19_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA19_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA19_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA19_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA19_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA20_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA20_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA20_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA20_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA20_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA20_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA20_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA21_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA21_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA21_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA21_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA21_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA21_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA22_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA22_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA22_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA22_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA22_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA22_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA23_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA23_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA23_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA23_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA23_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA24_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA24_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA24_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA24_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA24_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA25_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA25_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA25_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA25_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA25_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA26_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA26_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA26_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA26_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA26_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA26_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA26_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA26_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA26_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA27_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA27_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA27_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA27_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA27_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA27_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA27_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA27_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA28_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA28_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA28_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA28_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA28_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA28_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA28_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA28_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA28_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA29_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA29_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA29_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA29_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA29_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA29_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA29_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA29_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA30_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA30_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA30_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA30_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA30_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA30_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA31_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA31_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA31_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA31_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA31_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA31_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB00_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB00_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB00_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB01_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB01_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB01_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB02_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB02_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB02_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB03_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB03_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB03_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB04_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB04_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB04_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB04_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB04_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB05_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB05_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB05_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB05_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB05_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB06_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB06_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB06_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PB06_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB06_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB06_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB07_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB07_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB07_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PB07_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB07_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB08_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB08_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB08_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB08_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB08_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB09_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB09_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB09_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB09_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB09_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB10_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB10_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB10_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB10_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB10_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB10_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB11_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB11_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB11_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB12_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB12_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB12_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB12_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB12_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB12_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB13_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB13_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB13_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB13_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB13_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB13_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB14_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB14_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB14_FUNC_CTL_RDC0_EXC_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PB14_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB14_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB14_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB15_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB15_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB15_FUNC_CTL_RDC0_EXC_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PB15_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB15_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX03_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX05_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY00_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PY00_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY01_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PY01_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY01_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PY01_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY02_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY02_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PY02_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY02_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PY02_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PY02_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY03_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY03_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PY03_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY03_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY04_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY04_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY05_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY05_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY05_FUNC_CTL_EWDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY06_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PY06_FUNC_CTL_EWDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PY07_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_l1c_drv.h deleted file mode 100644 index e3034e6e831..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 16KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(16 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 32B */ -#define HPM_L1C_CACHELINE_SIZE (32) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_mcan_soc.h deleted file mode 100644 index 0cf2b7408d9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_mcan_soc.h +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MCAN_SOC_H -#define HPM_MCAN_SOC_H - -#include -#include "hpm_mcan_regs.h" -#include "hpm_soc.h" -#include "hpm_soc_feature.h" - -#define MCAN_SOC_TSU_SRC_TWO_STAGES (1U) - -#define HPM_MCAN_EXT_TBSEL_NUM (4U) -#define HPM_MCAN_TBSEL_BASE (0xF02FF000UL) -#define HPM_MCAN_TBSEL (*(volatile uint32_t *)HPM_MCAN_TBSEL_BASE) -#define HPM_MCAN_TBSEL_BITWIDTH (6U) -#define HPM_MCAN_TBSEL_MASK ((1UL << HPM_MCAN_TBSEL_BITWIDTH) - 1UL) -#define HPM_MCAN_TBSEL0_SHIFT (8U) - -/** - * @brief MCAN MSG BUF base address (AHB_RAM) - */ -#define MCAN_MSG_BUF_SIZE_IN_WORDS (640U) -#define MCAN_IP_SLOT_SIZE (0x4000U) - -/** - * @brief TSU External Timebase Sources - */ -#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_1 (1U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_2 (2U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3 (3U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3) - -/** - * @brief MCAN TSU timebase option for each External Timebase - */ -#define MCAN_TSU_TBSEL_PTPC0 (0x20) -#define MCAN_TSU_TBSEL_MCAN0 (0x00) -#define MCAN_TSU_TBSEL_MCAN1 (0x01) -#define MCAN_TSU_TBSEL_MCAN2 (0x02) -#define MCAN_TSU_TBSEL_MCAN3 (0x03) - - -ATTR_PLACE_AT(".ahb_sram") extern uint32_t mcan_soc_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS * MCAN_SOC_MAX_COUNT]; - -#ifdef __cpluspus -extern "C" { -#endif - -/** - * @brief Set External Timebase Source for MCAN TSU - * @param [in] ptr MCAN base - * @param [in] src External Timebase source - */ -static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) -{ - if (src < HPM_MCAN_EXT_TBSEL_NUM) { - ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); - } -} - -/** - * @brief Set the Source for specified external timebase - * - * @param [in] ptr MCAN base - * @param [in] ext_tbsel External TBSEL index - * @param [in] tbsel_option Timebase source selection - */ -static inline void mcan_set_tsu_tbsel_option(MCAN_Type *ptr, uint8_t ext_tbsel, uint8_t tbsel_option) -{ - (void) ptr; - if (ext_tbsel < HPM_MCAN_EXT_TBSEL_NUM) { - uint32_t tbsel_shift = (ext_tbsel * HPM_MCAN_TBSEL_BITWIDTH) + HPM_MCAN_TBSEL0_SHIFT; - uint32_t tbsel_mask = HPM_MCAN_TBSEL_MASK << tbsel_shift; - HPM_MCAN_TBSEL = (HPM_MCAN_TBSEL & ~tbsel_mask) | (((uint32_t) tbsel_option << tbsel_shift) & tbsel_mask); - } -} - -/** - * @brief Enable Standby Pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Disable Standby pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Get RAM base for MCAN - * @param [in] ptr MCAN base - * @return RAM base for MCAN - */ -static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) -{ - (void) ptr; - return (uint32_t) &mcan_soc_msg_buf[0]; -} - -/** - * @brief Get the MCAN RAM offset in the dedicated/shared RAM for - * @param [in] ptr MCAN base - * @return RAM offset for MCAN - */ -static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) -{ - uint32_t index = ((uint32_t) ptr - HPM_MCAN0_BASE) / MCAN_IP_SLOT_SIZE; - - return (index * MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); -} - -/** - * @brief Get MCAN RAM size - * @param [in] ptr MCAN base - * @return RAM size in bytes - */ -static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) -{ - (void) ptr; - return (MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); -} - -#ifdef __cpluspus -} -#endif - -#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_misc.h deleted file mode 100644 index 367c61138a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_misc.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define ILM_LOCAL_BASE (0x0U) -#define ILM_SIZE_IN_BYTE (0x20000U) -#define DLM_LOCAL_BASE (0x80000U) -#define DLM_SIZE_IN_BYTE (0x20000U) -#define CORE0_ILM_SYSTEM_BASE (0x1040000U) -#define CORE0_DLM_SYSTEM_BASE (0x1060000U) - -#define ADDRESS_IN_ILM(address) \ - ((ILM_LOCAL_BASE) <= (address)) && \ - ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_DLM(address) \ - ((DLM_LOCAL_BASE) <= (address)) && \ - ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) - -#define DLM_TO_SYSTEM(address) \ - (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) -#define ILM_TO_SYSTEM(address) \ - (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) -#define SYSTEM_TO_DLM(address) \ - ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) - -#define HPM_CORE0 (0U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_otp_drv.c deleted file mode 100644 index a68fc69c0e0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - /* Wait until LDO is ready */ - while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { - } - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = HPM_OTP; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_otp_drv.h deleted file mode 100644 index b61c805a1df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_otp_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - -/** - * @brief Initialize OTP controller - */ -void otp_init(void); - -/** - * @brief De-initialize OTP controller - */ -void otp_deinit(void); - -/** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_shadow(uint32_t addr); - -/** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_ip(uint32_t addr); - -/** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - -/** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ -hpm_stat_t otp_reload(otp_region_t region); - -/** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - -/** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [in] val Data to be written - * @return API execution status - */ -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_pcfg_drv.h deleted file mode 100644 index 1920823cebd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_pcfg_drv.h +++ /dev/null @@ -1,497 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) -{ - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK | PCFG_DCDC_PROT_OVERLOAD_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_plic_drv.h deleted file mode 100644 index 4c96737ece4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_plic_drv.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -#define HPM_PLIC_TRIGGER_TYPE_OFFSET (0x00001080UL) -#define HPM_PLIC_TRIGGER_TYPE_SHIFT_PER_SORUCE 1 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *) (base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *) (base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *) (base + - HPM_PLIC_PRIORITY_OFFSET + - ((irq - 1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Set interrupt trigger type to edge-triggerred - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_edge_trigger(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); - *current_ptr |= (1UL << (irq & 0x1F)); -} - -/** - * @brief Set interrupt trigger type to level-triggerred - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_level_trigger(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); - *current_ptr &= ~(1UL << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *) (base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *) (base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} - -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_pmic_iomux.h deleted file mode 100644 index a95ce61e50f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_pmic_iomux.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PEWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ppor_drv.h deleted file mode 100644 index bc7ee37f6ad..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ppor_drv.h +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_pmic_wdog = 1 << 24, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE &= ~mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE |= mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE |= mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE &= ~mask; -} - - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_romapi.h deleted file mode 100644 index c93f04dc914..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_romapi.h +++ /dev/null @@ -1,938 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_sdp_drv.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -typedef struct { - uint32_t region_start; - uint32_t region_end; - uint8_t aes_key[16]; - uint8_t nonce[8]; - uint8_t index; - bool enable; - bool valid; - bool lock; -} exip_region_context_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, - uint32_t serial_root_clk_freq, - uint32_t data_valid_time, - xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t - (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t - (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t - (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t - (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t - (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t - (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief EXIP driver interface - */ -typedef struct { - uint32_t version; - hpm_stat_t (*enable)(XPI_Type *base); - hpm_stat_t (*disable)(XPI_Type *base); - hpm_stat_t (*lock_reg_access)(XPI_Type *base); - hpm_stat_t (*configure_region)(XPI_Type *base, const exip_region_context_t *ctx); - - bool (*remap_config)(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset); - bool (*remap_enabled)(XPI_Type *base); - void (*remap_disable)(XPI_Type *base); - bool (*exip_region_config)(XPI_Type *base, uint32_t index, exip_region_param_t *param); - void (*exip_region_disable)(XPI_Type *base, uint32_t index); -} exip_driver_interface_t; - -/** - * @brief SDP API interface - */ -typedef struct { - /**< SDP API interface: API version */ - uint32_t version; - /**< SDP API interface: Initialize IP */ - hpm_stat_t (*sdp_ip_init)(void); - /**< SDP API interface: Deinitialize IP */ - hpm_stat_t (*sdp_ip_deinit)(void); - /**< SDP API interface: Set AES key */ - hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: AES ECB crypto operation */ - hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API interface: AES CBC crypto operation */ - hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API interface: AES CTR crypto operation */ - hpm_stat_t - (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API interface: AES CCM encryption */ - hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: AES CCM Decrypt and verify */ - hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: memcpy */ - hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); - /**< SDP API interface: memset */ - hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); - /**< SDP API interface: HASH initialization */ - hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - /**< SDP API interface: HASH update */ - hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - /**< SDP API interface: HASH finish */ - hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); - /**< SDP API interface: Set SM4 Key */ - hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: SM4 Crypto ECB mode */ - hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API Interface: SM4 Crypto CBC mode*/ - hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API Interface: SM4 CTR mode */ - hpm_stat_t - (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API Interface: SM4 CCM Encryption */ - hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API Interface: SM4 CCM Decrypt and Verify */ - hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); -} sdp_driver_interface_t; - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const uint32_t reserved0; - /**< Bootloader API table: sdp driver interface address */ - const sdp_driver_interface_t *sdp_driver_if; - const uint32_t reserved1[3]; - const exip_driver_interface_t *exip_api_if; - const uint32_t family_id; -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); - fencei(); - return status; -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); - fencei(); - return status; -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if - ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API execution address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, - xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - return ROM_API_TABLE_ROOT->exip_api_if->remap_config(base, start, len, offset); -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->remap_disable(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - return ROM_API_TABLE_ROOT->exip_api_if->remap_enabled(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - bool result = ROM_API_TABLE_ROOT->exip_api_if->exip_region_config(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - ROM_API_TABLE_ROOT->exip_api_if->exip_region_disable(base, index); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->enable(base); - fencei(); -} - -/** - * @brief Disable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->disable(base); - fencei(); -} - -/*********************************************************************************************************************** - * - * - * SDP Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Initialize SDP IP - */ -static inline void rom_sdp_init(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); -} - -/** - * @brief De-initialize SDP IP - */ -static inline void rom_sdp_deinit(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); -} - -/** - * @brief Set AES key to SDP - * @param [in] aes_ctx AES context - * @param [in] key AES key buffer - * @param [in] key_bits AES key-bit option - * @param[in] key_idx AES key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] len Data length for AES encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); -} - -/** - * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] length Data length for AES encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); -} - -/** - * @brief Set SM4 key to SDP - * @param [in] sm4_ctx SM4 context - * @param [in] key SM4 key buffer - * @param [in] key_bits SM4 key-bit option - * @param[in] key_idx SM4 key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, - const uint8_t *key, - sdp_sm4_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] len Data length for SM4 encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); -} - -/** - * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); -} - -/** - * @brief HASH initialization - * @param [in] hash_ctx HASH context - * @param [in] alg HASH algorithm - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); -} - -/** - * @brief HASH Update - * @param [in] hash_ctx HASH context - * @param [in] data Data for HASH operation - * @param [in] length of the data for HASH operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); -} - -/** - * @brief HASH finialize - * @param [in] hash_ctx HASH context - * @param [out] digest the output digest - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); -} - -/** - * @brief SDP memcpy operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memcpy - * @param [in] src Source address for memcpy - * @param [in] length Size of data for memcpy operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); -} - -/** - * @brief SDP memset operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memset - * @param [in] pattern pattern for memset - * @param [in] length Size of data for memset operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ea3ba9e8f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union { - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ses_reg.xml deleted file mode 100644 index ed56f20d89d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ses_reg.xml +++ /dev/null @@ -1,23630 +0,0 @@ - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ses_riscv_cpu_regs.xml deleted file mode 100644 index 7e693311ca5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_ses_riscv_cpu_regs.xml +++ /dev/null @@ -1,808 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc.h deleted file mode 100644 index 268e53839f0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_X 3 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 4 /* GPIO0_Y IRQ */ -#define IRQn_GPTMR0 5 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 6 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 7 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 8 /* GPTMR3 IRQ */ -#define IRQn_UART0 13 /* UART0 IRQ */ -#define IRQn_UART1 14 /* UART1 IRQ */ -#define IRQn_UART2 15 /* UART2 IRQ */ -#define IRQn_UART3 16 /* UART3 IRQ */ -#define IRQn_UART4 17 /* UART4 IRQ */ -#define IRQn_UART5 18 /* UART5 IRQ */ -#define IRQn_UART6 19 /* UART6 IRQ */ -#define IRQn_UART7 20 /* UART7 IRQ */ -#define IRQn_I2C0 21 /* I2C0 IRQ */ -#define IRQn_I2C1 22 /* I2C1 IRQ */ -#define IRQn_I2C2 23 /* I2C2 IRQ */ -#define IRQn_I2C3 24 /* I2C3 IRQ */ -#define IRQn_SPI0 25 /* SPI0 IRQ */ -#define IRQn_SPI1 26 /* SPI1 IRQ */ -#define IRQn_SPI2 27 /* SPI2 IRQ */ -#define IRQn_SPI3 28 /* SPI3 IRQ */ -#define IRQn_TSNS 29 /* TSNS IRQ */ -#define IRQn_MBX0A 30 /* MBX0A IRQ */ -#define IRQn_MBX0B 31 /* MBX0B IRQ */ -#define IRQn_EWDG0 32 /* EWDG0 IRQ */ -#define IRQn_EWDG1 33 /* EWDG1 IRQ */ -#define IRQn_HDMA 34 /* HDMA IRQ */ -#define IRQn_MCAN0 35 /* MCAN0 IRQ */ -#define IRQn_MCAN1 36 /* MCAN1 IRQ */ -#define IRQn_MCAN2 37 /* MCAN2 IRQ */ -#define IRQn_MCAN3 38 /* MCAN3 IRQ */ -#define IRQn_PTPC 39 /* PTPC IRQ */ -#define IRQn_PWM0 40 /* PWM0 IRQ */ -#define IRQn_QEI0 41 /* QEI0 IRQ */ -#define IRQn_SEI0 42 /* SEI0 IRQ */ -#define IRQn_MMC0 43 /* MMC0 IRQ */ -#define IRQn_TRGMUX0 44 /* TRGMUX0 IRQ */ -#define IRQn_PWM1 45 /* PWM1 IRQ */ -#define IRQn_QEI1 46 /* QEI1 IRQ */ -#define IRQn_SEI1 47 /* SEI1 IRQ */ -#define IRQn_MMC1 48 /* MMC1 IRQ */ -#define IRQn_TRGMUX1 49 /* TRGMUX1 IRQ */ -#define IRQn_RDC 50 /* RDC IRQ */ -#define IRQn_USB0 51 /* USB0 IRQ */ -#define IRQn_XPI0 52 /* XPI0 IRQ */ -#define IRQn_SDP 53 /* SDP IRQ */ -#define IRQn_PSEC 54 /* PSEC IRQ */ -#define IRQn_SECMON 55 /* SECMON IRQ */ -#define IRQn_RNG 56 /* RNG IRQ */ -#define IRQn_FUSE 57 /* FUSE IRQ */ -#define IRQn_ADC0 58 /* ADC0 IRQ */ -#define IRQn_ADC1 59 /* ADC1 IRQ */ -#define IRQn_DAC0 60 /* DAC0 IRQ */ -#define IRQn_DAC1 61 /* DAC1 IRQ */ -#define IRQn_ACMP_0 62 /* ACMP_0 IRQ */ -#define IRQn_ACMP_1 63 /* ACMP_1 IRQ */ -#define IRQn_SYSCTL 64 /* SYSCTL IRQ */ -#define IRQn_PGPIO 65 /* PGPIO IRQ */ -#define IRQn_PTMR 66 /* PTMR IRQ */ -#define IRQn_PUART 67 /* PUART IRQ */ -#define IRQn_PEWDG 68 /* PEWDG IRQ */ -#define IRQn_BROWNOUT 69 /* BROWNOUT IRQ */ -#define IRQn_PAD_WAKEUP 70 /* PAD_WAKEUP IRQ */ -#define IRQn_DEBUG0 71 /* DEBUG0 IRQ */ -#define IRQn_DEBUG1 72 /* DEBUG1 IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0xC0000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF00D0000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF411C000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF0000000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF0004000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* GPTMR2 base address */ -#define HPM_GPTMR2_BASE (0xF0008000UL) -/* GPTMR2 base pointer */ -#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) -/* GPTMR3 base address */ -#define HPM_GPTMR3_BASE (0xF000C000UL) -/* GPTMR3 base pointer */ -#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF4120000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* UART4 base address */ -#define HPM_UART4_BASE (0xF0050000UL) -/* UART4 base pointer */ -#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) -/* UART5 base address */ -#define HPM_UART5_BASE (0xF0054000UL) -/* UART5 base pointer */ -#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) -/* UART6 base address */ -#define HPM_UART6_BASE (0xF0058000UL) -/* UART6 base pointer */ -#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) -/* UART7 base address */ -#define HPM_UART7_BASE (0xF005C000UL) -/* UART7 base pointer */ -#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF4124000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF0060000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF0064000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF0068000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF006C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0070000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0074000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0078000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF007C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) - -#include "hpm_crc_regs.h" -/* Address of CRC instances */ -/* CRC base address */ -#define HPM_CRC_BASE (0xF0080000UL) -/* CRC base pointer */ -#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) - -#include "hpm_tsns_regs.h" -/* Address of TSNS instances */ -/* TSNS base address */ -#define HPM_TSNS_BASE (0xF0090000UL) -/* TSNS base pointer */ -#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) - -#include "hpm_ewdg_regs.h" -/* Address of EWDG instances */ -/* EWDG0 base address */ -#define HPM_EWDG0_BASE (0xF00B0000UL) -/* EWDG0 base pointer */ -#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) -/* EWDG1 base address */ -#define HPM_EWDG1_BASE (0xF00B4000UL) -/* EWDG1 base pointer */ -#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) -/* PEWDG base address */ -#define HPM_PEWDG_BASE (0xF4128000UL) -/* PEWDG base pointer */ -#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C4000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dmav2_regs.h" -/* Address of DMAV2 instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C8000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF00D8000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_mcan_regs.h" -/* Address of MCAN instances */ -/* MCAN0 base address */ -#define HPM_MCAN0_BASE (0xF0280000UL) -/* MCAN0 base pointer */ -#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) -/* MCAN1 base address */ -#define HPM_MCAN1_BASE (0xF0284000UL) -/* MCAN1 base pointer */ -#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) -/* MCAN2 base address */ -#define HPM_MCAN2_BASE (0xF0288000UL) -/* MCAN2 base pointer */ -#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) -/* MCAN3 base address */ -#define HPM_MCAN3_BASE (0xF028C000UL) -/* MCAN3 base pointer */ -#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) - -#include "hpm_ptpc_regs.h" -/* Address of PTPC instances */ -/* PTPC base address */ -#define HPM_PTPC_BASE (0xF02FC000UL) -/* PTPC base pointer */ -#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) - -#include "hpm_qeiv2_regs.h" -/* Address of QEIV2 instances */ -/* QEI0 base address */ -#define HPM_QEI0_BASE (0xF0300000UL) -/* QEI0 base pointer */ -#define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE) -/* QEI1 base address */ -#define HPM_QEI1_BASE (0xF0304000UL) -/* QEI1 base pointer */ -#define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE) - -#include "hpm_qeo_regs.h" -/* Address of QEO instances */ -/* QEO0 base address */ -#define HPM_QEO0_BASE (0xF0308000UL) -/* QEO0 base pointer */ -#define HPM_QEO0 ((QEO_Type *) HPM_QEO0_BASE) -/* QEO1 base address */ -#define HPM_QEO1_BASE (0xF030C000UL) -/* QEO1 base pointer */ -#define HPM_QEO1 ((QEO_Type *) HPM_QEO1_BASE) - -#include "hpm_mmc_regs.h" -/* Address of MMC instances */ -/* MMC0 base address */ -#define HPM_MMC0_BASE (0xF0310000UL) -/* MMC0 base pointer */ -#define HPM_MMC0 ((MMC_Type *) HPM_MMC0_BASE) -/* MMC1 base address */ -#define HPM_MMC1_BASE (0xF0314000UL) -/* MMC1 base pointer */ -#define HPM_MMC1 ((MMC_Type *) HPM_MMC1_BASE) - -#include "hpm_pwm_regs.h" -/* Address of PWM instances */ -/* PWM0 base address */ -#define HPM_PWM0_BASE (0xF0318000UL) -/* PWM0 base pointer */ -#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) -/* PWM1 base address */ -#define HPM_PWM1_BASE (0xF031C000UL) -/* PWM1 base pointer */ -#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) - -#include "hpm_rdc_regs.h" -/* Address of RDC instances */ -/* RDC base address */ -#define HPM_RDC_BASE (0xF0320000UL) -/* RDC base pointer */ -#define HPM_RDC ((RDC_Type *) HPM_RDC_BASE) - -#include "hpm_plb_regs.h" -/* Address of PLB instances */ -/* PLB base address */ -#define HPM_PLB_BASE (0xF0324000UL) -/* PLB base pointer */ -#define HPM_PLB ((PLB_Type *) HPM_PLB_BASE) - -#include "hpm_synt_regs.h" -/* Address of SYNT instances */ -/* SYNT base address */ -#define HPM_SYNT_BASE (0xF0328000UL) -/* SYNT base pointer */ -#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) - -#include "hpm_sei_regs.h" -/* Address of SEI instances */ -/* SEI base address */ -#define HPM_SEI_BASE (0xF032C000UL) -/* SEI base pointer */ -#define HPM_SEI ((SEI_Type *) HPM_SEI_BASE) - -#include "hpm_trgm_regs.h" -/* Address of TRGM instances */ -/* TRGM0 base address */ -#define HPM_TRGM0_BASE (0xF033C000UL) -/* TRGM0 base pointer */ -#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF300C000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) - -/* Address of ROMC instances */ -/* ROMC base address */ -#define HPM_ROMC_BASE (0xF3014000UL) - -#include "hpm_sdp_regs.h" -/* Address of SDP instances */ -/* SDP base address */ -#define HPM_SDP_BASE (0xF3040000UL) -/* SDP base pointer */ -#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) - -#include "hpm_sec_regs.h" -/* Address of SEC instances */ -/* SEC base address */ -#define HPM_SEC_BASE (0xF3044000UL) -/* SEC base pointer */ -#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) - -#include "hpm_mon_regs.h" -/* Address of MON instances */ -/* MON base address */ -#define HPM_MON_BASE (0xF3048000UL) -/* MON base pointer */ -#define HPM_MON ((MON_Type *) HPM_MON_BASE) - -#include "hpm_rng_regs.h" -/* Address of RNG instances */ -/* RNG base address */ -#define HPM_RNG_BASE (0xF304C000UL) -/* RNG base pointer */ -#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTP base address */ -#define HPM_OTP_BASE (0xF3050000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF3054000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF3080000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) -/* ADC1 base address */ -#define HPM_ADC1_BASE (0xF3084000UL) -/* ADC1 base pointer */ -#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) - -#include "hpm_dac_regs.h" -/* Address of DAC instances */ -/* DAC0 base address */ -#define HPM_DAC0_BASE (0xF3090000UL) -/* DAC0 base pointer */ -#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) -/* DAC1 base address */ -#define HPM_DAC1_BASE (0xF3094000UL) -/* DAC1 base pointer */ -#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) - -#include "hpm_opamp_regs.h" -/* Address of OPAMP instances */ -/* OPAMP0 base address */ -#define HPM_OPAMP0_BASE (0xF30A0000UL) -/* OPAMP0 base pointer */ -#define HPM_OPAMP0 ((OPAMP_Type *) HPM_OPAMP0_BASE) -/* OPAMP1 base address */ -#define HPM_OPAMP1_BASE (0xF30A4000UL) -/* OPAMP1 base pointer */ -#define HPM_OPAMP1 ((OPAMP_Type *) HPM_OPAMP1_BASE) - -#include "hpm_acmp_regs.h" -/* Address of ACMP instances */ -/* ACMP base address */ -#define HPM_ACMP_BASE (0xF30B0000UL) -/* ACMP base pointer */ -#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF4118000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) - -#include "hpm_pllctlv2_regs.h" -/* Address of PLLCTLV2 instances */ -/* PLLCTLV2 base address */ -#define HPM_PLLCTLV2_BASE (0xF40C0000UL) -/* PLLCTLV2 base pointer */ -#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF4100000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF4104000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR0 base address */ -#define HPM_PGPR0_BASE (0xF4110000UL) -/* PGPR0 base pointer */ -#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) -/* PGPR1 base address */ -#define HPM_PGPR1_BASE (0xF4114000UL) -/* PGPR1 base pointer */ -#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) - -#include "hpm_pdgo_regs.h" -/* Address of PDGO instances */ -/* PDGO base address */ -#define HPM_PDGO_BASE (0xF4134000UL) -/* PDGO base pointer */ -#define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_trgmmux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc_feature.h deleted file mode 100644 index 9a9bfebeca4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc_feature.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" -#include "hpm_soc_ip_feature.h" - -/* - * PLIC feature - */ -#define PLIC_SUPPORT_EDGE_TRIGGER (1) - -/* - * PMP/PMA Feature - */ -#define PMP_SUPPORT_PMA (0) - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (2U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (24U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (32U) -#define DMA_SOC_MAX_COUNT (1U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n) -#define DMA_SOC_HAS_IDLE_FLAG (1U) - -/* - * DMAMUX Section - */ -#define DMAMUX_SOC_WRITEONLY (1U) - -/* - * USB Section - */ -#define USB_SOC_MAX_COUNT (1U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* - * ADC Section - */ -#define ADC_SOC_IP_VERSION (3U) -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_SEQ_HCFG_EN (1U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * SDP Section - */ -#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) -#define SDP_HAS_SM3_SUPPORT (1U) -#define SDP_HAS_SM4_SUPPORT (1U) - -/* - * SOC Privilege mode - */ -#define SOC_HAS_S_MODE (0U) - -/* - * DAC Section - */ -#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) -#define DAC_SOC_MAX_DATA (4095U) -#define DAC_SOC_MAX_BUFF_COUNT (65536U) -#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) - -/* - * UART Section - */ -#define UART_SOC_FIFO_SIZE (16U) -#define UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */ - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) -#define SPI_SOC_FIFO_DEPTH (8U) - -/* - * OTP Section - */ -#define OTP_SOC_UUID_IDX (88U) -#define OTP_SOC_UUID_LEN (16U) /* in bytes */ - -/* - * PWM Section - */ -#define PWM_SOC_HRPWM_SUPPORT (0U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) -#define PWM_SOC_TIMER_RESET_SUPPORT (1U) - -/* - * TRGM section - */ -#define TRGM_SOC_HAS_FILTER_SHIFT (1U) -#define TRGM_SOC_HAS_DMAMUX_EN (1U) -#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U) -#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U) -#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U) - -/* - * MCAN Section - */ -#define MCAN_SOC_MAX_COUNT (4U) -#define MCAN_SOC_MSG_BUF_IN_IP (0U) -#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) -#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT - -/* - * EWDG Section - */ -#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) -#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) -#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1) -#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1) - -/* - * Sync Timer - */ -#define SYNT_SOC_HAS_TIMESTAMP (1U) - -/* - * GPIO - */ -#define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U) - -/** - * OPAMP - */ -#define OPAMP_SOC_HAS_MAX_PRESET_CHN_NUM (7U) - - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc_ip_feature.h deleted file mode 100644 index d066173d287..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_soc_ip_feature.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* GPTMR related feature */ -#define HPM_IP_FEATURE_GPTMR_MONITOR 1 -#define HPM_IP_FEATURE_GPTMR_OP_MODE 1 - -/* UART related feature */ -#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 -#define HPM_IP_FEATURE_UART_FCRR 1 -#define HPM_IP_FEATURE_UART_RX_EN 1 -#define HPM_IP_FEATURE_UART_E00018_FIX 1 -#define HPM_IP_FEATURE_UART_9BIT_MODE 1 -#define HPM_IP_FEATURE_UART_ADDR_MATCH 1 -#define HPM_IP_FEATURE_UART_TRIG_MODE 1 -#define HPM_IP_FEATURE_UART_FINE_FIFO_THRLD 1 -#define HPM_IP_FEATURE_UART_IIR2 1 - -/* I2C related feature */ -#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 - -/* SPI related feature */ -#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 -#define HPM_IP_FEATURE_SPI_CS_SELECT 1 -#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 - -/* PWM related feature */ -#define HPM_IP_FEATURE_PWM_COUNTER_RESET 1 - -/* ADC16 related feature */ -#define HPM_IP_FEATURE_ADC16_HAS_MOT_EN 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_sysctl_drv.c deleted file mode 100644 index ba5a53acbf3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_sysctl_drv.c +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) - -static inline bool sysctl_valid_cpu_index(uint8_t cpu) -{ - if (cpu != SYSCTL_CPU_CPU0) { - return false; - } - return true; -} - -hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) -{ - uint32_t i; - if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { - return status_invalid_argument; - } - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i]; - } - return status_success; -} - -static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[cpu].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); -} - -hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); -} - -static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[cpu].GPR[start + i] = *(data + i); - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) -{ - ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & - ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | - SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | - (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | - SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | - SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | - SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | - SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | - SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = { 0 }; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].GPR[0] = entry; - ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); - return status_success; -} - -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 0, entry); -} - -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable) -{ - uint32_t index, offset; - if (resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource) -{ - uint32_t index, offset; - bool enable; - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | - (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, - clock_source_t source, - uint32_t cpu_div, - uint32_t ahb_sub_div) -{ - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - - uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; - if (origin_cpu_div == cpu_div) { - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - } - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | SYSCTL_CLOCK_CPU_SUB0_DIV_SET(ahb_sub_div - 1); - - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - - return status_success; -} - -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) -{ - if (source >= clock_source_adc_clk_end) { - return status_invalid_argument; - } - uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); - if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { - return status_invalid_argument; - } - - ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); - - return status_success; -} - -hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source) -{ - if (source >= clock_source_dac_clk_end) { - return status_invalid_argument; - } - uint32_t dac_index = (uint32_t) (node - clock_node_dac_start); - if (dac_index >= ARRAY_SIZE(ptr->DACCLK)) { - return status_invalid_argument; - } - - ptr->DACCLK[dac_index] = (ptr->DACCLK[dac_index] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(source); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_sysctl_drv.h deleted file mode 100644 index b591746c954..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_sysctl_drv.h +++ /dev/null @@ -1,1254 +0,0 @@ -/** - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - - sysctl_retention_domain_xtal24m = 4, - sysctl_retention_domain_pll0 = 5, - sysctl_retention_domain_pll1 = 6, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_cpu0, -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = 0, - sysctl_resource_cpx0 = 1, - sysctl_resource_pow_cpu0 = 21, - sysctl_resource_rst_soc = 22, - sysctl_resource_rst_cpu0 = 23, - sysctl_resource_xtal = 32, - sysctl_resource_pll0 = 33, - sysctl_resource_clk0_pll0 = 34, - sysctl_resource_clk1_pll0 = 35, - sysctl_resource_clk2_pll0 = 36, - sysctl_resource_pll1 = 37, - sysctl_resource_clk0_pll1 = 38, - sysctl_resource_clk1_pll1 = 39, - sysctl_resource_clk2_pll1 = 40, - sysctl_resource_clk3_pll1 = 41, - sysctl_resource_pll0_ref = 42, - sysctl_resource_pll1_ref = 43, - sysctl_resource_clk_top_cpu0 = 64, - sysctl_resource_clk_top_mchtmr0 = 65, - sysctl_resource_clk_top_can0 = 66, - sysctl_resource_clk_top_can1 = 67, - sysctl_resource_clk_top_can2 = 68, - sysctl_resource_clk_top_can3 = 69, - sysctl_resource_clk_top_lin0 = 70, - sysctl_resource_clk_top_lin1 = 71, - sysctl_resource_clk_top_lin2 = 72, - sysctl_resource_clk_top_lin3 = 73, - sysctl_resource_clk_top_gptmr0 = 74, - sysctl_resource_clk_top_gptmr1 = 75, - sysctl_resource_clk_top_gptmr2 = 76, - sysctl_resource_clk_top_gptmr3 = 77, - sysctl_resource_clk_top_i2c0 = 78, - sysctl_resource_clk_top_i2c1 = 79, - sysctl_resource_clk_top_i2c2 = 80, - sysctl_resource_clk_top_i2c3 = 81, - sysctl_resource_clk_top_spi0 = 82, - sysctl_resource_clk_top_spi1 = 83, - sysctl_resource_clk_top_spi2 = 84, - sysctl_resource_clk_top_spi3 = 85, - sysctl_resource_clk_top_uart0 = 86, - sysctl_resource_clk_top_uart1 = 87, - sysctl_resource_clk_top_uart2 = 88, - sysctl_resource_clk_top_uart3 = 89, - sysctl_resource_clk_top_uart4 = 90, - sysctl_resource_clk_top_uart5 = 91, - sysctl_resource_clk_top_uart6 = 92, - sysctl_resource_clk_top_uart7 = 93, - sysctl_resource_clk_top_xip0 = 94, - sysctl_resource_clk_top_ana0 = 95, - sysctl_resource_clk_top_ana1 = 96, - sysctl_resource_clk_top_ana2 = 97, - sysctl_resource_clk_top_ana3 = 98, - sysctl_resource_clk_top_ref0 = 99, - sysctl_resource_clk_top_ref1 = 100, - sysctl_resource_clk_top_adc0 = 101, - sysctl_resource_clk_top_adc1 = 102, - sysctl_resource_clk_top_dac0 = 103, - sysctl_resource_clk_top_dac1 = 104, - - sysctl_resource_linkable_start = 256, - sysctl_resource_ahb0 = 256, - sysctl_resource_lmm0 = 257, - sysctl_resource_mchtmr0 = 258, - sysctl_resource_rom0 = 259, - sysctl_resource_can0 = 260, - sysctl_resource_can1 = 261, - sysctl_resource_can2 = 262, - sysctl_resource_can3 = 263, - sysctl_resource_ptpc = 264, - sysctl_resource_lin0 = 265, - sysctl_resource_lin1 = 266, - sysctl_resource_lin2 = 267, - sysctl_resource_lin3 = 268, - sysctl_resource_gptmr0 = 269, - sysctl_resource_gptmr1 = 270, - sysctl_resource_gptmr2 = 271, - sysctl_resource_gptmr3 = 272, - sysctl_resource_i2c0 = 273, - sysctl_resource_i2c1 = 274, - sysctl_resource_i2c2 = 275, - sysctl_resource_i2c3 = 276, - sysctl_resource_spi0 = 277, - sysctl_resource_spi1 = 278, - sysctl_resource_spi2 = 279, - sysctl_resource_spi3 = 280, - sysctl_resource_uart0 = 281, - sysctl_resource_uart1 = 282, - sysctl_resource_uart2 = 283, - sysctl_resource_uart3 = 284, - sysctl_resource_uart4 = 285, - sysctl_resource_uart5 = 286, - sysctl_resource_uart6 = 287, - sysctl_resource_uart7 = 288, - sysctl_resource_wdg0 = 289, - sysctl_resource_wdg1 = 290, - sysctl_resource_mbx0 = 291, - sysctl_resource_tsns = 292, - sysctl_resource_crc0 = 293, - sysctl_resource_adc0 = 294, - sysctl_resource_adc1 = 295, - sysctl_resource_dac0 = 296, - sysctl_resource_dac1 = 297, - sysctl_resource_acmp = 298, - sysctl_resource_opa0 = 299, - sysctl_resource_opa1 = 300, - sysctl_resource_mot0 = 301, - sysctl_resource_rng0 = 302, - sysctl_resource_sdp0 = 303, - sysctl_resource_kman = 304, - sysctl_resource_gpio = 305, - sysctl_resource_hdma = 306, - sysctl_resource_xpi0 = 307, - sysctl_resource_usb0 = 308, - sysctl_resource_ref0 = 309, - sysctl_resource_ref1 = 310, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ - sysctl_resource_mode_force_on, /*!< Force the resource clock on */ - sysctl_resource_mode_force_off, /*!< Force the resource clock off */ -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, - clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, - clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, - clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, - clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, - clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, - clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, - clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, - clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, - clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, - clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, - clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, - clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, - clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, - clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, - clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, - clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, - clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, - clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, - clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, - clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, - clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, - clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, - clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, - clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, - clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, - clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, - clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, - clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, - clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, - clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, - clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, - - clock_node_adc_start, - clock_node_adc0 = clock_node_adc_start, - clock_node_adc1, - - clock_node_dac_start, - clock_node_dac0 = clock_node_dac_start, - clock_node_dac1, - clock_node_end, - - clock_node_core_start = 0xfc, - clock_node_cpu0 = clock_node_core_start, - clock_node_axi, - clock_node_ahb, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll0_clk1 = 2, - clock_source_pll0_clk2 = 3, - clock_source_pll1_clk0 = 4, - clock_source_pll1_clk1 = 5, - clock_source_pll1_clk2 = 6, - clock_source_pll1_clk3 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC/I2S clock sources - */ -typedef enum { - clock_source_adc_ana_clock = 0, - clock_source_adc_ahb_clock = 1, - clock_source_adc_clk_end, -} clock_source_adc_t; - -/** - * @brief DAC clock sources - */ -typedef enum { - clock_source_dac_ana_clock = 0, - clock_source_dac_ahb_clock = 1, - clock_source_dac_clk_end, -} clock_source_dac_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -typedef enum { - monitor_target_clk_32k = 1, - monitor_target_clk_irc24m = 2, - monitor_target_clk_xtal_24m = 3, - monitor_target_clk_usb0_phy = 4, - monitor_target_clk0_osc0 = 20, - monitor_target_clk0_pll0 = 21, - monitor_target_clk0_pll1 = 22, - monitor_target_clk0_pll2 = 23, - monitor_target_clk1_pll0 = 24, - monitor_target_clk1_pll1 = 25, - monitor_target_clk1_pll2 = 26, - monitor_target_clk1_pll3 = 27, - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_can0 = 130, - monitor_target_clk_top_can1 = 131, - monitor_target_clk_top_can2 = 132, - monitor_target_clk_top_can3 = 133, - monitor_target_clk_top_lin0 = 134, - monitor_target_clk_top_lin1 = 135, - monitor_target_clk_top_lin2 = 136, - monitor_target_clk_top_lin3 = 137, - monitor_target_clk_top_gptmr0 = 138, - monitor_target_clk_top_gptmr1 = 139, - monitor_target_clk_top_gptmr2 = 140, - monitor_target_clk_top_gptmr3 = 141, - monitor_target_clk_top_i2c0 = 142, - monitor_target_clk_top_i2c1 = 143, - monitor_target_clk_top_i2c2 = 144, - monitor_target_clk_top_i2c3 = 145, - monitor_target_clk_top_spi0 = 146, - monitor_target_clk_top_spi1 = 147, - monitor_target_clk_top_spi2 = 148, - monitor_target_clk_top_spi3 = 149, - monitor_target_clk_top_uart0 = 150, - monitor_target_clk_top_uart1 = 151, - monitor_target_clk_top_uart2 = 152, - monitor_target_clk_top_uart3 = 153, - monitor_target_clk_top_uart4 = 154, - monitor_target_clk_top_uart5 = 155, - monitor_target_clk_top_uart6 = 156, - monitor_target_clk_top_uart7 = 157, - monitor_target_clk_top_xpi0 = 158, - monitor_target_clk_top_ana0 = 159, - monitor_target_clk_top_ana1 = 160, - monitor_target_clk_top_ana2 = 161, - monitor_target_clk_top_ana3 = 162, - monitor_target_clk_top_ref0 = 163, - monitor_target_clk_top_ref1 = 164, -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | - (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit_high, - uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = - (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | - SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Disable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, - uint8_t cpu_index, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - uint8_t set_mask = 0x1; - if (domain < sysctl_retention_domain_xtal24m) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Retain target domain for specific CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); -} - -/** - * @brief Check if cpu clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; -} - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Preserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Unpreserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Get target CPU0 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 0, status_index); -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index, - uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Check CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); -} - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Disable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); -} - - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Lock CPU gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); -} - -/** - * @brief Lock CPU lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 0); -} - -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) -{ - ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); -} - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 0, mode); -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Get CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); -} - -/** - * @brief Get CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 0); -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); - -/** - * @brief Configure CPU domain clock - * @param ptr SYSCTL base address - * @param source clock source to be used - * @param cpu_div CPU divider - * @param ahb_sub_div AHB BUS divider based on divided CPU clock - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, uint32_t ahb_sub_div); - -/** - * @brief Set ADC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); - - -/** - * @brief Set DAC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source); - - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); - -/** - * @brief Save data to GPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved from GPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_trgm_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_trgm_soc_drv.h deleted file mode 100644 index 29143932dc9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_trgm_soc_drv.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_TRGM_SOC_DRV_H -#define HPM_TRGM_SOC_DRV_H - -#include "hpm_soc.h" -#include "hpm_trgm_regs.h" - -typedef enum { - trgm_adc_matrix_output_to_qei0_adc0 = 0, - trgm_adc_matrix_output_to_qei0_adc1 = 1, - trgm_adc_matrix_output_to_qei1_adc0 = 2, - trgm_adc_matrix_output_to_qei1_adc1 = 3, -} trgm_adc_matrix_out_t; - -typedef enum { - trgm_adc_matrix_in_from_adc0 = 0, - trgm_adc_matrix_in_from_adc1 = 1, - trgm_adc_matrix_in_from_rdc_adc0 = 2, - trgm_adc_matrix_in_from_rdc_adc1 = 3, -} trgm_adc_matrix_in_t; - -typedef enum { - trgm_dac_matrix_output_to_acmp0 = 0, - trgm_dac_matrix_output_to_acmp1 = 1, - trgm_dac_matrix_output_to_dac0 = 2, - trgm_dac_matrix_output_to_dac1 = 3, -} trgm_dac_matrix_out_t; - -typedef enum { - trgm_dac_matrix_in_from_qeo0_dac0 = 0, - trgm_dac_matrix_in_from_qeo0_dac1 = 1, - trgm_dac_matrix_in_from_qeo0_dac2 = 2, - trgm_dac_matrix_in_from_qeo1_dac0 = 3, - trgm_dac_matrix_in_from_qeo1_dac1 = 4, - trgm_dac_matrix_in_from_qeo1_dac2 = 5, - trgm_dac_matrix_in_from_rdc_dac0 = 6, - trgm_dac_matrix_in_from_rdc_dac1 = 7, -} trgm_dac_matrix_in_t; - -typedef enum { - trgm_pos_matrix_output_to_sei_pos0 = 0, - trgm_pos_matrix_output_to_sei_pos1 = 1, - trgm_pos_matrix_output_to_mmc0 = 2, - trgm_pos_matrix_output_to_mmc1 = 3, - trgm_pos_matrix_output_to_qeo0 = 4, - trgm_pos_matrix_output_to_qeo1 = 5, -} trgm_pos_matrix_out_t; - -typedef enum { - trgm_pos_matrix_in_from_sei_pos0 = 0, - trgm_pos_matrix_in_from_sei_pos1 = 1, - trgm_pos_matrix_in_from_qei0 = 2, - trgm_pos_matrix_in_from_qei1 = 3, - trgm_pos_matrix_in_from_mmc0_pos0 = 4, - trgm_pos_matrix_in_from_mmc0_pos1 = 5, - trgm_pos_matrix_in_from_mmc1_pos0 = 6, - trgm_pos_matrix_in_from_mmc1_pos1 = 7, -} trgm_pos_matrix_in_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -static inline void trgm_adc_matrix_config(TRGM_Type *ptr, trgm_adc_matrix_out_t consumer, trgm_adc_matrix_in_t src, bool inv_val) -{ - if (inv_val) { - ptr->ADC_MATRIX_SEL |= 0x80 << consumer * 8U; - } else { - ptr->ADC_MATRIX_SEL &= ~(0x80 << consumer * 8U); - } - ptr->ADC_MATRIX_SEL &= ~(0x7f << consumer * 8U); - ptr->ADC_MATRIX_SEL |= src << consumer * 8U; -} - -static inline void trgm_dac_matrix_config(TRGM_Type *ptr, trgm_dac_matrix_out_t consumer, trgm_dac_matrix_in_t src, bool inv_val) -{ - if (inv_val) { - ptr->DAC_MATRIX_SEL |= 0x80 << consumer * 8U; - } else { - ptr->DAC_MATRIX_SEL &= ~(0x80 << consumer * 8U); - } - ptr->DAC_MATRIX_SEL &= ~(0x7f << consumer * 8U); - ptr->DAC_MATRIX_SEL |= src << consumer * 8U; -} - -static inline void trgm_pos_matrix_config(TRGM_Type *ptr, trgm_pos_matrix_out_t consumer, trgm_pos_matrix_in_t src, bool inv_val) -{ - uint8_t index = consumer / 4U; - uint8_t offset = (consumer % 4U) * 8U; - - if (index == 0) { - if (inv_val) { - ptr->POS_MATRIX_SEL0 |= 0x80 << offset; - } else { - ptr->POS_MATRIX_SEL0 &= ~(0x80 << offset); - } - ptr->POS_MATRIX_SEL0 &= ~(0x7f << offset); - ptr->POS_MATRIX_SEL0 |= src << offset; - } else if (index == 1) { - if (inv_val) { - ptr->POS_MATRIX_SEL1 |= 0x80 << offset; - } else { - ptr->POS_MATRIX_SEL1 &= ~(0x80 << offset); - } - ptr->POS_MATRIX_SEL1 &= ~(0x7f << offset); - ptr->POS_MATRIX_SEL1 |= src << offset; - } -} - -#if defined(__cplusplus) -} -#endif - -#endif /* HPM_TRGM_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_trgmmux_src.h deleted file mode 100644 index 42eed680bb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/hpm_trgmmux_src.h +++ /dev/null @@ -1,377 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGMMUX_SRC_H -#define HPM_TRGMMUX_SRC_H - -/* trgm0_input mux definitions */ -#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x2UL) -#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x3UL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x6UL) -#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x7UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0xDUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0xEUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0xFUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x10UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x11UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x12UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x13UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x14UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x15UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x16UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x17UL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x18UL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x19UL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x1AUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x1BUL) -#define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_0 (0x1CUL) -#define HPM_TRGM0_INPUT_SRC_MMC0_TRGO_1 (0x1DUL) -#define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_0 (0x1EUL) -#define HPM_TRGM0_INPUT_SRC_MMC1_TRGO_1 (0x1FUL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_0 (0x20UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_1 (0x21UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_2 (0x22UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_3 (0x23UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_4 (0x24UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_5 (0x25UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_6 (0x26UL) -#define HPM_TRGM0_INPUT_SRC_QEO0_TRGO_7 (0x27UL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_0 (0x28UL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_1 (0x29UL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_2 (0x2AUL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_3 (0x2BUL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_4 (0x2CUL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_5 (0x2DUL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_6 (0x2EUL) -#define HPM_TRGM0_INPUT_SRC_QEO1_TRGO_7 (0x2FUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x30UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x31UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x32UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x33UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x34UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x35UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x36UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x37UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH8REF (0x38UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH9REF (0x39UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH10REF (0x3AUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH11REF (0x3BUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH12REF (0x3CUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH13REF (0x3DUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH14REF (0x3EUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CH15REF (0x3FUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x40UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x41UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x42UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x43UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x44UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x45UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x46UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x47UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x48UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x49UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x4AUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x4BUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x4CUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x4DUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x4EUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x4FUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x50UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x51UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x52UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x53UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x54UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x55UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x56UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x57UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x58UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x59UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x5AUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x5BUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x5CUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x5DUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x5EUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x5FUL) -#define HPM_TRGM0_INPUT_SRC_RDC_TRGO_0 (0x60UL) -#define HPM_TRGM0_INPUT_SRC_RDC_TRGO_1 (0x61UL) -#define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0x62UL) -#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x63UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x64UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x65UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x66UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x67UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x68UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x69UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x6AUL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x6BUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_FAULT0 (0x6CUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_FAULT1 (0x6DUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_FAULT0 (0x6EUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_FAULT1 (0x6FUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x70UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x71UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN2 (0x72UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN3 (0x73UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN4 (0x74UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN5 (0x75UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN6 (0x76UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN7 (0x77UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0x78UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0x79UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN2 (0x7AUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN3 (0x7BUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN4 (0x7CUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN5 (0x7DUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN6 (0x7EUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN7 (0x7FUL) - -/* trgm0_output mux definitions */ -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_0 (0x0UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_1 (0x1UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_2 (0x2UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_3 (0x3UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_4 (0x4UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_5 (0x5UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_6 (0x6UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP0_7 (0x7UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_0 (0x8UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_1 (0x9UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_2 (0xAUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_3 (0xBUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_4 (0xCUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_5 (0xDUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_6 (0xEUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT2OPAMP1_7 (0xFUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x10UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x11UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x12UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x13UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x14UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x15UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x16UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x17UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x18UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x19UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x1AUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x1BUL) -#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN (0x1CUL) -#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN (0x1DUL) -#define HPM_TRGM0_OUTPUT_SRC_DAC0_BUFTRG (0x1EUL) -#define HPM_TRGM0_OUTPUT_SRC_DAC1_BUFTRG (0x1FUL) -#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x20UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x21UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x22UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x23UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x24UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x25UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x26UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x27UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x28UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x29UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x2AUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x2BUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x2CUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x2DUL) -#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP (0x2EUL) -#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP (0x2FUL) -#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x30UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x31UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x32UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x33UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x34UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x35UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x36UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x37UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x38UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x39UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x3AUL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x3BUL) -#define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN0 (0x3CUL) -#define HPM_TRGM0_OUTPUT_SRC_MMC0_TRIG_IN1 (0x3DUL) -#define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN0 (0x3EUL) -#define HPM_TRGM0_OUTPUT_SRC_MMC1_TRIG_IN1 (0x3FUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x40UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x41UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x42UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x43UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x44UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x45UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x46UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x47UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x48UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x49UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x4AUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x4BUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x4CUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x4DUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x4EUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x4FUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x50UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x51UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x52UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x53UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x54UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x55UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x56UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x57UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x58UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x59UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x5AUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x5BUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x5CUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x5DUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x5EUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x5FUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x60UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x61UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x62UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x63UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x64UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x65UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x66UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x67UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN8 (0x68UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN9 (0x69UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN10 (0x6AUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN11 (0x6BUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN12 (0x6CUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN13 (0x6DUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN14 (0x6EUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM_IN15 (0x6FUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0x70UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x71UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0x72UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x73UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x74UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x75UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCI (0x76UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_FRCSYNCI (0x77UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_SYNCI (0x78UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x79UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI0 (0x7AUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_FAULTI1 (0x7BUL) -#define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN0 (0x7CUL) -#define HPM_TRGM0_OUTPUT_SRC_RDC_TRIG_IN1 (0x7DUL) -#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0x7EUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x7FUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x80UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x81UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x82UL) -#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0x83UL) -#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0x84UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0x85UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0x86UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0x87UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0x88UL) - -/* trgm0_filter mux definitions */ -#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN0 (0x10UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN1 (0x11UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN2 (0x12UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN3 (0x13UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN4 (0x14UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN5 (0x15UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN6 (0x16UL) -#define HPM_TRGM0_FILTER_SRC_TRGM_IN7 (0x17UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_FAULT0 (0x18UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_FAULT1 (0x19UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_FAULT0 (0x1AUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_FAULT1 (0x1BUL) - -/* trgm0_dma mux definitions */ -#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) -#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) -#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) -#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP0 (0x1BUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP1 (0x1CUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP2 (0x1DUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP3 (0x1EUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP4 (0x1FUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP5 (0x20UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP6 (0x21UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP7 (0x22UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP8 (0x23UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP9 (0x24UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP10 (0x25UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP11 (0x26UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP12 (0x27UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP13 (0x28UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP14 (0x29UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP15 (0x2AUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP16 (0x2BUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP17 (0x2CUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP18 (0x2DUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP19 (0x2EUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP20 (0x2FUL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP21 (0x30UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP22 (0x31UL) -#define HPM_TRGM0_DMA_SRC_PWM1_CMP23 (0x32UL) -#define HPM_TRGM0_DMA_SRC_PWM1_RLD (0x33UL) -#define HPM_TRGM0_DMA_SRC_PWM1_HALFRLD (0x34UL) -#define HPM_TRGM0_DMA_SRC_PWM1_XRLD (0x35UL) -#define HPM_TRGM0_DMA_SRC_QEI0 (0x36UL) -#define HPM_TRGM0_DMA_SRC_QEI1 (0x37UL) -#define HPM_TRGM0_DMA_SRC_MMC0 (0x38UL) -#define HPM_TRGM0_DMA_SRC_MMC1 (0x39UL) -#define HPM_TRGM0_DMA_SRC_SEI0 (0x3AUL) -#define HPM_TRGM0_DMA_SRC_SEI1 (0x3BUL) -#define HPM_TRGM0_DMA_SRC_TRGM0 (0x3CUL) -#define HPM_TRGM0_DMA_SRC_TRGM1 (0x3DUL) - - - -#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/soc_modules.list deleted file mode 100644 index 6370a0e6bbb..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/soc_modules.list +++ /dev/null @@ -1,52 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_CRC=y -HPMSOC_HAS_HPMSDK_TSNS=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_EWDG=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMAV2=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_MCAN=y -HPMSOC_HAS_HPMSDK_PTPC=y -HPMSOC_HAS_HPMSDK_QEIV2=y -HPMSOC_HAS_HPMSDK_QEO=y -HPMSOC_HAS_HPMSDK_MMC=y -HPMSOC_HAS_HPMSDK_PWM=y -HPMSOC_HAS_HPMSDK_RDC=y -HPMSOC_HAS_HPMSDK_PLB=y -HPMSOC_HAS_HPMSDK_SYNT=y -HPMSOC_HAS_HPMSDK_SEI=y -HPMSOC_HAS_HPMSDK_TRGM=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_SDP=y -HPMSOC_HAS_HPMSDK_SEC=y -HPMSOC_HAS_HPMSDK_MON=y -HPMSOC_HAS_HPMSDK_RNG=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_DAC=y -HPMSOC_HAS_HPMSDK_OPAMP=y -HPMSOC_HAS_HPMSDK_ACMP=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_PLLCTLV2=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_PDGO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/system.c deleted file mode 100644 index 3ea422c42ea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/system.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif - -#ifdef USE_S_MODE_IRQ - disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#else - disable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - - disable_irq_from_intc(); -#ifdef USE_S_MODE_IRQ - disable_s_irq_from_intc(); -#endif - - enable_plic_feature(); - enable_irq_from_intc(); - -#ifdef USE_S_MODE_IRQ - delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); - enable_s_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#endif -#else -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash.ld deleted file mode 100644 index ec881b8787c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash.ld +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index 2f7aa456866..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,277 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash_xip.ld deleted file mode 100644 index 554e7aacc58..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/flash_xip.ld +++ /dev/null @@ -1,295 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xf0400000, LENGTH = 32K -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/ram.ld deleted file mode 100644 index 01c381d9677..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/ram.ld +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > DLM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/start.S deleted file mode 100644 index 2f803b378aa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/gcc/start.S +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - la tp, __thread_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/flash_uf2.icf deleted file mode 100644 index 460c9efbb4b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { - block RW_DATA - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/flash_xip.icf deleted file mode 100644 index 1a15d12848d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { - block RW_DATA - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .nor_cfg_option, - section .boot_header, - section .fw_info_table, - section .dc_info - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/ram.icf deleted file mode 100644 index c8c79f20fe8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/ram.icf +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { - block RW_DATA - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/startup.s deleted file mode 100644 index 073436a68d9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/iar/startup.s +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/reset.c deleted file mode 100644 index 312a82688af..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash.icf deleted file mode 100644 index d2ed190b152..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash.icf +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 3e0a987229b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash_xip.icf deleted file mode 100644 index 5c33e331637..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xf0400000 size 32k]; /* AHB_SRAM */ - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/ram.icf deleted file mode 100644 index b5f384d7204..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/ram.icf +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AHB_SRAM = [from 0xF0400000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in DLM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info}; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/startup.s deleted file mode 100644 index 8a7036e137d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/segger/startup.s +++ /dev/null @@ -1,419 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/trap.c deleted file mode 100644 index 66e5dd580f9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/trap.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ -#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ -#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ -#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ -#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ -#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : : "t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : : "a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : : "r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/vectors.h deleted file mode 100644 index 4778d86827d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/HPM5361/toolchains/vectors.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(9) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_HANDLER 8 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_HANDLER 9 /* Reserved */ - IRQ_DEFAULT_HANDLER 10 /* Reserved */ - IRQ_DEFAULT_HANDLER 11 /* Reserved */ - IRQ_DEFAULT_HANDLER 12 /* Reserved */ - IRQ_DEFAULT_HANDLER 13 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* UART4 IRQ handler */ - IRQ_DEFAULT_HANDLER 18 /* UART5 IRQ handler */ - IRQ_DEFAULT_HANDLER 19 /* UART6 IRQ handler */ - IRQ_DEFAULT_HANDLER 20 /* UART7 IRQ handler */ - IRQ_DEFAULT_HANDLER 21 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 22 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 23 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 24 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* TSNS IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* EWDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* EWDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 36 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 37 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_HANDLER 38 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_HANDLER 39 /* PTPC IRQ handler */ - IRQ_DEFAULT_HANDLER 40 /* PWM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 41 /* QEI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 42 /* SEI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 43 /* MMC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 44 /* TRGMUX0 IRQ handler */ - IRQ_DEFAULT_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 46 /* QEI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 47 /* SEI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 48 /* MMC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 49 /* TRGMUX1 IRQ handler */ - IRQ_DEFAULT_HANDLER 50 /* RDC IRQ handler */ - IRQ_DEFAULT_HANDLER 51 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* SDP IRQ handler */ - IRQ_DEFAULT_HANDLER 54 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* RNG IRQ handler */ - IRQ_DEFAULT_HANDLER 57 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 60 /* DAC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 61 /* DAC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 62 /* ACMP_0 IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* ACMP_1 IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* PEWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* PAD_WAKEUP IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* DEBUG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* DEBUG1 IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(9) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 7 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 8 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 9 /* Reserved */ - IRQ_HANDLER 10 /* Reserved */ - IRQ_HANDLER 11 /* Reserved */ - IRQ_HANDLER 12 /* Reserved */ - IRQ_HANDLER 13 /* UART0 IRQ handler */ - IRQ_HANDLER 14 /* UART1 IRQ handler */ - IRQ_HANDLER 15 /* UART2 IRQ handler */ - IRQ_HANDLER 16 /* UART3 IRQ handler */ - IRQ_HANDLER 17 /* UART4 IRQ handler */ - IRQ_HANDLER 18 /* UART5 IRQ handler */ - IRQ_HANDLER 19 /* UART6 IRQ handler */ - IRQ_HANDLER 20 /* UART7 IRQ handler */ - IRQ_HANDLER 21 /* I2C0 IRQ handler */ - IRQ_HANDLER 22 /* I2C1 IRQ handler */ - IRQ_HANDLER 23 /* I2C2 IRQ handler */ - IRQ_HANDLER 24 /* I2C3 IRQ handler */ - IRQ_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_HANDLER 29 /* TSNS IRQ handler */ - IRQ_HANDLER 30 /* MBX0A IRQ handler */ - IRQ_HANDLER 31 /* MBX0B IRQ handler */ - IRQ_HANDLER 32 /* EWDG0 IRQ handler */ - IRQ_HANDLER 33 /* EWDG1 IRQ handler */ - IRQ_HANDLER 34 /* HDMA IRQ handler */ - IRQ_HANDLER 35 /* MCAN0 IRQ handler */ - IRQ_HANDLER 36 /* MCAN1 IRQ handler */ - IRQ_HANDLER 37 /* MCAN2 IRQ handler */ - IRQ_HANDLER 38 /* MCAN3 IRQ handler */ - IRQ_HANDLER 39 /* PTPC IRQ handler */ - IRQ_HANDLER 40 /* PWM0 IRQ handler */ - IRQ_HANDLER 41 /* QEI0 IRQ handler */ - IRQ_HANDLER 42 /* SEI0 IRQ handler */ - IRQ_HANDLER 43 /* MMC0 IRQ handler */ - IRQ_HANDLER 44 /* TRGMUX0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* QEI1 IRQ handler */ - IRQ_HANDLER 47 /* SEI1 IRQ handler */ - IRQ_HANDLER 48 /* MMC1 IRQ handler */ - IRQ_HANDLER 49 /* TRGMUX1 IRQ handler */ - IRQ_HANDLER 50 /* RDC IRQ handler */ - IRQ_HANDLER 51 /* USB0 IRQ handler */ - IRQ_HANDLER 52 /* XPI0 IRQ handler */ - IRQ_HANDLER 53 /* SDP IRQ handler */ - IRQ_HANDLER 54 /* PSEC IRQ handler */ - IRQ_HANDLER 55 /* SECMON IRQ handler */ - IRQ_HANDLER 56 /* RNG IRQ handler */ - IRQ_HANDLER 57 /* FUSE IRQ handler */ - IRQ_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_HANDLER 60 /* DAC0 IRQ handler */ - IRQ_HANDLER 61 /* DAC1 IRQ handler */ - IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ - IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ - IRQ_HANDLER 64 /* SYSCTL IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PTMR IRQ handler */ - IRQ_HANDLER 67 /* PUART IRQ handler */ - IRQ_HANDLER 68 /* PEWDG IRQ handler */ - IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 5 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 6 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 7 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 8 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 9 /* Reserved */ - IRQ_HANDLER 10 /* Reserved */ - IRQ_HANDLER 11 /* Reserved */ - IRQ_HANDLER 12 /* Reserved */ - IRQ_HANDLER 13 /* UART0 IRQ handler */ - IRQ_HANDLER 14 /* UART1 IRQ handler */ - IRQ_HANDLER 15 /* UART2 IRQ handler */ - IRQ_HANDLER 16 /* UART3 IRQ handler */ - IRQ_HANDLER 17 /* UART4 IRQ handler */ - IRQ_HANDLER 18 /* UART5 IRQ handler */ - IRQ_HANDLER 19 /* UART6 IRQ handler */ - IRQ_HANDLER 20 /* UART7 IRQ handler */ - IRQ_HANDLER 21 /* I2C0 IRQ handler */ - IRQ_HANDLER 22 /* I2C1 IRQ handler */ - IRQ_HANDLER 23 /* I2C2 IRQ handler */ - IRQ_HANDLER 24 /* I2C3 IRQ handler */ - IRQ_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_HANDLER 29 /* TSNS IRQ handler */ - IRQ_HANDLER 30 /* MBX0A IRQ handler */ - IRQ_HANDLER 31 /* MBX0B IRQ handler */ - IRQ_HANDLER 32 /* EWDG0 IRQ handler */ - IRQ_HANDLER 33 /* EWDG1 IRQ handler */ - IRQ_HANDLER 34 /* HDMA IRQ handler */ - IRQ_HANDLER 35 /* MCAN0 IRQ handler */ - IRQ_HANDLER 36 /* MCAN1 IRQ handler */ - IRQ_HANDLER 37 /* MCAN2 IRQ handler */ - IRQ_HANDLER 38 /* MCAN3 IRQ handler */ - IRQ_HANDLER 39 /* PTPC IRQ handler */ - IRQ_HANDLER 40 /* PWM0 IRQ handler */ - IRQ_HANDLER 41 /* QEI0 IRQ handler */ - IRQ_HANDLER 42 /* SEI0 IRQ handler */ - IRQ_HANDLER 43 /* MMC0 IRQ handler */ - IRQ_HANDLER 44 /* TRGMUX0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* QEI1 IRQ handler */ - IRQ_HANDLER 47 /* SEI1 IRQ handler */ - IRQ_HANDLER 48 /* MMC1 IRQ handler */ - IRQ_HANDLER 49 /* TRGMUX1 IRQ handler */ - IRQ_HANDLER 50 /* RDC IRQ handler */ - IRQ_HANDLER 51 /* USB0 IRQ handler */ - IRQ_HANDLER 52 /* XPI0 IRQ handler */ - IRQ_HANDLER 53 /* SDP IRQ handler */ - IRQ_HANDLER 54 /* PSEC IRQ handler */ - IRQ_HANDLER 55 /* SECMON IRQ handler */ - IRQ_HANDLER 56 /* RNG IRQ handler */ - IRQ_HANDLER 57 /* FUSE IRQ handler */ - IRQ_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_HANDLER 60 /* DAC0 IRQ handler */ - IRQ_HANDLER 61 /* DAC1 IRQ handler */ - IRQ_HANDLER 62 /* ACMP_0 IRQ handler */ - IRQ_HANDLER 63 /* ACMP_1 IRQ handler */ - IRQ_HANDLER 64 /* SYSCTL IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PTMR IRQ handler */ - IRQ_HANDLER 67 /* PUART IRQ handler */ - IRQ_HANDLER 68 /* PEWDG IRQ handler */ - IRQ_HANDLER 69 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 70 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 71 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 72 /* DEBUG1 IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_acmp_regs.h deleted file mode 100644 index 1f67819e312..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_acmp_regs.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ACMP_H -#define HPM_ACMP_H - -typedef struct { - struct { - __RW uint32_t CFG; /* 0x0: Configure Register */ - __RW uint32_t DACCFG; /* 0x4: DAC configure register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t SR; /* 0x10: Status register */ - __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */ - __RW uint32_t DMAEN; /* 0x18: DMA request enable register */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - } CHANNEL[2]; -} ACMP_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CFG */ -/* - * HYST (RW) - * - * This bitfield configure the comparator hysteresis. - * 00: Hysteresis level 0 - * 01: Hysteresis level 1 - * 10: Hysteresis level 2 - * 11: Hysteresis level 3 - */ -#define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) -#define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) -#define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) -#define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) - -/* - * DACEN (RW) - * - * This bit enable the comparator internal DAC - * 0: DAC disabled - * 1: DAC enabled - */ -#define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) -#define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) -#define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) -#define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) - -/* - * HPMODE (RW) - * - * This bit enable the comparator high performance mode. - * 0: HP mode disabled - * 1: HP mode enabled - */ -#define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) -#define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) -#define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) -#define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) - -/* - * CMPEN (RW) - * - * This bit enable the comparator. - * 0: ACMP disabled - * 1: ACMP enabled - */ -#define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) -#define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) -#define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) -#define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) - -/* - * MINSEL (RW) - * - * PIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) -#define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) -#define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) -#define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) - -/* - * DAC_TRIG_EN (RW) - * - * if set, the dac value is from moto system when valid - * if clr, use dac_cfg value - */ -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK (0x800000UL) -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT (23U) -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) >> ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) - -/* - * PINSEL (RW) - * - * MIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) -#define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) -#define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) -#define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) - -/* - * CMPOEN (RW) - * - * This bit enable the comparator output on pad. - * 0: ACMP output disabled - * 1: ACMP output enabled - */ -#define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) -#define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) -#define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) -#define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) - -/* - * FLTBYPS (RW) - * - * This bit bypass the comparator output digital filter. - * 0: The ACMP output need pass digital filter - * 1: The ACMP output digital filter is bypassed. - */ -#define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) -#define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) -#define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) -#define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) - -/* - * WINEN (RW) - * - * This bit enable the comparator window mode. - * 0: Window mode is disabled - * 1: Window mode is enabled - */ -#define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) -#define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) -#define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) -#define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) - -/* - * OPOL (RW) - * - * The output polarity control bit. - * 0: The ACMP output remain un-changed. - * 1: The ACMP output is inverted. - */ -#define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) -#define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) -#define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) -#define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) - -/* - * FLTMODE (RW) - * - * This bitfield define the ACMP output digital filter mode: - * 000-bypass - * 100-change immediately; - * 101-change after filter; - * 110-stalbe low; - * 111-stable high - */ -#define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) -#define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) -#define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) -#define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) - -/* - * SYNCEN (RW) - * - * This bit enable the comparator output synchronization. - * 0: ACMP output not synchronized with ACMP clock. - * 1: ACMP output synchronized with ACMP clock. - */ -#define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) -#define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) -#define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) -#define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) - -/* - * FLTLEN (RW) - * - * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - */ -#define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) -#define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) -#define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) -#define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DACCFG */ -/* - * DACCFG (RW) - * - * 8bit DAC digital value output to analog block - */ -#define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) -#define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) -#define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) -#define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: SR */ -/* - * FEDGF (RW) - * - * Output falling edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) -#define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) -#define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) -#define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) - -/* - * REDGF (RW) - * - * Output rising edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) -#define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) -#define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) -#define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: IRQEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DMAEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) - - - -/* CHANNEL register group index macro definition */ -#define ACMP_CHANNEL_CHN0 (0UL) -#define ACMP_CHANNEL_CHN1 (1UL) - - -#endif /* HPM_ACMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_adc16_regs.h deleted file mode 100644 index 8b798b4e708..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_adc16_regs.h +++ /dev/null @@ -1,1027 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC16_H -#define HPM_ADC16_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ - __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint32_t SEQ_WR_ADDR; /* 0x808: */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __RW uint32_t SEQ_HIGH_CFG; /* 0x850: */ - __R uint8_t RESERVED3[940]; /* 0x854 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[16]; - __R uint8_t RESERVED4[768]; /* 0xD00 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */ - __R uint8_t RESERVED5[196]; /* 0x1040 - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __R uint8_t RESERVED8[12]; /* 0x1204 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ - __R uint8_t RESERVED9[492]; /* 0x1214 - 0x13FF: Reserved */ - __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ - __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ - __R uint8_t RESERVED10[24]; /* 0x1448 - 0x145F: Reserved */ - __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ -} ADC16_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) -#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC16_CONFIG_INTEN3_SHIFT (29U) -#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) -#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC16_CONFIG_CHAN3_SHIFT (24U) -#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) -#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC16_CONFIG_INTEN2_SHIFT (21U) -#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) -#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC16_CONFIG_CHAN2_SHIFT (16U) -#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) -#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC16_CONFIG_INTEN1_MASK (0x2000U) -#define ADC16_CONFIG_INTEN1_SHIFT (13U) -#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) -#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC16_CONFIG_CHAN1_SHIFT (8U) -#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) -#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) - -/* - * QUEUE_EN (RW) - * - * preemption queue enable control - */ -#define ADC16_CONFIG_QUEUE_EN_MASK (0x40U) -#define ADC16_CONFIG_QUEUE_EN_SHIFT (6U) -#define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK) -#define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC16_CONFIG_INTEN0_MASK (0x20U) -#define ADC16_CONFIG_INTEN0_SHIFT (5U) -#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) -#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC16_CONFIG_CHAN0_MASK (0x1FU) -#define ADC16_CONFIG_CHAN0_SHIFT (0U) -#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) -#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC16_BUS_RESULT_VALID_SHIFT (16U) -#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * BUS_MODE_EN (RW) - * - * bus mode enable - */ -#define ADC16_BUF_CFG0_BUS_MODE_EN_MASK (0x2U) -#define ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT (1U) -#define ADC16_BUF_CFG0_BUS_MODE_EN_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) -#define ADC16_BUF_CFG0_BUS_MODE_EN_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) >> ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) - -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) -#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) -#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) -#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_WR_ADDR */ -/* - * SEQ_WR_POINTER (RO) - * - * HW update this field after each dma write, it indicate the next dma write pointer. - * dma write address is (tar_addr+seq_wr_pointer)*4 - */ -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFFFFUL) -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register: SEQ_HIGH_CFG */ -/* - * STOP_POS_HIGH (RW) - * - */ -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK (0xFFF000UL) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT (12U) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) - -/* - * BUF_LEN_HIGH (RW) - * - */ -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK (0xFFFU) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT (0U) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample clock number - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); - * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - */ -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* - * PORT3_REALTIME (RW) - * - * set to enable trg queue stop other queues - */ -#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) -#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) -#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) -#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) -#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) -#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) -#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) -#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_STS_WDOG_MASK (0xFFFFU) -#define ADC16_INT_STS_WDOG_SHIFT (0U) -#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) -#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) -#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) -#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) -#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) -#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) -#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) -#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_EN_WDOG_MASK (0xFFFFU) -#define ADC16_INT_EN_WDOG_SHIFT (0U) -#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) -#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * MOTO_EN (RW) - * - * "set to enable moto_soc and moto_valid. - * Should use AHB clock for adc, this bit can be used avoid async output" - */ -#define ADC16_ANA_CTRL0_MOTO_EN_MASK (0x80000000UL) -#define ADC16_ANA_CTRL0_MOTO_EN_SHIFT (31U) -#define ADC16_ANA_CTRL0_MOTO_EN_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_MOTO_EN_SHIFT) & ADC16_ANA_CTRL0_MOTO_EN_MASK) -#define ADC16_ANA_CTRL0_MOTO_EN_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_MOTO_EN_MASK) >> ADC16_ANA_CTRL0_MOTO_EN_SHIFT) - -/* - * ADC_CLK_ON (RW) - * - * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. - * MUST set clock_period to 0 or 1 for adc16 reg access - */ -#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) -#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC16_ANA_STATUS_CALON_MASK (0x80U) -#define ADC16_ANA_STATUS_CALON_SHIFT (7U) -#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) -#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) - -/* Bitfield definition for register array: ADC16_PARAMS */ -/* - * PARAM_VAL (RW) - * - */ -#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) -#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG0 */ -/* - * REG_EN (RW) - * - * set to enable regulator - */ -#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) -#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) -#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) -#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) - -/* - * BANDGAP_EN (RW) - * - * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - */ -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) - -/* - * CAL_AVG_CFG (RW) - * - * for average the calibration result. - * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; - * 4- 16 loops; 5-32 loops; others reserved - */ -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) - -/* - * PREEMPT_EN (RW) - * - * set to enable preemption feature - */ -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) - -/* - * CONV_PARAM (RW) - * - * conversion parameter - */ -#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG1 */ -/* - * COV_END_CNT (RW) - * - * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number+1). - */ -#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC16_CONFIG_TRG0A (0UL) -#define ADC16_CONFIG_TRG0B (1UL) -#define ADC16_CONFIG_TRG0C (2UL) -#define ADC16_CONFIG_TRG1A (3UL) -#define ADC16_CONFIG_TRG1B (4UL) -#define ADC16_CONFIG_TRG1C (5UL) -#define ADC16_CONFIG_TRG2A (6UL) -#define ADC16_CONFIG_TRG2B (7UL) -#define ADC16_CONFIG_TRG2C (8UL) -#define ADC16_CONFIG_TRG3A (9UL) -#define ADC16_CONFIG_TRG3B (10UL) -#define ADC16_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC16_BUS_RESULT_CHN0 (0UL) -#define ADC16_BUS_RESULT_CHN1 (1UL) -#define ADC16_BUS_RESULT_CHN2 (2UL) -#define ADC16_BUS_RESULT_CHN3 (3UL) -#define ADC16_BUS_RESULT_CHN4 (4UL) -#define ADC16_BUS_RESULT_CHN5 (5UL) -#define ADC16_BUS_RESULT_CHN6 (6UL) -#define ADC16_BUS_RESULT_CHN7 (7UL) -#define ADC16_BUS_RESULT_CHN8 (8UL) -#define ADC16_BUS_RESULT_CHN9 (9UL) -#define ADC16_BUS_RESULT_CHN10 (10UL) -#define ADC16_BUS_RESULT_CHN11 (11UL) -#define ADC16_BUS_RESULT_CHN12 (12UL) -#define ADC16_BUS_RESULT_CHN13 (13UL) -#define ADC16_BUS_RESULT_CHN14 (14UL) -#define ADC16_BUS_RESULT_CHN15 (15UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC16_SEQ_QUE_CFG0 (0UL) -#define ADC16_SEQ_QUE_CFG1 (1UL) -#define ADC16_SEQ_QUE_CFG2 (2UL) -#define ADC16_SEQ_QUE_CFG3 (3UL) -#define ADC16_SEQ_QUE_CFG4 (4UL) -#define ADC16_SEQ_QUE_CFG5 (5UL) -#define ADC16_SEQ_QUE_CFG6 (6UL) -#define ADC16_SEQ_QUE_CFG7 (7UL) -#define ADC16_SEQ_QUE_CFG8 (8UL) -#define ADC16_SEQ_QUE_CFG9 (9UL) -#define ADC16_SEQ_QUE_CFG10 (10UL) -#define ADC16_SEQ_QUE_CFG11 (11UL) -#define ADC16_SEQ_QUE_CFG12 (12UL) -#define ADC16_SEQ_QUE_CFG13 (13UL) -#define ADC16_SEQ_QUE_CFG14 (14UL) -#define ADC16_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC16_PRD_CFG_CHN0 (0UL) -#define ADC16_PRD_CFG_CHN1 (1UL) -#define ADC16_PRD_CFG_CHN2 (2UL) -#define ADC16_PRD_CFG_CHN3 (3UL) -#define ADC16_PRD_CFG_CHN4 (4UL) -#define ADC16_PRD_CFG_CHN5 (5UL) -#define ADC16_PRD_CFG_CHN6 (6UL) -#define ADC16_PRD_CFG_CHN7 (7UL) -#define ADC16_PRD_CFG_CHN8 (8UL) -#define ADC16_PRD_CFG_CHN9 (9UL) -#define ADC16_PRD_CFG_CHN10 (10UL) -#define ADC16_PRD_CFG_CHN11 (11UL) -#define ADC16_PRD_CFG_CHN12 (12UL) -#define ADC16_PRD_CFG_CHN13 (13UL) -#define ADC16_PRD_CFG_CHN14 (14UL) -#define ADC16_PRD_CFG_CHN15 (15UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC16_SAMPLE_CFG_CHN0 (0UL) -#define ADC16_SAMPLE_CFG_CHN1 (1UL) -#define ADC16_SAMPLE_CFG_CHN2 (2UL) -#define ADC16_SAMPLE_CFG_CHN3 (3UL) -#define ADC16_SAMPLE_CFG_CHN4 (4UL) -#define ADC16_SAMPLE_CFG_CHN5 (5UL) -#define ADC16_SAMPLE_CFG_CHN6 (6UL) -#define ADC16_SAMPLE_CFG_CHN7 (7UL) -#define ADC16_SAMPLE_CFG_CHN8 (8UL) -#define ADC16_SAMPLE_CFG_CHN9 (9UL) -#define ADC16_SAMPLE_CFG_CHN10 (10UL) -#define ADC16_SAMPLE_CFG_CHN11 (11UL) -#define ADC16_SAMPLE_CFG_CHN12 (12UL) -#define ADC16_SAMPLE_CFG_CHN13 (13UL) -#define ADC16_SAMPLE_CFG_CHN14 (14UL) -#define ADC16_SAMPLE_CFG_CHN15 (15UL) - -/* ADC16_PARAMS register group index macro definition */ -#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) - - -#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_crc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_crc_regs.h deleted file mode 100644 index 7c06d3e0e4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_crc_regs.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CRC_H -#define HPM_CRC_H - -typedef struct { - struct { - __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ - __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ - __RW uint32_t POLY; /* 0x8: chn poly */ - __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ - __RW uint32_t XOROUT; /* 0x10: chn xorout */ - __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ - __RW uint32_t DATA; /* 0x18: chn data */ - __RW uint32_t RESULT; /* 0x1C: chn result */ - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - } CHN[8]; -} CRC_Type; - - -/* Bitfield definition for register of struct array CHN: PRE_SET */ -/* - * PRE_SET (RW) - * - * 0: no pre set - * 1: CRC32 - * 2: CRC32-AUTOSAR - * 3: CRC16-CCITT - * 4: CRC16-XMODEM - * 5: CRC16-MODBUS - * 1: CRC32 - * 2: CRC32-autosar - * 3: CRC16-ccitt - * 4: CRC16-xmodem - * 5: CRC16-modbus - * 6: crc16_dnp - * 7: crc16_x25 - * 8: crc16_usb - * 9: crc16_maxim - * 10: crc16_ibm - * 11: crc8_maxim - * 12: crc8_rohc - * 13: crc8_itu - * 14: crc8 - * 15: crc5_usb - */ -#define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) -#define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) -#define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) -#define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) - -/* Bitfield definition for register of struct array CHN: CLR */ -/* - * CLR (RW) - * - * write 1 to clr crc setting and result for its channel. - * always read 0. - */ -#define CRC_CHN_CLR_CLR_MASK (0x1U) -#define CRC_CHN_CLR_CLR_SHIFT (0U) -#define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) -#define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) - -/* Bitfield definition for register of struct array CHN: POLY */ -/* - * POLY (RW) - * - * poly setting - */ -#define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) -#define CRC_CHN_POLY_POLY_SHIFT (0U) -#define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) -#define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array CHN: INIT_DATA */ -/* - * INIT_DATA (RW) - * - * initial data of CRC - */ -#define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) -#define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) -#define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: XOROUT */ -/* - * XOROUT (RW) - * - * XOR for CRC result - */ -#define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) -#define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) -#define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) - -/* Bitfield definition for register of struct array CHN: MISC_SETTING */ -/* - * BYTE_REV (RW) - * - * 0: no wrap input byte order - * 1: wrap input byte order - */ -#define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) -#define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) - -/* - * REV_OUT (RW) - * - * 0: no wrap output bit order - * 1: wrap output bit order - */ -#define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) -#define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) -#define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) -#define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) - -/* - * REV_IN (RW) - * - * 0: no wrap input bit order - * 1: wrap input bit order - */ -#define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) -#define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) -#define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) -#define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) - -/* - * POLY_WIDTH (RW) - * - * crc data length - */ -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) - -/* Bitfield definition for register of struct array CHN: DATA */ -/* - * DATA (RW) - * - * data for crc - */ -#define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_DATA_DATA_SHIFT (0U) -#define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) -#define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: RESULT */ -/* - * RESULT (RW) - * - * crc result - */ -#define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_RESULT_RESULT_SHIFT (0U) -#define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) -#define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) - - - -/* CHN register group index macro definition */ -#define CRC_CHN_0 (0UL) -#define CRC_CHN_1 (1UL) -#define CRC_CHN_2 (2UL) -#define CRC_CHN_3 (3UL) -#define CRC_CHN_4 (4UL) -#define CRC_CHN_5 (5UL) -#define CRC_CHN_6 (6UL) -#define CRC_CHN_7 (7UL) - - -#endif /* HPM_CRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dac_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dac_regs.h deleted file mode 100644 index 8ef7ec50f74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dac_regs.h +++ /dev/null @@ -1,637 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAC_H -#define HPM_DAC_H - -typedef struct { - __W uint32_t CFG0; /* 0x0: */ - __RW uint32_t CFG1; /* 0x4: */ - __RW uint32_t CFG2; /* 0x8: */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t STEP_CFG[4]; /* 0x10 - 0x1C: */ - __RW uint32_t BUF_ADDR[2]; /* 0x20 - 0x24: */ - __RW uint32_t BUF_LENGTH; /* 0x28: */ - __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ - __W uint32_t IRQ_STS; /* 0x30: */ - __RW uint32_t IRQ_EN; /* 0x34: */ - __RW uint32_t DMA_EN; /* 0x38: */ - __R uint8_t RESERVED2[4]; /* 0x3C - 0x3F: Reserved */ - __RW uint32_t ANA_CFG0; /* 0x40: */ - __RW uint32_t CFG0_BAK; /* 0x44: */ - __RW uint32_t STATUS0; /* 0x48: */ -} DAC_Type; - - -/* Bitfield definition for register: CFG0 */ -/* - * SW_DAC_DATA (WO) - * - * dac data used in direct mode(dac_mode==2'b10) - */ -#define DAC_CFG0_SW_DAC_DATA_MASK (0xFFF0000UL) -#define DAC_CFG0_SW_DAC_DATA_SHIFT (16U) -#define DAC_CFG0_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_SW_DAC_DATA_SHIFT) & DAC_CFG0_SW_DAC_DATA_MASK) -#define DAC_CFG0_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_SW_DAC_DATA_MASK) >> DAC_CFG0_SW_DAC_DATA_SHIFT) - -/* - * DMA_AHB_EN (WO) - * - * set to enable internal DMA, it will read one burst if enough space in FIFO. - * Should only be used in buffer mode. - */ -#define DAC_CFG0_DMA_AHB_EN_MASK (0x200U) -#define DAC_CFG0_DMA_AHB_EN_SHIFT (9U) -#define DAC_CFG0_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_DMA_AHB_EN_SHIFT) & DAC_CFG0_DMA_AHB_EN_MASK) -#define DAC_CFG0_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_DMA_AHB_EN_MASK) >> DAC_CFG0_DMA_AHB_EN_SHIFT) - -/* - * SYNC_MODE (WO) - * - * 1: sync dac clock and ahb clock. - * all HW trigger signals are pulse in sync mode, can get faster response; - * 0: async dac clock and ahb_clock - * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - */ -#define DAC_CFG0_SYNC_MODE_MASK (0x100U) -#define DAC_CFG0_SYNC_MODE_SHIFT (8U) -#define DAC_CFG0_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_SYNC_MODE_SHIFT) & DAC_CFG0_SYNC_MODE_MASK) -#define DAC_CFG0_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_SYNC_MODE_MASK) >> DAC_CFG0_SYNC_MODE_SHIFT) - -/* - * TRIG_MODE (WO) - * - * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; - * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - */ -#define DAC_CFG0_TRIG_MODE_MASK (0x80U) -#define DAC_CFG0_TRIG_MODE_SHIFT (7U) -#define DAC_CFG0_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_TRIG_MODE_SHIFT) & DAC_CFG0_TRIG_MODE_MASK) -#define DAC_CFG0_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_TRIG_MODE_MASK) >> DAC_CFG0_TRIG_MODE_SHIFT) - -/* - * HW_TRIG_EN (WO) - * - * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - */ -#define DAC_CFG0_HW_TRIG_EN_MASK (0x40U) -#define DAC_CFG0_HW_TRIG_EN_SHIFT (6U) -#define DAC_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_HW_TRIG_EN_SHIFT) & DAC_CFG0_HW_TRIG_EN_MASK) -#define DAC_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_HW_TRIG_EN_MASK) >> DAC_CFG0_HW_TRIG_EN_SHIFT) - -/* - * DAC_MODE (WO) - * - * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) - * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down - * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - * 11: trigger mode, DAC output from external trigger signals - * Note: - * Trigger mode is not supported in hpm63xx and hpm62xx families. - */ -#define DAC_CFG0_DAC_MODE_MASK (0x30U) -#define DAC_CFG0_DAC_MODE_SHIFT (4U) -#define DAC_CFG0_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_DAC_MODE_SHIFT) & DAC_CFG0_DAC_MODE_MASK) -#define DAC_CFG0_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_DAC_MODE_MASK) >> DAC_CFG0_DAC_MODE_SHIFT) - -/* - * BUF_DATA_MODE (WO) - * - * data structure for buffer mode, - * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. - * 1: each 32-bit data contains 1 point, b11:0 for first - */ -#define DAC_CFG0_BUF_DATA_MODE_MASK (0x8U) -#define DAC_CFG0_BUF_DATA_MODE_SHIFT (3U) -#define DAC_CFG0_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BUF_DATA_MODE_MASK) -#define DAC_CFG0_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BUF_DATA_MODE_MASK) >> DAC_CFG0_BUF_DATA_MODE_SHIFT) - -/* - * HBURST_CFG (WO) - * - * DAC support following fixed burst only - * 000-SINGLE; 011-INCR4; 101: INCR8 - * others are reserved - */ -#define DAC_CFG0_HBURST_CFG_MASK (0x7U) -#define DAC_CFG0_HBURST_CFG_SHIFT (0U) -#define DAC_CFG0_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_HBURST_CFG_SHIFT) & DAC_CFG0_HBURST_CFG_MASK) -#define DAC_CFG0_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_HBURST_CFG_MASK) >> DAC_CFG0_HBURST_CFG_SHIFT) - -/* Bitfield definition for register: CFG1 */ -/* - * ANA_CLK_EN (RW) - * - * set to enable analog clock(divided by ana_div_cfg) - * need to be set in direct mode and trigger mode - */ -#define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) -#define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) -#define DAC_CFG1_ANA_CLK_EN_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_CLK_EN_SHIFT) & DAC_CFG1_ANA_CLK_EN_MASK) -#define DAC_CFG1_ANA_CLK_EN_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_CLK_EN_MASK) >> DAC_CFG1_ANA_CLK_EN_SHIFT) - -/* - * ANA_DIV_CFG (RW) - * - * clock divider config for ana_clk to dac analog; - * 00: div2 - * 01: div4 - * 10: div6 - * 11: div8 - */ -#define DAC_CFG1_ANA_DIV_CFG_MASK (0x30000UL) -#define DAC_CFG1_ANA_DIV_CFG_SHIFT (16U) -#define DAC_CFG1_ANA_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_DIV_CFG_SHIFT) & DAC_CFG1_ANA_DIV_CFG_MASK) -#define DAC_CFG1_ANA_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_DIV_CFG_MASK) >> DAC_CFG1_ANA_DIV_CFG_SHIFT) - -/* - * DIV_CFG (RW) - * - * step mode and buffer mode: - * defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. - * Direct mode and trigger mode: - * defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. - * Note: - * For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. - */ -#define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) -#define DAC_CFG1_DIV_CFG_SHIFT (0U) -#define DAC_CFG1_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_DIV_CFG_SHIFT) & DAC_CFG1_DIV_CFG_MASK) -#define DAC_CFG1_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_DIV_CFG_MASK) >> DAC_CFG1_DIV_CFG_SHIFT) - -/* Bitfield definition for register: CFG2 */ -/* - * DMA_RST1 (WO) - * - * set to reset dma read pointer to buf1_start_addr; - * if set both dma_rst0&dma_rst1, will set to buf0_start_addr - * user can set fifo_clr bit when use dma_rst* - */ -#define DAC_CFG2_DMA_RST1_MASK (0x80U) -#define DAC_CFG2_DMA_RST1_SHIFT (7U) -#define DAC_CFG2_DMA_RST1_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST1_SHIFT) & DAC_CFG2_DMA_RST1_MASK) -#define DAC_CFG2_DMA_RST1_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST1_MASK) >> DAC_CFG2_DMA_RST1_SHIFT) - -/* - * DMA_RST0 (WO) - * - * set to reset dma read pointer to buf0_start_addr - */ -#define DAC_CFG2_DMA_RST0_MASK (0x40U) -#define DAC_CFG2_DMA_RST0_SHIFT (6U) -#define DAC_CFG2_DMA_RST0_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST0_SHIFT) & DAC_CFG2_DMA_RST0_MASK) -#define DAC_CFG2_DMA_RST0_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST0_MASK) >> DAC_CFG2_DMA_RST0_SHIFT) - -/* - * FIFO_CLR (WO) - * - * set to clear FIFO content(set both read/write pointer to 0) - */ -#define DAC_CFG2_FIFO_CLR_MASK (0x20U) -#define DAC_CFG2_FIFO_CLR_SHIFT (5U) -#define DAC_CFG2_FIFO_CLR_SET(x) (((uint32_t)(x) << DAC_CFG2_FIFO_CLR_SHIFT) & DAC_CFG2_FIFO_CLR_MASK) -#define DAC_CFG2_FIFO_CLR_GET(x) (((uint32_t)(x) & DAC_CFG2_FIFO_CLR_MASK) >> DAC_CFG2_FIFO_CLR_SHIFT) - -/* - * BUF_SW_TRIG (RW) - * - * software trigger for buffer mode, - * W1C in single mode. - * RW in continual mode - */ -#define DAC_CFG2_BUF_SW_TRIG_MASK (0x10U) -#define DAC_CFG2_BUF_SW_TRIG_SHIFT (4U) -#define DAC_CFG2_BUF_SW_TRIG_SET(x) (((uint32_t)(x) << DAC_CFG2_BUF_SW_TRIG_SHIFT) & DAC_CFG2_BUF_SW_TRIG_MASK) -#define DAC_CFG2_BUF_SW_TRIG_GET(x) (((uint32_t)(x) & DAC_CFG2_BUF_SW_TRIG_MASK) >> DAC_CFG2_BUF_SW_TRIG_SHIFT) - -/* - * STEP_SW_TRIG3 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG3_MASK (0x8U) -#define DAC_CFG2_STEP_SW_TRIG3_SHIFT (3U) -#define DAC_CFG2_STEP_SW_TRIG3_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG3_SHIFT) & DAC_CFG2_STEP_SW_TRIG3_MASK) -#define DAC_CFG2_STEP_SW_TRIG3_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG3_MASK) >> DAC_CFG2_STEP_SW_TRIG3_SHIFT) - -/* - * STEP_SW_TRIG2 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG2_MASK (0x4U) -#define DAC_CFG2_STEP_SW_TRIG2_SHIFT (2U) -#define DAC_CFG2_STEP_SW_TRIG2_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG2_SHIFT) & DAC_CFG2_STEP_SW_TRIG2_MASK) -#define DAC_CFG2_STEP_SW_TRIG2_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG2_MASK) >> DAC_CFG2_STEP_SW_TRIG2_SHIFT) - -/* - * STEP_SW_TRIG1 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG1_MASK (0x2U) -#define DAC_CFG2_STEP_SW_TRIG1_SHIFT (1U) -#define DAC_CFG2_STEP_SW_TRIG1_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG1_SHIFT) & DAC_CFG2_STEP_SW_TRIG1_MASK) -#define DAC_CFG2_STEP_SW_TRIG1_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG1_MASK) >> DAC_CFG2_STEP_SW_TRIG1_SHIFT) - -/* - * STEP_SW_TRIG0 (RW) - * - * software trigger0 for step mode, - * W1C in single mode. - * RW in continual mode - */ -#define DAC_CFG2_STEP_SW_TRIG0_MASK (0x1U) -#define DAC_CFG2_STEP_SW_TRIG0_SHIFT (0U) -#define DAC_CFG2_STEP_SW_TRIG0_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG0_SHIFT) & DAC_CFG2_STEP_SW_TRIG0_MASK) -#define DAC_CFG2_STEP_SW_TRIG0_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG0_MASK) >> DAC_CFG2_STEP_SW_TRIG0_SHIFT) - -/* Bitfield definition for register array: STEP_CFG */ -/* - * ROUND_MODE (RW) - * - * 0: stop at end point; - * 1: reload start point, step again - */ -#define DAC_STEP_CFG_ROUND_MODE_MASK (0x20000000UL) -#define DAC_STEP_CFG_ROUND_MODE_SHIFT (29U) -#define DAC_STEP_CFG_ROUND_MODE_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_ROUND_MODE_SHIFT) & DAC_STEP_CFG_ROUND_MODE_MASK) -#define DAC_STEP_CFG_ROUND_MODE_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_ROUND_MODE_MASK) >> DAC_STEP_CFG_ROUND_MODE_SHIFT) - -/* - * UP_DOWN (RW) - * - * 0 for up, 1 for down - */ -#define DAC_STEP_CFG_UP_DOWN_MASK (0x10000000UL) -#define DAC_STEP_CFG_UP_DOWN_SHIFT (28U) -#define DAC_STEP_CFG_UP_DOWN_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_UP_DOWN_SHIFT) & DAC_STEP_CFG_UP_DOWN_MASK) -#define DAC_STEP_CFG_UP_DOWN_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_UP_DOWN_MASK) >> DAC_STEP_CFG_UP_DOWN_SHIFT) - -/* - * END_POINT (RW) - * - */ -#define DAC_STEP_CFG_END_POINT_MASK (0xFFF0000UL) -#define DAC_STEP_CFG_END_POINT_SHIFT (16U) -#define DAC_STEP_CFG_END_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_END_POINT_SHIFT) & DAC_STEP_CFG_END_POINT_MASK) -#define DAC_STEP_CFG_END_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_END_POINT_MASK) >> DAC_STEP_CFG_END_POINT_SHIFT) - -/* - * STEP_NUM (RW) - * - * output data change step_num each DAC clock cycle. - * Ex: if step_num=3, output data sequence is 0,3,6,9 - * NOTE: user should make sure end_point can be reached if step_num is not 1 - * if step_num is 0, output data will always at start point - */ -#define DAC_STEP_CFG_STEP_NUM_MASK (0xF000U) -#define DAC_STEP_CFG_STEP_NUM_SHIFT (12U) -#define DAC_STEP_CFG_STEP_NUM_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_STEP_NUM_SHIFT) & DAC_STEP_CFG_STEP_NUM_MASK) -#define DAC_STEP_CFG_STEP_NUM_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_STEP_NUM_MASK) >> DAC_STEP_CFG_STEP_NUM_SHIFT) - -/* - * START_POINT (RW) - * - */ -#define DAC_STEP_CFG_START_POINT_MASK (0xFFFU) -#define DAC_STEP_CFG_START_POINT_SHIFT (0U) -#define DAC_STEP_CFG_START_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_START_POINT_SHIFT) & DAC_STEP_CFG_START_POINT_MASK) -#define DAC_STEP_CFG_START_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_START_POINT_MASK) >> DAC_STEP_CFG_START_POINT_SHIFT) - -/* Bitfield definition for register array: BUF_ADDR */ -/* - * BUF_START_ADDR (RW) - * - * buffer start address, should be 4-byte aligned - * AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - */ -#define DAC_BUF_ADDR_BUF_START_ADDR_MASK (0xFFFFFFFCUL) -#define DAC_BUF_ADDR_BUF_START_ADDR_SHIFT (2U) -#define DAC_BUF_ADDR_BUF_START_ADDR_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) -#define DAC_BUF_ADDR_BUF_START_ADDR_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) >> DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) - -/* - * BUF_STOP (RW) - * - * set to stop read point at end of bufffer0 - */ -#define DAC_BUF_ADDR_BUF_STOP_MASK (0x1U) -#define DAC_BUF_ADDR_BUF_STOP_SHIFT (0U) -#define DAC_BUF_ADDR_BUF_STOP_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_STOP_SHIFT) & DAC_BUF_ADDR_BUF_STOP_MASK) -#define DAC_BUF_ADDR_BUF_STOP_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_STOP_MASK) >> DAC_BUF_ADDR_BUF_STOP_SHIFT) - -/* Bitfield definition for register: BUF_LENGTH */ -/* - * BUF1_LEN (RW) - * - * buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - */ -#define DAC_BUF_LENGTH_BUF1_LEN_MASK (0xFFFF0000UL) -#define DAC_BUF_LENGTH_BUF1_LEN_SHIFT (16U) -#define DAC_BUF_LENGTH_BUF1_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF1_LEN_SHIFT) & DAC_BUF_LENGTH_BUF1_LEN_MASK) -#define DAC_BUF_LENGTH_BUF1_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF1_LEN_MASK) >> DAC_BUF_LENGTH_BUF1_LEN_SHIFT) - -/* - * BUF0_LEN (RW) - * - */ -#define DAC_BUF_LENGTH_BUF0_LEN_MASK (0xFFFFU) -#define DAC_BUF_LENGTH_BUF0_LEN_SHIFT (0U) -#define DAC_BUF_LENGTH_BUF0_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF0_LEN_SHIFT) & DAC_BUF_LENGTH_BUF0_LEN_MASK) -#define DAC_BUF_LENGTH_BUF0_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF0_LEN_MASK) >> DAC_BUF_LENGTH_BUF0_LEN_SHIFT) - -/* Bitfield definition for register: IRQ_STS */ -/* - * STEP_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_STEP_CMPT_MASK (0x10U) -#define DAC_IRQ_STS_STEP_CMPT_SHIFT (4U) -#define DAC_IRQ_STS_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_STEP_CMPT_SHIFT) & DAC_IRQ_STS_STEP_CMPT_MASK) -#define DAC_IRQ_STS_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_STEP_CMPT_MASK) >> DAC_IRQ_STS_STEP_CMPT_SHIFT) - -/* - * AHB_ERROR (W1C) - * - * set if hresp==2'b01(ERROR) - */ -#define DAC_IRQ_STS_AHB_ERROR_MASK (0x8U) -#define DAC_IRQ_STS_AHB_ERROR_SHIFT (3U) -#define DAC_IRQ_STS_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_AHB_ERROR_SHIFT) & DAC_IRQ_STS_AHB_ERROR_MASK) -#define DAC_IRQ_STS_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_AHB_ERROR_MASK) >> DAC_IRQ_STS_AHB_ERROR_SHIFT) - -/* - * FIFO_EMPTY (W1C) - * - */ -#define DAC_IRQ_STS_FIFO_EMPTY_MASK (0x4U) -#define DAC_IRQ_STS_FIFO_EMPTY_SHIFT (2U) -#define DAC_IRQ_STS_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_FIFO_EMPTY_SHIFT) & DAC_IRQ_STS_FIFO_EMPTY_MASK) -#define DAC_IRQ_STS_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_FIFO_EMPTY_MASK) >> DAC_IRQ_STS_FIFO_EMPTY_SHIFT) - -/* - * BUF1_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_BUF1_CMPT_MASK (0x2U) -#define DAC_IRQ_STS_BUF1_CMPT_SHIFT (1U) -#define DAC_IRQ_STS_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF1_CMPT_SHIFT) & DAC_IRQ_STS_BUF1_CMPT_MASK) -#define DAC_IRQ_STS_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF1_CMPT_MASK) >> DAC_IRQ_STS_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_BUF0_CMPT_MASK (0x1U) -#define DAC_IRQ_STS_BUF0_CMPT_SHIFT (0U) -#define DAC_IRQ_STS_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF0_CMPT_SHIFT) & DAC_IRQ_STS_BUF0_CMPT_MASK) -#define DAC_IRQ_STS_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF0_CMPT_MASK) >> DAC_IRQ_STS_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * STEP_CMPT (RW) - * - */ -#define DAC_IRQ_EN_STEP_CMPT_MASK (0x10U) -#define DAC_IRQ_EN_STEP_CMPT_SHIFT (4U) -#define DAC_IRQ_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_STEP_CMPT_SHIFT) & DAC_IRQ_EN_STEP_CMPT_MASK) -#define DAC_IRQ_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_STEP_CMPT_MASK) >> DAC_IRQ_EN_STEP_CMPT_SHIFT) - -/* - * AHB_ERROR (RW) - * - */ -#define DAC_IRQ_EN_AHB_ERROR_MASK (0x8U) -#define DAC_IRQ_EN_AHB_ERROR_SHIFT (3U) -#define DAC_IRQ_EN_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_AHB_ERROR_SHIFT) & DAC_IRQ_EN_AHB_ERROR_MASK) -#define DAC_IRQ_EN_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_AHB_ERROR_MASK) >> DAC_IRQ_EN_AHB_ERROR_SHIFT) - -/* - * FIFO_EMPTY (RW) - * - */ -#define DAC_IRQ_EN_FIFO_EMPTY_MASK (0x4U) -#define DAC_IRQ_EN_FIFO_EMPTY_SHIFT (2U) -#define DAC_IRQ_EN_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_FIFO_EMPTY_SHIFT) & DAC_IRQ_EN_FIFO_EMPTY_MASK) -#define DAC_IRQ_EN_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_FIFO_EMPTY_MASK) >> DAC_IRQ_EN_FIFO_EMPTY_SHIFT) - -/* - * BUF1_CMPT (RW) - * - */ -#define DAC_IRQ_EN_BUF1_CMPT_MASK (0x2U) -#define DAC_IRQ_EN_BUF1_CMPT_SHIFT (1U) -#define DAC_IRQ_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF1_CMPT_SHIFT) & DAC_IRQ_EN_BUF1_CMPT_MASK) -#define DAC_IRQ_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF1_CMPT_MASK) >> DAC_IRQ_EN_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (RW) - * - */ -#define DAC_IRQ_EN_BUF0_CMPT_MASK (0x1U) -#define DAC_IRQ_EN_BUF0_CMPT_SHIFT (0U) -#define DAC_IRQ_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF0_CMPT_SHIFT) & DAC_IRQ_EN_BUF0_CMPT_MASK) -#define DAC_IRQ_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF0_CMPT_MASK) >> DAC_IRQ_EN_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: DMA_EN */ -/* - * STEP_CMPT (RW) - * - */ -#define DAC_DMA_EN_STEP_CMPT_MASK (0x10U) -#define DAC_DMA_EN_STEP_CMPT_SHIFT (4U) -#define DAC_DMA_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_STEP_CMPT_SHIFT) & DAC_DMA_EN_STEP_CMPT_MASK) -#define DAC_DMA_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_STEP_CMPT_MASK) >> DAC_DMA_EN_STEP_CMPT_SHIFT) - -/* - * BUF1_CMPT (RW) - * - */ -#define DAC_DMA_EN_BUF1_CMPT_MASK (0x2U) -#define DAC_DMA_EN_BUF1_CMPT_SHIFT (1U) -#define DAC_DMA_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF1_CMPT_SHIFT) & DAC_DMA_EN_BUF1_CMPT_MASK) -#define DAC_DMA_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF1_CMPT_MASK) >> DAC_DMA_EN_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (RW) - * - */ -#define DAC_DMA_EN_BUF0_CMPT_MASK (0x1U) -#define DAC_DMA_EN_BUF0_CMPT_SHIFT (0U) -#define DAC_DMA_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF0_CMPT_SHIFT) & DAC_DMA_EN_BUF0_CMPT_MASK) -#define DAC_DMA_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF0_CMPT_MASK) >> DAC_DMA_EN_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: ANA_CFG0 */ -/* - * DAC12BIT_LP_MODE (RW) - * - */ -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK (0x100U) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT (8U) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) >> DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) - -/* - * DAC_CONFIG (RW) - * - */ -#define DAC_ANA_CFG0_DAC_CONFIG_MASK (0xF0U) -#define DAC_ANA_CFG0_DAC_CONFIG_SHIFT (4U) -#define DAC_ANA_CFG0_DAC_CONFIG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC_CONFIG_SHIFT) & DAC_ANA_CFG0_DAC_CONFIG_MASK) -#define DAC_ANA_CFG0_DAC_CONFIG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC_CONFIG_MASK) >> DAC_ANA_CFG0_DAC_CONFIG_SHIFT) - -/* - * CALI_DELTA_V_CFG (RW) - * - */ -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK (0xCU) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT (2U) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) >> DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) - -/* - * BYPASS_CALI_GM (RW) - * - */ -#define DAC_ANA_CFG0_BYPASS_CALI_GM_MASK (0x2U) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT (1U) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) >> DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) - -/* - * DAC12BIT_EN (RW) - * - */ -#define DAC_ANA_CFG0_DAC12BIT_EN_MASK (0x1U) -#define DAC_ANA_CFG0_DAC12BIT_EN_SHIFT (0U) -#define DAC_ANA_CFG0_DAC12BIT_EN_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) -#define DAC_ANA_CFG0_DAC12BIT_EN_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) >> DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) - -/* Bitfield definition for register: CFG0_BAK */ -/* - * SW_DAC_DATA (RW) - * - * dac data used in direct mode(dac_mode==2'b10) - */ -#define DAC_CFG0_BAK_SW_DAC_DATA_MASK (0xFFF0000UL) -#define DAC_CFG0_BAK_SW_DAC_DATA_SHIFT (16U) -#define DAC_CFG0_BAK_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) -#define DAC_CFG0_BAK_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) >> DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) - -/* - * DMA_AHB_EN (RW) - * - * set to enable internal DMA, it will read one burst if enough space in FIFO. - * Should only be used in buffer mode. - */ -#define DAC_CFG0_BAK_DMA_AHB_EN_MASK (0x200U) -#define DAC_CFG0_BAK_DMA_AHB_EN_SHIFT (9U) -#define DAC_CFG0_BAK_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) -#define DAC_CFG0_BAK_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) >> DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) - -/* - * SYNC_MODE (RW) - * - * 1: sync dac clock and ahb clock. - * all HW trigger signals are pulse in sync mode, can get faster response; - * 0: async dac clock and ahb_clock - * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - */ -#define DAC_CFG0_BAK_SYNC_MODE_MASK (0x100U) -#define DAC_CFG0_BAK_SYNC_MODE_SHIFT (8U) -#define DAC_CFG0_BAK_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SYNC_MODE_SHIFT) & DAC_CFG0_BAK_SYNC_MODE_MASK) -#define DAC_CFG0_BAK_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SYNC_MODE_MASK) >> DAC_CFG0_BAK_SYNC_MODE_SHIFT) - -/* - * TRIG_MODE (RW) - * - * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; - * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - */ -#define DAC_CFG0_BAK_TRIG_MODE_MASK (0x80U) -#define DAC_CFG0_BAK_TRIG_MODE_SHIFT (7U) -#define DAC_CFG0_BAK_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_TRIG_MODE_SHIFT) & DAC_CFG0_BAK_TRIG_MODE_MASK) -#define DAC_CFG0_BAK_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_TRIG_MODE_MASK) >> DAC_CFG0_BAK_TRIG_MODE_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - */ -#define DAC_CFG0_BAK_HW_TRIG_EN_MASK (0x40U) -#define DAC_CFG0_BAK_HW_TRIG_EN_SHIFT (6U) -#define DAC_CFG0_BAK_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) -#define DAC_CFG0_BAK_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) >> DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) - -/* - * DAC_MODE (RW) - * - * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) - * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down - * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - */ -#define DAC_CFG0_BAK_DAC_MODE_MASK (0x30U) -#define DAC_CFG0_BAK_DAC_MODE_SHIFT (4U) -#define DAC_CFG0_BAK_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DAC_MODE_SHIFT) & DAC_CFG0_BAK_DAC_MODE_MASK) -#define DAC_CFG0_BAK_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DAC_MODE_MASK) >> DAC_CFG0_BAK_DAC_MODE_SHIFT) - -/* - * BUF_DATA_MODE (RW) - * - * data structure for buffer mode, - * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. - * 1: each 32-bit data contains 1 point, b11:0 for first - */ -#define DAC_CFG0_BAK_BUF_DATA_MODE_MASK (0x8U) -#define DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT (3U) -#define DAC_CFG0_BAK_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) -#define DAC_CFG0_BAK_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) >> DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) - -/* - * HBURST_CFG (RW) - * - * DAC support following fixed burst only - * 000-SINGLE; 011-INCR4; 101: INCR8 - * others are reserved - */ -#define DAC_CFG0_BAK_HBURST_CFG_MASK (0x7U) -#define DAC_CFG0_BAK_HBURST_CFG_SHIFT (0U) -#define DAC_CFG0_BAK_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HBURST_CFG_SHIFT) & DAC_CFG0_BAK_HBURST_CFG_MASK) -#define DAC_CFG0_BAK_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HBURST_CFG_MASK) >> DAC_CFG0_BAK_HBURST_CFG_SHIFT) - -/* Bitfield definition for register: STATUS0 */ -/* - * CUR_BUF_OFFSET (RW) - * - */ -#define DAC_STATUS0_CUR_BUF_OFFSET_MASK (0xFFFF00UL) -#define DAC_STATUS0_CUR_BUF_OFFSET_SHIFT (8U) -#define DAC_STATUS0_CUR_BUF_OFFSET_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) -#define DAC_STATUS0_CUR_BUF_OFFSET_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) >> DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) - -/* - * CUR_BUF_INDEX (RW) - * - */ -#define DAC_STATUS0_CUR_BUF_INDEX_MASK (0x80U) -#define DAC_STATUS0_CUR_BUF_INDEX_SHIFT (7U) -#define DAC_STATUS0_CUR_BUF_INDEX_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_INDEX_SHIFT) & DAC_STATUS0_CUR_BUF_INDEX_MASK) -#define DAC_STATUS0_CUR_BUF_INDEX_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_INDEX_MASK) >> DAC_STATUS0_CUR_BUF_INDEX_SHIFT) - - - -/* STEP_CFG register group index macro definition */ -#define DAC_STEP_CFG_STEP0 (0UL) -#define DAC_STEP_CFG_STEP1 (1UL) -#define DAC_STEP_CFG_STEP2 (2UL) -#define DAC_STEP_CFG_STEP3 (3UL) - -/* BUF_ADDR register group index macro definition */ -#define DAC_BUF_ADDR_BUF0 (0UL) -#define DAC_BUF_ADDR_BUF1 (1UL) - - -#endif /* HPM_DAC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dmamux_regs.h deleted file mode 100644 index b656cf1c5a1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dmamux_regs.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_H -#define HPM_DMAMUX_H - -typedef struct { - __W uint32_t MUXCFG[32]; /* 0x0 - 0x7C: HDMA MUX0 Configuration */ -} DMAMUX_Type; - - -/* Bitfield definition for register array: MUXCFG */ -/* - * ENABLE (WO) - * - * DMA Mux Channel Enable - * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be - * used to disable or reconfigure a DMA channel. - * 0b - DMA Mux channel is disabled - * 1b - DMA Mux channel is enabled - */ -#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) -#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) -#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) -#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) - -/* - * SOURCE (WO) - * - * DMA Channel Source - * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - */ -#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) -#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) -#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) - - - -/* MUXCFG register group index macro definition */ -#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) -#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) -#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) -#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) -#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) -#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) -#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) -#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) -#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) -#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) -#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) -#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) -#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) -#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) -#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) -#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) -#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) -#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) -#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) -#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) -#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) -#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) -#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) -#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) -#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) -#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) -#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) -#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) -#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) -#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) -#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) -#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) - - -#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dmav2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dmav2_regs.h deleted file mode 100644 index dbedcaadb10..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_dmav2_regs.h +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAV2_H -#define HPM_DMAV2_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t IDMISC; /* 0x4: ID Misc */ - __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ - __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */ - __W uint32_t CHABORT; /* 0x18: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */ - __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */ - __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */ - __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */ - __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */ - __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x40: Channel Control Register */ - __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */ - __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */ - __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */ - __R uint8_t RESERVED0[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */ - __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ - } CHCTRL[32]; -} DMAV2_Type; - - -/* Bitfield definition for register: IDMISC */ -/* - * DMASTATE (RO) - * - * DMA state machine - * localparam ST_IDLE = 3'b000; - * localparam ST_READ = 3'b001; - * localparam ST_READ_ACK = 3'b010; - * localparam ST_WRITE = 3'b011; - * localparam ST_WRITE_ACK = 3'b100; - * localparam ST_LL = 3'b101; - * localparam ST_END = 3'b110; - * localparam ST_END_WAIT = 3'b111; - */ -#define DMAV2_IDMISC_DMASTATE_MASK (0xE000U) -#define DMAV2_IDMISC_DMASTATE_SHIFT (13U) -#define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT) - -/* - * CURCHAN (RO) - * - * current channel in used - */ -#define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U) -#define DMAV2_IDMISC_CURCHAN_SHIFT (8U) -#define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT) - -/* Bitfield definition for register: DMACFG */ -/* - * CHAINXFR (RO) - * - * Chain transfer - * 0x0: Chain transfer is not configured - * 0x1: Chain transfer is configured - */ -#define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL) -#define DMAV2_DMACFG_CHAINXFR_SHIFT (31U) -#define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT) - -/* - * REQSYNC (RO) - * - * DMA request synchronization. - * The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, - * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. - * 0x0: Request synchronization is not configured - * 0x1: Request synchronization is configured - */ -#define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL) -#define DMAV2_DMACFG_REQSYNC_SHIFT (30U) -#define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT) - -/* - * DATAWIDTH (RO) - * - * AXI bus data width - * 0x0: 32 bits - * 0x1: 64 bits - * 0x2: 128 bits - * 0x3: 256 bits - */ -#define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL) -#define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U) -#define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT) - -/* - * ADDRWIDTH (RO) - * - * AXI bus address width - * 0x18: 24 bits - * 0x19: 25 bits - * ... - * 0x40: 64 bits - * Others: Invalid - */ -#define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) -#define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U) -#define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT) - -/* - * CORENUM (RO) - * - * DMA core number - * 0x0: 1 core - * 0x1: 2 cores - */ -#define DMAV2_DMACFG_CORENUM_MASK (0x10000UL) -#define DMAV2_DMACFG_CORENUM_SHIFT (16U) -#define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT) - -/* - * BUSNUM (RO) - * - * AXI bus interface number - * 0x0: 1 AXI bus - * 0x1: 2 AXI busses - */ -#define DMAV2_DMACFG_BUSNUM_MASK (0x8000U) -#define DMAV2_DMACFG_BUSNUM_SHIFT (15U) -#define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT) - -/* - * REQNUM (RO) - * - * Request/acknowledge pair number - * 0x0: 0 pair - * 0x1: 1 pair - * 0x2: 2 pairs - * ... - * 0x10: 16 pairs - */ -#define DMAV2_DMACFG_REQNUM_MASK (0x7C00U) -#define DMAV2_DMACFG_REQNUM_SHIFT (10U) -#define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT) - -/* - * FIFODEPTH (RO) - * - * FIFO depth - * 0x4: 4 entries - * 0x8: 8 entries - * 0x10: 16 entries - * 0x20: 32 entries - * Others: Invalid - */ -#define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U) -#define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U) -#define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT) - -/* - * CHANNELNUM (RO) - * - * Channel number - * 0x1: 1 channel - * 0x2: 2 channels - * ... - * 0x8: 8 channels - * Others: Invalid - */ -#define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU) -#define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U) -#define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT) - -/* Bitfield definition for register: DMACTRL */ -/* - * RESET (WO) - * - * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. - * Note: The software reset may cause the in-completion of AXI transaction. - */ -#define DMAV2_DMACTRL_RESET_MASK (0x1U) -#define DMAV2_DMACTRL_RESET_SHIFT (0U) -#define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK) -#define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT) - -/* Bitfield definition for register: CHABORT */ -/* - * CHABORT (WO) - * - * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. - * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - */ -#define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) -#define DMAV2_CHABORT_CHABORT_SHIFT (0U) -#define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK) -#define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT) - -/* Bitfield definition for register: INTHALFSTS */ -/* - * STS (RW) - * - * half transfer done irq status - */ -#define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTHALFSTS_STS_SHIFT (0U) -#define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK) -#define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT) - -/* Bitfield definition for register: INTTCSTS */ -/* - * STS (W1C) - * - * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. - * 0x0: Channel n has no terminal count status - * 0x1: Channel n has terminal count status - */ -#define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTTCSTS_STS_SHIFT (0U) -#define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK) -#define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT) - -/* Bitfield definition for register: INTABORTSTS */ -/* - * STS (W1C) - * - * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. - * 0x0: Channel n has no abort status - * 0x1: Channel n has abort status - */ -#define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTABORTSTS_STS_SHIFT (0U) -#define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK) -#define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT) - -/* Bitfield definition for register: INTERRSTS */ -/* - * STS (W1C) - * - * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - * - Bus error - * - Unaligned address - * - Unaligned transfer width - * - Reserved configuration - * 0x0: Channel n has no error status - * 0x1: Channel n has error status - */ -#define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTERRSTS_STS_SHIFT (0U) -#define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK) -#define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT) - -/* Bitfield definition for register: CHEN */ -/* - * CHEN (RO) - * - * Alias of the Enable field of all ChnCtrl registers - */ -#define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL) -#define DMAV2_CHEN_CHEN_SHIFT (0U) -#define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CTRL */ -/* - * INFINITELOOP (RW) - * - * set to loop current config infinitely - */ -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) - -/* - * HANDSHAKEOPT (RW) - * - * 0: one request to transfer one burst - * 1: one request to transfer all the data defined in ch_tts - */ -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) - -/* - * PRIORITY (RW) - * - * Channel priority level - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) -#define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U) -#define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) -#define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) - -/* - * BURSTOPT (RW) - * - * set to change burst_size definition - */ -#define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. - * The burst transfer byte number is (SrcBurstSize * SrcWidth). - * 0x0: 1 transfer - * 0x1: 2 transfers - * 0x2: 4 transfers - * 0x3: 8 transfers - * 0x4: 16 transfers - * 0x5: 32 transfers - * 0x6: 64 transfers - * 0x7: 128 transfers - * 0x8: 256 transfers - * 0x9:512 transfers - * 0xa: 1024 transfers - * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source transfer width - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination transfer width. - * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; - * otherwise the error event will be triggered. - * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. - * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * Source DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - * Normal mode is enabled and started by software set Enable bit; - * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - */ -#define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) -#define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U) -#define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) -#define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * Destination DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - * the difference bewteen Source/Destination handshake mode is: - * the dma block will response hardware request after read in Source handshake mode; - * the dma block will response hardware request after write in Destination handshake mode; - * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - */ -#define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) -#define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U) -#define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) -#define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * Source address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * Destination address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) - -/* - * INTHALFCNTMASK (RW) - * - * Channel half interrupt mask - * 0x0: Allow the half interrupt to be triggered - * 0x1: Disable the half interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) - -/* - * INTABTMASK (RW) - * - * Channel abort interrupt mask - * 0x0: Allow the abort interrupt to be triggered - * 0x1: Disable the abort interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) - -/* - * INTERRMASK (RW) - * - * Channel error interrupt mask - * 0x0: Allow the error interrupt to be triggered - * 0x1: Disable the error interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) - -/* - * INTTCMASK (RW) - * - * Channel terminal count interrupt mask - * 0x0: Allow the terminal count interrupt to be triggered - * 0x1: Disable the terminal count interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) - -/* - * ENABLE (RW) - * - * Channel enable bit - * 0x0: Disable - * 0x1: Enable - */ -#define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U) -#define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U) -#define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) -#define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ -/* - * TRANSIZE (RW) - * - * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. - * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - */ -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ -/* - * SRCADDRL (RW) - * - * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - */ -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */ -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ -/* - * DSTADDRL (RW) - * - * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - */ -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ -/* - * LLPOINTERL (RW) - * - * Low part of the pointer to the next descriptor. The pointer must be double word aligned. - */ -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) - - - -/* CHCTRL register group index macro definition */ -#define DMAV2_CHCTRL_CH0 (0UL) -#define DMAV2_CHCTRL_CH1 (1UL) -#define DMAV2_CHCTRL_CH2 (2UL) -#define DMAV2_CHCTRL_CH3 (3UL) -#define DMAV2_CHCTRL_CH4 (4UL) -#define DMAV2_CHCTRL_CH5 (5UL) -#define DMAV2_CHCTRL_CH6 (6UL) -#define DMAV2_CHCTRL_CH7 (7UL) -#define DMAV2_CHCTRL_CH8 (8UL) -#define DMAV2_CHCTRL_CH9 (9UL) -#define DMAV2_CHCTRL_CH10 (10UL) -#define DMAV2_CHCTRL_CH11 (11UL) -#define DMAV2_CHCTRL_CH12 (12UL) -#define DMAV2_CHCTRL_CH13 (13UL) -#define DMAV2_CHCTRL_CH14 (14UL) -#define DMAV2_CHCTRL_CH15 (15UL) -#define DMAV2_CHCTRL_CH16 (16UL) -#define DMAV2_CHCTRL_CH17 (17UL) -#define DMAV2_CHCTRL_CH18 (18UL) -#define DMAV2_CHCTRL_CH19 (19UL) -#define DMAV2_CHCTRL_CH20 (20UL) -#define DMAV2_CHCTRL_CH21 (21UL) -#define DMAV2_CHCTRL_CH22 (22UL) -#define DMAV2_CHCTRL_CH23 (23UL) -#define DMAV2_CHCTRL_CH24 (24UL) -#define DMAV2_CHCTRL_CH25 (25UL) -#define DMAV2_CHCTRL_CH26 (26UL) -#define DMAV2_CHCTRL_CH27 (27UL) -#define DMAV2_CHCTRL_CH28 (28UL) -#define DMAV2_CHCTRL_CH29 (29UL) -#define DMAV2_CHCTRL_CH30 (30UL) -#define DMAV2_CHCTRL_CH31 (31UL) - - -#endif /* HPM_DMAV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ewdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ewdg_regs.h deleted file mode 100644 index aacfa33c742..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ewdg_regs.h +++ /dev/null @@ -1,467 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_EWDG_H -#define HPM_EWDG_H - -typedef struct { - __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ - __RW uint32_t CTRL1; /* 0x4: wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ - __RW uint32_t OT_INT_VAL; /* 0x8: wdog timeout interrupt counter value */ - __RW uint32_t OT_RST_VAL; /* 0xC: wdog timeout reset counter value */ - __W uint32_t WDT_REFRESH_REG; /* 0x10: wdog refresh register */ - __W uint32_t WDT_STATUS; /* 0x14: wdog status register */ - __RW uint32_t CFG_PROT; /* 0x18: ctrl register protection register */ - __RW uint32_t REF_PROT; /* 0x1C: refresh protection register */ - __RW uint32_t WDT_EN; /* 0x20: Wdog enable */ - __RW uint32_t REF_TIME; /* 0x24: Refresh period value */ -} EWDG_Type; - - -/* Bitfield definition for register: CTRL0 */ -/* - * CLK_SEL (RW) - * - * clock select - * 0：bus clock - * 1：ext clock - */ -#define EWDG_CTRL0_CLK_SEL_MASK (0x20000000UL) -#define EWDG_CTRL0_CLK_SEL_SHIFT (29U) -#define EWDG_CTRL0_CLK_SEL_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK) -#define EWDG_CTRL0_CLK_SEL_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT) - -/* - * DIV_VALUE (RW) - * - * clock divider, the clock divider works as 2 ^ div_value for wdt counter - */ -#define EWDG_CTRL0_DIV_VALUE_MASK (0xE000000UL) -#define EWDG_CTRL0_DIV_VALUE_SHIFT (25U) -#define EWDG_CTRL0_DIV_VALUE_SET(x) (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK) -#define EWDG_CTRL0_DIV_VALUE_GET(x) (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT) - -/* - * WIN_EN (RW) - * - * window mode enable - */ -#define EWDG_CTRL0_WIN_EN_MASK (0x1000000UL) -#define EWDG_CTRL0_WIN_EN_SHIFT (24U) -#define EWDG_CTRL0_WIN_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK) -#define EWDG_CTRL0_WIN_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT) - -/* - * WIN_LOWER (RW) - * - * Once window mode is opened, the lower counter value to refresh wdt - * 00: 4/8 overtime value - * 01: 5/8 of overtime value - * 10: 6/8 of overtime value - * 11: 7/8 of overtime value - */ -#define EWDG_CTRL0_WIN_LOWER_MASK (0xC00000UL) -#define EWDG_CTRL0_WIN_LOWER_SHIFT (22U) -#define EWDG_CTRL0_WIN_LOWER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK) -#define EWDG_CTRL0_WIN_LOWER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT) - -/* - * CFG_LOCK (RW) - * - * The register is locked and unlock is needed before re-config registers - * Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. - * The register update needs to be finished in the required period defined by UPD_OT_TIME register - */ -#define EWDG_CTRL0_CFG_LOCK_MASK (0x200000UL) -#define EWDG_CTRL0_CFG_LOCK_SHIFT (21U) -#define EWDG_CTRL0_CFG_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK) -#define EWDG_CTRL0_CFG_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT) - -/* - * OT_SELF_CLEAR (RW) - * - * overtime reset can be self released after 32 function cycles - */ -#define EWDG_CTRL0_OT_SELF_CLEAR_MASK (0x20000UL) -#define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT (17U) -#define EWDG_CTRL0_OT_SELF_CLEAR_SET(x) (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) -#define EWDG_CTRL0_OT_SELF_CLEAR_GET(x) (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) - -/* - * REF_OT_REQ (RW) - * - * If refresh event has to be limited into a period after refresh unlocked. - * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - */ -#define EWDG_CTRL0_REF_OT_REQ_MASK (0x8000U) -#define EWDG_CTRL0_REF_OT_REQ_SHIFT (15U) -#define EWDG_CTRL0_REF_OT_REQ_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK) -#define EWDG_CTRL0_REF_OT_REQ_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT) - -/* - * WIN_UPPER (RW) - * - * The upper threshold of window value - * The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value - * If this register value is zero, then no upper level limitation - */ -#define EWDG_CTRL0_WIN_UPPER_MASK (0x7000U) -#define EWDG_CTRL0_WIN_UPPER_SHIFT (12U) -#define EWDG_CTRL0_WIN_UPPER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK) -#define EWDG_CTRL0_WIN_UPPER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT) - -/* - * REF_LOCK (RW) - * - * WDT refresh has to be unlocked firstly once refresh lock is enable. - */ -#define EWDG_CTRL0_REF_LOCK_MASK (0x20U) -#define EWDG_CTRL0_REF_LOCK_SHIFT (5U) -#define EWDG_CTRL0_REF_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK) -#define EWDG_CTRL0_REF_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT) - -/* - * REF_UNLOCK_MEC (RW) - * - * Unlock refresh mechanism - * 00: the required unlock password is the same with refresh_psd_register - * 01: the required unlock password is a ring shift left value of refresh_psd_register - * 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is - * 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - */ -#define EWDG_CTRL0_REF_UNLOCK_MEC_MASK (0x18U) -#define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT (3U) -#define EWDG_CTRL0_REF_UNLOCK_MEC_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) -#define EWDG_CTRL0_REF_UNLOCK_MEC_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) - -/* - * EN_DBG (RW) - * - * WTD enable or not in debug mode - */ -#define EWDG_CTRL0_EN_DBG_MASK (0x4U) -#define EWDG_CTRL0_EN_DBG_SHIFT (2U) -#define EWDG_CTRL0_EN_DBG_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK) -#define EWDG_CTRL0_EN_DBG_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT) - -/* - * EN_LP (RW) - * - * WDT enable or not in low power mode - * 2'b00: wdt is halted once in low power mode - * 2'b01: wdt will work with 1/4 normal clock freq in low power mode - * 2'b10: wdt will work with 1/2 normal clock freq in low power mode - * 2'b11: wdt will work with normal clock freq in low power mode - */ -#define EWDG_CTRL0_EN_LP_MASK (0x3U) -#define EWDG_CTRL0_EN_LP_SHIFT (0U) -#define EWDG_CTRL0_EN_LP_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK) -#define EWDG_CTRL0_EN_LP_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT) - -/* Bitfield definition for register: CTRL1 */ -/* - * REF_FAIL_RST_EN (RW) - * - * Refresh violation will trigger an reset. - * These event will be taken as a refresh violation: - * 1) Not refresh in the window once window mode is enabled - * 2) Not unlock refresh firstly if unlock is required - * 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. - * 4) Not write the required word to refresh wdt. - */ -#define EWDG_CTRL1_REF_FAIL_RST_EN_MASK (0x800000UL) -#define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT (23U) -#define EWDG_CTRL1_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) - -/* - * REF_FAIL_INT_EN (RW) - * - * Refresh violation will trigger an interrupt - */ -#define EWDG_CTRL1_REF_FAIL_INT_EN_MASK (0x400000UL) -#define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT (22U) -#define EWDG_CTRL1_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) - -/* - * UNL_REF_FAIL_RST_EN (RW) - * - * Refresh unlock fail will trigger a reset - */ -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK (0x200000UL) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT (21U) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) - -/* - * UNL_REF_FAIL_INT_EN (RW) - * - * Refresh unlock fail will trigger a interrupt - */ -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK (0x100000UL) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT (20U) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) - -/* - * OT_RST_EN (RW) - * - * WDT overtime will generate a reset - */ -#define EWDG_CTRL1_OT_RST_EN_MASK (0x20000UL) -#define EWDG_CTRL1_OT_RST_EN_SHIFT (17U) -#define EWDG_CTRL1_OT_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK) -#define EWDG_CTRL1_OT_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT) - -/* - * OT_INT_EN (RW) - * - * WDT can generate an interrupt warning before timeout - */ -#define EWDG_CTRL1_OT_INT_EN_MASK (0x10000UL) -#define EWDG_CTRL1_OT_INT_EN_SHIFT (16U) -#define EWDG_CTRL1_OT_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK) -#define EWDG_CTRL1_OT_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT) - -/* - * CTL_VIO_RST_EN (RW) - * - * Ctrl update violation will trigger a reset - * The violation event is to try updating the locked register before unlock them - */ -#define EWDG_CTRL1_CTL_VIO_RST_EN_MASK (0x80U) -#define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT (7U) -#define EWDG_CTRL1_CTL_VIO_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) -#define EWDG_CTRL1_CTL_VIO_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) - -/* - * CTL_VIO_INT_EN (RW) - * - * Ctrl update violation will trigger a interrupt - */ -#define EWDG_CTRL1_CTL_VIO_INT_EN_MASK (0x40U) -#define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT (6U) -#define EWDG_CTRL1_CTL_VIO_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) -#define EWDG_CTRL1_CTL_VIO_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) - -/* - * UNL_CTL_FAIL_RST_EN (RW) - * - * Unlock register update failure will trigger a reset - */ -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK (0x20U) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT (5U) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) - -/* - * UNL_CTL_FAIL_INT_EN (RW) - * - * Unlock register update failure will trigger a interrupt - */ -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK (0x10U) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT (4U) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) - -/* - * PARITY_FAIL_RST_EN (RW) - * - * Parity error will trigger a reset - * A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - */ -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK (0x8U) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT (3U) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) - -/* - * PARITY_FAIL_INT_EN (RW) - * - * Parity error will trigger a interrupt - */ -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK (0x4U) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT (2U) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) - -/* Bitfield definition for register: OT_INT_VAL */ -/* - * OT_INT_VAL (RW) - * - * WDT timeout interrupt value - */ -#define EWDG_OT_INT_VAL_OT_INT_VAL_MASK (0xFFFFU) -#define EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT (0U) -#define EWDG_OT_INT_VAL_OT_INT_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) -#define EWDG_OT_INT_VAL_OT_INT_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) - -/* Bitfield definition for register: OT_RST_VAL */ -/* - * OT_RST_VAL (RW) - * - * WDT timeout reset value - */ -#define EWDG_OT_RST_VAL_OT_RST_VAL_MASK (0xFFFFU) -#define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT (0U) -#define EWDG_OT_RST_VAL_OT_RST_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) -#define EWDG_OT_RST_VAL_OT_RST_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) - -/* Bitfield definition for register: WDT_REFRESH_REG */ -/* - * WDT_REFRESH_REG (WO) - * - * Write this register by 32'h5A45_524F to refresh wdog - * Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - */ -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK (0xFFFFFFFFUL) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT (0U) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x) (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x) (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) - -/* Bitfield definition for register: WDT_STATUS */ -/* - * PARITY_ERROR (W1C) - * - * parity error - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_PARITY_ERROR_MASK (0x40U) -#define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT (6U) -#define EWDG_WDT_STATUS_PARITY_ERROR_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) -#define EWDG_WDT_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) - -/* - * OT_RST (W1C) - * - * Timeout happens, a reset will happen once enable bit set - * This bit can be cleared only by refreshing wdt or reset - */ -#define EWDG_WDT_STATUS_OT_RST_MASK (0x20U) -#define EWDG_WDT_STATUS_OT_RST_SHIFT (5U) -#define EWDG_WDT_STATUS_OT_RST_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_OT_RST_SHIFT) & EWDG_WDT_STATUS_OT_RST_MASK) -#define EWDG_WDT_STATUS_OT_RST_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT) - -/* - * OT_INT (W1C) - * - * Timeout happens, a interrupt will happen once enable bit set - * This bit can be cleared only by refreshing wdt or reset - */ -#define EWDG_WDT_STATUS_OT_INT_MASK (0x10U) -#define EWDG_WDT_STATUS_OT_INT_SHIFT (4U) -#define EWDG_WDT_STATUS_OT_INT_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_OT_INT_SHIFT) & EWDG_WDT_STATUS_OT_INT_MASK) -#define EWDG_WDT_STATUS_OT_INT_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT) - -/* - * CTL_UNL_FAIL (W1C) - * - * Unlock ctrl reg update protection fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK (0x8U) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT (3U) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) - -/* - * CTL_VIO (W1C) - * - * Violate register update protection mechanism - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_CTL_VIO_MASK (0x4U) -#define EWDG_WDT_STATUS_CTL_VIO_SHIFT (2U) -#define EWDG_WDT_STATUS_CTL_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK) -#define EWDG_WDT_STATUS_CTL_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT) - -/* - * REF_UNL_FAIL (W1C) - * - * Refresh unlock fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK (0x2U) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT (1U) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) - -/* - * REF_VIO (W1C) - * - * Refresh fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_REF_VIO_MASK (0x1U) -#define EWDG_WDT_STATUS_REF_VIO_SHIFT (0U) -#define EWDG_WDT_STATUS_REF_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK) -#define EWDG_WDT_STATUS_REF_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT) - -/* Bitfield definition for register: CFG_PROT */ -/* - * UPD_OT_TIME (RW) - * - * The period in which register update has to be in after unlock - * The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - */ -#define EWDG_CFG_PROT_UPD_OT_TIME_MASK (0xF0000UL) -#define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT (16U) -#define EWDG_CFG_PROT_UPD_OT_TIME_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) -#define EWDG_CFG_PROT_UPD_OT_TIME_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) - -/* - * UPD_PSD (RW) - * - * The password of unlocking register update - */ -#define EWDG_CFG_PROT_UPD_PSD_MASK (0xFFFFU) -#define EWDG_CFG_PROT_UPD_PSD_SHIFT (0U) -#define EWDG_CFG_PROT_UPD_PSD_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK) -#define EWDG_CFG_PROT_UPD_PSD_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT) - -/* Bitfield definition for register: REF_PROT */ -/* - * REF_UNL_PSD (RW) - * - * The password to unlock refreshing - */ -#define EWDG_REF_PROT_REF_UNL_PSD_MASK (0xFFFFU) -#define EWDG_REF_PROT_REF_UNL_PSD_SHIFT (0U) -#define EWDG_REF_PROT_REF_UNL_PSD_SET(x) (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK) -#define EWDG_REF_PROT_REF_UNL_PSD_GET(x) (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT) - -/* Bitfield definition for register: WDT_EN */ -/* - * WDOG_EN (RW) - * - * Wdog is enabled, the re-written of this register is impacted by enable lock function - */ -#define EWDG_WDT_EN_WDOG_EN_MASK (0x1U) -#define EWDG_WDT_EN_WDOG_EN_SHIFT (0U) -#define EWDG_WDT_EN_WDOG_EN_SET(x) (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK) -#define EWDG_WDT_EN_WDOG_EN_GET(x) (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT) - -/* Bitfield definition for register: REF_TIME */ -/* - * REFRESH_PERIOD (RW) - * - * The refresh period after refresh unlocked - * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - */ -#define EWDG_REF_TIME_REFRESH_PERIOD_MASK (0xFFFFU) -#define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT (0U) -#define EWDG_REF_TIME_REFRESH_PERIOD_SET(x) (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) -#define EWDG_REF_TIME_REFRESH_PERIOD_GET(x) (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) - - - - -#endif /* HPM_EWDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gpio_regs.h deleted file mode 100644 index 4f79fb29c8e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gpio_regs.h +++ /dev/null @@ -1,524 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIO_H -#define HPM_GPIO_H - -typedef struct { - struct { - __R uint32_t VALUE; /* 0x0: GPIO input value */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - } DI[15]; - __R uint8_t RESERVED0[16]; /* 0xF0 - 0xFF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x100: GPIO output value */ - __RW uint32_t SET; /* 0x104: GPIO output set */ - __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ - __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ - } DO[15]; - __R uint8_t RESERVED1[16]; /* 0x1F0 - 0x1FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x200: GPIO direction value */ - __RW uint32_t SET; /* 0x204: GPIO direction set */ - __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ - __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ - } OE[15]; - __R uint8_t RESERVED2[16]; /* 0x2F0 - 0x2FF: Reserved */ - struct { - __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ - } IF[15]; - __R uint8_t RESERVED3[16]; /* 0x3F0 - 0x3FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ - __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ - __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ - } IE[15]; - __R uint8_t RESERVED4[16]; /* 0x4F0 - 0x4FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ - __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ - __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ - __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ - } PL[15]; - __R uint8_t RESERVED5[16]; /* 0x5F0 - 0x5FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ - __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ - __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ - __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ - } TP[15]; - __R uint8_t RESERVED6[16]; /* 0x6F0 - 0x6FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ - __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ - __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ - __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ - } AS[15]; - __R uint8_t RESERVED7[16]; /* 0x7F0 - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: GPIO dual edge interrupt enable value */ - __RW uint32_t SET; /* 0x804: GPIO dual edge interrupt enable set */ - __RW uint32_t CLEAR; /* 0x808: GPIO dual edge interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x80C: GPIO dual edge interrupt enable toggle */ - } PD[15]; -} GPIO_Type; - - -/* Bitfield definition for register of struct array DI: VALUE */ -/* - * INPUT (RO) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: VALUE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) -#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) -#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: SET */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_SET_OUTPUT_SHIFT (0U) -#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) -#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: CLEAR */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) -#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) -#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: TOGGLE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) -#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) -#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array OE: VALUE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) -#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) -#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: SET */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_SET_DIRECTION_SHIFT (0U) -#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) -#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: CLEAR */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) -#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) -#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: TOGGLE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) -#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) -#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array IF: VALUE */ -/* - * IRQ_FLAG (W1C) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) -#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IE: VALUE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) -#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: SET */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) -#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) -#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: CLEAR */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) -#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) -#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: TOGGLE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) -#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array PL: VALUE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) -#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: SET */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) -#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) -#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: CLEAR */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) -#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) -#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: TOGGLE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) -#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array TP: VALUE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) -#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: SET */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) -#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: CLEAR */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) -#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: TOGGLE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) -#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array AS: VALUE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) -#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: SET */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) -#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: CLEAR */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) -#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: TOGGLE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array PD: VALUE */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable - * 0: single edge interrupt - * 1: dual edge interrupt enable - */ -#define GPIO_PD_VALUE_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_VALUE_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_VALUE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_VALUE_IRQ_DUAL_SHIFT) & GPIO_PD_VALUE_IRQ_DUAL_MASK) -#define GPIO_PD_VALUE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_VALUE_IRQ_DUAL_MASK) >> GPIO_PD_VALUE_IRQ_DUAL_SHIFT) - -/* Bitfield definition for register of struct array PD: SET */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable set - * 0: keep original edge interrupt type - * 1: dual edge interrupt enable - */ -#define GPIO_PD_SET_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_SET_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_SET_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_SET_IRQ_DUAL_SHIFT) & GPIO_PD_SET_IRQ_DUAL_MASK) -#define GPIO_PD_SET_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_SET_IRQ_DUAL_MASK) >> GPIO_PD_SET_IRQ_DUAL_SHIFT) - -/* Bitfield definition for register of struct array PD: CLEAR */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable clear - * 0: keep original edge interrupt type - * 1: single edge interrupt enable - */ -#define GPIO_PD_CLEAR_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_CLEAR_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_CLEAR_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) -#define GPIO_PD_CLEAR_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) >> GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) - -/* Bitfield definition for register of struct array PD: TOGGLE */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable toggle - * 0: keep original edge interrupt type - * 1: change original edge interrupt type to another one. - */ -#define GPIO_PD_TOGGLE_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_TOGGLE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) -#define GPIO_PD_TOGGLE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) >> GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) - - - -/* DI register group index macro definition */ -#define GPIO_DI_GPIOA (0UL) -#define GPIO_DI_GPIOB (1UL) -#define GPIO_DI_GPIOX (13UL) -#define GPIO_DI_GPIOY (14UL) - -/* DO register group index macro definition */ -#define GPIO_DO_GPIOA (0UL) -#define GPIO_DO_GPIOB (1UL) -#define GPIO_DO_GPIOX (13UL) -#define GPIO_DO_GPIOY (14UL) - -/* OE register group index macro definition */ -#define GPIO_OE_GPIOA (0UL) -#define GPIO_OE_GPIOB (1UL) -#define GPIO_OE_GPIOX (13UL) -#define GPIO_OE_GPIOY (14UL) - -/* IF register group index macro definition */ -#define GPIO_IF_GPIOA (0UL) -#define GPIO_IF_GPIOB (1UL) -#define GPIO_IF_GPIOX (13UL) -#define GPIO_IF_GPIOY (14UL) - -/* IE register group index macro definition */ -#define GPIO_IE_GPIOA (0UL) -#define GPIO_IE_GPIOB (1UL) -#define GPIO_IE_GPIOX (13UL) -#define GPIO_IE_GPIOY (14UL) - -/* PL register group index macro definition */ -#define GPIO_PL_GPIOA (0UL) -#define GPIO_PL_GPIOB (1UL) -#define GPIO_PL_GPIOX (13UL) -#define GPIO_PL_GPIOY (14UL) - -/* TP register group index macro definition */ -#define GPIO_TP_GPIOA (0UL) -#define GPIO_TP_GPIOB (1UL) -#define GPIO_TP_GPIOX (13UL) -#define GPIO_TP_GPIOY (14UL) - -/* AS register group index macro definition */ -#define GPIO_AS_GPIOA (0UL) -#define GPIO_AS_GPIOB (1UL) -#define GPIO_AS_GPIOX (13UL) -#define GPIO_AS_GPIOY (14UL) - -/* PD register group index macro definition */ -#define GPIO_PD_GPIOA (0UL) -#define GPIO_PD_GPIOB (1UL) -#define GPIO_PD_GPIOX (13UL) -#define GPIO_PD_GPIOY (14UL) - - -#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gpiom_regs.h deleted file mode 100644 index 85a507cc26d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gpiom_regs.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIOM_H -#define HPM_GPIOM_H - -typedef struct { - struct { - __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ - } ASSIGN[15]; -} GPIOM_Type; - - -/* Bitfield definition for register of struct array ASSIGN: PIN00 */ -/* - * LOCK (RW) - * - * lock fields in this register, lock can only be cleared by soc reset - * 0: fields can be changed - * 1: fields locked to current value, not changeable - */ -#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) -#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) -#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) - -/* - * HIDE (RW) - * - * pin value visibility to gpios, - * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 - * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - */ -#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) -#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) -#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) -#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) - -/* - * SELECT (RW) - * - * select which gpio controls chip pin, - * 0: soc gpio0; - * 2: cpu0 fastgpio - */ -#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) -#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) -#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) -#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) - - - -/* PIN register group index macro definition */ -#define GPIOM_ASSIGN_PIN_PIN00 (0UL) -#define GPIOM_ASSIGN_PIN_PIN01 (1UL) -#define GPIOM_ASSIGN_PIN_PIN02 (2UL) -#define GPIOM_ASSIGN_PIN_PIN03 (3UL) -#define GPIOM_ASSIGN_PIN_PIN04 (4UL) -#define GPIOM_ASSIGN_PIN_PIN05 (5UL) -#define GPIOM_ASSIGN_PIN_PIN06 (6UL) -#define GPIOM_ASSIGN_PIN_PIN07 (7UL) -#define GPIOM_ASSIGN_PIN_PIN08 (8UL) -#define GPIOM_ASSIGN_PIN_PIN09 (9UL) -#define GPIOM_ASSIGN_PIN_PIN10 (10UL) -#define GPIOM_ASSIGN_PIN_PIN11 (11UL) -#define GPIOM_ASSIGN_PIN_PIN12 (12UL) -#define GPIOM_ASSIGN_PIN_PIN13 (13UL) -#define GPIOM_ASSIGN_PIN_PIN14 (14UL) -#define GPIOM_ASSIGN_PIN_PIN15 (15UL) -#define GPIOM_ASSIGN_PIN_PIN16 (16UL) -#define GPIOM_ASSIGN_PIN_PIN17 (17UL) -#define GPIOM_ASSIGN_PIN_PIN18 (18UL) -#define GPIOM_ASSIGN_PIN_PIN19 (19UL) -#define GPIOM_ASSIGN_PIN_PIN20 (20UL) -#define GPIOM_ASSIGN_PIN_PIN21 (21UL) -#define GPIOM_ASSIGN_PIN_PIN22 (22UL) -#define GPIOM_ASSIGN_PIN_PIN23 (23UL) -#define GPIOM_ASSIGN_PIN_PIN24 (24UL) -#define GPIOM_ASSIGN_PIN_PIN25 (25UL) -#define GPIOM_ASSIGN_PIN_PIN26 (26UL) -#define GPIOM_ASSIGN_PIN_PIN27 (27UL) -#define GPIOM_ASSIGN_PIN_PIN28 (28UL) -#define GPIOM_ASSIGN_PIN_PIN29 (29UL) -#define GPIOM_ASSIGN_PIN_PIN30 (30UL) -#define GPIOM_ASSIGN_PIN_PIN31 (31UL) - -/* ASSIGN register group index macro definition */ -#define GPIOM_ASSIGN_GPIOA (0UL) -#define GPIOM_ASSIGN_GPIOB (1UL) -#define GPIOM_ASSIGN_GPIOX (13UL) -#define GPIOM_ASSIGN_GPIOY (14UL) - - -#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gptmr_regs.h deleted file mode 100644 index 50e6e586e4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_gptmr_regs.h +++ /dev/null @@ -1,644 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPTMR_H -#define HPM_GPTMR_H - -typedef struct { - struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ - __RW uint32_t RLD; /* 0xC: Reload register */ - __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ - __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ - __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ - __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ - __R uint32_t CNT; /* 0x30: Counter */ - __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ - } CHANNEL[4]; - __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ - __RW uint32_t SR; /* 0x200: Status register */ - __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ - __RW uint32_t GCR; /* 0x208: Global control register */ -} GPTMR_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CR */ -/* - * CNTUPT (WO) - * - * 1- update counter to new value as CNTUPTVAL - * This bit will be auto cleared after 1 cycle - */ -#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) -#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) -#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) -#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) - -/* - * OPMODE (RW) - * - * 0: round mode - * 1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. - * NOTE: reload irq will be always set at one-shot mode at end - */ -#define GPTMR_CHANNEL_CR_OPMODE_MASK (0x20000UL) -#define GPTMR_CHANNEL_CR_OPMODE_SHIFT (17U) -#define GPTMR_CHANNEL_CR_OPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_OPMODE_SHIFT) & GPTMR_CHANNEL_CR_OPMODE_MASK) -#define GPTMR_CHANNEL_CR_OPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_OPMODE_MASK) >> GPTMR_CHANNEL_CR_OPMODE_SHIFT) - -/* - * MONITOR_SEL (RW) - * - * set to monitor input signal high level time(chan_meas_high) - * clr to monitor input signal period(chan_meas_prd) - */ -#define GPTMR_CHANNEL_CR_MONITOR_SEL_MASK (0x10000UL) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT (16U) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) >> GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) - -/* - * MONITOR_EN (RW) - * - * set to monitor input signal period or high level time. - * When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts - * * only can be used when trig_mode is selected as measure mode(100) - * * the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. - * if no posedge after reload for more than val_1, will also assert irq_capt - */ -#define GPTMR_CHANNEL_CR_MONITOR_EN_MASK (0x8000U) -#define GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT (15U) -#define GPTMR_CHANNEL_CR_MONITOR_EN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) -#define GPTMR_CHANNEL_CR_MONITOR_EN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) >> GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) - -/* - * CNTRST (RW) - * - * 1- reset counter - */ -#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) -#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) -#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) -#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) - -/* - * SYNCFLW (RW) - * - * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. - * This bit is not valid for channel 0. - */ -#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) -#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) - -/* - * SYNCIFEN (RW) - * - * 1- SYNCI is valid on its falling edge - */ -#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) - -/* - * SYNCIREN (RW) - * - * 1- SYNCI is valid on its rising edge - */ -#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) - -/* - * CEN (RW) - * - * 1- counter enable - */ -#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) -#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) -#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) -#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) - -/* - * CMPINIT (RW) - * - * Output compare initial poliarity - * 1- The channel output initial level is high - * 0- The channel output initial level is low - * User should set this bit before set CMPEN to 1. - */ -#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) -#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) -#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) -#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) - -/* - * CMPEN (RW) - * - * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - */ -#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) -#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) -#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) -#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) - -/* - * DMASEL (RW) - * - * select one of DMA request: - * 00- CMP0 flag - * 01- CMP1 flag - * 10- Input signal toggle captured - * 11- RLD flag, counter reload; - */ -#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) -#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) -#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) -#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) - -/* - * DMAEN (RW) - * - * 1- enable dma - */ -#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) -#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) -#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) -#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) - -/* - * SWSYNCIEN (RW) - * - * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - */ -#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) - -/* - * DBGPAUSE (RW) - * - * 1- counter will pause if chip is in debug mode - */ -#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) -#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) - -/* - * CAPMODE (RW) - * - * This bitfield define the input capture mode - * 100: width measure mode, timer will calculate the input signal period and duty cycle - * 011: capture at both rising edge and falling edge - * 010: capture at falling edge - * 001: capture at rising edge - * 000: No capture - */ -#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) -#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) -#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) -#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CMP0 */ -/* - * CMP (RW) - * - * compare value 0 - */ -#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) -#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) -#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: RLD */ -/* - * RLD (RW) - * - * reload value - */ -#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) -#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) -#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ -/* - * CNTUPTVAL (RW) - * - * counter will be set to this value when software write cntupt bit in CR - */ -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ -/* - * CAPPOS (RO) - * - * This register contains the counter value captured at input signal rising edge - */ -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ -/* - * CAPNEG (RO) - * - * This register contains the counter value captured at input signal falling edge - */ -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ -/* - * CAPPRD (RO) - * - * This register contains the input signal period when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ -/* - * MEAS_HIGH (RO) - * - * This register contains the input signal duty cycle when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNT */ -/* - * COUNTER (RO) - * - * 32 bit counter value - */ -#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) -#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * CH3CMP1F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) -#define GPTMR_SR_CH3CMP1F_SHIFT (15U) -#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) -#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) - -/* - * CH3CMP0F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) -#define GPTMR_SR_CH3CMP0F_SHIFT (14U) -#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) -#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) - -/* - * CH3CAPF (W1C) - * - * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH3CAPF_MASK (0x2000U) -#define GPTMR_SR_CH3CAPF_SHIFT (13U) -#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) -#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) - -/* - * CH3RLDF (W1C) - * - * channel 3 counter reload flag - */ -#define GPTMR_SR_CH3RLDF_MASK (0x1000U) -#define GPTMR_SR_CH3RLDF_SHIFT (12U) -#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) -#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) - -/* - * CH2CMP1F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP1F_MASK (0x800U) -#define GPTMR_SR_CH2CMP1F_SHIFT (11U) -#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) -#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) - -/* - * CH2CMP0F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP0F_MASK (0x400U) -#define GPTMR_SR_CH2CMP0F_SHIFT (10U) -#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) -#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) - -/* - * CH2CAPF (W1C) - * - * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH2CAPF_MASK (0x200U) -#define GPTMR_SR_CH2CAPF_SHIFT (9U) -#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) -#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) - -/* - * CH2RLDF (W1C) - * - * channel 2 counter reload flag - */ -#define GPTMR_SR_CH2RLDF_MASK (0x100U) -#define GPTMR_SR_CH2RLDF_SHIFT (8U) -#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) -#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) - -/* - * CH1CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP1F_MASK (0x80U) -#define GPTMR_SR_CH1CMP1F_SHIFT (7U) -#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) -#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) - -/* - * CH1CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP0F_MASK (0x40U) -#define GPTMR_SR_CH1CMP0F_SHIFT (6U) -#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) -#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) - -/* - * CH1CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH1CAPF_MASK (0x20U) -#define GPTMR_SR_CH1CAPF_SHIFT (5U) -#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) -#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) - -/* - * CH1RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH1RLDF_MASK (0x10U) -#define GPTMR_SR_CH1RLDF_SHIFT (4U) -#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) -#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) - -/* - * CH0CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP1F_MASK (0x8U) -#define GPTMR_SR_CH0CMP1F_SHIFT (3U) -#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) -#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) - -/* - * CH0CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP0F_MASK (0x4U) -#define GPTMR_SR_CH0CMP0F_SHIFT (2U) -#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) -#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) - -/* - * CH0CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH0CAPF_MASK (0x2U) -#define GPTMR_SR_CH0CAPF_SHIFT (1U) -#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) -#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) - -/* - * CH0RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH0RLDF_MASK (0x1U) -#define GPTMR_SR_CH0RLDF_SHIFT (0U) -#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) -#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * CH3CMP1EN (RW) - * - * 1- generate interrupt request when ch3cmp1f flag is set - */ -#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) -#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) -#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) -#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) - -/* - * CH3CMP0EN (RW) - * - * 1- generate interrupt request when ch3cmp0f flag is set - */ -#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) -#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) -#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) -#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) - -/* - * CH3CAPEN (RW) - * - * 1- generate interrupt request when ch3capf flag is set - */ -#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) -#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) -#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) -#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) - -/* - * CH3RLDEN (RW) - * - * 1- generate interrupt request when ch3rldf flag is set - */ -#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) -#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) -#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) -#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) - -/* - * CH2CMP1EN (RW) - * - * 1- generate interrupt request when ch2cmp1f flag is set - */ -#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) -#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) -#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) -#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) - -/* - * CH2CMP0EN (RW) - * - * 1- generate interrupt request when ch2cmp0f flag is set - */ -#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) -#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) -#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) -#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) - -/* - * CH2CAPEN (RW) - * - * 1- generate interrupt request when ch2capf flag is set - */ -#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) -#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) -#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) -#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) - -/* - * CH2RLDEN (RW) - * - * 1- generate interrupt request when ch2rldf flag is set - */ -#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) -#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) -#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) -#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) - -/* - * CH1CMP1EN (RW) - * - * 1- generate interrupt request when ch1cmp1f flag is set - */ -#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) -#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) -#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) -#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) - -/* - * CH1CMP0EN (RW) - * - * 1- generate interrupt request when ch1cmp0f flag is set - */ -#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) -#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) -#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) -#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) - -/* - * CH1CAPEN (RW) - * - * 1- generate interrupt request when ch1capf flag is set - */ -#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) -#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) -#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) -#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) - -/* - * CH1RLDEN (RW) - * - * 1- generate interrupt request when ch1rldf flag is set - */ -#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) -#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) -#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) -#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) - -/* - * CH0CMP1EN (RW) - * - * 1- generate interrupt request when ch0cmp1f flag is set - */ -#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) -#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) -#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) -#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) - -/* - * CH0CMP0EN (RW) - * - * 1- generate interrupt request when ch0cmp0f flag is set - */ -#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) -#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) -#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) -#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) - -/* - * CH0CAPEN (RW) - * - * 1- generate interrupt request when ch0capf flag is set - */ -#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) -#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) -#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) -#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) - -/* - * CH0RLDEN (RW) - * - * 1- generate interrupt request when ch0rldf flag is set - */ -#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) -#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) -#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) -#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * SWSYNCT (RW) - * - * set this bitfield to trigger software counter sync event - */ -#define GPTMR_GCR_SWSYNCT_MASK (0xFU) -#define GPTMR_GCR_SWSYNCT_SHIFT (0U) -#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) -#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) - - - -/* CMP register group index macro definition */ -#define GPTMR_CHANNEL_CMP_CMP0 (0UL) -#define GPTMR_CHANNEL_CMP_CMP1 (1UL) - -/* CHANNEL register group index macro definition */ -#define GPTMR_CHANNEL_CH0 (0UL) -#define GPTMR_CHANNEL_CH1 (1UL) -#define GPTMR_CHANNEL_CH2 (2UL) -#define GPTMR_CHANNEL_CH3 (3UL) - - -#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_i2c_regs.h deleted file mode 100644 index 1446ec912e7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_i2c_regs.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2C_H -#define HPM_I2C_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ - __RW uint32_t STATUS; /* 0x18: Status Register */ - __RW uint32_t ADDR; /* 0x1C: Address Register */ - __RW uint32_t DATA; /* 0x20: Data Register */ - __RW uint32_t CTRL; /* 0x24: Control Register */ - __RW uint32_t CMD; /* 0x28: Command Register */ - __RW uint32_t SETUP; /* 0x2C: Setup Register */ - __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ -} I2C_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * FIFO Size: - * 0: 2 bytes - * 1: 4 bytes - * 2: 8 bytes - * 3: 16 bytes - */ -#define I2C_CFG_FIFOSIZE_MASK (0x3U) -#define I2C_CFG_FIFOSIZE_SHIFT (0U) -#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * CMPL (RW) - * - * Set to enable the Completion Interrupt. - * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. - * Slave: interrupts when a transaction addressing the controller is completed. - */ -#define I2C_INTEN_CMPL_MASK (0x200U) -#define I2C_INTEN_CMPL_SHIFT (9U) -#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) -#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) - -/* - * BYTERECV (RW) - * - * Set to enable the Byte Receive Interrupt. - * Interrupts when a byte of data is received - * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - */ -#define I2C_INTEN_BYTERECV_MASK (0x100U) -#define I2C_INTEN_BYTERECV_SHIFT (8U) -#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) -#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) - -/* - * BYTETRANS (RW) - * - * Set to enable the Byte Transmit Interrupt. - * Interrupts when a byte of data is transmitted. - */ -#define I2C_INTEN_BYTETRANS_MASK (0x80U) -#define I2C_INTEN_BYTETRANS_SHIFT (7U) -#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) -#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) - -/* - * START (RW) - * - * Set to enable the START Condition Interrupt. - * Interrupts when a START condition/repeated START condition is detected. - */ -#define I2C_INTEN_START_MASK (0x40U) -#define I2C_INTEN_START_SHIFT (6U) -#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) -#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) - -/* - * STOP (RW) - * - * Set to enable the STOP Condition Interrupt - * Interrupts when a STOP condition is detected. - */ -#define I2C_INTEN_STOP_MASK (0x20U) -#define I2C_INTEN_STOP_SHIFT (5U) -#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) -#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) - -/* - * ARBLOSE (RW) - * - * Set to enable the Arbitration Lose Interrupt. - * Master: interrupts when the controller loses the bus arbitration - * Slave: not available in this mode. - */ -#define I2C_INTEN_ARBLOSE_MASK (0x10U) -#define I2C_INTEN_ARBLOSE_SHIFT (4U) -#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) -#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) - -/* - * ADDRHIT (RW) - * - * Set to enable the Address Hit Interrupt. - * Master: interrupts when the addressed slave returned an ACK. - * Slave: interrupts when the controller is addressed. - */ -#define I2C_INTEN_ADDRHIT_MASK (0x8U) -#define I2C_INTEN_ADDRHIT_SHIFT (3U) -#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) -#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RW) - * - * Set to enable the FIFO Half Interrupt. - * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. - * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. - * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - */ -#define I2C_INTEN_FIFOHALF_MASK (0x4U) -#define I2C_INTEN_FIFOHALF_SHIFT (2U) -#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) -#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RW) - * - * Set to enable the FIFO Full Interrupt. - * Interrupts when the FIFO is full. - */ -#define I2C_INTEN_FIFOFULL_MASK (0x2U) -#define I2C_INTEN_FIFOFULL_SHIFT (1U) -#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) -#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RW) - * - * Set to enabled the FIFO Empty Interrupt - * Interrupts when the FIFO is empty. - */ -#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) -#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) -#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) -#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * LINESDA (RO) - * - * Indicates the current status of the SDA line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESDA_MASK (0x4000U) -#define I2C_STATUS_LINESDA_SHIFT (14U) -#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) - -/* - * LINESCL (RO) - * - * Indicates the current status of the SCL line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESCL_MASK (0x2000U) -#define I2C_STATUS_LINESCL_SHIFT (13U) -#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) - -/* - * GENCALL (RO) - * - * Indicates that the address of the current transaction is a general call address: - * 1: General call - * 0: Not general call - */ -#define I2C_STATUS_GENCALL_MASK (0x1000U) -#define I2C_STATUS_GENCALL_SHIFT (12U) -#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) - -/* - * BUSBUSY (RO) - * - * Indicates that the bus is busy - * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus - * 1: Busy - * 0: Not busy - */ -#define I2C_STATUS_BUSBUSY_MASK (0x800U) -#define I2C_STATUS_BUSBUSY_SHIFT (11U) -#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) - -/* - * ACK (RO) - * - * Indicates the type of the last received/transmitted acknowledgement bit: - * 1: ACK - * 0: NACK - */ -#define I2C_STATUS_ACK_MASK (0x400U) -#define I2C_STATUS_ACK_SHIFT (10U) -#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) - -/* - * CMPL (W1C) - * - * Transaction Completion - * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration - * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - */ -#define I2C_STATUS_CMPL_MASK (0x200U) -#define I2C_STATUS_CMPL_SHIFT (9U) -#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) -#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) - -/* - * BYTERECV (W1C) - * - * Indicates that a byte of data has been received. - */ -#define I2C_STATUS_BYTERECV_MASK (0x100U) -#define I2C_STATUS_BYTERECV_SHIFT (8U) -#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) -#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) - -/* - * BYTETRANS (W1C) - * - * Indicates that a byte of data has been transmitted. - */ -#define I2C_STATUS_BYTETRANS_MASK (0x80U) -#define I2C_STATUS_BYTETRANS_SHIFT (7U) -#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) -#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) - -/* - * START (W1C) - * - * Indicates that a START Condition or a repeated START condition has been transmitted/received. - */ -#define I2C_STATUS_START_MASK (0x40U) -#define I2C_STATUS_START_SHIFT (6U) -#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) -#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) - -/* - * STOP (W1C) - * - * Indicates that a STOP Condition has been transmitted/received. - */ -#define I2C_STATUS_STOP_MASK (0x20U) -#define I2C_STATUS_STOP_SHIFT (5U) -#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) -#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) - -/* - * ARBLOSE (W1C) - * - * Indicates that the controller has lost the bus arbitration. - */ -#define I2C_STATUS_ARBLOSE_MASK (0x10U) -#define I2C_STATUS_ARBLOSE_SHIFT (4U) -#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) -#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) - -/* - * ADDRHIT (W1C) - * - * Master: indicates that a slave has responded to the transaction. - * Slave: indicates that a transaction is targeting the controller (including the General Call). - */ -#define I2C_STATUS_ADDRHIT_MASK (0x8U) -#define I2C_STATUS_ADDRHIT_SHIFT (3U) -#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) -#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RO) - * - * Transmitter: Indicates that the FIFO is half-empty. - */ -#define I2C_STATUS_FIFOHALF_MASK (0x4U) -#define I2C_STATUS_FIFOHALF_SHIFT (2U) -#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RO) - * - * Indicates that the FIFO is full. - */ -#define I2C_STATUS_FIFOFULL_MASK (0x2U) -#define I2C_STATUS_FIFOFULL_SHIFT (1U) -#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RO) - * - * Indicates that the FIFO is empty. - */ -#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) -#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) -#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * The slave address. - * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - */ -#define I2C_ADDR_ADDR_MASK (0x3FFU) -#define I2C_ADDR_ADDR_SHIFT (0U) -#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) -#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Write this register to put one byte of data to the FIFO. - * Read this register to get one byte of data from the FIFO. - */ -#define I2C_DATA_DATA_MASK (0xFFU) -#define I2C_DATA_DATA_SHIFT (0U) -#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) -#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * DATACNT_HIGH (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_HIGH_MASK (0xFF000000UL) -#define I2C_CTRL_DATACNT_HIGH_SHIFT (24U) -#define I2C_CTRL_DATACNT_HIGH_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_HIGH_SHIFT) & I2C_CTRL_DATACNT_HIGH_MASK) -#define I2C_CTRL_DATACNT_HIGH_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_HIGH_MASK) >> I2C_CTRL_DATACNT_HIGH_SHIFT) - -/* - * RESET_LEN (RW) - * - * reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - */ -#define I2C_CTRL_RESET_LEN_MASK (0xF00000UL) -#define I2C_CTRL_RESET_LEN_SHIFT (20U) -#define I2C_CTRL_RESET_LEN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_LEN_SHIFT) & I2C_CTRL_RESET_LEN_MASK) -#define I2C_CTRL_RESET_LEN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_LEN_MASK) >> I2C_CTRL_RESET_LEN_SHIFT) - -/* - * RESET_HOLD_SCKIN (RW) - * - * set to hold input clock to high when reset is active - */ -#define I2C_CTRL_RESET_HOLD_SCKIN_MASK (0x4000U) -#define I2C_CTRL_RESET_HOLD_SCKIN_SHIFT (14U) -#define I2C_CTRL_RESET_HOLD_SCKIN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) -#define I2C_CTRL_RESET_HOLD_SCKIN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) >> I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) - -/* - * RESET_ON (RW) - * - * set to send reset signals(just toggle clock bus defined by reset_len). - * this register is clered when reset is end, can't be cleared by software - */ -#define I2C_CTRL_RESET_ON_MASK (0x2000U) -#define I2C_CTRL_RESET_ON_SHIFT (13U) -#define I2C_CTRL_RESET_ON_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_ON_SHIFT) & I2C_CTRL_RESET_ON_MASK) -#define I2C_CTRL_RESET_ON_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_ON_MASK) >> I2C_CTRL_RESET_ON_SHIFT) - -/* - * PHASE_START (RW) - * - * Enable this bit to send a START condition at the beginning of transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_START_MASK (0x1000U) -#define I2C_CTRL_PHASE_START_SHIFT (12U) -#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) -#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) - -/* - * PHASE_ADDR (RW) - * - * Enable this bit to send the address after START condition. - * Master mode only. - */ -#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) -#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) -#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) -#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) - -/* - * PHASE_DATA (RW) - * - * Enable this bit to send the data after Address phase. - * Master mode only. - */ -#define I2C_CTRL_PHASE_DATA_MASK (0x400U) -#define I2C_CTRL_PHASE_DATA_SHIFT (10U) -#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) -#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) - -/* - * PHASE_STOP (RW) - * - * Enable this bit to send a STOP condition at the end of a transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_STOP_MASK (0x200U) -#define I2C_CTRL_PHASE_STOP_SHIFT (9U) -#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) -#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) - -/* - * DIR (RW) - * - * Transaction direction - * Master: Set this bit to determine the direction for the next transaction. - * 0: Transmitter - * 1: Receiver - * Slave: The direction of the last received transaction. - * 0: Receiver - * 1: Transmitter - */ -#define I2C_CTRL_DIR_MASK (0x100U) -#define I2C_CTRL_DIR_SHIFT (8U) -#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) -#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) - -/* - * DATACNT (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_MASK (0xFFU) -#define I2C_CTRL_DATACNT_SHIFT (0U) -#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) -#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * Write this register with the following values to perform the corresponding actions: - * 0x0: no action - * 0x1: issue a data transaction (Master only) - * 0x2: respond with an ACK to the received byte - * 0x3: respond with a NACK to the received byte - * 0x4: clear the FIFO - * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) - * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. - * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - */ -#define I2C_CMD_CMD_MASK (0x7U) -#define I2C_CMD_CMD_SHIFT (0U) -#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) -#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) - -/* Bitfield definition for register: SETUP */ -/* - * T_SUDAT (RW) - * - * T_SUDAT defines the data setup time before releasing the SCL. - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) - * tpclk = PCLK period - * TPM = The multiplier value in Timing Parameter Multiplier Register - */ -#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) -#define I2C_SETUP_T_SUDAT_SHIFT (24U) -#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) -#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) - -/* - * T_SP (RW) - * - * T_SP defines the pulse width of spikes that must be suppressed by the input filter. - * Pulse width = T_SP * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_SP_MASK (0xE00000UL) -#define I2C_SETUP_T_SP_SHIFT (21U) -#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) -#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) - -/* - * T_HDDAT (RW) - * - * T_HDDAT defines the data hold time after SCL goes LOW - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) -#define I2C_SETUP_T_HDDAT_SHIFT (16U) -#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) -#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) - -/* - * T_SCLRADIO (RW) - * - * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. - * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) - * 1: ratio = 2 - * 0: ratio = 1 - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) -#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) -#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) -#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) - -/* - * T_SCLHI (RW) - * - * The HIGH period of generated SCL clock is defined by T_SCLHi. - * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) - * The T_SCLHi value must be greater than T_SP and T_HDDAT values. - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) -#define I2C_SETUP_T_SCLHI_SHIFT (4U) -#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) -#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) - -/* - * DMAEN (RW) - * - * Enable the direct memory access mode data transfer. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_DMAEN_MASK (0x8U) -#define I2C_SETUP_DMAEN_SHIFT (3U) -#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) -#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) - -/* - * MASTER (RW) - * - * Configure this device as a master or a slave. - * 1: Master mode - * 0: Slave mode - */ -#define I2C_SETUP_MASTER_MASK (0x4U) -#define I2C_SETUP_MASTER_SHIFT (2U) -#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) -#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) - -/* - * ADDRESSING (RW) - * - * I2C addressing mode: - * 1: 10-bit addressing mode - * 0: 7-bit addressing mode - */ -#define I2C_SETUP_ADDRESSING_MASK (0x2U) -#define I2C_SETUP_ADDRESSING_SHIFT (1U) -#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) -#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) - -/* - * IICEN (RW) - * - * Enable the I2C controller. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_IICEN_MASK (0x1U) -#define I2C_SETUP_IICEN_SHIFT (0U) -#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) -#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) - -/* Bitfield definition for register: TPM */ -/* - * TPM (RW) - * - * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - */ -#define I2C_TPM_TPM_MASK (0x1FU) -#define I2C_TPM_TPM_SHIFT (0U) -#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) -#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) - - - - -#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ioc_regs.h deleted file mode 100644 index 5913db1ed7a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ioc_regs.h +++ /dev/null @@ -1,259 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOC_H -#define HPM_IOC_H - -typedef struct { - struct { - __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ - __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[456]; -} IOC_Type; - - -/* Bitfield definition for register of struct array PAD: FUNC_CTL */ -/* - * LOOP_BACK (RW) - * - * force input on - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) - -/* - * ANALOG (RW) - * - * select analog pin in pad - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) -#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) -#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) -#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) - -/* - * ALT_SELECT (RW) - * - * alt select - * 0: ALT0 - * 1: ALT1 - * ... - * 31:ALT31 - */ -#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) - -/* Bitfield definition for register of struct array PAD: PAD_CTL */ -/* - * HYS (RW) - * - * schmitt trigger enable - * 0: disable - * 1: enable - */ -#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) -#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) -#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) -#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) - -/* - * PRS (RW) - * - * select pull up/down internal resistance strength: - * For pull down, only have 100 Kohm resistance - * For pull up: - * 00: 100 KOhm - * 01: 47 KOhm - * 10: 22 KOhm - * 11: 22 KOhm - */ -#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) -#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) -#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) -#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) - -/* - * PS (RW) - * - * pull select - * 0: pull down - * 1: pull up - */ -#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) -#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) -#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) -#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) - -/* - * PE (RW) - * - * pull enable - * 0: pull disable - * 1: pull enable - */ -#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) -#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) -#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) -#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) - -/* - * KE (RW) - * - * keeper capability enable - * 0: keeper disable - * 1: keeper enable - */ -#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) -#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) -#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) -#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) - -/* - * OD (RW) - * - * open drain - * 0: open drain disable - * 1: open drain enable - */ -#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) -#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) -#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) -#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) - -/* - * SR (RW) - * - * slew rate - * 0: Slow slew rate - * 1: Fast slew rate - */ -#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) -#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) -#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) -#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) - -/* - * SPD (RW) - * - * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise - * 00: Slow frequency slew rate(50Mhz) - * 01: Medium frequency slew rate(100 Mhz) - * 10: Fast frequency slew rate(150 Mhz) - * 11: Max frequency slew rate(200Mhz) - */ -#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) -#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) -#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) -#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) - -/* - * DS (RW) - * - * drive strength - * 1.8V Mode: - * 000: 260 Ohm - * 001: 260 Ohm - * 010: 130 Ohm - * 011: 88 Ohm - * 100: 65 Ohm - * 101: 52 Ohm - * 110: 43 Ohm - * 111: 37 Ohm - * 3.3V Mode: - * 000: 157 Ohm - * 001: 157 Ohm - * 010: 78 Ohm - * 011: 53 Ohm - * 100: 39 Ohm - * 101: 32 Ohm - * 110: 26 Ohm - * 111: 23 Ohm - */ -#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) -#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) -#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) -#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) - - - -/* PAD register group index macro definition */ -#define IOC_PAD_PA00 (0UL) -#define IOC_PAD_PA01 (1UL) -#define IOC_PAD_PA02 (2UL) -#define IOC_PAD_PA03 (3UL) -#define IOC_PAD_PA04 (4UL) -#define IOC_PAD_PA05 (5UL) -#define IOC_PAD_PA06 (6UL) -#define IOC_PAD_PA07 (7UL) -#define IOC_PAD_PA08 (8UL) -#define IOC_PAD_PA09 (9UL) -#define IOC_PAD_PA10 (10UL) -#define IOC_PAD_PA11 (11UL) -#define IOC_PAD_PA12 (12UL) -#define IOC_PAD_PA13 (13UL) -#define IOC_PAD_PA14 (14UL) -#define IOC_PAD_PA15 (15UL) -#define IOC_PAD_PA16 (16UL) -#define IOC_PAD_PA17 (17UL) -#define IOC_PAD_PA18 (18UL) -#define IOC_PAD_PA19 (19UL) -#define IOC_PAD_PA20 (20UL) -#define IOC_PAD_PA21 (21UL) -#define IOC_PAD_PA22 (22UL) -#define IOC_PAD_PA23 (23UL) -#define IOC_PAD_PA24 (24UL) -#define IOC_PAD_PA25 (25UL) -#define IOC_PAD_PA26 (26UL) -#define IOC_PAD_PA27 (27UL) -#define IOC_PAD_PA28 (28UL) -#define IOC_PAD_PA29 (29UL) -#define IOC_PAD_PA30 (30UL) -#define IOC_PAD_PA31 (31UL) -#define IOC_PAD_PB00 (32UL) -#define IOC_PAD_PB01 (33UL) -#define IOC_PAD_PB02 (34UL) -#define IOC_PAD_PB03 (35UL) -#define IOC_PAD_PB04 (36UL) -#define IOC_PAD_PB05 (37UL) -#define IOC_PAD_PB06 (38UL) -#define IOC_PAD_PB07 (39UL) -#define IOC_PAD_PB08 (40UL) -#define IOC_PAD_PB09 (41UL) -#define IOC_PAD_PB10 (42UL) -#define IOC_PAD_PB11 (43UL) -#define IOC_PAD_PB12 (44UL) -#define IOC_PAD_PB13 (45UL) -#define IOC_PAD_PB14 (46UL) -#define IOC_PAD_PB15 (47UL) -#define IOC_PAD_PX00 (416UL) -#define IOC_PAD_PX01 (416UL) -#define IOC_PAD_PX02 (417UL) -#define IOC_PAD_PX03 (417UL) -#define IOC_PAD_PX04 (418UL) -#define IOC_PAD_PX05 (418UL) -#define IOC_PAD_PX06 (419UL) -#define IOC_PAD_PX07 (419UL) -#define IOC_PAD_PY00 (448UL) -#define IOC_PAD_PY01 (449UL) -#define IOC_PAD_PY02 (450UL) -#define IOC_PAD_PY03 (451UL) -#define IOC_PAD_PY04 (452UL) -#define IOC_PAD_PY05 (453UL) -#define IOC_PAD_PY06 (454UL) -#define IOC_PAD_PY07 (455UL) - - -#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_keym_regs.h deleted file mode 100644 index 0d97ce1ecb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_keym_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_KEYM_H -#define HPM_KEYM_H - -typedef struct { - __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ - __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ - __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ - __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ - __RW uint32_t RNG; /* 0x48: Random number interface behavior */ - __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ -} KEYM_Type; - - -/* Bitfield definition for register array: SOFTMKEY */ -/* - * KEY (RW) - * - * software symmetric key - * key will be scambled to 4 variants for software to use, and replicable on same chip. - * scramble keys are chip different, and not replicable on different chip - * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - */ -#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTMKEY_KEY_SHIFT (0U) -#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) -#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) - -/* Bitfield definition for register array: SOFTPKEY */ -/* - * KEY (RW) - * - * software asymmetric key - * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. - * This key os read once, sencondary read will read out 0 - */ -#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTPKEY_KEY_SHIFT (0U) -#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) -#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) - -/* Bitfield definition for register: SEC_KEY_CTL */ -/* - * LOCK_SEC_CTL (RW) - * - * block secure state key setting being changed - */ -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use origin value in software symmetric key - * 1: use scramble version of software symmetric key - */ -#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use alnertave scramble of fuse symmetric key - */ -#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: NSC_KEY_CTL */ -/* - * LOCK_NSC_CTL (RW) - * - * block non-secure state key setting being changed - */ -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use origin value in fuse symmetric key - */ -#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * non-secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: RNG */ -/* - * BLOCK_RNG_XOR (RW) - * - * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset - * 0: RNG_XOR can be changed by software - * 1: RNG_XOR ignore software change from software - */ -#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) -#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) -#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) -#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) - -/* - * RNG_XOR (RW) - * - * control how SFK is accepted from random number generator - * 0: SFK value replaced by random number input - * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - */ -#define KEYM_RNG_RNG_XOR_MASK (0x1U) -#define KEYM_RNG_RNG_XOR_SHIFT (0U) -#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) -#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) - -/* Bitfield definition for register: READ_CONTROL */ -/* - * BLOCK_PK_READ (RW) - * - * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) - -/* - * BLOCK_SMK_READ (RW) - * - * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) - - - -/* SOFTMKEY register group index macro definition */ -#define KEYM_SOFTMKEY_SFK0 (0UL) -#define KEYM_SOFTMKEY_SFK1 (1UL) -#define KEYM_SOFTMKEY_SFK2 (2UL) -#define KEYM_SOFTMKEY_SFK3 (3UL) -#define KEYM_SOFTMKEY_SFK4 (4UL) -#define KEYM_SOFTMKEY_SFK5 (5UL) -#define KEYM_SOFTMKEY_SFK6 (6UL) -#define KEYM_SOFTMKEY_SFK7 (7UL) - -/* SOFTPKEY register group index macro definition */ -#define KEYM_SOFTPKEY_SPK0 (0UL) -#define KEYM_SOFTPKEY_SPK1 (1UL) -#define KEYM_SOFTPKEY_SPK2 (2UL) -#define KEYM_SOFTPKEY_SPK3 (3UL) -#define KEYM_SOFTPKEY_SPK4 (4UL) -#define KEYM_SOFTPKEY_SPK5 (5UL) -#define KEYM_SOFTPKEY_SPK6 (6UL) -#define KEYM_SOFTPKEY_SPK7 (7UL) - - -#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_linv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_linv2_regs.h deleted file mode 100644 index 99833f3fcaf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_linv2_regs.h +++ /dev/null @@ -1,466 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LINV2_H -#define HPM_LINV2_H - -typedef struct { - union { - __RW uint32_t DATA[2]; /* 0x0 - 0x4: data byte */ - __RW uint8_t DATA_BYTE[8]; /* 0x0 - 0x7: */ - }; - __RW uint32_t DATA_LEN_ID; /* 0x8: data length and ID register */ - __RW uint32_t CONTROL_STATUS; /* 0xC: control and status register */ - __RW uint32_t TIMING_CONTROL; /* 0x10: timing control register */ - __RW uint32_t DMA_CONTROL; /* 0x14: dma control register */ -} LINV2_Type; - - -/* Bitfield definition for register: DATA0 */ -/* - * DATA (RW) - * - * data - */ -#define LINV2_DATA_DATA_MASK (0xFFFFFFFFUL) -#define LINV2_DATA_DATA_SHIFT (0U) -#define LINV2_DATA_DATA_SET(x) (((uint32_t)(x) << LINV2_DATA_DATA_SHIFT) & LINV2_DATA_DATA_MASK) -#define LINV2_DATA_DATA_GET(x) (((uint32_t)(x) & LINV2_DATA_DATA_MASK) >> LINV2_DATA_DATA_SHIFT) - -/* Bitfield definition for register: DATA_BYTE0 */ -/* - * DATA_BYTE (RW) - * - * data byte - */ -#define LINV2_DATA_BYTE_DATA_BYTE_MASK (0xFFU) -#define LINV2_DATA_BYTE_DATA_BYTE_SHIFT (0U) -#define LINV2_DATA_BYTE_DATA_BYTE_SET(x) (((uint8_t)(x) << LINV2_DATA_BYTE_DATA_BYTE_SHIFT) & LINV2_DATA_BYTE_DATA_BYTE_MASK) -#define LINV2_DATA_BYTE_DATA_BYTE_GET(x) (((uint8_t)(x) & LINV2_DATA_BYTE_DATA_BYTE_MASK) >> LINV2_DATA_BYTE_DATA_BYTE_SHIFT) - -/* Bitfield definition for register: DATA_LEN_ID */ -/* - * CHECKSUM (RO) - * - */ -#define LINV2_DATA_LEN_ID_CHECKSUM_MASK (0xFF0000UL) -#define LINV2_DATA_LEN_ID_CHECKSUM_SHIFT (16U) -#define LINV2_DATA_LEN_ID_CHECKSUM_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_CHECKSUM_MASK) >> LINV2_DATA_LEN_ID_CHECKSUM_SHIFT) - -/* - * ID_PARITY (RO) - * - */ -#define LINV2_DATA_LEN_ID_ID_PARITY_MASK (0xC000U) -#define LINV2_DATA_LEN_ID_ID_PARITY_SHIFT (14U) -#define LINV2_DATA_LEN_ID_ID_PARITY_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_PARITY_MASK) >> LINV2_DATA_LEN_ID_ID_PARITY_SHIFT) - -/* - * ID (RW) - * - * ID register - */ -#define LINV2_DATA_LEN_ID_ID_MASK (0x3F00U) -#define LINV2_DATA_LEN_ID_ID_SHIFT (8U) -#define LINV2_DATA_LEN_ID_ID_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ID_SHIFT) & LINV2_DATA_LEN_ID_ID_MASK) -#define LINV2_DATA_LEN_ID_ID_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ID_MASK) >> LINV2_DATA_LEN_ID_ID_SHIFT) - -/* - * ENH_CHECK (RW) - * - * 1:enhance check mode 0:classical check mode - */ -#define LINV2_DATA_LEN_ID_ENH_CHECK_MASK (0x80U) -#define LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT (7U) -#define LINV2_DATA_LEN_ID_ENH_CHECK_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) -#define LINV2_DATA_LEN_ID_ENH_CHECK_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_ENH_CHECK_MASK) >> LINV2_DATA_LEN_ID_ENH_CHECK_SHIFT) - -/* - * DATA_LEN (RW) - * - * payload data length control register。The data length will decoded from ID[5:4] when all 1 is configured: 00-2 01-2 10-4 11-8 - */ -#define LINV2_DATA_LEN_ID_DATA_LEN_MASK (0xFU) -#define LINV2_DATA_LEN_ID_DATA_LEN_SHIFT (0U) -#define LINV2_DATA_LEN_ID_DATA_LEN_SET(x) (((uint32_t)(x) << LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) -#define LINV2_DATA_LEN_ID_DATA_LEN_GET(x) (((uint32_t)(x) & LINV2_DATA_LEN_ID_DATA_LEN_MASK) >> LINV2_DATA_LEN_ID_DATA_LEN_SHIFT) - -/* Bitfield definition for register: CONTROL_STATUS */ -/* - * BREAK_ERR_DIS (RW) - * - */ -#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK (0x200000UL) -#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT (21U) -#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) -#define LINV2_CONTROL_STATUS_BREAK_ERR_DIS_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_DIS_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_DIS_SHIFT) - -/* - * BREAK_ERR (RO) - * - */ -#define LINV2_CONTROL_STATUS_BREAK_ERR_MASK (0x100000UL) -#define LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT (20U) -#define LINV2_CONTROL_STATUS_BREAK_ERR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BREAK_ERR_MASK) >> LINV2_CONTROL_STATUS_BREAK_ERR_SHIFT) - -/* - * PARITY_ERROR (RO) - * - * slave only. identifier parity error - */ -#define LINV2_CONTROL_STATUS_PARITY_ERROR_MASK (0x80000UL) -#define LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT (19U) -#define LINV2_CONTROL_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_PARITY_ERROR_MASK) >> LINV2_CONTROL_STATUS_PARITY_ERROR_SHIFT) - -/* - * TIME_OUT (RO) - * - * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms - */ -#define LINV2_CONTROL_STATUS_TIME_OUT_MASK (0x40000UL) -#define LINV2_CONTROL_STATUS_TIME_OUT_SHIFT (18U) -#define LINV2_CONTROL_STATUS_TIME_OUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TIME_OUT_MASK) >> LINV2_CONTROL_STATUS_TIME_OUT_SHIFT) - -/* - * CHK_ERROR (RO) - * - * checksum error - */ -#define LINV2_CONTROL_STATUS_CHK_ERROR_MASK (0x20000UL) -#define LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT (17U) -#define LINV2_CONTROL_STATUS_CHK_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_CHK_ERROR_MASK) >> LINV2_CONTROL_STATUS_CHK_ERROR_SHIFT) - -/* - * BIT_ERROR (RO) - * - * bit error - */ -#define LINV2_CONTROL_STATUS_BIT_ERROR_MASK (0x10000UL) -#define LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT (16U) -#define LINV2_CONTROL_STATUS_BIT_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BIT_ERROR_MASK) >> LINV2_CONTROL_STATUS_BIT_ERROR_SHIFT) - -/* - * LIN_ACTIVE (RO) - * - * The bit indicates whether the LIN bus is active or not - */ -#define LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK (0x8000U) -#define LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT (15U) -#define LINV2_CONTROL_STATUS_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_LIN_ACTIVE_MASK) >> LINV2_CONTROL_STATUS_LIN_ACTIVE_SHIFT) - -/* - * BUS_IDLE_TIMEOUT (RO) - * - * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s - */ -#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK (0x4000U) -#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT (14U) -#define LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_MASK) >> LINV2_CONTROL_STATUS_BUS_IDLE_TIMEOUT_SHIFT) - -/* - * ABORTED (RO) - * - * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. - */ -#define LINV2_CONTROL_STATUS_ABORTED_MASK (0x2000U) -#define LINV2_CONTROL_STATUS_ABORTED_SHIFT (13U) -#define LINV2_CONTROL_STATUS_ABORTED_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ABORTED_MASK) >> LINV2_CONTROL_STATUS_ABORTED_SHIFT) - -/* - * DATA_REQ (RO) - * - * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. - */ -#define LINV2_CONTROL_STATUS_DATA_REQ_MASK (0x1000U) -#define LINV2_CONTROL_STATUS_DATA_REQ_SHIFT (12U) -#define LINV2_CONTROL_STATUS_DATA_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_REQ_MASK) >> LINV2_CONTROL_STATUS_DATA_REQ_SHIFT) - -/* - * INT (RO) - * - * set when request an interrupt. Reset by reset_int - */ -#define LINV2_CONTROL_STATUS_INT_MASK (0x800U) -#define LINV2_CONTROL_STATUS_INT_SHIFT (11U) -#define LINV2_CONTROL_STATUS_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_INT_MASK) >> LINV2_CONTROL_STATUS_INT_SHIFT) - -/* - * ERROR (RO) - * - * set when detecte an error, clear by reset_error - */ -#define LINV2_CONTROL_STATUS_ERROR_MASK (0x400U) -#define LINV2_CONTROL_STATUS_ERROR_SHIFT (10U) -#define LINV2_CONTROL_STATUS_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_ERROR_MASK) >> LINV2_CONTROL_STATUS_ERROR_SHIFT) - -/* - * WAKEUP (RO) - * - * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 - */ -#define LINV2_CONTROL_STATUS_WAKEUP_MASK (0x200U) -#define LINV2_CONTROL_STATUS_WAKEUP_SHIFT (9U) -#define LINV2_CONTROL_STATUS_WAKEUP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_SHIFT) - -/* - * COMPLETE (RO) - * - * set after a transmission has been successful finished and it will reset at the start of a transmission. - */ -#define LINV2_CONTROL_STATUS_COMPLETE_MASK (0x100U) -#define LINV2_CONTROL_STATUS_COMPLETE_SHIFT (8U) -#define LINV2_CONTROL_STATUS_COMPLETE_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_COMPLETE_MASK) >> LINV2_CONTROL_STATUS_COMPLETE_SHIFT) - -/* - * STOP (WO) - * - * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID - */ -#define LINV2_CONTROL_STATUS_STOP_MASK (0x80U) -#define LINV2_CONTROL_STATUS_STOP_SHIFT (7U) -#define LINV2_CONTROL_STATUS_STOP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_STOP_SHIFT) & LINV2_CONTROL_STATUS_STOP_MASK) -#define LINV2_CONTROL_STATUS_STOP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_STOP_MASK) >> LINV2_CONTROL_STATUS_STOP_SHIFT) - -/* - * SLEEP (RW) - * - * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. - */ -#define LINV2_CONTROL_STATUS_SLEEP_MASK (0x40U) -#define LINV2_CONTROL_STATUS_SLEEP_SHIFT (6U) -#define LINV2_CONTROL_STATUS_SLEEP_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_SLEEP_SHIFT) & LINV2_CONTROL_STATUS_SLEEP_MASK) -#define LINV2_CONTROL_STATUS_SLEEP_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_SLEEP_MASK) >> LINV2_CONTROL_STATUS_SLEEP_SHIFT) - -/* - * TRANSMIT (RW) - * - * 1: transmit operation 0: receive operation - */ -#define LINV2_CONTROL_STATUS_TRANSMIT_MASK (0x20U) -#define LINV2_CONTROL_STATUS_TRANSMIT_SHIFT (5U) -#define LINV2_CONTROL_STATUS_TRANSMIT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) -#define LINV2_CONTROL_STATUS_TRANSMIT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_TRANSMIT_MASK) >> LINV2_CONTROL_STATUS_TRANSMIT_SHIFT) - -/* - * DATA_ACK (RW) - * - * slave only. Write 1 after handling a data request interrupt - */ -#define LINV2_CONTROL_STATUS_DATA_ACK_MASK (0x10U) -#define LINV2_CONTROL_STATUS_DATA_ACK_SHIFT (4U) -#define LINV2_CONTROL_STATUS_DATA_ACK_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) -#define LINV2_CONTROL_STATUS_DATA_ACK_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_DATA_ACK_MASK) >> LINV2_CONTROL_STATUS_DATA_ACK_SHIFT) - -/* - * RESET_INT (WO) - * - * set 1 will clear the int register - */ -#define LINV2_CONTROL_STATUS_RESET_INT_MASK (0x8U) -#define LINV2_CONTROL_STATUS_RESET_INT_SHIFT (3U) -#define LINV2_CONTROL_STATUS_RESET_INT_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_INT_SHIFT) & LINV2_CONTROL_STATUS_RESET_INT_MASK) -#define LINV2_CONTROL_STATUS_RESET_INT_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_INT_MASK) >> LINV2_CONTROL_STATUS_RESET_INT_SHIFT) - -/* - * RESET_ERROR (WO) - * - * set 1 will clear the error register, and also the timeout/complete/wakeup register - */ -#define LINV2_CONTROL_STATUS_RESET_ERROR_MASK (0x4U) -#define LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT (2U) -#define LINV2_CONTROL_STATUS_RESET_ERROR_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) -#define LINV2_CONTROL_STATUS_RESET_ERROR_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_RESET_ERROR_MASK) >> LINV2_CONTROL_STATUS_RESET_ERROR_SHIFT) - -/* - * WAKEUP_REQ (RW) - * - * set 1 will make LIN bus exit sleep mode, the bit auto cleared after a wakeup signal has been complete - */ -#define LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK (0x2U) -#define LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT (1U) -#define LINV2_CONTROL_STATUS_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) -#define LINV2_CONTROL_STATUS_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_WAKEUP_REQ_MASK) >> LINV2_CONTROL_STATUS_WAKEUP_REQ_SHIFT) - -/* - * START_REQ (RW) - * - * master only. Set 1 will start lin transmission, the bit will be auto cleared when an error occur or the transmission complete - */ -#define LINV2_CONTROL_STATUS_START_REQ_MASK (0x1U) -#define LINV2_CONTROL_STATUS_START_REQ_SHIFT (0U) -#define LINV2_CONTROL_STATUS_START_REQ_SET(x) (((uint32_t)(x) << LINV2_CONTROL_STATUS_START_REQ_SHIFT) & LINV2_CONTROL_STATUS_START_REQ_MASK) -#define LINV2_CONTROL_STATUS_START_REQ_GET(x) (((uint32_t)(x) & LINV2_CONTROL_STATUS_START_REQ_MASK) >> LINV2_CONTROL_STATUS_START_REQ_SHIFT) - -/* Bitfield definition for register: TIMING_CONTROL */ -/* - * WAKE_LEN (RW) - * - */ -#define LINV2_TIMING_CONTROL_WAKE_LEN_MASK (0x38000000UL) -#define LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT (27U) -#define LINV2_TIMING_CONTROL_WAKE_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) -#define LINV2_TIMING_CONTROL_WAKE_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WAKE_LEN_MASK) >> LINV2_TIMING_CONTROL_WAKE_LEN_SHIFT) - -/* - * BRK_LEN (RW) - * - */ -#define LINV2_TIMING_CONTROL_BRK_LEN_MASK (0x7000000UL) -#define LINV2_TIMING_CONTROL_BRK_LEN_SHIFT (24U) -#define LINV2_TIMING_CONTROL_BRK_LEN_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) -#define LINV2_TIMING_CONTROL_BRK_LEN_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BRK_LEN_MASK) >> LINV2_TIMING_CONTROL_BRK_LEN_SHIFT) - -/* - * LINBUSDISABLE (RW) - * - * 1：lin rx is disable - */ -#define LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK (0x400000UL) -#define LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT (22U) -#define LINV2_TIMING_CONTROL_LINBUSDISABLE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) -#define LINV2_TIMING_CONTROL_LINBUSDISABLE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LINBUSDISABLE_MASK) >> LINV2_TIMING_CONTROL_LINBUSDISABLE_SHIFT) - -/* - * LIN_INITIAL (RW) - * - * 1:initial lin controller - */ -#define LINV2_TIMING_CONTROL_LIN_INITIAL_MASK (0x200000UL) -#define LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT (21U) -#define LINV2_TIMING_CONTROL_LIN_INITIAL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) -#define LINV2_TIMING_CONTROL_LIN_INITIAL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_LIN_INITIAL_MASK) >> LINV2_TIMING_CONTROL_LIN_INITIAL_SHIFT) - -/* - * MASTER_MODE (RW) - * - * 1：master mode - */ -#define LINV2_TIMING_CONTROL_MASTER_MODE_MASK (0x100000UL) -#define LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT (20U) -#define LINV2_TIMING_CONTROL_MASTER_MODE_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) -#define LINV2_TIMING_CONTROL_MASTER_MODE_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_MASTER_MODE_MASK) >> LINV2_TIMING_CONTROL_MASTER_MODE_SHIFT) - -/* - * BUS_INACTIVE_TIME (RW) - * - * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s - */ -#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK (0xC0000UL) -#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT (18U) -#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) -#define LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_MASK) >> LINV2_TIMING_CONTROL_BUS_INACTIVE_TIME_SHIFT) - -/* - * WUP_REPEAT_TIME (RW) - * - * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms - */ -#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK (0x30000UL) -#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT (16U) -#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) -#define LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_MASK) >> LINV2_TIMING_CONTROL_WUP_REPEAT_TIME_SHIFT) - -/* - * PRESCL (RW) - * - * prescl register - */ -#define LINV2_TIMING_CONTROL_PRESCL_MASK (0xC000U) -#define LINV2_TIMING_CONTROL_PRESCL_SHIFT (14U) -#define LINV2_TIMING_CONTROL_PRESCL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_PRESCL_SHIFT) & LINV2_TIMING_CONTROL_PRESCL_MASK) -#define LINV2_TIMING_CONTROL_PRESCL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_PRESCL_MASK) >> LINV2_TIMING_CONTROL_PRESCL_SHIFT) - -/* - * BT_MUL (RW) - * - * bt_mul register - */ -#define LINV2_TIMING_CONTROL_BT_MUL_MASK (0x3E00U) -#define LINV2_TIMING_CONTROL_BT_MUL_SHIFT (9U) -#define LINV2_TIMING_CONTROL_BT_MUL_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_MUL_SHIFT) & LINV2_TIMING_CONTROL_BT_MUL_MASK) -#define LINV2_TIMING_CONTROL_BT_MUL_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_MUL_MASK) >> LINV2_TIMING_CONTROL_BT_MUL_SHIFT) - -/* - * BT_DIV (RW) - * - * bt_div register - */ -#define LINV2_TIMING_CONTROL_BT_DIV_MASK (0x1FFU) -#define LINV2_TIMING_CONTROL_BT_DIV_SHIFT (0U) -#define LINV2_TIMING_CONTROL_BT_DIV_SET(x) (((uint32_t)(x) << LINV2_TIMING_CONTROL_BT_DIV_SHIFT) & LINV2_TIMING_CONTROL_BT_DIV_MASK) -#define LINV2_TIMING_CONTROL_BT_DIV_GET(x) (((uint32_t)(x) & LINV2_TIMING_CONTROL_BT_DIV_MASK) >> LINV2_TIMING_CONTROL_BT_DIV_SHIFT) - -/* Bitfield definition for register: DMA_CONTROL */ -/* - * DMA_REQ_ENH_CHK (RW) - * - * payload data checksum type for dma operation - */ -#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK (0x1000U) -#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT (12U) -#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) -#define LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENH_CHK_SHIFT) - -/* - * DMA_REQ_LEN (RW) - * - * paylaod length for dma request - */ -#define LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK (0xF00U) -#define LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT (8U) -#define LINV2_DMA_CONTROL_DMA_REQ_LEN_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) -#define LINV2_DMA_CONTROL_DMA_REQ_LEN_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_LEN_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_LEN_SHIFT) - -/* - * DMA_REQ_ID_TYPE (RW) - * - * 1：transmite 0：receive - */ -#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK (0x80U) -#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT (7U) -#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) -#define LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_TYPE_SHIFT) - -/* - * DMA_REQ_ID (RW) - * - * dma_req_id register - */ -#define LINV2_DMA_CONTROL_DMA_REQ_ID_MASK (0x7EU) -#define LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT (1U) -#define LINV2_DMA_CONTROL_DMA_REQ_ID_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) -#define LINV2_DMA_CONTROL_DMA_REQ_ID_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ID_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ID_SHIFT) - -/* - * DMA_REQ_ENABLE (RW) - * - * slave mode only. 1: enable dma request for data request ID equal dma_req_id - */ -#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK (0x1U) -#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT (0U) -#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SET(x) (((uint32_t)(x) << LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) -#define LINV2_DMA_CONTROL_DMA_REQ_ENABLE_GET(x) (((uint32_t)(x) & LINV2_DMA_CONTROL_DMA_REQ_ENABLE_MASK) >> LINV2_DMA_CONTROL_DMA_REQ_ENABLE_SHIFT) - - - -/* DATA register group index macro definition */ -#define LINV2_DATA_DATA0 (0UL) -#define LINV2_DATA_DATA1 (1UL) - -/* DATA_BYTE register group index macro definition */ -#define LINV2_DATA_BYTE_DATA_BYTE0 (0UL) -#define LINV2_DATA_BYTE_DATA_BYTE1 (1UL) -#define LINV2_DATA_BYTE_DATA_BYTE2 (2UL) -#define LINV2_DATA_BYTE_DATA_BYTE3 (3UL) -#define LINV2_DATA_BYTE_DATA_BYTE4 (4UL) -#define LINV2_DATA_BYTE_DATA_BYTE5 (5UL) -#define LINV2_DATA_BYTE_DATA_BYTE6 (6UL) -#define LINV2_DATA_BYTE_DATA_BYTE7 (7UL) - - -#endif /* HPM_LINV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mbx_regs.h deleted file mode 100644 index d159b97303a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mbx_regs.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_H -#define HPM_MBX_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Command Registers */ - __RW uint32_t SR; /* 0x4: Status Registers */ - __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ - __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ - __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ -} MBX_Type; - - -/* Bitfield definition for register: CR */ -/* - * TXRESET (RW) - * - * Reset TX Fifo and word. - */ -#define MBX_CR_TXRESET_MASK (0x80000000UL) -#define MBX_CR_TXRESET_SHIFT (31U) -#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) -#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) - -/* - * BARCTL (RW) - * - * Bus Access Response Control, when bit 15:14= - * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. - * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. - * 11: reserved. - */ -#define MBX_CR_BARCTL_MASK (0xC000U) -#define MBX_CR_BARCTL_SHIFT (14U) -#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) -#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. - * 1, enable the bus access error interrupt. - * 0, disable the bus access error interrupt. - */ -#define MBX_CR_BEIE_MASK (0x100U) -#define MBX_CR_BEIE_SHIFT (8U) -#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) -#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) - -/* - * TFMAIE (RW) - * - * TX FIFO message available interrupt enable. - * 1, enable the TX FIFO massage available interrupt. - * 0, disable the TX FIFO message available interrupt. - */ -#define MBX_CR_TFMAIE_MASK (0x80U) -#define MBX_CR_TFMAIE_SHIFT (7U) -#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) -#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) - -/* - * TFMEIE (RW) - * - * TX FIFO message empty interrupt enable. - * 1, enable the TX FIFO massage empty interrupt. - * 0, disable the TX FIFO message empty interrupt. - */ -#define MBX_CR_TFMEIE_MASK (0x40U) -#define MBX_CR_TFMEIE_SHIFT (6U) -#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) -#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) - -/* - * RFMAIE (RW) - * - * RX FIFO message available interrupt enable. - * 1, enable the RX FIFO massage available interrupt. - * 0, disable the RX FIFO message available interrupt. - */ -#define MBX_CR_RFMAIE_MASK (0x20U) -#define MBX_CR_RFMAIE_SHIFT (5U) -#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) -#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) - -/* - * RFMFIE (RW) - * - * RX fifo message full interrupt enable. - * 1, enable the RX fifo message full interrupt. - * 0, disable the RX fifo message full interrupt. - */ -#define MBX_CR_RFMFIE_MASK (0x10U) -#define MBX_CR_RFMFIE_SHIFT (4U) -#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) -#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) - -/* - * TWMEIE (RW) - * - * TX word message empty interrupt enable. - * 1, enable the TX word massage empty interrupt. - * 0, disable the TX word message empty interrupt. - */ -#define MBX_CR_TWMEIE_MASK (0x2U) -#define MBX_CR_TWMEIE_SHIFT (1U) -#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) -#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) - -/* - * RWMVIE (RW) - * - * RX word message valid interrupt enable. - * 1, enable the RX word massage valid interrupt. - * 0, disable the RX word message valid interrupt. - */ -#define MBX_CR_RWMVIE_MASK (0x1U) -#define MBX_CR_RWMVIE_SHIFT (0U) -#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) -#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * RFVC (RO) - * - * RX FIFO valid message count - */ -#define MBX_SR_RFVC_MASK (0xF00000UL) -#define MBX_SR_RFVC_SHIFT (20U) -#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) - -/* - * TFEC (RO) - * - * TX FIFO empty message word count - */ -#define MBX_SR_TFEC_MASK (0xF0000UL) -#define MBX_SR_TFEC_SHIFT (16U) -#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) - -/* - * ERRRE (W1C) - * - * bus Error for read when rx word message are still invalid, this bit is W1C bit. - * 1, read from word message when the word message are still invalid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRRE_MASK (0x2000U) -#define MBX_SR_ERRRE_SHIFT (13U) -#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) -#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) - -/* - * EWTRF (W1C) - * - * bus Error for write when tx word message are still valid, this bit is W1C bit. - * 1, write to word message when the word message are still valid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTRF_MASK (0x1000U) -#define MBX_SR_EWTRF_SHIFT (12U) -#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) -#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) - -/* - * ERRFE (W1C) - * - * bus Error for read when rx fifo empty, this bit is W1C bit. - * 1, read from a empty rx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRFE_MASK (0x800U) -#define MBX_SR_ERRFE_SHIFT (11U) -#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) -#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) - -/* - * EWTFF (W1C) - * - * bus Error for write when tx fifo full, this bit is W1C bit. - * 1, write to a fulled tx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTFF_MASK (0x400U) -#define MBX_SR_EWTFF_SHIFT (10U) -#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) -#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) - -/* - * EAIVA (W1C) - * - * bus Error for Accessing Invalid Address; this bit is W1C bit. - * 1, read and write to invalid address in the bus of this block, will set this bit. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EAIVA_MASK (0x200U) -#define MBX_SR_EAIVA_SHIFT (9U) -#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) -#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) - -/* - * EW2RO (W1C) - * - * bus Error for Write to Read Only address; this bit is W1C bit. - * 1, write to read only address happened in the bus of this block. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EW2RO_MASK (0x100U) -#define MBX_SR_EW2RO_SHIFT (8U) -#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) -#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) - -/* - * TFMA (RW) - * - * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. - * 1, TXFIFO message buffer has slot available - * 0, no slot available (fifo full) - */ -#define MBX_SR_TFMA_MASK (0x80U) -#define MBX_SR_TFMA_SHIFT (7U) -#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) -#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) - -/* - * TFME (RW) - * - * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. - * 1, no any message data in TXFIFO from other core. - * 0, there are some data in the 4x32 TX FIFO from other core yet. - */ -#define MBX_SR_TFME_MASK (0x40U) -#define MBX_SR_TFME_SHIFT (6U) -#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) -#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) - -/* - * RFMA (RO) - * - * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, no any data in the 4x32 TXFIFO message buffer. - * 0, there are some data in the the 4x32 TXFIFO message buffer already. - */ -#define MBX_SR_RFMA_MASK (0x20U) -#define MBX_SR_RFMA_SHIFT (5U) -#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) - -/* - * RFMF (RO) - * - * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written 4x32 message in the RXFIFO. - * 0, no 4x32 RX FIFO message from other core yet. - */ -#define MBX_SR_RFMF_MASK (0x10U) -#define MBX_SR_RFMF_SHIFT (4U) -#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) - -/* - * TWME (RO) - * - * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, means this core had write word message to TXREG. - * 0, means no valid word message in the TXREG yet. - */ -#define MBX_SR_TWME_MASK (0x2U) -#define MBX_SR_TWME_SHIFT (1U) -#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) - -/* - * RWMV (RO) - * - * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written word message in the RXREG. - * 0, no valid word message yet in the RXREG. - */ -#define MBX_SR_RWMV_MASK (0x1U) -#define MBX_SR_RWMV_SHIFT (0U) -#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) - -/* Bitfield definition for register: TXREG */ -/* - * TXREG (WO) - * - * Transmit word message to other core. - */ -#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) -#define MBX_TXREG_TXREG_SHIFT (0U) -#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) -#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) - -/* Bitfield definition for register: RXREG */ -/* - * RXREG (RO) - * - * Receive word message from other core. - */ -#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) -#define MBX_RXREG_RXREG_SHIFT (0U) -#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) - -/* Bitfield definition for register array: TXWRD */ -/* - * TXFIFO (WO) - * - * TXFIFO for sending message to other core, FIFO size, 4x32 - * can write one of the word address to push data to the FIFO; - * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - */ -#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_TXWRD_TXFIFO_SHIFT (0U) -#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) -#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) - -/* Bitfield definition for register array: RXWRD */ -/* - * RXFIFO (RO) - * - * RXFIFO for receiving message from other core, FIFO size, 4x32 - * can read one of the word address to pop data to the FIFO; - * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - */ -#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_RXWRD_RXFIFO_SHIFT (0U) -#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) - - - -/* TXWRD register group index macro definition */ -#define MBX_TXWRD_TXFIFO0 (0UL) - -/* RXWRD register group index macro definition */ -#define MBX_RXWRD_RXFIFO0 (0UL) - - -#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mcan_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mcan_regs.h deleted file mode 100644 index 0b0c83d3e77..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mcan_regs.h +++ /dev/null @@ -1,2951 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCAN_H -#define HPM_MCAN_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t ENDN; /* 0x4: endian register */ - __R uint8_t RESERVED1[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t DBTP; /* 0xC: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set */ - __RW uint32_t TEST; /* 0x10: test register */ - __RW uint32_t RWD; /* 0x14: ram watchdog */ - __RW uint32_t CCCR; /* 0x18: CC control register */ - __RW uint32_t NBTP; /* 0x1C: nominal bit timing and prescaler register */ - __RW uint32_t TSCC; /* 0x20: timestamp counter configuration */ - __R uint32_t TSCV; /* 0x24: timestamp counter value */ - __RW uint32_t TOCC; /* 0x28: timeout counter configuration */ - __R uint32_t TOCV; /* 0x2C: timeout counter value */ - __R uint8_t RESERVED2[16]; /* 0x30 - 0x3F: Reserved */ - __R uint32_t ECR; /* 0x40: error counter register */ - __R uint32_t PSR; /* 0x44: protocol status register */ - __RW uint32_t TDCR; /* 0x48: transmitter delay compensation */ - __R uint8_t RESERVED3[4]; /* 0x4C - 0x4F: Reserved */ - __RW uint32_t IR; /* 0x50: interrupt register */ - __RW uint32_t IE; /* 0x54: interrupt enable */ - __RW uint32_t ILS; /* 0x58: interrupt line select */ - __RW uint32_t ILE; /* 0x5C: interrupt line enable */ - __R uint8_t RESERVED4[32]; /* 0x60 - 0x7F: Reserved */ - __RW uint32_t GFC; /* 0x80: global filter configuration */ - __RW uint32_t SIDFC; /* 0x84: standard ID filter configuration */ - __RW uint32_t XIDFC; /* 0x88: extended ID filter configuration */ - __R uint8_t RESERVED5[4]; /* 0x8C - 0x8F: Reserved */ - __RW uint32_t XIDAM; /* 0x90: extended id and mask */ - __R uint32_t HPMS; /* 0x94: high priority message status */ - __RW uint32_t NDAT1; /* 0x98: new data1 */ - __RW uint32_t NDAT2; /* 0x9C: new data2 */ - __RW uint32_t RXF0C; /* 0xA0: rx fifo 0 configuration */ - __R uint32_t RXF0S; /* 0xA4: rx fifo 0 status */ - __RW uint32_t RXF0A; /* 0xA8: rx fifo0 acknowledge */ - __RW uint32_t RXBC; /* 0xAC: rx buffer configuration */ - __RW uint32_t RXF1C; /* 0xB0: rx fifo1 configuration */ - __R uint32_t RXF1S; /* 0xB4: rx fifo1 status */ - __RW uint32_t RXF1A; /* 0xB8: rx fifo 1 acknowledge */ - __RW uint32_t RXESC; /* 0xBC: rx buffer/fifo element size configuration */ - __RW uint32_t TXBC; /* 0xC0: tx buffer configuration */ - __R uint32_t TXFQS; /* 0xC4: tx fifo/queue status */ - __RW uint32_t TXESC; /* 0xC8: tx buffer element size configuration */ - __R uint32_t TXBRP; /* 0xCC: tx buffer request pending */ - __RW uint32_t TXBAR; /* 0xD0: tx buffer add request */ - __RW uint32_t TXBCR; /* 0xD4: tx buffer cancellation request */ - __R uint32_t TXBTO; /* 0xD8: tx buffer transmission occurred */ - __R uint32_t TXBCF; /* 0xDC: tx buffer cancellation finished */ - __RW uint32_t TXBTIE; /* 0xE0: tx buffer transmission interrupt enable */ - __RW uint32_t TXBCIE; /* 0xE4: tx buffer cancellation finished interrupt enable */ - __R uint8_t RESERVED6[8]; /* 0xE8 - 0xEF: Reserved */ - __RW uint32_t TXEFC; /* 0xF0: tx event fifo configuration */ - __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ - __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ - __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ - __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0 */ - __R uint32_t CREL; /* 0x240: core release register */ - __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ - __R uint32_t TSS1; /* 0x248: timestamp status1 */ - __R uint32_t TSS2; /* 0x24C: timestamp status2 */ - __R uint32_t ATB; /* 0x250: actual timebase */ - __R uint32_t ATBH; /* 0x254: actual timebase high */ - __R uint8_t RESERVED8[424]; /* 0x258 - 0x3FF: Reserved */ - __RW uint32_t GLB_CTL; /* 0x400: global control */ - __R uint32_t GLB_STATUS; /* 0x404: global status */ - __R uint8_t RESERVED9[4]; /* 0x408 - 0x40B: Reserved */ -} MCAN_Type; - - -/* Bitfield definition for register: ENDN */ -/* - * EVT (R) - * - * Endianness Test Value - * The endianness test value is 0x87654321. - */ -#define MCAN_ENDN_EVT_MASK (0xFFFFFFFFUL) -#define MCAN_ENDN_EVT_SHIFT (0U) -#define MCAN_ENDN_EVT_GET(x) (((uint32_t)(x) & MCAN_ENDN_EVT_MASK) >> MCAN_ENDN_EVT_SHIFT) - -/* Bitfield definition for register: DBTP */ -/* - * TDC (RW) - * - * transmitter delay compensation enable - * 0= Transmitter Delay Compensation disabled - * 1= Transmitter Delay Compensation enabled - */ -#define MCAN_DBTP_TDC_MASK (0x800000UL) -#define MCAN_DBTP_TDC_SHIFT (23U) -#define MCAN_DBTP_TDC_SET(x) (((uint32_t)(x) << MCAN_DBTP_TDC_SHIFT) & MCAN_DBTP_TDC_MASK) -#define MCAN_DBTP_TDC_GET(x) (((uint32_t)(x) & MCAN_DBTP_TDC_MASK) >> MCAN_DBTP_TDC_SHIFT) - -/* - * DBRP (RW) - * - * Data Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. - * When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DBRP_MASK (0x1F0000UL) -#define MCAN_DBTP_DBRP_SHIFT (16U) -#define MCAN_DBTP_DBRP_SET(x) (((uint32_t)(x) << MCAN_DBTP_DBRP_SHIFT) & MCAN_DBTP_DBRP_MASK) -#define MCAN_DBTP_DBRP_GET(x) (((uint32_t)(x) & MCAN_DBTP_DBRP_MASK) >> MCAN_DBTP_DBRP_SHIFT) - -/* - * DTSEG1 (RW) - * - * Data time segment before sample point - * Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG1_MASK (0x1F00U) -#define MCAN_DBTP_DTSEG1_SHIFT (8U) -#define MCAN_DBTP_DTSEG1_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG1_SHIFT) & MCAN_DBTP_DTSEG1_MASK) -#define MCAN_DBTP_DTSEG1_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG1_MASK) >> MCAN_DBTP_DTSEG1_SHIFT) - -/* - * DTSEG2 (RW) - * - * Data time segment after sample point - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG2_MASK (0xF0U) -#define MCAN_DBTP_DTSEG2_SHIFT (4U) -#define MCAN_DBTP_DTSEG2_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG2_SHIFT) & MCAN_DBTP_DTSEG2_MASK) -#define MCAN_DBTP_DTSEG2_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG2_MASK) >> MCAN_DBTP_DTSEG2_SHIFT) - -/* - * DSJW (RW) - * - * Data (Re)Synchronization Jump Width - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DSJW_MASK (0xFU) -#define MCAN_DBTP_DSJW_SHIFT (0U) -#define MCAN_DBTP_DSJW_SET(x) (((uint32_t)(x) << MCAN_DBTP_DSJW_SHIFT) & MCAN_DBTP_DSJW_MASK) -#define MCAN_DBTP_DSJW_GET(x) (((uint32_t)(x) & MCAN_DBTP_DSJW_MASK) >> MCAN_DBTP_DSJW_SHIFT) - -/* Bitfield definition for register: TEST */ -/* - * SVAL (R) - * - * Started Valid - * 0= Value of TXBNS not valid - * 1= Value of TXBNS valid - */ -#define MCAN_TEST_SVAL_MASK (0x200000UL) -#define MCAN_TEST_SVAL_SHIFT (21U) -#define MCAN_TEST_SVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_SVAL_MASK) >> MCAN_TEST_SVAL_SHIFT) - -/* - * TXBNS (R) - * - * Tx Buffer Number Started - * Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNS_MASK (0x1F0000UL) -#define MCAN_TEST_TXBNS_SHIFT (16U) -#define MCAN_TEST_TXBNS_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNS_MASK) >> MCAN_TEST_TXBNS_SHIFT) - -/* - * PVAL (R) - * - * Prepared Valid - * 0= Value of TXBNP not valid - * 1= Value of TXBNP valid - */ -#define MCAN_TEST_PVAL_MASK (0x2000U) -#define MCAN_TEST_PVAL_SHIFT (13U) -#define MCAN_TEST_PVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_PVAL_MASK) >> MCAN_TEST_PVAL_SHIFT) - -/* - * TXBNP (R) - * - * Tx Buffer Number Prepared - * Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNP_MASK (0x1F00U) -#define MCAN_TEST_TXBNP_SHIFT (8U) -#define MCAN_TEST_TXBNP_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNP_MASK) >> MCAN_TEST_TXBNP_SHIFT) - -/* - * RX (R) - * - * Receive Pin - * Monitors the actual value of pin m_can_rx - * 0= The CAN bus is dominant (m_can_rx = ‘0’) - * 1= The CAN bus is recessive (m_can_rx = ‘1’) - */ -#define MCAN_TEST_RX_MASK (0x80U) -#define MCAN_TEST_RX_SHIFT (7U) -#define MCAN_TEST_RX_GET(x) (((uint32_t)(x) & MCAN_TEST_RX_MASK) >> MCAN_TEST_RX_SHIFT) - -/* - * TX (RW) - * - * Control of Transmit Pin - * 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time - * 01 Sample Point can be monitored at pin m_can_tx - * 10 Dominant (‘0’) level at pin m_can_tx - * 11 Recessive (‘1’) at pin m_can_tx - */ -#define MCAN_TEST_TX_MASK (0x60U) -#define MCAN_TEST_TX_SHIFT (5U) -#define MCAN_TEST_TX_SET(x) (((uint32_t)(x) << MCAN_TEST_TX_SHIFT) & MCAN_TEST_TX_MASK) -#define MCAN_TEST_TX_GET(x) (((uint32_t)(x) & MCAN_TEST_TX_MASK) >> MCAN_TEST_TX_SHIFT) - -/* - * LBCK (RW) - * - * Loop Back Mode - * 0= Reset value, Loop Back Mode is disabled - * 1= Loop Back Mode is enabled - */ -#define MCAN_TEST_LBCK_MASK (0x10U) -#define MCAN_TEST_LBCK_SHIFT (4U) -#define MCAN_TEST_LBCK_SET(x) (((uint32_t)(x) << MCAN_TEST_LBCK_SHIFT) & MCAN_TEST_LBCK_MASK) -#define MCAN_TEST_LBCK_GET(x) (((uint32_t)(x) & MCAN_TEST_LBCK_MASK) >> MCAN_TEST_LBCK_SHIFT) - -/* Bitfield definition for register: RWD */ -/* - * WDV (R) - * - * Watchdog Value - * Actual Message RAM Watchdog Counter Value. - */ -#define MCAN_RWD_WDV_MASK (0xFF00U) -#define MCAN_RWD_WDV_SHIFT (8U) -#define MCAN_RWD_WDV_GET(x) (((uint32_t)(x) & MCAN_RWD_WDV_MASK) >> MCAN_RWD_WDV_SHIFT) - -/* - * WDC (RW) - * - * Watchdog Configuration - * Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - */ -#define MCAN_RWD_WDC_MASK (0xFFU) -#define MCAN_RWD_WDC_SHIFT (0U) -#define MCAN_RWD_WDC_SET(x) (((uint32_t)(x) << MCAN_RWD_WDC_SHIFT) & MCAN_RWD_WDC_MASK) -#define MCAN_RWD_WDC_GET(x) (((uint32_t)(x) & MCAN_RWD_WDC_MASK) >> MCAN_RWD_WDC_SHIFT) - -/* Bitfield definition for register: CCCR */ -/* - * NISO (RW) - * - * Non ISO Operation - * If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD - * Specification V1.0. - * 0= CAN FD frame format according to ISO 11898-1:2015 - * 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 - * Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - */ -#define MCAN_CCCR_NISO_MASK (0x8000U) -#define MCAN_CCCR_NISO_SHIFT (15U) -#define MCAN_CCCR_NISO_SET(x) (((uint32_t)(x) << MCAN_CCCR_NISO_SHIFT) & MCAN_CCCR_NISO_MASK) -#define MCAN_CCCR_NISO_GET(x) (((uint32_t)(x) & MCAN_CCCR_NISO_MASK) >> MCAN_CCCR_NISO_SHIFT) - -/* - * TXP (RW) - * - * Transmit Pause - * If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after - * itself has successfully transmitted a frame (see Section 3.5). - * 0= Transmit pause disabled - * 1= Transmit pause enabled - */ -#define MCAN_CCCR_TXP_MASK (0x4000U) -#define MCAN_CCCR_TXP_SHIFT (14U) -#define MCAN_CCCR_TXP_SET(x) (((uint32_t)(x) << MCAN_CCCR_TXP_SHIFT) & MCAN_CCCR_TXP_MASK) -#define MCAN_CCCR_TXP_GET(x) (((uint32_t)(x) & MCAN_CCCR_TXP_MASK) >> MCAN_CCCR_TXP_SHIFT) - -/* - * EFBI (RW) - * - * Edge Filtering during Bus Integration - * 0= Edge filtering disabled - * 1= Two consecutive dominant tq required to detect an edge for hard synchronization - */ -#define MCAN_CCCR_EFBI_MASK (0x2000U) -#define MCAN_CCCR_EFBI_SHIFT (13U) -#define MCAN_CCCR_EFBI_SET(x) (((uint32_t)(x) << MCAN_CCCR_EFBI_SHIFT) & MCAN_CCCR_EFBI_MASK) -#define MCAN_CCCR_EFBI_GET(x) (((uint32_t)(x) & MCAN_CCCR_EFBI_MASK) >> MCAN_CCCR_EFBI_SHIFT) - -/* - * PXHD (RW) - * - * Protocol Exception Handling Disable - * 0= Protocol exception handling enabled - * 1= Protocol exception handling disabled - * Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - */ -#define MCAN_CCCR_PXHD_MASK (0x1000U) -#define MCAN_CCCR_PXHD_SHIFT (12U) -#define MCAN_CCCR_PXHD_SET(x) (((uint32_t)(x) << MCAN_CCCR_PXHD_SHIFT) & MCAN_CCCR_PXHD_MASK) -#define MCAN_CCCR_PXHD_GET(x) (((uint32_t)(x) & MCAN_CCCR_PXHD_MASK) >> MCAN_CCCR_PXHD_SHIFT) - -/* - * WMM (RW) - * - * Wide Message Marker - * Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. - * 0= 8-bit Message Marker used - * 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - */ -#define MCAN_CCCR_WMM_MASK (0x800U) -#define MCAN_CCCR_WMM_SHIFT (11U) -#define MCAN_CCCR_WMM_SET(x) (((uint32_t)(x) << MCAN_CCCR_WMM_SHIFT) & MCAN_CCCR_WMM_MASK) -#define MCAN_CCCR_WMM_GET(x) (((uint32_t)(x) & MCAN_CCCR_WMM_MASK) >> MCAN_CCCR_WMM_SHIFT) - -/* - * UTSU (RW) - * - * Use Timestamping Unit - * When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. - * 0= Internal time stamping - * 1= External time stamping by TSU - * Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. - * In this case bit UTSU is fixed to zero by synthesis. - */ -#define MCAN_CCCR_UTSU_MASK (0x400U) -#define MCAN_CCCR_UTSU_SHIFT (10U) -#define MCAN_CCCR_UTSU_SET(x) (((uint32_t)(x) << MCAN_CCCR_UTSU_SHIFT) & MCAN_CCCR_UTSU_MASK) -#define MCAN_CCCR_UTSU_GET(x) (((uint32_t)(x) & MCAN_CCCR_UTSU_MASK) >> MCAN_CCCR_UTSU_SHIFT) - -/* - * BRSE (RW) - * - * Bit Rate Switch Enable - * 0= Bit rate switching for transmissions disabled - * 1= Bit rate switching for transmissions enabled - * Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - */ -#define MCAN_CCCR_BRSE_MASK (0x200U) -#define MCAN_CCCR_BRSE_SHIFT (9U) -#define MCAN_CCCR_BRSE_SET(x) (((uint32_t)(x) << MCAN_CCCR_BRSE_SHIFT) & MCAN_CCCR_BRSE_MASK) -#define MCAN_CCCR_BRSE_GET(x) (((uint32_t)(x) & MCAN_CCCR_BRSE_MASK) >> MCAN_CCCR_BRSE_SHIFT) - -/* - * FDOE (RW) - * - * FD Operation Enable - * 0= FD operation disabled - * 1= FD operation enabled - */ -#define MCAN_CCCR_FDOE_MASK (0x100U) -#define MCAN_CCCR_FDOE_SHIFT (8U) -#define MCAN_CCCR_FDOE_SET(x) (((uint32_t)(x) << MCAN_CCCR_FDOE_SHIFT) & MCAN_CCCR_FDOE_MASK) -#define MCAN_CCCR_FDOE_GET(x) (((uint32_t)(x) & MCAN_CCCR_FDOE_MASK) >> MCAN_CCCR_FDOE_SHIFT) - -/* - * TEST (RW) - * - * Test Mode Enable - * 0= Normal operation, register TEST holds reset values - * 1= Test Mode, write access to register TEST enabled - */ -#define MCAN_CCCR_TEST_MASK (0x80U) -#define MCAN_CCCR_TEST_SHIFT (7U) -#define MCAN_CCCR_TEST_SET(x) (((uint32_t)(x) << MCAN_CCCR_TEST_SHIFT) & MCAN_CCCR_TEST_MASK) -#define MCAN_CCCR_TEST_GET(x) (((uint32_t)(x) & MCAN_CCCR_TEST_MASK) >> MCAN_CCCR_TEST_SHIFT) - -/* - * DAR (RW) - * - * Disable Automatic Retransmission - * 0= Automatic retransmission of messages not transmitted successfully enabled - * 1= Automatic retransmission disabled - */ -#define MCAN_CCCR_DAR_MASK (0x40U) -#define MCAN_CCCR_DAR_SHIFT (6U) -#define MCAN_CCCR_DAR_SET(x) (((uint32_t)(x) << MCAN_CCCR_DAR_SHIFT) & MCAN_CCCR_DAR_MASK) -#define MCAN_CCCR_DAR_GET(x) (((uint32_t)(x) & MCAN_CCCR_DAR_MASK) >> MCAN_CCCR_DAR_SHIFT) - -/* - * MON (RW) - * - * Bus Monitoring Mode - * Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. - * 0= Bus Monitoring Mode is disabled - * 1= Bus Monitoring Mode is enabled - */ -#define MCAN_CCCR_MON_MASK (0x20U) -#define MCAN_CCCR_MON_SHIFT (5U) -#define MCAN_CCCR_MON_SET(x) (((uint32_t)(x) << MCAN_CCCR_MON_SHIFT) & MCAN_CCCR_MON_MASK) -#define MCAN_CCCR_MON_GET(x) (((uint32_t)(x) & MCAN_CCCR_MON_MASK) >> MCAN_CCCR_MON_SHIFT) - -/* - * CSR (RW) - * - * Clock Stop Request - * 0= No clock stop is requested - * 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - */ -#define MCAN_CCCR_CSR_MASK (0x10U) -#define MCAN_CCCR_CSR_SHIFT (4U) -#define MCAN_CCCR_CSR_SET(x) (((uint32_t)(x) << MCAN_CCCR_CSR_SHIFT) & MCAN_CCCR_CSR_MASK) -#define MCAN_CCCR_CSR_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSR_MASK) >> MCAN_CCCR_CSR_SHIFT) - -/* - * CSA (R) - * - * Clock Stop Acknowledge - * 0= No clock stop acknowledged - * 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - */ -#define MCAN_CCCR_CSA_MASK (0x8U) -#define MCAN_CCCR_CSA_SHIFT (3U) -#define MCAN_CCCR_CSA_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSA_MASK) >> MCAN_CCCR_CSA_SHIFT) - -/* - * ASM (RW) - * - * Restricted Operation Mode - * Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. - * 0= Normal CAN operation - * 1= Restricted Operation Mode active - */ -#define MCAN_CCCR_ASM_MASK (0x4U) -#define MCAN_CCCR_ASM_SHIFT (2U) -#define MCAN_CCCR_ASM_SET(x) (((uint32_t)(x) << MCAN_CCCR_ASM_SHIFT) & MCAN_CCCR_ASM_MASK) -#define MCAN_CCCR_ASM_GET(x) (((uint32_t)(x) & MCAN_CCCR_ASM_MASK) >> MCAN_CCCR_ASM_SHIFT) - -/* - * CCE (RW) - * - * Configuration Change Enable - * 0= The CPU has no write access to the protected configuration registers - * 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - */ -#define MCAN_CCCR_CCE_MASK (0x2U) -#define MCAN_CCCR_CCE_SHIFT (1U) -#define MCAN_CCCR_CCE_SET(x) (((uint32_t)(x) << MCAN_CCCR_CCE_SHIFT) & MCAN_CCCR_CCE_MASK) -#define MCAN_CCCR_CCE_GET(x) (((uint32_t)(x) & MCAN_CCCR_CCE_MASK) >> MCAN_CCCR_CCE_SHIFT) - -/* - * INIT (RW) - * - * Initialization - * 0= Normal Operation - * 1= Initialization is started - */ -#define MCAN_CCCR_INIT_MASK (0x1U) -#define MCAN_CCCR_INIT_SHIFT (0U) -#define MCAN_CCCR_INIT_SET(x) (((uint32_t)(x) << MCAN_CCCR_INIT_SHIFT) & MCAN_CCCR_INIT_MASK) -#define MCAN_CCCR_INIT_GET(x) (((uint32_t)(x) & MCAN_CCCR_INIT_MASK) >> MCAN_CCCR_INIT_SHIFT) - -/* Bitfield definition for register: NBTP */ -/* - * NSJW (RW) - * - * Nominal (Re)Synchronization Jump Width - * Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NSJW_MASK (0xFE000000UL) -#define MCAN_NBTP_NSJW_SHIFT (25U) -#define MCAN_NBTP_NSJW_SET(x) (((uint32_t)(x) << MCAN_NBTP_NSJW_SHIFT) & MCAN_NBTP_NSJW_MASK) -#define MCAN_NBTP_NSJW_GET(x) (((uint32_t)(x) & MCAN_NBTP_NSJW_MASK) >> MCAN_NBTP_NSJW_SHIFT) - -/* - * NBRP (RW) - * - * Nominal Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is - * such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NBRP_MASK (0x1FF0000UL) -#define MCAN_NBTP_NBRP_SHIFT (16U) -#define MCAN_NBTP_NBRP_SET(x) (((uint32_t)(x) << MCAN_NBTP_NBRP_SHIFT) & MCAN_NBTP_NBRP_MASK) -#define MCAN_NBTP_NBRP_GET(x) (((uint32_t)(x) & MCAN_NBTP_NBRP_MASK) >> MCAN_NBTP_NBRP_SHIFT) - -/* - * NTSEG1 (RW) - * - * Nominal Time segment before sample point - * Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG1_MASK (0xFF00U) -#define MCAN_NBTP_NTSEG1_SHIFT (8U) -#define MCAN_NBTP_NTSEG1_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG1_SHIFT) & MCAN_NBTP_NTSEG1_MASK) -#define MCAN_NBTP_NTSEG1_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG1_MASK) >> MCAN_NBTP_NTSEG1_SHIFT) - -/* - * NTSEG2 (RW) - * - * Nominal Time segment after sample point - * Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG2_MASK (0x7FU) -#define MCAN_NBTP_NTSEG2_SHIFT (0U) -#define MCAN_NBTP_NTSEG2_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG2_SHIFT) & MCAN_NBTP_NTSEG2_MASK) -#define MCAN_NBTP_NTSEG2_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG2_MASK) >> MCAN_NBTP_NTSEG2_SHIFT) - -/* Bitfield definition for register: TSCC */ -/* - * TCP (RW) - * - * Timestamp Counter Prescaler - * Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_TSCC_TCP_MASK (0xF0000UL) -#define MCAN_TSCC_TCP_SHIFT (16U) -#define MCAN_TSCC_TCP_SET(x) (((uint32_t)(x) << MCAN_TSCC_TCP_SHIFT) & MCAN_TSCC_TCP_MASK) -#define MCAN_TSCC_TCP_GET(x) (((uint32_t)(x) & MCAN_TSCC_TCP_MASK) >> MCAN_TSCC_TCP_SHIFT) - -/* - * TSS (RW) - * - * timestamp Select - * 00= Timestamp counter value always 0x0000 - * 01= Timestamp counter value incremented according to TCP - * 10= External timestamp counter value used - * 11= Same as “00” - */ -#define MCAN_TSCC_TSS_MASK (0x3U) -#define MCAN_TSCC_TSS_SHIFT (0U) -#define MCAN_TSCC_TSS_SET(x) (((uint32_t)(x) << MCAN_TSCC_TSS_SHIFT) & MCAN_TSCC_TSS_MASK) -#define MCAN_TSCC_TSS_GET(x) (((uint32_t)(x) & MCAN_TSCC_TSS_MASK) >> MCAN_TSCC_TSS_SHIFT) - -/* Bitfield definition for register: TSCV */ -/* - * TSC (RC) - * - * Timestamp Counter - * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - */ -#define MCAN_TSCV_TSC_MASK (0xFFFFU) -#define MCAN_TSCV_TSC_SHIFT (0U) -#define MCAN_TSCV_TSC_GET(x) (((uint32_t)(x) & MCAN_TSCV_TSC_MASK) >> MCAN_TSCV_TSC_SHIFT) - -/* Bitfield definition for register: TOCC */ -/* - * TOP (RW) - * - * Timeout Period - * Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - */ -#define MCAN_TOCC_TOP_MASK (0xFFFF0000UL) -#define MCAN_TOCC_TOP_SHIFT (16U) -#define MCAN_TOCC_TOP_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOP_SHIFT) & MCAN_TOCC_TOP_MASK) -#define MCAN_TOCC_TOP_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOP_MASK) >> MCAN_TOCC_TOP_SHIFT) - -/* - * TOS (RW) - * - * Timeout Select - * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. - * When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. - * 00= Continuous operation - * 01= Timeout controlled by Tx Event FIFO - * 10= Timeout controlled by Rx FIFO 0 - * 11= Timeout controlled by Rx FIFO 1 - */ -#define MCAN_TOCC_TOS_MASK (0x6U) -#define MCAN_TOCC_TOS_SHIFT (1U) -#define MCAN_TOCC_TOS_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOS_SHIFT) & MCAN_TOCC_TOS_MASK) -#define MCAN_TOCC_TOS_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOS_MASK) >> MCAN_TOCC_TOS_SHIFT) - -/* - * RP (RW) - * - * Enable Timeout Counter - * 0= Timeout Counter disabled - * 1= Timeout Counter enabled - */ -#define MCAN_TOCC_RP_MASK (0x1U) -#define MCAN_TOCC_RP_SHIFT (0U) -#define MCAN_TOCC_RP_SET(x) (((uint32_t)(x) << MCAN_TOCC_RP_SHIFT) & MCAN_TOCC_RP_MASK) -#define MCAN_TOCC_RP_GET(x) (((uint32_t)(x) & MCAN_TOCC_RP_MASK) >> MCAN_TOCC_RP_SHIFT) - -/* Bitfield definition for register: TOCV */ -/* - * TOC (RC) - * - * Timeout Counter - * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. - * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - */ -#define MCAN_TOCV_TOC_MASK (0xFFFFU) -#define MCAN_TOCV_TOC_SHIFT (0U) -#define MCAN_TOCV_TOC_GET(x) (((uint32_t)(x) & MCAN_TOCV_TOC_MASK) >> MCAN_TOCV_TOC_SHIFT) - -/* Bitfield definition for register: ECR */ -/* - * CEL (X) - * - * CAN Error Logging - * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. - * The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. - * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. - * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - */ -#define MCAN_ECR_CEL_MASK (0xFF0000UL) -#define MCAN_ECR_CEL_SHIFT (16U) -#define MCAN_ECR_CEL_GET(x) (((uint32_t)(x) & MCAN_ECR_CEL_MASK) >> MCAN_ECR_CEL_SHIFT) - -/* - * RP (R) - * - * Receive Error Passive - * 0= The Receive Error Counter is below the error passive level of 128 - * 1= The Receive Error Counter has reached the error passive level of 128 - */ -#define MCAN_ECR_RP_MASK (0x8000U) -#define MCAN_ECR_RP_SHIFT (15U) -#define MCAN_ECR_RP_GET(x) (((uint32_t)(x) & MCAN_ECR_RP_MASK) >> MCAN_ECR_RP_SHIFT) - -/* - * REC (R) - * - * Receive Error Counter - * Actual state of the Receive Error Counter, values between 0 and 127 - */ -#define MCAN_ECR_REC_MASK (0x7F00U) -#define MCAN_ECR_REC_SHIFT (8U) -#define MCAN_ECR_REC_GET(x) (((uint32_t)(x) & MCAN_ECR_REC_MASK) >> MCAN_ECR_REC_SHIFT) - -/* - * TEC (R) - * - * Transmit Error Counter - * Actual state of the Transmit Error Counter, values between 0 and 255 - * Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - */ -#define MCAN_ECR_TEC_MASK (0xFFU) -#define MCAN_ECR_TEC_SHIFT (0U) -#define MCAN_ECR_TEC_GET(x) (((uint32_t)(x) & MCAN_ECR_TEC_MASK) >> MCAN_ECR_TEC_SHIFT) - -/* Bitfield definition for register: PSR */ -/* - * TDCV (R) - * - * Transmitter Delay Compensation Value - * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. - * The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_PSR_TDCV_MASK (0x7F0000UL) -#define MCAN_PSR_TDCV_SHIFT (16U) -#define MCAN_PSR_TDCV_GET(x) (((uint32_t)(x) & MCAN_PSR_TDCV_MASK) >> MCAN_PSR_TDCV_SHIFT) - -/* - * PXE (X) - * - * Protocol Exception Event - * 0= No protocol exception event occurred since last read access - * 1= Protocol exception event occurred - * Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_PXE_MASK (0x4000U) -#define MCAN_PSR_PXE_SHIFT (14U) -#define MCAN_PSR_PXE_GET(x) (((uint32_t)(x) & MCAN_PSR_PXE_MASK) >> MCAN_PSR_PXE_SHIFT) - -/* - * RFDF (X) - * - * Received a CAN FD Message - * This bit is set independent of acceptance filtering. - * 0= Since this bit was reset by the CPU, no CAN FD message has been received - * 1= Message in CAN FD format with FDF flag set has been received - * Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RFDF_MASK (0x2000U) -#define MCAN_PSR_RFDF_SHIFT (13U) -#define MCAN_PSR_RFDF_GET(x) (((uint32_t)(x) & MCAN_PSR_RFDF_MASK) >> MCAN_PSR_RFDF_SHIFT) - -/* - * RBRS (X) - * - * BRS flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its BRS flag set - * 1= Last received CAN FD message had its BRS flag set - * Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RBRS_MASK (0x1000U) -#define MCAN_PSR_RBRS_SHIFT (12U) -#define MCAN_PSR_RBRS_GET(x) (((uint32_t)(x) & MCAN_PSR_RBRS_MASK) >> MCAN_PSR_RBRS_SHIFT) - -/* - * RESI (X) - * - * ESI flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its ESI flag set - * 1= Last received CAN FD message had its ESI flag set - * Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RESI_MASK (0x800U) -#define MCAN_PSR_RESI_SHIFT (11U) -#define MCAN_PSR_RESI_GET(x) (((uint32_t)(x) & MCAN_PSR_RESI_MASK) >> MCAN_PSR_RESI_SHIFT) - -/* - * DLEC (S) - * - * Data Phase Last Error Code - * Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with - * its BRS flag set has been transferred (reception or transmission) without error. - * Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_DLEC_MASK (0x700U) -#define MCAN_PSR_DLEC_SHIFT (8U) -#define MCAN_PSR_DLEC_GET(x) (((uint32_t)(x) & MCAN_PSR_DLEC_MASK) >> MCAN_PSR_DLEC_SHIFT) - -/* - * BO (R) - * - * Bus_Off Status - * 0= The M_CAN is not Bus_Off - * 1= The M_CAN is in Bus_Off state - */ -#define MCAN_PSR_BO_MASK (0x80U) -#define MCAN_PSR_BO_SHIFT (7U) -#define MCAN_PSR_BO_GET(x) (((uint32_t)(x) & MCAN_PSR_BO_MASK) >> MCAN_PSR_BO_SHIFT) - -/* - * EW (R) - * - * Warning Status - * 0= Both error counters are below the Error_Warning limit of 96 - * 1= At least one of error counter has reached the Error_Warning limit of 96 - */ -#define MCAN_PSR_EW_MASK (0x40U) -#define MCAN_PSR_EW_SHIFT (6U) -#define MCAN_PSR_EW_GET(x) (((uint32_t)(x) & MCAN_PSR_EW_MASK) >> MCAN_PSR_EW_SHIFT) - -/* - * EP (R) - * - * Error Passive - * 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected - * 1= The M_CAN is in the Error_Passive state - */ -#define MCAN_PSR_EP_MASK (0x20U) -#define MCAN_PSR_EP_SHIFT (5U) -#define MCAN_PSR_EP_GET(x) (((uint32_t)(x) & MCAN_PSR_EP_MASK) >> MCAN_PSR_EP_SHIFT) - -/* - * ACT (R) - * - * Activity - * Monitors the module’s CAN communication state. - * 00= Synchronizing - node is synchronizing on CAN communication - * 01= Idle - node is neither receiver nor transmitter - * 10= Receiver - node is operating as receiver - * 11= Transmitter - node is operating as transmitter - * Note: ACT is set to “00” by a Protocol Exception Event. - */ -#define MCAN_PSR_ACT_MASK (0x18U) -#define MCAN_PSR_ACT_SHIFT (3U) -#define MCAN_PSR_ACT_GET(x) (((uint32_t)(x) & MCAN_PSR_ACT_MASK) >> MCAN_PSR_ACT_SHIFT) - -/* - * LEC (S) - * - * Last Error Code - * The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. - * 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. - * 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. - * 2= Form Error: A fixed format part of a received frame has the wrong format. - * 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. - * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), - * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus - * value was dominant. - * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - * During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at - * dominant or continuously disturbed). - * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. - * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. - * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. - * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - * Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. - * At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, - * enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. - * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_LEC_MASK (0x7U) -#define MCAN_PSR_LEC_SHIFT (0U) -#define MCAN_PSR_LEC_GET(x) (((uint32_t)(x) & MCAN_PSR_LEC_MASK) >> MCAN_PSR_LEC_SHIFT) - -/* Bitfield definition for register: TDCR */ -/* - * TDCO (RW) - * - * Transmitter Delay Compensation SSP Offset - * Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCO_MASK (0x7F00U) -#define MCAN_TDCR_TDCO_SHIFT (8U) -#define MCAN_TDCR_TDCO_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCO_SHIFT) & MCAN_TDCR_TDCO_MASK) -#define MCAN_TDCR_TDCO_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCO_MASK) >> MCAN_TDCR_TDCO_SHIFT) - -/* - * TDCF (RW) - * - * Transmitter Delay Compensation Filter Window Length - * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. - * The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCF_MASK (0x7FU) -#define MCAN_TDCR_TDCF_SHIFT (0U) -#define MCAN_TDCR_TDCF_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCF_SHIFT) & MCAN_TDCR_TDCF_MASK) -#define MCAN_TDCR_TDCF_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCF_MASK) >> MCAN_TDCR_TDCF_SHIFT) - -/* Bitfield definition for register: IR */ -/* - * ARA (RW) - * - * Access to Reserved Address - * 0= No access to reserved address occurred - * 1= Access to reserved address occurred - */ -#define MCAN_IR_ARA_MASK (0x20000000UL) -#define MCAN_IR_ARA_SHIFT (29U) -#define MCAN_IR_ARA_SET(x) (((uint32_t)(x) << MCAN_IR_ARA_SHIFT) & MCAN_IR_ARA_MASK) -#define MCAN_IR_ARA_GET(x) (((uint32_t)(x) & MCAN_IR_ARA_MASK) >> MCAN_IR_ARA_SHIFT) - -/* - * PED (RW) - * - * Protocol Error in Data Phase (Data Bit Time is used) - * 0= No protocol error in data phase - * 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - */ -#define MCAN_IR_PED_MASK (0x10000000UL) -#define MCAN_IR_PED_SHIFT (28U) -#define MCAN_IR_PED_SET(x) (((uint32_t)(x) << MCAN_IR_PED_SHIFT) & MCAN_IR_PED_MASK) -#define MCAN_IR_PED_GET(x) (((uint32_t)(x) & MCAN_IR_PED_MASK) >> MCAN_IR_PED_SHIFT) - -/* - * PEA (RW) - * - * Protocol Error in Arbitration Phase (Nominal Bit Time is used) - * 0= No protocol error in arbitration phase - * 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - */ -#define MCAN_IR_PEA_MASK (0x8000000UL) -#define MCAN_IR_PEA_SHIFT (27U) -#define MCAN_IR_PEA_SET(x) (((uint32_t)(x) << MCAN_IR_PEA_SHIFT) & MCAN_IR_PEA_MASK) -#define MCAN_IR_PEA_GET(x) (((uint32_t)(x) & MCAN_IR_PEA_MASK) >> MCAN_IR_PEA_SHIFT) - -/* - * WDI (RW) - * - * Watchdog Interrupt - * 0= No Message RAM Watchdog event occurred - * 1= Message RAM Watchdog event due to missing READY - */ -#define MCAN_IR_WDI_MASK (0x4000000UL) -#define MCAN_IR_WDI_SHIFT (26U) -#define MCAN_IR_WDI_SET(x) (((uint32_t)(x) << MCAN_IR_WDI_SHIFT) & MCAN_IR_WDI_MASK) -#define MCAN_IR_WDI_GET(x) (((uint32_t)(x) & MCAN_IR_WDI_MASK) >> MCAN_IR_WDI_SHIFT) - -/* - * BO (RW) - * - * Bus_Off Status - * 0= Bus_Off status unchanged - * 1= Bus_Off status changed - */ -#define MCAN_IR_BO_MASK (0x2000000UL) -#define MCAN_IR_BO_SHIFT (25U) -#define MCAN_IR_BO_SET(x) (((uint32_t)(x) << MCAN_IR_BO_SHIFT) & MCAN_IR_BO_MASK) -#define MCAN_IR_BO_GET(x) (((uint32_t)(x) & MCAN_IR_BO_MASK) >> MCAN_IR_BO_SHIFT) - -/* - * EW (RW) - * - * Warning Status - * 0= Error_Warning status unchanged - * 1= Error_Warning status changed - */ -#define MCAN_IR_EW_MASK (0x1000000UL) -#define MCAN_IR_EW_SHIFT (24U) -#define MCAN_IR_EW_SET(x) (((uint32_t)(x) << MCAN_IR_EW_SHIFT) & MCAN_IR_EW_MASK) -#define MCAN_IR_EW_GET(x) (((uint32_t)(x) & MCAN_IR_EW_MASK) >> MCAN_IR_EW_SHIFT) - -/* - * EP (RW) - * - * Error Passive - * 0= Error_Passive status unchanged - * 1= Error_Passive status changed - */ -#define MCAN_IR_EP_MASK (0x800000UL) -#define MCAN_IR_EP_SHIFT (23U) -#define MCAN_IR_EP_SET(x) (((uint32_t)(x) << MCAN_IR_EP_SHIFT) & MCAN_IR_EP_MASK) -#define MCAN_IR_EP_GET(x) (((uint32_t)(x) & MCAN_IR_EP_MASK) >> MCAN_IR_EP_SHIFT) - -/* - * ELO (RW) - * - * Error Logging Overflow - * 0= CAN Error Logging Counter did not overflow - * 1= Overflow of CAN Error Logging Counter occurred - */ -#define MCAN_IR_ELO_MASK (0x400000UL) -#define MCAN_IR_ELO_SHIFT (22U) -#define MCAN_IR_ELO_SET(x) (((uint32_t)(x) << MCAN_IR_ELO_SHIFT) & MCAN_IR_ELO_MASK) -#define MCAN_IR_ELO_GET(x) (((uint32_t)(x) & MCAN_IR_ELO_MASK) >> MCAN_IR_ELO_SHIFT) - -/* - * BEU (RW) - * - * Bit Error Uncorrected - * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. - * An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected, uncorrected (e.g. parity logic) - */ -#define MCAN_IR_BEU_MASK (0x200000UL) -#define MCAN_IR_BEU_SHIFT (21U) -#define MCAN_IR_BEU_SET(x) (((uint32_t)(x) << MCAN_IR_BEU_SHIFT) & MCAN_IR_BEU_MASK) -#define MCAN_IR_BEU_GET(x) (((uint32_t)(x) & MCAN_IR_BEU_MASK) >> MCAN_IR_BEU_SHIFT) - -/* - * BEC (RW) - * - * Bit Error Corrected - * Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected and corrected (e.g. ECC) - */ -#define MCAN_IR_BEC_MASK (0x100000UL) -#define MCAN_IR_BEC_SHIFT (20U) -#define MCAN_IR_BEC_SET(x) (((uint32_t)(x) << MCAN_IR_BEC_SHIFT) & MCAN_IR_BEC_MASK) -#define MCAN_IR_BEC_GET(x) (((uint32_t)(x) & MCAN_IR_BEC_MASK) >> MCAN_IR_BEC_SHIFT) - -/* - * DRX (RW) - * - * Message stored to Dedicated Rx Buffer - * The flag is set whenever a received message has been stored into a dedicated Rx Buffer. - * 0= No Rx Buffer updated - * 1= At least one received message stored into an Rx Buffer - */ -#define MCAN_IR_DRX_MASK (0x80000UL) -#define MCAN_IR_DRX_SHIFT (19U) -#define MCAN_IR_DRX_SET(x) (((uint32_t)(x) << MCAN_IR_DRX_SHIFT) & MCAN_IR_DRX_MASK) -#define MCAN_IR_DRX_GET(x) (((uint32_t)(x) & MCAN_IR_DRX_MASK) >> MCAN_IR_DRX_SHIFT) - -/* - * TOO (RW) - * - * Timeout Occurred - * 0= No timeout - * 1= Timeout reached - */ -#define MCAN_IR_TOO_MASK (0x40000UL) -#define MCAN_IR_TOO_SHIFT (18U) -#define MCAN_IR_TOO_SET(x) (((uint32_t)(x) << MCAN_IR_TOO_SHIFT) & MCAN_IR_TOO_MASK) -#define MCAN_IR_TOO_GET(x) (((uint32_t)(x) & MCAN_IR_TOO_MASK) >> MCAN_IR_TOO_SHIFT) - -/* - * MRAF (RW) - * - * Message RAM Access Failure - * The flag is set, when the Rx Handler - * .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message - * storage is aborted and the Rx Handler starts processing of the following message. - * .was not able to write a message to the Message RAM. In this case message storage is aborted. - * In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. - * The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the - * M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. - * 0= No Message RAM access failure occurred - * 1= Message RAM access failure occurred - */ -#define MCAN_IR_MRAF_MASK (0x20000UL) -#define MCAN_IR_MRAF_SHIFT (17U) -#define MCAN_IR_MRAF_SET(x) (((uint32_t)(x) << MCAN_IR_MRAF_SHIFT) & MCAN_IR_MRAF_MASK) -#define MCAN_IR_MRAF_GET(x) (((uint32_t)(x) & MCAN_IR_MRAF_MASK) >> MCAN_IR_MRAF_SHIFT) - -/* - * TSW (RW) - * - * Timestamp Wraparound - * 0= No timestamp counter wrap-around - * 1= Timestamp counter wrapped around - */ -#define MCAN_IR_TSW_MASK (0x10000UL) -#define MCAN_IR_TSW_SHIFT (16U) -#define MCAN_IR_TSW_SET(x) (((uint32_t)(x) << MCAN_IR_TSW_SHIFT) & MCAN_IR_TSW_MASK) -#define MCAN_IR_TSW_GET(x) (((uint32_t)(x) & MCAN_IR_TSW_MASK) >> MCAN_IR_TSW_SHIFT) - -/* - * TEFL (RW) - * - * Tx Event FIFO Element Lost - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - */ -#define MCAN_IR_TEFL_MASK (0x8000U) -#define MCAN_IR_TEFL_SHIFT (15U) -#define MCAN_IR_TEFL_SET(x) (((uint32_t)(x) << MCAN_IR_TEFL_SHIFT) & MCAN_IR_TEFL_MASK) -#define MCAN_IR_TEFL_GET(x) (((uint32_t)(x) & MCAN_IR_TEFL_MASK) >> MCAN_IR_TEFL_SHIFT) - -/* - * TEFF (RW) - * - * Tx Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_IR_TEFF_MASK (0x4000U) -#define MCAN_IR_TEFF_SHIFT (14U) -#define MCAN_IR_TEFF_SET(x) (((uint32_t)(x) << MCAN_IR_TEFF_SHIFT) & MCAN_IR_TEFF_MASK) -#define MCAN_IR_TEFF_GET(x) (((uint32_t)(x) & MCAN_IR_TEFF_MASK) >> MCAN_IR_TEFF_SHIFT) - -/* - * TEFW (RW) - * - * Tx Event FIFO Watermark Reached - * 0= Tx Event FIFO fill level below watermark - * 1= Tx Event FIFO fill level reached watermark - */ -#define MCAN_IR_TEFW_MASK (0x2000U) -#define MCAN_IR_TEFW_SHIFT (13U) -#define MCAN_IR_TEFW_SET(x) (((uint32_t)(x) << MCAN_IR_TEFW_SHIFT) & MCAN_IR_TEFW_MASK) -#define MCAN_IR_TEFW_GET(x) (((uint32_t)(x) & MCAN_IR_TEFW_MASK) >> MCAN_IR_TEFW_SHIFT) - -/* - * TEFN (RW) - * - * Tx Event FIFO New Entry - * 0= Tx Event FIFO unchanged - * 1= Tx Handler wrote Tx Event FIFO element - */ -#define MCAN_IR_TEFN_MASK (0x1000U) -#define MCAN_IR_TEFN_SHIFT (12U) -#define MCAN_IR_TEFN_SET(x) (((uint32_t)(x) << MCAN_IR_TEFN_SHIFT) & MCAN_IR_TEFN_MASK) -#define MCAN_IR_TEFN_GET(x) (((uint32_t)(x) & MCAN_IR_TEFN_MASK) >> MCAN_IR_TEFN_SHIFT) - -/* - * TFE (RW) - * - * Tx FIFO Empty - * 0= Tx FIFO non-empty - * 1= Tx FIFO empty - */ -#define MCAN_IR_TFE_MASK (0x800U) -#define MCAN_IR_TFE_SHIFT (11U) -#define MCAN_IR_TFE_SET(x) (((uint32_t)(x) << MCAN_IR_TFE_SHIFT) & MCAN_IR_TFE_MASK) -#define MCAN_IR_TFE_GET(x) (((uint32_t)(x) & MCAN_IR_TFE_MASK) >> MCAN_IR_TFE_SHIFT) - -/* - * TCF (RW) - * - * Transmission Cancellation Finished - * 0= No transmission cancellation finished - * 1= Transmission cancellation finished - */ -#define MCAN_IR_TCF_MASK (0x400U) -#define MCAN_IR_TCF_SHIFT (10U) -#define MCAN_IR_TCF_SET(x) (((uint32_t)(x) << MCAN_IR_TCF_SHIFT) & MCAN_IR_TCF_MASK) -#define MCAN_IR_TCF_GET(x) (((uint32_t)(x) & MCAN_IR_TCF_MASK) >> MCAN_IR_TCF_SHIFT) - -/* - * TC (RW) - * - * Transmission Completed - * 0= No transmission completed - * 1= Transmission completed - */ -#define MCAN_IR_TC_MASK (0x200U) -#define MCAN_IR_TC_SHIFT (9U) -#define MCAN_IR_TC_SET(x) (((uint32_t)(x) << MCAN_IR_TC_SHIFT) & MCAN_IR_TC_MASK) -#define MCAN_IR_TC_GET(x) (((uint32_t)(x) & MCAN_IR_TC_MASK) >> MCAN_IR_TC_SHIFT) - -/* - * HPM (RW) - * - * High Priority Message - * 0= No high priority message received - * 1= High priority message received - */ -#define MCAN_IR_HPM_MASK (0x100U) -#define MCAN_IR_HPM_SHIFT (8U) -#define MCAN_IR_HPM_SET(x) (((uint32_t)(x) << MCAN_IR_HPM_SHIFT) & MCAN_IR_HPM_MASK) -#define MCAN_IR_HPM_GET(x) (((uint32_t)(x) & MCAN_IR_HPM_MASK) >> MCAN_IR_HPM_SHIFT) - -/* - * RF1L (RW) - * - * Rx FIFO 1 Message Lost - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - */ -#define MCAN_IR_RF1L_MASK (0x80U) -#define MCAN_IR_RF1L_SHIFT (7U) -#define MCAN_IR_RF1L_SET(x) (((uint32_t)(x) << MCAN_IR_RF1L_SHIFT) & MCAN_IR_RF1L_MASK) -#define MCAN_IR_RF1L_GET(x) (((uint32_t)(x) & MCAN_IR_RF1L_MASK) >> MCAN_IR_RF1L_SHIFT) - -/* - * RF1F (RW) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_IR_RF1F_MASK (0x40U) -#define MCAN_IR_RF1F_SHIFT (6U) -#define MCAN_IR_RF1F_SET(x) (((uint32_t)(x) << MCAN_IR_RF1F_SHIFT) & MCAN_IR_RF1F_MASK) -#define MCAN_IR_RF1F_GET(x) (((uint32_t)(x) & MCAN_IR_RF1F_MASK) >> MCAN_IR_RF1F_SHIFT) - -/* - * RF1W (RW) - * - * Rx FIFO 1 Watermark Reached - * 0= Rx FIFO 1 fill level below watermark - * 1= Rx FIFO 1 fill level reached watermark - */ -#define MCAN_IR_RF1W_MASK (0x20U) -#define MCAN_IR_RF1W_SHIFT (5U) -#define MCAN_IR_RF1W_SET(x) (((uint32_t)(x) << MCAN_IR_RF1W_SHIFT) & MCAN_IR_RF1W_MASK) -#define MCAN_IR_RF1W_GET(x) (((uint32_t)(x) & MCAN_IR_RF1W_MASK) >> MCAN_IR_RF1W_SHIFT) - -/* - * RF1N (RW) - * - * Rx FIFO 1 New Message - * 0= No new message written to Rx FIFO 1 - * 1= New message written to Rx FIFO 1 - */ -#define MCAN_IR_RF1N_MASK (0x10U) -#define MCAN_IR_RF1N_SHIFT (4U) -#define MCAN_IR_RF1N_SET(x) (((uint32_t)(x) << MCAN_IR_RF1N_SHIFT) & MCAN_IR_RF1N_MASK) -#define MCAN_IR_RF1N_GET(x) (((uint32_t)(x) & MCAN_IR_RF1N_MASK) >> MCAN_IR_RF1N_SHIFT) - -/* - * RF0L (RW) - * - * Rx FIFO 0 Message Lost - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - */ -#define MCAN_IR_RF0L_MASK (0x8U) -#define MCAN_IR_RF0L_SHIFT (3U) -#define MCAN_IR_RF0L_SET(x) (((uint32_t)(x) << MCAN_IR_RF0L_SHIFT) & MCAN_IR_RF0L_MASK) -#define MCAN_IR_RF0L_GET(x) (((uint32_t)(x) & MCAN_IR_RF0L_MASK) >> MCAN_IR_RF0L_SHIFT) - -/* - * RF0F (RW) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_IR_RF0F_MASK (0x4U) -#define MCAN_IR_RF0F_SHIFT (2U) -#define MCAN_IR_RF0F_SET(x) (((uint32_t)(x) << MCAN_IR_RF0F_SHIFT) & MCAN_IR_RF0F_MASK) -#define MCAN_IR_RF0F_GET(x) (((uint32_t)(x) & MCAN_IR_RF0F_MASK) >> MCAN_IR_RF0F_SHIFT) - -/* - * RF0W (RW) - * - * Rx FIFO 0 Watermark Reached - * 0= Rx FIFO 0 fill level below watermark - * 1= Rx FIFO 0 fill level reached watermark - */ -#define MCAN_IR_RF0W_MASK (0x2U) -#define MCAN_IR_RF0W_SHIFT (1U) -#define MCAN_IR_RF0W_SET(x) (((uint32_t)(x) << MCAN_IR_RF0W_SHIFT) & MCAN_IR_RF0W_MASK) -#define MCAN_IR_RF0W_GET(x) (((uint32_t)(x) & MCAN_IR_RF0W_MASK) >> MCAN_IR_RF0W_SHIFT) - -/* - * RF0N (RW) - * - * Rx FIFO 0 New Message - * 0= No new message written to Rx FIFO 0 - * 1= New message written to Rx FIFO 0 - */ -#define MCAN_IR_RF0N_MASK (0x1U) -#define MCAN_IR_RF0N_SHIFT (0U) -#define MCAN_IR_RF0N_SET(x) (((uint32_t)(x) << MCAN_IR_RF0N_SHIFT) & MCAN_IR_RF0N_MASK) -#define MCAN_IR_RF0N_GET(x) (((uint32_t)(x) & MCAN_IR_RF0N_MASK) >> MCAN_IR_RF0N_SHIFT) - -/* Bitfield definition for register: IE */ -/* - * ARAE (RW) - * - * Access to Reserved Address Enable - */ -#define MCAN_IE_ARAE_MASK (0x20000000UL) -#define MCAN_IE_ARAE_SHIFT (29U) -#define MCAN_IE_ARAE_SET(x) (((uint32_t)(x) << MCAN_IE_ARAE_SHIFT) & MCAN_IE_ARAE_MASK) -#define MCAN_IE_ARAE_GET(x) (((uint32_t)(x) & MCAN_IE_ARAE_MASK) >> MCAN_IE_ARAE_SHIFT) - -/* - * PEDE (RW) - * - * Protocol Error in Data Phase Enable - */ -#define MCAN_IE_PEDE_MASK (0x10000000UL) -#define MCAN_IE_PEDE_SHIFT (28U) -#define MCAN_IE_PEDE_SET(x) (((uint32_t)(x) << MCAN_IE_PEDE_SHIFT) & MCAN_IE_PEDE_MASK) -#define MCAN_IE_PEDE_GET(x) (((uint32_t)(x) & MCAN_IE_PEDE_MASK) >> MCAN_IE_PEDE_SHIFT) - -/* - * PEAE (RW) - * - * Protocol Error in Arbitration Phase Enable - */ -#define MCAN_IE_PEAE_MASK (0x8000000UL) -#define MCAN_IE_PEAE_SHIFT (27U) -#define MCAN_IE_PEAE_SET(x) (((uint32_t)(x) << MCAN_IE_PEAE_SHIFT) & MCAN_IE_PEAE_MASK) -#define MCAN_IE_PEAE_GET(x) (((uint32_t)(x) & MCAN_IE_PEAE_MASK) >> MCAN_IE_PEAE_SHIFT) - -/* - * WDIE (RW) - * - * Watchdog Interrupt Enable - */ -#define MCAN_IE_WDIE_MASK (0x4000000UL) -#define MCAN_IE_WDIE_SHIFT (26U) -#define MCAN_IE_WDIE_SET(x) (((uint32_t)(x) << MCAN_IE_WDIE_SHIFT) & MCAN_IE_WDIE_MASK) -#define MCAN_IE_WDIE_GET(x) (((uint32_t)(x) & MCAN_IE_WDIE_MASK) >> MCAN_IE_WDIE_SHIFT) - -/* - * BOE (RW) - * - * Bus_Off Status Interrupt Enable - */ -#define MCAN_IE_BOE_MASK (0x2000000UL) -#define MCAN_IE_BOE_SHIFT (25U) -#define MCAN_IE_BOE_SET(x) (((uint32_t)(x) << MCAN_IE_BOE_SHIFT) & MCAN_IE_BOE_MASK) -#define MCAN_IE_BOE_GET(x) (((uint32_t)(x) & MCAN_IE_BOE_MASK) >> MCAN_IE_BOE_SHIFT) - -/* - * EWE (RW) - * - * Warning Status Interrupt Enable - */ -#define MCAN_IE_EWE_MASK (0x1000000UL) -#define MCAN_IE_EWE_SHIFT (24U) -#define MCAN_IE_EWE_SET(x) (((uint32_t)(x) << MCAN_IE_EWE_SHIFT) & MCAN_IE_EWE_MASK) -#define MCAN_IE_EWE_GET(x) (((uint32_t)(x) & MCAN_IE_EWE_MASK) >> MCAN_IE_EWE_SHIFT) - -/* - * EPE (RW) - * - * Error Passive Interrupt Enable - */ -#define MCAN_IE_EPE_MASK (0x800000UL) -#define MCAN_IE_EPE_SHIFT (23U) -#define MCAN_IE_EPE_SET(x) (((uint32_t)(x) << MCAN_IE_EPE_SHIFT) & MCAN_IE_EPE_MASK) -#define MCAN_IE_EPE_GET(x) (((uint32_t)(x) & MCAN_IE_EPE_MASK) >> MCAN_IE_EPE_SHIFT) - -/* - * ELOE (RW) - * - * Error Logging Overflow Interrupt Enable - */ -#define MCAN_IE_ELOE_MASK (0x400000UL) -#define MCAN_IE_ELOE_SHIFT (22U) -#define MCAN_IE_ELOE_SET(x) (((uint32_t)(x) << MCAN_IE_ELOE_SHIFT) & MCAN_IE_ELOE_MASK) -#define MCAN_IE_ELOE_GET(x) (((uint32_t)(x) & MCAN_IE_ELOE_MASK) >> MCAN_IE_ELOE_SHIFT) - -/* - * BEUE (RW) - * - * Bit Error Uncorrected Interrupt Enable - */ -#define MCAN_IE_BEUE_MASK (0x200000UL) -#define MCAN_IE_BEUE_SHIFT (21U) -#define MCAN_IE_BEUE_SET(x) (((uint32_t)(x) << MCAN_IE_BEUE_SHIFT) & MCAN_IE_BEUE_MASK) -#define MCAN_IE_BEUE_GET(x) (((uint32_t)(x) & MCAN_IE_BEUE_MASK) >> MCAN_IE_BEUE_SHIFT) - -/* - * BECE (RW) - * - * Bit Error Corrected Interrupt Enable - */ -#define MCAN_IE_BECE_MASK (0x100000UL) -#define MCAN_IE_BECE_SHIFT (20U) -#define MCAN_IE_BECE_SET(x) (((uint32_t)(x) << MCAN_IE_BECE_SHIFT) & MCAN_IE_BECE_MASK) -#define MCAN_IE_BECE_GET(x) (((uint32_t)(x) & MCAN_IE_BECE_MASK) >> MCAN_IE_BECE_SHIFT) - -/* - * DRXE (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Enable - */ -#define MCAN_IE_DRXE_MASK (0x80000UL) -#define MCAN_IE_DRXE_SHIFT (19U) -#define MCAN_IE_DRXE_SET(x) (((uint32_t)(x) << MCAN_IE_DRXE_SHIFT) & MCAN_IE_DRXE_MASK) -#define MCAN_IE_DRXE_GET(x) (((uint32_t)(x) & MCAN_IE_DRXE_MASK) >> MCAN_IE_DRXE_SHIFT) - -/* - * TOOE (RW) - * - * Timeout Occurred Interrupt Enable - */ -#define MCAN_IE_TOOE_MASK (0x40000UL) -#define MCAN_IE_TOOE_SHIFT (18U) -#define MCAN_IE_TOOE_SET(x) (((uint32_t)(x) << MCAN_IE_TOOE_SHIFT) & MCAN_IE_TOOE_MASK) -#define MCAN_IE_TOOE_GET(x) (((uint32_t)(x) & MCAN_IE_TOOE_MASK) >> MCAN_IE_TOOE_SHIFT) - -/* - * MRAFE (RW) - * - * Message RAM Access Failure Interrupt Enable - */ -#define MCAN_IE_MRAFE_MASK (0x20000UL) -#define MCAN_IE_MRAFE_SHIFT (17U) -#define MCAN_IE_MRAFE_SET(x) (((uint32_t)(x) << MCAN_IE_MRAFE_SHIFT) & MCAN_IE_MRAFE_MASK) -#define MCAN_IE_MRAFE_GET(x) (((uint32_t)(x) & MCAN_IE_MRAFE_MASK) >> MCAN_IE_MRAFE_SHIFT) - -/* - * TSWE (RW) - * - * Timestamp Wraparound Interrupt Enable - */ -#define MCAN_IE_TSWE_MASK (0x10000UL) -#define MCAN_IE_TSWE_SHIFT (16U) -#define MCAN_IE_TSWE_SET(x) (((uint32_t)(x) << MCAN_IE_TSWE_SHIFT) & MCAN_IE_TSWE_MASK) -#define MCAN_IE_TSWE_GET(x) (((uint32_t)(x) & MCAN_IE_TSWE_MASK) >> MCAN_IE_TSWE_SHIFT) - -/* - * TEFLE (RW) - * - * Tx Event FIFO Event Lost Interrupt Enable - */ -#define MCAN_IE_TEFLE_MASK (0x8000U) -#define MCAN_IE_TEFLE_SHIFT (15U) -#define MCAN_IE_TEFLE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFLE_SHIFT) & MCAN_IE_TEFLE_MASK) -#define MCAN_IE_TEFLE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFLE_MASK) >> MCAN_IE_TEFLE_SHIFT) - -/* - * TEFFE (RW) - * - * Tx Event FIFO Full Interrupt Enable - */ -#define MCAN_IE_TEFFE_MASK (0x4000U) -#define MCAN_IE_TEFFE_SHIFT (14U) -#define MCAN_IE_TEFFE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFFE_SHIFT) & MCAN_IE_TEFFE_MASK) -#define MCAN_IE_TEFFE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFFE_MASK) >> MCAN_IE_TEFFE_SHIFT) - -/* - * TEFWE (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Enable - */ -#define MCAN_IE_TEFWE_MASK (0x2000U) -#define MCAN_IE_TEFWE_SHIFT (13U) -#define MCAN_IE_TEFWE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFWE_SHIFT) & MCAN_IE_TEFWE_MASK) -#define MCAN_IE_TEFWE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFWE_MASK) >> MCAN_IE_TEFWE_SHIFT) - -/* - * TEFNE (RW) - * - * Tx Event FIFO New Entry Interrupt Enable - */ -#define MCAN_IE_TEFNE_MASK (0x1000U) -#define MCAN_IE_TEFNE_SHIFT (12U) -#define MCAN_IE_TEFNE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFNE_SHIFT) & MCAN_IE_TEFNE_MASK) -#define MCAN_IE_TEFNE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFNE_MASK) >> MCAN_IE_TEFNE_SHIFT) - -/* - * TFEE (RW) - * - * Tx FIFO Empty Interrupt Enable - */ -#define MCAN_IE_TFEE_MASK (0x800U) -#define MCAN_IE_TFEE_SHIFT (11U) -#define MCAN_IE_TFEE_SET(x) (((uint32_t)(x) << MCAN_IE_TFEE_SHIFT) & MCAN_IE_TFEE_MASK) -#define MCAN_IE_TFEE_GET(x) (((uint32_t)(x) & MCAN_IE_TFEE_MASK) >> MCAN_IE_TFEE_SHIFT) - -/* - * TCFE (RW) - * - * Transmission Cancellation Finished Interrupt Enable - */ -#define MCAN_IE_TCFE_MASK (0x400U) -#define MCAN_IE_TCFE_SHIFT (10U) -#define MCAN_IE_TCFE_SET(x) (((uint32_t)(x) << MCAN_IE_TCFE_SHIFT) & MCAN_IE_TCFE_MASK) -#define MCAN_IE_TCFE_GET(x) (((uint32_t)(x) & MCAN_IE_TCFE_MASK) >> MCAN_IE_TCFE_SHIFT) - -/* - * TCE (RW) - * - * Transmission Completed Interrupt Enable - */ -#define MCAN_IE_TCE_MASK (0x200U) -#define MCAN_IE_TCE_SHIFT (9U) -#define MCAN_IE_TCE_SET(x) (((uint32_t)(x) << MCAN_IE_TCE_SHIFT) & MCAN_IE_TCE_MASK) -#define MCAN_IE_TCE_GET(x) (((uint32_t)(x) & MCAN_IE_TCE_MASK) >> MCAN_IE_TCE_SHIFT) - -/* - * HPME (RW) - * - * High Priority Message Interrupt Enable - */ -#define MCAN_IE_HPME_MASK (0x100U) -#define MCAN_IE_HPME_SHIFT (8U) -#define MCAN_IE_HPME_SET(x) (((uint32_t)(x) << MCAN_IE_HPME_SHIFT) & MCAN_IE_HPME_MASK) -#define MCAN_IE_HPME_GET(x) (((uint32_t)(x) & MCAN_IE_HPME_MASK) >> MCAN_IE_HPME_SHIFT) - -/* - * RF1LE (RW) - * - * Rx FIFO 1 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF1LE_MASK (0x80U) -#define MCAN_IE_RF1LE_SHIFT (7U) -#define MCAN_IE_RF1LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1LE_SHIFT) & MCAN_IE_RF1LE_MASK) -#define MCAN_IE_RF1LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1LE_MASK) >> MCAN_IE_RF1LE_SHIFT) - -/* - * RF1FE (RW) - * - * Rx FIFO 1 Full Interrupt Enable - */ -#define MCAN_IE_RF1FE_MASK (0x40U) -#define MCAN_IE_RF1FE_SHIFT (6U) -#define MCAN_IE_RF1FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1FE_SHIFT) & MCAN_IE_RF1FE_MASK) -#define MCAN_IE_RF1FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1FE_MASK) >> MCAN_IE_RF1FE_SHIFT) - -/* - * RF1WE (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF1WE_MASK (0x20U) -#define MCAN_IE_RF1WE_SHIFT (5U) -#define MCAN_IE_RF1WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1WE_SHIFT) & MCAN_IE_RF1WE_MASK) -#define MCAN_IE_RF1WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1WE_MASK) >> MCAN_IE_RF1WE_SHIFT) - -/* - * RF1NE (RW) - * - * Rx FIFO 1 New Message Interrupt Enable - */ -#define MCAN_IE_RF1NE_MASK (0x10U) -#define MCAN_IE_RF1NE_SHIFT (4U) -#define MCAN_IE_RF1NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1NE_SHIFT) & MCAN_IE_RF1NE_MASK) -#define MCAN_IE_RF1NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1NE_MASK) >> MCAN_IE_RF1NE_SHIFT) - -/* - * RF0LE (RW) - * - * Rx FIFO 0 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF0LE_MASK (0x8U) -#define MCAN_IE_RF0LE_SHIFT (3U) -#define MCAN_IE_RF0LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0LE_SHIFT) & MCAN_IE_RF0LE_MASK) -#define MCAN_IE_RF0LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0LE_MASK) >> MCAN_IE_RF0LE_SHIFT) - -/* - * RF0FE (RW) - * - * Rx FIFO 0 Full Interrupt Enable - */ -#define MCAN_IE_RF0FE_MASK (0x4U) -#define MCAN_IE_RF0FE_SHIFT (2U) -#define MCAN_IE_RF0FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0FE_SHIFT) & MCAN_IE_RF0FE_MASK) -#define MCAN_IE_RF0FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0FE_MASK) >> MCAN_IE_RF0FE_SHIFT) - -/* - * RF0WE (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF0WE_MASK (0x2U) -#define MCAN_IE_RF0WE_SHIFT (1U) -#define MCAN_IE_RF0WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0WE_SHIFT) & MCAN_IE_RF0WE_MASK) -#define MCAN_IE_RF0WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0WE_MASK) >> MCAN_IE_RF0WE_SHIFT) - -/* - * RF0NE (RW) - * - * Rx FIFO 0 New Message Interrupt Enable - */ -#define MCAN_IE_RF0NE_MASK (0x1U) -#define MCAN_IE_RF0NE_SHIFT (0U) -#define MCAN_IE_RF0NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0NE_SHIFT) & MCAN_IE_RF0NE_MASK) -#define MCAN_IE_RF0NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0NE_MASK) >> MCAN_IE_RF0NE_SHIFT) - -/* Bitfield definition for register: ILS */ -/* - * ARAL (RW) - * - * Access to Reserved Address Line - */ -#define MCAN_ILS_ARAL_MASK (0x20000000UL) -#define MCAN_ILS_ARAL_SHIFT (29U) -#define MCAN_ILS_ARAL_SET(x) (((uint32_t)(x) << MCAN_ILS_ARAL_SHIFT) & MCAN_ILS_ARAL_MASK) -#define MCAN_ILS_ARAL_GET(x) (((uint32_t)(x) & MCAN_ILS_ARAL_MASK) >> MCAN_ILS_ARAL_SHIFT) - -/* - * PEDL (RW) - * - * Protocol Error in Data Phase Line - */ -#define MCAN_ILS_PEDL_MASK (0x10000000UL) -#define MCAN_ILS_PEDL_SHIFT (28U) -#define MCAN_ILS_PEDL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEDL_SHIFT) & MCAN_ILS_PEDL_MASK) -#define MCAN_ILS_PEDL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEDL_MASK) >> MCAN_ILS_PEDL_SHIFT) - -/* - * PEAL (RW) - * - * Protocol Error in Arbitration Phase Line - */ -#define MCAN_ILS_PEAL_MASK (0x8000000UL) -#define MCAN_ILS_PEAL_SHIFT (27U) -#define MCAN_ILS_PEAL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEAL_SHIFT) & MCAN_ILS_PEAL_MASK) -#define MCAN_ILS_PEAL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEAL_MASK) >> MCAN_ILS_PEAL_SHIFT) - -/* - * WDIL (RW) - * - * Watchdog Interrupt Line - */ -#define MCAN_ILS_WDIL_MASK (0x4000000UL) -#define MCAN_ILS_WDIL_SHIFT (26U) -#define MCAN_ILS_WDIL_SET(x) (((uint32_t)(x) << MCAN_ILS_WDIL_SHIFT) & MCAN_ILS_WDIL_MASK) -#define MCAN_ILS_WDIL_GET(x) (((uint32_t)(x) & MCAN_ILS_WDIL_MASK) >> MCAN_ILS_WDIL_SHIFT) - -/* - * BOL (RW) - * - * Bus_Off Status Interrupt Line - */ -#define MCAN_ILS_BOL_MASK (0x2000000UL) -#define MCAN_ILS_BOL_SHIFT (25U) -#define MCAN_ILS_BOL_SET(x) (((uint32_t)(x) << MCAN_ILS_BOL_SHIFT) & MCAN_ILS_BOL_MASK) -#define MCAN_ILS_BOL_GET(x) (((uint32_t)(x) & MCAN_ILS_BOL_MASK) >> MCAN_ILS_BOL_SHIFT) - -/* - * EWL (RW) - * - * Warning Status Interrupt Line - */ -#define MCAN_ILS_EWL_MASK (0x1000000UL) -#define MCAN_ILS_EWL_SHIFT (24U) -#define MCAN_ILS_EWL_SET(x) (((uint32_t)(x) << MCAN_ILS_EWL_SHIFT) & MCAN_ILS_EWL_MASK) -#define MCAN_ILS_EWL_GET(x) (((uint32_t)(x) & MCAN_ILS_EWL_MASK) >> MCAN_ILS_EWL_SHIFT) - -/* - * EPL (RW) - * - * Error Passive Interrupt Line - */ -#define MCAN_ILS_EPL_MASK (0x800000UL) -#define MCAN_ILS_EPL_SHIFT (23U) -#define MCAN_ILS_EPL_SET(x) (((uint32_t)(x) << MCAN_ILS_EPL_SHIFT) & MCAN_ILS_EPL_MASK) -#define MCAN_ILS_EPL_GET(x) (((uint32_t)(x) & MCAN_ILS_EPL_MASK) >> MCAN_ILS_EPL_SHIFT) - -/* - * ELOL (RW) - * - * Error Logging Overflow Interrupt Line - */ -#define MCAN_ILS_ELOL_MASK (0x400000UL) -#define MCAN_ILS_ELOL_SHIFT (22U) -#define MCAN_ILS_ELOL_SET(x) (((uint32_t)(x) << MCAN_ILS_ELOL_SHIFT) & MCAN_ILS_ELOL_MASK) -#define MCAN_ILS_ELOL_GET(x) (((uint32_t)(x) & MCAN_ILS_ELOL_MASK) >> MCAN_ILS_ELOL_SHIFT) - -/* - * BEUL (RW) - * - * Bit Error Uncorrected Interrupt Line - */ -#define MCAN_ILS_BEUL_MASK (0x200000UL) -#define MCAN_ILS_BEUL_SHIFT (21U) -#define MCAN_ILS_BEUL_SET(x) (((uint32_t)(x) << MCAN_ILS_BEUL_SHIFT) & MCAN_ILS_BEUL_MASK) -#define MCAN_ILS_BEUL_GET(x) (((uint32_t)(x) & MCAN_ILS_BEUL_MASK) >> MCAN_ILS_BEUL_SHIFT) - -/* - * BECL (RW) - * - * Bit Error Corrected Interrupt Line - */ -#define MCAN_ILS_BECL_MASK (0x100000UL) -#define MCAN_ILS_BECL_SHIFT (20U) -#define MCAN_ILS_BECL_SET(x) (((uint32_t)(x) << MCAN_ILS_BECL_SHIFT) & MCAN_ILS_BECL_MASK) -#define MCAN_ILS_BECL_GET(x) (((uint32_t)(x) & MCAN_ILS_BECL_MASK) >> MCAN_ILS_BECL_SHIFT) - -/* - * DRXL (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Line - */ -#define MCAN_ILS_DRXL_MASK (0x80000UL) -#define MCAN_ILS_DRXL_SHIFT (19U) -#define MCAN_ILS_DRXL_SET(x) (((uint32_t)(x) << MCAN_ILS_DRXL_SHIFT) & MCAN_ILS_DRXL_MASK) -#define MCAN_ILS_DRXL_GET(x) (((uint32_t)(x) & MCAN_ILS_DRXL_MASK) >> MCAN_ILS_DRXL_SHIFT) - -/* - * TOOL (RW) - * - * Timeout Occurred Interrupt Line - */ -#define MCAN_ILS_TOOL_MASK (0x40000UL) -#define MCAN_ILS_TOOL_SHIFT (18U) -#define MCAN_ILS_TOOL_SET(x) (((uint32_t)(x) << MCAN_ILS_TOOL_SHIFT) & MCAN_ILS_TOOL_MASK) -#define MCAN_ILS_TOOL_GET(x) (((uint32_t)(x) & MCAN_ILS_TOOL_MASK) >> MCAN_ILS_TOOL_SHIFT) - -/* - * MRAFL (RW) - * - * Message RAM Access Failure Interrupt Line - */ -#define MCAN_ILS_MRAFL_MASK (0x20000UL) -#define MCAN_ILS_MRAFL_SHIFT (17U) -#define MCAN_ILS_MRAFL_SET(x) (((uint32_t)(x) << MCAN_ILS_MRAFL_SHIFT) & MCAN_ILS_MRAFL_MASK) -#define MCAN_ILS_MRAFL_GET(x) (((uint32_t)(x) & MCAN_ILS_MRAFL_MASK) >> MCAN_ILS_MRAFL_SHIFT) - -/* - * TSWL (RW) - * - * Timestamp Wraparound Interrupt Line - */ -#define MCAN_ILS_TSWL_MASK (0x10000UL) -#define MCAN_ILS_TSWL_SHIFT (16U) -#define MCAN_ILS_TSWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TSWL_SHIFT) & MCAN_ILS_TSWL_MASK) -#define MCAN_ILS_TSWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TSWL_MASK) >> MCAN_ILS_TSWL_SHIFT) - -/* - * TEFLL (RW) - * - * Tx Event FIFO Event Lost Interrupt Line - */ -#define MCAN_ILS_TEFLL_MASK (0x8000U) -#define MCAN_ILS_TEFLL_SHIFT (15U) -#define MCAN_ILS_TEFLL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFLL_SHIFT) & MCAN_ILS_TEFLL_MASK) -#define MCAN_ILS_TEFLL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFLL_MASK) >> MCAN_ILS_TEFLL_SHIFT) - -/* - * TEFFL (RW) - * - * Tx Event FIFO Full Interrupt Line - */ -#define MCAN_ILS_TEFFL_MASK (0x4000U) -#define MCAN_ILS_TEFFL_SHIFT (14U) -#define MCAN_ILS_TEFFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFFL_SHIFT) & MCAN_ILS_TEFFL_MASK) -#define MCAN_ILS_TEFFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFFL_MASK) >> MCAN_ILS_TEFFL_SHIFT) - -/* - * TEFWL (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Line - */ -#define MCAN_ILS_TEFWL_MASK (0x2000U) -#define MCAN_ILS_TEFWL_SHIFT (13U) -#define MCAN_ILS_TEFWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFWL_SHIFT) & MCAN_ILS_TEFWL_MASK) -#define MCAN_ILS_TEFWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFWL_MASK) >> MCAN_ILS_TEFWL_SHIFT) - -/* - * TEFNL (RW) - * - * Tx Event FIFO New Entry Interrupt Line - */ -#define MCAN_ILS_TEFNL_MASK (0x1000U) -#define MCAN_ILS_TEFNL_SHIFT (12U) -#define MCAN_ILS_TEFNL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFNL_SHIFT) & MCAN_ILS_TEFNL_MASK) -#define MCAN_ILS_TEFNL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFNL_MASK) >> MCAN_ILS_TEFNL_SHIFT) - -/* - * TFEL (RW) - * - * Tx FIFO Empty Interrupt Line - */ -#define MCAN_ILS_TFEL_MASK (0x800U) -#define MCAN_ILS_TFEL_SHIFT (11U) -#define MCAN_ILS_TFEL_SET(x) (((uint32_t)(x) << MCAN_ILS_TFEL_SHIFT) & MCAN_ILS_TFEL_MASK) -#define MCAN_ILS_TFEL_GET(x) (((uint32_t)(x) & MCAN_ILS_TFEL_MASK) >> MCAN_ILS_TFEL_SHIFT) - -/* - * TCFL (RW) - * - * Transmission Cancellation Finished Interrupt Line - */ -#define MCAN_ILS_TCFL_MASK (0x400U) -#define MCAN_ILS_TCFL_SHIFT (10U) -#define MCAN_ILS_TCFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCFL_SHIFT) & MCAN_ILS_TCFL_MASK) -#define MCAN_ILS_TCFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCFL_MASK) >> MCAN_ILS_TCFL_SHIFT) - -/* - * TCL (RW) - * - * Transmission Completed Interrupt Line - */ -#define MCAN_ILS_TCL_MASK (0x200U) -#define MCAN_ILS_TCL_SHIFT (9U) -#define MCAN_ILS_TCL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCL_SHIFT) & MCAN_ILS_TCL_MASK) -#define MCAN_ILS_TCL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCL_MASK) >> MCAN_ILS_TCL_SHIFT) - -/* - * HPML (RW) - * - * High Priority Message Interrupt Line - */ -#define MCAN_ILS_HPML_MASK (0x100U) -#define MCAN_ILS_HPML_SHIFT (8U) -#define MCAN_ILS_HPML_SET(x) (((uint32_t)(x) << MCAN_ILS_HPML_SHIFT) & MCAN_ILS_HPML_MASK) -#define MCAN_ILS_HPML_GET(x) (((uint32_t)(x) & MCAN_ILS_HPML_MASK) >> MCAN_ILS_HPML_SHIFT) - -/* - * RF1LL (RW) - * - * Rx FIFO 1 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF1LL_MASK (0x80U) -#define MCAN_ILS_RF1LL_SHIFT (7U) -#define MCAN_ILS_RF1LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1LL_SHIFT) & MCAN_ILS_RF1LL_MASK) -#define MCAN_ILS_RF1LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1LL_MASK) >> MCAN_ILS_RF1LL_SHIFT) - -/* - * RF1FL (RW) - * - * Rx FIFO 1 Full Interrupt Line - */ -#define MCAN_ILS_RF1FL_MASK (0x40U) -#define MCAN_ILS_RF1FL_SHIFT (6U) -#define MCAN_ILS_RF1FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1FL_SHIFT) & MCAN_ILS_RF1FL_MASK) -#define MCAN_ILS_RF1FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1FL_MASK) >> MCAN_ILS_RF1FL_SHIFT) - -/* - * RF1WL (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF1WL_MASK (0x20U) -#define MCAN_ILS_RF1WL_SHIFT (5U) -#define MCAN_ILS_RF1WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1WL_SHIFT) & MCAN_ILS_RF1WL_MASK) -#define MCAN_ILS_RF1WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1WL_MASK) >> MCAN_ILS_RF1WL_SHIFT) - -/* - * RF1NL (RW) - * - * Rx FIFO 1 New Message Interrupt Line - */ -#define MCAN_ILS_RF1NL_MASK (0x10U) -#define MCAN_ILS_RF1NL_SHIFT (4U) -#define MCAN_ILS_RF1NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1NL_SHIFT) & MCAN_ILS_RF1NL_MASK) -#define MCAN_ILS_RF1NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1NL_MASK) >> MCAN_ILS_RF1NL_SHIFT) - -/* - * RF0LL (RW) - * - * Rx FIFO 0 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF0LL_MASK (0x8U) -#define MCAN_ILS_RF0LL_SHIFT (3U) -#define MCAN_ILS_RF0LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0LL_SHIFT) & MCAN_ILS_RF0LL_MASK) -#define MCAN_ILS_RF0LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0LL_MASK) >> MCAN_ILS_RF0LL_SHIFT) - -/* - * RF0FL (RW) - * - * Rx FIFO 0 Full Interrupt Line - */ -#define MCAN_ILS_RF0FL_MASK (0x4U) -#define MCAN_ILS_RF0FL_SHIFT (2U) -#define MCAN_ILS_RF0FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0FL_SHIFT) & MCAN_ILS_RF0FL_MASK) -#define MCAN_ILS_RF0FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0FL_MASK) >> MCAN_ILS_RF0FL_SHIFT) - -/* - * RF0WL (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF0WL_MASK (0x2U) -#define MCAN_ILS_RF0WL_SHIFT (1U) -#define MCAN_ILS_RF0WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0WL_SHIFT) & MCAN_ILS_RF0WL_MASK) -#define MCAN_ILS_RF0WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0WL_MASK) >> MCAN_ILS_RF0WL_SHIFT) - -/* - * RF0NL (RW) - * - * Rx FIFO 0 New Message Interrupt Line - */ -#define MCAN_ILS_RF0NL_MASK (0x1U) -#define MCAN_ILS_RF0NL_SHIFT (0U) -#define MCAN_ILS_RF0NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0NL_SHIFT) & MCAN_ILS_RF0NL_MASK) -#define MCAN_ILS_RF0NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0NL_MASK) >> MCAN_ILS_RF0NL_SHIFT) - -/* Bitfield definition for register: ILE */ -/* - * EINT1 (RW) - * - * Enable Interrupt Line 1 - * 0= Interrupt line m_can_int1 disabled - * 1= Interrupt line m_can_int1 enabled - */ -#define MCAN_ILE_EINT1_MASK (0x2U) -#define MCAN_ILE_EINT1_SHIFT (1U) -#define MCAN_ILE_EINT1_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT1_SHIFT) & MCAN_ILE_EINT1_MASK) -#define MCAN_ILE_EINT1_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT1_MASK) >> MCAN_ILE_EINT1_SHIFT) - -/* - * EINT0 (RW) - * - * Enable Interrupt Line 0 - * 0= Interrupt line m_can_int0 disabled - * 1= Interrupt line m_can_int0 enabled - */ -#define MCAN_ILE_EINT0_MASK (0x1U) -#define MCAN_ILE_EINT0_SHIFT (0U) -#define MCAN_ILE_EINT0_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT0_SHIFT) & MCAN_ILE_EINT0_MASK) -#define MCAN_ILE_EINT0_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT0_MASK) >> MCAN_ILE_EINT0_SHIFT) - -/* Bitfield definition for register: GFC */ -/* - * ANFS (RW) - * - * Accept Non-matching Frames Standard - * Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFS_MASK (0x30U) -#define MCAN_GFC_ANFS_SHIFT (4U) -#define MCAN_GFC_ANFS_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFS_SHIFT) & MCAN_GFC_ANFS_MASK) -#define MCAN_GFC_ANFS_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFS_MASK) >> MCAN_GFC_ANFS_SHIFT) - -/* - * ANFE (RW) - * - * Accept Non-matching Frames Extended - * Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFE_MASK (0xCU) -#define MCAN_GFC_ANFE_SHIFT (2U) -#define MCAN_GFC_ANFE_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFE_SHIFT) & MCAN_GFC_ANFE_MASK) -#define MCAN_GFC_ANFE_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFE_MASK) >> MCAN_GFC_ANFE_SHIFT) - -/* - * RRFS (RW) - * - * Reject Remote Frames Standard - * 0= Filter remote frames with 11-bit standard IDs - * 1= Reject all remote frames with 11-bit standard IDs - */ -#define MCAN_GFC_RRFS_MASK (0x2U) -#define MCAN_GFC_RRFS_SHIFT (1U) -#define MCAN_GFC_RRFS_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFS_SHIFT) & MCAN_GFC_RRFS_MASK) -#define MCAN_GFC_RRFS_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFS_MASK) >> MCAN_GFC_RRFS_SHIFT) - -/* - * RRFE (RW) - * - * Reject Remote Frames Extended - * 0= Filter remote frames with 29-bit extended IDs - * 1= Reject all remote frames with 29-bit extended IDs - */ -#define MCAN_GFC_RRFE_MASK (0x1U) -#define MCAN_GFC_RRFE_SHIFT (0U) -#define MCAN_GFC_RRFE_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFE_SHIFT) & MCAN_GFC_RRFE_MASK) -#define MCAN_GFC_RRFE_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFE_MASK) >> MCAN_GFC_RRFE_SHIFT) - -/* Bitfield definition for register: SIDFC */ -/* - * LSS (RW) - * - * List Size Standard - * 0= No standard Message ID filter - * 1-128= Number of standard Message ID filter elements - * >128= Values greater than 128 are interpreted as 128 - */ -#define MCAN_SIDFC_LSS_MASK (0xFF0000UL) -#define MCAN_SIDFC_LSS_SHIFT (16U) -#define MCAN_SIDFC_LSS_SET(x) (((uint32_t)(x) << MCAN_SIDFC_LSS_SHIFT) & MCAN_SIDFC_LSS_MASK) -#define MCAN_SIDFC_LSS_GET(x) (((uint32_t)(x) & MCAN_SIDFC_LSS_MASK) >> MCAN_SIDFC_LSS_SHIFT) - -/* - * FLSSA (RW) - * - * Filter List Standard Start Address - * Start address of standard Message ID filter list (32-bit word address) - */ -#define MCAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define MCAN_SIDFC_FLSSA_SHIFT (2U) -#define MCAN_SIDFC_FLSSA_SET(x) (((uint32_t)(x) << MCAN_SIDFC_FLSSA_SHIFT) & MCAN_SIDFC_FLSSA_MASK) -#define MCAN_SIDFC_FLSSA_GET(x) (((uint32_t)(x) & MCAN_SIDFC_FLSSA_MASK) >> MCAN_SIDFC_FLSSA_SHIFT) - -/* Bitfield definition for register: XIDFC */ -/* - * LSE (RW) - * - * List Size Extended - * 0= No extended Message ID filter - * 1-64= Number of extended Message ID filter elements - * >64= Values greater than 64 are interpreted as 64 - */ -#define MCAN_XIDFC_LSE_MASK (0x7F0000UL) -#define MCAN_XIDFC_LSE_SHIFT (16U) -#define MCAN_XIDFC_LSE_SET(x) (((uint32_t)(x) << MCAN_XIDFC_LSE_SHIFT) & MCAN_XIDFC_LSE_MASK) -#define MCAN_XIDFC_LSE_GET(x) (((uint32_t)(x) & MCAN_XIDFC_LSE_MASK) >> MCAN_XIDFC_LSE_SHIFT) - -/* - * FLESA (RW) - * - * Filter List Extended Start Address - * Start address of extended Message ID filter list (32-bit word address). - */ -#define MCAN_XIDFC_FLESA_MASK (0xFFFCU) -#define MCAN_XIDFC_FLESA_SHIFT (2U) -#define MCAN_XIDFC_FLESA_SET(x) (((uint32_t)(x) << MCAN_XIDFC_FLESA_SHIFT) & MCAN_XIDFC_FLESA_MASK) -#define MCAN_XIDFC_FLESA_GET(x) (((uint32_t)(x) & MCAN_XIDFC_FLESA_MASK) >> MCAN_XIDFC_FLESA_SHIFT) - -/* Bitfield definition for register: XIDAM */ -/* - * EIDM (RW) - * - * Extended ID Mask - * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - * Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - */ -#define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) -#define MCAN_XIDAM_EIDM_SHIFT (0U) -#define MCAN_XIDAM_EIDM_SET(x) (((uint32_t)(x) << MCAN_XIDAM_EIDM_SHIFT) & MCAN_XIDAM_EIDM_MASK) -#define MCAN_XIDAM_EIDM_GET(x) (((uint32_t)(x) & MCAN_XIDAM_EIDM_MASK) >> MCAN_XIDAM_EIDM_SHIFT) - -/* Bitfield definition for register: HPMS */ -/* - * FLST (R) - * - * Filter List - * Indicates the filter list of the matching filter element. - * 0= Standard Filter List - * 1= Extended Filter List - */ -#define MCAN_HPMS_FLST_MASK (0x8000U) -#define MCAN_HPMS_FLST_SHIFT (15U) -#define MCAN_HPMS_FLST_GET(x) (((uint32_t)(x) & MCAN_HPMS_FLST_MASK) >> MCAN_HPMS_FLST_SHIFT) - -/* - * FIDX (R) - * - * Filter Index - * Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - */ -#define MCAN_HPMS_FIDX_MASK (0x7F00U) -#define MCAN_HPMS_FIDX_SHIFT (8U) -#define MCAN_HPMS_FIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_FIDX_MASK) >> MCAN_HPMS_FIDX_SHIFT) - -/* - * MSI (R) - * - * Message Storage Indicator - * 00= No FIFO selected - * 01= FIFO message lost - * 10= Message stored in FIFO 0 - * 11= Message stored in FIFO 1 - */ -#define MCAN_HPMS_MSI_MASK (0xC0U) -#define MCAN_HPMS_MSI_SHIFT (6U) -#define MCAN_HPMS_MSI_GET(x) (((uint32_t)(x) & MCAN_HPMS_MSI_MASK) >> MCAN_HPMS_MSI_SHIFT) - -/* - * BIDX (R) - * - * Buffer Index - * Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - */ -#define MCAN_HPMS_BIDX_MASK (0x3FU) -#define MCAN_HPMS_BIDX_SHIFT (0U) -#define MCAN_HPMS_BIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_BIDX_MASK) >> MCAN_HPMS_BIDX_SHIFT) - -/* Bitfield definition for register: NDAT1 */ -/* - * ND1 (RW) - * - * New Data[31:0] - * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT1_ND1_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT1_ND1_SHIFT (0U) -#define MCAN_NDAT1_ND1_SET(x) (((uint32_t)(x) << MCAN_NDAT1_ND1_SHIFT) & MCAN_NDAT1_ND1_MASK) -#define MCAN_NDAT1_ND1_GET(x) (((uint32_t)(x) & MCAN_NDAT1_ND1_MASK) >> MCAN_NDAT1_ND1_SHIFT) - -/* Bitfield definition for register: NDAT2 */ -/* - * ND2 (RW) - * - * New Data[63:32] - * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT2_ND2_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT2_ND2_SHIFT (0U) -#define MCAN_NDAT2_ND2_SET(x) (((uint32_t)(x) << MCAN_NDAT2_ND2_SHIFT) & MCAN_NDAT2_ND2_MASK) -#define MCAN_NDAT2_ND2_GET(x) (((uint32_t)(x) & MCAN_NDAT2_ND2_MASK) >> MCAN_NDAT2_ND2_SHIFT) - -/* Bitfield definition for register: RXF0C */ -/* - * F0OM (RW) - * - * FIFO 0 Operation Mode - * FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 0 blocking mode - * 1= FIFO 0 overwrite mode - */ -#define MCAN_RXF0C_F0OM_MASK (0x80000000UL) -#define MCAN_RXF0C_F0OM_SHIFT (31U) -#define MCAN_RXF0C_F0OM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0OM_SHIFT) & MCAN_RXF0C_F0OM_MASK) -#define MCAN_RXF0C_F0OM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0OM_MASK) >> MCAN_RXF0C_F0OM_SHIFT) - -/* - * F0WM (RW) - * - * Rx FIFO 0 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF0C_F0WM_MASK (0x7F000000UL) -#define MCAN_RXF0C_F0WM_SHIFT (24U) -#define MCAN_RXF0C_F0WM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0WM_SHIFT) & MCAN_RXF0C_F0WM_MASK) -#define MCAN_RXF0C_F0WM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0WM_MASK) >> MCAN_RXF0C_F0WM_SHIFT) - -/* - * F0S (RW) - * - * Rx FIFO 0 Size - * 0= No Rx FIFO 0 - * 1-64= Number of Rx FIFO 0 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 0 elements are indexed from 0 to F0S-1 - */ -#define MCAN_RXF0C_F0S_MASK (0x7F0000UL) -#define MCAN_RXF0C_F0S_SHIFT (16U) -#define MCAN_RXF0C_F0S_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0S_SHIFT) & MCAN_RXF0C_F0S_MASK) -#define MCAN_RXF0C_F0S_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0S_MASK) >> MCAN_RXF0C_F0S_SHIFT) - -/* - * F0SA (RW) - * - * Rx FIFO 0 Start Address - * Start address of Rx FIFO 0 in Message RAM (32-bit word address) - */ -#define MCAN_RXF0C_F0SA_MASK (0xFFFCU) -#define MCAN_RXF0C_F0SA_SHIFT (2U) -#define MCAN_RXF0C_F0SA_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0SA_SHIFT) & MCAN_RXF0C_F0SA_MASK) -#define MCAN_RXF0C_F0SA_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0SA_MASK) >> MCAN_RXF0C_F0SA_SHIFT) - -/* Bitfield definition for register: RXF0S */ -/* - * RF0L (R) - * - * Rx FIFO 0 Message Lost - * This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - * Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF0S_RF0L_MASK (0x2000000UL) -#define MCAN_RXF0S_RF0L_SHIFT (25U) -#define MCAN_RXF0S_RF0L_GET(x) (((uint32_t)(x) & MCAN_RXF0S_RF0L_MASK) >> MCAN_RXF0S_RF0L_SHIFT) - -/* - * F0F (R) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_RXF0S_F0F_MASK (0x1000000UL) -#define MCAN_RXF0S_F0F_SHIFT (24U) -#define MCAN_RXF0S_F0F_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0F_MASK) >> MCAN_RXF0S_F0F_SHIFT) - -/* - * F0PI (R) - * - * Rx FIFO 0 Put Index - * Rx FIFO 0 write index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0PI_MASK (0x3F0000UL) -#define MCAN_RXF0S_F0PI_SHIFT (16U) -#define MCAN_RXF0S_F0PI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0PI_MASK) >> MCAN_RXF0S_F0PI_SHIFT) - -/* - * F0GI (R) - * - * Rx FIFO 0 Get Index - * Rx FIFO 0 read index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0GI_MASK (0x3F00U) -#define MCAN_RXF0S_F0GI_SHIFT (8U) -#define MCAN_RXF0S_F0GI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT) - -/* - * F0FL (R) - * - * Rx FIFO 0 Fill Level - * Number of elements stored in Rx FIFO 0, range 0 to 64. - */ -#define MCAN_RXF0S_F0FL_MASK (0x7FU) -#define MCAN_RXF0S_F0FL_SHIFT (0U) -#define MCAN_RXF0S_F0FL_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT) - -/* Bitfield definition for register: RXF0A */ -/* - * F0AI (RW) - * - * Rx FIFO 0 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. - * This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - */ -#define MCAN_RXF0A_F0AI_MASK (0x3FU) -#define MCAN_RXF0A_F0AI_SHIFT (0U) -#define MCAN_RXF0A_F0AI_SET(x) (((uint32_t)(x) << MCAN_RXF0A_F0AI_SHIFT) & MCAN_RXF0A_F0AI_MASK) -#define MCAN_RXF0A_F0AI_GET(x) (((uint32_t)(x) & MCAN_RXF0A_F0AI_MASK) >> MCAN_RXF0A_F0AI_SHIFT) - -/* Bitfield definition for register: RXBC */ -/* - * RBSA (RW) - * - * Rx Buffer Start Address - * Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - */ -#define MCAN_RXBC_RBSA_MASK (0xFFFCU) -#define MCAN_RXBC_RBSA_SHIFT (2U) -#define MCAN_RXBC_RBSA_SET(x) (((uint32_t)(x) << MCAN_RXBC_RBSA_SHIFT) & MCAN_RXBC_RBSA_MASK) -#define MCAN_RXBC_RBSA_GET(x) (((uint32_t)(x) & MCAN_RXBC_RBSA_MASK) >> MCAN_RXBC_RBSA_SHIFT) - -/* Bitfield definition for register: RXF1C */ -/* - * F1OM (RW) - * - * FIFO 1 Operation Mode - * FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 1 blocking mode - * 1= FIFO 1 overwrite mode - */ -#define MCAN_RXF1C_F1OM_MASK (0x80000000UL) -#define MCAN_RXF1C_F1OM_SHIFT (31U) -#define MCAN_RXF1C_F1OM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1OM_SHIFT) & MCAN_RXF1C_F1OM_MASK) -#define MCAN_RXF1C_F1OM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1OM_MASK) >> MCAN_RXF1C_F1OM_SHIFT) - -/* - * F1WM (RW) - * - * Rx FIFO 1 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF1C_F1WM_MASK (0x7F000000UL) -#define MCAN_RXF1C_F1WM_SHIFT (24U) -#define MCAN_RXF1C_F1WM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1WM_SHIFT) & MCAN_RXF1C_F1WM_MASK) -#define MCAN_RXF1C_F1WM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1WM_MASK) >> MCAN_RXF1C_F1WM_SHIFT) - -/* - * F1S (RW) - * - * Rx FIFO 1 Size - * 0= No Rx FIFO 1 - * 1-64= Number of Rx FIFO 1 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - */ -#define MCAN_RXF1C_F1S_MASK (0x7F0000UL) -#define MCAN_RXF1C_F1S_SHIFT (16U) -#define MCAN_RXF1C_F1S_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1S_SHIFT) & MCAN_RXF1C_F1S_MASK) -#define MCAN_RXF1C_F1S_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1S_MASK) >> MCAN_RXF1C_F1S_SHIFT) - -/* - * F1SA (RW) - * - * Rx FIFO 1 Start Address - * Start address of Rx FIFO 1 in Message RAM (32-bit word address) - */ -#define MCAN_RXF1C_F1SA_MASK (0xFFFCU) -#define MCAN_RXF1C_F1SA_SHIFT (2U) -#define MCAN_RXF1C_F1SA_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1SA_SHIFT) & MCAN_RXF1C_F1SA_MASK) -#define MCAN_RXF1C_F1SA_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1SA_MASK) >> MCAN_RXF1C_F1SA_SHIFT) - -/* Bitfield definition for register: RXF1S */ -/* - * DMS (R) - * - * Debug Message Status - * 00= Idle state, wait for reception of debug messages, DMA request is cleared - * 01= Debug message A received - * 10= Debug messages A, B received - * 11= Debug messages A, B, C received, DMA request is set - */ -#define MCAN_RXF1S_DMS_MASK (0xC0000000UL) -#define MCAN_RXF1S_DMS_SHIFT (30U) -#define MCAN_RXF1S_DMS_GET(x) (((uint32_t)(x) & MCAN_RXF1S_DMS_MASK) >> MCAN_RXF1S_DMS_SHIFT) - -/* - * RF1L (R) - * - * Rx FIFO 1 Message Lost - * This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - * Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF1S_RF1L_MASK (0x2000000UL) -#define MCAN_RXF1S_RF1L_SHIFT (25U) -#define MCAN_RXF1S_RF1L_GET(x) (((uint32_t)(x) & MCAN_RXF1S_RF1L_MASK) >> MCAN_RXF1S_RF1L_SHIFT) - -/* - * F1F (R) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_RXF1S_F1F_MASK (0x1000000UL) -#define MCAN_RXF1S_F1F_SHIFT (24U) -#define MCAN_RXF1S_F1F_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1F_MASK) >> MCAN_RXF1S_F1F_SHIFT) - -/* - * F1PI (R) - * - * Rx FIFO 1 Put Index - * Rx FIFO 1 write index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1PI_MASK (0x3F0000UL) -#define MCAN_RXF1S_F1PI_SHIFT (16U) -#define MCAN_RXF1S_F1PI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1PI_MASK) >> MCAN_RXF1S_F1PI_SHIFT) - -/* - * F1GI (R) - * - * Rx FIFO 1 Get Index - * Rx FIFO 1 read index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1GI_MASK (0x3F00U) -#define MCAN_RXF1S_F1GI_SHIFT (8U) -#define MCAN_RXF1S_F1GI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT) - -/* - * F1FL (R) - * - * Rx FIFO 1 Fill Level - * Number of elements stored in Rx FIFO 1, range 0 to 64. - */ -#define MCAN_RXF1S_F1FL_MASK (0x7FU) -#define MCAN_RXF1S_F1FL_SHIFT (0U) -#define MCAN_RXF1S_F1FL_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT) - -/* Bitfield definition for register: RXF1A */ -/* - * F1AI (RW) - * - * Rx FIFO 1 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. - * This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - */ -#define MCAN_RXF1A_F1AI_MASK (0x3FU) -#define MCAN_RXF1A_F1AI_SHIFT (0U) -#define MCAN_RXF1A_F1AI_SET(x) (((uint32_t)(x) << MCAN_RXF1A_F1AI_SHIFT) & MCAN_RXF1A_F1AI_MASK) -#define MCAN_RXF1A_F1AI_GET(x) (((uint32_t)(x) & MCAN_RXF1A_F1AI_MASK) >> MCAN_RXF1A_F1AI_SHIFT) - -/* Bitfield definition for register: RXESC */ -/* - * RBDS (RW) - * - * Rx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_RBDS_MASK (0x700U) -#define MCAN_RXESC_RBDS_SHIFT (8U) -#define MCAN_RXESC_RBDS_SET(x) (((uint32_t)(x) << MCAN_RXESC_RBDS_SHIFT) & MCAN_RXESC_RBDS_MASK) -#define MCAN_RXESC_RBDS_GET(x) (((uint32_t)(x) & MCAN_RXESC_RBDS_MASK) >> MCAN_RXESC_RBDS_SHIFT) - -/* - * F1DS (RW) - * - * Rx FIFO 1 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_F1DS_MASK (0x70U) -#define MCAN_RXESC_F1DS_SHIFT (4U) -#define MCAN_RXESC_F1DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F1DS_SHIFT) & MCAN_RXESC_F1DS_MASK) -#define MCAN_RXESC_F1DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F1DS_MASK) >> MCAN_RXESC_F1DS_SHIFT) - -/* - * F0DS (RW) - * - * Rx FIFO 0 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, - * only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - */ -#define MCAN_RXESC_F0DS_MASK (0x7U) -#define MCAN_RXESC_F0DS_SHIFT (0U) -#define MCAN_RXESC_F0DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F0DS_SHIFT) & MCAN_RXESC_F0DS_MASK) -#define MCAN_RXESC_F0DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F0DS_MASK) >> MCAN_RXESC_F0DS_SHIFT) - -/* Bitfield definition for register: TXBC */ -/* - * TFQM (RW) - * - * Tx FIFO/Queue Mode - * 0= Tx FIFO operation - * 1= Tx Queue operation - */ -#define MCAN_TXBC_TFQM_MASK (0x40000000UL) -#define MCAN_TXBC_TFQM_SHIFT (30U) -#define MCAN_TXBC_TFQM_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQM_SHIFT) & MCAN_TXBC_TFQM_MASK) -#define MCAN_TXBC_TFQM_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQM_MASK) >> MCAN_TXBC_TFQM_SHIFT) - -/* - * TFQS (RW) - * - * Transmit FIFO/Queue Size - * 0= No Tx FIFO/Queue - * 1-32= Number of Tx Buffers used for Tx FIFO/Queue - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_TFQS_MASK (0x3F000000UL) -#define MCAN_TXBC_TFQS_SHIFT (24U) -#define MCAN_TXBC_TFQS_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQS_SHIFT) & MCAN_TXBC_TFQS_MASK) -#define MCAN_TXBC_TFQS_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQS_MASK) >> MCAN_TXBC_TFQS_SHIFT) - -/* - * NDTB (RW) - * - * Number of Dedicated Transmit Buffers - * 0= No Dedicated Tx Buffers - * 1-32= Number of Dedicated Tx Buffers - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_NDTB_MASK (0x3F0000UL) -#define MCAN_TXBC_NDTB_SHIFT (16U) -#define MCAN_TXBC_NDTB_SET(x) (((uint32_t)(x) << MCAN_TXBC_NDTB_SHIFT) & MCAN_TXBC_NDTB_MASK) -#define MCAN_TXBC_NDTB_GET(x) (((uint32_t)(x) & MCAN_TXBC_NDTB_MASK) >> MCAN_TXBC_NDTB_SHIFT) - -/* - * TBSA (RW) - * - * Tx Buffers Start Address - * Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). - * Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - */ -#define MCAN_TXBC_TBSA_MASK (0xFFFCU) -#define MCAN_TXBC_TBSA_SHIFT (2U) -#define MCAN_TXBC_TBSA_SET(x) (((uint32_t)(x) << MCAN_TXBC_TBSA_SHIFT) & MCAN_TXBC_TBSA_MASK) -#define MCAN_TXBC_TBSA_GET(x) (((uint32_t)(x) & MCAN_TXBC_TBSA_MASK) >> MCAN_TXBC_TBSA_SHIFT) - -/* Bitfield definition for register: TXFQS */ -/* - * TFQF (R) - * - * Tx FIFO/Queue Full - * 0= Tx FIFO/Queue not full - * 1= Tx FIFO/Queue full - */ -#define MCAN_TXFQS_TFQF_MASK (0x200000UL) -#define MCAN_TXFQS_TFQF_SHIFT (21U) -#define MCAN_TXFQS_TFQF_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQF_MASK) >> MCAN_TXFQS_TFQF_SHIFT) - -/* - * TFQPI (R) - * - * Tx FIFO/Queue Put Index - * Tx FIFO/Queue write index pointer, range 0 to 31. - */ -#define MCAN_TXFQS_TFQPI_MASK (0x1F0000UL) -#define MCAN_TXFQS_TFQPI_SHIFT (16U) -#define MCAN_TXFQS_TFQPI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQPI_MASK) >> MCAN_TXFQS_TFQPI_SHIFT) - -/* - * TFGI (R) - * - * Tx FIFO Get Index - * Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured - * (TXBC.TFQM = ‘1’). - */ -#define MCAN_TXFQS_TFGI_MASK (0x1F00U) -#define MCAN_TXFQS_TFGI_SHIFT (8U) -#define MCAN_TXFQS_TFGI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFGI_MASK) >> MCAN_TXFQS_TFGI_SHIFT) - -/* - * TFFL (R) - * - * Tx FIFO Free Level - * Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) - * Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with - * the first dedicated Tx Buffers. - * Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - */ -#define MCAN_TXFQS_TFFL_MASK (0x3FU) -#define MCAN_TXFQS_TFFL_SHIFT (0U) -#define MCAN_TXFQS_TFFL_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFFL_MASK) >> MCAN_TXFQS_TFFL_SHIFT) - -/* Bitfield definition for register: TXESC */ -/* - * TBDS (RW) - * - * Tx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - */ -#define MCAN_TXESC_TBDS_MASK (0x7U) -#define MCAN_TXESC_TBDS_SHIFT (0U) -#define MCAN_TXESC_TBDS_SET(x) (((uint32_t)(x) << MCAN_TXESC_TBDS_SHIFT) & MCAN_TXESC_TBDS_MASK) -#define MCAN_TXESC_TBDS_GET(x) (((uint32_t)(x) & MCAN_TXESC_TBDS_MASK) >> MCAN_TXESC_TBDS_SHIFT) - -/* Bitfield definition for register: TXBRP */ -/* - * TRP (R) - * - * Transmission Request Pending - * Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register - * TXBCR. - * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the - * highest priority (Tx Buffer with lowest Message ID). - * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, - * this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. - * After a cancellation has been requested, a finished cancellation is signalled via TXBCF - * ? after successful transmission together with the corresponding TXBTO bit - * ? when the transmission has not yet been started at the point of cancellation - * ? when the transmission has been aborted due to lost arbitration - * ? when an error occurred during frame transmission - * In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. - * 0= No transmission request pending - * 1= Transmission request pending - * Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - */ -#define MCAN_TXBRP_TRP_MASK (0xFFFFFFFFUL) -#define MCAN_TXBRP_TRP_SHIFT (0U) -#define MCAN_TXBRP_TRP_GET(x) (((uint32_t)(x) & MCAN_TXBRP_TRP_MASK) >> MCAN_TXBRP_TRP_SHIFT) - -/* Bitfield definition for register: TXBAR */ -/* - * AR (RW) - * - * Add Request - * Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx - * Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. - * When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. - * 0= No transmission request added - * 1= Transmission requested added - * Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - */ -#define MCAN_TXBAR_AR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBAR_AR_SHIFT (0U) -#define MCAN_TXBAR_AR_SET(x) (((uint32_t)(x) << MCAN_TXBAR_AR_SHIFT) & MCAN_TXBAR_AR_MASK) -#define MCAN_TXBAR_AR_GET(x) (((uint32_t)(x) & MCAN_TXBAR_AR_MASK) >> MCAN_TXBAR_AR_SHIFT) - -/* Bitfield definition for register: TXBCR */ -/* - * CR (RW) - * - * Cancellation Request - * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. - * This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. - * 0= No cancellation pending - * 1= Cancellation pending - */ -#define MCAN_TXBCR_CR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCR_CR_SHIFT (0U) -#define MCAN_TXBCR_CR_SET(x) (((uint32_t)(x) << MCAN_TXBCR_CR_SHIFT) & MCAN_TXBCR_CR_MASK) -#define MCAN_TXBCR_CR_GET(x) (((uint32_t)(x) & MCAN_TXBCR_CR_MASK) >> MCAN_TXBCR_CR_SHIFT) - -/* Bitfield definition for register: TXBTO */ -/* - * TO (R) - * - * Transmission Occurred - * Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmission occurred - * 1= Transmission occurred - */ -#define MCAN_TXBTO_TO_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTO_TO_SHIFT (0U) -#define MCAN_TXBTO_TO_GET(x) (((uint32_t)(x) & MCAN_TXBTO_TO_MASK) >> MCAN_TXBTO_TO_SHIFT) - -/* Bitfield definition for register: TXBCF */ -/* - * CF (R) - * - * Cancellation Finished - * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. - * In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmit buffer cancellation - * 1= Transmit buffer cancellation finished - */ -#define MCAN_TXBCF_CF_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCF_CF_SHIFT (0U) -#define MCAN_TXBCF_CF_GET(x) (((uint32_t)(x) & MCAN_TXBCF_CF_MASK) >> MCAN_TXBCF_CF_SHIFT) - -/* Bitfield definition for register: TXBTIE */ -/* - * TIE (RW) - * - * Transmission Interrupt Enable - * Each Tx Buffer has its own Transmission Interrupt Enable bit. - * 0= Transmission interrupt disabled - * 1= Transmission interrupt enable - */ -#define MCAN_TXBTIE_TIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTIE_TIE_SHIFT (0U) -#define MCAN_TXBTIE_TIE_SET(x) (((uint32_t)(x) << MCAN_TXBTIE_TIE_SHIFT) & MCAN_TXBTIE_TIE_MASK) -#define MCAN_TXBTIE_TIE_GET(x) (((uint32_t)(x) & MCAN_TXBTIE_TIE_MASK) >> MCAN_TXBTIE_TIE_SHIFT) - -/* Bitfield definition for register: TXBCIE */ -/* - * CFIE (RW) - * - * Cancellation Finished Interrupt Enable - * Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. - * 0= Cancellation finished interrupt disabled - * 1= Cancellation finished interrupt enabled - */ -#define MCAN_TXBCIE_CFIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCIE_CFIE_SHIFT (0U) -#define MCAN_TXBCIE_CFIE_SET(x) (((uint32_t)(x) << MCAN_TXBCIE_CFIE_SHIFT) & MCAN_TXBCIE_CFIE_MASK) -#define MCAN_TXBCIE_CFIE_GET(x) (((uint32_t)(x) & MCAN_TXBCIE_CFIE_MASK) >> MCAN_TXBCIE_CFIE_SHIFT) - -/* Bitfield definition for register: TXEFC */ -/* - * EFWM (RW) - * - * Event FIFO Watermark - * 0= Watermark interrupt disabled - * 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) - * >32= Watermark interrupt disabled - */ -#define MCAN_TXEFC_EFWM_MASK (0x3F000000UL) -#define MCAN_TXEFC_EFWM_SHIFT (24U) -#define MCAN_TXEFC_EFWM_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFWM_SHIFT) & MCAN_TXEFC_EFWM_MASK) -#define MCAN_TXEFC_EFWM_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFWM_MASK) >> MCAN_TXEFC_EFWM_SHIFT) - -/* - * EFS (RW) - * - * Event FIFO Size - * 0= Tx Event FIFO disabled - * 1-32= Number of Tx Event FIFO elements - * >32= Values greater than 32 are interpreted as 32 - * The Tx Event FIFO elements are indexed from 0 to EFS - 1 - */ -#define MCAN_TXEFC_EFS_MASK (0x3F0000UL) -#define MCAN_TXEFC_EFS_SHIFT (16U) -#define MCAN_TXEFC_EFS_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFS_SHIFT) & MCAN_TXEFC_EFS_MASK) -#define MCAN_TXEFC_EFS_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFS_MASK) >> MCAN_TXEFC_EFS_SHIFT) - -/* - * EFSA (RW) - * - * Event FIFO Start Address - * Start address of Tx Event FIFO in Message RAM (32-bit word address) - */ -#define MCAN_TXEFC_EFSA_MASK (0xFFFCU) -#define MCAN_TXEFC_EFSA_SHIFT (2U) -#define MCAN_TXEFC_EFSA_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFSA_SHIFT) & MCAN_TXEFC_EFSA_MASK) -#define MCAN_TXEFC_EFSA_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFSA_MASK) >> MCAN_TXEFC_EFSA_SHIFT) - -/* Bitfield definition for register: TXEFS */ -/* - * TEFL (R) - * - * Tx Event FIFO Element Lost - * This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - */ -#define MCAN_TXEFS_TEFL_MASK (0x2000000UL) -#define MCAN_TXEFS_TEFL_SHIFT (25U) -#define MCAN_TXEFS_TEFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_TEFL_MASK) >> MCAN_TXEFS_TEFL_SHIFT) - -/* - * EFF (R) - * - * Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_TXEFS_EFF_MASK (0x1000000UL) -#define MCAN_TXEFS_EFF_SHIFT (24U) -#define MCAN_TXEFS_EFF_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFF_MASK) >> MCAN_TXEFS_EFF_SHIFT) - -/* - * EFPI (R) - * - * Event FIFO Put Index - * Tx Event FIFO write index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFPI_MASK (0x1F0000UL) -#define MCAN_TXEFS_EFPI_SHIFT (16U) -#define MCAN_TXEFS_EFPI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFPI_MASK) >> MCAN_TXEFS_EFPI_SHIFT) - -/* - * EFGI (R) - * - * Event FIFO Get Index - * Tx Event FIFO read index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFGI_MASK (0x1F00U) -#define MCAN_TXEFS_EFGI_SHIFT (8U) -#define MCAN_TXEFS_EFGI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFGI_MASK) >> MCAN_TXEFS_EFGI_SHIFT) - -/* - * EFFL (R) - * - * Event FIFO Fill Level - * Number of elements stored in Tx Event FIFO, range 0 to 32. - */ -#define MCAN_TXEFS_EFFL_MASK (0x3FU) -#define MCAN_TXEFS_EFFL_SHIFT (0U) -#define MCAN_TXEFS_EFFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFFL_MASK) >> MCAN_TXEFS_EFFL_SHIFT) - -/* Bitfield definition for register: TXEFA */ -/* - * EFAI (RW) - * - * Event FIFO Acknowledge Index - * After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get - * Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - */ -#define MCAN_TXEFA_EFAI_MASK (0x1FU) -#define MCAN_TXEFA_EFAI_SHIFT (0U) -#define MCAN_TXEFA_EFAI_SET(x) (((uint32_t)(x) << MCAN_TXEFA_EFAI_SHIFT) & MCAN_TXEFA_EFAI_MASK) -#define MCAN_TXEFA_EFAI_GET(x) (((uint32_t)(x) & MCAN_TXEFA_EFAI_MASK) >> MCAN_TXEFA_EFAI_SHIFT) - -/* Bitfield definition for register array: TS_SEL */ -/* - * TS (R) - * - * Timestamp Word TS - * default can save 16 timestamps with 32bit; - * if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - */ -#define MCAN_TS_SEL_TS_MASK (0xFFFFFFFFUL) -#define MCAN_TS_SEL_TS_SHIFT (0U) -#define MCAN_TS_SEL_TS_GET(x) (((uint32_t)(x) & MCAN_TS_SEL_TS_MASK) >> MCAN_TS_SEL_TS_SHIFT) - -/* Bitfield definition for register: CREL */ -/* - * REL (R) - * - * Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_REL_MASK (0xF0000000UL) -#define MCAN_CREL_REL_SHIFT (28U) -#define MCAN_CREL_REL_GET(x) (((uint32_t)(x) & MCAN_CREL_REL_MASK) >> MCAN_CREL_REL_SHIFT) - -/* - * STEP (R) - * - * Step of Core Release - * One digit, BCD-coded. - */ -#define MCAN_CREL_STEP_MASK (0xF000000UL) -#define MCAN_CREL_STEP_SHIFT (24U) -#define MCAN_CREL_STEP_GET(x) (((uint32_t)(x) & MCAN_CREL_STEP_MASK) >> MCAN_CREL_STEP_SHIFT) - -/* - * SUBSTEP (R) - * - * Sub-step of Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_SUBSTEP_MASK (0xF00000UL) -#define MCAN_CREL_SUBSTEP_SHIFT (20U) -#define MCAN_CREL_SUBSTEP_GET(x) (((uint32_t)(x) & MCAN_CREL_SUBSTEP_MASK) >> MCAN_CREL_SUBSTEP_SHIFT) - -/* - * YEAR (R) - * - * Timestamp Year - * One digit, BCD-coded. This field is set by generic parameter on - * synthesis. - */ -#define MCAN_CREL_YEAR_MASK (0xF0000UL) -#define MCAN_CREL_YEAR_SHIFT (16U) -#define MCAN_CREL_YEAR_GET(x) (((uint32_t)(x) & MCAN_CREL_YEAR_MASK) >> MCAN_CREL_YEAR_SHIFT) - -/* - * MON (R) - * - * Timestamp Month - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_MON_MASK (0xFF00U) -#define MCAN_CREL_MON_SHIFT (8U) -#define MCAN_CREL_MON_GET(x) (((uint32_t)(x) & MCAN_CREL_MON_MASK) >> MCAN_CREL_MON_SHIFT) - -/* - * DAY (R) - * - * Timestamp Day - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_DAY_MASK (0xFFU) -#define MCAN_CREL_DAY_SHIFT (0U) -#define MCAN_CREL_DAY_GET(x) (((uint32_t)(x) & MCAN_CREL_DAY_MASK) >> MCAN_CREL_DAY_SHIFT) - -/* Bitfield definition for register: TSCFG */ -/* - * TBPRE (RW) - * - * Timebase Prescaler - * 0x00 to 0xFF - * The value by which the oscillator frequency is divided for - * generating the timebase counter clock. Valid values for the - * Timebase Prescaler are 0 to 255. The actual interpretation by - * the hardware of this value is such that one more than the value - * programmed here is used. Affects only the TSU internal - * timebase. When the internal timebase is excluded by synthesis, - * TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not - * used. - */ -#define MCAN_TSCFG_TBPRE_MASK (0xFF00U) -#define MCAN_TSCFG_TBPRE_SHIFT (8U) -#define MCAN_TSCFG_TBPRE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBPRE_SHIFT) & MCAN_TSCFG_TBPRE_MASK) -#define MCAN_TSCFG_TBPRE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBPRE_MASK) >> MCAN_TSCFG_TBPRE_SHIFT) - -/* - * EN64 (RW) - * - * set to use 64bit timestamp. - * when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. - * TSP can be used to select different one - */ -#define MCAN_TSCFG_EN64_MASK (0x8U) -#define MCAN_TSCFG_EN64_SHIFT (3U) -#define MCAN_TSCFG_EN64_SET(x) (((uint32_t)(x) << MCAN_TSCFG_EN64_SHIFT) & MCAN_TSCFG_EN64_MASK) -#define MCAN_TSCFG_EN64_GET(x) (((uint32_t)(x) & MCAN_TSCFG_EN64_MASK) >> MCAN_TSCFG_EN64_SHIFT) - -/* - * SCP (RW) - * - * Select Capturing Position - * 0: Capture Timestamp at EOF - * 1: Capture Timestamp at SOF - */ -#define MCAN_TSCFG_SCP_MASK (0x4U) -#define MCAN_TSCFG_SCP_SHIFT (2U) -#define MCAN_TSCFG_SCP_SET(x) (((uint32_t)(x) << MCAN_TSCFG_SCP_SHIFT) & MCAN_TSCFG_SCP_MASK) -#define MCAN_TSCFG_SCP_GET(x) (((uint32_t)(x) & MCAN_TSCFG_SCP_MASK) >> MCAN_TSCFG_SCP_SHIFT) - -/* - * TBCS (RW) - * - * Timebase Counter Select - * When the internal timebase is excluded by synthesis, TBCS is - * fixed to ‘1’. - * 0: Timestamp value captured from internal timebase counter, - * ATB.TB[31:0] is the internal timbase counter - * 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - */ -#define MCAN_TSCFG_TBCS_MASK (0x2U) -#define MCAN_TSCFG_TBCS_SHIFT (1U) -#define MCAN_TSCFG_TBCS_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBCS_SHIFT) & MCAN_TSCFG_TBCS_MASK) -#define MCAN_TSCFG_TBCS_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBCS_MASK) >> MCAN_TSCFG_TBCS_SHIFT) - -/* - * TSUE (RW) - * - * Timestamp Unit Enable - * 0: TSU disabled - * 1: TSU enabled - */ -#define MCAN_TSCFG_TSUE_MASK (0x1U) -#define MCAN_TSCFG_TSUE_SHIFT (0U) -#define MCAN_TSCFG_TSUE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TSUE_SHIFT) & MCAN_TSCFG_TSUE_MASK) -#define MCAN_TSCFG_TSUE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TSUE_MASK) >> MCAN_TSCFG_TSUE_SHIFT) - -/* Bitfield definition for register: TSS1 */ -/* - * TSL (R) - * - * Timestamp Lost - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. - * Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSL_MASK (0xFFFF0000UL) -#define MCAN_TSS1_TSL_SHIFT (16U) -#define MCAN_TSS1_TSL_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSL_MASK) >> MCAN_TSS1_TSL_SHIFT) - -/* - * TSN (R) - * - * Timestamp New - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related - * Timestamp register. Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSN_MASK (0xFFFFU) -#define MCAN_TSS1_TSN_SHIFT (0U) -#define MCAN_TSS1_TSN_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSN_MASK) >> MCAN_TSS1_TSN_SHIFT) - -/* Bitfield definition for register: TSS2 */ -/* - * TSP (R) - * - * Timestamp Pointer - * The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 - * depending on number_ts_g), it is incremented to 0. - * Value also signalled on output m_can_tsp[3:0]. - */ -#define MCAN_TSS2_TSP_MASK (0xFU) -#define MCAN_TSS2_TSP_SHIFT (0U) -#define MCAN_TSS2_TSP_GET(x) (((uint32_t)(x) & MCAN_TSS2_TSP_MASK) >> MCAN_TSS2_TSP_SHIFT) - -/* Bitfield definition for register: ATB */ -/* - * TB (RC) - * - * timebase for timestamp generation 31-0 - */ -#define MCAN_ATB_TB_MASK (0xFFFFFFFFUL) -#define MCAN_ATB_TB_SHIFT (0U) -#define MCAN_ATB_TB_GET(x) (((uint32_t)(x) & MCAN_ATB_TB_MASK) >> MCAN_ATB_TB_SHIFT) - -/* Bitfield definition for register: ATBH */ -/* - * TBH (RC) - * - * timebase for timestamp generation 63-32 - */ -#define MCAN_ATBH_TBH_MASK (0xFFFFFFFFUL) -#define MCAN_ATBH_TBH_SHIFT (0U) -#define MCAN_ATBH_TBH_GET(x) (((uint32_t)(x) & MCAN_ATBH_TBH_MASK) >> MCAN_ATBH_TBH_SHIFT) - -/* Bitfield definition for register: GLB_CTL */ -/* - * M_CAN_STBY (RW) - * - * m_can standby control - */ -#define MCAN_GLB_CTL_M_CAN_STBY_MASK (0x80000000UL) -#define MCAN_GLB_CTL_M_CAN_STBY_SHIFT (31U) -#define MCAN_GLB_CTL_M_CAN_STBY_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_M_CAN_STBY_SHIFT) & MCAN_GLB_CTL_M_CAN_STBY_MASK) -#define MCAN_GLB_CTL_M_CAN_STBY_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_M_CAN_STBY_MASK) >> MCAN_GLB_CTL_M_CAN_STBY_SHIFT) - -/* - * STBY_CLR_EN (RW) - * - * m_can standby clear control - * 0:controlled by software by standby bit[bit31] - * 1:auto clear standby by hardware when rx data is 0 - */ -#define MCAN_GLB_CTL_STBY_CLR_EN_MASK (0x40000000UL) -#define MCAN_GLB_CTL_STBY_CLR_EN_SHIFT (30U) -#define MCAN_GLB_CTL_STBY_CLR_EN_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) -#define MCAN_GLB_CTL_STBY_CLR_EN_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) >> MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) - -/* - * STBY_POL (RW) - * - * standby polarity selection - */ -#define MCAN_GLB_CTL_STBY_POL_MASK (0x20000000UL) -#define MCAN_GLB_CTL_STBY_POL_SHIFT (29U) -#define MCAN_GLB_CTL_STBY_POL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_POL_SHIFT) & MCAN_GLB_CTL_STBY_POL_MASK) -#define MCAN_GLB_CTL_STBY_POL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_POL_MASK) >> MCAN_GLB_CTL_STBY_POL_SHIFT) - -/* - * TSU_TBIN_SEL (RW) - * - * external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - */ -#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x3U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) - -/* Bitfield definition for register: GLB_STATUS */ -/* - * M_CAN_INT1 (R) - * - * m_can interrupt status1 - */ -#define MCAN_GLB_STATUS_M_CAN_INT1_MASK (0x8U) -#define MCAN_GLB_STATUS_M_CAN_INT1_SHIFT (3U) -#define MCAN_GLB_STATUS_M_CAN_INT1_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT1_MASK) >> MCAN_GLB_STATUS_M_CAN_INT1_SHIFT) - -/* - * M_CAN_INT0 (R) - * - * m_can interrupt status0 - */ -#define MCAN_GLB_STATUS_M_CAN_INT0_MASK (0x4U) -#define MCAN_GLB_STATUS_M_CAN_INT0_SHIFT (2U) -#define MCAN_GLB_STATUS_M_CAN_INT0_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT0_MASK) >> MCAN_GLB_STATUS_M_CAN_INT0_SHIFT) - - - -/* TS_SEL register group index macro definition */ -#define MCAN_TS_SEL_TS_SEL0 (0UL) -#define MCAN_TS_SEL_TS_SEL1 (1UL) -#define MCAN_TS_SEL_TS_SEL2 (2UL) -#define MCAN_TS_SEL_TS_SEL3 (3UL) -#define MCAN_TS_SEL_TS_SEL4 (4UL) -#define MCAN_TS_SEL_TS_SEL5 (5UL) -#define MCAN_TS_SEL_TS_SEL6 (6UL) -#define MCAN_TS_SEL_TS_SEL7 (7UL) -#define MCAN_TS_SEL_TS_SEL8 (8UL) -#define MCAN_TS_SEL_TS_SEL9 (9UL) -#define MCAN_TS_SEL_TS_SEL10 (10UL) -#define MCAN_TS_SEL_TS_SEL11 (11UL) -#define MCAN_TS_SEL_TS_SEL12 (12UL) -#define MCAN_TS_SEL_TS_SEL13 (13UL) -#define MCAN_TS_SEL_TS_SEL14 (14UL) -#define MCAN_TS_SEL_TS_SEL15 (15UL) - - -#endif /* HPM_MCAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mchtmr_regs.h deleted file mode 100644 index d9dfe58a7b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mchtmr_regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCHTMR_H -#define HPM_MCHTMR_H - -typedef struct { - __RW uint64_t MTIME; /* 0x0: Machine Time */ - __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ -} MCHTMR_Type; - - -/* Bitfield definition for register: MTIME */ -/* - * MTIME (RW) - * - * Machine time - */ -#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIME_MTIME_SHIFT (0U) -#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) -#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) - -/* Bitfield definition for register: MTIMECMP */ -/* - * MTIMECMP (RW) - * - * Machine time compare - */ -#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) -#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) -#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) - - - - -#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mmc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mmc_regs.h deleted file mode 100644 index 9c130fab754..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mmc_regs.h +++ /dev/null @@ -1,1621 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MMC_H -#define HPM_MMC_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t STA; /* 0x4: Status Register */ - __RW uint32_t INT_EN; /* 0x8: Interrupt Enable Register */ - __RW uint32_t SYSCLK_FREQ; /* 0xC: System Clock Frequency Register */ - __RW uint32_t SYSCLK_PERIOD; /* 0x10: System Clock Period Register */ - __RW uint32_t OOSYNC_THETA_THR; /* 0x14: Position Out-Of-Sync Threshold Regster */ - __RW uint32_t DISCRETECFG0; /* 0x18: Discrete Mode Configuration 0 Register */ - __RW uint32_t DISCRETECFG1; /* 0x1C: Discrete Mode Configuration 1 Register */ - __RW uint32_t CONTCFG0; /* 0x20: Continuous Mode Configuration 0 Register */ - __RW uint32_t INI_POS_TIME; /* 0x24: The destined timestamp register for position initialization */ - __RW uint32_t INI_POS; /* 0x28: The destined position register for position initialization */ - __RW uint32_t INI_REV; /* 0x2C: The destined revolution register for position initialization */ - __RW uint32_t INI_SPEED; /* 0x30: The destined speed register for position initialization */ - __RW uint32_t INI_ACCEL; /* 0x34: The destined accelerator register for position initialization */ - __RW uint32_t INI_COEF_TIME; /* 0x38: The destined timestamp register for coefficients initialization */ - __RW uint32_t INI_PCOEF; /* 0x3C: The destined coefficient P register for coefficients initialization */ - __RW uint32_t INI_ICOEF; /* 0x40: The destined coefficient I register for coefficients initialization */ - __RW uint32_t INI_ACOEF; /* 0x44: The destined coefficient A register for coefficients initialization */ - __R uint32_t ESTM_TIM; /* 0x48: The timestamp register for internal estimation */ - __R uint32_t ESTM_POS; /* 0x4C: The position register for the internal estimation */ - __R uint32_t ESTM_REV; /* 0x50: The revolution register for the internal estimation */ - __R uint32_t ESTM_SPEED; /* 0x54: The speed register for the internal estimation */ - __R uint32_t ESTM_ACCEL; /* 0x58: The accelerator register for theinternal estimation */ - __R uint32_t CUR_PCOEF; /* 0x5C: The coefficient P register for the internal estimation */ - __R uint32_t CUR_ICOEF; /* 0x60: The coefficient I register for the internal estimation */ - __R uint32_t CUR_ACOEF; /* 0x64: The coefficient A register for the internal estimation */ - __RW uint32_t INI_DELTA_POS_TIME; /* 0x68: The destined timestamp register for delta position initialization */ - __RW uint32_t INI_DELTA_POS; /* 0x6C: The destined delta position register for delta position initialization */ - __RW uint32_t INI_DELTA_REV; /* 0x70: The destined delta revolution register for delta position initialization */ - __RW uint32_t INI_DELTA_SPEED; /* 0x74: The destined delta speed register for delta position initialization */ - __RW uint32_t INI_DELTA_ACCEL; /* 0x78: The destined delta accelerator register for delta position initialization */ - __R uint8_t RESERVED0[4]; /* 0x7C - 0x7F: Reserved */ - __RW uint32_t POS_TRG_CFG; /* 0x80: Tracking Configuration pos trigger cfg */ - __RW uint32_t POS_TRG_POS_THR; /* 0x84: Tracking Configuration position threshold */ - __RW uint32_t POS_TRG_REV_THR; /* 0x88: Tracking Configuration revolution threshold */ - __RW uint32_t SPEED_TRG_CFG; /* 0x8C: Tracking Configuration speed trigger cfg */ - __RW uint32_t SPEED_TRG_THR; /* 0x90: Tracking Configuration speed threshold */ - __R uint8_t RESERVED1[12]; /* 0x94 - 0x9F: Reserved */ - struct { - __RW uint32_t ERR_THR; /* 0xA0: Tracking Configuration coef trigger cfg */ - __RW uint32_t P; /* 0xA4: Tracking Configuration coef trigger cfg P */ - __RW uint32_t I; /* 0xA8: Tracking Configuration coef trigger cfg I */ - __RW uint32_t A; /* 0xAC: Tracking Configuration coef trigger cfg A */ - __RW uint32_t TIME; /* 0xB0: Tracking Configuration coef trigger cfg time */ - } COEF_TRG_CFG[3]; - __R uint8_t RESERVED2[36]; /* 0xDC - 0xFF: Reserved */ - struct { - __RW uint32_t BR_CTRL; /* 0x100: Prediction Control Register */ - __RW uint32_t BR_TIMEOFF; /* 0x104: Prediction Timing Offset Register */ - __RW uint32_t BR_TRG_PERIOD; /* 0x108: Prediction Triggering Period Offset Register */ - __RW uint32_t BR_TRG_F_TIME; /* 0x10C: Prediction Triggering First Offset Register */ - __RW uint32_t BR_ST; /* 0x110: Prediction Status Register */ - __R uint8_t RESERVED0[44]; /* 0x114 - 0x13F: Reserved */ - __RW uint32_t BR_TRG_POS_CFG; /* 0x140: Prediction Configuration postion trigger cfg */ - __RW uint32_t BR_TRG_POS_THR; /* 0x144: Prediction Configuration postion threshold */ - __RW uint32_t BR_TRG_REV_THR; /* 0x148: Prediction Configuration revolutiom threshold */ - __RW uint32_t BR_TRG_SPEED_CFG; /* 0x14C: Prediction Configuration speed trigger cfg */ - __RW uint32_t BR_TRG_SPEED_THR; /* 0x150: Prediction Configuration speed threshold */ - __R uint8_t RESERVED1[108]; /* 0x154 - 0x1BF: Reserved */ - __RW uint32_t BR_INI_POS_TIME; /* 0x1C0: Initialization timestamp for open-loop mode */ - __RW uint32_t BR_INI_POS; /* 0x1C4: Initialization position for open-loop mode */ - __RW uint32_t BR_INI_REV; /* 0x1C8: Initialization revolution for open-loop mode */ - __RW uint32_t BR_INI_SPEED; /* 0x1CC: Initialization speed for open-loop mode */ - __RW uint32_t BR_INI_ACCEL; /* 0x1D0: Initialization acceleration for open-loop mode */ - __RW uint32_t BR_INI_DELTA_POS_TIME; /* 0x1D4: Initialization timestamp for delta mode in prediction mode */ - __RW uint32_t BR_INI_DELTA_POS; /* 0x1D8: Initialization delta position for delta mode in prediction mode */ - __RW uint32_t BR_INI_DELTA_REV; /* 0x1DC: Initialization delta revolution for delta mode in prediction mode */ - __RW uint32_t BR_INI_DELTA_SPEED; /* 0x1E0: Initialization delta speed for delta mode in prediction mode */ - __RW uint32_t BR_INI_DELTA_ACCEL; /* 0x1E4: Initialization delta acceleration for delta mode in prediction mode */ - __R uint8_t RESERVED2[4]; /* 0x1E8 - 0x1EB: Reserved */ - __R uint32_t BR_CUR_POS_TIME; /* 0x1EC: Monitor of the output timestamp */ - __R uint32_t BR_CUR_POS; /* 0x1F0: Monitor of the output position */ - __R uint32_t BR_CUR_REV; /* 0x1F4: Monitor of the output revolution */ - __R uint32_t BR_CUR_SPEED; /* 0x1F8: Monitor of the output speed */ - __R uint32_t BR_CUR_ACCEL; /* 0x1FC: Monitor of the output acceleration */ - } BR[2]; - __R uint32_t BK0_TIMESTAMP; /* 0x300: Monitor of the just received input timestamp for tracing logic */ - __R uint32_t BK0_POSITION; /* 0x304: Monitor of the just received input position for tracing logic */ - __R uint32_t BK0_REVOLUTION; /* 0x308: Monitor of the just received input revolution for tracing logic */ - __R uint32_t BK0_SPEED; /* 0x30C: Monitor of the just received input speed for tracing logic */ - __R uint32_t BK0_ACCELERATOR; /* 0x310: Monitor of the just received input acceleration for tracing logic */ - __R uint8_t RESERVED3[12]; /* 0x314 - 0x31F: Reserved */ - __R uint32_t BK1_TIMESTAMP; /* 0x320: Monitor of the previous received input timestamp for tracing logic */ - __R uint32_t BK1_POSITION; /* 0x324: Monitor of the previous received input position for tracing logic */ - __R uint32_t BK1_REVOLUTION; /* 0x328: Monitor of the previous received input revolution for tracing logic */ - __R uint32_t BK1_SPEED; /* 0x32C: Monitor of the previous received input speed for tracing logic */ - __R uint32_t BK1_ACCELERATOR; /* 0x330: Monitor of the previous received input acceleration for tracing logic */ -} MMC_Type; - - -/* Bitfield definition for register: CR */ -/* - * SFTRST (RW) - * - * Software reset, high active. When write 1 ,all internal logical will be reset. - * 0b - No action - * 1b - All MMC internal registers are forced into their reset state. Interface registers are not affected. - */ -#define MMC_CR_SFTRST_MASK (0x80000000UL) -#define MMC_CR_SFTRST_SHIFT (31U) -#define MMC_CR_SFTRST_SET(x) (((uint32_t)(x) << MMC_CR_SFTRST_SHIFT) & MMC_CR_SFTRST_MASK) -#define MMC_CR_SFTRST_GET(x) (((uint32_t)(x) & MMC_CR_SFTRST_MASK) >> MMC_CR_SFTRST_SHIFT) - -/* - * INI_BR0_POS_REQ (RW) - * - * Auto clear. Only effective in open_loop mode. - */ -#define MMC_CR_INI_BR0_POS_REQ_MASK (0x20000000UL) -#define MMC_CR_INI_BR0_POS_REQ_SHIFT (29U) -#define MMC_CR_INI_BR0_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR0_POS_REQ_SHIFT) & MMC_CR_INI_BR0_POS_REQ_MASK) -#define MMC_CR_INI_BR0_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR0_POS_REQ_MASK) >> MMC_CR_INI_BR0_POS_REQ_SHIFT) - -/* - * INI_BR1_POS_REQ (RW) - * - * Auto clear. Only effective in open_loop mode. - */ -#define MMC_CR_INI_BR1_POS_REQ_MASK (0x10000000UL) -#define MMC_CR_INI_BR1_POS_REQ_SHIFT (28U) -#define MMC_CR_INI_BR1_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_BR1_POS_REQ_SHIFT) & MMC_CR_INI_BR1_POS_REQ_MASK) -#define MMC_CR_INI_BR1_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_BR1_POS_REQ_MASK) >> MMC_CR_INI_BR1_POS_REQ_SHIFT) - -/* - * FRCACCELZERO (RW) - * - * Zeroise the accelerator calculation. - */ -#define MMC_CR_FRCACCELZERO_MASK (0x8000000UL) -#define MMC_CR_FRCACCELZERO_SHIFT (27U) -#define MMC_CR_FRCACCELZERO_SET(x) (((uint32_t)(x) << MMC_CR_FRCACCELZERO_SHIFT) & MMC_CR_FRCACCELZERO_MASK) -#define MMC_CR_FRCACCELZERO_GET(x) (((uint32_t)(x) & MMC_CR_FRCACCELZERO_MASK) >> MMC_CR_FRCACCELZERO_SHIFT) - -/* - * MS_COEF_EN (RW) - * - * Multiple Coefficients Enable - */ -#define MMC_CR_MS_COEF_EN_MASK (0x4000000UL) -#define MMC_CR_MS_COEF_EN_SHIFT (26U) -#define MMC_CR_MS_COEF_EN_SET(x) (((uint32_t)(x) << MMC_CR_MS_COEF_EN_SHIFT) & MMC_CR_MS_COEF_EN_MASK) -#define MMC_CR_MS_COEF_EN_GET(x) (((uint32_t)(x) & MMC_CR_MS_COEF_EN_MASK) >> MMC_CR_MS_COEF_EN_SHIFT) - -/* - * INI_DELTA_POS_TRG_TYPE (RW) - * - * 0: Time Stamp in the configuration - * 1: Risedge of In Trg[0] - * 2: Risedge of In Trg[1] - * 3: Risedge of out trg[0] - * 4: Risedge of out trg[1] - * 5: triggered by self position trigger - * 6: triggered by self speed trigger - * Otherser: no function - */ -#define MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK (0x3800000UL) -#define MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT (23U) -#define MMC_CR_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) -#define MMC_CR_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_CR_INI_DELTA_POS_TRG_TYPE_SHIFT) - -/* - * INI_POS_TRG_TYPE (RW) - * - * 0: Time Stamp in the configuration - * 1: Risedge of In Trg[0] - * 2: Risedge of In Trg[1] - * 3: Risedge of out trg[0] - * 4: Risedge of out trg[1] - * 5: triggered by self position trigger - * 6: triggered by self speed trigger - * Otherser: no function - */ -#define MMC_CR_INI_POS_TRG_TYPE_MASK (0x700000UL) -#define MMC_CR_INI_POS_TRG_TYPE_SHIFT (20U) -#define MMC_CR_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_TRG_TYPE_SHIFT) & MMC_CR_INI_POS_TRG_TYPE_MASK) -#define MMC_CR_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_TRG_TYPE_MASK) >> MMC_CR_INI_POS_TRG_TYPE_SHIFT) - -/* - * INI_DELTA_POS_CMD_MSK (RW) - * - * 1: change - * 0: won't change - * bit 3: for delta accel - * bit 2: for delta speed - * bit 1: for delta revolution - * bit 0: for delta position - */ -#define MMC_CR_INI_DELTA_POS_CMD_MSK_MASK (0xF0000UL) -#define MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT (16U) -#define MMC_CR_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) -#define MMC_CR_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_CR_INI_DELTA_POS_CMD_MSK_SHIFT) - -/* - * INI_DELTA_POS_REQ (RW) - * - * 1: Command to reload the delta pos. Auto clear - * 0: - */ -#define MMC_CR_INI_DELTA_POS_REQ_MASK (0x8000U) -#define MMC_CR_INI_DELTA_POS_REQ_SHIFT (15U) -#define MMC_CR_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_DELTA_POS_REQ_SHIFT) & MMC_CR_INI_DELTA_POS_REQ_MASK) -#define MMC_CR_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_DELTA_POS_REQ_MASK) >> MMC_CR_INI_DELTA_POS_REQ_SHIFT) - -/* - * OPEN_LOOP_MODE (RW) - * - * 1: in open loop mode - * 0: not in open loop mode - */ -#define MMC_CR_OPEN_LOOP_MODE_MASK (0x4000U) -#define MMC_CR_OPEN_LOOP_MODE_SHIFT (14U) -#define MMC_CR_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_CR_OPEN_LOOP_MODE_SHIFT) & MMC_CR_OPEN_LOOP_MODE_MASK) -#define MMC_CR_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_CR_OPEN_LOOP_MODE_MASK) >> MMC_CR_OPEN_LOOP_MODE_SHIFT) - -/* - * POS_TYPE (RW) - * - * 1: 32-bit for rev+pos, with each element occupying 16 bits - * 0: 32-bit for rev, and 32 bit for pos - * When CR[MANUAL_IO]==1, - * 1: means that the INI_POS is acting as INI_POS cmds - * 0: means that the INI_POS is simulating the input of iposition and itimestamp - */ -#define MMC_CR_POS_TYPE_MASK (0x2000U) -#define MMC_CR_POS_TYPE_SHIFT (13U) -#define MMC_CR_POS_TYPE_SET(x) (((uint32_t)(x) << MMC_CR_POS_TYPE_SHIFT) & MMC_CR_POS_TYPE_MASK) -#define MMC_CR_POS_TYPE_GET(x) (((uint32_t)(x) & MMC_CR_POS_TYPE_MASK) >> MMC_CR_POS_TYPE_SHIFT) - -/* - * INI_POS_CMD_MSK (RW) - * - * 1: change - * 0: won't change - * bit 3: for accel - * bit 2: for speed - * bit 1: for revolution - * bit 0: for position - */ -#define MMC_CR_INI_POS_CMD_MSK_MASK (0x1E00U) -#define MMC_CR_INI_POS_CMD_MSK_SHIFT (9U) -#define MMC_CR_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_CMD_MSK_SHIFT) & MMC_CR_INI_POS_CMD_MSK_MASK) -#define MMC_CR_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_CMD_MSK_MASK) >> MMC_CR_INI_POS_CMD_MSK_SHIFT) - -/* - * INI_POS_REQ (RW) - * - * 1: Command to reload the positions. Auto clear - * 0: - */ -#define MMC_CR_INI_POS_REQ_MASK (0x100U) -#define MMC_CR_INI_POS_REQ_SHIFT (8U) -#define MMC_CR_INI_POS_REQ_SET(x) (((uint32_t)(x) << MMC_CR_INI_POS_REQ_SHIFT) & MMC_CR_INI_POS_REQ_MASK) -#define MMC_CR_INI_POS_REQ_GET(x) (((uint32_t)(x) & MMC_CR_INI_POS_REQ_MASK) >> MMC_CR_INI_POS_REQ_SHIFT) - -/* - * INI_COEFS_CMD_MSK (RW) - * - * 1: change - * 0: won't change - * bit 2: for ACOEF - * bit 1: for ICOEF - * bit 0: for PCOEF - */ -#define MMC_CR_INI_COEFS_CMD_MSK_MASK (0xE0U) -#define MMC_CR_INI_COEFS_CMD_MSK_SHIFT (5U) -#define MMC_CR_INI_COEFS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_MSK_SHIFT) & MMC_CR_INI_COEFS_CMD_MSK_MASK) -#define MMC_CR_INI_COEFS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MSK_MASK) >> MMC_CR_INI_COEFS_CMD_MSK_SHIFT) - -/* - * INI_COEFS_CMD (RW) - * - * 1: Command to reload the coefs. Auto clear - * 0: - */ -#define MMC_CR_INI_COEFS_CMD_MASK (0x10U) -#define MMC_CR_INI_COEFS_CMD_SHIFT (4U) -#define MMC_CR_INI_COEFS_CMD_SET(x) (((uint32_t)(x) << MMC_CR_INI_COEFS_CMD_SHIFT) & MMC_CR_INI_COEFS_CMD_MASK) -#define MMC_CR_INI_COEFS_CMD_GET(x) (((uint32_t)(x) & MMC_CR_INI_COEFS_CMD_MASK) >> MMC_CR_INI_COEFS_CMD_SHIFT) - -/* - * SHADOW_RD_REQ (RW) - * - * 1: Shadow Request for read of tracking parameters. Auto clear - * 0: - */ -#define MMC_CR_SHADOW_RD_REQ_MASK (0x8U) -#define MMC_CR_SHADOW_RD_REQ_SHIFT (3U) -#define MMC_CR_SHADOW_RD_REQ_SET(x) (((uint32_t)(x) << MMC_CR_SHADOW_RD_REQ_SHIFT) & MMC_CR_SHADOW_RD_REQ_MASK) -#define MMC_CR_SHADOW_RD_REQ_GET(x) (((uint32_t)(x) & MMC_CR_SHADOW_RD_REQ_MASK) >> MMC_CR_SHADOW_RD_REQ_SHIFT) - -/* - * ADJOP (RW) - * - * 1: use the input iposition whenever a new iposition comes, and force the predicted output stop at the boundaries. - * 0: Continuous tracking mode, without any boundary check - */ -#define MMC_CR_ADJOP_MASK (0x4U) -#define MMC_CR_ADJOP_SHIFT (2U) -#define MMC_CR_ADJOP_SET(x) (((uint32_t)(x) << MMC_CR_ADJOP_SHIFT) & MMC_CR_ADJOP_MASK) -#define MMC_CR_ADJOP_GET(x) (((uint32_t)(x) & MMC_CR_ADJOP_MASK) >> MMC_CR_ADJOP_SHIFT) - -/* - * DISCRETETRC (RW) - * - * 1: Discrete position input - * 0: Continuous position input - */ -#define MMC_CR_DISCRETETRC_MASK (0x2U) -#define MMC_CR_DISCRETETRC_SHIFT (1U) -#define MMC_CR_DISCRETETRC_SET(x) (((uint32_t)(x) << MMC_CR_DISCRETETRC_SHIFT) & MMC_CR_DISCRETETRC_MASK) -#define MMC_CR_DISCRETETRC_GET(x) (((uint32_t)(x) & MMC_CR_DISCRETETRC_MASK) >> MMC_CR_DISCRETETRC_SHIFT) - -/* - * MOD_EN (RW) - * - * Module Enable - */ -#define MMC_CR_MOD_EN_MASK (0x1U) -#define MMC_CR_MOD_EN_SHIFT (0U) -#define MMC_CR_MOD_EN_SET(x) (((uint32_t)(x) << MMC_CR_MOD_EN_SHIFT) & MMC_CR_MOD_EN_MASK) -#define MMC_CR_MOD_EN_GET(x) (((uint32_t)(x) & MMC_CR_MOD_EN_MASK) >> MMC_CR_MOD_EN_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * ERR_ID (RO) - * - * Tracking ERR_ID - */ -#define MMC_STA_ERR_ID_MASK (0xF0000000UL) -#define MMC_STA_ERR_ID_SHIFT (28U) -#define MMC_STA_ERR_ID_GET(x) (((uint32_t)(x) & MMC_STA_ERR_ID_MASK) >> MMC_STA_ERR_ID_SHIFT) - -/* - * SPEED_TRG_VALID (W1C) - * - * W1C - */ -#define MMC_STA_SPEED_TRG_VALID_MASK (0x400U) -#define MMC_STA_SPEED_TRG_VALID_SHIFT (10U) -#define MMC_STA_SPEED_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_SPEED_TRG_VALID_SHIFT) & MMC_STA_SPEED_TRG_VALID_MASK) -#define MMC_STA_SPEED_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_SPEED_TRG_VALID_MASK) >> MMC_STA_SPEED_TRG_VALID_SHIFT) - -/* - * POS_TRG_VALID (W1C) - * - * W1C - */ -#define MMC_STA_POS_TRG_VALID_MASK (0x200U) -#define MMC_STA_POS_TRG_VALID_SHIFT (9U) -#define MMC_STA_POS_TRG_VALID_SET(x) (((uint32_t)(x) << MMC_STA_POS_TRG_VALID_SHIFT) & MMC_STA_POS_TRG_VALID_MASK) -#define MMC_STA_POS_TRG_VALID_GET(x) (((uint32_t)(x) & MMC_STA_POS_TRG_VALID_MASK) >> MMC_STA_POS_TRG_VALID_SHIFT) - -/* - * INI_DELTA_POS_REQ_CMD_DONE (W1C) - * - * W1C - */ -#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK (0x100U) -#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT (8U) -#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) -#define MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_DELTA_POS_REQ_CMD_DONE_SHIFT) - -/* - * INI_BR0_POS_REQ_CMD_DONE (W1C) - * - * W1C - */ -#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK (0x80U) -#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT (7U) -#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) -#define MMC_STA_INI_BR0_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR0_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR0_POS_REQ_CMD_DONE_SHIFT) - -/* - * INI_BR1_POS_REQ_CMD_DONE (W1C) - * - * W1C - */ -#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK (0x40U) -#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT (6U) -#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) -#define MMC_STA_INI_BR1_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_BR1_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_BR1_POS_REQ_CMD_DONE_SHIFT) - -/* - * IDLE (RO) - * - * Tracking Module in Idle status - */ -#define MMC_STA_IDLE_MASK (0x20U) -#define MMC_STA_IDLE_SHIFT (5U) -#define MMC_STA_IDLE_GET(x) (((uint32_t)(x) & MMC_STA_IDLE_MASK) >> MMC_STA_IDLE_SHIFT) - -/* - * OOSYNC (W1C) - * - * Tracking module out-of sync. W1C - */ -#define MMC_STA_OOSYNC_MASK (0x10U) -#define MMC_STA_OOSYNC_SHIFT (4U) -#define MMC_STA_OOSYNC_SET(x) (((uint32_t)(x) << MMC_STA_OOSYNC_SHIFT) & MMC_STA_OOSYNC_MASK) -#define MMC_STA_OOSYNC_GET(x) (((uint32_t)(x) & MMC_STA_OOSYNC_MASK) >> MMC_STA_OOSYNC_SHIFT) - -/* - * INI_POS_REQ_CMD_DONE (W1C) - * - * W1C - */ -#define MMC_STA_INI_POS_REQ_CMD_DONE_MASK (0x4U) -#define MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT (2U) -#define MMC_STA_INI_POS_REQ_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) -#define MMC_STA_INI_POS_REQ_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_POS_REQ_CMD_DONE_MASK) >> MMC_STA_INI_POS_REQ_CMD_DONE_SHIFT) - -/* - * INI_COEFS_CMD_DONE (W1C) - * - * W1C - */ -#define MMC_STA_INI_COEFS_CMD_DONE_MASK (0x2U) -#define MMC_STA_INI_COEFS_CMD_DONE_SHIFT (1U) -#define MMC_STA_INI_COEFS_CMD_DONE_SET(x) (((uint32_t)(x) << MMC_STA_INI_COEFS_CMD_DONE_SHIFT) & MMC_STA_INI_COEFS_CMD_DONE_MASK) -#define MMC_STA_INI_COEFS_CMD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_INI_COEFS_CMD_DONE_MASK) >> MMC_STA_INI_COEFS_CMD_DONE_SHIFT) - -/* - * SHADOW_RD_DONE (RO) - * - * Shadow ready for read. Auto cleared by setting CR[SHADOW_RD_REQ] as 1 - */ -#define MMC_STA_SHADOW_RD_DONE_MASK (0x1U) -#define MMC_STA_SHADOW_RD_DONE_SHIFT (0U) -#define MMC_STA_SHADOW_RD_DONE_GET(x) (((uint32_t)(x) & MMC_STA_SHADOW_RD_DONE_MASK) >> MMC_STA_SHADOW_RD_DONE_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * SPEED_TRG_VLD_IE (RW) - * - * Interrupt Enable for SPEED_TRG_VALID - */ -#define MMC_INT_EN_SPEED_TRG_VLD_IE_MASK (0x400U) -#define MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT (10U) -#define MMC_INT_EN_SPEED_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) -#define MMC_INT_EN_SPEED_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SPEED_TRG_VLD_IE_MASK) >> MMC_INT_EN_SPEED_TRG_VLD_IE_SHIFT) - -/* - * POS_TRG_VLD_IE (RW) - * - * Interrupt Enable for POS_TRG_VALID - */ -#define MMC_INT_EN_POS_TRG_VLD_IE_MASK (0x200U) -#define MMC_INT_EN_POS_TRG_VLD_IE_SHIFT (9U) -#define MMC_INT_EN_POS_TRG_VLD_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) -#define MMC_INT_EN_POS_TRG_VLD_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_POS_TRG_VLD_IE_MASK) >> MMC_INT_EN_POS_TRG_VLD_IE_SHIFT) - -/* - * INI_DELTA_POS_REQ_CMD_DONE_IE (RW) - * - * Interrupt Enable for INI_DELTA_POS_REQ_CMD_DONE - */ -#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK (0x100U) -#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT (8U) -#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) -#define MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_DELTA_POS_REQ_CMD_DONE_IE_SHIFT) - -/* - * INI_BR0_POS_REQ_CMD_DONE_IE (RW) - * - * Interrupt Enable for INI_BR0_POS_REQ_CMD_DONE - */ -#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK (0x80U) -#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT (7U) -#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) -#define MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR0_POS_REQ_CMD_DONE_IE_SHIFT) - -/* - * INI_BR1_POS_REQ_CMD_DONE_IE (RW) - * - * Interrupt Enable for INI_BR1_POS_REQ_CMD_DONE - */ -#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK (0x40U) -#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT (6U) -#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) -#define MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_BR1_POS_REQ_CMD_DONE_IE_SHIFT) - -/* - * OOSYNC_IE (RW) - * - * Interrupt Enable for OOSYNC - */ -#define MMC_INT_EN_OOSYNC_IE_MASK (0x10U) -#define MMC_INT_EN_OOSYNC_IE_SHIFT (4U) -#define MMC_INT_EN_OOSYNC_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_OOSYNC_IE_SHIFT) & MMC_INT_EN_OOSYNC_IE_MASK) -#define MMC_INT_EN_OOSYNC_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_OOSYNC_IE_MASK) >> MMC_INT_EN_OOSYNC_IE_SHIFT) - -/* - * INI_POS_REQ_CMD_DONE_IE (RW) - * - * Interrupt Enable for INI_POS_REQ_CMD_DONE - */ -#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK (0x4U) -#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT (2U) -#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) -#define MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_POS_REQ_CMD_DONE_IE_SHIFT) - -/* - * INI_COEFS_CMD_DONE_IE (RW) - * - * Interrupt Enable for INI_COEFS_CMD_DONE - */ -#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK (0x2U) -#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT (1U) -#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) -#define MMC_INT_EN_INI_COEFS_CMD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_INI_COEFS_CMD_DONE_IE_MASK) >> MMC_INT_EN_INI_COEFS_CMD_DONE_IE_SHIFT) - -/* - * SHADOW_RD_DONE_IE (RW) - * - * Interrupt Enable for SHADOW_RD_DONE - */ -#define MMC_INT_EN_SHADOW_RD_DONE_IE_MASK (0x1U) -#define MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT (0U) -#define MMC_INT_EN_SHADOW_RD_DONE_IE_SET(x) (((uint32_t)(x) << MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) -#define MMC_INT_EN_SHADOW_RD_DONE_IE_GET(x) (((uint32_t)(x) & MMC_INT_EN_SHADOW_RD_DONE_IE_MASK) >> MMC_INT_EN_SHADOW_RD_DONE_IE_SHIFT) - -/* Bitfield definition for register: SYSCLK_FREQ */ -/* - * VAL (RW) - * - * system clock frequency, ufix<32, 0> - */ -#define MMC_SYSCLK_FREQ_VAL_MASK (0xFFFFFFFFUL) -#define MMC_SYSCLK_FREQ_VAL_SHIFT (0U) -#define MMC_SYSCLK_FREQ_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_FREQ_VAL_SHIFT) & MMC_SYSCLK_FREQ_VAL_MASK) -#define MMC_SYSCLK_FREQ_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_FREQ_VAL_MASK) >> MMC_SYSCLK_FREQ_VAL_SHIFT) - -/* Bitfield definition for register: SYSCLK_PERIOD */ -/* - * VAL (RW) - * - * round( the value of clock period * (2^24)*(2^20) ), ufix<32, 0> - */ -#define MMC_SYSCLK_PERIOD_VAL_MASK (0xFFFFFFFFUL) -#define MMC_SYSCLK_PERIOD_VAL_SHIFT (0U) -#define MMC_SYSCLK_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_SYSCLK_PERIOD_VAL_SHIFT) & MMC_SYSCLK_PERIOD_VAL_MASK) -#define MMC_SYSCLK_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_SYSCLK_PERIOD_VAL_MASK) >> MMC_SYSCLK_PERIOD_VAL_SHIFT) - -/* Bitfield definition for register: OOSYNC_THETA_THR */ -/* - * VAL (RW) - * - * the threshold of theta difference between actual and prediction for out-of-sync determination，ufix<32, 32> - */ -#define MMC_OOSYNC_THETA_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_OOSYNC_THETA_THR_VAL_SHIFT (0U) -#define MMC_OOSYNC_THETA_THR_VAL_SET(x) (((uint32_t)(x) << MMC_OOSYNC_THETA_THR_VAL_SHIFT) & MMC_OOSYNC_THETA_THR_VAL_MASK) -#define MMC_OOSYNC_THETA_THR_VAL_GET(x) (((uint32_t)(x) & MMC_OOSYNC_THETA_THR_VAL_MASK) >> MMC_OOSYNC_THETA_THR_VAL_SHIFT) - -/* Bitfield definition for register: DISCRETECFG0 */ -/* - * POSMAX (RW) - * - * Max ID Of Lines. For example-1, for 512 lines, it is 511. ufix<32, 0> - */ -#define MMC_DISCRETECFG0_POSMAX_MASK (0xFFFFFUL) -#define MMC_DISCRETECFG0_POSMAX_SHIFT (0U) -#define MMC_DISCRETECFG0_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG0_POSMAX_SHIFT) & MMC_DISCRETECFG0_POSMAX_MASK) -#define MMC_DISCRETECFG0_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG0_POSMAX_MASK) >> MMC_DISCRETECFG0_POSMAX_SHIFT) - -/* Bitfield definition for register: DISCRETECFG1 */ -/* - * INV_POSMAX (RW) - * - * discrete mode: ufix<32, 0> of 1/(Number Of Lines) - * continuous mode: the max delta for tracking from the last received position, ufix<32, 32> - */ -#define MMC_DISCRETECFG1_INV_POSMAX_MASK (0xFFFFFFFFUL) -#define MMC_DISCRETECFG1_INV_POSMAX_SHIFT (0U) -#define MMC_DISCRETECFG1_INV_POSMAX_SET(x) (((uint32_t)(x) << MMC_DISCRETECFG1_INV_POSMAX_SHIFT) & MMC_DISCRETECFG1_INV_POSMAX_MASK) -#define MMC_DISCRETECFG1_INV_POSMAX_GET(x) (((uint32_t)(x) & MMC_DISCRETECFG1_INV_POSMAX_MASK) >> MMC_DISCRETECFG1_INV_POSMAX_SHIFT) - -/* Bitfield definition for register: CONTCFG0 */ -/* - * HALF_CIRC_THETA (RW) - * - * the theta for cal the clockwise or anticlockwise rotation between two adjacent inputs, ufix<32, 32> - */ -#define MMC_CONTCFG0_HALF_CIRC_THETA_MASK (0xFFFFFFFFUL) -#define MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT (0U) -#define MMC_CONTCFG0_HALF_CIRC_THETA_SET(x) (((uint32_t)(x) << MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) -#define MMC_CONTCFG0_HALF_CIRC_THETA_GET(x) (((uint32_t)(x) & MMC_CONTCFG0_HALF_CIRC_THETA_MASK) >> MMC_CONTCFG0_HALF_CIRC_THETA_SHIFT) - -/* Bitfield definition for register: INI_POS_TIME */ -/* - * VAL (RW) - * - * indicate the time to change the values. - * 0: instant change - */ -#define MMC_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_POS_TIME_VAL_SHIFT (0U) -#define MMC_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_TIME_VAL_SHIFT) & MMC_INI_POS_TIME_VAL_MASK) -#define MMC_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_TIME_VAL_MASK) >> MMC_INI_POS_TIME_VAL_SHIFT) - -/* Bitfield definition for register: INI_POS */ -/* - * VAL (RW) - * - * the value； - * continuous mode: ufix<32, 32> - */ -#define MMC_INI_POS_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_POS_VAL_SHIFT (0U) -#define MMC_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_POS_VAL_SHIFT) & MMC_INI_POS_VAL_MASK) -#define MMC_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_POS_VAL_MASK) >> MMC_INI_POS_VAL_SHIFT) - -/* Bitfield definition for register: INI_REV */ -/* - * VAL (RW) - * - * the value； - * continuous mode: ufix<32, 0> - */ -#define MMC_INI_REV_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_REV_VAL_SHIFT (0U) -#define MMC_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_REV_VAL_SHIFT) & MMC_INI_REV_VAL_MASK) -#define MMC_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_REV_VAL_MASK) >> MMC_INI_REV_VAL_SHIFT) - -/* Bitfield definition for register: INI_SPEED */ -/* - * VAL (RW) - * - * the value; - * continuous mode: fix<32, 19> - */ -#define MMC_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_SPEED_VAL_SHIFT (0U) -#define MMC_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_SPEED_VAL_SHIFT) & MMC_INI_SPEED_VAL_MASK) -#define MMC_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_SPEED_VAL_MASK) >> MMC_INI_SPEED_VAL_SHIFT) - -/* Bitfield definition for register: INI_ACCEL */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 19> - */ -#define MMC_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_ACCEL_VAL_SHIFT (0U) -#define MMC_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACCEL_VAL_SHIFT) & MMC_INI_ACCEL_VAL_MASK) -#define MMC_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACCEL_VAL_MASK) >> MMC_INI_ACCEL_VAL_SHIFT) - -/* Bitfield definition for register: INI_COEF_TIME */ -/* - * VAL (RW) - * - * indicate the time to change the values. - * 0: instant change - */ -#define MMC_INI_COEF_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_COEF_TIME_VAL_SHIFT (0U) -#define MMC_INI_COEF_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_COEF_TIME_VAL_SHIFT) & MMC_INI_COEF_TIME_VAL_MASK) -#define MMC_INI_COEF_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_COEF_TIME_VAL_MASK) >> MMC_INI_COEF_TIME_VAL_SHIFT) - -/* Bitfield definition for register: INI_PCOEF */ -/* - * VAL (RW) - * - * the value, fix<32, 15> - */ -#define MMC_INI_PCOEF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_PCOEF_VAL_SHIFT (0U) -#define MMC_INI_PCOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_PCOEF_VAL_SHIFT) & MMC_INI_PCOEF_VAL_MASK) -#define MMC_INI_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_PCOEF_VAL_MASK) >> MMC_INI_PCOEF_VAL_SHIFT) - -/* Bitfield definition for register: INI_ICOEF */ -/* - * VAL (RW) - * - * the value, fix<32, 21> - */ -#define MMC_INI_ICOEF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_ICOEF_VAL_SHIFT (0U) -#define MMC_INI_ICOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ICOEF_VAL_SHIFT) & MMC_INI_ICOEF_VAL_MASK) -#define MMC_INI_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ICOEF_VAL_MASK) >> MMC_INI_ICOEF_VAL_SHIFT) - -/* Bitfield definition for register: INI_ACOEF */ -/* - * VAL (RW) - * - * the value, fix<32, 19> - */ -#define MMC_INI_ACOEF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_ACOEF_VAL_SHIFT (0U) -#define MMC_INI_ACOEF_VAL_SET(x) (((uint32_t)(x) << MMC_INI_ACOEF_VAL_SHIFT) & MMC_INI_ACOEF_VAL_MASK) -#define MMC_INI_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_INI_ACOEF_VAL_MASK) >> MMC_INI_ACOEF_VAL_SHIFT) - -/* Bitfield definition for register: ESTM_TIM */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_ESTM_TIM_VAL_MASK (0xFFFFFFFFUL) -#define MMC_ESTM_TIM_VAL_SHIFT (0U) -#define MMC_ESTM_TIM_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_TIM_VAL_MASK) >> MMC_ESTM_TIM_VAL_SHIFT) - -/* Bitfield definition for register: ESTM_POS */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_ESTM_POS_VAL_MASK (0xFFFFFFFFUL) -#define MMC_ESTM_POS_VAL_SHIFT (0U) -#define MMC_ESTM_POS_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_POS_VAL_MASK) >> MMC_ESTM_POS_VAL_SHIFT) - -/* Bitfield definition for register: ESTM_REV */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_ESTM_REV_VAL_MASK (0xFFFFFFFFUL) -#define MMC_ESTM_REV_VAL_SHIFT (0U) -#define MMC_ESTM_REV_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_REV_VAL_MASK) >> MMC_ESTM_REV_VAL_SHIFT) - -/* Bitfield definition for register: ESTM_SPEED */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_ESTM_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_ESTM_SPEED_VAL_SHIFT (0U) -#define MMC_ESTM_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_SPEED_VAL_MASK) >> MMC_ESTM_SPEED_VAL_SHIFT) - -/* Bitfield definition for register: ESTM_ACCEL */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_ESTM_ACCEL_VAL_MASK (0xFFFFFFFFUL) -#define MMC_ESTM_ACCEL_VAL_SHIFT (0U) -#define MMC_ESTM_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_ESTM_ACCEL_VAL_MASK) >> MMC_ESTM_ACCEL_VAL_SHIFT) - -/* Bitfield definition for register: CUR_PCOEF */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_CUR_PCOEF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_CUR_PCOEF_VAL_SHIFT (0U) -#define MMC_CUR_PCOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_PCOEF_VAL_MASK) >> MMC_CUR_PCOEF_VAL_SHIFT) - -/* Bitfield definition for register: CUR_ICOEF */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_CUR_ICOEF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_CUR_ICOEF_VAL_SHIFT (0U) -#define MMC_CUR_ICOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ICOEF_VAL_MASK) >> MMC_CUR_ICOEF_VAL_SHIFT) - -/* Bitfield definition for register: CUR_ACOEF */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_CUR_ACOEF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_CUR_ACOEF_VAL_SHIFT (0U) -#define MMC_CUR_ACOEF_VAL_GET(x) (((uint32_t)(x) & MMC_CUR_ACOEF_VAL_MASK) >> MMC_CUR_ACOEF_VAL_SHIFT) - -/* Bitfield definition for register: INI_DELTA_POS_TIME */ -/* - * VAL (RW) - * - * indicate the time to change the values. - * 0: instant change - */ -#define MMC_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_DELTA_POS_TIME_VAL_SHIFT (0U) -#define MMC_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_INI_DELTA_POS_TIME_VAL_MASK) -#define MMC_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_INI_DELTA_POS_TIME_VAL_SHIFT) - -/* Bitfield definition for register: INI_DELTA_POS */ -/* - * VAL (RW) - * - * the value - * continuous mode: ufix <32, 32> - */ -#define MMC_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_DELTA_POS_VAL_SHIFT (0U) -#define MMC_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_POS_VAL_SHIFT) & MMC_INI_DELTA_POS_VAL_MASK) -#define MMC_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_POS_VAL_MASK) >> MMC_INI_DELTA_POS_VAL_SHIFT) - -/* Bitfield definition for register: INI_DELTA_REV */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 0> - */ -#define MMC_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_DELTA_REV_VAL_SHIFT (0U) -#define MMC_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_REV_VAL_SHIFT) & MMC_INI_DELTA_REV_VAL_MASK) -#define MMC_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_REV_VAL_MASK) >> MMC_INI_DELTA_REV_VAL_SHIFT) - -/* Bitfield definition for register: INI_DELTA_SPEED */ -/* - * VAL (RW) - * - * the value； - * continuous mode: fix<32, 19> - */ -#define MMC_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_DELTA_SPEED_VAL_SHIFT (0U) -#define MMC_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_SPEED_VAL_SHIFT) & MMC_INI_DELTA_SPEED_VAL_MASK) -#define MMC_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_SPEED_VAL_MASK) >> MMC_INI_DELTA_SPEED_VAL_SHIFT) - -/* Bitfield definition for register: INI_DELTA_ACCEL */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 19> - */ -#define MMC_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) -#define MMC_INI_DELTA_ACCEL_VAL_SHIFT (0U) -#define MMC_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_INI_DELTA_ACCEL_VAL_MASK) -#define MMC_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_INI_DELTA_ACCEL_VAL_MASK) >> MMC_INI_DELTA_ACCEL_VAL_SHIFT) - -/* Bitfield definition for register: POS_TRG_CFG */ -/* - * EDGE (RW) - * - * 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than - */ -#define MMC_POS_TRG_CFG_EDGE_MASK (0x2U) -#define MMC_POS_TRG_CFG_EDGE_SHIFT (1U) -#define MMC_POS_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EDGE_SHIFT) & MMC_POS_TRG_CFG_EDGE_MASK) -#define MMC_POS_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EDGE_MASK) >> MMC_POS_TRG_CFG_EDGE_SHIFT) - -/* - * EN (RW) - * - * 1-trigger valid; 0-Trigger not valid" - */ -#define MMC_POS_TRG_CFG_EN_MASK (0x1U) -#define MMC_POS_TRG_CFG_EN_SHIFT (0U) -#define MMC_POS_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_POS_TRG_CFG_EN_SHIFT) & MMC_POS_TRG_CFG_EN_MASK) -#define MMC_POS_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_POS_TRG_CFG_EN_MASK) >> MMC_POS_TRG_CFG_EN_SHIFT) - -/* Bitfield definition for register: POS_TRG_POS_THR */ -/* - * VAL (RW) - * - * For pos out trigger (pos). - * ufix<32, 32> - */ -#define MMC_POS_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_POS_TRG_POS_THR_VAL_SHIFT (0U) -#define MMC_POS_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_POS_THR_VAL_SHIFT) & MMC_POS_TRG_POS_THR_VAL_MASK) -#define MMC_POS_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_POS_THR_VAL_MASK) >> MMC_POS_TRG_POS_THR_VAL_SHIFT) - -/* Bitfield definition for register: POS_TRG_REV_THR */ -/* - * VAL (RW) - * - * For pos out trigger (rev) - * fix<32, 0> - */ -#define MMC_POS_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_POS_TRG_REV_THR_VAL_SHIFT (0U) -#define MMC_POS_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_POS_TRG_REV_THR_VAL_SHIFT) & MMC_POS_TRG_REV_THR_VAL_MASK) -#define MMC_POS_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_POS_TRG_REV_THR_VAL_MASK) >> MMC_POS_TRG_REV_THR_VAL_SHIFT) - -/* Bitfield definition for register: SPEED_TRG_CFG */ -/* - * COMP_TYPE (RW) - * - * 1: Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) - */ -#define MMC_SPEED_TRG_CFG_COMP_TYPE_MASK (0x4U) -#define MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT (2U) -#define MMC_SPEED_TRG_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) -#define MMC_SPEED_TRG_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_COMP_TYPE_MASK) >> MMC_SPEED_TRG_CFG_COMP_TYPE_SHIFT) - -/* - * EDGE (RW) - * - * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than - */ -#define MMC_SPEED_TRG_CFG_EDGE_MASK (0x2U) -#define MMC_SPEED_TRG_CFG_EDGE_SHIFT (1U) -#define MMC_SPEED_TRG_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EDGE_SHIFT) & MMC_SPEED_TRG_CFG_EDGE_MASK) -#define MMC_SPEED_TRG_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EDGE_MASK) >> MMC_SPEED_TRG_CFG_EDGE_SHIFT) - -/* - * EN (RW) - * - * 1-trigger valid; 0-Trigger not valid - * Normally it means either the max pos speed, or the min negative speed. - */ -#define MMC_SPEED_TRG_CFG_EN_MASK (0x1U) -#define MMC_SPEED_TRG_CFG_EN_SHIFT (0U) -#define MMC_SPEED_TRG_CFG_EN_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_CFG_EN_SHIFT) & MMC_SPEED_TRG_CFG_EN_MASK) -#define MMC_SPEED_TRG_CFG_EN_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_CFG_EN_MASK) >> MMC_SPEED_TRG_CFG_EN_SHIFT) - -/* Bitfield definition for register: SPEED_TRG_THR */ -/* - * VAL (RW) - * - * For speed trigger. - * continuous mode: fix<32, 19> - */ -#define MMC_SPEED_TRG_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_SPEED_TRG_THR_VAL_SHIFT (0U) -#define MMC_SPEED_TRG_THR_VAL_SET(x) (((uint32_t)(x) << MMC_SPEED_TRG_THR_VAL_SHIFT) & MMC_SPEED_TRG_THR_VAL_MASK) -#define MMC_SPEED_TRG_THR_VAL_GET(x) (((uint32_t)(x) & MMC_SPEED_TRG_THR_VAL_MASK) >> MMC_SPEED_TRG_THR_VAL_SHIFT) - -/* Bitfield definition for register of struct array COEF_TRG_CFG: ERR_THR */ -/* - * VAL (RW) - * - * ErrThr0: Error Threshold 0, (abs(tracking error)>= will choose the coefs as below) - * Note: ErrThr0>ErrThr1>ErrThr2 - * ufix<31, 28> - */ -#define MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT (0U) -#define MMC_COEF_TRG_CFG_ERR_THR_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) -#define MMC_COEF_TRG_CFG_ERR_THR_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_ERR_THR_VAL_MASK) >> MMC_COEF_TRG_CFG_ERR_THR_VAL_SHIFT) - -/* Bitfield definition for register of struct array COEF_TRG_CFG: P */ -/* - * VAL (RW) - * - * P0_Coef, fix<32, 15> - */ -#define MMC_COEF_TRG_CFG_P_VAL_MASK (0xFFFFFFFFUL) -#define MMC_COEF_TRG_CFG_P_VAL_SHIFT (0U) -#define MMC_COEF_TRG_CFG_P_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_P_VAL_SHIFT) & MMC_COEF_TRG_CFG_P_VAL_MASK) -#define MMC_COEF_TRG_CFG_P_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_P_VAL_MASK) >> MMC_COEF_TRG_CFG_P_VAL_SHIFT) - -/* Bitfield definition for register of struct array COEF_TRG_CFG: I */ -/* - * VAL (RW) - * - * I0_Coef, fix<32, 21> - */ -#define MMC_COEF_TRG_CFG_I_VAL_MASK (0xFFFFFFFFUL) -#define MMC_COEF_TRG_CFG_I_VAL_SHIFT (0U) -#define MMC_COEF_TRG_CFG_I_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_I_VAL_SHIFT) & MMC_COEF_TRG_CFG_I_VAL_MASK) -#define MMC_COEF_TRG_CFG_I_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_I_VAL_MASK) >> MMC_COEF_TRG_CFG_I_VAL_SHIFT) - -/* Bitfield definition for register of struct array COEF_TRG_CFG: A */ -/* - * VAL (RW) - * - * A0_Coef，fix<32, 19> - */ -#define MMC_COEF_TRG_CFG_A_VAL_MASK (0xFFFFFFFFUL) -#define MMC_COEF_TRG_CFG_A_VAL_SHIFT (0U) -#define MMC_COEF_TRG_CFG_A_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_A_VAL_SHIFT) & MMC_COEF_TRG_CFG_A_VAL_MASK) -#define MMC_COEF_TRG_CFG_A_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_A_VAL_MASK) >> MMC_COEF_TRG_CFG_A_VAL_SHIFT) - -/* Bitfield definition for register of struct array COEF_TRG_CFG: TIME */ -/* - * VAL (RW) - * - * CoefTime0: Time Stayed using this coefs (counted in input samples). Ideal value of tracing cycles should +1. ufix<32,0> - */ -#define MMC_COEF_TRG_CFG_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_COEF_TRG_CFG_TIME_VAL_SHIFT (0U) -#define MMC_COEF_TRG_CFG_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) -#define MMC_COEF_TRG_CFG_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_COEF_TRG_CFG_TIME_VAL_MASK) >> MMC_COEF_TRG_CFG_TIME_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_CTRL */ -/* - * SPEED_TRG_VALID_IE (RW) - * - * Interrupt Enable for SPEED_TRG_VALID - */ -#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK (0x40000000UL) -#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT (30U) -#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) -#define MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_SHIFT) - -/* - * POS_TRG_VALID_IE (RW) - * - * Interrupt Enable for POS_TRG_VALID - */ -#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK (0x20000000UL) -#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT (29U) -#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) -#define MMC_BR_BR_CTRL_POS_TRG_VALID_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK) >> MMC_BR_BR_CTRL_POS_TRG_VALID_IE_SHIFT) - -/* - * INI_POS_TRG_TYPE (RW) - * - * 0: Time Stamp in the configuration - * 1: Risedge of In Trg[0] - * 2: Risedge of In Trg[1] - * 3: Risedge of out trg[0] - * 4: Risedge of out trg[1] - * 5: Risedge of self pos trigger - * 6: Risedge of self speed trigger - * Others: no function - */ -#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK (0x3800000UL) -#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT (23U) -#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) -#define MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_POS_TRG_TYPE_SHIFT) - -/* - * INI_POS_CMD_MSK (RW) - * - * 1: change - * 0: won't change - * bit 3: for accel - * bit 2: for speed - * bit 1: for revolution - * bit 0: for position - */ -#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK (0x3C0000UL) -#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT (18U) -#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) -#define MMC_BR_BR_CTRL_INI_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_POS_CMD_MSK_SHIFT) - -/* - * INI_DELTA_POS_TRG_TYPE (RW) - * - * 0: Time Stamp in the configuration - * 1: Risedge of In Trg[0] - * 2: Risedge of In Trg[1] - * 3: Risedge of out trg[0] - * 4: Risedge of out trg[1] - * 5: Risedge of self pos trigger - * 6: Risedge of self speed trigger - * Others: no function - */ -#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK (0x1C000UL) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT (14U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_TRG_TYPE_SHIFT) - -/* - * INI_DELTA_POS_DONE_IE (RW) - * - * Interrupt Enable for INI_DELTA_POS_DONE - */ -#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK (0x2000U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT (13U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_SHIFT) - -/* - * INI_DELTA_POS_CMD_MSK (RW) - * - * 1: change - * 0: won't change - * bit 3: for delta accel - * bit 2: for delta speed - * bit 1: for delta revolution - * bit 0: for delta position - */ -#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK (0x1E00U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT (9U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_CMD_MSK_SHIFT) - -/* - * INI_DELTA_POS_REQ (RW) - * - * 1: Command to reload the delta pos. Auto clear - * 0: - */ -#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK (0x100U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT (8U) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) -#define MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_MASK) >> MMC_BR_BR_CTRL_INI_DELTA_POS_REQ_SHIFT) - -/* - * OPEN_LOOP_MODE (RW) - * - * 1: in open loop mode - * 0: not in open loop mode - */ -#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK (0x80U) -#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT (7U) -#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) -#define MMC_BR_BR_CTRL_OPEN_LOOP_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK) >> MMC_BR_BR_CTRL_OPEN_LOOP_MODE_SHIFT) - -/* - * PRED_MODE (RW) - * - * 1:continuously repeat pred, - * 0:cal the pred based on a definite time-stamp offset, - * 2:programed one-shot prediction mode - */ -#define MMC_BR_BR_CTRL_PRED_MODE_MASK (0x30U) -#define MMC_BR_BR_CTRL_PRED_MODE_SHIFT (4U) -#define MMC_BR_BR_CTRL_PRED_MODE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_PRED_MODE_SHIFT) & MMC_BR_BR_CTRL_PRED_MODE_MASK) -#define MMC_BR_BR_CTRL_PRED_MODE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_PRED_MODE_MASK) >> MMC_BR_BR_CTRL_PRED_MODE_SHIFT) - -/* - * NF_TRG_TYPE (RW) - * - * 1. Each non-first trigger by external trigger pin - * 0. Each non-first trigger by the timer - */ -#define MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK (0x4U) -#define MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT (2U) -#define MMC_BR_BR_CTRL_NF_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) -#define MMC_BR_BR_CTRL_NF_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_NF_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_NF_TRG_TYPE_SHIFT) - -/* - * F_TRG_TYPE (RW) - * - * 1. First trigger by external trigger pin - * 0. First trigger by the timer - * When in CR[MANUAL_IO]=1 mode, it is the prediction trigger - */ -#define MMC_BR_BR_CTRL_F_TRG_TYPE_MASK (0x2U) -#define MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT (1U) -#define MMC_BR_BR_CTRL_F_TRG_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) -#define MMC_BR_BR_CTRL_F_TRG_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_F_TRG_TYPE_MASK) >> MMC_BR_BR_CTRL_F_TRG_TYPE_SHIFT) - -/* - * BR_EN (RW) - * - * Branch Enable - */ -#define MMC_BR_BR_CTRL_BR_EN_MASK (0x1U) -#define MMC_BR_BR_CTRL_BR_EN_SHIFT (0U) -#define MMC_BR_BR_CTRL_BR_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_CTRL_BR_EN_SHIFT) & MMC_BR_BR_CTRL_BR_EN_MASK) -#define MMC_BR_BR_CTRL_BR_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_CTRL_BR_EN_MASK) >> MMC_BR_BR_CTRL_BR_EN_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TIMEOFF */ -/* - * VAL (RW) - * - * ufix<32, 0> time offset incycles from the trigger time - */ -#define MMC_BR_BR_TIMEOFF_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_TIMEOFF_VAL_SHIFT (0U) -#define MMC_BR_BR_TIMEOFF_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TIMEOFF_VAL_SHIFT) & MMC_BR_BR_TIMEOFF_VAL_MASK) -#define MMC_BR_BR_TIMEOFF_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TIMEOFF_VAL_MASK) >> MMC_BR_BR_TIMEOFF_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_PERIOD */ -/* - * VAL (RW) - * - * uifx<32, 0>, time offset incycles between each trigger time - */ -#define MMC_BR_BR_TRG_PERIOD_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_TRG_PERIOD_VAL_SHIFT (0U) -#define MMC_BR_BR_TRG_PERIOD_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) -#define MMC_BR_BR_TRG_PERIOD_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_PERIOD_VAL_MASK) >> MMC_BR_BR_TRG_PERIOD_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_F_TIME */ -/* - * VAL (RW) - * - * uifx<32, 0> the time for the first trigger - */ -#define MMC_BR_BR_TRG_F_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_TRG_F_TIME_VAL_SHIFT (0U) -#define MMC_BR_BR_TRG_F_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) -#define MMC_BR_BR_TRG_F_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_F_TIME_VAL_MASK) >> MMC_BR_BR_TRG_F_TIME_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_ST */ -/* - * OPEN_LOOP_ST (RO) - * - * 1：in open loop mode - * 0：in closed loop mode - */ -#define MMC_BR_BR_ST_OPEN_LOOP_ST_MASK (0x400U) -#define MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT (10U) -#define MMC_BR_BR_ST_OPEN_LOOP_ST_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_OPEN_LOOP_ST_MASK) >> MMC_BR_BR_ST_OPEN_LOOP_ST_SHIFT) - -/* - * SPEED_TRG_VLD (W1C) - * - * 1：self speed trigger event found - * 0：self speed trigger event not found yet - */ -#define MMC_BR_BR_ST_SPEED_TRG_VLD_MASK (0x200U) -#define MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT (9U) -#define MMC_BR_BR_ST_SPEED_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) -#define MMC_BR_BR_ST_SPEED_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_SPEED_TRG_VLD_MASK) >> MMC_BR_BR_ST_SPEED_TRG_VLD_SHIFT) - -/* - * POS_TRG_VLD (W1C) - * - * 1：self position trigger event found - * 0：self position trigger event not found yet - */ -#define MMC_BR_BR_ST_POS_TRG_VLD_MASK (0x100U) -#define MMC_BR_BR_ST_POS_TRG_VLD_SHIFT (8U) -#define MMC_BR_BR_ST_POS_TRG_VLD_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) -#define MMC_BR_BR_ST_POS_TRG_VLD_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_POS_TRG_VLD_MASK) >> MMC_BR_BR_ST_POS_TRG_VLD_SHIFT) - -/* - * INI_DELTA_POS_DONE (W1C) - * - * 1: the initialization of delta position command is done - * 0: the initialization of delta position command is not done - */ -#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK (0x40U) -#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT (6U) -#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_SET(x) (((uint32_t)(x) << MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) -#define MMC_BR_BR_ST_INI_DELTA_POS_DONE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK) >> MMC_BR_BR_ST_INI_DELTA_POS_DONE_SHIFT) - -/* - * IDLE (RO) - * - * 1: The prediction module is idle. - * 0: The prediction module is not idle. - */ -#define MMC_BR_BR_ST_IDLE_MASK (0x20U) -#define MMC_BR_BR_ST_IDLE_SHIFT (5U) -#define MMC_BR_BR_ST_IDLE_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_IDLE_MASK) >> MMC_BR_BR_ST_IDLE_SHIFT) - -/* - * ERR_ID (RO) - * - * The module's error ID output - */ -#define MMC_BR_BR_ST_ERR_ID_MASK (0xFU) -#define MMC_BR_BR_ST_ERR_ID_SHIFT (0U) -#define MMC_BR_BR_ST_ERR_ID_GET(x) (((uint32_t)(x) & MMC_BR_BR_ST_ERR_ID_MASK) >> MMC_BR_BR_ST_ERR_ID_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_POS_CFG */ -/* - * EDGE (RW) - * - * bit1: 0: (rising edge) pos inc greater than, 1: (falling edge) pos dec less than - */ -#define MMC_BR_BR_TRG_POS_CFG_EDGE_MASK (0x2U) -#define MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT (1U) -#define MMC_BR_BR_TRG_POS_CFG_EDGE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) -#define MMC_BR_BR_TRG_POS_CFG_EDGE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EDGE_MASK) >> MMC_BR_BR_TRG_POS_CFG_EDGE_SHIFT) - -/* - * EN (RW) - * - * 1-trigger valid; 0-Trigger not valid - */ -#define MMC_BR_BR_TRG_POS_CFG_EN_MASK (0x1U) -#define MMC_BR_BR_TRG_POS_CFG_EN_SHIFT (0U) -#define MMC_BR_BR_TRG_POS_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) -#define MMC_BR_BR_TRG_POS_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_CFG_EN_MASK) >> MMC_BR_BR_TRG_POS_CFG_EN_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_POS_THR */ -/* - * VAL (RW) - * - * For pos out trigger (pos). - * ufix<32, 32> - */ -#define MMC_BR_BR_TRG_POS_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_TRG_POS_THR_VAL_SHIFT (0U) -#define MMC_BR_BR_TRG_POS_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) -#define MMC_BR_BR_TRG_POS_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_POS_THR_VAL_MASK) >> MMC_BR_BR_TRG_POS_THR_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_REV_THR */ -/* - * VAL (RW) - * - * For pos out trigger (rev) - * ufix<32, 0> - */ -#define MMC_BR_BR_TRG_REV_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_TRG_REV_THR_VAL_SHIFT (0U) -#define MMC_BR_BR_TRG_REV_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) -#define MMC_BR_BR_TRG_REV_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_REV_THR_VAL_MASK) >> MMC_BR_BR_TRG_REV_THR_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_SPEED_CFG */ -/* - * COMP_TYPE (RW) - * - * Use abs value for comparion. 0: Use the speed with direction info (so not the abs value) - */ -#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK (0x4U) -#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT (2U) -#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) -#define MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_COMP_TYPE_SHIFT) - -/* - * EDGE_SEL (RW) - * - * 0: (rising edge) speed inc greater than, 1: (falling edge) speed dec less than - */ -#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK (0x2U) -#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT (1U) -#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) -#define MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EDGE_SEL_SHIFT) - -/* - * EN (RW) - * - * 1-trigger valid; 0-Trigger not valid - * Normally it means either the max pos speed, or the min negative speed. - */ -#define MMC_BR_BR_TRG_SPEED_CFG_EN_MASK (0x1U) -#define MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT (0U) -#define MMC_BR_BR_TRG_SPEED_CFG_EN_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) -#define MMC_BR_BR_TRG_SPEED_CFG_EN_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_CFG_EN_MASK) >> MMC_BR_BR_TRG_SPEED_CFG_EN_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_TRG_SPEED_THR */ -/* - * VAL (RW) - * - * For speed trigger. - * continuous mode: fix<32, 19> - */ -#define MMC_BR_BR_TRG_SPEED_THR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT (0U) -#define MMC_BR_BR_TRG_SPEED_THR_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) -#define MMC_BR_BR_TRG_SPEED_THR_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_TRG_SPEED_THR_VAL_MASK) >> MMC_BR_BR_TRG_SPEED_THR_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_POS_TIME */ -/* - * VAL (RW) - * - * indicate the time to change the values. - * 0: instant change - */ -#define MMC_BR_BR_INI_POS_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_POS_TIME_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) -#define MMC_BR_BR_INI_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_POS_TIME_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_POS */ -/* - * VAL (RW) - * - * the value - * ufix<32, 32> - */ -#define MMC_BR_BR_INI_POS_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_POS_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_POS_VAL_SHIFT) & MMC_BR_BR_INI_POS_VAL_MASK) -#define MMC_BR_BR_INI_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_POS_VAL_MASK) >> MMC_BR_BR_INI_POS_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_REV */ -/* - * VAL (RW) - * - * the value - * ufix<32, 0> - */ -#define MMC_BR_BR_INI_REV_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_REV_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_REV_VAL_SHIFT) & MMC_BR_BR_INI_REV_VAL_MASK) -#define MMC_BR_BR_INI_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_REV_VAL_MASK) >> MMC_BR_BR_INI_REV_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_SPEED */ -/* - * VAL (RW) - * - * the value - * fix<32, 19> - */ -#define MMC_BR_BR_INI_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_SPEED_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_SPEED_VAL_MASK) -#define MMC_BR_BR_INI_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_SPEED_VAL_MASK) >> MMC_BR_BR_INI_SPEED_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_ACCEL */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 19> - */ -#define MMC_BR_BR_INI_ACCEL_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_ACCEL_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_ACCEL_VAL_MASK) -#define MMC_BR_BR_INI_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_ACCEL_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS_TIME */ -/* - * VAL (RW) - * - * indicate the time to change the values. - * 0: instant change - */ -#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) -#define MMC_BR_BR_INI_DELTA_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_TIME_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_TIME_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_DELTA_POS */ -/* - * VAL (RW) - * - * the value - * continuous mode: ufix<32, 32> - */ -#define MMC_BR_BR_INI_DELTA_POS_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_DELTA_POS_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) -#define MMC_BR_BR_INI_DELTA_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_POS_VAL_MASK) >> MMC_BR_BR_INI_DELTA_POS_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_DELTA_REV */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 0> - */ -#define MMC_BR_BR_INI_DELTA_REV_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_DELTA_REV_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) -#define MMC_BR_BR_INI_DELTA_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_REV_VAL_MASK) >> MMC_BR_BR_INI_DELTA_REV_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_DELTA_SPEED */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 19> - */ -#define MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_DELTA_SPEED_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) -#define MMC_BR_BR_INI_DELTA_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_SPEED_VAL_MASK) >> MMC_BR_BR_INI_DELTA_SPEED_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_INI_DELTA_ACCEL */ -/* - * VAL (RW) - * - * the value - * continuous mode: fix<32, 19> - */ -#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT (0U) -#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_SET(x) (((uint32_t)(x) << MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) -#define MMC_BR_BR_INI_DELTA_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_INI_DELTA_ACCEL_VAL_MASK) >> MMC_BR_BR_INI_DELTA_ACCEL_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_CUR_POS_TIME */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BR_BR_CUR_POS_TIME_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT (0U) -#define MMC_BR_BR_CUR_POS_TIME_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_TIME_VAL_MASK) >> MMC_BR_BR_CUR_POS_TIME_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_CUR_POS */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BR_BR_CUR_POS_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_CUR_POS_VAL_SHIFT (0U) -#define MMC_BR_BR_CUR_POS_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_POS_VAL_MASK) >> MMC_BR_BR_CUR_POS_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_CUR_REV */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BR_BR_CUR_REV_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_CUR_REV_VAL_SHIFT (0U) -#define MMC_BR_BR_CUR_REV_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_REV_VAL_MASK) >> MMC_BR_BR_CUR_REV_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_CUR_SPEED */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BR_BR_CUR_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_CUR_SPEED_VAL_SHIFT (0U) -#define MMC_BR_BR_CUR_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_SPEED_VAL_MASK) >> MMC_BR_BR_CUR_SPEED_VAL_SHIFT) - -/* Bitfield definition for register of struct array BR: BR_CUR_ACCEL */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BR_BR_CUR_ACCEL_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BR_BR_CUR_ACCEL_VAL_SHIFT (0U) -#define MMC_BR_BR_CUR_ACCEL_VAL_GET(x) (((uint32_t)(x) & MMC_BR_BR_CUR_ACCEL_VAL_MASK) >> MMC_BR_BR_CUR_ACCEL_VAL_SHIFT) - -/* Bitfield definition for register: BK0_TIMESTAMP */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK0_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK0_TIMESTAMP_VAL_SHIFT (0U) -#define MMC_BK0_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_TIMESTAMP_VAL_MASK) >> MMC_BK0_TIMESTAMP_VAL_SHIFT) - -/* Bitfield definition for register: BK0_POSITION */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK0_POSITION_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK0_POSITION_VAL_SHIFT (0U) -#define MMC_BK0_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_POSITION_VAL_MASK) >> MMC_BK0_POSITION_VAL_SHIFT) - -/* Bitfield definition for register: BK0_REVOLUTION */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK0_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK0_REVOLUTION_VAL_SHIFT (0U) -#define MMC_BK0_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_REVOLUTION_VAL_MASK) >> MMC_BK0_REVOLUTION_VAL_SHIFT) - -/* Bitfield definition for register: BK0_SPEED */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK0_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK0_SPEED_VAL_SHIFT (0U) -#define MMC_BK0_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_SPEED_VAL_MASK) >> MMC_BK0_SPEED_VAL_SHIFT) - -/* Bitfield definition for register: BK0_ACCELERATOR */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK0_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK0_ACCELERATOR_VAL_SHIFT (0U) -#define MMC_BK0_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK0_ACCELERATOR_VAL_MASK) >> MMC_BK0_ACCELERATOR_VAL_SHIFT) - -/* Bitfield definition for register: BK1_TIMESTAMP */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK1_TIMESTAMP_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK1_TIMESTAMP_VAL_SHIFT (0U) -#define MMC_BK1_TIMESTAMP_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_TIMESTAMP_VAL_MASK) >> MMC_BK1_TIMESTAMP_VAL_SHIFT) - -/* Bitfield definition for register: BK1_POSITION */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK1_POSITION_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK1_POSITION_VAL_SHIFT (0U) -#define MMC_BK1_POSITION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_POSITION_VAL_MASK) >> MMC_BK1_POSITION_VAL_SHIFT) - -/* Bitfield definition for register: BK1_REVOLUTION */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK1_REVOLUTION_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK1_REVOLUTION_VAL_SHIFT (0U) -#define MMC_BK1_REVOLUTION_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_REVOLUTION_VAL_MASK) >> MMC_BK1_REVOLUTION_VAL_SHIFT) - -/* Bitfield definition for register: BK1_SPEED */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK1_SPEED_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK1_SPEED_VAL_SHIFT (0U) -#define MMC_BK1_SPEED_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_SPEED_VAL_MASK) >> MMC_BK1_SPEED_VAL_SHIFT) - -/* Bitfield definition for register: BK1_ACCELERATOR */ -/* - * VAL (RO) - * - * the value - */ -#define MMC_BK1_ACCELERATOR_VAL_MASK (0xFFFFFFFFUL) -#define MMC_BK1_ACCELERATOR_VAL_SHIFT (0U) -#define MMC_BK1_ACCELERATOR_VAL_GET(x) (((uint32_t)(x) & MMC_BK1_ACCELERATOR_VAL_MASK) >> MMC_BK1_ACCELERATOR_VAL_SHIFT) - - - -/* COEF_TRG_CFG register group index macro definition */ -#define MMC_COEF_TRG_CFG_0 (0UL) -#define MMC_COEF_TRG_CFG_1 (1UL) -#define MMC_COEF_TRG_CFG_2 (2UL) - -/* BR register group index macro definition */ -#define MMC_BR_0 (0UL) -#define MMC_BR_1 (1UL) - - -#endif /* HPM_MMC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mon_regs.h deleted file mode 100644 index ddc1f854707..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_mon_regs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MON_H -#define HPM_MON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[4]; - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - __RW uint32_t IRQ_FLAG; /* 0x40: */ - __RW uint32_t IRQ_ENABLE; /* 0x44: */ -} MON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define MON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define MON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define MON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << MON_MONITOR_CONTROL_ACTIVE_SHIFT) & MON_MONITOR_CONTROL_ACTIVE_MASK) -#define MON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & MON_MONITOR_CONTROL_ACTIVE_MASK) >> MON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define MON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define MON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define MON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MON_MONITOR_CONTROL_ENABLE_SHIFT) & MON_MONITOR_CONTROL_ENABLE_MASK) -#define MON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MON_MONITOR_CONTROL_ENABLE_MASK) >> MON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define MON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define MON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define MON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << MON_MONITOR_STATUS_FLAG_SHIFT) & MON_MONITOR_STATUS_FLAG_MASK) -#define MON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & MON_MONITOR_STATUS_FLAG_MASK) >> MON_MONITOR_STATUS_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_FLAG */ -/* - * FLAG (RW) - * - * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt - * 1: monitor interrupt happened - */ -#define MON_IRQ_FLAG_FLAG_MASK (0xFU) -#define MON_IRQ_FLAG_FLAG_SHIFT (0U) -#define MON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << MON_IRQ_FLAG_FLAG_SHIFT) & MON_IRQ_FLAG_FLAG_MASK) -#define MON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & MON_IRQ_FLAG_FLAG_MASK) >> MON_IRQ_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * ENABLE (RW) - * - * interrupt enable, each bit represents for one monitor - * 0: monitor interrupt disabled - * 1: monitor interrupt enabled - */ -#define MON_IRQ_ENABLE_ENABLE_MASK (0xFU) -#define MON_IRQ_ENABLE_ENABLE_SHIFT (0U) -#define MON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << MON_IRQ_ENABLE_ENABLE_SHIFT) & MON_IRQ_ENABLE_ENABLE_MASK) -#define MON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & MON_IRQ_ENABLE_ENABLE_MASK) >> MON_IRQ_ENABLE_ENABLE_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define MON_MONITOR_GLITCH0 (0UL) -#define MON_MONITOR_GLITCH1 (1UL) -#define MON_MONITOR_CLOCK0 (2UL) -#define MON_MONITOR_CLOCK1 (3UL) - - -#endif /* HPM_MON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_opamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_opamp_regs.h deleted file mode 100644 index 16e2d60b2f9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_opamp_regs.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OPAMP_H -#define HPM_OPAMP_H - -typedef struct { - __RW uint32_t CTRL0; /* 0x0: control reg */ - __RW uint32_t STATUS; /* 0x4: status reg */ - __RW uint32_t CTRL1; /* 0x8: control reg1 */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x10: */ - __RW uint32_t CFG1; /* 0x14: */ - __RW uint32_t CFG2; /* 0x18: */ - } CFG[10]; -} OPAMP_Type; - - -/* Bitfield definition for register: CTRL0 */ -/* - * EN_LV (RW) - * - */ -#define OPAMP_CTRL0_EN_LV_MASK (0x4000000UL) -#define OPAMP_CTRL0_EN_LV_SHIFT (26U) -#define OPAMP_CTRL0_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_EN_LV_SHIFT) & OPAMP_CTRL0_EN_LV_MASK) -#define OPAMP_CTRL0_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_EN_LV_MASK) >> OPAMP_CTRL0_EN_LV_SHIFT) - -/* - * VIM_SEL (RW) - * - */ -#define OPAMP_CTRL0_VIM_SEL_MASK (0x70000UL) -#define OPAMP_CTRL0_VIM_SEL_SHIFT (16U) -#define OPAMP_CTRL0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIM_SEL_SHIFT) & OPAMP_CTRL0_VIM_SEL_MASK) -#define OPAMP_CTRL0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIM_SEL_MASK) >> OPAMP_CTRL0_VIM_SEL_SHIFT) - -/* - * MODE (RW) - * - */ -#define OPAMP_CTRL0_MODE_MASK (0xF800U) -#define OPAMP_CTRL0_MODE_SHIFT (11U) -#define OPAMP_CTRL0_MODE_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MODE_SHIFT) & OPAMP_CTRL0_MODE_MASK) -#define OPAMP_CTRL0_MODE_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MODE_MASK) >> OPAMP_CTRL0_MODE_SHIFT) - -/* - * GAIN_SEL (RW) - * - */ -#define OPAMP_CTRL0_GAIN_SEL_MASK (0x700U) -#define OPAMP_CTRL0_GAIN_SEL_SHIFT (8U) -#define OPAMP_CTRL0_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_GAIN_SEL_SHIFT) & OPAMP_CTRL0_GAIN_SEL_MASK) -#define OPAMP_CTRL0_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_GAIN_SEL_MASK) >> OPAMP_CTRL0_GAIN_SEL_SHIFT) - -/* - * DISABLE_PM_CAP (RW) - * - */ -#define OPAMP_CTRL0_DISABLE_PM_CAP_MASK (0x80U) -#define OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT (7U) -#define OPAMP_CTRL0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) -#define OPAMP_CTRL0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_DISABLE_PM_CAP_MASK) >> OPAMP_CTRL0_DISABLE_PM_CAP_SHIFT) - -/* - * MILLER_SEL (RW) - * - */ -#define OPAMP_CTRL0_MILLER_SEL_MASK (0x70U) -#define OPAMP_CTRL0_MILLER_SEL_SHIFT (4U) -#define OPAMP_CTRL0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_MILLER_SEL_SHIFT) & OPAMP_CTRL0_MILLER_SEL_MASK) -#define OPAMP_CTRL0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_MILLER_SEL_MASK) >> OPAMP_CTRL0_MILLER_SEL_SHIFT) - -/* - * VBYPASS (RW) - * - */ -#define OPAMP_CTRL0_VBYPASS_MASK (0x8U) -#define OPAMP_CTRL0_VBYPASS_SHIFT (3U) -#define OPAMP_CTRL0_VBYPASS_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VBYPASS_SHIFT) & OPAMP_CTRL0_VBYPASS_MASK) -#define OPAMP_CTRL0_VBYPASS_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VBYPASS_MASK) >> OPAMP_CTRL0_VBYPASS_SHIFT) - -/* - * VIP_SEL (RW) - * - */ -#define OPAMP_CTRL0_VIP_SEL_MASK (0x7U) -#define OPAMP_CTRL0_VIP_SEL_SHIFT (0U) -#define OPAMP_CTRL0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL0_VIP_SEL_SHIFT) & OPAMP_CTRL0_VIP_SEL_MASK) -#define OPAMP_CTRL0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL0_VIP_SEL_MASK) >> OPAMP_CTRL0_VIP_SEL_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TRIG_CONFLICT (RWC) - * - * if more than one hardware trigger is set, will put all trigger input here; - * write any value to clear - */ -#define OPAMP_STATUS_TRIG_CONFLICT_MASK (0xFF00000UL) -#define OPAMP_STATUS_TRIG_CONFLICT_SHIFT (20U) -#define OPAMP_STATUS_TRIG_CONFLICT_SET(x) (((uint32_t)(x) << OPAMP_STATUS_TRIG_CONFLICT_SHIFT) & OPAMP_STATUS_TRIG_CONFLICT_MASK) -#define OPAMP_STATUS_TRIG_CONFLICT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_TRIG_CONFLICT_MASK) >> OPAMP_STATUS_TRIG_CONFLICT_SHIFT) - -/* - * PRESET_ACT (RO) - * - * 1 for preset active; one of cur_preset is selected for OPAMP; - * 0 for no preset, OPAMP use cfg0 parameters - */ -#define OPAMP_STATUS_PRESET_ACT_MASK (0x80000UL) -#define OPAMP_STATUS_PRESET_ACT_SHIFT (19U) -#define OPAMP_STATUS_PRESET_ACT_GET(x) (((uint32_t)(x) & OPAMP_STATUS_PRESET_ACT_MASK) >> OPAMP_STATUS_PRESET_ACT_SHIFT) - -/* - * CUR_PRESET (RO) - * - * current selected preset - */ -#define OPAMP_STATUS_CUR_PRESET_MASK (0x70000UL) -#define OPAMP_STATUS_CUR_PRESET_SHIFT (16U) -#define OPAMP_STATUS_CUR_PRESET_GET(x) (((uint32_t)(x) & OPAMP_STATUS_CUR_PRESET_MASK) >> OPAMP_STATUS_CUR_PRESET_SHIFT) - -/* Bitfield definition for register: CTRL1 */ -/* - * SW_PRESET (RW) - * - * set to use preset defined by sw_sel. - * NOTE: when set, the hardware trigger will not be used - */ -#define OPAMP_CTRL1_SW_PRESET_MASK (0x80000000UL) -#define OPAMP_CTRL1_SW_PRESET_SHIFT (31U) -#define OPAMP_CTRL1_SW_PRESET_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_PRESET_SHIFT) & OPAMP_CTRL1_SW_PRESET_MASK) -#define OPAMP_CTRL1_SW_PRESET_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_PRESET_MASK) >> OPAMP_CTRL1_SW_PRESET_SHIFT) - -/* - * SW_SEL (RW) - * - */ -#define OPAMP_CTRL1_SW_SEL_MASK (0x7U) -#define OPAMP_CTRL1_SW_SEL_SHIFT (0U) -#define OPAMP_CTRL1_SW_SEL_SET(x) (((uint32_t)(x) << OPAMP_CTRL1_SW_SEL_SHIFT) & OPAMP_CTRL1_SW_SEL_MASK) -#define OPAMP_CTRL1_SW_SEL_GET(x) (((uint32_t)(x) & OPAMP_CTRL1_SW_SEL_MASK) >> OPAMP_CTRL1_SW_SEL_SHIFT) - -/* Bitfield definition for register of struct array CFG: CFG0 */ -/* - * DISABLE_PM_CAP (RW) - * - */ -#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK (0x8000000UL) -#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT (27U) -#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) -#define OPAMP_CFG_CFG0_DISABLE_PM_CAP_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_DISABLE_PM_CAP_MASK) >> OPAMP_CFG_CFG0_DISABLE_PM_CAP_SHIFT) - -/* - * MILLER_SEL (RW) - * - */ -#define OPAMP_CFG_CFG0_MILLER_SEL_MASK (0x7000000UL) -#define OPAMP_CFG_CFG0_MILLER_SEL_SHIFT (24U) -#define OPAMP_CFG_CFG0_MILLER_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) -#define OPAMP_CFG_CFG0_MILLER_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_MILLER_SEL_MASK) >> OPAMP_CFG_CFG0_MILLER_SEL_SHIFT) - -/* - * VIM_SEL (RW) - * - */ -#define OPAMP_CFG_CFG0_VIM_SEL_MASK (0x700U) -#define OPAMP_CFG_CFG0_VIM_SEL_SHIFT (8U) -#define OPAMP_CFG_CFG0_VIM_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIM_SEL_SHIFT) & OPAMP_CFG_CFG0_VIM_SEL_MASK) -#define OPAMP_CFG_CFG0_VIM_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIM_SEL_MASK) >> OPAMP_CFG_CFG0_VIM_SEL_SHIFT) - -/* - * VIP_SEL (RW) - * - */ -#define OPAMP_CFG_CFG0_VIP_SEL_MASK (0x7U) -#define OPAMP_CFG_CFG0_VIP_SEL_SHIFT (0U) -#define OPAMP_CFG_CFG0_VIP_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG0_VIP_SEL_SHIFT) & OPAMP_CFG_CFG0_VIP_SEL_MASK) -#define OPAMP_CFG_CFG0_VIP_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG0_VIP_SEL_MASK) >> OPAMP_CFG_CFG0_VIP_SEL_SHIFT) - -/* Bitfield definition for register of struct array CFG: CFG1 */ -/* - * HW_TRIG_EN (RW) - * - * set to enable hardware trigger from moto system. - * NOTE: when sw_preset is enabled, this bit will not take effert - */ -#define OPAMP_CFG_CFG1_HW_TRIG_EN_MASK (0x80000000UL) -#define OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT (31U) -#define OPAMP_CFG_CFG1_HW_TRIG_EN_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) -#define OPAMP_CFG_CFG1_HW_TRIG_EN_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_HW_TRIG_EN_MASK) >> OPAMP_CFG_CFG1_HW_TRIG_EN_SHIFT) - -/* - * EN_LV (RW) - * - */ -#define OPAMP_CFG_CFG1_EN_LV_MASK (0x40000000UL) -#define OPAMP_CFG_CFG1_EN_LV_SHIFT (30U) -#define OPAMP_CFG_CFG1_EN_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_EN_LV_SHIFT) & OPAMP_CFG_CFG1_EN_LV_MASK) -#define OPAMP_CFG_CFG1_EN_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_EN_LV_MASK) >> OPAMP_CFG_CFG1_EN_LV_SHIFT) - -/* - * VBYPASS_LV (RW) - * - */ -#define OPAMP_CFG_CFG1_VBYPASS_LV_MASK (0x20000000UL) -#define OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT (29U) -#define OPAMP_CFG_CFG1_VBYPASS_LV_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) -#define OPAMP_CFG_CFG1_VBYPASS_LV_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_VBYPASS_LV_MASK) >> OPAMP_CFG_CFG1_VBYPASS_LV_SHIFT) - -/* - * MODE (RW) - * - */ -#define OPAMP_CFG_CFG1_MODE_MASK (0xF8U) -#define OPAMP_CFG_CFG1_MODE_SHIFT (3U) -#define OPAMP_CFG_CFG1_MODE_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_MODE_SHIFT) & OPAMP_CFG_CFG1_MODE_MASK) -#define OPAMP_CFG_CFG1_MODE_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_MODE_MASK) >> OPAMP_CFG_CFG1_MODE_SHIFT) - -/* - * GAIN_SEL (RW) - * - */ -#define OPAMP_CFG_CFG1_GAIN_SEL_MASK (0x7U) -#define OPAMP_CFG_CFG1_GAIN_SEL_SHIFT (0U) -#define OPAMP_CFG_CFG1_GAIN_SEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) -#define OPAMP_CFG_CFG1_GAIN_SEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG1_GAIN_SEL_MASK) >> OPAMP_CFG_CFG1_GAIN_SEL_SHIFT) - -/* Bitfield definition for register of struct array CFG: CFG2 */ -/* - * CHANNEL (RW) - * - */ -#define OPAMP_CFG_CFG2_CHANNEL_MASK (0x7000000UL) -#define OPAMP_CFG_CFG2_CHANNEL_SHIFT (24U) -#define OPAMP_CFG_CFG2_CHANNEL_SET(x) (((uint32_t)(x) << OPAMP_CFG_CFG2_CHANNEL_SHIFT) & OPAMP_CFG_CFG2_CHANNEL_MASK) -#define OPAMP_CFG_CFG2_CHANNEL_GET(x) (((uint32_t)(x) & OPAMP_CFG_CFG2_CHANNEL_MASK) >> OPAMP_CFG_CFG2_CHANNEL_SHIFT) - - - -/* CFG register group index macro definition */ -#define OPAMP_CFG_PRESET0 (0UL) -#define OPAMP_CFG_PRESET1 (1UL) -#define OPAMP_CFG_PRESET2 (2UL) -#define OPAMP_CFG_PRESET3 (4UL) -#define OPAMP_CFG_PRESET4 (5UL) -#define OPAMP_CFG_PRESET5 (6UL) -#define OPAMP_CFG_PRESET6 (8UL) -#define OPAMP_CFG_PRESET7 (9UL) - - -#endif /* HPM_OPAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_otp_regs.h deleted file mode 100644 index feb5f9c2efe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_otp_regs.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OTP_H -#define HPM_OTP_H - -typedef struct { - __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ - __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ - __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ - __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ - __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ - __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ - __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ - __RW uint32_t DATA; /* 0x804: DATA */ - __RW uint32_t ADDR; /* 0x808: ADDR */ - __RW uint32_t CMD; /* 0x80C: CMD */ - __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ - __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ - __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ - __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ - __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ - __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ - __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ - __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ -} OTP_Type; - - -/* Bitfield definition for register array: SHADOW */ -/* - * SHADOW (RW) - * - * shadow register of fuse for pmic area - * for PMIC, index valid for 0-15, for SOC index valid for 16-128 - */ -#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_SHADOW_SHIFT (0U) -#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) -#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) - -/* Bitfield definition for register array: SHADOW_LOCK */ -/* - * LOCK (RW) - * - * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) -#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) -#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register array: FUSE */ -/* - * FUSE (RW) - * - * fuse array, valid in PMIC part only - * read operation will read out value in fuse array - * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - */ -#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_FUSE_SHIFT (0U) -#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) -#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) - -/* Bitfield definition for register array: FUSE_LOCK */ -/* - * LOCK (RW) - * - * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) -#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) -#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK (RW) - * - * unlock word for fuse array operation - * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. - * Please make sure 24M crystal is running and 2.5V LDO working properly - */ -#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) -#define OTP_UNLOCK_UNLOCK_SHIFT (0U) -#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) -#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * data register for non-blocking access - * this register hold dat read from fuse array or data to by programmed to fuse array - */ -#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) -#define OTP_DATA_DATA_SHIFT (0U) -#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) -#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * word address to be read or write - */ -#define OTP_ADDR_ADDR_MASK (0x7FU) -#define OTP_ADDR_ADDR_SHIFT (0U) -#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) -#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * command to access fure array - * "BLOW" will update fuse word at ADDR to value hold in DATA - * "READ" will fetch fuse value in at ADDR to DATA register - */ -#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) -#define OTP_CMD_CMD_SHIFT (0U) -#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) -#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) - -/* Bitfield definition for register: LOAD_REQ */ -/* - * REQUEST (RW) - * - * reload request for 4 regions - * bit0: region0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) -#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) -#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) -#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) - -/* Bitfield definition for register: LOAD_COMP */ -/* - * COMPLETE (RW) - * - * reload complete sign for 4 regions - * bit0: region 0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) -#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) -#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) -#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) - -/* Bitfield definition for register array: REGION */ -/* - * STOP (RW) - * - * stop address of load region, fuse word at end address will NOT be reloaded - * region0: fixed at 8 - * region1: fixed at 16 - * region2: fixed at 0, - * region3: usrer configurable - */ -#define OTP_REGION_STOP_MASK (0x7F00U) -#define OTP_REGION_STOP_SHIFT (8U) -#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) -#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) - -/* - * START (RW) - * - * start address of load region, fuse word at start address will be reloaded - * region0: fixed at 0 - * region1: fixed at 8 - * region2: fixed at 16, - * region3: usrer configurable - */ -#define OTP_REGION_START_MASK (0x7FU) -#define OTP_REGION_START_SHIFT (0U) -#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) -#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) - -/* Bitfield definition for register: INT_FLAG */ -/* - * WRITE (RW) - * - * fuse write flag, write 1 to clear - * 0: fuse is not written or writing - * 1: value in DATA register is programmed into fuse - */ -#define OTP_INT_FLAG_WRITE_MASK (0x4U) -#define OTP_INT_FLAG_WRITE_SHIFT (2U) -#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) -#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read flag, write 1 to clear - * 0: fuse is not read or reading - * 1: fuse value is put in DATA register - */ -#define OTP_INT_FLAG_READ_MASK (0x2U) -#define OTP_INT_FLAG_READ_SHIFT (1U) -#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) -#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load flag, write 1 to clear - * 0: fuse is not loaded or loading - * 1: fuse loaded - */ -#define OTP_INT_FLAG_LOAD_MASK (0x1U) -#define OTP_INT_FLAG_LOAD_SHIFT (0U) -#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) -#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRITE (RW) - * - * fuse write interrupt enable - * 0: fuse write interrupt is not enable - * 1: fuse write interrupt is enable - */ -#define OTP_INT_EN_WRITE_MASK (0x4U) -#define OTP_INT_EN_WRITE_SHIFT (2U) -#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) -#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read interrupt enable - * 0: fuse read interrupt is not enable - * 1: fuse read interrupt is enable - */ -#define OTP_INT_EN_READ_MASK (0x2U) -#define OTP_INT_EN_READ_SHIFT (1U) -#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) -#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load interrupt enable - * 0: fuse load interrupt is not enable - * 1: fuse load interrupt is enable - */ -#define OTP_INT_EN_LOAD_MASK (0x1U) -#define OTP_INT_EN_LOAD_SHIFT (0U) -#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) -#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) - - - -/* SHADOW register group index macro definition */ -#define OTP_SHADOW_SHADOW000 (0UL) -#define OTP_SHADOW_SHADOW001 (1UL) -#define OTP_SHADOW_SHADOW002 (2UL) -#define OTP_SHADOW_SHADOW003 (3UL) -#define OTP_SHADOW_SHADOW004 (4UL) -#define OTP_SHADOW_SHADOW005 (5UL) -#define OTP_SHADOW_SHADOW006 (6UL) -#define OTP_SHADOW_SHADOW007 (7UL) -#define OTP_SHADOW_SHADOW008 (8UL) -#define OTP_SHADOW_SHADOW009 (9UL) -#define OTP_SHADOW_SHADOW010 (10UL) -#define OTP_SHADOW_SHADOW011 (11UL) -#define OTP_SHADOW_SHADOW012 (12UL) -#define OTP_SHADOW_SHADOW013 (13UL) -#define OTP_SHADOW_SHADOW014 (14UL) -#define OTP_SHADOW_SHADOW015 (15UL) -#define OTP_SHADOW_SHADOW016 (16UL) -#define OTP_SHADOW_SHADOW017 (17UL) -#define OTP_SHADOW_SHADOW018 (18UL) -#define OTP_SHADOW_SHADOW019 (19UL) -#define OTP_SHADOW_SHADOW020 (20UL) -#define OTP_SHADOW_SHADOW021 (21UL) -#define OTP_SHADOW_SHADOW022 (22UL) -#define OTP_SHADOW_SHADOW023 (23UL) -#define OTP_SHADOW_SHADOW024 (24UL) -#define OTP_SHADOW_SHADOW025 (25UL) -#define OTP_SHADOW_SHADOW026 (26UL) -#define OTP_SHADOW_SHADOW027 (27UL) -#define OTP_SHADOW_SHADOW028 (28UL) -#define OTP_SHADOW_SHADOW029 (29UL) -#define OTP_SHADOW_SHADOW030 (30UL) -#define OTP_SHADOW_SHADOW031 (31UL) -#define OTP_SHADOW_SHADOW032 (32UL) -#define OTP_SHADOW_SHADOW033 (33UL) -#define OTP_SHADOW_SHADOW034 (34UL) -#define OTP_SHADOW_SHADOW035 (35UL) -#define OTP_SHADOW_SHADOW036 (36UL) -#define OTP_SHADOW_SHADOW037 (37UL) -#define OTP_SHADOW_SHADOW038 (38UL) -#define OTP_SHADOW_SHADOW039 (39UL) -#define OTP_SHADOW_SHADOW040 (40UL) -#define OTP_SHADOW_SHADOW041 (41UL) -#define OTP_SHADOW_SHADOW042 (42UL) -#define OTP_SHADOW_SHADOW043 (43UL) -#define OTP_SHADOW_SHADOW044 (44UL) -#define OTP_SHADOW_SHADOW045 (45UL) -#define OTP_SHADOW_SHADOW046 (46UL) -#define OTP_SHADOW_SHADOW047 (47UL) -#define OTP_SHADOW_SHADOW048 (48UL) -#define OTP_SHADOW_SHADOW049 (49UL) -#define OTP_SHADOW_SHADOW050 (50UL) -#define OTP_SHADOW_SHADOW051 (51UL) -#define OTP_SHADOW_SHADOW052 (52UL) -#define OTP_SHADOW_SHADOW053 (53UL) -#define OTP_SHADOW_SHADOW054 (54UL) -#define OTP_SHADOW_SHADOW055 (55UL) -#define OTP_SHADOW_SHADOW056 (56UL) -#define OTP_SHADOW_SHADOW057 (57UL) -#define OTP_SHADOW_SHADOW058 (58UL) -#define OTP_SHADOW_SHADOW059 (59UL) -#define OTP_SHADOW_SHADOW060 (60UL) -#define OTP_SHADOW_SHADOW061 (61UL) -#define OTP_SHADOW_SHADOW062 (62UL) -#define OTP_SHADOW_SHADOW063 (63UL) -#define OTP_SHADOW_SHADOW064 (64UL) -#define OTP_SHADOW_SHADOW065 (65UL) -#define OTP_SHADOW_SHADOW066 (66UL) -#define OTP_SHADOW_SHADOW067 (67UL) -#define OTP_SHADOW_SHADOW068 (68UL) -#define OTP_SHADOW_SHADOW069 (69UL) -#define OTP_SHADOW_SHADOW070 (70UL) -#define OTP_SHADOW_SHADOW071 (71UL) -#define OTP_SHADOW_SHADOW072 (72UL) -#define OTP_SHADOW_SHADOW073 (73UL) -#define OTP_SHADOW_SHADOW074 (74UL) -#define OTP_SHADOW_SHADOW075 (75UL) -#define OTP_SHADOW_SHADOW076 (76UL) -#define OTP_SHADOW_SHADOW077 (77UL) -#define OTP_SHADOW_SHADOW078 (78UL) -#define OTP_SHADOW_SHADOW079 (79UL) -#define OTP_SHADOW_SHADOW080 (80UL) -#define OTP_SHADOW_SHADOW081 (81UL) -#define OTP_SHADOW_SHADOW082 (82UL) -#define OTP_SHADOW_SHADOW083 (83UL) -#define OTP_SHADOW_SHADOW084 (84UL) -#define OTP_SHADOW_SHADOW085 (85UL) -#define OTP_SHADOW_SHADOW086 (86UL) -#define OTP_SHADOW_SHADOW087 (87UL) -#define OTP_SHADOW_SHADOW088 (88UL) -#define OTP_SHADOW_SHADOW089 (89UL) -#define OTP_SHADOW_SHADOW090 (90UL) -#define OTP_SHADOW_SHADOW091 (91UL) -#define OTP_SHADOW_SHADOW092 (92UL) -#define OTP_SHADOW_SHADOW093 (93UL) -#define OTP_SHADOW_SHADOW094 (94UL) -#define OTP_SHADOW_SHADOW095 (95UL) -#define OTP_SHADOW_SHADOW096 (96UL) -#define OTP_SHADOW_SHADOW097 (97UL) -#define OTP_SHADOW_SHADOW098 (98UL) -#define OTP_SHADOW_SHADOW099 (99UL) -#define OTP_SHADOW_SHADOW100 (100UL) -#define OTP_SHADOW_SHADOW101 (101UL) -#define OTP_SHADOW_SHADOW102 (102UL) -#define OTP_SHADOW_SHADOW103 (103UL) -#define OTP_SHADOW_SHADOW104 (104UL) -#define OTP_SHADOW_SHADOW105 (105UL) -#define OTP_SHADOW_SHADOW106 (106UL) -#define OTP_SHADOW_SHADOW107 (107UL) -#define OTP_SHADOW_SHADOW108 (108UL) -#define OTP_SHADOW_SHADOW109 (109UL) -#define OTP_SHADOW_SHADOW110 (110UL) -#define OTP_SHADOW_SHADOW111 (111UL) -#define OTP_SHADOW_SHADOW112 (112UL) -#define OTP_SHADOW_SHADOW113 (113UL) -#define OTP_SHADOW_SHADOW114 (114UL) -#define OTP_SHADOW_SHADOW115 (115UL) -#define OTP_SHADOW_SHADOW116 (116UL) -#define OTP_SHADOW_SHADOW117 (117UL) -#define OTP_SHADOW_SHADOW118 (118UL) -#define OTP_SHADOW_SHADOW119 (119UL) -#define OTP_SHADOW_SHADOW120 (120UL) -#define OTP_SHADOW_SHADOW121 (121UL) -#define OTP_SHADOW_SHADOW122 (122UL) -#define OTP_SHADOW_SHADOW123 (123UL) -#define OTP_SHADOW_SHADOW124 (124UL) -#define OTP_SHADOW_SHADOW125 (125UL) -#define OTP_SHADOW_SHADOW126 (126UL) -#define OTP_SHADOW_SHADOW127 (127UL) - -/* SHADOW_LOCK register group index macro definition */ -#define OTP_SHADOW_LOCK_LOCK00 (0UL) -#define OTP_SHADOW_LOCK_LOCK01 (1UL) -#define OTP_SHADOW_LOCK_LOCK02 (2UL) -#define OTP_SHADOW_LOCK_LOCK03 (3UL) -#define OTP_SHADOW_LOCK_LOCK04 (4UL) -#define OTP_SHADOW_LOCK_LOCK05 (5UL) -#define OTP_SHADOW_LOCK_LOCK06 (6UL) -#define OTP_SHADOW_LOCK_LOCK07 (7UL) - -/* FUSE register group index macro definition */ -#define OTP_FUSE_FUSE000 (0UL) -#define OTP_FUSE_FUSE001 (1UL) -#define OTP_FUSE_FUSE002 (2UL) -#define OTP_FUSE_FUSE003 (3UL) -#define OTP_FUSE_FUSE004 (4UL) -#define OTP_FUSE_FUSE005 (5UL) -#define OTP_FUSE_FUSE006 (6UL) -#define OTP_FUSE_FUSE007 (7UL) -#define OTP_FUSE_FUSE008 (8UL) -#define OTP_FUSE_FUSE009 (9UL) -#define OTP_FUSE_FUSE010 (10UL) -#define OTP_FUSE_FUSE011 (11UL) -#define OTP_FUSE_FUSE012 (12UL) -#define OTP_FUSE_FUSE013 (13UL) -#define OTP_FUSE_FUSE014 (14UL) -#define OTP_FUSE_FUSE015 (15UL) -#define OTP_FUSE_FUSE016 (16UL) -#define OTP_FUSE_FUSE017 (17UL) -#define OTP_FUSE_FUSE018 (18UL) -#define OTP_FUSE_FUSE019 (19UL) -#define OTP_FUSE_FUSE020 (20UL) -#define OTP_FUSE_FUSE021 (21UL) -#define OTP_FUSE_FUSE022 (22UL) -#define OTP_FUSE_FUSE023 (23UL) -#define OTP_FUSE_FUSE024 (24UL) -#define OTP_FUSE_FUSE025 (25UL) -#define OTP_FUSE_FUSE026 (26UL) -#define OTP_FUSE_FUSE027 (27UL) -#define OTP_FUSE_FUSE028 (28UL) -#define OTP_FUSE_FUSE029 (29UL) -#define OTP_FUSE_FUSE030 (30UL) -#define OTP_FUSE_FUSE031 (31UL) -#define OTP_FUSE_FUSE032 (32UL) -#define OTP_FUSE_FUSE033 (33UL) -#define OTP_FUSE_FUSE034 (34UL) -#define OTP_FUSE_FUSE035 (35UL) -#define OTP_FUSE_FUSE036 (36UL) -#define OTP_FUSE_FUSE037 (37UL) -#define OTP_FUSE_FUSE038 (38UL) -#define OTP_FUSE_FUSE039 (39UL) -#define OTP_FUSE_FUSE040 (40UL) -#define OTP_FUSE_FUSE041 (41UL) -#define OTP_FUSE_FUSE042 (42UL) -#define OTP_FUSE_FUSE043 (43UL) -#define OTP_FUSE_FUSE044 (44UL) -#define OTP_FUSE_FUSE045 (45UL) -#define OTP_FUSE_FUSE046 (46UL) -#define OTP_FUSE_FUSE047 (47UL) -#define OTP_FUSE_FUSE048 (48UL) -#define OTP_FUSE_FUSE049 (49UL) -#define OTP_FUSE_FUSE050 (50UL) -#define OTP_FUSE_FUSE051 (51UL) -#define OTP_FUSE_FUSE052 (52UL) -#define OTP_FUSE_FUSE053 (53UL) -#define OTP_FUSE_FUSE054 (54UL) -#define OTP_FUSE_FUSE055 (55UL) -#define OTP_FUSE_FUSE056 (56UL) -#define OTP_FUSE_FUSE057 (57UL) -#define OTP_FUSE_FUSE058 (58UL) -#define OTP_FUSE_FUSE059 (59UL) -#define OTP_FUSE_FUSE060 (60UL) -#define OTP_FUSE_FUSE061 (61UL) -#define OTP_FUSE_FUSE062 (62UL) -#define OTP_FUSE_FUSE063 (63UL) -#define OTP_FUSE_FUSE064 (64UL) -#define OTP_FUSE_FUSE065 (65UL) -#define OTP_FUSE_FUSE066 (66UL) -#define OTP_FUSE_FUSE067 (67UL) -#define OTP_FUSE_FUSE068 (68UL) -#define OTP_FUSE_FUSE069 (69UL) -#define OTP_FUSE_FUSE070 (70UL) -#define OTP_FUSE_FUSE071 (71UL) -#define OTP_FUSE_FUSE072 (72UL) -#define OTP_FUSE_FUSE073 (73UL) -#define OTP_FUSE_FUSE074 (74UL) -#define OTP_FUSE_FUSE075 (75UL) -#define OTP_FUSE_FUSE076 (76UL) -#define OTP_FUSE_FUSE077 (77UL) -#define OTP_FUSE_FUSE078 (78UL) -#define OTP_FUSE_FUSE079 (79UL) -#define OTP_FUSE_FUSE080 (80UL) -#define OTP_FUSE_FUSE081 (81UL) -#define OTP_FUSE_FUSE082 (82UL) -#define OTP_FUSE_FUSE083 (83UL) -#define OTP_FUSE_FUSE084 (84UL) -#define OTP_FUSE_FUSE085 (85UL) -#define OTP_FUSE_FUSE086 (86UL) -#define OTP_FUSE_FUSE087 (87UL) -#define OTP_FUSE_FUSE088 (88UL) -#define OTP_FUSE_FUSE089 (89UL) -#define OTP_FUSE_FUSE090 (90UL) -#define OTP_FUSE_FUSE091 (91UL) -#define OTP_FUSE_FUSE092 (92UL) -#define OTP_FUSE_FUSE093 (93UL) -#define OTP_FUSE_FUSE094 (94UL) -#define OTP_FUSE_FUSE095 (95UL) -#define OTP_FUSE_FUSE096 (96UL) -#define OTP_FUSE_FUSE097 (97UL) -#define OTP_FUSE_FUSE098 (98UL) -#define OTP_FUSE_FUSE099 (99UL) -#define OTP_FUSE_FUSE100 (100UL) -#define OTP_FUSE_FUSE101 (101UL) -#define OTP_FUSE_FUSE102 (102UL) -#define OTP_FUSE_FUSE103 (103UL) -#define OTP_FUSE_FUSE104 (104UL) -#define OTP_FUSE_FUSE105 (105UL) -#define OTP_FUSE_FUSE106 (106UL) -#define OTP_FUSE_FUSE107 (107UL) -#define OTP_FUSE_FUSE108 (108UL) -#define OTP_FUSE_FUSE109 (109UL) -#define OTP_FUSE_FUSE110 (110UL) -#define OTP_FUSE_FUSE111 (111UL) -#define OTP_FUSE_FUSE112 (112UL) -#define OTP_FUSE_FUSE113 (113UL) -#define OTP_FUSE_FUSE114 (114UL) -#define OTP_FUSE_FUSE115 (115UL) -#define OTP_FUSE_FUSE116 (116UL) -#define OTP_FUSE_FUSE117 (117UL) -#define OTP_FUSE_FUSE118 (118UL) -#define OTP_FUSE_FUSE119 (119UL) -#define OTP_FUSE_FUSE120 (120UL) -#define OTP_FUSE_FUSE121 (121UL) -#define OTP_FUSE_FUSE122 (122UL) -#define OTP_FUSE_FUSE123 (123UL) -#define OTP_FUSE_FUSE124 (124UL) -#define OTP_FUSE_FUSE125 (125UL) -#define OTP_FUSE_FUSE126 (126UL) -#define OTP_FUSE_FUSE127 (127UL) - -/* FUSE_LOCK register group index macro definition */ -#define OTP_FUSE_LOCK_LOCK00 (0UL) -#define OTP_FUSE_LOCK_LOCK01 (1UL) -#define OTP_FUSE_LOCK_LOCK02 (2UL) -#define OTP_FUSE_LOCK_LOCK03 (3UL) -#define OTP_FUSE_LOCK_LOCK04 (4UL) -#define OTP_FUSE_LOCK_LOCK05 (5UL) -#define OTP_FUSE_LOCK_LOCK06 (6UL) -#define OTP_FUSE_LOCK_LOCK07 (7UL) - -/* REGION register group index macro definition */ -#define OTP_REGION_LOAD_REGION0 (0UL) -#define OTP_REGION_LOAD_REGION1 (1UL) -#define OTP_REGION_LOAD_REGION2 (2UL) -#define OTP_REGION_LOAD_REGION3 (3UL) - - -#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pcfg_regs.h deleted file mode 100644 index 831d277710b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pcfg_regs.h +++ /dev/null @@ -1,834 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PCFG_H -#define HPM_PCFG_H - -typedef struct { - __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ - __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ - __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ - __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ - __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ - __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ - __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ - __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ - __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ - __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ - __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ - __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ - __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ - __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ - __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ - __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ - __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ - __RW uint32_t RC24M; /* 0x60: RC 24M config */ - __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ - __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ - __R uint32_t STATUS; /* 0x6C: RC 24M track status */ -} PCFG_Type; - - -/* Bitfield definition for register: BANDGAP */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) -#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) -#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) -#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) - -/* - * VBG_1P0_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) -#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) - -/* - * VBG_P65_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) - -/* - * VBG_P50_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) -#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) -#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) - -/* Bitfield definition for register: LDO1P1 */ -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. - * 700: 700mV - * 720: 720mV - * . . . - * 1320:1320mV - */ -#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) -#define PCFG_LDO1P1_VOLT_SHIFT (0U) -#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) -#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) - -/* Bitfield definition for register: LDO2P5 */ -/* - * READY (RO) - * - * Ready flag, will set 1ms after enabled or voltage change - * 0: LDO is not ready for use - * 1: LDO is ready - */ -#define PCFG_LDO2P5_READY_MASK (0x10000000UL) -#define PCFG_LDO2P5_READY_SHIFT (28U) -#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) -#define PCFG_LDO2P5_ENABLE_SHIFT (16U) -#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) -#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. - * 2125: 2125mV - * 2150: 2150mV - * . . . - * 2900:2900mV - */ -#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) -#define PCFG_LDO2P5_VOLT_SHIFT (0U) -#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) -#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDC is applying new change - * 1: DCDC is ready - */ -#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDC_MODE_READY_SHIFT (28U) -#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDC work mode - * XX0: trun off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDC_MODE_MODE_SHIFT (16U) -#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) -#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) -#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * ouput over voltage protection - * 0: protection enabled, DCDC will shut down is output voltage is unexpected high - * 1: protection disabled, DCDC continue to adjust output voltage - */ -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A, - * 1: 1.3A - */ -#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDC_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDC current level, current level is num * 50mA - */ -#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDC_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) -#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) -#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_AUTOLP (RW) - * - * enable auto enter low power mode - * 0: do not enter low power mode - * 1: enter low power mode if current is detected low - */ -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDC_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDC_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) -#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) -#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) -#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) -#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) -#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) -#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) -#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) -#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDC internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) -#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled - * 1: steping enabled - */ -#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) -#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDC_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDC voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) -#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - */ -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: POWER_TRAP */ -/* - * TRIGGERED (RW) - * - * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. - * 0: low power trap is not triggered - * 1: low power trap triggered - */ -#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) -#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) -#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) -#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) - -/* - * RETENTION (RW) - * - * DCDC enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDC - * 1: reduce DCDC voltage - */ -#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) -#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) -#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) -#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) - -/* - * TRAP (RW) - * - * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered - * 0: trap not enabled, pmic side low power function disabled - * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - */ -#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) -#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) -#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) -#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) - -/* Bitfield definition for register: WAKE_CAUSE */ -/* - * CAUSE (RW) - * - * wake up cause, each bit represents one wake up source, write 1 to clear the register bit - * 0: wake up source is not active during last wakeup - * 1: wake up source is active furing last wakeup - * bit 0: pmic_enable - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit31: pin wakeup - */ -#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) -#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) -#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: WAKE_MASK */ -/* - * MASK (RW) - * - * mask for wake up sources, each bit represents one wakeup source - * 0: allow source to wake up system - * 1: disallow source to wakeup system - * bit 0: pmic_enable - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit31: pin wakeup - */ -#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_MASK_MASK_SHIFT (0U) -#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) -#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) - -/* Bitfield definition for register: SCG_CTRL */ -/* - * SCG (RW) - * - * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: reserved - * 10: clock is always off - * 11: clock is always on - * bit6-7:gpio - * bit8-9:ioc - * bit10-11: timer - * bit12-13:wdog - * bit14-15:uart - */ -#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) -#define PCFG_SCG_CTRL_SCG_SHIFT (0U) -#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) -#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) - -/* Bitfield definition for register: RC24M */ -/* - * RC_TRIMMED (RW) - * - * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: RC is not trimmed - * 1: RC is trimmed - */ -#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) -#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) -#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) -#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) - -/* - * TRIM_C (RW) - * - * Coarse trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_C_MASK (0x700U) -#define PCFG_RC24M_TRIM_C_SHIFT (8U) -#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) -#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) - -/* - * TRIM_F (RW) - * - * Fine trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_F_MASK (0x1FU) -#define PCFG_RC24M_TRIM_F_SHIFT (0U) -#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) -#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) - -/* Bitfield definition for register: RC24M_TRACK */ -/* - * SEL24M (RW) - * - * Select track reference - * 0: select 32K as reference - * 1: select 24M XTAL as reference - */ -#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) -#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) -#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) -#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) - -/* - * RETURN (RW) - * - * Retrun default value when XTAL loss - * 0: remain last tracking value - * 1: switch to default value - */ -#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) -#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) -#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) -#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) - -/* - * TRACK (RW) - * - * track mode - * 0: RC24M free running - * 1: track RC24M to external XTAL - */ -#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) -#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) -#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) -#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) - -/* Bitfield definition for register: TRACK_TARGET */ -/* - * PRE_DIV (RW) - * - * Divider for reference source - */ -#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) -#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) -#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) -#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) - -/* - * TARGET (RW) - * - * Target frequency multiplier of divided source - */ -#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) -#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) -#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) -#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * SEL32K (RO) - * - * track is using XTAL32K - * 0: track is not using XTAL32K - * 1: track is using XTAL32K - */ -#define PCFG_STATUS_SEL32K_MASK (0x100000UL) -#define PCFG_STATUS_SEL32K_SHIFT (20U) -#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) - -/* - * SEL24M (RO) - * - * track is using XTAL24M - * 0: track is not using XTAL24M - * 1: track is using XTAL24M - */ -#define PCFG_STATUS_SEL24M_MASK (0x10000UL) -#define PCFG_STATUS_SEL24M_SHIFT (16U) -#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) - -/* - * EN_TRIM (RO) - * - * default value takes effect - * 0: default value is invalid - * 1: default value is valid - */ -#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) -#define PCFG_STATUS_EN_TRIM_SHIFT (15U) -#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) - -/* - * TRIM_C (RO) - * - * default coarse trim value - */ -#define PCFG_STATUS_TRIM_C_MASK (0x700U) -#define PCFG_STATUS_TRIM_C_SHIFT (8U) -#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) - -/* - * TRIM_F (RO) - * - * default fine trim value - */ -#define PCFG_STATUS_TRIM_F_MASK (0x1FU) -#define PCFG_STATUS_TRIM_F_SHIFT (0U) -#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) - - - - -#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pdgo_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pdgo_regs.h deleted file mode 100644 index 5f4c0feeb19..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pdgo_regs.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDGO_H -#define HPM_PDGO_H - -typedef struct { - __W uint32_t DGO_TURNOFF; /* 0x0: trunoff control */ - __RW uint32_t DGO_RC32K_CFG; /* 0x4: RC32K CLOCK */ - __R uint8_t RESERVED0[1528]; /* 0x8 - 0x5FF: Reserved */ - __RW uint32_t DGO_GPR00; /* 0x600: Generic control 0 */ - __RW uint32_t DGO_GPR01; /* 0x604: Generic control 1 */ - __RW uint32_t DGO_GPR02; /* 0x608: Generic control 2 */ - __RW uint32_t DGO_GPR03; /* 0x60C: Generic control 3 */ - __R uint8_t RESERVED1[240]; /* 0x610 - 0x6FF: Reserved */ - __RW uint32_t DGO_CTR0; /* 0x700: control register 0 */ - __RW uint32_t DGO_CTR1; /* 0x704: control register 1 */ - __RW uint32_t DGO_CTR2; /* 0x708: control register 2 */ - __RW uint32_t DGO_CTR3; /* 0x70C: control register 3 */ - __RW uint32_t DGO_CTR4; /* 0x710: control register 4 */ -} PDGO_Type; - - -/* Bitfield definition for register: DGO_TURNOFF */ -/* - * COUNTER (WO) - * - * trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. - */ -#define PDGO_DGO_TURNOFF_COUNTER_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_TURNOFF_COUNTER_SHIFT (0U) -#define PDGO_DGO_TURNOFF_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK) -#define PDGO_DGO_TURNOFF_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT) - -/* Bitfield definition for register: DGO_RC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT (0U) -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: DGO_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR00_GPR_SHIFT (0U) -#define PDGO_DGO_GPR00_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK) -#define PDGO_DGO_GPR00_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: DGO_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR01_GPR_SHIFT (0U) -#define PDGO_DGO_GPR01_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK) -#define PDGO_DGO_GPR01_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: DGO_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR02_GPR_SHIFT (0U) -#define PDGO_DGO_GPR02_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK) -#define PDGO_DGO_GPR02_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: DGO_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR03_GPR_SHIFT (0U) -#define PDGO_DGO_GPR03_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK) -#define PDGO_DGO_GPR03_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: DGO_CTR0 */ -/* - * RETENTION (RW) - * - * dgo register status retenion - */ -#define PDGO_DGO_CTR0_RETENTION_MASK (0x10000UL) -#define PDGO_DGO_CTR0_RETENTION_SHIFT (16U) -#define PDGO_DGO_CTR0_RETENTION_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK) -#define PDGO_DGO_CTR0_RETENTION_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT) - -/* Bitfield definition for register: DGO_CTR1 */ -/* - * AOTO_SYS_WAKEUP (RW) - * - * software wakeup： 0 : wakeup once； 1：auto wakeup Continuously - */ -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK (0x80000000UL) -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT (31U) -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) - -/* - * WAKEUP_EN (RW) - * - * permit wakeup pin or software wakeup - */ -#define PDGO_DGO_CTR1_WAKEUP_EN_MASK (0x10000UL) -#define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT (16U) -#define PDGO_DGO_CTR1_WAKEUP_EN_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) -#define PDGO_DGO_CTR1_WAKEUP_EN_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) - -/* - * PIN_WAKEUP_STATUS (RO) - * - * wakeup pin status - */ -#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK (0x1U) -#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT (0U) -#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT) - -/* Bitfield definition for register: DGO_CTR2 */ -/* - * RESETN_PULLUP_DISABLE (RW) - * - * resetn pin pull up disable - */ -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK (0x1000000UL) -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT (24U) -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) - -/* - * WAKEUP_PULLDN_DISABLE (RW) - * - * wakeup pin pull down disable - */ -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK (0x10000UL) -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT (16U) -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) - -/* Bitfield definition for register: DGO_CTR3 */ -/* - * WAKEUP_COUNTER (RW) - * - * software wakeup counter - */ -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT (0U) -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) - -/* Bitfield definition for register: DGO_CTR4 */ -/* - * BANDGAP_LESS_POWER (RW) - * - * Banggap work in power save mode, banggap function normally - * 0: banggap works in high performance mode - * 1: banggap works in power saving mode - */ -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK (0x2U) -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT (1U) -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) - -/* - * BANDGAP_LP_MODE (RW) - * - * Banggap work in low power mode, banggap function limited - * 0: banggap works in normal mode - * 1: banggap works in low power mode - */ -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK (0x1U) -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT (0U) -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) - - - - -#endif /* HPM_PDGO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pgpr_regs.h deleted file mode 100644 index acf20cfecd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pgpr_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PGPR_H -#define HPM_PGPR_H - -typedef struct { - __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ - __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ - __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ - __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ - __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ - __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ - __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ - __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ - __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ - __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ - __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ - __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ - __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ - __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ - __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ - __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ -} PGPR_Type; - - -/* Bitfield definition for register: PMIC_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) -#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) -#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) -#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) -#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR04 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) -#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR05 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) -#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR06 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) -#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR07 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) -#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR08 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) -#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR09 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) -#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR10 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) -#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR11 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) -#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR12 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) -#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR13 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) -#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR14 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) -#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR15 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) -#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) - - - - -#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plb_regs.h deleted file mode 100644 index 163f31f8a7f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plb_regs.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLB_H -#define HPM_PLB_H - -typedef struct { - struct { - __RW uint32_t LOOKUP_TABLE[4]; /* 0x0 - 0xC: TYPE A CHN lookup_table 0 */ - __RW uint32_t SW_INJECT; /* 0x10: TYPE A CHN software inject */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - } TYPE_A[4]; - __R uint8_t RESERVED0[896]; /* 0x80 - 0x3FF: Reserved */ - struct { - __RW uint32_t LUT[2]; /* 0x400 - 0x404: TYPE B CHN lookup table 0 */ - __RW uint32_t CMP[4]; /* 0x408 - 0x414: TYPE B CHN data unit cmp0 */ - __RW uint32_t MODE; /* 0x418: TYPE B CHN mode ctrl */ - __RW uint32_t SW_INJECT; /* 0x41C: TYPE B CHN software inject */ - } TYPE_B[4]; -} PLB_Type; - - -/* Bitfield definition for register of struct array TYPE_A: 0 */ -/* - * LOOKUP_TABLE (RW) - * - * using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. - */ -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK (0xFFFFU) -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT (0U) -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) >> PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) - -/* Bitfield definition for register of struct array TYPE_A: SW_INJECT */ -/* - * SW_INJECT (RW) - * - * software can inject value to TYPEA's output - */ -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK (0xFU) -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT (0U) -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) >> PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: 0 */ -/* - * LOOKUP_TABLE (RW) - * - * lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in - */ -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK (0xFFFFFFFFUL) -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT (0U) -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) >> PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: 0 */ -/* - * CMP_VALUE (RW) - * - * cmp value, using as data unit operation - */ -#define PLB_TYPE_B_CMP_CMP_VALUE_MASK (0xFFFFFFFFUL) -#define PLB_TYPE_B_CMP_CMP_VALUE_SHIFT (0U) -#define PLB_TYPE_B_CMP_CMP_VALUE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) -#define PLB_TYPE_B_CMP_CMP_VALUE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) >> PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: MODE */ -/* - * OPT_SEL (RW) - * - * operation selection in data unit. - */ -#define PLB_TYPE_B_MODE_OPT_SEL_MASK (0x10000UL) -#define PLB_TYPE_B_MODE_OPT_SEL_SHIFT (16U) -#define PLB_TYPE_B_MODE_OPT_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OPT_SEL_SHIFT) & PLB_TYPE_B_MODE_OPT_SEL_MASK) -#define PLB_TYPE_B_MODE_OPT_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OPT_SEL_MASK) >> PLB_TYPE_B_MODE_OPT_SEL_SHIFT) - -/* - * OUT3_SEL (RW) - * - * trig out 3 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT3_SEL_MASK (0xF000U) -#define PLB_TYPE_B_MODE_OUT3_SEL_SHIFT (12U) -#define PLB_TYPE_B_MODE_OUT3_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT3_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) >> PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) - -/* - * OUT2_SEL (RW) - * - * trig out 2 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT2_SEL_MASK (0xF00U) -#define PLB_TYPE_B_MODE_OUT2_SEL_SHIFT (8U) -#define PLB_TYPE_B_MODE_OUT2_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT2_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) >> PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) - -/* - * OUT1_SEL (RW) - * - * trig out 1 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT1_SEL_MASK (0xF0U) -#define PLB_TYPE_B_MODE_OUT1_SEL_SHIFT (4U) -#define PLB_TYPE_B_MODE_OUT1_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT1_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) >> PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) - -/* - * OUT0_SEL (RW) - * - * trig out 0 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT0_SEL_MASK (0xFU) -#define PLB_TYPE_B_MODE_OUT0_SEL_SHIFT (0U) -#define PLB_TYPE_B_MODE_OUT0_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT0_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) >> PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: SW_INJECT */ -/* - * SOFTWARE_INJECT (RW) - * - * data unit value can be changed if program this register - */ -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK (0xFFFFFFFFUL) -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT (0U) -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) >> PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) - - - -/* LOOKUP_TABLE register group index macro definition */ -#define PLB_TYPE_A_LOOKUP_TABLE_0 (0UL) -#define PLB_TYPE_A_LOOKUP_TABLE_1 (1UL) -#define PLB_TYPE_A_LOOKUP_TABLE_2 (2UL) -#define PLB_TYPE_A_LOOKUP_TABLE_3 (3UL) - -/* TYPE_A register group index macro definition */ -#define PLB_TYPE_A_0 (0UL) -#define PLB_TYPE_A_1 (1UL) -#define PLB_TYPE_A_2 (2UL) -#define PLB_TYPE_A_3 (3UL) - -/* LUT register group index macro definition */ -#define PLB_TYPE_B_LUT_0 (0UL) -#define PLB_TYPE_B_LUT_1 (1UL) - -/* CMP register group index macro definition */ -#define PLB_TYPE_B_CMP_0 (0UL) -#define PLB_TYPE_B_CMP_1 (1UL) -#define PLB_TYPE_B_CMP_2 (2UL) -#define PLB_TYPE_B_CMP_3 (3UL) - -/* TYPE_B register group index macro definition */ -#define PLB_TYPE_B_0 (0UL) -#define PLB_TYPE_B_1 (1UL) -#define PLB_TYPE_B_2 (2UL) -#define PLB_TYPE_B_3 (3UL) - - -#endif /* HPM_PLB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plic_regs.h deleted file mode 100644 index c1ac3296bca..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plic_regs.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_H -#define HPM_PLIC_H - -typedef struct { - __RW uint32_t FEATURE; /* 0x0: Feature enable register */ - __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ - __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ - __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ - __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ - __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ - __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ - __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ - __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ - __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ - struct { - __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ - __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ - } TARGETINT[1]; - __R uint8_t RESERVED4[2088832]; /* 0x2080 - 0x1FFFFF: Reserved */ - struct { - __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ - __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ - __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ - __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ - __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ - } TARGETCONFIG[1]; -} PLIC_Type; - - -/* Bitfield definition for register: FEATURE */ -/* - * VECTORED (RW) - * - * Vector mode enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_VECTORED_MASK (0x2U) -#define PLIC_FEATURE_VECTORED_SHIFT (1U) -#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) -#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) - -/* - * PREEMPT (RW) - * - * Preemptive priority interrupt enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_PREEMPT_MASK (0x1U) -#define PLIC_FEATURE_PREEMPT_SHIFT (0U) -#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) -#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) - -/* Bitfield definition for register array: PRIORITY */ -/* - * PRIORITY (RW) - * - * Interrupt source priority. The valid range of this field is 0-7. - * 0: Never interrupt - * 1-7: Interrupt source priority. The larger the value, the higher the priority. - */ -#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) -#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) -#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) -#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) - -/* Bitfield definition for register array: PENDING */ -/* - * INTERRUPT (RW) - * - * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - */ -#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_PENDING_INTERRUPT_SHIFT (0U) -#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) -#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register array: TRIGGER */ -/* - * INTERRUPT (RO) - * - * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. - * 0: Level-triggered interrupt - * 1: Edge-triggered interrupt - */ -#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) -#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) - -/* Bitfield definition for register: NUMBER */ -/* - * NUM_TARGET (RO) - * - * The number of supported targets - */ -#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) -#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) -#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) - -/* - * NUM_INTERRUPT (RO) - * - * The number of supported interrupt sources - */ -#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) -#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) -#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INFO */ -/* - * MAX_PRIORITY (RO) - * - * The maximum priority supported - */ -#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) -#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) -#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) - -/* - * VERSION (RO) - * - * The version of the PLIC design - */ -#define PLIC_INFO_VERSION_MASK (0xFFFFU) -#define PLIC_INFO_VERSION_SHIFT (0U) -#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) - -/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ -/* - * INTERRUPT (RW) - * - * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - */ -#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) -#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ -/* - * THRESHOLD (RW) - * - * Interrupt priority threshold. - */ -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ -/* - * PRIORITY_PREEMPTED (RW) - * - * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - */ -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) - - - -/* PRIORITY register group index macro definition */ -#define PLIC_PRIORITY_PRIORITY1 (0UL) -#define PLIC_PRIORITY_PRIORITY2 (1UL) -#define PLIC_PRIORITY_PRIORITY3 (2UL) -#define PLIC_PRIORITY_PRIORITY4 (3UL) -#define PLIC_PRIORITY_PRIORITY5 (4UL) -#define PLIC_PRIORITY_PRIORITY6 (5UL) -#define PLIC_PRIORITY_PRIORITY7 (6UL) -#define PLIC_PRIORITY_PRIORITY8 (7UL) -#define PLIC_PRIORITY_PRIORITY9 (8UL) -#define PLIC_PRIORITY_PRIORITY10 (9UL) -#define PLIC_PRIORITY_PRIORITY11 (10UL) -#define PLIC_PRIORITY_PRIORITY12 (11UL) -#define PLIC_PRIORITY_PRIORITY13 (12UL) -#define PLIC_PRIORITY_PRIORITY14 (13UL) -#define PLIC_PRIORITY_PRIORITY15 (14UL) -#define PLIC_PRIORITY_PRIORITY16 (15UL) -#define PLIC_PRIORITY_PRIORITY17 (16UL) -#define PLIC_PRIORITY_PRIORITY18 (17UL) -#define PLIC_PRIORITY_PRIORITY19 (18UL) -#define PLIC_PRIORITY_PRIORITY20 (19UL) -#define PLIC_PRIORITY_PRIORITY21 (20UL) -#define PLIC_PRIORITY_PRIORITY22 (21UL) -#define PLIC_PRIORITY_PRIORITY23 (22UL) -#define PLIC_PRIORITY_PRIORITY24 (23UL) -#define PLIC_PRIORITY_PRIORITY25 (24UL) -#define PLIC_PRIORITY_PRIORITY26 (25UL) -#define PLIC_PRIORITY_PRIORITY27 (26UL) -#define PLIC_PRIORITY_PRIORITY28 (27UL) -#define PLIC_PRIORITY_PRIORITY29 (28UL) -#define PLIC_PRIORITY_PRIORITY30 (29UL) -#define PLIC_PRIORITY_PRIORITY31 (30UL) -#define PLIC_PRIORITY_PRIORITY32 (31UL) -#define PLIC_PRIORITY_PRIORITY33 (32UL) -#define PLIC_PRIORITY_PRIORITY34 (33UL) -#define PLIC_PRIORITY_PRIORITY35 (34UL) -#define PLIC_PRIORITY_PRIORITY36 (35UL) -#define PLIC_PRIORITY_PRIORITY37 (36UL) -#define PLIC_PRIORITY_PRIORITY38 (37UL) -#define PLIC_PRIORITY_PRIORITY39 (38UL) -#define PLIC_PRIORITY_PRIORITY40 (39UL) -#define PLIC_PRIORITY_PRIORITY41 (40UL) -#define PLIC_PRIORITY_PRIORITY42 (41UL) -#define PLIC_PRIORITY_PRIORITY43 (42UL) -#define PLIC_PRIORITY_PRIORITY44 (43UL) -#define PLIC_PRIORITY_PRIORITY45 (44UL) -#define PLIC_PRIORITY_PRIORITY46 (45UL) -#define PLIC_PRIORITY_PRIORITY47 (46UL) -#define PLIC_PRIORITY_PRIORITY48 (47UL) -#define PLIC_PRIORITY_PRIORITY49 (48UL) -#define PLIC_PRIORITY_PRIORITY50 (49UL) -#define PLIC_PRIORITY_PRIORITY51 (50UL) -#define PLIC_PRIORITY_PRIORITY52 (51UL) -#define PLIC_PRIORITY_PRIORITY53 (52UL) -#define PLIC_PRIORITY_PRIORITY54 (53UL) -#define PLIC_PRIORITY_PRIORITY55 (54UL) -#define PLIC_PRIORITY_PRIORITY56 (55UL) -#define PLIC_PRIORITY_PRIORITY57 (56UL) -#define PLIC_PRIORITY_PRIORITY58 (57UL) -#define PLIC_PRIORITY_PRIORITY59 (58UL) -#define PLIC_PRIORITY_PRIORITY60 (59UL) -#define PLIC_PRIORITY_PRIORITY61 (60UL) -#define PLIC_PRIORITY_PRIORITY62 (61UL) -#define PLIC_PRIORITY_PRIORITY63 (62UL) -#define PLIC_PRIORITY_PRIORITY64 (63UL) -#define PLIC_PRIORITY_PRIORITY65 (64UL) -#define PLIC_PRIORITY_PRIORITY66 (65UL) -#define PLIC_PRIORITY_PRIORITY67 (66UL) -#define PLIC_PRIORITY_PRIORITY68 (67UL) -#define PLIC_PRIORITY_PRIORITY69 (68UL) -#define PLIC_PRIORITY_PRIORITY70 (69UL) -#define PLIC_PRIORITY_PRIORITY71 (70UL) -#define PLIC_PRIORITY_PRIORITY72 (71UL) -#define PLIC_PRIORITY_PRIORITY73 (72UL) -#define PLIC_PRIORITY_PRIORITY74 (73UL) -#define PLIC_PRIORITY_PRIORITY75 (74UL) -#define PLIC_PRIORITY_PRIORITY76 (75UL) -#define PLIC_PRIORITY_PRIORITY77 (76UL) -#define PLIC_PRIORITY_PRIORITY78 (77UL) -#define PLIC_PRIORITY_PRIORITY79 (78UL) -#define PLIC_PRIORITY_PRIORITY80 (79UL) -#define PLIC_PRIORITY_PRIORITY81 (80UL) -#define PLIC_PRIORITY_PRIORITY82 (81UL) -#define PLIC_PRIORITY_PRIORITY83 (82UL) -#define PLIC_PRIORITY_PRIORITY84 (83UL) -#define PLIC_PRIORITY_PRIORITY85 (84UL) -#define PLIC_PRIORITY_PRIORITY86 (85UL) -#define PLIC_PRIORITY_PRIORITY87 (86UL) -#define PLIC_PRIORITY_PRIORITY88 (87UL) -#define PLIC_PRIORITY_PRIORITY89 (88UL) -#define PLIC_PRIORITY_PRIORITY90 (89UL) -#define PLIC_PRIORITY_PRIORITY91 (90UL) -#define PLIC_PRIORITY_PRIORITY92 (91UL) -#define PLIC_PRIORITY_PRIORITY93 (92UL) -#define PLIC_PRIORITY_PRIORITY94 (93UL) -#define PLIC_PRIORITY_PRIORITY95 (94UL) -#define PLIC_PRIORITY_PRIORITY96 (95UL) -#define PLIC_PRIORITY_PRIORITY97 (96UL) -#define PLIC_PRIORITY_PRIORITY98 (97UL) -#define PLIC_PRIORITY_PRIORITY99 (98UL) -#define PLIC_PRIORITY_PRIORITY100 (99UL) -#define PLIC_PRIORITY_PRIORITY101 (100UL) -#define PLIC_PRIORITY_PRIORITY102 (101UL) -#define PLIC_PRIORITY_PRIORITY103 (102UL) -#define PLIC_PRIORITY_PRIORITY104 (103UL) -#define PLIC_PRIORITY_PRIORITY105 (104UL) -#define PLIC_PRIORITY_PRIORITY106 (105UL) -#define PLIC_PRIORITY_PRIORITY107 (106UL) -#define PLIC_PRIORITY_PRIORITY108 (107UL) -#define PLIC_PRIORITY_PRIORITY109 (108UL) -#define PLIC_PRIORITY_PRIORITY110 (109UL) -#define PLIC_PRIORITY_PRIORITY111 (110UL) -#define PLIC_PRIORITY_PRIORITY112 (111UL) -#define PLIC_PRIORITY_PRIORITY113 (112UL) -#define PLIC_PRIORITY_PRIORITY114 (113UL) -#define PLIC_PRIORITY_PRIORITY115 (114UL) -#define PLIC_PRIORITY_PRIORITY116 (115UL) -#define PLIC_PRIORITY_PRIORITY117 (116UL) -#define PLIC_PRIORITY_PRIORITY118 (117UL) -#define PLIC_PRIORITY_PRIORITY119 (118UL) -#define PLIC_PRIORITY_PRIORITY120 (119UL) -#define PLIC_PRIORITY_PRIORITY121 (120UL) -#define PLIC_PRIORITY_PRIORITY122 (121UL) -#define PLIC_PRIORITY_PRIORITY123 (122UL) -#define PLIC_PRIORITY_PRIORITY124 (123UL) -#define PLIC_PRIORITY_PRIORITY125 (124UL) -#define PLIC_PRIORITY_PRIORITY126 (125UL) -#define PLIC_PRIORITY_PRIORITY127 (126UL) - -/* PENDING register group index macro definition */ -#define PLIC_PENDING_PENDING0 (0UL) -#define PLIC_PENDING_PENDING1 (1UL) -#define PLIC_PENDING_PENDING2 (2UL) -#define PLIC_PENDING_PENDING3 (3UL) - -/* TRIGGER register group index macro definition */ -#define PLIC_TRIGGER_TRIGGER0 (0UL) -#define PLIC_TRIGGER_TRIGGER1 (1UL) -#define PLIC_TRIGGER_TRIGGER2 (2UL) -#define PLIC_TRIGGER_TRIGGER3 (3UL) - -/* INTEN register group index macro definition */ -#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) -#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) -#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) -#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) - -/* TARGETINT register group index macro definition */ -#define PLIC_TARGETINT_TARGET0 (0UL) - -/* TARGETCONFIG register group index macro definition */ -#define PLIC_TARGETCONFIG_TARGET0 (0UL) - - -#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plic_sw_regs.h deleted file mode 100644 index 998dafa2d57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_plic_sw_regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_SW_H -#define HPM_PLIC_SW_H - -typedef struct { - __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ - __RW uint32_t PENDING; /* 0x1000: Pending status */ - __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ - __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ - __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ - __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ -} PLIC_SW_Type; - - -/* Bitfield definition for register: PENDING */ -/* - * INTERRUPT (RW) - * - * writing 1 to trigger software interrupt - */ -#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) -#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) -#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) -#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * INTERRUPT (RW) - * - * enable software interrupt - */ -#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) -#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) -#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) - - - - -#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pllctlv2_regs.h deleted file mode 100644 index b05379b8be8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pllctlv2_regs.h +++ /dev/null @@ -1,305 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLLCTLV2_H -#define HPM_PLLCTLV2_H - -typedef struct { - __RW uint32_t XTAL; /* 0x0: OSC configuration */ - __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ - struct { - __RW uint32_t MFI; /* 0x80: PLL0 multiple register */ - __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */ - __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */ - __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */ - __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */ - __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */ - __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */ - __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */ - __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */ - __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ - __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ - __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ - } PLL[2]; -} PLLCTLV2_Type; - - -/* Bitfield definition for register: XTAL */ -/* - * BUSY (RO) - * - * Busy flag - * 0: Oscillator is working or shutdown - * 1: Oscillator is changing status - */ -#define PLLCTLV2_XTAL_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_XTAL_BUSY_SHIFT (31U) -#define PLLCTLV2_XTAL_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTLV2_XTAL_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_XTAL_RESPONSE_SHIFT (29U) -#define PLLCTLV2_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTLV2_XTAL_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_XTAL_ENABLE_SHIFT (28U) -#define PLLCTLV2_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT) - -/* - * RAMP_TIME (RW) - * - * Rampup time of XTAL oscillator in cycles of RC24M clock - * 0: 0 cycle - * 1: 1 cycle - * 2: 2 cycle - * 1048575: 1048575 cycles - */ -#define PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) -#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) -#define PLLCTLV2_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK) -#define PLLCTLV2_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFI */ -/* - * BUSY (RO) - * - * Busy flag - * 0: PLL is stable or shutdown - * 1: PLL is changing status - */ -#define PLLCTLV2_PLL_MFI_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_MFI_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_MFI_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * PLL status - * 0: PLL is not stable - * 1: PLL is stable for use - */ -#define PLLCTLV2_PLL_MFI_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_MFI_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * PLL enable status - * 0: PLL is off - * 1: PLL is on - */ -#define PLLCTLV2_PLL_MFI_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_MFI_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT) - -/* - * MFI (RW) - * - * loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) - * 0-15: invalid - * 16: divide by 16 - * 17: divide by17 - * . . . - * 42: divide by 42 - * 43~:invalid - */ -#define PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) -#define PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) -#define PLLCTLV2_PLL_MFI_MFI_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK) -#define PLLCTLV2_PLL_MFI_MFI_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFN */ -/* - * MFN (RW) - * - * Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - */ -#define PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) -#define PLLCTLV2_PLL_MFN_MFN_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK) -#define PLLCTLV2_PLL_MFN_MFN_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFD */ -/* - * MFD (RW) - * - * Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - */ -#define PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) -#define PLLCTLV2_PLL_MFD_MFD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK) -#define PLLCTLV2_PLL_MFD_MFD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STEP */ -/* - * STEP (RW) - * - * Step of spread spectrum modulator. - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STEP_STEP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) -#define PLLCTLV2_PLL_SS_STEP_STEP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STOP */ -/* - * STOP (RW) - * - * Stop point of spread spectrum modulator - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STOP_STOP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) -#define PLLCTLV2_PLL_SS_STOP_STOP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) - -/* Bitfield definition for register of struct array PLL: CONFIG */ -/* - * SPREAD (RW) - * - * Enable spread spectrum function. This field supports changing during PLL running. - */ -#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK (0x100U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT (8U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) -#define PLLCTLV2_PLL_CONFIG_SPREAD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) - -/* - * REFSEL (RW) - * - * Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. - * 0: XTAL24M - * 1: IRC24M - */ -#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK (0x1U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT (0U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) -#define PLLCTLV2_PLL_CONFIG_REFSEL_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) - -/* Bitfield definition for register of struct array PLL: LOCKTIME */ -/* - * LOCKTIME (RW) - * - * Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - */ -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: STEPTIME */ -/* - * STEPTIME (RW) - * - * Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - */ -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: ADVANCED */ -/* - * SLOW (RW) - * - * Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. - * 0: fast lock enabled, lock time is 100us - * 1: fast lock disabled, lock time is 400us - */ -#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK (0x10000000UL) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT (28U) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) -#define PLLCTLV2_PLL_ADVANCED_SLOW_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither function - */ -#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK (0x1000000UL) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT (24U) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) -#define PLLCTLV2_PLL_ADVANCED_DITHER_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV0 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTLV2_PLL_DIV_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_DIV_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Divider response status - * 0: Divider is not stable - * 1: Divider is stable for use - */ -#define PLLCTLV2_PLL_DIV_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Divider enable status - * 0: Divider is off - * 1: Divider is on - */ -#define PLLCTLV2_PLL_DIV_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider factor, divider factor is DIV/5 + 1 - * 0: divide by 1 - * 1: divide by 1.2 - * 2: divide by 1.4 - * . . . - * 63: divide by 13.6 - */ -#define PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) -#define PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) -#define PLLCTLV2_PLL_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK) -#define PLLCTLV2_PLL_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT) - - - -/* DIV register group index macro definition */ -#define PLLCTLV2_PLL_DIV_DIV0 (0UL) -#define PLLCTLV2_PLL_DIV_DIV1 (1UL) -#define PLLCTLV2_PLL_DIV_DIV2 (2UL) - -/* PLL register group index macro definition */ -#define PLLCTLV2_PLL_PLL0 (0UL) -#define PLLCTLV2_PLL_PLL1 (1UL) - - -#endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ppor_regs.h deleted file mode 100644 index 32f5f6bcc61..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ppor_regs.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPOR_H -#define HPM_PPOR_H - -typedef struct { - __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ - __R uint32_t RESET_STATUS; /* 0x4: reset source status */ - __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ - __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ - __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */ - __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */ - __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ -} PPOR_Type; - - -/* Bitfield definition for register: RESET_FLAG */ -/* - * FLAG (W1C) - * - * reset reason of last hard reset, write 1 to clear each bit - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) -#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) -#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: RESET_STATUS */ -/* - * STATUS (RO) - * - * current status of reset sources - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) -#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_HOLD */ -/* - * HOLD (RW) - * - * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) -#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) -#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) - -/* Bitfield definition for register: RESET_ENABLE */ -/* - * ENABLE (RW) - * - * enable of reset sources - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) -#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) -#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) - -/* Bitfield definition for register: RESET_TYPE */ -/* - * TYPE (RW) - * - * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_TYPE_TYPE_SHIFT (0U) -#define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK) -#define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT) - -/* Bitfield definition for register: SOFTWARE_RESET */ -/* - * COUNTER (RW) - * - * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - */ -#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) -#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) -#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) -#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) - - - - -#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ptpc_regs.h deleted file mode 100644 index 5d9609c0c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_ptpc_regs.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PTPC_H -#define HPM_PTPC_H - -typedef struct { - struct { - __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ - __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ - __R uint32_t TIMEH; /* 0x8: timestamp high */ - __R uint32_t TIMEL; /* 0xC: timestamp low */ - __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ - __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ - __RW uint32_t ADDEND; /* 0x18: */ - __RW uint32_t TARH; /* 0x1C: */ - __RW uint32_t TARL; /* 0x20: */ - __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ - __RW uint32_t PPS_CTRL; /* 0x2C: */ - __R uint32_t CAPT_SNAPH; /* 0x30: */ - __RW uint32_t CAPT_SNAPL; /* 0x34: */ - __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ - } PTPC[2]; - __RW uint32_t TIME_SEL; /* 0x2000: */ - __W uint32_t INT_STS; /* 0x2004: */ - __RW uint32_t INT_EN; /* 0x2008: */ - __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ - __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ -} PTPC_Type; - - -/* Bitfield definition for register of struct array PTPC: CTRL0 */ -/* - * SUBSEC_DIGITAL_ROLLOVER (RW) - * - * Format for ns counter rollover, - * 1-digital, overflow time 1000000000/0x3B9ACA00 - * 0-binary, overflow time 0x7FFFFFFF - */ -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) - -/* - * CAPT_SNAP_KEEP (RW) - * - * set will keep capture snap till software read capt_snapl. - * If this bit is set, software should read capt_snaph first to avoid wrong result. - * If this bit is cleared, capture result will be updated at each capture event - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) - -/* - * CAPT_SNAP_POS_EN (RW) - * - * set will use posege of input capture signal to latch timestamp value - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) - -/* - * CAPT_SNAP_NEG_EN (RW) - * - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - -/* - * COMP_EN (RW) - * - * set to enable compare, will be cleared by HW when compare event triggered - */ -#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) -#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) -#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) -#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) - -/* - * UPDATE_TIMER (WO) - * - * update timer with +/- ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) - -/* - * INIT_TIMER (WO) - * - * initial timer with ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) -#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) - -/* - * FINE_COARSE_SEL (RW) - * - * 0: coarse update, ns counter add ss_incr[7:0] each clk - * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - */ -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - */ -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CTRL1 */ -/* - * SS_INCR (RW) - * - * constant value used to add ns counter; - * such as for 50MHz timer clock, set it to 8'd20 - */ -#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) -#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) -#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) -#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEH */ -/* - * TIMESTAMP_HIGH (RO) - * - */ -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEL */ -/* - * TIMESTAMP_LOW (RO) - * - */ -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ -/* - * SEC_UPDATE (RW) - * - * together with ts_updtl, used to initial or update timestamp - */ -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ -/* - * ADD_SUB (RW) - * - * 1 for sub; 0 for add, used only at update - */ -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) - -/* - * NS_UPDATE (RW) - * - */ -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: ADDEND */ -/* - * ADDEND (RW) - * - * used in fine update mode only - */ -#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) -#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) -#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARH */ -/* - * TARGET_TIME_HIGH (RW) - * - * used for generate compare signal if enabled - */ -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARL */ -/* - * TARGET_TIME_LOW (RW) - * - */ -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ -/* - * PPS_CTRL (RW) - * - */ -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ -/* - * CAPT_SNAP_HIGH (RO) - * - * take snapshot for input capture signal, at pos or neg or both; - * the result can be kept or updated at each event according to cfg0.bit8 - */ -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ -/* - * CAPT_SNAP_LOW (RW) - * - */ -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) - -/* Bitfield definition for register: TIME_SEL */ -/* - * CAN3_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) - -/* - * CAN2_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) - -/* - * CAN1_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) - -/* - * CAN0_TIME_SEL (RW) - * - * set to use ptpc1 for canx - * clr to use ptpc0 for canx - */ -#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * COMP_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) -#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) -#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) -#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) -#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * COMP_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) -#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) -#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) -#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) -#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: PTPC_CAN_TS_SEL */ -/* - * TSU_TBIN3_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) - -/* - * TSU_TBIN2_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) - -/* - * TSU_TBIN1_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) - -/* - * TSU_TBIN0_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) - - - -/* PTPC register group index macro definition */ -#define PTPC_PTPC_0 (0UL) -#define PTPC_PTPC_1 (1UL) - - -#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pwm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pwm_regs.h deleted file mode 100644 index 1e73954216f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_pwm_regs.h +++ /dev/null @@ -1,948 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PWM_H -#define HPM_PWM_H - -typedef struct { - __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ - union { - __RW uint32_t STA; /* 0x4: Counter start register */ - }; - union { - __RW uint32_t RLD; /* 0x8: Counter reload register */ - }; - union { - __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ - }; - __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ - __RW uint32_t FRCMD; /* 0x78: Force output mode register */ - __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ - __RW uint32_t CHCFG[24]; /* 0x80 - 0xDC: Output channel configure register */ - __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */ - __RW uint32_t GCR; /* 0xF0: Global control register */ - __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ - __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ - __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */ - __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */ - __R uint32_t CNT; /* 0x170: Counter */ - __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ - __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */ - __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */ - __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ - __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ - __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ - __W uint32_t SR; /* 0x220: Status register */ - __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ - __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ - __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ - __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ -} PWM_Type; - - -/* Bitfield definition for register: UNLK */ -/* - * SHUNLK (RW) - * - * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, - * otherwise the shadow registers can not be written. - */ -#define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) -#define PWM_UNLK_SHUNLK_SHIFT (0U) -#define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) -#define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * XSTA (RW) - * - * pwm timer counter extended start point, should back to this value after reach xrld - */ -#define PWM_STA_XSTA_MASK (0xF0000000UL) -#define PWM_STA_XSTA_SHIFT (28U) -#define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) -#define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) - -/* - * STA (RW) - * - * pwm timer counter start value - * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - */ -#define PWM_STA_STA_MASK (0xFFFFFF0UL) -#define PWM_STA_STA_SHIFT (4U) -#define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) -#define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * XRLD (RW) - * - * timeout counter extended reload point, counter will reload to xsta after reach this point - */ -#define PWM_RLD_XRLD_MASK (0xF0000000UL) -#define PWM_RLD_XRLD_SHIFT (28U) -#define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) -#define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) - -/* - * RLD (RW) - * - * pwm timer counter reload value - */ -#define PWM_RLD_RLD_MASK (0xFFFFFF0UL) -#define PWM_RLD_RLD_SHIFT (4U) -#define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) -#define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) - -/* Bitfield definition for register: 0 */ -/* - * XCMP (RW) - * - * extended counter compare value - */ -#define PWM_CMP_XCMP_MASK (0xF0000000UL) -#define PWM_CMP_XCMP_SHIFT (28U) -#define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) -#define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) - -/* - * CMP (RW) - * - * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, - * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - */ -#define PWM_CMP_CMP_MASK (0xFFFFFF0UL) -#define PWM_CMP_CMP_SHIFT (4U) -#define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) -#define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) - -/* - * CMPHLF (RW) - * - * half clock counter compare value - */ -#define PWM_CMP_CMPHLF_MASK (0x8U) -#define PWM_CMP_CMPHLF_SHIFT (3U) -#define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) -#define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) - -/* - * CMPJIT (RW) - * - * jitter counter compare value - */ -#define PWM_CMP_CMPJIT_MASK (0x7U) -#define PWM_CMP_CMPJIT_SHIFT (0U) -#define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) -#define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) - -/* Bitfield definition for register: FRCMD */ -/* - * FRCMD (RW) - * - * 2bit for each PWM output channel (0-7); - * 00: force output 0 - * 01: force output 1 - * 10: output highz - * 11: no force - */ -#define PWM_FRCMD_FRCMD_MASK (0xFFFFU) -#define PWM_FRCMD_FRCMD_SHIFT (0U) -#define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) -#define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) - -/* Bitfield definition for register: SHLK */ -/* - * SHLK (RW) - * - * write 1 to lock all shawdow register, write access is not permitted - */ -#define PWM_SHLK_SHLK_MASK (0x80000000UL) -#define PWM_SHLK_SHLK_SHIFT (31U) -#define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) -#define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) - -/* Bitfield definition for register array: CHCFG */ -/* - * CMPSELEND (RW) - * - * assign the last comparator for this output channel - */ -#define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) -#define PWM_CHCFG_CMPSELEND_SHIFT (24U) -#define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) -#define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) - -/* - * CMPSELBEG (RW) - * - * assign the first comparator for this output channel - */ -#define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) -#define PWM_CHCFG_CMPSELBEG_SHIFT (16U) -#define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) -#define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) - -/* - * OUTPOL (RW) - * - * output polarity, set to 1 will invert the output - */ -#define PWM_CHCFG_OUTPOL_MASK (0x2U) -#define PWM_CHCFG_OUTPOL_SHIFT (1U) -#define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) -#define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * FAULTI3EN (RW) - * - * 1- enable the internal fault input 3 - */ -#define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) -#define PWM_GCR_FAULTI3EN_SHIFT (31U) -#define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) -#define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) - -/* - * FAULTI2EN (RW) - * - * 1- enable the internal fault input 2 - */ -#define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) -#define PWM_GCR_FAULTI2EN_SHIFT (30U) -#define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) -#define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) - -/* - * FAULTI1EN (RW) - * - * 1- enable the internal fault input 1 - */ -#define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) -#define PWM_GCR_FAULTI1EN_SHIFT (29U) -#define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) -#define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) - -/* - * FAULTI0EN (RW) - * - * 1- enable the internal fault input 0 - */ -#define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) -#define PWM_GCR_FAULTI0EN_SHIFT (28U) -#define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) -#define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) - -/* - * DEBUGFAULT (RW) - * - * 1- enable debug mode output protection - */ -#define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) -#define PWM_GCR_DEBUGFAULT_SHIFT (27U) -#define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) -#define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) - -/* - * FRCPOL (RW) - * - * polarity of input pwm_force, - * 1- active low - * 0- active high - */ -#define PWM_GCR_FRCPOL_MASK (0x4000000UL) -#define PWM_GCR_FRCPOL_SHIFT (26U) -#define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) -#define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) - -/* - * HWSHDWEDG (RW) - * - * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. - * This bit assign its which edge is used as compare shadow register hardware load event. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) -#define PWM_GCR_HWSHDWEDG_SHIFT (24U) -#define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) -#define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) - -/* - * CMPSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load comparator shadow registers - */ -#define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) -#define PWM_GCR_CMPSHDWSEL_SHIFT (19U) -#define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) -#define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) - -/* - * FAULTRECEDG (RW) - * - * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. - * This bit assign its effective edge of fault recover trigger. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) -#define PWM_GCR_FAULTRECEDG_SHIFT (18U) -#define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) -#define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) - -/* - * FAULTRECHWSEL (RW) - * - * Selec one of the 24 comparators as fault output recover trigger. - */ -#define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) -#define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) -#define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) -#define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) - -/* - * FAULTE1EN (RW) - * - * 1- enable the external fault input 1 - */ -#define PWM_GCR_FAULTE1EN_MASK (0x1000U) -#define PWM_GCR_FAULTE1EN_SHIFT (12U) -#define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) -#define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) - -/* - * FAULTE0EN (RW) - * - * 1- enable the external fault input 0 - */ -#define PWM_GCR_FAULTE0EN_MASK (0x800U) -#define PWM_GCR_FAULTE0EN_SHIFT (11U) -#define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) -#define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) - -/* - * FAULTEXPOL (RW) - * - * external fault polarity - * 1-active low - * 0-active high - */ -#define PWM_GCR_FAULTEXPOL_MASK (0x600U) -#define PWM_GCR_FAULTEXPOL_SHIFT (9U) -#define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) -#define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) - -/* - * RLDSYNCEN (RW) - * - * 1- pwm timer counter reset to reload value (rld) by synci is enabled - */ -#define PWM_GCR_RLDSYNCEN_MASK (0x100U) -#define PWM_GCR_RLDSYNCEN_SHIFT (8U) -#define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) -#define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) - -/* - * CEN (RW) - * - * 1- enable the pwm timer counter - * 0- stop the pwm timer counter - */ -#define PWM_GCR_CEN_MASK (0x80U) -#define PWM_GCR_CEN_SHIFT (7U) -#define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) -#define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) - -/* - * FAULTCLR (RW) - * - * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. - * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - */ -#define PWM_GCR_FAULTCLR_MASK (0x40U) -#define PWM_GCR_FAULTCLR_SHIFT (6U) -#define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) -#define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) - -/* - * XRLDSYNCEN (RW) - * - * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - */ -#define PWM_GCR_XRLDSYNCEN_MASK (0x20U) -#define PWM_GCR_XRLDSYNCEN_SHIFT (5U) -#define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) -#define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) - -/* - * TIMERRESET (RW) - * - * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear - */ -#define PWM_GCR_TIMERRESET_MASK (0x8U) -#define PWM_GCR_TIMERRESET_SHIFT (3U) -#define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) -#define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) - -/* - * FRCTIME (WO) - * - * This bit field select the force effective time - * 00: force immediately - * 01: force at main counter reload time - * 10: force at FRCSYNCI - * 11: no force - */ -#define PWM_GCR_FRCTIME_MASK (0x6U) -#define PWM_GCR_FRCTIME_SHIFT (1U) -#define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) -#define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) - -/* - * SWFRC (RW) - * - * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - */ -#define PWM_GCR_SWFRC_MASK (0x1U) -#define PWM_GCR_SWFRC_SHIFT (0U) -#define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) -#define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) - -/* Bitfield definition for register: SHCR */ -/* - * FRCSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - */ -#define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) -#define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) -#define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) -#define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) - -/* - * CNTSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - */ -#define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) -#define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) -#define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) -#define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) - -/* - * CNTSHDWUPT (RW) - * - * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) -#define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) -#define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) -#define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) - -/* - * SHLKEN (RW) - * - * 1- enable shadow registers lock feature, - * 0- disable shadow registers lock, shlk bit will always be 0 - */ -#define PWM_SHCR_SHLKEN_MASK (0x1U) -#define PWM_SHCR_SHLKEN_SHIFT (0U) -#define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) -#define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) - -/* Bitfield definition for register array: CAPPOS */ -/* - * CAPPOS (RO) - * - * counter value captured at input posedge - */ -#define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) -#define PWM_CAPPOS_CAPPOS_SHIFT (4U) -#define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNT_XCNT_MASK (0xF0000000UL) -#define PWM_CNT_XCNT_SHIFT (28U) -#define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNT_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNT_CNT_SHIFT (4U) -#define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CAPNEG */ -/* - * CAPNEG (RO) - * - * counter value captured at input signal falling edge - */ -#define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define PWM_CAPNEG_CAPNEG_SHIFT (0U) -#define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register: CNTCOPY */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) -#define PWM_CNTCOPY_XCNT_SHIFT (28U) -#define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNTCOPY_CNT_SHIFT (4U) -#define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) - -/* Bitfield definition for register array: PWMCFG */ -/* - * OEN (RW) - * - * PWM output enable - * 1- output is enabled - * 0- output is disabled - */ -#define PWM_PWMCFG_OEN_MASK (0x10000000UL) -#define PWM_PWMCFG_OEN_SHIFT (28U) -#define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) -#define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) - -/* - * FRCSHDWUPT (RW) - * - * This bitfield select when the FRCMD shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) -#define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) -#define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) -#define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) - -/* - * FAULTMODE (RW) - * - * This bitfield defines the PWM output status when fault condition happen - * 00: force output 0 - * 01: force output 1 - * 1x: output highz - */ -#define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) -#define PWM_PWMCFG_FAULTMODE_SHIFT (24U) -#define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) -#define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) - -/* - * FAULTRECTIME (RW) - * - * This bitfield select when to recover PWM output after fault condition removed. - * 00: immediately - * 01: after pwm timer counter reload time - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after software write faultclr bit in GCR register - */ -#define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) -#define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) -#define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) -#define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) - -/* - * FRCSRCSEL (RW) - * - * Select sources for force output - * 0- force output is enabled when FRCI assert - * 1- force output is enabled by software write swfrc to 1 - */ -#define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) -#define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) -#define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) -#define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) - -/* - * PAIR (RW) - * - * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. - * 0- PWM output is in indepandent mode. - */ -#define PWM_PWMCFG_PAIR_MASK (0x100000UL) -#define PWM_PWMCFG_PAIR_SHIFT (20U) -#define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) -#define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) - -/* - * DEADAREA (RW) - * - * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. - * Note: user should configure pair bit and this bitfield before PWM output is enabled. - */ -#define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) -#define PWM_PWMCFG_DEADAREA_SHIFT (0U) -#define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) -#define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * FAULTF (W1C) - * - * fault condition flag - */ -#define PWM_SR_FAULTF_MASK (0x8000000UL) -#define PWM_SR_FAULTF_SHIFT (27U) -#define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) -#define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) - -/* - * XRLDF (W1C) - * - * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - */ -#define PWM_SR_XRLDF_MASK (0x4000000UL) -#define PWM_SR_XRLDF_SHIFT (26U) -#define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) -#define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) - -/* - * HALFRLDF (W1C) - * - * half reload flag, this flag set when cnt count to rld/2 - */ -#define PWM_SR_HALFRLDF_MASK (0x2000000UL) -#define PWM_SR_HALFRLDF_SHIFT (25U) -#define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) -#define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) - -/* - * RLDF (W1C) - * - * reload flag, this flag set when cnt count to rld value or when SYNCI assert - */ -#define PWM_SR_RLDF_MASK (0x1000000UL) -#define PWM_SR_RLDF_SHIFT (24U) -#define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) -#define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) - -/* - * CMPFX (W1C) - * - * comparator output compare or input capture flag - */ -#define PWM_SR_CMPFX_MASK (0xFFFFFFUL) -#define PWM_SR_CMPFX_SHIFT (0U) -#define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) -#define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * FAULTIRQE (RW) - * - * fault condition interrupt enable - */ -#define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) -#define PWM_IRQEN_FAULTIRQE_SHIFT (27U) -#define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) -#define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) - -/* - * XRLDIRQE (RW) - * - * extended reload flag interrupt enable - */ -#define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) -#define PWM_IRQEN_XRLDIRQE_SHIFT (26U) -#define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) -#define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) - -/* - * HALFRLDIRQE (RW) - * - * half reload flag interrupt enable - */ -#define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) -#define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) -#define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) -#define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) - -/* - * RLDIRQE (RW) - * - * reload flag interrupt enable - */ -#define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) -#define PWM_IRQEN_RLDIRQE_SHIFT (24U) -#define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) -#define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) - -/* - * CMPIRQEX (RW) - * - * comparator output compare or input capture flag interrupt enable - */ -#define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) -#define PWM_IRQEN_CMPIRQEX_SHIFT (0U) -#define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) -#define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * FAULTEN (RW) - * - * fault condition DMA request enable - */ -#define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) -#define PWM_DMAEN_FAULTEN_SHIFT (27U) -#define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) -#define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) - -/* - * XRLDEN (RW) - * - * extended reload flag DMA request enable - */ -#define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) -#define PWM_DMAEN_XRLDEN_SHIFT (26U) -#define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) -#define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) - -/* - * HALFRLDEN (RW) - * - * half reload flag DMA request enable - */ -#define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) -#define PWM_DMAEN_HALFRLDEN_SHIFT (25U) -#define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) -#define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) - -/* - * RLDEN (RW) - * - * reload flag DMA request enable - */ -#define PWM_DMAEN_RLDEN_MASK (0x1000000UL) -#define PWM_DMAEN_RLDEN_SHIFT (24U) -#define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) -#define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) - -/* - * CMPENX (RW) - * - * comparator output compare or input capture flag DMA request enable - */ -#define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) -#define PWM_DMAEN_CMPENX_SHIFT (0U) -#define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) -#define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) - -/* Bitfield definition for register array: CMPCFG */ -/* - * XCNTCMPEN (RW) - * - * This bitfield enable the comparator to compare xcmp with xcnt. - */ -#define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) -#define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) -#define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) -#define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) - -/* - * CMPSHDWUPT (RW) - * - * This bitfield select when the comparator shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) -#define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) -#define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) -#define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) - -/* - * CMPMODE (RW) - * - * comparator mode - * 0- output compare mode - * 1- input capture mode - */ -#define PWM_CMPCFG_CMPMODE_MASK (0x2U) -#define PWM_CMPCFG_CMPMODE_SHIFT (1U) -#define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) -#define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) - - - -/* CMP register group index macro definition */ -#define PWM_CMP_0 (0UL) -#define PWM_CMP_1 (1UL) -#define PWM_CMP_2 (2UL) -#define PWM_CMP_3 (3UL) -#define PWM_CMP_4 (4UL) -#define PWM_CMP_5 (5UL) -#define PWM_CMP_6 (6UL) -#define PWM_CMP_7 (7UL) -#define PWM_CMP_8 (8UL) -#define PWM_CMP_9 (9UL) -#define PWM_CMP_10 (10UL) -#define PWM_CMP_11 (11UL) -#define PWM_CMP_12 (12UL) -#define PWM_CMP_13 (13UL) -#define PWM_CMP_14 (14UL) -#define PWM_CMP_15 (15UL) -#define PWM_CMP_16 (16UL) -#define PWM_CMP_17 (17UL) -#define PWM_CMP_18 (18UL) -#define PWM_CMP_19 (19UL) -#define PWM_CMP_20 (20UL) -#define PWM_CMP_21 (21UL) -#define PWM_CMP_22 (22UL) -#define PWM_CMP_23 (23UL) - -/* CHCFG register group index macro definition */ -#define PWM_CHCFG_0 (0UL) -#define PWM_CHCFG_1 (1UL) -#define PWM_CHCFG_2 (2UL) -#define PWM_CHCFG_3 (3UL) -#define PWM_CHCFG_4 (4UL) -#define PWM_CHCFG_5 (5UL) -#define PWM_CHCFG_6 (6UL) -#define PWM_CHCFG_7 (7UL) -#define PWM_CHCFG_8 (8UL) -#define PWM_CHCFG_9 (9UL) -#define PWM_CHCFG_10 (10UL) -#define PWM_CHCFG_11 (11UL) -#define PWM_CHCFG_12 (12UL) -#define PWM_CHCFG_13 (13UL) -#define PWM_CHCFG_14 (14UL) -#define PWM_CHCFG_15 (15UL) -#define PWM_CHCFG_16 (16UL) -#define PWM_CHCFG_17 (17UL) -#define PWM_CHCFG_18 (18UL) -#define PWM_CHCFG_19 (19UL) -#define PWM_CHCFG_20 (20UL) -#define PWM_CHCFG_21 (21UL) -#define PWM_CHCFG_22 (22UL) -#define PWM_CHCFG_23 (23UL) - -/* CAPPOS register group index macro definition */ -#define PWM_CAPPOS_0 (0UL) -#define PWM_CAPPOS_1 (1UL) -#define PWM_CAPPOS_2 (2UL) -#define PWM_CAPPOS_3 (3UL) -#define PWM_CAPPOS_4 (4UL) -#define PWM_CAPPOS_5 (5UL) -#define PWM_CAPPOS_6 (6UL) -#define PWM_CAPPOS_7 (7UL) -#define PWM_CAPPOS_8 (8UL) -#define PWM_CAPPOS_9 (9UL) -#define PWM_CAPPOS_10 (10UL) -#define PWM_CAPPOS_11 (11UL) -#define PWM_CAPPOS_12 (12UL) -#define PWM_CAPPOS_13 (13UL) -#define PWM_CAPPOS_14 (14UL) -#define PWM_CAPPOS_15 (15UL) -#define PWM_CAPPOS_16 (16UL) -#define PWM_CAPPOS_17 (17UL) -#define PWM_CAPPOS_18 (18UL) -#define PWM_CAPPOS_19 (19UL) -#define PWM_CAPPOS_20 (20UL) -#define PWM_CAPPOS_21 (21UL) -#define PWM_CAPPOS_22 (22UL) -#define PWM_CAPPOS_23 (23UL) - -/* CAPNEG register group index macro definition */ -#define PWM_CAPNEG_0 (0UL) -#define PWM_CAPNEG_1 (1UL) -#define PWM_CAPNEG_2 (2UL) -#define PWM_CAPNEG_3 (3UL) -#define PWM_CAPNEG_4 (4UL) -#define PWM_CAPNEG_5 (5UL) -#define PWM_CAPNEG_6 (6UL) -#define PWM_CAPNEG_7 (7UL) -#define PWM_CAPNEG_8 (8UL) -#define PWM_CAPNEG_9 (9UL) -#define PWM_CAPNEG_10 (10UL) -#define PWM_CAPNEG_11 (11UL) -#define PWM_CAPNEG_12 (12UL) -#define PWM_CAPNEG_13 (13UL) -#define PWM_CAPNEG_14 (14UL) -#define PWM_CAPNEG_15 (15UL) -#define PWM_CAPNEG_16 (16UL) -#define PWM_CAPNEG_17 (17UL) -#define PWM_CAPNEG_18 (18UL) -#define PWM_CAPNEG_19 (19UL) -#define PWM_CAPNEG_20 (20UL) -#define PWM_CAPNEG_21 (21UL) -#define PWM_CAPNEG_22 (22UL) -#define PWM_CAPNEG_23 (23UL) - -/* PWMCFG register group index macro definition */ -#define PWM_PWMCFG_0 (0UL) -#define PWM_PWMCFG_1 (1UL) -#define PWM_PWMCFG_2 (2UL) -#define PWM_PWMCFG_3 (3UL) -#define PWM_PWMCFG_4 (4UL) -#define PWM_PWMCFG_5 (5UL) -#define PWM_PWMCFG_6 (6UL) -#define PWM_PWMCFG_7 (7UL) - -/* CMPCFG register group index macro definition */ -#define PWM_CMPCFG_CMPCFG0 (0UL) -#define PWM_CMPCFG_1 (1UL) -#define PWM_CMPCFG_2 (2UL) -#define PWM_CMPCFG_3 (3UL) -#define PWM_CMPCFG_4 (4UL) -#define PWM_CMPCFG_5 (5UL) -#define PWM_CMPCFG_6 (6UL) -#define PWM_CMPCFG_7 (7UL) -#define PWM_CMPCFG_8 (8UL) -#define PWM_CMPCFG_9 (9UL) -#define PWM_CMPCFG_10 (10UL) -#define PWM_CMPCFG_11 (11UL) -#define PWM_CMPCFG_12 (12UL) -#define PWM_CMPCFG_13 (13UL) -#define PWM_CMPCFG_14 (14UL) -#define PWM_CMPCFG_15 (15UL) -#define PWM_CMPCFG_16 (16UL) -#define PWM_CMPCFG_17 (17UL) -#define PWM_CMPCFG_18 (18UL) -#define PWM_CMPCFG_19 (19UL) -#define PWM_CMPCFG_20 (20UL) -#define PWM_CMPCFG_21 (21UL) -#define PWM_CMPCFG_22 (22UL) -#define PWM_CMPCFG_23 (23UL) - - -#endif /* HPM_PWM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_qeiv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_qeiv2_regs.h deleted file mode 100644 index f0bfafa1b8f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_qeiv2_regs.h +++ /dev/null @@ -1,1991 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEIV2_H -#define HPM_QEIV2_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t PHIDX; /* 0xC: Phase index register */ - __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __RW uint32_t ZCMP; /* 0x18: Z comparator */ - __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ - __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ - __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ - struct { - __RW uint32_t Z; /* 0x30: Z counter */ - __R uint32_t PH; /* 0x34: Phase counter */ - __RW uint32_t SPD; /* 0x38: Speed counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */ - __RW uint32_t ZCMP2; /* 0x80: Z comparator */ - __RW uint32_t PHCMP2; /* 0x84: Phase comparator */ - __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */ - __RW uint32_t MATCH_CFG; /* 0x8C: */ - __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */ - __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */ - __RW uint32_t QEI_CFG; /* 0x100: qei config register */ - __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */ - __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */ - __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */ - __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */ - __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */ - __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */ - __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */ - __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */ - __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */ - __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */ - __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */ - __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */ - __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */ - __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */ - __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */ - __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */ - __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */ - __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */ - __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */ - __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */ - __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */ - __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */ - __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */ - __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */ - __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */ - __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */ - __R uint8_t RESERVED4[136]; /* 0x178 - 0x1FF: Reserved */ - __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */ - __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */ - __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */ - __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */ - __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */ - __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */ - __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */ - __R uint8_t RESERVED6[4]; /* 0x21C - 0x21F: Reserved */ - __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */ - __R uint8_t RESERVED7[12]; /* 0x224 - 0x22F: Reserved */ - __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */ - __R uint8_t RESERVED8[4]; /* 0x234 - 0x237: Reserved */ - __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */ - __R uint8_t RESERVED9[4]; /* 0x23C - 0x23F: Reserved */ - __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */ - __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: uvw_pos0_cfg */ - __R uint8_t RESERVED10[16]; /* 0x270 - 0x27F: Reserved */ - __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */ - __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */ - __RW uint32_t POSITION; /* 0x288: position */ - __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */ - __R uint32_t ANGLE; /* 0x290: */ - __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */ -} QEIV2_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define QEIV2_CR_READ_MASK (0x80000000UL) -#define QEIV2_CR_READ_SHIFT (31U) -#define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK) -#define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT) - -/* - * ZCNTCFG (RW) - * - * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * 0- zcnt will increment or decrement when Z input assert - */ -#define QEIV2_CR_ZCNTCFG_MASK (0x400000UL) -#define QEIV2_CR_ZCNTCFG_SHIFT (22U) -#define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK) -#define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT) - -/* - * PHCALIZ (RW) - * - * 1- phcnt will set to phidx when Z input assert(for abz digital signsl) - */ -#define QEIV2_CR_PHCALIZ_MASK (0x200000UL) -#define QEIV2_CR_PHCALIZ_SHIFT (21U) -#define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK) -#define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT) - -/* - * Z_ONLY_EN (RW) - * - * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) - */ -#define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL) -#define QEIV2_CR_Z_ONLY_EN_SHIFT (20U) -#define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK) -#define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT) - -/* - * H2FDIR0 (RW) - * - */ -#define QEIV2_CR_H2FDIR0_MASK (0x80000UL) -#define QEIV2_CR_H2FDIR0_SHIFT (19U) -#define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK) -#define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT) - -/* - * H2FDIR1 (RW) - * - */ -#define QEIV2_CR_H2FDIR1_MASK (0x40000UL) -#define QEIV2_CR_H2FDIR1_SHIFT (18U) -#define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK) -#define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT) - -/* - * H2RDIR0 (RW) - * - */ -#define QEIV2_CR_H2RDIR0_MASK (0x20000UL) -#define QEIV2_CR_H2RDIR0_SHIFT (17U) -#define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK) -#define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT) - -/* - * H2RDIR1 (RW) - * - */ -#define QEIV2_CR_H2RDIR1_MASK (0x10000UL) -#define QEIV2_CR_H2RDIR1_SHIFT (16U) -#define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK) -#define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT) - -/* - * PAUSEPOS (RW) - * - * 1- pause position output valid when PAUSE assert - */ -#define QEIV2_CR_PAUSEPOS_MASK (0x8000U) -#define QEIV2_CR_PAUSEPOS_SHIFT (15U) -#define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK) -#define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT) - -/* - * PAUSESPD (RW) - * - * 1- pause spdcnt when PAUSE assert - */ -#define QEIV2_CR_PAUSESPD_MASK (0x4000U) -#define QEIV2_CR_PAUSESPD_SHIFT (14U) -#define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK) -#define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT) - -/* - * PAUSEPH (RW) - * - * 1- pause phcnt when PAUSE assert - */ -#define QEIV2_CR_PAUSEPH_MASK (0x2000U) -#define QEIV2_CR_PAUSEPH_SHIFT (13U) -#define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK) -#define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT) - -/* - * PAUSEZ (RW) - * - * 1- pause zcnt when PAUSE assert - */ -#define QEIV2_CR_PAUSEZ_MASK (0x1000U) -#define QEIV2_CR_PAUSEZ_SHIFT (12U) -#define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK) -#define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT) - -/* - * HFDIR0 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - */ -#define QEIV2_CR_HFDIR0_MASK (0x800U) -#define QEIV2_CR_HFDIR0_SHIFT (11U) -#define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK) -#define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT) - -/* - * HFDIR1 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - */ -#define QEIV2_CR_HFDIR1_MASK (0x400U) -#define QEIV2_CR_HFDIR1_SHIFT (10U) -#define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK) -#define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT) - -/* - * HRDIR0 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - */ -#define QEIV2_CR_HRDIR0_MASK (0x200U) -#define QEIV2_CR_HRDIR0_SHIFT (9U) -#define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK) -#define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT) - -/* - * HRDIR1 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - */ -#define QEIV2_CR_HRDIR1_MASK (0x100U) -#define QEIV2_CR_HRDIR1_SHIFT (8U) -#define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK) -#define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT) - -/* - * FAULTPOS (RW) - * - */ -#define QEIV2_CR_FAULTPOS_MASK (0x40U) -#define QEIV2_CR_FAULTPOS_SHIFT (6U) -#define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK) -#define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - */ -#define QEIV2_CR_SNAPEN_MASK (0x20U) -#define QEIV2_CR_SNAPEN_SHIFT (5U) -#define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK) -#define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - */ -#define QEIV2_CR_RSTCNT_MASK (0x10U) -#define QEIV2_CR_RSTCNT_SHIFT (4U) -#define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK) -#define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT) - -/* - * RD_SEL (RW) - * - * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, - * width_snap0,width_snap1, timer_snap0, timer_snap1) - * 0 : same as hpm1000/500/500s; - * 1: use width for position; use timer for angle - */ -#define QEIV2_CR_RD_SEL_MASK (0x8U) -#define QEIV2_CR_RD_SEL_SHIFT (3U) -#define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK) -#define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT) - -/* - * ENCTYP (RW) - * - * 000-abz; 001-pd; 010-ud; 011-UVW(hal) - * 100-single A; 101-single sin; 110: sin&cos - */ -#define QEIV2_CR_ENCTYP_MASK (0x7U) -#define QEIV2_CR_ENCTYP_SHIFT (0U) -#define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK) -#define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * PHMAX (RW) - * - * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - */ -#define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL) -#define QEIV2_PHCFG_PHMAX_SHIFT (0U) -#define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK) -#define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL) -#define QEIV2_WDGCFG_WDGEN_SHIFT (31U) -#define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK) -#define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT) - -/* - * WDOG_CFG (RW) - * - * define as stop if phase_cnt change is less than it - * if 0, then each change of phase_cnt will clear wdog counter; - * if 2, then phase_cnt change larger than 2 will clear wdog counter - */ -#define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL) -#define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U) -#define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK) -#define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL) -#define QEIV2_WDGCFG_WDGTO_SHIFT (0U) -#define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK) -#define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: PHIDX */ -/* - * PHIDX (RW) - * - * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - */ -#define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL) -#define QEIV2_PHIDX_PHIDX_SHIFT (0U) -#define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK) -#define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGFEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL) -#define QEIV2_TRGOEN_WDGFEN_SHIFT (31U) -#define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK) -#define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- enable trigger output when homef flag set - */ -#define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL) -#define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U) -#define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK) -#define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- enable trigger output when poscmpf flag set - */ -#define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL) -#define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U) -#define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK) -#define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- enable trigger output when zphf flag set - */ -#define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL) -#define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U) -#define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK) -#define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT) - -/* - * ZMISSFEN (RW) - * - */ -#define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL) -#define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U) -#define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK) -#define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT) - -/* - * WIDTHTMFEN (RW) - * - */ -#define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL) -#define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U) -#define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) -#define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) - -/* - * POS2CMPFEN (RW) - * - */ -#define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL) -#define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U) -#define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK) -#define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT) - -/* - * DIRCHGFEN (RW) - * - */ -#define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL) -#define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U) -#define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK) -#define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT) - -/* - * CYCLE0FEN (RW) - * - */ -#define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL) -#define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U) -#define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK) -#define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT) - -/* - * CYCLE1FEN (RW) - * - */ -#define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL) -#define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U) -#define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK) -#define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT) - -/* - * PULSE0FEN (RW) - * - */ -#define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL) -#define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U) -#define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK) -#define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT) - -/* - * PULSE1FEN (RW) - * - */ -#define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL) -#define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U) -#define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK) -#define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT) - -/* - * HOME2FEN (RW) - * - */ -#define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL) -#define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U) -#define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK) -#define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT) - -/* - * FAULTFEN (RW) - * - */ -#define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL) -#define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U) -#define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK) -#define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGFEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define QEIV2_READEN_WDGFEN_MASK (0x80000000UL) -#define QEIV2_READEN_WDGFEN_SHIFT (31U) -#define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK) -#define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- load counters to their read registers when homef flag set - */ -#define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL) -#define QEIV2_READEN_HOMEFEN_SHIFT (30U) -#define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK) -#define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- load counters to their read registers when poscmpf flag set - */ -#define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL) -#define QEIV2_READEN_POSCMPFEN_SHIFT (29U) -#define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK) -#define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- load counters to their read registers when zphf flag set - */ -#define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL) -#define QEIV2_READEN_ZPHFEN_SHIFT (28U) -#define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK) -#define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT) - -/* - * ZMISSFEN (RW) - * - */ -#define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL) -#define QEIV2_READEN_ZMISSFEN_SHIFT (27U) -#define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK) -#define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT) - -/* - * WIDTHTMFEN (RW) - * - */ -#define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL) -#define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U) -#define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK) -#define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT) - -/* - * POS2CMPFEN (RW) - * - */ -#define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL) -#define QEIV2_READEN_POS2CMPFEN_SHIFT (25U) -#define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK) -#define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT) - -/* - * DIRCHGFEN (RW) - * - */ -#define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL) -#define QEIV2_READEN_DIRCHGFEN_SHIFT (24U) -#define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK) -#define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT) - -/* - * CYCLE0FEN (RW) - * - */ -#define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL) -#define QEIV2_READEN_CYCLE0FEN_SHIFT (23U) -#define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK) -#define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT) - -/* - * CYCLE1FEN (RW) - * - */ -#define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL) -#define QEIV2_READEN_CYCLE1FEN_SHIFT (22U) -#define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK) -#define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT) - -/* - * PULSE0FEN (RW) - * - */ -#define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL) -#define QEIV2_READEN_PULSE0FEN_SHIFT (21U) -#define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK) -#define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT) - -/* - * PULSE1FEN (RW) - * - */ -#define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL) -#define QEIV2_READEN_PULSE1FEN_SHIFT (20U) -#define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK) -#define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT) - -/* - * HOME2FEN (RW) - * - */ -#define QEIV2_READEN_HOME2FEN_MASK (0x80000UL) -#define QEIV2_READEN_HOME2FEN_SHIFT (19U) -#define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK) -#define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT) - -/* - * FAULTFEN (RW) - * - */ -#define QEIV2_READEN_FAULTFEN_MASK (0x40000UL) -#define QEIV2_READEN_FAULTFEN_SHIFT (18U) -#define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK) -#define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT) - -/* Bitfield definition for register: ZCMP */ -/* - * ZCMP (RW) - * - * zcnt postion compare value - */ -#define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) -#define QEIV2_ZCMP_ZCMP_SHIFT (0U) -#define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK) -#define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT) - -/* Bitfield definition for register: PHCMP */ -/* - * PHCMP (RW) - * - * phcnt position compare value - */ -#define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL) -#define QEIV2_PHCMP_PHCMP_SHIFT (0U) -#define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK) -#define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT) - -/* Bitfield definition for register: SPDCMP */ -/* - * SPDCMP (RW) - * - * spdcnt position compare value - */ -#define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) -#define QEIV2_SPDCMP_SPDCMP_SHIFT (0U) -#define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK) -#define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGFEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL) -#define QEIV2_DMAEN_WDGFEN_SHIFT (31U) -#define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK) -#define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- generate dma request when homef flag set - */ -#define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL) -#define QEIV2_DMAEN_HOMEFEN_SHIFT (30U) -#define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK) -#define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- generate dma request when poscmpf flag set - */ -#define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL) -#define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U) -#define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK) -#define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- generate dma request when zphf flag set - */ -#define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL) -#define QEIV2_DMAEN_ZPHFEN_SHIFT (28U) -#define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK) -#define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT) - -/* - * ZMISSFEN (RW) - * - */ -#define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL) -#define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U) -#define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK) -#define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT) - -/* - * WIDTHTMFEN (RW) - * - */ -#define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL) -#define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U) -#define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK) -#define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT) - -/* - * POS2CMPFEN (RW) - * - */ -#define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL) -#define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U) -#define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK) -#define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT) - -/* - * DIRCHGFEN (RW) - * - */ -#define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL) -#define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U) -#define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK) -#define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT) - -/* - * CYCLE0FEN (RW) - * - */ -#define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL) -#define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U) -#define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK) -#define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT) - -/* - * CYCLE1FEN (RW) - * - */ -#define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL) -#define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U) -#define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK) -#define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT) - -/* - * PULSE0FEN (RW) - * - */ -#define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL) -#define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U) -#define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK) -#define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT) - -/* - * PULSE1FEN (RW) - * - */ -#define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL) -#define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U) -#define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK) -#define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT) - -/* - * HOME2FEN (RW) - * - */ -#define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL) -#define QEIV2_DMAEN_HOME2FEN_SHIFT (19U) -#define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK) -#define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT) - -/* - * FAULTFEN (RW) - * - */ -#define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL) -#define QEIV2_DMAEN_FAULTFEN_SHIFT (18U) -#define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK) -#define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog flag - */ -#define QEIV2_SR_WDGF_MASK (0x80000000UL) -#define QEIV2_SR_WDGF_SHIFT (31U) -#define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK) -#define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT) - -/* - * HOMEF (RW) - * - * home flag - */ -#define QEIV2_SR_HOMEF_MASK (0x40000000UL) -#define QEIV2_SR_HOMEF_SHIFT (30U) -#define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK) -#define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT) - -/* - * POSCMPF (RW) - * - * postion compare match flag - */ -#define QEIV2_SR_POSCMPF_MASK (0x20000000UL) -#define QEIV2_SR_POSCMPF_SHIFT (29U) -#define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK) -#define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT) - -/* - * ZPHF (RW) - * - * z input flag - */ -#define QEIV2_SR_ZPHF_MASK (0x10000000UL) -#define QEIV2_SR_ZPHF_SHIFT (28U) -#define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK) -#define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT) - -/* - * ZMISSF (RW) - * - */ -#define QEIV2_SR_ZMISSF_MASK (0x8000000UL) -#define QEIV2_SR_ZMISSF_SHIFT (27U) -#define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK) -#define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT) - -/* - * WIDTHTMF (RW) - * - */ -#define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL) -#define QEIV2_SR_WIDTHTMF_SHIFT (26U) -#define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK) -#define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT) - -/* - * POS2CMPF (RW) - * - */ -#define QEIV2_SR_POS2CMPF_MASK (0x2000000UL) -#define QEIV2_SR_POS2CMPF_SHIFT (25U) -#define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK) -#define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT) - -/* - * DIRCHGF (RW) - * - */ -#define QEIV2_SR_DIRCHGF_MASK (0x1000000UL) -#define QEIV2_SR_DIRCHGF_SHIFT (24U) -#define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK) -#define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT) - -/* - * CYCLE0F (RW) - * - */ -#define QEIV2_SR_CYCLE0F_MASK (0x800000UL) -#define QEIV2_SR_CYCLE0F_SHIFT (23U) -#define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK) -#define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT) - -/* - * CYCLE1F (RW) - * - */ -#define QEIV2_SR_CYCLE1F_MASK (0x400000UL) -#define QEIV2_SR_CYCLE1F_SHIFT (22U) -#define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK) -#define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT) - -/* - * PULSE0F (RW) - * - */ -#define QEIV2_SR_PULSE0F_MASK (0x200000UL) -#define QEIV2_SR_PULSE0F_SHIFT (21U) -#define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK) -#define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT) - -/* - * PULSE1F (RW) - * - */ -#define QEIV2_SR_PULSE1F_MASK (0x100000UL) -#define QEIV2_SR_PULSE1F_SHIFT (20U) -#define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK) -#define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT) - -/* - * HOME2F (RW) - * - */ -#define QEIV2_SR_HOME2F_MASK (0x80000UL) -#define QEIV2_SR_HOME2F_SHIFT (19U) -#define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK) -#define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT) - -/* - * FAULTF (RW) - * - */ -#define QEIV2_SR_FAULTF_MASK (0x40000UL) -#define QEIV2_SR_FAULTF_SHIFT (18U) -#define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK) -#define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt when wdg flag set - */ -#define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL) -#define QEIV2_IRQEN_WDGIE_SHIFT (31U) -#define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK) -#define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT) - -/* - * HOMEIE (RW) - * - * 1- generate interrupt when homef flag set - */ -#define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL) -#define QEIV2_IRQEN_HOMEIE_SHIFT (30U) -#define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK) -#define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT) - -/* - * POSCMPIE (RW) - * - * 1- generate interrupt when poscmpf flag set - */ -#define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL) -#define QEIV2_IRQEN_POSCMPIE_SHIFT (29U) -#define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK) -#define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT) - -/* - * ZPHIE (RW) - * - * 1- generate interrupt when zphf flag set - */ -#define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL) -#define QEIV2_IRQEN_ZPHIE_SHIFT (28U) -#define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK) -#define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT) - -/* - * ZMISSE (RW) - * - */ -#define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL) -#define QEIV2_IRQEN_ZMISSE_SHIFT (27U) -#define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK) -#define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT) - -/* - * WIDTHTME (RW) - * - */ -#define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL) -#define QEIV2_IRQEN_WIDTHTME_SHIFT (26U) -#define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK) -#define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT) - -/* - * POS2CMPE (RW) - * - */ -#define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL) -#define QEIV2_IRQEN_POS2CMPE_SHIFT (25U) -#define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK) -#define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT) - -/* - * DIRCHGE (RW) - * - */ -#define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL) -#define QEIV2_IRQEN_DIRCHGE_SHIFT (24U) -#define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK) -#define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT) - -/* - * CYCLE0E (RW) - * - */ -#define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL) -#define QEIV2_IRQEN_CYCLE0E_SHIFT (23U) -#define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK) -#define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT) - -/* - * CYCLE1E (RW) - * - */ -#define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL) -#define QEIV2_IRQEN_CYCLE1E_SHIFT (22U) -#define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK) -#define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT) - -/* - * PULSE0E (RW) - * - */ -#define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL) -#define QEIV2_IRQEN_PULSE0E_SHIFT (21U) -#define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK) -#define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT) - -/* - * PULSE1E (RW) - * - */ -#define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL) -#define QEIV2_IRQEN_PULSE1E_SHIFT (20U) -#define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK) -#define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT) - -/* - * HOME2E (RW) - * - */ -#define QEIV2_IRQEN_HOME2E_MASK (0x80000UL) -#define QEIV2_IRQEN_HOME2E_SHIFT (19U) -#define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK) -#define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT) - -/* - * FAULTE (RW) - * - */ -#define QEIV2_IRQEN_FAULTE_MASK (0x40000UL) -#define QEIV2_IRQEN_FAULTE_SHIFT (18U) -#define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK) -#define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: Z */ -/* - * ZCNT (RW) - * - * zcnt value - */ -#define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) -#define QEIV2_COUNT_Z_ZCNT_SHIFT (0U) -#define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK) -#define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: PH */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL) -#define QEIV2_COUNT_PH_DIR_SHIFT (30U) -#define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL) -#define QEIV2_COUNT_PH_ASTAT_SHIFT (26U) -#define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT) - -/* - * BSTAT (RO) - * - * 1- b input is high - * 0- b input is low - */ -#define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL) -#define QEIV2_COUNT_PH_BSTAT_SHIFT (25U) -#define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT) - -/* - * PHCNT (RO) - * - * phcnt value - */ -#define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) -#define QEIV2_COUNT_PH_PHCNT_SHIFT (0U) -#define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: SPD */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL) -#define QEIV2_COUNT_SPD_DIR_SHIFT (31U) -#define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL) -#define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U) -#define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT) - -/* - * BSTAT (RW) - * - * 1- b input is high - * 0- b input is low - */ -#define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL) -#define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U) -#define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK) -#define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT) - -/* - * SPDCNT (RO) - * - * spdcnt value - */ -#define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) -#define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U) -#define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TMRCNT (RO) - * - * 32 bit free run timer - */ -#define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) -#define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U) -#define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT) - -/* Bitfield definition for register: ZCMP2 */ -/* - * ZCMP2 (RW) - * - */ -#define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL) -#define QEIV2_ZCMP2_ZCMP2_SHIFT (0U) -#define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK) -#define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT) - -/* Bitfield definition for register: PHCMP2 */ -/* - * PHCMP2 (RW) - * - */ -#define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL) -#define QEIV2_PHCMP2_PHCMP2_SHIFT (0U) -#define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK) -#define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT) - -/* Bitfield definition for register: SPDCMP2 */ -/* - * SPDCMP2 (RW) - * - */ -#define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL) -#define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U) -#define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK) -#define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT) - -/* Bitfield definition for register: MATCH_CFG */ -/* - * ZCMPDIS (RW) - * - * 1- postion compare not include zcnt - */ -#define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL) -#define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U) -#define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) -#define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) - -/* - * DIRCMPDIS (RW) - * - * 1- postion compare not include rotation direction - */ -#define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL) -#define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U) -#define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) -#define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) - -/* - * DIRCMP (RW) - * - * 0- position compare need positive rotation - * 1- position compare need negative rotation - */ -#define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL) -#define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U) -#define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK) -#define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT) - -/* - * SPDCMPDIS (RW) - * - */ -#define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL) -#define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U) -#define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) -#define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) - -/* - * PHASE_MATCH_DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) - -/* - * POS_MATCH_DIR (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL) -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U) -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) - -/* - * POS_MATCH_OPT (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL) -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U) -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) - -/* - * ZCMP2DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U) -#define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U) -#define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) -#define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) - -/* - * DIRCMP2DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U) -#define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U) -#define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) -#define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) - -/* - * DIRCMP2 (RW) - * - */ -#define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U) -#define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U) -#define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK) -#define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT) - -/* - * SPDCMP2DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U) -#define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U) -#define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) -#define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) - -/* - * PHASE_MATCH_DIS2 (RW) - * - */ -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) - -/* - * POS_MATCH2_DIR (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U) -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U) -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) - -/* - * POS_MATCH2_OPT (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U) -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U) -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) - -/* Bitfield definition for register array: FILT_CFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL) -#define QEIV2_FILT_CFG_OUTINV_SHIFT (16U) -#define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK) -#define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stable low mode; - * 111-stable high mode - */ -#define QEIV2_FILT_CFG_MODE_MASK (0xE000U) -#define QEIV2_FILT_CFG_MODE_SHIFT (13U) -#define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK) -#define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U) -#define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U) -#define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK) -#define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT) - -/* - * FILTLEN (RW) - * - * This bitfields defines the filter counter length. - */ -#define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU) -#define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U) -#define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK) -#define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT) - -/* Bitfield definition for register: QEI_CFG */ -/* - * SPEED_DIR_CHG_EN (RW) - * - * clear counter if detect direction change - */ -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U) -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U) -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) - -/* - * UVW_POS_OPT0 (RW) - * - * set to output next area position for QEO use; - * clr to output exact point position for MMC use - */ -#define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U) -#define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U) -#define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) -#define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) - -/* - * NEGEDGE_EN (RW) - * - * bit4: negedge enable - * bit3: posedge enable - * bit2: W in hal enable - * bit1: signal b(or V in hal) enable - * bit0: signal a(or U in hal) enable - * such as: - * 01001: use posedge A - * 11010: use both edge of signal B - * 11111: use both edge of all HAL siganls - */ -#define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U) -#define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U) -#define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) -#define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) - -/* - * POSIDGE_EN (RW) - * - */ -#define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U) -#define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U) -#define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) -#define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) - -/* - * SIGZ_EN (RW) - * - */ -#define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U) -#define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U) -#define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK) -#define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT) - -/* - * SIGB_EN (RW) - * - */ -#define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U) -#define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U) -#define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK) -#define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT) - -/* - * SIGA_EN (RW) - * - */ -#define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U) -#define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U) -#define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK) -#define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT) - -/* Bitfield definition for register: PULSE0_NUM */ -/* - * PULSE0_NUM (RW) - * - * for speed detection, will count the cycle number for configed pulse_num - */ -#define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U) -#define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) -#define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) - -/* Bitfield definition for register: PULSE1_NUM */ -/* - * PULSE1_NUM (RW) - * - */ -#define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U) -#define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) -#define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) - -/* Bitfield definition for register: CYCLE0_CNT */ -/* - * CYCLE0_CNT (RO) - * - */ -#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U) -#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE0PULSE_CNT */ -/* - * CYCLE0PULSE_CNT (RO) - * - */ -#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U) -#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE1_CNT */ -/* - * CYCLE1_CNT (RO) - * - */ -#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U) -#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE1PULSE_CNT */ -/* - * CYCLE1PULSE_CNT (RO) - * - */ -#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U) -#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE0_SNAP0 */ -/* - * CYCLE0_SNAP0 (RO) - * - */ -#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U) -#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT) - -/* Bitfield definition for register: CYCLE0_SNAP1 */ -/* - * CYCLE0_SNAP1 (RO) - * - */ -#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U) -#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT) - -/* Bitfield definition for register: CYCLE1_SNAP0 */ -/* - * CYCLE1_SNAP0 (RO) - * - */ -#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U) -#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT) - -/* Bitfield definition for register: CYCLE1_SNAP1 */ -/* - * CYCLE1_SNAP1 (RO) - * - */ -#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U) -#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT) - -/* Bitfield definition for register: CYCLE0_NUM */ -/* - * CYCLE0_NUM (RW) - * - */ -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U) -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) - -/* Bitfield definition for register: CYCLE1_NUM */ -/* - * CYCLE1_NUM (RW) - * - */ -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U) -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) - -/* Bitfield definition for register: PULSE0_CNT */ -/* - * PULSE0_CNT (RO) - * - */ -#define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U) -#define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT) - -/* Bitfield definition for register: PULSE0CYCLE_CNT */ -/* - * PULSE0CYCLE_CNT (RO) - * - */ -#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U) -#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT) - -/* Bitfield definition for register: PULSE1_CNT */ -/* - * PULSE1_CNT (RO) - * - */ -#define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U) -#define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT) - -/* Bitfield definition for register: PULSE1CYCLE_CNT */ -/* - * PULSE1CYCLE_CNT (RO) - * - */ -#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U) -#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT) - -/* Bitfield definition for register: PULSE0_SNAP0 */ -/* - * PULSE0_SNAP0 (RO) - * - */ -#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U) -#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE0CYCLE_SNAP0 */ -/* - * PULSE0CYCLE_SNAP0 (RO) - * - */ -#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U) -#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE0_SNAP1 */ -/* - * PULSE0_SNAP1 (RO) - * - */ -#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U) -#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT) - -/* Bitfield definition for register: PULSE0CYCLE_SNAP1 */ -/* - * PULSE0CYCLE_SNAP1 (RO) - * - */ -#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U) -#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT) - -/* Bitfield definition for register: PULSE1_SNAP0 */ -/* - * PULSE1_SNAP0 (RO) - * - */ -#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U) -#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE1CYCLE_SNAP0 */ -/* - * PULSE1CYCLE_SNAP0 (RO) - * - */ -#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U) -#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE1_SNAP1 */ -/* - * PULSE1_SNAP1 (RO) - * - */ -#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U) -#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT) - -/* Bitfield definition for register: PULSE1CYCLE_SNAP1 */ -/* - * PULSE1CYCLE_SNAP1 (RO) - * - */ -#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U) -#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT) - -/* Bitfield definition for register: ADCX_CFG0 */ -/* - * X_ADCSEL (RW) - * - */ -#define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U) -#define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U) -#define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) -#define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) - -/* - * X_ADC_ENABLE (RW) - * - */ -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U) -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U) -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) - -/* - * X_CHAN (RW) - * - */ -#define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU) -#define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U) -#define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK) -#define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT) - -/* Bitfield definition for register: ADCX_CFG1 */ -/* - * X_PARAM1 (RW) - * - */ -#define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL) -#define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U) -#define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) -#define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) - -/* - * X_PARAM0 (RW) - * - */ -#define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU) -#define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U) -#define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) -#define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) - -/* Bitfield definition for register: ADCX_CFG2 */ -/* - * X_OFFSET (RW) - * - */ -#define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL) -#define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U) -#define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) -#define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) - -/* Bitfield definition for register: ADCY_CFG0 */ -/* - * Y_ADCSEL (RW) - * - */ -#define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U) -#define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U) -#define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) -#define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) - -/* - * Y_ADC_ENABLE (RW) - * - */ -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U) -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U) -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) - -/* - * Y_CHAN (RW) - * - */ -#define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU) -#define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U) -#define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) -#define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) - -/* Bitfield definition for register: ADCY_CFG1 */ -/* - * Y_PARAM1 (RW) - * - */ -#define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL) -#define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U) -#define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) -#define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) - -/* - * Y_PARAM0 (RW) - * - */ -#define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU) -#define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U) -#define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) -#define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) - -/* Bitfield definition for register: ADCY_CFG2 */ -/* - * Y_OFFSET (RW) - * - */ -#define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL) -#define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U) -#define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) -#define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: CAL_CFG */ -/* - * XY_DELAY (RW) - * - * valid x/y delay, larger than this delay will be treated as invalid data. - * Default 1.25us@200MHz; max 80ms; - */ -#define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL) -#define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U) -#define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK) -#define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT) - -/* Bitfield definition for register: PHASE_PARAM */ -/* - * PHASE_PARAM (RW) - * - */ -#define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL) -#define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U) -#define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) -#define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) - -/* Bitfield definition for register: POS_THRESHOLD */ -/* - * POS_THRESHOLD (RW) - * - */ -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL) -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U) -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) - -/* Bitfield definition for register array: UVW_POS */ -/* - * UVW_POS0 (RW) - * - */ -#define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL) -#define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U) -#define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK) -#define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT) - -/* Bitfield definition for register array: UVW_POS_CFG */ -/* - * POS_EN (RW) - * - */ -#define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U) -#define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U) -#define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK) -#define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT) - -/* - * U_POS_SEL (RW) - * - */ -#define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U) -#define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U) -#define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) -#define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) - -/* - * V_POS_SEL (RW) - * - */ -#define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU) -#define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U) -#define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) -#define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) - -/* - * W_POS_SEL (RW) - * - */ -#define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U) -#define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U) -#define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) -#define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) - -/* Bitfield definition for register: PHASE_CNT */ -/* - * PHASE_CNT (RW) - * - */ -#define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U) -#define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) -#define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) - -/* Bitfield definition for register: PHASE_UPDATE */ -/* - * INC (WO) - * - * set to add value to phase_cnt - */ -#define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL) -#define QEIV2_PHASE_UPDATE_INC_SHIFT (31U) -#define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK) -#define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT) - -/* - * DEC (WO) - * - * set to minus value from phase_cnt(set inc and dec same time willl act inc) - */ -#define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL) -#define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U) -#define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK) -#define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT) - -/* - * VALUE (WO) - * - * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation - */ -#define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL) -#define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U) -#define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK) -#define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT) - -/* Bitfield definition for register: POSITION */ -/* - * POSITION (RW) - * - */ -#define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL) -#define QEIV2_POSITION_POSITION_SHIFT (0U) -#define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK) -#define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT) - -/* Bitfield definition for register: POSITION_UPDATE */ -/* - * INC (WO) - * - * set to add value to position - */ -#define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL) -#define QEIV2_POSITION_UPDATE_INC_SHIFT (31U) -#define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK) -#define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT) - -/* - * DEC (WO) - * - * set to minus value from position(set inc and dec same time willl act inc) - */ -#define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL) -#define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U) -#define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK) -#define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT) - -/* - * VALUE (WO) - * - * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation - */ -#define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL) -#define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U) -#define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK) -#define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT) - -/* Bitfield definition for register: ANGLE */ -/* - * ANGLE (RO) - * - */ -#define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL) -#define QEIV2_ANGLE_ANGLE_SHIFT (0U) -#define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT) - -/* Bitfield definition for register: POS_TIMEOUT */ -/* - * ENABLE (RW) - * - * enable position timeout feature, if timeout, send valid again - */ -#define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL) -#define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U) -#define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK) -#define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT) - -/* - * TIMEOUT (RW) - * - * postion timeout value - */ -#define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL) -#define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U) -#define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) -#define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) - - - -/* COUNT register group index macro definition */ -#define QEIV2_COUNT_CURRENT (0UL) -#define QEIV2_COUNT_READ (1UL) -#define QEIV2_COUNT_SNAP0 (2UL) -#define QEIV2_COUNT_SNAP1 (3UL) - -/* FILT_CFG register group index macro definition */ -#define QEIV2_FILT_CFG_FILT_CFG_A (0UL) -#define QEIV2_FILT_CFG_FILT_CFG_B (1UL) -#define QEIV2_FILT_CFG_FILT_CFG_Z (2UL) -#define QEIV2_FILT_CFG_FILT_CFG_H (3UL) -#define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL) -#define QEIV2_FILT_CFG_FILT_CFG_F (5UL) - -/* UVW_POS register group index macro definition */ -#define QEIV2_UVW_POS_UVW_POS0 (0UL) -#define QEIV2_UVW_POS_UVW_POS1 (1UL) -#define QEIV2_UVW_POS_UVW_POS2 (2UL) -#define QEIV2_UVW_POS_UVW_POS3 (3UL) -#define QEIV2_UVW_POS_UVW_POS4 (4UL) -#define QEIV2_UVW_POS_UVW_POS5 (5UL) - -/* UVW_POS_CFG register group index macro definition */ -#define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL) -#define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL) -#define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL) -#define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL) -#define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL) -#define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL) - - -#endif /* HPM_QEIV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_qeo_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_qeo_regs.h deleted file mode 100644 index 50c3cf9c3fa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_qeo_regs.h +++ /dev/null @@ -1,1065 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEO_H -#define HPM_QEO_H - -typedef struct { - struct { - __RW uint32_t MODE; /* 0x0: analog waves mode */ - __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */ - __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */ - __RW uint32_t VD_VQ_INJECT[3]; /* 0x14 - 0x1C: wave0 vd vq inject value */ - __W uint32_t VD_VQ_LOAD; /* 0x20: load wave0/1/2 vd vq value */ - __RW uint32_t AMPLITUDE[3]; /* 0x24 - 0x2C: wave0 amplitude */ - __RW uint32_t MID_POINT[3]; /* 0x30 - 0x38: wave0 output middle point offset */ - struct { - __RW uint32_t MIN; /* 0x3C: wave0 low area limit value */ - __RW uint32_t MAX; /* 0x40: wave0 high area limit value */ - } LIMIT[3]; - __RW uint32_t DEADZONE_SHIFT[3]; /* 0x54 - 0x5C: deadzone_shifter_wave0 */ - } WAVE; - struct { - __RW uint32_t MODE; /* 0x60: wave_a/b/z output mode */ - __RW uint32_t RESOLUTION; /* 0x64: resolution of wave_a/b/z */ - __RW uint32_t PHASE_SHIFT[3]; /* 0x68 - 0x70: wave_a phase shifter */ - __RW uint32_t LINE_WIDTH; /* 0x74: Two-phase orthogonality wave 1/4 period */ - __RW uint32_t WDOG_WIDTH; /* 0x78: wdog width of qeo */ - __W uint32_t POSTION_SYNC; /* 0x7C: sync abz owned postion */ - } ABZ; - struct { - __RW uint32_t MODE; /* 0x80: pwm mode */ - __RW uint32_t RESOLUTION; /* 0x84: resolution of pwm */ - __RW uint32_t PHASE_SHIFT[4]; /* 0x88 - 0x94: pwm_a phase shifter */ - __RW uint32_t PHASE_TABLE[24]; /* 0x98 - 0xF4: pwm_phase_table 0 */ - } PWM; - __RW uint32_t POSTION_SOFTWARE; /* 0xF8: softwave inject postion */ - __RW uint32_t POSTION_SEL; /* 0xFC: select softwave inject postion */ - __R uint32_t STATUS; /* 0x100: qeo status */ - __R uint32_t DEBUG0; /* 0x104: qeo debug 0 */ - __R uint32_t DEBUG1; /* 0x108: qeo debug 1 */ - __R uint32_t DEBUG2; /* 0x10C: qeo debug 2 */ - __R uint32_t DEBUG3; /* 0x110: qeo debug 3 */ -} QEO_Type; - - -/* Bitfield definition for register of struct WAVE: MODE */ -/* - * WAVE2_ABOVE_MAX_LIMIT (RW) - * - * wave2 above max limit mode. - * 0: output 0xffff. - * 1: output 0x0. - * 2: output as level_max_limit2.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL) -#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U) -#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) - -/* - * WAVE2_HIGH_AREA1_LIMIT (RW) - * - * wave2 high area1 limit mode. - * 0: output 0xffff. - * 1: output as level_max_limit2.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL) -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U) -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) - -/* - * WAVE2_HIGH_AREA0_LIMIT (RW) - * - * wave2 high area0 limit mode. - * 0: output 0xffff. - * 1: output as level_max_limit2.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL) -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U) -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) - -/* - * WAVE2_LOW_AREA1_LIMIT (RW) - * - * wave2 low area1 limit mode. - * 0: output 0. - * 1: output as level_min_limit2.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL) -#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U) -#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) - -/* - * WAVE2_LOW_AREA0_LIMIT (RW) - * - * wave2 low area0 limit mode. - * 0: output 0. - * 1: output as level_min_limit2.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL) -#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U) -#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) - -/* - * WAVE2_BELOW_MIN_LIMIT (RW) - * - * wave2 below min limit mode. - * 0: output 0. - * 1: output 0xffff. - * 2: output as level_min_limit2.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL) -#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U) -#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) - -/* - * WAVE1_ABOVE_MAX_LIMIT (RW) - * - * wave1 above max limit mode. - * 0: output 0xffff. - * 1: output 0x0. - * 2: output as level_max_limit1.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL) -#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U) -#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) - -/* - * WAVE1_HIGH_AREA1_LIMIT (RW) - * - * wave1 high area1 limit mode. - * 0: output 0xffff. - * 1: output as level_max_limit1.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL) -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U) -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) - -/* - * WAVE1_HIGH_AREA0_LIMIT (RW) - * - * wave1 high area0 limit mode. - * 0: output 0xffff. - * 1: output as level_max_limit1.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL) -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U) -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) - -/* - * WAVE1_LOW_AREA1_LIMIT (RW) - * - * wave1 low area1 limit mode. - * 0: output 0. - * 1: output as level_min_limit1.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL) -#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U) -#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) - -/* - * WAVE1_LOW_AREA0_LIMIT (RW) - * - * wave1 low area0 limit mode. - * 0: output 0. - * 1: output as level_min_limit1.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL) -#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U) -#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) - -/* - * WAVE1_BELOW_MIN_LIMIT (RW) - * - * wave1 below min limit mode. - * 0: output 0. - * 1: output 0xffff. - * 2: output as level_min_limit1.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL) -#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U) -#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) - -/* - * WAVE0_ABOVE_MAX_LIMIT (RW) - * - * wave0 above max limit mode. - * 0: output 0xffff. - * 1: output 0x0. - * 2: output as level_max_limit0.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U) -#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U) -#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) - -/* - * WAVE0_HIGH_AREA1_LIMIT (RW) - * - * wave0 high area1 limit mode. - * 0: output 0xffff. - * 1: output as level_max_limit0.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U) -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U) -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) - -/* - * WAVE0_HIGH_AREA0_LIMIT (RW) - * - * wave0 high area0 limit mode. - * 0: output 0xffff. - * 1: output as level_max_limit0.level0_max_limit - */ -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U) -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U) -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) - -/* - * WAVE0_LOW_AREA1_LIMIT (RW) - * - * wave0 low area1 limit mode. - * 0: output 0. - * 1: output as level_min_limit0.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U) -#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U) -#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) - -/* - * WAVE0_LOW_AREA0_LIMIT (RW) - * - * wave0 low area0 limit mode. - * 0: output 0. - * 1: output as level_min_limit0.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U) -#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U) -#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) - -/* - * WAVE0_BELOW_MIN_LIMIT (RW) - * - * wave0 below min limit mode. - * 0: output 0. - * 1: output 0xffff. - * 2: output as level_min_limit0.level1_min_limit - */ -#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U) -#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U) -#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) -#define QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEO_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) - -/* - * SADDLE_TYPE (RW) - * - * saddle type seclect; - * 0:standard saddle. - * 1: triple-cos saddle. - */ -#define QEO_WAVE_MODE_SADDLE_TYPE_MASK (0x80U) -#define QEO_WAVE_MODE_SADDLE_TYPE_SHIFT (7U) -#define QEO_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) -#define QEO_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_SADDLE_TYPE_MASK) >> QEO_WAVE_MODE_SADDLE_TYPE_SHIFT) - -/* - * EN_WAVE2_VD_VQ_INJECT (RW) - * - * wave2 VdVq inject enable. - * 0: disable VdVq inject. - * 1: enable VdVq inject. - */ -#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK (0x40U) -#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT (6U) -#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) -#define QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE2_VD_VQ_INJECT_SHIFT) - -/* - * EN_WAVE1_VD_VQ_INJECT (RW) - * - * wave1 VdVq inject enable. - * 0: disable VdVq inject. - * 1: enable VdVq inject. - */ -#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK (0x20U) -#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT (5U) -#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) -#define QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE1_VD_VQ_INJECT_SHIFT) - -/* - * EN_WAVE0_VD_VQ_INJECT (RW) - * - * wave0 VdVq inject enable. - * 0: disable VdVq inject. - * 1: enable VdVq inject. - */ -#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK (0x10U) -#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT (4U) -#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) -#define QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_MASK) >> QEO_WAVE_MODE_EN_WAVE0_VD_VQ_INJECT_SHIFT) - -/* - * WAVES_OUTPUT_TYPE (RW) - * - * wave0/1/2 output mode. - * 0: cosine wave. - * 1: saddle wave. - * 2. abs cosine wave. - * 3. saw wave - */ -#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U) -#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U) -#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) -#define QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEO_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) - -/* Bitfield definition for register of struct WAVE: RESOLUTION */ -/* - * LINES (RW) - * - * wave0/1/2 resolution - */ -#define QEO_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) -#define QEO_WAVE_RESOLUTION_LINES_SHIFT (0U) -#define QEO_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_WAVE_RESOLUTION_LINES_SHIFT) & QEO_WAVE_RESOLUTION_LINES_MASK) -#define QEO_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_WAVE_RESOLUTION_LINES_MASK) >> QEO_WAVE_RESOLUTION_LINES_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VAL (RW) - * - * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period - */ -#define QEO_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFU) -#define QEO_WAVE_PHASE_SHIFT_VAL_SHIFT (0U) -#define QEO_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) -#define QEO_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_PHASE_SHIFT_VAL_MASK) >> QEO_WAVE_PHASE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VQ_VAL (RW) - * - * Vq inject value - */ -#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK (0xFFFF0000UL) -#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT (16U) -#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) -#define QEO_WAVE_VD_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VQ_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VQ_VAL_SHIFT) - -/* - * VD_VAL (RW) - * - * Vd inject value - */ -#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK (0xFFFFU) -#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT (0U) -#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) -#define QEO_WAVE_VD_VQ_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_INJECT_VD_VAL_MASK) >> QEO_WAVE_VD_VQ_INJECT_VD_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */ -/* - * LOAD (WO) - * - * load wave0/1/2 vd vq value. always read 0 - * 0: vd vq keep previous value. - * 1: load wave0/1/2 vd vq value at sametime. - */ -#define QEO_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U) -#define QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U) -#define QEO_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) -#define QEO_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEO_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEO_WAVE_VD_VQ_LOAD_LOAD_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * EN_SCAL (RW) - * - * enable wave amplitude scaling. 0: disable; 1: enable - */ -#define QEO_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL) -#define QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U) -#define QEO_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) -#define QEO_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEO_WAVE_AMPLITUDE_EN_SCAL_SHIFT) - -/* - * AMP_VAL (RW) - * - * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. - */ -#define QEO_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU) -#define QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U) -#define QEO_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) -#define QEO_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEO_WAVE_AMPLITUDE_AMP_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VAL (RW) - * - * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. - */ -#define QEO_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL) -#define QEO_WAVE_MID_POINT_VAL_SHIFT (0U) -#define QEO_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_MID_POINT_VAL_SHIFT) & QEO_WAVE_MID_POINT_VAL_MASK) -#define QEO_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_MID_POINT_VAL_MASK) >> QEO_WAVE_MID_POINT_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: MIN */ -/* - * LIMIT1 (RW) - * - * low area limit level1 - */ -#define QEO_WAVE_LIMIT_MIN_LIMIT1_MASK (0xFFFF0000UL) -#define QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT (16U) -#define QEO_WAVE_LIMIT_MIN_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) -#define QEO_WAVE_LIMIT_MIN_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT1_SHIFT) - -/* - * LIMIT0 (RW) - * - * low area limit level0 - */ -#define QEO_WAVE_LIMIT_MIN_LIMIT0_MASK (0xFFFFU) -#define QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT (0U) -#define QEO_WAVE_LIMIT_MIN_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) -#define QEO_WAVE_LIMIT_MIN_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MIN_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MIN_LIMIT0_SHIFT) - -/* Bitfield definition for register of struct WAVE: MAX */ -/* - * LIMIT1 (RW) - * - * high area limit level1 - */ -#define QEO_WAVE_LIMIT_MAX_LIMIT1_MASK (0xFFFF0000UL) -#define QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT (16U) -#define QEO_WAVE_LIMIT_MAX_LIMIT1_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) -#define QEO_WAVE_LIMIT_MAX_LIMIT1_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT1_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT1_SHIFT) - -/* - * LIMIT0 (RW) - * - * high area limit level0 - */ -#define QEO_WAVE_LIMIT_MAX_LIMIT0_MASK (0xFFFFU) -#define QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT (0U) -#define QEO_WAVE_LIMIT_MAX_LIMIT0_SET(x) (((uint32_t)(x) << QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) -#define QEO_WAVE_LIMIT_MAX_LIMIT0_GET(x) (((uint32_t)(x) & QEO_WAVE_LIMIT_MAX_LIMIT0_MASK) >> QEO_WAVE_LIMIT_MAX_LIMIT0_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VAL (RW) - * - * wave0 deadzone shifter value - */ -#define QEO_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFU) -#define QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U) -#define QEO_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) -#define QEO_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEO_WAVE_DEADZONE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct ABZ: MODE */ -/* - * REVERSE_EDGE_TYPE (RW) - * - * pulse reverse wave，reverse edge point: - * 0: between pulse's posedge and negedge, min period dedicated by the num line_width - * 1: edge change point flow pulse's negedge. - */ -#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL) -#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U) -#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) -#define QEO_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEO_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) - -/* - * EN_WDOG (RW) - * - * enable abz wdog: - * 0: disable abz wdog. - * 1: enable abz wdog. - */ -#define QEO_ABZ_MODE_EN_WDOG_MASK (0x1000000UL) -#define QEO_ABZ_MODE_EN_WDOG_SHIFT (24U) -#define QEO_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_EN_WDOG_SHIFT) & QEO_ABZ_MODE_EN_WDOG_MASK) -#define QEO_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_EN_WDOG_MASK) >> QEO_ABZ_MODE_EN_WDOG_SHIFT) - -/* - * Z_POLARITY (RW) - * - * wave_z polarity. - * 0: normal output. - * 1: invert normal output - */ -#define QEO_ABZ_MODE_Z_POLARITY_MASK (0x100000UL) -#define QEO_ABZ_MODE_Z_POLARITY_SHIFT (20U) -#define QEO_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_POLARITY_SHIFT) & QEO_ABZ_MODE_Z_POLARITY_MASK) -#define QEO_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_POLARITY_MASK) >> QEO_ABZ_MODE_Z_POLARITY_SHIFT) - -/* - * B_POLARITY (RW) - * - * wave_b polarity. - * 0: normal output. - * 1: invert normal output - */ -#define QEO_ABZ_MODE_B_POLARITY_MASK (0x10000UL) -#define QEO_ABZ_MODE_B_POLARITY_SHIFT (16U) -#define QEO_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_POLARITY_SHIFT) & QEO_ABZ_MODE_B_POLARITY_MASK) -#define QEO_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_POLARITY_MASK) >> QEO_ABZ_MODE_B_POLARITY_SHIFT) - -/* - * A_POLARITY (RW) - * - * wave_a polarity. - * 0: normal output. - * 1: invert normal output - */ -#define QEO_ABZ_MODE_A_POLARITY_MASK (0x1000U) -#define QEO_ABZ_MODE_A_POLARITY_SHIFT (12U) -#define QEO_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_POLARITY_SHIFT) & QEO_ABZ_MODE_A_POLARITY_MASK) -#define QEO_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_POLARITY_MASK) >> QEO_ABZ_MODE_A_POLARITY_SHIFT) - -/* - * Z_TYPE (RW) - * - * wave_z type: - * 0: zero pulse and output high at both wave_a and wave_b are high. mantain about 25% period. - * 1: zero pulse output high about 75% period. start from 0 to 75% period. - * 2: zero pulse output high about 100% period. - * 3: wave_z output as tree-phase wave same as wave_a/wave_b - */ -#define QEO_ABZ_MODE_Z_TYPE_MASK (0x300U) -#define QEO_ABZ_MODE_Z_TYPE_SHIFT (8U) -#define QEO_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_Z_TYPE_SHIFT) & QEO_ABZ_MODE_Z_TYPE_MASK) -#define QEO_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_Z_TYPE_MASK) >> QEO_ABZ_MODE_Z_TYPE_SHIFT) - -/* - * B_TYPE (RW) - * - * wave_b type: - * 0: Two-phase orthogonality wave_b. - * 1: reverse wave of pulse/reverse type. - * 2: down wave of up/down type. - * 3: Three-phase orthogonality wave_b. - */ -#define QEO_ABZ_MODE_B_TYPE_MASK (0x30U) -#define QEO_ABZ_MODE_B_TYPE_SHIFT (4U) -#define QEO_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_B_TYPE_SHIFT) & QEO_ABZ_MODE_B_TYPE_MASK) -#define QEO_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_B_TYPE_MASK) >> QEO_ABZ_MODE_B_TYPE_SHIFT) - -/* - * A_TYPE (RW) - * - * wave_a type: - * 0: Two-phase orthogonality wave_a. - * 1: pulse wave of pulse/reverse type. - * 2: up wave of up/down type. - * 3: Three-phase orthogonality wave_a. - */ -#define QEO_ABZ_MODE_A_TYPE_MASK (0x3U) -#define QEO_ABZ_MODE_A_TYPE_SHIFT (0U) -#define QEO_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEO_ABZ_MODE_A_TYPE_SHIFT) & QEO_ABZ_MODE_A_TYPE_MASK) -#define QEO_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEO_ABZ_MODE_A_TYPE_MASK) >> QEO_ABZ_MODE_A_TYPE_SHIFT) - -/* Bitfield definition for register of struct ABZ: RESOLUTION */ -/* - * LINES (RW) - * - * wave_a/b/z resolution - */ -#define QEO_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) -#define QEO_ABZ_RESOLUTION_LINES_SHIFT (0U) -#define QEO_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_ABZ_RESOLUTION_LINES_SHIFT) & QEO_ABZ_RESOLUTION_LINES_MASK) -#define QEO_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_ABZ_RESOLUTION_LINES_MASK) >> QEO_ABZ_RESOLUTION_LINES_SHIFT) - -/* Bitfield definition for register of struct ABZ: A */ -/* - * VAL (RW) - * - * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period. - */ -#define QEO_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFU) -#define QEO_ABZ_PHASE_SHIFT_VAL_SHIFT (0U) -#define QEO_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) -#define QEO_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_ABZ_PHASE_SHIFT_VAL_MASK) >> QEO_ABZ_PHASE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct ABZ: LINE_WIDTH */ -/* - * LINE (RW) - * - * the num of system clk by 1/4 period when using as Two-phase orthogonality. - */ -#define QEO_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL) -#define QEO_ABZ_LINE_WIDTH_LINE_SHIFT (0U) -#define QEO_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEO_ABZ_LINE_WIDTH_LINE_SHIFT) & QEO_ABZ_LINE_WIDTH_LINE_MASK) -#define QEO_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEO_ABZ_LINE_WIDTH_LINE_MASK) >> QEO_ABZ_LINE_WIDTH_LINE_SHIFT) - -/* Bitfield definition for register of struct ABZ: WDOG_WIDTH */ -/* - * WIDTH (RW) - * - * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. - */ -#define QEO_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL) -#define QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U) -#define QEO_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) -#define QEO_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEO_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEO_ABZ_WDOG_WIDTH_WIDTH_SHIFT) - -/* Bitfield definition for register of struct ABZ: POSTION_SYNC */ -/* - * POSTION (WO) - * - * load next valid postion into abz owned postion. always read 0 - * 0: sync abz owned postion with next valid postion. - * 1: not sync. - */ -#define QEO_ABZ_POSTION_SYNC_POSTION_MASK (0x1U) -#define QEO_ABZ_POSTION_SYNC_POSTION_SHIFT (0U) -#define QEO_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) -#define QEO_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEO_ABZ_POSTION_SYNC_POSTION_MASK) >> QEO_ABZ_POSTION_SYNC_POSTION_SHIFT) - -/* Bitfield definition for register of struct PWM: MODE */ -/* - * PWM7_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL) -#define QEO_PWM_MODE_PWM7_SAFETY_SHIFT (30U) -#define QEO_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM7_SAFETY_SHIFT) & QEO_PWM_MODE_PWM7_SAFETY_MASK) -#define QEO_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM7_SAFETY_MASK) >> QEO_PWM_MODE_PWM7_SAFETY_SHIFT) - -/* - * PWM6_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL) -#define QEO_PWM_MODE_PWM6_SAFETY_SHIFT (28U) -#define QEO_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM6_SAFETY_SHIFT) & QEO_PWM_MODE_PWM6_SAFETY_MASK) -#define QEO_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM6_SAFETY_MASK) >> QEO_PWM_MODE_PWM6_SAFETY_SHIFT) - -/* - * PWM5_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL) -#define QEO_PWM_MODE_PWM5_SAFETY_SHIFT (26U) -#define QEO_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM5_SAFETY_SHIFT) & QEO_PWM_MODE_PWM5_SAFETY_MASK) -#define QEO_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM5_SAFETY_MASK) >> QEO_PWM_MODE_PWM5_SAFETY_SHIFT) - -/* - * PWM4_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL) -#define QEO_PWM_MODE_PWM4_SAFETY_SHIFT (24U) -#define QEO_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM4_SAFETY_SHIFT) & QEO_PWM_MODE_PWM4_SAFETY_MASK) -#define QEO_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM4_SAFETY_MASK) >> QEO_PWM_MODE_PWM4_SAFETY_SHIFT) - -/* - * PWM3_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL) -#define QEO_PWM_MODE_PWM3_SAFETY_SHIFT (22U) -#define QEO_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM3_SAFETY_SHIFT) & QEO_PWM_MODE_PWM3_SAFETY_MASK) -#define QEO_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM3_SAFETY_MASK) >> QEO_PWM_MODE_PWM3_SAFETY_SHIFT) - -/* - * PWM2_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL) -#define QEO_PWM_MODE_PWM2_SAFETY_SHIFT (20U) -#define QEO_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM2_SAFETY_SHIFT) & QEO_PWM_MODE_PWM2_SAFETY_MASK) -#define QEO_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM2_SAFETY_MASK) >> QEO_PWM_MODE_PWM2_SAFETY_SHIFT) - -/* - * PWM1_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL) -#define QEO_PWM_MODE_PWM1_SAFETY_SHIFT (18U) -#define QEO_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM1_SAFETY_SHIFT) & QEO_PWM_MODE_PWM1_SAFETY_MASK) -#define QEO_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM1_SAFETY_MASK) >> QEO_PWM_MODE_PWM1_SAFETY_SHIFT) - -/* - * PWM0_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEO_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL) -#define QEO_PWM_MODE_PWM0_SAFETY_SHIFT (16U) -#define QEO_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM0_SAFETY_SHIFT) & QEO_PWM_MODE_PWM0_SAFETY_MASK) -#define QEO_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM0_SAFETY_MASK) >> QEO_PWM_MODE_PWM0_SAFETY_SHIFT) - -/* - * PWM_ENTER_SAFETY_MODE (RW) - * - * PWM enter safety mode - * 0: not enter - * 1: enter - */ -#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U) -#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U) -#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) -#define QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEO_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) - -/* - * PWM_SAFETY_BYPASS (RW) - * - * PWM safety mode bypass - * 0: not bypass - * 1: bypass - */ -#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U) -#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U) -#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) -#define QEO_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEO_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) - -/* - * REVISE_UP_DN (RW) - * - * exchange PWM pairs’ output - * 0: not exchange. - * 1: exchange. - */ -#define QEO_PWM_MODE_REVISE_UP_DN_MASK (0x10U) -#define QEO_PWM_MODE_REVISE_UP_DN_SHIFT (4U) -#define QEO_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_REVISE_UP_DN_SHIFT) & QEO_PWM_MODE_REVISE_UP_DN_MASK) -#define QEO_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_REVISE_UP_DN_MASK) >> QEO_PWM_MODE_REVISE_UP_DN_SHIFT) - -/* - * PHASE_NUM (RW) - * - * pwm force phase number. - */ -#define QEO_PWM_MODE_PHASE_NUM_MASK (0xFU) -#define QEO_PWM_MODE_PHASE_NUM_SHIFT (0U) -#define QEO_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEO_PWM_MODE_PHASE_NUM_SHIFT) & QEO_PWM_MODE_PHASE_NUM_MASK) -#define QEO_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEO_PWM_MODE_PHASE_NUM_MASK) >> QEO_PWM_MODE_PHASE_NUM_SHIFT) - -/* Bitfield definition for register of struct PWM: RESOLUTION */ -/* - * LINES (RW) - * - * pwm resolution - */ -#define QEO_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) -#define QEO_PWM_RESOLUTION_LINES_SHIFT (0U) -#define QEO_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEO_PWM_RESOLUTION_LINES_SHIFT) & QEO_PWM_RESOLUTION_LINES_MASK) -#define QEO_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEO_PWM_RESOLUTION_LINES_MASK) >> QEO_PWM_RESOLUTION_LINES_SHIFT) - -/* Bitfield definition for register of struct PWM: A */ -/* - * VAL (RW) - * - * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^16) period - */ -#define QEO_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFU) -#define QEO_PWM_PHASE_SHIFT_VAL_SHIFT (0U) -#define QEO_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_SHIFT_VAL_SHIFT) & QEO_PWM_PHASE_SHIFT_VAL_MASK) -#define QEO_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_SHIFT_VAL_MASK) >> QEO_PWM_PHASE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct PWM: POSEDGE0 */ -/* - * PWM7 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM7_MASK (0xC000U) -#define QEO_PWM_PHASE_TABLE_PWM7_SHIFT (14U) -#define QEO_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM7_SHIFT) & QEO_PWM_PHASE_TABLE_PWM7_MASK) -#define QEO_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM7_MASK) >> QEO_PWM_PHASE_TABLE_PWM7_SHIFT) - -/* - * PWM6 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM6_MASK (0x3000U) -#define QEO_PWM_PHASE_TABLE_PWM6_SHIFT (12U) -#define QEO_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM6_SHIFT) & QEO_PWM_PHASE_TABLE_PWM6_MASK) -#define QEO_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM6_MASK) >> QEO_PWM_PHASE_TABLE_PWM6_SHIFT) - -/* - * PWM5 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM5_MASK (0xC00U) -#define QEO_PWM_PHASE_TABLE_PWM5_SHIFT (10U) -#define QEO_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM5_SHIFT) & QEO_PWM_PHASE_TABLE_PWM5_MASK) -#define QEO_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM5_MASK) >> QEO_PWM_PHASE_TABLE_PWM5_SHIFT) - -/* - * PWM4 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM4_MASK (0x300U) -#define QEO_PWM_PHASE_TABLE_PWM4_SHIFT (8U) -#define QEO_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM4_SHIFT) & QEO_PWM_PHASE_TABLE_PWM4_MASK) -#define QEO_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM4_MASK) >> QEO_PWM_PHASE_TABLE_PWM4_SHIFT) - -/* - * PWM3 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM3_MASK (0xC0U) -#define QEO_PWM_PHASE_TABLE_PWM3_SHIFT (6U) -#define QEO_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM3_SHIFT) & QEO_PWM_PHASE_TABLE_PWM3_MASK) -#define QEO_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM3_MASK) >> QEO_PWM_PHASE_TABLE_PWM3_SHIFT) - -/* - * PWM2 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM2_MASK (0x30U) -#define QEO_PWM_PHASE_TABLE_PWM2_SHIFT (4U) -#define QEO_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM2_SHIFT) & QEO_PWM_PHASE_TABLE_PWM2_MASK) -#define QEO_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM2_MASK) >> QEO_PWM_PHASE_TABLE_PWM2_SHIFT) - -/* - * PWM1 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM1_MASK (0xCU) -#define QEO_PWM_PHASE_TABLE_PWM1_SHIFT (2U) -#define QEO_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM1_SHIFT) & QEO_PWM_PHASE_TABLE_PWM1_MASK) -#define QEO_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM1_MASK) >> QEO_PWM_PHASE_TABLE_PWM1_SHIFT) - -/* - * PWM0 (RW) - * - * pwm phase table value - */ -#define QEO_PWM_PHASE_TABLE_PWM0_MASK (0x3U) -#define QEO_PWM_PHASE_TABLE_PWM0_SHIFT (0U) -#define QEO_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEO_PWM_PHASE_TABLE_PWM0_SHIFT) & QEO_PWM_PHASE_TABLE_PWM0_MASK) -#define QEO_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEO_PWM_PHASE_TABLE_PWM0_MASK) >> QEO_PWM_PHASE_TABLE_PWM0_SHIFT) - -/* Bitfield definition for register: POSTION_SOFTWARE */ -/* - * POSTION_SOFTWAVE (RW) - * - * softwave inject postion - */ -#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL) -#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U) -#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) -#define QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEO_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) - -/* Bitfield definition for register: POSTION_SEL */ -/* - * POSTION_SEL (RW) - * - * enable softwave inject postion. - * 0: disable. - * 1: enable. - */ -#define QEO_POSTION_SEL_POSTION_SEL_MASK (0x1U) -#define QEO_POSTION_SEL_POSTION_SEL_SHIFT (0U) -#define QEO_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEO_POSTION_SEL_POSTION_SEL_SHIFT) & QEO_POSTION_SEL_POSTION_SEL_MASK) -#define QEO_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEO_POSTION_SEL_POSTION_SEL_MASK) >> QEO_POSTION_SEL_POSTION_SEL_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * PWM_FOURCE (RO) - * - * qeo_pwm_force observe - */ -#define QEO_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL) -#define QEO_STATUS_PWM_FOURCE_SHIFT (16U) -#define QEO_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_FOURCE_MASK) >> QEO_STATUS_PWM_FOURCE_SHIFT) - -/* - * PWM_SAFETY (RO) - * - * pwm_fault status - */ -#define QEO_STATUS_PWM_SAFETY_MASK (0x1U) -#define QEO_STATUS_PWM_SAFETY_SHIFT (0U) -#define QEO_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEO_STATUS_PWM_SAFETY_MASK) >> QEO_STATUS_PWM_SAFETY_SHIFT) - -/* Bitfield definition for register: DEBUG0 */ -/* - * WAVE1 (RO) - * - * wave1 observe - */ -#define QEO_DEBUG0_WAVE1_MASK (0xFFFF0000UL) -#define QEO_DEBUG0_WAVE1_SHIFT (16U) -#define QEO_DEBUG0_WAVE1_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE1_MASK) >> QEO_DEBUG0_WAVE1_SHIFT) - -/* - * WAVE0 (RO) - * - * wave0 observe - */ -#define QEO_DEBUG0_WAVE0_MASK (0xFFFFU) -#define QEO_DEBUG0_WAVE0_SHIFT (0U) -#define QEO_DEBUG0_WAVE0_GET(x) (((uint32_t)(x) & QEO_DEBUG0_WAVE0_MASK) >> QEO_DEBUG0_WAVE0_SHIFT) - -/* Bitfield definition for register: DEBUG1 */ -/* - * QEO_FINISH (RO) - * - * qeo finish observe - */ -#define QEO_DEBUG1_QEO_FINISH_MASK (0x10000000UL) -#define QEO_DEBUG1_QEO_FINISH_SHIFT (28U) -#define QEO_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEO_DEBUG1_QEO_FINISH_MASK) >> QEO_DEBUG1_QEO_FINISH_SHIFT) - -/* - * WAVE_Z (RO) - * - * wave_z observe - */ -#define QEO_DEBUG1_WAVE_Z_MASK (0x1000000UL) -#define QEO_DEBUG1_WAVE_Z_SHIFT (24U) -#define QEO_DEBUG1_WAVE_Z_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_Z_MASK) >> QEO_DEBUG1_WAVE_Z_SHIFT) - -/* - * WAVE_B (RO) - * - * wave_b observe - */ -#define QEO_DEBUG1_WAVE_B_MASK (0x100000UL) -#define QEO_DEBUG1_WAVE_B_SHIFT (20U) -#define QEO_DEBUG1_WAVE_B_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_B_MASK) >> QEO_DEBUG1_WAVE_B_SHIFT) - -/* - * WAVE_A (RO) - * - * wave_a observe - */ -#define QEO_DEBUG1_WAVE_A_MASK (0x10000UL) -#define QEO_DEBUG1_WAVE_A_SHIFT (16U) -#define QEO_DEBUG1_WAVE_A_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE_A_MASK) >> QEO_DEBUG1_WAVE_A_SHIFT) - -/* - * WAVE2 (RO) - * - * wave2 observe - */ -#define QEO_DEBUG1_WAVE2_MASK (0xFFFFU) -#define QEO_DEBUG1_WAVE2_SHIFT (0U) -#define QEO_DEBUG1_WAVE2_GET(x) (((uint32_t)(x) & QEO_DEBUG1_WAVE2_MASK) >> QEO_DEBUG1_WAVE2_SHIFT) - -/* Bitfield definition for register: DEBUG2 */ -/* - * ABZ_OWN_POSTION (RO) - * - * abz_own_postion observe - */ -#define QEO_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) -#define QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U) -#define QEO_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG2_ABZ_OWN_POSTION_SHIFT) - -/* Bitfield definition for register: DEBUG3 */ -/* - * ABZ_OWN_POSTION (RO) - * - * abz_own_postion observe - */ -#define QEO_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) -#define QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U) -#define QEO_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEO_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEO_DEBUG3_ABZ_OWN_POSTION_SHIFT) - - - -/* PHASE_SHIFT register group index macro definition */ -#define QEO_WAVE_PHASE_SHIFT_WAVE0 (0UL) -#define QEO_WAVE_PHASE_SHIFT_WAVE1 (1UL) -#define QEO_WAVE_PHASE_SHIFT_WAVE2 (2UL) - -/* VD_VQ_INJECT register group index macro definition */ -#define QEO_WAVE_VD_VQ_INJECT_WAVE0 (0UL) -#define QEO_WAVE_VD_VQ_INJECT_WAVE1 (1UL) -#define QEO_WAVE_VD_VQ_INJECT_WAVE2 (2UL) - -/* AMPLITUDE register group index macro definition */ -#define QEO_WAVE_AMPLITUDE_WAVE0 (0UL) -#define QEO_WAVE_AMPLITUDE_WAVE1 (1UL) -#define QEO_WAVE_AMPLITUDE_WAVE2 (2UL) - -/* MID_POINT register group index macro definition */ -#define QEO_WAVE_MID_POINT_WAVE0 (0UL) -#define QEO_WAVE_MID_POINT_WAVE1 (1UL) -#define QEO_WAVE_MID_POINT_WAVE2 (2UL) - -/* LIMIT register group index macro definition */ -#define QEO_LIMIT_WAVE0 (0UL) -#define QEO_LIMIT_WAVE1 (1UL) -#define QEO_LIMIT_WAVE2 (2UL) - -/* DEADZONE_SHIFT register group index macro definition */ -#define QEO_WAVE_DEADZONE_SHIFT_WAVE0 (0UL) -#define QEO_WAVE_DEADZONE_SHIFT_WAVE1 (1UL) -#define QEO_WAVE_DEADZONE_SHIFT_WAVE2 (2UL) - -/* PHASE_SHIFT register group index macro definition */ -#define QEO_ABZ_PHASE_SHIFT_A (0UL) -#define QEO_ABZ_PHASE_SHIFT_B (1UL) -#define QEO_ABZ_PHASE_SHIFT_Z (2UL) - -/* PHASE_SHIFT register group index macro definition */ -#define QEO_PWM_PHASE_SHIFT_A (0UL) -#define QEO_PWM_PHASE_SHIFT_B (1UL) -#define QEO_PWM_PHASE_SHIFT_C (2UL) -#define QEO_PWM_PHASE_SHIFT_D (3UL) - -/* PHASE_TABLE register group index macro definition */ -#define QEO_PWM_PHASE_TABLE_POSEDGE0 (0UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE1 (1UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE2 (2UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE3 (3UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE4 (4UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE5 (5UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE6 (6UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE7 (7UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE8 (8UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE9 (9UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE10 (10UL) -#define QEO_PWM_PHASE_TABLE_POSEDGE11 (11UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE0 (12UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE1 (13UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE2 (14UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE3 (15UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE4 (16UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE5 (17UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE6 (18UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE7 (19UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE8 (20UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE9 (21UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE10 (22UL) -#define QEO_PWM_PHASE_TABLE_NEGEDGE11 (23UL) - - -#endif /* HPM_QEO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_rdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_rdc_regs.h deleted file mode 100644 index e778a1da261..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_rdc_regs.h +++ /dev/null @@ -1,1331 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RDC_H -#define HPM_RDC_H - -typedef struct { - __RW uint32_t RDC_CTL; /* 0x0: rdc control */ - __R uint32_t ACC_I; /* 0x4: accumulate result of i_channel */ - __R uint32_t ACC_Q; /* 0x8: accumulate result of q_channel */ - __RW uint32_t IN_CTL; /* 0xC: input channel selection */ - __RW uint32_t OUT_CTL; /* 0x10: output channel selection */ - __R uint8_t RESERVED0[32]; /* 0x14 - 0x33: Reserved */ - __RW uint32_t EXC_TIMMING; /* 0x34: excitation signal timming setting */ - __RW uint32_t EXC_SCALING; /* 0x38: amplitude scaling for excitation */ - __RW uint32_t EXC_OFFSET; /* 0x3C: amplitude offset setting */ - __RW uint32_t PWM_SCALING; /* 0x40: amplitude scaling for excitation */ - __RW uint32_t PWM_OFFSET; /* 0x44: amplitude offset setting */ - __RW uint32_t TRIG_OUT0_CFG; /* 0x48: Configuration for trigger out 0 in clock cycle */ - __RW uint32_t TRIG_OUT1_CFG; /* 0x4C: Configuration for trigger out 1 in clock cycle */ - __RW uint32_t PWM_DZ; /* 0x50: pwm dead zone control in clock cycle */ - __RW uint32_t SYNC_OUT_CTRL; /* 0x54: synchronize output signal control */ - __RW uint32_t EXC_SYNC_DLY; /* 0x58: trigger in delay timming in soc bus cycle */ - __R uint8_t RESERVED1[20]; /* 0x5C - 0x6F: Reserved */ - __RW uint32_t MAX_I; /* 0x70: max value of i_channel */ - __RW uint32_t MIN_I; /* 0x74: min value of i_channel */ - __RW uint32_t MAX_Q; /* 0x78: max value of q_channel */ - __RW uint32_t MIN_Q; /* 0x7C: min value of q_channel */ - __RW uint32_t THRS_I; /* 0x80: the offset setting for edge detection of the i_channel */ - __RW uint32_t THRS_Q; /* 0x84: the offset setting for edge detection of the q_channel */ - __RW uint32_t EDG_DET_CTL; /* 0x88: the control for edge detection */ - __RW uint32_t ACC_SCALING; /* 0x8C: scaling for accumulation result */ - __RW uint32_t EXC_PERIOD; /* 0x90: period of excitation */ - __R uint8_t RESERVED2[12]; /* 0x94 - 0x9F: Reserved */ - __RW uint32_t SYNC_DELAY_I; /* 0xA0: delay setting in clock cycle for synchronous signal */ - __R uint8_t RESERVED3[4]; /* 0xA4 - 0xA7: Reserved */ - __R uint32_t RISE_DELAY_I; /* 0xA8: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data */ - __R uint32_t FALL_DELAY_I; /* 0xAC: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data */ - __R uint32_t SAMPLE_RISE_I; /* 0xB0: sample value on rising edge of rectify signal */ - __R uint32_t SAMPLE_FALL_I; /* 0xB4: sample value on falling edge of rectify signal */ - __R uint32_t ACC_CNT_I; /* 0xB8: number of accumulation */ - __R uint32_t SIGN_CNT_I; /* 0xBC: sample counter of opposite sign with rectify signal */ - __RW uint32_t SYNC_DELAY_Q; /* 0xC0: delay setting in clock cycle for synchronous signal */ - __R uint8_t RESERVED4[4]; /* 0xC4 - 0xC7: Reserved */ - __R uint32_t RISE_DELAY_Q; /* 0xC8: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data */ - __R uint32_t FALL_DELAY_Q; /* 0xCC: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data */ - __R uint32_t SAMPLE_RISE_Q; /* 0xD0: sample value on rising edge of rectify signal */ - __R uint32_t SAMPLE_FALL_Q; /* 0xD4: sample value on falling edge of rectify signal */ - __R uint32_t ACC_CNT_Q; /* 0xD8: number of accumulation */ - __R uint32_t SIGN_CNT_Q; /* 0xDC: sample counter of opposite sign with rectify signal */ - __RW uint32_t AMP_MAX; /* 0xE0: the maximum of acc amplitude */ - __RW uint32_t AMP_MIN; /* 0xE4: the minimum of acc amplitude */ - __RW uint32_t INT_EN; /* 0xE8: the interrupt mask control */ - __W uint32_t ADC_INT_STATE; /* 0xEC: the interrupt state */ -} RDC_Type; - - -/* Bitfield definition for register: RDC_CTL */ -/* - * TS_SEL (RW) - * - * Time stamp selection for accumulation - * 0: end of accumulation - * 1: start of accumulation - * 2: center of accumulation - */ -#define RDC_RDC_CTL_TS_SEL_MASK (0x300000UL) -#define RDC_RDC_CTL_TS_SEL_SHIFT (20U) -#define RDC_RDC_CTL_TS_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_TS_SEL_SHIFT) & RDC_RDC_CTL_TS_SEL_MASK) -#define RDC_RDC_CTL_TS_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_TS_SEL_MASK) >> RDC_RDC_CTL_TS_SEL_SHIFT) - -/* - * ACC_LEN (RW) - * - * Accumulate time, support on the fly change - * 0：1 cycle - * 1：2 cycles - * … - * 255: 256 cycles - */ -#define RDC_RDC_CTL_ACC_LEN_MASK (0xFF000UL) -#define RDC_RDC_CTL_ACC_LEN_SHIFT (12U) -#define RDC_RDC_CTL_ACC_LEN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_LEN_SHIFT) & RDC_RDC_CTL_ACC_LEN_MASK) -#define RDC_RDC_CTL_ACC_LEN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_LEN_MASK) >> RDC_RDC_CTL_ACC_LEN_SHIFT) - -/* - * RECTIFY_SEL (RW) - * - * Select reference point of rectify signal - * 0: 0 phase of internal exciting signal - * 1: 90 phase of internal exciting signal - * 2: 180 phase of internal exciting signal - * 3: 270 phase of internal exciting signal - * 4: use value on external pin - * 5: use invert value on external pin - */ -#define RDC_RDC_CTL_RECTIFY_SEL_MASK (0x70U) -#define RDC_RDC_CTL_RECTIFY_SEL_SHIFT (4U) -#define RDC_RDC_CTL_RECTIFY_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_RECTIFY_SEL_SHIFT) & RDC_RDC_CTL_RECTIFY_SEL_MASK) -#define RDC_RDC_CTL_RECTIFY_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_RECTIFY_SEL_MASK) >> RDC_RDC_CTL_RECTIFY_SEL_SHIFT) - -/* - * ACC_EN (RW) - * - * Enable rdc accumulate - * 0: rdc disable - * 1: rdc enable - */ -#define RDC_RDC_CTL_ACC_EN_MASK (0x4U) -#define RDC_RDC_CTL_ACC_EN_SHIFT (2U) -#define RDC_RDC_CTL_ACC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_EN_SHIFT) & RDC_RDC_CTL_ACC_EN_MASK) -#define RDC_RDC_CTL_ACC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_EN_MASK) >> RDC_RDC_CTL_ACC_EN_SHIFT) - -/* - * EXC_START (RW1C) - * - * Write 1 start excite signal, always read 0 - * 0: no effect - * 1: start excite signal - */ -#define RDC_RDC_CTL_EXC_START_MASK (0x2U) -#define RDC_RDC_CTL_EXC_START_SHIFT (1U) -#define RDC_RDC_CTL_EXC_START_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_START_SHIFT) & RDC_RDC_CTL_EXC_START_MASK) -#define RDC_RDC_CTL_EXC_START_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_START_MASK) >> RDC_RDC_CTL_EXC_START_SHIFT) - -/* - * EXC_EN (RW) - * - * Enable rdc excite signal - * 0: rdc disable - * 1: rdc enable - */ -#define RDC_RDC_CTL_EXC_EN_MASK (0x1U) -#define RDC_RDC_CTL_EXC_EN_SHIFT (0U) -#define RDC_RDC_CTL_EXC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_EN_SHIFT) & RDC_RDC_CTL_EXC_EN_MASK) -#define RDC_RDC_CTL_EXC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_EN_MASK) >> RDC_RDC_CTL_EXC_EN_SHIFT) - -/* Bitfield definition for register: ACC_I */ -/* - * ACC (RO) - * - * accumulate result of i_channel, this is a signed number - */ -#define RDC_ACC_I_ACC_MASK (0xFFFFFFFFUL) -#define RDC_ACC_I_ACC_SHIFT (0U) -#define RDC_ACC_I_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_I_ACC_MASK) >> RDC_ACC_I_ACC_SHIFT) - -/* Bitfield definition for register: ACC_Q */ -/* - * ACC (RO) - * - * accumulate result of q_channel, this is a signed number - */ -#define RDC_ACC_Q_ACC_MASK (0xFFFFFFFFUL) -#define RDC_ACC_Q_ACC_SHIFT (0U) -#define RDC_ACC_Q_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_Q_ACC_MASK) >> RDC_ACC_Q_ACC_SHIFT) - -/* Bitfield definition for register: IN_CTL */ -/* - * PORT_Q_SEL (RW) - * - * Input port selection for q_channel, - * 0:sel port0 - * 1:sel port1 - */ -#define RDC_IN_CTL_PORT_Q_SEL_MASK (0x100000UL) -#define RDC_IN_CTL_PORT_Q_SEL_SHIFT (20U) -#define RDC_IN_CTL_PORT_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_Q_SEL_SHIFT) & RDC_IN_CTL_PORT_Q_SEL_MASK) -#define RDC_IN_CTL_PORT_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_Q_SEL_MASK) >> RDC_IN_CTL_PORT_Q_SEL_SHIFT) - -/* - * CH_Q_SEL (RW) - * - * Input channel selection for q_channel - * 0: channel 0 selected - * 1: channel 1 selected - * … - * 31: channel 31 selected - */ -#define RDC_IN_CTL_CH_Q_SEL_MASK (0x1F000UL) -#define RDC_IN_CTL_CH_Q_SEL_SHIFT (12U) -#define RDC_IN_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_Q_SEL_SHIFT) & RDC_IN_CTL_CH_Q_SEL_MASK) -#define RDC_IN_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_Q_SEL_MASK) >> RDC_IN_CTL_CH_Q_SEL_SHIFT) - -/* - * PORT_I_SEL (RW) - * - * Input port selection for i_channel, - * 0:sel port0 - * 1:sel port1 - */ -#define RDC_IN_CTL_PORT_I_SEL_MASK (0x100U) -#define RDC_IN_CTL_PORT_I_SEL_SHIFT (8U) -#define RDC_IN_CTL_PORT_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_I_SEL_SHIFT) & RDC_IN_CTL_PORT_I_SEL_MASK) -#define RDC_IN_CTL_PORT_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_I_SEL_MASK) >> RDC_IN_CTL_PORT_I_SEL_SHIFT) - -/* - * CH_I_SEL (RW) - * - * Input channel selection for i_channel - * 0: channel 0 selected - * 1: channel 1 selected - * … - * 31: channel 31 selected - */ -#define RDC_IN_CTL_CH_I_SEL_MASK (0x1FU) -#define RDC_IN_CTL_CH_I_SEL_SHIFT (0U) -#define RDC_IN_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_I_SEL_SHIFT) & RDC_IN_CTL_CH_I_SEL_MASK) -#define RDC_IN_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_I_SEL_MASK) >> RDC_IN_CTL_CH_I_SEL_SHIFT) - -/* Bitfield definition for register: OUT_CTL */ -/* - * CH_Q_SEL (RW) - * - * Output channel selection for q_channel - */ -#define RDC_OUT_CTL_CH_Q_SEL_MASK (0x1F00U) -#define RDC_OUT_CTL_CH_Q_SEL_SHIFT (8U) -#define RDC_OUT_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_Q_SEL_SHIFT) & RDC_OUT_CTL_CH_Q_SEL_MASK) -#define RDC_OUT_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_Q_SEL_MASK) >> RDC_OUT_CTL_CH_Q_SEL_SHIFT) - -/* - * CH_I_SEL (RW) - * - * Output channel selection for i_channel - */ -#define RDC_OUT_CTL_CH_I_SEL_MASK (0x1FU) -#define RDC_OUT_CTL_CH_I_SEL_SHIFT (0U) -#define RDC_OUT_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_I_SEL_SHIFT) & RDC_OUT_CTL_CH_I_SEL_MASK) -#define RDC_OUT_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_I_SEL_MASK) >> RDC_OUT_CTL_CH_I_SEL_SHIFT) - -/* Bitfield definition for register: EXC_TIMMING */ -/* - * SWAP (RW) - * - * Swap output of PWM and DAC - * 0: disable swap - * 1: swap output - */ -#define RDC_EXC_TIMMING_SWAP_MASK (0x1000000UL) -#define RDC_EXC_TIMMING_SWAP_SHIFT (24U) -#define RDC_EXC_TIMMING_SWAP_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SWAP_SHIFT) & RDC_EXC_TIMMING_SWAP_MASK) -#define RDC_EXC_TIMMING_SWAP_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SWAP_MASK) >> RDC_EXC_TIMMING_SWAP_SHIFT) - -/* - * PWM_PRD (RW) - * - * Pwm period in samples， - * 0：1 sample period - * 1: 2 sample period - * ... - * 15: 16 sample period - */ -#define RDC_EXC_TIMMING_PWM_PRD_MASK (0xF00000UL) -#define RDC_EXC_TIMMING_PWM_PRD_SHIFT (20U) -#define RDC_EXC_TIMMING_PWM_PRD_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_PWM_PRD_SHIFT) & RDC_EXC_TIMMING_PWM_PRD_MASK) -#define RDC_EXC_TIMMING_PWM_PRD_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_PWM_PRD_MASK) >> RDC_EXC_TIMMING_PWM_PRD_SHIFT) - -/* - * SMP_NUM (RW) - * - * Number of sample every excitation period - * 0: 4 point - * 1: 8 point - * … - * 8: 1024 point - */ -#define RDC_EXC_TIMMING_SMP_NUM_MASK (0xF0000UL) -#define RDC_EXC_TIMMING_SMP_NUM_SHIFT (16U) -#define RDC_EXC_TIMMING_SMP_NUM_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_NUM_SHIFT) & RDC_EXC_TIMMING_SMP_NUM_MASK) -#define RDC_EXC_TIMMING_SMP_NUM_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_NUM_MASK) >> RDC_EXC_TIMMING_SMP_NUM_SHIFT) - -/* - * SMP_RATE (RW) - * - * The period for excitation sample in clock cycle， - * 0: not allowed - * 1: 1 cycle - * 2: 2 cycles - * … - * 65535 : 65535 cycles - */ -#define RDC_EXC_TIMMING_SMP_RATE_MASK (0xFFFFU) -#define RDC_EXC_TIMMING_SMP_RATE_SHIFT (0U) -#define RDC_EXC_TIMMING_SMP_RATE_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_RATE_SHIFT) & RDC_EXC_TIMMING_SMP_RATE_MASK) -#define RDC_EXC_TIMMING_SMP_RATE_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_RATE_MASK) >> RDC_EXC_TIMMING_SMP_RATE_SHIFT) - -/* Bitfield definition for register: EXC_SCALING */ -/* - * AMP_EXP (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_EXC_SCALING_AMP_EXP_MASK (0xF0U) -#define RDC_EXC_SCALING_AMP_EXP_SHIFT (4U) -#define RDC_EXC_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_EXP_SHIFT) & RDC_EXC_SCALING_AMP_EXP_MASK) -#define RDC_EXC_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_EXP_MASK) >> RDC_EXC_SCALING_AMP_EXP_SHIFT) - -/* - * AMP_MAN (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_EXC_SCALING_AMP_MAN_MASK (0xFU) -#define RDC_EXC_SCALING_AMP_MAN_SHIFT (0U) -#define RDC_EXC_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_MAN_SHIFT) & RDC_EXC_SCALING_AMP_MAN_MASK) -#define RDC_EXC_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_MAN_MASK) >> RDC_EXC_SCALING_AMP_MAN_SHIFT) - -/* Bitfield definition for register: EXC_OFFSET */ -/* - * AMP_OFFSET (RW) - * - * Offset for excitation - */ -#define RDC_EXC_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) -#define RDC_EXC_OFFSET_AMP_OFFSET_SHIFT (0U) -#define RDC_EXC_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) -#define RDC_EXC_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) >> RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) - -/* Bitfield definition for register: PWM_SCALING */ -/* - * N_POL (RW) - * - * Polarity of exc_n signal - * 0: high active - * 1: low active - */ -#define RDC_PWM_SCALING_N_POL_MASK (0x2000U) -#define RDC_PWM_SCALING_N_POL_SHIFT (13U) -#define RDC_PWM_SCALING_N_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_N_POL_SHIFT) & RDC_PWM_SCALING_N_POL_MASK) -#define RDC_PWM_SCALING_N_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_N_POL_MASK) >> RDC_PWM_SCALING_N_POL_SHIFT) - -/* - * P_POL (RW) - * - * Polarity of exc_p signal - * 0: high active - * 1: low active - */ -#define RDC_PWM_SCALING_P_POL_MASK (0x1000U) -#define RDC_PWM_SCALING_P_POL_SHIFT (12U) -#define RDC_PWM_SCALING_P_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_P_POL_SHIFT) & RDC_PWM_SCALING_P_POL_MASK) -#define RDC_PWM_SCALING_P_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_P_POL_MASK) >> RDC_PWM_SCALING_P_POL_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither of pwm - * 0: disable - * 1: enable - */ -#define RDC_PWM_SCALING_DITHER_MASK (0x100U) -#define RDC_PWM_SCALING_DITHER_SHIFT (8U) -#define RDC_PWM_SCALING_DITHER_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_DITHER_SHIFT) & RDC_PWM_SCALING_DITHER_MASK) -#define RDC_PWM_SCALING_DITHER_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_DITHER_MASK) >> RDC_PWM_SCALING_DITHER_SHIFT) - -/* - * AMP_EXP (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_PWM_SCALING_AMP_EXP_MASK (0xF0U) -#define RDC_PWM_SCALING_AMP_EXP_SHIFT (4U) -#define RDC_PWM_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_EXP_SHIFT) & RDC_PWM_SCALING_AMP_EXP_MASK) -#define RDC_PWM_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_EXP_MASK) >> RDC_PWM_SCALING_AMP_EXP_SHIFT) - -/* - * AMP_MAN (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_PWM_SCALING_AMP_MAN_MASK (0xFU) -#define RDC_PWM_SCALING_AMP_MAN_SHIFT (0U) -#define RDC_PWM_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_MAN_SHIFT) & RDC_PWM_SCALING_AMP_MAN_MASK) -#define RDC_PWM_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_MAN_MASK) >> RDC_PWM_SCALING_AMP_MAN_SHIFT) - -/* Bitfield definition for register: PWM_OFFSET */ -/* - * AMP_OFFSET (RW) - * - * Offset for excitation - */ -#define RDC_PWM_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) -#define RDC_PWM_OFFSET_AMP_OFFSET_SHIFT (0U) -#define RDC_PWM_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) -#define RDC_PWM_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) >> RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) - -/* Bitfield definition for register: TRIG_OUT0_CFG */ -/* - * ENABLE (RW) - * - * Enable trigger out0 - * 0: disable - * 1: enable - */ -#define RDC_TRIG_OUT0_CFG_ENABLE_MASK (0x100000UL) -#define RDC_TRIG_OUT0_CFG_ENABLE_SHIFT (20U) -#define RDC_TRIG_OUT0_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) -#define RDC_TRIG_OUT0_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) >> RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) - -/* - * LEAD_TIM (RW) - * - * Lead time for trigger out0 from center of low level , this is a signed value - * … - * 2: 2 cycle befor center of low level - * 1: 1 cycle before center of low level - * 0: center of low level - * -1: 1cycle after center of low level - * -2: 2cycle after center of low level - */ -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK (0xFFFFFUL) -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT (0U) -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) - -/* Bitfield definition for register: TRIG_OUT1_CFG */ -/* - * ENABLE (RW) - * - * Enable trigger out1 - * 0: disable - * 1: enable - */ -#define RDC_TRIG_OUT1_CFG_ENABLE_MASK (0x100000UL) -#define RDC_TRIG_OUT1_CFG_ENABLE_SHIFT (20U) -#define RDC_TRIG_OUT1_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) -#define RDC_TRIG_OUT1_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) >> RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) - -/* - * LEAD_TIM (RW) - * - * Lead time for trigger out0 from center of hight level , this is a signed value - * … - * 2: 2 cycle befor center of hight level - * 1: 1 cycle before center of hight level - * 0: center of hight level - * -1: 1cycle after center of hight level - * -2: 2cycle after center of hight level - */ -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK (0xFFFFFUL) -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT (0U) -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) - -/* Bitfield definition for register: PWM_DZ */ -/* - * DZ_N (RW) - * - * Exc_n dead zone in clock cycle before swap - * 0: no dead zone - * 1: 1 cycle dead zone - * 2: 2 cycle dead zone - * … - */ -#define RDC_PWM_DZ_DZ_N_MASK (0xFF00U) -#define RDC_PWM_DZ_DZ_N_SHIFT (8U) -#define RDC_PWM_DZ_DZ_N_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_N_SHIFT) & RDC_PWM_DZ_DZ_N_MASK) -#define RDC_PWM_DZ_DZ_N_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_N_MASK) >> RDC_PWM_DZ_DZ_N_SHIFT) - -/* - * DZ_P (RW) - * - * Exc_p dead zone in clock cycle before swap - * 0: no dead zone - * 1: 1 cycle dead zone - * 2: 2 cycle dead zone - * … - */ -#define RDC_PWM_DZ_DZ_P_MASK (0xFFU) -#define RDC_PWM_DZ_DZ_P_SHIFT (0U) -#define RDC_PWM_DZ_DZ_P_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_P_SHIFT) & RDC_PWM_DZ_DZ_P_MASK) -#define RDC_PWM_DZ_DZ_P_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_P_MASK) >> RDC_PWM_DZ_DZ_P_SHIFT) - -/* Bitfield definition for register: SYNC_OUT_CTRL */ -/* - * PWM_OUT_DLY (RO) - * - * Delay bettween the delyed trigger and the first pwm pulse in clock cycle - * 1: 1 cycle - * 2: 2 cycle - * … - */ -#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK (0xFFFF0000UL) -#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT (16U) -#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK) >> RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT) - -/* - * MIN2TRIG_EN (RW) - * - * Enable trigger out from the min point of exciting signal - * 1: enable - * 0: disable - */ -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK (0x20U) -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT (5U) -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) - -/* - * MAX2TRIG_EN (RW) - * - * Enable trigger out from the max point of exciting signal - * 1: enable - * 0: disable - */ -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK (0x10U) -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT (4U) -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) - -/* - * SYNC_OUT_SEL (RW) - * - * Select output synchornize signal - * 0: 0 phase of internal exciting signal - * 1: 90 phase of internal exciting signal - * 2: 180 phase of internal exciting signal - * 3: 270 phase of internal exciting signal - */ -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK (0x3U) -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT (0U) -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) >> RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) - -/* Bitfield definition for register: EXC_SYNC_DLY */ -/* - * DISABLE (RW) - * - * Disable hardware trigger input - * 0: enable - * 1: disable - */ -#define RDC_EXC_SYNC_DLY_DISABLE_MASK (0x1000000UL) -#define RDC_EXC_SYNC_DLY_DISABLE_SHIFT (24U) -#define RDC_EXC_SYNC_DLY_DISABLE_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DISABLE_SHIFT) & RDC_EXC_SYNC_DLY_DISABLE_MASK) -#define RDC_EXC_SYNC_DLY_DISABLE_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DISABLE_MASK) >> RDC_EXC_SYNC_DLY_DISABLE_SHIFT) - -/* - * DELAY (RW) - * - * Trigger in delay timming in bus cycle from rising edge of trigger signal - * 0: 1 cycle - * 1: 2 cycle - * … - * 0xffffff: 2^24 cycle - */ -#define RDC_EXC_SYNC_DLY_DELAY_MASK (0xFFFFFFUL) -#define RDC_EXC_SYNC_DLY_DELAY_SHIFT (0U) -#define RDC_EXC_SYNC_DLY_DELAY_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DELAY_SHIFT) & RDC_EXC_SYNC_DLY_DELAY_MASK) -#define RDC_EXC_SYNC_DLY_DELAY_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DELAY_MASK) >> RDC_EXC_SYNC_DLY_DELAY_SHIFT) - -/* Bitfield definition for register: MAX_I */ -/* - * MAX (RWC) - * - * Max value of i_channel, write clear - */ -#define RDC_MAX_I_MAX_MASK (0xFFFFFF00UL) -#define RDC_MAX_I_MAX_SHIFT (8U) -#define RDC_MAX_I_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_I_MAX_SHIFT) & RDC_MAX_I_MAX_MASK) -#define RDC_MAX_I_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_I_MAX_MASK) >> RDC_MAX_I_MAX_SHIFT) - -/* - * VALID (RWC) - * - * Max value valid, write clear - * 0: max value is not valid - * 1: max value is valid - */ -#define RDC_MAX_I_VALID_MASK (0x1U) -#define RDC_MAX_I_VALID_SHIFT (0U) -#define RDC_MAX_I_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_I_VALID_SHIFT) & RDC_MAX_I_VALID_MASK) -#define RDC_MAX_I_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_I_VALID_MASK) >> RDC_MAX_I_VALID_SHIFT) - -/* Bitfield definition for register: MIN_I */ -/* - * MIN (RWC) - * - * Min value of i_channel, write clear - */ -#define RDC_MIN_I_MIN_MASK (0xFFFFFF00UL) -#define RDC_MIN_I_MIN_SHIFT (8U) -#define RDC_MIN_I_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_I_MIN_SHIFT) & RDC_MIN_I_MIN_MASK) -#define RDC_MIN_I_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_I_MIN_MASK) >> RDC_MIN_I_MIN_SHIFT) - -/* - * VALID (RWC) - * - * Min value valid, write clear - * 0: min value is not valid - * 1: min value is valid - */ -#define RDC_MIN_I_VALID_MASK (0x1U) -#define RDC_MIN_I_VALID_SHIFT (0U) -#define RDC_MIN_I_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_I_VALID_SHIFT) & RDC_MIN_I_VALID_MASK) -#define RDC_MIN_I_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_I_VALID_MASK) >> RDC_MIN_I_VALID_SHIFT) - -/* Bitfield definition for register: MAX_Q */ -/* - * MAX (RWC) - * - * Max value of q_channel, write clear - */ -#define RDC_MAX_Q_MAX_MASK (0xFFFFFF00UL) -#define RDC_MAX_Q_MAX_SHIFT (8U) -#define RDC_MAX_Q_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_Q_MAX_SHIFT) & RDC_MAX_Q_MAX_MASK) -#define RDC_MAX_Q_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_Q_MAX_MASK) >> RDC_MAX_Q_MAX_SHIFT) - -/* - * VALID (RWC) - * - * Max value valid, write clear - * 0: max value is not valid - * 1: max value is valid - */ -#define RDC_MAX_Q_VALID_MASK (0x1U) -#define RDC_MAX_Q_VALID_SHIFT (0U) -#define RDC_MAX_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_Q_VALID_SHIFT) & RDC_MAX_Q_VALID_MASK) -#define RDC_MAX_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_Q_VALID_MASK) >> RDC_MAX_Q_VALID_SHIFT) - -/* Bitfield definition for register: MIN_Q */ -/* - * MIN (RWC) - * - * Min value of q_channel, write clear - */ -#define RDC_MIN_Q_MIN_MASK (0xFFFFFF00UL) -#define RDC_MIN_Q_MIN_SHIFT (8U) -#define RDC_MIN_Q_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_Q_MIN_SHIFT) & RDC_MIN_Q_MIN_MASK) -#define RDC_MIN_Q_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_Q_MIN_MASK) >> RDC_MIN_Q_MIN_SHIFT) - -/* - * VALID (RWC) - * - * Min value valid, write clear - * 0: min value is not valid - * 1: min value is valid - */ -#define RDC_MIN_Q_VALID_MASK (0x1U) -#define RDC_MIN_Q_VALID_SHIFT (0U) -#define RDC_MIN_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_Q_VALID_SHIFT) & RDC_MIN_Q_VALID_MASK) -#define RDC_MIN_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_Q_VALID_MASK) >> RDC_MIN_Q_VALID_SHIFT) - -/* Bitfield definition for register: THRS_I */ -/* - * THRS (RW) - * - * The offset setting for edge detection of the i_channel, signed number - * … - * 2: the offset is 0x800000+2 - * 1: the offset is 0x800000+1 - * 0: the offset is 0x800000 - * -1: the offset is 0x800000-1 - * -2: the offset is 0x800000-2 - * … - */ -#define RDC_THRS_I_THRS_MASK (0xFFFFFF00UL) -#define RDC_THRS_I_THRS_SHIFT (8U) -#define RDC_THRS_I_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_I_THRS_SHIFT) & RDC_THRS_I_THRS_MASK) -#define RDC_THRS_I_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_I_THRS_MASK) >> RDC_THRS_I_THRS_SHIFT) - -/* Bitfield definition for register: THRS_Q */ -/* - * THRS (RW) - * - * The offset setting for edge detection of the q_channel, signed number - * … - * 2: the offset is 0x800000+2 - * 1: the offset is 0x800000+1 - * 0: the offset is 0x800000 - * -1: the offset is 0x800000-1 - * -2: the offset is 0x800000-2 - * … - */ -#define RDC_THRS_Q_THRS_MASK (0xFFFFFF00UL) -#define RDC_THRS_Q_THRS_SHIFT (8U) -#define RDC_THRS_Q_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_Q_THRS_SHIFT) & RDC_THRS_Q_THRS_MASK) -#define RDC_THRS_Q_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_Q_THRS_MASK) >> RDC_THRS_Q_THRS_SHIFT) - -/* Bitfield definition for register: EDG_DET_CTL */ -/* - * HOLD (RW) - * - * The minimum edge distance in sample - * 0:1 sample - * 1:2 sample - * 2:3 samples - * … - * 63:64 samples - */ -#define RDC_EDG_DET_CTL_HOLD_MASK (0x3F0U) -#define RDC_EDG_DET_CTL_HOLD_SHIFT (4U) -#define RDC_EDG_DET_CTL_HOLD_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_HOLD_SHIFT) & RDC_EDG_DET_CTL_HOLD_MASK) -#define RDC_EDG_DET_CTL_HOLD_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_HOLD_MASK) >> RDC_EDG_DET_CTL_HOLD_SHIFT) - -/* - * FILTER (RW) - * - * The continuous positive or negative number for edge detection - * 0: 1 - * 1: 2 - * … - * 7: 8 - */ -#define RDC_EDG_DET_CTL_FILTER_MASK (0x7U) -#define RDC_EDG_DET_CTL_FILTER_SHIFT (0U) -#define RDC_EDG_DET_CTL_FILTER_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_FILTER_SHIFT) & RDC_EDG_DET_CTL_FILTER_MASK) -#define RDC_EDG_DET_CTL_FILTER_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_FILTER_MASK) >> RDC_EDG_DET_CTL_FILTER_SHIFT) - -/* Bitfield definition for register: ACC_SCALING */ -/* - * TOXIC_LK (RW) - * - * Toxic accumulation data be removed control - * 1: enable - * 0: disable - */ -#define RDC_ACC_SCALING_TOXIC_LK_MASK (0x100U) -#define RDC_ACC_SCALING_TOXIC_LK_SHIFT (8U) -#define RDC_ACC_SCALING_TOXIC_LK_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_TOXIC_LK_SHIFT) & RDC_ACC_SCALING_TOXIC_LK_MASK) -#define RDC_ACC_SCALING_TOXIC_LK_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_TOXIC_LK_MASK) >> RDC_ACC_SCALING_TOXIC_LK_SHIFT) - -/* - * ACC_SHIFT (RW) - * - * Accumulation value shift control, this is a sign number. - * 0: {acc[39],acc[38:8]} - * 1: {acc[39],acc[37:7]} - * 2: {acc[39],acc[36:6]} - * … - * 7: {acc[39],acc[31:1]} - * 8: {acc[39],acc[30:0]} - * 9: acc/2^9 - * 10: acc/2^10 - * … - * 15:acc/2^15 - */ -#define RDC_ACC_SCALING_ACC_SHIFT_MASK (0xFU) -#define RDC_ACC_SCALING_ACC_SHIFT_SHIFT (0U) -#define RDC_ACC_SCALING_ACC_SHIFT_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_ACC_SHIFT_SHIFT) & RDC_ACC_SCALING_ACC_SHIFT_MASK) -#define RDC_ACC_SCALING_ACC_SHIFT_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_ACC_SHIFT_MASK) >> RDC_ACC_SCALING_ACC_SHIFT_SHIFT) - -/* Bitfield definition for register: EXC_PERIOD */ -/* - * EXC_PERIOD (RW) - * - * The num in clock cycle for period of excitation - * 0: invalid value - * 1:1 cycle - * 2:2 cycles - * … - */ -#define RDC_EXC_PERIOD_EXC_PERIOD_MASK (0xFFFFFFFFUL) -#define RDC_EXC_PERIOD_EXC_PERIOD_SHIFT (0U) -#define RDC_EXC_PERIOD_EXC_PERIOD_SET(x) (((uint32_t)(x) << RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) -#define RDC_EXC_PERIOD_EXC_PERIOD_GET(x) (((uint32_t)(x) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) >> RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) - -/* Bitfield definition for register: SYNC_DELAY_I */ -/* - * DELAY (RW) - * - * Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. - * 0: invalid value - * 1: 1 cycles - * 2: 2 cycles - * ... - */ -#define RDC_SYNC_DELAY_I_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_SYNC_DELAY_I_DELAY_SHIFT (0U) -#define RDC_SYNC_DELAY_I_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_I_DELAY_SHIFT) & RDC_SYNC_DELAY_I_DELAY_MASK) -#define RDC_SYNC_DELAY_I_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_I_DELAY_MASK) >> RDC_SYNC_DELAY_I_DELAY_SHIFT) - -/* Bitfield definition for register: RISE_DELAY_I */ -/* - * RISE_DELAY (RO) - * - * Delay value on rising edge of i_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_RISE_DELAY_I_RISE_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_RISE_DELAY_I_RISE_DELAY_SHIFT (0U) -#define RDC_RISE_DELAY_I_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_I_RISE_DELAY_MASK) >> RDC_RISE_DELAY_I_RISE_DELAY_SHIFT) - -/* Bitfield definition for register: FALL_DELAY_I */ -/* - * FALL_DELAY (RO) - * - * Delay value on falling edge of i_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_FALL_DELAY_I_FALL_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_FALL_DELAY_I_FALL_DELAY_SHIFT (0U) -#define RDC_FALL_DELAY_I_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_I_FALL_DELAY_MASK) >> RDC_FALL_DELAY_I_FALL_DELAY_SHIFT) - -/* Bitfield definition for register: SAMPLE_RISE_I */ -/* - * VALUE (RO) - * - * sample value on rising edge of rectify signal - */ -#define RDC_SAMPLE_RISE_I_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_RISE_I_VALUE_SHIFT (8U) -#define RDC_SAMPLE_RISE_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_I_VALUE_MASK) >> RDC_SAMPLE_RISE_I_VALUE_SHIFT) - -/* Bitfield definition for register: SAMPLE_FALL_I */ -/* - * VALUE (RO) - * - * sample value on falling edge of rectify signal - */ -#define RDC_SAMPLE_FALL_I_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_FALL_I_VALUE_SHIFT (8U) -#define RDC_SAMPLE_FALL_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_I_VALUE_MASK) >> RDC_SAMPLE_FALL_I_VALUE_SHIFT) - -/* Bitfield definition for register: ACC_CNT_I */ -/* - * CNT_NEG (RO) - * - * sample number during the negtive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_ACC_CNT_I_CNT_NEG_SHIFT (16U) -#define RDC_ACC_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_NEG_MASK) >> RDC_ACC_CNT_I_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * sample number during the positive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_I_CNT_POS_MASK (0xFFFFU) -#define RDC_ACC_CNT_I_CNT_POS_SHIFT (0U) -#define RDC_ACC_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_POS_MASK) >> RDC_ACC_CNT_I_CNT_POS_SHIFT) - -/* Bitfield definition for register: SIGN_CNT_I */ -/* - * CNT_NEG (RO) - * - * Positive sample counter during negative rectify signal - */ -#define RDC_SIGN_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_SIGN_CNT_I_CNT_NEG_SHIFT (16U) -#define RDC_SIGN_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_NEG_MASK) >> RDC_SIGN_CNT_I_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * Negative sample counter during positive rectify signal - */ -#define RDC_SIGN_CNT_I_CNT_POS_MASK (0xFFFFU) -#define RDC_SIGN_CNT_I_CNT_POS_SHIFT (0U) -#define RDC_SIGN_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_POS_MASK) >> RDC_SIGN_CNT_I_CNT_POS_SHIFT) - -/* Bitfield definition for register: SYNC_DELAY_Q */ -/* - * DELAY (RW) - * - * Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. - * 0: invalid value - * 1: 1 cycles - * 2: 2 cycles - * ... - */ -#define RDC_SYNC_DELAY_Q_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_SYNC_DELAY_Q_DELAY_SHIFT (0U) -#define RDC_SYNC_DELAY_Q_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_Q_DELAY_SHIFT) & RDC_SYNC_DELAY_Q_DELAY_MASK) -#define RDC_SYNC_DELAY_Q_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_Q_DELAY_MASK) >> RDC_SYNC_DELAY_Q_DELAY_SHIFT) - -/* Bitfield definition for register: RISE_DELAY_Q */ -/* - * RISE_DELAY (RO) - * - * Delay value on rising edge of q_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_RISE_DELAY_Q_RISE_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT (0U) -#define RDC_RISE_DELAY_Q_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_Q_RISE_DELAY_MASK) >> RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT) - -/* Bitfield definition for register: FALL_DELAY_Q */ -/* - * FALL_DELAY (RO) - * - * Delay value on falling edge of q_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_FALL_DELAY_Q_FALL_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT (0U) -#define RDC_FALL_DELAY_Q_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_Q_FALL_DELAY_MASK) >> RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT) - -/* Bitfield definition for register: SAMPLE_RISE_Q */ -/* - * VALUE (RO) - * - * sample value on rising edge of rectify signal - */ -#define RDC_SAMPLE_RISE_Q_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_RISE_Q_VALUE_SHIFT (8U) -#define RDC_SAMPLE_RISE_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_Q_VALUE_MASK) >> RDC_SAMPLE_RISE_Q_VALUE_SHIFT) - -/* Bitfield definition for register: SAMPLE_FALL_Q */ -/* - * VALUE (RO) - * - * sample value on falling edge of rectify signal - */ -#define RDC_SAMPLE_FALL_Q_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_FALL_Q_VALUE_SHIFT (8U) -#define RDC_SAMPLE_FALL_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_Q_VALUE_MASK) >> RDC_SAMPLE_FALL_Q_VALUE_SHIFT) - -/* Bitfield definition for register: ACC_CNT_Q */ -/* - * CNT_NEG (RO) - * - * sample number during the negtive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_ACC_CNT_Q_CNT_NEG_SHIFT (16U) -#define RDC_ACC_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_NEG_MASK) >> RDC_ACC_CNT_Q_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * sample number during the positive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_Q_CNT_POS_MASK (0xFFFFU) -#define RDC_ACC_CNT_Q_CNT_POS_SHIFT (0U) -#define RDC_ACC_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_POS_MASK) >> RDC_ACC_CNT_Q_CNT_POS_SHIFT) - -/* Bitfield definition for register: SIGN_CNT_Q */ -/* - * CNT_NEG (RO) - * - * Positive sample counter during negative rectify signal - */ -#define RDC_SIGN_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_SIGN_CNT_Q_CNT_NEG_SHIFT (16U) -#define RDC_SIGN_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_NEG_MASK) >> RDC_SIGN_CNT_Q_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * Negative sample counter during positive rectify signal - */ -#define RDC_SIGN_CNT_Q_CNT_POS_MASK (0xFFFFU) -#define RDC_SIGN_CNT_Q_CNT_POS_SHIFT (0U) -#define RDC_SIGN_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_POS_MASK) >> RDC_SIGN_CNT_Q_CNT_POS_SHIFT) - -/* Bitfield definition for register: AMP_MAX */ -/* - * MAX (RW) - * - * the maximum of acc amplitude - */ -#define RDC_AMP_MAX_MAX_MASK (0xFFFFFFFFUL) -#define RDC_AMP_MAX_MAX_SHIFT (0U) -#define RDC_AMP_MAX_MAX_SET(x) (((uint32_t)(x) << RDC_AMP_MAX_MAX_SHIFT) & RDC_AMP_MAX_MAX_MASK) -#define RDC_AMP_MAX_MAX_GET(x) (((uint32_t)(x) & RDC_AMP_MAX_MAX_MASK) >> RDC_AMP_MAX_MAX_SHIFT) - -/* Bitfield definition for register: AMP_MIN */ -/* - * MIN (RW) - * - * the minimum of acc amplitude - */ -#define RDC_AMP_MIN_MIN_MASK (0xFFFFFFFFUL) -#define RDC_AMP_MIN_MIN_SHIFT (0U) -#define RDC_AMP_MIN_MIN_SET(x) (((uint32_t)(x) << RDC_AMP_MIN_MIN_SHIFT) & RDC_AMP_MIN_MIN_MASK) -#define RDC_AMP_MIN_MIN_GET(x) (((uint32_t)(x) & RDC_AMP_MIN_MIN_MASK) >> RDC_AMP_MIN_MIN_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * INT_EN (RW) - * - * enable interrupt output - */ -#define RDC_INT_EN_INT_EN_MASK (0x80000000UL) -#define RDC_INT_EN_INT_EN_SHIFT (31U) -#define RDC_INT_EN_INT_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_INT_EN_SHIFT) & RDC_INT_EN_INT_EN_MASK) -#define RDC_INT_EN_INT_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_INT_EN_MASK) >> RDC_INT_EN_INT_EN_SHIFT) - -/* - * ACC_VLD_I_EN (RW) - * - * i_channel accumulate valid interrupt enable for i_channel - */ -#define RDC_INT_EN_ACC_VLD_I_EN_MASK (0x8000U) -#define RDC_INT_EN_ACC_VLD_I_EN_SHIFT (15U) -#define RDC_INT_EN_ACC_VLD_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_EN_MASK) -#define RDC_INT_EN_ACC_VLD_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_EN_SHIFT) - -/* - * ACC_VLD_Q_EN (RW) - * - * q_channel accumulate valid interrupt enable for i_channel - */ -#define RDC_INT_EN_ACC_VLD_Q_EN_MASK (0x4000U) -#define RDC_INT_EN_ACC_VLD_Q_EN_SHIFT (14U) -#define RDC_INT_EN_ACC_VLD_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) -#define RDC_INT_EN_ACC_VLD_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) - -/* - * RISING_DELAY_I_EN (RW) - * - * i_channel delayed rectify signal rising edge interrupt enable - */ -#define RDC_INT_EN_RISING_DELAY_I_EN_MASK (0x2000U) -#define RDC_INT_EN_RISING_DELAY_I_EN_SHIFT (13U) -#define RDC_INT_EN_RISING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) -#define RDC_INT_EN_RISING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) >> RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) - -/* - * FALLING_DELAY_I_EN (RW) - * - * i_channel delayed rectify signal falling edge interrupt enable - */ -#define RDC_INT_EN_FALLING_DELAY_I_EN_MASK (0x1000U) -#define RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT (12U) -#define RDC_INT_EN_FALLING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) -#define RDC_INT_EN_FALLING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) - -/* - * RISING_DELAY_Q_EN (RW) - * - * q_channel delayed rectify signal rising edge interrupt enable - */ -#define RDC_INT_EN_RISING_DELAY_Q_EN_MASK (0x800U) -#define RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT (11U) -#define RDC_INT_EN_RISING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) -#define RDC_INT_EN_RISING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) >> RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) - -/* - * FALLING_DELAY_Q_EN (RW) - * - * q_channel delayed rectify signal falling edge interrupt enable - */ -#define RDC_INT_EN_FALLING_DELAY_Q_EN_MASK (0x400U) -#define RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT (10U) -#define RDC_INT_EN_FALLING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) -#define RDC_INT_EN_FALLING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) - -/* - * SAMPLE_RISING_I_EN (RW) - * - * i_channel rising edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_RISING_I_EN_MASK (0x200U) -#define RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT (9U) -#define RDC_INT_EN_SAMPLE_RISING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) -#define RDC_INT_EN_SAMPLE_RISING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) - -/* - * SAMPLE_FALLING_I_EN (RW) - * - * i_channel falling edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK (0x100U) -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT (8U) -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) - -/* - * SAMPLE_RISING_Q_EN (RW) - * - * q_channel rising edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK (0x80U) -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT (7U) -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) - -/* - * SAMPLE_FALLING_Q_EN (RW) - * - * q_channel falling edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK (0x40U) -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT (6U) -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) - -/* - * ACC_VLD_I_OVH_EN (RW) - * - * i_channel accumulate overflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK (0x20U) -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT (5U) -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) - -/* - * ACC_VLD_Q_OVH_EN (RW) - * - * q_channel accumulate overflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK (0x10U) -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT (4U) -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) - -/* - * ACC_VLD_I_OVL_EN (RW) - * - * i_channel accumulate underflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK (0x8U) -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT (3U) -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) - -/* - * ACC_VLD_Q_OVL_EN (RW) - * - * q_channel accumulate underflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK (0x4U) -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT (2U) -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) - -/* - * ACC_AMP_OVH_EN (RW) - * - * accumulate ample overflow interrupt enable - */ -#define RDC_INT_EN_ACC_AMP_OVH_EN_MASK (0x2U) -#define RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT (1U) -#define RDC_INT_EN_ACC_AMP_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) -#define RDC_INT_EN_ACC_AMP_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) - -/* - * ACC_AMP_OVL_EN (RW) - * - * accumulate ample underflow interrupt enable - */ -#define RDC_INT_EN_ACC_AMP_OVL_EN_MASK (0x1U) -#define RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT (0U) -#define RDC_INT_EN_ACC_AMP_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) -#define RDC_INT_EN_ACC_AMP_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) - -/* Bitfield definition for register: ADC_INT_STATE */ -/* - * ACC_VLD_I_STA (W1C) - * - * i_channel accumulate valid interrupt status for i_channel - */ -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK (0x8000U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT (15U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) - -/* - * ACC_VLD_Q_STA (W1C) - * - * q_channel accumulate valid interrupt status for i_channel - */ -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK (0x4000U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT (14U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) - -/* - * RISING_DELAY_I_STA (W1C) - * - * i_channel delayed rectify signal rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK (0x2000U) -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT (13U) -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) - -/* - * FALLING_DELAY_I_STA (W1C) - * - * i_channel delayed rectify signal falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK (0x1000U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT (12U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) - -/* - * RISING_DELAY_Q_STA (W1C) - * - * q_channel delayed rectify signal rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK (0x800U) -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT (11U) -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) - -/* - * FALLING_DELAY_Q_STA (W1C) - * - * q_channel delayed rectify signal falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK (0x400U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT (10U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) - -/* - * SAMPLE_RISING_I_STA (W1C) - * - * i_channel rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK (0x200U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT (9U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) - -/* - * SAMPLE_FALLING_I_STA (W1C) - * - * i_channel falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK (0x100U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT (8U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) - -/* - * SAMPLE_RISING_Q_STA (W1C) - * - * q_channel rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK (0x80U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT (7U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) - -/* - * SAMPLE_FALLING_Q_STA (W1C) - * - * q_channel falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK (0x40U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT (6U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) - -/* - * ACC_VLD_I_OVH_STA (W1C) - * - * i_channel accumulate overflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK (0x20U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT (5U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) - -/* - * ACC_VLD_Q_OVH_STA (W1C) - * - * q_channel accumulate overflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK (0x10U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT (4U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) - -/* - * ACC_VLD_I_OVL_STA (W1C) - * - * i_channel accumulate underflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK (0x8U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT (3U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) - -/* - * ACC_VLD_Q_OVL_STA (W1C) - * - * q_channel accumulate underflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK (0x4U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT (2U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) - -/* - * ACC_AMP_OVH_STA (W1C) - * - * accumulate ample overflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK (0x2U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT (1U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) - -/* - * ACC_AMP_OVL_STA (W1C) - * - * accumulate ample underflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK (0x1U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT (0U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) - - - - -#endif /* HPM_RDC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_rng_regs.h deleted file mode 100644 index 1a847f5d090..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_rng_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RNG_H -#define HPM_RNG_H - -typedef struct { - __RW uint32_t CMD; /* 0x0: Command Register */ - __RW uint32_t CTRL; /* 0x4: Control Register */ - __R uint32_t STA; /* 0x8: Status Register */ - __R uint32_t ERR; /* 0xC: Error Registers */ - __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ -} RNG_Type; - - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. - * 0 Do not perform a software reset. - * 1 Software reset - */ -#define RNG_CMD_SFTRST_MASK (0x40U) -#define RNG_CMD_SFTRST_SHIFT (6U) -#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) -#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) - -/* - * CLRERR (RW) - * - * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. - * 0 Do not clear the errors and the interrupt. - * 1 Clear the errors and the interrupt. - */ -#define RNG_CMD_CLRERR_MASK (0x20U) -#define RNG_CMD_CLRERR_SHIFT (5U) -#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) -#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) - -/* - * CLRINT (RW) - * - * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. - * 0 Do not clear the interrupt. - * 1 Clear the interrupt - */ -#define RNG_CMD_CLRINT_MASK (0x10U) -#define RNG_CMD_CLRINT_SHIFT (4U) -#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) -#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) - -/* - * GENSD (RW) - * - * Generate Seed, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_GENSD_MASK (0x2U) -#define RNG_CMD_GENSD_SHIFT (1U) -#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) -#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) - -/* - * SLFCHK (RW) - * - * Self Test, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_SLFCHK_MASK (0x1U) -#define RNG_CMD_SLFCHK_SHIFT (0U) -#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) -#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * MIRQERR (RW) - * - * Mask Interrupt Request for Error - */ -#define RNG_CTRL_MIRQERR_MASK (0x40U) -#define RNG_CTRL_MIRQERR_SHIFT (6U) -#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) -#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) - -/* - * MIRQDN (RW) - * - * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: - * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). - * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - */ -#define RNG_CTRL_MIRQDN_MASK (0x20U) -#define RNG_CTRL_MIRQDN_SHIFT (5U) -#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) -#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) - -/* - * AUTRSD (RW) - * - * Auto Reseed - */ -#define RNG_CTRL_AUTRSD_MASK (0x10U) -#define RNG_CTRL_AUTRSD_SHIFT (4U) -#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) -#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) - -/* - * FUFMOD (RW) - * - * FIFO underflow response mode - * 00 Return all zeros and set the ESR[FUFE]. - * 01 Return all zeros and set the ESR[FUFE]. - * 10 Generate the bus transfer error - * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - */ -#define RNG_CTRL_FUFMOD_MASK (0x3U) -#define RNG_CTRL_FUFMOD_SHIFT (0U) -#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) -#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * SCPF (RO) - * - * Self Check Pass Fail - */ -#define RNG_STA_SCPF_MASK (0xE00000UL) -#define RNG_STA_SCPF_SHIFT (21U) -#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) - -/* - * FUNCERR (RO) - * - * Error was detected, check ESR register for details - */ -#define RNG_STA_FUNCERR_MASK (0x10000UL) -#define RNG_STA_FUNCERR_SHIFT (16U) -#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) - -/* - * FSIZE (RO) - * - * Fifo Size, it is 5 in this design. - */ -#define RNG_STA_FSIZE_MASK (0xF000U) -#define RNG_STA_FSIZE_SHIFT (12U) -#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) - -/* - * FRNNU (RO) - * - * Fifo Level, Indicates the number of random words currently in the output FIFO - */ -#define RNG_STA_FRNNU_MASK (0xF00U) -#define RNG_STA_FRNNU_SHIFT (8U) -#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) - -/* - * NSDDN (RO) - * - * New seed done. - */ -#define RNG_STA_NSDDN_MASK (0x40U) -#define RNG_STA_NSDDN_SHIFT (6U) -#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) - -/* - * FSDDN (RO) - * - * 1st Seed done - * When "1", Indicates that the RNG generated the first seed. - */ -#define RNG_STA_FSDDN_MASK (0x20U) -#define RNG_STA_FSDDN_SHIFT (5U) -#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) - -/* - * SCDN (RO) - * - * Self Check Done - * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is - * initiated by setting the CMD[ST]. - * 0 Self test not completed - * 1 Completed a self test since the last reset. - */ -#define RNG_STA_SCDN_MASK (0x10U) -#define RNG_STA_SCDN_SHIFT (4U) -#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) - -/* - * RSDREQ (RO) - * - * Reseed needed - * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or - * automatically if the CTRL[ARS] is set. - */ -#define RNG_STA_RSDREQ_MASK (0x8U) -#define RNG_STA_RSDREQ_SHIFT (3U) -#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) - -/* - * IDLE (RO) - * - * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - */ -#define RNG_STA_IDLE_MASK (0x4U) -#define RNG_STA_IDLE_SHIFT (2U) -#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) - -/* - * BUSY (RO) - * - * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - */ -#define RNG_STA_BUSY_MASK (0x2U) -#define RNG_STA_BUSY_SHIFT (1U) -#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) - -/* Bitfield definition for register: ERR */ -/* - * FUFE (RO) - * - * FIFO access error(underflow) - */ -#define RNG_ERR_FUFE_MASK (0x20U) -#define RNG_ERR_FUFE_SHIFT (5U) -#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) - -/* - * SCKERR (RO) - * - * Self-test error - * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a - * hardware reset or by writing 1 to the CMD[CE] - */ -#define RNG_ERR_SCKERR_MASK (0x8U) -#define RNG_ERR_SCKERR_SHIFT (3U) -#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) - -/* Bitfield definition for register: FO2B */ -/* - * FO2B (RO) - * - * SW read the FIFO output. - */ -#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) -#define RNG_FO2B_FO2B_SHIFT (0U) -#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) - -/* Bitfield definition for register array: R2SK */ -/* - * FO2S0 (RO) - * - * FIFO out to KMAN, will be SDP engine key. - */ -#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) -#define RNG_R2SK_FO2S0_SHIFT (0U) -#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) - - - -/* R2SK register group index macro definition */ -#define RNG_R2SK_FO2S0 (0UL) -#define RNG_R2SK_FO2S1 (1UL) -#define RNG_R2SK_FO2S2 (2UL) -#define RNG_R2SK_FO2S3 (3UL) -#define RNG_R2SK_FO2S4 (4UL) -#define RNG_R2SK_FO2S5 (5UL) -#define RNG_R2SK_FO2S6 (6UL) -#define RNG_R2SK_FO2S7 (7UL) - - -#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sdp_regs.h deleted file mode 100644 index 7562ad654a5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sdp_regs.h +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDP_H -#define HPM_SDP_H - -typedef struct { - __RW uint32_t SDPCR; /* 0x0: SDP control register */ - __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ - __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ - __RW uint32_t STA; /* 0xC: Status Registers */ - __RW uint32_t KEYADDR; /* 0x10: Key Address */ - __RW uint32_t KEYDAT; /* 0x14: Key Data */ - __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ - __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ - __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ - __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ - __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ - __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ - __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ - __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ -} SDP_Type; - - -/* Bitfield definition for register: SDPCR */ -/* - * SFTRST (RW) - * - * soft reset. - * Write 1 then 0, to reset the SDP block. - */ -#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) -#define SDP_SDPCR_SFTRST_SHIFT (31U) -#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) -#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) - -/* - * CLKGAT (RW) - * - * Clock Gate for the SDP main logic. - * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - */ -#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) -#define SDP_SDPCR_CLKGAT_SHIFT (30U) -#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) -#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) - -/* - * CIPDIS (RO) - * - * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. - * 1, Cipher is disabled in this chip. - * 0, Cipher is enabled in this chip. - */ -#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) -#define SDP_SDPCR_CIPDIS_SHIFT (29U) -#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) - -/* - * HASDIS (RO) - * - * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. - * 1, HASH is disabled in this chip. - * 0, HASH is enabled in this chip. - */ -#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) -#define SDP_SDPCR_HASDIS_SHIFT (28U) -#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) - -/* - * CIPHEN (RW) - * - * Cipher Enablement, controlled by SW. - * 1, Cipher is Enabled. - * 0, Cipher is Disabled. - */ -#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) -#define SDP_SDPCR_CIPHEN_SHIFT (23U) -#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) -#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) - -/* - * HASHEN (RW) - * - * HASH Enablement, controlled by SW. - * 1, HASH is Enabled. - * 0, HASH is Disabled. - */ -#define SDP_SDPCR_HASHEN_MASK (0x400000UL) -#define SDP_SDPCR_HASHEN_SHIFT (22U) -#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) -#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) - -/* - * MCPEN (RW) - * - * Memory Copy Enablement, controlled by SW. - * 1, Memory copy is Enabled. - * 0, Memory copy is Disabled. - */ -#define SDP_SDPCR_MCPEN_MASK (0x200000UL) -#define SDP_SDPCR_MCPEN_SHIFT (21U) -#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) -#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) - -/* - * CONFEN (RW) - * - * Constant Fill to memory, controlled by SW. - * 1, Constant fill is Enabled. - * 0, Constant fill is Disabled. - */ -#define SDP_SDPCR_CONFEN_MASK (0x100000UL) -#define SDP_SDPCR_CONFEN_SHIFT (20U) -#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) -#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) - -/* - * DCRPDI (RW) - * - * Decryption Disable bit, Write to 1 to disable the decryption. - */ -#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) -#define SDP_SDPCR_DCRPDI_SHIFT (19U) -#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) -#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) - -/* - * TSTPKT0IRQ (RW) - * - * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - */ -#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) -#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) -#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) -#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) - -/* - * RDSCEN (RW) - * - * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) - * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - */ -#define SDP_SDPCR_RDSCEN_MASK (0x100U) -#define SDP_SDPCR_RDSCEN_SHIFT (8U) -#define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK) -#define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT) - -/* - * INTEN (RW) - * - * Interrupt Enablement, controlled by SW. - * 1, SDP interrupt is enabled. - * 0, SDP interrupt is disabled. - */ -#define SDP_SDPCR_INTEN_MASK (0x1U) -#define SDP_SDPCR_INTEN_SHIFT (0U) -#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) -#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) - -/* Bitfield definition for register: MODCTRL */ -/* - * AESALG (RW) - * - * AES algorithem selection. - * 0x0 = AES 128; - * 0x1 = AES 256; - * 0x8 = SM4； - * Others, reserved. - */ -#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) -#define SDP_MODCTRL_AESALG_SHIFT (28U) -#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) -#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) - -/* - * AESMOD (RW) - * - * AES mode selection. - * 0x0 = ECB; - * 0x1 = CBC; - * Others, reserved. - */ -#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) -#define SDP_MODCTRL_AESMOD_SHIFT (24U) -#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) -#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) - -/* - * AESKS (RW) - * - * AES Key Selection. - * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: - * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. - * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * .... - * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. - * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. - * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. - * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. - * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. - * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. - * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. - * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. - * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. - * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. - * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. - * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. - * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. - * Other values, reserved. - */ -#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) -#define SDP_MODCTRL_AESKS_SHIFT (18U) -#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) -#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) - -/* - * AESDIR (RW) - * - * AES direction - * 1x1, AES Decryption - * 1x0, AES Encryption. - */ -#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) -#define SDP_MODCTRL_AESDIR_SHIFT (16U) -#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) -#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) - -/* - * HASALG (RW) - * - * HASH Algorithem selection. - * 0x0 SHA1 — - * 0x1 CRC32 — - * 0x2 SHA256 — - */ -#define SDP_MODCTRL_HASALG_MASK (0xF000U) -#define SDP_MODCTRL_HASALG_SHIFT (12U) -#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) -#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) - -/* - * HASCHK (RW) - * - * HASH Check Enable Bit. - * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; - * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. - * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - */ -#define SDP_MODCTRL_HASCHK_MASK (0x400U) -#define SDP_MODCTRL_HASCHK_SHIFT (10U) -#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) -#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) - -/* - * HASOUT (RW) - * - * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. - * 0 INPUT HASH - * 1 OUTPUT HASH - */ -#define SDP_MODCTRL_HASOUT_MASK (0x200U) -#define SDP_MODCTRL_HASOUT_SHIFT (9U) -#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) -#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) - -/* - * DINSWP (RW) - * - * Decide whether the SDP byteswaps the input data (big-endian data); - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DINSWP_MASK (0x30U) -#define SDP_MODCTRL_DINSWP_SHIFT (4U) -#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) -#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) - -/* - * DOUTSWP (RW) - * - * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) -#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) -#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) -#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) - -/* - * KEYSWP (RW) - * - * Decide whether the SDP byteswaps the Key (big-endian data). - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_KEYSWP_MASK (0x3U) -#define SDP_MODCTRL_KEYSWP_SHIFT (0U) -#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) -#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) - -/* Bitfield definition for register: PKTCNT */ -/* - * CNTVAL (RO) - * - * This read-only field shows the current (instantaneous) value of the packet counter - */ -#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) -#define SDP_PKTCNT_CNTVAL_SHIFT (16U) -#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) - -/* - * CNTINCR (RW) - * - * The value written to this field is added to the spacket count. - */ -#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) -#define SDP_PKTCNT_CNTINCR_SHIFT (0U) -#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) -#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TAG (RO) - * - * packet tag. - */ -#define SDP_STA_TAG_MASK (0xFF000000UL) -#define SDP_STA_TAG_SHIFT (24U) -#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) - -/* - * IRQ (W1C) - * - * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - */ -#define SDP_STA_IRQ_MASK (0x800000UL) -#define SDP_STA_IRQ_SHIFT (23U) -#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) -#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) - -/* - * CHN1PKT0 (W1C) - * - * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - */ -#define SDP_STA_CHN1PKT0_MASK (0x100000UL) -#define SDP_STA_CHN1PKT0_SHIFT (20U) -#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) -#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) - -/* - * AESBSY (RO) - * - * AES Busy - */ -#define SDP_STA_AESBSY_MASK (0x80000UL) -#define SDP_STA_AESBSY_SHIFT (19U) -#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) - -/* - * HASBSY (RO) - * - * Hashing Busy - */ -#define SDP_STA_HASBSY_MASK (0x40000UL) -#define SDP_STA_HASBSY_SHIFT (18U) -#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) - -/* - * PKTCNT0 (W1C) - * - * Packet Counter registers reachs to ZERO now. - */ -#define SDP_STA_PKTCNT0_MASK (0x20000UL) -#define SDP_STA_PKTCNT0_SHIFT (17U) -#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) -#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) - -/* - * PKTDON (W1C) - * - * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - */ -#define SDP_STA_PKTDON_MASK (0x10000UL) -#define SDP_STA_PKTDON_SHIFT (16U) -#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) -#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) - -/* - * ERRSET (W1C) - * - * Working mode setup error. - */ -#define SDP_STA_ERRSET_MASK (0x20U) -#define SDP_STA_ERRSET_SHIFT (5U) -#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) -#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) - -/* - * ERRPKT (W1C) - * - * Packet head access error, or status update error. - */ -#define SDP_STA_ERRPKT_MASK (0x10U) -#define SDP_STA_ERRPKT_SHIFT (4U) -#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) -#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) - -/* - * ERRSRC (W1C) - * - * Source Buffer Access Error - */ -#define SDP_STA_ERRSRC_MASK (0x8U) -#define SDP_STA_ERRSRC_SHIFT (3U) -#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) -#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) - -/* - * ERRDST (W1C) - * - * Destination Buffer Error - */ -#define SDP_STA_ERRDST_MASK (0x4U) -#define SDP_STA_ERRDST_SHIFT (2U) -#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) -#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) - -/* - * ERRHAS (W1C) - * - * Hashing Check Error - */ -#define SDP_STA_ERRHAS_MASK (0x2U) -#define SDP_STA_ERRHAS_SHIFT (1U) -#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) -#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) - -/* - * ERRCHAIN (W1C) - * - * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - */ -#define SDP_STA_ERRCHAIN_MASK (0x1U) -#define SDP_STA_ERRCHAIN_SHIFT (0U) -#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) -#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) - -/* Bitfield definition for register: KEYADDR */ -/* - * INDEX (RW) - * - * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. - * Key index pointer. The valid indices are 0-[number_keys]. - * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - */ -#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) -#define SDP_KEYADDR_INDEX_SHIFT (16U) -#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) -#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) - -/* - * SUBWRD (RW) - * - * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field - * increments; To write a key, the software must first write the desired key index/subword to this register. - */ -#define SDP_KEYADDR_SUBWRD_MASK (0x3U) -#define SDP_KEYADDR_SUBWRD_SHIFT (0U) -#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) -#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) - -/* Bitfield definition for register: KEYDAT */ -/* - * KEYDAT (RW) - * - * This register provides the write access to the key/key subword specified by the key index register. - * Writing this location updates the selected subword for the key located at the index - * specified by the key index register. The write also triggers the SUBWORD field of the - * KEY register to increment to the next higher word in the key - */ -#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) -#define SDP_KEYDAT_KEYDAT_SHIFT (0U) -#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) -#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) - -/* Bitfield definition for register array: CIPHIV */ -/* - * CIPHIV (RW) - * - * cipher initialization vector. - */ -#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) -#define SDP_CIPHIV_CIPHIV_SHIFT (0U) -#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) -#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) - -/* Bitfield definition for register array: HASWRD */ -/* - * HASWRD (RW) - * - * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. - * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - */ -#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) -#define SDP_HASWRD_HASWRD_SHIFT (0U) -#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) -#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) - -/* Bitfield definition for register: CMDPTR */ -/* - * CMDPTR (RW) - * - * current command addresses the register points to the multiword - * descriptor that is to be executed (or is currently being executed) - */ -#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) -#define SDP_CMDPTR_CMDPTR_SHIFT (0U) -#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) -#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) - -/* Bitfield definition for register: NPKTPTR */ -/* - * NPKTPTR (RW) - * - * Next Packet Address Pointer - */ -#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) -#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) -#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) -#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) - -/* Bitfield definition for register: PKTCTL */ -/* - * PKTTAG (RW) - * - * packet tag - */ -#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) -#define SDP_PKTCTL_PKTTAG_SHIFT (24U) -#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) -#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) - -/* - * CIPHIV (RW) - * - * Load Initial Vector for the AES in this packet. - */ -#define SDP_PKTCTL_CIPHIV_MASK (0x40U) -#define SDP_PKTCTL_CIPHIV_SHIFT (6U) -#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) -#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) - -/* - * HASFNL (RW) - * - * Hash Termination packet - */ -#define SDP_PKTCTL_HASFNL_MASK (0x20U) -#define SDP_PKTCTL_HASFNL_SHIFT (5U) -#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) -#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) - -/* - * HASINI (RW) - * - * Hash Initialization packat - */ -#define SDP_PKTCTL_HASINI_MASK (0x10U) -#define SDP_PKTCTL_HASINI_SHIFT (4U) -#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) -#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) - -/* - * CHAIN (RW) - * - * whether the next command pointer register must be loaded into the channel's current descriptor - * pointer. - */ -#define SDP_PKTCTL_CHAIN_MASK (0x8U) -#define SDP_PKTCTL_CHAIN_SHIFT (3U) -#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) -#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) - -/* - * DCRSEMA (RW) - * - * whether the channel's semaphore must be decremented at the end of the current operation. - * When the semaphore reaches a value of zero, no more operations are issued from the channel. - */ -#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) -#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) -#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) -#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) - -/* - * PKTINT (RW) - * - * Reflects whether the channel must issue an interrupt upon the completion of the packet - */ -#define SDP_PKTCTL_PKTINT_MASK (0x2U) -#define SDP_PKTCTL_PKTINT_SHIFT (1U) -#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) -#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) - -/* Bitfield definition for register: PKTSRC */ -/* - * PKTSRC (RW) - * - * Packet Memory Source Address - */ -#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) -#define SDP_PKTSRC_PKTSRC_SHIFT (0U) -#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) -#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) - -/* Bitfield definition for register: PKTDST */ -/* - * PKTDST (RW) - * - * Packet Memory Destination Address - */ -#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) -#define SDP_PKTDST_PKTDST_SHIFT (0U) -#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) -#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) - -/* Bitfield definition for register: PKTBUF */ -/* - * PKTBUF (RW) - * - */ -#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) -#define SDP_PKTBUF_PKTBUF_SHIFT (0U) -#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) -#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) - - - -/* CIPHIV register group index macro definition */ -#define SDP_CIPHIV_CIPHIV0 (0UL) -#define SDP_CIPHIV_CIPHIV1 (1UL) -#define SDP_CIPHIV_CIPHIV2 (2UL) -#define SDP_CIPHIV_CIPHIV3 (3UL) - -/* HASWRD register group index macro definition */ -#define SDP_HASWRD_HASWRD0 (0UL) -#define SDP_HASWRD_HASWRD1 (1UL) -#define SDP_HASWRD_HASWRD2 (2UL) -#define SDP_HASWRD_HASWRD3 (3UL) -#define SDP_HASWRD_HASWRD4 (4UL) -#define SDP_HASWRD_HASWRD5 (5UL) -#define SDP_HASWRD_HASWRD6 (6UL) -#define SDP_HASWRD_HASWRD7 (7UL) - - -#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sec_regs.h deleted file mode 100644 index 19362a87502..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sec_regs.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SEC_H -#define HPM_SEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ - __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ -} SEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define SEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define SEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define SEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_NSC_MASK) >> SEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define SEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define SEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define SEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_SEC_MASK) >> SEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * PMIC_FAIL (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define SEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) -#define SEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) -#define SEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_FAIL_SHIFT) & SEC_SECURE_STATE_PMIC_FAIL_MASK) -#define SEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_FAIL_MASK) >> SEC_SECURE_STATE_PMIC_FAIL_SHIFT) - -/* - * PMIC_NSC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define SEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) -#define SEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) -#define SEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_NSC_SHIFT) & SEC_SECURE_STATE_PMIC_NSC_MASK) -#define SEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_NSC_MASK) >> SEC_SECURE_STATE_PMIC_NSC_SHIFT) - -/* - * PMIC_SEC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define SEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) -#define SEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) -#define SEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_SEC_SHIFT) & SEC_SECURE_STATE_PMIC_SEC_MASK) -#define SEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_SEC_MASK) >> SEC_SECURE_STATE_PMIC_SEC_SHIFT) - -/* - * PMIC_INS (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define SEC_SECURE_STATE_PMIC_INS_MASK (0x10U) -#define SEC_SECURE_STATE_PMIC_INS_SHIFT (4U) -#define SEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_INS_SHIFT) & SEC_SECURE_STATE_PMIC_INS_MASK) -#define SEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_INS_MASK) >> SEC_SECURE_STATE_PMIC_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define SEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define SEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define SEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define SEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) >> SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define SEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define SEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define SEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define SEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define SEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define SEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define SEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define SEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define SEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define SEC_EVENT_EVENT_SHIFT (16U) -#define SEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & SEC_EVENT_EVENT_MASK) >> SEC_EVENT_EVENT_SHIFT) - -/* - * PMIC_ESC_NSC (RO) - * - * PMIC is escalating non-secure event - */ -#define SEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) -#define SEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) -#define SEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_NSC_MASK) >> SEC_EVENT_PMIC_ESC_NSC_SHIFT) - -/* - * PMIC_ESC_SEC (RO) - * - * PMIC is escalting secure event - */ -#define SEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) -#define SEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) -#define SEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_SEC_MASK) >> SEC_EVENT_PMIC_ESC_SEC_SHIFT) - -/* Bitfield definition for register: LIFECYCLE */ -/* - * LIFECYCLE (RO) - * - * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, - * bit0: lifecycle_unknow - */ -#define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) -#define SEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) -#define SEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & SEC_LIFECYCLE_LIFECYCLE_MASK) >> SEC_LIFECYCLE_LIFECYCLE_SHIFT) - - - - -#endif /* HPM_SEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sei_regs.h deleted file mode 100644 index 3be39abb035..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sei_regs.h +++ /dev/null @@ -1,3301 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SEI_H -#define HPM_SEI_H - -typedef struct { - struct { - struct { - __RW uint32_t CTRL; /* 0x0: Engine control register */ - __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */ - __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __R uint32_t EXE_STA; /* 0x10: Execution status */ - __R uint32_t EXE_PTR; /* 0x14: Execution pointer */ - __R uint32_t EXE_INST; /* 0x18: Execution instruction */ - __R uint32_t WDG_STA; /* 0x1C: Watch dog status */ - } ENGINE; - struct { - __RW uint32_t CTRL; /* 0x20: Transceiver control register */ - __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */ - __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */ - __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */ - __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __R uint32_t PIN; /* 0x38: Transceiver pin status */ - __R uint32_t STATE; /* 0x3C: FSM of asynchronous */ - } XCVR; - struct { - __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */ - __W uint32_t SW; /* 0x44: Software trigger */ - __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */ - __RW uint32_t PRD; /* 0x4C: Trigger period */ - __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */ - __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */ - __R uint32_t PRD_STS; /* 0x60: Period trigger status */ - __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */ - __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */ - } TRG; - struct { - __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */ - __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */ - __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */ - __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */ - } TRG_TABLE; - struct { - __RW uint32_t MODE; /* 0xC0: command register mode */ - __RW uint32_t IDX; /* 0xC4: command register configuration */ - __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */ - __RW uint32_t CMD; /* 0xE0: command */ - __RW uint32_t SET; /* 0xE4: command bit set register */ - __RW uint32_t CLR; /* 0xE8: command bit clear register */ - __RW uint32_t INV; /* 0xEC: command bit invert register */ - __R uint32_t IN; /* 0xF0: Commad input */ - __R uint32_t OUT; /* 0xF4: Command output */ - __RW uint32_t STS; /* 0xF8: Command status */ - __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */ - } CMD; - struct { - __RW uint32_t MIN; /* 0x100: command start value */ - __RW uint32_t MAX; /* 0x104: command end value */ - __RW uint32_t MSK; /* 0x108: command compare bit enable */ - __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */ - __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */ - __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */ - __R uint8_t RESERVED1[8]; /* 0x118 - 0x11F: Reserved */ - } CMD_TABLE[8]; - struct { - __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */ - __RW uint32_t CFG; /* 0x210: Latch configuration */ - __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ - __R uint32_t TIME; /* 0x218: Latch time */ - __R uint32_t STS; /* 0x21C: Latch status */ - } LATCH[4]; - struct { - __RW uint32_t SMP_EN; /* 0x280: Sample selection register */ - __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */ - __RW uint32_t SMP_DAT; /* 0x288: Sample data */ - __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */ - __RW uint32_t SMP_POS; /* 0x290: Sample override position */ - __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */ - __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */ - __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */ - __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */ - __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */ - __RW uint32_t UPD_DAT; /* 0x2A8: Update data */ - __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */ - __RW uint32_t UPD_POS; /* 0x2B0: Update override position */ - __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */ - __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */ - __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */ - __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */ - __R uint32_t SMP_STS; /* 0x2C4: Sample status */ - __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */ - __R uint32_t TIME_IN; /* 0x2CC: input time */ - __R uint32_t POS_IN; /* 0x2D0: Input position */ - __R uint32_t REV_IN; /* 0x2D4: Input revolution */ - __R uint32_t SPD_IN; /* 0x2D8: Input speed */ - __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */ - __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */ - __R uint32_t UPD_STS; /* 0x2E4: Update status */ - __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */ - } POS; - struct { - __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */ - __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */ - __R uint32_t INT_STS; /* 0x308: Interrupt status */ - __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */ - __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */ - __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */ - __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */ - __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */ - } IRQ; - __R uint8_t RESERVED0[224]; /* 0x320 - 0x3FF: Reserved */ - } CTRL[2]; - __R uint8_t RESERVED0[11264]; /* 0x800 - 0x33FF: Reserved */ - __RW uint32_t INSTR[64]; /* 0x3400 - 0x34FC: Instructions */ - __R uint8_t RESERVED1[768]; /* 0x3500 - 0x37FF: Reserved */ - struct { - __RW uint32_t MODE; /* 0x3800: */ - __RW uint32_t IDX; /* 0x3804: Data register bit index */ - __RW uint32_t GOLD; /* 0x3808: Gold data for data check */ - __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */ - __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */ - __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */ - __RW uint32_t DATA; /* 0x3820: Data value */ - __RW uint32_t SET; /* 0x3824: Data bit set */ - __RW uint32_t CLR; /* 0x3828: Data bit clear */ - __RW uint32_t INV; /* 0x382C: Data bit invert */ - __R uint32_t IN; /* 0x3830: Data input */ - __R uint32_t OUT; /* 0x3834: Data output */ - __RW uint32_t STS; /* 0x3838: Data status */ - __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */ - } DAT[10]; -} SEI_Type; - - -/* Bitfield definition for register of struct array CTRL: CTRL */ -/* - * WATCH (RW) - * - * Enable watch dog - * 0: Watch dog disabled - * 1: Watch dog enabled - */ -#define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL) -#define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U) -#define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) -#define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) - -/* - * ARMING (RW) - * - * Wait for trigger before excuting - * 0: Execute on enable - * 1: Wait trigger before exection after enabled - */ -#define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL) -#define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U) -#define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) -#define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) - -/* - * EXCEPT (RW) - * - * Explain timout as exception - * 0: when timeout, pointer move to next instruction - * 1: when timeout, pointer jump to timeout vector - */ -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U) -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U) -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) - -/* - * REWIND (RW) - * - * Rewind execution pointer - * 0: run - * 1: clean status and rewind - */ -#define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U) -#define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U) -#define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) -#define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) - -/* - * ENABLE (RW) - * - * Enable - * 0: disable - * 1: enable - */ -#define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U) -#define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U) -#define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) -#define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTR_CFG */ -/* - * DAT_CDM (RW) - * - * Select DATA register to receive CDM bit in BiSSC slave mode - * 0: ignore - * 1: command - * 2: data register 2 - * 3: data register 3 - * ... - * 29:data register 29 - * 30: value 0 when send, ignore in receive - * 31: value1 when send, ignore in receive - */ -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) - -/* - * DAT_BASE (RW) - * - * Bias for data register access, if calculated index bigger than 32, index will wrap around - * 0: real data index - * 1: access index is 1 greater than instruction address - * 2: access index is 2 greater than instruction address - * ... - * 31: access index is 31 greater than instruction address - */ -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) - -/* - * POINTER_WDOG (RW) - * - * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME - */ -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) - -/* - * POINTER_INIT (RW) - * - * Initial execute pointer - */ -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: WDG_CFG */ -/* - * WDOG_TIME (RW) - * - * Time out count for each instruction, counter in bit time. - */ -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU) -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U) -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: EXE_STA */ -/* - * TRIGERED (RO) - * - * Execution has been triggered - * 0: Execution not triggered - * 1: Execution triggered - */ -#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL) -#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U) -#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT) - -/* - * ARMED (RO) - * - * Waiting for trigger for execution - * 0: Not in waiting status - * 1: In waiting status - */ -#define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL) -#define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U) -#define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT) - -/* - * EXPIRE (RO) - * - * Watchdog timer expired - * 0: Not expired - * 1: Expired - */ -#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U) -#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U) -#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT) - -/* - * STALL (RO) - * - * Program finished - * 0: Program is executing - * 1: Program finished - */ -#define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U) -#define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U) -#define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: EXE_PTR */ -/* - * HALT_CNT (RO) - * - * Halt count in halt instrution - */ -#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL) -#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U) -#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT) - -/* - * BIT_CNT (RO) - * - * Bit count in send and receive instruction execution - */ -#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL) -#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U) -#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT) - -/* - * POINTER (RO) - * - * Current program pointer - */ -#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU) -#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U) -#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT) - -/* Bitfield definition for register of struct array CTRL: EXE_INST */ -/* - * INST (RO) - * - * Current instruction - */ -#define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U) -#define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT) - -/* Bitfield definition for register of struct array CTRL: WDG_STA */ -/* - * WDOG_CNT (RO) - * - * Current watch dog counter value - */ -#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU) -#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U) -#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CTRL */ -/* - * TRISMP (RW) - * - * Tipple sampe - * 0: sample 1 time for data transition - * 1: sample 3 times in receive and result in 2oo3 - */ -#define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U) -#define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U) -#define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) -#define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) - -/* - * PAR_CLR (WC) - * - * Clear parity error, this is a self clear bit - * 0: no effect - * 1: clear parity error - */ -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U) -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U) -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) - -/* - * RESTART (WC) - * - * Restart tranceiver, this is a self clear bit - * 0: no effect - * 1: reset tranceiver - */ -#define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U) -#define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U) -#define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) -#define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) - -/* - * MODE (RW) - * - * Tranceiver mode - * 0: synchronous maaster - * 1: synchronous slave - * 2: asynchronous mode - * 3: asynchronous mode - */ -#define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U) -#define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U) -#define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK) -#define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: TYPE_CFG */ -/* - * WAIT_LEN (RW) - * - * Number of extra stop bit for asynchronous mode - * 0: 1 bit - * 1: 2 bit - * ... - * 255: 256 bit - */ -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL) -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U) -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) - -/* - * DATA_LEN (RW) - * - * Number of data bit for asynchronous mode - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL) -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U) -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) - -/* - * PAR_POL (RW) - * - * Polarity of parity for asynchronous mode - * 0: even - * 1: odd - */ -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) - -/* - * PAR_EN (RW) - * - * enable parity check for asynchronous mode - * 0: disable - * 1: enable - */ -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) - -/* - * DA_IDLEZ (RW) - * - * Idle state driver of data line - * 0: output - * 1: high-Z - */ -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) - -/* - * CK_IDLEZ (RW) - * - * Idle state driver of clock line - * 0: output - * 1: high-Z - */ -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) - -/* - * DA_IDLEV (RW) - * - * Idle state value of data line - * 0: data'0' - * 1: data'1' - */ -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) - -/* - * CK_IDLEV (RW) - * - * Idle state value of clock line - * 0: data'0' - * 1: data'1' - */ -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: BAUD_CFG */ -/* - * SYNC_POINT (RW) - * - * Baud synchronous time, minmum bit time - */ -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL) -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U) -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) - -/* - * BAUD_DIV (RW) - * - * Baud rate, bit time in system clock cycle - */ -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU) -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U) -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: DATA_CFG */ -/* - * TXD_POINT (RW) - * - * data transmit point in system clcok cycle - */ -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL) -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U) -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) - -/* - * RXD_POINT (RW) - * - * data receive point in system clcok cycle - */ -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU) -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U) -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CLK_CFG */ -/* - * CK1_POINT (RW) - * - * clock point 1 in system clcok cycle - */ -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL) -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U) -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) - -/* - * CK0_POINT (RW) - * - * clock point 0 in system clcok cycle - */ -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU) -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U) -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PIN */ -/* - * OE_CK (RO) - * - * CK drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL) -#define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U) -#define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT) - -/* - * DI_CK (RO) - * - * CK state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL) -#define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U) -#define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT) - -/* - * DO_CK (RO) - * - * CK output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL) -#define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U) -#define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT) - -/* - * OE_RX (RO) - * - * RX drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL) -#define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U) -#define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT) - -/* - * DI_RX (RO) - * - * RX state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL) -#define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U) -#define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT) - -/* - * DO_RX (RO) - * - * RX output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL) -#define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U) -#define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT) - -/* - * OE_DE (RO) - * - * DE drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U) -#define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U) -#define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT) - -/* - * DI_DE (RO) - * - * DE state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U) -#define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U) -#define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT) - -/* - * DO_DE (RO) - * - * DE output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U) -#define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U) -#define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT) - -/* - * OE_TX (RO) - * - * TX drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U) -#define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U) -#define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT) - -/* - * DI_TX (RO) - * - * TX state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U) -#define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U) -#define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT) - -/* - * DO_TX (RO) - * - * TX output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U) -#define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U) -#define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT) - -/* Bitfield definition for register of struct array CTRL: STATE */ -/* - * RECV_STATE (RO) - * - * FSM of asynchronous receive - */ -#define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL) -#define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U) -#define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT) - -/* - * SEND_STATE (RO) - * - * FSM of asynchronous transmit - */ -#define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL) -#define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U) -#define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: IN_CFG */ -/* - * PRD_EN (RW) - * - * Enable period trigger (tigger 2) - * 0: periodical trigger disabled - * 1: periodical trigger enabled - */ -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL) -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U) -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) - -/* - * SYNC_SEL (RW) - * - * Synchronize sigal selection (tigger 2) - * 0: trigger in 0 - * 1: trigger in 1 - * ... - * 7: trigger in 7 - */ -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL) -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U) -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) - -/* - * IN1_EN (RW) - * - * Enable trigger 1 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U) -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U) -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) - -/* - * IN1_SEL (RW) - * - * Trigger 1 sigal selection - * 0: trigger in 0 - * 1: trigger in 1 - * ... - * 7: trigger in 7 - */ -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U) -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U) -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) - -/* - * IN0_EN (RW) - * - * Enable trigger 0 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U) -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U) -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) - -/* - * IN0_SEL (RW) - * - * Trigger 0 sigal selection - * 0: trigger in 0 - * 1: trigger in 1 - * ... - * 7: trigger in 7 - */ -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U) -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U) -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SW */ -/* - * SOFT (WC) - * - * Software trigger (tigger 3). this bit is self-clear - * 0: trigger source disabled - * 1: trigger source enabled - */ -#define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U) -#define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U) -#define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK) -#define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD_CFG */ -/* - * ARMING (RW) - * - * Wait for trigger synchronous before trigger - * 0: Trigger directly - * 1: Wait trigger source before period trigger - */ -#define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL) -#define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U) -#define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) -#define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) - -/* - * SYNC (RW) - * - * Synchronous - * 0: Not synchronous - * 1: Synchronous every trigger source - */ -#define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U) -#define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U) -#define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) -#define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD */ -/* - * PERIOD (RW) - * - * Trigger period - */ -#define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U) -#define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK) -#define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: OUT_CFG */ -/* - * OUT3_EN (RW) - * - * Enable trigger 3 - * 0: disable trigger 3 - * 1: enable trigger 3 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) - -/* - * OUT3_SEL (RW) - * - * Trigger 3 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) - -/* - * OUT2_EN (RW) - * - * Enable trigger 2 - * 0: disable trigger 2 - * 1: enable trigger 2 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) - -/* - * OUT2_SEL (RW) - * - * Trigger 2 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) - -/* - * OUT1_EN (RW) - * - * Enable trigger 1 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) - -/* - * OUT1_SEL (RW) - * - * Trigger 1 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) - -/* - * OUT0_EN (RW) - * - * Enable trigger 0 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) - -/* - * OUT0_SEL (RW) - * - * Trigger 0 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD_STS */ -/* - * TRIGERED (RO) - * - * Period has been triggered - * 0: Not triggered - * 1: Triggered - */ -#define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL) -#define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U) -#define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT) - -/* - * ARMED (RO) - * - * Waiting for trigger - * 0: Not in waiting status - * 1: In waiting status - */ -#define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL) -#define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U) -#define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD_CNT */ -/* - * PERIOD_CNT (RO) - * - * Trigger period counter - */ -#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U) -#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: 0 */ -/* - * CMD_TRIGGER0 (RW) - * - * Trigger command - */ -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U) -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) - -/* Bitfield definition for register of struct array CTRL: 0 */ -/* - * TRIGGER0_TIME (RO) - * - * Trigger time - */ -#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U) -#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MODE */ -/* - * WLEN (RW) - * - * word length - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL) -#define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U) -#define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK) -#define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT) - -/* - * WORDER (RW) - * - * word order - * 0: sample as bit order - * 1: different from bit order - */ -#define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U) -#define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U) -#define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK) -#define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT) - -/* - * BORDER (RW) - * - * bit order - * 0: LSB first - * 1: MSB first - */ -#define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U) -#define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U) -#define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK) -#define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT) - -/* - * SIGNED (RW) - * - * Signed - * 0: unsigned value - * 1: signed value - */ -#define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U) -#define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U) -#define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK) -#define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT) - -/* - * REWIND (WC) - * - * Write 1 to rewind read/write pointer, this is a self clear bit - */ -#define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U) -#define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U) -#define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK) -#define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT) - -/* - * MODE (RW) - * - * Data mode(CMD register only support data mode) - * 0: data mode - * 1: check mode - * 2: CRC mode - */ -#define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U) -#define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U) -#define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK) -#define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: IDX */ -/* - * LAST_BIT (RW) - * - * Last bit index for tranceive - */ -#define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL) -#define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U) -#define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) -#define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) - -/* - * FIRST_BIT (RW) - * - * First bit index for tranceive - */ -#define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL) -#define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U) -#define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) -#define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) - -/* - * MAX_BIT (RW) - * - * Highest bit index - */ -#define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U) -#define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U) -#define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) -#define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) - -/* - * MIN_BIT (RW) - * - * Lowest bit index - */ -#define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU) -#define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U) -#define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) -#define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CMD */ -/* - * DATA (RW) - * - * DATA - */ -#define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U) -#define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK) -#define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SET */ -/* - * DATA_SET (RW) - * - * DATA bit set - */ -#define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U) -#define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK) -#define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CLR */ -/* - * DATA_CLR (RW) - * - * DATA bit clear - */ -#define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U) -#define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) -#define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INV */ -/* - * DATA_TGL (RW) - * - * DATA bit toggle - */ -#define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U) -#define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) -#define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: IN */ -/* - * DATA_IN (RO) - * - * Commad input - */ -#define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U) -#define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT) - -/* Bitfield definition for register of struct array CTRL: OUT */ -/* - * DATA_OUT (RO) - * - * Command output - */ -#define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U) -#define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: STS */ -/* - * WORD_IDX (RO) - * - * Word index - */ -#define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL) -#define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U) -#define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT) - -/* - * WORD_CNT (RO) - * - * Word counter - */ -#define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U) -#define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U) -#define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT) - -/* - * BIT_IDX (RO) - * - * Bit index - */ -#define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU) -#define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U) -#define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MIN */ -/* - * CMD_MIN (RW) - * - * minimum command value - */ -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MAX */ -/* - * CMD_MAX (RW) - * - * maximum command value - */ -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MSK */ -/* - * CMD_MASK (RW) - * - * compare mask - */ -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTA */ -/* - * PTR3 (RW) - * - * pointer3 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL) -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) - -/* - * PTR2 (RW) - * - * pointer2 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL) -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) - -/* - * PTR1 (RW) - * - * pointer1 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) - -/* - * PTR0 (RW) - * - * pointer0 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU) -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTB */ -/* - * PTR7 (RW) - * - * pointer7 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL) -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) - -/* - * PTR6 (RW) - * - * pointer6 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL) -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) - -/* - * PTR5 (RW) - * - * pointer5 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) - -/* - * PTR4 (RW) - * - * pointer4 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU) -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) - -/* Bitfield definition for register of struct array CTRL: 0_1 */ -/* - * POINTER (RW) - * - * pointer - */ -#define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL) -#define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U) -#define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) -#define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) - -/* - * CFG_TM (RW) - * - * timeout - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL) -#define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U) -#define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) - -/* - * CFG_TXD (RW) - * - * data send - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U) -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U) -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) - -/* - * CFG_CLK (RW) - * - * clock(only support master mode) - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U) -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U) -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) - -/* - * CFG_PTR (RW) - * - * pointer - * 0: match - * 1: not match - * 2:entry - * 3:leave - */ -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U) -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U) -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) - -/* - * OV_TM (RW) - * - * override timeout check - */ -#define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U) -#define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U) -#define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) - -/* - * OV_TXD (RW) - * - * override TX data check - */ -#define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U) -#define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U) -#define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) - -/* - * OV_CLK (RW) - * - * override clock check - */ -#define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U) -#define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U) -#define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) - -/* - * OV_PTR (RW) - * - * override pointer check - */ -#define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U) -#define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U) -#define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CFG */ -/* - * EN (RW) - * - * Enable latch - * 0: disable - * 1: enable - */ -#define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL) -#define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U) -#define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK) -#define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT) - -/* - * SELECT (RW) - * - * Output select - * 0: state0-state1 - * 1: state1-state2 - * 2: state2-state3 - * 3: state3-state0 - */ -#define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL) -#define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U) -#define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK) -#define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT) - -/* - * DELAY (RW) - * - * Delay in system clock cycle, for state transition - */ -#define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU) -#define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U) -#define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK) -#define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT) - -/* Bitfield definition for register of struct array CTRL: TIME */ -/* - * LAT_TIME (RO) - * - * Latch time - */ -#define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U) -#define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: STS */ -/* - * STATE (RO) - * - * State - */ -#define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL) -#define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U) -#define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT) - -/* - * LAT_CNT (RO) - * - * Latch counter - */ -#define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU) -#define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U) -#define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_EN */ -/* - * ACC_EN (RW) - * - * Position include acceleration - * 0: use acceleration from sample override acceleration register - * 1: use acceleration from motor group - */ -#define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL) -#define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U) -#define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) - -/* - * ACC_SEL (RW) - * - * Data register for acceleration transfer - */ -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL) -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U) -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) - -/* - * SPD_EN (RW) - * - * Position include speed - * 0: use speed from sample override speed register - * 1: use speed from motor group - */ -#define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL) -#define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U) -#define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) - -/* - * SPD_SEL (RW) - * - * Data register for speed transfer - */ -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL) -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U) -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) - -/* - * REV_EN (RW) - * - * Position include revolution - * 0: use revolution from sample override revolution register - * 1: use revolution from motor group - */ -#define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U) -#define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U) -#define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) - -/* - * REV_SEL (RW) - * - * Data register for revolution transfer - */ -#define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U) -#define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U) -#define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) - -/* - * POS_EN (RW) - * - * Position include position - * 0: use position from sample override position register - * 1: use position from motor group - */ -#define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U) -#define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U) -#define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) - -/* - * POS_SEL (RW) - * - * Data register for position transfer - */ -#define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU) -#define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U) -#define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_CFG */ -/* - * ONCE (RW) - * - * Sample one time - * 0: Sample during windows time - * 1: Close sample window after first sample - */ -#define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL) -#define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U) -#define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) -#define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) - -/* - * LAT_SEL (RW) - * - * Latch selection - * 0: latch 0 - * 1: latch 1 - * 2: latch 2 - * 3: latch 3 - */ -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL) -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U) -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) - -/* - * WINDOW (RW) - * - * Sample window, in clock cycle - */ -#define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU) -#define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U) -#define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) -#define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_DAT */ -/* - * DAT_SEL (RW) - * - * Data register sampled, each bit represent a data register - */ -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U) -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_POS */ -/* - * POS (RW) - * - * Sample override position - */ -#define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U) -#define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK) -#define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_REV */ -/* - * REV (RW) - * - * Sample override revolution - */ -#define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U) -#define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK) -#define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_SPD */ -/* - * SPD (RW) - * - * Sample override speed - */ -#define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U) -#define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) -#define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_ACC */ -/* - * ACC (RW) - * - * Sample override accelerate - */ -#define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U) -#define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) -#define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_EN */ -/* - * ACC_EN (RW) - * - * Position include acceleration - * 0: use acceleration from update override acceleration register - * 1: use acceleration from data register - */ -#define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL) -#define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U) -#define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) - -/* - * ACC_SEL (RW) - * - * Data register for acceleration transfer - */ -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL) -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U) -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) - -/* - * SPD_EN (RW) - * - * Position include speed - * 0: use speed from update override speed register - * 1: use speed from data register - */ -#define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL) -#define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U) -#define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) - -/* - * SPD_SEL (RW) - * - * Data register for speed transfer - */ -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL) -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U) -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) - -/* - * REV_EN (RW) - * - * Position include revolution - * 0: use revolution from update override revolution register - * 1: use revolution from data register - */ -#define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U) -#define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U) -#define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) - -/* - * REV_SEL (RW) - * - * Data register for revolution transfer - */ -#define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U) -#define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U) -#define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) - -/* - * POS_EN (RW) - * - * Position include position - * 0: use position from update override position register - * 1: use position from data register - */ -#define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U) -#define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U) -#define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) - -/* - * POS_SEL (RW) - * - * Data register for position transfer - */ -#define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU) -#define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U) -#define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_CFG */ -/* - * TIME_OVRD (RW) - * - * Use override time - * 0: use time sample from motor group - * 1: use override time - */ -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL) -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U) -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) - -/* - * ONERR (RW) - * - * Sample one time - * 0: Sample during windows time - * 1: Close sample window after first sample - */ -#define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL) -#define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U) -#define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) -#define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) - -/* - * LAT_SEL (RW) - * - * Latch selection - * 0: latch 0 - * 1: latch 1 - * 2: latch 2 - * 3: latch 3 - */ -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL) -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U) -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_DAT */ -/* - * DAT_SEL (RW) - * - * Data register sampled, each bit represent a data register - */ -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U) -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_TIME */ -/* - * TIME (RW) - * - * Update override time - */ -#define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U) -#define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) -#define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_POS */ -/* - * POS (RW) - * - * Update override position - */ -#define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U) -#define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK) -#define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_REV */ -/* - * REV (RW) - * - * Update override revolution - */ -#define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U) -#define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK) -#define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_SPD */ -/* - * SPD (RW) - * - * Update override speed - */ -#define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U) -#define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) -#define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_ACC */ -/* - * ACC (RW) - * - * Update override accelerate - */ -#define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U) -#define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) -#define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_VAL */ -/* - * ACC (RO) - * - * Position include acceleration - */ -#define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL) -#define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U) -#define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT) - -/* - * SPD (RO) - * - * Position include speed - */ -#define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL) -#define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U) -#define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT) - -/* - * REV (RO) - * - * Position include revolution - */ -#define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U) -#define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U) -#define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT) - -/* - * POS (RO) - * - * Position include position - */ -#define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U) -#define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U) -#define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_STS */ -/* - * OCCUR (RO) - * - * Sample occured - * 0: Sample not happened - * 1: Sample occured - */ -#define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL) -#define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U) -#define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT) - -/* - * WIN_CNT (RO) - * - * Sample window counter - */ -#define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU) -#define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U) -#define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: TIME_IN */ -/* - * TIME (RO) - * - * input time - */ -#define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U) -#define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: POS_IN */ -/* - * POS (RO) - * - * Input position - */ -#define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U) -#define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: REV_IN */ -/* - * REV (RO) - * - * Input revolution - */ -#define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U) -#define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SPD_IN */ -/* - * SPD (RO) - * - * Input speed - */ -#define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U) -#define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: ACC_IN */ -/* - * ACC (RO) - * - * Input accelerate - */ -#define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U) -#define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_STS */ -/* - * UPD_ERR (RO) - * - * Update error - * 0: data receive normally - * 1: data receive error - */ -#define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL) -#define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U) -#define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INT_EN */ -/* - * TRG_ERR3 (RW) - * - * Trigger3 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) - -/* - * TRG_ERR2 (RW) - * - * Trigger2 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) - -/* - * TRG_ERR1 (RW) - * - * Trigger1 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) - -/* - * TRG_ERR0 (RW) - * - * Trigger0 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) - -/* - * TRIGER3 (RW) - * - * Trigger3 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) - -/* - * TRIGER2 (RW) - * - * Trigger2 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) - -/* - * TRIGER1 (RW) - * - * Trigger1 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) - -/* - * TRIGER0 (RW) - * - * Trigger0 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) - -/* - * SMP_ERR (RW) - * - * Sample error - */ -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL) -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U) -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) - -/* - * LATCH3 (RW) - * - * Latch3 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U) -#define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) - -/* - * LATCH2 (RW) - * - * Latch2 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U) -#define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) - -/* - * LATCH1 (RW) - * - * Latch1 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U) -#define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) - -/* - * LATCH0 (RW) - * - * Latch0 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U) -#define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) - -/* - * TIMEOUT (RW) - * - * Timeout - */ -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U) -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U) -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) - -/* - * TRX_ERR (RW) - * - * Transfer error - */ -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U) -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U) -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) - -/* - * INSTR1_END (RW) - * - * Instruction 1 end - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) - -/* - * INSTR0_END (RW) - * - * Instruction 0 end - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) - -/* - * PTR1_END (RW) - * - * Pointer 1 end - */ -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) - -/* - * PTR0_END (RW) - * - * Pointer 0 end - */ -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) - -/* - * INSTR1_ST (RW) - * - * Instruction 1 start - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) - -/* - * INSTR0_ST (RW) - * - * Instruction 0 start - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) - -/* - * PTR1_ST (RW) - * - * Pointer 1 start - */ -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) - -/* - * PTR0_ST (RW) - * - * Pointer 0 start - */ -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) - -/* - * WDOG (RW) - * - * Watch dog - */ -#define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U) -#define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U) -#define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) -#define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) - -/* - * EXCEPT (RW) - * - * Exception - */ -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U) -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U) -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) - -/* - * STALL (RW) - * - * Stall - */ -#define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U) -#define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U) -#define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) -#define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INT_FLAG */ -/* - * TRG_ERR3 (W1C) - * - * Trigger3 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) - -/* - * TRG_ERR2 (W1C) - * - * Trigger2 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) - -/* - * TRG_ERR1 (W1C) - * - * Trigger1 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) - -/* - * TRG_ERR0 (W1C) - * - * Trigger0 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) - -/* - * TRIGER3 (W1C) - * - * Trigger3 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) - -/* - * TRIGER2 (W1C) - * - * Trigger2 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) - -/* - * TRIGER1 (W1C) - * - * Trigger1 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) - -/* - * TRIGER0 (W1C) - * - * Trigger0 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) - -/* - * SMP_ERR (W1C) - * - * Sample error - */ -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL) -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U) -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) - -/* - * LATCH3 (W1C) - * - * Latch3 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) - -/* - * LATCH2 (W1C) - * - * Latch2 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) - -/* - * LATCH1 (W1C) - * - * Latch1 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) - -/* - * LATCH0 (W1C) - * - * Latch0 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) - -/* - * TIMEOUT (W1C) - * - * Timeout - */ -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U) -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U) -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) - -/* - * TRX_ERR (W1C) - * - * Transfer error - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U) -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U) -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) - -/* - * INSTR1_END (W1C) - * - * Instruction 1 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) - -/* - * INSTR0_END (W1C) - * - * Instruction 0 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) - -/* - * PTR1_END (W1C) - * - * Pointer 1 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) - -/* - * PTR0_END (W1C) - * - * Pointer 0 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) - -/* - * INSTR1_ST (W1C) - * - * Instruction 1 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) - -/* - * INSTR0_ST (W1C) - * - * Instruction 0 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) - -/* - * PTR1_ST (W1C) - * - * Pointer 1 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) - -/* - * PTR0_ST (W1C) - * - * Pointer 0 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) - -/* - * WDOG (W1C) - * - * Watch dog - */ -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U) -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U) -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) - -/* - * EXCEPT (W1C) - * - * Exception - */ -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U) -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U) -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) - -/* - * STALL (W1C) - * - * Stall - */ -#define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U) -#define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U) -#define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INT_STS */ -/* - * TRG_ERR3 (RO) - * - * Trigger3 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT) - -/* - * TRG_ERR2 (RO) - * - * Trigger2 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT) - -/* - * TRG_ERR1 (RO) - * - * Trigger1 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT) - -/* - * TRG_ERR0 (RO) - * - * Trigger0 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT) - -/* - * TRIGER3 (RO) - * - * Trigger3 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT) - -/* - * TRIGER2 (RO) - * - * Trigger2 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT) - -/* - * TRIGER1 (RO) - * - * Trigger1 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT) - -/* - * TRIGER0 (RO) - * - * Trigger0 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT) - -/* - * SMP_ERR (RO) - * - * Sample error - */ -#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL) -#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U) -#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT) - -/* - * LATCH3 (RO) - * - * Latch3 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U) -#define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT) - -/* - * LATCH2 (RO) - * - * Latch2 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U) -#define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT) - -/* - * LATCH1 (RO) - * - * Latch1 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U) -#define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT) - -/* - * LATCH0 (RO) - * - * Latch0 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U) -#define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT) - -/* - * TIMEOUT (RO) - * - * Timeout - */ -#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U) -#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U) -#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT) - -/* - * TRX_ERR (RO) - * - * Transfer error - */ -#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U) -#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U) -#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT) - -/* - * INSTR1_END (RO) - * - * Instruction 1 end - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT) - -/* - * INSTR0_END (RO) - * - * Instruction 0 end - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT) - -/* - * PTR1_END (RO) - * - * Pointer 1 end - */ -#define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT) - -/* - * PTR0_END (RO) - * - * Pointer 0 end - */ -#define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT) - -/* - * INSTR1_ST (RO) - * - * Instruction 1 start - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT) - -/* - * INSTR0_ST (RO) - * - * Instruction 0 start - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT) - -/* - * PTR1_ST (RO) - * - * Pointer 1 start - */ -#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT) - -/* - * PTR0_ST (RO) - * - * Pointer 0 start - */ -#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT) - -/* - * WDOG (RO) - * - * Watch dog - */ -#define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U) -#define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U) -#define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT) - -/* - * EXCEPT (RO) - * - * Exception - */ -#define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U) -#define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U) -#define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT) - -/* - * STALL (RO) - * - * Stall - */ -#define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U) -#define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U) -#define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: POINTER0 */ -/* - * POINTER (RW) - * - * Match pointer 0 - */ -#define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU) -#define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U) -#define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) -#define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) - -/* Bitfield definition for register of struct array CTRL: POINTER1 */ -/* - * POINTER (RW) - * - * Match pointer 1 - */ -#define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU) -#define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U) -#define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) -#define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INSTR0 */ -/* - * INSTR (RW) - * - * Match instruction 0 - */ -#define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U) -#define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) -#define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INSTR1 */ -/* - * INSTR (RW) - * - * Match instruction 1 - */ -#define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U) -#define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) -#define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) - -/* Bitfield definition for register array: INSTR */ -/* - * OP (RW) - * - * operation - * 0: halt - * 1: jump - * 2: send with timeout check - * 3: send without timout check - * 4: wait with timeout check - * 5: wait without timout check - * 6: receive with timeout check - * 7: receive without timout check - */ -#define SEI_INSTR_OP_MASK (0x1C000000UL) -#define SEI_INSTR_OP_SHIFT (26U) -#define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK) -#define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT) - -/* - * CK (RW) - * - * clock - * 0: low - * 1: rise-fall - * 2: fall-rise - * 3: high - */ -#define SEI_INSTR_CK_MASK (0x3000000UL) -#define SEI_INSTR_CK_SHIFT (24U) -#define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK) -#define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT) - -/* - * CRC (RW) - * - * CRC register - * 0: don't calculate CRC - * 1: do not set this value - * 2: data register 2 - * 3: data register 3 - * ... - * 29: data register 29 - * 30: value 0 when send, wait 0 in receive - * 31: value1 when send, wait 1 in receive - */ -#define SEI_INSTR_CRC_MASK (0x1F0000UL) -#define SEI_INSTR_CRC_SHIFT (16U) -#define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK) -#define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT) - -/* - * DAT (RW) - * - * DATA register - * 0: ignore data - * 1: command - * 2: data register 2 - * 3: data register 3 - * ... - * 29: data register 29 - * 30: value 0 when send, wait 0 in receive - * 31: value1 when send, wait 1 in receive - */ -#define SEI_INSTR_DAT_MASK (0x1F00U) -#define SEI_INSTR_DAT_SHIFT (8U) -#define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK) -#define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT) - -/* - * OPR (RW) - * - * [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. - * [2] When OP is 1, this area is the the pointer to the command table. - * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; - * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; - * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. - * [3] When OP is 2-7, this area is the data length as fellow: - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_INSTR_OPR_MASK (0x1FU) -#define SEI_INSTR_OPR_SHIFT (0U) -#define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK) -#define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT) - -/* Bitfield definition for register of struct array DAT: MODE */ -/* - * CRC_LEN (RW) - * - * CRC length - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL) -#define SEI_DAT_MODE_CRC_LEN_SHIFT (24U) -#define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK) -#define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT) - -/* - * WLEN (RW) - * - * word length - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL) -#define SEI_DAT_MODE_WLEN_SHIFT (16U) -#define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK) -#define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT) - -/* - * CRC_SHIFT (RW) - * - * CRC shift mode, this mode is used to perform repeat code check - * 0: CRC - * 1: shift mode - */ -#define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U) -#define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U) -#define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK) -#define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT) - -/* - * CRC_INV (RW) - * - * CRC invert - * 0: use CRC - * 1: use inverted CRC - */ -#define SEI_DAT_MODE_CRC_INV_MASK (0x1000U) -#define SEI_DAT_MODE_CRC_INV_SHIFT (12U) -#define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK) -#define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT) - -/* - * WORDER (RW) - * - * word order - * 0: sample as bit order - * 1: different from bit order - */ -#define SEI_DAT_MODE_WORDER_MASK (0x800U) -#define SEI_DAT_MODE_WORDER_SHIFT (11U) -#define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK) -#define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT) - -/* - * BORDER (RW) - * - * bit order - * 0: LSB first - * 1: MSB first - */ -#define SEI_DAT_MODE_BORDER_MASK (0x400U) -#define SEI_DAT_MODE_BORDER_SHIFT (10U) -#define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK) -#define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT) - -/* - * SIGNED (RW) - * - * Signed - * 0: unsigned value - * 1: signed value - */ -#define SEI_DAT_MODE_SIGNED_MASK (0x200U) -#define SEI_DAT_MODE_SIGNED_SHIFT (9U) -#define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK) -#define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT) - -/* - * REWIND (RW) - * - * Write 1 to rewind read/write pointer, this is a self clear bit - */ -#define SEI_DAT_MODE_REWIND_MASK (0x100U) -#define SEI_DAT_MODE_REWIND_SHIFT (8U) -#define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK) -#define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT) - -/* - * MODE (RW) - * - * Data mode - * 0: data mode - * 1: check mode - * 2: CRC mode - */ -#define SEI_DAT_MODE_MODE_MASK (0x3U) -#define SEI_DAT_MODE_MODE_SHIFT (0U) -#define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK) -#define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT) - -/* Bitfield definition for register of struct array DAT: IDX */ -/* - * LAST_BIT (RW) - * - * Last bit index for tranceive - */ -#define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL) -#define SEI_DAT_IDX_LAST_BIT_SHIFT (24U) -#define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK) -#define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT) - -/* - * FIRST_BIT (RW) - * - * First bit index for tranceive - */ -#define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL) -#define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U) -#define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK) -#define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT) - -/* - * MAX_BIT (RW) - * - * Highest bit index - */ -#define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U) -#define SEI_DAT_IDX_MAX_BIT_SHIFT (8U) -#define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK) -#define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT) - -/* - * MIN_BIT (RW) - * - * Lowest bit index - */ -#define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU) -#define SEI_DAT_IDX_MIN_BIT_SHIFT (0U) -#define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK) -#define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT) - -/* Bitfield definition for register of struct array DAT: GOLD */ -/* - * GOLD_VALUE (RW) - * - * Gold value for check mode - */ -#define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) -#define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U) -#define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK) -#define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT) - -/* Bitfield definition for register of struct array DAT: CRCINIT */ -/* - * CRC_INIT (RW) - * - * CRC initial value - */ -#define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) -#define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U) -#define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK) -#define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT) - -/* Bitfield definition for register of struct array DAT: CRCPOLY */ -/* - * CRC_POLY (RW) - * - * CRC polymonial - */ -#define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) -#define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U) -#define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) -#define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) - -/* Bitfield definition for register of struct array DAT: DATA */ -/* - * DATA (RW) - * - * DATA - */ -#define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SEI_DAT_DATA_DATA_SHIFT (0U) -#define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK) -#define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT) - -/* Bitfield definition for register of struct array DAT: SET */ -/* - * DATA_SET (RW) - * - * DATA bit set - */ -#define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL) -#define SEI_DAT_SET_DATA_SET_SHIFT (0U) -#define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK) -#define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT) - -/* Bitfield definition for register of struct array DAT: CLR */ -/* - * DATA_CLR (RW) - * - * DATA bit clear - */ -#define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) -#define SEI_DAT_CLR_DATA_CLR_SHIFT (0U) -#define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK) -#define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT) - -/* Bitfield definition for register of struct array DAT: INV */ -/* - * DATA_INV (RW) - * - * DATA bit toggle - */ -#define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL) -#define SEI_DAT_INV_DATA_INV_SHIFT (0U) -#define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK) -#define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT) - -/* Bitfield definition for register of struct array DAT: IN */ -/* - * DATA_IN (RO) - * - * Data input - */ -#define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL) -#define SEI_DAT_IN_DATA_IN_SHIFT (0U) -#define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT) - -/* Bitfield definition for register of struct array DAT: OUT */ -/* - * DATA_OUT (RO) - * - * Data output - */ -#define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) -#define SEI_DAT_OUT_DATA_OUT_SHIFT (0U) -#define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT) - -/* Bitfield definition for register of struct array DAT: STS */ -/* - * CRC_IDX (RO) - * - * CRC index - */ -#define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL) -#define SEI_DAT_STS_CRC_IDX_SHIFT (24U) -#define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT) - -/* - * WORD_IDX (RO) - * - * Word index - */ -#define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL) -#define SEI_DAT_STS_WORD_IDX_SHIFT (16U) -#define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT) - -/* - * WORD_CNT (RO) - * - * Word counter - */ -#define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U) -#define SEI_DAT_STS_WORD_CNT_SHIFT (8U) -#define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT) - -/* - * BIT_IDX (RO) - * - * Bit index - */ -#define SEI_DAT_STS_BIT_IDX_MASK (0x1FU) -#define SEI_DAT_STS_BIT_IDX_SHIFT (0U) -#define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT) - - - -/* CMD register group index macro definition */ -#define SEI_CTRL_TRG_TABLE_CMD_0 (0UL) -#define SEI_CTRL_TRG_TABLE_CMD_1 (1UL) -#define SEI_CTRL_TRG_TABLE_CMD_2 (2UL) -#define SEI_CTRL_TRG_TABLE_CMD_3 (3UL) - -/* TIME register group index macro definition */ -#define SEI_CTRL_TRG_TABLE_TIME_0 (0UL) -#define SEI_CTRL_TRG_TABLE_TIME_1 (1UL) -#define SEI_CTRL_TRG_TABLE_TIME_2 (2UL) -#define SEI_CTRL_TRG_TABLE_TIME_3 (3UL) - -/* CMD_TABLE register group index macro definition */ -#define SEI_CMD_TABLE_0 (0UL) -#define SEI_CMD_TABLE_1 (1UL) -#define SEI_CMD_TABLE_2 (2UL) -#define SEI_CMD_TABLE_3 (3UL) -#define SEI_CMD_TABLE_4 (4UL) -#define SEI_CMD_TABLE_5 (5UL) -#define SEI_CMD_TABLE_6 (6UL) -#define SEI_CMD_TABLE_7 (7UL) - -/* TRAN register group index macro definition */ -#define SEI_CTRL_LATCH_TRAN_0_1 (0UL) -#define SEI_CTRL_LATCH_TRAN_1_2 (1UL) -#define SEI_CTRL_LATCH_TRAN_2_3 (2UL) -#define SEI_CTRL_LATCH_TRAN_3_0 (3UL) - -/* LATCH register group index macro definition */ -#define SEI_LATCH_0 (0UL) -#define SEI_LATCH_1 (1UL) -#define SEI_LATCH_2 (2UL) -#define SEI_LATCH_3 (3UL) - -/* CTRL register group index macro definition */ -#define SEI_CTRL_0 (0UL) -#define SEI_CTRL_1 (1UL) - -/* INSTR register group index macro definition */ -#define SEI_INSTR_0 (0UL) -#define SEI_INSTR_1 (1UL) -#define SEI_INSTR_2 (2UL) -#define SEI_INSTR_3 (3UL) -#define SEI_INSTR_4 (4UL) -#define SEI_INSTR_5 (5UL) -#define SEI_INSTR_6 (6UL) -#define SEI_INSTR_7 (7UL) -#define SEI_INSTR_8 (8UL) -#define SEI_INSTR_9 (9UL) -#define SEI_INSTR_10 (10UL) -#define SEI_INSTR_11 (11UL) -#define SEI_INSTR_12 (12UL) -#define SEI_INSTR_13 (13UL) -#define SEI_INSTR_14 (14UL) -#define SEI_INSTR_15 (15UL) -#define SEI_INSTR_16 (16UL) -#define SEI_INSTR_17 (17UL) -#define SEI_INSTR_18 (18UL) -#define SEI_INSTR_19 (19UL) -#define SEI_INSTR_20 (20UL) -#define SEI_INSTR_21 (21UL) -#define SEI_INSTR_22 (22UL) -#define SEI_INSTR_23 (23UL) -#define SEI_INSTR_24 (24UL) -#define SEI_INSTR_25 (25UL) -#define SEI_INSTR_26 (26UL) -#define SEI_INSTR_27 (27UL) -#define SEI_INSTR_28 (28UL) -#define SEI_INSTR_29 (29UL) -#define SEI_INSTR_30 (30UL) -#define SEI_INSTR_31 (31UL) -#define SEI_INSTR_32 (32UL) -#define SEI_INSTR_33 (33UL) -#define SEI_INSTR_34 (34UL) -#define SEI_INSTR_35 (35UL) -#define SEI_INSTR_36 (36UL) -#define SEI_INSTR_37 (37UL) -#define SEI_INSTR_38 (38UL) -#define SEI_INSTR_39 (39UL) -#define SEI_INSTR_40 (40UL) -#define SEI_INSTR_41 (41UL) -#define SEI_INSTR_42 (42UL) -#define SEI_INSTR_43 (43UL) -#define SEI_INSTR_44 (44UL) -#define SEI_INSTR_45 (45UL) -#define SEI_INSTR_46 (46UL) -#define SEI_INSTR_47 (47UL) -#define SEI_INSTR_48 (48UL) -#define SEI_INSTR_49 (49UL) -#define SEI_INSTR_50 (50UL) -#define SEI_INSTR_51 (51UL) -#define SEI_INSTR_52 (52UL) -#define SEI_INSTR_53 (53UL) -#define SEI_INSTR_54 (54UL) -#define SEI_INSTR_55 (55UL) -#define SEI_INSTR_56 (56UL) -#define SEI_INSTR_57 (57UL) -#define SEI_INSTR_58 (58UL) -#define SEI_INSTR_59 (59UL) -#define SEI_INSTR_60 (60UL) -#define SEI_INSTR_61 (61UL) -#define SEI_INSTR_62 (62UL) -#define SEI_INSTR_63 (63UL) - -/* DAT register group index macro definition */ -#define SEI_DAT_0 (0UL) -#define SEI_DAT_1 (1UL) -#define SEI_DAT_2 (2UL) -#define SEI_DAT_3 (3UL) -#define SEI_DAT_4 (4UL) -#define SEI_DAT_5 (5UL) -#define SEI_DAT_6 (6UL) -#define SEI_DAT_7 (7UL) -#define SEI_DAT_8 (8UL) -#define SEI_DAT_9 (9UL) - - -#endif /* HPM_SEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_spi_regs.h deleted file mode 100644 index 204a3dc9961..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_spi_regs.h +++ /dev/null @@ -1,1034 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SPI_H -#define HPM_SPI_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t WR_TRANS_CNT; /* 0x4: Transfer count for write data */ - __RW uint32_t RD_TRANS_CNT; /* 0x8: Transfer count for read data */ - __R uint8_t RESERVED1[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ - __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ - __RW uint32_t CMD; /* 0x24: Command Register */ - __RW uint32_t ADDR; /* 0x28: Address Register */ - __RW uint32_t DATA; /* 0x2C: Data Register */ - __RW uint32_t CTRL; /* 0x30: Control Register */ - __R uint32_t STATUS; /* 0x34: Status Register */ - __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ - __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED3[28]; /* 0x44 - 0x5F: Reserved */ - __RW uint32_t SLVST; /* 0x60: Slave Status Register */ - __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint32_t SLVDATAWCNT; /* 0x68: WCnt */ - __R uint32_t SLVDATARCNT; /* 0x6C: RCnt */ - __R uint8_t RESERVED4[12]; /* 0x70 - 0x7B: Reserved */ - __R uint32_t CONFIG; /* 0x7C: Configuration Register */ -} SPI_Type; - - -/* Bitfield definition for register: WR_TRANS_CNT */ -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_WR_TRANS_CNT_WRTRANCNT_MASK (0xFFFFFFFFUL) -#define SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT (0U) -#define SPI_WR_TRANS_CNT_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) -#define SPI_WR_TRANS_CNT_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) >> SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) - -/* Bitfield definition for register: RD_TRANS_CNT */ -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_RD_TRANS_CNT_RDTRANCNT_MASK (0xFFFFFFFFUL) -#define SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT (0U) -#define SPI_RD_TRANS_CNT_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) -#define SPI_RD_TRANS_CNT_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) >> SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: TRANSFMT */ -/* - * ADDRLEN (RW) - * - * Address length in bytes - * 0x0: 1 byte - * 0x1: 2 bytes - * 0x2: 3 bytes - * 0x3: 4 bytes - */ -#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) -#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) -#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) -#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) - -/* - * DATALEN (RW) - * - * The length of each data unit in bits - * The actual bit number of a data unit is (DataLen + 1) - */ -#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) -#define SPI_TRANSFMT_DATALEN_SHIFT (8U) -#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) -#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) - -/* - * DATAMERGE (RW) - * - * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. - * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. - * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - */ -#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) -#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) -#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) -#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) - -/* - * MOSIBIDIR (RW) - * - * Bi-directional MOSI in regular (single) mode - * 0x0: MOSI is uni-directional signal in regular mode. - * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - */ -#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) -#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) -#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) -#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) - -/* - * LSB (RW) - * - * Transfer data with the least significant bit first - * 0x0: Most significant bit first - * 0x1: Least significant bit first - */ -#define SPI_TRANSFMT_LSB_MASK (0x8U) -#define SPI_TRANSFMT_LSB_SHIFT (3U) -#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) -#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) - -/* - * SLVMODE (RW) - * - * SPI Master/Slave mode selection - * 0x0: Master mode - * 0x1: Slave mode - */ -#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) -#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) -#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) -#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) - -/* - * CPOL (RW) - * - * SPI Clock Polarity - * 0x0: SCLK is LOW in the idle states - * 0x1: SCLK is HIGH in the idle states - */ -#define SPI_TRANSFMT_CPOL_MASK (0x2U) -#define SPI_TRANSFMT_CPOL_SHIFT (1U) -#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) -#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) - -/* - * CPHA (RW) - * - * SPI Clock Phase - * 0x0: Sampling data at odd SCLK edges - * 0x1: Sampling data at even SCLK edges - */ -#define SPI_TRANSFMT_CPHA_MASK (0x1U) -#define SPI_TRANSFMT_CPHA_SHIFT (0U) -#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) -#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) - -/* Bitfield definition for register: DIRECTIO */ -/* - * DIRECTIOEN (RW) - * - * Enable Direct IO - * 0x0: Disable - * 0x1: Enable - */ -#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) -#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) -#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) -#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) - -/* - * HOLD_OE (RW) - * - * Output enable for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) -#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) -#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) -#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) - -/* - * WP_OE (RW) - * - * Output enable for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) -#define SPI_DIRECTIO_WP_OE_SHIFT (20U) -#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) -#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) - -/* - * MISO_OE (RW) - * - * Output enable fo the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) -#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) -#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) -#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) - -/* - * MOSI_OE (RW) - * - * Output enable for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) -#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) -#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) -#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) - -/* - * SCLK_OE (RW) - * - * Output enable for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) -#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) -#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) -#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) - -/* - * CS_OE (RW) - * - * Output enable for SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) -#define SPI_DIRECTIO_CS_OE_SHIFT (16U) -#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) -#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) - -/* - * HOLD_O (RW) - * - * Output value for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) -#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) -#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) -#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) - -/* - * WP_O (RW) - * - * Output value for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_O_MASK (0x1000U) -#define SPI_DIRECTIO_WP_O_SHIFT (12U) -#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) -#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) - -/* - * MISO_O (RW) - * - * Output value for the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_O_MASK (0x800U) -#define SPI_DIRECTIO_MISO_O_SHIFT (11U) -#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) -#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) - -/* - * MOSI_O (RW) - * - * Output value for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) -#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) -#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) -#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) - -/* - * SCLK_O (RW) - * - * Output value for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) -#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) -#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) -#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) - -/* - * CS_O (RW) - * - * Output value for the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_O_MASK (0x100U) -#define SPI_DIRECTIO_CS_O_SHIFT (8U) -#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) -#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) - -/* - * HOLD_I (RO) - * - * Status of the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) -#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) -#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) - -/* - * WP_I (RO) - * - * Status of the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_I_MASK (0x10U) -#define SPI_DIRECTIO_WP_I_SHIFT (4U) -#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) - -/* - * MISO_I (RO) - * - * Status of the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_I_MASK (0x8U) -#define SPI_DIRECTIO_MISO_I_SHIFT (3U) -#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) - -/* - * MOSI_I (RO) - * - * Status of the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) -#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) -#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) - -/* - * SCLK_I (RO) - * - * Status of the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) -#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) -#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) - -/* - * CS_I (RO) - * - * Status of the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_I_MASK (0x1U) -#define SPI_DIRECTIO_CS_I_SHIFT (0U) -#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) - -/* Bitfield definition for register: TRANSCTRL */ -/* - * SLVDATAONLY (RW) - * - * Data-only mode (slave mode only) - * 0x0: Disable the data-only mode - * 0x1: Enable the data-only mode - * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - */ -#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) -#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) -#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) -#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) - -/* - * CMDEN (RW) - * - * SPI command phase enable (Master mode only) - * 0x0: Disable the command phase - * 0x1: Enable the command phase - */ -#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) -#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) -#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) -#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) - -/* - * ADDREN (RW) - * - * SPI address phase enable (Master mode only) - * 0x0: Disable the address phase - * 0x1: Enable the address phase - */ -#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) -#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) -#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) -#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) - -/* - * ADDRFMT (RW) - * - * SPI address phase format (Master mode only) - * 0x0: Address phase is the regular (single) mode - * 0x1: The format of the address phase is the same as the data phase (DualQuad). - */ -#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) -#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) -#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) -#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) - -/* - * TRANSMODE (RW) - * - * Transfer mode - * The transfer sequence could be - * 0x0: Write and read at the same time - * 0x1: Write only - * 0x2: Read only - * 0x3: Write, Read - * 0x4: Read, Write - * 0x5: Write, Dummy, Read - * 0x6: Read, Dummy, Write - * 0x7: None Data (must enable CmdEn or AddrEn in master mode) - * 0x8: Dummy, Write - * 0x9: Dummy, Read - * 0xa~0xf: Reserved - */ -#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) -#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) -#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) -#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) - -/* - * DUALQUAD (RW) - * - * SPI data phase format - * 0x0: Regular (Single) mode - * 0x1: Dual I/O mode - * 0x2: Quad I/O mode - * 0x3: Reserved - */ -#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) -#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) -#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) -#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) - -/* - * TOKENEN (RW) - * - * Token transfer enable (Master mode only) - * Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. - * 0x0: Disable the one-byte special token - * 0x1: Enable the one-byte special token - */ -#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) -#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) -#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) -#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) - -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) -#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) -#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) -#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) - -/* - * TOKENVALUE (RW) - * - * Token value (Master mode only) - * The value of the one-byte special token following the address phase for SPI read transfers. - * 0x0: token value = 0x00 - * 0x1: token value = 0x69 - */ -#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) -#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) -#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) -#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) - -/* - * DUMMYCNT (RW) - * - * Dummy data count. The actual dummy count is (DummyCnt +1). - * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) - * The Data pins are put into the high impedance during the dummy data phase. - * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - */ -#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) -#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) -#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) -#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) - -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) -#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) -#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) -#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * SPI Command - */ -#define SPI_CMD_CMD_MASK (0xFFU) -#define SPI_CMD_CMD_SHIFT (0U) -#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) -#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * SPI Address - * (Master mode only) - */ -#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define SPI_ADDR_ADDR_SHIFT (0U) -#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) -#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Data to transmit or the received data - * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. - * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - */ -#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SPI_DATA_DATA_SHIFT (0U) -#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) -#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * CS_EN (RW) - * - */ -#define SPI_CTRL_CS_EN_MASK (0xF000000UL) -#define SPI_CTRL_CS_EN_SHIFT (24U) -#define SPI_CTRL_CS_EN_SET(x) (((uint32_t)(x) << SPI_CTRL_CS_EN_SHIFT) & SPI_CTRL_CS_EN_MASK) -#define SPI_CTRL_CS_EN_GET(x) (((uint32_t)(x) & SPI_CTRL_CS_EN_MASK) >> SPI_CTRL_CS_EN_SHIFT) - -/* - * TXTHRES (RW) - * - * Transmit (TX) FIFO Threshold - * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - */ -#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) -#define SPI_CTRL_TXTHRES_SHIFT (16U) -#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) -#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) - -/* - * RXTHRES (RW) - * - * Receive (RX) FIFO Threshold - * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - */ -#define SPI_CTRL_RXTHRES_MASK (0xFF00U) -#define SPI_CTRL_RXTHRES_SHIFT (8U) -#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) -#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) - -/* - * TXDMAEN (RW) - * - * TX DMA enable - */ -#define SPI_CTRL_TXDMAEN_MASK (0x10U) -#define SPI_CTRL_TXDMAEN_SHIFT (4U) -#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) -#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) - -/* - * RXDMAEN (RW) - * - * RX DMA enable - */ -#define SPI_CTRL_RXDMAEN_MASK (0x8U) -#define SPI_CTRL_RXDMAEN_SHIFT (3U) -#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) -#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) - -/* - * TXFIFORST (RW) - * - * Transmit FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_TXFIFORST_MASK (0x4U) -#define SPI_CTRL_TXFIFORST_SHIFT (2U) -#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) -#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) - -/* - * RXFIFORST (RW) - * - * Receive FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_RXFIFORST_MASK (0x2U) -#define SPI_CTRL_RXFIFORST_SHIFT (1U) -#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) -#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) - -/* - * SPIRST (RW) - * - * SPI reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_SPIRST_MASK (0x1U) -#define SPI_CTRL_SPIRST_SHIFT (0U) -#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) -#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TXNUM_7_6 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) -#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) -#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) - -/* - * RXNUM_7_6 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) -#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) -#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) - -/* - * TXFULL (RO) - * - * Transmit FIFO Full flag - */ -#define SPI_STATUS_TXFULL_MASK (0x800000UL) -#define SPI_STATUS_TXFULL_SHIFT (23U) -#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) - -/* - * TXEMPTY (RO) - * - * Transmit FIFO Empty flag - */ -#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) -#define SPI_STATUS_TXEMPTY_SHIFT (22U) -#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) - -/* - * TXNUM_5_0 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) -#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) -#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) - -/* - * RXFULL (RO) - * - * Receive FIFO Full flag - */ -#define SPI_STATUS_RXFULL_MASK (0x8000U) -#define SPI_STATUS_RXFULL_SHIFT (15U) -#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) - -/* - * RXEMPTY (RO) - * - * Receive FIFO Empty flag - */ -#define SPI_STATUS_RXEMPTY_MASK (0x4000U) -#define SPI_STATUS_RXEMPTY_SHIFT (14U) -#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) - -/* - * RXNUM_5_0 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) -#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) -#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) - -/* - * SPIACTIVE (RO) - * - * SPI register programming is in progress. - * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. - * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. - * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. - * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - */ -#define SPI_STATUS_SPIACTIVE_MASK (0x1U) -#define SPI_STATUS_SPIACTIVE_SHIFT (0U) -#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) - -/* Bitfield definition for register: INTREN */ -/* - * SLVCMDEN (RW) - * - * Enable the Slave Command Interrupt. - * Control whether interrupts are triggered whenever slave commands are received. - * (Slave mode only) - */ -#define SPI_INTREN_SLVCMDEN_MASK (0x20U) -#define SPI_INTREN_SLVCMDEN_SHIFT (5U) -#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) -#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) - -/* - * ENDINTEN (RW) - * - * Enable the End of SPI Transfer interrupt. - * Control whether interrupts are triggered when SPI transfers end. - * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - */ -#define SPI_INTREN_ENDINTEN_MASK (0x10U) -#define SPI_INTREN_ENDINTEN_SHIFT (4U) -#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) -#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) - -/* - * TXFIFOINTEN (RW) - * - * Enable the SPI Transmit FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - */ -#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) -#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) -#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) -#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) - -/* - * RXFIFOINTEN (RW) - * - * Enable the SPI Receive FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - */ -#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) -#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) -#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) -#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) - -/* - * TXFIFOURINTEN (RW) - * - * Enable the SPI Transmit FIFO Underrun interrupt. - * Control whether interrupts are triggered when the Transmit FIFO run out of data. - * (Slave mode only) - */ -#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) -#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) -#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) -#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) - -/* - * RXFIFOORINTEN (RW) - * - * Enable the SPI Receive FIFO Overrun interrupt. - * Control whether interrupts are triggered when the Receive FIFO overflows. - * (Slave mode only) - */ -#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) -#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) -#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) -#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) - -/* Bitfield definition for register: INTRST */ -/* - * SLVCMDINT (W1C) - * - * Slave Command Interrupt. - * This bit is set when Slave Command interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_SLVCMDINT_MASK (0x20U) -#define SPI_INTRST_SLVCMDINT_SHIFT (5U) -#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) -#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) - -/* - * ENDINT (W1C) - * - * End of SPI Transfer interrupt. - * This bit is set when End of SPI Transfer interrupts occur. - */ -#define SPI_INTRST_ENDINT_MASK (0x10U) -#define SPI_INTRST_ENDINT_SHIFT (4U) -#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) -#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) - -/* - * TXFIFOINT (W1C) - * - * TX FIFO Threshold interrupt. - * This bit is set when TX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_TXFIFOINT_MASK (0x8U) -#define SPI_INTRST_TXFIFOINT_SHIFT (3U) -#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) -#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) - -/* - * RXFIFOINT (W1C) - * - * RX FIFO Threshold interrupt. - * This bit is set when RX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_RXFIFOINT_MASK (0x4U) -#define SPI_INTRST_RXFIFOINT_SHIFT (2U) -#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) -#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) - -/* - * TXFIFOURINT (W1C) - * - * TX FIFO Underrun interrupt. - * This bit is set when TX FIFO Underrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) -#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) -#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) -#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) - -/* - * RXFIFOORINT (W1C) - * - * RX FIFO Overrun interrupt. - * This bit is set when RX FIFO Overrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) -#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) -#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) -#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) - -/* Bitfield definition for register: TIMING */ -/* - * CS2SCLK (RW) - * - * The minimum time between the edges of SPI CS and the edges of SCLK. - * SCLK_period * (CS2SCLK + 1) / 2 - */ -#define SPI_TIMING_CS2SCLK_MASK (0x3000U) -#define SPI_TIMING_CS2SCLK_SHIFT (12U) -#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) -#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) - -/* - * CSHT (RW) - * - * The minimum time that SPI CS should stay HIGH. - * SCLK_period * (CSHT + 1) / 2 - */ -#define SPI_TIMING_CSHT_MASK (0xF00U) -#define SPI_TIMING_CSHT_SHIFT (8U) -#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) -#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) - -/* - * SCLK_DIV (RW) - * - * The clock frequency ratio between the clock source and SPI interface SCLK. - * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) - * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - */ -#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) -#define SPI_TIMING_SCLK_DIV_SHIFT (0U) -#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) -#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) - -/* Bitfield definition for register: SLVST */ -/* - * UNDERRUN (W1C) - * - * Data underrun occurs in the last transaction - */ -#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) -#define SPI_SLVST_UNDERRUN_SHIFT (18U) -#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) -#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) - -/* - * OVERRUN (RW) - * - * Data overrun occurs in the last transaction - */ -#define SPI_SLVST_OVERRUN_MASK (0x20000UL) -#define SPI_SLVST_OVERRUN_SHIFT (17U) -#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) -#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) - -/* - * READY (RW) - * - * Set this bit to indicate that the ATCSPI200 is ready for data transaction. - * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - */ -#define SPI_SLVST_READY_MASK (0x10000UL) -#define SPI_SLVST_READY_SHIFT (16U) -#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) -#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) - -/* - * USR_STATUS (RW) - * - * User defined status flags - */ -#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) -#define SPI_SLVST_USR_STATUS_SHIFT (0U) -#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) -#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) - -/* Bitfield definition for register: SLVDATACNT */ -/* - * WCNT (RO) - * - * Slave transmitted data count - */ -#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) -#define SPI_SLVDATACNT_WCNT_SHIFT (16U) -#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) - -/* - * RCNT (RO) - * - * Slave received data count - */ -#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) -#define SPI_SLVDATACNT_RCNT_SHIFT (0U) -#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) - -/* Bitfield definition for register: SLVDATAWCNT */ -/* - * VAL (RO) - * - */ -#define SPI_SLVDATAWCNT_VAL_MASK (0xFFFFFFFFUL) -#define SPI_SLVDATAWCNT_VAL_SHIFT (0U) -#define SPI_SLVDATAWCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATAWCNT_VAL_MASK) >> SPI_SLVDATAWCNT_VAL_SHIFT) - -/* Bitfield definition for register: SLVDATARCNT */ -/* - * VAL (RO) - * - */ -#define SPI_SLVDATARCNT_VAL_MASK (0xFFFFFFFFUL) -#define SPI_SLVDATARCNT_VAL_SHIFT (0U) -#define SPI_SLVDATARCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATARCNT_VAL_MASK) >> SPI_SLVDATARCNT_VAL_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * SLAVE (RO) - * - * Support for SPI Slave mode - */ -#define SPI_CONFIG_SLAVE_MASK (0x4000U) -#define SPI_CONFIG_SLAVE_SHIFT (14U) -#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) - -/* - * QUADSPI (RO) - * - * Support for Quad I/O SPI - */ -#define SPI_CONFIG_QUADSPI_MASK (0x200U) -#define SPI_CONFIG_QUADSPI_SHIFT (9U) -#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) - -/* - * DUALSPI (RO) - * - * Support for Dual I/O SPI - */ -#define SPI_CONFIG_DUALSPI_MASK (0x100U) -#define SPI_CONFIG_DUALSPI_SHIFT (8U) -#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) - -/* - * TXFIFOSIZE (RO) - * - * Depth of TX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) -#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) -#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) - -/* - * RXFIFOSIZE (RO) - * - * Depth of RX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) -#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) -#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) - - - - -#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_synt_regs.h deleted file mode 100644 index 789767e1138..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_synt_regs.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYNT_H -#define HPM_SYNT_H - -typedef struct { - __RW uint32_t GCR; /* 0x0: Global control register */ - __RW uint32_t RLD; /* 0x4: Counter reload register */ - __RW uint32_t TIMESTAMP_NEW; /* 0x8: timestamp new value register */ - __R uint32_t CNT; /* 0xC: Counter */ - __R uint32_t TIMESTAMP_SAV; /* 0x10: timestamp trig save value */ - __R uint32_t TIMESTAMP_CUR; /* 0x14: timestamp read value */ - __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ -} SYNT_Type; - - -/* Bitfield definition for register: GCR */ -/* - * TIMESTAMP_INC_NEW (WO) - * - * set to increase the timesamp with new value, auto clr - */ -#define SYNT_GCR_TIMESTAMP_INC_NEW_MASK (0x80000000UL) -#define SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT (31U) -#define SYNT_GCR_TIMESTAMP_INC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) -#define SYNT_GCR_TIMESTAMP_INC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) - -/* - * TIMESTAMP_DEC_NEW (WO) - * - * set to decrease the timesamp with new value, auto clr - */ -#define SYNT_GCR_TIMESTAMP_DEC_NEW_MASK (0x40000000UL) -#define SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT (30U) -#define SYNT_GCR_TIMESTAMP_DEC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) -#define SYNT_GCR_TIMESTAMP_DEC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) - -/* - * TIMESTAMP_SET_NEW (WO) - * - * set the timesamp to new value, auto clr - */ -#define SYNT_GCR_TIMESTAMP_SET_NEW_MASK (0x20000000UL) -#define SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT (29U) -#define SYNT_GCR_TIMESTAMP_SET_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) -#define SYNT_GCR_TIMESTAMP_SET_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) >> SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) - -/* - * TIMESTAMP_RESET (WO) - * - * reset timesamp to 0, auto clr - */ -#define SYNT_GCR_TIMESTAMP_RESET_MASK (0x10000000UL) -#define SYNT_GCR_TIMESTAMP_RESET_SHIFT (28U) -#define SYNT_GCR_TIMESTAMP_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_RESET_SHIFT) & SYNT_GCR_TIMESTAMP_RESET_MASK) -#define SYNT_GCR_TIMESTAMP_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_RESET_MASK) >> SYNT_GCR_TIMESTAMP_RESET_SHIFT) - -/* - * TIMESTAMP_DEBUG_EN (RW) - * - * set to enable cpu_debug_mode to stop the timesamp - */ -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK (0x20U) -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT (5U) -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) >> SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) - -/* - * TIMESTAMP_ENABLE (RW) - * - * set to enable the timesamp , clr to stop - */ -#define SYNT_GCR_TIMESTAMP_ENABLE_MASK (0x10U) -#define SYNT_GCR_TIMESTAMP_ENABLE_SHIFT (4U) -#define SYNT_GCR_TIMESTAMP_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) -#define SYNT_GCR_TIMESTAMP_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) >> SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) - -/* - * COUNTER_DEBUG_EN (RW) - * - * set to enable cpu_debug_mode to stop the counter - */ -#define SYNT_GCR_COUNTER_DEBUG_EN_MASK (0x4U) -#define SYNT_GCR_COUNTER_DEBUG_EN_SHIFT (2U) -#define SYNT_GCR_COUNTER_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) -#define SYNT_GCR_COUNTER_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) >> SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) - -/* - * CRST (RW) - * - * 1- Reset counter - */ -#define SYNT_GCR_CRST_MASK (0x2U) -#define SYNT_GCR_CRST_SHIFT (1U) -#define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK) -#define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT) - -/* - * CEN (RW) - * - * 1- Enable counter - */ -#define SYNT_GCR_CEN_MASK (0x1U) -#define SYNT_GCR_CEN_SHIFT (0U) -#define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK) -#define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * RLD (RW) - * - * counter reload value - */ -#define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL) -#define SYNT_RLD_RLD_SHIFT (0U) -#define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) -#define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_NEW */ -/* - * VALUE (RW) - * - * new value for timesamp , can be used as set/inc/dec - */ -#define SYNT_TIMESTAMP_NEW_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_TIMESTAMP_NEW_VALUE_SHIFT (0U) -#define SYNT_TIMESTAMP_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_TIMESTAMP_NEW_VALUE_SHIFT) & SYNT_TIMESTAMP_NEW_VALUE_MASK) -#define SYNT_TIMESTAMP_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_NEW_VALUE_MASK) >> SYNT_TIMESTAMP_NEW_VALUE_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * CNT (RO) - * - * counter - */ -#define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL) -#define SYNT_CNT_CNT_SHIFT (0U) -#define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_SAV */ -/* - * VALUE (RO) - * - * use the trigger to save timesamp here - */ -#define SYNT_TIMESTAMP_SAV_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_TIMESTAMP_SAV_VALUE_SHIFT (0U) -#define SYNT_TIMESTAMP_SAV_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_SAV_VALUE_MASK) >> SYNT_TIMESTAMP_SAV_VALUE_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_CUR */ -/* - * VALUE (RO) - * - * current timesamp value - */ -#define SYNT_TIMESTAMP_CUR_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_TIMESTAMP_CUR_VALUE_SHIFT (0U) -#define SYNT_TIMESTAMP_CUR_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_CUR_VALUE_MASK) >> SYNT_TIMESTAMP_CUR_VALUE_SHIFT) - -/* Bitfield definition for register array: CMP */ -/* - * CMP (RW) - * - * comparator value, the output will assert when counter count to this value - */ -#define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL) -#define SYNT_CMP_CMP_SHIFT (0U) -#define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK) -#define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT) - - - -/* CMP register group index macro definition */ -#define SYNT_CMP_0 (0UL) -#define SYNT_CMP_1 (1UL) -#define SYNT_CMP_2 (2UL) -#define SYNT_CMP_3 (3UL) - - -#endif /* HPM_SYNT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sysctl_regs.h deleted file mode 100644 index 489fa19d41b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_sysctl_regs.h +++ /dev/null @@ -1,1271 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYSCTL_H -#define HPM_SYSCTL_H - -typedef struct { - __RW uint32_t RESOURCE[311]; /* 0x0 - 0x4D8: Resource control register for cpu0_core */ - __R uint8_t RESERVED0[804]; /* 0x4DC - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: Group setting */ - __RW uint32_t SET; /* 0x804: Group setting */ - __RW uint32_t CLEAR; /* 0x808: Group setting */ - __RW uint32_t TOGGLE; /* 0x80C: Group setting */ - } GROUP0[2]; - __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ - __RW uint32_t SET; /* 0x904: Affiliate of Group */ - __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ - __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ - } AFFILIATE[1]; - __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x920: Retention Control */ - __RW uint32_t SET; /* 0x924: Retention Control */ - __RW uint32_t CLEAR; /* 0x928: Retention Control */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ - } RETENTION[1]; - __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ - struct { - __RW uint32_t STATUS; /* 0x1000: Power Setting */ - __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ - __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ - __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ - __RW uint32_t RET_WAIT; /* 0x1010: Power Setting */ - } POWER[1]; - __R uint8_t RESERVED4[1004]; /* 0x1014 - 0x13FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ - __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ - __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ - __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ - } RESET[2]; - __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ - __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ - __RW uint32_t CLOCK[36]; /* 0x1804 - 0x1890: Clock setting */ - __R uint8_t RESERVED6[876]; /* 0x1894 - 0x1BFF: Reserved */ - __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ - __RW uint32_t DACCLK[2]; /* 0x1C08 - 0x1C0C: Clock setting */ - __R uint8_t RESERVED7[1008]; /* 0x1C10 - 0x1FFF: Reserved */ - __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ - __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ - __R uint32_t CURRENT; /* 0x2404: Clock measure result */ - __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ - __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ - __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ - } MONITOR[4]; - __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ - struct { - __RW uint32_t LP; /* 0x2800: CPU0 LP control */ - __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ - __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ - __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ - __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ - __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ - __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ - } CPU[1]; -} SYSCTL_Type; - - -/* Bitfield definition for register array: RESOURCE */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any nodes - * 1: any of nodes is changing status - */ -#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) -#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: no change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) -#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) - -/* - * MODE (RW) - * - * resource work mode - * 0:auto turn on and off as system required(recommended) - * 1:always on - * 2:always off - * 3:reserved - */ -#define SYSCTL_RESOURCE_MODE_MASK (0x3U) -#define SYSCTL_RESOURCE_MODE_SHIFT (0U) -#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) -#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) -#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) -#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) -#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: VALUE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * bit0: cpu0 depends on group0 - * bit1: cpu0 depends on group1 - * bit2: cpu0 depends on group2 - * bit3: cpu0 depends on group3 - */ -#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) -#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: SET */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0，each bit represents a group - * 0: no effect - * 1: the group is assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) -#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: the group is not assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) -#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: toggle the result that whether the group is assigned to CPU0 before - */ -#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: VALUE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * bit00: soc_mem is kept on while cpu0 stop - * bit01: soc_ctx is kept on while cpu0 stop - * bit02: cpu0_mem is kept on while cpu0 stop - * bit03: cpu0_ctx is kept on while cpu0 stop - * bit04: xtal_hold is kept on while cpu0 stop - * bit05: pll0_hold is kept on while cpu0 stop - * bit06: pll1_hold is kept on while cpu0 stop - */ -#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) -#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: SET */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: keep - */ -#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) -#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: CLEAR */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: no keep - */ -#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) -#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: TOGGLE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: toggle the result that whether the resource is kept on while CPU0 stop before - */ -#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) -#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array POWER: STATUS */ -/* - * FLAG (RW) - * - * flag represents power cycle happened from last clear of this bit - * 0: power domain did not edurance power cycle since last clear of this bit - * 1: power domain enduranced power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) -#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) -#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) -#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup power cycle happened from last clear of this bit - * 0: power domain did not edurance wakeup power cycle since last clear of this bit - * 1: power domain enduranced wakeup power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) - -/* - * MEM_RET_N (RO) - * - * memory info retention control signal - * 0: memory enter retention mode - * 1: memory exit retention mode - */ -#define SYSCTL_POWER_STATUS_MEM_RET_N_MASK (0x20000UL) -#define SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT (17U) -#define SYSCTL_POWER_STATUS_MEM_RET_N_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_N_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_N_SHIFT) - -/* - * MEM_RET_P (RO) - * - * memory info retention control signal - * 0: memory not enterexitretention mode - * 1: memory enter retention mode - */ -#define SYSCTL_POWER_STATUS_MEM_RET_P_MASK (0x10000UL) -#define SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT (16U) -#define SYSCTL_POWER_STATUS_MEM_RET_P_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_MEM_RET_P_MASK) >> SYSCTL_POWER_STATUS_MEM_RET_P_SHIFT) - -/* - * LF_DISABLE (RO) - * - * low fanout power switch disable - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) - -/* - * LF_ACK (RO) - * - * low fanout power switch feedback - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) -#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) -#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) - -/* Bitfield definition for register of struct array POWER: LF_WAIT */ -/* - * WAIT (RW) - * - * wait time for low fan out power switch turn on, default value is 255 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: OFF_WAIT */ -/* - * WAIT (RW) - * - * wait time for power switch turn off, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: RET_WAIT */ -/* - * WAIT (RW) - * - * wait time for memory retention mode transition, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_RET_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_RET_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_RET_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) -#define SYSCTL_POWER_RET_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_RET_WAIT_WAIT_MASK) >> SYSCTL_POWER_RET_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONTROL */ -/* - * FLAG (RW) - * - * flag represents reset happened from last clear of this bit - * 0: domain did not edurance reset cycle since last clear of this bit - * 1: domain enduranced reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) -#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup reset happened from last clear of this bit - * 0: domain did not edurance wakeup reset cycle since last clear of this bit - * 1: domain enduranced wakeup reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) - -/* - * HOLD (RW) - * - * perform reset and hold in reset, until ths bit cleared by software - * 0: reset is released for function - * 1: reset is assert and hold - */ -#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) -#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) -#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) -#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) - -/* - * RESET (RW) - * - * perform reset and release imediately - * 0: reset is released - * 1 reset is asserted and will release automatically - */ -#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) -#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) -#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) -#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONFIG */ -/* - * PRE_WAIT (RW) - * - * wait cycle numbers before assert reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) - -/* - * RSTCLK_NUM (RW) - * - * reset clock number(must be even number) - * 0: 0 cycle - * 1: 0 cycles - * 2: 2 cycles - * 3: 2 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) - -/* - * POST_WAIT (RW) - * - * time guard band for reset release - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: COUNTER */ -/* - * COUNTER (RW) - * - * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) -#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) -#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) -#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) - -/* Bitfield definition for register array: CLOCK_CPU */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) -#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) - -/* - * SUB0_DIV (RW) - * - * ahb bus divider, the bus clock is generated by cpu_clock/div - * 0: divider by 1 - * 1: divider by 2 - * … - */ -#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll0_clk2 - * 4:pll1_clk0 - * 5:pll1_clk1 - * 6:pll1_clk2 - * 7:pll1_clk3 - */ -#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) -#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) -#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) -#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) - -/* Bitfield definition for register array: CLOCK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) -#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll0_clk2 - * 4:pll1_clk0 - * 5:pll1_clk1 - * 6:pll1_clk2 - * 7:pll1_clk3 - */ -#define SYSCTL_CLOCK_MUX_MASK (0x700U) -#define SYSCTL_CLOCK_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) -#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) -#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) - -/* Bitfield definition for register array: ADCCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) -#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ahb0 clock - * 1: ana clock N - */ -#define SYSCTL_ADCCLK_MUX_MASK (0x100U) -#define SYSCTL_ADCCLK_MUX_SHIFT (8U) -#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) -#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) - -/* Bitfield definition for register array: DACCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) -#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ahb0 clock - * 1: ana clock N - */ -#define SYSCTL_DACCLK_MUX_MASK (0x100U) -#define SYSCTL_DACCLK_MUX_SHIFT (8U) -#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) -#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) - -/* Bitfield definition for register: GLOBAL00 */ -/* - * MUX (RW) - * - * global clock override request - * bit0: override to preset0 - * bit1: override to preset1 - * bit2: override to preset2 - * bit3: override to preset3 - * bit4: override to preset4 - * bit5: override to preset5 - * bit6: override to preset6 - * bit7: override to preset7 - */ -#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) -#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) -#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) -#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * VALID (RW) - * - * result is ready for read - * 0: not ready - * 1: result is ready - */ -#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) -#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) -#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) -#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) - -/* - * DIV_BUSY (RO) - * - * divider is applying new setting - */ -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) - -/* - * OUTEN (RW) - * - * enable clock output - */ -#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) -#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) - -/* - * DIV (RW) - * - * output divider - */ -#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) -#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) -#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) - -/* - * HIGH (RW) - * - * clock frequency higher than upper limit - */ -#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) -#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock frequency lower than lower limit - */ -#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) -#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) -#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) -#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) - -/* - * START (RW) - * - * start measurement - */ -#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) -#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) -#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) -#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) - -/* - * MODE (RW) - * - * work mode, - * 0: register value will be compared to measurement - * 1: upper and lower value will be recordered in register - */ -#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) -#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) -#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) -#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) - -/* - * ACCURACY (RW) - * - * measurement accuracy, - * 0: resolution is 1kHz - * 1: resolution is 1Hz - */ -#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) - -/* - * REFERENCE (RW) - * - * reference clock selection, - * 0: 32k - * 1: 24M - */ -#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) - -/* - * SELECTION (RW) - * - * clock measurement selection - */ -#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) -#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CURRENT */ -/* - * FREQUENCY (RO) - * - * self updating measure result - */ -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ -/* - * FREQUENCY (RW) - * - * lower frequency - */ -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ -/* - * FREQUENCY (RW) - * - * upper frequency - */ -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array CPU: LP */ -/* - * WAKE_CNT (RW) - * - * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - */ -#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) -#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) -#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) -#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) - -/* - * HALT (RW) - * - * halt request for CPU0, - * 0: CPU0 will start to execute after reset or receive wakeup request - * 1: CPU0 will not start after reset, or wakeup after WFI - */ -#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) -#define SYSCTL_CPU_LP_HALT_SHIFT (16U) -#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) -#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) - -/* - * WAKE (RO) - * - * CPU0 is waking up - * 0: CPU0 wake up not asserted - * 1: CPU0 wake up asserted - */ -#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) -#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) -#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) - -/* - * EXEC (RO) - * - * CPU0 is executing - * 0: CPU0 is not executing - * 1: CPU0 is executing - */ -#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) -#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) -#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) - -/* - * WAKE_FLAG (RW) - * - * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit - * 0: CPU0 wakeup not happened - * 1: CPU0 wake up happened - */ -#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) -#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) - -/* - * SLEEP_FLAG (RW) - * - * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) -#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) - -/* - * RESET_FLAG (RW) - * - * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit - * 0: CPU0 reset not happened - * 1: CPU0 reset happened - */ -#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) -#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) -#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) -#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) - -/* - * MODE (RW) - * - * Low power mode, system behavior after WFI - * 00: CPU clock stop after WFI - * 01: System enter low power mode after WFI - * 10: Keep running after WFI - * 11: reserved - */ -#define SYSCTL_CPU_LP_MODE_MASK (0x3U) -#define SYSCTL_CPU_LP_MODE_SHIFT (0U) -#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) -#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) - -/* Bitfield definition for register of struct array CPU: LOCK */ -/* - * GPR (RW) - * - * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - */ -#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) -#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) -#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) -#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) - -/* - * LOCK (RW) - * - * Lock bit for CPU_LOCK - */ -#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) -#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) -#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) -#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register of struct array CPU: GPR0 */ -/* - * GPR (RW) - * - * register for software to handle resume, can save resume address or status - */ -#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) -#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) -#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) - -/* Bitfield definition for register of struct array CPU: STATUS0 */ -/* - * STATUS (RO) - * - * IRQ values - */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register of struct array CPU: ENABLE0 */ -/* - * ENABLE (RW) - * - * IRQ wakeup enable - */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) - - - -/* RESOURCE register group index macro definition */ -#define SYSCTL_RESOURCE_CPU0 (0UL) -#define SYSCTL_RESOURCE_CPX0 (1UL) -#define SYSCTL_RESOURCE_POW_CPU0 (21UL) -#define SYSCTL_RESOURCE_RST_SOC (22UL) -#define SYSCTL_RESOURCE_RST_CPU0 (23UL) -#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (40UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK3_PLL1 (41UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (42UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (43UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (66UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (67UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (68UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (69UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (74UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (75UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (76UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (77UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (78UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (79UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (80UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (81UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (82UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (83UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (84UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (85UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT0 (86UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT1 (87UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT2 (88UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT3 (89UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT4 (90UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT5 (91UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT6 (92UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT7 (93UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (94UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (95UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (96UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (97UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (98UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF0 (99UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF1 (100UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (101UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (102UL) -#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (103UL) -#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (104UL) -#define SYSCTL_RESOURCE_AHB0 (256UL) -#define SYSCTL_RESOURCE_LMM0 (257UL) -#define SYSCTL_RESOURCE_MCT0 (258UL) -#define SYSCTL_RESOURCE_ROM0 (259UL) -#define SYSCTL_RESOURCE_CAN0 (260UL) -#define SYSCTL_RESOURCE_CAN1 (261UL) -#define SYSCTL_RESOURCE_CAN2 (262UL) -#define SYSCTL_RESOURCE_CAN3 (263UL) -#define SYSCTL_RESOURCE_PTPC (264UL) -#define SYSCTL_RESOURCE_TMR0 (269UL) -#define SYSCTL_RESOURCE_TMR1 (270UL) -#define SYSCTL_RESOURCE_TMR2 (271UL) -#define SYSCTL_RESOURCE_TMR3 (272UL) -#define SYSCTL_RESOURCE_I2C0 (273UL) -#define SYSCTL_RESOURCE_I2C1 (274UL) -#define SYSCTL_RESOURCE_I2C2 (275UL) -#define SYSCTL_RESOURCE_I2C3 (276UL) -#define SYSCTL_RESOURCE_SPI0 (277UL) -#define SYSCTL_RESOURCE_SPI1 (278UL) -#define SYSCTL_RESOURCE_SPI2 (279UL) -#define SYSCTL_RESOURCE_SPI3 (280UL) -#define SYSCTL_RESOURCE_URT0 (281UL) -#define SYSCTL_RESOURCE_URT1 (282UL) -#define SYSCTL_RESOURCE_URT2 (283UL) -#define SYSCTL_RESOURCE_URT3 (284UL) -#define SYSCTL_RESOURCE_URT4 (285UL) -#define SYSCTL_RESOURCE_URT5 (286UL) -#define SYSCTL_RESOURCE_URT6 (287UL) -#define SYSCTL_RESOURCE_URT7 (288UL) -#define SYSCTL_RESOURCE_WDG0 (289UL) -#define SYSCTL_RESOURCE_WDG1 (290UL) -#define SYSCTL_RESOURCE_MBX0 (291UL) -#define SYSCTL_RESOURCE_TSNS (292UL) -#define SYSCTL_RESOURCE_CRC0 (293UL) -#define SYSCTL_RESOURCE_ADC0 (294UL) -#define SYSCTL_RESOURCE_ADC1 (295UL) -#define SYSCTL_RESOURCE_DAC0 (296UL) -#define SYSCTL_RESOURCE_DAC1 (297UL) -#define SYSCTL_RESOURCE_ACMP (298UL) -#define SYSCTL_RESOURCE_OPA0 (299UL) -#define SYSCTL_RESOURCE_OPA1 (300UL) -#define SYSCTL_RESOURCE_MOT0 (301UL) -#define SYSCTL_RESOURCE_RNG0 (302UL) -#define SYSCTL_RESOURCE_SDP0 (303UL) -#define SYSCTL_RESOURCE_KMAN (304UL) -#define SYSCTL_RESOURCE_GPIO (305UL) -#define SYSCTL_RESOURCE_HDMA (306UL) -#define SYSCTL_RESOURCE_XPI0 (307UL) -#define SYSCTL_RESOURCE_USB0 (308UL) -#define SYSCTL_RESOURCE_REF0 (309UL) -#define SYSCTL_RESOURCE_REF1 (310UL) - -/* GROUP0 register group index macro definition */ -#define SYSCTL_GROUP0_LINK0 (0UL) -#define SYSCTL_GROUP0_LINK1 (1UL) - -/* AFFILIATE register group index macro definition */ -#define SYSCTL_AFFILIATE_CPU0 (0UL) - -/* RETENTION register group index macro definition */ -#define SYSCTL_RETENTION_CPU0 (0UL) - -/* POWER register group index macro definition */ -#define SYSCTL_POWER_CPU0 (0UL) - -/* RESET register group index macro definition */ -#define SYSCTL_RESET_SOC (0UL) -#define SYSCTL_RESET_CPU0 (1UL) - -/* CLOCK_CPU register group index macro definition */ -#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) - -/* CLOCK register group index macro definition */ -#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN0 (1UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN1 (2UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN2 (3UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN3 (4UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C0 (13UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C1 (14UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C2 (15UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C3 (16UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI0 (17UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI1 (18UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI2 (19UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI3 (20UL) -#define SYSCTL_CLOCK_CLK_TOP_URT0 (21UL) -#define SYSCTL_CLOCK_CLK_TOP_URT1 (22UL) -#define SYSCTL_CLOCK_CLK_TOP_URT2 (23UL) -#define SYSCTL_CLOCK_CLK_TOP_URT3 (24UL) -#define SYSCTL_CLOCK_CLK_TOP_URT4 (25UL) -#define SYSCTL_CLOCK_CLK_TOP_URT5 (26UL) -#define SYSCTL_CLOCK_CLK_TOP_URT6 (27UL) -#define SYSCTL_CLOCK_CLK_TOP_URT7 (28UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI0 (29UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA0 (30UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA1 (31UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA2 (32UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA3 (33UL) -#define SYSCTL_CLOCK_CLK_TOP_REF0 (34UL) -#define SYSCTL_CLOCK_CLK_TOP_REF1 (35UL) - -/* ADCCLK register group index macro definition */ -#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) - -/* DACCLK register group index macro definition */ -#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) -#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) - -/* MONITOR register group index macro definition */ -#define SYSCTL_MONITOR_SLICE0 (0UL) -#define SYSCTL_MONITOR_SLICE1 (1UL) -#define SYSCTL_MONITOR_SLICE2 (2UL) -#define SYSCTL_MONITOR_SLICE3 (3UL) - -/* GPR register group index macro definition */ -#define SYSCTL_CPU_GPR_GPR0 (0UL) -#define SYSCTL_CPU_GPR_GPR1 (1UL) -#define SYSCTL_CPU_GPR_GPR2 (2UL) -#define SYSCTL_CPU_GPR_GPR3 (3UL) -#define SYSCTL_CPU_GPR_GPR4 (4UL) -#define SYSCTL_CPU_GPR_GPR5 (5UL) -#define SYSCTL_CPU_GPR_GPR6 (6UL) -#define SYSCTL_CPU_GPR_GPR7 (7UL) -#define SYSCTL_CPU_GPR_GPR8 (8UL) -#define SYSCTL_CPU_GPR_GPR9 (9UL) -#define SYSCTL_CPU_GPR_GPR10 (10UL) -#define SYSCTL_CPU_GPR_GPR11 (11UL) -#define SYSCTL_CPU_GPR_GPR12 (12UL) -#define SYSCTL_CPU_GPR_GPR13 (13UL) - -/* WAKEUP_STATUS register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) - -/* WAKEUP_ENABLE register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) - -/* CPU register group index macro definition */ -#define SYSCTL_CPU_CPU0 (0UL) - - -#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_trgm_regs.h deleted file mode 100644 index 4d712e28520..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_trgm_regs.h +++ /dev/null @@ -1,535 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGM_H -#define HPM_TRGM_H - -typedef struct { - __RW uint32_t FILTCFG[28]; /* 0x0 - 0x6C: Filter configure register */ - __R uint8_t RESERVED0[144]; /* 0x70 - 0xFF: Reserved */ - __RW uint32_t TRGOCFG[137]; /* 0x100 - 0x320: Trigger manager output configure register */ - __R uint8_t RESERVED1[220]; /* 0x324 - 0x3FF: Reserved */ - __RW uint32_t DMACFG[8]; /* 0x400 - 0x41C: DMA request configure register */ - __R uint8_t RESERVED2[224]; /* 0x420 - 0x4FF: Reserved */ - __RW uint32_t GCR; /* 0x500: General Control Register */ - __R uint8_t RESERVED3[12]; /* 0x504 - 0x50F: Reserved */ - __RW uint32_t ADC_MATRIX_SEL; /* 0x510: adc matrix select register */ - __RW uint32_t DAC_MATRIX_SEL; /* 0x514: dac matrix select register */ - __RW uint32_t POS_MATRIX_SEL0; /* 0x518: position matrix select register0 */ - __RW uint32_t POS_MATRIX_SEL1; /* 0x51C: position matrix select register1 */ - __R uint8_t RESERVED4[224]; /* 0x520 - 0x5FF: Reserved */ - __R uint32_t TRGM_IN[4]; /* 0x600 - 0x60C: trigmux input read register0 */ - __R uint8_t RESERVED5[16]; /* 0x610 - 0x61F: Reserved */ - __R uint32_t TRGM_OUT[5]; /* 0x620 - 0x630: trigmux output read register0 */ -} TRGM_Type; - - -/* Bitfield definition for register array: FILTCFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) -#define TRGM_FILTCFG_OUTINV_SHIFT (16U) -#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) -#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stalbe low mode; - * 111-stable high mode - */ -#define TRGM_FILTCFG_MODE_MASK (0xE000U) -#define TRGM_FILTCFG_MODE_SHIFT (13U) -#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) -#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) -#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) -#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) -#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) - -/* - * FILTLEN_SHIFT (RW) - * - */ -#define TRGM_FILTCFG_FILTLEN_SHIFT_MASK (0xE00U) -#define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT (9U) -#define TRGM_FILTCFG_FILTLEN_SHIFT_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) -#define TRGM_FILTCFG_FILTLEN_SHIFT_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) - -/* - * FILTLEN_BASE (RW) - * - * This bitfields defines the filter counter length. - */ -#define TRGM_FILTCFG_FILTLEN_BASE_MASK (0x1FFU) -#define TRGM_FILTCFG_FILTLEN_BASE_SHIFT (0U) -#define TRGM_FILTCFG_FILTLEN_BASE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK) -#define TRGM_FILTCFG_FILTLEN_BASE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT) - -/* Bitfield definition for register array: TRGOCFG */ -/* - * OUTINV (RW) - * - * 1- Invert the output - */ -#define TRGM_TRGOCFG_OUTINV_MASK (0x800U) -#define TRGM_TRGOCFG_OUTINV_SHIFT (11U) -#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) -#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) - -/* - * FEDG2PEN (RW) - * - * 1- The selected input signal falling edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x400U) -#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (10U) -#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) -#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) - -/* - * REDG2PEN (RW) - * - * 1- The selected input signal rising edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_REDG2PEN_MASK (0x200U) -#define TRGM_TRGOCFG_REDG2PEN_SHIFT (9U) -#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) -#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) - -/* - * TRIGOSEL (RW) - * - * This bitfield selects one of the TRGM inputs as output. - */ -#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x7FU) -#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) -#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) -#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) - -/* Bitfield definition for register array: DMACFG */ -/* - * DMAMUX_EN (RW) - * - */ -#define TRGM_DMACFG_DMAMUX_EN_MASK (0x80000000UL) -#define TRGM_DMACFG_DMAMUX_EN_SHIFT (31U) -#define TRGM_DMACFG_DMAMUX_EN_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK) -#define TRGM_DMACFG_DMAMUX_EN_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT) - -/* - * DMASRCSEL (RW) - * - * This field selects one of the DMA requests as the DMA request output. - */ -#define TRGM_DMACFG_DMASRCSEL_MASK (0x3FU) -#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) -#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) -#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * TRGOPEN (RW) - * - * The bitfield enable the TRGM outputs. - */ -#define TRGM_GCR_TRGOPEN_MASK (0xFFU) -#define TRGM_GCR_TRGOPEN_SHIFT (0U) -#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) -#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) - -/* Bitfield definition for register: ADC_MATRIX_SEL */ -/* - * QEI1_ADC1_SEL (RW) - * - * 0-adc0; 1-adc1; 2-rdc_adc0; 3-rdc_adc1; - * bit7 is used to invert adc_value; - * others reserved - */ -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK (0xFF000000UL) -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT (24U) -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI1_ADC1_SEL_SHIFT) - -/* - * QEI1_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK (0xFF0000UL) -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT (16U) -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI1_ADC0_SEL_SHIFT) - -/* - * QEI0_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK (0xFF00U) -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT (8U) -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI0_ADC1_SEL_SHIFT) - -/* - * QEI0_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK (0xFFU) -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT (0U) -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL_QEI0_ADC0_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL */ -/* - * DAC1_DAC_SEL (RW) - * - * 0-qeo0_dac0; 1-qeo0_dac1; 2-qeo0_dac2; - * 3-qeo1_dac0; 4-qeo1_dac1; 5-qeo1_dac2; - * 6-rdc_dac0; 7-rdc_dac1; - * bit7 is used to invert dac_value; - * others reserved - */ -#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_DAC1_DAC_SEL_SHIFT) - -/* - * DAC0_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_DAC0_DAC_SEL_SHIFT) - -/* - * ACMP1_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_ACMP1_DAC_SEL_SHIFT) - -/* - * ACMP0_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL_ACMP0_DAC_SEL_SHIFT) - -/* Bitfield definition for register: POS_MATRIX_SEL0 */ -/* - * MMC1_POSIN_SEL (RW) - * - * 0-sei_pos_out0; 1-sei_pos_out1; - * 2-qei0_pos; 3-qei1_pos; - * 4-mmc0_pos_out0; 5-mmc0_pos_out1; - * 6-mmc1_pos_out0; 7-mmc1_pos_out1; - * bit7 is used to invert position value; - * others reserved - */ -#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK (0xFF000000UL) -#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT (24U) -#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MMC1_POSIN_SEL_SHIFT) - -/* - * MMC0_POSIN_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK (0xFF0000UL) -#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT (16U) -#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_MMC0_POSIN_SEL_SHIFT) - -/* - * SEI_POSIN1_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK (0xFF00U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT (8U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) - -/* - * SEI_POSIN0_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK (0xFFU) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT (0U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) - -/* Bitfield definition for register: POS_MATRIX_SEL1 */ -/* - * QEO1_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK (0xFF00U) -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT (8U) -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) - -/* - * QEO0_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK (0xFFU) -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT (0U) -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) - -/* Bitfield definition for register array: TRGM_IN */ -/* - * TRGM_IN (RO) - * - * mmc1_trig_out[1:0], mmc0_trig_out[1:0],sync_pulse[3:0],moto_gpio_in_sync[7:0],//31:16 - * gtmr3_to_motor_sync[1:0],gtmr2_to_motor_sync[1:0],gtmr1_to_motor_sync[1:0],gtmr0_to_motor_sync[1:0], //15:8 - * acmp_out_sync[1:0],can2mot_event_sync[1:0],usb0_sof_tog_sync,pwm_debug,1'b1,1'b0 //7:0 - */ -#define TRGM_TRGM_IN_TRGM_IN_MASK (0xFFFFFFFFUL) -#define TRGM_TRGM_IN_TRGM_IN_SHIFT (0U) -#define TRGM_TRGM_IN_TRGM_IN_GET(x) (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT) - -/* Bitfield definition for register array: TRGM_OUT */ -/* - * TRGM_OUT (RO) - * - * motor_to_opamp0[7:0] = trig_mux_out[7:0]; - * motor_to_opamp1[7:0] = trig_mux_out[15:8]; - * motor_to_gtmr0_capt[1:0] = trig_mux_out[17:16]; - * motor_to_gtmr0_sync = trig_mux_out[18]; - * motor_to_gtmr1_capt[1:0] = trig_mux_out[20:19]; - * motor_to_gtmr1_sync = trig_mux_out[21]; - * motor_to_gtmr2_capt[1:0] = trig_mux_out[23:22]; - * motor_to_gtmr2_sync = trig_mux_out[24]; - * motor_to_gtmr3_capt[1:0] = trig_mux_out[26:25]; - * motor_to_gtmr3_sync = trig_mux_out[27]; - * acmp_window[1:0] = trig_mux_out[29:28]; - * dac0_buf_trigger = trig_mux_out[30]; - * dac1_buf_trigger = trig_mux_out[31]; - * dac0_step_trigger[3:0] = {trig_mux_out[24:22],trig_mux_out[30]};//use same buf_trig, and gtmr2 - * dac1_step_trigger[3:0] = {trig_mux_out[27:25],trig_mux_out[31]}; //use same buf_trig, and gtmr3 - */ -#define TRGM_TRGM_OUT_TRGM_OUT_MASK (0xFFFFFFFFUL) -#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT (0U) -#define TRGM_TRGM_OUT_TRGM_OUT_GET(x) (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT) - - - -/* FILTCFG register group index macro definition */ -#define TRGM_FILTCFG_PWM0_IN0 (0UL) -#define TRGM_FILTCFG_PWM0_IN1 (1UL) -#define TRGM_FILTCFG_PWM0_IN2 (2UL) -#define TRGM_FILTCFG_PWM0_IN3 (3UL) -#define TRGM_FILTCFG_PWM0_IN4 (4UL) -#define TRGM_FILTCFG_PWM0_IN5 (5UL) -#define TRGM_FILTCFG_PWM0_IN6 (6UL) -#define TRGM_FILTCFG_PWM0_IN7 (7UL) -#define TRGM_FILTCFG_PWM1_IN0 (8UL) -#define TRGM_FILTCFG_PWM1_IN1 (9UL) -#define TRGM_FILTCFG_PWM1_IN2 (10UL) -#define TRGM_FILTCFG_PWM1_IN3 (11UL) -#define TRGM_FILTCFG_PWM1_IN4 (12UL) -#define TRGM_FILTCFG_PWM1_IN5 (13UL) -#define TRGM_FILTCFG_PWM1_IN6 (14UL) -#define TRGM_FILTCFG_PWM1_IN7 (15UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN0 (16UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN1 (17UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN2 (18UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN3 (19UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN4 (20UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN5 (21UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN6 (22UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN7 (23UL) -#define TRGM_FILTCFG_PWM0_FAULT0 (24UL) -#define TRGM_FILTCFG_PWM0_FAULT1 (25UL) -#define TRGM_FILTCFG_PWM1_FAULT0 (26UL) -#define TRGM_FILTCFG_PWM1_FAULT1 (27UL) - -/* TRGOCFG register group index macro definition */ -#define TRGM_TRGOCFG_MOT2OPAMP0_0 (0UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_1 (1UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_2 (2UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_3 (3UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_4 (4UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_5 (5UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_6 (6UL) -#define TRGM_TRGOCFG_MOT2OPAMP0_7 (7UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_0 (8UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_1 (9UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_2 (10UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_3 (11UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_4 (12UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_5 (13UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_6 (14UL) -#define TRGM_TRGOCFG_MOT2OPAMP1_7 (15UL) -#define TRGM_TRGOCFG_GPTMR0_IN2 (16UL) -#define TRGM_TRGOCFG_GPTMR0_IN3 (17UL) -#define TRGM_TRGOCFG_GPTMR0_SYNCI (18UL) -#define TRGM_TRGOCFG_GPTMR1_IN2 (19UL) -#define TRGM_TRGOCFG_GPTMR1_IN3 (20UL) -#define TRGM_TRGOCFG_GPTMR1_SYNCI (21UL) -#define TRGM_TRGOCFG_GPTMR2_IN2 (22UL) -#define TRGM_TRGOCFG_GPTMR2_IN3 (23UL) -#define TRGM_TRGOCFG_GPTMR2_SYNCI (24UL) -#define TRGM_TRGOCFG_GPTMR3_IN2 (25UL) -#define TRGM_TRGOCFG_GPTMR3_IN3 (26UL) -#define TRGM_TRGOCFG_GPTMR3_SYNCI (27UL) -#define TRGM_TRGOCFG_CMP0_WIN (28UL) -#define TRGM_TRGOCFG_CMP1_WIN (29UL) -#define TRGM_TRGOCFG_DAC0_BUFTRG (30UL) -#define TRGM_TRGOCFG_DAC1_BUFTRG (31UL) -#define TRGM_TRGOCFG_ADC0_STRGI (32UL) -#define TRGM_TRGOCFG_ADC1_STRGI (33UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0A (34UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0B (35UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0C (36UL) -#define TRGM_TRGOCFG_ADCX_PTRGI1A (37UL) -#define TRGM_TRGOCFG_ADCX_PTRGI1B (38UL) -#define TRGM_TRGOCFG_ADCX_PTRGI1C (39UL) -#define TRGM_TRGOCFG_ADCX_PTRGI2A (40UL) -#define TRGM_TRGOCFG_ADCX_PTRGI2B (41UL) -#define TRGM_TRGOCFG_ADCX_PTRGI2C (42UL) -#define TRGM_TRGOCFG_ADCX_PTRGI3A (43UL) -#define TRGM_TRGOCFG_ADCX_PTRGI3B (44UL) -#define TRGM_TRGOCFG_ADCX_PTRGI3C (45UL) -#define TRGM_TRGOCFG_CAN_PTPC0_CAP (46UL) -#define TRGM_TRGOCFG_CAN_PTPC1_CAP (47UL) -#define TRGM_TRGOCFG_QEO0_TRIG_IN0 (48UL) -#define TRGM_TRGOCFG_QEO0_TRIG_IN1 (49UL) -#define TRGM_TRGOCFG_QEO1_TRIG_IN0 (50UL) -#define TRGM_TRGOCFG_QEO1_TRIG_IN1 (51UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN0 (52UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN1 (53UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN2 (54UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN3 (55UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN4 (56UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN5 (57UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN6 (58UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN7 (59UL) -#define TRGM_TRGOCFG_MMC0_TRIG_IN0 (60UL) -#define TRGM_TRGOCFG_MMC0_TRIG_IN1 (61UL) -#define TRGM_TRGOCFG_MMC1_TRIG_IN0 (62UL) -#define TRGM_TRGOCFG_MMC1_TRIG_IN1 (63UL) -#define TRGM_TRGOCFG_PLB_IN_00 (64UL) -#define TRGM_TRGOCFG_PLB_IN_01 (65UL) -#define TRGM_TRGOCFG_PLB_IN_02 (66UL) -#define TRGM_TRGOCFG_PLB_IN_03 (67UL) -#define TRGM_TRGOCFG_PLB_IN_04 (68UL) -#define TRGM_TRGOCFG_PLB_IN_05 (69UL) -#define TRGM_TRGOCFG_PLB_IN_06 (70UL) -#define TRGM_TRGOCFG_PLB_IN_07 (71UL) -#define TRGM_TRGOCFG_PLB_IN_08 (72UL) -#define TRGM_TRGOCFG_PLB_IN_09 (73UL) -#define TRGM_TRGOCFG_PLB_IN_10 (74UL) -#define TRGM_TRGOCFG_PLB_IN_11 (75UL) -#define TRGM_TRGOCFG_PLB_IN_12 (76UL) -#define TRGM_TRGOCFG_PLB_IN_13 (77UL) -#define TRGM_TRGOCFG_PLB_IN_14 (78UL) -#define TRGM_TRGOCFG_PLB_IN_15 (79UL) -#define TRGM_TRGOCFG_PLB_IN_16 (80UL) -#define TRGM_TRGOCFG_PLB_IN_17 (81UL) -#define TRGM_TRGOCFG_PLB_IN_18 (82UL) -#define TRGM_TRGOCFG_PLB_IN_19 (83UL) -#define TRGM_TRGOCFG_PLB_IN_20 (84UL) -#define TRGM_TRGOCFG_PLB_IN_21 (85UL) -#define TRGM_TRGOCFG_PLB_IN_22 (86UL) -#define TRGM_TRGOCFG_PLB_IN_23 (87UL) -#define TRGM_TRGOCFG_PLB_IN_24 (88UL) -#define TRGM_TRGOCFG_PLB_IN_25 (89UL) -#define TRGM_TRGOCFG_PLB_IN_26 (90UL) -#define TRGM_TRGOCFG_PLB_IN_27 (91UL) -#define TRGM_TRGOCFG_PLB_IN_28 (92UL) -#define TRGM_TRGOCFG_PLB_IN_29 (93UL) -#define TRGM_TRGOCFG_PLB_IN_30 (94UL) -#define TRGM_TRGOCFG_PLB_IN_31 (95UL) -#define TRGM_TRGOCFG_MOT_GPIO0 (96UL) -#define TRGM_TRGOCFG_MOT_GPIO1 (97UL) -#define TRGM_TRGOCFG_MOT_GPIO2 (98UL) -#define TRGM_TRGOCFG_MOT_GPIO3 (99UL) -#define TRGM_TRGOCFG_MOT_GPIO4 (100UL) -#define TRGM_TRGOCFG_MOT_GPIO5 (101UL) -#define TRGM_TRGOCFG_MOT_GPIO6 (102UL) -#define TRGM_TRGOCFG_MOT_GPIO7 (103UL) -#define TRGM_TRGOCFG_PWM_IN8 (104UL) -#define TRGM_TRGOCFG_PWM_IN9 (105UL) -#define TRGM_TRGOCFG_PWM_IN10 (106UL) -#define TRGM_TRGOCFG_PWM_IN11 (107UL) -#define TRGM_TRGOCFG_PWM_IN12 (108UL) -#define TRGM_TRGOCFG_PWM_IN13 (109UL) -#define TRGM_TRGOCFG_PWM_IN14 (110UL) -#define TRGM_TRGOCFG_PWM_IN15 (111UL) -#define TRGM_TRGOCFG_PWM0_FRCI (112UL) -#define TRGM_TRGOCFG_PWM0_FRCSYNCI (113UL) -#define TRGM_TRGOCFG_PWM0_SYNCI (114UL) -#define TRGM_TRGOCFG_PWM0_SHRLDSYNCI (115UL) -#define TRGM_TRGOCFG_PWM0_FAULTI0 (116UL) -#define TRGM_TRGOCFG_PWM0_FAULTI1 (117UL) -#define TRGM_TRGOCFG_PWM1_FRCI (118UL) -#define TRGM_TRGOCFG_PWM1_FRCSYNCI (119UL) -#define TRGM_TRGOCFG_PWM1_SYNCI (120UL) -#define TRGM_TRGOCFG_PWM1_SHRLDSYNCI (121UL) -#define TRGM_TRGOCFG_PWM1_FAULTI0 (122UL) -#define TRGM_TRGOCFG_PWM1_FAULTI1 (123UL) -#define TRGM_TRGOCFG_RDC_TRIG_IN0 (124UL) -#define TRGM_TRGOCFG_RDC_TRIG_IN1 (125UL) -#define TRGM_TRGOCFG_SYNCTIMER_TRIG (126UL) -#define TRGM_TRGOCFG_QEI0_TRIG_IN (127UL) -#define TRGM_TRGOCFG_QEI1_TRIG_IN (128UL) -#define TRGM_TRGOCFG_QEI0_PAUSE (129UL) -#define TRGM_TRGOCFG_QEI1_PAUSE (130UL) -#define TRGM_TRGOCFG_UART_TRIG0 (131UL) -#define TRGM_TRGOCFG_UART_TRIG1 (132UL) -#define TRGM_TRGOCFG_TRGM_IRQ0 (133UL) -#define TRGM_TRGOCFG_TRGM_IRQ1 (134UL) -#define TRGM_TRGOCFG_TRGM_DMA0 (135UL) -#define TRGM_TRGOCFG_TRGM_DMA1 (136UL) - -/* DMACFG register group index macro definition */ -#define TRGM_DMACFG_0 (0UL) -#define TRGM_DMACFG_1 (1UL) -#define TRGM_DMACFG_2 (2UL) -#define TRGM_DMACFG_3 (3UL) -#define TRGM_DMACFG_4 (4UL) -#define TRGM_DMACFG_5 (5UL) -#define TRGM_DMACFG_6 (6UL) -#define TRGM_DMACFG_7 (7UL) - -/* TRGM_IN register group index macro definition */ -#define TRGM_TRGM_IN_0 (0UL) -#define TRGM_TRGM_IN_1 (1UL) -#define TRGM_TRGM_IN_2 (2UL) -#define TRGM_TRGM_IN_3 (3UL) - -/* TRGM_OUT register group index macro definition */ -#define TRGM_TRGM_OUT_0 (0UL) -#define TRGM_TRGM_OUT_1 (1UL) -#define TRGM_TRGM_OUT_2 (2UL) -#define TRGM_TRGM_OUT_3 (3UL) -#define TRGM_TRGM_OUT_4 (4UL) - - -#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_tsns_regs.h deleted file mode 100644 index fcaf224c309..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_tsns_regs.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSNS_H -#define HPM_TSNS_H - -typedef struct { - __R uint32_t T; /* 0x0: Temperature */ - __R uint32_t TMAX; /* 0x4: Maximum Temperature */ - __R uint32_t TMIN; /* 0x8: Minimum Temperature */ - __R uint32_t AGE; /* 0xC: Sample age */ - __RW uint32_t STATUS; /* 0x10: Status */ - __RW uint32_t CONFIG; /* 0x14: Configuration */ - __RW uint32_t VALIDITY; /* 0x18: Sample validity */ - __RW uint32_t FLAG; /* 0x1C: Temperature flag */ - __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ - __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ - __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ - __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ - __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __RW uint32_t ADVAN; /* 0x38: Advance configuration */ -} TSNS_Type; - - -/* Bitfield definition for register: T */ -/* - * T (RO) - * - * Signed number of temperature in 256 x celsius degree - */ -#define TSNS_T_T_MASK (0xFFFFFFFFUL) -#define TSNS_T_T_SHIFT (0U) -#define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) - -/* Bitfield definition for register: TMAX */ -/* - * T (RO) - * - * maximum temperature ever found - */ -#define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMAX_T_SHIFT (0U) -#define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) - -/* Bitfield definition for register: TMIN */ -/* - * T (RO) - * - * minimum temperature ever found - */ -#define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMIN_T_SHIFT (0U) -#define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) - -/* Bitfield definition for register: AGE */ -/* - * AGE (RO) - * - * age of T register in 24MHz clock cycles - */ -#define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) -#define TSNS_AGE_AGE_SHIFT (0U) -#define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * VALID (RO) - * - * indicate value in T is valid or not - * 0: not valid - * 1:valid - */ -#define TSNS_STATUS_VALID_MASK (0x80000000UL) -#define TSNS_STATUS_VALID_SHIFT (31U) -#define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) - -/* - * TRIGGER (W1C) - * - * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - */ -#define TSNS_STATUS_TRIGGER_MASK (0x1U) -#define TSNS_STATUS_TRIGGER_SHIFT (0U) -#define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) -#define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * IRQ_EN (RW) - * - * Enable interrupt - */ -#define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) -#define TSNS_CONFIG_IRQ_EN_SHIFT (31U) -#define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) -#define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) - -/* - * RST_EN (RW) - * - * Enable reset - */ -#define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) -#define TSNS_CONFIG_RST_EN_SHIFT (30U) -#define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) -#define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) - -/* - * COMPARE_MIN_EN (RW) - * - * Enable compare for minimum temperature - */ -#define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) -#define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) -#define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) -#define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) - -/* - * COMPARE_MAX_EN (RW) - * - * Enable compare for maximum temperature - */ -#define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) -#define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) -#define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) -#define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) - -/* - * SPEED (RW) - * - * cycles of a progressive step in 24M clock, valid from 24-255, default 96 - * 24: 24 cycle for a step - * 25: 25 cycle for a step - * 26: 26 cycle for a step - * ... - * 255: 255 cycle for a step - */ -#define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) -#define TSNS_CONFIG_SPEED_SHIFT (16U) -#define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) -#define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) - -/* - * AVERAGE (RW) - * - * Average time, default in 3 - * 0: measure and return - * 1: twice and average - * 2: 4 times and average - * . . . - * 7: 128 times and average - */ -#define TSNS_CONFIG_AVERAGE_MASK (0x700U) -#define TSNS_CONFIG_AVERAGE_SHIFT (8U) -#define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) -#define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) - -/* - * CONTINUOUS (RW) - * - * continuous mode that keep sampling temperature peridically - * 0: trigger mode - * 1: continuous mode - */ -#define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) -#define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) -#define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) -#define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) - -/* - * ASYNC (RW) - * - * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value - * 0: active mode - * 1: Async mode - */ -#define TSNS_CONFIG_ASYNC_MASK (0x2U) -#define TSNS_CONFIG_ASYNC_SHIFT (1U) -#define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) -#define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) - -/* - * ENABLE (RW) - * - * Enable temperature - * 0: disable, temperature sensor is shut down - * 1: enable. Temperature sensor enabled - */ -#define TSNS_CONFIG_ENABLE_MASK (0x1U) -#define TSNS_CONFIG_ENABLE_SHIFT (0U) -#define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) -#define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) - -/* Bitfield definition for register: VALIDITY */ -/* - * VALIDITY (RW) - * - * time for temperature values to expire in 24M clock cycles - */ -#define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) -#define TSNS_VALIDITY_VALIDITY_SHIFT (0U) -#define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) -#define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) - -/* Bitfield definition for register: FLAG */ -/* - * RECORD_MIN_CLR (RW) - * - * Clear minimum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) -#define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) -#define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) -#define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) - -/* - * RECORD_MAX_CLR (RW) - * - * Clear maximum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) -#define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) -#define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) -#define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) - -/* - * UNDER_TEMP (RW) - * - * Clear under temperature status, write 1 to clear - */ -#define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) -#define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) -#define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) -#define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) - -/* - * OVER_TEMP (RW) - * - * Clear over temperature status, write 1 to clear - */ -#define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) -#define TSNS_FLAG_OVER_TEMP_SHIFT (16U) -#define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) -#define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) - -/* - * IRQ (RW) - * - * IRQ flag, write 1 to clear - */ -#define TSNS_FLAG_IRQ_MASK (0x1U) -#define TSNS_FLAG_IRQ_SHIFT (0U) -#define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) -#define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_IRQ */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) -#define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_IRQ */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) -#define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_RST */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_RST_T_SHIFT (0U) -#define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) -#define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_RST */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_RST_T_SHIFT (0U) -#define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) -#define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: ASYNC */ -/* - * ASYNC_TYPE (RW) - * - * Compare hotter than or colder than in asynchoronous mode - * 0: hotter than - * 1: colder than - */ -#define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) -#define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) -#define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) -#define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) - -/* - * POLARITY (RW) - * - * Polarity of internal comparator - */ -#define TSNS_ASYNC_POLARITY_MASK (0x10000UL) -#define TSNS_ASYNC_POLARITY_SHIFT (16U) -#define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) -#define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) - -/* - * VALUE (RW) - * - * Value of async mode to compare - */ -#define TSNS_ASYNC_VALUE_MASK (0x7FFU) -#define TSNS_ASYNC_VALUE_SHIFT (0U) -#define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) -#define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) - -/* Bitfield definition for register: ADVAN */ -/* - * ASYNC_IRQ (RO) - * - * interrupt status of asynchronous mode - */ -#define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) -#define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) -#define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) - -/* - * ACTIVE_IRQ (RO) - * - * interrupt status of active mode - */ -#define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) -#define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) -#define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) - -/* - * SAMPLING (RO) - * - * temperature sampling is working - */ -#define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) -#define TSNS_ADVAN_SAMPLING_SHIFT (16U) -#define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) - -/* - * NEG_ONLY (RW) - * - * use negative compare polarity only - */ -#define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) -#define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) -#define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) -#define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) - -/* - * POS_ONLY (RW) - * - * use positive compare polarity only - */ -#define TSNS_ADVAN_POS_ONLY_MASK (0x1U) -#define TSNS_ADVAN_POS_ONLY_SHIFT (0U) -#define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) -#define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) - - - - -#endif /* HPM_TSNS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_uart_regs.h deleted file mode 100644 index c64a4ba9f69..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_uart_regs.h +++ /dev/null @@ -1,1044 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_UART_H -#define HPM_UART_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t IDLE_CFG; /* 0x4: Idle Configuration Register */ - __RW uint32_t ADDR_CFG; /* 0x8: address match config register */ - __RW uint32_t IIR2; /* 0xC: Interrupt Identification Register2 */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __RW uint32_t FCRR; /* 0x18: FIFO Control Register config */ - __RW uint32_t MOTO_CFG; /* 0x1C: moto system control register */ - union { - __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ - __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ - __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ - __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ - __W uint32_t FCR; /* 0x28: FIFO Control Register */ - }; - __RW uint32_t LCR; /* 0x2C: Line Control Register */ - __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ - __R uint32_t LSR; /* 0x34: Line Status Register */ - __R uint32_t MSR; /* 0x38: Modem Status Register */ - __RW uint32_t GPR; /* 0x3C: GPR Register */ -} UART_Type; - - -/* Bitfield definition for register: IDLE_CFG */ -/* - * TX_IDLE_COND (RW) - * - * IDLE Detection Condition - * 0 - Treat as idle if TX pin is logic one - * 1 - Treat as idle if UART state machine state is idle - */ -#define UART_IDLE_CFG_TX_IDLE_COND_MASK (0x2000000UL) -#define UART_IDLE_CFG_TX_IDLE_COND_SHIFT (25U) -#define UART_IDLE_CFG_TX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_COND_SHIFT) & UART_IDLE_CFG_TX_IDLE_COND_MASK) -#define UART_IDLE_CFG_TX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_COND_MASK) >> UART_IDLE_CFG_TX_IDLE_COND_SHIFT) - -/* - * TX_IDLE_EN (RW) - * - * UART TX Idle Detect Enable - * 0 - Disable - * 1 - Enable - */ -#define UART_IDLE_CFG_TX_IDLE_EN_MASK (0x1000000UL) -#define UART_IDLE_CFG_TX_IDLE_EN_SHIFT (24U) -#define UART_IDLE_CFG_TX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_EN_SHIFT) & UART_IDLE_CFG_TX_IDLE_EN_MASK) -#define UART_IDLE_CFG_TX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_EN_MASK) >> UART_IDLE_CFG_TX_IDLE_EN_SHIFT) - -/* - * TX_IDLE_THR (RW) - * - * Threshold for UART transmit Idle detection (in terms of bits) - */ -#define UART_IDLE_CFG_TX_IDLE_THR_MASK (0xFF0000UL) -#define UART_IDLE_CFG_TX_IDLE_THR_SHIFT (16U) -#define UART_IDLE_CFG_TX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_THR_SHIFT) & UART_IDLE_CFG_TX_IDLE_THR_MASK) -#define UART_IDLE_CFG_TX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_THR_MASK) >> UART_IDLE_CFG_TX_IDLE_THR_SHIFT) - -/* - * RXEN (RW) - * - * UART receive enable. - * 0 - hold RX input to high, avoide wrong data input when config pinmux - * 1 - bypass RX input from PIN - * software should set it after config pinmux - */ -#define UART_IDLE_CFG_RXEN_MASK (0x800U) -#define UART_IDLE_CFG_RXEN_SHIFT (11U) -#define UART_IDLE_CFG_RXEN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RXEN_SHIFT) & UART_IDLE_CFG_RXEN_MASK) -#define UART_IDLE_CFG_RXEN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RXEN_MASK) >> UART_IDLE_CFG_RXEN_SHIFT) - -/* - * RX_IDLE_COND (RW) - * - * IDLE Detection Condition - * 0 - Treat as idle if RX pin is logic one - * 1 - Treat as idle if UART state machine state is idle - */ -#define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x200U) -#define UART_IDLE_CFG_RX_IDLE_COND_SHIFT (9U) -#define UART_IDLE_CFG_RX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_COND_SHIFT) & UART_IDLE_CFG_RX_IDLE_COND_MASK) -#define UART_IDLE_CFG_RX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_COND_MASK) >> UART_IDLE_CFG_RX_IDLE_COND_SHIFT) - -/* - * RX_IDLE_EN (RW) - * - * UART Idle Detect Enable - * 0 - Disable - * 1 - Enable - * it should be enabled if enable address match feature - */ -#define UART_IDLE_CFG_RX_IDLE_EN_MASK (0x100U) -#define UART_IDLE_CFG_RX_IDLE_EN_SHIFT (8U) -#define UART_IDLE_CFG_RX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_EN_SHIFT) & UART_IDLE_CFG_RX_IDLE_EN_MASK) -#define UART_IDLE_CFG_RX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_EN_MASK) >> UART_IDLE_CFG_RX_IDLE_EN_SHIFT) - -/* - * RX_IDLE_THR (RW) - * - * Threshold for UART Receive Idle detection (in terms of bits) - */ -#define UART_IDLE_CFG_RX_IDLE_THR_MASK (0xFFU) -#define UART_IDLE_CFG_RX_IDLE_THR_SHIFT (0U) -#define UART_IDLE_CFG_RX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_THR_SHIFT) & UART_IDLE_CFG_RX_IDLE_THR_MASK) -#define UART_IDLE_CFG_RX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_THR_MASK) >> UART_IDLE_CFG_RX_IDLE_THR_SHIFT) - -/* Bitfield definition for register: ADDR_CFG */ -/* - * TXEN_9BIT (RW) - * - * set to use 9bit mode for transmitter, - * will set the MSB for the first character as address flag, keep 0 for others. - */ -#define UART_ADDR_CFG_TXEN_9BIT_MASK (0x100000UL) -#define UART_ADDR_CFG_TXEN_9BIT_SHIFT (20U) -#define UART_ADDR_CFG_TXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_TXEN_9BIT_SHIFT) & UART_ADDR_CFG_TXEN_9BIT_MASK) -#define UART_ADDR_CFG_TXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_TXEN_9BIT_MASK) >> UART_ADDR_CFG_TXEN_9BIT_SHIFT) - -/* - * RXEN_ADDR_MSB (RW) - * - * set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). - * Clr to use first character as address. - * Only needed if enable address match feature - */ -#define UART_ADDR_CFG_RXEN_ADDR_MSB_MASK (0x80000UL) -#define UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT (19U) -#define UART_ADDR_CFG_RXEN_ADDR_MSB_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) -#define UART_ADDR_CFG_RXEN_ADDR_MSB_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) >> UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) - -/* - * RXEN_9BIT (RW) - * - * set to use 9bit mode for receiver, only valid if rxen_addr_msb is set - */ -#define UART_ADDR_CFG_RXEN_9BIT_MASK (0x40000UL) -#define UART_ADDR_CFG_RXEN_9BIT_SHIFT (18U) -#define UART_ADDR_CFG_RXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_9BIT_SHIFT) & UART_ADDR_CFG_RXEN_9BIT_MASK) -#define UART_ADDR_CFG_RXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_9BIT_MASK) >> UART_ADDR_CFG_RXEN_9BIT_SHIFT) - -/* - * A1_EN (RW) - * - * enable addr1 compare for the first character. - * If a1_en OR a0_en, then do not receive data if address not match. - * If ~a1_en AND ~a0_en, the receive all data like before. - * NOTE: should set idle_tmout_en if enable address match feature - */ -#define UART_ADDR_CFG_A1_EN_MASK (0x20000UL) -#define UART_ADDR_CFG_A1_EN_SHIFT (17U) -#define UART_ADDR_CFG_A1_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A1_EN_SHIFT) & UART_ADDR_CFG_A1_EN_MASK) -#define UART_ADDR_CFG_A1_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A1_EN_MASK) >> UART_ADDR_CFG_A1_EN_SHIFT) - -/* - * A0_EN (RW) - * - * enable addr0 compare for the first character - */ -#define UART_ADDR_CFG_A0_EN_MASK (0x10000UL) -#define UART_ADDR_CFG_A0_EN_SHIFT (16U) -#define UART_ADDR_CFG_A0_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A0_EN_SHIFT) & UART_ADDR_CFG_A0_EN_MASK) -#define UART_ADDR_CFG_A0_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A0_EN_MASK) >> UART_ADDR_CFG_A0_EN_SHIFT) - -/* - * ADDR1 (RW) - * - * address 1 fileld. - * in 9bit mode, this is the full address byte. - * For other mode(8/7/6/5bit), MSB should be set for address flag. - * If want address==0 to be matched at 8bit mode, should set addr1=0x80 - */ -#define UART_ADDR_CFG_ADDR1_MASK (0xFF00U) -#define UART_ADDR_CFG_ADDR1_SHIFT (8U) -#define UART_ADDR_CFG_ADDR1_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR1_SHIFT) & UART_ADDR_CFG_ADDR1_MASK) -#define UART_ADDR_CFG_ADDR1_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR1_MASK) >> UART_ADDR_CFG_ADDR1_SHIFT) - -/* - * ADDR0 (RW) - * - * address 0 field. - */ -#define UART_ADDR_CFG_ADDR0_MASK (0xFFU) -#define UART_ADDR_CFG_ADDR0_SHIFT (0U) -#define UART_ADDR_CFG_ADDR0_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR0_SHIFT) & UART_ADDR_CFG_ADDR0_MASK) -#define UART_ADDR_CFG_ADDR0_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR0_MASK) >> UART_ADDR_CFG_ADDR0_SHIFT) - -/* Bitfield definition for register: IIR2 */ -/* - * RXIDLE_FLAG (W1C) - * - * UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear - * 0 - UART RX is busy - * 1 - UART RX is idle - */ -#define UART_IIR2_RXIDLE_FLAG_MASK (0x80000000UL) -#define UART_IIR2_RXIDLE_FLAG_SHIFT (31U) -#define UART_IIR2_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_RXIDLE_FLAG_SHIFT) & UART_IIR2_RXIDLE_FLAG_MASK) -#define UART_IIR2_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_RXIDLE_FLAG_MASK) >> UART_IIR2_RXIDLE_FLAG_SHIFT) - -/* - * TXIDLE_FLAG (W1C) - * - * UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear - * 0 - UART TX is busy - * 1 - UART TX is idle - */ -#define UART_IIR2_TXIDLE_FLAG_MASK (0x40000000UL) -#define UART_IIR2_TXIDLE_FLAG_SHIFT (30U) -#define UART_IIR2_TXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_TXIDLE_FLAG_SHIFT) & UART_IIR2_TXIDLE_FLAG_MASK) -#define UART_IIR2_TXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_TXIDLE_FLAG_MASK) >> UART_IIR2_TXIDLE_FLAG_SHIFT) - -/* - * ADDR_MATCH (W1C) - * - * address match irq status, assert if either address match(and enabled). Write one clear - * NOTE: the address byte may not moved by DMA at this point. - * User can wait next addr_match_idle irq for the whole data include address - */ -#define UART_IIR2_ADDR_MATCH_MASK (0x20000000UL) -#define UART_IIR2_ADDR_MATCH_SHIFT (29U) -#define UART_IIR2_ADDR_MATCH_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_SHIFT) & UART_IIR2_ADDR_MATCH_MASK) -#define UART_IIR2_ADDR_MATCH_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_MASK) >> UART_IIR2_ADDR_MATCH_SHIFT) - -/* - * ADDR_MATCH_IDLE (W1C) - * - * address match and idle irq status, assert at rx bus idle if address match event triggered. - * Write one clear; - */ -#define UART_IIR2_ADDR_MATCH_IDLE_MASK (0x10000000UL) -#define UART_IIR2_ADDR_MATCH_IDLE_SHIFT (28U) -#define UART_IIR2_ADDR_MATCH_IDLE_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_IDLE_SHIFT) & UART_IIR2_ADDR_MATCH_IDLE_MASK) -#define UART_IIR2_ADDR_MATCH_IDLE_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_IDLE_MASK) >> UART_IIR2_ADDR_MATCH_IDLE_SHIFT) - -/* - * DATA_LOST (W1C) - * - * assert if data lost before address match status, write one clear; - * It will not assert if no address match occurs - */ -#define UART_IIR2_DATA_LOST_MASK (0x8000000UL) -#define UART_IIR2_DATA_LOST_SHIFT (27U) -#define UART_IIR2_DATA_LOST_SET(x) (((uint32_t)(x) << UART_IIR2_DATA_LOST_SHIFT) & UART_IIR2_DATA_LOST_MASK) -#define UART_IIR2_DATA_LOST_GET(x) (((uint32_t)(x) & UART_IIR2_DATA_LOST_MASK) >> UART_IIR2_DATA_LOST_SHIFT) - -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR2_FIFOED_MASK (0xC0U) -#define UART_IIR2_FIFOED_SHIFT (6U) -#define UART_IIR2_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR2_FIFOED_MASK) >> UART_IIR2_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR2_INTRID_MASK (0xFU) -#define UART_IIR2_INTRID_SHIFT (0U) -#define UART_IIR2_INTRID_GET(x) (((uint32_t)(x) & UART_IIR2_INTRID_MASK) >> UART_IIR2_INTRID_SHIFT) - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * The depth of RXFIFO and TXFIFO - * 0: 16-byte FIFO - * 1: 32-byte FIFO - * 2: 64-byte FIFO - * 3: 128-byte FIFO - */ -#define UART_CFG_FIFOSIZE_MASK (0x3U) -#define UART_CFG_FIFOSIZE_SHIFT (0U) -#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: OSCR */ -/* - * OSC (RW) - * - * Over-sample control - * The value must be an even number; any odd value - * writes to this field will be converted to an even value. - * OSC=0: reserved - * OSC<=8: The over-sample ratio is 8 - * 8 < OSC< 32: The over sample ratio is OSC - */ -#define UART_OSCR_OSC_MASK (0x1FU) -#define UART_OSCR_OSC_SHIFT (0U) -#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) -#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) - -/* Bitfield definition for register: FCRR */ -/* - * FIFOT4EN (RW) - * - * set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) - * clr to use 2bit(TFIFOT and RFIFOT) - */ -#define UART_FCRR_FIFOT4EN_MASK (0x800000UL) -#define UART_FCRR_FIFOT4EN_SHIFT (23U) -#define UART_FCRR_FIFOT4EN_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOT4EN_SHIFT) & UART_FCRR_FIFOT4EN_MASK) -#define UART_FCRR_FIFOT4EN_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOT4EN_MASK) >> UART_FCRR_FIFOT4EN_SHIFT) - -/* - * TFIFOT4 (RW) - * - * txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. - */ -#define UART_FCRR_TFIFOT4_MASK (0xF0000UL) -#define UART_FCRR_TFIFOT4_SHIFT (16U) -#define UART_FCRR_TFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT4_SHIFT) & UART_FCRR_TFIFOT4_MASK) -#define UART_FCRR_TFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT4_MASK) >> UART_FCRR_TFIFOT4_SHIFT) - -/* - * RFIFOT4 (RW) - * - * rxfifo threshold(0 for 1byte, 0xF for 16bytes). - * Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled - */ -#define UART_FCRR_RFIFOT4_MASK (0xF00U) -#define UART_FCRR_RFIFOT4_SHIFT (8U) -#define UART_FCRR_RFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT4_SHIFT) & UART_FCRR_RFIFOT4_MASK) -#define UART_FCRR_RFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT4_MASK) >> UART_FCRR_RFIFOT4_SHIFT) - -/* - * RFIFOT (RW) - * - * Receiver FIFO trigger level - */ -#define UART_FCRR_RFIFOT_MASK (0xC0U) -#define UART_FCRR_RFIFOT_SHIFT (6U) -#define UART_FCRR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT_SHIFT) & UART_FCRR_RFIFOT_MASK) -#define UART_FCRR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT_MASK) >> UART_FCRR_RFIFOT_SHIFT) - -/* - * TFIFOT (RW) - * - * Transmitter FIFO trigger level - */ -#define UART_FCRR_TFIFOT_MASK (0x30U) -#define UART_FCRR_TFIFOT_SHIFT (4U) -#define UART_FCRR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT_SHIFT) & UART_FCRR_TFIFOT_MASK) -#define UART_FCRR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT_MASK) >> UART_FCRR_TFIFOT_SHIFT) - -/* - * DMAE (RW) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCRR_DMAE_MASK (0x8U) -#define UART_FCRR_DMAE_SHIFT (3U) -#define UART_FCRR_DMAE_SET(x) (((uint32_t)(x) << UART_FCRR_DMAE_SHIFT) & UART_FCRR_DMAE_MASK) -#define UART_FCRR_DMAE_GET(x) (((uint32_t)(x) & UART_FCRR_DMAE_MASK) >> UART_FCRR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCRR_TFIFORST_MASK (0x4U) -#define UART_FCRR_TFIFORST_SHIFT (2U) -#define UART_FCRR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFORST_SHIFT) & UART_FCRR_TFIFORST_MASK) -#define UART_FCRR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFORST_MASK) >> UART_FCRR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCRR_RFIFORST_MASK (0x2U) -#define UART_FCRR_RFIFORST_SHIFT (1U) -#define UART_FCRR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFORST_SHIFT) & UART_FCRR_RFIFORST_MASK) -#define UART_FCRR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFORST_MASK) >> UART_FCRR_RFIFORST_SHIFT) - -/* - * FIFOE (RW) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCRR_FIFOE_MASK (0x1U) -#define UART_FCRR_FIFOE_SHIFT (0U) -#define UART_FCRR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOE_SHIFT) & UART_FCRR_FIFOE_MASK) -#define UART_FCRR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOE_MASK) >> UART_FCRR_FIFOE_SHIFT) - -/* Bitfield definition for register: MOTO_CFG */ -/* - * SWTRG (WO) - * - * software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. - * Hardware auto reset. - */ -#define UART_MOTO_CFG_SWTRG_MASK (0x80000000UL) -#define UART_MOTO_CFG_SWTRG_SHIFT (31U) -#define UART_MOTO_CFG_SWTRG_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_SWTRG_SHIFT) & UART_MOTO_CFG_SWTRG_MASK) -#define UART_MOTO_CFG_SWTRG_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_SWTRG_MASK) >> UART_MOTO_CFG_SWTRG_SHIFT) - -/* - * TXSTP_BITS (RW) - * - * if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits - */ -#define UART_MOTO_CFG_TXSTP_BITS_MASK (0xFF00U) -#define UART_MOTO_CFG_TXSTP_BITS_SHIFT (8U) -#define UART_MOTO_CFG_TXSTP_BITS_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTP_BITS_SHIFT) & UART_MOTO_CFG_TXSTP_BITS_MASK) -#define UART_MOTO_CFG_TXSTP_BITS_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTP_BITS_MASK) >> UART_MOTO_CFG_TXSTP_BITS_SHIFT) - -/* - * HWTRG_EN (RW) - * - * set to enable hardware trigger(trigger from moto is shared by other UART) - */ -#define UART_MOTO_CFG_HWTRG_EN_MASK (0x80U) -#define UART_MOTO_CFG_HWTRG_EN_SHIFT (7U) -#define UART_MOTO_CFG_HWTRG_EN_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_HWTRG_EN_SHIFT) & UART_MOTO_CFG_HWTRG_EN_MASK) -#define UART_MOTO_CFG_HWTRG_EN_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_HWTRG_EN_MASK) >> UART_MOTO_CFG_HWTRG_EN_SHIFT) - -/* - * TRG_MODE (RW) - * - * set to enable trigger mode. - * software should push needed data into txbuffer frist, uart will not start transmission at this time. - * User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty - * NOTE: the hw_trigger should be pulse signal from trig mux. - */ -#define UART_MOTO_CFG_TRG_MODE_MASK (0x40U) -#define UART_MOTO_CFG_TRG_MODE_SHIFT (6U) -#define UART_MOTO_CFG_TRG_MODE_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_MODE_SHIFT) & UART_MOTO_CFG_TRG_MODE_MASK) -#define UART_MOTO_CFG_TRG_MODE_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_MODE_MASK) >> UART_MOTO_CFG_TRG_MODE_SHIFT) - -/* - * TRG_CLR_RFIFO (RW) - * - * set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. - */ -#define UART_MOTO_CFG_TRG_CLR_RFIFO_MASK (0x20U) -#define UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT (5U) -#define UART_MOTO_CFG_TRG_CLR_RFIFO_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) -#define UART_MOTO_CFG_TRG_CLR_RFIFO_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) >> UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) - -/* - * TXSTOP_INSERT (RW) - * - * set to insert STOP bits between each tx byte till tx fifo empty. - * NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set - */ -#define UART_MOTO_CFG_TXSTOP_INSERT_MASK (0x10U) -#define UART_MOTO_CFG_TXSTOP_INSERT_SHIFT (4U) -#define UART_MOTO_CFG_TXSTOP_INSERT_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) -#define UART_MOTO_CFG_TXSTOP_INSERT_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) >> UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RBR (RO) - * - * Receive data read port - */ -#define UART_RBR_RBR_MASK (0xFFU) -#define UART_RBR_RBR_SHIFT (0U) -#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) - -/* Bitfield definition for register: THR */ -/* - * THR (WO) - * - * Transmit data write port - */ -#define UART_THR_THR_MASK (0xFFU) -#define UART_THR_THR_SHIFT (0U) -#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) -#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) - -/* Bitfield definition for register: DLL */ -/* - * DLL (RW) - * - * Least significant byte of the Divisor Latch - */ -#define UART_DLL_DLL_MASK (0xFFU) -#define UART_DLL_DLL_SHIFT (0U) -#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) -#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) - -/* Bitfield definition for register: IER */ -/* - * ERXIDLE (RW) - * - * Enable Receive Idle interrupt - * 0 - Disable Idle interrupt - * 1 - Enable Idle interrupt - */ -#define UART_IER_ERXIDLE_MASK (0x80000000UL) -#define UART_IER_ERXIDLE_SHIFT (31U) -#define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) -#define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) - -/* - * ETXIDLE (RW) - * - * enable transmit idle interrupt - */ -#define UART_IER_ETXIDLE_MASK (0x40000000UL) -#define UART_IER_ETXIDLE_SHIFT (30U) -#define UART_IER_ETXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ETXIDLE_SHIFT) & UART_IER_ETXIDLE_MASK) -#define UART_IER_ETXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ETXIDLE_MASK) >> UART_IER_ETXIDLE_SHIFT) - -/* - * EADDRM (RW) - * - * enable ADDR_MATCH interrupt - */ -#define UART_IER_EADDRM_MASK (0x20000000UL) -#define UART_IER_EADDRM_SHIFT (29U) -#define UART_IER_EADDRM_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_SHIFT) & UART_IER_EADDRM_MASK) -#define UART_IER_EADDRM_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_MASK) >> UART_IER_EADDRM_SHIFT) - -/* - * EADDRM_IDLE (RW) - * - * enable ADDR_MATCH_IDLE interrupt - */ -#define UART_IER_EADDRM_IDLE_MASK (0x10000000UL) -#define UART_IER_EADDRM_IDLE_SHIFT (28U) -#define UART_IER_EADDRM_IDLE_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_IDLE_SHIFT) & UART_IER_EADDRM_IDLE_MASK) -#define UART_IER_EADDRM_IDLE_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_IDLE_MASK) >> UART_IER_EADDRM_IDLE_SHIFT) - -/* - * EDATLOST (RW) - * - * enable DATA_LOST interrupt - */ -#define UART_IER_EDATLOST_MASK (0x8000000UL) -#define UART_IER_EDATLOST_SHIFT (27U) -#define UART_IER_EDATLOST_SET(x) (((uint32_t)(x) << UART_IER_EDATLOST_SHIFT) & UART_IER_EDATLOST_MASK) -#define UART_IER_EDATLOST_GET(x) (((uint32_t)(x) & UART_IER_EDATLOST_MASK) >> UART_IER_EDATLOST_SHIFT) - -/* - * EMSI (RW) - * - * Enable modem status interrupt - * The interrupt asserts when the status of one of the - * following occurs: - * The status of modem_rin, modem_dcdn, - * modem_dsrn or modem_ctsn (If the auto-cts mode is - * disabled) has been changed. - * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), - * modem_ctsn would be used to control the transmitter. - */ -#define UART_IER_EMSI_MASK (0x8U) -#define UART_IER_EMSI_SHIFT (3U) -#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) -#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) - -/* - * ELSI (RW) - * - * Enable receiver line status interrupt - */ -#define UART_IER_ELSI_MASK (0x4U) -#define UART_IER_ELSI_SHIFT (2U) -#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) -#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) - -/* - * ETHEI (RW) - * - * Enable transmitter holding register interrupt - */ -#define UART_IER_ETHEI_MASK (0x2U) -#define UART_IER_ETHEI_SHIFT (1U) -#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) -#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) - -/* - * ERBI (RW) - * - * Enable received data available interrupt and the - * character timeout interrupt - * 0: Disable - * 1: Enable - */ -#define UART_IER_ERBI_MASK (0x1U) -#define UART_IER_ERBI_SHIFT (0U) -#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) -#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) - -/* Bitfield definition for register: DLM */ -/* - * DLM (RW) - * - * Most significant byte of the Divisor Latch - */ -#define UART_DLM_DLM_MASK (0xFFU) -#define UART_DLM_DLM_SHIFT (0U) -#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) -#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) - -/* Bitfield definition for register: IIR */ -/* - * RXIDLE_FLAG (W1C) - * - * UART IDLE Flag - * 0 - UART is busy - * 1 - UART is idle - * NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - */ -#define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) -#define UART_IIR_RXIDLE_FLAG_SHIFT (31U) -#define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) -#define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) - -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR_FIFOED_MASK (0xC0U) -#define UART_IIR_FIFOED_SHIFT (6U) -#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR_INTRID_MASK (0xFU) -#define UART_IIR_INTRID_SHIFT (0U) -#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) - -/* Bitfield definition for register: FCR */ -/* - * RFIFOT (WO) - * - * Receiver FIFO trigger level - */ -#define UART_FCR_RFIFOT_MASK (0xC0U) -#define UART_FCR_RFIFOT_SHIFT (6U) -#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) -#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) - -/* - * TFIFOT (WO) - * - * Transmitter FIFO trigger level - */ -#define UART_FCR_TFIFOT_MASK (0x30U) -#define UART_FCR_TFIFOT_SHIFT (4U) -#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) -#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) - -/* - * DMAE (WO) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCR_DMAE_MASK (0x8U) -#define UART_FCR_DMAE_SHIFT (3U) -#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) -#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_TFIFORST_MASK (0x4U) -#define UART_FCR_TFIFORST_SHIFT (2U) -#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) -#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_RFIFORST_MASK (0x2U) -#define UART_FCR_RFIFORST_SHIFT (1U) -#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) -#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) - -/* - * FIFOE (WO) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCR_FIFOE_MASK (0x1U) -#define UART_FCR_FIFOE_SHIFT (0U) -#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) -#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) - -/* Bitfield definition for register: LCR */ -/* - * DLAB (RW) - * - * Divisor latch access bit - */ -#define UART_LCR_DLAB_MASK (0x80U) -#define UART_LCR_DLAB_SHIFT (7U) -#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) -#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) - -/* - * BC (RW) - * - * Break control - */ -#define UART_LCR_BC_MASK (0x40U) -#define UART_LCR_BC_SHIFT (6U) -#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) -#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) - -/* - * SPS (RW) - * - * Stick parity - * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). - * 0: Disable the sticky bit parity. - */ -#define UART_LCR_SPS_MASK (0x20U) -#define UART_LCR_SPS_SHIFT (5U) -#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) -#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) - -/* - * EPS (RW) - * - * Even parity select - * 1: Even parity (an even number of logic-1 is in the data - * and parity bits) - * 0: Old parity. - */ -#define UART_LCR_EPS_MASK (0x10U) -#define UART_LCR_EPS_SHIFT (4U) -#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) -#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) - -/* - * PEN (RW) - * - * Parity enable - * When this bit is set, a parity bit is generated in - * transmitted data before the first STOP bit and the parity - * bit would be checked for the received data. - */ -#define UART_LCR_PEN_MASK (0x8U) -#define UART_LCR_PEN_SHIFT (3U) -#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) -#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) - -/* - * STB (RW) - * - * Number of STOP bits - * 0: 1 bits - * 1: The number of STOP bit is based on the WLS setting - * When WLS = 0, STOP bit is 1.5 bits - * When WLS = 1, 2, 3, STOP bit is 2 bits - */ -#define UART_LCR_STB_MASK (0x4U) -#define UART_LCR_STB_SHIFT (2U) -#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) -#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) - -/* - * WLS (RW) - * - * Word length setting - * 0: 5 bits - * 1: 6 bits - * 2: 7 bits - * 3: 8 bits - */ -#define UART_LCR_WLS_MASK (0x3U) -#define UART_LCR_WLS_SHIFT (0U) -#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) -#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) - -/* Bitfield definition for register: MCR */ -/* - * AFE (RW) - * - * Auto flow control enable - * 0: Disable - * 1: The auto-CTS and auto-RTS setting is based on the - * RTS bit setting: - * When RTS = 0, auto-CTS only - * When RTS = 1, auto-CTS and auto-RTS - */ -#define UART_MCR_AFE_MASK (0x20U) -#define UART_MCR_AFE_SHIFT (5U) -#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) -#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) - -/* - * LOOP (RW) - * - * Enable loopback mode - * 0: Disable - * 1: Enable - */ -#define UART_MCR_LOOP_MASK (0x10U) -#define UART_MCR_LOOP_SHIFT (4U) -#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) -#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) - -/* - * RTS (RW) - * - * Request to send - * This bit controls the modem_rtsn output. - * 0: The modem_rtsn output signal will be driven HIGH - * 1: The modem_rtsn output signal will be driven LOW - */ -#define UART_MCR_RTS_MASK (0x2U) -#define UART_MCR_RTS_SHIFT (1U) -#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) -#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) - -/* Bitfield definition for register: LSR */ -/* - * RXIDLE (RO) - * - * rxidle after timeout, clear after rx idle condition not match - */ -#define UART_LSR_RXIDLE_MASK (0x80000000UL) -#define UART_LSR_RXIDLE_SHIFT (31U) -#define UART_LSR_RXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_RXIDLE_MASK) >> UART_LSR_RXIDLE_SHIFT) - -/* - * TXIDLE (RO) - * - * txidle after timeout, clear after tx idle condition not match - */ -#define UART_LSR_TXIDLE_MASK (0x40000000UL) -#define UART_LSR_TXIDLE_SHIFT (30U) -#define UART_LSR_TXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_TXIDLE_MASK) >> UART_LSR_TXIDLE_SHIFT) - -/* - * RFIFO_NUM (RO) - * - * data bytes in rxfifo not read - */ -#define UART_LSR_RFIFO_NUM_MASK (0x1F0000UL) -#define UART_LSR_RFIFO_NUM_SHIFT (16U) -#define UART_LSR_RFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_RFIFO_NUM_MASK) >> UART_LSR_RFIFO_NUM_SHIFT) - -/* - * TFIFO_NUM (RO) - * - * data bytes in txfifo not sent - */ -#define UART_LSR_TFIFO_NUM_MASK (0x1F00U) -#define UART_LSR_TFIFO_NUM_SHIFT (8U) -#define UART_LSR_TFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_TFIFO_NUM_MASK) >> UART_LSR_TFIFO_NUM_SHIFT) - -/* - * ERRF (RO) - * - * Error in RXFIFO - * In the FIFO mode, this bit is set when there is at least - * one parity error, framing error, or line break - * associated with data in the RXFIFO. It is cleared when - * this register is read and there is no more error for the - * rest of data in the RXFIFO. - */ -#define UART_LSR_ERRF_MASK (0x80U) -#define UART_LSR_ERRF_SHIFT (7U) -#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) - -/* - * TEMT (RO) - * - * Transmitter empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) and the Transmitter Shift Register (TSR) are - * both empty. Otherwise, it is zero. - */ -#define UART_LSR_TEMT_MASK (0x40U) -#define UART_LSR_TEMT_SHIFT (6U) -#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) - -/* - * THRE (RO) - * - * Transmitter Holding Register empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) is empty. Otherwise, it is zero. - * If the THRE interrupt is enabled, an interrupt is - * triggered when THRE becomes 1. - */ -#define UART_LSR_THRE_MASK (0x20U) -#define UART_LSR_THRE_SHIFT (5U) -#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) - -/* - * LBREAK (RO) - * - * Line break - * This bit is set when the uart_sin input signal was held - * LOWfor longer than the time for a full-word - * transmission. A full-word transmission is the - * transmission of the START, data, parity, and STOP - * bits. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the line break for - * the received data at the top of the RXFIFO. - */ -#define UART_LSR_LBREAK_MASK (0x10U) -#define UART_LSR_LBREAK_SHIFT (4U) -#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) - -/* - * FE (RO) - * - * Framing error - * This bit is set when the received STOP bit is not - * HIGH. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the framing error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_FE_MASK (0x8U) -#define UART_LSR_FE_SHIFT (3U) -#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) - -/* - * PE (RO) - * - * Parity error - * This bit is set when the received parity does not match - * with the parity selected in the LCR[5:4]. It is cleared - * when this register is read. - * In the FIFO mode, this bit indicates the parity error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_PE_MASK (0x4U) -#define UART_LSR_PE_SHIFT (2U) -#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) - -/* - * OE (RO) - * - * Overrun error - * This bit indicates that data in the Receiver Buffer - * Register (RBR) is overrun. - */ -#define UART_LSR_OE_MASK (0x2U) -#define UART_LSR_OE_SHIFT (1U) -#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) - -/* - * DR (RO) - * - * Data ready. - * This bit is set when there are incoming received data - * in the Receiver Buffer Register (RBR). It is cleared - * when all of the received data are read. - */ -#define UART_LSR_DR_MASK (0x1U) -#define UART_LSR_DR_SHIFT (0U) -#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) - -/* Bitfield definition for register: MSR */ -/* - * CTS (RO) - * - * Clear to send - * 0: The modem_ctsn input signal is HIGH. - * 1: The modem_ctsn input signal is LOW. - */ -#define UART_MSR_CTS_MASK (0x10U) -#define UART_MSR_CTS_SHIFT (4U) -#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) - -/* - * DCTS (RC) - * - * Delta clear to send - * This bit is set when the state of the modem_ctsn input - * signal has been changed since the last time this - * register is read. - */ -#define UART_MSR_DCTS_MASK (0x1U) -#define UART_MSR_DCTS_SHIFT (0U) -#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) - -/* Bitfield definition for register: GPR */ -/* - * DATA (RW) - * - * A one-byte storage register - */ -#define UART_GPR_DATA_MASK (0xFFU) -#define UART_GPR_DATA_SHIFT (0U) -#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) -#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) - - - - -#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_usb_regs.h deleted file mode 100644 index ffaaefb4024..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM5300/ip/hpm_usb_regs.h +++ /dev/null @@ -1,2271 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_USB_H -#define HPM_USB_H - -typedef struct { - __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ - __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ - __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ - __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ - __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ - __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ - __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ - __RW uint32_t USBCMD; /* 0x140: USB Command Register */ - __RW uint32_t USBSTS; /* 0x144: USB Status Register */ - __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ - __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ - __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ - union { - __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ - __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ - }; - union { - __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ - __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ - }; - __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ - __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ - __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ - __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ - __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ - __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ - __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ - __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ - __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ - __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ - __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ - __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ - __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ - __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ - __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ - __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[16]; /* 0x1C0 - 0x1FC: Endpoint Control0 Register... Endpoint Control7 Register */ - __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */ - __RW uint32_t PHY_CTRL0; /* 0x210: */ - __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED8[8]; /* 0x218 - 0x21F: Reserved */ - __RW uint32_t TOP_STATUS; /* 0x220: */ - __RW uint32_t PHY_STATUS; /* 0x224: */ -} USB_Type; - - -/* Bitfield definition for register: GPTIMER0LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) -#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER0CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD - */ -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software; - * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the - * counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: GPTIMER1LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) -#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER1CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - */ -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and - * automatically reload the counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: SBUSCFG */ -/* - * AHBBRST (RW) - * - * AHBBRST - * AHB master interface Burst configuration - * These bits control AHB master transfer type sequence (or priority). - * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. - * 000 - Incremental burst of unspecified length only - * 001 - INCR4 burst, then single transfer - * 010 - INCR8 burst, INCR4 burst, then single transfer - * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer - * 100 - Reserved, don't use - * 101 - INCR4 burst, then incremental burst of unspecified length - * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length - * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) -#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) - -/* Bitfield definition for register: USBCMD */ -/* - * ITC (RW) - * - * ITC - * Interrupt Threshold Control -Read/Write. - * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. - * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are - * shown below. - * Value Maximum Interrupt Interval - * 00000000 - Immediate (no threshold) - * 00000001 - 1 micro-frame - * 00000010 - 2 micro-frames - * 00000100 - 4 micro-frames - * 00001000 - 8 micro-frames - * 00010000 - 16 micro-frames - * 00100000 - 32 micro-frames - * 01000000 - 64 micro-frames - */ -#define USB_USBCMD_ITC_MASK (0xFF0000UL) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) -#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) - -/* - * FS_2 (RW) - * - * FS_2 - * Frame List Size - (Read/Write or Read Only). [host mode only] - * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. - * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. - * NOTE: This field is made up from USBCMD bits 15, 3 and 2. - * Value Meaning - * 0b000 - 1024 elements (4096 bytes) Default value - * 0b001 - 512 elements (2048 bytes) - * 0b010 - 256 elements (1024 bytes) - * 0b011 - 128 elements (512 bytes) - * 0b100 - 64 elements (256 bytes) - * 0b101 - 32 elements (128 bytes) - * 0b110 - 16 elements (64 bytes) - * 0b111 - 8 elements (32 bytes) - */ -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) - -/* - * ATDTW (RW) - * - * ATDTW - * Add dTD TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's - * linked list. This bit is set and cleared by software. - * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD - * to a primed endpoint may go unrecognized. - */ -#define USB_USBCMD_ATDTW_MASK (0x4000U) -#define USB_USBCMD_ATDTW_SHIFT (14U) -#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) - -/* - * SUTW (RW) - * - * SUTW - * Setup TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. - * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then - * there is a hazard when new setup data arrives while the DCD is copying the setup data payload - * from the QH for a previous setup packet. This bit is set and cleared by software. - * This bit would also be cleared by hardware when a hazard detected. - */ -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) - -/* - * PRM (WO) - * - * Asynchronous Schedule start- Write only， host mode only。 - * this bit is used to notify hostcontroller to start async schedule immediately. - */ -#define USB_USBCMD_PRM_MASK (0x1000U) -#define USB_USBCMD_PRM_SHIFT (12U) -#define USB_USBCMD_PRM_SET(x) (((uint32_t)(x) << USB_USBCMD_PRM_SHIFT) & USB_USBCMD_PRM_MASK) -#define USB_USBCMD_PRM_GET(x) (((uint32_t)(x) & USB_USBCMD_PRM_MASK) >> USB_USBCMD_PRM_SHIFT) - -/* - * ASPE (RW) - * - * ASPE - * Asynchronous Schedule Park Mode Enable - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. - * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. - * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - * NOTE: ASPE bit reset value: '0b' for OTG controller . - */ -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) - -/* - * ASP (RW) - * - * ASP - * Asynchronous Schedule Park Mode Count - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. - * It contains a count of the number of successive transactions the host controller is allowed to - * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. - * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. - * This field is set to 3h in all controller core. - */ -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) - -/* - * IAA (RW) - * - * IAA - * Interrupt on Async Advance Doorbell - Read/Write. - * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. - * When the host controller has evicted all appropriate cached schedule states, - * it sets the Interrupt on Async Advance status bit in the USBSTS register. - * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. - * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. - * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. - * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - */ -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) - -/* - * ASE (RW) - * - * ASE - * Asynchronous Schedule Enable - Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Asynchronous Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Asynchronous Schedule. - * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - */ -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) - -/* - * PSE (RW) - * - * PSE - * Periodic Schedule Enable- Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Periodic Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Periodic Schedule - * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - */ -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) - -/* - * FS_1 (RW) - * - * FS_1 - * See description at bit 15 - */ -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) - -/* - * RST (RW) - * - * RST - * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. - * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. - * Host operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. - * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. - * Attempting to reset an actively running host controller will result in undefined behavior. - * Device operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. - * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - */ -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) - -/* - * RS (RW) - * - * RS - * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. - * Host operation mode: - * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. - * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. - * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. - * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). - * Device operation mode: - * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. - * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. - * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) - -/* Bitfield definition for register: USBSTS */ -/* - * TI1 (RWC) - * - * TI1 - * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. - * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this - * bit will clear it. - */ -#define USB_USBSTS_TI1_MASK (0x2000000UL) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) -#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) - -/* - * TI0 (RWC) - * - * TI0 - * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. - * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this - * bit clears it. - */ -#define USB_USBSTS_TI0_MASK (0x1000000UL) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) - -/* - * UPI (RWC) - * - * USB Host Periodic Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. - * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero. - */ -#define USB_USBSTS_UPI_MASK (0x80000UL) -#define USB_USBSTS_UPI_SHIFT (19U) -#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) -#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) - -/* - * UAI (RWC) - * - * USB Host Asynchronous Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. - * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero - */ -#define USB_USBSTS_UAI_MASK (0x40000UL) -#define USB_USBSTS_UAI_SHIFT (18U) -#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) -#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) - -/* - * NAKI (RO) - * - * NAKI - * NAK Interrupt Bit--RO. - * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and - * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware - * when all Enabled TX/RX Endpoint NAK bits are cleared. - */ -#define USB_USBSTS_NAKI_MASK (0x10000UL) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) - -/* - * AS (RO) - * - * AS - * Asynchronous Schedule Status - Read Only. - * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. - * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) - -/* - * PS (RO) - * - * PS - * Periodic Schedule Status - Read Only. - * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. - * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) - -/* - * RCL (RO) - * - * RCL - * Reclamation - Read Only. - * This is a read-only status bit used to detect an empty asynchronous schedule. - * Only used in the host operation mode. - */ -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) - -/* - * HCH (RO) - * - * HCH - * HCHaIted - Read Only. - * This bit is a zero whenever the Run/Stop bit is a one. - * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - * either by software or by the Controller hardware (for example, an internal error). - * Only used in the host operation mode. - * Default value is '0b' for OTG core . - * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE - * register. - * NOTE: HCH bit reset value: '0b' for OTG controller core . - */ -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) - -/* - * SLI (RWC) - * - * SLI - * DCSuspend - R/WC. - * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. - * Only used in device operation mode. - */ -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) - -/* - * SRI (RWC) - * - * SRI - * SOF Received - R/WC. - * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. - * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. - * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. - * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. - * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. - * Software writes a 1 to this bit to clear it. - */ -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) - -/* - * URI (RWC) - * - * URI - * USB Reset Received - R/WC. - * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. - * Software can write a 1 to this bit to clear the USB Reset Received status bit. - * Only used in device operation mode. - */ -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) - -/* - * AAI (RWC) - * - * AAI - * Interrupt on Async Advance - R/WC. - * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule - * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. - * Only used in host operation mode. - */ -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) - -/* - * SEI (RWC) - * - * System Error – RWC. Default = 0b. - * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. - * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - */ -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) - -/* - * FRI (RWC) - * - * FRI - * Frame List Rollover - R/WC. - * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to - * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the - * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the - * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host - * Controller sets this bit to a one every time FHINDEX [12] toggles. - * Only used in host operation mode. - */ -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) - -/* - * PCI (RWC) - * - * PCI - * Port Change Detect - R/WC. - * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, - * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. - * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. - * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, - * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - */ -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) - -/* - * UEI (RWC) - * - * UEI - * USB Error Interrupt (USBERRINT) - R/WC. - * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. - * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - */ -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) - -/* - * UI (RWC) - * - * UI - * USB Interrupt (USBINT) - R/WC. - * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB - * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. - * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when - * the actual number of bytes received was less than the expected number of bytes. - */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) - -/* Bitfield definition for register: USBINTR */ -/* - * TIE1 (RW) - * - * TIE1 - * General Purpose Timer #1 Interrupt Enable - * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE1_MASK (0x2000000UL) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) -#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) - -/* - * TIE0 (RW) - * - * TIE0 - * General Purpose Timer #0 Interrupt Enable - * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE0_MASK (0x1000000UL) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) - -/* - * UPIE (RW) - * - * UPIE - * USB Host Periodic Interrupt Enable - * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UPIE_MASK (0x80000UL) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) - -/* - * UAIE (RW) - * - * UAIE - * USB Host Asynchronous Interrupt Enable - * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UAIE_MASK (0x40000UL) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) - -/* - * NAKE (RO) - * - * NAKE - * NAK Interrupt Enable - * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_NAKE_MASK (0x10000UL) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) - -/* - * SLE (RW) - * - * SLE - * Sleep Interrupt Enable - * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) - -/* - * SRE (RW) - * - * SRE - * SOF Received Interrupt Enable - * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) - -/* - * URE (RW) - * - * URE - * USB Reset Interrupt Enable - * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) - -/* - * AAE (RW) - * - * AAE - * Async Advance Interrupt Enable - * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) - -/* - * SEE (RW) - * - * SEE - * System Error Interrupt Enable - * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) - -/* - * FRE (RW) - * - * FRE - * Frame List Rollover Interrupt Enable - * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) - -/* - * PCE (RW) - * - * PCE - * Port Change Detect Interrupt Enable - * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) - -/* - * UEE (RWC) - * - * UEE - * USB Error Interrupt Enable - * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) - -/* - * UE (RW) - * - * UE - * USB Interrupt Enable - * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) - -/* Bitfield definition for register: FRINDEX */ -/* - * FRINDEX (RW) - * - * FRINDEX - * Frame Index. - * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. - * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. - * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. - * USBCMD [Frame List Size] Number Elements N - * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. - * In either mode bits 2:0 indicate the current microframe. - * The bit field values description below is represented as (Frame List Size) Number Elements N. - * 00000000000000 - (1024) 12 - * 00000000000001 - (512) 11 - * 00000000000010 - (256) 10 - * 00000000000011 - (128) 9 - * 00000000000100 - (64) 8 - * 00000000000101 - (32) 7 - * 00000000000110 - (16) 6 - * 00000000000111 - (8) 5 - */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) -#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) - -/* Bitfield definition for register: DEVICEADDR */ -/* - * USBADR (RW) - * - * USBADR - * Device Address. - * These bits correspond to the USB device address - */ -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) -#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) - -/* - * USBADRA (RW) - * - * USBADRA - * Device Address Advance. Default=0. - * When this bit is '0', any writes to USBADR are instantaneous. - * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. - * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. - * Hardware will automatically clear this bit on the following conditions: - * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). - * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). - * 3) Device Reset occurs (USBADR is reset to 0). - * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. - * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. - * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), - * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) - -/* Bitfield definition for register: PERIODICLISTBASE */ -/* - * BASEADR (RW) - * - * BASEADR - * Base Address (Low). - * These bits correspond to memory address signals [31:12], respectively. - * Only used by the host controller. - */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) -#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) - -/* Bitfield definition for register: ASYNCLISTADDR */ -/* - * ASYBASE (RW) - * - * ASYBASE - * Link Pointer Low (LPL). - * These bits correspond to memory address signals [31:5], respectively. This field may only reference a - * Queue Head (QH). - * Only used by the host controller. - */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) -#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) - -/* Bitfield definition for register: ENDPTLISTADDR */ -/* - * EPBASE (RW) - * - * EPBASE - * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. - * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) -#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) - -/* Bitfield definition for register: BURSTSIZE */ -/* - * TXPBURST (RW) - * - * TXPBURST - * Programmable TX Burst Size. - * Default value is determined by TXBURST bits in n_HWTXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from system - * memory to the USB bus. - */ -#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) - -/* - * RXPBURST (RW) - * - * RXPBURST - * Programmable RX Burst Size. - * Default value is determined by TXBURST bits in n_HWRXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from the - * USB bus to system memory. - */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) - -/* Bitfield definition for register: TXFILLTUNING */ -/* - * TXFIFOTHRES (RW) - * - * TXFIFOTHRES - * FIFO Burst Threshold. (Read/Write) - * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. - * The minimum value is 2 and this value should be a low as possible to maximize USB performance. - * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth - * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. - * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - */ -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* - * TXSCHHEALTH (RWC) - * - * TXSCHHEALTH - * Scheduler Health Counter. (Read/Write To Clear) - * Table continues on the next page - * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES - * before running out of time to send the packet before the next Start-Of-Frame. - * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. - * Writing to this register will clear the counter and this counter will max. at 31. - */ -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) - -/* - * TXSCHOH (RW) - * - * TXSCHOH - * Scheduler Overhead. (Read/Write) [Default = 0] - * This register adds an additional fixed offset to the schedule time estimator described above as Tff. - * As an approximation, the value chosen for this register should limit the number of back-off events captured - * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. - * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. - * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. - * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. - * Default value is '08h' for OTG controller core . - */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) - -/* Bitfield definition for register: ENDPTNAK */ -/* - * EPTN (RWC) - * - * EPTN - * TX Endpoint NAK - R/WC. - * Each TX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received IN token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) -#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) - -/* - * EPRN (RWC) - * - * EPRN - * RX Endpoint NAK - R/WC. - * Each RX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) - -/* Bitfield definition for register: ENDPTNAKEN */ -/* - * EPTNE (RW) - * - * EPTNE - * TX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the - * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) - -/* - * EPRNE (RW) - * - * EPRNE - * RX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the - * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) - -/* Bitfield definition for register: PORTSC1 */ -/* - * STS (RW) - * - * STS - * Serial Transceiver Select - * 1 Serial Interface Engine is selected - * 0 Parallel Interface signals is selected - * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. - * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - */ -#define USB_PORTSC1_STS_MASK (0x20000000UL) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) - -/* - * PTW (RW) - * - * PTW - * Parallel Transceiver Width - * This bit has no effect if serial interface engine is used. - * 0 - Select the 8-bit UTMI interface [60MHz] - * 1 - Select the 16-bit UTMI interface [30MHz] - */ -#define USB_PORTSC1_PTW_MASK (0x10000000UL) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) - -/* - * PSPD (RO) - * - * PSPD - * Port Speed - Read Only. - * This register field indicates the speed at which the port is operating. - * 00 - Full Speed - * 01 - Low Speed - * 10 - High Speed - * 11 - Undefined - */ -#define USB_PORTSC1_PSPD_MASK (0xC000000UL) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) - -/* - * PFSC (RW) - * - * PFSC - * Port Force Full Speed Connect - Read/Write. Default = 0b. - * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp - * sequence that allows the port to identify itself as High Speed. - * 0 - Normal operation - * 1 - Forced to full speed - */ -#define USB_PORTSC1_PFSC_MASK (0x1000000UL) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) - -/* - * PHCD (RW) - * - * PHCD - * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. - * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY - * clock. - * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. - * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD - * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend - * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the - * device controller driver must clear this bit. - * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put - * into suspend mode or when no downstream device is connected. Low power suspend is completely - * under the control of software. - * 0 - Enable PHY clock - * 1 - Disable PHY clock - */ -#define USB_PORTSC1_PHCD_MASK (0x800000UL) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) - -/* - * WKOC (RW) - * - * WKOC - * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. - * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero. - */ -#define USB_PORTSC1_WKOC_MASK (0x400000UL) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) - -/* - * WKDC (RW) - * - * WKDC - * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables - * the port to be sensitive to device disconnects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKDC_MASK (0x200000UL) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) - -/* - * WKCN (RW) - * - * WKCN - * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. - * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKCN_MASK (0x100000UL) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) - -/* - * PTC (RW) - * - * PTC - * Port Test Control - Read/Write. Default = 0000b. - * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. - * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. - * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. - * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. - * NOTE: Low speed operations are not supported as a peripheral device. - * Any other value than zero indicates that the port is operating in test mode. - * Value Specific Test - * 0000 - TEST_MODE_DISABLE - * 0001 - J_STATE - * 0010 - K_STATE - * 0011 - SE0 (host) / NAK (device) - * 0100 - Packet - * 0101 - FORCE_ENABLE_HS - * 0110 - FORCE_ENABLE_FS - * 0111 - FORCE_ENABLE_LS - * 1000-1111 - Reserved - */ -#define USB_PORTSC1_PTC_MASK (0xF0000UL) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) - -/* - * PP (RW) - * - * PP - * Port Power (PP)-Read/Write or Read Only. - * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: - * PPC - * PP Operation - * 0 - * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. - * 1 - * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). - * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. - * When an over-current condition is detected on a powered port and PPC is a one, - * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). - * This feature is implemented in all controller cores (PPC = 1). - */ -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) - -/* - * LS (RO) - * - * LS - * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal - * lines. - * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because - * the port controller state machine and the port routing manage the connection of LS and FS. - * In device mode, the use of linestate by the device controller driver is not necessary. - * The encoding of the bits are: - * Bits [11:10] Meaning - * 00 - SE0 - * 01 - K-state - * 10 - J-state - * 11 - Undefined - */ -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) - -/* - * HSP (RO) - * - * HSP - * High-Speed Port - Read Only. Default = 0b. - * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the - * host/device connected to the port is not in a high-speed mode. - * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - */ -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) - -/* - * PR (RW) - * - * PR - * Port Reset - Read/Write or Read Only. Default = 0b. - * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. - * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. - * This bit will automatically change to zero after the reset sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. - * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - */ -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) - -/* - * SUSP (RW) - * - * SUSP - * Suspend - Read/Write or Read Only. Default = 0b. - * 1=Port in suspend state. 0=Port not in suspend state. - * In Host Mode: Read/Write. - * Port Enabled Bit and Suspend bit of this register define the port states as follows: - * Bits [Port Enabled, Suspend] Port State - * 0x Disable - * 10 Enable - * 11 Suspend - * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. - * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. - * In the suspend state, the port is sensitive to resume detection. - * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. - * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. - * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: Read Only. - * In device mode this bit is a read only status bit. - */ -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) - -/* - * FPR (RW) - * - * FPR - * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. - * In Host Mode: - * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. - * This bit will automatically change to zero after the resume sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. - * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. - * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. - * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * This bit is not-EHCI compatible. - * In Device mode: - * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. - * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * The bit will be cleared when the device returns to normal operation. - * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - */ -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) - -/* - * OCC (RW) - * - * OCC - * Over-current Change-R/WC. Default=0. - * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - */ -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) - -/* - * OCA (RO) - * - * OCA - * Over-current Active-Read Only. Default 0. - * This bit will automatically transition from one to zero when the over current condition is removed. - * 0 - This port does not have an over-current condition. - * 1 - This port currently has an over-current condition - */ -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) - -/* - * PEC (RWC) - * - * PEC - * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. - * In Host Mode: - * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or - * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). - * Software clears this by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero. - * In Device mode: - * The device port is always enabled, so this bit is always '0b'. - */ -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) - -/* - * PE (RWC) - * - * PE - * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. - * In Host Mode: - * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. - * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. - * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. - * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * The device port is always enabled, so this bit is always '1b'. - */ -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) - -/* - * CSC (RWC) - * - * CSC - * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. - * In Host Mode: - * Indicates a change has occurred in the port's Current Connect Status. - * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. - * For example, the insertion status changes twice before system software has cleared the changed condition, - * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * This bit is undefined in device controller mode. - */ -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) - -/* - * CCS (RWC) - * - * CCS - * Current Connect Status-Read Only. - * In Host Mode: - * 1=Device is present on port. 0=No device is present. Default = 0. - * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * 1=Attached. 0=Not Attached. Default=0. - * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. - * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. - * It does not state the device being disconnected or Suspended. - */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) - -/* Bitfield definition for register: OTGSC */ -/* - * ASVIE (RW) - * - * ASVIE - * A Session Valid Interrupt Enable - Read/Write. - */ -#define USB_OTGSC_ASVIE_MASK (0x4000000UL) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) - -/* - * AVVIE (RW) - * - * AVVIE - * A VBus Valid Interrupt Enable - Read/Write. - * Setting this bit enables the A VBus valid interrupt. - */ -#define USB_OTGSC_AVVIE_MASK (0x2000000UL) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) - -/* - * IDIE (RW) - * - * IDIE - * USB ID Interrupt Enable - Read/Write. - * Setting this bit enables the USB ID interrupt. - */ -#define USB_OTGSC_IDIE_MASK (0x1000000UL) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) - -/* - * ASVIS (RWC) - * - * ASVIS - * A Session Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the A session valid threshold. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_ASVIS_MASK (0x40000UL) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) - -/* - * AVVIS (RWC) - * - * AVVIS - * A VBus Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_AVVIS_MASK (0x20000UL) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) - -/* - * IDIS (RWC) - * - * IDIS - * USB ID Interrupt Status - Read/Write. - * This bit is set when a change on the ID input has been detected. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_IDIS_MASK (0x10000UL) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) - -/* - * ASV (RO) - * - * ASV - * A Session Valid - Read Only. - * Indicates VBus is above the A session valid threshold. - */ -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) - -/* - * AVV (RO) - * - * AVV - * A VBus Valid - Read Only. - * Indicates VBus is above the A VBus valid threshold. - */ -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) - -/* - * ID (RO) - * - * ID - * USB ID - Read Only. - * 0 = A device, 1 = B device - */ -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) - -/* - * IDPU (RW) - * - * IDPU - * ID Pullup - Read/Write - * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input - * will not be sampled. - */ -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) - -/* - * VC (RW) - * - * VC - * VBUS Charge - Read/Write. - * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - */ -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) - -/* - * VD (RW) - * - * VD - * VBUS_Discharge - Read/Write. - * Setting this bit causes VBus to discharge through a resistor. - */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) - -/* Bitfield definition for register: USBMODE */ -/* - * SDIS (RW) - * - * SDIS - * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) - * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. - * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. - * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. - * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems - * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. - * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for - * the scheduler when using this feature. - * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - */ -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) -#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) - -/* - * SLOM (RW) - * - * SLOM - * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . - * 0 - Setup Lockouts On (default); - * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - */ -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) - -/* - * ES (RW) - * - * ES - * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the - * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected - * by the value of this bit because they are based upon the 32-bit word. - * Bit Meaning - * 0 - Little Endian [Default] - * 1 - Big Endian - */ -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) - -/* - * CM (RW) - * - * CM - * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only - * implementations. For those designs that contain both host & device capability, the controller defaults to - * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ - * device controllers, this register can only be written once after reset. If it is necessary to switch modes, - * software must reset the controller by writing to the RESET bit in the USBCMD register before - * reprogramming this register. - * For OTG controller core, reset value is '00b'. - * 00 - Idle [Default for combination host/device] - * 01 - Reserved - * 10 - Device Controller [Default for device only controller] - * 11 - Host Controller [Default for host only controller] - */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) - -/* Bitfield definition for register: ENDPTSETUPSTAT */ -/* - * ENDPTSETUPSTAT (RWC) - * - * ENDPTSETUPSTAT - * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. - * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. - * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. - * This register is only used in device mode. - */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* Bitfield definition for register: ENDPTPRIME */ -/* - * PETB (RWS) - * - * PETB - * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a - * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. - * Software should write a one to the corresponding bit when posting a new transfer descriptor to an - * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor - * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated - * endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) -#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) - -/* - * PERB (RWS) - * - * PERB - * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. - * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. - * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. - * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) - -/* Bitfield definition for register: ENDPTFLUSH */ -/* - * FETB (RWS) - * - * FETB - * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) -#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) - -/* - * FERB (RWS) - * - * FERB - * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) - -/* Bitfield definition for register: ENDPTSTAT */ -/* - * ETBR (RO) - * - * ETBR - * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. - * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. - * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. - * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. - * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. - * ETBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) - -/* - * ERBR (RO) - * - * ERBR - * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective - * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a - * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the - * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB - * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the - * USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations - * when a dTD is retired, and the dQH is updated. - * ERBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) - -/* Bitfield definition for register: ENDPTCOMPLETE */ -/* - * ETCE (RWC) - * - * ETCE - * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. - * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. - * ETCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) - -/* - * ERCE (RWC) - * - * ERCE - * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred - * and software should read the corresponding endpoint queue to determine the transfer status. If the - * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the - * USBINT . Writing one clears the corresponding bit in this register. - * ERCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) - -/* Bitfield definition for register array: ENDPTCTRL */ -/* - * TXE (RW) - * - * TXE - * TX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) -#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) - -/* - * TXR (WS) - * - * TXR - * TX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the Host and device. - */ -#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) - -/* - * TXT (RW) - * - * TXT - * TX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) - -/* - * TXS (RW) - * - * TXS - * TX Endpoint Stall - Read/Write - * 0 End Point OK - * 1 End Point Stalled - * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured - * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. - * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. - * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: - * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - */ -#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) - -/* - * RXE (RW) - * - * RXE - * RX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) - -/* - * RXR (WS) - * - * RXR - * RX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the host and device. - */ -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) - -/* - * RXT (RW) - * - * RXT - * RX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) - -/* - * RXS (RW) - * - * RXS - * RX Endpoint Stall - Read/Write - * 0 End Point OK. [Default] - * 1 End Point Stalled - * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control - * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit - * is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This - * control will continue to STALL until this bit is either cleared by software or automatically cleared as above - * for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the - * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it - * is unlikely the DCD software will observe this delay. However, should the DCD observe that the - * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit - * until it is set or until a new setup has been received by checking the associated endptsetupstat - * Bit. - */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) - -/* Bitfield definition for register: OTG_CTRL0 */ -/* - * OTG_WKDPDMCHG_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) - -/* - * AUTORESUME_EN (RW) - * - */ -#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) -#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) -#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) -#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) - -/* - * OTG_VBUS_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) - -/* - * OTG_ID_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) - -/* - * OTG_VBUS_SOURCE_SEL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) - -/* - * OTG_UTMI_SUSPENDM_SW (RW) - * - * default 0 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) - -/* - * OTG_UTMI_RESET_SW (RW) - * - * default 1 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) - -/* - * OTG_WAKEUP_INT_ENABLE (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) - -/* - * OTG_POWER_MASK (RW) - * - */ -#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) -#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) - -/* - * OTG_OVER_CUR_POL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) - -/* - * OTG_OVER_CUR_DIS (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) - -/* - * SER_MODE_SUSPEND_EN (RW) - * - * for naneng usbphy, only switch to serial mode when suspend - */ -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL0 */ -/* - * GPIO_ID_SEL_N (RW) - * - */ -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) - -/* - * ID_DIG_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) - -/* - * SESS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) - -/* - * VBUS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) - -/* - * ID_DIG_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) - -/* - * SESS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) - -/* - * VBUS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL1 */ -/* - * UTMI_CFG_RST_N (RW) - * - */ -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) - -/* - * UTMI_OTG_SUSPENDM (RW) - * - * OTG suspend, not utmi_suspendm - */ -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) - -/* Bitfield definition for register: TOP_STATUS */ -/* - * WAKEUP_INT_STATUS (RW) - * - */ -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * UTMI_CLK_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) -#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) - -/* - * LINE_STATE (RW) - * - */ -#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) -#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) -#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) -#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) - -/* - * HOST_DISCONNECT (RW) - * - */ -#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) -#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) - -/* - * ID_DIG (RW) - * - */ -#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) -#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) -#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) -#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) - -/* - * UTMI_SESS_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) -#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) - -/* - * VBUS_VALID (RW) - * - */ -#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) -#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) -#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) -#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) - - - -/* ENDPTCTRL register group index macro definition */ -#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) -#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) -#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) -#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) -#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) -#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) -#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) -#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) -#define USB_ENDPTCTRL_ENDPTCTRL8 (8UL) -#define USB_ENDPTCTRL_ENDPTCTRL9 (9UL) -#define USB_ENDPTCTRL_ENDPTCTRL10 (10UL) -#define USB_ENDPTCTRL_ENDPTCTRL11 (11UL) -#define USB_ENDPTCTRL_ENDPTCTRL12 (12UL) -#define USB_ENDPTCTRL_ENDPTCTRL13 (13UL) -#define USB_ENDPTCTRL_ENDPTCTRL14 (14UL) -#define USB_ENDPTCTRL_ENDPTCTRL15 (15UL) - - -#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/HPM6280_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/HPM6280_svd.xml deleted file mode 100644 index 65c7646162b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/HPM6280_svd.xml +++ /dev/null @@ -1,23381 +0,0 @@ - - - HPMICRO - HPM6280 - HPM6200 - 1.0 - HPM6200 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - GPIO1 - GPIO1 - GPIO - 0xf0004000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - - - - ADC0 - ADC0 - ADC16 - 0xf0010000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 16 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x01F07FFF - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ADC1 - ADC1 - ADC16 - 0xf0014000 - - - ADC2 - ADC2 - ADC16 - 0xf0018000 - - - SDM - SDM - SDM - 0xf001c000 - - 0x0 - 0x110 - registers - - - - CTRL - SDM control register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFE - - - SFTRST - software reset the module if asserted to be1’b1. - 31 - 1 - read-write - - - CHMD - Channel Rcv mode -Bits[2:0] for Ch0. -Bits[5:3] for Ch1 -Bits[8:6] for Ch2 -Bits[11:9] for Ch3 -3'b000: Capture at posedge of MCLK -3'b001: Capture at both posedge and negedge of MCLK -3'b010: Manchestor Mode -3'b011: Capture at negedge of MCLK -3'b100: Capture at every other posedge of MCLK -3'b101: Capture at every other negedge of MCLK -Others: Undefined - 14 - 12 - read-write - - - SYNC_MCLK - Asserted to double sync the mclk input pin before its usage inside the module - 10 - 4 - read-write - - - SYNC_MDAT - Asserted to double sync the mdat input pin before its usage inside the module - 6 - 4 - read-write - - - CH_EN - Channel Enable - 2 - 4 - read-write - - - IE - Interrupt Enable - 1 - 1 - read-write - - - - - INT_EN - Interrupt enable register. - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3DRY - Ch3 Data Ready interrupt enable. - 7 - 1 - read-write - - - CH2DRY - Ch2 Data Ready interrupt enable - 6 - 1 - read-write - - - CH1DRY - Ch1 Data Ready interrupt enable - 5 - 1 - read-write - - - CH0DRY - Ch0 Data Ready interrupt enable - 4 - 1 - read-write - - - CH3ERR - Ch3 Error interrupt enable. - 3 - 1 - read-write - - - CH2ERR - Ch2 Error interrupt enable - 2 - 1 - read-write - - - CH1ERR - Ch1 Error interrupt enable - 1 - 1 - read-write - - - CH0ERR - Ch0 Error interrupt enable - 0 - 1 - read-write - - - - - STATUS - Status Registers - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3DRY - Ch3 Data Ready. -De-assert this bit by reading the data (or data fifo) registers. - 7 - 1 - read-only - - - CH2DRY - Ch2 Data Ready - 6 - 1 - read-only - - - CH1DRY - Ch1 Data Ready - 5 - 1 - read-only - - - CH0DRY - Ch0 Data Ready - 4 - 1 - read-only - - - CH3ERR - Ch3 Error. -ORed together by channel related error signals and corresponding error interrupt enable signals. -De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. - 3 - 1 - read-only - - - CH2ERR - Ch2 Error - 2 - 1 - read-only - - - CH1ERR - Ch1 Error - 1 - 1 - read-only - - - CH0ERR - Ch0 Error - 0 - 1 - read-only - - - - - 4 - 0x40 - 0,1,2,3 - CH[%s] - no description available - 0x10 - - SDFIFOCTRL - Data FIFO Path Control Register - 0x0 - 32 - 0x00000000 - 0xFFFF01F4 - - - GATE_SAMPLES - The number-1-3 of input PDM bit samples to be gated when CIC_GATE_EN=1. Max 255. So the minimum gated samples is 4 samples when GATE_SAMPLES=0. - 16 - 8 - read-write - - - THRSH - FIFO threshold (0,..,16) (fillings > threshold, then gen int) - 4 - 5 - read-write - - - D_RDY_INT_EN - FIFO data ready interrupt enable - 2 - 1 - read-write - - - - - SDCTRLP - Data Path Control Primary Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MANCH_THR - Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] - 25 - 7 - read-write - - - WDOG_THR - Watch dog threshold for channel failure of CLK halting - 17 - 8 - read-write - - - AF_IE - Acknowledge feedback interrupt enable - 16 - 1 - read-write - - - DFFOVIE - Ch Data FIFO overflow interrupt enable - 15 - 1 - read-write - - - DSATIE - Ch CIC Data Saturation Interrupt Enable - 14 - 1 - read-write - - - DRIE - Ch Data Ready Interrupt Enable - 13 - 1 - read-write - - - SYNCSEL - Select the PWM SYNC Source - 7 - 6 - read-write - - - FFSYNCCLREN - Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 - 6 - 1 - read-write - - - WTSYNACLR - 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen -0: WTSYNFLG should be cleared manually by WTSYNMCLR - 5 - 1 - read-write - - - WTSYNMCLR - 1: Manually clear WTSYNFLG. Auto-clear. - 4 - 1 - read-write - - - WTSYNCEN - 1: Start to store data only after PWM SYNC event -0: Start to store data whenever enabled - 3 - 1 - read-write - - - D32 - 1:32 bit data -0:16 bit data - 2 - 1 - read-write - - - DR_OPT - 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold -0: Use Data Reg Ready as data ready - 1 - 1 - read-write - - - EN - Data Path Enable - 0 - 1 - read-write - - - - - SDCTRLE - Data Path Control Extra Register - 0x8 - 32 - 0x00000000 - 0xFE77FFFF - - - CIC_GATE_TYPE - 1: the gate cycle is determined by SDFIFOCTRLn[GATE_SAMPLES]. -0: the gate cycle is determined by the CIC decimation counter, and the minimal gated off PDM bits are determined by SDFIFOCTRLn[GATE_SAMPLES], and at the same time, to keep alignment with normal PCM sampling time. - 31 - 1 - read-write - - - CIC_GATE_POL - 1: When mask signal is 1, pause the CIC stage at he rising edge of mask signal. -0: When mask signal is 0, pause the CIC stage at he falling edge of mask signal. - 30 - 1 - read-write - - - CIC_GATE_SEL - Select the mask signal for CIC gate signal. - 26 - 4 - read-write - - - CIC_GATE_EN - 1: the CIC stage can be paused by the mask input. -0: the CIC stage won't be paused by the mask input. - 25 - 1 - read-write - - - TIMESTAMP_TYPE - 1. Use the time (when the data is calculated out) - delta_time_of_filter_span as the timestamp. -0: Use the time when the data is calculated out. - 22 - 1 - read-write - - - DFIFO_S_T - 1: the output of SDFIFO is data and timestamp interleaved. First is data. -0: the output of SDFIFO is data only - 21 - 1 - read-write - - - DATA_S_T - "1: the read output of SData is data and timestamp interleaved. First is data. -0: the read output of SData is data only" - 20 - 1 - read-write - - - SGD_ORDR - CIC order -0: SYNC1 -1: SYNC2 -2: SYNC3 -3: FAST_SYNC - 17 - 2 - read-write - - - PWMSYNC - Asserted to double sync the PWM trigger signal - 16 - 1 - read-write - - - CIC_SCL - CIC shift control - 11 - 4 - read-write - - - CIC_DEC_RATIO - CIC decimation ratio. 0 means div-by-256 - 3 - 8 - read-write - - - IGN_INI_SAMPLES - NotZero: Don't store the first samples that are not accurate -Zero: Store all samples - 0 - 3 - read-write - - - - - SDST - Data Path Status - 0xc - 32 - 0x00000000 - 0xFF8033FF - - - PERIOD_MCLK - maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. - 23 - 8 - read-only - - - SDATA_D0_T1 - 1: next readout is timestamp -0: next readout is data - 13 - 1 - read-only - - - SDFIFO_D0_T1 - 1: next readout is timestamp -0: next readout is data - 12 - 1 - read-only - - - FIFO_DR - FIFO data ready - 9 - 1 - write-only - - - AF - Achnowledge flag - 8 - 1 - write-only - - - DOV_ERR - Data FIFO Overflow Error. Error flag. - 7 - 1 - write-only - - - DSAT_ERR - CIC out Data saturation err. Error flag. - 6 - 1 - write-only - - - WTSYNFLG - Wait-for-sync event found - 5 - 1 - read-only - - - FILL - Data FIFO Fillings - 0 - 5 - read-only - - - - - SDATA - Data - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Data - 0 - 32 - read-only - - - - - SDFIFO - FIFO Data - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - FIFO Data - 0 - 32 - read-only - - - - - SCAMP - instant Amplitude Results - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - instant Amplitude Results - 0 - 16 - read-only - - - - - SCHTL - Amplitude Threshold for High Limit - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Amplitude Threshold for High Limit - 0 - 16 - read-write - - - - - SCHTLZ - Amplitude Threshold for zero crossing - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Amplitude Threshold for zero crossing - 0 - 16 - read-write - - - - - SCLLT - Amplitude Threshold for low limit - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Amplitude Threshold for low limit - 0 - 16 - read-write - - - - - SCCTRL - Amplitude Path Control - 0x28 - 32 - 0x00000000 - 0xFFFC01FF - - - HZ_EN - Zero Crossing Enable - 23 - 1 - read-write - - - MF_IE - Module failure Interrupt enable - 22 - 1 - read-write - - - HL_IE - HLT Interrupt Enable - 21 - 1 - read-write - - - LL_IE - LLT interrupt Enable - 20 - 1 - read-write - - - SGD_ORDR - CIC order -0: SYNC1 -1: SYNC2 -2: SYNC3 -3: FAST_SYNC - 18 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation ratio. 0 means div-by-32 - 4 - 5 - read-write - - - IGN_INI_SAMPLES - NotZero: Ignore the first samples that are not accurate -Zero: Use all samples - 1 - 3 - read-write - - - EN - Amplitude Path Enable - 0 - 1 - read-write - - - - - SCST - Amplitude Path Status - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - HZ - Amplitude rising above HZ event found. - 3 - 1 - write-only - - - MF - power modulator Failure found. MCLK not found. Error flag. - 2 - 1 - write-only - - - CMPH - HLT out of range. Error flag. - 1 - 1 - write-only - - - CMPL - LLT out of range. Error flag. - 0 - 1 - write-only - - - - - - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - 4 - 0x20 - chn0,chn1,chn2,chn3 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - DAC0 - DAC0 - DAC - 0xf0024000 - - 0x0 - 0x4c - registers - - - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - write-only - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - write-only - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - write-only - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - write-only - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - write-only - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; -11: trigger mode, DAC output from external trigger signals -Note: -Trigger mode is not supported in hpm63xx and hpm62xx families. - 4 - 2 - write-only - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - write-only - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - write-only - - - - - cfg1 - No description available - 0x4 - 32 - 0x00010000 - 0x0007FFFF - - - ANA_CLK_EN - set to enable analog clock(divided by ana_div_cfg) -need to be set in direct mode and trigger mode - 18 - 1 - read-write - - - ANA_DIV_CFG - clock divider config for ana_clk to dac analog; -00: div2 -01: div4 -10: div6 -11: div8 - 16 - 2 - read-write - - - DIV_CFG - step mode and buffer mode: - defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. -Direct mode and trigger mode: - defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. -Note: -For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. - 0 - 16 - read-write - - - - - cfg2 - No description available - 0x8 - 32 - 0x00000000 - 0x000000FF - - - DMA_RST1 - set to reset dma read pointer to buf1_start_addr; -if set both dma_rst0&dma_rst1, will set to buf0_start_addr -user can set fifo_clr bit when use dma_rst* - 7 - 1 - write-only - - - DMA_RST0 - set to reset dma read pointer to buf0_start_addr - 6 - 1 - write-only - - - FIFO_CLR - set to clear FIFO content(set both read/write pointer to 0) - 5 - 1 - write-only - - - BUF_SW_TRIG - software trigger for buffer mode, -W1C in single mode. -RW in continual mode - 4 - 1 - read-write - - - STEP_SW_TRIG3 - No description available - 3 - 1 - read-write - - - STEP_SW_TRIG2 - No description available - 2 - 1 - read-write - - - STEP_SW_TRIG1 - No description available - 1 - 1 - read-write - - - STEP_SW_TRIG0 - software trigger0 for step mode, -W1C in single mode. -RW in continual mode - 0 - 1 - read-write - - - - - 4 - 0x4 - step0,step1,step2,step3 - STEP_CFG[%s] - no description available - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description available - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description available - 0 - 12 - read-write - - - - - 2 - 0x4 - buf0,buf1 - BUF_ADDR[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFD - - - BUF_START_ADDR - buffer start address, should be 4-byte aligned -AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - 2 - 30 - read-write - - - BUF_STOP - set to stop read point at end of bufffer0 - 0 - 1 - read-write - - - - - buf_length - No description available - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF1_LEN - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - 16 - 16 - read-write - - - BUF0_LEN - No description available - 0 - 16 - read-write - - - - - irq_sts - No description available - 0x30 - 32 - 0x00000000 - 0x0000001F - - - STEP_CMPT - No description available - 4 - 1 - write-only - - - AHB_ERROR - set if hresp==2'b01(ERROR) - 3 - 1 - write-only - - - FIFO_EMPTY - No description available - 2 - 1 - write-only - - - BUF1_CMPT - No description available - 1 - 1 - write-only - - - BUF0_CMPT - No description available - 0 - 1 - write-only - - - - - irq_en - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - STEP_CMPT - No description available - 4 - 1 - read-write - - - AHB_ERROR - No description available - 3 - 1 - read-write - - - FIFO_EMPTY - No description available - 2 - 1 - read-write - - - BUF1_CMPT - No description available - 1 - 1 - read-write - - - BUF0_CMPT - No description available - 0 - 1 - read-write - - - - - dma_en - No description available - 0x38 - 32 - 0x00000000 - 0x00000013 - - - STEP_CMPT - No description available - 4 - 1 - read-write - - - BUF1_CMPT - No description available - 1 - 1 - read-write - - - BUF0_CMPT - No description available - 0 - 1 - read-write - - - - - ana_cfg0 - No description available - 0x40 - 32 - 0x00000030 - 0x000001FF - - - DAC12BIT_LP_MODE - No description available - 8 - 1 - read-write - - - DAC_CONFIG - No description available - 4 - 4 - read-write - - - CALI_DELTA_V_CFG - No description available - 2 - 2 - read-write - - - BYPASS_CALI_GM - No description available - 1 - 1 - read-write - - - DAC12BIT_EN - No description available - 0 - 1 - read-write - - - - - cfg0_bak - No description available - 0x44 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - read-write - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - read-write - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - read-write - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - read-write - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - read-write - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - 4 - 2 - read-write - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - read-write - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - read-write - - - - - status0 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFF80 - - - CUR_BUF_OFFSET - No description available - 8 - 16 - read-write - - - CUR_BUF_INDEX - No description available - 7 - 1 - read-write - - - - - - - DAC1 - DAC1 - DAC - 0xf0028000 - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x4 - 0x3c - registers - - - - IDLE_CFG - Idle Configuration Register - 0x4 - 32 - 0x00000000 - 0x000003FF - - - RX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if RX pin is logic one -1 - Treat as idle if UART state machine state is idle - 9 - 1 - read-write - - - RX_IDLE_EN - UART Idle Detect Enable -0 - Disable -1 - Enable -it should be enabled if enable address match feature - 8 - 1 - read-write - - - RX_IDLE_THR - Threshold for UART Receive Idle detection (in terms of bits) - 0 - 8 - read-write - - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x8000000F - - - ERXIDLE - Enable Receive Idle interrupt -0 - Disable Idle interrupt -1 - Enable Idle interrupt - 31 - 1 - read-write - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x800000CF - - - RXIDLE_FLAG - UART IDLE Flag -0 - UART is busy -1 - UART is idle -NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - 31 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - PUART - PUART - UART - 0xf40e4000 - - - MCAN0 - MCAN0 - MCAN - 0xf0080000 - - 0x4 - 0x29fc - registers - - - - ENDN - endian register - 0x4 - 32 - 0x87654321 - 0xFFFFFFFF - - - EVT - Endianness Test Value -The endianness test value is 0x87654321. - 0 - 32 - read-only - - - - - DBTP - data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set - 0xc - 32 - 0x00000A33 - 0x009F1FFF - - - TDC - transmitter delay compensation enable -0= Transmitter Delay Compensation disabled -1= Transmitter Delay Compensation enabled - 23 - 1 - read-write - - - DBRP - Data Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. -When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 5 - read-write - - - DTSEG1 - Data time segment before sample point -Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 5 - read-write - - - DTSEG2 - Data time segment after sample point -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 4 - 4 - read-write - - - DSJW - Data (Re)Synchronization Jump Width -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 0 - 4 - read-write - - - - - TEST - test register - 0x10 - 32 - 0x00000000 - 0x003F3FF0 - - - SVAL - Started Valid -0= Value of TXBNS not valid -1= Value of TXBNS valid - 21 - 1 - read-only - - - TXBNS - Tx Buffer Number Started -Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - 16 - 5 - read-only - - - PVAL - Prepared Valid -0= Value of TXBNP not valid -1= Value of TXBNP valid - 13 - 1 - read-only - - - TXBNP - Tx Buffer Number Prepared -Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - 8 - 5 - read-only - - - RX - Receive Pin -Monitors the actual value of pin m_can_rx -0= The CAN bus is dominant (m_can_rx = ‘0’) -1= The CAN bus is recessive (m_can_rx = ‘1’) - 7 - 1 - read-only - - - TX - Control of Transmit Pin -00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time -01 Sample Point can be monitored at pin m_can_tx -10 Dominant (‘0’) level at pin m_can_tx -11 Recessive (‘1’) at pin m_can_tx - 5 - 2 - read-write - - - LBCK - Loop Back Mode -0= Reset value, Loop Back Mode is disabled -1= Loop Back Mode is enabled - 4 - 1 - read-write - - - - - RWD - ram watchdog - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - WDV - Watchdog Value -Actual Message RAM Watchdog Counter Value. - 8 - 8 - read-only - - - WDC - Watchdog Configuration -Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - 0 - 8 - read-write - - - - - CCCR - CC control register - 0x18 - 32 - 0x00000001 - 0x0000FFFF - - - NISO - Non ISO Operation -If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD -Specification V1.0. -0= CAN FD frame format according to ISO 11898-1:2015 -1= CAN FD frame format according to Bosch CAN FD Specification V1.0 -Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - 15 - 1 - read-write - - - TXP - Transmit Pause -If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after -itself has successfully transmitted a frame (see Section 3.5). -0= Transmit pause disabled -1= Transmit pause enabled - 14 - 1 - read-write - - - EFBI - Edge Filtering during Bus Integration -0= Edge filtering disabled -1= Two consecutive dominant tq required to detect an edge for hard synchronization - 13 - 1 - read-write - - - PXHD - Protocol Exception Handling Disable -0= Protocol exception handling enabled -1= Protocol exception handling disabled -Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - 12 - 1 - read-write - - - WMM - Wide Message Marker -Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. -0= 8-bit Message Marker used -1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - 11 - 1 - read-write - - - UTSU - Use Timestamping Unit -When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. -0= Internal time stamping -1= External time stamping by TSU -Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. -In this case bit UTSU is fixed to zero by synthesis. - 10 - 1 - read-write - - - BRSE - Bit Rate Switch Enable -0= Bit rate switching for transmissions disabled -1= Bit rate switching for transmissions enabled -Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - 9 - 1 - read-write - - - FDOE - FD Operation Enable -0= FD operation disabled -1= FD operation enabled - 8 - 1 - read-write - - - TEST - Test Mode Enable -0= Normal operation, register TEST holds reset values -1= Test Mode, write access to register TEST enabled - 7 - 1 - read-write - - - DAR - Disable Automatic Retransmission -0= Automatic retransmission of messages not transmitted successfully enabled -1= Automatic retransmission disabled - 6 - 1 - read-write - - - MON - Bus Monitoring Mode -Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. -0= Bus Monitoring Mode is disabled -1= Bus Monitoring Mode is enabled - 5 - 1 - read-write - - - CSR - Clock Stop Request -0= No clock stop is requested -1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - 4 - 1 - read-write - - - CSA - Clock Stop Acknowledge -0= No clock stop acknowledged -1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - 3 - 1 - read-only - - - ASM - Restricted Operation Mode -Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. -0= Normal CAN operation -1= Restricted Operation Mode active - 2 - 1 - read-write - - - CCE - Configuration Change Enable -0= The CPU has no write access to the protected configuration registers -1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - 1 - 1 - read-write - - - INIT - Initialization -0= Normal Operation -1= Initialization is started - 0 - 1 - read-write - - - - - NBTP - nominal bit timing and prescaler register - 0x1c - 32 - 0x06000A03 - 0xFFFFFF7F - - - NSJW - Nominal (Re)Synchronization Jump Width -Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 25 - 7 - read-write - - - NBRP - Nominal Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is -such that one more than the value programmed here is used. - 16 - 9 - read-write - - - NTSEG1 - Nominal Time segment before sample point -Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 8 - read-write - - - NTSEG2 - Nominal Time segment after sample point -Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 0 - 7 - read-write - - - - - TSCC - timestamp counter configuration - 0x20 - 32 - 0x00000000 - 0x000F0003 - - - TCP - Timestamp Counter Prescaler -Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 4 - read-write - - - TSS - timestamp Select -00= Timestamp counter value always 0x0000 -01= Timestamp counter value incremented according to TCP -10= External timestamp counter value used -11= Same as “00” - 0 - 2 - read-write - - - - - TSCV - timestamp counter value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - TSC - Timestamp Counter -The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - 0 - 16 - read-only - - - - - TOCC - timeout counter configuration - 0x28 - 32 - 0xFFFF0000 - 0xFFFF0007 - - - TOP - Timeout Period -Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - 16 - 16 - read-write - - - TOS - Timeout Select -When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. -When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. -00= Continuous operation -01= Timeout controlled by Tx Event FIFO -10= Timeout controlled by Rx FIFO 0 -11= Timeout controlled by Rx FIFO 1 - 1 - 2 - read-write - - - RP - Enable Timeout Counter -0= Timeout Counter disabled -1= Timeout Counter enabled - 0 - 1 - read-write - - - - - TOCV - timeout counter value - 0x2c - 32 - 0x0000FFFF - 0x0000FFFF - - - TOC - Timeout Counter -The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. -Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - 0 - 16 - read-only - - - - - ECR - error counter register - 0x40 - 32 - 0x00000000 - 0x00FFFFFF - - - CEL - CAN Error Logging -The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. -The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. -The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. -Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - 16 - 8 - read-only - - - RP - Receive Error Passive -0= The Receive Error Counter is below the error passive level of 128 -1= The Receive Error Counter has reached the error passive level of 128 - 15 - 1 - read-only - - - REC - Receive Error Counter -Actual state of the Receive Error Counter, values between 0 and 127 - 8 - 7 - read-only - - - TEC - Transmit Error Counter -Actual state of the Transmit Error Counter, values between 0 and 255 -Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - 0 - 8 - read-only - - - - - PSR - protocol status register - 0x44 - 32 - 0x00000707 - 0x007F7FFF - - - TDCV - Transmitter Delay Compensation Value -Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. -The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - 16 - 7 - read-only - - - PXE - Protocol Exception Event -0= No protocol exception event occurred since last read access -1= Protocol exception event occurred -Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - 14 - 1 - read-only - - - RFDF - Received a CAN FD Message -This bit is set independent of acceptance filtering. -0= Since this bit was reset by the CPU, no CAN FD message has been received -1= Message in CAN FD format with FDF flag set has been received -Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - 13 - 1 - read-only - - - RBRS - BRS flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its BRS flag set -1= Last received CAN FD message had its BRS flag set -Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - 12 - 1 - read-only - - - RESI - ESI flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its ESI flag set -1= Last received CAN FD message had its ESI flag set -Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - 11 - 1 - read-only - - - DLEC - Data Phase Last Error Code -Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with -its BRS flag set has been transferred (reception or transmission) without error. -Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - 8 - 3 - read-only - - - BO - Bus_Off Status -0= The M_CAN is not Bus_Off -1= The M_CAN is in Bus_Off state - 7 - 1 - read-only - - - EW - Warning Status -0= Both error counters are below the Error_Warning limit of 96 -1= At least one of error counter has reached the Error_Warning limit of 96 - 6 - 1 - read-only - - - EP - Error Passive -0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected -1= The M_CAN is in the Error_Passive state - 5 - 1 - read-only - - - ACT - Activity -Monitors the module’s CAN communication state. -00= Synchronizing - node is synchronizing on CAN communication -01= Idle - node is neither receiver nor transmitter -10= Receiver - node is operating as receiver -11= Transmitter - node is operating as transmitter -Note: ACT is set to “00” by a Protocol Exception Event. - 3 - 2 - read-only - - - LEC - Last Error Code -The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. -0= No Error: No error occurred since LEC has been reset by successful reception or transmission. -1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. -2= Form Error: A fixed format part of a received frame has the wrong format. -3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. -4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), -the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus -value was dominant. -5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at -dominant or continuously disturbed). -6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. -7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. -Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. -Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. -At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, -enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. -Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - 0 - 3 - read-only - - - - - TDCR - transmitter delay compensation - 0x48 - 32 - 0x00000000 - 0x00007F7F - - - TDCO - Transmitter Delay Compensation SSP Offset -Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - 8 - 7 - read-write - - - TDCF - Transmitter Delay Compensation Filter Window Length -Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. -The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - 0 - 7 - read-write - - - - - IR - interrupt register - 0x50 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARA - Access to Reserved Address -0= No access to reserved address occurred -1= Access to reserved address occurred - 29 - 1 - read-write - - - PED - Protocol Error in Data Phase (Data Bit Time is used) -0= No protocol error in data phase -1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - 28 - 1 - read-write - - - PEA - Protocol Error in Arbitration Phase (Nominal Bit Time is used) -0= No protocol error in arbitration phase -1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - 27 - 1 - read-write - - - WDI - Watchdog Interrupt -0= No Message RAM Watchdog event occurred -1= Message RAM Watchdog event due to missing READY - 26 - 1 - read-write - - - BO - Bus_Off Status -0= Bus_Off status unchanged -1= Bus_Off status changed - 25 - 1 - read-write - - - EW - Warning Status -0= Error_Warning status unchanged -1= Error_Warning status changed - 24 - 1 - read-write - - - EP - Error Passive -0= Error_Passive status unchanged -1= Error_Passive status changed - 23 - 1 - read-write - - - ELO - Error Logging Overflow -0= CAN Error Logging Counter did not overflow -1= Overflow of CAN Error Logging Counter occurred - 22 - 1 - read-write - - - BEU - Bit Error Uncorrected -Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. -An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. -0= No bit error detected when reading from Message RAM -1= Bit error detected, uncorrected (e.g. parity logic) - 21 - 1 - read-write - - - BEC - Bit Error Corrected -Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. -0= No bit error detected when reading from Message RAM -1= Bit error detected and corrected (e.g. ECC) - 20 - 1 - read-write - - - DRX - Message stored to Dedicated Rx Buffer -The flag is set whenever a received message has been stored into a dedicated Rx Buffer. -0= No Rx Buffer updated -1= At least one received message stored into an Rx Buffer - 19 - 1 - read-write - - - TOO - Timeout Occurred -0= No timeout -1= Timeout reached - 18 - 1 - read-write - - - MRAF - Message RAM Access Failure -The flag is set, when the Rx Handler -.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message -storage is aborted and the Rx Handler starts processing of the following message. -.was not able to write a message to the Message RAM. In this case message storage is aborted. -In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. -The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the -M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. -0= No Message RAM access failure occurred -1= Message RAM access failure occurred - 17 - 1 - read-write - - - TSW - Timestamp Wraparound -0= No timestamp counter wrap-around -1= Timestamp counter wrapped around - 16 - 1 - read-write - - - TEFL - Tx Event FIFO Element Lost -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - 15 - 1 - read-write - - - TEFF - Tx Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 14 - 1 - read-write - - - TEFW - Tx Event FIFO Watermark Reached -0= Tx Event FIFO fill level below watermark -1= Tx Event FIFO fill level reached watermark - 13 - 1 - read-write - - - TEFN - Tx Event FIFO New Entry -0= Tx Event FIFO unchanged -1= Tx Handler wrote Tx Event FIFO element - 12 - 1 - read-write - - - TFE - Tx FIFO Empty -0= Tx FIFO non-empty -1= Tx FIFO empty - 11 - 1 - read-write - - - TCF - Transmission Cancellation Finished -0= No transmission cancellation finished -1= Transmission cancellation finished - 10 - 1 - read-write - - - TC - Transmission Completed -0= No transmission completed -1= Transmission completed - 9 - 1 - read-write - - - HPM - High Priority Message -0= No high priority message received -1= High priority message received - 8 - 1 - read-write - - - RF1L - Rx FIFO 1 Message Lost -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - 7 - 1 - read-write - - - RF1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 6 - 1 - read-write - - - RF1W - Rx FIFO 1 Watermark Reached -0= Rx FIFO 1 fill level below watermark -1= Rx FIFO 1 fill level reached watermark - 5 - 1 - read-write - - - RF1N - Rx FIFO 1 New Message -0= No new message written to Rx FIFO 1 -1= New message written to Rx FIFO 1 - 4 - 1 - read-write - - - RF0L - Rx FIFO 0 Message Lost -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - 3 - 1 - read-write - - - RF0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 2 - 1 - read-write - - - RF0W - Rx FIFO 0 Watermark Reached -0= Rx FIFO 0 fill level below watermark -1= Rx FIFO 0 fill level reached watermark - 1 - 1 - read-write - - - RF0N - Rx FIFO 0 New Message -0= No new message written to Rx FIFO 0 -1= New message written to Rx FIFO 0 - 0 - 1 - read-write - - - - - IE - interrupt enable - 0x54 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAE - Access to Reserved Address Enable - 29 - 1 - read-write - - - PEDE - Protocol Error in Data Phase Enable - 28 - 1 - read-write - - - PEAE - Protocol Error in Arbitration Phase Enable - 27 - 1 - read-write - - - WDIE - Watchdog Interrupt Enable - 26 - 1 - read-write - - - BOE - Bus_Off Status Interrupt Enable - 25 - 1 - read-write - - - EWE - Warning Status Interrupt Enable - 24 - 1 - read-write - - - EPE - Error Passive Interrupt Enable - 23 - 1 - read-write - - - ELOE - Error Logging Overflow Interrupt Enable - 22 - 1 - read-write - - - BEUE - Bit Error Uncorrected Interrupt Enable - 21 - 1 - read-write - - - BECE - Bit Error Corrected Interrupt Enable - 20 - 1 - read-write - - - DRXE - Message stored to Dedicated Rx Buffer Interrupt Enable - 19 - 1 - read-write - - - TOOE - Timeout Occurred Interrupt Enable - 18 - 1 - read-write - - - MRAFE - Message RAM Access Failure Interrupt Enable - 17 - 1 - read-write - - - TSWE - Timestamp Wraparound Interrupt Enable - 16 - 1 - read-write - - - TEFLE - Tx Event FIFO Event Lost Interrupt Enable - 15 - 1 - read-write - - - TEFFE - Tx Event FIFO Full Interrupt Enable - 14 - 1 - read-write - - - TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - 13 - 1 - read-write - - - TEFNE - Tx Event FIFO New Entry Interrupt Enable - 12 - 1 - read-write - - - TFEE - Tx FIFO Empty Interrupt Enable - 11 - 1 - read-write - - - TCFE - Transmission Cancellation Finished Interrupt Enable - 10 - 1 - read-write - - - TCE - Transmission Completed Interrupt Enable - 9 - 1 - read-write - - - HPME - High Priority Message Interrupt Enable - 8 - 1 - read-write - - - RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - 7 - 1 - read-write - - - RF1FE - Rx FIFO 1 Full Interrupt Enable - 6 - 1 - read-write - - - RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - 5 - 1 - read-write - - - RF1NE - Rx FIFO 1 New Message Interrupt Enable - 4 - 1 - read-write - - - RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - 3 - 1 - read-write - - - RF0FE - Rx FIFO 0 Full Interrupt Enable - 2 - 1 - read-write - - - RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - 1 - 1 - read-write - - - RF0NE - Rx FIFO 0 New Message Interrupt Enable - 0 - 1 - read-write - - - - - ILS - interrupt line select - 0x58 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAL - Access to Reserved Address Line - 29 - 1 - read-write - - - PEDL - Protocol Error in Data Phase Line - 28 - 1 - read-write - - - PEAL - Protocol Error in Arbitration Phase Line - 27 - 1 - read-write - - - WDIL - Watchdog Interrupt Line - 26 - 1 - read-write - - - BOL - Bus_Off Status Interrupt Line - 25 - 1 - read-write - - - EWL - Warning Status Interrupt Line - 24 - 1 - read-write - - - EPL - Error Passive Interrupt Line - 23 - 1 - read-write - - - ELOL - Error Logging Overflow Interrupt Line - 22 - 1 - read-write - - - BEUL - Bit Error Uncorrected Interrupt Line - 21 - 1 - read-write - - - BECL - Bit Error Corrected Interrupt Line - 20 - 1 - read-write - - - DRXL - Message stored to Dedicated Rx Buffer Interrupt Line - 19 - 1 - read-write - - - TOOL - Timeout Occurred Interrupt Line - 18 - 1 - read-write - - - MRAFL - Message RAM Access Failure Interrupt Line - 17 - 1 - read-write - - - TSWL - Timestamp Wraparound Interrupt Line - 16 - 1 - read-write - - - TEFLL - Tx Event FIFO Event Lost Interrupt Line - 15 - 1 - read-write - - - TEFFL - Tx Event FIFO Full Interrupt Line - 14 - 1 - read-write - - - TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - 13 - 1 - read-write - - - TEFNL - Tx Event FIFO New Entry Interrupt Line - 12 - 1 - read-write - - - TFEL - Tx FIFO Empty Interrupt Line - 11 - 1 - read-write - - - TCFL - Transmission Cancellation Finished Interrupt Line - 10 - 1 - read-write - - - TCL - Transmission Completed Interrupt Line - 9 - 1 - read-write - - - HPML - High Priority Message Interrupt Line - 8 - 1 - read-write - - - RF1LL - Rx FIFO 1 Message Lost Interrupt Line - 7 - 1 - read-write - - - RF1FL - Rx FIFO 1 Full Interrupt Line - 6 - 1 - read-write - - - RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - 5 - 1 - read-write - - - RF1NL - Rx FIFO 1 New Message Interrupt Line - 4 - 1 - read-write - - - RF0LL - Rx FIFO 0 Message Lost Interrupt Line - 3 - 1 - read-write - - - RF0FL - Rx FIFO 0 Full Interrupt Line - 2 - 1 - read-write - - - RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - 1 - 1 - read-write - - - RF0NL - Rx FIFO 0 New Message Interrupt Line - 0 - 1 - read-write - - - - - ILE - interrupt line enable - 0x5c - 32 - 0x00000000 - 0x00000003 - - - EINT1 - Enable Interrupt Line 1 -0= Interrupt line m_can_int1 disabled -1= Interrupt line m_can_int1 enabled - 1 - 1 - read-write - - - EINT0 - Enable Interrupt Line 0 -0= Interrupt line m_can_int0 disabled -1= Interrupt line m_can_int0 enabled - 0 - 1 - read-write - - - - - GFC - global filter configuration - 0x80 - 32 - 0x00000000 - 0x0000003F - - - ANFS - Accept Non-matching Frames Standard -Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 4 - 2 - read-write - - - ANFE - Accept Non-matching Frames Extended -Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 2 - 2 - read-write - - - RRFS - Reject Remote Frames Standard -0= Filter remote frames with 11-bit standard IDs -1= Reject all remote frames with 11-bit standard IDs - 1 - 1 - read-write - - - RRFE - Reject Remote Frames Extended -0= Filter remote frames with 29-bit extended IDs -1= Reject all remote frames with 29-bit extended IDs - 0 - 1 - read-write - - - - - SIDFC - standard ID filter configuration - 0x84 - 32 - 0x00000000 - 0x00FFFFFC - - - LSS - List Size Standard -0= No standard Message ID filter -1-128= Number of standard Message ID filter elements ->128= Values greater than 128 are interpreted as 128 - 16 - 8 - read-write - - - FLSSA - Filter List Standard Start Address -Start address of standard Message ID filter list (32-bit word address) - 2 - 14 - read-write - - - - - XIDFC - extended ID filter configuration - 0x88 - 32 - 0x00000000 - 0x007FFFFC - - - LSE - List Size Extended -0= No extended Message ID filter -1-64= Number of extended Message ID filter elements ->64= Values greater than 64 are interpreted as 64 - 16 - 7 - read-write - - - FLESA - Filter List Extended Start Address -Start address of extended Message ID filter list (32-bit word address). - 2 - 14 - read-write - - - - - XIDAM - extended id and mask - 0x90 - 32 - 0x1FFFFFFF - 0x1FFFFFFF - - - EIDM - Extended ID Mask -For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - 0 - 29 - read-write - - - - - HPMS - high priority message status - 0x94 - 32 - 0x00000000 - 0x0000FFFF - - - FLST - Filter List -Indicates the filter list of the matching filter element. -0= Standard Filter List -1= Extended Filter List - 15 - 1 - read-only - - - FIDX - Filter Index -Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - 8 - 7 - read-only - - - MSI - Message Storage Indicator -00= No FIFO selected -01= FIFO message lost -10= Message stored in FIFO 0 -11= Message stored in FIFO 1 - 6 - 2 - read-only - - - BIDX - Buffer Index -Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - 0 - 6 - read-only - - - - - NDAT1 - new data1 - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - ND1 - New Data[31:0] -The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - NDAT2 - new data2 - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - ND2 - New Data[63:32] -The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - RXF0C - rx fifo 0 configuration - 0xa0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F0OM - FIFO 0 Operation Mode -FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 0 blocking mode -1= FIFO 0 overwrite mode - 31 - 1 - read-write - - - F0WM - Rx FIFO 0 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F0S - Rx FIFO 0 Size -0= No Rx FIFO 0 -1-64= Number of Rx FIFO 0 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 0 elements are indexed from 0 to F0S-1 - 16 - 7 - read-write - - - F0SA - Rx FIFO 0 Start Address -Start address of Rx FIFO 0 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF0S - rx fifo 0 status - 0xa4 - 32 - 0x00000000 - 0x033F3F7F - - - RF0L - Rx FIFO 0 Message Lost -This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero -Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 24 - 1 - read-only - - - F0PI - Rx FIFO 0 Put Index -Rx FIFO 0 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F0GI - Rx FIFO 0 Get Index -Rx FIFO 0 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F0FL - Rx FIFO 0 Fill Level -Number of elements stored in Rx FIFO 0, range 0 to 64. - 0 - 7 - read-only - - - - - RXF0A - rx fifo0 acknowledge - 0xa8 - 32 - 0x00000000 - 0x0000003F - - - F0AI - Rx FIFO 0 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. -This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - 0 - 6 - read-write - - - - - RXBC - rx buffer configuration - 0xac - 32 - 0x00000000 - 0x0000FFFC - - - RBSA - Rx Buffer Start Address -Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - 2 - 14 - read-write - - - - - RXF1C - rx fifo1 configuration - 0xb0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F1OM - FIFO 1 Operation Mode -FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 1 blocking mode -1= FIFO 1 overwrite mode - 31 - 1 - read-write - - - F1WM - Rx FIFO 1 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F1S - Rx FIFO 1 Size -0= No Rx FIFO 1 -1-64= Number of Rx FIFO 1 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - 16 - 7 - read-write - - - F1SA - Rx FIFO 1 Start Address -Start address of Rx FIFO 1 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF1S - rx fifo1 status - 0xb4 - 32 - 0x00000000 - 0xC33F3F7F - - - DMS - Debug Message Status -00= Idle state, wait for reception of debug messages, DMA request is cleared -01= Debug message A received -10= Debug messages A, B received -11= Debug messages A, B, C received, DMA request is set - 30 - 2 - read-only - - - RF1L - Rx FIFO 1 Message Lost -This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero -Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 24 - 1 - read-only - - - F1PI - Rx FIFO 1 Put Index -Rx FIFO 1 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F1GI - Rx FIFO 1 Get Index -Rx FIFO 1 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F1FL - Rx FIFO 1 Fill Level -Number of elements stored in Rx FIFO 1, range 0 to 64. - 0 - 7 - read-only - - - - - RXF1A - rx fifo 1 acknowledge - 0xb8 - 32 - 0x00000000 - 0x0000003F - - - F1AI - Rx FIFO 1 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. -This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - 0 - 6 - read-write - - - - - RXESC - rx buffer/fifo element size configuration - 0xbc - 32 - 0x00000000 - 0x00000777 - - - RBDS - Rx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 8 - 3 - read-write - - - F1DS - Rx FIFO 1 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 4 - 3 - read-write - - - F0DS - Rx FIFO 0 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, -only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - 0 - 3 - read-write - - - - - TXBC - tx buffer configuration - 0xc0 - 32 - 0x00000000 - 0x7F3FFFFC - - - TFQM - Tx FIFO/Queue Mode -0= Tx FIFO operation -1= Tx Queue operation - 30 - 1 - read-write - - - TFQS - Transmit FIFO/Queue Size -0= No Tx FIFO/Queue -1-32= Number of Tx Buffers used for Tx FIFO/Queue ->32= Values greater than 32 are interpreted as 32 - 24 - 6 - read-write - - - NDTB - Number of Dedicated Transmit Buffers -0= No Dedicated Tx Buffers -1-32= Number of Dedicated Tx Buffers ->32= Values greater than 32 are interpreted as 32 - 16 - 6 - read-write - - - TBSA - Tx Buffers Start Address -Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). -Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - 2 - 14 - read-write - - - - - TXFQS - tx fifo/queue status - 0xc4 - 32 - 0x00000000 - 0x003F1F3F - - - TFQF - Tx FIFO/Queue Full -0= Tx FIFO/Queue not full -1= Tx FIFO/Queue full - 21 - 1 - read-only - - - TFQPI - Tx FIFO/Queue Put Index -Tx FIFO/Queue write index pointer, range 0 to 31. - 16 - 5 - read-only - - - TFGI - Tx FIFO Get Index -Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured -(TXBC.TFQM = ‘1’). - 8 - 5 - read-only - - - TFFL - Tx FIFO Free Level -Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) -Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with -the first dedicated Tx Buffers. -Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - 0 - 6 - read-only - - - - - TXESC - tx buffer element size configuration - 0xc8 - 32 - 0x00000000 - 0x00000007 - - - TBDS - Tx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - 0 - 3 - read-write - - - - - TXBRP - tx buffer request pending - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - TRP - Transmission Request Pending -Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register -TXBCR. -TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the -highest priority (Tx Buffer with lowest Message ID). -A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, -this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. -After a cancellation has been requested, a finished cancellation is signalled via TXBCF -? after successful transmission together with the corresponding TXBTO bit -? when the transmission has not yet been started at the point of cancellation -? when the transmission has been aborted due to lost arbitration -? when an error occurred during frame transmission -In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. -0= No transmission request pending -1= Transmission request pending -Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - 0 - 32 - read-only - - - - - TXBAR - tx buffer add request - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - AR - Add Request -Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx -Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. -When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. -0= No transmission request added -1= Transmission requested added -Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - 0 - 32 - read-write - - - - - TXBCR - tx buffer cancellation request - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR - Cancellation Request -Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. -This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. -0= No cancellation pending -1= Cancellation pending - 0 - 32 - read-write - - - - - TXBTO - tx buffer transmission occurred - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TO - Transmission Occurred -Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmission occurred -1= Transmission occurred - 0 - 32 - read-only - - - - - TXBCF - tx buffer cancellation finished - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - CF - Cancellation Finished -Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. -In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmit buffer cancellation -1= Transmit buffer cancellation finished - 0 - 32 - read-only - - - - - TXBTIE - tx buffer transmission interrupt enable - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIE - Transmission Interrupt Enable -Each Tx Buffer has its own Transmission Interrupt Enable bit. -0= Transmission interrupt disabled -1= Transmission interrupt enable - 0 - 32 - read-write - - - - - TXBCIE - tx buffer cancellation finished interrupt enable - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFIE - Cancellation Finished Interrupt Enable -Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. -0= Cancellation finished interrupt disabled -1= Cancellation finished interrupt enabled - 0 - 32 - read-write - - - - - TXEFC - tx event fifo configuration - 0xf0 - 32 - 0x00000000 - 0x3F3FFFFC - - - EFWM - Event FIFO Watermark -0= Watermark interrupt disabled -1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) ->32= Watermark interrupt disabled - 24 - 6 - read-write - - - EFS - Event FIFO Size -0= Tx Event FIFO disabled -1-32= Number of Tx Event FIFO elements ->32= Values greater than 32 are interpreted as 32 -The Tx Event FIFO elements are indexed from 0 to EFS - 1 - 16 - 6 - read-write - - - EFSA - Event FIFO Start Address -Start address of Tx Event FIFO in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - TXEFS - tx event fifo status - 0xf4 - 32 - 0x00000000 - 0x031F1F3F - - - TEFL - Tx Event FIFO Element Lost -This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - 25 - 1 - read-only - - - EFF - Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 24 - 1 - read-only - - - EFPI - Event FIFO Put Index -Tx Event FIFO write index pointer, range 0 to 31. - 16 - 5 - read-only - - - EFGI - Event FIFO Get Index -Tx Event FIFO read index pointer, range 0 to 31. - 8 - 5 - read-only - - - EFFL - Event FIFO Fill Level -Number of elements stored in Tx Event FIFO, range 0 to 32. - 0 - 6 - read-only - - - - - TXEFA - tx event fifo acknowledge - 0xf8 - 32 - 0x00000000 - 0x0000001F - - - EFAI - Event FIFO Acknowledge Index -After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get -Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - 0 - 5 - read-write - - - - - 16 - 0x4 - TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 - TS_SEL[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - TS - Timestamp Word TS -default can save 16 timestamps with 32bit; -if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - 0 - 32 - read-only - - - - - CREL - core release register - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - REL - Core Release -One digit, BCD-coded - 28 - 4 - read-only - - - STEP - Step of Core Release -One digit, BCD-coded. - 24 - 4 - read-only - - - SUBSTEP - Sub-step of Core Release -One digit, BCD-coded - 20 - 4 - read-only - - - YEAR - Timestamp Year -One digit, BCD-coded. This field is set by generic parameter on -synthesis. - 16 - 4 - read-only - - - MON - Timestamp Month -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 8 - 8 - read-only - - - DAY - Timestamp Day -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 0 - 8 - read-only - - - - - TSCFG - timestamp configuration - 0x244 - 32 - 0x00000000 - 0x0000FF0F - - - TBPRE - Timebase Prescaler -0x00 to 0xFF -The value by which the oscillator frequency is divided for -generating the timebase counter clock. Valid values for the -Timebase Prescaler are 0 to 255. The actual interpretation by -the hardware of this value is such that one more than the value -programmed here is used. Affects only the TSU internal -timebase. When the internal timebase is excluded by synthesis, -TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not -used. - 8 - 8 - read-write - - - EN64 - set to use 64bit timestamp. -when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. -TSP can be used to select different one - 3 - 1 - read-write - - - SCP - Select Capturing Position -0: Capture Timestamp at EOF -1: Capture Timestamp at SOF - 2 - 1 - read-write - - - TBCS - Timebase Counter Select -When the internal timebase is excluded by synthesis, TBCS is -fixed to ‘1’. -0: Timestamp value captured from internal timebase counter, - ATB.TB[31:0] is the internal timbase counter -1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - 1 - 1 - read-write - - - TSUE - Timestamp Unit Enable -0: TSU disabled -1: TSU enabled - 0 - 1 - read-write - - - - - TSS1 - timestamp status1 - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSL - Timestamp Lost -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. -Reading a Timestamp register resets the related bit. - 16 - 16 - read-only - - - TSN - Timestamp New -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related -Timestamp register. Reading a Timestamp register resets the related bit. - 0 - 16 - read-only - - - - - TSS2 - timestamp status2 - 0x24c - 32 - 0x00000000 - 0x0000000F - - - TSP - Timestamp Pointer -The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 -depending on number_ts_g), it is incremented to 0. -Value also signalled on output m_can_tsp[3:0]. - 0 - 4 - read-only - - - - - ATB - actual timebase - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - TB - timebase for timestamp generation 31-0 - 0 - 32 - read-only - - - - - ATBH - actual timebase high - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBH - timebase for timestamp generation 63-32 - 0 - 32 - read-only - - - - - GLB_CTL - global control - 0x400 - 32 - 0x00000000 - 0xE0000003 - - - M_CAN_STBY - m_can standby control - 31 - 1 - read-write - - - STBY_CLR_EN - m_can standby clear control -0:controlled by software by standby bit[bit31] -1:auto clear standby by hardware when rx data is 0 - 30 - 1 - read-write - - - STBY_POL - standby polarity selection - 29 - 1 - read-write - - - TSU_TBIN_SEL - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - 0 - 2 - read-write - - - - - GLB_STATUS - global status - 0x404 - 32 - 0x00000000 - 0x0000000C - - - M_CAN_INT1 - m_can interrupt status1 - 3 - 1 - read-only - - - M_CAN_INT0 - m_can interrupt status0 - 2 - 1 - read-only - - - - - 640 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511,512,513,514,515,516,517,518,519,520,521,522,523,524,525,526,527,528,529,530,531,532,533,534,535,536,537,538,539,540,541,542,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,564,565,566,567,568,569,570,571,572,573,574,575,576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639 - MESSAGE_BUFF[%s] - no description available - 0x2000 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - m_can message buffer - 0 - 32 - read-write - - - - - - - MCAN1 - MCAN1 - MCAN - 0xf0084000 - - - MCAN2 - MCAN2 - MCAN - 0xf0088000 - - - MCAN3 - MCAN3 - MCAN - 0xf008c000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - Restart - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WrEn - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - St - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - write-only - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - CRC - CRC - CRC - 0xf00b8000 - - 0x0 - 0x200 - registers - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - pre_set - &index0 pre set for crc setting - 0x0 - 32 - 0x00000000 - 0x000000FF - - - PRE_SET - 0: no pre set -1: CRC32 -2: CRC32-AUTOSAR -3: CRC16-CCITT -4: CRC16-XMODEM -5: CRC16-MODBUS -1: CRC32 -2: CRC32-autosar -3: CRC16-ccitt -4: CRC16-xmodem -5: CRC16-modbus -6: crc16_dnp -7: crc16_x25 -8: crc16_usb -9: crc16_maxim -10: crc16_ibm -11: crc8_maxim -12: crc8_rohc -13: crc8_itu -14: crc8 -15: crc5_usb - 0 - 8 - read-write - - - - - clr - chn&index0 clear crc result and setting - 0x4 - 32 - 0x00000000 - 0x00000001 - - - CLR - write 1 to clr crc setting and result for its channel. -always read 0. - 0 - 1 - read-write - - - - - poly - chn&index0 poly - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - poly setting - 0 - 32 - read-write - - - - - init_data - chn&index0 init_data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INIT_DATA - initial data of CRC - 0 - 32 - read-write - - - - - xorout - chn&index0 xorout - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XOROUT - XOR for CRC result - 0 - 32 - read-write - - - - - misc_setting - chn&index0 misc_setting - 0x14 - 32 - 0x00000000 - 0x0101013F - - - BYTE_REV - 0: no wrap input byte order -1: wrap input byte order - 24 - 1 - read-write - - - REV_OUT - 0: no wrap output bit order -1: wrap output bit order - 16 - 1 - read-write - - - REV_IN - 0: no wrap input bit order -1: wrap input bit order - 8 - 1 - read-write - - - POLY_WIDTH - crc data length - 0 - 6 - read-write - - - - - data - chn&index0 data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data for crc - 0 - 32 - read-write - - - - - result - chn&index0 result - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - crc result - 0 - 32 - read-write - - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - 16 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x4 - 0x13c - registers - - - - IDMisc - ID Misc - 0x4 - 32 - 0x00000000 - 0x00008000 - - - IDLE_FLAG - DMA Idle Flag -0 - DMA is busy -1 - DMA is dile - 15 - 1 - read-only - - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - IntStatus - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - write-only - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - write-only - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 8 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel n Control Register - 0x0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel n Transfer Size Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - SrcAddr - Channel n Source Address Low Part Register - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - SrcAddrH - Channel n Source Address High Part Register - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - DstAddr - Channel n Destination Address Low Part Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - DstAddrH - Channel n Destination Address High Part Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - LLPointer - Channel n Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - LLPointerH - Channel n Linked List Pointer High Part Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x428 - registers - - - - unlk - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, -otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - sta - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - - - sta_hrpwm - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFF00 - - - STA - No description available - 8 - 24 - read-write - - - - - rld - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - - - rld_hrpwm - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - No description available - 8 - 24 - read-write - - - RLD_HR - pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. - 0 - 8 - read-write - - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CMP[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, -and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CMP_HRPWM[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - No description available - 8 - 24 - read-write - - - CMP_HR - high resolution compare value - 0 - 8 - read-write - - - - - frcmd - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0-7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - shlk - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, write access is not permitted - 31 - 1 - read-write - - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CHCFG[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - - - gcr - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFFF - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as compare shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. -This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. -User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - HR_PWM_EN - set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. - 4 - 1 - read-write - - - TIMERRESET - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear - 3 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - write-only - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - shcr - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x0000FFFF - - - CNT_UPDATE_RELOAD - set to update counter working register at reload point, clear to use cnt_update_time as old version. - 15 - 1 - read-write - - - CNT_UPDATE_EDGE - 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers - 14 - 1 - read-write - - - FORCE_UPDATE_EDGE - 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers - 13 - 1 - read-write - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CAPPOS[%s] - no description available - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - cnt - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CAPNEG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - cntcopy - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - PWMCFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x3FFFFFFF - - - HR_UPDATE_MODE - 0: update the hr value for the first edge at reload point; -1: update the hr value for the first edge at the last edge; -all others will be updated at previous edge -for pair mode, only pwm_cfg 0/2/4/6 are used - 29 - 1 - read-write - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - sr - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - write-only - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - write-only - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - write-only - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - write-only - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - write-only - - - - - irqen - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - dmaen - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - 16 - 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CMPCFG[%s] - no description available - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - ANASTS[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x80000000 - - - CALON - calibration status. -will be set by hardware after setting cal_start. -cleared after calibration finished - 31 - 1 - read-only - - - - - hrpwm_cfg - hrpwm config register - 0x420 - 32 - 0x00000000 - 0x0000FFFF - - - CAL_SW_EN - software calibration enable, internal use only - 8 - 8 - read-write - - - CAL_START - calibration start. -software setting this bit to start calibration process. -each bit for one channel. - 0 - 8 - write-only - - - - - ana_cfg0 - analog config register - 0x424 - 32 - 0x00000000 - 0x00010000 - - - CAL_SW_TRIG_H - No description available - 16 - 1 - read-write - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - PWM2 - PWM2 - PWM - 0xf0220000 - - - PWM3 - PWM3 - PWM - 0xf0230000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x88 - registers - - - - cr - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - uvwcfg - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - trgoen - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - dmaen - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - w - W counter - 0x0 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - v - V counter - 0x4 - 32 - 0x00000000 - 0xCFFFFFFF - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - u - U counter - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - - 3 - 0x8 - u,v,w - HIS[%s] - no description available - 0x70 - - his0 - history register 0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - his1 - history register 1 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - HALL2 - HALL2 - HALL - 0xf0224000 - - - HALL3 - HALL3 - HALL - 0xf0234000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - 4 - 0x4 - spdhis0,spdhis1,spdhis2,spdhis3 - SPDHIS[%s] - no description available - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - QEI2 - QEI2 - QEI - 0xf0228000 - - - QEI3 - QEI3 - QEI - 0xf0238000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - 20 - 0x4 - PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - 67 - 0x4 - TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PLA_IN0,PLA_IN1,PLA_IN2,PLA_IN3,PLA_IN4,PLA_IN5,PLA_IN6,PLA_IN7,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,rsv51,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,DAC_BUF_TRIG,DAC0_STEP_TRIG,DAC1_STEP_TRIG,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP,SDFM_EVT0,SDFM_EVT1,SDFM_EVT2,SDFM_EVT3 - TRGOCFG[%s] - no description available - 0x100 - 32 - 0x00000000 - 0x000003FF - - - OUTINV - 1- Invert the output - 9 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 8 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 7 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 7 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - DMACFG[%s] - no description available - 0x300 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - TRGM2 - TRGM2 - TRGM - 0xf022c000 - - - TRGM3 - TRGM3 - TRGM - 0xf023c000 - - - PLA0 - PLA0 - PLA - 0xf020e000 - - 0x0 - 0x420 - registers - - - - 8 - 0x70 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - 8 - 0x4 - AOI_16to8_00,AOI_16to8_01,AOI_16to8_02,AOI_16to8_03,AOI_16to8_04,AOI_16to8_05,AOI_16to8_06,AOI_16to8_07 - AOI_16TO8[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - AOI_16TO8_15 - select value for AOI_16to8_15. -0: 0. -1: 1st_filter_out[15]. -2: ~1st_filter_out[15]. -3: 1 - 30 - 2 - read-write - - - AOI_16TO8_14 - select value for AOI_16to8_14. -0: 0. -1: 1st_filter_out[14]. -2: ~1st_filter_out[14]. -3: 1 - 28 - 2 - read-write - - - AOI_16TO8_13 - select value for AOI_16to8_13. -0: 0. -1: 1st_filter_out[13]. -2: ~1st_filter_out[13]. -3: 1 - 26 - 2 - read-write - - - AOI_16TO8_12 - select value for AOI_16to8_12. -0: 0. -1: 1st_filter_out[12]. -2: ~1st_filter_out[12]. -3: 1 - 24 - 2 - read-write - - - AOI_16TO8_11 - select value for AOI_16to8_11. -0: 0. -1: 1st_filter_out[11]. -2: ~1st_filter_out[11]. -3: 1 - 22 - 2 - read-write - - - AOI_16TO8_10 - select value for AOI_16to8_10. -0: 0. -1: 1st_filter_out[10]. -2: ~1st_filter_out[10]. -3: 1 - 20 - 2 - read-write - - - AOI_16TO8_9 - select value for AOI_16to8_9. -0: 0. -1: 1st_filter_out[9]. -2: ~1st_filter_out[9]. -3: 1 - 18 - 2 - read-write - - - AOI_16TO8_8 - select value for AOI_16to8_8. -0: 0. -1: 1st_filter_out[8]. -2: ~1st_filter_out[8]. -3: 1 - 16 - 2 - read-write - - - AOI_16TO8_7 - select value for AOI_16to8_7. -0: 0. -1: 1st_filter_out[7]. -2: ~1st_filter_out[7]. -3: 1 - 14 - 2 - read-write - - - AOI_16TO8_6 - select value for AOI_16to8_6. -0: 0. -1: 1st_filter_out[6]. -2: ~1st_filter_out[6]. -3: 1 - 12 - 2 - read-write - - - AOI_16TO8_5 - select value for AOI_16to8_5. -0: 0. -1: 1st_filter_out[5]. -2: ~1st_filter_out[5]. -3: 1 - 10 - 2 - read-write - - - AOI_16TO8_4 - select value for AOI_16to8_4. -0: 0. -1: 1st_filter_out[4]. -2: ~1st_filter_out[4]. -3: 1 - 8 - 2 - read-write - - - AOI_16TO8_3 - select value for AOI_16to8_3. -0: 0. -1: 1st_filter_out[3]. -2: ~1st_filter_out[3]. -3: 1 - 6 - 2 - read-write - - - AOI_16TO8_2 - select value for AOI_16to8_2. -0: 0. -1: 1st_filter_out[2]. -2: ~1st_filter_out[2]. -3: 1 - 4 - 2 - read-write - - - AOI_16TO8_1 - select value for AOI_16to8_1. -0: 0. -1: 1st_filter_out[1]. -2: ~1st_filter_out[1]. -3: 1 - 2 - 2 - read-write - - - AOI_16TO8_0 - select value for AOI_16to8_0. -0: 0. -1: 1st_filter_out[0]. -2: ~1st_filter_out[0]. -3: 1 - 0 - 2 - read-write - - - - - AOI_8to7_00_01 - CHN&index0 AOI_16to8_00_01 OR logic cfg - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - AOI_8TO7_01_7 - select value for AOI_8to7_01_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 30 - 2 - read-write - - - AOI_8TO7_01_6 - select value for AOI_8to7_01_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 28 - 2 - read-write - - - AOI_8TO7_01_5 - select value for AOI_8to7_01_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 26 - 2 - read-write - - - AOI_8TO7_01_4 - select value for AOI_8to7_01_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 24 - 2 - read-write - - - AOI_8TO7_01_3 - select value for AOI_8to7_01_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 22 - 2 - read-write - - - AOI_8TO7_01_2 - select value for AOI_8to7_01_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 20 - 2 - read-write - - - AOI_8TO7_01_1 - select value for AOI_8to7_01_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 18 - 2 - read-write - - - AOI_8TO7_01_0 - select value for AOI_8to7_01_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 16 - 2 - read-write - - - AOI_8TO7_00_7 - select value for AOI_8to7_00_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 14 - 2 - read-write - - - AOI_8TO7_00_6 - select value for AOI_8to7_00_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 12 - 2 - read-write - - - AOI_8TO7_00_5 - select value for AOI_8to7_00_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 10 - 2 - read-write - - - AOI_8TO7_00_4 - select value for AOI_8to7_00_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 8 - 2 - read-write - - - AOI_8TO7_00_3 - select value for AOI_8to7_00_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 6 - 2 - read-write - - - AOI_8TO7_00_2 - select value for AOI_8to7_00_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 4 - 2 - read-write - - - AOI_8TO7_00_1 - select value for AOI_8to7_00_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 2 - 2 - read-write - - - AOI_8TO7_00_0 - select value for AOI_8to7_00_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 0 - 2 - read-write - - - - - AOI_8to7_02_03 - CHN&index0 AOI_16to8_02_03 OR logic cfg - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - AOI_8TO7_03_7 - select value for AOI_8to7_03_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 30 - 2 - read-write - - - AOI_8TO7_03_6 - select value for AOI_8to7_03_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 28 - 2 - read-write - - - AOI_8TO7_03_5 - select value for AOI_8to7_03_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 26 - 2 - read-write - - - AOI_8TO7_03_4 - select value for AOI_8to7_03_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 24 - 2 - read-write - - - AOI_8TO7_03_3 - select value for AOI_8to7_03_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 22 - 2 - read-write - - - AOI_8TO7_03_2 - select value for AOI_8to7_03_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 20 - 2 - read-write - - - AOI_8TO7_03_1 - select value for AOI_8to7_03_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 18 - 2 - read-write - - - AOI_8TO7_03_0 - select value for AOI_8to7_03_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 16 - 2 - read-write - - - AOI_8TO7_02_7 - select value for AOI_8to7_02_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 14 - 2 - read-write - - - AOI_8TO7_02_6 - select value for AOI_8to7_02_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 12 - 2 - read-write - - - AOI_8TO7_02_5 - select value for AOI_8to7_02_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 10 - 2 - read-write - - - AOI_8TO7_02_4 - select value for AOI_8to7_02_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 8 - 2 - read-write - - - AOI_8TO7_02_3 - select value for AOI_8to7_02_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 6 - 2 - read-write - - - AOI_8TO7_02_2 - select value for AOI_8to7_02_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 4 - 2 - read-write - - - AOI_8TO7_02_1 - select value for AOI_8to7_02_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 2 - 2 - read-write - - - AOI_8TO7_02_0 - select value for AOI_8to7_02_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 0 - 2 - read-write - - - - - AOI_8to7_04_05 - CHN&index0 AOI_16to8_04_05 OR logic cfg - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - AOI_8TO7_05_7 - select value for AOI_8to7_05_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 30 - 2 - read-write - - - AOI_8TO7_05_6 - select value for AOI_8to7_05_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 28 - 2 - read-write - - - AOI_8TO7_05_5 - select value for AOI_8to7_05_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 26 - 2 - read-write - - - AOI_8TO7_05_4 - select value for AOI_8to7_05_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 24 - 2 - read-write - - - AOI_8TO7_05_3 - select value for AOI_8to7_05_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 22 - 2 - read-write - - - AOI_8TO7_05_2 - select value for AOI_8to7_05_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 20 - 2 - read-write - - - AOI_8TO7_05_1 - select value for AOI_8to7_05_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 18 - 2 - read-write - - - AOI_8TO7_05_0 - select value for AOI_8to7_05_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 16 - 2 - read-write - - - AOI_8TO7_04_7 - select value for AOI_8to7_04_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 14 - 2 - read-write - - - AOI_8TO7_04_6 - select value for AOI_8to7_04_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 12 - 2 - read-write - - - AOI_8TO7_04_5 - select value for AOI_8to7_04_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 10 - 2 - read-write - - - AOI_8TO7_04_4 - select value for AOI_8to7_04_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 8 - 2 - read-write - - - AOI_8TO7_04_3 - select value for AOI_8to7_04_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 6 - 2 - read-write - - - AOI_8TO7_04_2 - select value for AOI_8to7_04_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 4 - 2 - read-write - - - AOI_8TO7_04_1 - select value for AOI_8to7_04_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 2 - 2 - read-write - - - AOI_8TO7_04_0 - select value for AOI_8to7_04_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 0 - 2 - read-write - - - - - AOI_8to7_06 - CHN&index0 AOI_16to8_06 OR logic cfg - 0x2c - 32 - 0x00000000 - 0x0000FFFF - - - AOI_8TO7_06_7 - select value for AOI_8to7_06_7. -0: 0. -1: 2nd_filter_out[7]. -2: ~2nd_filter_out[7]. -3: 1 - 14 - 2 - read-write - - - AOI_8TO7_06_6 - select value for AOI_8to7_06_6. -0: 0. -1: 2nd_filter_out[6]. -2: ~2nd_filter_out[6]. -3: 1 - 12 - 2 - read-write - - - AOI_8TO7_06_5 - select value for AOI_8to7_06_5. -0: 0. -1: 2nd_filter_out[5]. -2: ~2nd_filter_out[5]. -3: 1 - 10 - 2 - read-write - - - AOI_8TO7_06_4 - select value for AOI_8to7_06_4. -0: 0. -1: 2nd_filter_out[4]. -2: ~2nd_filter_out[4]. -3: 1 - 8 - 2 - read-write - - - AOI_8TO7_06_3 - select value for AOI_8to7_06_3. -0: 0. -1: 2nd_filter_out[3]. -2: ~2nd_filter_out[3]. -3: 1 - 6 - 2 - read-write - - - AOI_8TO7_06_2 - select value for AOI_8to7_06_2. -0: 0. -1: 2nd_filter_out[2]. -2: ~2nd_filter_out[2]. -3: 1 - 4 - 2 - read-write - - - AOI_8TO7_06_1 - select value for AOI_8to7_06_1. -0: 0. -1: 2nd_filter_out[1]. -2: ~2nd_filter_out[1]. -3: 1 - 2 - 2 - read-write - - - AOI_8TO7_06_0 - select value for AOI_8to7_06_0. -0: 0. -1: 2nd_filter_out[0]. -2: ~2nd_filter_out[0]. -3: 1 - 0 - 2 - read-write - - - - - 8 - 0x4 - SECOND_FILTER_0,SECOND_FILTER_1,SECOND_FILTER_2,SECOND_FILTER_3,SECOND_FILTER_4,SECOND_FILTER_5,SECOND_FILTER_6,SECOND_FILTER_7 - FILTER_2ND[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFF71FF - - - FILTER_EXT_COUNTER - filter_ext counter value, cycles for filter or extent by system clock。 -0：0*apb_clk_period -1：1*apb_clk_period -2: 2*apb_clk_period -… -65535: 65535*apb_clk_period - 16 - 16 - read-write - - - FILTER_EXT_TYPE - filter extend type. -0-3：nothing to do. -4： input high level extend. -5： input low level extend. -6： output extend. -7： input pulse extend. - 12 - 3 - read-write - - - FILTER_EXT_ENABLE - filter extend enable. -0. bypass filter extend. all setting in bit31:12 are inactive -1. enable filter extend, all setting in bit31:12 are active. - 8 - 1 - read-write - - - FILTER_SYNC_LEVEL - synchroniser level. -0: 2 level sync. -1: 3 level sync - 7 - 1 - read-write - - - POSE_EDGE_DECT_ENABLE - pose edge detector enable. -0: disable. -1: enable. - 6 - 1 - read-write - - - NEGE_EDGE_DECT_ENABLE - nege edge detector enable. -0: disable. -1: enable. - 5 - 1 - read-write - - - EDGE_DECT_ENABLE - edge detector enable. -0: disable. bit6/bit5 setting inactive. -1: enable. bit6/bit5 setting active. - 4 - 1 - read-write - - - FILTER_REVERSE - reverse sync and edge detector filter's output. -0: not reverse. -1: reverse. - 3 - 1 - read-write - - - SOFTWARE_INJECT - software inject value for sync and edge detector filter. -0: inject low level. -1: inject high level. -2: not inject. -3. inject high level. - 1 - 2 - read-write - - - SYNC_EDGE_FILTER_ENABLE - sync and edge detector filter. -0: disable. -1: enable. - 0 - 1 - read-write - - - - - 7 - 0x4 - THIRD_FILTER_0,THIRD_FILTER_1,THIRD_FILTER_2,THIRD_FILTER_3,THIRD_FILTER_4,THIRD_FILTER_5,THIRD_FILTER_6 - FILTER_3RD[%s] - no description available - 0x50 - 32 - 0x00000000 - 0xFFFF71FF - - - FILTER_EXT_COUNTER - filter_ext counter value, cycles for filter or extent by system clock。 -0：0*apb_clk_period -1：1*apb_clk_period -2: 2*apb_clk_period -… -65535: 65535*apb_clk_period - 16 - 16 - read-write - - - FILTER_EXT_TYPE - filter extend type. -0-3：nothing to do. -4： input high level extend. -5： input low level extend. -6： output extend. -7： input pulse extend. - 12 - 3 - read-write - - - FILTER_EXT_ENABLE - filter extend enable. -0. bypass filter extend. all setting in bit31:12 are inactive -1. enable filter extend, all setting in bit31:12 are active. - 8 - 1 - read-write - - - FILTER_SYNC_LEVEL - synchroniser level. -0: 2 level sync. -1: 3 level sync - 7 - 1 - read-write - - - POSE_EDGE_DECT_ENABLE - pose edge detector enable. -0: disable. -1: enable. - 6 - 1 - read-write - - - NEGE_EDGE_DECT_ENABLE - nege edge detector enable. -0: disable. -1: enable. - 5 - 1 - read-write - - - EDGE_DECT_ENABLE - edge detector enable. -0: disable. bit6/bit5 setting inactive. -1: enable. bit6/bit5 setting active. - 4 - 1 - read-write - - - FILTER_REVERSE - reverse sync and edge detector filter's output. -0: not reverse. -1: reverse. - 3 - 1 - read-write - - - SOFTWARE_INJECT - software inject value for sync and edge detector filter. -0: inject low level. -1: inject high level. -2: not inject. -3. inject high level. - 1 - 2 - read-write - - - SYNC_EDGE_FILTER_ENABLE - sync and edge detector filter. -0: disable. -1: enable. - 0 - 1 - read-write - - - - - CFG_FF - CHN&index0 cfg ff - 0x6c - 32 - 0x00000000 - 0x0003001F - - - OSC_LOOP_CLAMP_VALUE - osc loop clamp value when osc ring active. -0: clamp 0. -1: clamp 1. - 17 - 1 - read-write - - - DIS_OSC_LOOP_CLAMP - disable osc loop clamp. -0: enable osc loop clamp when osc ring active. -1: disable or clean current osc loop clamp. - 16 - 1 - read-write - - - SEL_ADDER_MINUS - 0: select adder when cfg_adder_minus active. -1: select minus when cfg_adder_minus active. - 4 - 1 - read-write - - - SEL_CLK_SOURCE - cfg_ff clock source. -0: system clock. -1: use 3rd_filter_2 as clock. - 3 - 1 - read-write - - - SEL_CFG_FF_TYPE - cfg_ff type. -0: DFF. -1: 3rd_filter_0. -2: dual-edge DFF. -3: Trigger FF. -4: JK FF. -5. latch. -6: full adder/minus. - 0 - 3 - read-write - - - - - - 8 - 0x4 - FRIST_FILTER_PLA_IN_0,FRIST_FILTER_PLA_IN_1,FRIST_FILTER_PLA_IN_2,FRIST_FILTER_PLA_IN_3,FRIST_FILTER_PLA_IN_4,FRIST_FILTER_PLA_IN_5,FRIST_FILTER_PLA_IN_6,FRIST_FILTER_PLA_IN_7 - FILTER_1ST_PLA_IN[%s] - no description available - 0x3c0 - 32 - 0x00000000 - 0xFFFF71FF - - - FILTER_EXT_COUNTER - filter_ext counter value, cycles for filter or extent by system clock。 -0：0*apb_clk_period -1：1*apb_clk_period -2: 2*apb_clk_period -… -65535: 65535*apb_clk_period - 16 - 16 - read-write - - - FILTER_EXT_TYPE - filter extend type. -0-3：nothing to do. -4： input high level extend. -5： input low level extend. -6： output extend. -7： input pulse extend. - 12 - 3 - read-write - - - FILTER_EXT_ENABLE - filter extend enable. -0. bypass filter extend. all setting in bit31:12 are inactive -1. enable filter extend, all setting in bit31:12 are active. - 8 - 1 - read-write - - - FILTER_SYNC_LEVEL - synchroniser level. -0: 2 level sync. -1: 3 level sync - 7 - 1 - read-write - - - POSE_EDGE_DECT_ENABLE - pose edge detector enable. -0: disable. -1: enable. - 6 - 1 - read-write - - - NEGE_EDGE_DECT_ENABLE - nege edge detector enable. -0: disable. -1: enable. - 5 - 1 - read-write - - - EDGE_DECT_ENABLE - edge detector enable. -0: disable. bit6/bit5 setting inactive. -1: enable. bit6/bit5 setting active. - 4 - 1 - read-write - - - FILTER_REVERSE - reverse sync and edge detector filter's output. -0: not reverse. -1: reverse. - 3 - 1 - read-write - - - SOFTWARE_INJECT - software inject value for sync and edge detector filter. -0: inject low level. -1: inject high level. -2: not inject. -3. inject high level. - 1 - 2 - read-write - - - SYNC_EDGE_FILTER_ENABLE - sync and edge detector filter. -0: disable. -1: enable. - 0 - 1 - read-write - - - - - 9 - 0x4 - FRIST_FILTER_PLA_IN_0,FRIST_FILTER_PLA_OUT_0,FRIST_FILTER_PLA_OUT_1,FRIST_FILTER_PLA_OUT_2,FRIST_FILTER_PLA_OUT_3,FRIST_FILTER_PLA_OUT_4,FRIST_FILTER_PLA_OUT_5,FRIST_FILTER_PLA_OUT_6,FRIST_FILTER_PLA_OUT_7 - FILTER_1ST_PLA_OUT[%s] - no description available - 0x3e0 - 32 - 0x00000000 - 0xFFFF71FF - - - FILTER_EXT_COUNTER - filter_ext counter value, cycles for filter or extent by system clock。 -0：0*apb_clk_period -1：1*apb_clk_period -2: 2*apb_clk_period -… -65535: 65535*apb_clk_period - 16 - 16 - read-write - - - FILTER_EXT_TYPE - filter extend type. -0-3：nothing to do. -4： input high level extend. -5： input low level extend. -6： output extend. -7： input pulse extend. - 12 - 3 - read-write - - - FILTER_EXT_ENABLE - filter extend enable. -0. bypass filter extend. all setting in bit31:12 are inactive -1. enable filter extend, all setting in bit31:12 are active. - 8 - 1 - read-write - - - FILTER_SYNC_LEVEL - synchroniser level. -0: 2 level sync. -1: 3 level sync - 7 - 1 - read-write - - - POSE_EDGE_DECT_ENABLE - pose edge detector enable. -0: disable. -1: enable. - 6 - 1 - read-write - - - NEGE_EDGE_DECT_ENABLE - nege edge detector enable. -0: disable. -1: enable. - 5 - 1 - read-write - - - EDGE_DECT_ENABLE - edge detector enable. -0: disable. bit6/bit5 setting inactive. -1: enable. bit6/bit5 setting active. - 4 - 1 - read-write - - - FILTER_REVERSE - reverse sync and edge detector filter's output. -0: not reverse. -1: reverse. - 3 - 1 - read-write - - - SOFTWARE_INJECT - software inject value for sync and edge detector filter. -0: inject low level. -1: inject high level. -2: not inject. -3. inject high level. - 1 - 2 - read-write - - - SYNC_EDGE_FILTER_ENABLE - sync and edge detector filter. -0: disable. -1: enable. - 0 - 1 - read-write - - - - - 8 - 0x4 - CFG_ACTIVE_CHN0,CFG_ACTIVE_CHN1,CFG_ACTIVE_CHN2,CFG_ACTIVE_CHN3,CFG_ACTIVE_CHN4,CFG_ACTIVE_CHN5,CFG_ACTIVE_CHN6,CFG_ACTIVE_CHN7 - CHN_CFG_ACTIVE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0000FFFF - - - CFG_ACTIVE - write 0xF00D to enable all setting. Otherwire, all setting inactive. - 0 - 16 - read-write - - - - - - - PLA1 - PLA1 - PLA - 0xf021e000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 8 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - GPTMR0 - GPTMR0 - GPTMR - 0xf3000000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x80007FFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - GPTMR1 - GPTMR1 - GPTMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf300c000 - - - PTMR - PTMR - GPTMR - 0xf40e0000 - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00001E00 - 0x000F9FFF - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - LIN0 - LIN0 - LIN - 0xf3030000 - - 0x0 - 0x40 - registers - - - - 8 - 0x4 - data_byte0,data_byte1,data_byte2,data_byte3,data_byte4,data_byte5,data_byte6,data_byte7 - DATABYTE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x000000FF - - - DATA_BYTE - data byte - 0 - 8 - read-write - - - - - control - control register - 0x20 - 32 - 0x00000000 - 0x000000FF - - - STOP - slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID - 7 - 1 - write-only - - - SLEEP - The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. - 6 - 1 - read-write - - - TRANSMIT - 1: transmit operation 0: receive operation - 5 - 1 - read-write - - - DATA_ACK - slave only. Write 1 after handling a data request interrupt - 4 - 1 - read-write - - - RESET_INT - write 1 to reset the int bit in the status register and the interrupt request output of LIN - 3 - 1 - write-only - - - RESET_ERROR - assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 - 2 - 1 - write-only - - - WAKEUP_REQ - wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core - 1 - 1 - read-write - - - START_REQ - master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred - 0 - 1 - read-write - - - - - state - state register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - LIN_ACTIVE - The bit indicates whether the LIN bus is active or not - 7 - 1 - read-only - - - BUS_IDLE_TV - slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s - 6 - 1 - read-only - - - ABORTED - slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. - 5 - 1 - read-only - - - DATA_REQ - slave only. Sets after receiving the identifier and requests an interrupt to the host controller. - 4 - 1 - read-only - - - INT - set when request an interrupt. Reset by reset_int - 3 - 1 - read-only - - - ERROR - set when detecte an error, clear by reset_error - 2 - 1 - read-only - - - WAKEUP - set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 - 1 - 1 - read-only - - - COMPLETE - set after a transmission has been successful finished and it will reset at the start of a transmission. - 0 - 1 - read-only - - - - - error - error register - 0x28 - 32 - 0x00000000 - 0x0000000F - - - PARITY_ERROR - slave only. identifier parity error - 3 - 1 - read-only - - - TIMEOUT - timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms - 2 - 1 - read-only - - - CHK_ERROR - checksum error - 1 - 1 - read-only - - - BIT_ERROR - bit error - 0 - 1 - read-only - - - - - data_len - data lenth register - 0x2c - 32 - 0x00000000 - 0x0000008F - - - ENH_CHECK - 1:enhence check mode - 7 - 1 - read-write - - - DATA_LENGTH - data length - 0 - 4 - read-write - - - - - baudrate_ctl_low - baudrate control low register - 0x30 - 32 - 0x00000000 - 0x000000FF - - - BT_DIV_LOW - bit div register 7:0 - 0 - 8 - read-write - - - - - bardrate_ctl_high - baudrate control high register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - PRESCL - prescl register - 6 - 2 - read-write - - - BT_MUL - bt_mul register - 1 - 5 - read-write - - - BT_DIV_HIGH - bit div register 8 - 0 - 1 - read-write - - - - - id - id register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - ID - id register - 0 - 6 - read-write - - - - - tv - timeout control register - 0x3c - 32 - 0x00000040 - 0x000000CF - - - INITIAL_MODE - initial_mode - 7 - 1 - read-write - - - MASTER_MODE - master_mode - 6 - 1 - read-write - - - BUS_INACTIVITY_TIME - slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s - 2 - 2 - read-write - - - WUP_REPEAT_TIME - slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms - 0 - 2 - read-write - - - - - - - LIN1 - LIN1 - LIN - 0xf3034000 - - - LIN2 - LIN2 - LIN - 0xf3038000 - - - LIN3 - LIN3 - LIN - 0xf303c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x3000 - registers - - - - 134 - 0x4 - cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1,cpx1,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,pow_cpu1,rst_soc,rst_cpu0,rst_cpu1,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_mct1,clk_top_xpi0,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ana4,clk_top_ref0,clk_top_ref1,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_dac1,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbp,axis,axic,lmm0,mct0,lmm1,mct1,rom0,ram0,i2c0,i2c1,i2c2,i2c3,tmr0,tmr1,tmr2,tmr3,gpio,adc0,adc1,adc2,dac0,dac1,acmp,spi0,spi1,spi2,spi3,sdm0,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,lin0,lin1,lin2,lin3,ptpc,can0,can1,can2,can3,wdg0,wdg1,mbx0,mbx1,crc0,mot0,mot1,mot2,mot3,synt,xpi0,hdma,xdma,kman,sdp0,rng0,tsns,usb0,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 3 - 0x10 - link0,link1,link2 - GROUP0[%s] - no description available - 0x800 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 3 - 0x10 - link0,link1,link2 - GROUP1[%s] - no description available - 0x840 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x00000000 - 0x000003FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu0 stop -bit01: soc_ctx is kept on while cpu0 stop -bit02: cpu0_mem is kept on while cpu0 stop -bit03: cpu0_ctx is kept on while cpu0 stop -bit04: cpu1_mem is kept on while cpu0 stop -bit05: cpu1_ctx is kept on while cpu0 stop -bit06: xtal_hold is kept on while cpu0 stop -bit07: pll0_hold is kept on while cpu0 stop -bit08: pll1_hold is kept on while cpu0 stop -bit09: pll2_hold is kept on while cpu0 stop - 0 - 10 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x00000000 - 0x000003FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 10 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x00000000 - 0x000003FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 10 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x00000000 - 0x000003FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 10 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 3 - 0x10 - soc,cpu0,cpu1 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 1 - 0x4 - clk_top_cpu0 - CLOCK_CPU[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xD0FF07FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - SUB1_DIV - ahb bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 20 - 4 - read-write - - - SUB0_DIV - axi bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 16 - 4 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 39 - 0x4 - clk_top_mct0,clk_top_mct1,clk_top_xpi0,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_ana4,clk_top_ref0,clk_top_ref1,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3 - CLOCK[%s] - no description available - 0x1804 - 32 - 0x00000000 - 0xD00007FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 3 - 0x4 - clk_top_adc0,clk_top_adc1,clk_top_adc2 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock N -1: ahb clock - 8 - 1 - read-write - - - - - 2 - 0x4 - clk_top_dac0,clk_top_dac1 - DACCLK[%s] - no description available - 0x1c0c - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock N -1: ahb clock - 8 - 1 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0: clk_32k - 1: clk_irc24m - 2: clk_xtal_24m - 3: clk_usb0_phy - 8: clk0_osc0 - 9: clk0_pll0 - 10: clk1_pll0 - 11: clk2_pll0 - 12: clk0_pll1 - 13: clk1_pll1 - 14: clk0_pll2 - 15: clk1_pll2 -128: clk_top_cpu0 -129: clk_top_mct0 -130: clk_top_mct1 -131: clk_top_xpi0 -132: clk_top_tmr0 -133: clk_top_tmr1 -134: clk_top_tmr2 -135: clk_top_tmr3 -136: clk_top_urt0 -137: clk_top_urt1 -138: clk_top_urt2 -139: clk_top_urt3 -140: clk_top_urt4 -141: clk_top_urt5 -142: clk_top_urt6 -143: clk_top_urt7 -144: clk_top_i2c0 -145: clk_top_i2c1 -146: clk_top_i2c2 -147: clk_top_i2c3 -148: clk_top_spi0 -149: clk_top_spi1 -150: clk_top_spi2 -151: clk_top_spi3 -152: clk_top_can0 -153: clk_top_can1 -154: clk_top_can2 -155: clk_top_can3 -156: clk_top_ptpc -157: clk_top_ana0 -158: clk_top_ana1 -159: clk_top_ana2 -160: clk_top_ana3 -161: clk_top_ana4 -162: clk_top_ref0 -163: clk_top_ref1 -164: clk_top_lin0 -165: clk_top_lin1 -166: clk_top_lin2 -167: clk_top_lin3 - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 2 - 0x400 - cpu0,cpu1 - CPU[%s] - no description available - 0x2800 - - LP - CPU0 LP control - 0x0 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - CPU0 Lock GPR - 0x4 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 4 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 4 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf40 - registers - - - - 488 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,rsv456,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x0001047E - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00000384 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000010 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x03120040 - 0x073F006F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00006E1C - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit0-1: fuse -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000310 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf4100000 - - 0x0 - 0x200 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 3 - 0x80 - pll0,pll1,pll2 - PLL[%s] - no description available - 0x80 - - MFI - PLL0 multiple register - 0x0 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - MFN - PLL0 fraction numerator register - 0x4 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - MFD - PLL0 fraction demoninator register - 0x8 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - SS_STEP - PLL0 spread spectrum step register - 0xc - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - SS_STOP - PLL0 spread spectrum stop register - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - CONFIG - PLL0 confguration register - 0x14 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - LOCKTIME - PLL0 lock time register - 0x18 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - STEPTIME - PLL0 step time register - 0x1c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - ADVANCED - PLL0 advance configuration register - 0x20 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - 3 - 0x4 - DIV0,DIV1,DIV2 - DIV[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - - TSNS - TSNS - TSNS - 0xf4104000 - - 0x0 - 0x3c - registers - - - - T - Temperature - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - Maximum Temperature - 0x4 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - Minimum Temperature - 0x8 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - Sample age - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - Status - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - write-only - - - - - CONFIG - Configuration - 0x14 - 32 - 0x00600300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valid from 24-255, default 96 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, default in 3 -0: measure and return -1: twice and average -2: 4 times and average -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - Sample validity - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - Temperature flag - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - Maximum temperature to interrupt - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - Minimum temperature to interrupt - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - Maximum temperature to reset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - Minimum temperature to reset - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - Configuration in asynchronous mode - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - Polarity of internal comparator - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - Advance configuration - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - BACC - BACC - BACC - 0xf5000000 - - 0x0 - 0x10 - registers - - - - CONFIG - Access timing for access - 0x0 - 32 - 0x00000000 - 0x3000FFFF - - - FAST_WRITE - Use fast write -0: Write normally -1: boost write - 29 - 1 - read-write - - - FAST_READ - Use fast read -0: Read normally -1: boost read - 28 - 1 - read-write - - - TIMING - Time in APB clock cycles, for battery timing penerate - 0 - 16 - read-write - - - - - PRE_TIME - Timing gap before rising edge - 0x8 - 32 - 0x00000000 - 0x000FFFFF - - - PRE_RATIO - Ratio of guard band before rising edge -0: 0 -1: 1/32768 of low level width -2: 1/16384 of low level width -14: 1/4 of low level width -15: 1/2 of low level width - 16 - 4 - read-write - - - PRE_OFFSET - guard band before rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - POST_TIME - Timing gap after rising edge - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - POST_RATIO - Ratio of guard band after rising edge -0: 0 -1: 1/32768 of high level width -2: 1/16384 of high level width -14: 1/4 of high level width -15: 1/2 of high level width - 16 - 4 - read-write - - - POST_OFFSET - guard band after rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LP_MODE - Bandgap works in low power mode -0: not in low power mode -1: bandgap work in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - RTC - RTC - RTC - 0xf5044000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - 4 - 0x10 - tamp0,tamp1,tamp2,tamp3 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/SConscript deleted file mode 100644 index 5717c3e6317..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/SConscript +++ /dev/null @@ -1,25 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_batt_iomux.h deleted file mode 100644 index 9978a0fcaaf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_batt_iomux.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BATT_IOMUX_H -#define HPM_BATT_IOMUX_H - -/* BIOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_BATT_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_BATT_TAMPER_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_SOC_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_BATT_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_BATT_TAMPER_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_SOC_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_BATT_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_BATT_TAMPER_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_SOC_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_BATT_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_BATT_TAMPER_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_SOC_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_BATT_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_BATT_TAMPER_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_SOC_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_BATT_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_BATT_TAMPER_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_SOC_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_BATT_TAMPER_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_SOC_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_BATT_TAMPER_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_SOC_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_bcfg_drv.h deleted file mode 100644 index 00dfb6fcf3c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_bcfg_drv.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BCFG_DRV_H -#define HPM_BCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_bcfg_regs.h" - -/** - * - * @brief BCFG driver APIs - * @defgroup bcfg_interface BCFG driver APIs - * @ingroup io_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable VBAT LP mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; -} - -/** - * @brief disable VBAT LP mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; -} - -/** - * @brief enable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -/** - * @brief disable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BCFG_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_bpor_drv.h deleted file mode 100644 index e37bac24b13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_bpor_drv.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BPOR_DRV_H -#define HPM_BPOR_DRV_H - -#include "hpm_common.h" -#include "hpm_bpor_regs.h" - -/** - * - * @brief BPOR driver APIs - * @defgroup bpor_interface BPOR driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -/** @brief Define BPOR power on cause */ -typedef enum { - bpor_power_on_cause_wbutn = 1 << 0, - bpor_power_on_cause_safety_violation = 1 << 1, - bpor_power_on_cause_rtc_0 = 1 << 2, - bpor_power_on_cause_rtc_1 = 1 << 3, - bpor_power_on_cause_gpio = 1 << 4 -} bpor_power_on_cause_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get power on cause - * - * @param[in] ptr BPOR base address - * @retval POR_CAUSE register value - */ -static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) -{ - return ptr->POR_CAUSE; -} - -/** - * @brief Clear power on cause - * - * @param[in] ptr BPOR base address - * @param[in] mask cause status to be cleared - */ -static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) -{ - ptr->POR_CAUSE |= mask; -} - -/** - * @brief enable power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be enabled - */ -static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) -{ - ptr->POR_SELECT |= cause; -} - -/** - * @brief disable power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be disabled - */ -static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) -{ - ptr->POR_SELECT &= ~cause; -} - -/** - * @brief Set power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be used - */ -static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) -{ - ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; -} - -/** - * @brief Enable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Disable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Set power down counter - * - * @param[in] ptr BPOR base address - * @param[in] counter counter value - */ -static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) -{ - ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_clock_drv.c deleted file mode 100644 index b032b7d0d07..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_clock_drv.c +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_soc.h" -#include "hpm_common.h" -#include "hpm_pllctlv2_drv.h" -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (400000000UL) -#define FREQ_PRESET1_PLL0_CLK1 (333333333UL) -#define FREQ_PRESET1_PLL1_CLK2 (250000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (480000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (320000000UL) -#define FREQ_PRESET1_PLL2_CLK0 (516096000UL) -#define FREQ_PRESET1_PLL2_CLK1 (451584000UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) -#define WDG_INSTANCE_NUM (2U) -#define BUS_FREQ_MAX (200000000UL) -#define FREQ_1MHz (1000000UL) - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ - - - -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for ADC - */ -static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance); - -/** - * @brief Get Clock frequency for DAC - */ -static uint32_t get_frequency_for_dac(uint32_t instance); - -/** - * @brief Get Clock frequency for WDG - */ -static uint32_t get_frequency_for_wdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PWDG - */ -static uint32_t get_frequency_for_pwdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - -static uint32_t get_frequency_for_cpu(void); -static uint32_t get_frequency_for_axi(void); -static uint32_t get_frequency_for_ahb(void); - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ana0, clock_node_ahb, -}; - -static const clock_node_t s_dac_clk_mux_node[] = { - clock_node_ana3, clock_node_ahb -}; - -static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1 }; - -uint32_t hpm_core_clock; - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_adc(CLK_SRC_GROUP_ADC, node_or_instance); - break; - case CLK_SRC_GROUP_DAC: - clk_freq = get_frequency_for_dac(node_or_instance); - break; - case CLK_SRC_GROUP_WDG: - clk_freq = get_frequency_for_wdg(node_or_instance); - break; - case CLK_SRC_GROUP_PWDG: - clk_freq = get_frequency_for_pwdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_CPU0: - clk_freq = get_frequency_for_cpu(); - break; - case CLK_SRC_GROUP_AHB: - clk_freq = get_frequency_for_ahb(); - break; - case CLK_SRC_GROUP_AXI: - clk_freq = get_frequency_for_axi(); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); - break; - case clock_source_pll0_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); - break; - case clock_source_pll0_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); - break; - case clock_source_pll1_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); - break; - case clock_source_pll1_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); - break; - case clock_source_pll2_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); - break; - case clock_source_pll2_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_adc(uint32_t clk_src_type, uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - uint32_t adc_index = instance; - - (void) clk_src_type; - - if (adc_index < ADC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); - if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { - node = s_adc_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node != clock_node_ahb) { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } else { - clk_freq = get_frequency_for_ahb(); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_dac(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - if (instance < DAC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); - if (mux_in_reg < ARRAY_SIZE(s_dac_clk_mux_node)) { - node = s_dac_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node == clock_node_ahb) { - clk_freq = get_frequency_for_ahb(); - } else { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - - return clk_freq; -} - -static uint32_t get_frequency_for_wdg(uint32_t instance) -{ - uint32_t freq_in_hz; - /* EXT clock is chosen */ - if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_ahb(); - } - /* PCLK is chosen */ - else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_pwdg(void) -{ - uint32_t freq_in_hz; - if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_cpu(void) -{ - uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_source(mux) / div); -} - -static uint32_t get_frequency_for_axi(void) -{ - uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_cpu() / div); -} - -static uint32_t get_frequency_for_ahb(void) -{ - uint32_t div = SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_cpu() / div); -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_DAC: - if (node_or_instance < DAC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_DAC; - clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_WDG; - clk_src_index = WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL); - } - break; - case CLK_SRC_GROUP_PWDG: - clk_src_group = CLK_SRC_GROUP_PWDG; - clk_src_index = WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_CPU0: - case CLK_SRC_GROUP_AHB: - case CLK_SRC_GROUP_AXI: - clk_src_group = CLK_SRC_GROUP_CPU0; - clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -uint32_t clock_get_divider(clock_name_t clock_name) -{ - uint32_t clk_divider = CLOCK_DIV_INVALID; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_divider = 1UL; - } - break; - case CLK_SRC_GROUP_PWDG: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_PMIC: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_CPU0: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_AHB: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_AXI: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - default: - clk_divider = CLOCK_DIV_INVALID; - break; - } - return clk_divider; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_dac_src_ana3) || (src > clk_dac_src_ahb0)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->DACCLK[node_or_instance] = - (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_WDG) && (clk_src_grp != CLK_SRC_GROUP_PWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PWDG->CTRL = (HPM_PWDG->CTRL & ~WDG_CTRL_CLKSEL_MASK) | WDG_CTRL_CLKSEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL = (s_wdgs[instance]->CTRL & ~WDG_CTRL_CLKSEL_MASK) | WDG_CTRL_CLKSEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_DAC: - case CLK_SRC_GROUP_WDG: - case CLK_SRC_GROUP_PWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AHB: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_AXI: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_CPU0: - if (node_or_instance == clock_node_cpu0) { - /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency - * changes, the AXI and AHB clock changes accordingly, here the driver ensures the - * AXI and AHB bus clock frequency is in valid range. - */ - uint32_t expected_freq = get_frequency_for_source((clock_source_t) src) / div; - uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, (clock_source_t) src, div, axi_sub_div, ahb_sub_div); - } else { - status = status_clk_shared_cpu0; - } - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t) ticks_per_us * 1000UL * ms; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_update_core_clock(void) -{ - uint32_t hart_id = read_csr(CSR_MHARTID); - clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; - hpm_core_clock = clock_get_frequency(cpu_clk_name); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_clock_drv.h deleted file mode 100644 index 80d7f191022..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_clock_drv.h +++ /dev/null @@ -1,359 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" -#include "hpm_csr_drv.h" - -#define CLOCK_DIV_INVALID (~0UL) - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), - status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), - status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), - status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), - status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), - status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), - status_clk_fixed = MAKE_STATUS(status_group_clk, 10), - -}; - - - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_WDG (3U) -#define CLK_SRC_GROUP_PMIC (4U) -#define CLK_SRC_GROUP_AHB (5U) -#define CLK_SRC_GROUP_AXI (6U) -#define CLK_SRC_GROUP_DAC (7U) -#define CLK_SRC_GROUP_CPU0 (9U) -#define CLK_SRC_GROUP_SRC (10U) -#define CLK_SRC_GROUP_PWDG (11U) -#define CLK_SRC_GROUP_INVALID (15U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - - clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), - clk_dac_src_ana4 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), - clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - - -#define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_CPU0 (0xFFFDU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)(node))) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_CPU0, clock_node_cpu1), - clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), - clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), - clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), - clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), - clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), - clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), - clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), - clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), - clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), - clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), - clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), - - clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), - clock_axi = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AXI, clock_node_axi), - clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_AXI, clock_node_axi), - clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_AXI, clock_node_axi), - clock_ahbp = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_AHB, clock_node_ahb), - - clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), - clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), - clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), - clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), - clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI, 3), - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI, 4), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 3), - clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 4), - clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 5), - clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 6), - clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 7), - clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 8), - clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 9), - clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), - clock_synt = MAKE_CLOCK_NAME(sysctl_resource_synt, CLK_SRC_GROUP_AHB, 11), - clock_sdm0 = MAKE_CLOCK_NAME(sysctl_resource_sdm0, CLK_SRC_GROUP_AHB, 13), - clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AHB, 14), - clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), - clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU0, 1), - clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 2), - - - /* For ADC, there are 2-stage clock source and divider configurations */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), - clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), - clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), - - /* For DAC, there are 2-stage clock source and divider configurations */ - clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), - clock_ana4 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana4), - clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), - clock_dac1 = MAKE_CLOCK_NAME(sysctl_resource_dac1, CLK_SRC_GROUP_DAC, 1), - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), - clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), - clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 6), - clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 7), -} clock_name_t; - -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @param [in] clock_name clock name - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Get the IP clock divider - * Note:This API return the direct clock divider - * @param [in] clock_name clock name - * @return IP clock divider - */ -uint32_t clock_get_divider(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @return #status_success Setting ADC clock source is successful - * #status_clk_invalid Invalid ADC clock - * #status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set DAC clock source - * @param[in] clock_name DAC clock name - * @param[in] src DAC clock source - * - * @return #status_success Setting DAC clock source is successful - * #status_clk_invalid Invalid DAC clock - * #status_clk_src_invalid Invalid DAC clock source - */ -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @return #status_success Setting Clock source and divider is successful. - * #status_clk_src_invalid clock source is invalid. - * #status_clk_fixed clock source and divider is a fixed value - * #status_clk_shared_ahb Clock is shared with the AHB clock - * #status_clk_shared_axi0 Clock is shared with the AXI0 clock - * #status_clk_shared_axi1 CLock is shared with the AXI1 clock - * #status_clk_shared_axi2 Clock is shared with the AXI2 clock - * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_csr_regs.h deleted file mode 100644 index 5f43b12bd1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_csr_regs.h +++ /dev/null @@ -1,6512 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_SSTATUS (0x100) -#define CSR_SEDELEG (0x102) -#define CSR_SIDELEG (0x103) -#define CSR_SIE (0x104) -#define CSR_STVEC (0x105) -#define CSR_SSCRATCH (0x140) -#define CSR_SEPC (0x141) -#define CSR_SCAUSE (0x142) -#define CSR_STVAL (0x143) -#define CSR_SIP (0x144) -#define CSR_SATP (0x180) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MEDELEG (0x302) -#define CSR_MIDELEG (0x303) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_PMACFG0 (0xBC0) -#define CSR_PMACFG1 (0xBC1) -#define CSR_PMACFG2 (0xBC2) -#define CSR_PMACFG3 (0xBC3) -#define CSR_PMAADDR0 (0xBD0) -#define CSR_PMAADDR1 (0xBD1) -#define CSR_PMAADDR2 (0xBD2) -#define CSR_PMAADDR3 (0xBD3) -#define CSR_PMAADDR4 (0xBD4) -#define CSR_PMAADDR5 (0xBD5) -#define CSR_PMAADDR6 (0xBD6) -#define CSR_PMAADDR7 (0xBD7) -#define CSR_PMAADDR8 (0xBD8) -#define CSR_PMAADDR9 (0xBD9) -#define CSR_PMAADDR10 (0xBDA) -#define CSR_PMAADDR11 (0xBDB) -#define CSR_PMAADDR12 (0xBDC) -#define CSR_PMAADDR13 (0xBDD) -#define CSR_PMAADDR14 (0xBDE) -#define CSR_PMAADDR15 (0xBDF) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_SCOUNTEREN (0x106) -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_MSLIDELEG (0x7D5) -#define CSR_MCLK_CTL (0x7DF) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_SLIE (0x9C4) -#define CSR_SLIP (0x9C5) -#define CSR_SDCAUSE (0x9C9) -#define CSR_SCCTLDATA (0x9CD) -#define CSR_SCOUNTERINTEN (0x9CF) -#define CSR_SCOUNTERMASK_M (0x9D1) -#define CSR_SCOUNTERMASK_S (0x9D2) -#define CSR_SCOUNTERMASK_U (0x9D3) -#define CSR_SCOUNTEROVF (0x9D4) -#define CSR_SCOUNTINHIBIT (0x9E0) -#define CSR_SHPMEVENT3 (0x9E3) -#define CSR_SHPMEVENT4 (0x9E4) -#define CSR_SHPMEVENT5 (0x9E5) -#define CSR_SHPMEVENT6 (0x9E6) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: SSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_SSTATUS_SD_MASK (0x80000000UL) -#define CSR_SSTATUS_SD_SHIFT (31U) -#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_SSTATUS_MXR_MASK (0x80000UL) -#define CSR_SSTATUS_MXR_SHIFT (19U) -#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) -#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_SSTATUS_SUM_MASK (0x40000UL) -#define CSR_SSTATUS_SUM_SHIFT (18U) -#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) -#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggeredwhen XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. - * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_XS_MASK (0x18000UL) -#define CSR_SSTATUS_XS_SHIFT (15U) -#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. - * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_FS_MASK (0x6000U) -#define CSR_SSTATUS_FS_SHIFT (13U) -#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) -#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_SSTATUS_SPP_MASK (0x100U) -#define CSR_SSTATUS_SPP_SHIFT (8U) -#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) -#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_SSTATUS_SPIE_MASK (0x20U) -#define CSR_SSTATUS_SPIE_SHIFT (5U) -#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) -#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_SSTATUS_UPIE_MASK (0x10U) -#define CSR_SSTATUS_UPIE_SHIFT (4U) -#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) -#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_SIE_MASK (0x2U) -#define CSR_SSTATUS_SIE_SHIFT (1U) -#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) -#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_UIE_MASK (0x1U) -#define CSR_SSTATUS_UIE_SHIFT (0U) -#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) -#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: SEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SPF_MASK (0x8000U) -#define CSR_SEDELEG_SPF_SHIFT (15U) -#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) -#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LPF_MASK (0x2000U) -#define CSR_SEDELEG_LPF_SHIFT (13U) -#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) -#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IPF_MASK (0x1000U) -#define CSR_SEDELEG_IPF_SHIFT (12U) -#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) -#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_UEC_MASK (0x100U) -#define CSR_SEDELEG_UEC_SHIFT (8U) -#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) -#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAF_MASK (0x80U) -#define CSR_SEDELEG_SAF_SHIFT (7U) -#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) -#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAM_MASK (0x40U) -#define CSR_SEDELEG_SAM_SHIFT (6U) -#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) -#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAF_MASK (0x20U) -#define CSR_SEDELEG_LAF_SHIFT (5U) -#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) -#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAM_MASK (0x10U) -#define CSR_SEDELEG_LAM_SHIFT (4U) -#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) -#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) - -/* - * B (RW) - * - * B indicates whether an exception triggered by breakpoint will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_B_MASK (0x8U) -#define CSR_SEDELEG_B_SHIFT (3U) -#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) -#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_II_MASK (0x4U) -#define CSR_SEDELEG_II_SHIFT (2U) -#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) -#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAF_MASK (0x2U) -#define CSR_SEDELEG_IAF_SHIFT (1U) -#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) -#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAM_MASK (0x1U) -#define CSR_SEDELEG_IAM_SHIFT (0U) -#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) -#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: SIDELEG */ -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UEI_MASK (0x100U) -#define CSR_SIDELEG_UEI_SHIFT (8U) -#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) -#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UTI_MASK (0x10U) -#define CSR_SIDELEG_UTI_SHIFT (4U) -#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) -#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_USI_MASK (0x1U) -#define CSR_SIDELEG_USI_SHIFT (0U) -#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) -#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) - -/* Bitfield definition for register: SIE */ -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SEIE_MASK (0x200U) -#define CSR_SIE_SEIE_SHIFT (9U) -#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) -#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UEIE_MASK (0x100U) -#define CSR_SIE_UEIE_SHIFT (8U) -#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) -#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_STIE_MASK (0x20U) -#define CSR_SIE_STIE_SHIFT (5U) -#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) -#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UTIE_MASK (0x10U) -#define CSR_SIE_UTIE_SHIFT (4U) -#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) -#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SSIE_MASK (0x2U) -#define CSR_SIE_SSIE_SHIFT (1U) -#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) -#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_USIE_MASK (0x1U) -#define CSR_SIE_USIE_SHIFT (0U) -#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) -#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) - -/* Bitfield definition for register: STVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_STVEC_BASE_31_2_SHIFT (2U) -#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) -#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: SSCRATCH */ -/* - * SSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) -#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) -#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) - -/* Bitfield definition for register: SEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_SEPC_EPC_SHIFT (1U) -#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) -#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) - -/* Bitfield definition for register: SCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) -#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 256+16:Slave port ECC error interrupt (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt(S-mode) - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:10:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) -#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: STVAL */ -/* - * STVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) -#define CSR_STVAL_STVAL_SHIFT (0U) -#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) -#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) - -/* Bitfield definition for register: SIP */ -/* - * SEIP (RO) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SEIP_MASK (0x200U) -#define CSR_SIP_SEIP_SHIFT (9U) -#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UEIP_MASK (0x100U) -#define CSR_SIP_UEIP_SHIFT (8U) -#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) -#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) - -/* - * STIP (RO) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_STIP_MASK (0x20U) -#define CSR_SIP_STIP_SHIFT (5U) -#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) - -/* - * UTIP (RO) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UTIP_MASK (0x10U) -#define CSR_SIP_UTIP_SHIFT (4U) -#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SSIP_MASK (0x2U) -#define CSR_SIP_SSIP_SHIFT (1U) -#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) -#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_USIP_MASK (0x1U) -#define CSR_SIP_USIP_SHIFT (0U) -#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) -#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) - -/* Bitfield definition for register: SATP */ -/* - * MODE (RW) - * - * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is - * not supported in the product, this CSR will be - * hardwired to 0. - * 0:No page translation - * 1:Page-based 32-bit virtual addressing - */ -#define CSR_SATP_MODE_MASK (0x80000000UL) -#define CSR_SATP_MODE_SHIFT (31U) -#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) -#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) - -/* - * ASID (RW) - * - * ASID holds the address space identifier. - */ -#define CSR_SATP_ASID_MASK (0x7FC00000UL) -#define CSR_SATP_ASID_SHIFT (22U) -#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) -#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) - -/* - * PPN (RW) - * - * PPN holds the physical page number of the root page table. - */ -#define CSR_SATP_PPN_MASK (0x3FFFFFUL) -#define CSR_SATP_PPN_SHIFT (0U) -#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) -#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * TSR (RW) - * - * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TSR_MASK (0x400000UL) -#define CSR_MSTATUS_TSR_SHIFT (22U) -#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) -#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) - -/* - * TW (RW) - * - * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TW_MASK (0x200000UL) -#define CSR_MSTATUS_TW_SHIFT (21U) -#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) -#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) - -/* - * TVM (RW) - * - * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. - * 0:Normal execution - * 1:Raising exceptions - */ -#define CSR_MSTATUS_TVM_MASK (0x100000UL) -#define CSR_MSTATUS_TVM_SHIFT (20U) -#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) -#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_MSTATUS_SUM_MASK (0x40000UL) -#define CSR_MSTATUS_SUM_SHIFT (18U) -#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) -#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_MSTATUS_SPP_MASK (0x100U) -#define CSR_MSTATUS_SPP_SHIFT (8U) -#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) -#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_MSTATUS_SPIE_MASK (0x20U) -#define CSR_MSTATUS_SPIE_SHIFT (5U) -#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) -#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_SIE_MASK (0x2U) -#define CSR_MSTATUS_SIE_SHIFT (1U) -#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) -#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SPF_MASK (0x8000U) -#define CSR_MEDELEG_SPF_SHIFT (15U) -#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) -#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LPF_MASK (0x2000U) -#define CSR_MEDELEG_LPF_SHIFT (13U) -#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) -#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IPF_MASK (0x1000U) -#define CSR_MEDELEG_IPF_SHIFT (12U) -#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) -#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) - -/* - * SEC (RW) - * - * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SEC_MASK (0x200U) -#define CSR_MEDELEG_SEC_SHIFT (9U) -#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) -#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_UEC_MASK (0x100U) -#define CSR_MEDELEG_UEC_SHIFT (8U) -#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) -#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAF_MASK (0x80U) -#define CSR_MEDELEG_SAF_SHIFT (7U) -#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) -#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAM_MASK (0x40U) -#define CSR_MEDELEG_SAM_SHIFT (6U) -#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) -#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAF_MASK (0x20U) -#define CSR_MEDELEG_LAF_SHIFT (5U) -#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) -#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAM_MASK (0x10U) -#define CSR_MEDELEG_LAM_SHIFT (4U) -#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) -#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_II_MASK (0x4U) -#define CSR_MEDELEG_II_SHIFT (2U) -#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) -#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAF_MASK (0x2U) -#define CSR_MEDELEG_IAF_SHIFT (1U) -#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) -#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAM_MASK (0x1U) -#define CSR_MEDELEG_IAM_SHIFT (0U) -#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) -#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: MIDELEG */ -/* - * SEI (RW) - * - * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SEI_MASK (0x200U) -#define CSR_MIDELEG_SEI_SHIFT (9U) -#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) -#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) - -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UEI_MASK (0x100U) -#define CSR_MIDELEG_UEI_SHIFT (8U) -#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) -#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) - -/* - * STI (RW) - * - * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_STI_MASK (0x20U) -#define CSR_MIDELEG_STI_SHIFT (5U) -#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) -#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UTI_MASK (0x10U) -#define CSR_MIDELEG_UTI_SHIFT (4U) -#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) -#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) - -/* - * SSI (RW) - * - * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SSI_MASK (0x2U) -#define CSR_MIDELEG_SSI_SHIFT (1U) -#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) -#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_USI_MASK (0x1U) -#define CSR_MIDELEG_USI_SHIFT (0U) -#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) -#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SEIE_MASK (0x200U) -#define CSR_MIE_SEIE_SHIFT (9U) -#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) -#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_STIE_MASK (0x20U) -#define CSR_MIE_STIE_SHIFT (5U) -#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) -#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SSIE_MASK (0x2U) -#define CSR_MIE_SSIE_SHIFT (1U) -#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) -#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_MCONTROL_S_MASK (0x10U) -#define CSR_MCONTROL_S_SHIFT (4U) -#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) -#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ICOUNT_S_MASK (0x80U) -#define CSR_ICOUNT_S_SHIFT (7U) -#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) -#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ITRIGGER_S_MASK (0x80U) -#define CSR_ITRIGGER_S_SHIFT (7U) -#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) -#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ETRIGGER_S_MASK (0x80U) -#define CSR_ETRIGGER_S_SHIFT (7U) -#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) -#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKS (RW) - * - * This bit controls the behavior of EBREAK instructions in Supervisor Mode. - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKS_MASK (0x2000U) -#define CSR_DCSR_EBREAKS_SHIFT (13U) -#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) -#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: PMACFG0 */ -/* - * PMA3CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) -#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) -#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) -#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) - -/* - * PMA2CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) -#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) -#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) -#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) - -/* - * PMA1CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) -#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) -#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) -#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) - -/* - * PMA0CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) -#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) -#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) -#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) - -/* Bitfield definition for register: PMACFG1 */ -/* - * PMA7CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) -#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) -#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) -#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) - -/* - * PMA6CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) -#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) -#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) -#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) - -/* - * PMA5CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) -#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) -#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) -#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) - -/* - * PMA4CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) -#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) -#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) -#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) - -/* Bitfield definition for register: PMACFG2 */ -/* - * PMA11CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) -#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) -#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) -#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) - -/* - * PMA10CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) -#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) -#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) -#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) - -/* - * PMA9CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) -#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) -#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) -#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) - -/* - * PMA8CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) -#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) -#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) -#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) - -/* Bitfield definition for register: PMACFG3 */ -/* - * PMA15CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) -#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) -#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) -#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) - -/* - * PMA14CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) -#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) -#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) -#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) - -/* - * PMA13CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) -#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) -#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) -#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) - -/* - * PMA12CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) -#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) -#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) -#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaaaaaaaaaa Reserved - * . . . . . . - * aaaa. . . aa011111111 Reserved - * aaaa. . . a0111111111 2^{12} - * aaaa. . . 01111111111 2^{13} - * . . . . . . - * aa01. . . 11111111111 2^{XLEN} - * a011. . . 11111111111 2^{XLEN+1} - * 0111. . . 11111111111 2^{XLEN+2} - * 1111. . . 11111111111 Reserved - */ -#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) -#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) -#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) -#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) -#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) -#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) -#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) -#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) -#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) -#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) -#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) -#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) -#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) -#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) -#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) -#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) -#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: SCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) -#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) -#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) -#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) -#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_IR_MASK (0x4U) -#define CSR_SCOUNTEREN_IR_SHIFT (2U) -#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) -#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_CY_MASK (0x1U) -#define CSR_SCOUNTEREN_CY_SHIFT (0U) -#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) -#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * PM (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MDCAUSE_PM_MASK (0x60U) -#define CSR_MDCAUSE_PM_SHIFT (5U) -#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) -#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) - -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * DC_WAROUND (RW) - * - * Cache Write-Around threshold - * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. - * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. - * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. - * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. - */ -#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) -#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) -#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) -#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) - -/* - * DC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) - -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * DPREF_EN (RW) - * - * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 - * 0:Disable hardware prefetch on load/store memory accesses - * 1:Enable hardware prefetch on load/store memory accesses - */ -#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) -#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) -#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) -#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) - -/* - * IPREF_EN (RW) - * - * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 - * 0:Disable hardware prefetch on instruction fetches - * 1:Enable hardware prefetch on instruction fetches - */ -#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) -#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) -#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) -#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * NBLD_EN (RW) - * - * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. - * 0:Load to memory regions are blocking. - * 1:Load to memory regions are non-blocking. - */ -#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) -#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) -#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) -#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) - -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: MSLIDELEG */ -/* - * PMOVI (RW) - * - * Delegate S-mode performance monitor overflow local interrupt to S-mode. - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) -#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) -#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) -#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Delegate S-mode bus read/write transaction error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) -#define CSR_MSLIDELEG_BWEI_SHIFT (17U) -#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) -#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Delegate S-mode slave-port ECC error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) -#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) -#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) -#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) - -/* Bitfield definition for register: MCLK_CTL */ -/* - * FUNIT (RW) - * - * Level 2 clock gating enable for function units listed in the following table. - * 16:integer arithmetic unit - * 17:integer permutation unit - * 18:integer mask unit - * 19:integer division unit - * 20:integer multiply and add unit - * 21:floating-point multiply and add - * unit - * 22:floating-point miscellaneous unit - * 23:floating-point division unit - * 24:load/store unit - * 31:25:Reserved - */ -#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) -#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) -#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) -#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) - -/* - * VI (RW) - * - * Level 1 clock gating enable for the vector/floating-point issue queues. - */ -#define CSR_MCLK_CTL_VI_MASK (0x8000U) -#define CSR_MCLK_CTL_VI_SHIFT (15U) -#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) -#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) - -/* - * VR (RW) - * - * Level 1 clock gating enable for the vector/floating-point register file. - */ -#define CSR_MCLK_CTL_VR_MASK (0x4000U) -#define CSR_MCLK_CTL_VR_SHIFT (14U) -#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) -#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) - -/* - * AQ (RW) - * - * Level 1 clock gating enable for ACE load/store queues. - */ -#define CSR_MCLK_CTL_AQ_MASK (0x2000U) -#define CSR_MCLK_CTL_AQ_SHIFT (13U) -#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) -#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) - -/* - * DQ (RW) - * - * Level 1 clock gating enable for data cache load/store queues. - */ -#define CSR_MCLK_CTL_DQ_MASK (0x1000U) -#define CSR_MCLK_CTL_DQ_SHIFT (12U) -#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) -#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) - -/* - * UQ (RW) - * - * Level 1 clock gating enable for uncached queues - */ -#define CSR_MCLK_CTL_UQ_MASK (0x800U) -#define CSR_MCLK_CTL_UQ_SHIFT (11U) -#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) -#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) - -/* - * FP (RW) - * - * Level 1 clock gating enable for scalar floating point issue unit and queues. - */ -#define CSR_MCLK_CTL_FP_MASK (0x400U) -#define CSR_MCLK_CTL_FP_SHIFT (10U) -#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) -#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) - -/* - * CLKGATE (RW) - * - * One-hot clock gating levels. - * 0:Level 1 clock gating in module level - * 1:Level 2 clock gating in unit level - * 2:Level 3 clock gating in VPU level - * 7:3:Reserved - */ -#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) -#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) -#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) -#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * SPF (RW) - * - * Indicates whether store page fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) -#define CSR_DEXC2DBG_SPF_SHIFT (18U) -#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) -#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) - -/* - * LPF (RW) - * - * Indicates whether load fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) -#define CSR_DEXC2DBG_LPF_SHIFT (17U) -#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) -#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) - -/* - * IPF (RW) - * - * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) -#define CSR_DEXC2DBG_IPF_SHIFT (16U) -#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) -#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * SEC (RW) - * - * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SEC_MASK (0x200U) -#define CSR_DEXC2DBG_SEC_SHIFT (9U) -#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) -#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: SLIE */ -/* - * PMOVI (RW) - * - * Enable S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_PMOVI_MASK (0x40000UL) -#define CSR_SLIE_PMOVI_SHIFT (18U) -#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) -#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_BWEI_MASK (0x20000UL) -#define CSR_SLIE_BWEI_SHIFT (17U) -#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) -#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Enable S-mode slave-port ECC error local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_IMECCI_MASK (0x10000UL) -#define CSR_SLIE_IMECCI_SHIFT (16U) -#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) -#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) - -/* Bitfield definition for register: SLIP */ -/* - * PMOVI (RW) - * - * Pending control and status of S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_PMOVI_MASK (0x40000UL) -#define CSR_SLIP_PMOVI_SHIFT (18U) -#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) -#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_BWEI_MASK (0x20000UL) -#define CSR_SLIP_BWEI_SHIFT (17U) -#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) -#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Pending control and status of S-mode slave-port ECC error local interrupt.. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_IMECCI_MASK (0x10000UL) -#define CSR_SLIP_IMECCI_SHIFT (16U) -#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) -#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) - -/* Bitfield definition for register: SDCAUSE */ -/* - * PM (RW) - * - * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0:User mode - * 1:Supervisor mode - * 2:Reserved - * 3:Machine mode - */ -#define CSR_SDCAUSE_PM_MASK (0x60U) -#define CSR_SDCAUSE_PM_SHIFT (5U) -#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) -#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) - -/* - * SDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. - * The value of SDCAUSE for precise exception: - * When scause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When scause == 2 (Illegal instruction): - * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When scause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When scause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of SDCAUSE for imprecise exception: - * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) -#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) -#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) -#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) - -/* Bitfield definition for register: SCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_SCCTLDATA_VA_MASK (0x1FU) -#define CSR_SCCTLDATA_VA_SHIFT (0U) -#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) -#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: SCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) -#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) -#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) -#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) -#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) -#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) -#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) -#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) -#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) -#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) -#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) -#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) -#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) -#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) -#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) -#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) -#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) -#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) -#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) -#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) -#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) -#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) -#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) -#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) -#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) -#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) -#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) -#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) -#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_IR_MASK (0x4U) -#define CSR_SCOUNTEROVF_IR_SHIFT (2U) -#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) -#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_CY_MASK (0x1U) -#define CSR_SCOUNTEROVF_CY_SHIFT (0U) -#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) -#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) -#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) -#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) -#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) -#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) -#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) -#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) -#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: SHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT3_SEL_SHIFT (4U) -#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) -#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) -#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT4_SEL_SHIFT (4U) -#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) -#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) -#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT5_SEL_SHIFT (4U) -#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) -#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) -#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT6_SEL_SHIFT (4U) -#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) -#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) -#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_dmamux_src.h deleted file mode 100644 index c2a15b87f6f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_dmamux_src.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_SPI0_RX (0x0UL) -#define HPM_DMA_SRC_SPI0_TX (0x1UL) -#define HPM_DMA_SRC_SPI1_RX (0x2UL) -#define HPM_DMA_SRC_SPI1_TX (0x3UL) -#define HPM_DMA_SRC_SPI2_RX (0x4UL) -#define HPM_DMA_SRC_SPI2_TX (0x5UL) -#define HPM_DMA_SRC_SPI3_RX (0x6UL) -#define HPM_DMA_SRC_SPI3_TX (0x7UL) -#define HPM_DMA_SRC_UART0_RX (0x8UL) -#define HPM_DMA_SRC_UART0_TX (0x9UL) -#define HPM_DMA_SRC_UART1_RX (0xAUL) -#define HPM_DMA_SRC_UART1_TX (0xBUL) -#define HPM_DMA_SRC_UART2_RX (0xCUL) -#define HPM_DMA_SRC_UART2_TX (0xDUL) -#define HPM_DMA_SRC_UART3_RX (0xEUL) -#define HPM_DMA_SRC_UART3_TX (0xFUL) -#define HPM_DMA_SRC_UART4_RX (0x10UL) -#define HPM_DMA_SRC_UART4_TX (0x11UL) -#define HPM_DMA_SRC_UART5_RX (0x12UL) -#define HPM_DMA_SRC_UART5_TX (0x13UL) -#define HPM_DMA_SRC_UART6_RX (0x14UL) -#define HPM_DMA_SRC_UART6_TX (0x15UL) -#define HPM_DMA_SRC_UART7_RX (0x16UL) -#define HPM_DMA_SRC_UART7_TX (0x17UL) -#define HPM_DMA_SRC_MOT0_0 (0x18UL) -#define HPM_DMA_SRC_MOT0_1 (0x19UL) -#define HPM_DMA_SRC_MOT0_2 (0x1AUL) -#define HPM_DMA_SRC_MOT0_3 (0x1BUL) -#define HPM_DMA_SRC_MOT1_0 (0x1CUL) -#define HPM_DMA_SRC_MOT1_1 (0x1DUL) -#define HPM_DMA_SRC_MOT1_2 (0x1EUL) -#define HPM_DMA_SRC_MOT1_3 (0x1FUL) -#define HPM_DMA_SRC_MOT2_0 (0x20UL) -#define HPM_DMA_SRC_MOT2_1 (0x21UL) -#define HPM_DMA_SRC_MOT2_2 (0x22UL) -#define HPM_DMA_SRC_MOT2_3 (0x23UL) -#define HPM_DMA_SRC_MOT3_0 (0x24UL) -#define HPM_DMA_SRC_MOT3_1 (0x25UL) -#define HPM_DMA_SRC_MOT3_2 (0x26UL) -#define HPM_DMA_SRC_MOT3_3 (0x27UL) -#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) -#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) -#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) -#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) -#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) -#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) -#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) -#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) -#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) -#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) -#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) -#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) -#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) -#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) -#define HPM_DMA_SRC_I2C0 (0x38UL) -#define HPM_DMA_SRC_I2C1 (0x39UL) -#define HPM_DMA_SRC_I2C2 (0x3AUL) -#define HPM_DMA_SRC_I2C3 (0x3BUL) -#define HPM_DMA_SRC_XPI0_RX (0x3CUL) -#define HPM_DMA_SRC_XPI0_TX (0x3DUL) -#define HPM_DMA_SRC_DAC0 (0x3EUL) -#define HPM_DMA_SRC_DAC1 (0x3FUL) -#define HPM_DMA_SRC_ACMP_0 (0x40UL) -#define HPM_DMA_SRC_ACMP_1 (0x41UL) -#define HPM_DMA_SRC_ACMP_2 (0x42UL) -#define HPM_DMA_SRC_ACMP_3 (0x43UL) -#define HPM_DMA_SRC_MCAN0 (0x44UL) -#define HPM_DMA_SRC_MCAN1 (0x45UL) -#define HPM_DMA_SRC_MCAN2 (0x46UL) -#define HPM_DMA_SRC_MCAN3 (0x47UL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_gpiom_soc_drv.h deleted file mode 100644 index 92d909f9537..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_soc_gpio1 = 1, - gpiom_core0_fast = 2, - gpiom_core1_fast = 3, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_interrupt.h deleted file mode 100644 index 57c7e86b1e4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_interrupt.h +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Delegate IRQ handling - * - * @param[in] mask interrupt mask to be delegated - */ -ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) -{ - set_csr(CSR_MIDELEG, mask); -} - -/** - * @brief Undelegate IRQ handling - * - * @param[in] mask interrupt mask to be undelegated - */ -ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) -{ - clear_csr(CSR_MIDELEG, mask); -} - - -/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ - -/** - * @brief Enable global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return sstatus for supervisor mode - * - * @param[in] mask interrupt mask to be disabled - * @retval current sstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) -{ - set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ for supervisor mode - */ -ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) -{ - set_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) -{ - clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - - - -/* Supervisor mode */ - -/** - * @brief Enable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) -{ - set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Disable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Trigger software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) -{ - set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - - -/** - * @brief Complete software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) -{ - clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - -/* - * @brief Enable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Disable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -#define intc_set_s_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) - -/* - * @brief Complete IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Claim IRQ for supervisor mode - * - */ -#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) - -/* - * @brief Enable IRQ for supervisor mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_s_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_s_enable_irq(irq); \ - } while (0) - - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* Supervisor mode */ -extern int __vector_s_table[]; -extern void default_s_irq_entry(void); -/** - * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) -{ - __vector_s_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) -{ - __vector_s_table[irq] = (int) default_s_irq_entry; -} - - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else /*__riscv_flen == 64*/ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - - -#define ENTER_NESTED_IRQ_HANDLING_S() {\ - __asm volatile("\n\ - csrr s2, sepc \n\ - csrr s3, sstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi sstatus, 2"); \ -} -#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("csrci sstatus, 2"); \ - __asm volatile("lui a4, 0xe4201"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling at supervisor mode - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * SCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * SSTATUS = word offset 18 - */ -#define EXIT_NESTED_IRQ_HANDLING_S() { \ - __asm volatile("\n\ - csrw sstatus, s3 \n\ - csrw sepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define EXTERN_C extern "C" -#else -#define EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -#define ISR_NAME_S(irq_num) default_isr_s_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void ISR_NAME_S(irq_num)(void) {\ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_S();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_S(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_S();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("sret\n");\ -} - -#endif -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) { \ - isr(); \ -} - -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_S(irq_num)(void) { \ - isr(); \ -} - -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) {\ - isr();\ -} - -/* Supervisor mode */ - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_s_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR_S(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_s_isr(void) {\ - isr();\ -} - -#define CSR_MSTATUS_MPP_S_MODE (0x1) -#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ -do { \ - if (label) { \ - write_csr(mepc, label); \ - } \ - clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ - set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ -} while(0) - -typedef void (*s_mode_entry)(void); - -/** - * @brief Switch mode to supervisor from machine - * - * @param[in] entry - entry point after mode is switched - */ -static inline void switch_to_s_mode(s_mode_entry entry) -{ - write_csr(CSR_SEPC, entry); - MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); - if (entry) { - __asm("mret"); - } -} -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_iomux.h deleted file mode 100644 index 8b8ab423802..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_iomux.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA00_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA00_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA01_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA01_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA02_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA02_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA03_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA03_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA04_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA04_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA05_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA05_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA06_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA06_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA06_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA07_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA07_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA07_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA08_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA08_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA09_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA09_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA10_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA10_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA10_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA11_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA11_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA11_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA12_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA12_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA12_FUNC_CTL_TRGM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA13_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA13_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA13_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA13_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA14_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA14_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA14_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA15_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA15_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA15_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA16_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA16_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA17_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA17_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA18_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA18_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA19_FUNC_CTL_TRGM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA20_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA20_FUNC_CTL_PWM3_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA21_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA21_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA21_FUNC_CTL_PWM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA22_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA22_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA22_FUNC_CTL_PWM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA23_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA23_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA23_FUNC_CTL_PWM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA24_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA24_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA24_FUNC_CTL_PWM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA25_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA25_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA25_FUNC_CTL_PWM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA26_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA26_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA26_FUNC_CTL_PWM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA27_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA27_FUNC_CTL_PWM3_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA28_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA28_FUNC_CTL_TRGM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA29_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA29_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA29_FUNC_CTL_TRGM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA30_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA30_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA30_FUNC_CTL_TRGM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PA31_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA31_FUNC_CTL_TRGM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB00_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB00_FUNC_CTL_TRGM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB01_FUNC_CTL_TRGM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB02_FUNC_CTL_TRGM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB03_FUNC_CTL_TRGM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB04_FUNC_CTL_TRGM3_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB05_FUNC_CTL_TRGM3_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB06_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB07_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB12_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB12_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB13_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB13_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB14_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB14_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB15_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB15_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB16_FUNC_CTL function mux definitions */ -#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB16_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB16_FUNC_CTL_TRGM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB17_FUNC_CTL function mux definitions */ -#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB17_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB17_FUNC_CTL_TRGM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB18_FUNC_CTL function mux definitions */ -#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB18_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB18_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB19_FUNC_CTL function mux definitions */ -#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB19_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB19_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB20_FUNC_CTL function mux definitions */ -#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB20_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB20_FUNC_CTL_TRGM2_P_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB21_FUNC_CTL function mux definitions */ -#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB21_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB21_FUNC_CTL_TRGM2_P_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB22_FUNC_CTL function mux definitions */ -#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB22_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB22_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB22_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB23_FUNC_CTL function mux definitions */ -#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB23_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB23_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB24_FUNC_CTL function mux definitions */ -#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB24_FUNC_CTL_PWM2_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB24_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB25_FUNC_CTL function mux definitions */ -#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB25_FUNC_CTL_PWM2_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB25_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB26_FUNC_CTL function mux definitions */ -#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB26_FUNC_CTL_PWM2_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB27_FUNC_CTL function mux definitions */ -#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB27_FUNC_CTL_PWM2_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB28_FUNC_CTL function mux definitions */ -#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB28_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB28_FUNC_CTL_PWM2_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB28_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB29_FUNC_CTL function mux definitions */ -#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB29_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB29_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB29_FUNC_CTL_PWM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB29_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB30_FUNC_CTL function mux definitions */ -#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB30_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB30_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB30_FUNC_CTL_PWM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB31_FUNC_CTL function mux definitions */ -#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB31_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PB31_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB31_FUNC_CTL_PWM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC00_FUNC_CTL function mux definitions */ -#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC00_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC00_FUNC_CTL_TRGM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC01_FUNC_CTL function mux definitions */ -#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC01_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC01_FUNC_CTL_TRGM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC02_FUNC_CTL function mux definitions */ -#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC02_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC02_FUNC_CTL_TRGM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC03_FUNC_CTL function mux definitions */ -#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC03_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC03_FUNC_CTL_TRGM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC04_FUNC_CTL function mux definitions */ -#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC04_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC04_FUNC_CTL_TRGM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC05_FUNC_CTL function mux definitions */ -#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC05_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC05_FUNC_CTL_TRGM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC06_FUNC_CTL function mux definitions */ -#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC06_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC06_FUNC_CTL_TRGM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC07_FUNC_CTL function mux definitions */ -#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC07_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC07_FUNC_CTL_TRGM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC08_FUNC_CTL function mux definitions */ -#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC08_FUNC_CTL_PWM2_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC09_FUNC_CTL function mux definitions */ -#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC09_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC09_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC10_FUNC_CTL function mux definitions */ -#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC10_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PC11_FUNC_CTL function mux definitions */ -#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC11_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PC12_FUNC_CTL function mux definitions */ -#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC12_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC12_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PC13_FUNC_CTL function mux definitions */ -#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC13_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC13_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC13_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC14_FUNC_CTL function mux definitions */ -#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC14_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC15_FUNC_CTL function mux definitions */ -#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC15_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC16_FUNC_CTL function mux definitions */ -#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC16_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC16_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC17_FUNC_CTL function mux definitions */ -#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC17_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PC18_FUNC_CTL function mux definitions */ -#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC18_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PC19_FUNC_CTL function mux definitions */ -#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC19_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PC20_FUNC_CTL function mux definitions */ -#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC20_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC20_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC21_FUNC_CTL function mux definitions */ -#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC21_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC21_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC22_FUNC_CTL function mux definitions */ -#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC22_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC22_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC23_FUNC_CTL function mux definitions */ -#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC23_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PC23_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC24_FUNC_CTL function mux definitions */ -#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC24_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC25_FUNC_CTL function mux definitions */ -#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC25_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC26_FUNC_CTL function mux definitions */ -#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC26_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC27_FUNC_CTL function mux definitions */ -#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC27_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY00_FUNC_CTL_LIN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY00_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY01_FUNC_CTL_LIN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY01_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY02_FUNC_CTL_LIN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY03_FUNC_CTL_LIN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY04_FUNC_CTL_LIN0_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY04_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY05_FUNC_CTL_LIN1_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PY05_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY06_FUNC_CTL_LIN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY07_FUNC_CTL_LIN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ02_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ03_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_LIN3_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PZ04_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_LIN2_TREN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) -#define IOC_PZ05_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ06_FUNC_CTL_LIN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ07_FUNC_CTL_LIN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(6) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_l1c_drv.h deleted file mode 100644 index 1f1a21639a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 32KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 64B */ -#define HPM_L1C_CACHELINE_SIZE (64) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_mcan_soc.h deleted file mode 100644 index 41e4395ddc3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_mcan_soc.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MCAN_SOC_H -#define HPM_MCAN_SOC_H - -#include -#include "hpm_mcan_regs.h" -#include "hpm_soc_feature.h" - -/** - * @brief TSU External Timebase Sources - */ -#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN1 (1U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN2 (2U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MCAN3 (3U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_PTPC (4U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_PTPC) - -#ifdef __cpluspus -extern "C" { -#endif - -/** - * @brief Set External Timebase Source for MCAN TSU - * @param [in] ptr MCAN base - * @param [in] src External Timebase source - */ -static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) -{ - ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); -} - -/** - * @brief Enable Standby Pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Disable Standby pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Get RAM base for MCAN - * @param [in] ptr MCAN base - * @return RAM base for MCAN - */ -static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) -{ - return (uint32_t) &ptr->MESSAGE_BUFF[0]; -} - -/** - * @brief Get the MCAN RAM offset in the dedicated/shared RAM for - * @param [in] ptr MCAN base - * @return RAM offset for MCAN - */ -static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) -{ - (void) ptr; - return 0U; -} - -/** - * @brief Get MCAN RAM size - * @param [in] ptr MCAN base - * @return RAM size in bytes - */ -static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) -{ - return sizeof(ptr->MESSAGE_BUFF); -} - -#ifdef __cpluspus -} -#endif - -#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_misc.h deleted file mode 100644 index 802c37691b3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_misc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define CORE0_ILM_LOCAL_BASE (0x0U) -#define CORE0_ILM_SIZE_IN_BYTE (0x20000U) -#define CORE0_DLM_LOCAL_BASE (0x80000U) -#define CORE0_DLM_SIZE_IN_BYTE (0x20000U) -#define CORE1_ILM_LOCAL_BASE (0x20000U) -#define CORE1_ILM_SIZE_IN_BYTE (0x20000U) -#define CORE1_DLM_LOCAL_BASE (0xA0000U) -#define CORE1_DLM_SIZE_IN_BYTE (0x20000U) -#define CORE0_ILM_SYSTEM_BASE (0x0U) -#define CORE0_DLM_SYSTEM_BASE (0x80000U) -#define CORE1_ILM_SYSTEM_BASE (0x20000U) -#define CORE1_DLM_SYSTEM_BASE (0xA0000U) - -#define HPM_CORE0 (0U) -#define HPM_CORE1 (1U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_otp_drv.c deleted file mode 100644 index dbab2999552..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - /* Wait until LDO is ready */ - while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { - } - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_otp_drv.h deleted file mode 100644 index b61c805a1df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_otp_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - -/** - * @brief Initialize OTP controller - */ -void otp_init(void); - -/** - * @brief De-initialize OTP controller - */ -void otp_deinit(void); - -/** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_shadow(uint32_t addr); - -/** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_ip(uint32_t addr); - -/** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - -/** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ -hpm_stat_t otp_reload(otp_region_t region); - -/** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - -/** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [in] val Data to be written - * @return API execution status - */ -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_pcfg_drv.h deleted file mode 100644 index c5f8de4b942..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_pcfg_drv.h +++ /dev/null @@ -1,617 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_fuse = 0, - pcfg_pmc_periph_ram = 2, - pcfg_pmc_periph_vad = 4, - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, - pcfg_pmc_periph_debug = 16, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) -#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) -#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) -#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap enable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief bandgap enable low power mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - * @param[in] over_limit unused parameter, will be discarded - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) -{ - (void) over_limit; - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - -/** - * @brief disable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief enable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/** - * @brief Disable CPU0 debug stop notficiation to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; -} - -/** - * @brief Enable CPU0 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; -} - -/** - * @brief Disable CPU1 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; -} - -/** - * @brief Enable CPU1 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; -} - -/** - * @brief Configure CPU core debug stop notification to peripherals - * - * @param[in] ptr - * @param[in] mask - */ -static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) -{ - ptr->DEBUG_STOP = mask; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_plic_drv.h deleted file mode 100644 index 9595051f906..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_plic_drv.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_pmic_iomux.h deleted file mode 100644 index 48bcf5ee53a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_pmic_iomux.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_SOC_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_SOC_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_SOC_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_SOC_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_SOC_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_WDOG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_SOC_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_UART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_SOC_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_UART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_SOC_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_ppor_drv.h deleted file mode 100644 index 687508cc684..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_ppor_drv.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_wdog2 = 1 << 18, - ppor_reset_wdog3 = 1 << 19, - ppor_reset_pmic_wdog = 1 << 20, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_COLD |= mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_COLD &= ~mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOT |= mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOT &= ~mask; -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_romapi.h deleted file mode 100644 index 81c8b5d2c60..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_romapi.h +++ /dev/null @@ -1,1025 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_sdp_drv.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, - uint32_t serial_root_clk_freq, - uint32_t data_valid_time, - xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t - (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t - (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t - (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t - (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t - (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t - (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief XPI RAM driver interface - */ -typedef struct { - /**< XPI RAM driver interface: API version */ - uint32_t version; - - /**< Get XPI RAM configuration based on cfg_option */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); - - /**< XPI RAM driver interface: Initialize XPI RAM */ - hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); -} xpi_ram_driver_interface_t; - -/** - * @brief SDP API interface - */ -typedef struct { - /**< SDP API interface: API version */ - uint32_t version; - /**< SDP API interface: Initialize IP */ - hpm_stat_t (*sdp_ip_init)(void); - /**< SDP API interface: Deinitialize IP */ - hpm_stat_t (*sdp_ip_deinit)(void); - /**< SDP API interface: Set AES key */ - hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: AES ECB crypto operation */ - hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API interface: AES CBC crypto operation */ - hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API interface: AES CTR crypto operation */ - hpm_stat_t - (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API interface: AES CCM encryption */ - hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: AES CCM Decrypt and verify */ - hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: memcpy */ - hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); - /**< SDP API interface: memset */ - hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); - /**< SDP API interface: HASH initialization */ - hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - /**< SDP API interface: HASH update */ - hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - /**< SDP API interface: HASH finish */ - hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); - /**< SDP API interface: Set SM4 Key */ - hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: SM4 Crypto ECB mode */ - hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API Interface: SM4 Crypto CBC mode*/ - hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API Interface: SM4 CTR mode */ - hpm_stat_t - (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API Interface: SM4 CCM Encryption */ - hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API Interface: SM4 CCM Decrypt and Verify */ - hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); -} sdp_driver_interface_t; - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const xpi_ram_driver_interface_t *xpi_ram_driver_if; - /**< Bootloader API table: sdp driver interface address */ - const sdp_driver_interface_t *sdp_driver_if; -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Setup API Runtime environment on demand - */ -static inline void rom_xpi_nor_api_setup(void) -{ - static const uint32_t s_setup_code[] = { - 0x300027f3, 0xf6b36719, 0xe68100e7, 0x90738fd9, 0x80823007, - }; - if (ROM_API_TABLE_ROOT->version == 0x56010000UL) { - typedef union { - void (*callback)(void); - const uint32_t *buffer; - } api_setup_entry_t; - volatile api_setup_entry_t entry; - entry.buffer = &s_setup_code[0]; - entry.callback(); - } -} - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - rom_xpi_nor_api_setup(); - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if - ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API execution address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, - xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - rom_xpi_nor_api_setup(); - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - if ((base != HPM_XPI0) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) - || ((offset & 0xFFF) != 0)) { - return false; - } - static const uint8_t k_mc_xpi_remap_config[] = { - 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, - 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, - 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, - }; - typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); - remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; - bool result = cb(base, start, len, offset); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_disable[] = { - 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, - 0xf5, 0x42, 0x82, 0x80, - }; - typedef void (*remap_disable_cb_t)(XPI_Type *); - remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; - cb(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_enabled[] = { - 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, - }; - typedef bool (*remap_chk_cb_t)(XPI_Type *); - remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; - return chk_cb(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - if (base != HPM_XPI0) { - return false; - } - static const uint8_t k_mc_exip_region_config[] = { - 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, - 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, - 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, - 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, - 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, - 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, - 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, - 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, - 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, - }; - typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); - exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; - cb(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return true; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - static const uint8_t k_mc_exip_region_disable[] = { - 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, - 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, - 0xe7, 0xd0, 0x82, 0x80 - }; - typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); - exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; - cb(base, index); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_enable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, - 0xf5, 0xc0, 0x82, 0x80 - }; - typedef void (*exip_enable_cb_t)(XPI_Type *); - exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; - cb(base); -} - -/** - * @brief Disable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_disable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, - 0x82, 0x80 - }; - typedef void (*exip_disable_cb_t)(XPI_Type *); - exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; - cb(base); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/*********************************************************************************************************************** - * - * - * XPI RAM Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Get XPI RAM configuration based on cfg_option - * @param [in] base XPI base address - * @param [out] ram_cfg XPI RAM configuration structure - * @param [in] cfg_option XPI RAM configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, - xpi_ram_config_t *ram_cfg, - xpi_ram_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); -} - -/** - * @brief Initialize XPI RAM - * @param [in] base XPI base address - * @param [in] ram_cfg XPI ram configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); -} - -/*********************************************************************************************************************** - * - * - * SDP Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Initialize SDP IP - */ -static inline void rom_sdp_init(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); -} - -/** - * @brief De-initialize SDP IP - */ -static inline void rom_sdp_deinit(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); -} - -/** - * @brief Set AES key to SDP - * @param [in] aes_ctx AES context - * @param [in] key AES key buffer - * @param [in] key_bits AES key-bit option - * @param[in] key_idx AES key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] len Data length for AES encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); -} - -/** - * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] length Data length for AES encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); -} - -/** - * @brief Set SM4 key to SDP - * @param [in] sm4_ctx SM4 context - * @param [in] key SM4 key buffer - * @param [in] key_bits SM4 key-bit option - * @param[in] key_idx SM4 key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, - const uint8_t *key, - sdp_sm4_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] len Data length for SM4 encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); -} - -/** - * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); -} - -/** - * @brief HASH initialization - * @param [in] hash_ctx HASH context - * @param [in] alg HASH algorithm - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); -} - -/** - * @brief HASH Update - * @param [in] hash_ctx HASH context - * @param [in] data Data for HASH operation - * @param [in] length of the data for HASH operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); -} - -/** - * @brief HASH finialize - * @param [in] hash_ctx HASH context - * @param [out] digest the output digest - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); -} - -/** - * @brief SDP memcpy operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memcpy - * @param [in] src Source address for memcpy - * @param [in] length Size of data for memcpy operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); -} - -/** - * @brief SDP memset operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memset - * @param [in] pattern pattern for memset - * @param [in] length Size of data for memset operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ea3ba9e8f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union { - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_ses_reg.xml deleted file mode 100644 index 66fcec231df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_ses_reg.xml +++ /dev/null @@ -1,42489 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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* Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ -#define IRQn_GPIO1_A 8 /* GPIO1_A IRQ */ -#define IRQn_GPIO1_B 9 /* GPIO1_B IRQ */ -#define IRQn_GPIO1_C 10 /* GPIO1_C IRQ */ -#define IRQn_GPIO1_D 11 /* GPIO1_D IRQ */ -#define IRQn_GPIO1_X 12 /* GPIO1_X IRQ */ -#define IRQn_GPIO1_Y 13 /* GPIO1_Y IRQ */ -#define IRQn_GPIO1_Z 14 /* GPIO1_Z IRQ */ -#define IRQn_ADC0 15 /* ADC0 IRQ */ -#define IRQn_ADC1 16 /* ADC1 IRQ */ -#define IRQn_ADC2 17 /* ADC2 IRQ */ -#define IRQn_SDFM 18 /* SDFM IRQ */ -#define IRQn_DAC0 19 /* DAC0 IRQ */ -#define IRQn_DAC1 20 /* DAC1 IRQ */ -#define IRQn_ACMP_0 21 /* ACMP[0] IRQ */ -#define IRQn_ACMP_1 22 /* ACMP[1] IRQ */ -#define IRQn_ACMP_2 23 /* ACMP[2] IRQ */ -#define IRQn_ACMP_3 24 /* ACMP[3] IRQ */ -#define IRQn_SPI0 25 /* SPI0 IRQ */ -#define IRQn_SPI1 26 /* SPI1 IRQ */ -#define IRQn_SPI2 27 /* SPI2 IRQ */ -#define IRQn_SPI3 28 /* SPI3 IRQ */ -#define IRQn_UART0 29 /* UART0 IRQ */ -#define IRQn_UART1 30 /* UART1 IRQ */ -#define IRQn_UART2 31 /* UART2 IRQ */ -#define IRQn_UART3 32 /* UART3 IRQ */ -#define IRQn_UART4 33 /* UART4 IRQ */ -#define IRQn_UART5 34 /* UART5 IRQ */ -#define IRQn_UART6 35 /* UART6 IRQ */ -#define IRQn_UART7 36 /* UART7 IRQ */ -#define IRQn_MCAN0 37 /* MCAN0 IRQ */ -#define IRQn_MCAN1 38 /* MCAN1 IRQ */ -#define IRQn_MCAN2 39 /* MCAN2 IRQ */ -#define IRQn_MCAN3 40 /* MCAN3 IRQ */ -#define IRQn_PTPC 41 /* PTPC IRQ */ -#define IRQn_WDG0 42 /* WDG0 IRQ */ -#define IRQn_WDG1 43 /* WDG1 IRQ */ -#define IRQn_TSNS 44 /* TSNS IRQ */ -#define IRQn_MBX0A 45 /* MBX0A IRQ */ -#define IRQn_MBX0B 46 /* MBX0B IRQ */ -#define IRQn_MBX1A 47 /* MBX1A IRQ */ -#define IRQn_MBX1B 48 /* MBX1B IRQ */ -#define IRQn_GPTMR0 49 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 50 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 51 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 52 /* GPTMR3 IRQ */ -#define IRQn_I2C0 53 /* I2C0 IRQ */ -#define IRQn_I2C1 54 /* I2C1 IRQ */ -#define IRQn_I2C2 55 /* I2C2 IRQ */ -#define IRQn_I2C3 56 /* I2C3 IRQ */ -#define IRQn_PWM0 57 /* PWM0 IRQ */ -#define IRQn_HALL0 58 /* HALL0 IRQ */ -#define IRQn_QEI0 59 /* QEI0 IRQ */ -#define IRQn_PWM1 60 /* PWM1 IRQ */ -#define IRQn_HALL1 61 /* HALL1 IRQ */ -#define IRQn_QEI1 62 /* QEI1 IRQ */ -#define IRQn_PWM2 63 /* PWM2 IRQ */ -#define IRQn_HALL2 64 /* HALL2 IRQ */ -#define IRQn_QEI2 65 /* QEI2 IRQ */ -#define IRQn_PWM3 66 /* PWM3 IRQ */ -#define IRQn_HALL3 67 /* HALL3 IRQ */ -#define IRQn_QEI3 68 /* QEI3 IRQ */ -#define IRQn_SDP 69 /* SDP IRQ */ -#define IRQn_XPI0 70 /* XPI0 IRQ */ -#define IRQn_XDMA 71 /* XDMA IRQ */ -#define IRQn_HDMA 72 /* HDMA IRQ */ -#define IRQn_RNG 73 /* RNG IRQ */ -#define IRQn_USB0 74 /* USB0 IRQ */ -#define IRQn_PSEC 75 /* PSEC IRQ */ -#define IRQn_PGPIO 76 /* PGPIO IRQ */ -#define IRQn_PWDG 77 /* PWDG IRQ */ -#define IRQn_PTMR 78 /* PTMR IRQ */ -#define IRQn_PUART 79 /* PUART IRQ */ -#define IRQn_FUSE 80 /* FUSE IRQ */ -#define IRQn_SECMON 81 /* SECMON IRQ */ -#define IRQn_RTC 82 /* RTC IRQ */ -#define IRQn_BUTN 83 /* BUTN IRQ */ -#define IRQn_BGPIO 84 /* BGPIO IRQ */ -#define IRQn_BVIO 85 /* BVIO IRQ */ -#define IRQn_BROWNOUT 86 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 87 /* SYSCTL IRQ */ -#define IRQn_DEBUG_0 88 /* DEBUG[0] IRQ */ -#define IRQn_DEBUG_1 89 /* DEBUG[1] IRQ */ -#define IRQn_LIN0 90 /* LIN0 IRQ */ -#define IRQn_LIN1 91 /* LIN1 IRQ */ -#define IRQn_LIN2 92 /* LIN2 IRQ */ -#define IRQn_LIN3 93 /* LIN3 IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0xC0000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF0000000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* GPIO1 base address */ -#define HPM_GPIO1_BASE (0xF0004000UL) -/* GPIO1 base pointer */ -#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF40DC000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) -/* BGPIO base address */ -#define HPM_BGPIO_BASE (0xF5014000UL) -/* BGPIO base pointer */ -#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF0008000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF0010000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) -/* ADC1 base address */ -#define HPM_ADC1_BASE (0xF0014000UL) -/* ADC1 base pointer */ -#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) -/* ADC2 base address */ -#define HPM_ADC2_BASE (0xF0018000UL) -/* ADC2 base pointer */ -#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) - -#include "hpm_sdm_regs.h" -/* Address of SDM instances */ -/* SDM base address */ -#define HPM_SDM_BASE (0xF001C000UL) -/* SDM base pointer */ -#define HPM_SDM ((SDM_Type *) HPM_SDM_BASE) - -#include "hpm_acmp_regs.h" -/* Address of ACMP instances */ -/* ACMP base address */ -#define HPM_ACMP_BASE (0xF0020000UL) -/* ACMP base pointer */ -#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) - -#include "hpm_dac_regs.h" -/* Address of DAC instances */ -/* DAC0 base address */ -#define HPM_DAC0_BASE (0xF0024000UL) -/* DAC0 base pointer */ -#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE) -/* DAC1 base address */ -#define HPM_DAC1_BASE (0xF0028000UL) -/* DAC1 base pointer */ -#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0030000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0034000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0038000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF003C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* UART4 base address */ -#define HPM_UART4_BASE (0xF0050000UL) -/* UART4 base pointer */ -#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) -/* UART5 base address */ -#define HPM_UART5_BASE (0xF0054000UL) -/* UART5 base pointer */ -#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) -/* UART6 base address */ -#define HPM_UART6_BASE (0xF0058000UL) -/* UART6 base pointer */ -#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) -/* UART7 base address */ -#define HPM_UART7_BASE (0xF005C000UL) -/* UART7 base pointer */ -#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF40E4000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_mcan_regs.h" -/* Address of MCAN instances */ -/* MCAN0 base address */ -#define HPM_MCAN0_BASE (0xF0080000UL) -/* MCAN0 base pointer */ -#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) -/* MCAN1 base address */ -#define HPM_MCAN1_BASE (0xF0084000UL) -/* MCAN1 base pointer */ -#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) -/* MCAN2 base address */ -#define HPM_MCAN2_BASE (0xF0088000UL) -/* MCAN2 base pointer */ -#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) -/* MCAN3 base address */ -#define HPM_MCAN3_BASE (0xF008C000UL) -/* MCAN3 base pointer */ -#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) - -#include "hpm_wdg_regs.h" -/* Address of WDOG instances */ -/* WDG0 base address */ -#define HPM_WDG0_BASE (0xF0090000UL) -/* WDG0 base pointer */ -#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) -/* WDG1 base address */ -#define HPM_WDG1_BASE (0xF0094000UL) -/* WDG1 base pointer */ -#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) -/* PWDG base address */ -#define HPM_PWDG_BASE (0xF40E8000UL) -/* PWDG base pointer */ -#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) -/* MBX1A base address */ -#define HPM_MBX1A_BASE (0xF00A8000UL) -/* MBX1A base pointer */ -#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) -/* MBX1B base address */ -#define HPM_MBX1B_BASE (0xF00AC000UL) -/* MBX1B base pointer */ -#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) - -#include "hpm_ptpc_regs.h" -/* Address of PTPC instances */ -/* PTPC base address */ -#define HPM_PTPC_BASE (0xF00B0000UL) -/* PTPC base pointer */ -#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) - -#include "hpm_crc_regs.h" -/* Address of CRC instances */ -/* CRC base address */ -#define HPM_CRC_BASE (0xF00B8000UL) -/* CRC base pointer */ -#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C0000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dma_regs.h" -/* Address of DMA instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C4000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) -/* XDMA base address */ -#define HPM_XDMA_BASE (0xF3048000UL) -/* XDMA base pointer */ -#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) - -#include "hpm_rng_regs.h" -/* Address of RNG instances */ -/* RNG base address */ -#define HPM_RNG_BASE (0xF00C8000UL) -/* RNG base pointer */ -#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF00CC000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_pwm_regs.h" -/* Address of PWM instances */ -/* PWM0 base address */ -#define HPM_PWM0_BASE (0xF0200000UL) -/* PWM0 base pointer */ -#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) -/* PWM1 base address */ -#define HPM_PWM1_BASE (0xF0210000UL) -/* PWM1 base pointer */ -#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) -/* PWM2 base address */ -#define HPM_PWM2_BASE (0xF0220000UL) -/* PWM2 base pointer */ -#define HPM_PWM2 ((PWM_Type *) HPM_PWM2_BASE) -/* PWM3 base address */ -#define HPM_PWM3_BASE (0xF0230000UL) -/* PWM3 base pointer */ -#define HPM_PWM3 ((PWM_Type *) HPM_PWM3_BASE) - -#include "hpm_hall_regs.h" -/* Address of HALL instances */ -/* HALL0 base address */ -#define HPM_HALL0_BASE (0xF0204000UL) -/* HALL0 base pointer */ -#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) -/* HALL1 base address */ -#define HPM_HALL1_BASE (0xF0214000UL) -/* HALL1 base pointer */ -#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) -/* HALL2 base address */ -#define HPM_HALL2_BASE (0xF0224000UL) -/* HALL2 base pointer */ -#define HPM_HALL2 ((HALL_Type *) HPM_HALL2_BASE) -/* HALL3 base address */ -#define HPM_HALL3_BASE (0xF0234000UL) -/* HALL3 base pointer */ -#define HPM_HALL3 ((HALL_Type *) HPM_HALL3_BASE) - -#include "hpm_qei_regs.h" -/* Address of QEI instances */ -/* QEI0 base address */ -#define HPM_QEI0_BASE (0xF0208000UL) -/* QEI0 base pointer */ -#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) -/* QEI1 base address */ -#define HPM_QEI1_BASE (0xF0218000UL) -/* QEI1 base pointer */ -#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) -/* QEI2 base address */ -#define HPM_QEI2_BASE (0xF0228000UL) -/* QEI2 base pointer */ -#define HPM_QEI2 ((QEI_Type *) HPM_QEI2_BASE) -/* QEI3 base address */ -#define HPM_QEI3_BASE (0xF0238000UL) -/* QEI3 base pointer */ -#define HPM_QEI3 ((QEI_Type *) HPM_QEI3_BASE) - -#include "hpm_trgm_regs.h" -/* Address of TRGM instances */ -/* TRGM0 base address */ -#define HPM_TRGM0_BASE (0xF020C000UL) -/* TRGM0 base pointer */ -#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) -/* TRGM1 base address */ -#define HPM_TRGM1_BASE (0xF021C000UL) -/* TRGM1 base pointer */ -#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) -/* TRGM2 base address */ -#define HPM_TRGM2_BASE (0xF022C000UL) -/* TRGM2 base pointer */ -#define HPM_TRGM2 ((TRGM_Type *) HPM_TRGM2_BASE) -/* TRGM3 base address */ -#define HPM_TRGM3_BASE (0xF023C000UL) -/* TRGM3 base pointer */ -#define HPM_TRGM3 ((TRGM_Type *) HPM_TRGM3_BASE) - -#include "hpm_pla_regs.h" -/* Address of PLA instances */ -/* PLA0 base address */ -#define HPM_PLA0_BASE (0xF020E000UL) -/* PLA0 base pointer */ -#define HPM_PLA0 ((PLA_Type *) HPM_PLA0_BASE) -/* PLA1 base address */ -#define HPM_PLA1_BASE (0xF021E000UL) -/* PLA1 base pointer */ -#define HPM_PLA1 ((PLA_Type *) HPM_PLA1_BASE) - -#include "hpm_synt_regs.h" -/* Address of SYNT instances */ -/* SYNT base address */ -#define HPM_SYNT_BASE (0xF0240000UL) -/* SYNT base pointer */ -#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF2020000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF3000000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF3004000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* GPTMR2 base address */ -#define HPM_GPTMR2_BASE (0xF3008000UL) -/* GPTMR2 base pointer */ -#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) -/* GPTMR3 base address */ -#define HPM_GPTMR3_BASE (0xF300C000UL) -/* GPTMR3 base pointer */ -#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF40E0000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF3020000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF3024000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF3028000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF302C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) - -#include "hpm_lin_regs.h" -/* Address of LIN instances */ -/* LIN0 base address */ -#define HPM_LIN0_BASE (0xF3030000UL) -/* LIN0 base pointer */ -#define HPM_LIN0 ((LIN_Type *) HPM_LIN0_BASE) -/* LIN1 base address */ -#define HPM_LIN1_BASE (0xF3034000UL) -/* LIN1 base pointer */ -#define HPM_LIN1 ((LIN_Type *) HPM_LIN1_BASE) -/* LIN2 base address */ -#define HPM_LIN2_BASE (0xF3038000UL) -/* LIN2 base pointer */ -#define HPM_LIN2 ((LIN_Type *) HPM_LIN2_BASE) -/* LIN3 base address */ -#define HPM_LIN3_BASE (0xF303C000UL) -/* LIN3 base pointer */ -#define HPM_LIN3 ((LIN_Type *) HPM_LIN3_BASE) - -#include "hpm_sdp_regs.h" -/* Address of SDP instances */ -/* SDP base address */ -#define HPM_SDP_BASE (0xF304C000UL) -/* SDP base pointer */ -#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) - -/* Address of ROMC instances */ -/* ROMC base address */ -#define HPM_ROMC_BASE (0xF3054000UL) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF40D8000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) -/* BIOC base address */ -#define HPM_BIOC_BASE (0xF5010000UL) -/* BIOC base pointer */ -#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTPSHW base address */ -#define HPM_OTPSHW_BASE (0xF4080000UL) -/* OTPSHW base pointer */ -#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) -/* OTP base address */ -#define HPM_OTP_BASE (0xF40C8000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF40C0000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF40C4000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_psec_regs.h" -/* Address of PSEC instances */ -/* PSEC base address */ -#define HPM_PSEC_BASE (0xF40CC000UL) -/* PSEC base pointer */ -#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) - -#include "hpm_pmon_regs.h" -/* Address of PMON instances */ -/* PMON base address */ -#define HPM_PMON_BASE (0xF40D0000UL) -/* PMON base pointer */ -#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR base address */ -#define HPM_PGPR_BASE (0xF40D4000UL) -/* PGPR base pointer */ -#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) - -#include "hpm_pllctlv2_regs.h" -/* Address of PLLCTLV2 instances */ -/* PLLCTLV2 base address */ -#define HPM_PLLCTLV2_BASE (0xF4100000UL) -/* PLLCTLV2 base pointer */ -#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) - -#include "hpm_tsns_regs.h" -/* Address of TSNS instances */ -/* TSNS base address */ -#define HPM_TSNS_BASE (0xF4104000UL) -/* TSNS base pointer */ -#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) - -#include "hpm_bacc_regs.h" -/* Address of BACC instances */ -/* BACC base address */ -#define HPM_BACC_BASE (0xF5000000UL) -/* BACC base pointer */ -#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) - -#include "hpm_bpor_regs.h" -/* Address of BPOR instances */ -/* BPOR base address */ -#define HPM_BPOR_BASE (0xF5004000UL) -/* BPOR base pointer */ -#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) - -#include "hpm_bcfg_regs.h" -/* Address of BCFG instances */ -/* BCFG base address */ -#define HPM_BCFG_BASE (0xF5008000UL) -/* BCFG base pointer */ -#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) - -#include "hpm_butn_regs.h" -/* Address of BUTN instances */ -/* BUTN base address */ -#define HPM_BUTN_BASE (0xF500C000UL) -/* BUTN base pointer */ -#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) - -#include "hpm_bgpr_regs.h" -/* Address of BGPR instances */ -/* BGPR base address */ -#define HPM_BGPR_BASE (0xF5018000UL) -/* BGPR base pointer */ -#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) - -#include "hpm_bsec_regs.h" -/* Address of BSEC instances */ -/* BSEC base address */ -#define HPM_BSEC_BASE (0xF5040000UL) -/* BSEC base pointer */ -#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) - -#include "hpm_rtc_regs.h" -/* Address of RTC instances */ -/* RTC base address */ -#define HPM_RTC_BASE (0xF5044000UL) -/* RTC base pointer */ -#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) - -#include "hpm_bkey_regs.h" -/* Address of BKEY instances */ -/* BKEY base address */ -#define HPM_BKEY_BASE (0xF5048000UL) -/* BKEY base pointer */ -#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) - -#include "hpm_bmon_regs.h" -/* Address of BMON instances */ -/* BMON base address */ -#define HPM_BMON_BASE (0xF504C000UL) -/* BMON base pointer */ -#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) - -#include "hpm_tamp_regs.h" -/* Address of TAMP instances */ -/* TAMP base address */ -#define HPM_TAMP_BASE (0xF5050000UL) -/* TAMP base pointer */ -#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) - -#include "hpm_mono_regs.h" -/* Address of MONO instances */ -/* MONO base address */ -#define HPM_MONO_BASE (0xF5054000UL) -/* MONO base pointer */ -#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_trgmmux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_soc_feature.h deleted file mode 100644 index be5184f10cd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_soc_feature.h +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" -#include "hpm_soc_ip_feature.h" - -/* - * UART section - */ -#define UART_SOC_FIFO_SIZE (16U) - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (256U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (3U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (16U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (8U) -#define DMA_SOC_MAX_COUNT (2U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) -#define DMA_SOC_HAS_IDLE_FLAG (1U) - -/* - * PDMA Section - */ -#define PDMA_SOC_PS_MAX_COUNT (0U) - -/* - * LCDC Section - */ -#define LCDC_SOC_MAX_LAYER_COUNT (0U) -#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U) -#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) -#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) - -/* - * USB Section - */ -#define USB_SOC_MAX_COUNT (1U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* - * ADC Section - */ -#define ADC_SOC_IP_VERSION (1U) -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * CAN Section - */ -#define CAN_SOC_MAX_COUNT (2U) -#define CAN_SOC_TX_RX_BUFFER_ACCESS_WORKAROUND (1) /* Refer to E00028 in HPM6200 Errata */ - -/* - * SDP Section - */ -#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) -#define SDP_HAS_SM3_SUPPORT (1U) -#define SDP_HAS_SM4_SUPPORT (1U) - -/* - * SOC Privilege mode - */ -#define SOC_HAS_S_MODE (1U) - -/* - * DAC Section - */ -#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) -#define DAC_SOC_MAX_DATA (4095U) -#define DAC_SOC_MAX_BUFF_COUNT (65536U) -#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) - - -/* - * SDXC Section - */ -#define SDXC_SOC_HAS_MISC_CTRL0 (1) -#define SDXC_SOC_HAS_MISC_CTRL1 (1) - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (512U) -#define SPI_SOC_FIFO_DEPTH (4U) - -/** - * PWM Section - * - */ -#define PWM_SOC_HRPWM_SUPPORT (1U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (1U) -#define PWM_SOC_TIMER_RESET_SUPPORT (1U) - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_soc_ip_feature.h deleted file mode 100644 index bc97a6413b7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_soc_ip_feature.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* UART related feature */ -#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 - -/* PWM related feature */ -#define HPM_IP_FEATURE_PWM_COUNTER_RESET 1 -#define HPM_IP_FEATURE_PWM_HRPWM 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_sysctl_drv.c deleted file mode 100644 index 7e2d2cf73d5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_sysctl_drv.c +++ /dev/null @@ -1,353 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 -#define SYSCTL_RESOURCE_GROUP1 1 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) - -static inline bool sysctl_valid_cpu_index(uint8_t cpu) -{ -#ifdef SYSCTL_CPU_CPU1 - return (cpu > SYSCTL_CPU_CPU1) ? false : true; -#else - return (cpu != SYSCTL_CPU_CPU0) ? false : true; -#endif -} - -hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) -{ - uint32_t i; - if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { - return status_invalid_argument; - } - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i]; - } - return status_success; -} - -static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[cpu].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); -} - -hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); -} - -static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[cpu].GPR[start + i] = *(data + i); - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 1, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu1_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) -{ - ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & - ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | - SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | - (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | - SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | - SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | - SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | - SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | - SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = { 0 }; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].GPR[0] = entry; - ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); - return status_success; -} - -hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 1, entry); -} - -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 0, entry); -} - -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable) -{ - uint32_t index, offset; - if (resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - case SYSCTL_RESOURCE_GROUP1: - ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource) -{ - uint32_t index, offset; - bool enable; - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - case SYSCTL_RESOURCE_GROUP1: - enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - case SYSCTL_RESOURCE_GROUP1: - value = ptr->GROUP1[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | - (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, - clock_source_t source, - uint32_t cpu_div, - uint32_t axi_sub_div, - uint32_t ahb_sub_div) -{ - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - - uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; - if (origin_cpu_div == cpu_div) { - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | - SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - } - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | - SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); - - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - - return status_success; -} - -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) -{ - if (source >= clock_source_adc_clk_end) { - return status_invalid_argument; - } - uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); - if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { - return status_invalid_argument; - } - - ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); - - return status_success; -} - -hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source) -{ - if (source >= clock_source_dac_clk_end) { - return status_invalid_argument; - } - uint32_t dac_index = (uint32_t) (node - clock_node_dac_start); - if (dac_index >= ARRAY_SIZE(ptr->DACCLK)) { - return status_invalid_argument; - } - - ptr->DACCLK[dac_index] = (ptr->DACCLK[dac_index] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(source); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_sysctl_drv.h deleted file mode 100644 index 8ddd5db72d7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_sysctl_drv.h +++ /dev/null @@ -1,1577 +0,0 @@ -/** - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - sysctl_retention_domain_cpu1 = 4, - sysctl_retention_domain_xtal24m = 6, - sysctl_retention_domain_pll0 = 7, - sysctl_retention_domain_pll1 = 8, - sysctl_retention_domain_pll2 = 9, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_cpu0, - sysctl_reset_domain_cpu1, -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0, - sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0, - sysctl_resource_cpu1 = SYSCTL_RESOURCE_CPU1, - sysctl_resource_cpx1 = SYSCTL_RESOURCE_CPX1, - sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0, - sysctl_resource_pow_cpu1 = SYSCTL_RESOURCE_POW_CPU1, - sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC, - sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0, - sysctl_resource_rst_cpu1 = SYSCTL_RESOURCE_RST_CPU1, - sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL, - sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0, - sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0, - sysctl_resource_clk1_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0, - sysctl_resource_clk2_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0, - sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1, - sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1, - sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1, - sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2, - sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2, - sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2, - sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF, - sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF, - sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF, - - sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0, - sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0, - sysctl_resource_clk_top_mchtmr1 = SYSCTL_RESOURCE_CLK_TOP_MCT1, - sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0, - sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0, - sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1, - sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2, - sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3, - sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0, - sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1, - sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2, - sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3, - sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4, - sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5, - sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6, - sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7, - sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0, - sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1, - sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2, - sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3, - sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0, - sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1, - sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2, - sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3, - sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0, - sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1, - sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2, - sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3, - sysctl_resource_clk_top_ptpc = SYSCTL_RESOURCE_CLK_TOP_PTPC, - sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0, - sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1, - sysctl_resource_clk_top_ana2 = SYSCTL_RESOURCE_CLK_TOP_ANA2, - sysctl_resource_clk_top_ana3 = SYSCTL_RESOURCE_CLK_TOP_ANA3, - sysctl_resource_clk_top_ana4 = SYSCTL_RESOURCE_CLK_TOP_ANA4, - sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0, - sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1, - sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0, - sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1, - sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2, - sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3, - sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0, - sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1, - sysctl_resource_clk_top_adc2 = SYSCTL_RESOURCE_CLK_TOP_ADC2, - sysctl_resource_clk_top_dac0 = SYSCTL_RESOURCE_CLK_TOP_DAC0, - sysctl_resource_clk_top_dac1 = SYSCTL_RESOURCE_CLK_TOP_DAC1, - - - sysctl_resource_linkable_start = 256, - sysctl_resource_ahbp = SYSCTL_RESOURCE_AHBP, - sysctl_resource_axis = SYSCTL_RESOURCE_AXIS, - sysctl_resource_axic = SYSCTL_RESOURCE_AXIC, - sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0, - sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0, - sysctl_resource_lmm1 = SYSCTL_RESOURCE_LMM1, - sysctl_resource_mchtmr1 = SYSCTL_RESOURCE_MCT1, - sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0, - sysctl_resource_ram0 = SYSCTL_RESOURCE_RAM0, - sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0, - sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1, - sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2, - sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3, - sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0, - sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1, - sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2, - sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3, - sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO, - sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0, - sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1, - sysctl_resource_adc2 = SYSCTL_RESOURCE_ADC2, - sysctl_resource_dac0 = SYSCTL_RESOURCE_DAC0, - sysctl_resource_dac1 = SYSCTL_RESOURCE_DAC1, - sysctl_resource_acmp = SYSCTL_RESOURCE_ACMP, - sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0, - sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1, - sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2, - sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3, - sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0, - sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0, - sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1, - sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2, - sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3, - sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4, - sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5, - sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6, - sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7, - sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0, - sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1, - sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2, - sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3, - sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC, - sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0, - sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1, - sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2, - sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3, - sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0, - sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1, - sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0, - sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1, - sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0, - sysctl_resource_mot0 = SYSCTL_RESOURCE_MOT0, - sysctl_resource_mot1 = SYSCTL_RESOURCE_MOT1, - sysctl_resource_mot2 = SYSCTL_RESOURCE_MOT2, - sysctl_resource_mot3 = SYSCTL_RESOURCE_MOT3, - sysctl_resource_synt = SYSCTL_RESOURCE_SYNT, - sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0, - sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA, - sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA, - sysctl_resource_kman = SYSCTL_RESOURCE_KMAN, - sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0, - sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0, - sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS, - sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0, - sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0, - sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ - sysctl_resource_mode_force_on, /*!< Force the resource clock on */ - sysctl_resource_mode_force_off, /*!< Force the resource clock off */ -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, - clock_node_mchtmr1 = SYSCTL_CLOCK_CLK_TOP_MCT1, - clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, - clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, - clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, - clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, - clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, - clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, - clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, - clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, - clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, - clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, - clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, - clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, - clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, - clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, - clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, - clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, - clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, - clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, - clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, - clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, - clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, - clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, - clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, - clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, - clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, - clock_node_ptpc = SYSCTL_CLOCK_CLK_TOP_PTPC, - clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, - clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, - clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, - clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, - clock_node_ana4 = SYSCTL_CLOCK_CLK_TOP_ANA4, - clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, - clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, - clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0, - clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1, - clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2, - clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3, - - clock_node_adc_start, - clock_node_adc0 = clock_node_adc_start, - clock_node_adc1, - clock_node_adc2, - clock_node_adc3, - - clock_node_dac_start, - clock_node_dac0 = clock_node_dac_start, - clock_node_dac1, - clock_node_end, - - clock_node_core_start = 0xfc, - clock_node_cpu0 = clock_node_core_start, - clock_node_cpu1 = clock_node_cpu0, - clock_node_axi, - clock_node_ahb, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll0_clk1 = 2, - clock_source_pll0_clk2 = 3, - clock_source_pll1_clk0 = 4, - clock_source_pll1_clk1 = 5, - clock_source_pll2_clk0 = 6, - clock_source_pll2_clk1 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC clock sources - */ -typedef enum { - clock_source_adc_ana_clock = 0, - clock_source_adc_ahb_clock = 1, - clock_source_adc_clk_end, -} clock_source_adc_t; - -/** - * @brief DAC clock sources - */ -typedef enum { - clock_source_dac_ana_clock = 0, - clock_source_dac_ahb_clock = 1, - clock_source_dac_clk_end, -} clock_source_dac_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -/* Monitor Target types */ -typedef enum { - monitor_target_clk_32k = 0, - monitor_target_clk_irc24m = 1, - monitor_target_clk_xtal_24m = 2, - monitor_target_clk_usb0_phy = 3, - monitor_target_clk_usb1_phy = 4, - monitor_target_clk0_osc0 = 8, - monitor_target_clk0_pll0 = 9, - monitor_target_clk1_pll0 = 10, - monitor_target_clk2_pll0 = 11, - monitor_target_clk0_pll1 = 12, - monitor_target_clk1_pll1 = 13, - monitor_target_clk0_pll2 = 14, - monitor_target_clk1_pll2 = 15, - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_mchtmr1 = 130, - monitor_target_clk_top_xpi0 = 131, - monitor_target_clk_top_gptmr0 = 132, - monitor_target_clk_top_gptmr1 = 133, - monitor_target_clk_top_gptmr2 = 134, - monitor_target_clk_top_gptmr3 = 135, - monitor_target_clk_top_uart0 = 136, - monitor_target_clk_top_uart1 = 137, - monitor_target_clk_top_uart2 = 138, - monitor_target_clk_top_uart3 = 139, - monitor_target_clk_top_uart4 = 140, - monitor_target_clk_top_uart5 = 141, - monitor_target_clk_top_uart6 = 142, - monitor_target_clk_top_uart7 = 143, - monitor_target_clk_top_i2c0 = 144, - monitor_target_clk_top_i2c1 = 145, - monitor_target_clk_top_i2c2 = 146, - monitor_target_clk_top_i2c3 = 147, - monitor_target_clk_top_spi0 = 148, - monitor_target_clk_top_spi1 = 149, - monitor_target_clk_top_spi2 = 150, - monitor_target_clk_top_spi3 = 151, - monitor_target_clk_top_can0 = 152, - monitor_target_clk_top_can1 = 153, - monitor_target_clk_top_can2 = 154, - monitor_target_clk_top_can3 = 155, - monitor_target_clk_top_ptpc = 156, - monitor_target_clk_top_ana0 = 157, - monitor_target_clk_top_ana1 = 158, - monitor_target_clk_top_ana2 = 159, - monitor_target_clk_top_ana3 = 160, - monitor_target_clk_top_ana4 = 161, - monitor_target_clk_top_ref0 = 162, - monitor_target_clk_top_ref1 = 163, - monitor_target_clk_top_lin0 = 164, - monitor_target_clk_top_lin1 = 165, - monitor_target_clk_top_lin2 = 166, - monitor_target_clk_top_lin3 = 167, -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | - (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit_high, - uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = - (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | - SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Disable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Disable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 1, value); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, - uint8_t cpu_index, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - uint8_t set_mask = 0x1; - if (domain < sysctl_retention_domain_xtal24m) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Retain target domain for specific CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem); -} - -/** - * @brief Check if cpu clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; -} - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Preserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Unpreserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Get target CPU0 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 0, status_index); -} - -/** - * @brief Get target CPU1 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 1, status_index); -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index, - uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Check CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); -} - -/** - * @brief Check CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask); -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); -} - - -/** - * @brief Disable CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask); -} - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Disable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); -} - - -/** - * @brief Disable CPU1 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num); -} - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Enable CPU1 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num); -} - -/** - * @brief Lock CPU gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); -} - -/** - * @brief Lock CPU1 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask); -} - -/** - * @brief Lock CPU lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 0); -} - -/** - * @brief Lock CPU1 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 1); -} - -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) -{ - ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); -} - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 0, mode); -} - -/** - * @brief Set CPU1 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 1, mode); -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= - ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Clear CPU1 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 1, flags); -} - -/** - * @brief Get CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ptr->CPU[cpu_index].LP & - (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); -} - -/** - * @brief Get CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 0); -} - -/** - * @brief Get CPU1 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 1); -} - -/** - * @brief Release cpu - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; -} - -/** - * @brief Release cpu1 - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) -{ - sysctl_release_cpu(ptr, 1); -} - -/** - * @brief Check whether CPU is released or not - * - * @param [in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval true CPU is released - * @retval false CPU is on-hold - */ -static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); -} - -/** - * @brief Check whether CPU1 is released or not - * - * @param [in] ptr SYSCTL_Type base address - * @retval true CPU1 is released - * @retval false CPU1 is on-hold - */ -static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) -{ - return sysctl_is_cpu_released(ptr, 1); -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); - -/** - * @brief Configure CPU domain clock - * @param ptr SYSCTL base address - * @param source clock source to be used - * @param cpu_div CPU divider - * @param axi_sub_div AXI BUS divider based on divided CPU clock - * @param ahb_sub_div AHB BUS divider based on divided CPU clock - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, - clock_source_t source, - uint32_t cpu_div, - uint32_t axi_sub_div, - uint32_t ahb_sub_div); - -/** - * @brief Set ADC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); - - -/** - * @brief Set DAC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_dac_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_dac_t source); - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Add resource to CPU1 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be added to CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU1 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); - -/** - * @brief Save data to CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved from CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set data to CPU1 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved in CPU1 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set entry point on CPU boot or wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu CPU index - * @param[in] entry Entry address for CPU - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - -/** - * @brief Set entry point on either CPU1 boot or wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_trgmmux_src.h deleted file mode 100644 index 2379fe38099..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/hpm_trgmmux_src.h +++ /dev/null @@ -1,734 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGMMUX_SRC_H -#define HPM_TRGMMUX_SRC_H - -/* trgm0_input mux definitions */ -#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) -#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) -#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) -#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) -#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) -#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) -#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) -#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x1CUL) -#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x1DUL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x1EUL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x1FUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH0 (0x20UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH1 (0x21UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH2 (0x22UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH3 (0x23UL) -#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x24UL) -#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x25UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x26UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x27UL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPL0 (0x28UL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPL1 (0x29UL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPL2 (0x2AUL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPL3 (0x2BUL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPH0 (0x2CUL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPH1 (0x2DUL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPH2 (0x2EUL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPH3 (0x2FUL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ0 (0x30UL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ1 (0x31UL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ2 (0x32UL) -#define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ3 (0x33UL) -#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT0 (0x38UL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT1 (0x39UL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT2 (0x3AUL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT3 (0x3BUL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT4 (0x3CUL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT5 (0x3DUL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT6 (0x3EUL) -#define HPM_TRGM0_INPUT_SRC_PLA0_OUT7 (0x3FUL) - -/* trgm1_input mux definitions */ -#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) -#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) -#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) -#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) -#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) -#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) -#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x1CUL) -#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x1DUL) -#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x1EUL) -#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x1FUL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x20UL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x21UL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x22UL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x23UL) -#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x24UL) -#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x25UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2 (0x26UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT3 (0x27UL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPL0 (0x28UL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPL1 (0x29UL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPL2 (0x2AUL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPL3 (0x2BUL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPH0 (0x2CUL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPH1 (0x2DUL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPH2 (0x2EUL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPH3 (0x2FUL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ0 (0x30UL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ1 (0x31UL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ2 (0x32UL) -#define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ3 (0x33UL) -#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT0 (0x38UL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT1 (0x39UL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT2 (0x3AUL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT3 (0x3BUL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT4 (0x3CUL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT5 (0x3DUL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT6 (0x3EUL) -#define HPM_TRGM1_INPUT_SRC_PLA1_OUT7 (0x3FUL) - -/* trgm2_input mux definitions */ -#define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) -#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) -#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) -#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) -#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) -#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) -#define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x1CUL) -#define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x1DUL) -#define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x1EUL) -#define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x1FUL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x20UL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x21UL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x22UL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x23UL) -#define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x24UL) -#define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x25UL) -#define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT2 (0x26UL) -#define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT3 (0x27UL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPL0 (0x28UL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPL1 (0x29UL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPL2 (0x2AUL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPL3 (0x2BUL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPH0 (0x2CUL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPH1 (0x2DUL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPH2 (0x2EUL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPH3 (0x2FUL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ0 (0x30UL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ1 (0x31UL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ2 (0x32UL) -#define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ3 (0x33UL) -#define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) - -/* trgm3_input mux definitions */ -#define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) -#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) -#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) -#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) -#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) -#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) -#define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x1CUL) -#define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x1DUL) -#define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x1EUL) -#define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x1FUL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x20UL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x21UL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x22UL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x23UL) -#define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x24UL) -#define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x25UL) -#define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 (0x26UL) -#define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT3 (0x27UL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPL0 (0x28UL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPL1 (0x29UL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPL2 (0x2AUL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPL3 (0x2BUL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPH0 (0x2CUL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPH1 (0x2DUL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPH2 (0x2EUL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPH3 (0x2FUL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ0 (0x30UL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ1 (0x31UL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ2 (0x32UL) -#define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ3 (0x33UL) -#define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) - -/* trgm0_output mux definitions */ -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN0 (0x1EUL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN1 (0x1FUL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN2 (0x20UL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN3 (0x21UL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN4 (0x22UL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN5 (0x23UL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN6 (0x24UL) -#define HPM_TRGM0_OUTPUT_SRC_PLA0_IN7 (0x25UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) -#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) -#define HPM_TRGM0_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) -#define HPM_TRGM0_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) -#define HPM_TRGM0_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) -#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) -#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG0 (0x40UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG1 (0x41UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG2 (0x42UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_TRG3 (0x43UL) - -/* trgm1_output mux definitions */ -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN0 (0x1EUL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN1 (0x1FUL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN2 (0x20UL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN3 (0x21UL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN4 (0x22UL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN5 (0x23UL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN6 (0x24UL) -#define HPM_TRGM1_OUTPUT_SRC_PLA1_IN7 (0x25UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) -#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_SYNCI (0x37UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN2 (0x38UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN3 (0x39UL) -#define HPM_TRGM1_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) -#define HPM_TRGM1_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) -#define HPM_TRGM1_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) -#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) -#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) -#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG4 (0x40UL) -#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG5 (0x41UL) -#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG6 (0x42UL) -#define HPM_TRGM1_OUTPUT_SRC_SDM_TRG7 (0x43UL) - -/* trgm2_output mux definitions */ -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) -#define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) -#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) -#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) -#define HPM_TRGM2_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) -#define HPM_TRGM2_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) -#define HPM_TRGM2_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) -#define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) -#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) -#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG8 (0x40UL) -#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG9 (0x41UL) -#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG10 (0x42UL) -#define HPM_TRGM2_OUTPUT_SRC_SDM_TRG11 (0x43UL) - -/* trgm3_output mux definitions */ -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) -#define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) -#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) -#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_SYNCI (0x37UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN2 (0x38UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN3 (0x39UL) -#define HPM_TRGM3_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) -#define HPM_TRGM3_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) -#define HPM_TRGM3_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) -#define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) -#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) -#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG12 (0x40UL) -#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG13 (0x41UL) -#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG14 (0x42UL) -#define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 (0x43UL) - -/* trgm0_filter mux definitions */ -#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) - -/* trgm1_filter mux definitions */ -#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) - -/* trgm2_filter mux definitions */ -#define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) - -/* trgm3_filter mux definitions */ -#define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) - -/* trgm0_dma mux definitions */ -#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) -#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) -#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) -#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) -#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) -#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) - -/* trgm1_dma mux definitions */ -#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) -#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) -#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) -#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) -#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) -#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) - -/* trgm2_dma mux definitions */ -#define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) -#define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) -#define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) -#define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) -#define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) -#define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) - -/* trgm3_dma mux definitions */ -#define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) -#define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) -#define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) -#define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) -#define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) -#define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) - - - -#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/soc_modules.list deleted file mode 100644 index b72d68e0496..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/soc_modules.list +++ /dev/null @@ -1,61 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_MULTICORE=y -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_SDM=y -HPMSOC_HAS_HPMSDK_ACMP=y -HPMSOC_HAS_HPMSDK_DAC=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_MCAN=y -HPMSOC_HAS_HPMSDK_WDG=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_PTPC=y -HPMSOC_HAS_HPMSDK_CRC=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMA=y -HPMSOC_HAS_HPMSDK_RNG=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_PWM=y -HPMSOC_HAS_HPMSDK_HALL=y -HPMSOC_HAS_HPMSDK_QEI=y -HPMSOC_HAS_HPMSDK_TRGM=y -HPMSOC_HAS_HPMSDK_PLA=y -HPMSOC_HAS_HPMSDK_SYNT=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_LIN=y -HPMSOC_HAS_HPMSDK_SDP=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PSEC=y -HPMSOC_HAS_HPMSDK_PMON=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_PLLCTLV2=y -HPMSOC_HAS_HPMSDK_TSNS=y -HPMSOC_HAS_HPMSDK_BACC=y -HPMSOC_HAS_HPMSDK_BPOR=y -HPMSOC_HAS_HPMSDK_BCFG=y -HPMSOC_HAS_HPMSDK_BUTN=y -HPMSOC_HAS_HPMSDK_BGPR=y -HPMSOC_HAS_HPMSDK_BSEC=y -HPMSOC_HAS_HPMSDK_RTC=y -HPMSOC_HAS_HPMSDK_BKEY=y -HPMSOC_HAS_HPMSDK_BMON=y -HPMSOC_HAS_HPMSDK_TAMP=y -HPMSOC_HAS_HPMSDK_MONO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/system.c deleted file mode 100644 index 3ea422c42ea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/system.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif - -#ifdef USE_S_MODE_IRQ - disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#else - disable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - - disable_irq_from_intc(); -#ifdef USE_S_MODE_IRQ - disable_s_irq_from_intc(); -#endif - - enable_plic_feature(); - enable_irq_from_intc(); - -#ifdef USE_S_MODE_IRQ - delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); - enable_s_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#endif -#else -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash.ld deleted file mode 100644 index 2e88e4af3f2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash.ld +++ /dev/null @@ -1,288 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index c9d2bcfc44f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash_xip.ld deleted file mode 100644 index a85f7d3ffed..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/flash_xip.ld +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - *(.tdata) - *(.tdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/ram.ld deleted file mode 100644 index 04de4e7d862..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/ram.ld +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x010A0000, LENGTH = 112K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/ram_core1.ld deleted file mode 100644 index 12819ba1e7a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/ram_core1.ld +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00020000, LENGTH = 128K - DLM (w) : ORIGIN = 0x000A0000, LENGTH = 96K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x000B8000, LENGTH = 32K - SHARE_RAM (w) : ORIGIN = 0x010BC000, LENGTH = 16K -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > DLM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > DLM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > DLM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > DLM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/start.S deleted file mode 100644 index 88e081d56b6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/gcc/start.S +++ /dev/null @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - la tp, __thread_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/flash_uf2.icf deleted file mode 100644 index a7a2e85d8d0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01080000 size 128k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x010A0000 size 112k]; /* AXI SRAM0 */ -define region SHARE_RAM = mem:[from 0x010BC000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/flash_xip.icf deleted file mode 100644 index d593d7ad98e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01080000 size 128k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x010A0000 size 112k]; -define region SHARE_RAM = mem:[from 0x010BC000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .nor_cfg_option, - section .boot_header, - section .fw_info_table, - section .dc_info - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/ram.icf deleted file mode 100644 index 6ac0ae85802..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/ram.icf +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01080000 size 128k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x010A0000 size 112k]; -define region SHARE_RAM = mem:[from 0x010BC000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/ram_core1.icf deleted file mode 100644 index b5113b97b8c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/ram_core1.icf +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00020000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x000A0000 size 96k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x000B8000 size 32k]; /* AXI SRAM */ -define region SHARE_RAM = mem:[from 0x010BC000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/startup.s deleted file mode 100644 index 81175908610..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/iar/startup.s +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - EXTERN _init_ext_ram -__iar_cstart_init_ext_ram: - la t0, SFE(SAFESTACK) - mv sp, t0 - call _init_ext_ram -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/reset.c deleted file mode 100644 index e3d725a1d7a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash.icf deleted file mode 100644 index 320b6411e83..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash.icf +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 1a04c8a0f5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash_xip.icf deleted file mode 100644 index add0edac923..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0xc00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/ram.icf deleted file mode 100644 index 25e51facc80..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/ram.icf +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01080000 size 128k]; -define region AXI_SRAM = [from 0x010A0000 size 112k]; -define region SHARE_RAM = [from 0x010BC000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/ram_core1.icf deleted file mode 100644 index f0c649e1ab1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/ram_core1.icf +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00020000 size 128k]; /* ILM */ -define region DLM = [from 0x000A0000 size 96k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x000B8000 size 32k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x010BC000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in DLM { block cherryusb_usbh_class_info }; -place in DLM { block framebuffer }; -place in DLM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/startup.s deleted file mode 100644 index b57cbe4a7f2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/segger/startup.s +++ /dev/null @@ -1,413 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/trap.c deleted file mode 100644 index 3df45f565c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/trap.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ -#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ -#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ -#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ -#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ -#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -__attribute__((weak)) long exception_s_handler(long cause, long epc) -{ - (void) cause; - return epc; -} - -__attribute__((weak)) void swi_s_isr(void) -{ -} - -__attribute__((weak)) void mchtmr_s_isr(void) -{ -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} - - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_s_table[]; -HPM_ATTR_SUPERVISOR_INTERRUPT -#endif -void irq_handler_s_trap(void) -{ - long scause = read_csr(CSR_SCAUSE); - long sepc = read_csr(CSR_SEPC); - long sstatus = read_csr(CSR_SSTATUS); - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { - /* Machine timer interrupt */ - mchtmr_s_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_s_global_irq(CSR_SSTATUS_SIE_MASK); -#endif - ((isr_func_t)__vector_s_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); - - } -#endif - - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_s_isr(); - intc_s_complete_swi(); - } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - sepc += 4; - } else { - sepc = exception_s_handler(scause, sepc); - } - - /* Restore CSR */ - write_csr(CSR_SSTATUS, sstatus); - write_csr(CSR_SEPC, sepc); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/vectors.h deleted file mode 100644 index c53d6bbabaf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/HPM6280/toolchains/vectors.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(9) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 8 /* GPIO1_A IRQ handler */ - IRQ_DEFAULT_HANDLER 9 /* GPIO1_B IRQ handler */ - IRQ_DEFAULT_HANDLER 10 /* GPIO1_C IRQ handler */ - IRQ_DEFAULT_HANDLER 11 /* GPIO1_D IRQ handler */ - IRQ_DEFAULT_HANDLER 12 /* GPIO1_X IRQ handler */ - IRQ_DEFAULT_HANDLER 13 /* GPIO1_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* GPIO1_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* ADC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* ADC2 IRQ handler */ - IRQ_DEFAULT_HANDLER 18 /* SDFM IRQ handler */ - IRQ_DEFAULT_HANDLER 19 /* DAC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 20 /* DAC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 21 /* ACMP[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 22 /* ACMP[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 23 /* ACMP[2] IRQ handler */ - IRQ_DEFAULT_HANDLER 24 /* ACMP[3] IRQ handler */ - IRQ_DEFAULT_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* UART4 IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* UART5 IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* UART6 IRQ handler */ - IRQ_DEFAULT_HANDLER 36 /* UART7 IRQ handler */ - IRQ_DEFAULT_HANDLER 37 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 38 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 39 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_HANDLER 40 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_HANDLER 41 /* PTPC IRQ handler */ - IRQ_DEFAULT_HANDLER 42 /* WDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 43 /* WDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 44 /* TSNS IRQ handler */ - IRQ_DEFAULT_HANDLER 45 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 46 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 47 /* MBX1A IRQ handler */ - IRQ_DEFAULT_HANDLER 48 /* MBX1B IRQ handler */ - IRQ_DEFAULT_HANDLER 49 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 50 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 51 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 54 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 57 /* PWM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* HALL0 IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* QEI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 60 /* PWM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 61 /* HALL1 IRQ handler */ - IRQ_DEFAULT_HANDLER 62 /* QEI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* PWM2 IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* HALL2 IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* QEI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* PWM3 IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* HALL3 IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* QEI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* SDP IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* XDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 73 /* RNG IRQ handler */ - IRQ_DEFAULT_HANDLER 74 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 75 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 76 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 77 /* PWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 78 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 79 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 80 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 81 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 82 /* RTC IRQ handler */ - IRQ_DEFAULT_HANDLER 83 /* BUTN IRQ handler */ - IRQ_DEFAULT_HANDLER 84 /* BGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 85 /* BVIO IRQ handler */ - IRQ_DEFAULT_HANDLER 86 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 87 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 88 /* DEBUG[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 89 /* DEBUG[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 90 /* LIN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 91 /* LIN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 92 /* LIN2 IRQ handler */ - IRQ_DEFAULT_HANDLER 93 /* LIN3 IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(9) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ - IRQ_HANDLER 15 /* ADC0 IRQ handler */ - IRQ_HANDLER 16 /* ADC1 IRQ handler */ - IRQ_HANDLER 17 /* ADC2 IRQ handler */ - IRQ_HANDLER 18 /* SDFM IRQ handler */ - IRQ_HANDLER 19 /* DAC0 IRQ handler */ - IRQ_HANDLER 20 /* DAC1 IRQ handler */ - IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ - IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ - IRQ_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_HANDLER 29 /* UART0 IRQ handler */ - IRQ_HANDLER 30 /* UART1 IRQ handler */ - IRQ_HANDLER 31 /* UART2 IRQ handler */ - IRQ_HANDLER 32 /* UART3 IRQ handler */ - IRQ_HANDLER 33 /* UART4 IRQ handler */ - IRQ_HANDLER 34 /* UART5 IRQ handler */ - IRQ_HANDLER 35 /* UART6 IRQ handler */ - IRQ_HANDLER 36 /* UART7 IRQ handler */ - IRQ_HANDLER 37 /* MCAN0 IRQ handler */ - IRQ_HANDLER 38 /* MCAN1 IRQ handler */ - IRQ_HANDLER 39 /* MCAN2 IRQ handler */ - IRQ_HANDLER 40 /* MCAN3 IRQ handler */ - IRQ_HANDLER 41 /* PTPC IRQ handler */ - IRQ_HANDLER 42 /* WDG0 IRQ handler */ - IRQ_HANDLER 43 /* WDG1 IRQ handler */ - IRQ_HANDLER 44 /* TSNS IRQ handler */ - IRQ_HANDLER 45 /* MBX0A IRQ handler */ - IRQ_HANDLER 46 /* MBX0B IRQ handler */ - IRQ_HANDLER 47 /* MBX1A IRQ handler */ - IRQ_HANDLER 48 /* MBX1B IRQ handler */ - IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 53 /* I2C0 IRQ handler */ - IRQ_HANDLER 54 /* I2C1 IRQ handler */ - IRQ_HANDLER 55 /* I2C2 IRQ handler */ - IRQ_HANDLER 56 /* I2C3 IRQ handler */ - IRQ_HANDLER 57 /* PWM0 IRQ handler */ - IRQ_HANDLER 58 /* HALL0 IRQ handler */ - IRQ_HANDLER 59 /* QEI0 IRQ handler */ - IRQ_HANDLER 60 /* PWM1 IRQ handler */ - IRQ_HANDLER 61 /* HALL1 IRQ handler */ - IRQ_HANDLER 62 /* QEI1 IRQ handler */ - IRQ_HANDLER 63 /* PWM2 IRQ handler */ - IRQ_HANDLER 64 /* HALL2 IRQ handler */ - IRQ_HANDLER 65 /* QEI2 IRQ handler */ - IRQ_HANDLER 66 /* PWM3 IRQ handler */ - IRQ_HANDLER 67 /* HALL3 IRQ handler */ - IRQ_HANDLER 68 /* QEI3 IRQ handler */ - IRQ_HANDLER 69 /* SDP IRQ handler */ - IRQ_HANDLER 70 /* XPI0 IRQ handler */ - IRQ_HANDLER 71 /* XDMA IRQ handler */ - IRQ_HANDLER 72 /* HDMA IRQ handler */ - IRQ_HANDLER 73 /* RNG IRQ handler */ - IRQ_HANDLER 74 /* USB0 IRQ handler */ - IRQ_HANDLER 75 /* PSEC IRQ handler */ - IRQ_HANDLER 76 /* PGPIO IRQ handler */ - IRQ_HANDLER 77 /* PWDG IRQ handler */ - IRQ_HANDLER 78 /* PTMR IRQ handler */ - IRQ_HANDLER 79 /* PUART IRQ handler */ - IRQ_HANDLER 80 /* FUSE IRQ handler */ - IRQ_HANDLER 81 /* SECMON IRQ handler */ - IRQ_HANDLER 82 /* RTC IRQ handler */ - IRQ_HANDLER 83 /* BUTN IRQ handler */ - IRQ_HANDLER 84 /* BGPIO IRQ handler */ - IRQ_HANDLER 85 /* BVIO IRQ handler */ - IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 87 /* SYSCTL IRQ handler */ - IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ - IRQ_HANDLER 90 /* LIN0 IRQ handler */ - IRQ_HANDLER 91 /* LIN1 IRQ handler */ - IRQ_HANDLER 92 /* LIN2 IRQ handler */ - IRQ_HANDLER 93 /* LIN3 IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 9 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 10 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 11 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */ - IRQ_HANDLER 15 /* ADC0 IRQ handler */ - IRQ_HANDLER 16 /* ADC1 IRQ handler */ - IRQ_HANDLER 17 /* ADC2 IRQ handler */ - IRQ_HANDLER 18 /* SDFM IRQ handler */ - IRQ_HANDLER 19 /* DAC0 IRQ handler */ - IRQ_HANDLER 20 /* DAC1 IRQ handler */ - IRQ_HANDLER 21 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 22 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 23 /* ACMP[2] IRQ handler */ - IRQ_HANDLER 24 /* ACMP[3] IRQ handler */ - IRQ_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_HANDLER 29 /* UART0 IRQ handler */ - IRQ_HANDLER 30 /* UART1 IRQ handler */ - IRQ_HANDLER 31 /* UART2 IRQ handler */ - IRQ_HANDLER 32 /* UART3 IRQ handler */ - IRQ_HANDLER 33 /* UART4 IRQ handler */ - IRQ_HANDLER 34 /* UART5 IRQ handler */ - IRQ_HANDLER 35 /* UART6 IRQ handler */ - IRQ_HANDLER 36 /* UART7 IRQ handler */ - IRQ_HANDLER 37 /* MCAN0 IRQ handler */ - IRQ_HANDLER 38 /* MCAN1 IRQ handler */ - IRQ_HANDLER 39 /* MCAN2 IRQ handler */ - IRQ_HANDLER 40 /* MCAN3 IRQ handler */ - IRQ_HANDLER 41 /* PTPC IRQ handler */ - IRQ_HANDLER 42 /* WDG0 IRQ handler */ - IRQ_HANDLER 43 /* WDG1 IRQ handler */ - IRQ_HANDLER 44 /* TSNS IRQ handler */ - IRQ_HANDLER 45 /* MBX0A IRQ handler */ - IRQ_HANDLER 46 /* MBX0B IRQ handler */ - IRQ_HANDLER 47 /* MBX1A IRQ handler */ - IRQ_HANDLER 48 /* MBX1B IRQ handler */ - IRQ_HANDLER 49 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 50 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 51 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 52 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 53 /* I2C0 IRQ handler */ - IRQ_HANDLER 54 /* I2C1 IRQ handler */ - IRQ_HANDLER 55 /* I2C2 IRQ handler */ - IRQ_HANDLER 56 /* I2C3 IRQ handler */ - IRQ_HANDLER 57 /* PWM0 IRQ handler */ - IRQ_HANDLER 58 /* HALL0 IRQ handler */ - IRQ_HANDLER 59 /* QEI0 IRQ handler */ - IRQ_HANDLER 60 /* PWM1 IRQ handler */ - IRQ_HANDLER 61 /* HALL1 IRQ handler */ - IRQ_HANDLER 62 /* QEI1 IRQ handler */ - IRQ_HANDLER 63 /* PWM2 IRQ handler */ - IRQ_HANDLER 64 /* HALL2 IRQ handler */ - IRQ_HANDLER 65 /* QEI2 IRQ handler */ - IRQ_HANDLER 66 /* PWM3 IRQ handler */ - IRQ_HANDLER 67 /* HALL3 IRQ handler */ - IRQ_HANDLER 68 /* QEI3 IRQ handler */ - IRQ_HANDLER 69 /* SDP IRQ handler */ - IRQ_HANDLER 70 /* XPI0 IRQ handler */ - IRQ_HANDLER 71 /* XDMA IRQ handler */ - IRQ_HANDLER 72 /* HDMA IRQ handler */ - IRQ_HANDLER 73 /* RNG IRQ handler */ - IRQ_HANDLER 74 /* USB0 IRQ handler */ - IRQ_HANDLER 75 /* PSEC IRQ handler */ - IRQ_HANDLER 76 /* PGPIO IRQ handler */ - IRQ_HANDLER 77 /* PWDG IRQ handler */ - IRQ_HANDLER 78 /* PTMR IRQ handler */ - IRQ_HANDLER 79 /* PUART IRQ handler */ - IRQ_HANDLER 80 /* FUSE IRQ handler */ - IRQ_HANDLER 81 /* SECMON IRQ handler */ - IRQ_HANDLER 82 /* RTC IRQ handler */ - IRQ_HANDLER 83 /* BUTN IRQ handler */ - IRQ_HANDLER 84 /* BGPIO IRQ handler */ - IRQ_HANDLER 85 /* BVIO IRQ handler */ - IRQ_HANDLER 86 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 87 /* SYSCTL IRQ handler */ - IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */ - IRQ_HANDLER 90 /* LIN0 IRQ handler */ - IRQ_HANDLER 91 /* LIN1 IRQ handler */ - IRQ_HANDLER 92 /* LIN2 IRQ handler */ - IRQ_HANDLER 93 /* LIN3 IRQ handler */ - -#endif - -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_S_HANDLER macro - dc32 default_isr_s_\1 - endm - -IRQ_DEFAULT_S_HANDLER macro - PUBWEAK default_isr_s_\1 -default_isr_s_\1 - j default_irq_s_handler - endm - - SECTION `.isr_s_vector`:CODE:ROOT(9) - PUBWEAK default_irq_s_handler -default_irq_s_handler - j default_irq_s_handler - IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_S_HANDLER 8 /* GPIO1_A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 9 /* GPIO1_B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 10 /* GPIO1_C IRQ handler */ - IRQ_DEFAULT_S_HANDLER 11 /* GPIO1_D IRQ handler */ - IRQ_DEFAULT_S_HANDLER 12 /* GPIO1_X IRQ handler */ - IRQ_DEFAULT_S_HANDLER 13 /* GPIO1_Y IRQ handler */ - IRQ_DEFAULT_S_HANDLER 14 /* GPIO1_Z IRQ handler */ - IRQ_DEFAULT_S_HANDLER 15 /* ADC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 16 /* ADC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 17 /* ADC2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 18 /* SDFM IRQ handler */ - IRQ_DEFAULT_S_HANDLER 19 /* DAC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 20 /* DAC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 21 /* ACMP[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 22 /* ACMP[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 23 /* ACMP[2] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 24 /* ACMP[3] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 29 /* UART0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 30 /* UART1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 31 /* UART2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 32 /* UART3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 33 /* UART4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 34 /* UART5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 35 /* UART6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 36 /* UART7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 37 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 38 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 39 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 40 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 41 /* PTPC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 42 /* WDG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 43 /* WDG1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 44 /* TSNS IRQ handler */ - IRQ_DEFAULT_S_HANDLER 45 /* MBX0A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 46 /* MBX0B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 47 /* MBX1A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 48 /* MBX1B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 49 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 50 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 51 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 52 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 53 /* I2C0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 54 /* I2C1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 55 /* I2C2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 56 /* I2C3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 57 /* PWM0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 58 /* HALL0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 59 /* QEI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 60 /* PWM1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 61 /* HALL1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 62 /* QEI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 63 /* PWM2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 64 /* HALL2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 65 /* QEI2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 66 /* PWM3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 67 /* HALL3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 68 /* QEI3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 69 /* SDP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 70 /* XPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 71 /* XDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 72 /* HDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 73 /* RNG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 74 /* USB0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 75 /* PSEC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 76 /* PGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 77 /* PWDG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 78 /* PTMR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 79 /* PUART IRQ handler */ - IRQ_DEFAULT_S_HANDLER 80 /* FUSE IRQ handler */ - IRQ_DEFAULT_S_HANDLER 81 /* SECMON IRQ handler */ - IRQ_DEFAULT_S_HANDLER 82 /* RTC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 83 /* BUTN IRQ handler */ - IRQ_DEFAULT_S_HANDLER 84 /* BGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 85 /* BVIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 86 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_S_HANDLER 87 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_S_HANDLER 88 /* DEBUG[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 89 /* DEBUG[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 90 /* LIN0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 91 /* LIN1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 92 /* LIN2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 93 /* LIN3 IRQ handler */ - - EXTERN irq_handler_s_trap - SECTION `.vector_s_table`:CODE:ROOT(9) - PUBLIC __vector_s_table - DATA - -__vector_s_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_s_trap -#endif - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 8 /* GPIO1_A IRQ handler */ - IRQ_S_HANDLER 9 /* GPIO1_B IRQ handler */ - IRQ_S_HANDLER 10 /* GPIO1_C IRQ handler */ - IRQ_S_HANDLER 11 /* GPIO1_D IRQ handler */ - IRQ_S_HANDLER 12 /* GPIO1_X IRQ handler */ - IRQ_S_HANDLER 13 /* GPIO1_Y IRQ handler */ - IRQ_S_HANDLER 14 /* GPIO1_Z IRQ handler */ - IRQ_S_HANDLER 15 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 16 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 17 /* ADC2 IRQ handler */ - IRQ_S_HANDLER 18 /* SDFM IRQ handler */ - IRQ_S_HANDLER 19 /* DAC0 IRQ handler */ - IRQ_S_HANDLER 20 /* DAC1 IRQ handler */ - IRQ_S_HANDLER 21 /* ACMP[0] IRQ handler */ - IRQ_S_HANDLER 22 /* ACMP[1] IRQ handler */ - IRQ_S_HANDLER 23 /* ACMP[2] IRQ handler */ - IRQ_S_HANDLER 24 /* ACMP[3] IRQ handler */ - IRQ_S_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 29 /* UART0 IRQ handler */ - IRQ_S_HANDLER 30 /* UART1 IRQ handler */ - IRQ_S_HANDLER 31 /* UART2 IRQ handler */ - IRQ_S_HANDLER 32 /* UART3 IRQ handler */ - IRQ_S_HANDLER 33 /* UART4 IRQ handler */ - IRQ_S_HANDLER 34 /* UART5 IRQ handler */ - IRQ_S_HANDLER 35 /* UART6 IRQ handler */ - IRQ_S_HANDLER 36 /* UART7 IRQ handler */ - IRQ_S_HANDLER 37 /* MCAN0 IRQ handler */ - IRQ_S_HANDLER 38 /* MCAN1 IRQ handler */ - IRQ_S_HANDLER 39 /* MCAN2 IRQ handler */ - IRQ_S_HANDLER 40 /* MCAN3 IRQ handler */ - IRQ_S_HANDLER 41 /* PTPC IRQ handler */ - IRQ_S_HANDLER 42 /* WDG0 IRQ handler */ - IRQ_S_HANDLER 43 /* WDG1 IRQ handler */ - IRQ_S_HANDLER 44 /* TSNS IRQ handler */ - IRQ_S_HANDLER 45 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 46 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 47 /* MBX1A IRQ handler */ - IRQ_S_HANDLER 48 /* MBX1B IRQ handler */ - IRQ_S_HANDLER 49 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 50 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 51 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 52 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 53 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 54 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 55 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 56 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 57 /* PWM0 IRQ handler */ - IRQ_S_HANDLER 58 /* HALL0 IRQ handler */ - IRQ_S_HANDLER 59 /* QEI0 IRQ handler */ - IRQ_S_HANDLER 60 /* PWM1 IRQ handler */ - IRQ_S_HANDLER 61 /* HALL1 IRQ handler */ - IRQ_S_HANDLER 62 /* QEI1 IRQ handler */ - IRQ_S_HANDLER 63 /* PWM2 IRQ handler */ - IRQ_S_HANDLER 64 /* HALL2 IRQ handler */ - IRQ_S_HANDLER 65 /* QEI2 IRQ handler */ - IRQ_S_HANDLER 66 /* PWM3 IRQ handler */ - IRQ_S_HANDLER 67 /* HALL3 IRQ handler */ - IRQ_S_HANDLER 68 /* QEI3 IRQ handler */ - IRQ_S_HANDLER 69 /* SDP IRQ handler */ - IRQ_S_HANDLER 70 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 71 /* XDMA IRQ handler */ - IRQ_S_HANDLER 72 /* HDMA IRQ handler */ - IRQ_S_HANDLER 73 /* RNG IRQ handler */ - IRQ_S_HANDLER 74 /* USB0 IRQ handler */ - IRQ_S_HANDLER 75 /* PSEC IRQ handler */ - IRQ_S_HANDLER 76 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 77 /* PWDG IRQ handler */ - IRQ_S_HANDLER 78 /* PTMR IRQ handler */ - IRQ_S_HANDLER 79 /* PUART IRQ handler */ - IRQ_S_HANDLER 80 /* FUSE IRQ handler */ - IRQ_S_HANDLER 81 /* SECMON IRQ handler */ - IRQ_S_HANDLER 82 /* RTC IRQ handler */ - IRQ_S_HANDLER 83 /* BUTN IRQ handler */ - IRQ_S_HANDLER 84 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 85 /* BVIO IRQ handler */ - IRQ_S_HANDLER 86 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 87 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 88 /* DEBUG[0] IRQ handler */ - IRQ_S_HANDLER 89 /* DEBUG[1] IRQ handler */ - IRQ_S_HANDLER 90 /* LIN0 IRQ handler */ - IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ - IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ - IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ - -#else - -.global default_irq_s_handler -.weak default_irq_s_handler -.align 2 -default_irq_s_handler: -1: j 1b - -.macro IRQ_S_HANDLER irq - .weak default_isr_s_\irq - .set default_isr_s_\irq, default_irq_s_handler - .long default_isr_s_\irq -.endm - -.section .vector_s_table, "a" -.global __vector_s_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_s_trap, freertos_risc_v_trap_handler -#else - .set default_isr_s_trap, irq_handler_s_trap -#endif - -__vector_s_table: - .weak default_isr_s_trap - .long default_isr_s_trap - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 8 /* GPIO1_A IRQ handler */ - IRQ_S_HANDLER 9 /* GPIO1_B IRQ handler */ - IRQ_S_HANDLER 10 /* GPIO1_C IRQ handler */ - IRQ_S_HANDLER 11 /* GPIO1_D IRQ handler */ - IRQ_S_HANDLER 12 /* GPIO1_X IRQ handler */ - IRQ_S_HANDLER 13 /* GPIO1_Y IRQ handler */ - IRQ_S_HANDLER 14 /* GPIO1_Z IRQ handler */ - IRQ_S_HANDLER 15 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 16 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 17 /* ADC2 IRQ handler */ - IRQ_S_HANDLER 18 /* SDFM IRQ handler */ - IRQ_S_HANDLER 19 /* DAC0 IRQ handler */ - IRQ_S_HANDLER 20 /* DAC1 IRQ handler */ - IRQ_S_HANDLER 21 /* ACMP[0] IRQ handler */ - IRQ_S_HANDLER 22 /* ACMP[1] IRQ handler */ - IRQ_S_HANDLER 23 /* ACMP[2] IRQ handler */ - IRQ_S_HANDLER 24 /* ACMP[3] IRQ handler */ - IRQ_S_HANDLER 25 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 26 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 27 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 28 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 29 /* UART0 IRQ handler */ - IRQ_S_HANDLER 30 /* UART1 IRQ handler */ - IRQ_S_HANDLER 31 /* UART2 IRQ handler */ - IRQ_S_HANDLER 32 /* UART3 IRQ handler */ - IRQ_S_HANDLER 33 /* UART4 IRQ handler */ - IRQ_S_HANDLER 34 /* UART5 IRQ handler */ - IRQ_S_HANDLER 35 /* UART6 IRQ handler */ - IRQ_S_HANDLER 36 /* UART7 IRQ handler */ - IRQ_S_HANDLER 37 /* MCAN0 IRQ handler */ - IRQ_S_HANDLER 38 /* MCAN1 IRQ handler */ - IRQ_S_HANDLER 39 /* MCAN2 IRQ handler */ - IRQ_S_HANDLER 40 /* MCAN3 IRQ handler */ - IRQ_S_HANDLER 41 /* PTPC IRQ handler */ - IRQ_S_HANDLER 42 /* WDG0 IRQ handler */ - IRQ_S_HANDLER 43 /* WDG1 IRQ handler */ - IRQ_S_HANDLER 44 /* TSNS IRQ handler */ - IRQ_S_HANDLER 45 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 46 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 47 /* MBX1A IRQ handler */ - IRQ_S_HANDLER 48 /* MBX1B IRQ handler */ - IRQ_S_HANDLER 49 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 50 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 51 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 52 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 53 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 54 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 55 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 56 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 57 /* PWM0 IRQ handler */ - IRQ_S_HANDLER 58 /* HALL0 IRQ handler */ - IRQ_S_HANDLER 59 /* QEI0 IRQ handler */ - IRQ_S_HANDLER 60 /* PWM1 IRQ handler */ - IRQ_S_HANDLER 61 /* HALL1 IRQ handler */ - IRQ_S_HANDLER 62 /* QEI1 IRQ handler */ - IRQ_S_HANDLER 63 /* PWM2 IRQ handler */ - IRQ_S_HANDLER 64 /* HALL2 IRQ handler */ - IRQ_S_HANDLER 65 /* QEI2 IRQ handler */ - IRQ_S_HANDLER 66 /* PWM3 IRQ handler */ - IRQ_S_HANDLER 67 /* HALL3 IRQ handler */ - IRQ_S_HANDLER 68 /* QEI3 IRQ handler */ - IRQ_S_HANDLER 69 /* SDP IRQ handler */ - IRQ_S_HANDLER 70 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 71 /* XDMA IRQ handler */ - IRQ_S_HANDLER 72 /* HDMA IRQ handler */ - IRQ_S_HANDLER 73 /* RNG IRQ handler */ - IRQ_S_HANDLER 74 /* USB0 IRQ handler */ - IRQ_S_HANDLER 75 /* PSEC IRQ handler */ - IRQ_S_HANDLER 76 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 77 /* PWDG IRQ handler */ - IRQ_S_HANDLER 78 /* PTMR IRQ handler */ - IRQ_S_HANDLER 79 /* PUART IRQ handler */ - IRQ_S_HANDLER 80 /* FUSE IRQ handler */ - IRQ_S_HANDLER 81 /* SECMON IRQ handler */ - IRQ_S_HANDLER 82 /* RTC IRQ handler */ - IRQ_S_HANDLER 83 /* BUTN IRQ handler */ - IRQ_S_HANDLER 84 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 85 /* BVIO IRQ handler */ - IRQ_S_HANDLER 86 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 87 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 88 /* DEBUG[0] IRQ handler */ - IRQ_S_HANDLER 89 /* DEBUG[1] IRQ handler */ - IRQ_S_HANDLER 90 /* LIN0 IRQ handler */ - IRQ_S_HANDLER 91 /* LIN1 IRQ handler */ - IRQ_S_HANDLER 92 /* LIN2 IRQ handler */ - IRQ_S_HANDLER 93 /* LIN3 IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_acmp_regs.h deleted file mode 100644 index 9f7e0b6d9cd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_acmp_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ACMP_H -#define HPM_ACMP_H - -typedef struct { - struct { - __RW uint32_t CFG; /* 0x0: Configure Register */ - __RW uint32_t DACCFG; /* 0x4: DAC configure register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t SR; /* 0x10: Status register */ - __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */ - __RW uint32_t DMAEN; /* 0x18: DMA request enable register */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - } CHANNEL[4]; -} ACMP_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CFG */ -/* - * HYST (RW) - * - * This bitfield configure the comparator hysteresis. - * 00: Hysteresis level 0 - * 01: Hysteresis level 1 - * 10: Hysteresis level 2 - * 11: Hysteresis level 3 - */ -#define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) -#define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) -#define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) -#define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) - -/* - * DACEN (RW) - * - * This bit enable the comparator internal DAC - * 0: DAC disabled - * 1: DAC enabled - */ -#define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) -#define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) -#define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) -#define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) - -/* - * HPMODE (RW) - * - * This bit enable the comparator high performance mode. - * 0: HP mode disabled - * 1: HP mode enabled - */ -#define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) -#define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) -#define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) -#define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) - -/* - * CMPEN (RW) - * - * This bit enable the comparator. - * 0: ACMP disabled - * 1: ACMP enabled - */ -#define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) -#define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) -#define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) -#define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) - -/* - * MINSEL (RW) - * - * PIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) -#define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) -#define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) -#define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) - -/* - * PINSEL (RW) - * - * MIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) -#define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) -#define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) -#define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) - -/* - * CMPOEN (RW) - * - * This bit enable the comparator output on pad. - * 0: ACMP output disabled - * 1: ACMP output enabled - */ -#define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) -#define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) -#define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) -#define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) - -/* - * FLTBYPS (RW) - * - * This bit bypass the comparator output digital filter. - * 0: The ACMP output need pass digital filter - * 1: The ACMP output digital filter is bypassed. - */ -#define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) -#define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) -#define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) -#define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) - -/* - * WINEN (RW) - * - * This bit enable the comparator window mode. - * 0: Window mode is disabled - * 1: Window mode is enabled - */ -#define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) -#define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) -#define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) -#define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) - -/* - * OPOL (RW) - * - * The output polarity control bit. - * 0: The ACMP output remain un-changed. - * 1: The ACMP output is inverted. - */ -#define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) -#define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) -#define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) -#define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) - -/* - * FLTMODE (RW) - * - * This bitfield define the ACMP output digital filter mode: - * 000-bypass - * 100-change immediately; - * 101-change after filter; - * 110-stalbe low; - * 111-stable high - */ -#define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) -#define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) -#define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) -#define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) - -/* - * SYNCEN (RW) - * - * This bit enable the comparator output synchronization. - * 0: ACMP output not synchronized with ACMP clock. - * 1: ACMP output synchronized with ACMP clock. - */ -#define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) -#define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) -#define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) -#define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) - -/* - * FLTLEN (RW) - * - * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - */ -#define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) -#define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) -#define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) -#define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DACCFG */ -/* - * DACCFG (RW) - * - * 8bit DAC digital value output to analog block - */ -#define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) -#define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) -#define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) -#define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: SR */ -/* - * FEDGF (RW) - * - * Output falling edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) -#define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) -#define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) -#define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) - -/* - * REDGF (RW) - * - * Output rising edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) -#define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) -#define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) -#define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: IRQEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DMAEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) - - - -/* CHANNEL register group index macro definition */ -#define ACMP_CHANNEL_CHN0 (0UL) -#define ACMP_CHANNEL_CHN1 (1UL) -#define ACMP_CHANNEL_CHN2 (2UL) -#define ACMP_CHANNEL_CHN3 (3UL) - - -#endif /* HPM_ACMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_adc16_regs.h deleted file mode 100644 index f4f754a8910..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_adc16_regs.h +++ /dev/null @@ -1,975 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC16_H -#define HPM_ADC16_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ - __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint8_t RESERVED3[4]; /* 0x808 - 0x80B: Reserved */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __R uint8_t RESERVED4[944]; /* 0x850 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[16]; - __R uint8_t RESERVED5[768]; /* 0xD00 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */ - __R uint8_t RESERVED6[196]; /* 0x1040 - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED7[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __R uint8_t RESERVED8[232]; /* 0x1118 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __R uint8_t RESERVED9[12]; /* 0x1204 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ - __R uint8_t RESERVED10[492]; /* 0x1214 - 0x13FF: Reserved */ - __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ - __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ - __R uint8_t RESERVED11[24]; /* 0x1448 - 0x145F: Reserved */ - __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ -} ADC16_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) -#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC16_CONFIG_INTEN3_SHIFT (29U) -#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) -#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC16_CONFIG_CHAN3_SHIFT (24U) -#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) -#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC16_CONFIG_INTEN2_SHIFT (21U) -#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) -#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC16_CONFIG_CHAN2_SHIFT (16U) -#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) -#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC16_CONFIG_INTEN1_MASK (0x2000U) -#define ADC16_CONFIG_INTEN1_SHIFT (13U) -#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) -#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC16_CONFIG_CHAN1_SHIFT (8U) -#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) -#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) - -/* - * QUEUE_EN (RW) - * - * preemption queue enable control - */ -#define ADC16_CONFIG_QUEUE_EN_MASK (0x40U) -#define ADC16_CONFIG_QUEUE_EN_SHIFT (6U) -#define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK) -#define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC16_CONFIG_INTEN0_MASK (0x20U) -#define ADC16_CONFIG_INTEN0_SHIFT (5U) -#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) -#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC16_CONFIG_CHAN0_MASK (0x1FU) -#define ADC16_CONFIG_CHAN0_SHIFT (0U) -#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) -#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC16_BUS_RESULT_VALID_SHIFT (16U) -#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) -#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) -#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) -#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample clock number - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); - * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - */ -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* - * PORT3_REALTIME (RW) - * - * set to enable trg queue stop other queues - */ -#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) -#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) -#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) -#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) -#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) -#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) -#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) -#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_STS_WDOG_MASK (0xFFFFU) -#define ADC16_INT_STS_WDOG_SHIFT (0U) -#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) -#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) -#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) -#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) -#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) -#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) -#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) -#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_EN_WDOG_MASK (0xFFFFU) -#define ADC16_INT_EN_WDOG_SHIFT (0U) -#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) -#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * ADC_CLK_ON (RW) - * - * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. - * MUST set clock_period to 0 or 1 for adc16 reg access - */ -#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) -#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC16_ANA_STATUS_CALON_MASK (0x80U) -#define ADC16_ANA_STATUS_CALON_SHIFT (7U) -#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) -#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) - -/* Bitfield definition for register array: ADC16_PARAMS */ -/* - * PARAM_VAL (RW) - * - */ -#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) -#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG0 */ -/* - * REG_EN (RW) - * - * set to enable regulator - */ -#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) -#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) -#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) -#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) - -/* - * BANDGAP_EN (RW) - * - * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - */ -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) - -/* - * CAL_AVG_CFG (RW) - * - * for average the calibration result. - * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; - * 4- 16 loops; 5-32 loops; others reserved - */ -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) - -/* - * PREEMPT_EN (RW) - * - * set to enable preemption feature - */ -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) - -/* - * CONV_PARAM (RW) - * - * conversion parameter - */ -#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG1 */ -/* - * COV_END_CNT (RW) - * - * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number+1). - */ -#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC16_CONFIG_TRG0A (0UL) -#define ADC16_CONFIG_TRG0B (1UL) -#define ADC16_CONFIG_TRG0C (2UL) -#define ADC16_CONFIG_TRG1A (3UL) -#define ADC16_CONFIG_TRG1B (4UL) -#define ADC16_CONFIG_TRG1C (5UL) -#define ADC16_CONFIG_TRG2A (6UL) -#define ADC16_CONFIG_TRG2B (7UL) -#define ADC16_CONFIG_TRG2C (8UL) -#define ADC16_CONFIG_TRG3A (9UL) -#define ADC16_CONFIG_TRG3B (10UL) -#define ADC16_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC16_BUS_RESULT_CHN0 (0UL) -#define ADC16_BUS_RESULT_CHN1 (1UL) -#define ADC16_BUS_RESULT_CHN2 (2UL) -#define ADC16_BUS_RESULT_CHN3 (3UL) -#define ADC16_BUS_RESULT_CHN4 (4UL) -#define ADC16_BUS_RESULT_CHN5 (5UL) -#define ADC16_BUS_RESULT_CHN6 (6UL) -#define ADC16_BUS_RESULT_CHN7 (7UL) -#define ADC16_BUS_RESULT_CHN8 (8UL) -#define ADC16_BUS_RESULT_CHN9 (9UL) -#define ADC16_BUS_RESULT_CHN10 (10UL) -#define ADC16_BUS_RESULT_CHN11 (11UL) -#define ADC16_BUS_RESULT_CHN12 (12UL) -#define ADC16_BUS_RESULT_CHN13 (13UL) -#define ADC16_BUS_RESULT_CHN14 (14UL) -#define ADC16_BUS_RESULT_CHN15 (15UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC16_SEQ_QUE_CFG0 (0UL) -#define ADC16_SEQ_QUE_CFG1 (1UL) -#define ADC16_SEQ_QUE_CFG2 (2UL) -#define ADC16_SEQ_QUE_CFG3 (3UL) -#define ADC16_SEQ_QUE_CFG4 (4UL) -#define ADC16_SEQ_QUE_CFG5 (5UL) -#define ADC16_SEQ_QUE_CFG6 (6UL) -#define ADC16_SEQ_QUE_CFG7 (7UL) -#define ADC16_SEQ_QUE_CFG8 (8UL) -#define ADC16_SEQ_QUE_CFG9 (9UL) -#define ADC16_SEQ_QUE_CFG10 (10UL) -#define ADC16_SEQ_QUE_CFG11 (11UL) -#define ADC16_SEQ_QUE_CFG12 (12UL) -#define ADC16_SEQ_QUE_CFG13 (13UL) -#define ADC16_SEQ_QUE_CFG14 (14UL) -#define ADC16_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC16_PRD_CFG_CHN0 (0UL) -#define ADC16_PRD_CFG_CHN1 (1UL) -#define ADC16_PRD_CFG_CHN2 (2UL) -#define ADC16_PRD_CFG_CHN3 (3UL) -#define ADC16_PRD_CFG_CHN4 (4UL) -#define ADC16_PRD_CFG_CHN5 (5UL) -#define ADC16_PRD_CFG_CHN6 (6UL) -#define ADC16_PRD_CFG_CHN7 (7UL) -#define ADC16_PRD_CFG_CHN8 (8UL) -#define ADC16_PRD_CFG_CHN9 (9UL) -#define ADC16_PRD_CFG_CHN10 (10UL) -#define ADC16_PRD_CFG_CHN11 (11UL) -#define ADC16_PRD_CFG_CHN12 (12UL) -#define ADC16_PRD_CFG_CHN13 (13UL) -#define ADC16_PRD_CFG_CHN14 (14UL) -#define ADC16_PRD_CFG_CHN15 (15UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC16_SAMPLE_CFG_CHN0 (0UL) -#define ADC16_SAMPLE_CFG_CHN1 (1UL) -#define ADC16_SAMPLE_CFG_CHN2 (2UL) -#define ADC16_SAMPLE_CFG_CHN3 (3UL) -#define ADC16_SAMPLE_CFG_CHN4 (4UL) -#define ADC16_SAMPLE_CFG_CHN5 (5UL) -#define ADC16_SAMPLE_CFG_CHN6 (6UL) -#define ADC16_SAMPLE_CFG_CHN7 (7UL) -#define ADC16_SAMPLE_CFG_CHN8 (8UL) -#define ADC16_SAMPLE_CFG_CHN9 (9UL) -#define ADC16_SAMPLE_CFG_CHN10 (10UL) -#define ADC16_SAMPLE_CFG_CHN11 (11UL) -#define ADC16_SAMPLE_CFG_CHN12 (12UL) -#define ADC16_SAMPLE_CFG_CHN13 (13UL) -#define ADC16_SAMPLE_CFG_CHN14 (14UL) -#define ADC16_SAMPLE_CFG_CHN15 (15UL) - -/* ADC16_PARAMS register group index macro definition */ -#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) - - -#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bacc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bacc_regs.h deleted file mode 100644 index 597f50ed16c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bacc_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BACC_H -#define HPM_BACC_H - -typedef struct { - __RW uint32_t CONFIG; /* 0x0: Access timing for access */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t PRE_TIME; /* 0x8: Timing gap before rising edge */ - __RW uint32_t POST_TIME; /* 0xC: Timing gap after rising edge */ -} BACC_Type; - - -/* Bitfield definition for register: CONFIG */ -/* - * FAST_WRITE (RW) - * - * Use fast write - * 0: Write normally - * 1: boost write - */ -#define BACC_CONFIG_FAST_WRITE_MASK (0x20000000UL) -#define BACC_CONFIG_FAST_WRITE_SHIFT (29U) -#define BACC_CONFIG_FAST_WRITE_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_WRITE_SHIFT) & BACC_CONFIG_FAST_WRITE_MASK) -#define BACC_CONFIG_FAST_WRITE_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_WRITE_MASK) >> BACC_CONFIG_FAST_WRITE_SHIFT) - -/* - * FAST_READ (RW) - * - * Use fast read - * 0: Read normally - * 1: boost read - */ -#define BACC_CONFIG_FAST_READ_MASK (0x10000000UL) -#define BACC_CONFIG_FAST_READ_SHIFT (28U) -#define BACC_CONFIG_FAST_READ_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_READ_SHIFT) & BACC_CONFIG_FAST_READ_MASK) -#define BACC_CONFIG_FAST_READ_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_READ_MASK) >> BACC_CONFIG_FAST_READ_SHIFT) - -/* - * TIMING (RW) - * - * Time in APB clock cycles, for battery timing penerate - */ -#define BACC_CONFIG_TIMING_MASK (0xFFFFU) -#define BACC_CONFIG_TIMING_SHIFT (0U) -#define BACC_CONFIG_TIMING_SET(x) (((uint32_t)(x) << BACC_CONFIG_TIMING_SHIFT) & BACC_CONFIG_TIMING_MASK) -#define BACC_CONFIG_TIMING_GET(x) (((uint32_t)(x) & BACC_CONFIG_TIMING_MASK) >> BACC_CONFIG_TIMING_SHIFT) - -/* Bitfield definition for register: PRE_TIME */ -/* - * PRE_RATIO (RW) - * - * Ratio of guard band before rising edge - * 0: 0 - * 1: 1/32768 of low level width - * 2: 1/16384 of low level width - * 14: 1/4 of low level width - * 15: 1/2 of low level width - */ -#define BACC_PRE_TIME_PRE_RATIO_MASK (0xF0000UL) -#define BACC_PRE_TIME_PRE_RATIO_SHIFT (16U) -#define BACC_PRE_TIME_PRE_RATIO_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_RATIO_SHIFT) & BACC_PRE_TIME_PRE_RATIO_MASK) -#define BACC_PRE_TIME_PRE_RATIO_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_RATIO_MASK) >> BACC_PRE_TIME_PRE_RATIO_SHIFT) - -/* - * PRE_OFFSET (RW) - * - * guard band before rising edge - * this value will be added to ratio number - */ -#define BACC_PRE_TIME_PRE_OFFSET_MASK (0xFFFFU) -#define BACC_PRE_TIME_PRE_OFFSET_SHIFT (0U) -#define BACC_PRE_TIME_PRE_OFFSET_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_OFFSET_SHIFT) & BACC_PRE_TIME_PRE_OFFSET_MASK) -#define BACC_PRE_TIME_PRE_OFFSET_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_OFFSET_MASK) >> BACC_PRE_TIME_PRE_OFFSET_SHIFT) - -/* Bitfield definition for register: POST_TIME */ -/* - * POST_RATIO (RW) - * - * Ratio of guard band after rising edge - * 0: 0 - * 1: 1/32768 of high level width - * 2: 1/16384 of high level width - * 14: 1/4 of high level width - * 15: 1/2 of high level width - */ -#define BACC_POST_TIME_POST_RATIO_MASK (0xF0000UL) -#define BACC_POST_TIME_POST_RATIO_SHIFT (16U) -#define BACC_POST_TIME_POST_RATIO_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_RATIO_SHIFT) & BACC_POST_TIME_POST_RATIO_MASK) -#define BACC_POST_TIME_POST_RATIO_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_RATIO_MASK) >> BACC_POST_TIME_POST_RATIO_SHIFT) - -/* - * POST_OFFSET (RW) - * - * guard band after rising edge - * this value will be added to ratio number - */ -#define BACC_POST_TIME_POST_OFFSET_MASK (0xFFFFU) -#define BACC_POST_TIME_POST_OFFSET_SHIFT (0U) -#define BACC_POST_TIME_POST_OFFSET_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_OFFSET_SHIFT) & BACC_POST_TIME_POST_OFFSET_MASK) -#define BACC_POST_TIME_POST_OFFSET_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_OFFSET_MASK) >> BACC_POST_TIME_POST_OFFSET_SHIFT) - - - - -#endif /* HPM_BACC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bcfg_regs.h deleted file mode 100644 index 56355a5e012..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bcfg_regs.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BCFG_H -#define HPM_BCFG_H - -typedef struct { - __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ - __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ - __RW uint32_t CLK_CFG; /* 0x10: Clock config */ -} BCFG_Type; - - -/* Bitfield definition for register: VBG_CFG */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) -#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) -#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) -#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) - -/* - * LP_MODE (RW) - * - * Bandgap works in low power mode - * 0: not in low power mode - * 1: bandgap work in low power mode - */ -#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) -#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) -#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) -#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Bandgap works in power save mode - * 0: not in power save mode - * 1: bandgap work in power save mode - */ -#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) -#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) -#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) -#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) - -/* - * VBG_1P0 (RW) - * - * Bandgap 1.0V output trim - */ -#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) -#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) -#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) -#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) - -/* - * VBG_P65 (RW) - * - * Bandgap 0.65V output trim - */ -#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) -#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) -#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) -#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) - -/* - * VBG_P50 (RW) - * - * Bandgap 0.50V output trim - */ -#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) -#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) -#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) -#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) - -/* Bitfield definition for register: IRC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) -#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: XTAL32K_CFG */ -/* - * HYST_EN (RW) - * - * crystal 32k hysteres enable - */ -#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) -#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) -#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) -#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) - -/* - * GMSEL (RW) - * - * crystal 32k gm selection - */ -#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) -#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) -#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) -#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) - -/* - * CFG (RW) - * - * crystal 32k config - */ -#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) -#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) -#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) -#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) - -/* - * AMP (RW) - * - * crystal 32k amplifier - */ -#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) -#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) -#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) -#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) - -/* Bitfield definition for register: CLK_CFG */ -/* - * XTAL_SEL (RO) - * - * crystal selected - */ -#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) -#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) -#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) - -/* - * KEEP_IRC (RW) - * - * force irc32k run - */ -#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) -#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) -#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) -#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) - -/* - * FORCE_XTAL (RW) - * - * force switch to crystal - */ -#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) -#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) -#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) -#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) - - - - -#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bgpr_regs.h deleted file mode 100644 index 9d81aab19cf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bgpr_regs.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BGPR_H -#define HPM_BGPR_H - -typedef struct { - __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ -} BGPR_Type; - - -/* Bitfield definition for register array: GPR */ -/* - * DATA (RW) - * - * Generic control - */ -#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) -#define BGPR_GPR_DATA_SHIFT (0U) -#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) -#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) - - - -/* GPR register group index macro definition */ -#define BGPR_GPR_0 (0UL) -#define BGPR_GPR_1 (1UL) -#define BGPR_GPR_2 (2UL) -#define BGPR_GPR_3 (3UL) -#define BGPR_GPR_4 (4UL) -#define BGPR_GPR_5 (5UL) -#define BGPR_GPR_6 (6UL) -#define BGPR_GPR_7 (7UL) - - -#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bkey_regs.h deleted file mode 100644 index 1c82a4b90e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bkey_regs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BKEY_H -#define HPM_BKEY_H - -typedef struct { - struct { - __RW uint32_t DATA[8]; /* 0x0 - 0x1C: Key data */ - } KEY[2]; - __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ - __RW uint32_t SELECT; /* 0x48: Key selection */ -} BKEY_Type; - - -/* Bitfield definition for register of struct array KEY: 0 */ -/* - * DATA (RW) - * - * security key data - */ -#define BKEY_KEY_DATA_DATA_MASK (0xFFFFFFFFUL) -#define BKEY_KEY_DATA_DATA_SHIFT (0U) -#define BKEY_KEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_KEY_DATA_DATA_SHIFT) & BKEY_KEY_DATA_DATA_MASK) -#define BKEY_KEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_KEY_DATA_DATA_MASK) >> BKEY_KEY_DATA_DATA_SHIFT) - -/* Bitfield definition for register array: ECC */ -/* - * WLOCK (RW) - * - * write lock to key0 - * 0: write enable - * 1: write ignored - */ -#define BKEY_ECC_WLOCK_MASK (0x80000000UL) -#define BKEY_ECC_WLOCK_SHIFT (31U) -#define BKEY_ECC_WLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_WLOCK_SHIFT) & BKEY_ECC_WLOCK_MASK) -#define BKEY_ECC_WLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_WLOCK_MASK) >> BKEY_ECC_WLOCK_SHIFT) - -/* - * RLOCK (RW) - * - * read lock to key0 - * 0: key read enable - * 1: key always read as 0 - */ -#define BKEY_ECC_RLOCK_MASK (0x40000000UL) -#define BKEY_ECC_RLOCK_SHIFT (30U) -#define BKEY_ECC_RLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_RLOCK_SHIFT) & BKEY_ECC_RLOCK_MASK) -#define BKEY_ECC_RLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_RLOCK_MASK) >> BKEY_ECC_RLOCK_SHIFT) - -/* - * ECC (RW) - * - * Parity check bits for key0 - */ -#define BKEY_ECC_ECC_MASK (0xFFFFU) -#define BKEY_ECC_ECC_SHIFT (0U) -#define BKEY_ECC_ECC_SET(x) (((uint32_t)(x) << BKEY_ECC_ECC_SHIFT) & BKEY_ECC_ECC_MASK) -#define BKEY_ECC_ECC_GET(x) (((uint32_t)(x) & BKEY_ECC_ECC_MASK) >> BKEY_ECC_ECC_SHIFT) - -/* Bitfield definition for register: SELECT */ -/* - * SELECT (RW) - * - * select key, key0 treated as secure key, in non-scure mode, only key1 can be selected - * 0: select key0 in secure mode, key1 in non-secure mode - * 1: select key1 in secure or nonsecure mode - */ -#define BKEY_SELECT_SELECT_MASK (0x1U) -#define BKEY_SELECT_SELECT_SHIFT (0U) -#define BKEY_SELECT_SELECT_SET(x) (((uint32_t)(x) << BKEY_SELECT_SELECT_SHIFT) & BKEY_SELECT_SELECT_MASK) -#define BKEY_SELECT_SELECT_GET(x) (((uint32_t)(x) & BKEY_SELECT_SELECT_MASK) >> BKEY_SELECT_SELECT_SHIFT) - - - -/* DATA register group index macro definition */ -#define BKEY_KEY_DATA_0 (0UL) -#define BKEY_KEY_DATA_1 (1UL) -#define BKEY_KEY_DATA_2 (2UL) -#define BKEY_KEY_DATA_3 (3UL) -#define BKEY_KEY_DATA_4 (4UL) -#define BKEY_KEY_DATA_5 (5UL) -#define BKEY_KEY_DATA_6 (6UL) -#define BKEY_KEY_DATA_7 (7UL) - -/* KEY register group index macro definition */ -#define BKEY_KEY_0 (0UL) -#define BKEY_KEY_1 (1UL) - -/* ECC register group index macro definition */ -#define BKEY_ECC_KEY0 (0UL) -#define BKEY_ECC_KEY1 (1UL) - - -#endif /* HPM_BKEY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bmon_regs.h deleted file mode 100644 index f297a1dbb93..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bmon_regs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BMON_H -#define HPM_BMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - } MONITOR[2]; -} BMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define BMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define BMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define BMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ACTIVE_SHIFT) & BMON_MONITOR_CONTROL_ACTIVE_MASK) -#define BMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ACTIVE_MASK) >> BMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define BMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define BMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define BMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ENABLE_SHIFT) & BMON_MONITOR_CONTROL_ENABLE_MASK) -#define BMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ENABLE_MASK) >> BMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define BMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define BMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define BMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << BMON_MONITOR_STATUS_FLAG_SHIFT) & BMON_MONITOR_STATUS_FLAG_MASK) -#define BMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & BMON_MONITOR_STATUS_FLAG_MASK) >> BMON_MONITOR_STATUS_FLAG_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define BMON_MONITOR_GLITCH0 (0UL) -#define BMON_MONITOR_CLOCK0 (1UL) - - -#endif /* HPM_BMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bpor_regs.h deleted file mode 100644 index 4f48a15578d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bpor_regs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BPOR_H -#define HPM_BPOR_H - -typedef struct { - __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ - __RW uint32_t POR_SELECT; /* 0x4: Power on select */ - __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ - __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ -} BPOR_Type; - - -/* Bitfield definition for register: POR_CAUSE */ -/* - * CAUSE (RW) - * - * Power on cause, each bit represnts one cause, write 1 to clear each bit - * bit0: wakeup button - * bit1: security violation - * bit2: RTC alarm 0 - * bit3: RTC alarm 1 - * bit4: GPIO - */ -#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) -#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) -#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) -#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: POR_SELECT */ -/* - * SELECT (RW) - * - * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause - * bit0: wakeup button - * bit1: security violation - * bit2: RTC alarm 0 - * bit3: RTC alarm 1 - * bit4: GPIO - */ -#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) -#define BPOR_POR_SELECT_SELECT_SHIFT (0U) -#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) -#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) - -/* Bitfield definition for register: POR_CONFIG */ -/* - * RETENTION (RW) - * - * retention battery domain setting - * 0: battery reset on reset pin reset happen - * 1: battery domain retention when reset pin reset happen - */ -#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) -#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) -#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) -#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) - -/* Bitfield definition for register: POR_CONTROL */ -/* - * COUNTER (RW) - * - * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - */ -#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) -#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) -#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) -#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) - - - - -#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bsec_regs.h deleted file mode 100644 index 6167b47be78..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_bsec_regs.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BSEC_H -#define HPM_BSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ -} BSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * BATT_FAIL (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U) -#define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U) -#define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK) -#define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT) - -/* - * BATT_NSC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U) -#define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U) -#define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK) -#define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT) - -/* - * BATT_SEC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U) -#define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U) -#define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK) -#define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT) - -/* - * BATT_INS (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U) -#define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U) -#define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK) -#define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define BSEC_EVENT_EVENT_SHIFT (16U) -#define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT) - -/* - * BATT_ESC_NSC (RO) - * - * BATT is escalating non-secure event - */ -#define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U) -#define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U) -#define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT) - -/* - * BATT_ESC_SEC (RO) - * - * BATT is escalting ssecure event - */ -#define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U) -#define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U) -#define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT) - - - - -#endif /* HPM_BSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_butn_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_butn_regs.h deleted file mode 100644 index 03d711e0c58..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_butn_regs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BUTN_H -#define HPM_BUTN_H - -typedef struct { - __RW uint32_t BTN_STATUS; /* 0x0: Button status */ - __RW uint32_t BTN_IRQ_MASK; /* 0x4: Button interrupt mask */ - __RW uint32_t LED_INTENSE; /* 0x8: Debounce setting */ -} BUTN_Type; - - -/* Bitfield definition for register: BTN_STATUS */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_STATUS_XWCLICK_SHIFT (28U) -#define BUTN_BTN_STATUS_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XWCLICK_SHIFT) & BUTN_BTN_STATUS_XWCLICK_MASK) -#define BUTN_BTN_STATUS_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XWCLICK_MASK) >> BUTN_BTN_STATUS_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_STATUS_WCLICK_SHIFT (24U) -#define BUTN_BTN_STATUS_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WCLICK_SHIFT) & BUTN_BTN_STATUS_WCLICK_MASK) -#define BUTN_BTN_STATUS_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WCLICK_MASK) >> BUTN_BTN_STATUS_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_STATUS_XPCLICK_SHIFT (20U) -#define BUTN_BTN_STATUS_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XPCLICK_SHIFT) & BUTN_BTN_STATUS_XPCLICK_MASK) -#define BUTN_BTN_STATUS_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XPCLICK_MASK) >> BUTN_BTN_STATUS_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_STATUS_PCLICK_SHIFT (16U) -#define BUTN_BTN_STATUS_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PCLICK_SHIFT) & BUTN_BTN_STATUS_PCLICK_MASK) -#define BUTN_BTN_STATUS_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PCLICK_MASK) >> BUTN_BTN_STATUS_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_DBTN_MASK (0xF00U) -#define BUTN_BTN_STATUS_DBTN_SHIFT (8U) -#define BUTN_BTN_STATUS_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_DBTN_SHIFT) & BUTN_BTN_STATUS_DBTN_MASK) -#define BUTN_BTN_STATUS_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_DBTN_MASK) >> BUTN_BTN_STATUS_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_WBTN_MASK (0xF0U) -#define BUTN_BTN_STATUS_WBTN_SHIFT (4U) -#define BUTN_BTN_STATUS_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WBTN_SHIFT) & BUTN_BTN_STATUS_WBTN_MASK) -#define BUTN_BTN_STATUS_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WBTN_MASK) >> BUTN_BTN_STATUS_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_PBTN_MASK (0xFU) -#define BUTN_BTN_STATUS_PBTN_SHIFT (0U) -#define BUTN_BTN_STATUS_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PBTN_SHIFT) & BUTN_BTN_STATUS_PBTN_MASK) -#define BUTN_BTN_STATUS_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PBTN_MASK) >> BUTN_BTN_STATUS_PBTN_SHIFT) - -/* Bitfield definition for register: BTN_IRQ_MASK */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT (28U) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_IRQ_MASK_WCLICK_SHIFT (24U) -#define BUTN_BTN_IRQ_MASK_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) >> BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT (20U) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_IRQ_MASK_PCLICK_SHIFT (16U) -#define BUTN_BTN_IRQ_MASK_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) >> BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_DBTN_MASK (0xF00U) -#define BUTN_BTN_IRQ_MASK_DBTN_SHIFT (8U) -#define BUTN_BTN_IRQ_MASK_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_DBTN_SHIFT) & BUTN_BTN_IRQ_MASK_DBTN_MASK) -#define BUTN_BTN_IRQ_MASK_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_DBTN_MASK) >> BUTN_BTN_IRQ_MASK_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_WBTN_MASK (0xF0U) -#define BUTN_BTN_IRQ_MASK_WBTN_SHIFT (4U) -#define BUTN_BTN_IRQ_MASK_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WBTN_SHIFT) & BUTN_BTN_IRQ_MASK_WBTN_MASK) -#define BUTN_BTN_IRQ_MASK_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WBTN_MASK) >> BUTN_BTN_IRQ_MASK_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_PBTN_MASK (0xFU) -#define BUTN_BTN_IRQ_MASK_PBTN_SHIFT (0U) -#define BUTN_BTN_IRQ_MASK_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PBTN_SHIFT) & BUTN_BTN_IRQ_MASK_PBTN_MASK) -#define BUTN_BTN_IRQ_MASK_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PBTN_MASK) >> BUTN_BTN_IRQ_MASK_PBTN_SHIFT) - -/* Bitfield definition for register: LED_INTENSE */ -/* - * RLED (RW) - * - * Rbutton brightness 0 - */ -#define BUTN_LED_INTENSE_RLED_MASK (0xF0000UL) -#define BUTN_LED_INTENSE_RLED_SHIFT (16U) -#define BUTN_LED_INTENSE_RLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_RLED_SHIFT) & BUTN_LED_INTENSE_RLED_MASK) -#define BUTN_LED_INTENSE_RLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_RLED_MASK) >> BUTN_LED_INTENSE_RLED_SHIFT) - -/* - * PLED (RW) - * - * Pbutton brightness 0 - */ -#define BUTN_LED_INTENSE_PLED_MASK (0xFU) -#define BUTN_LED_INTENSE_PLED_SHIFT (0U) -#define BUTN_LED_INTENSE_PLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_PLED_SHIFT) & BUTN_LED_INTENSE_PLED_MASK) -#define BUTN_LED_INTENSE_PLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_PLED_MASK) >> BUTN_LED_INTENSE_PLED_SHIFT) - - - - -#endif /* HPM_BUTN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_crc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_crc_regs.h deleted file mode 100644 index 7c06d3e0e4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_crc_regs.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CRC_H -#define HPM_CRC_H - -typedef struct { - struct { - __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ - __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ - __RW uint32_t POLY; /* 0x8: chn poly */ - __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ - __RW uint32_t XOROUT; /* 0x10: chn xorout */ - __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ - __RW uint32_t DATA; /* 0x18: chn data */ - __RW uint32_t RESULT; /* 0x1C: chn result */ - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - } CHN[8]; -} CRC_Type; - - -/* Bitfield definition for register of struct array CHN: PRE_SET */ -/* - * PRE_SET (RW) - * - * 0: no pre set - * 1: CRC32 - * 2: CRC32-AUTOSAR - * 3: CRC16-CCITT - * 4: CRC16-XMODEM - * 5: CRC16-MODBUS - * 1: CRC32 - * 2: CRC32-autosar - * 3: CRC16-ccitt - * 4: CRC16-xmodem - * 5: CRC16-modbus - * 6: crc16_dnp - * 7: crc16_x25 - * 8: crc16_usb - * 9: crc16_maxim - * 10: crc16_ibm - * 11: crc8_maxim - * 12: crc8_rohc - * 13: crc8_itu - * 14: crc8 - * 15: crc5_usb - */ -#define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) -#define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) -#define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) -#define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) - -/* Bitfield definition for register of struct array CHN: CLR */ -/* - * CLR (RW) - * - * write 1 to clr crc setting and result for its channel. - * always read 0. - */ -#define CRC_CHN_CLR_CLR_MASK (0x1U) -#define CRC_CHN_CLR_CLR_SHIFT (0U) -#define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) -#define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) - -/* Bitfield definition for register of struct array CHN: POLY */ -/* - * POLY (RW) - * - * poly setting - */ -#define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) -#define CRC_CHN_POLY_POLY_SHIFT (0U) -#define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) -#define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array CHN: INIT_DATA */ -/* - * INIT_DATA (RW) - * - * initial data of CRC - */ -#define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) -#define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) -#define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: XOROUT */ -/* - * XOROUT (RW) - * - * XOR for CRC result - */ -#define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) -#define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) -#define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) - -/* Bitfield definition for register of struct array CHN: MISC_SETTING */ -/* - * BYTE_REV (RW) - * - * 0: no wrap input byte order - * 1: wrap input byte order - */ -#define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) -#define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) - -/* - * REV_OUT (RW) - * - * 0: no wrap output bit order - * 1: wrap output bit order - */ -#define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) -#define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) -#define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) -#define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) - -/* - * REV_IN (RW) - * - * 0: no wrap input bit order - * 1: wrap input bit order - */ -#define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) -#define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) -#define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) -#define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) - -/* - * POLY_WIDTH (RW) - * - * crc data length - */ -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) - -/* Bitfield definition for register of struct array CHN: DATA */ -/* - * DATA (RW) - * - * data for crc - */ -#define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_DATA_DATA_SHIFT (0U) -#define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) -#define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: RESULT */ -/* - * RESULT (RW) - * - * crc result - */ -#define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_RESULT_RESULT_SHIFT (0U) -#define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) -#define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) - - - -/* CHN register group index macro definition */ -#define CRC_CHN_0 (0UL) -#define CRC_CHN_1 (1UL) -#define CRC_CHN_2 (2UL) -#define CRC_CHN_3 (3UL) -#define CRC_CHN_4 (4UL) -#define CRC_CHN_5 (5UL) -#define CRC_CHN_6 (6UL) -#define CRC_CHN_7 (7UL) - - -#endif /* HPM_CRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dac_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dac_regs.h deleted file mode 100644 index 8ef7ec50f74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dac_regs.h +++ /dev/null @@ -1,637 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAC_H -#define HPM_DAC_H - -typedef struct { - __W uint32_t CFG0; /* 0x0: */ - __RW uint32_t CFG1; /* 0x4: */ - __RW uint32_t CFG2; /* 0x8: */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t STEP_CFG[4]; /* 0x10 - 0x1C: */ - __RW uint32_t BUF_ADDR[2]; /* 0x20 - 0x24: */ - __RW uint32_t BUF_LENGTH; /* 0x28: */ - __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ - __W uint32_t IRQ_STS; /* 0x30: */ - __RW uint32_t IRQ_EN; /* 0x34: */ - __RW uint32_t DMA_EN; /* 0x38: */ - __R uint8_t RESERVED2[4]; /* 0x3C - 0x3F: Reserved */ - __RW uint32_t ANA_CFG0; /* 0x40: */ - __RW uint32_t CFG0_BAK; /* 0x44: */ - __RW uint32_t STATUS0; /* 0x48: */ -} DAC_Type; - - -/* Bitfield definition for register: CFG0 */ -/* - * SW_DAC_DATA (WO) - * - * dac data used in direct mode(dac_mode==2'b10) - */ -#define DAC_CFG0_SW_DAC_DATA_MASK (0xFFF0000UL) -#define DAC_CFG0_SW_DAC_DATA_SHIFT (16U) -#define DAC_CFG0_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_SW_DAC_DATA_SHIFT) & DAC_CFG0_SW_DAC_DATA_MASK) -#define DAC_CFG0_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_SW_DAC_DATA_MASK) >> DAC_CFG0_SW_DAC_DATA_SHIFT) - -/* - * DMA_AHB_EN (WO) - * - * set to enable internal DMA, it will read one burst if enough space in FIFO. - * Should only be used in buffer mode. - */ -#define DAC_CFG0_DMA_AHB_EN_MASK (0x200U) -#define DAC_CFG0_DMA_AHB_EN_SHIFT (9U) -#define DAC_CFG0_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_DMA_AHB_EN_SHIFT) & DAC_CFG0_DMA_AHB_EN_MASK) -#define DAC_CFG0_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_DMA_AHB_EN_MASK) >> DAC_CFG0_DMA_AHB_EN_SHIFT) - -/* - * SYNC_MODE (WO) - * - * 1: sync dac clock and ahb clock. - * all HW trigger signals are pulse in sync mode, can get faster response; - * 0: async dac clock and ahb_clock - * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - */ -#define DAC_CFG0_SYNC_MODE_MASK (0x100U) -#define DAC_CFG0_SYNC_MODE_SHIFT (8U) -#define DAC_CFG0_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_SYNC_MODE_SHIFT) & DAC_CFG0_SYNC_MODE_MASK) -#define DAC_CFG0_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_SYNC_MODE_MASK) >> DAC_CFG0_SYNC_MODE_SHIFT) - -/* - * TRIG_MODE (WO) - * - * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; - * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - */ -#define DAC_CFG0_TRIG_MODE_MASK (0x80U) -#define DAC_CFG0_TRIG_MODE_SHIFT (7U) -#define DAC_CFG0_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_TRIG_MODE_SHIFT) & DAC_CFG0_TRIG_MODE_MASK) -#define DAC_CFG0_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_TRIG_MODE_MASK) >> DAC_CFG0_TRIG_MODE_SHIFT) - -/* - * HW_TRIG_EN (WO) - * - * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - */ -#define DAC_CFG0_HW_TRIG_EN_MASK (0x40U) -#define DAC_CFG0_HW_TRIG_EN_SHIFT (6U) -#define DAC_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_HW_TRIG_EN_SHIFT) & DAC_CFG0_HW_TRIG_EN_MASK) -#define DAC_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_HW_TRIG_EN_MASK) >> DAC_CFG0_HW_TRIG_EN_SHIFT) - -/* - * DAC_MODE (WO) - * - * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) - * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down - * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - * 11: trigger mode, DAC output from external trigger signals - * Note: - * Trigger mode is not supported in hpm63xx and hpm62xx families. - */ -#define DAC_CFG0_DAC_MODE_MASK (0x30U) -#define DAC_CFG0_DAC_MODE_SHIFT (4U) -#define DAC_CFG0_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_DAC_MODE_SHIFT) & DAC_CFG0_DAC_MODE_MASK) -#define DAC_CFG0_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_DAC_MODE_MASK) >> DAC_CFG0_DAC_MODE_SHIFT) - -/* - * BUF_DATA_MODE (WO) - * - * data structure for buffer mode, - * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. - * 1: each 32-bit data contains 1 point, b11:0 for first - */ -#define DAC_CFG0_BUF_DATA_MODE_MASK (0x8U) -#define DAC_CFG0_BUF_DATA_MODE_SHIFT (3U) -#define DAC_CFG0_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BUF_DATA_MODE_MASK) -#define DAC_CFG0_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BUF_DATA_MODE_MASK) >> DAC_CFG0_BUF_DATA_MODE_SHIFT) - -/* - * HBURST_CFG (WO) - * - * DAC support following fixed burst only - * 000-SINGLE; 011-INCR4; 101: INCR8 - * others are reserved - */ -#define DAC_CFG0_HBURST_CFG_MASK (0x7U) -#define DAC_CFG0_HBURST_CFG_SHIFT (0U) -#define DAC_CFG0_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_HBURST_CFG_SHIFT) & DAC_CFG0_HBURST_CFG_MASK) -#define DAC_CFG0_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_HBURST_CFG_MASK) >> DAC_CFG0_HBURST_CFG_SHIFT) - -/* Bitfield definition for register: CFG1 */ -/* - * ANA_CLK_EN (RW) - * - * set to enable analog clock(divided by ana_div_cfg) - * need to be set in direct mode and trigger mode - */ -#define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) -#define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) -#define DAC_CFG1_ANA_CLK_EN_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_CLK_EN_SHIFT) & DAC_CFG1_ANA_CLK_EN_MASK) -#define DAC_CFG1_ANA_CLK_EN_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_CLK_EN_MASK) >> DAC_CFG1_ANA_CLK_EN_SHIFT) - -/* - * ANA_DIV_CFG (RW) - * - * clock divider config for ana_clk to dac analog; - * 00: div2 - * 01: div4 - * 10: div6 - * 11: div8 - */ -#define DAC_CFG1_ANA_DIV_CFG_MASK (0x30000UL) -#define DAC_CFG1_ANA_DIV_CFG_SHIFT (16U) -#define DAC_CFG1_ANA_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_DIV_CFG_SHIFT) & DAC_CFG1_ANA_DIV_CFG_MASK) -#define DAC_CFG1_ANA_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_DIV_CFG_MASK) >> DAC_CFG1_ANA_DIV_CFG_SHIFT) - -/* - * DIV_CFG (RW) - * - * step mode and buffer mode: - * defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. - * Direct mode and trigger mode: - * defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. - * Note: - * For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. - */ -#define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) -#define DAC_CFG1_DIV_CFG_SHIFT (0U) -#define DAC_CFG1_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_DIV_CFG_SHIFT) & DAC_CFG1_DIV_CFG_MASK) -#define DAC_CFG1_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_DIV_CFG_MASK) >> DAC_CFG1_DIV_CFG_SHIFT) - -/* Bitfield definition for register: CFG2 */ -/* - * DMA_RST1 (WO) - * - * set to reset dma read pointer to buf1_start_addr; - * if set both dma_rst0&dma_rst1, will set to buf0_start_addr - * user can set fifo_clr bit when use dma_rst* - */ -#define DAC_CFG2_DMA_RST1_MASK (0x80U) -#define DAC_CFG2_DMA_RST1_SHIFT (7U) -#define DAC_CFG2_DMA_RST1_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST1_SHIFT) & DAC_CFG2_DMA_RST1_MASK) -#define DAC_CFG2_DMA_RST1_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST1_MASK) >> DAC_CFG2_DMA_RST1_SHIFT) - -/* - * DMA_RST0 (WO) - * - * set to reset dma read pointer to buf0_start_addr - */ -#define DAC_CFG2_DMA_RST0_MASK (0x40U) -#define DAC_CFG2_DMA_RST0_SHIFT (6U) -#define DAC_CFG2_DMA_RST0_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST0_SHIFT) & DAC_CFG2_DMA_RST0_MASK) -#define DAC_CFG2_DMA_RST0_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST0_MASK) >> DAC_CFG2_DMA_RST0_SHIFT) - -/* - * FIFO_CLR (WO) - * - * set to clear FIFO content(set both read/write pointer to 0) - */ -#define DAC_CFG2_FIFO_CLR_MASK (0x20U) -#define DAC_CFG2_FIFO_CLR_SHIFT (5U) -#define DAC_CFG2_FIFO_CLR_SET(x) (((uint32_t)(x) << DAC_CFG2_FIFO_CLR_SHIFT) & DAC_CFG2_FIFO_CLR_MASK) -#define DAC_CFG2_FIFO_CLR_GET(x) (((uint32_t)(x) & DAC_CFG2_FIFO_CLR_MASK) >> DAC_CFG2_FIFO_CLR_SHIFT) - -/* - * BUF_SW_TRIG (RW) - * - * software trigger for buffer mode, - * W1C in single mode. - * RW in continual mode - */ -#define DAC_CFG2_BUF_SW_TRIG_MASK (0x10U) -#define DAC_CFG2_BUF_SW_TRIG_SHIFT (4U) -#define DAC_CFG2_BUF_SW_TRIG_SET(x) (((uint32_t)(x) << DAC_CFG2_BUF_SW_TRIG_SHIFT) & DAC_CFG2_BUF_SW_TRIG_MASK) -#define DAC_CFG2_BUF_SW_TRIG_GET(x) (((uint32_t)(x) & DAC_CFG2_BUF_SW_TRIG_MASK) >> DAC_CFG2_BUF_SW_TRIG_SHIFT) - -/* - * STEP_SW_TRIG3 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG3_MASK (0x8U) -#define DAC_CFG2_STEP_SW_TRIG3_SHIFT (3U) -#define DAC_CFG2_STEP_SW_TRIG3_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG3_SHIFT) & DAC_CFG2_STEP_SW_TRIG3_MASK) -#define DAC_CFG2_STEP_SW_TRIG3_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG3_MASK) >> DAC_CFG2_STEP_SW_TRIG3_SHIFT) - -/* - * STEP_SW_TRIG2 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG2_MASK (0x4U) -#define DAC_CFG2_STEP_SW_TRIG2_SHIFT (2U) -#define DAC_CFG2_STEP_SW_TRIG2_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG2_SHIFT) & DAC_CFG2_STEP_SW_TRIG2_MASK) -#define DAC_CFG2_STEP_SW_TRIG2_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG2_MASK) >> DAC_CFG2_STEP_SW_TRIG2_SHIFT) - -/* - * STEP_SW_TRIG1 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG1_MASK (0x2U) -#define DAC_CFG2_STEP_SW_TRIG1_SHIFT (1U) -#define DAC_CFG2_STEP_SW_TRIG1_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG1_SHIFT) & DAC_CFG2_STEP_SW_TRIG1_MASK) -#define DAC_CFG2_STEP_SW_TRIG1_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG1_MASK) >> DAC_CFG2_STEP_SW_TRIG1_SHIFT) - -/* - * STEP_SW_TRIG0 (RW) - * - * software trigger0 for step mode, - * W1C in single mode. - * RW in continual mode - */ -#define DAC_CFG2_STEP_SW_TRIG0_MASK (0x1U) -#define DAC_CFG2_STEP_SW_TRIG0_SHIFT (0U) -#define DAC_CFG2_STEP_SW_TRIG0_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG0_SHIFT) & DAC_CFG2_STEP_SW_TRIG0_MASK) -#define DAC_CFG2_STEP_SW_TRIG0_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG0_MASK) >> DAC_CFG2_STEP_SW_TRIG0_SHIFT) - -/* Bitfield definition for register array: STEP_CFG */ -/* - * ROUND_MODE (RW) - * - * 0: stop at end point; - * 1: reload start point, step again - */ -#define DAC_STEP_CFG_ROUND_MODE_MASK (0x20000000UL) -#define DAC_STEP_CFG_ROUND_MODE_SHIFT (29U) -#define DAC_STEP_CFG_ROUND_MODE_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_ROUND_MODE_SHIFT) & DAC_STEP_CFG_ROUND_MODE_MASK) -#define DAC_STEP_CFG_ROUND_MODE_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_ROUND_MODE_MASK) >> DAC_STEP_CFG_ROUND_MODE_SHIFT) - -/* - * UP_DOWN (RW) - * - * 0 for up, 1 for down - */ -#define DAC_STEP_CFG_UP_DOWN_MASK (0x10000000UL) -#define DAC_STEP_CFG_UP_DOWN_SHIFT (28U) -#define DAC_STEP_CFG_UP_DOWN_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_UP_DOWN_SHIFT) & DAC_STEP_CFG_UP_DOWN_MASK) -#define DAC_STEP_CFG_UP_DOWN_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_UP_DOWN_MASK) >> DAC_STEP_CFG_UP_DOWN_SHIFT) - -/* - * END_POINT (RW) - * - */ -#define DAC_STEP_CFG_END_POINT_MASK (0xFFF0000UL) -#define DAC_STEP_CFG_END_POINT_SHIFT (16U) -#define DAC_STEP_CFG_END_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_END_POINT_SHIFT) & DAC_STEP_CFG_END_POINT_MASK) -#define DAC_STEP_CFG_END_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_END_POINT_MASK) >> DAC_STEP_CFG_END_POINT_SHIFT) - -/* - * STEP_NUM (RW) - * - * output data change step_num each DAC clock cycle. - * Ex: if step_num=3, output data sequence is 0,3,6,9 - * NOTE: user should make sure end_point can be reached if step_num is not 1 - * if step_num is 0, output data will always at start point - */ -#define DAC_STEP_CFG_STEP_NUM_MASK (0xF000U) -#define DAC_STEP_CFG_STEP_NUM_SHIFT (12U) -#define DAC_STEP_CFG_STEP_NUM_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_STEP_NUM_SHIFT) & DAC_STEP_CFG_STEP_NUM_MASK) -#define DAC_STEP_CFG_STEP_NUM_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_STEP_NUM_MASK) >> DAC_STEP_CFG_STEP_NUM_SHIFT) - -/* - * START_POINT (RW) - * - */ -#define DAC_STEP_CFG_START_POINT_MASK (0xFFFU) -#define DAC_STEP_CFG_START_POINT_SHIFT (0U) -#define DAC_STEP_CFG_START_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_START_POINT_SHIFT) & DAC_STEP_CFG_START_POINT_MASK) -#define DAC_STEP_CFG_START_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_START_POINT_MASK) >> DAC_STEP_CFG_START_POINT_SHIFT) - -/* Bitfield definition for register array: BUF_ADDR */ -/* - * BUF_START_ADDR (RW) - * - * buffer start address, should be 4-byte aligned - * AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - */ -#define DAC_BUF_ADDR_BUF_START_ADDR_MASK (0xFFFFFFFCUL) -#define DAC_BUF_ADDR_BUF_START_ADDR_SHIFT (2U) -#define DAC_BUF_ADDR_BUF_START_ADDR_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) -#define DAC_BUF_ADDR_BUF_START_ADDR_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) >> DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) - -/* - * BUF_STOP (RW) - * - * set to stop read point at end of bufffer0 - */ -#define DAC_BUF_ADDR_BUF_STOP_MASK (0x1U) -#define DAC_BUF_ADDR_BUF_STOP_SHIFT (0U) -#define DAC_BUF_ADDR_BUF_STOP_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_STOP_SHIFT) & DAC_BUF_ADDR_BUF_STOP_MASK) -#define DAC_BUF_ADDR_BUF_STOP_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_STOP_MASK) >> DAC_BUF_ADDR_BUF_STOP_SHIFT) - -/* Bitfield definition for register: BUF_LENGTH */ -/* - * BUF1_LEN (RW) - * - * buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - */ -#define DAC_BUF_LENGTH_BUF1_LEN_MASK (0xFFFF0000UL) -#define DAC_BUF_LENGTH_BUF1_LEN_SHIFT (16U) -#define DAC_BUF_LENGTH_BUF1_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF1_LEN_SHIFT) & DAC_BUF_LENGTH_BUF1_LEN_MASK) -#define DAC_BUF_LENGTH_BUF1_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF1_LEN_MASK) >> DAC_BUF_LENGTH_BUF1_LEN_SHIFT) - -/* - * BUF0_LEN (RW) - * - */ -#define DAC_BUF_LENGTH_BUF0_LEN_MASK (0xFFFFU) -#define DAC_BUF_LENGTH_BUF0_LEN_SHIFT (0U) -#define DAC_BUF_LENGTH_BUF0_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF0_LEN_SHIFT) & DAC_BUF_LENGTH_BUF0_LEN_MASK) -#define DAC_BUF_LENGTH_BUF0_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF0_LEN_MASK) >> DAC_BUF_LENGTH_BUF0_LEN_SHIFT) - -/* Bitfield definition for register: IRQ_STS */ -/* - * STEP_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_STEP_CMPT_MASK (0x10U) -#define DAC_IRQ_STS_STEP_CMPT_SHIFT (4U) -#define DAC_IRQ_STS_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_STEP_CMPT_SHIFT) & DAC_IRQ_STS_STEP_CMPT_MASK) -#define DAC_IRQ_STS_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_STEP_CMPT_MASK) >> DAC_IRQ_STS_STEP_CMPT_SHIFT) - -/* - * AHB_ERROR (W1C) - * - * set if hresp==2'b01(ERROR) - */ -#define DAC_IRQ_STS_AHB_ERROR_MASK (0x8U) -#define DAC_IRQ_STS_AHB_ERROR_SHIFT (3U) -#define DAC_IRQ_STS_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_AHB_ERROR_SHIFT) & DAC_IRQ_STS_AHB_ERROR_MASK) -#define DAC_IRQ_STS_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_AHB_ERROR_MASK) >> DAC_IRQ_STS_AHB_ERROR_SHIFT) - -/* - * FIFO_EMPTY (W1C) - * - */ -#define DAC_IRQ_STS_FIFO_EMPTY_MASK (0x4U) -#define DAC_IRQ_STS_FIFO_EMPTY_SHIFT (2U) -#define DAC_IRQ_STS_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_FIFO_EMPTY_SHIFT) & DAC_IRQ_STS_FIFO_EMPTY_MASK) -#define DAC_IRQ_STS_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_FIFO_EMPTY_MASK) >> DAC_IRQ_STS_FIFO_EMPTY_SHIFT) - -/* - * BUF1_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_BUF1_CMPT_MASK (0x2U) -#define DAC_IRQ_STS_BUF1_CMPT_SHIFT (1U) -#define DAC_IRQ_STS_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF1_CMPT_SHIFT) & DAC_IRQ_STS_BUF1_CMPT_MASK) -#define DAC_IRQ_STS_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF1_CMPT_MASK) >> DAC_IRQ_STS_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_BUF0_CMPT_MASK (0x1U) -#define DAC_IRQ_STS_BUF0_CMPT_SHIFT (0U) -#define DAC_IRQ_STS_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF0_CMPT_SHIFT) & DAC_IRQ_STS_BUF0_CMPT_MASK) -#define DAC_IRQ_STS_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF0_CMPT_MASK) >> DAC_IRQ_STS_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * STEP_CMPT (RW) - * - */ -#define DAC_IRQ_EN_STEP_CMPT_MASK (0x10U) -#define DAC_IRQ_EN_STEP_CMPT_SHIFT (4U) -#define DAC_IRQ_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_STEP_CMPT_SHIFT) & DAC_IRQ_EN_STEP_CMPT_MASK) -#define DAC_IRQ_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_STEP_CMPT_MASK) >> DAC_IRQ_EN_STEP_CMPT_SHIFT) - -/* - * AHB_ERROR (RW) - * - */ -#define DAC_IRQ_EN_AHB_ERROR_MASK (0x8U) -#define DAC_IRQ_EN_AHB_ERROR_SHIFT (3U) -#define DAC_IRQ_EN_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_AHB_ERROR_SHIFT) & DAC_IRQ_EN_AHB_ERROR_MASK) -#define DAC_IRQ_EN_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_AHB_ERROR_MASK) >> DAC_IRQ_EN_AHB_ERROR_SHIFT) - -/* - * FIFO_EMPTY (RW) - * - */ -#define DAC_IRQ_EN_FIFO_EMPTY_MASK (0x4U) -#define DAC_IRQ_EN_FIFO_EMPTY_SHIFT (2U) -#define DAC_IRQ_EN_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_FIFO_EMPTY_SHIFT) & DAC_IRQ_EN_FIFO_EMPTY_MASK) -#define DAC_IRQ_EN_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_FIFO_EMPTY_MASK) >> DAC_IRQ_EN_FIFO_EMPTY_SHIFT) - -/* - * BUF1_CMPT (RW) - * - */ -#define DAC_IRQ_EN_BUF1_CMPT_MASK (0x2U) -#define DAC_IRQ_EN_BUF1_CMPT_SHIFT (1U) -#define DAC_IRQ_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF1_CMPT_SHIFT) & DAC_IRQ_EN_BUF1_CMPT_MASK) -#define DAC_IRQ_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF1_CMPT_MASK) >> DAC_IRQ_EN_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (RW) - * - */ -#define DAC_IRQ_EN_BUF0_CMPT_MASK (0x1U) -#define DAC_IRQ_EN_BUF0_CMPT_SHIFT (0U) -#define DAC_IRQ_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF0_CMPT_SHIFT) & DAC_IRQ_EN_BUF0_CMPT_MASK) -#define DAC_IRQ_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF0_CMPT_MASK) >> DAC_IRQ_EN_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: DMA_EN */ -/* - * STEP_CMPT (RW) - * - */ -#define DAC_DMA_EN_STEP_CMPT_MASK (0x10U) -#define DAC_DMA_EN_STEP_CMPT_SHIFT (4U) -#define DAC_DMA_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_STEP_CMPT_SHIFT) & DAC_DMA_EN_STEP_CMPT_MASK) -#define DAC_DMA_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_STEP_CMPT_MASK) >> DAC_DMA_EN_STEP_CMPT_SHIFT) - -/* - * BUF1_CMPT (RW) - * - */ -#define DAC_DMA_EN_BUF1_CMPT_MASK (0x2U) -#define DAC_DMA_EN_BUF1_CMPT_SHIFT (1U) -#define DAC_DMA_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF1_CMPT_SHIFT) & DAC_DMA_EN_BUF1_CMPT_MASK) -#define DAC_DMA_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF1_CMPT_MASK) >> DAC_DMA_EN_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (RW) - * - */ -#define DAC_DMA_EN_BUF0_CMPT_MASK (0x1U) -#define DAC_DMA_EN_BUF0_CMPT_SHIFT (0U) -#define DAC_DMA_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF0_CMPT_SHIFT) & DAC_DMA_EN_BUF0_CMPT_MASK) -#define DAC_DMA_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF0_CMPT_MASK) >> DAC_DMA_EN_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: ANA_CFG0 */ -/* - * DAC12BIT_LP_MODE (RW) - * - */ -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK (0x100U) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT (8U) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) >> DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) - -/* - * DAC_CONFIG (RW) - * - */ -#define DAC_ANA_CFG0_DAC_CONFIG_MASK (0xF0U) -#define DAC_ANA_CFG0_DAC_CONFIG_SHIFT (4U) -#define DAC_ANA_CFG0_DAC_CONFIG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC_CONFIG_SHIFT) & DAC_ANA_CFG0_DAC_CONFIG_MASK) -#define DAC_ANA_CFG0_DAC_CONFIG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC_CONFIG_MASK) >> DAC_ANA_CFG0_DAC_CONFIG_SHIFT) - -/* - * CALI_DELTA_V_CFG (RW) - * - */ -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK (0xCU) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT (2U) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) >> DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) - -/* - * BYPASS_CALI_GM (RW) - * - */ -#define DAC_ANA_CFG0_BYPASS_CALI_GM_MASK (0x2U) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT (1U) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) >> DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) - -/* - * DAC12BIT_EN (RW) - * - */ -#define DAC_ANA_CFG0_DAC12BIT_EN_MASK (0x1U) -#define DAC_ANA_CFG0_DAC12BIT_EN_SHIFT (0U) -#define DAC_ANA_CFG0_DAC12BIT_EN_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) -#define DAC_ANA_CFG0_DAC12BIT_EN_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) >> DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) - -/* Bitfield definition for register: CFG0_BAK */ -/* - * SW_DAC_DATA (RW) - * - * dac data used in direct mode(dac_mode==2'b10) - */ -#define DAC_CFG0_BAK_SW_DAC_DATA_MASK (0xFFF0000UL) -#define DAC_CFG0_BAK_SW_DAC_DATA_SHIFT (16U) -#define DAC_CFG0_BAK_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) -#define DAC_CFG0_BAK_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) >> DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) - -/* - * DMA_AHB_EN (RW) - * - * set to enable internal DMA, it will read one burst if enough space in FIFO. - * Should only be used in buffer mode. - */ -#define DAC_CFG0_BAK_DMA_AHB_EN_MASK (0x200U) -#define DAC_CFG0_BAK_DMA_AHB_EN_SHIFT (9U) -#define DAC_CFG0_BAK_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) -#define DAC_CFG0_BAK_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) >> DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) - -/* - * SYNC_MODE (RW) - * - * 1: sync dac clock and ahb clock. - * all HW trigger signals are pulse in sync mode, can get faster response; - * 0: async dac clock and ahb_clock - * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - */ -#define DAC_CFG0_BAK_SYNC_MODE_MASK (0x100U) -#define DAC_CFG0_BAK_SYNC_MODE_SHIFT (8U) -#define DAC_CFG0_BAK_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SYNC_MODE_SHIFT) & DAC_CFG0_BAK_SYNC_MODE_MASK) -#define DAC_CFG0_BAK_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SYNC_MODE_MASK) >> DAC_CFG0_BAK_SYNC_MODE_SHIFT) - -/* - * TRIG_MODE (RW) - * - * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; - * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - */ -#define DAC_CFG0_BAK_TRIG_MODE_MASK (0x80U) -#define DAC_CFG0_BAK_TRIG_MODE_SHIFT (7U) -#define DAC_CFG0_BAK_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_TRIG_MODE_SHIFT) & DAC_CFG0_BAK_TRIG_MODE_MASK) -#define DAC_CFG0_BAK_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_TRIG_MODE_MASK) >> DAC_CFG0_BAK_TRIG_MODE_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - */ -#define DAC_CFG0_BAK_HW_TRIG_EN_MASK (0x40U) -#define DAC_CFG0_BAK_HW_TRIG_EN_SHIFT (6U) -#define DAC_CFG0_BAK_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) -#define DAC_CFG0_BAK_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) >> DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) - -/* - * DAC_MODE (RW) - * - * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) - * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down - * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - */ -#define DAC_CFG0_BAK_DAC_MODE_MASK (0x30U) -#define DAC_CFG0_BAK_DAC_MODE_SHIFT (4U) -#define DAC_CFG0_BAK_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DAC_MODE_SHIFT) & DAC_CFG0_BAK_DAC_MODE_MASK) -#define DAC_CFG0_BAK_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DAC_MODE_MASK) >> DAC_CFG0_BAK_DAC_MODE_SHIFT) - -/* - * BUF_DATA_MODE (RW) - * - * data structure for buffer mode, - * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. - * 1: each 32-bit data contains 1 point, b11:0 for first - */ -#define DAC_CFG0_BAK_BUF_DATA_MODE_MASK (0x8U) -#define DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT (3U) -#define DAC_CFG0_BAK_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) -#define DAC_CFG0_BAK_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) >> DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) - -/* - * HBURST_CFG (RW) - * - * DAC support following fixed burst only - * 000-SINGLE; 011-INCR4; 101: INCR8 - * others are reserved - */ -#define DAC_CFG0_BAK_HBURST_CFG_MASK (0x7U) -#define DAC_CFG0_BAK_HBURST_CFG_SHIFT (0U) -#define DAC_CFG0_BAK_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HBURST_CFG_SHIFT) & DAC_CFG0_BAK_HBURST_CFG_MASK) -#define DAC_CFG0_BAK_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HBURST_CFG_MASK) >> DAC_CFG0_BAK_HBURST_CFG_SHIFT) - -/* Bitfield definition for register: STATUS0 */ -/* - * CUR_BUF_OFFSET (RW) - * - */ -#define DAC_STATUS0_CUR_BUF_OFFSET_MASK (0xFFFF00UL) -#define DAC_STATUS0_CUR_BUF_OFFSET_SHIFT (8U) -#define DAC_STATUS0_CUR_BUF_OFFSET_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) -#define DAC_STATUS0_CUR_BUF_OFFSET_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) >> DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) - -/* - * CUR_BUF_INDEX (RW) - * - */ -#define DAC_STATUS0_CUR_BUF_INDEX_MASK (0x80U) -#define DAC_STATUS0_CUR_BUF_INDEX_SHIFT (7U) -#define DAC_STATUS0_CUR_BUF_INDEX_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_INDEX_SHIFT) & DAC_STATUS0_CUR_BUF_INDEX_MASK) -#define DAC_STATUS0_CUR_BUF_INDEX_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_INDEX_MASK) >> DAC_STATUS0_CUR_BUF_INDEX_SHIFT) - - - -/* STEP_CFG register group index macro definition */ -#define DAC_STEP_CFG_STEP0 (0UL) -#define DAC_STEP_CFG_STEP1 (1UL) -#define DAC_STEP_CFG_STEP2 (2UL) -#define DAC_STEP_CFG_STEP3 (3UL) - -/* BUF_ADDR register group index macro definition */ -#define DAC_BUF_ADDR_BUF0 (0UL) -#define DAC_BUF_ADDR_BUF1 (1UL) - - -#endif /* HPM_DAC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dma_regs.h deleted file mode 100644 index e1937d13172..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dma_regs.h +++ /dev/null @@ -1,564 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMA_H -#define HPM_DMA_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t IDMISC; /* 0x4: ID Misc */ - __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ - __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __R uint8_t RESERVED2[12]; /* 0x14 - 0x1F: Reserved */ - __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ - __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ - __R uint8_t RESERVED3[8]; /* 0x28 - 0x2F: Reserved */ - __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ - __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED4[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ - __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel n Source Address Low Part Register */ - __RW uint32_t SRCADDRH; /* 0x4C: Channel n Source Address High Part Register */ - __RW uint32_t DSTADDR; /* 0x50: Channel n Destination Address Low Part Register */ - __RW uint32_t DSTADDRH; /* 0x54: Channel n Destination Address High Part Register */ - __RW uint32_t LLPOINTER; /* 0x58: Channel n Linked List Pointer Low Part Register */ - __RW uint32_t LLPOINTERH; /* 0x5C: Channel n Linked List Pointer High Part Register */ - } CHCTRL[8]; -} DMA_Type; - - -/* Bitfield definition for register: IDMISC */ -/* - * IDLE_FLAG (RO) - * - * DMA Idle Flag - * 0 - DMA is busy - * 1 - DMA is dile - */ -#define DMA_IDMISC_IDLE_FLAG_MASK (0x8000U) -#define DMA_IDMISC_IDLE_FLAG_SHIFT (15U) -#define DMA_IDMISC_IDLE_FLAG_GET(x) (((uint32_t)(x) & DMA_IDMISC_IDLE_FLAG_MASK) >> DMA_IDMISC_IDLE_FLAG_SHIFT) - -/* Bitfield definition for register: DMACFG */ -/* - * CHAINXFR (RO) - * - * Chain transfer - * 0x0: Chain transfer is not configured - * 0x1: Chain transfer is configured - */ -#define DMA_DMACFG_CHAINXFR_MASK (0x80000000UL) -#define DMA_DMACFG_CHAINXFR_SHIFT (31U) -#define DMA_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHAINXFR_MASK) >> DMA_DMACFG_CHAINXFR_SHIFT) - -/* - * REQSYNC (RO) - * - * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. - * 0x0: Request synchronization is not configured - * 0x1: Request synchronization is configured - */ -#define DMA_DMACFG_REQSYNC_MASK (0x40000000UL) -#define DMA_DMACFG_REQSYNC_SHIFT (30U) -#define DMA_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQSYNC_MASK) >> DMA_DMACFG_REQSYNC_SHIFT) - -/* - * DATAWIDTH (RO) - * - * AXI bus data width - * 0x0: 32 bits - * 0x1: 64 bits - * 0x2: 128 bits - * 0x3: 256 bits - */ -#define DMA_DMACFG_DATAWIDTH_MASK (0x3000000UL) -#define DMA_DMACFG_DATAWIDTH_SHIFT (24U) -#define DMA_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_DATAWIDTH_MASK) >> DMA_DMACFG_DATAWIDTH_SHIFT) - -/* - * ADDRWIDTH (RO) - * - * AXI bus address width - * 0x18: 24 bits - * 0x19: 25 bits - * ... - * 0x40: 64 bits - * Others: Invalid - */ -#define DMA_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) -#define DMA_DMACFG_ADDRWIDTH_SHIFT (17U) -#define DMA_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_ADDRWIDTH_MASK) >> DMA_DMACFG_ADDRWIDTH_SHIFT) - -/* - * CORENUM (RO) - * - * DMA core number - * 0x0: 1 core - * 0x1: 2 cores - */ -#define DMA_DMACFG_CORENUM_MASK (0x10000UL) -#define DMA_DMACFG_CORENUM_SHIFT (16U) -#define DMA_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CORENUM_MASK) >> DMA_DMACFG_CORENUM_SHIFT) - -/* - * BUSNUM (RO) - * - * AXI bus interface number - * 0x0: 1 AXI bus - * 0x1: 2 AXI busses - */ -#define DMA_DMACFG_BUSNUM_MASK (0x8000U) -#define DMA_DMACFG_BUSNUM_SHIFT (15U) -#define DMA_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_BUSNUM_MASK) >> DMA_DMACFG_BUSNUM_SHIFT) - -/* - * REQNUM (RO) - * - * Request/acknowledge pair number - * 0x0: 0 pair - * 0x1: 1 pair - * 0x2: 2 pairs - * ... - * 0x10: 16 pairs - */ -#define DMA_DMACFG_REQNUM_MASK (0x7C00U) -#define DMA_DMACFG_REQNUM_SHIFT (10U) -#define DMA_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQNUM_MASK) >> DMA_DMACFG_REQNUM_SHIFT) - -/* - * FIFODEPTH (RO) - * - * FIFO depth - * 0x4: 4 entries - * 0x8: 8 entries - * 0x10: 16 entries - * 0x20: 32 entries - * Others: Invalid - */ -#define DMA_DMACFG_FIFODEPTH_MASK (0x3F0U) -#define DMA_DMACFG_FIFODEPTH_SHIFT (4U) -#define DMA_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_FIFODEPTH_MASK) >> DMA_DMACFG_FIFODEPTH_SHIFT) - -/* - * CHANNELNUM (RO) - * - * Channel number - * 0x1: 1 channel - * 0x2: 2 channels - * ... - * 0x8: 8 channels - * Others: Invalid - */ -#define DMA_DMACFG_CHANNELNUM_MASK (0xFU) -#define DMA_DMACFG_CHANNELNUM_SHIFT (0U) -#define DMA_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHANNELNUM_MASK) >> DMA_DMACFG_CHANNELNUM_SHIFT) - -/* Bitfield definition for register: DMACTRL */ -/* - * RESET (WO) - * - * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. - * Note: The software reset may cause the in-completion of AXI transaction. - */ -#define DMA_DMACTRL_RESET_MASK (0x1U) -#define DMA_DMACTRL_RESET_SHIFT (0U) -#define DMA_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMA_DMACTRL_RESET_SHIFT) & DMA_DMACTRL_RESET_MASK) -#define DMA_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMA_DMACTRL_RESET_MASK) >> DMA_DMACTRL_RESET_SHIFT) - -/* Bitfield definition for register: CHABORT */ -/* - * CHABORT (WO) - * - * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - */ -#define DMA_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) -#define DMA_CHABORT_CHABORT_SHIFT (0U) -#define DMA_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMA_CHABORT_CHABORT_SHIFT) & DMA_CHABORT_CHABORT_MASK) -#define DMA_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMA_CHABORT_CHABORT_MASK) >> DMA_CHABORT_CHABORT_SHIFT) - -/* Bitfield definition for register: INTSTATUS */ -/* - * TC (W1C) - * - * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. - * 0x0: Channel n has no terminal count status - * 0x1: Channel n has terminal count status - */ -#define DMA_INTSTATUS_TC_MASK (0xFF0000UL) -#define DMA_INTSTATUS_TC_SHIFT (16U) -#define DMA_INTSTATUS_TC_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_TC_SHIFT) & DMA_INTSTATUS_TC_MASK) -#define DMA_INTSTATUS_TC_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_TC_MASK) >> DMA_INTSTATUS_TC_SHIFT) - -/* - * ABORT (W1C) - * - * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. - * 0x0: Channel n has no abort status - * 0x1: Channel n has abort status - */ -#define DMA_INTSTATUS_ABORT_MASK (0xFF00U) -#define DMA_INTSTATUS_ABORT_SHIFT (8U) -#define DMA_INTSTATUS_ABORT_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ABORT_SHIFT) & DMA_INTSTATUS_ABORT_MASK) -#define DMA_INTSTATUS_ABORT_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ABORT_MASK) >> DMA_INTSTATUS_ABORT_SHIFT) - -/* - * ERROR (W1C) - * - * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - * - Bus error - * - Unaligned address - * - Unaligned transfer width - * - Reserved configuration - * 0x0: Channel n has no error status - * 0x1: Channel n has error status - */ -#define DMA_INTSTATUS_ERROR_MASK (0xFFU) -#define DMA_INTSTATUS_ERROR_SHIFT (0U) -#define DMA_INTSTATUS_ERROR_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ERROR_SHIFT) & DMA_INTSTATUS_ERROR_MASK) -#define DMA_INTSTATUS_ERROR_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ERROR_MASK) >> DMA_INTSTATUS_ERROR_SHIFT) - -/* Bitfield definition for register: CHEN */ -/* - * CHEN (RO) - * - * Alias of the Enable field of all ChnCtrl registers - */ -#define DMA_CHEN_CHEN_MASK (0xFFFFFFFFUL) -#define DMA_CHEN_CHEN_SHIFT (0U) -#define DMA_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMA_CHEN_CHEN_MASK) >> DMA_CHEN_CHEN_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CTRL */ -/* - * SRCBUSINFIDX (RW) - * - * Bus interface index that source data is read from - * 0x0: Data is read from bus interface 0 - * 0x1: Data is read from bus interface - */ -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK (0x80000000UL) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT (31U) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) - -/* - * DSTBUSINFIDX (RW) - * - * Bus interface index that destination data is written to - * 0x0: Data is written to bus interface 0 - * 0x1: Data is written to bus interface 1 - */ -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK (0x40000000UL) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT (30U) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) - -/* - * PRIORITY (RW) - * - * Channel priority level - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define DMA_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) -#define DMA_CHCTRL_CTRL_PRIORITY_SHIFT (29U) -#define DMA_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_PRIORITY_SHIFT) & DMA_CHCTRL_CTRL_PRIORITY_MASK) -#define DMA_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_PRIORITY_MASK) >> DMA_CHCTRL_CTRL_PRIORITY_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. - * The burst transfer byte number is (SrcBurstSize * SrcWidth). - * 0x0: 1 transfer - * 0x1: 2 transfers - * 0x2: 4 transfers - * 0x3: 8 transfers - * 0x4: 16 transfers - * 0x5: 32 transfers - * 0x6: 64 transfers - * 0x7: 128 transfers - * 0x8: 256 transfers - * 0x9:512 transfers - * 0xa: 1024 transfers - * 0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - */ -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source transfer width - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - */ -#define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) -#define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) -#define DMA_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) -#define DMA_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination transfer width. - * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. - * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - */ -#define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) -#define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) -#define DMA_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) -#define DMA_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * Source DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define DMA_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) -#define DMA_CHCTRL_CTRL_SRCMODE_SHIFT (17U) -#define DMA_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCMODE_SHIFT) & DMA_CHCTRL_CTRL_SRCMODE_MASK) -#define DMA_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCMODE_MASK) >> DMA_CHCTRL_CTRL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * Destination DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define DMA_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) -#define DMA_CHCTRL_CTRL_DSTMODE_SHIFT (16U) -#define DMA_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTMODE_SHIFT) & DMA_CHCTRL_CTRL_DSTMODE_MASK) -#define DMA_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTMODE_MASK) >> DMA_CHCTRL_CTRL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * Source address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * Destination address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) - -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define DMA_CHCTRL_CTRL_SRCREQSEL_MASK (0xF00U) -#define DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT (8U) -#define DMA_CHCTRL_CTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) -#define DMA_CHCTRL_CTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) >> DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define DMA_CHCTRL_CTRL_DSTREQSEL_MASK (0xF0U) -#define DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT (4U) -#define DMA_CHCTRL_CTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) -#define DMA_CHCTRL_CTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) >> DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) - -/* - * INTABTMASK (RW) - * - * Channel abort interrupt mask - * 0x0: Allow the abort interrupt to be triggered - * 0x1: Disable the abort interrupt - */ -#define DMA_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) -#define DMA_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) -#define DMA_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) -#define DMA_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) >> DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) - -/* - * INTERRMASK (RW) - * - * Channel error interrupt mask - * 0x0: Allow the error interrupt to be triggered - * 0x1: Disable the error interrupt - */ -#define DMA_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) -#define DMA_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) -#define DMA_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) -#define DMA_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) >> DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) - -/* - * INTTCMASK (RW) - * - * Channel terminal count interrupt mask - * 0x0: Allow the terminal count interrupt to be triggered - * 0x1: Disable the terminal count interrupt - */ -#define DMA_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) -#define DMA_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) -#define DMA_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) -#define DMA_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) >> DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) - -/* - * ENABLE (RW) - * - * Channel enable bit - * 0x0: Disable - * 0x1: Enable - */ -#define DMA_CHCTRL_CTRL_ENABLE_MASK (0x1U) -#define DMA_CHCTRL_CTRL_ENABLE_SHIFT (0U) -#define DMA_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_ENABLE_SHIFT) & DMA_CHCTRL_CTRL_ENABLE_MASK) -#define DMA_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_ENABLE_MASK) >> DMA_CHCTRL_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ -/* - * TRANSIZE (RW) - * - * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. - * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - */ -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ -/* - * SRCADDRL (RW) - * - * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - */ -#define DMA_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDRH */ -/* - * SRCADDRH (RW) - * - * High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT (0U) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) >> DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ -/* - * DSTADDRL (RW) - * - * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - */ -#define DMA_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDRH */ -/* - * DSTADDRH (RW) - * - * High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT (0U) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) >> DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ -/* - * LLPOINTERL (RW) - * - * Low part of the pointer to the next descriptor. The pointer must be double word aligned. - */ -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) - -/* - * LLDBUSINFIDX (RW) - * - * Bus interface index that the next descriptor is read from - * 0x0: The next descriptor is read from bus interface 0 - */ -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK (0x1U) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT (0U) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) >> DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTERH */ -/* - * LLPOINTERH (RW) - * - * High part of the pointer to the next descriptor. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT (0U) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) >> DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) - - - -/* CHCTRL register group index macro definition */ -#define DMA_CHCTRL_CH0 (0UL) -#define DMA_CHCTRL_CH1 (1UL) -#define DMA_CHCTRL_CH2 (2UL) -#define DMA_CHCTRL_CH3 (3UL) -#define DMA_CHCTRL_CH4 (4UL) -#define DMA_CHCTRL_CH5 (5UL) -#define DMA_CHCTRL_CH6 (6UL) -#define DMA_CHCTRL_CH7 (7UL) - - -#endif /* HPM_DMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dmamux_regs.h deleted file mode 100644 index e7f67339ea4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_dmamux_regs.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_H -#define HPM_DMAMUX_H - -typedef struct { - __RW uint32_t MUXCFG[16]; /* 0x0 - 0x3C: HDMA MUX0 Configuration */ -} DMAMUX_Type; - - -/* Bitfield definition for register array: MUXCFG */ -/* - * ENABLE (RW) - * - * DMA Mux Channel Enable - * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be - * used to disable or reconfigure a DMA channel. - * 0b - DMA Mux channel is disabled - * 1b - DMA Mux channel is enabled - */ -#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) -#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) -#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) -#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) - -/* - * SOURCE (RW) - * - * DMA Channel Source - * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - */ -#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) -#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) -#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) - - - -/* MUXCFG register group index macro definition */ -#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) -#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) -#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) -#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) -#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) -#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) -#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) -#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) -#define DMAMUX_MUXCFG_XDMA_MUX0 (8UL) -#define DMAMUX_MUXCFG_XDMA_MUX1 (9UL) -#define DMAMUX_MUXCFG_XDMA_MUX2 (10UL) -#define DMAMUX_MUXCFG_XDMA_MUX3 (11UL) -#define DMAMUX_MUXCFG_XDMA_MUX4 (12UL) -#define DMAMUX_MUXCFG_XDMA_MUX5 (13UL) -#define DMAMUX_MUXCFG_XDMA_MUX6 (14UL) -#define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) - - -#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gpio_regs.h deleted file mode 100644 index 4f2a3d18dbf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gpio_regs.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIO_H -#define HPM_GPIO_H - -typedef struct { - struct { - __R uint32_t VALUE; /* 0x0: GPIO input value */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - } DI[16]; - struct { - __RW uint32_t VALUE; /* 0x100: GPIO output value */ - __RW uint32_t SET; /* 0x104: GPIO output set */ - __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ - __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ - } DO[16]; - struct { - __RW uint32_t VALUE; /* 0x200: GPIO direction value */ - __RW uint32_t SET; /* 0x204: GPIO direction set */ - __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ - __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ - } OE[16]; - struct { - __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ - } IF[16]; - struct { - __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ - __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ - __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ - } IE[16]; - struct { - __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ - __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ - __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ - __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ - } PL[16]; - struct { - __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ - __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ - __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ - __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ - } TP[16]; - struct { - __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ - __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ - __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ - __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ - } AS[16]; -} GPIO_Type; - - -/* Bitfield definition for register of struct array DI: VALUE */ -/* - * INPUT (RO) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: VALUE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) -#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) -#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: SET */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_SET_OUTPUT_SHIFT (0U) -#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) -#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: CLEAR */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) -#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) -#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: TOGGLE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) -#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) -#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array OE: VALUE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) -#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) -#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: SET */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_SET_DIRECTION_SHIFT (0U) -#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) -#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: CLEAR */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) -#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) -#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: TOGGLE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) -#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) -#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array IF: VALUE */ -/* - * IRQ_FLAG (W1C) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) -#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IE: VALUE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) -#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: SET */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) -#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) -#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: CLEAR */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) -#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) -#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: TOGGLE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) -#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array PL: VALUE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) -#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: SET */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) -#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) -#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: CLEAR */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) -#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) -#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: TOGGLE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) -#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array TP: VALUE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) -#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: SET */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) -#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: CLEAR */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) -#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: TOGGLE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) -#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array AS: VALUE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) -#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: SET */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) -#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: CLEAR */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) -#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: TOGGLE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) - - - -/* DI register group index macro definition */ -#define GPIO_DI_GPIOA (0UL) -#define GPIO_DI_GPIOB (1UL) -#define GPIO_DI_GPIOC (2UL) -#define GPIO_DI_GPIOX (13UL) -#define GPIO_DI_GPIOY (14UL) -#define GPIO_DI_GPIOZ (15UL) - -/* DO register group index macro definition */ -#define GPIO_DO_GPIOA (0UL) -#define GPIO_DO_GPIOB (1UL) -#define GPIO_DO_GPIOC (2UL) -#define GPIO_DO_GPIOX (13UL) -#define GPIO_DO_GPIOY (14UL) -#define GPIO_DO_GPIOZ (15UL) - -/* OE register group index macro definition */ -#define GPIO_OE_GPIOA (0UL) -#define GPIO_OE_GPIOB (1UL) -#define GPIO_OE_GPIOC (2UL) -#define GPIO_OE_GPIOX (13UL) -#define GPIO_OE_GPIOY (14UL) -#define GPIO_OE_GPIOZ (15UL) - -/* IF register group index macro definition */ -#define GPIO_IF_GPIOA (0UL) -#define GPIO_IF_GPIOB (1UL) -#define GPIO_IF_GPIOC (2UL) -#define GPIO_IF_GPIOX (13UL) -#define GPIO_IF_GPIOY (14UL) -#define GPIO_IF_GPIOZ (15UL) - -/* IE register group index macro definition */ -#define GPIO_IE_GPIOA (0UL) -#define GPIO_IE_GPIOB (1UL) -#define GPIO_IE_GPIOC (2UL) -#define GPIO_IE_GPIOX (13UL) -#define GPIO_IE_GPIOY (14UL) -#define GPIO_IE_GPIOZ (15UL) - -/* PL register group index macro definition */ -#define GPIO_PL_GPIOA (0UL) -#define GPIO_PL_GPIOB (1UL) -#define GPIO_PL_GPIOC (2UL) -#define GPIO_PL_GPIOX (13UL) -#define GPIO_PL_GPIOY (14UL) -#define GPIO_PL_GPIOZ (15UL) - -/* TP register group index macro definition */ -#define GPIO_TP_GPIOA (0UL) -#define GPIO_TP_GPIOB (1UL) -#define GPIO_TP_GPIOC (2UL) -#define GPIO_TP_GPIOX (13UL) -#define GPIO_TP_GPIOY (14UL) -#define GPIO_TP_GPIOZ (15UL) - -/* AS register group index macro definition */ -#define GPIO_AS_GPIOA (0UL) -#define GPIO_AS_GPIOB (1UL) -#define GPIO_AS_GPIOC (2UL) -#define GPIO_AS_GPIOX (13UL) -#define GPIO_AS_GPIOY (14UL) -#define GPIO_AS_GPIOZ (15UL) - - -#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gpiom_regs.h deleted file mode 100644 index 5c3eaf6f18f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gpiom_regs.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIOM_H -#define HPM_GPIOM_H - -typedef struct { - struct { - __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ - } ASSIGN[16]; -} GPIOM_Type; - - -/* Bitfield definition for register of struct array ASSIGN: PIN00 */ -/* - * LOCK (RW) - * - * lock fields in this register, lock can only be cleared by soc reset - * 0: fields can be changed - * 1: fields locked to current value, not changeable - */ -#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) -#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) -#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) - -/* - * HIDE (RW) - * - * pin value visibility to gpios, - * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 - * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 - * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - */ -#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) -#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) -#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) -#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) - -/* - * SELECT (RW) - * - * select which gpio controls chip pin, - * 0: soc gpio0; - * 1: soc gpio1; - * 2: cpu0 fastgpio - * 3: cpu1 fast gpio - */ -#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) -#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) -#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) -#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) - - - -/* PIN register group index macro definition */ -#define GPIOM_ASSIGN_PIN_PIN00 (0UL) -#define GPIOM_ASSIGN_PIN_PIN01 (1UL) -#define GPIOM_ASSIGN_PIN_PIN02 (2UL) -#define GPIOM_ASSIGN_PIN_PIN03 (3UL) -#define GPIOM_ASSIGN_PIN_PIN04 (4UL) -#define GPIOM_ASSIGN_PIN_PIN05 (5UL) -#define GPIOM_ASSIGN_PIN_PIN06 (6UL) -#define GPIOM_ASSIGN_PIN_PIN07 (7UL) -#define GPIOM_ASSIGN_PIN_PIN08 (8UL) -#define GPIOM_ASSIGN_PIN_PIN09 (9UL) -#define GPIOM_ASSIGN_PIN_PIN10 (10UL) -#define GPIOM_ASSIGN_PIN_PIN11 (11UL) -#define GPIOM_ASSIGN_PIN_PIN12 (12UL) -#define GPIOM_ASSIGN_PIN_PIN13 (13UL) -#define GPIOM_ASSIGN_PIN_PIN14 (14UL) -#define GPIOM_ASSIGN_PIN_PIN15 (15UL) -#define GPIOM_ASSIGN_PIN_PIN16 (16UL) -#define GPIOM_ASSIGN_PIN_PIN17 (17UL) -#define GPIOM_ASSIGN_PIN_PIN18 (18UL) -#define GPIOM_ASSIGN_PIN_PIN19 (19UL) -#define GPIOM_ASSIGN_PIN_PIN20 (20UL) -#define GPIOM_ASSIGN_PIN_PIN21 (21UL) -#define GPIOM_ASSIGN_PIN_PIN22 (22UL) -#define GPIOM_ASSIGN_PIN_PIN23 (23UL) -#define GPIOM_ASSIGN_PIN_PIN24 (24UL) -#define GPIOM_ASSIGN_PIN_PIN25 (25UL) -#define GPIOM_ASSIGN_PIN_PIN26 (26UL) -#define GPIOM_ASSIGN_PIN_PIN27 (27UL) -#define GPIOM_ASSIGN_PIN_PIN28 (28UL) -#define GPIOM_ASSIGN_PIN_PIN29 (29UL) -#define GPIOM_ASSIGN_PIN_PIN30 (30UL) -#define GPIOM_ASSIGN_PIN_PIN31 (31UL) - -/* ASSIGN register group index macro definition */ -#define GPIOM_ASSIGN_GPIOA (0UL) -#define GPIOM_ASSIGN_GPIOB (1UL) -#define GPIOM_ASSIGN_GPIOC (2UL) -#define GPIOM_ASSIGN_GPIOX (13UL) -#define GPIOM_ASSIGN_GPIOY (14UL) -#define GPIOM_ASSIGN_GPIOZ (15UL) - - -#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gptmr_regs.h deleted file mode 100644 index f87b1a75632..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_gptmr_regs.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPTMR_H -#define HPM_GPTMR_H - -typedef struct { - struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ - __RW uint32_t RLD; /* 0xC: Reload register */ - __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ - __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ - __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ - __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ - __R uint32_t CNT; /* 0x30: Counter */ - __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ - } CHANNEL[4]; - __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ - __RW uint32_t SR; /* 0x200: Status register */ - __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ - __RW uint32_t GCR; /* 0x208: Global control register */ -} GPTMR_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CR */ -/* - * CNTUPT (WO) - * - * 1- update counter to new value as CNTUPTVAL - * This bit will be auto cleared after 1 cycle - */ -#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) -#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) -#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) -#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) - -/* - * CNTRST (RW) - * - * 1- reset counter - */ -#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) -#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) -#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) -#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) - -/* - * SYNCFLW (RW) - * - * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. - * This bit is not valid for channel 0. - */ -#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) -#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) - -/* - * SYNCIFEN (RW) - * - * 1- SYNCI is valid on its falling edge - */ -#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) - -/* - * SYNCIREN (RW) - * - * 1- SYNCI is valid on its rising edge - */ -#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) - -/* - * CEN (RW) - * - * 1- counter enable - */ -#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) -#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) -#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) -#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) - -/* - * CMPINIT (RW) - * - * Output compare initial poliarity - * 1- The channel output initial level is high - * 0- The channel output initial level is low - * User should set this bit before set CMPEN to 1. - */ -#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) -#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) -#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) -#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) - -/* - * CMPEN (RW) - * - * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - */ -#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) -#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) -#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) -#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) - -/* - * DMASEL (RW) - * - * select one of DMA request: - * 00- CMP0 flag - * 01- CMP1 flag - * 10- Input signal toggle captured - * 11- RLD flag, counter reload; - */ -#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) -#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) -#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) -#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) - -/* - * DMAEN (RW) - * - * 1- enable dma - */ -#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) -#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) -#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) -#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) - -/* - * SWSYNCIEN (RW) - * - * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - */ -#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) - -/* - * DBGPAUSE (RW) - * - * 1- counter will pause if chip is in debug mode - */ -#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) -#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) - -/* - * CAPMODE (RW) - * - * This bitfield define the input capture mode - * 100: width measure mode, timer will calculate the input signal period and duty cycle - * 011: capture at both rising edge and falling edge - * 010: capture at falling edge - * 001: capture at rising edge - * 000: No capture - */ -#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) -#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) -#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) -#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CMP0 */ -/* - * CMP (RW) - * - * compare value 0 - */ -#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) -#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) -#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: RLD */ -/* - * RLD (RW) - * - * reload value - */ -#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) -#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) -#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ -/* - * CNTUPTVAL (RW) - * - * counter will be set to this value when software write cntupt bit in CR - */ -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ -/* - * CAPPOS (RO) - * - * This register contains the counter value captured at input signal rising edge - */ -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ -/* - * CAPNEG (RO) - * - * This register contains the counter value captured at input signal falling edge - */ -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ -/* - * CAPPRD (RO) - * - * This register contains the input signal period when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ -/* - * MEAS_HIGH (RO) - * - * This register contains the input signal duty cycle when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNT */ -/* - * COUNTER (RO) - * - * 32 bit counter value - */ -#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) -#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * CH3CMP1F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) -#define GPTMR_SR_CH3CMP1F_SHIFT (15U) -#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) -#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) - -/* - * CH3CMP0F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) -#define GPTMR_SR_CH3CMP0F_SHIFT (14U) -#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) -#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) - -/* - * CH3CAPF (W1C) - * - * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH3CAPF_MASK (0x2000U) -#define GPTMR_SR_CH3CAPF_SHIFT (13U) -#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) -#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) - -/* - * CH3RLDF (W1C) - * - * channel 3 counter reload flag - */ -#define GPTMR_SR_CH3RLDF_MASK (0x1000U) -#define GPTMR_SR_CH3RLDF_SHIFT (12U) -#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) -#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) - -/* - * CH2CMP1F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP1F_MASK (0x800U) -#define GPTMR_SR_CH2CMP1F_SHIFT (11U) -#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) -#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) - -/* - * CH2CMP0F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP0F_MASK (0x400U) -#define GPTMR_SR_CH2CMP0F_SHIFT (10U) -#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) -#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) - -/* - * CH2CAPF (W1C) - * - * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH2CAPF_MASK (0x200U) -#define GPTMR_SR_CH2CAPF_SHIFT (9U) -#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) -#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) - -/* - * CH2RLDF (W1C) - * - * channel 2 counter reload flag - */ -#define GPTMR_SR_CH2RLDF_MASK (0x100U) -#define GPTMR_SR_CH2RLDF_SHIFT (8U) -#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) -#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) - -/* - * CH1CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP1F_MASK (0x80U) -#define GPTMR_SR_CH1CMP1F_SHIFT (7U) -#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) -#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) - -/* - * CH1CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP0F_MASK (0x40U) -#define GPTMR_SR_CH1CMP0F_SHIFT (6U) -#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) -#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) - -/* - * CH1CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH1CAPF_MASK (0x20U) -#define GPTMR_SR_CH1CAPF_SHIFT (5U) -#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) -#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) - -/* - * CH1RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH1RLDF_MASK (0x10U) -#define GPTMR_SR_CH1RLDF_SHIFT (4U) -#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) -#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) - -/* - * CH0CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP1F_MASK (0x8U) -#define GPTMR_SR_CH0CMP1F_SHIFT (3U) -#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) -#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) - -/* - * CH0CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP0F_MASK (0x4U) -#define GPTMR_SR_CH0CMP0F_SHIFT (2U) -#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) -#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) - -/* - * CH0CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH0CAPF_MASK (0x2U) -#define GPTMR_SR_CH0CAPF_SHIFT (1U) -#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) -#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) - -/* - * CH0RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH0RLDF_MASK (0x1U) -#define GPTMR_SR_CH0RLDF_SHIFT (0U) -#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) -#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * CH3CMP1EN (RW) - * - * 1- generate interrupt request when ch3cmp1f flag is set - */ -#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) -#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) -#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) -#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) - -/* - * CH3CMP0EN (RW) - * - * 1- generate interrupt request when ch3cmp0f flag is set - */ -#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) -#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) -#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) -#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) - -/* - * CH3CAPEN (RW) - * - * 1- generate interrupt request when ch3capf flag is set - */ -#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) -#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) -#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) -#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) - -/* - * CH3RLDEN (RW) - * - * 1- generate interrupt request when ch3rldf flag is set - */ -#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) -#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) -#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) -#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) - -/* - * CH2CMP1EN (RW) - * - * 1- generate interrupt request when ch2cmp1f flag is set - */ -#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) -#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) -#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) -#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) - -/* - * CH2CMP0EN (RW) - * - * 1- generate interrupt request when ch2cmp0f flag is set - */ -#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) -#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) -#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) -#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) - -/* - * CH2CAPEN (RW) - * - * 1- generate interrupt request when ch2capf flag is set - */ -#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) -#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) -#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) -#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) - -/* - * CH2RLDEN (RW) - * - * 1- generate interrupt request when ch2rldf flag is set - */ -#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) -#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) -#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) -#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) - -/* - * CH1CMP1EN (RW) - * - * 1- generate interrupt request when ch1cmp1f flag is set - */ -#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) -#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) -#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) -#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) - -/* - * CH1CMP0EN (RW) - * - * 1- generate interrupt request when ch1cmp0f flag is set - */ -#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) -#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) -#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) -#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) - -/* - * CH1CAPEN (RW) - * - * 1- generate interrupt request when ch1capf flag is set - */ -#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) -#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) -#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) -#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) - -/* - * CH1RLDEN (RW) - * - * 1- generate interrupt request when ch1rldf flag is set - */ -#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) -#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) -#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) -#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) - -/* - * CH0CMP1EN (RW) - * - * 1- generate interrupt request when ch0cmp1f flag is set - */ -#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) -#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) -#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) -#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) - -/* - * CH0CMP0EN (RW) - * - * 1- generate interrupt request when ch0cmp0f flag is set - */ -#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) -#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) -#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) -#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) - -/* - * CH0CAPEN (RW) - * - * 1- generate interrupt request when ch0capf flag is set - */ -#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) -#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) -#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) -#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) - -/* - * CH0RLDEN (RW) - * - * 1- generate interrupt request when ch0rldf flag is set - */ -#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) -#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) -#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) -#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * SWSYNCT (RW) - * - * set this bitfield to trigger software counter sync event - */ -#define GPTMR_GCR_SWSYNCT_MASK (0xFU) -#define GPTMR_GCR_SWSYNCT_SHIFT (0U) -#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) -#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) - - - -/* CMP register group index macro definition */ -#define GPTMR_CHANNEL_CMP_CMP0 (0UL) -#define GPTMR_CHANNEL_CMP_CMP1 (1UL) - -/* CHANNEL register group index macro definition */ -#define GPTMR_CHANNEL_CH0 (0UL) -#define GPTMR_CHANNEL_CH1 (1UL) -#define GPTMR_CHANNEL_CH2 (2UL) -#define GPTMR_CHANNEL_CH3 (3UL) - - -#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_hall_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_hall_regs.h deleted file mode 100644 index 4b48f04c3d3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_hall_regs.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_HALL_H -#define HPM_HALL_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t UVWCFG; /* 0xC: U,V,W configure register */ - __RW uint32_t TRGOEN; /* 0x10: Trigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __R uint8_t RESERVED0[12]; /* 0x18 - 0x23: Reserved */ - __RW uint32_t DMAEN; /* 0x24: DMA enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request enable register */ - struct { - __R uint32_t W; /* 0x30: W counter */ - __R uint32_t V; /* 0x34: V counter */ - __R uint32_t U; /* 0x38: U counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - struct { - __R uint32_t HIS0; /* 0x70: history register 0 */ - __R uint32_t HIS1; /* 0x74: history register 1 */ - } HIS[3]; -} HALL_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define HALL_CR_READ_MASK (0x80000000UL) -#define HALL_CR_READ_SHIFT (31U) -#define HALL_CR_READ_SET(x) (((uint32_t)(x) << HALL_CR_READ_SHIFT) & HALL_CR_READ_MASK) -#define HALL_CR_READ_GET(x) (((uint32_t)(x) & HALL_CR_READ_MASK) >> HALL_CR_READ_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - */ -#define HALL_CR_SNAPEN_MASK (0x800U) -#define HALL_CR_SNAPEN_SHIFT (11U) -#define HALL_CR_SNAPEN_SET(x) (((uint32_t)(x) << HALL_CR_SNAPEN_SHIFT) & HALL_CR_SNAPEN_MASK) -#define HALL_CR_SNAPEN_GET(x) (((uint32_t)(x) & HALL_CR_SNAPEN_MASK) >> HALL_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * set to reset all counter and related snapshots - */ -#define HALL_CR_RSTCNT_MASK (0x10U) -#define HALL_CR_RSTCNT_SHIFT (4U) -#define HALL_CR_RSTCNT_SET(x) (((uint32_t)(x) << HALL_CR_RSTCNT_SHIFT) & HALL_CR_RSTCNT_MASK) -#define HALL_CR_RSTCNT_GET(x) (((uint32_t)(x) & HALL_CR_RSTCNT_MASK) >> HALL_CR_RSTCNT_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * DLYSEL (RW) - * - * This bit select delay start time: - * 1- start counting delay after pre-trigger - * 0- start counting delay after u,v,w toggle - */ -#define HALL_PHCFG_DLYSEL_MASK (0x80000000UL) -#define HALL_PHCFG_DLYSEL_SHIFT (31U) -#define HALL_PHCFG_DLYSEL_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYSEL_SHIFT) & HALL_PHCFG_DLYSEL_MASK) -#define HALL_PHCFG_DLYSEL_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYSEL_MASK) >> HALL_PHCFG_DLYSEL_SHIFT) - -/* - * DLYCNT (RW) - * - * delay clock cycles number - */ -#define HALL_PHCFG_DLYCNT_MASK (0xFFFFFFUL) -#define HALL_PHCFG_DLYCNT_SHIFT (0U) -#define HALL_PHCFG_DLYCNT_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYCNT_SHIFT) & HALL_PHCFG_DLYCNT_MASK) -#define HALL_PHCFG_DLYCNT_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYCNT_MASK) >> HALL_PHCFG_DLYCNT_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define HALL_WDGCFG_WDGEN_MASK (0x80000000UL) -#define HALL_WDGCFG_WDGEN_SHIFT (31U) -#define HALL_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGEN_SHIFT) & HALL_WDGCFG_WDGEN_MASK) -#define HALL_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGEN_MASK) >> HALL_WDGCFG_WDGEN_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define HALL_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) -#define HALL_WDGCFG_WDGTO_SHIFT (0U) -#define HALL_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGTO_SHIFT) & HALL_WDGCFG_WDGTO_MASK) -#define HALL_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGTO_MASK) >> HALL_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: UVWCFG */ -/* - * PRECNT (RW) - * - * the clock cycle number which the pre flag will set before the next uvw transition - */ -#define HALL_UVWCFG_PRECNT_MASK (0xFFFFFFUL) -#define HALL_UVWCFG_PRECNT_SHIFT (0U) -#define HALL_UVWCFG_PRECNT_SET(x) (((uint32_t)(x) << HALL_UVWCFG_PRECNT_SHIFT) & HALL_UVWCFG_PRECNT_MASK) -#define HALL_UVWCFG_PRECNT_GET(x) (((uint32_t)(x) & HALL_UVWCFG_PRECNT_MASK) >> HALL_UVWCFG_PRECNT_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define HALL_TRGOEN_WDGEN_MASK (0x80000000UL) -#define HALL_TRGOEN_WDGEN_SHIFT (31U) -#define HALL_TRGOEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WDGEN_SHIFT) & HALL_TRGOEN_WDGEN_MASK) -#define HALL_TRGOEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WDGEN_MASK) >> HALL_TRGOEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- enable trigger output when phupt flag set - */ -#define HALL_TRGOEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_TRGOEN_PHUPTEN_SHIFT (30U) -#define HALL_TRGOEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHUPTEN_SHIFT) & HALL_TRGOEN_PHUPTEN_MASK) -#define HALL_TRGOEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHUPTEN_MASK) >> HALL_TRGOEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- enable trigger output when phpre flag set - */ -#define HALL_TRGOEN_PHPREEN_MASK (0x20000000UL) -#define HALL_TRGOEN_PHPREEN_SHIFT (29U) -#define HALL_TRGOEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHPREEN_SHIFT) & HALL_TRGOEN_PHPREEN_MASK) -#define HALL_TRGOEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHPREEN_MASK) >> HALL_TRGOEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- enable trigger output when phdly flag set - */ -#define HALL_TRGOEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_TRGOEN_PHDLYEN_SHIFT (28U) -#define HALL_TRGOEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHDLYEN_SHIFT) & HALL_TRGOEN_PHDLYEN_MASK) -#define HALL_TRGOEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHDLYEN_MASK) >> HALL_TRGOEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- enable trigger output when u flag set - */ -#define HALL_TRGOEN_UFEN_MASK (0x800000UL) -#define HALL_TRGOEN_UFEN_SHIFT (23U) -#define HALL_TRGOEN_UFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_UFEN_SHIFT) & HALL_TRGOEN_UFEN_MASK) -#define HALL_TRGOEN_UFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_UFEN_MASK) >> HALL_TRGOEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- enable trigger output when v flag set - */ -#define HALL_TRGOEN_VFEN_MASK (0x400000UL) -#define HALL_TRGOEN_VFEN_SHIFT (22U) -#define HALL_TRGOEN_VFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_VFEN_SHIFT) & HALL_TRGOEN_VFEN_MASK) -#define HALL_TRGOEN_VFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_VFEN_MASK) >> HALL_TRGOEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- enable trigger output when w flag set - */ -#define HALL_TRGOEN_WFEN_MASK (0x200000UL) -#define HALL_TRGOEN_WFEN_SHIFT (21U) -#define HALL_TRGOEN_WFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WFEN_SHIFT) & HALL_TRGOEN_WFEN_MASK) -#define HALL_TRGOEN_WFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WFEN_MASK) >> HALL_TRGOEN_WFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define HALL_READEN_WDGEN_MASK (0x80000000UL) -#define HALL_READEN_WDGEN_SHIFT (31U) -#define HALL_READEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_READEN_WDGEN_SHIFT) & HALL_READEN_WDGEN_MASK) -#define HALL_READEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_READEN_WDGEN_MASK) >> HALL_READEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- load counters to their read registers when phupt flag set - */ -#define HALL_READEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_READEN_PHUPTEN_SHIFT (30U) -#define HALL_READEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHUPTEN_SHIFT) & HALL_READEN_PHUPTEN_MASK) -#define HALL_READEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHUPTEN_MASK) >> HALL_READEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- load counters to their read registers when phpre flag set - */ -#define HALL_READEN_PHPREEN_MASK (0x20000000UL) -#define HALL_READEN_PHPREEN_SHIFT (29U) -#define HALL_READEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHPREEN_SHIFT) & HALL_READEN_PHPREEN_MASK) -#define HALL_READEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHPREEN_MASK) >> HALL_READEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- load counters to their read registers when phdly flag set - */ -#define HALL_READEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_READEN_PHDLYEN_SHIFT (28U) -#define HALL_READEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHDLYEN_SHIFT) & HALL_READEN_PHDLYEN_MASK) -#define HALL_READEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHDLYEN_MASK) >> HALL_READEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- load counters to their read registers when u flag set - */ -#define HALL_READEN_UFEN_MASK (0x800000UL) -#define HALL_READEN_UFEN_SHIFT (23U) -#define HALL_READEN_UFEN_SET(x) (((uint32_t)(x) << HALL_READEN_UFEN_SHIFT) & HALL_READEN_UFEN_MASK) -#define HALL_READEN_UFEN_GET(x) (((uint32_t)(x) & HALL_READEN_UFEN_MASK) >> HALL_READEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- load counters to their read registers when v flag set - */ -#define HALL_READEN_VFEN_MASK (0x400000UL) -#define HALL_READEN_VFEN_SHIFT (22U) -#define HALL_READEN_VFEN_SET(x) (((uint32_t)(x) << HALL_READEN_VFEN_SHIFT) & HALL_READEN_VFEN_MASK) -#define HALL_READEN_VFEN_GET(x) (((uint32_t)(x) & HALL_READEN_VFEN_MASK) >> HALL_READEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- load counters to their read registers when w flag set - */ -#define HALL_READEN_WFEN_MASK (0x200000UL) -#define HALL_READEN_WFEN_SHIFT (21U) -#define HALL_READEN_WFEN_SET(x) (((uint32_t)(x) << HALL_READEN_WFEN_SHIFT) & HALL_READEN_WFEN_MASK) -#define HALL_READEN_WFEN_GET(x) (((uint32_t)(x) & HALL_READEN_WFEN_MASK) >> HALL_READEN_WFEN_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define HALL_DMAEN_WDGEN_MASK (0x80000000UL) -#define HALL_DMAEN_WDGEN_SHIFT (31U) -#define HALL_DMAEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WDGEN_SHIFT) & HALL_DMAEN_WDGEN_MASK) -#define HALL_DMAEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WDGEN_MASK) >> HALL_DMAEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- generate dma request when phupt flag set - */ -#define HALL_DMAEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_DMAEN_PHUPTEN_SHIFT (30U) -#define HALL_DMAEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHUPTEN_SHIFT) & HALL_DMAEN_PHUPTEN_MASK) -#define HALL_DMAEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHUPTEN_MASK) >> HALL_DMAEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- generate dma request when phpre flag set - */ -#define HALL_DMAEN_PHPREEN_MASK (0x20000000UL) -#define HALL_DMAEN_PHPREEN_SHIFT (29U) -#define HALL_DMAEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHPREEN_SHIFT) & HALL_DMAEN_PHPREEN_MASK) -#define HALL_DMAEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHPREEN_MASK) >> HALL_DMAEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- generate dma request when phdly flag set - */ -#define HALL_DMAEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_DMAEN_PHDLYEN_SHIFT (28U) -#define HALL_DMAEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHDLYEN_SHIFT) & HALL_DMAEN_PHDLYEN_MASK) -#define HALL_DMAEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHDLYEN_MASK) >> HALL_DMAEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- generate dma request when u flag set - */ -#define HALL_DMAEN_UFEN_MASK (0x800000UL) -#define HALL_DMAEN_UFEN_SHIFT (23U) -#define HALL_DMAEN_UFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_UFEN_SHIFT) & HALL_DMAEN_UFEN_MASK) -#define HALL_DMAEN_UFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_UFEN_MASK) >> HALL_DMAEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- generate dma request when v flag set - */ -#define HALL_DMAEN_VFEN_MASK (0x400000UL) -#define HALL_DMAEN_VFEN_SHIFT (22U) -#define HALL_DMAEN_VFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_VFEN_SHIFT) & HALL_DMAEN_VFEN_MASK) -#define HALL_DMAEN_VFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_VFEN_MASK) >> HALL_DMAEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- generate dma request when w flag set - */ -#define HALL_DMAEN_WFEN_MASK (0x200000UL) -#define HALL_DMAEN_WFEN_SHIFT (21U) -#define HALL_DMAEN_WFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WFEN_SHIFT) & HALL_DMAEN_WFEN_MASK) -#define HALL_DMAEN_WFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WFEN_MASK) >> HALL_DMAEN_WFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog count timeout flag - */ -#define HALL_SR_WDGF_MASK (0x80000000UL) -#define HALL_SR_WDGF_SHIFT (31U) -#define HALL_SR_WDGF_SET(x) (((uint32_t)(x) << HALL_SR_WDGF_SHIFT) & HALL_SR_WDGF_MASK) -#define HALL_SR_WDGF_GET(x) (((uint32_t)(x) & HALL_SR_WDGF_MASK) >> HALL_SR_WDGF_SHIFT) - -/* - * PHUPTF (RW) - * - * phase update flag, will set when any of u, v, w signal toggle - */ -#define HALL_SR_PHUPTF_MASK (0x40000000UL) -#define HALL_SR_PHUPTF_SHIFT (30U) -#define HALL_SR_PHUPTF_SET(x) (((uint32_t)(x) << HALL_SR_PHUPTF_SHIFT) & HALL_SR_PHUPTF_MASK) -#define HALL_SR_PHUPTF_GET(x) (((uint32_t)(x) & HALL_SR_PHUPTF_MASK) >> HALL_SR_PHUPTF_SHIFT) - -/* - * PHPREF (RW) - * - * phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - */ -#define HALL_SR_PHPREF_MASK (0x20000000UL) -#define HALL_SR_PHPREF_SHIFT (29U) -#define HALL_SR_PHPREF_SET(x) (((uint32_t)(x) << HALL_SR_PHPREF_SHIFT) & HALL_SR_PHPREF_MASK) -#define HALL_SR_PHPREF_GET(x) (((uint32_t)(x) & HALL_SR_PHPREF_MASK) >> HALL_SR_PHPREF_SHIFT) - -/* - * PHDLYF (RW) - * - * phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - */ -#define HALL_SR_PHDLYF_MASK (0x10000000UL) -#define HALL_SR_PHDLYF_SHIFT (28U) -#define HALL_SR_PHDLYF_SET(x) (((uint32_t)(x) << HALL_SR_PHDLYF_SHIFT) & HALL_SR_PHDLYF_MASK) -#define HALL_SR_PHDLYF_GET(x) (((uint32_t)(x) & HALL_SR_PHDLYF_MASK) >> HALL_SR_PHDLYF_SHIFT) - -/* - * UF (RW) - * - * u flag, will set when u signal toggle - */ -#define HALL_SR_UF_MASK (0x800000UL) -#define HALL_SR_UF_SHIFT (23U) -#define HALL_SR_UF_SET(x) (((uint32_t)(x) << HALL_SR_UF_SHIFT) & HALL_SR_UF_MASK) -#define HALL_SR_UF_GET(x) (((uint32_t)(x) & HALL_SR_UF_MASK) >> HALL_SR_UF_SHIFT) - -/* - * VF (RW) - * - * v flag, will set when v signal toggle - */ -#define HALL_SR_VF_MASK (0x400000UL) -#define HALL_SR_VF_SHIFT (22U) -#define HALL_SR_VF_SET(x) (((uint32_t)(x) << HALL_SR_VF_SHIFT) & HALL_SR_VF_MASK) -#define HALL_SR_VF_GET(x) (((uint32_t)(x) & HALL_SR_VF_MASK) >> HALL_SR_VF_SHIFT) - -/* - * WF (RW) - * - * w flag, will set when w signal toggle - */ -#define HALL_SR_WF_MASK (0x200000UL) -#define HALL_SR_WF_SHIFT (21U) -#define HALL_SR_WF_SET(x) (((uint32_t)(x) << HALL_SR_WF_SHIFT) & HALL_SR_WF_MASK) -#define HALL_SR_WF_GET(x) (((uint32_t)(x) & HALL_SR_WF_MASK) >> HALL_SR_WF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt request when wdg flag set - */ -#define HALL_IRQEN_WDGIE_MASK (0x80000000UL) -#define HALL_IRQEN_WDGIE_SHIFT (31U) -#define HALL_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WDGIE_SHIFT) & HALL_IRQEN_WDGIE_MASK) -#define HALL_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WDGIE_MASK) >> HALL_IRQEN_WDGIE_SHIFT) - -/* - * PHUPTIE (RW) - * - * 1- generate interrupt request when phupt flag set - */ -#define HALL_IRQEN_PHUPTIE_MASK (0x40000000UL) -#define HALL_IRQEN_PHUPTIE_SHIFT (30U) -#define HALL_IRQEN_PHUPTIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHUPTIE_SHIFT) & HALL_IRQEN_PHUPTIE_MASK) -#define HALL_IRQEN_PHUPTIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHUPTIE_MASK) >> HALL_IRQEN_PHUPTIE_SHIFT) - -/* - * PHPREIE (RW) - * - * 1- generate interrupt request when phpre flag set - */ -#define HALL_IRQEN_PHPREIE_MASK (0x20000000UL) -#define HALL_IRQEN_PHPREIE_SHIFT (29U) -#define HALL_IRQEN_PHPREIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHPREIE_SHIFT) & HALL_IRQEN_PHPREIE_MASK) -#define HALL_IRQEN_PHPREIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHPREIE_MASK) >> HALL_IRQEN_PHPREIE_SHIFT) - -/* - * PHDLYIE (RW) - * - * 1- generate interrupt request when phdly flag set - */ -#define HALL_IRQEN_PHDLYIE_MASK (0x10000000UL) -#define HALL_IRQEN_PHDLYIE_SHIFT (28U) -#define HALL_IRQEN_PHDLYIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHDLYIE_SHIFT) & HALL_IRQEN_PHDLYIE_MASK) -#define HALL_IRQEN_PHDLYIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHDLYIE_MASK) >> HALL_IRQEN_PHDLYIE_SHIFT) - -/* - * UFIE (RW) - * - * 1- generate interrupt request when u flag set - */ -#define HALL_IRQEN_UFIE_MASK (0x800000UL) -#define HALL_IRQEN_UFIE_SHIFT (23U) -#define HALL_IRQEN_UFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_UFIE_SHIFT) & HALL_IRQEN_UFIE_MASK) -#define HALL_IRQEN_UFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_UFIE_MASK) >> HALL_IRQEN_UFIE_SHIFT) - -/* - * VFIE (RW) - * - * 1- generate interrupt request when v flag set - */ -#define HALL_IRQEN_VFIE_MASK (0x400000UL) -#define HALL_IRQEN_VFIE_SHIFT (22U) -#define HALL_IRQEN_VFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_VFIE_SHIFT) & HALL_IRQEN_VFIE_MASK) -#define HALL_IRQEN_VFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_VFIE_MASK) >> HALL_IRQEN_VFIE_SHIFT) - -/* - * WFIE (RW) - * - * 1- generate interrupt request when w flag set - */ -#define HALL_IRQEN_WFIE_MASK (0x200000UL) -#define HALL_IRQEN_WFIE_SHIFT (21U) -#define HALL_IRQEN_WFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WFIE_SHIFT) & HALL_IRQEN_WFIE_MASK) -#define HALL_IRQEN_WFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WFIE_MASK) >> HALL_IRQEN_WFIE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: W */ -/* - * WCNT (RO) - * - * wcnt counter - */ -#define HALL_COUNT_W_WCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_W_WCNT_SHIFT (0U) -#define HALL_COUNT_W_WCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_W_WCNT_MASK) >> HALL_COUNT_W_WCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: V */ -/* - * VCNT (RO) - * - * vcnt counter - */ -#define HALL_COUNT_V_VCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_V_VCNT_SHIFT (0U) -#define HALL_COUNT_V_VCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_V_VCNT_MASK) >> HALL_COUNT_V_VCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: U */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define HALL_COUNT_U_DIR_MASK (0x80000000UL) -#define HALL_COUNT_U_DIR_SHIFT (31U) -#define HALL_COUNT_U_DIR_GET(x) (((uint32_t)(x) & HALL_COUNT_U_DIR_MASK) >> HALL_COUNT_U_DIR_SHIFT) - -/* - * USTAT (RO) - * - * this bit indicate U state - */ -#define HALL_COUNT_U_USTAT_MASK (0x40000000UL) -#define HALL_COUNT_U_USTAT_SHIFT (30U) -#define HALL_COUNT_U_USTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_USTAT_MASK) >> HALL_COUNT_U_USTAT_SHIFT) - -/* - * VSTAT (RO) - * - * this bit indicate V state - */ -#define HALL_COUNT_U_VSTAT_MASK (0x20000000UL) -#define HALL_COUNT_U_VSTAT_SHIFT (29U) -#define HALL_COUNT_U_VSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_VSTAT_MASK) >> HALL_COUNT_U_VSTAT_SHIFT) - -/* - * WSTAT (RO) - * - * this bit indicate W state - */ -#define HALL_COUNT_U_WSTAT_MASK (0x10000000UL) -#define HALL_COUNT_U_WSTAT_SHIFT (28U) -#define HALL_COUNT_U_WSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_WSTAT_MASK) >> HALL_COUNT_U_WSTAT_SHIFT) - -/* - * UCNT (RO) - * - * ucnt counter - */ -#define HALL_COUNT_U_UCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_U_UCNT_SHIFT (0U) -#define HALL_COUNT_U_UCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_UCNT_MASK) >> HALL_COUNT_U_UCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TIMER (RO) - * - * 32 bit free run timer - */ -#define HALL_COUNT_TMR_TIMER_MASK (0xFFFFFFFFUL) -#define HALL_COUNT_TMR_TIMER_SHIFT (0U) -#define HALL_COUNT_TMR_TIMER_GET(x) (((uint32_t)(x) & HALL_COUNT_TMR_TIMER_MASK) >> HALL_COUNT_TMR_TIMER_SHIFT) - -/* Bitfield definition for register of struct array HIS: HIS0 */ -/* - * UHIS0 (RO) - * - * copy of ucnt when u signal transition from 0 to 1 - */ -#define HALL_HIS_HIS0_UHIS0_MASK (0xFFFFFFFFUL) -#define HALL_HIS_HIS0_UHIS0_SHIFT (0U) -#define HALL_HIS_HIS0_UHIS0_GET(x) (((uint32_t)(x) & HALL_HIS_HIS0_UHIS0_MASK) >> HALL_HIS_HIS0_UHIS0_SHIFT) - -/* Bitfield definition for register of struct array HIS: HIS1 */ -/* - * UHIS1 (RO) - * - * copy of ucnt when u signal transition from 1 to 0 - */ -#define HALL_HIS_HIS1_UHIS1_MASK (0xFFFFFFFFUL) -#define HALL_HIS_HIS1_UHIS1_SHIFT (0U) -#define HALL_HIS_HIS1_UHIS1_GET(x) (((uint32_t)(x) & HALL_HIS_HIS1_UHIS1_MASK) >> HALL_HIS_HIS1_UHIS1_SHIFT) - - - -/* COUNT register group index macro definition */ -#define HALL_COUNT_CURRENT (0UL) -#define HALL_COUNT_READ (1UL) -#define HALL_COUNT_SNAP0 (2UL) -#define HALL_COUNT_SNAP1 (3UL) - -/* HIS register group index macro definition */ -#define HALL_HIS_U (0UL) -#define HALL_HIS_V (1UL) -#define HALL_HIS_W (2UL) - - -#endif /* HPM_HALL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_i2c_regs.h deleted file mode 100644 index 5c5c0025996..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_i2c_regs.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2C_H -#define HPM_I2C_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ - __RW uint32_t STATUS; /* 0x18: Status Register */ - __RW uint32_t ADDR; /* 0x1C: Address Register */ - __RW uint32_t DATA; /* 0x20: Data Register */ - __RW uint32_t CTRL; /* 0x24: Control Register */ - __RW uint32_t CMD; /* 0x28: Command Register */ - __RW uint32_t SETUP; /* 0x2C: Setup Register */ - __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ -} I2C_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * FIFO Size: - * 0: 2 bytes - * 1: 4 bytes - * 2: 8 bytes - * 3: 16 bytes - */ -#define I2C_CFG_FIFOSIZE_MASK (0x3U) -#define I2C_CFG_FIFOSIZE_SHIFT (0U) -#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * CMPL (RW) - * - * Set to enable the Completion Interrupt. - * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. - * Slave: interrupts when a transaction addressing the controller is completed. - */ -#define I2C_INTEN_CMPL_MASK (0x200U) -#define I2C_INTEN_CMPL_SHIFT (9U) -#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) -#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) - -/* - * BYTERECV (RW) - * - * Set to enable the Byte Receive Interrupt. - * Interrupts when a byte of data is received - * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - */ -#define I2C_INTEN_BYTERECV_MASK (0x100U) -#define I2C_INTEN_BYTERECV_SHIFT (8U) -#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) -#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) - -/* - * BYTETRANS (RW) - * - * Set to enable the Byte Transmit Interrupt. - * Interrupts when a byte of data is transmitted. - */ -#define I2C_INTEN_BYTETRANS_MASK (0x80U) -#define I2C_INTEN_BYTETRANS_SHIFT (7U) -#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) -#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) - -/* - * START (RW) - * - * Set to enable the START Condition Interrupt. - * Interrupts when a START condition/repeated START condition is detected. - */ -#define I2C_INTEN_START_MASK (0x40U) -#define I2C_INTEN_START_SHIFT (6U) -#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) -#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) - -/* - * STOP (RW) - * - * Set to enable the STOP Condition Interrupt - * Interrupts when a STOP condition is detected. - */ -#define I2C_INTEN_STOP_MASK (0x20U) -#define I2C_INTEN_STOP_SHIFT (5U) -#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) -#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) - -/* - * ARBLOSE (RW) - * - * Set to enable the Arbitration Lose Interrupt. - * Master: interrupts when the controller loses the bus arbitration - * Slave: not available in this mode. - */ -#define I2C_INTEN_ARBLOSE_MASK (0x10U) -#define I2C_INTEN_ARBLOSE_SHIFT (4U) -#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) -#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) - -/* - * ADDRHIT (RW) - * - * Set to enable the Address Hit Interrupt. - * Master: interrupts when the addressed slave returned an ACK. - * Slave: interrupts when the controller is addressed. - */ -#define I2C_INTEN_ADDRHIT_MASK (0x8U) -#define I2C_INTEN_ADDRHIT_SHIFT (3U) -#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) -#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RW) - * - * Set to enable the FIFO Half Interrupt. - * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. - * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. - * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - */ -#define I2C_INTEN_FIFOHALF_MASK (0x4U) -#define I2C_INTEN_FIFOHALF_SHIFT (2U) -#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) -#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RW) - * - * Set to enable the FIFO Full Interrupt. - * Interrupts when the FIFO is full. - */ -#define I2C_INTEN_FIFOFULL_MASK (0x2U) -#define I2C_INTEN_FIFOFULL_SHIFT (1U) -#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) -#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RW) - * - * Set to enabled the FIFO Empty Interrupt - * Interrupts when the FIFO is empty. - */ -#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) -#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) -#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) -#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * LINESDA (RO) - * - * Indicates the current status of the SDA line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESDA_MASK (0x4000U) -#define I2C_STATUS_LINESDA_SHIFT (14U) -#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) - -/* - * LINESCL (RO) - * - * Indicates the current status of the SCL line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESCL_MASK (0x2000U) -#define I2C_STATUS_LINESCL_SHIFT (13U) -#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) - -/* - * GENCALL (RO) - * - * Indicates that the address of the current transaction is a general call address: - * 1: General call - * 0: Not general call - */ -#define I2C_STATUS_GENCALL_MASK (0x1000U) -#define I2C_STATUS_GENCALL_SHIFT (12U) -#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) - -/* - * BUSBUSY (RO) - * - * Indicates that the bus is busy - * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus - * 1: Busy - * 0: Not busy - */ -#define I2C_STATUS_BUSBUSY_MASK (0x800U) -#define I2C_STATUS_BUSBUSY_SHIFT (11U) -#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) - -/* - * ACK (RO) - * - * Indicates the type of the last received/transmitted acknowledgement bit: - * 1: ACK - * 0: NACK - */ -#define I2C_STATUS_ACK_MASK (0x400U) -#define I2C_STATUS_ACK_SHIFT (10U) -#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) - -/* - * CMPL (W1C) - * - * Transaction Completion - * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration - * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - */ -#define I2C_STATUS_CMPL_MASK (0x200U) -#define I2C_STATUS_CMPL_SHIFT (9U) -#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) -#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) - -/* - * BYTERECV (W1C) - * - * Indicates that a byte of data has been received. - */ -#define I2C_STATUS_BYTERECV_MASK (0x100U) -#define I2C_STATUS_BYTERECV_SHIFT (8U) -#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) -#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) - -/* - * BYTETRANS (W1C) - * - * Indicates that a byte of data has been transmitted. - */ -#define I2C_STATUS_BYTETRANS_MASK (0x80U) -#define I2C_STATUS_BYTETRANS_SHIFT (7U) -#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) -#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) - -/* - * START (W1C) - * - * Indicates that a START Condition or a repeated START condition has been transmitted/received. - */ -#define I2C_STATUS_START_MASK (0x40U) -#define I2C_STATUS_START_SHIFT (6U) -#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) -#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) - -/* - * STOP (W1C) - * - * Indicates that a STOP Condition has been transmitted/received. - */ -#define I2C_STATUS_STOP_MASK (0x20U) -#define I2C_STATUS_STOP_SHIFT (5U) -#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) -#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) - -/* - * ARBLOSE (W1C) - * - * Indicates that the controller has lost the bus arbitration. - */ -#define I2C_STATUS_ARBLOSE_MASK (0x10U) -#define I2C_STATUS_ARBLOSE_SHIFT (4U) -#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) -#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) - -/* - * ADDRHIT (W1C) - * - * Master: indicates that a slave has responded to the transaction. - * Slave: indicates that a transaction is targeting the controller (including the General Call). - */ -#define I2C_STATUS_ADDRHIT_MASK (0x8U) -#define I2C_STATUS_ADDRHIT_SHIFT (3U) -#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) -#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RO) - * - * Transmitter: Indicates that the FIFO is half-empty. - */ -#define I2C_STATUS_FIFOHALF_MASK (0x4U) -#define I2C_STATUS_FIFOHALF_SHIFT (2U) -#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RO) - * - * Indicates that the FIFO is full. - */ -#define I2C_STATUS_FIFOFULL_MASK (0x2U) -#define I2C_STATUS_FIFOFULL_SHIFT (1U) -#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RO) - * - * Indicates that the FIFO is empty. - */ -#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) -#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) -#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * The slave address. - * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - */ -#define I2C_ADDR_ADDR_MASK (0x3FFU) -#define I2C_ADDR_ADDR_SHIFT (0U) -#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) -#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Write this register to put one byte of data to the FIFO. - * Read this register to get one byte of data from the FIFO. - */ -#define I2C_DATA_DATA_MASK (0xFFU) -#define I2C_DATA_DATA_SHIFT (0U) -#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) -#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * PHASE_START (RW) - * - * Enable this bit to send a START condition at the beginning of transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_START_MASK (0x1000U) -#define I2C_CTRL_PHASE_START_SHIFT (12U) -#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) -#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) - -/* - * PHASE_ADDR (RW) - * - * Enable this bit to send the address after START condition. - * Master mode only. - */ -#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) -#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) -#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) -#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) - -/* - * PHASE_DATA (RW) - * - * Enable this bit to send the data after Address phase. - * Master mode only. - */ -#define I2C_CTRL_PHASE_DATA_MASK (0x400U) -#define I2C_CTRL_PHASE_DATA_SHIFT (10U) -#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) -#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) - -/* - * PHASE_STOP (RW) - * - * Enable this bit to send a STOP condition at the end of a transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_STOP_MASK (0x200U) -#define I2C_CTRL_PHASE_STOP_SHIFT (9U) -#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) -#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) - -/* - * DIR (RW) - * - * Transaction direction - * Master: Set this bit to determine the direction for the next transaction. - * 0: Transmitter - * 1: Receiver - * Slave: The direction of the last received transaction. - * 0: Receiver - * 1: Transmitter - */ -#define I2C_CTRL_DIR_MASK (0x100U) -#define I2C_CTRL_DIR_SHIFT (8U) -#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) -#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) - -/* - * DATACNT (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_MASK (0xFFU) -#define I2C_CTRL_DATACNT_SHIFT (0U) -#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) -#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * Write this register with the following values to perform the corresponding actions: - * 0x0: no action - * 0x1: issue a data transaction (Master only) - * 0x2: respond with an ACK to the received byte - * 0x3: respond with a NACK to the received byte - * 0x4: clear the FIFO - * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) - * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. - * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - */ -#define I2C_CMD_CMD_MASK (0x7U) -#define I2C_CMD_CMD_SHIFT (0U) -#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) -#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) - -/* Bitfield definition for register: SETUP */ -/* - * T_SUDAT (RW) - * - * T_SUDAT defines the data setup time before releasing the SCL. - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) - * tpclk = PCLK period - * TPM = The multiplier value in Timing Parameter Multiplier Register - */ -#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) -#define I2C_SETUP_T_SUDAT_SHIFT (24U) -#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) -#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) - -/* - * T_SP (RW) - * - * T_SP defines the pulse width of spikes that must be suppressed by the input filter. - * Pulse width = T_SP * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_SP_MASK (0xE00000UL) -#define I2C_SETUP_T_SP_SHIFT (21U) -#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) -#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) - -/* - * T_HDDAT (RW) - * - * T_HDDAT defines the data hold time after SCL goes LOW - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) -#define I2C_SETUP_T_HDDAT_SHIFT (16U) -#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) -#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) - -/* - * T_SCLRADIO (RW) - * - * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. - * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) - * 1: ratio = 2 - * 0: ratio = 1 - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) -#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) -#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) -#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) - -/* - * T_SCLHI (RW) - * - * The HIGH period of generated SCL clock is defined by T_SCLHi. - * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) - * The T_SCLHi value must be greater than T_SP and T_HDDAT values. - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) -#define I2C_SETUP_T_SCLHI_SHIFT (4U) -#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) -#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) - -/* - * DMAEN (RW) - * - * Enable the direct memory access mode data transfer. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_DMAEN_MASK (0x8U) -#define I2C_SETUP_DMAEN_SHIFT (3U) -#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) -#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) - -/* - * MASTER (RW) - * - * Configure this device as a master or a slave. - * 1: Master mode - * 0: Slave mode - */ -#define I2C_SETUP_MASTER_MASK (0x4U) -#define I2C_SETUP_MASTER_SHIFT (2U) -#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) -#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) - -/* - * ADDRESSING (RW) - * - * I2C addressing mode: - * 1: 10-bit addressing mode - * 0: 7-bit addressing mode - */ -#define I2C_SETUP_ADDRESSING_MASK (0x2U) -#define I2C_SETUP_ADDRESSING_SHIFT (1U) -#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) -#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) - -/* - * IICEN (RW) - * - * Enable the I2C controller. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_IICEN_MASK (0x1U) -#define I2C_SETUP_IICEN_SHIFT (0U) -#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) -#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) - -/* Bitfield definition for register: TPM */ -/* - * TPM (RW) - * - * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - */ -#define I2C_TPM_TPM_MASK (0x1FU) -#define I2C_TPM_TPM_SHIFT (0U) -#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) -#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) - - - - -#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ioc_regs.h deleted file mode 100644 index 7bac3840655..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ioc_regs.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOC_H -#define HPM_IOC_H - -typedef struct { - struct { - __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ - __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[488]; -} IOC_Type; - - -/* Bitfield definition for register of struct array PAD: FUNC_CTL */ -/* - * LOOP_BACK (RW) - * - * force input on - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) - -/* - * ANALOG (RW) - * - * select analog pin in pad - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) -#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) -#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) -#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) - -/* - * ALT_SELECT (RW) - * - * alt select - * 0: ALT0 - * 1: ALT1 - * … - * 31:ALT31 - */ -#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) - -/* Bitfield definition for register of struct array PAD: PAD_CTL */ -/* - * HYS (RW) - * - * schmitt trigger enable - * 0: disable - * 1: enable - */ -#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) -#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) -#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) -#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) - -/* - * PRS (RW) - * - * select pull up/down internal resistance strength: - * For pull down, only have 100 Kohm resistance - * For pull up: - * 00: 100 KOhm - * 01: 47 KOhm - * 10: 22 KOhm - * 11: 22 KOhm - */ -#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) -#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) -#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) -#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) - -/* - * PS (RW) - * - * pull select - * 0: pull down - * 1: pull up - */ -#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) -#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) -#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) -#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) - -/* - * PE (RW) - * - * pull enable - * 0: pull disable - * 1: pull enable - */ -#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) -#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) -#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) -#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) - -/* - * KE (RW) - * - * keeper capability enable - * 0: keeper disable - * 1: keeper enable - */ -#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) -#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) -#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) -#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) - -/* - * OD (RW) - * - * open drain - * 0: open drain disable - * 1: open drain enable - */ -#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) -#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) -#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) -#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) - -/* - * SR (RW) - * - * slew rate - * 0: Slow slew rate - * 1: Fast slew rate - */ -#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) -#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) -#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) -#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) - -/* - * SPD (RW) - * - * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise - * 00: Slow frequency slew rate(50Mhz) - * 01: Medium frequency slew rate(100 Mhz) - * 10: Fast frequency slew rate(150 Mhz) - * 11: Max frequency slew rate(200Mhz) - */ -#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) -#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) -#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) -#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) - -/* - * DS (RW) - * - * drive strength - * 1.8V Mode: - * 000: 260 Ohm - * 001: 260 Ohm - * 010: 130 Ohm - * 011: 88 Ohm - * 100: 65 Ohm - * 101: 52 Ohm - * 110: 43 Ohm - * 111: 37 Ohm - * 3.3V Mode: - * 000: 157 Ohm - * 001: 157 Ohm - * 010: 78 Ohm - * 011: 53 Ohm - * 100: 39 Ohm - * 101: 32 Ohm - * 110: 26 Ohm - * 111: 23 Ohm - */ -#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) -#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) -#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) -#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) - - - -/* PAD register group index macro definition */ -#define IOC_PAD_PA00 (0UL) -#define IOC_PAD_PA01 (1UL) -#define IOC_PAD_PA02 (2UL) -#define IOC_PAD_PA03 (3UL) -#define IOC_PAD_PA04 (4UL) -#define IOC_PAD_PA05 (5UL) -#define IOC_PAD_PA06 (6UL) -#define IOC_PAD_PA07 (7UL) -#define IOC_PAD_PA08 (8UL) -#define IOC_PAD_PA09 (9UL) -#define IOC_PAD_PA10 (10UL) -#define IOC_PAD_PA11 (11UL) -#define IOC_PAD_PA12 (12UL) -#define IOC_PAD_PA13 (13UL) -#define IOC_PAD_PA14 (14UL) -#define IOC_PAD_PA15 (15UL) -#define IOC_PAD_PA16 (16UL) -#define IOC_PAD_PA17 (17UL) -#define IOC_PAD_PA18 (18UL) -#define IOC_PAD_PA19 (19UL) -#define IOC_PAD_PA20 (20UL) -#define IOC_PAD_PA21 (21UL) -#define IOC_PAD_PA22 (22UL) -#define IOC_PAD_PA23 (23UL) -#define IOC_PAD_PA24 (24UL) -#define IOC_PAD_PA25 (25UL) -#define IOC_PAD_PA26 (26UL) -#define IOC_PAD_PA27 (27UL) -#define IOC_PAD_PA28 (28UL) -#define IOC_PAD_PA29 (29UL) -#define IOC_PAD_PA30 (30UL) -#define IOC_PAD_PA31 (31UL) -#define IOC_PAD_PB00 (32UL) -#define IOC_PAD_PB01 (33UL) -#define IOC_PAD_PB02 (34UL) -#define IOC_PAD_PB03 (35UL) -#define IOC_PAD_PB04 (36UL) -#define IOC_PAD_PB05 (37UL) -#define IOC_PAD_PB06 (38UL) -#define IOC_PAD_PB07 (39UL) -#define IOC_PAD_PB08 (40UL) -#define IOC_PAD_PB09 (41UL) -#define IOC_PAD_PB10 (42UL) -#define IOC_PAD_PB11 (43UL) -#define IOC_PAD_PB12 (44UL) -#define IOC_PAD_PB13 (45UL) -#define IOC_PAD_PB14 (46UL) -#define IOC_PAD_PB15 (47UL) -#define IOC_PAD_PB16 (48UL) -#define IOC_PAD_PB17 (49UL) -#define IOC_PAD_PB18 (50UL) -#define IOC_PAD_PB19 (51UL) -#define IOC_PAD_PB20 (52UL) -#define IOC_PAD_PB21 (53UL) -#define IOC_PAD_PB22 (54UL) -#define IOC_PAD_PB23 (55UL) -#define IOC_PAD_PB24 (56UL) -#define IOC_PAD_PB25 (57UL) -#define IOC_PAD_PB26 (58UL) -#define IOC_PAD_PB27 (59UL) -#define IOC_PAD_PB28 (60UL) -#define IOC_PAD_PB29 (61UL) -#define IOC_PAD_PB30 (62UL) -#define IOC_PAD_PB31 (63UL) -#define IOC_PAD_PC00 (64UL) -#define IOC_PAD_PC01 (65UL) -#define IOC_PAD_PC02 (66UL) -#define IOC_PAD_PC03 (67UL) -#define IOC_PAD_PC04 (68UL) -#define IOC_PAD_PC05 (69UL) -#define IOC_PAD_PC06 (70UL) -#define IOC_PAD_PC07 (71UL) -#define IOC_PAD_PC08 (72UL) -#define IOC_PAD_PC09 (73UL) -#define IOC_PAD_PC10 (74UL) -#define IOC_PAD_PC11 (75UL) -#define IOC_PAD_PC12 (76UL) -#define IOC_PAD_PC13 (77UL) -#define IOC_PAD_PC14 (78UL) -#define IOC_PAD_PC15 (79UL) -#define IOC_PAD_PC16 (80UL) -#define IOC_PAD_PC17 (81UL) -#define IOC_PAD_PC18 (82UL) -#define IOC_PAD_PC19 (83UL) -#define IOC_PAD_PC20 (84UL) -#define IOC_PAD_PC21 (85UL) -#define IOC_PAD_PC22 (86UL) -#define IOC_PAD_PC23 (87UL) -#define IOC_PAD_PC24 (88UL) -#define IOC_PAD_PC25 (89UL) -#define IOC_PAD_PC26 (90UL) -#define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PX00 (416UL) -#define IOC_PAD_PX01 (417UL) -#define IOC_PAD_PX02 (418UL) -#define IOC_PAD_PX03 (419UL) -#define IOC_PAD_PX04 (420UL) -#define IOC_PAD_PX05 (421UL) -#define IOC_PAD_PX06 (422UL) -#define IOC_PAD_PX07 (423UL) -#define IOC_PAD_PY00 (448UL) -#define IOC_PAD_PY01 (449UL) -#define IOC_PAD_PY02 (450UL) -#define IOC_PAD_PY03 (451UL) -#define IOC_PAD_PY04 (452UL) -#define IOC_PAD_PY05 (453UL) -#define IOC_PAD_PY06 (454UL) -#define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PZ00 (480UL) -#define IOC_PAD_PZ01 (481UL) -#define IOC_PAD_PZ02 (482UL) -#define IOC_PAD_PZ03 (483UL) -#define IOC_PAD_PZ04 (484UL) -#define IOC_PAD_PZ05 (485UL) -#define IOC_PAD_PZ06 (486UL) -#define IOC_PAD_PZ07 (487UL) - - -#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_keym_regs.h deleted file mode 100644 index 0d97ce1ecb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_keym_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_KEYM_H -#define HPM_KEYM_H - -typedef struct { - __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ - __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ - __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ - __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ - __RW uint32_t RNG; /* 0x48: Random number interface behavior */ - __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ -} KEYM_Type; - - -/* Bitfield definition for register array: SOFTMKEY */ -/* - * KEY (RW) - * - * software symmetric key - * key will be scambled to 4 variants for software to use, and replicable on same chip. - * scramble keys are chip different, and not replicable on different chip - * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - */ -#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTMKEY_KEY_SHIFT (0U) -#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) -#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) - -/* Bitfield definition for register array: SOFTPKEY */ -/* - * KEY (RW) - * - * software asymmetric key - * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. - * This key os read once, sencondary read will read out 0 - */ -#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTPKEY_KEY_SHIFT (0U) -#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) -#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) - -/* Bitfield definition for register: SEC_KEY_CTL */ -/* - * LOCK_SEC_CTL (RW) - * - * block secure state key setting being changed - */ -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use origin value in software symmetric key - * 1: use scramble version of software symmetric key - */ -#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use alnertave scramble of fuse symmetric key - */ -#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: NSC_KEY_CTL */ -/* - * LOCK_NSC_CTL (RW) - * - * block non-secure state key setting being changed - */ -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use origin value in fuse symmetric key - */ -#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * non-secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: RNG */ -/* - * BLOCK_RNG_XOR (RW) - * - * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset - * 0: RNG_XOR can be changed by software - * 1: RNG_XOR ignore software change from software - */ -#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) -#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) -#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) -#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) - -/* - * RNG_XOR (RW) - * - * control how SFK is accepted from random number generator - * 0: SFK value replaced by random number input - * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - */ -#define KEYM_RNG_RNG_XOR_MASK (0x1U) -#define KEYM_RNG_RNG_XOR_SHIFT (0U) -#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) -#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) - -/* Bitfield definition for register: READ_CONTROL */ -/* - * BLOCK_PK_READ (RW) - * - * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) - -/* - * BLOCK_SMK_READ (RW) - * - * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) - - - -/* SOFTMKEY register group index macro definition */ -#define KEYM_SOFTMKEY_SFK0 (0UL) -#define KEYM_SOFTMKEY_SFK1 (1UL) -#define KEYM_SOFTMKEY_SFK2 (2UL) -#define KEYM_SOFTMKEY_SFK3 (3UL) -#define KEYM_SOFTMKEY_SFK4 (4UL) -#define KEYM_SOFTMKEY_SFK5 (5UL) -#define KEYM_SOFTMKEY_SFK6 (6UL) -#define KEYM_SOFTMKEY_SFK7 (7UL) - -/* SOFTPKEY register group index macro definition */ -#define KEYM_SOFTPKEY_SPK0 (0UL) -#define KEYM_SOFTPKEY_SPK1 (1UL) -#define KEYM_SOFTPKEY_SPK2 (2UL) -#define KEYM_SOFTPKEY_SPK3 (3UL) -#define KEYM_SOFTPKEY_SPK4 (4UL) -#define KEYM_SOFTPKEY_SPK5 (5UL) -#define KEYM_SOFTPKEY_SPK6 (6UL) -#define KEYM_SOFTPKEY_SPK7 (7UL) - - -#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_lin_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_lin_regs.h deleted file mode 100644 index a0d44c85720..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_lin_regs.h +++ /dev/null @@ -1,355 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LIN_H -#define HPM_LIN_H - -typedef struct { - __RW uint32_t DATABYTE[8]; /* 0x0 - 0x1C: data byte */ - __RW uint32_t CONTROL; /* 0x20: control register */ - __R uint32_t STATE; /* 0x24: state register */ - __R uint32_t ERROR; /* 0x28: error register */ - __RW uint32_t DATA_LEN; /* 0x2C: data lenth register */ - __RW uint32_t BAUDRATE_CTL_LOW; /* 0x30: baudrate control low register */ - __RW uint32_t BARDRATE_CTL_HIGH; /* 0x34: baudrate control high register */ - __RW uint32_t ID; /* 0x38: id register */ - __RW uint32_t TV; /* 0x3C: timeout control register */ -} LIN_Type; - - -/* Bitfield definition for register array: DATABYTE */ -/* - * DATA_BYTE (RW) - * - * data byte - */ -#define LIN_DATABYTE_DATA_BYTE_MASK (0xFFU) -#define LIN_DATABYTE_DATA_BYTE_SHIFT (0U) -#define LIN_DATABYTE_DATA_BYTE_SET(x) (((uint32_t)(x) << LIN_DATABYTE_DATA_BYTE_SHIFT) & LIN_DATABYTE_DATA_BYTE_MASK) -#define LIN_DATABYTE_DATA_BYTE_GET(x) (((uint32_t)(x) & LIN_DATABYTE_DATA_BYTE_MASK) >> LIN_DATABYTE_DATA_BYTE_SHIFT) - -/* Bitfield definition for register: CONTROL */ -/* - * STOP (WO) - * - * slave only. Write 1 when the Host determin do not response to the data request according to a unkown ID - */ -#define LIN_CONTROL_STOP_MASK (0x80U) -#define LIN_CONTROL_STOP_SHIFT (7U) -#define LIN_CONTROL_STOP_SET(x) (((uint32_t)(x) << LIN_CONTROL_STOP_SHIFT) & LIN_CONTROL_STOP_MASK) -#define LIN_CONTROL_STOP_GET(x) (((uint32_t)(x) & LIN_CONTROL_STOP_MASK) >> LIN_CONTROL_STOP_SHIFT) - -/* - * SLEEP (RW) - * - * The bit is used by the LIN core to determine whether the LIN bus is in sleep mode or not. Set this bit after sending or receiving a Sleep Mode frame or if a bus idle timeout interrupt is requested or if after a wakeup request there is no response from the master and a timeout is signaled. The bit will be automatically reset by the LIN core. - */ -#define LIN_CONTROL_SLEEP_MASK (0x40U) -#define LIN_CONTROL_SLEEP_SHIFT (6U) -#define LIN_CONTROL_SLEEP_SET(x) (((uint32_t)(x) << LIN_CONTROL_SLEEP_SHIFT) & LIN_CONTROL_SLEEP_MASK) -#define LIN_CONTROL_SLEEP_GET(x) (((uint32_t)(x) & LIN_CONTROL_SLEEP_MASK) >> LIN_CONTROL_SLEEP_SHIFT) - -/* - * TRANSMIT (RW) - * - * 1: transmit operation 0: receive operation - */ -#define LIN_CONTROL_TRANSMIT_MASK (0x20U) -#define LIN_CONTROL_TRANSMIT_SHIFT (5U) -#define LIN_CONTROL_TRANSMIT_SET(x) (((uint32_t)(x) << LIN_CONTROL_TRANSMIT_SHIFT) & LIN_CONTROL_TRANSMIT_MASK) -#define LIN_CONTROL_TRANSMIT_GET(x) (((uint32_t)(x) & LIN_CONTROL_TRANSMIT_MASK) >> LIN_CONTROL_TRANSMIT_SHIFT) - -/* - * DATA_ACK (RW) - * - * slave only. Write 1 after handling a data request interrupt - */ -#define LIN_CONTROL_DATA_ACK_MASK (0x10U) -#define LIN_CONTROL_DATA_ACK_SHIFT (4U) -#define LIN_CONTROL_DATA_ACK_SET(x) (((uint32_t)(x) << LIN_CONTROL_DATA_ACK_SHIFT) & LIN_CONTROL_DATA_ACK_MASK) -#define LIN_CONTROL_DATA_ACK_GET(x) (((uint32_t)(x) & LIN_CONTROL_DATA_ACK_MASK) >> LIN_CONTROL_DATA_ACK_SHIFT) - -/* - * RESET_INT (WO) - * - * write 1 to reset the int bit in the status register and the interrupt request output of LIN - */ -#define LIN_CONTROL_RESET_INT_MASK (0x8U) -#define LIN_CONTROL_RESET_INT_SHIFT (3U) -#define LIN_CONTROL_RESET_INT_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_INT_SHIFT) & LIN_CONTROL_RESET_INT_MASK) -#define LIN_CONTROL_RESET_INT_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_INT_MASK) >> LIN_CONTROL_RESET_INT_SHIFT) - -/* - * RESET_ERROR (WO) - * - * assert 1 to reset the error bits in status register and error register. A read access to this bit delivers always the value 0 - */ -#define LIN_CONTROL_RESET_ERROR_MASK (0x4U) -#define LIN_CONTROL_RESET_ERROR_SHIFT (2U) -#define LIN_CONTROL_RESET_ERROR_SET(x) (((uint32_t)(x) << LIN_CONTROL_RESET_ERROR_SHIFT) & LIN_CONTROL_RESET_ERROR_MASK) -#define LIN_CONTROL_RESET_ERROR_GET(x) (((uint32_t)(x) & LIN_CONTROL_RESET_ERROR_MASK) >> LIN_CONTROL_RESET_ERROR_SHIFT) - -/* - * WAKEUP_REQ (RW) - * - * wakeup request. Assert to terminate the Sleep mode of the LIN bus. The bit will be reset by core - */ -#define LIN_CONTROL_WAKEUP_REQ_MASK (0x2U) -#define LIN_CONTROL_WAKEUP_REQ_SHIFT (1U) -#define LIN_CONTROL_WAKEUP_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_WAKEUP_REQ_SHIFT) & LIN_CONTROL_WAKEUP_REQ_MASK) -#define LIN_CONTROL_WAKEUP_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_WAKEUP_REQ_MASK) >> LIN_CONTROL_WAKEUP_REQ_SHIFT) - -/* - * START_REQ (RW) - * - * master only. Set by host controller of a LIN master to start the LIN transmission. The core will reset the bit after the transmission is finished or an error is occurred - */ -#define LIN_CONTROL_START_REQ_MASK (0x1U) -#define LIN_CONTROL_START_REQ_SHIFT (0U) -#define LIN_CONTROL_START_REQ_SET(x) (((uint32_t)(x) << LIN_CONTROL_START_REQ_SHIFT) & LIN_CONTROL_START_REQ_MASK) -#define LIN_CONTROL_START_REQ_GET(x) (((uint32_t)(x) & LIN_CONTROL_START_REQ_MASK) >> LIN_CONTROL_START_REQ_SHIFT) - -/* Bitfield definition for register: STATE */ -/* - * LIN_ACTIVE (RO) - * - * The bit indicates whether the LIN bus is active or not - */ -#define LIN_STATE_LIN_ACTIVE_MASK (0x80U) -#define LIN_STATE_LIN_ACTIVE_SHIFT (7U) -#define LIN_STATE_LIN_ACTIVE_GET(x) (((uint32_t)(x) & LIN_STATE_LIN_ACTIVE_MASK) >> LIN_STATE_LIN_ACTIVE_SHIFT) - -/* - * BUS_IDLE_TV (RO) - * - * slave only. This bit is set by LIN core if bit sleep is not set and no bus activity is detected for 4s - */ -#define LIN_STATE_BUS_IDLE_TV_MASK (0x40U) -#define LIN_STATE_BUS_IDLE_TV_SHIFT (6U) -#define LIN_STATE_BUS_IDLE_TV_GET(x) (((uint32_t)(x) & LIN_STATE_BUS_IDLE_TV_MASK) >> LIN_STATE_BUS_IDLE_TV_SHIFT) - -/* - * ABORTED (RO) - * - * slave only. This bit is set by LIN core slave if a transmission is aborted after the bneginning of the data field due to a timeout or bit error. - */ -#define LIN_STATE_ABORTED_MASK (0x20U) -#define LIN_STATE_ABORTED_SHIFT (5U) -#define LIN_STATE_ABORTED_GET(x) (((uint32_t)(x) & LIN_STATE_ABORTED_MASK) >> LIN_STATE_ABORTED_SHIFT) - -/* - * DATA_REQ (RO) - * - * slave only. Sets after receiving the identifier and requests an interrupt to the host controller. - */ -#define LIN_STATE_DATA_REQ_MASK (0x10U) -#define LIN_STATE_DATA_REQ_SHIFT (4U) -#define LIN_STATE_DATA_REQ_GET(x) (((uint32_t)(x) & LIN_STATE_DATA_REQ_MASK) >> LIN_STATE_DATA_REQ_SHIFT) - -/* - * INT (RO) - * - * set when request an interrupt. Reset by reset_int - */ -#define LIN_STATE_INT_MASK (0x8U) -#define LIN_STATE_INT_SHIFT (3U) -#define LIN_STATE_INT_GET(x) (((uint32_t)(x) & LIN_STATE_INT_MASK) >> LIN_STATE_INT_SHIFT) - -/* - * ERROR (RO) - * - * set when detecte an error, clear by reset_error - */ -#define LIN_STATE_ERROR_MASK (0x4U) -#define LIN_STATE_ERROR_SHIFT (2U) -#define LIN_STATE_ERROR_GET(x) (((uint32_t)(x) & LIN_STATE_ERROR_MASK) >> LIN_STATE_ERROR_SHIFT) - -/* - * WAKEUP (RO) - * - * set when transmitting a wakeup signal or when received a wakeup signal. Clear when reset_error bit is 1 - */ -#define LIN_STATE_WAKEUP_MASK (0x2U) -#define LIN_STATE_WAKEUP_SHIFT (1U) -#define LIN_STATE_WAKEUP_GET(x) (((uint32_t)(x) & LIN_STATE_WAKEUP_MASK) >> LIN_STATE_WAKEUP_SHIFT) - -/* - * COMPLETE (RO) - * - * set after a transmission has been successful finished and it will reset at the start of a transmission. - */ -#define LIN_STATE_COMPLETE_MASK (0x1U) -#define LIN_STATE_COMPLETE_SHIFT (0U) -#define LIN_STATE_COMPLETE_GET(x) (((uint32_t)(x) & LIN_STATE_COMPLETE_MASK) >> LIN_STATE_COMPLETE_SHIFT) - -/* Bitfield definition for register: ERROR */ -/* - * PARITY_ERROR (RO) - * - * slave only. identifier parity error - */ -#define LIN_ERROR_PARITY_ERROR_MASK (0x8U) -#define LIN_ERROR_PARITY_ERROR_SHIFT (3U) -#define LIN_ERROR_PARITY_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_PARITY_ERROR_MASK) >> LIN_ERROR_PARITY_ERROR_SHIFT) - -/* - * TIMEOUT (RO) - * - * timeout error. The master detects a timeout error if it is expecting data from the bus but no slave does respond. The slave detects a timeout error if it is requesting a data acknowledge to the host controller. The slave detects a timeout if it has transmitted a wakeup signal and it detects no sync field within 150ms - */ -#define LIN_ERROR_TIMEOUT_MASK (0x4U) -#define LIN_ERROR_TIMEOUT_SHIFT (2U) -#define LIN_ERROR_TIMEOUT_GET(x) (((uint32_t)(x) & LIN_ERROR_TIMEOUT_MASK) >> LIN_ERROR_TIMEOUT_SHIFT) - -/* - * CHK_ERROR (RO) - * - * checksum error - */ -#define LIN_ERROR_CHK_ERROR_MASK (0x2U) -#define LIN_ERROR_CHK_ERROR_SHIFT (1U) -#define LIN_ERROR_CHK_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_CHK_ERROR_MASK) >> LIN_ERROR_CHK_ERROR_SHIFT) - -/* - * BIT_ERROR (RO) - * - * bit error - */ -#define LIN_ERROR_BIT_ERROR_MASK (0x1U) -#define LIN_ERROR_BIT_ERROR_SHIFT (0U) -#define LIN_ERROR_BIT_ERROR_GET(x) (((uint32_t)(x) & LIN_ERROR_BIT_ERROR_MASK) >> LIN_ERROR_BIT_ERROR_SHIFT) - -/* Bitfield definition for register: DATA_LEN */ -/* - * ENH_CHECK (RW) - * - * 1:enhence check mode - */ -#define LIN_DATA_LEN_ENH_CHECK_MASK (0x80U) -#define LIN_DATA_LEN_ENH_CHECK_SHIFT (7U) -#define LIN_DATA_LEN_ENH_CHECK_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_ENH_CHECK_SHIFT) & LIN_DATA_LEN_ENH_CHECK_MASK) -#define LIN_DATA_LEN_ENH_CHECK_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_ENH_CHECK_MASK) >> LIN_DATA_LEN_ENH_CHECK_SHIFT) - -/* - * DATA_LENGTH (RW) - * - * data length - */ -#define LIN_DATA_LEN_DATA_LENGTH_MASK (0xFU) -#define LIN_DATA_LEN_DATA_LENGTH_SHIFT (0U) -#define LIN_DATA_LEN_DATA_LENGTH_SET(x) (((uint32_t)(x) << LIN_DATA_LEN_DATA_LENGTH_SHIFT) & LIN_DATA_LEN_DATA_LENGTH_MASK) -#define LIN_DATA_LEN_DATA_LENGTH_GET(x) (((uint32_t)(x) & LIN_DATA_LEN_DATA_LENGTH_MASK) >> LIN_DATA_LEN_DATA_LENGTH_SHIFT) - -/* Bitfield definition for register: BAUDRATE_CTL_LOW */ -/* - * BT_DIV_LOW (RW) - * - * bit div register 7:0 - */ -#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK (0xFFU) -#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT (0U) -#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SET(x) (((uint32_t)(x) << LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) -#define LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_GET(x) (((uint32_t)(x) & LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_MASK) >> LIN_BAUDRATE_CTL_LOW_BT_DIV_LOW_SHIFT) - -/* Bitfield definition for register: BARDRATE_CTL_HIGH */ -/* - * PRESCL (RW) - * - * prescl register - */ -#define LIN_BARDRATE_CTL_HIGH_PRESCL_MASK (0xC0U) -#define LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT (6U) -#define LIN_BARDRATE_CTL_HIGH_PRESCL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) -#define LIN_BARDRATE_CTL_HIGH_PRESCL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_PRESCL_MASK) >> LIN_BARDRATE_CTL_HIGH_PRESCL_SHIFT) - -/* - * BT_MUL (RW) - * - * bt_mul register - */ -#define LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK (0x3EU) -#define LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT (1U) -#define LIN_BARDRATE_CTL_HIGH_BT_MUL_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) -#define LIN_BARDRATE_CTL_HIGH_BT_MUL_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_MUL_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_MUL_SHIFT) - -/* - * BT_DIV_HIGH (RW) - * - * bit div register 8 - */ -#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK (0x1U) -#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT (0U) -#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SET(x) (((uint32_t)(x) << LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) -#define LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_GET(x) (((uint32_t)(x) & LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_MASK) >> LIN_BARDRATE_CTL_HIGH_BT_DIV_HIGH_SHIFT) - -/* Bitfield definition for register: ID */ -/* - * ID (RW) - * - * id register - */ -#define LIN_ID_ID_MASK (0x3FU) -#define LIN_ID_ID_SHIFT (0U) -#define LIN_ID_ID_SET(x) (((uint32_t)(x) << LIN_ID_ID_SHIFT) & LIN_ID_ID_MASK) -#define LIN_ID_ID_GET(x) (((uint32_t)(x) & LIN_ID_ID_MASK) >> LIN_ID_ID_SHIFT) - -/* Bitfield definition for register: TV */ -/* - * INITIAL_MODE (RW) - * - * initial_mode - */ -#define LIN_TV_INITIAL_MODE_MASK (0x80U) -#define LIN_TV_INITIAL_MODE_SHIFT (7U) -#define LIN_TV_INITIAL_MODE_SET(x) (((uint32_t)(x) << LIN_TV_INITIAL_MODE_SHIFT) & LIN_TV_INITIAL_MODE_MASK) -#define LIN_TV_INITIAL_MODE_GET(x) (((uint32_t)(x) & LIN_TV_INITIAL_MODE_MASK) >> LIN_TV_INITIAL_MODE_SHIFT) - -/* - * MASTER_MODE (RW) - * - * master_mode - */ -#define LIN_TV_MASTER_MODE_MASK (0x40U) -#define LIN_TV_MASTER_MODE_SHIFT (6U) -#define LIN_TV_MASTER_MODE_SET(x) (((uint32_t)(x) << LIN_TV_MASTER_MODE_SHIFT) & LIN_TV_MASTER_MODE_MASK) -#define LIN_TV_MASTER_MODE_GET(x) (((uint32_t)(x) & LIN_TV_MASTER_MODE_MASK) >> LIN_TV_MASTER_MODE_SHIFT) - -/* - * BUS_INACTIVITY_TIME (RW) - * - * slave only. LIN bus idle timeout register： 00-4s 01-6s 10-8s 11-10s - */ -#define LIN_TV_BUS_INACTIVITY_TIME_MASK (0xCU) -#define LIN_TV_BUS_INACTIVITY_TIME_SHIFT (2U) -#define LIN_TV_BUS_INACTIVITY_TIME_SET(x) (((uint32_t)(x) << LIN_TV_BUS_INACTIVITY_TIME_SHIFT) & LIN_TV_BUS_INACTIVITY_TIME_MASK) -#define LIN_TV_BUS_INACTIVITY_TIME_GET(x) (((uint32_t)(x) & LIN_TV_BUS_INACTIVITY_TIME_MASK) >> LIN_TV_BUS_INACTIVITY_TIME_SHIFT) - -/* - * WUP_REPEAT_TIME (RW) - * - * slave only. wakeup repeat interval time 00-180ms 01-200ms 10-220ms 11-240ms - */ -#define LIN_TV_WUP_REPEAT_TIME_MASK (0x3U) -#define LIN_TV_WUP_REPEAT_TIME_SHIFT (0U) -#define LIN_TV_WUP_REPEAT_TIME_SET(x) (((uint32_t)(x) << LIN_TV_WUP_REPEAT_TIME_SHIFT) & LIN_TV_WUP_REPEAT_TIME_MASK) -#define LIN_TV_WUP_REPEAT_TIME_GET(x) (((uint32_t)(x) & LIN_TV_WUP_REPEAT_TIME_MASK) >> LIN_TV_WUP_REPEAT_TIME_SHIFT) - - - -/* DATABYTE register group index macro definition */ -#define LIN_DATABYTE_DATA_BYTE0 (0UL) -#define LIN_DATABYTE_DATA_BYTE1 (1UL) -#define LIN_DATABYTE_DATA_BYTE2 (2UL) -#define LIN_DATABYTE_DATA_BYTE3 (3UL) -#define LIN_DATABYTE_DATA_BYTE4 (4UL) -#define LIN_DATABYTE_DATA_BYTE5 (5UL) -#define LIN_DATABYTE_DATA_BYTE6 (6UL) -#define LIN_DATABYTE_DATA_BYTE7 (7UL) - - -#endif /* HPM_LIN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mbx_regs.h deleted file mode 100644 index d159b97303a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mbx_regs.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_H -#define HPM_MBX_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Command Registers */ - __RW uint32_t SR; /* 0x4: Status Registers */ - __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ - __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ - __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ -} MBX_Type; - - -/* Bitfield definition for register: CR */ -/* - * TXRESET (RW) - * - * Reset TX Fifo and word. - */ -#define MBX_CR_TXRESET_MASK (0x80000000UL) -#define MBX_CR_TXRESET_SHIFT (31U) -#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) -#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) - -/* - * BARCTL (RW) - * - * Bus Access Response Control, when bit 15:14= - * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. - * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. - * 11: reserved. - */ -#define MBX_CR_BARCTL_MASK (0xC000U) -#define MBX_CR_BARCTL_SHIFT (14U) -#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) -#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. - * 1, enable the bus access error interrupt. - * 0, disable the bus access error interrupt. - */ -#define MBX_CR_BEIE_MASK (0x100U) -#define MBX_CR_BEIE_SHIFT (8U) -#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) -#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) - -/* - * TFMAIE (RW) - * - * TX FIFO message available interrupt enable. - * 1, enable the TX FIFO massage available interrupt. - * 0, disable the TX FIFO message available interrupt. - */ -#define MBX_CR_TFMAIE_MASK (0x80U) -#define MBX_CR_TFMAIE_SHIFT (7U) -#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) -#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) - -/* - * TFMEIE (RW) - * - * TX FIFO message empty interrupt enable. - * 1, enable the TX FIFO massage empty interrupt. - * 0, disable the TX FIFO message empty interrupt. - */ -#define MBX_CR_TFMEIE_MASK (0x40U) -#define MBX_CR_TFMEIE_SHIFT (6U) -#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) -#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) - -/* - * RFMAIE (RW) - * - * RX FIFO message available interrupt enable. - * 1, enable the RX FIFO massage available interrupt. - * 0, disable the RX FIFO message available interrupt. - */ -#define MBX_CR_RFMAIE_MASK (0x20U) -#define MBX_CR_RFMAIE_SHIFT (5U) -#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) -#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) - -/* - * RFMFIE (RW) - * - * RX fifo message full interrupt enable. - * 1, enable the RX fifo message full interrupt. - * 0, disable the RX fifo message full interrupt. - */ -#define MBX_CR_RFMFIE_MASK (0x10U) -#define MBX_CR_RFMFIE_SHIFT (4U) -#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) -#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) - -/* - * TWMEIE (RW) - * - * TX word message empty interrupt enable. - * 1, enable the TX word massage empty interrupt. - * 0, disable the TX word message empty interrupt. - */ -#define MBX_CR_TWMEIE_MASK (0x2U) -#define MBX_CR_TWMEIE_SHIFT (1U) -#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) -#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) - -/* - * RWMVIE (RW) - * - * RX word message valid interrupt enable. - * 1, enable the RX word massage valid interrupt. - * 0, disable the RX word message valid interrupt. - */ -#define MBX_CR_RWMVIE_MASK (0x1U) -#define MBX_CR_RWMVIE_SHIFT (0U) -#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) -#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * RFVC (RO) - * - * RX FIFO valid message count - */ -#define MBX_SR_RFVC_MASK (0xF00000UL) -#define MBX_SR_RFVC_SHIFT (20U) -#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) - -/* - * TFEC (RO) - * - * TX FIFO empty message word count - */ -#define MBX_SR_TFEC_MASK (0xF0000UL) -#define MBX_SR_TFEC_SHIFT (16U) -#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) - -/* - * ERRRE (W1C) - * - * bus Error for read when rx word message are still invalid, this bit is W1C bit. - * 1, read from word message when the word message are still invalid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRRE_MASK (0x2000U) -#define MBX_SR_ERRRE_SHIFT (13U) -#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) -#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) - -/* - * EWTRF (W1C) - * - * bus Error for write when tx word message are still valid, this bit is W1C bit. - * 1, write to word message when the word message are still valid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTRF_MASK (0x1000U) -#define MBX_SR_EWTRF_SHIFT (12U) -#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) -#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) - -/* - * ERRFE (W1C) - * - * bus Error for read when rx fifo empty, this bit is W1C bit. - * 1, read from a empty rx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRFE_MASK (0x800U) -#define MBX_SR_ERRFE_SHIFT (11U) -#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) -#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) - -/* - * EWTFF (W1C) - * - * bus Error for write when tx fifo full, this bit is W1C bit. - * 1, write to a fulled tx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTFF_MASK (0x400U) -#define MBX_SR_EWTFF_SHIFT (10U) -#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) -#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) - -/* - * EAIVA (W1C) - * - * bus Error for Accessing Invalid Address; this bit is W1C bit. - * 1, read and write to invalid address in the bus of this block, will set this bit. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EAIVA_MASK (0x200U) -#define MBX_SR_EAIVA_SHIFT (9U) -#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) -#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) - -/* - * EW2RO (W1C) - * - * bus Error for Write to Read Only address; this bit is W1C bit. - * 1, write to read only address happened in the bus of this block. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EW2RO_MASK (0x100U) -#define MBX_SR_EW2RO_SHIFT (8U) -#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) -#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) - -/* - * TFMA (RW) - * - * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. - * 1, TXFIFO message buffer has slot available - * 0, no slot available (fifo full) - */ -#define MBX_SR_TFMA_MASK (0x80U) -#define MBX_SR_TFMA_SHIFT (7U) -#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) -#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) - -/* - * TFME (RW) - * - * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. - * 1, no any message data in TXFIFO from other core. - * 0, there are some data in the 4x32 TX FIFO from other core yet. - */ -#define MBX_SR_TFME_MASK (0x40U) -#define MBX_SR_TFME_SHIFT (6U) -#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) -#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) - -/* - * RFMA (RO) - * - * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, no any data in the 4x32 TXFIFO message buffer. - * 0, there are some data in the the 4x32 TXFIFO message buffer already. - */ -#define MBX_SR_RFMA_MASK (0x20U) -#define MBX_SR_RFMA_SHIFT (5U) -#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) - -/* - * RFMF (RO) - * - * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written 4x32 message in the RXFIFO. - * 0, no 4x32 RX FIFO message from other core yet. - */ -#define MBX_SR_RFMF_MASK (0x10U) -#define MBX_SR_RFMF_SHIFT (4U) -#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) - -/* - * TWME (RO) - * - * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, means this core had write word message to TXREG. - * 0, means no valid word message in the TXREG yet. - */ -#define MBX_SR_TWME_MASK (0x2U) -#define MBX_SR_TWME_SHIFT (1U) -#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) - -/* - * RWMV (RO) - * - * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written word message in the RXREG. - * 0, no valid word message yet in the RXREG. - */ -#define MBX_SR_RWMV_MASK (0x1U) -#define MBX_SR_RWMV_SHIFT (0U) -#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) - -/* Bitfield definition for register: TXREG */ -/* - * TXREG (WO) - * - * Transmit word message to other core. - */ -#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) -#define MBX_TXREG_TXREG_SHIFT (0U) -#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) -#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) - -/* Bitfield definition for register: RXREG */ -/* - * RXREG (RO) - * - * Receive word message from other core. - */ -#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) -#define MBX_RXREG_RXREG_SHIFT (0U) -#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) - -/* Bitfield definition for register array: TXWRD */ -/* - * TXFIFO (WO) - * - * TXFIFO for sending message to other core, FIFO size, 4x32 - * can write one of the word address to push data to the FIFO; - * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - */ -#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_TXWRD_TXFIFO_SHIFT (0U) -#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) -#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) - -/* Bitfield definition for register array: RXWRD */ -/* - * RXFIFO (RO) - * - * RXFIFO for receiving message from other core, FIFO size, 4x32 - * can read one of the word address to pop data to the FIFO; - * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - */ -#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_RXWRD_RXFIFO_SHIFT (0U) -#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) - - - -/* TXWRD register group index macro definition */ -#define MBX_TXWRD_TXFIFO0 (0UL) - -/* RXWRD register group index macro definition */ -#define MBX_RXWRD_RXFIFO0 (0UL) - - -#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mcan_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mcan_regs.h deleted file mode 100644 index ad873392ba7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mcan_regs.h +++ /dev/null @@ -1,3605 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCAN_H -#define HPM_MCAN_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t ENDN; /* 0x4: endian register */ - __R uint8_t RESERVED1[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t DBTP; /* 0xC: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set */ - __RW uint32_t TEST; /* 0x10: test register */ - __RW uint32_t RWD; /* 0x14: ram watchdog */ - __RW uint32_t CCCR; /* 0x18: CC control register */ - __RW uint32_t NBTP; /* 0x1C: nominal bit timing and prescaler register */ - __RW uint32_t TSCC; /* 0x20: timestamp counter configuration */ - __R uint32_t TSCV; /* 0x24: timestamp counter value */ - __RW uint32_t TOCC; /* 0x28: timeout counter configuration */ - __R uint32_t TOCV; /* 0x2C: timeout counter value */ - __R uint8_t RESERVED2[16]; /* 0x30 - 0x3F: Reserved */ - __R uint32_t ECR; /* 0x40: error counter register */ - __R uint32_t PSR; /* 0x44: protocol status register */ - __RW uint32_t TDCR; /* 0x48: transmitter delay compensation */ - __R uint8_t RESERVED3[4]; /* 0x4C - 0x4F: Reserved */ - __RW uint32_t IR; /* 0x50: interrupt register */ - __RW uint32_t IE; /* 0x54: interrupt enable */ - __RW uint32_t ILS; /* 0x58: interrupt line select */ - __RW uint32_t ILE; /* 0x5C: interrupt line enable */ - __R uint8_t RESERVED4[32]; /* 0x60 - 0x7F: Reserved */ - __RW uint32_t GFC; /* 0x80: global filter configuration */ - __RW uint32_t SIDFC; /* 0x84: standard ID filter configuration */ - __RW uint32_t XIDFC; /* 0x88: extended ID filter configuration */ - __R uint8_t RESERVED5[4]; /* 0x8C - 0x8F: Reserved */ - __RW uint32_t XIDAM; /* 0x90: extended id and mask */ - __R uint32_t HPMS; /* 0x94: high priority message status */ - __RW uint32_t NDAT1; /* 0x98: new data1 */ - __RW uint32_t NDAT2; /* 0x9C: new data2 */ - __RW uint32_t RXF0C; /* 0xA0: rx fifo 0 configuration */ - __R uint32_t RXF0S; /* 0xA4: rx fifo 0 status */ - __RW uint32_t RXF0A; /* 0xA8: rx fifo0 acknowledge */ - __RW uint32_t RXBC; /* 0xAC: rx buffer configuration */ - __RW uint32_t RXF1C; /* 0xB0: rx fifo1 configuration */ - __R uint32_t RXF1S; /* 0xB4: rx fifo1 status */ - __RW uint32_t RXF1A; /* 0xB8: rx fifo 1 acknowledge */ - __RW uint32_t RXESC; /* 0xBC: rx buffer/fifo element size configuration */ - __RW uint32_t TXBC; /* 0xC0: tx buffer configuration */ - __R uint32_t TXFQS; /* 0xC4: tx fifo/queue status */ - __RW uint32_t TXESC; /* 0xC8: tx buffer element size configuration */ - __R uint32_t TXBRP; /* 0xCC: tx buffer request pending */ - __RW uint32_t TXBAR; /* 0xD0: tx buffer add request */ - __RW uint32_t TXBCR; /* 0xD4: tx buffer cancellation request */ - __R uint32_t TXBTO; /* 0xD8: tx buffer transmission occurred */ - __R uint32_t TXBCF; /* 0xDC: tx buffer cancellation finished */ - __RW uint32_t TXBTIE; /* 0xE0: tx buffer transmission interrupt enable */ - __RW uint32_t TXBCIE; /* 0xE4: tx buffer cancellation finished interrupt enable */ - __R uint8_t RESERVED6[8]; /* 0xE8 - 0xEF: Reserved */ - __RW uint32_t TXEFC; /* 0xF0: tx event fifo configuration */ - __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ - __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ - __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ - __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0 */ - __R uint32_t CREL; /* 0x240: core release register */ - __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ - __R uint32_t TSS1; /* 0x248: timestamp status1 */ - __R uint32_t TSS2; /* 0x24C: timestamp status2 */ - __R uint32_t ATB; /* 0x250: actual timebase */ - __R uint32_t ATBH; /* 0x254: actual timebase high */ - __R uint8_t RESERVED8[424]; /* 0x258 - 0x3FF: Reserved */ - __RW uint32_t GLB_CTL; /* 0x400: global control */ - __R uint32_t GLB_STATUS; /* 0x404: global status */ - __R uint8_t RESERVED9[7160]; /* 0x408 - 0x1FFF: Reserved */ - __RW uint32_t MESSAGE_BUFF[640]; /* 0x2000 - 0x29FC: message buff */ -} MCAN_Type; - - -/* Bitfield definition for register: ENDN */ -/* - * EVT (R) - * - * Endianness Test Value - * The endianness test value is 0x87654321. - */ -#define MCAN_ENDN_EVT_MASK (0xFFFFFFFFUL) -#define MCAN_ENDN_EVT_SHIFT (0U) -#define MCAN_ENDN_EVT_GET(x) (((uint32_t)(x) & MCAN_ENDN_EVT_MASK) >> MCAN_ENDN_EVT_SHIFT) - -/* Bitfield definition for register: DBTP */ -/* - * TDC (RW) - * - * transmitter delay compensation enable - * 0= Transmitter Delay Compensation disabled - * 1= Transmitter Delay Compensation enabled - */ -#define MCAN_DBTP_TDC_MASK (0x800000UL) -#define MCAN_DBTP_TDC_SHIFT (23U) -#define MCAN_DBTP_TDC_SET(x) (((uint32_t)(x) << MCAN_DBTP_TDC_SHIFT) & MCAN_DBTP_TDC_MASK) -#define MCAN_DBTP_TDC_GET(x) (((uint32_t)(x) & MCAN_DBTP_TDC_MASK) >> MCAN_DBTP_TDC_SHIFT) - -/* - * DBRP (RW) - * - * Data Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. - * When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DBRP_MASK (0x1F0000UL) -#define MCAN_DBTP_DBRP_SHIFT (16U) -#define MCAN_DBTP_DBRP_SET(x) (((uint32_t)(x) << MCAN_DBTP_DBRP_SHIFT) & MCAN_DBTP_DBRP_MASK) -#define MCAN_DBTP_DBRP_GET(x) (((uint32_t)(x) & MCAN_DBTP_DBRP_MASK) >> MCAN_DBTP_DBRP_SHIFT) - -/* - * DTSEG1 (RW) - * - * Data time segment before sample point - * Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG1_MASK (0x1F00U) -#define MCAN_DBTP_DTSEG1_SHIFT (8U) -#define MCAN_DBTP_DTSEG1_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG1_SHIFT) & MCAN_DBTP_DTSEG1_MASK) -#define MCAN_DBTP_DTSEG1_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG1_MASK) >> MCAN_DBTP_DTSEG1_SHIFT) - -/* - * DTSEG2 (RW) - * - * Data time segment after sample point - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG2_MASK (0xF0U) -#define MCAN_DBTP_DTSEG2_SHIFT (4U) -#define MCAN_DBTP_DTSEG2_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG2_SHIFT) & MCAN_DBTP_DTSEG2_MASK) -#define MCAN_DBTP_DTSEG2_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG2_MASK) >> MCAN_DBTP_DTSEG2_SHIFT) - -/* - * DSJW (RW) - * - * Data (Re)Synchronization Jump Width - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DSJW_MASK (0xFU) -#define MCAN_DBTP_DSJW_SHIFT (0U) -#define MCAN_DBTP_DSJW_SET(x) (((uint32_t)(x) << MCAN_DBTP_DSJW_SHIFT) & MCAN_DBTP_DSJW_MASK) -#define MCAN_DBTP_DSJW_GET(x) (((uint32_t)(x) & MCAN_DBTP_DSJW_MASK) >> MCAN_DBTP_DSJW_SHIFT) - -/* Bitfield definition for register: TEST */ -/* - * SVAL (R) - * - * Started Valid - * 0= Value of TXBNS not valid - * 1= Value of TXBNS valid - */ -#define MCAN_TEST_SVAL_MASK (0x200000UL) -#define MCAN_TEST_SVAL_SHIFT (21U) -#define MCAN_TEST_SVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_SVAL_MASK) >> MCAN_TEST_SVAL_SHIFT) - -/* - * TXBNS (R) - * - * Tx Buffer Number Started - * Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNS_MASK (0x1F0000UL) -#define MCAN_TEST_TXBNS_SHIFT (16U) -#define MCAN_TEST_TXBNS_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNS_MASK) >> MCAN_TEST_TXBNS_SHIFT) - -/* - * PVAL (R) - * - * Prepared Valid - * 0= Value of TXBNP not valid - * 1= Value of TXBNP valid - */ -#define MCAN_TEST_PVAL_MASK (0x2000U) -#define MCAN_TEST_PVAL_SHIFT (13U) -#define MCAN_TEST_PVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_PVAL_MASK) >> MCAN_TEST_PVAL_SHIFT) - -/* - * TXBNP (R) - * - * Tx Buffer Number Prepared - * Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNP_MASK (0x1F00U) -#define MCAN_TEST_TXBNP_SHIFT (8U) -#define MCAN_TEST_TXBNP_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNP_MASK) >> MCAN_TEST_TXBNP_SHIFT) - -/* - * RX (R) - * - * Receive Pin - * Monitors the actual value of pin m_can_rx - * 0= The CAN bus is dominant (m_can_rx = ‘0’) - * 1= The CAN bus is recessive (m_can_rx = ‘1’) - */ -#define MCAN_TEST_RX_MASK (0x80U) -#define MCAN_TEST_RX_SHIFT (7U) -#define MCAN_TEST_RX_GET(x) (((uint32_t)(x) & MCAN_TEST_RX_MASK) >> MCAN_TEST_RX_SHIFT) - -/* - * TX (RW) - * - * Control of Transmit Pin - * 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time - * 01 Sample Point can be monitored at pin m_can_tx - * 10 Dominant (‘0’) level at pin m_can_tx - * 11 Recessive (‘1’) at pin m_can_tx - */ -#define MCAN_TEST_TX_MASK (0x60U) -#define MCAN_TEST_TX_SHIFT (5U) -#define MCAN_TEST_TX_SET(x) (((uint32_t)(x) << MCAN_TEST_TX_SHIFT) & MCAN_TEST_TX_MASK) -#define MCAN_TEST_TX_GET(x) (((uint32_t)(x) & MCAN_TEST_TX_MASK) >> MCAN_TEST_TX_SHIFT) - -/* - * LBCK (RW) - * - * Loop Back Mode - * 0= Reset value, Loop Back Mode is disabled - * 1= Loop Back Mode is enabled - */ -#define MCAN_TEST_LBCK_MASK (0x10U) -#define MCAN_TEST_LBCK_SHIFT (4U) -#define MCAN_TEST_LBCK_SET(x) (((uint32_t)(x) << MCAN_TEST_LBCK_SHIFT) & MCAN_TEST_LBCK_MASK) -#define MCAN_TEST_LBCK_GET(x) (((uint32_t)(x) & MCAN_TEST_LBCK_MASK) >> MCAN_TEST_LBCK_SHIFT) - -/* Bitfield definition for register: RWD */ -/* - * WDV (R) - * - * Watchdog Value - * Actual Message RAM Watchdog Counter Value. - */ -#define MCAN_RWD_WDV_MASK (0xFF00U) -#define MCAN_RWD_WDV_SHIFT (8U) -#define MCAN_RWD_WDV_GET(x) (((uint32_t)(x) & MCAN_RWD_WDV_MASK) >> MCAN_RWD_WDV_SHIFT) - -/* - * WDC (RW) - * - * Watchdog Configuration - * Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - */ -#define MCAN_RWD_WDC_MASK (0xFFU) -#define MCAN_RWD_WDC_SHIFT (0U) -#define MCAN_RWD_WDC_SET(x) (((uint32_t)(x) << MCAN_RWD_WDC_SHIFT) & MCAN_RWD_WDC_MASK) -#define MCAN_RWD_WDC_GET(x) (((uint32_t)(x) & MCAN_RWD_WDC_MASK) >> MCAN_RWD_WDC_SHIFT) - -/* Bitfield definition for register: CCCR */ -/* - * NISO (RW) - * - * Non ISO Operation - * If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD - * Specification V1.0. - * 0= CAN FD frame format according to ISO 11898-1:2015 - * 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 - * Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - */ -#define MCAN_CCCR_NISO_MASK (0x8000U) -#define MCAN_CCCR_NISO_SHIFT (15U) -#define MCAN_CCCR_NISO_SET(x) (((uint32_t)(x) << MCAN_CCCR_NISO_SHIFT) & MCAN_CCCR_NISO_MASK) -#define MCAN_CCCR_NISO_GET(x) (((uint32_t)(x) & MCAN_CCCR_NISO_MASK) >> MCAN_CCCR_NISO_SHIFT) - -/* - * TXP (RW) - * - * Transmit Pause - * If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after - * itself has successfully transmitted a frame (see Section 3.5). - * 0= Transmit pause disabled - * 1= Transmit pause enabled - */ -#define MCAN_CCCR_TXP_MASK (0x4000U) -#define MCAN_CCCR_TXP_SHIFT (14U) -#define MCAN_CCCR_TXP_SET(x) (((uint32_t)(x) << MCAN_CCCR_TXP_SHIFT) & MCAN_CCCR_TXP_MASK) -#define MCAN_CCCR_TXP_GET(x) (((uint32_t)(x) & MCAN_CCCR_TXP_MASK) >> MCAN_CCCR_TXP_SHIFT) - -/* - * EFBI (RW) - * - * Edge Filtering during Bus Integration - * 0= Edge filtering disabled - * 1= Two consecutive dominant tq required to detect an edge for hard synchronization - */ -#define MCAN_CCCR_EFBI_MASK (0x2000U) -#define MCAN_CCCR_EFBI_SHIFT (13U) -#define MCAN_CCCR_EFBI_SET(x) (((uint32_t)(x) << MCAN_CCCR_EFBI_SHIFT) & MCAN_CCCR_EFBI_MASK) -#define MCAN_CCCR_EFBI_GET(x) (((uint32_t)(x) & MCAN_CCCR_EFBI_MASK) >> MCAN_CCCR_EFBI_SHIFT) - -/* - * PXHD (RW) - * - * Protocol Exception Handling Disable - * 0= Protocol exception handling enabled - * 1= Protocol exception handling disabled - * Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - */ -#define MCAN_CCCR_PXHD_MASK (0x1000U) -#define MCAN_CCCR_PXHD_SHIFT (12U) -#define MCAN_CCCR_PXHD_SET(x) (((uint32_t)(x) << MCAN_CCCR_PXHD_SHIFT) & MCAN_CCCR_PXHD_MASK) -#define MCAN_CCCR_PXHD_GET(x) (((uint32_t)(x) & MCAN_CCCR_PXHD_MASK) >> MCAN_CCCR_PXHD_SHIFT) - -/* - * WMM (RW) - * - * Wide Message Marker - * Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. - * 0= 8-bit Message Marker used - * 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - */ -#define MCAN_CCCR_WMM_MASK (0x800U) -#define MCAN_CCCR_WMM_SHIFT (11U) -#define MCAN_CCCR_WMM_SET(x) (((uint32_t)(x) << MCAN_CCCR_WMM_SHIFT) & MCAN_CCCR_WMM_MASK) -#define MCAN_CCCR_WMM_GET(x) (((uint32_t)(x) & MCAN_CCCR_WMM_MASK) >> MCAN_CCCR_WMM_SHIFT) - -/* - * UTSU (RW) - * - * Use Timestamping Unit - * When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. - * 0= Internal time stamping - * 1= External time stamping by TSU - * Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. - * In this case bit UTSU is fixed to zero by synthesis. - */ -#define MCAN_CCCR_UTSU_MASK (0x400U) -#define MCAN_CCCR_UTSU_SHIFT (10U) -#define MCAN_CCCR_UTSU_SET(x) (((uint32_t)(x) << MCAN_CCCR_UTSU_SHIFT) & MCAN_CCCR_UTSU_MASK) -#define MCAN_CCCR_UTSU_GET(x) (((uint32_t)(x) & MCAN_CCCR_UTSU_MASK) >> MCAN_CCCR_UTSU_SHIFT) - -/* - * BRSE (RW) - * - * Bit Rate Switch Enable - * 0= Bit rate switching for transmissions disabled - * 1= Bit rate switching for transmissions enabled - * Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - */ -#define MCAN_CCCR_BRSE_MASK (0x200U) -#define MCAN_CCCR_BRSE_SHIFT (9U) -#define MCAN_CCCR_BRSE_SET(x) (((uint32_t)(x) << MCAN_CCCR_BRSE_SHIFT) & MCAN_CCCR_BRSE_MASK) -#define MCAN_CCCR_BRSE_GET(x) (((uint32_t)(x) & MCAN_CCCR_BRSE_MASK) >> MCAN_CCCR_BRSE_SHIFT) - -/* - * FDOE (RW) - * - * FD Operation Enable - * 0= FD operation disabled - * 1= FD operation enabled - */ -#define MCAN_CCCR_FDOE_MASK (0x100U) -#define MCAN_CCCR_FDOE_SHIFT (8U) -#define MCAN_CCCR_FDOE_SET(x) (((uint32_t)(x) << MCAN_CCCR_FDOE_SHIFT) & MCAN_CCCR_FDOE_MASK) -#define MCAN_CCCR_FDOE_GET(x) (((uint32_t)(x) & MCAN_CCCR_FDOE_MASK) >> MCAN_CCCR_FDOE_SHIFT) - -/* - * TEST (RW) - * - * Test Mode Enable - * 0= Normal operation, register TEST holds reset values - * 1= Test Mode, write access to register TEST enabled - */ -#define MCAN_CCCR_TEST_MASK (0x80U) -#define MCAN_CCCR_TEST_SHIFT (7U) -#define MCAN_CCCR_TEST_SET(x) (((uint32_t)(x) << MCAN_CCCR_TEST_SHIFT) & MCAN_CCCR_TEST_MASK) -#define MCAN_CCCR_TEST_GET(x) (((uint32_t)(x) & MCAN_CCCR_TEST_MASK) >> MCAN_CCCR_TEST_SHIFT) - -/* - * DAR (RW) - * - * Disable Automatic Retransmission - * 0= Automatic retransmission of messages not transmitted successfully enabled - * 1= Automatic retransmission disabled - */ -#define MCAN_CCCR_DAR_MASK (0x40U) -#define MCAN_CCCR_DAR_SHIFT (6U) -#define MCAN_CCCR_DAR_SET(x) (((uint32_t)(x) << MCAN_CCCR_DAR_SHIFT) & MCAN_CCCR_DAR_MASK) -#define MCAN_CCCR_DAR_GET(x) (((uint32_t)(x) & MCAN_CCCR_DAR_MASK) >> MCAN_CCCR_DAR_SHIFT) - -/* - * MON (RW) - * - * Bus Monitoring Mode - * Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. - * 0= Bus Monitoring Mode is disabled - * 1= Bus Monitoring Mode is enabled - */ -#define MCAN_CCCR_MON_MASK (0x20U) -#define MCAN_CCCR_MON_SHIFT (5U) -#define MCAN_CCCR_MON_SET(x) (((uint32_t)(x) << MCAN_CCCR_MON_SHIFT) & MCAN_CCCR_MON_MASK) -#define MCAN_CCCR_MON_GET(x) (((uint32_t)(x) & MCAN_CCCR_MON_MASK) >> MCAN_CCCR_MON_SHIFT) - -/* - * CSR (RW) - * - * Clock Stop Request - * 0= No clock stop is requested - * 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - */ -#define MCAN_CCCR_CSR_MASK (0x10U) -#define MCAN_CCCR_CSR_SHIFT (4U) -#define MCAN_CCCR_CSR_SET(x) (((uint32_t)(x) << MCAN_CCCR_CSR_SHIFT) & MCAN_CCCR_CSR_MASK) -#define MCAN_CCCR_CSR_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSR_MASK) >> MCAN_CCCR_CSR_SHIFT) - -/* - * CSA (R) - * - * Clock Stop Acknowledge - * 0= No clock stop acknowledged - * 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - */ -#define MCAN_CCCR_CSA_MASK (0x8U) -#define MCAN_CCCR_CSA_SHIFT (3U) -#define MCAN_CCCR_CSA_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSA_MASK) >> MCAN_CCCR_CSA_SHIFT) - -/* - * ASM (RW) - * - * Restricted Operation Mode - * Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. - * 0= Normal CAN operation - * 1= Restricted Operation Mode active - */ -#define MCAN_CCCR_ASM_MASK (0x4U) -#define MCAN_CCCR_ASM_SHIFT (2U) -#define MCAN_CCCR_ASM_SET(x) (((uint32_t)(x) << MCAN_CCCR_ASM_SHIFT) & MCAN_CCCR_ASM_MASK) -#define MCAN_CCCR_ASM_GET(x) (((uint32_t)(x) & MCAN_CCCR_ASM_MASK) >> MCAN_CCCR_ASM_SHIFT) - -/* - * CCE (RW) - * - * Configuration Change Enable - * 0= The CPU has no write access to the protected configuration registers - * 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - */ -#define MCAN_CCCR_CCE_MASK (0x2U) -#define MCAN_CCCR_CCE_SHIFT (1U) -#define MCAN_CCCR_CCE_SET(x) (((uint32_t)(x) << MCAN_CCCR_CCE_SHIFT) & MCAN_CCCR_CCE_MASK) -#define MCAN_CCCR_CCE_GET(x) (((uint32_t)(x) & MCAN_CCCR_CCE_MASK) >> MCAN_CCCR_CCE_SHIFT) - -/* - * INIT (RW) - * - * Initialization - * 0= Normal Operation - * 1= Initialization is started - */ -#define MCAN_CCCR_INIT_MASK (0x1U) -#define MCAN_CCCR_INIT_SHIFT (0U) -#define MCAN_CCCR_INIT_SET(x) (((uint32_t)(x) << MCAN_CCCR_INIT_SHIFT) & MCAN_CCCR_INIT_MASK) -#define MCAN_CCCR_INIT_GET(x) (((uint32_t)(x) & MCAN_CCCR_INIT_MASK) >> MCAN_CCCR_INIT_SHIFT) - -/* Bitfield definition for register: NBTP */ -/* - * NSJW (RW) - * - * Nominal (Re)Synchronization Jump Width - * Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NSJW_MASK (0xFE000000UL) -#define MCAN_NBTP_NSJW_SHIFT (25U) -#define MCAN_NBTP_NSJW_SET(x) (((uint32_t)(x) << MCAN_NBTP_NSJW_SHIFT) & MCAN_NBTP_NSJW_MASK) -#define MCAN_NBTP_NSJW_GET(x) (((uint32_t)(x) & MCAN_NBTP_NSJW_MASK) >> MCAN_NBTP_NSJW_SHIFT) - -/* - * NBRP (RW) - * - * Nominal Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is - * such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NBRP_MASK (0x1FF0000UL) -#define MCAN_NBTP_NBRP_SHIFT (16U) -#define MCAN_NBTP_NBRP_SET(x) (((uint32_t)(x) << MCAN_NBTP_NBRP_SHIFT) & MCAN_NBTP_NBRP_MASK) -#define MCAN_NBTP_NBRP_GET(x) (((uint32_t)(x) & MCAN_NBTP_NBRP_MASK) >> MCAN_NBTP_NBRP_SHIFT) - -/* - * NTSEG1 (RW) - * - * Nominal Time segment before sample point - * Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG1_MASK (0xFF00U) -#define MCAN_NBTP_NTSEG1_SHIFT (8U) -#define MCAN_NBTP_NTSEG1_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG1_SHIFT) & MCAN_NBTP_NTSEG1_MASK) -#define MCAN_NBTP_NTSEG1_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG1_MASK) >> MCAN_NBTP_NTSEG1_SHIFT) - -/* - * NTSEG2 (RW) - * - * Nominal Time segment after sample point - * Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG2_MASK (0x7FU) -#define MCAN_NBTP_NTSEG2_SHIFT (0U) -#define MCAN_NBTP_NTSEG2_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG2_SHIFT) & MCAN_NBTP_NTSEG2_MASK) -#define MCAN_NBTP_NTSEG2_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG2_MASK) >> MCAN_NBTP_NTSEG2_SHIFT) - -/* Bitfield definition for register: TSCC */ -/* - * TCP (RW) - * - * Timestamp Counter Prescaler - * Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_TSCC_TCP_MASK (0xF0000UL) -#define MCAN_TSCC_TCP_SHIFT (16U) -#define MCAN_TSCC_TCP_SET(x) (((uint32_t)(x) << MCAN_TSCC_TCP_SHIFT) & MCAN_TSCC_TCP_MASK) -#define MCAN_TSCC_TCP_GET(x) (((uint32_t)(x) & MCAN_TSCC_TCP_MASK) >> MCAN_TSCC_TCP_SHIFT) - -/* - * TSS (RW) - * - * timestamp Select - * 00= Timestamp counter value always 0x0000 - * 01= Timestamp counter value incremented according to TCP - * 10= External timestamp counter value used - * 11= Same as “00” - */ -#define MCAN_TSCC_TSS_MASK (0x3U) -#define MCAN_TSCC_TSS_SHIFT (0U) -#define MCAN_TSCC_TSS_SET(x) (((uint32_t)(x) << MCAN_TSCC_TSS_SHIFT) & MCAN_TSCC_TSS_MASK) -#define MCAN_TSCC_TSS_GET(x) (((uint32_t)(x) & MCAN_TSCC_TSS_MASK) >> MCAN_TSCC_TSS_SHIFT) - -/* Bitfield definition for register: TSCV */ -/* - * TSC (RC) - * - * Timestamp Counter - * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - */ -#define MCAN_TSCV_TSC_MASK (0xFFFFU) -#define MCAN_TSCV_TSC_SHIFT (0U) -#define MCAN_TSCV_TSC_GET(x) (((uint32_t)(x) & MCAN_TSCV_TSC_MASK) >> MCAN_TSCV_TSC_SHIFT) - -/* Bitfield definition for register: TOCC */ -/* - * TOP (RW) - * - * Timeout Period - * Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - */ -#define MCAN_TOCC_TOP_MASK (0xFFFF0000UL) -#define MCAN_TOCC_TOP_SHIFT (16U) -#define MCAN_TOCC_TOP_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOP_SHIFT) & MCAN_TOCC_TOP_MASK) -#define MCAN_TOCC_TOP_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOP_MASK) >> MCAN_TOCC_TOP_SHIFT) - -/* - * TOS (RW) - * - * Timeout Select - * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. - * When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. - * 00= Continuous operation - * 01= Timeout controlled by Tx Event FIFO - * 10= Timeout controlled by Rx FIFO 0 - * 11= Timeout controlled by Rx FIFO 1 - */ -#define MCAN_TOCC_TOS_MASK (0x6U) -#define MCAN_TOCC_TOS_SHIFT (1U) -#define MCAN_TOCC_TOS_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOS_SHIFT) & MCAN_TOCC_TOS_MASK) -#define MCAN_TOCC_TOS_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOS_MASK) >> MCAN_TOCC_TOS_SHIFT) - -/* - * RP (RW) - * - * Enable Timeout Counter - * 0= Timeout Counter disabled - * 1= Timeout Counter enabled - */ -#define MCAN_TOCC_RP_MASK (0x1U) -#define MCAN_TOCC_RP_SHIFT (0U) -#define MCAN_TOCC_RP_SET(x) (((uint32_t)(x) << MCAN_TOCC_RP_SHIFT) & MCAN_TOCC_RP_MASK) -#define MCAN_TOCC_RP_GET(x) (((uint32_t)(x) & MCAN_TOCC_RP_MASK) >> MCAN_TOCC_RP_SHIFT) - -/* Bitfield definition for register: TOCV */ -/* - * TOC (RC) - * - * Timeout Counter - * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. - * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - */ -#define MCAN_TOCV_TOC_MASK (0xFFFFU) -#define MCAN_TOCV_TOC_SHIFT (0U) -#define MCAN_TOCV_TOC_GET(x) (((uint32_t)(x) & MCAN_TOCV_TOC_MASK) >> MCAN_TOCV_TOC_SHIFT) - -/* Bitfield definition for register: ECR */ -/* - * CEL (X) - * - * CAN Error Logging - * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. - * The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. - * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. - * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - */ -#define MCAN_ECR_CEL_MASK (0xFF0000UL) -#define MCAN_ECR_CEL_SHIFT (16U) -#define MCAN_ECR_CEL_GET(x) (((uint32_t)(x) & MCAN_ECR_CEL_MASK) >> MCAN_ECR_CEL_SHIFT) - -/* - * RP (R) - * - * Receive Error Passive - * 0= The Receive Error Counter is below the error passive level of 128 - * 1= The Receive Error Counter has reached the error passive level of 128 - */ -#define MCAN_ECR_RP_MASK (0x8000U) -#define MCAN_ECR_RP_SHIFT (15U) -#define MCAN_ECR_RP_GET(x) (((uint32_t)(x) & MCAN_ECR_RP_MASK) >> MCAN_ECR_RP_SHIFT) - -/* - * REC (R) - * - * Receive Error Counter - * Actual state of the Receive Error Counter, values between 0 and 127 - */ -#define MCAN_ECR_REC_MASK (0x7F00U) -#define MCAN_ECR_REC_SHIFT (8U) -#define MCAN_ECR_REC_GET(x) (((uint32_t)(x) & MCAN_ECR_REC_MASK) >> MCAN_ECR_REC_SHIFT) - -/* - * TEC (R) - * - * Transmit Error Counter - * Actual state of the Transmit Error Counter, values between 0 and 255 - * Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - */ -#define MCAN_ECR_TEC_MASK (0xFFU) -#define MCAN_ECR_TEC_SHIFT (0U) -#define MCAN_ECR_TEC_GET(x) (((uint32_t)(x) & MCAN_ECR_TEC_MASK) >> MCAN_ECR_TEC_SHIFT) - -/* Bitfield definition for register: PSR */ -/* - * TDCV (R) - * - * Transmitter Delay Compensation Value - * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. - * The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_PSR_TDCV_MASK (0x7F0000UL) -#define MCAN_PSR_TDCV_SHIFT (16U) -#define MCAN_PSR_TDCV_GET(x) (((uint32_t)(x) & MCAN_PSR_TDCV_MASK) >> MCAN_PSR_TDCV_SHIFT) - -/* - * PXE (X) - * - * Protocol Exception Event - * 0= No protocol exception event occurred since last read access - * 1= Protocol exception event occurred - * Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_PXE_MASK (0x4000U) -#define MCAN_PSR_PXE_SHIFT (14U) -#define MCAN_PSR_PXE_GET(x) (((uint32_t)(x) & MCAN_PSR_PXE_MASK) >> MCAN_PSR_PXE_SHIFT) - -/* - * RFDF (X) - * - * Received a CAN FD Message - * This bit is set independent of acceptance filtering. - * 0= Since this bit was reset by the CPU, no CAN FD message has been received - * 1= Message in CAN FD format with FDF flag set has been received - * Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RFDF_MASK (0x2000U) -#define MCAN_PSR_RFDF_SHIFT (13U) -#define MCAN_PSR_RFDF_GET(x) (((uint32_t)(x) & MCAN_PSR_RFDF_MASK) >> MCAN_PSR_RFDF_SHIFT) - -/* - * RBRS (X) - * - * BRS flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its BRS flag set - * 1= Last received CAN FD message had its BRS flag set - * Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RBRS_MASK (0x1000U) -#define MCAN_PSR_RBRS_SHIFT (12U) -#define MCAN_PSR_RBRS_GET(x) (((uint32_t)(x) & MCAN_PSR_RBRS_MASK) >> MCAN_PSR_RBRS_SHIFT) - -/* - * RESI (X) - * - * ESI flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its ESI flag set - * 1= Last received CAN FD message had its ESI flag set - * Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RESI_MASK (0x800U) -#define MCAN_PSR_RESI_SHIFT (11U) -#define MCAN_PSR_RESI_GET(x) (((uint32_t)(x) & MCAN_PSR_RESI_MASK) >> MCAN_PSR_RESI_SHIFT) - -/* - * DLEC (S) - * - * Data Phase Last Error Code - * Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with - * its BRS flag set has been transferred (reception or transmission) without error. - * Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_DLEC_MASK (0x700U) -#define MCAN_PSR_DLEC_SHIFT (8U) -#define MCAN_PSR_DLEC_GET(x) (((uint32_t)(x) & MCAN_PSR_DLEC_MASK) >> MCAN_PSR_DLEC_SHIFT) - -/* - * BO (R) - * - * Bus_Off Status - * 0= The M_CAN is not Bus_Off - * 1= The M_CAN is in Bus_Off state - */ -#define MCAN_PSR_BO_MASK (0x80U) -#define MCAN_PSR_BO_SHIFT (7U) -#define MCAN_PSR_BO_GET(x) (((uint32_t)(x) & MCAN_PSR_BO_MASK) >> MCAN_PSR_BO_SHIFT) - -/* - * EW (R) - * - * Warning Status - * 0= Both error counters are below the Error_Warning limit of 96 - * 1= At least one of error counter has reached the Error_Warning limit of 96 - */ -#define MCAN_PSR_EW_MASK (0x40U) -#define MCAN_PSR_EW_SHIFT (6U) -#define MCAN_PSR_EW_GET(x) (((uint32_t)(x) & MCAN_PSR_EW_MASK) >> MCAN_PSR_EW_SHIFT) - -/* - * EP (R) - * - * Error Passive - * 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected - * 1= The M_CAN is in the Error_Passive state - */ -#define MCAN_PSR_EP_MASK (0x20U) -#define MCAN_PSR_EP_SHIFT (5U) -#define MCAN_PSR_EP_GET(x) (((uint32_t)(x) & MCAN_PSR_EP_MASK) >> MCAN_PSR_EP_SHIFT) - -/* - * ACT (R) - * - * Activity - * Monitors the module’s CAN communication state. - * 00= Synchronizing - node is synchronizing on CAN communication - * 01= Idle - node is neither receiver nor transmitter - * 10= Receiver - node is operating as receiver - * 11= Transmitter - node is operating as transmitter - * Note: ACT is set to “00” by a Protocol Exception Event. - */ -#define MCAN_PSR_ACT_MASK (0x18U) -#define MCAN_PSR_ACT_SHIFT (3U) -#define MCAN_PSR_ACT_GET(x) (((uint32_t)(x) & MCAN_PSR_ACT_MASK) >> MCAN_PSR_ACT_SHIFT) - -/* - * LEC (S) - * - * Last Error Code - * The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. - * 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. - * 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. - * 2= Form Error: A fixed format part of a received frame has the wrong format. - * 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. - * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), - * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus - * value was dominant. - * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - * During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at - * dominant or continuously disturbed). - * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. - * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. - * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. - * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - * Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. - * At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, - * enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. - * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_LEC_MASK (0x7U) -#define MCAN_PSR_LEC_SHIFT (0U) -#define MCAN_PSR_LEC_GET(x) (((uint32_t)(x) & MCAN_PSR_LEC_MASK) >> MCAN_PSR_LEC_SHIFT) - -/* Bitfield definition for register: TDCR */ -/* - * TDCO (RW) - * - * Transmitter Delay Compensation SSP Offset - * Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCO_MASK (0x7F00U) -#define MCAN_TDCR_TDCO_SHIFT (8U) -#define MCAN_TDCR_TDCO_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCO_SHIFT) & MCAN_TDCR_TDCO_MASK) -#define MCAN_TDCR_TDCO_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCO_MASK) >> MCAN_TDCR_TDCO_SHIFT) - -/* - * TDCF (RW) - * - * Transmitter Delay Compensation Filter Window Length - * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. - * The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCF_MASK (0x7FU) -#define MCAN_TDCR_TDCF_SHIFT (0U) -#define MCAN_TDCR_TDCF_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCF_SHIFT) & MCAN_TDCR_TDCF_MASK) -#define MCAN_TDCR_TDCF_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCF_MASK) >> MCAN_TDCR_TDCF_SHIFT) - -/* Bitfield definition for register: IR */ -/* - * ARA (RW) - * - * Access to Reserved Address - * 0= No access to reserved address occurred - * 1= Access to reserved address occurred - */ -#define MCAN_IR_ARA_MASK (0x20000000UL) -#define MCAN_IR_ARA_SHIFT (29U) -#define MCAN_IR_ARA_SET(x) (((uint32_t)(x) << MCAN_IR_ARA_SHIFT) & MCAN_IR_ARA_MASK) -#define MCAN_IR_ARA_GET(x) (((uint32_t)(x) & MCAN_IR_ARA_MASK) >> MCAN_IR_ARA_SHIFT) - -/* - * PED (RW) - * - * Protocol Error in Data Phase (Data Bit Time is used) - * 0= No protocol error in data phase - * 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - */ -#define MCAN_IR_PED_MASK (0x10000000UL) -#define MCAN_IR_PED_SHIFT (28U) -#define MCAN_IR_PED_SET(x) (((uint32_t)(x) << MCAN_IR_PED_SHIFT) & MCAN_IR_PED_MASK) -#define MCAN_IR_PED_GET(x) (((uint32_t)(x) & MCAN_IR_PED_MASK) >> MCAN_IR_PED_SHIFT) - -/* - * PEA (RW) - * - * Protocol Error in Arbitration Phase (Nominal Bit Time is used) - * 0= No protocol error in arbitration phase - * 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - */ -#define MCAN_IR_PEA_MASK (0x8000000UL) -#define MCAN_IR_PEA_SHIFT (27U) -#define MCAN_IR_PEA_SET(x) (((uint32_t)(x) << MCAN_IR_PEA_SHIFT) & MCAN_IR_PEA_MASK) -#define MCAN_IR_PEA_GET(x) (((uint32_t)(x) & MCAN_IR_PEA_MASK) >> MCAN_IR_PEA_SHIFT) - -/* - * WDI (RW) - * - * Watchdog Interrupt - * 0= No Message RAM Watchdog event occurred - * 1= Message RAM Watchdog event due to missing READY - */ -#define MCAN_IR_WDI_MASK (0x4000000UL) -#define MCAN_IR_WDI_SHIFT (26U) -#define MCAN_IR_WDI_SET(x) (((uint32_t)(x) << MCAN_IR_WDI_SHIFT) & MCAN_IR_WDI_MASK) -#define MCAN_IR_WDI_GET(x) (((uint32_t)(x) & MCAN_IR_WDI_MASK) >> MCAN_IR_WDI_SHIFT) - -/* - * BO (RW) - * - * Bus_Off Status - * 0= Bus_Off status unchanged - * 1= Bus_Off status changed - */ -#define MCAN_IR_BO_MASK (0x2000000UL) -#define MCAN_IR_BO_SHIFT (25U) -#define MCAN_IR_BO_SET(x) (((uint32_t)(x) << MCAN_IR_BO_SHIFT) & MCAN_IR_BO_MASK) -#define MCAN_IR_BO_GET(x) (((uint32_t)(x) & MCAN_IR_BO_MASK) >> MCAN_IR_BO_SHIFT) - -/* - * EW (RW) - * - * Warning Status - * 0= Error_Warning status unchanged - * 1= Error_Warning status changed - */ -#define MCAN_IR_EW_MASK (0x1000000UL) -#define MCAN_IR_EW_SHIFT (24U) -#define MCAN_IR_EW_SET(x) (((uint32_t)(x) << MCAN_IR_EW_SHIFT) & MCAN_IR_EW_MASK) -#define MCAN_IR_EW_GET(x) (((uint32_t)(x) & MCAN_IR_EW_MASK) >> MCAN_IR_EW_SHIFT) - -/* - * EP (RW) - * - * Error Passive - * 0= Error_Passive status unchanged - * 1= Error_Passive status changed - */ -#define MCAN_IR_EP_MASK (0x800000UL) -#define MCAN_IR_EP_SHIFT (23U) -#define MCAN_IR_EP_SET(x) (((uint32_t)(x) << MCAN_IR_EP_SHIFT) & MCAN_IR_EP_MASK) -#define MCAN_IR_EP_GET(x) (((uint32_t)(x) & MCAN_IR_EP_MASK) >> MCAN_IR_EP_SHIFT) - -/* - * ELO (RW) - * - * Error Logging Overflow - * 0= CAN Error Logging Counter did not overflow - * 1= Overflow of CAN Error Logging Counter occurred - */ -#define MCAN_IR_ELO_MASK (0x400000UL) -#define MCAN_IR_ELO_SHIFT (22U) -#define MCAN_IR_ELO_SET(x) (((uint32_t)(x) << MCAN_IR_ELO_SHIFT) & MCAN_IR_ELO_MASK) -#define MCAN_IR_ELO_GET(x) (((uint32_t)(x) & MCAN_IR_ELO_MASK) >> MCAN_IR_ELO_SHIFT) - -/* - * BEU (RW) - * - * Bit Error Uncorrected - * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. - * An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected, uncorrected (e.g. parity logic) - */ -#define MCAN_IR_BEU_MASK (0x200000UL) -#define MCAN_IR_BEU_SHIFT (21U) -#define MCAN_IR_BEU_SET(x) (((uint32_t)(x) << MCAN_IR_BEU_SHIFT) & MCAN_IR_BEU_MASK) -#define MCAN_IR_BEU_GET(x) (((uint32_t)(x) & MCAN_IR_BEU_MASK) >> MCAN_IR_BEU_SHIFT) - -/* - * BEC (RW) - * - * Bit Error Corrected - * Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected and corrected (e.g. ECC) - */ -#define MCAN_IR_BEC_MASK (0x100000UL) -#define MCAN_IR_BEC_SHIFT (20U) -#define MCAN_IR_BEC_SET(x) (((uint32_t)(x) << MCAN_IR_BEC_SHIFT) & MCAN_IR_BEC_MASK) -#define MCAN_IR_BEC_GET(x) (((uint32_t)(x) & MCAN_IR_BEC_MASK) >> MCAN_IR_BEC_SHIFT) - -/* - * DRX (RW) - * - * Message stored to Dedicated Rx Buffer - * The flag is set whenever a received message has been stored into a dedicated Rx Buffer. - * 0= No Rx Buffer updated - * 1= At least one received message stored into an Rx Buffer - */ -#define MCAN_IR_DRX_MASK (0x80000UL) -#define MCAN_IR_DRX_SHIFT (19U) -#define MCAN_IR_DRX_SET(x) (((uint32_t)(x) << MCAN_IR_DRX_SHIFT) & MCAN_IR_DRX_MASK) -#define MCAN_IR_DRX_GET(x) (((uint32_t)(x) & MCAN_IR_DRX_MASK) >> MCAN_IR_DRX_SHIFT) - -/* - * TOO (RW) - * - * Timeout Occurred - * 0= No timeout - * 1= Timeout reached - */ -#define MCAN_IR_TOO_MASK (0x40000UL) -#define MCAN_IR_TOO_SHIFT (18U) -#define MCAN_IR_TOO_SET(x) (((uint32_t)(x) << MCAN_IR_TOO_SHIFT) & MCAN_IR_TOO_MASK) -#define MCAN_IR_TOO_GET(x) (((uint32_t)(x) & MCAN_IR_TOO_MASK) >> MCAN_IR_TOO_SHIFT) - -/* - * MRAF (RW) - * - * Message RAM Access Failure - * The flag is set, when the Rx Handler - * .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message - * storage is aborted and the Rx Handler starts processing of the following message. - * .was not able to write a message to the Message RAM. In this case message storage is aborted. - * In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. - * The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the - * M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. - * 0= No Message RAM access failure occurred - * 1= Message RAM access failure occurred - */ -#define MCAN_IR_MRAF_MASK (0x20000UL) -#define MCAN_IR_MRAF_SHIFT (17U) -#define MCAN_IR_MRAF_SET(x) (((uint32_t)(x) << MCAN_IR_MRAF_SHIFT) & MCAN_IR_MRAF_MASK) -#define MCAN_IR_MRAF_GET(x) (((uint32_t)(x) & MCAN_IR_MRAF_MASK) >> MCAN_IR_MRAF_SHIFT) - -/* - * TSW (RW) - * - * Timestamp Wraparound - * 0= No timestamp counter wrap-around - * 1= Timestamp counter wrapped around - */ -#define MCAN_IR_TSW_MASK (0x10000UL) -#define MCAN_IR_TSW_SHIFT (16U) -#define MCAN_IR_TSW_SET(x) (((uint32_t)(x) << MCAN_IR_TSW_SHIFT) & MCAN_IR_TSW_MASK) -#define MCAN_IR_TSW_GET(x) (((uint32_t)(x) & MCAN_IR_TSW_MASK) >> MCAN_IR_TSW_SHIFT) - -/* - * TEFL (RW) - * - * Tx Event FIFO Element Lost - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - */ -#define MCAN_IR_TEFL_MASK (0x8000U) -#define MCAN_IR_TEFL_SHIFT (15U) -#define MCAN_IR_TEFL_SET(x) (((uint32_t)(x) << MCAN_IR_TEFL_SHIFT) & MCAN_IR_TEFL_MASK) -#define MCAN_IR_TEFL_GET(x) (((uint32_t)(x) & MCAN_IR_TEFL_MASK) >> MCAN_IR_TEFL_SHIFT) - -/* - * TEFF (RW) - * - * Tx Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_IR_TEFF_MASK (0x4000U) -#define MCAN_IR_TEFF_SHIFT (14U) -#define MCAN_IR_TEFF_SET(x) (((uint32_t)(x) << MCAN_IR_TEFF_SHIFT) & MCAN_IR_TEFF_MASK) -#define MCAN_IR_TEFF_GET(x) (((uint32_t)(x) & MCAN_IR_TEFF_MASK) >> MCAN_IR_TEFF_SHIFT) - -/* - * TEFW (RW) - * - * Tx Event FIFO Watermark Reached - * 0= Tx Event FIFO fill level below watermark - * 1= Tx Event FIFO fill level reached watermark - */ -#define MCAN_IR_TEFW_MASK (0x2000U) -#define MCAN_IR_TEFW_SHIFT (13U) -#define MCAN_IR_TEFW_SET(x) (((uint32_t)(x) << MCAN_IR_TEFW_SHIFT) & MCAN_IR_TEFW_MASK) -#define MCAN_IR_TEFW_GET(x) (((uint32_t)(x) & MCAN_IR_TEFW_MASK) >> MCAN_IR_TEFW_SHIFT) - -/* - * TEFN (RW) - * - * Tx Event FIFO New Entry - * 0= Tx Event FIFO unchanged - * 1= Tx Handler wrote Tx Event FIFO element - */ -#define MCAN_IR_TEFN_MASK (0x1000U) -#define MCAN_IR_TEFN_SHIFT (12U) -#define MCAN_IR_TEFN_SET(x) (((uint32_t)(x) << MCAN_IR_TEFN_SHIFT) & MCAN_IR_TEFN_MASK) -#define MCAN_IR_TEFN_GET(x) (((uint32_t)(x) & MCAN_IR_TEFN_MASK) >> MCAN_IR_TEFN_SHIFT) - -/* - * TFE (RW) - * - * Tx FIFO Empty - * 0= Tx FIFO non-empty - * 1= Tx FIFO empty - */ -#define MCAN_IR_TFE_MASK (0x800U) -#define MCAN_IR_TFE_SHIFT (11U) -#define MCAN_IR_TFE_SET(x) (((uint32_t)(x) << MCAN_IR_TFE_SHIFT) & MCAN_IR_TFE_MASK) -#define MCAN_IR_TFE_GET(x) (((uint32_t)(x) & MCAN_IR_TFE_MASK) >> MCAN_IR_TFE_SHIFT) - -/* - * TCF (RW) - * - * Transmission Cancellation Finished - * 0= No transmission cancellation finished - * 1= Transmission cancellation finished - */ -#define MCAN_IR_TCF_MASK (0x400U) -#define MCAN_IR_TCF_SHIFT (10U) -#define MCAN_IR_TCF_SET(x) (((uint32_t)(x) << MCAN_IR_TCF_SHIFT) & MCAN_IR_TCF_MASK) -#define MCAN_IR_TCF_GET(x) (((uint32_t)(x) & MCAN_IR_TCF_MASK) >> MCAN_IR_TCF_SHIFT) - -/* - * TC (RW) - * - * Transmission Completed - * 0= No transmission completed - * 1= Transmission completed - */ -#define MCAN_IR_TC_MASK (0x200U) -#define MCAN_IR_TC_SHIFT (9U) -#define MCAN_IR_TC_SET(x) (((uint32_t)(x) << MCAN_IR_TC_SHIFT) & MCAN_IR_TC_MASK) -#define MCAN_IR_TC_GET(x) (((uint32_t)(x) & MCAN_IR_TC_MASK) >> MCAN_IR_TC_SHIFT) - -/* - * HPM (RW) - * - * High Priority Message - * 0= No high priority message received - * 1= High priority message received - */ -#define MCAN_IR_HPM_MASK (0x100U) -#define MCAN_IR_HPM_SHIFT (8U) -#define MCAN_IR_HPM_SET(x) (((uint32_t)(x) << MCAN_IR_HPM_SHIFT) & MCAN_IR_HPM_MASK) -#define MCAN_IR_HPM_GET(x) (((uint32_t)(x) & MCAN_IR_HPM_MASK) >> MCAN_IR_HPM_SHIFT) - -/* - * RF1L (RW) - * - * Rx FIFO 1 Message Lost - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - */ -#define MCAN_IR_RF1L_MASK (0x80U) -#define MCAN_IR_RF1L_SHIFT (7U) -#define MCAN_IR_RF1L_SET(x) (((uint32_t)(x) << MCAN_IR_RF1L_SHIFT) & MCAN_IR_RF1L_MASK) -#define MCAN_IR_RF1L_GET(x) (((uint32_t)(x) & MCAN_IR_RF1L_MASK) >> MCAN_IR_RF1L_SHIFT) - -/* - * RF1F (RW) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_IR_RF1F_MASK (0x40U) -#define MCAN_IR_RF1F_SHIFT (6U) -#define MCAN_IR_RF1F_SET(x) (((uint32_t)(x) << MCAN_IR_RF1F_SHIFT) & MCAN_IR_RF1F_MASK) -#define MCAN_IR_RF1F_GET(x) (((uint32_t)(x) & MCAN_IR_RF1F_MASK) >> MCAN_IR_RF1F_SHIFT) - -/* - * RF1W (RW) - * - * Rx FIFO 1 Watermark Reached - * 0= Rx FIFO 1 fill level below watermark - * 1= Rx FIFO 1 fill level reached watermark - */ -#define MCAN_IR_RF1W_MASK (0x20U) -#define MCAN_IR_RF1W_SHIFT (5U) -#define MCAN_IR_RF1W_SET(x) (((uint32_t)(x) << MCAN_IR_RF1W_SHIFT) & MCAN_IR_RF1W_MASK) -#define MCAN_IR_RF1W_GET(x) (((uint32_t)(x) & MCAN_IR_RF1W_MASK) >> MCAN_IR_RF1W_SHIFT) - -/* - * RF1N (RW) - * - * Rx FIFO 1 New Message - * 0= No new message written to Rx FIFO 1 - * 1= New message written to Rx FIFO 1 - */ -#define MCAN_IR_RF1N_MASK (0x10U) -#define MCAN_IR_RF1N_SHIFT (4U) -#define MCAN_IR_RF1N_SET(x) (((uint32_t)(x) << MCAN_IR_RF1N_SHIFT) & MCAN_IR_RF1N_MASK) -#define MCAN_IR_RF1N_GET(x) (((uint32_t)(x) & MCAN_IR_RF1N_MASK) >> MCAN_IR_RF1N_SHIFT) - -/* - * RF0L (RW) - * - * Rx FIFO 0 Message Lost - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - */ -#define MCAN_IR_RF0L_MASK (0x8U) -#define MCAN_IR_RF0L_SHIFT (3U) -#define MCAN_IR_RF0L_SET(x) (((uint32_t)(x) << MCAN_IR_RF0L_SHIFT) & MCAN_IR_RF0L_MASK) -#define MCAN_IR_RF0L_GET(x) (((uint32_t)(x) & MCAN_IR_RF0L_MASK) >> MCAN_IR_RF0L_SHIFT) - -/* - * RF0F (RW) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_IR_RF0F_MASK (0x4U) -#define MCAN_IR_RF0F_SHIFT (2U) -#define MCAN_IR_RF0F_SET(x) (((uint32_t)(x) << MCAN_IR_RF0F_SHIFT) & MCAN_IR_RF0F_MASK) -#define MCAN_IR_RF0F_GET(x) (((uint32_t)(x) & MCAN_IR_RF0F_MASK) >> MCAN_IR_RF0F_SHIFT) - -/* - * RF0W (RW) - * - * Rx FIFO 0 Watermark Reached - * 0= Rx FIFO 0 fill level below watermark - * 1= Rx FIFO 0 fill level reached watermark - */ -#define MCAN_IR_RF0W_MASK (0x2U) -#define MCAN_IR_RF0W_SHIFT (1U) -#define MCAN_IR_RF0W_SET(x) (((uint32_t)(x) << MCAN_IR_RF0W_SHIFT) & MCAN_IR_RF0W_MASK) -#define MCAN_IR_RF0W_GET(x) (((uint32_t)(x) & MCAN_IR_RF0W_MASK) >> MCAN_IR_RF0W_SHIFT) - -/* - * RF0N (RW) - * - * Rx FIFO 0 New Message - * 0= No new message written to Rx FIFO 0 - * 1= New message written to Rx FIFO 0 - */ -#define MCAN_IR_RF0N_MASK (0x1U) -#define MCAN_IR_RF0N_SHIFT (0U) -#define MCAN_IR_RF0N_SET(x) (((uint32_t)(x) << MCAN_IR_RF0N_SHIFT) & MCAN_IR_RF0N_MASK) -#define MCAN_IR_RF0N_GET(x) (((uint32_t)(x) & MCAN_IR_RF0N_MASK) >> MCAN_IR_RF0N_SHIFT) - -/* Bitfield definition for register: IE */ -/* - * ARAE (RW) - * - * Access to Reserved Address Enable - */ -#define MCAN_IE_ARAE_MASK (0x20000000UL) -#define MCAN_IE_ARAE_SHIFT (29U) -#define MCAN_IE_ARAE_SET(x) (((uint32_t)(x) << MCAN_IE_ARAE_SHIFT) & MCAN_IE_ARAE_MASK) -#define MCAN_IE_ARAE_GET(x) (((uint32_t)(x) & MCAN_IE_ARAE_MASK) >> MCAN_IE_ARAE_SHIFT) - -/* - * PEDE (RW) - * - * Protocol Error in Data Phase Enable - */ -#define MCAN_IE_PEDE_MASK (0x10000000UL) -#define MCAN_IE_PEDE_SHIFT (28U) -#define MCAN_IE_PEDE_SET(x) (((uint32_t)(x) << MCAN_IE_PEDE_SHIFT) & MCAN_IE_PEDE_MASK) -#define MCAN_IE_PEDE_GET(x) (((uint32_t)(x) & MCAN_IE_PEDE_MASK) >> MCAN_IE_PEDE_SHIFT) - -/* - * PEAE (RW) - * - * Protocol Error in Arbitration Phase Enable - */ -#define MCAN_IE_PEAE_MASK (0x8000000UL) -#define MCAN_IE_PEAE_SHIFT (27U) -#define MCAN_IE_PEAE_SET(x) (((uint32_t)(x) << MCAN_IE_PEAE_SHIFT) & MCAN_IE_PEAE_MASK) -#define MCAN_IE_PEAE_GET(x) (((uint32_t)(x) & MCAN_IE_PEAE_MASK) >> MCAN_IE_PEAE_SHIFT) - -/* - * WDIE (RW) - * - * Watchdog Interrupt Enable - */ -#define MCAN_IE_WDIE_MASK (0x4000000UL) -#define MCAN_IE_WDIE_SHIFT (26U) -#define MCAN_IE_WDIE_SET(x) (((uint32_t)(x) << MCAN_IE_WDIE_SHIFT) & MCAN_IE_WDIE_MASK) -#define MCAN_IE_WDIE_GET(x) (((uint32_t)(x) & MCAN_IE_WDIE_MASK) >> MCAN_IE_WDIE_SHIFT) - -/* - * BOE (RW) - * - * Bus_Off Status Interrupt Enable - */ -#define MCAN_IE_BOE_MASK (0x2000000UL) -#define MCAN_IE_BOE_SHIFT (25U) -#define MCAN_IE_BOE_SET(x) (((uint32_t)(x) << MCAN_IE_BOE_SHIFT) & MCAN_IE_BOE_MASK) -#define MCAN_IE_BOE_GET(x) (((uint32_t)(x) & MCAN_IE_BOE_MASK) >> MCAN_IE_BOE_SHIFT) - -/* - * EWE (RW) - * - * Warning Status Interrupt Enable - */ -#define MCAN_IE_EWE_MASK (0x1000000UL) -#define MCAN_IE_EWE_SHIFT (24U) -#define MCAN_IE_EWE_SET(x) (((uint32_t)(x) << MCAN_IE_EWE_SHIFT) & MCAN_IE_EWE_MASK) -#define MCAN_IE_EWE_GET(x) (((uint32_t)(x) & MCAN_IE_EWE_MASK) >> MCAN_IE_EWE_SHIFT) - -/* - * EPE (RW) - * - * Error Passive Interrupt Enable - */ -#define MCAN_IE_EPE_MASK (0x800000UL) -#define MCAN_IE_EPE_SHIFT (23U) -#define MCAN_IE_EPE_SET(x) (((uint32_t)(x) << MCAN_IE_EPE_SHIFT) & MCAN_IE_EPE_MASK) -#define MCAN_IE_EPE_GET(x) (((uint32_t)(x) & MCAN_IE_EPE_MASK) >> MCAN_IE_EPE_SHIFT) - -/* - * ELOE (RW) - * - * Error Logging Overflow Interrupt Enable - */ -#define MCAN_IE_ELOE_MASK (0x400000UL) -#define MCAN_IE_ELOE_SHIFT (22U) -#define MCAN_IE_ELOE_SET(x) (((uint32_t)(x) << MCAN_IE_ELOE_SHIFT) & MCAN_IE_ELOE_MASK) -#define MCAN_IE_ELOE_GET(x) (((uint32_t)(x) & MCAN_IE_ELOE_MASK) >> MCAN_IE_ELOE_SHIFT) - -/* - * BEUE (RW) - * - * Bit Error Uncorrected Interrupt Enable - */ -#define MCAN_IE_BEUE_MASK (0x200000UL) -#define MCAN_IE_BEUE_SHIFT (21U) -#define MCAN_IE_BEUE_SET(x) (((uint32_t)(x) << MCAN_IE_BEUE_SHIFT) & MCAN_IE_BEUE_MASK) -#define MCAN_IE_BEUE_GET(x) (((uint32_t)(x) & MCAN_IE_BEUE_MASK) >> MCAN_IE_BEUE_SHIFT) - -/* - * BECE (RW) - * - * Bit Error Corrected Interrupt Enable - */ -#define MCAN_IE_BECE_MASK (0x100000UL) -#define MCAN_IE_BECE_SHIFT (20U) -#define MCAN_IE_BECE_SET(x) (((uint32_t)(x) << MCAN_IE_BECE_SHIFT) & MCAN_IE_BECE_MASK) -#define MCAN_IE_BECE_GET(x) (((uint32_t)(x) & MCAN_IE_BECE_MASK) >> MCAN_IE_BECE_SHIFT) - -/* - * DRXE (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Enable - */ -#define MCAN_IE_DRXE_MASK (0x80000UL) -#define MCAN_IE_DRXE_SHIFT (19U) -#define MCAN_IE_DRXE_SET(x) (((uint32_t)(x) << MCAN_IE_DRXE_SHIFT) & MCAN_IE_DRXE_MASK) -#define MCAN_IE_DRXE_GET(x) (((uint32_t)(x) & MCAN_IE_DRXE_MASK) >> MCAN_IE_DRXE_SHIFT) - -/* - * TOOE (RW) - * - * Timeout Occurred Interrupt Enable - */ -#define MCAN_IE_TOOE_MASK (0x40000UL) -#define MCAN_IE_TOOE_SHIFT (18U) -#define MCAN_IE_TOOE_SET(x) (((uint32_t)(x) << MCAN_IE_TOOE_SHIFT) & MCAN_IE_TOOE_MASK) -#define MCAN_IE_TOOE_GET(x) (((uint32_t)(x) & MCAN_IE_TOOE_MASK) >> MCAN_IE_TOOE_SHIFT) - -/* - * MRAFE (RW) - * - * Message RAM Access Failure Interrupt Enable - */ -#define MCAN_IE_MRAFE_MASK (0x20000UL) -#define MCAN_IE_MRAFE_SHIFT (17U) -#define MCAN_IE_MRAFE_SET(x) (((uint32_t)(x) << MCAN_IE_MRAFE_SHIFT) & MCAN_IE_MRAFE_MASK) -#define MCAN_IE_MRAFE_GET(x) (((uint32_t)(x) & MCAN_IE_MRAFE_MASK) >> MCAN_IE_MRAFE_SHIFT) - -/* - * TSWE (RW) - * - * Timestamp Wraparound Interrupt Enable - */ -#define MCAN_IE_TSWE_MASK (0x10000UL) -#define MCAN_IE_TSWE_SHIFT (16U) -#define MCAN_IE_TSWE_SET(x) (((uint32_t)(x) << MCAN_IE_TSWE_SHIFT) & MCAN_IE_TSWE_MASK) -#define MCAN_IE_TSWE_GET(x) (((uint32_t)(x) & MCAN_IE_TSWE_MASK) >> MCAN_IE_TSWE_SHIFT) - -/* - * TEFLE (RW) - * - * Tx Event FIFO Event Lost Interrupt Enable - */ -#define MCAN_IE_TEFLE_MASK (0x8000U) -#define MCAN_IE_TEFLE_SHIFT (15U) -#define MCAN_IE_TEFLE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFLE_SHIFT) & MCAN_IE_TEFLE_MASK) -#define MCAN_IE_TEFLE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFLE_MASK) >> MCAN_IE_TEFLE_SHIFT) - -/* - * TEFFE (RW) - * - * Tx Event FIFO Full Interrupt Enable - */ -#define MCAN_IE_TEFFE_MASK (0x4000U) -#define MCAN_IE_TEFFE_SHIFT (14U) -#define MCAN_IE_TEFFE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFFE_SHIFT) & MCAN_IE_TEFFE_MASK) -#define MCAN_IE_TEFFE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFFE_MASK) >> MCAN_IE_TEFFE_SHIFT) - -/* - * TEFWE (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Enable - */ -#define MCAN_IE_TEFWE_MASK (0x2000U) -#define MCAN_IE_TEFWE_SHIFT (13U) -#define MCAN_IE_TEFWE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFWE_SHIFT) & MCAN_IE_TEFWE_MASK) -#define MCAN_IE_TEFWE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFWE_MASK) >> MCAN_IE_TEFWE_SHIFT) - -/* - * TEFNE (RW) - * - * Tx Event FIFO New Entry Interrupt Enable - */ -#define MCAN_IE_TEFNE_MASK (0x1000U) -#define MCAN_IE_TEFNE_SHIFT (12U) -#define MCAN_IE_TEFNE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFNE_SHIFT) & MCAN_IE_TEFNE_MASK) -#define MCAN_IE_TEFNE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFNE_MASK) >> MCAN_IE_TEFNE_SHIFT) - -/* - * TFEE (RW) - * - * Tx FIFO Empty Interrupt Enable - */ -#define MCAN_IE_TFEE_MASK (0x800U) -#define MCAN_IE_TFEE_SHIFT (11U) -#define MCAN_IE_TFEE_SET(x) (((uint32_t)(x) << MCAN_IE_TFEE_SHIFT) & MCAN_IE_TFEE_MASK) -#define MCAN_IE_TFEE_GET(x) (((uint32_t)(x) & MCAN_IE_TFEE_MASK) >> MCAN_IE_TFEE_SHIFT) - -/* - * TCFE (RW) - * - * Transmission Cancellation Finished Interrupt Enable - */ -#define MCAN_IE_TCFE_MASK (0x400U) -#define MCAN_IE_TCFE_SHIFT (10U) -#define MCAN_IE_TCFE_SET(x) (((uint32_t)(x) << MCAN_IE_TCFE_SHIFT) & MCAN_IE_TCFE_MASK) -#define MCAN_IE_TCFE_GET(x) (((uint32_t)(x) & MCAN_IE_TCFE_MASK) >> MCAN_IE_TCFE_SHIFT) - -/* - * TCE (RW) - * - * Transmission Completed Interrupt Enable - */ -#define MCAN_IE_TCE_MASK (0x200U) -#define MCAN_IE_TCE_SHIFT (9U) -#define MCAN_IE_TCE_SET(x) (((uint32_t)(x) << MCAN_IE_TCE_SHIFT) & MCAN_IE_TCE_MASK) -#define MCAN_IE_TCE_GET(x) (((uint32_t)(x) & MCAN_IE_TCE_MASK) >> MCAN_IE_TCE_SHIFT) - -/* - * HPME (RW) - * - * High Priority Message Interrupt Enable - */ -#define MCAN_IE_HPME_MASK (0x100U) -#define MCAN_IE_HPME_SHIFT (8U) -#define MCAN_IE_HPME_SET(x) (((uint32_t)(x) << MCAN_IE_HPME_SHIFT) & MCAN_IE_HPME_MASK) -#define MCAN_IE_HPME_GET(x) (((uint32_t)(x) & MCAN_IE_HPME_MASK) >> MCAN_IE_HPME_SHIFT) - -/* - * RF1LE (RW) - * - * Rx FIFO 1 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF1LE_MASK (0x80U) -#define MCAN_IE_RF1LE_SHIFT (7U) -#define MCAN_IE_RF1LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1LE_SHIFT) & MCAN_IE_RF1LE_MASK) -#define MCAN_IE_RF1LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1LE_MASK) >> MCAN_IE_RF1LE_SHIFT) - -/* - * RF1FE (RW) - * - * Rx FIFO 1 Full Interrupt Enable - */ -#define MCAN_IE_RF1FE_MASK (0x40U) -#define MCAN_IE_RF1FE_SHIFT (6U) -#define MCAN_IE_RF1FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1FE_SHIFT) & MCAN_IE_RF1FE_MASK) -#define MCAN_IE_RF1FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1FE_MASK) >> MCAN_IE_RF1FE_SHIFT) - -/* - * RF1WE (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF1WE_MASK (0x20U) -#define MCAN_IE_RF1WE_SHIFT (5U) -#define MCAN_IE_RF1WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1WE_SHIFT) & MCAN_IE_RF1WE_MASK) -#define MCAN_IE_RF1WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1WE_MASK) >> MCAN_IE_RF1WE_SHIFT) - -/* - * RF1NE (RW) - * - * Rx FIFO 1 New Message Interrupt Enable - */ -#define MCAN_IE_RF1NE_MASK (0x10U) -#define MCAN_IE_RF1NE_SHIFT (4U) -#define MCAN_IE_RF1NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1NE_SHIFT) & MCAN_IE_RF1NE_MASK) -#define MCAN_IE_RF1NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1NE_MASK) >> MCAN_IE_RF1NE_SHIFT) - -/* - * RF0LE (RW) - * - * Rx FIFO 0 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF0LE_MASK (0x8U) -#define MCAN_IE_RF0LE_SHIFT (3U) -#define MCAN_IE_RF0LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0LE_SHIFT) & MCAN_IE_RF0LE_MASK) -#define MCAN_IE_RF0LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0LE_MASK) >> MCAN_IE_RF0LE_SHIFT) - -/* - * RF0FE (RW) - * - * Rx FIFO 0 Full Interrupt Enable - */ -#define MCAN_IE_RF0FE_MASK (0x4U) -#define MCAN_IE_RF0FE_SHIFT (2U) -#define MCAN_IE_RF0FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0FE_SHIFT) & MCAN_IE_RF0FE_MASK) -#define MCAN_IE_RF0FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0FE_MASK) >> MCAN_IE_RF0FE_SHIFT) - -/* - * RF0WE (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF0WE_MASK (0x2U) -#define MCAN_IE_RF0WE_SHIFT (1U) -#define MCAN_IE_RF0WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0WE_SHIFT) & MCAN_IE_RF0WE_MASK) -#define MCAN_IE_RF0WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0WE_MASK) >> MCAN_IE_RF0WE_SHIFT) - -/* - * RF0NE (RW) - * - * Rx FIFO 0 New Message Interrupt Enable - */ -#define MCAN_IE_RF0NE_MASK (0x1U) -#define MCAN_IE_RF0NE_SHIFT (0U) -#define MCAN_IE_RF0NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0NE_SHIFT) & MCAN_IE_RF0NE_MASK) -#define MCAN_IE_RF0NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0NE_MASK) >> MCAN_IE_RF0NE_SHIFT) - -/* Bitfield definition for register: ILS */ -/* - * ARAL (RW) - * - * Access to Reserved Address Line - */ -#define MCAN_ILS_ARAL_MASK (0x20000000UL) -#define MCAN_ILS_ARAL_SHIFT (29U) -#define MCAN_ILS_ARAL_SET(x) (((uint32_t)(x) << MCAN_ILS_ARAL_SHIFT) & MCAN_ILS_ARAL_MASK) -#define MCAN_ILS_ARAL_GET(x) (((uint32_t)(x) & MCAN_ILS_ARAL_MASK) >> MCAN_ILS_ARAL_SHIFT) - -/* - * PEDL (RW) - * - * Protocol Error in Data Phase Line - */ -#define MCAN_ILS_PEDL_MASK (0x10000000UL) -#define MCAN_ILS_PEDL_SHIFT (28U) -#define MCAN_ILS_PEDL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEDL_SHIFT) & MCAN_ILS_PEDL_MASK) -#define MCAN_ILS_PEDL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEDL_MASK) >> MCAN_ILS_PEDL_SHIFT) - -/* - * PEAL (RW) - * - * Protocol Error in Arbitration Phase Line - */ -#define MCAN_ILS_PEAL_MASK (0x8000000UL) -#define MCAN_ILS_PEAL_SHIFT (27U) -#define MCAN_ILS_PEAL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEAL_SHIFT) & MCAN_ILS_PEAL_MASK) -#define MCAN_ILS_PEAL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEAL_MASK) >> MCAN_ILS_PEAL_SHIFT) - -/* - * WDIL (RW) - * - * Watchdog Interrupt Line - */ -#define MCAN_ILS_WDIL_MASK (0x4000000UL) -#define MCAN_ILS_WDIL_SHIFT (26U) -#define MCAN_ILS_WDIL_SET(x) (((uint32_t)(x) << MCAN_ILS_WDIL_SHIFT) & MCAN_ILS_WDIL_MASK) -#define MCAN_ILS_WDIL_GET(x) (((uint32_t)(x) & MCAN_ILS_WDIL_MASK) >> MCAN_ILS_WDIL_SHIFT) - -/* - * BOL (RW) - * - * Bus_Off Status Interrupt Line - */ -#define MCAN_ILS_BOL_MASK (0x2000000UL) -#define MCAN_ILS_BOL_SHIFT (25U) -#define MCAN_ILS_BOL_SET(x) (((uint32_t)(x) << MCAN_ILS_BOL_SHIFT) & MCAN_ILS_BOL_MASK) -#define MCAN_ILS_BOL_GET(x) (((uint32_t)(x) & MCAN_ILS_BOL_MASK) >> MCAN_ILS_BOL_SHIFT) - -/* - * EWL (RW) - * - * Warning Status Interrupt Line - */ -#define MCAN_ILS_EWL_MASK (0x1000000UL) -#define MCAN_ILS_EWL_SHIFT (24U) -#define MCAN_ILS_EWL_SET(x) (((uint32_t)(x) << MCAN_ILS_EWL_SHIFT) & MCAN_ILS_EWL_MASK) -#define MCAN_ILS_EWL_GET(x) (((uint32_t)(x) & MCAN_ILS_EWL_MASK) >> MCAN_ILS_EWL_SHIFT) - -/* - * EPL (RW) - * - * Error Passive Interrupt Line - */ -#define MCAN_ILS_EPL_MASK (0x800000UL) -#define MCAN_ILS_EPL_SHIFT (23U) -#define MCAN_ILS_EPL_SET(x) (((uint32_t)(x) << MCAN_ILS_EPL_SHIFT) & MCAN_ILS_EPL_MASK) -#define MCAN_ILS_EPL_GET(x) (((uint32_t)(x) & MCAN_ILS_EPL_MASK) >> MCAN_ILS_EPL_SHIFT) - -/* - * ELOL (RW) - * - * Error Logging Overflow Interrupt Line - */ -#define MCAN_ILS_ELOL_MASK (0x400000UL) -#define MCAN_ILS_ELOL_SHIFT (22U) -#define MCAN_ILS_ELOL_SET(x) (((uint32_t)(x) << MCAN_ILS_ELOL_SHIFT) & MCAN_ILS_ELOL_MASK) -#define MCAN_ILS_ELOL_GET(x) (((uint32_t)(x) & MCAN_ILS_ELOL_MASK) >> MCAN_ILS_ELOL_SHIFT) - -/* - * BEUL (RW) - * - * Bit Error Uncorrected Interrupt Line - */ -#define MCAN_ILS_BEUL_MASK (0x200000UL) -#define MCAN_ILS_BEUL_SHIFT (21U) -#define MCAN_ILS_BEUL_SET(x) (((uint32_t)(x) << MCAN_ILS_BEUL_SHIFT) & MCAN_ILS_BEUL_MASK) -#define MCAN_ILS_BEUL_GET(x) (((uint32_t)(x) & MCAN_ILS_BEUL_MASK) >> MCAN_ILS_BEUL_SHIFT) - -/* - * BECL (RW) - * - * Bit Error Corrected Interrupt Line - */ -#define MCAN_ILS_BECL_MASK (0x100000UL) -#define MCAN_ILS_BECL_SHIFT (20U) -#define MCAN_ILS_BECL_SET(x) (((uint32_t)(x) << MCAN_ILS_BECL_SHIFT) & MCAN_ILS_BECL_MASK) -#define MCAN_ILS_BECL_GET(x) (((uint32_t)(x) & MCAN_ILS_BECL_MASK) >> MCAN_ILS_BECL_SHIFT) - -/* - * DRXL (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Line - */ -#define MCAN_ILS_DRXL_MASK (0x80000UL) -#define MCAN_ILS_DRXL_SHIFT (19U) -#define MCAN_ILS_DRXL_SET(x) (((uint32_t)(x) << MCAN_ILS_DRXL_SHIFT) & MCAN_ILS_DRXL_MASK) -#define MCAN_ILS_DRXL_GET(x) (((uint32_t)(x) & MCAN_ILS_DRXL_MASK) >> MCAN_ILS_DRXL_SHIFT) - -/* - * TOOL (RW) - * - * Timeout Occurred Interrupt Line - */ -#define MCAN_ILS_TOOL_MASK (0x40000UL) -#define MCAN_ILS_TOOL_SHIFT (18U) -#define MCAN_ILS_TOOL_SET(x) (((uint32_t)(x) << MCAN_ILS_TOOL_SHIFT) & MCAN_ILS_TOOL_MASK) -#define MCAN_ILS_TOOL_GET(x) (((uint32_t)(x) & MCAN_ILS_TOOL_MASK) >> MCAN_ILS_TOOL_SHIFT) - -/* - * MRAFL (RW) - * - * Message RAM Access Failure Interrupt Line - */ -#define MCAN_ILS_MRAFL_MASK (0x20000UL) -#define MCAN_ILS_MRAFL_SHIFT (17U) -#define MCAN_ILS_MRAFL_SET(x) (((uint32_t)(x) << MCAN_ILS_MRAFL_SHIFT) & MCAN_ILS_MRAFL_MASK) -#define MCAN_ILS_MRAFL_GET(x) (((uint32_t)(x) & MCAN_ILS_MRAFL_MASK) >> MCAN_ILS_MRAFL_SHIFT) - -/* - * TSWL (RW) - * - * Timestamp Wraparound Interrupt Line - */ -#define MCAN_ILS_TSWL_MASK (0x10000UL) -#define MCAN_ILS_TSWL_SHIFT (16U) -#define MCAN_ILS_TSWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TSWL_SHIFT) & MCAN_ILS_TSWL_MASK) -#define MCAN_ILS_TSWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TSWL_MASK) >> MCAN_ILS_TSWL_SHIFT) - -/* - * TEFLL (RW) - * - * Tx Event FIFO Event Lost Interrupt Line - */ -#define MCAN_ILS_TEFLL_MASK (0x8000U) -#define MCAN_ILS_TEFLL_SHIFT (15U) -#define MCAN_ILS_TEFLL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFLL_SHIFT) & MCAN_ILS_TEFLL_MASK) -#define MCAN_ILS_TEFLL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFLL_MASK) >> MCAN_ILS_TEFLL_SHIFT) - -/* - * TEFFL (RW) - * - * Tx Event FIFO Full Interrupt Line - */ -#define MCAN_ILS_TEFFL_MASK (0x4000U) -#define MCAN_ILS_TEFFL_SHIFT (14U) -#define MCAN_ILS_TEFFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFFL_SHIFT) & MCAN_ILS_TEFFL_MASK) -#define MCAN_ILS_TEFFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFFL_MASK) >> MCAN_ILS_TEFFL_SHIFT) - -/* - * TEFWL (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Line - */ -#define MCAN_ILS_TEFWL_MASK (0x2000U) -#define MCAN_ILS_TEFWL_SHIFT (13U) -#define MCAN_ILS_TEFWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFWL_SHIFT) & MCAN_ILS_TEFWL_MASK) -#define MCAN_ILS_TEFWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFWL_MASK) >> MCAN_ILS_TEFWL_SHIFT) - -/* - * TEFNL (RW) - * - * Tx Event FIFO New Entry Interrupt Line - */ -#define MCAN_ILS_TEFNL_MASK (0x1000U) -#define MCAN_ILS_TEFNL_SHIFT (12U) -#define MCAN_ILS_TEFNL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFNL_SHIFT) & MCAN_ILS_TEFNL_MASK) -#define MCAN_ILS_TEFNL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFNL_MASK) >> MCAN_ILS_TEFNL_SHIFT) - -/* - * TFEL (RW) - * - * Tx FIFO Empty Interrupt Line - */ -#define MCAN_ILS_TFEL_MASK (0x800U) -#define MCAN_ILS_TFEL_SHIFT (11U) -#define MCAN_ILS_TFEL_SET(x) (((uint32_t)(x) << MCAN_ILS_TFEL_SHIFT) & MCAN_ILS_TFEL_MASK) -#define MCAN_ILS_TFEL_GET(x) (((uint32_t)(x) & MCAN_ILS_TFEL_MASK) >> MCAN_ILS_TFEL_SHIFT) - -/* - * TCFL (RW) - * - * Transmission Cancellation Finished Interrupt Line - */ -#define MCAN_ILS_TCFL_MASK (0x400U) -#define MCAN_ILS_TCFL_SHIFT (10U) -#define MCAN_ILS_TCFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCFL_SHIFT) & MCAN_ILS_TCFL_MASK) -#define MCAN_ILS_TCFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCFL_MASK) >> MCAN_ILS_TCFL_SHIFT) - -/* - * TCL (RW) - * - * Transmission Completed Interrupt Line - */ -#define MCAN_ILS_TCL_MASK (0x200U) -#define MCAN_ILS_TCL_SHIFT (9U) -#define MCAN_ILS_TCL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCL_SHIFT) & MCAN_ILS_TCL_MASK) -#define MCAN_ILS_TCL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCL_MASK) >> MCAN_ILS_TCL_SHIFT) - -/* - * HPML (RW) - * - * High Priority Message Interrupt Line - */ -#define MCAN_ILS_HPML_MASK (0x100U) -#define MCAN_ILS_HPML_SHIFT (8U) -#define MCAN_ILS_HPML_SET(x) (((uint32_t)(x) << MCAN_ILS_HPML_SHIFT) & MCAN_ILS_HPML_MASK) -#define MCAN_ILS_HPML_GET(x) (((uint32_t)(x) & MCAN_ILS_HPML_MASK) >> MCAN_ILS_HPML_SHIFT) - -/* - * RF1LL (RW) - * - * Rx FIFO 1 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF1LL_MASK (0x80U) -#define MCAN_ILS_RF1LL_SHIFT (7U) -#define MCAN_ILS_RF1LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1LL_SHIFT) & MCAN_ILS_RF1LL_MASK) -#define MCAN_ILS_RF1LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1LL_MASK) >> MCAN_ILS_RF1LL_SHIFT) - -/* - * RF1FL (RW) - * - * Rx FIFO 1 Full Interrupt Line - */ -#define MCAN_ILS_RF1FL_MASK (0x40U) -#define MCAN_ILS_RF1FL_SHIFT (6U) -#define MCAN_ILS_RF1FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1FL_SHIFT) & MCAN_ILS_RF1FL_MASK) -#define MCAN_ILS_RF1FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1FL_MASK) >> MCAN_ILS_RF1FL_SHIFT) - -/* - * RF1WL (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF1WL_MASK (0x20U) -#define MCAN_ILS_RF1WL_SHIFT (5U) -#define MCAN_ILS_RF1WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1WL_SHIFT) & MCAN_ILS_RF1WL_MASK) -#define MCAN_ILS_RF1WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1WL_MASK) >> MCAN_ILS_RF1WL_SHIFT) - -/* - * RF1NL (RW) - * - * Rx FIFO 1 New Message Interrupt Line - */ -#define MCAN_ILS_RF1NL_MASK (0x10U) -#define MCAN_ILS_RF1NL_SHIFT (4U) -#define MCAN_ILS_RF1NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1NL_SHIFT) & MCAN_ILS_RF1NL_MASK) -#define MCAN_ILS_RF1NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1NL_MASK) >> MCAN_ILS_RF1NL_SHIFT) - -/* - * RF0LL (RW) - * - * Rx FIFO 0 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF0LL_MASK (0x8U) -#define MCAN_ILS_RF0LL_SHIFT (3U) -#define MCAN_ILS_RF0LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0LL_SHIFT) & MCAN_ILS_RF0LL_MASK) -#define MCAN_ILS_RF0LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0LL_MASK) >> MCAN_ILS_RF0LL_SHIFT) - -/* - * RF0FL (RW) - * - * Rx FIFO 0 Full Interrupt Line - */ -#define MCAN_ILS_RF0FL_MASK (0x4U) -#define MCAN_ILS_RF0FL_SHIFT (2U) -#define MCAN_ILS_RF0FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0FL_SHIFT) & MCAN_ILS_RF0FL_MASK) -#define MCAN_ILS_RF0FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0FL_MASK) >> MCAN_ILS_RF0FL_SHIFT) - -/* - * RF0WL (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF0WL_MASK (0x2U) -#define MCAN_ILS_RF0WL_SHIFT (1U) -#define MCAN_ILS_RF0WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0WL_SHIFT) & MCAN_ILS_RF0WL_MASK) -#define MCAN_ILS_RF0WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0WL_MASK) >> MCAN_ILS_RF0WL_SHIFT) - -/* - * RF0NL (RW) - * - * Rx FIFO 0 New Message Interrupt Line - */ -#define MCAN_ILS_RF0NL_MASK (0x1U) -#define MCAN_ILS_RF0NL_SHIFT (0U) -#define MCAN_ILS_RF0NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0NL_SHIFT) & MCAN_ILS_RF0NL_MASK) -#define MCAN_ILS_RF0NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0NL_MASK) >> MCAN_ILS_RF0NL_SHIFT) - -/* Bitfield definition for register: ILE */ -/* - * EINT1 (RW) - * - * Enable Interrupt Line 1 - * 0= Interrupt line m_can_int1 disabled - * 1= Interrupt line m_can_int1 enabled - */ -#define MCAN_ILE_EINT1_MASK (0x2U) -#define MCAN_ILE_EINT1_SHIFT (1U) -#define MCAN_ILE_EINT1_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT1_SHIFT) & MCAN_ILE_EINT1_MASK) -#define MCAN_ILE_EINT1_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT1_MASK) >> MCAN_ILE_EINT1_SHIFT) - -/* - * EINT0 (RW) - * - * Enable Interrupt Line 0 - * 0= Interrupt line m_can_int0 disabled - * 1= Interrupt line m_can_int0 enabled - */ -#define MCAN_ILE_EINT0_MASK (0x1U) -#define MCAN_ILE_EINT0_SHIFT (0U) -#define MCAN_ILE_EINT0_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT0_SHIFT) & MCAN_ILE_EINT0_MASK) -#define MCAN_ILE_EINT0_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT0_MASK) >> MCAN_ILE_EINT0_SHIFT) - -/* Bitfield definition for register: GFC */ -/* - * ANFS (RW) - * - * Accept Non-matching Frames Standard - * Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFS_MASK (0x30U) -#define MCAN_GFC_ANFS_SHIFT (4U) -#define MCAN_GFC_ANFS_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFS_SHIFT) & MCAN_GFC_ANFS_MASK) -#define MCAN_GFC_ANFS_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFS_MASK) >> MCAN_GFC_ANFS_SHIFT) - -/* - * ANFE (RW) - * - * Accept Non-matching Frames Extended - * Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFE_MASK (0xCU) -#define MCAN_GFC_ANFE_SHIFT (2U) -#define MCAN_GFC_ANFE_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFE_SHIFT) & MCAN_GFC_ANFE_MASK) -#define MCAN_GFC_ANFE_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFE_MASK) >> MCAN_GFC_ANFE_SHIFT) - -/* - * RRFS (RW) - * - * Reject Remote Frames Standard - * 0= Filter remote frames with 11-bit standard IDs - * 1= Reject all remote frames with 11-bit standard IDs - */ -#define MCAN_GFC_RRFS_MASK (0x2U) -#define MCAN_GFC_RRFS_SHIFT (1U) -#define MCAN_GFC_RRFS_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFS_SHIFT) & MCAN_GFC_RRFS_MASK) -#define MCAN_GFC_RRFS_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFS_MASK) >> MCAN_GFC_RRFS_SHIFT) - -/* - * RRFE (RW) - * - * Reject Remote Frames Extended - * 0= Filter remote frames with 29-bit extended IDs - * 1= Reject all remote frames with 29-bit extended IDs - */ -#define MCAN_GFC_RRFE_MASK (0x1U) -#define MCAN_GFC_RRFE_SHIFT (0U) -#define MCAN_GFC_RRFE_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFE_SHIFT) & MCAN_GFC_RRFE_MASK) -#define MCAN_GFC_RRFE_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFE_MASK) >> MCAN_GFC_RRFE_SHIFT) - -/* Bitfield definition for register: SIDFC */ -/* - * LSS (RW) - * - * List Size Standard - * 0= No standard Message ID filter - * 1-128= Number of standard Message ID filter elements - * >128= Values greater than 128 are interpreted as 128 - */ -#define MCAN_SIDFC_LSS_MASK (0xFF0000UL) -#define MCAN_SIDFC_LSS_SHIFT (16U) -#define MCAN_SIDFC_LSS_SET(x) (((uint32_t)(x) << MCAN_SIDFC_LSS_SHIFT) & MCAN_SIDFC_LSS_MASK) -#define MCAN_SIDFC_LSS_GET(x) (((uint32_t)(x) & MCAN_SIDFC_LSS_MASK) >> MCAN_SIDFC_LSS_SHIFT) - -/* - * FLSSA (RW) - * - * Filter List Standard Start Address - * Start address of standard Message ID filter list (32-bit word address) - */ -#define MCAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define MCAN_SIDFC_FLSSA_SHIFT (2U) -#define MCAN_SIDFC_FLSSA_SET(x) (((uint32_t)(x) << MCAN_SIDFC_FLSSA_SHIFT) & MCAN_SIDFC_FLSSA_MASK) -#define MCAN_SIDFC_FLSSA_GET(x) (((uint32_t)(x) & MCAN_SIDFC_FLSSA_MASK) >> MCAN_SIDFC_FLSSA_SHIFT) - -/* Bitfield definition for register: XIDFC */ -/* - * LSE (RW) - * - * List Size Extended - * 0= No extended Message ID filter - * 1-64= Number of extended Message ID filter elements - * >64= Values greater than 64 are interpreted as 64 - */ -#define MCAN_XIDFC_LSE_MASK (0x7F0000UL) -#define MCAN_XIDFC_LSE_SHIFT (16U) -#define MCAN_XIDFC_LSE_SET(x) (((uint32_t)(x) << MCAN_XIDFC_LSE_SHIFT) & MCAN_XIDFC_LSE_MASK) -#define MCAN_XIDFC_LSE_GET(x) (((uint32_t)(x) & MCAN_XIDFC_LSE_MASK) >> MCAN_XIDFC_LSE_SHIFT) - -/* - * FLESA (RW) - * - * Filter List Extended Start Address - * Start address of extended Message ID filter list (32-bit word address). - */ -#define MCAN_XIDFC_FLESA_MASK (0xFFFCU) -#define MCAN_XIDFC_FLESA_SHIFT (2U) -#define MCAN_XIDFC_FLESA_SET(x) (((uint32_t)(x) << MCAN_XIDFC_FLESA_SHIFT) & MCAN_XIDFC_FLESA_MASK) -#define MCAN_XIDFC_FLESA_GET(x) (((uint32_t)(x) & MCAN_XIDFC_FLESA_MASK) >> MCAN_XIDFC_FLESA_SHIFT) - -/* Bitfield definition for register: XIDAM */ -/* - * EIDM (RW) - * - * Extended ID Mask - * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - * Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - */ -#define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) -#define MCAN_XIDAM_EIDM_SHIFT (0U) -#define MCAN_XIDAM_EIDM_SET(x) (((uint32_t)(x) << MCAN_XIDAM_EIDM_SHIFT) & MCAN_XIDAM_EIDM_MASK) -#define MCAN_XIDAM_EIDM_GET(x) (((uint32_t)(x) & MCAN_XIDAM_EIDM_MASK) >> MCAN_XIDAM_EIDM_SHIFT) - -/* Bitfield definition for register: HPMS */ -/* - * FLST (R) - * - * Filter List - * Indicates the filter list of the matching filter element. - * 0= Standard Filter List - * 1= Extended Filter List - */ -#define MCAN_HPMS_FLST_MASK (0x8000U) -#define MCAN_HPMS_FLST_SHIFT (15U) -#define MCAN_HPMS_FLST_GET(x) (((uint32_t)(x) & MCAN_HPMS_FLST_MASK) >> MCAN_HPMS_FLST_SHIFT) - -/* - * FIDX (R) - * - * Filter Index - * Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - */ -#define MCAN_HPMS_FIDX_MASK (0x7F00U) -#define MCAN_HPMS_FIDX_SHIFT (8U) -#define MCAN_HPMS_FIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_FIDX_MASK) >> MCAN_HPMS_FIDX_SHIFT) - -/* - * MSI (R) - * - * Message Storage Indicator - * 00= No FIFO selected - * 01= FIFO message lost - * 10= Message stored in FIFO 0 - * 11= Message stored in FIFO 1 - */ -#define MCAN_HPMS_MSI_MASK (0xC0U) -#define MCAN_HPMS_MSI_SHIFT (6U) -#define MCAN_HPMS_MSI_GET(x) (((uint32_t)(x) & MCAN_HPMS_MSI_MASK) >> MCAN_HPMS_MSI_SHIFT) - -/* - * BIDX (R) - * - * Buffer Index - * Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - */ -#define MCAN_HPMS_BIDX_MASK (0x3FU) -#define MCAN_HPMS_BIDX_SHIFT (0U) -#define MCAN_HPMS_BIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_BIDX_MASK) >> MCAN_HPMS_BIDX_SHIFT) - -/* Bitfield definition for register: NDAT1 */ -/* - * ND1 (RW) - * - * New Data[31:0] - * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT1_ND1_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT1_ND1_SHIFT (0U) -#define MCAN_NDAT1_ND1_SET(x) (((uint32_t)(x) << MCAN_NDAT1_ND1_SHIFT) & MCAN_NDAT1_ND1_MASK) -#define MCAN_NDAT1_ND1_GET(x) (((uint32_t)(x) & MCAN_NDAT1_ND1_MASK) >> MCAN_NDAT1_ND1_SHIFT) - -/* Bitfield definition for register: NDAT2 */ -/* - * ND2 (RW) - * - * New Data[63:32] - * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT2_ND2_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT2_ND2_SHIFT (0U) -#define MCAN_NDAT2_ND2_SET(x) (((uint32_t)(x) << MCAN_NDAT2_ND2_SHIFT) & MCAN_NDAT2_ND2_MASK) -#define MCAN_NDAT2_ND2_GET(x) (((uint32_t)(x) & MCAN_NDAT2_ND2_MASK) >> MCAN_NDAT2_ND2_SHIFT) - -/* Bitfield definition for register: RXF0C */ -/* - * F0OM (RW) - * - * FIFO 0 Operation Mode - * FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 0 blocking mode - * 1= FIFO 0 overwrite mode - */ -#define MCAN_RXF0C_F0OM_MASK (0x80000000UL) -#define MCAN_RXF0C_F0OM_SHIFT (31U) -#define MCAN_RXF0C_F0OM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0OM_SHIFT) & MCAN_RXF0C_F0OM_MASK) -#define MCAN_RXF0C_F0OM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0OM_MASK) >> MCAN_RXF0C_F0OM_SHIFT) - -/* - * F0WM (RW) - * - * Rx FIFO 0 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF0C_F0WM_MASK (0x7F000000UL) -#define MCAN_RXF0C_F0WM_SHIFT (24U) -#define MCAN_RXF0C_F0WM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0WM_SHIFT) & MCAN_RXF0C_F0WM_MASK) -#define MCAN_RXF0C_F0WM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0WM_MASK) >> MCAN_RXF0C_F0WM_SHIFT) - -/* - * F0S (RW) - * - * Rx FIFO 0 Size - * 0= No Rx FIFO 0 - * 1-64= Number of Rx FIFO 0 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 0 elements are indexed from 0 to F0S-1 - */ -#define MCAN_RXF0C_F0S_MASK (0x7F0000UL) -#define MCAN_RXF0C_F0S_SHIFT (16U) -#define MCAN_RXF0C_F0S_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0S_SHIFT) & MCAN_RXF0C_F0S_MASK) -#define MCAN_RXF0C_F0S_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0S_MASK) >> MCAN_RXF0C_F0S_SHIFT) - -/* - * F0SA (RW) - * - * Rx FIFO 0 Start Address - * Start address of Rx FIFO 0 in Message RAM (32-bit word address) - */ -#define MCAN_RXF0C_F0SA_MASK (0xFFFCU) -#define MCAN_RXF0C_F0SA_SHIFT (2U) -#define MCAN_RXF0C_F0SA_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0SA_SHIFT) & MCAN_RXF0C_F0SA_MASK) -#define MCAN_RXF0C_F0SA_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0SA_MASK) >> MCAN_RXF0C_F0SA_SHIFT) - -/* Bitfield definition for register: RXF0S */ -/* - * RF0L (R) - * - * Rx FIFO 0 Message Lost - * This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - * Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF0S_RF0L_MASK (0x2000000UL) -#define MCAN_RXF0S_RF0L_SHIFT (25U) -#define MCAN_RXF0S_RF0L_GET(x) (((uint32_t)(x) & MCAN_RXF0S_RF0L_MASK) >> MCAN_RXF0S_RF0L_SHIFT) - -/* - * F0F (R) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_RXF0S_F0F_MASK (0x1000000UL) -#define MCAN_RXF0S_F0F_SHIFT (24U) -#define MCAN_RXF0S_F0F_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0F_MASK) >> MCAN_RXF0S_F0F_SHIFT) - -/* - * F0PI (R) - * - * Rx FIFO 0 Put Index - * Rx FIFO 0 write index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0PI_MASK (0x3F0000UL) -#define MCAN_RXF0S_F0PI_SHIFT (16U) -#define MCAN_RXF0S_F0PI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0PI_MASK) >> MCAN_RXF0S_F0PI_SHIFT) - -/* - * F0GI (R) - * - * Rx FIFO 0 Get Index - * Rx FIFO 0 read index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0GI_MASK (0x3F00U) -#define MCAN_RXF0S_F0GI_SHIFT (8U) -#define MCAN_RXF0S_F0GI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT) - -/* - * F0FL (R) - * - * Rx FIFO 0 Fill Level - * Number of elements stored in Rx FIFO 0, range 0 to 64. - */ -#define MCAN_RXF0S_F0FL_MASK (0x7FU) -#define MCAN_RXF0S_F0FL_SHIFT (0U) -#define MCAN_RXF0S_F0FL_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT) - -/* Bitfield definition for register: RXF0A */ -/* - * F0AI (RW) - * - * Rx FIFO 0 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. - * This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - */ -#define MCAN_RXF0A_F0AI_MASK (0x3FU) -#define MCAN_RXF0A_F0AI_SHIFT (0U) -#define MCAN_RXF0A_F0AI_SET(x) (((uint32_t)(x) << MCAN_RXF0A_F0AI_SHIFT) & MCAN_RXF0A_F0AI_MASK) -#define MCAN_RXF0A_F0AI_GET(x) (((uint32_t)(x) & MCAN_RXF0A_F0AI_MASK) >> MCAN_RXF0A_F0AI_SHIFT) - -/* Bitfield definition for register: RXBC */ -/* - * RBSA (RW) - * - * Rx Buffer Start Address - * Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - */ -#define MCAN_RXBC_RBSA_MASK (0xFFFCU) -#define MCAN_RXBC_RBSA_SHIFT (2U) -#define MCAN_RXBC_RBSA_SET(x) (((uint32_t)(x) << MCAN_RXBC_RBSA_SHIFT) & MCAN_RXBC_RBSA_MASK) -#define MCAN_RXBC_RBSA_GET(x) (((uint32_t)(x) & MCAN_RXBC_RBSA_MASK) >> MCAN_RXBC_RBSA_SHIFT) - -/* Bitfield definition for register: RXF1C */ -/* - * F1OM (RW) - * - * FIFO 1 Operation Mode - * FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 1 blocking mode - * 1= FIFO 1 overwrite mode - */ -#define MCAN_RXF1C_F1OM_MASK (0x80000000UL) -#define MCAN_RXF1C_F1OM_SHIFT (31U) -#define MCAN_RXF1C_F1OM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1OM_SHIFT) & MCAN_RXF1C_F1OM_MASK) -#define MCAN_RXF1C_F1OM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1OM_MASK) >> MCAN_RXF1C_F1OM_SHIFT) - -/* - * F1WM (RW) - * - * Rx FIFO 1 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF1C_F1WM_MASK (0x7F000000UL) -#define MCAN_RXF1C_F1WM_SHIFT (24U) -#define MCAN_RXF1C_F1WM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1WM_SHIFT) & MCAN_RXF1C_F1WM_MASK) -#define MCAN_RXF1C_F1WM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1WM_MASK) >> MCAN_RXF1C_F1WM_SHIFT) - -/* - * F1S (RW) - * - * Rx FIFO 1 Size - * 0= No Rx FIFO 1 - * 1-64= Number of Rx FIFO 1 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - */ -#define MCAN_RXF1C_F1S_MASK (0x7F0000UL) -#define MCAN_RXF1C_F1S_SHIFT (16U) -#define MCAN_RXF1C_F1S_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1S_SHIFT) & MCAN_RXF1C_F1S_MASK) -#define MCAN_RXF1C_F1S_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1S_MASK) >> MCAN_RXF1C_F1S_SHIFT) - -/* - * F1SA (RW) - * - * Rx FIFO 1 Start Address - * Start address of Rx FIFO 1 in Message RAM (32-bit word address) - */ -#define MCAN_RXF1C_F1SA_MASK (0xFFFCU) -#define MCAN_RXF1C_F1SA_SHIFT (2U) -#define MCAN_RXF1C_F1SA_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1SA_SHIFT) & MCAN_RXF1C_F1SA_MASK) -#define MCAN_RXF1C_F1SA_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1SA_MASK) >> MCAN_RXF1C_F1SA_SHIFT) - -/* Bitfield definition for register: RXF1S */ -/* - * DMS (R) - * - * Debug Message Status - * 00= Idle state, wait for reception of debug messages, DMA request is cleared - * 01= Debug message A received - * 10= Debug messages A, B received - * 11= Debug messages A, B, C received, DMA request is set - */ -#define MCAN_RXF1S_DMS_MASK (0xC0000000UL) -#define MCAN_RXF1S_DMS_SHIFT (30U) -#define MCAN_RXF1S_DMS_GET(x) (((uint32_t)(x) & MCAN_RXF1S_DMS_MASK) >> MCAN_RXF1S_DMS_SHIFT) - -/* - * RF1L (R) - * - * Rx FIFO 1 Message Lost - * This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - * Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF1S_RF1L_MASK (0x2000000UL) -#define MCAN_RXF1S_RF1L_SHIFT (25U) -#define MCAN_RXF1S_RF1L_GET(x) (((uint32_t)(x) & MCAN_RXF1S_RF1L_MASK) >> MCAN_RXF1S_RF1L_SHIFT) - -/* - * F1F (R) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_RXF1S_F1F_MASK (0x1000000UL) -#define MCAN_RXF1S_F1F_SHIFT (24U) -#define MCAN_RXF1S_F1F_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1F_MASK) >> MCAN_RXF1S_F1F_SHIFT) - -/* - * F1PI (R) - * - * Rx FIFO 1 Put Index - * Rx FIFO 1 write index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1PI_MASK (0x3F0000UL) -#define MCAN_RXF1S_F1PI_SHIFT (16U) -#define MCAN_RXF1S_F1PI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1PI_MASK) >> MCAN_RXF1S_F1PI_SHIFT) - -/* - * F1GI (R) - * - * Rx FIFO 1 Get Index - * Rx FIFO 1 read index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1GI_MASK (0x3F00U) -#define MCAN_RXF1S_F1GI_SHIFT (8U) -#define MCAN_RXF1S_F1GI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT) - -/* - * F1FL (R) - * - * Rx FIFO 1 Fill Level - * Number of elements stored in Rx FIFO 1, range 0 to 64. - */ -#define MCAN_RXF1S_F1FL_MASK (0x7FU) -#define MCAN_RXF1S_F1FL_SHIFT (0U) -#define MCAN_RXF1S_F1FL_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT) - -/* Bitfield definition for register: RXF1A */ -/* - * F1AI (RW) - * - * Rx FIFO 1 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. - * This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - */ -#define MCAN_RXF1A_F1AI_MASK (0x3FU) -#define MCAN_RXF1A_F1AI_SHIFT (0U) -#define MCAN_RXF1A_F1AI_SET(x) (((uint32_t)(x) << MCAN_RXF1A_F1AI_SHIFT) & MCAN_RXF1A_F1AI_MASK) -#define MCAN_RXF1A_F1AI_GET(x) (((uint32_t)(x) & MCAN_RXF1A_F1AI_MASK) >> MCAN_RXF1A_F1AI_SHIFT) - -/* Bitfield definition for register: RXESC */ -/* - * RBDS (RW) - * - * Rx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_RBDS_MASK (0x700U) -#define MCAN_RXESC_RBDS_SHIFT (8U) -#define MCAN_RXESC_RBDS_SET(x) (((uint32_t)(x) << MCAN_RXESC_RBDS_SHIFT) & MCAN_RXESC_RBDS_MASK) -#define MCAN_RXESC_RBDS_GET(x) (((uint32_t)(x) & MCAN_RXESC_RBDS_MASK) >> MCAN_RXESC_RBDS_SHIFT) - -/* - * F1DS (RW) - * - * Rx FIFO 1 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_F1DS_MASK (0x70U) -#define MCAN_RXESC_F1DS_SHIFT (4U) -#define MCAN_RXESC_F1DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F1DS_SHIFT) & MCAN_RXESC_F1DS_MASK) -#define MCAN_RXESC_F1DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F1DS_MASK) >> MCAN_RXESC_F1DS_SHIFT) - -/* - * F0DS (RW) - * - * Rx FIFO 0 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, - * only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - */ -#define MCAN_RXESC_F0DS_MASK (0x7U) -#define MCAN_RXESC_F0DS_SHIFT (0U) -#define MCAN_RXESC_F0DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F0DS_SHIFT) & MCAN_RXESC_F0DS_MASK) -#define MCAN_RXESC_F0DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F0DS_MASK) >> MCAN_RXESC_F0DS_SHIFT) - -/* Bitfield definition for register: TXBC */ -/* - * TFQM (RW) - * - * Tx FIFO/Queue Mode - * 0= Tx FIFO operation - * 1= Tx Queue operation - */ -#define MCAN_TXBC_TFQM_MASK (0x40000000UL) -#define MCAN_TXBC_TFQM_SHIFT (30U) -#define MCAN_TXBC_TFQM_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQM_SHIFT) & MCAN_TXBC_TFQM_MASK) -#define MCAN_TXBC_TFQM_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQM_MASK) >> MCAN_TXBC_TFQM_SHIFT) - -/* - * TFQS (RW) - * - * Transmit FIFO/Queue Size - * 0= No Tx FIFO/Queue - * 1-32= Number of Tx Buffers used for Tx FIFO/Queue - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_TFQS_MASK (0x3F000000UL) -#define MCAN_TXBC_TFQS_SHIFT (24U) -#define MCAN_TXBC_TFQS_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQS_SHIFT) & MCAN_TXBC_TFQS_MASK) -#define MCAN_TXBC_TFQS_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQS_MASK) >> MCAN_TXBC_TFQS_SHIFT) - -/* - * NDTB (RW) - * - * Number of Dedicated Transmit Buffers - * 0= No Dedicated Tx Buffers - * 1-32= Number of Dedicated Tx Buffers - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_NDTB_MASK (0x3F0000UL) -#define MCAN_TXBC_NDTB_SHIFT (16U) -#define MCAN_TXBC_NDTB_SET(x) (((uint32_t)(x) << MCAN_TXBC_NDTB_SHIFT) & MCAN_TXBC_NDTB_MASK) -#define MCAN_TXBC_NDTB_GET(x) (((uint32_t)(x) & MCAN_TXBC_NDTB_MASK) >> MCAN_TXBC_NDTB_SHIFT) - -/* - * TBSA (RW) - * - * Tx Buffers Start Address - * Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). - * Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - */ -#define MCAN_TXBC_TBSA_MASK (0xFFFCU) -#define MCAN_TXBC_TBSA_SHIFT (2U) -#define MCAN_TXBC_TBSA_SET(x) (((uint32_t)(x) << MCAN_TXBC_TBSA_SHIFT) & MCAN_TXBC_TBSA_MASK) -#define MCAN_TXBC_TBSA_GET(x) (((uint32_t)(x) & MCAN_TXBC_TBSA_MASK) >> MCAN_TXBC_TBSA_SHIFT) - -/* Bitfield definition for register: TXFQS */ -/* - * TFQF (R) - * - * Tx FIFO/Queue Full - * 0= Tx FIFO/Queue not full - * 1= Tx FIFO/Queue full - */ -#define MCAN_TXFQS_TFQF_MASK (0x200000UL) -#define MCAN_TXFQS_TFQF_SHIFT (21U) -#define MCAN_TXFQS_TFQF_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQF_MASK) >> MCAN_TXFQS_TFQF_SHIFT) - -/* - * TFQPI (R) - * - * Tx FIFO/Queue Put Index - * Tx FIFO/Queue write index pointer, range 0 to 31. - */ -#define MCAN_TXFQS_TFQPI_MASK (0x1F0000UL) -#define MCAN_TXFQS_TFQPI_SHIFT (16U) -#define MCAN_TXFQS_TFQPI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQPI_MASK) >> MCAN_TXFQS_TFQPI_SHIFT) - -/* - * TFGI (R) - * - * Tx FIFO Get Index - * Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured - * (TXBC.TFQM = ‘1’). - */ -#define MCAN_TXFQS_TFGI_MASK (0x1F00U) -#define MCAN_TXFQS_TFGI_SHIFT (8U) -#define MCAN_TXFQS_TFGI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFGI_MASK) >> MCAN_TXFQS_TFGI_SHIFT) - -/* - * TFFL (R) - * - * Tx FIFO Free Level - * Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) - * Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with - * the first dedicated Tx Buffers. - * Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - */ -#define MCAN_TXFQS_TFFL_MASK (0x3FU) -#define MCAN_TXFQS_TFFL_SHIFT (0U) -#define MCAN_TXFQS_TFFL_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFFL_MASK) >> MCAN_TXFQS_TFFL_SHIFT) - -/* Bitfield definition for register: TXESC */ -/* - * TBDS (RW) - * - * Tx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - */ -#define MCAN_TXESC_TBDS_MASK (0x7U) -#define MCAN_TXESC_TBDS_SHIFT (0U) -#define MCAN_TXESC_TBDS_SET(x) (((uint32_t)(x) << MCAN_TXESC_TBDS_SHIFT) & MCAN_TXESC_TBDS_MASK) -#define MCAN_TXESC_TBDS_GET(x) (((uint32_t)(x) & MCAN_TXESC_TBDS_MASK) >> MCAN_TXESC_TBDS_SHIFT) - -/* Bitfield definition for register: TXBRP */ -/* - * TRP (R) - * - * Transmission Request Pending - * Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register - * TXBCR. - * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the - * highest priority (Tx Buffer with lowest Message ID). - * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, - * this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. - * After a cancellation has been requested, a finished cancellation is signalled via TXBCF - * ? after successful transmission together with the corresponding TXBTO bit - * ? when the transmission has not yet been started at the point of cancellation - * ? when the transmission has been aborted due to lost arbitration - * ? when an error occurred during frame transmission - * In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. - * 0= No transmission request pending - * 1= Transmission request pending - * Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - */ -#define MCAN_TXBRP_TRP_MASK (0xFFFFFFFFUL) -#define MCAN_TXBRP_TRP_SHIFT (0U) -#define MCAN_TXBRP_TRP_GET(x) (((uint32_t)(x) & MCAN_TXBRP_TRP_MASK) >> MCAN_TXBRP_TRP_SHIFT) - -/* Bitfield definition for register: TXBAR */ -/* - * AR (RW) - * - * Add Request - * Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx - * Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. - * When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. - * 0= No transmission request added - * 1= Transmission requested added - * Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - */ -#define MCAN_TXBAR_AR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBAR_AR_SHIFT (0U) -#define MCAN_TXBAR_AR_SET(x) (((uint32_t)(x) << MCAN_TXBAR_AR_SHIFT) & MCAN_TXBAR_AR_MASK) -#define MCAN_TXBAR_AR_GET(x) (((uint32_t)(x) & MCAN_TXBAR_AR_MASK) >> MCAN_TXBAR_AR_SHIFT) - -/* Bitfield definition for register: TXBCR */ -/* - * CR (RW) - * - * Cancellation Request - * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. - * This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. - * 0= No cancellation pending - * 1= Cancellation pending - */ -#define MCAN_TXBCR_CR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCR_CR_SHIFT (0U) -#define MCAN_TXBCR_CR_SET(x) (((uint32_t)(x) << MCAN_TXBCR_CR_SHIFT) & MCAN_TXBCR_CR_MASK) -#define MCAN_TXBCR_CR_GET(x) (((uint32_t)(x) & MCAN_TXBCR_CR_MASK) >> MCAN_TXBCR_CR_SHIFT) - -/* Bitfield definition for register: TXBTO */ -/* - * TO (R) - * - * Transmission Occurred - * Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmission occurred - * 1= Transmission occurred - */ -#define MCAN_TXBTO_TO_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTO_TO_SHIFT (0U) -#define MCAN_TXBTO_TO_GET(x) (((uint32_t)(x) & MCAN_TXBTO_TO_MASK) >> MCAN_TXBTO_TO_SHIFT) - -/* Bitfield definition for register: TXBCF */ -/* - * CF (R) - * - * Cancellation Finished - * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. - * In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmit buffer cancellation - * 1= Transmit buffer cancellation finished - */ -#define MCAN_TXBCF_CF_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCF_CF_SHIFT (0U) -#define MCAN_TXBCF_CF_GET(x) (((uint32_t)(x) & MCAN_TXBCF_CF_MASK) >> MCAN_TXBCF_CF_SHIFT) - -/* Bitfield definition for register: TXBTIE */ -/* - * TIE (RW) - * - * Transmission Interrupt Enable - * Each Tx Buffer has its own Transmission Interrupt Enable bit. - * 0= Transmission interrupt disabled - * 1= Transmission interrupt enable - */ -#define MCAN_TXBTIE_TIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTIE_TIE_SHIFT (0U) -#define MCAN_TXBTIE_TIE_SET(x) (((uint32_t)(x) << MCAN_TXBTIE_TIE_SHIFT) & MCAN_TXBTIE_TIE_MASK) -#define MCAN_TXBTIE_TIE_GET(x) (((uint32_t)(x) & MCAN_TXBTIE_TIE_MASK) >> MCAN_TXBTIE_TIE_SHIFT) - -/* Bitfield definition for register: TXBCIE */ -/* - * CFIE (RW) - * - * Cancellation Finished Interrupt Enable - * Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. - * 0= Cancellation finished interrupt disabled - * 1= Cancellation finished interrupt enabled - */ -#define MCAN_TXBCIE_CFIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCIE_CFIE_SHIFT (0U) -#define MCAN_TXBCIE_CFIE_SET(x) (((uint32_t)(x) << MCAN_TXBCIE_CFIE_SHIFT) & MCAN_TXBCIE_CFIE_MASK) -#define MCAN_TXBCIE_CFIE_GET(x) (((uint32_t)(x) & MCAN_TXBCIE_CFIE_MASK) >> MCAN_TXBCIE_CFIE_SHIFT) - -/* Bitfield definition for register: TXEFC */ -/* - * EFWM (RW) - * - * Event FIFO Watermark - * 0= Watermark interrupt disabled - * 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) - * >32= Watermark interrupt disabled - */ -#define MCAN_TXEFC_EFWM_MASK (0x3F000000UL) -#define MCAN_TXEFC_EFWM_SHIFT (24U) -#define MCAN_TXEFC_EFWM_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFWM_SHIFT) & MCAN_TXEFC_EFWM_MASK) -#define MCAN_TXEFC_EFWM_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFWM_MASK) >> MCAN_TXEFC_EFWM_SHIFT) - -/* - * EFS (RW) - * - * Event FIFO Size - * 0= Tx Event FIFO disabled - * 1-32= Number of Tx Event FIFO elements - * >32= Values greater than 32 are interpreted as 32 - * The Tx Event FIFO elements are indexed from 0 to EFS - 1 - */ -#define MCAN_TXEFC_EFS_MASK (0x3F0000UL) -#define MCAN_TXEFC_EFS_SHIFT (16U) -#define MCAN_TXEFC_EFS_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFS_SHIFT) & MCAN_TXEFC_EFS_MASK) -#define MCAN_TXEFC_EFS_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFS_MASK) >> MCAN_TXEFC_EFS_SHIFT) - -/* - * EFSA (RW) - * - * Event FIFO Start Address - * Start address of Tx Event FIFO in Message RAM (32-bit word address) - */ -#define MCAN_TXEFC_EFSA_MASK (0xFFFCU) -#define MCAN_TXEFC_EFSA_SHIFT (2U) -#define MCAN_TXEFC_EFSA_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFSA_SHIFT) & MCAN_TXEFC_EFSA_MASK) -#define MCAN_TXEFC_EFSA_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFSA_MASK) >> MCAN_TXEFC_EFSA_SHIFT) - -/* Bitfield definition for register: TXEFS */ -/* - * TEFL (R) - * - * Tx Event FIFO Element Lost - * This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - */ -#define MCAN_TXEFS_TEFL_MASK (0x2000000UL) -#define MCAN_TXEFS_TEFL_SHIFT (25U) -#define MCAN_TXEFS_TEFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_TEFL_MASK) >> MCAN_TXEFS_TEFL_SHIFT) - -/* - * EFF (R) - * - * Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_TXEFS_EFF_MASK (0x1000000UL) -#define MCAN_TXEFS_EFF_SHIFT (24U) -#define MCAN_TXEFS_EFF_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFF_MASK) >> MCAN_TXEFS_EFF_SHIFT) - -/* - * EFPI (R) - * - * Event FIFO Put Index - * Tx Event FIFO write index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFPI_MASK (0x1F0000UL) -#define MCAN_TXEFS_EFPI_SHIFT (16U) -#define MCAN_TXEFS_EFPI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFPI_MASK) >> MCAN_TXEFS_EFPI_SHIFT) - -/* - * EFGI (R) - * - * Event FIFO Get Index - * Tx Event FIFO read index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFGI_MASK (0x1F00U) -#define MCAN_TXEFS_EFGI_SHIFT (8U) -#define MCAN_TXEFS_EFGI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFGI_MASK) >> MCAN_TXEFS_EFGI_SHIFT) - -/* - * EFFL (R) - * - * Event FIFO Fill Level - * Number of elements stored in Tx Event FIFO, range 0 to 32. - */ -#define MCAN_TXEFS_EFFL_MASK (0x3FU) -#define MCAN_TXEFS_EFFL_SHIFT (0U) -#define MCAN_TXEFS_EFFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFFL_MASK) >> MCAN_TXEFS_EFFL_SHIFT) - -/* Bitfield definition for register: TXEFA */ -/* - * EFAI (RW) - * - * Event FIFO Acknowledge Index - * After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get - * Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - */ -#define MCAN_TXEFA_EFAI_MASK (0x1FU) -#define MCAN_TXEFA_EFAI_SHIFT (0U) -#define MCAN_TXEFA_EFAI_SET(x) (((uint32_t)(x) << MCAN_TXEFA_EFAI_SHIFT) & MCAN_TXEFA_EFAI_MASK) -#define MCAN_TXEFA_EFAI_GET(x) (((uint32_t)(x) & MCAN_TXEFA_EFAI_MASK) >> MCAN_TXEFA_EFAI_SHIFT) - -/* Bitfield definition for register array: TS_SEL */ -/* - * TS (R) - * - * Timestamp Word TS - * default can save 16 timestamps with 32bit; - * if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - */ -#define MCAN_TS_SEL_TS_MASK (0xFFFFFFFFUL) -#define MCAN_TS_SEL_TS_SHIFT (0U) -#define MCAN_TS_SEL_TS_GET(x) (((uint32_t)(x) & MCAN_TS_SEL_TS_MASK) >> MCAN_TS_SEL_TS_SHIFT) - -/* Bitfield definition for register: CREL */ -/* - * REL (R) - * - * Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_REL_MASK (0xF0000000UL) -#define MCAN_CREL_REL_SHIFT (28U) -#define MCAN_CREL_REL_GET(x) (((uint32_t)(x) & MCAN_CREL_REL_MASK) >> MCAN_CREL_REL_SHIFT) - -/* - * STEP (R) - * - * Step of Core Release - * One digit, BCD-coded. - */ -#define MCAN_CREL_STEP_MASK (0xF000000UL) -#define MCAN_CREL_STEP_SHIFT (24U) -#define MCAN_CREL_STEP_GET(x) (((uint32_t)(x) & MCAN_CREL_STEP_MASK) >> MCAN_CREL_STEP_SHIFT) - -/* - * SUBSTEP (R) - * - * Sub-step of Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_SUBSTEP_MASK (0xF00000UL) -#define MCAN_CREL_SUBSTEP_SHIFT (20U) -#define MCAN_CREL_SUBSTEP_GET(x) (((uint32_t)(x) & MCAN_CREL_SUBSTEP_MASK) >> MCAN_CREL_SUBSTEP_SHIFT) - -/* - * YEAR (R) - * - * Timestamp Year - * One digit, BCD-coded. This field is set by generic parameter on - * synthesis. - */ -#define MCAN_CREL_YEAR_MASK (0xF0000UL) -#define MCAN_CREL_YEAR_SHIFT (16U) -#define MCAN_CREL_YEAR_GET(x) (((uint32_t)(x) & MCAN_CREL_YEAR_MASK) >> MCAN_CREL_YEAR_SHIFT) - -/* - * MON (R) - * - * Timestamp Month - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_MON_MASK (0xFF00U) -#define MCAN_CREL_MON_SHIFT (8U) -#define MCAN_CREL_MON_GET(x) (((uint32_t)(x) & MCAN_CREL_MON_MASK) >> MCAN_CREL_MON_SHIFT) - -/* - * DAY (R) - * - * Timestamp Day - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_DAY_MASK (0xFFU) -#define MCAN_CREL_DAY_SHIFT (0U) -#define MCAN_CREL_DAY_GET(x) (((uint32_t)(x) & MCAN_CREL_DAY_MASK) >> MCAN_CREL_DAY_SHIFT) - -/* Bitfield definition for register: TSCFG */ -/* - * TBPRE (RW) - * - * Timebase Prescaler - * 0x00 to 0xFF - * The value by which the oscillator frequency is divided for - * generating the timebase counter clock. Valid values for the - * Timebase Prescaler are 0 to 255. The actual interpretation by - * the hardware of this value is such that one more than the value - * programmed here is used. Affects only the TSU internal - * timebase. When the internal timebase is excluded by synthesis, - * TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not - * used. - */ -#define MCAN_TSCFG_TBPRE_MASK (0xFF00U) -#define MCAN_TSCFG_TBPRE_SHIFT (8U) -#define MCAN_TSCFG_TBPRE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBPRE_SHIFT) & MCAN_TSCFG_TBPRE_MASK) -#define MCAN_TSCFG_TBPRE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBPRE_MASK) >> MCAN_TSCFG_TBPRE_SHIFT) - -/* - * EN64 (RW) - * - * set to use 64bit timestamp. - * when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. - * TSP can be used to select different one - */ -#define MCAN_TSCFG_EN64_MASK (0x8U) -#define MCAN_TSCFG_EN64_SHIFT (3U) -#define MCAN_TSCFG_EN64_SET(x) (((uint32_t)(x) << MCAN_TSCFG_EN64_SHIFT) & MCAN_TSCFG_EN64_MASK) -#define MCAN_TSCFG_EN64_GET(x) (((uint32_t)(x) & MCAN_TSCFG_EN64_MASK) >> MCAN_TSCFG_EN64_SHIFT) - -/* - * SCP (RW) - * - * Select Capturing Position - * 0: Capture Timestamp at EOF - * 1: Capture Timestamp at SOF - */ -#define MCAN_TSCFG_SCP_MASK (0x4U) -#define MCAN_TSCFG_SCP_SHIFT (2U) -#define MCAN_TSCFG_SCP_SET(x) (((uint32_t)(x) << MCAN_TSCFG_SCP_SHIFT) & MCAN_TSCFG_SCP_MASK) -#define MCAN_TSCFG_SCP_GET(x) (((uint32_t)(x) & MCAN_TSCFG_SCP_MASK) >> MCAN_TSCFG_SCP_SHIFT) - -/* - * TBCS (RW) - * - * Timebase Counter Select - * When the internal timebase is excluded by synthesis, TBCS is - * fixed to ‘1’. - * 0: Timestamp value captured from internal timebase counter, - * ATB.TB[31:0] is the internal timbase counter - * 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - */ -#define MCAN_TSCFG_TBCS_MASK (0x2U) -#define MCAN_TSCFG_TBCS_SHIFT (1U) -#define MCAN_TSCFG_TBCS_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBCS_SHIFT) & MCAN_TSCFG_TBCS_MASK) -#define MCAN_TSCFG_TBCS_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBCS_MASK) >> MCAN_TSCFG_TBCS_SHIFT) - -/* - * TSUE (RW) - * - * Timestamp Unit Enable - * 0: TSU disabled - * 1: TSU enabled - */ -#define MCAN_TSCFG_TSUE_MASK (0x1U) -#define MCAN_TSCFG_TSUE_SHIFT (0U) -#define MCAN_TSCFG_TSUE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TSUE_SHIFT) & MCAN_TSCFG_TSUE_MASK) -#define MCAN_TSCFG_TSUE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TSUE_MASK) >> MCAN_TSCFG_TSUE_SHIFT) - -/* Bitfield definition for register: TSS1 */ -/* - * TSL (R) - * - * Timestamp Lost - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. - * Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSL_MASK (0xFFFF0000UL) -#define MCAN_TSS1_TSL_SHIFT (16U) -#define MCAN_TSS1_TSL_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSL_MASK) >> MCAN_TSS1_TSL_SHIFT) - -/* - * TSN (R) - * - * Timestamp New - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related - * Timestamp register. Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSN_MASK (0xFFFFU) -#define MCAN_TSS1_TSN_SHIFT (0U) -#define MCAN_TSS1_TSN_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSN_MASK) >> MCAN_TSS1_TSN_SHIFT) - -/* Bitfield definition for register: TSS2 */ -/* - * TSP (R) - * - * Timestamp Pointer - * The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 - * depending on number_ts_g), it is incremented to 0. - * Value also signalled on output m_can_tsp[3:0]. - */ -#define MCAN_TSS2_TSP_MASK (0xFU) -#define MCAN_TSS2_TSP_SHIFT (0U) -#define MCAN_TSS2_TSP_GET(x) (((uint32_t)(x) & MCAN_TSS2_TSP_MASK) >> MCAN_TSS2_TSP_SHIFT) - -/* Bitfield definition for register: ATB */ -/* - * TB (RC) - * - * timebase for timestamp generation 31-0 - */ -#define MCAN_ATB_TB_MASK (0xFFFFFFFFUL) -#define MCAN_ATB_TB_SHIFT (0U) -#define MCAN_ATB_TB_GET(x) (((uint32_t)(x) & MCAN_ATB_TB_MASK) >> MCAN_ATB_TB_SHIFT) - -/* Bitfield definition for register: ATBH */ -/* - * TBH (RC) - * - * timebase for timestamp generation 63-32 - */ -#define MCAN_ATBH_TBH_MASK (0xFFFFFFFFUL) -#define MCAN_ATBH_TBH_SHIFT (0U) -#define MCAN_ATBH_TBH_GET(x) (((uint32_t)(x) & MCAN_ATBH_TBH_MASK) >> MCAN_ATBH_TBH_SHIFT) - -/* Bitfield definition for register: GLB_CTL */ -/* - * M_CAN_STBY (RW) - * - * m_can standby control - */ -#define MCAN_GLB_CTL_M_CAN_STBY_MASK (0x80000000UL) -#define MCAN_GLB_CTL_M_CAN_STBY_SHIFT (31U) -#define MCAN_GLB_CTL_M_CAN_STBY_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_M_CAN_STBY_SHIFT) & MCAN_GLB_CTL_M_CAN_STBY_MASK) -#define MCAN_GLB_CTL_M_CAN_STBY_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_M_CAN_STBY_MASK) >> MCAN_GLB_CTL_M_CAN_STBY_SHIFT) - -/* - * STBY_CLR_EN (RW) - * - * m_can standby clear control - * 0:controlled by software by standby bit[bit31] - * 1:auto clear standby by hardware when rx data is 0 - */ -#define MCAN_GLB_CTL_STBY_CLR_EN_MASK (0x40000000UL) -#define MCAN_GLB_CTL_STBY_CLR_EN_SHIFT (30U) -#define MCAN_GLB_CTL_STBY_CLR_EN_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) -#define MCAN_GLB_CTL_STBY_CLR_EN_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) >> MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) - -/* - * STBY_POL (RW) - * - * standby polarity selection - */ -#define MCAN_GLB_CTL_STBY_POL_MASK (0x20000000UL) -#define MCAN_GLB_CTL_STBY_POL_SHIFT (29U) -#define MCAN_GLB_CTL_STBY_POL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_POL_SHIFT) & MCAN_GLB_CTL_STBY_POL_MASK) -#define MCAN_GLB_CTL_STBY_POL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_POL_MASK) >> MCAN_GLB_CTL_STBY_POL_SHIFT) - -/* - * TSU_TBIN_SEL (RW) - * - * external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - */ -#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x3U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) - -/* Bitfield definition for register: GLB_STATUS */ -/* - * M_CAN_INT1 (R) - * - * m_can interrupt status1 - */ -#define MCAN_GLB_STATUS_M_CAN_INT1_MASK (0x8U) -#define MCAN_GLB_STATUS_M_CAN_INT1_SHIFT (3U) -#define MCAN_GLB_STATUS_M_CAN_INT1_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT1_MASK) >> MCAN_GLB_STATUS_M_CAN_INT1_SHIFT) - -/* - * M_CAN_INT0 (R) - * - * m_can interrupt status0 - */ -#define MCAN_GLB_STATUS_M_CAN_INT0_MASK (0x4U) -#define MCAN_GLB_STATUS_M_CAN_INT0_SHIFT (2U) -#define MCAN_GLB_STATUS_M_CAN_INT0_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT0_MASK) >> MCAN_GLB_STATUS_M_CAN_INT0_SHIFT) - -/* Bitfield definition for register array: MESSAGE_BUFF */ -/* - * DATA (RW) - * - * m_can message buffer - */ -#define MCAN_MESSAGE_BUFF_DATA_MASK (0xFFFFFFFFUL) -#define MCAN_MESSAGE_BUFF_DATA_SHIFT (0U) -#define MCAN_MESSAGE_BUFF_DATA_SET(x) (((uint32_t)(x) << MCAN_MESSAGE_BUFF_DATA_SHIFT) & MCAN_MESSAGE_BUFF_DATA_MASK) -#define MCAN_MESSAGE_BUFF_DATA_GET(x) (((uint32_t)(x) & MCAN_MESSAGE_BUFF_DATA_MASK) >> MCAN_MESSAGE_BUFF_DATA_SHIFT) - - - -/* TS_SEL register group index macro definition */ -#define MCAN_TS_SEL_TS_SEL0 (0UL) -#define MCAN_TS_SEL_TS_SEL1 (1UL) -#define MCAN_TS_SEL_TS_SEL2 (2UL) -#define MCAN_TS_SEL_TS_SEL3 (3UL) -#define MCAN_TS_SEL_TS_SEL4 (4UL) -#define MCAN_TS_SEL_TS_SEL5 (5UL) -#define MCAN_TS_SEL_TS_SEL6 (6UL) -#define MCAN_TS_SEL_TS_SEL7 (7UL) -#define MCAN_TS_SEL_TS_SEL8 (8UL) -#define MCAN_TS_SEL_TS_SEL9 (9UL) -#define MCAN_TS_SEL_TS_SEL10 (10UL) -#define MCAN_TS_SEL_TS_SEL11 (11UL) -#define MCAN_TS_SEL_TS_SEL12 (12UL) -#define MCAN_TS_SEL_TS_SEL13 (13UL) -#define MCAN_TS_SEL_TS_SEL14 (14UL) -#define MCAN_TS_SEL_TS_SEL15 (15UL) - -/* MESSAGE_BUFF register group index macro definition */ -#define MCAN_MESSAGE_BUFF_0 (0UL) -#define MCAN_MESSAGE_BUFF_1 (1UL) -#define MCAN_MESSAGE_BUFF_2 (2UL) -#define MCAN_MESSAGE_BUFF_3 (3UL) -#define MCAN_MESSAGE_BUFF_4 (4UL) -#define MCAN_MESSAGE_BUFF_5 (5UL) -#define MCAN_MESSAGE_BUFF_6 (6UL) -#define MCAN_MESSAGE_BUFF_7 (7UL) -#define MCAN_MESSAGE_BUFF_8 (8UL) -#define MCAN_MESSAGE_BUFF_9 (9UL) -#define MCAN_MESSAGE_BUFF_10 (10UL) -#define MCAN_MESSAGE_BUFF_11 (11UL) -#define MCAN_MESSAGE_BUFF_12 (12UL) -#define MCAN_MESSAGE_BUFF_13 (13UL) -#define MCAN_MESSAGE_BUFF_14 (14UL) -#define MCAN_MESSAGE_BUFF_15 (15UL) -#define MCAN_MESSAGE_BUFF_16 (16UL) -#define MCAN_MESSAGE_BUFF_17 (17UL) -#define MCAN_MESSAGE_BUFF_18 (18UL) -#define MCAN_MESSAGE_BUFF_19 (19UL) -#define MCAN_MESSAGE_BUFF_20 (20UL) -#define MCAN_MESSAGE_BUFF_21 (21UL) -#define MCAN_MESSAGE_BUFF_22 (22UL) -#define MCAN_MESSAGE_BUFF_23 (23UL) -#define MCAN_MESSAGE_BUFF_24 (24UL) -#define MCAN_MESSAGE_BUFF_25 (25UL) -#define MCAN_MESSAGE_BUFF_26 (26UL) -#define MCAN_MESSAGE_BUFF_27 (27UL) -#define MCAN_MESSAGE_BUFF_28 (28UL) -#define MCAN_MESSAGE_BUFF_29 (29UL) -#define MCAN_MESSAGE_BUFF_30 (30UL) -#define MCAN_MESSAGE_BUFF_31 (31UL) -#define MCAN_MESSAGE_BUFF_32 (32UL) -#define MCAN_MESSAGE_BUFF_33 (33UL) -#define MCAN_MESSAGE_BUFF_34 (34UL) -#define MCAN_MESSAGE_BUFF_35 (35UL) -#define MCAN_MESSAGE_BUFF_36 (36UL) -#define MCAN_MESSAGE_BUFF_37 (37UL) -#define MCAN_MESSAGE_BUFF_38 (38UL) -#define MCAN_MESSAGE_BUFF_39 (39UL) -#define MCAN_MESSAGE_BUFF_40 (40UL) -#define MCAN_MESSAGE_BUFF_41 (41UL) -#define MCAN_MESSAGE_BUFF_42 (42UL) -#define MCAN_MESSAGE_BUFF_43 (43UL) -#define MCAN_MESSAGE_BUFF_44 (44UL) -#define MCAN_MESSAGE_BUFF_45 (45UL) -#define MCAN_MESSAGE_BUFF_46 (46UL) -#define MCAN_MESSAGE_BUFF_47 (47UL) -#define MCAN_MESSAGE_BUFF_48 (48UL) -#define MCAN_MESSAGE_BUFF_49 (49UL) -#define MCAN_MESSAGE_BUFF_50 (50UL) -#define MCAN_MESSAGE_BUFF_51 (51UL) -#define MCAN_MESSAGE_BUFF_52 (52UL) -#define MCAN_MESSAGE_BUFF_53 (53UL) -#define MCAN_MESSAGE_BUFF_54 (54UL) -#define MCAN_MESSAGE_BUFF_55 (55UL) -#define MCAN_MESSAGE_BUFF_56 (56UL) -#define MCAN_MESSAGE_BUFF_57 (57UL) -#define MCAN_MESSAGE_BUFF_58 (58UL) -#define MCAN_MESSAGE_BUFF_59 (59UL) -#define MCAN_MESSAGE_BUFF_60 (60UL) -#define MCAN_MESSAGE_BUFF_61 (61UL) -#define MCAN_MESSAGE_BUFF_62 (62UL) -#define MCAN_MESSAGE_BUFF_63 (63UL) -#define MCAN_MESSAGE_BUFF_64 (64UL) -#define MCAN_MESSAGE_BUFF_65 (65UL) -#define MCAN_MESSAGE_BUFF_66 (66UL) -#define MCAN_MESSAGE_BUFF_67 (67UL) -#define MCAN_MESSAGE_BUFF_68 (68UL) -#define MCAN_MESSAGE_BUFF_69 (69UL) -#define MCAN_MESSAGE_BUFF_70 (70UL) -#define MCAN_MESSAGE_BUFF_71 (71UL) -#define MCAN_MESSAGE_BUFF_72 (72UL) -#define MCAN_MESSAGE_BUFF_73 (73UL) -#define MCAN_MESSAGE_BUFF_74 (74UL) -#define MCAN_MESSAGE_BUFF_75 (75UL) -#define MCAN_MESSAGE_BUFF_76 (76UL) -#define MCAN_MESSAGE_BUFF_77 (77UL) -#define MCAN_MESSAGE_BUFF_78 (78UL) -#define MCAN_MESSAGE_BUFF_79 (79UL) -#define MCAN_MESSAGE_BUFF_80 (80UL) -#define MCAN_MESSAGE_BUFF_81 (81UL) -#define MCAN_MESSAGE_BUFF_82 (82UL) -#define MCAN_MESSAGE_BUFF_83 (83UL) -#define MCAN_MESSAGE_BUFF_84 (84UL) -#define MCAN_MESSAGE_BUFF_85 (85UL) -#define MCAN_MESSAGE_BUFF_86 (86UL) -#define MCAN_MESSAGE_BUFF_87 (87UL) -#define MCAN_MESSAGE_BUFF_88 (88UL) -#define MCAN_MESSAGE_BUFF_89 (89UL) -#define MCAN_MESSAGE_BUFF_90 (90UL) -#define MCAN_MESSAGE_BUFF_91 (91UL) -#define MCAN_MESSAGE_BUFF_92 (92UL) -#define MCAN_MESSAGE_BUFF_93 (93UL) -#define MCAN_MESSAGE_BUFF_94 (94UL) -#define MCAN_MESSAGE_BUFF_95 (95UL) -#define MCAN_MESSAGE_BUFF_96 (96UL) -#define MCAN_MESSAGE_BUFF_97 (97UL) -#define MCAN_MESSAGE_BUFF_98 (98UL) -#define MCAN_MESSAGE_BUFF_99 (99UL) -#define MCAN_MESSAGE_BUFF_100 (100UL) -#define MCAN_MESSAGE_BUFF_101 (101UL) -#define MCAN_MESSAGE_BUFF_102 (102UL) -#define MCAN_MESSAGE_BUFF_103 (103UL) -#define MCAN_MESSAGE_BUFF_104 (104UL) -#define MCAN_MESSAGE_BUFF_105 (105UL) -#define MCAN_MESSAGE_BUFF_106 (106UL) -#define MCAN_MESSAGE_BUFF_107 (107UL) -#define MCAN_MESSAGE_BUFF_108 (108UL) -#define MCAN_MESSAGE_BUFF_109 (109UL) -#define MCAN_MESSAGE_BUFF_110 (110UL) -#define MCAN_MESSAGE_BUFF_111 (111UL) -#define MCAN_MESSAGE_BUFF_112 (112UL) -#define MCAN_MESSAGE_BUFF_113 (113UL) -#define MCAN_MESSAGE_BUFF_114 (114UL) -#define MCAN_MESSAGE_BUFF_115 (115UL) -#define MCAN_MESSAGE_BUFF_116 (116UL) -#define MCAN_MESSAGE_BUFF_117 (117UL) -#define MCAN_MESSAGE_BUFF_118 (118UL) -#define MCAN_MESSAGE_BUFF_119 (119UL) -#define MCAN_MESSAGE_BUFF_120 (120UL) -#define MCAN_MESSAGE_BUFF_121 (121UL) -#define MCAN_MESSAGE_BUFF_122 (122UL) -#define MCAN_MESSAGE_BUFF_123 (123UL) -#define MCAN_MESSAGE_BUFF_124 (124UL) -#define MCAN_MESSAGE_BUFF_125 (125UL) -#define MCAN_MESSAGE_BUFF_126 (126UL) -#define MCAN_MESSAGE_BUFF_127 (127UL) -#define MCAN_MESSAGE_BUFF_128 (128UL) -#define MCAN_MESSAGE_BUFF_129 (129UL) -#define MCAN_MESSAGE_BUFF_130 (130UL) -#define MCAN_MESSAGE_BUFF_131 (131UL) -#define MCAN_MESSAGE_BUFF_132 (132UL) -#define MCAN_MESSAGE_BUFF_133 (133UL) -#define MCAN_MESSAGE_BUFF_134 (134UL) -#define MCAN_MESSAGE_BUFF_135 (135UL) -#define MCAN_MESSAGE_BUFF_136 (136UL) -#define MCAN_MESSAGE_BUFF_137 (137UL) -#define MCAN_MESSAGE_BUFF_138 (138UL) -#define MCAN_MESSAGE_BUFF_139 (139UL) -#define MCAN_MESSAGE_BUFF_140 (140UL) -#define MCAN_MESSAGE_BUFF_141 (141UL) -#define MCAN_MESSAGE_BUFF_142 (142UL) -#define MCAN_MESSAGE_BUFF_143 (143UL) -#define MCAN_MESSAGE_BUFF_144 (144UL) -#define MCAN_MESSAGE_BUFF_145 (145UL) -#define MCAN_MESSAGE_BUFF_146 (146UL) -#define MCAN_MESSAGE_BUFF_147 (147UL) -#define MCAN_MESSAGE_BUFF_148 (148UL) -#define MCAN_MESSAGE_BUFF_149 (149UL) -#define MCAN_MESSAGE_BUFF_150 (150UL) -#define MCAN_MESSAGE_BUFF_151 (151UL) -#define MCAN_MESSAGE_BUFF_152 (152UL) -#define MCAN_MESSAGE_BUFF_153 (153UL) -#define MCAN_MESSAGE_BUFF_154 (154UL) -#define MCAN_MESSAGE_BUFF_155 (155UL) -#define MCAN_MESSAGE_BUFF_156 (156UL) -#define MCAN_MESSAGE_BUFF_157 (157UL) -#define MCAN_MESSAGE_BUFF_158 (158UL) -#define MCAN_MESSAGE_BUFF_159 (159UL) -#define MCAN_MESSAGE_BUFF_160 (160UL) -#define MCAN_MESSAGE_BUFF_161 (161UL) -#define MCAN_MESSAGE_BUFF_162 (162UL) -#define MCAN_MESSAGE_BUFF_163 (163UL) -#define MCAN_MESSAGE_BUFF_164 (164UL) -#define MCAN_MESSAGE_BUFF_165 (165UL) -#define MCAN_MESSAGE_BUFF_166 (166UL) -#define MCAN_MESSAGE_BUFF_167 (167UL) -#define MCAN_MESSAGE_BUFF_168 (168UL) -#define MCAN_MESSAGE_BUFF_169 (169UL) -#define MCAN_MESSAGE_BUFF_170 (170UL) -#define MCAN_MESSAGE_BUFF_171 (171UL) -#define MCAN_MESSAGE_BUFF_172 (172UL) -#define MCAN_MESSAGE_BUFF_173 (173UL) -#define MCAN_MESSAGE_BUFF_174 (174UL) -#define MCAN_MESSAGE_BUFF_175 (175UL) -#define MCAN_MESSAGE_BUFF_176 (176UL) -#define MCAN_MESSAGE_BUFF_177 (177UL) -#define MCAN_MESSAGE_BUFF_178 (178UL) -#define MCAN_MESSAGE_BUFF_179 (179UL) -#define MCAN_MESSAGE_BUFF_180 (180UL) -#define MCAN_MESSAGE_BUFF_181 (181UL) -#define MCAN_MESSAGE_BUFF_182 (182UL) -#define MCAN_MESSAGE_BUFF_183 (183UL) -#define MCAN_MESSAGE_BUFF_184 (184UL) -#define MCAN_MESSAGE_BUFF_185 (185UL) -#define MCAN_MESSAGE_BUFF_186 (186UL) -#define MCAN_MESSAGE_BUFF_187 (187UL) -#define MCAN_MESSAGE_BUFF_188 (188UL) -#define MCAN_MESSAGE_BUFF_189 (189UL) -#define MCAN_MESSAGE_BUFF_190 (190UL) -#define MCAN_MESSAGE_BUFF_191 (191UL) -#define MCAN_MESSAGE_BUFF_192 (192UL) -#define MCAN_MESSAGE_BUFF_193 (193UL) -#define MCAN_MESSAGE_BUFF_194 (194UL) -#define MCAN_MESSAGE_BUFF_195 (195UL) -#define MCAN_MESSAGE_BUFF_196 (196UL) -#define MCAN_MESSAGE_BUFF_197 (197UL) -#define MCAN_MESSAGE_BUFF_198 (198UL) -#define MCAN_MESSAGE_BUFF_199 (199UL) -#define MCAN_MESSAGE_BUFF_200 (200UL) -#define MCAN_MESSAGE_BUFF_201 (201UL) -#define MCAN_MESSAGE_BUFF_202 (202UL) -#define MCAN_MESSAGE_BUFF_203 (203UL) -#define MCAN_MESSAGE_BUFF_204 (204UL) -#define MCAN_MESSAGE_BUFF_205 (205UL) -#define MCAN_MESSAGE_BUFF_206 (206UL) -#define MCAN_MESSAGE_BUFF_207 (207UL) -#define MCAN_MESSAGE_BUFF_208 (208UL) -#define MCAN_MESSAGE_BUFF_209 (209UL) -#define MCAN_MESSAGE_BUFF_210 (210UL) -#define MCAN_MESSAGE_BUFF_211 (211UL) -#define MCAN_MESSAGE_BUFF_212 (212UL) -#define MCAN_MESSAGE_BUFF_213 (213UL) -#define MCAN_MESSAGE_BUFF_214 (214UL) -#define MCAN_MESSAGE_BUFF_215 (215UL) -#define MCAN_MESSAGE_BUFF_216 (216UL) -#define MCAN_MESSAGE_BUFF_217 (217UL) -#define MCAN_MESSAGE_BUFF_218 (218UL) -#define MCAN_MESSAGE_BUFF_219 (219UL) -#define MCAN_MESSAGE_BUFF_220 (220UL) -#define MCAN_MESSAGE_BUFF_221 (221UL) -#define MCAN_MESSAGE_BUFF_222 (222UL) -#define MCAN_MESSAGE_BUFF_223 (223UL) -#define MCAN_MESSAGE_BUFF_224 (224UL) -#define MCAN_MESSAGE_BUFF_225 (225UL) -#define MCAN_MESSAGE_BUFF_226 (226UL) -#define MCAN_MESSAGE_BUFF_227 (227UL) -#define MCAN_MESSAGE_BUFF_228 (228UL) -#define MCAN_MESSAGE_BUFF_229 (229UL) -#define MCAN_MESSAGE_BUFF_230 (230UL) -#define MCAN_MESSAGE_BUFF_231 (231UL) -#define MCAN_MESSAGE_BUFF_232 (232UL) -#define MCAN_MESSAGE_BUFF_233 (233UL) -#define MCAN_MESSAGE_BUFF_234 (234UL) -#define MCAN_MESSAGE_BUFF_235 (235UL) -#define MCAN_MESSAGE_BUFF_236 (236UL) -#define MCAN_MESSAGE_BUFF_237 (237UL) -#define MCAN_MESSAGE_BUFF_238 (238UL) -#define MCAN_MESSAGE_BUFF_239 (239UL) -#define MCAN_MESSAGE_BUFF_240 (240UL) -#define MCAN_MESSAGE_BUFF_241 (241UL) -#define MCAN_MESSAGE_BUFF_242 (242UL) -#define MCAN_MESSAGE_BUFF_243 (243UL) -#define MCAN_MESSAGE_BUFF_244 (244UL) -#define MCAN_MESSAGE_BUFF_245 (245UL) -#define MCAN_MESSAGE_BUFF_246 (246UL) -#define MCAN_MESSAGE_BUFF_247 (247UL) -#define MCAN_MESSAGE_BUFF_248 (248UL) -#define MCAN_MESSAGE_BUFF_249 (249UL) -#define MCAN_MESSAGE_BUFF_250 (250UL) -#define MCAN_MESSAGE_BUFF_251 (251UL) -#define MCAN_MESSAGE_BUFF_252 (252UL) -#define MCAN_MESSAGE_BUFF_253 (253UL) -#define MCAN_MESSAGE_BUFF_254 (254UL) -#define MCAN_MESSAGE_BUFF_255 (255UL) -#define MCAN_MESSAGE_BUFF_256 (256UL) -#define MCAN_MESSAGE_BUFF_257 (257UL) -#define MCAN_MESSAGE_BUFF_258 (258UL) -#define MCAN_MESSAGE_BUFF_259 (259UL) -#define MCAN_MESSAGE_BUFF_260 (260UL) -#define MCAN_MESSAGE_BUFF_261 (261UL) -#define MCAN_MESSAGE_BUFF_262 (262UL) -#define MCAN_MESSAGE_BUFF_263 (263UL) -#define MCAN_MESSAGE_BUFF_264 (264UL) -#define MCAN_MESSAGE_BUFF_265 (265UL) -#define MCAN_MESSAGE_BUFF_266 (266UL) -#define MCAN_MESSAGE_BUFF_267 (267UL) -#define MCAN_MESSAGE_BUFF_268 (268UL) -#define MCAN_MESSAGE_BUFF_269 (269UL) -#define MCAN_MESSAGE_BUFF_270 (270UL) -#define MCAN_MESSAGE_BUFF_271 (271UL) -#define MCAN_MESSAGE_BUFF_272 (272UL) -#define MCAN_MESSAGE_BUFF_273 (273UL) -#define MCAN_MESSAGE_BUFF_274 (274UL) -#define MCAN_MESSAGE_BUFF_275 (275UL) -#define MCAN_MESSAGE_BUFF_276 (276UL) -#define MCAN_MESSAGE_BUFF_277 (277UL) -#define MCAN_MESSAGE_BUFF_278 (278UL) -#define MCAN_MESSAGE_BUFF_279 (279UL) -#define MCAN_MESSAGE_BUFF_280 (280UL) -#define MCAN_MESSAGE_BUFF_281 (281UL) -#define MCAN_MESSAGE_BUFF_282 (282UL) -#define MCAN_MESSAGE_BUFF_283 (283UL) -#define MCAN_MESSAGE_BUFF_284 (284UL) -#define MCAN_MESSAGE_BUFF_285 (285UL) -#define MCAN_MESSAGE_BUFF_286 (286UL) -#define MCAN_MESSAGE_BUFF_287 (287UL) -#define MCAN_MESSAGE_BUFF_288 (288UL) -#define MCAN_MESSAGE_BUFF_289 (289UL) -#define MCAN_MESSAGE_BUFF_290 (290UL) -#define MCAN_MESSAGE_BUFF_291 (291UL) -#define MCAN_MESSAGE_BUFF_292 (292UL) -#define MCAN_MESSAGE_BUFF_293 (293UL) -#define MCAN_MESSAGE_BUFF_294 (294UL) -#define MCAN_MESSAGE_BUFF_295 (295UL) -#define MCAN_MESSAGE_BUFF_296 (296UL) -#define MCAN_MESSAGE_BUFF_297 (297UL) -#define MCAN_MESSAGE_BUFF_298 (298UL) -#define MCAN_MESSAGE_BUFF_299 (299UL) -#define MCAN_MESSAGE_BUFF_300 (300UL) -#define MCAN_MESSAGE_BUFF_301 (301UL) -#define MCAN_MESSAGE_BUFF_302 (302UL) -#define MCAN_MESSAGE_BUFF_303 (303UL) -#define MCAN_MESSAGE_BUFF_304 (304UL) -#define MCAN_MESSAGE_BUFF_305 (305UL) -#define MCAN_MESSAGE_BUFF_306 (306UL) -#define MCAN_MESSAGE_BUFF_307 (307UL) -#define MCAN_MESSAGE_BUFF_308 (308UL) -#define MCAN_MESSAGE_BUFF_309 (309UL) -#define MCAN_MESSAGE_BUFF_310 (310UL) -#define MCAN_MESSAGE_BUFF_311 (311UL) -#define MCAN_MESSAGE_BUFF_312 (312UL) -#define MCAN_MESSAGE_BUFF_313 (313UL) -#define MCAN_MESSAGE_BUFF_314 (314UL) -#define MCAN_MESSAGE_BUFF_315 (315UL) -#define MCAN_MESSAGE_BUFF_316 (316UL) -#define MCAN_MESSAGE_BUFF_317 (317UL) -#define MCAN_MESSAGE_BUFF_318 (318UL) -#define MCAN_MESSAGE_BUFF_319 (319UL) -#define MCAN_MESSAGE_BUFF_320 (320UL) -#define MCAN_MESSAGE_BUFF_321 (321UL) -#define MCAN_MESSAGE_BUFF_322 (322UL) -#define MCAN_MESSAGE_BUFF_323 (323UL) -#define MCAN_MESSAGE_BUFF_324 (324UL) -#define MCAN_MESSAGE_BUFF_325 (325UL) -#define MCAN_MESSAGE_BUFF_326 (326UL) -#define MCAN_MESSAGE_BUFF_327 (327UL) -#define MCAN_MESSAGE_BUFF_328 (328UL) -#define MCAN_MESSAGE_BUFF_329 (329UL) -#define MCAN_MESSAGE_BUFF_330 (330UL) -#define MCAN_MESSAGE_BUFF_331 (331UL) -#define MCAN_MESSAGE_BUFF_332 (332UL) -#define MCAN_MESSAGE_BUFF_333 (333UL) -#define MCAN_MESSAGE_BUFF_334 (334UL) -#define MCAN_MESSAGE_BUFF_335 (335UL) -#define MCAN_MESSAGE_BUFF_336 (336UL) -#define MCAN_MESSAGE_BUFF_337 (337UL) -#define MCAN_MESSAGE_BUFF_338 (338UL) -#define MCAN_MESSAGE_BUFF_339 (339UL) -#define MCAN_MESSAGE_BUFF_340 (340UL) -#define MCAN_MESSAGE_BUFF_341 (341UL) -#define MCAN_MESSAGE_BUFF_342 (342UL) -#define MCAN_MESSAGE_BUFF_343 (343UL) -#define MCAN_MESSAGE_BUFF_344 (344UL) -#define MCAN_MESSAGE_BUFF_345 (345UL) -#define MCAN_MESSAGE_BUFF_346 (346UL) -#define MCAN_MESSAGE_BUFF_347 (347UL) -#define MCAN_MESSAGE_BUFF_348 (348UL) -#define MCAN_MESSAGE_BUFF_349 (349UL) -#define MCAN_MESSAGE_BUFF_350 (350UL) -#define MCAN_MESSAGE_BUFF_351 (351UL) -#define MCAN_MESSAGE_BUFF_352 (352UL) -#define MCAN_MESSAGE_BUFF_353 (353UL) -#define MCAN_MESSAGE_BUFF_354 (354UL) -#define MCAN_MESSAGE_BUFF_355 (355UL) -#define MCAN_MESSAGE_BUFF_356 (356UL) -#define MCAN_MESSAGE_BUFF_357 (357UL) -#define MCAN_MESSAGE_BUFF_358 (358UL) -#define MCAN_MESSAGE_BUFF_359 (359UL) -#define MCAN_MESSAGE_BUFF_360 (360UL) -#define MCAN_MESSAGE_BUFF_361 (361UL) -#define MCAN_MESSAGE_BUFF_362 (362UL) -#define MCAN_MESSAGE_BUFF_363 (363UL) -#define MCAN_MESSAGE_BUFF_364 (364UL) -#define MCAN_MESSAGE_BUFF_365 (365UL) -#define MCAN_MESSAGE_BUFF_366 (366UL) -#define MCAN_MESSAGE_BUFF_367 (367UL) -#define MCAN_MESSAGE_BUFF_368 (368UL) -#define MCAN_MESSAGE_BUFF_369 (369UL) -#define MCAN_MESSAGE_BUFF_370 (370UL) -#define MCAN_MESSAGE_BUFF_371 (371UL) -#define MCAN_MESSAGE_BUFF_372 (372UL) -#define MCAN_MESSAGE_BUFF_373 (373UL) -#define MCAN_MESSAGE_BUFF_374 (374UL) -#define MCAN_MESSAGE_BUFF_375 (375UL) -#define MCAN_MESSAGE_BUFF_376 (376UL) -#define MCAN_MESSAGE_BUFF_377 (377UL) -#define MCAN_MESSAGE_BUFF_378 (378UL) -#define MCAN_MESSAGE_BUFF_379 (379UL) -#define MCAN_MESSAGE_BUFF_380 (380UL) -#define MCAN_MESSAGE_BUFF_381 (381UL) -#define MCAN_MESSAGE_BUFF_382 (382UL) -#define MCAN_MESSAGE_BUFF_383 (383UL) -#define MCAN_MESSAGE_BUFF_384 (384UL) -#define MCAN_MESSAGE_BUFF_385 (385UL) -#define MCAN_MESSAGE_BUFF_386 (386UL) -#define MCAN_MESSAGE_BUFF_387 (387UL) -#define MCAN_MESSAGE_BUFF_388 (388UL) -#define MCAN_MESSAGE_BUFF_389 (389UL) -#define MCAN_MESSAGE_BUFF_390 (390UL) -#define MCAN_MESSAGE_BUFF_391 (391UL) -#define MCAN_MESSAGE_BUFF_392 (392UL) -#define MCAN_MESSAGE_BUFF_393 (393UL) -#define MCAN_MESSAGE_BUFF_394 (394UL) -#define MCAN_MESSAGE_BUFF_395 (395UL) -#define MCAN_MESSAGE_BUFF_396 (396UL) -#define MCAN_MESSAGE_BUFF_397 (397UL) -#define MCAN_MESSAGE_BUFF_398 (398UL) -#define MCAN_MESSAGE_BUFF_399 (399UL) -#define MCAN_MESSAGE_BUFF_400 (400UL) -#define MCAN_MESSAGE_BUFF_401 (401UL) -#define MCAN_MESSAGE_BUFF_402 (402UL) -#define MCAN_MESSAGE_BUFF_403 (403UL) -#define MCAN_MESSAGE_BUFF_404 (404UL) -#define MCAN_MESSAGE_BUFF_405 (405UL) -#define MCAN_MESSAGE_BUFF_406 (406UL) -#define MCAN_MESSAGE_BUFF_407 (407UL) -#define MCAN_MESSAGE_BUFF_408 (408UL) -#define MCAN_MESSAGE_BUFF_409 (409UL) -#define MCAN_MESSAGE_BUFF_410 (410UL) -#define MCAN_MESSAGE_BUFF_411 (411UL) -#define MCAN_MESSAGE_BUFF_412 (412UL) -#define MCAN_MESSAGE_BUFF_413 (413UL) -#define MCAN_MESSAGE_BUFF_414 (414UL) -#define MCAN_MESSAGE_BUFF_415 (415UL) -#define MCAN_MESSAGE_BUFF_416 (416UL) -#define MCAN_MESSAGE_BUFF_417 (417UL) -#define MCAN_MESSAGE_BUFF_418 (418UL) -#define MCAN_MESSAGE_BUFF_419 (419UL) -#define MCAN_MESSAGE_BUFF_420 (420UL) -#define MCAN_MESSAGE_BUFF_421 (421UL) -#define MCAN_MESSAGE_BUFF_422 (422UL) -#define MCAN_MESSAGE_BUFF_423 (423UL) -#define MCAN_MESSAGE_BUFF_424 (424UL) -#define MCAN_MESSAGE_BUFF_425 (425UL) -#define MCAN_MESSAGE_BUFF_426 (426UL) -#define MCAN_MESSAGE_BUFF_427 (427UL) -#define MCAN_MESSAGE_BUFF_428 (428UL) -#define MCAN_MESSAGE_BUFF_429 (429UL) -#define MCAN_MESSAGE_BUFF_430 (430UL) -#define MCAN_MESSAGE_BUFF_431 (431UL) -#define MCAN_MESSAGE_BUFF_432 (432UL) -#define MCAN_MESSAGE_BUFF_433 (433UL) -#define MCAN_MESSAGE_BUFF_434 (434UL) -#define MCAN_MESSAGE_BUFF_435 (435UL) -#define MCAN_MESSAGE_BUFF_436 (436UL) -#define MCAN_MESSAGE_BUFF_437 (437UL) -#define MCAN_MESSAGE_BUFF_438 (438UL) -#define MCAN_MESSAGE_BUFF_439 (439UL) -#define MCAN_MESSAGE_BUFF_440 (440UL) -#define MCAN_MESSAGE_BUFF_441 (441UL) -#define MCAN_MESSAGE_BUFF_442 (442UL) -#define MCAN_MESSAGE_BUFF_443 (443UL) -#define MCAN_MESSAGE_BUFF_444 (444UL) -#define MCAN_MESSAGE_BUFF_445 (445UL) -#define MCAN_MESSAGE_BUFF_446 (446UL) -#define MCAN_MESSAGE_BUFF_447 (447UL) -#define MCAN_MESSAGE_BUFF_448 (448UL) -#define MCAN_MESSAGE_BUFF_449 (449UL) -#define MCAN_MESSAGE_BUFF_450 (450UL) -#define MCAN_MESSAGE_BUFF_451 (451UL) -#define MCAN_MESSAGE_BUFF_452 (452UL) -#define MCAN_MESSAGE_BUFF_453 (453UL) -#define MCAN_MESSAGE_BUFF_454 (454UL) -#define MCAN_MESSAGE_BUFF_455 (455UL) -#define MCAN_MESSAGE_BUFF_456 (456UL) -#define MCAN_MESSAGE_BUFF_457 (457UL) -#define MCAN_MESSAGE_BUFF_458 (458UL) -#define MCAN_MESSAGE_BUFF_459 (459UL) -#define MCAN_MESSAGE_BUFF_460 (460UL) -#define MCAN_MESSAGE_BUFF_461 (461UL) -#define MCAN_MESSAGE_BUFF_462 (462UL) -#define MCAN_MESSAGE_BUFF_463 (463UL) -#define MCAN_MESSAGE_BUFF_464 (464UL) -#define MCAN_MESSAGE_BUFF_465 (465UL) -#define MCAN_MESSAGE_BUFF_466 (466UL) -#define MCAN_MESSAGE_BUFF_467 (467UL) -#define MCAN_MESSAGE_BUFF_468 (468UL) -#define MCAN_MESSAGE_BUFF_469 (469UL) -#define MCAN_MESSAGE_BUFF_470 (470UL) -#define MCAN_MESSAGE_BUFF_471 (471UL) -#define MCAN_MESSAGE_BUFF_472 (472UL) -#define MCAN_MESSAGE_BUFF_473 (473UL) -#define MCAN_MESSAGE_BUFF_474 (474UL) -#define MCAN_MESSAGE_BUFF_475 (475UL) -#define MCAN_MESSAGE_BUFF_476 (476UL) -#define MCAN_MESSAGE_BUFF_477 (477UL) -#define MCAN_MESSAGE_BUFF_478 (478UL) -#define MCAN_MESSAGE_BUFF_479 (479UL) -#define MCAN_MESSAGE_BUFF_480 (480UL) -#define MCAN_MESSAGE_BUFF_481 (481UL) -#define MCAN_MESSAGE_BUFF_482 (482UL) -#define MCAN_MESSAGE_BUFF_483 (483UL) -#define MCAN_MESSAGE_BUFF_484 (484UL) -#define MCAN_MESSAGE_BUFF_485 (485UL) -#define MCAN_MESSAGE_BUFF_486 (486UL) -#define MCAN_MESSAGE_BUFF_487 (487UL) -#define MCAN_MESSAGE_BUFF_488 (488UL) -#define MCAN_MESSAGE_BUFF_489 (489UL) -#define MCAN_MESSAGE_BUFF_490 (490UL) -#define MCAN_MESSAGE_BUFF_491 (491UL) -#define MCAN_MESSAGE_BUFF_492 (492UL) -#define MCAN_MESSAGE_BUFF_493 (493UL) -#define MCAN_MESSAGE_BUFF_494 (494UL) -#define MCAN_MESSAGE_BUFF_495 (495UL) -#define MCAN_MESSAGE_BUFF_496 (496UL) -#define MCAN_MESSAGE_BUFF_497 (497UL) -#define MCAN_MESSAGE_BUFF_498 (498UL) -#define MCAN_MESSAGE_BUFF_499 (499UL) -#define MCAN_MESSAGE_BUFF_500 (500UL) -#define MCAN_MESSAGE_BUFF_501 (501UL) -#define MCAN_MESSAGE_BUFF_502 (502UL) -#define MCAN_MESSAGE_BUFF_503 (503UL) -#define MCAN_MESSAGE_BUFF_504 (504UL) -#define MCAN_MESSAGE_BUFF_505 (505UL) -#define MCAN_MESSAGE_BUFF_506 (506UL) -#define MCAN_MESSAGE_BUFF_507 (507UL) -#define MCAN_MESSAGE_BUFF_508 (508UL) -#define MCAN_MESSAGE_BUFF_509 (509UL) -#define MCAN_MESSAGE_BUFF_510 (510UL) -#define MCAN_MESSAGE_BUFF_511 (511UL) -#define MCAN_MESSAGE_BUFF_512 (512UL) -#define MCAN_MESSAGE_BUFF_513 (513UL) -#define MCAN_MESSAGE_BUFF_514 (514UL) -#define MCAN_MESSAGE_BUFF_515 (515UL) -#define MCAN_MESSAGE_BUFF_516 (516UL) -#define MCAN_MESSAGE_BUFF_517 (517UL) -#define MCAN_MESSAGE_BUFF_518 (518UL) -#define MCAN_MESSAGE_BUFF_519 (519UL) -#define MCAN_MESSAGE_BUFF_520 (520UL) -#define MCAN_MESSAGE_BUFF_521 (521UL) -#define MCAN_MESSAGE_BUFF_522 (522UL) -#define MCAN_MESSAGE_BUFF_523 (523UL) -#define MCAN_MESSAGE_BUFF_524 (524UL) -#define MCAN_MESSAGE_BUFF_525 (525UL) -#define MCAN_MESSAGE_BUFF_526 (526UL) -#define MCAN_MESSAGE_BUFF_527 (527UL) -#define MCAN_MESSAGE_BUFF_528 (528UL) -#define MCAN_MESSAGE_BUFF_529 (529UL) -#define MCAN_MESSAGE_BUFF_530 (530UL) -#define MCAN_MESSAGE_BUFF_531 (531UL) -#define MCAN_MESSAGE_BUFF_532 (532UL) -#define MCAN_MESSAGE_BUFF_533 (533UL) -#define MCAN_MESSAGE_BUFF_534 (534UL) -#define MCAN_MESSAGE_BUFF_535 (535UL) -#define MCAN_MESSAGE_BUFF_536 (536UL) -#define MCAN_MESSAGE_BUFF_537 (537UL) -#define MCAN_MESSAGE_BUFF_538 (538UL) -#define MCAN_MESSAGE_BUFF_539 (539UL) -#define MCAN_MESSAGE_BUFF_540 (540UL) -#define MCAN_MESSAGE_BUFF_541 (541UL) -#define MCAN_MESSAGE_BUFF_542 (542UL) -#define MCAN_MESSAGE_BUFF_543 (543UL) -#define MCAN_MESSAGE_BUFF_544 (544UL) -#define MCAN_MESSAGE_BUFF_545 (545UL) -#define MCAN_MESSAGE_BUFF_546 (546UL) -#define MCAN_MESSAGE_BUFF_547 (547UL) -#define MCAN_MESSAGE_BUFF_548 (548UL) -#define MCAN_MESSAGE_BUFF_549 (549UL) -#define MCAN_MESSAGE_BUFF_550 (550UL) -#define MCAN_MESSAGE_BUFF_551 (551UL) -#define MCAN_MESSAGE_BUFF_552 (552UL) -#define MCAN_MESSAGE_BUFF_553 (553UL) -#define MCAN_MESSAGE_BUFF_554 (554UL) -#define MCAN_MESSAGE_BUFF_555 (555UL) -#define MCAN_MESSAGE_BUFF_556 (556UL) -#define MCAN_MESSAGE_BUFF_557 (557UL) -#define MCAN_MESSAGE_BUFF_558 (558UL) -#define MCAN_MESSAGE_BUFF_559 (559UL) -#define MCAN_MESSAGE_BUFF_560 (560UL) -#define MCAN_MESSAGE_BUFF_561 (561UL) -#define MCAN_MESSAGE_BUFF_562 (562UL) -#define MCAN_MESSAGE_BUFF_563 (563UL) -#define MCAN_MESSAGE_BUFF_564 (564UL) -#define MCAN_MESSAGE_BUFF_565 (565UL) -#define MCAN_MESSAGE_BUFF_566 (566UL) -#define MCAN_MESSAGE_BUFF_567 (567UL) -#define MCAN_MESSAGE_BUFF_568 (568UL) -#define MCAN_MESSAGE_BUFF_569 (569UL) -#define MCAN_MESSAGE_BUFF_570 (570UL) -#define MCAN_MESSAGE_BUFF_571 (571UL) -#define MCAN_MESSAGE_BUFF_572 (572UL) -#define MCAN_MESSAGE_BUFF_573 (573UL) -#define MCAN_MESSAGE_BUFF_574 (574UL) -#define MCAN_MESSAGE_BUFF_575 (575UL) -#define MCAN_MESSAGE_BUFF_576 (576UL) -#define MCAN_MESSAGE_BUFF_577 (577UL) -#define MCAN_MESSAGE_BUFF_578 (578UL) -#define MCAN_MESSAGE_BUFF_579 (579UL) -#define MCAN_MESSAGE_BUFF_580 (580UL) -#define MCAN_MESSAGE_BUFF_581 (581UL) -#define MCAN_MESSAGE_BUFF_582 (582UL) -#define MCAN_MESSAGE_BUFF_583 (583UL) -#define MCAN_MESSAGE_BUFF_584 (584UL) -#define MCAN_MESSAGE_BUFF_585 (585UL) -#define MCAN_MESSAGE_BUFF_586 (586UL) -#define MCAN_MESSAGE_BUFF_587 (587UL) -#define MCAN_MESSAGE_BUFF_588 (588UL) -#define MCAN_MESSAGE_BUFF_589 (589UL) -#define MCAN_MESSAGE_BUFF_590 (590UL) -#define MCAN_MESSAGE_BUFF_591 (591UL) -#define MCAN_MESSAGE_BUFF_592 (592UL) -#define MCAN_MESSAGE_BUFF_593 (593UL) -#define MCAN_MESSAGE_BUFF_594 (594UL) -#define MCAN_MESSAGE_BUFF_595 (595UL) -#define MCAN_MESSAGE_BUFF_596 (596UL) -#define MCAN_MESSAGE_BUFF_597 (597UL) -#define MCAN_MESSAGE_BUFF_598 (598UL) -#define MCAN_MESSAGE_BUFF_599 (599UL) -#define MCAN_MESSAGE_BUFF_600 (600UL) -#define MCAN_MESSAGE_BUFF_601 (601UL) -#define MCAN_MESSAGE_BUFF_602 (602UL) -#define MCAN_MESSAGE_BUFF_603 (603UL) -#define MCAN_MESSAGE_BUFF_604 (604UL) -#define MCAN_MESSAGE_BUFF_605 (605UL) -#define MCAN_MESSAGE_BUFF_606 (606UL) -#define MCAN_MESSAGE_BUFF_607 (607UL) -#define MCAN_MESSAGE_BUFF_608 (608UL) -#define MCAN_MESSAGE_BUFF_609 (609UL) -#define MCAN_MESSAGE_BUFF_610 (610UL) -#define MCAN_MESSAGE_BUFF_611 (611UL) -#define MCAN_MESSAGE_BUFF_612 (612UL) -#define MCAN_MESSAGE_BUFF_613 (613UL) -#define MCAN_MESSAGE_BUFF_614 (614UL) -#define MCAN_MESSAGE_BUFF_615 (615UL) -#define MCAN_MESSAGE_BUFF_616 (616UL) -#define MCAN_MESSAGE_BUFF_617 (617UL) -#define MCAN_MESSAGE_BUFF_618 (618UL) -#define MCAN_MESSAGE_BUFF_619 (619UL) -#define MCAN_MESSAGE_BUFF_620 (620UL) -#define MCAN_MESSAGE_BUFF_621 (621UL) -#define MCAN_MESSAGE_BUFF_622 (622UL) -#define MCAN_MESSAGE_BUFF_623 (623UL) -#define MCAN_MESSAGE_BUFF_624 (624UL) -#define MCAN_MESSAGE_BUFF_625 (625UL) -#define MCAN_MESSAGE_BUFF_626 (626UL) -#define MCAN_MESSAGE_BUFF_627 (627UL) -#define MCAN_MESSAGE_BUFF_628 (628UL) -#define MCAN_MESSAGE_BUFF_629 (629UL) -#define MCAN_MESSAGE_BUFF_630 (630UL) -#define MCAN_MESSAGE_BUFF_631 (631UL) -#define MCAN_MESSAGE_BUFF_632 (632UL) -#define MCAN_MESSAGE_BUFF_633 (633UL) -#define MCAN_MESSAGE_BUFF_634 (634UL) -#define MCAN_MESSAGE_BUFF_635 (635UL) -#define MCAN_MESSAGE_BUFF_636 (636UL) -#define MCAN_MESSAGE_BUFF_637 (637UL) -#define MCAN_MESSAGE_BUFF_638 (638UL) -#define MCAN_MESSAGE_BUFF_639 (639UL) - - -#endif /* HPM_MCAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mchtmr_regs.h deleted file mode 100644 index d9dfe58a7b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mchtmr_regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCHTMR_H -#define HPM_MCHTMR_H - -typedef struct { - __RW uint64_t MTIME; /* 0x0: Machine Time */ - __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ -} MCHTMR_Type; - - -/* Bitfield definition for register: MTIME */ -/* - * MTIME (RW) - * - * Machine time - */ -#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIME_MTIME_SHIFT (0U) -#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) -#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) - -/* Bitfield definition for register: MTIMECMP */ -/* - * MTIMECMP (RW) - * - * Machine time compare - */ -#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) -#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) -#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) - - - - -#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mono_regs.h deleted file mode 100644 index 2c6c3a3d2fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_mono_regs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MONO_H -#define HPM_MONO_H - -typedef struct { - __RW uint32_t MONOL; /* 0x0: Low part of monotonic counter */ - __RW uint32_t MONOH; /* 0x4: High part of monotonic counter */ -} MONO_Type; - - -/* Bitfield definition for register: MONOL */ -/* - * COUNTER (RW) - * - * low part of monotonica counter, write to this counter will cause counter increase by 1 - */ -#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) -#define MONO_MONOL_COUNTER_SHIFT (0U) -#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) -#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) - -/* Bitfield definition for register: MONOH */ -/* - * EPOCH (RW) - * - * Fuse value for high part of monotonica - */ -#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) -#define MONO_MONOH_EPOCH_SHIFT (16U) -#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) -#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) - -/* - * COUNTER (RW) - * - * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - */ -#define MONO_MONOH_COUNTER_MASK (0xFFFFU) -#define MONO_MONOH_COUNTER_SHIFT (0U) -#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) -#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) - - - - -#endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_otp_regs.h deleted file mode 100644 index feb5f9c2efe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_otp_regs.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OTP_H -#define HPM_OTP_H - -typedef struct { - __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ - __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ - __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ - __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ - __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ - __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ - __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ - __RW uint32_t DATA; /* 0x804: DATA */ - __RW uint32_t ADDR; /* 0x808: ADDR */ - __RW uint32_t CMD; /* 0x80C: CMD */ - __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ - __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ - __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ - __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ - __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ - __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ - __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ - __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ -} OTP_Type; - - -/* Bitfield definition for register array: SHADOW */ -/* - * SHADOW (RW) - * - * shadow register of fuse for pmic area - * for PMIC, index valid for 0-15, for SOC index valid for 16-128 - */ -#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_SHADOW_SHIFT (0U) -#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) -#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) - -/* Bitfield definition for register array: SHADOW_LOCK */ -/* - * LOCK (RW) - * - * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) -#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) -#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register array: FUSE */ -/* - * FUSE (RW) - * - * fuse array, valid in PMIC part only - * read operation will read out value in fuse array - * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - */ -#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_FUSE_SHIFT (0U) -#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) -#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) - -/* Bitfield definition for register array: FUSE_LOCK */ -/* - * LOCK (RW) - * - * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) -#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) -#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK (RW) - * - * unlock word for fuse array operation - * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. - * Please make sure 24M crystal is running and 2.5V LDO working properly - */ -#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) -#define OTP_UNLOCK_UNLOCK_SHIFT (0U) -#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) -#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * data register for non-blocking access - * this register hold dat read from fuse array or data to by programmed to fuse array - */ -#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) -#define OTP_DATA_DATA_SHIFT (0U) -#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) -#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * word address to be read or write - */ -#define OTP_ADDR_ADDR_MASK (0x7FU) -#define OTP_ADDR_ADDR_SHIFT (0U) -#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) -#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * command to access fure array - * "BLOW" will update fuse word at ADDR to value hold in DATA - * "READ" will fetch fuse value in at ADDR to DATA register - */ -#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) -#define OTP_CMD_CMD_SHIFT (0U) -#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) -#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) - -/* Bitfield definition for register: LOAD_REQ */ -/* - * REQUEST (RW) - * - * reload request for 4 regions - * bit0: region0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) -#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) -#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) -#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) - -/* Bitfield definition for register: LOAD_COMP */ -/* - * COMPLETE (RW) - * - * reload complete sign for 4 regions - * bit0: region 0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) -#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) -#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) -#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) - -/* Bitfield definition for register array: REGION */ -/* - * STOP (RW) - * - * stop address of load region, fuse word at end address will NOT be reloaded - * region0: fixed at 8 - * region1: fixed at 16 - * region2: fixed at 0, - * region3: usrer configurable - */ -#define OTP_REGION_STOP_MASK (0x7F00U) -#define OTP_REGION_STOP_SHIFT (8U) -#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) -#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) - -/* - * START (RW) - * - * start address of load region, fuse word at start address will be reloaded - * region0: fixed at 0 - * region1: fixed at 8 - * region2: fixed at 16, - * region3: usrer configurable - */ -#define OTP_REGION_START_MASK (0x7FU) -#define OTP_REGION_START_SHIFT (0U) -#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) -#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) - -/* Bitfield definition for register: INT_FLAG */ -/* - * WRITE (RW) - * - * fuse write flag, write 1 to clear - * 0: fuse is not written or writing - * 1: value in DATA register is programmed into fuse - */ -#define OTP_INT_FLAG_WRITE_MASK (0x4U) -#define OTP_INT_FLAG_WRITE_SHIFT (2U) -#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) -#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read flag, write 1 to clear - * 0: fuse is not read or reading - * 1: fuse value is put in DATA register - */ -#define OTP_INT_FLAG_READ_MASK (0x2U) -#define OTP_INT_FLAG_READ_SHIFT (1U) -#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) -#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load flag, write 1 to clear - * 0: fuse is not loaded or loading - * 1: fuse loaded - */ -#define OTP_INT_FLAG_LOAD_MASK (0x1U) -#define OTP_INT_FLAG_LOAD_SHIFT (0U) -#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) -#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRITE (RW) - * - * fuse write interrupt enable - * 0: fuse write interrupt is not enable - * 1: fuse write interrupt is enable - */ -#define OTP_INT_EN_WRITE_MASK (0x4U) -#define OTP_INT_EN_WRITE_SHIFT (2U) -#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) -#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read interrupt enable - * 0: fuse read interrupt is not enable - * 1: fuse read interrupt is enable - */ -#define OTP_INT_EN_READ_MASK (0x2U) -#define OTP_INT_EN_READ_SHIFT (1U) -#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) -#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load interrupt enable - * 0: fuse load interrupt is not enable - * 1: fuse load interrupt is enable - */ -#define OTP_INT_EN_LOAD_MASK (0x1U) -#define OTP_INT_EN_LOAD_SHIFT (0U) -#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) -#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) - - - -/* SHADOW register group index macro definition */ -#define OTP_SHADOW_SHADOW000 (0UL) -#define OTP_SHADOW_SHADOW001 (1UL) -#define OTP_SHADOW_SHADOW002 (2UL) -#define OTP_SHADOW_SHADOW003 (3UL) -#define OTP_SHADOW_SHADOW004 (4UL) -#define OTP_SHADOW_SHADOW005 (5UL) -#define OTP_SHADOW_SHADOW006 (6UL) -#define OTP_SHADOW_SHADOW007 (7UL) -#define OTP_SHADOW_SHADOW008 (8UL) -#define OTP_SHADOW_SHADOW009 (9UL) -#define OTP_SHADOW_SHADOW010 (10UL) -#define OTP_SHADOW_SHADOW011 (11UL) -#define OTP_SHADOW_SHADOW012 (12UL) -#define OTP_SHADOW_SHADOW013 (13UL) -#define OTP_SHADOW_SHADOW014 (14UL) -#define OTP_SHADOW_SHADOW015 (15UL) -#define OTP_SHADOW_SHADOW016 (16UL) -#define OTP_SHADOW_SHADOW017 (17UL) -#define OTP_SHADOW_SHADOW018 (18UL) -#define OTP_SHADOW_SHADOW019 (19UL) -#define OTP_SHADOW_SHADOW020 (20UL) -#define OTP_SHADOW_SHADOW021 (21UL) -#define OTP_SHADOW_SHADOW022 (22UL) -#define OTP_SHADOW_SHADOW023 (23UL) -#define OTP_SHADOW_SHADOW024 (24UL) -#define OTP_SHADOW_SHADOW025 (25UL) -#define OTP_SHADOW_SHADOW026 (26UL) -#define OTP_SHADOW_SHADOW027 (27UL) -#define OTP_SHADOW_SHADOW028 (28UL) -#define OTP_SHADOW_SHADOW029 (29UL) -#define OTP_SHADOW_SHADOW030 (30UL) -#define OTP_SHADOW_SHADOW031 (31UL) -#define OTP_SHADOW_SHADOW032 (32UL) -#define OTP_SHADOW_SHADOW033 (33UL) -#define OTP_SHADOW_SHADOW034 (34UL) -#define OTP_SHADOW_SHADOW035 (35UL) -#define OTP_SHADOW_SHADOW036 (36UL) -#define OTP_SHADOW_SHADOW037 (37UL) -#define OTP_SHADOW_SHADOW038 (38UL) -#define OTP_SHADOW_SHADOW039 (39UL) -#define OTP_SHADOW_SHADOW040 (40UL) -#define OTP_SHADOW_SHADOW041 (41UL) -#define OTP_SHADOW_SHADOW042 (42UL) -#define OTP_SHADOW_SHADOW043 (43UL) -#define OTP_SHADOW_SHADOW044 (44UL) -#define OTP_SHADOW_SHADOW045 (45UL) -#define OTP_SHADOW_SHADOW046 (46UL) -#define OTP_SHADOW_SHADOW047 (47UL) -#define OTP_SHADOW_SHADOW048 (48UL) -#define OTP_SHADOW_SHADOW049 (49UL) -#define OTP_SHADOW_SHADOW050 (50UL) -#define OTP_SHADOW_SHADOW051 (51UL) -#define OTP_SHADOW_SHADOW052 (52UL) -#define OTP_SHADOW_SHADOW053 (53UL) -#define OTP_SHADOW_SHADOW054 (54UL) -#define OTP_SHADOW_SHADOW055 (55UL) -#define OTP_SHADOW_SHADOW056 (56UL) -#define OTP_SHADOW_SHADOW057 (57UL) -#define OTP_SHADOW_SHADOW058 (58UL) -#define OTP_SHADOW_SHADOW059 (59UL) -#define OTP_SHADOW_SHADOW060 (60UL) -#define OTP_SHADOW_SHADOW061 (61UL) -#define OTP_SHADOW_SHADOW062 (62UL) -#define OTP_SHADOW_SHADOW063 (63UL) -#define OTP_SHADOW_SHADOW064 (64UL) -#define OTP_SHADOW_SHADOW065 (65UL) -#define OTP_SHADOW_SHADOW066 (66UL) -#define OTP_SHADOW_SHADOW067 (67UL) -#define OTP_SHADOW_SHADOW068 (68UL) -#define OTP_SHADOW_SHADOW069 (69UL) -#define OTP_SHADOW_SHADOW070 (70UL) -#define OTP_SHADOW_SHADOW071 (71UL) -#define OTP_SHADOW_SHADOW072 (72UL) -#define OTP_SHADOW_SHADOW073 (73UL) -#define OTP_SHADOW_SHADOW074 (74UL) -#define OTP_SHADOW_SHADOW075 (75UL) -#define OTP_SHADOW_SHADOW076 (76UL) -#define OTP_SHADOW_SHADOW077 (77UL) -#define OTP_SHADOW_SHADOW078 (78UL) -#define OTP_SHADOW_SHADOW079 (79UL) -#define OTP_SHADOW_SHADOW080 (80UL) -#define OTP_SHADOW_SHADOW081 (81UL) -#define OTP_SHADOW_SHADOW082 (82UL) -#define OTP_SHADOW_SHADOW083 (83UL) -#define OTP_SHADOW_SHADOW084 (84UL) -#define OTP_SHADOW_SHADOW085 (85UL) -#define OTP_SHADOW_SHADOW086 (86UL) -#define OTP_SHADOW_SHADOW087 (87UL) -#define OTP_SHADOW_SHADOW088 (88UL) -#define OTP_SHADOW_SHADOW089 (89UL) -#define OTP_SHADOW_SHADOW090 (90UL) -#define OTP_SHADOW_SHADOW091 (91UL) -#define OTP_SHADOW_SHADOW092 (92UL) -#define OTP_SHADOW_SHADOW093 (93UL) -#define OTP_SHADOW_SHADOW094 (94UL) -#define OTP_SHADOW_SHADOW095 (95UL) -#define OTP_SHADOW_SHADOW096 (96UL) -#define OTP_SHADOW_SHADOW097 (97UL) -#define OTP_SHADOW_SHADOW098 (98UL) -#define OTP_SHADOW_SHADOW099 (99UL) -#define OTP_SHADOW_SHADOW100 (100UL) -#define OTP_SHADOW_SHADOW101 (101UL) -#define OTP_SHADOW_SHADOW102 (102UL) -#define OTP_SHADOW_SHADOW103 (103UL) -#define OTP_SHADOW_SHADOW104 (104UL) -#define OTP_SHADOW_SHADOW105 (105UL) -#define OTP_SHADOW_SHADOW106 (106UL) -#define OTP_SHADOW_SHADOW107 (107UL) -#define OTP_SHADOW_SHADOW108 (108UL) -#define OTP_SHADOW_SHADOW109 (109UL) -#define OTP_SHADOW_SHADOW110 (110UL) -#define OTP_SHADOW_SHADOW111 (111UL) -#define OTP_SHADOW_SHADOW112 (112UL) -#define OTP_SHADOW_SHADOW113 (113UL) -#define OTP_SHADOW_SHADOW114 (114UL) -#define OTP_SHADOW_SHADOW115 (115UL) -#define OTP_SHADOW_SHADOW116 (116UL) -#define OTP_SHADOW_SHADOW117 (117UL) -#define OTP_SHADOW_SHADOW118 (118UL) -#define OTP_SHADOW_SHADOW119 (119UL) -#define OTP_SHADOW_SHADOW120 (120UL) -#define OTP_SHADOW_SHADOW121 (121UL) -#define OTP_SHADOW_SHADOW122 (122UL) -#define OTP_SHADOW_SHADOW123 (123UL) -#define OTP_SHADOW_SHADOW124 (124UL) -#define OTP_SHADOW_SHADOW125 (125UL) -#define OTP_SHADOW_SHADOW126 (126UL) -#define OTP_SHADOW_SHADOW127 (127UL) - -/* SHADOW_LOCK register group index macro definition */ -#define OTP_SHADOW_LOCK_LOCK00 (0UL) -#define OTP_SHADOW_LOCK_LOCK01 (1UL) -#define OTP_SHADOW_LOCK_LOCK02 (2UL) -#define OTP_SHADOW_LOCK_LOCK03 (3UL) -#define OTP_SHADOW_LOCK_LOCK04 (4UL) -#define OTP_SHADOW_LOCK_LOCK05 (5UL) -#define OTP_SHADOW_LOCK_LOCK06 (6UL) -#define OTP_SHADOW_LOCK_LOCK07 (7UL) - -/* FUSE register group index macro definition */ -#define OTP_FUSE_FUSE000 (0UL) -#define OTP_FUSE_FUSE001 (1UL) -#define OTP_FUSE_FUSE002 (2UL) -#define OTP_FUSE_FUSE003 (3UL) -#define OTP_FUSE_FUSE004 (4UL) -#define OTP_FUSE_FUSE005 (5UL) -#define OTP_FUSE_FUSE006 (6UL) -#define OTP_FUSE_FUSE007 (7UL) -#define OTP_FUSE_FUSE008 (8UL) -#define OTP_FUSE_FUSE009 (9UL) -#define OTP_FUSE_FUSE010 (10UL) -#define OTP_FUSE_FUSE011 (11UL) -#define OTP_FUSE_FUSE012 (12UL) -#define OTP_FUSE_FUSE013 (13UL) -#define OTP_FUSE_FUSE014 (14UL) -#define OTP_FUSE_FUSE015 (15UL) -#define OTP_FUSE_FUSE016 (16UL) -#define OTP_FUSE_FUSE017 (17UL) -#define OTP_FUSE_FUSE018 (18UL) -#define OTP_FUSE_FUSE019 (19UL) -#define OTP_FUSE_FUSE020 (20UL) -#define OTP_FUSE_FUSE021 (21UL) -#define OTP_FUSE_FUSE022 (22UL) -#define OTP_FUSE_FUSE023 (23UL) -#define OTP_FUSE_FUSE024 (24UL) -#define OTP_FUSE_FUSE025 (25UL) -#define OTP_FUSE_FUSE026 (26UL) -#define OTP_FUSE_FUSE027 (27UL) -#define OTP_FUSE_FUSE028 (28UL) -#define OTP_FUSE_FUSE029 (29UL) -#define OTP_FUSE_FUSE030 (30UL) -#define OTP_FUSE_FUSE031 (31UL) -#define OTP_FUSE_FUSE032 (32UL) -#define OTP_FUSE_FUSE033 (33UL) -#define OTP_FUSE_FUSE034 (34UL) -#define OTP_FUSE_FUSE035 (35UL) -#define OTP_FUSE_FUSE036 (36UL) -#define OTP_FUSE_FUSE037 (37UL) -#define OTP_FUSE_FUSE038 (38UL) -#define OTP_FUSE_FUSE039 (39UL) -#define OTP_FUSE_FUSE040 (40UL) -#define OTP_FUSE_FUSE041 (41UL) -#define OTP_FUSE_FUSE042 (42UL) -#define OTP_FUSE_FUSE043 (43UL) -#define OTP_FUSE_FUSE044 (44UL) -#define OTP_FUSE_FUSE045 (45UL) -#define OTP_FUSE_FUSE046 (46UL) -#define OTP_FUSE_FUSE047 (47UL) -#define OTP_FUSE_FUSE048 (48UL) -#define OTP_FUSE_FUSE049 (49UL) -#define OTP_FUSE_FUSE050 (50UL) -#define OTP_FUSE_FUSE051 (51UL) -#define OTP_FUSE_FUSE052 (52UL) -#define OTP_FUSE_FUSE053 (53UL) -#define OTP_FUSE_FUSE054 (54UL) -#define OTP_FUSE_FUSE055 (55UL) -#define OTP_FUSE_FUSE056 (56UL) -#define OTP_FUSE_FUSE057 (57UL) -#define OTP_FUSE_FUSE058 (58UL) -#define OTP_FUSE_FUSE059 (59UL) -#define OTP_FUSE_FUSE060 (60UL) -#define OTP_FUSE_FUSE061 (61UL) -#define OTP_FUSE_FUSE062 (62UL) -#define OTP_FUSE_FUSE063 (63UL) -#define OTP_FUSE_FUSE064 (64UL) -#define OTP_FUSE_FUSE065 (65UL) -#define OTP_FUSE_FUSE066 (66UL) -#define OTP_FUSE_FUSE067 (67UL) -#define OTP_FUSE_FUSE068 (68UL) -#define OTP_FUSE_FUSE069 (69UL) -#define OTP_FUSE_FUSE070 (70UL) -#define OTP_FUSE_FUSE071 (71UL) -#define OTP_FUSE_FUSE072 (72UL) -#define OTP_FUSE_FUSE073 (73UL) -#define OTP_FUSE_FUSE074 (74UL) -#define OTP_FUSE_FUSE075 (75UL) -#define OTP_FUSE_FUSE076 (76UL) -#define OTP_FUSE_FUSE077 (77UL) -#define OTP_FUSE_FUSE078 (78UL) -#define OTP_FUSE_FUSE079 (79UL) -#define OTP_FUSE_FUSE080 (80UL) -#define OTP_FUSE_FUSE081 (81UL) -#define OTP_FUSE_FUSE082 (82UL) -#define OTP_FUSE_FUSE083 (83UL) -#define OTP_FUSE_FUSE084 (84UL) -#define OTP_FUSE_FUSE085 (85UL) -#define OTP_FUSE_FUSE086 (86UL) -#define OTP_FUSE_FUSE087 (87UL) -#define OTP_FUSE_FUSE088 (88UL) -#define OTP_FUSE_FUSE089 (89UL) -#define OTP_FUSE_FUSE090 (90UL) -#define OTP_FUSE_FUSE091 (91UL) -#define OTP_FUSE_FUSE092 (92UL) -#define OTP_FUSE_FUSE093 (93UL) -#define OTP_FUSE_FUSE094 (94UL) -#define OTP_FUSE_FUSE095 (95UL) -#define OTP_FUSE_FUSE096 (96UL) -#define OTP_FUSE_FUSE097 (97UL) -#define OTP_FUSE_FUSE098 (98UL) -#define OTP_FUSE_FUSE099 (99UL) -#define OTP_FUSE_FUSE100 (100UL) -#define OTP_FUSE_FUSE101 (101UL) -#define OTP_FUSE_FUSE102 (102UL) -#define OTP_FUSE_FUSE103 (103UL) -#define OTP_FUSE_FUSE104 (104UL) -#define OTP_FUSE_FUSE105 (105UL) -#define OTP_FUSE_FUSE106 (106UL) -#define OTP_FUSE_FUSE107 (107UL) -#define OTP_FUSE_FUSE108 (108UL) -#define OTP_FUSE_FUSE109 (109UL) -#define OTP_FUSE_FUSE110 (110UL) -#define OTP_FUSE_FUSE111 (111UL) -#define OTP_FUSE_FUSE112 (112UL) -#define OTP_FUSE_FUSE113 (113UL) -#define OTP_FUSE_FUSE114 (114UL) -#define OTP_FUSE_FUSE115 (115UL) -#define OTP_FUSE_FUSE116 (116UL) -#define OTP_FUSE_FUSE117 (117UL) -#define OTP_FUSE_FUSE118 (118UL) -#define OTP_FUSE_FUSE119 (119UL) -#define OTP_FUSE_FUSE120 (120UL) -#define OTP_FUSE_FUSE121 (121UL) -#define OTP_FUSE_FUSE122 (122UL) -#define OTP_FUSE_FUSE123 (123UL) -#define OTP_FUSE_FUSE124 (124UL) -#define OTP_FUSE_FUSE125 (125UL) -#define OTP_FUSE_FUSE126 (126UL) -#define OTP_FUSE_FUSE127 (127UL) - -/* FUSE_LOCK register group index macro definition */ -#define OTP_FUSE_LOCK_LOCK00 (0UL) -#define OTP_FUSE_LOCK_LOCK01 (1UL) -#define OTP_FUSE_LOCK_LOCK02 (2UL) -#define OTP_FUSE_LOCK_LOCK03 (3UL) -#define OTP_FUSE_LOCK_LOCK04 (4UL) -#define OTP_FUSE_LOCK_LOCK05 (5UL) -#define OTP_FUSE_LOCK_LOCK06 (6UL) -#define OTP_FUSE_LOCK_LOCK07 (7UL) - -/* REGION register group index macro definition */ -#define OTP_REGION_LOAD_REGION0 (0UL) -#define OTP_REGION_LOAD_REGION1 (1UL) -#define OTP_REGION_LOAD_REGION2 (2UL) -#define OTP_REGION_LOAD_REGION3 (3UL) - - -#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pcfg_regs.h deleted file mode 100644 index 55bc385a454..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pcfg_regs.h +++ /dev/null @@ -1,900 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PCFG_H -#define HPM_PCFG_H - -typedef struct { - __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ - __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ - __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ - __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ - __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ - __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ - __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ - __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ - __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ - __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ - __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ - __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ - __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ - __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ - __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ - __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ - __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ - __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ - __RW uint32_t RC24M; /* 0x60: RC 24M config */ - __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ - __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ - __R uint32_t STATUS; /* 0x6C: RC 24M track status */ -} PCFG_Type; - - -/* Bitfield definition for register: BANDGAP */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) -#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) -#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) -#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) - -/* - * LOWPOWER_MODE (RW) - * - * Banggap work in low power mode, banggap function limited - * 0: banggap works in normal mode - * 1: banggap works in low power mode - */ -#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) -#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) -#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) -#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Banggap work in power save mode, banggap function normally - * 0: banggap works in high performance mode - * 1: banggap works in power saving mode - */ -#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) -#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) -#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) -#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) - -/* - * VBG_1P0_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) -#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) - -/* - * VBG_P65_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) - -/* - * VBG_P50_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) -#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) -#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) - -/* Bitfield definition for register: LDO1P1 */ -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. - * 700: 700mV - * 720: 720mV - * . . . - * 1320:1320mV - */ -#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) -#define PCFG_LDO1P1_VOLT_SHIFT (0U) -#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) -#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) - -/* Bitfield definition for register: LDO2P5 */ -/* - * READY (RO) - * - * Ready flag, will set 1ms after enabled or voltage change - * 0: LDO is not ready for use - * 1: LDO is ready - */ -#define PCFG_LDO2P5_READY_MASK (0x10000000UL) -#define PCFG_LDO2P5_READY_SHIFT (28U) -#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) -#define PCFG_LDO2P5_ENABLE_SHIFT (16U) -#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) -#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. - * 2125: 2125mV - * 2150: 2150mV - * . . . - * 2900:2900mV - */ -#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) -#define PCFG_LDO2P5_VOLT_SHIFT (0U) -#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) -#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDC is applying new change - * 1: DCDC is ready - */ -#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDC_MODE_READY_SHIFT (28U) -#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDC work mode - * XX0: turn off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDC_MODE_MODE_SHIFT (16U) -#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) -#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) -#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) - -/* - * DISABLE_POWER_LOSS (RW) - * - * disable power loss protection - * 0: power loss protection enabled, DCDC shuts down when power loss - * 1: power loss protection disabled, DCDC try working after power voltage drop - */ -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * output over voltage protection - * 0: protection enabled, DCDC will shut down is output voltage is unexpected high - * 1: protection disabled, DCDC continue to adjust output voltage - */ -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A, - * 1: 1.3A - */ -#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDC_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDC current level, current level is num * 50mA - */ -#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDC_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) -#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) -#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDC_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDC_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) -#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) -#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) -#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) -#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) -#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) -#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) -#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) -#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDC internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) -#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled, - * 1: steping enabled - */ -#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) -#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDC_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDC voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) -#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - */ -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: POWER_TRAP */ -/* - * TRIGGERED (RW) - * - * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. - * 0: low power trap is not triggered - * 1: low power trap triggered - */ -#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) -#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) -#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) -#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) - -/* - * RETENTION (RW) - * - * DCDC enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDC - * 1: reduce DCDC voltage - */ -#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) -#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) -#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) -#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) - -/* - * TRAP (RW) - * - * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered - * 0: trap not enabled, pmic side low power function disabled - * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - */ -#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) -#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) -#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) -#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) - -/* Bitfield definition for register: WAKE_CAUSE */ -/* - * CAUSE (RW) - * - * wake up cause, each bit represents one wake up source, write 1 to clear the register bit - * 0: wake up source is not active during last wakeup - * 1: wake up source is active furing last wakeup - * bit 0: pmic_enable - * bit 1: debug wakeup - * bit 4: fuse interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit11: Security monitor interrupt - * bit12: Security in PMIC event - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit18: BATT Button interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) -#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) -#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: WAKE_MASK */ -/* - * MASK (RW) - * - * mask for wake up sources, each bit represents one wakeup source - * 0: allow source to wake up system - * 1: disallow source to wakeup system - * bit 0: pmic_enable - * bit 1: debug wakeup - * bit 4: fuse interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit11: Security monitor interrupt - * bit12: Security in PMIC event - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit18: BATT Button interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_MASK_MASK_SHIFT (0U) -#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) -#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) - -/* Bitfield definition for register: SCG_CTRL */ -/* - * SCG (RW) - * - * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: reserved - * 10: clock is always off - * 11: clock is always on - * bit0-1: fuse - * bit6-7:gpio - * bit8-9:ioc - * bit10-11: timer - * bit12-13:wdog - * bit14-15:uart - * bit16-17:debug - */ -#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) -#define PCFG_SCG_CTRL_SCG_SHIFT (0U) -#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) -#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) - -/* Bitfield definition for register: DEBUG_STOP */ -/* - * CPU1 (RW) - * - * Stop peripheral when CPU1 enter debug mode - * 0: peripheral keep running when CPU1 in debug mode - * 1: peripheral enter debug mode when CPU1 enter debug - */ -#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) -#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) -#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) -#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) - -/* - * CPU0 (RW) - * - * Stop peripheral when CPU0 enter debug mode - * 0: peripheral keep running when CPU0 in debug mode - * 1: peripheral enter debug mode when CPU0 enter debug - */ -#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) -#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) -#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) -#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) - -/* Bitfield definition for register: RC24M */ -/* - * RC_TRIMMED (RW) - * - * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: RC is not trimmed - * 1: RC is trimmed - */ -#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) -#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) -#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) -#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) - -/* - * TRIM_C (RW) - * - * Coarse trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_C_MASK (0x700U) -#define PCFG_RC24M_TRIM_C_SHIFT (8U) -#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) -#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) - -/* - * TRIM_F (RW) - * - * Fine trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_F_MASK (0x1FU) -#define PCFG_RC24M_TRIM_F_SHIFT (0U) -#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) -#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) - -/* Bitfield definition for register: RC24M_TRACK */ -/* - * SEL24M (RW) - * - * Select track reference - * 0: select 32K as reference - * 1: select 24M XTAL as reference - */ -#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) -#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) -#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) -#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) - -/* - * RETURN (RW) - * - * Retrun default value when XTAL loss - * 0: remain last tracking value - * 1: switch to default value - */ -#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) -#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) -#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) -#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) - -/* - * TRACK (RW) - * - * track mode - * 0: RC24M free running - * 1: track RC24M to external XTAL - */ -#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) -#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) -#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) -#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) - -/* Bitfield definition for register: TRACK_TARGET */ -/* - * PRE_DIV (RW) - * - * Divider for reference source - */ -#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) -#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) -#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) -#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) - -/* - * TARGET (RW) - * - * Target frequency multiplier of divided source - */ -#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) -#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) -#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) -#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * SEL32K (RO) - * - * track is using XTAL32K - * 0: track is not using XTAL32K - * 1: track is using XTAL32K - */ -#define PCFG_STATUS_SEL32K_MASK (0x100000UL) -#define PCFG_STATUS_SEL32K_SHIFT (20U) -#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) - -/* - * SEL24M (RO) - * - * track is using XTAL24M - * 0: track is not using XTAL24M - * 1: track is using XTAL24M - */ -#define PCFG_STATUS_SEL24M_MASK (0x10000UL) -#define PCFG_STATUS_SEL24M_SHIFT (16U) -#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) - -/* - * EN_TRIM (RO) - * - * default value takes effect - * 0: default value is invalid - * 1: default value is valid - */ -#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) -#define PCFG_STATUS_EN_TRIM_SHIFT (15U) -#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) - -/* - * TRIM_C (RO) - * - * default coarse trim value - */ -#define PCFG_STATUS_TRIM_C_MASK (0x700U) -#define PCFG_STATUS_TRIM_C_SHIFT (8U) -#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) - -/* - * TRIM_F (RO) - * - * default fine trim value - */ -#define PCFG_STATUS_TRIM_F_MASK (0x1FU) -#define PCFG_STATUS_TRIM_F_SHIFT (0U) -#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) - - - - -#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pgpr_regs.h deleted file mode 100644 index acf20cfecd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pgpr_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PGPR_H -#define HPM_PGPR_H - -typedef struct { - __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ - __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ - __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ - __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ - __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ - __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ - __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ - __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ - __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ - __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ - __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ - __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ - __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ - __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ - __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ - __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ -} PGPR_Type; - - -/* Bitfield definition for register: PMIC_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) -#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) -#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) -#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) -#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR04 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) -#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR05 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) -#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR06 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) -#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR07 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) -#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR08 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) -#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR09 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) -#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR10 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) -#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR11 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) -#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR12 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) -#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR13 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) -#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR14 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) -#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR15 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) -#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) - - - - -#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pla_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pla_regs.h deleted file mode 100644 index c82f90d0235..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pla_regs.h +++ /dev/null @@ -1,1708 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLA_H -#define HPM_PLA_H - -typedef struct { - struct { - __RW uint32_t AOI_16TO8[8]; /* 0x0 - 0x1C: CHN AOI_16to8 AND logic cfg */ - __RW uint32_t AOI_8TO7_00_01; /* 0x20: CHN AOI_16to8_00_01 OR logic cfg */ - __RW uint32_t AOI_8TO7_02_03; /* 0x24: CHN AOI_16to8_02_03 OR logic cfg */ - __RW uint32_t AOI_8TO7_04_05; /* 0x28: CHN AOI_16to8_04_05 OR logic cfg */ - __RW uint32_t AOI_8TO7_06; /* 0x2C: CHN AOI_16to8_06 OR logic cfg */ - __RW uint32_t FILTER_2ND[8]; /* 0x30 - 0x4C: CHN SECOND_FILTER cfg */ - __RW uint32_t FILTER_3RD[7]; /* 0x50 - 0x68: CHN THIRD_FILTER cfg */ - __RW uint32_t CFG_FF; /* 0x6C: CHN cfg ff */ - } CHN[8]; - __R uint8_t RESERVED0[64]; /* 0x380 - 0x3BF: Reserved */ - __RW uint32_t FILTER_1ST_PLA_IN[8]; /* 0x3C0 - 0x3DC: FRIST_FILTER_PLA_IN setting */ - __RW uint32_t FILTER_1ST_PLA_OUT[8]; /* 0x3E0 - 0x3FC: FRIST_FILTER_PLA_OUT setting */ - __RW uint32_t CHN_CFG_ACTIVE[8]; /* 0x400 - 0x41C: CHN cfg active */ -} PLA_Type; - - -/* Bitfield definition for register of struct array CHN: AOI_16TO8_00 */ -/* - * AOI_16TO8_15 (RW) - * - * select value for AOI_16to8_15. - * 0: 0. - * 1: 1st_filter_out[15]. - * 2: ~1st_filter_out[15]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK (0xC0000000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT (30U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_15_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_15_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_15_SHIFT) - -/* - * AOI_16TO8_14 (RW) - * - * select value for AOI_16to8_14. - * 0: 0. - * 1: 1st_filter_out[14]. - * 2: ~1st_filter_out[14]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK (0x30000000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT (28U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_14_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_14_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_14_SHIFT) - -/* - * AOI_16TO8_13 (RW) - * - * select value for AOI_16to8_13. - * 0: 0. - * 1: 1st_filter_out[13]. - * 2: ~1st_filter_out[13]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK (0xC000000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT (26U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_13_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_13_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_13_SHIFT) - -/* - * AOI_16TO8_12 (RW) - * - * select value for AOI_16to8_12. - * 0: 0. - * 1: 1st_filter_out[12]. - * 2: ~1st_filter_out[12]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK (0x3000000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT (24U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_12_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_12_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_12_SHIFT) - -/* - * AOI_16TO8_11 (RW) - * - * select value for AOI_16to8_11. - * 0: 0. - * 1: 1st_filter_out[11]. - * 2: ~1st_filter_out[11]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK (0xC00000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT (22U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_11_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_11_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_11_SHIFT) - -/* - * AOI_16TO8_10 (RW) - * - * select value for AOI_16to8_10. - * 0: 0. - * 1: 1st_filter_out[10]. - * 2: ~1st_filter_out[10]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK (0x300000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT (20U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_10_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_10_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_10_SHIFT) - -/* - * AOI_16TO8_9 (RW) - * - * select value for AOI_16to8_9. - * 0: 0. - * 1: 1st_filter_out[9]. - * 2: ~1st_filter_out[9]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK (0xC0000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT (18U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_9_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_9_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_9_SHIFT) - -/* - * AOI_16TO8_8 (RW) - * - * select value for AOI_16to8_8. - * 0: 0. - * 1: 1st_filter_out[8]. - * 2: ~1st_filter_out[8]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK (0x30000UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT (16U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_8_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_8_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_8_SHIFT) - -/* - * AOI_16TO8_7 (RW) - * - * select value for AOI_16to8_7. - * 0: 0. - * 1: 1st_filter_out[7]. - * 2: ~1st_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK (0xC000U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT (14U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_7_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_7_SHIFT) - -/* - * AOI_16TO8_6 (RW) - * - * select value for AOI_16to8_6. - * 0: 0. - * 1: 1st_filter_out[6]. - * 2: ~1st_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK (0x3000U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT (12U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_6_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_6_SHIFT) - -/* - * AOI_16TO8_5 (RW) - * - * select value for AOI_16to8_5. - * 0: 0. - * 1: 1st_filter_out[5]. - * 2: ~1st_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK (0xC00U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT (10U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_5_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_5_SHIFT) - -/* - * AOI_16TO8_4 (RW) - * - * select value for AOI_16to8_4. - * 0: 0. - * 1: 1st_filter_out[4]. - * 2: ~1st_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK (0x300U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT (8U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_4_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_4_SHIFT) - -/* - * AOI_16TO8_3 (RW) - * - * select value for AOI_16to8_3. - * 0: 0. - * 1: 1st_filter_out[3]. - * 2: ~1st_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK (0xC0U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT (6U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_3_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_3_SHIFT) - -/* - * AOI_16TO8_2 (RW) - * - * select value for AOI_16to8_2. - * 0: 0. - * 1: 1st_filter_out[2]. - * 2: ~1st_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK (0x30U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT (4U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_2_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_2_SHIFT) - -/* - * AOI_16TO8_1 (RW) - * - * select value for AOI_16to8_1. - * 0: 0. - * 1: 1st_filter_out[1]. - * 2: ~1st_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK (0xCU) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT (2U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_1_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_1_SHIFT) - -/* - * AOI_16TO8_0 (RW) - * - * select value for AOI_16to8_0. - * 0: 0. - * 1: 1st_filter_out[0]. - * 2: ~1st_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK (0x3U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT (0U) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_16TO8_AOI_16TO8_0_MASK) >> PLA_CHN_AOI_16TO8_AOI_16TO8_0_SHIFT) - -/* Bitfield definition for register of struct array CHN: AOI_8TO7_00_01 */ -/* - * AOI_8TO7_01_7 (RW) - * - * select value for AOI_8to7_01_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK (0xC0000000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT (30U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_7_SHIFT) - -/* - * AOI_8TO7_01_6 (RW) - * - * select value for AOI_8to7_01_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK (0x30000000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT (28U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_6_SHIFT) - -/* - * AOI_8TO7_01_5 (RW) - * - * select value for AOI_8to7_01_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK (0xC000000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT (26U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_5_SHIFT) - -/* - * AOI_8TO7_01_4 (RW) - * - * select value for AOI_8to7_01_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK (0x3000000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT (24U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_4_SHIFT) - -/* - * AOI_8TO7_01_3 (RW) - * - * select value for AOI_8to7_01_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK (0xC00000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT (22U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_3_SHIFT) - -/* - * AOI_8TO7_01_2 (RW) - * - * select value for AOI_8to7_01_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK (0x300000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT (20U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_2_SHIFT) - -/* - * AOI_8TO7_01_1 (RW) - * - * select value for AOI_8to7_01_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK (0xC0000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT (18U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_1_SHIFT) - -/* - * AOI_8TO7_01_0 (RW) - * - * select value for AOI_8to7_01_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK (0x30000UL) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT (16U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_01_0_SHIFT) - -/* - * AOI_8TO7_00_7 (RW) - * - * select value for AOI_8to7_00_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK (0xC000U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT (14U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_7_SHIFT) - -/* - * AOI_8TO7_00_6 (RW) - * - * select value for AOI_8to7_00_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK (0x3000U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT (12U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_6_SHIFT) - -/* - * AOI_8TO7_00_5 (RW) - * - * select value for AOI_8to7_00_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK (0xC00U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT (10U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_5_SHIFT) - -/* - * AOI_8TO7_00_4 (RW) - * - * select value for AOI_8to7_00_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK (0x300U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT (8U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_4_SHIFT) - -/* - * AOI_8TO7_00_3 (RW) - * - * select value for AOI_8to7_00_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK (0xC0U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT (6U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_3_SHIFT) - -/* - * AOI_8TO7_00_2 (RW) - * - * select value for AOI_8to7_00_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK (0x30U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT (4U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_2_SHIFT) - -/* - * AOI_8TO7_00_1 (RW) - * - * select value for AOI_8to7_00_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK (0xCU) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT (2U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_1_SHIFT) - -/* - * AOI_8TO7_00_0 (RW) - * - * select value for AOI_8to7_00_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK (0x3U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT (0U) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) -#define PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_MASK) >> PLA_CHN_AOI_8TO7_00_01_AOI_8TO7_00_0_SHIFT) - -/* Bitfield definition for register of struct array CHN: AOI_8TO7_02_03 */ -/* - * AOI_8TO7_03_7 (RW) - * - * select value for AOI_8to7_03_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK (0xC0000000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT (30U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_7_SHIFT) - -/* - * AOI_8TO7_03_6 (RW) - * - * select value for AOI_8to7_03_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK (0x30000000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT (28U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_6_SHIFT) - -/* - * AOI_8TO7_03_5 (RW) - * - * select value for AOI_8to7_03_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK (0xC000000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT (26U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_5_SHIFT) - -/* - * AOI_8TO7_03_4 (RW) - * - * select value for AOI_8to7_03_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK (0x3000000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT (24U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_4_SHIFT) - -/* - * AOI_8TO7_03_3 (RW) - * - * select value for AOI_8to7_03_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK (0xC00000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT (22U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_3_SHIFT) - -/* - * AOI_8TO7_03_2 (RW) - * - * select value for AOI_8to7_03_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK (0x300000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT (20U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_2_SHIFT) - -/* - * AOI_8TO7_03_1 (RW) - * - * select value for AOI_8to7_03_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK (0xC0000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT (18U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_1_SHIFT) - -/* - * AOI_8TO7_03_0 (RW) - * - * select value for AOI_8to7_03_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK (0x30000UL) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT (16U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_03_0_SHIFT) - -/* - * AOI_8TO7_02_7 (RW) - * - * select value for AOI_8to7_02_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK (0xC000U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT (14U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_7_SHIFT) - -/* - * AOI_8TO7_02_6 (RW) - * - * select value for AOI_8to7_02_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK (0x3000U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT (12U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_6_SHIFT) - -/* - * AOI_8TO7_02_5 (RW) - * - * select value for AOI_8to7_02_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK (0xC00U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT (10U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_5_SHIFT) - -/* - * AOI_8TO7_02_4 (RW) - * - * select value for AOI_8to7_02_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK (0x300U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT (8U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_4_SHIFT) - -/* - * AOI_8TO7_02_3 (RW) - * - * select value for AOI_8to7_02_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK (0xC0U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT (6U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_3_SHIFT) - -/* - * AOI_8TO7_02_2 (RW) - * - * select value for AOI_8to7_02_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK (0x30U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT (4U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_2_SHIFT) - -/* - * AOI_8TO7_02_1 (RW) - * - * select value for AOI_8to7_02_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK (0xCU) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT (2U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_1_SHIFT) - -/* - * AOI_8TO7_02_0 (RW) - * - * select value for AOI_8to7_02_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK (0x3U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT (0U) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) -#define PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_MASK) >> PLA_CHN_AOI_8TO7_02_03_AOI_8TO7_02_0_SHIFT) - -/* Bitfield definition for register of struct array CHN: AOI_8TO7_04_05 */ -/* - * AOI_8TO7_05_7 (RW) - * - * select value for AOI_8to7_05_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK (0xC0000000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT (30U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_7_SHIFT) - -/* - * AOI_8TO7_05_6 (RW) - * - * select value for AOI_8to7_05_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK (0x30000000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT (28U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_6_SHIFT) - -/* - * AOI_8TO7_05_5 (RW) - * - * select value for AOI_8to7_05_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK (0xC000000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT (26U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_5_SHIFT) - -/* - * AOI_8TO7_05_4 (RW) - * - * select value for AOI_8to7_05_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK (0x3000000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT (24U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_4_SHIFT) - -/* - * AOI_8TO7_05_3 (RW) - * - * select value for AOI_8to7_05_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK (0xC00000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT (22U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_3_SHIFT) - -/* - * AOI_8TO7_05_2 (RW) - * - * select value for AOI_8to7_05_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK (0x300000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT (20U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_2_SHIFT) - -/* - * AOI_8TO7_05_1 (RW) - * - * select value for AOI_8to7_05_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK (0xC0000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT (18U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_1_SHIFT) - -/* - * AOI_8TO7_05_0 (RW) - * - * select value for AOI_8to7_05_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK (0x30000UL) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT (16U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_05_0_SHIFT) - -/* - * AOI_8TO7_04_7 (RW) - * - * select value for AOI_8to7_04_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK (0xC000U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT (14U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_7_SHIFT) - -/* - * AOI_8TO7_04_6 (RW) - * - * select value for AOI_8to7_04_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK (0x3000U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT (12U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_6_SHIFT) - -/* - * AOI_8TO7_04_5 (RW) - * - * select value for AOI_8to7_04_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK (0xC00U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT (10U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_5_SHIFT) - -/* - * AOI_8TO7_04_4 (RW) - * - * select value for AOI_8to7_04_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK (0x300U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT (8U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_4_SHIFT) - -/* - * AOI_8TO7_04_3 (RW) - * - * select value for AOI_8to7_04_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK (0xC0U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT (6U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_3_SHIFT) - -/* - * AOI_8TO7_04_2 (RW) - * - * select value for AOI_8to7_04_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK (0x30U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT (4U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_2_SHIFT) - -/* - * AOI_8TO7_04_1 (RW) - * - * select value for AOI_8to7_04_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK (0xCU) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT (2U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_1_SHIFT) - -/* - * AOI_8TO7_04_0 (RW) - * - * select value for AOI_8to7_04_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK (0x3U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT (0U) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) -#define PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_MASK) >> PLA_CHN_AOI_8TO7_04_05_AOI_8TO7_04_0_SHIFT) - -/* Bitfield definition for register of struct array CHN: AOI_8TO7_06 */ -/* - * AOI_8TO7_06_7 (RW) - * - * select value for AOI_8to7_06_7. - * 0: 0. - * 1: 2nd_filter_out[7]. - * 2: ~2nd_filter_out[7]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK (0xC000U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT (14U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_7_SHIFT) - -/* - * AOI_8TO7_06_6 (RW) - * - * select value for AOI_8to7_06_6. - * 0: 0. - * 1: 2nd_filter_out[6]. - * 2: ~2nd_filter_out[6]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK (0x3000U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT (12U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_6_SHIFT) - -/* - * AOI_8TO7_06_5 (RW) - * - * select value for AOI_8to7_06_5. - * 0: 0. - * 1: 2nd_filter_out[5]. - * 2: ~2nd_filter_out[5]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK (0xC00U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT (10U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_5_SHIFT) - -/* - * AOI_8TO7_06_4 (RW) - * - * select value for AOI_8to7_06_4. - * 0: 0. - * 1: 2nd_filter_out[4]. - * 2: ~2nd_filter_out[4]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK (0x300U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT (8U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_4_SHIFT) - -/* - * AOI_8TO7_06_3 (RW) - * - * select value for AOI_8to7_06_3. - * 0: 0. - * 1: 2nd_filter_out[3]. - * 2: ~2nd_filter_out[3]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK (0xC0U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT (6U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_3_SHIFT) - -/* - * AOI_8TO7_06_2 (RW) - * - * select value for AOI_8to7_06_2. - * 0: 0. - * 1: 2nd_filter_out[2]. - * 2: ~2nd_filter_out[2]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK (0x30U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT (4U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_2_SHIFT) - -/* - * AOI_8TO7_06_1 (RW) - * - * select value for AOI_8to7_06_1. - * 0: 0. - * 1: 2nd_filter_out[1]. - * 2: ~2nd_filter_out[1]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK (0xCU) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT (2U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_1_SHIFT) - -/* - * AOI_8TO7_06_0 (RW) - * - * select value for AOI_8to7_06_0. - * 0: 0. - * 1: 2nd_filter_out[0]. - * 2: ~2nd_filter_out[0]. - * 3: 1 - */ -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK (0x3U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT (0U) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SET(x) (((uint32_t)(x) << PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) -#define PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_GET(x) (((uint32_t)(x) & PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_MASK) >> PLA_CHN_AOI_8TO7_06_AOI_8TO7_06_0_SHIFT) - -/* Bitfield definition for register of struct array CHN: SECOND_FILTER_0 */ -/* - * FILTER_EXT_COUNTER (RW) - * - * filter_ext counter value, cycles for filter or extent by system clock。 - * 0：0*apb_clk_period - * 1：1*apb_clk_period - * 2: 2*apb_clk_period - * … - * 65535: 65535*apb_clk_period - */ -#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT (16U) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_COUNTER_SHIFT) - -/* - * FILTER_EXT_TYPE (RW) - * - * filter extend type. - * 0-3：nothing to do. - * 4： input high level extend. - * 5： input low level extend. - * 6： output extend. - * 7： input pulse extend. - */ -#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK (0x7000U) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT (12U) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_TYPE_SHIFT) - -/* - * FILTER_EXT_ENABLE (RW) - * - * filter extend enable. - * 0. bypass filter extend. all setting in bit31:12 are inactive - * 1. enable filter extend, all setting in bit31:12 are active. - */ -#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK (0x100U) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT (8U) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) -#define PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_EXT_ENABLE_SHIFT) - -/* - * FILTER_SYNC_LEVEL (RW) - * - * synchroniser level. - * 0: 2 level sync. - * 1: 3 level sync - */ -#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK (0x80U) -#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT (7U) -#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) -#define PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_2ND_FILTER_SYNC_LEVEL_SHIFT) - -/* - * POSE_EDGE_DECT_ENABLE (RW) - * - * pose edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK (0x40U) -#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT (6U) -#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) -#define PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_POSE_EDGE_DECT_ENABLE_SHIFT) - -/* - * NEGE_EDGE_DECT_ENABLE (RW) - * - * nege edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) -#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) -#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) -#define PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_NEGE_EDGE_DECT_ENABLE_SHIFT) - -/* - * EDGE_DECT_ENABLE (RW) - * - * edge detector enable. - * 0: disable. bit6/bit5 setting inactive. - * 1: enable. bit6/bit5 setting active. - */ -#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK (0x10U) -#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT (4U) -#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) -#define PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_EDGE_DECT_ENABLE_SHIFT) - -/* - * FILTER_REVERSE (RW) - * - * reverse sync and edge detector filter's output. - * 0: not reverse. - * 1: reverse. - */ -#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK (0x8U) -#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT (3U) -#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) -#define PLA_CHN_FILTER_2ND_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_2ND_FILTER_REVERSE_SHIFT) - -/* - * SOFTWARE_INJECT (RW) - * - * software inject value for sync and edge detector filter. - * 0: inject low level. - * 1: inject high level. - * 2: not inject. - * 3. inject high level. - */ -#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK (0x6U) -#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT (1U) -#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) -#define PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_2ND_SOFTWARE_INJECT_SHIFT) - -/* - * SYNC_EDGE_FILTER_ENABLE (RW) - * - * sync and edge detector filter. - * 0: disable. - * 1: enable. - */ -#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) -#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) -#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) -#define PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_2ND_SYNC_EDGE_FILTER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHN: THIRD_FILTER_0 */ -/* - * FILTER_EXT_COUNTER (RW) - * - * filter_ext counter value, cycles for filter or extent by system clock。 - * 0：0*apb_clk_period - * 1：1*apb_clk_period - * 2: 2*apb_clk_period - * … - * 65535: 65535*apb_clk_period - */ -#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT (16U) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_COUNTER_SHIFT) - -/* - * FILTER_EXT_TYPE (RW) - * - * filter extend type. - * 0-3：nothing to do. - * 4： input high level extend. - * 5： input low level extend. - * 6： output extend. - * 7： input pulse extend. - */ -#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK (0x7000U) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT (12U) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_TYPE_SHIFT) - -/* - * FILTER_EXT_ENABLE (RW) - * - * filter extend enable. - * 0. bypass filter extend. all setting in bit31:12 are inactive - * 1. enable filter extend, all setting in bit31:12 are active. - */ -#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK (0x100U) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT (8U) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) -#define PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_EXT_ENABLE_SHIFT) - -/* - * FILTER_SYNC_LEVEL (RW) - * - * synchroniser level. - * 0: 2 level sync. - * 1: 3 level sync - */ -#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK (0x80U) -#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT (7U) -#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) -#define PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_MASK) >> PLA_CHN_FILTER_3RD_FILTER_SYNC_LEVEL_SHIFT) - -/* - * POSE_EDGE_DECT_ENABLE (RW) - * - * pose edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK (0x40U) -#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT (6U) -#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) -#define PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_POSE_EDGE_DECT_ENABLE_SHIFT) - -/* - * NEGE_EDGE_DECT_ENABLE (RW) - * - * nege edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) -#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) -#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) -#define PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_NEGE_EDGE_DECT_ENABLE_SHIFT) - -/* - * EDGE_DECT_ENABLE (RW) - * - * edge detector enable. - * 0: disable. bit6/bit5 setting inactive. - * 1: enable. bit6/bit5 setting active. - */ -#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK (0x10U) -#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT (4U) -#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) -#define PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_EDGE_DECT_ENABLE_SHIFT) - -/* - * FILTER_REVERSE (RW) - * - * reverse sync and edge detector filter's output. - * 0: not reverse. - * 1: reverse. - */ -#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK (0x8U) -#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT (3U) -#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) -#define PLA_CHN_FILTER_3RD_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_FILTER_REVERSE_MASK) >> PLA_CHN_FILTER_3RD_FILTER_REVERSE_SHIFT) - -/* - * SOFTWARE_INJECT (RW) - * - * software inject value for sync and edge detector filter. - * 0: inject low level. - * 1: inject high level. - * 2: not inject. - * 3. inject high level. - */ -#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK (0x6U) -#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT (1U) -#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) -#define PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_MASK) >> PLA_CHN_FILTER_3RD_SOFTWARE_INJECT_SHIFT) - -/* - * SYNC_EDGE_FILTER_ENABLE (RW) - * - * sync and edge detector filter. - * 0: disable. - * 1: enable. - */ -#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) -#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) -#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) -#define PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_CHN_FILTER_3RD_SYNC_EDGE_FILTER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHN: CFG_FF */ -/* - * OSC_LOOP_CLAMP_VALUE (RW) - * - * osc loop clamp value when osc ring active. - * 0: clamp 0. - * 1: clamp 1. - */ -#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK (0x20000UL) -#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT (17U) -#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) -#define PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_MASK) >> PLA_CHN_CFG_FF_OSC_LOOP_CLAMP_VALUE_SHIFT) - -/* - * DIS_OSC_LOOP_CLAMP (RW) - * - * disable osc loop clamp. - * 0: enable osc loop clamp when osc ring active. - * 1: disable or clean current osc loop clamp. - */ -#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK (0x10000UL) -#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT (16U) -#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) -#define PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_MASK) >> PLA_CHN_CFG_FF_DIS_OSC_LOOP_CLAMP_SHIFT) - -/* - * SEL_ADDER_MINUS (RW) - * - * 0: select adder when cfg_adder_minus active. - * 1: select minus when cfg_adder_minus active. - */ -#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK (0x10U) -#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT (4U) -#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) -#define PLA_CHN_CFG_FF_SEL_ADDER_MINUS_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_ADDER_MINUS_MASK) >> PLA_CHN_CFG_FF_SEL_ADDER_MINUS_SHIFT) - -/* - * SEL_CLK_SOURCE (RW) - * - * cfg_ff clock source. - * 0: system clock. - * 1: use 3rd_filter_2 as clock. - */ -#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK (0x8U) -#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT (3U) -#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) -#define PLA_CHN_CFG_FF_SEL_CLK_SOURCE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CLK_SOURCE_MASK) >> PLA_CHN_CFG_FF_SEL_CLK_SOURCE_SHIFT) - -/* - * SEL_CFG_FF_TYPE (RW) - * - * cfg_ff type. - * 0: DFF. - * 1: 3rd_filter_0. - * 2: dual-edge DFF. - * 3: Trigger FF. - * 4: JK FF. - * 5. latch. - * 6: full adder/minus. - */ -#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK (0x7U) -#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT (0U) -#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) -#define PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_MASK) >> PLA_CHN_CFG_FF_SEL_CFG_FF_TYPE_SHIFT) - -/* Bitfield definition for register array: FILTER_1ST_PLA_IN */ -/* - * FILTER_EXT_COUNTER (RW) - * - * filter_ext counter value, cycles for filter or extent by system clock。 - * 0：0*apb_clk_period - * 1：1*apb_clk_period - * 2: 2*apb_clk_period - * … - * 65535: 65535*apb_clk_period - */ -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT (16U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_COUNTER_SHIFT) - -/* - * FILTER_EXT_TYPE (RW) - * - * filter extend type. - * 0-3：nothing to do. - * 4： input high level extend. - * 5： input low level extend. - * 6： output extend. - * 7： input pulse extend. - */ -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK (0x7000U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT (12U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_TYPE_SHIFT) - -/* - * FILTER_EXT_ENABLE (RW) - * - * filter extend enable. - * 0. bypass filter extend. all setting in bit31:12 are inactive - * 1. enable filter extend, all setting in bit31:12 are active. - */ -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK (0x100U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT (8U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_EXT_ENABLE_SHIFT) - -/* - * FILTER_SYNC_LEVEL (RW) - * - * synchroniser level. - * 0: 2 level sync. - * 1: 3 level sync - */ -#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK (0x80U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT (7U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) -#define PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_SYNC_LEVEL_SHIFT) - -/* - * POSE_EDGE_DECT_ENABLE (RW) - * - * pose edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK (0x40U) -#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT (6U) -#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_POSE_EDGE_DECT_ENABLE_SHIFT) - -/* - * NEGE_EDGE_DECT_ENABLE (RW) - * - * nege edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) -#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) -#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_NEGE_EDGE_DECT_ENABLE_SHIFT) - -/* - * EDGE_DECT_ENABLE (RW) - * - * edge detector enable. - * 0: disable. bit6/bit5 setting inactive. - * 1: enable. bit6/bit5 setting active. - */ -#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK (0x10U) -#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT (4U) -#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_EDGE_DECT_ENABLE_SHIFT) - -/* - * FILTER_REVERSE (RW) - * - * reverse sync and edge detector filter's output. - * 0: not reverse. - * 1: reverse. - */ -#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK (0x8U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT (3U) -#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) -#define PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_IN_FILTER_REVERSE_SHIFT) - -/* - * SOFTWARE_INJECT (RW) - * - * software inject value for sync and edge detector filter. - * 0: inject low level. - * 1: inject high level. - * 2: not inject. - * 3. inject high level. - */ -#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK (0x6U) -#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT (1U) -#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) -#define PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_IN_SOFTWARE_INJECT_SHIFT) - -/* - * SYNC_EDGE_FILTER_ENABLE (RW) - * - * sync and edge detector filter. - * 0: disable. - * 1: enable. - */ -#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) -#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) -#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_IN_SYNC_EDGE_FILTER_ENABLE_SHIFT) - -/* Bitfield definition for register array: FILTER_1ST_PLA_OUT */ -/* - * FILTER_EXT_COUNTER (RW) - * - * filter_ext counter value, cycles for filter or extent by system clock。 - * 0：0*apb_clk_period - * 1：1*apb_clk_period - * 2: 2*apb_clk_period - * … - * 65535: 65535*apb_clk_period - */ -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK (0xFFFF0000UL) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT (16U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_COUNTER_SHIFT) - -/* - * FILTER_EXT_TYPE (RW) - * - * filter extend type. - * 0-3：nothing to do. - * 4： input high level extend. - * 5： input low level extend. - * 6： output extend. - * 7： input pulse extend. - */ -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK (0x7000U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT (12U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_TYPE_SHIFT) - -/* - * FILTER_EXT_ENABLE (RW) - * - * filter extend enable. - * 0. bypass filter extend. all setting in bit31:12 are inactive - * 1. enable filter extend, all setting in bit31:12 are active. - */ -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK (0x100U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT (8U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_EXT_ENABLE_SHIFT) - -/* - * FILTER_SYNC_LEVEL (RW) - * - * synchroniser level. - * 0: 2 level sync. - * 1: 3 level sync - */ -#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK (0x80U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT (7U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_SYNC_LEVEL_SHIFT) - -/* - * POSE_EDGE_DECT_ENABLE (RW) - * - * pose edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK (0x40U) -#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT (6U) -#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_POSE_EDGE_DECT_ENABLE_SHIFT) - -/* - * NEGE_EDGE_DECT_ENABLE (RW) - * - * nege edge detector enable. - * 0: disable. - * 1: enable. - */ -#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK (0x20U) -#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT (5U) -#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_NEGE_EDGE_DECT_ENABLE_SHIFT) - -/* - * EDGE_DECT_ENABLE (RW) - * - * edge detector enable. - * 0: disable. bit6/bit5 setting inactive. - * 1: enable. bit6/bit5 setting active. - */ -#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK (0x10U) -#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT (4U) -#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_EDGE_DECT_ENABLE_SHIFT) - -/* - * FILTER_REVERSE (RW) - * - * reverse sync and edge detector filter's output. - * 0: not reverse. - * 1: reverse. - */ -#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK (0x8U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT (3U) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_MASK) >> PLA_FILTER_1ST_PLA_OUT_FILTER_REVERSE_SHIFT) - -/* - * SOFTWARE_INJECT (RW) - * - * software inject value for sync and edge detector filter. - * 0: inject low level. - * 1: inject high level. - * 2: not inject. - * 3. inject high level. - */ -#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK (0x6U) -#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT (1U) -#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) -#define PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_MASK) >> PLA_FILTER_1ST_PLA_OUT_SOFTWARE_INJECT_SHIFT) - -/* - * SYNC_EDGE_FILTER_ENABLE (RW) - * - * sync and edge detector filter. - * 0: disable. - * 1: enable. - */ -#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK (0x1U) -#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT (0U) -#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SET(x) (((uint32_t)(x) << PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) -#define PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_GET(x) (((uint32_t)(x) & PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_MASK) >> PLA_FILTER_1ST_PLA_OUT_SYNC_EDGE_FILTER_ENABLE_SHIFT) - -/* Bitfield definition for register array: CHN_CFG_ACTIVE */ -/* - * CFG_ACTIVE (RW) - * - * write 0xF00D to enable all setting. Otherwire, all setting inactive. - */ -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK (0xFFFFU) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT (0U) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SET(x) (((uint32_t)(x) << PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_GET(x) (((uint32_t)(x) & PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_MASK) >> PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_SHIFT) - - - -/* AOI_16TO8 register group index macro definition */ -#define PLA_CHN_AOI_16TO8_AOI_16TO8_00 (0UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_01 (1UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_02 (2UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_03 (3UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_04 (4UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_05 (5UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_06 (6UL) -#define PLA_CHN_AOI_16TO8_AOI_16TO8_07 (7UL) - -/* FILTER_2ND register group index macro definition */ -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_0 (0UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_1 (1UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_2 (2UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_3 (3UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_4 (4UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_5 (5UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_6 (6UL) -#define PLA_CHN_FILTER_2ND_SECOND_FILTER_7 (7UL) - -/* FILTER_3RD register group index macro definition */ -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_0 (0UL) -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_1 (1UL) -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_2 (2UL) -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_3 (3UL) -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_4 (4UL) -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_5 (5UL) -#define PLA_CHN_FILTER_3RD_THIRD_FILTER_6 (6UL) - -/* CHN register group index macro definition */ -#define PLA_CHN_0 (0UL) -#define PLA_CHN_1 (1UL) -#define PLA_CHN_2 (2UL) -#define PLA_CHN_3 (3UL) -#define PLA_CHN_4 (4UL) -#define PLA_CHN_5 (5UL) -#define PLA_CHN_6 (6UL) -#define PLA_CHN_7 (7UL) - -/* FILTER_1ST_PLA_IN register group index macro definition */ -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_0 (0UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_1 (1UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_2 (2UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_3 (3UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_4 (4UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_5 (5UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_6 (6UL) -#define PLA_FILTER_1ST_PLA_IN_FRIST_FILTER_PLA_IN_7 (7UL) - -/* FILTER_1ST_PLA_OUT register group index macro definition */ -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_IN_0 (0UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_0 (0UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_1 (1UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_2 (2UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_3 (3UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_4 (4UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_5 (5UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_6 (6UL) -#define PLA_FILTER_1ST_PLA_OUT_FRIST_FILTER_PLA_OUT_7 (7UL) - -/* CHN_CFG_ACTIVE register group index macro definition */ -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN0 (0UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN1 (1UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN2 (2UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN3 (3UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN4 (4UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN5 (5UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN6 (6UL) -#define PLA_CHN_CFG_ACTIVE_CFG_ACTIVE_CHN7 (7UL) - - -#endif /* HPM_PLA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_plic_regs.h deleted file mode 100644 index eb5a6504d9c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_plic_regs.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_H -#define HPM_PLIC_H - -typedef struct { - __RW uint32_t FEATURE; /* 0x0: Feature enable register */ - __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ - __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ - __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ - __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ - __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ - __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ - __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ - __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ - __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ - struct { - __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ - __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ - } TARGETINT[2]; - __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */ - struct { - __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ - __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ - __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ - __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ - __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ - } TARGETCONFIG[2]; -} PLIC_Type; - - -/* Bitfield definition for register: FEATURE */ -/* - * VECTORED (RW) - * - * Vector mode enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_VECTORED_MASK (0x2U) -#define PLIC_FEATURE_VECTORED_SHIFT (1U) -#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) -#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) - -/* - * PREEMPT (RW) - * - * Preemptive priority interrupt enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_PREEMPT_MASK (0x1U) -#define PLIC_FEATURE_PREEMPT_SHIFT (0U) -#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) -#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) - -/* Bitfield definition for register array: PRIORITY */ -/* - * PRIORITY (RW) - * - * Interrupt source priority. The valid range of this field is 0-7. - * 0: Never interrupt - * 1-7: Interrupt source priority. The larger the value, the higher the priority. - */ -#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) -#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) -#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) -#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) - -/* Bitfield definition for register array: PENDING */ -/* - * INTERRUPT (RW) - * - * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - */ -#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_PENDING_INTERRUPT_SHIFT (0U) -#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) -#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register array: TRIGGER */ -/* - * INTERRUPT (RO) - * - * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. - * 0: Level-triggered interrupt - * 1: Edge-triggered interrupt - */ -#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) -#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) - -/* Bitfield definition for register: NUMBER */ -/* - * NUM_TARGET (RO) - * - * The number of supported targets - */ -#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) -#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) -#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) - -/* - * NUM_INTERRUPT (RO) - * - * The number of supported interrupt sources - */ -#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) -#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) -#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INFO */ -/* - * MAX_PRIORITY (RO) - * - * The maximum priority supported - */ -#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) -#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) -#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) - -/* - * VERSION (RO) - * - * The version of the PLIC design - */ -#define PLIC_INFO_VERSION_MASK (0xFFFFU) -#define PLIC_INFO_VERSION_SHIFT (0U) -#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) - -/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ -/* - * INTERRUPT (RW) - * - * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - */ -#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) -#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ -/* - * THRESHOLD (RW) - * - * Interrupt priority threshold. - */ -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ -/* - * PRIORITY_PREEMPTED (RW) - * - * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - */ -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) - - - -/* PRIORITY register group index macro definition */ -#define PLIC_PRIORITY_PRIORITY1 (0UL) -#define PLIC_PRIORITY_PRIORITY2 (1UL) -#define PLIC_PRIORITY_PRIORITY3 (2UL) -#define PLIC_PRIORITY_PRIORITY4 (3UL) -#define PLIC_PRIORITY_PRIORITY5 (4UL) -#define PLIC_PRIORITY_PRIORITY6 (5UL) -#define PLIC_PRIORITY_PRIORITY7 (6UL) -#define PLIC_PRIORITY_PRIORITY8 (7UL) -#define PLIC_PRIORITY_PRIORITY9 (8UL) -#define PLIC_PRIORITY_PRIORITY10 (9UL) -#define PLIC_PRIORITY_PRIORITY11 (10UL) -#define PLIC_PRIORITY_PRIORITY12 (11UL) -#define PLIC_PRIORITY_PRIORITY13 (12UL) -#define PLIC_PRIORITY_PRIORITY14 (13UL) -#define PLIC_PRIORITY_PRIORITY15 (14UL) -#define PLIC_PRIORITY_PRIORITY16 (15UL) -#define PLIC_PRIORITY_PRIORITY17 (16UL) -#define PLIC_PRIORITY_PRIORITY18 (17UL) -#define PLIC_PRIORITY_PRIORITY19 (18UL) -#define PLIC_PRIORITY_PRIORITY20 (19UL) -#define PLIC_PRIORITY_PRIORITY21 (20UL) -#define PLIC_PRIORITY_PRIORITY22 (21UL) -#define PLIC_PRIORITY_PRIORITY23 (22UL) -#define PLIC_PRIORITY_PRIORITY24 (23UL) -#define PLIC_PRIORITY_PRIORITY25 (24UL) -#define PLIC_PRIORITY_PRIORITY26 (25UL) -#define PLIC_PRIORITY_PRIORITY27 (26UL) -#define PLIC_PRIORITY_PRIORITY28 (27UL) -#define PLIC_PRIORITY_PRIORITY29 (28UL) -#define PLIC_PRIORITY_PRIORITY30 (29UL) -#define PLIC_PRIORITY_PRIORITY31 (30UL) -#define PLIC_PRIORITY_PRIORITY32 (31UL) -#define PLIC_PRIORITY_PRIORITY33 (32UL) -#define PLIC_PRIORITY_PRIORITY34 (33UL) -#define PLIC_PRIORITY_PRIORITY35 (34UL) -#define PLIC_PRIORITY_PRIORITY36 (35UL) -#define PLIC_PRIORITY_PRIORITY37 (36UL) -#define PLIC_PRIORITY_PRIORITY38 (37UL) -#define PLIC_PRIORITY_PRIORITY39 (38UL) -#define PLIC_PRIORITY_PRIORITY40 (39UL) -#define PLIC_PRIORITY_PRIORITY41 (40UL) -#define PLIC_PRIORITY_PRIORITY42 (41UL) -#define PLIC_PRIORITY_PRIORITY43 (42UL) -#define PLIC_PRIORITY_PRIORITY44 (43UL) -#define PLIC_PRIORITY_PRIORITY45 (44UL) -#define PLIC_PRIORITY_PRIORITY46 (45UL) -#define PLIC_PRIORITY_PRIORITY47 (46UL) -#define PLIC_PRIORITY_PRIORITY48 (47UL) -#define PLIC_PRIORITY_PRIORITY49 (48UL) -#define PLIC_PRIORITY_PRIORITY50 (49UL) -#define PLIC_PRIORITY_PRIORITY51 (50UL) -#define PLIC_PRIORITY_PRIORITY52 (51UL) -#define PLIC_PRIORITY_PRIORITY53 (52UL) -#define PLIC_PRIORITY_PRIORITY54 (53UL) -#define PLIC_PRIORITY_PRIORITY55 (54UL) -#define PLIC_PRIORITY_PRIORITY56 (55UL) -#define PLIC_PRIORITY_PRIORITY57 (56UL) -#define PLIC_PRIORITY_PRIORITY58 (57UL) -#define PLIC_PRIORITY_PRIORITY59 (58UL) -#define PLIC_PRIORITY_PRIORITY60 (59UL) -#define PLIC_PRIORITY_PRIORITY61 (60UL) -#define PLIC_PRIORITY_PRIORITY62 (61UL) -#define PLIC_PRIORITY_PRIORITY63 (62UL) -#define PLIC_PRIORITY_PRIORITY64 (63UL) -#define PLIC_PRIORITY_PRIORITY65 (64UL) -#define PLIC_PRIORITY_PRIORITY66 (65UL) -#define PLIC_PRIORITY_PRIORITY67 (66UL) -#define PLIC_PRIORITY_PRIORITY68 (67UL) -#define PLIC_PRIORITY_PRIORITY69 (68UL) -#define PLIC_PRIORITY_PRIORITY70 (69UL) -#define PLIC_PRIORITY_PRIORITY71 (70UL) -#define PLIC_PRIORITY_PRIORITY72 (71UL) -#define PLIC_PRIORITY_PRIORITY73 (72UL) -#define PLIC_PRIORITY_PRIORITY74 (73UL) -#define PLIC_PRIORITY_PRIORITY75 (74UL) -#define PLIC_PRIORITY_PRIORITY76 (75UL) -#define PLIC_PRIORITY_PRIORITY77 (76UL) -#define PLIC_PRIORITY_PRIORITY78 (77UL) -#define PLIC_PRIORITY_PRIORITY79 (78UL) -#define PLIC_PRIORITY_PRIORITY80 (79UL) -#define PLIC_PRIORITY_PRIORITY81 (80UL) -#define PLIC_PRIORITY_PRIORITY82 (81UL) -#define PLIC_PRIORITY_PRIORITY83 (82UL) -#define PLIC_PRIORITY_PRIORITY84 (83UL) -#define PLIC_PRIORITY_PRIORITY85 (84UL) -#define PLIC_PRIORITY_PRIORITY86 (85UL) -#define PLIC_PRIORITY_PRIORITY87 (86UL) -#define PLIC_PRIORITY_PRIORITY88 (87UL) -#define PLIC_PRIORITY_PRIORITY89 (88UL) -#define PLIC_PRIORITY_PRIORITY90 (89UL) -#define PLIC_PRIORITY_PRIORITY91 (90UL) -#define PLIC_PRIORITY_PRIORITY92 (91UL) -#define PLIC_PRIORITY_PRIORITY93 (92UL) -#define PLIC_PRIORITY_PRIORITY94 (93UL) -#define PLIC_PRIORITY_PRIORITY95 (94UL) -#define PLIC_PRIORITY_PRIORITY96 (95UL) -#define PLIC_PRIORITY_PRIORITY97 (96UL) -#define PLIC_PRIORITY_PRIORITY98 (97UL) -#define PLIC_PRIORITY_PRIORITY99 (98UL) -#define PLIC_PRIORITY_PRIORITY100 (99UL) -#define PLIC_PRIORITY_PRIORITY101 (100UL) -#define PLIC_PRIORITY_PRIORITY102 (101UL) -#define PLIC_PRIORITY_PRIORITY103 (102UL) -#define PLIC_PRIORITY_PRIORITY104 (103UL) -#define PLIC_PRIORITY_PRIORITY105 (104UL) -#define PLIC_PRIORITY_PRIORITY106 (105UL) -#define PLIC_PRIORITY_PRIORITY107 (106UL) -#define PLIC_PRIORITY_PRIORITY108 (107UL) -#define PLIC_PRIORITY_PRIORITY109 (108UL) -#define PLIC_PRIORITY_PRIORITY110 (109UL) -#define PLIC_PRIORITY_PRIORITY111 (110UL) -#define PLIC_PRIORITY_PRIORITY112 (111UL) -#define PLIC_PRIORITY_PRIORITY113 (112UL) -#define PLIC_PRIORITY_PRIORITY114 (113UL) -#define PLIC_PRIORITY_PRIORITY115 (114UL) -#define PLIC_PRIORITY_PRIORITY116 (115UL) -#define PLIC_PRIORITY_PRIORITY117 (116UL) -#define PLIC_PRIORITY_PRIORITY118 (117UL) -#define PLIC_PRIORITY_PRIORITY119 (118UL) -#define PLIC_PRIORITY_PRIORITY120 (119UL) -#define PLIC_PRIORITY_PRIORITY121 (120UL) -#define PLIC_PRIORITY_PRIORITY122 (121UL) -#define PLIC_PRIORITY_PRIORITY123 (122UL) -#define PLIC_PRIORITY_PRIORITY124 (123UL) -#define PLIC_PRIORITY_PRIORITY125 (124UL) -#define PLIC_PRIORITY_PRIORITY126 (125UL) -#define PLIC_PRIORITY_PRIORITY127 (126UL) - -/* PENDING register group index macro definition */ -#define PLIC_PENDING_PENDING0 (0UL) -#define PLIC_PENDING_PENDING1 (1UL) -#define PLIC_PENDING_PENDING2 (2UL) -#define PLIC_PENDING_PENDING3 (3UL) - -/* TRIGGER register group index macro definition */ -#define PLIC_TRIGGER_TRIGGER0 (0UL) -#define PLIC_TRIGGER_TRIGGER1 (1UL) -#define PLIC_TRIGGER_TRIGGER2 (2UL) -#define PLIC_TRIGGER_TRIGGER3 (3UL) - -/* INTEN register group index macro definition */ -#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) -#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) -#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) -#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) - -/* TARGETINT register group index macro definition */ -#define PLIC_TARGETINT_TARGET0 (0UL) -#define PLIC_TARGETINT_TARGET1 (1UL) - -/* TARGETCONFIG register group index macro definition */ -#define PLIC_TARGETCONFIG_TARGET0 (0UL) -#define PLIC_TARGETCONFIG_TARGET1 (1UL) - - -#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_plic_sw_regs.h deleted file mode 100644 index 998dafa2d57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_plic_sw_regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_SW_H -#define HPM_PLIC_SW_H - -typedef struct { - __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ - __RW uint32_t PENDING; /* 0x1000: Pending status */ - __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ - __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ - __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ - __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ -} PLIC_SW_Type; - - -/* Bitfield definition for register: PENDING */ -/* - * INTERRUPT (RW) - * - * writing 1 to trigger software interrupt - */ -#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) -#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) -#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) -#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * INTERRUPT (RW) - * - * enable software interrupt - */ -#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) -#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) -#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) - - - - -#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pllctlv2_regs.h deleted file mode 100644 index f9bdd046b74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pllctlv2_regs.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLLCTLV2_H -#define HPM_PLLCTLV2_H - -typedef struct { - __RW uint32_t XTAL; /* 0x0: OSC configuration */ - __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ - struct { - __RW uint32_t MFI; /* 0x80: PLL0 multiple register */ - __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */ - __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */ - __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */ - __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */ - __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */ - __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */ - __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */ - __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */ - __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ - __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ - __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ - } PLL[3]; -} PLLCTLV2_Type; - - -/* Bitfield definition for register: XTAL */ -/* - * BUSY (RO) - * - * Busy flag - * 0: Oscillator is working or shutdown - * 1: Oscillator is changing status - */ -#define PLLCTLV2_XTAL_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_XTAL_BUSY_SHIFT (31U) -#define PLLCTLV2_XTAL_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTLV2_XTAL_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_XTAL_RESPONSE_SHIFT (29U) -#define PLLCTLV2_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTLV2_XTAL_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_XTAL_ENABLE_SHIFT (28U) -#define PLLCTLV2_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT) - -/* - * RAMP_TIME (RW) - * - * Rampup time of XTAL oscillator in cycles of RC24M clock - * 0: 0 cycle - * 1: 1 cycle - * 2: 2 cycle - * 1048575: 1048575 cycles - */ -#define PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) -#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) -#define PLLCTLV2_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK) -#define PLLCTLV2_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFI */ -/* - * BUSY (RO) - * - * Busy flag - * 0: PLL is stable or shutdown - * 1: PLL is changing status - */ -#define PLLCTLV2_PLL_MFI_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_MFI_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_MFI_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * PLL status - * 0: PLL is not stable - * 1: PLL is stable for use - */ -#define PLLCTLV2_PLL_MFI_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_MFI_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * PLL enable status - * 0: PLL is off - * 1: PLL is on - */ -#define PLLCTLV2_PLL_MFI_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_MFI_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT) - -/* - * MFI (RW) - * - * loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) - * 0-15: invalid - * 16: divide by 16 - * 17: divide by17 - * . . . - * 42: divide by 42 - * 43~:invalid - */ -#define PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) -#define PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) -#define PLLCTLV2_PLL_MFI_MFI_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK) -#define PLLCTLV2_PLL_MFI_MFI_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFN */ -/* - * MFN (RW) - * - * Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - */ -#define PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) -#define PLLCTLV2_PLL_MFN_MFN_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK) -#define PLLCTLV2_PLL_MFN_MFN_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFD */ -/* - * MFD (RW) - * - * Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - */ -#define PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) -#define PLLCTLV2_PLL_MFD_MFD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK) -#define PLLCTLV2_PLL_MFD_MFD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STEP */ -/* - * STEP (RW) - * - * Step of spread spectrum modulator. - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STEP_STEP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) -#define PLLCTLV2_PLL_SS_STEP_STEP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STOP */ -/* - * STOP (RW) - * - * Stop point of spread spectrum modulator - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STOP_STOP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) -#define PLLCTLV2_PLL_SS_STOP_STOP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) - -/* Bitfield definition for register of struct array PLL: CONFIG */ -/* - * SPREAD (RW) - * - * Enable spread spectrum function. This field supports changing during PLL running. - */ -#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK (0x100U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT (8U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) -#define PLLCTLV2_PLL_CONFIG_SPREAD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) - -/* - * REFSEL (RW) - * - * Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. - * 0: XTAL24M - * 1: IRC24M - */ -#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK (0x1U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT (0U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) -#define PLLCTLV2_PLL_CONFIG_REFSEL_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) - -/* Bitfield definition for register of struct array PLL: LOCKTIME */ -/* - * LOCKTIME (RW) - * - * Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - */ -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: STEPTIME */ -/* - * STEPTIME (RW) - * - * Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - */ -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: ADVANCED */ -/* - * SLOW (RW) - * - * Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. - * 0: fast lock enabled, lock time is 100us - * 1: fast lock disabled, lock time is 400us - */ -#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK (0x10000000UL) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT (28U) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) -#define PLLCTLV2_PLL_ADVANCED_SLOW_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither function - */ -#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK (0x1000000UL) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT (24U) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) -#define PLLCTLV2_PLL_ADVANCED_DITHER_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV0 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTLV2_PLL_DIV_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_DIV_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Divider response status - * 0: Divider is not stable - * 1: Divider is stable for use - */ -#define PLLCTLV2_PLL_DIV_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Divider enable status - * 0: Divider is off - * 1: Divider is on - */ -#define PLLCTLV2_PLL_DIV_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider factor, divider factor is DIV/5 + 1 - * 0: divide by 1 - * 1: divide by 1.2 - * 2: divide by 1.4 - * . . . - * 63: divide by 13.6 - */ -#define PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) -#define PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) -#define PLLCTLV2_PLL_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK) -#define PLLCTLV2_PLL_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT) - - - -/* DIV register group index macro definition */ -#define PLLCTLV2_PLL_DIV_DIV0 (0UL) -#define PLLCTLV2_PLL_DIV_DIV1 (1UL) -#define PLLCTLV2_PLL_DIV_DIV2 (2UL) - -/* PLL register group index macro definition */ -#define PLLCTLV2_PLL_PLL0 (0UL) -#define PLLCTLV2_PLL_PLL1 (1UL) -#define PLLCTLV2_PLL_PLL2 (2UL) - - -#endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pmon_regs.h deleted file mode 100644 index 7e3a0798d2a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pmon_regs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMON_H -#define HPM_PMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[4]; - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - __RW uint32_t IRQ_FLAG; /* 0x40: */ - __RW uint32_t IRQ_ENABLE; /* 0x44: */ -} PMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define PMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define PMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define PMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ACTIVE_SHIFT) & PMON_MONITOR_CONTROL_ACTIVE_MASK) -#define PMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ACTIVE_MASK) >> PMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define PMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define PMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define PMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ENABLE_SHIFT) & PMON_MONITOR_CONTROL_ENABLE_MASK) -#define PMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ENABLE_MASK) >> PMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define PMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define PMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define PMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << PMON_MONITOR_STATUS_FLAG_SHIFT) & PMON_MONITOR_STATUS_FLAG_MASK) -#define PMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & PMON_MONITOR_STATUS_FLAG_MASK) >> PMON_MONITOR_STATUS_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_FLAG */ -/* - * FLAG (RW) - * - * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt - * 1: monitor interrupt happened - */ -#define PMON_IRQ_FLAG_FLAG_MASK (0xFU) -#define PMON_IRQ_FLAG_FLAG_SHIFT (0U) -#define PMON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << PMON_IRQ_FLAG_FLAG_SHIFT) & PMON_IRQ_FLAG_FLAG_MASK) -#define PMON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & PMON_IRQ_FLAG_FLAG_MASK) >> PMON_IRQ_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * ENABLE (RW) - * - * interrupt enable, each bit represents for one monitor - * 0: monitor interrupt disabled - * 1: monitor interrupt enabled - */ -#define PMON_IRQ_ENABLE_ENABLE_MASK (0xFU) -#define PMON_IRQ_ENABLE_ENABLE_SHIFT (0U) -#define PMON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PMON_IRQ_ENABLE_ENABLE_SHIFT) & PMON_IRQ_ENABLE_ENABLE_MASK) -#define PMON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PMON_IRQ_ENABLE_ENABLE_MASK) >> PMON_IRQ_ENABLE_ENABLE_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define PMON_MONITOR_GLITCH0 (0UL) -#define PMON_MONITOR_GLITCH1 (1UL) -#define PMON_MONITOR_CLOCK0 (2UL) -#define PMON_MONITOR_CLOCK1 (3UL) - - -#endif /* HPM_PMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ppor_regs.h deleted file mode 100644 index 7ce378b07da..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ppor_regs.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPOR_H -#define HPM_PPOR_H - -typedef struct { - __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ - __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ - __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ - __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ - __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ - __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ - __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ - __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ -} PPOR_Type; - - -/* Bitfield definition for register: RESET_FLAG */ -/* - * FLAG (W1C) - * - * reset reason of last hard reset, write 1 to clear each bit - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) -#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) -#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: RESET_STATUS */ -/* - * STATUS (RW) - * - * current status of reset sources - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) -#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) -#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_HOLD */ -/* - * STATUS (RW) - * - * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) -#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) -#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_ENABLE */ -/* - * ENABLE (RW) - * - * enable of reset sources - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) -#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) -#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) - -/* Bitfield definition for register: RESET_HOT */ -/* - * TYPE (RW) - * - * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOT_TYPE_SHIFT (0U) -#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) -#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) - -/* Bitfield definition for register: RESET_COLD */ -/* - * FLAG (RW) - * - * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_COLD_FLAG_SHIFT (0U) -#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) -#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) - -/* Bitfield definition for register: SOFTWARE_RESET */ -/* - * COUNTER (RW) - * - * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - */ -#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) -#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) -#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) -#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) - - - - -#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_psec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_psec_regs.h deleted file mode 100644 index a848fbf5d13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_psec_regs.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PSEC_H -#define HPM_PSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ - __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ -} PSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define PSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define PSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define PSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_NSC_MASK) >> PSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define PSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define PSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define PSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_SEC_MASK) >> PSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * PMIC_FAIL (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define PSEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) -#define PSEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) >> PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) - -/* - * PMIC_NSC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define PSEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) -#define PSEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) -#define PSEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_NSC_SHIFT) & PSEC_SECURE_STATE_PMIC_NSC_MASK) -#define PSEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_NSC_MASK) >> PSEC_SECURE_STATE_PMIC_NSC_SHIFT) - -/* - * PMIC_SEC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define PSEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) -#define PSEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) -#define PSEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_SEC_SHIFT) & PSEC_SECURE_STATE_PMIC_SEC_MASK) -#define PSEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_SEC_MASK) >> PSEC_SECURE_STATE_PMIC_SEC_SHIFT) - -/* - * PMIC_INS (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define PSEC_SECURE_STATE_PMIC_INS_MASK (0x10U) -#define PSEC_SECURE_STATE_PMIC_INS_SHIFT (4U) -#define PSEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_INS_SHIFT) & PSEC_SECURE_STATE_PMIC_INS_MASK) -#define PSEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_INS_MASK) >> PSEC_SECURE_STATE_PMIC_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define PSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define PSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define PSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define PSEC_EVENT_EVENT_SHIFT (16U) -#define PSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & PSEC_EVENT_EVENT_MASK) >> PSEC_EVENT_EVENT_SHIFT) - -/* - * PMIC_ESC_NSC (RO) - * - * PMIC is escalating non-secure event - */ -#define PSEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) -#define PSEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) -#define PSEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_NSC_MASK) >> PSEC_EVENT_PMIC_ESC_NSC_SHIFT) - -/* - * PMIC_ESC_SEC (RO) - * - * PMIC is escalting secure event - */ -#define PSEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) -#define PSEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) -#define PSEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_SEC_MASK) >> PSEC_EVENT_PMIC_ESC_SEC_SHIFT) - -/* Bitfield definition for register: LIFECYCLE */ -/* - * LIFECYCLE (RO) - * - * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, - * bit0: lifecycle_unknow - */ -#define PSEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) -#define PSEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) -#define PSEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & PSEC_LIFECYCLE_LIFECYCLE_MASK) >> PSEC_LIFECYCLE_LIFECYCLE_SHIFT) - - - - -#endif /* HPM_PSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ptpc_regs.h deleted file mode 100644 index 5d9609c0c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_ptpc_regs.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PTPC_H -#define HPM_PTPC_H - -typedef struct { - struct { - __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ - __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ - __R uint32_t TIMEH; /* 0x8: timestamp high */ - __R uint32_t TIMEL; /* 0xC: timestamp low */ - __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ - __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ - __RW uint32_t ADDEND; /* 0x18: */ - __RW uint32_t TARH; /* 0x1C: */ - __RW uint32_t TARL; /* 0x20: */ - __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ - __RW uint32_t PPS_CTRL; /* 0x2C: */ - __R uint32_t CAPT_SNAPH; /* 0x30: */ - __RW uint32_t CAPT_SNAPL; /* 0x34: */ - __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ - } PTPC[2]; - __RW uint32_t TIME_SEL; /* 0x2000: */ - __W uint32_t INT_STS; /* 0x2004: */ - __RW uint32_t INT_EN; /* 0x2008: */ - __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ - __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ -} PTPC_Type; - - -/* Bitfield definition for register of struct array PTPC: CTRL0 */ -/* - * SUBSEC_DIGITAL_ROLLOVER (RW) - * - * Format for ns counter rollover, - * 1-digital, overflow time 1000000000/0x3B9ACA00 - * 0-binary, overflow time 0x7FFFFFFF - */ -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) - -/* - * CAPT_SNAP_KEEP (RW) - * - * set will keep capture snap till software read capt_snapl. - * If this bit is set, software should read capt_snaph first to avoid wrong result. - * If this bit is cleared, capture result will be updated at each capture event - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) - -/* - * CAPT_SNAP_POS_EN (RW) - * - * set will use posege of input capture signal to latch timestamp value - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) - -/* - * CAPT_SNAP_NEG_EN (RW) - * - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - -/* - * COMP_EN (RW) - * - * set to enable compare, will be cleared by HW when compare event triggered - */ -#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) -#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) -#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) -#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) - -/* - * UPDATE_TIMER (WO) - * - * update timer with +/- ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) - -/* - * INIT_TIMER (WO) - * - * initial timer with ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) -#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) - -/* - * FINE_COARSE_SEL (RW) - * - * 0: coarse update, ns counter add ss_incr[7:0] each clk - * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - */ -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - */ -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CTRL1 */ -/* - * SS_INCR (RW) - * - * constant value used to add ns counter; - * such as for 50MHz timer clock, set it to 8'd20 - */ -#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) -#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) -#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) -#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEH */ -/* - * TIMESTAMP_HIGH (RO) - * - */ -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEL */ -/* - * TIMESTAMP_LOW (RO) - * - */ -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ -/* - * SEC_UPDATE (RW) - * - * together with ts_updtl, used to initial or update timestamp - */ -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ -/* - * ADD_SUB (RW) - * - * 1 for sub; 0 for add, used only at update - */ -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) - -/* - * NS_UPDATE (RW) - * - */ -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: ADDEND */ -/* - * ADDEND (RW) - * - * used in fine update mode only - */ -#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) -#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) -#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARH */ -/* - * TARGET_TIME_HIGH (RW) - * - * used for generate compare signal if enabled - */ -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARL */ -/* - * TARGET_TIME_LOW (RW) - * - */ -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ -/* - * PPS_CTRL (RW) - * - */ -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ -/* - * CAPT_SNAP_HIGH (RO) - * - * take snapshot for input capture signal, at pos or neg or both; - * the result can be kept or updated at each event according to cfg0.bit8 - */ -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ -/* - * CAPT_SNAP_LOW (RW) - * - */ -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) - -/* Bitfield definition for register: TIME_SEL */ -/* - * CAN3_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) - -/* - * CAN2_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) - -/* - * CAN1_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) - -/* - * CAN0_TIME_SEL (RW) - * - * set to use ptpc1 for canx - * clr to use ptpc0 for canx - */ -#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * COMP_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) -#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) -#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) -#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) -#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * COMP_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) -#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) -#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) -#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) -#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: PTPC_CAN_TS_SEL */ -/* - * TSU_TBIN3_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) - -/* - * TSU_TBIN2_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) - -/* - * TSU_TBIN1_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) - -/* - * TSU_TBIN0_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) - - - -/* PTPC register group index macro definition */ -#define PTPC_PTPC_0 (0UL) -#define PTPC_PTPC_1 (1UL) - - -#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pwm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pwm_regs.h deleted file mode 100644 index 0e425dd1b39..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_pwm_regs.h +++ /dev/null @@ -1,1091 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PWM_H -#define HPM_PWM_H - -typedef struct { - __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ - union { - __RW uint32_t STA; /* 0x4: Counter start register */ - __RW uint32_t STA_HRPWM; /* 0x4: Counter start register */ - }; - union { - __RW uint32_t RLD; /* 0x8: Counter reload register */ - __RW uint32_t RLD_HRPWM; /* 0x8: Counter reload register */ - }; - union { - __RW uint32_t CMP[16]; /* 0xC - 0x48: Comparator register */ - __RW uint32_t CMP_HRPWM[16]; /* 0xC - 0x48: Comparator register */ - }; - __R uint8_t RESERVED0[44]; /* 0x4C - 0x77: Reserved */ - __RW uint32_t FRCMD; /* 0x78: Force output mode register */ - __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ - __RW uint32_t CHCFG[16]; /* 0x80 - 0xBC: Output channel configure register */ - __R uint8_t RESERVED1[48]; /* 0xC0 - 0xEF: Reserved */ - __RW uint32_t GCR; /* 0xF0: Global control register */ - __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ - __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ - __R uint32_t CAPPOS[16]; /* 0x100 - 0x13C: Capture rising edge register */ - __R uint8_t RESERVED3[48]; /* 0x140 - 0x16F: Reserved */ - __R uint32_t CNT; /* 0x170: Counter */ - __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ - __R uint32_t CAPNEG[16]; /* 0x180 - 0x1BC: Capture falling edge register */ - __R uint8_t RESERVED5[48]; /* 0x1C0 - 0x1EF: Reserved */ - __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ - __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ - __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ - __W uint32_t SR; /* 0x220: Status register */ - __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ - __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ - __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ - __RW uint32_t CMPCFG[16]; /* 0x230 - 0x26C: Comparator configure register */ - __R uint8_t RESERVED8[400]; /* 0x270 - 0x3FF: Reserved */ - __R uint32_t ANASTS[8]; /* 0x400 - 0x41C: analog status register */ - __RW uint32_t HRPWM_CFG; /* 0x420: hrpwm config register */ - __RW uint32_t ANA_CFG0; /* 0x424: analog config register */ -} PWM_Type; - - -/* Bitfield definition for register: UNLK */ -/* - * SHUNLK (RW) - * - * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, - * otherwise the shadow registers can not be written. - */ -#define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) -#define PWM_UNLK_SHUNLK_SHIFT (0U) -#define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) -#define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * XSTA (RW) - * - * pwm timer counter extended start point, should back to this value after reach xrld - */ -#define PWM_STA_XSTA_MASK (0xF0000000UL) -#define PWM_STA_XSTA_SHIFT (28U) -#define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) -#define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) - -/* - * STA (RW) - * - * pwm timer counter start value - * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - */ -#define PWM_STA_STA_MASK (0xFFFFFF0UL) -#define PWM_STA_STA_SHIFT (4U) -#define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) -#define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) - -/* Bitfield definition for register: STA_HRPWM */ -/* - * STA (RW) - * - */ -#define PWM_STA_HRPWM_STA_MASK (0xFFFFFF00UL) -#define PWM_STA_HRPWM_STA_SHIFT (8U) -#define PWM_STA_HRPWM_STA_SET(x) (((uint32_t)(x) << PWM_STA_HRPWM_STA_SHIFT) & PWM_STA_HRPWM_STA_MASK) -#define PWM_STA_HRPWM_STA_GET(x) (((uint32_t)(x) & PWM_STA_HRPWM_STA_MASK) >> PWM_STA_HRPWM_STA_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * XRLD (RW) - * - * timeout counter extended reload point, counter will reload to xsta after reach this point - */ -#define PWM_RLD_XRLD_MASK (0xF0000000UL) -#define PWM_RLD_XRLD_SHIFT (28U) -#define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) -#define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) - -/* - * RLD (RW) - * - * pwm timer counter reload value - */ -#define PWM_RLD_RLD_MASK (0xFFFFFF0UL) -#define PWM_RLD_RLD_SHIFT (4U) -#define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) -#define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) - -/* Bitfield definition for register: RLD_HRPWM */ -/* - * RLD (RW) - * - */ -#define PWM_RLD_HRPWM_RLD_MASK (0xFFFFFF00UL) -#define PWM_RLD_HRPWM_RLD_SHIFT (8U) -#define PWM_RLD_HRPWM_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_SHIFT) & PWM_RLD_HRPWM_RLD_MASK) -#define PWM_RLD_HRPWM_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_MASK) >> PWM_RLD_HRPWM_RLD_SHIFT) - -/* - * RLD_HR (RW) - * - * pwm timer counter reload value at high resolution, only exist if hwpwm is enabled. - */ -#define PWM_RLD_HRPWM_RLD_HR_MASK (0xFFU) -#define PWM_RLD_HRPWM_RLD_HR_SHIFT (0U) -#define PWM_RLD_HRPWM_RLD_HR_SET(x) (((uint32_t)(x) << PWM_RLD_HRPWM_RLD_HR_SHIFT) & PWM_RLD_HRPWM_RLD_HR_MASK) -#define PWM_RLD_HRPWM_RLD_HR_GET(x) (((uint32_t)(x) & PWM_RLD_HRPWM_RLD_HR_MASK) >> PWM_RLD_HRPWM_RLD_HR_SHIFT) - -/* Bitfield definition for register: 0 */ -/* - * XCMP (RW) - * - * extended counter compare value - */ -#define PWM_CMP_XCMP_MASK (0xF0000000UL) -#define PWM_CMP_XCMP_SHIFT (28U) -#define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) -#define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) - -/* - * CMP (RW) - * - * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, - * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - */ -#define PWM_CMP_CMP_MASK (0xFFFFFF0UL) -#define PWM_CMP_CMP_SHIFT (4U) -#define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) -#define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) - -/* - * CMPHLF (RW) - * - * half clock counter compare value - */ -#define PWM_CMP_CMPHLF_MASK (0x8U) -#define PWM_CMP_CMPHLF_SHIFT (3U) -#define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) -#define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) - -/* - * CMPJIT (RW) - * - * jitter counter compare value - */ -#define PWM_CMP_CMPJIT_MASK (0x7U) -#define PWM_CMP_CMPJIT_SHIFT (0U) -#define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) -#define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) - -/* Bitfield definition for register: 0 */ -/* - * CMP (RW) - * - */ -#define PWM_CMP_HRPWM_CMP_MASK (0xFFFFFF00UL) -#define PWM_CMP_HRPWM_CMP_SHIFT (8U) -#define PWM_CMP_HRPWM_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_SHIFT) & PWM_CMP_HRPWM_CMP_MASK) -#define PWM_CMP_HRPWM_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_MASK) >> PWM_CMP_HRPWM_CMP_SHIFT) - -/* - * CMP_HR (RW) - * - * high resolution compare value - */ -#define PWM_CMP_HRPWM_CMP_HR_MASK (0xFFU) -#define PWM_CMP_HRPWM_CMP_HR_SHIFT (0U) -#define PWM_CMP_HRPWM_CMP_HR_SET(x) (((uint32_t)(x) << PWM_CMP_HRPWM_CMP_HR_SHIFT) & PWM_CMP_HRPWM_CMP_HR_MASK) -#define PWM_CMP_HRPWM_CMP_HR_GET(x) (((uint32_t)(x) & PWM_CMP_HRPWM_CMP_HR_MASK) >> PWM_CMP_HRPWM_CMP_HR_SHIFT) - -/* Bitfield definition for register: FRCMD */ -/* - * FRCMD (RW) - * - * 2bit for each PWM output channel (0-7); - * 00: force output 0 - * 01: force output 1 - * 10: output highz - * 11: no force - */ -#define PWM_FRCMD_FRCMD_MASK (0xFFFFU) -#define PWM_FRCMD_FRCMD_SHIFT (0U) -#define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) -#define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) - -/* Bitfield definition for register: SHLK */ -/* - * SHLK (RW) - * - * write 1 to lock all shawdow register, write access is not permitted - */ -#define PWM_SHLK_SHLK_MASK (0x80000000UL) -#define PWM_SHLK_SHLK_SHIFT (31U) -#define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) -#define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) - -/* Bitfield definition for register array: CHCFG */ -/* - * CMPSELEND (RW) - * - * assign the last comparator for this output channel - */ -#define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) -#define PWM_CHCFG_CMPSELEND_SHIFT (24U) -#define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) -#define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) - -/* - * CMPSELBEG (RW) - * - * assign the first comparator for this output channel - */ -#define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) -#define PWM_CHCFG_CMPSELBEG_SHIFT (16U) -#define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) -#define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) - -/* - * OUTPOL (RW) - * - * output polarity, set to 1 will invert the output - */ -#define PWM_CHCFG_OUTPOL_MASK (0x2U) -#define PWM_CHCFG_OUTPOL_SHIFT (1U) -#define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) -#define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * FAULTI3EN (RW) - * - * 1- enable the internal fault input 3 - */ -#define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) -#define PWM_GCR_FAULTI3EN_SHIFT (31U) -#define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) -#define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) - -/* - * FAULTI2EN (RW) - * - * 1- enable the internal fault input 2 - */ -#define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) -#define PWM_GCR_FAULTI2EN_SHIFT (30U) -#define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) -#define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) - -/* - * FAULTI1EN (RW) - * - * 1- enable the internal fault input 1 - */ -#define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) -#define PWM_GCR_FAULTI1EN_SHIFT (29U) -#define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) -#define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) - -/* - * FAULTI0EN (RW) - * - * 1- enable the internal fault input 0 - */ -#define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) -#define PWM_GCR_FAULTI0EN_SHIFT (28U) -#define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) -#define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) - -/* - * DEBUGFAULT (RW) - * - * 1- enable debug mode output protection - */ -#define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) -#define PWM_GCR_DEBUGFAULT_SHIFT (27U) -#define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) -#define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) - -/* - * FRCPOL (RW) - * - * polarity of input pwm_force, - * 1- active low - * 0- active high - */ -#define PWM_GCR_FRCPOL_MASK (0x4000000UL) -#define PWM_GCR_FRCPOL_SHIFT (26U) -#define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) -#define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) - -/* - * HWSHDWEDG (RW) - * - * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. - * This bit assign its which edge is used as compare shadow register hardware load event. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) -#define PWM_GCR_HWSHDWEDG_SHIFT (24U) -#define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) -#define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) - -/* - * CMPSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load comparator shadow registers - */ -#define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) -#define PWM_GCR_CMPSHDWSEL_SHIFT (19U) -#define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) -#define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) - -/* - * FAULTRECEDG (RW) - * - * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. - * This bit assign its effective edge of fault recover trigger. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) -#define PWM_GCR_FAULTRECEDG_SHIFT (18U) -#define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) -#define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) - -/* - * FAULTRECHWSEL (RW) - * - * Selec one of the 24 comparators as fault output recover trigger. - */ -#define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) -#define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) -#define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) -#define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) - -/* - * FAULTE1EN (RW) - * - * 1- enable the external fault input 1 - */ -#define PWM_GCR_FAULTE1EN_MASK (0x1000U) -#define PWM_GCR_FAULTE1EN_SHIFT (12U) -#define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) -#define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) - -/* - * FAULTE0EN (RW) - * - * 1- enable the external fault input 0 - */ -#define PWM_GCR_FAULTE0EN_MASK (0x800U) -#define PWM_GCR_FAULTE0EN_SHIFT (11U) -#define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) -#define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) - -/* - * FAULTEXPOL (RW) - * - * external fault polarity - * 1-active low - * 0-active high - */ -#define PWM_GCR_FAULTEXPOL_MASK (0x600U) -#define PWM_GCR_FAULTEXPOL_SHIFT (9U) -#define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) -#define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) - -/* - * RLDSYNCEN (RW) - * - * 1- pwm timer counter reset to reload value (rld) by synci is enabled - */ -#define PWM_GCR_RLDSYNCEN_MASK (0x100U) -#define PWM_GCR_RLDSYNCEN_SHIFT (8U) -#define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) -#define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) - -/* - * CEN (RW) - * - * 1- enable the pwm timer counter - * 0- stop the pwm timer counter - */ -#define PWM_GCR_CEN_MASK (0x80U) -#define PWM_GCR_CEN_SHIFT (7U) -#define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) -#define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) - -/* - * FAULTCLR (RW) - * - * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. - * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - */ -#define PWM_GCR_FAULTCLR_MASK (0x40U) -#define PWM_GCR_FAULTCLR_SHIFT (6U) -#define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) -#define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) - -/* - * XRLDSYNCEN (RW) - * - * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - */ -#define PWM_GCR_XRLDSYNCEN_MASK (0x20U) -#define PWM_GCR_XRLDSYNCEN_SHIFT (5U) -#define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) -#define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) - -/* - * HR_PWM_EN (RW) - * - * set to enable high resolution pwm, trig_cmp, start/reload register will have different definition. - */ -#define PWM_GCR_HR_PWM_EN_MASK (0x10U) -#define PWM_GCR_HR_PWM_EN_SHIFT (4U) -#define PWM_GCR_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWM_GCR_HR_PWM_EN_SHIFT) & PWM_GCR_HR_PWM_EN_MASK) -#define PWM_GCR_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWM_GCR_HR_PWM_EN_MASK) >> PWM_GCR_HR_PWM_EN_SHIFT) - -/* - * TIMERRESET (RW) - * - * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear - */ -#define PWM_GCR_TIMERRESET_MASK (0x8U) -#define PWM_GCR_TIMERRESET_SHIFT (3U) -#define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) -#define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) - -/* - * FRCTIME (WO) - * - * This bit field select the force effective time - * 00: force immediately - * 01: force at main counter reload time - * 10: force at FRCSYNCI - * 11: no force - */ -#define PWM_GCR_FRCTIME_MASK (0x6U) -#define PWM_GCR_FRCTIME_SHIFT (1U) -#define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) -#define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) - -/* - * SWFRC (RW) - * - * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - */ -#define PWM_GCR_SWFRC_MASK (0x1U) -#define PWM_GCR_SWFRC_SHIFT (0U) -#define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) -#define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) - -/* Bitfield definition for register: SHCR */ -/* - * CNT_UPDATE_RELOAD (RW) - * - * set to update counter working register at reload point, clear to use cnt_update_time as old version. - */ -#define PWM_SHCR_CNT_UPDATE_RELOAD_MASK (0x8000U) -#define PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT (15U) -#define PWM_SHCR_CNT_UPDATE_RELOAD_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) -#define PWM_SHCR_CNT_UPDATE_RELOAD_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_RELOAD_MASK) >> PWM_SHCR_CNT_UPDATE_RELOAD_SHIFT) - -/* - * CNT_UPDATE_EDGE (RW) - * - * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for counter shadow registers - */ -#define PWM_SHCR_CNT_UPDATE_EDGE_MASK (0x4000U) -#define PWM_SHCR_CNT_UPDATE_EDGE_SHIFT (14U) -#define PWM_SHCR_CNT_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) -#define PWM_SHCR_CNT_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_CNT_UPDATE_EDGE_MASK) >> PWM_SHCR_CNT_UPDATE_EDGE_SHIFT) - -/* - * FORCE_UPDATE_EDGE (RW) - * - * 0 for posedge; 1 for negedge if hardware trigger time is selected for update_time, and selected channel is capture mode, for FRCMD shadow registers - */ -#define PWM_SHCR_FORCE_UPDATE_EDGE_MASK (0x2000U) -#define PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT (13U) -#define PWM_SHCR_FORCE_UPDATE_EDGE_SET(x) (((uint32_t)(x) << PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) -#define PWM_SHCR_FORCE_UPDATE_EDGE_GET(x) (((uint32_t)(x) & PWM_SHCR_FORCE_UPDATE_EDGE_MASK) >> PWM_SHCR_FORCE_UPDATE_EDGE_SHIFT) - -/* - * FRCSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - */ -#define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) -#define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) -#define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) -#define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) - -/* - * CNTSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - */ -#define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) -#define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) -#define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) -#define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) - -/* - * CNTSHDWUPT (RW) - * - * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) -#define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) -#define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) -#define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) - -/* - * SHLKEN (RW) - * - * 1- enable shadow registers lock feature, - * 0- disable shadow registers lock, shlk bit will always be 0 - */ -#define PWM_SHCR_SHLKEN_MASK (0x1U) -#define PWM_SHCR_SHLKEN_SHIFT (0U) -#define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) -#define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) - -/* Bitfield definition for register array: CAPPOS */ -/* - * CAPPOS (RO) - * - * counter value captured at input posedge - */ -#define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) -#define PWM_CAPPOS_CAPPOS_SHIFT (4U) -#define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNT_XCNT_MASK (0xF0000000UL) -#define PWM_CNT_XCNT_SHIFT (28U) -#define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNT_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNT_CNT_SHIFT (4U) -#define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CAPNEG */ -/* - * CAPNEG (RO) - * - * counter value captured at input signal falling edge - */ -#define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define PWM_CAPNEG_CAPNEG_SHIFT (0U) -#define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register: CNTCOPY */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) -#define PWM_CNTCOPY_XCNT_SHIFT (28U) -#define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNTCOPY_CNT_SHIFT (4U) -#define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) - -/* Bitfield definition for register array: PWMCFG */ -/* - * HR_UPDATE_MODE (RW) - * - * 0: update the hr value for the first edge at reload point; - * 1: update the hr value for the first edge at the last edge; - * all others will be updated at previous edge - * for pair mode, only pwm_cfg 0/2/4/6 are used - */ -#define PWM_PWMCFG_HR_UPDATE_MODE_MASK (0x20000000UL) -#define PWM_PWMCFG_HR_UPDATE_MODE_SHIFT (29U) -#define PWM_PWMCFG_HR_UPDATE_MODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) -#define PWM_PWMCFG_HR_UPDATE_MODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_HR_UPDATE_MODE_MASK) >> PWM_PWMCFG_HR_UPDATE_MODE_SHIFT) - -/* - * OEN (RW) - * - * PWM output enable - * 1- output is enabled - * 0- output is disabled - */ -#define PWM_PWMCFG_OEN_MASK (0x10000000UL) -#define PWM_PWMCFG_OEN_SHIFT (28U) -#define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) -#define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) - -/* - * FRCSHDWUPT (RW) - * - * This bitfield select when the FRCMD shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) -#define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) -#define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) -#define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) - -/* - * FAULTMODE (RW) - * - * This bitfield defines the PWM output status when fault condition happen - * 00: force output 0 - * 01: force output 1 - * 1x: output highz - */ -#define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) -#define PWM_PWMCFG_FAULTMODE_SHIFT (24U) -#define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) -#define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) - -/* - * FAULTRECTIME (RW) - * - * This bitfield select when to recover PWM output after fault condition removed. - * 00: immediately - * 01: after pwm timer counter reload time - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after software write faultclr bit in GCR register - */ -#define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) -#define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) -#define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) -#define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) - -/* - * FRCSRCSEL (RW) - * - * Select sources for force output - * 0- force output is enabled when FRCI assert - * 1- force output is enabled by software write swfrc to 1 - */ -#define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) -#define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) -#define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) -#define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) - -/* - * PAIR (RW) - * - * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. - * 0- PWM output is in indepandent mode. - */ -#define PWM_PWMCFG_PAIR_MASK (0x100000UL) -#define PWM_PWMCFG_PAIR_SHIFT (20U) -#define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) -#define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) - -/* - * DEADAREA (RW) - * - * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. - * Note: user should configure pair bit and this bitfield before PWM output is enabled. - */ -#define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) -#define PWM_PWMCFG_DEADAREA_SHIFT (0U) -#define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) -#define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * FAULTF (W1C) - * - * fault condition flag - */ -#define PWM_SR_FAULTF_MASK (0x8000000UL) -#define PWM_SR_FAULTF_SHIFT (27U) -#define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) -#define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) - -/* - * XRLDF (W1C) - * - * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - */ -#define PWM_SR_XRLDF_MASK (0x4000000UL) -#define PWM_SR_XRLDF_SHIFT (26U) -#define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) -#define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) - -/* - * HALFRLDF (W1C) - * - * half reload flag, this flag set when cnt count to rld/2 - */ -#define PWM_SR_HALFRLDF_MASK (0x2000000UL) -#define PWM_SR_HALFRLDF_SHIFT (25U) -#define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) -#define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) - -/* - * RLDF (W1C) - * - * reload flag, this flag set when cnt count to rld value or when SYNCI assert - */ -#define PWM_SR_RLDF_MASK (0x1000000UL) -#define PWM_SR_RLDF_SHIFT (24U) -#define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) -#define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) - -/* - * CMPFX (W1C) - * - * comparator output compare or input capture flag - */ -#define PWM_SR_CMPFX_MASK (0xFFFFFFUL) -#define PWM_SR_CMPFX_SHIFT (0U) -#define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) -#define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * FAULTIRQE (RW) - * - * fault condition interrupt enable - */ -#define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) -#define PWM_IRQEN_FAULTIRQE_SHIFT (27U) -#define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) -#define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) - -/* - * XRLDIRQE (RW) - * - * extended reload flag interrupt enable - */ -#define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) -#define PWM_IRQEN_XRLDIRQE_SHIFT (26U) -#define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) -#define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) - -/* - * HALFRLDIRQE (RW) - * - * half reload flag interrupt enable - */ -#define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) -#define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) -#define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) -#define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) - -/* - * RLDIRQE (RW) - * - * reload flag interrupt enable - */ -#define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) -#define PWM_IRQEN_RLDIRQE_SHIFT (24U) -#define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) -#define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) - -/* - * CMPIRQEX (RW) - * - * comparator output compare or input capture flag interrupt enable - */ -#define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) -#define PWM_IRQEN_CMPIRQEX_SHIFT (0U) -#define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) -#define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * FAULTEN (RW) - * - * fault condition DMA request enable - */ -#define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) -#define PWM_DMAEN_FAULTEN_SHIFT (27U) -#define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) -#define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) - -/* - * XRLDEN (RW) - * - * extended reload flag DMA request enable - */ -#define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) -#define PWM_DMAEN_XRLDEN_SHIFT (26U) -#define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) -#define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) - -/* - * HALFRLDEN (RW) - * - * half reload flag DMA request enable - */ -#define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) -#define PWM_DMAEN_HALFRLDEN_SHIFT (25U) -#define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) -#define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) - -/* - * RLDEN (RW) - * - * reload flag DMA request enable - */ -#define PWM_DMAEN_RLDEN_MASK (0x1000000UL) -#define PWM_DMAEN_RLDEN_SHIFT (24U) -#define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) -#define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) - -/* - * CMPENX (RW) - * - * comparator output compare or input capture flag DMA request enable - */ -#define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) -#define PWM_DMAEN_CMPENX_SHIFT (0U) -#define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) -#define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) - -/* Bitfield definition for register array: CMPCFG */ -/* - * XCNTCMPEN (RW) - * - * This bitfield enable the comparator to compare xcmp with xcnt. - */ -#define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) -#define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) -#define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) -#define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) - -/* - * CMPSHDWUPT (RW) - * - * This bitfield select when the comparator shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) -#define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) -#define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) -#define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) - -/* - * CMPMODE (RW) - * - * comparator mode - * 0- output compare mode - * 1- input capture mode - */ -#define PWM_CMPCFG_CMPMODE_MASK (0x2U) -#define PWM_CMPCFG_CMPMODE_SHIFT (1U) -#define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) -#define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) - -/* Bitfield definition for register array: ANASTS */ -/* - * CALON (RO) - * - * calibration status. - * will be set by hardware after setting cal_start. - * cleared after calibration finished - */ -#define PWM_ANASTS_CALON_MASK (0x80000000UL) -#define PWM_ANASTS_CALON_SHIFT (31U) -#define PWM_ANASTS_CALON_GET(x) (((uint32_t)(x) & PWM_ANASTS_CALON_MASK) >> PWM_ANASTS_CALON_SHIFT) - -/* Bitfield definition for register: HRPWM_CFG */ -/* - * CAL_SW_EN (RW) - * - * software calibration enable, internal use only - */ -#define PWM_HRPWM_CFG_CAL_SW_EN_MASK (0xFF00U) -#define PWM_HRPWM_CFG_CAL_SW_EN_SHIFT (8U) -#define PWM_HRPWM_CFG_CAL_SW_EN_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_SW_EN_SHIFT) & PWM_HRPWM_CFG_CAL_SW_EN_MASK) -#define PWM_HRPWM_CFG_CAL_SW_EN_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_SW_EN_MASK) >> PWM_HRPWM_CFG_CAL_SW_EN_SHIFT) - -/* - * CAL_START (WO) - * - * calibration start. - * software setting this bit to start calibration process. - * each bit for one channel. - */ -#define PWM_HRPWM_CFG_CAL_START_MASK (0xFFU) -#define PWM_HRPWM_CFG_CAL_START_SHIFT (0U) -#define PWM_HRPWM_CFG_CAL_START_SET(x) (((uint32_t)(x) << PWM_HRPWM_CFG_CAL_START_SHIFT) & PWM_HRPWM_CFG_CAL_START_MASK) -#define PWM_HRPWM_CFG_CAL_START_GET(x) (((uint32_t)(x) & PWM_HRPWM_CFG_CAL_START_MASK) >> PWM_HRPWM_CFG_CAL_START_SHIFT) - -/* Bitfield definition for register: ANA_CFG0 */ -/* - * CAL_SW_TRIG_H (RW) - * - */ -#define PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK (0x10000UL) -#define PWM_ANA_CFG0_CAL_SW_TRIG_H_SHIFT (16U) -#define PWM_ANA_CFG0_CAL_SW_TRIG_H_SET(x) (((uint32_t)(x) << PWM_ANA_CFG0_CAL_SW_TRIG_H_SHIFT) & PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK) -#define PWM_ANA_CFG0_CAL_SW_TRIG_H_GET(x) (((uint32_t)(x) & PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK) >> PWM_ANA_CFG0_CAL_SW_TRIG_H_SHIFT) - - - -/* CMP register group index macro definition */ -#define PWM_CMP_0 (0UL) -#define PWM_CMP_1 (1UL) -#define PWM_CMP_2 (2UL) -#define PWM_CMP_3 (3UL) -#define PWM_CMP_4 (4UL) -#define PWM_CMP_5 (5UL) -#define PWM_CMP_6 (6UL) -#define PWM_CMP_7 (7UL) -#define PWM_CMP_8 (8UL) -#define PWM_CMP_9 (9UL) -#define PWM_CMP_10 (10UL) -#define PWM_CMP_11 (11UL) -#define PWM_CMP_12 (12UL) -#define PWM_CMP_13 (13UL) -#define PWM_CMP_14 (14UL) -#define PWM_CMP_15 (15UL) - -/* CMP_HRPWM register group index macro definition */ -#define PWM_CMP_HRPWM_0 (0UL) -#define PWM_CMP_HRPWM_1 (1UL) -#define PWM_CMP_HRPWM_2 (2UL) -#define PWM_CMP_HRPWM_3 (3UL) -#define PWM_CMP_HRPWM_4 (4UL) -#define PWM_CMP_HRPWM_5 (5UL) -#define PWM_CMP_HRPWM_6 (6UL) -#define PWM_CMP_HRPWM_7 (7UL) -#define PWM_CMP_HRPWM_8 (8UL) -#define PWM_CMP_HRPWM_9 (9UL) -#define PWM_CMP_HRPWM_10 (10UL) -#define PWM_CMP_HRPWM_11 (11UL) -#define PWM_CMP_HRPWM_12 (12UL) -#define PWM_CMP_HRPWM_13 (13UL) -#define PWM_CMP_HRPWM_14 (14UL) -#define PWM_CMP_HRPWM_15 (15UL) - -/* CHCFG register group index macro definition */ -#define PWM_CHCFG_0 (0UL) -#define PWM_CHCFG_1 (1UL) -#define PWM_CHCFG_2 (2UL) -#define PWM_CHCFG_3 (3UL) -#define PWM_CHCFG_4 (4UL) -#define PWM_CHCFG_5 (5UL) -#define PWM_CHCFG_6 (6UL) -#define PWM_CHCFG_7 (7UL) -#define PWM_CHCFG_8 (8UL) -#define PWM_CHCFG_9 (9UL) -#define PWM_CHCFG_10 (10UL) -#define PWM_CHCFG_11 (11UL) -#define PWM_CHCFG_12 (12UL) -#define PWM_CHCFG_13 (13UL) -#define PWM_CHCFG_14 (14UL) -#define PWM_CHCFG_15 (15UL) - -/* CAPPOS register group index macro definition */ -#define PWM_CAPPOS_0 (0UL) -#define PWM_CAPPOS_1 (1UL) -#define PWM_CAPPOS_2 (2UL) -#define PWM_CAPPOS_3 (3UL) -#define PWM_CAPPOS_4 (4UL) -#define PWM_CAPPOS_5 (5UL) -#define PWM_CAPPOS_6 (6UL) -#define PWM_CAPPOS_7 (7UL) -#define PWM_CAPPOS_8 (8UL) -#define PWM_CAPPOS_9 (9UL) -#define PWM_CAPPOS_10 (10UL) -#define PWM_CAPPOS_11 (11UL) -#define PWM_CAPPOS_12 (12UL) -#define PWM_CAPPOS_13 (13UL) -#define PWM_CAPPOS_14 (14UL) -#define PWM_CAPPOS_15 (15UL) - -/* CAPNEG register group index macro definition */ -#define PWM_CAPNEG_0 (0UL) -#define PWM_CAPNEG_1 (1UL) -#define PWM_CAPNEG_2 (2UL) -#define PWM_CAPNEG_3 (3UL) -#define PWM_CAPNEG_4 (4UL) -#define PWM_CAPNEG_5 (5UL) -#define PWM_CAPNEG_6 (6UL) -#define PWM_CAPNEG_7 (7UL) -#define PWM_CAPNEG_8 (8UL) -#define PWM_CAPNEG_9 (9UL) -#define PWM_CAPNEG_10 (10UL) -#define PWM_CAPNEG_11 (11UL) -#define PWM_CAPNEG_12 (12UL) -#define PWM_CAPNEG_13 (13UL) -#define PWM_CAPNEG_14 (14UL) -#define PWM_CAPNEG_15 (15UL) - -/* PWMCFG register group index macro definition */ -#define PWM_PWMCFG_0 (0UL) -#define PWM_PWMCFG_1 (1UL) -#define PWM_PWMCFG_2 (2UL) -#define PWM_PWMCFG_3 (3UL) -#define PWM_PWMCFG_4 (4UL) -#define PWM_PWMCFG_5 (5UL) -#define PWM_PWMCFG_6 (6UL) -#define PWM_PWMCFG_7 (7UL) - -/* CMPCFG register group index macro definition */ -#define PWM_CMPCFG_CMPCFG0 (0UL) -#define PWM_CMPCFG_1 (1UL) -#define PWM_CMPCFG_2 (2UL) -#define PWM_CMPCFG_3 (3UL) -#define PWM_CMPCFG_4 (4UL) -#define PWM_CMPCFG_5 (5UL) -#define PWM_CMPCFG_6 (6UL) -#define PWM_CMPCFG_7 (7UL) -#define PWM_CMPCFG_8 (8UL) -#define PWM_CMPCFG_9 (9UL) -#define PWM_CMPCFG_10 (10UL) -#define PWM_CMPCFG_11 (11UL) -#define PWM_CMPCFG_12 (12UL) -#define PWM_CMPCFG_13 (13UL) -#define PWM_CMPCFG_14 (14UL) -#define PWM_CMPCFG_15 (15UL) - -/* ANASTS register group index macro definition */ -#define PWM_ANASTS_0 (0UL) -#define PWM_ANASTS_1 (1UL) -#define PWM_ANASTS_2 (2UL) -#define PWM_ANASTS_3 (3UL) -#define PWM_ANASTS_4 (4UL) -#define PWM_ANASTS_5 (5UL) -#define PWM_ANASTS_6 (6UL) -#define PWM_ANASTS_7 (7UL) - - -#endif /* HPM_PWM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_qei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_qei_regs.h deleted file mode 100644 index cafcdfe2851..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_qei_regs.h +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEI_H -#define HPM_QEI_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t PHIDX; /* 0xC: Phase index register */ - __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __RW uint32_t ZCMP; /* 0x18: Z comparator */ - __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ - __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ - __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ - struct { - __RW uint32_t Z; /* 0x30: Z counter */ - __R uint32_t PH; /* 0x34: Phase counter */ - __RW uint32_t SPD; /* 0x38: Speed counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - __R uint32_t SPDHIS[4]; /* 0x70 - 0x7C: Speed history */ -} QEI_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define QEI_CR_READ_MASK (0x80000000UL) -#define QEI_CR_READ_SHIFT (31U) -#define QEI_CR_READ_SET(x) (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK) -#define QEI_CR_READ_GET(x) (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT) - -/* - * HRSTSPD (RW) - * - * 1- reset spdcnt when H assert - */ -#define QEI_CR_HRSTSPD_MASK (0x40000UL) -#define QEI_CR_HRSTSPD_SHIFT (18U) -#define QEI_CR_HRSTSPD_SET(x) (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK) -#define QEI_CR_HRSTSPD_GET(x) (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT) - -/* - * HRSTPH (RW) - * - * 1- reset phcnt when H assert - */ -#define QEI_CR_HRSTPH_MASK (0x20000UL) -#define QEI_CR_HRSTPH_SHIFT (17U) -#define QEI_CR_HRSTPH_SET(x) (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK) -#define QEI_CR_HRSTPH_GET(x) (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT) - -/* - * HRSTZ (RW) - * - * 1- reset zcnt when H assert - */ -#define QEI_CR_HRSTZ_MASK (0x10000UL) -#define QEI_CR_HRSTZ_SHIFT (16U) -#define QEI_CR_HRSTZ_SET(x) (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK) -#define QEI_CR_HRSTZ_GET(x) (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT) - -/* - * PAUSESPD (RW) - * - * 1- pause spdcnt when PAUSE assert - */ -#define QEI_CR_PAUSESPD_MASK (0x4000U) -#define QEI_CR_PAUSESPD_SHIFT (14U) -#define QEI_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK) -#define QEI_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT) - -/* - * PAUSEPH (RW) - * - * 1- pause phcnt when PAUSE assert - */ -#define QEI_CR_PAUSEPH_MASK (0x2000U) -#define QEI_CR_PAUSEPH_SHIFT (13U) -#define QEI_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK) -#define QEI_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT) - -/* - * PAUSEZ (RW) - * - * 1- pause zcnt when PAUSE assert - */ -#define QEI_CR_PAUSEZ_MASK (0x1000U) -#define QEI_CR_PAUSEZ_SHIFT (12U) -#define QEI_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK) -#define QEI_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT) - -/* - * HRDIR1 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - */ -#define QEI_CR_HRDIR1_MASK (0x800U) -#define QEI_CR_HRDIR1_SHIFT (11U) -#define QEI_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK) -#define QEI_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT) - -/* - * HRDIR0 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - */ -#define QEI_CR_HRDIR0_MASK (0x400U) -#define QEI_CR_HRDIR0_SHIFT (10U) -#define QEI_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK) -#define QEI_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT) - -/* - * HFDIR1 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - */ -#define QEI_CR_HFDIR1_MASK (0x200U) -#define QEI_CR_HFDIR1_SHIFT (9U) -#define QEI_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK) -#define QEI_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT) - -/* - * HFDIR0 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - */ -#define QEI_CR_HFDIR0_MASK (0x100U) -#define QEI_CR_HFDIR0_SHIFT (8U) -#define QEI_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK) -#define QEI_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - */ -#define QEI_CR_SNAPEN_MASK (0x20U) -#define QEI_CR_SNAPEN_SHIFT (5U) -#define QEI_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK) -#define QEI_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - */ -#define QEI_CR_RSTCNT_MASK (0x10U) -#define QEI_CR_RSTCNT_SHIFT (4U) -#define QEI_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK) -#define QEI_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT) - -/* - * ENCTYP (RW) - * - * 00-abz; 01-pd; 10-ud; 11-reserved - */ -#define QEI_CR_ENCTYP_MASK (0x3U) -#define QEI_CR_ENCTYP_SHIFT (0U) -#define QEI_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK) -#define QEI_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * ZCNTCFG (RW) - * - * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * 0- zcnt will increment or decrement when Z input assert - */ -#define QEI_PHCFG_ZCNTCFG_MASK (0x400000UL) -#define QEI_PHCFG_ZCNTCFG_SHIFT (22U) -#define QEI_PHCFG_ZCNTCFG_SET(x) (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK) -#define QEI_PHCFG_ZCNTCFG_GET(x) (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT) - -/* - * PHCALIZ (RW) - * - * 1- phcnt will set to phidx when Z input assert - */ -#define QEI_PHCFG_PHCALIZ_MASK (0x200000UL) -#define QEI_PHCFG_PHCALIZ_SHIFT (21U) -#define QEI_PHCFG_PHCALIZ_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK) -#define QEI_PHCFG_PHCALIZ_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT) - -/* - * PHMAX (RW) - * - * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - */ -#define QEI_PHCFG_PHMAX_MASK (0x1FFFFFUL) -#define QEI_PHCFG_PHMAX_SHIFT (0U) -#define QEI_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK) -#define QEI_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define QEI_WDGCFG_WDGEN_MASK (0x80000000UL) -#define QEI_WDGCFG_WDGEN_SHIFT (31U) -#define QEI_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK) -#define QEI_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define QEI_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) -#define QEI_WDGCFG_WDGTO_SHIFT (0U) -#define QEI_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK) -#define QEI_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: PHIDX */ -/* - * PHIDX (RW) - * - * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - */ -#define QEI_PHIDX_PHIDX_MASK (0x1FFFFFUL) -#define QEI_PHIDX_PHIDX_SHIFT (0U) -#define QEI_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK) -#define QEI_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGFEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define QEI_TRGOEN_WDGFEN_MASK (0x80000000UL) -#define QEI_TRGOEN_WDGFEN_SHIFT (31U) -#define QEI_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK) -#define QEI_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- enable trigger output when homef flag set - */ -#define QEI_TRGOEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_TRGOEN_HOMEFEN_SHIFT (30U) -#define QEI_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK) -#define QEI_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- enable trigger output when poscmpf flag set - */ -#define QEI_TRGOEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_TRGOEN_POSCMPFEN_SHIFT (29U) -#define QEI_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK) -#define QEI_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- enable trigger output when zphf flag set - */ -#define QEI_TRGOEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_TRGOEN_ZPHFEN_SHIFT (28U) -#define QEI_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK) -#define QEI_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGFEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define QEI_READEN_WDGFEN_MASK (0x80000000UL) -#define QEI_READEN_WDGFEN_SHIFT (31U) -#define QEI_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK) -#define QEI_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- load counters to their read registers when homef flag set - */ -#define QEI_READEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_READEN_HOMEFEN_SHIFT (30U) -#define QEI_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK) -#define QEI_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- load counters to their read registers when poscmpf flag set - */ -#define QEI_READEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_READEN_POSCMPFEN_SHIFT (29U) -#define QEI_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK) -#define QEI_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- load counters to their read registers when zphf flag set - */ -#define QEI_READEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_READEN_ZPHFEN_SHIFT (28U) -#define QEI_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK) -#define QEI_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: ZCMP */ -/* - * ZCMP (RW) - * - * zcnt postion compare value - */ -#define QEI_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) -#define QEI_ZCMP_ZCMP_SHIFT (0U) -#define QEI_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK) -#define QEI_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT) - -/* Bitfield definition for register: PHCMP */ -/* - * ZCMPDIS (RW) - * - * 1- postion compare not include zcnt - */ -#define QEI_PHCMP_ZCMPDIS_MASK (0x80000000UL) -#define QEI_PHCMP_ZCMPDIS_SHIFT (31U) -#define QEI_PHCMP_ZCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK) -#define QEI_PHCMP_ZCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT) - -/* - * DIRCMPDIS (RW) - * - * 1- postion compare not include rotation direction - */ -#define QEI_PHCMP_DIRCMPDIS_MASK (0x40000000UL) -#define QEI_PHCMP_DIRCMPDIS_SHIFT (30U) -#define QEI_PHCMP_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK) -#define QEI_PHCMP_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT) - -/* - * DIRCMP (RW) - * - * 0- position compare need positive rotation - * 1- position compare need negative rotation - */ -#define QEI_PHCMP_DIRCMP_MASK (0x20000000UL) -#define QEI_PHCMP_DIRCMP_SHIFT (29U) -#define QEI_PHCMP_DIRCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK) -#define QEI_PHCMP_DIRCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT) - -/* - * PHCMP (RW) - * - * phcnt position compare value - */ -#define QEI_PHCMP_PHCMP_MASK (0x1FFFFFUL) -#define QEI_PHCMP_PHCMP_SHIFT (0U) -#define QEI_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK) -#define QEI_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT) - -/* Bitfield definition for register: SPDCMP */ -/* - * SPDCMP (RW) - * - * spdcnt position compare value - */ -#define QEI_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) -#define QEI_SPDCMP_SPDCMP_SHIFT (0U) -#define QEI_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK) -#define QEI_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGFEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define QEI_DMAEN_WDGFEN_MASK (0x80000000UL) -#define QEI_DMAEN_WDGFEN_SHIFT (31U) -#define QEI_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK) -#define QEI_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- generate dma request when homef flag set - */ -#define QEI_DMAEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_DMAEN_HOMEFEN_SHIFT (30U) -#define QEI_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK) -#define QEI_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- generate dma request when poscmpf flag set - */ -#define QEI_DMAEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_DMAEN_POSCMPFEN_SHIFT (29U) -#define QEI_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK) -#define QEI_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- generate dma request when zphf flag set - */ -#define QEI_DMAEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_DMAEN_ZPHFEN_SHIFT (28U) -#define QEI_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK) -#define QEI_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog flag - */ -#define QEI_SR_WDGF_MASK (0x80000000UL) -#define QEI_SR_WDGF_SHIFT (31U) -#define QEI_SR_WDGF_SET(x) (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK) -#define QEI_SR_WDGF_GET(x) (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT) - -/* - * HOMEF (RW) - * - * home flag - */ -#define QEI_SR_HOMEF_MASK (0x40000000UL) -#define QEI_SR_HOMEF_SHIFT (30U) -#define QEI_SR_HOMEF_SET(x) (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK) -#define QEI_SR_HOMEF_GET(x) (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT) - -/* - * POSCMPF (RW) - * - * postion compare match flag - */ -#define QEI_SR_POSCMPF_MASK (0x20000000UL) -#define QEI_SR_POSCMPF_SHIFT (29U) -#define QEI_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK) -#define QEI_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT) - -/* - * ZPHF (RW) - * - * z input flag - */ -#define QEI_SR_ZPHF_MASK (0x10000000UL) -#define QEI_SR_ZPHF_SHIFT (28U) -#define QEI_SR_ZPHF_SET(x) (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK) -#define QEI_SR_ZPHF_GET(x) (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt when wdg flag set - */ -#define QEI_IRQEN_WDGIE_MASK (0x80000000UL) -#define QEI_IRQEN_WDGIE_SHIFT (31U) -#define QEI_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK) -#define QEI_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT) - -/* - * HOMEIE (RW) - * - * 1- generate interrupt when homef flag set - */ -#define QEI_IRQEN_HOMEIE_MASK (0x40000000UL) -#define QEI_IRQEN_HOMEIE_SHIFT (30U) -#define QEI_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK) -#define QEI_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT) - -/* - * POSCMPIE (RW) - * - * 1- generate interrupt when poscmpf flag set - */ -#define QEI_IRQEN_POSCMPIE_MASK (0x20000000UL) -#define QEI_IRQEN_POSCMPIE_SHIFT (29U) -#define QEI_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK) -#define QEI_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT) - -/* - * ZPHIE (RW) - * - * 1- generate interrupt when zphf flag set - */ -#define QEI_IRQEN_ZPHIE_MASK (0x10000000UL) -#define QEI_IRQEN_ZPHIE_SHIFT (28U) -#define QEI_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK) -#define QEI_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: Z */ -/* - * ZCNT (RW) - * - * zcnt value - */ -#define QEI_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) -#define QEI_COUNT_Z_ZCNT_SHIFT (0U) -#define QEI_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK) -#define QEI_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: PH */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEI_COUNT_PH_DIR_MASK (0x40000000UL) -#define QEI_COUNT_PH_DIR_SHIFT (30U) -#define QEI_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEI_COUNT_PH_ASTAT_MASK (0x4000000UL) -#define QEI_COUNT_PH_ASTAT_SHIFT (26U) -#define QEI_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT) - -/* - * BSTAT (RO) - * - * 1- b input is high - * 0- b input is low - */ -#define QEI_COUNT_PH_BSTAT_MASK (0x2000000UL) -#define QEI_COUNT_PH_BSTAT_SHIFT (25U) -#define QEI_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT) - -/* - * PHCNT (RO) - * - * phcnt value - */ -#define QEI_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) -#define QEI_COUNT_PH_PHCNT_SHIFT (0U) -#define QEI_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: SPD */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEI_COUNT_SPD_DIR_MASK (0x80000000UL) -#define QEI_COUNT_SPD_DIR_SHIFT (31U) -#define QEI_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEI_COUNT_SPD_ASTAT_MASK (0x40000000UL) -#define QEI_COUNT_SPD_ASTAT_SHIFT (30U) -#define QEI_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT) - -/* - * BSTAT (RW) - * - * 1- b input is high - * 0- b input is low - */ -#define QEI_COUNT_SPD_BSTAT_MASK (0x20000000UL) -#define QEI_COUNT_SPD_BSTAT_SHIFT (29U) -#define QEI_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK) -#define QEI_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT) - -/* - * SPDCNT (RO) - * - * spdcnt value - */ -#define QEI_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) -#define QEI_COUNT_SPD_SPDCNT_SHIFT (0U) -#define QEI_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TMRCNT (RO) - * - * 32 bit free run timer - */ -#define QEI_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) -#define QEI_COUNT_TMR_TMRCNT_SHIFT (0U) -#define QEI_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT) - -/* Bitfield definition for register array: SPDHIS */ -/* - * SPDHIS0 (RO) - * - * copy of spdcnt, load from spdcnt after any transition from a = low, b = low - */ -#define QEI_SPDHIS_SPDHIS0_MASK (0xFFFFFFFFUL) -#define QEI_SPDHIS_SPDHIS0_SHIFT (0U) -#define QEI_SPDHIS_SPDHIS0_GET(x) (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT) - - - -/* COUNT register group index macro definition */ -#define QEI_COUNT_CURRENT (0UL) -#define QEI_COUNT_READ (1UL) -#define QEI_COUNT_SNAP0 (2UL) -#define QEI_COUNT_SNAP1 (3UL) - -/* SPDHIS register group index macro definition */ -#define QEI_SPDHIS_SPDHIS0 (0UL) -#define QEI_SPDHIS_SPDHIS1 (1UL) -#define QEI_SPDHIS_SPDHIS2 (2UL) -#define QEI_SPDHIS_SPDHIS3 (3UL) - - -#endif /* HPM_QEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_rng_regs.h deleted file mode 100644 index 1a847f5d090..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_rng_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RNG_H -#define HPM_RNG_H - -typedef struct { - __RW uint32_t CMD; /* 0x0: Command Register */ - __RW uint32_t CTRL; /* 0x4: Control Register */ - __R uint32_t STA; /* 0x8: Status Register */ - __R uint32_t ERR; /* 0xC: Error Registers */ - __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ -} RNG_Type; - - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. - * 0 Do not perform a software reset. - * 1 Software reset - */ -#define RNG_CMD_SFTRST_MASK (0x40U) -#define RNG_CMD_SFTRST_SHIFT (6U) -#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) -#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) - -/* - * CLRERR (RW) - * - * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. - * 0 Do not clear the errors and the interrupt. - * 1 Clear the errors and the interrupt. - */ -#define RNG_CMD_CLRERR_MASK (0x20U) -#define RNG_CMD_CLRERR_SHIFT (5U) -#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) -#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) - -/* - * CLRINT (RW) - * - * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. - * 0 Do not clear the interrupt. - * 1 Clear the interrupt - */ -#define RNG_CMD_CLRINT_MASK (0x10U) -#define RNG_CMD_CLRINT_SHIFT (4U) -#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) -#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) - -/* - * GENSD (RW) - * - * Generate Seed, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_GENSD_MASK (0x2U) -#define RNG_CMD_GENSD_SHIFT (1U) -#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) -#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) - -/* - * SLFCHK (RW) - * - * Self Test, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_SLFCHK_MASK (0x1U) -#define RNG_CMD_SLFCHK_SHIFT (0U) -#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) -#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * MIRQERR (RW) - * - * Mask Interrupt Request for Error - */ -#define RNG_CTRL_MIRQERR_MASK (0x40U) -#define RNG_CTRL_MIRQERR_SHIFT (6U) -#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) -#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) - -/* - * MIRQDN (RW) - * - * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: - * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). - * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - */ -#define RNG_CTRL_MIRQDN_MASK (0x20U) -#define RNG_CTRL_MIRQDN_SHIFT (5U) -#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) -#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) - -/* - * AUTRSD (RW) - * - * Auto Reseed - */ -#define RNG_CTRL_AUTRSD_MASK (0x10U) -#define RNG_CTRL_AUTRSD_SHIFT (4U) -#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) -#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) - -/* - * FUFMOD (RW) - * - * FIFO underflow response mode - * 00 Return all zeros and set the ESR[FUFE]. - * 01 Return all zeros and set the ESR[FUFE]. - * 10 Generate the bus transfer error - * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - */ -#define RNG_CTRL_FUFMOD_MASK (0x3U) -#define RNG_CTRL_FUFMOD_SHIFT (0U) -#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) -#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * SCPF (RO) - * - * Self Check Pass Fail - */ -#define RNG_STA_SCPF_MASK (0xE00000UL) -#define RNG_STA_SCPF_SHIFT (21U) -#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) - -/* - * FUNCERR (RO) - * - * Error was detected, check ESR register for details - */ -#define RNG_STA_FUNCERR_MASK (0x10000UL) -#define RNG_STA_FUNCERR_SHIFT (16U) -#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) - -/* - * FSIZE (RO) - * - * Fifo Size, it is 5 in this design. - */ -#define RNG_STA_FSIZE_MASK (0xF000U) -#define RNG_STA_FSIZE_SHIFT (12U) -#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) - -/* - * FRNNU (RO) - * - * Fifo Level, Indicates the number of random words currently in the output FIFO - */ -#define RNG_STA_FRNNU_MASK (0xF00U) -#define RNG_STA_FRNNU_SHIFT (8U) -#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) - -/* - * NSDDN (RO) - * - * New seed done. - */ -#define RNG_STA_NSDDN_MASK (0x40U) -#define RNG_STA_NSDDN_SHIFT (6U) -#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) - -/* - * FSDDN (RO) - * - * 1st Seed done - * When "1", Indicates that the RNG generated the first seed. - */ -#define RNG_STA_FSDDN_MASK (0x20U) -#define RNG_STA_FSDDN_SHIFT (5U) -#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) - -/* - * SCDN (RO) - * - * Self Check Done - * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is - * initiated by setting the CMD[ST]. - * 0 Self test not completed - * 1 Completed a self test since the last reset. - */ -#define RNG_STA_SCDN_MASK (0x10U) -#define RNG_STA_SCDN_SHIFT (4U) -#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) - -/* - * RSDREQ (RO) - * - * Reseed needed - * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or - * automatically if the CTRL[ARS] is set. - */ -#define RNG_STA_RSDREQ_MASK (0x8U) -#define RNG_STA_RSDREQ_SHIFT (3U) -#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) - -/* - * IDLE (RO) - * - * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - */ -#define RNG_STA_IDLE_MASK (0x4U) -#define RNG_STA_IDLE_SHIFT (2U) -#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) - -/* - * BUSY (RO) - * - * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - */ -#define RNG_STA_BUSY_MASK (0x2U) -#define RNG_STA_BUSY_SHIFT (1U) -#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) - -/* Bitfield definition for register: ERR */ -/* - * FUFE (RO) - * - * FIFO access error(underflow) - */ -#define RNG_ERR_FUFE_MASK (0x20U) -#define RNG_ERR_FUFE_SHIFT (5U) -#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) - -/* - * SCKERR (RO) - * - * Self-test error - * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a - * hardware reset or by writing 1 to the CMD[CE] - */ -#define RNG_ERR_SCKERR_MASK (0x8U) -#define RNG_ERR_SCKERR_SHIFT (3U) -#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) - -/* Bitfield definition for register: FO2B */ -/* - * FO2B (RO) - * - * SW read the FIFO output. - */ -#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) -#define RNG_FO2B_FO2B_SHIFT (0U) -#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) - -/* Bitfield definition for register array: R2SK */ -/* - * FO2S0 (RO) - * - * FIFO out to KMAN, will be SDP engine key. - */ -#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) -#define RNG_R2SK_FO2S0_SHIFT (0U) -#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) - - - -/* R2SK register group index macro definition */ -#define RNG_R2SK_FO2S0 (0UL) -#define RNG_R2SK_FO2S1 (1UL) -#define RNG_R2SK_FO2S2 (2UL) -#define RNG_R2SK_FO2S3 (3UL) -#define RNG_R2SK_FO2S4 (4UL) -#define RNG_R2SK_FO2S5 (5UL) -#define RNG_R2SK_FO2S6 (6UL) -#define RNG_R2SK_FO2S7 (7UL) - - -#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_rtc_regs.h deleted file mode 100644 index d2325b94590..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_rtc_regs.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTC_H -#define HPM_RTC_H - -typedef struct { - __RW uint32_t SECOND; /* 0x0: Second counter */ - __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ - __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ - __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ - __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ - __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ - __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ - __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ - __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ - __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ -} RTC_Type; - - -/* Bitfield definition for register: SECOND */ -/* - * SECOND (RW) - * - * second counter - */ -#define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) -#define RTC_SECOND_SECOND_SHIFT (0U) -#define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) -#define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) - -/* Bitfield definition for register: SUBSEC */ -/* - * SUBSEC (RO) - * - * sub second counter - */ -#define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) - -/* Bitfield definition for register: SEC_SNAP */ -/* - * SEC_SNAP (RW) - * - * second snap shot, write to take snap shot - */ -#define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) -#define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) -#define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) - -/* Bitfield definition for register: SUB_SNAP */ -/* - * SUB_SNAP (RW) - * - * sub second snap shot, write to take snap shot - */ -#define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) -#define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) -#define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) - -/* Bitfield definition for register: ALARM0 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_ALARM_SHIFT (0U) -#define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) -#define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM0_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) -#define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM1 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_ALARM_SHIFT (0U) -#define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) -#define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM1_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) -#define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM_FLAG */ -/* - * ALARM1 (RW) - * - * alarm1 happen - */ -#define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) -#define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) -#define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) -#define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) - -/* - * ALARM0 (RW) - * - * alarm0 happen - */ -#define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) -#define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) -#define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) -#define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) - -/* Bitfield definition for register: ALARM_EN */ -/* - * ENABLE1 (RW) - * - * alarm1 mask - * 0: alarm1 disabled - * 1: alarm1 enabled - */ -#define RTC_ALARM_EN_ENABLE1_MASK (0x2U) -#define RTC_ALARM_EN_ENABLE1_SHIFT (1U) -#define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) -#define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) - -/* - * ENABLE0 (RW) - * - * alarm0 mask - * 0: alarm0 disabled - * 1: alarm0 enabled - */ -#define RTC_ALARM_EN_ENABLE0_MASK (0x1U) -#define RTC_ALARM_EN_ENABLE0_SHIFT (0U) -#define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) -#define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) - - - - -#endif /* HPM_RTC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sdm_regs.h deleted file mode 100644 index 98009c8d178..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sdm_regs.h +++ /dev/null @@ -1,859 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDM_H -#define HPM_SDM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: SDM control register */ - __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ - __R uint32_t STATUS; /* 0x8: Status Registers */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - struct { - __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ - __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ - __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ - __RW uint32_t SDST; /* 0x1C: Data Path Status */ - __R uint32_t SDATA; /* 0x20: Data */ - __R uint32_t SDFIFO; /* 0x24: FIFO Data */ - __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ - __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ - __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ - __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ - __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ - __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ - __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ - } CH[4]; -} SDM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module if asserted to be1’b1. - */ -#define SDM_CTRL_SFTRST_MASK (0x80000000UL) -#define SDM_CTRL_SFTRST_SHIFT (31U) -#define SDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK) -#define SDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT) - -/* - * CHMD (RW) - * - * Channel Rcv mode - * Bits[2:0] for Ch0. - * Bits[5:3] for Ch1 - * Bits[8:6] for Ch2 - * Bits[11:9] for Ch3 - * 3'b000: Capture at posedge of MCLK - * 3'b001: Capture at both posedge and negedge of MCLK - * 3'b010: Manchestor Mode - * 3'b011: Capture at negedge of MCLK - * 3'b100: Capture at every other posedge of MCLK - * 3'b101: Capture at every other negedge of MCLK - * Others: Undefined - */ -#define SDM_CTRL_CHMD_MASK (0x3FFC000UL) -#define SDM_CTRL_CHMD_SHIFT (14U) -#define SDM_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK) -#define SDM_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT) - -/* - * SYNC_MCLK (RW) - * - * Asserted to double sync the mclk input pin before its usage inside the module - */ -#define SDM_CTRL_SYNC_MCLK_MASK (0x3C00U) -#define SDM_CTRL_SYNC_MCLK_SHIFT (10U) -#define SDM_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK) -#define SDM_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT) - -/* - * SYNC_MDAT (RW) - * - * Asserted to double sync the mdat input pin before its usage inside the module - */ -#define SDM_CTRL_SYNC_MDAT_MASK (0x3C0U) -#define SDM_CTRL_SYNC_MDAT_SHIFT (6U) -#define SDM_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK) -#define SDM_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT) - -/* - * CH_EN (RW) - * - * Channel Enable - */ -#define SDM_CTRL_CH_EN_MASK (0x3CU) -#define SDM_CTRL_CH_EN_SHIFT (2U) -#define SDM_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK) -#define SDM_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT) - -/* - * IE (RW) - * - * Interrupt Enable - */ -#define SDM_CTRL_IE_MASK (0x2U) -#define SDM_CTRL_IE_SHIFT (1U) -#define SDM_CTRL_IE_SET(x) (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK) -#define SDM_CTRL_IE_GET(x) (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * CH3DRY (RW) - * - * Ch3 Data Ready interrupt enable. - */ -#define SDM_INT_EN_CH3DRY_MASK (0x80U) -#define SDM_INT_EN_CH3DRY_SHIFT (7U) -#define SDM_INT_EN_CH3DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK) -#define SDM_INT_EN_CH3DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT) - -/* - * CH2DRY (RW) - * - * Ch2 Data Ready interrupt enable - */ -#define SDM_INT_EN_CH2DRY_MASK (0x40U) -#define SDM_INT_EN_CH2DRY_SHIFT (6U) -#define SDM_INT_EN_CH2DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK) -#define SDM_INT_EN_CH2DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT) - -/* - * CH1DRY (RW) - * - * Ch1 Data Ready interrupt enable - */ -#define SDM_INT_EN_CH1DRY_MASK (0x20U) -#define SDM_INT_EN_CH1DRY_SHIFT (5U) -#define SDM_INT_EN_CH1DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK) -#define SDM_INT_EN_CH1DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT) - -/* - * CH0DRY (RW) - * - * Ch0 Data Ready interrupt enable - */ -#define SDM_INT_EN_CH0DRY_MASK (0x10U) -#define SDM_INT_EN_CH0DRY_SHIFT (4U) -#define SDM_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK) -#define SDM_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT) - -/* - * CH3ERR (RW) - * - * Ch3 Error interrupt enable. - */ -#define SDM_INT_EN_CH3ERR_MASK (0x8U) -#define SDM_INT_EN_CH3ERR_SHIFT (3U) -#define SDM_INT_EN_CH3ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK) -#define SDM_INT_EN_CH3ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT) - -/* - * CH2ERR (RW) - * - * Ch2 Error interrupt enable - */ -#define SDM_INT_EN_CH2ERR_MASK (0x4U) -#define SDM_INT_EN_CH2ERR_SHIFT (2U) -#define SDM_INT_EN_CH2ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK) -#define SDM_INT_EN_CH2ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT) - -/* - * CH1ERR (RW) - * - * Ch1 Error interrupt enable - */ -#define SDM_INT_EN_CH1ERR_MASK (0x2U) -#define SDM_INT_EN_CH1ERR_SHIFT (1U) -#define SDM_INT_EN_CH1ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK) -#define SDM_INT_EN_CH1ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT) - -/* - * CH0ERR (RW) - * - * Ch0 Error interrupt enable - */ -#define SDM_INT_EN_CH0ERR_MASK (0x1U) -#define SDM_INT_EN_CH0ERR_SHIFT (0U) -#define SDM_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK) -#define SDM_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * CH3DRY (RO) - * - * Ch3 Data Ready. - * De-assert this bit by reading the data (or data fifo) registers. - */ -#define SDM_STATUS_CH3DRY_MASK (0x80U) -#define SDM_STATUS_CH3DRY_SHIFT (7U) -#define SDM_STATUS_CH3DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT) - -/* - * CH2DRY (RO) - * - * Ch2 Data Ready - */ -#define SDM_STATUS_CH2DRY_MASK (0x40U) -#define SDM_STATUS_CH2DRY_SHIFT (6U) -#define SDM_STATUS_CH2DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT) - -/* - * CH1DRY (RO) - * - * Ch1 Data Ready - */ -#define SDM_STATUS_CH1DRY_MASK (0x20U) -#define SDM_STATUS_CH1DRY_SHIFT (5U) -#define SDM_STATUS_CH1DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT) - -/* - * CH0DRY (RO) - * - * Ch0 Data Ready - */ -#define SDM_STATUS_CH0DRY_MASK (0x10U) -#define SDM_STATUS_CH0DRY_SHIFT (4U) -#define SDM_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT) - -/* - * CH3ERR (RO) - * - * Ch3 Error. - * ORed together by channel related error signals and corresponding error interrupt enable signals. - * De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. - */ -#define SDM_STATUS_CH3ERR_MASK (0x8U) -#define SDM_STATUS_CH3ERR_SHIFT (3U) -#define SDM_STATUS_CH3ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT) - -/* - * CH2ERR (RO) - * - * Ch2 Error - */ -#define SDM_STATUS_CH2ERR_MASK (0x4U) -#define SDM_STATUS_CH2ERR_SHIFT (2U) -#define SDM_STATUS_CH2ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT) - -/* - * CH1ERR (RO) - * - * Ch1 Error - */ -#define SDM_STATUS_CH1ERR_MASK (0x2U) -#define SDM_STATUS_CH1ERR_SHIFT (1U) -#define SDM_STATUS_CH1ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT) - -/* - * CH0ERR (RO) - * - * Ch0 Error - */ -#define SDM_STATUS_CH0ERR_MASK (0x1U) -#define SDM_STATUS_CH0ERR_SHIFT (0U) -#define SDM_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT) - -/* Bitfield definition for register of struct array CH: SDFIFOCTRL */ -/* - * GATE_SAMPLES (RW) - * - * The number-1-3 of input PDM bit samples to be gated when CIC_GATE_EN=1. Max 255. So the minimum gated samples is 4 samples when GATE_SAMPLES=0. - */ -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK (0xFF0000UL) -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT (16U) -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK) -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK) >> SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT) - -/* - * THRSH (RW) - * - * FIFO threshold (0,..,16) (fillings > threshold, then gen int) - */ -#define SDM_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) -#define SDM_CH_SDFIFOCTRL_THRSH_SHIFT (4U) -#define SDM_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK) -#define SDM_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT) - -/* - * D_RDY_INT_EN (RW) - * - * FIFO data ready interrupt enable - */ -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) - -/* Bitfield definition for register of struct array CH: SDCTRLP */ -/* - * MANCH_THR (RW) - * - * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] - */ -#define SDM_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) -#define SDM_CH_SDCTRLP_MANCH_THR_SHIFT (25U) -#define SDM_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK) -#define SDM_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT) - -/* - * WDOG_THR (RW) - * - * Watch dog threshold for channel failure of CLK halting - */ -#define SDM_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) -#define SDM_CH_SDCTRLP_WDOG_THR_SHIFT (17U) -#define SDM_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK) -#define SDM_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT) - -/* - * AF_IE (RW) - * - * Acknowledge feedback interrupt enable - */ -#define SDM_CH_SDCTRLP_AF_IE_MASK (0x10000UL) -#define SDM_CH_SDCTRLP_AF_IE_SHIFT (16U) -#define SDM_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_AF_IE_SHIFT) & SDM_CH_SDCTRLP_AF_IE_MASK) -#define SDM_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_AF_IE_MASK) >> SDM_CH_SDCTRLP_AF_IE_SHIFT) - -/* - * DFFOVIE (RW) - * - * Ch Data FIFO overflow interrupt enable - */ -#define SDM_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) -#define SDM_CH_SDCTRLP_DFFOVIE_SHIFT (15U) -#define SDM_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK) -#define SDM_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT) - -/* - * DSATIE (RW) - * - * Ch CIC Data Saturation Interrupt Enable - */ -#define SDM_CH_SDCTRLP_DSATIE_MASK (0x4000U) -#define SDM_CH_SDCTRLP_DSATIE_SHIFT (14U) -#define SDM_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK) -#define SDM_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT) - -/* - * DRIE (RW) - * - * Ch Data Ready Interrupt Enable - */ -#define SDM_CH_SDCTRLP_DRIE_MASK (0x2000U) -#define SDM_CH_SDCTRLP_DRIE_SHIFT (13U) -#define SDM_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK) -#define SDM_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT) - -/* - * SYNCSEL (RW) - * - * Select the PWM SYNC Source - */ -#define SDM_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) -#define SDM_CH_SDCTRLP_SYNCSEL_SHIFT (7U) -#define SDM_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK) -#define SDM_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT) - -/* - * FFSYNCCLREN (RW) - * - * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 - */ -#define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) -#define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) -#define SDM_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) -#define SDM_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) - -/* - * WTSYNACLR (RW) - * - * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen - * 0: WTSYNFLG should be cleared manually by WTSYNMCLR - */ -#define SDM_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) -#define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) -#define SDM_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) -#define SDM_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) - -/* - * WTSYNMCLR (RW) - * - * 1: Manually clear WTSYNFLG. Auto-clear. - */ -#define SDM_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) -#define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) -#define SDM_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) -#define SDM_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) - -/* - * WTSYNCEN (RW) - * - * 1: Start to store data only after PWM SYNC event - * 0: Start to store data whenever enabled - */ -#define SDM_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) -#define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) -#define SDM_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) -#define SDM_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) - -/* - * D32 (RW) - * - * 1:32 bit data - * 0:16 bit data - */ -#define SDM_CH_SDCTRLP_D32_MASK (0x4U) -#define SDM_CH_SDCTRLP_D32_SHIFT (2U) -#define SDM_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK) -#define SDM_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT) - -/* - * DR_OPT (RW) - * - * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold - * 0: Use Data Reg Ready as data ready - */ -#define SDM_CH_SDCTRLP_DR_OPT_MASK (0x2U) -#define SDM_CH_SDCTRLP_DR_OPT_SHIFT (1U) -#define SDM_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK) -#define SDM_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT) - -/* - * EN (RW) - * - * Data Path Enable - */ -#define SDM_CH_SDCTRLP_EN_MASK (0x1U) -#define SDM_CH_SDCTRLP_EN_SHIFT (0U) -#define SDM_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK) -#define SDM_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT) - -/* Bitfield definition for register of struct array CH: SDCTRLE */ -/* - * CIC_GATE_TYPE (RW) - * - * 1: the gate cycle is determined by SDFIFOCTRLn[GATE_SAMPLES]. - * 0: the gate cycle is determined by the CIC decimation counter, and the minimal gated off PDM bits are determined by SDFIFOCTRLn[GATE_SAMPLES], and at the same time, to keep alignment with normal PCM sampling time. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK (0x80000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT (31U) -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT) - -/* - * CIC_GATE_POL (RW) - * - * 1: When mask signal is 1, pause the CIC stage at he rising edge of mask signal. - * 0: When mask signal is 0, pause the CIC stage at he falling edge of mask signal. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_POL_MASK (0x40000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT (30U) -#define SDM_CH_SDCTRLE_CIC_GATE_POL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_POL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT) - -/* - * CIC_GATE_SEL (RW) - * - * Select the mask signal for CIC gate signal. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK (0x3C000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT (26U) -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT) - -/* - * CIC_GATE_EN (RW) - * - * 1: the CIC stage can be paused by the mask input. - * 0: the CIC stage won't be paused by the mask input. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_EN_MASK (0x2000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT (25U) -#define SDM_CH_SDCTRLE_CIC_GATE_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT) - -/* - * TIMESTAMP_TYPE (RW) - * - * 1. Use the time (when the data is calculated out) - delta_time_of_filter_span as the timestamp. - * 0: Use the time when the data is calculated out. - */ -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK (0x400000UL) -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT (22U) -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK) -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK) >> SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT) - -/* - * DFIFO_S_T (RW) - * - * 1: the output of SDFIFO is data and timestamp interleaved. First is data. - * 0: the output of SDFIFO is data only - */ -#define SDM_CH_SDCTRLE_DFIFO_S_T_MASK (0x200000UL) -#define SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT (21U) -#define SDM_CH_SDCTRLE_DFIFO_S_T_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK) -#define SDM_CH_SDCTRLE_DFIFO_S_T_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK) >> SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT) - -/* - * DATA_S_T (RW) - * - * "1: the read output of SData is data and timestamp interleaved. First is data. - * 0: the read output of SData is data only" - */ -#define SDM_CH_SDCTRLE_DATA_S_T_MASK (0x100000UL) -#define SDM_CH_SDCTRLE_DATA_S_T_SHIFT (20U) -#define SDM_CH_SDCTRLE_DATA_S_T_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_DATA_S_T_SHIFT) & SDM_CH_SDCTRLE_DATA_S_T_MASK) -#define SDM_CH_SDCTRLE_DATA_S_T_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_DATA_S_T_MASK) >> SDM_CH_SDCTRLE_DATA_S_T_SHIFT) - -/* - * SGD_ORDR (RW) - * - * CIC order - * 0: SYNC1 - * 1: SYNC2 - * 2: SYNC3 - * 3: FAST_SYNC - */ -#define SDM_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) -#define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) -#define SDM_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) -#define SDM_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) - -/* - * PWMSYNC (RW) - * - * Asserted to double sync the PWM trigger signal - */ -#define SDM_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) -#define SDM_CH_SDCTRLE_PWMSYNC_SHIFT (16U) -#define SDM_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK) -#define SDM_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT) - -/* - * CIC_SCL (RW) - * - * CIC shift control - */ -#define SDM_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) -#define SDM_CH_SDCTRLE_CIC_SCL_SHIFT (11U) -#define SDM_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK) -#define SDM_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation ratio. 0 means div-by-256 - */ -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) - -/* - * IGN_INI_SAMPLES (RW) - * - * NotZero: Don't store the first samples that are not accurate - * Zero: Store all samples - */ -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) - -/* Bitfield definition for register of struct array CH: SDST */ -/* - * PERIOD_MCLK (RO) - * - * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. - */ -#define SDM_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) -#define SDM_CH_SDST_PERIOD_MCLK_SHIFT (23U) -#define SDM_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT) - -/* - * SDATA_D0_T1 (RO) - * - * 1: next readout is timestamp - * 0: next readout is data - */ -#define SDM_CH_SDST_SDATA_D0_T1_MASK (0x2000U) -#define SDM_CH_SDST_SDATA_D0_T1_SHIFT (13U) -#define SDM_CH_SDST_SDATA_D0_T1_GET(x) (((uint32_t)(x) & SDM_CH_SDST_SDATA_D0_T1_MASK) >> SDM_CH_SDST_SDATA_D0_T1_SHIFT) - -/* - * SDFIFO_D0_T1 (RO) - * - * 1: next readout is timestamp - * 0: next readout is data - */ -#define SDM_CH_SDST_SDFIFO_D0_T1_MASK (0x1000U) -#define SDM_CH_SDST_SDFIFO_D0_T1_SHIFT (12U) -#define SDM_CH_SDST_SDFIFO_D0_T1_GET(x) (((uint32_t)(x) & SDM_CH_SDST_SDFIFO_D0_T1_MASK) >> SDM_CH_SDST_SDFIFO_D0_T1_SHIFT) - -/* - * FIFO_DR (W1C) - * - * FIFO data ready - */ -#define SDM_CH_SDST_FIFO_DR_MASK (0x200U) -#define SDM_CH_SDST_FIFO_DR_SHIFT (9U) -#define SDM_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK) -#define SDM_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT) - -/* - * AF (W1C) - * - * Achnowledge flag - */ -#define SDM_CH_SDST_AF_MASK (0x100U) -#define SDM_CH_SDST_AF_SHIFT (8U) -#define SDM_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDM_CH_SDST_AF_SHIFT) & SDM_CH_SDST_AF_MASK) -#define SDM_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDM_CH_SDST_AF_MASK) >> SDM_CH_SDST_AF_SHIFT) - -/* - * DOV_ERR (W1C) - * - * Data FIFO Overflow Error. Error flag. - */ -#define SDM_CH_SDST_DOV_ERR_MASK (0x80U) -#define SDM_CH_SDST_DOV_ERR_SHIFT (7U) -#define SDM_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK) -#define SDM_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT) - -/* - * DSAT_ERR (W1C) - * - * CIC out Data saturation err. Error flag. - */ -#define SDM_CH_SDST_DSAT_ERR_MASK (0x40U) -#define SDM_CH_SDST_DSAT_ERR_SHIFT (6U) -#define SDM_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK) -#define SDM_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT) - -/* - * WTSYNFLG (RO) - * - * Wait-for-sync event found - */ -#define SDM_CH_SDST_WTSYNFLG_MASK (0x20U) -#define SDM_CH_SDST_WTSYNFLG_SHIFT (5U) -#define SDM_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT) - -/* - * FILL (RO) - * - * Data FIFO Fillings - */ -#define SDM_CH_SDST_FILL_MASK (0x1FU) -#define SDM_CH_SDST_FILL_SHIFT (0U) -#define SDM_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT) - -/* Bitfield definition for register of struct array CH: SDATA */ -/* - * VAL (RO) - * - * Data - */ -#define SDM_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) -#define SDM_CH_SDATA_VAL_SHIFT (0U) -#define SDM_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SDFIFO */ -/* - * VAL (RO) - * - * FIFO Data - */ -#define SDM_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) -#define SDM_CH_SDFIFO_VAL_SHIFT (0U) -#define SDM_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCAMP */ -/* - * VAL (RO) - * - * instant Amplitude Results - */ -#define SDM_CH_SCAMP_VAL_MASK (0xFFFFU) -#define SDM_CH_SCAMP_VAL_SHIFT (0U) -#define SDM_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCHTL */ -/* - * VAL (RW) - * - * Amplitude Threshold for High Limit - */ -#define SDM_CH_SCHTL_VAL_MASK (0xFFFFU) -#define SDM_CH_SCHTL_VAL_SHIFT (0U) -#define SDM_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK) -#define SDM_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCHTLZ */ -/* - * VAL (RW) - * - * Amplitude Threshold for zero crossing - */ -#define SDM_CH_SCHTLZ_VAL_MASK (0xFFFFU) -#define SDM_CH_SCHTLZ_VAL_SHIFT (0U) -#define SDM_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK) -#define SDM_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCLLT */ -/* - * VAL (RW) - * - * Amplitude Threshold for low limit - */ -#define SDM_CH_SCLLT_VAL_MASK (0xFFFFU) -#define SDM_CH_SCLLT_VAL_SHIFT (0U) -#define SDM_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK) -#define SDM_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCCTRL */ -/* - * HZ_EN (RW) - * - * Zero Crossing Enable - */ -#define SDM_CH_SCCTRL_HZ_EN_MASK (0x800000UL) -#define SDM_CH_SCCTRL_HZ_EN_SHIFT (23U) -#define SDM_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK) -#define SDM_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT) - -/* - * MF_IE (RW) - * - * Module failure Interrupt enable - */ -#define SDM_CH_SCCTRL_MF_IE_MASK (0x400000UL) -#define SDM_CH_SCCTRL_MF_IE_SHIFT (22U) -#define SDM_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK) -#define SDM_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT) - -/* - * HL_IE (RW) - * - * HLT Interrupt Enable - */ -#define SDM_CH_SCCTRL_HL_IE_MASK (0x200000UL) -#define SDM_CH_SCCTRL_HL_IE_SHIFT (21U) -#define SDM_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK) -#define SDM_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT) - -/* - * LL_IE (RW) - * - * LLT interrupt Enable - */ -#define SDM_CH_SCCTRL_LL_IE_MASK (0x100000UL) -#define SDM_CH_SCCTRL_LL_IE_SHIFT (20U) -#define SDM_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK) -#define SDM_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT) - -/* - * SGD_ORDR (RW) - * - * CIC order - * 0: SYNC1 - * 1: SYNC2 - * 2: SYNC3 - * 3: FAST_SYNC - */ -#define SDM_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) -#define SDM_CH_SCCTRL_SGD_ORDR_SHIFT (18U) -#define SDM_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK) -#define SDM_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation ratio. 0 means div-by-32 - */ -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) - -/* - * IGN_INI_SAMPLES (RW) - * - * NotZero: Ignore the first samples that are not accurate - * Zero: Use all samples - */ -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) - -/* - * EN (RW) - * - * Amplitude Path Enable - */ -#define SDM_CH_SCCTRL_EN_MASK (0x1U) -#define SDM_CH_SCCTRL_EN_SHIFT (0U) -#define SDM_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK) -#define SDM_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT) - -/* Bitfield definition for register of struct array CH: SCST */ -/* - * HZ (W1C) - * - * Amplitude rising above HZ event found. - */ -#define SDM_CH_SCST_HZ_MASK (0x8U) -#define SDM_CH_SCST_HZ_SHIFT (3U) -#define SDM_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK) -#define SDM_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT) - -/* - * MF (W1C) - * - * power modulator Failure found. MCLK not found. Error flag. - */ -#define SDM_CH_SCST_MF_MASK (0x4U) -#define SDM_CH_SCST_MF_SHIFT (2U) -#define SDM_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK) -#define SDM_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT) - -/* - * CMPH (W1C) - * - * HLT out of range. Error flag. - */ -#define SDM_CH_SCST_CMPH_MASK (0x2U) -#define SDM_CH_SCST_CMPH_SHIFT (1U) -#define SDM_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK) -#define SDM_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT) - -/* - * CMPL (W1C) - * - * LLT out of range. Error flag. - */ -#define SDM_CH_SCST_CMPL_MASK (0x1U) -#define SDM_CH_SCST_CMPL_SHIFT (0U) -#define SDM_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK) -#define SDM_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT) - - - -/* CH register group index macro definition */ -#define SDM_CH_0 (0UL) -#define SDM_CH_1 (1UL) -#define SDM_CH_2 (2UL) -#define SDM_CH_3 (3UL) - - -#endif /* HPM_SDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sdp_regs.h deleted file mode 100644 index 7562ad654a5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sdp_regs.h +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDP_H -#define HPM_SDP_H - -typedef struct { - __RW uint32_t SDPCR; /* 0x0: SDP control register */ - __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ - __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ - __RW uint32_t STA; /* 0xC: Status Registers */ - __RW uint32_t KEYADDR; /* 0x10: Key Address */ - __RW uint32_t KEYDAT; /* 0x14: Key Data */ - __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ - __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ - __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ - __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ - __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ - __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ - __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ - __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ -} SDP_Type; - - -/* Bitfield definition for register: SDPCR */ -/* - * SFTRST (RW) - * - * soft reset. - * Write 1 then 0, to reset the SDP block. - */ -#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) -#define SDP_SDPCR_SFTRST_SHIFT (31U) -#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) -#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) - -/* - * CLKGAT (RW) - * - * Clock Gate for the SDP main logic. - * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - */ -#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) -#define SDP_SDPCR_CLKGAT_SHIFT (30U) -#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) -#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) - -/* - * CIPDIS (RO) - * - * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. - * 1, Cipher is disabled in this chip. - * 0, Cipher is enabled in this chip. - */ -#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) -#define SDP_SDPCR_CIPDIS_SHIFT (29U) -#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) - -/* - * HASDIS (RO) - * - * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. - * 1, HASH is disabled in this chip. - * 0, HASH is enabled in this chip. - */ -#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) -#define SDP_SDPCR_HASDIS_SHIFT (28U) -#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) - -/* - * CIPHEN (RW) - * - * Cipher Enablement, controlled by SW. - * 1, Cipher is Enabled. - * 0, Cipher is Disabled. - */ -#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) -#define SDP_SDPCR_CIPHEN_SHIFT (23U) -#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) -#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) - -/* - * HASHEN (RW) - * - * HASH Enablement, controlled by SW. - * 1, HASH is Enabled. - * 0, HASH is Disabled. - */ -#define SDP_SDPCR_HASHEN_MASK (0x400000UL) -#define SDP_SDPCR_HASHEN_SHIFT (22U) -#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) -#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) - -/* - * MCPEN (RW) - * - * Memory Copy Enablement, controlled by SW. - * 1, Memory copy is Enabled. - * 0, Memory copy is Disabled. - */ -#define SDP_SDPCR_MCPEN_MASK (0x200000UL) -#define SDP_SDPCR_MCPEN_SHIFT (21U) -#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) -#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) - -/* - * CONFEN (RW) - * - * Constant Fill to memory, controlled by SW. - * 1, Constant fill is Enabled. - * 0, Constant fill is Disabled. - */ -#define SDP_SDPCR_CONFEN_MASK (0x100000UL) -#define SDP_SDPCR_CONFEN_SHIFT (20U) -#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) -#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) - -/* - * DCRPDI (RW) - * - * Decryption Disable bit, Write to 1 to disable the decryption. - */ -#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) -#define SDP_SDPCR_DCRPDI_SHIFT (19U) -#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) -#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) - -/* - * TSTPKT0IRQ (RW) - * - * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - */ -#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) -#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) -#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) -#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) - -/* - * RDSCEN (RW) - * - * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) - * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - */ -#define SDP_SDPCR_RDSCEN_MASK (0x100U) -#define SDP_SDPCR_RDSCEN_SHIFT (8U) -#define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK) -#define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT) - -/* - * INTEN (RW) - * - * Interrupt Enablement, controlled by SW. - * 1, SDP interrupt is enabled. - * 0, SDP interrupt is disabled. - */ -#define SDP_SDPCR_INTEN_MASK (0x1U) -#define SDP_SDPCR_INTEN_SHIFT (0U) -#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) -#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) - -/* Bitfield definition for register: MODCTRL */ -/* - * AESALG (RW) - * - * AES algorithem selection. - * 0x0 = AES 128; - * 0x1 = AES 256; - * 0x8 = SM4； - * Others, reserved. - */ -#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) -#define SDP_MODCTRL_AESALG_SHIFT (28U) -#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) -#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) - -/* - * AESMOD (RW) - * - * AES mode selection. - * 0x0 = ECB; - * 0x1 = CBC; - * Others, reserved. - */ -#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) -#define SDP_MODCTRL_AESMOD_SHIFT (24U) -#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) -#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) - -/* - * AESKS (RW) - * - * AES Key Selection. - * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: - * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. - * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * .... - * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. - * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. - * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. - * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. - * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. - * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. - * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. - * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. - * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. - * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. - * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. - * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. - * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. - * Other values, reserved. - */ -#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) -#define SDP_MODCTRL_AESKS_SHIFT (18U) -#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) -#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) - -/* - * AESDIR (RW) - * - * AES direction - * 1x1, AES Decryption - * 1x0, AES Encryption. - */ -#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) -#define SDP_MODCTRL_AESDIR_SHIFT (16U) -#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) -#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) - -/* - * HASALG (RW) - * - * HASH Algorithem selection. - * 0x0 SHA1 — - * 0x1 CRC32 — - * 0x2 SHA256 — - */ -#define SDP_MODCTRL_HASALG_MASK (0xF000U) -#define SDP_MODCTRL_HASALG_SHIFT (12U) -#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) -#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) - -/* - * HASCHK (RW) - * - * HASH Check Enable Bit. - * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; - * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. - * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - */ -#define SDP_MODCTRL_HASCHK_MASK (0x400U) -#define SDP_MODCTRL_HASCHK_SHIFT (10U) -#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) -#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) - -/* - * HASOUT (RW) - * - * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. - * 0 INPUT HASH - * 1 OUTPUT HASH - */ -#define SDP_MODCTRL_HASOUT_MASK (0x200U) -#define SDP_MODCTRL_HASOUT_SHIFT (9U) -#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) -#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) - -/* - * DINSWP (RW) - * - * Decide whether the SDP byteswaps the input data (big-endian data); - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DINSWP_MASK (0x30U) -#define SDP_MODCTRL_DINSWP_SHIFT (4U) -#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) -#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) - -/* - * DOUTSWP (RW) - * - * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) -#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) -#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) -#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) - -/* - * KEYSWP (RW) - * - * Decide whether the SDP byteswaps the Key (big-endian data). - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_KEYSWP_MASK (0x3U) -#define SDP_MODCTRL_KEYSWP_SHIFT (0U) -#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) -#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) - -/* Bitfield definition for register: PKTCNT */ -/* - * CNTVAL (RO) - * - * This read-only field shows the current (instantaneous) value of the packet counter - */ -#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) -#define SDP_PKTCNT_CNTVAL_SHIFT (16U) -#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) - -/* - * CNTINCR (RW) - * - * The value written to this field is added to the spacket count. - */ -#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) -#define SDP_PKTCNT_CNTINCR_SHIFT (0U) -#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) -#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TAG (RO) - * - * packet tag. - */ -#define SDP_STA_TAG_MASK (0xFF000000UL) -#define SDP_STA_TAG_SHIFT (24U) -#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) - -/* - * IRQ (W1C) - * - * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - */ -#define SDP_STA_IRQ_MASK (0x800000UL) -#define SDP_STA_IRQ_SHIFT (23U) -#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) -#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) - -/* - * CHN1PKT0 (W1C) - * - * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - */ -#define SDP_STA_CHN1PKT0_MASK (0x100000UL) -#define SDP_STA_CHN1PKT0_SHIFT (20U) -#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) -#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) - -/* - * AESBSY (RO) - * - * AES Busy - */ -#define SDP_STA_AESBSY_MASK (0x80000UL) -#define SDP_STA_AESBSY_SHIFT (19U) -#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) - -/* - * HASBSY (RO) - * - * Hashing Busy - */ -#define SDP_STA_HASBSY_MASK (0x40000UL) -#define SDP_STA_HASBSY_SHIFT (18U) -#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) - -/* - * PKTCNT0 (W1C) - * - * Packet Counter registers reachs to ZERO now. - */ -#define SDP_STA_PKTCNT0_MASK (0x20000UL) -#define SDP_STA_PKTCNT0_SHIFT (17U) -#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) -#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) - -/* - * PKTDON (W1C) - * - * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - */ -#define SDP_STA_PKTDON_MASK (0x10000UL) -#define SDP_STA_PKTDON_SHIFT (16U) -#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) -#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) - -/* - * ERRSET (W1C) - * - * Working mode setup error. - */ -#define SDP_STA_ERRSET_MASK (0x20U) -#define SDP_STA_ERRSET_SHIFT (5U) -#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) -#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) - -/* - * ERRPKT (W1C) - * - * Packet head access error, or status update error. - */ -#define SDP_STA_ERRPKT_MASK (0x10U) -#define SDP_STA_ERRPKT_SHIFT (4U) -#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) -#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) - -/* - * ERRSRC (W1C) - * - * Source Buffer Access Error - */ -#define SDP_STA_ERRSRC_MASK (0x8U) -#define SDP_STA_ERRSRC_SHIFT (3U) -#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) -#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) - -/* - * ERRDST (W1C) - * - * Destination Buffer Error - */ -#define SDP_STA_ERRDST_MASK (0x4U) -#define SDP_STA_ERRDST_SHIFT (2U) -#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) -#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) - -/* - * ERRHAS (W1C) - * - * Hashing Check Error - */ -#define SDP_STA_ERRHAS_MASK (0x2U) -#define SDP_STA_ERRHAS_SHIFT (1U) -#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) -#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) - -/* - * ERRCHAIN (W1C) - * - * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - */ -#define SDP_STA_ERRCHAIN_MASK (0x1U) -#define SDP_STA_ERRCHAIN_SHIFT (0U) -#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) -#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) - -/* Bitfield definition for register: KEYADDR */ -/* - * INDEX (RW) - * - * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. - * Key index pointer. The valid indices are 0-[number_keys]. - * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - */ -#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) -#define SDP_KEYADDR_INDEX_SHIFT (16U) -#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) -#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) - -/* - * SUBWRD (RW) - * - * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field - * increments; To write a key, the software must first write the desired key index/subword to this register. - */ -#define SDP_KEYADDR_SUBWRD_MASK (0x3U) -#define SDP_KEYADDR_SUBWRD_SHIFT (0U) -#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) -#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) - -/* Bitfield definition for register: KEYDAT */ -/* - * KEYDAT (RW) - * - * This register provides the write access to the key/key subword specified by the key index register. - * Writing this location updates the selected subword for the key located at the index - * specified by the key index register. The write also triggers the SUBWORD field of the - * KEY register to increment to the next higher word in the key - */ -#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) -#define SDP_KEYDAT_KEYDAT_SHIFT (0U) -#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) -#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) - -/* Bitfield definition for register array: CIPHIV */ -/* - * CIPHIV (RW) - * - * cipher initialization vector. - */ -#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) -#define SDP_CIPHIV_CIPHIV_SHIFT (0U) -#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) -#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) - -/* Bitfield definition for register array: HASWRD */ -/* - * HASWRD (RW) - * - * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. - * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - */ -#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) -#define SDP_HASWRD_HASWRD_SHIFT (0U) -#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) -#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) - -/* Bitfield definition for register: CMDPTR */ -/* - * CMDPTR (RW) - * - * current command addresses the register points to the multiword - * descriptor that is to be executed (or is currently being executed) - */ -#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) -#define SDP_CMDPTR_CMDPTR_SHIFT (0U) -#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) -#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) - -/* Bitfield definition for register: NPKTPTR */ -/* - * NPKTPTR (RW) - * - * Next Packet Address Pointer - */ -#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) -#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) -#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) -#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) - -/* Bitfield definition for register: PKTCTL */ -/* - * PKTTAG (RW) - * - * packet tag - */ -#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) -#define SDP_PKTCTL_PKTTAG_SHIFT (24U) -#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) -#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) - -/* - * CIPHIV (RW) - * - * Load Initial Vector for the AES in this packet. - */ -#define SDP_PKTCTL_CIPHIV_MASK (0x40U) -#define SDP_PKTCTL_CIPHIV_SHIFT (6U) -#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) -#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) - -/* - * HASFNL (RW) - * - * Hash Termination packet - */ -#define SDP_PKTCTL_HASFNL_MASK (0x20U) -#define SDP_PKTCTL_HASFNL_SHIFT (5U) -#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) -#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) - -/* - * HASINI (RW) - * - * Hash Initialization packat - */ -#define SDP_PKTCTL_HASINI_MASK (0x10U) -#define SDP_PKTCTL_HASINI_SHIFT (4U) -#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) -#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) - -/* - * CHAIN (RW) - * - * whether the next command pointer register must be loaded into the channel's current descriptor - * pointer. - */ -#define SDP_PKTCTL_CHAIN_MASK (0x8U) -#define SDP_PKTCTL_CHAIN_SHIFT (3U) -#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) -#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) - -/* - * DCRSEMA (RW) - * - * whether the channel's semaphore must be decremented at the end of the current operation. - * When the semaphore reaches a value of zero, no more operations are issued from the channel. - */ -#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) -#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) -#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) -#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) - -/* - * PKTINT (RW) - * - * Reflects whether the channel must issue an interrupt upon the completion of the packet - */ -#define SDP_PKTCTL_PKTINT_MASK (0x2U) -#define SDP_PKTCTL_PKTINT_SHIFT (1U) -#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) -#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) - -/* Bitfield definition for register: PKTSRC */ -/* - * PKTSRC (RW) - * - * Packet Memory Source Address - */ -#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) -#define SDP_PKTSRC_PKTSRC_SHIFT (0U) -#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) -#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) - -/* Bitfield definition for register: PKTDST */ -/* - * PKTDST (RW) - * - * Packet Memory Destination Address - */ -#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) -#define SDP_PKTDST_PKTDST_SHIFT (0U) -#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) -#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) - -/* Bitfield definition for register: PKTBUF */ -/* - * PKTBUF (RW) - * - */ -#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) -#define SDP_PKTBUF_PKTBUF_SHIFT (0U) -#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) -#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) - - - -/* CIPHIV register group index macro definition */ -#define SDP_CIPHIV_CIPHIV0 (0UL) -#define SDP_CIPHIV_CIPHIV1 (1UL) -#define SDP_CIPHIV_CIPHIV2 (2UL) -#define SDP_CIPHIV_CIPHIV3 (3UL) - -/* HASWRD register group index macro definition */ -#define SDP_HASWRD_HASWRD0 (0UL) -#define SDP_HASWRD_HASWRD1 (1UL) -#define SDP_HASWRD_HASWRD2 (2UL) -#define SDP_HASWRD_HASWRD3 (3UL) -#define SDP_HASWRD_HASWRD4 (4UL) -#define SDP_HASWRD_HASWRD5 (5UL) -#define SDP_HASWRD_HASWRD6 (6UL) -#define SDP_HASWRD_HASWRD7 (7UL) - - -#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_spi_regs.h deleted file mode 100644 index 8ee088e0d91..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_spi_regs.h +++ /dev/null @@ -1,784 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SPI_H -#define HPM_SPI_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ - __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ - __RW uint32_t CMD; /* 0x24: Command Register */ - __RW uint32_t ADDR; /* 0x28: Address Register */ - __RW uint32_t DATA; /* 0x2C: Data Register */ - __RW uint32_t CTRL; /* 0x30: Control Register */ - __R uint32_t STATUS; /* 0x34: Status Register */ - __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ - __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */ - __RW uint32_t SLVST; /* 0x60: Slave Status Register */ - __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */ - __R uint32_t CONFIG; /* 0x7C: Configuration Register */ -} SPI_Type; - - -/* Bitfield definition for register: TRANSFMT */ -/* - * ADDRLEN (RW) - * - * Address length in bytes - * 0x0: 1 byte - * 0x1: 2 bytes - * 0x2: 3 bytes - * 0x3: 4 bytes - */ -#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) -#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) -#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) -#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) - -/* - * DATALEN (RW) - * - * The length of each data unit in bits - * The actual bit number of a data unit is (DataLen + 1) - */ -#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) -#define SPI_TRANSFMT_DATALEN_SHIFT (8U) -#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) -#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) - -/* - * DATAMERGE (RW) - * - * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. - * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. - * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - */ -#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) -#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) -#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) -#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) - -/* - * MOSIBIDIR (RW) - * - * Bi-directional MOSI in regular (single) mode - * 0x0: MOSI is uni-directional signal in regular mode. - * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - */ -#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) -#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) -#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) -#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) - -/* - * LSB (RW) - * - * Transfer data with the least significant bit first - * 0x0: Most significant bit first - * 0x1: Least significant bit first - */ -#define SPI_TRANSFMT_LSB_MASK (0x8U) -#define SPI_TRANSFMT_LSB_SHIFT (3U) -#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) -#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) - -/* - * SLVMODE (RW) - * - * SPI Master/Slave mode selection - * 0x0: Master mode - * 0x1: Slave mode - */ -#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) -#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) -#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) -#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) - -/* - * CPOL (RW) - * - * SPI Clock Polarity - * 0x0: SCLK is LOW in the idle states - * 0x1: SCLK is HIGH in the idle states - */ -#define SPI_TRANSFMT_CPOL_MASK (0x2U) -#define SPI_TRANSFMT_CPOL_SHIFT (1U) -#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) -#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) - -/* - * CPHA (RW) - * - * SPI Clock Phase - * 0x0: Sampling data at odd SCLK edges - * 0x1: Sampling data at even SCLK edges - */ -#define SPI_TRANSFMT_CPHA_MASK (0x1U) -#define SPI_TRANSFMT_CPHA_SHIFT (0U) -#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) -#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) - -/* Bitfield definition for register: TRANSCTRL */ -/* - * SLVDATAONLY (RW) - * - * Data-only mode (slave mode only) - * 0x0: Disable the data-only mode - * 0x1: Enable the data-only mode - * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - */ -#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) -#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) -#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) -#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) - -/* - * CMDEN (RW) - * - * SPI command phase enable (Master mode only) - * 0x0: Disable the command phase - * 0x1: Enable the command phase - */ -#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) -#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) -#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) -#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) - -/* - * ADDREN (RW) - * - * SPI address phase enable (Master mode only) - * 0x0: Disable the address phase - * 0x1: Enable the address phase - */ -#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) -#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) -#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) -#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) - -/* - * ADDRFMT (RW) - * - * SPI address phase format (Master mode only) - * 0x0: Address phase is the regular (single) mode - * 0x1: The format of the address phase is the same as the data phase (DualQuad). - */ -#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) -#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) -#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) -#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) - -/* - * TRANSMODE (RW) - * - * Transfer mode - * The transfer sequence could be - * 0x0: Write and read at the same time - * 0x1: Write only - * 0x2: Read only - * 0x3: Write, Read - * 0x4: Read, Write - * 0x5: Write, Dummy, Read - * 0x6: Read, Dummy, Write - * 0x7: None Data (must enable CmdEn or AddrEn in master mode) - * 0x8: Dummy, Write - * 0x9: Dummy, Read - * 0xa~0xf: Reserved - */ -#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) -#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) -#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) -#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) - -/* - * DUALQUAD (RW) - * - * SPI data phase format - * 0x0: Regular (Single) mode - * 0x1: Dual I/O mode - * 0x2: Quad I/O mode - * 0x3: Reserved - */ -#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) -#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) -#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) -#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) - -/* - * TOKENEN (RW) - * - * Token transfer enable (Master mode only) - * Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. - * 0x0: Disable the one-byte special token - * 0x1: Enable the one-byte special token - */ -#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) -#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) -#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) -#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) - -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) -#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) -#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) -#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) - -/* - * TOKENVALUE (RW) - * - * Token value (Master mode only) - * The value of the one-byte special token following the address phase for SPI read transfers. - * 0x0: token value = 0x00 - * 0x1: token value = 0x69 - */ -#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) -#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) -#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) -#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) - -/* - * DUMMYCNT (RW) - * - * Dummy data count. The actual dummy count is (DummyCnt +1). - * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) - * The Data pins are put into the high impedance during the dummy data phase. - * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - */ -#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) -#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) -#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) -#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) - -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) -#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) -#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) -#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * SPI Command - */ -#define SPI_CMD_CMD_MASK (0xFFU) -#define SPI_CMD_CMD_SHIFT (0U) -#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) -#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * SPI Address - * (Master mode only) - */ -#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define SPI_ADDR_ADDR_SHIFT (0U) -#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) -#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Data to transmit or the received data - * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. - * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - */ -#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SPI_DATA_DATA_SHIFT (0U) -#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) -#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * TXTHRES (RW) - * - * Transmit (TX) FIFO Threshold - * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - */ -#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) -#define SPI_CTRL_TXTHRES_SHIFT (16U) -#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) -#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) - -/* - * RXTHRES (RW) - * - * Receive (RX) FIFO Threshold - * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - */ -#define SPI_CTRL_RXTHRES_MASK (0xFF00U) -#define SPI_CTRL_RXTHRES_SHIFT (8U) -#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) -#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) - -/* - * TXDMAEN (RW) - * - * TX DMA enable - */ -#define SPI_CTRL_TXDMAEN_MASK (0x10U) -#define SPI_CTRL_TXDMAEN_SHIFT (4U) -#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) -#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) - -/* - * RXDMAEN (RW) - * - * RX DMA enable - */ -#define SPI_CTRL_RXDMAEN_MASK (0x8U) -#define SPI_CTRL_RXDMAEN_SHIFT (3U) -#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) -#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) - -/* - * TXFIFORST (RW) - * - * Transmit FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_TXFIFORST_MASK (0x4U) -#define SPI_CTRL_TXFIFORST_SHIFT (2U) -#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) -#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) - -/* - * RXFIFORST (RW) - * - * Receive FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_RXFIFORST_MASK (0x2U) -#define SPI_CTRL_RXFIFORST_SHIFT (1U) -#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) -#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) - -/* - * SPIRST (RW) - * - * SPI reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_SPIRST_MASK (0x1U) -#define SPI_CTRL_SPIRST_SHIFT (0U) -#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) -#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TXNUM_7_6 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) -#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) -#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) - -/* - * RXNUM_7_6 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) -#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) -#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) - -/* - * TXFULL (RO) - * - * Transmit FIFO Full flag - */ -#define SPI_STATUS_TXFULL_MASK (0x800000UL) -#define SPI_STATUS_TXFULL_SHIFT (23U) -#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) - -/* - * TXEMPTY (RO) - * - * Transmit FIFO Empty flag - */ -#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) -#define SPI_STATUS_TXEMPTY_SHIFT (22U) -#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) - -/* - * TXNUM_5_0 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) -#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) -#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) - -/* - * RXFULL (RO) - * - * Receive FIFO Full flag - */ -#define SPI_STATUS_RXFULL_MASK (0x8000U) -#define SPI_STATUS_RXFULL_SHIFT (15U) -#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) - -/* - * RXEMPTY (RO) - * - * Receive FIFO Empty flag - */ -#define SPI_STATUS_RXEMPTY_MASK (0x4000U) -#define SPI_STATUS_RXEMPTY_SHIFT (14U) -#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) - -/* - * RXNUM_5_0 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) -#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) -#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) - -/* - * SPIACTIVE (RO) - * - * SPI register programming is in progress. - * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. - * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. - * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. - * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - */ -#define SPI_STATUS_SPIACTIVE_MASK (0x1U) -#define SPI_STATUS_SPIACTIVE_SHIFT (0U) -#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) - -/* Bitfield definition for register: INTREN */ -/* - * SLVCMDEN (RW) - * - * Enable the Slave Command Interrupt. - * Control whether interrupts are triggered whenever slave commands are received. - * (Slave mode only) - */ -#define SPI_INTREN_SLVCMDEN_MASK (0x20U) -#define SPI_INTREN_SLVCMDEN_SHIFT (5U) -#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) -#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) - -/* - * ENDINTEN (RW) - * - * Enable the End of SPI Transfer interrupt. - * Control whether interrupts are triggered when SPI transfers end. - * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - */ -#define SPI_INTREN_ENDINTEN_MASK (0x10U) -#define SPI_INTREN_ENDINTEN_SHIFT (4U) -#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) -#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) - -/* - * TXFIFOINTEN (RW) - * - * Enable the SPI Transmit FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - */ -#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) -#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) -#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) -#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) - -/* - * RXFIFOINTEN (RW) - * - * Enable the SPI Receive FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - */ -#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) -#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) -#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) -#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) - -/* - * TXFIFOURINTEN (RW) - * - * Enable the SPI Transmit FIFO Underrun interrupt. - * Control whether interrupts are triggered when the Transmit FIFO run out of data. - * (Slave mode only) - */ -#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) -#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) -#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) -#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) - -/* - * RXFIFOORINTEN (RW) - * - * Enable the SPI Receive FIFO Overrun interrupt. - * Control whether interrupts are triggered when the Receive FIFO overflows. - * (Slave mode only) - */ -#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) -#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) -#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) -#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) - -/* Bitfield definition for register: INTRST */ -/* - * SLVCMDINT (W1C) - * - * Slave Command Interrupt. - * This bit is set when Slave Command interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_SLVCMDINT_MASK (0x20U) -#define SPI_INTRST_SLVCMDINT_SHIFT (5U) -#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) -#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) - -/* - * ENDINT (W1C) - * - * End of SPI Transfer interrupt. - * This bit is set when End of SPI Transfer interrupts occur. - */ -#define SPI_INTRST_ENDINT_MASK (0x10U) -#define SPI_INTRST_ENDINT_SHIFT (4U) -#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) -#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) - -/* - * TXFIFOINT (W1C) - * - * TX FIFO Threshold interrupt. - * This bit is set when TX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_TXFIFOINT_MASK (0x8U) -#define SPI_INTRST_TXFIFOINT_SHIFT (3U) -#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) -#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) - -/* - * RXFIFOINT (W1C) - * - * RX FIFO Threshold interrupt. - * This bit is set when RX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_RXFIFOINT_MASK (0x4U) -#define SPI_INTRST_RXFIFOINT_SHIFT (2U) -#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) -#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) - -/* - * TXFIFOURINT (W1C) - * - * TX FIFO Underrun interrupt. - * This bit is set when TX FIFO Underrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) -#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) -#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) -#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) - -/* - * RXFIFOORINT (W1C) - * - * RX FIFO Overrun interrupt. - * This bit is set when RX FIFO Overrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) -#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) -#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) -#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) - -/* Bitfield definition for register: TIMING */ -/* - * CS2SCLK (RW) - * - * The minimum time between the edges of SPI CS and the edges of SCLK. - * SCLK_period * (CS2SCLK + 1) / 2 - */ -#define SPI_TIMING_CS2SCLK_MASK (0x3000U) -#define SPI_TIMING_CS2SCLK_SHIFT (12U) -#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) -#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) - -/* - * CSHT (RW) - * - * The minimum time that SPI CS should stay HIGH. - * SCLK_period * (CSHT + 1) / 2 - */ -#define SPI_TIMING_CSHT_MASK (0xF00U) -#define SPI_TIMING_CSHT_SHIFT (8U) -#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) -#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) - -/* - * SCLK_DIV (RW) - * - * The clock frequency ratio between the clock source and SPI interface SCLK. - * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) - * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - */ -#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) -#define SPI_TIMING_SCLK_DIV_SHIFT (0U) -#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) -#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) - -/* Bitfield definition for register: SLVST */ -/* - * UNDERRUN (W1C) - * - * Data underrun occurs in the last transaction - */ -#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) -#define SPI_SLVST_UNDERRUN_SHIFT (18U) -#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) -#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) - -/* - * OVERRUN (RW) - * - * Data overrun occurs in the last transaction - */ -#define SPI_SLVST_OVERRUN_MASK (0x20000UL) -#define SPI_SLVST_OVERRUN_SHIFT (17U) -#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) -#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) - -/* - * READY (RW) - * - * Set this bit to indicate that the ATCSPI200 is ready for data transaction. - * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - */ -#define SPI_SLVST_READY_MASK (0x10000UL) -#define SPI_SLVST_READY_SHIFT (16U) -#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) -#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) - -/* - * USR_STATUS (RW) - * - * User defined status flags - */ -#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) -#define SPI_SLVST_USR_STATUS_SHIFT (0U) -#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) -#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) - -/* Bitfield definition for register: SLVDATACNT */ -/* - * WCNT (RO) - * - * Slave transmitted data count - */ -#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) -#define SPI_SLVDATACNT_WCNT_SHIFT (16U) -#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) - -/* - * RCNT (RO) - * - * Slave received data count - */ -#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) -#define SPI_SLVDATACNT_RCNT_SHIFT (0U) -#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * SLAVE (RO) - * - * Support for SPI Slave mode - */ -#define SPI_CONFIG_SLAVE_MASK (0x4000U) -#define SPI_CONFIG_SLAVE_SHIFT (14U) -#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) - -/* - * QUADSPI (RO) - * - * Support for Quad I/O SPI - */ -#define SPI_CONFIG_QUADSPI_MASK (0x200U) -#define SPI_CONFIG_QUADSPI_SHIFT (9U) -#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) - -/* - * DUALSPI (RO) - * - * Support for Dual I/O SPI - */ -#define SPI_CONFIG_DUALSPI_MASK (0x100U) -#define SPI_CONFIG_DUALSPI_SHIFT (8U) -#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) - -/* - * TXFIFOSIZE (RO) - * - * Depth of TX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) -#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) -#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) - -/* - * RXFIFOSIZE (RO) - * - * Depth of RX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) -#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) -#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) - - - - -#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_synt_regs.h deleted file mode 100644 index 6e88bde3e4e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_synt_regs.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYNT_H -#define HPM_SYNT_H - -typedef struct { - __RW uint32_t GCR; /* 0x0: Global control register */ - __RW uint32_t RLD; /* 0x4: Counter reload register */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ - __R uint32_t CNT; /* 0xC: Counter */ - __R uint8_t RESERVED1[16]; /* 0x10 - 0x1F: Reserved */ - __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ -} SYNT_Type; - - -/* Bitfield definition for register: GCR */ -/* - * CRST (RW) - * - * 1- Reset counter - */ -#define SYNT_GCR_CRST_MASK (0x2U) -#define SYNT_GCR_CRST_SHIFT (1U) -#define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK) -#define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT) - -/* - * CEN (RW) - * - * 1- Enable counter - */ -#define SYNT_GCR_CEN_MASK (0x1U) -#define SYNT_GCR_CEN_SHIFT (0U) -#define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK) -#define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * RLD (RW) - * - * counter reload value - */ -#define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL) -#define SYNT_RLD_RLD_SHIFT (0U) -#define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) -#define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * CNT (RO) - * - * counter - */ -#define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL) -#define SYNT_CNT_CNT_SHIFT (0U) -#define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CMP */ -/* - * CMP (RW) - * - * comparator value, the output will assert when counter count to this value - */ -#define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL) -#define SYNT_CMP_CMP_SHIFT (0U) -#define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK) -#define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT) - - - -/* CMP register group index macro definition */ -#define SYNT_CMP_0 (0UL) -#define SYNT_CMP_1 (1UL) -#define SYNT_CMP_2 (2UL) -#define SYNT_CMP_3 (3UL) - - -#endif /* HPM_SYNT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sysctl_regs.h deleted file mode 100644 index 62b2a715c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_sysctl_regs.h +++ /dev/null @@ -1,1403 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYSCTL_H -#define HPM_SYSCTL_H - -typedef struct { - __RW uint32_t RESOURCE[322]; /* 0x0 - 0x504: Resource control register for cpu0_core */ - __R uint8_t RESERVED0[760]; /* 0x508 - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: Group setting */ - __RW uint32_t SET; /* 0x804: Group setting */ - __RW uint32_t CLEAR; /* 0x808: Group setting */ - __RW uint32_t TOGGLE; /* 0x80C: Group setting */ - } GROUP0[3]; - __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x840: Group setting */ - __RW uint32_t SET; /* 0x844: Group setting */ - __RW uint32_t CLEAR; /* 0x848: Group setting */ - __RW uint32_t TOGGLE; /* 0x84C: Group setting */ - } GROUP1[3]; - __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ - __RW uint32_t SET; /* 0x904: Affiliate of Group */ - __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ - __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ - } AFFILIATE[2]; - struct { - __RW uint32_t VALUE; /* 0x920: Retention Control */ - __RW uint32_t SET; /* 0x924: Retention Control */ - __RW uint32_t CLEAR; /* 0x928: Retention Control */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ - } RETENTION[2]; - __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ - struct { - __RW uint32_t STATUS; /* 0x1000: Power Setting */ - __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ - __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ - __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ - } POWER[2]; - __R uint8_t RESERVED4[992]; /* 0x1020 - 0x13FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ - __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ - __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ - __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ - } RESET[3]; - __R uint8_t RESERVED5[976]; /* 0x1430 - 0x17FF: Reserved */ - __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ - __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */ - __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */ - __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */ - __RW uint32_t DACCLK[2]; /* 0x1C0C - 0x1C10: Clock setting */ - __R uint8_t RESERVED7[1004]; /* 0x1C14 - 0x1FFF: Reserved */ - __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ - __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ - __R uint32_t CURRENT; /* 0x2404: Clock measure result */ - __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ - __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ - __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ - } MONITOR[4]; - __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ - struct { - __RW uint32_t LP; /* 0x2800: CPU0 LP control */ - __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ - __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ - __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ - __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ - __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ - __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ - } CPU[2]; -} SYSCTL_Type; - - -/* Bitfield definition for register array: RESOURCE */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any nodes - * 1: any of nodes is changing status - */ -#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) -#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: no change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) -#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) - -/* - * MODE (RW) - * - * resource work mode - * 0:auto turn on and off as system required(recommended) - * 1:always on - * 2:always off - * 3:reserved - */ -#define SYSCTL_RESOURCE_MODE_MASK (0x3U) -#define SYSCTL_RESOURCE_MODE_SHIFT (0U) -#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) -#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) -#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) -#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) -#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK) -#define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK) -#define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK) -#define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: VALUE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * bit0: cpu0 depends on group0 - * bit1: cpu0 depends on group1 - * bit2: cpu0 depends on group2 - * bit3: cpu0 depends on group3 - */ -#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) -#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: SET */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0，each bit represents a group - * 0: no effect - * 1: the group is assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) -#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: the group is not assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) -#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: toggle the result that whether the group is assigned to CPU0 before - */ -#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: VALUE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * bit00: soc_mem is kept on while cpu0 stop - * bit01: soc_ctx is kept on while cpu0 stop - * bit02: cpu0_mem is kept on while cpu0 stop - * bit03: cpu0_ctx is kept on while cpu0 stop - * bit04: cpu1_mem is kept on while cpu0 stop - * bit05: cpu1_ctx is kept on while cpu0 stop - * bit06: xtal_hold is kept on while cpu0 stop - * bit07: pll0_hold is kept on while cpu0 stop - * bit08: pll1_hold is kept on while cpu0 stop - * bit09: pll2_hold is kept on while cpu0 stop - */ -#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFU) -#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) -#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: SET */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: keep - */ -#define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFU) -#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) -#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: CLEAR */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: no keep - */ -#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFU) -#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) -#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: TOGGLE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: toggle the result that whether the resource is kept on while CPU0 stop before - */ -#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFU) -#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) -#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array POWER: STATUS */ -/* - * FLAG (RW) - * - * flag represents power cycle happened from last clear of this bit - * 0: power domain did not edurance power cycle since last clear of this bit - * 1: power domain enduranced power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) -#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) -#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) -#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup power cycle happened from last clear of this bit - * 0: power domain did not edurance wakeup power cycle since last clear of this bit - * 1: power domain enduranced wakeup power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) - -/* - * LF_DISABLE (RO) - * - * low fanout power switch disable - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) - -/* - * LF_ACK (RO) - * - * low fanout power switch feedback - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) -#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) -#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) - -/* Bitfield definition for register of struct array POWER: LF_WAIT */ -/* - * WAIT (RW) - * - * wait time for low fan out power switch turn on, default value is 255 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: OFF_WAIT */ -/* - * WAIT (RW) - * - * wait time for power switch turn off, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONTROL */ -/* - * FLAG (RW) - * - * flag represents reset happened from last clear of this bit - * 0: domain did not edurance reset cycle since last clear of this bit - * 1: domain enduranced reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) -#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup reset happened from last clear of this bit - * 0: domain did not edurance wakeup reset cycle since last clear of this bit - * 1: domain enduranced wakeup reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) - -/* - * HOLD (RW) - * - * perform reset and hold in reset, until ths bit cleared by software - * 0: reset is released for function - * 1: reset is assert and hold - */ -#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) -#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) -#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) -#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) - -/* - * RESET (RW) - * - * perform reset and release imediately - * 0: reset is released - * 1 reset is asserted and will release automatically - */ -#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) -#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) -#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) -#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONFIG */ -/* - * PRE_WAIT (RW) - * - * wait cycle numbers before assert reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) - -/* - * RSTCLK_NUM (RW) - * - * reset clock number(must be even number) - * 0: 0 cycle - * 1: 0 cycles - * 2: 2 cycles - * 3: 2 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) - -/* - * POST_WAIT (RW) - * - * time guard band for reset release - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: COUNTER */ -/* - * COUNTER (RW) - * - * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) -#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) -#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) -#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) - -/* Bitfield definition for register array: CLOCK_CPU */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) -#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) - -/* - * SUB1_DIV (RW) - * - * ahb bus divider, the bus clock is generated by cpu_clock/div - * 0: divider by 1 - * 1: divider by 2 - * … - */ -#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL) -#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U) -#define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) -#define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) - -/* - * SUB0_DIV (RW) - * - * axi bus divider, the bus clock is generated by cpu_clock/div - * 0: divider by 1 - * 1: divider by 2 - * … - */ -#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll0_clk2 - * 4:pll1_clk0 - * 5:pll1_clk1 - * 6:pll2_clk0 - * 7:pll2_clk1 - */ -#define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U) -#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) -#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) -#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) - -/* Bitfield definition for register array: CLOCK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) -#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll0_clk2 - * 4:pll1_clk0 - * 5:pll1_clk1 - * 6:pll2_clk0 - * 7:pll2_clk1 - */ -#define SYSCTL_CLOCK_MUX_MASK (0x700U) -#define SYSCTL_CLOCK_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) -#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) -#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) - -/* Bitfield definition for register array: ADCCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) -#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ana clock N - * 1: ahb clock - */ -#define SYSCTL_ADCCLK_MUX_MASK (0x100U) -#define SYSCTL_ADCCLK_MUX_SHIFT (8U) -#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) -#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) - -/* Bitfield definition for register array: DACCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) -#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ana clock N - * 1: ahb clock - */ -#define SYSCTL_DACCLK_MUX_MASK (0x100U) -#define SYSCTL_DACCLK_MUX_SHIFT (8U) -#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) -#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) - -/* Bitfield definition for register: GLOBAL00 */ -/* - * MUX (RW) - * - * global clock override request - * bit0: override to preset0 - * bit1: override to preset1 - * bit2: override to preset2 - * bit3: override to preset3 - */ -#define SYSCTL_GLOBAL00_MUX_MASK (0xFU) -#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) -#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) -#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * VALID (RW) - * - * result is ready for read - * 0: not ready - * 1: result is ready - */ -#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) -#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) -#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) -#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) - -/* - * DIV_BUSY (RO) - * - * divider is applying new setting - */ -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) - -/* - * OUTEN (RW) - * - * enable clock output - */ -#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) -#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) - -/* - * DIV (RW) - * - * output divider - */ -#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) -#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) -#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) - -/* - * HIGH (RW) - * - * clock frequency higher than upper limit - */ -#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) -#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock frequency lower than lower limit - */ -#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) -#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) -#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) -#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) - -/* - * START (RW) - * - * start measurement - */ -#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) -#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) -#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) -#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) - -/* - * MODE (RW) - * - * work mode, - * 0: register value will be compared to measurement - * 1: upper and lower value will be recordered in register - */ -#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) -#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) -#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) -#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) - -/* - * ACCURACY (RW) - * - * measurement accuracy, - * 0: resolution is 1kHz - * 1: resolution is 1Hz - */ -#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) - -/* - * REFERENCE (RW) - * - * reference clock selection, - * 0: 32k - * 1: 24M - */ -#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) - -/* - * SELECTION (RW) - * - * clock measurement selection - * 0: clk_32k - * 1: clk_irc24m - * 2: clk_xtal_24m - * 3: clk_usb0_phy - * 8: clk0_osc0 - * 9: clk0_pll0 - * 10: clk1_pll0 - * 11: clk2_pll0 - * 12: clk0_pll1 - * 13: clk1_pll1 - * 14: clk0_pll2 - * 15: clk1_pll2 - * 128: clk_top_cpu0 - * 129: clk_top_mct0 - * 130: clk_top_mct1 - * 131: clk_top_xpi0 - * 132: clk_top_tmr0 - * 133: clk_top_tmr1 - * 134: clk_top_tmr2 - * 135: clk_top_tmr3 - * 136: clk_top_urt0 - * 137: clk_top_urt1 - * 138: clk_top_urt2 - * 139: clk_top_urt3 - * 140: clk_top_urt4 - * 141: clk_top_urt5 - * 142: clk_top_urt6 - * 143: clk_top_urt7 - * 144: clk_top_i2c0 - * 145: clk_top_i2c1 - * 146: clk_top_i2c2 - * 147: clk_top_i2c3 - * 148: clk_top_spi0 - * 149: clk_top_spi1 - * 150: clk_top_spi2 - * 151: clk_top_spi3 - * 152: clk_top_can0 - * 153: clk_top_can1 - * 154: clk_top_can2 - * 155: clk_top_can3 - * 156: clk_top_ptpc - * 157: clk_top_ana0 - * 158: clk_top_ana1 - * 159: clk_top_ana2 - * 160: clk_top_ana3 - * 161: clk_top_ana4 - * 162: clk_top_ref0 - * 163: clk_top_ref1 - * 164: clk_top_lin0 - * 165: clk_top_lin1 - * 166: clk_top_lin2 - * 167: clk_top_lin3 - */ -#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) -#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CURRENT */ -/* - * FREQUENCY (RO) - * - * self updating measure result - */ -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ -/* - * FREQUENCY (RW) - * - * lower frequency - */ -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ -/* - * FREQUENCY (RW) - * - * upper frequency - */ -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array CPU: LP */ -/* - * WAKE_CNT (RW) - * - * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - */ -#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) -#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) -#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) -#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) - -/* - * HALT (RW) - * - * halt request for CPU0, - * 0: CPU0 will start to execute after reset or receive wakeup request - * 1: CPU0 will not start after reset, or wakeup after WFI - */ -#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) -#define SYSCTL_CPU_LP_HALT_SHIFT (16U) -#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) -#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) - -/* - * WAKE (RO) - * - * CPU0 is waking up - * 0: CPU0 wake up not asserted - * 1: CPU0 wake up asserted - */ -#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) -#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) -#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) - -/* - * EXEC (RO) - * - * CPU0 is executing - * 0: CPU0 is not executing - * 1: CPU0 is executing - */ -#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) -#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) -#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) - -/* - * WAKE_FLAG (RW) - * - * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit - * 0: CPU0 wakeup not happened - * 1: CPU0 wake up happened - */ -#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) -#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) - -/* - * SLEEP_FLAG (RW) - * - * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) -#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) - -/* - * RESET_FLAG (RW) - * - * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit - * 0: CPU0 reset not happened - * 1: CPU0 reset happened - */ -#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) -#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) -#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) -#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) - -/* - * MODE (RW) - * - * Low power mode, system behavior after WFI - * 00: CPU clock stop after WFI - * 01: System enter low power mode after WFI - * 10: Keep running after WFI - * 11: reserved - */ -#define SYSCTL_CPU_LP_MODE_MASK (0x3U) -#define SYSCTL_CPU_LP_MODE_SHIFT (0U) -#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) -#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) - -/* Bitfield definition for register of struct array CPU: LOCK */ -/* - * GPR (RW) - * - * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - */ -#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) -#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) -#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) -#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) - -/* - * LOCK (RW) - * - * Lock bit for CPU_LOCK - */ -#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) -#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) -#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) -#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register of struct array CPU: GPR0 */ -/* - * GPR (RW) - * - * register for software to handle resume, can save resume address or status - */ -#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) -#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) -#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) - -/* Bitfield definition for register of struct array CPU: STATUS0 */ -/* - * STATUS (RO) - * - * IRQ values - */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register of struct array CPU: ENABLE0 */ -/* - * ENABLE (RW) - * - * IRQ wakeup enable - */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) - - - -/* RESOURCE register group index macro definition */ -#define SYSCTL_RESOURCE_CPU0 (0UL) -#define SYSCTL_RESOURCE_CPX0 (1UL) -#define SYSCTL_RESOURCE_CPU1 (8UL) -#define SYSCTL_RESOURCE_CPX1 (9UL) -#define SYSCTL_RESOURCE_POW_CPU0 (21UL) -#define SYSCTL_RESOURCE_POW_CPU1 (22UL) -#define SYSCTL_RESOURCE_RST_SOC (23UL) -#define SYSCTL_RESOURCE_RST_CPU0 (24UL) -#define SYSCTL_RESOURCE_RST_CPU1 (25UL) -#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT1 (66UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (68UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (69UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (70UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (71UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT0 (72UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT1 (73UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT2 (74UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT3 (75UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT4 (76UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT5 (77UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT6 (78UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT7 (79UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (80UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (81UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (82UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (83UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (84UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (85UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (86UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (87UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (88UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (89UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (90UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (91UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTPC (92UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (93UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (94UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (95UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (96UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA4 (97UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF0 (98UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF1 (99UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN0 (100UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN1 (101UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN2 (102UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN3 (103UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL) -#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL) -#define SYSCTL_RESOURCE_CLK_TOP_DAC1 (132UL) -#define SYSCTL_RESOURCE_AHBP (256UL) -#define SYSCTL_RESOURCE_AXIS (257UL) -#define SYSCTL_RESOURCE_AXIC (258UL) -#define SYSCTL_RESOURCE_LMM0 (259UL) -#define SYSCTL_RESOURCE_MCT0 (260UL) -#define SYSCTL_RESOURCE_LMM1 (261UL) -#define SYSCTL_RESOURCE_MCT1 (262UL) -#define SYSCTL_RESOURCE_ROM0 (263UL) -#define SYSCTL_RESOURCE_RAM0 (264UL) -#define SYSCTL_RESOURCE_I2C0 (265UL) -#define SYSCTL_RESOURCE_I2C1 (266UL) -#define SYSCTL_RESOURCE_I2C2 (267UL) -#define SYSCTL_RESOURCE_I2C3 (268UL) -#define SYSCTL_RESOURCE_TMR0 (269UL) -#define SYSCTL_RESOURCE_TMR1 (270UL) -#define SYSCTL_RESOURCE_TMR2 (271UL) -#define SYSCTL_RESOURCE_TMR3 (272UL) -#define SYSCTL_RESOURCE_GPIO (273UL) -#define SYSCTL_RESOURCE_ADC0 (274UL) -#define SYSCTL_RESOURCE_ADC1 (275UL) -#define SYSCTL_RESOURCE_ADC2 (276UL) -#define SYSCTL_RESOURCE_DAC0 (277UL) -#define SYSCTL_RESOURCE_DAC1 (278UL) -#define SYSCTL_RESOURCE_ACMP (279UL) -#define SYSCTL_RESOURCE_SPI0 (280UL) -#define SYSCTL_RESOURCE_SPI1 (281UL) -#define SYSCTL_RESOURCE_SPI2 (282UL) -#define SYSCTL_RESOURCE_SPI3 (283UL) -#define SYSCTL_RESOURCE_SDM0 (284UL) -#define SYSCTL_RESOURCE_URT0 (285UL) -#define SYSCTL_RESOURCE_URT1 (286UL) -#define SYSCTL_RESOURCE_URT2 (287UL) -#define SYSCTL_RESOURCE_URT3 (288UL) -#define SYSCTL_RESOURCE_URT4 (289UL) -#define SYSCTL_RESOURCE_URT5 (290UL) -#define SYSCTL_RESOURCE_URT6 (291UL) -#define SYSCTL_RESOURCE_URT7 (292UL) -#define SYSCTL_RESOURCE_LIN0 (293UL) -#define SYSCTL_RESOURCE_LIN1 (294UL) -#define SYSCTL_RESOURCE_LIN2 (295UL) -#define SYSCTL_RESOURCE_LIN3 (296UL) -#define SYSCTL_RESOURCE_PTPC (297UL) -#define SYSCTL_RESOURCE_CAN0 (298UL) -#define SYSCTL_RESOURCE_CAN1 (299UL) -#define SYSCTL_RESOURCE_CAN2 (300UL) -#define SYSCTL_RESOURCE_CAN3 (301UL) -#define SYSCTL_RESOURCE_WDG0 (302UL) -#define SYSCTL_RESOURCE_WDG1 (303UL) -#define SYSCTL_RESOURCE_MBX0 (304UL) -#define SYSCTL_RESOURCE_MBX1 (305UL) -#define SYSCTL_RESOURCE_CRC0 (306UL) -#define SYSCTL_RESOURCE_MOT0 (307UL) -#define SYSCTL_RESOURCE_MOT1 (308UL) -#define SYSCTL_RESOURCE_MOT2 (309UL) -#define SYSCTL_RESOURCE_MOT3 (310UL) -#define SYSCTL_RESOURCE_SYNT (311UL) -#define SYSCTL_RESOURCE_XPI0 (312UL) -#define SYSCTL_RESOURCE_HDMA (313UL) -#define SYSCTL_RESOURCE_XDMA (314UL) -#define SYSCTL_RESOURCE_KMAN (315UL) -#define SYSCTL_RESOURCE_SDP0 (316UL) -#define SYSCTL_RESOURCE_RNG0 (317UL) -#define SYSCTL_RESOURCE_TSNS (318UL) -#define SYSCTL_RESOURCE_USB0 (319UL) -#define SYSCTL_RESOURCE_REF0 (320UL) -#define SYSCTL_RESOURCE_REF1 (321UL) - -/* GROUP0 register group index macro definition */ -#define SYSCTL_GROUP0_LINK0 (0UL) -#define SYSCTL_GROUP0_LINK1 (1UL) -#define SYSCTL_GROUP0_LINK2 (2UL) - -/* GROUP1 register group index macro definition */ -#define SYSCTL_GROUP1_LINK0 (0UL) -#define SYSCTL_GROUP1_LINK1 (1UL) -#define SYSCTL_GROUP1_LINK2 (2UL) - -/* AFFILIATE register group index macro definition */ -#define SYSCTL_AFFILIATE_CPU0 (0UL) -#define SYSCTL_AFFILIATE_CPU1 (1UL) - -/* RETENTION register group index macro definition */ -#define SYSCTL_RETENTION_CPU0 (0UL) -#define SYSCTL_RETENTION_CPU1 (1UL) - -/* POWER register group index macro definition */ -#define SYSCTL_POWER_CPU0 (0UL) -#define SYSCTL_POWER_CPU1 (1UL) - -/* RESET register group index macro definition */ -#define SYSCTL_RESET_SOC (0UL) -#define SYSCTL_RESET_CPU0 (1UL) -#define SYSCTL_RESET_CPU1 (2UL) - -/* CLOCK_CPU register group index macro definition */ -#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) - -/* CLOCK register group index macro definition */ -#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_MCT1 (1UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR0 (3UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR1 (4UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR2 (5UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR3 (6UL) -#define SYSCTL_CLOCK_CLK_TOP_URT0 (7UL) -#define SYSCTL_CLOCK_CLK_TOP_URT1 (8UL) -#define SYSCTL_CLOCK_CLK_TOP_URT2 (9UL) -#define SYSCTL_CLOCK_CLK_TOP_URT3 (10UL) -#define SYSCTL_CLOCK_CLK_TOP_URT4 (11UL) -#define SYSCTL_CLOCK_CLK_TOP_URT5 (12UL) -#define SYSCTL_CLOCK_CLK_TOP_URT6 (13UL) -#define SYSCTL_CLOCK_CLK_TOP_URT7 (14UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C0 (15UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C1 (16UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C2 (17UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C3 (18UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI0 (19UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI1 (20UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI2 (21UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI3 (22UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN0 (23UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN1 (24UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN2 (25UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN3 (26UL) -#define SYSCTL_CLOCK_CLK_TOP_PTPC (27UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA0 (28UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA1 (29UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA2 (30UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA3 (31UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA4 (32UL) -#define SYSCTL_CLOCK_CLK_TOP_REF0 (33UL) -#define SYSCTL_CLOCK_CLK_TOP_REF1 (34UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN0 (35UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN1 (36UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN2 (37UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN3 (38UL) - -/* ADCCLK register group index macro definition */ -#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) - -/* DACCLK register group index macro definition */ -#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) -#define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL) - -/* MONITOR register group index macro definition */ -#define SYSCTL_MONITOR_SLICE0 (0UL) -#define SYSCTL_MONITOR_SLICE1 (1UL) -#define SYSCTL_MONITOR_SLICE2 (2UL) -#define SYSCTL_MONITOR_SLICE3 (3UL) - -/* GPR register group index macro definition */ -#define SYSCTL_CPU_GPR_GPR0 (0UL) -#define SYSCTL_CPU_GPR_GPR1 (1UL) -#define SYSCTL_CPU_GPR_GPR2 (2UL) -#define SYSCTL_CPU_GPR_GPR3 (3UL) -#define SYSCTL_CPU_GPR_GPR4 (4UL) -#define SYSCTL_CPU_GPR_GPR5 (5UL) -#define SYSCTL_CPU_GPR_GPR6 (6UL) -#define SYSCTL_CPU_GPR_GPR7 (7UL) -#define SYSCTL_CPU_GPR_GPR8 (8UL) -#define SYSCTL_CPU_GPR_GPR9 (9UL) -#define SYSCTL_CPU_GPR_GPR10 (10UL) -#define SYSCTL_CPU_GPR_GPR11 (11UL) -#define SYSCTL_CPU_GPR_GPR12 (12UL) -#define SYSCTL_CPU_GPR_GPR13 (13UL) - -/* WAKEUP_STATUS register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) - -/* WAKEUP_ENABLE register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) - -/* CPU register group index macro definition */ -#define SYSCTL_CPU_CPU0 (0UL) -#define SYSCTL_CPU_CPU1 (1UL) - - -#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_tamp_regs.h deleted file mode 100644 index 77a04f69e05..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_tamp_regs.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TAMP_H -#define HPM_TAMP_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Tamper n control */ - __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */ - __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - } TAMP[4]; - __R uint8_t RESERVED0[64]; /* 0x40 - 0x7F: Reserved */ - __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */ - __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */ -} TAMP_Type; - - -/* Bitfield definition for register of struct array TAMP: CONTROL */ -/* - * LOCK (RW) - * - * lock tamper setting - * 0: tamper setting can be changed - * 1: tamper setting will last to next battery domain power cycle - */ -#define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL) -#define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U) -#define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK) -#define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT) - -/* - * BYPASS (RW) - * - * bypass tamper violation filter - * 0: filter applied - * 1: filter not used - */ -#define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL) -#define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U) -#define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK) -#define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT) - -/* - * FILTER (RW) - * - * filter length - * 0: 1 cycle - * 1: 2 cycle - * 15: 65526 cycle - */ -#define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL) -#define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U) -#define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK) -#define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT) - -/* - * VALUE (RW) - * - * pin value for passive tamper - */ -#define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U) -#define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U) -#define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK) -#define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT) - -/* - * SPEED (RW) - * - * tamper speed selection, (2^SPEED) changes per second - * 0: 1 shift per second - * 1: 2 shifts per second - * . . . - * 15: 32768 shifts per second - */ -#define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U) -#define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U) -#define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK) -#define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT) - -/* - * RECOVER (RW) - * - * tamper will recover itself if tamper LFSR goes wrong - * 0: tamper will not recover - * 1: tamper will recover - */ -#define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U) -#define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U) -#define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK) -#define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT) - -/* - * ACTIVE (RW) - * - * select active or passive tamper - * 0: passive tamper - * 1: active tamper - */ -#define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U) -#define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U) -#define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK) -#define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable tamper - * 0: tamper disableed - * 1: tamper enabled - */ -#define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U) -#define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U) -#define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK) -#define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array TAMP: POLY */ -/* - * POLY (RW) - * - * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - */ -#define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_POLY_POLY_SHIFT (0U) -#define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK) -#define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array TAMP: LFSR */ -/* - * LFSR (WO) - * - * LFSR for active tamper, write only register, always read 0 - */ -#define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_LFSR_LFSR_SHIFT (0U) -#define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK) -#define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT) - -/* Bitfield definition for register: TAMP_FLAG */ -/* - * FLAG (RW) - * - * tamper flag, each bit represents one tamper pin, write 1 to clear the flag - * Note, clear can only be cleared when tamper disappeared - */ -#define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU) -#define TAMP_TAMP_FLAG_FLAG_SHIFT (0U) -#define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK) -#define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * LOCK (RW) - * - * lock bit for IRQ enable - * 0: enable bits can be changed - * 1: enable bits hold until next battery domain power cycle - */ -#define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL) -#define TAMP_IRQ_EN_LOCK_SHIFT (31U) -#define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK) -#define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable, each bit represents one tamper pin - * 0: interrupt disabled - * 1: interrupt enabled - */ -#define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU) -#define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U) -#define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK) -#define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT) - - - -/* TAMP register group index macro definition */ -#define TAMP_TAMP_TAMP0 (0UL) -#define TAMP_TAMP_TAMP1 (1UL) -#define TAMP_TAMP_TAMP2 (2UL) -#define TAMP_TAMP_TAMP3 (3UL) - - -#endif /* HPM_TAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_trgm_regs.h deleted file mode 100644 index a3796d28c9d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_trgm_regs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGM_H -#define HPM_TRGM_H - -typedef struct { - __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ - __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ - __RW uint32_t TRGOCFG[68]; /* 0x100 - 0x20C: Trigger manager output configure register */ - __R uint8_t RESERVED1[240]; /* 0x210 - 0x2FF: Reserved */ - __RW uint32_t DMACFG[4]; /* 0x300 - 0x30C: DMA request configure register */ - __R uint8_t RESERVED2[240]; /* 0x310 - 0x3FF: Reserved */ - __RW uint32_t GCR; /* 0x400: General Control Register */ -} TRGM_Type; - - -/* Bitfield definition for register array: FILTCFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) -#define TRGM_FILTCFG_OUTINV_SHIFT (16U) -#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) -#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stalbe low mode; - * 111-stable high mode - */ -#define TRGM_FILTCFG_MODE_MASK (0xE000U) -#define TRGM_FILTCFG_MODE_SHIFT (13U) -#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) -#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) -#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) -#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) -#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) - -/* - * FILTLEN (RW) - * - * This bitfields defines the filter counter length. - */ -#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) -#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) -#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) -#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) - -/* Bitfield definition for register array: TRGOCFG */ -/* - * OUTINV (RW) - * - * 1- Invert the output - */ -#define TRGM_TRGOCFG_OUTINV_MASK (0x200U) -#define TRGM_TRGOCFG_OUTINV_SHIFT (9U) -#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) -#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) - -/* - * FEDG2PEN (RW) - * - * 1- The selected input signal falling edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x100U) -#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (8U) -#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) -#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) - -/* - * REDG2PEN (RW) - * - * 1- The selected input signal rising edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_REDG2PEN_MASK (0x80U) -#define TRGM_TRGOCFG_REDG2PEN_SHIFT (7U) -#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) -#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) - -/* - * TRIGOSEL (RW) - * - * This bitfield selects one of the TRGM inputs as output. - */ -#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x7FU) -#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) -#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) -#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) - -/* Bitfield definition for register array: DMACFG */ -/* - * DMASRCSEL (RW) - * - * This field selects one of the DMA requests as the DMA request output. - */ -#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) -#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) -#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) -#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * TRGOPEN (RW) - * - * The bitfield enable the TRGM outputs. - */ -#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) -#define TRGM_GCR_TRGOPEN_SHIFT (0U) -#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) -#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) - - - -/* FILTCFG register group index macro definition */ -#define TRGM_FILTCFG_PWM_IN0 (0UL) -#define TRGM_FILTCFG_PWM_IN1 (1UL) -#define TRGM_FILTCFG_PWM_IN2 (2UL) -#define TRGM_FILTCFG_PWM_IN3 (3UL) -#define TRGM_FILTCFG_PWM_IN4 (4UL) -#define TRGM_FILTCFG_PWM_IN5 (5UL) -#define TRGM_FILTCFG_PWM_IN6 (6UL) -#define TRGM_FILTCFG_PWM_IN7 (7UL) -#define TRGM_FILTCFG_TRGM_IN0 (8UL) -#define TRGM_FILTCFG_TRGM_IN1 (9UL) -#define TRGM_FILTCFG_TRGM_IN2 (10UL) -#define TRGM_FILTCFG_TRGM_IN3 (11UL) -#define TRGM_FILTCFG_TRGM_IN4 (12UL) -#define TRGM_FILTCFG_TRGM_IN5 (13UL) -#define TRGM_FILTCFG_TRGM_IN6 (14UL) -#define TRGM_FILTCFG_TRGM_IN7 (15UL) -#define TRGM_FILTCFG_TRGM_IN8 (16UL) -#define TRGM_FILTCFG_TRGM_IN9 (17UL) -#define TRGM_FILTCFG_TRGM_IN10 (18UL) -#define TRGM_FILTCFG_TRGM_IN11 (19UL) - -/* TRGOCFG register group index macro definition */ -#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) -#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) -#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) -#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) -#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) -#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) -#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) -#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) -#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) -#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) -#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) -#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) -#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) -#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) -#define TRGM_TRGOCFG_PWM_SYNCI (14UL) -#define TRGM_TRGOCFG_PWM_FRCI (15UL) -#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) -#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) -#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) -#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) -#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) -#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) -#define TRGM_TRGOCFG_PWM_IN8 (22UL) -#define TRGM_TRGOCFG_PWM_IN9 (23UL) -#define TRGM_TRGOCFG_PWM_IN10 (24UL) -#define TRGM_TRGOCFG_PWM_IN11 (25UL) -#define TRGM_TRGOCFG_PWM_IN12 (26UL) -#define TRGM_TRGOCFG_PWM_IN13 (27UL) -#define TRGM_TRGOCFG_PWM_IN14 (28UL) -#define TRGM_TRGOCFG_PWM_IN15 (29UL) -#define TRGM_TRGOCFG_PLA_IN0 (30UL) -#define TRGM_TRGOCFG_PLA_IN1 (31UL) -#define TRGM_TRGOCFG_PLA_IN2 (32UL) -#define TRGM_TRGOCFG_PLA_IN3 (33UL) -#define TRGM_TRGOCFG_PLA_IN4 (34UL) -#define TRGM_TRGOCFG_PLA_IN5 (35UL) -#define TRGM_TRGOCFG_PLA_IN6 (36UL) -#define TRGM_TRGOCFG_PLA_IN7 (37UL) -#define TRGM_TRGOCFG_QEI_A (38UL) -#define TRGM_TRGOCFG_QEI_B (39UL) -#define TRGM_TRGOCFG_QEI_Z (40UL) -#define TRGM_TRGOCFG_QEI_H (41UL) -#define TRGM_TRGOCFG_QEI_PAUSE (42UL) -#define TRGM_TRGOCFG_QEI_SNAPI (43UL) -#define TRGM_TRGOCFG_HALL_U (44UL) -#define TRGM_TRGOCFG_HALL_V (45UL) -#define TRGM_TRGOCFG_HALL_W (46UL) -#define TRGM_TRGOCFG_HALL_SNAPI (47UL) -#define TRGM_TRGOCFG_ADC0_STRGI (48UL) -#define TRGM_TRGOCFG_ADC1_STRGI (49UL) -#define TRGM_TRGOCFG_ADC2_STRGI (50UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) -#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) -#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) -#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) -#define TRGM_TRGOCFG_DAC_BUF_TRIG (58UL) -#define TRGM_TRGOCFG_DAC0_STEP_TRIG (59UL) -#define TRGM_TRGOCFG_DAC1_STEP_TRIG (60UL) -#define TRGM_TRGOCFG_CMPX_WIN (61UL) -#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) -#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) -#define TRGM_TRGOCFG_SDFM_EVT0 (64UL) -#define TRGM_TRGOCFG_SDFM_EVT1 (65UL) -#define TRGM_TRGOCFG_SDFM_EVT2 (66UL) -#define TRGM_TRGOCFG_SDFM_EVT3 (67UL) - -/* DMACFG register group index macro definition */ -#define TRGM_DMACFG_0 (0UL) -#define TRGM_DMACFG_1 (1UL) -#define TRGM_DMACFG_2 (2UL) -#define TRGM_DMACFG_3 (3UL) - - -#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_tsns_regs.h deleted file mode 100644 index fcaf224c309..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_tsns_regs.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSNS_H -#define HPM_TSNS_H - -typedef struct { - __R uint32_t T; /* 0x0: Temperature */ - __R uint32_t TMAX; /* 0x4: Maximum Temperature */ - __R uint32_t TMIN; /* 0x8: Minimum Temperature */ - __R uint32_t AGE; /* 0xC: Sample age */ - __RW uint32_t STATUS; /* 0x10: Status */ - __RW uint32_t CONFIG; /* 0x14: Configuration */ - __RW uint32_t VALIDITY; /* 0x18: Sample validity */ - __RW uint32_t FLAG; /* 0x1C: Temperature flag */ - __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ - __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ - __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ - __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ - __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __RW uint32_t ADVAN; /* 0x38: Advance configuration */ -} TSNS_Type; - - -/* Bitfield definition for register: T */ -/* - * T (RO) - * - * Signed number of temperature in 256 x celsius degree - */ -#define TSNS_T_T_MASK (0xFFFFFFFFUL) -#define TSNS_T_T_SHIFT (0U) -#define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) - -/* Bitfield definition for register: TMAX */ -/* - * T (RO) - * - * maximum temperature ever found - */ -#define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMAX_T_SHIFT (0U) -#define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) - -/* Bitfield definition for register: TMIN */ -/* - * T (RO) - * - * minimum temperature ever found - */ -#define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMIN_T_SHIFT (0U) -#define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) - -/* Bitfield definition for register: AGE */ -/* - * AGE (RO) - * - * age of T register in 24MHz clock cycles - */ -#define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) -#define TSNS_AGE_AGE_SHIFT (0U) -#define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * VALID (RO) - * - * indicate value in T is valid or not - * 0: not valid - * 1:valid - */ -#define TSNS_STATUS_VALID_MASK (0x80000000UL) -#define TSNS_STATUS_VALID_SHIFT (31U) -#define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) - -/* - * TRIGGER (W1C) - * - * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - */ -#define TSNS_STATUS_TRIGGER_MASK (0x1U) -#define TSNS_STATUS_TRIGGER_SHIFT (0U) -#define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) -#define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * IRQ_EN (RW) - * - * Enable interrupt - */ -#define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) -#define TSNS_CONFIG_IRQ_EN_SHIFT (31U) -#define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) -#define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) - -/* - * RST_EN (RW) - * - * Enable reset - */ -#define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) -#define TSNS_CONFIG_RST_EN_SHIFT (30U) -#define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) -#define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) - -/* - * COMPARE_MIN_EN (RW) - * - * Enable compare for minimum temperature - */ -#define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) -#define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) -#define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) -#define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) - -/* - * COMPARE_MAX_EN (RW) - * - * Enable compare for maximum temperature - */ -#define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) -#define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) -#define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) -#define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) - -/* - * SPEED (RW) - * - * cycles of a progressive step in 24M clock, valid from 24-255, default 96 - * 24: 24 cycle for a step - * 25: 25 cycle for a step - * 26: 26 cycle for a step - * ... - * 255: 255 cycle for a step - */ -#define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) -#define TSNS_CONFIG_SPEED_SHIFT (16U) -#define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) -#define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) - -/* - * AVERAGE (RW) - * - * Average time, default in 3 - * 0: measure and return - * 1: twice and average - * 2: 4 times and average - * . . . - * 7: 128 times and average - */ -#define TSNS_CONFIG_AVERAGE_MASK (0x700U) -#define TSNS_CONFIG_AVERAGE_SHIFT (8U) -#define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) -#define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) - -/* - * CONTINUOUS (RW) - * - * continuous mode that keep sampling temperature peridically - * 0: trigger mode - * 1: continuous mode - */ -#define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) -#define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) -#define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) -#define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) - -/* - * ASYNC (RW) - * - * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value - * 0: active mode - * 1: Async mode - */ -#define TSNS_CONFIG_ASYNC_MASK (0x2U) -#define TSNS_CONFIG_ASYNC_SHIFT (1U) -#define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) -#define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) - -/* - * ENABLE (RW) - * - * Enable temperature - * 0: disable, temperature sensor is shut down - * 1: enable. Temperature sensor enabled - */ -#define TSNS_CONFIG_ENABLE_MASK (0x1U) -#define TSNS_CONFIG_ENABLE_SHIFT (0U) -#define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) -#define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) - -/* Bitfield definition for register: VALIDITY */ -/* - * VALIDITY (RW) - * - * time for temperature values to expire in 24M clock cycles - */ -#define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) -#define TSNS_VALIDITY_VALIDITY_SHIFT (0U) -#define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) -#define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) - -/* Bitfield definition for register: FLAG */ -/* - * RECORD_MIN_CLR (RW) - * - * Clear minimum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) -#define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) -#define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) -#define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) - -/* - * RECORD_MAX_CLR (RW) - * - * Clear maximum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) -#define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) -#define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) -#define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) - -/* - * UNDER_TEMP (RW) - * - * Clear under temperature status, write 1 to clear - */ -#define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) -#define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) -#define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) -#define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) - -/* - * OVER_TEMP (RW) - * - * Clear over temperature status, write 1 to clear - */ -#define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) -#define TSNS_FLAG_OVER_TEMP_SHIFT (16U) -#define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) -#define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) - -/* - * IRQ (RW) - * - * IRQ flag, write 1 to clear - */ -#define TSNS_FLAG_IRQ_MASK (0x1U) -#define TSNS_FLAG_IRQ_SHIFT (0U) -#define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) -#define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_IRQ */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) -#define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_IRQ */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) -#define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_RST */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_RST_T_SHIFT (0U) -#define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) -#define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_RST */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_RST_T_SHIFT (0U) -#define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) -#define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: ASYNC */ -/* - * ASYNC_TYPE (RW) - * - * Compare hotter than or colder than in asynchoronous mode - * 0: hotter than - * 1: colder than - */ -#define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) -#define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) -#define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) -#define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) - -/* - * POLARITY (RW) - * - * Polarity of internal comparator - */ -#define TSNS_ASYNC_POLARITY_MASK (0x10000UL) -#define TSNS_ASYNC_POLARITY_SHIFT (16U) -#define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) -#define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) - -/* - * VALUE (RW) - * - * Value of async mode to compare - */ -#define TSNS_ASYNC_VALUE_MASK (0x7FFU) -#define TSNS_ASYNC_VALUE_SHIFT (0U) -#define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) -#define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) - -/* Bitfield definition for register: ADVAN */ -/* - * ASYNC_IRQ (RO) - * - * interrupt status of asynchronous mode - */ -#define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) -#define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) -#define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) - -/* - * ACTIVE_IRQ (RO) - * - * interrupt status of active mode - */ -#define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) -#define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) -#define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) - -/* - * SAMPLING (RO) - * - * temperature sampling is working - */ -#define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) -#define TSNS_ADVAN_SAMPLING_SHIFT (16U) -#define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) - -/* - * NEG_ONLY (RW) - * - * use negative compare polarity only - */ -#define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) -#define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) -#define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) -#define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) - -/* - * POS_ONLY (RW) - * - * use positive compare polarity only - */ -#define TSNS_ADVAN_POS_ONLY_MASK (0x1U) -#define TSNS_ADVAN_POS_ONLY_SHIFT (0U) -#define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) -#define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) - - - - -#endif /* HPM_TSNS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_uart_regs.h deleted file mode 100644 index 939891f4f31..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_uart_regs.h +++ /dev/null @@ -1,590 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_UART_H -#define HPM_UART_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t IDLE_CFG; /* 0x4: Idle Configuration Register */ - __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ - union { - __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ - __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ - __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ - __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ - __W uint32_t FCR; /* 0x28: FIFO Control Register */ - }; - __RW uint32_t LCR; /* 0x2C: Line Control Register */ - __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ - __R uint32_t LSR; /* 0x34: Line Status Register */ - __R uint32_t MSR; /* 0x38: Modem Status Register */ - __RW uint32_t GPR; /* 0x3C: GPR Register */ -} UART_Type; - - -/* Bitfield definition for register: IDLE_CFG */ -/* - * RX_IDLE_COND (RW) - * - * IDLE Detection Condition - * 0 - Treat as idle if RX pin is logic one - * 1 - Treat as idle if UART state machine state is idle - */ -#define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x200U) -#define UART_IDLE_CFG_RX_IDLE_COND_SHIFT (9U) -#define UART_IDLE_CFG_RX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_COND_SHIFT) & UART_IDLE_CFG_RX_IDLE_COND_MASK) -#define UART_IDLE_CFG_RX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_COND_MASK) >> UART_IDLE_CFG_RX_IDLE_COND_SHIFT) - -/* - * RX_IDLE_EN (RW) - * - * UART Idle Detect Enable - * 0 - Disable - * 1 - Enable - * it should be enabled if enable address match feature - */ -#define UART_IDLE_CFG_RX_IDLE_EN_MASK (0x100U) -#define UART_IDLE_CFG_RX_IDLE_EN_SHIFT (8U) -#define UART_IDLE_CFG_RX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_EN_SHIFT) & UART_IDLE_CFG_RX_IDLE_EN_MASK) -#define UART_IDLE_CFG_RX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_EN_MASK) >> UART_IDLE_CFG_RX_IDLE_EN_SHIFT) - -/* - * RX_IDLE_THR (RW) - * - * Threshold for UART Receive Idle detection (in terms of bits) - */ -#define UART_IDLE_CFG_RX_IDLE_THR_MASK (0xFFU) -#define UART_IDLE_CFG_RX_IDLE_THR_SHIFT (0U) -#define UART_IDLE_CFG_RX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_THR_SHIFT) & UART_IDLE_CFG_RX_IDLE_THR_MASK) -#define UART_IDLE_CFG_RX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_THR_MASK) >> UART_IDLE_CFG_RX_IDLE_THR_SHIFT) - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * The depth of RXFIFO and TXFIFO - * 0: 16-byte FIFO - * 1: 32-byte FIFO - * 2: 64-byte FIFO - * 3: 128-byte FIFO - */ -#define UART_CFG_FIFOSIZE_MASK (0x3U) -#define UART_CFG_FIFOSIZE_SHIFT (0U) -#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: OSCR */ -/* - * OSC (RW) - * - * Over-sample control - * The value must be an even number; any odd value - * writes to this field will be converted to an even value. - * OSC=0: reserved - * OSC<=8: The over-sample ratio is 8 - * 8 < OSC< 32: The over sample ratio is OSC - */ -#define UART_OSCR_OSC_MASK (0x1FU) -#define UART_OSCR_OSC_SHIFT (0U) -#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) -#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RBR (RO) - * - * Receive data read port - */ -#define UART_RBR_RBR_MASK (0xFFU) -#define UART_RBR_RBR_SHIFT (0U) -#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) - -/* Bitfield definition for register: THR */ -/* - * THR (WO) - * - * Transmit data write port - */ -#define UART_THR_THR_MASK (0xFFU) -#define UART_THR_THR_SHIFT (0U) -#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) -#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) - -/* Bitfield definition for register: DLL */ -/* - * DLL (RW) - * - * Least significant byte of the Divisor Latch - */ -#define UART_DLL_DLL_MASK (0xFFU) -#define UART_DLL_DLL_SHIFT (0U) -#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) -#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) - -/* Bitfield definition for register: IER */ -/* - * ERXIDLE (RW) - * - * Enable Receive Idle interrupt - * 0 - Disable Idle interrupt - * 1 - Enable Idle interrupt - */ -#define UART_IER_ERXIDLE_MASK (0x80000000UL) -#define UART_IER_ERXIDLE_SHIFT (31U) -#define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) -#define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) - -/* - * EMSI (RW) - * - * Enable modem status interrupt - * The interrupt asserts when the status of one of the - * following occurs: - * The status of modem_rin, modem_dcdn, - * modem_dsrn or modem_ctsn (If the auto-cts mode is - * disabled) has been changed. - * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), - * modem_ctsn would be used to control the transmitter. - */ -#define UART_IER_EMSI_MASK (0x8U) -#define UART_IER_EMSI_SHIFT (3U) -#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) -#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) - -/* - * ELSI (RW) - * - * Enable receiver line status interrupt - */ -#define UART_IER_ELSI_MASK (0x4U) -#define UART_IER_ELSI_SHIFT (2U) -#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) -#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) - -/* - * ETHEI (RW) - * - * Enable transmitter holding register interrupt - */ -#define UART_IER_ETHEI_MASK (0x2U) -#define UART_IER_ETHEI_SHIFT (1U) -#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) -#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) - -/* - * ERBI (RW) - * - * Enable received data available interrupt and the - * character timeout interrupt - * 0: Disable - * 1: Enable - */ -#define UART_IER_ERBI_MASK (0x1U) -#define UART_IER_ERBI_SHIFT (0U) -#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) -#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) - -/* Bitfield definition for register: DLM */ -/* - * DLM (RW) - * - * Most significant byte of the Divisor Latch - */ -#define UART_DLM_DLM_MASK (0xFFU) -#define UART_DLM_DLM_SHIFT (0U) -#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) -#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) - -/* Bitfield definition for register: IIR */ -/* - * RXIDLE_FLAG (W1C) - * - * UART IDLE Flag - * 0 - UART is busy - * 1 - UART is idle - * NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - */ -#define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) -#define UART_IIR_RXIDLE_FLAG_SHIFT (31U) -#define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) -#define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) - -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR_FIFOED_MASK (0xC0U) -#define UART_IIR_FIFOED_SHIFT (6U) -#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR_INTRID_MASK (0xFU) -#define UART_IIR_INTRID_SHIFT (0U) -#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) - -/* Bitfield definition for register: FCR */ -/* - * RFIFOT (WO) - * - * Receiver FIFO trigger level - */ -#define UART_FCR_RFIFOT_MASK (0xC0U) -#define UART_FCR_RFIFOT_SHIFT (6U) -#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) -#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) - -/* - * TFIFOT (WO) - * - * Transmitter FIFO trigger level - */ -#define UART_FCR_TFIFOT_MASK (0x30U) -#define UART_FCR_TFIFOT_SHIFT (4U) -#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) -#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) - -/* - * DMAE (WO) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCR_DMAE_MASK (0x8U) -#define UART_FCR_DMAE_SHIFT (3U) -#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) -#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_TFIFORST_MASK (0x4U) -#define UART_FCR_TFIFORST_SHIFT (2U) -#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) -#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_RFIFORST_MASK (0x2U) -#define UART_FCR_RFIFORST_SHIFT (1U) -#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) -#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) - -/* - * FIFOE (WO) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCR_FIFOE_MASK (0x1U) -#define UART_FCR_FIFOE_SHIFT (0U) -#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) -#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) - -/* Bitfield definition for register: LCR */ -/* - * DLAB (RW) - * - * Divisor latch access bit - */ -#define UART_LCR_DLAB_MASK (0x80U) -#define UART_LCR_DLAB_SHIFT (7U) -#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) -#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) - -/* - * BC (RW) - * - * Break control - */ -#define UART_LCR_BC_MASK (0x40U) -#define UART_LCR_BC_SHIFT (6U) -#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) -#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) - -/* - * SPS (RW) - * - * Stick parity - * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). - * 0: Disable the sticky bit parity. - */ -#define UART_LCR_SPS_MASK (0x20U) -#define UART_LCR_SPS_SHIFT (5U) -#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) -#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) - -/* - * EPS (RW) - * - * Even parity select - * 1: Even parity (an even number of logic-1 is in the data - * and parity bits) - * 0: Old parity. - */ -#define UART_LCR_EPS_MASK (0x10U) -#define UART_LCR_EPS_SHIFT (4U) -#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) -#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) - -/* - * PEN (RW) - * - * Parity enable - * When this bit is set, a parity bit is generated in - * transmitted data before the first STOP bit and the parity - * bit would be checked for the received data. - */ -#define UART_LCR_PEN_MASK (0x8U) -#define UART_LCR_PEN_SHIFT (3U) -#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) -#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) - -/* - * STB (RW) - * - * Number of STOP bits - * 0: 1 bits - * 1: The number of STOP bit is based on the WLS setting - * When WLS = 0, STOP bit is 1.5 bits - * When WLS = 1, 2, 3, STOP bit is 2 bits - */ -#define UART_LCR_STB_MASK (0x4U) -#define UART_LCR_STB_SHIFT (2U) -#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) -#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) - -/* - * WLS (RW) - * - * Word length setting - * 0: 5 bits - * 1: 6 bits - * 2: 7 bits - * 3: 8 bits - */ -#define UART_LCR_WLS_MASK (0x3U) -#define UART_LCR_WLS_SHIFT (0U) -#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) -#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) - -/* Bitfield definition for register: MCR */ -/* - * AFE (RW) - * - * Auto flow control enable - * 0: Disable - * 1: The auto-CTS and auto-RTS setting is based on the - * RTS bit setting: - * When RTS = 0, auto-CTS only - * When RTS = 1, auto-CTS and auto-RTS - */ -#define UART_MCR_AFE_MASK (0x20U) -#define UART_MCR_AFE_SHIFT (5U) -#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) -#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) - -/* - * LOOP (RW) - * - * Enable loopback mode - * 0: Disable - * 1: Enable - */ -#define UART_MCR_LOOP_MASK (0x10U) -#define UART_MCR_LOOP_SHIFT (4U) -#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) -#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) - -/* - * RTS (RW) - * - * Request to send - * This bit controls the modem_rtsn output. - * 0: The modem_rtsn output signal will be driven HIGH - * 1: The modem_rtsn output signal will be driven LOW - */ -#define UART_MCR_RTS_MASK (0x2U) -#define UART_MCR_RTS_SHIFT (1U) -#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) -#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) - -/* Bitfield definition for register: LSR */ -/* - * ERRF (RO) - * - * Error in RXFIFO - * In the FIFO mode, this bit is set when there is at least - * one parity error, framing error, or line break - * associated with data in the RXFIFO. It is cleared when - * this register is read and there is no more error for the - * rest of data in the RXFIFO. - */ -#define UART_LSR_ERRF_MASK (0x80U) -#define UART_LSR_ERRF_SHIFT (7U) -#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) - -/* - * TEMT (RO) - * - * Transmitter empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) and the Transmitter Shift Register (TSR) are - * both empty. Otherwise, it is zero. - */ -#define UART_LSR_TEMT_MASK (0x40U) -#define UART_LSR_TEMT_SHIFT (6U) -#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) - -/* - * THRE (RO) - * - * Transmitter Holding Register empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) is empty. Otherwise, it is zero. - * If the THRE interrupt is enabled, an interrupt is - * triggered when THRE becomes 1. - */ -#define UART_LSR_THRE_MASK (0x20U) -#define UART_LSR_THRE_SHIFT (5U) -#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) - -/* - * LBREAK (RO) - * - * Line break - * This bit is set when the uart_sin input signal was held - * LOWfor longer than the time for a full-word - * transmission. A full-word transmission is the - * transmission of the START, data, parity, and STOP - * bits. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the line break for - * the received data at the top of the RXFIFO. - */ -#define UART_LSR_LBREAK_MASK (0x10U) -#define UART_LSR_LBREAK_SHIFT (4U) -#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) - -/* - * FE (RO) - * - * Framing error - * This bit is set when the received STOP bit is not - * HIGH. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the framing error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_FE_MASK (0x8U) -#define UART_LSR_FE_SHIFT (3U) -#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) - -/* - * PE (RO) - * - * Parity error - * This bit is set when the received parity does not match - * with the parity selected in the LCR[5:4]. It is cleared - * when this register is read. - * In the FIFO mode, this bit indicates the parity error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_PE_MASK (0x4U) -#define UART_LSR_PE_SHIFT (2U) -#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) - -/* - * OE (RO) - * - * Overrun error - * This bit indicates that data in the Receiver Buffer - * Register (RBR) is overrun. - */ -#define UART_LSR_OE_MASK (0x2U) -#define UART_LSR_OE_SHIFT (1U) -#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) - -/* - * DR (RO) - * - * Data ready. - * This bit is set when there are incoming received data - * in the Receiver Buffer Register (RBR). It is cleared - * when all of the received data are read. - */ -#define UART_LSR_DR_MASK (0x1U) -#define UART_LSR_DR_SHIFT (0U) -#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) - -/* Bitfield definition for register: MSR */ -/* - * CTS (RO) - * - * Clear to send - * 0: The modem_ctsn input signal is HIGH. - * 1: The modem_ctsn input signal is LOW. - */ -#define UART_MSR_CTS_MASK (0x10U) -#define UART_MSR_CTS_SHIFT (4U) -#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) - -/* - * DCTS (RC) - * - * Delta clear to send - * This bit is set when the state of the modem_ctsn input - * signal has been changed since the last time this - * register is read. - */ -#define UART_MSR_DCTS_MASK (0x1U) -#define UART_MSR_DCTS_SHIFT (0U) -#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) - -/* Bitfield definition for register: GPR */ -/* - * DATA (RW) - * - * A one-byte storage register - */ -#define UART_GPR_DATA_MASK (0xFFU) -#define UART_GPR_DATA_SHIFT (0U) -#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) -#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) - - - - -#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_usb_regs.h deleted file mode 100644 index ff2a137f826..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_usb_regs.h +++ /dev/null @@ -1,2253 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_USB_H -#define HPM_USB_H - -typedef struct { - __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ - __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ - __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ - __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ - __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ - __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ - __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ - __RW uint32_t USBCMD; /* 0x140: USB Command Register */ - __RW uint32_t USBSTS; /* 0x144: USB Status Register */ - __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ - __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ - __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ - union { - __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ - __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ - }; - union { - __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ - __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ - }; - __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ - __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ - __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ - __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ - __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ - __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ - __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ - __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ - __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ - __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ - __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ - __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ - __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ - __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ - __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ - __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ - __R uint8_t RESERVED7[32]; /* 0x1E0 - 0x1FF: Reserved */ - __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED8[12]; /* 0x204 - 0x20F: Reserved */ - __RW uint32_t PHY_CTRL0; /* 0x210: */ - __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED9[8]; /* 0x218 - 0x21F: Reserved */ - __RW uint32_t TOP_STATUS; /* 0x220: */ - __RW uint32_t PHY_STATUS; /* 0x224: */ -} USB_Type; - - -/* Bitfield definition for register: GPTIMER0LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) -#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER0CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD - */ -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software; - * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the - * counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: GPTIMER1LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) -#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER1CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - */ -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and - * automatically reload the counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: SBUSCFG */ -/* - * AHBBRST (RW) - * - * AHBBRST - * AHB master interface Burst configuration - * These bits control AHB master transfer type sequence (or priority). - * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. - * 000 - Incremental burst of unspecified length only - * 001 - INCR4 burst, then single transfer - * 010 - INCR8 burst, INCR4 burst, then single transfer - * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer - * 100 - Reserved, don't use - * 101 - INCR4 burst, then incremental burst of unspecified length - * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length - * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) -#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) - -/* Bitfield definition for register: USBCMD */ -/* - * ITC (RW) - * - * ITC - * Interrupt Threshold Control -Read/Write. - * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. - * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are - * shown below. - * Value Maximum Interrupt Interval - * 00000000 - Immediate (no threshold) - * 00000001 - 1 micro-frame - * 00000010 - 2 micro-frames - * 00000100 - 4 micro-frames - * 00001000 - 8 micro-frames - * 00010000 - 16 micro-frames - * 00100000 - 32 micro-frames - * 01000000 - 64 micro-frames - */ -#define USB_USBCMD_ITC_MASK (0xFF0000UL) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) -#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) - -/* - * FS_2 (RW) - * - * FS_2 - * Frame List Size - (Read/Write or Read Only). [host mode only] - * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. - * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. - * NOTE: This field is made up from USBCMD bits 15, 3 and 2. - * Value Meaning - * 0b000 - 1024 elements (4096 bytes) Default value - * 0b001 - 512 elements (2048 bytes) - * 0b010 - 256 elements (1024 bytes) - * 0b011 - 128 elements (512 bytes) - * 0b100 - 64 elements (256 bytes) - * 0b101 - 32 elements (128 bytes) - * 0b110 - 16 elements (64 bytes) - * 0b111 - 8 elements (32 bytes) - */ -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) - -/* - * ATDTW (RW) - * - * ATDTW - * Add dTD TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's - * linked list. This bit is set and cleared by software. - * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD - * to a primed endpoint may go unrecognized. - */ -#define USB_USBCMD_ATDTW_MASK (0x4000U) -#define USB_USBCMD_ATDTW_SHIFT (14U) -#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) - -/* - * SUTW (RW) - * - * SUTW - * Setup TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. - * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then - * there is a hazard when new setup data arrives while the DCD is copying the setup data payload - * from the QH for a previous setup packet. This bit is set and cleared by software. - * This bit would also be cleared by hardware when a hazard detected. - */ -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) - -/* - * ASPE (RW) - * - * ASPE - * Asynchronous Schedule Park Mode Enable - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. - * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. - * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - * NOTE: ASPE bit reset value: '0b' for OTG controller . - */ -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) - -/* - * ASP (RW) - * - * ASP - * Asynchronous Schedule Park Mode Count - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. - * It contains a count of the number of successive transactions the host controller is allowed to - * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. - * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. - * This field is set to 3h in all controller core. - */ -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) - -/* - * IAA (RW) - * - * IAA - * Interrupt on Async Advance Doorbell - Read/Write. - * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. - * When the host controller has evicted all appropriate cached schedule states, - * it sets the Interrupt on Async Advance status bit in the USBSTS register. - * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. - * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. - * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. - * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - */ -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) - -/* - * ASE (RW) - * - * ASE - * Asynchronous Schedule Enable - Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Asynchronous Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Asynchronous Schedule. - * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - */ -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) - -/* - * PSE (RW) - * - * PSE - * Periodic Schedule Enable- Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Periodic Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Periodic Schedule - * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - */ -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) - -/* - * FS_1 (RW) - * - * FS_1 - * See description at bit 15 - */ -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) - -/* - * RST (RW) - * - * RST - * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. - * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. - * Host operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. - * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. - * Attempting to reset an actively running host controller will result in undefined behavior. - * Device operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. - * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - */ -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) - -/* - * RS (RW) - * - * RS - * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. - * Host operation mode: - * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. - * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. - * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. - * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). - * Device operation mode: - * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. - * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. - * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) - -/* Bitfield definition for register: USBSTS */ -/* - * TI1 (RWC) - * - * TI1 - * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. - * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this - * bit will clear it. - */ -#define USB_USBSTS_TI1_MASK (0x2000000UL) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) -#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) - -/* - * TI0 (RWC) - * - * TI0 - * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. - * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this - * bit clears it. - */ -#define USB_USBSTS_TI0_MASK (0x1000000UL) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) - -/* - * UPI (RWC) - * - * USB Host Periodic Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. - * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero. - */ -#define USB_USBSTS_UPI_MASK (0x80000UL) -#define USB_USBSTS_UPI_SHIFT (19U) -#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) -#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) - -/* - * UAI (RWC) - * - * USB Host Asynchronous Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. - * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero - */ -#define USB_USBSTS_UAI_MASK (0x40000UL) -#define USB_USBSTS_UAI_SHIFT (18U) -#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) -#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) - -/* - * NAKI (RO) - * - * NAKI - * NAK Interrupt Bit--RO. - * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and - * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware - * when all Enabled TX/RX Endpoint NAK bits are cleared. - */ -#define USB_USBSTS_NAKI_MASK (0x10000UL) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) - -/* - * AS (RO) - * - * AS - * Asynchronous Schedule Status - Read Only. - * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. - * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) - -/* - * PS (RO) - * - * PS - * Periodic Schedule Status - Read Only. - * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. - * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) - -/* - * RCL (RO) - * - * RCL - * Reclamation - Read Only. - * This is a read-only status bit used to detect an empty asynchronous schedule. - * Only used in the host operation mode. - */ -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) - -/* - * HCH (RO) - * - * HCH - * HCHaIted - Read Only. - * This bit is a zero whenever the Run/Stop bit is a one. - * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - * either by software or by the Controller hardware (for example, an internal error). - * Only used in the host operation mode. - * Default value is '0b' for OTG core . - * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE - * register. - * NOTE: HCH bit reset value: '0b' for OTG controller core . - */ -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) - -/* - * SLI (RWC) - * - * SLI - * DCSuspend - R/WC. - * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. - * Only used in device operation mode. - */ -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) - -/* - * SRI (RWC) - * - * SRI - * SOF Received - R/WC. - * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. - * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. - * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. - * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. - * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. - * Software writes a 1 to this bit to clear it. - */ -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) - -/* - * URI (RWC) - * - * URI - * USB Reset Received - R/WC. - * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. - * Software can write a 1 to this bit to clear the USB Reset Received status bit. - * Only used in device operation mode. - */ -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) - -/* - * AAI (RWC) - * - * AAI - * Interrupt on Async Advance - R/WC. - * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule - * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. - * Only used in host operation mode. - */ -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) - -/* - * SEI (RWC) - * - * System Error – RWC. Default = 0b. - * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. - * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - */ -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) - -/* - * FRI (RWC) - * - * FRI - * Frame List Rollover - R/WC. - * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to - * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the - * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the - * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host - * Controller sets this bit to a one every time FHINDEX [12] toggles. - * Only used in host operation mode. - */ -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) - -/* - * PCI (RWC) - * - * PCI - * Port Change Detect - R/WC. - * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, - * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. - * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. - * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, - * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - */ -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) - -/* - * UEI (RWC) - * - * UEI - * USB Error Interrupt (USBERRINT) - R/WC. - * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. - * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - */ -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) - -/* - * UI (RWC) - * - * UI - * USB Interrupt (USBINT) - R/WC. - * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB - * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. - * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when - * the actual number of bytes received was less than the expected number of bytes. - */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) - -/* Bitfield definition for register: USBINTR */ -/* - * TIE1 (RW) - * - * TIE1 - * General Purpose Timer #1 Interrupt Enable - * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE1_MASK (0x2000000UL) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) -#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) - -/* - * TIE0 (RW) - * - * TIE0 - * General Purpose Timer #0 Interrupt Enable - * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE0_MASK (0x1000000UL) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) - -/* - * UPIE (RW) - * - * UPIE - * USB Host Periodic Interrupt Enable - * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UPIE_MASK (0x80000UL) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) - -/* - * UAIE (RW) - * - * UAIE - * USB Host Asynchronous Interrupt Enable - * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UAIE_MASK (0x40000UL) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) - -/* - * NAKE (RO) - * - * NAKE - * NAK Interrupt Enable - * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_NAKE_MASK (0x10000UL) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) - -/* - * SLE (RW) - * - * SLE - * Sleep Interrupt Enable - * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) - -/* - * SRE (RW) - * - * SRE - * SOF Received Interrupt Enable - * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) - -/* - * URE (RW) - * - * URE - * USB Reset Interrupt Enable - * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) - -/* - * AAE (RW) - * - * AAE - * Async Advance Interrupt Enable - * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) - -/* - * SEE (RW) - * - * SEE - * System Error Interrupt Enable - * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) - -/* - * FRE (RW) - * - * FRE - * Frame List Rollover Interrupt Enable - * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) - -/* - * PCE (RW) - * - * PCE - * Port Change Detect Interrupt Enable - * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) - -/* - * UEE (RWC) - * - * UEE - * USB Error Interrupt Enable - * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) - -/* - * UE (RW) - * - * UE - * USB Interrupt Enable - * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) - -/* Bitfield definition for register: FRINDEX */ -/* - * FRINDEX (RW) - * - * FRINDEX - * Frame Index. - * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. - * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. - * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. - * USBCMD [Frame List Size] Number Elements N - * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. - * In either mode bits 2:0 indicate the current microframe. - * The bit field values description below is represented as (Frame List Size) Number Elements N. - * 00000000000000 - (1024) 12 - * 00000000000001 - (512) 11 - * 00000000000010 - (256) 10 - * 00000000000011 - (128) 9 - * 00000000000100 - (64) 8 - * 00000000000101 - (32) 7 - * 00000000000110 - (16) 6 - * 00000000000111 - (8) 5 - */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) -#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) - -/* Bitfield definition for register: DEVICEADDR */ -/* - * USBADR (RW) - * - * USBADR - * Device Address. - * These bits correspond to the USB device address - */ -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) -#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) - -/* - * USBADRA (RW) - * - * USBADRA - * Device Address Advance. Default=0. - * When this bit is '0', any writes to USBADR are instantaneous. - * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. - * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. - * Hardware will automatically clear this bit on the following conditions: - * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). - * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). - * 3) Device Reset occurs (USBADR is reset to 0). - * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. - * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. - * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), - * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) - -/* Bitfield definition for register: PERIODICLISTBASE */ -/* - * BASEADR (RW) - * - * BASEADR - * Base Address (Low). - * These bits correspond to memory address signals [31:12], respectively. - * Only used by the host controller. - */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) -#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) - -/* Bitfield definition for register: ASYNCLISTADDR */ -/* - * ASYBASE (RW) - * - * ASYBASE - * Link Pointer Low (LPL). - * These bits correspond to memory address signals [31:5], respectively. This field may only reference a - * Queue Head (QH). - * Only used by the host controller. - */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) -#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) - -/* Bitfield definition for register: ENDPTLISTADDR */ -/* - * EPBASE (RW) - * - * EPBASE - * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. - * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) -#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) - -/* Bitfield definition for register: BURSTSIZE */ -/* - * TXPBURST (RW) - * - * TXPBURST - * Programmable TX Burst Size. - * Default value is determined by TXBURST bits in n_HWTXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from system - * memory to the USB bus. - */ -#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) - -/* - * RXPBURST (RW) - * - * RXPBURST - * Programmable RX Burst Size. - * Default value is determined by TXBURST bits in n_HWRXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from the - * USB bus to system memory. - */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) - -/* Bitfield definition for register: TXFILLTUNING */ -/* - * TXFIFOTHRES (RW) - * - * TXFIFOTHRES - * FIFO Burst Threshold. (Read/Write) - * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. - * The minimum value is 2 and this value should be a low as possible to maximize USB performance. - * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth - * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. - * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - */ -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* - * TXSCHHEALTH (RWC) - * - * TXSCHHEALTH - * Scheduler Health Counter. (Read/Write To Clear) - * Table continues on the next page - * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES - * before running out of time to send the packet before the next Start-Of-Frame. - * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. - * Writing to this register will clear the counter and this counter will max. at 31. - */ -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) - -/* - * TXSCHOH (RW) - * - * TXSCHOH - * Scheduler Overhead. (Read/Write) [Default = 0] - * This register adds an additional fixed offset to the schedule time estimator described above as Tff. - * As an approximation, the value chosen for this register should limit the number of back-off events captured - * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. - * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. - * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. - * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. - * Default value is '08h' for OTG controller core . - */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) - -/* Bitfield definition for register: ENDPTNAK */ -/* - * EPTN (RWC) - * - * EPTN - * TX Endpoint NAK - R/WC. - * Each TX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received IN token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) -#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) - -/* - * EPRN (RWC) - * - * EPRN - * RX Endpoint NAK - R/WC. - * Each RX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) - -/* Bitfield definition for register: ENDPTNAKEN */ -/* - * EPTNE (RW) - * - * EPTNE - * TX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the - * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) - -/* - * EPRNE (RW) - * - * EPRNE - * RX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the - * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) - -/* Bitfield definition for register: PORTSC1 */ -/* - * STS (RW) - * - * STS - * Serial Transceiver Select - * 1 Serial Interface Engine is selected - * 0 Parallel Interface signals is selected - * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. - * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - */ -#define USB_PORTSC1_STS_MASK (0x20000000UL) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) - -/* - * PTW (RW) - * - * PTW - * Parallel Transceiver Width - * This bit has no effect if serial interface engine is used. - * 0 - Select the 8-bit UTMI interface [60MHz] - * 1 - Select the 16-bit UTMI interface [30MHz] - */ -#define USB_PORTSC1_PTW_MASK (0x10000000UL) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) - -/* - * PSPD (RO) - * - * PSPD - * Port Speed - Read Only. - * This register field indicates the speed at which the port is operating. - * 00 - Full Speed - * 01 - Low Speed - * 10 - High Speed - * 11 - Undefined - */ -#define USB_PORTSC1_PSPD_MASK (0xC000000UL) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) - -/* - * PFSC (RW) - * - * PFSC - * Port Force Full Speed Connect - Read/Write. Default = 0b. - * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp - * sequence that allows the port to identify itself as High Speed. - * 0 - Normal operation - * 1 - Forced to full speed - */ -#define USB_PORTSC1_PFSC_MASK (0x1000000UL) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) - -/* - * PHCD (RW) - * - * PHCD - * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. - * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY - * clock. - * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. - * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD - * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend - * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the - * device controller driver must clear this bit. - * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put - * into suspend mode or when no downstream device is connected. Low power suspend is completely - * under the control of software. - * 0 - Enable PHY clock - * 1 - Disable PHY clock - */ -#define USB_PORTSC1_PHCD_MASK (0x800000UL) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) - -/* - * WKOC (RW) - * - * WKOC - * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. - * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero. - */ -#define USB_PORTSC1_WKOC_MASK (0x400000UL) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) - -/* - * WKDC (RW) - * - * WKDC - * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables - * the port to be sensitive to device disconnects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKDC_MASK (0x200000UL) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) - -/* - * WKCN (RW) - * - * WKCN - * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. - * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKCN_MASK (0x100000UL) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) - -/* - * PTC (RW) - * - * PTC - * Port Test Control - Read/Write. Default = 0000b. - * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. - * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. - * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. - * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. - * NOTE: Low speed operations are not supported as a peripheral device. - * Any other value than zero indicates that the port is operating in test mode. - * Value Specific Test - * 0000 - TEST_MODE_DISABLE - * 0001 - J_STATE - * 0010 - K_STATE - * 0011 - SE0 (host) / NAK (device) - * 0100 - Packet - * 0101 - FORCE_ENABLE_HS - * 0110 - FORCE_ENABLE_FS - * 0111 - FORCE_ENABLE_LS - * 1000-1111 - Reserved - */ -#define USB_PORTSC1_PTC_MASK (0xF0000UL) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) - -/* - * PP (RW) - * - * PP - * Port Power (PP)-Read/Write or Read Only. - * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: - * PPC - * PP Operation - * 0 - * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. - * 1 - * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). - * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. - * When an over-current condition is detected on a powered port and PPC is a one, - * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). - * This feature is implemented in all controller cores (PPC = 1). - */ -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) - -/* - * LS (RO) - * - * LS - * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal - * lines. - * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because - * the port controller state machine and the port routing manage the connection of LS and FS. - * In device mode, the use of linestate by the device controller driver is not necessary. - * The encoding of the bits are: - * Bits [11:10] Meaning - * 00 - SE0 - * 01 - K-state - * 10 - J-state - * 11 - Undefined - */ -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) - -/* - * HSP (RO) - * - * HSP - * High-Speed Port - Read Only. Default = 0b. - * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the - * host/device connected to the port is not in a high-speed mode. - * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - */ -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) - -/* - * PR (RW) - * - * PR - * Port Reset - Read/Write or Read Only. Default = 0b. - * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. - * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. - * This bit will automatically change to zero after the reset sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. - * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - */ -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) - -/* - * SUSP (RW) - * - * SUSP - * Suspend - Read/Write or Read Only. Default = 0b. - * 1=Port in suspend state. 0=Port not in suspend state. - * In Host Mode: Read/Write. - * Port Enabled Bit and Suspend bit of this register define the port states as follows: - * Bits [Port Enabled, Suspend] Port State - * 0x Disable - * 10 Enable - * 11 Suspend - * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. - * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. - * In the suspend state, the port is sensitive to resume detection. - * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. - * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. - * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: Read Only. - * In device mode this bit is a read only status bit. - */ -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) - -/* - * FPR (RW) - * - * FPR - * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. - * In Host Mode: - * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. - * This bit will automatically change to zero after the resume sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. - * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. - * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. - * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * This bit is not-EHCI compatible. - * In Device mode: - * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. - * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * The bit will be cleared when the device returns to normal operation. - * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - */ -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) - -/* - * OCC (RW) - * - * OCC - * Over-current Change-R/WC. Default=0. - * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - */ -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) - -/* - * OCA (RO) - * - * OCA - * Over-current Active-Read Only. Default 0. - * This bit will automatically transition from one to zero when the over current condition is removed. - * 0 - This port does not have an over-current condition. - * 1 - This port currently has an over-current condition - */ -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) - -/* - * PEC (RWC) - * - * PEC - * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. - * In Host Mode: - * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or - * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). - * Software clears this by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero. - * In Device mode: - * The device port is always enabled, so this bit is always '0b'. - */ -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) - -/* - * PE (RWC) - * - * PE - * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. - * In Host Mode: - * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. - * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. - * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. - * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * The device port is always enabled, so this bit is always '1b'. - */ -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) - -/* - * CSC (RWC) - * - * CSC - * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. - * In Host Mode: - * Indicates a change has occurred in the port's Current Connect Status. - * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. - * For example, the insertion status changes twice before system software has cleared the changed condition, - * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * This bit is undefined in device controller mode. - */ -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) - -/* - * CCS (RWC) - * - * CCS - * Current Connect Status-Read Only. - * In Host Mode: - * 1=Device is present on port. 0=No device is present. Default = 0. - * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * 1=Attached. 0=Not Attached. Default=0. - * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. - * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. - * It does not state the device being disconnected or Suspended. - */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) - -/* Bitfield definition for register: OTGSC */ -/* - * ASVIE (RW) - * - * ASVIE - * A Session Valid Interrupt Enable - Read/Write. - */ -#define USB_OTGSC_ASVIE_MASK (0x4000000UL) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) - -/* - * AVVIE (RW) - * - * AVVIE - * A VBus Valid Interrupt Enable - Read/Write. - * Setting this bit enables the A VBus valid interrupt. - */ -#define USB_OTGSC_AVVIE_MASK (0x2000000UL) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) - -/* - * IDIE (RW) - * - * IDIE - * USB ID Interrupt Enable - Read/Write. - * Setting this bit enables the USB ID interrupt. - */ -#define USB_OTGSC_IDIE_MASK (0x1000000UL) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) - -/* - * ASVIS (RWC) - * - * ASVIS - * A Session Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the A session valid threshold. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_ASVIS_MASK (0x40000UL) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) - -/* - * AVVIS (RWC) - * - * AVVIS - * A VBus Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_AVVIS_MASK (0x20000UL) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) - -/* - * IDIS (RWC) - * - * IDIS - * USB ID Interrupt Status - Read/Write. - * This bit is set when a change on the ID input has been detected. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_IDIS_MASK (0x10000UL) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) - -/* - * ASV (RO) - * - * ASV - * A Session Valid - Read Only. - * Indicates VBus is above the A session valid threshold. - */ -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) - -/* - * AVV (RO) - * - * AVV - * A VBus Valid - Read Only. - * Indicates VBus is above the A VBus valid threshold. - */ -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) - -/* - * ID (RO) - * - * ID - * USB ID - Read Only. - * 0 = A device, 1 = B device - */ -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) - -/* - * IDPU (RW) - * - * IDPU - * ID Pullup - Read/Write - * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input - * will not be sampled. - */ -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) - -/* - * VC (RW) - * - * VC - * VBUS Charge - Read/Write. - * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - */ -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) - -/* - * VD (RW) - * - * VD - * VBUS_Discharge - Read/Write. - * Setting this bit causes VBus to discharge through a resistor. - */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) - -/* Bitfield definition for register: USBMODE */ -/* - * SDIS (RW) - * - * SDIS - * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) - * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. - * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. - * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. - * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems - * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. - * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for - * the scheduler when using this feature. - * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - */ -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) -#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) - -/* - * SLOM (RW) - * - * SLOM - * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . - * 0 - Setup Lockouts On (default); - * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - */ -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) - -/* - * ES (RW) - * - * ES - * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the - * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected - * by the value of this bit because they are based upon the 32-bit word. - * Bit Meaning - * 0 - Little Endian [Default] - * 1 - Big Endian - */ -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) - -/* - * CM (RW) - * - * CM - * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only - * implementations. For those designs that contain both host & device capability, the controller defaults to - * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ - * device controllers, this register can only be written once after reset. If it is necessary to switch modes, - * software must reset the controller by writing to the RESET bit in the USBCMD register before - * reprogramming this register. - * For OTG controller core, reset value is '00b'. - * 00 - Idle [Default for combination host/device] - * 01 - Reserved - * 10 - Device Controller [Default for device only controller] - * 11 - Host Controller [Default for host only controller] - */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) - -/* Bitfield definition for register: ENDPTSETUPSTAT */ -/* - * ENDPTSETUPSTAT (RWC) - * - * ENDPTSETUPSTAT - * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. - * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. - * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. - * This register is only used in device mode. - */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* Bitfield definition for register: ENDPTPRIME */ -/* - * PETB (RWS) - * - * PETB - * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a - * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. - * Software should write a one to the corresponding bit when posting a new transfer descriptor to an - * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor - * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated - * endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) -#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) - -/* - * PERB (RWS) - * - * PERB - * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. - * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. - * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. - * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) - -/* Bitfield definition for register: ENDPTFLUSH */ -/* - * FETB (RWS) - * - * FETB - * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) -#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) - -/* - * FERB (RWS) - * - * FERB - * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) - -/* Bitfield definition for register: ENDPTSTAT */ -/* - * ETBR (RO) - * - * ETBR - * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. - * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. - * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. - * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. - * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. - * ETBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) - -/* - * ERBR (RO) - * - * ERBR - * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective - * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a - * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the - * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB - * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the - * USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations - * when a dTD is retired, and the dQH is updated. - * ERBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) - -/* Bitfield definition for register: ENDPTCOMPLETE */ -/* - * ETCE (RWC) - * - * ETCE - * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. - * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. - * ETCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) - -/* - * ERCE (RWC) - * - * ERCE - * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred - * and software should read the corresponding endpoint queue to determine the transfer status. If the - * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the - * USBINT . Writing one clears the corresponding bit in this register. - * ERCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) - -/* Bitfield definition for register array: ENDPTCTRL */ -/* - * TXE (RW) - * - * TXE - * TX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) -#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) - -/* - * TXR (WS) - * - * TXR - * TX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the Host and device. - */ -#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) - -/* - * TXT (RW) - * - * TXT - * TX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) - -/* - * TXS (RW) - * - * TXS - * TX Endpoint Stall - Read/Write - * 0 End Point OK - * 1 End Point Stalled - * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured - * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. - * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. - * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: - * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - */ -#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) - -/* - * RXE (RW) - * - * RXE - * RX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) - -/* - * RXR (WS) - * - * RXR - * RX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the host and device. - */ -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) - -/* - * RXT (RW) - * - * RXT - * RX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) - -/* - * RXS (RW) - * - * RXS - * RX Endpoint Stall - Read/Write - * 0 End Point OK. [Default] - * 1 End Point Stalled - * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control - * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit - * is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This - * control will continue to STALL until this bit is either cleared by software or automatically cleared as above - * for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the - * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it - * is unlikely the DCD software will observe this delay. However, should the DCD observe that the - * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit - * until it is set or until a new setup has been received by checking the associated endptsetupstat - * Bit. - */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) - -/* Bitfield definition for register: OTG_CTRL0 */ -/* - * OTG_WKDPDMCHG_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) - -/* - * AUTORESUME_EN (RW) - * - */ -#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) -#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) -#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) -#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) - -/* - * OTG_VBUS_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) - -/* - * OTG_ID_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) - -/* - * OTG_VBUS_SOURCE_SEL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) - -/* - * OTG_UTMI_SUSPENDM_SW (RW) - * - * default 0 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) - -/* - * OTG_UTMI_RESET_SW (RW) - * - * default 1 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) - -/* - * OTG_WAKEUP_INT_ENABLE (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) - -/* - * OTG_POWER_MASK (RW) - * - */ -#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) -#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) - -/* - * OTG_OVER_CUR_POL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) - -/* - * OTG_OVER_CUR_DIS (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) - -/* - * SER_MODE_SUSPEND_EN (RW) - * - * for naneng usbphy, only switch to serial mode when suspend - */ -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL0 */ -/* - * GPIO_ID_SEL_N (RW) - * - */ -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) - -/* - * ID_DIG_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) - -/* - * SESS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) - -/* - * VBUS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) - -/* - * ID_DIG_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) - -/* - * SESS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) - -/* - * VBUS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL1 */ -/* - * UTMI_CFG_RST_N (RW) - * - */ -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) - -/* - * UTMI_OTG_SUSPENDM (RW) - * - * OTG suspend, not utmi_suspendm - */ -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) - -/* Bitfield definition for register: TOP_STATUS */ -/* - * WAKEUP_INT_STATUS (RW) - * - */ -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * UTMI_CLK_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) -#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) - -/* - * LINE_STATE (RW) - * - */ -#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) -#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) -#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) -#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) - -/* - * HOST_DISCONNECT (RW) - * - */ -#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) -#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) - -/* - * ID_DIG (RW) - * - */ -#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) -#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) -#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) -#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) - -/* - * UTMI_SESS_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) -#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) - -/* - * VBUS_VALID (RW) - * - */ -#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) -#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) -#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) -#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) - - - -/* ENDPTCTRL register group index macro definition */ -#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) -#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) -#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) -#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) -#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) -#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) -#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) -#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) - - -#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_wdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_wdg_regs.h deleted file mode 100644 index 89788a7ebce..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6200/ip/hpm_wdg_regs.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_WDG_H -#define HPM_WDG_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CTRL; /* 0x10: Control Register */ - __W uint32_t RESTART; /* 0x14: Restart Register */ - __W uint32_t WREN; /* 0x18: Write Protection Register */ - __W uint32_t ST; /* 0x1C: Status Register */ -} WDG_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * RSTTIME (RW) - * - * The time interval of the reset stage: - * 0: Clock period x 2^7 - * 1: Clock period x 2^8 - * 2: Clock period x 2^9 - * 3: Clock period x 2^10 - * 4: Clock period x 2^11 - * 5: Clock period x 2^12 - * 6: Clock period x 2^13 - * 7: Clock period x 2^14 - */ -#define WDG_CTRL_RSTTIME_MASK (0x700U) -#define WDG_CTRL_RSTTIME_SHIFT (8U) -#define WDG_CTRL_RSTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK) -#define WDG_CTRL_RSTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT) - -/* - * INTTIME (RW) - * - * The timer interval of the interrupt stage: - * 0: Clock period x 2^6 - * 1: Clock period x 2^8 - * 2: Clock period x 2^10 - * 3: Clock period x 2^11 - * 4: Clock period x 2^12 - * 5: Clock period x 2^13 - * 6: Clock period x 2^14 - * 7: Clock period x 2^15 - * 8: Clock period x 2^17 - * 9: Clock period x 2^19 - * 10: Clock period x 2^21 - * 11: Clock period x 2^23 - * 12: Clock period x 2^25 - * 13: Clock period x 2^27 - * 14: Clock period x 2^29 - * 15: Clock period x 2^31 - */ -#define WDG_CTRL_INTTIME_MASK (0xF0U) -#define WDG_CTRL_INTTIME_SHIFT (4U) -#define WDG_CTRL_INTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK) -#define WDG_CTRL_INTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT) - -/* - * RSTEN (RW) - * - * Enable or disable the watchdog reset - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_RSTEN_MASK (0x8U) -#define WDG_CTRL_RSTEN_SHIFT (3U) -#define WDG_CTRL_RSTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK) -#define WDG_CTRL_RSTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT) - -/* - * INTEN (RW) - * - * Enable or disable the watchdog interrupt - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_INTEN_MASK (0x4U) -#define WDG_CTRL_INTEN_SHIFT (2U) -#define WDG_CTRL_INTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK) -#define WDG_CTRL_INTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT) - -/* - * CLKSEL (RW) - * - * Clock source of timer: - * 0: EXTCLK - * 1: PCLK - */ -#define WDG_CTRL_CLKSEL_MASK (0x2U) -#define WDG_CTRL_CLKSEL_SHIFT (1U) -#define WDG_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK) -#define WDG_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT) - -/* - * EN (RW) - * - * Enable or disable the watchdog timer - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_EN_MASK (0x1U) -#define WDG_CTRL_EN_SHIFT (0U) -#define WDG_CTRL_EN_SET(x) (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK) -#define WDG_CTRL_EN_GET(x) (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT) - -/* Bitfield definition for register: RESTART */ -/* - * RESTART (WO) - * - * Write the magic number - * ATCWDT200_RESTART_NUM to restart the - * watchdog timer. - */ -#define WDG_RESTART_RESTART_MASK (0xFFFFU) -#define WDG_RESTART_RESTART_SHIFT (0U) -#define WDG_RESTART_RESTART_SET(x) (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK) -#define WDG_RESTART_RESTART_GET(x) (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT) - -/* Bitfield definition for register: WREN */ -/* - * WEN (WO) - * - * Write the magic code to disable the write - * protection of the Control Register and the - * Restart Register. - */ -#define WDG_WREN_WEN_MASK (0xFFFFU) -#define WDG_WREN_WEN_SHIFT (0U) -#define WDG_WREN_WEN_SET(x) (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK) -#define WDG_WREN_WEN_GET(x) (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * INTEXPIRED (W1C) - * - * The status of the watchdog interrupt timer - * 0: timer is not expired yet - * 1: timer is expired - */ -#define WDG_ST_INTEXPIRED_MASK (0x1U) -#define WDG_ST_INTEXPIRED_SHIFT (0U) -#define WDG_ST_INTEXPIRED_SET(x) (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK) -#define WDG_ST_INTEXPIRED_GET(x) (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT) - - - - -#endif /* HPM_WDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/HPM6360_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/HPM6360_svd.xml deleted file mode 100644 index 8c29b378ba6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/HPM6360_svd.xml +++ /dev/null @@ -1,30839 +0,0 @@ - - - HPMICRO - HPM6360 - HPM6300 - 1.0 - HPM6300 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000301 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: cpu0 fastgpio - 0 - 1 - read-write - - - - - - - - ADC0 - ADC0 - ADC16 - 0xf0010000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 16 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x01F07FFF - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ADC1 - ADC1 - ADC16 - 0xf0014000 - - - ADC2 - ADC2 - ADC16 - 0xf0018000 - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - 4 - 0x20 - chn0,chn1,chn2,chn3 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - DAC - DAC - DAC - 0xf0024000 - - 0x0 - 0x4c - registers - - - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - write-only - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - write-only - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - write-only - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - write-only - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - write-only - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; -11: trigger mode, DAC output from external trigger signals -Note: -Trigger mode is not supported in hpm63xx and hpm62xx families. - 4 - 2 - write-only - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - write-only - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - write-only - - - - - cfg1 - No description available - 0x4 - 32 - 0x00010000 - 0x0007FFFF - - - ANA_CLK_EN - set to enable analog clock(divided by ana_div_cfg) -need to be set in direct mode and trigger mode - 18 - 1 - read-write - - - ANA_DIV_CFG - clock divider config for ana_clk to dac analog; -00: div2 -01: div4 -10: div6 -11: div8 - 16 - 2 - read-write - - - DIV_CFG - step mode and buffer mode: - defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. -Direct mode and trigger mode: - defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. -Note: -For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. - 0 - 16 - read-write - - - - - cfg2 - No description available - 0x8 - 32 - 0x00000000 - 0x000000FF - - - DMA_RST1 - set to reset dma read pointer to buf1_start_addr; -if set both dma_rst0&dma_rst1, will set to buf0_start_addr -user can set fifo_clr bit when use dma_rst* - 7 - 1 - write-only - - - DMA_RST0 - set to reset dma read pointer to buf0_start_addr - 6 - 1 - write-only - - - FIFO_CLR - set to clear FIFO content(set both read/write pointer to 0) - 5 - 1 - write-only - - - BUF_SW_TRIG - software trigger for buffer mode, -W1C in single mode. -RW in continual mode - 4 - 1 - read-write - - - STEP_SW_TRIG3 - No description available - 3 - 1 - read-write - - - STEP_SW_TRIG2 - No description available - 2 - 1 - read-write - - - STEP_SW_TRIG1 - No description available - 1 - 1 - read-write - - - STEP_SW_TRIG0 - software trigger0 for step mode, -W1C in single mode. -RW in continual mode - 0 - 1 - read-write - - - - - 4 - 0x4 - step0,step1,step2,step3 - STEP_CFG[%s] - no description available - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - ROUND_MODE - 0: stop at end point; -1: reload start point, step again - 29 - 1 - read-write - - - UP_DOWN - 0 for up, 1 for down - 28 - 1 - read-write - - - END_POINT - No description available - 16 - 12 - read-write - - - STEP_NUM - output data change step_num each DAC clock cycle. -Ex: if step_num=3, output data sequence is 0,3,6,9 -NOTE: user should make sure end_point can be reached if step_num is not 1 -if step_num is 0, output data will always at start point - 12 - 4 - read-write - - - START_POINT - No description available - 0 - 12 - read-write - - - - - 2 - 0x4 - buf0,buf1 - BUF_ADDR[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFD - - - BUF_START_ADDR - buffer start address, should be 4-byte aligned -AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - 2 - 30 - read-write - - - BUF_STOP - set to stop read point at end of bufffer0 - 0 - 1 - read-write - - - - - buf_length - No description available - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF1_LEN - buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - 16 - 16 - read-write - - - BUF0_LEN - No description available - 0 - 16 - read-write - - - - - irq_sts - No description available - 0x30 - 32 - 0x00000000 - 0x0000000F - - - AHB_ERROR - set if hresp==2'b01(ERROR) - 3 - 1 - write-only - - - FIFO_EMPTY - No description available - 2 - 1 - write-only - - - BUF1_CMPT - No description available - 1 - 1 - write-only - - - BUF0_CMPT - No description available - 0 - 1 - write-only - - - - - irq_en - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - STEP_CMPT - No description available - 4 - 1 - read-write - - - AHB_ERROR - No description available - 3 - 1 - read-write - - - FIFO_EMPTY - No description available - 2 - 1 - read-write - - - BUF1_CMPT - No description available - 1 - 1 - read-write - - - BUF0_CMPT - No description available - 0 - 1 - read-write - - - - - dma_en - No description available - 0x38 - 32 - 0x00000000 - 0x00000003 - - - BUF1_CMPT - No description available - 1 - 1 - read-write - - - BUF0_CMPT - No description available - 0 - 1 - read-write - - - - - ana_cfg0 - No description available - 0x40 - 32 - 0x00000030 - 0x000001FF - - - DAC12BIT_LP_MODE - No description available - 8 - 1 - read-write - - - DAC_CONFIG - No description available - 4 - 4 - read-write - - - CALI_DELTA_V_CFG - No description available - 2 - 2 - read-write - - - BYPASS_CALI_GM - No description available - 1 - 1 - read-write - - - DAC12BIT_EN - No description available - 0 - 1 - read-write - - - - - cfg0_bak - No description available - 0x44 - 32 - 0x00000000 - 0x0FFF03FF - - - SW_DAC_DATA - dac data used in direct mode(dac_mode==2'b10) - 16 - 12 - read-write - - - DMA_AHB_EN - set to enable internal DMA, it will read one burst if enough space in FIFO. -Should only be used in buffer mode. - 9 - 1 - read-write - - - SYNC_MODE - 1: sync dac clock and ahb clock. - all HW trigger signals are pulse in sync mode, can get faster response; -0: async dac clock and ahb_clock - all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - 8 - 1 - read-write - - - TRIG_MODE - 0: single mode, one trigger pulse will send one 12bit data to DAC analog; -1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - 7 - 1 - read-write - - - HW_TRIG_EN - set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - 6 - 1 - read-write - - - DAC_MODE - 00: direct mode, DAC output the fixed configured data(from sw_dac_data) -01: step mode, DAC output from start_point to end point, with configured step, can step up or step down -10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - 4 - 2 - read-write - - - BUF_DATA_MODE - data structure for buffer mode, -0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. -1: each 32-bit data contains 1 point, b11:0 for first - 3 - 1 - read-write - - - HBURST_CFG - DAC support following fixed burst only -000-SINGLE; 011-INCR4; 101: INCR8 -others are reserved - 0 - 3 - read-write - - - - - status0 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFF80 - - - CUR_BUF_OFFSET - No description available - 8 - 16 - read-write - - - CUR_BUF_INDEX - No description available - 7 - 1 - read-write - - - - - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x10 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x0000000F - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x000000CF - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - PUART - PUART - UART - 0xf40e4000 - - - CAN0 - CAN0 - CAN - 0xf0080000 - - 0x0 - 0xca - registers - - - - 20 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17,buf18,buf19 - RBUF[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - 18 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17 - TBUF[%s] - no description available - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - 2 - 0x4 - wrd0,wrd1 - TTS[%s] - no description available - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - CMD_STA_CMD_CTRL - config, status, command and control bits - 0xa0 - 32 - 0x00900080 - 0xFBF3FFFF - - - SACK - Self-ACKnowledge -0 – no self-ACK -1 – self-ACK when LBME=1 - 31 - 1 - read-write - - - ROM - Receive buffer Overflow Mode -In case of a full RBUF when a new message is received, then ROM selects the following: -1 – The new message will not be stored. -0 – The oldest message will be overwritten. - 30 - 1 - read-write - - - ROV - Receive buffer OVerflow -1 – Overflow. At least one message is lost. -0 – No Overflow. -ROV is cleared by setting RREL=1. - 29 - 1 - read-only - - - RREL - Receive buffer RELease -The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL -core points to the next RB slot. RSTAT gets updated. -1 – Release: The host has read the RB. -0 – No release - 28 - 1 - read-write - - - RBALL - Receive Buffer stores ALL data frames -0 – normal operation -1 – RB stores correct data frames as well as data frames with error - 27 - 1 - read-write - - - RSTAT - Receive buffer STATus -00 - empty -01 - > empty and < almost full (AFWL) -10 -  almost full (programmable threshold by AFWL) but not full and no overflow -11 - full (stays set in case of overflow – for overflow signaling see ROV) - 24 - 2 - read-only - - - FD_ISO - CAN FD ISO mode -0 - Bosch CAN FD (non-ISO) mode -1 - ISO CAN FD mode (ISO 11898-1:2015) -ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. -Both modes are incompatible and must not be mixed in one CAN network. -This bit has no impact to CAN 2.0B. -This bit is only writeable if RESET=1. - 23 - 1 - read-write - - - TSNEXT - Transmit buffer Secondary NEXT -0 - no action -1 - STB slot filled, select next slot. -After all frame bytes are written to the TBUF registers, the host controller has to set -TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF -registers to the next slot. Once a slot is marked as filled a transmission can be started -using TSONE or TSALL. -It is possible to set TSNEXT and TSONE or TSALL together in one write access. -TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL -core immediately after it was set. -Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and -automatically cleared. It does not do any harm. -If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. -TSNEXT has no meaning in TTCAN mode and is fixed to 0. - 22 - 1 - read-write - - - TSMODE - Transmit buffer Secondary operation MODE -0 - FIFO mode -1 - priority decision mode -In FIFO mode frames are transmitted in the order in that they are written into the STB. -In priority decision mode the frame with the highest priority in the STB is automatically -transmitted first. The ID of a frame is used for the priority decision. A lower ID means a -higher priority of a frame. A frame in the PTB has always the highest priority regardless of -the ID. -TSMODE shall be switched only if the STB if empty - 21 - 1 - read-write - - - TTTBM - TTCAN Transmit Buffer Mode -If TTEN=0 then TTTBM is ignored, otherwise the following is valid: -0 - separate PTB and STB, behavior defined by TSMODE -1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR -For event-driven CAN communication (TTEN=0), the system provides PTB and STB and -the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. -For time-triggered CAN communication (TTEN=1) with full support of all features including -time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are -addressable using TTPTR and TBPTR. -For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode -and the behavior can be selected by TSMODE. -TTTBM shall be switched only if the TBUF is empty. - 20 - 1 - read-write - - - TSSTAT - Transmission Secondary STATus bits -If TTEN=0 or TTTBM=0: -00 – STB is empty -01 – STB is less than or equal to half full -10 – STB is more than half full -11 – STB is full -If the STB is disabled using STB_DISABLE, then TSSTAT=00. -If TTEN=1 and TTTBM=1: -00 – PTB and STB are empty -01 – PTB and STB are not empty and not full -11 – PTB and STB are full - 16 - 2 - read-only - - - TBSEL - Transmit Buffer Select -Selects the transmit buffer to be loaded with a message. Use the TBUF registers for -access. TBSEL needs to be stable all the time the TBUF registers are written and when -TSNEXT is set. -0 - PTB (high-priority buffer) -1 - STB -The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - 15 - 1 - read-write - - - LOM - Listen Only Mode -0 - Disabled -1 - Enabled -LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM -is enabled and LBME is disabled. -LOM=1 and LBME=0 disables all transmissions. -LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables -the transmission of own frames. - 14 - 1 - read-write - - - STBY - Transceiver Standby Mode -0 - Disabled -1 - Enabled -This register bit is connected to the output signal stby which can be used to control a -standby mode of a transceiver. -STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. -If the host sets STBY to 0 then the host needs to wait for the time required by the -transceiver to start up before the host requests a new transmission. - 13 - 1 - read-write - - - TPE - Transmit Primary Enable -1 - Transmission enable for the message in the high-priority PTB -0 - No transmission for the PTB -If TPE is set, the message from the PTB will be transmitted at the next possible transmit -position. A started transmission from the STB will be completed before, but pending new -messages are delayed until the PTB message has been transmitted. -TPE stays set until the message has been transmitted successfully or it is aborted using -TPA. -The host controller can set TPE to 1 but can not reset it to 0. This would only be possible -using TPA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 12 - 1 - read-write - - - TPA - Transmit Primary Abort -1 – Aborts a transmission from PTB which has been requested by TPE=1 but not -started yet. (The data bytes of the message remains in the PTB.) -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA -automatically de-asserts TPE. -The host controller can set TPA to 1 but can not reset it to 0. -During the short time while the CAN-CTRL core resets the bit, it cannot be set by the -host. -The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). -TPA should not be set simultaneously with TPE. - 11 - 1 - read-write - - - TSONE - Transmit Secondary ONE frame -1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message -and in priority mode this is the one with the highest priority. -TSONE in priority mode is difficult to handle, because it is not always clear which -message will be transmitted if new messages are written to the STB meanwhile. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSONE stays set until the message has been transmitted successfully or it is aborted -using TSA. -The host controller can set TSONE to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 10 - 1 - read-write - - - TSALL - Transmit Secondary ALL frames -1 – Transmission enable of all messages in the STB. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSALL stays set until all messages have been transmitted successfully or they are aborted -using TSA. -The host controller can set TSALL to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the messages. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). -If during a transmission the STB is loaded with a new frame then the new frame will be -transmitted too. In other words: a transmission initiated by TSALL is finished when the -STB becomes empty. - 9 - 1 - read-write - - - TSA - Transmit Secondary Abort -1 – Aborts a transmission from STB which has been requested but not started yet. -For a TSONE transmission, only one frame is aborted while for a TSALL -Transmission, all frames are aborted. -One or all message slots will be released which updates TSSTAT. -All aborted messages are lost because they are not accessible any more. -If in priority mode a TSONE transmission is aborted, then it is not clear which -frame will be aborted if new frames are written to the STB meanwhile. -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. -The host controller can set TSA to 1 but can not reset it to 0. -The bit will be reset to the hardware reset value if RESET=1. -TSA should not be set simultaneously with TSONE or TSALL. - 8 - 1 - read-write - - - RESET - RESET request bit -1 - The host controller performs a local reset of CAN-CTRL. -0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. -Bit RESET forces several components to a reset state. -RESET is automatically set if the node enters “bus off” state. -Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. -This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. -The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - 7 - 1 - read-write - - - LBME - Loop Back Mode, External -0 - Disabled -1 - EnabledLBME should not be enabled while a transmission is active - 6 - 1 - read-write - - - LBMI - Loop Back Mode, Internal -0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - 5 - 1 - read-write - - - TPSS - Transmission Primary Single Shot mode for PTB -0 - Disabled -1 - Enabled - 4 - 1 - read-write - - - TSSS - Transmission Secondary Single Shot mode for STB -0 - Disabled -1 - Enabled - 3 - 1 - read-write - - - RACTIVE - Reception ACTIVE (Receive Status bit) -1 - The controller is currently receiving a frame. -0 - No receive activity. - 2 - 1 - read-only - - - TACTIVE - Transmission ACTIVE (Transmit Status bit) -1 - The controller is currently transmitting a frame. -0 - No transmit activity. - 1 - 1 - read-only - - - BUSOFF - Bus Off (Bus Status bit) -1 - The controller status is “bus off”. -0 - The controller status is “bus on”. -Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. -See Chapter 3.9.10.6 for details. - 0 - 1 - read-write - - - - - RTIE - Receive and Transmit Interrupt Enable Register RTIE - 0xa4 - 8 - 0xFE - 0xFF - - - RIE - Receive Interrupt Enable -0 – Disabled, 1 – Enabled - 7 - 1 - read-write - - - ROIE - RB Overrun Interrupt Enable -0 – Disabled, 1 – Enabled - 6 - 1 - read-write - - - RFIE - RB Full Interrupt Enable -0 – Disabled, 1 – Enabled - 5 - 1 - read-write - - - RAFIE - RB Almost Full Interrupt Enable -0 – Disabled, 1 – Enabled - 4 - 1 - read-write - - - TPIE - Transmission Primary Interrupt Enable -0 – Disabled, 1 – Enabled - 3 - 1 - read-write - - - TSIE - Transmission Secondary Interrupt Enable -0 – Disabled, 1 – Enabled - 2 - 1 - read-write - - - EIE - Error Interrupt Enable -0 – Disabled, 1 – Enabled - 1 - 1 - read-write - - - TSFF - If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag -1 - The STB is filled with the maximal number of messages. -0 - The STB is not filled with the maximal number of messages. -If the STB is disabled using STB_DISABLE, then TSFF=0. -If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag -1 - The buffer slot selected by TBPTR is filled. -0 - The buffer slot selected by TBPTR is empty. - 0 - 1 - read-only - - - - - RTIF - Receive and Transmit Interrupt Flag Register RTIF (0xa5) - 0xa5 - 8 - 0x00 - 0xFF - - - RIF - Receive Interrupt Flag -1 - Data or a remote frame has been received and is available in the receive buffer. -0 - No frame has been received. - 7 - 1 - write-only - - - ROIF - RB Overrun Interrupt Flag -1 - At least one received message has been overwritten in the RB. -0 - No RB overwritten. -In case of an overrun both ROIF and RFIF will be set. - 6 - 1 - write-only - - - RFIF - RB Full Interrupt Flag -1 - All RBs are full. If no RB will be released until the next valid message is received, -the oldest message will be lost. -0 - The RB FIFO is not full. - 5 - 1 - write-only - - - RAFIF - RB Almost Full Interrupt Flag -1 - number of filled RB slots >= AFWL_i -0 - number of filled RB slots < AFWL_i - 4 - 1 - write-only - - - TPIF - Transmission Primary Interrupt Flag -1 - The requested transmission of the PTB has been successfully completed. -0 - No transmission of the PTB has been completed. -In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - 3 - 1 - write-only - - - TSIF - Transmission Secondary Interrupt Flag -1 - The requested transmission of the STB has been successfully completed. -0 - No transmission of the STB has been completed successfully. -In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of -the message. - 2 - 1 - write-only - - - EIF - Error Interrupt Flag -1 - The border of the error warning limit has been crossed in either direction, -or the BUSOFF bit has been changed in either direction. -0 - There has been no change. - 1 - 1 - write-only - - - AIF - Abort Interrupt Flag -1 - After setting TPA or TSA the appropriated message(s) have been aborted. -It is recommended to not set both TPA and TSA simultaneously because both -source AIF. -0 - No abort has been executed. -The AIF does not have an associated enable register. - 0 - 1 - write-only - - - - - ERRINT - ERRor INTerrupt Enable and Flag Register ERRINT - 0xa6 - 8 - 0x00 - 0xFF - - - EWARN - Error WARNing limit reached -1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - 7 - 1 - read-only - - - EPASS - Error Passive mode active -0 - not active (node is error active) -1 - active (node is error passive) - 6 - 1 - read-only - - - EPIE - Error Passive Interrupt Enable - 5 - 1 - read-write - - - EPIF - Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error -active to error passive or vice versa and if this interrupt is enabled. - 4 - 1 - write-only - - - ALIE - Arbitration Lost Interrupt Enable - 3 - 1 - read-write - - - ALIF - Arbitration Lost Interrupt Flag - 2 - 1 - write-only - - - BEIE - Bus Error Interrupt Enable - 1 - 1 - read-write - - - BEIF - Bus Error Interrupt Flag - 0 - 1 - write-only - - - - - LIMIT - Warning Limits Register LIMIT - 0xa7 - 8 - 0x1B - 0xFF - - - AFWL - receive buffer Almost Full Warning Limit -AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. -AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . -AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) -AFWL_i > nRB is meaningless and automatically treated as nRB. -AFWL_i = nRB is a valid value, but note that RFIF also exists. - 4 - 4 - read-write - - - EWL - Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. -The value of EWL controls EIF. - 0 - 4 - read-write - - - - - S_PRESC - Bit Timing Register(Slow Speed) - 0xa8 - 32 - 0x01020203 - 0xFF7F7FFF - - - S_PRESC - Prescaler (slow speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - S_SJW - Synchronization Jump Width (slow speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 7 - read-write - - - S_SEG_2 - Bit Timing Segment 2 (slow speed) -Time after the sample point. - 8 - 7 - read-write - - - S_SEG_1 - Bit Timing Segment 1 (slow speed) -The sample point will be set to after start of bit time. - 0 - 8 - read-write - - - - - F_PRESC - Bit Timing Register(Fast Speed) - 0xac - 32 - 0x01020203 - 0xFF0F0F0F - - - F_PRESC - Prescaler (fast speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - F_SJW - Synchronization Jump Width (fast speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 4 - read-write - - - F_SEG_2 - Bit Timing Segment 2 (fast speed) -Time after the sample point - 8 - 4 - read-write - - - F_SEG_1 - Bit Timing Segment 1 (fast speed) -The sample point will be set to after start of bit time. - 0 - 4 - read-write - - - - - EALCAP - Error and Arbitration Lost Capture Register EALCAP - 0xb0 - 8 - 0x00 - 0xFF - - - KOER - Kind Of ERror (Error code) -000 - no error -001 - BIT ERROR -010 - FORM ERROR -011 - STUFF ERROR -100 - ACKNOWLEDGEMENT ERROR -101 - CRC ERROR -110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) -111 - not used -KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - 5 - 3 - read-only - - - ALC - Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - 0 - 5 - read-only - - - - - TDC - Transmitter Delay Compensation Register TDC - 0xb1 - 8 - 0x00 - 0xFF - - - TDCEN - Transmitter Delay Compensation ENable -TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - 7 - 1 - read-write - - - SSPOFF - Secondary Sample Point OFFset -The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. -SSPOFF is given as a number of TQ. - 0 - 7 - read-write - - - - - RECNT - Error Counter Registers RECNT - 0xb2 - 8 - 0x00 - 0xFF - - - RECNT - Receive Error CouNT (number of errors during reception) -RECNT is incremented and decremented as defined in the CAN specification. -RECNT does not overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - TECNT - Error Counter Registers TECNT - 0xb3 - 8 - 0x00 - 0xFF - - - TECNT - Transmit Error CouNT (number of errors during transmission) -TECNT is incremented and decremented as defined in the CAN specification. -In case of the “bus off state” TECNT may overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - ACFCTRL - Acceptance Filter Control Register ACFCTRL - 0xb4 - 8 - 0x00 - 0x2F - - - SELMASK - SELect acceptance MASK -0 - Registers ACF_x point to acceptance code -1 - Registers ACF_x point to acceptance mask. -ACFADR selects one specific acceptance filter. - 5 - 1 - read-write - - - ACFADR - acceptance filter address -ACFADR points to a specific acceptance filter. -The selected filter is accessible using theregisters ACF_x. -Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. -A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. -ACF_NUMBER = 16. - 0 - 4 - read-write - - - - - TIMECFG - CiA 603 Time-Stamping TIMECFG - 0xb5 - 8 - 0x00 - 0x03 - - - TIMEPOS - TIME-stamping POSition -0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - 1 - 1 - read-write - - - TIMEEN - TIME-stamping ENable -0 – disabled -1 – enabled - 0 - 1 - read-write - - - - - ACF_EN - Acceptance Filter Enable ACF_EN - 0xb6 - 16 - 0x0000 - 0xFFFF - - - ACF_EN - Acceptance filter Enable -1 - acceptance filter enabled -0 - acceptance filter disable -Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. -Disabled filters reject a message. Only enabled filters can accept a message if the -appropriate AMASK / ACODE configuration matches. - 0 - 16 - read-write - - - - - ACF - Acceptance CODE ACODE or ACMASK - 0xb8 - 32 - 0x00000000 - 0x7FFFFFFF - - - AIDEE - Acceptance mask IDE bit check enable -1 - acceptance filter accepts either standard or extended as defined by AIDE -0 - acceptance filter accepts both standard or extended frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 30 - 1 - read-write - - - AIDE - Acceptance mask IDE bit value -If AIDEE=1 then: -1 - acceptance filter accepts only extended frames -0 - acceptance filter accepts only standard frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 29 - 1 - read-write - - - CODE_MASK - Acceptance CODE -1 - ACC bit value to compare with ID bit of the received message -0 - ACC bit value to compare with ID bit of the received message -ACODE_x(10:0) will be used for extended frames. -ACODE_x(28:0) will be used for extended frames. -Only filter 0 is affected by the power-on reset. -Acceptance MASK(if SELMASK ==1 ) -1 - acceptance check for these bits of receive identifier disabled -0 - acceptance check for these bits of receive identifier enable -AMASK_x(10:0) will be used for extended frames. -AMASK_x(28:0) will be used for extended frames. -Disabled bits result in accepting the message. Therefore the default configuration after -reset for filter 0 accepts all messages. -Only filter 0 is affected by the power-on reset. - 0 - 29 - read-write - - - - - VER - Version Information VER - 0xbc - 16 - 0x0000 - 0xFFFF - - - VERSION - Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and -VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - 0 - 16 - read-write - - - - - TBSLOT - TTCAN: TB Slot Pointer TBSLOT - 0xbe - 8 - 0x00 - 0xFF - - - TBE - set TB slot to “Empty” -1 - slot selected by TBPTR shall be marked as “empty” -0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. -If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - transmissionis not active any more. -If both TBF and TBE are set, then TBE wins - 7 - 1 - read-write - - - TBF - set TB slot to “Filled” -1 - slot selected by TBPTR shall be marked as “filled” -0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. -If both TBF and TBE are set, then TBE wins. - 6 - 1 - read-write - - - TBPTR - Pointer to a TB message slot. -0x00 - Pointer to the PTB -others - Pointer to a slot in the STB -The message slot pointed to by TBPTR is readable / writable using the TBUF registers. -Write access is only possible if TSFF=0. -Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. -TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. -TBPTR can only point to buffer slots, that exist in the hardware. -Unusable bits ofTBPTR are fixed to 0. -TBPTR is limited to the PTB and 63 STB slots. - More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - 0 - 6 - read-write - - - - - TTCFG - TTCAN: Time Trigger Configuration TTCFG - 0xbf - 8 - 0x00 - 0xFF - - - WTIE - Watch Trigger Interrupt Enable - 7 - 1 - read-write - - - WTIF - Watch Trigger Interrupt Flag -WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - 6 - 1 - read-write - - - TEIF - Trigger Error Interrupt Flag -The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - 5 - 1 - read-write - - - TTIE - Time Trigger Interrupt Enable -If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - 4 - 1 - read-write - - - TTIF - Time Trigger Interrupt Flag -TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. -Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. -If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - 3 - 1 - read-write - - - T_PRESC - TTCAN Timer PRESCaler -00b - 1 -01b - 2 -10b - 4 -11b - 8 -The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. -T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - 1 - 2 - read-write - - - TTEN - Time Trigger Enable -1 - TTCAN enabled, timer is running0 - disabled - 0 - 1 - read-write - - - - - REF_MSG - TTCAN: Reference Message REF_MSG - 0xc0 - 32 - 0x00000000 - 0x9FFFFFFF - - - REF_IDE - REFerence message IDE bit. - 31 - 1 - read-write - - - REF_MSG - REFerence message IDentifier. -If REF_IDE is -1 - REF_ID(28:0) is valid (extended ID) -0 - REF_ID(10:0) is valid (standard ID) -REF_ID is used in TTCAN mode to detect a reference message. This holds for time -slaves (reception) as well as for the time master (transmission). If the reference -message is detected and there are no errors, then the Sync_Mark of this frame will -become the Ref_Mark. -REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. -These bits are used for up to 8 potential time masters. -CAN-CTRL recognizes the reference message only by ID. The payload is not tested. -Additional note: A time master will transmit a reference message in the same way as a -normal frame. REF_ID is intended for detection of a successful transmission of a -reference message. - 0 - 29 - read-write - - - - - TRIG_CFG - TTCAN: Trigger Configuration TRIG_CFG - 0xc4 - 16 - 0x0000 - 0xF73F - - - TEW - Transmit Enable Window -For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time -where the frame is allowed to start. TWE+1 defines the number of ticks. -TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - 12 - 4 - read-write - - - TTYPE - Trigger Type -000b - Immediate Trigger for immediate transmission -001b - Time Trigger for receive triggers -010b - Single Shot Transmit Trigger for exclusive time windows -011b - Transmit Start Trigger for merged arbitrating time windows -100b - Transmit Stop Trigger for merged arbitrating time windows -others - no action -The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the -transmit triggers. See Chapter 6.4 for more details. - 8 - 3 - read-write - - - TTPTR - Transmit Trigger TB slot Pointer -If TTPTR is too big and points to a slot that is not available, then TEIF is set and no -new trigger can be activated after a write access to TT_TRIG_1. -If TTPTR points to an empty slot, then TEIF will be set at the moment, when the -trigger time is reached. - 0 - 6 - read-write - - - - - TT_TRIG - TTCAN: Trigger Time TT_TRIG - 0xc6 - 16 - 0x0000 - 0xFFFF - - - TT_TRIG - Trigger Time -TT_TRIG(15:0) defines the cycle time for a trigger. -For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - 0 - 16 - read-write - - - - - TT_WTRIG - TTCAN: Watch Trigger Time TT_WTRIG - 0xc8 - 16 - 0x0000 - 0xFFFF - - - TT_WTRIG - Watch Trigger Time -TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - 0 - 16 - read-write - - - - - - - CAN1 - CAN1 - CAN - 0xf0084000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - Restart - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WrEn - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - St - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - write-only - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - 16 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x10 - 0x130 - registers - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - IntStatus - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - write-only - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - write-only - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 8 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel n Control Register - 0x0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel n Transfer Size Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - SrcAddr - Channel n Source Address Low Part Register - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - SrcAddrH - Channel n Source Address High Part Register - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - DstAddr - Channel n Destination Address Low Part Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - DstAddrH - Channel n Destination Address High Part Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - LLPointer - Channel n Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - LLPointerH - Channel n Linked List Pointer High Part Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0100000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - write-only - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - write-only - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXD[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -5'h2: 2 channels -5'h4: 4 channels -... -5‘h10: 16 channels (max) - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXDSLOT[%s] - no description available - 0x60 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXDSLOT[%s] - no description available - 0x70 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0104000 - - - DAO - DAO - DAO - 0xf0110000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000200FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to consume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x000007C0 - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0114000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - write-only - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - write-only - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description available - 18 - 2 - read-write - - - CH8_TYPE - No description available - 16 - 2 - read-write - - - CH7_TYPE - No description available - 14 - 2 - read-write - - - CH6_TYPE - No description available - 12 - 2 - read-write - - - CH5_TYPE - No description available - 10 - 2 - read-write - - - CH4_TYPE - No description available - 8 - 2 - read-write - - - CH3_TYPE - No description available - 6 - 2 - read-write - - - CH2_TYPE - No description available - 4 - 2 - read-write - - - CH1_TYPE - No description available - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMAddr - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMData - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x290 - registers - - - - unlk - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, -otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - sta - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - - - rld - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, -and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - frcmd - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0-7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - shlk - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, write access is not permitted - 31 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CHCFG[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - - - gcr - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFEF - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as compare shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. -This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. -User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - TIMERRESET - set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear - 3 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - write-only - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - shcr - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPPOS[%s] - no description available - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - cnt - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPNEG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - cntcopy - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - PWMCFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - sr - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - write-only - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - write-only - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - write-only - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - write-only - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - write-only - - - - - irqen - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - dmaen - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - 24 - 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMPCFG[%s] - no description available - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x88 - registers - - - - cr - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - uvwcfg - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - trgoen - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - dmaen - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - w - W counter - 0x0 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - v - V counter - 0x4 - 32 - 0x00000000 - 0xCFFFFFFF - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - u - U counter - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - - 3 - 0x8 - u,v,w - HIS[%s] - no description available - 0x70 - - his0 - history register 0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - his1 - history register 1 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - 4 - 0x4 - spdhis0,spdhis1,spdhis2,spdhis3 - SPDHIS[%s] - no description available - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - 20 - 0x4 - PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - 64 - 0x4 - TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM_IN16,PWM_IN17,PWM_IN18,PWM_IN19,PWM_IN20,PWM_IN21,PWM_IN22,PWM_IN23,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,GPTMRb_SYNCI,GPTMRb_IN2,GPTMRb_IN3,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP - TRGOCFG[%s] - no description available - 0x100 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - DMACFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - ENET0 - ENET0 - ENET - 0xf2000000 - - 0x0 - 0x3028 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. -Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -Note: - Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, -that is, the current frame does not use the updated value. -- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. -When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. -When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. -When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. -This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - or SGMII port. When this bit is reset, no such information is driven to the PHY. -This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. -When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). -Lower values are not considered. -In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. -When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. -In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, -this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. -This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. -This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. -In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. -In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. -When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. -This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. -The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. -It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) -of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. -The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) -and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). -When this bit is reset, this function is disabled. -When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. -When a collision occurs on the GMII or MII interface, -the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. -When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. -All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. -When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays - (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. -This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. -The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, -when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, -but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. -For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, -the transmitter transmits and collision happens. -Because of collision, the transmitter needs to back off and then defer again after back off completion. -In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, -the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. -The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, -the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. -When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, -this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. -When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. -When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. -When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. -The following conditions should be true for the Pause frames processing: -- Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. -- Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. -- Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. -Note: This field should be set to 01 only when the Condition 1 is true, -that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. -Otherwise, the Pause frame filtering may be inconsistent. -When Condition 1 is false, the Pause frames are considered as generic control frames. -Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, -you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. -When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. -When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. -When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, -the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. -When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. -The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. -The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) -ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved -When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. -For example, -when CSR clock is of 100 MHz frequency and you program these bits as 1010, -then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. -Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, -it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. -During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - Register 5 is invalid until this bit is cleared by the MAC. -Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. -Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. -The subsequent read or write operation should happen only after the previous operation is complete. -Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, -there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation -or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. -If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of -the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). -When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. -The threshold values should be always less than the Pause Time configured in Bits[31:16]. - For example, if PT = 100H (256 slot-times), and PLT = 01, -then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. -The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. -When this bit is set, the MAC can also detect Pause frames with unicast address of the station. -This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. -When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. -When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. -In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. -In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - To initiate a Pause frame, the Application must set this bit to 1'b1. -During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. -After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. -The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, -when this bit is set (and TFE is set), then backpressure is asserted by the MAC. -During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. -This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. -When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). -A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. -When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, -the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, -only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. -When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. -The following list describes the bits of this field: - - Bits [15:13]: User Priority -- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) -- Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). -The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. -The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. -Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, -the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. -This bit is then self-cleared and the power-down mode is disabled. -The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. -The frames, received by the MAC after this bit is cleared, are forwarded to the application. -This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. -Note: You can gate-off the CSR clock during the power-down mode. -However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Register - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. -This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, -the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. -The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. -If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), -when the MAC is in the LPI mode, the MAC exits the LPI mode. -When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. -When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. -When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. -This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. -This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. -The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - the LPI pattern to the PHY and before it resumes the normal transmission. -The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. -This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. -This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: -- The system time value equals or exceeds the value specified in the Target Time High and Low registers. -- There is an overflow in the seconds register. - - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). -This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). -This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is RO. The bit value is fixed at 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - 4 - 0x8 - 1,2,3,4 - MAC_ADDR[%s] - no description available - 0x48 - - HIGH - MAC Address High Register - 0x0 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. -When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. -Each bit controls the masking of the bytes as follows: -- Bit 29: Register 18[15:8] -- Bit 28: Register 18[7:0] -- Bit 27: Register 19[31:24] - -... -- Bit 24: Register 19[7:0] -You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - LOW - MAC Address Low Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0000003F - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. -It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. -The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. -When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -this field is used as watchdog timeout for a received frame. - If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. -Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). -Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - mmc_cntrl - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. -This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. -Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - mmc_intr_rx - MMC Receive Interrupt - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_tx - MMC Transmit Interrupt - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_mask_rx - MMC Receive Interrupt mask - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - mmc_intr_mask_tx - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - tx64octets_gb - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx65to127octets_gb - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx128to255octets_gb - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx256to511octets_gb - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx512to1023octets_gb - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx1024tomaxoctets_gb - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - rxframecount_gb - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - mmc_ipc_intr_mask_rx - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_ipc_intr_rx - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - rxipv4_gd_fms - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - 1 - 0x20 - 0 - L3_L4_CFG[%s] - no description available - 0x400 - - L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x0 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. -When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. -This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. -When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. -The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, -which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. -The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. -This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. -When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. -Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. -This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. -When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. -The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L4_Addr - Layer 4 Address Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_Addr_0 - Layer 3 Address 0 Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_1 - Layer 3 Address 1 Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_2 - Layer 3 Address 2 Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_Addr_3 - Layer 3 Address 3 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. -This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). -Note: Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - When reset, the rollover value of sub-second register is 0x7FFF_FFFF. -The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. -This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. -This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the initialization is complete. -The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. -You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. -For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) -when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. -When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. -In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Target Time Registers when this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). -This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. -The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. -These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. -This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. -This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. -When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. -These bits are applicable only if the number of Auxiliary snapshots is more than one. -One bit is assigned for each trigger as shown in the following list: -- Bit 16: Auxiliary trigger 0 -- Bit 17: Auxiliary trigger 1 -- Bit 18: Auxiliary trigger 2 -- Bit 19: Auxiliary trigger 3 - The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description available - 7 - 1 - read-only - - - TSTARGT2 - No description available - 6 - 1 - read-only - - - TSTRGTERR1 - No description available - 5 - 1 - read-only - - - TSTARGT1 - No description available - 4 - 1 - read-only - - - TSTRGTERR - No description available - 3 - 1 - read-only - - - AUXTSTRIG - No description available - 2 - 1 - read-only - - - TSTARGT - No description available - 1 - 1 - read-only - - - TSSOVF - No description available - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - write-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - write-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - write-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. -The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. -For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. -Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. -In the digital rollover mode, the PPS output frequency is an average number. -The actual clock is of different frequency that gets synchronized every second. For example: -- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms -- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - - One clock of 50 percent duty cycle and 537 ms period - - Second clock of 463 ms period (268 ms low and 195 ms high) -- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - - Three clocks of 50 percent duty cycle and 268 ms period - - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-only - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-only - - - - - PPS0_INTERVAL - PPS Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if the PTP reference clock is 50 MHz (period of 20ns), -and desired interval between rising edges of PPS0 signal output is 100ns - (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - 3 - 0x20 - 1,2,3 - PPS[%s] - no description available - 0x780 - - TGTTM_SEC - PPS Target Time Seconds Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Targeers wht Time Registen this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - INTERVAL - PPS Interval Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), -then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - WIDTH - PPS Width Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, - if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), -then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. -The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. -By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), -whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, -the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. -Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. -The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. -When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. -This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. -When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. -When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. -PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. -Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. -If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). -This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. -The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. -This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: -- Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. -When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. -The address skipping starts from the end of current descriptor to the start of next descriptor. -When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. -It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. -Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. -Note: - The Software reset function is driven only by this bit. -Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. -- The reset operation is completed only when all resets in all active clock domains are de-asserted. -Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. -The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. -The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. -The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. -To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. -Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. -When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. --or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. -To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. -Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. -Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. -This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. - The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the Power Management feature is enabled. -Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac -to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): -- PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event -- SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - read any of the following corresponding registers: -- PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) -- SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) -- General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in -Register 7 (Interrupt Enable Register): -- Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt -- Register 5[14]: Early Receive Interrupt Only unmasked bits - (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following -when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive FIFO Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt -- Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. -This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. -The Receive Process is suspended. To resume processing Receive descriptors, - the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. -This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. -When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, -and the specific frame status information is updated in the descriptor. -The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). -When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. -To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. -When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, -this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. -This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. -When this bit is set, the TTC values specified in Bits [16:14] are ignored. -This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. -This bit is cleared internally when the flushing operation is complete. -The Operation Mode register should not be written to until this bit is cleared. -The data which is already accepted by the MAC transmitter is not flushed. -It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. - Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. -In addition, full frames with a length less than the threshold are also transmitted. - These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -Descriptor acquisition is attempted either from the current position in the list, -which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), -or from the position retained when transmission was stopped previously. - If the DMA does not own the current descriptor, -transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Transmission command is effective only when transmission is stopped. -If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - then the DMA behavior is unpredictable. When this bit is reset, -the transmission process is placed in the Stopped state after completing the transmission of the current frame. -The Next Descriptor position in the Transmit List is saved, -and it becomes the current position when transmission is restarted. -To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. -The new value is considered when this bit is set again. -The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB -The de-assertion is effective only after flow control is asserted. - If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. -These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) -These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. -These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, -an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. -These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. -Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, -the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. -When reset, the flow control operation is disabled. - This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). -However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), -then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, -the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. -When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. -If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, -then the frame is dropped irrespective of the FEF bit setting. -However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. -Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: -- The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - - The advanced timestamp feature is not selected but the extended status is selected. -The extended status is available with the following features: -- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations -- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC -When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, -that is, frames that are larger than the computed giant frame limit. -When reset, the MAC does not drop the giant frames in the Rx FIFO. -Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: -- Configurations in which IP Checksum Offload (Type 1) is selected in Rx -- Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format -- Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. -Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. -In addition, full frames with length less than the threshold are automatically transferred. -The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. -These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. -The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. -The descriptor acquisition is attempted from the current position in the list, -which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. -If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Receive command is effective only when the reception has stopped. - If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. -When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. -The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. -The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. -When this bit is reset, normal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): - - Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt - - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. -When this bit is reset, the abnormal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt - - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, -that is, the Rx FIFO overflows with the overflow frame counter at maximum value. -In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, -that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. -This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. -The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer -of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. -When the watchdog timer runs out, the RI bit is set and the timer is stopped. -The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. -When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. -When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. -Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. -Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. -When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). -When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). -- When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. -- When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. -If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - CTRL2 - Control Register 1 - 0x3008 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt - 29 - 1 - read-write - - - ENET0_REFCLK_OE - set to enable output 50MHz clock to rmii phy. -User should set it if use soc internal clock as refclk - 19 - 1 - read-write - - - ENET0_PHY_INF_SEL - PHY mode select -001RGMII; 100RMII; -should be set before config IOMUX, otherwise may cause glitch for RGMII - 13 - 3 - read-write - - - ENET0_FLOWCTRL - flow control request - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - RMII mode output clock pad select -set to use refclk from pad; -Note: refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. - 10 - 1 - read-write - - - - - - - NTMR0 - NTMR0 - GPTMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x80007FFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - GPTMR0 - GPTMR0 - GPTMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - GPTMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf300c000 - - - PTMR - PTMR - GPTMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 8 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x3008 - registers - - - - SDMASA - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description available - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description available - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. -If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - 4 - 0x4 - RESP01,RESP23,RESP45,RESP67 - RESP[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - 0 - 32 - read-only - - - - - BUF_DATA - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description available - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description available - 0x28 - 32 - 0x00000000 - 0x070F0F3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - SD_BUS_PWR_VDD1 - SD Bus Power for VDD1 -This bit enables VDD1 power of the card. -This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. -Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. -In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. -Values: -0x0 (OFF): Power off -0x1 (ON): Power on - 8 - 1 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description available - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description available - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgment Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. -If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description available - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description available - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description available - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description available - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description available - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description available - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description available - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description available - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description available - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - 9 - 0x2 - INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 - PRESET[%s] - no description available - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description available - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description available - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description available - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description available - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description available - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description available - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description available - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description available - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description available - 0 - 1 - read-write - - - - - CQCTL - No description available - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description available - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description available - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description available - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description available - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description available - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description available - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description available - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description available - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description available - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description available - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description available - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description available - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description available - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description available - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description available - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description available - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description available - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description available - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description available - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description available - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description available - 0 - 32 - read-only - - - - - EMMC_BOOT_CTRL - No description available - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description available - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description available - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - MISC_CTRL0 - No description available - 0x3000 - 32 - 0x00000000 - 0x10020FFF - - - CARDCLK_INV_EN - set to invert card_clk, for slow speed card to meet 5ns setup timing. -May cause glitch on clock, should be set before enable clk(in core cfg) - 28 - 1 - read-write - - - PAD_CLK_SEL_B - set to use internal clock directly, may have timing issue; -clr to use clock loopback from pad. - 17 - 1 - read-write - - - FREQ_SEL_SW_EN - set to use FREQ_SEL_SW as card clock divider; -clear to use core logic as clock divider. - 11 - 1 - read-write - - - TMCLK_EN - set to force enable tmclk; -clear to use core signal intclk_en to control it - 10 - 1 - read-write - - - FREQ_SEL_SW - software card clock divider, it will be used only when FREQ_SEL_SW_EN is set - 0 - 10 - read-write - - - - - MISC_CTRL1 - No description available - 0x3004 - 32 - 0x00000000 - 0xB0000000 - - - CARD_ACTIVE - SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). -When counter finished, this bit will be cleared by hardware. -Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) - 31 - 1 - read-write - - - CARD_ACTIVE_PERIOD_SEL - card clock delay config. -00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle - 28 - 2 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00001E00 - 0x000F9FFF - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - FEMC - FEMC - FEMC - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - IOCTRL - IO Mux Control Register - 0x4 - 32 - 0x00000000 - 0x000000F0 - - - IO_CSX - IO_CSX output selection -0001b - SDRAM CS1 -0110b - SRAM CE# - 4 - 4 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - 3 - 0x4 - BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 - BR[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - write-only - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - write-only - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - write-only - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - write-only - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SRCTRL0 - SRAM control register 0 - 0x70 - 32 - 0x00000000 - 0x00000F01 - - - ADVH - ADV hold state -0b - ADV is high during address hold state -1b - ADV is low during address hold state - 11 - 1 - read-write - - - ADVP - ADV polarity -0b - ADV is active low -1b - ADV is active high - 10 - 1 - read-write - - - ADM - address data mode -00b - address and data MUX mode -11b - address and data non-MUX mode - 8 - 2 - read-write - - - PORTSZ - port size -0b - 8bit -1b - 16bit - 0 - 1 - read-write - - - - - SRCTRL1 - SRAM control register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - OEH - OE high time, is OEH+1 clock cycles - 28 - 4 - read-write - - - OEL - OE low time, is OEL+1 clock cycles - 24 - 4 - read-write - - - WEH - WE high time, is WEH+1 clock cycles - 20 - 4 - read-write - - - WEL - WE low time, is WEL+1 clock cycles - 16 - 4 - read-write - - - AH - Address hold time, is AH+1 clock cycles - 12 - 4 - read-write - - - AS - Address setup time, is AS+1 clock cycles - 8 - 4 - read-write - - - CEH - Chip enable hold time, is CEH+1 clock cycles - 4 - 4 - read-write - - - CES - Chip enable setup time, is CES+1 clock cycles - 0 - 4 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - FFA - FFA - FFA - 0xf3058000 - - 0x0 - 0x48 - registers - - - - CTRL - No description available - 0x0 - 32 - 0x00000000 - 0x80000001 - - - SFTRST - software reset the module if asserted to be 1. -EN is only active after this bit is zero. - 31 - 1 - read-write - - - EN - Asserted to enable the module - 0 - 1 - read-write - - - - - STATUS - No description available - 0x4 - 32 - 0x00000000 - 0x000000FF - - - FIR_OV - FIR Overflow err - 7 - 1 - write-only - - - FFT_OV - FFT Overflow Err - 6 - 1 - write-only - - - WR_ERR - AXI Data Write Error - 5 - 1 - write-only - - - RD_NXT_ERR - AXI Read Bus Error for NXT DATA - 4 - 1 - write-only - - - RD_ERR - AXI Data Read Error - 3 - 1 - write-only - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - write-only - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - write-only - - - - - INT_EN - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRSV1 - Reserved - 8 - 24 - read-write - - - FIR_OV - FIR Overflow err - 7 - 1 - read-write - - - FFT_OV - FFT Overflow Err - 6 - 1 - read-write - - - WR_ERR - Enable Data Write Error interrupt - 5 - 1 - read-write - - - RD_NXT_ERR - Enable Read Bus Error for NXT DATA interrupt - 4 - 1 - read-write - - - RD_ERR - Enable Data Read Error interrupt - 3 - 1 - read-write - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - read-write - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - read-write - - - - - OP_CTRL - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - NXT_ADDR - The address for the next command. -It will be processed after CUR_CMD is executed and done.. - 2 - 30 - read-write - - - NXT_EN - Whether NXT_CMD is enabled. -Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - 1 - 1 - read-write - - - EN - Whether CUR_CMD is enabled. -Asserted to enable the CUR_CMD - 0 - 1 - read-write - - - - - OP_CMD - No description available - 0x24 - 32 - 0x00000000 - 0x01FFFEFF - - - CONJ_C - asserted to have conjuate value for coefs in computation - 24 - 1 - read-write - - - CMD - The Command Used: -0: FIR -2: FFT -Others: Reserved - 18 - 6 - read-write - - - OUTD_TYPE - Output data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 15 - 3 - read-write - - - COEF_TYPE - Coef data type (used for FIR): -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 12 - 3 - read-write - - - IND_TYPE - Input data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 9 - 3 - read-write - - - NXT_CMD_LEN - The length of nxt commands in 32-bit words - 0 - 8 - read-write - - - - - OP_REG0 - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0x00003FFF - - - FIR_COEF_TAPS - Length of FIR coefs （max 256） - 0 - 14 - read-write - - - - - OP_FFT_MISC - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000007FF - - - FFT_LEN - FFT length -0:8, -..., -n:2^(3+n) - 7 - 4 - read-write - - - IFFT - Asserted to indicate IFFT - 6 - 1 - read-write - - - TMP_BLK - Memory block for indata. Should be assigned as 1 - 2 - 2 - read-write - - - IND_BLK - Memory block for indata. Should be assigned as 0 - 0 - 2 - read-write - - - - - OP_REG1 - No description available - UNION_2C - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC1 - No description available - UNION_2C - 0x2c - 32 - 0x00000000 - 0x003FFFFF - - - OUTD_MEM_BLK - Should be assigned as 0 - 20 - 2 - read-write - - - COEF_MEM_BLK - Should be assigned as 1 - 18 - 2 - read-write - - - IND_MEM_BLK - Should be assigned as 2 - 16 - 2 - read-write - - - FIR_DATA_TAPS - The input data data length - 0 - 16 - read-write - - - - - OP_REG2 - No description available - UNION_30 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FFT_INRBUF - No description available - UNION_30 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG3 - No description available - UNION_34 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_INBUF - No description available - UNION_34 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input data buffer pointer - 0 - 32 - read-write - - - - - OP_REG4 - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_COEFBUF - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The coef buf pointer - 0 - 32 - read-write - - - - - OP_FFT_OUTRBUF - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG5 - No description available - UNION_3C - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_OUTBUF - No description available - UNION_3C - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - 0 - 32 - read-write - - - - - OP_REG6 - No description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_REG7 - No description available - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x2c00 - registers - - - - 127 - 0x4 - cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,rst_soc,rst_cpu0,rsv24,rsv25,rsv26,rsv27,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_clk2_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_sdc0,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_dac0,clk_top_i2s0,clk_top_i2s1,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbp,axis,axic,femc,rom0,lmm0,ram0,mct0,xpi0,xpi1,sdp0,rng0,kman,dma0,dma1,ffa0,gpio,mbx0,wdg0,wdg1,tsns,tmr0,tmr1,tmr2,tmr3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,ptpc,adc0,adc1,adc2,dac0,acmp,i2s0,i2s1,pdm0,dao,synt,mot0,mot1,eth0,ntm0,sdc0,usb0,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 2 - 0x10 - link0,link1 - GROUP0[%s] - no description available - 0x800 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 1 - 0x10 - cpu0 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - - 1 - 0x10 - cpu0 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu stop, -bit01: soc_ctx is kept on while cpu stop, -bit02: cpu0_mem is kept on while cpu stop, -bit03: cpu0_ctx is kept on while cpu stop, -bit04: xtal_hold is kept on while cpu stop, -bit05: pll0_hold is kept on while cpu stop, -bit06: pll1_hold is kept on while cpu stop, -bit07: pll2_hold is kept on while cpu stop, - 0 - 8 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 8 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 8 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x00000000 - 0x000000FF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 8 - read-write - - - - - - 1 - 0x10 - cpu0 - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 2 - 0x10 - soc,cpu0 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000003 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 1 - 0x4 - clk_top_cpu0 - CLOCK_CPU[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xD0FF0FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - SUB1_DIV - ahb bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 20 - 4 - read-write - - - SUB0_DIV - axi bus divider, the bus clock is generated by cpu_clock/div -0: divider by 1 -1: divider by 2 -… - 16 - 4 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 39 - 0x4 - clk_top_mct0,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_sdc0 - CLOCK[%s] - no description available - 0x1804 - 32 - 0x00000000 - 0xD0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll0_clk2 -4:pll1_clk0 -5:pll1_clk1 -6:pll2_clk0 -7:pll2_clk1 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 3 - 0x4 - clk_top_adc0,clk_top_adc1,clk_top_adc2 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock N -1: ahb clock - 8 - 1 - read-write - - - - - 1 - 0x4 - clk_top_dac0 - DACCLK[%s] - no description available - 0x1c0c - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock N -1: ahb clock - 8 - 1 - read-write - - - - - 2 - 0x4 - clk_top_i2s0,clk_top_i2s1 - I2SCLK[%s] - no description available - 0x1c10 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock 0 -1: aud clock 0 for others , aud clock 1 for i2s0 - 8 - 1 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 1 - 0x400 - cpu0 - CPU[%s] - no description available - 0x2800 - - LP - CPU0 LP control - 0x0 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - CPU0 Lock GPR - 0x4 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 4 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 4 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf40 - registers - - - - 488 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,rsv92,rsv93,rsv94,rsv95,rsv96,rsv97,rsv98,rsv99,rsv100,rsv101,rsv102,rsv103,rsv104,rsv105,rsv106,rsv107,rsv108,rsv109,rsv110,rsv111,rsv112,rsv113,rsv114,rsv115,rsv116,rsv117,rsv118,rsv119,rsv120,rsv121,rsv122,rsv123,rsv124,rsv125,rsv126,rsv127,rsv128,rsv129,rsv130,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,rsv456,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x00B010B0 - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00B010B0 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x00EF1C6E - 0x073F006F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00EF1C6E - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit0-1: fuse -bit2-3: sram -bit4-5: vad -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000316 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf4100000 - - 0x0 - 0x200 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 3 - 0x80 - pll0,pll1,pll2 - PLL[%s] - no description available - 0x80 - - MFI - PLL0 multiple register - 0x0 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - MFN - PLL0 fraction numerator register - 0x4 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - MFD - PLL0 fraction demoninator register - 0x8 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - SS_STEP - PLL0 spread spectrum step register - 0xc - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - SS_STOP - PLL0 spread spectrum stop register - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - CONFIG - PLL0 confguration register - 0x14 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - LOCKTIME - PLL0 lock time register - 0x18 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - STEPTIME - PLL0 step time register - 0x1c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - ADVANCED - PLL0 advance configuration register - 0x20 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - 3 - 0x4 - DIV0,DIV1,DIV2 - DIV[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - - TSNS - TSNS - TSNS - 0xf4104000 - - 0x0 - 0x3c - registers - - - - T - Temperature - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - Maximum Temperature - 0x4 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - Minimum Temperature - 0x8 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - Sample age - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - Status - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - write-only - - - - - CONFIG - Configuration - 0x14 - 32 - 0x00600300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valid from 24-255, default 96 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, default in 3 -0: measure and return -1: twice and average -2: 4 times and average -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - Sample validity - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - Temperature flag - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - Maximum temperature to interrupt - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - Minimum temperature to interrupt - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - Maximum temperature to reset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - Minimum temperature to reset - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - Configuration in asynchronous mode - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - Polarity of internal comparator - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - Advance configuration - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - BACC - BACC - BACC - 0xf5000000 - - 0x0 - 0x10 - registers - - - - CONFIG - Access timing for access - 0x0 - 32 - 0x00000000 - 0x3000FFFF - - - FAST_WRITE - Use fast write -0: Write normally -1: boost write - 29 - 1 - read-write - - - FAST_READ - Use fast read -0: Read normally -1: boost read - 28 - 1 - read-write - - - TIMING - Time in APB clock cycles, for battery timing penerate - 0 - 16 - read-write - - - - - PRE_TIME - Timing gap before rising edge - 0x8 - 32 - 0x00000000 - 0x000FFFFF - - - PRE_RATIO - Ratio of guard band before rising edge -0: 0 -1: 1/32768 of low level width -2: 1/16384 of low level width -14: 1/4 of low level width -15: 1/2 of low level width - 16 - 4 - read-write - - - PRE_OFFSET - guard band before rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - POST_TIME - Timing gap after rising edge - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - POST_RATIO - Ratio of guard band after rising edge -0: 0 -1: 1/32768 of high level width -2: 1/16384 of high level width -14: 1/4 of high level width -15: 1/2 of high level width - 16 - 4 - read-write - - - POST_OFFSET - guard band after rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LP_MODE - Bandgap works in low power mode -0: not in low power mode -1: bandgap work in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - RTC - RTC - RTC - 0xf5044000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - 4 - 0x10 - tamp0,tamp1,tamp2,tamp3 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/SConscript deleted file mode 100644 index 5717c3e6317..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/SConscript +++ /dev/null @@ -1,25 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_batt_iomux.h deleted file mode 100644 index 42236137ac5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_batt_iomux.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BATT_IOMUX_H -#define HPM_BATT_IOMUX_H - -/* BIOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_bcfg_drv.h deleted file mode 100644 index 00dfb6fcf3c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_bcfg_drv.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BCFG_DRV_H -#define HPM_BCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_bcfg_regs.h" - -/** - * - * @brief BCFG driver APIs - * @defgroup bcfg_interface BCFG driver APIs - * @ingroup io_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable VBAT LP mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; -} - -/** - * @brief disable VBAT LP mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; -} - -/** - * @brief enable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -/** - * @brief disable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BCFG_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_bpor_drv.h deleted file mode 100644 index e37bac24b13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_bpor_drv.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BPOR_DRV_H -#define HPM_BPOR_DRV_H - -#include "hpm_common.h" -#include "hpm_bpor_regs.h" - -/** - * - * @brief BPOR driver APIs - * @defgroup bpor_interface BPOR driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -/** @brief Define BPOR power on cause */ -typedef enum { - bpor_power_on_cause_wbutn = 1 << 0, - bpor_power_on_cause_safety_violation = 1 << 1, - bpor_power_on_cause_rtc_0 = 1 << 2, - bpor_power_on_cause_rtc_1 = 1 << 3, - bpor_power_on_cause_gpio = 1 << 4 -} bpor_power_on_cause_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get power on cause - * - * @param[in] ptr BPOR base address - * @retval POR_CAUSE register value - */ -static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) -{ - return ptr->POR_CAUSE; -} - -/** - * @brief Clear power on cause - * - * @param[in] ptr BPOR base address - * @param[in] mask cause status to be cleared - */ -static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) -{ - ptr->POR_CAUSE |= mask; -} - -/** - * @brief enable power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be enabled - */ -static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) -{ - ptr->POR_SELECT |= cause; -} - -/** - * @brief disable power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be disabled - */ -static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) -{ - ptr->POR_SELECT &= ~cause; -} - -/** - * @brief Set power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be used - */ -static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) -{ - ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; -} - -/** - * @brief Enable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Disable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Set power down counter - * - * @param[in] ptr BPOR base address - * @param[in] counter counter value - */ -static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) -{ - ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_clock_drv.c deleted file mode 100644 index b92a4235c87..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_clock_drv.c +++ /dev/null @@ -1,640 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_soc.h" -#include "hpm_common.h" -#include "hpm_pllctlv2_drv.h" -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define FREQ_1MHz (1000000UL) - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (400000000UL) -#define FREQ_PRESET1_PLL0_CLK1 (333333333UL) -#define FREQ_PRESET1_PLL1_CLK2 (250000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (480000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (320000000UL) -#define FREQ_PRESET1_PLL2_CLK0 (516096000UL) -#define FREQ_PRESET1_PLL2_CLK1 (451584000UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define DAC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->DACCLK) -#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) -#define WDG_INSTANCE_NUM (4U) -#define BUS_FREQ_MAX (166000000UL) - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ - - - -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for I2S or ADC - */ -static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance); - -/** - * @brief Get Clock frequency for DAC - */ -static uint32_t get_frequency_for_dac(uint32_t instance); - -/** - * @brief Get Clock frequency for WDG - */ -static uint32_t get_frequency_for_wdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PWDG - */ -static uint32_t get_frequency_for_pwdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - -static uint32_t get_frequency_for_cpu(void); -static uint32_t get_frequency_for_axi(void); -static uint32_t get_frequency_for_ahb(void); - - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ana0, - clock_node_ahb, -}; - -static const clock_node_t s_dac_clk_mux_node[] = { - clock_node_ana3, - clock_node_ahb -}; - -static const clock_node_t s_i2s_clk_mux_node[] = { - clock_node_aud0, - clock_node_aud1, -}; - -static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1}; - -uint32_t hpm_core_clock; - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq = 0UL; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_ADC, node_or_instance); - break; - case CLK_SRC_GROUP_DAC: - clk_freq = get_frequency_for_dac(node_or_instance); - break; - case CLK_SRC_GROUP_I2S: - clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_I2S, node_or_instance); - break; - case CLK_SRC_GROUP_WDG: - clk_freq = get_frequency_for_wdg(node_or_instance); - break; - case CLK_SRC_GROUP_PWDG: - clk_freq = get_frequency_for_pwdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_CPU0: - clk_freq = get_frequency_for_cpu(); - break; - case CLK_SRC_GROUP_AHB: - clk_freq = get_frequency_for_ahb(); - break; - case CLK_SRC_GROUP_AXI: - clk_freq = get_frequency_for_axi(); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq = 0UL; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); - break; - case clock_source_pll0_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); - break; - case clock_source_pll0_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 2U); - break; - case clock_source_pll1_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); - break; - case clock_source_pll1_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); - break; - case clock_source_pll2_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); - break; - case clock_source_pll2_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - if (clk_src_type == CLK_SRC_GROUP_ADC) { - uint32_t adc_index = instance; - if (adc_index < ADC_INSTANCE_NUM) { - is_mux_valid = true; - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); - if (mux_in_reg == 1) { - node = s_adc_clk_mux_node[1]; - } else { - node = s_adc_clk_mux_node[0] + adc_index; - } - } - } else { - uint32_t i2s_index = instance; - if (i2s_index < I2S_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[i2s_index]); - if (mux_in_reg < ARRAY_SIZE(s_i2s_clk_mux_node)) { - node = s_i2s_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - } - - if (is_mux_valid) { - if (node == clock_node_ahb) { - clk_freq = get_frequency_for_ahb(); - } else { - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_dac(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - clock_node_t node = clock_node_end; - if (instance < DAC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[instance]); - if (mux_in_reg == 1) { - node = s_dac_clk_mux_node[1]; - } else { - node = s_dac_clk_mux_node[0] + instance; - } - - if (node == clock_node_ahb) { - clk_freq = get_frequency_for_ahb(); - } else { - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - - return clk_freq; -} - -static uint32_t get_frequency_for_wdg(uint32_t instance) -{ - uint32_t freq_in_hz; - /* EXT clock is chosen */ - if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_ahb(); - } - /* PCLK is chosen */ - else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_pwdg(void) -{ - uint32_t freq_in_hz; - if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_cpu(void) -{ - uint32_t mux = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - uint32_t div = SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_source(mux) / div); -} - -static uint32_t get_frequency_for_axi(void) -{ - uint32_t div = SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_cpu() / div); -} - -static uint32_t get_frequency_for_ahb(void) -{ - uint32_t div = SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]) + 1U; - return (get_frequency_for_cpu() / div); -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_DAC: - if (node_or_instance < DAC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_DAC; - clk_src_index = SYSCTL_DACCLK_MUX_GET(HPM_SYSCTL->DACCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_I2S: - if (node_or_instance < I2S_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_I2S; - clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_WDG; - clk_src_index = WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL); - } - break; - case CLK_SRC_GROUP_PWDG: - clk_src_group = CLK_SRC_GROUP_PWDG; - clk_src_index = WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_CPU0: - case CLK_SRC_GROUP_AHB: - case CLK_SRC_GROUP_AXI: - clk_src_group = CLK_SRC_GROUP_CPU0; - clk_src_index = SYSCTL_CLOCK_CPU_MUX_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -uint32_t clock_get_divider(clock_name_t clock_name) -{ - uint32_t clk_divider = CLOCK_DIV_INVALID; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_divider = 1UL; - } - break; - case CLK_SRC_GROUP_PWDG: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_PMIC: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_CPU0: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_AHB: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB1_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - case CLK_SRC_GROUP_AXI: - clk_divider = 1UL + SYSCTL_CLOCK_CPU_SUB0_DIV_GET(HPM_SYSCTL->CLOCK_CPU[0]); - break; - default: - clk_divider = CLOCK_DIV_INVALID; - break; - } - return clk_divider; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_DAC) || (node_or_instance >= DAC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_dac_src_ana3) || (src > clk_dac_src_ahb0)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->DACCLK[node_or_instance] = - (HPM_SYSCTL->DACCLK[node_or_instance] & ~SYSCTL_DACCLK_MUX_MASK) | SYSCTL_DACCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if (!((src == clk_i2s_src_aud0) || (src == clk_i2s_src_aud1))) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->I2SCLK[node_or_instance] = - (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_WDG) && (clk_src_grp != CLK_SRC_GROUP_PWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PWDG->CTRL = (HPM_PWDG->CTRL & ~WDG_CTRL_CLKSEL_MASK) | WDG_CTRL_CLKSEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL = (s_wdgs[instance]->CTRL & ~WDG_CTRL_CLKSEL_MASK) | WDG_CTRL_CLKSEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t source = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, source, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_DAC: - case CLK_SRC_GROUP_I2S: - case CLK_SRC_GROUP_WDG: - case CLK_SRC_GROUP_PWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AHB: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_AXI: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_CPU0: - if (node_or_instance == clock_node_cpu0) { - /* Note: the AXI and AHB BUS share the same CPU clock, once the CPU clock frequency - * changes, the AXI and AHB clock changes accordingly, here the driver ensures the - * AXI and AHB bus clock frequency is in valid range. - */ - clock_source_t source = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - uint32_t expected_freq = get_frequency_for_source(source) / div; - uint32_t axi_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - uint32_t ahb_sub_div = (expected_freq + BUS_FREQ_MAX - 1U) / BUS_FREQ_MAX; - sysctl_config_cpu0_domain_clock(HPM_SYSCTL, source, div, axi_sub_div, ahb_sub_div); - } else { - status = status_clk_shared_cpu0; - } - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } else if (resource == RESOURCE_SHARED_PTPC) { - sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } else if (resource == RESOURCE_SHARED_PTPC) { - sysctl_enable_group_resource(HPM_SYSCTL, group, sysctl_resource_ptpc, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - bool added = false; - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); - } else if (resource == RESOURCE_SHARED_PTPC) { - added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, sysctl_resource_ptpc); - } - return added; -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_update_core_clock(void) -{ - hpm_core_clock = clock_get_frequency(clock_cpu0); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_clock_drv.h deleted file mode 100644 index 5a31392181d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_clock_drv.h +++ /dev/null @@ -1,375 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" -#include "hpm_csr_drv.h" - -#define CLOCK_DIV_INVALID (~0UL) - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), - status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), - status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), - status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), - status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), - status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), - status_clk_fixed = MAKE_STATUS(status_group_clk, 10), - -}; - - - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_I2S (2U) -#define CLK_SRC_GROUP_WDG (3U) -#define CLK_SRC_GROUP_PMIC (4U) -#define CLK_SRC_GROUP_AHB (5U) -#define CLK_SRC_GROUP_AXI (6U) -#define CLK_SRC_GROUP_DAC (7U) -#define CLK_SRC_GROUP_CPU0 (9U) -#define CLK_SRC_GROUP_SRC (10U) -#define CLK_SRC_GROUP_PWDG (11U) -#define CLK_SRC_GROUP_INVALID (15U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll0_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - - clk_dac_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 0), - clk_dac_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_DAC, 1), - - clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - - -#define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_PTPC (0xFFFEU) -#define RESOURCE_SHARED_CPU0 (0xFFFDU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_CPU0, clock_node_cpu0), - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_femc = MAKE_CLOCK_NAME(sysctl_resource_femc, CLK_SRC_GROUP_COMMON, clock_node_femc), - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - clock_xpi1 = MAKE_CLOCK_NAME(sysctl_resource_xpi1, CLK_SRC_GROUP_COMMON, clock_node_xpi1), - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), - clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), - clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), - clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), - clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), - clock_sdxc0 = MAKE_CLOCK_NAME(sysctl_resource_sdxc0, CLK_SRC_GROUP_COMMON, clock_node_sdxc0), - clock_ntmr0 = MAKE_CLOCK_NAME(sysctl_resource_ntmr0, CLK_SRC_GROUP_COMMON, clock_node_ntmr0), - clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AHB, clock_node_ahb), - clock_axi = MAKE_CLOCK_NAME(RESOURCE_SHARED_CPU0, CLK_SRC_GROUP_AXI, clock_node_axi), - clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_AXI, clock_node_axi), - clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_AXI, clock_node_axi), - clock_ahbp = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_AHB, clock_node_ahb), - - clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), - clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_SHARED_PTPC, CLK_SRC_GROUP_COMMON, clock_node_ptp0), - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), - clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), - clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI, 0), - clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI, 1), - clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI, 2), - clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI, 3), - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI, 4), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 4), - clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 5), - clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 6), - clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 7), - clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), - clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_I2S, 0), - clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_I2S, 1), - clock_synt = MAKE_CLOCK_NAME(sysctl_resource_synt, CLK_SRC_GROUP_AHB, 13), - clock_ffa0 = MAKE_CLOCK_NAME(sysctl_resource_ffa0, CLK_SRC_GROUP_AHB, 14), - clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), - clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_CPU0, 0), - - - /* For ADC, there are 2-stage clock source and divider configurations */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), - clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), - clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), - - /* For DAC, there are 2-stage clock source and divider configurations */ - clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), - clock_dac0 = MAKE_CLOCK_NAME(sysctl_resource_dac0, CLK_SRC_GROUP_DAC, 0), - - /* For I2S, there are 2-stage clock source and divider configurations */ - clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), - clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), - clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), - clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), - clk_pll0clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll0, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 5), - clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 6), - clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 7), -} clock_name_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @param [in] clock_name clock name - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Get the IP clock divider - * Note:This API return the direct clock divider - * @param [in] clock_name clock name - * @return IP clock divider - */ -uint32_t clock_get_divider(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @return #status_success Setting ADC clock source is successful - * #status_clk_invalid Invalid ADC clock - * #status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set DAC clock source - * @param[in] clock_name DAC clock name - * @param[in] src DAC clock source - * - * @return #status_success Setting DAC clock source is successful - * #status_clk_invalid Invalid DAC clock - * #status_clk_src_invalid Invalid DAC clock source - */ -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set I2S clock source - * @param[in] clock_name I2S clock name - * @param[in] src I2S clock source - * - * @return #status_success Setting I2S clock source is successful - * #status_clk_invalid Invalid I2S clock - * #status_clk_src_invalid Invalid I2S clock source - */ -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @return #status_success Setting Clock source and divider is successful. - * #status_clk_src_invalid clock source is invalid. - * #status_clk_fixed clock source and divider is a fixed value - * #status_clk_shared_ahb Clock is shared with the AHB clock - * #status_clk_shared_axi0 Clock is shared with the AXI0 clock - * #status_clk_shared_axi1 CLock is shared with the AXI1 clock - * #status_clk_shared_axi2 Clock is shared with the AXI2 clock - * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - -/** - * @brief HPM Core clock variable - */ -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_csr_regs.h deleted file mode 100644 index 5f43b12bd1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_csr_regs.h +++ /dev/null @@ -1,6512 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_SSTATUS (0x100) -#define CSR_SEDELEG (0x102) -#define CSR_SIDELEG (0x103) -#define CSR_SIE (0x104) -#define CSR_STVEC (0x105) -#define CSR_SSCRATCH (0x140) -#define CSR_SEPC (0x141) -#define CSR_SCAUSE (0x142) -#define CSR_STVAL (0x143) -#define CSR_SIP (0x144) -#define CSR_SATP (0x180) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MEDELEG (0x302) -#define CSR_MIDELEG (0x303) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_PMACFG0 (0xBC0) -#define CSR_PMACFG1 (0xBC1) -#define CSR_PMACFG2 (0xBC2) -#define CSR_PMACFG3 (0xBC3) -#define CSR_PMAADDR0 (0xBD0) -#define CSR_PMAADDR1 (0xBD1) -#define CSR_PMAADDR2 (0xBD2) -#define CSR_PMAADDR3 (0xBD3) -#define CSR_PMAADDR4 (0xBD4) -#define CSR_PMAADDR5 (0xBD5) -#define CSR_PMAADDR6 (0xBD6) -#define CSR_PMAADDR7 (0xBD7) -#define CSR_PMAADDR8 (0xBD8) -#define CSR_PMAADDR9 (0xBD9) -#define CSR_PMAADDR10 (0xBDA) -#define CSR_PMAADDR11 (0xBDB) -#define CSR_PMAADDR12 (0xBDC) -#define CSR_PMAADDR13 (0xBDD) -#define CSR_PMAADDR14 (0xBDE) -#define CSR_PMAADDR15 (0xBDF) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_SCOUNTEREN (0x106) -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_MSLIDELEG (0x7D5) -#define CSR_MCLK_CTL (0x7DF) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_SLIE (0x9C4) -#define CSR_SLIP (0x9C5) -#define CSR_SDCAUSE (0x9C9) -#define CSR_SCCTLDATA (0x9CD) -#define CSR_SCOUNTERINTEN (0x9CF) -#define CSR_SCOUNTERMASK_M (0x9D1) -#define CSR_SCOUNTERMASK_S (0x9D2) -#define CSR_SCOUNTERMASK_U (0x9D3) -#define CSR_SCOUNTEROVF (0x9D4) -#define CSR_SCOUNTINHIBIT (0x9E0) -#define CSR_SHPMEVENT3 (0x9E3) -#define CSR_SHPMEVENT4 (0x9E4) -#define CSR_SHPMEVENT5 (0x9E5) -#define CSR_SHPMEVENT6 (0x9E6) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: SSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_SSTATUS_SD_MASK (0x80000000UL) -#define CSR_SSTATUS_SD_SHIFT (31U) -#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_SSTATUS_MXR_MASK (0x80000UL) -#define CSR_SSTATUS_MXR_SHIFT (19U) -#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) -#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_SSTATUS_SUM_MASK (0x40000UL) -#define CSR_SSTATUS_SUM_SHIFT (18U) -#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) -#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggeredwhen XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. - * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_XS_MASK (0x18000UL) -#define CSR_SSTATUS_XS_SHIFT (15U) -#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. - * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_FS_MASK (0x6000U) -#define CSR_SSTATUS_FS_SHIFT (13U) -#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) -#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_SSTATUS_SPP_MASK (0x100U) -#define CSR_SSTATUS_SPP_SHIFT (8U) -#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) -#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_SSTATUS_SPIE_MASK (0x20U) -#define CSR_SSTATUS_SPIE_SHIFT (5U) -#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) -#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_SSTATUS_UPIE_MASK (0x10U) -#define CSR_SSTATUS_UPIE_SHIFT (4U) -#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) -#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_SIE_MASK (0x2U) -#define CSR_SSTATUS_SIE_SHIFT (1U) -#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) -#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_UIE_MASK (0x1U) -#define CSR_SSTATUS_UIE_SHIFT (0U) -#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) -#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: SEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SPF_MASK (0x8000U) -#define CSR_SEDELEG_SPF_SHIFT (15U) -#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) -#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LPF_MASK (0x2000U) -#define CSR_SEDELEG_LPF_SHIFT (13U) -#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) -#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IPF_MASK (0x1000U) -#define CSR_SEDELEG_IPF_SHIFT (12U) -#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) -#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_UEC_MASK (0x100U) -#define CSR_SEDELEG_UEC_SHIFT (8U) -#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) -#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAF_MASK (0x80U) -#define CSR_SEDELEG_SAF_SHIFT (7U) -#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) -#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAM_MASK (0x40U) -#define CSR_SEDELEG_SAM_SHIFT (6U) -#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) -#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAF_MASK (0x20U) -#define CSR_SEDELEG_LAF_SHIFT (5U) -#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) -#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAM_MASK (0x10U) -#define CSR_SEDELEG_LAM_SHIFT (4U) -#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) -#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) - -/* - * B (RW) - * - * B indicates whether an exception triggered by breakpoint will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_B_MASK (0x8U) -#define CSR_SEDELEG_B_SHIFT (3U) -#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) -#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_II_MASK (0x4U) -#define CSR_SEDELEG_II_SHIFT (2U) -#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) -#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAF_MASK (0x2U) -#define CSR_SEDELEG_IAF_SHIFT (1U) -#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) -#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAM_MASK (0x1U) -#define CSR_SEDELEG_IAM_SHIFT (0U) -#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) -#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: SIDELEG */ -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UEI_MASK (0x100U) -#define CSR_SIDELEG_UEI_SHIFT (8U) -#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) -#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UTI_MASK (0x10U) -#define CSR_SIDELEG_UTI_SHIFT (4U) -#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) -#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_USI_MASK (0x1U) -#define CSR_SIDELEG_USI_SHIFT (0U) -#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) -#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) - -/* Bitfield definition for register: SIE */ -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SEIE_MASK (0x200U) -#define CSR_SIE_SEIE_SHIFT (9U) -#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) -#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UEIE_MASK (0x100U) -#define CSR_SIE_UEIE_SHIFT (8U) -#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) -#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_STIE_MASK (0x20U) -#define CSR_SIE_STIE_SHIFT (5U) -#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) -#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UTIE_MASK (0x10U) -#define CSR_SIE_UTIE_SHIFT (4U) -#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) -#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SSIE_MASK (0x2U) -#define CSR_SIE_SSIE_SHIFT (1U) -#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) -#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_USIE_MASK (0x1U) -#define CSR_SIE_USIE_SHIFT (0U) -#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) -#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) - -/* Bitfield definition for register: STVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_STVEC_BASE_31_2_SHIFT (2U) -#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) -#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: SSCRATCH */ -/* - * SSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) -#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) -#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) - -/* Bitfield definition for register: SEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_SEPC_EPC_SHIFT (1U) -#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) -#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) - -/* Bitfield definition for register: SCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) -#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 256+16:Slave port ECC error interrupt (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt(S-mode) - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:10:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) -#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: STVAL */ -/* - * STVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) -#define CSR_STVAL_STVAL_SHIFT (0U) -#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) -#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) - -/* Bitfield definition for register: SIP */ -/* - * SEIP (RO) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SEIP_MASK (0x200U) -#define CSR_SIP_SEIP_SHIFT (9U) -#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UEIP_MASK (0x100U) -#define CSR_SIP_UEIP_SHIFT (8U) -#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) -#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) - -/* - * STIP (RO) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_STIP_MASK (0x20U) -#define CSR_SIP_STIP_SHIFT (5U) -#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) - -/* - * UTIP (RO) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UTIP_MASK (0x10U) -#define CSR_SIP_UTIP_SHIFT (4U) -#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SSIP_MASK (0x2U) -#define CSR_SIP_SSIP_SHIFT (1U) -#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) -#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_USIP_MASK (0x1U) -#define CSR_SIP_USIP_SHIFT (0U) -#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) -#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) - -/* Bitfield definition for register: SATP */ -/* - * MODE (RW) - * - * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is - * not supported in the product, this CSR will be - * hardwired to 0. - * 0:No page translation - * 1:Page-based 32-bit virtual addressing - */ -#define CSR_SATP_MODE_MASK (0x80000000UL) -#define CSR_SATP_MODE_SHIFT (31U) -#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) -#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) - -/* - * ASID (RW) - * - * ASID holds the address space identifier. - */ -#define CSR_SATP_ASID_MASK (0x7FC00000UL) -#define CSR_SATP_ASID_SHIFT (22U) -#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) -#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) - -/* - * PPN (RW) - * - * PPN holds the physical page number of the root page table. - */ -#define CSR_SATP_PPN_MASK (0x3FFFFFUL) -#define CSR_SATP_PPN_SHIFT (0U) -#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) -#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * TSR (RW) - * - * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TSR_MASK (0x400000UL) -#define CSR_MSTATUS_TSR_SHIFT (22U) -#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) -#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) - -/* - * TW (RW) - * - * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TW_MASK (0x200000UL) -#define CSR_MSTATUS_TW_SHIFT (21U) -#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) -#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) - -/* - * TVM (RW) - * - * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. - * 0:Normal execution - * 1:Raising exceptions - */ -#define CSR_MSTATUS_TVM_MASK (0x100000UL) -#define CSR_MSTATUS_TVM_SHIFT (20U) -#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) -#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_MSTATUS_SUM_MASK (0x40000UL) -#define CSR_MSTATUS_SUM_SHIFT (18U) -#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) -#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_MSTATUS_SPP_MASK (0x100U) -#define CSR_MSTATUS_SPP_SHIFT (8U) -#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) -#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_MSTATUS_SPIE_MASK (0x20U) -#define CSR_MSTATUS_SPIE_SHIFT (5U) -#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) -#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_SIE_MASK (0x2U) -#define CSR_MSTATUS_SIE_SHIFT (1U) -#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) -#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SPF_MASK (0x8000U) -#define CSR_MEDELEG_SPF_SHIFT (15U) -#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) -#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LPF_MASK (0x2000U) -#define CSR_MEDELEG_LPF_SHIFT (13U) -#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) -#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IPF_MASK (0x1000U) -#define CSR_MEDELEG_IPF_SHIFT (12U) -#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) -#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) - -/* - * SEC (RW) - * - * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SEC_MASK (0x200U) -#define CSR_MEDELEG_SEC_SHIFT (9U) -#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) -#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_UEC_MASK (0x100U) -#define CSR_MEDELEG_UEC_SHIFT (8U) -#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) -#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAF_MASK (0x80U) -#define CSR_MEDELEG_SAF_SHIFT (7U) -#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) -#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAM_MASK (0x40U) -#define CSR_MEDELEG_SAM_SHIFT (6U) -#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) -#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAF_MASK (0x20U) -#define CSR_MEDELEG_LAF_SHIFT (5U) -#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) -#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAM_MASK (0x10U) -#define CSR_MEDELEG_LAM_SHIFT (4U) -#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) -#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_II_MASK (0x4U) -#define CSR_MEDELEG_II_SHIFT (2U) -#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) -#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAF_MASK (0x2U) -#define CSR_MEDELEG_IAF_SHIFT (1U) -#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) -#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAM_MASK (0x1U) -#define CSR_MEDELEG_IAM_SHIFT (0U) -#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) -#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: MIDELEG */ -/* - * SEI (RW) - * - * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SEI_MASK (0x200U) -#define CSR_MIDELEG_SEI_SHIFT (9U) -#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) -#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) - -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UEI_MASK (0x100U) -#define CSR_MIDELEG_UEI_SHIFT (8U) -#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) -#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) - -/* - * STI (RW) - * - * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_STI_MASK (0x20U) -#define CSR_MIDELEG_STI_SHIFT (5U) -#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) -#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UTI_MASK (0x10U) -#define CSR_MIDELEG_UTI_SHIFT (4U) -#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) -#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) - -/* - * SSI (RW) - * - * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SSI_MASK (0x2U) -#define CSR_MIDELEG_SSI_SHIFT (1U) -#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) -#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_USI_MASK (0x1U) -#define CSR_MIDELEG_USI_SHIFT (0U) -#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) -#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SEIE_MASK (0x200U) -#define CSR_MIE_SEIE_SHIFT (9U) -#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) -#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_STIE_MASK (0x20U) -#define CSR_MIE_STIE_SHIFT (5U) -#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) -#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SSIE_MASK (0x2U) -#define CSR_MIE_SSIE_SHIFT (1U) -#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) -#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_MCONTROL_S_MASK (0x10U) -#define CSR_MCONTROL_S_SHIFT (4U) -#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) -#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ICOUNT_S_MASK (0x80U) -#define CSR_ICOUNT_S_SHIFT (7U) -#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) -#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ITRIGGER_S_MASK (0x80U) -#define CSR_ITRIGGER_S_SHIFT (7U) -#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) -#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ETRIGGER_S_MASK (0x80U) -#define CSR_ETRIGGER_S_SHIFT (7U) -#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) -#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKS (RW) - * - * This bit controls the behavior of EBREAK instructions in Supervisor Mode. - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKS_MASK (0x2000U) -#define CSR_DCSR_EBREAKS_SHIFT (13U) -#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) -#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: PMACFG0 */ -/* - * PMA3CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) -#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) -#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) -#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) - -/* - * PMA2CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) -#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) -#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) -#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) - -/* - * PMA1CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) -#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) -#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) -#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) - -/* - * PMA0CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) -#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) -#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) -#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) - -/* Bitfield definition for register: PMACFG1 */ -/* - * PMA7CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) -#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) -#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) -#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) - -/* - * PMA6CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) -#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) -#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) -#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) - -/* - * PMA5CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) -#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) -#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) -#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) - -/* - * PMA4CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) -#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) -#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) -#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) - -/* Bitfield definition for register: PMACFG2 */ -/* - * PMA11CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) -#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) -#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) -#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) - -/* - * PMA10CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) -#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) -#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) -#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) - -/* - * PMA9CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) -#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) -#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) -#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) - -/* - * PMA8CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) -#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) -#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) -#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) - -/* Bitfield definition for register: PMACFG3 */ -/* - * PMA15CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) -#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) -#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) -#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) - -/* - * PMA14CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) -#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) -#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) -#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) - -/* - * PMA13CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) -#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) -#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) -#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) - -/* - * PMA12CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) -#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) -#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) -#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaaaaaaaaaa Reserved - * . . . . . . - * aaaa. . . aa011111111 Reserved - * aaaa. . . a0111111111 2^{12} - * aaaa. . . 01111111111 2^{13} - * . . . . . . - * aa01. . . 11111111111 2^{XLEN} - * a011. . . 11111111111 2^{XLEN+1} - * 0111. . . 11111111111 2^{XLEN+2} - * 1111. . . 11111111111 Reserved - */ -#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) -#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) -#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) -#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) -#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) -#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) -#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) -#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) -#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) -#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) -#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) -#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) -#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) -#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) -#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) -#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) -#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: SCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) -#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) -#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) -#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) -#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_IR_MASK (0x4U) -#define CSR_SCOUNTEREN_IR_SHIFT (2U) -#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) -#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_CY_MASK (0x1U) -#define CSR_SCOUNTEREN_CY_SHIFT (0U) -#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) -#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * PM (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MDCAUSE_PM_MASK (0x60U) -#define CSR_MDCAUSE_PM_SHIFT (5U) -#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) -#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) - -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * DC_WAROUND (RW) - * - * Cache Write-Around threshold - * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. - * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. - * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. - * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. - */ -#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) -#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) -#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) -#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) - -/* - * DC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) - -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * DPREF_EN (RW) - * - * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 - * 0:Disable hardware prefetch on load/store memory accesses - * 1:Enable hardware prefetch on load/store memory accesses - */ -#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) -#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) -#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) -#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) - -/* - * IPREF_EN (RW) - * - * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 - * 0:Disable hardware prefetch on instruction fetches - * 1:Enable hardware prefetch on instruction fetches - */ -#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) -#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) -#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) -#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * NBLD_EN (RW) - * - * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. - * 0:Load to memory regions are blocking. - * 1:Load to memory regions are non-blocking. - */ -#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) -#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) -#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) -#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) - -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: MSLIDELEG */ -/* - * PMOVI (RW) - * - * Delegate S-mode performance monitor overflow local interrupt to S-mode. - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) -#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) -#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) -#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Delegate S-mode bus read/write transaction error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) -#define CSR_MSLIDELEG_BWEI_SHIFT (17U) -#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) -#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Delegate S-mode slave-port ECC error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) -#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) -#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) -#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) - -/* Bitfield definition for register: MCLK_CTL */ -/* - * FUNIT (RW) - * - * Level 2 clock gating enable for function units listed in the following table. - * 16:integer arithmetic unit - * 17:integer permutation unit - * 18:integer mask unit - * 19:integer division unit - * 20:integer multiply and add unit - * 21:floating-point multiply and add - * unit - * 22:floating-point miscellaneous unit - * 23:floating-point division unit - * 24:load/store unit - * 31:25:Reserved - */ -#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) -#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) -#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) -#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) - -/* - * VI (RW) - * - * Level 1 clock gating enable for the vector/floating-point issue queues. - */ -#define CSR_MCLK_CTL_VI_MASK (0x8000U) -#define CSR_MCLK_CTL_VI_SHIFT (15U) -#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) -#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) - -/* - * VR (RW) - * - * Level 1 clock gating enable for the vector/floating-point register file. - */ -#define CSR_MCLK_CTL_VR_MASK (0x4000U) -#define CSR_MCLK_CTL_VR_SHIFT (14U) -#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) -#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) - -/* - * AQ (RW) - * - * Level 1 clock gating enable for ACE load/store queues. - */ -#define CSR_MCLK_CTL_AQ_MASK (0x2000U) -#define CSR_MCLK_CTL_AQ_SHIFT (13U) -#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) -#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) - -/* - * DQ (RW) - * - * Level 1 clock gating enable for data cache load/store queues. - */ -#define CSR_MCLK_CTL_DQ_MASK (0x1000U) -#define CSR_MCLK_CTL_DQ_SHIFT (12U) -#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) -#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) - -/* - * UQ (RW) - * - * Level 1 clock gating enable for uncached queues - */ -#define CSR_MCLK_CTL_UQ_MASK (0x800U) -#define CSR_MCLK_CTL_UQ_SHIFT (11U) -#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) -#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) - -/* - * FP (RW) - * - * Level 1 clock gating enable for scalar floating point issue unit and queues. - */ -#define CSR_MCLK_CTL_FP_MASK (0x400U) -#define CSR_MCLK_CTL_FP_SHIFT (10U) -#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) -#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) - -/* - * CLKGATE (RW) - * - * One-hot clock gating levels. - * 0:Level 1 clock gating in module level - * 1:Level 2 clock gating in unit level - * 2:Level 3 clock gating in VPU level - * 7:3:Reserved - */ -#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) -#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) -#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) -#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * SPF (RW) - * - * Indicates whether store page fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) -#define CSR_DEXC2DBG_SPF_SHIFT (18U) -#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) -#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) - -/* - * LPF (RW) - * - * Indicates whether load fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) -#define CSR_DEXC2DBG_LPF_SHIFT (17U) -#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) -#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) - -/* - * IPF (RW) - * - * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) -#define CSR_DEXC2DBG_IPF_SHIFT (16U) -#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) -#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * SEC (RW) - * - * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SEC_MASK (0x200U) -#define CSR_DEXC2DBG_SEC_SHIFT (9U) -#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) -#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: SLIE */ -/* - * PMOVI (RW) - * - * Enable S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_PMOVI_MASK (0x40000UL) -#define CSR_SLIE_PMOVI_SHIFT (18U) -#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) -#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_BWEI_MASK (0x20000UL) -#define CSR_SLIE_BWEI_SHIFT (17U) -#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) -#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Enable S-mode slave-port ECC error local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_IMECCI_MASK (0x10000UL) -#define CSR_SLIE_IMECCI_SHIFT (16U) -#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) -#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) - -/* Bitfield definition for register: SLIP */ -/* - * PMOVI (RW) - * - * Pending control and status of S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_PMOVI_MASK (0x40000UL) -#define CSR_SLIP_PMOVI_SHIFT (18U) -#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) -#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_BWEI_MASK (0x20000UL) -#define CSR_SLIP_BWEI_SHIFT (17U) -#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) -#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Pending control and status of S-mode slave-port ECC error local interrupt.. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_IMECCI_MASK (0x10000UL) -#define CSR_SLIP_IMECCI_SHIFT (16U) -#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) -#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) - -/* Bitfield definition for register: SDCAUSE */ -/* - * PM (RW) - * - * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0:User mode - * 1:Supervisor mode - * 2:Reserved - * 3:Machine mode - */ -#define CSR_SDCAUSE_PM_MASK (0x60U) -#define CSR_SDCAUSE_PM_SHIFT (5U) -#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) -#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) - -/* - * SDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. - * The value of SDCAUSE for precise exception: - * When scause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When scause == 2 (Illegal instruction): - * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When scause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When scause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of SDCAUSE for imprecise exception: - * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) -#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) -#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) -#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) - -/* Bitfield definition for register: SCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_SCCTLDATA_VA_MASK (0x1FU) -#define CSR_SCCTLDATA_VA_SHIFT (0U) -#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) -#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: SCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) -#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) -#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) -#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) -#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) -#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) -#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) -#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) -#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) -#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) -#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) -#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) -#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) -#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) -#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) -#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) -#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) -#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) -#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) -#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) -#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) -#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) -#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) -#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) -#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) -#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) -#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) -#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) -#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_IR_MASK (0x4U) -#define CSR_SCOUNTEROVF_IR_SHIFT (2U) -#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) -#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_CY_MASK (0x1U) -#define CSR_SCOUNTEROVF_CY_SHIFT (0U) -#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) -#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) -#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) -#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) -#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) -#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) -#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) -#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) -#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: SHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT3_SEL_SHIFT (4U) -#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) -#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) -#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT4_SEL_SHIFT (4U) -#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) -#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) -#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT5_SEL_SHIFT (4U) -#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) -#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) -#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT6_SEL_SHIFT (4U) -#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) -#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) -#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_dmamux_src.h deleted file mode 100644 index b0ed97d8e5f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_dmamux_src.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_SPI0_RX (0x0UL) -#define HPM_DMA_SRC_SPI0_TX (0x1UL) -#define HPM_DMA_SRC_SPI1_RX (0x2UL) -#define HPM_DMA_SRC_SPI1_TX (0x3UL) -#define HPM_DMA_SRC_SPI2_RX (0x4UL) -#define HPM_DMA_SRC_SPI2_TX (0x5UL) -#define HPM_DMA_SRC_SPI3_RX (0x6UL) -#define HPM_DMA_SRC_SPI3_TX (0x7UL) -#define HPM_DMA_SRC_UART0_RX (0x8UL) -#define HPM_DMA_SRC_UART0_TX (0x9UL) -#define HPM_DMA_SRC_UART1_RX (0xAUL) -#define HPM_DMA_SRC_UART1_TX (0xBUL) -#define HPM_DMA_SRC_UART2_RX (0xCUL) -#define HPM_DMA_SRC_UART2_TX (0xDUL) -#define HPM_DMA_SRC_UART3_RX (0xEUL) -#define HPM_DMA_SRC_UART3_TX (0xFUL) -#define HPM_DMA_SRC_UART4_RX (0x10UL) -#define HPM_DMA_SRC_UART4_TX (0x11UL) -#define HPM_DMA_SRC_UART5_RX (0x12UL) -#define HPM_DMA_SRC_UART5_TX (0x13UL) -#define HPM_DMA_SRC_UART6_RX (0x14UL) -#define HPM_DMA_SRC_UART6_TX (0x15UL) -#define HPM_DMA_SRC_UART7_RX (0x16UL) -#define HPM_DMA_SRC_UART7_TX (0x17UL) -#define HPM_DMA_SRC_I2S0_RX (0x18UL) -#define HPM_DMA_SRC_I2S0_TX (0x19UL) -#define HPM_DMA_SRC_I2S1_RX (0x1AUL) -#define HPM_DMA_SRC_I2S1_TX (0x1BUL) -#define HPM_DMA_SRC_MOT0_0 (0x1CUL) -#define HPM_DMA_SRC_MOT0_1 (0x1DUL) -#define HPM_DMA_SRC_MOT0_2 (0x1EUL) -#define HPM_DMA_SRC_MOT0_3 (0x1FUL) -#define HPM_DMA_SRC_MOT1_0 (0x20UL) -#define HPM_DMA_SRC_MOT1_1 (0x21UL) -#define HPM_DMA_SRC_MOT1_2 (0x22UL) -#define HPM_DMA_SRC_MOT1_3 (0x23UL) -#define HPM_DMA_SRC_NTMR0_0 (0x24UL) -#define HPM_DMA_SRC_NTMR0_1 (0x25UL) -#define HPM_DMA_SRC_NTMR0_2 (0x26UL) -#define HPM_DMA_SRC_NTMR0_3 (0x27UL) -#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) -#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) -#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) -#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) -#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) -#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) -#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) -#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) -#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) -#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) -#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) -#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) -#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) -#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) -#define HPM_DMA_SRC_I2C0 (0x38UL) -#define HPM_DMA_SRC_I2C1 (0x39UL) -#define HPM_DMA_SRC_I2C2 (0x3AUL) -#define HPM_DMA_SRC_I2C3 (0x3BUL) -#define HPM_DMA_SRC_XPI0_RX (0x3CUL) -#define HPM_DMA_SRC_XPI0_TX (0x3DUL) -#define HPM_DMA_SRC_XPI1_RX (0x3EUL) -#define HPM_DMA_SRC_XPI1_TX (0x3FUL) -#define HPM_DMA_SRC_DAC (0x40UL) -#define HPM_DMA_SRC_ACMP_0 (0x41UL) -#define HPM_DMA_SRC_ACMP_1 (0x42UL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_enet_soc_drv.h deleted file mode 100644 index 688c6970c16..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_enet_soc_drv.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ENET_SOC_DRV_H -#define HPM_ENET_SOC_DRV_H - -#include "hpm_soc.h" - -#if defined __cplusplus -extern "C" { -#endif - -static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; - ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 |= ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) -{ - (void) ptr; - (void) tx_delay; - (void) rx_delay; - hpm_stat_t stat = status_fail; - - return stat; -} - -static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) -{ - hpm_stat_t stat = status_success; - - /* use an internal PLL clock as reference clock for rmii mode */ - if (ptr == HPM_ENET0) { - if (internal == true) { - /* use a pll clock */ - ptr->CTRL2 |= ENET_CTRL2_ENET0_REFCLK_OE_MASK | ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else { - /* use an external clock as reference clock for rmii mode */ - ptr->CTRL2 |= ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ - } - } else { - return status_invalid_argument; - } - - return stat; -} - -#if defined __cplusplus -} /* __cplusplus */ -#endif - -#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_gpiom_soc_drv.h deleted file mode 100644 index be5605892a4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_core0_fast = 1, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_interrupt.h deleted file mode 100644 index 57c7e86b1e4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_interrupt.h +++ /dev/null @@ -1,1206 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Delegate IRQ handling - * - * @param[in] mask interrupt mask to be delegated - */ -ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) -{ - set_csr(CSR_MIDELEG, mask); -} - -/** - * @brief Undelegate IRQ handling - * - * @param[in] mask interrupt mask to be undelegated - */ -ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) -{ - clear_csr(CSR_MIDELEG, mask); -} - - -/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ - -/** - * @brief Enable global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return sstatus for supervisor mode - * - * @param[in] mask interrupt mask to be disabled - * @retval current sstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) -{ - set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ for supervisor mode - */ -ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) -{ - set_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) -{ - clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - - - -/* Supervisor mode */ - -/** - * @brief Enable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) -{ - set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Disable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Trigger software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) -{ - set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - - -/** - * @brief Complete software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) -{ - clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - -/* - * @brief Enable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Disable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -#define intc_set_s_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) - -/* - * @brief Complete IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Claim IRQ for supervisor mode - * - */ -#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) - -/* - * @brief Enable IRQ for supervisor mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_s_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_s_enable_irq(irq); \ - } while (0) - - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* Supervisor mode */ -extern int __vector_s_table[]; -extern void default_s_irq_entry(void); -/** - * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) -{ - __vector_s_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) -{ - __vector_s_table[irq] = (int) default_s_irq_entry; -} - - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else /*__riscv_flen == 64*/ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - - -#define ENTER_NESTED_IRQ_HANDLING_S() {\ - __asm volatile("\n\ - csrr s2, sepc \n\ - csrr s3, sstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi sstatus, 2"); \ -} -#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("csrci sstatus, 2"); \ - __asm volatile("lui a4, 0xe4201"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling at supervisor mode - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * SCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * SSTATUS = word offset 18 - */ -#define EXIT_NESTED_IRQ_HANDLING_S() { \ - __asm volatile("\n\ - csrw sstatus, s3 \n\ - csrw sepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define EXTERN_C extern "C" -#else -#define EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -#define ISR_NAME_S(irq_num) default_isr_s_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void ISR_NAME_S(irq_num)(void) {\ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_S();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_S(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_S();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("sret\n");\ -} - -#endif -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) { \ - isr(); \ -} - -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_S(irq_num)(void) { \ - isr(); \ -} - -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) {\ - isr();\ -} - -/* Supervisor mode */ - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_s_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR_S(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_s_isr(void) {\ - isr();\ -} - -#define CSR_MSTATUS_MPP_S_MODE (0x1) -#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ -do { \ - if (label) { \ - write_csr(mepc, label); \ - } \ - clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ - set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ -} while(0) - -typedef void (*s_mode_entry)(void); - -/** - * @brief Switch mode to supervisor from machine - * - * @param[in] entry - entry point after mode is switched - */ -static inline void switch_to_s_mode(s_mode_entry entry) -{ - write_csr(CSR_SEPC, entry); - MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); - if (entry) { - __asm("mret"); - } -} -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_iomux.h deleted file mode 100644 index 1a02f60cd65..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_iomux.h +++ /dev/null @@ -1,956 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA00_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA01_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA03_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA04_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA05_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA06_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA07_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA08_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA08_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA09_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA10_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA11_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA12_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA12_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA13_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA13_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA13_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA13_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA14_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA14_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA14_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA14_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA15_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA15_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA15_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA16_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA16_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA16_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA16_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA17_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA17_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA18_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA18_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA19_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA20_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA20_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA21_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA22_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA22_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA23_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA23_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_FEMC_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA24_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA25_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA26_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA26_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA26_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA27_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA27_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA28_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB00_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB01_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB02_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB03_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB04_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB05_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB07_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB08_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB09_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB10_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB11_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB12_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB12_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB13_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB13_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB14_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB15_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB16_FUNC_CTL function mux definitions */ -#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB16_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB16_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB17_FUNC_CTL function mux definitions */ -#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB17_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB17_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB18_FUNC_CTL function mux definitions */ -#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB18_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB18_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB19_FUNC_CTL function mux definitions */ -#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB19_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB19_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB20_FUNC_CTL function mux definitions */ -#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB20_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB20_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB21_FUNC_CTL function mux definitions */ -#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB21_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB22_FUNC_CTL function mux definitions */ -#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB22_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB22_FUNC_CTL_FEMC_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB23_FUNC_CTL function mux definitions */ -#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB23_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB23_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB24_FUNC_CTL function mux definitions */ -#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB24_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB24_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB25_FUNC_CTL function mux definitions */ -#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB25_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB25_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB26_FUNC_CTL function mux definitions */ -#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB26_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB26_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB27_FUNC_CTL function mux definitions */ -#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB27_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB27_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB28_FUNC_CTL function mux definitions */ -#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB28_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB28_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB29_FUNC_CTL function mux definitions */ -#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB29_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB29_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB30_FUNC_CTL function mux definitions */ -#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB30_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB30_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB31_FUNC_CTL function mux definitions */ -#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB31_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB31_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC00_FUNC_CTL function mux definitions */ -#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC00_FUNC_CTL_FEMC_SRDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC01_FUNC_CTL function mux definitions */ -#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC01_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC02_FUNC_CTL function mux definitions */ -#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC02_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC03_FUNC_CTL function mux definitions */ -#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC03_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC03_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC04_FUNC_CTL function mux definitions */ -#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC04_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC04_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC04_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC05_FUNC_CTL function mux definitions */ -#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC05_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC05_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC05_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC06_FUNC_CTL function mux definitions */ -#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC06_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC06_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC07_FUNC_CTL function mux definitions */ -#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC07_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC07_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC07_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC08_FUNC_CTL function mux definitions */ -#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC08_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC08_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC09_FUNC_CTL function mux definitions */ -#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC09_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC09_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC10_FUNC_CTL function mux definitions */ -#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC10_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC10_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC10_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC11_FUNC_CTL function mux definitions */ -#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC11_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC11_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC11_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC12_FUNC_CTL function mux definitions */ -#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC12_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC12_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC12_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC13_FUNC_CTL function mux definitions */ -#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC13_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC13_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PC14_FUNC_CTL function mux definitions */ -#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC14_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC14_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC15_FUNC_CTL function mux definitions */ -#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC16_FUNC_CTL function mux definitions */ -#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC16_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PC17_FUNC_CTL function mux definitions */ -#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC17_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC17_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC18_FUNC_CTL function mux definitions */ -#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC18_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC19_FUNC_CTL function mux definitions */ -#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC19_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC19_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PC20_FUNC_CTL function mux definitions */ -#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC20_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC20_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC20_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC21_FUNC_CTL function mux definitions */ -#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC21_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC21_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC21_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC22_FUNC_CTL function mux definitions */ -#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC22_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC22_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC22_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC22_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC23_FUNC_CTL function mux definitions */ -#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC23_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC23_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC23_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC24_FUNC_CTL function mux definitions */ -#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC24_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC24_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC25_FUNC_CTL function mux definitions */ -#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC25_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC26_FUNC_CTL function mux definitions */ -#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC26_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC26_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC26_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC27_FUNC_CTL function mux definitions */ -#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC27_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PC27_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC27_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PX07_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY04_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY05_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY06_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY07_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_l1c_drv.h deleted file mode 100644 index 1f1a21639a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 32KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 64B */ -#define HPM_L1C_CACHELINE_SIZE (64) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_misc.h deleted file mode 100644 index e81a74fa29f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_misc.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define ILM_LOCAL_BASE (0x0U) -#define ILM_SIZE_IN_BYTE (0x40000U) -#define DLM_LOCAL_BASE (0x80000U) -#define DLM_SIZE_IN_BYTE (0x40000U) -#define CORE0_ILM_SYSTEM_BASE (0x1040000U) -#define CORE0_DLM_SYSTEM_BASE (0x1060000U) -#define CORE1_ILM_SYSTEM_BASE (0x1180000U) -#define CORE1_DLM_SYSTEM_BASE (0x11C0000U) - -#define ADDRESS_IN_ILM(address) \ - ((ILM_LOCAL_BASE) <= (address)) && \ - ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_DLM(address) \ - ((DLM_LOCAL_BASE) <= (address)) && \ - ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) - -#define DLM_TO_SYSTEM(address) \ - (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) -#define ILM_TO_SYSTEM(address) \ - (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) -#define SYSTEM_TO_DLM(address) \ - ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) - -#define HPM_CORE0 (0U) -#define HPM_CORE1 (1U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_otp_drv.c deleted file mode 100644 index dbab2999552..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - /* Wait until LDO is ready */ - while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { - } - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_otp_drv.h deleted file mode 100644 index b61c805a1df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_otp_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - -/** - * @brief Initialize OTP controller - */ -void otp_init(void); - -/** - * @brief De-initialize OTP controller - */ -void otp_deinit(void); - -/** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_shadow(uint32_t addr); - -/** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_ip(uint32_t addr); - -/** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - -/** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ -hpm_stat_t otp_reload(otp_region_t region); - -/** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - -/** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [in] val Data to be written - * @return API execution status - */ -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_pcfg_drv.h deleted file mode 100644 index c5f8de4b942..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_pcfg_drv.h +++ /dev/null @@ -1,617 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_fuse = 0, - pcfg_pmc_periph_ram = 2, - pcfg_pmc_periph_vad = 4, - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, - pcfg_pmc_periph_debug = 16, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) -#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) -#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) -#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap enable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief bandgap enable low power mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - * @param[in] over_limit unused parameter, will be discarded - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) -{ - (void) over_limit; - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - -/** - * @brief disable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief enable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/** - * @brief Disable CPU0 debug stop notficiation to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; -} - -/** - * @brief Enable CPU0 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; -} - -/** - * @brief Disable CPU1 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; -} - -/** - * @brief Enable CPU1 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; -} - -/** - * @brief Configure CPU core debug stop notification to peripherals - * - * @param[in] ptr - * @param[in] mask - */ -static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) -{ - ptr->DEBUG_STOP = mask; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_plic_drv.h deleted file mode 100644 index 9595051f906..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_plic_drv.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_pmic_iomux.h deleted file mode 100644 index 5bd62a86bfa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_pmic_iomux.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ppor_drv.h deleted file mode 100644 index 687508cc684..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ppor_drv.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_wdog2 = 1 << 18, - ppor_reset_wdog3 = 1 << 19, - ppor_reset_pmic_wdog = 1 << 20, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_COLD |= mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_COLD &= ~mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOT |= mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOT &= ~mask; -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_romapi.h deleted file mode 100644 index d814cc27647..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_romapi.h +++ /dev/null @@ -1,1089 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_sdp_drv.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ -/* XPI1 base address */ -#define HPM_XPI1_BASE (0xF3044000UL) /**< XPI1 Base address */ -/* XPI1 base pointer */ -#define HPM_XPI1 ((XPI_Type *) HPM_XPI1_BASE) /**< XPI1 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -typedef struct { - uint32_t _internal[138]; -} sm3_context_t; - - -#define SM4_ENCRYPT 1 -#define SM4_DECRYPT 0 - -typedef struct { - uint32_t mode; - uint32_t _internal[116]; -} sm4_context_t; - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, - uint32_t serial_root_clk_freq, - uint32_t data_valid_time, - xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t - (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t - (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t - (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t - (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t - (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t - (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief XPI RAM driver interface - */ -typedef struct { - /**< XPI RAM driver interface: API version */ - uint32_t version; - - /**< Get XPI RAM configuration based on cfg_option */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); - - /**< XPI RAM driver interface: Initialize XPI RAM */ - hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); -} xpi_ram_driver_interface_t; - -/** - * @brief SDP API interface - */ -typedef struct { - /**< SDP API interface: API version */ - uint32_t version; - /**< SDP API interface: Initialize IP */ - hpm_stat_t (*sdp_ip_init)(void); - /**< SDP API interface: Deinitialize IP */ - hpm_stat_t (*sdp_ip_deinit)(void); - /**< SDP API interface: Set AES key */ - hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: AES ECB crypto operation */ - hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API interface: AES CBC crypto operation */ - hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API interface: AES CTR crypto operation */ - hpm_stat_t - (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API interface: AES CCM encryption */ - hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: AES CCM Decrypt and verify */ - hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: memcpy */ - hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); - /**< SDP API interface: memset */ - hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); - /**< SDP API interface: HASH initialization */ - hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - /**< SDP API interface: HASH update */ - hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - /**< SDP API interface: HASH finish */ - hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); -} sdp_driver_interface_t; - -typedef struct { - /**< SM3 API version*/ - uint32_t version; - /**< SM3 API itnerface: HASH Initialization */ - hpm_stat_t (*init)(sm3_context_t *ctx); - /**< SM3 API interface: HASH update */ - hpm_stat_t (*update)(sm3_context_t *ctx, const void *input, uint32_t len); - /**< SM3 API interface: HASH finish */ - hpm_stat_t (*finalize)(sm3_context_t *ctx, uint8_t output[32]); -} sm3_api_interface_t; - -typedef struct { - /**< SM4 API interface: Version */ - uint32_t version; - /**< SM4 API interface: Set encryption key */ - void (*setkey_enc)(sm4_context_t *ctx, const uint8_t key[16]); - /**< SM4 API interface: Set decryption key */ - void (*setkey_dec)(sm4_context_t *ctx, const uint8_t key[16]); - /**< SM4 API interface: SM4 ECB operation */ - hpm_stat_t (*crypt_ecb)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output); - /**< SM4 API interface: SM4 CBC operation */ - hpm_stat_t (*crypt_cbc)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], - const uint8_t *input, uint8_t *output); - /**< SM4 API interface: SM4 CTR operation */ - hpm_stat_t (*crypt_ctr)(sm4_context_t *ctx, uint8_t *nonce_counter, const uint8_t *input, - uint8_t *output, uint32_t length); - /**< SM4 API interface: SM4 CCB encryption */ - hpm_stat_t (*ccm_gen_enc)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, uint8_t *tag, uint32_t tag_len); - /**< SM4 API interface: SM4 CCM Decryption and verifying */ - hpm_stat_t (*ccm_dec_verify)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len); -} sm4_api_interface_t; - - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const xpi_ram_driver_interface_t *xpi_ram_driver_if; - /**< Bootloader API table: sdp driver interface address */ - const sdp_driver_interface_t *sdp_driver_if; - const uint32_t reserved0; - const sm3_api_interface_t *sm3_api_if; /* SM3 driver interface address */ - const sm4_api_interface_t *sm4_api_if; /* SM4 driver itnerface address */ -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t*)0x2001FF00U) - - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); - fencei(); - return status; -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); - fencei(); - return status; -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if - ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API exection address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, - xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) - || ((offset & 0xFFF) != 0)) { - return false; - } - static const uint8_t k_mc_xpi_remap_config[] = { - 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, - 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, - 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, - }; - typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); - remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; - bool result = cb(base, start, len, offset); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_disable[] = { - 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, - 0xf5, 0x42, 0x82, 0x80, - }; - typedef void (*remap_disable_cb_t)(XPI_Type *); - remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; - cb(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_enabled[] = { - 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, - }; - typedef bool (*remap_chk_cb_t)(XPI_Type *); - remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; - return chk_cb(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - if (base != HPM_XPI0) { - return false; - } - static const uint8_t k_mc_exip_region_config[] = { - 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, - 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, - 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, - 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, - 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, - 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, - 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, - 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, - 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, - }; - typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); - exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; - cb(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return true; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - static const uint8_t k_mc_exip_region_disable[] = { - 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, - 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, - 0xe7, 0xd0, 0x82, 0x80 - }; - typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); - exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; - cb(base, index); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_enable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, - 0xf5, 0xc0, 0x82, 0x80 - }; - typedef void (*exip_enable_cb_t)(XPI_Type *); - exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; - cb(base); -} - -/** - * @brief Disable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_disable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, - 0x82, 0x80 - }; - typedef void (*exip_disable_cb_t)(XPI_Type *); - exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; - cb(base); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/*********************************************************************************************************************** - * - * - * XPI RAM Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Get XPI RAM configuration based on cfg_option - * @param [in] base XPI base address - * @param [out] ram_cfg XPI RAM configuration structure - * @param [in] cfg_option XPI RAM configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, - xpi_ram_config_t *ram_cfg, - xpi_ram_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); -} - -/** - * @brief Initialize XPI RAM - * @param [in] base XPI base address - * @param [in] ram_cfg XPI ram configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); -} - -/*********************************************************************************************************************** - * - * - * SDP Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Initialize SDP IP - */ -static inline void rom_sdp_init(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); -} - -/** - * @brief De-initialize SDP IP - */ -static inline void rom_sdp_deinit(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); -} - -/** - * @brief Set AES key to SDP - * @param [in] aes_ctx AES context - * @param [in] key AES key buffer - * @param [in] key_bits AES key-bit option - * @param[in] key_idx AES key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] len Data length for AES encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] length Data length for AES encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); -} - -/** - * @brief HASH initialization - * @param [in] hash_ctx HASH context - * @param [in] alg HASH algorithm - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); -} - -/** - * @brief HASH Update - * @param [in] hash_ctx HASH context - * @param [in] data Data for HASH operation - * @param [in] length of the data for HASH operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); -} - -/** - * @brief HASH finialize - * @param [in] hash_ctx HASH context - * @param [out] digest the output digest - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); -} - -/** - * @brief SDP memcpy operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memcpy - * @param [in] src Source address for memcpy - * @param [in] length Size of data for memcpy operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); -} - -/** - * @brief SDP memset operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memset - * @param [in] pattern pattern for memset - * @param [in] length Size of data for memset operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); -} - - -/*********************************************************************************************************************** - * - * - * SM3 Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief SM4 initialization - * - * @param [in] ctx SM3 context - * @return API execution status - */ -static inline hpm_stat_t rom_sm3_init(sm3_context_t *ctx) -{ - return ROM_API_TABLE_ROOT->sm3_api_if->init(ctx); -} - -/** - * @brief SM3 update operation - * - * @param [in,out] ctx SM3 context - * @param [in] input Data for SM3 calculation - * @param [in] len length of the data for SM3 calculation - * @return API execution status - */ -static inline hpm_stat_t rom_sm3_update(sm3_context_t *ctx, const void *input, uint32_t len) -{ - return ROM_API_TABLE_ROOT->sm3_api_if->update(ctx, input, len); -} - -/** - * @brief SM3 finalize - * Return the computing SM3 digest - * - * @param [in] ctx SM3 context - * @param [out] output SM3 digest calculated by the above API - * @return API execution status - */ -static inline hpm_stat_t rom_sm3_finalize(sm3_context_t *ctx, uint8_t output[32]) -{ - return ROM_API_TABLE_ROOT->sm3_api_if->finalize(ctx, output); -} - -/*********************************************************************************************************************** - * - * - * SM4 Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Set SM4 encryption key - * - * @param [in] ctx SM4 context - * @param [in] key SM4 encryption key - */ -static inline void rom_sm4_setkey_enc(sm4_context_t *ctx, const uint8_t key[16]) -{ - ROM_API_TABLE_ROOT->sm4_api_if->setkey_enc(ctx, key); -} - -/** - * @brief Set SM4 decryption key - * - * @param [in] ctx SM4 context - * @param [in] key SM4 decryption key - */ -static inline void rom_sm4_setkey_dec(sm4_context_t *ctx, const uint8_t key[16]) -{ - ROM_API_TABLE_ROOT->sm4_api_if->setkey_dec(ctx, key); -} - -/** - * @brief SM4 ECB crypto operation(Encrypt or Decrypt) - * @param [in] ctx SM4 context - * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] input Input data - * @param [out] output Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output) -{ - return ROM_API_TABLE_ROOT->sm4_api_if->crypt_ecb(ctx, mode, length, input, output); -} - -/** - * @brief SM4 CBC crypto operation(Encrypt or Decrypt) - * @param [in] ctx SM4 context - * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] iv The initial vector for SM4 CBC crypto operation - * @param [in] input Input data - * @param [out] output Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], const uint8_t *input, uint8_t *output) -{ - return ROM_API_TABLE_ROOT->sm4_api_if->crypt_cbc(ctx, mode, length, iv, input, output); -} - - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ce18ef5544c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union -{ - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sdxc_soc_drv.h deleted file mode 100644 index 4a4e473daab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sdxc_soc_drv.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDXC_SOC_DRV_H -#define HPM_SDXC_SOC_DRV_H - -#include "hpm_soc.h" -#include "hpm_sdxc_regs.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - -static inline void sdxc_enable_tm_clock(SDXC_Type *base) -{ - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; -} - -static inline void sdxc_enable_freq_selection(SDXC_Type *base) -{ - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; -} - -static inline void sdxc_disable_freq_selection(SDXC_Type *base) -{ - base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; -} - -static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) -{ - base->MISC_CTRL0 = - (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div - 1U) | - SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; -} - -static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) -{ - return (1U + SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0)); -} - -/** - * @brief Wait at least 74 clocks until card is ready to receive the first command - */ -static inline void sdxc_wait_card_active(SDXC_Type *base) -{ - base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; - - base->MISC_CTRL1 |= SDXC_MISC_CTRL1_CARD_ACTIVE_MASK; - - while (!IS_HPM_BITMASK_SET(base->MISC_CTRL1, SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)) { - } -} - -static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) -{ - if (enable) { - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; - } else { - base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; - } -} - -static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) -{ - return ((base->MISC_CTRL0 & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) != 0U); -} - -static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool loopback_from_pad) -{ - if (!loopback_from_pad) { - base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; - } else { - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; - } -} - -/** - * @brief Set the Card Clock Delay chain - * @note This feature is not supported on this SoC - */ -static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t number_of_delaycells) -{ -} - -/** - * @brief Set SDXC data strobe delay chain - * @note This feature is not supported on this SoC - * @param [in] base SDXC base - * @param [in] num_of_delaycells Number of delay cells for Data strobe - */ -static inline void sdxc_set_data_strobe_delay(SDXC_Type *base, uint8_t num_of_delaycells) -{ -} - -static inline uint32_t sdxc_get_default_strobe_delay(SDXC_Type *base) -{ - (void) base; - return 0; -} - -static inline uint32_t sdxc_get_default_cardclk_delay_chain(SDXC_Type *base, uint32_t clock_freq) -{ - (void) base; - uint32_t num_delaycells = 3; - if (clock_freq <= 52000000) { - num_delaycells = 26; - } - return num_delaycells; -} - -static inline bool sdxc_is_ddr50_supported(SDXC_Type *base) -{ - (void) base; - return false; -} - - -#if defined(__cplusplus) -} -#endif - - -#endif /* HPM_SDXC_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ses_reg.xml deleted file mode 100644 index 9f86a426645..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ses_reg.xml +++ /dev/null @@ -1,24243 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ses_riscv_cpu_regs.xml deleted file mode 100644 index ec5ba6cb980..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_ses_riscv_cpu_regs.xml +++ /dev/null @@ -1,1098 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc.h deleted file mode 100644 index f500338c526..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc.h +++ /dev/null @@ -1,646 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */ -#define IRQn_ADC0 8 /* ADC0 IRQ */ -#define IRQn_ADC1 9 /* ADC1 IRQ */ -#define IRQn_ADC2 10 /* ADC2 IRQ */ -#define IRQn_DAC 11 /* DAC IRQ */ -#define IRQn_ACMP_0 12 /* ACMP[0] IRQ */ -#define IRQn_ACMP_1 13 /* ACMP[1] IRQ */ -#define IRQn_SPI0 14 /* SPI0 IRQ */ -#define IRQn_SPI1 15 /* SPI1 IRQ */ -#define IRQn_SPI2 16 /* SPI2 IRQ */ -#define IRQn_SPI3 17 /* SPI3 IRQ */ -#define IRQn_UART0 18 /* UART0 IRQ */ -#define IRQn_UART1 19 /* UART1 IRQ */ -#define IRQn_UART2 20 /* UART2 IRQ */ -#define IRQn_UART3 21 /* UART3 IRQ */ -#define IRQn_UART4 22 /* UART4 IRQ */ -#define IRQn_UART5 23 /* UART5 IRQ */ -#define IRQn_UART6 24 /* UART6 IRQ */ -#define IRQn_UART7 25 /* UART7 IRQ */ -#define IRQn_CAN0 26 /* CAN0 IRQ */ -#define IRQn_CAN1 27 /* CAN1 IRQ */ -#define IRQn_PTPC 28 /* PTPC IRQ */ -#define IRQn_WDG0 29 /* WDG0 IRQ */ -#define IRQn_WDG1 30 /* WDG1 IRQ */ -#define IRQn_TSNS 31 /* TSNS IRQ */ -#define IRQn_MBX0A 32 /* MBX0A IRQ */ -#define IRQn_MBX0B 33 /* MBX0B IRQ */ -#define IRQn_GPTMR0 34 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 35 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 36 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 37 /* GPTMR3 IRQ */ -#define IRQn_I2C0 38 /* I2C0 IRQ */ -#define IRQn_I2C1 39 /* I2C1 IRQ */ -#define IRQn_I2C2 40 /* I2C2 IRQ */ -#define IRQn_I2C3 41 /* I2C3 IRQ */ -#define IRQn_PWM0 42 /* PWM0 IRQ */ -#define IRQn_HALL0 43 /* HALL0 IRQ */ -#define IRQn_QEI0 44 /* QEI0 IRQ */ -#define IRQn_PWM1 45 /* PWM1 IRQ */ -#define IRQn_HALL1 46 /* HALL1 IRQ */ -#define IRQn_QEI1 47 /* QEI1 IRQ */ -#define IRQn_SDP 48 /* SDP IRQ */ -#define IRQn_XPI0 49 /* XPI0 IRQ */ -#define IRQn_XPI1 50 /* XPI1 IRQ */ -#define IRQn_XDMA 51 /* XDMA IRQ */ -#define IRQn_HDMA 52 /* HDMA IRQ */ -#define IRQn_FEMC 53 /* FEMC IRQ */ -#define IRQn_RNG 54 /* RNG IRQ */ -#define IRQn_I2S0 55 /* I2S0 IRQ */ -#define IRQn_I2S1 56 /* I2S1 IRQ */ -#define IRQn_DAO 57 /* DAO IRQ */ -#define IRQn_PDM 58 /* PDM IRQ */ -#define IRQn_FFA 59 /* FFA IRQ */ -#define IRQn_NTMR0 60 /* NTMR0 IRQ */ -#define IRQn_USB0 61 /* USB0 IRQ */ -#define IRQn_ENET0 62 /* ENET0 IRQ */ -#define IRQn_SDXC0 63 /* SDXC0 IRQ */ -#define IRQn_PSEC 64 /* PSEC IRQ */ -#define IRQn_PGPIO 65 /* PGPIO IRQ */ -#define IRQn_PWDG 66 /* PWDG IRQ */ -#define IRQn_PTMR 67 /* PTMR IRQ */ -#define IRQn_PUART 68 /* PUART IRQ */ -#define IRQn_FUSE 69 /* FUSE IRQ */ -#define IRQn_SECMON 70 /* SECMON IRQ */ -#define IRQn_RTC 71 /* RTC IRQ */ -#define IRQn_BUTN 72 /* BUTN IRQ */ -#define IRQn_BGPIO 73 /* BGPIO IRQ */ -#define IRQn_BVIO 74 /* BVIO IRQ */ -#define IRQn_BROWNOUT 75 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 76 /* SYSCTL IRQ */ -#define IRQn_DEBUG_0 77 /* DEBUG[0] IRQ */ -#define IRQn_DEBUG_1 78 /* DEBUG[1] IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0xC0000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF0000000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF40DC000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) -/* BGPIO base address */ -#define HPM_BGPIO_BASE (0xF5014000UL) -/* BGPIO base pointer */ -#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF0008000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF0010000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) -/* ADC1 base address */ -#define HPM_ADC1_BASE (0xF0014000UL) -/* ADC1 base pointer */ -#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) -/* ADC2 base address */ -#define HPM_ADC2_BASE (0xF0018000UL) -/* ADC2 base pointer */ -#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) - -#include "hpm_acmp_regs.h" -/* Address of ACMP instances */ -/* ACMP base address */ -#define HPM_ACMP_BASE (0xF0020000UL) -/* ACMP base pointer */ -#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) - -#include "hpm_dac_regs.h" -/* Address of DAC instances */ -/* DAC base address */ -#define HPM_DAC_BASE (0xF0024000UL) -/* DAC base pointer */ -#define HPM_DAC ((DAC_Type *) HPM_DAC_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0030000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0034000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0038000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF003C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* UART4 base address */ -#define HPM_UART4_BASE (0xF0050000UL) -/* UART4 base pointer */ -#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) -/* UART5 base address */ -#define HPM_UART5_BASE (0xF0054000UL) -/* UART5 base pointer */ -#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) -/* UART6 base address */ -#define HPM_UART6_BASE (0xF0058000UL) -/* UART6 base pointer */ -#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) -/* UART7 base address */ -#define HPM_UART7_BASE (0xF005C000UL) -/* UART7 base pointer */ -#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF40E4000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_can_regs.h" -/* Address of CAN instances */ -/* CAN0 base address */ -#define HPM_CAN0_BASE (0xF0080000UL) -/* CAN0 base pointer */ -#define HPM_CAN0 ((CAN_Type *) HPM_CAN0_BASE) -/* CAN1 base address */ -#define HPM_CAN1_BASE (0xF0084000UL) -/* CAN1 base pointer */ -#define HPM_CAN1 ((CAN_Type *) HPM_CAN1_BASE) - -#include "hpm_wdg_regs.h" -/* Address of WDOG instances */ -/* WDG0 base address */ -#define HPM_WDG0_BASE (0xF0090000UL) -/* WDG0 base pointer */ -#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) -/* WDG1 base address */ -#define HPM_WDG1_BASE (0xF0094000UL) -/* WDG1 base pointer */ -#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) -/* PWDG base address */ -#define HPM_PWDG_BASE (0xF40E8000UL) -/* PWDG base pointer */ -#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) - -#include "hpm_ptpc_regs.h" -/* Address of PTPC instances */ -/* PTPC base address */ -#define HPM_PTPC_BASE (0xF00B0000UL) -/* PTPC base pointer */ -#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C0000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dma_regs.h" -/* Address of DMA instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C4000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) -/* XDMA base address */ -#define HPM_XDMA_BASE (0xF3048000UL) -/* XDMA base pointer */ -#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) - -#include "hpm_rng_regs.h" -/* Address of RNG instances */ -/* RNG base address */ -#define HPM_RNG_BASE (0xF00C8000UL) -/* RNG base pointer */ -#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF00CC000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_i2s_regs.h" -/* Address of I2S instances */ -/* I2S0 base address */ -#define HPM_I2S0_BASE (0xF0100000UL) -/* I2S0 base pointer */ -#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) -/* I2S1 base address */ -#define HPM_I2S1_BASE (0xF0104000UL) -/* I2S1 base pointer */ -#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) - -#include "hpm_dao_regs.h" -/* Address of DAO instances */ -/* DAO base address */ -#define HPM_DAO_BASE (0xF0110000UL) -/* DAO base pointer */ -#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) - -#include "hpm_pdm_regs.h" -/* Address of PDM instances */ -/* PDM base address */ -#define HPM_PDM_BASE (0xF0114000UL) -/* PDM base pointer */ -#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) - -#include "hpm_pwm_regs.h" -/* Address of PWM instances */ -/* PWM0 base address */ -#define HPM_PWM0_BASE (0xF0200000UL) -/* PWM0 base pointer */ -#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) -/* PWM1 base address */ -#define HPM_PWM1_BASE (0xF0210000UL) -/* PWM1 base pointer */ -#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) - -#include "hpm_hall_regs.h" -/* Address of HALL instances */ -/* HALL0 base address */ -#define HPM_HALL0_BASE (0xF0204000UL) -/* HALL0 base pointer */ -#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) -/* HALL1 base address */ -#define HPM_HALL1_BASE (0xF0214000UL) -/* HALL1 base pointer */ -#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) - -#include "hpm_qei_regs.h" -/* Address of QEI instances */ -/* QEI0 base address */ -#define HPM_QEI0_BASE (0xF0208000UL) -/* QEI0 base pointer */ -#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) -/* QEI1 base address */ -#define HPM_QEI1_BASE (0xF0218000UL) -/* QEI1 base pointer */ -#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) - -#include "hpm_trgm_regs.h" -/* Address of TRGM instances */ -/* TRGM0 base address */ -#define HPM_TRGM0_BASE (0xF020C000UL) -/* TRGM0 base pointer */ -#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) -/* TRGM1 base address */ -#define HPM_TRGM1_BASE (0xF021C000UL) -/* TRGM1 base pointer */ -#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) - -#include "hpm_synt_regs.h" -/* Address of SYNT instances */ -/* SYNT base address */ -#define HPM_SYNT_BASE (0xF0240000UL) -/* SYNT base pointer */ -#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) - -#include "hpm_enet_regs.h" -/* Address of ENET instances */ -/* ENET0 base address */ -#define HPM_ENET0_BASE (0xF2000000UL) -/* ENET0 base pointer */ -#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* NTMR0 base address */ -#define HPM_NTMR0_BASE (0xF2010000UL) -/* NTMR0 base pointer */ -#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF3000000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF3004000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* GPTMR2 base address */ -#define HPM_GPTMR2_BASE (0xF3008000UL) -/* GPTMR2 base pointer */ -#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) -/* GPTMR3 base address */ -#define HPM_GPTMR3_BASE (0xF300C000UL) -/* GPTMR3 base pointer */ -#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF40E0000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF2020000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) - -#include "hpm_sdxc_regs.h" -/* Address of SDXC instances */ -/* SDXC0 base address */ -#define HPM_SDXC0_BASE (0xF2030000UL) -/* SDXC0 base pointer */ -#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF3020000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF3024000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF3028000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF302C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) - -#include "hpm_sdp_regs.h" -/* Address of SDP instances */ -/* SDP base address */ -#define HPM_SDP_BASE (0xF304C000UL) -/* SDP base pointer */ -#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) - -#include "hpm_femc_regs.h" -/* Address of FEMC instances */ -/* FEMC base address */ -#define HPM_FEMC_BASE (0xF3050000UL) -/* FEMC base pointer */ -#define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE) - -/* Address of ROMC instances */ -/* ROMC base address */ -#define HPM_ROMC_BASE (0xF3054000UL) - -#include "hpm_ffa_regs.h" -/* Address of FFA instances */ -/* FFA base address */ -#define HPM_FFA_BASE (0xF3058000UL) -/* FFA base pointer */ -#define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF40D8000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) -/* BIOC base address */ -#define HPM_BIOC_BASE (0xF5010000UL) -/* BIOC base pointer */ -#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTPSHW base address */ -#define HPM_OTPSHW_BASE (0xF4080000UL) -/* OTPSHW base pointer */ -#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) -/* OTP base address */ -#define HPM_OTP_BASE (0xF40C8000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF40C0000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF40C4000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_psec_regs.h" -/* Address of PSEC instances */ -/* PSEC base address */ -#define HPM_PSEC_BASE (0xF40CC000UL) -/* PSEC base pointer */ -#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) - -#include "hpm_pmon_regs.h" -/* Address of PMON instances */ -/* PMON base address */ -#define HPM_PMON_BASE (0xF40D0000UL) -/* PMON base pointer */ -#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR base address */ -#define HPM_PGPR_BASE (0xF40D4000UL) -/* PGPR base pointer */ -#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) - -#include "hpm_pllctlv2_regs.h" -/* Address of PLLCTLV2 instances */ -/* PLLCTLV2 base address */ -#define HPM_PLLCTLV2_BASE (0xF4100000UL) -/* PLLCTLV2 base pointer */ -#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) - -#include "hpm_tsns_regs.h" -/* Address of TSNS instances */ -/* TSNS base address */ -#define HPM_TSNS_BASE (0xF4104000UL) -/* TSNS base pointer */ -#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) - -#include "hpm_bacc_regs.h" -/* Address of BACC instances */ -/* BACC base address */ -#define HPM_BACC_BASE (0xF5000000UL) -/* BACC base pointer */ -#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) - -#include "hpm_bpor_regs.h" -/* Address of BPOR instances */ -/* BPOR base address */ -#define HPM_BPOR_BASE (0xF5004000UL) -/* BPOR base pointer */ -#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) - -#include "hpm_bcfg_regs.h" -/* Address of BCFG instances */ -/* BCFG base address */ -#define HPM_BCFG_BASE (0xF5008000UL) -/* BCFG base pointer */ -#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) - -#include "hpm_butn_regs.h" -/* Address of BUTN instances */ -/* BUTN base address */ -#define HPM_BUTN_BASE (0xF500C000UL) -/* BUTN base pointer */ -#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) - -#include "hpm_bgpr_regs.h" -/* Address of BGPR instances */ -/* BGPR base address */ -#define HPM_BGPR_BASE (0xF5018000UL) -/* BGPR base pointer */ -#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) - -#include "hpm_bsec_regs.h" -/* Address of BSEC instances */ -/* BSEC base address */ -#define HPM_BSEC_BASE (0xF5040000UL) -/* BSEC base pointer */ -#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) - -#include "hpm_rtc_regs.h" -/* Address of RTC instances */ -/* RTC base address */ -#define HPM_RTC_BASE (0xF5044000UL) -/* RTC base pointer */ -#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) - -#include "hpm_bkey_regs.h" -/* Address of BKEY instances */ -/* BKEY base address */ -#define HPM_BKEY_BASE (0xF5048000UL) -/* BKEY base pointer */ -#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) - -#include "hpm_bmon_regs.h" -/* Address of BMON instances */ -/* BMON base address */ -#define HPM_BMON_BASE (0xF504C000UL) -/* BMON base pointer */ -#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) - -#include "hpm_tamp_regs.h" -/* Address of TAMP instances */ -/* TAMP base address */ -#define HPM_TAMP_BASE (0xF5050000UL) -/* TAMP base pointer */ -#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) - -#include "hpm_mono_regs.h" -/* Address of MONO instances */ -/* MONO base address */ -#define HPM_MONO_BASE (0xF5054000UL) -/* MONO base pointer */ -#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_trgmmux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc_feature.h deleted file mode 100644 index 4285c89cb70..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc_feature.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" -#include "hpm_soc_ip_feature.h" - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (256U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * I2S Section - */ -#define I2S_SOC_MAX_CHANNEL_NUM (16U) -#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) -#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) -#define PDM_I2S HPM_I2S0 -#define DAO_I2S HPM_I2S1 -#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) -#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) -#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (3U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (24U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (8U) -#define DMA_SOC_MAX_COUNT (2U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) - -/* - * PDMA Section - */ -#define PDMA_SOC_PS_MAX_COUNT (0U) - -/* - * LCDC Section - */ -#define LCDC_SOC_MAX_LAYER_COUNT (0U) -#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U) -#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) -#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) - -/* -* USB Section -*/ -#define USB_SOC_MAX_COUNT (1U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* -* ENET Section -*/ -#define ENET_SOC_RGMII_EN (0U) -#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) -#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) -#define ENET_SOC_ADDR_MAX_COUNT (5U) -#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) -#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) -#define ENET_SOC_ALT_EHD_DES_LEN (8U) -#define ENET_SOC_PPS_MAX_COUNT (2L) -#define ENET_SOC_PPS1_EN (0U) - -/* -* ADC Section -*/ -#define ADC_SOC_IP_VERSION (1U) -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * CAN Section - */ -#define CAN_SOC_MAX_COUNT (2U) - -/* - * SDP Section - */ -#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) - -/* - * SOC Privilege mode - */ -#define SOC_HAS_S_MODE (1U) - -/* - * DAC Section - */ -#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) -#define DAC_SOC_MAX_DATA (4095U) -#define DAC_SOC_MAX_BUFF_COUNT (65536U) -#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) - - -/* - * SDXC Section - */ -#define SDXC_SOC_HAS_MISC_CTRL0 (1) -#define SDXC_SOC_HAS_MISC_CTRL1 (1) - -/* - * UART Section - */ -#define UART_SOC_FIFO_SIZE (16U) - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (512U) -#define SPI_SOC_FIFO_DEPTH (4U) - -/* - * SDXC Section - */ -#define SDXC_SOC_MAX_COUNT (1) - -/* - * ROM API section - */ -#define ROMAPI_HAS_SW_SM3 (1) -#define ROMAPI_HAS_SW_SM4 (1) - -/* - * OTP Section - */ -#define OTP_SOC_MAC0_IDX (65U) -#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ - -#define OTP_SOC_UUID_IDX (88U) -#define OTP_SOC_UUID_LEN (16U) /* in bytes */ - -/** - * PWM Section - * - */ -#define PWM_SOC_HRPWM_SUPPORT (0U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) -#define PWM_SOC_TIMER_RESET_SUPPORT (1U) - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc_ip_feature.h deleted file mode 100644 index 410acf83beb..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_soc_ip_feature.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* PWM related feature */ -#define HPM_IP_FEATURE_PWM_COUNTER_RESET 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sysctl_drv.c deleted file mode 100644 index 48fb57bc6aa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sysctl_drv.c +++ /dev/null @@ -1,297 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) - -static inline bool sysctl_valid_cpu_index(uint8_t cpu) -{ - if (cpu != SYSCTL_CPU_CPU0) { - return false; - } - return true; -} - -hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) -{ - uint32_t i; - if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { - return status_invalid_argument; - } - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i]; - } - return status_success; -} - -static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[cpu].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); -} - -hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); -} - -static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[cpu].GPR[start + i] = *(data + i); - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) -{ - ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & - ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | - SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | - (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | - SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | - SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | - SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | - SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | - SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t -sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_target_t target, bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = { 0 }; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -static hpm_stat_t _sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].GPR[0] = entry; - ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); - return status_success; -} - -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return _sysctl_set_cpu_entry(ptr, 0, entry); -} - -hpm_stat_t -sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable) -{ - uint32_t index, offset; - if (resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource) -{ - uint32_t index, offset; - bool enable; - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_i2s_t source) -{ - uint32_t index; - if ((node < clock_node_adc_i2s_start) || (source >= clock_source_adc_i2s_clk_end)) { - return status_invalid_argument; - } - - switch (node) { - case clock_node_adc2: - case clock_node_adc1: - case clock_node_adc0: - index = node - clock_node_adc0; - ptr->ADCCLK[index] = (ptr->ADCCLK[index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); - break; - case clock_node_i2s1: - case clock_node_i2s0: - index = node - clock_node_i2s0; - ptr->I2SCLK[index] = (ptr->I2SCLK[index] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(source); - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) -{ - if (node >= clock_node_adc_i2s_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) -{ - if (node >= clock_node_adc_i2s_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | - (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { } - return status_success; -} - -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, - clock_source_t source, - uint32_t cpu_div, - uint32_t axi_sub_div, - uint32_t ahb_sub_div) -{ - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - - uint32_t origin_cpu_div = SYSCTL_CLOCK_CPU_DIV_GET(ptr->CLOCK_CPU[0]) + 1U; - if (origin_cpu_div == cpu_div) { - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div) | - SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - } - ptr->CLOCK_CPU[0] = SYSCTL_CLOCK_CPU_MUX_SET(source) | SYSCTL_CLOCK_CPU_DIV_SET(cpu_div - 1) | - SYSCTL_CLOCK_CPU_SUB0_DIV_SET(axi_sub_div - 1) | SYSCTL_CLOCK_CPU_SUB1_DIV_SET(ahb_sub_div - 1); - - while (sysctl_cpu_clock_any_is_busy(ptr)) { - } - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sysctl_drv.h deleted file mode 100644 index 4c2930100e3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_sysctl_drv.h +++ /dev/null @@ -1,1308 +0,0 @@ -/** - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */ -typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - - sysctl_retention_domain_xtal24m = 4, - sysctl_retention_domain_pll0 = 5, - sysctl_retention_domain_pll1 = 6, - sysctl_retention_domain_pll2 = 7, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_cpu0, -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = 0, - sysctl_resource_cpx0 = 1, - sysctl_resource_exe0 = 2, - sysctl_resource_wak0 = 3, - sysctl_resource_cpu0_per = 4, - sysctl_resource_logic0 = 16, - sysctl_resource_logic1 = 17, - sysctl_resource_logic2 = 18, - sysctl_resource_logic3 = 19, - sysctl_resource_pmic = 20, - sysctl_resource_pow_cpu0 = 21, - sysctl_resource_rst_soc = 22, - sysctl_resource_rst_cpu0 = 23, - sysctl_resource_xtal = 32, - sysctl_resource_pll0 = 33, - sysctl_resource_clk0_pll0 = 34, - sysctl_resource_clk1_pll0 = 35, - sysctl_resource_clk2_pll0 = 36, - sysctl_resource_pll1 = 37, - sysctl_resource_clk0_pll1 = 38, - sysctl_resource_clk1_pll1 = 39, - sysctl_resource_pll2 = 40, - sysctl_resource_clk0_pll2 = 41, - sysctl_resource_clk1_pll2 = 42, - sysctl_resource_pll0_ref = 43, - sysctl_resource_pll1_ref = 44, - sysctl_resource_pll2_ref = 45, - sysctl_resource_mbist_soc = 48, - sysctl_resource_mbist_cpu = 49, - sysctl_resource_mbist_con = 50, - sysctl_resource_dft_start_bus = 51, - sysctl_resource_clk_top_cpu0 = 64, - sysctl_resource_clk_top_mchtmr0 = 65, - sysctl_resource_clk_top_femc = 66, - sysctl_resource_clk_top_xpi0 = 67, - sysctl_resource_clk_top_xpi1 = 68, - sysctl_resource_clk_top_gptmr0 = 69, - sysctl_resource_clk_top_gptmr1 = 70, - sysctl_resource_clk_top_gptmr2 = 71, - sysctl_resource_clk_top_gptmr3 = 72, - sysctl_resource_clk_top_uart0 = 73, - sysctl_resource_clk_top_uart1 = 74, - sysctl_resource_clk_top_uart2 = 75, - sysctl_resource_clk_top_uart3 = 76, - sysctl_resource_clk_top_uart4 = 77, - sysctl_resource_clk_top_uart5 = 78, - sysctl_resource_clk_top_uart6 = 79, - sysctl_resource_clk_top_uart7 = 80, - sysctl_resource_clk_top_i2c0 = 81, - sysctl_resource_clk_top_i2c1 = 82, - sysctl_resource_clk_top_i2c2 = 83, - sysctl_resource_clk_top_i2c3 = 84, - sysctl_resource_clk_top_spi0 = 85, - sysctl_resource_clk_top_spi1 = 86, - sysctl_resource_clk_top_spi2 = 87, - sysctl_resource_clk_top_spi3 = 88, - sysctl_resource_clk_top_can0 = 89, - sysctl_resource_clk_top_can1 = 90, - sysctl_resource_clk_top_ptpc = 91, - sysctl_resource_clk_top_ana0 = 92, - sysctl_resource_clk_top_ana1 = 93, - sysctl_resource_clk_top_ana2 = 94, - sysctl_resource_clk_top_ana3 = 95, - sysctl_resource_clk_top_aud0 = 96, - sysctl_resource_clk_top_aud1 = 97, - sysctl_resource_clk_top_eth0 = 98, - sysctl_resource_clk_top_ptp0 = 99, - sysctl_resource_clk_top_ref0 = 100, - sysctl_resource_clk_top_ref1 = 101, - sysctl_resource_clk_top_ntmr0 = 102, - sysctl_resource_clk_top_sdxc0 = 103, - sysctl_resource_clk_top_adc0 = 128, - sysctl_resource_clk_top_adc1 = 129, - sysctl_resource_clk_top_adc2 = 130, - sysctl_resource_clk_top_dac0 = 131, - sysctl_resource_clk_top_i2s0 = 132, - sysctl_resource_clk_top_i2s1 = 133, - - sysctl_resource_eth0_mem = 192, - sysctl_resource_sdxc0_mem = 193, - sysctl_resource_usb0_mem = 194, - sysctl_resource_ram0_mem = 195, - sysctl_resource_ahbp_mem = 196, - sysctl_resource_femc_mem = 197, - sysctl_resource_rom0_mem = 198, - sysctl_resource_xpi0_mem = 199, - sysctl_resource_xpi1_mem = 200, - sysctl_resource_can0_mem = 201, - sysctl_resource_can1_mem = 202, - sysctl_resource_i2s0_mem = 203, - sysctl_resource_i2s1_mem = 204, - sysctl_resource_pdm0_mem = 205, - sysctl_resource_sdp0_mem = 206, - sysctl_resource_ffa0_mem = 207, - sysctl_resource_cpx_mem = 208, - sysctl_resource_core_mem = 209, - sysctl_resource_lmm0_mem = 210, - - - sysctl_resource_linkable_start = 256, - sysctl_resource_ahbp = 256, - sysctl_resource_axis = 257, - sysctl_resource_axic = 258, - sysctl_resource_femc = 259, - sysctl_resource_rom0 = 260, - sysctl_resource_lmm0 = 261, - sysctl_resource_ram0 = 262, - sysctl_resource_mchtmr0 = 263, - sysctl_resource_xpi0 = 264, - sysctl_resource_xpi1 = 265, - sysctl_resource_sdp0 = 266, - sysctl_resource_rng0 = 267, - sysctl_resource_kman = 268, - sysctl_resource_dma0 = 269, - sysctl_resource_dma1 = 270, - sysctl_resource_ffa0 = 271, - sysctl_resource_gpio = 272, - sysctl_resource_mbx0 = 273, - sysctl_resource_wdg0 = 274, - sysctl_resource_wdg1 = 275, - sysctl_resource_tsns = 276, - sysctl_resource_gptmr0 = 277, - sysctl_resource_gptmr1 = 278, - sysctl_resource_gptmr2 = 279, - sysctl_resource_gptmr3 = 280, - sysctl_resource_uart0 = 281, - sysctl_resource_uart1 = 282, - sysctl_resource_uart2 = 283, - sysctl_resource_uart3 = 284, - sysctl_resource_uart4 = 285, - sysctl_resource_uart5 = 286, - sysctl_resource_uart6 = 287, - sysctl_resource_uart7 = 288, - sysctl_resource_i2c0 = 289, - sysctl_resource_i2c1 = 290, - sysctl_resource_i2c2 = 291, - sysctl_resource_i2c3 = 292, - sysctl_resource_spi0 = 293, - sysctl_resource_spi1 = 294, - sysctl_resource_spi2 = 295, - sysctl_resource_spi3 = 296, - sysctl_resource_can0 = 297, - sysctl_resource_can1 = 298, - sysctl_resource_ptpc = 299, - sysctl_resource_adc0 = 300, - sysctl_resource_adc1 = 301, - sysctl_resource_adc2 = 302, - sysctl_resource_dac0 = 303, - sysctl_resource_acmp = 304, - sysctl_resource_i2s0 = 305, - sysctl_resource_i2s1 = 306, - sysctl_resource_i2spdm0 = 307, - sysctl_resource_i2sdao = 308, - sysctl_resource_synt = 309, - sysctl_resource_mot0 = 310, - sysctl_resource_mot1 = 311, - sysctl_resource_eth0 = 312, - sysctl_resource_ntmr0 = 313, - sysctl_resource_sdxc0 = 314, - sysctl_resource_usb0 = 315, - sysctl_resource_ref0 = 316, - sysctl_resource_ref1 = 317, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, - sysctl_resource_mode_force_on, - sysctl_resource_mode_force_off, -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_mchtmr0 = 0, - clock_node_femc = 1, - clock_node_xpi0 = 2, - clock_node_xpi1 = 3, - clock_node_gptmr0 = 4, - clock_node_gptmr1 = 5, - clock_node_gptmr2 = 6, - clock_node_gptmr3 = 7, - clock_node_uart0 = 8, - clock_node_uart1 = 9, - clock_node_uart2 = 10, - clock_node_uart3 = 11, - clock_node_uart4 = 12, - clock_node_uart5 = 13, - clock_node_uart6 = 14, - clock_node_uart7 = 15, - clock_node_i2c0 = 16, - clock_node_i2c1 = 17, - clock_node_i2c2 = 18, - clock_node_i2c3 = 19, - clock_node_spi0 = 20, - clock_node_spi1 = 21, - clock_node_spi2 = 22, - clock_node_spi3 = 23, - clock_node_can0 = 24, - clock_node_can1 = 25, - clock_node_ptpc = 26, - clock_node_ana0 = 27, - clock_node_ana1 = 28, - clock_node_ana2 = 29, - clock_node_ana3 = 30, - clock_node_aud0 = 31, - clock_node_aud1 = 32, - clock_node_eth0 = 33, - clock_node_ptp0 = 34, - clock_node_ref0 = 35, - clock_node_ref1 = 36, - clock_node_ntmr0 = 37, - clock_node_sdxc0 = 38, - - clock_node_adc_i2s_start, - clock_node_adc0 = clock_node_adc_i2s_start, - clock_node_adc1, - clock_node_adc2, - - clock_node_i2s0, - clock_node_i2s1, - - clock_node_end, - - clock_node_core_start = 0xfc, - clock_node_cpu0 = clock_node_core_start, - clock_node_axi, - clock_node_ahb, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll0_clk1 = 2, - clock_source_pll0_clk2 = 3, - clock_source_pll1_clk0 = 4, - clock_source_pll1_clk1 = 5, - clock_source_pll2_clk0 = 6, - clock_source_pll2_clk1 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC/I2S clock sources - */ -typedef enum { - clock_source_adc_ana_clk = 0, - clock_source_adc_ahb_clk = 1, - clock_source_i2s_aud0_clk = 0, - clock_source_i2s_aud1_clk = 1, - clock_source_adc_i2s_clk_end, -} clock_source_adc_i2s_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -typedef enum { - monitor_target_clk_32k = 0, - monitor_target_clk_irc24m = 1, - monitor_target_clk_xtal_24m = 2, - monitor_target_clk_usb0_phy = 3, - - monitor_target_clk0_osc0 = 8, - monitor_target_clk0_pll0 = 9, - monitor_target_clk1_pll0 = 10, - monitor_target_clk2_pll0 = 11, - monitor_target_clk0_pll1 = 12, - monitor_target_clk1_pll1 = 13, - monitor_target_clk0_pll2 = 14, - monitor_target_clk1_pll2 = 15, - - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - - monitor_target_clk_top_femc = 136, - monitor_target_clk_top_xpi0 = 137, - monitor_target_clk_top_xpi1 = 138, - monitor_target_clk_top_gptmr0 = 139, - monitor_target_clk_top_gptmr1 = 140, - monitor_target_clk_top_gptmr2 = 141, - monitor_target_clk_top_gptmr3 = 142, - - monitor_target_clk_top_uart0 = 147, - monitor_target_clk_top_uart1 = 148, - monitor_target_clk_top_uart2 = 149, - monitor_target_clk_top_uart3 = 150, - monitor_target_clk_top_uart4 = 151, - monitor_target_clk_top_uart5 = 152, - monitor_target_clk_top_uart6 = 153, - monitor_target_clk_top_uart7 = 154, - - monitor_target_clk_top_i2c0 = 163, - monitor_target_clk_top_i2c1 = 164, - monitor_target_clk_top_i2c2 = 165, - monitor_target_clk_top_i2c3 = 166, - monitor_target_clk_top_spi0 = 167, - monitor_target_clk_top_spi1 = 168, - monitor_target_clk_top_spi2 = 169, - monitor_target_clk_top_spi3 = 170, - monitor_target_clk_top_can0 = 171, - monitor_target_clk_top_can1 = 172, - - monitor_target_clk_top_ptpc = 175, - monitor_target_clk_top_ana0 = 176, - monitor_target_clk_top_ana1 = 177, - monitor_target_clk_top_ana2 = 178, - monitor_target_clk_top_ana3 = 179, - monitor_target_clk_top_aud0 = 180, - monitor_target_clk_top_aud1 = 181, - - monitor_target_clk_top_eth0 = 185, - - monitor_target_clk_top_ptp0 = 187, - - monitor_target_clk_top_ref0 = 189, - monitor_target_clk_top_ref1 = 190, - monitor_target_clk_top_ntmr0 = 191, - - monitor_target_clk_top_sdxc0 = 193, - -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | - (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t -sysctl_monitor_set_limit(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit_high, uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t -sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_target_t target, bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = - (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | - SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Disable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void -sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, uint8_t cpu_index, sysctl_retention_domain_t domain, bool retain_mem) -{ - uint8_t set_mask = 0x1; - if (domain < sysctl_retention_domain_xtal24m) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Retain target domain for specific CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); -} - -/** - * @brief Check if cpu clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_cpu_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK_CPU[0] & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK; -} - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Preserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Unpreserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Get target CPU0 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, - uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 0, status_index); -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t -sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index, uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Check CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline - uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void -sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t enable_index, uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void -sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t enable_index, uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); -} - - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Disable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); -} - - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Lock CPU gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint16_t gpr_mask) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, - uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); -} - -/** - * @brief Lock CPU lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 0); -} - -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) -{ - ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); -} - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 0, mode); -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Get CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); -} - -/** - * @brief Get CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 0); -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); - -/** - * @brief Configure CPU domain clock - * @param ptr SYSCTL base address - * @param source clock source to be used - * @param cpu_div CPU divider - * @param axi_sub_div AXI BUS divider based on divided CPU clock - * @param ahb_sub_div AHB BUS divider based on divided CPU clock - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_cpu0_domain_clock(SYSCTL_Type *ptr, clock_source_t source, uint32_t cpu_div, - uint32_t axi_sub_div, uint32_t ahb_sub_div); - -/** - * @brief Set ADC/I2S clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_i2s_t source); - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); - -/** - * @brief Save data to CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved from CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_trgmmux_src.h deleted file mode 100644 index 6854b7aadf7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/hpm_trgmmux_src.h +++ /dev/null @@ -1,366 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGMMUX_SRC_H -#define HPM_TRGMMUX_SRC_H - -/* trgm0_input mux definitions */ -#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) -#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) -#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) -#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) -#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) -#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) -#define HPM_TRGM0_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) -#define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) -#define HPM_TRGM0_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) -#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) - -/* trgm1_input mux definitions */ -#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) -#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) -#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) -#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) -#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) -#define HPM_TRGM1_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) -#define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) -#define HPM_TRGM1_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) -#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) -#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) -#define HPM_TRGM1_INPUT_SRC_SYNT0_CH0 (0x2CUL) -#define HPM_TRGM1_INPUT_SRC_SYNT0_CH1 (0x2DUL) -#define HPM_TRGM1_INPUT_SRC_SYNT0_CH2 (0x2EUL) -#define HPM_TRGM1_INPUT_SRC_SYNT0_CH3 (0x2FUL) -#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) -#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) - -/* trgm0_output mux definitions */ -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) -#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI2A (0x30UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI2B (0x31UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI2C (0x32UL) -#define HPM_TRGM0_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) -#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) -#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) -#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) -#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) -#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) -#define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) - -/* trgm1_output mux definitions */ -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) -#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI3A (0x30UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI3B (0x31UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI3C (0x32UL) -#define HPM_TRGM1_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) -#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) -#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) -#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) -#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) -#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) -#define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) - -/* trgm0_filter mux definitions */ -#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) - -/* trgm1_filter mux definitions */ -#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) - -/* trgm0_dma mux definitions */ -#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) -#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) -#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) -#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) -#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) -#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) - -/* trgm1_dma mux definitions */ -#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) -#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) -#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) -#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) -#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) -#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) - - - -#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/soc_modules.list deleted file mode 100644 index 3b645a18c9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/soc_modules.list +++ /dev/null @@ -1,63 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_ACMP=y -HPMSOC_HAS_HPMSDK_DAC=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_CAN=y -HPMSOC_HAS_HPMSDK_WDG=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_PTPC=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMA=y -HPMSOC_HAS_HPMSDK_RNG=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_I2S=y -HPMSOC_HAS_HPMSDK_DAO=y -HPMSOC_HAS_HPMSDK_PDM=y -HPMSOC_HAS_HPMSDK_PWM=y -HPMSOC_HAS_HPMSDK_HALL=y -HPMSOC_HAS_HPMSDK_QEI=y -HPMSOC_HAS_HPMSDK_TRGM=y -HPMSOC_HAS_HPMSDK_SYNT=y -HPMSOC_HAS_HPMSDK_ENET=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_SDXC=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_SDP=y -HPMSOC_HAS_HPMSDK_FEMC=y -HPMSOC_HAS_HPMSDK_FFA=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PSEC=y -HPMSOC_HAS_HPMSDK_PMON=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_PLLCTLV2=y -HPMSOC_HAS_HPMSDK_TSNS=y -HPMSOC_HAS_HPMSDK_BACC=y -HPMSOC_HAS_HPMSDK_BPOR=y -HPMSOC_HAS_HPMSDK_BCFG=y -HPMSOC_HAS_HPMSDK_BUTN=y -HPMSOC_HAS_HPMSDK_BGPR=y -HPMSOC_HAS_HPMSDK_BSEC=y -HPMSOC_HAS_HPMSDK_RTC=y -HPMSOC_HAS_HPMSDK_BKEY=y -HPMSOC_HAS_HPMSDK_BMON=y -HPMSOC_HAS_HPMSDK_TAMP=y -HPMSOC_HAS_HPMSDK_MONO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/system.c deleted file mode 100644 index 3ea422c42ea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/system.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif - -#ifdef USE_S_MODE_IRQ - disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#else - disable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - - disable_irq_from_intc(); -#ifdef USE_S_MODE_IRQ - disable_s_irq_from_intc(); -#endif - - enable_plic_feature(); - enable_irq_from_intc(); - -#ifdef USE_S_MODE_IRQ - delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); - enable_s_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#endif -#else -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash.ld deleted file mode 100644 index 87fb76632b8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash.ld +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_sdram_uf2.ld deleted file mode 100644 index 33390fd7c2c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_sdram_uf2.ld +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_sdram_xip.ld deleted file mode 100644 index 1d1da80cd73..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_sdram_xip.ld +++ /dev/null @@ -1,301 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x1080000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index 419093878f7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_xip.ld deleted file mode 100644 index 9c748779ff1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/flash_xip.ld +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/ram.ld deleted file mode 100644 index c5d7afb8b4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/ram.ld +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 128K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 128K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x010C0000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/start.S deleted file mode 100644 index 9dbd93c8935..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/gcc/start.S +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - la tp, __thread_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_sdram_uf2.icf deleted file mode 100644 index 92dbd558fea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_sdram_uf2.icf +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 16M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 512k]; /* AXI SRAM */ -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 4M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 4M size 4M]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_sdram_xip.icf deleted file mode 100644 index b2e1406d434..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_sdram_xip.icf +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 16M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x2000 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 512k]; /* AXI SRAM */ -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 4M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 4M size 4M]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_uf2.icf deleted file mode 100644 index f3eaeb47c77..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01080000 size 256k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x010C0000 size 256k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_xip.icf deleted file mode 100644 index f9b95ba2542..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,124 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01080000 size 256k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x010C0000 size 256k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .nor_cfg_option, - section .boot_header, - section .fw_info_table, - section .dc_info - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/ram.icf deleted file mode 100644 index d1b97f7a85d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/ram.icf +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 128k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 128k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01080000 size 256k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x010C0000 size 256k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/startup.s deleted file mode 100644 index 81175908610..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/iar/startup.s +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - EXTERN _init_ext_ram -__iar_cstart_init_ext_ram: - la t0, SFE(SAFESTACK) - mv sp, t0 - call _init_ext_ram -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/reset.c deleted file mode 100644 index 84dbb6ef286..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash.icf deleted file mode 100644 index fbf69cbdd11..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_sdram_uf2.icf deleted file mode 100644 index 6fbd935294a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_sdram_uf2.icf +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_sdram_xip.icf deleted file mode 100644 index de511d3c739..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_sdram_xip.icf +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 18fc954d0a0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_xip.icf deleted file mode 100644 index b4925b3154e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/ram.icf deleted file mode 100644 index c4faec93788..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/ram.icf +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 128k]; /* ILM */ -define region DLM = [from 0x00080000 size 128k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x010C0000 size 256k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/startup.s deleted file mode 100644 index 8a7036e137d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/segger/startup.s +++ /dev/null @@ -1,419 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/trap.c deleted file mode 100644 index 3df45f565c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/trap.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ -#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ -#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ -#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ -#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ -#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -__attribute__((weak)) long exception_s_handler(long cause, long epc) -{ - (void) cause; - return epc; -} - -__attribute__((weak)) void swi_s_isr(void) -{ -} - -__attribute__((weak)) void mchtmr_s_isr(void) -{ -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} - - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_s_table[]; -HPM_ATTR_SUPERVISOR_INTERRUPT -#endif -void irq_handler_s_trap(void) -{ - long scause = read_csr(CSR_SCAUSE); - long sepc = read_csr(CSR_SEPC); - long sstatus = read_csr(CSR_SSTATUS); - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { - /* Machine timer interrupt */ - mchtmr_s_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_s_global_irq(CSR_SSTATUS_SIE_MASK); -#endif - ((isr_func_t)__vector_s_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); - - } -#endif - - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_s_isr(); - intc_s_complete_swi(); - } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - sepc += 4; - } else { - sepc = exception_s_handler(scause, sepc); - } - - /* Restore CSR */ - write_csr(CSR_SSTATUS, sstatus); - write_csr(CSR_SEPC, sepc); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/vectors.h deleted file mode 100644 index 3e2198f4a3f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/HPM6360/toolchains/vectors.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(9) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_DEFAULT_HANDLER 11 /* DAC IRQ handler */ - IRQ_DEFAULT_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 18 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 19 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 20 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 21 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 22 /* UART4 IRQ handler */ - IRQ_DEFAULT_HANDLER 23 /* UART5 IRQ handler */ - IRQ_DEFAULT_HANDLER 24 /* UART6 IRQ handler */ - IRQ_DEFAULT_HANDLER 25 /* UART7 IRQ handler */ - IRQ_DEFAULT_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* PTPC IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* TSNS IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_DEFAULT_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_DEFAULT_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 48 /* SDP IRQ handler */ - IRQ_DEFAULT_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 51 /* XDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* FEMC IRQ handler */ - IRQ_DEFAULT_HANDLER 54 /* RNG IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_DEFAULT_HANDLER 57 /* DAO IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* PDM IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* FFA IRQ handler */ - IRQ_DEFAULT_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 61 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* PWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* RTC IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* BUTN IRQ handler */ - IRQ_DEFAULT_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 74 /* BVIO IRQ handler */ - IRQ_DEFAULT_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 78 /* DEBUG[1] IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(9) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_HANDLER 11 /* DAC IRQ handler */ - IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_HANDLER 18 /* UART0 IRQ handler */ - IRQ_HANDLER 19 /* UART1 IRQ handler */ - IRQ_HANDLER 20 /* UART2 IRQ handler */ - IRQ_HANDLER 21 /* UART3 IRQ handler */ - IRQ_HANDLER 22 /* UART4 IRQ handler */ - IRQ_HANDLER 23 /* UART5 IRQ handler */ - IRQ_HANDLER 24 /* UART6 IRQ handler */ - IRQ_HANDLER 25 /* UART7 IRQ handler */ - IRQ_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_HANDLER 28 /* PTPC IRQ handler */ - IRQ_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_HANDLER 31 /* TSNS IRQ handler */ - IRQ_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_HANDLER 48 /* SDP IRQ handler */ - IRQ_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_HANDLER 51 /* XDMA IRQ handler */ - IRQ_HANDLER 52 /* HDMA IRQ handler */ - IRQ_HANDLER 53 /* FEMC IRQ handler */ - IRQ_HANDLER 54 /* RNG IRQ handler */ - IRQ_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_HANDLER 57 /* DAO IRQ handler */ - IRQ_HANDLER 58 /* PDM IRQ handler */ - IRQ_HANDLER 59 /* FFA IRQ handler */ - IRQ_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_HANDLER 61 /* USB0 IRQ handler */ - IRQ_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_HANDLER 64 /* PSEC IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PWDG IRQ handler */ - IRQ_HANDLER 67 /* PTMR IRQ handler */ - IRQ_HANDLER 68 /* PUART IRQ handler */ - IRQ_HANDLER 69 /* FUSE IRQ handler */ - IRQ_HANDLER 70 /* SECMON IRQ handler */ - IRQ_HANDLER 71 /* RTC IRQ handler */ - IRQ_HANDLER 72 /* BUTN IRQ handler */ - IRQ_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_HANDLER 74 /* BVIO IRQ handler */ - IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_HANDLER 11 /* DAC IRQ handler */ - IRQ_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_HANDLER 18 /* UART0 IRQ handler */ - IRQ_HANDLER 19 /* UART1 IRQ handler */ - IRQ_HANDLER 20 /* UART2 IRQ handler */ - IRQ_HANDLER 21 /* UART3 IRQ handler */ - IRQ_HANDLER 22 /* UART4 IRQ handler */ - IRQ_HANDLER 23 /* UART5 IRQ handler */ - IRQ_HANDLER 24 /* UART6 IRQ handler */ - IRQ_HANDLER 25 /* UART7 IRQ handler */ - IRQ_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_HANDLER 28 /* PTPC IRQ handler */ - IRQ_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_HANDLER 31 /* TSNS IRQ handler */ - IRQ_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_HANDLER 48 /* SDP IRQ handler */ - IRQ_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_HANDLER 51 /* XDMA IRQ handler */ - IRQ_HANDLER 52 /* HDMA IRQ handler */ - IRQ_HANDLER 53 /* FEMC IRQ handler */ - IRQ_HANDLER 54 /* RNG IRQ handler */ - IRQ_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_HANDLER 57 /* DAO IRQ handler */ - IRQ_HANDLER 58 /* PDM IRQ handler */ - IRQ_HANDLER 59 /* FFA IRQ handler */ - IRQ_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_HANDLER 61 /* USB0 IRQ handler */ - IRQ_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_HANDLER 64 /* PSEC IRQ handler */ - IRQ_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_HANDLER 66 /* PWDG IRQ handler */ - IRQ_HANDLER 67 /* PTMR IRQ handler */ - IRQ_HANDLER 68 /* PUART IRQ handler */ - IRQ_HANDLER 69 /* FUSE IRQ handler */ - IRQ_HANDLER 70 /* SECMON IRQ handler */ - IRQ_HANDLER 71 /* RTC IRQ handler */ - IRQ_HANDLER 72 /* BUTN IRQ handler */ - IRQ_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_HANDLER 74 /* BVIO IRQ handler */ - IRQ_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 78 /* DEBUG[1] IRQ handler */ - -#endif - -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_S_HANDLER macro - dc32 default_isr_s_\1 - endm - -IRQ_DEFAULT_S_HANDLER macro - PUBWEAK default_isr_s_\1 -default_isr_s_\1 - j default_irq_s_handler - endm - - SECTION `.isr_s_vector`:CODE:ROOT(9) - PUBWEAK default_irq_s_handler -default_irq_s_handler - j default_irq_s_handler - IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_S_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 11 /* DAC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 18 /* UART0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 19 /* UART1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 20 /* UART2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 21 /* UART3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 22 /* UART4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 23 /* UART5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 24 /* UART6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 25 /* UART7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 28 /* PTPC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 31 /* TSNS IRQ handler */ - IRQ_DEFAULT_S_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 48 /* SDP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 51 /* XDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 52 /* HDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 53 /* FEMC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 54 /* RNG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 57 /* DAO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 58 /* PDM IRQ handler */ - IRQ_DEFAULT_S_HANDLER 59 /* FFA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 61 /* USB0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 64 /* PSEC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 66 /* PWDG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 67 /* PTMR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 68 /* PUART IRQ handler */ - IRQ_DEFAULT_S_HANDLER 69 /* FUSE IRQ handler */ - IRQ_DEFAULT_S_HANDLER 70 /* SECMON IRQ handler */ - IRQ_DEFAULT_S_HANDLER 71 /* RTC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 72 /* BUTN IRQ handler */ - IRQ_DEFAULT_S_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 74 /* BVIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_S_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_S_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 78 /* DEBUG[1] IRQ handler */ - - EXTERN irq_handler_s_trap - SECTION `.vector_s_table`:CODE:ROOT(9) - PUBLIC __vector_s_table - DATA - -__vector_s_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_s_trap -#endif - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_S_HANDLER 11 /* DAC IRQ handler */ - IRQ_S_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_S_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_S_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 18 /* UART0 IRQ handler */ - IRQ_S_HANDLER 19 /* UART1 IRQ handler */ - IRQ_S_HANDLER 20 /* UART2 IRQ handler */ - IRQ_S_HANDLER 21 /* UART3 IRQ handler */ - IRQ_S_HANDLER 22 /* UART4 IRQ handler */ - IRQ_S_HANDLER 23 /* UART5 IRQ handler */ - IRQ_S_HANDLER 24 /* UART6 IRQ handler */ - IRQ_S_HANDLER 25 /* UART7 IRQ handler */ - IRQ_S_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_S_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_S_HANDLER 28 /* PTPC IRQ handler */ - IRQ_S_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_S_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_S_HANDLER 31 /* TSNS IRQ handler */ - IRQ_S_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_S_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_S_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_S_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_S_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_S_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_S_HANDLER 48 /* SDP IRQ handler */ - IRQ_S_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_S_HANDLER 51 /* XDMA IRQ handler */ - IRQ_S_HANDLER 52 /* HDMA IRQ handler */ - IRQ_S_HANDLER 53 /* FEMC IRQ handler */ - IRQ_S_HANDLER 54 /* RNG IRQ handler */ - IRQ_S_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_S_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_S_HANDLER 57 /* DAO IRQ handler */ - IRQ_S_HANDLER 58 /* PDM IRQ handler */ - IRQ_S_HANDLER 59 /* FFA IRQ handler */ - IRQ_S_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_S_HANDLER 61 /* USB0 IRQ handler */ - IRQ_S_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_S_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_S_HANDLER 64 /* PSEC IRQ handler */ - IRQ_S_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 66 /* PWDG IRQ handler */ - IRQ_S_HANDLER 67 /* PTMR IRQ handler */ - IRQ_S_HANDLER 68 /* PUART IRQ handler */ - IRQ_S_HANDLER 69 /* FUSE IRQ handler */ - IRQ_S_HANDLER 70 /* SECMON IRQ handler */ - IRQ_S_HANDLER 71 /* RTC IRQ handler */ - IRQ_S_HANDLER 72 /* BUTN IRQ handler */ - IRQ_S_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 74 /* BVIO IRQ handler */ - IRQ_S_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_S_HANDLER 78 /* DEBUG[1] IRQ handler */ - -#else - -.global default_irq_s_handler -.weak default_irq_s_handler -.align 2 -default_irq_s_handler: -1: j 1b - -.macro IRQ_S_HANDLER irq - .weak default_isr_s_\irq - .set default_isr_s_\irq, default_irq_s_handler - .long default_isr_s_\irq -.endm - -.section .vector_s_table, "a" -.global __vector_s_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_s_trap, freertos_risc_v_trap_handler -#else - .set default_isr_s_trap, irq_handler_s_trap -#endif - -__vector_s_table: - .weak default_isr_s_trap - .long default_isr_s_trap - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 8 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 9 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 10 /* ADC2 IRQ handler */ - IRQ_S_HANDLER 11 /* DAC IRQ handler */ - IRQ_S_HANDLER 12 /* ACMP[0] IRQ handler */ - IRQ_S_HANDLER 13 /* ACMP[1] IRQ handler */ - IRQ_S_HANDLER 14 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 15 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 16 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 17 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 18 /* UART0 IRQ handler */ - IRQ_S_HANDLER 19 /* UART1 IRQ handler */ - IRQ_S_HANDLER 20 /* UART2 IRQ handler */ - IRQ_S_HANDLER 21 /* UART3 IRQ handler */ - IRQ_S_HANDLER 22 /* UART4 IRQ handler */ - IRQ_S_HANDLER 23 /* UART5 IRQ handler */ - IRQ_S_HANDLER 24 /* UART6 IRQ handler */ - IRQ_S_HANDLER 25 /* UART7 IRQ handler */ - IRQ_S_HANDLER 26 /* CAN0 IRQ handler */ - IRQ_S_HANDLER 27 /* CAN1 IRQ handler */ - IRQ_S_HANDLER 28 /* PTPC IRQ handler */ - IRQ_S_HANDLER 29 /* WDG0 IRQ handler */ - IRQ_S_HANDLER 30 /* WDG1 IRQ handler */ - IRQ_S_HANDLER 31 /* TSNS IRQ handler */ - IRQ_S_HANDLER 32 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 33 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 34 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 35 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 36 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 37 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 38 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 39 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 40 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 41 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 42 /* PWM0 IRQ handler */ - IRQ_S_HANDLER 43 /* HALL0 IRQ handler */ - IRQ_S_HANDLER 44 /* QEI0 IRQ handler */ - IRQ_S_HANDLER 45 /* PWM1 IRQ handler */ - IRQ_S_HANDLER 46 /* HALL1 IRQ handler */ - IRQ_S_HANDLER 47 /* QEI1 IRQ handler */ - IRQ_S_HANDLER 48 /* SDP IRQ handler */ - IRQ_S_HANDLER 49 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 50 /* XPI1 IRQ handler */ - IRQ_S_HANDLER 51 /* XDMA IRQ handler */ - IRQ_S_HANDLER 52 /* HDMA IRQ handler */ - IRQ_S_HANDLER 53 /* FEMC IRQ handler */ - IRQ_S_HANDLER 54 /* RNG IRQ handler */ - IRQ_S_HANDLER 55 /* I2S0 IRQ handler */ - IRQ_S_HANDLER 56 /* I2S1 IRQ handler */ - IRQ_S_HANDLER 57 /* DAO IRQ handler */ - IRQ_S_HANDLER 58 /* PDM IRQ handler */ - IRQ_S_HANDLER 59 /* FFA IRQ handler */ - IRQ_S_HANDLER 60 /* NTMR0 IRQ handler */ - IRQ_S_HANDLER 61 /* USB0 IRQ handler */ - IRQ_S_HANDLER 62 /* ENET0 IRQ handler */ - IRQ_S_HANDLER 63 /* SDXC0 IRQ handler */ - IRQ_S_HANDLER 64 /* PSEC IRQ handler */ - IRQ_S_HANDLER 65 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 66 /* PWDG IRQ handler */ - IRQ_S_HANDLER 67 /* PTMR IRQ handler */ - IRQ_S_HANDLER 68 /* PUART IRQ handler */ - IRQ_S_HANDLER 69 /* FUSE IRQ handler */ - IRQ_S_HANDLER 70 /* SECMON IRQ handler */ - IRQ_S_HANDLER 71 /* RTC IRQ handler */ - IRQ_S_HANDLER 72 /* BUTN IRQ handler */ - IRQ_S_HANDLER 73 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 74 /* BVIO IRQ handler */ - IRQ_S_HANDLER 75 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 76 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 77 /* DEBUG[0] IRQ handler */ - IRQ_S_HANDLER 78 /* DEBUG[1] IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_acmp_regs.h deleted file mode 100644 index 9f7e0b6d9cd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_acmp_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ACMP_H -#define HPM_ACMP_H - -typedef struct { - struct { - __RW uint32_t CFG; /* 0x0: Configure Register */ - __RW uint32_t DACCFG; /* 0x4: DAC configure register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t SR; /* 0x10: Status register */ - __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */ - __RW uint32_t DMAEN; /* 0x18: DMA request enable register */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - } CHANNEL[4]; -} ACMP_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CFG */ -/* - * HYST (RW) - * - * This bitfield configure the comparator hysteresis. - * 00: Hysteresis level 0 - * 01: Hysteresis level 1 - * 10: Hysteresis level 2 - * 11: Hysteresis level 3 - */ -#define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) -#define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) -#define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) -#define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) - -/* - * DACEN (RW) - * - * This bit enable the comparator internal DAC - * 0: DAC disabled - * 1: DAC enabled - */ -#define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) -#define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) -#define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) -#define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) - -/* - * HPMODE (RW) - * - * This bit enable the comparator high performance mode. - * 0: HP mode disabled - * 1: HP mode enabled - */ -#define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) -#define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) -#define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) -#define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) - -/* - * CMPEN (RW) - * - * This bit enable the comparator. - * 0: ACMP disabled - * 1: ACMP enabled - */ -#define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) -#define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) -#define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) -#define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) - -/* - * MINSEL (RW) - * - * PIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) -#define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) -#define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) -#define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) - -/* - * PINSEL (RW) - * - * MIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) -#define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) -#define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) -#define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) - -/* - * CMPOEN (RW) - * - * This bit enable the comparator output on pad. - * 0: ACMP output disabled - * 1: ACMP output enabled - */ -#define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) -#define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) -#define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) -#define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) - -/* - * FLTBYPS (RW) - * - * This bit bypass the comparator output digital filter. - * 0: The ACMP output need pass digital filter - * 1: The ACMP output digital filter is bypassed. - */ -#define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) -#define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) -#define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) -#define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) - -/* - * WINEN (RW) - * - * This bit enable the comparator window mode. - * 0: Window mode is disabled - * 1: Window mode is enabled - */ -#define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) -#define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) -#define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) -#define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) - -/* - * OPOL (RW) - * - * The output polarity control bit. - * 0: The ACMP output remain un-changed. - * 1: The ACMP output is inverted. - */ -#define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) -#define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) -#define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) -#define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) - -/* - * FLTMODE (RW) - * - * This bitfield define the ACMP output digital filter mode: - * 000-bypass - * 100-change immediately; - * 101-change after filter; - * 110-stalbe low; - * 111-stable high - */ -#define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) -#define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) -#define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) -#define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) - -/* - * SYNCEN (RW) - * - * This bit enable the comparator output synchronization. - * 0: ACMP output not synchronized with ACMP clock. - * 1: ACMP output synchronized with ACMP clock. - */ -#define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) -#define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) -#define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) -#define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) - -/* - * FLTLEN (RW) - * - * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - */ -#define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) -#define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) -#define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) -#define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DACCFG */ -/* - * DACCFG (RW) - * - * 8bit DAC digital value output to analog block - */ -#define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) -#define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) -#define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) -#define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: SR */ -/* - * FEDGF (RW) - * - * Output falling edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) -#define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) -#define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) -#define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) - -/* - * REDGF (RW) - * - * Output rising edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) -#define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) -#define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) -#define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: IRQEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DMAEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) - - - -/* CHANNEL register group index macro definition */ -#define ACMP_CHANNEL_CHN0 (0UL) -#define ACMP_CHANNEL_CHN1 (1UL) -#define ACMP_CHANNEL_CHN2 (2UL) -#define ACMP_CHANNEL_CHN3 (3UL) - - -#endif /* HPM_ACMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_adc16_regs.h deleted file mode 100644 index f4f754a8910..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_adc16_regs.h +++ /dev/null @@ -1,975 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC16_H -#define HPM_ADC16_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ - __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint8_t RESERVED3[4]; /* 0x808 - 0x80B: Reserved */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __R uint8_t RESERVED4[944]; /* 0x850 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[16]; - __R uint8_t RESERVED5[768]; /* 0xD00 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */ - __R uint8_t RESERVED6[196]; /* 0x1040 - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED7[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __R uint8_t RESERVED8[232]; /* 0x1118 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __R uint8_t RESERVED9[12]; /* 0x1204 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ - __R uint8_t RESERVED10[492]; /* 0x1214 - 0x13FF: Reserved */ - __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ - __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ - __R uint8_t RESERVED11[24]; /* 0x1448 - 0x145F: Reserved */ - __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ -} ADC16_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) -#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC16_CONFIG_INTEN3_SHIFT (29U) -#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) -#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC16_CONFIG_CHAN3_SHIFT (24U) -#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) -#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC16_CONFIG_INTEN2_SHIFT (21U) -#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) -#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC16_CONFIG_CHAN2_SHIFT (16U) -#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) -#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC16_CONFIG_INTEN1_MASK (0x2000U) -#define ADC16_CONFIG_INTEN1_SHIFT (13U) -#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) -#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC16_CONFIG_CHAN1_SHIFT (8U) -#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) -#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) - -/* - * QUEUE_EN (RW) - * - * preemption queue enable control - */ -#define ADC16_CONFIG_QUEUE_EN_MASK (0x40U) -#define ADC16_CONFIG_QUEUE_EN_SHIFT (6U) -#define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK) -#define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC16_CONFIG_INTEN0_MASK (0x20U) -#define ADC16_CONFIG_INTEN0_SHIFT (5U) -#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) -#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC16_CONFIG_CHAN0_MASK (0x1FU) -#define ADC16_CONFIG_CHAN0_SHIFT (0U) -#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) -#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC16_BUS_RESULT_VALID_SHIFT (16U) -#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) -#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) -#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) -#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample clock number - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); - * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - */ -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* - * PORT3_REALTIME (RW) - * - * set to enable trg queue stop other queues - */ -#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) -#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) -#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) -#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) -#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) -#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) -#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) -#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_STS_WDOG_MASK (0xFFFFU) -#define ADC16_INT_STS_WDOG_SHIFT (0U) -#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) -#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) -#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) -#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) -#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) -#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) -#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) -#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_EN_WDOG_MASK (0xFFFFU) -#define ADC16_INT_EN_WDOG_SHIFT (0U) -#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) -#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * ADC_CLK_ON (RW) - * - * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. - * MUST set clock_period to 0 or 1 for adc16 reg access - */ -#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) -#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC16_ANA_STATUS_CALON_MASK (0x80U) -#define ADC16_ANA_STATUS_CALON_SHIFT (7U) -#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) -#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) - -/* Bitfield definition for register array: ADC16_PARAMS */ -/* - * PARAM_VAL (RW) - * - */ -#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) -#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG0 */ -/* - * REG_EN (RW) - * - * set to enable regulator - */ -#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) -#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) -#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) -#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) - -/* - * BANDGAP_EN (RW) - * - * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - */ -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) - -/* - * CAL_AVG_CFG (RW) - * - * for average the calibration result. - * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; - * 4- 16 loops; 5-32 loops; others reserved - */ -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) - -/* - * PREEMPT_EN (RW) - * - * set to enable preemption feature - */ -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) - -/* - * CONV_PARAM (RW) - * - * conversion parameter - */ -#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG1 */ -/* - * COV_END_CNT (RW) - * - * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number+1). - */ -#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC16_CONFIG_TRG0A (0UL) -#define ADC16_CONFIG_TRG0B (1UL) -#define ADC16_CONFIG_TRG0C (2UL) -#define ADC16_CONFIG_TRG1A (3UL) -#define ADC16_CONFIG_TRG1B (4UL) -#define ADC16_CONFIG_TRG1C (5UL) -#define ADC16_CONFIG_TRG2A (6UL) -#define ADC16_CONFIG_TRG2B (7UL) -#define ADC16_CONFIG_TRG2C (8UL) -#define ADC16_CONFIG_TRG3A (9UL) -#define ADC16_CONFIG_TRG3B (10UL) -#define ADC16_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC16_BUS_RESULT_CHN0 (0UL) -#define ADC16_BUS_RESULT_CHN1 (1UL) -#define ADC16_BUS_RESULT_CHN2 (2UL) -#define ADC16_BUS_RESULT_CHN3 (3UL) -#define ADC16_BUS_RESULT_CHN4 (4UL) -#define ADC16_BUS_RESULT_CHN5 (5UL) -#define ADC16_BUS_RESULT_CHN6 (6UL) -#define ADC16_BUS_RESULT_CHN7 (7UL) -#define ADC16_BUS_RESULT_CHN8 (8UL) -#define ADC16_BUS_RESULT_CHN9 (9UL) -#define ADC16_BUS_RESULT_CHN10 (10UL) -#define ADC16_BUS_RESULT_CHN11 (11UL) -#define ADC16_BUS_RESULT_CHN12 (12UL) -#define ADC16_BUS_RESULT_CHN13 (13UL) -#define ADC16_BUS_RESULT_CHN14 (14UL) -#define ADC16_BUS_RESULT_CHN15 (15UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC16_SEQ_QUE_CFG0 (0UL) -#define ADC16_SEQ_QUE_CFG1 (1UL) -#define ADC16_SEQ_QUE_CFG2 (2UL) -#define ADC16_SEQ_QUE_CFG3 (3UL) -#define ADC16_SEQ_QUE_CFG4 (4UL) -#define ADC16_SEQ_QUE_CFG5 (5UL) -#define ADC16_SEQ_QUE_CFG6 (6UL) -#define ADC16_SEQ_QUE_CFG7 (7UL) -#define ADC16_SEQ_QUE_CFG8 (8UL) -#define ADC16_SEQ_QUE_CFG9 (9UL) -#define ADC16_SEQ_QUE_CFG10 (10UL) -#define ADC16_SEQ_QUE_CFG11 (11UL) -#define ADC16_SEQ_QUE_CFG12 (12UL) -#define ADC16_SEQ_QUE_CFG13 (13UL) -#define ADC16_SEQ_QUE_CFG14 (14UL) -#define ADC16_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC16_PRD_CFG_CHN0 (0UL) -#define ADC16_PRD_CFG_CHN1 (1UL) -#define ADC16_PRD_CFG_CHN2 (2UL) -#define ADC16_PRD_CFG_CHN3 (3UL) -#define ADC16_PRD_CFG_CHN4 (4UL) -#define ADC16_PRD_CFG_CHN5 (5UL) -#define ADC16_PRD_CFG_CHN6 (6UL) -#define ADC16_PRD_CFG_CHN7 (7UL) -#define ADC16_PRD_CFG_CHN8 (8UL) -#define ADC16_PRD_CFG_CHN9 (9UL) -#define ADC16_PRD_CFG_CHN10 (10UL) -#define ADC16_PRD_CFG_CHN11 (11UL) -#define ADC16_PRD_CFG_CHN12 (12UL) -#define ADC16_PRD_CFG_CHN13 (13UL) -#define ADC16_PRD_CFG_CHN14 (14UL) -#define ADC16_PRD_CFG_CHN15 (15UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC16_SAMPLE_CFG_CHN0 (0UL) -#define ADC16_SAMPLE_CFG_CHN1 (1UL) -#define ADC16_SAMPLE_CFG_CHN2 (2UL) -#define ADC16_SAMPLE_CFG_CHN3 (3UL) -#define ADC16_SAMPLE_CFG_CHN4 (4UL) -#define ADC16_SAMPLE_CFG_CHN5 (5UL) -#define ADC16_SAMPLE_CFG_CHN6 (6UL) -#define ADC16_SAMPLE_CFG_CHN7 (7UL) -#define ADC16_SAMPLE_CFG_CHN8 (8UL) -#define ADC16_SAMPLE_CFG_CHN9 (9UL) -#define ADC16_SAMPLE_CFG_CHN10 (10UL) -#define ADC16_SAMPLE_CFG_CHN11 (11UL) -#define ADC16_SAMPLE_CFG_CHN12 (12UL) -#define ADC16_SAMPLE_CFG_CHN13 (13UL) -#define ADC16_SAMPLE_CFG_CHN14 (14UL) -#define ADC16_SAMPLE_CFG_CHN15 (15UL) - -/* ADC16_PARAMS register group index macro definition */ -#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) - - -#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bacc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bacc_regs.h deleted file mode 100644 index 597f50ed16c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bacc_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BACC_H -#define HPM_BACC_H - -typedef struct { - __RW uint32_t CONFIG; /* 0x0: Access timing for access */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t PRE_TIME; /* 0x8: Timing gap before rising edge */ - __RW uint32_t POST_TIME; /* 0xC: Timing gap after rising edge */ -} BACC_Type; - - -/* Bitfield definition for register: CONFIG */ -/* - * FAST_WRITE (RW) - * - * Use fast write - * 0: Write normally - * 1: boost write - */ -#define BACC_CONFIG_FAST_WRITE_MASK (0x20000000UL) -#define BACC_CONFIG_FAST_WRITE_SHIFT (29U) -#define BACC_CONFIG_FAST_WRITE_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_WRITE_SHIFT) & BACC_CONFIG_FAST_WRITE_MASK) -#define BACC_CONFIG_FAST_WRITE_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_WRITE_MASK) >> BACC_CONFIG_FAST_WRITE_SHIFT) - -/* - * FAST_READ (RW) - * - * Use fast read - * 0: Read normally - * 1: boost read - */ -#define BACC_CONFIG_FAST_READ_MASK (0x10000000UL) -#define BACC_CONFIG_FAST_READ_SHIFT (28U) -#define BACC_CONFIG_FAST_READ_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_READ_SHIFT) & BACC_CONFIG_FAST_READ_MASK) -#define BACC_CONFIG_FAST_READ_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_READ_MASK) >> BACC_CONFIG_FAST_READ_SHIFT) - -/* - * TIMING (RW) - * - * Time in APB clock cycles, for battery timing penerate - */ -#define BACC_CONFIG_TIMING_MASK (0xFFFFU) -#define BACC_CONFIG_TIMING_SHIFT (0U) -#define BACC_CONFIG_TIMING_SET(x) (((uint32_t)(x) << BACC_CONFIG_TIMING_SHIFT) & BACC_CONFIG_TIMING_MASK) -#define BACC_CONFIG_TIMING_GET(x) (((uint32_t)(x) & BACC_CONFIG_TIMING_MASK) >> BACC_CONFIG_TIMING_SHIFT) - -/* Bitfield definition for register: PRE_TIME */ -/* - * PRE_RATIO (RW) - * - * Ratio of guard band before rising edge - * 0: 0 - * 1: 1/32768 of low level width - * 2: 1/16384 of low level width - * 14: 1/4 of low level width - * 15: 1/2 of low level width - */ -#define BACC_PRE_TIME_PRE_RATIO_MASK (0xF0000UL) -#define BACC_PRE_TIME_PRE_RATIO_SHIFT (16U) -#define BACC_PRE_TIME_PRE_RATIO_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_RATIO_SHIFT) & BACC_PRE_TIME_PRE_RATIO_MASK) -#define BACC_PRE_TIME_PRE_RATIO_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_RATIO_MASK) >> BACC_PRE_TIME_PRE_RATIO_SHIFT) - -/* - * PRE_OFFSET (RW) - * - * guard band before rising edge - * this value will be added to ratio number - */ -#define BACC_PRE_TIME_PRE_OFFSET_MASK (0xFFFFU) -#define BACC_PRE_TIME_PRE_OFFSET_SHIFT (0U) -#define BACC_PRE_TIME_PRE_OFFSET_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_OFFSET_SHIFT) & BACC_PRE_TIME_PRE_OFFSET_MASK) -#define BACC_PRE_TIME_PRE_OFFSET_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_OFFSET_MASK) >> BACC_PRE_TIME_PRE_OFFSET_SHIFT) - -/* Bitfield definition for register: POST_TIME */ -/* - * POST_RATIO (RW) - * - * Ratio of guard band after rising edge - * 0: 0 - * 1: 1/32768 of high level width - * 2: 1/16384 of high level width - * 14: 1/4 of high level width - * 15: 1/2 of high level width - */ -#define BACC_POST_TIME_POST_RATIO_MASK (0xF0000UL) -#define BACC_POST_TIME_POST_RATIO_SHIFT (16U) -#define BACC_POST_TIME_POST_RATIO_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_RATIO_SHIFT) & BACC_POST_TIME_POST_RATIO_MASK) -#define BACC_POST_TIME_POST_RATIO_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_RATIO_MASK) >> BACC_POST_TIME_POST_RATIO_SHIFT) - -/* - * POST_OFFSET (RW) - * - * guard band after rising edge - * this value will be added to ratio number - */ -#define BACC_POST_TIME_POST_OFFSET_MASK (0xFFFFU) -#define BACC_POST_TIME_POST_OFFSET_SHIFT (0U) -#define BACC_POST_TIME_POST_OFFSET_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_OFFSET_SHIFT) & BACC_POST_TIME_POST_OFFSET_MASK) -#define BACC_POST_TIME_POST_OFFSET_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_OFFSET_MASK) >> BACC_POST_TIME_POST_OFFSET_SHIFT) - - - - -#endif /* HPM_BACC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bcfg_regs.h deleted file mode 100644 index 56355a5e012..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bcfg_regs.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BCFG_H -#define HPM_BCFG_H - -typedef struct { - __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ - __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ - __RW uint32_t CLK_CFG; /* 0x10: Clock config */ -} BCFG_Type; - - -/* Bitfield definition for register: VBG_CFG */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) -#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) -#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) -#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) - -/* - * LP_MODE (RW) - * - * Bandgap works in low power mode - * 0: not in low power mode - * 1: bandgap work in low power mode - */ -#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) -#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) -#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) -#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Bandgap works in power save mode - * 0: not in power save mode - * 1: bandgap work in power save mode - */ -#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) -#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) -#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) -#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) - -/* - * VBG_1P0 (RW) - * - * Bandgap 1.0V output trim - */ -#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) -#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) -#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) -#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) - -/* - * VBG_P65 (RW) - * - * Bandgap 0.65V output trim - */ -#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) -#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) -#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) -#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) - -/* - * VBG_P50 (RW) - * - * Bandgap 0.50V output trim - */ -#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) -#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) -#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) -#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) - -/* Bitfield definition for register: IRC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) -#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: XTAL32K_CFG */ -/* - * HYST_EN (RW) - * - * crystal 32k hysteres enable - */ -#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) -#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) -#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) -#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) - -/* - * GMSEL (RW) - * - * crystal 32k gm selection - */ -#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) -#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) -#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) -#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) - -/* - * CFG (RW) - * - * crystal 32k config - */ -#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) -#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) -#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) -#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) - -/* - * AMP (RW) - * - * crystal 32k amplifier - */ -#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) -#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) -#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) -#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) - -/* Bitfield definition for register: CLK_CFG */ -/* - * XTAL_SEL (RO) - * - * crystal selected - */ -#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) -#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) -#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) - -/* - * KEEP_IRC (RW) - * - * force irc32k run - */ -#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) -#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) -#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) -#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) - -/* - * FORCE_XTAL (RW) - * - * force switch to crystal - */ -#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) -#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) -#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) -#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) - - - - -#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bgpr_regs.h deleted file mode 100644 index 9d81aab19cf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bgpr_regs.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BGPR_H -#define HPM_BGPR_H - -typedef struct { - __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ -} BGPR_Type; - - -/* Bitfield definition for register array: GPR */ -/* - * DATA (RW) - * - * Generic control - */ -#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) -#define BGPR_GPR_DATA_SHIFT (0U) -#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) -#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) - - - -/* GPR register group index macro definition */ -#define BGPR_GPR_0 (0UL) -#define BGPR_GPR_1 (1UL) -#define BGPR_GPR_2 (2UL) -#define BGPR_GPR_3 (3UL) -#define BGPR_GPR_4 (4UL) -#define BGPR_GPR_5 (5UL) -#define BGPR_GPR_6 (6UL) -#define BGPR_GPR_7 (7UL) - - -#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bkey_regs.h deleted file mode 100644 index 1c82a4b90e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bkey_regs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BKEY_H -#define HPM_BKEY_H - -typedef struct { - struct { - __RW uint32_t DATA[8]; /* 0x0 - 0x1C: Key data */ - } KEY[2]; - __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ - __RW uint32_t SELECT; /* 0x48: Key selection */ -} BKEY_Type; - - -/* Bitfield definition for register of struct array KEY: 0 */ -/* - * DATA (RW) - * - * security key data - */ -#define BKEY_KEY_DATA_DATA_MASK (0xFFFFFFFFUL) -#define BKEY_KEY_DATA_DATA_SHIFT (0U) -#define BKEY_KEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_KEY_DATA_DATA_SHIFT) & BKEY_KEY_DATA_DATA_MASK) -#define BKEY_KEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_KEY_DATA_DATA_MASK) >> BKEY_KEY_DATA_DATA_SHIFT) - -/* Bitfield definition for register array: ECC */ -/* - * WLOCK (RW) - * - * write lock to key0 - * 0: write enable - * 1: write ignored - */ -#define BKEY_ECC_WLOCK_MASK (0x80000000UL) -#define BKEY_ECC_WLOCK_SHIFT (31U) -#define BKEY_ECC_WLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_WLOCK_SHIFT) & BKEY_ECC_WLOCK_MASK) -#define BKEY_ECC_WLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_WLOCK_MASK) >> BKEY_ECC_WLOCK_SHIFT) - -/* - * RLOCK (RW) - * - * read lock to key0 - * 0: key read enable - * 1: key always read as 0 - */ -#define BKEY_ECC_RLOCK_MASK (0x40000000UL) -#define BKEY_ECC_RLOCK_SHIFT (30U) -#define BKEY_ECC_RLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_RLOCK_SHIFT) & BKEY_ECC_RLOCK_MASK) -#define BKEY_ECC_RLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_RLOCK_MASK) >> BKEY_ECC_RLOCK_SHIFT) - -/* - * ECC (RW) - * - * Parity check bits for key0 - */ -#define BKEY_ECC_ECC_MASK (0xFFFFU) -#define BKEY_ECC_ECC_SHIFT (0U) -#define BKEY_ECC_ECC_SET(x) (((uint32_t)(x) << BKEY_ECC_ECC_SHIFT) & BKEY_ECC_ECC_MASK) -#define BKEY_ECC_ECC_GET(x) (((uint32_t)(x) & BKEY_ECC_ECC_MASK) >> BKEY_ECC_ECC_SHIFT) - -/* Bitfield definition for register: SELECT */ -/* - * SELECT (RW) - * - * select key, key0 treated as secure key, in non-scure mode, only key1 can be selected - * 0: select key0 in secure mode, key1 in non-secure mode - * 1: select key1 in secure or nonsecure mode - */ -#define BKEY_SELECT_SELECT_MASK (0x1U) -#define BKEY_SELECT_SELECT_SHIFT (0U) -#define BKEY_SELECT_SELECT_SET(x) (((uint32_t)(x) << BKEY_SELECT_SELECT_SHIFT) & BKEY_SELECT_SELECT_MASK) -#define BKEY_SELECT_SELECT_GET(x) (((uint32_t)(x) & BKEY_SELECT_SELECT_MASK) >> BKEY_SELECT_SELECT_SHIFT) - - - -/* DATA register group index macro definition */ -#define BKEY_KEY_DATA_0 (0UL) -#define BKEY_KEY_DATA_1 (1UL) -#define BKEY_KEY_DATA_2 (2UL) -#define BKEY_KEY_DATA_3 (3UL) -#define BKEY_KEY_DATA_4 (4UL) -#define BKEY_KEY_DATA_5 (5UL) -#define BKEY_KEY_DATA_6 (6UL) -#define BKEY_KEY_DATA_7 (7UL) - -/* KEY register group index macro definition */ -#define BKEY_KEY_0 (0UL) -#define BKEY_KEY_1 (1UL) - -/* ECC register group index macro definition */ -#define BKEY_ECC_KEY0 (0UL) -#define BKEY_ECC_KEY1 (1UL) - - -#endif /* HPM_BKEY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bmon_regs.h deleted file mode 100644 index f297a1dbb93..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bmon_regs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BMON_H -#define HPM_BMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - } MONITOR[2]; -} BMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define BMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define BMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define BMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ACTIVE_SHIFT) & BMON_MONITOR_CONTROL_ACTIVE_MASK) -#define BMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ACTIVE_MASK) >> BMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define BMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define BMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define BMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ENABLE_SHIFT) & BMON_MONITOR_CONTROL_ENABLE_MASK) -#define BMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ENABLE_MASK) >> BMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define BMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define BMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define BMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << BMON_MONITOR_STATUS_FLAG_SHIFT) & BMON_MONITOR_STATUS_FLAG_MASK) -#define BMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & BMON_MONITOR_STATUS_FLAG_MASK) >> BMON_MONITOR_STATUS_FLAG_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define BMON_MONITOR_GLITCH0 (0UL) -#define BMON_MONITOR_CLOCK0 (1UL) - - -#endif /* HPM_BMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bpor_regs.h deleted file mode 100644 index 4f48a15578d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bpor_regs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BPOR_H -#define HPM_BPOR_H - -typedef struct { - __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ - __RW uint32_t POR_SELECT; /* 0x4: Power on select */ - __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ - __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ -} BPOR_Type; - - -/* Bitfield definition for register: POR_CAUSE */ -/* - * CAUSE (RW) - * - * Power on cause, each bit represnts one cause, write 1 to clear each bit - * bit0: wakeup button - * bit1: security violation - * bit2: RTC alarm 0 - * bit3: RTC alarm 1 - * bit4: GPIO - */ -#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) -#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) -#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) -#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: POR_SELECT */ -/* - * SELECT (RW) - * - * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause - * bit0: wakeup button - * bit1: security violation - * bit2: RTC alarm 0 - * bit3: RTC alarm 1 - * bit4: GPIO - */ -#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) -#define BPOR_POR_SELECT_SELECT_SHIFT (0U) -#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) -#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) - -/* Bitfield definition for register: POR_CONFIG */ -/* - * RETENTION (RW) - * - * retention battery domain setting - * 0: battery reset on reset pin reset happen - * 1: battery domain retention when reset pin reset happen - */ -#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) -#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) -#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) -#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) - -/* Bitfield definition for register: POR_CONTROL */ -/* - * COUNTER (RW) - * - * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - */ -#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) -#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) -#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) -#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) - - - - -#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bsec_regs.h deleted file mode 100644 index 6167b47be78..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_bsec_regs.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BSEC_H -#define HPM_BSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ -} BSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * BATT_FAIL (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U) -#define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U) -#define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK) -#define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT) - -/* - * BATT_NSC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U) -#define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U) -#define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK) -#define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT) - -/* - * BATT_SEC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U) -#define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U) -#define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK) -#define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT) - -/* - * BATT_INS (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U) -#define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U) -#define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK) -#define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define BSEC_EVENT_EVENT_SHIFT (16U) -#define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT) - -/* - * BATT_ESC_NSC (RO) - * - * BATT is escalating non-secure event - */ -#define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U) -#define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U) -#define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT) - -/* - * BATT_ESC_SEC (RO) - * - * BATT is escalting ssecure event - */ -#define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U) -#define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U) -#define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT) - - - - -#endif /* HPM_BSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_butn_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_butn_regs.h deleted file mode 100644 index 03d711e0c58..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_butn_regs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BUTN_H -#define HPM_BUTN_H - -typedef struct { - __RW uint32_t BTN_STATUS; /* 0x0: Button status */ - __RW uint32_t BTN_IRQ_MASK; /* 0x4: Button interrupt mask */ - __RW uint32_t LED_INTENSE; /* 0x8: Debounce setting */ -} BUTN_Type; - - -/* Bitfield definition for register: BTN_STATUS */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_STATUS_XWCLICK_SHIFT (28U) -#define BUTN_BTN_STATUS_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XWCLICK_SHIFT) & BUTN_BTN_STATUS_XWCLICK_MASK) -#define BUTN_BTN_STATUS_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XWCLICK_MASK) >> BUTN_BTN_STATUS_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_STATUS_WCLICK_SHIFT (24U) -#define BUTN_BTN_STATUS_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WCLICK_SHIFT) & BUTN_BTN_STATUS_WCLICK_MASK) -#define BUTN_BTN_STATUS_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WCLICK_MASK) >> BUTN_BTN_STATUS_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_STATUS_XPCLICK_SHIFT (20U) -#define BUTN_BTN_STATUS_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XPCLICK_SHIFT) & BUTN_BTN_STATUS_XPCLICK_MASK) -#define BUTN_BTN_STATUS_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XPCLICK_MASK) >> BUTN_BTN_STATUS_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_STATUS_PCLICK_SHIFT (16U) -#define BUTN_BTN_STATUS_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PCLICK_SHIFT) & BUTN_BTN_STATUS_PCLICK_MASK) -#define BUTN_BTN_STATUS_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PCLICK_MASK) >> BUTN_BTN_STATUS_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_DBTN_MASK (0xF00U) -#define BUTN_BTN_STATUS_DBTN_SHIFT (8U) -#define BUTN_BTN_STATUS_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_DBTN_SHIFT) & BUTN_BTN_STATUS_DBTN_MASK) -#define BUTN_BTN_STATUS_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_DBTN_MASK) >> BUTN_BTN_STATUS_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_WBTN_MASK (0xF0U) -#define BUTN_BTN_STATUS_WBTN_SHIFT (4U) -#define BUTN_BTN_STATUS_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WBTN_SHIFT) & BUTN_BTN_STATUS_WBTN_MASK) -#define BUTN_BTN_STATUS_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WBTN_MASK) >> BUTN_BTN_STATUS_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_PBTN_MASK (0xFU) -#define BUTN_BTN_STATUS_PBTN_SHIFT (0U) -#define BUTN_BTN_STATUS_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PBTN_SHIFT) & BUTN_BTN_STATUS_PBTN_MASK) -#define BUTN_BTN_STATUS_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PBTN_MASK) >> BUTN_BTN_STATUS_PBTN_SHIFT) - -/* Bitfield definition for register: BTN_IRQ_MASK */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT (28U) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_IRQ_MASK_WCLICK_SHIFT (24U) -#define BUTN_BTN_IRQ_MASK_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) >> BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT (20U) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_IRQ_MASK_PCLICK_SHIFT (16U) -#define BUTN_BTN_IRQ_MASK_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) >> BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_DBTN_MASK (0xF00U) -#define BUTN_BTN_IRQ_MASK_DBTN_SHIFT (8U) -#define BUTN_BTN_IRQ_MASK_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_DBTN_SHIFT) & BUTN_BTN_IRQ_MASK_DBTN_MASK) -#define BUTN_BTN_IRQ_MASK_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_DBTN_MASK) >> BUTN_BTN_IRQ_MASK_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_WBTN_MASK (0xF0U) -#define BUTN_BTN_IRQ_MASK_WBTN_SHIFT (4U) -#define BUTN_BTN_IRQ_MASK_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WBTN_SHIFT) & BUTN_BTN_IRQ_MASK_WBTN_MASK) -#define BUTN_BTN_IRQ_MASK_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WBTN_MASK) >> BUTN_BTN_IRQ_MASK_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_PBTN_MASK (0xFU) -#define BUTN_BTN_IRQ_MASK_PBTN_SHIFT (0U) -#define BUTN_BTN_IRQ_MASK_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PBTN_SHIFT) & BUTN_BTN_IRQ_MASK_PBTN_MASK) -#define BUTN_BTN_IRQ_MASK_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PBTN_MASK) >> BUTN_BTN_IRQ_MASK_PBTN_SHIFT) - -/* Bitfield definition for register: LED_INTENSE */ -/* - * RLED (RW) - * - * Rbutton brightness 0 - */ -#define BUTN_LED_INTENSE_RLED_MASK (0xF0000UL) -#define BUTN_LED_INTENSE_RLED_SHIFT (16U) -#define BUTN_LED_INTENSE_RLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_RLED_SHIFT) & BUTN_LED_INTENSE_RLED_MASK) -#define BUTN_LED_INTENSE_RLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_RLED_MASK) >> BUTN_LED_INTENSE_RLED_SHIFT) - -/* - * PLED (RW) - * - * Pbutton brightness 0 - */ -#define BUTN_LED_INTENSE_PLED_MASK (0xFU) -#define BUTN_LED_INTENSE_PLED_SHIFT (0U) -#define BUTN_LED_INTENSE_PLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_PLED_SHIFT) & BUTN_LED_INTENSE_PLED_MASK) -#define BUTN_LED_INTENSE_PLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_PLED_MASK) >> BUTN_LED_INTENSE_PLED_SHIFT) - - - - -#endif /* HPM_BUTN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_can_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_can_regs.h deleted file mode 100644 index 5da84c9ef71..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_can_regs.h +++ /dev/null @@ -1,1402 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CAN_H -#define HPM_CAN_H - -typedef struct { - __RW uint32_t RBUF[20]; /* 0x0 - 0x4C: receive buffer registers and reception time stamp */ - __RW uint32_t TBUF[18]; /* 0x50 - 0x94: transmit buffer register */ - __R uint32_t TTS[2]; /* 0x98 - 0x9C: transmission time stamp, LSB 32bit */ - __RW uint32_t CMD_STA_CMD_CTRL; /* 0xA0: config, status, command and control bits */ - __RW uint8_t RTIE; /* 0xA4: Receive and Transmit Interrupt Enable Register RTIE */ - __W uint8_t RTIF; /* 0xA5: Receive and Transmit Interrupt Flag Register RTIF (0xa5) */ - __RW uint8_t ERRINT; /* 0xA6: ERRor INTerrupt Enable and Flag Register ERRINT */ - __RW uint8_t LIMIT; /* 0xA7: Warning Limits Register LIMIT */ - __RW uint32_t S_PRESC; /* 0xA8: Bit Timing Register(Slow Speed) */ - __RW uint32_t F_PRESC; /* 0xAC: Bit Timing Register(Fast Speed) */ - __R uint8_t EALCAP; /* 0xB0: Error and Arbitration Lost Capture Register EALCAP */ - __RW uint8_t TDC; /* 0xB1: Transmitter Delay Compensation Register TDC */ - __R uint8_t RECNT; /* 0xB2: Error Counter Registers RECNT */ - __R uint8_t TECNT; /* 0xB3: Error Counter Registers TECNT */ - __RW uint8_t ACFCTRL; /* 0xB4: Acceptance Filter Control Register ACFCTRL */ - __RW uint8_t TIMECFG; /* 0xB5: CiA 603 Time-Stamping TIMECFG */ - __RW uint16_t ACF_EN; /* 0xB6: Acceptance Filter Enable ACF_EN */ - __RW uint32_t ACF; /* 0xB8: Acceptance CODE ACODE or ACMASK */ - __RW uint16_t VER; /* 0xBC: Version Information VER */ - __RW uint8_t TBSLOT; /* 0xBE: TTCAN: TB Slot Pointer TBSLOT */ - __RW uint8_t TTCFG; /* 0xBF: TTCAN: Time Trigger Configuration TTCFG */ - __RW uint32_t REF_MSG; /* 0xC0: TTCAN: Reference Message REF_MSG */ - __RW uint16_t TRIG_CFG; /* 0xC4: TTCAN: Trigger Configuration TRIG_CFG */ - __RW uint16_t TT_TRIG; /* 0xC6: TTCAN: Trigger Time TT_TRIG */ - __RW uint16_t TT_WTRIG; /* 0xC8: TTCAN: Watch Trigger Time TT_WTRIG */ -} CAN_Type; - - -/* Bitfield definition for register array: RBUF */ -/* - * RBUF (RW) - * - * receive buffer - */ -#define CAN_RBUF_RBUF_MASK (0xFFFFFFFFUL) -#define CAN_RBUF_RBUF_SHIFT (0U) -#define CAN_RBUF_RBUF_SET(x) (((uint32_t)(x) << CAN_RBUF_RBUF_SHIFT) & CAN_RBUF_RBUF_MASK) -#define CAN_RBUF_RBUF_GET(x) (((uint32_t)(x) & CAN_RBUF_RBUF_MASK) >> CAN_RBUF_RBUF_SHIFT) - -/* Bitfield definition for register array: TBUF */ -/* - * TBUF (RW) - * - * transmit buffer - */ -#define CAN_TBUF_TBUF_MASK (0xFFFFFFFFUL) -#define CAN_TBUF_TBUF_SHIFT (0U) -#define CAN_TBUF_TBUF_SET(x) (((uint32_t)(x) << CAN_TBUF_TBUF_SHIFT) & CAN_TBUF_TBUF_MASK) -#define CAN_TBUF_TBUF_GET(x) (((uint32_t)(x) & CAN_TBUF_TBUF_MASK) >> CAN_TBUF_TBUF_SHIFT) - -/* Bitfield definition for register array: TTS */ -/* - * TTS_WRD0 (RO) - * - * transmission time stamp, word 0, LSB 32bit - */ -#define CAN_TTS_TTS_WRD0_MASK (0xFFFFFFFFUL) -#define CAN_TTS_TTS_WRD0_SHIFT (0U) -#define CAN_TTS_TTS_WRD0_GET(x) (((uint32_t)(x) & CAN_TTS_TTS_WRD0_MASK) >> CAN_TTS_TTS_WRD0_SHIFT) - -/* Bitfield definition for register: CMD_STA_CMD_CTRL */ -/* - * SACK (RW) - * - * Self-ACKnowledge - * 0 – no self-ACK - * 1 – self-ACK when LBME=1 - */ -#define CAN_CMD_STA_CMD_CTRL_SACK_MASK (0x80000000UL) -#define CAN_CMD_STA_CMD_CTRL_SACK_SHIFT (31U) -#define CAN_CMD_STA_CMD_CTRL_SACK_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) -#define CAN_CMD_STA_CMD_CTRL_SACK_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) >> CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) - -/* - * ROM (RW) - * - * Receive buffer Overflow Mode - * In case of a full RBUF when a new message is received, then ROM selects the following: - * 1 – The new message will not be stored. - * 0 – The oldest message will be overwritten. - */ -#define CAN_CMD_STA_CMD_CTRL_ROM_MASK (0x40000000UL) -#define CAN_CMD_STA_CMD_CTRL_ROM_SHIFT (30U) -#define CAN_CMD_STA_CMD_CTRL_ROM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) -#define CAN_CMD_STA_CMD_CTRL_ROM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) >> CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) - -/* - * ROV (RO) - * - * Receive buffer OVerflow - * 1 – Overflow. At least one message is lost. - * 0 – No Overflow. - * ROV is cleared by setting RREL=1. - */ -#define CAN_CMD_STA_CMD_CTRL_ROV_MASK (0x20000000UL) -#define CAN_CMD_STA_CMD_CTRL_ROV_SHIFT (29U) -#define CAN_CMD_STA_CMD_CTRL_ROV_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROV_MASK) >> CAN_CMD_STA_CMD_CTRL_ROV_SHIFT) - -/* - * RREL (RW) - * - * Receive buffer RELease - * The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL - * core points to the next RB slot. RSTAT gets updated. - * 1 – Release: The host has read the RB. - * 0 – No release - */ -#define CAN_CMD_STA_CMD_CTRL_RREL_MASK (0x10000000UL) -#define CAN_CMD_STA_CMD_CTRL_RREL_SHIFT (28U) -#define CAN_CMD_STA_CMD_CTRL_RREL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) -#define CAN_CMD_STA_CMD_CTRL_RREL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) >> CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) - -/* - * RBALL (RW) - * - * Receive Buffer stores ALL data frames - * 0 – normal operation - * 1 – RB stores correct data frames as well as data frames with error - */ -#define CAN_CMD_STA_CMD_CTRL_RBALL_MASK (0x8000000UL) -#define CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT (27U) -#define CAN_CMD_STA_CMD_CTRL_RBALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) -#define CAN_CMD_STA_CMD_CTRL_RBALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) >> CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) - -/* - * RSTAT (RO) - * - * Receive buffer STATus - * 00 - empty - * 01 - > empty and < almost full (AFWL) - * 10 -  almost full (programmable threshold by AFWL) but not full and no overflow - * 11 - full (stays set in case of overflow – for overflow signaling see ROV) - */ -#define CAN_CMD_STA_CMD_CTRL_RSTAT_MASK (0x3000000UL) -#define CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT (24U) -#define CAN_CMD_STA_CMD_CTRL_RSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT) - -/* - * FD_ISO (RW) - * - * CAN FD ISO mode - * 0 - Bosch CAN FD (non-ISO) mode - * 1 - ISO CAN FD mode (ISO 11898-1:2015) - * ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. - * Both modes are incompatible and must not be mixed in one CAN network. - * This bit has no impact to CAN 2.0B. - * This bit is only writeable if RESET=1. - */ -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK (0x800000UL) -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT (23U) -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) >> CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) - -/* - * TSNEXT (RW) - * - * Transmit buffer Secondary NEXT - * 0 - no action - * 1 - STB slot filled, select next slot. - * After all frame bytes are written to the TBUF registers, the host controller has to set - * TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF - * registers to the next slot. Once a slot is marked as filled a transmission can be started - * using TSONE or TSALL. - * It is possible to set TSNEXT and TSONE or TSALL together in one write access. - * TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL - * core immediately after it was set. - * Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and - * automatically cleared. It does not do any harm. - * If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. - * TSNEXT has no meaning in TTCAN mode and is fixed to 0. - */ -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK (0x400000UL) -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT (22U) -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) - -/* - * TSMODE (RW) - * - * Transmit buffer Secondary operation MODE - * 0 - FIFO mode - * 1 - priority decision mode - * In FIFO mode frames are transmitted in the order in that they are written into the STB. - * In priority decision mode the frame with the highest priority in the STB is automatically - * transmitted first. The ID of a frame is used for the priority decision. A lower ID means a - * higher priority of a frame. A frame in the PTB has always the highest priority regardless of - * the ID. - * TSMODE shall be switched only if the STB if empty - */ -#define CAN_CMD_STA_CMD_CTRL_TSMODE_MASK (0x200000UL) -#define CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT (21U) -#define CAN_CMD_STA_CMD_CTRL_TSMODE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSMODE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) - -/* - * TTTBM (RW) - * - * TTCAN Transmit Buffer Mode - * If TTEN=0 then TTTBM is ignored, otherwise the following is valid: - * 0 - separate PTB and STB, behavior defined by TSMODE - * 1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR - * For event-driven CAN communication (TTEN=0), the system provides PTB and STB and - * the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. - * For time-triggered CAN communication (TTEN=1) with full support of all features including - * time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are - * addressable using TTPTR and TBPTR. - * For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode - * and the behavior can be selected by TSMODE. - * TTTBM shall be switched only if the TBUF is empty. - */ -#define CAN_CMD_STA_CMD_CTRL_TTTBM_MASK (0x100000UL) -#define CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT (20U) -#define CAN_CMD_STA_CMD_CTRL_TTTBM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) -#define CAN_CMD_STA_CMD_CTRL_TTTBM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) >> CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) - -/* - * TSSTAT (RO) - * - * Transmission Secondary STATus bits - * If TTEN=0 or TTTBM=0: - * 00 – STB is empty - * 01 – STB is less than or equal to half full - * 10 – STB is more than half full - * 11 – STB is full - * If the STB is disabled using STB_DISABLE, then TSSTAT=00. - * If TTEN=1 and TTTBM=1: - * 00 – PTB and STB are empty - * 01 – PTB and STB are not empty and not full - * 11 – PTB and STB are full - */ -#define CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK (0x30000UL) -#define CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT (16U) -#define CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT) - -/* - * TBSEL (RW) - * - * Transmit Buffer Select - * Selects the transmit buffer to be loaded with a message. Use the TBUF registers for - * access. TBSEL needs to be stable all the time the TBUF registers are written and when - * TSNEXT is set. - * 0 - PTB (high-priority buffer) - * 1 - STB - * The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - */ -#define CAN_CMD_STA_CMD_CTRL_TBSEL_MASK (0x8000U) -#define CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT (15U) -#define CAN_CMD_STA_CMD_CTRL_TBSEL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) -#define CAN_CMD_STA_CMD_CTRL_TBSEL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) >> CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) - -/* - * LOM (RW) - * - * Listen Only Mode - * 0 - Disabled - * 1 - Enabled - * LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM - * is enabled and LBME is disabled. - * LOM=1 and LBME=0 disables all transmissions. - * LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables - * the transmission of own frames. - */ -#define CAN_CMD_STA_CMD_CTRL_LOM_MASK (0x4000U) -#define CAN_CMD_STA_CMD_CTRL_LOM_SHIFT (14U) -#define CAN_CMD_STA_CMD_CTRL_LOM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) -#define CAN_CMD_STA_CMD_CTRL_LOM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) >> CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) - -/* - * STBY (RW) - * - * Transceiver Standby Mode - * 0 - Disabled - * 1 - Enabled - * This register bit is connected to the output signal stby which can be used to control a - * standby mode of a transceiver. - * STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. - * If the host sets STBY to 0 then the host needs to wait for the time required by the - * transceiver to start up before the host requests a new transmission. - */ -#define CAN_CMD_STA_CMD_CTRL_STBY_MASK (0x2000U) -#define CAN_CMD_STA_CMD_CTRL_STBY_SHIFT (13U) -#define CAN_CMD_STA_CMD_CTRL_STBY_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) -#define CAN_CMD_STA_CMD_CTRL_STBY_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) >> CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) - -/* - * TPE (RW) - * - * Transmit Primary Enable - * 1 - Transmission enable for the message in the high-priority PTB - * 0 - No transmission for the PTB - * If TPE is set, the message from the PTB will be transmitted at the next possible transmit - * position. A started transmission from the STB will be completed before, but pending new - * messages are delayed until the PTB message has been transmitted. - * TPE stays set until the message has been transmitted successfully or it is aborted using - * TPA. - * The host controller can set TPE to 1 but can not reset it to 0. This would only be possible - * using TPA and aborting the message. - * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and - * LBME=0) or (TTEN=1 and TTTBM=1). - */ -#define CAN_CMD_STA_CMD_CTRL_TPE_MASK (0x1000U) -#define CAN_CMD_STA_CMD_CTRL_TPE_SHIFT (12U) -#define CAN_CMD_STA_CMD_CTRL_TPE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) -#define CAN_CMD_STA_CMD_CTRL_TPE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) >> CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) - -/* - * TPA (RW) - * - * Transmit Primary Abort - * 1 – Aborts a transmission from PTB which has been requested by TPE=1 but not - * started yet. (The data bytes of the message remains in the PTB.) - * 0 – no abort - * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA - * automatically de-asserts TPE. - * The host controller can set TPA to 1 but can not reset it to 0. - * During the short time while the CAN-CTRL core resets the bit, it cannot be set by the - * host. - * The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). - * TPA should not be set simultaneously with TPE. - */ -#define CAN_CMD_STA_CMD_CTRL_TPA_MASK (0x800U) -#define CAN_CMD_STA_CMD_CTRL_TPA_SHIFT (11U) -#define CAN_CMD_STA_CMD_CTRL_TPA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) -#define CAN_CMD_STA_CMD_CTRL_TPA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) >> CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) - -/* - * TSONE (RW) - * - * Transmit Secondary ONE frame - * 1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message - * and in priority mode this is the one with the highest priority. - * TSONE in priority mode is difficult to handle, because it is not always clear which - * message will be transmitted if new messages are written to the STB meanwhile. - * The controller starts the transmission as soon as the bus becomes vacant and - * no request of the PTB (bit TPE) is pending. - * 0 – No transmission for the STB. - * TSONE stays set until the message has been transmitted successfully or it is aborted - * using TSA. - * The host controller can set TSONE to 1 but can not reset it to 0. This would only be - * possible using TSA and aborting the message. - * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and - * LBME=0) or (TTEN=1 and TTTBM=1). - */ -#define CAN_CMD_STA_CMD_CTRL_TSONE_MASK (0x400U) -#define CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT (10U) -#define CAN_CMD_STA_CMD_CTRL_TSONE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSONE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) - -/* - * TSALL (RW) - * - * Transmit Secondary ALL frames - * 1 – Transmission enable of all messages in the STB. - * The controller starts the transmission as soon as the bus becomes vacant and - * no request of the PTB (bit TPE) is pending. - * 0 – No transmission for the STB. - * TSALL stays set until all messages have been transmitted successfully or they are aborted - * using TSA. - * The host controller can set TSALL to 1 but can not reset it to 0. This would only be - * possible using TSA and aborting the messages. - * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and - * LBME=0) or (TTEN=1 and TTTBM=1). - * If during a transmission the STB is loaded with a new frame then the new frame will be - * transmitted too. In other words: a transmission initiated by TSALL is finished when the - * STB becomes empty. - */ -#define CAN_CMD_STA_CMD_CTRL_TSALL_MASK (0x200U) -#define CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT (9U) -#define CAN_CMD_STA_CMD_CTRL_TSALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) >> CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) - -/* - * TSA (RW) - * - * Transmit Secondary Abort - * 1 – Aborts a transmission from STB which has been requested but not started yet. - * For a TSONE transmission, only one frame is aborted while for a TSALL - * Transmission, all frames are aborted. - * One or all message slots will be released which updates TSSTAT. - * All aborted messages are lost because they are not accessible any more. - * If in priority mode a TSONE transmission is aborted, then it is not clear which - * frame will be aborted if new frames are written to the STB meanwhile. - * 0 – no abort - * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. - * The host controller can set TSA to 1 but can not reset it to 0. - * The bit will be reset to the hardware reset value if RESET=1. - * TSA should not be set simultaneously with TSONE or TSALL. - */ -#define CAN_CMD_STA_CMD_CTRL_TSA_MASK (0x100U) -#define CAN_CMD_STA_CMD_CTRL_TSA_SHIFT (8U) -#define CAN_CMD_STA_CMD_CTRL_TSA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) >> CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) - -/* - * RESET (RW) - * - * RESET request bit - * 1 - The host controller performs a local reset of CAN-CTRL. - * 0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. - * Bit RESET forces several components to a reset state. - * RESET is automatically set if the node enters “bus off” state. - * Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. - * This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. - * The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - */ -#define CAN_CMD_STA_CMD_CTRL_RESET_MASK (0x80U) -#define CAN_CMD_STA_CMD_CTRL_RESET_SHIFT (7U) -#define CAN_CMD_STA_CMD_CTRL_RESET_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) -#define CAN_CMD_STA_CMD_CTRL_RESET_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) >> CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) - -/* - * LBME (RW) - * - * Loop Back Mode, External - * 0 - Disabled - * 1 - EnabledLBME should not be enabled while a transmission is active - */ -#define CAN_CMD_STA_CMD_CTRL_LBME_MASK (0x40U) -#define CAN_CMD_STA_CMD_CTRL_LBME_SHIFT (6U) -#define CAN_CMD_STA_CMD_CTRL_LBME_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) -#define CAN_CMD_STA_CMD_CTRL_LBME_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) >> CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) - -/* - * LBMI (RW) - * - * Loop Back Mode, Internal - * 0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - */ -#define CAN_CMD_STA_CMD_CTRL_LBMI_MASK (0x20U) -#define CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT (5U) -#define CAN_CMD_STA_CMD_CTRL_LBMI_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) -#define CAN_CMD_STA_CMD_CTRL_LBMI_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) >> CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) - -/* - * TPSS (RW) - * - * Transmission Primary Single Shot mode for PTB - * 0 - Disabled - * 1 - Enabled - */ -#define CAN_CMD_STA_CMD_CTRL_TPSS_MASK (0x10U) -#define CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT (4U) -#define CAN_CMD_STA_CMD_CTRL_TPSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) -#define CAN_CMD_STA_CMD_CTRL_TPSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) - -/* - * TSSS (RW) - * - * Transmission Secondary Single Shot mode for STB - * 0 - Disabled - * 1 - Enabled - */ -#define CAN_CMD_STA_CMD_CTRL_TSSS_MASK (0x8U) -#define CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT (3U) -#define CAN_CMD_STA_CMD_CTRL_TSSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) - -/* - * RACTIVE (RO) - * - * Reception ACTIVE (Receive Status bit) - * 1 - The controller is currently receiving a frame. - * 0 - No receive activity. - */ -#define CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK (0x4U) -#define CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT (2U) -#define CAN_CMD_STA_CMD_CTRL_RACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT) - -/* - * TACTIVE (RO) - * - * Transmission ACTIVE (Transmit Status bit) - * 1 - The controller is currently transmitting a frame. - * 0 - No transmit activity. - */ -#define CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK (0x2U) -#define CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT (1U) -#define CAN_CMD_STA_CMD_CTRL_TACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT) - -/* - * BUSOFF (RW) - * - * Bus Off (Bus Status bit) - * 1 - The controller status is “bus off”. - * 0 - The controller status is “bus on”. - * Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. - * See Chapter 3.9.10.6 for details. - */ -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK (0x1U) -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT (0U) -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) >> CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) - -/* Bitfield definition for register: RTIE */ -/* - * RIE (RW) - * - * Receive Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_RIE_MASK (0x80U) -#define CAN_RTIE_RIE_SHIFT (7U) -#define CAN_RTIE_RIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RIE_SHIFT) & CAN_RTIE_RIE_MASK) -#define CAN_RTIE_RIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RIE_MASK) >> CAN_RTIE_RIE_SHIFT) - -/* - * ROIE (RW) - * - * RB Overrun Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_ROIE_MASK (0x40U) -#define CAN_RTIE_ROIE_SHIFT (6U) -#define CAN_RTIE_ROIE_SET(x) (((uint8_t)(x) << CAN_RTIE_ROIE_SHIFT) & CAN_RTIE_ROIE_MASK) -#define CAN_RTIE_ROIE_GET(x) (((uint8_t)(x) & CAN_RTIE_ROIE_MASK) >> CAN_RTIE_ROIE_SHIFT) - -/* - * RFIE (RW) - * - * RB Full Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_RFIE_MASK (0x20U) -#define CAN_RTIE_RFIE_SHIFT (5U) -#define CAN_RTIE_RFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RFIE_SHIFT) & CAN_RTIE_RFIE_MASK) -#define CAN_RTIE_RFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RFIE_MASK) >> CAN_RTIE_RFIE_SHIFT) - -/* - * RAFIE (RW) - * - * RB Almost Full Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_RAFIE_MASK (0x10U) -#define CAN_RTIE_RAFIE_SHIFT (4U) -#define CAN_RTIE_RAFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RAFIE_SHIFT) & CAN_RTIE_RAFIE_MASK) -#define CAN_RTIE_RAFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RAFIE_MASK) >> CAN_RTIE_RAFIE_SHIFT) - -/* - * TPIE (RW) - * - * Transmission Primary Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_TPIE_MASK (0x8U) -#define CAN_RTIE_TPIE_SHIFT (3U) -#define CAN_RTIE_TPIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TPIE_SHIFT) & CAN_RTIE_TPIE_MASK) -#define CAN_RTIE_TPIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TPIE_MASK) >> CAN_RTIE_TPIE_SHIFT) - -/* - * TSIE (RW) - * - * Transmission Secondary Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_TSIE_MASK (0x4U) -#define CAN_RTIE_TSIE_SHIFT (2U) -#define CAN_RTIE_TSIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TSIE_SHIFT) & CAN_RTIE_TSIE_MASK) -#define CAN_RTIE_TSIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TSIE_MASK) >> CAN_RTIE_TSIE_SHIFT) - -/* - * EIE (RW) - * - * Error Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_EIE_MASK (0x2U) -#define CAN_RTIE_EIE_SHIFT (1U) -#define CAN_RTIE_EIE_SET(x) (((uint8_t)(x) << CAN_RTIE_EIE_SHIFT) & CAN_RTIE_EIE_MASK) -#define CAN_RTIE_EIE_GET(x) (((uint8_t)(x) & CAN_RTIE_EIE_MASK) >> CAN_RTIE_EIE_SHIFT) - -/* - * TSFF (RO) - * - * If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag - * 1 - The STB is filled with the maximal number of messages. - * 0 - The STB is not filled with the maximal number of messages. - * If the STB is disabled using STB_DISABLE, then TSFF=0. - * If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag - * 1 - The buffer slot selected by TBPTR is filled. - * 0 - The buffer slot selected by TBPTR is empty. - */ -#define CAN_RTIE_TSFF_MASK (0x1U) -#define CAN_RTIE_TSFF_SHIFT (0U) -#define CAN_RTIE_TSFF_GET(x) (((uint8_t)(x) & CAN_RTIE_TSFF_MASK) >> CAN_RTIE_TSFF_SHIFT) - -/* Bitfield definition for register: RTIF */ -/* - * RIF (W1C) - * - * Receive Interrupt Flag - * 1 - Data or a remote frame has been received and is available in the receive buffer. - * 0 - No frame has been received. - */ -#define CAN_RTIF_RIF_MASK (0x80U) -#define CAN_RTIF_RIF_SHIFT (7U) -#define CAN_RTIF_RIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RIF_SHIFT) & CAN_RTIF_RIF_MASK) -#define CAN_RTIF_RIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RIF_MASK) >> CAN_RTIF_RIF_SHIFT) - -/* - * ROIF (W1C) - * - * RB Overrun Interrupt Flag - * 1 - At least one received message has been overwritten in the RB. - * 0 - No RB overwritten. - * In case of an overrun both ROIF and RFIF will be set. - */ -#define CAN_RTIF_ROIF_MASK (0x40U) -#define CAN_RTIF_ROIF_SHIFT (6U) -#define CAN_RTIF_ROIF_SET(x) (((uint8_t)(x) << CAN_RTIF_ROIF_SHIFT) & CAN_RTIF_ROIF_MASK) -#define CAN_RTIF_ROIF_GET(x) (((uint8_t)(x) & CAN_RTIF_ROIF_MASK) >> CAN_RTIF_ROIF_SHIFT) - -/* - * RFIF (W1C) - * - * RB Full Interrupt Flag - * 1 - All RBs are full. If no RB will be released until the next valid message is received, - * the oldest message will be lost. - * 0 - The RB FIFO is not full. - */ -#define CAN_RTIF_RFIF_MASK (0x20U) -#define CAN_RTIF_RFIF_SHIFT (5U) -#define CAN_RTIF_RFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RFIF_SHIFT) & CAN_RTIF_RFIF_MASK) -#define CAN_RTIF_RFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RFIF_MASK) >> CAN_RTIF_RFIF_SHIFT) - -/* - * RAFIF (W1C) - * - * RB Almost Full Interrupt Flag - * 1 - number of filled RB slots >= AFWL_i - * 0 - number of filled RB slots < AFWL_i - */ -#define CAN_RTIF_RAFIF_MASK (0x10U) -#define CAN_RTIF_RAFIF_SHIFT (4U) -#define CAN_RTIF_RAFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RAFIF_SHIFT) & CAN_RTIF_RAFIF_MASK) -#define CAN_RTIF_RAFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RAFIF_MASK) >> CAN_RTIF_RAFIF_SHIFT) - -/* - * TPIF (W1C) - * - * Transmission Primary Interrupt Flag - * 1 - The requested transmission of the PTB has been successfully completed. - * 0 - No transmission of the PTB has been completed. - * In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - */ -#define CAN_RTIF_TPIF_MASK (0x8U) -#define CAN_RTIF_TPIF_SHIFT (3U) -#define CAN_RTIF_TPIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TPIF_SHIFT) & CAN_RTIF_TPIF_MASK) -#define CAN_RTIF_TPIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TPIF_MASK) >> CAN_RTIF_TPIF_SHIFT) - -/* - * TSIF (W1C) - * - * Transmission Secondary Interrupt Flag - * 1 - The requested transmission of the STB has been successfully completed. - * 0 - No transmission of the STB has been completed successfully. - * In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of - * the message. - */ -#define CAN_RTIF_TSIF_MASK (0x4U) -#define CAN_RTIF_TSIF_SHIFT (2U) -#define CAN_RTIF_TSIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TSIF_SHIFT) & CAN_RTIF_TSIF_MASK) -#define CAN_RTIF_TSIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TSIF_MASK) >> CAN_RTIF_TSIF_SHIFT) - -/* - * EIF (W1C) - * - * Error Interrupt Flag - * 1 - The border of the error warning limit has been crossed in either direction, - * or the BUSOFF bit has been changed in either direction. - * 0 - There has been no change. - */ -#define CAN_RTIF_EIF_MASK (0x2U) -#define CAN_RTIF_EIF_SHIFT (1U) -#define CAN_RTIF_EIF_SET(x) (((uint8_t)(x) << CAN_RTIF_EIF_SHIFT) & CAN_RTIF_EIF_MASK) -#define CAN_RTIF_EIF_GET(x) (((uint8_t)(x) & CAN_RTIF_EIF_MASK) >> CAN_RTIF_EIF_SHIFT) - -/* - * AIF (W1C) - * - * Abort Interrupt Flag - * 1 - After setting TPA or TSA the appropriated message(s) have been aborted. - * It is recommended to not set both TPA and TSA simultaneously because both - * source AIF. - * 0 - No abort has been executed. - * The AIF does not have an associated enable register. - */ -#define CAN_RTIF_AIF_MASK (0x1U) -#define CAN_RTIF_AIF_SHIFT (0U) -#define CAN_RTIF_AIF_SET(x) (((uint8_t)(x) << CAN_RTIF_AIF_SHIFT) & CAN_RTIF_AIF_MASK) -#define CAN_RTIF_AIF_GET(x) (((uint8_t)(x) & CAN_RTIF_AIF_MASK) >> CAN_RTIF_AIF_SHIFT) - -/* Bitfield definition for register: ERRINT */ -/* - * EWARN (RO) - * - * Error WARNing limit reached - * 1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - */ -#define CAN_ERRINT_EWARN_MASK (0x80U) -#define CAN_ERRINT_EWARN_SHIFT (7U) -#define CAN_ERRINT_EWARN_GET(x) (((uint8_t)(x) & CAN_ERRINT_EWARN_MASK) >> CAN_ERRINT_EWARN_SHIFT) - -/* - * EPASS (RO) - * - * Error Passive mode active - * 0 - not active (node is error active) - * 1 - active (node is error passive) - */ -#define CAN_ERRINT_EPASS_MASK (0x40U) -#define CAN_ERRINT_EPASS_SHIFT (6U) -#define CAN_ERRINT_EPASS_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPASS_MASK) >> CAN_ERRINT_EPASS_SHIFT) - -/* - * EPIE (RW) - * - * Error Passive Interrupt Enable - */ -#define CAN_ERRINT_EPIE_MASK (0x20U) -#define CAN_ERRINT_EPIE_SHIFT (5U) -#define CAN_ERRINT_EPIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIE_SHIFT) & CAN_ERRINT_EPIE_MASK) -#define CAN_ERRINT_EPIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIE_MASK) >> CAN_ERRINT_EPIE_SHIFT) - -/* - * EPIF (W1C) - * - * Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error - * active to error passive or vice versa and if this interrupt is enabled. - */ -#define CAN_ERRINT_EPIF_MASK (0x10U) -#define CAN_ERRINT_EPIF_SHIFT (4U) -#define CAN_ERRINT_EPIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIF_SHIFT) & CAN_ERRINT_EPIF_MASK) -#define CAN_ERRINT_EPIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIF_MASK) >> CAN_ERRINT_EPIF_SHIFT) - -/* - * ALIE (RW) - * - * Arbitration Lost Interrupt Enable - */ -#define CAN_ERRINT_ALIE_MASK (0x8U) -#define CAN_ERRINT_ALIE_SHIFT (3U) -#define CAN_ERRINT_ALIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIE_SHIFT) & CAN_ERRINT_ALIE_MASK) -#define CAN_ERRINT_ALIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIE_MASK) >> CAN_ERRINT_ALIE_SHIFT) - -/* - * ALIF (W1C) - * - * Arbitration Lost Interrupt Flag - */ -#define CAN_ERRINT_ALIF_MASK (0x4U) -#define CAN_ERRINT_ALIF_SHIFT (2U) -#define CAN_ERRINT_ALIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIF_SHIFT) & CAN_ERRINT_ALIF_MASK) -#define CAN_ERRINT_ALIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIF_MASK) >> CAN_ERRINT_ALIF_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable - */ -#define CAN_ERRINT_BEIE_MASK (0x2U) -#define CAN_ERRINT_BEIE_SHIFT (1U) -#define CAN_ERRINT_BEIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIE_SHIFT) & CAN_ERRINT_BEIE_MASK) -#define CAN_ERRINT_BEIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIE_MASK) >> CAN_ERRINT_BEIE_SHIFT) - -/* - * BEIF (W1C) - * - * Bus Error Interrupt Flag - */ -#define CAN_ERRINT_BEIF_MASK (0x1U) -#define CAN_ERRINT_BEIF_SHIFT (0U) -#define CAN_ERRINT_BEIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIF_SHIFT) & CAN_ERRINT_BEIF_MASK) -#define CAN_ERRINT_BEIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIF_MASK) >> CAN_ERRINT_BEIF_SHIFT) - -/* Bitfield definition for register: LIMIT */ -/* - * AFWL (RW) - * - * receive buffer Almost Full Warning Limit - * AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. - * AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . - * AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) - * AFWL_i > nRB is meaningless and automatically treated as nRB. - * AFWL_i = nRB is a valid value, but note that RFIF also exists. - */ -#define CAN_LIMIT_AFWL_MASK (0xF0U) -#define CAN_LIMIT_AFWL_SHIFT (4U) -#define CAN_LIMIT_AFWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_AFWL_SHIFT) & CAN_LIMIT_AFWL_MASK) -#define CAN_LIMIT_AFWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_AFWL_MASK) >> CAN_LIMIT_AFWL_SHIFT) - -/* - * EWL (RW) - * - * Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. - * The value of EWL controls EIF. - */ -#define CAN_LIMIT_EWL_MASK (0xFU) -#define CAN_LIMIT_EWL_SHIFT (0U) -#define CAN_LIMIT_EWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_EWL_SHIFT) & CAN_LIMIT_EWL_MASK) -#define CAN_LIMIT_EWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_EWL_MASK) >> CAN_LIMIT_EWL_SHIFT) - -/* Bitfield definition for register: S_PRESC */ -/* - * S_PRESC (RW) - * - * Prescaler (slow speed) - * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - */ -#define CAN_S_PRESC_S_PRESC_MASK (0xFF000000UL) -#define CAN_S_PRESC_S_PRESC_SHIFT (24U) -#define CAN_S_PRESC_S_PRESC_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_PRESC_SHIFT) & CAN_S_PRESC_S_PRESC_MASK) -#define CAN_S_PRESC_S_PRESC_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_PRESC_MASK) >> CAN_S_PRESC_S_PRESC_SHIFT) - -/* - * S_SJW (RW) - * - * Synchronization Jump Width (slow speed) - * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - */ -#define CAN_S_PRESC_S_SJW_MASK (0x7F0000UL) -#define CAN_S_PRESC_S_SJW_SHIFT (16U) -#define CAN_S_PRESC_S_SJW_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SJW_SHIFT) & CAN_S_PRESC_S_SJW_MASK) -#define CAN_S_PRESC_S_SJW_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SJW_MASK) >> CAN_S_PRESC_S_SJW_SHIFT) - -/* - * S_SEG_2 (RW) - * - * Bit Timing Segment 2 (slow speed) - * Time after the sample point. - */ -#define CAN_S_PRESC_S_SEG_2_MASK (0x7F00U) -#define CAN_S_PRESC_S_SEG_2_SHIFT (8U) -#define CAN_S_PRESC_S_SEG_2_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_2_SHIFT) & CAN_S_PRESC_S_SEG_2_MASK) -#define CAN_S_PRESC_S_SEG_2_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_2_MASK) >> CAN_S_PRESC_S_SEG_2_SHIFT) - -/* - * S_SEG_1 (RW) - * - * Bit Timing Segment 1 (slow speed) - * The sample point will be set to after start of bit time. - */ -#define CAN_S_PRESC_S_SEG_1_MASK (0xFFU) -#define CAN_S_PRESC_S_SEG_1_SHIFT (0U) -#define CAN_S_PRESC_S_SEG_1_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_1_SHIFT) & CAN_S_PRESC_S_SEG_1_MASK) -#define CAN_S_PRESC_S_SEG_1_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_1_MASK) >> CAN_S_PRESC_S_SEG_1_SHIFT) - -/* Bitfield definition for register: F_PRESC */ -/* - * F_PRESC (RW) - * - * Prescaler (fast speed) - * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - */ -#define CAN_F_PRESC_F_PRESC_MASK (0xFF000000UL) -#define CAN_F_PRESC_F_PRESC_SHIFT (24U) -#define CAN_F_PRESC_F_PRESC_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_PRESC_SHIFT) & CAN_F_PRESC_F_PRESC_MASK) -#define CAN_F_PRESC_F_PRESC_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_PRESC_MASK) >> CAN_F_PRESC_F_PRESC_SHIFT) - -/* - * F_SJW (RW) - * - * Synchronization Jump Width (fast speed) - * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - */ -#define CAN_F_PRESC_F_SJW_MASK (0xF0000UL) -#define CAN_F_PRESC_F_SJW_SHIFT (16U) -#define CAN_F_PRESC_F_SJW_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SJW_SHIFT) & CAN_F_PRESC_F_SJW_MASK) -#define CAN_F_PRESC_F_SJW_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SJW_MASK) >> CAN_F_PRESC_F_SJW_SHIFT) - -/* - * F_SEG_2 (RW) - * - * Bit Timing Segment 2 (fast speed) - * Time after the sample point - */ -#define CAN_F_PRESC_F_SEG_2_MASK (0xF00U) -#define CAN_F_PRESC_F_SEG_2_SHIFT (8U) -#define CAN_F_PRESC_F_SEG_2_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_2_SHIFT) & CAN_F_PRESC_F_SEG_2_MASK) -#define CAN_F_PRESC_F_SEG_2_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_2_MASK) >> CAN_F_PRESC_F_SEG_2_SHIFT) - -/* - * F_SEG_1 (RW) - * - * Bit Timing Segment 1 (fast speed) - * The sample point will be set to after start of bit time. - */ -#define CAN_F_PRESC_F_SEG_1_MASK (0xFU) -#define CAN_F_PRESC_F_SEG_1_SHIFT (0U) -#define CAN_F_PRESC_F_SEG_1_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_1_SHIFT) & CAN_F_PRESC_F_SEG_1_MASK) -#define CAN_F_PRESC_F_SEG_1_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_1_MASK) >> CAN_F_PRESC_F_SEG_1_SHIFT) - -/* Bitfield definition for register: EALCAP */ -/* - * KOER (RO) - * - * Kind Of ERror (Error code) - * 000 - no error - * 001 - BIT ERROR - * 010 - FORM ERROR - * 011 - STUFF ERROR - * 100 - ACKNOWLEDGEMENT ERROR - * 101 - CRC ERROR - * 110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) - * 111 - not used - * KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - */ -#define CAN_EALCAP_KOER_MASK (0xE0U) -#define CAN_EALCAP_KOER_SHIFT (5U) -#define CAN_EALCAP_KOER_GET(x) (((uint8_t)(x) & CAN_EALCAP_KOER_MASK) >> CAN_EALCAP_KOER_SHIFT) - -/* - * ALC (RO) - * - * Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - */ -#define CAN_EALCAP_ALC_MASK (0x1FU) -#define CAN_EALCAP_ALC_SHIFT (0U) -#define CAN_EALCAP_ALC_GET(x) (((uint8_t)(x) & CAN_EALCAP_ALC_MASK) >> CAN_EALCAP_ALC_SHIFT) - -/* Bitfield definition for register: TDC */ -/* - * TDCEN (RW) - * - * Transmitter Delay Compensation ENable - * TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - */ -#define CAN_TDC_TDCEN_MASK (0x80U) -#define CAN_TDC_TDCEN_SHIFT (7U) -#define CAN_TDC_TDCEN_SET(x) (((uint8_t)(x) << CAN_TDC_TDCEN_SHIFT) & CAN_TDC_TDCEN_MASK) -#define CAN_TDC_TDCEN_GET(x) (((uint8_t)(x) & CAN_TDC_TDCEN_MASK) >> CAN_TDC_TDCEN_SHIFT) - -/* - * SSPOFF (RW) - * - * Secondary Sample Point OFFset - * The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. - * SSPOFF is given as a number of TQ. - */ -#define CAN_TDC_SSPOFF_MASK (0x7FU) -#define CAN_TDC_SSPOFF_SHIFT (0U) -#define CAN_TDC_SSPOFF_SET(x) (((uint8_t)(x) << CAN_TDC_SSPOFF_SHIFT) & CAN_TDC_SSPOFF_MASK) -#define CAN_TDC_SSPOFF_GET(x) (((uint8_t)(x) & CAN_TDC_SSPOFF_MASK) >> CAN_TDC_SSPOFF_SHIFT) - -/* Bitfield definition for register: RECNT */ -/* - * RECNT (RO) - * - * Receive Error CouNT (number of errors during reception) - * RECNT is incremented and decremented as defined in the CAN specification. - * RECNT does not overflow. - * If TXB=1, then the error counters are frozen. - */ -#define CAN_RECNT_RECNT_MASK (0xFFU) -#define CAN_RECNT_RECNT_SHIFT (0U) -#define CAN_RECNT_RECNT_GET(x) (((uint8_t)(x) & CAN_RECNT_RECNT_MASK) >> CAN_RECNT_RECNT_SHIFT) - -/* Bitfield definition for register: TECNT */ -/* - * TECNT (RO) - * - * Transmit Error CouNT (number of errors during transmission) - * TECNT is incremented and decremented as defined in the CAN specification. - * In case of the “bus off state” TECNT may overflow. - * If TXB=1, then the error counters are frozen. - */ -#define CAN_TECNT_TECNT_MASK (0xFFU) -#define CAN_TECNT_TECNT_SHIFT (0U) -#define CAN_TECNT_TECNT_GET(x) (((uint8_t)(x) & CAN_TECNT_TECNT_MASK) >> CAN_TECNT_TECNT_SHIFT) - -/* Bitfield definition for register: ACFCTRL */ -/* - * SELMASK (RW) - * - * SELect acceptance MASK - * 0 - Registers ACF_x point to acceptance code - * 1 - Registers ACF_x point to acceptance mask. - * ACFADR selects one specific acceptance filter. - */ -#define CAN_ACFCTRL_SELMASK_MASK (0x20U) -#define CAN_ACFCTRL_SELMASK_SHIFT (5U) -#define CAN_ACFCTRL_SELMASK_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_SELMASK_SHIFT) & CAN_ACFCTRL_SELMASK_MASK) -#define CAN_ACFCTRL_SELMASK_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_SELMASK_MASK) >> CAN_ACFCTRL_SELMASK_SHIFT) - -/* - * ACFADR (RW) - * - * acceptance filter address - * ACFADR points to a specific acceptance filter. - * The selected filter is accessible using theregisters ACF_x. - * Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. - * A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. - * ACF_NUMBER = 16. - */ -#define CAN_ACFCTRL_ACFADR_MASK (0xFU) -#define CAN_ACFCTRL_ACFADR_SHIFT (0U) -#define CAN_ACFCTRL_ACFADR_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_ACFADR_SHIFT) & CAN_ACFCTRL_ACFADR_MASK) -#define CAN_ACFCTRL_ACFADR_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_ACFADR_MASK) >> CAN_ACFCTRL_ACFADR_SHIFT) - -/* Bitfield definition for register: TIMECFG */ -/* - * TIMEPOS (RW) - * - * TIME-stamping POSition - * 0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - */ -#define CAN_TIMECFG_TIMEPOS_MASK (0x2U) -#define CAN_TIMECFG_TIMEPOS_SHIFT (1U) -#define CAN_TIMECFG_TIMEPOS_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEPOS_SHIFT) & CAN_TIMECFG_TIMEPOS_MASK) -#define CAN_TIMECFG_TIMEPOS_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEPOS_MASK) >> CAN_TIMECFG_TIMEPOS_SHIFT) - -/* - * TIMEEN (RW) - * - * TIME-stamping ENable - * 0 – disabled - * 1 – enabled - */ -#define CAN_TIMECFG_TIMEEN_MASK (0x1U) -#define CAN_TIMECFG_TIMEEN_SHIFT (0U) -#define CAN_TIMECFG_TIMEEN_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEEN_SHIFT) & CAN_TIMECFG_TIMEEN_MASK) -#define CAN_TIMECFG_TIMEEN_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEEN_MASK) >> CAN_TIMECFG_TIMEEN_SHIFT) - -/* Bitfield definition for register: ACF_EN */ -/* - * ACF_EN (RW) - * - * Acceptance filter Enable - * 1 - acceptance filter enabled - * 0 - acceptance filter disable - * Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. - * Disabled filters reject a message. Only enabled filters can accept a message if the - * appropriate AMASK / ACODE configuration matches. - */ -#define CAN_ACF_EN_ACF_EN_MASK (0xFFFFU) -#define CAN_ACF_EN_ACF_EN_SHIFT (0U) -#define CAN_ACF_EN_ACF_EN_SET(x) (((uint16_t)(x) << CAN_ACF_EN_ACF_EN_SHIFT) & CAN_ACF_EN_ACF_EN_MASK) -#define CAN_ACF_EN_ACF_EN_GET(x) (((uint16_t)(x) & CAN_ACF_EN_ACF_EN_MASK) >> CAN_ACF_EN_ACF_EN_SHIFT) - -/* Bitfield definition for register: ACF */ -/* - * AIDEE (RW) - * - * Acceptance mask IDE bit check enable - * 1 - acceptance filter accepts either standard or extended as defined by AIDE - * 0 - acceptance filter accepts both standard or extended frames - * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - */ -#define CAN_ACF_AIDEE_MASK (0x40000000UL) -#define CAN_ACF_AIDEE_SHIFT (30U) -#define CAN_ACF_AIDEE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDEE_SHIFT) & CAN_ACF_AIDEE_MASK) -#define CAN_ACF_AIDEE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDEE_MASK) >> CAN_ACF_AIDEE_SHIFT) - -/* - * AIDE (RW) - * - * Acceptance mask IDE bit value - * If AIDEE=1 then: - * 1 - acceptance filter accepts only extended frames - * 0 - acceptance filter accepts only standard frames - * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - */ -#define CAN_ACF_AIDE_MASK (0x20000000UL) -#define CAN_ACF_AIDE_SHIFT (29U) -#define CAN_ACF_AIDE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDE_SHIFT) & CAN_ACF_AIDE_MASK) -#define CAN_ACF_AIDE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDE_MASK) >> CAN_ACF_AIDE_SHIFT) - -/* - * CODE_MASK (RW) - * - * Acceptance CODE - * 1 - ACC bit value to compare with ID bit of the received message - * 0 - ACC bit value to compare with ID bit of the received message - * ACODE_x(10:0) will be used for extended frames. - * ACODE_x(28:0) will be used for extended frames. - * Only filter 0 is affected by the power-on reset. - * Acceptance MASK(if SELMASK ==1 ) - * 1 - acceptance check for these bits of receive identifier disabled - * 0 - acceptance check for these bits of receive identifier enable - * AMASK_x(10:0) will be used for extended frames. - * AMASK_x(28:0) will be used for extended frames. - * Disabled bits result in accepting the message. Therefore the default configuration after - * reset for filter 0 accepts all messages. - * Only filter 0 is affected by the power-on reset. - */ -#define CAN_ACF_CODE_MASK_MASK (0x1FFFFFFFUL) -#define CAN_ACF_CODE_MASK_SHIFT (0U) -#define CAN_ACF_CODE_MASK_SET(x) (((uint32_t)(x) << CAN_ACF_CODE_MASK_SHIFT) & CAN_ACF_CODE_MASK_MASK) -#define CAN_ACF_CODE_MASK_GET(x) (((uint32_t)(x) & CAN_ACF_CODE_MASK_MASK) >> CAN_ACF_CODE_MASK_SHIFT) - -/* Bitfield definition for register: VER */ -/* - * VERSION (RW) - * - * Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and - * VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - */ -#define CAN_VER_VERSION_MASK (0xFFFFU) -#define CAN_VER_VERSION_SHIFT (0U) -#define CAN_VER_VERSION_SET(x) (((uint16_t)(x) << CAN_VER_VERSION_SHIFT) & CAN_VER_VERSION_MASK) -#define CAN_VER_VERSION_GET(x) (((uint16_t)(x) & CAN_VER_VERSION_MASK) >> CAN_VER_VERSION_SHIFT) - -/* Bitfield definition for register: TBSLOT */ -/* - * TBE (RW) - * - * set TB slot to “Empty” - * 1 - slot selected by TBPTR shall be marked as “empty” - * 0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. - * If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - * transmissionis not active any more. - * If both TBF and TBE are set, then TBE wins - */ -#define CAN_TBSLOT_TBE_MASK (0x80U) -#define CAN_TBSLOT_TBE_SHIFT (7U) -#define CAN_TBSLOT_TBE_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBE_SHIFT) & CAN_TBSLOT_TBE_MASK) -#define CAN_TBSLOT_TBE_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBE_MASK) >> CAN_TBSLOT_TBE_SHIFT) - -/* - * TBF (RW) - * - * set TB slot to “Filled” - * 1 - slot selected by TBPTR shall be marked as “filled” - * 0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. - * If both TBF and TBE are set, then TBE wins. - */ -#define CAN_TBSLOT_TBF_MASK (0x40U) -#define CAN_TBSLOT_TBF_SHIFT (6U) -#define CAN_TBSLOT_TBF_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBF_SHIFT) & CAN_TBSLOT_TBF_MASK) -#define CAN_TBSLOT_TBF_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBF_MASK) >> CAN_TBSLOT_TBF_SHIFT) - -/* - * TBPTR (RW) - * - * Pointer to a TB message slot. - * 0x00 - Pointer to the PTB - * others - Pointer to a slot in the STB - * The message slot pointed to by TBPTR is readable / writable using the TBUF registers. - * Write access is only possible if TSFF=0. - * Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. - * TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. - * TBPTR can only point to buffer slots, that exist in the hardware. - * Unusable bits ofTBPTR are fixed to 0. - * TBPTR is limited to the PTB and 63 STB slots. - * More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - */ -#define CAN_TBSLOT_TBPTR_MASK (0x3FU) -#define CAN_TBSLOT_TBPTR_SHIFT (0U) -#define CAN_TBSLOT_TBPTR_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBPTR_SHIFT) & CAN_TBSLOT_TBPTR_MASK) -#define CAN_TBSLOT_TBPTR_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBPTR_MASK) >> CAN_TBSLOT_TBPTR_SHIFT) - -/* Bitfield definition for register: TTCFG */ -/* - * WTIE (RW) - * - * Watch Trigger Interrupt Enable - */ -#define CAN_TTCFG_WTIE_MASK (0x80U) -#define CAN_TTCFG_WTIE_SHIFT (7U) -#define CAN_TTCFG_WTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIE_SHIFT) & CAN_TTCFG_WTIE_MASK) -#define CAN_TTCFG_WTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIE_MASK) >> CAN_TTCFG_WTIE_SHIFT) - -/* - * WTIF (RW) - * - * Watch Trigger Interrupt Flag - * WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - */ -#define CAN_TTCFG_WTIF_MASK (0x40U) -#define CAN_TTCFG_WTIF_SHIFT (6U) -#define CAN_TTCFG_WTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIF_SHIFT) & CAN_TTCFG_WTIF_MASK) -#define CAN_TTCFG_WTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIF_MASK) >> CAN_TTCFG_WTIF_SHIFT) - -/* - * TEIF (RW) - * - * Trigger Error Interrupt Flag - * The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - */ -#define CAN_TTCFG_TEIF_MASK (0x20U) -#define CAN_TTCFG_TEIF_SHIFT (5U) -#define CAN_TTCFG_TEIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TEIF_SHIFT) & CAN_TTCFG_TEIF_MASK) -#define CAN_TTCFG_TEIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TEIF_MASK) >> CAN_TTCFG_TEIF_SHIFT) - -/* - * TTIE (RW) - * - * Time Trigger Interrupt Enable - * If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - */ -#define CAN_TTCFG_TTIE_MASK (0x10U) -#define CAN_TTCFG_TTIE_SHIFT (4U) -#define CAN_TTCFG_TTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIE_SHIFT) & CAN_TTCFG_TTIE_MASK) -#define CAN_TTCFG_TTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIE_MASK) >> CAN_TTCFG_TTIE_SHIFT) - -/* - * TTIF (RW) - * - * Time Trigger Interrupt Flag - * TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. - * Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. - * If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - */ -#define CAN_TTCFG_TTIF_MASK (0x8U) -#define CAN_TTCFG_TTIF_SHIFT (3U) -#define CAN_TTCFG_TTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIF_SHIFT) & CAN_TTCFG_TTIF_MASK) -#define CAN_TTCFG_TTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIF_MASK) >> CAN_TTCFG_TTIF_SHIFT) - -/* - * T_PRESC (RW) - * - * TTCAN Timer PRESCaler - * 00b - 1 - * 01b - 2 - * 10b - 4 - * 11b - 8 - * The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. - * T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - */ -#define CAN_TTCFG_T_PRESC_MASK (0x6U) -#define CAN_TTCFG_T_PRESC_SHIFT (1U) -#define CAN_TTCFG_T_PRESC_SET(x) (((uint8_t)(x) << CAN_TTCFG_T_PRESC_SHIFT) & CAN_TTCFG_T_PRESC_MASK) -#define CAN_TTCFG_T_PRESC_GET(x) (((uint8_t)(x) & CAN_TTCFG_T_PRESC_MASK) >> CAN_TTCFG_T_PRESC_SHIFT) - -/* - * TTEN (RW) - * - * Time Trigger Enable - * 1 - TTCAN enabled, timer is running0 - disabled - */ -#define CAN_TTCFG_TTEN_MASK (0x1U) -#define CAN_TTCFG_TTEN_SHIFT (0U) -#define CAN_TTCFG_TTEN_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTEN_SHIFT) & CAN_TTCFG_TTEN_MASK) -#define CAN_TTCFG_TTEN_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTEN_MASK) >> CAN_TTCFG_TTEN_SHIFT) - -/* Bitfield definition for register: REF_MSG */ -/* - * REF_IDE (RW) - * - * REFerence message IDE bit. - */ -#define CAN_REF_MSG_REF_IDE_MASK (0x80000000UL) -#define CAN_REF_MSG_REF_IDE_SHIFT (31U) -#define CAN_REF_MSG_REF_IDE_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_IDE_SHIFT) & CAN_REF_MSG_REF_IDE_MASK) -#define CAN_REF_MSG_REF_IDE_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_IDE_MASK) >> CAN_REF_MSG_REF_IDE_SHIFT) - -/* - * REF_MSG (RW) - * - * REFerence message IDentifier. - * If REF_IDE is - * 1 - REF_ID(28:0) is valid (extended ID) - * 0 - REF_ID(10:0) is valid (standard ID) - * REF_ID is used in TTCAN mode to detect a reference message. This holds for time - * slaves (reception) as well as for the time master (transmission). If the reference - * message is detected and there are no errors, then the Sync_Mark of this frame will - * become the Ref_Mark. - * REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. - * These bits are used for up to 8 potential time masters. - * CAN-CTRL recognizes the reference message only by ID. The payload is not tested. - * Additional note: A time master will transmit a reference message in the same way as a - * normal frame. REF_ID is intended for detection of a successful transmission of a - * reference message. - */ -#define CAN_REF_MSG_REF_MSG_MASK (0x1FFFFFFFUL) -#define CAN_REF_MSG_REF_MSG_SHIFT (0U) -#define CAN_REF_MSG_REF_MSG_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_MSG_SHIFT) & CAN_REF_MSG_REF_MSG_MASK) -#define CAN_REF_MSG_REF_MSG_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_MSG_MASK) >> CAN_REF_MSG_REF_MSG_SHIFT) - -/* Bitfield definition for register: TRIG_CFG */ -/* - * TEW (RW) - * - * Transmit Enable Window - * For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time - * where the frame is allowed to start. TWE+1 defines the number of ticks. - * TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - */ -#define CAN_TRIG_CFG_TEW_MASK (0xF000U) -#define CAN_TRIG_CFG_TEW_SHIFT (12U) -#define CAN_TRIG_CFG_TEW_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TEW_SHIFT) & CAN_TRIG_CFG_TEW_MASK) -#define CAN_TRIG_CFG_TEW_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TEW_MASK) >> CAN_TRIG_CFG_TEW_SHIFT) - -/* - * TTYPE (RW) - * - * Trigger Type - * 000b - Immediate Trigger for immediate transmission - * 001b - Time Trigger for receive triggers - * 010b - Single Shot Transmit Trigger for exclusive time windows - * 011b - Transmit Start Trigger for merged arbitrating time windows - * 100b - Transmit Stop Trigger for merged arbitrating time windows - * others - no action - * The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the - * transmit triggers. See Chapter 6.4 for more details. - */ -#define CAN_TRIG_CFG_TTYPE_MASK (0x700U) -#define CAN_TRIG_CFG_TTYPE_SHIFT (8U) -#define CAN_TRIG_CFG_TTYPE_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTYPE_SHIFT) & CAN_TRIG_CFG_TTYPE_MASK) -#define CAN_TRIG_CFG_TTYPE_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTYPE_MASK) >> CAN_TRIG_CFG_TTYPE_SHIFT) - -/* - * TTPTR (RW) - * - * Transmit Trigger TB slot Pointer - * If TTPTR is too big and points to a slot that is not available, then TEIF is set and no - * new trigger can be activated after a write access to TT_TRIG_1. - * If TTPTR points to an empty slot, then TEIF will be set at the moment, when the - * trigger time is reached. - */ -#define CAN_TRIG_CFG_TTPTR_MASK (0x3FU) -#define CAN_TRIG_CFG_TTPTR_SHIFT (0U) -#define CAN_TRIG_CFG_TTPTR_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTPTR_SHIFT) & CAN_TRIG_CFG_TTPTR_MASK) -#define CAN_TRIG_CFG_TTPTR_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTPTR_MASK) >> CAN_TRIG_CFG_TTPTR_SHIFT) - -/* Bitfield definition for register: TT_TRIG */ -/* - * TT_TRIG (RW) - * - * Trigger Time - * TT_TRIG(15:0) defines the cycle time for a trigger. - * For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - */ -#define CAN_TT_TRIG_TT_TRIG_MASK (0xFFFFU) -#define CAN_TT_TRIG_TT_TRIG_SHIFT (0U) -#define CAN_TT_TRIG_TT_TRIG_SET(x) (((uint16_t)(x) << CAN_TT_TRIG_TT_TRIG_SHIFT) & CAN_TT_TRIG_TT_TRIG_MASK) -#define CAN_TT_TRIG_TT_TRIG_GET(x) (((uint16_t)(x) & CAN_TT_TRIG_TT_TRIG_MASK) >> CAN_TT_TRIG_TT_TRIG_SHIFT) - -/* Bitfield definition for register: TT_WTRIG */ -/* - * TT_WTRIG (RW) - * - * Watch Trigger Time - * TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - */ -#define CAN_TT_WTRIG_TT_WTRIG_MASK (0xFFFFU) -#define CAN_TT_WTRIG_TT_WTRIG_SHIFT (0U) -#define CAN_TT_WTRIG_TT_WTRIG_SET(x) (((uint16_t)(x) << CAN_TT_WTRIG_TT_WTRIG_SHIFT) & CAN_TT_WTRIG_TT_WTRIG_MASK) -#define CAN_TT_WTRIG_TT_WTRIG_GET(x) (((uint16_t)(x) & CAN_TT_WTRIG_TT_WTRIG_MASK) >> CAN_TT_WTRIG_TT_WTRIG_SHIFT) - - - -/* RBUF register group index macro definition */ -#define CAN_RBUF_BUF0 (0UL) -#define CAN_RBUF_BUF1 (1UL) -#define CAN_RBUF_BUF2 (2UL) -#define CAN_RBUF_BUF3 (3UL) -#define CAN_RBUF_BUF4 (4UL) -#define CAN_RBUF_BUF5 (5UL) -#define CAN_RBUF_BUF6 (6UL) -#define CAN_RBUF_BUF7 (7UL) -#define CAN_RBUF_BUF8 (8UL) -#define CAN_RBUF_BUF9 (9UL) -#define CAN_RBUF_BUF10 (10UL) -#define CAN_RBUF_BUF11 (11UL) -#define CAN_RBUF_BUF12 (12UL) -#define CAN_RBUF_BUF13 (13UL) -#define CAN_RBUF_BUF14 (14UL) -#define CAN_RBUF_BUF15 (15UL) -#define CAN_RBUF_BUF16 (16UL) -#define CAN_RBUF_BUF17 (17UL) -#define CAN_RBUF_BUF18 (18UL) -#define CAN_RBUF_BUF19 (19UL) - -/* TBUF register group index macro definition */ -#define CAN_TBUF_BUF0 (0UL) -#define CAN_TBUF_BUF1 (1UL) -#define CAN_TBUF_BUF2 (2UL) -#define CAN_TBUF_BUF3 (3UL) -#define CAN_TBUF_BUF4 (4UL) -#define CAN_TBUF_BUF5 (5UL) -#define CAN_TBUF_BUF6 (6UL) -#define CAN_TBUF_BUF7 (7UL) -#define CAN_TBUF_BUF8 (8UL) -#define CAN_TBUF_BUF9 (9UL) -#define CAN_TBUF_BUF10 (10UL) -#define CAN_TBUF_BUF11 (11UL) -#define CAN_TBUF_BUF12 (12UL) -#define CAN_TBUF_BUF13 (13UL) -#define CAN_TBUF_BUF14 (14UL) -#define CAN_TBUF_BUF15 (15UL) -#define CAN_TBUF_BUF16 (16UL) -#define CAN_TBUF_BUF17 (17UL) - -/* TTS register group index macro definition */ -#define CAN_TTS_WRD0 (0UL) -#define CAN_TTS_WRD1 (1UL) - - -#endif /* HPM_CAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dac_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dac_regs.h deleted file mode 100644 index 9cb0ca9ad87..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dac_regs.h +++ /dev/null @@ -1,619 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAC_H -#define HPM_DAC_H - -typedef struct { - __W uint32_t CFG0; /* 0x0: */ - __RW uint32_t CFG1; /* 0x4: */ - __RW uint32_t CFG2; /* 0x8: */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t STEP_CFG[4]; /* 0x10 - 0x1C: */ - __RW uint32_t BUF_ADDR[2]; /* 0x20 - 0x24: */ - __RW uint32_t BUF_LENGTH; /* 0x28: */ - __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ - __W uint32_t IRQ_STS; /* 0x30: */ - __RW uint32_t IRQ_EN; /* 0x34: */ - __RW uint32_t DMA_EN; /* 0x38: */ - __R uint8_t RESERVED2[4]; /* 0x3C - 0x3F: Reserved */ - __RW uint32_t ANA_CFG0; /* 0x40: */ - __RW uint32_t CFG0_BAK; /* 0x44: */ - __RW uint32_t STATUS0; /* 0x48: */ -} DAC_Type; - - -/* Bitfield definition for register: CFG0 */ -/* - * SW_DAC_DATA (WO) - * - * dac data used in direct mode(dac_mode==2'b10) - */ -#define DAC_CFG0_SW_DAC_DATA_MASK (0xFFF0000UL) -#define DAC_CFG0_SW_DAC_DATA_SHIFT (16U) -#define DAC_CFG0_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_SW_DAC_DATA_SHIFT) & DAC_CFG0_SW_DAC_DATA_MASK) -#define DAC_CFG0_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_SW_DAC_DATA_MASK) >> DAC_CFG0_SW_DAC_DATA_SHIFT) - -/* - * DMA_AHB_EN (WO) - * - * set to enable internal DMA, it will read one burst if enough space in FIFO. - * Should only be used in buffer mode. - */ -#define DAC_CFG0_DMA_AHB_EN_MASK (0x200U) -#define DAC_CFG0_DMA_AHB_EN_SHIFT (9U) -#define DAC_CFG0_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_DMA_AHB_EN_SHIFT) & DAC_CFG0_DMA_AHB_EN_MASK) -#define DAC_CFG0_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_DMA_AHB_EN_MASK) >> DAC_CFG0_DMA_AHB_EN_SHIFT) - -/* - * SYNC_MODE (WO) - * - * 1: sync dac clock and ahb clock. - * all HW trigger signals are pulse in sync mode, can get faster response; - * 0: async dac clock and ahb_clock - * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - */ -#define DAC_CFG0_SYNC_MODE_MASK (0x100U) -#define DAC_CFG0_SYNC_MODE_SHIFT (8U) -#define DAC_CFG0_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_SYNC_MODE_SHIFT) & DAC_CFG0_SYNC_MODE_MASK) -#define DAC_CFG0_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_SYNC_MODE_MASK) >> DAC_CFG0_SYNC_MODE_SHIFT) - -/* - * TRIG_MODE (WO) - * - * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; - * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - */ -#define DAC_CFG0_TRIG_MODE_MASK (0x80U) -#define DAC_CFG0_TRIG_MODE_SHIFT (7U) -#define DAC_CFG0_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_TRIG_MODE_SHIFT) & DAC_CFG0_TRIG_MODE_MASK) -#define DAC_CFG0_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_TRIG_MODE_MASK) >> DAC_CFG0_TRIG_MODE_SHIFT) - -/* - * HW_TRIG_EN (WO) - * - * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - */ -#define DAC_CFG0_HW_TRIG_EN_MASK (0x40U) -#define DAC_CFG0_HW_TRIG_EN_SHIFT (6U) -#define DAC_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_HW_TRIG_EN_SHIFT) & DAC_CFG0_HW_TRIG_EN_MASK) -#define DAC_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_HW_TRIG_EN_MASK) >> DAC_CFG0_HW_TRIG_EN_SHIFT) - -/* - * DAC_MODE (WO) - * - * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) - * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down - * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - * 11: trigger mode, DAC output from external trigger signals - * Note: - * Trigger mode is not supported in hpm63xx and hpm62xx families. - */ -#define DAC_CFG0_DAC_MODE_MASK (0x30U) -#define DAC_CFG0_DAC_MODE_SHIFT (4U) -#define DAC_CFG0_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_DAC_MODE_SHIFT) & DAC_CFG0_DAC_MODE_MASK) -#define DAC_CFG0_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_DAC_MODE_MASK) >> DAC_CFG0_DAC_MODE_SHIFT) - -/* - * BUF_DATA_MODE (WO) - * - * data structure for buffer mode, - * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. - * 1: each 32-bit data contains 1 point, b11:0 for first - */ -#define DAC_CFG0_BUF_DATA_MODE_MASK (0x8U) -#define DAC_CFG0_BUF_DATA_MODE_SHIFT (3U) -#define DAC_CFG0_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BUF_DATA_MODE_MASK) -#define DAC_CFG0_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BUF_DATA_MODE_MASK) >> DAC_CFG0_BUF_DATA_MODE_SHIFT) - -/* - * HBURST_CFG (WO) - * - * DAC support following fixed burst only - * 000-SINGLE; 011-INCR4; 101: INCR8 - * others are reserved - */ -#define DAC_CFG0_HBURST_CFG_MASK (0x7U) -#define DAC_CFG0_HBURST_CFG_SHIFT (0U) -#define DAC_CFG0_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_HBURST_CFG_SHIFT) & DAC_CFG0_HBURST_CFG_MASK) -#define DAC_CFG0_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_HBURST_CFG_MASK) >> DAC_CFG0_HBURST_CFG_SHIFT) - -/* Bitfield definition for register: CFG1 */ -/* - * ANA_CLK_EN (RW) - * - * set to enable analog clock(divided by ana_div_cfg) - * need to be set in direct mode and trigger mode - */ -#define DAC_CFG1_ANA_CLK_EN_MASK (0x40000UL) -#define DAC_CFG1_ANA_CLK_EN_SHIFT (18U) -#define DAC_CFG1_ANA_CLK_EN_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_CLK_EN_SHIFT) & DAC_CFG1_ANA_CLK_EN_MASK) -#define DAC_CFG1_ANA_CLK_EN_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_CLK_EN_MASK) >> DAC_CFG1_ANA_CLK_EN_SHIFT) - -/* - * ANA_DIV_CFG (RW) - * - * clock divider config for ana_clk to dac analog; - * 00: div2 - * 01: div4 - * 10: div6 - * 11: div8 - */ -#define DAC_CFG1_ANA_DIV_CFG_MASK (0x30000UL) -#define DAC_CFG1_ANA_DIV_CFG_SHIFT (16U) -#define DAC_CFG1_ANA_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_ANA_DIV_CFG_SHIFT) & DAC_CFG1_ANA_DIV_CFG_MASK) -#define DAC_CFG1_ANA_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_ANA_DIV_CFG_MASK) >> DAC_CFG1_ANA_DIV_CFG_SHIFT) - -/* - * DIV_CFG (RW) - * - * step mode and buffer mode: - * defines how many clk_dac cycles to change data to analog, should configured to less than 1MHz data rate. - * Direct mode and trigger mode: - * defines how many clk_dac cycles to accpet the input data, dac will not accept new written data or trigger data before the clock cycles passed. should configured to less than 1MHz. - * Note: - * For direct mode and trigger mode, this config is not supported in hpm63xx and hpm62xx families. - */ -#define DAC_CFG1_DIV_CFG_MASK (0xFFFFU) -#define DAC_CFG1_DIV_CFG_SHIFT (0U) -#define DAC_CFG1_DIV_CFG_SET(x) (((uint32_t)(x) << DAC_CFG1_DIV_CFG_SHIFT) & DAC_CFG1_DIV_CFG_MASK) -#define DAC_CFG1_DIV_CFG_GET(x) (((uint32_t)(x) & DAC_CFG1_DIV_CFG_MASK) >> DAC_CFG1_DIV_CFG_SHIFT) - -/* Bitfield definition for register: CFG2 */ -/* - * DMA_RST1 (WO) - * - * set to reset dma read pointer to buf1_start_addr; - * if set both dma_rst0&dma_rst1, will set to buf0_start_addr - * user can set fifo_clr bit when use dma_rst* - */ -#define DAC_CFG2_DMA_RST1_MASK (0x80U) -#define DAC_CFG2_DMA_RST1_SHIFT (7U) -#define DAC_CFG2_DMA_RST1_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST1_SHIFT) & DAC_CFG2_DMA_RST1_MASK) -#define DAC_CFG2_DMA_RST1_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST1_MASK) >> DAC_CFG2_DMA_RST1_SHIFT) - -/* - * DMA_RST0 (WO) - * - * set to reset dma read pointer to buf0_start_addr - */ -#define DAC_CFG2_DMA_RST0_MASK (0x40U) -#define DAC_CFG2_DMA_RST0_SHIFT (6U) -#define DAC_CFG2_DMA_RST0_SET(x) (((uint32_t)(x) << DAC_CFG2_DMA_RST0_SHIFT) & DAC_CFG2_DMA_RST0_MASK) -#define DAC_CFG2_DMA_RST0_GET(x) (((uint32_t)(x) & DAC_CFG2_DMA_RST0_MASK) >> DAC_CFG2_DMA_RST0_SHIFT) - -/* - * FIFO_CLR (WO) - * - * set to clear FIFO content(set both read/write pointer to 0) - */ -#define DAC_CFG2_FIFO_CLR_MASK (0x20U) -#define DAC_CFG2_FIFO_CLR_SHIFT (5U) -#define DAC_CFG2_FIFO_CLR_SET(x) (((uint32_t)(x) << DAC_CFG2_FIFO_CLR_SHIFT) & DAC_CFG2_FIFO_CLR_MASK) -#define DAC_CFG2_FIFO_CLR_GET(x) (((uint32_t)(x) & DAC_CFG2_FIFO_CLR_MASK) >> DAC_CFG2_FIFO_CLR_SHIFT) - -/* - * BUF_SW_TRIG (RW) - * - * software trigger for buffer mode, - * W1C in single mode. - * RW in continual mode - */ -#define DAC_CFG2_BUF_SW_TRIG_MASK (0x10U) -#define DAC_CFG2_BUF_SW_TRIG_SHIFT (4U) -#define DAC_CFG2_BUF_SW_TRIG_SET(x) (((uint32_t)(x) << DAC_CFG2_BUF_SW_TRIG_SHIFT) & DAC_CFG2_BUF_SW_TRIG_MASK) -#define DAC_CFG2_BUF_SW_TRIG_GET(x) (((uint32_t)(x) & DAC_CFG2_BUF_SW_TRIG_MASK) >> DAC_CFG2_BUF_SW_TRIG_SHIFT) - -/* - * STEP_SW_TRIG3 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG3_MASK (0x8U) -#define DAC_CFG2_STEP_SW_TRIG3_SHIFT (3U) -#define DAC_CFG2_STEP_SW_TRIG3_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG3_SHIFT) & DAC_CFG2_STEP_SW_TRIG3_MASK) -#define DAC_CFG2_STEP_SW_TRIG3_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG3_MASK) >> DAC_CFG2_STEP_SW_TRIG3_SHIFT) - -/* - * STEP_SW_TRIG2 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG2_MASK (0x4U) -#define DAC_CFG2_STEP_SW_TRIG2_SHIFT (2U) -#define DAC_CFG2_STEP_SW_TRIG2_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG2_SHIFT) & DAC_CFG2_STEP_SW_TRIG2_MASK) -#define DAC_CFG2_STEP_SW_TRIG2_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG2_MASK) >> DAC_CFG2_STEP_SW_TRIG2_SHIFT) - -/* - * STEP_SW_TRIG1 (RW) - * - */ -#define DAC_CFG2_STEP_SW_TRIG1_MASK (0x2U) -#define DAC_CFG2_STEP_SW_TRIG1_SHIFT (1U) -#define DAC_CFG2_STEP_SW_TRIG1_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG1_SHIFT) & DAC_CFG2_STEP_SW_TRIG1_MASK) -#define DAC_CFG2_STEP_SW_TRIG1_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG1_MASK) >> DAC_CFG2_STEP_SW_TRIG1_SHIFT) - -/* - * STEP_SW_TRIG0 (RW) - * - * software trigger0 for step mode, - * W1C in single mode. - * RW in continual mode - */ -#define DAC_CFG2_STEP_SW_TRIG0_MASK (0x1U) -#define DAC_CFG2_STEP_SW_TRIG0_SHIFT (0U) -#define DAC_CFG2_STEP_SW_TRIG0_SET(x) (((uint32_t)(x) << DAC_CFG2_STEP_SW_TRIG0_SHIFT) & DAC_CFG2_STEP_SW_TRIG0_MASK) -#define DAC_CFG2_STEP_SW_TRIG0_GET(x) (((uint32_t)(x) & DAC_CFG2_STEP_SW_TRIG0_MASK) >> DAC_CFG2_STEP_SW_TRIG0_SHIFT) - -/* Bitfield definition for register array: STEP_CFG */ -/* - * ROUND_MODE (RW) - * - * 0: stop at end point; - * 1: reload start point, step again - */ -#define DAC_STEP_CFG_ROUND_MODE_MASK (0x20000000UL) -#define DAC_STEP_CFG_ROUND_MODE_SHIFT (29U) -#define DAC_STEP_CFG_ROUND_MODE_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_ROUND_MODE_SHIFT) & DAC_STEP_CFG_ROUND_MODE_MASK) -#define DAC_STEP_CFG_ROUND_MODE_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_ROUND_MODE_MASK) >> DAC_STEP_CFG_ROUND_MODE_SHIFT) - -/* - * UP_DOWN (RW) - * - * 0 for up, 1 for down - */ -#define DAC_STEP_CFG_UP_DOWN_MASK (0x10000000UL) -#define DAC_STEP_CFG_UP_DOWN_SHIFT (28U) -#define DAC_STEP_CFG_UP_DOWN_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_UP_DOWN_SHIFT) & DAC_STEP_CFG_UP_DOWN_MASK) -#define DAC_STEP_CFG_UP_DOWN_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_UP_DOWN_MASK) >> DAC_STEP_CFG_UP_DOWN_SHIFT) - -/* - * END_POINT (RW) - * - */ -#define DAC_STEP_CFG_END_POINT_MASK (0xFFF0000UL) -#define DAC_STEP_CFG_END_POINT_SHIFT (16U) -#define DAC_STEP_CFG_END_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_END_POINT_SHIFT) & DAC_STEP_CFG_END_POINT_MASK) -#define DAC_STEP_CFG_END_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_END_POINT_MASK) >> DAC_STEP_CFG_END_POINT_SHIFT) - -/* - * STEP_NUM (RW) - * - * output data change step_num each DAC clock cycle. - * Ex: if step_num=3, output data sequence is 0,3,6,9 - * NOTE: user should make sure end_point can be reached if step_num is not 1 - * if step_num is 0, output data will always at start point - */ -#define DAC_STEP_CFG_STEP_NUM_MASK (0xF000U) -#define DAC_STEP_CFG_STEP_NUM_SHIFT (12U) -#define DAC_STEP_CFG_STEP_NUM_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_STEP_NUM_SHIFT) & DAC_STEP_CFG_STEP_NUM_MASK) -#define DAC_STEP_CFG_STEP_NUM_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_STEP_NUM_MASK) >> DAC_STEP_CFG_STEP_NUM_SHIFT) - -/* - * START_POINT (RW) - * - */ -#define DAC_STEP_CFG_START_POINT_MASK (0xFFFU) -#define DAC_STEP_CFG_START_POINT_SHIFT (0U) -#define DAC_STEP_CFG_START_POINT_SET(x) (((uint32_t)(x) << DAC_STEP_CFG_START_POINT_SHIFT) & DAC_STEP_CFG_START_POINT_MASK) -#define DAC_STEP_CFG_START_POINT_GET(x) (((uint32_t)(x) & DAC_STEP_CFG_START_POINT_MASK) >> DAC_STEP_CFG_START_POINT_SHIFT) - -/* Bitfield definition for register array: BUF_ADDR */ -/* - * BUF_START_ADDR (RW) - * - * buffer start address, should be 4-byte aligned - * AHB burst can't cross 1K-byte boundary, user should config the address/length/burst to avoid such issue. - */ -#define DAC_BUF_ADDR_BUF_START_ADDR_MASK (0xFFFFFFFCUL) -#define DAC_BUF_ADDR_BUF_START_ADDR_SHIFT (2U) -#define DAC_BUF_ADDR_BUF_START_ADDR_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) -#define DAC_BUF_ADDR_BUF_START_ADDR_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_START_ADDR_MASK) >> DAC_BUF_ADDR_BUF_START_ADDR_SHIFT) - -/* - * BUF_STOP (RW) - * - * set to stop read point at end of bufffer0 - */ -#define DAC_BUF_ADDR_BUF_STOP_MASK (0x1U) -#define DAC_BUF_ADDR_BUF_STOP_SHIFT (0U) -#define DAC_BUF_ADDR_BUF_STOP_SET(x) (((uint32_t)(x) << DAC_BUF_ADDR_BUF_STOP_SHIFT) & DAC_BUF_ADDR_BUF_STOP_MASK) -#define DAC_BUF_ADDR_BUF_STOP_GET(x) (((uint32_t)(x) & DAC_BUF_ADDR_BUF_STOP_MASK) >> DAC_BUF_ADDR_BUF_STOP_SHIFT) - -/* Bitfield definition for register: BUF_LENGTH */ -/* - * BUF1_LEN (RW) - * - * buffer length, 1 indicate one 32bit date, 256K-byte max for one buffer - */ -#define DAC_BUF_LENGTH_BUF1_LEN_MASK (0xFFFF0000UL) -#define DAC_BUF_LENGTH_BUF1_LEN_SHIFT (16U) -#define DAC_BUF_LENGTH_BUF1_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF1_LEN_SHIFT) & DAC_BUF_LENGTH_BUF1_LEN_MASK) -#define DAC_BUF_LENGTH_BUF1_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF1_LEN_MASK) >> DAC_BUF_LENGTH_BUF1_LEN_SHIFT) - -/* - * BUF0_LEN (RW) - * - */ -#define DAC_BUF_LENGTH_BUF0_LEN_MASK (0xFFFFU) -#define DAC_BUF_LENGTH_BUF0_LEN_SHIFT (0U) -#define DAC_BUF_LENGTH_BUF0_LEN_SET(x) (((uint32_t)(x) << DAC_BUF_LENGTH_BUF0_LEN_SHIFT) & DAC_BUF_LENGTH_BUF0_LEN_MASK) -#define DAC_BUF_LENGTH_BUF0_LEN_GET(x) (((uint32_t)(x) & DAC_BUF_LENGTH_BUF0_LEN_MASK) >> DAC_BUF_LENGTH_BUF0_LEN_SHIFT) - -/* Bitfield definition for register: IRQ_STS */ -/* - * AHB_ERROR (W1C) - * - * set if hresp==2'b01(ERROR) - */ -#define DAC_IRQ_STS_AHB_ERROR_MASK (0x8U) -#define DAC_IRQ_STS_AHB_ERROR_SHIFT (3U) -#define DAC_IRQ_STS_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_AHB_ERROR_SHIFT) & DAC_IRQ_STS_AHB_ERROR_MASK) -#define DAC_IRQ_STS_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_AHB_ERROR_MASK) >> DAC_IRQ_STS_AHB_ERROR_SHIFT) - -/* - * FIFO_EMPTY (W1C) - * - */ -#define DAC_IRQ_STS_FIFO_EMPTY_MASK (0x4U) -#define DAC_IRQ_STS_FIFO_EMPTY_SHIFT (2U) -#define DAC_IRQ_STS_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_FIFO_EMPTY_SHIFT) & DAC_IRQ_STS_FIFO_EMPTY_MASK) -#define DAC_IRQ_STS_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_FIFO_EMPTY_MASK) >> DAC_IRQ_STS_FIFO_EMPTY_SHIFT) - -/* - * BUF1_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_BUF1_CMPT_MASK (0x2U) -#define DAC_IRQ_STS_BUF1_CMPT_SHIFT (1U) -#define DAC_IRQ_STS_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF1_CMPT_SHIFT) & DAC_IRQ_STS_BUF1_CMPT_MASK) -#define DAC_IRQ_STS_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF1_CMPT_MASK) >> DAC_IRQ_STS_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (W1C) - * - */ -#define DAC_IRQ_STS_BUF0_CMPT_MASK (0x1U) -#define DAC_IRQ_STS_BUF0_CMPT_SHIFT (0U) -#define DAC_IRQ_STS_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_STS_BUF0_CMPT_SHIFT) & DAC_IRQ_STS_BUF0_CMPT_MASK) -#define DAC_IRQ_STS_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_STS_BUF0_CMPT_MASK) >> DAC_IRQ_STS_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * STEP_CMPT (RW) - * - */ -#define DAC_IRQ_EN_STEP_CMPT_MASK (0x10U) -#define DAC_IRQ_EN_STEP_CMPT_SHIFT (4U) -#define DAC_IRQ_EN_STEP_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_STEP_CMPT_SHIFT) & DAC_IRQ_EN_STEP_CMPT_MASK) -#define DAC_IRQ_EN_STEP_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_STEP_CMPT_MASK) >> DAC_IRQ_EN_STEP_CMPT_SHIFT) - -/* - * AHB_ERROR (RW) - * - */ -#define DAC_IRQ_EN_AHB_ERROR_MASK (0x8U) -#define DAC_IRQ_EN_AHB_ERROR_SHIFT (3U) -#define DAC_IRQ_EN_AHB_ERROR_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_AHB_ERROR_SHIFT) & DAC_IRQ_EN_AHB_ERROR_MASK) -#define DAC_IRQ_EN_AHB_ERROR_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_AHB_ERROR_MASK) >> DAC_IRQ_EN_AHB_ERROR_SHIFT) - -/* - * FIFO_EMPTY (RW) - * - */ -#define DAC_IRQ_EN_FIFO_EMPTY_MASK (0x4U) -#define DAC_IRQ_EN_FIFO_EMPTY_SHIFT (2U) -#define DAC_IRQ_EN_FIFO_EMPTY_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_FIFO_EMPTY_SHIFT) & DAC_IRQ_EN_FIFO_EMPTY_MASK) -#define DAC_IRQ_EN_FIFO_EMPTY_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_FIFO_EMPTY_MASK) >> DAC_IRQ_EN_FIFO_EMPTY_SHIFT) - -/* - * BUF1_CMPT (RW) - * - */ -#define DAC_IRQ_EN_BUF1_CMPT_MASK (0x2U) -#define DAC_IRQ_EN_BUF1_CMPT_SHIFT (1U) -#define DAC_IRQ_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF1_CMPT_SHIFT) & DAC_IRQ_EN_BUF1_CMPT_MASK) -#define DAC_IRQ_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF1_CMPT_MASK) >> DAC_IRQ_EN_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (RW) - * - */ -#define DAC_IRQ_EN_BUF0_CMPT_MASK (0x1U) -#define DAC_IRQ_EN_BUF0_CMPT_SHIFT (0U) -#define DAC_IRQ_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_IRQ_EN_BUF0_CMPT_SHIFT) & DAC_IRQ_EN_BUF0_CMPT_MASK) -#define DAC_IRQ_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_IRQ_EN_BUF0_CMPT_MASK) >> DAC_IRQ_EN_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: DMA_EN */ -/* - * BUF1_CMPT (RW) - * - */ -#define DAC_DMA_EN_BUF1_CMPT_MASK (0x2U) -#define DAC_DMA_EN_BUF1_CMPT_SHIFT (1U) -#define DAC_DMA_EN_BUF1_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF1_CMPT_SHIFT) & DAC_DMA_EN_BUF1_CMPT_MASK) -#define DAC_DMA_EN_BUF1_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF1_CMPT_MASK) >> DAC_DMA_EN_BUF1_CMPT_SHIFT) - -/* - * BUF0_CMPT (RW) - * - */ -#define DAC_DMA_EN_BUF0_CMPT_MASK (0x1U) -#define DAC_DMA_EN_BUF0_CMPT_SHIFT (0U) -#define DAC_DMA_EN_BUF0_CMPT_SET(x) (((uint32_t)(x) << DAC_DMA_EN_BUF0_CMPT_SHIFT) & DAC_DMA_EN_BUF0_CMPT_MASK) -#define DAC_DMA_EN_BUF0_CMPT_GET(x) (((uint32_t)(x) & DAC_DMA_EN_BUF0_CMPT_MASK) >> DAC_DMA_EN_BUF0_CMPT_SHIFT) - -/* Bitfield definition for register: ANA_CFG0 */ -/* - * DAC12BIT_LP_MODE (RW) - * - */ -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK (0x100U) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT (8U) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) -#define DAC_ANA_CFG0_DAC12BIT_LP_MODE_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_LP_MODE_MASK) >> DAC_ANA_CFG0_DAC12BIT_LP_MODE_SHIFT) - -/* - * DAC_CONFIG (RW) - * - */ -#define DAC_ANA_CFG0_DAC_CONFIG_MASK (0xF0U) -#define DAC_ANA_CFG0_DAC_CONFIG_SHIFT (4U) -#define DAC_ANA_CFG0_DAC_CONFIG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC_CONFIG_SHIFT) & DAC_ANA_CFG0_DAC_CONFIG_MASK) -#define DAC_ANA_CFG0_DAC_CONFIG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC_CONFIG_MASK) >> DAC_ANA_CFG0_DAC_CONFIG_SHIFT) - -/* - * CALI_DELTA_V_CFG (RW) - * - */ -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK (0xCU) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT (2U) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) -#define DAC_ANA_CFG0_CALI_DELTA_V_CFG_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_CALI_DELTA_V_CFG_MASK) >> DAC_ANA_CFG0_CALI_DELTA_V_CFG_SHIFT) - -/* - * BYPASS_CALI_GM (RW) - * - */ -#define DAC_ANA_CFG0_BYPASS_CALI_GM_MASK (0x2U) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT (1U) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) -#define DAC_ANA_CFG0_BYPASS_CALI_GM_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_BYPASS_CALI_GM_MASK) >> DAC_ANA_CFG0_BYPASS_CALI_GM_SHIFT) - -/* - * DAC12BIT_EN (RW) - * - */ -#define DAC_ANA_CFG0_DAC12BIT_EN_MASK (0x1U) -#define DAC_ANA_CFG0_DAC12BIT_EN_SHIFT (0U) -#define DAC_ANA_CFG0_DAC12BIT_EN_SET(x) (((uint32_t)(x) << DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) -#define DAC_ANA_CFG0_DAC12BIT_EN_GET(x) (((uint32_t)(x) & DAC_ANA_CFG0_DAC12BIT_EN_MASK) >> DAC_ANA_CFG0_DAC12BIT_EN_SHIFT) - -/* Bitfield definition for register: CFG0_BAK */ -/* - * SW_DAC_DATA (RW) - * - * dac data used in direct mode(dac_mode==2'b10) - */ -#define DAC_CFG0_BAK_SW_DAC_DATA_MASK (0xFFF0000UL) -#define DAC_CFG0_BAK_SW_DAC_DATA_SHIFT (16U) -#define DAC_CFG0_BAK_SW_DAC_DATA_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) -#define DAC_CFG0_BAK_SW_DAC_DATA_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SW_DAC_DATA_MASK) >> DAC_CFG0_BAK_SW_DAC_DATA_SHIFT) - -/* - * DMA_AHB_EN (RW) - * - * set to enable internal DMA, it will read one burst if enough space in FIFO. - * Should only be used in buffer mode. - */ -#define DAC_CFG0_BAK_DMA_AHB_EN_MASK (0x200U) -#define DAC_CFG0_BAK_DMA_AHB_EN_SHIFT (9U) -#define DAC_CFG0_BAK_DMA_AHB_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) -#define DAC_CFG0_BAK_DMA_AHB_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DMA_AHB_EN_MASK) >> DAC_CFG0_BAK_DMA_AHB_EN_SHIFT) - -/* - * SYNC_MODE (RW) - * - * 1: sync dac clock and ahb clock. - * all HW trigger signals are pulse in sync mode, can get faster response; - * 0: async dac clock and ahb_clock - * all HW trigger signals should be level and should be more than one dac clock cycle, used to get accurate output frequency(which may not be divided from AHB clock) - */ -#define DAC_CFG0_BAK_SYNC_MODE_MASK (0x100U) -#define DAC_CFG0_BAK_SYNC_MODE_SHIFT (8U) -#define DAC_CFG0_BAK_SYNC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_SYNC_MODE_SHIFT) & DAC_CFG0_BAK_SYNC_MODE_MASK) -#define DAC_CFG0_BAK_SYNC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_SYNC_MODE_MASK) >> DAC_CFG0_BAK_SYNC_MODE_SHIFT) - -/* - * TRIG_MODE (RW) - * - * 0: single mode, one trigger pulse will send one 12bit data to DAC analog; - * 1: continual mode, if trigger signal(either or HW) is set, DAC will send data if FIFO is not empty, if trigger signal is clear, DAC will stop send data. - */ -#define DAC_CFG0_BAK_TRIG_MODE_MASK (0x80U) -#define DAC_CFG0_BAK_TRIG_MODE_SHIFT (7U) -#define DAC_CFG0_BAK_TRIG_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_TRIG_MODE_SHIFT) & DAC_CFG0_BAK_TRIG_MODE_MASK) -#define DAC_CFG0_BAK_TRIG_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_TRIG_MODE_MASK) >> DAC_CFG0_BAK_TRIG_MODE_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to use trigger signal from trigger_mux, user should config it to pulse in single mode, and level in continual mode - */ -#define DAC_CFG0_BAK_HW_TRIG_EN_MASK (0x40U) -#define DAC_CFG0_BAK_HW_TRIG_EN_SHIFT (6U) -#define DAC_CFG0_BAK_HW_TRIG_EN_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) -#define DAC_CFG0_BAK_HW_TRIG_EN_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HW_TRIG_EN_MASK) >> DAC_CFG0_BAK_HW_TRIG_EN_SHIFT) - -/* - * DAC_MODE (RW) - * - * 00: direct mode, DAC output the fixed configured data(from sw_dac_data) - * 01: step mode, DAC output from start_point to end point, with configured step, can step up or step down - * 10: buffer mode, read data from buffer, then output to analog, internal DMA will load next burst if enough space in local FIFO; - */ -#define DAC_CFG0_BAK_DAC_MODE_MASK (0x30U) -#define DAC_CFG0_BAK_DAC_MODE_SHIFT (4U) -#define DAC_CFG0_BAK_DAC_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_DAC_MODE_SHIFT) & DAC_CFG0_BAK_DAC_MODE_MASK) -#define DAC_CFG0_BAK_DAC_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_DAC_MODE_MASK) >> DAC_CFG0_BAK_DAC_MODE_SHIFT) - -/* - * BUF_DATA_MODE (RW) - * - * data structure for buffer mode, - * 0: each 32-bit data contains 2 points, b11:0 for first, b27:16 for second. - * 1: each 32-bit data contains 1 point, b11:0 for first - */ -#define DAC_CFG0_BAK_BUF_DATA_MODE_MASK (0x8U) -#define DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT (3U) -#define DAC_CFG0_BAK_BUF_DATA_MODE_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) -#define DAC_CFG0_BAK_BUF_DATA_MODE_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_BUF_DATA_MODE_MASK) >> DAC_CFG0_BAK_BUF_DATA_MODE_SHIFT) - -/* - * HBURST_CFG (RW) - * - * DAC support following fixed burst only - * 000-SINGLE; 011-INCR4; 101: INCR8 - * others are reserved - */ -#define DAC_CFG0_BAK_HBURST_CFG_MASK (0x7U) -#define DAC_CFG0_BAK_HBURST_CFG_SHIFT (0U) -#define DAC_CFG0_BAK_HBURST_CFG_SET(x) (((uint32_t)(x) << DAC_CFG0_BAK_HBURST_CFG_SHIFT) & DAC_CFG0_BAK_HBURST_CFG_MASK) -#define DAC_CFG0_BAK_HBURST_CFG_GET(x) (((uint32_t)(x) & DAC_CFG0_BAK_HBURST_CFG_MASK) >> DAC_CFG0_BAK_HBURST_CFG_SHIFT) - -/* Bitfield definition for register: STATUS0 */ -/* - * CUR_BUF_OFFSET (RW) - * - */ -#define DAC_STATUS0_CUR_BUF_OFFSET_MASK (0xFFFF00UL) -#define DAC_STATUS0_CUR_BUF_OFFSET_SHIFT (8U) -#define DAC_STATUS0_CUR_BUF_OFFSET_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) -#define DAC_STATUS0_CUR_BUF_OFFSET_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_OFFSET_MASK) >> DAC_STATUS0_CUR_BUF_OFFSET_SHIFT) - -/* - * CUR_BUF_INDEX (RW) - * - */ -#define DAC_STATUS0_CUR_BUF_INDEX_MASK (0x80U) -#define DAC_STATUS0_CUR_BUF_INDEX_SHIFT (7U) -#define DAC_STATUS0_CUR_BUF_INDEX_SET(x) (((uint32_t)(x) << DAC_STATUS0_CUR_BUF_INDEX_SHIFT) & DAC_STATUS0_CUR_BUF_INDEX_MASK) -#define DAC_STATUS0_CUR_BUF_INDEX_GET(x) (((uint32_t)(x) & DAC_STATUS0_CUR_BUF_INDEX_MASK) >> DAC_STATUS0_CUR_BUF_INDEX_SHIFT) - - - -/* STEP_CFG register group index macro definition */ -#define DAC_STEP_CFG_STEP0 (0UL) -#define DAC_STEP_CFG_STEP1 (1UL) -#define DAC_STEP_CFG_STEP2 (2UL) -#define DAC_STEP_CFG_STEP3 (3UL) - -/* BUF_ADDR register group index macro definition */ -#define DAC_BUF_ADDR_BUF0 (0UL) -#define DAC_BUF_ADDR_BUF1 (1UL) - - -#endif /* HPM_DAC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dao_regs.h deleted file mode 100644 index 671c35bdcf9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dao_regs.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAO_H -#define HPM_DAO_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t CMD; /* 0x8: Command Register */ - __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ - __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ - __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ -} DAO_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * HPF_EN (RW) - * - * Whether HPF is enabled. This HPF is used to filter out the DC part. - */ -#define DAO_CTRL_HPF_EN_MASK (0x20000UL) -#define DAO_CTRL_HPF_EN_SHIFT (17U) -#define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) -#define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) - -/* - * MONO (RW) - * - * Asserted to let the left and right channel output the same value. - */ -#define DAO_CTRL_MONO_MASK (0x80U) -#define DAO_CTRL_MONO_SHIFT (7U) -#define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) -#define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) - -/* - * RIGHT_EN (RW) - * - * Asserted to enable the right channel - */ -#define DAO_CTRL_RIGHT_EN_MASK (0x40U) -#define DAO_CTRL_RIGHT_EN_SHIFT (6U) -#define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) -#define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) - -/* - * LEFT_EN (RW) - * - * Asserted to enable the left channel - */ -#define DAO_CTRL_LEFT_EN_MASK (0x20U) -#define DAO_CTRL_LEFT_EN_SHIFT (5U) -#define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) -#define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) - -/* - * REMAP (RW) - * - * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative - * 0: Don't use remap pwm version - */ -#define DAO_CTRL_REMAP_MASK (0x10U) -#define DAO_CTRL_REMAP_SHIFT (4U) -#define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) -#define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) - -/* - * INVERT (RW) - * - * all the outputs are inverted before sending to pad - */ -#define DAO_CTRL_INVERT_MASK (0x8U) -#define DAO_CTRL_INVERT_SHIFT (3U) -#define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) -#define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) - -/* - * FALSE_LEVEL (RW) - * - * the pad output in False run mode, or when the module is disabled - * 0: all low - * 1: all high - * 2: P-high, N-low - * 3. output is not enabled - */ -#define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) -#define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) -#define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) -#define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) - -/* - * FALSE_RUN (RW) - * - * the module continues to consume data, but all the pads are constant, thus no audio out - */ -#define DAO_CTRL_FALSE_RUN_MASK (0x1U) -#define DAO_CTRL_FALSE_RUN_SHIFT (0U) -#define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) -#define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Self-clear - */ -#define DAO_CMD_SFTRST_MASK (0x2U) -#define DAO_CMD_SFTRST_SHIFT (1U) -#define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) -#define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) - -/* - * RUN (RW) - * - * Enable this module to run. - */ -#define DAO_CMD_RUN_MASK (0x1U) -#define DAO_CMD_RUN_SHIFT (0U) -#define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) -#define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) - -/* Bitfield definition for register: RX_CFGR */ -/* - * CH_MAX (RW) - * - * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 4'h2: 2 channels - * 4'h4: 4 channels - * etc - */ -#define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) -#define DAO_RX_CFGR_CH_MAX_SHIFT (6U) -#define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) -#define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) - -/* Bitfield definition for register: RXSLT */ -/* - * EN (RW) - * - * Slot enable for the channels. - */ -#define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) -#define DAO_RXSLT_EN_SHIFT (0U) -#define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) -#define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_MA_COEF_SHIFT (0U) -#define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) -#define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_B_COEF_SHIFT (0U) -#define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) -#define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_DAO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dma_regs.h deleted file mode 100644 index 214ed0213e0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dma_regs.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMA_H -#define HPM_DMA_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ - __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ - __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ - __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ - __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ - __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel n Source Address Low Part Register */ - __RW uint32_t SRCADDRH; /* 0x4C: Channel n Source Address High Part Register */ - __RW uint32_t DSTADDR; /* 0x50: Channel n Destination Address Low Part Register */ - __RW uint32_t DSTADDRH; /* 0x54: Channel n Destination Address High Part Register */ - __RW uint32_t LLPOINTER; /* 0x58: Channel n Linked List Pointer Low Part Register */ - __RW uint32_t LLPOINTERH; /* 0x5C: Channel n Linked List Pointer High Part Register */ - } CHCTRL[8]; -} DMA_Type; - - -/* Bitfield definition for register: DMACFG */ -/* - * CHAINXFR (RO) - * - * Chain transfer - * 0x0: Chain transfer is not configured - * 0x1: Chain transfer is configured - */ -#define DMA_DMACFG_CHAINXFR_MASK (0x80000000UL) -#define DMA_DMACFG_CHAINXFR_SHIFT (31U) -#define DMA_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHAINXFR_MASK) >> DMA_DMACFG_CHAINXFR_SHIFT) - -/* - * REQSYNC (RO) - * - * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. - * 0x0: Request synchronization is not configured - * 0x1: Request synchronization is configured - */ -#define DMA_DMACFG_REQSYNC_MASK (0x40000000UL) -#define DMA_DMACFG_REQSYNC_SHIFT (30U) -#define DMA_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQSYNC_MASK) >> DMA_DMACFG_REQSYNC_SHIFT) - -/* - * DATAWIDTH (RO) - * - * AXI bus data width - * 0x0: 32 bits - * 0x1: 64 bits - * 0x2: 128 bits - * 0x3: 256 bits - */ -#define DMA_DMACFG_DATAWIDTH_MASK (0x3000000UL) -#define DMA_DMACFG_DATAWIDTH_SHIFT (24U) -#define DMA_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_DATAWIDTH_MASK) >> DMA_DMACFG_DATAWIDTH_SHIFT) - -/* - * ADDRWIDTH (RO) - * - * AXI bus address width - * 0x18: 24 bits - * 0x19: 25 bits - * ... - * 0x40: 64 bits - * Others: Invalid - */ -#define DMA_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) -#define DMA_DMACFG_ADDRWIDTH_SHIFT (17U) -#define DMA_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_ADDRWIDTH_MASK) >> DMA_DMACFG_ADDRWIDTH_SHIFT) - -/* - * CORENUM (RO) - * - * DMA core number - * 0x0: 1 core - * 0x1: 2 cores - */ -#define DMA_DMACFG_CORENUM_MASK (0x10000UL) -#define DMA_DMACFG_CORENUM_SHIFT (16U) -#define DMA_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CORENUM_MASK) >> DMA_DMACFG_CORENUM_SHIFT) - -/* - * BUSNUM (RO) - * - * AXI bus interface number - * 0x0: 1 AXI bus - * 0x1: 2 AXI busses - */ -#define DMA_DMACFG_BUSNUM_MASK (0x8000U) -#define DMA_DMACFG_BUSNUM_SHIFT (15U) -#define DMA_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_BUSNUM_MASK) >> DMA_DMACFG_BUSNUM_SHIFT) - -/* - * REQNUM (RO) - * - * Request/acknowledge pair number - * 0x0: 0 pair - * 0x1: 1 pair - * 0x2: 2 pairs - * ... - * 0x10: 16 pairs - */ -#define DMA_DMACFG_REQNUM_MASK (0x7C00U) -#define DMA_DMACFG_REQNUM_SHIFT (10U) -#define DMA_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQNUM_MASK) >> DMA_DMACFG_REQNUM_SHIFT) - -/* - * FIFODEPTH (RO) - * - * FIFO depth - * 0x4: 4 entries - * 0x8: 8 entries - * 0x10: 16 entries - * 0x20: 32 entries - * Others: Invalid - */ -#define DMA_DMACFG_FIFODEPTH_MASK (0x3F0U) -#define DMA_DMACFG_FIFODEPTH_SHIFT (4U) -#define DMA_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_FIFODEPTH_MASK) >> DMA_DMACFG_FIFODEPTH_SHIFT) - -/* - * CHANNELNUM (RO) - * - * Channel number - * 0x1: 1 channel - * 0x2: 2 channels - * ... - * 0x8: 8 channels - * Others: Invalid - */ -#define DMA_DMACFG_CHANNELNUM_MASK (0xFU) -#define DMA_DMACFG_CHANNELNUM_SHIFT (0U) -#define DMA_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHANNELNUM_MASK) >> DMA_DMACFG_CHANNELNUM_SHIFT) - -/* Bitfield definition for register: DMACTRL */ -/* - * RESET (WO) - * - * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. - * Note: The software reset may cause the in-completion of AXI transaction. - */ -#define DMA_DMACTRL_RESET_MASK (0x1U) -#define DMA_DMACTRL_RESET_SHIFT (0U) -#define DMA_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMA_DMACTRL_RESET_SHIFT) & DMA_DMACTRL_RESET_MASK) -#define DMA_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMA_DMACTRL_RESET_MASK) >> DMA_DMACTRL_RESET_SHIFT) - -/* Bitfield definition for register: CHABORT */ -/* - * CHABORT (WO) - * - * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - */ -#define DMA_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) -#define DMA_CHABORT_CHABORT_SHIFT (0U) -#define DMA_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMA_CHABORT_CHABORT_SHIFT) & DMA_CHABORT_CHABORT_MASK) -#define DMA_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMA_CHABORT_CHABORT_MASK) >> DMA_CHABORT_CHABORT_SHIFT) - -/* Bitfield definition for register: INTSTATUS */ -/* - * TC (W1C) - * - * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. - * 0x0: Channel n has no terminal count status - * 0x1: Channel n has terminal count status - */ -#define DMA_INTSTATUS_TC_MASK (0xFF0000UL) -#define DMA_INTSTATUS_TC_SHIFT (16U) -#define DMA_INTSTATUS_TC_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_TC_SHIFT) & DMA_INTSTATUS_TC_MASK) -#define DMA_INTSTATUS_TC_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_TC_MASK) >> DMA_INTSTATUS_TC_SHIFT) - -/* - * ABORT (W1C) - * - * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. - * 0x0: Channel n has no abort status - * 0x1: Channel n has abort status - */ -#define DMA_INTSTATUS_ABORT_MASK (0xFF00U) -#define DMA_INTSTATUS_ABORT_SHIFT (8U) -#define DMA_INTSTATUS_ABORT_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ABORT_SHIFT) & DMA_INTSTATUS_ABORT_MASK) -#define DMA_INTSTATUS_ABORT_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ABORT_MASK) >> DMA_INTSTATUS_ABORT_SHIFT) - -/* - * ERROR (W1C) - * - * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - * - Bus error - * - Unaligned address - * - Unaligned transfer width - * - Reserved configuration - * 0x0: Channel n has no error status - * 0x1: Channel n has error status - */ -#define DMA_INTSTATUS_ERROR_MASK (0xFFU) -#define DMA_INTSTATUS_ERROR_SHIFT (0U) -#define DMA_INTSTATUS_ERROR_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ERROR_SHIFT) & DMA_INTSTATUS_ERROR_MASK) -#define DMA_INTSTATUS_ERROR_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ERROR_MASK) >> DMA_INTSTATUS_ERROR_SHIFT) - -/* Bitfield definition for register: CHEN */ -/* - * CHEN (RO) - * - * Alias of the Enable field of all ChnCtrl registers - */ -#define DMA_CHEN_CHEN_MASK (0xFFFFFFFFUL) -#define DMA_CHEN_CHEN_SHIFT (0U) -#define DMA_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMA_CHEN_CHEN_MASK) >> DMA_CHEN_CHEN_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CTRL */ -/* - * SRCBUSINFIDX (RW) - * - * Bus interface index that source data is read from - * 0x0: Data is read from bus interface 0 - * 0x1: Data is read from bus interface - */ -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK (0x80000000UL) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT (31U) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) - -/* - * DSTBUSINFIDX (RW) - * - * Bus interface index that destination data is written to - * 0x0: Data is written to bus interface 0 - * 0x1: Data is written to bus interface 1 - */ -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK (0x40000000UL) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT (30U) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) - -/* - * PRIORITY (RW) - * - * Channel priority level - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define DMA_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) -#define DMA_CHCTRL_CTRL_PRIORITY_SHIFT (29U) -#define DMA_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_PRIORITY_SHIFT) & DMA_CHCTRL_CTRL_PRIORITY_MASK) -#define DMA_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_PRIORITY_MASK) >> DMA_CHCTRL_CTRL_PRIORITY_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. - * The burst transfer byte number is (SrcBurstSize * SrcWidth). - * 0x0: 1 transfer - * 0x1: 2 transfers - * 0x2: 4 transfers - * 0x3: 8 transfers - * 0x4: 16 transfers - * 0x5: 32 transfers - * 0x6: 64 transfers - * 0x7: 128 transfers - * 0x8: 256 transfers - * 0x9:512 transfers - * 0xa: 1024 transfers - * 0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - */ -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source transfer width - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - */ -#define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) -#define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) -#define DMA_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) -#define DMA_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination transfer width. - * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. - * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - */ -#define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) -#define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) -#define DMA_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) -#define DMA_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * Source DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define DMA_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) -#define DMA_CHCTRL_CTRL_SRCMODE_SHIFT (17U) -#define DMA_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCMODE_SHIFT) & DMA_CHCTRL_CTRL_SRCMODE_MASK) -#define DMA_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCMODE_MASK) >> DMA_CHCTRL_CTRL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * Destination DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define DMA_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) -#define DMA_CHCTRL_CTRL_DSTMODE_SHIFT (16U) -#define DMA_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTMODE_SHIFT) & DMA_CHCTRL_CTRL_DSTMODE_MASK) -#define DMA_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTMODE_MASK) >> DMA_CHCTRL_CTRL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * Source address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * Destination address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) - -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define DMA_CHCTRL_CTRL_SRCREQSEL_MASK (0xF00U) -#define DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT (8U) -#define DMA_CHCTRL_CTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) -#define DMA_CHCTRL_CTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) >> DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define DMA_CHCTRL_CTRL_DSTREQSEL_MASK (0xF0U) -#define DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT (4U) -#define DMA_CHCTRL_CTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) -#define DMA_CHCTRL_CTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) >> DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) - -/* - * INTABTMASK (RW) - * - * Channel abort interrupt mask - * 0x0: Allow the abort interrupt to be triggered - * 0x1: Disable the abort interrupt - */ -#define DMA_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) -#define DMA_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) -#define DMA_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) -#define DMA_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) >> DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) - -/* - * INTERRMASK (RW) - * - * Channel error interrupt mask - * 0x0: Allow the error interrupt to be triggered - * 0x1: Disable the error interrupt - */ -#define DMA_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) -#define DMA_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) -#define DMA_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) -#define DMA_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) >> DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) - -/* - * INTTCMASK (RW) - * - * Channel terminal count interrupt mask - * 0x0: Allow the terminal count interrupt to be triggered - * 0x1: Disable the terminal count interrupt - */ -#define DMA_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) -#define DMA_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) -#define DMA_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) -#define DMA_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) >> DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) - -/* - * ENABLE (RW) - * - * Channel enable bit - * 0x0: Disable - * 0x1: Enable - */ -#define DMA_CHCTRL_CTRL_ENABLE_MASK (0x1U) -#define DMA_CHCTRL_CTRL_ENABLE_SHIFT (0U) -#define DMA_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_ENABLE_SHIFT) & DMA_CHCTRL_CTRL_ENABLE_MASK) -#define DMA_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_ENABLE_MASK) >> DMA_CHCTRL_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ -/* - * TRANSIZE (RW) - * - * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. - * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - */ -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ -/* - * SRCADDRL (RW) - * - * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - */ -#define DMA_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDRH */ -/* - * SRCADDRH (RW) - * - * High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT (0U) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) >> DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ -/* - * DSTADDRL (RW) - * - * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - */ -#define DMA_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDRH */ -/* - * DSTADDRH (RW) - * - * High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT (0U) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) >> DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ -/* - * LLPOINTERL (RW) - * - * Low part of the pointer to the next descriptor. The pointer must be double word aligned. - */ -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) - -/* - * LLDBUSINFIDX (RW) - * - * Bus interface index that the next descriptor is read from - * 0x0: The next descriptor is read from bus interface 0 - */ -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK (0x1U) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT (0U) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) >> DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTERH */ -/* - * LLPOINTERH (RW) - * - * High part of the pointer to the next descriptor. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT (0U) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) >> DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) - - - -/* CHCTRL register group index macro definition */ -#define DMA_CHCTRL_CH0 (0UL) -#define DMA_CHCTRL_CH1 (1UL) -#define DMA_CHCTRL_CH2 (2UL) -#define DMA_CHCTRL_CH3 (3UL) -#define DMA_CHCTRL_CH4 (4UL) -#define DMA_CHCTRL_CH5 (5UL) -#define DMA_CHCTRL_CH6 (6UL) -#define DMA_CHCTRL_CH7 (7UL) - - -#endif /* HPM_DMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dmamux_regs.h deleted file mode 100644 index e7f67339ea4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_dmamux_regs.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_H -#define HPM_DMAMUX_H - -typedef struct { - __RW uint32_t MUXCFG[16]; /* 0x0 - 0x3C: HDMA MUX0 Configuration */ -} DMAMUX_Type; - - -/* Bitfield definition for register array: MUXCFG */ -/* - * ENABLE (RW) - * - * DMA Mux Channel Enable - * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be - * used to disable or reconfigure a DMA channel. - * 0b - DMA Mux channel is disabled - * 1b - DMA Mux channel is enabled - */ -#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) -#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) -#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) -#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) - -/* - * SOURCE (RW) - * - * DMA Channel Source - * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - */ -#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) -#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) -#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) - - - -/* MUXCFG register group index macro definition */ -#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) -#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) -#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) -#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) -#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) -#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) -#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) -#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) -#define DMAMUX_MUXCFG_XDMA_MUX0 (8UL) -#define DMAMUX_MUXCFG_XDMA_MUX1 (9UL) -#define DMAMUX_MUXCFG_XDMA_MUX2 (10UL) -#define DMAMUX_MUXCFG_XDMA_MUX3 (11UL) -#define DMAMUX_MUXCFG_XDMA_MUX4 (12UL) -#define DMAMUX_MUXCFG_XDMA_MUX5 (13UL) -#define DMAMUX_MUXCFG_XDMA_MUX6 (14UL) -#define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) - - -#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_enet_regs.h deleted file mode 100644 index 676159604f4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_enet_regs.h +++ /dev/null @@ -1,6121 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ENET_H -#define HPM_ENET_H - -typedef struct { - __RW uint32_t MACCFG; /* 0x0: MAC Configuration Register */ - __RW uint32_t MACFF; /* 0x4: MAC Frame Filter */ - __RW uint32_t HASH_H; /* 0x8: Hash Table High Register */ - __RW uint32_t HASH_L; /* 0xC: Hash Table Low Register */ - __RW uint32_t GMII_ADDR; /* 0x10: GMII Address Register */ - __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ - __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ - __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ - __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ - __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ - __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ - __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Register */ - __RW uint32_t LPI_TCR; /* 0x34: LPI Timers Control Register */ - __R uint32_t INTR_STATUS; /* 0x38: Interrupt Status Register */ - __RW uint32_t INTR_MASK; /* 0x3C: Interrupt Mask Register */ - __RW uint32_t MAC_ADDR_0_HIGH; /* 0x40: MAC Address 0 High Register */ - __RW uint32_t MAC_ADDR_0_LOW; /* 0x44: MAC Address 0 Low Register */ - struct { - __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ - __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ - } MAC_ADDR[4]; - __R uint8_t RESERVED1[112]; /* 0x68 - 0xD7: Reserved */ - __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ - __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ - __R uint8_t RESERVED2[32]; /* 0xE0 - 0xFF: Reserved */ - __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ - __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt */ - __RW uint32_t MMC_INTR_TX; /* 0x108: MMC Transmit Interrupt */ - __RW uint32_t MMC_INTR_MASK_RX; /* 0x10C: MMC Receive Interrupt mask */ - __RW uint32_t MMC_INTR_MASK_TX; /* 0x110: MMC Transmit Interrupt Mask */ - __R uint8_t RESERVED3[16]; /* 0x114 - 0x123: Reserved */ - __RW uint32_t TX64OCTETS_GB; /* 0x124: Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. */ - __RW uint32_t TX65TO127OCTETS_GB; /* 0x128: Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX128TO255OCTETS_GB; /* 0x12C: Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX256TO511OCTETS_GB; /* 0x130: Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX512TO1023OCTETS_GB; /* 0x134: Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. */ - __R uint8_t RESERVED4[68]; /* 0x13C - 0x17F: Reserved */ - __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ - __R uint8_t RESERVED5[124]; /* 0x184 - 0x1FF: Reserved */ - __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. */ - __R uint8_t RESERVED6[4]; /* 0x204 - 0x207: Reserved */ - __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. */ - __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */ - __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload */ - __R uint8_t RESERVED8[492]; /* 0x214 - 0x3FF: Reserved */ - struct { - __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ - __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ - __R uint8_t RESERVED0[8]; /* 0x408 - 0x40F: Reserved */ - __RW uint32_t L3_ADDR_0; /* 0x410: Layer 3 Address 0 Register */ - __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ - __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ - __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ - } L3_L4_CFG[1]; - __R uint8_t RESERVED9[356]; /* 0x420 - 0x583: Reserved */ - __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ - __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ - __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ - __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ - __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ - __R uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ - __R uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ - __RW uint32_t SYST_SEC_UPD; /* 0x710: System Time - Seconds Update Register */ - __RW uint32_t SYST_NSEC_UPD; /* 0x714: System Time - Nanoseconds Update Register */ - __RW uint32_t TS_ADDEND; /* 0x718: Timestamp Addend Register */ - __RW uint32_t TGTTM_SEC; /* 0x71C: Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x720: Target Time Nanoseconds Register */ - __RW uint32_t SYSTM_H_SEC; /* 0x724: System Time - Higher Word Seconds Register */ - __R uint32_t TS_STATUS; /* 0x728: Timestamp Status Register */ - __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ - __R uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ - __R uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ - __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ - __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS Interval Register */ - __RW uint32_t PPS0_WIDTH; /* 0x764: PPS Width Register */ - __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ - struct { - __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ - __RW uint32_t INTERVAL; /* 0x788: PPS Interval Register */ - __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ - __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ - } PPS[3]; - __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ - __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ - __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ - __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ - __RW uint32_t DMA_RX_DESC_LIST_ADDR; /* 0x100C: Receive Descriptor List Address Register */ - __RW uint32_t DMA_TX_DESC_LIST_ADDR; /* 0x1010: Transmit Descriptor List Address Register */ - __RW uint32_t DMA_STATUS; /* 0x1014: Status Register */ - __RW uint32_t DMA_OP_MODE; /* 0x1018: Operation Mode Register */ - __RW uint32_t DMA_INTR_EN; /* 0x101C: Interrupt Enable Register */ - __RW uint32_t DMA_MISS_OVF_CNT; /* 0x1020: Missed Frame And Buffer Overflow Counter Register */ - __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ - __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ - __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ - __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ - __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ - __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ - __R uint8_t RESERVED15[8112]; /* 0x1058 - 0x3007: Reserved */ - __RW uint32_t CTRL2; /* 0x3008: Control Register 1 */ - __R uint8_t RESERVED16[28]; /* 0x300C - 0x3027: Reserved */ -} ENET_Type; - - -/* Bitfield definition for register: MACCFG */ -/* - * SARC (RW) - * - * Source Address Insertion or Replacement Control - * This field controls the source address insertion or replacement for all transmitted frames. - * Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: - * - 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. - * - 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * - 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * Note: - Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, - * that is, the current frame does not use the updated value. - * - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - */ -#define ENET_MACCFG_SARC_MASK (0x70000000UL) -#define ENET_MACCFG_SARC_SHIFT (28U) -#define ENET_MACCFG_SARC_SET(x) (((uint32_t)(x) << ENET_MACCFG_SARC_SHIFT) & ENET_MACCFG_SARC_MASK) -#define ENET_MACCFG_SARC_GET(x) (((uint32_t)(x) & ENET_MACCFG_SARC_MASK) >> ENET_MACCFG_SARC_SHIFT) - -/* - * TWOKPE (RW) - * - * IEEE 802.3as Support for 2K Packets - * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. - * When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. - * When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. - * When Bit 20 is set, setting this bit has no effect on Giant Frame status. - */ -#define ENET_MACCFG_TWOKPE_MASK (0x8000000UL) -#define ENET_MACCFG_TWOKPE_SHIFT (27U) -#define ENET_MACCFG_TWOKPE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TWOKPE_SHIFT) & ENET_MACCFG_TWOKPE_MASK) -#define ENET_MACCFG_TWOKPE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TWOKPE_MASK) >> ENET_MACCFG_TWOKPE_SHIFT) - -/* - * SFTERR (RW) - * - * SMII Force Transmit Error - * When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_SFTERR_MASK (0x4000000UL) -#define ENET_MACCFG_SFTERR_SHIFT (26U) -#define ENET_MACCFG_SFTERR_SET(x) (((uint32_t)(x) << ENET_MACCFG_SFTERR_SHIFT) & ENET_MACCFG_SFTERR_MASK) -#define ENET_MACCFG_SFTERR_GET(x) (((uint32_t)(x) & ENET_MACCFG_SFTERR_MASK) >> ENET_MACCFG_SFTERR_SHIFT) - -/* - * CST (RW) - * - * CRC Stripping for Type Frames - * When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. - * This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - */ -#define ENET_MACCFG_CST_MASK (0x2000000UL) -#define ENET_MACCFG_CST_SHIFT (25U) -#define ENET_MACCFG_CST_SET(x) (((uint32_t)(x) << ENET_MACCFG_CST_SHIFT) & ENET_MACCFG_CST_MASK) -#define ENET_MACCFG_CST_GET(x) (((uint32_t)(x) & ENET_MACCFG_CST_MASK) >> ENET_MACCFG_CST_SHIFT) - -/* - * TC (RW) - * - * Transmit Configuration in RGMII, SGMII, or SMII - * When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - * or SGMII port. When this bit is reset, no such information is driven to the PHY. - * This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_TC_MASK (0x1000000UL) -#define ENET_MACCFG_TC_SHIFT (24U) -#define ENET_MACCFG_TC_SET(x) (((uint32_t)(x) << ENET_MACCFG_TC_SHIFT) & ENET_MACCFG_TC_MASK) -#define ENET_MACCFG_TC_GET(x) (((uint32_t)(x) & ENET_MACCFG_TC_MASK) >> ENET_MACCFG_TC_SHIFT) - -/* - * WD (RW) - * - * Watchdog Disable - * When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - */ -#define ENET_MACCFG_WD_MASK (0x800000UL) -#define ENET_MACCFG_WD_SHIFT (23U) -#define ENET_MACCFG_WD_SET(x) (((uint32_t)(x) << ENET_MACCFG_WD_SHIFT) & ENET_MACCFG_WD_MASK) -#define ENET_MACCFG_WD_GET(x) (((uint32_t)(x) & ENET_MACCFG_WD_MASK) >> ENET_MACCFG_WD_SHIFT) - -/* - * JD (RW) - * - * Jabber Disable - * When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. - * When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - */ -#define ENET_MACCFG_JD_MASK (0x400000UL) -#define ENET_MACCFG_JD_SHIFT (22U) -#define ENET_MACCFG_JD_SET(x) (((uint32_t)(x) << ENET_MACCFG_JD_SHIFT) & ENET_MACCFG_JD_MASK) -#define ENET_MACCFG_JD_GET(x) (((uint32_t)(x) & ENET_MACCFG_JD_MASK) >> ENET_MACCFG_JD_SHIFT) - -/* - * BE (RW) - * - * Frame Burst Enable - * When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - */ -#define ENET_MACCFG_BE_MASK (0x200000UL) -#define ENET_MACCFG_BE_SHIFT (21U) -#define ENET_MACCFG_BE_SET(x) (((uint32_t)(x) << ENET_MACCFG_BE_SHIFT) & ENET_MACCFG_BE_MASK) -#define ENET_MACCFG_BE_GET(x) (((uint32_t)(x) & ENET_MACCFG_BE_MASK) >> ENET_MACCFG_BE_SHIFT) - -/* - * JE (RW) - * - * Jumbo Frame Enable - * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - */ -#define ENET_MACCFG_JE_MASK (0x100000UL) -#define ENET_MACCFG_JE_SHIFT (20U) -#define ENET_MACCFG_JE_SET(x) (((uint32_t)(x) << ENET_MACCFG_JE_SHIFT) & ENET_MACCFG_JE_MASK) -#define ENET_MACCFG_JE_GET(x) (((uint32_t)(x) & ENET_MACCFG_JE_MASK) >> ENET_MACCFG_JE_SHIFT) - -/* - * IFG (RW) - * - * Inter-Frame Gap - * These bits control the minimum IFG between frames during transmission. - * - 000: 96 bit times - * - 001: 88 bit times - * - 010: 80 bit times - ... - * - 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). - * Lower values are not considered. - * In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - * When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - */ -#define ENET_MACCFG_IFG_MASK (0xE0000UL) -#define ENET_MACCFG_IFG_SHIFT (17U) -#define ENET_MACCFG_IFG_SET(x) (((uint32_t)(x) << ENET_MACCFG_IFG_SHIFT) & ENET_MACCFG_IFG_MASK) -#define ENET_MACCFG_IFG_GET(x) (((uint32_t)(x) & ENET_MACCFG_IFG_MASK) >> ENET_MACCFG_IFG_SHIFT) - -/* - * DCRS (RW) - * - * Disable Carrier Sense During Transmission - * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - * This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. - * When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - */ -#define ENET_MACCFG_DCRS_MASK (0x10000UL) -#define ENET_MACCFG_DCRS_SHIFT (16U) -#define ENET_MACCFG_DCRS_SET(x) (((uint32_t)(x) << ENET_MACCFG_DCRS_SHIFT) & ENET_MACCFG_DCRS_MASK) -#define ENET_MACCFG_DCRS_GET(x) (((uint32_t)(x) & ENET_MACCFG_DCRS_MASK) >> ENET_MACCFG_DCRS_SHIFT) - -/* - * PS (RW) - * - * Port Select - * This bit selects the Ethernet line speed. - * - 0: For 1000 Mbps operations - * - 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. - * In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, - * this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - */ -#define ENET_MACCFG_PS_MASK (0x8000U) -#define ENET_MACCFG_PS_SHIFT (15U) -#define ENET_MACCFG_PS_SET(x) (((uint32_t)(x) << ENET_MACCFG_PS_SHIFT) & ENET_MACCFG_PS_MASK) -#define ENET_MACCFG_PS_GET(x) (((uint32_t)(x) & ENET_MACCFG_PS_MASK) >> ENET_MACCFG_PS_SHIFT) - -/* - * FES (RW) - * - * Speed - * This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: - * - 0: 10 Mbps - * - 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. - * This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. - * This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. - * In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. - * In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - */ -#define ENET_MACCFG_FES_MASK (0x4000U) -#define ENET_MACCFG_FES_SHIFT (14U) -#define ENET_MACCFG_FES_SET(x) (((uint32_t)(x) << ENET_MACCFG_FES_SHIFT) & ENET_MACCFG_FES_MASK) -#define ENET_MACCFG_FES_GET(x) (((uint32_t)(x) & ENET_MACCFG_FES_MASK) >> ENET_MACCFG_FES_SHIFT) - -/* - * DO (RW) - * - * Disable Receive Own - * When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. - * When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. - * This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - */ -#define ENET_MACCFG_DO_MASK (0x2000U) -#define ENET_MACCFG_DO_SHIFT (13U) -#define ENET_MACCFG_DO_SET(x) (((uint32_t)(x) << ENET_MACCFG_DO_SHIFT) & ENET_MACCFG_DO_MASK) -#define ENET_MACCFG_DO_GET(x) (((uint32_t)(x) & ENET_MACCFG_DO_MASK) >> ENET_MACCFG_DO_SHIFT) - -/* - * LM (RW) - * - * Loopback Mode - * When this bit is set, the MAC operates in the loopback mode at GMII or MII. - * The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - */ -#define ENET_MACCFG_LM_MASK (0x1000U) -#define ENET_MACCFG_LM_SHIFT (12U) -#define ENET_MACCFG_LM_SET(x) (((uint32_t)(x) << ENET_MACCFG_LM_SHIFT) & ENET_MACCFG_LM_MASK) -#define ENET_MACCFG_LM_GET(x) (((uint32_t)(x) & ENET_MACCFG_LM_MASK) >> ENET_MACCFG_LM_SHIFT) - -/* - * DM (RW) - * - * Duplex Mode - * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - */ -#define ENET_MACCFG_DM_MASK (0x800U) -#define ENET_MACCFG_DM_SHIFT (11U) -#define ENET_MACCFG_DM_SET(x) (((uint32_t)(x) << ENET_MACCFG_DM_SHIFT) & ENET_MACCFG_DM_MASK) -#define ENET_MACCFG_DM_GET(x) (((uint32_t)(x) & ENET_MACCFG_DM_MASK) >> ENET_MACCFG_DM_SHIFT) - -/* - * IPC (RW) - * - * Checksum Offload - * When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. - * It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) - * of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. - * The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) - * and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). - * When this bit is reset, this function is disabled. - * When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - */ -#define ENET_MACCFG_IPC_MASK (0x400U) -#define ENET_MACCFG_IPC_SHIFT (10U) -#define ENET_MACCFG_IPC_SET(x) (((uint32_t)(x) << ENET_MACCFG_IPC_SHIFT) & ENET_MACCFG_IPC_MASK) -#define ENET_MACCFG_IPC_GET(x) (((uint32_t)(x) & ENET_MACCFG_IPC_MASK) >> ENET_MACCFG_IPC_SHIFT) - -/* - * DR (RW) - * - * Disable Retry - * When this bit is set, the MAC attempts only one transmission. - * When a collision occurs on the GMII or MII interface, - * the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. - * When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - */ -#define ENET_MACCFG_DR_MASK (0x200U) -#define ENET_MACCFG_DR_SHIFT (9U) -#define ENET_MACCFG_DR_SET(x) (((uint32_t)(x) << ENET_MACCFG_DR_SHIFT) & ENET_MACCFG_DR_MASK) -#define ENET_MACCFG_DR_GET(x) (((uint32_t)(x) & ENET_MACCFG_DR_MASK) >> ENET_MACCFG_DR_SHIFT) - -/* - * LUD (RW) - * - * Link Up or Down - * This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: - * - 0: Link Down - * - 1: Link Up - */ -#define ENET_MACCFG_LUD_MASK (0x100U) -#define ENET_MACCFG_LUD_SHIFT (8U) -#define ENET_MACCFG_LUD_SET(x) (((uint32_t)(x) << ENET_MACCFG_LUD_SHIFT) & ENET_MACCFG_LUD_MASK) -#define ENET_MACCFG_LUD_GET(x) (((uint32_t)(x) & ENET_MACCFG_LUD_MASK) >> ENET_MACCFG_LUD_SHIFT) - -/* - * ACS (RW) - * - * Automatic Pad or CRC Stripping - * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. - * All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. - * When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - */ -#define ENET_MACCFG_ACS_MASK (0x80U) -#define ENET_MACCFG_ACS_SHIFT (7U) -#define ENET_MACCFG_ACS_SET(x) (((uint32_t)(x) << ENET_MACCFG_ACS_SHIFT) & ENET_MACCFG_ACS_MASK) -#define ENET_MACCFG_ACS_GET(x) (((uint32_t)(x) & ENET_MACCFG_ACS_MASK) >> ENET_MACCFG_ACS_SHIFT) - -/* - * BL (RW) - * - * Back-Off Limit - * The Back-Off limit determines the random integer number (r) of slot time delays - * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. - * This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. - * - 00: k= min (n, 10) - * - 01: k = min (n, 8) - * - 10: k = min (n, 4) - * - 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - */ -#define ENET_MACCFG_BL_MASK (0x60U) -#define ENET_MACCFG_BL_SHIFT (5U) -#define ENET_MACCFG_BL_SET(x) (((uint32_t)(x) << ENET_MACCFG_BL_SHIFT) & ENET_MACCFG_BL_MASK) -#define ENET_MACCFG_BL_GET(x) (((uint32_t)(x) & ENET_MACCFG_BL_MASK) >> ENET_MACCFG_BL_SHIFT) - -/* - * DC (RW) - * - * Deferral Check - * When this bit is set, the deferral check function is enabled in the MAC. - * The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, - * when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - * If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - * the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, - * but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. - * For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, - * the transmitter transmits and collision happens. - * Because of collision, the transmitter needs to back off and then defer again after back off completion. - * In such a scenario, the deferral timer is reset to 0 and it is restarted. - */ -#define ENET_MACCFG_DC_MASK (0x10U) -#define ENET_MACCFG_DC_SHIFT (4U) -#define ENET_MACCFG_DC_SET(x) (((uint32_t)(x) << ENET_MACCFG_DC_SHIFT) & ENET_MACCFG_DC_MASK) -#define ENET_MACCFG_DC_GET(x) (((uint32_t)(x) & ENET_MACCFG_DC_MASK) >> ENET_MACCFG_DC_SHIFT) - -/* - * TE (RW) - * - * Transmitter Enable - * When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - * the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - */ -#define ENET_MACCFG_TE_MASK (0x8U) -#define ENET_MACCFG_TE_SHIFT (3U) -#define ENET_MACCFG_TE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TE_SHIFT) & ENET_MACCFG_TE_MASK) -#define ENET_MACCFG_TE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TE_MASK) >> ENET_MACCFG_TE_SHIFT) - -/* - * RE (RW) - * - * Receiver Enable - * When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, - * the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - */ -#define ENET_MACCFG_RE_MASK (0x4U) -#define ENET_MACCFG_RE_SHIFT (2U) -#define ENET_MACCFG_RE_SET(x) (((uint32_t)(x) << ENET_MACCFG_RE_SHIFT) & ENET_MACCFG_RE_MASK) -#define ENET_MACCFG_RE_GET(x) (((uint32_t)(x) & ENET_MACCFG_RE_MASK) >> ENET_MACCFG_RE_SHIFT) - -/* - * PRELEN (RW) - * - * Preamble Length for Transmit frames - * These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - * The preamble reduction occurs only when the MAC is operating in the full-duplex mode. - * - 2'b00: 7 bytes of preamble - * - 2'b01: 5 bytes of preamble - * - 2'b10: 3 bytes of preamble - * - 2'b11: Reserved - */ -#define ENET_MACCFG_PRELEN_MASK (0x3U) -#define ENET_MACCFG_PRELEN_SHIFT (0U) -#define ENET_MACCFG_PRELEN_SET(x) (((uint32_t)(x) << ENET_MACCFG_PRELEN_SHIFT) & ENET_MACCFG_PRELEN_MASK) -#define ENET_MACCFG_PRELEN_GET(x) (((uint32_t)(x) & ENET_MACCFG_PRELEN_MASK) >> ENET_MACCFG_PRELEN_SHIFT) - -/* Bitfield definition for register: MACFF */ -/* - * RA (RW) - * - * Receive All - * When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. - * The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, - * the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - */ -#define ENET_MACFF_RA_MASK (0x80000000UL) -#define ENET_MACFF_RA_SHIFT (31U) -#define ENET_MACFF_RA_SET(x) (((uint32_t)(x) << ENET_MACFF_RA_SHIFT) & ENET_MACFF_RA_MASK) -#define ENET_MACFF_RA_GET(x) (((uint32_t)(x) & ENET_MACFF_RA_MASK) >> ENET_MACFF_RA_SHIFT) - -/* - * DNTU (RW) - * - * Drop non-TCP/UDP over IP Frames - * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. - * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - */ -#define ENET_MACFF_DNTU_MASK (0x200000UL) -#define ENET_MACFF_DNTU_SHIFT (21U) -#define ENET_MACFF_DNTU_SET(x) (((uint32_t)(x) << ENET_MACFF_DNTU_SHIFT) & ENET_MACFF_DNTU_MASK) -#define ENET_MACFF_DNTU_GET(x) (((uint32_t)(x) & ENET_MACFF_DNTU_MASK) >> ENET_MACFF_DNTU_SHIFT) - -/* - * IPFE (RW) - * - * Layer 3 and Layer 4 Filter Enable - * When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, - * this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - */ -#define ENET_MACFF_IPFE_MASK (0x100000UL) -#define ENET_MACFF_IPFE_SHIFT (20U) -#define ENET_MACFF_IPFE_SET(x) (((uint32_t)(x) << ENET_MACFF_IPFE_SHIFT) & ENET_MACFF_IPFE_MASK) -#define ENET_MACFF_IPFE_GET(x) (((uint32_t)(x) & ENET_MACFF_IPFE_MASK) >> ENET_MACFF_IPFE_SHIFT) - -/* - * VTFE (RW) - * - * VLAN Tag Filter Enable - * When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. - * When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - */ -#define ENET_MACFF_VTFE_MASK (0x8000U) -#define ENET_MACFF_VTFE_SHIFT (15U) -#define ENET_MACFF_VTFE_SET(x) (((uint32_t)(x) << ENET_MACFF_VTFE_SHIFT) & ENET_MACFF_VTFE_MASK) -#define ENET_MACFF_VTFE_GET(x) (((uint32_t)(x) & ENET_MACFF_VTFE_MASK) >> ENET_MACFF_VTFE_SHIFT) - -/* - * HPF (RW) - * - * Hash or Perfect Filter - * When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. - * When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - */ -#define ENET_MACFF_HPF_MASK (0x400U) -#define ENET_MACFF_HPF_SHIFT (10U) -#define ENET_MACFF_HPF_SET(x) (((uint32_t)(x) << ENET_MACFF_HPF_SHIFT) & ENET_MACFF_HPF_MASK) -#define ENET_MACFF_HPF_GET(x) (((uint32_t)(x) & ENET_MACFF_HPF_MASK) >> ENET_MACFF_HPF_SHIFT) - -/* - * SAF (RW) - * - * Source Address Filter Enable - * When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - * the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - */ -#define ENET_MACFF_SAF_MASK (0x200U) -#define ENET_MACFF_SAF_SHIFT (9U) -#define ENET_MACFF_SAF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAF_SHIFT) & ENET_MACFF_SAF_MASK) -#define ENET_MACFF_SAF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAF_MASK) >> ENET_MACFF_SAF_SHIFT) - -/* - * SAIF (RW) - * - * SA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. - * When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - */ -#define ENET_MACFF_SAIF_MASK (0x100U) -#define ENET_MACFF_SAIF_SHIFT (8U) -#define ENET_MACFF_SAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAIF_SHIFT) & ENET_MACFF_SAIF_MASK) -#define ENET_MACFF_SAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAIF_MASK) >> ENET_MACFF_SAIF_SHIFT) - -/* - * PCF (RW) - * - * Pass Control Frames - * These bits control the forwarding of all control frames (including unicast and multicast Pause frames). - * - 00: MAC filters all control frames from reaching the application. - * - 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. - * - 10: MAC forwards all control frames to application even if they fail the Address Filter. - * - 11: MAC forwards control frames that pass the Address Filter. - * The following conditions should be true for the Pause frames processing: - * - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - * - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - * - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. - * Note: This field should be set to 01 only when the Condition 1 is true, - * that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. - * Otherwise, the Pause frame filtering may be inconsistent. - * When Condition 1 is false, the Pause frames are considered as generic control frames. - * Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, - * you should set the PCF field to 10 or 11 (as required by the application). - */ -#define ENET_MACFF_PCF_MASK (0xC0U) -#define ENET_MACFF_PCF_SHIFT (6U) -#define ENET_MACFF_PCF_SET(x) (((uint32_t)(x) << ENET_MACFF_PCF_SHIFT) & ENET_MACFF_PCF_MASK) -#define ENET_MACFF_PCF_GET(x) (((uint32_t)(x) & ENET_MACFF_PCF_MASK) >> ENET_MACFF_PCF_SHIFT) - -/* - * DBF (RW) - * - * Disable Broadcast Frames - * When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. - * When this bit is reset, the AFM module passes all received broadcast frames. - */ -#define ENET_MACFF_DBF_MASK (0x20U) -#define ENET_MACFF_DBF_SHIFT (5U) -#define ENET_MACFF_DBF_SET(x) (((uint32_t)(x) << ENET_MACFF_DBF_SHIFT) & ENET_MACFF_DBF_MASK) -#define ENET_MACFF_DBF_GET(x) (((uint32_t)(x) & ENET_MACFF_DBF_MASK) >> ENET_MACFF_DBF_SHIFT) - -/* - * PM (RW) - * - * Pass All Multicast - * When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. - * When reset, filtering of multicast frame depends on HMC bit. - */ -#define ENET_MACFF_PM_MASK (0x10U) -#define ENET_MACFF_PM_SHIFT (4U) -#define ENET_MACFF_PM_SET(x) (((uint32_t)(x) << ENET_MACFF_PM_SHIFT) & ENET_MACFF_PM_MASK) -#define ENET_MACFF_PM_GET(x) (((uint32_t)(x) & ENET_MACFF_PM_MASK) >> ENET_MACFF_PM_SHIFT) - -/* - * DAIF (RW) - * - * DA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. - * When reset, normal filtering of frames is performed. - */ -#define ENET_MACFF_DAIF_MASK (0x8U) -#define ENET_MACFF_DAIF_SHIFT (3U) -#define ENET_MACFF_DAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_DAIF_SHIFT) & ENET_MACFF_DAIF_MASK) -#define ENET_MACFF_DAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_DAIF_MASK) >> ENET_MACFF_DAIF_SHIFT) - -/* - * HMC (RW) - * - * Hash Multicast - * When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, - * the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HMC_MASK (0x4U) -#define ENET_MACFF_HMC_SHIFT (2U) -#define ENET_MACFF_HMC_SET(x) (((uint32_t)(x) << ENET_MACFF_HMC_SHIFT) & ENET_MACFF_HMC_MASK) -#define ENET_MACFF_HMC_GET(x) (((uint32_t)(x) & ENET_MACFF_HMC_MASK) >> ENET_MACFF_HMC_SHIFT) - -/* - * HUC (RW) - * - * Hash Unicast - * When set, the MAC performs destination address filtering of unicast frames according to the hash table. - * When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HUC_MASK (0x2U) -#define ENET_MACFF_HUC_SHIFT (1U) -#define ENET_MACFF_HUC_SET(x) (((uint32_t)(x) << ENET_MACFF_HUC_SHIFT) & ENET_MACFF_HUC_MASK) -#define ENET_MACFF_HUC_GET(x) (((uint32_t)(x) & ENET_MACFF_HUC_MASK) >> ENET_MACFF_HUC_SHIFT) - -/* - * PR (RW) - * - * Promiscuous Mode - * When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - * The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - */ -#define ENET_MACFF_PR_MASK (0x1U) -#define ENET_MACFF_PR_SHIFT (0U) -#define ENET_MACFF_PR_SET(x) (((uint32_t)(x) << ENET_MACFF_PR_SHIFT) & ENET_MACFF_PR_MASK) -#define ENET_MACFF_PR_GET(x) (((uint32_t)(x) & ENET_MACFF_PR_MASK) >> ENET_MACFF_PR_SHIFT) - -/* Bitfield definition for register: HASH_H */ -/* - * HTH (RW) - * - * Hash Table High - * This field contains the upper 32 bits of the Hash table. - */ -#define ENET_HASH_H_HTH_MASK (0xFFFFFFFFUL) -#define ENET_HASH_H_HTH_SHIFT (0U) -#define ENET_HASH_H_HTH_SET(x) (((uint32_t)(x) << ENET_HASH_H_HTH_SHIFT) & ENET_HASH_H_HTH_MASK) -#define ENET_HASH_H_HTH_GET(x) (((uint32_t)(x) & ENET_HASH_H_HTH_MASK) >> ENET_HASH_H_HTH_SHIFT) - -/* Bitfield definition for register: HASH_L */ -/* - * HTL (RW) - * - * Hash Table Low - * This field contains the lower 32 bits of the Hash table. - */ -#define ENET_HASH_L_HTL_MASK (0xFFFFFFFFUL) -#define ENET_HASH_L_HTL_SHIFT (0U) -#define ENET_HASH_L_HTL_SET(x) (((uint32_t)(x) << ENET_HASH_L_HTL_SHIFT) & ENET_HASH_L_HTL_MASK) -#define ENET_HASH_L_HTL_GET(x) (((uint32_t)(x) & ENET_HASH_L_HTL_MASK) >> ENET_HASH_L_HTL_SHIFT) - -/* Bitfield definition for register: GMII_ADDR */ -/* - * PA (RW) - * - * Physical Layer Address - * This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - */ -#define ENET_GMII_ADDR_PA_MASK (0xF800U) -#define ENET_GMII_ADDR_PA_SHIFT (11U) -#define ENET_GMII_ADDR_PA_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_PA_SHIFT) & ENET_GMII_ADDR_PA_MASK) -#define ENET_GMII_ADDR_PA_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_PA_MASK) >> ENET_GMII_ADDR_PA_SHIFT) - -/* - * GR (RW) - * - * GMII Register - * These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - */ -#define ENET_GMII_ADDR_GR_MASK (0x7C0U) -#define ENET_GMII_ADDR_GR_SHIFT (6U) -#define ENET_GMII_ADDR_GR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GR_SHIFT) & ENET_GMII_ADDR_GR_MASK) -#define ENET_GMII_ADDR_GR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GR_MASK) >> ENET_GMII_ADDR_GR_SHIFT) - -/* - * CR (RW) - * - * CSR Clock Range - * The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. - * The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. - * The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) - * ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. - * - 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. - * - 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. - * - 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. - * - 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. - * - 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. - * - 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. - * - 0110, 0111: Reserved - * When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. - * For example, - * when CSR clock is of 100 MHz frequency and you program these bits as 1010, - * then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. - * Program the following values only if the interfacing chips support faster MDC clocks. - * - 1000: CSR clock/4 - * - 1001: CSR clock/6 - * - 1010: CSR clock/8 - * - 1011: CSR clock/10 - * - 1100: CSR clock/12 - * - 1101: CSR clock/14 - * - 1110: CSR clock/16 - * - 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - */ -#define ENET_GMII_ADDR_CR_MASK (0x3CU) -#define ENET_GMII_ADDR_CR_SHIFT (2U) -#define ENET_GMII_ADDR_CR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_CR_SHIFT) & ENET_GMII_ADDR_CR_MASK) -#define ENET_GMII_ADDR_CR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_CR_MASK) >> ENET_GMII_ADDR_CR_SHIFT) - -/* - * GW (RW) - * - * GMII Write - * When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, - * it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - */ -#define ENET_GMII_ADDR_GW_MASK (0x2U) -#define ENET_GMII_ADDR_GW_SHIFT (1U) -#define ENET_GMII_ADDR_GW_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GW_SHIFT) & ENET_GMII_ADDR_GW_MASK) -#define ENET_GMII_ADDR_GW_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GW_MASK) >> ENET_GMII_ADDR_GW_SHIFT) - -/* - * GB (RW) - * - * GMII Busy - * This bit should read logic 0 before writing to Register 4 and Register 5. - * During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - * Register 5 is invalid until this bit is cleared by the MAC. - * Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. - * Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. - * The subsequent read or write operation should happen only after the previous operation is complete. - * Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, - * there is no change in the functionality of this bit even when the PHY is not present. - */ -#define ENET_GMII_ADDR_GB_MASK (0x1U) -#define ENET_GMII_ADDR_GB_SHIFT (0U) -#define ENET_GMII_ADDR_GB_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GB_SHIFT) & ENET_GMII_ADDR_GB_MASK) -#define ENET_GMII_ADDR_GB_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GB_MASK) >> ENET_GMII_ADDR_GB_SHIFT) - -/* Bitfield definition for register: GMII_DATA */ -/* - * GD (RW) - * - * GMII Data - * This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation - * or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - */ -#define ENET_GMII_DATA_GD_MASK (0xFFFFU) -#define ENET_GMII_DATA_GD_SHIFT (0U) -#define ENET_GMII_DATA_GD_SET(x) (((uint32_t)(x) << ENET_GMII_DATA_GD_SHIFT) & ENET_GMII_DATA_GD_MASK) -#define ENET_GMII_DATA_GD_GET(x) (((uint32_t)(x) & ENET_GMII_DATA_GD_MASK) >> ENET_GMII_DATA_GD_SHIFT) - -/* Bitfield definition for register: FLOWCTRL */ -/* - * PT (RW) - * - * Pause Time - * This field holds the value to be used in the Pause Time field in the transmit control frame. - * If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - * then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - */ -#define ENET_FLOWCTRL_PT_MASK (0xFFFF0000UL) -#define ENET_FLOWCTRL_PT_SHIFT (16U) -#define ENET_FLOWCTRL_PT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PT_SHIFT) & ENET_FLOWCTRL_PT_MASK) -#define ENET_FLOWCTRL_PT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PT_MASK) >> ENET_FLOWCTRL_PT_SHIFT) - -/* - * DZPQ (RW) - * - * Disable Zero-Quanta Pause - * When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of - * the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). - * When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - */ -#define ENET_FLOWCTRL_DZPQ_MASK (0x80U) -#define ENET_FLOWCTRL_DZPQ_SHIFT (7U) -#define ENET_FLOWCTRL_DZPQ_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_DZPQ_SHIFT) & ENET_FLOWCTRL_DZPQ_MASK) -#define ENET_FLOWCTRL_DZPQ_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_DZPQ_MASK) >> ENET_FLOWCTRL_DZPQ_SHIFT) - -/* - * PLT (RW) - * - * Pause Low Threshold - * This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. - * The threshold values should be always less than the Pause Time configured in Bits[31:16]. - * For example, if PT = 100H (256 slot-times), and PLT = 01, - * then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. - * The following list provides the threshold values for different values: - * - 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). - * - 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). - * - 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). - * - 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - */ -#define ENET_FLOWCTRL_PLT_MASK (0x30U) -#define ENET_FLOWCTRL_PLT_SHIFT (4U) -#define ENET_FLOWCTRL_PLT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PLT_SHIFT) & ENET_FLOWCTRL_PLT_MASK) -#define ENET_FLOWCTRL_PLT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PLT_MASK) >> ENET_FLOWCTRL_PLT_SHIFT) - -/* - * UP (RW) - * - * Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. - * When this bit is set, the MAC can also detect Pause frames with unicast address of the station. - * This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. - * When this bit is reset, the MAC only detects Pause frames with unique multicast address. - */ -#define ENET_FLOWCTRL_UP_MASK (0x8U) -#define ENET_FLOWCTRL_UP_SHIFT (3U) -#define ENET_FLOWCTRL_UP_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_UP_SHIFT) & ENET_FLOWCTRL_UP_MASK) -#define ENET_FLOWCTRL_UP_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_UP_MASK) >> ENET_FLOWCTRL_UP_SHIFT) - -/* - * RFE (RW) - * - * Receive Flow Control Enable - * When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - */ -#define ENET_FLOWCTRL_RFE_MASK (0x4U) -#define ENET_FLOWCTRL_RFE_SHIFT (2U) -#define ENET_FLOWCTRL_RFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_RFE_SHIFT) & ENET_FLOWCTRL_RFE_MASK) -#define ENET_FLOWCTRL_RFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_RFE_MASK) >> ENET_FLOWCTRL_RFE_SHIFT) - -/* - * TFE (RW) - * - * Transmit Flow Control Enable - * In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. - * When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. - * In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - */ -#define ENET_FLOWCTRL_TFE_MASK (0x2U) -#define ENET_FLOWCTRL_TFE_SHIFT (1U) -#define ENET_FLOWCTRL_TFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_TFE_SHIFT) & ENET_FLOWCTRL_TFE_MASK) -#define ENET_FLOWCTRL_TFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_TFE_MASK) >> ENET_FLOWCTRL_TFE_SHIFT) - -/* - * FCB_BPA (RW) - * - * Flow Control Busy or Backpressure Activate - * This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. - * In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - * To initiate a Pause frame, the Application must set this bit to 1'b1. - * During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. - * After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. - * The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, - * when this bit is set (and TFE is set), then backpressure is asserted by the MAC. - * During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. - * This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. - * When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - */ -#define ENET_FLOWCTRL_FCB_BPA_MASK (0x1U) -#define ENET_FLOWCTRL_FCB_BPA_SHIFT (0U) -#define ENET_FLOWCTRL_FCB_BPA_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_FCB_BPA_SHIFT) & ENET_FLOWCTRL_FCB_BPA_MASK) -#define ENET_FLOWCTRL_FCB_BPA_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_FCB_BPA_MASK) >> ENET_FLOWCTRL_FCB_BPA_SHIFT) - -/* Bitfield definition for register: VLAN_TAG */ -/* - * VTHM (RW) - * - * VLAN Tag Hash Table Match Enable - * When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). - * A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. - * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, - * the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - */ -#define ENET_VLAN_TAG_VTHM_MASK (0x80000UL) -#define ENET_VLAN_TAG_VTHM_SHIFT (19U) -#define ENET_VLAN_TAG_VTHM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTHM_SHIFT) & ENET_VLAN_TAG_VTHM_MASK) -#define ENET_VLAN_TAG_VTHM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTHM_MASK) >> ENET_VLAN_TAG_VTHM_SHIFT) - -/* - * ESVL (RW) - * - * Enable S-VLAN - * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - */ -#define ENET_VLAN_TAG_ESVL_MASK (0x40000UL) -#define ENET_VLAN_TAG_ESVL_SHIFT (18U) -#define ENET_VLAN_TAG_ESVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ESVL_SHIFT) & ENET_VLAN_TAG_ESVL_MASK) -#define ENET_VLAN_TAG_ESVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ESVL_MASK) >> ENET_VLAN_TAG_ESVL_SHIFT) - -/* - * VTIM (RW) - * - * VLAN Tag Inverse Match Enable - * When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - * The frames with matched VLAN Tag are marked as matched. - */ -#define ENET_VLAN_TAG_VTIM_MASK (0x20000UL) -#define ENET_VLAN_TAG_VTIM_SHIFT (17U) -#define ENET_VLAN_TAG_VTIM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTIM_SHIFT) & ENET_VLAN_TAG_VTIM_MASK) -#define ENET_VLAN_TAG_VTIM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTIM_MASK) >> ENET_VLAN_TAG_VTIM_SHIFT) - -/* - * ETV (RW) - * - * Enable 12-Bit VLAN Tag Comparison - * When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - * Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, - * only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. - * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - */ -#define ENET_VLAN_TAG_ETV_MASK (0x10000UL) -#define ENET_VLAN_TAG_ETV_SHIFT (16U) -#define ENET_VLAN_TAG_ETV_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ETV_SHIFT) & ENET_VLAN_TAG_ETV_MASK) -#define ENET_VLAN_TAG_ETV_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ETV_MASK) >> ENET_VLAN_TAG_ETV_SHIFT) - -/* - * VL (RW) - * - * VLAN Tag Identifier for Receive Frames - * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. - * The following list describes the bits of this field: - * - Bits [15:13]: User Priority - * - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - * - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - * and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - */ -#define ENET_VLAN_TAG_VL_MASK (0xFFFFU) -#define ENET_VLAN_TAG_VL_SHIFT (0U) -#define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) -#define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) - -/* Bitfield definition for register: RWKFRMFILT */ -/* - * WKUPFRMFILT (RW) - * - * This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). - * The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. - * The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. - * Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - * Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - */ -#define ENET_RWKFRMFILT_WKUPFRMFILT_MASK (0xFFFFFFFFUL) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT (0U) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SET(x) (((uint32_t)(x) << ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) -#define ENET_RWKFRMFILT_WKUPFRMFILT_GET(x) (((uint32_t)(x) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) >> ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) - -/* Bitfield definition for register: PMT_CSR */ -/* - * RWKFILTRST (RW) - * - * Remote Wake-Up Frame Filter Register Pointer Reset - * When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - */ -#define ENET_PMT_CSR_RWKFILTRST_MASK (0x80000000UL) -#define ENET_PMT_CSR_RWKFILTRST_SHIFT (31U) -#define ENET_PMT_CSR_RWKFILTRST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKFILTRST_SHIFT) & ENET_PMT_CSR_RWKFILTRST_MASK) -#define ENET_PMT_CSR_RWKFILTRST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKFILTRST_MASK) >> ENET_PMT_CSR_RWKFILTRST_SHIFT) - -/* - * RWKPTR (RW) - * - * Remote Wake-up FIFO Pointer - * This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, - * the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - * The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - */ -#define ENET_PMT_CSR_RWKPTR_MASK (0x1F000000UL) -#define ENET_PMT_CSR_RWKPTR_SHIFT (24U) -#define ENET_PMT_CSR_RWKPTR_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPTR_SHIFT) & ENET_PMT_CSR_RWKPTR_MASK) -#define ENET_PMT_CSR_RWKPTR_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPTR_MASK) >> ENET_PMT_CSR_RWKPTR_SHIFT) - -/* - * GLBLUCAST (RW) - * - * Global Unicast - * When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - */ -#define ENET_PMT_CSR_GLBLUCAST_MASK (0x200U) -#define ENET_PMT_CSR_GLBLUCAST_SHIFT (9U) -#define ENET_PMT_CSR_GLBLUCAST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_GLBLUCAST_SHIFT) & ENET_PMT_CSR_GLBLUCAST_MASK) -#define ENET_PMT_CSR_GLBLUCAST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_GLBLUCAST_MASK) >> ENET_PMT_CSR_GLBLUCAST_SHIFT) - -/* - * RWKPRCVD (RW) - * - * Remote Wake-Up Frame Received - * When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_RWKPRCVD_MASK (0x40U) -#define ENET_PMT_CSR_RWKPRCVD_SHIFT (6U) -#define ENET_PMT_CSR_RWKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPRCVD_SHIFT) & ENET_PMT_CSR_RWKPRCVD_MASK) -#define ENET_PMT_CSR_RWKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPRCVD_MASK) >> ENET_PMT_CSR_RWKPRCVD_SHIFT) - -/* - * MGKPRCVD (RW) - * - * Magic Packet Received - * When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_MGKPRCVD_MASK (0x20U) -#define ENET_PMT_CSR_MGKPRCVD_SHIFT (5U) -#define ENET_PMT_CSR_MGKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPRCVD_SHIFT) & ENET_PMT_CSR_MGKPRCVD_MASK) -#define ENET_PMT_CSR_MGKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPRCVD_MASK) >> ENET_PMT_CSR_MGKPRCVD_SHIFT) - -/* - * RWKPKTEN (RW) - * - * Remote Wake-Up Frame Enable - * When set, enables generation of a power management event because of remote wake-up frame reception. - */ -#define ENET_PMT_CSR_RWKPKTEN_MASK (0x4U) -#define ENET_PMT_CSR_RWKPKTEN_SHIFT (2U) -#define ENET_PMT_CSR_RWKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPKTEN_SHIFT) & ENET_PMT_CSR_RWKPKTEN_MASK) -#define ENET_PMT_CSR_RWKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPKTEN_MASK) >> ENET_PMT_CSR_RWKPKTEN_SHIFT) - -/* - * MGKPKTEN (RW) - * - * Magic Packet Enable - * When set, enables generation of a power management event because of magic packet reception. - */ -#define ENET_PMT_CSR_MGKPKTEN_MASK (0x2U) -#define ENET_PMT_CSR_MGKPKTEN_SHIFT (1U) -#define ENET_PMT_CSR_MGKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPKTEN_SHIFT) & ENET_PMT_CSR_MGKPKTEN_MASK) -#define ENET_PMT_CSR_MGKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPKTEN_MASK) >> ENET_PMT_CSR_MGKPKTEN_SHIFT) - -/* - * PWRDWN (RW) - * - * Power Down - * When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. - * This bit is then self-cleared and the power-down mode is disabled. - * The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. - * The frames, received by the MAC after this bit is cleared, are forwarded to the application. - * This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. - * Note: You can gate-off the CSR clock during the power-down mode. - * However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - */ -#define ENET_PMT_CSR_PWRDWN_MASK (0x1U) -#define ENET_PMT_CSR_PWRDWN_SHIFT (0U) -#define ENET_PMT_CSR_PWRDWN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_PWRDWN_SHIFT) & ENET_PMT_CSR_PWRDWN_MASK) -#define ENET_PMT_CSR_PWRDWN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_PWRDWN_MASK) >> ENET_PMT_CSR_PWRDWN_SHIFT) - -/* Bitfield definition for register: LPI_CSR */ -/* - * LPITXA (RW) - * - * LPI TX Automate - * This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. - * This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, - * the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. - * The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - * In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. - * If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), - * when the MAC is in the LPI mode, the MAC exits the LPI mode. - * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - */ -#define ENET_LPI_CSR_LPITXA_MASK (0x80000UL) -#define ENET_LPI_CSR_LPITXA_SHIFT (19U) -#define ENET_LPI_CSR_LPITXA_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPITXA_SHIFT) & ENET_LPI_CSR_LPITXA_MASK) -#define ENET_LPI_CSR_LPITXA_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPITXA_MASK) >> ENET_LPI_CSR_LPITXA_SHIFT) - -/* - * PLSEN (RW) - * - * PHY Link Status Enable - * This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. - * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - * When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - */ -#define ENET_LPI_CSR_PLSEN_MASK (0x40000UL) -#define ENET_LPI_CSR_PLSEN_SHIFT (18U) -#define ENET_LPI_CSR_PLSEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLSEN_SHIFT) & ENET_LPI_CSR_PLSEN_MASK) -#define ENET_LPI_CSR_PLSEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLSEN_MASK) >> ENET_LPI_CSR_PLSEN_SHIFT) - -/* - * PLS (RW) - * - * PHY Link Status - * This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. - * When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - */ -#define ENET_LPI_CSR_PLS_MASK (0x20000UL) -#define ENET_LPI_CSR_PLS_SHIFT (17U) -#define ENET_LPI_CSR_PLS_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLS_SHIFT) & ENET_LPI_CSR_PLS_MASK) -#define ENET_LPI_CSR_PLS_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLS_MASK) >> ENET_LPI_CSR_PLS_SHIFT) - -/* - * LPIEN (RW) - * - * LPI Enable - * When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. - * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - */ -#define ENET_LPI_CSR_LPIEN_MASK (0x10000UL) -#define ENET_LPI_CSR_LPIEN_SHIFT (16U) -#define ENET_LPI_CSR_LPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPIEN_SHIFT) & ENET_LPI_CSR_LPIEN_MASK) -#define ENET_LPI_CSR_LPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPIEN_MASK) >> ENET_LPI_CSR_LPIEN_SHIFT) - -/* - * RLPIST (RW) - * - * Receive LPI State - * When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_RLPIST_MASK (0x200U) -#define ENET_LPI_CSR_RLPIST_SHIFT (9U) -#define ENET_LPI_CSR_RLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIST_SHIFT) & ENET_LPI_CSR_RLPIST_MASK) -#define ENET_LPI_CSR_RLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIST_MASK) >> ENET_LPI_CSR_RLPIST_SHIFT) - -/* - * TLPIST (RW) - * - * Transmit LPI State - * When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_TLPIST_MASK (0x100U) -#define ENET_LPI_CSR_TLPIST_SHIFT (8U) -#define ENET_LPI_CSR_TLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIST_SHIFT) & ENET_LPI_CSR_TLPIST_MASK) -#define ENET_LPI_CSR_TLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIST_MASK) >> ENET_LPI_CSR_TLPIST_SHIFT) - -/* - * RLPIEX (RW) - * - * Receive LPI Exit - * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. - * This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEX_MASK (0x8U) -#define ENET_LPI_CSR_RLPIEX_SHIFT (3U) -#define ENET_LPI_CSR_RLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEX_SHIFT) & ENET_LPI_CSR_RLPIEX_MASK) -#define ENET_LPI_CSR_RLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEX_MASK) >> ENET_LPI_CSR_RLPIEX_SHIFT) - -/* - * RLPIEN (RW) - * - * Receive LPI Entry - * When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEN_MASK (0x4U) -#define ENET_LPI_CSR_RLPIEN_SHIFT (2U) -#define ENET_LPI_CSR_RLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEN_SHIFT) & ENET_LPI_CSR_RLPIEN_MASK) -#define ENET_LPI_CSR_RLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEN_MASK) >> ENET_LPI_CSR_RLPIEN_SHIFT) - -/* - * TLPIEX (RW) - * - * Transmit LPI Exit - * When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEX_MASK (0x2U) -#define ENET_LPI_CSR_TLPIEX_SHIFT (1U) -#define ENET_LPI_CSR_TLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEX_SHIFT) & ENET_LPI_CSR_TLPIEX_MASK) -#define ENET_LPI_CSR_TLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEX_MASK) >> ENET_LPI_CSR_TLPIEX_SHIFT) - -/* - * TLPIEN (RW) - * - * Transmit LPI Entry - * When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEN_MASK (0x1U) -#define ENET_LPI_CSR_TLPIEN_SHIFT (0U) -#define ENET_LPI_CSR_TLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEN_SHIFT) & ENET_LPI_CSR_TLPIEN_MASK) -#define ENET_LPI_CSR_TLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEN_MASK) >> ENET_LPI_CSR_TLPIEN_SHIFT) - -/* Bitfield definition for register: LPI_TCR */ -/* - * LST (RW) - * - * LPI LS TIMER - * This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - * The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. - * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - */ -#define ENET_LPI_TCR_LST_MASK (0x3FF0000UL) -#define ENET_LPI_TCR_LST_SHIFT (16U) -#define ENET_LPI_TCR_LST_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_LST_SHIFT) & ENET_LPI_TCR_LST_MASK) -#define ENET_LPI_TCR_LST_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_LST_MASK) >> ENET_LPI_TCR_LST_SHIFT) - -/* - * TWT (RW) - * - * LPI TW TIMER - * This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - * the LPI pattern to the PHY and before it resumes the normal transmission. - * The TLPIEX status bit is set after the expiry of this timer. - */ -#define ENET_LPI_TCR_TWT_MASK (0xFFFFU) -#define ENET_LPI_TCR_TWT_SHIFT (0U) -#define ENET_LPI_TCR_TWT_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_TWT_SHIFT) & ENET_LPI_TCR_TWT_MASK) -#define ENET_LPI_TCR_TWT_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_TWT_MASK) >> ENET_LPI_TCR_TWT_SHIFT) - -/* Bitfield definition for register: INTR_STATUS */ -/* - * GPIIS (RO) - * - * GPI Interrupt Status - * When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - * of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. - * This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - * When the GPIO feature is not enabled, this bit is reserved. - */ -#define ENET_INTR_STATUS_GPIIS_MASK (0x800U) -#define ENET_INTR_STATUS_GPIIS_SHIFT (11U) -#define ENET_INTR_STATUS_GPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_GPIIS_MASK) >> ENET_INTR_STATUS_GPIIS_SHIFT) - -/* - * LPIIS (RO) - * - * LPI Interrupt Status - * When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. - * This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - */ -#define ENET_INTR_STATUS_LPIIS_MASK (0x400U) -#define ENET_INTR_STATUS_LPIIS_SHIFT (10U) -#define ENET_INTR_STATUS_LPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_LPIIS_MASK) >> ENET_INTR_STATUS_LPIIS_SHIFT) - -/* - * TSIS (RO) - * - * Timestamp Interrupt Status - * When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - * - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - * - There is an overflow in the seconds register. - * - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - */ -#define ENET_INTR_STATUS_TSIS_MASK (0x200U) -#define ENET_INTR_STATUS_TSIS_SHIFT (9U) -#define ENET_INTR_STATUS_TSIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_TSIS_MASK) >> ENET_INTR_STATUS_TSIS_SHIFT) - -/* - * MMCRXIPIS (RO) - * - * MMC Receive Checksum Offload Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIPIS_MASK (0x80U) -#define ENET_INTR_STATUS_MMCRXIPIS_SHIFT (7U) -#define ENET_INTR_STATUS_MMCRXIPIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIPIS_MASK) >> ENET_INTR_STATUS_MMCRXIPIS_SHIFT) - -/* - * MMCTXIS (RO) - * - * MMC Transmit Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCTXIS_MASK (0x40U) -#define ENET_INTR_STATUS_MMCTXIS_SHIFT (6U) -#define ENET_INTR_STATUS_MMCTXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCTXIS_MASK) >> ENET_INTR_STATUS_MMCTXIS_SHIFT) - -/* - * MMCRXIS (RO) - * - * MMC Receive Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIS_MASK (0x20U) -#define ENET_INTR_STATUS_MMCRXIS_SHIFT (5U) -#define ENET_INTR_STATUS_MMCRXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIS_MASK) >> ENET_INTR_STATUS_MMCRXIS_SHIFT) - -/* - * MMCIS (RO) - * - * MMC Interrupt Status - * This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - */ -#define ENET_INTR_STATUS_MMCIS_MASK (0x10U) -#define ENET_INTR_STATUS_MMCIS_SHIFT (4U) -#define ENET_INTR_STATUS_MMCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCIS_MASK) >> ENET_INTR_STATUS_MMCIS_SHIFT) - -/* - * PMTIS (RO) - * - * PMT Interrupt Status - * This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). - * This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - */ -#define ENET_INTR_STATUS_PMTIS_MASK (0x8U) -#define ENET_INTR_STATUS_PMTIS_SHIFT (3U) -#define ENET_INTR_STATUS_PMTIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PMTIS_MASK) >> ENET_INTR_STATUS_PMTIS_SHIFT) - -/* - * PCSANCIS (RO) - * - * PCS Auto-Negotiation Complete - * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation to the AN Status register. - */ -#define ENET_INTR_STATUS_PCSANCIS_MASK (0x4U) -#define ENET_INTR_STATUS_PCSANCIS_SHIFT (2U) -#define ENET_INTR_STATUS_PCSANCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSANCIS_MASK) >> ENET_INTR_STATUS_PCSANCIS_SHIFT) - -/* - * PCSLCHGIS (RO) - * - * PCS Link Status Changed - * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation on the AN Status register. - */ -#define ENET_INTR_STATUS_PCSLCHGIS_MASK (0x2U) -#define ENET_INTR_STATUS_PCSLCHGIS_SHIFT (1U) -#define ENET_INTR_STATUS_PCSLCHGIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSLCHGIS_MASK) >> ENET_INTR_STATUS_PCSLCHGIS_SHIFT) - -/* - * RGSMIIIS (RO) - * - * RGMII or SMII Interrupt Status - * This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). - * This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - */ -#define ENET_INTR_STATUS_RGSMIIIS_MASK (0x1U) -#define ENET_INTR_STATUS_RGSMIIIS_SHIFT (0U) -#define ENET_INTR_STATUS_RGSMIIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_RGSMIIIS_MASK) >> ENET_INTR_STATUS_RGSMIIIS_SHIFT) - -/* Bitfield definition for register: INTR_MASK */ -/* - * LPIIM (RW) - * - * LPI Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_LPIIM_MASK (0x400U) -#define ENET_INTR_MASK_LPIIM_SHIFT (10U) -#define ENET_INTR_MASK_LPIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_LPIIM_SHIFT) & ENET_INTR_MASK_LPIIM_MASK) -#define ENET_INTR_MASK_LPIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_LPIIM_MASK) >> ENET_INTR_MASK_LPIIM_SHIFT) - -/* - * TSIM (RW) - * - * Timestamp Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_TSIM_MASK (0x200U) -#define ENET_INTR_MASK_TSIM_SHIFT (9U) -#define ENET_INTR_MASK_TSIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_TSIM_SHIFT) & ENET_INTR_MASK_TSIM_MASK) -#define ENET_INTR_MASK_TSIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_TSIM_MASK) >> ENET_INTR_MASK_TSIM_SHIFT) - -/* - * PMTIM (RW) - * - * PMT Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PMTIM_MASK (0x8U) -#define ENET_INTR_MASK_PMTIM_SHIFT (3U) -#define ENET_INTR_MASK_PMTIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PMTIM_SHIFT) & ENET_INTR_MASK_PMTIM_MASK) -#define ENET_INTR_MASK_PMTIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PMTIM_MASK) >> ENET_INTR_MASK_PMTIM_SHIFT) - -/* - * PCSANCIM (RW) - * - * PCS AN Completion Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSANCIM_MASK (0x4U) -#define ENET_INTR_MASK_PCSANCIM_SHIFT (2U) -#define ENET_INTR_MASK_PCSANCIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSANCIM_SHIFT) & ENET_INTR_MASK_PCSANCIM_MASK) -#define ENET_INTR_MASK_PCSANCIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSANCIM_MASK) >> ENET_INTR_MASK_PCSANCIM_SHIFT) - -/* - * PCSLCHGIM (RW) - * - * PCS Link Status Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSLCHGIM_MASK (0x2U) -#define ENET_INTR_MASK_PCSLCHGIM_SHIFT (1U) -#define ENET_INTR_MASK_PCSLCHGIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSLCHGIM_SHIFT) & ENET_INTR_MASK_PCSLCHGIM_MASK) -#define ENET_INTR_MASK_PCSLCHGIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSLCHGIM_MASK) >> ENET_INTR_MASK_PCSLCHGIM_SHIFT) - -/* - * RGSMIIIM (RW) - * - * RGMII or SMII Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_RGSMIIIM_MASK (0x1U) -#define ENET_INTR_MASK_RGSMIIIM_SHIFT (0U) -#define ENET_INTR_MASK_RGSMIIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_RGSMIIIM_SHIFT) & ENET_INTR_MASK_RGSMIIIM_MASK) -#define ENET_INTR_MASK_RGSMIIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_RGSMIIIM_MASK) >> ENET_INTR_MASK_RGSMIIIM_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_HIGH */ -/* - * AE (RO) - * - * Address Enable - * This bit is RO. The bit value is fixed at 1. - */ -#define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_0_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_AE_MASK) >> ENET_MAC_ADDR_0_HIGH_AE_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address0 [47:32] - * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_LOW */ -/* - * ADDRLO (RW) - * - * MAC Address0 [31:0] - * This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: HIGH */ -/* - * AE (RW) - * - * Address Enable - * When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - */ -#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_AE_SHIFT) & ENET_MAC_ADDR_HIGH_AE_MASK) -#define ENET_MAC_ADDR_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_AE_MASK) >> ENET_MAC_ADDR_HIGH_AE_SHIFT) - -/* - * SA (RW) - * - * Source Address - * When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - */ -#define ENET_MAC_ADDR_HIGH_SA_MASK (0x40000000UL) -#define ENET_MAC_ADDR_HIGH_SA_SHIFT (30U) -#define ENET_MAC_ADDR_HIGH_SA_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_SA_SHIFT) & ENET_MAC_ADDR_HIGH_SA_MASK) -#define ENET_MAC_ADDR_HIGH_SA_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_SA_MASK) >> ENET_MAC_ADDR_HIGH_SA_SHIFT) - -/* - * MBC (RW) - * - * Mask Byte Control - * These bits are mask control bits for comparison of each of the MAC Address bytes. - * When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. - * Each bit controls the masking of the bytes as follows: - * - Bit 29: Register 18[15:8] - * - Bit 28: Register 18[7:0] - * - Bit 27: Register 19[31:24] - - * ... - * - Bit 24: Register 19[7:0] - * You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - */ -#define ENET_MAC_ADDR_HIGH_MBC_MASK (0x3F000000UL) -#define ENET_MAC_ADDR_HIGH_MBC_SHIFT (24U) -#define ENET_MAC_ADDR_HIGH_MBC_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_MBC_SHIFT) & ENET_MAC_ADDR_HIGH_MBC_MASK) -#define ENET_MAC_ADDR_HIGH_MBC_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_MBC_MASK) >> ENET_MAC_ADDR_HIGH_MBC_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address1 [47:32] - * This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - */ -#define ENET_MAC_ADDR_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: LOW */ -/* - * ADDRLO (RW) - * - * MAC Address1 [31:0] - * This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - */ -#define ENET_MAC_ADDR_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register: XMII_CSR */ -/* - * FALSCARDET (RW) - * - * False Carrier Detected - * This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_FALSCARDET_MASK (0x20U) -#define ENET_XMII_CSR_FALSCARDET_SHIFT (5U) -#define ENET_XMII_CSR_FALSCARDET_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_FALSCARDET_SHIFT) & ENET_XMII_CSR_FALSCARDET_MASK) -#define ENET_XMII_CSR_FALSCARDET_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_FALSCARDET_MASK) >> ENET_XMII_CSR_FALSCARDET_SHIFT) - -/* - * JABTO (RW) - * - * Jabber Timeout - * This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_JABTO_MASK (0x10U) -#define ENET_XMII_CSR_JABTO_SHIFT (4U) -#define ENET_XMII_CSR_JABTO_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_JABTO_SHIFT) & ENET_XMII_CSR_JABTO_MASK) -#define ENET_XMII_CSR_JABTO_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_JABTO_MASK) >> ENET_XMII_CSR_JABTO_SHIFT) - -/* - * LNKSTS (RW) - * - * Link Status - * This bit indicates whether the link between the local PHY and the remote PHY is up or down. - * It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. - * The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - */ -#define ENET_XMII_CSR_LNKSTS_MASK (0x8U) -#define ENET_XMII_CSR_LNKSTS_SHIFT (3U) -#define ENET_XMII_CSR_LNKSTS_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSTS_SHIFT) & ENET_XMII_CSR_LNKSTS_MASK) -#define ENET_XMII_CSR_LNKSTS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSTS_MASK) >> ENET_XMII_CSR_LNKSTS_SHIFT) - -/* - * LNKSPEED (RW) - * - * Link Speed - * This bit indicates the current speed of the link: - * - 00: 2.5 MHz - * - 01: 25 MHz - * - 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - */ -#define ENET_XMII_CSR_LNKSPEED_MASK (0x6U) -#define ENET_XMII_CSR_LNKSPEED_SHIFT (1U) -#define ENET_XMII_CSR_LNKSPEED_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSPEED_SHIFT) & ENET_XMII_CSR_LNKSPEED_MASK) -#define ENET_XMII_CSR_LNKSPEED_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSPEED_MASK) >> ENET_XMII_CSR_LNKSPEED_SHIFT) - -/* - * LNKMOD (RW) - * - * Link Mode - * This bit indicates the current mode of operation of the link: - * - 1’b0: Half-duplex mode - * - 1’b1: Full-duplex mode - */ -#define ENET_XMII_CSR_LNKMOD_MASK (0x1U) -#define ENET_XMII_CSR_LNKMOD_SHIFT (0U) -#define ENET_XMII_CSR_LNKMOD_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKMOD_SHIFT) & ENET_XMII_CSR_LNKMOD_MASK) -#define ENET_XMII_CSR_LNKMOD_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKMOD_MASK) >> ENET_XMII_CSR_LNKMOD_SHIFT) - -/* Bitfield definition for register: WDOG_WTO */ -/* - * PWE (RW) - * - * Programmable Watchdog Enable - * When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. - * When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - */ -#define ENET_WDOG_WTO_PWE_MASK (0x10000UL) -#define ENET_WDOG_WTO_PWE_SHIFT (16U) -#define ENET_WDOG_WTO_PWE_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_PWE_SHIFT) & ENET_WDOG_WTO_PWE_MASK) -#define ENET_WDOG_WTO_PWE_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_PWE_MASK) >> ENET_WDOG_WTO_PWE_SHIFT) - -/* - * WTO (RW) - * - * Watchdog Timeout - * When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * this field is used as watchdog timeout for a received frame. - * If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. - * Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). - * Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - */ -#define ENET_WDOG_WTO_WTO_MASK (0x3FFFU) -#define ENET_WDOG_WTO_WTO_SHIFT (0U) -#define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) -#define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) - -/* Bitfield definition for register: MMC_CNTRL */ -/* - * UCDBC (RW) - * - * Update MMC Counters for Dropped Broadcast Frames - * When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - * When reset, the MMC Counters are not updated for dropped Broadcast frames. - */ -#define ENET_MMC_CNTRL_UCDBC_MASK (0x100U) -#define ENET_MMC_CNTRL_UCDBC_SHIFT (8U) -#define ENET_MMC_CNTRL_UCDBC_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_UCDBC_SHIFT) & ENET_MMC_CNTRL_UCDBC_MASK) -#define ENET_MMC_CNTRL_UCDBC_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_UCDBC_MASK) >> ENET_MMC_CNTRL_UCDBC_SHIFT) - -/* - * CNTPRSTLVL (RW) - * - * Full-Half Preset - * When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - * - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - * - 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - * - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - * - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - */ -#define ENET_MMC_CNTRL_CNTPRSTLVL_MASK (0x20U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT (5U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) -#define ENET_MMC_CNTRL_CNTPRSTLVL_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) >> ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) - -/* - * CNTPRST (RW) - * - * Counters Preset - * When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. - * This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - */ -#define ENET_MMC_CNTRL_CNTPRST_MASK (0x10U) -#define ENET_MMC_CNTRL_CNTPRST_SHIFT (4U) -#define ENET_MMC_CNTRL_CNTPRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRST_SHIFT) & ENET_MMC_CNTRL_CNTPRST_MASK) -#define ENET_MMC_CNTRL_CNTPRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRST_MASK) >> ENET_MMC_CNTRL_CNTPRST_SHIFT) - -/* - * CNTFREEZ (RW) - * - * MMC Counter Freeze - * When this bit is set, it freezes all MMC counters to their current value. - * Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - * If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - */ -#define ENET_MMC_CNTRL_CNTFREEZ_MASK (0x8U) -#define ENET_MMC_CNTRL_CNTFREEZ_SHIFT (3U) -#define ENET_MMC_CNTRL_CNTFREEZ_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTFREEZ_SHIFT) & ENET_MMC_CNTRL_CNTFREEZ_MASK) -#define ENET_MMC_CNTRL_CNTFREEZ_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTFREEZ_MASK) >> ENET_MMC_CNTRL_CNTFREEZ_SHIFT) - -/* - * RSTONRD (RW) - * - * Reset on Read - * When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - */ -#define ENET_MMC_CNTRL_RSTONRD_MASK (0x4U) -#define ENET_MMC_CNTRL_RSTONRD_SHIFT (2U) -#define ENET_MMC_CNTRL_RSTONRD_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_RSTONRD_SHIFT) & ENET_MMC_CNTRL_RSTONRD_MASK) -#define ENET_MMC_CNTRL_RSTONRD_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_RSTONRD_MASK) >> ENET_MMC_CNTRL_RSTONRD_SHIFT) - -/* - * CNTSTOPRO (RW) - * - * Counter Stop Rollover - * When this bit is set, the counter does not roll over to zero after reaching the maximum value. - */ -#define ENET_MMC_CNTRL_CNTSTOPRO_MASK (0x2U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SHIFT (1U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) -#define ENET_MMC_CNTRL_CNTSTOPRO_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) >> ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) - -/* - * CNTRST (RW) - * - * Counters Reset - * When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - */ -#define ENET_MMC_CNTRL_CNTRST_MASK (0x1U) -#define ENET_MMC_CNTRL_CNTRST_SHIFT (0U) -#define ENET_MMC_CNTRL_CNTRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTRST_SHIFT) & ENET_MMC_CNTRL_CNTRST_MASK) -#define ENET_MMC_CNTRL_CNTRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTRST_MASK) >> ENET_MMC_CNTRL_CNTRST_SHIFT) - -/* Bitfield definition for register: MMC_INTR_RX */ -/* - * RXCTRLFIS (RW) - * - * MMC Receive Control Frame Counter Interrupt Status - * This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCTRLFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT (25U) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) -#define ENET_MMC_INTR_RX_RXCTRLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) >> ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) - -/* - * RXRCVERRFIS (RW) - * - * MMC Receive Error Frame Counter Interrupt Status - * This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRCVERRFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT (24U) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) >> ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) - -/* - * RXWDOGFIS (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Status - * This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXWDOGFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT (23U) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) -#define ENET_MMC_INTR_RX_RXWDOGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) >> ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) - -/* - * RXVLANGBFIS (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Status - * This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXVLANGBFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT (22U) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) >> ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) - -/* - * RXFOVFIS (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Status - * This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXFOVFIS_MASK (0x200000UL) -#define ENET_MMC_INTR_RX_RXFOVFIS_SHIFT (21U) -#define ENET_MMC_INTR_RX_RXFOVFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) -#define ENET_MMC_INTR_RX_RXFOVFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) >> ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) - -/* - * RXPAUSFIS (RW) - * - * MMC Receive Pause Frame Counter Interrupt Status - * This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXPAUSFIS_MASK (0x100000UL) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT (20U) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) -#define ENET_MMC_INTR_RX_RXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) >> ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) - -/* - * RXORANGEFIS (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Status. - * This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXORANGEFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT (19U) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) -#define ENET_MMC_INTR_RX_RXORANGEFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) >> ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) - -/* - * RXLENERFIS (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Status - * This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXLENERFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_RX_RXLENERFIS_SHIFT (18U) -#define ENET_MMC_INTR_RX_RXLENERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) -#define ENET_MMC_INTR_RX_RXLENERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) >> ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) - -/* - * RXUCGFIS (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Status - * This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUCGFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_RX_RXUCGFIS_SHIFT (17U) -#define ENET_MMC_INTR_RX_RXUCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) >> ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) - -/* - * RX1024TMAXOCTGBFIS (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. - * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT (16U) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) - -/* - * RX512T1023OCTGBFIS (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK (0x8000U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT (15U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) - -/* - * RX256T511OCTGBFIS (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK (0x4000U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT (14U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) - -/* - * RX128T255OCTGBFIS (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK (0x2000U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT (13U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) - -/* - * RX65T127OCTGBFIS (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) - -/* - * RX64OCTGBFIS (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) - -/* - * RXOSIZEGFIS (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Status - * This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK (0x400U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT (10U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) - -/* - * RXUSIZEGFIS (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Status - * This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK (0x200U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT (9U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) - -/* - * RXJABERFIS (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Status - * This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXJABERFIS_MASK (0x100U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SHIFT (8U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) -#define ENET_MMC_INTR_RX_RXJABERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) >> ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) - -/* - * RXRUNTFIS (RW) - * - * MMC Receive Runt Frame Counter Interrupt Status - * This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRUNTFIS_MASK (0x80U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT (7U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) -#define ENET_MMC_INTR_RX_RXRUNTFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) >> ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) - -/* - * RXALGNERFIS (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Status - * This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXALGNERFIS_MASK (0x40U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT (6U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) -#define ENET_MMC_INTR_RX_RXALGNERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) >> ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) - -/* - * RXCRCERFIS (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Status - * This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCRCERFIS_MASK (0x20U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT (5U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) -#define ENET_MMC_INTR_RX_RXCRCERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) >> ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) - -/* - * RXMCGFIS (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Status - * This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXMCGFIS_MASK (0x10U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SHIFT (4U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) >> ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) - -/* - * RXBCGFIS (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Status - * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXBCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) >> ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) - -/* - * RXGOCTIS (RW) - * - * MMC Receive Good Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGOCTIS_MASK (0x4U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SHIFT (2U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) - -/* - * RXGBOCTIS (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBOCTIS_MASK (0x2U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT (1U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) - -/* - * RXGBFRMIS (RW) - * - * MMC Receive Good Bad Frame Counter Interrupt Status - * This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBFRMIS_MASK (0x1U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT (0U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) -#define ENET_MMC_INTR_RX_RXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) >> ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_TX */ -/* - * TXOSIZEGFIS (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Status - * This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT (25U) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) >> ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) - -/* - * TXVLANGFIS (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Status - * This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXVLANGFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT (24U) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) -#define ENET_MMC_INTR_TX_TXVLANGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) >> ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) - -/* - * TXPAUSFIS (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Status - * This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXPAUSFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT (23U) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) -#define ENET_MMC_INTR_TX_TXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) >> ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) - -/* - * TXEXDEFFIS (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Status - * This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXDEFFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT (22U) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) - -/* - * TXGFRMIS (RW) - * - * MMC Transmit Good Frame Counter Interrupt Status - * This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGFRMIS_MASK (0x200000UL) -#define ENET_MMC_INTR_TX_TXGFRMIS_SHIFT (21U) -#define ENET_MMC_INTR_TX_TXGFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) - -/* - * TXGOCTIS (RW) - * - * MMC Transmit Good Octet Counter Interrupt Status - * This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGOCTIS_MASK (0x100000UL) -#define ENET_MMC_INTR_TX_TXGOCTIS_SHIFT (20U) -#define ENET_MMC_INTR_TX_TXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) - -/* - * TXCARERFIS (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Status - * This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXCARERFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_TX_TXCARERFIS_SHIFT (19U) -#define ENET_MMC_INTR_TX_TXCARERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) -#define ENET_MMC_INTR_TX_TXCARERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) >> ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) - -/* - * TXEXCOLFIS (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Status - * This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXCOLFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT (18U) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) - -/* - * TXLATCOLFIS (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Status - * This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXLATCOLFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT (17U) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) - -/* - * TXDEFFIS (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Status - * This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXDEFFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_TX_TXDEFFIS_SHIFT (16U) -#define ENET_MMC_INTR_TX_TXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) - -/* - * TXMCOLGFIS (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - * This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCOLGFIS_MASK (0x8000U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT (15U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) - -/* - * TXSCOLGFIS (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Status - * This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXSCOLGFIS_MASK (0x4000U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT (14U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) - -/* - * TXUFLOWERFIS (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Status - * This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK (0x2000U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT (13U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) >> ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) - -/* - * TXBCGBFIS (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) - -/* - * TXMCGBFIS (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - * The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) - -/* - * TXUCGBFIS (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - * This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUCGBFIS_MASK (0x400U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT (10U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXUCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) - -/* - * TX1024TMAXOCTGBFIS (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK (0x200U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT (9U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) - -/* - * TX512T1023OCTGBFIS (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK (0x100U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT (8U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) - -/* - * TX256T511OCTGBFIS (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK (0x80U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT (7U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) - -/* - * TX128T255OCTGBFIS (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK (0x40U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT (6U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) - -/* - * TX65T127OCTGBFIS (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - */ -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK (0x20U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT (5U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) - -/* - * TX64OCTGBFIS (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK (0x10U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT (4U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) - -/* - * TXMCGFIS (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Status - * This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) - -/* - * TXBCGFIS (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGFIS_MASK (0x4U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SHIFT (2U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) - -/* - * TXGBFRMIS (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Status - * This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBFRMIS_MASK (0x2U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT (1U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) - -/* - * TXGBOCTIS (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Status - * This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBOCTIS_MASK (0x1U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT (0U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_RX */ -/* - * RXCTRLFIM (RW) - * - * MMC Receive Control Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) - -/* - * RXRCVERRFIM (RW) - * - * MMC Receive Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) - -/* - * RXWDOGFIM (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) - -/* - * RXVLANGBFIM (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) - -/* - * RXFOVFIM (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) - -/* - * RXPAUSFIM (RW) - * - * MMC Receive Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) - -/* - * RXORANGEFIM (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) - -/* - * RXLENERFIM (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) - -/* - * RXUCGFIM (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) - -/* - * RX1024TMAXOCTGBFIM (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) - -/* - * RX512T1023OCTGBFIM (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) - -/* - * RX256T511OCTGBFIM (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) - -/* - * RX128T255OCTGBFIM (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) - -/* - * RX65T127OCTGBFIM (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) - -/* - * RX64OCTGBFIM (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) - -/* - * RXOSIZEGFIM (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) - -/* - * RXUSIZEGFIM (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) - -/* - * RXJABERFIM (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) - -/* - * RXRUNTFIM (RW) - * - * MMC Receive Runt Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) - -/* - * RXALGNERFIM (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) - -/* - * RXCRCERFIM (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) - -/* - * RXMCGFIM (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) - -/* - * RXBCGFIM (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) - -/* - * RXGOCTIM (RW) - * - * MMC Receive Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) - -/* - * RXGBOCTIM (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_TX */ -/* - * TXOSIZEGFIM (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) - -/* - * TXVLANGFIM (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) - -/* - * TXPAUSFIM (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) - -/* - * TXEXDEFFIM (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) - -/* - * TXGFRMIM (RW) - * - * MMC Transmit Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) - -/* - * TXGOCTIM (RW) - * - * MMC Transmit Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) - -/* - * TXCARERFIM (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) - -/* - * TXEXCOLFIM (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) - -/* - * TXLATCOLFIM (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) - -/* - * TXDEFFIM (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) - -/* - * TXMCOLGFIM (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) - -/* - * TXSCOLGFIM (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) - -/* - * TXUFLOWERFIM (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) - -/* - * TXBCGBFIM (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) - -/* - * TXMCGBFIM (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) - -/* - * TXUCGBFIM (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) - -/* - * TX1024TMAXOCTGBFIM (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) - -/* - * TX512T1023OCTGBFIM (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) - -/* - * TX256T511OCTGBFIM (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) - -/* - * TX128T255OCTGBFIM (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) - -/* - * TX65T127OCTGBFIM (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) - -/* - * TX64OCTGBFIM (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) - -/* - * TXMCGFIM (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) - -/* - * TXBCGFIM (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) - -/* - * TXGBFRMIM (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) - -/* - * TXGBOCTIM (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK (0x1U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT (0U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) - -/* Bitfield definition for register: TX64OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX64OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX64OCTETS_GB_FRMCNT_SHIFT) & ENET_TX64OCTETS_GB_FRMCNT_MASK) -#define ENET_TX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX64OCTETS_GB_FRMCNT_MASK) >> ENET_TX64OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX65TO127OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX128TO255OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX256TO511OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX512TO1023OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX1024TOMAXOCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFRAMECOUNT_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received. - */ -#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ -/* - * RXICMPEROIM (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT (29U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) - -/* - * RXICMPGOIM (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT (28U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) - -/* - * RXTCPEROIM (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT (27U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) - -/* - * RXTCPGOIM (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT (26U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) - -/* - * RXUDPEROIM (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT (25U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) - -/* - * RXUDPGOIM (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT (24U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) - -/* - * RXIPV6NOPAYOIM (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT (23U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) - -/* - * RXIPV6HEROIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT (22U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) - -/* - * RXIPV6GOIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT (21U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) - -/* - * RXIPV4UDSBLOIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT (20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) - -/* - * RXIPV4FRAGOIM (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT (19U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) - -/* - * RXIPV4NOPAYOIM (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT (18U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) - -/* - * RXIPV4HEROIM (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT (17U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) - -/* - * RXIPV4GOIM (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT (16U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) - -/* - * RXICMPERFIM (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT (13U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) - -/* - * RXICMPGFIM (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT (12U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) - -/* - * RXTCPERFIM (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK (0x800U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT (11U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) - -/* - * RXTCPGFIM (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK (0x400U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT (10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) - -/* - * RXUDPERFIM (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK (0x200U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT (9U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) - -/* - * RXUDPGFIM (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK (0x100U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT (8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) - -/* - * RXIPV6NOPAYFIM (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK (0x80U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT (7U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) - -/* - * RXIPV6HERFIM (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK (0x40U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT (6U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) - -/* - * RXIPV6GFIM (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK (0x20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT (5U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) - -/* - * RXIPV4UDSBLFIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK (0x10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT (4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) - -/* - * RXIPV4FRAGFIM (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK (0x8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT (3U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) - -/* - * RXIPV4NOPAYFIM (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK (0x4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT (2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) - -/* - * RXIPV4HERFIM (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK (0x2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT (1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) - -/* - * RXIPV4GFIM (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK (0x1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT (0U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_RX */ -/* - * RXICMPEROIS (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Status - * This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT (29U) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) - -/* - * RXICMPGOIS (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Status - * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT (28U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) - -/* - * RXTCPEROIS (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Status - * This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT (27U) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) - -/* - * RXTCPGOIS (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Status - * This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT (26U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) - -/* - * RXUDPEROIS (RW) - * - * MMC Receive UDP Error Octet Counter Interrupt Status - * This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT (25U) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) - -/* - * RXUDPGOIS (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Status - * This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT (24U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) - -/* - * RXIPV6NOPAYOIS (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT (23U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) - -/* - * RXIPV6HEROIS (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT (22U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) - -/* - * RXIPV6GOIS (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Status - * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT (21U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) - -/* - * RXIPV4UDSBLOIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT (20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) - -/* - * RXIPV4FRAGOIS (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT (19U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) - -/* - * RXIPV4NOPAYOIS (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT (18U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) - -/* - * RXIPV4HEROIS (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT (17U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) - -/* - * RXIPV4GOIS (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Status - * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT (16U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) - -/* - * RXICMPERFIS (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Status - * This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT (13U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) - -/* - * RXICMPGFIS (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Status - * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT (12U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) - -/* - * RXTCPERFIS (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Status - * This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK (0x800U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT (11U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) - -/* - * RXTCPGFIS (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Status - * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK (0x400U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT (10U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) - -/* - * RXUDPERFIS (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Status - * This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK (0x200U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT (9U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) - -/* - * RXUDPGFIS (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Status - * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK (0x100U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT (8U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) - -/* - * RXIPV6NOPAYFIS (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK (0x80U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT (7U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) - -/* - * RXIPV6HERFIS (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK (0x40U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT (6U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) - -/* - * RXIPV6GFIS (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Status - * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK (0x20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT (5U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) - -/* - * RXIPV4UDSBLFIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK (0x10U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT (4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) - -/* - * RXIPV4FRAGFIS (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK (0x8U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT (3U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) - -/* - * RXIPV4NOPAYFIS (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK (0x4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT (2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) - -/* - * RXIPV4HERFIS (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK (0x2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT (1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) - -/* - * RXIPV4GFIS (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Status - * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK (0x1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT (0U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) - -/* Bitfield definition for register: RXIPV4_GD_FMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - */ -#define ENET_RXIPV4_GD_FMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) -#define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ -/* - * L4DPIM0 (RW) - * - * Layer 4 Destination Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK (0x200000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT (21U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) - -/* - * L4DPM0 (RW) - * - * Layer 4 Destination Port Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. - * When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK (0x100000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT (20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) - -/* - * L4SPIM0 (RW) - * - * Layer 4 Source Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK (0x80000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT (19U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) - -/* - * L4SPM0 (RW) - * - * Layer 4 Source Port Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK (0x40000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT (18U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) - -/* - * L4PEN0 (RW) - * - * Layer 4 Protocol Enable - * When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. - * When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. - * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK (0x10000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT (16U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) - -/* - * L3HDBM0 (RW) - * - * Layer 3 IP DA Higher Bits Match - * IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, - * which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. - * The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - … - * - 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK (0xF800U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT (11U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) - -/* - * L3HSBM0 (RW) - * - * Layer 3 IP SA Higher Bits Match - * IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. - * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK (0x7C0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT (6U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) - -/* - * L3DAIM0 (RW) - * - * Layer 3 IP DA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK (0x20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT (5U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) - -/* - * L3DAM0 (RW) - * - * Layer 3 IP DA Match Enable - * When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. - * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK (0x10U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT (4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) - -/* - * L3SAIM0 (RW) - * - * Layer 3 IP SA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK (0x8U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT (3U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) - -/* - * L3SAM0 (RW) - * - * Layer 3 IP SA Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK (0x4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT (2U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) - -/* - * L3PEN0 (RW) - * - * Layer 3 Protocol Enable - * When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. - * When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. - * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK (0x1U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L4_ADDR */ -/* - * L4DP0 (RW) - * - * Layer 4 Destination Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK (0xFFFF0000UL) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT (16U) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) - -/* - * L4SP0 (RW) - * - * Layer 4 Source Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK (0xFFFFU) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT (0U) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_0 */ -/* - * L3A00 (RW) - * - * Layer 3 Address 0 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) >> ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_1 */ -/* - * L3A10 (RW) - * - * Layer 3 Address 1 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) >> ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_2 */ -/* - * L3A20 (RW) - * - * Layer 3 Address 2 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) >> ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_3 */ -/* - * L3A30 (RW) - * - * Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) - -/* Bitfield definition for register: VLAN_TAG_INC_RPL */ -/* - * CSVL (RW) - * - * C-VLAN or S-VLAN - * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - */ -#define ENET_VLAN_TAG_INC_RPL_CSVL_MASK (0x80000UL) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT (19U) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) -#define ENET_VLAN_TAG_INC_RPL_CSVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) >> ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) - -/* - * VLP (RW) - * - * VLAN Priority Control - * When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - */ -#define ENET_VLAN_TAG_INC_RPL_VLP_MASK (0x40000UL) -#define ENET_VLAN_TAG_INC_RPL_VLP_SHIFT (18U) -#define ENET_VLAN_TAG_INC_RPL_VLP_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLP_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) >> ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) - -/* - * VLC (RW) - * - * VLAN Tag Control in Transmit Frames - * - 2’b00: No VLAN tag deletion, insertion, or replacement - * - 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. - * - 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. - * This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. - * - 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). - * Note: Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - */ -#define ENET_VLAN_TAG_INC_RPL_VLC_MASK (0x30000UL) -#define ENET_VLAN_TAG_INC_RPL_VLC_SHIFT (16U) -#define ENET_VLAN_TAG_INC_RPL_VLC_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLC_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) >> ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) - -/* - * VLT (RW) - * - * VLAN Tag for Transmit Frames - * This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - * Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - */ -#define ENET_VLAN_TAG_INC_RPL_VLT_MASK (0xFFFFU) -#define ENET_VLAN_TAG_INC_RPL_VLT_SHIFT (0U) -#define ENET_VLAN_TAG_INC_RPL_VLT_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLT_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) >> ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) - -/* Bitfield definition for register: VLAN_HASH */ -/* - * VLHT (RW) - * - * VLAN Hash Table - * This field contains the 16-bit VLAN Hash Table. - */ -#define ENET_VLAN_HASH_VLHT_MASK (0xFFFFU) -#define ENET_VLAN_HASH_VLHT_SHIFT (0U) -#define ENET_VLAN_HASH_VLHT_SET(x) (((uint32_t)(x) << ENET_VLAN_HASH_VLHT_SHIFT) & ENET_VLAN_HASH_VLHT_MASK) -#define ENET_VLAN_HASH_VLHT_GET(x) (((uint32_t)(x) & ENET_VLAN_HASH_VLHT_MASK) >> ENET_VLAN_HASH_VLHT_SHIFT) - -/* Bitfield definition for register: TS_CTRL */ -/* - * ATSEN3 (RW) - * - * Auxiliary Snapshot 3 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - */ -#define ENET_TS_CTRL_ATSEN3_MASK (0x10000000UL) -#define ENET_TS_CTRL_ATSEN3_SHIFT (28U) -#define ENET_TS_CTRL_ATSEN3_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN3_SHIFT) & ENET_TS_CTRL_ATSEN3_MASK) -#define ENET_TS_CTRL_ATSEN3_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN3_MASK) >> ENET_TS_CTRL_ATSEN3_SHIFT) - -/* - * ATSEN2 (RW) - * - * Auxiliary Snapshot 2 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - */ -#define ENET_TS_CTRL_ATSEN2_MASK (0x8000000UL) -#define ENET_TS_CTRL_ATSEN2_SHIFT (27U) -#define ENET_TS_CTRL_ATSEN2_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN2_SHIFT) & ENET_TS_CTRL_ATSEN2_MASK) -#define ENET_TS_CTRL_ATSEN2_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN2_MASK) >> ENET_TS_CTRL_ATSEN2_SHIFT) - -/* - * ATSEN1 (RW) - * - * Auxiliary Snapshot 1 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - */ -#define ENET_TS_CTRL_ATSEN1_MASK (0x4000000UL) -#define ENET_TS_CTRL_ATSEN1_SHIFT (26U) -#define ENET_TS_CTRL_ATSEN1_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN1_SHIFT) & ENET_TS_CTRL_ATSEN1_MASK) -#define ENET_TS_CTRL_ATSEN1_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN1_MASK) >> ENET_TS_CTRL_ATSEN1_SHIFT) - -/* - * ATSEN0 (RW) - * - * Auxiliary Snapshot 0 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - */ -#define ENET_TS_CTRL_ATSEN0_MASK (0x2000000UL) -#define ENET_TS_CTRL_ATSEN0_SHIFT (25U) -#define ENET_TS_CTRL_ATSEN0_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN0_SHIFT) & ENET_TS_CTRL_ATSEN0_MASK) -#define ENET_TS_CTRL_ATSEN0_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN0_MASK) >> ENET_TS_CTRL_ATSEN0_SHIFT) - -/* - * ATSFC (RW) - * - * Auxiliary Snapshot FIFO Clear - * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - */ -#define ENET_TS_CTRL_ATSFC_MASK (0x1000000UL) -#define ENET_TS_CTRL_ATSFC_SHIFT (24U) -#define ENET_TS_CTRL_ATSFC_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSFC_SHIFT) & ENET_TS_CTRL_ATSFC_MASK) -#define ENET_TS_CTRL_ATSFC_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSFC_MASK) >> ENET_TS_CTRL_ATSFC_SHIFT) - -/* - * TSENMACADDR (RW) - * - * Enable MAC address for PTP Frame Filtering - * When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - */ -#define ENET_TS_CTRL_TSENMACADDR_MASK (0x40000UL) -#define ENET_TS_CTRL_TSENMACADDR_SHIFT (18U) -#define ENET_TS_CTRL_TSENMACADDR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENMACADDR_SHIFT) & ENET_TS_CTRL_TSENMACADDR_MASK) -#define ENET_TS_CTRL_TSENMACADDR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENMACADDR_MASK) >> ENET_TS_CTRL_TSENMACADDR_SHIFT) - -/* - * SNAPTYPSEL (RW) - * - * Select PTP packets for Taking Snapshots - * These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - */ -#define ENET_TS_CTRL_SNAPTYPSEL_MASK (0x30000UL) -#define ENET_TS_CTRL_SNAPTYPSEL_SHIFT (16U) -#define ENET_TS_CTRL_SNAPTYPSEL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_SNAPTYPSEL_SHIFT) & ENET_TS_CTRL_SNAPTYPSEL_MASK) -#define ENET_TS_CTRL_SNAPTYPSEL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_SNAPTYPSEL_MASK) >> ENET_TS_CTRL_SNAPTYPSEL_SHIFT) - -/* - * TSMSTRENA (RW) - * - * Enable Snapshot for Messages Relevant to Master - * When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - */ -#define ENET_TS_CTRL_TSMSTRENA_MASK (0x8000U) -#define ENET_TS_CTRL_TSMSTRENA_SHIFT (15U) -#define ENET_TS_CTRL_TSMSTRENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSMSTRENA_SHIFT) & ENET_TS_CTRL_TSMSTRENA_MASK) -#define ENET_TS_CTRL_TSMSTRENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSMSTRENA_MASK) >> ENET_TS_CTRL_TSMSTRENA_SHIFT) - -/* - * TSEVNTENA (RW) - * - * Enable Timestamp Snapshot for Event Messages - * When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - */ -#define ENET_TS_CTRL_TSEVNTENA_MASK (0x4000U) -#define ENET_TS_CTRL_TSEVNTENA_SHIFT (14U) -#define ENET_TS_CTRL_TSEVNTENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSEVNTENA_SHIFT) & ENET_TS_CTRL_TSEVNTENA_MASK) -#define ENET_TS_CTRL_TSEVNTENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSEVNTENA_MASK) >> ENET_TS_CTRL_TSEVNTENA_SHIFT) - -/* - * TSIPV4ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv4-UDP - * When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - */ -#define ENET_TS_CTRL_TSIPV4ENA_MASK (0x2000U) -#define ENET_TS_CTRL_TSIPV4ENA_SHIFT (13U) -#define ENET_TS_CTRL_TSIPV4ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV4ENA_SHIFT) & ENET_TS_CTRL_TSIPV4ENA_MASK) -#define ENET_TS_CTRL_TSIPV4ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV4ENA_MASK) >> ENET_TS_CTRL_TSIPV4ENA_SHIFT) - -/* - * TSIPV6ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv6-UDP - * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - */ -#define ENET_TS_CTRL_TSIPV6ENA_MASK (0x1000U) -#define ENET_TS_CTRL_TSIPV6ENA_SHIFT (12U) -#define ENET_TS_CTRL_TSIPV6ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV6ENA_SHIFT) & ENET_TS_CTRL_TSIPV6ENA_MASK) -#define ENET_TS_CTRL_TSIPV6ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV6ENA_MASK) >> ENET_TS_CTRL_TSIPV6ENA_SHIFT) - -/* - * TSIPENA (RW) - * - * Enable Processing of PTP over Ethernet Frames - * When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - */ -#define ENET_TS_CTRL_TSIPENA_MASK (0x800U) -#define ENET_TS_CTRL_TSIPENA_SHIFT (11U) -#define ENET_TS_CTRL_TSIPENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPENA_SHIFT) & ENET_TS_CTRL_TSIPENA_MASK) -#define ENET_TS_CTRL_TSIPENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPENA_MASK) >> ENET_TS_CTRL_TSIPENA_SHIFT) - -/* - * TSVER2ENA (RW) - * - * Enable PTP packet Processing for Version 2 Format - * When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - */ -#define ENET_TS_CTRL_TSVER2ENA_MASK (0x400U) -#define ENET_TS_CTRL_TSVER2ENA_SHIFT (10U) -#define ENET_TS_CTRL_TSVER2ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSVER2ENA_SHIFT) & ENET_TS_CTRL_TSVER2ENA_MASK) -#define ENET_TS_CTRL_TSVER2ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSVER2ENA_MASK) >> ENET_TS_CTRL_TSVER2ENA_SHIFT) - -/* - * TSCTRLSSR (RW) - * - * Timestamp Digital or Binary Rollover Control - * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - * When reset, the rollover value of sub-second register is 0x7FFF_FFFF. - * The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - */ -#define ENET_TS_CTRL_TSCTRLSSR_MASK (0x200U) -#define ENET_TS_CTRL_TSCTRLSSR_SHIFT (9U) -#define ENET_TS_CTRL_TSCTRLSSR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCTRLSSR_SHIFT) & ENET_TS_CTRL_TSCTRLSSR_MASK) -#define ENET_TS_CTRL_TSCTRLSSR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCTRLSSR_MASK) >> ENET_TS_CTRL_TSCTRLSSR_SHIFT) - -/* - * TSENALL (RW) - * - * Enable Timestamp for All Frames - * When set, the timestamp snapshot is enabled for all frames received by the MAC. - */ -#define ENET_TS_CTRL_TSENALL_MASK (0x100U) -#define ENET_TS_CTRL_TSENALL_SHIFT (8U) -#define ENET_TS_CTRL_TSENALL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENALL_SHIFT) & ENET_TS_CTRL_TSENALL_MASK) -#define ENET_TS_CTRL_TSENALL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENALL_MASK) >> ENET_TS_CTRL_TSENALL_SHIFT) - -/* - * TSADDREG (RW) - * - * Addend Reg Update - * When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. - * This register bit should be zero before setting it. - */ -#define ENET_TS_CTRL_TSADDREG_MASK (0x20U) -#define ENET_TS_CTRL_TSADDREG_SHIFT (5U) -#define ENET_TS_CTRL_TSADDREG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSADDREG_SHIFT) & ENET_TS_CTRL_TSADDREG_MASK) -#define ENET_TS_CTRL_TSADDREG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSADDREG_MASK) >> ENET_TS_CTRL_TSADDREG_SHIFT) - -/* - * TSTRIG (RW) - * - * Timestamp Interrupt Trigger Enable - * When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. - * This bit is reset after the generation of the Timestamp Trigger Interrupt. - */ -#define ENET_TS_CTRL_TSTRIG_MASK (0x10U) -#define ENET_TS_CTRL_TSTRIG_SHIFT (4U) -#define ENET_TS_CTRL_TSTRIG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSTRIG_SHIFT) & ENET_TS_CTRL_TSTRIG_MASK) -#define ENET_TS_CTRL_TSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSTRIG_MASK) >> ENET_TS_CTRL_TSTRIG_SHIFT) - -/* - * TSUPDT (RW) - * - * Timestamp Update - * When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - */ -#define ENET_TS_CTRL_TSUPDT_MASK (0x8U) -#define ENET_TS_CTRL_TSUPDT_SHIFT (3U) -#define ENET_TS_CTRL_TSUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSUPDT_SHIFT) & ENET_TS_CTRL_TSUPDT_MASK) -#define ENET_TS_CTRL_TSUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSUPDT_MASK) >> ENET_TS_CTRL_TSUPDT_SHIFT) - -/* - * TSINIT (RW) - * - * Timestamp Initialize - * When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the initialization is complete. - * The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - */ -#define ENET_TS_CTRL_TSINIT_MASK (0x4U) -#define ENET_TS_CTRL_TSINIT_SHIFT (2U) -#define ENET_TS_CTRL_TSINIT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSINIT_SHIFT) & ENET_TS_CTRL_TSINIT_MASK) -#define ENET_TS_CTRL_TSINIT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSINIT_MASK) >> ENET_TS_CTRL_TSINIT_SHIFT) - -/* - * TSCFUPDT (RW) - * - * Timestamp Fine or Coarse Update - * When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - */ -#define ENET_TS_CTRL_TSCFUPDT_MASK (0x2U) -#define ENET_TS_CTRL_TSCFUPDT_SHIFT (1U) -#define ENET_TS_CTRL_TSCFUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCFUPDT_SHIFT) & ENET_TS_CTRL_TSCFUPDT_MASK) -#define ENET_TS_CTRL_TSCFUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCFUPDT_MASK) >> ENET_TS_CTRL_TSCFUPDT_SHIFT) - -/* - * TSENA (RW) - * - * Timestamp Enable - * When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. - * You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - */ -#define ENET_TS_CTRL_TSENA_MASK (0x1U) -#define ENET_TS_CTRL_TSENA_SHIFT (0U) -#define ENET_TS_CTRL_TSENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENA_SHIFT) & ENET_TS_CTRL_TSENA_MASK) -#define ENET_TS_CTRL_TSENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENA_MASK) >> ENET_TS_CTRL_TSENA_SHIFT) - -/* Bitfield definition for register: SUB_SEC_INCR */ -/* - * SSINC (RW) - * - * Sub-second Increment Value - * The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. - * For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) - * when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. - * When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. - * In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - */ -#define ENET_SUB_SEC_INCR_SSINC_MASK (0xFFU) -#define ENET_SUB_SEC_INCR_SSINC_SHIFT (0U) -#define ENET_SUB_SEC_INCR_SSINC_SET(x) (((uint32_t)(x) << ENET_SUB_SEC_INCR_SSINC_SHIFT) & ENET_SUB_SEC_INCR_SSINC_MASK) -#define ENET_SUB_SEC_INCR_SSINC_GET(x) (((uint32_t)(x) & ENET_SUB_SEC_INCR_SSINC_MASK) >> ENET_SUB_SEC_INCR_SSINC_SHIFT) - -/* Bitfield definition for register: SYST_SEC */ -/* - * TSS (RO) - * - * Timestamp Second - * The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - */ -#define ENET_SYST_SEC_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_TSS_SHIFT (0U) -#define ENET_SYST_SEC_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_TSS_MASK) >> ENET_SYST_SEC_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC */ -/* - * TSSS (RO) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - */ -#define ENET_SYST_NSEC_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_TSSS_MASK) >> ENET_SYST_NSEC_TSSS_SHIFT) - -/* Bitfield definition for register: SYST_SEC_UPD */ -/* - * TSS (RW) - * - * Timestamp Second - * The value in this field indicates the time in seconds to be initialized or added to the system time. - */ -#define ENET_SYST_SEC_UPD_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_UPD_TSS_SHIFT (0U) -#define ENET_SYST_SEC_UPD_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_UPD_TSS_SHIFT) & ENET_SYST_SEC_UPD_TSS_MASK) -#define ENET_SYST_SEC_UPD_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_UPD_TSS_MASK) >> ENET_SYST_SEC_UPD_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC_UPD */ -/* - * ADDSUB (RW) - * - * Add or Subtract Time - * When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - */ -#define ENET_SYST_NSEC_UPD_ADDSUB_MASK (0x80000000UL) -#define ENET_SYST_NSEC_UPD_ADDSUB_SHIFT (31U) -#define ENET_SYST_NSEC_UPD_ADDSUB_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) -#define ENET_SYST_NSEC_UPD_ADDSUB_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) >> ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) - -/* - * TSSS (RW) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - */ -#define ENET_SYST_NSEC_UPD_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_UPD_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_UPD_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_TSSS_SHIFT) & ENET_SYST_NSEC_UPD_TSSS_MASK) -#define ENET_SYST_NSEC_UPD_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_TSSS_MASK) >> ENET_SYST_NSEC_UPD_TSSS_SHIFT) - -/* Bitfield definition for register: TS_ADDEND */ -/* - * TSAR (RW) - * - * Timestamp Addend Register - * This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - */ -#define ENET_TS_ADDEND_TSAR_MASK (0xFFFFFFFFUL) -#define ENET_TS_ADDEND_TSAR_SHIFT (0U) -#define ENET_TS_ADDEND_TSAR_SET(x) (((uint32_t)(x) << ENET_TS_ADDEND_TSAR_SHIFT) & ENET_TS_ADDEND_TSAR_MASK) -#define ENET_TS_ADDEND_TSAR_GET(x) (((uint32_t)(x) & ENET_TS_ADDEND_TSAR_MASK) >> ENET_TS_ADDEND_TSAR_SHIFT) - -/* Bitfield definition for register: TGTTM_SEC */ -/* - * TSTR (RW) - * - * Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_TGTTM_SEC_TSTR_MASK (0xFFFFFFFFUL) -#define ENET_TGTTM_SEC_TSTR_SHIFT (0U) -#define ENET_TGTTM_SEC_TSTR_SET(x) (((uint32_t)(x) << ENET_TGTTM_SEC_TSTR_SHIFT) & ENET_TGTTM_SEC_TSTR_MASK) -#define ENET_TGTTM_SEC_TSTR_GET(x) (((uint32_t)(x) & ENET_TGTTM_SEC_TSTR_MASK) >> ENET_TGTTM_SEC_TSTR_SHIFT) - -/* Bitfield definition for register: TGTTM_NSEC */ -/* - * TRGTBUSY (RW) - * - * Target Time Register Busy - * The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Target Time Registers when this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - */ -#define ENET_TGTTM_NSEC_TRGTBUSY_MASK (0x80000000UL) -#define ENET_TGTTM_NSEC_TRGTBUSY_SHIFT (31U) -#define ENET_TGTTM_NSEC_TRGTBUSY_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) -#define ENET_TGTTM_NSEC_TRGTBUSY_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) >> ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) - -/* - * TTSLO (RW) - * - * Target Timestamp Low Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_TGTTM_NSEC_TTSLO_MASK (0x7FFFFFFFUL) -#define ENET_TGTTM_NSEC_TTSLO_SHIFT (0U) -#define ENET_TGTTM_NSEC_TTSLO_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TTSLO_SHIFT) & ENET_TGTTM_NSEC_TTSLO_MASK) -#define ENET_TGTTM_NSEC_TTSLO_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TTSLO_MASK) >> ENET_TGTTM_NSEC_TTSLO_SHIFT) - -/* Bitfield definition for register: SYSTM_H_SEC */ -/* - * TSHWR (RW) - * - * Timestamp Higher Word Register - * This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. - * The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - */ -#define ENET_SYSTM_H_SEC_TSHWR_MASK (0xFFFFU) -#define ENET_SYSTM_H_SEC_TSHWR_SHIFT (0U) -#define ENET_SYSTM_H_SEC_TSHWR_SET(x) (((uint32_t)(x) << ENET_SYSTM_H_SEC_TSHWR_SHIFT) & ENET_SYSTM_H_SEC_TSHWR_MASK) -#define ENET_SYSTM_H_SEC_TSHWR_GET(x) (((uint32_t)(x) & ENET_SYSTM_H_SEC_TSHWR_MASK) >> ENET_SYSTM_H_SEC_TSHWR_SHIFT) - -/* Bitfield definition for register: TS_STATUS */ -/* - * ATSNS (RO) - * - * Number of Auxiliary Timestamp Snapshots - * This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. - * These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. - * This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSNS_MASK (0x3E000000UL) -#define ENET_TS_STATUS_ATSNS_SHIFT (25U) -#define ENET_TS_STATUS_ATSNS_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSNS_MASK) >> ENET_TS_STATUS_ATSNS_SHIFT) - -/* - * ATSSTM (RO) - * - * Auxiliary Timestamp Snapshot Trigger Missed - * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. - * This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSSTM_MASK (0x1000000UL) -#define ENET_TS_STATUS_ATSSTM_SHIFT (24U) -#define ENET_TS_STATUS_ATSSTM_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTM_MASK) >> ENET_TS_STATUS_ATSSTM_SHIFT) - -/* - * ATSSTN (RO) - * - * Auxiliary Timestamp Snapshot Trigger Identifier - * These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. - * When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. - * These bits are applicable only if the number of Auxiliary snapshots is more than one. - * One bit is assigned for each trigger as shown in the following list: - * - Bit 16: Auxiliary trigger 0 - * - Bit 17: Auxiliary trigger 1 - * - Bit 18: Auxiliary trigger 2 - * - Bit 19: Auxiliary trigger 3 - * The software can read this register to find the triggers that are set when the timestamp is taken. - */ -#define ENET_TS_STATUS_ATSSTN_MASK (0xF0000UL) -#define ENET_TS_STATUS_ATSSTN_SHIFT (16U) -#define ENET_TS_STATUS_ATSSTN_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTN_MASK) >> ENET_TS_STATUS_ATSSTN_SHIFT) - -/* - * TSTRGTERR3 (RO) - * - * Timestamp Target Time Error - * This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - */ -#define ENET_TS_STATUS_TSTRGTERR3_MASK (0x200U) -#define ENET_TS_STATUS_TSTRGTERR3_SHIFT (9U) -#define ENET_TS_STATUS_TSTRGTERR3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR3_MASK) >> ENET_TS_STATUS_TSTRGTERR3_SHIFT) - -/* - * TSTARGT3 (RO) - * - * Timestamp Target Time Reached for Target Time PPS3 - * When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - */ -#define ENET_TS_STATUS_TSTARGT3_MASK (0x100U) -#define ENET_TS_STATUS_TSTARGT3_SHIFT (8U) -#define ENET_TS_STATUS_TSTARGT3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT3_MASK) >> ENET_TS_STATUS_TSTARGT3_SHIFT) - -/* - * TSTRGTERR2 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR2_MASK (0x80U) -#define ENET_TS_STATUS_TSTRGTERR2_SHIFT (7U) -#define ENET_TS_STATUS_TSTRGTERR2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR2_MASK) >> ENET_TS_STATUS_TSTRGTERR2_SHIFT) - -/* - * TSTARGT2 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT2_MASK (0x40U) -#define ENET_TS_STATUS_TSTARGT2_SHIFT (6U) -#define ENET_TS_STATUS_TSTARGT2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT2_MASK) >> ENET_TS_STATUS_TSTARGT2_SHIFT) - -/* - * TSTRGTERR1 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR1_MASK (0x20U) -#define ENET_TS_STATUS_TSTRGTERR1_SHIFT (5U) -#define ENET_TS_STATUS_TSTRGTERR1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR1_MASK) >> ENET_TS_STATUS_TSTRGTERR1_SHIFT) - -/* - * TSTARGT1 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT1_MASK (0x10U) -#define ENET_TS_STATUS_TSTARGT1_SHIFT (4U) -#define ENET_TS_STATUS_TSTARGT1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT1_MASK) >> ENET_TS_STATUS_TSTARGT1_SHIFT) - -/* - * TSTRGTERR (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR_MASK (0x8U) -#define ENET_TS_STATUS_TSTRGTERR_SHIFT (3U) -#define ENET_TS_STATUS_TSTRGTERR_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR_MASK) >> ENET_TS_STATUS_TSTRGTERR_SHIFT) - -/* - * AUXTSTRIG (RO) - * - */ -#define ENET_TS_STATUS_AUXTSTRIG_MASK (0x4U) -#define ENET_TS_STATUS_AUXTSTRIG_SHIFT (2U) -#define ENET_TS_STATUS_AUXTSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_AUXTSTRIG_MASK) >> ENET_TS_STATUS_AUXTSTRIG_SHIFT) - -/* - * TSTARGT (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT_MASK (0x2U) -#define ENET_TS_STATUS_TSTARGT_SHIFT (1U) -#define ENET_TS_STATUS_TSTARGT_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT_MASK) >> ENET_TS_STATUS_TSTARGT_SHIFT) - -/* - * TSSOVF (RO) - * - */ -#define ENET_TS_STATUS_TSSOVF_MASK (0x1U) -#define ENET_TS_STATUS_TSSOVF_SHIFT (0U) -#define ENET_TS_STATUS_TSSOVF_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSSOVF_MASK) >> ENET_TS_STATUS_TSSOVF_SHIFT) - -/* Bitfield definition for register: PPS_CTRL */ -/* - * TRGTMODSEL3 (RW) - * - * Target Time Register Mode for PPS3 Output - * This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL3_MASK (0x60000000UL) -#define ENET_PPS_CTRL_TRGTMODSEL3_SHIFT (29U) -#define ENET_PPS_CTRL_TRGTMODSEL3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) >> ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) - -/* - * PPSCMD3 (WO) - * - * Flexible PPS3 Output Control - * This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD3_MASK (0x7000000UL) -#define ENET_PPS_CTRL_PPSCMD3_SHIFT (24U) -#define ENET_PPS_CTRL_PPSCMD3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD3_SHIFT) & ENET_PPS_CTRL_PPSCMD3_MASK) -#define ENET_PPS_CTRL_PPSCMD3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD3_MASK) >> ENET_PPS_CTRL_PPSCMD3_SHIFT) - -/* - * TRGTMODSEL2 (RW) - * - * Target Time Register Mode for PPS2 Output - * This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL2_MASK (0x600000UL) -#define ENET_PPS_CTRL_TRGTMODSEL2_SHIFT (21U) -#define ENET_PPS_CTRL_TRGTMODSEL2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) >> ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) - -/* - * PPSCMD2 (WO) - * - * Flexible PPS2 Output Control - * This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD2_MASK (0x70000UL) -#define ENET_PPS_CTRL_PPSCMD2_SHIFT (16U) -#define ENET_PPS_CTRL_PPSCMD2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD2_SHIFT) & ENET_PPS_CTRL_PPSCMD2_MASK) -#define ENET_PPS_CTRL_PPSCMD2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD2_MASK) >> ENET_PPS_CTRL_PPSCMD2_SHIFT) - -/* - * TRGTMODSEL1 (RW) - * - * Target Time Register Mode for PPS1 Output - * This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL1_MASK (0x6000U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SHIFT (13U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) - -/* - * PPSCMD1 (WO) - * - * Flexible PPS1 Output Control - * This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD1_MASK (0x700U) -#define ENET_PPS_CTRL_PPSCMD1_SHIFT (8U) -#define ENET_PPS_CTRL_PPSCMD1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD1_SHIFT) & ENET_PPS_CTRL_PPSCMD1_MASK) -#define ENET_PPS_CTRL_PPSCMD1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD1_MASK) >> ENET_PPS_CTRL_PPSCMD1_SHIFT) - -/* - * TRGTMODSEL0 (RW) - * - * Target Time Register Mode for PPS0 Output - * This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: - * - 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. - * - 01: Reserved - * - 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. - * - 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - */ -#define ENET_PPS_CTRL_TRGTMODSEL0_MASK (0x60U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SHIFT (5U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) >> ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) - -/* - * PPSEN0 (RW) - * - * Flexible PPS Output Mode Enable - * When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - */ -#define ENET_PPS_CTRL_PPSEN0_MASK (0x10U) -#define ENET_PPS_CTRL_PPSEN0_SHIFT (4U) -#define ENET_PPS_CTRL_PPSEN0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN0_SHIFT) & ENET_PPS_CTRL_PPSEN0_MASK) -#define ENET_PPS_CTRL_PPSEN0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN0_MASK) >> ENET_PPS_CTRL_PPSEN0_SHIFT) - -/* - * PPSCTRLCMD0 (RW/WO) - * - * PPSCTRL0: PPS0 Output Frequency Control - * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. - * The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. - * For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: - * - 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. - * - 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. - * - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. - * - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... - * - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. - * Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. - * In the digital rollover mode, the PPS output frequency is an average number. - * The actual clock is of different frequency that gets synchronized every second. For example: - * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - * - One clock of 50 percent duty cycle and 537 ms period - * - Second clock of 463 ms period (268 ms low and 195 ms high) - * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - * - Three clocks of 50 percent duty cycle and 268 ms period - * - Fourth clock of 195 ms period (134 ms low and 61 ms high) - * PPSCMD0: Flexible PPS0 Output Control - * 0000: No Command - * 0001: START Single Pulse - * This command generates single pulse rising at the start point defined in - * Target Time Registers and of a duration defined - * in the PPS0 Width Register. - * 0010: START Pulse Train - * This command generates the train of pulses rising at the start point - * defined in the Target Time Registers and of a duration defined in the - * PPS0 Width Register and repeated at interval defined in the PPS - * Interval Register. By default, the PPS pulse train is free-running unless - * stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train - * immediately’ commands. - * 0011: Cancel START - * This command cancels the START Single Pulse and START Pulse Train - * commands if the system time has not crossed the programmed start - * time. - * 0100: STOP Pulse train at time - * This command stops the train of pulses initiated by the START Pulse - * Train command (PPSCMD = 0010) after the time programmed in the - * Target Time registers elapses. - * 0101: STOP Pulse Train immediately - * This command immediately stops the train of pulses initiated by the - * START Pulse Train command (PPSCMD = 0010). - * 0110: Cancel STOP Pulse train - * This command cancels the STOP pulse train at time command if the - * programmed stop time has not elapsed. The PPS pulse train becomes - * free-running on the successful execution of this command. - * 0111-1111: Reserved - * Note: These bits get cleared automatically - */ -#define ENET_PPS_CTRL_PPSCTRLCMD0_MASK (0xFU) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT (0U) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) -#define ENET_PPS_CTRL_PPSCTRLCMD0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) >> ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) - -/* Bitfield definition for register: AUX_TS_NSEC */ -/* - * AUXTSLO (RO) - * - * Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - */ -#define ENET_AUX_TS_NSEC_AUXTSLO_MASK (0x7FFFFFFFUL) -#define ENET_AUX_TS_NSEC_AUXTSLO_SHIFT (0U) -#define ENET_AUX_TS_NSEC_AUXTSLO_GET(x) (((uint32_t)(x) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) >> ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) - -/* Bitfield definition for register: AUX_TS_SEC */ -/* - * AUXTSHI (RO) - * - * Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - */ -#define ENET_AUX_TS_SEC_AUXTSHI_MASK (0xFFFFFFFFUL) -#define ENET_AUX_TS_SEC_AUXTSHI_SHIFT (0U) -#define ENET_AUX_TS_SEC_AUXTSHI_GET(x) (((uint32_t)(x) & ENET_AUX_TS_SEC_AUXTSHI_MASK) >> ENET_AUX_TS_SEC_AUXTSHI_SHIFT) - -/* Bitfield definition for register: PPS0_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS0 Output Signal Interval - * These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS0 signal output is 100ns - * (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS0_INTERVAL_PPSINT_SHIFT) & ENET_PPS0_INTERVAL_PPSINT_MASK) -#define ENET_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS0_INTERVAL_PPSINT_MASK) >> ENET_PPS0_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PPS0_WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS0 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - * (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS0_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS0_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS0_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) >> ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_SEC */ -/* - * TSTRH1 (RW) - * - * PPS1 Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_PPS_TGTTM_SEC_TSTRH1_MASK (0xFFFFFFFFUL) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT (0U) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) -#define ENET_PPS_TGTTM_SEC_TSTRH1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) >> ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_NSEC */ -/* - * TRGTBUSY1 (RW) - * - * PPS1 Target Time Register Busy - * The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Targeers wht Time Registen this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. - */ -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK (0x80000000UL) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT (31U) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) >> ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) - -/* - * TTSL1 (RW) - * - * Target Time Low for PPS1 Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_PPS_TGTTM_NSEC_TTSL1_MASK (0x7FFFFFFFUL) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT (0U) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) -#define ENET_PPS_TGTTM_NSEC_TTSL1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) >> ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) - -/* Bitfield definition for register of struct array PPS: INTERVAL */ -/* - * PPSINT (RW) - * - * PPS1 Output Signal Interval - * These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), - * then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS_INTERVAL_PPSINT_SHIFT) & ENET_PPS_INTERVAL_PPSINT_MASK) -#define ENET_PPS_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS_INTERVAL_PPSINT_MASK) >> ENET_PPS_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register of struct array PPS: WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS1 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, - * if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), - * then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS_WIDTH_PPSWIDTH_MASK) >> ENET_PPS_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register: DMA_BUS_MODE */ -/* - * RIB (RW) - * - * Rebuild INCRx Burst - * When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - * the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. - * The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. - * By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - */ -#define ENET_DMA_BUS_MODE_RIB_MASK (0x80000000UL) -#define ENET_DMA_BUS_MODE_RIB_SHIFT (31U) -#define ENET_DMA_BUS_MODE_RIB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RIB_SHIFT) & ENET_DMA_BUS_MODE_RIB_MASK) -#define ENET_DMA_BUS_MODE_RIB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RIB_MASK) >> ENET_DMA_BUS_MODE_RIB_SHIFT) - -/* - * PRWG (RW) - * - * Channel Priority - * Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. - * - 00: The priority weight is 1. - * - 01: The priority weight is 2. - * - 10: The priority weight is 3. - * - 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_PRWG_MASK (0x30000000UL) -#define ENET_DMA_BUS_MODE_PRWG_SHIFT (28U) -#define ENET_DMA_BUS_MODE_PRWG_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PRWG_SHIFT) & ENET_DMA_BUS_MODE_PRWG_MASK) -#define ENET_DMA_BUS_MODE_PRWG_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PRWG_MASK) >> ENET_DMA_BUS_MODE_PRWG_SHIFT) - -/* - * TXPR (RW) - * - * Transmit Priority - * When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_TXPR_MASK (0x8000000UL) -#define ENET_DMA_BUS_MODE_TXPR_SHIFT (27U) -#define ENET_DMA_BUS_MODE_TXPR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_TXPR_SHIFT) & ENET_DMA_BUS_MODE_TXPR_MASK) -#define ENET_DMA_BUS_MODE_TXPR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_TXPR_MASK) >> ENET_DMA_BUS_MODE_TXPR_SHIFT) - -/* - * MB (RW) - * - * Mixed Burst - * When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), - * whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - */ -#define ENET_DMA_BUS_MODE_MB_MASK (0x4000000UL) -#define ENET_DMA_BUS_MODE_MB_SHIFT (26U) -#define ENET_DMA_BUS_MODE_MB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_MB_SHIFT) & ENET_DMA_BUS_MODE_MB_MASK) -#define ENET_DMA_BUS_MODE_MB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_MB_MASK) >> ENET_DMA_BUS_MODE_MB_SHIFT) - -/* - * AAL (RW) - * - * Address-Aligned Beats - * When this bit is set high and the FB bit is equal to 1, - * the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - * the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - */ -#define ENET_DMA_BUS_MODE_AAL_MASK (0x2000000UL) -#define ENET_DMA_BUS_MODE_AAL_SHIFT (25U) -#define ENET_DMA_BUS_MODE_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_AAL_SHIFT) & ENET_DMA_BUS_MODE_AAL_MASK) -#define ENET_DMA_BUS_MODE_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_AAL_MASK) >> ENET_DMA_BUS_MODE_AAL_SHIFT) - -/* - * PBLX8 (RW) - * - * PBLx8 Mode - * When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. - * Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - */ -#define ENET_DMA_BUS_MODE_PBLX8_MASK (0x1000000UL) -#define ENET_DMA_BUS_MODE_PBLX8_SHIFT (24U) -#define ENET_DMA_BUS_MODE_PBLX8_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBLX8_SHIFT) & ENET_DMA_BUS_MODE_PBLX8_MASK) -#define ENET_DMA_BUS_MODE_PBLX8_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBLX8_MASK) >> ENET_DMA_BUS_MODE_PBLX8_SHIFT) - -/* - * USP (RW) - * - * Use Separate PBL - * When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. - * The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. - * When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - */ -#define ENET_DMA_BUS_MODE_USP_MASK (0x800000UL) -#define ENET_DMA_BUS_MODE_USP_SHIFT (23U) -#define ENET_DMA_BUS_MODE_USP_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_USP_SHIFT) & ENET_DMA_BUS_MODE_USP_MASK) -#define ENET_DMA_BUS_MODE_USP_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_USP_MASK) >> ENET_DMA_BUS_MODE_USP_SHIFT) - -/* - * RPBL (RW) - * - * Rx DMA PBL - * This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - * You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. - * This field is valid and applicable only when USP is set high. - */ -#define ENET_DMA_BUS_MODE_RPBL_MASK (0x7E0000UL) -#define ENET_DMA_BUS_MODE_RPBL_SHIFT (17U) -#define ENET_DMA_BUS_MODE_RPBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RPBL_SHIFT) & ENET_DMA_BUS_MODE_RPBL_MASK) -#define ENET_DMA_BUS_MODE_RPBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RPBL_MASK) >> ENET_DMA_BUS_MODE_RPBL_SHIFT) - -/* - * FB (RW) - * - * Fixed Burst - * This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. - * When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. - * When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - */ -#define ENET_DMA_BUS_MODE_FB_MASK (0x10000UL) -#define ENET_DMA_BUS_MODE_FB_SHIFT (16U) -#define ENET_DMA_BUS_MODE_FB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_FB_SHIFT) & ENET_DMA_BUS_MODE_FB_MASK) -#define ENET_DMA_BUS_MODE_FB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_FB_MASK) >> ENET_DMA_BUS_MODE_FB_SHIFT) - -/* - * PR (RW) - * - * Priority Ratio - * These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - * These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. - * - 00: The Priority Ratio is 1:1. - * - 01: The Priority Ratio is 2:1. - * - 10: The Priority Ratio is 3:1. - * - 11: The Priority Ratio is 4:1. - */ -#define ENET_DMA_BUS_MODE_PR_MASK (0xC000U) -#define ENET_DMA_BUS_MODE_PR_SHIFT (14U) -#define ENET_DMA_BUS_MODE_PR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PR_SHIFT) & ENET_DMA_BUS_MODE_PR_MASK) -#define ENET_DMA_BUS_MODE_PR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PR_MASK) >> ENET_DMA_BUS_MODE_PR_SHIFT) - -/* - * PBL (RW) - * - * Programmable Burst Length - * These bits indicate the maximum number of beats to be transferred in one DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. - * PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. - * Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. - * If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - */ -#define ENET_DMA_BUS_MODE_PBL_MASK (0x3F00U) -#define ENET_DMA_BUS_MODE_PBL_SHIFT (8U) -#define ENET_DMA_BUS_MODE_PBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBL_SHIFT) & ENET_DMA_BUS_MODE_PBL_MASK) -#define ENET_DMA_BUS_MODE_PBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBL_MASK) >> ENET_DMA_BUS_MODE_PBL_SHIFT) - -/* - * ATDS (RW) - * - * Alternate Descriptor Size - * When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). - * This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. - * The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - * In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. - * This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - * - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. - * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - */ -#define ENET_DMA_BUS_MODE_ATDS_MASK (0x80U) -#define ENET_DMA_BUS_MODE_ATDS_SHIFT (7U) -#define ENET_DMA_BUS_MODE_ATDS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_ATDS_SHIFT) & ENET_DMA_BUS_MODE_ATDS_MASK) -#define ENET_DMA_BUS_MODE_ATDS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_ATDS_MASK) >> ENET_DMA_BUS_MODE_ATDS_SHIFT) - -/* - * DSL (RW) - * - * Descriptor Skip Length - * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. - * The address skipping starts from the end of current descriptor to the start of next descriptor. - * When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - */ -#define ENET_DMA_BUS_MODE_DSL_MASK (0x7CU) -#define ENET_DMA_BUS_MODE_DSL_SHIFT (2U) -#define ENET_DMA_BUS_MODE_DSL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DSL_SHIFT) & ENET_DMA_BUS_MODE_DSL_MASK) -#define ENET_DMA_BUS_MODE_DSL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DSL_MASK) >> ENET_DMA_BUS_MODE_DSL_SHIFT) - -/* - * DA (RW) - * - * DMA Arbitration Scheme - * This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. - * - 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). - * - 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - */ -#define ENET_DMA_BUS_MODE_DA_MASK (0x2U) -#define ENET_DMA_BUS_MODE_DA_SHIFT (1U) -#define ENET_DMA_BUS_MODE_DA_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DA_SHIFT) & ENET_DMA_BUS_MODE_DA_MASK) -#define ENET_DMA_BUS_MODE_DA_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DA_MASK) >> ENET_DMA_BUS_MODE_DA_SHIFT) - -/* - * SWR (RW) - * - * Software Reset - * When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. - * It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. - * Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. - * Note: - The Software reset function is driven only by this bit. - * Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - * - The reset operation is completed only when all resets in all active clock domains are de-asserted. - * Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. - * The time to complete the software reset operation depends on the frequency of the slowest active clock. - */ -#define ENET_DMA_BUS_MODE_SWR_MASK (0x1U) -#define ENET_DMA_BUS_MODE_SWR_SHIFT (0U) -#define ENET_DMA_BUS_MODE_SWR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_SWR_SHIFT) & ENET_DMA_BUS_MODE_SWR_MASK) -#define ENET_DMA_BUS_MODE_SWR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_SWR_MASK) >> ENET_DMA_BUS_MODE_SWR_SHIFT) - -/* Bitfield definition for register: DMA_TX_POLL_DEMAND */ -/* - * TPD (RW) - * - * Transmit Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the transmission resumes. - */ -#define ENET_DMA_TX_POLL_DEMAND_TPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT (0U) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SET(x) (((uint32_t)(x) << ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) -#define ENET_DMA_TX_POLL_DEMAND_TPD_GET(x) (((uint32_t)(x) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) >> ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_POLL_DEMAND */ -/* - * RPD (RW) - * - * Receive Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the Rx DMA returns to the active state. - */ -#define ENET_DMA_RX_POLL_DEMAND_RPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT (0U) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SET(x) (((uint32_t)(x) << ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) -#define ENET_DMA_RX_POLL_DEMAND_RPD_GET(x) (((uint32_t)(x) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) >> ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_DESC_LIST_ADDR */ -/* - * RDESLA (RW) - * - * Start of Receive List - * This field contains the base address of the first descriptor in the Receive Descriptor list. - * The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT (0U) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) >> ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) - -/* Bitfield definition for register: DMA_TX_DESC_LIST_ADDR */ -/* - * TDESLA (RW) - * - * Start of Transmit List - * This field contains the base address of the first descriptor in the Transmit Descriptor list. - * The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT (0U) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) >> ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) - -/* Bitfield definition for register: DMA_STATUS */ -/* - * GLPII (RW) - * - * GLPII: GMAC LPI Interrupt (for Channel 0) - * This bit indicates an interrupt event in the LPI logic of the MAC. - * To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. - * Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. - * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - * -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. - * To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. - * Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. - * Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - */ -#define ENET_DMA_STATUS_GLPII_MASK (0x40000000UL) -#define ENET_DMA_STATUS_GLPII_SHIFT (30U) -#define ENET_DMA_STATUS_GLPII_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLPII_SHIFT) & ENET_DMA_STATUS_GLPII_MASK) -#define ENET_DMA_STATUS_GLPII_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLPII_MASK) >> ENET_DMA_STATUS_GLPII_SHIFT) - -/* - * TTI (RW) - * - * Timestamp Trigger Interrupt - * This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - * When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. - * This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_TTI_MASK (0x20000000UL) -#define ENET_DMA_STATUS_TTI_SHIFT (29U) -#define ENET_DMA_STATUS_TTI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TTI_SHIFT) & ENET_DMA_STATUS_TTI_MASK) -#define ENET_DMA_STATUS_TTI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TTI_MASK) >> ENET_DMA_STATUS_TTI_SHIFT) - -/* - * GPI (RW) - * - * GMAC PMT Interrupt - * This bit indicates an interrupt event in the PMT module of the DWC_gmac. - * The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the Power Management feature is enabled. - * Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - */ -#define ENET_DMA_STATUS_GPI_MASK (0x10000000UL) -#define ENET_DMA_STATUS_GPI_SHIFT (28U) -#define ENET_DMA_STATUS_GPI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GPI_SHIFT) & ENET_DMA_STATUS_GPI_MASK) -#define ENET_DMA_STATUS_GPI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GPI_MASK) >> ENET_DMA_STATUS_GPI_SHIFT) - -/* - * GMI (RW) - * - * GMAC MMC Interrupt - * This bit reflects an interrupt event in the MMC module of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac - * to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_GMI_MASK (0x8000000UL) -#define ENET_DMA_STATUS_GMI_SHIFT (27U) -#define ENET_DMA_STATUS_GMI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GMI_SHIFT) & ENET_DMA_STATUS_GMI_MASK) -#define ENET_DMA_STATUS_GMI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GMI_MASK) >> ENET_DMA_STATUS_GMI_SHIFT) - -/* - * GLI (RW) - * - * GMAC Line Interface Interrupt - * When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - * - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - * - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - * Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - * the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - * read any of the following corresponding registers: - * - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - * - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - * - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - */ -#define ENET_DMA_STATUS_GLI_MASK (0x4000000UL) -#define ENET_DMA_STATUS_GLI_SHIFT (26U) -#define ENET_DMA_STATUS_GLI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLI_SHIFT) & ENET_DMA_STATUS_GLI_MASK) -#define ENET_DMA_STATUS_GLI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLI_MASK) >> ENET_DMA_STATUS_GLI_SHIFT) - -/* - * EB (RW) - * - * Error Bits - * This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - * This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. - * - 0 0 0: Error during Rx DMA Write Data Transfer - * - 0 1 1: Error during Tx DMA Read Data Transfer - * - 1 0 0: Error during Rx DMA Descriptor Write Access - * - 1 0 1: Error during Tx DMA Descriptor Write Access - * - 1 1 0: Error during Rx DMA Descriptor Read Access - * - 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - */ -#define ENET_DMA_STATUS_EB_MASK (0x3800000UL) -#define ENET_DMA_STATUS_EB_SHIFT (23U) -#define ENET_DMA_STATUS_EB_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_EB_SHIFT) & ENET_DMA_STATUS_EB_MASK) -#define ENET_DMA_STATUS_EB_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_EB_MASK) >> ENET_DMA_STATUS_EB_SHIFT) - -/* - * TS (RW) - * - * Transmit Process State - * This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped; Reset or Stop Transmit Command issued - * - 3’b001: Running; Fetching Transmit Transfer Descriptor - * - 3’b010: Running; Waiting for status - * - 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) - * - 3’b100: TIME_STAMP write state - * - 3’b101: Reserved for future use - * - 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow - * - 3’b111: Running; Closing Transmit Descriptor - */ -#define ENET_DMA_STATUS_TS_MASK (0x700000UL) -#define ENET_DMA_STATUS_TS_SHIFT (20U) -#define ENET_DMA_STATUS_TS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TS_SHIFT) & ENET_DMA_STATUS_TS_MASK) -#define ENET_DMA_STATUS_TS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TS_MASK) >> ENET_DMA_STATUS_TS_SHIFT) - -/* - * RS (RW) - * - * Receive Process State - * This field indicates the Receive DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped: Reset or Stop Receive Command issued - * - 3’b001: Running: Fetching Receive Transfer Descriptor - * - 3’b010: Reserved for future use - * - 3’b011: Running: Waiting for receive packet - * - 3’b100: Suspended: Receive Descriptor Unavailable - * - 3’b101: Running: Closing Receive Descriptor - * - 3’b110: TIME_STAMP write state - * - 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - */ -#define ENET_DMA_STATUS_RS_MASK (0xE0000UL) -#define ENET_DMA_STATUS_RS_SHIFT (17U) -#define ENET_DMA_STATUS_RS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RS_SHIFT) & ENET_DMA_STATUS_RS_MASK) -#define ENET_DMA_STATUS_RS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RS_MASK) >> ENET_DMA_STATUS_RS_SHIFT) - -/* - * NIS (RW) - * - * Normal Interrupt Summary - * Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in - * Register 7 (Interrupt Enable Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt Only unmasked bits - * (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_NIS_MASK (0x10000UL) -#define ENET_DMA_STATUS_NIS_SHIFT (16U) -#define ENET_DMA_STATUS_NIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_NIS_SHIFT) & ENET_DMA_STATUS_NIS_MASK) -#define ENET_DMA_STATUS_NIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_NIS_MASK) >> ENET_DMA_STATUS_NIS_SHIFT) - -/* - * AIS (RW) - * - * Abnormal Interrupt Summary - * Abnormal Interrupt Summary bit value is the logical OR of the following - * when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive FIFO Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_AIS_MASK (0x8000U) -#define ENET_DMA_STATUS_AIS_SHIFT (15U) -#define ENET_DMA_STATUS_AIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_AIS_SHIFT) & ENET_DMA_STATUS_AIS_MASK) -#define ENET_DMA_STATUS_AIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_AIS_MASK) >> ENET_DMA_STATUS_AIS_SHIFT) - -/* - * ERI (RW) - * - * Early Receive Interrupt - * This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - */ -#define ENET_DMA_STATUS_ERI_MASK (0x4000U) -#define ENET_DMA_STATUS_ERI_SHIFT (14U) -#define ENET_DMA_STATUS_ERI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ERI_SHIFT) & ENET_DMA_STATUS_ERI_MASK) -#define ENET_DMA_STATUS_ERI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ERI_MASK) >> ENET_DMA_STATUS_ERI_SHIFT) - -/* - * FBI (RW) - * - * Fatal Bus Error Interrupt - * This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - */ -#define ENET_DMA_STATUS_FBI_MASK (0x2000U) -#define ENET_DMA_STATUS_FBI_SHIFT (13U) -#define ENET_DMA_STATUS_FBI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_FBI_SHIFT) & ENET_DMA_STATUS_FBI_MASK) -#define ENET_DMA_STATUS_FBI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_FBI_MASK) >> ENET_DMA_STATUS_FBI_SHIFT) - -/* - * ETI (RW) - * - * Early Transmit Interrupt - * This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - */ -#define ENET_DMA_STATUS_ETI_MASK (0x400U) -#define ENET_DMA_STATUS_ETI_SHIFT (10U) -#define ENET_DMA_STATUS_ETI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ETI_SHIFT) & ENET_DMA_STATUS_ETI_MASK) -#define ENET_DMA_STATUS_ETI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ETI_MASK) >> ENET_DMA_STATUS_ETI_SHIFT) - -/* - * RWT (RW) - * - * Receive Watchdog Timeout - * When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - */ -#define ENET_DMA_STATUS_RWT_MASK (0x200U) -#define ENET_DMA_STATUS_RWT_SHIFT (9U) -#define ENET_DMA_STATUS_RWT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RWT_SHIFT) & ENET_DMA_STATUS_RWT_MASK) -#define ENET_DMA_STATUS_RWT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RWT_MASK) >> ENET_DMA_STATUS_RWT_SHIFT) - -/* - * RPS (RW) - * - * Receive Process Stopped - * This bit is asserted when the Receive Process enters the Stopped state. - */ -#define ENET_DMA_STATUS_RPS_MASK (0x100U) -#define ENET_DMA_STATUS_RPS_SHIFT (8U) -#define ENET_DMA_STATUS_RPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RPS_SHIFT) & ENET_DMA_STATUS_RPS_MASK) -#define ENET_DMA_STATUS_RPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RPS_MASK) >> ENET_DMA_STATUS_RPS_SHIFT) - -/* - * RU (RW) - * - * Receive Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. - * The Receive Process is suspended. To resume processing Receive descriptors, - * the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - * If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. - * This bit is set only when the previous Receive Descriptor is owned by the DMA. - */ -#define ENET_DMA_STATUS_RU_MASK (0x80U) -#define ENET_DMA_STATUS_RU_SHIFT (7U) -#define ENET_DMA_STATUS_RU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RU_SHIFT) & ENET_DMA_STATUS_RU_MASK) -#define ENET_DMA_STATUS_RU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RU_MASK) >> ENET_DMA_STATUS_RU_SHIFT) - -/* - * RI (RW) - * - * Receive Interrupt - * This bit indicates that the frame reception is complete. - * When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, - * and the specific frame status information is updated in the descriptor. - * The reception remains in the Running state. - */ -#define ENET_DMA_STATUS_RI_MASK (0x40U) -#define ENET_DMA_STATUS_RI_SHIFT (6U) -#define ENET_DMA_STATUS_RI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RI_SHIFT) & ENET_DMA_STATUS_RI_MASK) -#define ENET_DMA_STATUS_RI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RI_MASK) >> ENET_DMA_STATUS_RI_SHIFT) - -/* - * UNF (RW) - * - * Transmit Underflow - * This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - */ -#define ENET_DMA_STATUS_UNF_MASK (0x20U) -#define ENET_DMA_STATUS_UNF_SHIFT (5U) -#define ENET_DMA_STATUS_UNF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_UNF_SHIFT) & ENET_DMA_STATUS_UNF_MASK) -#define ENET_DMA_STATUS_UNF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_UNF_MASK) >> ENET_DMA_STATUS_UNF_SHIFT) - -/* - * OVF (RW) - * - * Receive Overflow - * This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - */ -#define ENET_DMA_STATUS_OVF_MASK (0x10U) -#define ENET_DMA_STATUS_OVF_SHIFT (4U) -#define ENET_DMA_STATUS_OVF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_OVF_SHIFT) & ENET_DMA_STATUS_OVF_MASK) -#define ENET_DMA_STATUS_OVF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_OVF_MASK) >> ENET_DMA_STATUS_OVF_SHIFT) - -/* - * TJT (RW) - * - * Transmit Jabber Timeout - * This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). - * When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - */ -#define ENET_DMA_STATUS_TJT_MASK (0x8U) -#define ENET_DMA_STATUS_TJT_SHIFT (3U) -#define ENET_DMA_STATUS_TJT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TJT_SHIFT) & ENET_DMA_STATUS_TJT_MASK) -#define ENET_DMA_STATUS_TJT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TJT_MASK) >> ENET_DMA_STATUS_TJT_SHIFT) - -/* - * TU (RW) - * - * Transmit Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. - * To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - */ -#define ENET_DMA_STATUS_TU_MASK (0x4U) -#define ENET_DMA_STATUS_TU_SHIFT (2U) -#define ENET_DMA_STATUS_TU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TU_SHIFT) & ENET_DMA_STATUS_TU_MASK) -#define ENET_DMA_STATUS_TU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TU_MASK) >> ENET_DMA_STATUS_TU_SHIFT) - -/* - * TPS (RW) - * - * Transmit Process Stopped - * This bit is set when the transmission is stopped. - */ -#define ENET_DMA_STATUS_TPS_MASK (0x2U) -#define ENET_DMA_STATUS_TPS_SHIFT (1U) -#define ENET_DMA_STATUS_TPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TPS_SHIFT) & ENET_DMA_STATUS_TPS_MASK) -#define ENET_DMA_STATUS_TPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TPS_MASK) >> ENET_DMA_STATUS_TPS_SHIFT) - -/* - * TI (RW) - * - * Transmit Interrupt - * This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - */ -#define ENET_DMA_STATUS_TI_MASK (0x1U) -#define ENET_DMA_STATUS_TI_SHIFT (0U) -#define ENET_DMA_STATUS_TI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TI_SHIFT) & ENET_DMA_STATUS_TI_MASK) -#define ENET_DMA_STATUS_TI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TI_MASK) >> ENET_DMA_STATUS_TI_SHIFT) - -/* Bitfield definition for register: DMA_OP_MODE */ -/* - * DT (RW) - * - * Disable Dropping of TCP/IP Checksum Error Frames - * When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - * Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. - * When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - */ -#define ENET_DMA_OP_MODE_DT_MASK (0x10000000UL) -#define ENET_DMA_OP_MODE_DT_SHIFT (28U) -#define ENET_DMA_OP_MODE_DT_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DT_SHIFT) & ENET_DMA_OP_MODE_DT_MASK) -#define ENET_DMA_OP_MODE_DT_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DT_MASK) >> ENET_DMA_OP_MODE_DT_SHIFT) - -/* - * RSF (RW) - * - * Receive Store and Forward - * When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - * When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - */ -#define ENET_DMA_OP_MODE_RSF_MASK (0x2000000UL) -#define ENET_DMA_OP_MODE_RSF_SHIFT (25U) -#define ENET_DMA_OP_MODE_RSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RSF_SHIFT) & ENET_DMA_OP_MODE_RSF_MASK) -#define ENET_DMA_OP_MODE_RSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RSF_MASK) >> ENET_DMA_OP_MODE_RSF_SHIFT) - -/* - * DFF (RW) - * - * Disable Flushing of Received Frames - * When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - */ -#define ENET_DMA_OP_MODE_DFF_MASK (0x1000000UL) -#define ENET_DMA_OP_MODE_DFF_SHIFT (24U) -#define ENET_DMA_OP_MODE_DFF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DFF_SHIFT) & ENET_DMA_OP_MODE_DFF_MASK) -#define ENET_DMA_OP_MODE_DFF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DFF_MASK) >> ENET_DMA_OP_MODE_DFF_SHIFT) - -/* - * RFA_2 (RW) - * - * MSB of Threshold for Activating Flow Control - * If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFA_2_MASK (0x800000UL) -#define ENET_DMA_OP_MODE_RFA_2_SHIFT (23U) -#define ENET_DMA_OP_MODE_RFA_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_2_SHIFT) & ENET_DMA_OP_MODE_RFA_2_MASK) -#define ENET_DMA_OP_MODE_RFA_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_2_MASK) >> ENET_DMA_OP_MODE_RFA_2_SHIFT) - -/* - * RFD_2 (RW) - * - * MSB of Threshold for Deactivating Flow Control - * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFD_2_MASK (0x400000UL) -#define ENET_DMA_OP_MODE_RFD_2_SHIFT (22U) -#define ENET_DMA_OP_MODE_RFD_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_2_SHIFT) & ENET_DMA_OP_MODE_RFD_2_MASK) -#define ENET_DMA_OP_MODE_RFD_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_2_MASK) >> ENET_DMA_OP_MODE_RFD_2_SHIFT) - -/* - * TSF (RW) - * - * Transmit Store and Forward - * When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. - * When this bit is set, the TTC values specified in Bits [16:14] are ignored. - * This bit should be changed only when the transmission is stopped. - */ -#define ENET_DMA_OP_MODE_TSF_MASK (0x200000UL) -#define ENET_DMA_OP_MODE_TSF_SHIFT (21U) -#define ENET_DMA_OP_MODE_TSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TSF_SHIFT) & ENET_DMA_OP_MODE_TSF_MASK) -#define ENET_DMA_OP_MODE_TSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TSF_MASK) >> ENET_DMA_OP_MODE_TSF_SHIFT) - -/* - * FTF (RW) - * - * Flush Transmit FIFO - * When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. - * This bit is cleared internally when the flushing operation is complete. - * The Operation Mode register should not be written to until this bit is cleared. - * The data which is already accepted by the MAC transmitter is not flushed. - * It is scheduled for transmission and results in underflow and runt frame transmission. - */ -#define ENET_DMA_OP_MODE_FTF_MASK (0x100000UL) -#define ENET_DMA_OP_MODE_FTF_SHIFT (20U) -#define ENET_DMA_OP_MODE_FTF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FTF_SHIFT) & ENET_DMA_OP_MODE_FTF_MASK) -#define ENET_DMA_OP_MODE_FTF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FTF_MASK) >> ENET_DMA_OP_MODE_FTF_SHIFT) - -/* - * TTC (RW) - * - * Transmit Threshold Control - * These bits control the threshold level of the MTL Transmit FIFO. - * Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. - * In addition, full frames with a length less than the threshold are also transmitted. - * These bits are used only when Bit 21 (TSF) is reset. - * - 000: 64 - * - 001: 128 - * - 010: 192 - * - 011: 256 - * - 100: 40 - * - 101: 32 - * - 110: 24 - * - 111: 16 - */ -#define ENET_DMA_OP_MODE_TTC_MASK (0x1C000UL) -#define ENET_DMA_OP_MODE_TTC_SHIFT (14U) -#define ENET_DMA_OP_MODE_TTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TTC_SHIFT) & ENET_DMA_OP_MODE_TTC_MASK) -#define ENET_DMA_OP_MODE_TTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TTC_MASK) >> ENET_DMA_OP_MODE_TTC_SHIFT) - -/* - * ST (RW) - * - * Start or Stop Transmission Command - * When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. - * Descriptor acquisition is attempted either from the current position in the list, - * which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), - * or from the position retained when transmission was stopped previously. - * If the DMA does not own the current descriptor, - * transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Transmission command is effective only when transmission is stopped. - * If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - * then the DMA behavior is unpredictable. When this bit is reset, - * the transmission process is placed in the Stopped state after completing the transmission of the current frame. - * The Next Descriptor position in the Transmit List is saved, - * and it becomes the current position when transmission is restarted. - * To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. - * The new value is considered when this bit is set again. - * The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - */ -#define ENET_DMA_OP_MODE_ST_MASK (0x2000U) -#define ENET_DMA_OP_MODE_ST_SHIFT (13U) -#define ENET_DMA_OP_MODE_ST_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_ST_SHIFT) & ENET_DMA_OP_MODE_ST_MASK) -#define ENET_DMA_OP_MODE_ST_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_ST_MASK) >> ENET_DMA_OP_MODE_ST_SHIFT) - -/* - * RFD (RW) - * - * Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. - * - 00: Full minus 1 KB, that is, FULL — 1 KB - * - 01: Full minus 2 KB, that is, FULL — 2 KB - * - 10: Full minus 3 KB, that is, FULL — 3 KB - * - 11: Full minus 4 KB, that is, FULL — 4 KB - * The de-assertion is effective only after flow control is asserted. - * If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. - * These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_RFD_MASK (0x1800U) -#define ENET_DMA_OP_MODE_RFD_SHIFT (11U) -#define ENET_DMA_OP_MODE_RFD_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_SHIFT) & ENET_DMA_OP_MODE_RFD_MASK) -#define ENET_DMA_OP_MODE_RFD_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_MASK) >> ENET_DMA_OP_MODE_RFD_SHIFT) - -/* - * RFA (RW) - * - * Threshold for Activating Flow Control (in half-duplex and full-duplex modes) - * These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. - * - 00: Full minus 1 KB, that is, FULL—1KB. - * - 01: Full minus 2 KB, that is, FULL—2KB. - * - 10: Full minus 3 KB, that is, FULL—3KB. - * - 11: Full minus 4 KB, that is, FULL—4KB. - * These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, - * an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. - * These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. - * Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, - * the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - */ -#define ENET_DMA_OP_MODE_RFA_MASK (0x600U) -#define ENET_DMA_OP_MODE_RFA_SHIFT (9U) -#define ENET_DMA_OP_MODE_RFA_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_SHIFT) & ENET_DMA_OP_MODE_RFA_MASK) -#define ENET_DMA_OP_MODE_RFA_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_MASK) >> ENET_DMA_OP_MODE_RFA_SHIFT) - -/* - * EFC (RW) - * - * Enable HW Flow Control - * When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. - * When reset, the flow control operation is disabled. - * This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_EFC_MASK (0x100U) -#define ENET_DMA_OP_MODE_EFC_SHIFT (8U) -#define ENET_DMA_OP_MODE_EFC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_EFC_SHIFT) & ENET_DMA_OP_MODE_EFC_MASK) -#define ENET_DMA_OP_MODE_EFC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_EFC_MASK) >> ENET_DMA_OP_MODE_EFC_SHIFT) - -/* - * FEF (RW) - * - * Forward Error Frames - * When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). - * However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), - * then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, - * the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. - * When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. - * If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, - * then the frame is dropped irrespective of the FEF bit setting. - * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. - * Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - * - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - * - The advanced timestamp feature is not selected but the extended status is selected. - * The extended status is available with the following features: - * - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - * - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - */ -#define ENET_DMA_OP_MODE_FEF_MASK (0x80U) -#define ENET_DMA_OP_MODE_FEF_SHIFT (7U) -#define ENET_DMA_OP_MODE_FEF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FEF_SHIFT) & ENET_DMA_OP_MODE_FEF_MASK) -#define ENET_DMA_OP_MODE_FEF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FEF_MASK) >> ENET_DMA_OP_MODE_FEF_SHIFT) - -/* - * FUF (RW) - * - * Forward Undersized Good Frames - * When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC - * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - */ -#define ENET_DMA_OP_MODE_FUF_MASK (0x40U) -#define ENET_DMA_OP_MODE_FUF_SHIFT (6U) -#define ENET_DMA_OP_MODE_FUF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FUF_SHIFT) & ENET_DMA_OP_MODE_FUF_MASK) -#define ENET_DMA_OP_MODE_FUF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FUF_MASK) >> ENET_DMA_OP_MODE_FUF_SHIFT) - -/* - * DGF (RW) - * - * Drop Giant Frames - * When set, the MAC drops the received giant frames in the Rx FIFO, - * that is, frames that are larger than the computed giant frame limit. - * When reset, the MAC does not drop the giant frames in the Rx FIFO. - * Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - * - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - * - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - * - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - */ -#define ENET_DMA_OP_MODE_DGF_MASK (0x20U) -#define ENET_DMA_OP_MODE_DGF_SHIFT (5U) -#define ENET_DMA_OP_MODE_DGF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DGF_SHIFT) & ENET_DMA_OP_MODE_DGF_MASK) -#define ENET_DMA_OP_MODE_DGF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DGF_MASK) >> ENET_DMA_OP_MODE_DGF_SHIFT) - -/* - * RTC (RW) - * - * Receive Threshold Control - * These two bits control the threshold level of the MTL Receive FIFO. - * Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. - * In addition, full frames with length less than the threshold are automatically transferred. - * The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. - * These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. - * - 00: 64 - * - 01: 32 - * - 10: 96 - * - 11: 128 - */ -#define ENET_DMA_OP_MODE_RTC_MASK (0x18U) -#define ENET_DMA_OP_MODE_RTC_SHIFT (3U) -#define ENET_DMA_OP_MODE_RTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RTC_SHIFT) & ENET_DMA_OP_MODE_RTC_MASK) -#define ENET_DMA_OP_MODE_RTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RTC_MASK) >> ENET_DMA_OP_MODE_RTC_SHIFT) - -/* - * OSF (RW) - * - * Operate on Second Frame - * When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - */ -#define ENET_DMA_OP_MODE_OSF_MASK (0x4U) -#define ENET_DMA_OP_MODE_OSF_SHIFT (2U) -#define ENET_DMA_OP_MODE_OSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_OSF_SHIFT) & ENET_DMA_OP_MODE_OSF_MASK) -#define ENET_DMA_OP_MODE_OSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_OSF_MASK) >> ENET_DMA_OP_MODE_OSF_SHIFT) - -/* - * SR (RW) - * - * Start or Stop Receive - * When this bit is set, the Receive process is placed in the Running state. - * The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. - * The descriptor acquisition is attempted from the current position in the list, - * which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. - * If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Receive command is effective only when the reception has stopped. - * If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. - * When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. - * The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. - * The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - */ -#define ENET_DMA_OP_MODE_SR_MASK (0x2U) -#define ENET_DMA_OP_MODE_SR_SHIFT (1U) -#define ENET_DMA_OP_MODE_SR_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_SR_SHIFT) & ENET_DMA_OP_MODE_SR_MASK) -#define ENET_DMA_OP_MODE_SR_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_SR_MASK) >> ENET_DMA_OP_MODE_SR_SHIFT) - -/* Bitfield definition for register: DMA_INTR_EN */ -/* - * NIE (RW) - * - * Normal Interrupt Summary Enable - * When this bit is set, normal interrupt summary is enabled. - * When this bit is reset, normal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt - */ -#define ENET_DMA_INTR_EN_NIE_MASK (0x10000UL) -#define ENET_DMA_INTR_EN_NIE_SHIFT (16U) -#define ENET_DMA_INTR_EN_NIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_NIE_SHIFT) & ENET_DMA_INTR_EN_NIE_MASK) -#define ENET_DMA_INTR_EN_NIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_NIE_MASK) >> ENET_DMA_INTR_EN_NIE_SHIFT) - -/* - * AIE (RW) - * - * Abnormal Interrupt Summary Enable - * When this bit is set, abnormal interrupt summary is enabled. - * When this bit is reset, the abnormal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error - */ -#define ENET_DMA_INTR_EN_AIE_MASK (0x8000U) -#define ENET_DMA_INTR_EN_AIE_SHIFT (15U) -#define ENET_DMA_INTR_EN_AIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_AIE_SHIFT) & ENET_DMA_INTR_EN_AIE_MASK) -#define ENET_DMA_INTR_EN_AIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_AIE_MASK) >> ENET_DMA_INTR_EN_AIE_SHIFT) - -/* - * ERE (RW) - * - * Early Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ERE_MASK (0x4000U) -#define ENET_DMA_INTR_EN_ERE_SHIFT (14U) -#define ENET_DMA_INTR_EN_ERE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ERE_SHIFT) & ENET_DMA_INTR_EN_ERE_MASK) -#define ENET_DMA_INTR_EN_ERE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ERE_MASK) >> ENET_DMA_INTR_EN_ERE_SHIFT) - -/* - * FBE (RW) - * - * Fatal Bus Error Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_FBE_MASK (0x2000U) -#define ENET_DMA_INTR_EN_FBE_SHIFT (13U) -#define ENET_DMA_INTR_EN_FBE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_FBE_SHIFT) & ENET_DMA_INTR_EN_FBE_MASK) -#define ENET_DMA_INTR_EN_FBE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_FBE_MASK) >> ENET_DMA_INTR_EN_FBE_SHIFT) - -/* - * ETE (RW) - * - * Early Transmit Interrupt Enable - * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ETE_MASK (0x400U) -#define ENET_DMA_INTR_EN_ETE_SHIFT (10U) -#define ENET_DMA_INTR_EN_ETE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ETE_SHIFT) & ENET_DMA_INTR_EN_ETE_MASK) -#define ENET_DMA_INTR_EN_ETE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ETE_MASK) >> ENET_DMA_INTR_EN_ETE_SHIFT) - -/* - * RWE (RW) - * - * Receive Watchdog Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RWE_MASK (0x200U) -#define ENET_DMA_INTR_EN_RWE_SHIFT (9U) -#define ENET_DMA_INTR_EN_RWE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RWE_SHIFT) & ENET_DMA_INTR_EN_RWE_MASK) -#define ENET_DMA_INTR_EN_RWE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RWE_MASK) >> ENET_DMA_INTR_EN_RWE_SHIFT) - -/* - * RSE (RW) - * - * Receive Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RSE_MASK (0x100U) -#define ENET_DMA_INTR_EN_RSE_SHIFT (8U) -#define ENET_DMA_INTR_EN_RSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RSE_SHIFT) & ENET_DMA_INTR_EN_RSE_MASK) -#define ENET_DMA_INTR_EN_RSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RSE_MASK) >> ENET_DMA_INTR_EN_RSE_SHIFT) - -/* - * RUE (RW) - * - * Receive Buffer Unavailable Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RUE_MASK (0x80U) -#define ENET_DMA_INTR_EN_RUE_SHIFT (7U) -#define ENET_DMA_INTR_EN_RUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RUE_SHIFT) & ENET_DMA_INTR_EN_RUE_MASK) -#define ENET_DMA_INTR_EN_RUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RUE_MASK) >> ENET_DMA_INTR_EN_RUE_SHIFT) - -/* - * RIE (RW) - * - * Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RIE_MASK (0x40U) -#define ENET_DMA_INTR_EN_RIE_SHIFT (6U) -#define ENET_DMA_INTR_EN_RIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RIE_SHIFT) & ENET_DMA_INTR_EN_RIE_MASK) -#define ENET_DMA_INTR_EN_RIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RIE_MASK) >> ENET_DMA_INTR_EN_RIE_SHIFT) - -/* - * UNE (RW) - * - * Underflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_UNE_MASK (0x20U) -#define ENET_DMA_INTR_EN_UNE_SHIFT (5U) -#define ENET_DMA_INTR_EN_UNE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_UNE_SHIFT) & ENET_DMA_INTR_EN_UNE_MASK) -#define ENET_DMA_INTR_EN_UNE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_UNE_MASK) >> ENET_DMA_INTR_EN_UNE_SHIFT) - -/* - * OVE (RW) - * - * Overflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_OVE_MASK (0x10U) -#define ENET_DMA_INTR_EN_OVE_SHIFT (4U) -#define ENET_DMA_INTR_EN_OVE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_OVE_SHIFT) & ENET_DMA_INTR_EN_OVE_MASK) -#define ENET_DMA_INTR_EN_OVE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_OVE_MASK) >> ENET_DMA_INTR_EN_OVE_SHIFT) - -/* - * TJE (RW) - * - * Transmit Jabber Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TJE_MASK (0x8U) -#define ENET_DMA_INTR_EN_TJE_SHIFT (3U) -#define ENET_DMA_INTR_EN_TJE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TJE_SHIFT) & ENET_DMA_INTR_EN_TJE_MASK) -#define ENET_DMA_INTR_EN_TJE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TJE_MASK) >> ENET_DMA_INTR_EN_TJE_SHIFT) - -/* - * TUE (RW) - * - * Transmit Buffer Unavailable Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TUE_MASK (0x4U) -#define ENET_DMA_INTR_EN_TUE_SHIFT (2U) -#define ENET_DMA_INTR_EN_TUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TUE_SHIFT) & ENET_DMA_INTR_EN_TUE_MASK) -#define ENET_DMA_INTR_EN_TUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TUE_MASK) >> ENET_DMA_INTR_EN_TUE_SHIFT) - -/* - * TSE (RW) - * - * Transmit Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TSE_MASK (0x2U) -#define ENET_DMA_INTR_EN_TSE_SHIFT (1U) -#define ENET_DMA_INTR_EN_TSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TSE_SHIFT) & ENET_DMA_INTR_EN_TSE_MASK) -#define ENET_DMA_INTR_EN_TSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TSE_MASK) >> ENET_DMA_INTR_EN_TSE_SHIFT) - -/* - * TIE (RW) - * - * Transmit Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TIE_MASK (0x1U) -#define ENET_DMA_INTR_EN_TIE_SHIFT (0U) -#define ENET_DMA_INTR_EN_TIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TIE_SHIFT) & ENET_DMA_INTR_EN_TIE_MASK) -#define ENET_DMA_INTR_EN_TIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TIE_MASK) >> ENET_DMA_INTR_EN_TIE_SHIFT) - -/* Bitfield definition for register: DMA_MISS_OVF_CNT */ -/* - * ONFCNTOVF (RW) - * - * Overflow Bit for FIFO Overflow Counter - * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, - * that is, the Rx FIFO overflows with the overflow frame counter at maximum value. - * In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK (0x10000000UL) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT (28U) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) - -/* - * OVFFRMCNT (RW) - * - * Overflow Frame Counter - * This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK (0xFFE0000UL) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT (17U) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) - -/* - * MISCNTOVF (RW) - * - * Overflow Bit for Missed Frame Counter - * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, - * that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - * the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK (0x10000UL) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT (16U) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) - -/* - * MISFRMCNT (RW) - * - * Missed Frame Counter - * This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. - * This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK (0xFFFFU) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT (0U) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) - -/* Bitfield definition for register: DMA_RX_INTR_WDOG */ -/* - * RIWT (RW) - * - * RI Watchdog Timer Count - * This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. - * The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer - * of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. - * When the watchdog timer runs out, the RI bit is set and the timer is stopped. - * The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - */ -#define ENET_DMA_RX_INTR_WDOG_RIWT_MASK (0xFFU) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT (0U) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SET(x) (((uint32_t)(x) << ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) -#define ENET_DMA_RX_INTR_WDOG_RIWT_GET(x) (((uint32_t)(x) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) >> ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) - -/* Bitfield definition for register: DMA_AXI_MODE */ -/* - * EN_LPI (RW) - * - * Enable Low Power Interface (LPI) - * When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. - * When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - */ -#define ENET_DMA_AXI_MODE_EN_LPI_MASK (0x80000000UL) -#define ENET_DMA_AXI_MODE_EN_LPI_SHIFT (31U) -#define ENET_DMA_AXI_MODE_EN_LPI_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_EN_LPI_SHIFT) & ENET_DMA_AXI_MODE_EN_LPI_MASK) -#define ENET_DMA_AXI_MODE_EN_LPI_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_EN_LPI_MASK) >> ENET_DMA_AXI_MODE_EN_LPI_SHIFT) - -/* - * LPI_XIT_FRM (RW) - * - * Unlock on Magic Packet or Remote Wake-Up Frame - * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. - * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - */ -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK (0x40000000UL) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT (30U) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) >> ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) - -/* - * WR_OSR_LMT (RW) - * - * AXI Maximum Write Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI write interface. - * Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK (0xF00000UL) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT (20U) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) - -/* - * RD_OSR_LMT (RW) - * - * AXI Maximum Read Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI read interface. - * Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK (0xF0000UL) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT (16U) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) - -/* - * ONEKBBE (RW) - * - * 1 KB Boundary Crossing Enable for the GMAC-AXI Master - * When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. - * When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - */ -#define ENET_DMA_AXI_MODE_ONEKBBE_MASK (0x2000U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SHIFT (13U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) -#define ENET_DMA_AXI_MODE_ONEKBBE_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) >> ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) - -/* - * AXI_AAL (RW) - * - * Address-Aligned Beats - * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). - * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - */ -#define ENET_DMA_AXI_MODE_AXI_AAL_MASK (0x1000U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SHIFT (12U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) -#define ENET_DMA_AXI_MODE_AXI_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) >> ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) - -/* - * BLEN256 (RW) - * - * AXI Burst Length 256 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN256_MASK (0x80U) -#define ENET_DMA_AXI_MODE_BLEN256_SHIFT (7U) -#define ENET_DMA_AXI_MODE_BLEN256_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN256_SHIFT) & ENET_DMA_AXI_MODE_BLEN256_MASK) -#define ENET_DMA_AXI_MODE_BLEN256_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN256_MASK) >> ENET_DMA_AXI_MODE_BLEN256_SHIFT) - -/* - * BLEN128 (RW) - * - * AXI Burst Length 128 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN128_MASK (0x40U) -#define ENET_DMA_AXI_MODE_BLEN128_SHIFT (6U) -#define ENET_DMA_AXI_MODE_BLEN128_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN128_SHIFT) & ENET_DMA_AXI_MODE_BLEN128_MASK) -#define ENET_DMA_AXI_MODE_BLEN128_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN128_MASK) >> ENET_DMA_AXI_MODE_BLEN128_SHIFT) - -/* - * BLEN64 (RW) - * - * AXI Burst Length 64 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN64_MASK (0x20U) -#define ENET_DMA_AXI_MODE_BLEN64_SHIFT (5U) -#define ENET_DMA_AXI_MODE_BLEN64_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN64_SHIFT) & ENET_DMA_AXI_MODE_BLEN64_MASK) -#define ENET_DMA_AXI_MODE_BLEN64_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN64_MASK) >> ENET_DMA_AXI_MODE_BLEN64_SHIFT) - -/* - * BLEN32 (RW) - * - * AXI Burst Length 32 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN32_MASK (0x10U) -#define ENET_DMA_AXI_MODE_BLEN32_SHIFT (4U) -#define ENET_DMA_AXI_MODE_BLEN32_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN32_SHIFT) & ENET_DMA_AXI_MODE_BLEN32_MASK) -#define ENET_DMA_AXI_MODE_BLEN32_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN32_MASK) >> ENET_DMA_AXI_MODE_BLEN32_SHIFT) - -/* - * BLEN16 (RW) - * - * AXI Burst Length 16 - * When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - */ -#define ENET_DMA_AXI_MODE_BLEN16_MASK (0x8U) -#define ENET_DMA_AXI_MODE_BLEN16_SHIFT (3U) -#define ENET_DMA_AXI_MODE_BLEN16_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN16_SHIFT) & ENET_DMA_AXI_MODE_BLEN16_MASK) -#define ENET_DMA_AXI_MODE_BLEN16_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN16_MASK) >> ENET_DMA_AXI_MODE_BLEN16_SHIFT) - -/* - * BLEN8 (RW) - * - * AXI Burst Length 8 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN8_MASK (0x4U) -#define ENET_DMA_AXI_MODE_BLEN8_SHIFT (2U) -#define ENET_DMA_AXI_MODE_BLEN8_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN8_SHIFT) & ENET_DMA_AXI_MODE_BLEN8_MASK) -#define ENET_DMA_AXI_MODE_BLEN8_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN8_MASK) >> ENET_DMA_AXI_MODE_BLEN8_SHIFT) - -/* - * BLEN4 (RW) - * - * AXI Burst Length 4 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN4_MASK (0x2U) -#define ENET_DMA_AXI_MODE_BLEN4_SHIFT (1U) -#define ENET_DMA_AXI_MODE_BLEN4_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN4_SHIFT) & ENET_DMA_AXI_MODE_BLEN4_MASK) -#define ENET_DMA_AXI_MODE_BLEN4_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN4_MASK) >> ENET_DMA_AXI_MODE_BLEN4_SHIFT) - -/* - * UNDEF (RW) - * - * AXI Undefined Burst Length - * This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - * - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - * - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. - * If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - */ -#define ENET_DMA_AXI_MODE_UNDEF_MASK (0x1U) -#define ENET_DMA_AXI_MODE_UNDEF_SHIFT (0U) -#define ENET_DMA_AXI_MODE_UNDEF_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_UNDEF_SHIFT) & ENET_DMA_AXI_MODE_UNDEF_MASK) -#define ENET_DMA_AXI_MODE_UNDEF_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_UNDEF_MASK) >> ENET_DMA_AXI_MODE_UNDEF_SHIFT) - -/* Bitfield definition for register: DMA_BUS_STATUS */ -/* - * AXIRDSTS (RW) - * - * AXI Master Read Channel Status - * When high, it indicates that AXI master's read channel is active and transferring data. - */ -#define ENET_DMA_BUS_STATUS_AXIRDSTS_MASK (0x2U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT (1U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) >> ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) - -/* - * AXWHSTS (RW) - * - * AXI Master Write Channel or AHB Master Status - * When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - * it indicates that the AHB master interface FSMs are in the non-idle state. - */ -#define ENET_DMA_BUS_STATUS_AXWHSTS_MASK (0x1U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT (0U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXWHSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) >> ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_DESC */ -/* - * CURTDESAPTR (RW) - * - * Host Transmit Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_DESC */ -/* - * CURRDESAPTR (RW) - * - * Host Receive Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_BUF */ -/* - * CURTBUFAPTR (RW) - * - * Host Transmit Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_BUF */ -/* - * CURRBUFAPTR (RW) - * - * Host Receive Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) - -/* Bitfield definition for register: CTRL2 */ -/* - * ENET0_LPI_IRQ_EN (RW) - * - * lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt - */ -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) - -/* - * ENET0_REFCLK_OE (RW) - * - * set to enable output 50MHz clock to rmii phy. - * User should set it if use soc internal clock as refclk - */ -#define ENET_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) -#define ENET_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) -#define ENET_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) -#define ENET_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) >> ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) - -/* - * ENET0_PHY_INF_SEL (RW) - * - * PHY mode select - * 001RGMII; 100RMII; - * should be set before config IOMUX, otherwise may cause glitch for RGMII - */ -#define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK (0xE000U) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT (13U) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) >> ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) - -/* - * ENET0_FLOWCTRL (RW) - * - * flow control request - */ -#define ENET_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) -#define ENET_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) -#define ENET_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) -#define ENET_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) >> ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) - -/* - * ENET0_RMII_TXCLK_SEL (RW) - * - * RMII mode output clock pad select - * set to use refclk from pad; - * Note: refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. - */ -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) - - - -/* MAC_ADDR register group index macro definition */ -#define ENET_MAC_ADDR_1 (0UL) -#define ENET_MAC_ADDR_2 (1UL) -#define ENET_MAC_ADDR_3 (2UL) -#define ENET_MAC_ADDR_4 (3UL) - -/* L3_L4_CFG register group index macro definition */ -#define ENET_L3_L4_CFG_0 (0UL) - -/* PPS register group index macro definition */ -#define ENET_PPS_1 (0UL) -#define ENET_PPS_2 (1UL) -#define ENET_PPS_3 (2UL) - - -#endif /* HPM_ENET_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_femc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_femc_regs.h deleted file mode 100644 index f450817a80b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_femc_regs.h +++ /dev/null @@ -1,981 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_FEMC_H -#define HPM_FEMC_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t IOCTRL; /* 0x4: IO Mux Control Register */ - __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ - __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ - __RW uint32_t BR[7]; /* 0x10 - 0x28: Base Register 0 (for SDRAM CS0 device) */ - __R uint8_t RESERVED0[12]; /* 0x2C - 0x37: Reserved */ - __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ - __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ - __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ - __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ - __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ - __R uint8_t RESERVED1[32]; /* 0x50 - 0x6F: Reserved */ - __RW uint32_t SRCTRL0; /* 0x70: SRAM control register 0 */ - __RW uint32_t SRCTRL1; /* 0x74: SRAM control register 1 */ - __R uint8_t RESERVED2[24]; /* 0x78 - 0x8F: Reserved */ - __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ - __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ - __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ - __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ - __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ - __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ - __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ - __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ - __R uint32_t STAT0; /* 0xC0: Status Register 0 */ - __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ - __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ -} FEMC_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * BTO (RW) - * - * Bus timeout cycles - * AXI Bus timeout cycle is as following (255*(2^BTO)): - * 00000b - 255*1 - * 00001-11110b - 255*2 - 255*2^30 - * 11111b - 255*2^31 - */ -#define FEMC_CTRL_BTO_MASK (0x1F000000UL) -#define FEMC_CTRL_BTO_SHIFT (24U) -#define FEMC_CTRL_BTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_BTO_SHIFT) & FEMC_CTRL_BTO_MASK) -#define FEMC_CTRL_BTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_BTO_MASK) >> FEMC_CTRL_BTO_SHIFT) - -/* - * CTO (RW) - * - * Command Execution timeout cycles - * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is - * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is - * CTO*1024 cycle. - */ -#define FEMC_CTRL_CTO_MASK (0xFF0000UL) -#define FEMC_CTRL_CTO_SHIFT (16U) -#define FEMC_CTRL_CTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_CTO_SHIFT) & FEMC_CTRL_CTO_MASK) -#define FEMC_CTRL_CTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_CTO_MASK) >> FEMC_CTRL_CTO_SHIFT) - -/* - * DQS (RW) - * - * DQS (read strobe) mode - * 0b - Dummy read strobe loopbacked internally - * 1b - Dummy read strobe loopbacked from DQS pad - */ -#define FEMC_CTRL_DQS_MASK (0x4U) -#define FEMC_CTRL_DQS_SHIFT (2U) -#define FEMC_CTRL_DQS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DQS_SHIFT) & FEMC_CTRL_DQS_MASK) -#define FEMC_CTRL_DQS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DQS_MASK) >> FEMC_CTRL_DQS_SHIFT) - -/* - * DIS (RW) - * - * Module Disable - * 0b - Module enabled - * 1b - Module disabled - */ -#define FEMC_CTRL_DIS_MASK (0x2U) -#define FEMC_CTRL_DIS_SHIFT (1U) -#define FEMC_CTRL_DIS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DIS_SHIFT) & FEMC_CTRL_DIS_MASK) -#define FEMC_CTRL_DIS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DIS_MASK) >> FEMC_CTRL_DIS_SHIFT) - -/* - * RST (RW) - * - * Software Reset - * Reset all internal logic in SEMC except configuration register - */ -#define FEMC_CTRL_RST_MASK (0x1U) -#define FEMC_CTRL_RST_SHIFT (0U) -#define FEMC_CTRL_RST_SET(x) (((uint32_t)(x) << FEMC_CTRL_RST_SHIFT) & FEMC_CTRL_RST_MASK) -#define FEMC_CTRL_RST_GET(x) (((uint32_t)(x) & FEMC_CTRL_RST_MASK) >> FEMC_CTRL_RST_SHIFT) - -/* Bitfield definition for register: IOCTRL */ -/* - * IO_CSX (RW) - * - * IO_CSX output selection - * 0001b - SDRAM CS1 - * 0110b - SRAM CE# - */ -#define FEMC_IOCTRL_IO_CSX_MASK (0xF0U) -#define FEMC_IOCTRL_IO_CSX_SHIFT (4U) -#define FEMC_IOCTRL_IO_CSX_SET(x) (((uint32_t)(x) << FEMC_IOCTRL_IO_CSX_SHIFT) & FEMC_IOCTRL_IO_CSX_MASK) -#define FEMC_IOCTRL_IO_CSX_GET(x) (((uint32_t)(x) & FEMC_IOCTRL_IO_CSX_MASK) >> FEMC_IOCTRL_IO_CSX_SHIFT) - -/* Bitfield definition for register: BMW0 */ -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define FEMC_BMW0_RWS_MASK (0xFF0000UL) -#define FEMC_BMW0_RWS_SHIFT (16U) -#define FEMC_BMW0_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW0_RWS_SHIFT) & FEMC_BMW0_RWS_MASK) -#define FEMC_BMW0_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW0_RWS_MASK) >> FEMC_BMW0_RWS_SHIFT) - -/* - * SH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define FEMC_BMW0_SH_MASK (0xFF00U) -#define FEMC_BMW0_SH_SHIFT (8U) -#define FEMC_BMW0_SH_SET(x) (((uint32_t)(x) << FEMC_BMW0_SH_SHIFT) & FEMC_BMW0_SH_MASK) -#define FEMC_BMW0_SH_GET(x) (((uint32_t)(x) & FEMC_BMW0_SH_MASK) >> FEMC_BMW0_SH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define FEMC_BMW0_AGE_MASK (0xF0U) -#define FEMC_BMW0_AGE_SHIFT (4U) -#define FEMC_BMW0_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW0_AGE_SHIFT) & FEMC_BMW0_AGE_MASK) -#define FEMC_BMW0_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW0_AGE_MASK) >> FEMC_BMW0_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define FEMC_BMW0_QOS_MASK (0xFU) -#define FEMC_BMW0_QOS_SHIFT (0U) -#define FEMC_BMW0_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW0_QOS_SHIFT) & FEMC_BMW0_QOS_MASK) -#define FEMC_BMW0_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW0_QOS_MASK) >> FEMC_BMW0_QOS_SHIFT) - -/* Bitfield definition for register: BMW1 */ -/* - * BR (RW) - * - * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current - * executing command. - */ -#define FEMC_BMW1_BR_MASK (0xFF000000UL) -#define FEMC_BMW1_BR_SHIFT (24U) -#define FEMC_BMW1_BR_SET(x) (((uint32_t)(x) << FEMC_BMW1_BR_SHIFT) & FEMC_BMW1_BR_MASK) -#define FEMC_BMW1_BR_GET(x) (((uint32_t)(x) & FEMC_BMW1_BR_MASK) >> FEMC_BMW1_BR_SHIFT) - -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define FEMC_BMW1_RWS_MASK (0xFF0000UL) -#define FEMC_BMW1_RWS_SHIFT (16U) -#define FEMC_BMW1_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW1_RWS_SHIFT) & FEMC_BMW1_RWS_MASK) -#define FEMC_BMW1_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW1_RWS_MASK) >> FEMC_BMW1_RWS_SHIFT) - -/* - * PH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define FEMC_BMW1_PH_MASK (0xFF00U) -#define FEMC_BMW1_PH_SHIFT (8U) -#define FEMC_BMW1_PH_SET(x) (((uint32_t)(x) << FEMC_BMW1_PH_SHIFT) & FEMC_BMW1_PH_MASK) -#define FEMC_BMW1_PH_GET(x) (((uint32_t)(x) & FEMC_BMW1_PH_MASK) >> FEMC_BMW1_PH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define FEMC_BMW1_AGE_MASK (0xF0U) -#define FEMC_BMW1_AGE_SHIFT (4U) -#define FEMC_BMW1_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW1_AGE_SHIFT) & FEMC_BMW1_AGE_MASK) -#define FEMC_BMW1_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW1_AGE_MASK) >> FEMC_BMW1_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define FEMC_BMW1_QOS_MASK (0xFU) -#define FEMC_BMW1_QOS_SHIFT (0U) -#define FEMC_BMW1_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW1_QOS_SHIFT) & FEMC_BMW1_QOS_MASK) -#define FEMC_BMW1_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW1_QOS_MASK) >> FEMC_BMW1_QOS_SHIFT) - -/* Bitfield definition for register array: BR */ -/* - * BASE (RW) - * - * Base Address - * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low - * position 12 bits are all zero. - */ -#define FEMC_BR_BASE_MASK (0xFFFFF000UL) -#define FEMC_BR_BASE_SHIFT (12U) -#define FEMC_BR_BASE_SET(x) (((uint32_t)(x) << FEMC_BR_BASE_SHIFT) & FEMC_BR_BASE_MASK) -#define FEMC_BR_BASE_GET(x) (((uint32_t)(x) & FEMC_BR_BASE_MASK) >> FEMC_BR_BASE_SHIFT) - -/* - * SIZE (RW) - * - * Memory size - * 00000b - 4KB - * 00001b - 8KB - * 00010b - 16KB - * 00011b - 32KB - * 00100b - 64KB - * 00101b - 128KB - * 00110b - 256KB - * 00111b - 512KB - * 01000b - 1MB - * 01001b - 2MB - * 01010b - 4MB - * 01011b - 8MB - * 01100b - 16MB - * 01101b - 32MB - * 01110b - 64MB - * 01111b - 128MB - * 10000b - 256MB - * 10001b - 512MB - * 10010b - 1GB - * 10011b - 2GB - * 10100-11111b - 4GB - */ -#define FEMC_BR_SIZE_MASK (0x3EU) -#define FEMC_BR_SIZE_SHIFT (1U) -#define FEMC_BR_SIZE_SET(x) (((uint32_t)(x) << FEMC_BR_SIZE_SHIFT) & FEMC_BR_SIZE_MASK) -#define FEMC_BR_SIZE_GET(x) (((uint32_t)(x) & FEMC_BR_SIZE_MASK) >> FEMC_BR_SIZE_SHIFT) - -/* - * VLD (RW) - * - * Valid - */ -#define FEMC_BR_VLD_MASK (0x1U) -#define FEMC_BR_VLD_SHIFT (0U) -#define FEMC_BR_VLD_SET(x) (((uint32_t)(x) << FEMC_BR_VLD_SHIFT) & FEMC_BR_VLD_MASK) -#define FEMC_BR_VLD_GET(x) (((uint32_t)(x) & FEMC_BR_VLD_MASK) >> FEMC_BR_VLD_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * AXIBUSERR (RW) - * - * AXI BUS error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_AXIBUSERR_MASK (0x8U) -#define FEMC_INTEN_AXIBUSERR_SHIFT (3U) -#define FEMC_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXIBUSERR_SHIFT) & FEMC_INTEN_AXIBUSERR_MASK) -#define FEMC_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXIBUSERR_MASK) >> FEMC_INTEN_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (RW) - * - * AXI command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_AXICMDERR_MASK (0x4U) -#define FEMC_INTEN_AXICMDERR_SHIFT (2U) -#define FEMC_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXICMDERR_SHIFT) & FEMC_INTEN_AXICMDERR_MASK) -#define FEMC_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXICMDERR_MASK) >> FEMC_INTEN_AXICMDERR_SHIFT) - -/* - * IPCMDERR (RW) - * - * IP command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_IPCMDERR_MASK (0x2U) -#define FEMC_INTEN_IPCMDERR_SHIFT (1U) -#define FEMC_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDERR_SHIFT) & FEMC_INTEN_IPCMDERR_MASK) -#define FEMC_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDERR_MASK) >> FEMC_INTEN_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (RW) - * - * IP command done interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_IPCMDDONE_MASK (0x1U) -#define FEMC_INTEN_IPCMDDONE_SHIFT (0U) -#define FEMC_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDDONE_SHIFT) & FEMC_INTEN_IPCMDDONE_MASK) -#define FEMC_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDDONE_MASK) >> FEMC_INTEN_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: INTR */ -/* - * AXIBUSERR (W1C) - * - * AXI bus error interrupt - * AXI Bus error interrupt is generated in following cases: - * • AXI address is invalid - * • AXI 8-bit or 16-bit WRAP write/read - */ -#define FEMC_INTR_AXIBUSERR_MASK (0x8U) -#define FEMC_INTR_AXIBUSERR_SHIFT (3U) -#define FEMC_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXIBUSERR_SHIFT) & FEMC_INTR_AXIBUSERR_MASK) -#define FEMC_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXIBUSERR_MASK) >> FEMC_INTR_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (W1C) - * - * AXI command error interrupt - * AXI command error interrupt is generated when AXI command execution timeout. - */ -#define FEMC_INTR_AXICMDERR_MASK (0x4U) -#define FEMC_INTR_AXICMDERR_SHIFT (2U) -#define FEMC_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXICMDERR_SHIFT) & FEMC_INTR_AXICMDERR_MASK) -#define FEMC_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXICMDERR_MASK) >> FEMC_INTR_AXICMDERR_SHIFT) - -/* - * IPCMDERR (W1C) - * - * IP command error done interrupt - * IP command error interrupt is generated in following case: - * • IP Command Address target invalid device space - * • IP Command Code unsupported - * • IP Command triggered when previous command - */ -#define FEMC_INTR_IPCMDERR_MASK (0x2U) -#define FEMC_INTR_IPCMDERR_SHIFT (1U) -#define FEMC_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDERR_SHIFT) & FEMC_INTR_IPCMDERR_MASK) -#define FEMC_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDERR_MASK) >> FEMC_INTR_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (W1C) - * - * IP command normal done interrupt - */ -#define FEMC_INTR_IPCMDDONE_MASK (0x1U) -#define FEMC_INTR_IPCMDDONE_SHIFT (0U) -#define FEMC_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDDONE_SHIFT) & FEMC_INTR_IPCMDDONE_MASK) -#define FEMC_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDDONE_MASK) >> FEMC_INTR_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: SDRCTRL0 */ -/* - * BANK2 (RW) - * - * 2 Bank selection bit - * 0b - SDRAM device has 4 banks. - * 1b - SDRAM device has 2 banks. - */ -#define FEMC_SDRCTRL0_BANK2_MASK (0x4000U) -#define FEMC_SDRCTRL0_BANK2_SHIFT (14U) -#define FEMC_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BANK2_SHIFT) & FEMC_SDRCTRL0_BANK2_MASK) -#define FEMC_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BANK2_MASK) >> FEMC_SDRCTRL0_BANK2_SHIFT) - -/* - * CAS (RW) - * - * CAS Latency - * 00b - 1 - * 01b - 1 - * 10b - 2 - * 11b - 3 - */ -#define FEMC_SDRCTRL0_CAS_MASK (0xC00U) -#define FEMC_SDRCTRL0_CAS_SHIFT (10U) -#define FEMC_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_CAS_SHIFT) & FEMC_SDRCTRL0_CAS_MASK) -#define FEMC_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_CAS_MASK) >> FEMC_SDRCTRL0_CAS_SHIFT) - -/* - * COL (RW) - * - * Column address bit number - * 00b - 12 bit - * 01b - 11 bit - * 10b - 10 bit - * 11b - 9 bit - */ -#define FEMC_SDRCTRL0_COL_MASK (0x300U) -#define FEMC_SDRCTRL0_COL_SHIFT (8U) -#define FEMC_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL_SHIFT) & FEMC_SDRCTRL0_COL_MASK) -#define FEMC_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL_MASK) >> FEMC_SDRCTRL0_COL_SHIFT) - -/* - * COL8 (RW) - * - * Column 8 selection bit - * 0b - Column address bit number is decided by COL field. - * 1b - Column address bit number is 8. COL field is ignored. - */ -#define FEMC_SDRCTRL0_COL8_MASK (0x80U) -#define FEMC_SDRCTRL0_COL8_SHIFT (7U) -#define FEMC_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL8_SHIFT) & FEMC_SDRCTRL0_COL8_MASK) -#define FEMC_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL8_MASK) >> FEMC_SDRCTRL0_COL8_SHIFT) - -/* - * BURSTLEN (RW) - * - * Burst Length - * 000b - 1 - * 001b - 2 - * 010b - 4 - * 011b - 8 - * 100b - 8 - * 101b - 8 - * 110b - 8 - * 111b - 8 - */ -#define FEMC_SDRCTRL0_BURSTLEN_MASK (0x70U) -#define FEMC_SDRCTRL0_BURSTLEN_SHIFT (4U) -#define FEMC_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BURSTLEN_SHIFT) & FEMC_SDRCTRL0_BURSTLEN_MASK) -#define FEMC_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BURSTLEN_MASK) >> FEMC_SDRCTRL0_BURSTLEN_SHIFT) - -/* - * HIGHBAND (RW) - * - * high band select - * 0: use data[15:0] for 16bit SDRAM; - * 1: use data[31:16] for 16bit SDRAM; - * only used when Port Size is 16bit(PORTSZ=01b) - */ -#define FEMC_SDRCTRL0_HIGHBAND_MASK (0x8U) -#define FEMC_SDRCTRL0_HIGHBAND_SHIFT (3U) -#define FEMC_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_HIGHBAND_SHIFT) & FEMC_SDRCTRL0_HIGHBAND_MASK) -#define FEMC_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_HIGHBAND_MASK) >> FEMC_SDRCTRL0_HIGHBAND_SHIFT) - -/* - * PORTSZ (RW) - * - * Port Size - * 00b - 8bit - * 01b - 16bit - * 10b - 32bit - */ -#define FEMC_SDRCTRL0_PORTSZ_MASK (0x3U) -#define FEMC_SDRCTRL0_PORTSZ_SHIFT (0U) -#define FEMC_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_PORTSZ_SHIFT) & FEMC_SDRCTRL0_PORTSZ_MASK) -#define FEMC_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_PORTSZ_MASK) >> FEMC_SDRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SDRCTRL1 */ -/* - * ACT2PRE (RW) - * - * ACT to Precharge minimum time - * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - */ -#define FEMC_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) -#define FEMC_SDRCTRL1_ACT2PRE_SHIFT (20U) -#define FEMC_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2PRE_SHIFT) & FEMC_SDRCTRL1_ACT2PRE_MASK) -#define FEMC_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2PRE_MASK) >> FEMC_SDRCTRL1_ACT2PRE_SHIFT) - -/* - * CKEOFF (RW) - * - * CKE OFF minimum time - * It is promised clock suspend last at leat CKEOFF+1 clock cycles. - */ -#define FEMC_SDRCTRL1_CKEOFF_MASK (0xF0000UL) -#define FEMC_SDRCTRL1_CKEOFF_SHIFT (16U) -#define FEMC_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_CKEOFF_SHIFT) & FEMC_SDRCTRL1_CKEOFF_MASK) -#define FEMC_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_CKEOFF_MASK) >> FEMC_SDRCTRL1_CKEOFF_SHIFT) - -/* - * WRC (RW) - * - * Write recovery time - * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_WRC_MASK (0xE000U) -#define FEMC_SDRCTRL1_WRC_SHIFT (13U) -#define FEMC_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_WRC_SHIFT) & FEMC_SDRCTRL1_WRC_MASK) -#define FEMC_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_WRC_MASK) >> FEMC_SDRCTRL1_WRC_SHIFT) - -/* - * RFRC (RW) - * - * Refresh recovery time - * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_RFRC_MASK (0x1F00U) -#define FEMC_SDRCTRL1_RFRC_SHIFT (8U) -#define FEMC_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_RFRC_SHIFT) & FEMC_SDRCTRL1_RFRC_MASK) -#define FEMC_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_RFRC_MASK) >> FEMC_SDRCTRL1_RFRC_SHIFT) - -/* - * ACT2RW (RW) - * - * ACT to Read/Write wait time - * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_ACT2RW_MASK (0xF0U) -#define FEMC_SDRCTRL1_ACT2RW_SHIFT (4U) -#define FEMC_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2RW_SHIFT) & FEMC_SDRCTRL1_ACT2RW_MASK) -#define FEMC_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2RW_MASK) >> FEMC_SDRCTRL1_ACT2RW_SHIFT) - -/* - * PRE2ACT (RW) - * - * PRECHARGE to ACT/Refresh wait time - * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_PRE2ACT_MASK (0xFU) -#define FEMC_SDRCTRL1_PRE2ACT_SHIFT (0U) -#define FEMC_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_PRE2ACT_SHIFT) & FEMC_SDRCTRL1_PRE2ACT_MASK) -#define FEMC_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_PRE2ACT_MASK) >> FEMC_SDRCTRL1_PRE2ACT_SHIFT) - -/* Bitfield definition for register: SDRCTRL2 */ -/* - * ITO (RW) - * - * SDRAM Idle timeout - * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is - * considered idle when there is no AXI Bus transfer and no SDRAM command pending. - * 00000000b - IDLE timeout period is 256*Prescale period. - * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. - */ -#define FEMC_SDRCTRL2_ITO_MASK (0xFF000000UL) -#define FEMC_SDRCTRL2_ITO_SHIFT (24U) -#define FEMC_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ITO_SHIFT) & FEMC_SDRCTRL2_ITO_MASK) -#define FEMC_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ITO_MASK) >> FEMC_SDRCTRL2_ITO_SHIFT) - -/* - * ACT2ACT (RW) - * - * ACT to ACT wait time - * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This - * could help to meet tRRD timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) -#define FEMC_SDRCTRL2_ACT2ACT_SHIFT (16U) -#define FEMC_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ACT2ACT_SHIFT) & FEMC_SDRCTRL2_ACT2ACT_MASK) -#define FEMC_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ACT2ACT_MASK) >> FEMC_SDRCTRL2_ACT2ACT_SHIFT) - -/* - * REF2REF (RW) - * - * Refresh to Refresh wait time - * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. - * This could help to meet tRFC timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL2_REF2REF_MASK (0xFF00U) -#define FEMC_SDRCTRL2_REF2REF_SHIFT (8U) -#define FEMC_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_REF2REF_SHIFT) & FEMC_SDRCTRL2_REF2REF_MASK) -#define FEMC_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_REF2REF_MASK) >> FEMC_SDRCTRL2_REF2REF_SHIFT) - -/* - * SRRC (RW) - * - * Self Refresh Recovery time - * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - */ -#define FEMC_SDRCTRL2_SRRC_MASK (0xFFU) -#define FEMC_SDRCTRL2_SRRC_SHIFT (0U) -#define FEMC_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_SRRC_SHIFT) & FEMC_SDRCTRL2_SRRC_MASK) -#define FEMC_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_SRRC_MASK) >> FEMC_SDRCTRL2_SRRC_SHIFT) - -/* Bitfield definition for register: SDRCTRL3 */ -/* - * UT (RW) - * - * Refresh urgent threshold - * Internal refresh request is generated on every Refresh period. Before internal request timer count up to - * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh - * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. - * When internal request timer count up to this urgent threshold, refresh request is considered as urgent - * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP - * command to SDRAM device. - * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as - * urgent refresh request. - * Refresh urgent threshold is as follwoing: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - UT*Prescaler period - */ -#define FEMC_SDRCTRL3_UT_MASK (0xFF000000UL) -#define FEMC_SDRCTRL3_UT_SHIFT (24U) -#define FEMC_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_UT_SHIFT) & FEMC_SDRCTRL3_UT_MASK) -#define FEMC_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_UT_MASK) >> FEMC_SDRCTRL3_UT_SHIFT) - -/* - * RT (RW) - * - * Refresh timer period - * Refresh timer period is as following: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - RT*Prescaler period - */ -#define FEMC_SDRCTRL3_RT_MASK (0xFF0000UL) -#define FEMC_SDRCTRL3_RT_SHIFT (16U) -#define FEMC_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_RT_SHIFT) & FEMC_SDRCTRL3_RT_MASK) -#define FEMC_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_RT_MASK) >> FEMC_SDRCTRL3_RT_SHIFT) - -/* - * PRESCALE (RW) - * - * Prescaler timer period - * Prescaler timer period is as following: - * 00000000b - 256*16 clock cycles - * 00000001-11111111b - PRESCALE*16 clock cycles - */ -#define FEMC_SDRCTRL3_PRESCALE_MASK (0xFF00U) -#define FEMC_SDRCTRL3_PRESCALE_SHIFT (8U) -#define FEMC_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_PRESCALE_SHIFT) & FEMC_SDRCTRL3_PRESCALE_MASK) -#define FEMC_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_PRESCALE_MASK) >> FEMC_SDRCTRL3_PRESCALE_SHIFT) - -/* - * REBL (RW) - * - * Refresh burst length - * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The - * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. - * 000b - 1 - * 001b - 2 - * 010b - 3 - * 011b - 4 - * 100b - 5 - * 101b - 6 - * 110b - 7 - * 111b - 8 - */ -#define FEMC_SDRCTRL3_REBL_MASK (0xEU) -#define FEMC_SDRCTRL3_REBL_SHIFT (1U) -#define FEMC_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REBL_SHIFT) & FEMC_SDRCTRL3_REBL_MASK) -#define FEMC_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REBL_MASK) >> FEMC_SDRCTRL3_REBL_SHIFT) - -/* - * REN (RW) - * - * Refresh enable - */ -#define FEMC_SDRCTRL3_REN_MASK (0x1U) -#define FEMC_SDRCTRL3_REN_SHIFT (0U) -#define FEMC_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REN_SHIFT) & FEMC_SDRCTRL3_REN_MASK) -#define FEMC_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REN_MASK) >> FEMC_SDRCTRL3_REN_SHIFT) - -/* Bitfield definition for register: SRCTRL0 */ -/* - * ADVH (RW) - * - * ADV hold state - * 0b - ADV is high during address hold state - * 1b - ADV is low during address hold state - */ -#define FEMC_SRCTRL0_ADVH_MASK (0x800U) -#define FEMC_SRCTRL0_ADVH_SHIFT (11U) -#define FEMC_SRCTRL0_ADVH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVH_SHIFT) & FEMC_SRCTRL0_ADVH_MASK) -#define FEMC_SRCTRL0_ADVH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVH_MASK) >> FEMC_SRCTRL0_ADVH_SHIFT) - -/* - * ADVP (RW) - * - * ADV polarity - * 0b - ADV is active low - * 1b - ADV is active high - */ -#define FEMC_SRCTRL0_ADVP_MASK (0x400U) -#define FEMC_SRCTRL0_ADVP_SHIFT (10U) -#define FEMC_SRCTRL0_ADVP_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVP_SHIFT) & FEMC_SRCTRL0_ADVP_MASK) -#define FEMC_SRCTRL0_ADVP_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVP_MASK) >> FEMC_SRCTRL0_ADVP_SHIFT) - -/* - * ADM (RW) - * - * address data mode - * 00b - address and data MUX mode - * 11b - address and data non-MUX mode - */ -#define FEMC_SRCTRL0_ADM_MASK (0x300U) -#define FEMC_SRCTRL0_ADM_SHIFT (8U) -#define FEMC_SRCTRL0_ADM_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADM_SHIFT) & FEMC_SRCTRL0_ADM_MASK) -#define FEMC_SRCTRL0_ADM_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADM_MASK) >> FEMC_SRCTRL0_ADM_SHIFT) - -/* - * PORTSZ (RW) - * - * port size - * 0b - 8bit - * 1b - 16bit - */ -#define FEMC_SRCTRL0_PORTSZ_MASK (0x1U) -#define FEMC_SRCTRL0_PORTSZ_SHIFT (0U) -#define FEMC_SRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_PORTSZ_SHIFT) & FEMC_SRCTRL0_PORTSZ_MASK) -#define FEMC_SRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_PORTSZ_MASK) >> FEMC_SRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SRCTRL1 */ -/* - * OEH (RW) - * - * OE high time, is OEH+1 clock cycles - */ -#define FEMC_SRCTRL1_OEH_MASK (0xF0000000UL) -#define FEMC_SRCTRL1_OEH_SHIFT (28U) -#define FEMC_SRCTRL1_OEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEH_SHIFT) & FEMC_SRCTRL1_OEH_MASK) -#define FEMC_SRCTRL1_OEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEH_MASK) >> FEMC_SRCTRL1_OEH_SHIFT) - -/* - * OEL (RW) - * - * OE low time, is OEL+1 clock cycles - */ -#define FEMC_SRCTRL1_OEL_MASK (0xF000000UL) -#define FEMC_SRCTRL1_OEL_SHIFT (24U) -#define FEMC_SRCTRL1_OEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEL_SHIFT) & FEMC_SRCTRL1_OEL_MASK) -#define FEMC_SRCTRL1_OEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEL_MASK) >> FEMC_SRCTRL1_OEL_SHIFT) - -/* - * WEH (RW) - * - * WE high time, is WEH+1 clock cycles - */ -#define FEMC_SRCTRL1_WEH_MASK (0xF00000UL) -#define FEMC_SRCTRL1_WEH_SHIFT (20U) -#define FEMC_SRCTRL1_WEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEH_SHIFT) & FEMC_SRCTRL1_WEH_MASK) -#define FEMC_SRCTRL1_WEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEH_MASK) >> FEMC_SRCTRL1_WEH_SHIFT) - -/* - * WEL (RW) - * - * WE low time, is WEL+1 clock cycles - */ -#define FEMC_SRCTRL1_WEL_MASK (0xF0000UL) -#define FEMC_SRCTRL1_WEL_SHIFT (16U) -#define FEMC_SRCTRL1_WEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEL_SHIFT) & FEMC_SRCTRL1_WEL_MASK) -#define FEMC_SRCTRL1_WEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEL_MASK) >> FEMC_SRCTRL1_WEL_SHIFT) - -/* - * AH (RW) - * - * Address hold time, is AH+1 clock cycles - */ -#define FEMC_SRCTRL1_AH_MASK (0xF000U) -#define FEMC_SRCTRL1_AH_SHIFT (12U) -#define FEMC_SRCTRL1_AH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AH_SHIFT) & FEMC_SRCTRL1_AH_MASK) -#define FEMC_SRCTRL1_AH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AH_MASK) >> FEMC_SRCTRL1_AH_SHIFT) - -/* - * AS (RW) - * - * Address setup time, is AS+1 clock cycles - */ -#define FEMC_SRCTRL1_AS_MASK (0xF00U) -#define FEMC_SRCTRL1_AS_SHIFT (8U) -#define FEMC_SRCTRL1_AS_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AS_SHIFT) & FEMC_SRCTRL1_AS_MASK) -#define FEMC_SRCTRL1_AS_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AS_MASK) >> FEMC_SRCTRL1_AS_SHIFT) - -/* - * CEH (RW) - * - * Chip enable hold time, is CEH+1 clock cycles - */ -#define FEMC_SRCTRL1_CEH_MASK (0xF0U) -#define FEMC_SRCTRL1_CEH_SHIFT (4U) -#define FEMC_SRCTRL1_CEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CEH_SHIFT) & FEMC_SRCTRL1_CEH_MASK) -#define FEMC_SRCTRL1_CEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CEH_MASK) >> FEMC_SRCTRL1_CEH_SHIFT) - -/* - * CES (RW) - * - * Chip enable setup time, is CES+1 clock cycles - */ -#define FEMC_SRCTRL1_CES_MASK (0xFU) -#define FEMC_SRCTRL1_CES_SHIFT (0U) -#define FEMC_SRCTRL1_CES_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CES_SHIFT) & FEMC_SRCTRL1_CES_MASK) -#define FEMC_SRCTRL1_CES_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CES_MASK) >> FEMC_SRCTRL1_CES_SHIFT) - -/* Bitfield definition for register: SADDR */ -/* - * SA (RW) - * - * Slave address - */ -#define FEMC_SADDR_SA_MASK (0xFFFFFFFFUL) -#define FEMC_SADDR_SA_SHIFT (0U) -#define FEMC_SADDR_SA_SET(x) (((uint32_t)(x) << FEMC_SADDR_SA_SHIFT) & FEMC_SADDR_SA_MASK) -#define FEMC_SADDR_SA_GET(x) (((uint32_t)(x) & FEMC_SADDR_SA_MASK) >> FEMC_SADDR_SA_SHIFT) - -/* Bitfield definition for register: DATSZ */ -/* - * DATSZ (RW) - * - * Data Size in Byte - * When IP command is not a write/read operation, DATSZ field would be ignored. - * 000b - 4 - * 001b - 1 - * 010b - 2 - * 011b - 3 - * 100b - 4 - * 101b - 4 - * 110b - 4 - * 111b - 4 - */ -#define FEMC_DATSZ_DATSZ_MASK (0x7U) -#define FEMC_DATSZ_DATSZ_SHIFT (0U) -#define FEMC_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << FEMC_DATSZ_DATSZ_SHIFT) & FEMC_DATSZ_DATSZ_MASK) -#define FEMC_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & FEMC_DATSZ_DATSZ_MASK) >> FEMC_DATSZ_DATSZ_SHIFT) - -/* Bitfield definition for register: BYTEMSK */ -/* - * BM3 (RW) - * - * Byte Mask for Byte 3 (IPTXD bit 31:24) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM3_MASK (0x8U) -#define FEMC_BYTEMSK_BM3_SHIFT (3U) -#define FEMC_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM3_SHIFT) & FEMC_BYTEMSK_BM3_MASK) -#define FEMC_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM3_MASK) >> FEMC_BYTEMSK_BM3_SHIFT) - -/* - * BM2 (RW) - * - * Byte Mask for Byte 2 (IPTXD bit 23:16) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM2_MASK (0x4U) -#define FEMC_BYTEMSK_BM2_SHIFT (2U) -#define FEMC_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM2_SHIFT) & FEMC_BYTEMSK_BM2_MASK) -#define FEMC_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM2_MASK) >> FEMC_BYTEMSK_BM2_SHIFT) - -/* - * BM1 (RW) - * - * Byte Mask for Byte 1 (IPTXD bit 15:8) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM1_MASK (0x2U) -#define FEMC_BYTEMSK_BM1_SHIFT (1U) -#define FEMC_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM1_SHIFT) & FEMC_BYTEMSK_BM1_MASK) -#define FEMC_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM1_MASK) >> FEMC_BYTEMSK_BM1_SHIFT) - -/* - * BM0 (RW) - * - * Byte Mask for Byte 0 (IPTXD bit 7:0) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM0_MASK (0x1U) -#define FEMC_BYTEMSK_BM0_SHIFT (0U) -#define FEMC_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM0_SHIFT) & FEMC_BYTEMSK_BM0_MASK) -#define FEMC_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM0_MASK) >> FEMC_BYTEMSK_BM0_SHIFT) - -/* Bitfield definition for register: IPCMD */ -/* - * KEY (WO) - * - * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory - * device is selected by BRx settings and IPCR0 registers. - */ -#define FEMC_IPCMD_KEY_MASK (0xFFFF0000UL) -#define FEMC_IPCMD_KEY_SHIFT (16U) -#define FEMC_IPCMD_KEY_SET(x) (((uint32_t)(x) << FEMC_IPCMD_KEY_SHIFT) & FEMC_IPCMD_KEY_MASK) -#define FEMC_IPCMD_KEY_GET(x) (((uint32_t)(x) & FEMC_IPCMD_KEY_MASK) >> FEMC_IPCMD_KEY_SHIFT) - -/* - * CMD (RW) - * - * SDRAM Commands: - * • 0x8: READ - * • 0x9: WRITE - * • 0xA: MODESET - * • 0xB: ACTIVE - * • 0xC: AUTO REFRESH - * • 0xD: SELF REFRESH - * • 0xE: PRECHARGE - * • 0xF: PRECHARGE ALL - * • Others: RSVD - * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - */ -#define FEMC_IPCMD_CMD_MASK (0xFFFFU) -#define FEMC_IPCMD_CMD_SHIFT (0U) -#define FEMC_IPCMD_CMD_SET(x) (((uint32_t)(x) << FEMC_IPCMD_CMD_SHIFT) & FEMC_IPCMD_CMD_MASK) -#define FEMC_IPCMD_CMD_GET(x) (((uint32_t)(x) & FEMC_IPCMD_CMD_MASK) >> FEMC_IPCMD_CMD_SHIFT) - -/* Bitfield definition for register: IPTX */ -/* - * DAT (RW) - * - * Data - */ -#define FEMC_IPTX_DAT_MASK (0xFFFFFFFFUL) -#define FEMC_IPTX_DAT_SHIFT (0U) -#define FEMC_IPTX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPTX_DAT_SHIFT) & FEMC_IPTX_DAT_MASK) -#define FEMC_IPTX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPTX_DAT_MASK) >> FEMC_IPTX_DAT_SHIFT) - -/* Bitfield definition for register: IPRX */ -/* - * DAT (RW) - * - * Data - */ -#define FEMC_IPRX_DAT_MASK (0xFFFFFFFFUL) -#define FEMC_IPRX_DAT_SHIFT (0U) -#define FEMC_IPRX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPRX_DAT_SHIFT) & FEMC_IPRX_DAT_MASK) -#define FEMC_IPRX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPRX_DAT_MASK) >> FEMC_IPRX_DAT_SHIFT) - -/* Bitfield definition for register: STAT0 */ -/* - * IDLE (RO) - * - * Indicating whether it is in IDLE state. - * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no - * pending device access. - */ -#define FEMC_STAT0_IDLE_MASK (0x1U) -#define FEMC_STAT0_IDLE_SHIFT (0U) -#define FEMC_STAT0_IDLE_GET(x) (((uint32_t)(x) & FEMC_STAT0_IDLE_MASK) >> FEMC_STAT0_IDLE_SHIFT) - -/* Bitfield definition for register: DLYCFG */ -/* - * OE (RW) - * - * delay clock output enable, should be set after setting DLYEN and DLYSEL - */ -#define FEMC_DLYCFG_OE_MASK (0x2000U) -#define FEMC_DLYCFG_OE_SHIFT (13U) -#define FEMC_DLYCFG_OE_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_OE_SHIFT) & FEMC_DLYCFG_OE_MASK) -#define FEMC_DLYCFG_OE_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_OE_MASK) >> FEMC_DLYCFG_OE_SHIFT) - -/* - * DLYSEL (RW) - * - * delay line select, 0 for 1 cell, 31 for all 32 cells - */ -#define FEMC_DLYCFG_DLYSEL_MASK (0x3EU) -#define FEMC_DLYCFG_DLYSEL_SHIFT (1U) -#define FEMC_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYSEL_SHIFT) & FEMC_DLYCFG_DLYSEL_MASK) -#define FEMC_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYSEL_MASK) >> FEMC_DLYCFG_DLYSEL_SHIFT) - -/* - * DLYEN (RW) - * - * delay line enable - */ -#define FEMC_DLYCFG_DLYEN_MASK (0x1U) -#define FEMC_DLYCFG_DLYEN_SHIFT (0U) -#define FEMC_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYEN_SHIFT) & FEMC_DLYCFG_DLYEN_MASK) -#define FEMC_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYEN_MASK) >> FEMC_DLYCFG_DLYEN_SHIFT) - - - -/* BR register group index macro definition */ -#define FEMC_BR_BASE0 (0UL) -#define FEMC_BR_BASE1 (1UL) -#define FEMC_BR_BASE6 (6UL) - - -#endif /* HPM_FEMC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ffa_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ffa_regs.h deleted file mode 100644 index 432aab85c2c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ffa_regs.h +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_FFA_H -#define HPM_FFA_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: */ - __RW uint32_t STATUS; /* 0x4: */ - __RW uint32_t INT_EN; /* 0x8: */ - __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ - __RW uint32_t OP_CTRL; /* 0x20: */ - __RW uint32_t OP_CMD; /* 0x24: */ - union { - __RW uint32_t OP_REG0; /* 0x28: */ - __RW uint32_t OP_FIR_MISC; /* 0x28: */ - __RW uint32_t OP_FFT_MISC; /* 0x28: */ - }; - union { - __RW uint32_t OP_REG1; /* 0x2C: */ - __RW uint32_t OP_FIR_MISC1; /* 0x2C: */ - }; - union { - __RW uint32_t OP_REG2; /* 0x30: */ - __RW uint32_t OP_FFT_INRBUF; /* 0x30: */ - }; - union { - __RW uint32_t OP_REG3; /* 0x34: */ - __RW uint32_t OP_FIR_INBUF; /* 0x34: */ - }; - union { - __RW uint32_t OP_REG4; /* 0x38: */ - __RW uint32_t OP_FIR_COEFBUF; /* 0x38: */ - __RW uint32_t OP_FFT_OUTRBUF; /* 0x38: */ - }; - union { - __RW uint32_t OP_REG5; /* 0x3C: */ - __RW uint32_t OP_FIR_OUTBUF; /* 0x3C: */ - }; - __RW uint32_t OP_REG6; /* 0x40: */ - __RW uint32_t OP_REG7; /* 0x44: */ -} FFA_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module if asserted to be 1. - * EN is only active after this bit is zero. - */ -#define FFA_CTRL_SFTRST_MASK (0x80000000UL) -#define FFA_CTRL_SFTRST_SHIFT (31U) -#define FFA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << FFA_CTRL_SFTRST_SHIFT) & FFA_CTRL_SFTRST_MASK) -#define FFA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & FFA_CTRL_SFTRST_MASK) >> FFA_CTRL_SFTRST_SHIFT) - -/* - * EN (RW) - * - * Asserted to enable the module - */ -#define FFA_CTRL_EN_MASK (0x1U) -#define FFA_CTRL_EN_SHIFT (0U) -#define FFA_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_CTRL_EN_SHIFT) & FFA_CTRL_EN_MASK) -#define FFA_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_CTRL_EN_MASK) >> FFA_CTRL_EN_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * FIR_OV (W1C) - * - * FIR Overflow err - */ -#define FFA_STATUS_FIR_OV_MASK (0x80U) -#define FFA_STATUS_FIR_OV_SHIFT (7U) -#define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) -#define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) - -/* - * FFT_OV (W1C) - * - * FFT Overflow Err - */ -#define FFA_STATUS_FFT_OV_MASK (0x40U) -#define FFA_STATUS_FFT_OV_SHIFT (6U) -#define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) -#define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) - -/* - * WR_ERR (W1C) - * - * AXI Data Write Error - */ -#define FFA_STATUS_WR_ERR_MASK (0x20U) -#define FFA_STATUS_WR_ERR_SHIFT (5U) -#define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) -#define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) - -/* - * RD_NXT_ERR (W1C) - * - * AXI Read Bus Error for NXT DATA - */ -#define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) -#define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) -#define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) -#define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) - -/* - * RD_ERR (W1C) - * - * AXI Data Read Error - */ -#define FFA_STATUS_RD_ERR_MASK (0x8U) -#define FFA_STATUS_RD_ERR_SHIFT (3U) -#define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) -#define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) - -/* - * NXT_CMD_RD_DONE (W1C) - * - * Indicate that next command sequence is already read into the module. - */ -#define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) -#define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) -#define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) -#define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) - -/* - * OP_CMD_DONE (W1C) - * - * Indicate that operation cmd is done, and data are available in system memory. - */ -#define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) -#define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) -#define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) -#define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRSV1 (RW) - * - * Reserved - */ -#define FFA_INT_EN_WRSV1_MASK (0xFFFFFF00UL) -#define FFA_INT_EN_WRSV1_SHIFT (8U) -#define FFA_INT_EN_WRSV1_SET(x) (((uint32_t)(x) << FFA_INT_EN_WRSV1_SHIFT) & FFA_INT_EN_WRSV1_MASK) -#define FFA_INT_EN_WRSV1_GET(x) (((uint32_t)(x) & FFA_INT_EN_WRSV1_MASK) >> FFA_INT_EN_WRSV1_SHIFT) - -/* - * FIR_OV (RW) - * - * FIR Overflow err - */ -#define FFA_INT_EN_FIR_OV_MASK (0x80U) -#define FFA_INT_EN_FIR_OV_SHIFT (7U) -#define FFA_INT_EN_FIR_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FIR_OV_SHIFT) & FFA_INT_EN_FIR_OV_MASK) -#define FFA_INT_EN_FIR_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FIR_OV_MASK) >> FFA_INT_EN_FIR_OV_SHIFT) - -/* - * FFT_OV (RW) - * - * FFT Overflow Err - */ -#define FFA_INT_EN_FFT_OV_MASK (0x40U) -#define FFA_INT_EN_FFT_OV_SHIFT (6U) -#define FFA_INT_EN_FFT_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FFT_OV_SHIFT) & FFA_INT_EN_FFT_OV_MASK) -#define FFA_INT_EN_FFT_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FFT_OV_MASK) >> FFA_INT_EN_FFT_OV_SHIFT) - -/* - * WR_ERR (RW) - * - * Enable Data Write Error interrupt - */ -#define FFA_INT_EN_WR_ERR_MASK (0x20U) -#define FFA_INT_EN_WR_ERR_SHIFT (5U) -#define FFA_INT_EN_WR_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_WR_ERR_SHIFT) & FFA_INT_EN_WR_ERR_MASK) -#define FFA_INT_EN_WR_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_WR_ERR_MASK) >> FFA_INT_EN_WR_ERR_SHIFT) - -/* - * RD_NXT_ERR (RW) - * - * Enable Read Bus Error for NXT DATA interrupt - */ -#define FFA_INT_EN_RD_NXT_ERR_MASK (0x10U) -#define FFA_INT_EN_RD_NXT_ERR_SHIFT (4U) -#define FFA_INT_EN_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_NXT_ERR_SHIFT) & FFA_INT_EN_RD_NXT_ERR_MASK) -#define FFA_INT_EN_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_NXT_ERR_MASK) >> FFA_INT_EN_RD_NXT_ERR_SHIFT) - -/* - * RD_ERR (RW) - * - * Enable Data Read Error interrupt - */ -#define FFA_INT_EN_RD_ERR_MASK (0x8U) -#define FFA_INT_EN_RD_ERR_SHIFT (3U) -#define FFA_INT_EN_RD_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_ERR_SHIFT) & FFA_INT_EN_RD_ERR_MASK) -#define FFA_INT_EN_RD_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_ERR_MASK) >> FFA_INT_EN_RD_ERR_SHIFT) - -/* - * NXT_CMD_RD_DONE (RW) - * - * Indicate that next command sequence is already read into the module. - */ -#define FFA_INT_EN_NXT_CMD_RD_DONE_MASK (0x2U) -#define FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT (1U) -#define FFA_INT_EN_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) -#define FFA_INT_EN_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) >> FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) - -/* - * OP_CMD_DONE (RW) - * - * Indicate that operation cmd is done, and data are available in system memory. - */ -#define FFA_INT_EN_OP_CMD_DONE_MASK (0x1U) -#define FFA_INT_EN_OP_CMD_DONE_SHIFT (0U) -#define FFA_INT_EN_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_OP_CMD_DONE_SHIFT) & FFA_INT_EN_OP_CMD_DONE_MASK) -#define FFA_INT_EN_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_OP_CMD_DONE_MASK) >> FFA_INT_EN_OP_CMD_DONE_SHIFT) - -/* Bitfield definition for register: OP_CTRL */ -/* - * NXT_ADDR (RW) - * - * The address for the next command. - * It will be processed after CUR_CMD is executed and done.. - */ -#define FFA_OP_CTRL_NXT_ADDR_MASK (0xFFFFFFFCUL) -#define FFA_OP_CTRL_NXT_ADDR_SHIFT (2U) -#define FFA_OP_CTRL_NXT_ADDR_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_ADDR_SHIFT) & FFA_OP_CTRL_NXT_ADDR_MASK) -#define FFA_OP_CTRL_NXT_ADDR_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_ADDR_MASK) >> FFA_OP_CTRL_NXT_ADDR_SHIFT) - -/* - * NXT_EN (RW) - * - * Whether NXT_CMD is enabled. - * Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - */ -#define FFA_OP_CTRL_NXT_EN_MASK (0x2U) -#define FFA_OP_CTRL_NXT_EN_SHIFT (1U) -#define FFA_OP_CTRL_NXT_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_EN_SHIFT) & FFA_OP_CTRL_NXT_EN_MASK) -#define FFA_OP_CTRL_NXT_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_EN_MASK) >> FFA_OP_CTRL_NXT_EN_SHIFT) - -/* - * EN (RW) - * - * Whether CUR_CMD is enabled. - * Asserted to enable the CUR_CMD - */ -#define FFA_OP_CTRL_EN_MASK (0x1U) -#define FFA_OP_CTRL_EN_SHIFT (0U) -#define FFA_OP_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_EN_SHIFT) & FFA_OP_CTRL_EN_MASK) -#define FFA_OP_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_EN_MASK) >> FFA_OP_CTRL_EN_SHIFT) - -/* Bitfield definition for register: OP_CMD */ -/* - * CONJ_C (RW) - * - * asserted to have conjuate value for coefs in computation - */ -#define FFA_OP_CMD_CONJ_C_MASK (0x1000000UL) -#define FFA_OP_CMD_CONJ_C_SHIFT (24U) -#define FFA_OP_CMD_CONJ_C_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CONJ_C_SHIFT) & FFA_OP_CMD_CONJ_C_MASK) -#define FFA_OP_CMD_CONJ_C_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CONJ_C_MASK) >> FFA_OP_CMD_CONJ_C_SHIFT) - -/* - * CMD (RW) - * - * The Command Used: - * 0: FIR - * 2: FFT - * Others: Reserved - */ -#define FFA_OP_CMD_CMD_MASK (0xFC0000UL) -#define FFA_OP_CMD_CMD_SHIFT (18U) -#define FFA_OP_CMD_CMD_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CMD_SHIFT) & FFA_OP_CMD_CMD_MASK) -#define FFA_OP_CMD_CMD_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CMD_MASK) >> FFA_OP_CMD_CMD_SHIFT) - -/* - * OUTD_TYPE (RW) - * - * Output data type: - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_OUTD_TYPE_MASK (0x38000UL) -#define FFA_OP_CMD_OUTD_TYPE_SHIFT (15U) -#define FFA_OP_CMD_OUTD_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_OUTD_TYPE_SHIFT) & FFA_OP_CMD_OUTD_TYPE_MASK) -#define FFA_OP_CMD_OUTD_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_OUTD_TYPE_MASK) >> FFA_OP_CMD_OUTD_TYPE_SHIFT) - -/* - * COEF_TYPE (RW) - * - * Coef data type (used for FIR): - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_COEF_TYPE_MASK (0x7000U) -#define FFA_OP_CMD_COEF_TYPE_SHIFT (12U) -#define FFA_OP_CMD_COEF_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_COEF_TYPE_SHIFT) & FFA_OP_CMD_COEF_TYPE_MASK) -#define FFA_OP_CMD_COEF_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_COEF_TYPE_MASK) >> FFA_OP_CMD_COEF_TYPE_SHIFT) - -/* - * IND_TYPE (RW) - * - * Input data type: - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_IND_TYPE_MASK (0xE00U) -#define FFA_OP_CMD_IND_TYPE_SHIFT (9U) -#define FFA_OP_CMD_IND_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_IND_TYPE_SHIFT) & FFA_OP_CMD_IND_TYPE_MASK) -#define FFA_OP_CMD_IND_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_IND_TYPE_MASK) >> FFA_OP_CMD_IND_TYPE_SHIFT) - -/* - * NXT_CMD_LEN (RW) - * - * The length of nxt commands in 32-bit words - */ -#define FFA_OP_CMD_NXT_CMD_LEN_MASK (0xFFU) -#define FFA_OP_CMD_NXT_CMD_LEN_SHIFT (0U) -#define FFA_OP_CMD_NXT_CMD_LEN_SET(x) (((uint32_t)(x) << FFA_OP_CMD_NXT_CMD_LEN_SHIFT) & FFA_OP_CMD_NXT_CMD_LEN_MASK) -#define FFA_OP_CMD_NXT_CMD_LEN_GET(x) (((uint32_t)(x) & FFA_OP_CMD_NXT_CMD_LEN_MASK) >> FFA_OP_CMD_NXT_CMD_LEN_SHIFT) - -/* Bitfield definition for register: OP_REG0 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG0_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG0_CT_SHIFT (0U) -#define FFA_OP_REG0_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG0_CT_SHIFT) & FFA_OP_REG0_CT_MASK) -#define FFA_OP_REG0_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG0_CT_MASK) >> FFA_OP_REG0_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_MISC */ -/* - * FIR_COEF_TAPS (RW) - * - * Length of FIR coefs （max 256） - */ -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) >> FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) - -/* Bitfield definition for register: OP_FFT_MISC */ -/* - * FFT_LEN (RW) - * - * FFT length - * 0:8, - * ..., - * n:2^(3+n) - */ -#define FFA_OP_FFT_MISC_FFT_LEN_MASK (0x780U) -#define FFA_OP_FFT_MISC_FFT_LEN_SHIFT (7U) -#define FFA_OP_FFT_MISC_FFT_LEN_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_FFT_LEN_SHIFT) & FFA_OP_FFT_MISC_FFT_LEN_MASK) -#define FFA_OP_FFT_MISC_FFT_LEN_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_FFT_LEN_MASK) >> FFA_OP_FFT_MISC_FFT_LEN_SHIFT) - -/* - * IFFT (RW) - * - * Asserted to indicate IFFT - */ -#define FFA_OP_FFT_MISC_IFFT_MASK (0x40U) -#define FFA_OP_FFT_MISC_IFFT_SHIFT (6U) -#define FFA_OP_FFT_MISC_IFFT_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IFFT_SHIFT) & FFA_OP_FFT_MISC_IFFT_MASK) -#define FFA_OP_FFT_MISC_IFFT_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IFFT_MASK) >> FFA_OP_FFT_MISC_IFFT_SHIFT) - -/* - * TMP_BLK (RW) - * - * Memory block for indata. Should be assigned as 1 - */ -#define FFA_OP_FFT_MISC_TMP_BLK_MASK (0xCU) -#define FFA_OP_FFT_MISC_TMP_BLK_SHIFT (2U) -#define FFA_OP_FFT_MISC_TMP_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_TMP_BLK_SHIFT) & FFA_OP_FFT_MISC_TMP_BLK_MASK) -#define FFA_OP_FFT_MISC_TMP_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_TMP_BLK_MASK) >> FFA_OP_FFT_MISC_TMP_BLK_SHIFT) - -/* - * IND_BLK (RW) - * - * Memory block for indata. Should be assigned as 0 - */ -#define FFA_OP_FFT_MISC_IND_BLK_MASK (0x3U) -#define FFA_OP_FFT_MISC_IND_BLK_SHIFT (0U) -#define FFA_OP_FFT_MISC_IND_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IND_BLK_SHIFT) & FFA_OP_FFT_MISC_IND_BLK_MASK) -#define FFA_OP_FFT_MISC_IND_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IND_BLK_MASK) >> FFA_OP_FFT_MISC_IND_BLK_SHIFT) - -/* Bitfield definition for register: OP_REG1 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG1_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG1_CT_SHIFT (0U) -#define FFA_OP_REG1_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG1_CT_SHIFT) & FFA_OP_REG1_CT_MASK) -#define FFA_OP_REG1_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG1_CT_MASK) >> FFA_OP_REG1_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_MISC1 */ -/* - * OUTD_MEM_BLK (RW) - * - * Should be assigned as 0 - */ -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK (0x300000UL) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT (20U) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) - -/* - * COEF_MEM_BLK (RW) - * - * Should be assigned as 1 - */ -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK (0xC0000UL) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT (18U) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) - -/* - * IND_MEM_BLK (RW) - * - * Should be assigned as 2 - */ -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK (0x30000UL) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT (16U) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) - -/* - * FIR_DATA_TAPS (RW) - * - * The input data data length - */ -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK (0xFFFFU) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT (0U) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) >> FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) - -/* Bitfield definition for register: OP_REG2 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG2_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG2_CT_SHIFT (0U) -#define FFA_OP_REG2_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG2_CT_SHIFT) & FFA_OP_REG2_CT_MASK) -#define FFA_OP_REG2_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG2_CT_MASK) >> FFA_OP_REG2_CT_SHIFT) - -/* Bitfield definition for register: OP_FFT_INRBUF */ -/* - * LOC (RW) - * - * The input (real) data buffer pointer - */ -#define FFA_OP_FFT_INRBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FFT_INRBUF_LOC_SHIFT (0U) -#define FFA_OP_FFT_INRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_INRBUF_LOC_SHIFT) & FFA_OP_FFT_INRBUF_LOC_MASK) -#define FFA_OP_FFT_INRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_INRBUF_LOC_MASK) >> FFA_OP_FFT_INRBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG3 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG3_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG3_CT_SHIFT (0U) -#define FFA_OP_REG3_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG3_CT_SHIFT) & FFA_OP_REG3_CT_MASK) -#define FFA_OP_REG3_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG3_CT_MASK) >> FFA_OP_REG3_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_INBUF */ -/* - * LOC (RW) - * - * The input data buffer pointer - */ -#define FFA_OP_FIR_INBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_INBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_INBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_INBUF_LOC_SHIFT) & FFA_OP_FIR_INBUF_LOC_MASK) -#define FFA_OP_FIR_INBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_INBUF_LOC_MASK) >> FFA_OP_FIR_INBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG4 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG4_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG4_CT_SHIFT (0U) -#define FFA_OP_REG4_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG4_CT_SHIFT) & FFA_OP_REG4_CT_MASK) -#define FFA_OP_REG4_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG4_CT_MASK) >> FFA_OP_REG4_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_COEFBUF */ -/* - * LOC (RW) - * - * The coef buf pointer - */ -#define FFA_OP_FIR_COEFBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_COEFBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_COEFBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_COEFBUF_LOC_SHIFT) & FFA_OP_FIR_COEFBUF_LOC_MASK) -#define FFA_OP_FIR_COEFBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_COEFBUF_LOC_MASK) >> FFA_OP_FIR_COEFBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_FFT_OUTRBUF */ -/* - * LOC (RW) - * - * The output (real) data buffer pointer - */ -#define FFA_OP_FFT_OUTRBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FFT_OUTRBUF_LOC_SHIFT (0U) -#define FFA_OP_FFT_OUTRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_OUTRBUF_LOC_SHIFT) & FFA_OP_FFT_OUTRBUF_LOC_MASK) -#define FFA_OP_FFT_OUTRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_OUTRBUF_LOC_MASK) >> FFA_OP_FFT_OUTRBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG5 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG5_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG5_CT_SHIFT (0U) -#define FFA_OP_REG5_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG5_CT_SHIFT) & FFA_OP_REG5_CT_MASK) -#define FFA_OP_REG5_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG5_CT_MASK) >> FFA_OP_REG5_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_OUTBUF */ -/* - * LOC (RW) - * - * The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - */ -#define FFA_OP_FIR_OUTBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_OUTBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_OUTBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_OUTBUF_LOC_SHIFT) & FFA_OP_FIR_OUTBUF_LOC_MASK) -#define FFA_OP_FIR_OUTBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_OUTBUF_LOC_MASK) >> FFA_OP_FIR_OUTBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG6 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG6_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG6_CT_SHIFT (0U) -#define FFA_OP_REG6_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG6_CT_SHIFT) & FFA_OP_REG6_CT_MASK) -#define FFA_OP_REG6_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG6_CT_MASK) >> FFA_OP_REG6_CT_SHIFT) - -/* Bitfield definition for register: OP_REG7 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG7_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG7_CT_SHIFT (0U) -#define FFA_OP_REG7_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG7_CT_SHIFT) & FFA_OP_REG7_CT_MASK) -#define FFA_OP_REG7_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG7_CT_MASK) >> FFA_OP_REG7_CT_SHIFT) - - - - -#endif /* HPM_FFA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gpio_regs.h deleted file mode 100644 index 4f2a3d18dbf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gpio_regs.h +++ /dev/null @@ -1,468 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIO_H -#define HPM_GPIO_H - -typedef struct { - struct { - __R uint32_t VALUE; /* 0x0: GPIO input value */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - } DI[16]; - struct { - __RW uint32_t VALUE; /* 0x100: GPIO output value */ - __RW uint32_t SET; /* 0x104: GPIO output set */ - __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ - __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ - } DO[16]; - struct { - __RW uint32_t VALUE; /* 0x200: GPIO direction value */ - __RW uint32_t SET; /* 0x204: GPIO direction set */ - __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ - __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ - } OE[16]; - struct { - __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ - } IF[16]; - struct { - __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ - __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ - __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ - } IE[16]; - struct { - __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ - __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ - __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ - __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ - } PL[16]; - struct { - __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ - __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ - __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ - __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ - } TP[16]; - struct { - __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ - __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ - __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ - __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ - } AS[16]; -} GPIO_Type; - - -/* Bitfield definition for register of struct array DI: VALUE */ -/* - * INPUT (RO) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: VALUE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) -#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) -#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: SET */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_SET_OUTPUT_SHIFT (0U) -#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) -#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: CLEAR */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) -#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) -#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: TOGGLE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) -#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) -#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array OE: VALUE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) -#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) -#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: SET */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_SET_DIRECTION_SHIFT (0U) -#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) -#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: CLEAR */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) -#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) -#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: TOGGLE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) -#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) -#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array IF: VALUE */ -/* - * IRQ_FLAG (W1C) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) -#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IE: VALUE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) -#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: SET */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) -#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) -#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: CLEAR */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) -#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) -#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: TOGGLE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) -#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array PL: VALUE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) -#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: SET */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) -#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) -#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: CLEAR */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) -#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) -#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: TOGGLE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) -#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array TP: VALUE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) -#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: SET */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) -#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: CLEAR */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) -#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: TOGGLE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) -#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array AS: VALUE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) -#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: SET */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) -#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: CLEAR */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) -#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: TOGGLE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) - - - -/* DI register group index macro definition */ -#define GPIO_DI_GPIOA (0UL) -#define GPIO_DI_GPIOB (1UL) -#define GPIO_DI_GPIOC (2UL) -#define GPIO_DI_GPIOX (13UL) -#define GPIO_DI_GPIOY (14UL) -#define GPIO_DI_GPIOZ (15UL) - -/* DO register group index macro definition */ -#define GPIO_DO_GPIOA (0UL) -#define GPIO_DO_GPIOB (1UL) -#define GPIO_DO_GPIOC (2UL) -#define GPIO_DO_GPIOX (13UL) -#define GPIO_DO_GPIOY (14UL) -#define GPIO_DO_GPIOZ (15UL) - -/* OE register group index macro definition */ -#define GPIO_OE_GPIOA (0UL) -#define GPIO_OE_GPIOB (1UL) -#define GPIO_OE_GPIOC (2UL) -#define GPIO_OE_GPIOX (13UL) -#define GPIO_OE_GPIOY (14UL) -#define GPIO_OE_GPIOZ (15UL) - -/* IF register group index macro definition */ -#define GPIO_IF_GPIOA (0UL) -#define GPIO_IF_GPIOB (1UL) -#define GPIO_IF_GPIOC (2UL) -#define GPIO_IF_GPIOX (13UL) -#define GPIO_IF_GPIOY (14UL) -#define GPIO_IF_GPIOZ (15UL) - -/* IE register group index macro definition */ -#define GPIO_IE_GPIOA (0UL) -#define GPIO_IE_GPIOB (1UL) -#define GPIO_IE_GPIOC (2UL) -#define GPIO_IE_GPIOX (13UL) -#define GPIO_IE_GPIOY (14UL) -#define GPIO_IE_GPIOZ (15UL) - -/* PL register group index macro definition */ -#define GPIO_PL_GPIOA (0UL) -#define GPIO_PL_GPIOB (1UL) -#define GPIO_PL_GPIOC (2UL) -#define GPIO_PL_GPIOX (13UL) -#define GPIO_PL_GPIOY (14UL) -#define GPIO_PL_GPIOZ (15UL) - -/* TP register group index macro definition */ -#define GPIO_TP_GPIOA (0UL) -#define GPIO_TP_GPIOB (1UL) -#define GPIO_TP_GPIOC (2UL) -#define GPIO_TP_GPIOX (13UL) -#define GPIO_TP_GPIOY (14UL) -#define GPIO_TP_GPIOZ (15UL) - -/* AS register group index macro definition */ -#define GPIO_AS_GPIOA (0UL) -#define GPIO_AS_GPIOB (1UL) -#define GPIO_AS_GPIOC (2UL) -#define GPIO_AS_GPIOX (13UL) -#define GPIO_AS_GPIOY (14UL) -#define GPIO_AS_GPIOZ (15UL) - - -#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gpiom_regs.h deleted file mode 100644 index b7bc4e72702..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gpiom_regs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIOM_H -#define HPM_GPIOM_H - -typedef struct { - struct { - __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ - } ASSIGN[16]; -} GPIOM_Type; - - -/* Bitfield definition for register of struct array ASSIGN: PIN00 */ -/* - * LOCK (RW) - * - * lock fields in this register, lock can only be cleared by soc reset - * 0: fields can be changed - * 1: fields locked to current value, not changeable - */ -#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) -#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) -#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) - -/* - * HIDE (RW) - * - * pin value visibility to gpios, - * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 - * bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - */ -#define GPIOM_ASSIGN_PIN_HIDE_MASK (0x300U) -#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) -#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) -#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) - -/* - * SELECT (RW) - * - * select which gpio controls chip pin, - * 0: soc gpio0; - * 1: cpu0 fastgpio - */ -#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x1U) -#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) -#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) -#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) - - - -/* PIN register group index macro definition */ -#define GPIOM_ASSIGN_PIN_PIN00 (0UL) -#define GPIOM_ASSIGN_PIN_PIN01 (1UL) -#define GPIOM_ASSIGN_PIN_PIN02 (2UL) -#define GPIOM_ASSIGN_PIN_PIN03 (3UL) -#define GPIOM_ASSIGN_PIN_PIN04 (4UL) -#define GPIOM_ASSIGN_PIN_PIN05 (5UL) -#define GPIOM_ASSIGN_PIN_PIN06 (6UL) -#define GPIOM_ASSIGN_PIN_PIN07 (7UL) -#define GPIOM_ASSIGN_PIN_PIN08 (8UL) -#define GPIOM_ASSIGN_PIN_PIN09 (9UL) -#define GPIOM_ASSIGN_PIN_PIN10 (10UL) -#define GPIOM_ASSIGN_PIN_PIN11 (11UL) -#define GPIOM_ASSIGN_PIN_PIN12 (12UL) -#define GPIOM_ASSIGN_PIN_PIN13 (13UL) -#define GPIOM_ASSIGN_PIN_PIN14 (14UL) -#define GPIOM_ASSIGN_PIN_PIN15 (15UL) -#define GPIOM_ASSIGN_PIN_PIN16 (16UL) -#define GPIOM_ASSIGN_PIN_PIN17 (17UL) -#define GPIOM_ASSIGN_PIN_PIN18 (18UL) -#define GPIOM_ASSIGN_PIN_PIN19 (19UL) -#define GPIOM_ASSIGN_PIN_PIN20 (20UL) -#define GPIOM_ASSIGN_PIN_PIN21 (21UL) -#define GPIOM_ASSIGN_PIN_PIN22 (22UL) -#define GPIOM_ASSIGN_PIN_PIN23 (23UL) -#define GPIOM_ASSIGN_PIN_PIN24 (24UL) -#define GPIOM_ASSIGN_PIN_PIN25 (25UL) -#define GPIOM_ASSIGN_PIN_PIN26 (26UL) -#define GPIOM_ASSIGN_PIN_PIN27 (27UL) -#define GPIOM_ASSIGN_PIN_PIN28 (28UL) -#define GPIOM_ASSIGN_PIN_PIN29 (29UL) -#define GPIOM_ASSIGN_PIN_PIN30 (30UL) -#define GPIOM_ASSIGN_PIN_PIN31 (31UL) - -/* ASSIGN register group index macro definition */ -#define GPIOM_ASSIGN_GPIOA (0UL) -#define GPIOM_ASSIGN_GPIOB (1UL) -#define GPIOM_ASSIGN_GPIOC (2UL) -#define GPIOM_ASSIGN_GPIOX (13UL) -#define GPIOM_ASSIGN_GPIOY (14UL) -#define GPIOM_ASSIGN_GPIOZ (15UL) - - -#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gptmr_regs.h deleted file mode 100644 index f87b1a75632..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_gptmr_regs.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPTMR_H -#define HPM_GPTMR_H - -typedef struct { - struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ - __RW uint32_t RLD; /* 0xC: Reload register */ - __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ - __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ - __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ - __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ - __R uint32_t CNT; /* 0x30: Counter */ - __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ - } CHANNEL[4]; - __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ - __RW uint32_t SR; /* 0x200: Status register */ - __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ - __RW uint32_t GCR; /* 0x208: Global control register */ -} GPTMR_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CR */ -/* - * CNTUPT (WO) - * - * 1- update counter to new value as CNTUPTVAL - * This bit will be auto cleared after 1 cycle - */ -#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) -#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) -#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) -#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) - -/* - * CNTRST (RW) - * - * 1- reset counter - */ -#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) -#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) -#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) -#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) - -/* - * SYNCFLW (RW) - * - * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. - * This bit is not valid for channel 0. - */ -#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) -#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) - -/* - * SYNCIFEN (RW) - * - * 1- SYNCI is valid on its falling edge - */ -#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) - -/* - * SYNCIREN (RW) - * - * 1- SYNCI is valid on its rising edge - */ -#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) - -/* - * CEN (RW) - * - * 1- counter enable - */ -#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) -#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) -#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) -#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) - -/* - * CMPINIT (RW) - * - * Output compare initial poliarity - * 1- The channel output initial level is high - * 0- The channel output initial level is low - * User should set this bit before set CMPEN to 1. - */ -#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) -#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) -#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) -#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) - -/* - * CMPEN (RW) - * - * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - */ -#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) -#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) -#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) -#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) - -/* - * DMASEL (RW) - * - * select one of DMA request: - * 00- CMP0 flag - * 01- CMP1 flag - * 10- Input signal toggle captured - * 11- RLD flag, counter reload; - */ -#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) -#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) -#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) -#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) - -/* - * DMAEN (RW) - * - * 1- enable dma - */ -#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) -#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) -#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) -#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) - -/* - * SWSYNCIEN (RW) - * - * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - */ -#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) - -/* - * DBGPAUSE (RW) - * - * 1- counter will pause if chip is in debug mode - */ -#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) -#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) - -/* - * CAPMODE (RW) - * - * This bitfield define the input capture mode - * 100: width measure mode, timer will calculate the input signal period and duty cycle - * 011: capture at both rising edge and falling edge - * 010: capture at falling edge - * 001: capture at rising edge - * 000: No capture - */ -#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) -#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) -#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) -#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CMP0 */ -/* - * CMP (RW) - * - * compare value 0 - */ -#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) -#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) -#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: RLD */ -/* - * RLD (RW) - * - * reload value - */ -#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) -#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) -#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ -/* - * CNTUPTVAL (RW) - * - * counter will be set to this value when software write cntupt bit in CR - */ -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ -/* - * CAPPOS (RO) - * - * This register contains the counter value captured at input signal rising edge - */ -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ -/* - * CAPNEG (RO) - * - * This register contains the counter value captured at input signal falling edge - */ -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ -/* - * CAPPRD (RO) - * - * This register contains the input signal period when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ -/* - * MEAS_HIGH (RO) - * - * This register contains the input signal duty cycle when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNT */ -/* - * COUNTER (RO) - * - * 32 bit counter value - */ -#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) -#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * CH3CMP1F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) -#define GPTMR_SR_CH3CMP1F_SHIFT (15U) -#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) -#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) - -/* - * CH3CMP0F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) -#define GPTMR_SR_CH3CMP0F_SHIFT (14U) -#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) -#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) - -/* - * CH3CAPF (W1C) - * - * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH3CAPF_MASK (0x2000U) -#define GPTMR_SR_CH3CAPF_SHIFT (13U) -#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) -#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) - -/* - * CH3RLDF (W1C) - * - * channel 3 counter reload flag - */ -#define GPTMR_SR_CH3RLDF_MASK (0x1000U) -#define GPTMR_SR_CH3RLDF_SHIFT (12U) -#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) -#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) - -/* - * CH2CMP1F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP1F_MASK (0x800U) -#define GPTMR_SR_CH2CMP1F_SHIFT (11U) -#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) -#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) - -/* - * CH2CMP0F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP0F_MASK (0x400U) -#define GPTMR_SR_CH2CMP0F_SHIFT (10U) -#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) -#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) - -/* - * CH2CAPF (W1C) - * - * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH2CAPF_MASK (0x200U) -#define GPTMR_SR_CH2CAPF_SHIFT (9U) -#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) -#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) - -/* - * CH2RLDF (W1C) - * - * channel 2 counter reload flag - */ -#define GPTMR_SR_CH2RLDF_MASK (0x100U) -#define GPTMR_SR_CH2RLDF_SHIFT (8U) -#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) -#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) - -/* - * CH1CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP1F_MASK (0x80U) -#define GPTMR_SR_CH1CMP1F_SHIFT (7U) -#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) -#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) - -/* - * CH1CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP0F_MASK (0x40U) -#define GPTMR_SR_CH1CMP0F_SHIFT (6U) -#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) -#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) - -/* - * CH1CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH1CAPF_MASK (0x20U) -#define GPTMR_SR_CH1CAPF_SHIFT (5U) -#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) -#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) - -/* - * CH1RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH1RLDF_MASK (0x10U) -#define GPTMR_SR_CH1RLDF_SHIFT (4U) -#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) -#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) - -/* - * CH0CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP1F_MASK (0x8U) -#define GPTMR_SR_CH0CMP1F_SHIFT (3U) -#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) -#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) - -/* - * CH0CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP0F_MASK (0x4U) -#define GPTMR_SR_CH0CMP0F_SHIFT (2U) -#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) -#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) - -/* - * CH0CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH0CAPF_MASK (0x2U) -#define GPTMR_SR_CH0CAPF_SHIFT (1U) -#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) -#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) - -/* - * CH0RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH0RLDF_MASK (0x1U) -#define GPTMR_SR_CH0RLDF_SHIFT (0U) -#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) -#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * CH3CMP1EN (RW) - * - * 1- generate interrupt request when ch3cmp1f flag is set - */ -#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) -#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) -#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) -#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) - -/* - * CH3CMP0EN (RW) - * - * 1- generate interrupt request when ch3cmp0f flag is set - */ -#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) -#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) -#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) -#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) - -/* - * CH3CAPEN (RW) - * - * 1- generate interrupt request when ch3capf flag is set - */ -#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) -#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) -#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) -#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) - -/* - * CH3RLDEN (RW) - * - * 1- generate interrupt request when ch3rldf flag is set - */ -#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) -#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) -#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) -#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) - -/* - * CH2CMP1EN (RW) - * - * 1- generate interrupt request when ch2cmp1f flag is set - */ -#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) -#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) -#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) -#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) - -/* - * CH2CMP0EN (RW) - * - * 1- generate interrupt request when ch2cmp0f flag is set - */ -#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) -#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) -#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) -#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) - -/* - * CH2CAPEN (RW) - * - * 1- generate interrupt request when ch2capf flag is set - */ -#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) -#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) -#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) -#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) - -/* - * CH2RLDEN (RW) - * - * 1- generate interrupt request when ch2rldf flag is set - */ -#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) -#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) -#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) -#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) - -/* - * CH1CMP1EN (RW) - * - * 1- generate interrupt request when ch1cmp1f flag is set - */ -#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) -#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) -#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) -#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) - -/* - * CH1CMP0EN (RW) - * - * 1- generate interrupt request when ch1cmp0f flag is set - */ -#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) -#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) -#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) -#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) - -/* - * CH1CAPEN (RW) - * - * 1- generate interrupt request when ch1capf flag is set - */ -#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) -#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) -#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) -#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) - -/* - * CH1RLDEN (RW) - * - * 1- generate interrupt request when ch1rldf flag is set - */ -#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) -#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) -#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) -#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) - -/* - * CH0CMP1EN (RW) - * - * 1- generate interrupt request when ch0cmp1f flag is set - */ -#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) -#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) -#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) -#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) - -/* - * CH0CMP0EN (RW) - * - * 1- generate interrupt request when ch0cmp0f flag is set - */ -#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) -#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) -#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) -#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) - -/* - * CH0CAPEN (RW) - * - * 1- generate interrupt request when ch0capf flag is set - */ -#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) -#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) -#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) -#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) - -/* - * CH0RLDEN (RW) - * - * 1- generate interrupt request when ch0rldf flag is set - */ -#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) -#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) -#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) -#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * SWSYNCT (RW) - * - * set this bitfield to trigger software counter sync event - */ -#define GPTMR_GCR_SWSYNCT_MASK (0xFU) -#define GPTMR_GCR_SWSYNCT_SHIFT (0U) -#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) -#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) - - - -/* CMP register group index macro definition */ -#define GPTMR_CHANNEL_CMP_CMP0 (0UL) -#define GPTMR_CHANNEL_CMP_CMP1 (1UL) - -/* CHANNEL register group index macro definition */ -#define GPTMR_CHANNEL_CH0 (0UL) -#define GPTMR_CHANNEL_CH1 (1UL) -#define GPTMR_CHANNEL_CH2 (2UL) -#define GPTMR_CHANNEL_CH3 (3UL) - - -#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_hall_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_hall_regs.h deleted file mode 100644 index 4b48f04c3d3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_hall_regs.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_HALL_H -#define HPM_HALL_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t UVWCFG; /* 0xC: U,V,W configure register */ - __RW uint32_t TRGOEN; /* 0x10: Trigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __R uint8_t RESERVED0[12]; /* 0x18 - 0x23: Reserved */ - __RW uint32_t DMAEN; /* 0x24: DMA enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request enable register */ - struct { - __R uint32_t W; /* 0x30: W counter */ - __R uint32_t V; /* 0x34: V counter */ - __R uint32_t U; /* 0x38: U counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - struct { - __R uint32_t HIS0; /* 0x70: history register 0 */ - __R uint32_t HIS1; /* 0x74: history register 1 */ - } HIS[3]; -} HALL_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define HALL_CR_READ_MASK (0x80000000UL) -#define HALL_CR_READ_SHIFT (31U) -#define HALL_CR_READ_SET(x) (((uint32_t)(x) << HALL_CR_READ_SHIFT) & HALL_CR_READ_MASK) -#define HALL_CR_READ_GET(x) (((uint32_t)(x) & HALL_CR_READ_MASK) >> HALL_CR_READ_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - */ -#define HALL_CR_SNAPEN_MASK (0x800U) -#define HALL_CR_SNAPEN_SHIFT (11U) -#define HALL_CR_SNAPEN_SET(x) (((uint32_t)(x) << HALL_CR_SNAPEN_SHIFT) & HALL_CR_SNAPEN_MASK) -#define HALL_CR_SNAPEN_GET(x) (((uint32_t)(x) & HALL_CR_SNAPEN_MASK) >> HALL_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * set to reset all counter and related snapshots - */ -#define HALL_CR_RSTCNT_MASK (0x10U) -#define HALL_CR_RSTCNT_SHIFT (4U) -#define HALL_CR_RSTCNT_SET(x) (((uint32_t)(x) << HALL_CR_RSTCNT_SHIFT) & HALL_CR_RSTCNT_MASK) -#define HALL_CR_RSTCNT_GET(x) (((uint32_t)(x) & HALL_CR_RSTCNT_MASK) >> HALL_CR_RSTCNT_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * DLYSEL (RW) - * - * This bit select delay start time: - * 1- start counting delay after pre-trigger - * 0- start counting delay after u,v,w toggle - */ -#define HALL_PHCFG_DLYSEL_MASK (0x80000000UL) -#define HALL_PHCFG_DLYSEL_SHIFT (31U) -#define HALL_PHCFG_DLYSEL_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYSEL_SHIFT) & HALL_PHCFG_DLYSEL_MASK) -#define HALL_PHCFG_DLYSEL_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYSEL_MASK) >> HALL_PHCFG_DLYSEL_SHIFT) - -/* - * DLYCNT (RW) - * - * delay clock cycles number - */ -#define HALL_PHCFG_DLYCNT_MASK (0xFFFFFFUL) -#define HALL_PHCFG_DLYCNT_SHIFT (0U) -#define HALL_PHCFG_DLYCNT_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYCNT_SHIFT) & HALL_PHCFG_DLYCNT_MASK) -#define HALL_PHCFG_DLYCNT_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYCNT_MASK) >> HALL_PHCFG_DLYCNT_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define HALL_WDGCFG_WDGEN_MASK (0x80000000UL) -#define HALL_WDGCFG_WDGEN_SHIFT (31U) -#define HALL_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGEN_SHIFT) & HALL_WDGCFG_WDGEN_MASK) -#define HALL_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGEN_MASK) >> HALL_WDGCFG_WDGEN_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define HALL_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) -#define HALL_WDGCFG_WDGTO_SHIFT (0U) -#define HALL_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGTO_SHIFT) & HALL_WDGCFG_WDGTO_MASK) -#define HALL_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGTO_MASK) >> HALL_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: UVWCFG */ -/* - * PRECNT (RW) - * - * the clock cycle number which the pre flag will set before the next uvw transition - */ -#define HALL_UVWCFG_PRECNT_MASK (0xFFFFFFUL) -#define HALL_UVWCFG_PRECNT_SHIFT (0U) -#define HALL_UVWCFG_PRECNT_SET(x) (((uint32_t)(x) << HALL_UVWCFG_PRECNT_SHIFT) & HALL_UVWCFG_PRECNT_MASK) -#define HALL_UVWCFG_PRECNT_GET(x) (((uint32_t)(x) & HALL_UVWCFG_PRECNT_MASK) >> HALL_UVWCFG_PRECNT_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define HALL_TRGOEN_WDGEN_MASK (0x80000000UL) -#define HALL_TRGOEN_WDGEN_SHIFT (31U) -#define HALL_TRGOEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WDGEN_SHIFT) & HALL_TRGOEN_WDGEN_MASK) -#define HALL_TRGOEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WDGEN_MASK) >> HALL_TRGOEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- enable trigger output when phupt flag set - */ -#define HALL_TRGOEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_TRGOEN_PHUPTEN_SHIFT (30U) -#define HALL_TRGOEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHUPTEN_SHIFT) & HALL_TRGOEN_PHUPTEN_MASK) -#define HALL_TRGOEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHUPTEN_MASK) >> HALL_TRGOEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- enable trigger output when phpre flag set - */ -#define HALL_TRGOEN_PHPREEN_MASK (0x20000000UL) -#define HALL_TRGOEN_PHPREEN_SHIFT (29U) -#define HALL_TRGOEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHPREEN_SHIFT) & HALL_TRGOEN_PHPREEN_MASK) -#define HALL_TRGOEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHPREEN_MASK) >> HALL_TRGOEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- enable trigger output when phdly flag set - */ -#define HALL_TRGOEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_TRGOEN_PHDLYEN_SHIFT (28U) -#define HALL_TRGOEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHDLYEN_SHIFT) & HALL_TRGOEN_PHDLYEN_MASK) -#define HALL_TRGOEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHDLYEN_MASK) >> HALL_TRGOEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- enable trigger output when u flag set - */ -#define HALL_TRGOEN_UFEN_MASK (0x800000UL) -#define HALL_TRGOEN_UFEN_SHIFT (23U) -#define HALL_TRGOEN_UFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_UFEN_SHIFT) & HALL_TRGOEN_UFEN_MASK) -#define HALL_TRGOEN_UFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_UFEN_MASK) >> HALL_TRGOEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- enable trigger output when v flag set - */ -#define HALL_TRGOEN_VFEN_MASK (0x400000UL) -#define HALL_TRGOEN_VFEN_SHIFT (22U) -#define HALL_TRGOEN_VFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_VFEN_SHIFT) & HALL_TRGOEN_VFEN_MASK) -#define HALL_TRGOEN_VFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_VFEN_MASK) >> HALL_TRGOEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- enable trigger output when w flag set - */ -#define HALL_TRGOEN_WFEN_MASK (0x200000UL) -#define HALL_TRGOEN_WFEN_SHIFT (21U) -#define HALL_TRGOEN_WFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WFEN_SHIFT) & HALL_TRGOEN_WFEN_MASK) -#define HALL_TRGOEN_WFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WFEN_MASK) >> HALL_TRGOEN_WFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define HALL_READEN_WDGEN_MASK (0x80000000UL) -#define HALL_READEN_WDGEN_SHIFT (31U) -#define HALL_READEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_READEN_WDGEN_SHIFT) & HALL_READEN_WDGEN_MASK) -#define HALL_READEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_READEN_WDGEN_MASK) >> HALL_READEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- load counters to their read registers when phupt flag set - */ -#define HALL_READEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_READEN_PHUPTEN_SHIFT (30U) -#define HALL_READEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHUPTEN_SHIFT) & HALL_READEN_PHUPTEN_MASK) -#define HALL_READEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHUPTEN_MASK) >> HALL_READEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- load counters to their read registers when phpre flag set - */ -#define HALL_READEN_PHPREEN_MASK (0x20000000UL) -#define HALL_READEN_PHPREEN_SHIFT (29U) -#define HALL_READEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHPREEN_SHIFT) & HALL_READEN_PHPREEN_MASK) -#define HALL_READEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHPREEN_MASK) >> HALL_READEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- load counters to their read registers when phdly flag set - */ -#define HALL_READEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_READEN_PHDLYEN_SHIFT (28U) -#define HALL_READEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHDLYEN_SHIFT) & HALL_READEN_PHDLYEN_MASK) -#define HALL_READEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHDLYEN_MASK) >> HALL_READEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- load counters to their read registers when u flag set - */ -#define HALL_READEN_UFEN_MASK (0x800000UL) -#define HALL_READEN_UFEN_SHIFT (23U) -#define HALL_READEN_UFEN_SET(x) (((uint32_t)(x) << HALL_READEN_UFEN_SHIFT) & HALL_READEN_UFEN_MASK) -#define HALL_READEN_UFEN_GET(x) (((uint32_t)(x) & HALL_READEN_UFEN_MASK) >> HALL_READEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- load counters to their read registers when v flag set - */ -#define HALL_READEN_VFEN_MASK (0x400000UL) -#define HALL_READEN_VFEN_SHIFT (22U) -#define HALL_READEN_VFEN_SET(x) (((uint32_t)(x) << HALL_READEN_VFEN_SHIFT) & HALL_READEN_VFEN_MASK) -#define HALL_READEN_VFEN_GET(x) (((uint32_t)(x) & HALL_READEN_VFEN_MASK) >> HALL_READEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- load counters to their read registers when w flag set - */ -#define HALL_READEN_WFEN_MASK (0x200000UL) -#define HALL_READEN_WFEN_SHIFT (21U) -#define HALL_READEN_WFEN_SET(x) (((uint32_t)(x) << HALL_READEN_WFEN_SHIFT) & HALL_READEN_WFEN_MASK) -#define HALL_READEN_WFEN_GET(x) (((uint32_t)(x) & HALL_READEN_WFEN_MASK) >> HALL_READEN_WFEN_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define HALL_DMAEN_WDGEN_MASK (0x80000000UL) -#define HALL_DMAEN_WDGEN_SHIFT (31U) -#define HALL_DMAEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WDGEN_SHIFT) & HALL_DMAEN_WDGEN_MASK) -#define HALL_DMAEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WDGEN_MASK) >> HALL_DMAEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- generate dma request when phupt flag set - */ -#define HALL_DMAEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_DMAEN_PHUPTEN_SHIFT (30U) -#define HALL_DMAEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHUPTEN_SHIFT) & HALL_DMAEN_PHUPTEN_MASK) -#define HALL_DMAEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHUPTEN_MASK) >> HALL_DMAEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- generate dma request when phpre flag set - */ -#define HALL_DMAEN_PHPREEN_MASK (0x20000000UL) -#define HALL_DMAEN_PHPREEN_SHIFT (29U) -#define HALL_DMAEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHPREEN_SHIFT) & HALL_DMAEN_PHPREEN_MASK) -#define HALL_DMAEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHPREEN_MASK) >> HALL_DMAEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- generate dma request when phdly flag set - */ -#define HALL_DMAEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_DMAEN_PHDLYEN_SHIFT (28U) -#define HALL_DMAEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHDLYEN_SHIFT) & HALL_DMAEN_PHDLYEN_MASK) -#define HALL_DMAEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHDLYEN_MASK) >> HALL_DMAEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- generate dma request when u flag set - */ -#define HALL_DMAEN_UFEN_MASK (0x800000UL) -#define HALL_DMAEN_UFEN_SHIFT (23U) -#define HALL_DMAEN_UFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_UFEN_SHIFT) & HALL_DMAEN_UFEN_MASK) -#define HALL_DMAEN_UFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_UFEN_MASK) >> HALL_DMAEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- generate dma request when v flag set - */ -#define HALL_DMAEN_VFEN_MASK (0x400000UL) -#define HALL_DMAEN_VFEN_SHIFT (22U) -#define HALL_DMAEN_VFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_VFEN_SHIFT) & HALL_DMAEN_VFEN_MASK) -#define HALL_DMAEN_VFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_VFEN_MASK) >> HALL_DMAEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- generate dma request when w flag set - */ -#define HALL_DMAEN_WFEN_MASK (0x200000UL) -#define HALL_DMAEN_WFEN_SHIFT (21U) -#define HALL_DMAEN_WFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WFEN_SHIFT) & HALL_DMAEN_WFEN_MASK) -#define HALL_DMAEN_WFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WFEN_MASK) >> HALL_DMAEN_WFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog count timeout flag - */ -#define HALL_SR_WDGF_MASK (0x80000000UL) -#define HALL_SR_WDGF_SHIFT (31U) -#define HALL_SR_WDGF_SET(x) (((uint32_t)(x) << HALL_SR_WDGF_SHIFT) & HALL_SR_WDGF_MASK) -#define HALL_SR_WDGF_GET(x) (((uint32_t)(x) & HALL_SR_WDGF_MASK) >> HALL_SR_WDGF_SHIFT) - -/* - * PHUPTF (RW) - * - * phase update flag, will set when any of u, v, w signal toggle - */ -#define HALL_SR_PHUPTF_MASK (0x40000000UL) -#define HALL_SR_PHUPTF_SHIFT (30U) -#define HALL_SR_PHUPTF_SET(x) (((uint32_t)(x) << HALL_SR_PHUPTF_SHIFT) & HALL_SR_PHUPTF_MASK) -#define HALL_SR_PHUPTF_GET(x) (((uint32_t)(x) & HALL_SR_PHUPTF_MASK) >> HALL_SR_PHUPTF_SHIFT) - -/* - * PHPREF (RW) - * - * phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - */ -#define HALL_SR_PHPREF_MASK (0x20000000UL) -#define HALL_SR_PHPREF_SHIFT (29U) -#define HALL_SR_PHPREF_SET(x) (((uint32_t)(x) << HALL_SR_PHPREF_SHIFT) & HALL_SR_PHPREF_MASK) -#define HALL_SR_PHPREF_GET(x) (((uint32_t)(x) & HALL_SR_PHPREF_MASK) >> HALL_SR_PHPREF_SHIFT) - -/* - * PHDLYF (RW) - * - * phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - */ -#define HALL_SR_PHDLYF_MASK (0x10000000UL) -#define HALL_SR_PHDLYF_SHIFT (28U) -#define HALL_SR_PHDLYF_SET(x) (((uint32_t)(x) << HALL_SR_PHDLYF_SHIFT) & HALL_SR_PHDLYF_MASK) -#define HALL_SR_PHDLYF_GET(x) (((uint32_t)(x) & HALL_SR_PHDLYF_MASK) >> HALL_SR_PHDLYF_SHIFT) - -/* - * UF (RW) - * - * u flag, will set when u signal toggle - */ -#define HALL_SR_UF_MASK (0x800000UL) -#define HALL_SR_UF_SHIFT (23U) -#define HALL_SR_UF_SET(x) (((uint32_t)(x) << HALL_SR_UF_SHIFT) & HALL_SR_UF_MASK) -#define HALL_SR_UF_GET(x) (((uint32_t)(x) & HALL_SR_UF_MASK) >> HALL_SR_UF_SHIFT) - -/* - * VF (RW) - * - * v flag, will set when v signal toggle - */ -#define HALL_SR_VF_MASK (0x400000UL) -#define HALL_SR_VF_SHIFT (22U) -#define HALL_SR_VF_SET(x) (((uint32_t)(x) << HALL_SR_VF_SHIFT) & HALL_SR_VF_MASK) -#define HALL_SR_VF_GET(x) (((uint32_t)(x) & HALL_SR_VF_MASK) >> HALL_SR_VF_SHIFT) - -/* - * WF (RW) - * - * w flag, will set when w signal toggle - */ -#define HALL_SR_WF_MASK (0x200000UL) -#define HALL_SR_WF_SHIFT (21U) -#define HALL_SR_WF_SET(x) (((uint32_t)(x) << HALL_SR_WF_SHIFT) & HALL_SR_WF_MASK) -#define HALL_SR_WF_GET(x) (((uint32_t)(x) & HALL_SR_WF_MASK) >> HALL_SR_WF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt request when wdg flag set - */ -#define HALL_IRQEN_WDGIE_MASK (0x80000000UL) -#define HALL_IRQEN_WDGIE_SHIFT (31U) -#define HALL_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WDGIE_SHIFT) & HALL_IRQEN_WDGIE_MASK) -#define HALL_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WDGIE_MASK) >> HALL_IRQEN_WDGIE_SHIFT) - -/* - * PHUPTIE (RW) - * - * 1- generate interrupt request when phupt flag set - */ -#define HALL_IRQEN_PHUPTIE_MASK (0x40000000UL) -#define HALL_IRQEN_PHUPTIE_SHIFT (30U) -#define HALL_IRQEN_PHUPTIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHUPTIE_SHIFT) & HALL_IRQEN_PHUPTIE_MASK) -#define HALL_IRQEN_PHUPTIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHUPTIE_MASK) >> HALL_IRQEN_PHUPTIE_SHIFT) - -/* - * PHPREIE (RW) - * - * 1- generate interrupt request when phpre flag set - */ -#define HALL_IRQEN_PHPREIE_MASK (0x20000000UL) -#define HALL_IRQEN_PHPREIE_SHIFT (29U) -#define HALL_IRQEN_PHPREIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHPREIE_SHIFT) & HALL_IRQEN_PHPREIE_MASK) -#define HALL_IRQEN_PHPREIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHPREIE_MASK) >> HALL_IRQEN_PHPREIE_SHIFT) - -/* - * PHDLYIE (RW) - * - * 1- generate interrupt request when phdly flag set - */ -#define HALL_IRQEN_PHDLYIE_MASK (0x10000000UL) -#define HALL_IRQEN_PHDLYIE_SHIFT (28U) -#define HALL_IRQEN_PHDLYIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHDLYIE_SHIFT) & HALL_IRQEN_PHDLYIE_MASK) -#define HALL_IRQEN_PHDLYIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHDLYIE_MASK) >> HALL_IRQEN_PHDLYIE_SHIFT) - -/* - * UFIE (RW) - * - * 1- generate interrupt request when u flag set - */ -#define HALL_IRQEN_UFIE_MASK (0x800000UL) -#define HALL_IRQEN_UFIE_SHIFT (23U) -#define HALL_IRQEN_UFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_UFIE_SHIFT) & HALL_IRQEN_UFIE_MASK) -#define HALL_IRQEN_UFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_UFIE_MASK) >> HALL_IRQEN_UFIE_SHIFT) - -/* - * VFIE (RW) - * - * 1- generate interrupt request when v flag set - */ -#define HALL_IRQEN_VFIE_MASK (0x400000UL) -#define HALL_IRQEN_VFIE_SHIFT (22U) -#define HALL_IRQEN_VFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_VFIE_SHIFT) & HALL_IRQEN_VFIE_MASK) -#define HALL_IRQEN_VFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_VFIE_MASK) >> HALL_IRQEN_VFIE_SHIFT) - -/* - * WFIE (RW) - * - * 1- generate interrupt request when w flag set - */ -#define HALL_IRQEN_WFIE_MASK (0x200000UL) -#define HALL_IRQEN_WFIE_SHIFT (21U) -#define HALL_IRQEN_WFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WFIE_SHIFT) & HALL_IRQEN_WFIE_MASK) -#define HALL_IRQEN_WFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WFIE_MASK) >> HALL_IRQEN_WFIE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: W */ -/* - * WCNT (RO) - * - * wcnt counter - */ -#define HALL_COUNT_W_WCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_W_WCNT_SHIFT (0U) -#define HALL_COUNT_W_WCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_W_WCNT_MASK) >> HALL_COUNT_W_WCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: V */ -/* - * VCNT (RO) - * - * vcnt counter - */ -#define HALL_COUNT_V_VCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_V_VCNT_SHIFT (0U) -#define HALL_COUNT_V_VCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_V_VCNT_MASK) >> HALL_COUNT_V_VCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: U */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define HALL_COUNT_U_DIR_MASK (0x80000000UL) -#define HALL_COUNT_U_DIR_SHIFT (31U) -#define HALL_COUNT_U_DIR_GET(x) (((uint32_t)(x) & HALL_COUNT_U_DIR_MASK) >> HALL_COUNT_U_DIR_SHIFT) - -/* - * USTAT (RO) - * - * this bit indicate U state - */ -#define HALL_COUNT_U_USTAT_MASK (0x40000000UL) -#define HALL_COUNT_U_USTAT_SHIFT (30U) -#define HALL_COUNT_U_USTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_USTAT_MASK) >> HALL_COUNT_U_USTAT_SHIFT) - -/* - * VSTAT (RO) - * - * this bit indicate V state - */ -#define HALL_COUNT_U_VSTAT_MASK (0x20000000UL) -#define HALL_COUNT_U_VSTAT_SHIFT (29U) -#define HALL_COUNT_U_VSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_VSTAT_MASK) >> HALL_COUNT_U_VSTAT_SHIFT) - -/* - * WSTAT (RO) - * - * this bit indicate W state - */ -#define HALL_COUNT_U_WSTAT_MASK (0x10000000UL) -#define HALL_COUNT_U_WSTAT_SHIFT (28U) -#define HALL_COUNT_U_WSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_WSTAT_MASK) >> HALL_COUNT_U_WSTAT_SHIFT) - -/* - * UCNT (RO) - * - * ucnt counter - */ -#define HALL_COUNT_U_UCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_U_UCNT_SHIFT (0U) -#define HALL_COUNT_U_UCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_UCNT_MASK) >> HALL_COUNT_U_UCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TIMER (RO) - * - * 32 bit free run timer - */ -#define HALL_COUNT_TMR_TIMER_MASK (0xFFFFFFFFUL) -#define HALL_COUNT_TMR_TIMER_SHIFT (0U) -#define HALL_COUNT_TMR_TIMER_GET(x) (((uint32_t)(x) & HALL_COUNT_TMR_TIMER_MASK) >> HALL_COUNT_TMR_TIMER_SHIFT) - -/* Bitfield definition for register of struct array HIS: HIS0 */ -/* - * UHIS0 (RO) - * - * copy of ucnt when u signal transition from 0 to 1 - */ -#define HALL_HIS_HIS0_UHIS0_MASK (0xFFFFFFFFUL) -#define HALL_HIS_HIS0_UHIS0_SHIFT (0U) -#define HALL_HIS_HIS0_UHIS0_GET(x) (((uint32_t)(x) & HALL_HIS_HIS0_UHIS0_MASK) >> HALL_HIS_HIS0_UHIS0_SHIFT) - -/* Bitfield definition for register of struct array HIS: HIS1 */ -/* - * UHIS1 (RO) - * - * copy of ucnt when u signal transition from 1 to 0 - */ -#define HALL_HIS_HIS1_UHIS1_MASK (0xFFFFFFFFUL) -#define HALL_HIS_HIS1_UHIS1_SHIFT (0U) -#define HALL_HIS_HIS1_UHIS1_GET(x) (((uint32_t)(x) & HALL_HIS_HIS1_UHIS1_MASK) >> HALL_HIS_HIS1_UHIS1_SHIFT) - - - -/* COUNT register group index macro definition */ -#define HALL_COUNT_CURRENT (0UL) -#define HALL_COUNT_READ (1UL) -#define HALL_COUNT_SNAP0 (2UL) -#define HALL_COUNT_SNAP1 (3UL) - -/* HIS register group index macro definition */ -#define HALL_HIS_U (0UL) -#define HALL_HIS_V (1UL) -#define HALL_HIS_W (2UL) - - -#endif /* HPM_HALL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_i2c_regs.h deleted file mode 100644 index 5c5c0025996..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_i2c_regs.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2C_H -#define HPM_I2C_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ - __RW uint32_t STATUS; /* 0x18: Status Register */ - __RW uint32_t ADDR; /* 0x1C: Address Register */ - __RW uint32_t DATA; /* 0x20: Data Register */ - __RW uint32_t CTRL; /* 0x24: Control Register */ - __RW uint32_t CMD; /* 0x28: Command Register */ - __RW uint32_t SETUP; /* 0x2C: Setup Register */ - __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ -} I2C_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * FIFO Size: - * 0: 2 bytes - * 1: 4 bytes - * 2: 8 bytes - * 3: 16 bytes - */ -#define I2C_CFG_FIFOSIZE_MASK (0x3U) -#define I2C_CFG_FIFOSIZE_SHIFT (0U) -#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * CMPL (RW) - * - * Set to enable the Completion Interrupt. - * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. - * Slave: interrupts when a transaction addressing the controller is completed. - */ -#define I2C_INTEN_CMPL_MASK (0x200U) -#define I2C_INTEN_CMPL_SHIFT (9U) -#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) -#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) - -/* - * BYTERECV (RW) - * - * Set to enable the Byte Receive Interrupt. - * Interrupts when a byte of data is received - * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - */ -#define I2C_INTEN_BYTERECV_MASK (0x100U) -#define I2C_INTEN_BYTERECV_SHIFT (8U) -#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) -#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) - -/* - * BYTETRANS (RW) - * - * Set to enable the Byte Transmit Interrupt. - * Interrupts when a byte of data is transmitted. - */ -#define I2C_INTEN_BYTETRANS_MASK (0x80U) -#define I2C_INTEN_BYTETRANS_SHIFT (7U) -#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) -#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) - -/* - * START (RW) - * - * Set to enable the START Condition Interrupt. - * Interrupts when a START condition/repeated START condition is detected. - */ -#define I2C_INTEN_START_MASK (0x40U) -#define I2C_INTEN_START_SHIFT (6U) -#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) -#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) - -/* - * STOP (RW) - * - * Set to enable the STOP Condition Interrupt - * Interrupts when a STOP condition is detected. - */ -#define I2C_INTEN_STOP_MASK (0x20U) -#define I2C_INTEN_STOP_SHIFT (5U) -#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) -#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) - -/* - * ARBLOSE (RW) - * - * Set to enable the Arbitration Lose Interrupt. - * Master: interrupts when the controller loses the bus arbitration - * Slave: not available in this mode. - */ -#define I2C_INTEN_ARBLOSE_MASK (0x10U) -#define I2C_INTEN_ARBLOSE_SHIFT (4U) -#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) -#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) - -/* - * ADDRHIT (RW) - * - * Set to enable the Address Hit Interrupt. - * Master: interrupts when the addressed slave returned an ACK. - * Slave: interrupts when the controller is addressed. - */ -#define I2C_INTEN_ADDRHIT_MASK (0x8U) -#define I2C_INTEN_ADDRHIT_SHIFT (3U) -#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) -#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RW) - * - * Set to enable the FIFO Half Interrupt. - * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. - * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. - * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - */ -#define I2C_INTEN_FIFOHALF_MASK (0x4U) -#define I2C_INTEN_FIFOHALF_SHIFT (2U) -#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) -#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RW) - * - * Set to enable the FIFO Full Interrupt. - * Interrupts when the FIFO is full. - */ -#define I2C_INTEN_FIFOFULL_MASK (0x2U) -#define I2C_INTEN_FIFOFULL_SHIFT (1U) -#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) -#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RW) - * - * Set to enabled the FIFO Empty Interrupt - * Interrupts when the FIFO is empty. - */ -#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) -#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) -#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) -#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * LINESDA (RO) - * - * Indicates the current status of the SDA line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESDA_MASK (0x4000U) -#define I2C_STATUS_LINESDA_SHIFT (14U) -#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) - -/* - * LINESCL (RO) - * - * Indicates the current status of the SCL line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESCL_MASK (0x2000U) -#define I2C_STATUS_LINESCL_SHIFT (13U) -#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) - -/* - * GENCALL (RO) - * - * Indicates that the address of the current transaction is a general call address: - * 1: General call - * 0: Not general call - */ -#define I2C_STATUS_GENCALL_MASK (0x1000U) -#define I2C_STATUS_GENCALL_SHIFT (12U) -#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) - -/* - * BUSBUSY (RO) - * - * Indicates that the bus is busy - * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus - * 1: Busy - * 0: Not busy - */ -#define I2C_STATUS_BUSBUSY_MASK (0x800U) -#define I2C_STATUS_BUSBUSY_SHIFT (11U) -#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) - -/* - * ACK (RO) - * - * Indicates the type of the last received/transmitted acknowledgement bit: - * 1: ACK - * 0: NACK - */ -#define I2C_STATUS_ACK_MASK (0x400U) -#define I2C_STATUS_ACK_SHIFT (10U) -#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) - -/* - * CMPL (W1C) - * - * Transaction Completion - * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration - * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - */ -#define I2C_STATUS_CMPL_MASK (0x200U) -#define I2C_STATUS_CMPL_SHIFT (9U) -#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) -#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) - -/* - * BYTERECV (W1C) - * - * Indicates that a byte of data has been received. - */ -#define I2C_STATUS_BYTERECV_MASK (0x100U) -#define I2C_STATUS_BYTERECV_SHIFT (8U) -#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) -#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) - -/* - * BYTETRANS (W1C) - * - * Indicates that a byte of data has been transmitted. - */ -#define I2C_STATUS_BYTETRANS_MASK (0x80U) -#define I2C_STATUS_BYTETRANS_SHIFT (7U) -#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) -#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) - -/* - * START (W1C) - * - * Indicates that a START Condition or a repeated START condition has been transmitted/received. - */ -#define I2C_STATUS_START_MASK (0x40U) -#define I2C_STATUS_START_SHIFT (6U) -#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) -#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) - -/* - * STOP (W1C) - * - * Indicates that a STOP Condition has been transmitted/received. - */ -#define I2C_STATUS_STOP_MASK (0x20U) -#define I2C_STATUS_STOP_SHIFT (5U) -#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) -#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) - -/* - * ARBLOSE (W1C) - * - * Indicates that the controller has lost the bus arbitration. - */ -#define I2C_STATUS_ARBLOSE_MASK (0x10U) -#define I2C_STATUS_ARBLOSE_SHIFT (4U) -#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) -#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) - -/* - * ADDRHIT (W1C) - * - * Master: indicates that a slave has responded to the transaction. - * Slave: indicates that a transaction is targeting the controller (including the General Call). - */ -#define I2C_STATUS_ADDRHIT_MASK (0x8U) -#define I2C_STATUS_ADDRHIT_SHIFT (3U) -#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) -#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RO) - * - * Transmitter: Indicates that the FIFO is half-empty. - */ -#define I2C_STATUS_FIFOHALF_MASK (0x4U) -#define I2C_STATUS_FIFOHALF_SHIFT (2U) -#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RO) - * - * Indicates that the FIFO is full. - */ -#define I2C_STATUS_FIFOFULL_MASK (0x2U) -#define I2C_STATUS_FIFOFULL_SHIFT (1U) -#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RO) - * - * Indicates that the FIFO is empty. - */ -#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) -#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) -#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * The slave address. - * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - */ -#define I2C_ADDR_ADDR_MASK (0x3FFU) -#define I2C_ADDR_ADDR_SHIFT (0U) -#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) -#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Write this register to put one byte of data to the FIFO. - * Read this register to get one byte of data from the FIFO. - */ -#define I2C_DATA_DATA_MASK (0xFFU) -#define I2C_DATA_DATA_SHIFT (0U) -#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) -#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * PHASE_START (RW) - * - * Enable this bit to send a START condition at the beginning of transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_START_MASK (0x1000U) -#define I2C_CTRL_PHASE_START_SHIFT (12U) -#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) -#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) - -/* - * PHASE_ADDR (RW) - * - * Enable this bit to send the address after START condition. - * Master mode only. - */ -#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) -#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) -#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) -#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) - -/* - * PHASE_DATA (RW) - * - * Enable this bit to send the data after Address phase. - * Master mode only. - */ -#define I2C_CTRL_PHASE_DATA_MASK (0x400U) -#define I2C_CTRL_PHASE_DATA_SHIFT (10U) -#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) -#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) - -/* - * PHASE_STOP (RW) - * - * Enable this bit to send a STOP condition at the end of a transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_STOP_MASK (0x200U) -#define I2C_CTRL_PHASE_STOP_SHIFT (9U) -#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) -#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) - -/* - * DIR (RW) - * - * Transaction direction - * Master: Set this bit to determine the direction for the next transaction. - * 0: Transmitter - * 1: Receiver - * Slave: The direction of the last received transaction. - * 0: Receiver - * 1: Transmitter - */ -#define I2C_CTRL_DIR_MASK (0x100U) -#define I2C_CTRL_DIR_SHIFT (8U) -#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) -#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) - -/* - * DATACNT (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_MASK (0xFFU) -#define I2C_CTRL_DATACNT_SHIFT (0U) -#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) -#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * Write this register with the following values to perform the corresponding actions: - * 0x0: no action - * 0x1: issue a data transaction (Master only) - * 0x2: respond with an ACK to the received byte - * 0x3: respond with a NACK to the received byte - * 0x4: clear the FIFO - * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) - * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. - * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - */ -#define I2C_CMD_CMD_MASK (0x7U) -#define I2C_CMD_CMD_SHIFT (0U) -#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) -#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) - -/* Bitfield definition for register: SETUP */ -/* - * T_SUDAT (RW) - * - * T_SUDAT defines the data setup time before releasing the SCL. - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) - * tpclk = PCLK period - * TPM = The multiplier value in Timing Parameter Multiplier Register - */ -#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) -#define I2C_SETUP_T_SUDAT_SHIFT (24U) -#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) -#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) - -/* - * T_SP (RW) - * - * T_SP defines the pulse width of spikes that must be suppressed by the input filter. - * Pulse width = T_SP * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_SP_MASK (0xE00000UL) -#define I2C_SETUP_T_SP_SHIFT (21U) -#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) -#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) - -/* - * T_HDDAT (RW) - * - * T_HDDAT defines the data hold time after SCL goes LOW - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) -#define I2C_SETUP_T_HDDAT_SHIFT (16U) -#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) -#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) - -/* - * T_SCLRADIO (RW) - * - * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. - * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) - * 1: ratio = 2 - * 0: ratio = 1 - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) -#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) -#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) -#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) - -/* - * T_SCLHI (RW) - * - * The HIGH period of generated SCL clock is defined by T_SCLHi. - * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) - * The T_SCLHi value must be greater than T_SP and T_HDDAT values. - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) -#define I2C_SETUP_T_SCLHI_SHIFT (4U) -#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) -#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) - -/* - * DMAEN (RW) - * - * Enable the direct memory access mode data transfer. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_DMAEN_MASK (0x8U) -#define I2C_SETUP_DMAEN_SHIFT (3U) -#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) -#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) - -/* - * MASTER (RW) - * - * Configure this device as a master or a slave. - * 1: Master mode - * 0: Slave mode - */ -#define I2C_SETUP_MASTER_MASK (0x4U) -#define I2C_SETUP_MASTER_SHIFT (2U) -#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) -#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) - -/* - * ADDRESSING (RW) - * - * I2C addressing mode: - * 1: 10-bit addressing mode - * 0: 7-bit addressing mode - */ -#define I2C_SETUP_ADDRESSING_MASK (0x2U) -#define I2C_SETUP_ADDRESSING_SHIFT (1U) -#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) -#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) - -/* - * IICEN (RW) - * - * Enable the I2C controller. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_IICEN_MASK (0x1U) -#define I2C_SETUP_IICEN_SHIFT (0U) -#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) -#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) - -/* Bitfield definition for register: TPM */ -/* - * TPM (RW) - * - * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - */ -#define I2C_TPM_TPM_MASK (0x1FU) -#define I2C_TPM_TPM_SHIFT (0U) -#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) -#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) - - - - -#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_i2s_regs.h deleted file mode 100644 index 3d3b34d7aab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_i2s_regs.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2S_H -#define HPM_I2S_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint32_t RFIFO_FILLINGS; /* 0x4: Rx FIFO Filling Level */ - __R uint32_t TFIFO_FILLINGS; /* 0x8: Tx FIFO Filling Level */ - __RW uint32_t FIFO_THRESH; /* 0xC: TX/RX FIFO Threshold setting. */ - __RW uint32_t STA; /* 0x10: Status Registers */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXD[4]; /* 0x20 - 0x2C: Rx Data0 */ - __W uint32_t TXD[4]; /* 0x30 - 0x3C: Tx Data0 */ - __R uint8_t RESERVED1[16]; /* 0x40 - 0x4F: Reserved */ - __RW uint32_t CFGR; /* 0x50: Configruation Regsiters */ - __R uint8_t RESERVED2[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t MISC_CFGR; /* 0x58: Misc configuration Registers */ - __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */ - __RW uint32_t RXDSLOT[4]; /* 0x60 - 0x6C: Rx Slots Enable for Rx Data0 */ - __RW uint32_t TXDSLOT[4]; /* 0x70 - 0x7C: Tx Slots Enable for Tx Data0. */ -} I2S_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST_RX (RW) - * - * software reset the RX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_RX_MASK (0x40000UL) -#define I2S_CTRL_SFTRST_RX_SHIFT (18U) -#define I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK) -#define I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT) - -/* - * SFTRST_TX (RW) - * - * software reset the TX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_TX_MASK (0x20000UL) -#define I2S_CTRL_SFTRST_TX_SHIFT (17U) -#define I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK) -#define I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT) - -/* - * SFTRST_CLKGEN (RW) - * - * software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL) -#define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U) -#define I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK) -#define I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT) - -/* - * TXDNIE (RW) - * - * TX buffer data needed interrupt enable - * 0: TXE interrupt masked - * 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - */ -#define I2S_CTRL_TXDNIE_MASK (0x8000U) -#define I2S_CTRL_TXDNIE_SHIFT (15U) -#define I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK) -#define I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT) - -/* - * RXDAIE (RW) - * - * RX buffer data available interrupt enable - * 0: RXNE interrupt masked - * 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - */ -#define I2S_CTRL_RXDAIE_MASK (0x4000U) -#define I2S_CTRL_RXDAIE_SHIFT (14U) -#define I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK) -#define I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT) - -/* - * ERRIE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define I2S_CTRL_ERRIE_MASK (0x2000U) -#define I2S_CTRL_ERRIE_SHIFT (13U) -#define I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK) -#define I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT) - -/* - * TX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_TX_DMA_EN_MASK (0x1000U) -#define I2S_CTRL_TX_DMA_EN_SHIFT (12U) -#define I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK) -#define I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT) - -/* - * RX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_RX_DMA_EN_MASK (0x800U) -#define I2S_CTRL_RX_DMA_EN_SHIFT (11U) -#define I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK) -#define I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT) - -/* - * TXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_TXFIFOCLR_MASK (0x400U) -#define I2S_CTRL_TXFIFOCLR_SHIFT (10U) -#define I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK) -#define I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT) - -/* - * RXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_RXFIFOCLR_MASK (0x200U) -#define I2S_CTRL_RXFIFOCLR_SHIFT (9U) -#define I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK) -#define I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT) - -/* - * TX_EN (RW) - * - * enable for each TX data pad - */ -#define I2S_CTRL_TX_EN_MASK (0x1E0U) -#define I2S_CTRL_TX_EN_SHIFT (5U) -#define I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK) -#define I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT) - -/* - * RX_EN (RW) - * - * enable for each RX data pad - */ -#define I2S_CTRL_RX_EN_MASK (0x1EU) -#define I2S_CTRL_RX_EN_SHIFT (1U) -#define I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK) -#define I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT) - -/* - * I2S_EN (RW) - * - * enable for the module - */ -#define I2S_CTRL_I2S_EN_MASK (0x1U) -#define I2S_CTRL_I2S_EN_SHIFT (0U) -#define I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK) -#define I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT) - -/* Bitfield definition for register: RFIFO_FILLINGS */ -/* - * RX3 (RO) - * - * RX3 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL) -#define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U) -#define I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT) - -/* - * RX2 (RO) - * - * RX2 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL) -#define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U) -#define I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT) - -/* - * RX1 (RO) - * - * RX1 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U) -#define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U) -#define I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT) - -/* - * RX0 (RO) - * - * RX0 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU) -#define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U) -#define I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT) - -/* Bitfield definition for register: TFIFO_FILLINGS */ -/* - * TX3 (RO) - * - * TX3 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL) -#define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U) -#define I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT) - -/* - * TX2 (RO) - * - * TX2 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL) -#define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U) -#define I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT) - -/* - * TX1 (RO) - * - * TX1 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U) -#define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U) -#define I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT) - -/* - * TX0 (RO) - * - * TX0 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU) -#define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U) -#define I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT) - -/* Bitfield definition for register: FIFO_THRESH */ -/* - * TX (RW) - * - * TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - */ -#define I2S_FIFO_THRESH_TX_MASK (0xFF00U) -#define I2S_FIFO_THRESH_TX_SHIFT (8U) -#define I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK) -#define I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT) - -/* - * RX (RW) - * - * RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - */ -#define I2S_FIFO_THRESH_RX_MASK (0xFFU) -#define I2S_FIFO_THRESH_RX_SHIFT (0U) -#define I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK) -#define I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TX_UD (W1C) - * - * Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - */ -#define I2S_STA_TX_UD_MASK (0x1E000UL) -#define I2S_STA_TX_UD_SHIFT (13U) -#define I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK) -#define I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT) - -/* - * RX_OV (W1C) - * - * Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - */ -#define I2S_STA_RX_OV_MASK (0x1E00U) -#define I2S_STA_RX_OV_SHIFT (9U) -#define I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK) -#define I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT) - -/* - * TX_DN (RO) - * - * Asserted when tx fifo data are needed. - */ -#define I2S_STA_TX_DN_MASK (0x1E0U) -#define I2S_STA_TX_DN_SHIFT (5U) -#define I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT) - -/* - * RX_DA (RO) - * - * Asserted when rx fifo data are available. - */ -#define I2S_STA_RX_DA_MASK (0x1EU) -#define I2S_STA_RX_DA_SHIFT (1U) -#define I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT) - -/* Bitfield definition for register array: RXD */ -/* - * D (RO) - * - */ -#define I2S_RXD_D_MASK (0xFFFFFFFFUL) -#define I2S_RXD_D_SHIFT (0U) -#define I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT) - -/* Bitfield definition for register array: TXD */ -/* - * D (WO) - * - */ -#define I2S_TXD_D_MASK (0xFFFFFFFFUL) -#define I2S_TXD_D_SHIFT (0U) -#define I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK) -#define I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT) - -/* Bitfield definition for register: CFGR */ -/* - * BCLK_GATEOFF (RW) - * - * Gate off the bclk. Asserted to gate-off the BCLK. - */ -#define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL) -#define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U) -#define I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK) -#define I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT) - -/* - * BCLK_DIV (RW) - * - * Linear prescaler to generate BCLK from MCLK. - * BCLK_DIV [8:0] = 0: BCLK=No CLK. - * BCLK_DIV [8:0] = 1: BCLK=MCLK/1 - * BCLK_DIV [8:0] = n: BCLK=MCLK/(n). - * Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL) -#define I2S_CFGR_BCLK_DIV_SHIFT (21U) -#define I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK) -#define I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT) - -/* - * INV_BCLK_OUT (RW) - * - * Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - */ -#define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL) -#define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U) -#define I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK) -#define I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT) - -/* - * INV_BCLK_IN (RW) - * - * Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - */ -#define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL) -#define I2S_CFGR_INV_BCLK_IN_SHIFT (19U) -#define I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK) -#define I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT) - -/* - * INV_FCLK_OUT (RW) - * - * Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - */ -#define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL) -#define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U) -#define I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK) -#define I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT) - -/* - * INV_FCLK_IN (RW) - * - * Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - */ -#define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL) -#define I2S_CFGR_INV_FCLK_IN_SHIFT (17U) -#define I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK) -#define I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT) - -/* - * INV_MCLK_OUT (RW) - * - * Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - */ -#define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL) -#define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U) -#define I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK) -#define I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT) - -/* - * INV_MCLK_IN (RW) - * - * Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - */ -#define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U) -#define I2S_CFGR_INV_MCLK_IN_SHIFT (15U) -#define I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK) -#define I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT) - -/* - * BCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U) -#define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U) -#define I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK) -#define I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT) - -/* - * FCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U) -#define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U) -#define I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK) -#define I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT) - -/* - * MCK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U) -#define I2S_CFGR_MCK_SEL_OP_SHIFT (12U) -#define I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK) -#define I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT) - -/* - * FRAME_EDGE (RW) - * - * The start edge of a frame - * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) - * 1: Rising edge indicates a new frame - */ -#define I2S_CFGR_FRAME_EDGE_MASK (0x800U) -#define I2S_CFGR_FRAME_EDGE_SHIFT (11U) -#define I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK) -#define I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT) - -/* - * CH_MAX (RW) - * - * CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 5'h2: 2 channels - * 5'h4: 4 channels - * ... - * 5‘h10: 16 channels (max) - */ -#define I2S_CFGR_CH_MAX_MASK (0x7C0U) -#define I2S_CFGR_CH_MAX_SHIFT (6U) -#define I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK) -#define I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT) - -/* - * TDM_EN (RW) - * - * TDM mode - * 0: not TDM mode - * 1: TDM mode - */ -#define I2S_CFGR_TDM_EN_MASK (0x20U) -#define I2S_CFGR_TDM_EN_SHIFT (5U) -#define I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK) -#define I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT) - -/* - * STD (RW) - * - * I2S standard selection - * 00: I2S Philips standard. - * 01: MSB justified standard (left justified) - * 10: LSB justified standard (right justified) - * 11: PCM standard - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_STD_MASK (0x18U) -#define I2S_CFGR_STD_SHIFT (3U) -#define I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK) -#define I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT) - -/* - * DATSIZ (RW) - * - * Data length to be transferred - * 00: 16-bit data length - * 01: 24-bit data length - * 10: 32-bit data length - * 11: Not allowed - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_DATSIZ_MASK (0x6U) -#define I2S_CFGR_DATSIZ_SHIFT (1U) -#define I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK) -#define I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT) - -/* - * CHSIZ (RW) - * - * Channel length (number of bits per audio channel) - * 0: 16-bit wide - * 1: 32-bit wide - * The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. - * Note: For correct operation, this bit should be configured when the I2S is disabled. - */ -#define I2S_CFGR_CHSIZ_MASK (0x1U) -#define I2S_CFGR_CHSIZ_SHIFT (0U) -#define I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK) -#define I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT) - -/* Bitfield definition for register: MISC_CFGR */ -/* - * MCLK_GATEOFF (RW) - * - * Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - */ -#define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) -#define I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) - -/* - * MCLKOE (RW) - * - * Master clock output to pad enable - * 0: Master clock output is disabled - * 1: Master clock output is enabled - * Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_MISC_CFGR_MCLKOE_MASK (0x1U) -#define I2S_MISC_CFGR_MCLKOE_SHIFT (0U) -#define I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK) -#define I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT) - -/* Bitfield definition for register array: RXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_RXDSLOT_EN_MASK (0xFFFFU) -#define I2S_RXDSLOT_EN_SHIFT (0U) -#define I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK) -#define I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT) - -/* Bitfield definition for register array: TXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_TXDSLOT_EN_MASK (0xFFFFU) -#define I2S_TXDSLOT_EN_SHIFT (0U) -#define I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK) -#define I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT) - - - -/* RXD register group index macro definition */ -#define I2S_RXD_DATA0 (0UL) -#define I2S_RXD_DATA1 (1UL) -#define I2S_RXD_DATA2 (2UL) -#define I2S_RXD_DATA3 (3UL) - -/* TXD register group index macro definition */ -#define I2S_TXD_DATA0 (0UL) -#define I2S_TXD_DATA1 (1UL) -#define I2S_TXD_DATA2 (2UL) -#define I2S_TXD_DATA3 (3UL) - -/* RXDSLOT register group index macro definition */ -#define I2S_RXDSLOT_DATA0 (0UL) -#define I2S_RXDSLOT_DATA1 (1UL) -#define I2S_RXDSLOT_DATA2 (2UL) -#define I2S_RXDSLOT_DATA3 (3UL) - -/* TXDSLOT register group index macro definition */ -#define I2S_TXDSLOT_DATA0 (0UL) -#define I2S_TXDSLOT_DATA1 (1UL) -#define I2S_TXDSLOT_DATA2 (2UL) -#define I2S_TXDSLOT_DATA3 (3UL) - - -#endif /* HPM_I2S_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ioc_regs.h deleted file mode 100644 index 7bac3840655..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ioc_regs.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOC_H -#define HPM_IOC_H - -typedef struct { - struct { - __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ - __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[488]; -} IOC_Type; - - -/* Bitfield definition for register of struct array PAD: FUNC_CTL */ -/* - * LOOP_BACK (RW) - * - * force input on - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) - -/* - * ANALOG (RW) - * - * select analog pin in pad - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) -#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) -#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) -#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) - -/* - * ALT_SELECT (RW) - * - * alt select - * 0: ALT0 - * 1: ALT1 - * … - * 31:ALT31 - */ -#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) - -/* Bitfield definition for register of struct array PAD: PAD_CTL */ -/* - * HYS (RW) - * - * schmitt trigger enable - * 0: disable - * 1: enable - */ -#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) -#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) -#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) -#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) - -/* - * PRS (RW) - * - * select pull up/down internal resistance strength: - * For pull down, only have 100 Kohm resistance - * For pull up: - * 00: 100 KOhm - * 01: 47 KOhm - * 10: 22 KOhm - * 11: 22 KOhm - */ -#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) -#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) -#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) -#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) - -/* - * PS (RW) - * - * pull select - * 0: pull down - * 1: pull up - */ -#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) -#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) -#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) -#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) - -/* - * PE (RW) - * - * pull enable - * 0: pull disable - * 1: pull enable - */ -#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) -#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) -#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) -#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) - -/* - * KE (RW) - * - * keeper capability enable - * 0: keeper disable - * 1: keeper enable - */ -#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) -#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) -#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) -#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) - -/* - * OD (RW) - * - * open drain - * 0: open drain disable - * 1: open drain enable - */ -#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) -#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) -#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) -#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) - -/* - * SR (RW) - * - * slew rate - * 0: Slow slew rate - * 1: Fast slew rate - */ -#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) -#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) -#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) -#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) - -/* - * SPD (RW) - * - * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise - * 00: Slow frequency slew rate(50Mhz) - * 01: Medium frequency slew rate(100 Mhz) - * 10: Fast frequency slew rate(150 Mhz) - * 11: Max frequency slew rate(200Mhz) - */ -#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) -#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) -#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) -#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) - -/* - * DS (RW) - * - * drive strength - * 1.8V Mode: - * 000: 260 Ohm - * 001: 260 Ohm - * 010: 130 Ohm - * 011: 88 Ohm - * 100: 65 Ohm - * 101: 52 Ohm - * 110: 43 Ohm - * 111: 37 Ohm - * 3.3V Mode: - * 000: 157 Ohm - * 001: 157 Ohm - * 010: 78 Ohm - * 011: 53 Ohm - * 100: 39 Ohm - * 101: 32 Ohm - * 110: 26 Ohm - * 111: 23 Ohm - */ -#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) -#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) -#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) -#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) - - - -/* PAD register group index macro definition */ -#define IOC_PAD_PA00 (0UL) -#define IOC_PAD_PA01 (1UL) -#define IOC_PAD_PA02 (2UL) -#define IOC_PAD_PA03 (3UL) -#define IOC_PAD_PA04 (4UL) -#define IOC_PAD_PA05 (5UL) -#define IOC_PAD_PA06 (6UL) -#define IOC_PAD_PA07 (7UL) -#define IOC_PAD_PA08 (8UL) -#define IOC_PAD_PA09 (9UL) -#define IOC_PAD_PA10 (10UL) -#define IOC_PAD_PA11 (11UL) -#define IOC_PAD_PA12 (12UL) -#define IOC_PAD_PA13 (13UL) -#define IOC_PAD_PA14 (14UL) -#define IOC_PAD_PA15 (15UL) -#define IOC_PAD_PA16 (16UL) -#define IOC_PAD_PA17 (17UL) -#define IOC_PAD_PA18 (18UL) -#define IOC_PAD_PA19 (19UL) -#define IOC_PAD_PA20 (20UL) -#define IOC_PAD_PA21 (21UL) -#define IOC_PAD_PA22 (22UL) -#define IOC_PAD_PA23 (23UL) -#define IOC_PAD_PA24 (24UL) -#define IOC_PAD_PA25 (25UL) -#define IOC_PAD_PA26 (26UL) -#define IOC_PAD_PA27 (27UL) -#define IOC_PAD_PA28 (28UL) -#define IOC_PAD_PA29 (29UL) -#define IOC_PAD_PA30 (30UL) -#define IOC_PAD_PA31 (31UL) -#define IOC_PAD_PB00 (32UL) -#define IOC_PAD_PB01 (33UL) -#define IOC_PAD_PB02 (34UL) -#define IOC_PAD_PB03 (35UL) -#define IOC_PAD_PB04 (36UL) -#define IOC_PAD_PB05 (37UL) -#define IOC_PAD_PB06 (38UL) -#define IOC_PAD_PB07 (39UL) -#define IOC_PAD_PB08 (40UL) -#define IOC_PAD_PB09 (41UL) -#define IOC_PAD_PB10 (42UL) -#define IOC_PAD_PB11 (43UL) -#define IOC_PAD_PB12 (44UL) -#define IOC_PAD_PB13 (45UL) -#define IOC_PAD_PB14 (46UL) -#define IOC_PAD_PB15 (47UL) -#define IOC_PAD_PB16 (48UL) -#define IOC_PAD_PB17 (49UL) -#define IOC_PAD_PB18 (50UL) -#define IOC_PAD_PB19 (51UL) -#define IOC_PAD_PB20 (52UL) -#define IOC_PAD_PB21 (53UL) -#define IOC_PAD_PB22 (54UL) -#define IOC_PAD_PB23 (55UL) -#define IOC_PAD_PB24 (56UL) -#define IOC_PAD_PB25 (57UL) -#define IOC_PAD_PB26 (58UL) -#define IOC_PAD_PB27 (59UL) -#define IOC_PAD_PB28 (60UL) -#define IOC_PAD_PB29 (61UL) -#define IOC_PAD_PB30 (62UL) -#define IOC_PAD_PB31 (63UL) -#define IOC_PAD_PC00 (64UL) -#define IOC_PAD_PC01 (65UL) -#define IOC_PAD_PC02 (66UL) -#define IOC_PAD_PC03 (67UL) -#define IOC_PAD_PC04 (68UL) -#define IOC_PAD_PC05 (69UL) -#define IOC_PAD_PC06 (70UL) -#define IOC_PAD_PC07 (71UL) -#define IOC_PAD_PC08 (72UL) -#define IOC_PAD_PC09 (73UL) -#define IOC_PAD_PC10 (74UL) -#define IOC_PAD_PC11 (75UL) -#define IOC_PAD_PC12 (76UL) -#define IOC_PAD_PC13 (77UL) -#define IOC_PAD_PC14 (78UL) -#define IOC_PAD_PC15 (79UL) -#define IOC_PAD_PC16 (80UL) -#define IOC_PAD_PC17 (81UL) -#define IOC_PAD_PC18 (82UL) -#define IOC_PAD_PC19 (83UL) -#define IOC_PAD_PC20 (84UL) -#define IOC_PAD_PC21 (85UL) -#define IOC_PAD_PC22 (86UL) -#define IOC_PAD_PC23 (87UL) -#define IOC_PAD_PC24 (88UL) -#define IOC_PAD_PC25 (89UL) -#define IOC_PAD_PC26 (90UL) -#define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PX00 (416UL) -#define IOC_PAD_PX01 (417UL) -#define IOC_PAD_PX02 (418UL) -#define IOC_PAD_PX03 (419UL) -#define IOC_PAD_PX04 (420UL) -#define IOC_PAD_PX05 (421UL) -#define IOC_PAD_PX06 (422UL) -#define IOC_PAD_PX07 (423UL) -#define IOC_PAD_PY00 (448UL) -#define IOC_PAD_PY01 (449UL) -#define IOC_PAD_PY02 (450UL) -#define IOC_PAD_PY03 (451UL) -#define IOC_PAD_PY04 (452UL) -#define IOC_PAD_PY05 (453UL) -#define IOC_PAD_PY06 (454UL) -#define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PZ00 (480UL) -#define IOC_PAD_PZ01 (481UL) -#define IOC_PAD_PZ02 (482UL) -#define IOC_PAD_PZ03 (483UL) -#define IOC_PAD_PZ04 (484UL) -#define IOC_PAD_PZ05 (485UL) -#define IOC_PAD_PZ06 (486UL) -#define IOC_PAD_PZ07 (487UL) - - -#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_keym_regs.h deleted file mode 100644 index 0d97ce1ecb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_keym_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_KEYM_H -#define HPM_KEYM_H - -typedef struct { - __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ - __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ - __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ - __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ - __RW uint32_t RNG; /* 0x48: Random number interface behavior */ - __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ -} KEYM_Type; - - -/* Bitfield definition for register array: SOFTMKEY */ -/* - * KEY (RW) - * - * software symmetric key - * key will be scambled to 4 variants for software to use, and replicable on same chip. - * scramble keys are chip different, and not replicable on different chip - * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - */ -#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTMKEY_KEY_SHIFT (0U) -#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) -#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) - -/* Bitfield definition for register array: SOFTPKEY */ -/* - * KEY (RW) - * - * software asymmetric key - * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. - * This key os read once, sencondary read will read out 0 - */ -#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTPKEY_KEY_SHIFT (0U) -#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) -#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) - -/* Bitfield definition for register: SEC_KEY_CTL */ -/* - * LOCK_SEC_CTL (RW) - * - * block secure state key setting being changed - */ -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use origin value in software symmetric key - * 1: use scramble version of software symmetric key - */ -#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use alnertave scramble of fuse symmetric key - */ -#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: NSC_KEY_CTL */ -/* - * LOCK_NSC_CTL (RW) - * - * block non-secure state key setting being changed - */ -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use origin value in fuse symmetric key - */ -#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * non-secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: RNG */ -/* - * BLOCK_RNG_XOR (RW) - * - * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset - * 0: RNG_XOR can be changed by software - * 1: RNG_XOR ignore software change from software - */ -#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) -#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) -#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) -#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) - -/* - * RNG_XOR (RW) - * - * control how SFK is accepted from random number generator - * 0: SFK value replaced by random number input - * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - */ -#define KEYM_RNG_RNG_XOR_MASK (0x1U) -#define KEYM_RNG_RNG_XOR_SHIFT (0U) -#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) -#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) - -/* Bitfield definition for register: READ_CONTROL */ -/* - * BLOCK_PK_READ (RW) - * - * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) - -/* - * BLOCK_SMK_READ (RW) - * - * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) - - - -/* SOFTMKEY register group index macro definition */ -#define KEYM_SOFTMKEY_SFK0 (0UL) -#define KEYM_SOFTMKEY_SFK1 (1UL) -#define KEYM_SOFTMKEY_SFK2 (2UL) -#define KEYM_SOFTMKEY_SFK3 (3UL) -#define KEYM_SOFTMKEY_SFK4 (4UL) -#define KEYM_SOFTMKEY_SFK5 (5UL) -#define KEYM_SOFTMKEY_SFK6 (6UL) -#define KEYM_SOFTMKEY_SFK7 (7UL) - -/* SOFTPKEY register group index macro definition */ -#define KEYM_SOFTPKEY_SPK0 (0UL) -#define KEYM_SOFTPKEY_SPK1 (1UL) -#define KEYM_SOFTPKEY_SPK2 (2UL) -#define KEYM_SOFTPKEY_SPK3 (3UL) -#define KEYM_SOFTPKEY_SPK4 (4UL) -#define KEYM_SOFTPKEY_SPK5 (5UL) -#define KEYM_SOFTPKEY_SPK6 (6UL) -#define KEYM_SOFTPKEY_SPK7 (7UL) - - -#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mbx_regs.h deleted file mode 100644 index d159b97303a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mbx_regs.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_H -#define HPM_MBX_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Command Registers */ - __RW uint32_t SR; /* 0x4: Status Registers */ - __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ - __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ - __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ -} MBX_Type; - - -/* Bitfield definition for register: CR */ -/* - * TXRESET (RW) - * - * Reset TX Fifo and word. - */ -#define MBX_CR_TXRESET_MASK (0x80000000UL) -#define MBX_CR_TXRESET_SHIFT (31U) -#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) -#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) - -/* - * BARCTL (RW) - * - * Bus Access Response Control, when bit 15:14= - * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. - * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. - * 11: reserved. - */ -#define MBX_CR_BARCTL_MASK (0xC000U) -#define MBX_CR_BARCTL_SHIFT (14U) -#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) -#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. - * 1, enable the bus access error interrupt. - * 0, disable the bus access error interrupt. - */ -#define MBX_CR_BEIE_MASK (0x100U) -#define MBX_CR_BEIE_SHIFT (8U) -#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) -#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) - -/* - * TFMAIE (RW) - * - * TX FIFO message available interrupt enable. - * 1, enable the TX FIFO massage available interrupt. - * 0, disable the TX FIFO message available interrupt. - */ -#define MBX_CR_TFMAIE_MASK (0x80U) -#define MBX_CR_TFMAIE_SHIFT (7U) -#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) -#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) - -/* - * TFMEIE (RW) - * - * TX FIFO message empty interrupt enable. - * 1, enable the TX FIFO massage empty interrupt. - * 0, disable the TX FIFO message empty interrupt. - */ -#define MBX_CR_TFMEIE_MASK (0x40U) -#define MBX_CR_TFMEIE_SHIFT (6U) -#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) -#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) - -/* - * RFMAIE (RW) - * - * RX FIFO message available interrupt enable. - * 1, enable the RX FIFO massage available interrupt. - * 0, disable the RX FIFO message available interrupt. - */ -#define MBX_CR_RFMAIE_MASK (0x20U) -#define MBX_CR_RFMAIE_SHIFT (5U) -#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) -#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) - -/* - * RFMFIE (RW) - * - * RX fifo message full interrupt enable. - * 1, enable the RX fifo message full interrupt. - * 0, disable the RX fifo message full interrupt. - */ -#define MBX_CR_RFMFIE_MASK (0x10U) -#define MBX_CR_RFMFIE_SHIFT (4U) -#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) -#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) - -/* - * TWMEIE (RW) - * - * TX word message empty interrupt enable. - * 1, enable the TX word massage empty interrupt. - * 0, disable the TX word message empty interrupt. - */ -#define MBX_CR_TWMEIE_MASK (0x2U) -#define MBX_CR_TWMEIE_SHIFT (1U) -#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) -#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) - -/* - * RWMVIE (RW) - * - * RX word message valid interrupt enable. - * 1, enable the RX word massage valid interrupt. - * 0, disable the RX word message valid interrupt. - */ -#define MBX_CR_RWMVIE_MASK (0x1U) -#define MBX_CR_RWMVIE_SHIFT (0U) -#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) -#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * RFVC (RO) - * - * RX FIFO valid message count - */ -#define MBX_SR_RFVC_MASK (0xF00000UL) -#define MBX_SR_RFVC_SHIFT (20U) -#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) - -/* - * TFEC (RO) - * - * TX FIFO empty message word count - */ -#define MBX_SR_TFEC_MASK (0xF0000UL) -#define MBX_SR_TFEC_SHIFT (16U) -#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) - -/* - * ERRRE (W1C) - * - * bus Error for read when rx word message are still invalid, this bit is W1C bit. - * 1, read from word message when the word message are still invalid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRRE_MASK (0x2000U) -#define MBX_SR_ERRRE_SHIFT (13U) -#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) -#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) - -/* - * EWTRF (W1C) - * - * bus Error for write when tx word message are still valid, this bit is W1C bit. - * 1, write to word message when the word message are still valid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTRF_MASK (0x1000U) -#define MBX_SR_EWTRF_SHIFT (12U) -#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) -#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) - -/* - * ERRFE (W1C) - * - * bus Error for read when rx fifo empty, this bit is W1C bit. - * 1, read from a empty rx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRFE_MASK (0x800U) -#define MBX_SR_ERRFE_SHIFT (11U) -#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) -#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) - -/* - * EWTFF (W1C) - * - * bus Error for write when tx fifo full, this bit is W1C bit. - * 1, write to a fulled tx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTFF_MASK (0x400U) -#define MBX_SR_EWTFF_SHIFT (10U) -#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) -#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) - -/* - * EAIVA (W1C) - * - * bus Error for Accessing Invalid Address; this bit is W1C bit. - * 1, read and write to invalid address in the bus of this block, will set this bit. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EAIVA_MASK (0x200U) -#define MBX_SR_EAIVA_SHIFT (9U) -#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) -#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) - -/* - * EW2RO (W1C) - * - * bus Error for Write to Read Only address; this bit is W1C bit. - * 1, write to read only address happened in the bus of this block. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EW2RO_MASK (0x100U) -#define MBX_SR_EW2RO_SHIFT (8U) -#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) -#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) - -/* - * TFMA (RW) - * - * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. - * 1, TXFIFO message buffer has slot available - * 0, no slot available (fifo full) - */ -#define MBX_SR_TFMA_MASK (0x80U) -#define MBX_SR_TFMA_SHIFT (7U) -#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) -#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) - -/* - * TFME (RW) - * - * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. - * 1, no any message data in TXFIFO from other core. - * 0, there are some data in the 4x32 TX FIFO from other core yet. - */ -#define MBX_SR_TFME_MASK (0x40U) -#define MBX_SR_TFME_SHIFT (6U) -#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) -#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) - -/* - * RFMA (RO) - * - * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, no any data in the 4x32 TXFIFO message buffer. - * 0, there are some data in the the 4x32 TXFIFO message buffer already. - */ -#define MBX_SR_RFMA_MASK (0x20U) -#define MBX_SR_RFMA_SHIFT (5U) -#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) - -/* - * RFMF (RO) - * - * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written 4x32 message in the RXFIFO. - * 0, no 4x32 RX FIFO message from other core yet. - */ -#define MBX_SR_RFMF_MASK (0x10U) -#define MBX_SR_RFMF_SHIFT (4U) -#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) - -/* - * TWME (RO) - * - * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, means this core had write word message to TXREG. - * 0, means no valid word message in the TXREG yet. - */ -#define MBX_SR_TWME_MASK (0x2U) -#define MBX_SR_TWME_SHIFT (1U) -#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) - -/* - * RWMV (RO) - * - * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written word message in the RXREG. - * 0, no valid word message yet in the RXREG. - */ -#define MBX_SR_RWMV_MASK (0x1U) -#define MBX_SR_RWMV_SHIFT (0U) -#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) - -/* Bitfield definition for register: TXREG */ -/* - * TXREG (WO) - * - * Transmit word message to other core. - */ -#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) -#define MBX_TXREG_TXREG_SHIFT (0U) -#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) -#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) - -/* Bitfield definition for register: RXREG */ -/* - * RXREG (RO) - * - * Receive word message from other core. - */ -#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) -#define MBX_RXREG_RXREG_SHIFT (0U) -#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) - -/* Bitfield definition for register array: TXWRD */ -/* - * TXFIFO (WO) - * - * TXFIFO for sending message to other core, FIFO size, 4x32 - * can write one of the word address to push data to the FIFO; - * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - */ -#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_TXWRD_TXFIFO_SHIFT (0U) -#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) -#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) - -/* Bitfield definition for register array: RXWRD */ -/* - * RXFIFO (RO) - * - * RXFIFO for receiving message from other core, FIFO size, 4x32 - * can read one of the word address to pop data to the FIFO; - * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - */ -#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_RXWRD_RXFIFO_SHIFT (0U) -#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) - - - -/* TXWRD register group index macro definition */ -#define MBX_TXWRD_TXFIFO0 (0UL) - -/* RXWRD register group index macro definition */ -#define MBX_RXWRD_RXFIFO0 (0UL) - - -#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mchtmr_regs.h deleted file mode 100644 index d9dfe58a7b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mchtmr_regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCHTMR_H -#define HPM_MCHTMR_H - -typedef struct { - __RW uint64_t MTIME; /* 0x0: Machine Time */ - __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ -} MCHTMR_Type; - - -/* Bitfield definition for register: MTIME */ -/* - * MTIME (RW) - * - * Machine time - */ -#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIME_MTIME_SHIFT (0U) -#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) -#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) - -/* Bitfield definition for register: MTIMECMP */ -/* - * MTIMECMP (RW) - * - * Machine time compare - */ -#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) -#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) -#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) - - - - -#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mono_regs.h deleted file mode 100644 index 2c6c3a3d2fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_mono_regs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MONO_H -#define HPM_MONO_H - -typedef struct { - __RW uint32_t MONOL; /* 0x0: Low part of monotonic counter */ - __RW uint32_t MONOH; /* 0x4: High part of monotonic counter */ -} MONO_Type; - - -/* Bitfield definition for register: MONOL */ -/* - * COUNTER (RW) - * - * low part of monotonica counter, write to this counter will cause counter increase by 1 - */ -#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) -#define MONO_MONOL_COUNTER_SHIFT (0U) -#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) -#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) - -/* Bitfield definition for register: MONOH */ -/* - * EPOCH (RW) - * - * Fuse value for high part of monotonica - */ -#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) -#define MONO_MONOH_EPOCH_SHIFT (16U) -#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) -#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) - -/* - * COUNTER (RW) - * - * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - */ -#define MONO_MONOH_COUNTER_MASK (0xFFFFU) -#define MONO_MONOH_COUNTER_SHIFT (0U) -#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) -#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) - - - - -#endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_otp_regs.h deleted file mode 100644 index feb5f9c2efe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_otp_regs.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OTP_H -#define HPM_OTP_H - -typedef struct { - __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ - __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ - __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ - __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ - __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ - __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ - __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ - __RW uint32_t DATA; /* 0x804: DATA */ - __RW uint32_t ADDR; /* 0x808: ADDR */ - __RW uint32_t CMD; /* 0x80C: CMD */ - __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ - __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ - __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ - __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ - __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ - __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ - __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ - __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ -} OTP_Type; - - -/* Bitfield definition for register array: SHADOW */ -/* - * SHADOW (RW) - * - * shadow register of fuse for pmic area - * for PMIC, index valid for 0-15, for SOC index valid for 16-128 - */ -#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_SHADOW_SHIFT (0U) -#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) -#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) - -/* Bitfield definition for register array: SHADOW_LOCK */ -/* - * LOCK (RW) - * - * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) -#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) -#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register array: FUSE */ -/* - * FUSE (RW) - * - * fuse array, valid in PMIC part only - * read operation will read out value in fuse array - * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - */ -#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_FUSE_SHIFT (0U) -#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) -#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) - -/* Bitfield definition for register array: FUSE_LOCK */ -/* - * LOCK (RW) - * - * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) -#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) -#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK (RW) - * - * unlock word for fuse array operation - * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. - * Please make sure 24M crystal is running and 2.5V LDO working properly - */ -#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) -#define OTP_UNLOCK_UNLOCK_SHIFT (0U) -#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) -#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * data register for non-blocking access - * this register hold dat read from fuse array or data to by programmed to fuse array - */ -#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) -#define OTP_DATA_DATA_SHIFT (0U) -#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) -#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * word address to be read or write - */ -#define OTP_ADDR_ADDR_MASK (0x7FU) -#define OTP_ADDR_ADDR_SHIFT (0U) -#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) -#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * command to access fure array - * "BLOW" will update fuse word at ADDR to value hold in DATA - * "READ" will fetch fuse value in at ADDR to DATA register - */ -#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) -#define OTP_CMD_CMD_SHIFT (0U) -#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) -#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) - -/* Bitfield definition for register: LOAD_REQ */ -/* - * REQUEST (RW) - * - * reload request for 4 regions - * bit0: region0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) -#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) -#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) -#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) - -/* Bitfield definition for register: LOAD_COMP */ -/* - * COMPLETE (RW) - * - * reload complete sign for 4 regions - * bit0: region 0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) -#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) -#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) -#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) - -/* Bitfield definition for register array: REGION */ -/* - * STOP (RW) - * - * stop address of load region, fuse word at end address will NOT be reloaded - * region0: fixed at 8 - * region1: fixed at 16 - * region2: fixed at 0, - * region3: usrer configurable - */ -#define OTP_REGION_STOP_MASK (0x7F00U) -#define OTP_REGION_STOP_SHIFT (8U) -#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) -#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) - -/* - * START (RW) - * - * start address of load region, fuse word at start address will be reloaded - * region0: fixed at 0 - * region1: fixed at 8 - * region2: fixed at 16, - * region3: usrer configurable - */ -#define OTP_REGION_START_MASK (0x7FU) -#define OTP_REGION_START_SHIFT (0U) -#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) -#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) - -/* Bitfield definition for register: INT_FLAG */ -/* - * WRITE (RW) - * - * fuse write flag, write 1 to clear - * 0: fuse is not written or writing - * 1: value in DATA register is programmed into fuse - */ -#define OTP_INT_FLAG_WRITE_MASK (0x4U) -#define OTP_INT_FLAG_WRITE_SHIFT (2U) -#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) -#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read flag, write 1 to clear - * 0: fuse is not read or reading - * 1: fuse value is put in DATA register - */ -#define OTP_INT_FLAG_READ_MASK (0x2U) -#define OTP_INT_FLAG_READ_SHIFT (1U) -#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) -#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load flag, write 1 to clear - * 0: fuse is not loaded or loading - * 1: fuse loaded - */ -#define OTP_INT_FLAG_LOAD_MASK (0x1U) -#define OTP_INT_FLAG_LOAD_SHIFT (0U) -#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) -#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRITE (RW) - * - * fuse write interrupt enable - * 0: fuse write interrupt is not enable - * 1: fuse write interrupt is enable - */ -#define OTP_INT_EN_WRITE_MASK (0x4U) -#define OTP_INT_EN_WRITE_SHIFT (2U) -#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) -#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read interrupt enable - * 0: fuse read interrupt is not enable - * 1: fuse read interrupt is enable - */ -#define OTP_INT_EN_READ_MASK (0x2U) -#define OTP_INT_EN_READ_SHIFT (1U) -#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) -#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load interrupt enable - * 0: fuse load interrupt is not enable - * 1: fuse load interrupt is enable - */ -#define OTP_INT_EN_LOAD_MASK (0x1U) -#define OTP_INT_EN_LOAD_SHIFT (0U) -#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) -#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) - - - -/* SHADOW register group index macro definition */ -#define OTP_SHADOW_SHADOW000 (0UL) -#define OTP_SHADOW_SHADOW001 (1UL) -#define OTP_SHADOW_SHADOW002 (2UL) -#define OTP_SHADOW_SHADOW003 (3UL) -#define OTP_SHADOW_SHADOW004 (4UL) -#define OTP_SHADOW_SHADOW005 (5UL) -#define OTP_SHADOW_SHADOW006 (6UL) -#define OTP_SHADOW_SHADOW007 (7UL) -#define OTP_SHADOW_SHADOW008 (8UL) -#define OTP_SHADOW_SHADOW009 (9UL) -#define OTP_SHADOW_SHADOW010 (10UL) -#define OTP_SHADOW_SHADOW011 (11UL) -#define OTP_SHADOW_SHADOW012 (12UL) -#define OTP_SHADOW_SHADOW013 (13UL) -#define OTP_SHADOW_SHADOW014 (14UL) -#define OTP_SHADOW_SHADOW015 (15UL) -#define OTP_SHADOW_SHADOW016 (16UL) -#define OTP_SHADOW_SHADOW017 (17UL) -#define OTP_SHADOW_SHADOW018 (18UL) -#define OTP_SHADOW_SHADOW019 (19UL) -#define OTP_SHADOW_SHADOW020 (20UL) -#define OTP_SHADOW_SHADOW021 (21UL) -#define OTP_SHADOW_SHADOW022 (22UL) -#define OTP_SHADOW_SHADOW023 (23UL) -#define OTP_SHADOW_SHADOW024 (24UL) -#define OTP_SHADOW_SHADOW025 (25UL) -#define OTP_SHADOW_SHADOW026 (26UL) -#define OTP_SHADOW_SHADOW027 (27UL) -#define OTP_SHADOW_SHADOW028 (28UL) -#define OTP_SHADOW_SHADOW029 (29UL) -#define OTP_SHADOW_SHADOW030 (30UL) -#define OTP_SHADOW_SHADOW031 (31UL) -#define OTP_SHADOW_SHADOW032 (32UL) -#define OTP_SHADOW_SHADOW033 (33UL) -#define OTP_SHADOW_SHADOW034 (34UL) -#define OTP_SHADOW_SHADOW035 (35UL) -#define OTP_SHADOW_SHADOW036 (36UL) -#define OTP_SHADOW_SHADOW037 (37UL) -#define OTP_SHADOW_SHADOW038 (38UL) -#define OTP_SHADOW_SHADOW039 (39UL) -#define OTP_SHADOW_SHADOW040 (40UL) -#define OTP_SHADOW_SHADOW041 (41UL) -#define OTP_SHADOW_SHADOW042 (42UL) -#define OTP_SHADOW_SHADOW043 (43UL) -#define OTP_SHADOW_SHADOW044 (44UL) -#define OTP_SHADOW_SHADOW045 (45UL) -#define OTP_SHADOW_SHADOW046 (46UL) -#define OTP_SHADOW_SHADOW047 (47UL) -#define OTP_SHADOW_SHADOW048 (48UL) -#define OTP_SHADOW_SHADOW049 (49UL) -#define OTP_SHADOW_SHADOW050 (50UL) -#define OTP_SHADOW_SHADOW051 (51UL) -#define OTP_SHADOW_SHADOW052 (52UL) -#define OTP_SHADOW_SHADOW053 (53UL) -#define OTP_SHADOW_SHADOW054 (54UL) -#define OTP_SHADOW_SHADOW055 (55UL) -#define OTP_SHADOW_SHADOW056 (56UL) -#define OTP_SHADOW_SHADOW057 (57UL) -#define OTP_SHADOW_SHADOW058 (58UL) -#define OTP_SHADOW_SHADOW059 (59UL) -#define OTP_SHADOW_SHADOW060 (60UL) -#define OTP_SHADOW_SHADOW061 (61UL) -#define OTP_SHADOW_SHADOW062 (62UL) -#define OTP_SHADOW_SHADOW063 (63UL) -#define OTP_SHADOW_SHADOW064 (64UL) -#define OTP_SHADOW_SHADOW065 (65UL) -#define OTP_SHADOW_SHADOW066 (66UL) -#define OTP_SHADOW_SHADOW067 (67UL) -#define OTP_SHADOW_SHADOW068 (68UL) -#define OTP_SHADOW_SHADOW069 (69UL) -#define OTP_SHADOW_SHADOW070 (70UL) -#define OTP_SHADOW_SHADOW071 (71UL) -#define OTP_SHADOW_SHADOW072 (72UL) -#define OTP_SHADOW_SHADOW073 (73UL) -#define OTP_SHADOW_SHADOW074 (74UL) -#define OTP_SHADOW_SHADOW075 (75UL) -#define OTP_SHADOW_SHADOW076 (76UL) -#define OTP_SHADOW_SHADOW077 (77UL) -#define OTP_SHADOW_SHADOW078 (78UL) -#define OTP_SHADOW_SHADOW079 (79UL) -#define OTP_SHADOW_SHADOW080 (80UL) -#define OTP_SHADOW_SHADOW081 (81UL) -#define OTP_SHADOW_SHADOW082 (82UL) -#define OTP_SHADOW_SHADOW083 (83UL) -#define OTP_SHADOW_SHADOW084 (84UL) -#define OTP_SHADOW_SHADOW085 (85UL) -#define OTP_SHADOW_SHADOW086 (86UL) -#define OTP_SHADOW_SHADOW087 (87UL) -#define OTP_SHADOW_SHADOW088 (88UL) -#define OTP_SHADOW_SHADOW089 (89UL) -#define OTP_SHADOW_SHADOW090 (90UL) -#define OTP_SHADOW_SHADOW091 (91UL) -#define OTP_SHADOW_SHADOW092 (92UL) -#define OTP_SHADOW_SHADOW093 (93UL) -#define OTP_SHADOW_SHADOW094 (94UL) -#define OTP_SHADOW_SHADOW095 (95UL) -#define OTP_SHADOW_SHADOW096 (96UL) -#define OTP_SHADOW_SHADOW097 (97UL) -#define OTP_SHADOW_SHADOW098 (98UL) -#define OTP_SHADOW_SHADOW099 (99UL) -#define OTP_SHADOW_SHADOW100 (100UL) -#define OTP_SHADOW_SHADOW101 (101UL) -#define OTP_SHADOW_SHADOW102 (102UL) -#define OTP_SHADOW_SHADOW103 (103UL) -#define OTP_SHADOW_SHADOW104 (104UL) -#define OTP_SHADOW_SHADOW105 (105UL) -#define OTP_SHADOW_SHADOW106 (106UL) -#define OTP_SHADOW_SHADOW107 (107UL) -#define OTP_SHADOW_SHADOW108 (108UL) -#define OTP_SHADOW_SHADOW109 (109UL) -#define OTP_SHADOW_SHADOW110 (110UL) -#define OTP_SHADOW_SHADOW111 (111UL) -#define OTP_SHADOW_SHADOW112 (112UL) -#define OTP_SHADOW_SHADOW113 (113UL) -#define OTP_SHADOW_SHADOW114 (114UL) -#define OTP_SHADOW_SHADOW115 (115UL) -#define OTP_SHADOW_SHADOW116 (116UL) -#define OTP_SHADOW_SHADOW117 (117UL) -#define OTP_SHADOW_SHADOW118 (118UL) -#define OTP_SHADOW_SHADOW119 (119UL) -#define OTP_SHADOW_SHADOW120 (120UL) -#define OTP_SHADOW_SHADOW121 (121UL) -#define OTP_SHADOW_SHADOW122 (122UL) -#define OTP_SHADOW_SHADOW123 (123UL) -#define OTP_SHADOW_SHADOW124 (124UL) -#define OTP_SHADOW_SHADOW125 (125UL) -#define OTP_SHADOW_SHADOW126 (126UL) -#define OTP_SHADOW_SHADOW127 (127UL) - -/* SHADOW_LOCK register group index macro definition */ -#define OTP_SHADOW_LOCK_LOCK00 (0UL) -#define OTP_SHADOW_LOCK_LOCK01 (1UL) -#define OTP_SHADOW_LOCK_LOCK02 (2UL) -#define OTP_SHADOW_LOCK_LOCK03 (3UL) -#define OTP_SHADOW_LOCK_LOCK04 (4UL) -#define OTP_SHADOW_LOCK_LOCK05 (5UL) -#define OTP_SHADOW_LOCK_LOCK06 (6UL) -#define OTP_SHADOW_LOCK_LOCK07 (7UL) - -/* FUSE register group index macro definition */ -#define OTP_FUSE_FUSE000 (0UL) -#define OTP_FUSE_FUSE001 (1UL) -#define OTP_FUSE_FUSE002 (2UL) -#define OTP_FUSE_FUSE003 (3UL) -#define OTP_FUSE_FUSE004 (4UL) -#define OTP_FUSE_FUSE005 (5UL) -#define OTP_FUSE_FUSE006 (6UL) -#define OTP_FUSE_FUSE007 (7UL) -#define OTP_FUSE_FUSE008 (8UL) -#define OTP_FUSE_FUSE009 (9UL) -#define OTP_FUSE_FUSE010 (10UL) -#define OTP_FUSE_FUSE011 (11UL) -#define OTP_FUSE_FUSE012 (12UL) -#define OTP_FUSE_FUSE013 (13UL) -#define OTP_FUSE_FUSE014 (14UL) -#define OTP_FUSE_FUSE015 (15UL) -#define OTP_FUSE_FUSE016 (16UL) -#define OTP_FUSE_FUSE017 (17UL) -#define OTP_FUSE_FUSE018 (18UL) -#define OTP_FUSE_FUSE019 (19UL) -#define OTP_FUSE_FUSE020 (20UL) -#define OTP_FUSE_FUSE021 (21UL) -#define OTP_FUSE_FUSE022 (22UL) -#define OTP_FUSE_FUSE023 (23UL) -#define OTP_FUSE_FUSE024 (24UL) -#define OTP_FUSE_FUSE025 (25UL) -#define OTP_FUSE_FUSE026 (26UL) -#define OTP_FUSE_FUSE027 (27UL) -#define OTP_FUSE_FUSE028 (28UL) -#define OTP_FUSE_FUSE029 (29UL) -#define OTP_FUSE_FUSE030 (30UL) -#define OTP_FUSE_FUSE031 (31UL) -#define OTP_FUSE_FUSE032 (32UL) -#define OTP_FUSE_FUSE033 (33UL) -#define OTP_FUSE_FUSE034 (34UL) -#define OTP_FUSE_FUSE035 (35UL) -#define OTP_FUSE_FUSE036 (36UL) -#define OTP_FUSE_FUSE037 (37UL) -#define OTP_FUSE_FUSE038 (38UL) -#define OTP_FUSE_FUSE039 (39UL) -#define OTP_FUSE_FUSE040 (40UL) -#define OTP_FUSE_FUSE041 (41UL) -#define OTP_FUSE_FUSE042 (42UL) -#define OTP_FUSE_FUSE043 (43UL) -#define OTP_FUSE_FUSE044 (44UL) -#define OTP_FUSE_FUSE045 (45UL) -#define OTP_FUSE_FUSE046 (46UL) -#define OTP_FUSE_FUSE047 (47UL) -#define OTP_FUSE_FUSE048 (48UL) -#define OTP_FUSE_FUSE049 (49UL) -#define OTP_FUSE_FUSE050 (50UL) -#define OTP_FUSE_FUSE051 (51UL) -#define OTP_FUSE_FUSE052 (52UL) -#define OTP_FUSE_FUSE053 (53UL) -#define OTP_FUSE_FUSE054 (54UL) -#define OTP_FUSE_FUSE055 (55UL) -#define OTP_FUSE_FUSE056 (56UL) -#define OTP_FUSE_FUSE057 (57UL) -#define OTP_FUSE_FUSE058 (58UL) -#define OTP_FUSE_FUSE059 (59UL) -#define OTP_FUSE_FUSE060 (60UL) -#define OTP_FUSE_FUSE061 (61UL) -#define OTP_FUSE_FUSE062 (62UL) -#define OTP_FUSE_FUSE063 (63UL) -#define OTP_FUSE_FUSE064 (64UL) -#define OTP_FUSE_FUSE065 (65UL) -#define OTP_FUSE_FUSE066 (66UL) -#define OTP_FUSE_FUSE067 (67UL) -#define OTP_FUSE_FUSE068 (68UL) -#define OTP_FUSE_FUSE069 (69UL) -#define OTP_FUSE_FUSE070 (70UL) -#define OTP_FUSE_FUSE071 (71UL) -#define OTP_FUSE_FUSE072 (72UL) -#define OTP_FUSE_FUSE073 (73UL) -#define OTP_FUSE_FUSE074 (74UL) -#define OTP_FUSE_FUSE075 (75UL) -#define OTP_FUSE_FUSE076 (76UL) -#define OTP_FUSE_FUSE077 (77UL) -#define OTP_FUSE_FUSE078 (78UL) -#define OTP_FUSE_FUSE079 (79UL) -#define OTP_FUSE_FUSE080 (80UL) -#define OTP_FUSE_FUSE081 (81UL) -#define OTP_FUSE_FUSE082 (82UL) -#define OTP_FUSE_FUSE083 (83UL) -#define OTP_FUSE_FUSE084 (84UL) -#define OTP_FUSE_FUSE085 (85UL) -#define OTP_FUSE_FUSE086 (86UL) -#define OTP_FUSE_FUSE087 (87UL) -#define OTP_FUSE_FUSE088 (88UL) -#define OTP_FUSE_FUSE089 (89UL) -#define OTP_FUSE_FUSE090 (90UL) -#define OTP_FUSE_FUSE091 (91UL) -#define OTP_FUSE_FUSE092 (92UL) -#define OTP_FUSE_FUSE093 (93UL) -#define OTP_FUSE_FUSE094 (94UL) -#define OTP_FUSE_FUSE095 (95UL) -#define OTP_FUSE_FUSE096 (96UL) -#define OTP_FUSE_FUSE097 (97UL) -#define OTP_FUSE_FUSE098 (98UL) -#define OTP_FUSE_FUSE099 (99UL) -#define OTP_FUSE_FUSE100 (100UL) -#define OTP_FUSE_FUSE101 (101UL) -#define OTP_FUSE_FUSE102 (102UL) -#define OTP_FUSE_FUSE103 (103UL) -#define OTP_FUSE_FUSE104 (104UL) -#define OTP_FUSE_FUSE105 (105UL) -#define OTP_FUSE_FUSE106 (106UL) -#define OTP_FUSE_FUSE107 (107UL) -#define OTP_FUSE_FUSE108 (108UL) -#define OTP_FUSE_FUSE109 (109UL) -#define OTP_FUSE_FUSE110 (110UL) -#define OTP_FUSE_FUSE111 (111UL) -#define OTP_FUSE_FUSE112 (112UL) -#define OTP_FUSE_FUSE113 (113UL) -#define OTP_FUSE_FUSE114 (114UL) -#define OTP_FUSE_FUSE115 (115UL) -#define OTP_FUSE_FUSE116 (116UL) -#define OTP_FUSE_FUSE117 (117UL) -#define OTP_FUSE_FUSE118 (118UL) -#define OTP_FUSE_FUSE119 (119UL) -#define OTP_FUSE_FUSE120 (120UL) -#define OTP_FUSE_FUSE121 (121UL) -#define OTP_FUSE_FUSE122 (122UL) -#define OTP_FUSE_FUSE123 (123UL) -#define OTP_FUSE_FUSE124 (124UL) -#define OTP_FUSE_FUSE125 (125UL) -#define OTP_FUSE_FUSE126 (126UL) -#define OTP_FUSE_FUSE127 (127UL) - -/* FUSE_LOCK register group index macro definition */ -#define OTP_FUSE_LOCK_LOCK00 (0UL) -#define OTP_FUSE_LOCK_LOCK01 (1UL) -#define OTP_FUSE_LOCK_LOCK02 (2UL) -#define OTP_FUSE_LOCK_LOCK03 (3UL) -#define OTP_FUSE_LOCK_LOCK04 (4UL) -#define OTP_FUSE_LOCK_LOCK05 (5UL) -#define OTP_FUSE_LOCK_LOCK06 (6UL) -#define OTP_FUSE_LOCK_LOCK07 (7UL) - -/* REGION register group index macro definition */ -#define OTP_REGION_LOAD_REGION0 (0UL) -#define OTP_REGION_LOAD_REGION1 (1UL) -#define OTP_REGION_LOAD_REGION2 (2UL) -#define OTP_REGION_LOAD_REGION3 (3UL) - - -#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pcfg_regs.h deleted file mode 100644 index cfc5f1eba37..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pcfg_regs.h +++ /dev/null @@ -1,902 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PCFG_H -#define HPM_PCFG_H - -typedef struct { - __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ - __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ - __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ - __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ - __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ - __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ - __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ - __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ - __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ - __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ - __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ - __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ - __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ - __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ - __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ - __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ - __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ - __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ - __RW uint32_t RC24M; /* 0x60: RC 24M config */ - __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ - __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ - __R uint32_t STATUS; /* 0x6C: RC 24M track status */ -} PCFG_Type; - - -/* Bitfield definition for register: BANDGAP */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) -#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) -#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) -#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) - -/* - * LOWPOWER_MODE (RW) - * - * Banggap work in low power mode, banggap function limited - * 0: banggap works in normal mode - * 1: banggap works in low power mode - */ -#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) -#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) -#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) -#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Banggap work in power save mode, banggap function normally - * 0: banggap works in high performance mode - * 1: banggap works in power saving mode - */ -#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) -#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) -#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) -#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) - -/* - * VBG_1P0_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) -#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) - -/* - * VBG_P65_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) - -/* - * VBG_P50_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) -#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) -#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) - -/* Bitfield definition for register: LDO1P1 */ -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. - * 700: 700mV - * 720: 720mV - * . . . - * 1320:1320mV - */ -#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) -#define PCFG_LDO1P1_VOLT_SHIFT (0U) -#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) -#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) - -/* Bitfield definition for register: LDO2P5 */ -/* - * READY (RO) - * - * Ready flag, will set 1ms after enabled or voltage change - * 0: LDO is not ready for use - * 1: LDO is ready - */ -#define PCFG_LDO2P5_READY_MASK (0x10000000UL) -#define PCFG_LDO2P5_READY_SHIFT (28U) -#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) -#define PCFG_LDO2P5_ENABLE_SHIFT (16U) -#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) -#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. - * 2125: 2125mV - * 2150: 2150mV - * . . . - * 2900:2900mV - */ -#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) -#define PCFG_LDO2P5_VOLT_SHIFT (0U) -#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) -#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDC is applying new change - * 1: DCDC is ready - */ -#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDC_MODE_READY_SHIFT (28U) -#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDC work mode - * XX0: turn off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDC_MODE_MODE_SHIFT (16U) -#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) -#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) -#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) - -/* - * DISABLE_POWER_LOSS (RW) - * - * disable power loss protection - * 0: power loss protection enabled, DCDC shuts down when power loss - * 1: power loss protection disabled, DCDC try working after power voltage drop - */ -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * output over voltage protection - * 0: protection enabled, DCDC will shut down is output voltage is unexpected high - * 1: protection disabled, DCDC continue to adjust output voltage - */ -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A, - * 1: 1.3A - */ -#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDC_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDC current level, current level is num * 50mA - */ -#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDC_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) -#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) -#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDC_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDC_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) -#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) -#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) -#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) -#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) -#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) -#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) -#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) -#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDC internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) -#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled, - * 1: steping enabled - */ -#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) -#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDC_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDC voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) -#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - */ -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: POWER_TRAP */ -/* - * TRIGGERED (RW) - * - * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. - * 0: low power trap is not triggered - * 1: low power trap triggered - */ -#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) -#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) -#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) -#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) - -/* - * RETENTION (RW) - * - * DCDC enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDC - * 1: reduce DCDC voltage - */ -#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) -#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) -#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) -#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) - -/* - * TRAP (RW) - * - * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered - * 0: trap not enabled, pmic side low power function disabled - * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - */ -#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) -#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) -#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) -#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) - -/* Bitfield definition for register: WAKE_CAUSE */ -/* - * CAUSE (RW) - * - * wake up cause, each bit represents one wake up source, write 1 to clear the register bit - * 0: wake up source is not active during last wakeup - * 1: wake up source is active furing last wakeup - * bit 0: pmic_enable - * bit 1: debug wakeup - * bit 4: fuse interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit11: Security monitor interrupt - * bit12: Security in PMIC event - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit18: BATT Button interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) -#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) -#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: WAKE_MASK */ -/* - * MASK (RW) - * - * mask for wake up sources, each bit represents one wakeup source - * 0: allow source to wake up system - * 1: disallow source to wakeup system - * bit 0: pmic_enable - * bit 1: debug wakeup - * bit 4: fuse interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit11: Security monitor interrupt - * bit12: Security in PMIC event - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit18: BATT Button interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_MASK_MASK_SHIFT (0U) -#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) -#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) - -/* Bitfield definition for register: SCG_CTRL */ -/* - * SCG (RW) - * - * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: reserved - * 10: clock is always off - * 11: clock is always on - * bit0-1: fuse - * bit2-3: sram - * bit4-5: vad - * bit6-7:gpio - * bit8-9:ioc - * bit10-11: timer - * bit12-13:wdog - * bit14-15:uart - * bit16-17:debug - */ -#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) -#define PCFG_SCG_CTRL_SCG_SHIFT (0U) -#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) -#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) - -/* Bitfield definition for register: DEBUG_STOP */ -/* - * CPU1 (RW) - * - * Stop peripheral when CPU1 enter debug mode - * 0: peripheral keep running when CPU1 in debug mode - * 1: peripheral enter debug mode when CPU1 enter debug - */ -#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) -#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) -#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) -#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) - -/* - * CPU0 (RW) - * - * Stop peripheral when CPU0 enter debug mode - * 0: peripheral keep running when CPU0 in debug mode - * 1: peripheral enter debug mode when CPU0 enter debug - */ -#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) -#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) -#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) -#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) - -/* Bitfield definition for register: RC24M */ -/* - * RC_TRIMMED (RW) - * - * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: RC is not trimmed - * 1: RC is trimmed - */ -#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) -#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) -#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) -#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) - -/* - * TRIM_C (RW) - * - * Coarse trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_C_MASK (0x700U) -#define PCFG_RC24M_TRIM_C_SHIFT (8U) -#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) -#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) - -/* - * TRIM_F (RW) - * - * Fine trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_F_MASK (0x1FU) -#define PCFG_RC24M_TRIM_F_SHIFT (0U) -#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) -#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) - -/* Bitfield definition for register: RC24M_TRACK */ -/* - * SEL24M (RW) - * - * Select track reference - * 0: select 32K as reference - * 1: select 24M XTAL as reference - */ -#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) -#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) -#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) -#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) - -/* - * RETURN (RW) - * - * Retrun default value when XTAL loss - * 0: remain last tracking value - * 1: switch to default value - */ -#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) -#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) -#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) -#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) - -/* - * TRACK (RW) - * - * track mode - * 0: RC24M free running - * 1: track RC24M to external XTAL - */ -#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) -#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) -#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) -#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) - -/* Bitfield definition for register: TRACK_TARGET */ -/* - * PRE_DIV (RW) - * - * Divider for reference source - */ -#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) -#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) -#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) -#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) - -/* - * TARGET (RW) - * - * Target frequency multiplier of divided source - */ -#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) -#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) -#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) -#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * SEL32K (RO) - * - * track is using XTAL32K - * 0: track is not using XTAL32K - * 1: track is using XTAL32K - */ -#define PCFG_STATUS_SEL32K_MASK (0x100000UL) -#define PCFG_STATUS_SEL32K_SHIFT (20U) -#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) - -/* - * SEL24M (RO) - * - * track is using XTAL24M - * 0: track is not using XTAL24M - * 1: track is using XTAL24M - */ -#define PCFG_STATUS_SEL24M_MASK (0x10000UL) -#define PCFG_STATUS_SEL24M_SHIFT (16U) -#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) - -/* - * EN_TRIM (RO) - * - * default value takes effect - * 0: default value is invalid - * 1: default value is valid - */ -#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) -#define PCFG_STATUS_EN_TRIM_SHIFT (15U) -#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) - -/* - * TRIM_C (RO) - * - * default coarse trim value - */ -#define PCFG_STATUS_TRIM_C_MASK (0x700U) -#define PCFG_STATUS_TRIM_C_SHIFT (8U) -#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) - -/* - * TRIM_F (RO) - * - * default fine trim value - */ -#define PCFG_STATUS_TRIM_F_MASK (0x1FU) -#define PCFG_STATUS_TRIM_F_SHIFT (0U) -#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) - - - - -#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pdm_regs.h deleted file mode 100644 index 94b550e0ee2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pdm_regs.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDM_H -#define HPM_PDM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t CH_CTRL; /* 0x4: Channel Control Register */ - __W uint32_t ST; /* 0x8: Status Register */ - __RW uint32_t CH_CFG; /* 0xC: Channel Configuration Register */ - __RW uint32_t CIC_CFG; /* 0x10: CIC configuration register */ - __RW uint32_t CTRL_INBUF; /* 0x14: In Buf Control Register */ - __RW uint32_t CTRL_FILT0; /* 0x18: Filter 0 Control Register */ - __RW uint32_t CTRL_FILT1; /* 0x1C: Filter 1 Control Register */ - __RW uint32_t RUN; /* 0x20: Run Register */ - __RW uint32_t MEMADDR; /* 0x24: Memory Access Address */ - __RW uint32_t MEMDATA; /* 0x28: Memory Access Data */ - __RW uint32_t HPF_MA; /* 0x2C: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x30: HPF B Coef Register */ -} PDM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module. Self-clear. - */ -#define PDM_CTRL_SFTRST_MASK (0x80000000UL) -#define PDM_CTRL_SFTRST_SHIFT (31U) -#define PDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PDM_CTRL_SFTRST_SHIFT) & PDM_CTRL_SFTRST_MASK) -#define PDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PDM_CTRL_SFTRST_MASK) >> PDM_CTRL_SFTRST_SHIFT) - -/* - * SOF_FEDGE (RW) - * - * asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - */ -#define PDM_CTRL_SOF_FEDGE_MASK (0x800000UL) -#define PDM_CTRL_SOF_FEDGE_SHIFT (23U) -#define PDM_CTRL_SOF_FEDGE_SET(x) (((uint32_t)(x) << PDM_CTRL_SOF_FEDGE_SHIFT) & PDM_CTRL_SOF_FEDGE_MASK) -#define PDM_CTRL_SOF_FEDGE_GET(x) (((uint32_t)(x) & PDM_CTRL_SOF_FEDGE_MASK) >> PDM_CTRL_SOF_FEDGE_SHIFT) - -/* - * USE_COEF_RAM (RW) - * - * Asserted to use Coef RAM instead of Coef ROM - */ -#define PDM_CTRL_USE_COEF_RAM_MASK (0x100000UL) -#define PDM_CTRL_USE_COEF_RAM_SHIFT (20U) -#define PDM_CTRL_USE_COEF_RAM_SET(x) (((uint32_t)(x) << PDM_CTRL_USE_COEF_RAM_SHIFT) & PDM_CTRL_USE_COEF_RAM_MASK) -#define PDM_CTRL_USE_COEF_RAM_GET(x) (((uint32_t)(x) & PDM_CTRL_USE_COEF_RAM_MASK) >> PDM_CTRL_USE_COEF_RAM_SHIFT) - -/* - * FILT_CRX_ERR_IE (RW) - * - * data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - */ -#define PDM_CTRL_FILT_CRX_ERR_IE_MASK (0x80000UL) -#define PDM_CTRL_FILT_CRX_ERR_IE_SHIFT (19U) -#define PDM_CTRL_FILT_CRX_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) -#define PDM_CTRL_FILT_CRX_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) >> PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) - -/* - * OFIFO_OVFL_ERR_IE (RW) - * - * output fifo overflow error interrupt enable - */ -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x40000UL) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (18U) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) - -/* - * CIC_OVLD_ERR_IE (RW) - * - * CIC overload error interrupt enable - */ -#define PDM_CTRL_CIC_OVLD_ERR_IE_MASK (0x20000UL) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT (17U) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) -#define PDM_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) >> PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) - -/* - * CIC_SAT_ERR_IE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define PDM_CTRL_CIC_SAT_ERR_IE_MASK (0x10000UL) -#define PDM_CTRL_CIC_SAT_ERR_IE_SHIFT (16U) -#define PDM_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) -#define PDM_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) >> PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) - -/* - * DEC_AFT_CIC (RW) - * - * decimation rate after CIC. Now it is forced to be 3. - */ -#define PDM_CTRL_DEC_AFT_CIC_MASK (0xF000U) -#define PDM_CTRL_DEC_AFT_CIC_SHIFT (12U) -#define PDM_CTRL_DEC_AFT_CIC_SET(x) (((uint32_t)(x) << PDM_CTRL_DEC_AFT_CIC_SHIFT) & PDM_CTRL_DEC_AFT_CIC_MASK) -#define PDM_CTRL_DEC_AFT_CIC_GET(x) (((uint32_t)(x) & PDM_CTRL_DEC_AFT_CIC_MASK) >> PDM_CTRL_DEC_AFT_CIC_SHIFT) - -/* - * CAPT_DLY (RW) - * - * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - */ -#define PDM_CTRL_CAPT_DLY_MASK (0x780U) -#define PDM_CTRL_CAPT_DLY_SHIFT (7U) -#define PDM_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << PDM_CTRL_CAPT_DLY_SHIFT) & PDM_CTRL_CAPT_DLY_MASK) -#define PDM_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & PDM_CTRL_CAPT_DLY_MASK) >> PDM_CTRL_CAPT_DLY_SHIFT) - -/* - * PDM_CLK_HFDIV (RW) - * - * The clock divider will work at least 4. - * 0: div-by-2, - * 1: div-by-4 - * . . . - * n: div-by-2*(n+1) - */ -#define PDM_CTRL_PDM_CLK_HFDIV_MASK (0x78U) -#define PDM_CTRL_PDM_CLK_HFDIV_SHIFT (3U) -#define PDM_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_HFDIV_SHIFT) & PDM_CTRL_PDM_CLK_HFDIV_MASK) -#define PDM_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_HFDIV_MASK) >> PDM_CTRL_PDM_CLK_HFDIV_SHIFT) - -/* - * PDM_CLK_DIV_BYPASS (RW) - * - * asserted to bypass the pdm clock divider - */ -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x4U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (2U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) - -/* - * PDM_CLK_OE (RW) - * - * pdm_clk_output_en - */ -#define PDM_CTRL_PDM_CLK_OE_MASK (0x2U) -#define PDM_CTRL_PDM_CLK_OE_SHIFT (1U) -#define PDM_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_OE_SHIFT) & PDM_CTRL_PDM_CLK_OE_MASK) -#define PDM_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_OE_MASK) >> PDM_CTRL_PDM_CLK_OE_SHIFT) - -/* - * HPF_EN (RW) - * - * pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - */ -#define PDM_CTRL_HPF_EN_MASK (0x1U) -#define PDM_CTRL_HPF_EN_SHIFT (0U) -#define PDM_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << PDM_CTRL_HPF_EN_SHIFT) & PDM_CTRL_HPF_EN_MASK) -#define PDM_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & PDM_CTRL_HPF_EN_MASK) >> PDM_CTRL_HPF_EN_SHIFT) - -/* Bitfield definition for register: CH_CTRL */ -/* - * CH_POL (RW) - * - * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - */ -#define PDM_CH_CTRL_CH_POL_MASK (0xFF0000UL) -#define PDM_CH_CTRL_CH_POL_SHIFT (16U) -#define PDM_CH_CTRL_CH_POL_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_POL_SHIFT) & PDM_CH_CTRL_CH_POL_MASK) -#define PDM_CH_CTRL_CH_POL_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_POL_MASK) >> PDM_CH_CTRL_CH_POL_SHIFT) - -/* - * CH_EN (RW) - * - * Asserted to enable the channel. - * Ch8 & 9 are refs. - * Ch0-7 are pdm mics. - */ -#define PDM_CH_CTRL_CH_EN_MASK (0x3FFU) -#define PDM_CH_CTRL_CH_EN_SHIFT (0U) -#define PDM_CH_CTRL_CH_EN_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_EN_SHIFT) & PDM_CH_CTRL_CH_EN_MASK) -#define PDM_CH_CTRL_CH_EN_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_EN_MASK) >> PDM_CH_CTRL_CH_EN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * FILT_CRX_ERR (W1C) - * - * data accessed out of boundary error - */ -#define PDM_ST_FILT_CRX_ERR_MASK (0x8U) -#define PDM_ST_FILT_CRX_ERR_SHIFT (3U) -#define PDM_ST_FILT_CRX_ERR_SET(x) (((uint32_t)(x) << PDM_ST_FILT_CRX_ERR_SHIFT) & PDM_ST_FILT_CRX_ERR_MASK) -#define PDM_ST_FILT_CRX_ERR_GET(x) (((uint32_t)(x) & PDM_ST_FILT_CRX_ERR_MASK) >> PDM_ST_FILT_CRX_ERR_SHIFT) - -/* - * OFIFO_OVFL_ERR (W1C) - * - * output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - */ -#define PDM_ST_OFIFO_OVFL_ERR_MASK (0x4U) -#define PDM_ST_OFIFO_OVFL_ERR_SHIFT (2U) -#define PDM_ST_OFIFO_OVFL_ERR_SET(x) (((uint32_t)(x) << PDM_ST_OFIFO_OVFL_ERR_SHIFT) & PDM_ST_OFIFO_OVFL_ERR_MASK) -#define PDM_ST_OFIFO_OVFL_ERR_GET(x) (((uint32_t)(x) & PDM_ST_OFIFO_OVFL_ERR_MASK) >> PDM_ST_OFIFO_OVFL_ERR_SHIFT) - -/* - * CIC_OVLD_ERR (W1C) - * - * CIC overload error. write 1 clear - */ -#define PDM_ST_CIC_OVLD_ERR_MASK (0x2U) -#define PDM_ST_CIC_OVLD_ERR_SHIFT (1U) -#define PDM_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_OVLD_ERR_SHIFT) & PDM_ST_CIC_OVLD_ERR_MASK) -#define PDM_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_OVLD_ERR_MASK) >> PDM_ST_CIC_OVLD_ERR_SHIFT) - -/* - * CIC_SAT_ERR (W1C) - * - * CIC saturation. Write 1 clear - */ -#define PDM_ST_CIC_SAT_ERR_MASK (0x1U) -#define PDM_ST_CIC_SAT_ERR_SHIFT (0U) -#define PDM_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_SAT_ERR_SHIFT) & PDM_ST_CIC_SAT_ERR_MASK) -#define PDM_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_SAT_ERR_MASK) >> PDM_ST_CIC_SAT_ERR_SHIFT) - -/* Bitfield definition for register: CH_CFG */ -/* - * CH9_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH9_TYPE_MASK (0xC0000UL) -#define PDM_CH_CFG_CH9_TYPE_SHIFT (18U) -#define PDM_CH_CFG_CH9_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH9_TYPE_SHIFT) & PDM_CH_CFG_CH9_TYPE_MASK) -#define PDM_CH_CFG_CH9_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH9_TYPE_MASK) >> PDM_CH_CFG_CH9_TYPE_SHIFT) - -/* - * CH8_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH8_TYPE_MASK (0x30000UL) -#define PDM_CH_CFG_CH8_TYPE_SHIFT (16U) -#define PDM_CH_CFG_CH8_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH8_TYPE_SHIFT) & PDM_CH_CFG_CH8_TYPE_MASK) -#define PDM_CH_CFG_CH8_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH8_TYPE_MASK) >> PDM_CH_CFG_CH8_TYPE_SHIFT) - -/* - * CH7_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH7_TYPE_MASK (0xC000U) -#define PDM_CH_CFG_CH7_TYPE_SHIFT (14U) -#define PDM_CH_CFG_CH7_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH7_TYPE_SHIFT) & PDM_CH_CFG_CH7_TYPE_MASK) -#define PDM_CH_CFG_CH7_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH7_TYPE_MASK) >> PDM_CH_CFG_CH7_TYPE_SHIFT) - -/* - * CH6_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH6_TYPE_MASK (0x3000U) -#define PDM_CH_CFG_CH6_TYPE_SHIFT (12U) -#define PDM_CH_CFG_CH6_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH6_TYPE_SHIFT) & PDM_CH_CFG_CH6_TYPE_MASK) -#define PDM_CH_CFG_CH6_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH6_TYPE_MASK) >> PDM_CH_CFG_CH6_TYPE_SHIFT) - -/* - * CH5_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH5_TYPE_MASK (0xC00U) -#define PDM_CH_CFG_CH5_TYPE_SHIFT (10U) -#define PDM_CH_CFG_CH5_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH5_TYPE_SHIFT) & PDM_CH_CFG_CH5_TYPE_MASK) -#define PDM_CH_CFG_CH5_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH5_TYPE_MASK) >> PDM_CH_CFG_CH5_TYPE_SHIFT) - -/* - * CH4_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH4_TYPE_MASK (0x300U) -#define PDM_CH_CFG_CH4_TYPE_SHIFT (8U) -#define PDM_CH_CFG_CH4_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH4_TYPE_SHIFT) & PDM_CH_CFG_CH4_TYPE_MASK) -#define PDM_CH_CFG_CH4_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH4_TYPE_MASK) >> PDM_CH_CFG_CH4_TYPE_SHIFT) - -/* - * CH3_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH3_TYPE_MASK (0xC0U) -#define PDM_CH_CFG_CH3_TYPE_SHIFT (6U) -#define PDM_CH_CFG_CH3_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH3_TYPE_SHIFT) & PDM_CH_CFG_CH3_TYPE_MASK) -#define PDM_CH_CFG_CH3_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH3_TYPE_MASK) >> PDM_CH_CFG_CH3_TYPE_SHIFT) - -/* - * CH2_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH2_TYPE_MASK (0x30U) -#define PDM_CH_CFG_CH2_TYPE_SHIFT (4U) -#define PDM_CH_CFG_CH2_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH2_TYPE_SHIFT) & PDM_CH_CFG_CH2_TYPE_MASK) -#define PDM_CH_CFG_CH2_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH2_TYPE_MASK) >> PDM_CH_CFG_CH2_TYPE_SHIFT) - -/* - * CH1_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH1_TYPE_MASK (0xCU) -#define PDM_CH_CFG_CH1_TYPE_SHIFT (2U) -#define PDM_CH_CFG_CH1_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH1_TYPE_SHIFT) & PDM_CH_CFG_CH1_TYPE_MASK) -#define PDM_CH_CFG_CH1_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH1_TYPE_MASK) >> PDM_CH_CFG_CH1_TYPE_SHIFT) - -/* - * CH0_TYPE (RW) - * - * Type of Channel 0 - * 2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) - * 2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - */ -#define PDM_CH_CFG_CH0_TYPE_MASK (0x3U) -#define PDM_CH_CFG_CH0_TYPE_SHIFT (0U) -#define PDM_CH_CFG_CH0_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH0_TYPE_SHIFT) & PDM_CH_CFG_CH0_TYPE_MASK) -#define PDM_CH_CFG_CH0_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH0_TYPE_MASK) >> PDM_CH_CFG_CH0_TYPE_SHIFT) - -/* Bitfield definition for register: CIC_CFG */ -/* - * POST_SCALE (RW) - * - * the shift value after CIC results. - */ -#define PDM_CIC_CFG_POST_SCALE_MASK (0xFC00U) -#define PDM_CIC_CFG_POST_SCALE_SHIFT (10U) -#define PDM_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_POST_SCALE_SHIFT) & PDM_CIC_CFG_POST_SCALE_MASK) -#define PDM_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_POST_SCALE_MASK) >> PDM_CIC_CFG_POST_SCALE_SHIFT) - -/* - * SGD (RW) - * - * Sigma_delta_order[1:0] - * 2'b00: 7 - * 2'b01: 6 - * 2'b10: 5 - * Others: unused - */ -#define PDM_CIC_CFG_SGD_MASK (0x300U) -#define PDM_CIC_CFG_SGD_SHIFT (8U) -#define PDM_CIC_CFG_SGD_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_SGD_SHIFT) & PDM_CIC_CFG_SGD_MASK) -#define PDM_CIC_CFG_SGD_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_SGD_MASK) >> PDM_CIC_CFG_SGD_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation factor - */ -#define PDM_CIC_CFG_CIC_DEC_RATIO_MASK (0xFFU) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT (0U) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) -#define PDM_CIC_CFG_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) >> PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) - -/* Bitfield definition for register: CTRL_INBUF */ -/* - * MAX_PTR (RW) - * - * The buf size-1 for each channel - */ -#define PDM_CTRL_INBUF_MAX_PTR_MASK (0x3FC00000UL) -#define PDM_CTRL_INBUF_MAX_PTR_SHIFT (22U) -#define PDM_CTRL_INBUF_MAX_PTR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_MAX_PTR_SHIFT) & PDM_CTRL_INBUF_MAX_PTR_MASK) -#define PDM_CTRL_INBUF_MAX_PTR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_MAX_PTR_MASK) >> PDM_CTRL_INBUF_MAX_PTR_SHIFT) - -/* - * PITCH (RW) - * - * The spacing between starting address of adjacent channels - */ -#define PDM_CTRL_INBUF_PITCH_MASK (0x3FF800UL) -#define PDM_CTRL_INBUF_PITCH_SHIFT (11U) -#define PDM_CTRL_INBUF_PITCH_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_PITCH_SHIFT) & PDM_CTRL_INBUF_PITCH_MASK) -#define PDM_CTRL_INBUF_PITCH_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_PITCH_MASK) >> PDM_CTRL_INBUF_PITCH_SHIFT) - -/* - * START_ADDR (RW) - * - * The starting address of channel 0 in filter data buffer - */ -#define PDM_CTRL_INBUF_START_ADDR_MASK (0x7FFU) -#define PDM_CTRL_INBUF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_INBUF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_START_ADDR_SHIFT) & PDM_CTRL_INBUF_START_ADDR_MASK) -#define PDM_CTRL_INBUF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_START_ADDR_MASK) >> PDM_CTRL_INBUF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT0 */ -/* - * COEF_LEN_M0 (RW) - * - * Coef length of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_LEN_M0_MASK (0xFF00U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT (8U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) -#define PDM_CTRL_FILT0_COEF_LEN_M0_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) >> PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT0_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT1 */ -/* - * COEF_LEN_M1 (RW) - * - * Coef length of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_LEN_M1_MASK (0xFF00U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT (8U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) -#define PDM_CTRL_FILT1_COEF_LEN_M1_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) >> PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT1_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: RUN */ -/* - * PDM_EN (RW) - * - * Asserted to enable the module - */ -#define PDM_RUN_PDM_EN_MASK (0x1U) -#define PDM_RUN_PDM_EN_SHIFT (0U) -#define PDM_RUN_PDM_EN_SET(x) (((uint32_t)(x) << PDM_RUN_PDM_EN_SHIFT) & PDM_RUN_PDM_EN_MASK) -#define PDM_RUN_PDM_EN_GET(x) (((uint32_t)(x) & PDM_RUN_PDM_EN_MASK) >> PDM_RUN_PDM_EN_SHIFT) - -/* Bitfield definition for register: MEMADDR */ -/* - * ADDR (RW) - * - * 0--0x0FFFFFFF: COEF_RAM - * 0x10000000--0x1FFFFFFF: DATA_RAM - */ -#define PDM_MEMADDR_ADDR_MASK (0xFFFFFFFFUL) -#define PDM_MEMADDR_ADDR_SHIFT (0U) -#define PDM_MEMADDR_ADDR_SET(x) (((uint32_t)(x) << PDM_MEMADDR_ADDR_SHIFT) & PDM_MEMADDR_ADDR_MASK) -#define PDM_MEMADDR_ADDR_GET(x) (((uint32_t)(x) & PDM_MEMADDR_ADDR_MASK) >> PDM_MEMADDR_ADDR_SHIFT) - -/* Bitfield definition for register: MEMDATA */ -/* - * DATA (RW) - * - * The data write-to/read-from buffer - */ -#define PDM_MEMDATA_DATA_MASK (0xFFFFFFFFUL) -#define PDM_MEMDATA_DATA_SHIFT (0U) -#define PDM_MEMDATA_DATA_SET(x) (((uint32_t)(x) << PDM_MEMDATA_DATA_SHIFT) & PDM_MEMDATA_DATA_MASK) -#define PDM_MEMDATA_DATA_GET(x) (((uint32_t)(x) & PDM_MEMDATA_DATA_MASK) >> PDM_MEMDATA_DATA_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define PDM_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_MA_COEF_SHIFT (0U) -#define PDM_HPF_MA_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_MA_COEF_SHIFT) & PDM_HPF_MA_COEF_MASK) -#define PDM_HPF_MA_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_MA_COEF_MASK) >> PDM_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define PDM_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_B_COEF_SHIFT (0U) -#define PDM_HPF_B_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_B_COEF_SHIFT) & PDM_HPF_B_COEF_MASK) -#define PDM_HPF_B_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_B_COEF_MASK) >> PDM_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_PDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pgpr_regs.h deleted file mode 100644 index acf20cfecd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pgpr_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PGPR_H -#define HPM_PGPR_H - -typedef struct { - __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ - __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ - __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ - __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ - __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ - __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ - __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ - __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ - __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ - __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ - __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ - __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ - __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ - __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ - __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ - __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ -} PGPR_Type; - - -/* Bitfield definition for register: PMIC_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) -#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) -#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) -#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) -#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR04 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) -#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR05 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) -#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR06 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) -#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR07 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) -#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR08 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) -#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR09 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) -#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR10 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) -#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR11 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) -#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR12 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) -#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR13 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) -#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR14 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) -#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR15 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) -#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) - - - - -#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_plic_regs.h deleted file mode 100644 index eb5a6504d9c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_plic_regs.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_H -#define HPM_PLIC_H - -typedef struct { - __RW uint32_t FEATURE; /* 0x0: Feature enable register */ - __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ - __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ - __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ - __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ - __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ - __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ - __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ - __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ - __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ - struct { - __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ - __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ - } TARGETINT[2]; - __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */ - struct { - __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ - __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ - __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ - __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ - __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ - } TARGETCONFIG[2]; -} PLIC_Type; - - -/* Bitfield definition for register: FEATURE */ -/* - * VECTORED (RW) - * - * Vector mode enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_VECTORED_MASK (0x2U) -#define PLIC_FEATURE_VECTORED_SHIFT (1U) -#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) -#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) - -/* - * PREEMPT (RW) - * - * Preemptive priority interrupt enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_PREEMPT_MASK (0x1U) -#define PLIC_FEATURE_PREEMPT_SHIFT (0U) -#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) -#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) - -/* Bitfield definition for register array: PRIORITY */ -/* - * PRIORITY (RW) - * - * Interrupt source priority. The valid range of this field is 0-7. - * 0: Never interrupt - * 1-7: Interrupt source priority. The larger the value, the higher the priority. - */ -#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) -#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) -#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) -#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) - -/* Bitfield definition for register array: PENDING */ -/* - * INTERRUPT (RW) - * - * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - */ -#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_PENDING_INTERRUPT_SHIFT (0U) -#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) -#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register array: TRIGGER */ -/* - * INTERRUPT (RO) - * - * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. - * 0: Level-triggered interrupt - * 1: Edge-triggered interrupt - */ -#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) -#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) - -/* Bitfield definition for register: NUMBER */ -/* - * NUM_TARGET (RO) - * - * The number of supported targets - */ -#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) -#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) -#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) - -/* - * NUM_INTERRUPT (RO) - * - * The number of supported interrupt sources - */ -#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) -#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) -#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INFO */ -/* - * MAX_PRIORITY (RO) - * - * The maximum priority supported - */ -#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) -#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) -#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) - -/* - * VERSION (RO) - * - * The version of the PLIC design - */ -#define PLIC_INFO_VERSION_MASK (0xFFFFU) -#define PLIC_INFO_VERSION_SHIFT (0U) -#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) - -/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ -/* - * INTERRUPT (RW) - * - * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - */ -#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) -#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ -/* - * THRESHOLD (RW) - * - * Interrupt priority threshold. - */ -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ -/* - * PRIORITY_PREEMPTED (RW) - * - * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - */ -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) - - - -/* PRIORITY register group index macro definition */ -#define PLIC_PRIORITY_PRIORITY1 (0UL) -#define PLIC_PRIORITY_PRIORITY2 (1UL) -#define PLIC_PRIORITY_PRIORITY3 (2UL) -#define PLIC_PRIORITY_PRIORITY4 (3UL) -#define PLIC_PRIORITY_PRIORITY5 (4UL) -#define PLIC_PRIORITY_PRIORITY6 (5UL) -#define PLIC_PRIORITY_PRIORITY7 (6UL) -#define PLIC_PRIORITY_PRIORITY8 (7UL) -#define PLIC_PRIORITY_PRIORITY9 (8UL) -#define PLIC_PRIORITY_PRIORITY10 (9UL) -#define PLIC_PRIORITY_PRIORITY11 (10UL) -#define PLIC_PRIORITY_PRIORITY12 (11UL) -#define PLIC_PRIORITY_PRIORITY13 (12UL) -#define PLIC_PRIORITY_PRIORITY14 (13UL) -#define PLIC_PRIORITY_PRIORITY15 (14UL) -#define PLIC_PRIORITY_PRIORITY16 (15UL) -#define PLIC_PRIORITY_PRIORITY17 (16UL) -#define PLIC_PRIORITY_PRIORITY18 (17UL) -#define PLIC_PRIORITY_PRIORITY19 (18UL) -#define PLIC_PRIORITY_PRIORITY20 (19UL) -#define PLIC_PRIORITY_PRIORITY21 (20UL) -#define PLIC_PRIORITY_PRIORITY22 (21UL) -#define PLIC_PRIORITY_PRIORITY23 (22UL) -#define PLIC_PRIORITY_PRIORITY24 (23UL) -#define PLIC_PRIORITY_PRIORITY25 (24UL) -#define PLIC_PRIORITY_PRIORITY26 (25UL) -#define PLIC_PRIORITY_PRIORITY27 (26UL) -#define PLIC_PRIORITY_PRIORITY28 (27UL) -#define PLIC_PRIORITY_PRIORITY29 (28UL) -#define PLIC_PRIORITY_PRIORITY30 (29UL) -#define PLIC_PRIORITY_PRIORITY31 (30UL) -#define PLIC_PRIORITY_PRIORITY32 (31UL) -#define PLIC_PRIORITY_PRIORITY33 (32UL) -#define PLIC_PRIORITY_PRIORITY34 (33UL) -#define PLIC_PRIORITY_PRIORITY35 (34UL) -#define PLIC_PRIORITY_PRIORITY36 (35UL) -#define PLIC_PRIORITY_PRIORITY37 (36UL) -#define PLIC_PRIORITY_PRIORITY38 (37UL) -#define PLIC_PRIORITY_PRIORITY39 (38UL) -#define PLIC_PRIORITY_PRIORITY40 (39UL) -#define PLIC_PRIORITY_PRIORITY41 (40UL) -#define PLIC_PRIORITY_PRIORITY42 (41UL) -#define PLIC_PRIORITY_PRIORITY43 (42UL) -#define PLIC_PRIORITY_PRIORITY44 (43UL) -#define PLIC_PRIORITY_PRIORITY45 (44UL) -#define PLIC_PRIORITY_PRIORITY46 (45UL) -#define PLIC_PRIORITY_PRIORITY47 (46UL) -#define PLIC_PRIORITY_PRIORITY48 (47UL) -#define PLIC_PRIORITY_PRIORITY49 (48UL) -#define PLIC_PRIORITY_PRIORITY50 (49UL) -#define PLIC_PRIORITY_PRIORITY51 (50UL) -#define PLIC_PRIORITY_PRIORITY52 (51UL) -#define PLIC_PRIORITY_PRIORITY53 (52UL) -#define PLIC_PRIORITY_PRIORITY54 (53UL) -#define PLIC_PRIORITY_PRIORITY55 (54UL) -#define PLIC_PRIORITY_PRIORITY56 (55UL) -#define PLIC_PRIORITY_PRIORITY57 (56UL) -#define PLIC_PRIORITY_PRIORITY58 (57UL) -#define PLIC_PRIORITY_PRIORITY59 (58UL) -#define PLIC_PRIORITY_PRIORITY60 (59UL) -#define PLIC_PRIORITY_PRIORITY61 (60UL) -#define PLIC_PRIORITY_PRIORITY62 (61UL) -#define PLIC_PRIORITY_PRIORITY63 (62UL) -#define PLIC_PRIORITY_PRIORITY64 (63UL) -#define PLIC_PRIORITY_PRIORITY65 (64UL) -#define PLIC_PRIORITY_PRIORITY66 (65UL) -#define PLIC_PRIORITY_PRIORITY67 (66UL) -#define PLIC_PRIORITY_PRIORITY68 (67UL) -#define PLIC_PRIORITY_PRIORITY69 (68UL) -#define PLIC_PRIORITY_PRIORITY70 (69UL) -#define PLIC_PRIORITY_PRIORITY71 (70UL) -#define PLIC_PRIORITY_PRIORITY72 (71UL) -#define PLIC_PRIORITY_PRIORITY73 (72UL) -#define PLIC_PRIORITY_PRIORITY74 (73UL) -#define PLIC_PRIORITY_PRIORITY75 (74UL) -#define PLIC_PRIORITY_PRIORITY76 (75UL) -#define PLIC_PRIORITY_PRIORITY77 (76UL) -#define PLIC_PRIORITY_PRIORITY78 (77UL) -#define PLIC_PRIORITY_PRIORITY79 (78UL) -#define PLIC_PRIORITY_PRIORITY80 (79UL) -#define PLIC_PRIORITY_PRIORITY81 (80UL) -#define PLIC_PRIORITY_PRIORITY82 (81UL) -#define PLIC_PRIORITY_PRIORITY83 (82UL) -#define PLIC_PRIORITY_PRIORITY84 (83UL) -#define PLIC_PRIORITY_PRIORITY85 (84UL) -#define PLIC_PRIORITY_PRIORITY86 (85UL) -#define PLIC_PRIORITY_PRIORITY87 (86UL) -#define PLIC_PRIORITY_PRIORITY88 (87UL) -#define PLIC_PRIORITY_PRIORITY89 (88UL) -#define PLIC_PRIORITY_PRIORITY90 (89UL) -#define PLIC_PRIORITY_PRIORITY91 (90UL) -#define PLIC_PRIORITY_PRIORITY92 (91UL) -#define PLIC_PRIORITY_PRIORITY93 (92UL) -#define PLIC_PRIORITY_PRIORITY94 (93UL) -#define PLIC_PRIORITY_PRIORITY95 (94UL) -#define PLIC_PRIORITY_PRIORITY96 (95UL) -#define PLIC_PRIORITY_PRIORITY97 (96UL) -#define PLIC_PRIORITY_PRIORITY98 (97UL) -#define PLIC_PRIORITY_PRIORITY99 (98UL) -#define PLIC_PRIORITY_PRIORITY100 (99UL) -#define PLIC_PRIORITY_PRIORITY101 (100UL) -#define PLIC_PRIORITY_PRIORITY102 (101UL) -#define PLIC_PRIORITY_PRIORITY103 (102UL) -#define PLIC_PRIORITY_PRIORITY104 (103UL) -#define PLIC_PRIORITY_PRIORITY105 (104UL) -#define PLIC_PRIORITY_PRIORITY106 (105UL) -#define PLIC_PRIORITY_PRIORITY107 (106UL) -#define PLIC_PRIORITY_PRIORITY108 (107UL) -#define PLIC_PRIORITY_PRIORITY109 (108UL) -#define PLIC_PRIORITY_PRIORITY110 (109UL) -#define PLIC_PRIORITY_PRIORITY111 (110UL) -#define PLIC_PRIORITY_PRIORITY112 (111UL) -#define PLIC_PRIORITY_PRIORITY113 (112UL) -#define PLIC_PRIORITY_PRIORITY114 (113UL) -#define PLIC_PRIORITY_PRIORITY115 (114UL) -#define PLIC_PRIORITY_PRIORITY116 (115UL) -#define PLIC_PRIORITY_PRIORITY117 (116UL) -#define PLIC_PRIORITY_PRIORITY118 (117UL) -#define PLIC_PRIORITY_PRIORITY119 (118UL) -#define PLIC_PRIORITY_PRIORITY120 (119UL) -#define PLIC_PRIORITY_PRIORITY121 (120UL) -#define PLIC_PRIORITY_PRIORITY122 (121UL) -#define PLIC_PRIORITY_PRIORITY123 (122UL) -#define PLIC_PRIORITY_PRIORITY124 (123UL) -#define PLIC_PRIORITY_PRIORITY125 (124UL) -#define PLIC_PRIORITY_PRIORITY126 (125UL) -#define PLIC_PRIORITY_PRIORITY127 (126UL) - -/* PENDING register group index macro definition */ -#define PLIC_PENDING_PENDING0 (0UL) -#define PLIC_PENDING_PENDING1 (1UL) -#define PLIC_PENDING_PENDING2 (2UL) -#define PLIC_PENDING_PENDING3 (3UL) - -/* TRIGGER register group index macro definition */ -#define PLIC_TRIGGER_TRIGGER0 (0UL) -#define PLIC_TRIGGER_TRIGGER1 (1UL) -#define PLIC_TRIGGER_TRIGGER2 (2UL) -#define PLIC_TRIGGER_TRIGGER3 (3UL) - -/* INTEN register group index macro definition */ -#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) -#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) -#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) -#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) - -/* TARGETINT register group index macro definition */ -#define PLIC_TARGETINT_TARGET0 (0UL) -#define PLIC_TARGETINT_TARGET1 (1UL) - -/* TARGETCONFIG register group index macro definition */ -#define PLIC_TARGETCONFIG_TARGET0 (0UL) -#define PLIC_TARGETCONFIG_TARGET1 (1UL) - - -#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_plic_sw_regs.h deleted file mode 100644 index 998dafa2d57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_plic_sw_regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_SW_H -#define HPM_PLIC_SW_H - -typedef struct { - __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ - __RW uint32_t PENDING; /* 0x1000: Pending status */ - __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ - __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ - __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ - __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ -} PLIC_SW_Type; - - -/* Bitfield definition for register: PENDING */ -/* - * INTERRUPT (RW) - * - * writing 1 to trigger software interrupt - */ -#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) -#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) -#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) -#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * INTERRUPT (RW) - * - * enable software interrupt - */ -#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) -#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) -#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) - - - - -#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pllctlv2_regs.h deleted file mode 100644 index f9bdd046b74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pllctlv2_regs.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLLCTLV2_H -#define HPM_PLLCTLV2_H - -typedef struct { - __RW uint32_t XTAL; /* 0x0: OSC configuration */ - __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ - struct { - __RW uint32_t MFI; /* 0x80: PLL0 multiple register */ - __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */ - __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */ - __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */ - __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */ - __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */ - __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */ - __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */ - __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */ - __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ - __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ - __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ - } PLL[3]; -} PLLCTLV2_Type; - - -/* Bitfield definition for register: XTAL */ -/* - * BUSY (RO) - * - * Busy flag - * 0: Oscillator is working or shutdown - * 1: Oscillator is changing status - */ -#define PLLCTLV2_XTAL_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_XTAL_BUSY_SHIFT (31U) -#define PLLCTLV2_XTAL_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTLV2_XTAL_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_XTAL_RESPONSE_SHIFT (29U) -#define PLLCTLV2_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTLV2_XTAL_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_XTAL_ENABLE_SHIFT (28U) -#define PLLCTLV2_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT) - -/* - * RAMP_TIME (RW) - * - * Rampup time of XTAL oscillator in cycles of RC24M clock - * 0: 0 cycle - * 1: 1 cycle - * 2: 2 cycle - * 1048575: 1048575 cycles - */ -#define PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) -#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) -#define PLLCTLV2_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK) -#define PLLCTLV2_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFI */ -/* - * BUSY (RO) - * - * Busy flag - * 0: PLL is stable or shutdown - * 1: PLL is changing status - */ -#define PLLCTLV2_PLL_MFI_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_MFI_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_MFI_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * PLL status - * 0: PLL is not stable - * 1: PLL is stable for use - */ -#define PLLCTLV2_PLL_MFI_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_MFI_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * PLL enable status - * 0: PLL is off - * 1: PLL is on - */ -#define PLLCTLV2_PLL_MFI_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_MFI_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT) - -/* - * MFI (RW) - * - * loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) - * 0-15: invalid - * 16: divide by 16 - * 17: divide by17 - * . . . - * 42: divide by 42 - * 43~:invalid - */ -#define PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) -#define PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) -#define PLLCTLV2_PLL_MFI_MFI_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK) -#define PLLCTLV2_PLL_MFI_MFI_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFN */ -/* - * MFN (RW) - * - * Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - */ -#define PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) -#define PLLCTLV2_PLL_MFN_MFN_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK) -#define PLLCTLV2_PLL_MFN_MFN_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFD */ -/* - * MFD (RW) - * - * Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - */ -#define PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) -#define PLLCTLV2_PLL_MFD_MFD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK) -#define PLLCTLV2_PLL_MFD_MFD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STEP */ -/* - * STEP (RW) - * - * Step of spread spectrum modulator. - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STEP_STEP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) -#define PLLCTLV2_PLL_SS_STEP_STEP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STOP */ -/* - * STOP (RW) - * - * Stop point of spread spectrum modulator - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STOP_STOP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) -#define PLLCTLV2_PLL_SS_STOP_STOP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) - -/* Bitfield definition for register of struct array PLL: CONFIG */ -/* - * SPREAD (RW) - * - * Enable spread spectrum function. This field supports changing during PLL running. - */ -#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK (0x100U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT (8U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) -#define PLLCTLV2_PLL_CONFIG_SPREAD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) - -/* - * REFSEL (RW) - * - * Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. - * 0: XTAL24M - * 1: IRC24M - */ -#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK (0x1U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT (0U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) -#define PLLCTLV2_PLL_CONFIG_REFSEL_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) - -/* Bitfield definition for register of struct array PLL: LOCKTIME */ -/* - * LOCKTIME (RW) - * - * Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - */ -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: STEPTIME */ -/* - * STEPTIME (RW) - * - * Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - */ -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: ADVANCED */ -/* - * SLOW (RW) - * - * Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. - * 0: fast lock enabled, lock time is 100us - * 1: fast lock disabled, lock time is 400us - */ -#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK (0x10000000UL) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT (28U) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) -#define PLLCTLV2_PLL_ADVANCED_SLOW_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither function - */ -#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK (0x1000000UL) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT (24U) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) -#define PLLCTLV2_PLL_ADVANCED_DITHER_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV0 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTLV2_PLL_DIV_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_DIV_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Divider response status - * 0: Divider is not stable - * 1: Divider is stable for use - */ -#define PLLCTLV2_PLL_DIV_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Divider enable status - * 0: Divider is off - * 1: Divider is on - */ -#define PLLCTLV2_PLL_DIV_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider factor, divider factor is DIV/5 + 1 - * 0: divide by 1 - * 1: divide by 1.2 - * 2: divide by 1.4 - * . . . - * 63: divide by 13.6 - */ -#define PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) -#define PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) -#define PLLCTLV2_PLL_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK) -#define PLLCTLV2_PLL_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT) - - - -/* DIV register group index macro definition */ -#define PLLCTLV2_PLL_DIV_DIV0 (0UL) -#define PLLCTLV2_PLL_DIV_DIV1 (1UL) -#define PLLCTLV2_PLL_DIV_DIV2 (2UL) - -/* PLL register group index macro definition */ -#define PLLCTLV2_PLL_PLL0 (0UL) -#define PLLCTLV2_PLL_PLL1 (1UL) -#define PLLCTLV2_PLL_PLL2 (2UL) - - -#endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pmon_regs.h deleted file mode 100644 index 7e3a0798d2a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pmon_regs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMON_H -#define HPM_PMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[4]; - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - __RW uint32_t IRQ_FLAG; /* 0x40: */ - __RW uint32_t IRQ_ENABLE; /* 0x44: */ -} PMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define PMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define PMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define PMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ACTIVE_SHIFT) & PMON_MONITOR_CONTROL_ACTIVE_MASK) -#define PMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ACTIVE_MASK) >> PMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define PMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define PMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define PMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ENABLE_SHIFT) & PMON_MONITOR_CONTROL_ENABLE_MASK) -#define PMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ENABLE_MASK) >> PMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define PMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define PMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define PMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << PMON_MONITOR_STATUS_FLAG_SHIFT) & PMON_MONITOR_STATUS_FLAG_MASK) -#define PMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & PMON_MONITOR_STATUS_FLAG_MASK) >> PMON_MONITOR_STATUS_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_FLAG */ -/* - * FLAG (RW) - * - * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt - * 1: monitor interrupt happened - */ -#define PMON_IRQ_FLAG_FLAG_MASK (0xFU) -#define PMON_IRQ_FLAG_FLAG_SHIFT (0U) -#define PMON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << PMON_IRQ_FLAG_FLAG_SHIFT) & PMON_IRQ_FLAG_FLAG_MASK) -#define PMON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & PMON_IRQ_FLAG_FLAG_MASK) >> PMON_IRQ_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * ENABLE (RW) - * - * interrupt enable, each bit represents for one monitor - * 0: monitor interrupt disabled - * 1: monitor interrupt enabled - */ -#define PMON_IRQ_ENABLE_ENABLE_MASK (0xFU) -#define PMON_IRQ_ENABLE_ENABLE_SHIFT (0U) -#define PMON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PMON_IRQ_ENABLE_ENABLE_SHIFT) & PMON_IRQ_ENABLE_ENABLE_MASK) -#define PMON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PMON_IRQ_ENABLE_ENABLE_MASK) >> PMON_IRQ_ENABLE_ENABLE_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define PMON_MONITOR_GLITCH0 (0UL) -#define PMON_MONITOR_GLITCH1 (1UL) -#define PMON_MONITOR_CLOCK0 (2UL) -#define PMON_MONITOR_CLOCK1 (3UL) - - -#endif /* HPM_PMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ppor_regs.h deleted file mode 100644 index 7ce378b07da..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ppor_regs.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPOR_H -#define HPM_PPOR_H - -typedef struct { - __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ - __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ - __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ - __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ - __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ - __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ - __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ - __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ -} PPOR_Type; - - -/* Bitfield definition for register: RESET_FLAG */ -/* - * FLAG (W1C) - * - * reset reason of last hard reset, write 1 to clear each bit - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) -#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) -#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: RESET_STATUS */ -/* - * STATUS (RW) - * - * current status of reset sources - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) -#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) -#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_HOLD */ -/* - * STATUS (RW) - * - * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) -#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) -#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_ENABLE */ -/* - * ENABLE (RW) - * - * enable of reset sources - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) -#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) -#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) - -/* Bitfield definition for register: RESET_HOT */ -/* - * TYPE (RW) - * - * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOT_TYPE_SHIFT (0U) -#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) -#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) - -/* Bitfield definition for register: RESET_COLD */ -/* - * FLAG (RW) - * - * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_COLD_FLAG_SHIFT (0U) -#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) -#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) - -/* Bitfield definition for register: SOFTWARE_RESET */ -/* - * COUNTER (RW) - * - * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - */ -#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) -#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) -#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) -#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) - - - - -#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_psec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_psec_regs.h deleted file mode 100644 index a848fbf5d13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_psec_regs.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PSEC_H -#define HPM_PSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ - __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ -} PSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define PSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define PSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define PSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_NSC_MASK) >> PSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define PSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define PSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define PSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_SEC_MASK) >> PSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * PMIC_FAIL (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define PSEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) -#define PSEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) >> PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) - -/* - * PMIC_NSC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define PSEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) -#define PSEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) -#define PSEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_NSC_SHIFT) & PSEC_SECURE_STATE_PMIC_NSC_MASK) -#define PSEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_NSC_MASK) >> PSEC_SECURE_STATE_PMIC_NSC_SHIFT) - -/* - * PMIC_SEC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define PSEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) -#define PSEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) -#define PSEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_SEC_SHIFT) & PSEC_SECURE_STATE_PMIC_SEC_MASK) -#define PSEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_SEC_MASK) >> PSEC_SECURE_STATE_PMIC_SEC_SHIFT) - -/* - * PMIC_INS (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define PSEC_SECURE_STATE_PMIC_INS_MASK (0x10U) -#define PSEC_SECURE_STATE_PMIC_INS_SHIFT (4U) -#define PSEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_INS_SHIFT) & PSEC_SECURE_STATE_PMIC_INS_MASK) -#define PSEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_INS_MASK) >> PSEC_SECURE_STATE_PMIC_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define PSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define PSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define PSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define PSEC_EVENT_EVENT_SHIFT (16U) -#define PSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & PSEC_EVENT_EVENT_MASK) >> PSEC_EVENT_EVENT_SHIFT) - -/* - * PMIC_ESC_NSC (RO) - * - * PMIC is escalating non-secure event - */ -#define PSEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) -#define PSEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) -#define PSEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_NSC_MASK) >> PSEC_EVENT_PMIC_ESC_NSC_SHIFT) - -/* - * PMIC_ESC_SEC (RO) - * - * PMIC is escalting secure event - */ -#define PSEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) -#define PSEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) -#define PSEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_SEC_MASK) >> PSEC_EVENT_PMIC_ESC_SEC_SHIFT) - -/* Bitfield definition for register: LIFECYCLE */ -/* - * LIFECYCLE (RO) - * - * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, - * bit0: lifecycle_unknow - */ -#define PSEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) -#define PSEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) -#define PSEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & PSEC_LIFECYCLE_LIFECYCLE_MASK) >> PSEC_LIFECYCLE_LIFECYCLE_SHIFT) - - - - -#endif /* HPM_PSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ptpc_regs.h deleted file mode 100644 index 5d9609c0c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_ptpc_regs.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PTPC_H -#define HPM_PTPC_H - -typedef struct { - struct { - __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ - __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ - __R uint32_t TIMEH; /* 0x8: timestamp high */ - __R uint32_t TIMEL; /* 0xC: timestamp low */ - __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ - __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ - __RW uint32_t ADDEND; /* 0x18: */ - __RW uint32_t TARH; /* 0x1C: */ - __RW uint32_t TARL; /* 0x20: */ - __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ - __RW uint32_t PPS_CTRL; /* 0x2C: */ - __R uint32_t CAPT_SNAPH; /* 0x30: */ - __RW uint32_t CAPT_SNAPL; /* 0x34: */ - __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ - } PTPC[2]; - __RW uint32_t TIME_SEL; /* 0x2000: */ - __W uint32_t INT_STS; /* 0x2004: */ - __RW uint32_t INT_EN; /* 0x2008: */ - __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ - __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ -} PTPC_Type; - - -/* Bitfield definition for register of struct array PTPC: CTRL0 */ -/* - * SUBSEC_DIGITAL_ROLLOVER (RW) - * - * Format for ns counter rollover, - * 1-digital, overflow time 1000000000/0x3B9ACA00 - * 0-binary, overflow time 0x7FFFFFFF - */ -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) - -/* - * CAPT_SNAP_KEEP (RW) - * - * set will keep capture snap till software read capt_snapl. - * If this bit is set, software should read capt_snaph first to avoid wrong result. - * If this bit is cleared, capture result will be updated at each capture event - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) - -/* - * CAPT_SNAP_POS_EN (RW) - * - * set will use posege of input capture signal to latch timestamp value - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) - -/* - * CAPT_SNAP_NEG_EN (RW) - * - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - -/* - * COMP_EN (RW) - * - * set to enable compare, will be cleared by HW when compare event triggered - */ -#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) -#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) -#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) -#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) - -/* - * UPDATE_TIMER (WO) - * - * update timer with +/- ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) - -/* - * INIT_TIMER (WO) - * - * initial timer with ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) -#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) - -/* - * FINE_COARSE_SEL (RW) - * - * 0: coarse update, ns counter add ss_incr[7:0] each clk - * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - */ -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - */ -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CTRL1 */ -/* - * SS_INCR (RW) - * - * constant value used to add ns counter; - * such as for 50MHz timer clock, set it to 8'd20 - */ -#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) -#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) -#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) -#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEH */ -/* - * TIMESTAMP_HIGH (RO) - * - */ -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEL */ -/* - * TIMESTAMP_LOW (RO) - * - */ -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ -/* - * SEC_UPDATE (RW) - * - * together with ts_updtl, used to initial or update timestamp - */ -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ -/* - * ADD_SUB (RW) - * - * 1 for sub; 0 for add, used only at update - */ -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) - -/* - * NS_UPDATE (RW) - * - */ -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: ADDEND */ -/* - * ADDEND (RW) - * - * used in fine update mode only - */ -#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) -#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) -#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARH */ -/* - * TARGET_TIME_HIGH (RW) - * - * used for generate compare signal if enabled - */ -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARL */ -/* - * TARGET_TIME_LOW (RW) - * - */ -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ -/* - * PPS_CTRL (RW) - * - */ -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ -/* - * CAPT_SNAP_HIGH (RO) - * - * take snapshot for input capture signal, at pos or neg or both; - * the result can be kept or updated at each event according to cfg0.bit8 - */ -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ -/* - * CAPT_SNAP_LOW (RW) - * - */ -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) - -/* Bitfield definition for register: TIME_SEL */ -/* - * CAN3_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) - -/* - * CAN2_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) - -/* - * CAN1_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) - -/* - * CAN0_TIME_SEL (RW) - * - * set to use ptpc1 for canx - * clr to use ptpc0 for canx - */ -#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * COMP_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) -#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) -#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) -#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) -#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * COMP_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) -#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) -#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) -#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) -#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: PTPC_CAN_TS_SEL */ -/* - * TSU_TBIN3_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) - -/* - * TSU_TBIN2_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) - -/* - * TSU_TBIN1_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) - -/* - * TSU_TBIN0_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) - - - -/* PTPC register group index macro definition */ -#define PTPC_PTPC_0 (0UL) -#define PTPC_PTPC_1 (1UL) - - -#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pwm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pwm_regs.h deleted file mode 100644 index 1e73954216f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_pwm_regs.h +++ /dev/null @@ -1,948 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PWM_H -#define HPM_PWM_H - -typedef struct { - __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ - union { - __RW uint32_t STA; /* 0x4: Counter start register */ - }; - union { - __RW uint32_t RLD; /* 0x8: Counter reload register */ - }; - union { - __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ - }; - __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ - __RW uint32_t FRCMD; /* 0x78: Force output mode register */ - __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ - __RW uint32_t CHCFG[24]; /* 0x80 - 0xDC: Output channel configure register */ - __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */ - __RW uint32_t GCR; /* 0xF0: Global control register */ - __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ - __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ - __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */ - __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */ - __R uint32_t CNT; /* 0x170: Counter */ - __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ - __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */ - __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */ - __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ - __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ - __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ - __W uint32_t SR; /* 0x220: Status register */ - __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ - __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ - __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ - __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ -} PWM_Type; - - -/* Bitfield definition for register: UNLK */ -/* - * SHUNLK (RW) - * - * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, - * otherwise the shadow registers can not be written. - */ -#define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) -#define PWM_UNLK_SHUNLK_SHIFT (0U) -#define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) -#define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * XSTA (RW) - * - * pwm timer counter extended start point, should back to this value after reach xrld - */ -#define PWM_STA_XSTA_MASK (0xF0000000UL) -#define PWM_STA_XSTA_SHIFT (28U) -#define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) -#define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) - -/* - * STA (RW) - * - * pwm timer counter start value - * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - */ -#define PWM_STA_STA_MASK (0xFFFFFF0UL) -#define PWM_STA_STA_SHIFT (4U) -#define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) -#define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * XRLD (RW) - * - * timeout counter extended reload point, counter will reload to xsta after reach this point - */ -#define PWM_RLD_XRLD_MASK (0xF0000000UL) -#define PWM_RLD_XRLD_SHIFT (28U) -#define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) -#define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) - -/* - * RLD (RW) - * - * pwm timer counter reload value - */ -#define PWM_RLD_RLD_MASK (0xFFFFFF0UL) -#define PWM_RLD_RLD_SHIFT (4U) -#define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) -#define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) - -/* Bitfield definition for register: 0 */ -/* - * XCMP (RW) - * - * extended counter compare value - */ -#define PWM_CMP_XCMP_MASK (0xF0000000UL) -#define PWM_CMP_XCMP_SHIFT (28U) -#define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) -#define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) - -/* - * CMP (RW) - * - * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, - * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - */ -#define PWM_CMP_CMP_MASK (0xFFFFFF0UL) -#define PWM_CMP_CMP_SHIFT (4U) -#define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) -#define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) - -/* - * CMPHLF (RW) - * - * half clock counter compare value - */ -#define PWM_CMP_CMPHLF_MASK (0x8U) -#define PWM_CMP_CMPHLF_SHIFT (3U) -#define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) -#define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) - -/* - * CMPJIT (RW) - * - * jitter counter compare value - */ -#define PWM_CMP_CMPJIT_MASK (0x7U) -#define PWM_CMP_CMPJIT_SHIFT (0U) -#define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) -#define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) - -/* Bitfield definition for register: FRCMD */ -/* - * FRCMD (RW) - * - * 2bit for each PWM output channel (0-7); - * 00: force output 0 - * 01: force output 1 - * 10: output highz - * 11: no force - */ -#define PWM_FRCMD_FRCMD_MASK (0xFFFFU) -#define PWM_FRCMD_FRCMD_SHIFT (0U) -#define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) -#define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) - -/* Bitfield definition for register: SHLK */ -/* - * SHLK (RW) - * - * write 1 to lock all shawdow register, write access is not permitted - */ -#define PWM_SHLK_SHLK_MASK (0x80000000UL) -#define PWM_SHLK_SHLK_SHIFT (31U) -#define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) -#define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) - -/* Bitfield definition for register array: CHCFG */ -/* - * CMPSELEND (RW) - * - * assign the last comparator for this output channel - */ -#define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) -#define PWM_CHCFG_CMPSELEND_SHIFT (24U) -#define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) -#define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) - -/* - * CMPSELBEG (RW) - * - * assign the first comparator for this output channel - */ -#define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) -#define PWM_CHCFG_CMPSELBEG_SHIFT (16U) -#define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) -#define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) - -/* - * OUTPOL (RW) - * - * output polarity, set to 1 will invert the output - */ -#define PWM_CHCFG_OUTPOL_MASK (0x2U) -#define PWM_CHCFG_OUTPOL_SHIFT (1U) -#define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) -#define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * FAULTI3EN (RW) - * - * 1- enable the internal fault input 3 - */ -#define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) -#define PWM_GCR_FAULTI3EN_SHIFT (31U) -#define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) -#define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) - -/* - * FAULTI2EN (RW) - * - * 1- enable the internal fault input 2 - */ -#define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) -#define PWM_GCR_FAULTI2EN_SHIFT (30U) -#define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) -#define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) - -/* - * FAULTI1EN (RW) - * - * 1- enable the internal fault input 1 - */ -#define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) -#define PWM_GCR_FAULTI1EN_SHIFT (29U) -#define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) -#define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) - -/* - * FAULTI0EN (RW) - * - * 1- enable the internal fault input 0 - */ -#define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) -#define PWM_GCR_FAULTI0EN_SHIFT (28U) -#define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) -#define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) - -/* - * DEBUGFAULT (RW) - * - * 1- enable debug mode output protection - */ -#define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) -#define PWM_GCR_DEBUGFAULT_SHIFT (27U) -#define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) -#define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) - -/* - * FRCPOL (RW) - * - * polarity of input pwm_force, - * 1- active low - * 0- active high - */ -#define PWM_GCR_FRCPOL_MASK (0x4000000UL) -#define PWM_GCR_FRCPOL_SHIFT (26U) -#define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) -#define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) - -/* - * HWSHDWEDG (RW) - * - * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. - * This bit assign its which edge is used as compare shadow register hardware load event. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) -#define PWM_GCR_HWSHDWEDG_SHIFT (24U) -#define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) -#define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) - -/* - * CMPSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load comparator shadow registers - */ -#define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) -#define PWM_GCR_CMPSHDWSEL_SHIFT (19U) -#define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) -#define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) - -/* - * FAULTRECEDG (RW) - * - * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. - * This bit assign its effective edge of fault recover trigger. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) -#define PWM_GCR_FAULTRECEDG_SHIFT (18U) -#define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) -#define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) - -/* - * FAULTRECHWSEL (RW) - * - * Selec one of the 24 comparators as fault output recover trigger. - */ -#define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) -#define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) -#define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) -#define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) - -/* - * FAULTE1EN (RW) - * - * 1- enable the external fault input 1 - */ -#define PWM_GCR_FAULTE1EN_MASK (0x1000U) -#define PWM_GCR_FAULTE1EN_SHIFT (12U) -#define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) -#define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) - -/* - * FAULTE0EN (RW) - * - * 1- enable the external fault input 0 - */ -#define PWM_GCR_FAULTE0EN_MASK (0x800U) -#define PWM_GCR_FAULTE0EN_SHIFT (11U) -#define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) -#define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) - -/* - * FAULTEXPOL (RW) - * - * external fault polarity - * 1-active low - * 0-active high - */ -#define PWM_GCR_FAULTEXPOL_MASK (0x600U) -#define PWM_GCR_FAULTEXPOL_SHIFT (9U) -#define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) -#define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) - -/* - * RLDSYNCEN (RW) - * - * 1- pwm timer counter reset to reload value (rld) by synci is enabled - */ -#define PWM_GCR_RLDSYNCEN_MASK (0x100U) -#define PWM_GCR_RLDSYNCEN_SHIFT (8U) -#define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) -#define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) - -/* - * CEN (RW) - * - * 1- enable the pwm timer counter - * 0- stop the pwm timer counter - */ -#define PWM_GCR_CEN_MASK (0x80U) -#define PWM_GCR_CEN_SHIFT (7U) -#define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) -#define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) - -/* - * FAULTCLR (RW) - * - * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. - * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - */ -#define PWM_GCR_FAULTCLR_MASK (0x40U) -#define PWM_GCR_FAULTCLR_SHIFT (6U) -#define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) -#define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) - -/* - * XRLDSYNCEN (RW) - * - * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - */ -#define PWM_GCR_XRLDSYNCEN_MASK (0x20U) -#define PWM_GCR_XRLDSYNCEN_SHIFT (5U) -#define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) -#define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) - -/* - * TIMERRESET (RW) - * - * set to clear current timer(total 28bit, main counter and tmout_count ). Auto clear - */ -#define PWM_GCR_TIMERRESET_MASK (0x8U) -#define PWM_GCR_TIMERRESET_SHIFT (3U) -#define PWM_GCR_TIMERRESET_SET(x) (((uint32_t)(x) << PWM_GCR_TIMERRESET_SHIFT) & PWM_GCR_TIMERRESET_MASK) -#define PWM_GCR_TIMERRESET_GET(x) (((uint32_t)(x) & PWM_GCR_TIMERRESET_MASK) >> PWM_GCR_TIMERRESET_SHIFT) - -/* - * FRCTIME (WO) - * - * This bit field select the force effective time - * 00: force immediately - * 01: force at main counter reload time - * 10: force at FRCSYNCI - * 11: no force - */ -#define PWM_GCR_FRCTIME_MASK (0x6U) -#define PWM_GCR_FRCTIME_SHIFT (1U) -#define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) -#define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) - -/* - * SWFRC (RW) - * - * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - */ -#define PWM_GCR_SWFRC_MASK (0x1U) -#define PWM_GCR_SWFRC_SHIFT (0U) -#define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) -#define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) - -/* Bitfield definition for register: SHCR */ -/* - * FRCSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - */ -#define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) -#define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) -#define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) -#define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) - -/* - * CNTSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - */ -#define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) -#define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) -#define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) -#define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) - -/* - * CNTSHDWUPT (RW) - * - * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) -#define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) -#define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) -#define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) - -/* - * SHLKEN (RW) - * - * 1- enable shadow registers lock feature, - * 0- disable shadow registers lock, shlk bit will always be 0 - */ -#define PWM_SHCR_SHLKEN_MASK (0x1U) -#define PWM_SHCR_SHLKEN_SHIFT (0U) -#define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) -#define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) - -/* Bitfield definition for register array: CAPPOS */ -/* - * CAPPOS (RO) - * - * counter value captured at input posedge - */ -#define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) -#define PWM_CAPPOS_CAPPOS_SHIFT (4U) -#define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNT_XCNT_MASK (0xF0000000UL) -#define PWM_CNT_XCNT_SHIFT (28U) -#define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNT_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNT_CNT_SHIFT (4U) -#define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CAPNEG */ -/* - * CAPNEG (RO) - * - * counter value captured at input signal falling edge - */ -#define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define PWM_CAPNEG_CAPNEG_SHIFT (0U) -#define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register: CNTCOPY */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) -#define PWM_CNTCOPY_XCNT_SHIFT (28U) -#define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNTCOPY_CNT_SHIFT (4U) -#define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) - -/* Bitfield definition for register array: PWMCFG */ -/* - * OEN (RW) - * - * PWM output enable - * 1- output is enabled - * 0- output is disabled - */ -#define PWM_PWMCFG_OEN_MASK (0x10000000UL) -#define PWM_PWMCFG_OEN_SHIFT (28U) -#define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) -#define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) - -/* - * FRCSHDWUPT (RW) - * - * This bitfield select when the FRCMD shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) -#define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) -#define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) -#define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) - -/* - * FAULTMODE (RW) - * - * This bitfield defines the PWM output status when fault condition happen - * 00: force output 0 - * 01: force output 1 - * 1x: output highz - */ -#define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) -#define PWM_PWMCFG_FAULTMODE_SHIFT (24U) -#define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) -#define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) - -/* - * FAULTRECTIME (RW) - * - * This bitfield select when to recover PWM output after fault condition removed. - * 00: immediately - * 01: after pwm timer counter reload time - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after software write faultclr bit in GCR register - */ -#define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) -#define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) -#define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) -#define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) - -/* - * FRCSRCSEL (RW) - * - * Select sources for force output - * 0- force output is enabled when FRCI assert - * 1- force output is enabled by software write swfrc to 1 - */ -#define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) -#define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) -#define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) -#define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) - -/* - * PAIR (RW) - * - * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. - * 0- PWM output is in indepandent mode. - */ -#define PWM_PWMCFG_PAIR_MASK (0x100000UL) -#define PWM_PWMCFG_PAIR_SHIFT (20U) -#define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) -#define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) - -/* - * DEADAREA (RW) - * - * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. - * Note: user should configure pair bit and this bitfield before PWM output is enabled. - */ -#define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) -#define PWM_PWMCFG_DEADAREA_SHIFT (0U) -#define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) -#define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * FAULTF (W1C) - * - * fault condition flag - */ -#define PWM_SR_FAULTF_MASK (0x8000000UL) -#define PWM_SR_FAULTF_SHIFT (27U) -#define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) -#define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) - -/* - * XRLDF (W1C) - * - * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - */ -#define PWM_SR_XRLDF_MASK (0x4000000UL) -#define PWM_SR_XRLDF_SHIFT (26U) -#define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) -#define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) - -/* - * HALFRLDF (W1C) - * - * half reload flag, this flag set when cnt count to rld/2 - */ -#define PWM_SR_HALFRLDF_MASK (0x2000000UL) -#define PWM_SR_HALFRLDF_SHIFT (25U) -#define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) -#define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) - -/* - * RLDF (W1C) - * - * reload flag, this flag set when cnt count to rld value or when SYNCI assert - */ -#define PWM_SR_RLDF_MASK (0x1000000UL) -#define PWM_SR_RLDF_SHIFT (24U) -#define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) -#define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) - -/* - * CMPFX (W1C) - * - * comparator output compare or input capture flag - */ -#define PWM_SR_CMPFX_MASK (0xFFFFFFUL) -#define PWM_SR_CMPFX_SHIFT (0U) -#define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) -#define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * FAULTIRQE (RW) - * - * fault condition interrupt enable - */ -#define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) -#define PWM_IRQEN_FAULTIRQE_SHIFT (27U) -#define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) -#define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) - -/* - * XRLDIRQE (RW) - * - * extended reload flag interrupt enable - */ -#define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) -#define PWM_IRQEN_XRLDIRQE_SHIFT (26U) -#define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) -#define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) - -/* - * HALFRLDIRQE (RW) - * - * half reload flag interrupt enable - */ -#define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) -#define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) -#define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) -#define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) - -/* - * RLDIRQE (RW) - * - * reload flag interrupt enable - */ -#define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) -#define PWM_IRQEN_RLDIRQE_SHIFT (24U) -#define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) -#define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) - -/* - * CMPIRQEX (RW) - * - * comparator output compare or input capture flag interrupt enable - */ -#define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) -#define PWM_IRQEN_CMPIRQEX_SHIFT (0U) -#define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) -#define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * FAULTEN (RW) - * - * fault condition DMA request enable - */ -#define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) -#define PWM_DMAEN_FAULTEN_SHIFT (27U) -#define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) -#define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) - -/* - * XRLDEN (RW) - * - * extended reload flag DMA request enable - */ -#define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) -#define PWM_DMAEN_XRLDEN_SHIFT (26U) -#define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) -#define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) - -/* - * HALFRLDEN (RW) - * - * half reload flag DMA request enable - */ -#define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) -#define PWM_DMAEN_HALFRLDEN_SHIFT (25U) -#define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) -#define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) - -/* - * RLDEN (RW) - * - * reload flag DMA request enable - */ -#define PWM_DMAEN_RLDEN_MASK (0x1000000UL) -#define PWM_DMAEN_RLDEN_SHIFT (24U) -#define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) -#define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) - -/* - * CMPENX (RW) - * - * comparator output compare or input capture flag DMA request enable - */ -#define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) -#define PWM_DMAEN_CMPENX_SHIFT (0U) -#define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) -#define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) - -/* Bitfield definition for register array: CMPCFG */ -/* - * XCNTCMPEN (RW) - * - * This bitfield enable the comparator to compare xcmp with xcnt. - */ -#define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) -#define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) -#define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) -#define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) - -/* - * CMPSHDWUPT (RW) - * - * This bitfield select when the comparator shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) -#define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) -#define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) -#define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) - -/* - * CMPMODE (RW) - * - * comparator mode - * 0- output compare mode - * 1- input capture mode - */ -#define PWM_CMPCFG_CMPMODE_MASK (0x2U) -#define PWM_CMPCFG_CMPMODE_SHIFT (1U) -#define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) -#define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) - - - -/* CMP register group index macro definition */ -#define PWM_CMP_0 (0UL) -#define PWM_CMP_1 (1UL) -#define PWM_CMP_2 (2UL) -#define PWM_CMP_3 (3UL) -#define PWM_CMP_4 (4UL) -#define PWM_CMP_5 (5UL) -#define PWM_CMP_6 (6UL) -#define PWM_CMP_7 (7UL) -#define PWM_CMP_8 (8UL) -#define PWM_CMP_9 (9UL) -#define PWM_CMP_10 (10UL) -#define PWM_CMP_11 (11UL) -#define PWM_CMP_12 (12UL) -#define PWM_CMP_13 (13UL) -#define PWM_CMP_14 (14UL) -#define PWM_CMP_15 (15UL) -#define PWM_CMP_16 (16UL) -#define PWM_CMP_17 (17UL) -#define PWM_CMP_18 (18UL) -#define PWM_CMP_19 (19UL) -#define PWM_CMP_20 (20UL) -#define PWM_CMP_21 (21UL) -#define PWM_CMP_22 (22UL) -#define PWM_CMP_23 (23UL) - -/* CHCFG register group index macro definition */ -#define PWM_CHCFG_0 (0UL) -#define PWM_CHCFG_1 (1UL) -#define PWM_CHCFG_2 (2UL) -#define PWM_CHCFG_3 (3UL) -#define PWM_CHCFG_4 (4UL) -#define PWM_CHCFG_5 (5UL) -#define PWM_CHCFG_6 (6UL) -#define PWM_CHCFG_7 (7UL) -#define PWM_CHCFG_8 (8UL) -#define PWM_CHCFG_9 (9UL) -#define PWM_CHCFG_10 (10UL) -#define PWM_CHCFG_11 (11UL) -#define PWM_CHCFG_12 (12UL) -#define PWM_CHCFG_13 (13UL) -#define PWM_CHCFG_14 (14UL) -#define PWM_CHCFG_15 (15UL) -#define PWM_CHCFG_16 (16UL) -#define PWM_CHCFG_17 (17UL) -#define PWM_CHCFG_18 (18UL) -#define PWM_CHCFG_19 (19UL) -#define PWM_CHCFG_20 (20UL) -#define PWM_CHCFG_21 (21UL) -#define PWM_CHCFG_22 (22UL) -#define PWM_CHCFG_23 (23UL) - -/* CAPPOS register group index macro definition */ -#define PWM_CAPPOS_0 (0UL) -#define PWM_CAPPOS_1 (1UL) -#define PWM_CAPPOS_2 (2UL) -#define PWM_CAPPOS_3 (3UL) -#define PWM_CAPPOS_4 (4UL) -#define PWM_CAPPOS_5 (5UL) -#define PWM_CAPPOS_6 (6UL) -#define PWM_CAPPOS_7 (7UL) -#define PWM_CAPPOS_8 (8UL) -#define PWM_CAPPOS_9 (9UL) -#define PWM_CAPPOS_10 (10UL) -#define PWM_CAPPOS_11 (11UL) -#define PWM_CAPPOS_12 (12UL) -#define PWM_CAPPOS_13 (13UL) -#define PWM_CAPPOS_14 (14UL) -#define PWM_CAPPOS_15 (15UL) -#define PWM_CAPPOS_16 (16UL) -#define PWM_CAPPOS_17 (17UL) -#define PWM_CAPPOS_18 (18UL) -#define PWM_CAPPOS_19 (19UL) -#define PWM_CAPPOS_20 (20UL) -#define PWM_CAPPOS_21 (21UL) -#define PWM_CAPPOS_22 (22UL) -#define PWM_CAPPOS_23 (23UL) - -/* CAPNEG register group index macro definition */ -#define PWM_CAPNEG_0 (0UL) -#define PWM_CAPNEG_1 (1UL) -#define PWM_CAPNEG_2 (2UL) -#define PWM_CAPNEG_3 (3UL) -#define PWM_CAPNEG_4 (4UL) -#define PWM_CAPNEG_5 (5UL) -#define PWM_CAPNEG_6 (6UL) -#define PWM_CAPNEG_7 (7UL) -#define PWM_CAPNEG_8 (8UL) -#define PWM_CAPNEG_9 (9UL) -#define PWM_CAPNEG_10 (10UL) -#define PWM_CAPNEG_11 (11UL) -#define PWM_CAPNEG_12 (12UL) -#define PWM_CAPNEG_13 (13UL) -#define PWM_CAPNEG_14 (14UL) -#define PWM_CAPNEG_15 (15UL) -#define PWM_CAPNEG_16 (16UL) -#define PWM_CAPNEG_17 (17UL) -#define PWM_CAPNEG_18 (18UL) -#define PWM_CAPNEG_19 (19UL) -#define PWM_CAPNEG_20 (20UL) -#define PWM_CAPNEG_21 (21UL) -#define PWM_CAPNEG_22 (22UL) -#define PWM_CAPNEG_23 (23UL) - -/* PWMCFG register group index macro definition */ -#define PWM_PWMCFG_0 (0UL) -#define PWM_PWMCFG_1 (1UL) -#define PWM_PWMCFG_2 (2UL) -#define PWM_PWMCFG_3 (3UL) -#define PWM_PWMCFG_4 (4UL) -#define PWM_PWMCFG_5 (5UL) -#define PWM_PWMCFG_6 (6UL) -#define PWM_PWMCFG_7 (7UL) - -/* CMPCFG register group index macro definition */ -#define PWM_CMPCFG_CMPCFG0 (0UL) -#define PWM_CMPCFG_1 (1UL) -#define PWM_CMPCFG_2 (2UL) -#define PWM_CMPCFG_3 (3UL) -#define PWM_CMPCFG_4 (4UL) -#define PWM_CMPCFG_5 (5UL) -#define PWM_CMPCFG_6 (6UL) -#define PWM_CMPCFG_7 (7UL) -#define PWM_CMPCFG_8 (8UL) -#define PWM_CMPCFG_9 (9UL) -#define PWM_CMPCFG_10 (10UL) -#define PWM_CMPCFG_11 (11UL) -#define PWM_CMPCFG_12 (12UL) -#define PWM_CMPCFG_13 (13UL) -#define PWM_CMPCFG_14 (14UL) -#define PWM_CMPCFG_15 (15UL) -#define PWM_CMPCFG_16 (16UL) -#define PWM_CMPCFG_17 (17UL) -#define PWM_CMPCFG_18 (18UL) -#define PWM_CMPCFG_19 (19UL) -#define PWM_CMPCFG_20 (20UL) -#define PWM_CMPCFG_21 (21UL) -#define PWM_CMPCFG_22 (22UL) -#define PWM_CMPCFG_23 (23UL) - - -#endif /* HPM_PWM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_qei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_qei_regs.h deleted file mode 100644 index cafcdfe2851..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_qei_regs.h +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEI_H -#define HPM_QEI_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t PHIDX; /* 0xC: Phase index register */ - __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __RW uint32_t ZCMP; /* 0x18: Z comparator */ - __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ - __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ - __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ - struct { - __RW uint32_t Z; /* 0x30: Z counter */ - __R uint32_t PH; /* 0x34: Phase counter */ - __RW uint32_t SPD; /* 0x38: Speed counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - __R uint32_t SPDHIS[4]; /* 0x70 - 0x7C: Speed history */ -} QEI_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define QEI_CR_READ_MASK (0x80000000UL) -#define QEI_CR_READ_SHIFT (31U) -#define QEI_CR_READ_SET(x) (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK) -#define QEI_CR_READ_GET(x) (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT) - -/* - * HRSTSPD (RW) - * - * 1- reset spdcnt when H assert - */ -#define QEI_CR_HRSTSPD_MASK (0x40000UL) -#define QEI_CR_HRSTSPD_SHIFT (18U) -#define QEI_CR_HRSTSPD_SET(x) (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK) -#define QEI_CR_HRSTSPD_GET(x) (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT) - -/* - * HRSTPH (RW) - * - * 1- reset phcnt when H assert - */ -#define QEI_CR_HRSTPH_MASK (0x20000UL) -#define QEI_CR_HRSTPH_SHIFT (17U) -#define QEI_CR_HRSTPH_SET(x) (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK) -#define QEI_CR_HRSTPH_GET(x) (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT) - -/* - * HRSTZ (RW) - * - * 1- reset zcnt when H assert - */ -#define QEI_CR_HRSTZ_MASK (0x10000UL) -#define QEI_CR_HRSTZ_SHIFT (16U) -#define QEI_CR_HRSTZ_SET(x) (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK) -#define QEI_CR_HRSTZ_GET(x) (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT) - -/* - * PAUSESPD (RW) - * - * 1- pause spdcnt when PAUSE assert - */ -#define QEI_CR_PAUSESPD_MASK (0x4000U) -#define QEI_CR_PAUSESPD_SHIFT (14U) -#define QEI_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK) -#define QEI_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT) - -/* - * PAUSEPH (RW) - * - * 1- pause phcnt when PAUSE assert - */ -#define QEI_CR_PAUSEPH_MASK (0x2000U) -#define QEI_CR_PAUSEPH_SHIFT (13U) -#define QEI_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK) -#define QEI_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT) - -/* - * PAUSEZ (RW) - * - * 1- pause zcnt when PAUSE assert - */ -#define QEI_CR_PAUSEZ_MASK (0x1000U) -#define QEI_CR_PAUSEZ_SHIFT (12U) -#define QEI_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK) -#define QEI_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT) - -/* - * HRDIR1 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - */ -#define QEI_CR_HRDIR1_MASK (0x800U) -#define QEI_CR_HRDIR1_SHIFT (11U) -#define QEI_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK) -#define QEI_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT) - -/* - * HRDIR0 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - */ -#define QEI_CR_HRDIR0_MASK (0x400U) -#define QEI_CR_HRDIR0_SHIFT (10U) -#define QEI_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK) -#define QEI_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT) - -/* - * HFDIR1 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - */ -#define QEI_CR_HFDIR1_MASK (0x200U) -#define QEI_CR_HFDIR1_SHIFT (9U) -#define QEI_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK) -#define QEI_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT) - -/* - * HFDIR0 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - */ -#define QEI_CR_HFDIR0_MASK (0x100U) -#define QEI_CR_HFDIR0_SHIFT (8U) -#define QEI_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK) -#define QEI_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - */ -#define QEI_CR_SNAPEN_MASK (0x20U) -#define QEI_CR_SNAPEN_SHIFT (5U) -#define QEI_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK) -#define QEI_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - */ -#define QEI_CR_RSTCNT_MASK (0x10U) -#define QEI_CR_RSTCNT_SHIFT (4U) -#define QEI_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK) -#define QEI_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT) - -/* - * ENCTYP (RW) - * - * 00-abz; 01-pd; 10-ud; 11-reserved - */ -#define QEI_CR_ENCTYP_MASK (0x3U) -#define QEI_CR_ENCTYP_SHIFT (0U) -#define QEI_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK) -#define QEI_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * ZCNTCFG (RW) - * - * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * 0- zcnt will increment or decrement when Z input assert - */ -#define QEI_PHCFG_ZCNTCFG_MASK (0x400000UL) -#define QEI_PHCFG_ZCNTCFG_SHIFT (22U) -#define QEI_PHCFG_ZCNTCFG_SET(x) (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK) -#define QEI_PHCFG_ZCNTCFG_GET(x) (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT) - -/* - * PHCALIZ (RW) - * - * 1- phcnt will set to phidx when Z input assert - */ -#define QEI_PHCFG_PHCALIZ_MASK (0x200000UL) -#define QEI_PHCFG_PHCALIZ_SHIFT (21U) -#define QEI_PHCFG_PHCALIZ_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK) -#define QEI_PHCFG_PHCALIZ_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT) - -/* - * PHMAX (RW) - * - * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - */ -#define QEI_PHCFG_PHMAX_MASK (0x1FFFFFUL) -#define QEI_PHCFG_PHMAX_SHIFT (0U) -#define QEI_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK) -#define QEI_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define QEI_WDGCFG_WDGEN_MASK (0x80000000UL) -#define QEI_WDGCFG_WDGEN_SHIFT (31U) -#define QEI_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK) -#define QEI_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define QEI_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) -#define QEI_WDGCFG_WDGTO_SHIFT (0U) -#define QEI_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK) -#define QEI_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: PHIDX */ -/* - * PHIDX (RW) - * - * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - */ -#define QEI_PHIDX_PHIDX_MASK (0x1FFFFFUL) -#define QEI_PHIDX_PHIDX_SHIFT (0U) -#define QEI_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK) -#define QEI_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGFEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define QEI_TRGOEN_WDGFEN_MASK (0x80000000UL) -#define QEI_TRGOEN_WDGFEN_SHIFT (31U) -#define QEI_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK) -#define QEI_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- enable trigger output when homef flag set - */ -#define QEI_TRGOEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_TRGOEN_HOMEFEN_SHIFT (30U) -#define QEI_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK) -#define QEI_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- enable trigger output when poscmpf flag set - */ -#define QEI_TRGOEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_TRGOEN_POSCMPFEN_SHIFT (29U) -#define QEI_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK) -#define QEI_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- enable trigger output when zphf flag set - */ -#define QEI_TRGOEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_TRGOEN_ZPHFEN_SHIFT (28U) -#define QEI_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK) -#define QEI_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGFEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define QEI_READEN_WDGFEN_MASK (0x80000000UL) -#define QEI_READEN_WDGFEN_SHIFT (31U) -#define QEI_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK) -#define QEI_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- load counters to their read registers when homef flag set - */ -#define QEI_READEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_READEN_HOMEFEN_SHIFT (30U) -#define QEI_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK) -#define QEI_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- load counters to their read registers when poscmpf flag set - */ -#define QEI_READEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_READEN_POSCMPFEN_SHIFT (29U) -#define QEI_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK) -#define QEI_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- load counters to their read registers when zphf flag set - */ -#define QEI_READEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_READEN_ZPHFEN_SHIFT (28U) -#define QEI_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK) -#define QEI_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: ZCMP */ -/* - * ZCMP (RW) - * - * zcnt postion compare value - */ -#define QEI_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) -#define QEI_ZCMP_ZCMP_SHIFT (0U) -#define QEI_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK) -#define QEI_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT) - -/* Bitfield definition for register: PHCMP */ -/* - * ZCMPDIS (RW) - * - * 1- postion compare not include zcnt - */ -#define QEI_PHCMP_ZCMPDIS_MASK (0x80000000UL) -#define QEI_PHCMP_ZCMPDIS_SHIFT (31U) -#define QEI_PHCMP_ZCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK) -#define QEI_PHCMP_ZCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT) - -/* - * DIRCMPDIS (RW) - * - * 1- postion compare not include rotation direction - */ -#define QEI_PHCMP_DIRCMPDIS_MASK (0x40000000UL) -#define QEI_PHCMP_DIRCMPDIS_SHIFT (30U) -#define QEI_PHCMP_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK) -#define QEI_PHCMP_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT) - -/* - * DIRCMP (RW) - * - * 0- position compare need positive rotation - * 1- position compare need negative rotation - */ -#define QEI_PHCMP_DIRCMP_MASK (0x20000000UL) -#define QEI_PHCMP_DIRCMP_SHIFT (29U) -#define QEI_PHCMP_DIRCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK) -#define QEI_PHCMP_DIRCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT) - -/* - * PHCMP (RW) - * - * phcnt position compare value - */ -#define QEI_PHCMP_PHCMP_MASK (0x1FFFFFUL) -#define QEI_PHCMP_PHCMP_SHIFT (0U) -#define QEI_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK) -#define QEI_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT) - -/* Bitfield definition for register: SPDCMP */ -/* - * SPDCMP (RW) - * - * spdcnt position compare value - */ -#define QEI_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) -#define QEI_SPDCMP_SPDCMP_SHIFT (0U) -#define QEI_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK) -#define QEI_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGFEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define QEI_DMAEN_WDGFEN_MASK (0x80000000UL) -#define QEI_DMAEN_WDGFEN_SHIFT (31U) -#define QEI_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK) -#define QEI_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- generate dma request when homef flag set - */ -#define QEI_DMAEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_DMAEN_HOMEFEN_SHIFT (30U) -#define QEI_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK) -#define QEI_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- generate dma request when poscmpf flag set - */ -#define QEI_DMAEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_DMAEN_POSCMPFEN_SHIFT (29U) -#define QEI_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK) -#define QEI_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- generate dma request when zphf flag set - */ -#define QEI_DMAEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_DMAEN_ZPHFEN_SHIFT (28U) -#define QEI_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK) -#define QEI_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog flag - */ -#define QEI_SR_WDGF_MASK (0x80000000UL) -#define QEI_SR_WDGF_SHIFT (31U) -#define QEI_SR_WDGF_SET(x) (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK) -#define QEI_SR_WDGF_GET(x) (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT) - -/* - * HOMEF (RW) - * - * home flag - */ -#define QEI_SR_HOMEF_MASK (0x40000000UL) -#define QEI_SR_HOMEF_SHIFT (30U) -#define QEI_SR_HOMEF_SET(x) (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK) -#define QEI_SR_HOMEF_GET(x) (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT) - -/* - * POSCMPF (RW) - * - * postion compare match flag - */ -#define QEI_SR_POSCMPF_MASK (0x20000000UL) -#define QEI_SR_POSCMPF_SHIFT (29U) -#define QEI_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK) -#define QEI_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT) - -/* - * ZPHF (RW) - * - * z input flag - */ -#define QEI_SR_ZPHF_MASK (0x10000000UL) -#define QEI_SR_ZPHF_SHIFT (28U) -#define QEI_SR_ZPHF_SET(x) (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK) -#define QEI_SR_ZPHF_GET(x) (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt when wdg flag set - */ -#define QEI_IRQEN_WDGIE_MASK (0x80000000UL) -#define QEI_IRQEN_WDGIE_SHIFT (31U) -#define QEI_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK) -#define QEI_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT) - -/* - * HOMEIE (RW) - * - * 1- generate interrupt when homef flag set - */ -#define QEI_IRQEN_HOMEIE_MASK (0x40000000UL) -#define QEI_IRQEN_HOMEIE_SHIFT (30U) -#define QEI_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK) -#define QEI_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT) - -/* - * POSCMPIE (RW) - * - * 1- generate interrupt when poscmpf flag set - */ -#define QEI_IRQEN_POSCMPIE_MASK (0x20000000UL) -#define QEI_IRQEN_POSCMPIE_SHIFT (29U) -#define QEI_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK) -#define QEI_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT) - -/* - * ZPHIE (RW) - * - * 1- generate interrupt when zphf flag set - */ -#define QEI_IRQEN_ZPHIE_MASK (0x10000000UL) -#define QEI_IRQEN_ZPHIE_SHIFT (28U) -#define QEI_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK) -#define QEI_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: Z */ -/* - * ZCNT (RW) - * - * zcnt value - */ -#define QEI_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) -#define QEI_COUNT_Z_ZCNT_SHIFT (0U) -#define QEI_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK) -#define QEI_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: PH */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEI_COUNT_PH_DIR_MASK (0x40000000UL) -#define QEI_COUNT_PH_DIR_SHIFT (30U) -#define QEI_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEI_COUNT_PH_ASTAT_MASK (0x4000000UL) -#define QEI_COUNT_PH_ASTAT_SHIFT (26U) -#define QEI_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT) - -/* - * BSTAT (RO) - * - * 1- b input is high - * 0- b input is low - */ -#define QEI_COUNT_PH_BSTAT_MASK (0x2000000UL) -#define QEI_COUNT_PH_BSTAT_SHIFT (25U) -#define QEI_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT) - -/* - * PHCNT (RO) - * - * phcnt value - */ -#define QEI_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) -#define QEI_COUNT_PH_PHCNT_SHIFT (0U) -#define QEI_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: SPD */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEI_COUNT_SPD_DIR_MASK (0x80000000UL) -#define QEI_COUNT_SPD_DIR_SHIFT (31U) -#define QEI_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEI_COUNT_SPD_ASTAT_MASK (0x40000000UL) -#define QEI_COUNT_SPD_ASTAT_SHIFT (30U) -#define QEI_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT) - -/* - * BSTAT (RW) - * - * 1- b input is high - * 0- b input is low - */ -#define QEI_COUNT_SPD_BSTAT_MASK (0x20000000UL) -#define QEI_COUNT_SPD_BSTAT_SHIFT (29U) -#define QEI_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK) -#define QEI_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT) - -/* - * SPDCNT (RO) - * - * spdcnt value - */ -#define QEI_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) -#define QEI_COUNT_SPD_SPDCNT_SHIFT (0U) -#define QEI_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TMRCNT (RO) - * - * 32 bit free run timer - */ -#define QEI_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) -#define QEI_COUNT_TMR_TMRCNT_SHIFT (0U) -#define QEI_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT) - -/* Bitfield definition for register array: SPDHIS */ -/* - * SPDHIS0 (RO) - * - * copy of spdcnt, load from spdcnt after any transition from a = low, b = low - */ -#define QEI_SPDHIS_SPDHIS0_MASK (0xFFFFFFFFUL) -#define QEI_SPDHIS_SPDHIS0_SHIFT (0U) -#define QEI_SPDHIS_SPDHIS0_GET(x) (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT) - - - -/* COUNT register group index macro definition */ -#define QEI_COUNT_CURRENT (0UL) -#define QEI_COUNT_READ (1UL) -#define QEI_COUNT_SNAP0 (2UL) -#define QEI_COUNT_SNAP1 (3UL) - -/* SPDHIS register group index macro definition */ -#define QEI_SPDHIS_SPDHIS0 (0UL) -#define QEI_SPDHIS_SPDHIS1 (1UL) -#define QEI_SPDHIS_SPDHIS2 (2UL) -#define QEI_SPDHIS_SPDHIS3 (3UL) - - -#endif /* HPM_QEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_rng_regs.h deleted file mode 100644 index 1a847f5d090..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_rng_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RNG_H -#define HPM_RNG_H - -typedef struct { - __RW uint32_t CMD; /* 0x0: Command Register */ - __RW uint32_t CTRL; /* 0x4: Control Register */ - __R uint32_t STA; /* 0x8: Status Register */ - __R uint32_t ERR; /* 0xC: Error Registers */ - __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ -} RNG_Type; - - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. - * 0 Do not perform a software reset. - * 1 Software reset - */ -#define RNG_CMD_SFTRST_MASK (0x40U) -#define RNG_CMD_SFTRST_SHIFT (6U) -#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) -#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) - -/* - * CLRERR (RW) - * - * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. - * 0 Do not clear the errors and the interrupt. - * 1 Clear the errors and the interrupt. - */ -#define RNG_CMD_CLRERR_MASK (0x20U) -#define RNG_CMD_CLRERR_SHIFT (5U) -#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) -#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) - -/* - * CLRINT (RW) - * - * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. - * 0 Do not clear the interrupt. - * 1 Clear the interrupt - */ -#define RNG_CMD_CLRINT_MASK (0x10U) -#define RNG_CMD_CLRINT_SHIFT (4U) -#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) -#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) - -/* - * GENSD (RW) - * - * Generate Seed, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_GENSD_MASK (0x2U) -#define RNG_CMD_GENSD_SHIFT (1U) -#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) -#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) - -/* - * SLFCHK (RW) - * - * Self Test, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_SLFCHK_MASK (0x1U) -#define RNG_CMD_SLFCHK_SHIFT (0U) -#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) -#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * MIRQERR (RW) - * - * Mask Interrupt Request for Error - */ -#define RNG_CTRL_MIRQERR_MASK (0x40U) -#define RNG_CTRL_MIRQERR_SHIFT (6U) -#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) -#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) - -/* - * MIRQDN (RW) - * - * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: - * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). - * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - */ -#define RNG_CTRL_MIRQDN_MASK (0x20U) -#define RNG_CTRL_MIRQDN_SHIFT (5U) -#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) -#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) - -/* - * AUTRSD (RW) - * - * Auto Reseed - */ -#define RNG_CTRL_AUTRSD_MASK (0x10U) -#define RNG_CTRL_AUTRSD_SHIFT (4U) -#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) -#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) - -/* - * FUFMOD (RW) - * - * FIFO underflow response mode - * 00 Return all zeros and set the ESR[FUFE]. - * 01 Return all zeros and set the ESR[FUFE]. - * 10 Generate the bus transfer error - * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - */ -#define RNG_CTRL_FUFMOD_MASK (0x3U) -#define RNG_CTRL_FUFMOD_SHIFT (0U) -#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) -#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * SCPF (RO) - * - * Self Check Pass Fail - */ -#define RNG_STA_SCPF_MASK (0xE00000UL) -#define RNG_STA_SCPF_SHIFT (21U) -#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) - -/* - * FUNCERR (RO) - * - * Error was detected, check ESR register for details - */ -#define RNG_STA_FUNCERR_MASK (0x10000UL) -#define RNG_STA_FUNCERR_SHIFT (16U) -#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) - -/* - * FSIZE (RO) - * - * Fifo Size, it is 5 in this design. - */ -#define RNG_STA_FSIZE_MASK (0xF000U) -#define RNG_STA_FSIZE_SHIFT (12U) -#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) - -/* - * FRNNU (RO) - * - * Fifo Level, Indicates the number of random words currently in the output FIFO - */ -#define RNG_STA_FRNNU_MASK (0xF00U) -#define RNG_STA_FRNNU_SHIFT (8U) -#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) - -/* - * NSDDN (RO) - * - * New seed done. - */ -#define RNG_STA_NSDDN_MASK (0x40U) -#define RNG_STA_NSDDN_SHIFT (6U) -#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) - -/* - * FSDDN (RO) - * - * 1st Seed done - * When "1", Indicates that the RNG generated the first seed. - */ -#define RNG_STA_FSDDN_MASK (0x20U) -#define RNG_STA_FSDDN_SHIFT (5U) -#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) - -/* - * SCDN (RO) - * - * Self Check Done - * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is - * initiated by setting the CMD[ST]. - * 0 Self test not completed - * 1 Completed a self test since the last reset. - */ -#define RNG_STA_SCDN_MASK (0x10U) -#define RNG_STA_SCDN_SHIFT (4U) -#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) - -/* - * RSDREQ (RO) - * - * Reseed needed - * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or - * automatically if the CTRL[ARS] is set. - */ -#define RNG_STA_RSDREQ_MASK (0x8U) -#define RNG_STA_RSDREQ_SHIFT (3U) -#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) - -/* - * IDLE (RO) - * - * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - */ -#define RNG_STA_IDLE_MASK (0x4U) -#define RNG_STA_IDLE_SHIFT (2U) -#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) - -/* - * BUSY (RO) - * - * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - */ -#define RNG_STA_BUSY_MASK (0x2U) -#define RNG_STA_BUSY_SHIFT (1U) -#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) - -/* Bitfield definition for register: ERR */ -/* - * FUFE (RO) - * - * FIFO access error(underflow) - */ -#define RNG_ERR_FUFE_MASK (0x20U) -#define RNG_ERR_FUFE_SHIFT (5U) -#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) - -/* - * SCKERR (RO) - * - * Self-test error - * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a - * hardware reset or by writing 1 to the CMD[CE] - */ -#define RNG_ERR_SCKERR_MASK (0x8U) -#define RNG_ERR_SCKERR_SHIFT (3U) -#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) - -/* Bitfield definition for register: FO2B */ -/* - * FO2B (RO) - * - * SW read the FIFO output. - */ -#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) -#define RNG_FO2B_FO2B_SHIFT (0U) -#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) - -/* Bitfield definition for register array: R2SK */ -/* - * FO2S0 (RO) - * - * FIFO out to KMAN, will be SDP engine key. - */ -#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) -#define RNG_R2SK_FO2S0_SHIFT (0U) -#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) - - - -/* R2SK register group index macro definition */ -#define RNG_R2SK_FO2S0 (0UL) -#define RNG_R2SK_FO2S1 (1UL) -#define RNG_R2SK_FO2S2 (2UL) -#define RNG_R2SK_FO2S3 (3UL) -#define RNG_R2SK_FO2S4 (4UL) -#define RNG_R2SK_FO2S5 (5UL) -#define RNG_R2SK_FO2S6 (6UL) -#define RNG_R2SK_FO2S7 (7UL) - - -#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_rtc_regs.h deleted file mode 100644 index d2325b94590..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_rtc_regs.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTC_H -#define HPM_RTC_H - -typedef struct { - __RW uint32_t SECOND; /* 0x0: Second counter */ - __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ - __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ - __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ - __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ - __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ - __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ - __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ - __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ - __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ -} RTC_Type; - - -/* Bitfield definition for register: SECOND */ -/* - * SECOND (RW) - * - * second counter - */ -#define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) -#define RTC_SECOND_SECOND_SHIFT (0U) -#define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) -#define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) - -/* Bitfield definition for register: SUBSEC */ -/* - * SUBSEC (RO) - * - * sub second counter - */ -#define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) - -/* Bitfield definition for register: SEC_SNAP */ -/* - * SEC_SNAP (RW) - * - * second snap shot, write to take snap shot - */ -#define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) -#define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) -#define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) - -/* Bitfield definition for register: SUB_SNAP */ -/* - * SUB_SNAP (RW) - * - * sub second snap shot, write to take snap shot - */ -#define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) -#define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) -#define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) - -/* Bitfield definition for register: ALARM0 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_ALARM_SHIFT (0U) -#define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) -#define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM0_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) -#define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM1 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_ALARM_SHIFT (0U) -#define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) -#define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM1_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) -#define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM_FLAG */ -/* - * ALARM1 (RW) - * - * alarm1 happen - */ -#define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) -#define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) -#define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) -#define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) - -/* - * ALARM0 (RW) - * - * alarm0 happen - */ -#define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) -#define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) -#define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) -#define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) - -/* Bitfield definition for register: ALARM_EN */ -/* - * ENABLE1 (RW) - * - * alarm1 mask - * 0: alarm1 disabled - * 1: alarm1 enabled - */ -#define RTC_ALARM_EN_ENABLE1_MASK (0x2U) -#define RTC_ALARM_EN_ENABLE1_SHIFT (1U) -#define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) -#define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) - -/* - * ENABLE0 (RW) - * - * alarm0 mask - * 0: alarm0 disabled - * 1: alarm0 enabled - */ -#define RTC_ALARM_EN_ENABLE0_MASK (0x1U) -#define RTC_ALARM_EN_ENABLE0_SHIFT (0U) -#define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) -#define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) - - - - -#endif /* HPM_RTC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sdp_regs.h deleted file mode 100644 index 7562ad654a5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sdp_regs.h +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDP_H -#define HPM_SDP_H - -typedef struct { - __RW uint32_t SDPCR; /* 0x0: SDP control register */ - __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ - __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ - __RW uint32_t STA; /* 0xC: Status Registers */ - __RW uint32_t KEYADDR; /* 0x10: Key Address */ - __RW uint32_t KEYDAT; /* 0x14: Key Data */ - __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ - __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ - __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ - __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ - __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ - __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ - __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ - __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ -} SDP_Type; - - -/* Bitfield definition for register: SDPCR */ -/* - * SFTRST (RW) - * - * soft reset. - * Write 1 then 0, to reset the SDP block. - */ -#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) -#define SDP_SDPCR_SFTRST_SHIFT (31U) -#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) -#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) - -/* - * CLKGAT (RW) - * - * Clock Gate for the SDP main logic. - * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - */ -#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) -#define SDP_SDPCR_CLKGAT_SHIFT (30U) -#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) -#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) - -/* - * CIPDIS (RO) - * - * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. - * 1, Cipher is disabled in this chip. - * 0, Cipher is enabled in this chip. - */ -#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) -#define SDP_SDPCR_CIPDIS_SHIFT (29U) -#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) - -/* - * HASDIS (RO) - * - * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. - * 1, HASH is disabled in this chip. - * 0, HASH is enabled in this chip. - */ -#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) -#define SDP_SDPCR_HASDIS_SHIFT (28U) -#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) - -/* - * CIPHEN (RW) - * - * Cipher Enablement, controlled by SW. - * 1, Cipher is Enabled. - * 0, Cipher is Disabled. - */ -#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) -#define SDP_SDPCR_CIPHEN_SHIFT (23U) -#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) -#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) - -/* - * HASHEN (RW) - * - * HASH Enablement, controlled by SW. - * 1, HASH is Enabled. - * 0, HASH is Disabled. - */ -#define SDP_SDPCR_HASHEN_MASK (0x400000UL) -#define SDP_SDPCR_HASHEN_SHIFT (22U) -#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) -#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) - -/* - * MCPEN (RW) - * - * Memory Copy Enablement, controlled by SW. - * 1, Memory copy is Enabled. - * 0, Memory copy is Disabled. - */ -#define SDP_SDPCR_MCPEN_MASK (0x200000UL) -#define SDP_SDPCR_MCPEN_SHIFT (21U) -#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) -#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) - -/* - * CONFEN (RW) - * - * Constant Fill to memory, controlled by SW. - * 1, Constant fill is Enabled. - * 0, Constant fill is Disabled. - */ -#define SDP_SDPCR_CONFEN_MASK (0x100000UL) -#define SDP_SDPCR_CONFEN_SHIFT (20U) -#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) -#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) - -/* - * DCRPDI (RW) - * - * Decryption Disable bit, Write to 1 to disable the decryption. - */ -#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) -#define SDP_SDPCR_DCRPDI_SHIFT (19U) -#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) -#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) - -/* - * TSTPKT0IRQ (RW) - * - * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - */ -#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) -#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) -#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) -#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) - -/* - * RDSCEN (RW) - * - * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) - * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - */ -#define SDP_SDPCR_RDSCEN_MASK (0x100U) -#define SDP_SDPCR_RDSCEN_SHIFT (8U) -#define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK) -#define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT) - -/* - * INTEN (RW) - * - * Interrupt Enablement, controlled by SW. - * 1, SDP interrupt is enabled. - * 0, SDP interrupt is disabled. - */ -#define SDP_SDPCR_INTEN_MASK (0x1U) -#define SDP_SDPCR_INTEN_SHIFT (0U) -#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) -#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) - -/* Bitfield definition for register: MODCTRL */ -/* - * AESALG (RW) - * - * AES algorithem selection. - * 0x0 = AES 128; - * 0x1 = AES 256; - * 0x8 = SM4； - * Others, reserved. - */ -#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) -#define SDP_MODCTRL_AESALG_SHIFT (28U) -#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) -#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) - -/* - * AESMOD (RW) - * - * AES mode selection. - * 0x0 = ECB; - * 0x1 = CBC; - * Others, reserved. - */ -#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) -#define SDP_MODCTRL_AESMOD_SHIFT (24U) -#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) -#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) - -/* - * AESKS (RW) - * - * AES Key Selection. - * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: - * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. - * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * .... - * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. - * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. - * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. - * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. - * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. - * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. - * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. - * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. - * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. - * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. - * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. - * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. - * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. - * Other values, reserved. - */ -#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) -#define SDP_MODCTRL_AESKS_SHIFT (18U) -#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) -#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) - -/* - * AESDIR (RW) - * - * AES direction - * 1x1, AES Decryption - * 1x0, AES Encryption. - */ -#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) -#define SDP_MODCTRL_AESDIR_SHIFT (16U) -#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) -#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) - -/* - * HASALG (RW) - * - * HASH Algorithem selection. - * 0x0 SHA1 — - * 0x1 CRC32 — - * 0x2 SHA256 — - */ -#define SDP_MODCTRL_HASALG_MASK (0xF000U) -#define SDP_MODCTRL_HASALG_SHIFT (12U) -#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) -#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) - -/* - * HASCHK (RW) - * - * HASH Check Enable Bit. - * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; - * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. - * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - */ -#define SDP_MODCTRL_HASCHK_MASK (0x400U) -#define SDP_MODCTRL_HASCHK_SHIFT (10U) -#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) -#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) - -/* - * HASOUT (RW) - * - * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. - * 0 INPUT HASH - * 1 OUTPUT HASH - */ -#define SDP_MODCTRL_HASOUT_MASK (0x200U) -#define SDP_MODCTRL_HASOUT_SHIFT (9U) -#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) -#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) - -/* - * DINSWP (RW) - * - * Decide whether the SDP byteswaps the input data (big-endian data); - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DINSWP_MASK (0x30U) -#define SDP_MODCTRL_DINSWP_SHIFT (4U) -#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) -#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) - -/* - * DOUTSWP (RW) - * - * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) -#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) -#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) -#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) - -/* - * KEYSWP (RW) - * - * Decide whether the SDP byteswaps the Key (big-endian data). - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_KEYSWP_MASK (0x3U) -#define SDP_MODCTRL_KEYSWP_SHIFT (0U) -#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) -#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) - -/* Bitfield definition for register: PKTCNT */ -/* - * CNTVAL (RO) - * - * This read-only field shows the current (instantaneous) value of the packet counter - */ -#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) -#define SDP_PKTCNT_CNTVAL_SHIFT (16U) -#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) - -/* - * CNTINCR (RW) - * - * The value written to this field is added to the spacket count. - */ -#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) -#define SDP_PKTCNT_CNTINCR_SHIFT (0U) -#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) -#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TAG (RO) - * - * packet tag. - */ -#define SDP_STA_TAG_MASK (0xFF000000UL) -#define SDP_STA_TAG_SHIFT (24U) -#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) - -/* - * IRQ (W1C) - * - * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - */ -#define SDP_STA_IRQ_MASK (0x800000UL) -#define SDP_STA_IRQ_SHIFT (23U) -#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) -#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) - -/* - * CHN1PKT0 (W1C) - * - * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - */ -#define SDP_STA_CHN1PKT0_MASK (0x100000UL) -#define SDP_STA_CHN1PKT0_SHIFT (20U) -#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) -#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) - -/* - * AESBSY (RO) - * - * AES Busy - */ -#define SDP_STA_AESBSY_MASK (0x80000UL) -#define SDP_STA_AESBSY_SHIFT (19U) -#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) - -/* - * HASBSY (RO) - * - * Hashing Busy - */ -#define SDP_STA_HASBSY_MASK (0x40000UL) -#define SDP_STA_HASBSY_SHIFT (18U) -#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) - -/* - * PKTCNT0 (W1C) - * - * Packet Counter registers reachs to ZERO now. - */ -#define SDP_STA_PKTCNT0_MASK (0x20000UL) -#define SDP_STA_PKTCNT0_SHIFT (17U) -#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) -#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) - -/* - * PKTDON (W1C) - * - * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - */ -#define SDP_STA_PKTDON_MASK (0x10000UL) -#define SDP_STA_PKTDON_SHIFT (16U) -#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) -#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) - -/* - * ERRSET (W1C) - * - * Working mode setup error. - */ -#define SDP_STA_ERRSET_MASK (0x20U) -#define SDP_STA_ERRSET_SHIFT (5U) -#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) -#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) - -/* - * ERRPKT (W1C) - * - * Packet head access error, or status update error. - */ -#define SDP_STA_ERRPKT_MASK (0x10U) -#define SDP_STA_ERRPKT_SHIFT (4U) -#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) -#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) - -/* - * ERRSRC (W1C) - * - * Source Buffer Access Error - */ -#define SDP_STA_ERRSRC_MASK (0x8U) -#define SDP_STA_ERRSRC_SHIFT (3U) -#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) -#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) - -/* - * ERRDST (W1C) - * - * Destination Buffer Error - */ -#define SDP_STA_ERRDST_MASK (0x4U) -#define SDP_STA_ERRDST_SHIFT (2U) -#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) -#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) - -/* - * ERRHAS (W1C) - * - * Hashing Check Error - */ -#define SDP_STA_ERRHAS_MASK (0x2U) -#define SDP_STA_ERRHAS_SHIFT (1U) -#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) -#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) - -/* - * ERRCHAIN (W1C) - * - * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - */ -#define SDP_STA_ERRCHAIN_MASK (0x1U) -#define SDP_STA_ERRCHAIN_SHIFT (0U) -#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) -#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) - -/* Bitfield definition for register: KEYADDR */ -/* - * INDEX (RW) - * - * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. - * Key index pointer. The valid indices are 0-[number_keys]. - * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - */ -#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) -#define SDP_KEYADDR_INDEX_SHIFT (16U) -#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) -#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) - -/* - * SUBWRD (RW) - * - * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field - * increments; To write a key, the software must first write the desired key index/subword to this register. - */ -#define SDP_KEYADDR_SUBWRD_MASK (0x3U) -#define SDP_KEYADDR_SUBWRD_SHIFT (0U) -#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) -#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) - -/* Bitfield definition for register: KEYDAT */ -/* - * KEYDAT (RW) - * - * This register provides the write access to the key/key subword specified by the key index register. - * Writing this location updates the selected subword for the key located at the index - * specified by the key index register. The write also triggers the SUBWORD field of the - * KEY register to increment to the next higher word in the key - */ -#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) -#define SDP_KEYDAT_KEYDAT_SHIFT (0U) -#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) -#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) - -/* Bitfield definition for register array: CIPHIV */ -/* - * CIPHIV (RW) - * - * cipher initialization vector. - */ -#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) -#define SDP_CIPHIV_CIPHIV_SHIFT (0U) -#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) -#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) - -/* Bitfield definition for register array: HASWRD */ -/* - * HASWRD (RW) - * - * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. - * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - */ -#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) -#define SDP_HASWRD_HASWRD_SHIFT (0U) -#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) -#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) - -/* Bitfield definition for register: CMDPTR */ -/* - * CMDPTR (RW) - * - * current command addresses the register points to the multiword - * descriptor that is to be executed (or is currently being executed) - */ -#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) -#define SDP_CMDPTR_CMDPTR_SHIFT (0U) -#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) -#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) - -/* Bitfield definition for register: NPKTPTR */ -/* - * NPKTPTR (RW) - * - * Next Packet Address Pointer - */ -#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) -#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) -#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) -#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) - -/* Bitfield definition for register: PKTCTL */ -/* - * PKTTAG (RW) - * - * packet tag - */ -#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) -#define SDP_PKTCTL_PKTTAG_SHIFT (24U) -#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) -#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) - -/* - * CIPHIV (RW) - * - * Load Initial Vector for the AES in this packet. - */ -#define SDP_PKTCTL_CIPHIV_MASK (0x40U) -#define SDP_PKTCTL_CIPHIV_SHIFT (6U) -#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) -#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) - -/* - * HASFNL (RW) - * - * Hash Termination packet - */ -#define SDP_PKTCTL_HASFNL_MASK (0x20U) -#define SDP_PKTCTL_HASFNL_SHIFT (5U) -#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) -#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) - -/* - * HASINI (RW) - * - * Hash Initialization packat - */ -#define SDP_PKTCTL_HASINI_MASK (0x10U) -#define SDP_PKTCTL_HASINI_SHIFT (4U) -#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) -#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) - -/* - * CHAIN (RW) - * - * whether the next command pointer register must be loaded into the channel's current descriptor - * pointer. - */ -#define SDP_PKTCTL_CHAIN_MASK (0x8U) -#define SDP_PKTCTL_CHAIN_SHIFT (3U) -#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) -#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) - -/* - * DCRSEMA (RW) - * - * whether the channel's semaphore must be decremented at the end of the current operation. - * When the semaphore reaches a value of zero, no more operations are issued from the channel. - */ -#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) -#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) -#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) -#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) - -/* - * PKTINT (RW) - * - * Reflects whether the channel must issue an interrupt upon the completion of the packet - */ -#define SDP_PKTCTL_PKTINT_MASK (0x2U) -#define SDP_PKTCTL_PKTINT_SHIFT (1U) -#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) -#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) - -/* Bitfield definition for register: PKTSRC */ -/* - * PKTSRC (RW) - * - * Packet Memory Source Address - */ -#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) -#define SDP_PKTSRC_PKTSRC_SHIFT (0U) -#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) -#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) - -/* Bitfield definition for register: PKTDST */ -/* - * PKTDST (RW) - * - * Packet Memory Destination Address - */ -#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) -#define SDP_PKTDST_PKTDST_SHIFT (0U) -#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) -#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) - -/* Bitfield definition for register: PKTBUF */ -/* - * PKTBUF (RW) - * - */ -#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) -#define SDP_PKTBUF_PKTBUF_SHIFT (0U) -#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) -#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) - - - -/* CIPHIV register group index macro definition */ -#define SDP_CIPHIV_CIPHIV0 (0UL) -#define SDP_CIPHIV_CIPHIV1 (1UL) -#define SDP_CIPHIV_CIPHIV2 (2UL) -#define SDP_CIPHIV_CIPHIV3 (3UL) - -/* HASWRD register group index macro definition */ -#define SDP_HASWRD_HASWRD0 (0UL) -#define SDP_HASWRD_HASWRD1 (1UL) -#define SDP_HASWRD_HASWRD2 (2UL) -#define SDP_HASWRD_HASWRD3 (3UL) -#define SDP_HASWRD_HASWRD4 (4UL) -#define SDP_HASWRD_HASWRD5 (5UL) -#define SDP_HASWRD_HASWRD6 (6UL) -#define SDP_HASWRD_HASWRD7 (7UL) - - -#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sdxc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sdxc_regs.h deleted file mode 100644 index 019daaa5f82..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sdxc_regs.h +++ /dev/null @@ -1,4397 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDXC_H -#define HPM_SDXC_H - -typedef struct { - __RW uint32_t SDMASA; /* 0x0: */ - __RW uint32_t BLK_ATTR; /* 0x4: */ - __RW uint32_t CMD_ARG; /* 0x8: */ - __RW uint32_t CMD_XFER; /* 0xC: */ - __R uint32_t RESP[4]; /* 0x10 - 0x1C: */ - __RW uint32_t BUF_DATA; /* 0x20: */ - __R uint32_t PSTATE; /* 0x24: */ - __RW uint32_t PROT_CTRL; /* 0x28: */ - __RW uint32_t SYS_CTRL; /* 0x2C: */ - __RW uint32_t INT_STAT; /* 0x30: */ - __RW uint32_t INT_STAT_EN; /* 0x34: */ - __RW uint32_t INT_SIGNAL_EN; /* 0x38: */ - __RW uint32_t AC_HOST_CTRL; /* 0x3C: */ - __R uint32_t CAPABILITIES1; /* 0x40: */ - __R uint32_t CAPABILITIES2; /* 0x44: */ - __R uint32_t CURR_CAPABILITIES1; /* 0x48: */ - __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */ - __W uint32_t FORCE_EVENT; /* 0x50: */ - __R uint32_t ADMA_ERR_STAT; /* 0x54: */ - __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */ - __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */ - __R uint16_t PRESET[11]; /* 0x60 - 0x74: */ - __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */ - __RW uint32_t ADMA_ID_ADDR; /* 0x78: */ - __R uint8_t RESERVED2[106]; /* 0x7C - 0xE5: Reserved */ - __R uint16_t P_EMBEDDED_CNTRL; /* 0xE6: */ - __R uint16_t P_VENDOR_SPECIFIC_AREA; /* 0xE8: */ - __R uint16_t P_VENDOR2_SPECIFIC_AREA; /* 0xEA: */ - __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */ - __R uint16_t SLOT_INTR_STATUS; /* 0xFC: */ - __R uint8_t RESERVED4[130]; /* 0xFE - 0x17F: Reserved */ - __R uint32_t CQVER; /* 0x180: */ - __R uint32_t CQCAP; /* 0x184: */ - __RW uint32_t CQCFG; /* 0x188: */ - __RW uint32_t CQCTL; /* 0x18C: */ - __RW uint32_t CQIS; /* 0x190: */ - __RW uint32_t CQISE; /* 0x194: */ - __RW uint32_t CQISGE; /* 0x198: */ - __RW uint32_t CQIC; /* 0x19C: */ - __RW uint32_t CQTDLBA; /* 0x1A0: */ - __R uint8_t RESERVED5[4]; /* 0x1A4 - 0x1A7: Reserved */ - __RW uint32_t CQTDBR; /* 0x1A8: */ - __RW uint32_t CQTCN; /* 0x1AC: */ - __RW uint32_t CQDQS; /* 0x1B0: */ - __RW uint32_t CQDPT; /* 0x1B4: */ - __RW uint32_t CQTCLR; /* 0x1B8: */ - __R uint8_t RESERVED6[4]; /* 0x1BC - 0x1BF: Reserved */ - __RW uint32_t CQSSC1; /* 0x1C0: */ - __RW uint32_t CQSSC2; /* 0x1C4: */ - __R uint32_t CQCRDCT; /* 0x1C8: */ - __R uint8_t RESERVED7[4]; /* 0x1CC - 0x1CF: Reserved */ - __RW uint32_t CQRMEM; /* 0x1D0: */ - __R uint32_t CQTERRI; /* 0x1D4: */ - __R uint32_t CQCRI; /* 0x1D8: */ - __R uint32_t CQCRA; /* 0x1DC: */ - __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */ - __R uint32_t MSHC_VER_ID; /* 0x500: */ - __R uint32_t MSHC_VER_TYPE; /* 0x504: */ - __R uint8_t RESERVED9[36]; /* 0x508 - 0x52B: Reserved */ - __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */ - __R uint8_t RESERVED10[16]; /* 0x530 - 0x53F: Reserved */ - __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */ - __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */ - __R uint8_t RESERVED11[10936]; /* 0x548 - 0x2FFF: Reserved */ - __RW uint32_t MISC_CTRL0; /* 0x3000: */ - __RW uint32_t MISC_CTRL1; /* 0x3004: */ -} SDXC_Type; - - -/* Bitfield definition for register: SDMASA */ -/* - * BLOCKCNT_SDMASA (RW) - * - * 32-bit Block Count (SDMA System Address) - * - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. - * When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. - * It can be accessed only if no transaction is executing. Reading this register during data transfers may - * return an invalid value. - * - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. - * The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. - * This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. - * Following are the values for BLOCKCNT_SDMASA: - * - 0xFFFF_FFFF: 4G - 1 Block - * - - * - 0x0000_0002: 2 Blocks - * - 0x0000_0001: 1 Block - * - 0x0000_0000: Stop Count - * Note: - * - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. - * The system address must be programmed in the ADMA System Address register. - * - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. - * Auto CMD23 cannot be used with SDMA. - * - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - */ -#define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) - -/* Bitfield definition for register: BLK_ATTR */ -/* - * BLOCK_CNT (RW) - * - * 16-bit Block Count - * - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. - * - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. - * Following are the values for BLOCK_CNT: - * - 0x0: Stop Count - * - 0x1: 1 Block - * - 0x2: 2 Blocks - * - . - * - 0xFFFF: 65535 Blocks - * Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - */ -#define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL) -#define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U) -#define SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) -#define SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) - -/* - * SDMA_BUF_BDARY (RW) - * - * SDMA Buffer Boundary - * These bits specify the size of contiguous buffer in system memory. - * The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. - * Values: - * - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary - * - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary - * - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary - * - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary - * - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary - * - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary - * - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary - * - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - */ -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) - -/* - * XFER_BLOCK_SIZE (RW) - * - * Transfer Block Size - * These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. - * Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: - * - 0x1: 1 byte - * - 0x2: 2 bytes - * - 0x3: 3 bytes - * - . - * - 0x1FF: 511 byte - * - 0x200: 512 byt es - * - . - * - 0x800: 2048 bytes - * Note: This register must be programmed with a non-zero value for data transfer. - */ -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) - -/* Bitfield definition for register: CMD_ARG */ -/* - * ARGUMNET (RW) - * - * Command Argument - * These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - */ -#define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL) -#define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U) -#define SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK) -#define SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT) - -/* Bitfield definition for register: CMD_XFER */ -/* - * CMD_INDEX (RW) - * - * Command Index - * These bits are set to the command number that is specified in bits 45-40 of the Command Format. - */ -#define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL) -#define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U) -#define SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK) -#define SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT) - -/* - * CMD_TYPE (RW) - * - * Command Type - * These bits indicate the command type. - * Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. - * Values: - * 0x3 (ABORT_CMD): Abort - * 0x2 (RESUME_CMD): Resume - * 0x1 (SUSPEND_CMD): Suspend - * 0x0 (NORMAL_CMD): Normal - */ -#define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL) -#define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U) -#define SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK) -#define SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT) - -/* - * DATA_PRESENT_SEL (RW) - * - * Data Present Select - * This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: - * Command using the CMD line - * Command with no data transfer but using busy signal on the DAT[0] line - * Resume Command - * Values: - * 0x0 (NO_DATA): No Data Present - * 0x1 (DATA): Data Present - */ -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) - -/* - * CMD_IDX_CHK_ENABLE (RW) - * - * Command Index Check Enable - * This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. - * If the value is not the same, it is reported as a Command Index error. - * Note: - * Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. - * For the tuning command, this bit must always be set to enable the index check. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) - -/* - * CMD_CRC_CHK_ENABLE (RW) - * - * Command CRC Check Enable - * This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. - * Note: - * CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. - * For the tuning command, this bit must always be set to 1 to enable the CRC check. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) - -/* - * SUB_CMD_FLAG (RW) - * - * Sub Command Flag - * This bit distinguishes between a main command and a sub command. - * Values: - * 0x0 (MAIN): Main Command - * 0x1 (SUB): Sub Command - */ -#define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) - -/* - * RESP_TYPE_SELECT (RW) - * - * Response Type Select - * This bit indicates the type of response expected from the card. - * Values: - * 0x0 (NO_RESP): No Response - * 0x1 (RESP_LEN_136): Response Length 136 - * 0x2 (RESP_LEN_48): Response Length 48 - * 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - */ -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) - -/* - * RESP_INT_DISABLE (RW) - * - * Response Interrupt Disable - * The Host Controller supports response check function to avoid overhead of response error check by the Host driver. - * Response types of only R1 and R5 can be checked by the Controller. - * If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. - * If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. - * The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. - * Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. - * Values: - * - 0x0 (ENABLED): Response Interrupt is enabled - * - 0x1 (DISABLED): Response Interrupt is disabled - */ -#define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) - -/* - * RESP_ERR_CHK_ENABLE (RW) - * - * Response Error Check Enable - * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. - * If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. - * Note: - * - Response error check must not be enabled for any response type other than R1 and R5. - * - Response check must not be enabled for the tuning command. - * Values: - * - 0x0 (DISABLED): Response Error Check is disabled - * - 0x1 (ENABLED): Response Error Check is enabled - */ -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) - -/* - * RESP_TYPE (RW) - * - * Response Type R1/R5 - * This bit selects either R1 or R5 as a response type when the Response Error Check is selected. - * Error statuses checked in R1: - * OUT_OF_RANGE - * ADDRESS_ERROR - * BLOCK_LEN_ERROR - * WP_VIOLATION - * CARD_IS_LOCKED - * COM_CRC_ERROR - * CARD_ECC_FAILED - * CC_ERROR - * ERROR - * Response Flags checked in R5: - * COM_CRC_ERROR - * ERROR - * FUNCTION_NUMBER - * OUT_OF_RANGE - * Values: - * 0x0 (RESP_R1): R1 (Memory) - * 0x1 (RESP_R5): R5 (SDIO) - */ -#define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U) -#define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U) -#define SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK) -#define SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT) - -/* - * MULTI_BLK_SEL (RW) - * - * Multi/Single Block Select - * This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. - * Values: - * 0x0 (SINGLE): Single Block - * 0x1 (MULTI): Multiple Block - */ -#define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) - -/* - * DATA_XFER_DIR (RW) - * - * Data Transfer Direction Select - * This bit defines the direction of DAT line data transfers. - * This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. - * Values: - * 0x1 (READ): Read (Card to Host) - * 0x0 (WRITE): Write (Host to Card) - */ -#define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U) -#define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U) -#define SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) -#define SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) - -/* - * AUTO_CMD_ENABLE (RW) - * - * Auto Command Enable - * This field determines use of Auto Command functions. - * Note: In SDIO, this field must be set as 00b (Auto Command Disabled). - * Values: - * 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled - * 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable - * 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable - * 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - */ -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) - -/* - * BLOCK_COUNT_ENABLE (RW) - * - * Block Count Enable - * This bit is used to enable the Block Count register, which is relevant for multiple block transfers. - * If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. - * The Host Driver must set this bit to 0 when ADMA is used. - * Values: - * 0x1 (ENABLED): Enable - * 0x0 (DISABLED): Disable - */ -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) - -/* - * DMA_ENABLE (RW) - * - * DMA Enable - * This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. - * You can select one of the DMA modes by using DMA Select in the Host Control 1 register. - * Values: - * 0x1 (ENABLED): DMA Data transfer - * 0x0 (DISABLED): No data transfer or Non-DMA data transfer - */ -#define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U) -#define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U) -#define SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK) -#define SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT) - -/* Bitfield definition for register array: RESP */ -/* - * RESP01 (RO) - * - * Command Response - * These bits reflect 39-8 bits of SD/eMMC Response Field. - * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - */ -#define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL) -#define SDXC_RESP_RESP01_SHIFT (0U) -#define SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT) - -/* Bitfield definition for register: BUF_DATA */ -/* - * BUF_DATA (RW) - * - * Buffer Data - * These bits enable access to the Host Controller packet buffer. - */ -#define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL) -#define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U) -#define SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK) -#define SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT) - -/* Bitfield definition for register: PSTATE */ -/* - * SUB_CMD_STAT (RO) - * - * Sub Command Status - * This bit is used to distinguish between a main command and a sub command status. - * Values: - * 0x0 (FALSE): Main Command Status - * 0x1 (TRUE): Sub Command Status - */ -#define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL) -#define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U) -#define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT) - -/* - * CMD_ISSUE_ERR (RO) - * - * Command Not Issued by Error - * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. - * Values: - * 0x0 (FALSE): No error for issuing a command - * 0x1 (TRUE): Command cannot be issued - */ -#define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL) -#define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U) -#define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT) - -/* - * CMD_LINE_LVL (RO) - * - * Command-Line Signal Level - * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - */ -#define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL) -#define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U) -#define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT) - -/* - * DAT_3_0 (RO) - * - * DAT[3:0] Line Signal Level - * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - */ -#define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL) -#define SDXC_PSTATE_DAT_3_0_SHIFT (20U) -#define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT) - -/* - * WR_PROTECT_SW_LVL (RO) - * - * Write Protect Switch Pin Level - * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. - * Values: - * 0x0 (FALSE): Write protected - * 0x1 (TRUE): Write enabled - */ -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL) -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U) -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT) - -/* - * CARD_DETECT_PIN_LEVEL (RO) - * - * Card Detect Pin Level - * This bit reflects the inverse synchronized value of the card_detect_n signal. - * Values: - * 0x0 (FALSE): No card present - * 0x1 (TRUE): Card Present - */ -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL) -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U) -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT) - -/* - * CARD_STABLE (RO) - * - * Card Stable - * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. - * Values: - * 0x0 (FALSE): Reset or Debouncing - * 0x1 (TRUE): No Card or Inserted - */ -#define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL) -#define SDXC_PSTATE_CARD_STABLE_SHIFT (17U) -#define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT) - -/* - * CARD_INSERTED (RO) - * - * Card Inserted - * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. - * Values: - * 0x0 (FALSE): Reset, Debouncing, or No card - * 0x1 (TRUE): Card Inserted - */ -#define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL) -#define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U) -#define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT) - -/* - * BUF_RD_ENABLE (RO) - * - * Buffer Read Enable - * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. - * Values: - * 0x0 (DISABLED): Read disable - * 0x1 (ENABLED): Read enable - */ -#define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U) -#define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U) -#define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT) - -/* - * BUF_WR_ENABLE (RO) - * - * Buffer Write Enable - * This bit is used for non-DMA transfers. This bit is set if space is available for writing data. - * Values: - * 0x0 (DISABLED): Write disable - * 0x1 (ENABLED): Write enable - */ -#define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U) -#define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U) -#define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT) - -/* - * RD_XFER_ACTIVE (RO) - * - * Read Transfer Active - * This bit indicates whether a read transfer is active for SD/eMMC mode. - * Values: - * 0x0 (INACTIVE): No valid data - * 0x1 (ACTIVE): Transferring data - */ -#define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U) -#define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U) -#define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT) - -/* - * WR_XFER_ACTIVE (RO) - * - * Write Transfer Active - * This status indicates whether a write transfer is active for SD/eMMC mode. - * Values: - * 0x0 (INACTIVE): No valid data - * 0x1 (ACTIVE): Transferring data - */ -#define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U) -#define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U) -#define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT) - -/* - * DAT_7_4 (RO) - * - * DAT[7:4] Line Signal Level - * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - */ -#define SDXC_PSTATE_DAT_7_4_MASK (0xF0U) -#define SDXC_PSTATE_DAT_7_4_SHIFT (4U) -#define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT) - -/* - * RE_TUNE_REQ (RO) - * - * Re-Tuning Request - * SDXC does not generate retuning request. The software must maintain the Retuning timer. - */ -#define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U) -#define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U) -#define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT) - -/* - * DAT_LINE_ACTIVE (RO) - * - * DAT Line Active ( - * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. - * In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. - * In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. - * For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. - * Values: - * 0x0 (INACTIVE): DAT Line Inactive - * 0x1 (ACTIVE): DAT Line Active - */ -#define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U) -#define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U) -#define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT) - -/* - * DAT_INHIBIT (RO) - * - * Command Inhibit (DAT) - * This bit is generated if either DAT line active or Read transfer active is set to 1. - * If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. - * Values: - * 0x0 (READY): Can issue command which used DAT line - * 0x1 (NOT_READY): Cannot issue command which used DAT line - */ -#define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U) -#define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U) -#define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT) - -/* - * CMD_INHIBIT (RO) - * - * Command Inhibit (CMD) - * This bit indicates the following : - * If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. - * This bit is set when the command register is written. This bit is cleared when the command response is received. - * This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. - * Values: - * 0x0 (READY): Host Controller is ready to issue a command - * 0x1 (NOT_READY): Host Controller is not ready to issue a command - */ -#define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U) -#define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U) -#define SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT) - -/* Bitfield definition for register: PROT_CTRL */ -/* - * CARD_REMOVAL (RW) - * - * Wakeup Event Enable on SD Card Removal - * This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. - * For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL) -#define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U) -#define SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) -#define SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) - -/* - * CARD_INSERT (RW) - * - * Wakeup Event Enable on SD Card Insertion - * This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. - * FN_WUS (Wake Up Support) in CIS does not affect this bit. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL) -#define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U) -#define SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK) -#define SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT) - -/* - * CARD_INT (RW) - * - * Wakeup Event Enable on Card Interrupt - * This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. - * This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL) -#define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U) -#define SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK) -#define SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT) - -/* - * INT_AT_BGAP (RW) - * - * Interrupt At Block Gap - * This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. - * Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. - * Values: - * 0x0 (DISABLE): Disabled - * 0x1 (ENABLE): Enabled - */ -#define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL) -#define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U) -#define SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) -#define SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) - -/* - * RD_WAIT_CTRL (RW) - * - * Read Wait Control - * This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. - * Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. - * Values: - * 0x0 (DISABLE): Disable Read Wait Control - * 0x1 (ENABLE): Enable Read Wait Control - */ -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) - -/* - * CONTINUE_REQ (RW) - * - * Continue Request - * This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. - * The Host Controller automatically clears this bit when the transaction restarts. - * If stop at block gap request is set to 1, any write to this bit is ignored. - * Values: - * 0x0 (NO_AFFECT): No Affect - * 0x1 (RESTART): Restart - */ -#define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL) -#define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U) -#define SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) -#define SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) - -/* - * STOP_BG_REQ (RW) - * - * Stop At Block Gap Request - * This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. - * Values: - * 0x0 (XFER): Transfer - * 0x1 (STOP): Stop - */ -#define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL) -#define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U) -#define SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) -#define SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) - -/* - * SD_BUS_VOL_VDD1 (RW) - * - * SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD - * These bits enable the Host Driver to select the voltage level for an SD/eMMC card. - * Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. - * If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. - * The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. - * SD Bus Voltage Select options: - * 0x7 : 3.3V(Typical) - * 0x6 : 3.0V(Typical) - * 0x5 : 1.8V(Typical) for Embedded - * 0x4 : 0x0 - Reserved - * eMMC Bus Voltage Select options: - * 0x7 : 3.3V(Typical) - * 0x6 : 1.8V(Typical) - * 0x5 : 1.2V(Typical) - * 0x4 : 0x0 - Reserved - * Values: - * 0x7 (V_3_3): 3.3V (Typ.) - * 0x6 (V_3_0): 3.0V (Typ.) - * 0x5 (V_1_8): 1.8V (Typ.) for Embedded - * 0x4 (RSVD4): Reserved - * 0x3 (RSVD3): Reserved - * 0x2 (RSVD2): Reserved - * 0x1 (RSVD1): Reserved - * 0x0 (RSVD0): Reserved - */ -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) - -/* - * SD_BUS_PWR_VDD1 (RW) - * - * SD Bus Power for VDD1 - * This bit enables VDD1 power of the card. - * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. - * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. - * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. - * Values: - * 0x0 (OFF): Power off - * 0x1 (ON): Power on - */ -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) - -/* - * EXT_DAT_XFER (RW) - * - * Extended Data Transfer Width - * This bit controls 8-bit bus width mode of embedded device. - * Values: - * 0x1 (EIGHT_BIT): 8-bit Bus Width - * 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - */ -#define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) - -/* - * DMA_SEL (RW) - * - * DMA Select - * This field is used to select the DMA type. - * When Host Version 4 Enable is 1 in Host Control 2 register: - * 0x0 : SDMA is selected - * 0x1 : Reserved - * 0x2 : ADMA2 is selected - * 0x3 : ADMA2 or ADMA3 is selected - * When Host Version 4 Enable is 0 in Host Control 2 register: - * 0x0 : SDMA is selected - * 0x1 : Reserved - * 0x2 : 32-bit Address ADMA2 is selected - * 0x3 : 64-bit Address ADMA2 is selected - * Values: - * 0x0 (SDMA): SDMA is selected - * 0x1 (RSVD_BIT): Reserved - * 0x2 (ADMA2): ADMA2 is selected - * 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - */ -#define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U) -#define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U) -#define SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK) -#define SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT) - -/* - * HIGH_SPEED_EN (RW) - * - * High Speed Enable - * this bit is used to determine the selection of preset value for High Speed mode. - * Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. - * Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. - * Values: - * 0x1 (HIGH_SPEED): High Speed mode - * 0x0 (NORMAL_SPEED): Normal Speed mode - */ -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) - -/* - * DAT_XFER_WIDTH (RW) - * - * Data Transfer Width - * For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. - * The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. - * Values: - * 0x1 (FOUR_BIT): 4-bit mode - * 0x0 (ONE_BIT): 1-bit mode - */ -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) - -/* Bitfield definition for register: SYS_CTRL */ -/* - * SW_RST_DAT (RW) - * - * Software Reset For DAT line - * This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. - * The following registers and bits are cleared by this bit: - * Buffer Data Port register - * -Buffer is cleared and initialized. - * Present state register - * -Buffer Read Enable - * -Buffer Write Enable - * -Read Transfer Active - * -Write Transfer Active - * -DAT Line Active - * -Command Inhibit (DAT) - * Block Gap Control register - * -Continue Request - * -Stop At Block Gap Request - * Normal Interrupt status register - * -Buffer Read Ready - * -Buffer Write Ready - * -DMA Interrupt - * -Block Gap Event - * -Transfer Complete - * In UHS-II mode, this bit shall be set to 0 - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL) -#define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U) -#define SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) -#define SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) - -/* - * SW_RST_CMD (RW) - * - * Software Reset For CMD line - * This bit resets only a part of the command circuit to be able to issue a command. - * It bit is also used to initialize a UHS-II command circuit. - * This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. - * Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. - * The following registers and bits are cleared by this bit: - * Present State register : Command Inhibit (CMD) bit - * Normal Interrupt Status register : Command Complete bit - * Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL) -#define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U) -#define SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) -#define SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) - -/* - * SW_RST_ALL (RW) - * - * Software Reset For All - * This reset affects the entire Host Controller except for the card detection circuit. - * During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. - * All registers are reset except the capabilities register. - * If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL) -#define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U) -#define SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) -#define SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) - -/* - * TOUT_CNT (RW) - * - * Data Timeout Counter Value. - * This value determines the interval by which DAT line timeouts are detected. - * The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. - * When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). - * The values for these bits are: - * 0xF : Reserved - * 0xE : TMCLK x 2^27 - * ......... - * 0x1 : TMCLK x 2^14 - * 0x0 : TMCLK x 2^13 - * Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - */ -#define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL) -#define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U) -#define SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK) -#define SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT) - -/* - * FREQ_SEL (RW) - * - * SDCLK/RCLK Frequency Select - * These bits are used to select the frequency of the SDCLK signal. - * These bits depend on setting of Preset Value Enable in the Host Control 2 register. - * If Preset Value Enable = 0, these bits are set by the Host Driver. - * If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. - * The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. - * 10-bit Divided Clock Mode: - * 0x3FF : 1/2046 Divided clock - * .......... - * N : 1/2N Divided Clock - * .......... - * 0x002 : 1/4 Divided Clock - * 0x001 : 1/2 Divided Clock - * 0x000 : Base clock (10MHz - 255 MHz) - * Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: - * 0x3FF : Base clock * M /1024 - * .......... - * N-1 : Base clock * M /N - * .......... - * 0x002 : Base clock * M /3 - * 0x001 : Base clock * M /2 - * 0x000 : Base clock * M - */ -#define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U) -#define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U) -#define SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK) -#define SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT) - -/* - * UPPER_FREQ_SEL (RW) - * - * These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. - * The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - */ -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) - -/* - * CLK_GEN_SELECT (RW) - * - * Clock Generator Select - * This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. - * If Preset Value Enable = 0, this bit is set by the Host Driver. - * If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. - * The value is reflected on the card_clk_gen_sel signal. - * Values: - * 0x0 (FALSE): Divided Clock Mode - * 0x1 (TRUE): Programmable Clock Mode - */ -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) - -/* - * PLL_ENABLE (RW) - * - * PLL Enable - * This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). - * When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. - * Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . - * Values: - * 0x0 (FALSE): PLL is in low power mode - * 0x1 (TRUE): PLL is enabled - */ -#define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U) -#define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U) -#define SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) -#define SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) - -/* - * SD_CLK_EN (RW) - * - * SD/eMMC Clock Enable - * This bit stops the SDCLK or RCLK when set to 0. - * The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. - * The value is reflected on the clk2card_on pin. - * Values: - * 0x0 (FALSE): Disable providing SDCLK/RCLK - * 0x1 (TRUE): Enable providing SDCLK/RCLK - */ -#define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U) -#define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U) -#define SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) -#define SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) - -/* - * INTERNAL_CLK_STABLE (RW) - * - * Internal Clock Stable - * This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. - * This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, - * and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. - * Values: - * 0x0 (FALSE): Not Ready - * 0x1 (TRUE): Ready - */ -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) - -/* - * INTERNAL_CLK_EN (RW) - * - * Internal Clock Enable - * This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. - * The Host Controller must stop its internal clock to enter a very low power state. - * However, registers can still be read and written to. The value is reflected on the intclk_en signal. - * Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . - * Values: - * 0x0 (FALSE): Stop - * 0x1 (TRUE): Oscillate - */ -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) - -/* Bitfield definition for register: INT_STAT */ -/* - * BOOT_ACK_ERR (R/W1C) - * - * Boot Acknowledgment Error - * This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. - * In SD/UHS-II mode, this bit is irrelevant. - */ -#define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL) -#define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U) -#define SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) -#define SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) - -/* - * RESP_ERR (R/W1C) - * - * Response Error - * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. - * If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL) -#define SDXC_INT_STAT_RESP_ERR_SHIFT (27U) -#define SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK) -#define SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT) - -/* - * TUNING_ERR (R/W1C) - * - * Tuning Error - * This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure - * (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). - * By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. - * To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. - * The Tuning Error is higher priority than the other error interrupts generated during data transfer. - * By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. - * This is applicable in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL) -#define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U) -#define SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK) -#define SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT) - -/* - * ADMA_ERR (R/W1C) - * - * ADMA Error - * This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: - * Error response received from System bus (Master I/F) - * ADMA3,ADMA2 Descriptors invalid - * CQE Task or Transfer descriptors invalid - * When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. - * In eMMC CQE mode: - * The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. - * ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. - * The Host Driver may find that Valid bit is not set at the error descriptor. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL) -#define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U) -#define SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK) -#define SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT) - -/* - * AUTO_CMD_ERR (R/W1C) - * - * Auto CMD Error - * This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. - * This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. - * D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL) -#define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U) -#define SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) -#define SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) - -/* - * CUR_LMT_ERR (R/W1C) - * - * Current Limit Error - * By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. - * If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. - * A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. - * A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. - * The Host Controller may require some sampling time to detect the current limit. - * SDXC Host Controller does not support this function, this bit is always set to 0. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Power Fail - */ -#define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL) -#define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U) -#define SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) -#define SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) - -/* - * DATA_END_BIT_ERR (R/W1C) - * - * Data End Bit Error - * This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) - -/* - * DATA_CRC_ERR (R/W1C) - * - * Data CRC Error - * This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, - * when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL) -#define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U) -#define SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) -#define SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) - -/* - * DATA_TOUT_ERR (R/W1C) - * - * Data Timeout Error - * This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: - * Busy timeout for R1b, R5b type - * Busy timeout after Write CRC status - * Write CRC Status timeout - * Read Data timeout - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Time out - */ -#define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL) -#define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U) -#define SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) -#define SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) - -/* - * CMD_IDX_ERR (R/W1C) - * - * Command Index Error - * This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL) -#define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U) -#define SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) -#define SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) - -/* - * CMD_END_BIT_ERR (R/W1C) - * - * Command End Bit Error - * This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): End Bit error generated - */ -#define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) - -/* - * CMD_CRC_ERR (R/W1C) - * - * Command CRC Error - * Command CRC Error is generated in SD/eMMC mode for following two cases. - * If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. - * The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. - * If the Host Controller drives the CMD line to 1 level, - * but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. - * The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): CRC error generated - */ -#define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL) -#define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U) -#define SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) -#define SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) - -/* - * CMD_TOUT_ERR (R/W1C) - * - * Command Timeout Error - * In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. - * If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Time out - */ -#define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL) -#define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U) -#define SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) -#define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) - -/* - * ERR_INTERRUPT (RO) - * - * Error Interrupt - * If any of the bits in the Error Interrupt Status register are set, then this bit is set. - * Values: - * 0x0 (FALSE): No Error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U) -#define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U) -#define SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT) - -/* - * CQE_EVENT (R/W1C) - * - * Command Queuing Event - * This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. - * Values: - * 0x0 (FALSE): No Event - * 0x1 (TRUE): Command Queuing Event is detected - */ -#define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U) -#define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U) -#define SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK) -#define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT) - -/* - * FX_EVENT (RO) - * - * FX Event - * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. - * Values: - * 0x0 (FALSE): No Event - * 0x1 (TRUE): FX Event is detected - */ -#define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U) -#define SDXC_INT_STAT_FX_EVENT_SHIFT (13U) -#define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT) - -/* - * RE_TUNE_EVENT (RO) - * - * Re-tuning Event - * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - */ -#define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U) -#define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U) -#define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT) - -/* - * CARD_INTERRUPT (RO) - * - * Card Interrupt - * This bit reflects the synchronized value of: - * DAT[1] Interrupt Input for SD Mode - * DAT[2] Interrupt Input for UHS-II Mode - * Values: - * 0x0 (FALSE): No Card Interrupt - * 0x1 (TRUE): Generate Card Interrupt - */ -#define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U) -#define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U) -#define SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT) - -/* - * CARD_REMOVAL (R/W1C) - * - * Card Removal - * This bit is set if the Card Inserted in the Present State register changes from 1 to 0. - * Values: - * 0x0 (FALSE): Card state stable or Debouncing - * 0x1 (TRUE): Card Removed - */ -#define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U) -#define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U) -#define SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK) -#define SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT) - -/* - * CARD_INSERTION (R/W1C) - * - * Card Insertion - * This bit is set if the Card Inserted in the Present State register changes from 0 to 1. - * Values: - * 0x0 (FALSE): Card state stable or Debouncing - * 0x1 (TRUE): Card Inserted - */ -#define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U) -#define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U) -#define SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK) -#define SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT) - -/* - * BUF_RD_READY (R/W1C) - * - * Buffer Read Ready - * This bit is set if the Buffer Read Enable changes from 0 to 1. - * Values: - * 0x0 (FALSE): Not ready to read buffer - * 0x1 (TRUE): Ready to read buffer - */ -#define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U) -#define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U) -#define SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK) -#define SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT) - -/* - * BUF_WR_READY (R/W1C) - * - * Buffer Write Ready - * This bit is set if the Buffer Write Enable changes from 0 to 1. - * Values: - * 0x0 (FALSE): Not ready to write buffer - * 0x1 (TRUE): Ready to write buffer - */ -#define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U) -#define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U) -#define SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK) -#define SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT) - -/* - * DMA_INTERRUPT (R/W1C) - * - * DMA Interrupt - * This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. - * In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. - * This interrupt is not generated after a Transfer Complete. - * Values: - * 0x0 (FALSE): No DMA Interrupt - * 0x1 (TRUE): DMA Interrupt is generated - */ -#define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U) -#define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U) -#define SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) -#define SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) - -/* - * BGAP_EVENT (R/W1C) - * - * Block Gap Event - * This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. - * Values: - * 0x0 (FALSE): No Block Gap Event - * 0x1 (TRUE): Transaction stopped at block gap - */ -#define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U) -#define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U) -#define SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK) -#define SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT) - -/* - * XFER_COMPLETE (R/W1C) - * - * Transfer Complete - * This bit is set when a read/write transfer and a command with status busy is completed. - * Values: - * 0x0 (FALSE): Not complete - * 0x1 (TRUE): Command execution is completed - */ -#define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U) -#define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U) -#define SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK) -#define SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT) - -/* - * CMD_COMPLETE (R/W1C) - * - * Command Complete - * In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. - * This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. - * Values: - * 0x0 (FALSE): No command complete - * 0x1 (TRUE): Command Complete - */ -#define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U) -#define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U) -#define SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK) -#define SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT) - -/* Bitfield definition for register: INT_STAT_EN */ -/* - * BOOT_ACK_ERR_STAT_EN (RW) - * - * Boot Acknowledgment Error (eMMC Mode only) - * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) - -/* - * RESP_ERR_STAT_EN (RW) - * - * Response Error Status Enable (SD Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) - -/* - * TUNING_ERR_STAT_EN (RW) - * - * Tuning Error Status Enable (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) - -/* - * ADMA_ERR_STAT_EN (RW) - * - * ADMA Error Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) - -/* - * AUTO_CMD_ERR_STAT_EN (RW) - * - * Auto CMD Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) - -/* - * CUR_LMT_ERR_STAT_EN (RW) - * - * Current Limit Error Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) - -/* - * DATA_END_BIT_ERR_STAT_EN (RW) - * - * Data End Bit Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) - -/* - * DATA_CRC_ERR_STAT_EN (RW) - * - * Data CRC Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) - -/* - * DATA_TOUT_ERR_STAT_EN (RW) - * - * Data Timeout Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) - -/* - * CMD_IDX_ERR_STAT_EN (RW) - * - * Command Index Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) - -/* - * CMD_END_BIT_ERR_STAT_EN (RW) - * - * Command End Bit Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) - -/* - * CMD_CRC_ERR_STAT_EN (RW) - * - * Command CRC Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) - -/* - * CMD_TOUT_ERR_STAT_EN (RW) - * - * Command Timeout Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) - -/* - * CQE_EVENT_STAT_EN (RW) - * - * CQE Event Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) - -/* - * FX_EVENT_STAT_EN (RW) - * - * FX Event Status Enable - * This bit is added from Version 4.10. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) - -/* - * RE_TUNE_EVENT_STAT_EN (RW) - * - * Re-Tuning Event (UHS-I only) Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) - -/* - * CARD_INTERRUPT_STAT_EN (RW) - * - * Card Interrupt Status Enable - * If this bit is set to 0, the Host Controller clears the interrupt request to the System. - * The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. - * The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. - * By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) - -/* - * CARD_REMOVAL_STAT_EN (RW) - * - * Card Removal Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) - -/* - * CARD_INSERTION_STAT_EN (RW) - * - * Card Insertion Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) - -/* - * BUF_RD_READY_STAT_EN (RW) - * - * Buffer Read Ready Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) - -/* - * BUF_WR_READY_STAT_EN (RW) - * - * Buffer Write Ready Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) - -/* - * DMA_INTERRUPT_STAT_EN (RW) - * - * DMA Interrupt Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) - -/* - * BGAP_EVENT_STAT_EN (RW) - * - * Block Gap Event Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) - -/* - * XFER_COMPLETE_STAT_EN (RW) - * - * Transfer Complete Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) - -/* - * CMD_COMPLETE_STAT_EN (RW) - * - * Command Complete Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) - -/* Bitfield definition for register: INT_SIGNAL_EN */ -/* - * BOOT_ACK_ERR_SIGNAL_EN (RW) - * - * Boot Acknowledgment Error (eMMC Mode only). - * Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) - -/* - * RESP_ERR_SIGNAL_EN (RW) - * - * Response Error Signal Enable (SD Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) - -/* - * TUNING_ERR_SIGNAL_EN (RW) - * - * Tuning Error Signal Enable (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) - -/* - * ADMA_ERR_SIGNAL_EN (RW) - * - * ADMA Error Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) - -/* - * AUTO_CMD_ERR_SIGNAL_EN (RW) - * - * Auto CMD Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) - -/* - * CUR_LMT_ERR_SIGNAL_EN (RW) - * - * Current Limit Error Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_END_BIT_ERR_SIGNAL_EN (RW) - * - * Data End Bit Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_CRC_ERR_SIGNAL_EN (RW) - * - * Data CRC Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_TOUT_ERR_SIGNAL_EN (RW) - * - * Data Timeout Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_IDX_ERR_SIGNAL_EN (RW) - * - * Command Index Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_END_BIT_ERR_SIGNAL_EN (RW) - * - * Command End Bit Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_CRC_ERR_SIGNAL_EN (RW) - * - * Command CRC Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_TOUT_ERR_SIGNAL_EN (RW) - * - * Command Timeout Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) - -/* - * CQE_EVENT_SIGNAL_EN (RW) - * - * Command Queuing Engine Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) - -/* - * FX_EVENT_SIGNAL_EN (RW) - * - * FX Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) - -/* - * RE_TUNE_EVENT_SIGNAL_EN (RW) - * - * Re-Tuning Event (UHS-I only) Signal Enable. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) - -/* - * CARD_INTERRUPT_SIGNAL_EN (RW) - * - * Card Interrupt Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) - -/* - * CARD_REMOVAL_SIGNAL_EN (RW) - * - * Card Removal Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) - -/* - * CARD_INSERTION_SIGNAL_EN (RW) - * - * Card Insertion Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) - -/* - * BUF_RD_READY_SIGNAL_EN (RW) - * - * Buffer Read Ready Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) - -/* - * BUF_WR_READY_SIGNAL_EN (RW) - * - * Buffer Write Ready Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) - -/* - * DMA_INTERRUPT_SIGNAL_EN (RW) - * - * DMA Interrupt Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) - -/* - * BGAP_EVENT_SIGNAL_EN (RW) - * - * Block Gap Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) - -/* - * XFER_COMPLETE_SIGNAL_EN (RW) - * - * Transfer Complete Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) - -/* - * CMD_COMPLETE_SIGNAL_EN (RW) - * - * Command Complete Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) - -/* Bitfield definition for register: AC_HOST_CTRL */ -/* - * PRESET_VAL_ENABLE (RW) - * - * Preset Value Enable - * This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. - * When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. - * These values are selected from set of Preset Value registers based on selected speed mode. - * Values: - * 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver - * 0x1 (TRUE): Automatic Selection by Preset Value are Enabled - */ -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) - -/* - * ASYNC_INT_ENABLE (RW) - * - * Asynchronous Interrupt Enable - * This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. - * Values: - * 0x0 (FALSE): Disabled - * 0x1 (TRUE): Enabled - */ -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) - -/* - * HOST_VER4_ENABLE (RW) - * - * Host Version 4 Enable - * This bit selects either Version 3.00 compatible mode or Version 4 mode. - * Functions of following fields are modified for Host Version 4 mode: - * SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) - * ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register - * 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 - * Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register - * 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register - * Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, - * UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). - * Values: - * 0x0 (FALSE): Version 3.00 compatible mode - * 0x1 (TRUE): Version 4 mode - */ -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) - -/* - * CMD23_ENABLE (RW) - * - * CMD23 Enable - * If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. - * Values: - * 0x0 (FALSE): Auto CMD23 is disabled - * 0x1 (TRUE): Auto CMD23 is enabled - */ -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) - -/* - * ADMA2_LEN_MODE (RW) - * - * ADMA2 Length Mode - * This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. - * Values: - * 0x0 (FALSE): 16-bit Data Length Mode - * 0x1 (TRUE): 26-bit Data Length Mode - */ -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) - -/* - * SAMPLE_CLK_SEL (RW) - * - * Sampling Clock Select - * This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. - * This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). - * Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. - * The value is reflected on the sample_cclk_sel pin. - * Values: - * 0x0 (FALSE): Fixed clock is used to sample data - * 0x1 (TRUE): Tuned clock is used to sample data - */ -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) - -/* - * EXEC_TUNING (RW) - * - * Execute Tuning - * This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. - * Values: - * 0x0 (FALSE): Not Tuned or Tuning completed - * 0x1 (TRUE): Execute Tuning - */ -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) - -/* - * SIGNALING_EN (RW) - * - * 1.8V Signaling Enable - * This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. - * Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. - * Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. - * Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). - * Values: - * 0x0 (V_3_3): 3.3V Signalling - * 0x1 (V_1_8): 1.8V Signalling - */ -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) - -/* - * UHS_MODE_SEL (RW) - * - * UHS Mode/eMMC Speed Mode Select - * These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. - * UHS Mode (SD/UHS-II mode only): - * 0x0 (SDR12): SDR12/Legacy - * 0x1 (SDR25): SDR25/High Speed SDR - * 0x2 (SDR50): SDR50 - * 0x3 (SDR104): SDR104/HS200 - * 0x4 (DDR50): DDR50/High Speed DDR - * 0x5 (RSVD5): Reserved - * 0x6 (RSVD6): Reserved - * 0x7 (UHS2): UHS-II/HS400 - * eMMC Speed Mode (eMMC mode only): - * 0x0: Legacy - * 0x1: High Speed SDR - * 0x2: Reserved - * 0x3: HS200 - * 0x4: High Speed DDR - * 0x5: Reserved - * 0x6: Reserved - * 0x7: HS400 - */ -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) - -/* - * CMD_NOT_ISSUED_AUTO_CMD12 (RO) - * - * Command Not Issued By Auto CMD12 Error - * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. - * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. - * Values: - * 0x1 (TRUE): Not Issued - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) - -/* - * AUTO_CMD_RESP_ERR (RO) - * - * Auto CMD Response Error - * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. - * This status is ignored if any bit between D00 to D04 is set to 1. - * Values: - * 0x1 (TRUE): Error - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT) - -/* - * AUTO_CMD_IDX_ERR (RO) - * - * Auto CMD Index Error - * This bit is set if the command index error occurs in response to a command. - * Values: - * 0x1 (TRUE): Error - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT) - -/* - * AUTO_CMD_EBIT_ERR (RO) - * - * Auto CMD End Bit Error - * This bit is set when detecting that the end bit of command response is 0. - * Values: - * 0x1 (TRUE): End Bit Error Generated - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT) - -/* - * AUTO_CMD_CRC_ERR (RO) - * - * Auto CMD CRC Error - * This bit is set when detecting a CRC error in the command response. - * Values: - * 0x1 (TRUE): CRC Error Generated - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT) - -/* - * AUTO_CMD_TOUT_ERR (RO) - * - * Auto CMD Timeout Error - * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. - * If this bit is set to 1, error status bits (D04-D01) are meaningless. - * Values: - * 0x1 (TRUE): Time out - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT) - -/* - * AUTO_CMD12_NOT_EXEC (RO) - * - * Auto CMD12 Not Executed - * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. - * Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - * If this bit is set to 1, error status bits (D04-D01) is meaningless. - * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. - * Values: - * 0x1 (TRUE): Not Executed - * 0x0 (FALSE): Executed - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT) - -/* Bitfield definition for register: CAPABILITIES1 */ -/* - * SLOT_TYPE_R (RO) - * - * Slot Type - * These bits indicate usage of a slot by a specific Host System. - * Values: - * 0x0 (REMOVABLE_SLOT): Removable Card Slot - * 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device - * 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) - * 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - */ -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL) -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U) -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT) - -/* - * ASYNC_INT_SUPPORT (RO) - * - * Asynchronous Interrupt Support (SD Mode only) - * Values: - * 0x0 (FALSE): Asynchronous Interrupt Not Supported - * 0x1 (TRUE): Asynchronous Interrupt Supported - */ -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL) -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U) -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT) - -/* - * VOLT_18 (RO) - * - * Voltage Support for 1.8V - * Values: - * 0x0 (FALSE): 1.8V Not Supported - * 0x1 (TRUE): 1.8V Supported - */ -#define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL) -#define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U) -#define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT) - -/* - * VOLT_30 (RO) - * - * Voltage Support for SD 3.0V or Embedded 1.2V - * Values: - * 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported - * 0x1 (TRUE): SD 3.0V or Embedded Supported - */ -#define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL) -#define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U) -#define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT) - -/* - * VOLT_33 (RO) - * - * Voltage Support for 3.3V - * Values: - * 0x0 (FALSE): 3.3V Not Supported - * 0x1 (TRUE): 3.3V Supported - */ -#define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL) -#define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U) -#define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT) - -/* - * SUS_RES_SUPPORT (RO) - * - * Suspense/Resume Support - * This bit indicates whether the Host Controller supports Suspend/Resume functionality. - * If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. - * Values: - * 0x0 (FALSE): Not Supported - * 0x1 (TRUE): Supported - */ -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL) -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U) -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT) - -/* - * SDMA_SUPPORT (RO) - * - * SDMA Support - * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. - * Values: - * 0x0 (FALSE): SDMA not Supported - * 0x1 (TRUE): SDMA Supported - */ -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL) -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U) -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT) - -/* - * HIGH_SPEED_SUPPORT (RO) - * - * High Speed Support - * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. - * Values: - * 0x0 (FALSE): High Speed not Supported - * 0x1 (TRUE): High Speed Supported - */ -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL) -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U) -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT) - -/* - * ADMA2_SUPPORT (RO) - * - * ADMA2 Support - * This bit indicates whether the Host Controller is capable of using ADMA2. - * Values: - * 0x0 (FALSE): ADMA2 not Supported - * 0x1 (TRUE): ADMA2 Supported - */ -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL) -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U) -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT) - -/* - * EMBEDDED_8_BIT (RO) - * - * 8-bit Support for Embedded Device - * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. - * Values: - * 0x0 (FALSE): 8-bit Bus Width not Supported - * 0x1 (TRUE): 8-bit Bus Width Supported - */ -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL) -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U) -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT) - -/* - * MAX_BLK_LEN (RO) - * - * Maximum Block Length - * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. - * The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit - * Values: - * 0x0 (ZERO): 512 Byte - * 0x1 (ONE): 1024 Byte - * 0x2 (TWO): 2048 Byte - * 0x3 (THREE): Reserved - */ -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL) -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U) -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT) - -/* - * BASE_CLK_FREQ (RO) - * - * Base Clock Frequency for SD clock - * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. - * 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. - * The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. - * -0x00 : Get information through another method - * -0x01 : 1 MHz - * -0x02 : 2 MHz - * -............. - * -0x3F : 63 MHz - * -0x40-0xFF : Not Supported - * 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. - * -0x00 : Get information through another method - * -0x01 : 1 MHz - * -0x02 : 2 MHz - * -............ - * -0xFF : 255 MHz - * If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. - * If these bits are all 0, the Host system has to get information using a different method. - */ -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U) -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U) -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT) - -/* - * TOUT_CLK_UNIT (RO) - * - * Timeout Clock Unit - * This bit shows the unit of base clock frequency used to detect Data TImeout Error. - * Values: - * 0x0 (KHZ): KHz - * 0x1 (MHZ): MHz - */ -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U) -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U) -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT) - -/* - * TOUT_CLK_FREQ (RO) - * - * Timeout Clock Frequency - * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. - * 0x00 : Get information through another method - * 0x01 : 1KHz / 1MHz - * 0x02 : 2KHz / 2MHz - * 0x03 : 3KHz / 3MHz - * ........... - * 0x3F : 63KHz / 63MHz - */ -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU) -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U) -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT) - -/* Bitfield definition for register: CAPABILITIES2 */ -/* - * VDD2_18V_SUPPORT (RO) - * - * 1.8V VDD2 Support - * This bit indicates support of VDD2 for the Host System. - * 0x0 (FALSE): 1.8V VDD2 is not Supported - * 0x1 (TRUE): 1.8V VDD2 is Supported - */ -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL) -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U) -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT) - -/* - * ADMA3_SUPPORT (RO) - * - * ADMA3 Support - * This bit indicates whether the Host Controller is capable of using ADMA3. - * Values: - * 0x0 (FALSE): ADMA3 not Supported - * 0x1 (TRUE): ADMA3 Supported - */ -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL) -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U) -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT) - -/* - * CLK_MUL (RO) - * - * Clock Multiplier - * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. - * 0x0: Clock Multiplier is not Supported - * 0x1: Clock Multiplier M = 2 - * 0x2: Clock Multiplier M = 3 - * ......... - * 0xFF: Clock Multiplier M = 256 - */ -#define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL) -#define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U) -#define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT) - -/* - * RE_TUNING_MODES (RO) - * - * Re-Tuning Modes (UHS-I only) - * These bits select the re-tuning method and limit the maximum data length. - * Values: - * 0x0 (MODE1): Timer - * 0x1 (MODE2): Timer and Re-Tuning Request (Not supported) - * 0x2 (MODE3): Auto Re-Tuning (for transfer) - * 0x3 (RSVD_MODE): Reserved - */ -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U) -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U) -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT) - -/* - * USE_TUNING_SDR50 (RO) - * - * Use Tuning for SDR50 (UHS-I only) - * Values: - * 0x0 (ZERO): SDR50 does not require tuning - * 0x1 (ONE): SDR50 requires tuning - */ -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U) -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U) -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT) - -/* - * RETUNE_CNT (RO) - * - * Timer Count for Re-Tuning (UHS-I only) - * 0x0: Re-Tuning Timer disabled - * 0x1: 1 seconds - * 0x2: 2 seconds - * 0x3: 4 seconds - * ........ - * 0xB: 1024 seconds - * 0xC: Reserved - * 0xD: Reserved - * 0xE: Reserved - * 0xF: Get information from other source - */ -#define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U) -#define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U) -#define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT) - -/* - * DRV_TYPED (RO) - * - * Driver Type D Support (UHS-I only) - * This bit indicates support of Driver Type D for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type D is not supported - * 0x1 (TRUE): Driver Type D is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U) -#define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U) -#define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT) - -/* - * DRV_TYPEC (RO) - * - * Driver Type C Support (UHS-I only) - * This bit indicates support of Driver Type C for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type C is not supported - * 0x1 (TRUE): Driver Type C is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U) -#define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U) -#define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT) - -/* - * DRV_TYPEA (RO) - * - * Driver Type A Support (UHS-I only) - * This bit indicates support of Driver Type A for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type A is not supported - * 0x1 (TRUE): Driver Type A is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U) -#define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U) -#define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT) - -/* - * UHS2_SUPPORT (RO) - * - * UHS-II Support (UHS-II only) - * This bit indicates whether Host Controller supports UHS-II. - * Values: - * 0x0 (FALSE): UHS-II is not supported - * 0x1 (TRUE): UHS-II is supported - */ -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U) -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U) -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT) - -/* - * DDR50_SUPPORT (RO) - * - * DDR50 Support (UHS-I only) - * Values: - * 0x0 (FALSE): DDR50 is not supported - * 0x1 (TRUE): DDR50 is supported - */ -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U) -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U) -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT) - -/* - * SDR104_SUPPORT (RO) - * - * SDR104 Support (UHS-I only) - * This bit mentions that SDR104 requires tuning. - * Values: - * 0x0 (FALSE): SDR104 is not supported - * 0x1 (TRUE): SDR104 is supported - */ -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U) -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U) -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT) - -/* - * SDR50_SUPPORT (RO) - * - * SDR50 Support (UHS-I only) - * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. - * Values: - * 0x0 (FALSE): SDR50 is not supported - * 0x1 (TRUE): SDR50 is supported - */ -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U) -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U) -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT) - -/* Bitfield definition for register: CURR_CAPABILITIES1 */ -/* - * MAX_CUR_18V (RO) - * - * Maximum Current for 1.8V - * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT) - -/* - * MAX_CUR_30V (RO) - * - * Maximum Current for 3.0V - * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT) - -/* - * MAX_CUR_33V (RO) - * - * Maximum Current for 3.3V - * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT) - -/* Bitfield definition for register: CURR_CAPABILITIES2 */ -/* - * MAX_CUR_VDD2_18V (RO) - * - * Maximum Current for 1.8V VDD2 - * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU) -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U) -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT) - -/* Bitfield definition for register: FORCE_EVENT */ -/* - * FORCE_BOOT_ACK_ERR (WO) - * - * Force Event for Boot Ack error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Boot ack Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) - -/* - * FORCE_RESP_ERR (WO) - * - * Force Event for Response Error (SD Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Response Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) - -/* - * FORCE_TUNING_ERR (WO) - * - * Force Event for Tuning Error (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Tuning Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) - -/* - * FORCE_ADMA_ERR (WO) - * - * Force Event for ADMA Error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): ADMA Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_ERR (WO) - * - * Force Event for Auto CMD Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Auto CMD Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) - -/* - * FORCE_CUR_LMT_ERR (WO) - * - * Force Event for Current Limit Error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Current Limit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) - -/* - * FORCE_DATA_END_BIT_ERR (WO) - * - * Force Event for Data End Bit Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data End Bit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) - -/* - * FORCE_DATA_CRC_ERR (WO) - * - * Force Event for Data CRC Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data CRC Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) - -/* - * FORCE_DATA_TOUT_ERR (WO) - * - * Force Event for Data Timeout Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data Timeout Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) - -/* - * FORCE_CMD_IDX_ERR (WO) - * - * Force Event for Command Index Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command Index Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) - -/* - * FORCE_CMD_END_BIT_ERR (WO) - * - * Force Event for Command End Bit Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command End Bit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) - -/* - * FORCE_CMD_CRC_ERR (WO) - * - * Force Event for Command CRC Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command CRC Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) - -/* - * FORCE_CMD_TOUT_ERR (WO) - * - * Force Event for Command Timeout Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command Timeout Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) - -/* - * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (WO) - * - * Force Event for Command Not Issued By Auto CMD12 Error - * Values: - * 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) - -/* - * FORCE_AUTO_CMD_RESP_ERR (WO) - * - * Force Event for Auto CMD Response Error - * Values: - * 0x1 (TRUE): Auto CMD Response Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_IDX_ERR (WO) - * - * Force Event for Auto CMD Index Error - * Values: - * 0x1 (TRUE): Auto CMD Index Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_EBIT_ERR (WO) - * - * Force Event for Auto CMD End Bit Error - * Values: - * 0x1 (TRUE): Auto CMD End Bit Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_CRC_ERR (WO) - * - * Force Event for Auto CMD CRC Error - * Values: - * 0x1 (TRUE): Auto CMD CRC Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_TOUT_ERR (WO) - * - * Force Event for Auto CMD Timeout Error - * Values: - * 0x1 (TRUE): Auto CMD Timeout Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD12_NOT_EXEC (WO) - * - * Force Event for Auto CMD12 Not Executed - * Values: - * 0x1 (TRUE): Auto CMD12 Not Executed Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) - -/* Bitfield definition for register: ADMA_ERR_STAT */ -/* - * ADMA_LEN_ERR (RO) - * - * ADMA Length Mismatch Error States - * This error occurs in the following instances: - * While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length - * When the total data length cannot be divided by the block length - * Values: - * 0x0 (NO_ERR): No Error - * 0x1 (ERROR): Error - */ -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U) -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U) -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT) - -/* - * ADMA_ERR_STATES (RO) - * - * ADMA Error States - * These bits indicate the state of ADMA when an error occurs during ADMA data transfer. - * Values: - * 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor - * 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor - * 0x2 (UNUSED): Never set this state - * 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - */ -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U) -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U) -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT) - -/* Bitfield definition for register: ADMA_SYS_ADDR */ -/* - * ADMA_SA (RW) - * - * ADMA System Address - * These bits indicate the lower 32 bits of the ADMA system address. - * SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location - * ADMA2: This register stores the byte address of the executing command of the descriptor table - * ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - */ -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) - -/* Bitfield definition for register array: PRESET */ -/* - * CLK_GEN_SEL_VAL (RO) - * - * Clock Generator Select Value - * This bit is effective when the Host Controller supports a programmable clock generator. - * Values: - * 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator - * 0x1 (PROG): Programmable Clock Generator - */ -#define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U) -#define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U) -#define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT) - -/* - * FREQ_SEL_VAL (RO) - * - * SDCLK/RCLK Frequency Select Value - * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - */ -#define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU) -#define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U) -#define SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT) - -/* Bitfield definition for register: ADMA_ID_ADDR */ -/* - * ADMA_ID_ADDR (RW) - * - * ADMA Integrated Descriptor Address - * These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. - * The start address of Integrated Descriptor is set to these register bits. - * The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - */ -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) - -/* Bitfield definition for register: P_EMBEDDED_CNTRL */ -/* - * REG_OFFSET_ADDR (RO) - * - * Offset Address of Embedded Control register. - */ -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU) -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */ -/* - * REG_OFFSET_ADDR (RO) - * - * Base offset Address for Vendor-Specific registers. - */ -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU) -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */ -/* - * REG_OFFSET_ADDR (RO) - * - * Base offset Address for Command Queuing registers. - */ -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU) -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: SLOT_INTR_STATUS */ -/* - * INTR_SLOT (RO) - * - * Interrupt signal for each Slot - * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. - * A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - * By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. - * Bit 00: Slot 1 - * Bit 01: Slot 2 - * Bit 02: Slot 3 - * .......... - * .......... - * Bit 07: Slot 8 - * Note: MSHC Host Controller support single card slot. This register shall always return 0. - */ -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU) -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U) -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT) - -/* Bitfield definition for register: CQVER */ -/* - * EMMC_VER_MAHOR (RO) - * - * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U) -#define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U) -#define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT) - -/* - * EMMC_VER_MINOR (RO) - * - * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U) -#define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U) -#define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT) - -/* - * EMMC_VER_SUFFIX (RO) - * - * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU) -#define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U) -#define SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT) - -/* Bitfield definition for register: CQCAP */ -/* - * CRYPTO_SUPPORT (RO) - * - * Crypto Support - * This bit indicates whether the Host Controller supports cryptographic operations. - * Values: - * 0x0 (FALSE): Crypto not Supported - * 0x1 (TRUE): Crypto Supported - */ -#define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL) -#define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U) -#define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT) - -/* - * ITCFMUL (RO) - * - * Internal Timer Clock Frequency Multiplier (ITCFMUL) - * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS - * polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. - * Values: - * 0x0 (CLK_1KHz): 1KHz clock - * 0x1 (CLK_10KHz): 10KHz clock - * 0x2 (CLK_100KHz): 100KHz clock - * 0x3 (CLK_1MHz): 1MHz clock - * 0x4 (CLK_10MHz): 10MHz clock - */ -#define SDXC_CQCAP_ITCFMUL_MASK (0xF000U) -#define SDXC_CQCAP_ITCFMUL_SHIFT (12U) -#define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT) - -/* - * ITCFVAL (RO) - * - * Internal Timer Clock Frequency Value (ITCFVAL) - * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - */ -#define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU) -#define SDXC_CQCAP_ITCFVAL_SHIFT (0U) -#define SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT) - -/* Bitfield definition for register: CQCFG */ -/* - * DCMD_EN (RW) - * - * This bit indicates to the hardware whether the Task - * Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. - * Values: - * 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - * 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - */ -#define SDXC_CQCFG_DCMD_EN_MASK (0x1000U) -#define SDXC_CQCFG_DCMD_EN_SHIFT (12U) -#define SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK) -#define SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT) - -/* - * TASK_DESC_SIZE (RW) - * - * Bit Value Description - * This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). - * Values: - * 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - * 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - */ -#define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U) -#define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U) -#define SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) -#define SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) - -/* - * CQ_EN (RW) - * - */ -#define SDXC_CQCFG_CQ_EN_MASK (0x1U) -#define SDXC_CQCFG_CQ_EN_SHIFT (0U) -#define SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK) -#define SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT) - -/* Bitfield definition for register: CQCTL */ -/* - * CLR_ALL_TASKS (RW) - * - * Clear all tasks - * This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. - * Values: - * 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller - * 0x0 (NO_EFFECT): Programming 0 has no effect - */ -#define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U) -#define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U) -#define SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) -#define SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) - -/* - * HALT (RW) - * - * Halt request and resume - * Values: - * 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. - * For example, issuing a Discard Task command (CMDQ_TASK_MGMT). - * When the software writes 1, CQE completes the ongoing task (if any in progress). - * After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. - * The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. - * 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - */ -#define SDXC_CQCTL_HALT_MASK (0x1U) -#define SDXC_CQCTL_HALT_SHIFT (0U) -#define SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK) -#define SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT) - -/* Bitfield definition for register: CQIS */ -/* - * TCL (RW) - * - * Task cleared interrupt - * This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. - * The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): TCL Interrupt is set - * 0x0 (NOTSET): TCL Interrupt is not set - */ -#define SDXC_CQIS_TCL_MASK (0x8U) -#define SDXC_CQIS_TCL_SHIFT (3U) -#define SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK) -#define SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT) - -/* - * RED (RW) - * - * Response error detected interrupt - * This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status - * field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): RED Interrupt is set - * 0x0 (NOTSET): RED Interrupt is not set - */ -#define SDXC_CQIS_RED_MASK (0x4U) -#define SDXC_CQIS_RED_SHIFT (2U) -#define SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK) -#define SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT) - -/* - * TCC (RW) - * - * Task complete interrupt - * This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: - * A task is completed and the INT bit is set in its Task Descriptor - * Interrupt caused by Interrupt Coalescing logic due to timeout - * Interrupt Coalescing logic reached the configured threshold - * A value of 1 clears this status bit - */ -#define SDXC_CQIS_TCC_MASK (0x2U) -#define SDXC_CQIS_TCC_SHIFT (1U) -#define SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK) -#define SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT) - -/* - * HAC (RW) - * - * Halt complete interrupt - * This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): HAC Interrupt is set - * 0x0 (NOTSET): HAC Interrupt is not set - */ -#define SDXC_CQIS_HAC_MASK (0x1U) -#define SDXC_CQIS_HAC_SHIFT (0U) -#define SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK) -#define SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT) - -/* Bitfield definition for register: CQISE */ -/* - * TCL_STE (RW) - * - * Task cleared interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - */ -#define SDXC_CQISE_TCL_STE_MASK (0x8U) -#define SDXC_CQISE_TCL_STE_SHIFT (3U) -#define SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK) -#define SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT) - -/* - * RED_STE (RW) - * - * Response error detected interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.RED is disabled - */ -#define SDXC_CQISE_RED_STE_MASK (0x4U) -#define SDXC_CQISE_RED_STE_SHIFT (2U) -#define SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK) -#define SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT) - -/* - * TCC_STE (RW) - * - * Task complete interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - */ -#define SDXC_CQISE_TCC_STE_MASK (0x2U) -#define SDXC_CQISE_TCC_STE_SHIFT (1U) -#define SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK) -#define SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT) - -/* - * HAC_STE (RW) - * - * Halt complete interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - */ -#define SDXC_CQISE_HAC_STE_MASK (0x1U) -#define SDXC_CQISE_HAC_STE_SHIFT (0U) -#define SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK) -#define SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT) - -/* Bitfield definition for register: CQISGE */ -/* - * TCL_SGE (RW) - * - * Task cleared interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - */ -#define SDXC_CQISGE_TCL_SGE_MASK (0x8U) -#define SDXC_CQISGE_TCL_SGE_SHIFT (3U) -#define SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK) -#define SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT) - -/* - * RED_SGE (RW) - * - * Response error detected interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - */ -#define SDXC_CQISGE_RED_SGE_MASK (0x4U) -#define SDXC_CQISGE_RED_SGE_SHIFT (2U) -#define SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK) -#define SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT) - -/* - * TCC_SGE (RW) - * - * Task complete interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - */ -#define SDXC_CQISGE_TCC_SGE_MASK (0x2U) -#define SDXC_CQISGE_TCC_SGE_SHIFT (1U) -#define SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK) -#define SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT) - -/* - * HAC_SGE (RW) - * - * Halt complete interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - */ -#define SDXC_CQISGE_HAC_SGE_MASK (0x1U) -#define SDXC_CQISGE_HAC_SGE_SHIFT (0U) -#define SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK) -#define SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT) - -/* Bitfield definition for register: CQIC */ -/* - * INTC_EN (RW) - * - * Interrupt Coalescing Enable Bit - * Values: - * 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated - * 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - */ -#define SDXC_CQIC_INTC_EN_MASK (0x80000000UL) -#define SDXC_CQIC_INTC_EN_SHIFT (31U) -#define SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK) -#define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT) - -/* - * INTC_STAT (RO) - * - * Interrupt Coalescing Status Bit - * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt - * coalescing (that is, this is set if and only if INTC counter > 0). - * Values: - * 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) - * 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - */ -#define SDXC_CQIC_INTC_STAT_MASK (0x100000UL) -#define SDXC_CQIC_INTC_STAT_SHIFT (20U) -#define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT) - -/* - * INTC_RST (WO) - * - * Counter and Timer Reset - * When host driver writes 1, the interrupt coalescing timer and counter are reset. - * Values: - * 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset - * 0x0 (NO_EFFECT): No Effect - */ -#define SDXC_CQIC_INTC_RST_MASK (0x10000UL) -#define SDXC_CQIC_INTC_RST_SHIFT (16U) -#define SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK) -#define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT) - -/* - * INTC_TH_WEN (WO) - * - * Interrupt Coalescing Counter Threshold Write Enable - * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. - * Values: - * 0x1 (WEN_SET): Sets INTC_TH_WEN - * 0x0 (WEN_CLR): Clears INTC_TH_WEN - */ -#define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U) -#define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U) -#define SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK) -#define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT) - -/* - * INTC_TH (WO) - * - * Interrupt Coalescing Counter Threshold filed - * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. - * Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. - * The counter is reset by software during the interrupt service routine. - * The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. - * 0x0: Interrupt coalescing feature disabled - * 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes - * 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes - * ........ - * 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes - * To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - */ -#define SDXC_CQIC_INTC_TH_MASK (0x1F00U) -#define SDXC_CQIC_INTC_TH_SHIFT (8U) -#define SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK) -#define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT) - -/* - * TOUT_VAL_WEN (WO) - * - * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. - * Values: - * 0x1 (WEN_SET): Sets TOUT_VAL_WEN - * 0x0 (WEN_CLR): clears TOUT_VAL_WEN - */ -#define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U) -#define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U) -#define SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK) -#define SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT) - -/* - * TOUT_VAL (RW) - * - * Interrupt Coalescing Timeout Value - * Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. - * Timer Operation: The timer is reset by software during the interrupt service routine. - * It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. - * When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. - * The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. - * 0x0: Timer is disabled. Timeout-based interrupt is not generated - * 0x1: Timeout on 01x1024 cycles of timer clock frequency - * 0x2: Timeout on 02x1024 cycles of timer clock frequency - * ........ - * 0x7f: Timeout on 127x1024 cycles of timer clock frequency - * In order to write to this field, the TOUT_VAL_WEN bit must - * be set at the same write operation. - */ -#define SDXC_CQIC_TOUT_VAL_MASK (0x7FU) -#define SDXC_CQIC_TOUT_VAL_SHIFT (0U) -#define SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK) -#define SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT) - -/* Bitfield definition for register: CQTDLBA */ -/* - * TDLBA (RW) - * - * This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. - * The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. - * This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - */ -#define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL) -#define SDXC_CQTDLBA_TDLBA_SHIFT (0U) -#define SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK) -#define SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT) - -/* Bitfield definition for register: CQTDBR */ -/* - * DBR (RW) - * - * The software configures TDLBA and TDLBAU, and enable - * CQE in CQCFG before using this register. - * Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. - * Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. - * CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. - * CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to - * the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. - * The corresponding bit is cleared to 0 by CQE in one of the following events: - * A task execution is completed (with success or error). - * The task is cleared using CQTCLR register. - * All tasks are cleared using CQCTL register. - * CQE is disabled using CQCFG register. - * Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. - * In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. - * If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - */ -#define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL) -#define SDXC_CQTDBR_DBR_SHIFT (0U) -#define SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK) -#define SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT) - -/* Bitfield definition for register: CQTCN */ -/* - * TCN (RW) - * - * Task Completion Notification - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Task-N has completed execution (with success or errors) - * Bit-N(0): Task-N has not completed, could be pending or not submitted. - * On task completion, software may read this register to know tasks that have completed. After reading this register, - * software may clear the relevant bit fields by writing 1 to the corresponding bits. - */ -#define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL) -#define SDXC_CQTCN_TCN_SHIFT (0U) -#define SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK) -#define SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT) - -/* Bitfield definition for register: CQDQS */ -/* - * DQS (RW) - * - * Device Queue Status - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Device has marked task N as ready for execution - * Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. - * Host controller updates this register with response of the Device Queue Status command. - */ -#define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL) -#define SDXC_CQDQS_DQS_SHIFT (0U) -#define SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK) -#define SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT) - -/* Bitfield definition for register: CQDPT */ -/* - * DPT (RW) - * - * Device-Pending Tasks - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution - * Bit-N(0): Task-N is not yet queued. - * Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. - * The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. - * Software reads this register in the task-discard procedure to determine if the task is queued in the device - */ -#define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL) -#define SDXC_CQDPT_DPT_SHIFT (0U) -#define SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK) -#define SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT) - -/* Bitfield definition for register: CQTCLR */ -/* - * TCLR (RW) - * - * Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. - * This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. - * When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. - * CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. - * Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - */ -#define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL) -#define SDXC_CQTCLR_TCLR_SHIFT (0U) -#define SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK) -#define SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT) - -/* Bitfield definition for register: CQSSC1 */ -/* - * SQSCMD_BLK_CNT (RW) - * - * This field indicates when SQS CMD is sent while data transfer is in progress. - * A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. - * 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. - * 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. - * 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. - * 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. - * ........ - * 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. - * Should be programmed only when CQCFG.CQ_EN is 0 - */ -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) - -/* - * SQSCMD_IDLE_TMR (RW) - * - * This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. - * Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. - * When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. - * Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. - * The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). - * For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). - * If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. - * Should be programmed only when CQCFG.CQ_EN is '0' - */ -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) - -/* Bitfield definition for register: CQSSC2 */ -/* - * SQSCMD_RCA (RW) - * - * This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. - * CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - */ -#define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU) -#define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U) -#define SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK) -#define SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT) - -/* Bitfield definition for register: CQCRDCT */ -/* - * DCMD_RESP (RO) - * - * This register contains the response of the command generated by the last direct command (DCMD) task that was sent. - * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - */ -#define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL) -#define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U) -#define SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT) - -/* Bitfield definition for register: CQRMEM */ -/* - * RESP_ERR_MASK (RW) - * - * The bits of this field are bit mapped to the device response. - * This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. - * 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. - * 0: When a R1/R1b response is received, bit i in the device status is ignored. - * The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. - * Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - */ -#define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL) -#define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U) -#define SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) -#define SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) - -/* Bitfield definition for register: CQTERRI */ -/* - * TRANS_ERR_TASKID (RO) - * - * This field captures the ID of the task that was executed and whose data transfer has errors. - */ -#define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL) -#define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U) -#define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT) - -/* - * TRANS_ERR_CMD_INDX (RO) - * - * This field captures the index of the command that was executed and whose data transfer has errors. - */ -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL) -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U) -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT) - -/* - * RESP_ERR_FIELDS_VALID (RO) - * - * This bit is updated when an error is detected while a command transaction was in progress. - * Values: - * 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields - * 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - */ -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U) -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U) -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT) - -/* - * RESP_ERR_TASKID (RO) - * - * This field captures the ID of the task which was executed on the command line when the error occurred. - */ -#define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U) -#define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U) -#define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT) - -/* - * RESP_ERR_CMD_INDX (RO) - * - * This field captures the index of the command that was executed on the command line when the error occurred - */ -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU) -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U) -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT) - -/* Bitfield definition for register: CQCRI */ -/* - * CMD_RESP_INDX (RO) - * - * Last Command Response index - * This field stores the index of the last received command response. Controller updates the value every time a command response is received - */ -#define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU) -#define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U) -#define SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT) - -/* Bitfield definition for register: CQCRA */ -/* - * CMD_RESP_ARG (RO) - * - * Last Command Response argument - * This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - */ -#define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL) -#define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U) -#define SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT) - -/* Bitfield definition for register: MSHC_VER_ID */ -/* - * VER_ID (RO) - * - */ -#define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL) -#define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U) -#define SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT) - -/* Bitfield definition for register: MSHC_VER_TYPE */ -/* - * VER_TYPE (RO) - * - */ -#define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL) -#define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U) -#define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT) - -/* Bitfield definition for register: EMMC_BOOT_CTRL */ -/* - * BOOT_TOUT_CNT (RW) - * - * Boot Ack Timeout Counter Value. - * This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. - * 0xF : Reserved - * 0xE : TMCLK x 2^27 - * ............ - * 0x1 : TMCLK x 2^14 - * 0x0 : TMCLK x 2^13 - */ -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) - -/* - * BOOT_ACK_ENABLE (RW) - * - * Boot Acknowledge Enable - * When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. - * Values: - * 0x1 (TRUE): Boot Ack enable - * 0x0 (FALSE): Boot Ack disable - */ -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) - -/* - * VALIDATE_BOOT (WO) - * - * Validate Mandatory Boot Enable bit - * This bit is used to validate the MAN_BOOT_EN bit. - * Values: - * 0x1 (TRUE): Validate Mandatory boot enable bit - * 0x0 (FALSE): Ignore Mandatory boot Enable bit - */ -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) - -/* - * MAN_BOOT_EN (RW) - * - * Mandatory Boot Enable - * This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. - * Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. - * Values: - * 0x1 (MAN_BOOT_EN): Mandatory boot enable - * 0x0 (MAN_BOOT_DIS): Mandatory boot disable - */ -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) - -/* - * CQE_PREFETCH_DISABLE (RW) - * - * Enable or Disable CQE's PREFETCH feature - * This field allows Software to disable CQE's data prefetch feature when set to 1. - * Values: - * 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers - * 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - */ -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) - -/* - * CQE_ALGO_SEL (RW) - * - * Scheduler algorithm selected for execution - * This bit selects the Algorithm used for selecting one of the many ready tasks for execution. - * Values: - * 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks - * 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - */ -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) - -/* - * ENH_STROBE_ENABLE (RW) - * - * Enhanced Strobe Enable - * This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. - * Values: - * 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode - * 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - */ -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) - -/* - * EMMC_RST_N_OE (RW) - * - * Output Enable control for EMMC Device Reset signal PAD - * control. - * This field drived sd_rst_n_oe output of SDXC - * Values: - * 0x1 (ENABLE): sd_rst_n_oe is 1 - * 0x0 (DISABLE): sd_rst_n_oe is 0 - */ -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) - -/* - * EMMC_RST_N (RW) - * - * EMMC Device Reset signal control. - * This register field controls the sd_rst_n output of SDXC - * Values: - * 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted - * 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - */ -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) - -/* - * DISABLE_DATA_CRC_CHK (RW) - * - * Disable Data CRC Check - * This bit controls masking of CRC16 error for Card Write in eMMC mode. - * This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, - * which may generate CRC error. This CRC error can be masked using this bit during bus testing. - * Values: - * 0x1 (DISABLE): DATA CRC check is disabled - * 0x0 (ENABLE): DATA CRC check is enabled - */ -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) - -/* - * CARD_IS_EMMC (RW) - * - * eMMC Card present - * This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. - * Values: - * 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card - * 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - */ -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) - -/* Bitfield definition for register: AUTO_TUNING_CTRL */ -/* - * SWIN_TH_VAL (RW) - * - * Sampling window threshold value setting - * The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps - * can use values from 0x0 to 0x1F. - * This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' - * 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. - * 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. - * 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. - * ........ - * 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - */ -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) - -/* - * POST_CHANGE_DLY (RW) - * - * Time taken for phase switching and stable clock output. - * Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. - * Values: - * 0x0 (LATENCY_LT_1): Less than 1-cycle latency - * 0x1 (LATENCY_LT_2): Less than 2-cycle latency - * 0x2 (LATENCY_LT_3): Less than 3-cycle latency - * 0x3 (LATENCY_LT_4): Less than 4-cycle latency - */ -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) - -/* - * PRE_CHANGE_DLY (RW) - * - * Maximum Latency specification between cclk_tx and cclk_rx. - * Values: - * 0x0 (LATENCY_LT_1): Less than 1-cycle latency - * 0x1 (LATENCY_LT_2): Less than 2-cycle latency - * 0x2 (LATENCY_LT_3): Less than 3-cycle latency - * 0x3 (LATENCY_LT_4): Less than 4-cycle latency - */ -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) - -/* - * TUNE_CLK_STOP_EN (RW) - * - * Clock stopping control for Tuning and auto-tuning circuit. - * When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. - * This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - * Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. - * Values: - * 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change - * 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - */ -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) - -/* - * WIN_EDGE_SEL (RW) - * - * This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. - * 0x0: User selection disabled. Tuning calculated edges are used. - * 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. - * 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess - * ... - * 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - */ -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) - -/* - * SW_TUNE_EN (RW) - * - * This fields enables software-managed tuning flow. - * Values: - * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. - * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - */ -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) - -/* - * RPT_TUNE_ERR (RW) - * - * Framing errors are not generated when executing tuning. - * This debug bit allows users to report these errors. - * Values: - * 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors - * 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - */ -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) - -/* - * SWIN_TH_EN (RW) - * - * Sampling window Threshold enable - * Selects the tuning mode - * Field should be programmed only when SAMPLE_CLK_SEL is '0' - * Values: - * 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold - * set by SWIN_TH_VAL field - * 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - */ -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) - -/* - * CI_SEL (RW) - * - * Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. - * Values: - * 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval - * 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - */ -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) - -/* - * AT_EN (RW) - * - * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. - * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. - * This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. - * Values: - * 0x1 (AT_ENABLE): AutoTuning is enabled - * 0x0 (AT_DISABLE): AutoTuning is disabled - */ -#define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) - -/* Bitfield definition for register: AUTO_TUNING_STAT */ -/* - * L_EDGE_PH_CODE (RO) - * - * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - */ -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL) -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U) -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT) - -/* - * R_EDGE_PH_CODE (RO) - * - * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - */ -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U) -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U) -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT) - -/* - * CENTER_PH_CODE (RW) - * - * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - */ -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) - -/* Bitfield definition for register: MISC_CTRL0 */ -/* - * CARDCLK_INV_EN (RW) - * - * set to invert card_clk, for slow speed card to meet 5ns setup timing. - * May cause glitch on clock, should be set before enable clk(in core cfg) - */ -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL) -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U) -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) >> SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) - -/* - * PAD_CLK_SEL_B (RW) - * - * set to use internal clock directly, may have timing issue; - * clr to use clock loopback from pad. - */ -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL) -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U) -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) - -/* - * FREQ_SEL_SW_EN (RW) - * - * set to use FREQ_SEL_SW as card clock divider; - * clear to use core logic as clock divider. - */ -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) - -/* - * TMCLK_EN (RW) - * - * set to force enable tmclk; - * clear to use core signal intclk_en to control it - */ -#define SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U) -#define SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U) -#define SDXC_MISC_CTRL0_TMCLK_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) -#define SDXC_MISC_CTRL0_TMCLK_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) >> SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) - -/* - * FREQ_SEL_SW (RW) - * - * software card clock divider, it will be used only when FREQ_SEL_SW_EN is set - */ -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) - -/* Bitfield definition for register: MISC_CTRL1 */ -/* - * CARD_ACTIVE (RW) - * - * SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). - * When counter finished, this bit will be cleared by hardware. - * Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) - */ -#define SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) - -/* - * CARD_ACTIVE_PERIOD_SEL (RW) - * - * card clock delay config. - * 00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle - */ -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) - - - -/* RESP register group index macro definition */ -#define SDXC_RESP_RESP01 (0UL) -#define SDXC_RESP_RESP23 (1UL) -#define SDXC_RESP_RESP45 (2UL) -#define SDXC_RESP_RESP67 (3UL) - -/* PRESET register group index macro definition */ -#define SDXC_PRESET_INIT (0UL) -#define SDXC_PRESET_DS (1UL) -#define SDXC_PRESET_HS (2UL) -#define SDXC_PRESET_SDR12 (3UL) -#define SDXC_PRESET_SDR25 (4UL) -#define SDXC_PRESET_SDR50 (5UL) -#define SDXC_PRESET_SDR104 (6UL) -#define SDXC_PRESET_DDR50 (7UL) -#define SDXC_PRESET_UHS2 (10UL) - - -#endif /* HPM_SDXC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_spi_regs.h deleted file mode 100644 index 8ee088e0d91..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_spi_regs.h +++ /dev/null @@ -1,784 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SPI_H -#define HPM_SPI_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ - __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ - __RW uint32_t CMD; /* 0x24: Command Register */ - __RW uint32_t ADDR; /* 0x28: Address Register */ - __RW uint32_t DATA; /* 0x2C: Data Register */ - __RW uint32_t CTRL; /* 0x30: Control Register */ - __R uint32_t STATUS; /* 0x34: Status Register */ - __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ - __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */ - __RW uint32_t SLVST; /* 0x60: Slave Status Register */ - __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */ - __R uint32_t CONFIG; /* 0x7C: Configuration Register */ -} SPI_Type; - - -/* Bitfield definition for register: TRANSFMT */ -/* - * ADDRLEN (RW) - * - * Address length in bytes - * 0x0: 1 byte - * 0x1: 2 bytes - * 0x2: 3 bytes - * 0x3: 4 bytes - */ -#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) -#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) -#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) -#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) - -/* - * DATALEN (RW) - * - * The length of each data unit in bits - * The actual bit number of a data unit is (DataLen + 1) - */ -#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) -#define SPI_TRANSFMT_DATALEN_SHIFT (8U) -#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) -#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) - -/* - * DATAMERGE (RW) - * - * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. - * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. - * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - */ -#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) -#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) -#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) -#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) - -/* - * MOSIBIDIR (RW) - * - * Bi-directional MOSI in regular (single) mode - * 0x0: MOSI is uni-directional signal in regular mode. - * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - */ -#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) -#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) -#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) -#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) - -/* - * LSB (RW) - * - * Transfer data with the least significant bit first - * 0x0: Most significant bit first - * 0x1: Least significant bit first - */ -#define SPI_TRANSFMT_LSB_MASK (0x8U) -#define SPI_TRANSFMT_LSB_SHIFT (3U) -#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) -#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) - -/* - * SLVMODE (RW) - * - * SPI Master/Slave mode selection - * 0x0: Master mode - * 0x1: Slave mode - */ -#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) -#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) -#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) -#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) - -/* - * CPOL (RW) - * - * SPI Clock Polarity - * 0x0: SCLK is LOW in the idle states - * 0x1: SCLK is HIGH in the idle states - */ -#define SPI_TRANSFMT_CPOL_MASK (0x2U) -#define SPI_TRANSFMT_CPOL_SHIFT (1U) -#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) -#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) - -/* - * CPHA (RW) - * - * SPI Clock Phase - * 0x0: Sampling data at odd SCLK edges - * 0x1: Sampling data at even SCLK edges - */ -#define SPI_TRANSFMT_CPHA_MASK (0x1U) -#define SPI_TRANSFMT_CPHA_SHIFT (0U) -#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) -#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) - -/* Bitfield definition for register: TRANSCTRL */ -/* - * SLVDATAONLY (RW) - * - * Data-only mode (slave mode only) - * 0x0: Disable the data-only mode - * 0x1: Enable the data-only mode - * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - */ -#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) -#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) -#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) -#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) - -/* - * CMDEN (RW) - * - * SPI command phase enable (Master mode only) - * 0x0: Disable the command phase - * 0x1: Enable the command phase - */ -#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) -#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) -#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) -#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) - -/* - * ADDREN (RW) - * - * SPI address phase enable (Master mode only) - * 0x0: Disable the address phase - * 0x1: Enable the address phase - */ -#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) -#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) -#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) -#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) - -/* - * ADDRFMT (RW) - * - * SPI address phase format (Master mode only) - * 0x0: Address phase is the regular (single) mode - * 0x1: The format of the address phase is the same as the data phase (DualQuad). - */ -#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) -#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) -#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) -#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) - -/* - * TRANSMODE (RW) - * - * Transfer mode - * The transfer sequence could be - * 0x0: Write and read at the same time - * 0x1: Write only - * 0x2: Read only - * 0x3: Write, Read - * 0x4: Read, Write - * 0x5: Write, Dummy, Read - * 0x6: Read, Dummy, Write - * 0x7: None Data (must enable CmdEn or AddrEn in master mode) - * 0x8: Dummy, Write - * 0x9: Dummy, Read - * 0xa~0xf: Reserved - */ -#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) -#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) -#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) -#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) - -/* - * DUALQUAD (RW) - * - * SPI data phase format - * 0x0: Regular (Single) mode - * 0x1: Dual I/O mode - * 0x2: Quad I/O mode - * 0x3: Reserved - */ -#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) -#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) -#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) -#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) - -/* - * TOKENEN (RW) - * - * Token transfer enable (Master mode only) - * Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. - * 0x0: Disable the one-byte special token - * 0x1: Enable the one-byte special token - */ -#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) -#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) -#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) -#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) - -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) -#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) -#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) -#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) - -/* - * TOKENVALUE (RW) - * - * Token value (Master mode only) - * The value of the one-byte special token following the address phase for SPI read transfers. - * 0x0: token value = 0x00 - * 0x1: token value = 0x69 - */ -#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) -#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) -#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) -#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) - -/* - * DUMMYCNT (RW) - * - * Dummy data count. The actual dummy count is (DummyCnt +1). - * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) - * The Data pins are put into the high impedance during the dummy data phase. - * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - */ -#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) -#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) -#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) -#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) - -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) -#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) -#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) -#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * SPI Command - */ -#define SPI_CMD_CMD_MASK (0xFFU) -#define SPI_CMD_CMD_SHIFT (0U) -#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) -#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * SPI Address - * (Master mode only) - */ -#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define SPI_ADDR_ADDR_SHIFT (0U) -#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) -#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Data to transmit or the received data - * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. - * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - */ -#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SPI_DATA_DATA_SHIFT (0U) -#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) -#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * TXTHRES (RW) - * - * Transmit (TX) FIFO Threshold - * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - */ -#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) -#define SPI_CTRL_TXTHRES_SHIFT (16U) -#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) -#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) - -/* - * RXTHRES (RW) - * - * Receive (RX) FIFO Threshold - * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - */ -#define SPI_CTRL_RXTHRES_MASK (0xFF00U) -#define SPI_CTRL_RXTHRES_SHIFT (8U) -#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) -#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) - -/* - * TXDMAEN (RW) - * - * TX DMA enable - */ -#define SPI_CTRL_TXDMAEN_MASK (0x10U) -#define SPI_CTRL_TXDMAEN_SHIFT (4U) -#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) -#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) - -/* - * RXDMAEN (RW) - * - * RX DMA enable - */ -#define SPI_CTRL_RXDMAEN_MASK (0x8U) -#define SPI_CTRL_RXDMAEN_SHIFT (3U) -#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) -#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) - -/* - * TXFIFORST (RW) - * - * Transmit FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_TXFIFORST_MASK (0x4U) -#define SPI_CTRL_TXFIFORST_SHIFT (2U) -#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) -#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) - -/* - * RXFIFORST (RW) - * - * Receive FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_RXFIFORST_MASK (0x2U) -#define SPI_CTRL_RXFIFORST_SHIFT (1U) -#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) -#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) - -/* - * SPIRST (RW) - * - * SPI reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_SPIRST_MASK (0x1U) -#define SPI_CTRL_SPIRST_SHIFT (0U) -#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) -#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TXNUM_7_6 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) -#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) -#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) - -/* - * RXNUM_7_6 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) -#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) -#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) - -/* - * TXFULL (RO) - * - * Transmit FIFO Full flag - */ -#define SPI_STATUS_TXFULL_MASK (0x800000UL) -#define SPI_STATUS_TXFULL_SHIFT (23U) -#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) - -/* - * TXEMPTY (RO) - * - * Transmit FIFO Empty flag - */ -#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) -#define SPI_STATUS_TXEMPTY_SHIFT (22U) -#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) - -/* - * TXNUM_5_0 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) -#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) -#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) - -/* - * RXFULL (RO) - * - * Receive FIFO Full flag - */ -#define SPI_STATUS_RXFULL_MASK (0x8000U) -#define SPI_STATUS_RXFULL_SHIFT (15U) -#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) - -/* - * RXEMPTY (RO) - * - * Receive FIFO Empty flag - */ -#define SPI_STATUS_RXEMPTY_MASK (0x4000U) -#define SPI_STATUS_RXEMPTY_SHIFT (14U) -#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) - -/* - * RXNUM_5_0 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) -#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) -#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) - -/* - * SPIACTIVE (RO) - * - * SPI register programming is in progress. - * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. - * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. - * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. - * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - */ -#define SPI_STATUS_SPIACTIVE_MASK (0x1U) -#define SPI_STATUS_SPIACTIVE_SHIFT (0U) -#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) - -/* Bitfield definition for register: INTREN */ -/* - * SLVCMDEN (RW) - * - * Enable the Slave Command Interrupt. - * Control whether interrupts are triggered whenever slave commands are received. - * (Slave mode only) - */ -#define SPI_INTREN_SLVCMDEN_MASK (0x20U) -#define SPI_INTREN_SLVCMDEN_SHIFT (5U) -#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) -#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) - -/* - * ENDINTEN (RW) - * - * Enable the End of SPI Transfer interrupt. - * Control whether interrupts are triggered when SPI transfers end. - * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - */ -#define SPI_INTREN_ENDINTEN_MASK (0x10U) -#define SPI_INTREN_ENDINTEN_SHIFT (4U) -#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) -#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) - -/* - * TXFIFOINTEN (RW) - * - * Enable the SPI Transmit FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - */ -#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) -#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) -#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) -#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) - -/* - * RXFIFOINTEN (RW) - * - * Enable the SPI Receive FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - */ -#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) -#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) -#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) -#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) - -/* - * TXFIFOURINTEN (RW) - * - * Enable the SPI Transmit FIFO Underrun interrupt. - * Control whether interrupts are triggered when the Transmit FIFO run out of data. - * (Slave mode only) - */ -#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) -#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) -#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) -#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) - -/* - * RXFIFOORINTEN (RW) - * - * Enable the SPI Receive FIFO Overrun interrupt. - * Control whether interrupts are triggered when the Receive FIFO overflows. - * (Slave mode only) - */ -#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) -#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) -#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) -#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) - -/* Bitfield definition for register: INTRST */ -/* - * SLVCMDINT (W1C) - * - * Slave Command Interrupt. - * This bit is set when Slave Command interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_SLVCMDINT_MASK (0x20U) -#define SPI_INTRST_SLVCMDINT_SHIFT (5U) -#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) -#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) - -/* - * ENDINT (W1C) - * - * End of SPI Transfer interrupt. - * This bit is set when End of SPI Transfer interrupts occur. - */ -#define SPI_INTRST_ENDINT_MASK (0x10U) -#define SPI_INTRST_ENDINT_SHIFT (4U) -#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) -#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) - -/* - * TXFIFOINT (W1C) - * - * TX FIFO Threshold interrupt. - * This bit is set when TX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_TXFIFOINT_MASK (0x8U) -#define SPI_INTRST_TXFIFOINT_SHIFT (3U) -#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) -#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) - -/* - * RXFIFOINT (W1C) - * - * RX FIFO Threshold interrupt. - * This bit is set when RX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_RXFIFOINT_MASK (0x4U) -#define SPI_INTRST_RXFIFOINT_SHIFT (2U) -#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) -#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) - -/* - * TXFIFOURINT (W1C) - * - * TX FIFO Underrun interrupt. - * This bit is set when TX FIFO Underrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) -#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) -#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) -#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) - -/* - * RXFIFOORINT (W1C) - * - * RX FIFO Overrun interrupt. - * This bit is set when RX FIFO Overrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) -#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) -#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) -#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) - -/* Bitfield definition for register: TIMING */ -/* - * CS2SCLK (RW) - * - * The minimum time between the edges of SPI CS and the edges of SCLK. - * SCLK_period * (CS2SCLK + 1) / 2 - */ -#define SPI_TIMING_CS2SCLK_MASK (0x3000U) -#define SPI_TIMING_CS2SCLK_SHIFT (12U) -#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) -#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) - -/* - * CSHT (RW) - * - * The minimum time that SPI CS should stay HIGH. - * SCLK_period * (CSHT + 1) / 2 - */ -#define SPI_TIMING_CSHT_MASK (0xF00U) -#define SPI_TIMING_CSHT_SHIFT (8U) -#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) -#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) - -/* - * SCLK_DIV (RW) - * - * The clock frequency ratio between the clock source and SPI interface SCLK. - * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) - * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - */ -#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) -#define SPI_TIMING_SCLK_DIV_SHIFT (0U) -#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) -#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) - -/* Bitfield definition for register: SLVST */ -/* - * UNDERRUN (W1C) - * - * Data underrun occurs in the last transaction - */ -#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) -#define SPI_SLVST_UNDERRUN_SHIFT (18U) -#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) -#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) - -/* - * OVERRUN (RW) - * - * Data overrun occurs in the last transaction - */ -#define SPI_SLVST_OVERRUN_MASK (0x20000UL) -#define SPI_SLVST_OVERRUN_SHIFT (17U) -#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) -#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) - -/* - * READY (RW) - * - * Set this bit to indicate that the ATCSPI200 is ready for data transaction. - * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - */ -#define SPI_SLVST_READY_MASK (0x10000UL) -#define SPI_SLVST_READY_SHIFT (16U) -#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) -#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) - -/* - * USR_STATUS (RW) - * - * User defined status flags - */ -#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) -#define SPI_SLVST_USR_STATUS_SHIFT (0U) -#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) -#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) - -/* Bitfield definition for register: SLVDATACNT */ -/* - * WCNT (RO) - * - * Slave transmitted data count - */ -#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) -#define SPI_SLVDATACNT_WCNT_SHIFT (16U) -#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) - -/* - * RCNT (RO) - * - * Slave received data count - */ -#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) -#define SPI_SLVDATACNT_RCNT_SHIFT (0U) -#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * SLAVE (RO) - * - * Support for SPI Slave mode - */ -#define SPI_CONFIG_SLAVE_MASK (0x4000U) -#define SPI_CONFIG_SLAVE_SHIFT (14U) -#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) - -/* - * QUADSPI (RO) - * - * Support for Quad I/O SPI - */ -#define SPI_CONFIG_QUADSPI_MASK (0x200U) -#define SPI_CONFIG_QUADSPI_SHIFT (9U) -#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) - -/* - * DUALSPI (RO) - * - * Support for Dual I/O SPI - */ -#define SPI_CONFIG_DUALSPI_MASK (0x100U) -#define SPI_CONFIG_DUALSPI_SHIFT (8U) -#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) - -/* - * TXFIFOSIZE (RO) - * - * Depth of TX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) -#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) -#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) - -/* - * RXFIFOSIZE (RO) - * - * Depth of RX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) -#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) -#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) - - - - -#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_synt_regs.h deleted file mode 100644 index 6e88bde3e4e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_synt_regs.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYNT_H -#define HPM_SYNT_H - -typedef struct { - __RW uint32_t GCR; /* 0x0: Global control register */ - __RW uint32_t RLD; /* 0x4: Counter reload register */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ - __R uint32_t CNT; /* 0xC: Counter */ - __R uint8_t RESERVED1[16]; /* 0x10 - 0x1F: Reserved */ - __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ -} SYNT_Type; - - -/* Bitfield definition for register: GCR */ -/* - * CRST (RW) - * - * 1- Reset counter - */ -#define SYNT_GCR_CRST_MASK (0x2U) -#define SYNT_GCR_CRST_SHIFT (1U) -#define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK) -#define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT) - -/* - * CEN (RW) - * - * 1- Enable counter - */ -#define SYNT_GCR_CEN_MASK (0x1U) -#define SYNT_GCR_CEN_SHIFT (0U) -#define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK) -#define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * RLD (RW) - * - * counter reload value - */ -#define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL) -#define SYNT_RLD_RLD_SHIFT (0U) -#define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) -#define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * CNT (RO) - * - * counter - */ -#define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL) -#define SYNT_CNT_CNT_SHIFT (0U) -#define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CMP */ -/* - * CMP (RW) - * - * comparator value, the output will assert when counter count to this value - */ -#define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL) -#define SYNT_CMP_CMP_SHIFT (0U) -#define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK) -#define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT) - - - -/* CMP register group index macro definition */ -#define SYNT_CMP_0 (0UL) -#define SYNT_CMP_1 (1UL) -#define SYNT_CMP_2 (2UL) -#define SYNT_CMP_3 (3UL) - - -#endif /* HPM_SYNT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sysctl_regs.h deleted file mode 100644 index d464016ad01..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_sysctl_regs.h +++ /dev/null @@ -1,1324 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYSCTL_H -#define HPM_SYSCTL_H - -typedef struct { - __RW uint32_t RESOURCE[318]; /* 0x0 - 0x4F4: Resource control register for cpu0_core */ - __R uint8_t RESERVED0[776]; /* 0x4F8 - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: Group setting */ - __RW uint32_t SET; /* 0x804: Group setting */ - __RW uint32_t CLEAR; /* 0x808: Group setting */ - __RW uint32_t TOGGLE; /* 0x80C: Group setting */ - } GROUP0[2]; - __R uint8_t RESERVED1[224]; /* 0x820 - 0x8FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ - __RW uint32_t SET; /* 0x904: Affiliate of Group */ - __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ - __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ - } AFFILIATE[1]; - __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x920: Retention Control */ - __RW uint32_t SET; /* 0x924: Retention Control */ - __RW uint32_t CLEAR; /* 0x928: Retention Control */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ - } RETENTION[1]; - __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ - struct { - __RW uint32_t STATUS; /* 0x1000: Power Setting */ - __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ - __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ - __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ - } POWER[1]; - __R uint8_t RESERVED4[1008]; /* 0x1010 - 0x13FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ - __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ - __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ - __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ - } RESET[2]; - __R uint8_t RESERVED5[992]; /* 0x1420 - 0x17FF: Reserved */ - __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */ - __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */ - __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */ - __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */ - __RW uint32_t DACCLK[1]; /* 0x1C0C: Clock setting */ - __RW uint32_t I2SCLK[2]; /* 0x1C10 - 0x1C14: Clock setting */ - __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */ - __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ - __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ - __R uint32_t CURRENT; /* 0x2404: Clock measure result */ - __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ - __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ - __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ - } MONITOR[4]; - __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ - struct { - __RW uint32_t LP; /* 0x2800: CPU0 LP control */ - __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ - __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ - __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ - __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ - __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ - __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ - } CPU[1]; -} SYSCTL_Type; - - -/* Bitfield definition for register array: RESOURCE */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any nodes - * 1: any of nodes is changing status - */ -#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) -#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: no change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) -#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) - -/* - * MODE (RW) - * - * resource work mode - * 0:auto turn on and off as system required(recommended) - * 1:always on - * 2:always off - * 3:reserved - */ -#define SYSCTL_RESOURCE_MODE_MASK (0x3U) -#define SYSCTL_RESOURCE_MODE_SHIFT (0U) -#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) -#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) -#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) -#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) -#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: VALUE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * bit0: cpu0 depends on group0 - * bit1: cpu0 depends on group1 - * bit2: cpu0 depends on group2 - * bit3: cpu0 depends on group3 - */ -#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) -#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: SET */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0，each bit represents a group - * 0: no effect - * 1: the group is assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) -#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: the group is not assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) -#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: toggle the result that whether the group is assigned to CPU0 before - */ -#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: VALUE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * bit00: soc_mem is kept on while cpu stop, - * bit01: soc_ctx is kept on while cpu stop, - * bit02: cpu0_mem is kept on while cpu stop, - * bit03: cpu0_ctx is kept on while cpu stop, - * bit04: xtal_hold is kept on while cpu stop, - * bit05: pll0_hold is kept on while cpu stop, - * bit06: pll1_hold is kept on while cpu stop, - * bit07: pll2_hold is kept on while cpu stop, - */ -#define SYSCTL_RETENTION_VALUE_LINK_MASK (0xFFU) -#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) -#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: SET */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: keep - */ -#define SYSCTL_RETENTION_SET_LINK_MASK (0xFFU) -#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) -#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: CLEAR */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: no keep - */ -#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0xFFU) -#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) -#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: TOGGLE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: toggle the result that whether the resource is kept on while CPU0 stop before - */ -#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0xFFU) -#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) -#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array POWER: STATUS */ -/* - * FLAG (RW) - * - * flag represents power cycle happened from last clear of this bit - * 0: power domain did not edurance power cycle since last clear of this bit - * 1: power domain enduranced power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) -#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) -#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) -#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup power cycle happened from last clear of this bit - * 0: power domain did not edurance wakeup power cycle since last clear of this bit - * 1: power domain enduranced wakeup power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) - -/* - * LF_DISABLE (RO) - * - * low fanout power switch disable - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) - -/* - * LF_ACK (RO) - * - * low fanout power switch feedback - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) -#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) -#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) - -/* Bitfield definition for register of struct array POWER: LF_WAIT */ -/* - * WAIT (RW) - * - * wait time for low fan out power switch turn on, default value is 255 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: OFF_WAIT */ -/* - * WAIT (RW) - * - * wait time for power switch turn off, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONTROL */ -/* - * FLAG (RW) - * - * flag represents reset happened from last clear of this bit - * 0: domain did not edurance reset cycle since last clear of this bit - * 1: domain enduranced reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) -#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup reset happened from last clear of this bit - * 0: domain did not edurance wakeup reset cycle since last clear of this bit - * 1: domain enduranced wakeup reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) - -/* - * HOLD (RW) - * - * perform reset and hold in reset, until ths bit cleared by software - * 0: reset is released for function - * 1: reset is assert and hold - */ -#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) -#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) -#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) -#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) - -/* - * RESET (RW) - * - * perform reset and release imediately - * 0: reset is released - * 1 reset is asserted and will release automatically - */ -#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) -#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) -#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) -#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONFIG */ -/* - * PRE_WAIT (RW) - * - * wait cycle numbers before assert reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) - -/* - * RSTCLK_NUM (RW) - * - * reset clock number(must be even number) - * 0: 0 cycle - * 1: 0 cycles - * 2: 2 cycles - * 3: 2 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) - -/* - * POST_WAIT (RW) - * - * time guard band for reset release - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: COUNTER */ -/* - * COUNTER (RW) - * - * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) -#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) -#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) -#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) - -/* Bitfield definition for register array: CLOCK_CPU */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) -#define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) - -/* - * SUB1_DIV (RW) - * - * ahb bus divider, the bus clock is generated by cpu_clock/div - * 0: divider by 1 - * 1: divider by 2 - * … - */ -#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL) -#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U) -#define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) -#define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) - -/* - * SUB0_DIV (RW) - * - * axi bus divider, the bus clock is generated by cpu_clock/div - * 0: divider by 1 - * 1: divider by 2 - * … - */ -#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) -#define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll0_clk2 - * 4:pll1_clk0 - * 5:pll1_clk1 - * 6:pll2_clk0 - * 7:pll2_clk1 - */ -#define SYSCTL_CLOCK_CPU_MUX_MASK (0xF00U) -#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK) -#define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK) -#define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT) - -/* Bitfield definition for register array: CLOCK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) -#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll0_clk2 - * 4:pll1_clk0 - * 5:pll1_clk1 - * 6:pll2_clk0 - * 7:pll2_clk1 - */ -#define SYSCTL_CLOCK_MUX_MASK (0xF00U) -#define SYSCTL_CLOCK_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) -#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) -#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) - -/* Bitfield definition for register array: ADCCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) -#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ana clock N - * 1: ahb clock - */ -#define SYSCTL_ADCCLK_MUX_MASK (0x100U) -#define SYSCTL_ADCCLK_MUX_SHIFT (8U) -#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) -#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) - -/* Bitfield definition for register array: DACCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_DACCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK) -#define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ana clock N - * 1: ahb clock - */ -#define SYSCTL_DACCLK_MUX_MASK (0x100U) -#define SYSCTL_DACCLK_MUX_SHIFT (8U) -#define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK) -#define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT) - -/* Bitfield definition for register array: I2SCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK) -#define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: aud clock 0 - * 1: aud clock 0 for others , aud clock 1 for i2s0 - */ -#define SYSCTL_I2SCLK_MUX_MASK (0x100U) -#define SYSCTL_I2SCLK_MUX_SHIFT (8U) -#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) -#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) - -/* Bitfield definition for register: GLOBAL00 */ -/* - * MUX (RW) - * - * global clock override request - * bit0: override to preset0 - * bit1: override to preset1 - * bit2: override to preset2 - * bit3: override to preset3 - */ -#define SYSCTL_GLOBAL00_MUX_MASK (0xFU) -#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) -#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) -#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * VALID (RW) - * - * result is ready for read - * 0: not ready - * 1: result is ready - */ -#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) -#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) -#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) -#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) - -/* - * DIV_BUSY (RO) - * - * divider is applying new setting - */ -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) - -/* - * OUTEN (RW) - * - * enable clock output - */ -#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) -#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) - -/* - * DIV (RW) - * - * output divider - */ -#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) -#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) -#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) - -/* - * HIGH (RW) - * - * clock frequency higher than upper limit - */ -#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) -#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock frequency lower than lower limit - */ -#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) -#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) -#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) -#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) - -/* - * START (RW) - * - * start measurement - */ -#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) -#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) -#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) -#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) - -/* - * MODE (RW) - * - * work mode, - * 0: register value will be compared to measurement - * 1: upper and lower value will be recordered in register - */ -#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) -#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) -#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) -#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) - -/* - * ACCURACY (RW) - * - * measurement accuracy, - * 0: resolution is 1kHz - * 1: resolution is 1Hz - */ -#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) - -/* - * REFERENCE (RW) - * - * reference clock selection, - * 0: 32k - * 1: 24M - */ -#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) - -/* - * SELECTION (RW) - * - * clock measurement selection - */ -#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) -#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CURRENT */ -/* - * FREQUENCY (RO) - * - * self updating measure result - */ -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ -/* - * FREQUENCY (RW) - * - * lower frequency - */ -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ -/* - * FREQUENCY (RW) - * - * upper frequency - */ -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array CPU: LP */ -/* - * WAKE_CNT (RW) - * - * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - */ -#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) -#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) -#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) -#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) - -/* - * HALT (RW) - * - * halt request for CPU0, - * 0: CPU0 will start to execute after reset or receive wakeup request - * 1: CPU0 will not start after reset, or wakeup after WFI - */ -#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) -#define SYSCTL_CPU_LP_HALT_SHIFT (16U) -#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) -#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) - -/* - * WAKE (RO) - * - * CPU0 is waking up - * 0: CPU0 wake up not asserted - * 1: CPU0 wake up asserted - */ -#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) -#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) -#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) - -/* - * EXEC (RO) - * - * CPU0 is executing - * 0: CPU0 is not executing - * 1: CPU0 is executing - */ -#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) -#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) -#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) - -/* - * WAKE_FLAG (RW) - * - * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit - * 0: CPU0 wakeup not happened - * 1: CPU0 wake up happened - */ -#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) -#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) - -/* - * SLEEP_FLAG (RW) - * - * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) -#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) - -/* - * RESET_FLAG (RW) - * - * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit - * 0: CPU0 reset not happened - * 1: CPU0 reset happened - */ -#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) -#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) -#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) -#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) - -/* - * MODE (RW) - * - * Low power mode, system behavior after WFI - * 00: CPU clock stop after WFI - * 01: System enter low power mode after WFI - * 10: Keep running after WFI - * 11: reserved - */ -#define SYSCTL_CPU_LP_MODE_MASK (0x3U) -#define SYSCTL_CPU_LP_MODE_SHIFT (0U) -#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) -#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) - -/* Bitfield definition for register of struct array CPU: LOCK */ -/* - * GPR (RW) - * - * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - */ -#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) -#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) -#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) -#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) - -/* - * LOCK (RW) - * - * Lock bit for CPU_LOCK - */ -#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) -#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) -#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) -#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register of struct array CPU: GPR0 */ -/* - * GPR (RW) - * - * register for software to handle resume, can save resume address or status - */ -#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) -#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) -#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) - -/* Bitfield definition for register of struct array CPU: STATUS0 */ -/* - * STATUS (RO) - * - * IRQ values - */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register of struct array CPU: ENABLE0 */ -/* - * ENABLE (RW) - * - * IRQ wakeup enable - */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) - - - -/* RESOURCE register group index macro definition */ -#define SYSCTL_RESOURCE_CPU0 (0UL) -#define SYSCTL_RESOURCE_CPX0 (1UL) -#define SYSCTL_RESOURCE_POW_CPU0 (21UL) -#define SYSCTL_RESOURCE_RST_SOC (22UL) -#define SYSCTL_RESOURCE_RST_CPU0 (23UL) -#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_FEMC (66UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (69UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (70UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (71UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (72UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT0 (73UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT1 (74UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT2 (75UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT3 (76UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT4 (77UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT5 (78UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT6 (79UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT7 (80UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (81UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (82UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (83UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (84UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (85UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (86UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (87UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (88UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (89UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (90UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTPC (91UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (92UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (93UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (94UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (95UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (96UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (97UL) -#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF0 (100UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF1 (101UL) -#define SYSCTL_RESOURCE_CLK_TOP_NTM0 (102UL) -#define SYSCTL_RESOURCE_CLK_TOP_SDC0 (103UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL) -#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (132UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (133UL) -#define SYSCTL_RESOURCE_AHBP (256UL) -#define SYSCTL_RESOURCE_AXIS (257UL) -#define SYSCTL_RESOURCE_AXIC (258UL) -#define SYSCTL_RESOURCE_FEMC (259UL) -#define SYSCTL_RESOURCE_ROM0 (260UL) -#define SYSCTL_RESOURCE_LMM0 (261UL) -#define SYSCTL_RESOURCE_RAM0 (262UL) -#define SYSCTL_RESOURCE_MCT0 (263UL) -#define SYSCTL_RESOURCE_XPI0 (264UL) -#define SYSCTL_RESOURCE_XPI1 (265UL) -#define SYSCTL_RESOURCE_SDP0 (266UL) -#define SYSCTL_RESOURCE_RNG0 (267UL) -#define SYSCTL_RESOURCE_KMAN (268UL) -#define SYSCTL_RESOURCE_DMA0 (269UL) -#define SYSCTL_RESOURCE_DMA1 (270UL) -#define SYSCTL_RESOURCE_FFA0 (271UL) -#define SYSCTL_RESOURCE_GPIO (272UL) -#define SYSCTL_RESOURCE_MBX0 (273UL) -#define SYSCTL_RESOURCE_WDG0 (274UL) -#define SYSCTL_RESOURCE_WDG1 (275UL) -#define SYSCTL_RESOURCE_TSNS (276UL) -#define SYSCTL_RESOURCE_TMR0 (277UL) -#define SYSCTL_RESOURCE_TMR1 (278UL) -#define SYSCTL_RESOURCE_TMR2 (279UL) -#define SYSCTL_RESOURCE_TMR3 (280UL) -#define SYSCTL_RESOURCE_URT0 (281UL) -#define SYSCTL_RESOURCE_URT1 (282UL) -#define SYSCTL_RESOURCE_URT2 (283UL) -#define SYSCTL_RESOURCE_URT3 (284UL) -#define SYSCTL_RESOURCE_URT4 (285UL) -#define SYSCTL_RESOURCE_URT5 (286UL) -#define SYSCTL_RESOURCE_URT6 (287UL) -#define SYSCTL_RESOURCE_URT7 (288UL) -#define SYSCTL_RESOURCE_I2C0 (289UL) -#define SYSCTL_RESOURCE_I2C1 (290UL) -#define SYSCTL_RESOURCE_I2C2 (291UL) -#define SYSCTL_RESOURCE_I2C3 (292UL) -#define SYSCTL_RESOURCE_SPI0 (293UL) -#define SYSCTL_RESOURCE_SPI1 (294UL) -#define SYSCTL_RESOURCE_SPI2 (295UL) -#define SYSCTL_RESOURCE_SPI3 (296UL) -#define SYSCTL_RESOURCE_CAN0 (297UL) -#define SYSCTL_RESOURCE_CAN1 (298UL) -#define SYSCTL_RESOURCE_PTPC (299UL) -#define SYSCTL_RESOURCE_ADC0 (300UL) -#define SYSCTL_RESOURCE_ADC1 (301UL) -#define SYSCTL_RESOURCE_ADC2 (302UL) -#define SYSCTL_RESOURCE_DAC0 (303UL) -#define SYSCTL_RESOURCE_ACMP (304UL) -#define SYSCTL_RESOURCE_I2S0 (305UL) -#define SYSCTL_RESOURCE_I2S1 (306UL) -#define SYSCTL_RESOURCE_PDM0 (307UL) -#define SYSCTL_RESOURCE_DAO (308UL) -#define SYSCTL_RESOURCE_SYNT (309UL) -#define SYSCTL_RESOURCE_MOT0 (310UL) -#define SYSCTL_RESOURCE_MOT1 (311UL) -#define SYSCTL_RESOURCE_ETH0 (312UL) -#define SYSCTL_RESOURCE_NTM0 (313UL) -#define SYSCTL_RESOURCE_SDC0 (314UL) -#define SYSCTL_RESOURCE_USB0 (315UL) -#define SYSCTL_RESOURCE_REF0 (316UL) -#define SYSCTL_RESOURCE_REF1 (317UL) - -/* GROUP0 register group index macro definition */ -#define SYSCTL_GROUP0_LINK0 (0UL) -#define SYSCTL_GROUP0_LINK1 (1UL) - -/* AFFILIATE register group index macro definition */ -#define SYSCTL_AFFILIATE_CPU0 (0UL) - -/* RETENTION register group index macro definition */ -#define SYSCTL_RETENTION_CPU0 (0UL) - -/* POWER register group index macro definition */ -#define SYSCTL_POWER_CPU0 (0UL) - -/* RESET register group index macro definition */ -#define SYSCTL_RESET_SOC (0UL) -#define SYSCTL_RESET_CPU0 (1UL) - -/* CLOCK_CPU register group index macro definition */ -#define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL) - -/* CLOCK register group index macro definition */ -#define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_FEMC (1UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI1 (3UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR0 (4UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR1 (5UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR2 (6UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR3 (7UL) -#define SYSCTL_CLOCK_CLK_TOP_URT0 (8UL) -#define SYSCTL_CLOCK_CLK_TOP_URT1 (9UL) -#define SYSCTL_CLOCK_CLK_TOP_URT2 (10UL) -#define SYSCTL_CLOCK_CLK_TOP_URT3 (11UL) -#define SYSCTL_CLOCK_CLK_TOP_URT4 (12UL) -#define SYSCTL_CLOCK_CLK_TOP_URT5 (13UL) -#define SYSCTL_CLOCK_CLK_TOP_URT6 (14UL) -#define SYSCTL_CLOCK_CLK_TOP_URT7 (15UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C0 (16UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C1 (17UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C2 (18UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C3 (19UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI0 (20UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI1 (21UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI2 (22UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI3 (23UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN0 (24UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN1 (25UL) -#define SYSCTL_CLOCK_CLK_TOP_PTPC (26UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA0 (27UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA1 (28UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA2 (29UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA3 (30UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD0 (31UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD1 (32UL) -#define SYSCTL_CLOCK_CLK_TOP_ETH0 (33UL) -#define SYSCTL_CLOCK_CLK_TOP_PTP0 (34UL) -#define SYSCTL_CLOCK_CLK_TOP_REF0 (35UL) -#define SYSCTL_CLOCK_CLK_TOP_REF1 (36UL) -#define SYSCTL_CLOCK_CLK_TOP_NTM0 (37UL) -#define SYSCTL_CLOCK_CLK_TOP_SDC0 (38UL) - -/* ADCCLK register group index macro definition */ -#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) - -/* DACCLK register group index macro definition */ -#define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL) - -/* I2SCLK register group index macro definition */ -#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) - -/* MONITOR register group index macro definition */ -#define SYSCTL_MONITOR_SLICE0 (0UL) -#define SYSCTL_MONITOR_SLICE1 (1UL) -#define SYSCTL_MONITOR_SLICE2 (2UL) -#define SYSCTL_MONITOR_SLICE3 (3UL) - -/* GPR register group index macro definition */ -#define SYSCTL_CPU_GPR_GPR0 (0UL) -#define SYSCTL_CPU_GPR_GPR1 (1UL) -#define SYSCTL_CPU_GPR_GPR2 (2UL) -#define SYSCTL_CPU_GPR_GPR3 (3UL) -#define SYSCTL_CPU_GPR_GPR4 (4UL) -#define SYSCTL_CPU_GPR_GPR5 (5UL) -#define SYSCTL_CPU_GPR_GPR6 (6UL) -#define SYSCTL_CPU_GPR_GPR7 (7UL) -#define SYSCTL_CPU_GPR_GPR8 (8UL) -#define SYSCTL_CPU_GPR_GPR9 (9UL) -#define SYSCTL_CPU_GPR_GPR10 (10UL) -#define SYSCTL_CPU_GPR_GPR11 (11UL) -#define SYSCTL_CPU_GPR_GPR12 (12UL) -#define SYSCTL_CPU_GPR_GPR13 (13UL) - -/* WAKEUP_STATUS register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) - -/* WAKEUP_ENABLE register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) - -/* CPU register group index macro definition */ -#define SYSCTL_CPU_CPU0 (0UL) - - -#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_tamp_regs.h deleted file mode 100644 index 77a04f69e05..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_tamp_regs.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TAMP_H -#define HPM_TAMP_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Tamper n control */ - __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */ - __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - } TAMP[4]; - __R uint8_t RESERVED0[64]; /* 0x40 - 0x7F: Reserved */ - __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */ - __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */ -} TAMP_Type; - - -/* Bitfield definition for register of struct array TAMP: CONTROL */ -/* - * LOCK (RW) - * - * lock tamper setting - * 0: tamper setting can be changed - * 1: tamper setting will last to next battery domain power cycle - */ -#define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL) -#define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U) -#define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK) -#define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT) - -/* - * BYPASS (RW) - * - * bypass tamper violation filter - * 0: filter applied - * 1: filter not used - */ -#define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL) -#define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U) -#define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK) -#define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT) - -/* - * FILTER (RW) - * - * filter length - * 0: 1 cycle - * 1: 2 cycle - * 15: 65526 cycle - */ -#define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL) -#define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U) -#define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK) -#define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT) - -/* - * VALUE (RW) - * - * pin value for passive tamper - */ -#define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U) -#define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U) -#define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK) -#define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT) - -/* - * SPEED (RW) - * - * tamper speed selection, (2^SPEED) changes per second - * 0: 1 shift per second - * 1: 2 shifts per second - * . . . - * 15: 32768 shifts per second - */ -#define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U) -#define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U) -#define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK) -#define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT) - -/* - * RECOVER (RW) - * - * tamper will recover itself if tamper LFSR goes wrong - * 0: tamper will not recover - * 1: tamper will recover - */ -#define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U) -#define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U) -#define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK) -#define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT) - -/* - * ACTIVE (RW) - * - * select active or passive tamper - * 0: passive tamper - * 1: active tamper - */ -#define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U) -#define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U) -#define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK) -#define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable tamper - * 0: tamper disableed - * 1: tamper enabled - */ -#define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U) -#define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U) -#define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK) -#define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array TAMP: POLY */ -/* - * POLY (RW) - * - * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - */ -#define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_POLY_POLY_SHIFT (0U) -#define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK) -#define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array TAMP: LFSR */ -/* - * LFSR (WO) - * - * LFSR for active tamper, write only register, always read 0 - */ -#define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_LFSR_LFSR_SHIFT (0U) -#define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK) -#define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT) - -/* Bitfield definition for register: TAMP_FLAG */ -/* - * FLAG (RW) - * - * tamper flag, each bit represents one tamper pin, write 1 to clear the flag - * Note, clear can only be cleared when tamper disappeared - */ -#define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU) -#define TAMP_TAMP_FLAG_FLAG_SHIFT (0U) -#define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK) -#define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * LOCK (RW) - * - * lock bit for IRQ enable - * 0: enable bits can be changed - * 1: enable bits hold until next battery domain power cycle - */ -#define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL) -#define TAMP_IRQ_EN_LOCK_SHIFT (31U) -#define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK) -#define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable, each bit represents one tamper pin - * 0: interrupt disabled - * 1: interrupt enabled - */ -#define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU) -#define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U) -#define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK) -#define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT) - - - -/* TAMP register group index macro definition */ -#define TAMP_TAMP_TAMP0 (0UL) -#define TAMP_TAMP_TAMP1 (1UL) -#define TAMP_TAMP_TAMP2 (2UL) -#define TAMP_TAMP_TAMP3 (3UL) - - -#endif /* HPM_TAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_trgm_regs.h deleted file mode 100644 index 6f996212bb6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_trgm_regs.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGM_H -#define HPM_TRGM_H - -typedef struct { - __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ - __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ - __RW uint32_t TRGOCFG[64]; /* 0x100 - 0x1FC: Trigger manager output configure register */ - __RW uint32_t DMACFG[4]; /* 0x200 - 0x20C: DMA request configure register */ - __R uint8_t RESERVED1[496]; /* 0x210 - 0x3FF: Reserved */ - __RW uint32_t GCR; /* 0x400: General Control Register */ -} TRGM_Type; - - -/* Bitfield definition for register array: FILTCFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) -#define TRGM_FILTCFG_OUTINV_SHIFT (16U) -#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) -#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stalbe low mode; - * 111-stable high mode - */ -#define TRGM_FILTCFG_MODE_MASK (0xE000U) -#define TRGM_FILTCFG_MODE_SHIFT (13U) -#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) -#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) -#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) -#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) -#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) - -/* - * FILTLEN (RW) - * - * This bitfields defines the filter counter length. - */ -#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) -#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) -#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) -#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) - -/* Bitfield definition for register array: TRGOCFG */ -/* - * OUTINV (RW) - * - * 1- Invert the output - */ -#define TRGM_TRGOCFG_OUTINV_MASK (0x100U) -#define TRGM_TRGOCFG_OUTINV_SHIFT (8U) -#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) -#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) - -/* - * FEDG2PEN (RW) - * - * 1- The selected input signal falling edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x80U) -#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (7U) -#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) -#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) - -/* - * REDG2PEN (RW) - * - * 1- The selected input signal rising edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_REDG2PEN_MASK (0x40U) -#define TRGM_TRGOCFG_REDG2PEN_SHIFT (6U) -#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) -#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) - -/* - * TRIGOSEL (RW) - * - * This bitfield selects one of the TRGM inputs as output. - */ -#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x3FU) -#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) -#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) -#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) - -/* Bitfield definition for register array: DMACFG */ -/* - * DMASRCSEL (RW) - * - * This field selects one of the DMA requests as the DMA request output. - */ -#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) -#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) -#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) -#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * TRGOPEN (RW) - * - * The bitfield enable the TRGM outputs. - */ -#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) -#define TRGM_GCR_TRGOPEN_SHIFT (0U) -#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) -#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) - - - -/* FILTCFG register group index macro definition */ -#define TRGM_FILTCFG_PWM_IN0 (0UL) -#define TRGM_FILTCFG_PWM_IN1 (1UL) -#define TRGM_FILTCFG_PWM_IN2 (2UL) -#define TRGM_FILTCFG_PWM_IN3 (3UL) -#define TRGM_FILTCFG_PWM_IN4 (4UL) -#define TRGM_FILTCFG_PWM_IN5 (5UL) -#define TRGM_FILTCFG_PWM_IN6 (6UL) -#define TRGM_FILTCFG_PWM_IN7 (7UL) -#define TRGM_FILTCFG_TRGM_IN0 (8UL) -#define TRGM_FILTCFG_TRGM_IN1 (9UL) -#define TRGM_FILTCFG_TRGM_IN2 (10UL) -#define TRGM_FILTCFG_TRGM_IN3 (11UL) -#define TRGM_FILTCFG_TRGM_IN4 (12UL) -#define TRGM_FILTCFG_TRGM_IN5 (13UL) -#define TRGM_FILTCFG_TRGM_IN6 (14UL) -#define TRGM_FILTCFG_TRGM_IN7 (15UL) -#define TRGM_FILTCFG_TRGM_IN8 (16UL) -#define TRGM_FILTCFG_TRGM_IN9 (17UL) -#define TRGM_FILTCFG_TRGM_IN10 (18UL) -#define TRGM_FILTCFG_TRGM_IN11 (19UL) - -/* TRGOCFG register group index macro definition */ -#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) -#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) -#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) -#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) -#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) -#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) -#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) -#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) -#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) -#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) -#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) -#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) -#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) -#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) -#define TRGM_TRGOCFG_PWM_SYNCI (14UL) -#define TRGM_TRGOCFG_PWM_FRCI (15UL) -#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) -#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) -#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) -#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) -#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) -#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) -#define TRGM_TRGOCFG_PWM_IN8 (22UL) -#define TRGM_TRGOCFG_PWM_IN9 (23UL) -#define TRGM_TRGOCFG_PWM_IN10 (24UL) -#define TRGM_TRGOCFG_PWM_IN11 (25UL) -#define TRGM_TRGOCFG_PWM_IN12 (26UL) -#define TRGM_TRGOCFG_PWM_IN13 (27UL) -#define TRGM_TRGOCFG_PWM_IN14 (28UL) -#define TRGM_TRGOCFG_PWM_IN15 (29UL) -#define TRGM_TRGOCFG_PWM_IN16 (30UL) -#define TRGM_TRGOCFG_PWM_IN17 (31UL) -#define TRGM_TRGOCFG_PWM_IN18 (32UL) -#define TRGM_TRGOCFG_PWM_IN19 (33UL) -#define TRGM_TRGOCFG_PWM_IN20 (34UL) -#define TRGM_TRGOCFG_PWM_IN21 (35UL) -#define TRGM_TRGOCFG_PWM_IN22 (36UL) -#define TRGM_TRGOCFG_PWM_IN23 (37UL) -#define TRGM_TRGOCFG_QEI_A (38UL) -#define TRGM_TRGOCFG_QEI_B (39UL) -#define TRGM_TRGOCFG_QEI_Z (40UL) -#define TRGM_TRGOCFG_QEI_H (41UL) -#define TRGM_TRGOCFG_QEI_PAUSE (42UL) -#define TRGM_TRGOCFG_QEI_SNAPI (43UL) -#define TRGM_TRGOCFG_HALL_U (44UL) -#define TRGM_TRGOCFG_HALL_V (45UL) -#define TRGM_TRGOCFG_HALL_W (46UL) -#define TRGM_TRGOCFG_HALL_SNAPI (47UL) -#define TRGM_TRGOCFG_ADC0_STRGI (48UL) -#define TRGM_TRGOCFG_ADC1_STRGI (49UL) -#define TRGM_TRGOCFG_ADC2_STRGI (50UL) -#define TRGM_TRGOCFG_ADC3_STRGI (51UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) -#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) -#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) -#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) -#define TRGM_TRGOCFG_GPTMRB_SYNCI (58UL) -#define TRGM_TRGOCFG_GPTMRB_IN2 (59UL) -#define TRGM_TRGOCFG_GPTMRB_IN3 (60UL) -#define TRGM_TRGOCFG_CMPX_WIN (61UL) -#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) -#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) - -/* DMACFG register group index macro definition */ -#define TRGM_DMACFG_0 (0UL) -#define TRGM_DMACFG_1 (1UL) -#define TRGM_DMACFG_2 (2UL) -#define TRGM_DMACFG_3 (3UL) - - -#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_tsns_regs.h deleted file mode 100644 index fcaf224c309..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_tsns_regs.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSNS_H -#define HPM_TSNS_H - -typedef struct { - __R uint32_t T; /* 0x0: Temperature */ - __R uint32_t TMAX; /* 0x4: Maximum Temperature */ - __R uint32_t TMIN; /* 0x8: Minimum Temperature */ - __R uint32_t AGE; /* 0xC: Sample age */ - __RW uint32_t STATUS; /* 0x10: Status */ - __RW uint32_t CONFIG; /* 0x14: Configuration */ - __RW uint32_t VALIDITY; /* 0x18: Sample validity */ - __RW uint32_t FLAG; /* 0x1C: Temperature flag */ - __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ - __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ - __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ - __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ - __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __RW uint32_t ADVAN; /* 0x38: Advance configuration */ -} TSNS_Type; - - -/* Bitfield definition for register: T */ -/* - * T (RO) - * - * Signed number of temperature in 256 x celsius degree - */ -#define TSNS_T_T_MASK (0xFFFFFFFFUL) -#define TSNS_T_T_SHIFT (0U) -#define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) - -/* Bitfield definition for register: TMAX */ -/* - * T (RO) - * - * maximum temperature ever found - */ -#define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMAX_T_SHIFT (0U) -#define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) - -/* Bitfield definition for register: TMIN */ -/* - * T (RO) - * - * minimum temperature ever found - */ -#define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMIN_T_SHIFT (0U) -#define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) - -/* Bitfield definition for register: AGE */ -/* - * AGE (RO) - * - * age of T register in 24MHz clock cycles - */ -#define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) -#define TSNS_AGE_AGE_SHIFT (0U) -#define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * VALID (RO) - * - * indicate value in T is valid or not - * 0: not valid - * 1:valid - */ -#define TSNS_STATUS_VALID_MASK (0x80000000UL) -#define TSNS_STATUS_VALID_SHIFT (31U) -#define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) - -/* - * TRIGGER (W1C) - * - * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - */ -#define TSNS_STATUS_TRIGGER_MASK (0x1U) -#define TSNS_STATUS_TRIGGER_SHIFT (0U) -#define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) -#define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * IRQ_EN (RW) - * - * Enable interrupt - */ -#define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) -#define TSNS_CONFIG_IRQ_EN_SHIFT (31U) -#define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) -#define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) - -/* - * RST_EN (RW) - * - * Enable reset - */ -#define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) -#define TSNS_CONFIG_RST_EN_SHIFT (30U) -#define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) -#define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) - -/* - * COMPARE_MIN_EN (RW) - * - * Enable compare for minimum temperature - */ -#define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) -#define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) -#define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) -#define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) - -/* - * COMPARE_MAX_EN (RW) - * - * Enable compare for maximum temperature - */ -#define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) -#define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) -#define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) -#define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) - -/* - * SPEED (RW) - * - * cycles of a progressive step in 24M clock, valid from 24-255, default 96 - * 24: 24 cycle for a step - * 25: 25 cycle for a step - * 26: 26 cycle for a step - * ... - * 255: 255 cycle for a step - */ -#define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) -#define TSNS_CONFIG_SPEED_SHIFT (16U) -#define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) -#define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) - -/* - * AVERAGE (RW) - * - * Average time, default in 3 - * 0: measure and return - * 1: twice and average - * 2: 4 times and average - * . . . - * 7: 128 times and average - */ -#define TSNS_CONFIG_AVERAGE_MASK (0x700U) -#define TSNS_CONFIG_AVERAGE_SHIFT (8U) -#define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) -#define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) - -/* - * CONTINUOUS (RW) - * - * continuous mode that keep sampling temperature peridically - * 0: trigger mode - * 1: continuous mode - */ -#define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) -#define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) -#define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) -#define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) - -/* - * ASYNC (RW) - * - * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value - * 0: active mode - * 1: Async mode - */ -#define TSNS_CONFIG_ASYNC_MASK (0x2U) -#define TSNS_CONFIG_ASYNC_SHIFT (1U) -#define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) -#define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) - -/* - * ENABLE (RW) - * - * Enable temperature - * 0: disable, temperature sensor is shut down - * 1: enable. Temperature sensor enabled - */ -#define TSNS_CONFIG_ENABLE_MASK (0x1U) -#define TSNS_CONFIG_ENABLE_SHIFT (0U) -#define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) -#define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) - -/* Bitfield definition for register: VALIDITY */ -/* - * VALIDITY (RW) - * - * time for temperature values to expire in 24M clock cycles - */ -#define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) -#define TSNS_VALIDITY_VALIDITY_SHIFT (0U) -#define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) -#define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) - -/* Bitfield definition for register: FLAG */ -/* - * RECORD_MIN_CLR (RW) - * - * Clear minimum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) -#define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) -#define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) -#define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) - -/* - * RECORD_MAX_CLR (RW) - * - * Clear maximum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) -#define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) -#define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) -#define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) - -/* - * UNDER_TEMP (RW) - * - * Clear under temperature status, write 1 to clear - */ -#define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) -#define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) -#define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) -#define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) - -/* - * OVER_TEMP (RW) - * - * Clear over temperature status, write 1 to clear - */ -#define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) -#define TSNS_FLAG_OVER_TEMP_SHIFT (16U) -#define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) -#define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) - -/* - * IRQ (RW) - * - * IRQ flag, write 1 to clear - */ -#define TSNS_FLAG_IRQ_MASK (0x1U) -#define TSNS_FLAG_IRQ_SHIFT (0U) -#define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) -#define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_IRQ */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) -#define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_IRQ */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) -#define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_RST */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_RST_T_SHIFT (0U) -#define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) -#define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_RST */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_RST_T_SHIFT (0U) -#define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) -#define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: ASYNC */ -/* - * ASYNC_TYPE (RW) - * - * Compare hotter than or colder than in asynchoronous mode - * 0: hotter than - * 1: colder than - */ -#define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) -#define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) -#define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) -#define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) - -/* - * POLARITY (RW) - * - * Polarity of internal comparator - */ -#define TSNS_ASYNC_POLARITY_MASK (0x10000UL) -#define TSNS_ASYNC_POLARITY_SHIFT (16U) -#define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) -#define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) - -/* - * VALUE (RW) - * - * Value of async mode to compare - */ -#define TSNS_ASYNC_VALUE_MASK (0x7FFU) -#define TSNS_ASYNC_VALUE_SHIFT (0U) -#define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) -#define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) - -/* Bitfield definition for register: ADVAN */ -/* - * ASYNC_IRQ (RO) - * - * interrupt status of asynchronous mode - */ -#define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) -#define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) -#define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) - -/* - * ACTIVE_IRQ (RO) - * - * interrupt status of active mode - */ -#define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) -#define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) -#define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) - -/* - * SAMPLING (RO) - * - * temperature sampling is working - */ -#define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) -#define TSNS_ADVAN_SAMPLING_SHIFT (16U) -#define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) - -/* - * NEG_ONLY (RW) - * - * use negative compare polarity only - */ -#define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) -#define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) -#define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) -#define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) - -/* - * POS_ONLY (RW) - * - * use positive compare polarity only - */ -#define TSNS_ADVAN_POS_ONLY_MASK (0x1U) -#define TSNS_ADVAN_POS_ONLY_SHIFT (0U) -#define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) -#define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) - - - - -#endif /* HPM_TSNS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_uart_regs.h deleted file mode 100644 index 86d725ce3b3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_uart_regs.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_UART_H -#define HPM_UART_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ - union { - __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ - __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ - __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ - __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ - }; - union { - __R uint32_t IIR; /* 0x28: Interrupt Identification Register */ - __W uint32_t FCR; /* 0x28: FIFO Control Register */ - }; - __RW uint32_t LCR; /* 0x2C: Line Control Register */ - __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ - __R uint32_t LSR; /* 0x34: Line Status Register */ - __R uint32_t MSR; /* 0x38: Modem Status Register */ - __RW uint32_t GPR; /* 0x3C: GPR Register */ -} UART_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * The depth of RXFIFO and TXFIFO - * 0: 16-byte FIFO - * 1: 32-byte FIFO - * 2: 64-byte FIFO - * 3: 128-byte FIFO - */ -#define UART_CFG_FIFOSIZE_MASK (0x3U) -#define UART_CFG_FIFOSIZE_SHIFT (0U) -#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: OSCR */ -/* - * OSC (RW) - * - * Over-sample control - * The value must be an even number; any odd value - * writes to this field will be converted to an even value. - * OSC=0: reserved - * OSC<=8: The over-sample ratio is 8 - * 8 < OSC< 32: The over sample ratio is OSC - */ -#define UART_OSCR_OSC_MASK (0x1FU) -#define UART_OSCR_OSC_SHIFT (0U) -#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) -#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RBR (RO) - * - * Receive data read port - */ -#define UART_RBR_RBR_MASK (0xFFU) -#define UART_RBR_RBR_SHIFT (0U) -#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) - -/* Bitfield definition for register: THR */ -/* - * THR (WO) - * - * Transmit data write port - */ -#define UART_THR_THR_MASK (0xFFU) -#define UART_THR_THR_SHIFT (0U) -#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) -#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) - -/* Bitfield definition for register: DLL */ -/* - * DLL (RW) - * - * Least significant byte of the Divisor Latch - */ -#define UART_DLL_DLL_MASK (0xFFU) -#define UART_DLL_DLL_SHIFT (0U) -#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) -#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) - -/* Bitfield definition for register: IER */ -/* - * EMSI (RW) - * - * Enable modem status interrupt - * The interrupt asserts when the status of one of the - * following occurs: - * The status of modem_rin, modem_dcdn, - * modem_dsrn or modem_ctsn (If the auto-cts mode is - * disabled) has been changed. - * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), - * modem_ctsn would be used to control the transmitter. - */ -#define UART_IER_EMSI_MASK (0x8U) -#define UART_IER_EMSI_SHIFT (3U) -#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) -#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) - -/* - * ELSI (RW) - * - * Enable receiver line status interrupt - */ -#define UART_IER_ELSI_MASK (0x4U) -#define UART_IER_ELSI_SHIFT (2U) -#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) -#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) - -/* - * ETHEI (RW) - * - * Enable transmitter holding register interrupt - */ -#define UART_IER_ETHEI_MASK (0x2U) -#define UART_IER_ETHEI_SHIFT (1U) -#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) -#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) - -/* - * ERBI (RW) - * - * Enable received data available interrupt and the - * character timeout interrupt - * 0: Disable - * 1: Enable - */ -#define UART_IER_ERBI_MASK (0x1U) -#define UART_IER_ERBI_SHIFT (0U) -#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) -#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) - -/* Bitfield definition for register: DLM */ -/* - * DLM (RW) - * - * Most significant byte of the Divisor Latch - */ -#define UART_DLM_DLM_MASK (0xFFU) -#define UART_DLM_DLM_SHIFT (0U) -#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) -#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) - -/* Bitfield definition for register: IIR */ -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR_FIFOED_MASK (0xC0U) -#define UART_IIR_FIFOED_SHIFT (6U) -#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR_INTRID_MASK (0xFU) -#define UART_IIR_INTRID_SHIFT (0U) -#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) - -/* Bitfield definition for register: FCR */ -/* - * RFIFOT (WO) - * - * Receiver FIFO trigger level - */ -#define UART_FCR_RFIFOT_MASK (0xC0U) -#define UART_FCR_RFIFOT_SHIFT (6U) -#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) -#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) - -/* - * TFIFOT (WO) - * - * Transmitter FIFO trigger level - */ -#define UART_FCR_TFIFOT_MASK (0x30U) -#define UART_FCR_TFIFOT_SHIFT (4U) -#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) -#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) - -/* - * DMAE (WO) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCR_DMAE_MASK (0x8U) -#define UART_FCR_DMAE_SHIFT (3U) -#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) -#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_TFIFORST_MASK (0x4U) -#define UART_FCR_TFIFORST_SHIFT (2U) -#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) -#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_RFIFORST_MASK (0x2U) -#define UART_FCR_RFIFORST_SHIFT (1U) -#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) -#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) - -/* - * FIFOE (WO) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCR_FIFOE_MASK (0x1U) -#define UART_FCR_FIFOE_SHIFT (0U) -#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) -#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) - -/* Bitfield definition for register: LCR */ -/* - * DLAB (RW) - * - * Divisor latch access bit - */ -#define UART_LCR_DLAB_MASK (0x80U) -#define UART_LCR_DLAB_SHIFT (7U) -#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) -#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) - -/* - * BC (RW) - * - * Break control - */ -#define UART_LCR_BC_MASK (0x40U) -#define UART_LCR_BC_SHIFT (6U) -#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) -#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) - -/* - * SPS (RW) - * - * Stick parity - * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). - * 0: Disable the sticky bit parity. - */ -#define UART_LCR_SPS_MASK (0x20U) -#define UART_LCR_SPS_SHIFT (5U) -#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) -#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) - -/* - * EPS (RW) - * - * Even parity select - * 1: Even parity (an even number of logic-1 is in the data - * and parity bits) - * 0: Old parity. - */ -#define UART_LCR_EPS_MASK (0x10U) -#define UART_LCR_EPS_SHIFT (4U) -#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) -#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) - -/* - * PEN (RW) - * - * Parity enable - * When this bit is set, a parity bit is generated in - * transmitted data before the first STOP bit and the parity - * bit would be checked for the received data. - */ -#define UART_LCR_PEN_MASK (0x8U) -#define UART_LCR_PEN_SHIFT (3U) -#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) -#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) - -/* - * STB (RW) - * - * Number of STOP bits - * 0: 1 bits - * 1: The number of STOP bit is based on the WLS setting - * When WLS = 0, STOP bit is 1.5 bits - * When WLS = 1, 2, 3, STOP bit is 2 bits - */ -#define UART_LCR_STB_MASK (0x4U) -#define UART_LCR_STB_SHIFT (2U) -#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) -#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) - -/* - * WLS (RW) - * - * Word length setting - * 0: 5 bits - * 1: 6 bits - * 2: 7 bits - * 3: 8 bits - */ -#define UART_LCR_WLS_MASK (0x3U) -#define UART_LCR_WLS_SHIFT (0U) -#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) -#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) - -/* Bitfield definition for register: MCR */ -/* - * AFE (RW) - * - * Auto flow control enable - * 0: Disable - * 1: The auto-CTS and auto-RTS setting is based on the - * RTS bit setting: - * When RTS = 0, auto-CTS only - * When RTS = 1, auto-CTS and auto-RTS - */ -#define UART_MCR_AFE_MASK (0x20U) -#define UART_MCR_AFE_SHIFT (5U) -#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) -#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) - -/* - * LOOP (RW) - * - * Enable loopback mode - * 0: Disable - * 1: Enable - */ -#define UART_MCR_LOOP_MASK (0x10U) -#define UART_MCR_LOOP_SHIFT (4U) -#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) -#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) - -/* - * RTS (RW) - * - * Request to send - * This bit controls the modem_rtsn output. - * 0: The modem_rtsn output signal will be driven HIGH - * 1: The modem_rtsn output signal will be driven LOW - */ -#define UART_MCR_RTS_MASK (0x2U) -#define UART_MCR_RTS_SHIFT (1U) -#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) -#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) - -/* Bitfield definition for register: LSR */ -/* - * ERRF (RO) - * - * Error in RXFIFO - * In the FIFO mode, this bit is set when there is at least - * one parity error, framing error, or line break - * associated with data in the RXFIFO. It is cleared when - * this register is read and there is no more error for the - * rest of data in the RXFIFO. - */ -#define UART_LSR_ERRF_MASK (0x80U) -#define UART_LSR_ERRF_SHIFT (7U) -#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) - -/* - * TEMT (RO) - * - * Transmitter empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) and the Transmitter Shift Register (TSR) are - * both empty. Otherwise, it is zero. - */ -#define UART_LSR_TEMT_MASK (0x40U) -#define UART_LSR_TEMT_SHIFT (6U) -#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) - -/* - * THRE (RO) - * - * Transmitter Holding Register empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) is empty. Otherwise, it is zero. - * If the THRE interrupt is enabled, an interrupt is - * triggered when THRE becomes 1. - */ -#define UART_LSR_THRE_MASK (0x20U) -#define UART_LSR_THRE_SHIFT (5U) -#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) - -/* - * LBREAK (RO) - * - * Line break - * This bit is set when the uart_sin input signal was held - * LOWfor longer than the time for a full-word - * transmission. A full-word transmission is the - * transmission of the START, data, parity, and STOP - * bits. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the line break for - * the received data at the top of the RXFIFO. - */ -#define UART_LSR_LBREAK_MASK (0x10U) -#define UART_LSR_LBREAK_SHIFT (4U) -#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) - -/* - * FE (RO) - * - * Framing error - * This bit is set when the received STOP bit is not - * HIGH. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the framing error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_FE_MASK (0x8U) -#define UART_LSR_FE_SHIFT (3U) -#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) - -/* - * PE (RO) - * - * Parity error - * This bit is set when the received parity does not match - * with the parity selected in the LCR[5:4]. It is cleared - * when this register is read. - * In the FIFO mode, this bit indicates the parity error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_PE_MASK (0x4U) -#define UART_LSR_PE_SHIFT (2U) -#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) - -/* - * OE (RO) - * - * Overrun error - * This bit indicates that data in the Receiver Buffer - * Register (RBR) is overrun. - */ -#define UART_LSR_OE_MASK (0x2U) -#define UART_LSR_OE_SHIFT (1U) -#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) - -/* - * DR (RO) - * - * Data ready. - * This bit is set when there are incoming received data - * in the Receiver Buffer Register (RBR). It is cleared - * when all of the received data are read. - */ -#define UART_LSR_DR_MASK (0x1U) -#define UART_LSR_DR_SHIFT (0U) -#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) - -/* Bitfield definition for register: MSR */ -/* - * CTS (RO) - * - * Clear to send - * 0: The modem_ctsn input signal is HIGH. - * 1: The modem_ctsn input signal is LOW. - */ -#define UART_MSR_CTS_MASK (0x10U) -#define UART_MSR_CTS_SHIFT (4U) -#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) - -/* - * DCTS (RC) - * - * Delta clear to send - * This bit is set when the state of the modem_ctsn input - * signal has been changed since the last time this - * register is read. - */ -#define UART_MSR_DCTS_MASK (0x1U) -#define UART_MSR_DCTS_SHIFT (0U) -#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) - -/* Bitfield definition for register: GPR */ -/* - * DATA (RW) - * - * A one-byte storage register - */ -#define UART_GPR_DATA_MASK (0xFFU) -#define UART_GPR_DATA_SHIFT (0U) -#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) -#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) - - - - -#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_usb_regs.h deleted file mode 100644 index ff2a137f826..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_usb_regs.h +++ /dev/null @@ -1,2253 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_USB_H -#define HPM_USB_H - -typedef struct { - __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ - __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ - __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ - __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ - __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ - __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ - __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ - __RW uint32_t USBCMD; /* 0x140: USB Command Register */ - __RW uint32_t USBSTS; /* 0x144: USB Status Register */ - __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ - __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ - __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ - union { - __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ - __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ - }; - union { - __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ - __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ - }; - __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ - __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ - __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ - __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ - __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ - __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ - __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ - __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ - __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ - __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ - __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ - __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ - __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ - __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ - __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ - __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ - __R uint8_t RESERVED7[32]; /* 0x1E0 - 0x1FF: Reserved */ - __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED8[12]; /* 0x204 - 0x20F: Reserved */ - __RW uint32_t PHY_CTRL0; /* 0x210: */ - __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED9[8]; /* 0x218 - 0x21F: Reserved */ - __RW uint32_t TOP_STATUS; /* 0x220: */ - __RW uint32_t PHY_STATUS; /* 0x224: */ -} USB_Type; - - -/* Bitfield definition for register: GPTIMER0LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) -#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER0CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD - */ -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software; - * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the - * counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: GPTIMER1LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) -#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER1CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - */ -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and - * automatically reload the counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: SBUSCFG */ -/* - * AHBBRST (RW) - * - * AHBBRST - * AHB master interface Burst configuration - * These bits control AHB master transfer type sequence (or priority). - * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. - * 000 - Incremental burst of unspecified length only - * 001 - INCR4 burst, then single transfer - * 010 - INCR8 burst, INCR4 burst, then single transfer - * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer - * 100 - Reserved, don't use - * 101 - INCR4 burst, then incremental burst of unspecified length - * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length - * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) -#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) - -/* Bitfield definition for register: USBCMD */ -/* - * ITC (RW) - * - * ITC - * Interrupt Threshold Control -Read/Write. - * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. - * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are - * shown below. - * Value Maximum Interrupt Interval - * 00000000 - Immediate (no threshold) - * 00000001 - 1 micro-frame - * 00000010 - 2 micro-frames - * 00000100 - 4 micro-frames - * 00001000 - 8 micro-frames - * 00010000 - 16 micro-frames - * 00100000 - 32 micro-frames - * 01000000 - 64 micro-frames - */ -#define USB_USBCMD_ITC_MASK (0xFF0000UL) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) -#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) - -/* - * FS_2 (RW) - * - * FS_2 - * Frame List Size - (Read/Write or Read Only). [host mode only] - * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. - * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. - * NOTE: This field is made up from USBCMD bits 15, 3 and 2. - * Value Meaning - * 0b000 - 1024 elements (4096 bytes) Default value - * 0b001 - 512 elements (2048 bytes) - * 0b010 - 256 elements (1024 bytes) - * 0b011 - 128 elements (512 bytes) - * 0b100 - 64 elements (256 bytes) - * 0b101 - 32 elements (128 bytes) - * 0b110 - 16 elements (64 bytes) - * 0b111 - 8 elements (32 bytes) - */ -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) - -/* - * ATDTW (RW) - * - * ATDTW - * Add dTD TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's - * linked list. This bit is set and cleared by software. - * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD - * to a primed endpoint may go unrecognized. - */ -#define USB_USBCMD_ATDTW_MASK (0x4000U) -#define USB_USBCMD_ATDTW_SHIFT (14U) -#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) - -/* - * SUTW (RW) - * - * SUTW - * Setup TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. - * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then - * there is a hazard when new setup data arrives while the DCD is copying the setup data payload - * from the QH for a previous setup packet. This bit is set and cleared by software. - * This bit would also be cleared by hardware when a hazard detected. - */ -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) - -/* - * ASPE (RW) - * - * ASPE - * Asynchronous Schedule Park Mode Enable - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. - * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. - * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - * NOTE: ASPE bit reset value: '0b' for OTG controller . - */ -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) - -/* - * ASP (RW) - * - * ASP - * Asynchronous Schedule Park Mode Count - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. - * It contains a count of the number of successive transactions the host controller is allowed to - * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. - * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. - * This field is set to 3h in all controller core. - */ -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) - -/* - * IAA (RW) - * - * IAA - * Interrupt on Async Advance Doorbell - Read/Write. - * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. - * When the host controller has evicted all appropriate cached schedule states, - * it sets the Interrupt on Async Advance status bit in the USBSTS register. - * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. - * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. - * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. - * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - */ -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) - -/* - * ASE (RW) - * - * ASE - * Asynchronous Schedule Enable - Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Asynchronous Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Asynchronous Schedule. - * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - */ -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) - -/* - * PSE (RW) - * - * PSE - * Periodic Schedule Enable- Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Periodic Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Periodic Schedule - * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - */ -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) - -/* - * FS_1 (RW) - * - * FS_1 - * See description at bit 15 - */ -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) - -/* - * RST (RW) - * - * RST - * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. - * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. - * Host operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. - * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. - * Attempting to reset an actively running host controller will result in undefined behavior. - * Device operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. - * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - */ -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) - -/* - * RS (RW) - * - * RS - * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. - * Host operation mode: - * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. - * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. - * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. - * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). - * Device operation mode: - * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. - * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. - * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) - -/* Bitfield definition for register: USBSTS */ -/* - * TI1 (RWC) - * - * TI1 - * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. - * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this - * bit will clear it. - */ -#define USB_USBSTS_TI1_MASK (0x2000000UL) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) -#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) - -/* - * TI0 (RWC) - * - * TI0 - * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. - * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this - * bit clears it. - */ -#define USB_USBSTS_TI0_MASK (0x1000000UL) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) - -/* - * UPI (RWC) - * - * USB Host Periodic Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. - * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero. - */ -#define USB_USBSTS_UPI_MASK (0x80000UL) -#define USB_USBSTS_UPI_SHIFT (19U) -#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) -#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) - -/* - * UAI (RWC) - * - * USB Host Asynchronous Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. - * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero - */ -#define USB_USBSTS_UAI_MASK (0x40000UL) -#define USB_USBSTS_UAI_SHIFT (18U) -#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) -#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) - -/* - * NAKI (RO) - * - * NAKI - * NAK Interrupt Bit--RO. - * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and - * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware - * when all Enabled TX/RX Endpoint NAK bits are cleared. - */ -#define USB_USBSTS_NAKI_MASK (0x10000UL) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) - -/* - * AS (RO) - * - * AS - * Asynchronous Schedule Status - Read Only. - * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. - * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) - -/* - * PS (RO) - * - * PS - * Periodic Schedule Status - Read Only. - * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. - * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) - -/* - * RCL (RO) - * - * RCL - * Reclamation - Read Only. - * This is a read-only status bit used to detect an empty asynchronous schedule. - * Only used in the host operation mode. - */ -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) - -/* - * HCH (RO) - * - * HCH - * HCHaIted - Read Only. - * This bit is a zero whenever the Run/Stop bit is a one. - * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - * either by software or by the Controller hardware (for example, an internal error). - * Only used in the host operation mode. - * Default value is '0b' for OTG core . - * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE - * register. - * NOTE: HCH bit reset value: '0b' for OTG controller core . - */ -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) - -/* - * SLI (RWC) - * - * SLI - * DCSuspend - R/WC. - * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. - * Only used in device operation mode. - */ -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) - -/* - * SRI (RWC) - * - * SRI - * SOF Received - R/WC. - * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. - * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. - * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. - * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. - * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. - * Software writes a 1 to this bit to clear it. - */ -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) - -/* - * URI (RWC) - * - * URI - * USB Reset Received - R/WC. - * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. - * Software can write a 1 to this bit to clear the USB Reset Received status bit. - * Only used in device operation mode. - */ -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) - -/* - * AAI (RWC) - * - * AAI - * Interrupt on Async Advance - R/WC. - * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule - * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. - * Only used in host operation mode. - */ -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) - -/* - * SEI (RWC) - * - * System Error – RWC. Default = 0b. - * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. - * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - */ -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) - -/* - * FRI (RWC) - * - * FRI - * Frame List Rollover - R/WC. - * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to - * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the - * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the - * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host - * Controller sets this bit to a one every time FHINDEX [12] toggles. - * Only used in host operation mode. - */ -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) - -/* - * PCI (RWC) - * - * PCI - * Port Change Detect - R/WC. - * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, - * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. - * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. - * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, - * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - */ -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) - -/* - * UEI (RWC) - * - * UEI - * USB Error Interrupt (USBERRINT) - R/WC. - * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. - * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - */ -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) - -/* - * UI (RWC) - * - * UI - * USB Interrupt (USBINT) - R/WC. - * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB - * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. - * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when - * the actual number of bytes received was less than the expected number of bytes. - */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) - -/* Bitfield definition for register: USBINTR */ -/* - * TIE1 (RW) - * - * TIE1 - * General Purpose Timer #1 Interrupt Enable - * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE1_MASK (0x2000000UL) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) -#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) - -/* - * TIE0 (RW) - * - * TIE0 - * General Purpose Timer #0 Interrupt Enable - * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE0_MASK (0x1000000UL) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) - -/* - * UPIE (RW) - * - * UPIE - * USB Host Periodic Interrupt Enable - * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UPIE_MASK (0x80000UL) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) - -/* - * UAIE (RW) - * - * UAIE - * USB Host Asynchronous Interrupt Enable - * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UAIE_MASK (0x40000UL) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) - -/* - * NAKE (RO) - * - * NAKE - * NAK Interrupt Enable - * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_NAKE_MASK (0x10000UL) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) - -/* - * SLE (RW) - * - * SLE - * Sleep Interrupt Enable - * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) - -/* - * SRE (RW) - * - * SRE - * SOF Received Interrupt Enable - * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) - -/* - * URE (RW) - * - * URE - * USB Reset Interrupt Enable - * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) - -/* - * AAE (RW) - * - * AAE - * Async Advance Interrupt Enable - * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) - -/* - * SEE (RW) - * - * SEE - * System Error Interrupt Enable - * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) - -/* - * FRE (RW) - * - * FRE - * Frame List Rollover Interrupt Enable - * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) - -/* - * PCE (RW) - * - * PCE - * Port Change Detect Interrupt Enable - * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) - -/* - * UEE (RWC) - * - * UEE - * USB Error Interrupt Enable - * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) - -/* - * UE (RW) - * - * UE - * USB Interrupt Enable - * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) - -/* Bitfield definition for register: FRINDEX */ -/* - * FRINDEX (RW) - * - * FRINDEX - * Frame Index. - * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. - * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. - * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. - * USBCMD [Frame List Size] Number Elements N - * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. - * In either mode bits 2:0 indicate the current microframe. - * The bit field values description below is represented as (Frame List Size) Number Elements N. - * 00000000000000 - (1024) 12 - * 00000000000001 - (512) 11 - * 00000000000010 - (256) 10 - * 00000000000011 - (128) 9 - * 00000000000100 - (64) 8 - * 00000000000101 - (32) 7 - * 00000000000110 - (16) 6 - * 00000000000111 - (8) 5 - */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) -#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) - -/* Bitfield definition for register: DEVICEADDR */ -/* - * USBADR (RW) - * - * USBADR - * Device Address. - * These bits correspond to the USB device address - */ -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) -#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) - -/* - * USBADRA (RW) - * - * USBADRA - * Device Address Advance. Default=0. - * When this bit is '0', any writes to USBADR are instantaneous. - * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. - * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. - * Hardware will automatically clear this bit on the following conditions: - * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). - * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). - * 3) Device Reset occurs (USBADR is reset to 0). - * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. - * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. - * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), - * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) - -/* Bitfield definition for register: PERIODICLISTBASE */ -/* - * BASEADR (RW) - * - * BASEADR - * Base Address (Low). - * These bits correspond to memory address signals [31:12], respectively. - * Only used by the host controller. - */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) -#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) - -/* Bitfield definition for register: ASYNCLISTADDR */ -/* - * ASYBASE (RW) - * - * ASYBASE - * Link Pointer Low (LPL). - * These bits correspond to memory address signals [31:5], respectively. This field may only reference a - * Queue Head (QH). - * Only used by the host controller. - */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) -#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) - -/* Bitfield definition for register: ENDPTLISTADDR */ -/* - * EPBASE (RW) - * - * EPBASE - * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. - * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) -#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) - -/* Bitfield definition for register: BURSTSIZE */ -/* - * TXPBURST (RW) - * - * TXPBURST - * Programmable TX Burst Size. - * Default value is determined by TXBURST bits in n_HWTXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from system - * memory to the USB bus. - */ -#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) - -/* - * RXPBURST (RW) - * - * RXPBURST - * Programmable RX Burst Size. - * Default value is determined by TXBURST bits in n_HWRXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from the - * USB bus to system memory. - */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) - -/* Bitfield definition for register: TXFILLTUNING */ -/* - * TXFIFOTHRES (RW) - * - * TXFIFOTHRES - * FIFO Burst Threshold. (Read/Write) - * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. - * The minimum value is 2 and this value should be a low as possible to maximize USB performance. - * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth - * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. - * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - */ -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* - * TXSCHHEALTH (RWC) - * - * TXSCHHEALTH - * Scheduler Health Counter. (Read/Write To Clear) - * Table continues on the next page - * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES - * before running out of time to send the packet before the next Start-Of-Frame. - * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. - * Writing to this register will clear the counter and this counter will max. at 31. - */ -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) - -/* - * TXSCHOH (RW) - * - * TXSCHOH - * Scheduler Overhead. (Read/Write) [Default = 0] - * This register adds an additional fixed offset to the schedule time estimator described above as Tff. - * As an approximation, the value chosen for this register should limit the number of back-off events captured - * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. - * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. - * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. - * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. - * Default value is '08h' for OTG controller core . - */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) - -/* Bitfield definition for register: ENDPTNAK */ -/* - * EPTN (RWC) - * - * EPTN - * TX Endpoint NAK - R/WC. - * Each TX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received IN token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) -#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) - -/* - * EPRN (RWC) - * - * EPRN - * RX Endpoint NAK - R/WC. - * Each RX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) - -/* Bitfield definition for register: ENDPTNAKEN */ -/* - * EPTNE (RW) - * - * EPTNE - * TX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the - * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) - -/* - * EPRNE (RW) - * - * EPRNE - * RX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the - * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) - -/* Bitfield definition for register: PORTSC1 */ -/* - * STS (RW) - * - * STS - * Serial Transceiver Select - * 1 Serial Interface Engine is selected - * 0 Parallel Interface signals is selected - * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. - * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - */ -#define USB_PORTSC1_STS_MASK (0x20000000UL) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) - -/* - * PTW (RW) - * - * PTW - * Parallel Transceiver Width - * This bit has no effect if serial interface engine is used. - * 0 - Select the 8-bit UTMI interface [60MHz] - * 1 - Select the 16-bit UTMI interface [30MHz] - */ -#define USB_PORTSC1_PTW_MASK (0x10000000UL) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) - -/* - * PSPD (RO) - * - * PSPD - * Port Speed - Read Only. - * This register field indicates the speed at which the port is operating. - * 00 - Full Speed - * 01 - Low Speed - * 10 - High Speed - * 11 - Undefined - */ -#define USB_PORTSC1_PSPD_MASK (0xC000000UL) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) - -/* - * PFSC (RW) - * - * PFSC - * Port Force Full Speed Connect - Read/Write. Default = 0b. - * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp - * sequence that allows the port to identify itself as High Speed. - * 0 - Normal operation - * 1 - Forced to full speed - */ -#define USB_PORTSC1_PFSC_MASK (0x1000000UL) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) - -/* - * PHCD (RW) - * - * PHCD - * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. - * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY - * clock. - * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. - * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD - * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend - * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the - * device controller driver must clear this bit. - * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put - * into suspend mode or when no downstream device is connected. Low power suspend is completely - * under the control of software. - * 0 - Enable PHY clock - * 1 - Disable PHY clock - */ -#define USB_PORTSC1_PHCD_MASK (0x800000UL) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) - -/* - * WKOC (RW) - * - * WKOC - * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. - * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero. - */ -#define USB_PORTSC1_WKOC_MASK (0x400000UL) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) - -/* - * WKDC (RW) - * - * WKDC - * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables - * the port to be sensitive to device disconnects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKDC_MASK (0x200000UL) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) - -/* - * WKCN (RW) - * - * WKCN - * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. - * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKCN_MASK (0x100000UL) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) - -/* - * PTC (RW) - * - * PTC - * Port Test Control - Read/Write. Default = 0000b. - * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. - * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. - * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. - * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. - * NOTE: Low speed operations are not supported as a peripheral device. - * Any other value than zero indicates that the port is operating in test mode. - * Value Specific Test - * 0000 - TEST_MODE_DISABLE - * 0001 - J_STATE - * 0010 - K_STATE - * 0011 - SE0 (host) / NAK (device) - * 0100 - Packet - * 0101 - FORCE_ENABLE_HS - * 0110 - FORCE_ENABLE_FS - * 0111 - FORCE_ENABLE_LS - * 1000-1111 - Reserved - */ -#define USB_PORTSC1_PTC_MASK (0xF0000UL) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) - -/* - * PP (RW) - * - * PP - * Port Power (PP)-Read/Write or Read Only. - * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: - * PPC - * PP Operation - * 0 - * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. - * 1 - * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). - * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. - * When an over-current condition is detected on a powered port and PPC is a one, - * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). - * This feature is implemented in all controller cores (PPC = 1). - */ -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) - -/* - * LS (RO) - * - * LS - * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal - * lines. - * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because - * the port controller state machine and the port routing manage the connection of LS and FS. - * In device mode, the use of linestate by the device controller driver is not necessary. - * The encoding of the bits are: - * Bits [11:10] Meaning - * 00 - SE0 - * 01 - K-state - * 10 - J-state - * 11 - Undefined - */ -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) - -/* - * HSP (RO) - * - * HSP - * High-Speed Port - Read Only. Default = 0b. - * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the - * host/device connected to the port is not in a high-speed mode. - * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - */ -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) - -/* - * PR (RW) - * - * PR - * Port Reset - Read/Write or Read Only. Default = 0b. - * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. - * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. - * This bit will automatically change to zero after the reset sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. - * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - */ -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) - -/* - * SUSP (RW) - * - * SUSP - * Suspend - Read/Write or Read Only. Default = 0b. - * 1=Port in suspend state. 0=Port not in suspend state. - * In Host Mode: Read/Write. - * Port Enabled Bit and Suspend bit of this register define the port states as follows: - * Bits [Port Enabled, Suspend] Port State - * 0x Disable - * 10 Enable - * 11 Suspend - * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. - * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. - * In the suspend state, the port is sensitive to resume detection. - * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. - * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. - * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: Read Only. - * In device mode this bit is a read only status bit. - */ -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) - -/* - * FPR (RW) - * - * FPR - * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. - * In Host Mode: - * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. - * This bit will automatically change to zero after the resume sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. - * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. - * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. - * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * This bit is not-EHCI compatible. - * In Device mode: - * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. - * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * The bit will be cleared when the device returns to normal operation. - * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - */ -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) - -/* - * OCC (RW) - * - * OCC - * Over-current Change-R/WC. Default=0. - * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - */ -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) - -/* - * OCA (RO) - * - * OCA - * Over-current Active-Read Only. Default 0. - * This bit will automatically transition from one to zero when the over current condition is removed. - * 0 - This port does not have an over-current condition. - * 1 - This port currently has an over-current condition - */ -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) - -/* - * PEC (RWC) - * - * PEC - * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. - * In Host Mode: - * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or - * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). - * Software clears this by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero. - * In Device mode: - * The device port is always enabled, so this bit is always '0b'. - */ -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) - -/* - * PE (RWC) - * - * PE - * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. - * In Host Mode: - * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. - * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. - * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. - * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * The device port is always enabled, so this bit is always '1b'. - */ -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) - -/* - * CSC (RWC) - * - * CSC - * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. - * In Host Mode: - * Indicates a change has occurred in the port's Current Connect Status. - * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. - * For example, the insertion status changes twice before system software has cleared the changed condition, - * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * This bit is undefined in device controller mode. - */ -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) - -/* - * CCS (RWC) - * - * CCS - * Current Connect Status-Read Only. - * In Host Mode: - * 1=Device is present on port. 0=No device is present. Default = 0. - * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * 1=Attached. 0=Not Attached. Default=0. - * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. - * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. - * It does not state the device being disconnected or Suspended. - */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) - -/* Bitfield definition for register: OTGSC */ -/* - * ASVIE (RW) - * - * ASVIE - * A Session Valid Interrupt Enable - Read/Write. - */ -#define USB_OTGSC_ASVIE_MASK (0x4000000UL) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) - -/* - * AVVIE (RW) - * - * AVVIE - * A VBus Valid Interrupt Enable - Read/Write. - * Setting this bit enables the A VBus valid interrupt. - */ -#define USB_OTGSC_AVVIE_MASK (0x2000000UL) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) - -/* - * IDIE (RW) - * - * IDIE - * USB ID Interrupt Enable - Read/Write. - * Setting this bit enables the USB ID interrupt. - */ -#define USB_OTGSC_IDIE_MASK (0x1000000UL) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) - -/* - * ASVIS (RWC) - * - * ASVIS - * A Session Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the A session valid threshold. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_ASVIS_MASK (0x40000UL) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) - -/* - * AVVIS (RWC) - * - * AVVIS - * A VBus Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_AVVIS_MASK (0x20000UL) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) - -/* - * IDIS (RWC) - * - * IDIS - * USB ID Interrupt Status - Read/Write. - * This bit is set when a change on the ID input has been detected. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_IDIS_MASK (0x10000UL) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) - -/* - * ASV (RO) - * - * ASV - * A Session Valid - Read Only. - * Indicates VBus is above the A session valid threshold. - */ -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) - -/* - * AVV (RO) - * - * AVV - * A VBus Valid - Read Only. - * Indicates VBus is above the A VBus valid threshold. - */ -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) - -/* - * ID (RO) - * - * ID - * USB ID - Read Only. - * 0 = A device, 1 = B device - */ -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) - -/* - * IDPU (RW) - * - * IDPU - * ID Pullup - Read/Write - * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input - * will not be sampled. - */ -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) - -/* - * VC (RW) - * - * VC - * VBUS Charge - Read/Write. - * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - */ -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) - -/* - * VD (RW) - * - * VD - * VBUS_Discharge - Read/Write. - * Setting this bit causes VBus to discharge through a resistor. - */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) - -/* Bitfield definition for register: USBMODE */ -/* - * SDIS (RW) - * - * SDIS - * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) - * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. - * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. - * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. - * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems - * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. - * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for - * the scheduler when using this feature. - * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - */ -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) -#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) - -/* - * SLOM (RW) - * - * SLOM - * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . - * 0 - Setup Lockouts On (default); - * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - */ -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) - -/* - * ES (RW) - * - * ES - * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the - * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected - * by the value of this bit because they are based upon the 32-bit word. - * Bit Meaning - * 0 - Little Endian [Default] - * 1 - Big Endian - */ -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) - -/* - * CM (RW) - * - * CM - * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only - * implementations. For those designs that contain both host & device capability, the controller defaults to - * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ - * device controllers, this register can only be written once after reset. If it is necessary to switch modes, - * software must reset the controller by writing to the RESET bit in the USBCMD register before - * reprogramming this register. - * For OTG controller core, reset value is '00b'. - * 00 - Idle [Default for combination host/device] - * 01 - Reserved - * 10 - Device Controller [Default for device only controller] - * 11 - Host Controller [Default for host only controller] - */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) - -/* Bitfield definition for register: ENDPTSETUPSTAT */ -/* - * ENDPTSETUPSTAT (RWC) - * - * ENDPTSETUPSTAT - * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. - * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. - * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. - * This register is only used in device mode. - */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* Bitfield definition for register: ENDPTPRIME */ -/* - * PETB (RWS) - * - * PETB - * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a - * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. - * Software should write a one to the corresponding bit when posting a new transfer descriptor to an - * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor - * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated - * endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) -#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) - -/* - * PERB (RWS) - * - * PERB - * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. - * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. - * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. - * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) - -/* Bitfield definition for register: ENDPTFLUSH */ -/* - * FETB (RWS) - * - * FETB - * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) -#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) - -/* - * FERB (RWS) - * - * FERB - * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) - -/* Bitfield definition for register: ENDPTSTAT */ -/* - * ETBR (RO) - * - * ETBR - * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. - * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. - * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. - * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. - * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. - * ETBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) - -/* - * ERBR (RO) - * - * ERBR - * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective - * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a - * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the - * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB - * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the - * USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations - * when a dTD is retired, and the dQH is updated. - * ERBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) - -/* Bitfield definition for register: ENDPTCOMPLETE */ -/* - * ETCE (RWC) - * - * ETCE - * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. - * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. - * ETCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) - -/* - * ERCE (RWC) - * - * ERCE - * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred - * and software should read the corresponding endpoint queue to determine the transfer status. If the - * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the - * USBINT . Writing one clears the corresponding bit in this register. - * ERCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) - -/* Bitfield definition for register array: ENDPTCTRL */ -/* - * TXE (RW) - * - * TXE - * TX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) -#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) - -/* - * TXR (WS) - * - * TXR - * TX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the Host and device. - */ -#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) - -/* - * TXT (RW) - * - * TXT - * TX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) - -/* - * TXS (RW) - * - * TXS - * TX Endpoint Stall - Read/Write - * 0 End Point OK - * 1 End Point Stalled - * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured - * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. - * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. - * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: - * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - */ -#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) - -/* - * RXE (RW) - * - * RXE - * RX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) - -/* - * RXR (WS) - * - * RXR - * RX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the host and device. - */ -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) - -/* - * RXT (RW) - * - * RXT - * RX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) - -/* - * RXS (RW) - * - * RXS - * RX Endpoint Stall - Read/Write - * 0 End Point OK. [Default] - * 1 End Point Stalled - * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control - * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit - * is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This - * control will continue to STALL until this bit is either cleared by software or automatically cleared as above - * for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the - * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it - * is unlikely the DCD software will observe this delay. However, should the DCD observe that the - * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit - * until it is set or until a new setup has been received by checking the associated endptsetupstat - * Bit. - */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) - -/* Bitfield definition for register: OTG_CTRL0 */ -/* - * OTG_WKDPDMCHG_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) - -/* - * AUTORESUME_EN (RW) - * - */ -#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) -#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) -#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) -#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) - -/* - * OTG_VBUS_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) - -/* - * OTG_ID_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) - -/* - * OTG_VBUS_SOURCE_SEL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) - -/* - * OTG_UTMI_SUSPENDM_SW (RW) - * - * default 0 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) - -/* - * OTG_UTMI_RESET_SW (RW) - * - * default 1 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) - -/* - * OTG_WAKEUP_INT_ENABLE (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) - -/* - * OTG_POWER_MASK (RW) - * - */ -#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) -#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) - -/* - * OTG_OVER_CUR_POL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) - -/* - * OTG_OVER_CUR_DIS (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) - -/* - * SER_MODE_SUSPEND_EN (RW) - * - * for naneng usbphy, only switch to serial mode when suspend - */ -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL0 */ -/* - * GPIO_ID_SEL_N (RW) - * - */ -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) - -/* - * ID_DIG_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) - -/* - * SESS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) - -/* - * VBUS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) - -/* - * ID_DIG_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) - -/* - * SESS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) - -/* - * VBUS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL1 */ -/* - * UTMI_CFG_RST_N (RW) - * - */ -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) - -/* - * UTMI_OTG_SUSPENDM (RW) - * - * OTG suspend, not utmi_suspendm - */ -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) - -/* Bitfield definition for register: TOP_STATUS */ -/* - * WAKEUP_INT_STATUS (RW) - * - */ -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * UTMI_CLK_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) -#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) - -/* - * LINE_STATE (RW) - * - */ -#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) -#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) -#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) -#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) - -/* - * HOST_DISCONNECT (RW) - * - */ -#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) -#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) - -/* - * ID_DIG (RW) - * - */ -#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) -#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) -#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) -#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) - -/* - * UTMI_SESS_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) -#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) - -/* - * VBUS_VALID (RW) - * - */ -#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) -#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) -#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) -#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) - - - -/* ENDPTCTRL register group index macro definition */ -#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) -#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) -#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) -#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) -#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) -#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) -#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) -#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) - - -#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_wdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_wdg_regs.h deleted file mode 100644 index 89788a7ebce..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6300/ip/hpm_wdg_regs.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_WDG_H -#define HPM_WDG_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CTRL; /* 0x10: Control Register */ - __W uint32_t RESTART; /* 0x14: Restart Register */ - __W uint32_t WREN; /* 0x18: Write Protection Register */ - __W uint32_t ST; /* 0x1C: Status Register */ -} WDG_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * RSTTIME (RW) - * - * The time interval of the reset stage: - * 0: Clock period x 2^7 - * 1: Clock period x 2^8 - * 2: Clock period x 2^9 - * 3: Clock period x 2^10 - * 4: Clock period x 2^11 - * 5: Clock period x 2^12 - * 6: Clock period x 2^13 - * 7: Clock period x 2^14 - */ -#define WDG_CTRL_RSTTIME_MASK (0x700U) -#define WDG_CTRL_RSTTIME_SHIFT (8U) -#define WDG_CTRL_RSTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK) -#define WDG_CTRL_RSTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT) - -/* - * INTTIME (RW) - * - * The timer interval of the interrupt stage: - * 0: Clock period x 2^6 - * 1: Clock period x 2^8 - * 2: Clock period x 2^10 - * 3: Clock period x 2^11 - * 4: Clock period x 2^12 - * 5: Clock period x 2^13 - * 6: Clock period x 2^14 - * 7: Clock period x 2^15 - * 8: Clock period x 2^17 - * 9: Clock period x 2^19 - * 10: Clock period x 2^21 - * 11: Clock period x 2^23 - * 12: Clock period x 2^25 - * 13: Clock period x 2^27 - * 14: Clock period x 2^29 - * 15: Clock period x 2^31 - */ -#define WDG_CTRL_INTTIME_MASK (0xF0U) -#define WDG_CTRL_INTTIME_SHIFT (4U) -#define WDG_CTRL_INTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK) -#define WDG_CTRL_INTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT) - -/* - * RSTEN (RW) - * - * Enable or disable the watchdog reset - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_RSTEN_MASK (0x8U) -#define WDG_CTRL_RSTEN_SHIFT (3U) -#define WDG_CTRL_RSTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK) -#define WDG_CTRL_RSTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT) - -/* - * INTEN (RW) - * - * Enable or disable the watchdog interrupt - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_INTEN_MASK (0x4U) -#define WDG_CTRL_INTEN_SHIFT (2U) -#define WDG_CTRL_INTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK) -#define WDG_CTRL_INTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT) - -/* - * CLKSEL (RW) - * - * Clock source of timer: - * 0: EXTCLK - * 1: PCLK - */ -#define WDG_CTRL_CLKSEL_MASK (0x2U) -#define WDG_CTRL_CLKSEL_SHIFT (1U) -#define WDG_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK) -#define WDG_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT) - -/* - * EN (RW) - * - * Enable or disable the watchdog timer - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_EN_MASK (0x1U) -#define WDG_CTRL_EN_SHIFT (0U) -#define WDG_CTRL_EN_SET(x) (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK) -#define WDG_CTRL_EN_GET(x) (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT) - -/* Bitfield definition for register: RESTART */ -/* - * RESTART (WO) - * - * Write the magic number - * ATCWDT200_RESTART_NUM to restart the - * watchdog timer. - */ -#define WDG_RESTART_RESTART_MASK (0xFFFFU) -#define WDG_RESTART_RESTART_SHIFT (0U) -#define WDG_RESTART_RESTART_SET(x) (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK) -#define WDG_RESTART_RESTART_GET(x) (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT) - -/* Bitfield definition for register: WREN */ -/* - * WEN (WO) - * - * Write the magic code to disable the write - * protection of the Control Register and the - * Restart Register. - */ -#define WDG_WREN_WEN_MASK (0xFFFFU) -#define WDG_WREN_WEN_SHIFT (0U) -#define WDG_WREN_WEN_SET(x) (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK) -#define WDG_WREN_WEN_GET(x) (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * INTEXPIRED (W1C) - * - * The status of the watchdog interrupt timer - * 0: timer is not expired yet - * 1: timer is expired - */ -#define WDG_ST_INTEXPIRED_MASK (0x1U) -#define WDG_ST_INTEXPIRED_SHIFT (0U) -#define WDG_ST_INTEXPIRED_SET(x) (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK) -#define WDG_ST_INTEXPIRED_GET(x) (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT) - - - - -#endif /* HPM_WDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/HPM6750_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/HPM6750_svd.xml deleted file mode 100644 index c9969b00b23..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/HPM6750_svd.xml +++ /dev/null @@ -1,34201 +0,0 @@ - - - HPMICRO - HPM6750 - HPM6700 - 1.0 - HPM6700/HPM6400 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf0000000 - - - GPIO1 - GPIO1 - GPIO - 0xf0004000 - - - PGPIO - PGPIO - GPIO - 0xf40dc000 - - - BGPIO - BGPIO - GPIO - 0xf5014000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPIOM - GPIOM - GPIOM - 0xf0008000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - - - - ADC0 - ADC0 - ADC12 - 0xf0010000 - - 0x0 - 0x1214 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 19 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFF0 - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 4 - 12 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00000FFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 12 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 19 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFF0FFF0 - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 20 - 12 - read-write - - - THSHDL - threshold low - 4 - 12 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFF0 - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 4 - 12 - read-only - - - - - - 19 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15,chn16,chn17,chn18 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00001FFF - - - DIFF_SEL - set to 1 to select differential channel - 12 - 1 - read-write - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample_clock_number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); -set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC conversion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000000 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - No description available - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1 - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE7FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 19 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x7F7F487E - - - CAL_VAL_DIFF - calibration value for differential mode - 24 - 7 - read-write - - - CAL_VAL_SE - calibration value for single-end mode - 16 - 7 - read-write - - - REARM_EN - set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number - 14 - 1 - read-write - - - SELRANGE_LDO - Defines the range for the LDO reference (vdd_soc) -selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] -selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] - 11 - 1 - read-write - - - ENLDO - set to enable adc LDO, need at least 20us for LDO to be stable. - 6 - 1 - read-write - - - ENADC - set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. - 5 - 1 - read-write - - - RESETADC - set to 1 to reset adc analog; default high. - 4 - 1 - read-write - - - RESETCAL - set to 1 to reset calibration logic; default high. - 3 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - LOADCAL - Signal that loads the offset calibration word into the internal registers (Active H) - 1 - 1 - read-write - - - - - ana_ctrl1 - No description available - 0x1204 - 32 - 0x00000000 - 0x000000C0 - - - SELRES - 11-12bit -10-10bit -01-8bit -00-6bit - 6 - 2 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x000000FF - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - CAL_OUT - No description available - 0 - 7 - read-write - - - - - - - ADC1 - ADC1 - ADC12 - 0xf0014000 - - - ADC2 - ADC2 - ADC12 - 0xf0018000 - - - ADC3 - ADC3 - ADC16 - 0xf001c000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F3F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 8 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - 8 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 8 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x03F07FFF - - - TEMPSNS_EN - set to enable temp sensor - 25 - 1 - read-write - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ACMP - ACMP - ACMP - 0xf0020000 - - 0x0 - 0x80 - registers - - - - 4 - 0x20 - chn0,chn1,chn2,chn3 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFF7FFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - SPI0 - SPI0 - SPI - 0xf0030000 - - 0x10 - 0x70 - registers - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x00FFFF1F - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0034000 - - - SPI2 - SPI2 - SPI - 0xf0038000 - - - SPI3 - SPI3 - SPI - 0xf003c000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x10 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x0000000F - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x000000CF - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - UART8 - UART8 - UART - 0xf0060000 - - - UART9 - UART9 - UART - 0xf0064000 - - - UART10 - UART10 - UART - 0xf0068000 - - - UART11 - UART11 - UART - 0xf006c000 - - - UART12 - UART12 - UART - 0xf0070000 - - - UART13 - UART13 - UART - 0xf0074000 - - - UART14 - UART14 - UART - 0xf0078000 - - - UART15 - UART15 - UART - 0xf007c000 - - - PUART - PUART - UART - 0xf40e4000 - - - CAN0 - CAN0 - CAN - 0xf0080000 - - 0x0 - 0xca - registers - - - - 20 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17,buf18,buf19 - RBUF[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RBUF - receive buffer - 0 - 32 - read-write - - - - - 18 - 0x4 - buf0,buf1,buf2,buf3,buf4,buf5,buf6,buf7,buf8,buf9,buf10,buf11,buf12,buf13,buf14,buf15,buf16,buf17 - TBUF[%s] - no description available - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBUF - transmit buffer - 0 - 32 - read-write - - - - - 2 - 0x4 - wrd0,wrd1 - TTS[%s] - no description available - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - TTS_WRD0 - transmission time stamp, word 0, LSB 32bit - 0 - 32 - read-only - - - - - CMD_STA_CMD_CTRL - config, status, command and control bits - 0xa0 - 32 - 0x00900080 - 0xFBF3FFFF - - - SACK - Self-ACKnowledge -0 – no self-ACK -1 – self-ACK when LBME=1 - 31 - 1 - read-write - - - ROM - Receive buffer Overflow Mode -In case of a full RBUF when a new message is received, then ROM selects the following: -1 – The new message will not be stored. -0 – The oldest message will be overwritten. - 30 - 1 - read-write - - - ROV - Receive buffer OVerflow -1 – Overflow. At least one message is lost. -0 – No Overflow. -ROV is cleared by setting RREL=1. - 29 - 1 - read-only - - - RREL - Receive buffer RELease -The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL -core points to the next RB slot. RSTAT gets updated. -1 – Release: The host has read the RB. -0 – No release - 28 - 1 - read-write - - - RBALL - Receive Buffer stores ALL data frames -0 – normal operation -1 – RB stores correct data frames as well as data frames with error - 27 - 1 - read-write - - - RSTAT - Receive buffer STATus -00 - empty -01 - > empty and < almost full (AFWL) -10 -  almost full (programmable threshold by AFWL) but not full and no overflow -11 - full (stays set in case of overflow – for overflow signaling see ROV) - 24 - 2 - read-only - - - FD_ISO - CAN FD ISO mode -0 - Bosch CAN FD (non-ISO) mode -1 - ISO CAN FD mode (ISO 11898-1:2015) -ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. -Both modes are incompatible and must not be mixed in one CAN network. -This bit has no impact to CAN 2.0B. -This bit is only writeable if RESET=1. - 23 - 1 - read-write - - - TSNEXT - Transmit buffer Secondary NEXT -0 - no action -1 - STB slot filled, select next slot. -After all frame bytes are written to the TBUF registers, the host controller has to set -TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF -registers to the next slot. Once a slot is marked as filled a transmission can be started -using TSONE or TSALL. -It is possible to set TSNEXT and TSONE or TSALL together in one write access. -TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL -core immediately after it was set. -Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and -automatically cleared. It does not do any harm. -If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. -TSNEXT has no meaning in TTCAN mode and is fixed to 0. - 22 - 1 - read-write - - - TSMODE - Transmit buffer Secondary operation MODE -0 - FIFO mode -1 - priority decision mode -In FIFO mode frames are transmitted in the order in that they are written into the STB. -In priority decision mode the frame with the highest priority in the STB is automatically -transmitted first. The ID of a frame is used for the priority decision. A lower ID means a -higher priority of a frame. A frame in the PTB has always the highest priority regardless of -the ID. -TSMODE shall be switched only if the STB if empty - 21 - 1 - read-write - - - TTTBM - TTCAN Transmit Buffer Mode -If TTEN=0 then TTTBM is ignored, otherwise the following is valid: -0 - separate PTB and STB, behavior defined by TSMODE -1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR -For event-driven CAN communication (TTEN=0), the system provides PTB and STB and -the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. -For time-triggered CAN communication (TTEN=1) with full support of all features including -time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are -addressable using TTPTR and TBPTR. -For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode -and the behavior can be selected by TSMODE. -TTTBM shall be switched only if the TBUF is empty. - 20 - 1 - read-write - - - TSSTAT - Transmission Secondary STATus bits -If TTEN=0 or TTTBM=0: -00 – STB is empty -01 – STB is less than or equal to half full -10 – STB is more than half full -11 – STB is full -If the STB is disabled using STB_DISABLE, then TSSTAT=00. -If TTEN=1 and TTTBM=1: -00 – PTB and STB are empty -01 – PTB and STB are not empty and not full -11 – PTB and STB are full - 16 - 2 - read-only - - - TBSEL - Transmit Buffer Select -Selects the transmit buffer to be loaded with a message. Use the TBUF registers for -access. TBSEL needs to be stable all the time the TBUF registers are written and when -TSNEXT is set. -0 - PTB (high-priority buffer) -1 - STB -The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - 15 - 1 - read-write - - - LOM - Listen Only Mode -0 - Disabled -1 - Enabled -LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM -is enabled and LBME is disabled. -LOM=1 and LBME=0 disables all transmissions. -LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables -the transmission of own frames. - 14 - 1 - read-write - - - STBY - Transceiver Standby Mode -0 - Disabled -1 - Enabled -This register bit is connected to the output signal stby which can be used to control a -standby mode of a transceiver. -STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. -If the host sets STBY to 0 then the host needs to wait for the time required by the -transceiver to start up before the host requests a new transmission. - 13 - 1 - read-write - - - TPE - Transmit Primary Enable -1 - Transmission enable for the message in the high-priority PTB -0 - No transmission for the PTB -If TPE is set, the message from the PTB will be transmitted at the next possible transmit -position. A started transmission from the STB will be completed before, but pending new -messages are delayed until the PTB message has been transmitted. -TPE stays set until the message has been transmitted successfully or it is aborted using -TPA. -The host controller can set TPE to 1 but can not reset it to 0. This would only be possible -using TPA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 12 - 1 - read-write - - - TPA - Transmit Primary Abort -1 – Aborts a transmission from PTB which has been requested by TPE=1 but not -started yet. (The data bytes of the message remains in the PTB.) -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA -automatically de-asserts TPE. -The host controller can set TPA to 1 but can not reset it to 0. -During the short time while the CAN-CTRL core resets the bit, it cannot be set by the -host. -The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). -TPA should not be set simultaneously with TPE. - 11 - 1 - read-write - - - TSONE - Transmit Secondary ONE frame -1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message -and in priority mode this is the one with the highest priority. -TSONE in priority mode is difficult to handle, because it is not always clear which -message will be transmitted if new messages are written to the STB meanwhile. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSONE stays set until the message has been transmitted successfully or it is aborted -using TSA. -The host controller can set TSONE to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the message. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). - 10 - 1 - read-write - - - TSALL - Transmit Secondary ALL frames -1 – Transmission enable of all messages in the STB. -The controller starts the transmission as soon as the bus becomes vacant and -no request of the PTB (bit TPE) is pending. -0 – No transmission for the STB. -TSALL stays set until all messages have been transmitted successfully or they are aborted -using TSA. -The host controller can set TSALL to 1 but can not reset it to 0. This would only be -possible using TSA and aborting the messages. -The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and -LBME=0) or (TTEN=1 and TTTBM=1). -If during a transmission the STB is loaded with a new frame then the new frame will be -transmitted too. In other words: a transmission initiated by TSALL is finished when the -STB becomes empty. - 9 - 1 - read-write - - - TSA - Transmit Secondary Abort -1 – Aborts a transmission from STB which has been requested but not started yet. -For a TSONE transmission, only one frame is aborted while for a TSALL -Transmission, all frames are aborted. -One or all message slots will be released which updates TSSTAT. -All aborted messages are lost because they are not accessible any more. -If in priority mode a TSONE transmission is aborted, then it is not clear which -frame will be aborted if new frames are written to the STB meanwhile. -0 – no abort -The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. -The host controller can set TSA to 1 but can not reset it to 0. -The bit will be reset to the hardware reset value if RESET=1. -TSA should not be set simultaneously with TSONE or TSALL. - 8 - 1 - read-write - - - RESET - RESET request bit -1 - The host controller performs a local reset of CAN-CTRL. -0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. -Bit RESET forces several components to a reset state. -RESET is automatically set if the node enters “bus off” state. -Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. -This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. -The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - 7 - 1 - read-write - - - LBME - Loop Back Mode, External -0 - Disabled -1 - EnabledLBME should not be enabled while a transmission is active - 6 - 1 - read-write - - - LBMI - Loop Back Mode, Internal -0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - 5 - 1 - read-write - - - TPSS - Transmission Primary Single Shot mode for PTB -0 - Disabled -1 - Enabled - 4 - 1 - read-write - - - TSSS - Transmission Secondary Single Shot mode for STB -0 - Disabled -1 - Enabled - 3 - 1 - read-write - - - RACTIVE - Reception ACTIVE (Receive Status bit) -1 - The controller is currently receiving a frame. -0 - No receive activity. - 2 - 1 - read-only - - - TACTIVE - Transmission ACTIVE (Transmit Status bit) -1 - The controller is currently transmitting a frame. -0 - No transmit activity. - 1 - 1 - read-only - - - BUSOFF - Bus Off (Bus Status bit) -1 - The controller status is “bus off”. -0 - The controller status is “bus on”. -Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. -See Chapter 3.9.10.6 for details. - 0 - 1 - read-write - - - - - RTIE - Receive and Transmit Interrupt Enable Register RTIE - 0xa4 - 8 - 0xFE - 0xFF - - - RIE - Receive Interrupt Enable -0 – Disabled, 1 – Enabled - 7 - 1 - read-write - - - ROIE - RB Overrun Interrupt Enable -0 – Disabled, 1 – Enabled - 6 - 1 - read-write - - - RFIE - RB Full Interrupt Enable -0 – Disabled, 1 – Enabled - 5 - 1 - read-write - - - RAFIE - RB Almost Full Interrupt Enable -0 – Disabled, 1 – Enabled - 4 - 1 - read-write - - - TPIE - Transmission Primary Interrupt Enable -0 – Disabled, 1 – Enabled - 3 - 1 - read-write - - - TSIE - Transmission Secondary Interrupt Enable -0 – Disabled, 1 – Enabled - 2 - 1 - read-write - - - EIE - Error Interrupt Enable -0 – Disabled, 1 – Enabled - 1 - 1 - read-write - - - TSFF - If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag -1 - The STB is filled with the maximal number of messages. -0 - The STB is not filled with the maximal number of messages. -If the STB is disabled using STB_DISABLE, then TSFF=0. -If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag -1 - The buffer slot selected by TBPTR is filled. -0 - The buffer slot selected by TBPTR is empty. - 0 - 1 - read-only - - - - - RTIF - Receive and Transmit Interrupt Flag Register RTIF (0xa5) - 0xa5 - 8 - 0x00 - 0xFF - - - RIF - Receive Interrupt Flag -1 - Data or a remote frame has been received and is available in the receive buffer. -0 - No frame has been received. - 7 - 1 - write-only - - - ROIF - RB Overrun Interrupt Flag -1 - At least one received message has been overwritten in the RB. -0 - No RB overwritten. -In case of an overrun both ROIF and RFIF will be set. - 6 - 1 - write-only - - - RFIF - RB Full Interrupt Flag -1 - All RBs are full. If no RB will be released until the next valid message is received, -the oldest message will be lost. -0 - The RB FIFO is not full. - 5 - 1 - write-only - - - RAFIF - RB Almost Full Interrupt Flag -1 - number of filled RB slots >= AFWL_i -0 - number of filled RB slots < AFWL_i - 4 - 1 - write-only - - - TPIF - Transmission Primary Interrupt Flag -1 - The requested transmission of the PTB has been successfully completed. -0 - No transmission of the PTB has been completed. -In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - 3 - 1 - write-only - - - TSIF - Transmission Secondary Interrupt Flag -1 - The requested transmission of the STB has been successfully completed. -0 - No transmission of the STB has been completed successfully. -In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of -the message. - 2 - 1 - write-only - - - EIF - Error Interrupt Flag -1 - The border of the error warning limit has been crossed in either direction, -or the BUSOFF bit has been changed in either direction. -0 - There has been no change. - 1 - 1 - write-only - - - AIF - Abort Interrupt Flag -1 - After setting TPA or TSA the appropriated message(s) have been aborted. -It is recommended to not set both TPA and TSA simultaneously because both -source AIF. -0 - No abort has been executed. -The AIF does not have an associated enable register. - 0 - 1 - write-only - - - - - ERRINT - ERRor INTerrupt Enable and Flag Register ERRINT - 0xa6 - 8 - 0x00 - 0xFF - - - EWARN - Error WARNing limit reached -1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - 7 - 1 - read-only - - - EPASS - Error Passive mode active -0 - not active (node is error active) -1 - active (node is error passive) - 6 - 1 - read-only - - - EPIE - Error Passive Interrupt Enable - 5 - 1 - read-write - - - EPIF - Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error -active to error passive or vice versa and if this interrupt is enabled. - 4 - 1 - write-only - - - ALIE - Arbitration Lost Interrupt Enable - 3 - 1 - read-write - - - ALIF - Arbitration Lost Interrupt Flag - 2 - 1 - write-only - - - BEIE - Bus Error Interrupt Enable - 1 - 1 - read-write - - - BEIF - Bus Error Interrupt Flag - 0 - 1 - write-only - - - - - LIMIT - Warning Limits Register LIMIT - 0xa7 - 8 - 0x1B - 0xFF - - - AFWL - receive buffer Almost Full Warning Limit -AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. -AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . -AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) -AFWL_i > nRB is meaningless and automatically treated as nRB. -AFWL_i = nRB is a valid value, but note that RFIF also exists. - 4 - 4 - read-write - - - EWL - Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. -The value of EWL controls EIF. - 0 - 4 - read-write - - - - - S_PRESC - Bit Timing Register(Slow Speed) - 0xa8 - 32 - 0x01020203 - 0xFF7F7FFF - - - S_PRESC - Prescaler (slow speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - S_SJW - Synchronization Jump Width (slow speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 7 - read-write - - - S_SEG_2 - Bit Timing Segment 2 (slow speed) -Time after the sample point. - 8 - 7 - read-write - - - S_SEG_1 - Bit Timing Segment 1 (slow speed) -The sample point will be set to after start of bit time. - 0 - 8 - read-write - - - - - F_PRESC - Bit Timing Register(Fast Speed) - 0xac - 32 - 0x01020203 - 0xFF0F0F0F - - - F_PRESC - Prescaler (fast speed) -The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - 24 - 8 - read-write - - - F_SJW - Synchronization Jump Width (fast speed) -The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - 16 - 4 - read-write - - - F_SEG_2 - Bit Timing Segment 2 (fast speed) -Time after the sample point - 8 - 4 - read-write - - - F_SEG_1 - Bit Timing Segment 1 (fast speed) -The sample point will be set to after start of bit time. - 0 - 4 - read-write - - - - - EALCAP - Error and Arbitration Lost Capture Register EALCAP - 0xb0 - 8 - 0x00 - 0xFF - - - KOER - Kind Of ERror (Error code) -000 - no error -001 - BIT ERROR -010 - FORM ERROR -011 - STUFF ERROR -100 - ACKNOWLEDGEMENT ERROR -101 - CRC ERROR -110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) -111 - not used -KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - 5 - 3 - read-only - - - ALC - Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - 0 - 5 - read-only - - - - - TDC - Transmitter Delay Compensation Register TDC - 0xb1 - 8 - 0x00 - 0xFF - - - TDCEN - Transmitter Delay Compensation ENable -TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - 7 - 1 - read-write - - - SSPOFF - Secondary Sample Point OFFset -The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. -SSPOFF is given as a number of TQ. - 0 - 7 - read-write - - - - - RECNT - Error Counter Registers RECNT - 0xb2 - 8 - 0x00 - 0xFF - - - RECNT - Receive Error CouNT (number of errors during reception) -RECNT is incremented and decremented as defined in the CAN specification. -RECNT does not overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - TECNT - Error Counter Registers TECNT - 0xb3 - 8 - 0x00 - 0xFF - - - TECNT - Transmit Error CouNT (number of errors during transmission) -TECNT is incremented and decremented as defined in the CAN specification. -In case of the “bus off state” TECNT may overflow. -If TXB=1, then the error counters are frozen. - 0 - 8 - read-only - - - - - ACFCTRL - Acceptance Filter Control Register ACFCTRL - 0xb4 - 8 - 0x00 - 0x2F - - - SELMASK - SELect acceptance MASK -0 - Registers ACF_x point to acceptance code -1 - Registers ACF_x point to acceptance mask. -ACFADR selects one specific acceptance filter. - 5 - 1 - read-write - - - ACFADR - acceptance filter address -ACFADR points to a specific acceptance filter. -The selected filter is accessible using theregisters ACF_x. -Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. -A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. -ACF_NUMBER = 16. - 0 - 4 - read-write - - - - - TIMECFG - CiA 603 Time-Stamping TIMECFG - 0xb5 - 8 - 0x00 - 0x03 - - - TIMEPOS - TIME-stamping POSition -0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - 1 - 1 - read-write - - - TIMEEN - TIME-stamping ENable -0 – disabled -1 – enabled - 0 - 1 - read-write - - - - - ACF_EN - Acceptance Filter Enable ACF_EN - 0xb6 - 16 - 0x0000 - 0xFFFF - - - ACF_EN - Acceptance filter Enable -1 - acceptance filter enabled -0 - acceptance filter disable -Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. -Disabled filters reject a message. Only enabled filters can accept a message if the -appropriate AMASK / ACODE configuration matches. - 0 - 16 - read-write - - - - - ACF - Acceptance CODE ACODE or ACMASK - 0xb8 - 32 - 0x00000000 - 0x7FFFFFFF - - - AIDEE - Acceptance mask IDE bit check enable -1 - acceptance filter accepts either standard or extended as defined by AIDE -0 - acceptance filter accepts both standard or extended frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 30 - 1 - read-write - - - AIDE - Acceptance mask IDE bit value -If AIDEE=1 then: -1 - acceptance filter accepts only extended frames -0 - acceptance filter accepts only standard frames -Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - 29 - 1 - read-write - - - CODE_MASK - Acceptance CODE -1 - ACC bit value to compare with ID bit of the received message -0 - ACC bit value to compare with ID bit of the received message -ACODE_x(10:0) will be used for extended frames. -ACODE_x(28:0) will be used for extended frames. -Only filter 0 is affected by the power-on reset. -Acceptance MASK(if SELMASK ==1 ) -1 - acceptance check for these bits of receive identifier disabled -0 - acceptance check for these bits of receive identifier enable -AMASK_x(10:0) will be used for extended frames. -AMASK_x(28:0) will be used for extended frames. -Disabled bits result in accepting the message. Therefore the default configuration after -reset for filter 0 accepts all messages. -Only filter 0 is affected by the power-on reset. - 0 - 29 - read-write - - - - - VER - Version Information VER - 0xbc - 16 - 0x0000 - 0xFFFF - - - VERSION - Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and -VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - 0 - 16 - read-write - - - - - TBSLOT - TTCAN: TB Slot Pointer TBSLOT - 0xbe - 8 - 0x00 - 0xFF - - - TBE - set TB slot to “Empty” -1 - slot selected by TBPTR shall be marked as “empty” -0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. -If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - transmissionis not active any more. -If both TBF and TBE are set, then TBE wins - 7 - 1 - read-write - - - TBF - set TB slot to “Filled” -1 - slot selected by TBPTR shall be marked as “filled” -0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. -If both TBF and TBE are set, then TBE wins. - 6 - 1 - read-write - - - TBPTR - Pointer to a TB message slot. -0x00 - Pointer to the PTB -others - Pointer to a slot in the STB -The message slot pointed to by TBPTR is readable / writable using the TBUF registers. -Write access is only possible if TSFF=0. -Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. -TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. -TBPTR can only point to buffer slots, that exist in the hardware. -Unusable bits ofTBPTR are fixed to 0. -TBPTR is limited to the PTB and 63 STB slots. - More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - 0 - 6 - read-write - - - - - TTCFG - TTCAN: Time Trigger Configuration TTCFG - 0xbf - 8 - 0x00 - 0xFF - - - WTIE - Watch Trigger Interrupt Enable - 7 - 1 - read-write - - - WTIF - Watch Trigger Interrupt Flag -WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - 6 - 1 - read-write - - - TEIF - Trigger Error Interrupt Flag -The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - 5 - 1 - read-write - - - TTIE - Time Trigger Interrupt Enable -If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - 4 - 1 - read-write - - - TTIF - Time Trigger Interrupt Flag -TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. -Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. -If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - 3 - 1 - read-write - - - T_PRESC - TTCAN Timer PRESCaler -00b - 1 -01b - 2 -10b - 4 -11b - 8 -The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. -T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - 1 - 2 - read-write - - - TTEN - Time Trigger Enable -1 - TTCAN enabled, timer is running0 - disabled - 0 - 1 - read-write - - - - - REF_MSG - TTCAN: Reference Message REF_MSG - 0xc0 - 32 - 0x00000000 - 0x9FFFFFFF - - - REF_IDE - REFerence message IDE bit. - 31 - 1 - read-write - - - REF_MSG - REFerence message IDentifier. -If REF_IDE is -1 - REF_ID(28:0) is valid (extended ID) -0 - REF_ID(10:0) is valid (standard ID) -REF_ID is used in TTCAN mode to detect a reference message. This holds for time -slaves (reception) as well as for the time master (transmission). If the reference -message is detected and there are no errors, then the Sync_Mark of this frame will -become the Ref_Mark. -REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. -These bits are used for up to 8 potential time masters. -CAN-CTRL recognizes the reference message only by ID. The payload is not tested. -Additional note: A time master will transmit a reference message in the same way as a -normal frame. REF_ID is intended for detection of a successful transmission of a -reference message. - 0 - 29 - read-write - - - - - TRIG_CFG - TTCAN: Trigger Configuration TRIG_CFG - 0xc4 - 16 - 0x0000 - 0xF73F - - - TEW - Transmit Enable Window -For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time -where the frame is allowed to start. TWE+1 defines the number of ticks. -TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - 12 - 4 - read-write - - - TTYPE - Trigger Type -000b - Immediate Trigger for immediate transmission -001b - Time Trigger for receive triggers -010b - Single Shot Transmit Trigger for exclusive time windows -011b - Transmit Start Trigger for merged arbitrating time windows -100b - Transmit Stop Trigger for merged arbitrating time windows -others - no action -The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the -transmit triggers. See Chapter 6.4 for more details. - 8 - 3 - read-write - - - TTPTR - Transmit Trigger TB slot Pointer -If TTPTR is too big and points to a slot that is not available, then TEIF is set and no -new trigger can be activated after a write access to TT_TRIG_1. -If TTPTR points to an empty slot, then TEIF will be set at the moment, when the -trigger time is reached. - 0 - 6 - read-write - - - - - TT_TRIG - TTCAN: Trigger Time TT_TRIG - 0xc6 - 16 - 0x0000 - 0xFFFF - - - TT_TRIG - Trigger Time -TT_TRIG(15:0) defines the cycle time for a trigger. -For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - 0 - 16 - read-write - - - - - TT_WTRIG - TTCAN: Watch Trigger Time TT_WTRIG - 0xc8 - 16 - 0x0000 - 0xFFFF - - - TT_WTRIG - Watch Trigger Time -TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - 0 - 16 - read-write - - - - - - - CAN1 - CAN1 - CAN - 0xf0084000 - - - CAN2 - CAN2 - CAN - 0xf0088000 - - - CAN3 - CAN3 - CAN - 0xf008c000 - - - WDG0 - WDG0 - WDOG - 0xf0090000 - - 0x10 - 0x10 - registers - - - - CTRL - Control Register - 0x10 - 32 - 0x00000000 - 0x000007FF - - - RSTTIME - The time interval of the reset stage: -0: Clock period x 2^7 -1: Clock period x 2^8 -2: Clock period x 2^9 -3: Clock period x 2^10 -4: Clock period x 2^11 -5: Clock period x 2^12 -6: Clock period x 2^13 -7: Clock period x 2^14 - 8 - 3 - read-write - - - INTTIME - The timer interval of the interrupt stage: -0: Clock period x 2^6 -1: Clock period x 2^8 -2: Clock period x 2^10 -3: Clock period x 2^11 -4: Clock period x 2^12 -5: Clock period x 2^13 -6: Clock period x 2^14 -7: Clock period x 2^15 -8: Clock period x 2^17 -9: Clock period x 2^19 -10: Clock period x 2^21 -11: Clock period x 2^23 -12: Clock period x 2^25 -13: Clock period x 2^27 -14: Clock period x 2^29 -15: Clock period x 2^31 - 4 - 4 - read-write - - - RSTEN - Enable or disable the watchdog reset -0: Disable -1: Enable - 3 - 1 - read-write - - - INTEN - Enable or disable the watchdog interrupt -0: Disable -1: Enable - 2 - 1 - read-write - - - CLKSEL - Clock source of timer: -0: EXTCLK -1: PCLK - 1 - 1 - read-write - - - EN - Enable or disable the watchdog timer -0: Disable -1: Enable - 0 - 1 - read-write - - - - - Restart - Restart Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - RESTART - Write the magic number -ATCWDT200_RESTART_NUM to restart the -watchdog timer. - 0 - 16 - write-only - - - - - WrEn - Write Protection Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - WEN - Write the magic code to disable the write -protection of the Control Register and the -Restart Register. - 0 - 16 - write-only - - - - - St - Status Register - 0x1c - 32 - 0x00000000 - 0x00000001 - - - INTEXPIRED - The status of the watchdog interrupt timer -0: timer is not expired yet -1: timer is expired - 0 - 1 - write-only - - - - - - - WDG1 - WDG1 - WDOG - 0xf0094000 - - - WDG2 - WDG2 - WDOG - 0xf0098000 - - - WDG3 - WDG3 - WDOG - 0xf009c000 - - - PWDG - PWDG - WDOG - 0xf40e8000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - PTPC - PTPC - PTPC - 0xf00b0000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c0000 - - 0x0 - 0x40 - registers - - - - 16 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMA - 0xf00c4000 - - 0x10 - 0x130 - registers - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - IntStatus - Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0x00FFFFFF - - - TC - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 16 - 8 - write-only - - - ABORT - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 8 - 8 - write-only - - - ERROR - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 8 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 8 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel n Control Register - 0x0 - 32 - 0x00000000 - 0xEFFFFFFF - - - SRCBUSINFIDX - Bus interface index that source data is read from -0x0: Data is read from bus interface 0 -0x1: Data is read from bus interface - 31 - 1 - read-write - - - DSTBUSINFIDX - Bus interface index that destination data is written to -0x0: Data is written to bus interface 0 -0x1: Data is written to bus interface 1 - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6-x7: Reserved, setting this field with a reserved value triggers the error exception -for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 8 - 4 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 4 - 4 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel n Transfer Size Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 32 - read-write - - - - - SrcAddr - Channel n Source Address Low Part Register - 0x8 - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - SrcAddrH - Channel n Source Address High Part Register - 0xc - 32 - 0x00000001 - 0xFFFFFFFF - - - SRCADDRH - High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - DstAddr - Channel n Destination Address Low Part Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - DstAddrH - Channel n Destination Address High Part Register - 0x14 - 32 - 0x00000001 - 0xFFFFFFFF - - - DSTADDRH - High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - LLPointer - Channel n Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF9 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - LLDBUSINFIDX - Bus interface index that the next descriptor is read from -0x0: The next descriptor is read from bus interface 0 - 0 - 1 - read-write - - - - - LLPointerH - Channel n Linked List Pointer High Part Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - LLPOINTERH - High part of the pointer to the next descriptor. -This register exists only when the address bus width is wider than 32 bits. - 0 - 32 - read-write - - - - - - - - XDMA - XDMA - DMA - 0xf3048000 - - - RNG - RNG - RNG - 0xf00c8000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf00cc000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0100000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - write-only - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - write-only - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXD[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -5'h2: 2 channels -5'h4: 4 channels -... -5‘h10: 16 channels (max) - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXDSLOT[%s] - no description available - 0x60 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXDSLOT[%s] - no description available - 0x70 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0104000 - - - I2S2 - I2S2 - I2S - 0xf0108000 - - - I2S3 - I2S3 - I2S - 0xf010c000 - - - DAO - DAO - DAO - 0xf0110000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000200FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to consume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x000007C0 - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0114000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - write-only - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - write-only - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description available - 18 - 2 - read-write - - - CH8_TYPE - No description available - 16 - 2 - read-write - - - CH7_TYPE - No description available - 14 - 2 - read-write - - - CH6_TYPE - No description available - 12 - 2 - read-write - - - CH5_TYPE - No description available - 10 - 2 - read-write - - - CH4_TYPE - No description available - 8 - 2 - read-write - - - CH3_TYPE - No description available - 6 - 2 - read-write - - - CH2_TYPE - No description available - 4 - 2 - read-write - - - CH1_TYPE - No description available - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMAddr - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMData - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PWM0 - PWM0 - PWM - 0xf0200000 - - 0x0 - 0x290 - registers - - - - unlk - Shadow registers unlock register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHUNLK - write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, -otherwise the shadow registers can not be written. - 0 - 32 - read-write - - - - - sta - Counter start register - UNION_STA - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - XSTA - pwm timer counter extended start point, should back to this value after reach xrld - 28 - 4 - read-write - - - STA - pwm timer counter start value - sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - 4 - 24 - read-write - - - - - rld - Counter reload register - UNION_RLD - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XRLD - timeout counter extended reload point, counter will reload to xsta after reach this point - 28 - 4 - read-write - - - RLD - pwm timer counter reload value - 4 - 24 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP[%s] - no description available - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - XCMP - extended counter compare value - 28 - 4 - read-write - - - CMP - clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, -and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - 4 - 24 - read-write - - - CMPHLF - half clock counter compare value - 3 - 1 - read-write - - - CMPJIT - jitter counter compare value - 0 - 3 - read-write - - - - - frcmd - Force output mode register - 0x78 - 32 - 0x00000000 - 0x0000FFFF - - - FRCMD - 2bit for each PWM output channel (0-7); -00: force output 0 -01: force output 1 -10: output highz -11: no force - 0 - 16 - read-write - - - - - shlk - Shadow registers lock register - 0x7c - 32 - 0x00000000 - 0x80000000 - - - SHLK - write 1 to lock all shawdow register, write access is not permitted - 31 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CHCFG[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFF0003 - - - CMPSELEND - assign the last comparator for this output channel - 24 - 5 - read-write - - - CMPSELBEG - assign the first comparator for this output channel - 16 - 5 - read-write - - - OUTPOL - output polarity, set to 1 will invert the output - 1 - 1 - read-write - - - - - gcr - Global control register - 0xf0 - 32 - 0x00000000 - 0xFDFFFFE7 - - - FAULTI3EN - 1- enable the internal fault input 3 - 31 - 1 - read-write - - - FAULTI2EN - 1- enable the internal fault input 2 - 30 - 1 - read-write - - - FAULTI1EN - 1- enable the internal fault input 1 - 29 - 1 - read-write - - - FAULTI0EN - 1- enable the internal fault input 0 - 28 - 1 - read-write - - - DEBUGFAULT - 1- enable debug mode output protection - 27 - 1 - read-write - - - FRCPOL - polarity of input pwm_force, -1- active low -0- active high - 26 - 1 - read-write - - - HWSHDWEDG - When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. -This bit assign its which edge is used as compare shadow register hardware load event. -1- Falling edge -0- Rising edge - 24 - 1 - read-write - - - CMPSHDWSEL - This bitfield select one of the comparators as hardware event time to load comparator shadow registers - 19 - 5 - read-write - - - FAULTRECEDG - When hardware load is selected as output fault recover trigger and the selected channel is capture mode. -This bit assign its effective edge of fault recover trigger. -1- Falling edge -0- Rising edge - 18 - 1 - read-write - - - FAULTRECHWSEL - Selec one of the 24 comparators as fault output recover trigger. - 13 - 5 - read-write - - - FAULTE1EN - 1- enable the external fault input 1 - 12 - 1 - read-write - - - FAULTE0EN - 1- enable the external fault input 0 - 11 - 1 - read-write - - - FAULTEXPOL - external fault polarity -1-active low -0-active high - 9 - 2 - read-write - - - RLDSYNCEN - 1- pwm timer counter reset to reload value (rld) by synci is enabled - 8 - 1 - read-write - - - CEN - 1- enable the pwm timer counter -0- stop the pwm timer counter - 7 - 1 - read-write - - - FAULTCLR - 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. -User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - 6 - 1 - read-write - - - XRLDSYNCEN - 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - 5 - 1 - read-write - - - FRCTIME - This bit field select the force effective time -00: force immediately -01: force at main counter reload time -10: force at FRCSYNCI -11: no force - 1 - 2 - write-only - - - SWFRC - 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - 0 - 1 - read-write - - - - - shcr - Shadow register control register - 0xf4 - 32 - 0x00000000 - 0x00001FFF - - - FRCSHDWSEL - This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - 8 - 5 - read-write - - - CNTSHDWSEL - This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - 3 - 5 - read-write - - - CNTSHDWUPT - This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 1 - 2 - read-write - - - SHLKEN - 1- enable shadow registers lock feature, -0- disable shadow registers lock, shlk bit will always be 0 - 0 - 1 - read-write - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPPOS[%s] - no description available - 0x100 - 32 - 0x00000000 - 0xFFFFFFF0 - - - CAPPOS - counter value captured at input posedge - 4 - 28 - read-only - - - - - cnt - Counter - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CAPNEG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - cntcopy - Counter copy - 0x1f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCNT - current extended counter value - 28 - 4 - read-only - - - CNT - current clock counter value - 4 - 24 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - PWMCFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x1FFFFFFF - - - OEN - PWM output enable -1- output is enabled -0- output is disabled - 28 - 1 - read-write - - - FRCSHDWUPT - This bitfield select when the FRCMD shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 26 - 2 - read-write - - - FAULTMODE - This bitfield defines the PWM output status when fault condition happen -00: force output 0 -01: force output 1 -1x: output highz - 24 - 2 - read-write - - - FAULTRECTIME - This bitfield select when to recover PWM output after fault condition removed. -00: immediately -01: after pwm timer counter reload time -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after software write faultclr bit in GCR register - 22 - 2 - read-write - - - FRCSRCSEL - Select sources for force output -0- force output is enabled when FRCI assert -1- force output is enabled by software write swfrc to 1 - 21 - 1 - read-write - - - PAIR - 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. -0- PWM output is in indepandent mode. - 20 - 1 - read-write - - - DEADAREA - This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. -Note: user should configure pair bit and this bitfield before PWM output is enabled. - 0 - 20 - read-write - - - - - sr - Status register - 0x220 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTF - fault condition flag - 27 - 1 - write-only - - - XRLDF - extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - 26 - 1 - write-only - - - HALFRLDF - half reload flag, this flag set when cnt count to rld/2 - 25 - 1 - write-only - - - RLDF - reload flag, this flag set when cnt count to rld value or when SYNCI assert - 24 - 1 - write-only - - - CMPFX - comparator output compare or input capture flag - 0 - 24 - write-only - - - - - irqen - Interrupt request enable register - 0x224 - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTIRQE - fault condition interrupt enable - 27 - 1 - read-write - - - XRLDIRQE - extended reload flag interrupt enable - 26 - 1 - read-write - - - HALFRLDIRQE - half reload flag interrupt enable - 25 - 1 - read-write - - - RLDIRQE - reload flag interrupt enable - 24 - 1 - read-write - - - CMPIRQEX - comparator output compare or input capture flag interrupt enable - 0 - 24 - read-write - - - - - dmaen - DMA request enable register - 0x22c - 32 - 0x00000000 - 0x0FFFFFFF - - - FAULTEN - fault condition DMA request enable - 27 - 1 - read-write - - - XRLDEN - extended reload flag DMA request enable - 26 - 1 - read-write - - - HALFRLDEN - half reload flag DMA request enable - 25 - 1 - read-write - - - RLDEN - reload flag DMA request enable - 24 - 1 - read-write - - - CMPENX - comparator output compare or input capture flag DMA request enable - 0 - 24 - read-write - - - - - 24 - 0x4 - cmpcfg0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMPCFG[%s] - no description available - 0x230 - 32 - 0x00000000 - 0x000000FF - - - XCNTCMPEN - This bitfield enable the comparator to compare xcmp with xcnt. - 4 - 4 - read-write - - - CMPSHDWUPT - This bitfield select when the comparator shadow register will be loaded to its work register -00: after software set shlk bit of shlk register -01: immediately after the register being modified -10: after hardware event assert, user can select one of the comparators to generate this hardware event. - The comparator can be either output compare mode or input capture mode. -11: after SHSYNCI assert - 2 - 2 - read-write - - - CMPMODE - comparator mode -0- output compare mode -1- input capture mode - 1 - 1 - read-write - - - - - - - PWM1 - PWM1 - PWM - 0xf0210000 - - - PWM2 - PWM2 - PWM - 0xf0220000 - - - PWM3 - PWM3 - PWM - 0xf0230000 - - - HALL0 - HALL0 - HALL - 0xf0204000 - - 0x0 - 0x88 - registers - - - - cr - Control Register - 0x0 - 32 - 0x00000000 - 0x8001083F - - - READ - 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - SNAPEN - 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - 11 - 1 - read-write - - - RSTCNT - set to reset all counter and related snapshots - 4 - 1 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLYSEL - This bit select delay start time: -1- start counting delay after pre-trigger -0- start counting delay after u,v,w toggle - 31 - 1 - read-write - - - DLYCNT - delay clock cycles number - 0 - 24 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - uvwcfg - U,V,W configure register - 0xc - 32 - 0x00000000 - 0x07FFFFFF - - - PRECNT - the clock cycle number which the pre flag will set before the next uvw transition - 0 - 24 - read-write - - - - - trgoen - Trigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- enable trigger output when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- enable trigger output when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- enable trigger output when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- enable trigger output when u flag set - 23 - 1 - read-write - - - VFEN - 1- enable trigger output when v flag set - 22 - 1 - read-write - - - WFEN - 1- enable trigger output when w flag set - 21 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- load counters to their read registers when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- load counters to their read registers when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- load counters to their read registers when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- load counters to their read registers when u flag set - 23 - 1 - read-write - - - VFEN - 1- load counters to their read registers when v flag set - 22 - 1 - read-write - - - WFEN - 1- load counters to their read registers when w flag set - 21 - 1 - read-write - - - - - dmaen - DMA enable register - 0x24 - 32 - 0x00000000 - 0xFFE00000 - - - WDGEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - PHUPTEN - 1- generate dma request when phupt flag set - 30 - 1 - read-write - - - PHPREEN - 1- generate dma request when phpre flag set - 29 - 1 - read-write - - - PHDLYEN - 1- generate dma request when phdly flag set - 28 - 1 - read-write - - - UFEN - 1- generate dma request when u flag set - 23 - 1 - read-write - - - VFEN - 1- generate dma request when v flag set - 22 - 1 - read-write - - - WFEN - 1- generate dma request when w flag set - 21 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFE00000 - - - WDGF - watchdog count timeout flag - 31 - 1 - read-write - - - PHUPTF - phase update flag, will set when any of u, v, w signal toggle - 30 - 1 - read-write - - - PHPREF - phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - 29 - 1 - read-write - - - PHDLYF - phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - 28 - 1 - read-write - - - UF - u flag, will set when u signal toggle - 23 - 1 - read-write - - - VF - v flag, will set when v signal toggle - 22 - 1 - read-write - - - WF - w flag, will set when w signal toggle - 21 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x2c - 32 - 0x00000000 - 0xFFE00000 - - - WDGIE - 1- generate interrupt request when wdg flag set - 31 - 1 - read-write - - - PHUPTIE - 1- generate interrupt request when phupt flag set - 30 - 1 - read-write - - - PHPREIE - 1- generate interrupt request when phpre flag set - 29 - 1 - read-write - - - PHDLYIE - 1- generate interrupt request when phdly flag set - 28 - 1 - read-write - - - UFIE - 1- generate interrupt request when u flag set - 23 - 1 - read-write - - - VFIE - 1- generate interrupt request when v flag set - 22 - 1 - read-write - - - WFIE - 1- generate interrupt request when w flag set - 21 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - w - W counter - 0x0 - 32 - 0x00000000 - 0x0FFFFFFF - - - WCNT - wcnt counter - 0 - 28 - read-only - - - - - v - V counter - 0x4 - 32 - 0x00000000 - 0xCFFFFFFF - - - VCNT - vcnt counter - 0 - 28 - read-only - - - - - u - U counter - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - USTAT - this bit indicate U state - 30 - 1 - read-only - - - VSTAT - this bit indicate V state - 29 - 1 - read-only - - - WSTAT - this bit indicate W state - 28 - 1 - read-only - - - UCNT - ucnt counter - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMER - 32 bit free run timer - 0 - 32 - read-only - - - - - - 3 - 0x8 - u,v,w - HIS[%s] - no description available - 0x70 - - his0 - history register 0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS0 - copy of ucnt when u signal transition from 0 to 1 - 0 - 32 - read-only - - - - - his1 - history register 1 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - UHIS1 - copy of ucnt when u signal transition from 1 to 0 - 0 - 32 - read-only - - - - - - - - HALL1 - HALL1 - HALL - 0xf0214000 - - - HALL2 - HALL2 - HALL - 0xf0224000 - - - HALL3 - HALL3 - HALL - 0xf0234000 - - - QEI0 - QEI0 - QEI - 0xf0208000 - - 0x0 - 0x80 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x80077F3F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - HRSTSPD - 1- reset spdcnt when H assert - 18 - 1 - read-write - - - HRSTPH - 1- reset phcnt when H assert - 17 - 1 - read-write - - - HRSTZ - 1- reset zcnt when H assert - 16 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - ENCTYP - 00-abz; 01-pd; 10-ud; 11-reserved - 0 - 2 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0x00000000 - 0x007FFFFF - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert - 21 - 1 - read-write - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 21 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDGTO - watch dog timeout value - 0 - 31 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0x001FFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 21 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x00000000 - 0xE01FFFFF - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - PHCMP - phcnt position compare value - 0 - 21 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xF0000000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xF0000000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xF0000000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - 4 - 0x4 - spdhis0,spdhis1,spdhis2,spdhis3 - SPDHIS[%s] - no description available - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPDHIS0 - copy of spdcnt, load from spdcnt after any transition from a = low, b = low - 0 - 32 - read-only - - - - - - - QEI1 - QEI1 - QEI - 0xf0218000 - - - QEI2 - QEI2 - QEI - 0xf0228000 - - - QEI3 - QEI3 - QEI - 0xf0238000 - - - TRGM0 - TRGM0 - TRGM - 0xf020c000 - - 0x0 - 0x404 - registers - - - - 20 - 0x4 - PWM_IN0,PWM_IN1,PWM_IN2,PWM_IN3,PWM_IN4,PWM_IN5,PWM_IN6,PWM_IN7,TRGM_IN0,TRGM_IN1,TRGM_IN2,TRGM_IN3,TRGM_IN4,TRGM_IN5,TRGM_IN6,TRGM_IN7,TRGM_IN8,TRGM_IN9,TRGM_IN10,TRGM_IN11 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - 64 - 0x4 - TRGM_OUT0,TRGM_OUT1,TRGM_OUT2,TRGM_OUT3,TRGM_OUT4,TRGM_OUT5,TRGM_OUT6,TRGM_OUT7,TRGM_OUT8,TRGM_OUT9,TRGM_OUT10,TRGM_OUT11,TRGM_OUTX0,TRGM_OUTX1,PWM_SYNCI,PWM_FRCI,PWM_FRCSYNCI,PWM_SHRLDSYNCI,PWM_FAULTI0,PWM_FAULTI1,PWM_FAULTI2,PWM_FAULTI3,PWM_IN8,PWM_IN9,PWM_IN10,PWM_IN11,PWM_IN12,PWM_IN13,PWM_IN14,PWM_IN15,PWM_IN16,PWM_IN17,PWM_IN18,PWM_IN19,PWM_IN20,PWM_IN21,PWM_IN22,PWM_IN23,QEI_A,QEI_B,QEI_Z,QEI_H,QEI_PAUSE,QEI_SNAPI,HALL_U,HALL_V,HALL_W,HALL_SNAPI,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,GPTMRa_SYNCI,GPTMRa_IN2,GPTMRa_IN3,GPTMRb_SYNCI,GPTMRb_IN2,GPTMRb_IN3,CMPx_WIN,CAN_PTPC0_CAP,CAN_PTPC1_CAP - TRGOCFG[%s] - no description available - 0x100 - 32 - 0x00000000 - 0x000001FF - - - OUTINV - 1- Invert the output - 8 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 7 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 6 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 6 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - DMACFG[%s] - no description available - 0x200 - 32 - 0x00000000 - 0x0000001F - - - DMASRCSEL - This field selects one of the DMA requests as the DMA request output. - 0 - 5 - read-write - - - - - GCR - General Control Register - 0x400 - 32 - 0x00000000 - 0x00000FFF - - - TRGOPEN - The bitfield enable the TRGM outputs. - 0 - 12 - read-write - - - - - - - TRGM1 - TRGM1 - TRGM - 0xf021c000 - - - TRGM2 - TRGM2 - TRGM - 0xf022c000 - - - TRGM3 - TRGM3 - TRGM - 0xf023c000 - - - SYNT - SYNT - SYNT - 0xf0240000 - - 0x0 - 0x30 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - LCDC - LCDC - LCDC - 0xf1000000 - - 0x0 - 0x404 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFF0001F - - - SW_RST - Software reset, high active. When write 1 ,all internal logical will be reset. -0b - No action -1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - 31 - 1 - read-write - - - DISP_ON - Display panel On/Off mode. -0b - Display Off. -1b - Display On. -Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. -So a good procedure to stop and turn on the display is: -1) clr VS_BLANK status -2) assert software reset -3) de-assert software reset -4) set display off -5) check VS_BLANK status until it is asserted, -6)reset the module, change settings -7) set display on - 30 - 1 - read-write - - - LINE_PATTERN - LCDIF line output order. -000b - RGB. -001b - RBG. -010b - GBR. -011b - GRB. -100b - BRG. -101b - BGR. - 27 - 3 - read-write - - - DISP_MODE - LCDIF operating mode. -00b - Normal mode. Panel content controlled by layer configuration. -01b - Test Mode1.(BGND Color Display) -10b - Test Mode2.(Column Color Bar) -11b - Test Mode3.(Row Color Bar) - 25 - 2 - read-write - - - BGDCL4CLR - background color for clear mode when the alpha channel is 0 - 24 - 1 - read-write - - - ARQOS - ARQOS for bus fabric arbitration - 20 - 4 - read-write - - - INV_PXDATA - Indicates if value at the output (pixel data output) needs to be negated. -0b - Output is to remain same as the data inside memory -1b - Output to be negated from the data inside memory - 4 - 1 - read-write - - - INV_PXCLK - Polarity change of Pixel Clock. -0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge -1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - 3 - 1 - read-write - - - INV_HREF - Polarity of HREF -0b - HREF signal active HIGH, indicating active pixel data -1b - HREF signal active LOW - 2 - 1 - read-write - - - INV_VSYNC - Polarity of VSYNC -0b - VSYNC signal active HIGH -1b - VSYNC signal active LOW - 1 - 1 - read-write - - - INV_HSYNC - Polarity of HSYNC -0b - HSYNC signal active HIGH -1b - HSYNC signal active LOW - 0 - 1 - read-write - - - - - BGND_CL - Background Color Register - 0x4 - 32 - 0x00000000 - 0x00FFFFFF - - - R - Red component of the default color displayed in the sectors where no layer is active. - 16 - 8 - read-write - - - G - Green component of the default color displayed in the sectors where no layer is active. - 8 - 8 - read-write - - - B - Blue component of the default color displayed in the sectors where no layer is active. - 0 - 8 - read-write - - - - - DISP_WN_SIZE - Display Window Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - Sets the display size vertical resolution in pixels. - 16 - 12 - read-write - - - X - Sets the display size horizontal resolution in pixels. - 0 - 12 - read-write - - - - - HSYNC_PARA - HSYNC Config Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - 22 - 9 - read-write - - - BP - HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - 11 - 9 - read-write - - - PW - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - VSYNC_PARA - VSYNC Config Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - 22 - 9 - read-write - - - BP - VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - 11 - 9 - read-write - - - PW - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - DMA_ST - DMA Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFF00 - - - DMA_ERR - plane n axi error. W1C. - 24 - 8 - write-only - - - DMA1_DONE - Plane n frame 1 dma done. W1C. - 16 - 8 - write-only - - - DMA0_DONE - Plane n frame 0 dma done. W1C. - 8 - 8 - write-only - - - - - ST - Status Register - 0x18 - 32 - 0x00000000 - 0x0000000F - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - write-only - - - VS_BLANK - Asserted when in vertical blanking period. At the start of VSYNC - 2 - 1 - write-only - - - UNDERRUN - Asserted when the output buffer underrun condition encountered - 1 - 1 - write-only - - - VSYNC - Asserted when in vertical blanking period. At the end of VSYNC - 0 - 1 - write-only - - - - - INT_EN - Interrupt Enable Register - 0x1c - 32 - 0x00000000 - 0xFFFFFF0F - - - DMA_ERR - Interrupt enable for DMA error - 24 - 8 - read-write - - - DMA_DONE - Interrupt enable for DMA done - 16 - 8 - read-write - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - read-write - - - VS_BLANK - Interrupt enable for start of sof - 2 - 1 - read-write - - - UNDERRUN - Interrupt enable for underrun - 1 - 1 - read-write - - - VSYNC - Interrupt enable for end of sof - 0 - 1 - read-write - - - - - TXFIFO - TX FIFO Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRSH - Threshold to start the lcd raster (0--0x7F) - 0 - 8 - read-write - - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - LAYER[%s] - no description available - 0x200 - - LAYCTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x000FFFFD - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), the low byte contains the full R component. -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional blending mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - ALPHAS - Layer Alpha Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYSIZE - Layer Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYPOS - Layer Position Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - START0 - Layer Buffer Pointer Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LINECFG - Layer Bus Config Register - 0x18 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. - 0 - 16 - read-write - - - - - BG_CL - Layer Background Color Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - - CLUT_LOAD - Clut Load Control Register - 0x400 - 32 - 0x00000000 - 0x0000007F - - - SEL_NUM - Selected CLUT Number -The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. -. 3'h0 - PLANE 0 -. 3'h1 - PLANE 1 -. ------ -. 3'h7 - PLANE 7 -CLUT 8 can be modified via APB even when display is on. -Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - 4 - 3 - read-write - - - UPDATE_EN - CLUT Update Enable -The bit is written to 1 when software want to update the Color Look Up Tables during display. -If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. -If set to 0, software can update CLUT8 directly according to the CLUT memory map. -Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - 0 - 1 - read-write - - - - - - - CAM0 - CAM0 - CAM - 0xf1008000 - - 0x0 - 0x490 - registers - - - - CR1 - Control Register - 0x0 - 32 - 0x00000000 - 0xBF9AAFFF - - - COLOR_EXT - If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. -The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - 29 - 1 - read-write - - - INV_PIXCLK - invert pixclk pad input before it is used - 28 - 1 - read-write - - - INV_HSYNC - invert hsync pad input before it is used - 27 - 1 - read-write - - - INV_VSYNC - invert vsync pad input before it is used - 26 - 1 - read-write - - - SWAP16_EN - SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. -NOTE: Example of swapping enabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x 33441122 -NOTE: Example of swapping disabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x11223344 -0 Disable swapping -1 Enable swapping - 25 - 1 - read-write - - - PACK_DIR - Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. -0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. -1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - 24 - 1 - read-write - - - RESTART_BUSPTR - force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - 23 - 1 - read-write - - - ASYNC_RXFIFO_CLR - ASynchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO immediately. -It will be auto-cleared. - 20 - 1 - read-write - - - SYNC_RXFIFO_CLR - Synchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO on every SOF. - 19 - 1 - read-write - - - SOF_INT_POL - SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. -0 SOF interrupt is generated on SOF falling edge -1 SOF interrupt is generated on SOF rising edge - 17 - 1 - read-write - - - INV_DATA - Invert Data Input. This bit enables or disables internal inverters on the data lines. -0 CAM_D data lines are directly applied to internal circuitry -1 CAM_D data lines are inverted before applied to internal circuitry - 15 - 1 - read-write - - - STORAGE_MODE - 00: Normal Mode (one plane mode) -01: Two Plane Mode (Y, UV plane) -10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 -11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - 10 - 2 - read-write - - - COLOR_FORMATS - input color formats: -0010b:24bit:RGB888 -0011b:24bit:RGB666 -0100b:16bit:RGB565 -0101b:16bit:RGB444 -0110b:16bit:RGB555 -0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) -YUV -YCrCb -Note: YUV420 is not supported. -1000b: 24bit: YUV444 - 3 - 4 - read-write - - - SENSOR_BIT_WIDTH - the bit width of the sensor -0: 8 bits -1: 10 bits -3:24bits -Others: Undefined - 0 - 3 - read-write - - - - - INT_EN - Interrupt Enable Register - 0x4 - 32 - 0x00000000 - 0xFFFFFF5F - - - ERR_CL_BWID_CFG_INT_EN - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - 13 - 1 - read-write - - - HIST_DONE_INT_EN - Enable hist done int - 12 - 1 - read-write - - - HRESP_ERR_EN - Hresponse Error Enable. This bit enables the hresponse error interrupt. -0 Disable hresponse error interrupt -1 Enable hresponse error interrupt - 11 - 1 - read-write - - - EOF_INT_EN - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. -0 EOF interrupt is disabled. -1 EOF interrupt is generated when RX count value is reached. - 9 - 1 - read-write - - - RF_OR_INTEN - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. -0 RxFIFO overrun interrupt is disabled -1 RxFIFO overrun interrupt is enabled - 6 - 1 - read-write - - - FB2_DMA_DONE_INTEN - Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA -transfer done. -0 Frame Buffer2 DMA Transfer Done interrupt disable -1 Frame Buffer2 DMA Transfer Done interrupt enable - 3 - 1 - read-write - - - FB1_DMA_DONE_INTEN - Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA -transfer done. -0 Frame Buffer1 DMA Transfer Done interrupt disable -1 Frame Buffer1 DMA Transfer Done interrupt enable - 2 - 1 - read-write - - - SOF_INT_EN - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. -0 SOF interrupt disable -1 SOF interrupt enable - 0 - 1 - read-write - - - - - CR2 - Control 2 Register - 0x10 - 32 - 0x00000000 - 0xFFFF8FEF - - - FRMCNT_15_0 - Frame Counter. This is a 16-bit Frame Counter -(Wraps around automatically after reaching the maximum) - 16 - 16 - read-only - - - FRMCNT_RST - Frame Count Reset. Resets the Frame Counter. -0 Do not reset -1 Reset frame counter immediately - 15 - 1 - read-write - - - RXFF_LEVEL - RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. -000 4 Double words -001 8 Double words -010 16 Double words -011 24 Double words -100 32 Double words -101 48 Double words -110 64 Double words -111 96 Double words - 9 - 3 - read-write - - - DMA_REQ_EN_RFF - DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. -0 Disable the dma request -1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - 5 - 1 - read-write - - - CLRBITFORMAT - Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - 0 - 4 - read-write - - - - - STA - Status Register - 0x24 - 32 - 0x00000000 - 0xFFFFA7FC - - - ERR_CL_BWID_CFG - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - 19 - 1 - write-only - - - HIST_DONE - hist cal done - 18 - 1 - write-only - - - RF_OR_INT - RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing -1) -0 RXFIFO has not overflowed. -1 RXFIFO has overflowed. - 13 - 1 - write-only - - - DMA_TSF_DONE_FB2 - DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 10 - 1 - write-only - - - DMA_TSF_DONE_FB1 - DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 9 - 1 - write-only - - - EOF_INT - End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) -0 EOF is not detected. -1 EOF is detected. - 7 - 1 - write-only - - - SOF_INT - Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) -0 SOF is not detected. -1 SOF is detected. - 6 - 1 - write-only - - - HRESP_ERR_INT - Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing -1) -0 No hresponse error. -1 Hresponse error is detected. - 2 - 1 - write-only - - - - - DMASA_FB1 - Pixel DMA Frame Buffer 1 Address - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer1 - 2 - 30 - read-write - - - - - DMASA_FB2 - Pixel DMA Frame Buffer 2 Address - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer2 - 2 - 30 - read-write - - - - - BUF_PARA - Buffer Parameters Register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINEBSP_STRIDE - Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. -The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - 0 - 16 - read-write - - - - - IDEAL_WN_SIZE - Ideal Image Size Register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Image Height. Indicates how many active pixels in a column of the image from the sensor. - 16 - 16 - read-write - - - WIDTH - Image Width. Indicates how many active pixels in a line of the image from the sensor. -The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. -As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - 0 - 16 - read-write - - - - - CR18 - Control CR18 Register - 0x4c - 32 - 0x00000000 - 0xFFFFE7BF - - - CAM_ENABLE - CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - 31 - 1 - read-write - - - AWQOS - AWQOS for bus fabric arbitration - 7 - 4 - read-write - - - - - DMASA_UV1 - Pixel UV DMA Frame Buffer 1 Address - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 1 - 2 - 30 - read-write - - - - - DMASA_UV2 - Pixel UV DMA Frame Buffer 2 Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 2 - 2 - 30 - read-write - - - - - CR20 - Control CR20 Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - BINARY_EN - binary picture output enable - 31 - 1 - read-write - - - HISTOGRAM_EN - histogarm enable - 30 - 1 - read-write - - - BIG_END - Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - 8 - 1 - read-write - - - THRESHOLD - Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - 0 - 8 - read-write - - - - - CSC_COEF0 - Color Space Conversion Config Register 0 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Color Space Conversion Config Register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Color Space Conversion Config Register 2 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - CLRKEY_LOW - Low Color Key Register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - High Color Key Register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - 256 - 0x4 - DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23,DATA24,DATA25,DATA26,DATA27,DATA28,DATA29,DATA30,DATA31,DATA32,DATA33,DATA34,DATA35,DATA36,DATA37,DATA38,DATA39,DATA40,DATA41,DATA42,DATA43,DATA44,DATA45,DATA46,DATA47,DATA48,DATA49,DATA50,DATA51,DATA52,DATA53,DATA54,DATA55,DATA56,DATA57,DATA58,DATA59,DATA60,DATA61,DATA62,DATA63,DATA64,DATA65,DATA66,DATA67,DATA68,DATA69,DATA70,DATA71,DATA72,DATA73,DATA74,DATA75,DATA76,DATA77,DATA78,DATA79,DATA80,DATA81,DATA82,DATA83,DATA84,DATA85,DATA86,DATA87,DATA88,DATA89,DATA90,DATA91,DATA92,DATA93,DATA94,DATA95,DATA96,DATA97,DATA98,DATA99,DATA100,DATA101,DATA102,DATA103,DATA104,DATA105,DATA106,DATA107,DATA108,DATA109,DATA110,DATA111,DATA112,DATA113,DATA114,DATA115,DATA116,DATA117,DATA118,DATA119,DATA120,DATA121,DATA122,DATA123,DATA124,DATA125,DATA126,DATA127,DATA128,DATA129,DATA130,DATA131,DATA132,DATA133,DATA134,DATA135,DATA136,DATA137,DATA138,DATA139,DATA140,DATA141,DATA142,DATA143,DATA144,DATA145,DATA146,DATA147,DATA148,DATA149,DATA150,DATA151,DATA152,DATA153,DATA154,DATA155,DATA156,DATA157,DATA158,DATA159,DATA160,DATA161,DATA162,DATA163,DATA164,DATA165,DATA166,DATA167,DATA168,DATA169,DATA170,DATA171,DATA172,DATA173,DATA174,DATA175,DATA176,DATA177,DATA178,DATA179,DATA180,DATA181,DATA182,DATA183,DATA184,DATA185,DATA186,DATA187,DATA188,DATA189,DATA190,DATA191,DATA192,DATA193,DATA194,DATA195,DATA196,DATA197,DATA198,DATA199,DATA200,DATA201,DATA202,DATA203,DATA204,DATA205,DATA206,DATA207,DATA208,DATA209,DATA210,DATA211,DATA212,DATA213,DATA214,DATA215,DATA216,DATA217,DATA218,DATA219,DATA220,DATA221,DATA222,DATA223,DATA224,DATA225,DATA226,DATA227,DATA228,DATA229,DATA230,DATA231,DATA232,DATA233,DATA234,DATA235,DATA236,DATA237,DATA238,DATA239,DATA240,DATA241,DATA242,DATA243,DATA244,DATA245,DATA246,DATA247,DATA248,DATA249,DATA250,DATA251,DATA252,DATA253,DATA254,DATA255 - HISTOGRAM_FIFO[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - - - CAM1 - CAM1 - CAM - 0xf100c000 - - - PDMA - PDMA - PDMA - 0xf1010000 - - 0x0 - 0xc0 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARQOS - QoS for AXI read bus - 19 - 4 - read-write - - - AWQOS - QoS for AXI write bus - 15 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 13 - 2 - read-write - - - AXIERR_IRQ_EN - Enable interrupt of AXI bus error - 12 - 1 - read-write - - - PDMA_DONE_IRQ_EN - Enable interrupt of PDMA_DONE - 11 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - IRQ_EN - Enable normal interrupt - 6 - 1 - read-write - - - BS16 - Asserted when the Block Size is 16x16, else 8x8 - 5 - 1 - read-write - - - P1_EN - Plane 1 Enable - 4 - 1 - read-write - - - P0_EN - Plane 0 Enable - 3 - 1 - read-write - - - PDMA_SFTRST - Software Reset. -Write 1 to clear PDMA internal logic. -Write 0 to exit software reset mode. - 1 - 1 - read-write - - - PDMA_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKY - Y block that is processing - 24 - 8 - read-only - - - BLOCKX - X block that is processing - 16 - 8 - read-only - - - PDMA_DONE - PDMA one image done - 9 - 1 - write-only - - - AXI_ERR_ID - AXI error ID - 5 - 4 - read-only - - - AXI_0_WRITE_ERR - AXI0 write err - 4 - 1 - write-only - - - AXI_1_READ_ERR - AXI1 read err - 3 - 1 - write-only - - - AXI_0_READ_ERR - AXI0 read err - 2 - 1 - write-only - - - IRQ - Asserted to indicate a IRQ event - 0 - 1 - read-only - - - - - OUT_CTRL - Out Layer Control Register - 0x8 - 32 - 0x00000000 - 0xFFFFFF3F - - - DSTALPHA - The destination (P1) system ALPHA value. - 24 - 8 - read-write - - - SRCALPHA - The source (P0) system ALPHA value. - 16 - 8 - read-write - - - DSTALPHA_OP - The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) -2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 14 - 2 - read-write - - - SRCALPHA_OP - The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) -2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream -Others: Reserved - 12 - 2 - read-write - - - ABLEND_MODE - Alpha Blending Mode -0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional belding mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 8 - 4 - read-write - - - FORMAT - Output buffer format. -0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - 0 - 6 - read-write - - - - - OUT_BUF - Output buffer address - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - 0 - 32 - read-write - - - - - OUT_PITCH - Outlayer Pitch Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - OUT_LRC - Output Lower Right Corner Register - 0x18 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. -The value is the height of the output image size. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. -Should be the width of the output image size. - 0 - 14 - read-write - - - - - 2 - 0x8 - 0,1 - OUT_PS[%s] - no description available - 0x1c - - ULC - Layer Upper Left Corner Register - 0x0 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - LRC - Layer Lower Right Corner Register - 0x4 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - - 2 - 0x30 - 0,1 - PS[%s] - no description available - 0x30 - - CTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x001FFFFF - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack_dir operation. - 20 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 18 - 2 - read-write - - - BKGCL4CLR - Enable to use background color for clear area - 17 - 1 - read-write - - - YCBCR_MODE - YCbCr mode or YUV mode - 16 - 1 - read-write - - - BYPASS - Asserted to bypass the CSC stage - 15 - 1 - read-write - - - VFLIP - Indicates that the input should be flipped vertically (effect applied before rotation). - 14 - 1 - read-write - - - HFLIP - Indicates that the input should be flipped horizontally (effect applied before rotation). - 13 - 1 - read-write - - - ROTATE - Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring -after the FLIP_X and FLIP_Y permutation. -0x0 ROT_0 -0x1 ROT_90 -0x2 ROT_180 -0x3 ROT_270 - 11 - 2 - read-write - - - DECY - Verticle pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECY2 - Decimate PS by 2. -0x2 DECY4 - Decimate PS by 4. -0x3 DECY8 - Decimate PS by 8. - 9 - 2 - read-write - - - DECX - Horizontal pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECX2 - Decimate PS by 2. -0x2 DECX4 - Decimate PS by 4. -0x3 DECX8 - Decimate PS by 8. - 7 - 2 - read-write - - - HW_BYTE_SWAP - Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - 6 - 1 - read-write - - - FORMAT - PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. -0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - 0 - 6 - read-write - - - - - BUF - Layer data buffer address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Address pointer for the PS RGB or Y (luma) input buffer. - 0 - 32 - read-write - - - - - PITCH - Layer data pitch register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - BKGD - Layer background color register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COLOR - Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - 0 - 32 - read-write - - - - - SCALE - Layer scale register - 0x18 - 32 - 0x00000000 - 0x7FFF7FFF - - - Y - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 16 - 15 - read-write - - - X - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 0 - 15 - read-write - - - - - OFFSET - Layer offset register - 0x1c - 32 - 0x00000000 - 0x0FFF0FFF - - - Y - This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 16 - 12 - read-write - - - X - This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 0 - 12 - read-write - - - - - CLRKEY_LOW - Layer low color key register - 0x20 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - Layer high color key register - 0x24 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - 0 - 24 - read-write - - - - - ORG - Layer original size register - 0x28 - 32 - 0x00000000 - 0x3FFF3FFF - - - HIGHT - The number of vertical pixels of the original frame (not -1) - 16 - 14 - read-write - - - WIDTH - The number of horizontal pixels of the original frame (not -1) - 0 - 14 - read-write - - - - - - YUV2RGB_COEF0 - YUV2RGB coefficients register 0 - 0xa0 - 32 - 0x00000000 - 0x1FFFFFFF - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - YUV2RGB_COEF1 - YUV2RGB coefficients register 1 - 0xa4 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - YUV2RGB_COEF2 - YUV2RGB coefficients register 2 - 0xa8 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients register 0 - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YUV CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients register 1 - 0xb0 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients register 2 - 0xb4 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients register 3 - 0xb8 - 32 - 0x00000000 - 0x07FF07FF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients register 4 - 0xbc - 32 - 0x00000000 - 0x07FF07FF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - - - JPEG - JPEG - JPEG - 0xf1014000 - - 0x0 - 0xa0 - registers - - - - InDMA_MISC - In DMA Misc Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFC - - - ARQOS - QoS for AXI read channel - 19 - 4 - read-write - - - MAX_OT - max_ot when input are RGB pixels. -For 16 bits per pixel, it can be set as 4. -For 32 bits per pixel, it will be set as 2. - 15 - 4 - read-write - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - 14 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - INDMA_RENEW - Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - 11 - 1 - read-write - - - NXT_IRQ_EN - In DMA Next Interrupt Enable - 10 - 1 - read-write - - - IN_DMA_DONE_IRQ_EN - In DMA Done enable - 9 - 1 - read-write - - - AXI_ERR_IRQ_EN - In DMA axi bus error inetrrupt enable - 8 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of In DMA module - 7 - 1 - read-write - - - IN_DMA_ID - 0: Pixel (In) -1: ECS (In) -2: Qmem -3: HuffEnc -4: HuffMin -5: HuffBase -6: HuffSymb - 4 - 3 - read-write - - - IN_DMA_REQ - Asserted to request DMA. Automatically clear after DMA is done. - 3 - 1 - read-write - - - INDMA2D - Asserted if In_DMA_ID=Pixel. - 2 - 1 - read-write - - - - - InDMABase - In DMA Buf Address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - InDMA_Ctrl0 - In DMA Buf Control 0 Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - 0 - 16 - read-write - - - - - InDMA_Ctrl1 - In DMA Buf Control 1 Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - INXT_CMD - In DMA Next Command Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - OutDMA_MISC - Out DMA Misc Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFC - - - AWQOS - No description available - 14 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. -2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - EN_OUTCNT - Enable output counter (unit as bytes) - 11 - 1 - read-write - - - INI_OUTCNT - Asserted to ini output counter - 10 - 1 - read-write - - - ADD_ODMA_ENDINGS - Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - 9 - 1 - read-write - - - NXT_IRQ_EN - Out DMA Next Interrupt Enable - 8 - 1 - read-write - - - OUT_DMA_DONE_IRQ_EN - Out DMA Done interrupt Enable - 7 - 1 - read-write - - - AXI_ERR_IRQ_EN - Out DMA axi bus error inetrrupt enable - 6 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of Out DMA module - 5 - 1 - read-write - - - OUT_DMA_ID - 0: Pixel (Out) -1: ECS (Out) - 4 - 1 - read-write - - - OUT_DMA_REQ - Asserted to enable Out DMA request - 3 - 1 - read-write - - - OUTDMA2D - Asserted if Out_DMA_ID==Pixel - 2 - 1 - read-write - - - - - OutDMABase - Out DMA Buf Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - OutDMA_Ctrl0 - Out DMA Buf Control 0 Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows when Out_DMA_ID==Pixel - 0 - 16 - read-write - - - - - OutDMA_Ctrl1 - Out DMA Buf Control 1 Register - 0x30 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - ONXT_CMD - Out DMA Next Command Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - CFG - Configuration Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - JD_UVSWAP - Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - 22 - 1 - read-write - - - CFG_IPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as B,R -2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - 20 - 2 - read-write - - - CODEC_OVER_IRQ_EN - The jpg endec process done interrupt enable - 19 - 1 - read-write - - - CODEC_RESTART_ERR_IRQ_EN - The jpg endec restart error interrupt enable - 18 - 1 - read-write - - - MEM_DEBUG_CLK_SEL - asserted to use APB clock, so that the memory contents could be read out through APB interface - 17 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - CFG_OPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as R,B -2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - 7 - 2 - read-write - - - JDATA_FORMAT - 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU -3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU -3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU -3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU -3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU -Others: Undefined - 4 - 3 - read-write - - - JPEG_SFTRST - Software Reset - 3 - 1 - read-write - - - START - Asserted if to start a new encoder/decoder conversion. -It will at first stop the inner JPEG module, then reset it, and then re-run it. -It is a different mode from DMA phase mode. -It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. -Auto clear. - 2 - 1 - read-write - - - MODE - 1: decoder, 0:encoder - 1 - 1 - read-write - - - JPEG_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x44 - 32 - 0x00000000 - 0xFFFFBFFE - - - BUSY - When 1 means that the module is busy doing conversion and data transfer. - 31 - 1 - read-only - - - AXI_ERR_ID - the axi err id - 10 - 4 - read-only - - - AXI_READ_ERR - in-dma axi bus error - 9 - 1 - read-only - - - AXI_WRITE_ERR - out-dma axi bus error - 8 - 1 - read-only - - - AXI_ERR - axi bus error - 7 - 1 - write-only - - - ONXT_IRQ - OutDMA next interrupt - 6 - 1 - write-only - - - INXT_IRQ - InDMA next interrupt - 5 - 1 - write-only - - - OUT_DMA_TRANSFER_DONE - OutDMA process done - 4 - 1 - write-only - - - IN_DMA_TRANSFER_DONE - InDMA process done - 3 - 1 - write-only - - - CODEC_OVER - Coding or decoding process is over. DMA is not included. -The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - 2 - 1 - write-only - - - RESTART_MARKER_ERROR - codec restart marker error interrupt - 1 - 1 - write-only - - - - - Width - Image width register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - Height - Image height register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - BufAddr - Buf Access Addr - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - ADDR[31:28] denotes the buffer type: -0x2: Qmem -0x3: HuffEnc -0x4: HuffMin -0x5: HuffBase -0x6: HuffSymb -ADDR[27:0] is the address inside the buffer - 0 - 32 - read-write - - - - - BufData - Buf Access Data - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer. -The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - 0 - 32 - read-write - - - - - OutDMACnt - Out DMA Bytes Counter - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The out DMA counter - 0 - 32 - read-only - - - - - CSC_COEF0 - YUV2RGB coefficients Register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit. -0b - The CSC is bypassed -1b - The CSC is enabled - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - YUV2RGB coefficients Register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - YUV2RGB coefficients Register 2 - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients Register 0 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode. Must be assigned as 1. - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YCbCr CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients Register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients Register 2 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients Register 3 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients Register 4 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - ImgReg1 - Image Control Register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFF7 - - - RE - Encoder Use only. -Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - 2 - 1 - read-write - - - NCOL - Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - 0 - 2 - read-write - - - - - ImgReg2 - Image Control Register 2 - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - NMCU - Encoder Use only. -The number of NMCU to be generated in encoder mode - 0 - 26 - read-write - - - - - ImgReg3 - Image Control Register 3 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - NRST - Encoder use only. -It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - 0 - 16 - read-write - - - - - 4 - 0x4 - Reg40,Reg41,Reg42,Reg43 - IMGREG[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - - - ENET0 - ENET0 - ENET - 0xf2000000 - - 0x0 - 0x1058 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. -Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -Note: - Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, -that is, the current frame does not use the updated value. -- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. -When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. -When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. -When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. -This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - or SGMII port. When this bit is reset, no such information is driven to the PHY. -This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. -When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). -Lower values are not considered. -In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. -When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. -In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, -this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. -This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. -This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. -In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. -In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. -When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. -This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. -The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. -It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) -of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. -The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) -and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). -When this bit is reset, this function is disabled. -When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. -When a collision occurs on the GMII or MII interface, -the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. -When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. -All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. -When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays - (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. -This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. -The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, -when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, -but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. -For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, -the transmitter transmits and collision happens. -Because of collision, the transmitter needs to back off and then defer again after back off completion. -In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, -the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. -The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, -the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. -When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, -this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. -When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. -When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. -When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. -The following conditions should be true for the Pause frames processing: -- Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. -- Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. -- Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. -Note: This field should be set to 01 only when the Condition 1 is true, -that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. -Otherwise, the Pause frame filtering may be inconsistent. -When Condition 1 is false, the Pause frames are considered as generic control frames. -Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, -you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. -When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. -When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. -When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, -the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. -When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. -The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. -The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) -ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved -When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. -For example, -when CSR clock is of 100 MHz frequency and you program these bits as 1010, -then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. -Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, -it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. -During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - Register 5 is invalid until this bit is cleared by the MAC. -Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. -Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. -The subsequent read or write operation should happen only after the previous operation is complete. -Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, -there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation -or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. -If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of -the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). -When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. -The threshold values should be always less than the Pause Time configured in Bits[31:16]. - For example, if PT = 100H (256 slot-times), and PLT = 01, -then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. -The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. -When this bit is set, the MAC can also detect Pause frames with unicast address of the station. -This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. -When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. -When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. -In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. -In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - To initiate a Pause frame, the Application must set this bit to 1'b1. -During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. -After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. -The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, -when this bit is set (and TFE is set), then backpressure is asserted by the MAC. -During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. -This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. -When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). -A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. -When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, -the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, -only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. -When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. -The following list describes the bits of this field: - - Bits [15:13]: User Priority -- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) -- Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). -The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. -The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. -Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, -the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. -This bit is then self-cleared and the power-down mode is disabled. -The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. -The frames, received by the MAC after this bit is cleared, are forwarded to the application. -This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. -Note: You can gate-off the CSR clock during the power-down mode. -However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Register - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. -This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, -the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. -The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. -If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), -when the MAC is in the LPI mode, the MAC exits the LPI mode. -When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. -When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. -When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. -This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. -This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. -The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - the LPI pattern to the PHY and before it resumes the normal transmission. -The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. -This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. -This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: -- The system time value equals or exceeds the value specified in the Target Time High and Low registers. -- There is an overflow in the seconds register. - - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). -This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). -This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is RO. The bit value is fixed at 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - 4 - 0x8 - 1,2,3,4 - MAC_ADDR[%s] - no description available - 0x48 - - HIGH - MAC Address High Register - 0x0 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. -When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. -Each bit controls the masking of the bytes as follows: -- Bit 29: Register 18[15:8] -- Bit 28: Register 18[7:0] -- Bit 27: Register 19[31:24] - -... -- Bit 24: Register 19[7:0] -You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - LOW - MAC Address Low Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0000003F - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. -It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. -The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. -When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -this field is used as watchdog timeout for a received frame. - If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. -Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). -Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - mmc_cntrl - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. -This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. -Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - mmc_intr_rx - MMC Receive Interrupt - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_tx - MMC Transmit Interrupt - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_mask_rx - MMC Receive Interrupt mask - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - mmc_intr_mask_tx - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - tx64octets_gb - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx65to127octets_gb - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx128to255octets_gb - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx256to511octets_gb - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx512to1023octets_gb - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx1024tomaxoctets_gb - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - rxframecount_gb - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - mmc_ipc_intr_mask_rx - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_ipc_intr_rx - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - rxipv4_gd_fms - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - 1 - 0x20 - 0 - L3_L4_CFG[%s] - no description available - 0x400 - - L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x0 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. -When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. -This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. -When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. -The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, -which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. -The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. -This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. -When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. -Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. -This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. -When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. -The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L4_Addr - Layer 4 Address Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_Addr_0 - Layer 3 Address 0 Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_1 - Layer 3 Address 1 Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_2 - Layer 3 Address 2 Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_Addr_3 - Layer 3 Address 3 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. -This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). -Note: Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - When reset, the rollover value of sub-second register is 0x7FFF_FFFF. -The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. -This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. -This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the initialization is complete. -The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. -You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. -For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) -when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. -When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. -In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Target Time Registers when this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). -This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. -The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. -These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. -This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. -This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. -When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. -These bits are applicable only if the number of Auxiliary snapshots is more than one. -One bit is assigned for each trigger as shown in the following list: -- Bit 16: Auxiliary trigger 0 -- Bit 17: Auxiliary trigger 1 -- Bit 18: Auxiliary trigger 2 -- Bit 19: Auxiliary trigger 3 - The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description available - 7 - 1 - read-only - - - TSTARGT2 - No description available - 6 - 1 - read-only - - - TSTRGTERR1 - No description available - 5 - 1 - read-only - - - TSTARGT1 - No description available - 4 - 1 - read-only - - - TSTRGTERR - No description available - 3 - 1 - read-only - - - AUXTSTRIG - No description available - 2 - 1 - read-only - - - TSTARGT - No description available - 1 - 1 - read-only - - - TSSOVF - No description available - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - write-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - write-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - write-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. -The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. -For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. -Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. -In the digital rollover mode, the PPS output frequency is an average number. -The actual clock is of different frequency that gets synchronized every second. For example: -- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms -- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - - One clock of 50 percent duty cycle and 537 ms period - - Second clock of 463 ms period (268 ms low and 195 ms high) -- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - - Three clocks of 50 percent duty cycle and 268 ms period - - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-only - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-only - - - - - PPS0_INTERVAL - PPS Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if the PTP reference clock is 50 MHz (period of 20ns), -and desired interval between rising edges of PPS0 signal output is 100ns - (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - 3 - 0x20 - 1,2,3 - PPS[%s] - no description available - 0x780 - - TGTTM_SEC - PPS Target Time Seconds Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Targeers wht Time Registen this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - INTERVAL - PPS Interval Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), -then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - WIDTH - PPS Width Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, - if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), -then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. -The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. -By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), -whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, -the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. -Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. -The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. -When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. -This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. -When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. -When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. -PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. -Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. -If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). -This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. -The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. -This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: -- Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. -When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. -The address skipping starts from the end of current descriptor to the start of next descriptor. -When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. -It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. -Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. -Note: - The Software reset function is driven only by this bit. -Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. -- The reset operation is completed only when all resets in all active clock domains are de-asserted. -Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. -The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. -The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. -The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. -To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. -Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. -When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. --or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. -To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. -Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. -Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. -This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. - The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the Power Management feature is enabled. -Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac -to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): -- PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event -- SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - read any of the following corresponding registers: -- PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) -- SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) -- General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in -Register 7 (Interrupt Enable Register): -- Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt -- Register 5[14]: Early Receive Interrupt Only unmasked bits - (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following -when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive FIFO Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt -- Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. -This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. -The Receive Process is suspended. To resume processing Receive descriptors, - the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. -This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. -When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, -and the specific frame status information is updated in the descriptor. -The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). -When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. -To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. -When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, -this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. -This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. -When this bit is set, the TTC values specified in Bits [16:14] are ignored. -This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. -This bit is cleared internally when the flushing operation is complete. -The Operation Mode register should not be written to until this bit is cleared. -The data which is already accepted by the MAC transmitter is not flushed. -It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. - Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. -In addition, full frames with a length less than the threshold are also transmitted. - These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -Descriptor acquisition is attempted either from the current position in the list, -which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), -or from the position retained when transmission was stopped previously. - If the DMA does not own the current descriptor, -transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Transmission command is effective only when transmission is stopped. -If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - then the DMA behavior is unpredictable. When this bit is reset, -the transmission process is placed in the Stopped state after completing the transmission of the current frame. -The Next Descriptor position in the Transmit List is saved, -and it becomes the current position when transmission is restarted. -To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. -The new value is considered when this bit is set again. -The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB -The de-assertion is effective only after flow control is asserted. - If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. -These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) -These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. -These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, -an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. -These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. -Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, -the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. -When reset, the flow control operation is disabled. - This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). -However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), -then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, -the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. -When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. -If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, -then the frame is dropped irrespective of the FEF bit setting. -However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. -Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: -- The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - - The advanced timestamp feature is not selected but the extended status is selected. -The extended status is available with the following features: -- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations -- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC -When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, -that is, frames that are larger than the computed giant frame limit. -When reset, the MAC does not drop the giant frames in the Rx FIFO. -Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: -- Configurations in which IP Checksum Offload (Type 1) is selected in Rx -- Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format -- Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. -Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. -In addition, full frames with length less than the threshold are automatically transferred. -The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. -These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. -The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. -The descriptor acquisition is attempted from the current position in the list, -which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. -If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Receive command is effective only when the reception has stopped. - If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. -When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. -The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. -The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. -When this bit is reset, normal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): - - Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt - - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. -When this bit is reset, the abnormal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt - - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, -that is, the Rx FIFO overflows with the overflow frame counter at maximum value. -In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, -that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. -This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. -The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer -of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. -When the watchdog timer runs out, the RI bit is set and the timer is stopped. -The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. -When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. -When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. -Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. -Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. -When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). -When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). -- When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. -- When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. -If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - - - ENET1 - ENET1 - ENET - 0xf2004000 - - - NTMR0 - NTMR0 - GPTMR - 0xf2010000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x80007FFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - NTMR1 - NTMR1 - GPTMR - 0xf2014000 - - - GPTMR0 - GPTMR0 - GPTMR - 0xf3000000 - - - GPTMR1 - GPTMR1 - GPTMR - 0xf3004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf3008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf300c000 - - - GPTMR4 - GPTMR4 - GPTMR - 0xf3010000 - - - GPTMR5 - GPTMR5 - GPTMR - 0xf3014000 - - - GPTMR6 - GPTMR6 - GPTMR - 0xf3018000 - - - GPTMR7 - GPTMR7 - GPTMR - 0xf301c000 - - - PTMR - PTMR - GPTMR - 0xf40e0000 - - - USB0 - USB0 - USB - 0xf2020000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFEB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 8 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - USB1 - USB1 - USB - 0xf2024000 - - - SDXC0 - SDXC0 - SDXC - 0xf2030000 - - 0x0 - 0x548 - registers - - - - SDMASA - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description available - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description available - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. -If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - 4 - 0x4 - RESP01,RESP23,RESP45,RESP67 - RESP[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - 0 - 32 - read-only - - - - - BUF_DATA - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description available - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description available - 0x28 - 32 - 0x00000000 - 0x070F0F3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - SD_BUS_PWR_VDD1 - SD Bus Power for VDD1 -This bit enables VDD1 power of the card. -This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. -Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. -In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. -Values: -0x0 (OFF): Power off -0x1 (ON): Power on - 8 - 1 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description available - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description available - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgment Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. -If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description available - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description available - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description available - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description available - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description available - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description available - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description available - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description available - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description available - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - 9 - 0x2 - INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 - PRESET[%s] - no description available - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description available - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description available - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description available - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description available - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description available - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description available - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description available - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description available - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description available - 0 - 1 - read-write - - - - - CQCTL - No description available - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description available - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description available - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description available - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description available - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description available - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description available - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description available - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description available - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description available - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description available - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description available - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description available - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description available - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description available - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description available - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description available - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description available - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description available - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description available - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description available - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description available - 0 - 32 - read-only - - - - - EMMC_BOOT_CTRL - No description available - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description available - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description available - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - - - SDXC1 - SDXC1 - SDXC - 0xf2034000 - - - CONCTL - CONCTL - CONCTL - 0xf2040000 - - 0x0 - 0x18 - registers - - - - ctrl0 - No description available - 0x0 - 32 - 0x00000000 - 0xFF0FFFFF - - - ENET1_RXCLK_DLY_SEL - No description available - 15 - 5 - read-write - - - ENET1_TXCLK_DLY_SEL - No description available - 10 - 5 - read-write - - - ENET0_RXCLK_DLY_SEL - No description available - 5 - 5 - read-write - - - ENET0_TXCLK_DLY_SEL - No description available - 0 - 5 - read-write - - - - - ctrl2 - No description available - 0x8 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - ENET0 LPI IRQ Enable - 29 - 1 - read-write - - - ENET0_REFCLK_OE - No description available - 19 - 1 - read-write - - - ENET0_PHY_INTF_SEL - 000:Reserved -001:RGMII -100:RMII -111:Reserved - 13 - 3 - read-write - - - ENET0_FLOWCTRL - No description available - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - default to use internal clk. -set from pad， two option here: - internal 50MHz clock out to pad then in; - use external clock; - 10 - 1 - read-write - - - - - ctrl3 - No description available - 0xc - 32 - 0x00000000 - 0x2008F400 - - - ENET1_LPI_IRQ_EN - ENET1 LPI Interrupt Enable - 29 - 1 - read-write - - - ENET1_REFCLK_OE - No description available - 19 - 1 - read-write - - - ENET1_PHY_INTF_SEL - No description available - 13 - 3 - read-write - - - ENET1_FLOWCTRL - No description available - 12 - 1 - read-write - - - ENET1_RMII_TXCLK_SEL - No description available - 10 - 1 - read-write - - - - - ctrl4 - No description available - 0x10 - 32 - 0x00000000 - 0xDFFFF800 - - - SDXC0_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC0_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC0_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC0_GPR_TUNING_CARD_CLK_SEL - for card clock DLL, default 0 - 23 - 5 - read-write - - - SDXC0_GPR_TUNING_STROBE_SEL - for strobe DLL, default 7taps(1ns) - 18 - 5 - read-write - - - SDXC0_GPR_STROBE_IN_ENABLE - enable strobe clock, maybe used when update strobe DLL - 17 - 1 - read-write - - - SDXC0_GPR_CCLK_RX_DLY_SW_SEL - No description available - 12 - 5 - read-write - - - SDXC0_GPR_CCLK_RX_DLY_SW_FORCE - force use sw DLL config - 11 - 1 - read-write - - - - - ctrl5 - No description available - 0x14 - 32 - 0x00000000 - 0xDFFFF800 - - - SDXC1_SYS_IRQ_EN - system irq enable - 31 - 1 - read-write - - - SDXC1_WKP_IRQ_EN - wakeup irq enable - 30 - 1 - read-write - - - SDXC1_CARDCLK_INV_EN - card clock inverter enable - 28 - 1 - read-write - - - SDXC1_GPR_TUNING_CARD_CLK_SEL - No description available - 23 - 5 - read-write - - - SDXC1_GPR_TUNING_STROBE_SEL - No description available - 18 - 5 - read-write - - - SDXC1_GPR_STROBE_IN_ENABLE - No description available - 17 - 1 - read-write - - - SDXC1_GPR_CCLK_RX_DLY_SW_SEL - No description available - 12 - 5 - read-write - - - SDXC1_GPR_CCLK_RX_DLY_SW_FORCE - No description available - 11 - 1 - read-write - - - - - - - I2C0 - I2C0 - I2C - 0xf3020000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00001E00 - 0x000F9FFF - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf3024000 - - - I2C2 - I2C2 - I2C - 0xf3028000 - - - I2C3 - I2C3 - I2C - 0xf302c000 - - - SDP - SDP - SDP - 0xf304c000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0001 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - FEMC - FEMC - FEMC - 0xf3050000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - IOCTRL - IO Mux Control Register - 0x4 - 32 - 0x00000000 - 0x000000F0 - - - IO_CSX - IO_CSX output selection -0001b - SDRAM CS1 -0110b - SRAM CE# - 4 - 4 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - 3 - 0x4 - BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 - BR[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - write-only - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - write-only - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - write-only - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - write-only - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SRCTRL0 - SRAM control register 0 - 0x70 - 32 - 0x00000000 - 0x00000F01 - - - ADVH - ADV hold state -0b - ADV is high during address hold state -1b - ADV is low during address hold state - 11 - 1 - read-write - - - ADVP - ADV polarity -0b - ADV is active low -1b - ADV is active high - 10 - 1 - read-write - - - ADM - address data mode -00b - address and data MUX mode -11b - address and data non-MUX mode - 8 - 2 - read-write - - - PORTSZ - port size -0b - 8bit -1b - 16bit - 0 - 1 - read-write - - - - - SRCTRL1 - SRAM control register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - OEH - OE high time, is OEH+1 clock cycles - 28 - 4 - read-write - - - OEL - OE low time, is OEL+1 clock cycles - 24 - 4 - read-write - - - WEH - WE high time, is WEH+1 clock cycles - 20 - 4 - read-write - - - WEL - WE low time, is WEL+1 clock cycles - 16 - 4 - read-write - - - AH - Address hold time, is AH+1 clock cycles - 12 - 4 - read-write - - - AS - Address setup time, is AS+1 clock cycles - 8 - 4 - read-write - - - CEH - Chip enable hold time, is CEH+1 clock cycles - 4 - 4 - read-write - - - CES - Chip enable setup time, is CES+1 clock cycles - 0 - 4 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x3000 - registers - - - - 195 - 0x4 - cpu0_core,cpu0_subsys,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1_core,cpx1_subsys,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_con,pow_vis,pow_cpu0,pow_cpu1,rst_soc,rst_con,rst_vis,rst_cpu0,rst_cpu1,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_pll0clk0,clk_src_pll1,clk_src_pll1clk0,clk_src_pll1clk1,clk_src_pll2,clk_src_pll2clk0,clk_src_pll2clk1,clk_src_pll3,clk_src_pll3clk0,clk_src_pll4,clk_src_pll4clk0,rsv45,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr1,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1,rsv131,rsv132,rsv133,rsv134,rsv135,rsv136,rsv137,rsv138,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbapb_bus,axi_bus,conn_bus,vis_bus,femc,rom,lmm0,lmm1,mchtmr0,mchtmr1,axi_sram0,axi_sram1,xpi0,xpi1,sdp,rng,keym,hdma,xdma,gpio,mbx0,mbx1,wdg0,wdg1,wdg2,wdg3,gptmr0,gptmr1,gptmr2,gptmr3,gptmr4,gptmr5,gptmr6,gptmr7,uart0,uart1,uart2,uart3,uart4,uart5,uart6,uart7,uart8,uart9,uart10,uart11,uart12,uart13,uart14,uart15,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,can0,can1,can2,can3,ptpc,adc0,adc1,adc2,adc3,acmp,i2s0,i2s1,i2s2,i2s3,pdm,dao,synt,mot0,mot1,mot2,mot3,lcdc,cam0,cam1,jpeg,pdma,enet0,enet1,ntmr0,ntmr1,sdxc0,sdxc1,usb0,usb1,ref0,ref1 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 3 - 0x10 - 0,1,2 - GROUP0[%s] - no description available - 0x800 - - VALUE - Goup setting - 0x0 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Goup setting - 0x4 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Goup setting - 0x8 - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - TOGGLE - Goup setting - 0xc - 32 - 0x00000023 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - - 3 - 0x10 - 0,1,2 - GROUP1[%s] - no description available - 0x840 - - VALUE - Goup setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Goup setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Goup setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - TOGGLE - Goup setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000001 - 0x0000000F - - - LINK - Affiliate groups of cpu0 -bit0: cpu0 depends on logic node0 -bit1: cpu0 depends on logic node1 -bit2: cpu0 depends on logic node2 -bit3: cpu0 depends on logic node3 - 0 - 4 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep, each bit represents a resource -bit0: soc_pow -bit1: soc_rst -bit2: cpu0_pow -bit3: cpu0_rst -bit4: cpu1_pow -bit5: cpu1_rst -bit6: con_pow -bit7: con_rst -bit8: vis_pow -bit9: vis_rst -bit10: xtal -bit11: pll0 -bit12: pll1 -bit13: pll2 -bit14: pll3 -bit15: pll4 - 0 - 18 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x0000000F - 0x0003FFFF - - - LINK - retention setting while system sleep - 0 - 18 - read-write - - - - - - 4 - 0x10 - cpu0,cpu1,con,vis - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x00000255 - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x00000015 - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 5 - 0x10 - soc,con,vis,cpu0,cpu1 - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00643203 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 67 - 0x4 - clk_top_cpu0,clk_top_mchtmr0,clk_top_cpu1,clk_top_mchtmr,clk_top_axi,clk_top_conn,clk_top_vis,clk_top_ahb,clk_top_femc,clk_top_xpi0,clk_top_xpi1,clk_top_gptmr0,clk_top_gptmr1,clk_top_gptmr2,clk_top_gptmr3,clk_top_gptmr4,clk_top_gptmr5,clk_top_gptmr6,clk_top_gptmr7,clk_top_uart0,clk_top_uart1,clk_top_uart2,clk_top_uart3,clk_top_uart4,clk_top_uart5,clk_top_uart6,clk_top_uart7,clk_top_uart8,clk_top_uart9,clk_top_uart10,clk_top_uart11,clk_top_uart12,clk_top_uart13,clk_top_uart14,clk_top_uart15,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_ptpc,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_lcdc,clk_top_cam0,clk_top_cam1,clk_top_enet0,clk_top_enet1,clk_top_ptp0,clk_top_ptp1,clk_top_ref0,clk_top_ref1,clk_top_ntmr0,clk_top_ntmr1,clk_top_sdxc0,clk_top_sdxc1 - CLOCK[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xC0000FFF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 4 - read-write - - - DIV - clock divider -0: divider by1 -1: divider by 2 -2 divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 4 - 0x4 - clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: adc clock 0 -2: adc clock 1 -3: adc clock 2 - 8 - 3 - read-write - - - - - 4 - 0x4 - clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 - I2SCLK[%s] - no description available - 0x1c10 - 32 - 0x00000000 - 0xC0000700 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MUX - clock source selection -0: ahb clock -1: i2s clock 0 -2: i2s clock 1 -3: i2s clock 2 - 8 - 3 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - PRESET - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 - 0 - 4 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 2 - 0x400 - cpu0,cpu1 - CPU[%s] - no description available - 0x2800 - - LP - No description available - 0x0 - 32 - 0x00001200 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter saturated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wakeup happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - No description available - 0x4 - 32 - 0x00000002 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 8 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3,STATUS4,STATUS5,STATUS6,STATUS7 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 8 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3,ENABLE4,ENABLE5,ENABLE6,ENABLE7 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf60 - registers - - - - 492 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -… -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x00001010 - 0x00007817 - - - MS - pin voltage select, only available in high-speed IO -0: 3.3V -1: 1.8V - 14 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 13 - 1 - read-write - - - SMT - schmitt trigger enable, only available in high-speed IO -0: disable -1: enable - 12 - 1 - read-write - - - PS - pull select -0: pull down -1: pull up - 11 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 4 - 1 - read-write - - - DS - drive strength -for high-speed IO 3.3V: -000: 85.61Ohm -001: 61.2 Ohm -010: 42.88Ohm -011: 35.76Ohm -111: 30.67Ohm -for high-speed IO 1.8V: -000: 84.07Ohm -001: 60.14Ohm -010: 42.15Ohm -011: 35.19Ohm -111: 30.2 Ohm -for general IO: -00: 4mA -01: 8mA -11: 12mA - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf40d8000 - - - BIOC - BIOC - IOC - 0xf5010000 - - - OTPSHW - OTPSHW - OTP - 0xf4080000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf40c8000 - - - PPOR - PPOR - PPOR - 0xf40c0000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_HOT - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - RESET_COLD - reset type attribute - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected -0: brownout -1: temperature(not available) -2: resetpin(not available) -4: debug reset -5: jtag reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2 -19: watch dog 3 -20: pmic watch dog -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf40c4000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x00B010B0 - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00B010B0 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x00EF1C6E - 0x073F006F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00EF1C6E - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 1: debug wakeup -bit 4: fuse interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit11: Security monitor interrupt -bit12: Security in PMIC event -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit18: BATT Button interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit0-1: fuse -bit2-3: sram -bit4-5: vad -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:debug - 0 - 32 - read-write - - - - - DEBUG_STOP - Debug stop config - 0x50 - 32 - 0x00000001 - 0x00000003 - - - CPU1 - Stop peripheral when CPU1 enter debug mode -0: peripheral keep running when CPU1 in debug mode -1: peripheral enter debug mode when CPU1 enter debug - 1 - 1 - read-write - - - CPU0 - Stop peripheral when CPU0 enter debug mode -0: peripheral keep running when CPU0 in debug mode -1: peripheral enter debug mode when CPU0 enter debug - 0 - 1 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000316 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PSEC - PSEC - PSEC - 0xf40cc000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf40d0000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - PGPR - PGPR - PGPR - 0xf40d4000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - VAD - VAD - VAD - 0xf40ec000 - - 0x0 - 0xa4 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x0FF7FBFF - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 24 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 20 - 4 - read-write - - - VAD_IE - VAD event interrupt enable - 18 - 1 - read-write - - - OFIFO_AV_IE - OFIFO data available interrupt enable - 17 - 1 - read-write - - - MEMBUF_EMPTY_IE - Buf empty interrupt enable - 16 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - OFIFO overflow error interrupt enable - 15 - 1 - read-write - - - IIR_OVLD_ERR_IE - IIR overload error interrupt enable - 14 - 1 - read-write - - - IIR_OVFL_ERR_IE - IIR overflow error interrupt enable - 13 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload Interrupt Enable - 12 - 1 - read-write - - - CIC_SAT_ERR_IE - CIC saturation Interrupt Enable - 11 - 1 - read-write - - - MEMBUF_DISABLE - asserted to disable membuf - 9 - 1 - read-write - - - FIFO_THRSH - OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - 5 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 4 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 3 - 1 - read-write - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 1 - 2 - read-write - - - CHNUM - the number of channels to be stored in buffer. Asserted to enable 2 channels. - 0 - 1 - read-write - - - - - FILTCTRL - Filter Control Register - 0x4 - 32 - 0x00000000 - 0x000007FF - - - DECRATIO - the decimation ratio of iir after CIC -1 -2: means dec-by-3 - 8 - 3 - read-write - - - IIR_SLOT_EN - IIR slot enable - 0 - 8 - read-write - - - - - DEC_CTRL0 - Decision Control Register 0 - 0x8 - 32 - 0x00000000 - 0xFFFF03FF - - - NOISE_TOL - the value of amplitude for noise determination when calculationg ZCR - 16 - 16 - read-write - - - BLK_CFG - asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - 9 - 1 - read-write - - - SUBBLK_LEN - length of sub-block - 0 - 9 - read-write - - - - - DEC_CTRL1 - Decision Control Register 1 - 0xc - 32 - 0x00000000 - 0x003FFFFF - - - ZCR_HIGH - ZCR high limit - 11 - 11 - read-write - - - ZCR_LOW - ZCR low limit - 0 - 11 - read-write - - - - - DEC_CTRL2 - Decision Control Register 2 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - AMP_HIGH - amplitude high limit - 16 - 16 - read-write - - - AMP_LOW - amplitude low limit - 0 - 16 - read-write - - - - - ST - Status - 0x18 - 32 - 0x00000000 - 0x000000FF - - - VAD - VAD event found - 7 - 1 - write-only - - - OFIFO_AV - OFIFO data available - 6 - 1 - read-only - - - MEMBUF_EMPTY - Buf empty - 5 - 1 - write-only - - - OFIFO_OVFL - OFIFO overflow - 4 - 1 - write-only - - - IIR_OVLD - IIR overloading - 3 - 1 - write-only - - - IIR_OVFL - IIR oberflow - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation - 0 - 1 - write-only - - - - - OFIFO - Out FIFO - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - The PCM data. -When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). -When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - 0 - 32 - read-write - - - - - RUN - Run Command Register - 0x20 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - software reset. Self-clear - 1 - 1 - read-write - - - VAD_EN - module enable - 0 - 1 - read-write - - - - - OFIFO_CTRL - Out FIFO Control Register - 0x24 - 32 - 0x00000000 - 0x00000001 - - - EN - Asserted to enable OFIFO - 0 - 1 - read-write - - - - - CIC_CFG - CIC Configuration Register - 0x28 - 32 - 0x00000000 - 0x0000FC00 - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - - - 1 - 0x4 - STE_ACT - COEF[%s] - no description available - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The current detected short time energy - 0 - 32 - read-only - - - - - - - PLLCTL - PLLCTL - PLLCTL - 0xf4100000 - - 0x0 - 0x300 - registers - - - - XTAL - Crystal control and status - 0x0 - 32 - 0x00000000 - 0x300FFFFF - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of IRC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 5 - 0x80 - pll0,pll1,pll2,pll3,pll4 - PLL[%s] - no description available - 0x80 - - CFG0 - PLLx config0 - 0x0 - 32 - 0x00140460 - 0xBF77FFE8 - - - SS_RSTPTR - reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - 31 - 1 - read-write - - - REFDIV - refclk diverder, lock when lock_en[24]&~pll_ana_pd - 24 - 6 - read-write - - - POSTDIV1 - lock when lock_en[20]&~pll_ana_pd - 20 - 3 - read-write - - - SS_SPREAD - lock when lock_en[14]&~pll_ana_pd - 14 - 5 - read-write - - - SS_DIVVAL - sscg divval, lock when lock_en[8]&~pll_ana_pd - 8 - 6 - read-write - - - SS_DOWNSPREAD - Downspread control -1’b0 –> Center-Spread -1’b1 –> Downspread - 7 - 1 - read-write - - - SS_RESET - No description available - 6 - 1 - read-write - - - SS_DISABLE_SSCG - No description available - 5 - 1 - read-write - - - DSMPD - 1: int mode; 0: frac mode - 3 - 1 - read-write - - - - - CFG1 - PLLx config1 - 0x4 - 32 - 0x80000000 - 0x86008000 - - - PLLCTRL_HW_EN - 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value -0: full software control PLL settings - 31 - 1 - read-write - - - CLKEN_SW - the clock enable used to gate pll output, should be set after lock, and clear before power down pll. -pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - 26 - 1 - read-write - - - PLLPD_SW - pll power down. -pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; -pll_pd_soc is just delay of soc enable, for soc to control pll on/off; -pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - 25 - 1 - read-write - - - LOCK_CNT_CFG - used to wait lock if set larger than lock time; -default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - 15 - 1 - read-write - - - - - CFG2 - PLLx config2 - 0x8 - 32 - 0x00000000 - 0x00000FFF - - - FBDIV_INT - fbdiv used in int mode - 0 - 12 - read-write - - - - - FREQ - PLLx frac mode frequency adjust - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FRAC - PLL output frequency is : -Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 -for default refdiv=1 and postdiv1=1, 24MHz refclk -Fout is 24*fbdiv in int mode -if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) -Fout is 24*fbdiv in int mode -if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - 8 - 24 - read-write - - - FBDIV_FRAC - fbdiv used in frac mode - 0 - 8 - read-write - - - - - LOCK - PLLx lock control - 0x10 - 32 - 0x00000000 - 0x81104100 - - - LOCK_SS_RSTPTR - lock bit of field ss_rstptr -0: field is open foe software to change -1: field is locked, not changeable - 31 - 1 - read-write - - - LOCK_REFDIV - lock bit of field refdiv -0: field is open foe software to change -1: field is locked, not changeable - 24 - 1 - read-write - - - LOCK_POSTDIV1 - lock bit of field postdiv1 -0: field is open foe software to change -1: field is locked, not changeable - 20 - 1 - read-write - - - LOCK_SS_SPEAD - lock bit of field ss_spead -0: field is open foe software to change -1: field is locked, not changeable - 14 - 1 - read-write - - - LOCK_SS_DIVVAL - lock bit of field ss_divval -0: field is open foe software to change -1: field is locked, not changeable - 8 - 1 - read-write - - - - - STATUS - PLLx status - 0x20 - 32 - 0x00000000 - 0x08000007 - - - ENABLE - enable from SYSCTL block - 27 - 1 - read-only - - - RESPONSE - response to SYSCTL, PLL is power down when both enable and response are 0. - 2 - 1 - read-only - - - PLL_LOCK_COMB - No description available - 1 - 1 - read-only - - - PLL_LOCK_SYNC - No description available - 0 - 1 - read-only - - - - - DIV0 - PLLx divider0 control - 0x40 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - DIV1 - PLLx divider1 control - 0x44 - 32 - 0x00000000 - 0xB00000FF - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - DIV - Divider -0: divide by 1 -1: divide by2 -. . . -255: divide by 256 - 0 - 8 - read-write - - - - - - - - BPOR - BPOR - BPOR - 0xf5004000 - - 0x0 - 0x10 - registers - - - - POR_CAUSE - Power on cause - 0x0 - 32 - 0x00000000 - 0x0000001F - - - CAUSE - Power on cause, each bit represnts one cause, write 1 to clear each bit -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_SELECT - Power on select - 0x4 - 32 - 0x00000000 - 0x0000001F - - - SELECT - Power on cause select, each bit represnts one cause, value 1 enables corresponding cause -bit0: wakeup button -bit1: security violation -bit2: RTC alarm 0 -bit3: RTC alarm 1 -bit4: GPIO - 0 - 5 - read-write - - - - - POR_CONFIG - Power on reset config - 0x8 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - POR_CONTROL - Power down control - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - COUNTER - Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - 0 - 16 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf5008000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LP_MODE - Bandgap works in low power mode -0: not in low power mode -1: bandgap work in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - LDO_CFG - LDO config - 0x4 - 32 - 0x00010000 - 0x03370FFF - - - RES_TRIM - Resistor trim - 24 - 2 - read-write - - - CP_TRIM - Capacitor trim - 20 - 2 - read-write - - - EN_SL - enable selfload, this bit helps improve LDO performance when current less than 200nA -0: self load disabled -1: selfload enabled - 18 - 1 - read-write - - - DIS_PD - disable pull down resistor, enable pull down may lead to more power but better response -0: pulldown resistor enabled -1: pulldown resistor disabled - 17 - 1 - read-write - - - ENABLE - LDO enable -0: LDO is disabled -1: LDO is enabled - 16 - 1 - read-write - - - VOLT - LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. -600: 600mV -620: 620mV -. . . -1100:1100mV - 0 - 12 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf500c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf5018000 - - 0x0 - 0x20 - registers - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - RTCSHW - RTCSHW - RTC - 0xf501c000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - RTC - RTC - RTC - 0xf5044000 - - - BSEC - BSEC - BSEC - 0xf5040000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - BKEY - BKEY - BKEY - 0xf5048000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf504c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf5050000 - - 0x0 - 0x88 - registers - - - - 6 - 0x10 - tamp0,tamp1,tamp2,tamp3,tamp4,tamp5 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf5054000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/SConscript deleted file mode 100644 index 5717c3e6317..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/SConscript +++ /dev/null @@ -1,25 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_acmp_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_acmp_soc_drv.h deleted file mode 100644 index 4b8d4831949..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_acmp_soc_drv.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ACMP_SOC_DRV_H -#define HPM_ACMP_SOC_DRV_H - -#include "hpm_soc.h" - -static inline void acmp_enable_bandgap(void) -{ - uint32_t clk_div_temp; - - clk_div_temp = ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(HPM_ADC3->CONV_CFG1); - - /* Set input clock divider temporarily */ - HPM_ADC3->CONV_CFG1 = (HPM_ADC3->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(1); - - /* Enable ADC config clock */ - HPM_ADC3->ANA_CTRL0 |= ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; - - /* Enable bandgap_en */ - HPM_ADC3->ADC16_CONFIG0 |= ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK; - - /* Recover input clock divider */ - HPM_ADC3->CONV_CFG1 = (HPM_ADC3->CONV_CFG1 & ~ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) - | ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(clk_div_temp); - - /* Disable ADC config clock */ - HPM_ADC3->ANA_CTRL0 &= ~ADC16_ANA_CTRL0_ADC_CLK_ON_MASK; -} - -#endif /* HPM_ACMP_SOC_DRV_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_batt_iomux.h deleted file mode 100644 index 57e881864da..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_batt_iomux.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BATT_IOMUX_H -#define HPM_BATT_IOMUX_H - -/* BIOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_PWR_ON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_TAMP_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_RESETN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_TAMP_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_PBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_TAMP_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_WBUTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_TAMP_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_PLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_TAMP_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_WLED IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_TAMP_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_TAMP_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_TAMP_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_TAMP_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_TAMP_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_HIBERNATE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_TAMP_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_STANDBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_TAMP_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_bcfg_drv.h deleted file mode 100644 index 7f5a005ef65..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_bcfg_drv.h +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BCFG_DRV_H -#define HPM_BCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_bcfg_regs.h" - -/** - * - * @brief BCFG driver APIs - * @defgroup bcfg_interface BCFG driver APIs - * @ingroup io_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable VBAT LP mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_lp_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_LP_MODE_MASK; -} - -/** - * @brief disable VBAT LP mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_lp_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_LP_MODE_MASK; -} - -/** - * @brief enable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -/** - * @brief disable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -/** - * @brief set ldo voltage - * - * @param[in] ptr base address - * @param[in] voltage target voltage - */ -static inline void bcfg_ldo_set_voltage(BCFG_Type *ptr, uint16_t voltage) -{ - ptr->LDO_CFG = (ptr->LDO_CFG & ~(BCFG_LDO_CFG_VOLT_MASK)) | BCFG_LDO_CFG_VOLT_SET(voltage); -} - -/** - * @brief enable ldo - * - * @param[in] ptr base address - */ -static inline void bcfg_ldo_enable(BCFG_Type *ptr) -{ - ptr->LDO_CFG |= BCFG_LDO_CFG_ENABLE_MASK; -} - -/** - * @brief disable ldo - * - * @param[in] ptr base address - */ -static inline void bcfg_ldo_disable(BCFG_Type *ptr) -{ - ptr->LDO_CFG &= ~BCFG_LDO_CFG_ENABLE_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BCFG_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_bpor_drv.h deleted file mode 100644 index e37bac24b13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_bpor_drv.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BPOR_DRV_H -#define HPM_BPOR_DRV_H - -#include "hpm_common.h" -#include "hpm_bpor_regs.h" - -/** - * - * @brief BPOR driver APIs - * @defgroup bpor_interface BPOR driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -/** @brief Define BPOR power on cause */ -typedef enum { - bpor_power_on_cause_wbutn = 1 << 0, - bpor_power_on_cause_safety_violation = 1 << 1, - bpor_power_on_cause_rtc_0 = 1 << 2, - bpor_power_on_cause_rtc_1 = 1 << 3, - bpor_power_on_cause_gpio = 1 << 4 -} bpor_power_on_cause_t; - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get power on cause - * - * @param[in] ptr BPOR base address - * @retval POR_CAUSE register value - */ -static inline uint32_t bpor_get_power_on_cause(BPOR_Type *ptr) -{ - return ptr->POR_CAUSE; -} - -/** - * @brief Clear power on cause - * - * @param[in] ptr BPOR base address - * @param[in] mask cause status to be cleared - */ -static inline void bpor_clear_power_on_cause(BPOR_Type *ptr, uint8_t mask) -{ - ptr->POR_CAUSE |= mask; -} - -/** - * @brief enable power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be enabled - */ -static inline void bpor_enable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) -{ - ptr->POR_SELECT |= cause; -} - -/** - * @brief disable power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be disabled - */ -static inline void bpor_disable_power_on_cause(BPOR_Type *ptr, bpor_power_on_cause_t cause) -{ - ptr->POR_SELECT &= ~cause; -} - -/** - * @brief Set power on cause - * - * @param[in] ptr BPOR base address - * @param[in] cause wake up cause to be used - */ -static inline void bpor_set_power_on_cause(BPOR_Type *ptr, uint8_t cause) -{ - ptr->POR_SELECT = (ptr->POR_SELECT & ~BPOR_POR_SELECT_SELECT_MASK) | cause; -} - -/** - * @brief Enable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Disable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Set power down counter - * - * @param[in] ptr BPOR base address - * @param[in] counter counter value - */ -static inline void bpor_set_power_down_counter(BPOR_Type *ptr, uint16_t counter) -{ - ptr->POR_CONTROL = BPOR_POR_CONTROL_COUNTER_SET(counter); -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_clock_drv.c deleted file mode 100644 index 19be37d65dc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_clock_drv.c +++ /dev/null @@ -1,582 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_pllctl_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define FREQ_1MHz (1000000UL) - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (648000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (266000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (400000000UL) -#define FREQ_PRESET1_PLL2_CLK0 (333000000UL) -#define FREQ_PRESET1_PLL2_CLK1 (250000000UL) -#define FREQ_PRESET1_PLL3_CLK0 (614400000UL) -#define FREQ_PRESET1_PLL4_CLK0 (594000000UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) -#define WDG_INSTANCE_NUM (4U) - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ - -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for I2S or ADC - */ -static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance); - -/** - * @brief Get Clock frequency for WDG - */ -static uint32_t get_frequency_for_wdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PWDG - */ -static uint32_t get_frequency_for_pwdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - -static uint64_t hpm_csr_get_core_cycle(void); - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ahb0, - clock_node_ana0, - clock_node_ana1, - clock_node_ana2, -}; -static const clock_node_t s_i2s_clk_mux_node[] = { - clock_node_ahb0, - clock_node_aud0, - clock_node_aud1, - clock_node_aud2, -}; - -static WDG_Type *const s_wdgs[] = { HPM_WDG0, HPM_WDG1, HPM_WDG2, HPM_WDG3 }; - -uint32_t hpm_core_clock; - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq = 0UL; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_ADC, node_or_instance); - break; - case CLK_SRC_GROUP_I2S: - clk_freq = get_frequency_for_i2s_or_adc(CLK_SRC_GROUP_I2S, node_or_instance); - break; - case CLK_SRC_GROUP_WDG: - clk_freq = get_frequency_for_wdg(node_or_instance); - break; - case CLK_SRC_GROUP_PWDG: - clk_freq = get_frequency_for_pwdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_AHB: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); - break; - case CLK_SRC_GROUP_AXI0: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axi0); - break; - case CLK_SRC_GROUP_AXI1: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axi1); - break; - case CLK_SRC_GROUP_AXI2: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axi2); - break; - case CLK_SRC_GROUP_CPU0: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_cpu0); - break; - case CLK_SRC_GROUP_CPU1: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_cpu1); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq = 0UL; - uint32_t div = 1; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 0U); - break; - case clock_source_pll1_clk0: - div = pllctl_get_div(HPM_PLLCTL, 1, 0); - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 1U) / div; - break; - case clock_source_pll1_clk1: - div = pllctl_get_div(HPM_PLLCTL, 1, 1); - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 1U) / div; - break; - case clock_source_pll2_clk0: - div = pllctl_get_div(HPM_PLLCTL, 2, 0); - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 2U) / div; - break; - case clock_source_pll2_clk1: - div = pllctl_get_div(HPM_PLLCTL, 2, 1); - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 2U) / div; - break; - case clock_source_pll3_clk0: - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 3U); - break; - case clock_source_pll4_clk0: - clk_freq = pllctl_get_pll_freq_in_hz(HPM_PLLCTL, 4U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_i2s_or_adc(uint32_t clk_src_type, uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - if (clk_src_type == CLK_SRC_GROUP_ADC) { - uint32_t adc_index = instance; - if (adc_index < ADC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[adc_index]); - if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { - node = s_adc_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - } else { - uint32_t i2s_index = instance; - if (i2s_index < I2S_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[i2s_index]); - if (mux_in_reg < ARRAY_SIZE(s_i2s_clk_mux_node)) { - node = s_i2s_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - } - - if (is_mux_valid) { - if (node == clock_node_ahb0) { - clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); - } else { - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_wdg(uint32_t instance) -{ - uint32_t freq_in_hz; - /* EXT clock is chosen */ - if (WDG_CTRL_CLKSEL_GET(s_wdgs[instance]->CTRL) == 0) { - freq_in_hz = get_frequency_for_ip_in_common_group(clock_node_ahb0); - } - /* PCLK is chosen */ - else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_pwdg(void) -{ - uint32_t freq_in_hz; - if (WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_I2S: - if (node_or_instance < I2S_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_I2S; - clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_WDG; - clk_src_index = WDG_CTRL_CLKSEL_GET(s_wdgs[node_or_instance]->CTRL); - } - break; - case CLK_SRC_GROUP_PWDG: - clk_src_group = CLK_SRC_GROUP_PWDG; - clk_src_index = WDG_CTRL_CLKSEL_GET(HPM_PWDG->CTRL); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_AHB: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_ahb0]); - break; - case CLK_SRC_GROUP_AXI0: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi0]); - break; - case CLK_SRC_GROUP_AXI1: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi1]); - break; - case CLK_SRC_GROUP_AXI2: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi2]); - break; - case CLK_SRC_GROUP_CPU0: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu0]); - break; - case CLK_SRC_GROUP_CPU1: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu1]); - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -uint32_t clock_get_divider(clock_name_t clock_name) -{ - uint32_t clk_divider = CLOCK_DIV_INVALID; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_WDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_divider = 1UL; - } - break; - case CLK_SRC_GROUP_PWDG: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_PMIC: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_AHB: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_ahb0]); - break; - case CLK_SRC_GROUP_AXI0: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi0]); - break; - case CLK_SRC_GROUP_AXI1: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi1]); - break; - case CLK_SRC_GROUP_AXI2: - clk_divider = SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axi2]); - break; - case CLK_SRC_GROUP_CPU0: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu0]); - break; - case CLK_SRC_GROUP_CPU1: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_cpu1]); - break; - default: - clk_divider = CLOCK_DIV_INVALID; - break; - } - return clk_divider; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ahb0) || (src > clk_adc_src_ana2)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src <= clk_i2s_src_ahb0) || (src >= clk_i2s_src_aud2)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->I2SCLK[node_or_instance] = - (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_WDG) && (clk_src_grp != CLK_SRC_GROUP_PWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PWDG->CTRL = (HPM_PWDG->CTRL & ~WDG_CTRL_CLKSEL_MASK) | WDG_CTRL_CLKSEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL = (s_wdgs[instance]->CTRL & ~WDG_CTRL_CLKSEL_MASK) | WDG_CTRL_CLKSEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_I2S: - case CLK_SRC_GROUP_WDG: - case CLK_SRC_GROUP_PWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AHB: - status = status_clk_shared_ahb; - break; - case CLK_SRC_GROUP_AXI0: - status = status_clk_shared_axi0; - break; - case CLK_SRC_GROUP_AXI1: - status = status_clk_shared_axi1; - break; - case CLK_SRC_GROUP_AXI2: - status = status_clk_shared_axi2; - break; - case CLK_SRC_GROUP_CPU0: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_CPU1: - status = status_clk_shared_cpu1; - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - return sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_update_core_clock(void) -{ - uint32_t hart_id = read_csr(CSR_MHARTID); - clock_name_t cpu_clk_name = (hart_id == 1U) ? clock_cpu1 : clock_cpu0; - hpm_core_clock = clock_get_frequency(cpu_clk_name); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_clock_drv.h deleted file mode 100644 index 97faf07a2e8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_clock_drv.h +++ /dev/null @@ -1,401 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" -#include "hpm_csr_drv.h" - -/** - * @brief CLOCK driver APIs - * @defgroup clock_interface CLOCK driver APIs - * @{ - * - */ - -#define CLOCK_DIV_INVALID (~0UL) - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), /**< Clock divider is invalid */ - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), /**< Clock source is invalid */ - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), /**< Clock name is invalid */ - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), /**< Clock operation is unsupported */ - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), /**< The clock source is shared with AHB */ - status_clk_shared_axi0 = MAKE_STATUS(status_group_clk, 5), /**< The clock source is shared with AXI0 */ - status_clk_shared_axi1 = MAKE_STATUS(status_group_clk, 6), /**< THe clock source is shared with AXI1 */ - status_clk_shared_axi2 = MAKE_STATUS(status_group_clk, 7), /**< The clock source is shared with AXI2 */ - status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 8), /**< The clock source is shared with CPU0 */ - status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 9), /**< The clock source is shared with CPU1 */ - status_clk_fixed = MAKE_STATUS(status_group_clk, 10), /**< The clock source is a fixed clock source */ - -}; - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_I2S (2U) -#define CLK_SRC_GROUP_WDG (3U) -#define CLK_SRC_GROUP_PMIC (4U) -#define CLK_SRC_GROUP_AHB (5U) -#define CLK_SRC_GROUP_AXI0 (6U) -#define CLK_SRC_GROUP_AXI1 (7U) -#define CLK_SRC_GROUP_AXI2 (8U) -#define CLK_SRC_GROUP_CPU0 (9U) -#define CLK_SRC_GROUP_CPU1 (10U) -#define CLK_SRC_GROUP_SRC (11U) -#define CLK_SRC_GROUP_PWDG (12U) -#define CLK_SRC_GROUP_INVALID (15U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp) << 4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src) >> 4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src)&0x0FU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll3_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll4_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 2), - clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 3), - - clk_i2s_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), - clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 2), - clk_i2s_src_aud2 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 3), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_WDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - -#define RESOURCE_INVALID (0xFFFFU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name)&0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_COMMON, clock_node_cpu0), - clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_COMMON, clock_node_cpu1), - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), - clock_axi0 = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_COMMON, clock_node_axi0), - clock_axi1 = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_COMMON, clock_node_axi1), - clock_axi2 = MAKE_CLOCK_NAME(sysctl_resource_axiv, CLK_SRC_GROUP_COMMON, clock_node_axi2), - clock_ahb = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_COMMON, clock_node_ahb0), - clock_femc = MAKE_CLOCK_NAME(sysctl_resource_femc, CLK_SRC_GROUP_COMMON, clock_node_femc), - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - clock_xpi1 = MAKE_CLOCK_NAME(sysctl_resource_xpi1, CLK_SRC_GROUP_COMMON, clock_node_xpi1), - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), - clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), - clock_gptmr4 = MAKE_CLOCK_NAME(sysctl_resource_gptmr4, CLK_SRC_GROUP_COMMON, clock_node_gptmr4), - clock_gptmr5 = MAKE_CLOCK_NAME(sysctl_resource_gptmr5, CLK_SRC_GROUP_COMMON, clock_node_gptmr5), - clock_gptmr6 = MAKE_CLOCK_NAME(sysctl_resource_gptmr6, CLK_SRC_GROUP_COMMON, clock_node_gptmr6), - clock_gptmr7 = MAKE_CLOCK_NAME(sysctl_resource_gptmr7, CLK_SRC_GROUP_COMMON, clock_node_gptmr7), - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), - clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), - clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), - clock_uart8 = MAKE_CLOCK_NAME(sysctl_resource_uart8, CLK_SRC_GROUP_COMMON, clock_node_uart8), - clock_uart9 = MAKE_CLOCK_NAME(sysctl_resource_uart9, CLK_SRC_GROUP_COMMON, clock_node_uart9), - clock_uart10 = MAKE_CLOCK_NAME(sysctl_resource_uarta, CLK_SRC_GROUP_COMMON, clock_node_uarta), - clock_uart11 = MAKE_CLOCK_NAME(sysctl_resource_uartb, CLK_SRC_GROUP_COMMON, clock_node_uartb), - clock_uart12 = MAKE_CLOCK_NAME(sysctl_resource_uartc, CLK_SRC_GROUP_COMMON, clock_node_uartc), - clock_uart13 = MAKE_CLOCK_NAME(sysctl_resource_uartd, CLK_SRC_GROUP_COMMON, clock_node_uartd), - clock_uart14 = MAKE_CLOCK_NAME(sysctl_resource_uarte, CLK_SRC_GROUP_COMMON, clock_node_uarte), - clock_uart15 = MAKE_CLOCK_NAME(sysctl_resource_uartf, CLK_SRC_GROUP_COMMON, clock_node_uartf), - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), - clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), - clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), - clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), - clock_display = MAKE_CLOCK_NAME(sysctl_resource_dis0, CLK_SRC_GROUP_COMMON, clock_node_dis0), - clock_sdxc0 = MAKE_CLOCK_NAME(sysctl_resource_sdxc0, CLK_SRC_GROUP_COMMON, clock_node_sdxc0), - clock_sdxc1 = MAKE_CLOCK_NAME(sysctl_resource_sdxc1, CLK_SRC_GROUP_COMMON, clock_node_sdxc1), - clock_camera0 = MAKE_CLOCK_NAME(sysctl_resource_cam0, CLK_SRC_GROUP_COMMON, clock_node_cam0), - clock_camera1 = MAKE_CLOCK_NAME(sysctl_resource_cam1, CLK_SRC_GROUP_COMMON, clock_node_cam1), - clock_ntmr0 = MAKE_CLOCK_NAME(sysctl_resource_ntmr0, CLK_SRC_GROUP_COMMON, clock_node_ntmr0), - clock_ntmr1 = MAKE_CLOCK_NAME(sysctl_resource_ntmr1, CLK_SRC_GROUP_COMMON, clock_node_ntmr1), - - clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_COMMON, clock_node_ptpc), - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_WDG, 0), - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_WDG, 1), - clock_watchdog2 = MAKE_CLOCK_NAME(sysctl_resource_wdg2, CLK_SRC_GROUP_WDG, 2), - clock_watchdog3 = MAKE_CLOCK_NAME(sysctl_resource_wdg3, CLK_SRC_GROUP_WDG, 3), - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PWDG, 0), - clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), - clock_eth1 = MAKE_CLOCK_NAME(sysctl_resource_eth1, CLK_SRC_GROUP_COMMON, clock_node_eth1), - clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp0), - clock_ptp1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp1), - clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI0, 0), - clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI0, 1), - clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI0, 2), - clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXI0, 3), - clock_ram1 = MAKE_CLOCK_NAME(sysctl_resource_ram1, CLK_SRC_GROUP_AXI0, 4), - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI1, 0), - clock_usb1 = MAKE_CLOCK_NAME(sysctl_resource_usb1, CLK_SRC_GROUP_AXI1, 1), - clock_jpeg = MAKE_CLOCK_NAME(sysctl_resource_jpeg, CLK_SRC_GROUP_AXI2, 0), - clock_pdma = MAKE_CLOCK_NAME(sysctl_resource_pdma, CLK_SRC_GROUP_AXI2, 1), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AHB, 0), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 1), - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 2), - clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AHB, 3), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AHB, 4), - clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AHB, 5), - clock_mot0 = MAKE_CLOCK_NAME(sysctl_resource_mot0, CLK_SRC_GROUP_AHB, 6), - clock_mot1 = MAKE_CLOCK_NAME(sysctl_resource_mot1, CLK_SRC_GROUP_AHB, 7), - clock_mot2 = MAKE_CLOCK_NAME(sysctl_resource_mot2, CLK_SRC_GROUP_AHB, 8), - clock_mot3 = MAKE_CLOCK_NAME(sysctl_resource_mot3, CLK_SRC_GROUP_AHB, 9), - clock_acmp = MAKE_CLOCK_NAME(sysctl_resource_acmp, CLK_SRC_GROUP_AHB, 10), - clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_I2S, 0), - clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_I2S, 1), - clock_synt = MAKE_CLOCK_NAME(sysctl_resource_synt, CLK_SRC_GROUP_AHB, 12), - clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), - clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm1, CLK_SRC_GROUP_CPU1, 0), - - /* For ADC, there are 2-stage clock source and divider configuration */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), - clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), - clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), - clock_adc3 = MAKE_CLOCK_NAME(sysctl_resource_adc3, CLK_SRC_GROUP_ADC, 3), - - /* For I2S, there are 2-stage clock source and divider configuration */ - clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), - clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), - clock_aud2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud2), - clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), - clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), - clock_i2s2 = MAKE_CLOCK_NAME(sysctl_resource_i2s2, CLK_SRC_GROUP_I2S, 2), - clock_i2s3 = MAKE_CLOCK_NAME(sysctl_resource_i2s3, CLK_SRC_GROUP_I2S, 3), - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 2), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 3), - clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 4), - clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 5), - clk_pll3clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll3, CLK_SRC_GROUP_SRC, 6), - clk_pll4clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll4, CLK_SRC_GROUP_SRC, 7), -} clock_name_t; - -#ifdef __cplusplus -extern "C" -{ -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * @param[in] clock_name IP clock name - * - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Get the IP clock divider - * Note:This API return the direct clock divider - * @param [in] clock_name clock name - * @return IP clock divider - */ -uint32_t clock_get_divider(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @retval status_success Setting ADC clock source is successful - * @retval status_clk_invalid Invalid ADC clock - * @retval status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set I2S clock source - * @param[in] clock_name I2S clock name - * @param[in] src I2S clock source - * - * @retval status_success Setting I2S clock source is successful - * @retval status_clk_invalid Invalid I2S clock - * @retval status_clk_src_invalid Invalid I2S clock source - */ -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @retval status_success Setting Clock source and divider is successful. - * @retval status_clk_set_by_other_api The clock should be set by other API - * @retval status_clk_src_invalid clock source is invalid. - * @retval status_clk_fixed clock source and divider is a fixed value - * @retval status_clk_shared_ahb Clock is shared with the AHB clock - * @retval status_clk_shared_axi0 Clock is shared with the AXI0 clock - * @retval status_clk_shared_axi1 CLock is shared with the AXI1 clock - * @retval status_clk_shared_axi2 Clock is shared with the AXI2 clock - * @retval status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * @retval status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - -/** - * @brief HPM Core clock variable - */ -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_csr_regs.h deleted file mode 100644 index 5f43b12bd1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_csr_regs.h +++ /dev/null @@ -1,6512 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_SSTATUS (0x100) -#define CSR_SEDELEG (0x102) -#define CSR_SIDELEG (0x103) -#define CSR_SIE (0x104) -#define CSR_STVEC (0x105) -#define CSR_SSCRATCH (0x140) -#define CSR_SEPC (0x141) -#define CSR_SCAUSE (0x142) -#define CSR_STVAL (0x143) -#define CSR_SIP (0x144) -#define CSR_SATP (0x180) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MEDELEG (0x302) -#define CSR_MIDELEG (0x303) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_PMACFG0 (0xBC0) -#define CSR_PMACFG1 (0xBC1) -#define CSR_PMACFG2 (0xBC2) -#define CSR_PMACFG3 (0xBC3) -#define CSR_PMAADDR0 (0xBD0) -#define CSR_PMAADDR1 (0xBD1) -#define CSR_PMAADDR2 (0xBD2) -#define CSR_PMAADDR3 (0xBD3) -#define CSR_PMAADDR4 (0xBD4) -#define CSR_PMAADDR5 (0xBD5) -#define CSR_PMAADDR6 (0xBD6) -#define CSR_PMAADDR7 (0xBD7) -#define CSR_PMAADDR8 (0xBD8) -#define CSR_PMAADDR9 (0xBD9) -#define CSR_PMAADDR10 (0xBDA) -#define CSR_PMAADDR11 (0xBDB) -#define CSR_PMAADDR12 (0xBDC) -#define CSR_PMAADDR13 (0xBDD) -#define CSR_PMAADDR14 (0xBDE) -#define CSR_PMAADDR15 (0xBDF) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_SCOUNTEREN (0x106) -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_MSLIDELEG (0x7D5) -#define CSR_MCLK_CTL (0x7DF) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_SLIE (0x9C4) -#define CSR_SLIP (0x9C5) -#define CSR_SDCAUSE (0x9C9) -#define CSR_SCCTLDATA (0x9CD) -#define CSR_SCOUNTERINTEN (0x9CF) -#define CSR_SCOUNTERMASK_M (0x9D1) -#define CSR_SCOUNTERMASK_S (0x9D2) -#define CSR_SCOUNTERMASK_U (0x9D3) -#define CSR_SCOUNTEROVF (0x9D4) -#define CSR_SCOUNTINHIBIT (0x9E0) -#define CSR_SHPMEVENT3 (0x9E3) -#define CSR_SHPMEVENT4 (0x9E4) -#define CSR_SHPMEVENT5 (0x9E5) -#define CSR_SHPMEVENT6 (0x9E6) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: SSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_SSTATUS_SD_MASK (0x80000000UL) -#define CSR_SSTATUS_SD_SHIFT (31U) -#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_SSTATUS_MXR_MASK (0x80000UL) -#define CSR_SSTATUS_MXR_SHIFT (19U) -#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) -#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_SSTATUS_SUM_MASK (0x40000UL) -#define CSR_SSTATUS_SUM_SHIFT (18U) -#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) -#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggeredwhen XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. - * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_XS_MASK (0x18000UL) -#define CSR_SSTATUS_XS_SHIFT (15U) -#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. - * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_FS_MASK (0x6000U) -#define CSR_SSTATUS_FS_SHIFT (13U) -#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) -#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_SSTATUS_SPP_MASK (0x100U) -#define CSR_SSTATUS_SPP_SHIFT (8U) -#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) -#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_SSTATUS_SPIE_MASK (0x20U) -#define CSR_SSTATUS_SPIE_SHIFT (5U) -#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) -#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_SSTATUS_UPIE_MASK (0x10U) -#define CSR_SSTATUS_UPIE_SHIFT (4U) -#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) -#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_SIE_MASK (0x2U) -#define CSR_SSTATUS_SIE_SHIFT (1U) -#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) -#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_UIE_MASK (0x1U) -#define CSR_SSTATUS_UIE_SHIFT (0U) -#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) -#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: SEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SPF_MASK (0x8000U) -#define CSR_SEDELEG_SPF_SHIFT (15U) -#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) -#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LPF_MASK (0x2000U) -#define CSR_SEDELEG_LPF_SHIFT (13U) -#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) -#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IPF_MASK (0x1000U) -#define CSR_SEDELEG_IPF_SHIFT (12U) -#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) -#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_UEC_MASK (0x100U) -#define CSR_SEDELEG_UEC_SHIFT (8U) -#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) -#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAF_MASK (0x80U) -#define CSR_SEDELEG_SAF_SHIFT (7U) -#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) -#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAM_MASK (0x40U) -#define CSR_SEDELEG_SAM_SHIFT (6U) -#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) -#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAF_MASK (0x20U) -#define CSR_SEDELEG_LAF_SHIFT (5U) -#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) -#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAM_MASK (0x10U) -#define CSR_SEDELEG_LAM_SHIFT (4U) -#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) -#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) - -/* - * B (RW) - * - * B indicates whether an exception triggered by breakpoint will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_B_MASK (0x8U) -#define CSR_SEDELEG_B_SHIFT (3U) -#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) -#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_II_MASK (0x4U) -#define CSR_SEDELEG_II_SHIFT (2U) -#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) -#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAF_MASK (0x2U) -#define CSR_SEDELEG_IAF_SHIFT (1U) -#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) -#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAM_MASK (0x1U) -#define CSR_SEDELEG_IAM_SHIFT (0U) -#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) -#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: SIDELEG */ -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UEI_MASK (0x100U) -#define CSR_SIDELEG_UEI_SHIFT (8U) -#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) -#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UTI_MASK (0x10U) -#define CSR_SIDELEG_UTI_SHIFT (4U) -#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) -#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_USI_MASK (0x1U) -#define CSR_SIDELEG_USI_SHIFT (0U) -#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) -#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) - -/* Bitfield definition for register: SIE */ -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SEIE_MASK (0x200U) -#define CSR_SIE_SEIE_SHIFT (9U) -#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) -#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UEIE_MASK (0x100U) -#define CSR_SIE_UEIE_SHIFT (8U) -#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) -#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_STIE_MASK (0x20U) -#define CSR_SIE_STIE_SHIFT (5U) -#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) -#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UTIE_MASK (0x10U) -#define CSR_SIE_UTIE_SHIFT (4U) -#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) -#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SSIE_MASK (0x2U) -#define CSR_SIE_SSIE_SHIFT (1U) -#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) -#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_USIE_MASK (0x1U) -#define CSR_SIE_USIE_SHIFT (0U) -#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) -#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) - -/* Bitfield definition for register: STVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_STVEC_BASE_31_2_SHIFT (2U) -#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) -#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: SSCRATCH */ -/* - * SSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) -#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) -#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) - -/* Bitfield definition for register: SEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_SEPC_EPC_SHIFT (1U) -#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) -#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) - -/* Bitfield definition for register: SCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) -#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 256+16:Slave port ECC error interrupt (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt(S-mode) - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:10:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) -#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: STVAL */ -/* - * STVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) -#define CSR_STVAL_STVAL_SHIFT (0U) -#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) -#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) - -/* Bitfield definition for register: SIP */ -/* - * SEIP (RO) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SEIP_MASK (0x200U) -#define CSR_SIP_SEIP_SHIFT (9U) -#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UEIP_MASK (0x100U) -#define CSR_SIP_UEIP_SHIFT (8U) -#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) -#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) - -/* - * STIP (RO) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_STIP_MASK (0x20U) -#define CSR_SIP_STIP_SHIFT (5U) -#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) - -/* - * UTIP (RO) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UTIP_MASK (0x10U) -#define CSR_SIP_UTIP_SHIFT (4U) -#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SSIP_MASK (0x2U) -#define CSR_SIP_SSIP_SHIFT (1U) -#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) -#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_USIP_MASK (0x1U) -#define CSR_SIP_USIP_SHIFT (0U) -#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) -#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) - -/* Bitfield definition for register: SATP */ -/* - * MODE (RW) - * - * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is - * not supported in the product, this CSR will be - * hardwired to 0. - * 0:No page translation - * 1:Page-based 32-bit virtual addressing - */ -#define CSR_SATP_MODE_MASK (0x80000000UL) -#define CSR_SATP_MODE_SHIFT (31U) -#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) -#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) - -/* - * ASID (RW) - * - * ASID holds the address space identifier. - */ -#define CSR_SATP_ASID_MASK (0x7FC00000UL) -#define CSR_SATP_ASID_SHIFT (22U) -#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) -#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) - -/* - * PPN (RW) - * - * PPN holds the physical page number of the root page table. - */ -#define CSR_SATP_PPN_MASK (0x3FFFFFUL) -#define CSR_SATP_PPN_SHIFT (0U) -#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) -#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * TSR (RW) - * - * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TSR_MASK (0x400000UL) -#define CSR_MSTATUS_TSR_SHIFT (22U) -#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) -#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) - -/* - * TW (RW) - * - * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TW_MASK (0x200000UL) -#define CSR_MSTATUS_TW_SHIFT (21U) -#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) -#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) - -/* - * TVM (RW) - * - * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. - * 0:Normal execution - * 1:Raising exceptions - */ -#define CSR_MSTATUS_TVM_MASK (0x100000UL) -#define CSR_MSTATUS_TVM_SHIFT (20U) -#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) -#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_MSTATUS_SUM_MASK (0x40000UL) -#define CSR_MSTATUS_SUM_SHIFT (18U) -#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) -#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_MSTATUS_SPP_MASK (0x100U) -#define CSR_MSTATUS_SPP_SHIFT (8U) -#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) -#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_MSTATUS_SPIE_MASK (0x20U) -#define CSR_MSTATUS_SPIE_SHIFT (5U) -#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) -#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_SIE_MASK (0x2U) -#define CSR_MSTATUS_SIE_SHIFT (1U) -#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) -#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SPF_MASK (0x8000U) -#define CSR_MEDELEG_SPF_SHIFT (15U) -#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) -#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LPF_MASK (0x2000U) -#define CSR_MEDELEG_LPF_SHIFT (13U) -#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) -#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IPF_MASK (0x1000U) -#define CSR_MEDELEG_IPF_SHIFT (12U) -#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) -#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) - -/* - * SEC (RW) - * - * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SEC_MASK (0x200U) -#define CSR_MEDELEG_SEC_SHIFT (9U) -#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) -#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_UEC_MASK (0x100U) -#define CSR_MEDELEG_UEC_SHIFT (8U) -#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) -#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAF_MASK (0x80U) -#define CSR_MEDELEG_SAF_SHIFT (7U) -#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) -#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAM_MASK (0x40U) -#define CSR_MEDELEG_SAM_SHIFT (6U) -#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) -#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAF_MASK (0x20U) -#define CSR_MEDELEG_LAF_SHIFT (5U) -#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) -#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAM_MASK (0x10U) -#define CSR_MEDELEG_LAM_SHIFT (4U) -#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) -#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_II_MASK (0x4U) -#define CSR_MEDELEG_II_SHIFT (2U) -#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) -#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAF_MASK (0x2U) -#define CSR_MEDELEG_IAF_SHIFT (1U) -#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) -#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAM_MASK (0x1U) -#define CSR_MEDELEG_IAM_SHIFT (0U) -#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) -#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: MIDELEG */ -/* - * SEI (RW) - * - * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SEI_MASK (0x200U) -#define CSR_MIDELEG_SEI_SHIFT (9U) -#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) -#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) - -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UEI_MASK (0x100U) -#define CSR_MIDELEG_UEI_SHIFT (8U) -#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) -#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) - -/* - * STI (RW) - * - * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_STI_MASK (0x20U) -#define CSR_MIDELEG_STI_SHIFT (5U) -#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) -#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UTI_MASK (0x10U) -#define CSR_MIDELEG_UTI_SHIFT (4U) -#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) -#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) - -/* - * SSI (RW) - * - * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SSI_MASK (0x2U) -#define CSR_MIDELEG_SSI_SHIFT (1U) -#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) -#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_USI_MASK (0x1U) -#define CSR_MIDELEG_USI_SHIFT (0U) -#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) -#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SEIE_MASK (0x200U) -#define CSR_MIE_SEIE_SHIFT (9U) -#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) -#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_STIE_MASK (0x20U) -#define CSR_MIE_STIE_SHIFT (5U) -#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) -#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SSIE_MASK (0x2U) -#define CSR_MIE_SSIE_SHIFT (1U) -#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) -#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_MCONTROL_S_MASK (0x10U) -#define CSR_MCONTROL_S_SHIFT (4U) -#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) -#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ICOUNT_S_MASK (0x80U) -#define CSR_ICOUNT_S_SHIFT (7U) -#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) -#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ITRIGGER_S_MASK (0x80U) -#define CSR_ITRIGGER_S_SHIFT (7U) -#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) -#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ETRIGGER_S_MASK (0x80U) -#define CSR_ETRIGGER_S_SHIFT (7U) -#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) -#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKS (RW) - * - * This bit controls the behavior of EBREAK instructions in Supervisor Mode. - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKS_MASK (0x2000U) -#define CSR_DCSR_EBREAKS_SHIFT (13U) -#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) -#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: PMACFG0 */ -/* - * PMA3CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) -#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) -#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) -#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) - -/* - * PMA2CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) -#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) -#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) -#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) - -/* - * PMA1CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) -#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) -#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) -#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) - -/* - * PMA0CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) -#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) -#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) -#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) - -/* Bitfield definition for register: PMACFG1 */ -/* - * PMA7CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) -#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) -#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) -#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) - -/* - * PMA6CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) -#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) -#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) -#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) - -/* - * PMA5CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) -#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) -#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) -#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) - -/* - * PMA4CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) -#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) -#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) -#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) - -/* Bitfield definition for register: PMACFG2 */ -/* - * PMA11CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) -#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) -#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) -#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) - -/* - * PMA10CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) -#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) -#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) -#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) - -/* - * PMA9CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) -#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) -#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) -#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) - -/* - * PMA8CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) -#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) -#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) -#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) - -/* Bitfield definition for register: PMACFG3 */ -/* - * PMA15CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) -#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) -#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) -#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) - -/* - * PMA14CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) -#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) -#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) -#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) - -/* - * PMA13CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) -#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) -#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) -#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) - -/* - * PMA12CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) -#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) -#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) -#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaaaaaaaaaa Reserved - * . . . . . . - * aaaa. . . aa011111111 Reserved - * aaaa. . . a0111111111 2^{12} - * aaaa. . . 01111111111 2^{13} - * . . . . . . - * aa01. . . 11111111111 2^{XLEN} - * a011. . . 11111111111 2^{XLEN+1} - * 0111. . . 11111111111 2^{XLEN+2} - * 1111. . . 11111111111 Reserved - */ -#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) -#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) -#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) -#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) -#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) -#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) -#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) -#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) -#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) -#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) -#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) -#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) -#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) -#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) -#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) -#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) -#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: SCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) -#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) -#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) -#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) -#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_IR_MASK (0x4U) -#define CSR_SCOUNTEREN_IR_SHIFT (2U) -#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) -#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_CY_MASK (0x1U) -#define CSR_SCOUNTEREN_CY_SHIFT (0U) -#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) -#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * PM (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MDCAUSE_PM_MASK (0x60U) -#define CSR_MDCAUSE_PM_SHIFT (5U) -#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) -#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) - -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * DC_WAROUND (RW) - * - * Cache Write-Around threshold - * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. - * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. - * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. - * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. - */ -#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) -#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) -#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) -#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) - -/* - * DC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) - -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * DPREF_EN (RW) - * - * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 - * 0:Disable hardware prefetch on load/store memory accesses - * 1:Enable hardware prefetch on load/store memory accesses - */ -#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) -#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) -#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) -#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) - -/* - * IPREF_EN (RW) - * - * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 - * 0:Disable hardware prefetch on instruction fetches - * 1:Enable hardware prefetch on instruction fetches - */ -#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) -#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) -#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) -#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * NBLD_EN (RW) - * - * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. - * 0:Load to memory regions are blocking. - * 1:Load to memory regions are non-blocking. - */ -#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) -#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) -#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) -#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) - -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: MSLIDELEG */ -/* - * PMOVI (RW) - * - * Delegate S-mode performance monitor overflow local interrupt to S-mode. - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) -#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) -#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) -#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Delegate S-mode bus read/write transaction error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) -#define CSR_MSLIDELEG_BWEI_SHIFT (17U) -#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) -#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Delegate S-mode slave-port ECC error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) -#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) -#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) -#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) - -/* Bitfield definition for register: MCLK_CTL */ -/* - * FUNIT (RW) - * - * Level 2 clock gating enable for function units listed in the following table. - * 16:integer arithmetic unit - * 17:integer permutation unit - * 18:integer mask unit - * 19:integer division unit - * 20:integer multiply and add unit - * 21:floating-point multiply and add - * unit - * 22:floating-point miscellaneous unit - * 23:floating-point division unit - * 24:load/store unit - * 31:25:Reserved - */ -#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) -#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) -#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) -#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) - -/* - * VI (RW) - * - * Level 1 clock gating enable for the vector/floating-point issue queues. - */ -#define CSR_MCLK_CTL_VI_MASK (0x8000U) -#define CSR_MCLK_CTL_VI_SHIFT (15U) -#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) -#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) - -/* - * VR (RW) - * - * Level 1 clock gating enable for the vector/floating-point register file. - */ -#define CSR_MCLK_CTL_VR_MASK (0x4000U) -#define CSR_MCLK_CTL_VR_SHIFT (14U) -#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) -#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) - -/* - * AQ (RW) - * - * Level 1 clock gating enable for ACE load/store queues. - */ -#define CSR_MCLK_CTL_AQ_MASK (0x2000U) -#define CSR_MCLK_CTL_AQ_SHIFT (13U) -#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) -#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) - -/* - * DQ (RW) - * - * Level 1 clock gating enable for data cache load/store queues. - */ -#define CSR_MCLK_CTL_DQ_MASK (0x1000U) -#define CSR_MCLK_CTL_DQ_SHIFT (12U) -#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) -#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) - -/* - * UQ (RW) - * - * Level 1 clock gating enable for uncached queues - */ -#define CSR_MCLK_CTL_UQ_MASK (0x800U) -#define CSR_MCLK_CTL_UQ_SHIFT (11U) -#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) -#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) - -/* - * FP (RW) - * - * Level 1 clock gating enable for scalar floating point issue unit and queues. - */ -#define CSR_MCLK_CTL_FP_MASK (0x400U) -#define CSR_MCLK_CTL_FP_SHIFT (10U) -#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) -#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) - -/* - * CLKGATE (RW) - * - * One-hot clock gating levels. - * 0:Level 1 clock gating in module level - * 1:Level 2 clock gating in unit level - * 2:Level 3 clock gating in VPU level - * 7:3:Reserved - */ -#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) -#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) -#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) -#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * SPF (RW) - * - * Indicates whether store page fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) -#define CSR_DEXC2DBG_SPF_SHIFT (18U) -#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) -#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) - -/* - * LPF (RW) - * - * Indicates whether load fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) -#define CSR_DEXC2DBG_LPF_SHIFT (17U) -#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) -#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) - -/* - * IPF (RW) - * - * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) -#define CSR_DEXC2DBG_IPF_SHIFT (16U) -#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) -#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * SEC (RW) - * - * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SEC_MASK (0x200U) -#define CSR_DEXC2DBG_SEC_SHIFT (9U) -#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) -#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: SLIE */ -/* - * PMOVI (RW) - * - * Enable S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_PMOVI_MASK (0x40000UL) -#define CSR_SLIE_PMOVI_SHIFT (18U) -#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) -#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_BWEI_MASK (0x20000UL) -#define CSR_SLIE_BWEI_SHIFT (17U) -#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) -#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Enable S-mode slave-port ECC error local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_IMECCI_MASK (0x10000UL) -#define CSR_SLIE_IMECCI_SHIFT (16U) -#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) -#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) - -/* Bitfield definition for register: SLIP */ -/* - * PMOVI (RW) - * - * Pending control and status of S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_PMOVI_MASK (0x40000UL) -#define CSR_SLIP_PMOVI_SHIFT (18U) -#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) -#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_BWEI_MASK (0x20000UL) -#define CSR_SLIP_BWEI_SHIFT (17U) -#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) -#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Pending control and status of S-mode slave-port ECC error local interrupt.. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_IMECCI_MASK (0x10000UL) -#define CSR_SLIP_IMECCI_SHIFT (16U) -#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) -#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) - -/* Bitfield definition for register: SDCAUSE */ -/* - * PM (RW) - * - * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0:User mode - * 1:Supervisor mode - * 2:Reserved - * 3:Machine mode - */ -#define CSR_SDCAUSE_PM_MASK (0x60U) -#define CSR_SDCAUSE_PM_SHIFT (5U) -#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) -#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) - -/* - * SDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. - * The value of SDCAUSE for precise exception: - * When scause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When scause == 2 (Illegal instruction): - * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When scause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When scause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of SDCAUSE for imprecise exception: - * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) -#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) -#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) -#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) - -/* Bitfield definition for register: SCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_SCCTLDATA_VA_MASK (0x1FU) -#define CSR_SCCTLDATA_VA_SHIFT (0U) -#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) -#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: SCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) -#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) -#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) -#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) -#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) -#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) -#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) -#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) -#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) -#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) -#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) -#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) -#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) -#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) -#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) -#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) -#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) -#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) -#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) -#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) -#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) -#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) -#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) -#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) -#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) -#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) -#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) -#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) -#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_IR_MASK (0x4U) -#define CSR_SCOUNTEROVF_IR_SHIFT (2U) -#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) -#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_CY_MASK (0x1U) -#define CSR_SCOUNTEROVF_CY_SHIFT (0U) -#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) -#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) -#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) -#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) -#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) -#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) -#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) -#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) -#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: SHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT3_SEL_SHIFT (4U) -#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) -#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) -#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT4_SEL_SHIFT (4U) -#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) -#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) -#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT5_SEL_SHIFT (4U) -#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) -#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) -#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT6_SEL_SHIFT (4U) -#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) -#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) -#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_dmamux_src.h deleted file mode 100644 index 0dc437c7f7e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_dmamux_src.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_SPI0_RX (0x0UL) -#define HPM_DMA_SRC_SPI0_TX (0x1UL) -#define HPM_DMA_SRC_SPI1_RX (0x2UL) -#define HPM_DMA_SRC_SPI1_TX (0x3UL) -#define HPM_DMA_SRC_SPI2_RX (0x4UL) -#define HPM_DMA_SRC_SPI2_TX (0x5UL) -#define HPM_DMA_SRC_SPI3_RX (0x6UL) -#define HPM_DMA_SRC_SPI3_TX (0x7UL) -#define HPM_DMA_SRC_UART0_RX (0x8UL) -#define HPM_DMA_SRC_UART0_TX (0x9UL) -#define HPM_DMA_SRC_UART1_RX (0xAUL) -#define HPM_DMA_SRC_UART1_TX (0xBUL) -#define HPM_DMA_SRC_UART2_RX (0xCUL) -#define HPM_DMA_SRC_UART2_TX (0xDUL) -#define HPM_DMA_SRC_UART3_RX (0xEUL) -#define HPM_DMA_SRC_UART3_TX (0xFUL) -#define HPM_DMA_SRC_UART4_RX (0x10UL) -#define HPM_DMA_SRC_UART4_TX (0x11UL) -#define HPM_DMA_SRC_UART5_RX (0x12UL) -#define HPM_DMA_SRC_UART5_TX (0x13UL) -#define HPM_DMA_SRC_UART6_RX (0x14UL) -#define HPM_DMA_SRC_UART6_TX (0x15UL) -#define HPM_DMA_SRC_UART7_RX (0x16UL) -#define HPM_DMA_SRC_UART7_TX (0x17UL) -#define HPM_DMA_SRC_UART8_RX (0x18UL) -#define HPM_DMA_SRC_UART8_TX (0x19UL) -#define HPM_DMA_SRC_UART9_RX (0x1AUL) -#define HPM_DMA_SRC_UART9_TX (0x1BUL) -#define HPM_DMA_SRC_UART10_RX (0x1CUL) -#define HPM_DMA_SRC_UART10_TX (0x1DUL) -#define HPM_DMA_SRC_UART11_RX (0x1EUL) -#define HPM_DMA_SRC_UART11_TX (0x1FUL) -#define HPM_DMA_SRC_UART12_RX (0x20UL) -#define HPM_DMA_SRC_UART12_TX (0x21UL) -#define HPM_DMA_SRC_UART13_RX (0x22UL) -#define HPM_DMA_SRC_UART13_TX (0x23UL) -#define HPM_DMA_SRC_UART14_RX (0x24UL) -#define HPM_DMA_SRC_UART14_TX (0x25UL) -#define HPM_DMA_SRC_UART15_RX (0x26UL) -#define HPM_DMA_SRC_UART15_TX (0x27UL) -#define HPM_DMA_SRC_I2S0_RX (0x28UL) -#define HPM_DMA_SRC_I2S0_TX (0x29UL) -#define HPM_DMA_SRC_I2S1_RX (0x2AUL) -#define HPM_DMA_SRC_I2S1_TX (0x2BUL) -#define HPM_DMA_SRC_I2S2_RX (0x2CUL) -#define HPM_DMA_SRC_I2S2_TX (0x2DUL) -#define HPM_DMA_SRC_I2S3_RX (0x2EUL) -#define HPM_DMA_SRC_I2S3_TX (0x2FUL) -#define HPM_DMA_SRC_MOT0_0 (0x30UL) -#define HPM_DMA_SRC_MOT0_1 (0x31UL) -#define HPM_DMA_SRC_MOT0_2 (0x32UL) -#define HPM_DMA_SRC_MOT0_3 (0x33UL) -#define HPM_DMA_SRC_MOT1_0 (0x34UL) -#define HPM_DMA_SRC_MOT1_1 (0x35UL) -#define HPM_DMA_SRC_MOT1_2 (0x36UL) -#define HPM_DMA_SRC_MOT1_3 (0x37UL) -#define HPM_DMA_SRC_MOT2_0 (0x38UL) -#define HPM_DMA_SRC_MOT2_1 (0x39UL) -#define HPM_DMA_SRC_MOT2_2 (0x3AUL) -#define HPM_DMA_SRC_MOT2_3 (0x3BUL) -#define HPM_DMA_SRC_MOT3_0 (0x3CUL) -#define HPM_DMA_SRC_MOT3_1 (0x3DUL) -#define HPM_DMA_SRC_MOT3_2 (0x3EUL) -#define HPM_DMA_SRC_MOT3_3 (0x3FUL) -#define HPM_DMA_SRC_NTMR0_0 (0x40UL) -#define HPM_DMA_SRC_NTMR0_1 (0x41UL) -#define HPM_DMA_SRC_NTMR0_2 (0x42UL) -#define HPM_DMA_SRC_NTMR0_3 (0x43UL) -#define HPM_DMA_SRC_NTMR1_0 (0x44UL) -#define HPM_DMA_SRC_NTMR1_1 (0x45UL) -#define HPM_DMA_SRC_NTMR1_2 (0x46UL) -#define HPM_DMA_SRC_NTMR1_3 (0x47UL) -#define HPM_DMA_SRC_GPTMR0_0 (0x48UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x49UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x4AUL) -#define HPM_DMA_SRC_GPTMR0_3 (0x4BUL) -#define HPM_DMA_SRC_GPTMR1_0 (0x4CUL) -#define HPM_DMA_SRC_GPTMR1_1 (0x4DUL) -#define HPM_DMA_SRC_GPTMR1_2 (0x4EUL) -#define HPM_DMA_SRC_GPTMR1_3 (0x4FUL) -#define HPM_DMA_SRC_GPTMR2_0 (0x50UL) -#define HPM_DMA_SRC_GPTMR2_1 (0x51UL) -#define HPM_DMA_SRC_GPTMR2_2 (0x52UL) -#define HPM_DMA_SRC_GPTMR2_3 (0x53UL) -#define HPM_DMA_SRC_GPTMR3_0 (0x54UL) -#define HPM_DMA_SRC_GPTMR3_1 (0x55UL) -#define HPM_DMA_SRC_GPTMR3_2 (0x56UL) -#define HPM_DMA_SRC_GPTMR3_3 (0x57UL) -#define HPM_DMA_SRC_GPTMR4_0 (0x58UL) -#define HPM_DMA_SRC_GPTMR4_1 (0x59UL) -#define HPM_DMA_SRC_GPTMR4_2 (0x5AUL) -#define HPM_DMA_SRC_GPTMR4_3 (0x5BUL) -#define HPM_DMA_SRC_GPTMR5_0 (0x5CUL) -#define HPM_DMA_SRC_GPTMR5_1 (0x5DUL) -#define HPM_DMA_SRC_GPTMR5_2 (0x5EUL) -#define HPM_DMA_SRC_GPTMR5_3 (0x5FUL) -#define HPM_DMA_SRC_GPTMR6_0 (0x60UL) -#define HPM_DMA_SRC_GPTMR6_1 (0x61UL) -#define HPM_DMA_SRC_GPTMR6_2 (0x62UL) -#define HPM_DMA_SRC_GPTMR6_3 (0x63UL) -#define HPM_DMA_SRC_GPTMR7_0 (0x64UL) -#define HPM_DMA_SRC_GPTMR7_1 (0x65UL) -#define HPM_DMA_SRC_GPTMR7_2 (0x66UL) -#define HPM_DMA_SRC_GPTMR7_3 (0x67UL) -#define HPM_DMA_SRC_I2C0 (0x68UL) -#define HPM_DMA_SRC_I2C1 (0x69UL) -#define HPM_DMA_SRC_I2C2 (0x6AUL) -#define HPM_DMA_SRC_I2C3 (0x6BUL) -#define HPM_DMA_SRC_XPI0_RX (0x6CUL) -#define HPM_DMA_SRC_XPI0_TX (0x6DUL) -#define HPM_DMA_SRC_XPI1_RX (0x6EUL) -#define HPM_DMA_SRC_XPI1_TX (0x6FUL) -#define HPM_DMA_SRC_ACMP_0 (0x70UL) -#define HPM_DMA_SRC_ACMP_1 (0x71UL) -#define HPM_DMA_SRC_ACMP_2 (0x72UL) -#define HPM_DMA_SRC_ACMP_3 (0x73UL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_enet_soc_drv.h deleted file mode 100644 index 18b35d6eb4d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_enet_soc_drv.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ENET_SOC_DRV_H -#define HPM_ENET_SOC_DRV_H - -#include "hpm_soc.h" - -#if defined __cplusplus -extern "C" { -#endif - -static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK; - HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(inf_type); - } else if (ptr == HPM_ENET1) { - HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK; - HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(inf_type); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else if (ptr == HPM_ENET1) { - HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else if (ptr == HPM_ENET1) { - HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); - HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); - } else if (ptr == HPM_ENET1) { - HPM_CONCTL->CTRL0 &= ~(CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK); - HPM_CONCTL->CTRL0 |= CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(tx_delay) | CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(rx_delay); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) -{ - hpm_stat_t stat = status_success; - - /* use an internal PLL clock as reference clock for rmii mode */ - if (ptr == HPM_ENET0) { - if (internal == true) { - /* use a pll clock */ - HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_REFCLK_OE_MASK | CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else { - /* use an external clock as reference clock for rmii mode */ - HPM_CONCTL->CTRL2 |= CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ - } - } else if (ptr == HPM_ENET1) { - if (internal == true) { - /* use a pll clock */ - HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_REFCLK_OE_MASK | CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK; - } else { - /* use an external clock as reference clock for rmii mode */ - HPM_CONCTL->CTRL3 |= CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK; /* use an external clock */ - } - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - /* use an internal PLL clock for rgmii mode */ - HPM_CONCTL->CTRL2 &= ~CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else if (ptr == HPM_ENET1) { - /* use an internal PLL clock for rgmii mode */ - HPM_CONCTL->CTRL3 &= ~CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -#if defined __cplusplus -} /* __cplusplus */ -#endif - -#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_gpiom_soc_drv.h deleted file mode 100644 index 79954c3d8fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_soc_gpio1 = 1, - gpiom_core0_fast = 2, - gpiom_core1_fast = 3, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_interrupt.h deleted file mode 100644 index db2de5a8356..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_interrupt.h +++ /dev/null @@ -1,877 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; - -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */ -#define CONTEXT_REG_NUM (4*(16 + 4 + 20*2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS */ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define HPM_EXTERN_C extern "C" -#else -#define HPM_EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -HPM_EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} - -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} -#endif -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - isr(); \ -} -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) \ -{ \ - isr();\ -} - - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_iomux.h deleted file mode 100644 index 7f386ba80e1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_iomux.h +++ /dev/null @@ -1,1666 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA00_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA00_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA00_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA01_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA01_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA01_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA02_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA02_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA02_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA03_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA03_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA03_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA03_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA04_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA04_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA04_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA04_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA04_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA05_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA05_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA05_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA05_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA05_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA06_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA06_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA06_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA06_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA07_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA07_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA07_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA08_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA08_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA09_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA09_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA09_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA09_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA10_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA10_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA10_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA10_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA11_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA11_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA11_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA11_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA11_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA12_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA12_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA12_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA12_FUNC_CTL_DIS0_B_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA12_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA13_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA13_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA13_FUNC_CTL_DIS0_B_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA13_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA14_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA14_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA14_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA14_FUNC_CTL_I2S2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA14_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA14_FUNC_CTL_DIS0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA15_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA15_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA15_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA15_FUNC_CTL_I2S2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA15_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA15_FUNC_CTL_DIS0_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA16_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA16_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA16_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA16_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA16_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA16_FUNC_CTL_DIS0_B_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA16_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA17_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA17_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA17_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA17_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA17_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA17_FUNC_CTL_DIS0_B_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA17_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA18_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA18_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA18_FUNC_CTL_DIS0_B_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA18_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA19_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA19_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA19_FUNC_CTL_I2S2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA19_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA19_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA19_FUNC_CTL_DIS0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA20_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA20_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA20_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA20_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA20_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA20_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA20_FUNC_CTL_DIS0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA21_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA21_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA21_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA21_FUNC_CTL_DIS0_R_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA22_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA22_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA22_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA22_FUNC_CTL_DIS0_G_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA22_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA23_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA23_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA23_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA23_FUNC_CTL_DIS0_G_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA23_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA24_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA24_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA24_FUNC_CTL_DIS0_G_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA24_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA25_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA25_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA25_FUNC_CTL_DIS0_G_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA25_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA26_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA26_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA26_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA26_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA26_FUNC_CTL_DIS0_R_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA27_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA27_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA27_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA27_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA27_FUNC_CTL_DIS0_R_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA28_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA28_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA28_FUNC_CTL_DIS0_R_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA28_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA29_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_I2S2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA29_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA29_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA29_FUNC_CTL_DIS0_G_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA29_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA30_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA30_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA30_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA30_FUNC_CTL_DIS0_G_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA30_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA31_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA31_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA31_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA31_FUNC_CTL_DIS0_R_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB00_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB00_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB00_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB00_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB00_FUNC_CTL_DIS0_R_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_I2S2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB01_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB01_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB01_FUNC_CTL_DIS0_G_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB01_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_I2S2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB02_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB02_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB02_FUNC_CTL_DIS0_B_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB03_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB03_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB03_FUNC_CTL_DIS0_R_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB03_FUNC_CTL_CAM1_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB04_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB04_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB04_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB04_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB04_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB04_FUNC_CTL_DIS0_R_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB04_FUNC_CTL_CAM1_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB05_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB05_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB05_FUNC_CTL_DIS0_B_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB05_FUNC_CTL_CAM1_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB06_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB06_FUNC_CTL_DIS0_G_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB06_FUNC_CTL_CAM1_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB06_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB07_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB07_FUNC_CTL_DIS0_B_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB07_FUNC_CTL_CAM1_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB07_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB08_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB08_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB08_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB08_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB08_FUNC_CTL_CAM1_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB09_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB09_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB09_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB09_FUNC_CTL_CAM1_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB10_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB10_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB10_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB10_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB10_FUNC_CTL_CAM1_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB11_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB11_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB11_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB11_FUNC_CTL_I2S3_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB11_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB11_FUNC_CTL_CAM1_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB12_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB12_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB12_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB12_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB12_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB12_FUNC_CTL_CAM1_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB13_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB13_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB13_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB13_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB13_FUNC_CTL_CAM1_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB14_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB14_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB14_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB14_FUNC_CTL_CAM1_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB15_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB15_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB15_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB15_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB16_FUNC_CTL function mux definitions */ -#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB16_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB16_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB16_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB17_FUNC_CTL function mux definitions */ -#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB17_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB17_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB17_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB17_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB18_FUNC_CTL function mux definitions */ -#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB18_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB18_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB18_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB18_FUNC_CTL_FEMC_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB19_FUNC_CTL function mux definitions */ -#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB19_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB19_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB19_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB19_FUNC_CTL_FEMC_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB20_FUNC_CTL function mux definitions */ -#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB20_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB20_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB20_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB20_FUNC_CTL_FEMC_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB20_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB21_FUNC_CTL function mux definitions */ -#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB21_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB21_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB21_FUNC_CTL_FEMC_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB21_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB22_FUNC_CTL function mux definitions */ -#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB22_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB22_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB22_FUNC_CTL_FEMC_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB22_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB23_FUNC_CTL function mux definitions */ -#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB23_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB23_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB23_FUNC_CTL_FEMC_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB23_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB24_FUNC_CTL function mux definitions */ -#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB24_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB24_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB24_FUNC_CTL_FEMC_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB24_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB25_FUNC_CTL function mux definitions */ -#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB25_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB25_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB25_FUNC_CTL_FEMC_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB25_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB26_FUNC_CTL function mux definitions */ -#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB26_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB26_FUNC_CTL_FEMC_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB26_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB27_FUNC_CTL function mux definitions */ -#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB27_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB27_FUNC_CTL_FEMC_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB27_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB28_FUNC_CTL function mux definitions */ -#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB28_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB28_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB28_FUNC_CTL_FEMC_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB28_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB29_FUNC_CTL function mux definitions */ -#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB29_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB29_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB29_FUNC_CTL_FEMC_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB29_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB30_FUNC_CTL function mux definitions */ -#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB30_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB30_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB30_FUNC_CTL_FEMC_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB30_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PB31_FUNC_CTL function mux definitions */ -#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB31_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB31_FUNC_CTL_FEMC_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PB31_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC00_FUNC_CTL function mux definitions */ -#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC00_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC00_FUNC_CTL_FEMC_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC00_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC01_FUNC_CTL function mux definitions */ -#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC01_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC01_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC01_FUNC_CTL_FEMC_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC01_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC02_FUNC_CTL function mux definitions */ -#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC02_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC02_FUNC_CTL_FEMC_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC02_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC03_FUNC_CTL function mux definitions */ -#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC03_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC03_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC03_FUNC_CTL_FEMC_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC03_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC04_FUNC_CTL function mux definitions */ -#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC04_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC04_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC04_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC05_FUNC_CTL function mux definitions */ -#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC05_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC05_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC05_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC06_FUNC_CTL function mux definitions */ -#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC06_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC06_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC06_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC07_FUNC_CTL function mux definitions */ -#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC07_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC07_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC07_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC07_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC08_FUNC_CTL function mux definitions */ -#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC08_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC08_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC08_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC08_FUNC_CTL_ETH1_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC09_FUNC_CTL function mux definitions */ -#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC09_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC09_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC09_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC09_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC09_FUNC_CTL_ETH1_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC10_FUNC_CTL function mux definitions */ -#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC10_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC10_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC10_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC10_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC11_FUNC_CTL function mux definitions */ -#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC11_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC11_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC11_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC11_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC12_FUNC_CTL function mux definitions */ -#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC12_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC12_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC12_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC12_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC13_FUNC_CTL function mux definitions */ -#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC13_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC13_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) - -/* IOC_PC14_FUNC_CTL function mux definitions */ -#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC14_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC14_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC14_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC14_FUNC_CTL_TRGM3_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC14_FUNC_CTL_ETH1_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC15_FUNC_CTL function mux definitions */ -#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC15_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC15_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC15_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC15_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC16_FUNC_CTL function mux definitions */ -#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC16_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC16_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC16_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC16_FUNC_CTL_TRGM2_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC17_FUNC_CTL function mux definitions */ -#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC17_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC17_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC17_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC17_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC18_FUNC_CTL function mux definitions */ -#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC18_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC18_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC18_FUNC_CTL_TRGM3_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC19_FUNC_CTL function mux definitions */ -#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC19_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC19_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC19_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC19_FUNC_CTL_TRGM3_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC19_FUNC_CTL_ETH1_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC20_FUNC_CTL function mux definitions */ -#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC20_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC20_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC20_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC20_FUNC_CTL_TRGM3_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC21_FUNC_CTL function mux definitions */ -#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC21_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC21_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC21_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC21_FUNC_CTL_TRGM2_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC22_FUNC_CTL function mux definitions */ -#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC22_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC22_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC22_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC22_FUNC_CTL_TRGM2_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC23_FUNC_CTL function mux definitions */ -#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC23_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC23_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC23_FUNC_CTL_TRGM3_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC23_FUNC_CTL_ETH1_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC24_FUNC_CTL function mux definitions */ -#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC24_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC24_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC24_FUNC_CTL_TRGM3_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC24_FUNC_CTL_ETH1_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC25_FUNC_CTL function mux definitions */ -#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC25_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC25_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC25_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC25_FUNC_CTL_TRGM2_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC26_FUNC_CTL function mux definitions */ -#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC26_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC26_FUNC_CTL_FEMC_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC26_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC26_FUNC_CTL_TRGM2_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC27_FUNC_CTL function mux definitions */ -#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC27_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC27_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC27_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC27_FUNC_CTL_ETH1_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC28_FUNC_CTL function mux definitions */ -#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC28_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC28_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC28_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC28_FUNC_CTL_ETH1_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC29_FUNC_CTL function mux definitions */ -#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC29_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC29_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC29_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC29_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC29_FUNC_CTL_ETH1_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PC30_FUNC_CTL function mux definitions */ -#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC30_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC30_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC30_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC30_FUNC_CTL_TRGM2_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PC31_FUNC_CTL function mux definitions */ -#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC31_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC31_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC31_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC31_FUNC_CTL_PWM2_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD00_FUNC_CTL function mux definitions */ -#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD00_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD00_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD00_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD00_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD01_FUNC_CTL function mux definitions */ -#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD01_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD01_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD01_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD01_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD01_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD01_FUNC_CTL_ETH1_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD02_FUNC_CTL function mux definitions */ -#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD02_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD02_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD02_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD02_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD02_FUNC_CTL_ETH1_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD03_FUNC_CTL function mux definitions */ -#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD03_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD03_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD03_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD04_FUNC_CTL function mux definitions */ -#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD04_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD04_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD04_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD04_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD05_FUNC_CTL function mux definitions */ -#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD05_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD05_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD05_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD06_FUNC_CTL function mux definitions */ -#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD06_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD06_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD07_FUNC_CTL function mux definitions */ -#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD07_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD07_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD07_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD08_FUNC_CTL function mux definitions */ -#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD08_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD08_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD08_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD08_FUNC_CTL_XPI1_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD08_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD08_FUNC_CTL_ETH1_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD09_FUNC_CTL function mux definitions */ -#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD09_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD09_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD09_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD09_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD09_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD10_FUNC_CTL function mux definitions */ -#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD10_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD10_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD10_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD10_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD10_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD10_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD11_FUNC_CTL function mux definitions */ -#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD11_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD11_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD11_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD11_FUNC_CTL_PWM3_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD11_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD12_FUNC_CTL function mux definitions */ -#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD12_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD12_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD12_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD12_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD12_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD13_FUNC_CTL function mux definitions */ -#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD13_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD13_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD13_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD13_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD13_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PD14_FUNC_CTL function mux definitions */ -#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD14_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD14_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD14_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD14_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD14_FUNC_CTL_PWM3_FAULT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD14_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD15_FUNC_CTL function mux definitions */ -#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD15_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD15_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD15_FUNC_CTL_PWM2_FAULT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD16_FUNC_CTL function mux definitions */ -#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD16_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD16_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD16_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD16_FUNC_CTL_TRGM2_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD16_FUNC_CTL_SDC1_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD16_FUNC_CTL_ETH1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD17_FUNC_CTL function mux definitions */ -#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD17_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD17_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD17_FUNC_CTL_TRGM3_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD17_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD17_FUNC_CTL_ETH1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD18_FUNC_CTL function mux definitions */ -#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD18_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD18_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD18_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD18_FUNC_CTL_TRGM3_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD18_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD18_FUNC_CTL_ETH1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD19_FUNC_CTL function mux definitions */ -#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD19_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD19_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD19_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD19_FUNC_CTL_TRGM2_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD19_FUNC_CTL_SDC1_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD19_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD20_FUNC_CTL function mux definitions */ -#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD20_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD20_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD20_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD20_FUNC_CTL_TRGM2_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD20_FUNC_CTL_SDC1_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD20_FUNC_CTL_ETH1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD21_FUNC_CTL function mux definitions */ -#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD21_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD21_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD21_FUNC_CTL_TRGM3_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD21_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD21_FUNC_CTL_ETH1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD22_FUNC_CTL function mux definitions */ -#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD22_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD22_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD22_FUNC_CTL_TRGM3_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD22_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD22_FUNC_CTL_ETH1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD23_FUNC_CTL function mux definitions */ -#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD23_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD23_FUNC_CTL_TRGM2_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD23_FUNC_CTL_SDC1_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD23_FUNC_CTL_ETH1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD24_FUNC_CTL function mux definitions */ -#define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD24_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD24_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD24_FUNC_CTL_TRGM2_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD24_FUNC_CTL_SDC1_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD24_FUNC_CTL_ETH1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD25_FUNC_CTL function mux definitions */ -#define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD25_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD25_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD25_FUNC_CTL_TRGM2_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD25_FUNC_CTL_SDC1_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD25_FUNC_CTL_ETH1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD26_FUNC_CTL function mux definitions */ -#define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD26_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD26_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD26_FUNC_CTL_TRGM3_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD26_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD26_FUNC_CTL_ETH1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD27_FUNC_CTL function mux definitions */ -#define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD27_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD27_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD27_FUNC_CTL_TRGM3_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD27_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD27_FUNC_CTL_ETH1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD28_FUNC_CTL function mux definitions */ -#define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD28_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD28_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD28_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD28_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD28_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD29_FUNC_CTL function mux definitions */ -#define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD29_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD29_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD29_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD29_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD29_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD30_FUNC_CTL function mux definitions */ -#define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD30_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD30_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD30_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD30_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD30_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD31_FUNC_CTL function mux definitions */ -#define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD31_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD31_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD31_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD31_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD31_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD31_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE00_FUNC_CTL function mux definitions */ -#define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE00_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE00_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE00_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE00_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE00_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE01_FUNC_CTL function mux definitions */ -#define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE01_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE01_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE01_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE01_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE01_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE02_FUNC_CTL function mux definitions */ -#define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE02_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE02_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE02_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE02_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE02_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE03_FUNC_CTL function mux definitions */ -#define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE03_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE03_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE03_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE03_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE03_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE03_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE04_FUNC_CTL function mux definitions */ -#define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE04_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE04_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE04_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE04_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE04_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE05_FUNC_CTL function mux definitions */ -#define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE05_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE05_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE05_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE05_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE05_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE06_FUNC_CTL function mux definitions */ -#define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE06_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE06_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE06_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE06_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE06_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE06_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE07_FUNC_CTL function mux definitions */ -#define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE07_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE07_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE07_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE07_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE07_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE08_FUNC_CTL function mux definitions */ -#define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE08_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE08_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE08_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE08_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE09_FUNC_CTL function mux definitions */ -#define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE09_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE09_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE09_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE09_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE09_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE09_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE10_FUNC_CTL function mux definitions */ -#define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE10_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE10_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE10_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE10_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE10_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE11_FUNC_CTL function mux definitions */ -#define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE11_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE11_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE11_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE11_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE11_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE11_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE12_FUNC_CTL function mux definitions */ -#define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE12_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE12_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE12_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE12_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE12_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PE13_FUNC_CTL function mux definitions */ -#define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE13_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE13_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE13_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE13_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PE13_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PE14_FUNC_CTL function mux definitions */ -#define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE14_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE14_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE14_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE14_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE14_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE14_FUNC_CTL_ETH1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE15_FUNC_CTL function mux definitions */ -#define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE15_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE15_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE15_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE15_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE15_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE15_FUNC_CTL_ETH1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE15_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE16_FUNC_CTL function mux definitions */ -#define IOC_PE16_FUNC_CTL_GPIO_E_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE16_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE16_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE16_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE16_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE16_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE16_FUNC_CTL_ETH1_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE17_FUNC_CTL function mux definitions */ -#define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE17_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE17_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE17_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE17_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE17_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE17_FUNC_CTL_ETH1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE17_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE18_FUNC_CTL function mux definitions */ -#define IOC_PE18_FUNC_CTL_GPIO_E_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE18_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE18_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE18_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE18_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE18_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE18_FUNC_CTL_ETH1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE18_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE19_FUNC_CTL function mux definitions */ -#define IOC_PE19_FUNC_CTL_GPIO_E_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE19_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE19_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE19_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE19_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE19_FUNC_CTL_ETH1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE19_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE20_FUNC_CTL function mux definitions */ -#define IOC_PE20_FUNC_CTL_GPIO_E_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE20_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE20_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE20_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE20_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE20_FUNC_CTL_ETH1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE20_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE21_FUNC_CTL function mux definitions */ -#define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE21_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE21_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE21_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE21_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE21_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE22_FUNC_CTL function mux definitions */ -#define IOC_PE22_FUNC_CTL_GPIO_E_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE22_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE22_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE22_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE22_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE22_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE22_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE23_FUNC_CTL function mux definitions */ -#define IOC_PE23_FUNC_CTL_GPIO_E_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE23_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE23_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE23_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE23_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE23_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE23_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE23_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE24_FUNC_CTL function mux definitions */ -#define IOC_PE24_FUNC_CTL_GPIO_E_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE24_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE24_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE24_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE24_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE24_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE25_FUNC_CTL function mux definitions */ -#define IOC_PE25_FUNC_CTL_GPIO_E_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE25_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE25_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE25_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE25_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE25_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE26_FUNC_CTL function mux definitions */ -#define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE26_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE26_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE26_FUNC_CTL_CAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE26_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE26_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE26_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE27_FUNC_CTL function mux definitions */ -#define IOC_PE27_FUNC_CTL_GPIO_E_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE27_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE27_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE27_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE27_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE27_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE27_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE27_FUNC_CTL_ETH1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE28_FUNC_CTL function mux definitions */ -#define IOC_PE28_FUNC_CTL_GPIO_E_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE28_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE28_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE28_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE28_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE28_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE28_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE28_FUNC_CTL_ETH1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE29_FUNC_CTL function mux definitions */ -#define IOC_PE29_FUNC_CTL_GPIO_E_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE29_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE29_FUNC_CTL_CAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE29_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE29_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE30_FUNC_CTL function mux definitions */ -#define IOC_PE30_FUNC_CTL_GPIO_E_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE30_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE30_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE30_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE30_FUNC_CTL_USB1_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE31_FUNC_CTL function mux definitions */ -#define IOC_PE31_FUNC_CTL_GPIO_E_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE31_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE31_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE31_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PF00_FUNC_CTL function mux definitions */ -#define IOC_PF00_FUNC_CTL_GPIO_F_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF00_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF00_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF00_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF00_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF00_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF00_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF01_FUNC_CTL function mux definitions */ -#define IOC_PF01_FUNC_CTL_GPIO_F_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF01_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF01_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF01_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF01_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF01_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF01_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF02_FUNC_CTL function mux definitions */ -#define IOC_PF02_FUNC_CTL_GPIO_F_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF02_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF02_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF02_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF02_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF02_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF03_FUNC_CTL function mux definitions */ -#define IOC_PF03_FUNC_CTL_GPIO_F_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF03_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF03_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF03_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF03_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PF04_FUNC_CTL function mux definitions */ -#define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF04_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF04_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF04_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF04_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PF05_FUNC_CTL function mux definitions */ -#define IOC_PF05_FUNC_CTL_GPIO_F_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF05_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF05_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF05_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF05_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF05_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PF05_FUNC_CTL_USB1_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF06_FUNC_CTL function mux definitions */ -#define IOC_PF06_FUNC_CTL_GPIO_F_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF06_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF06_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF06_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF06_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF06_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PF06_FUNC_CTL_USB1_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF07_FUNC_CTL function mux definitions */ -#define IOC_PF07_FUNC_CTL_GPIO_F_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF07_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF07_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF07_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF07_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF07_FUNC_CTL_USB1_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF08_FUNC_CTL function mux definitions */ -#define IOC_PF08_FUNC_CTL_GPIO_F_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF08_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF08_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF08_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF08_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF09_FUNC_CTL function mux definitions */ -#define IOC_PF09_FUNC_CTL_GPIO_F_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF09_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF09_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF09_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF09_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF09_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF09_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PF09_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF10_FUNC_CTL function mux definitions */ -#define IOC_PF10_FUNC_CTL_GPIO_F_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF10_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF10_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF10_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF10_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF10_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX00_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PX01_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX01_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX02_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX03_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX04_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PX04_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX05_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PX06_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX08_FUNC_CTL function mux definitions */ -#define IOC_PX08_FUNC_CTL_GPIO_X_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX08_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX08_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX09_FUNC_CTL function mux definitions */ -#define IOC_PX09_FUNC_CTL_GPIO_X_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX09_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX09_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX10_FUNC_CTL function mux definitions */ -#define IOC_PX10_FUNC_CTL_GPIO_X_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX10_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX11_FUNC_CTL function mux definitions */ -#define IOC_PX11_FUNC_CTL_GPIO_X_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX11_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY00_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY00_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY00_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY01_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY01_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY02_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY02_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY03_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY04_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY04_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY04_FUNC_CTL_CAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY04_FUNC_CTL_DAOL_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PY04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY05_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY05_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY05_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY05_FUNC_CTL_DAOL_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PY05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY06_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY07_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY08_FUNC_CTL_DAOR_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PY08_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PY09_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY10_FUNC_CTL_CAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY10_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PY10_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY11_FUNC_CTL_CAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY11_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PY11_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ02_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ03_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ04_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PZ04_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ05_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ06_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PZ06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PZ07_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ08_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PZ08_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PZ09_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ10_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ10_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PZ10_FUNC_CTL_ACMP_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ11_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ11_FUNC_CTL_CAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PZ11_FUNC_CTL_ACMP_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_l1c_drv.h deleted file mode 100644 index 1f1a21639a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 32KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 64B */ -#define HPM_L1C_CACHELINE_SIZE (64) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_misc.h deleted file mode 100644 index 0197bf37f8c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_misc.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define ILM_LOCAL_BASE (0x0U) -#define ILM_SIZE_IN_BYTE (0x40000U) -#define DLM_LOCAL_BASE (0x80000U) -#define DLM_SIZE_IN_BYTE (0x40000U) -#define CORE0_ILM_SYSTEM_BASE (0x1000000U) -#define CORE0_DLM_SYSTEM_BASE (0x1040000U) -#define CORE1_ILM_SYSTEM_BASE (0x1180000U) -#define CORE1_DLM_SYSTEM_BASE (0x11C0000U) - -#define ADDRESS_IN_ILM(address) \ - ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_DLM(address) \ - (((DLM_LOCAL_BASE) <= (address)) && \ - ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address))) - -#define ADDRESS_IN_CORE0_ILM_SYSTEM(address) \ - (((CORE0_ILM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address))) -#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - (((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address))) - -#define ADDRESS_IN_CORE1_ILM_SYSTEM(address) \ - (((CORE1_ILM_SYSTEM_BASE) <= (address)) && \ - ((CORE1_ILM_SYSTEM_BASE + ILM_SIZE_IN_BYTE) > (address))) -#define ADDRESS_IN_CORE1_DLM_SYSTEM(address) \ - (((CORE1_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE1_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address))) - -#define DLM_TO_SYSTEM(address) \ - (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) -#define ILM_TO_SYSTEM(address) \ - (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) -#define SYSTEM_TO_DLM(address) \ - ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) - -#define HPM_CORE0 (0U) -#define HPM_CORE1 (1U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - uint32_t sys_addr; - if (ADDRESS_IN_ILM(addr)) { - sys_addr = ILM_TO_SYSTEM(addr); - } else if (ADDRESS_IN_DLM(addr)) { - sys_addr = DLM_TO_SYSTEM(addr); - } else { - return addr; - } - if (core_id == HPM_CORE1) { - sys_addr += CORE1_ILM_SYSTEM_BASE - CORE0_ILM_SYSTEM_BASE; - } - - return sys_addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - if (core_id == HPM_CORE1) { - if (ADDRESS_IN_CORE1_DLM_SYSTEM(addr)) { - addr = (addr - CORE1_DLM_SYSTEM_BASE) + DLM_LOCAL_BASE; - } else if (ADDRESS_IN_CORE1_ILM_SYSTEM(addr)) { - addr = (addr - CORE1_ILM_SYSTEM_BASE) + ILM_LOCAL_BASE; - } - } else { - if (ADDRESS_IN_CORE0_DLM_SYSTEM(addr)) { - addr = (addr - CORE0_DLM_SYSTEM_BASE) + DLM_LOCAL_BASE; - } else if (ADDRESS_IN_CORE0_ILM_SYSTEM(addr)) { - addr = (addr - CORE0_ILM_SYSTEM_BASE) + ILM_LOCAL_BASE; - } - } - - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_otp_drv.c deleted file mode 100644 index f16c4c1b231..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* -* Copyright (c) 2021-2024 HPMicro -* -* SPDX-License-Identifier: BSD-3-Clause -* -*/ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" -#include "hpm_clock_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP->SHADOW[addr] : HPM_OTPSHW->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - clock_cpu_delay_ms(1); - - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = (addr <= SHADOW_INDEX_IN_PMIC_OTP_END) ? HPM_OTP : HPM_OTPSHW; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_otp_drv.h deleted file mode 100644 index fe647ac5e86..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_otp_drv.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - - /** - * @brief Initialize OTP controller - */ - void otp_init(void); - - /** - * @brief De-initialize OTP controller - */ - void otp_deinit(void); - - /** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ - uint32_t otp_read_from_shadow(uint32_t addr); - - /** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ - uint32_t otp_read_from_ip(uint32_t addr); - - /** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ - hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - - /** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ - hpm_stat_t otp_reload(otp_region_t region); - - /** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ - hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - - - /** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ - hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - - /** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ - hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - - /** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [in] val Data to be written - * @return API execution status - */ - hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_pcfg_drv.h deleted file mode 100644 index 72d7a5f5e84..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_pcfg_drv.h +++ /dev/null @@ -1,644 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW (0x1UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) -#define PCFG_PERIPH_SET_CLOCK_AUTO(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_FOLLOW_FLOW << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_fuse = 0, - pcfg_pmc_periph_ram = 2, - pcfg_pmc_periph_vad = 4, - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, - pcfg_pmc_periph_debug = 16, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE0 (PCFG_DEBUG_STOP_CPU0_MASK) -#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE0 (0) -#define PCFG_DEBUG_STOP_SOURCE_ENABLE_CORE1 (PCFG_DEBUG_STOP_CPU1_MASK) -#define PCFG_DEBUG_STOP_SOURCE_DISABLE_CORE1 (0) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap enable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief bandgap enable low power mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - * @param[in] over_limit unused parameter, will be discarded - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) -{ - (void) over_limit; - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - -/** - * @brief disable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief enable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/** - * @brief Disable CPU0 debug stop notficiation to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_disable_cpu0_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU0_MASK; -} - -/** - * @brief Enable CPU0 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_enable_cpu0_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU0_MASK; -} - -/** - * @brief Disable CPU1 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_disable_cpu1_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP &= ~PCFG_DEBUG_STOP_CPU1_MASK; -} - -/** - * @brief Enable CPU1 debug stop notification to peripherals - * - * @param[in] ptr - */ -static inline void pcfg_enable_cpu1_debug_stop_notfication(PCFG_Type *ptr) -{ - ptr->DEBUG_STOP |= PCFG_DEBUG_STOP_CPU1_MASK; -} - -/** - * @brief Configure CPU core debug stop notification to peripherals - * - * @param[in] ptr - * @param[in] mask - */ -static inline void pcfg_config_debug_stop_notification(PCFG_Type *ptr, uint8_t mask) -{ - ptr->DEBUG_STOP = mask; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief dcdc switch to dcm mode - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_switch_to_dcm_mode(PCFG_Type *ptr) -{ - const uint8_t pcfc_dcdc_min_duty_cycle[] = { - 0x6E, 0x6E, 0x70, 0x70, 0x70, 0x70, 0x72, 0x72, - 0x72, 0x72, 0x74, 0x74, 0x74, 0x74, 0x76, 0x76, - 0x76, 0x78, 0x78, 0x78, 0x78, 0x7A, 0x7A, 0x7A, - 0x7A, 0x7C, 0x7C, 0x7C, 0x7E, 0x7E, 0x7E, 0x7E - }; - uint16_t voltage; - - ptr->DCDC_MODE |= 0x77000u; - ptr->DCDC_ADVMODE = (ptr->DCDC_ADVMODE & ~0x73F0067u) | 0x4120067u; - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_SHORT_CURRENT_MASK; - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_SHORT_MASK; - ptr->DCDC_MISC = 0x100000u; - voltage = PCFG_DCDC_MODE_VOLT_GET(ptr->DCDC_MODE); - voltage = (voltage - 600) / 25; - ptr->DCDC_ADVPARAM = (ptr->DCDC_ADVPARAM & ~PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) | PCFG_DCDC_ADVPARAM_MIN_DUT_SET(pcfc_dcdc_min_duty_cycle[voltage]); -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_plic_drv.h deleted file mode 100644 index 9595051f906..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_plic_drv.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_pmic_iomux.h deleted file mode 100644 index 2a8c98bd6ed..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_pmic_iomux.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_PUART_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_PUART_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ppor_drv.h deleted file mode 100644 index 687508cc684..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ppor_drv.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_wdog2 = 1 << 18, - ppor_reset_wdog3 = 1 << 19, - ppor_reset_pmic_wdog = 1 << 20, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_COLD |= mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_COLD &= ~mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOT |= mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOT &= ~mask; -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_romapi.h deleted file mode 100644 index 5f226b0847e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_romapi.h +++ /dev/null @@ -1,1016 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_sdp_drv.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3040000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ -/* XPI1 base address */ -#define HPM_XPI1_BASE (0xF3044000UL) /**< XPI1 Base address */ -/* XPI1 base pointer */ -#define HPM_XPI1 ((XPI_Type *) HPM_XPI1_BASE) /**< XPI1 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -typedef struct { - uint32_t _internal[138]; -} sm3_context_t; - -#define SM4_ENCRYPT 1 -#define SM4_DECRYPT 0 - -typedef struct { - uint32_t mode; - uint32_t _internal[116]; -} sm4_context_t; - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, uint32_t serial_root_clk_freq, uint32_t data_valid_time, xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, - uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t *dst, - uint32_t start, uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, uint32_t dst_addr, uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief XPI RAM driver interface - */ -typedef struct { - /**< XPI RAM driver interface: API version */ - uint32_t version; - - /**< Get XPI RAM configuration based on cfg_option */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); - - /**< XPI RAM driver interface: Initialize XPI RAM */ - hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); -} xpi_ram_driver_interface_t; - -/** - * @brief SDP API interface - */ -typedef struct { - /**< SDP API interface: API version */ - uint32_t version; - /**< SDP API interface: Initialize IP */ - hpm_stat_t (*sdp_ip_init)(void); - /**< SDP API interface: Deinitialize IP */ - hpm_stat_t (*sdp_ip_deinit)(void); - /**< SDP API interface: Set AES key */ - hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: AES ECB crypto operation */ - hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API interface: AES CBC crypto operation */ - hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, uint8_t iv[16], - const uint8_t *input, uint8_t *output); - /**< SDP API interface: AES CTR crypto operation */ - hpm_stat_t (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, - uint32_t length); - /**< SDP API interface: AES CCM encryption */ - hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *nonce, uint32_t nonce_len, - const uint8_t *aad, uint32_t aad_len, const uint8_t *input, uint8_t *output, - uint8_t *tag, uint32_t tag_len); - /**< SDP API interface: AES CCM Decrypt and verify */ - hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, uint32_t input_len, const uint8_t *nonce, - uint32_t nonce_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len); - /**< SDP API interface: memcpy */ - hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); - /**< SDP API interface: memset */ - hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); - /**< SDP API interface: HASH initialization */ - hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - /**< SDP API interface: HASH update */ - hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - /**< SDP API interface: HASH finish */ - hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); -} sdp_driver_interface_t; - -typedef struct { - /**< SM3 API version*/ - uint32_t version; - /**< SM3 API itnerface: HASH Initialization */ - hpm_stat_t (*init)(sm3_context_t *ctx); - /**< SM3 API interface: HASH update */ - hpm_stat_t (*update)(sm3_context_t *ctx, const void *input, uint32_t len); - /**< SM3 API interface: HASH finish */ - hpm_stat_t (*finalize)(sm3_context_t *ctx, uint8_t output[32]); -} sm3_api_interface_t; - -typedef struct { - /**< SM4 API interface: Version */ - uint32_t version; - /**< SM4 API interface: Set encryption key */ - void (*setkey_enc)(sm4_context_t *ctx, const uint8_t key[16]); - /**< SM4 API interface: Set decryption key */ - void (*setkey_dec)(sm4_context_t *ctx, const uint8_t key[16]); - /**< SM4 API interface: SM4 ECB operation */ - hpm_stat_t (*crypt_ecb)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, uint8_t *output); - /**< SM4 API interface: SM4 CBC operation */ - hpm_stat_t (*crypt_cbc)(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], - const uint8_t *input, uint8_t *output); - /**< SM4 API interface: SM4 CTR operation */ - hpm_stat_t (*crypt_ctr)(sm4_context_t *ctx, uint8_t *nonce_counter, const uint8_t *input, - uint8_t *output, uint32_t length); - /**< SM4 API interface: SM4 CCB encryption */ - hpm_stat_t (*ccm_gen_enc)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, uint8_t *tag, uint32_t tag_len); - /**< SM4 API interface: SM4 CCM Decryption and verifying */ - hpm_stat_t (*ccm_dec_verify)(sm4_context_t *ctx, uint32_t input_len, const uint8_t *iv, - uint32_t iv_len, const uint8_t *aad, uint32_t aad_len, const uint8_t *input, - uint8_t *output, const uint8_t *tag, uint32_t tag_len); -} sm4_api_interface_t; - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const xpi_ram_driver_interface_t *xpi_ram_driver_if; - /**< Bootloader API table: sdp driver interface address */ - const sdp_driver_interface_t *sdp_driver_if; - const uint32_t reserved0; - const sm3_api_interface_t *sm3_api_if; /* SM3 driver interface address */ - const sm4_api_interface_t *sm4_api_if; /* SM4 driver itnerface address */ -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); - fencei(); - return status; -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, uint32_t dst_addr, uint32_t length) -{ - hpm_stat_t - status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); - fencei(); - return status; -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, const uint32_t *src, - uint32_t dst_addr, uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->page_program_nonblocking(base, channel, nor_config, src, dst_addr, - length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API exection address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, uint32_t start, uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - if (((base != HPM_XPI0) && (base != HPM_XPI1)) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) - || ((offset & 0xFFF) != 0)) { - return false; - } - static const uint8_t k_mc_xpi_remap_config[] = { - 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, - 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, - 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, - }; - typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); - remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; - bool result = cb(base, start, len, offset); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_disable[] = { - 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, - 0xf5, 0x42, 0x82, 0x80, - }; - typedef void (*remap_disable_cb_t)(XPI_Type *); - remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; - cb(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_enabled[] = { - 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, - }; - typedef bool (*remap_chk_cb_t)(XPI_Type *); - remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; - return chk_cb(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - if ((base != HPM_XPI0) && (base != HPM_XPI1)) { - return false; - } - static const uint8_t k_mc_exip_region_config[] = { - 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, - 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, - 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, - 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, - 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, - 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, - 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, - 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, - 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, - }; - typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); - exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; - cb(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return true; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - static const uint8_t k_mc_exip_region_disable[] = { - 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, - 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, - 0xe7, 0xd0, 0x82, 0x80 - }; - typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); - exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; - cb(base, index); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_enable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, - 0xf5, 0xc0, 0x82, 0x80 - }; - typedef void (*exip_enable_cb_t)(XPI_Type *); - exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; - cb(base); -} - -/** - * @brief Disable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_disable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, - 0x82, 0x80 - }; - typedef void (*exip_disable_cb_t)(XPI_Type *); - exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; - cb(base); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/*********************************************************************************************************************** - * - * - * XPI RAM Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Get XPI RAM configuration based on cfg_option - * @param [in] base XPI base address - * @param [out] ram_cfg XPI RAM configuration structure - * @param [in] cfg_option XPI RAM configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, xpi_ram_config_t *ram_cfg, - xpi_ram_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); -} - -/** - * @brief Initialize XPI RAM - * @param [in] base XPI base address - * @param [in] ram_cfg XPI ram configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); -} - -/*********************************************************************************************************************** - * - * - * SDP Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Initialize SDP IP - */ -static inline void rom_sdp_init(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); -} - -/** - * @brief De-initialize SDP IP - */ -static inline void rom_sdp_deinit(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); -} - -/** - * @brief Set AES key to SDP - * @param [in] aes_ctx AES context - * @param [in] key AES key buffer - * @param [in] key_bits AES key-bit option - * @param[in] key_idx AES key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, - sdp_aes_key_bits_t key_bits, uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] len Data length for AES encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, - uint32_t len, const uint8_t *in, uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] length Data length for AES encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t length, uint8_t iv[16], - const uint8_t *in, uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); -} - -/** - * @brief HASH initialization - * @param [in] hash_ctx HASH context - * @param [in] alg HASH algorithm - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); -} - -/** - * @brief HASH Update - * @param [in] hash_ctx HASH context - * @param [in] data Data for HASH operation - * @param [in] length of the data for HASH operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); -} - -/** - * @brief HASH finialize - * @param [in] hash_ctx HASH context - * @param [out] digest the output digest - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); -} - -/** - * @brief SDP memcpy operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memcpy - * @param [in] src Source address for memcpy - * @param [in] length Size of data for memcpy operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); -} - -/** - * @brief SDP memset operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memset - * @param [in] pattern pattern for memset - * @param [in] length Size of data for memset operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); -} - - -/*********************************************************************************************************************** - * - * - * SM3 Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief SM4 initialization - * - * @param [in] ctx SM3 context - * @return API execution status - */ -static inline hpm_stat_t rom_sm3_init(sm3_context_t *ctx) -{ - return ROM_API_TABLE_ROOT->sm3_api_if->init(ctx); -} - -/** - * @brief SM3 update operation - * - * @param [in,out] ctx SM3 context - * @param [in] input Data for SM3 calculation - * @param [in] len length of the data for SM3 calculation - * @return API execution status - */ -static inline hpm_stat_t rom_sm3_update(sm3_context_t *ctx, const void *input, uint32_t len) -{ - return ROM_API_TABLE_ROOT->sm3_api_if->update(ctx, input, len); -} - -/** - * @brief SM3 finalize - * Return the computing SM3 digest - * - * @param [in] ctx SM3 context - * @param [out] output SM3 digest calculated by the above API - * @return API execution status - */ -static inline hpm_stat_t rom_sm3_finalize(sm3_context_t *ctx, uint8_t output[32]) -{ - return ROM_API_TABLE_ROOT->sm3_api_if->finalize(ctx, output); -} - -/*********************************************************************************************************************** - * - * - * SM4 Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Set SM4 encryption key - * - * @param [in] ctx SM4 context - * @param [in] key SM4 encryption key - */ -static inline void rom_sm4_setkey_enc(sm4_context_t *ctx, const uint8_t key[16]) -{ - ROM_API_TABLE_ROOT->sm4_api_if->setkey_enc(ctx, key); -} - -/** - * @brief Set SM4 decryption key - * - * @param [in] ctx SM4 context - * @param [in] key SM4 decryption key - */ -static inline void rom_sm4_setkey_dec(sm4_context_t *ctx, const uint8_t key[16]) -{ - ROM_API_TABLE_ROOT->sm4_api_if->setkey_dec(ctx, key); -} - -/** - * @brief SM4 ECB crypto operation(Encrypt or Decrypt) - * @param [in] ctx SM4 context - * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] input Input data - * @param [out] output Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sm4_crypt_ecb(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t *input, - uint8_t *output) -{ - return ROM_API_TABLE_ROOT->sm4_api_if->crypt_ecb(ctx, mode, length, input, output); -} - -/** - * @brief SM4 CBC crypto operation(Encrypt or Decrypt) - * @param [in] ctx SM4 context - * @param [in] mode SM4 operation: 1 - ENCRYPT, 0 - DECRYPT - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] iv The initial vector for SM4 CBC crypto operation - * @param [in] input Input data - * @param [out] output Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sm4_crypt_cbc(sm4_context_t *ctx, uint32_t mode, uint32_t length, const uint8_t iv[16], - const uint8_t *input, uint8_t *output) -{ - return ROM_API_TABLE_ROOT->sm4_api_if->crypt_cbc(ctx, mode, length, iv, input, output); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ea3ba9e8f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union { - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sdxc_soc_drv.h deleted file mode 100644 index a63f93b241f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sdxc_soc_drv.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDXC_SOC_DRV_H -#define HPM_SDXC_SOC_DRV_H - -#include "hpm_soc.h" -#include "hpm_sdxc_regs.h" - -#if defined(__cplusplus) -extern "C" { -#endif - -/** - * @brief Enable TMCLK (for Data timeout detection) -*/ -static inline void sdxc_enable_tm_clock(SDXC_Type *base) -{ - volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; - (*reg) |= (1UL << 10); -} - -/** - * @brief Wait at least 74 clocks until card is ready to receive the first command - */ -static inline void sdxc_wait_card_active(SDXC_Type *base) -{ - base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; - - while (!IS_HPM_BITMASK_SET(base->SYS_CTRL, SDXC_SYS_CTRL_SD_CLK_EN_MASK)) { - } - /* - * Assume that the BUS clock is 200MHz, while in the identification state, the SD clock is 400KHz. - * - Reading the register costs about 5ns in best case, hence the loop should be (74 / 400KHz) * 1000000000 / 5 - * - For robustness, use 50000 here - */ - for (volatile uint32_t i = 0; i < 50000U; i++) { - (void) base->CAPABILITIES1; - } -} - -static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) -{ - volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; - if (enable) { - *reg |= (1UL << 28); - } else { - *reg &= ~(1UL << 28); - } -} - -static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) -{ - volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; - return ((*reg) & (1UL << 28)) != 0U; -} - -static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool delay_from_pad) -{ - (void) base; - (void) delay_from_pad; -} - -static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t delay_chain) -{ - (void) base; - volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; - *reg = (*reg & ~CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) | - CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(delay_chain); -} - -static inline void sdxc_set_data_strobe_delay(SDXC_Type *base, uint32_t num_delaycells) -{ - (void) base; - volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; - *reg = (*reg & ~CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) | - CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(num_delaycells); - *reg |= CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK; -} - - -static inline uint32_t sdxc_get_default_strobe_delay(SDXC_Type *base) -{ - (void) base; - return 0; -} - -static inline void sdxc_set_rxclk_delay_chain(SDXC_Type *base, uint32_t num_delaycells) -{ - volatile uint32_t *reg = (base == HPM_SDXC0) ? &HPM_CONCTL->CTRL4 : &HPM_CONCTL->CTRL5; - *reg = (*reg & ~CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) | - CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(num_delaycells); - - *reg |= CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK; -} - -static inline uint32_t sdxc_get_default_cardclk_delay_chain(SDXC_Type *base, uint32_t clock_freq) -{ - (void) base; - uint32_t num_delaycells = 1; - if (clock_freq <= 52000000) { - num_delaycells = 13; - } - return num_delaycells; -} - -static inline bool sdxc_is_ddr50_supported(SDXC_Type *base) -{ - (void) base; - return false; -} - -#if defined(__cplusplus) -} -#endif - - -#endif /* HPM_SDXC_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ses_reg.xml deleted file mode 100644 index b97a4f6d523..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ses_reg.xml +++ /dev/null @@ -1,39399 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ses_riscv_cpu_regs.xml deleted file mode 100644 index ec5ba6cb980..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_ses_riscv_cpu_regs.xml +++ /dev/null @@ -1,1098 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc.h deleted file mode 100644 index d2f96bfe5ce..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc.h +++ /dev/null @@ -1,852 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ -#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ -#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */ -#define IRQn_GPIO1_A 10 /* GPIO1_A IRQ */ -#define IRQn_GPIO1_B 11 /* GPIO1_B IRQ */ -#define IRQn_GPIO1_C 12 /* GPIO1_C IRQ */ -#define IRQn_GPIO1_D 13 /* GPIO1_D IRQ */ -#define IRQn_GPIO1_E 14 /* GPIO1_E IRQ */ -#define IRQn_GPIO1_F 15 /* GPIO1_F IRQ */ -#define IRQn_GPIO1_X 16 /* GPIO1_X IRQ */ -#define IRQn_GPIO1_Y 17 /* GPIO1_Y IRQ */ -#define IRQn_GPIO1_Z 18 /* GPIO1_Z IRQ */ -#define IRQn_ADC0 19 /* ADC0 IRQ */ -#define IRQn_ADC1 20 /* ADC1 IRQ */ -#define IRQn_ADC2 21 /* ADC2 IRQ */ -#define IRQn_ADC3 22 /* ADC3 IRQ */ -#define IRQn_ACMP_0 23 /* ACMP[0] IRQ */ -#define IRQn_ACMP_1 24 /* ACMP[1] IRQ */ -#define IRQn_ACMP_2 25 /* ACMP[2] IRQ */ -#define IRQn_ACMP_3 26 /* ACMP[3] IRQ */ -#define IRQn_SPI0 27 /* SPI0 IRQ */ -#define IRQn_SPI1 28 /* SPI1 IRQ */ -#define IRQn_SPI2 29 /* SPI2 IRQ */ -#define IRQn_SPI3 30 /* SPI3 IRQ */ -#define IRQn_UART0 31 /* UART0 IRQ */ -#define IRQn_UART1 32 /* UART1 IRQ */ -#define IRQn_UART2 33 /* UART2 IRQ */ -#define IRQn_UART3 34 /* UART3 IRQ */ -#define IRQn_UART4 35 /* UART4 IRQ */ -#define IRQn_UART5 36 /* UART5 IRQ */ -#define IRQn_UART6 37 /* UART6 IRQ */ -#define IRQn_UART7 38 /* UART7 IRQ */ -#define IRQn_UART8 39 /* UART8 IRQ */ -#define IRQn_UART9 40 /* UART9 IRQ */ -#define IRQn_UART10 41 /* UART10 IRQ */ -#define IRQn_UART11 42 /* UART11 IRQ */ -#define IRQn_UART12 43 /* UART12 IRQ */ -#define IRQn_UART13 44 /* UART13 IRQ */ -#define IRQn_UART14 45 /* UART14 IRQ */ -#define IRQn_UART15 46 /* UART15 IRQ */ -#define IRQn_CAN0 47 /* CAN0 IRQ */ -#define IRQn_CAN1 48 /* CAN1 IRQ */ -#define IRQn_CAN2 49 /* CAN2 IRQ */ -#define IRQn_CAN3 50 /* CAN3 IRQ */ -#define IRQn_PTPC 51 /* PTPC IRQ */ -#define IRQn_WDG0 52 /* WDG0 IRQ */ -#define IRQn_WDG1 53 /* WDG1 IRQ */ -#define IRQn_WDG2 54 /* WDG2 IRQ */ -#define IRQn_WDG3 55 /* WDG3 IRQ */ -#define IRQn_MBX0A 56 /* MBX0A IRQ */ -#define IRQn_MBX0B 57 /* MBX0B IRQ */ -#define IRQn_MBX1A 58 /* MBX1A IRQ */ -#define IRQn_MBX1B 59 /* MBX1B IRQ */ -#define IRQn_GPTMR0 60 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 61 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 62 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 63 /* GPTMR3 IRQ */ -#define IRQn_GPTMR4 64 /* GPTMR4 IRQ */ -#define IRQn_GPTMR5 65 /* GPTMR5 IRQ */ -#define IRQn_GPTMR6 66 /* GPTMR6 IRQ */ -#define IRQn_GPTMR7 67 /* GPTMR7 IRQ */ -#define IRQn_I2C0 68 /* I2C0 IRQ */ -#define IRQn_I2C1 69 /* I2C1 IRQ */ -#define IRQn_I2C2 70 /* I2C2 IRQ */ -#define IRQn_I2C3 71 /* I2C3 IRQ */ -#define IRQn_PWM0 72 /* PWM0 IRQ */ -#define IRQn_HALL0 73 /* HALL0 IRQ */ -#define IRQn_QEI0 74 /* QEI0 IRQ */ -#define IRQn_PWM1 75 /* PWM1 IRQ */ -#define IRQn_HALL1 76 /* HALL1 IRQ */ -#define IRQn_QEI1 77 /* QEI1 IRQ */ -#define IRQn_PWM2 78 /* PWM2 IRQ */ -#define IRQn_HALL2 79 /* HALL2 IRQ */ -#define IRQn_QEI2 80 /* QEI2 IRQ */ -#define IRQn_PWM3 81 /* PWM3 IRQ */ -#define IRQn_HALL3 82 /* HALL3 IRQ */ -#define IRQn_QEI3 83 /* QEI3 IRQ */ -#define IRQn_SDP 84 /* SDP IRQ */ -#define IRQn_XPI0 85 /* XPI0 IRQ */ -#define IRQn_XPI1 86 /* XPI1 IRQ */ -#define IRQn_XDMA 87 /* XDMA IRQ */ -#define IRQn_HDMA 88 /* HDMA IRQ */ -#define IRQn_FEMC 89 /* FEMC IRQ */ -#define IRQn_RNG 90 /* RNG IRQ */ -#define IRQn_I2S0 91 /* I2S0 IRQ */ -#define IRQn_I2S1 92 /* I2S1 IRQ */ -#define IRQn_I2S2 93 /* I2S2 IRQ */ -#define IRQn_I2S3 94 /* I2S3 IRQ */ -#define IRQn_DAO 95 /* DAO IRQ */ -#define IRQn_PDM 96 /* PDM IRQ */ -#define IRQn_CAM0 97 /* CAM0 IRQ */ -#define IRQn_CAM1 98 /* CAM1 IRQ */ -#define IRQn_LCDC_D0 99 /* LCDC_D0 IRQ */ -#define IRQn_LCDC_D1 100 /* LCDC_D1 IRQ */ -#define IRQn_PDMA_D0 101 /* PDMA_D0 IRQ */ -#define IRQn_PDMA_D1 102 /* PDMA_D1 IRQ */ -#define IRQn_JPEG 103 /* JPEG IRQ */ -#define IRQn_NTMR0 104 /* NTMR0 IRQ */ -#define IRQn_NTMR1 105 /* NTMR1 IRQ */ -#define IRQn_USB0 106 /* USB0 IRQ */ -#define IRQn_USB1 107 /* USB1 IRQ */ -#define IRQn_ENET0 108 /* ENET0 IRQ */ -#define IRQn_ENET1 109 /* ENET1 IRQ */ -#define IRQn_SDXC0 110 /* SDXC0 IRQ */ -#define IRQn_SDXC1 111 /* SDXC1 IRQ */ -#define IRQn_PSEC 112 /* PSEC IRQ */ -#define IRQn_PGPIO 113 /* PGPIO IRQ */ -#define IRQn_PWDG 114 /* PWDG IRQ */ -#define IRQn_PTMR 115 /* PTMR IRQ */ -#define IRQn_PUART 116 /* PUART IRQ */ -#define IRQn_VAD 117 /* VAD IRQ */ -#define IRQn_FUSE 118 /* FUSE IRQ */ -#define IRQn_SECMON 119 /* SECMON IRQ */ -#define IRQn_RTC 120 /* RTC IRQ */ -#define IRQn_BUTN 121 /* BUTN IRQ */ -#define IRQn_BGPIO 122 /* BGPIO IRQ */ -#define IRQn_BVIO 123 /* BVIO IRQ */ -#define IRQn_BROWNOUT 124 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 125 /* SYSCTL IRQ */ -#define IRQn_DEBUG_0 126 /* DEBUG[0] IRQ */ -#define IRQn_DEBUG_1 127 /* DEBUG[1] IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0xC0000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF0000000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* GPIO1 base address */ -#define HPM_GPIO1_BASE (0xF0004000UL) -/* GPIO1 base pointer */ -#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF40DC000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) -/* BGPIO base address */ -#define HPM_BGPIO_BASE (0xF5014000UL) -/* BGPIO base pointer */ -#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF0008000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_adc12_regs.h" -/* Address of ADC12 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF0010000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC12_Type *) HPM_ADC0_BASE) -/* ADC1 base address */ -#define HPM_ADC1_BASE (0xF0014000UL) -/* ADC1 base pointer */ -#define HPM_ADC1 ((ADC12_Type *) HPM_ADC1_BASE) -/* ADC2 base address */ -#define HPM_ADC2_BASE (0xF0018000UL) -/* ADC2 base pointer */ -#define HPM_ADC2 ((ADC12_Type *) HPM_ADC2_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC3 base address */ -#define HPM_ADC3_BASE (0xF001C000UL) -/* ADC3 base pointer */ -#define HPM_ADC3 ((ADC16_Type *) HPM_ADC3_BASE) - -#include "hpm_acmp_regs.h" -/* Address of ACMP instances */ -/* ACMP base address */ -#define HPM_ACMP_BASE (0xF0020000UL) -/* ACMP base pointer */ -#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0030000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0034000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0038000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF003C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* UART4 base address */ -#define HPM_UART4_BASE (0xF0050000UL) -/* UART4 base pointer */ -#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) -/* UART5 base address */ -#define HPM_UART5_BASE (0xF0054000UL) -/* UART5 base pointer */ -#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) -/* UART6 base address */ -#define HPM_UART6_BASE (0xF0058000UL) -/* UART6 base pointer */ -#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) -/* UART7 base address */ -#define HPM_UART7_BASE (0xF005C000UL) -/* UART7 base pointer */ -#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) -/* UART8 base address */ -#define HPM_UART8_BASE (0xF0060000UL) -/* UART8 base pointer */ -#define HPM_UART8 ((UART_Type *) HPM_UART8_BASE) -/* UART9 base address */ -#define HPM_UART9_BASE (0xF0064000UL) -/* UART9 base pointer */ -#define HPM_UART9 ((UART_Type *) HPM_UART9_BASE) -/* UART10 base address */ -#define HPM_UART10_BASE (0xF0068000UL) -/* UART10 base pointer */ -#define HPM_UART10 ((UART_Type *) HPM_UART10_BASE) -/* UART11 base address */ -#define HPM_UART11_BASE (0xF006C000UL) -/* UART11 base pointer */ -#define HPM_UART11 ((UART_Type *) HPM_UART11_BASE) -/* UART12 base address */ -#define HPM_UART12_BASE (0xF0070000UL) -/* UART12 base pointer */ -#define HPM_UART12 ((UART_Type *) HPM_UART12_BASE) -/* UART13 base address */ -#define HPM_UART13_BASE (0xF0074000UL) -/* UART13 base pointer */ -#define HPM_UART13 ((UART_Type *) HPM_UART13_BASE) -/* UART14 base address */ -#define HPM_UART14_BASE (0xF0078000UL) -/* UART14 base pointer */ -#define HPM_UART14 ((UART_Type *) HPM_UART14_BASE) -/* UART15 base address */ -#define HPM_UART15_BASE (0xF007C000UL) -/* UART15 base pointer */ -#define HPM_UART15 ((UART_Type *) HPM_UART15_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF40E4000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_can_regs.h" -/* Address of CAN instances */ -/* CAN0 base address */ -#define HPM_CAN0_BASE (0xF0080000UL) -/* CAN0 base pointer */ -#define HPM_CAN0 ((CAN_Type *) HPM_CAN0_BASE) -/* CAN1 base address */ -#define HPM_CAN1_BASE (0xF0084000UL) -/* CAN1 base pointer */ -#define HPM_CAN1 ((CAN_Type *) HPM_CAN1_BASE) -/* CAN2 base address */ -#define HPM_CAN2_BASE (0xF0088000UL) -/* CAN2 base pointer */ -#define HPM_CAN2 ((CAN_Type *) HPM_CAN2_BASE) -/* CAN3 base address */ -#define HPM_CAN3_BASE (0xF008C000UL) -/* CAN3 base pointer */ -#define HPM_CAN3 ((CAN_Type *) HPM_CAN3_BASE) - -#include "hpm_wdg_regs.h" -/* Address of WDOG instances */ -/* WDG0 base address */ -#define HPM_WDG0_BASE (0xF0090000UL) -/* WDG0 base pointer */ -#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE) -/* WDG1 base address */ -#define HPM_WDG1_BASE (0xF0094000UL) -/* WDG1 base pointer */ -#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE) -/* WDG2 base address */ -#define HPM_WDG2_BASE (0xF0098000UL) -/* WDG2 base pointer */ -#define HPM_WDG2 ((WDG_Type *) HPM_WDG2_BASE) -/* WDG3 base address */ -#define HPM_WDG3_BASE (0xF009C000UL) -/* WDG3 base pointer */ -#define HPM_WDG3 ((WDG_Type *) HPM_WDG3_BASE) -/* PWDG base address */ -#define HPM_PWDG_BASE (0xF40E8000UL) -/* PWDG base pointer */ -#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) -/* MBX1A base address */ -#define HPM_MBX1A_BASE (0xF00A8000UL) -/* MBX1A base pointer */ -#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) -/* MBX1B base address */ -#define HPM_MBX1B_BASE (0xF00AC000UL) -/* MBX1B base pointer */ -#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) - -#include "hpm_ptpc_regs.h" -/* Address of PTPC instances */ -/* PTPC base address */ -#define HPM_PTPC_BASE (0xF00B0000UL) -/* PTPC base pointer */ -#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C0000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dma_regs.h" -/* Address of DMA instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C4000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE) -/* XDMA base address */ -#define HPM_XDMA_BASE (0xF3048000UL) -/* XDMA base pointer */ -#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE) - -#include "hpm_rng_regs.h" -/* Address of RNG instances */ -/* RNG base address */ -#define HPM_RNG_BASE (0xF00C8000UL) -/* RNG base pointer */ -#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF00CC000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_i2s_regs.h" -/* Address of I2S instances */ -/* I2S0 base address */ -#define HPM_I2S0_BASE (0xF0100000UL) -/* I2S0 base pointer */ -#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) -/* I2S1 base address */ -#define HPM_I2S1_BASE (0xF0104000UL) -/* I2S1 base pointer */ -#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) -/* I2S2 base address */ -#define HPM_I2S2_BASE (0xF0108000UL) -/* I2S2 base pointer */ -#define HPM_I2S2 ((I2S_Type *) HPM_I2S2_BASE) -/* I2S3 base address */ -#define HPM_I2S3_BASE (0xF010C000UL) -/* I2S3 base pointer */ -#define HPM_I2S3 ((I2S_Type *) HPM_I2S3_BASE) - -#include "hpm_dao_regs.h" -/* Address of DAO instances */ -/* DAO base address */ -#define HPM_DAO_BASE (0xF0110000UL) -/* DAO base pointer */ -#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) - -#include "hpm_pdm_regs.h" -/* Address of PDM instances */ -/* PDM base address */ -#define HPM_PDM_BASE (0xF0114000UL) -/* PDM base pointer */ -#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) - -#include "hpm_pwm_regs.h" -/* Address of PWM instances */ -/* PWM0 base address */ -#define HPM_PWM0_BASE (0xF0200000UL) -/* PWM0 base pointer */ -#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE) -/* PWM1 base address */ -#define HPM_PWM1_BASE (0xF0210000UL) -/* PWM1 base pointer */ -#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE) -/* PWM2 base address */ -#define HPM_PWM2_BASE (0xF0220000UL) -/* PWM2 base pointer */ -#define HPM_PWM2 ((PWM_Type *) HPM_PWM2_BASE) -/* PWM3 base address */ -#define HPM_PWM3_BASE (0xF0230000UL) -/* PWM3 base pointer */ -#define HPM_PWM3 ((PWM_Type *) HPM_PWM3_BASE) - -#include "hpm_hall_regs.h" -/* Address of HALL instances */ -/* HALL0 base address */ -#define HPM_HALL0_BASE (0xF0204000UL) -/* HALL0 base pointer */ -#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE) -/* HALL1 base address */ -#define HPM_HALL1_BASE (0xF0214000UL) -/* HALL1 base pointer */ -#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE) -/* HALL2 base address */ -#define HPM_HALL2_BASE (0xF0224000UL) -/* HALL2 base pointer */ -#define HPM_HALL2 ((HALL_Type *) HPM_HALL2_BASE) -/* HALL3 base address */ -#define HPM_HALL3_BASE (0xF0234000UL) -/* HALL3 base pointer */ -#define HPM_HALL3 ((HALL_Type *) HPM_HALL3_BASE) - -#include "hpm_qei_regs.h" -/* Address of QEI instances */ -/* QEI0 base address */ -#define HPM_QEI0_BASE (0xF0208000UL) -/* QEI0 base pointer */ -#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE) -/* QEI1 base address */ -#define HPM_QEI1_BASE (0xF0218000UL) -/* QEI1 base pointer */ -#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE) -/* QEI2 base address */ -#define HPM_QEI2_BASE (0xF0228000UL) -/* QEI2 base pointer */ -#define HPM_QEI2 ((QEI_Type *) HPM_QEI2_BASE) -/* QEI3 base address */ -#define HPM_QEI3_BASE (0xF0238000UL) -/* QEI3 base pointer */ -#define HPM_QEI3 ((QEI_Type *) HPM_QEI3_BASE) - -#include "hpm_trgm_regs.h" -/* Address of TRGM instances */ -/* TRGM0 base address */ -#define HPM_TRGM0_BASE (0xF020C000UL) -/* TRGM0 base pointer */ -#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) -/* TRGM1 base address */ -#define HPM_TRGM1_BASE (0xF021C000UL) -/* TRGM1 base pointer */ -#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE) -/* TRGM2 base address */ -#define HPM_TRGM2_BASE (0xF022C000UL) -/* TRGM2 base pointer */ -#define HPM_TRGM2 ((TRGM_Type *) HPM_TRGM2_BASE) -/* TRGM3 base address */ -#define HPM_TRGM3_BASE (0xF023C000UL) -/* TRGM3 base pointer */ -#define HPM_TRGM3 ((TRGM_Type *) HPM_TRGM3_BASE) - -#include "hpm_synt_regs.h" -/* Address of SYNT instances */ -/* SYNT base address */ -#define HPM_SYNT_BASE (0xF0240000UL) -/* SYNT base pointer */ -#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) - -#include "hpm_lcdc_regs.h" -/* Address of LCDC instances */ -/* LCDC base address */ -#define HPM_LCDC_BASE (0xF1000000UL) -/* LCDC base pointer */ -#define HPM_LCDC ((LCDC_Type *) HPM_LCDC_BASE) - -#include "hpm_cam_regs.h" -/* Address of CAM instances */ -/* CAM0 base address */ -#define HPM_CAM0_BASE (0xF1008000UL) -/* CAM0 base pointer */ -#define HPM_CAM0 ((CAM_Type *) HPM_CAM0_BASE) -/* CAM1 base address */ -#define HPM_CAM1_BASE (0xF100C000UL) -/* CAM1 base pointer */ -#define HPM_CAM1 ((CAM_Type *) HPM_CAM1_BASE) - -#include "hpm_pdma_regs.h" -/* Address of PDMA instances */ -/* PDMA base address */ -#define HPM_PDMA_BASE (0xF1010000UL) -/* PDMA base pointer */ -#define HPM_PDMA ((PDMA_Type *) HPM_PDMA_BASE) - -#include "hpm_jpeg_regs.h" -/* Address of JPEG instances */ -/* JPEG base address */ -#define HPM_JPEG_BASE (0xF1014000UL) -/* JPEG base pointer */ -#define HPM_JPEG ((JPEG_Type *) HPM_JPEG_BASE) - -#include "hpm_enet_regs.h" -/* Address of ENET instances */ -/* ENET0 base address */ -#define HPM_ENET0_BASE (0xF2000000UL) -/* ENET0 base pointer */ -#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) -/* ENET1 base address */ -#define HPM_ENET1_BASE (0xF2004000UL) -/* ENET1 base pointer */ -#define HPM_ENET1 ((ENET_Type *) HPM_ENET1_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* NTMR0 base address */ -#define HPM_NTMR0_BASE (0xF2010000UL) -/* NTMR0 base pointer */ -#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) -/* NTMR1 base address */ -#define HPM_NTMR1_BASE (0xF2014000UL) -/* NTMR1 base pointer */ -#define HPM_NTMR1 ((GPTMR_Type *) HPM_NTMR1_BASE) -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF3000000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF3004000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* GPTMR2 base address */ -#define HPM_GPTMR2_BASE (0xF3008000UL) -/* GPTMR2 base pointer */ -#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) -/* GPTMR3 base address */ -#define HPM_GPTMR3_BASE (0xF300C000UL) -/* GPTMR3 base pointer */ -#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) -/* GPTMR4 base address */ -#define HPM_GPTMR4_BASE (0xF3010000UL) -/* GPTMR4 base pointer */ -#define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE) -/* GPTMR5 base address */ -#define HPM_GPTMR5_BASE (0xF3014000UL) -/* GPTMR5 base pointer */ -#define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE) -/* GPTMR6 base address */ -#define HPM_GPTMR6_BASE (0xF3018000UL) -/* GPTMR6 base pointer */ -#define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE) -/* GPTMR7 base address */ -#define HPM_GPTMR7_BASE (0xF301C000UL) -/* GPTMR7 base pointer */ -#define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF40E0000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF2020000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) -/* USB1 base address */ -#define HPM_USB1_BASE (0xF2024000UL) -/* USB1 base pointer */ -#define HPM_USB1 ((USB_Type *) HPM_USB1_BASE) - -#include "hpm_sdxc_regs.h" -/* Address of SDXC instances */ -/* SDXC0 base address */ -#define HPM_SDXC0_BASE (0xF2030000UL) -/* SDXC0 base pointer */ -#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) -/* SDXC1 base address */ -#define HPM_SDXC1_BASE (0xF2034000UL) -/* SDXC1 base pointer */ -#define HPM_SDXC1 ((SDXC_Type *) HPM_SDXC1_BASE) - -#include "hpm_conctl_regs.h" -/* Address of CONCTL instances */ -/* CONCTL base address */ -#define HPM_CONCTL_BASE (0xF2040000UL) -/* CONCTL base pointer */ -#define HPM_CONCTL ((CONCTL_Type *) HPM_CONCTL_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF3020000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF3024000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF3028000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF302C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) - -#include "hpm_sdp_regs.h" -/* Address of SDP instances */ -/* SDP base address */ -#define HPM_SDP_BASE (0xF304C000UL) -/* SDP base pointer */ -#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) - -#include "hpm_femc_regs.h" -/* Address of FEMC instances */ -/* FEMC base address */ -#define HPM_FEMC_BASE (0xF3050000UL) -/* FEMC base pointer */ -#define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF40D8000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) -/* BIOC base address */ -#define HPM_BIOC_BASE (0xF5010000UL) -/* BIOC base pointer */ -#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTPSHW base address */ -#define HPM_OTPSHW_BASE (0xF4080000UL) -/* OTPSHW base pointer */ -#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE) -/* OTP base address */ -#define HPM_OTP_BASE (0xF40C8000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF40C0000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF40C4000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_psec_regs.h" -/* Address of PSEC instances */ -/* PSEC base address */ -#define HPM_PSEC_BASE (0xF40CC000UL) -/* PSEC base pointer */ -#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) - -#include "hpm_pmon_regs.h" -/* Address of PMON instances */ -/* PMON base address */ -#define HPM_PMON_BASE (0xF40D0000UL) -/* PMON base pointer */ -#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR base address */ -#define HPM_PGPR_BASE (0xF40D4000UL) -/* PGPR base pointer */ -#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE) - -#include "hpm_vad_regs.h" -/* Address of VAD instances */ -/* VAD base address */ -#define HPM_VAD_BASE (0xF40EC000UL) -/* VAD base pointer */ -#define HPM_VAD ((VAD_Type *) HPM_VAD_BASE) - -#include "hpm_pllctl_regs.h" -/* Address of PLLCTL instances */ -/* PLLCTL base address */ -#define HPM_PLLCTL_BASE (0xF4100000UL) -/* PLLCTL base pointer */ -#define HPM_PLLCTL ((PLLCTL_Type *) HPM_PLLCTL_BASE) - -#include "hpm_bpor_regs.h" -/* Address of BPOR instances */ -/* BPOR base address */ -#define HPM_BPOR_BASE (0xF5004000UL) -/* BPOR base pointer */ -#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) - -#include "hpm_bcfg_regs.h" -/* Address of BCFG instances */ -/* BCFG base address */ -#define HPM_BCFG_BASE (0xF5008000UL) -/* BCFG base pointer */ -#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) - -#include "hpm_butn_regs.h" -/* Address of BUTN instances */ -/* BUTN base address */ -#define HPM_BUTN_BASE (0xF500C000UL) -/* BUTN base pointer */ -#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) - -#include "hpm_bgpr_regs.h" -/* Address of BGPR instances */ -/* BGPR base address */ -#define HPM_BGPR_BASE (0xF5018000UL) -/* BGPR base pointer */ -#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) - -#include "hpm_rtc_regs.h" -/* Address of RTC instances */ -/* RTCSHW base address */ -#define HPM_RTCSHW_BASE (0xF501C000UL) -/* RTCSHW base pointer */ -#define HPM_RTCSHW ((RTC_Type *) HPM_RTCSHW_BASE) -/* RTC base address */ -#define HPM_RTC_BASE (0xF5044000UL) -/* RTC base pointer */ -#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) - -#include "hpm_bsec_regs.h" -/* Address of BSEC instances */ -/* BSEC base address */ -#define HPM_BSEC_BASE (0xF5040000UL) -/* BSEC base pointer */ -#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) - -#include "hpm_bkey_regs.h" -/* Address of BKEY instances */ -/* BKEY base address */ -#define HPM_BKEY_BASE (0xF5048000UL) -/* BKEY base pointer */ -#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) - -#include "hpm_bmon_regs.h" -/* Address of BMON instances */ -/* BMON base address */ -#define HPM_BMON_BASE (0xF504C000UL) -/* BMON base pointer */ -#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) - -#include "hpm_tamp_regs.h" -/* Address of TAMP instances */ -/* TAMP base address */ -#define HPM_TAMP_BASE (0xF5050000UL) -/* TAMP base pointer */ -#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) - -#include "hpm_mono_regs.h" -/* Address of MONO instances */ -/* MONO base address */ -#define HPM_MONO_BASE (0xF5054000UL) -/* MONO base pointer */ -#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_trgmmux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc_feature.h deleted file mode 100644 index fa07d998db0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc_feature.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (256U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * I2S Section - */ -#define I2S_SOC_MAX_CHANNEL_NUM (16U) -#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) -#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) -#define PDM_I2S HPM_I2S0 -#define DAO_I2S HPM_I2S1 -#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) -#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) -#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (5U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (24U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (8U) -#define DMA_SOC_MAX_COUNT (2U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) - -/* - * PDMA Section - */ -#define PDMA_SOC_PS_MAX_COUNT (2U) -#define PDMA_SOC_SUPPORT_BS16 (1U) -/* - * LCDC Section - */ -#define LCDC_SOC_MAX_LAYER_COUNT (8U) -#define LCDC_SOC_MAX_CSC_LAYER_COUNT (2U) -#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) -#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) - -/* - * USB Section - */ -#define USB_SOC_MAX_COUNT (2U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* - * ENET Section - */ -#define ENET_SOC_RGMII_EN (1U) -#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) -#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) -#define ENET_SOC_ADDR_MAX_COUNT (5U) -#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) -#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) -#define ENET_SOC_ALT_EHD_DES_LEN (8U) -#define ENET_SOC_PPS_MAX_COUNT (4L) -#define ENET_SOC_PPS1_EN (0U) - -/* - * ACMP Section - */ -#define ACMP_SOC_BANDGAP (1U) - -/* - * ADC Section - */ -#define ADC_SOC_IP_VERSION (0U) -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (0U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) -#define ADC_SOC_OTP_TSNS_REF25_MASK (0xffffUL) -#define ADC_SOC_OTP_TSNS_REF25_SHIFT (21U) -#define ADC_SOC_REF_TEMP (25U) -#define ADC_SOC_REF_SLOPE (1.0f/6) -#define ADC_SOC_TEMPSENS_REF25_VOL (3300U) -#define ADC_SOC_VOUT25C_MAX_SAMPLE_VALUE (65535U) - -#define ADC12_SOC_CLOCK_CLK_DIV (2U) -#define ADC12_SOC_CALIBRATION_WAITING_LOOP_CNT (10) -#define ADC12_SOC_MAX_CH_NUM (17U) -#define ADC12_SOC_MAX_SAMPLE_VALUE (4095U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (7U) -#define ADC16_SOC_TEMP_CH_NUM (14U) -#define ADC16_SOC_TEMP_CH_EN (1U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * CAN Section - */ -#define CAN_SOC_MAX_COUNT (4U) -#define CAN_SOC_CANFD_TDC_REQUIRE_STUFF_EXCEPTION_WORKAROUND (1) /* Refer to E00016 in HPM6700/6400 Errata */ - -/* - * UART Section - */ -#define UART_SOC_FIFO_SIZE (16U) - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (512U) -#define SPI_SOC_FIFO_DEPTH (4U) - -/* - * SDXC Section - */ -#define SDXC_SOC_MAX_COUNT (2) - - -/* - * ROM API section - */ -#define ROMAPI_HAS_SW_SM3 (1) -#define ROMAPI_HAS_SW_SM4 (1) - -/* - * OTP Section - */ -#define OTP_SOC_MAC0_IDX (65U) -#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ - -#define OTP_SOC_UUID_IDX (88U) -#define OTP_SOC_UUID_LEN (16U) /* in bytes */ - -/** - * PWM Section - * - */ -#define PWM_SOC_HRPWM_SUPPORT (0U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) -#define PWM_SOC_TIMER_RESET_SUPPORT (0U) - -/** - * IOC Section - * - */ -#define IOC_SOC_PAD_CTRL_SETTING_WORKAROUND (1U) /* Refer to E00029 in HPM6700/HPM6400 Errata */ - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc_ip_feature.h deleted file mode 100644 index d21c1e5be3e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_soc_ip_feature.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* ADC16 related feature */ -#define HPM_IP_FEATURE_ADC16_HAS_TEMPSNS 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sysctl_drv.c deleted file mode 100644 index 9e23887d5de..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sysctl_drv.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 -#define SYSCTL_RESOURCE_GROUP1 1 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) - -static inline bool sysctl_valid_cpu_index(uint8_t cpu) -{ - if ((cpu != SYSCTL_CPU_CPU0) && (cpu != SYSCTL_CPU_CPU1)) { - return false; - } - return true; -} - -hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, - uint32_t *data, uint32_t size) -{ - uint32_t i; - if ((!sysctl_valid_cpu_index(cpu)) - || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { - return status_invalid_argument; - } - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i]; - } - return status_success; -} - -static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, - uint8_t cpu, - uint8_t start, - uint8_t count, - uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) - || (data == NULL) - || !count || start > size || count > size - || (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[cpu].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); -} - -hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); -} - -static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, - uint8_t cpu, - uint8_t start, - uint8_t count, - uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) - || (data == NULL) - || !count || start > size || count > size - || (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[cpu].GPR[start + i] = *(data + i); - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data, - bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data, - bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 1, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu1_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, - uint8_t slice, monitor_config_t *config) -{ - ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL - & ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK - | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | SYSCTL_MONITOR_CONTROL_REFERENCE_MASK - | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) - | (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) - | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) - | SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) - | SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) - | SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) - | SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) - | SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = {0}; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].GPR[0] = entry; - ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); - return status_success; -} - -hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 1, entry); -} - -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 0, entry); -} - -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable) -{ - uint32_t index, offset; - if (resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) - | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - case SYSCTL_RESOURCE_GROUP1: - ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) - | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource) -{ - uint32_t index, offset; - bool enable; - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - case SYSCTL_RESOURCE_GROUP1: - enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - case SYSCTL_RESOURCE_GROUP1: - value = ptr->GROUP1[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); -} - -hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, - clock_node_t node, - clock_source_adc_i2s_t source) -{ - uint32_t index; - if ((node < clock_node_adc_i2s_start) - || (source >= clock_source_adc_i2s_clk_end)) { - return status_invalid_argument; - } - - switch (node) { - case clock_node_adc3: - case clock_node_adc2: - case clock_node_adc1: - case clock_node_adc0: - index = node - clock_node_adc0; - ptr->ADCCLK[index] - = (ptr->ADCCLK[index] & ~SYSCTL_ADCCLK_MUX_MASK) - | SYSCTL_ADCCLK_MUX_SET(source); - break; - case clock_node_i2s3: - case clock_node_i2s2: - case clock_node_i2s1: - case clock_node_i2s0: - index = node - clock_node_i2s0; - ptr->I2SCLK[index] - = (ptr->I2SCLK[index] & ~SYSCTL_I2SCLK_MUX_MASK) - | SYSCTL_I2SCLK_MUX_SET(source); - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) -{ - if (node >= clock_node_adc_i2s_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, - clock_source_t source, uint32_t divide_by) -{ - if (node >= clock_node_adc_i2s_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & - ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) - | (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sysctl_drv.h deleted file mode 100644 index 16525a11f38..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_sysctl_drv.h +++ /dev/null @@ -1,1709 +0,0 @@ -/** - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */ -typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - sysctl_retention_domain_cpu1 = 4, - sysctl_retention_domain_conn = 6, - sysctl_retention_domain_vis = 8, - sysctl_retention_domain_xtal24m = 10, - sysctl_retention_domain_pll0 = 11, - sysctl_retention_domain_pll1 = 12, - sysctl_retention_domain_pll2 = 13, - sysctl_retention_domain_pll3 = 14, - sysctl_retention_domain_pll4 = 15, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_con, - sysctl_reset_domain_vis, - sysctl_reset_domain_cpu0, - sysctl_reset_domain_cpu1, -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = 0, - sysctl_resource_cpx0 = 1, - sysctl_resource_exe0 = 2, - sysctl_resource_wak0 = 3, - sysctl_resource_cpu0_per = 4, - sysctl_resource_cpu1 = 8, - sysctl_resource_cpx1 = 9, - sysctl_resource_exe1 = 10, - sysctl_resource_wak1 = 11, - sysctl_resource_cpu1_per = 12, - sysctl_resource_logic0 = 16, - sysctl_resource_logic1 = 17, - sysctl_resource_logic2 = 18, - sysctl_resource_logic3 = 19, - sysctl_resource_pmic = 20, - sysctl_resource_pow_con = 21, - sysctl_resource_pow_vis = 22, - sysctl_resource_pow_cpu0 = 23, - sysctl_resource_pow_cpu1 = 24, - sysctl_resource_rst_soc = 25, - sysctl_resource_rst_con = 26, - sysctl_resource_rst_vis = 27, - sysctl_resource_rst_cpu0 = 28, - sysctl_resource_rst_cpu1 = 29, - sysctl_resource_xtal = 32, - sysctl_resource_pll0 = 33, - sysctl_resource_clk0_pll0 = 34, - sysctl_resource_pll1 = 35, - sysctl_resource_clk0_pll1 = 36, - sysctl_resource_clk1_pll1 = 37, - sysctl_resource_pll2 = 38, - sysctl_resource_clk0_pll2 = 39, - sysctl_resource_clk1_pll2 = 40, - sysctl_resource_pll3 = 41, - sysctl_resource_clk0_pll3 = 42, - sysctl_resource_pll4 = 43, - sysctl_resource_clk0_pll4 = 44, - sysctl_resource_mbist_soc = 48, - sysctl_resource_mbist_cpu = 49, - sysctl_resource_mbist_cpu1 = 50, - sysctl_resource_mbist_con = 51, - sysctl_resource_mbist_vis = 52, - sysctl_resource_clk_top_cpu0 = 64, - sysctl_resource_clk_top_mchtmr0 = 65, - sysctl_resource_clk_top_cpu1 = 66, - sysctl_resource_clk_top_mchtmr1 = 67, - sysctl_resource_clk_top_axi0 = 68, - sysctl_resource_clk_top_axi1 = 69, - sysctl_resource_clk_top_axi2 = 70, - sysctl_resource_clk_top_ahb0 = 71, - sysctl_resource_clk_top_femc = 72, - sysctl_resource_clk_top_xpi0 = 73, - sysctl_resource_clk_top_xpi1 = 74, - sysctl_resource_clk_top_gptmr0 = 75, - sysctl_resource_clk_top_gptmr1 = 76, - sysctl_resource_clk_top_gptmr2 = 77, - sysctl_resource_clk_top_gptmr3 = 78, - sysctl_resource_clk_top_gptmr4 = 79, - sysctl_resource_clk_top_gptmr5 = 80, - sysctl_resource_clk_top_gptmr6 = 81, - sysctl_resource_clk_top_gptmr7 = 82, - sysctl_resource_clk_top_uart0 = 83, - sysctl_resource_clk_top_uart1 = 84, - sysctl_resource_clk_top_uart2 = 85, - sysctl_resource_clk_top_uart3 = 86, - sysctl_resource_clk_top_uart4 = 87, - sysctl_resource_clk_top_uart5 = 88, - sysctl_resource_clk_top_uart6 = 89, - sysctl_resource_clk_top_uart7 = 90, - sysctl_resource_clk_top_uart8 = 91, - sysctl_resource_clk_top_uart9 = 92, - sysctl_resource_clk_top_uarta = 93, - sysctl_resource_clk_top_uartb = 94, - sysctl_resource_clk_top_uartc = 95, - sysctl_resource_clk_top_uartd = 96, - sysctl_resource_clk_top_uarte = 97, - sysctl_resource_clk_top_uartf = 98, - sysctl_resource_clk_top_i2c0 = 99, - sysctl_resource_clk_top_i2c1 = 100, - sysctl_resource_clk_top_i2c2 = 101, - sysctl_resource_clk_top_i2c3 = 102, - sysctl_resource_clk_top_spi0 = 103, - sysctl_resource_clk_top_spi1 = 104, - sysctl_resource_clk_top_spi2 = 105, - sysctl_resource_clk_top_spi3 = 106, - sysctl_resource_clk_top_can0 = 107, - sysctl_resource_clk_top_can1 = 108, - sysctl_resource_clk_top_can2 = 109, - sysctl_resource_clk_top_can3 = 110, - sysctl_resource_clk_top_ptpc = 111, - sysctl_resource_clk_top_ana0 = 112, - sysctl_resource_clk_top_ana1 = 113, - sysctl_resource_clk_top_ana2 = 114, - sysctl_resource_clk_top_aud0 = 115, - sysctl_resource_clk_top_aud1 = 116, - sysctl_resource_clk_top_aud2 = 117, - sysctl_resource_clk_top_dis0 = 118, - sysctl_resource_clk_top_cam0 = 119, - sysctl_resource_clk_top_cam1 = 120, - sysctl_resource_clk_top_eth0 = 121, - sysctl_resource_clk_top_eth1 = 122, - sysctl_resource_clk_top_ptp0 = 123, - sysctl_resource_clk_top_ptp1 = 124, - sysctl_resource_clk_top_ref0 = 125, - sysctl_resource_clk_top_ref1 = 126, - sysctl_resource_clk_top_ntmr0 = 127, - sysctl_resource_clk_top_ntmr1 = 128, - sysctl_resource_clk_top_sdxc0 = 129, - sysctl_resource_clk_top_sdxc1 = 130, - sysctl_resource_clk_top_adc0 = 192, - sysctl_resource_clk_top_adc1 = 193, - sysctl_resource_clk_top_adc2 = 194, - sysctl_resource_clk_top_adc3 = 195, - sysctl_resource_clk_top_i2s0 = 196, - sysctl_resource_clk_top_i2s1 = 197, - sysctl_resource_clk_top_i2s2 = 198, - sysctl_resource_clk_top_i2s3 = 199, - - sysctl_resource_linkable_start = 256, - sysctl_resource_ahbp = 256, - sysctl_resource_axis = 257, - sysctl_resource_axic = 258, - sysctl_resource_axiv = 259, - sysctl_resource_femc = 260, - sysctl_resource_rom0 = 261, - sysctl_resource_lmm0 = 262, - sysctl_resource_lmm1 = 263, - sysctl_resource_mchtmr0 = 264, - sysctl_resource_mchtmr1 = 265, - sysctl_resource_ram0 = 266, - sysctl_resource_ram1 = 267, - sysctl_resource_xpi0 = 268, - sysctl_resource_xpi1 = 269, - sysctl_resource_sdp0 = 270, - sysctl_resource_rng0 = 271, - sysctl_resource_kman = 272, - sysctl_resource_dma0 = 273, - sysctl_resource_dma1 = 274, - sysctl_resource_gpio = 275, - sysctl_resource_mbx0 = 276, - sysctl_resource_mbx1 = 277, - sysctl_resource_wdg0 = 278, - sysctl_resource_wdg1 = 279, - sysctl_resource_wdg2 = 280, - sysctl_resource_wdg3 = 281, - sysctl_resource_gptmr0 = 282, - sysctl_resource_gptmr1 = 283, - sysctl_resource_gptmr2 = 284, - sysctl_resource_gptmr3 = 285, - sysctl_resource_gptmr4 = 286, - sysctl_resource_gptmr5 = 287, - sysctl_resource_gptmr6 = 288, - sysctl_resource_gptmr7 = 289, - sysctl_resource_uart0 = 290, - sysctl_resource_uart1 = 291, - sysctl_resource_uart2 = 292, - sysctl_resource_uart3 = 293, - sysctl_resource_uart4 = 294, - sysctl_resource_uart5 = 295, - sysctl_resource_uart6 = 296, - sysctl_resource_uart7 = 297, - sysctl_resource_uart8 = 298, - sysctl_resource_uart9 = 299, - sysctl_resource_uarta = 300, - sysctl_resource_uartb = 301, - sysctl_resource_uartc = 302, - sysctl_resource_uartd = 303, - sysctl_resource_uarte = 304, - sysctl_resource_uartf = 305, - sysctl_resource_i2c0 = 306, - sysctl_resource_i2c1 = 307, - sysctl_resource_i2c2 = 308, - sysctl_resource_i2c3 = 309, - sysctl_resource_spi0 = 310, - sysctl_resource_spi1 = 311, - sysctl_resource_spi2 = 312, - sysctl_resource_spi3 = 313, - sysctl_resource_can0 = 314, - sysctl_resource_can1 = 315, - sysctl_resource_can2 = 316, - sysctl_resource_can3 = 317, - sysctl_resource_ptpc = 318, - sysctl_resource_adc0 = 319, - sysctl_resource_adc1 = 320, - sysctl_resource_adc2 = 321, - sysctl_resource_adc3 = 322, - sysctl_resource_acmp = 323, - sysctl_resource_i2s0 = 324, - sysctl_resource_i2s1 = 325, - sysctl_resource_i2s2 = 326, - sysctl_resource_i2s3 = 327, - sysctl_resource_i2spdm0 = 328, - sysctl_resource_i2sdao = 329, - sysctl_resource_synt = 330, - sysctl_resource_mot0 = 331, - sysctl_resource_mot1 = 332, - sysctl_resource_mot2 = 333, - sysctl_resource_mot3 = 334, - sysctl_resource_dis0 = 335, - sysctl_resource_cam0 = 336, - sysctl_resource_cam1 = 337, - sysctl_resource_jpeg = 338, - sysctl_resource_pdma = 339, - sysctl_resource_eth0 = 340, - sysctl_resource_eth1 = 341, - sysctl_resource_ntmr0 = 342, - sysctl_resource_ntmr1 = 343, - sysctl_resource_sdxc0 = 344, - sysctl_resource_sdxc1 = 345, - sysctl_resource_usb0 = 346, - sysctl_resource_usb1 = 347, - sysctl_resource_ref0 = 348, - sysctl_resource_ref1 = 349, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, - sysctl_resource_mode_force_on, - sysctl_resource_mode_force_off, -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_cpu0 = 0, - clock_node_mchtmr0 = 1, - clock_node_cpu1 = 2, - clock_node_mchtmr1 = 3, - clock_node_axi0 = 4, - clock_node_axi1 = 5, - clock_node_axi2 = 6, - clock_node_ahb0 = 7, - clock_node_femc = 8, - clock_node_xpi0 = 9, - clock_node_xpi1 = 10, - clock_node_gptmr0 = 11, - clock_node_gptmr1 = 12, - clock_node_gptmr2 = 13, - clock_node_gptmr3 = 14, - clock_node_gptmr4 = 15, - clock_node_gptmr5 = 16, - clock_node_gptmr6 = 17, - clock_node_gptmr7 = 18, - clock_node_uart0 = 19, - clock_node_uart1 = 20, - clock_node_uart2 = 21, - clock_node_uart3 = 22, - clock_node_uart4 = 23, - clock_node_uart5 = 24, - clock_node_uart6 = 25, - clock_node_uart7 = 26, - clock_node_uart8 = 27, - clock_node_uart9 = 28, - clock_node_uarta = 29, - clock_node_uartb = 30, - clock_node_uartc = 31, - clock_node_uartd = 32, - clock_node_uarte = 33, - clock_node_uartf = 34, - clock_node_i2c0 = 35, - clock_node_i2c1 = 36, - clock_node_i2c2 = 37, - clock_node_i2c3 = 38, - clock_node_spi0 = 39, - clock_node_spi1 = 40, - clock_node_spi2 = 41, - clock_node_spi3 = 42, - clock_node_can0 = 43, - clock_node_can1 = 44, - clock_node_can2 = 45, - clock_node_can3 = 46, - clock_node_ptpc = 47, - clock_node_ana0 = 48, - clock_node_ana1 = 49, - clock_node_ana2 = 50, - clock_node_aud0 = 51, - clock_node_aud1 = 52, - clock_node_aud2 = 53, - clock_node_dis0 = 54, - clock_node_cam0 = 55, - clock_node_cam1 = 56, - clock_node_eth0 = 57, - clock_node_eth1 = 58, - clock_node_ptp0 = 59, - clock_node_ptp1 = 60, - clock_node_ref0 = 61, - clock_node_ref1 = 62, - clock_node_ntmr0 = 63, - clock_node_ntmr1 = 64, - clock_node_sdxc0 = 65, - clock_node_sdxc1 = 66, - - clock_node_adc_i2s_start, - clock_node_adc0 = clock_node_adc_i2s_start, - clock_node_adc1, - clock_node_adc2, - clock_node_adc3, - - clock_node_i2s0, - clock_node_i2s1, - clock_node_i2s2, - clock_node_i2s3, - clock_node_end, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll1_clk0 = 2, - clock_source_pll1_clk1 = 3, - clock_source_pll2_clk0 = 4, - clock_source_pll2_clk1 = 5, - clock_source_pll3_clk0 = 6, - clock_source_pll4_clk0 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC/I2S clock sources - */ -typedef enum { - clock_source_adc_i2s_ahb_clk = 0, - clock_source_adc_ana0_clk = 1, - clock_source_i2s_aud0_clk = 1, - clock_source_adc_ana1_clk = 2, - clock_source_i2s_aud1_clk = 2, - clock_source_adc_ana2_clk = 3, - clock_source_i2s_aud2_clk = 3, - clock_source_adc_i2s_clk_end, -} clock_source_adc_i2s_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -typedef enum { - monitor_target_clk_32k = 0, - monitor_target_clk_irc24m = 1, - monitor_target_clk_xtal_24m = 2, - monitor_target_clk_usb0_phy = 3, - monitor_target_clk_usb1_phy = 4, - monitor_target_osc0_clk0 = 8, - monitor_target_pll0_clk0 = 9, - monitor_target_pll1_clk0 = 10, - monitor_target_pll1_clk1 = 11, - monitor_target_pll2_clk0 = 12, - monitor_target_pll2_clk1 = 13, - monitor_target_pll3_clk0 = 14, - monitor_target_pll4_clk0 = 15, - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_cpu1 = 130, - monitor_target_clk_top_mchtmr1 = 131, - monitor_target_clk_top_axi0 = 132, - monitor_target_clk_top_axi1 = 133, - monitor_target_clk_top_axi2 = 134, - monitor_target_clk_top_ahb0 = 135, - monitor_target_clk_top_femc = 136, - monitor_target_clk_top_xpi0 = 137, - monitor_target_clk_top_xpi1 = 138, - monitor_target_clk_top_gptmr0 = 139, - monitor_target_clk_top_gptmr1 = 140, - monitor_target_clk_top_gptmr2 = 141, - monitor_target_clk_top_gptmr3 = 142, - monitor_target_clk_top_gptmr4 = 143, - monitor_target_clk_top_gptmr5 = 144, - monitor_target_clk_top_gptmr6 = 145, - monitor_target_clk_top_gptmr7 = 146, - monitor_target_clk_top_uart0 = 147, - monitor_target_clk_top_uart1 = 148, - monitor_target_clk_top_uart2 = 149, - monitor_target_clk_top_uart3 = 150, - monitor_target_clk_top_uart4 = 151, - monitor_target_clk_top_uart5 = 152, - monitor_target_clk_top_uart6 = 153, - monitor_target_clk_top_uart7 = 154, - monitor_target_clk_top_uart8 = 155, - monitor_target_clk_top_uart9 = 156, - monitor_target_clk_top_uarta = 157, - monitor_target_clk_top_uartb = 158, - monitor_target_clk_top_uartc = 159, - monitor_target_clk_top_uartd = 160, - monitor_target_clk_top_uarte = 161, - monitor_target_clk_top_uartf = 162, - monitor_target_clk_top_i2c0 = 163, - monitor_target_clk_top_i2c1 = 164, - monitor_target_clk_top_i2c2 = 165, - monitor_target_clk_top_i2c3 = 166, - monitor_target_clk_top_spi0 = 167, - monitor_target_clk_top_spi1 = 168, - monitor_target_clk_top_spi2 = 169, - monitor_target_clk_top_spi3 = 170, - monitor_target_clk_top_can0 = 171, - monitor_target_clk_top_can1 = 172, - monitor_target_clk_top_can2 = 173, - monitor_target_clk_top_can3 = 174, - monitor_target_clk_top_ptpc = 175, - monitor_target_clk_top_ana0 = 176, - monitor_target_clk_top_ana1 = 177, - monitor_target_clk_top_ana2 = 178, - monitor_target_clk_top_aud0 = 179, - monitor_target_clk_top_aud1 = 180, - monitor_target_clk_top_aud2 = 181, - monitor_target_clk_top_dis0 = 182, - monitor_target_clk_top_cam0 = 183, - monitor_target_clk_top_cam1 = 184, - monitor_target_clk_top_eth0 = 185, - monitor_target_clk_top_eth1 = 186, - monitor_target_clk_top_ptp0 = 187, - monitor_target_clk_top_ptp1 = 188, - monitor_target_clk_top_ref0 = 189, - monitor_target_clk_top_ref1 = 190, - monitor_target_clk_top_ntmr0 = 191, - monitor_target_clk_top_ntmr1 = 192, - monitor_target_clk_top_sdxc0 = 193, - monitor_target_clk_top_sdxc1 = 194, -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, - uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = - (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) - | (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit_high, - uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = - (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | - SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Disable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Disable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, - uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 1, value); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, - uint8_t cpu_index, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - uint8_t set_mask = 0x1; - if (domain < sysctl_retention_domain_xtal24m) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Retain target domain for specific CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem); -} - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, - clock_node_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, - sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_PRESET_MASK) - | SYSCTL_GLOBAL00_PRESET_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, - sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, - sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, - sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, - sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, - sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Get target CPU0 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, - uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 0, status_index); -} - -/** - * @brief Get target CPU1 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, - uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 1, status_index); -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline - uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index, - uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Check CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline - uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); -} - -/** - * @brief Check CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline - uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask); -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline - void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline - void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); -} - - -/** - * @brief Disable CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask); -} - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Disable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); -} - - -/** - * @brief Disable CPU1 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num); -} - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Enable CPU1 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num); -} - -/** - * @brief Lock CPU gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint16_t gpr_mask) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, - uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); -} - -/** - * @brief Lock CPU1 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, - uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask); -} - -/** - * @brief Lock CPU lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 0); -} - -/** - * @brief Lock CPU1 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 1); -} - -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) -{ - ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); -} - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 0, mode); -} - -/** - * @brief Set CPU1 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 1, mode); -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Clear CPU1 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 1, flags); -} - -/** - * @brief Get CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ptr->CPU[cpu_index].LP & (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); -} - -/** - * @brief Get CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 0); -} - -/** - * @brief Get CPU1 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 1); -} - -/** - * @brief Release cpu - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; -} - -/** - * @brief Release cpu1 - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) -{ - sysctl_release_cpu(ptr, 1); -} - -/** - * @brief Check whether CPU is released or not - * - * @param [in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval true CPU is released - * @retval false CPU is on-hold - */ -static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); -} - -/** - * @brief Check whether CPU1 is released or not - * - * @param [in] ptr SYSCTL_Type base address - * @retval true CPU1 is released - * @retval false CPU1 is on-hold - */ -static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) -{ - return sysctl_is_cpu_released(ptr, 1); -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, - clock_node_t node, - clock_source_t source, - uint32_t divide_by); - -/** - * @brief Set ADC/I2S clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_i2s_clock_mux(SYSCTL_Type *ptr, - clock_node_t node, - clock_source_adc_i2s_t source); - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Add resource to CPU1 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be added to CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU1 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_config_t *config); - -/** - * @brief Save data to CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data, - bool lock); - -/** - * @brief Get data saved from CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data); - -/** - * @brief Set data to CPU1 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data, - bool lock); - -/** - * @brief Get data saved in CPU1 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, - uint8_t start, - uint8_t count, - uint32_t *data); - -/** - * @brief Set entry point on CPU boot or wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu CPU index - * @param[in] entry Entry address for CPU - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - -/** - * @brief Set entry point on either CPU1 boot or wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_trgmmux_src.h deleted file mode 100644 index a1e7d691c3a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/hpm_trgmmux_src.h +++ /dev/null @@ -1,726 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGMMUX_SRC_H -#define HPM_TRGMMUX_SRC_H - -/* trgm0_input mux definitions */ -#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) -#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) -#define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) -#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) -#define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) -#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) -#define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) -#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) -#define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) -#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) -#define HPM_TRGM0_INPUT_SRC_USB1_SOF (0x27UL) -#define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) -#define HPM_TRGM0_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) -#define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) -#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x37UL) -#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) - -/* trgm1_input mux definitions */ -#define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) -#define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) -#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) -#define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) -#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) -#define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) -#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) -#define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) -#define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) -#define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) -#define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) -#define HPM_TRGM1_INPUT_SRC_USB1_SOF (0x27UL) -#define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) -#define HPM_TRGM1_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) -#define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) -#define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x2CUL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x2DUL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x2EUL) -#define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x2FUL) -#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) -#define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) -#define HPM_TRGM1_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM1_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM1_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM1_INPUT_SRC_CMP3_OUT (0x37UL) -#define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) - -/* trgm2_input mux definitions */ -#define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) -#define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) -#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) -#define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) -#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) -#define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) -#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH16REF (0x1CUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH17REF (0x1DUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH18REF (0x1EUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH19REF (0x1FUL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH20REF (0x20UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH21REF (0x21UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH22REF (0x22UL) -#define HPM_TRGM2_INPUT_SRC_PWM2_CH23REF (0x23UL) -#define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x24UL) -#define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x25UL) -#define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x26UL) -#define HPM_TRGM2_INPUT_SRC_USB1_SOF (0x27UL) -#define HPM_TRGM2_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) -#define HPM_TRGM2_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) -#define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x2AUL) -#define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x2BUL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x2CUL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x2DUL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x2EUL) -#define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x2FUL) -#define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT2 (0x30UL) -#define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT3 (0x31UL) -#define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2 (0x32UL) -#define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3 (0x33UL) -#define HPM_TRGM2_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM2_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM2_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM2_INPUT_SRC_CMP3_OUT (0x37UL) -#define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x38UL) - -/* trgm3_input mux definitions */ -#define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) -#define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) -#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) -#define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) -#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) -#define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) -#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) -#define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH16REF (0x1CUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH17REF (0x1DUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH18REF (0x1EUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH19REF (0x1FUL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH20REF (0x20UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH21REF (0x21UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH22REF (0x22UL) -#define HPM_TRGM3_INPUT_SRC_PWM3_CH23REF (0x23UL) -#define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x24UL) -#define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x25UL) -#define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x26UL) -#define HPM_TRGM3_INPUT_SRC_USB1_SOF (0x27UL) -#define HPM_TRGM3_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) -#define HPM_TRGM3_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) -#define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x2AUL) -#define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x2BUL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x2CUL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x2DUL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x2EUL) -#define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x2FUL) -#define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT2 (0x30UL) -#define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT3 (0x31UL) -#define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT2 (0x32UL) -#define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT3 (0x33UL) -#define HPM_TRGM3_INPUT_SRC_CMP0_OUT (0x34UL) -#define HPM_TRGM3_INPUT_SRC_CMP1_OUT (0x35UL) -#define HPM_TRGM3_INPUT_SRC_CMP2_OUT (0x36UL) -#define HPM_TRGM3_INPUT_SRC_CMP3_OUT (0x37UL) -#define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x38UL) - -/* trgm0_output mux definitions */ -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) -#define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) -#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI (0x33UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) -#define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) -#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) - -/* trgm1_output mux definitions */ -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) -#define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) -#define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) -#define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) -#define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) -#define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM1_OUTPUT_SRC_ADC3_STRGI (0x33UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) -#define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) -#define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) -#define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) -#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) - -/* trgm2_output mux definitions */ -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) -#define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN16 (0x1EUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN17 (0x1FUL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN18 (0x20UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN19 (0x21UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN20 (0x22UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN21 (0x23UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN22 (0x24UL) -#define HPM_TRGM2_OUTPUT_SRC_PWM2_IN23 (0x25UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) -#define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) -#define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) -#define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM2_OUTPUT_SRC_ADC3_STRGI (0x33UL) -#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) -#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) -#define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI (0x37UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 (0x38UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN3 (0x39UL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR5_SYNCI (0x3AUL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN2 (0x3BUL) -#define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN3 (0x3CUL) -#define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) -#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) - -/* trgm3_output mux definitions */ -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) -#define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN16 (0x1EUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN17 (0x1FUL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN18 (0x20UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN19 (0x21UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN20 (0x22UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN21 (0x23UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN22 (0x24UL) -#define HPM_TRGM3_OUTPUT_SRC_PWM3_IN23 (0x25UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) -#define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) -#define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) -#define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM3_OUTPUT_SRC_ADC3_STRGI (0x33UL) -#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) -#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) -#define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR6_SYNCI (0x37UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN2 (0x38UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN3 (0x39UL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR7_SYNCI (0x3AUL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN2 (0x3BUL) -#define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN3 (0x3CUL) -#define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) -#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) -#define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) - -/* trgm0_filter mux definitions */ -#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) -#define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) - -/* trgm1_filter mux definitions */ -#define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) -#define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) -#define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) - -/* trgm2_filter mux definitions */ -#define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) -#define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) -#define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) - -/* trgm3_filter mux definitions */ -#define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) -#define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) -#define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) - -/* trgm0_dma mux definitions */ -#define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) -#define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) -#define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) -#define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) -#define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) -#define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) -#define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) - -/* trgm1_dma mux definitions */ -#define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) -#define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) -#define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) -#define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) -#define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) -#define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) -#define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) - -/* trgm2_dma mux definitions */ -#define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) -#define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) -#define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) -#define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) -#define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) -#define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) -#define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) - -/* trgm3_dma mux definitions */ -#define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) -#define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) -#define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) -#define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) -#define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) -#define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) -#define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) - - - -#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/soc_modules.list deleted file mode 100644 index a5255e66227..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/soc_modules.list +++ /dev/null @@ -1,67 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_MULTICORE=y -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_ADC12=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_ACMP=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_CAN=y -HPMSOC_HAS_HPMSDK_WDG=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_PTPC=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMA=y -HPMSOC_HAS_HPMSDK_RNG=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_I2S=y -HPMSOC_HAS_HPMSDK_DAO=y -HPMSOC_HAS_HPMSDK_PDM=y -HPMSOC_HAS_HPMSDK_PWM=y -HPMSOC_HAS_HPMSDK_HALL=y -HPMSOC_HAS_HPMSDK_QEI=y -HPMSOC_HAS_HPMSDK_TRGM=y -HPMSOC_HAS_HPMSDK_SYNT=y -HPMSOC_HAS_HPMSDK_LCDC=y -HPMSOC_HAS_HPMSDK_CAM=y -HPMSOC_HAS_HPMSDK_PDMA=y -HPMSOC_HAS_HPMSDK_JPEG=y -HPMSOC_HAS_HPMSDK_ENET=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_SDXC=y -HPMSOC_HAS_HPMSDK_CONCTL=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_SDP=y -HPMSOC_HAS_HPMSDK_FEMC=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PSEC=y -HPMSOC_HAS_HPMSDK_PMON=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_VAD=y -HPMSOC_HAS_HPMSDK_PLLCTL=y -HPMSOC_HAS_HPMSDK_BPOR=y -HPMSOC_HAS_HPMSDK_BCFG=y -HPMSOC_HAS_HPMSDK_BUTN=y -HPMSOC_HAS_HPMSDK_BGPR=y -HPMSOC_HAS_HPMSDK_RTC=y -HPMSOC_HAS_HPMSDK_BSEC=y -HPMSOC_HAS_HPMSDK_BKEY=y -HPMSOC_HAS_HPMSDK_BMON=y -HPMSOC_HAS_HPMSDK_TAMP=y -HPMSOC_HAS_HPMSDK_MONO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/system.c deleted file mode 100644 index 9034847eebe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/system.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ - disable_global_irq(CSR_MSTATUS_MIE_MASK); - disable_irq_from_intc(); - enable_plic_feature(); - enable_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash.ld deleted file mode 100644 index c4f93d17b5c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash.ld +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_sdram_uf2.ld deleted file mode 100644 index fa44b61fd21..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_sdram_uf2.ld +++ /dev/null @@ -1,293 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 768K /* AXI SRAM */ - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_sdram_xip.ld deleted file mode 100644 index 7b83b915545..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_sdram_xip.ld +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 768K /* AXI SRAM */ - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - NONCACHEABLE_RAM (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(EXCLUDE_FILE (nx*.o*) .text) - *(EXCLUDE_FILE (nx*.o*) .text*) - *(EXCLUDE_FILE (nx*.o*) .rodata) - *(EXCLUDE_FILE (nx*.o*) .rodata*) - *(EXCLUDE_FILE (nx*.o*) .srodata) - *(EXCLUDE_FILE (nx*.o*) .srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - nx*.o*(.text) - nx*.o*(.text*) - nx*.o*(.rodata) - nx*.o*(.rodata*) - nx*.o*(.srodata) - nx*.o*(.srodata*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index daebc94f069..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_xip.ld deleted file mode 100644 index b11cc01f62e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/flash_xip.ld +++ /dev/null @@ -1,316 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(EXCLUDE_FILE (nx*.o*) .text) - *(EXCLUDE_FILE (nx*.o*) .text*) - *(EXCLUDE_FILE (nx*.o*) .rodata) - *(EXCLUDE_FILE (nx*.o*) .rodata*) - *(EXCLUDE_FILE (nx*.o*) .srodata) - *(EXCLUDE_FILE (nx*.o*) .srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - nx*.o*(.text) - nx*.o*(.text*) - nx*.o*(.rodata) - nx*.o*(.rodata*) - nx*.o*(.srodata) - nx*.o*(.srodata*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/ram.ld deleted file mode 100644 index 129383b3690..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/ram.ld +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01080000, LENGTH = 512K /* AXI SRAM0 */ - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01100000, LENGTH = 256K /* AXI SRAM1 */ - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0300000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF40F0000, LENGTH = 8k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/ram_core1.ld deleted file mode 100644 index c44fa50cb12..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/ram_core1.ld +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - NONCACHEABLE_RAM (wx) : ORIGIN = 0x01140000, LENGTH = 64K /* AXI SRAM1 */ - AXI_SRAM (wx) : ORIGIN = 0x01150000, LENGTH = 176K - SHARE_RAM (w) : ORIGIN = 0x0117C000, LENGTH = 16K -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > NONCACHEABLE_RAM - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(NONCACHEABLE_RAM); - __noncacheable_end__ = ORIGIN(NONCACHEABLE_RAM) + LENGTH(NONCACHEABLE_RAM); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/start.S deleted file mode 100644 index 826006cab29..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/gcc/start.S +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - la tp, __thread_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - - /* Enable LMM1 clock */ - la t0, 0xF4000800 - lw t1, 0(t0) - ori t1, t1, 0x80 - sw t1, 0(t0) - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_sdram_uf2.icf deleted file mode 100644 index 873461d90db..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_sdram_uf2.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 16M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 768k]; /* AXI SRAM */ -define region SHARE_RAM = mem:[from 0x0117C000 size 16k]; -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 4M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 4M size 4M]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; -define region APB_SRAM = mem:[from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_sdram_xip.icf deleted file mode 100644 index b4c3f02113a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_sdram_xip.icf +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 16M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x2000 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 768k]; /* AXI SRAM */ -define region SHARE_RAM = mem:[from 0x0117C000 size 16k]; -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 4M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 4M size 4M]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; -define region APB_SRAM = mem:[from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_uf2.icf deleted file mode 100644 index 8ec2f7f3755..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = mem:[from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = mem:[from 0x0117C000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; -define region APB_SRAM = mem:[from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_xip.icf deleted file mode 100644 index 8a0fe15382b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = mem:[from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = mem:[from 0x0117C000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; -define region APB_SRAM = mem:[from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA, - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/ram.icf deleted file mode 100644 index a27a4186bb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/ram.icf +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = mem:[from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = mem:[from 0x0117C000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0300000 size 32k]; -define region APB_SRAM = mem:[from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/ram_core1.icf deleted file mode 100644 index 442dc0991cd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/ram_core1.icf +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01140000 size 64k]; /* AXI SRAM1 */ -define region AXI_SRAM = mem:[from 0x01150000 size 176k]; -define region SHARE_RAM = mem:[from 0x0117C000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/startup.s deleted file mode 100644 index 81175908610..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/iar/startup.s +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - EXTERN _init_ext_ram -__iar_cstart_init_ext_ram: - la t0, SFE(SAFESTACK) - mv sp, t0 - call _init_ext_ram -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/reset.c deleted file mode 100644 index e3d725a1d7a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash.icf deleted file mode 100644 index 39024e6a191..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash.icf +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start}; - -place at start of ILM with fixed order { block vectors }; - -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_sdram_uf2.icf deleted file mode 100644 index 16a942da6fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_sdram_uf2.icf +++ /dev/null @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 768k]; /* AXI SRAM */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; - - -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; - -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_sdram_xip.icf deleted file mode 100644 index 90272756951..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_sdram_xip.icf +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size (_flash_size - 0x3000) ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 768k]; /* AXI SRAM */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, section .text.*nx*, // "ramfunc" section - }; - -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; - -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 36787199c25..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; - -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_xip.icf deleted file mode 100644 index d78a3315722..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size (_flash_size - 0x3000) ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.*, section .text.*nx* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start}; -place at start of ILM with fixed order { block vectors }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.*, section .text.*nx*, // "ramfunc" section - }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; - -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/ram.icf deleted file mode 100644 index c55d6ff2349..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/ram.icf +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01080000 size 512k]; /* AXI SRAM0 */ -define region NONCACHEABLE_RAM = [from 0x01100000 size 256k]; /* AXI SRAM1 */ -define region SHARE_RAM = [from 0x0117C000 size 16k]; -define region AHB_SRAM = [from 0xF0300000 size 32k]; -define region APB_SRAM = [from 0xF40F0000 size 8k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/ram_core1.icf deleted file mode 100644 index e3b64cda573..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/ram_core1.icf +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01140000 size 64k]; /* AXI SRAM1 */ -define region AXI_SRAM = [from 0x01150000 size 176k]; -define region SHARE_RAM = [from 0x0117C000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/startup.s deleted file mode 100644 index b56b195064e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/segger/startup.s +++ /dev/null @@ -1,416 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - - /* Enable LMM1 clock */ - la t0, 0xF4000800 - lw t1, 0(t0) - ori t1, t1, 0x80 - sw t1, 0(t0) - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/trap.c deleted file mode 100644 index f812f2c2730..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/trap.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) //!< Instruction Address misaligned -#define MCAUSE_INSTR_ACCESS_FAULT (1U) //!< Instruction access fault -#define MCAUSE_ILLEGAL_INSTR (2U) //!< Illegal instruction -#define MCAUSE_BREAKPOINT (3U) //!< Breakpoint -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) //!< Load address misaligned -#define MCAUSE_LOAD_ACCESS_FAULT (5U) //!< Load access fault -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) //!< Store/AMO address misaligned -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) //!< Store/AMO access fault -#define MCAUSE_ECALL_FROM_USER_MODE (8U) //!< Environment call from User mode -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) //!< Environment call from Supervisor mode -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) //!< Environment call from machine mode -#define MCAUSE_INSTR_PAGE_FAULT (12U) //!< Instruction page fault -#define MCAUSE_LOAD_PAGE_FAULT (13) //!< Load page fault -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) //!< Store/AMO page fault - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - - - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/vectors.h deleted file mode 100644 index 36793f483c9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/HPM6750/toolchains/vectors.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(9) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 10 /* GPIO1_A IRQ handler */ - IRQ_DEFAULT_HANDLER 11 /* GPIO1_B IRQ handler */ - IRQ_DEFAULT_HANDLER 12 /* GPIO1_C IRQ handler */ - IRQ_DEFAULT_HANDLER 13 /* GPIO1_D IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* GPIO1_E IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* GPIO1_F IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* GPIO1_X IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* GPIO1_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 18 /* GPIO1_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 19 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 20 /* ADC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 21 /* ADC2 IRQ handler */ - IRQ_DEFAULT_HANDLER 22 /* ADC3 IRQ handler */ - IRQ_DEFAULT_HANDLER 23 /* ACMP[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 24 /* ACMP[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 25 /* ACMP[2] IRQ handler */ - IRQ_DEFAULT_HANDLER 26 /* ACMP[3] IRQ handler */ - IRQ_DEFAULT_HANDLER 27 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* UART4 IRQ handler */ - IRQ_DEFAULT_HANDLER 36 /* UART5 IRQ handler */ - IRQ_DEFAULT_HANDLER 37 /* UART6 IRQ handler */ - IRQ_DEFAULT_HANDLER 38 /* UART7 IRQ handler */ - IRQ_DEFAULT_HANDLER 39 /* UART8 IRQ handler */ - IRQ_DEFAULT_HANDLER 40 /* UART9 IRQ handler */ - IRQ_DEFAULT_HANDLER 41 /* UART10 IRQ handler */ - IRQ_DEFAULT_HANDLER 42 /* UART11 IRQ handler */ - IRQ_DEFAULT_HANDLER 43 /* UART12 IRQ handler */ - IRQ_DEFAULT_HANDLER 44 /* UART13 IRQ handler */ - IRQ_DEFAULT_HANDLER 45 /* UART14 IRQ handler */ - IRQ_DEFAULT_HANDLER 46 /* UART15 IRQ handler */ - IRQ_DEFAULT_HANDLER 47 /* CAN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 48 /* CAN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 49 /* CAN2 IRQ handler */ - IRQ_DEFAULT_HANDLER 50 /* CAN3 IRQ handler */ - IRQ_DEFAULT_HANDLER 51 /* PTPC IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* WDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* WDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 54 /* WDG2 IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* WDG3 IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 57 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* MBX1A IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* MBX1B IRQ handler */ - IRQ_DEFAULT_HANDLER 60 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 61 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 62 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* GPTMR4 IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* GPTMR5 IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* GPTMR6 IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* GPTMR7 IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* PWM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 73 /* HALL0 IRQ handler */ - IRQ_DEFAULT_HANDLER 74 /* QEI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 75 /* PWM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 76 /* HALL1 IRQ handler */ - IRQ_DEFAULT_HANDLER 77 /* QEI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 78 /* PWM2 IRQ handler */ - IRQ_DEFAULT_HANDLER 79 /* HALL2 IRQ handler */ - IRQ_DEFAULT_HANDLER 80 /* QEI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 81 /* PWM3 IRQ handler */ - IRQ_DEFAULT_HANDLER 82 /* HALL3 IRQ handler */ - IRQ_DEFAULT_HANDLER 83 /* QEI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 84 /* SDP IRQ handler */ - IRQ_DEFAULT_HANDLER 85 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 86 /* XPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 87 /* XDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 88 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 89 /* FEMC IRQ handler */ - IRQ_DEFAULT_HANDLER 90 /* RNG IRQ handler */ - IRQ_DEFAULT_HANDLER 91 /* I2S0 IRQ handler */ - IRQ_DEFAULT_HANDLER 92 /* I2S1 IRQ handler */ - IRQ_DEFAULT_HANDLER 93 /* I2S2 IRQ handler */ - IRQ_DEFAULT_HANDLER 94 /* I2S3 IRQ handler */ - IRQ_DEFAULT_HANDLER 95 /* DAO IRQ handler */ - IRQ_DEFAULT_HANDLER 96 /* PDM IRQ handler */ - IRQ_DEFAULT_HANDLER 97 /* CAM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 98 /* CAM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 99 /* LCDC_D0 IRQ handler */ - IRQ_DEFAULT_HANDLER 100 /* LCDC_D1 IRQ handler */ - IRQ_DEFAULT_HANDLER 101 /* PDMA_D0 IRQ handler */ - IRQ_DEFAULT_HANDLER 102 /* PDMA_D1 IRQ handler */ - IRQ_DEFAULT_HANDLER 103 /* JPEG IRQ handler */ - IRQ_DEFAULT_HANDLER 104 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 105 /* NTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 106 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 107 /* USB1 IRQ handler */ - IRQ_DEFAULT_HANDLER 108 /* ENET0 IRQ handler */ - IRQ_DEFAULT_HANDLER 109 /* ENET1 IRQ handler */ - IRQ_DEFAULT_HANDLER 110 /* SDXC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 111 /* SDXC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 112 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 113 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 114 /* PWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 115 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 116 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 117 /* VAD IRQ handler */ - IRQ_DEFAULT_HANDLER 118 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 119 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 120 /* RTC IRQ handler */ - IRQ_DEFAULT_HANDLER 121 /* BUTN IRQ handler */ - IRQ_DEFAULT_HANDLER 122 /* BGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 123 /* BVIO IRQ handler */ - IRQ_DEFAULT_HANDLER 124 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 125 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 126 /* DEBUG[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 127 /* DEBUG[1] IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(9) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ - IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ - IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ - IRQ_HANDLER 19 /* ADC0 IRQ handler */ - IRQ_HANDLER 20 /* ADC1 IRQ handler */ - IRQ_HANDLER 21 /* ADC2 IRQ handler */ - IRQ_HANDLER 22 /* ADC3 IRQ handler */ - IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ - IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ - IRQ_HANDLER 27 /* SPI0 IRQ handler */ - IRQ_HANDLER 28 /* SPI1 IRQ handler */ - IRQ_HANDLER 29 /* SPI2 IRQ handler */ - IRQ_HANDLER 30 /* SPI3 IRQ handler */ - IRQ_HANDLER 31 /* UART0 IRQ handler */ - IRQ_HANDLER 32 /* UART1 IRQ handler */ - IRQ_HANDLER 33 /* UART2 IRQ handler */ - IRQ_HANDLER 34 /* UART3 IRQ handler */ - IRQ_HANDLER 35 /* UART4 IRQ handler */ - IRQ_HANDLER 36 /* UART5 IRQ handler */ - IRQ_HANDLER 37 /* UART6 IRQ handler */ - IRQ_HANDLER 38 /* UART7 IRQ handler */ - IRQ_HANDLER 39 /* UART8 IRQ handler */ - IRQ_HANDLER 40 /* UART9 IRQ handler */ - IRQ_HANDLER 41 /* UART10 IRQ handler */ - IRQ_HANDLER 42 /* UART11 IRQ handler */ - IRQ_HANDLER 43 /* UART12 IRQ handler */ - IRQ_HANDLER 44 /* UART13 IRQ handler */ - IRQ_HANDLER 45 /* UART14 IRQ handler */ - IRQ_HANDLER 46 /* UART15 IRQ handler */ - IRQ_HANDLER 47 /* CAN0 IRQ handler */ - IRQ_HANDLER 48 /* CAN1 IRQ handler */ - IRQ_HANDLER 49 /* CAN2 IRQ handler */ - IRQ_HANDLER 50 /* CAN3 IRQ handler */ - IRQ_HANDLER 51 /* PTPC IRQ handler */ - IRQ_HANDLER 52 /* WDG0 IRQ handler */ - IRQ_HANDLER 53 /* WDG1 IRQ handler */ - IRQ_HANDLER 54 /* WDG2 IRQ handler */ - IRQ_HANDLER 55 /* WDG3 IRQ handler */ - IRQ_HANDLER 56 /* MBX0A IRQ handler */ - IRQ_HANDLER 57 /* MBX0B IRQ handler */ - IRQ_HANDLER 58 /* MBX1A IRQ handler */ - IRQ_HANDLER 59 /* MBX1B IRQ handler */ - IRQ_HANDLER 60 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 61 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 62 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 63 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 64 /* GPTMR4 IRQ handler */ - IRQ_HANDLER 65 /* GPTMR5 IRQ handler */ - IRQ_HANDLER 66 /* GPTMR6 IRQ handler */ - IRQ_HANDLER 67 /* GPTMR7 IRQ handler */ - IRQ_HANDLER 68 /* I2C0 IRQ handler */ - IRQ_HANDLER 69 /* I2C1 IRQ handler */ - IRQ_HANDLER 70 /* I2C2 IRQ handler */ - IRQ_HANDLER 71 /* I2C3 IRQ handler */ - IRQ_HANDLER 72 /* PWM0 IRQ handler */ - IRQ_HANDLER 73 /* HALL0 IRQ handler */ - IRQ_HANDLER 74 /* QEI0 IRQ handler */ - IRQ_HANDLER 75 /* PWM1 IRQ handler */ - IRQ_HANDLER 76 /* HALL1 IRQ handler */ - IRQ_HANDLER 77 /* QEI1 IRQ handler */ - IRQ_HANDLER 78 /* PWM2 IRQ handler */ - IRQ_HANDLER 79 /* HALL2 IRQ handler */ - IRQ_HANDLER 80 /* QEI2 IRQ handler */ - IRQ_HANDLER 81 /* PWM3 IRQ handler */ - IRQ_HANDLER 82 /* HALL3 IRQ handler */ - IRQ_HANDLER 83 /* QEI3 IRQ handler */ - IRQ_HANDLER 84 /* SDP IRQ handler */ - IRQ_HANDLER 85 /* XPI0 IRQ handler */ - IRQ_HANDLER 86 /* XPI1 IRQ handler */ - IRQ_HANDLER 87 /* XDMA IRQ handler */ - IRQ_HANDLER 88 /* HDMA IRQ handler */ - IRQ_HANDLER 89 /* FEMC IRQ handler */ - IRQ_HANDLER 90 /* RNG IRQ handler */ - IRQ_HANDLER 91 /* I2S0 IRQ handler */ - IRQ_HANDLER 92 /* I2S1 IRQ handler */ - IRQ_HANDLER 93 /* I2S2 IRQ handler */ - IRQ_HANDLER 94 /* I2S3 IRQ handler */ - IRQ_HANDLER 95 /* DAO IRQ handler */ - IRQ_HANDLER 96 /* PDM IRQ handler */ - IRQ_HANDLER 97 /* CAM0 IRQ handler */ - IRQ_HANDLER 98 /* CAM1 IRQ handler */ - IRQ_HANDLER 99 /* LCDC_D0 IRQ handler */ - IRQ_HANDLER 100 /* LCDC_D1 IRQ handler */ - IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ - IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ - IRQ_HANDLER 103 /* JPEG IRQ handler */ - IRQ_HANDLER 104 /* NTMR0 IRQ handler */ - IRQ_HANDLER 105 /* NTMR1 IRQ handler */ - IRQ_HANDLER 106 /* USB0 IRQ handler */ - IRQ_HANDLER 107 /* USB1 IRQ handler */ - IRQ_HANDLER 108 /* ENET0 IRQ handler */ - IRQ_HANDLER 109 /* ENET1 IRQ handler */ - IRQ_HANDLER 110 /* SDXC0 IRQ handler */ - IRQ_HANDLER 111 /* SDXC1 IRQ handler */ - IRQ_HANDLER 112 /* PSEC IRQ handler */ - IRQ_HANDLER 113 /* PGPIO IRQ handler */ - IRQ_HANDLER 114 /* PWDG IRQ handler */ - IRQ_HANDLER 115 /* PTMR IRQ handler */ - IRQ_HANDLER 116 /* PUART IRQ handler */ - IRQ_HANDLER 117 /* VAD IRQ handler */ - IRQ_HANDLER 118 /* FUSE IRQ handler */ - IRQ_HANDLER 119 /* SECMON IRQ handler */ - IRQ_HANDLER 120 /* RTC IRQ handler */ - IRQ_HANDLER 121 /* BUTN IRQ handler */ - IRQ_HANDLER 122 /* BGPIO IRQ handler */ - IRQ_HANDLER 123 /* BVIO IRQ handler */ - IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 125 /* SYSCTL IRQ handler */ - IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 10 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 11 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 13 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 14 /* GPIO1_E IRQ handler */ - IRQ_HANDLER 15 /* GPIO1_F IRQ handler */ - IRQ_HANDLER 16 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 17 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 18 /* GPIO1_Z IRQ handler */ - IRQ_HANDLER 19 /* ADC0 IRQ handler */ - IRQ_HANDLER 20 /* ADC1 IRQ handler */ - IRQ_HANDLER 21 /* ADC2 IRQ handler */ - IRQ_HANDLER 22 /* ADC3 IRQ handler */ - IRQ_HANDLER 23 /* ACMP[0] IRQ handler */ - IRQ_HANDLER 24 /* ACMP[1] IRQ handler */ - IRQ_HANDLER 25 /* ACMP[2] IRQ handler */ - IRQ_HANDLER 26 /* ACMP[3] IRQ handler */ - IRQ_HANDLER 27 /* SPI0 IRQ handler */ - IRQ_HANDLER 28 /* SPI1 IRQ handler */ - IRQ_HANDLER 29 /* SPI2 IRQ handler */ - IRQ_HANDLER 30 /* SPI3 IRQ handler */ - IRQ_HANDLER 31 /* UART0 IRQ handler */ - IRQ_HANDLER 32 /* UART1 IRQ handler */ - IRQ_HANDLER 33 /* UART2 IRQ handler */ - IRQ_HANDLER 34 /* UART3 IRQ handler */ - IRQ_HANDLER 35 /* UART4 IRQ handler */ - IRQ_HANDLER 36 /* UART5 IRQ handler */ - IRQ_HANDLER 37 /* UART6 IRQ handler */ - IRQ_HANDLER 38 /* UART7 IRQ handler */ - IRQ_HANDLER 39 /* UART8 IRQ handler */ - IRQ_HANDLER 40 /* UART9 IRQ handler */ - IRQ_HANDLER 41 /* UART10 IRQ handler */ - IRQ_HANDLER 42 /* UART11 IRQ handler */ - IRQ_HANDLER 43 /* UART12 IRQ handler */ - IRQ_HANDLER 44 /* UART13 IRQ handler */ - IRQ_HANDLER 45 /* UART14 IRQ handler */ - IRQ_HANDLER 46 /* UART15 IRQ handler */ - IRQ_HANDLER 47 /* CAN0 IRQ handler */ - IRQ_HANDLER 48 /* CAN1 IRQ handler */ - IRQ_HANDLER 49 /* CAN2 IRQ handler */ - IRQ_HANDLER 50 /* CAN3 IRQ handler */ - IRQ_HANDLER 51 /* PTPC IRQ handler */ - IRQ_HANDLER 52 /* WDG0 IRQ handler */ - IRQ_HANDLER 53 /* WDG1 IRQ handler */ - IRQ_HANDLER 54 /* WDG2 IRQ handler */ - IRQ_HANDLER 55 /* WDG3 IRQ handler */ - IRQ_HANDLER 56 /* MBX0A IRQ handler */ - IRQ_HANDLER 57 /* MBX0B IRQ handler */ - IRQ_HANDLER 58 /* MBX1A IRQ handler */ - IRQ_HANDLER 59 /* MBX1B IRQ handler */ - IRQ_HANDLER 60 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 61 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 62 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 63 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 64 /* GPTMR4 IRQ handler */ - IRQ_HANDLER 65 /* GPTMR5 IRQ handler */ - IRQ_HANDLER 66 /* GPTMR6 IRQ handler */ - IRQ_HANDLER 67 /* GPTMR7 IRQ handler */ - IRQ_HANDLER 68 /* I2C0 IRQ handler */ - IRQ_HANDLER 69 /* I2C1 IRQ handler */ - IRQ_HANDLER 70 /* I2C2 IRQ handler */ - IRQ_HANDLER 71 /* I2C3 IRQ handler */ - IRQ_HANDLER 72 /* PWM0 IRQ handler */ - IRQ_HANDLER 73 /* HALL0 IRQ handler */ - IRQ_HANDLER 74 /* QEI0 IRQ handler */ - IRQ_HANDLER 75 /* PWM1 IRQ handler */ - IRQ_HANDLER 76 /* HALL1 IRQ handler */ - IRQ_HANDLER 77 /* QEI1 IRQ handler */ - IRQ_HANDLER 78 /* PWM2 IRQ handler */ - IRQ_HANDLER 79 /* HALL2 IRQ handler */ - IRQ_HANDLER 80 /* QEI2 IRQ handler */ - IRQ_HANDLER 81 /* PWM3 IRQ handler */ - IRQ_HANDLER 82 /* HALL3 IRQ handler */ - IRQ_HANDLER 83 /* QEI3 IRQ handler */ - IRQ_HANDLER 84 /* SDP IRQ handler */ - IRQ_HANDLER 85 /* XPI0 IRQ handler */ - IRQ_HANDLER 86 /* XPI1 IRQ handler */ - IRQ_HANDLER 87 /* XDMA IRQ handler */ - IRQ_HANDLER 88 /* HDMA IRQ handler */ - IRQ_HANDLER 89 /* FEMC IRQ handler */ - IRQ_HANDLER 90 /* RNG IRQ handler */ - IRQ_HANDLER 91 /* I2S0 IRQ handler */ - IRQ_HANDLER 92 /* I2S1 IRQ handler */ - IRQ_HANDLER 93 /* I2S2 IRQ handler */ - IRQ_HANDLER 94 /* I2S3 IRQ handler */ - IRQ_HANDLER 95 /* DAO IRQ handler */ - IRQ_HANDLER 96 /* PDM IRQ handler */ - IRQ_HANDLER 97 /* CAM0 IRQ handler */ - IRQ_HANDLER 98 /* CAM1 IRQ handler */ - IRQ_HANDLER 99 /* LCDC_D0 IRQ handler */ - IRQ_HANDLER 100 /* LCDC_D1 IRQ handler */ - IRQ_HANDLER 101 /* PDMA_D0 IRQ handler */ - IRQ_HANDLER 102 /* PDMA_D1 IRQ handler */ - IRQ_HANDLER 103 /* JPEG IRQ handler */ - IRQ_HANDLER 104 /* NTMR0 IRQ handler */ - IRQ_HANDLER 105 /* NTMR1 IRQ handler */ - IRQ_HANDLER 106 /* USB0 IRQ handler */ - IRQ_HANDLER 107 /* USB1 IRQ handler */ - IRQ_HANDLER 108 /* ENET0 IRQ handler */ - IRQ_HANDLER 109 /* ENET1 IRQ handler */ - IRQ_HANDLER 110 /* SDXC0 IRQ handler */ - IRQ_HANDLER 111 /* SDXC1 IRQ handler */ - IRQ_HANDLER 112 /* PSEC IRQ handler */ - IRQ_HANDLER 113 /* PGPIO IRQ handler */ - IRQ_HANDLER 114 /* PWDG IRQ handler */ - IRQ_HANDLER 115 /* PTMR IRQ handler */ - IRQ_HANDLER 116 /* PUART IRQ handler */ - IRQ_HANDLER 117 /* VAD IRQ handler */ - IRQ_HANDLER 118 /* FUSE IRQ handler */ - IRQ_HANDLER 119 /* SECMON IRQ handler */ - IRQ_HANDLER 120 /* RTC IRQ handler */ - IRQ_HANDLER 121 /* BUTN IRQ handler */ - IRQ_HANDLER 122 /* BGPIO IRQ handler */ - IRQ_HANDLER 123 /* BVIO IRQ handler */ - IRQ_HANDLER 124 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 125 /* SYSCTL IRQ handler */ - IRQ_HANDLER 126 /* DEBUG[0] IRQ handler */ - IRQ_HANDLER 127 /* DEBUG[1] IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_acmp_regs.h deleted file mode 100644 index 9f7e0b6d9cd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_acmp_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ACMP_H -#define HPM_ACMP_H - -typedef struct { - struct { - __RW uint32_t CFG; /* 0x0: Configure Register */ - __RW uint32_t DACCFG; /* 0x4: DAC configure register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t SR; /* 0x10: Status register */ - __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */ - __RW uint32_t DMAEN; /* 0x18: DMA request enable register */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - } CHANNEL[4]; -} ACMP_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CFG */ -/* - * HYST (RW) - * - * This bitfield configure the comparator hysteresis. - * 00: Hysteresis level 0 - * 01: Hysteresis level 1 - * 10: Hysteresis level 2 - * 11: Hysteresis level 3 - */ -#define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) -#define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) -#define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) -#define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) - -/* - * DACEN (RW) - * - * This bit enable the comparator internal DAC - * 0: DAC disabled - * 1: DAC enabled - */ -#define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) -#define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) -#define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) -#define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) - -/* - * HPMODE (RW) - * - * This bit enable the comparator high performance mode. - * 0: HP mode disabled - * 1: HP mode enabled - */ -#define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) -#define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) -#define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) -#define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) - -/* - * CMPEN (RW) - * - * This bit enable the comparator. - * 0: ACMP disabled - * 1: ACMP enabled - */ -#define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) -#define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) -#define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) -#define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) - -/* - * MINSEL (RW) - * - * PIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) -#define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) -#define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) -#define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) - -/* - * PINSEL (RW) - * - * MIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) -#define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) -#define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) -#define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) - -/* - * CMPOEN (RW) - * - * This bit enable the comparator output on pad. - * 0: ACMP output disabled - * 1: ACMP output enabled - */ -#define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) -#define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) -#define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) -#define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) - -/* - * FLTBYPS (RW) - * - * This bit bypass the comparator output digital filter. - * 0: The ACMP output need pass digital filter - * 1: The ACMP output digital filter is bypassed. - */ -#define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) -#define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) -#define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) -#define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) - -/* - * WINEN (RW) - * - * This bit enable the comparator window mode. - * 0: Window mode is disabled - * 1: Window mode is enabled - */ -#define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) -#define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) -#define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) -#define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) - -/* - * OPOL (RW) - * - * The output polarity control bit. - * 0: The ACMP output remain un-changed. - * 1: The ACMP output is inverted. - */ -#define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) -#define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) -#define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) -#define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) - -/* - * FLTMODE (RW) - * - * This bitfield define the ACMP output digital filter mode: - * 000-bypass - * 100-change immediately; - * 101-change after filter; - * 110-stalbe low; - * 111-stable high - */ -#define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) -#define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) -#define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) -#define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) - -/* - * SYNCEN (RW) - * - * This bit enable the comparator output synchronization. - * 0: ACMP output not synchronized with ACMP clock. - * 1: ACMP output synchronized with ACMP clock. - */ -#define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) -#define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) -#define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) -#define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) - -/* - * FLTLEN (RW) - * - * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - */ -#define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) -#define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) -#define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) -#define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DACCFG */ -/* - * DACCFG (RW) - * - * 8bit DAC digital value output to analog block - */ -#define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) -#define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) -#define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) -#define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: SR */ -/* - * FEDGF (RW) - * - * Output falling edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) -#define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) -#define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) -#define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) - -/* - * REDGF (RW) - * - * Output rising edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) -#define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) -#define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) -#define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: IRQEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DMAEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) - - - -/* CHANNEL register group index macro definition */ -#define ACMP_CHANNEL_CHN0 (0UL) -#define ACMP_CHANNEL_CHN1 (1UL) -#define ACMP_CHANNEL_CHN2 (2UL) -#define ACMP_CHANNEL_CHN3 (3UL) - - -#endif /* HPM_ACMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_adc12_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_adc12_regs.h deleted file mode 100644 index 9b1fc9ca89e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_adc12_regs.h +++ /dev/null @@ -1,973 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC12_H -#define HPM_ADC12_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[19]; /* 0x400 - 0x448: */ - __R uint8_t RESERVED1[180]; /* 0x44C - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint32_t SEQ_WR_ADDR; /* 0x808: */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __R uint8_t RESERVED3[944]; /* 0x850 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[19]; - __R uint8_t RESERVED4[720]; /* 0xD30 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[19]; /* 0x1000 - 0x1048: */ - __R uint8_t RESERVED5[184]; /* 0x104C - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __RW uint32_t ANA_CTRL1; /* 0x1204: */ - __R uint8_t RESERVED8[8]; /* 0x1208 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ -} ADC12_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC12_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC12_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC12_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC12_CONFIG_TRIG_LEN_SHIFT) & ADC12_CONFIG_TRIG_LEN_MASK) -#define ADC12_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC12_CONFIG_TRIG_LEN_MASK) >> ADC12_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC12_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC12_CONFIG_INTEN3_SHIFT (29U) -#define ADC12_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN3_SHIFT) & ADC12_CONFIG_INTEN3_MASK) -#define ADC12_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN3_MASK) >> ADC12_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC12_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC12_CONFIG_CHAN3_SHIFT (24U) -#define ADC12_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN3_SHIFT) & ADC12_CONFIG_CHAN3_MASK) -#define ADC12_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN3_MASK) >> ADC12_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC12_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC12_CONFIG_INTEN2_SHIFT (21U) -#define ADC12_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN2_SHIFT) & ADC12_CONFIG_INTEN2_MASK) -#define ADC12_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN2_MASK) >> ADC12_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC12_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC12_CONFIG_CHAN2_SHIFT (16U) -#define ADC12_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN2_SHIFT) & ADC12_CONFIG_CHAN2_MASK) -#define ADC12_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN2_MASK) >> ADC12_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC12_CONFIG_INTEN1_MASK (0x2000U) -#define ADC12_CONFIG_INTEN1_SHIFT (13U) -#define ADC12_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN1_SHIFT) & ADC12_CONFIG_INTEN1_MASK) -#define ADC12_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN1_MASK) >> ADC12_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC12_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC12_CONFIG_CHAN1_SHIFT (8U) -#define ADC12_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN1_SHIFT) & ADC12_CONFIG_CHAN1_MASK) -#define ADC12_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN1_MASK) >> ADC12_CONFIG_CHAN1_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC12_CONFIG_INTEN0_MASK (0x20U) -#define ADC12_CONFIG_INTEN0_SHIFT (5U) -#define ADC12_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC12_CONFIG_INTEN0_SHIFT) & ADC12_CONFIG_INTEN0_MASK) -#define ADC12_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC12_CONFIG_INTEN0_MASK) >> ADC12_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC12_CONFIG_CHAN0_MASK (0x1FU) -#define ADC12_CONFIG_CHAN0_SHIFT (0U) -#define ADC12_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC12_CONFIG_CHAN0_SHIFT) & ADC12_CONFIG_CHAN0_MASK) -#define ADC12_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC12_CONFIG_CHAN0_MASK) >> ADC12_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC12_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC12_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC12_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC12_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC12_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC12_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC12_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC12_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC12_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC12_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC12_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC12_BUS_RESULT_VALID_SHIFT (16U) -#define ADC12_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_VALID_MASK) >> ADC12_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC12_BUS_RESULT_CHAN_RESULT_MASK (0xFFF0U) -#define ADC12_BUS_RESULT_CHAN_RESULT_SHIFT (4U) -#define ADC12_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_BUS_RESULT_CHAN_RESULT_MASK) >> ADC12_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC12_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC12_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC12_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC12_BUF_CFG0_WAIT_DIS_SHIFT) & ADC12_BUF_CFG0_WAIT_DIS_MASK) -#define ADC12_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC12_BUF_CFG0_WAIT_DIS_MASK) >> ADC12_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC12_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC12_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC12_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_CYCLE_MASK) >> ADC12_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC12_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC12_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC12_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC12_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC12_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SEQ_LEN_MASK) >> ADC12_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC12_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC12_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC12_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_RESTART_EN_SHIFT) & ADC12_SEQ_CFG0_RESTART_EN_MASK) -#define ADC12_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_RESTART_EN_MASK) >> ADC12_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC12_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC12_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC12_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_CONT_EN_SHIFT) & ADC12_SEQ_CFG0_CONT_EN_MASK) -#define ADC12_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_CONT_EN_MASK) >> ADC12_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC12_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC12_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC12_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SW_TRIG_SHIFT) & ADC12_SEQ_CFG0_SW_TRIG_MASK) -#define ADC12_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SW_TRIG_MASK) >> ADC12_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC12_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC12_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC12_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC12_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC12_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC12_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC12_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC12_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC12_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC12_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC12_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC12_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_WR_ADDR */ -/* - * SEQ_WR_POINTER (RO) - * - * HW update this field after each dma write, it indicate the next dma write pointer. - * dma write address is (tar_addr+seq_wr_pointer)*4 - */ -#define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFU) -#define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) -#define ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC12_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC12_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC12_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC12_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC12_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC12_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC12_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC12_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC12_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC12_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC12_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC12_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC12_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC12_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC12_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC12_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC12_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC12_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC12_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC12_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC12_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC12_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC12_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC12_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC12_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC12_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC12_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC12_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC12_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC12_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC12_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC12_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC12_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC12_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC12_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC12_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC12_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC12_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFF00000UL) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (20U) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFF0U) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (4U) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC12_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFF0U) -#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (4U) -#define ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC12_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * DIFF_SEL (RW) - * - * set to 1 to select differential channel - */ -#define ADC12_SAMPLE_CFG_DIFF_SEL_MASK (0x1000U) -#define ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT (12U) -#define ADC12_SAMPLE_CFG_DIFF_SEL_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT) & ADC12_SAMPLE_CFG_DIFF_SEL_MASK) -#define ADC12_SAMPLE_CFG_DIFF_SEL_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_DIFF_SEL_MASK) >> ADC12_SAMPLE_CFG_DIFF_SEL_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample_clock_number - */ -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC12_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 13 (0xD) for 12bit mode, which means convert need 14 adc clock cycles(based on clock after divider); - * set to 11 for 10bit mode; set to 9 for 8bit mode; set to 7 or 6bit mode; - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 13 for 12bit mode, clock_divder to 2, then each ADC conversion(plus sample) need 18(14 convert, 4 sample) cycles(66MHz). - */ -#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC12_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC12_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC12_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC12_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC12_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC12_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC12_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC12_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC12_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC12_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC12_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC12_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC12_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC12_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC12_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC12_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC12_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC12_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_CMPT_SHIFT) & ADC12_INT_STS_TRIG_CMPT_MASK) -#define ADC12_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_CMPT_MASK) >> ADC12_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC12_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC12_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC12_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC12_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC12_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC12_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC12_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC12_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC12_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC12_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_READ_CFLCT_SHIFT) & ADC12_INT_STS_READ_CFLCT_MASK) -#define ADC12_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_READ_CFLCT_MASK) >> ADC12_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC12_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC12_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC12_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC12_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC12_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC12_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC12_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC12_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC12_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC12_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_DMAABT_SHIFT) & ADC12_INT_STS_SEQ_DMAABT_MASK) -#define ADC12_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_DMAABT_MASK) >> ADC12_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC12_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC12_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC12_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_CMPT_SHIFT) & ADC12_INT_STS_SEQ_CMPT_MASK) -#define ADC12_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CMPT_MASK) >> ADC12_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC12_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC12_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC12_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC12_INT_STS_SEQ_CVC_SHIFT) & ADC12_INT_STS_SEQ_CVC_MASK) -#define ADC12_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_STS_SEQ_CVC_MASK) >> ADC12_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - */ -#define ADC12_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC12_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC12_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC12_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_STS_DMA_FIFO_FULL_MASK) >> ADC12_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1 - */ -#define ADC12_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC12_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC12_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC12_INT_STS_AHB_ERR_SHIFT) & ADC12_INT_STS_AHB_ERR_MASK) -#define ADC12_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_STS_AHB_ERR_MASK) >> ADC12_INT_STS_AHB_ERR_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC12_INT_STS_WDOG_MASK (0x7FFFFUL) -#define ADC12_INT_STS_WDOG_SHIFT (0U) -#define ADC12_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC12_INT_STS_WDOG_SHIFT) & ADC12_INT_STS_WDOG_MASK) -#define ADC12_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC12_INT_STS_WDOG_MASK) >> ADC12_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC12_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC12_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC12_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_CMPT_SHIFT) & ADC12_INT_EN_TRIG_CMPT_MASK) -#define ADC12_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_CMPT_MASK) >> ADC12_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC12_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC12_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC12_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC12_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC12_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC12_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC12_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC12_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC12_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC12_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC12_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_READ_CFLCT_SHIFT) & ADC12_INT_EN_READ_CFLCT_MASK) -#define ADC12_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_READ_CFLCT_MASK) >> ADC12_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC12_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC12_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC12_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC12_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC12_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC12_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC12_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC12_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC12_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC12_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC12_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_DMAABT_SHIFT) & ADC12_INT_EN_SEQ_DMAABT_MASK) -#define ADC12_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_DMAABT_MASK) >> ADC12_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC12_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC12_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC12_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_CMPT_SHIFT) & ADC12_INT_EN_SEQ_CMPT_MASK) -#define ADC12_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CMPT_MASK) >> ADC12_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC12_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC12_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC12_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC12_INT_EN_SEQ_CVC_SHIFT) & ADC12_INT_EN_SEQ_CVC_MASK) -#define ADC12_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC12_INT_EN_SEQ_CVC_MASK) >> ADC12_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC12_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC12_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC12_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC12_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC12_INT_EN_DMA_FIFO_FULL_MASK) >> ADC12_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC12_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC12_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC12_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC12_INT_EN_AHB_ERR_SHIFT) & ADC12_INT_EN_AHB_ERR_MASK) -#define ADC12_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC12_INT_EN_AHB_ERR_MASK) >> ADC12_INT_EN_AHB_ERR_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC12_INT_EN_WDOG_MASK (0x7FFFFUL) -#define ADC12_INT_EN_WDOG_SHIFT (0U) -#define ADC12_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC12_INT_EN_WDOG_SHIFT) & ADC12_INT_EN_WDOG_MASK) -#define ADC12_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC12_INT_EN_WDOG_MASK) >> ADC12_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * CAL_VAL_DIFF (RW) - * - * calibration value for differential mode - */ -#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK (0x7F000000UL) -#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT (24U) -#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT) & ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) -#define ADC12_ANA_CTRL0_CAL_VAL_DIFF_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_CAL_VAL_DIFF_MASK) >> ADC12_ANA_CTRL0_CAL_VAL_DIFF_SHIFT) - -/* - * CAL_VAL_SE (RW) - * - * calibration value for single-end mode - */ -#define ADC12_ANA_CTRL0_CAL_VAL_SE_MASK (0x7F0000UL) -#define ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT (16U) -#define ADC12_ANA_CTRL0_CAL_VAL_SE_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT) & ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) -#define ADC12_ANA_CTRL0_CAL_VAL_SE_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_CAL_VAL_SE_MASK) >> ADC12_ANA_CTRL0_CAL_VAL_SE_SHIFT) - -/* - * REARM_EN (RW) - * - * set will insert one adc cycle rearm before sample, user need to increase one to sample_clock_number - */ -#define ADC12_ANA_CTRL0_REARM_EN_MASK (0x4000U) -#define ADC12_ANA_CTRL0_REARM_EN_SHIFT (14U) -#define ADC12_ANA_CTRL0_REARM_EN_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_REARM_EN_SHIFT) & ADC12_ANA_CTRL0_REARM_EN_MASK) -#define ADC12_ANA_CTRL0_REARM_EN_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_REARM_EN_MASK) >> ADC12_ANA_CTRL0_REARM_EN_SHIFT) - -/* - * SELRANGE_LDO (RW) - * - * Defines the range for the LDO reference (vdd_soc) - * selrange_ldo = 0: LDO reference dvdd or vref_ldo in range [0.81;0.99] - * selrange_ldo = 1: LDO reference dvdd or vref_ldo in range [0.99;1.21] - */ -#define ADC12_ANA_CTRL0_SELRANGE_LDO_MASK (0x800U) -#define ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT (11U) -#define ADC12_ANA_CTRL0_SELRANGE_LDO_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT) & ADC12_ANA_CTRL0_SELRANGE_LDO_MASK) -#define ADC12_ANA_CTRL0_SELRANGE_LDO_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_SELRANGE_LDO_MASK) >> ADC12_ANA_CTRL0_SELRANGE_LDO_SHIFT) - -/* - * ENLDO (RW) - * - * set to enable adc LDO, need at least 20us for LDO to be stable. - */ -#define ADC12_ANA_CTRL0_ENLDO_MASK (0x40U) -#define ADC12_ANA_CTRL0_ENLDO_SHIFT (6U) -#define ADC12_ANA_CTRL0_ENLDO_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_ENLDO_SHIFT) & ADC12_ANA_CTRL0_ENLDO_MASK) -#define ADC12_ANA_CTRL0_ENLDO_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_ENLDO_MASK) >> ADC12_ANA_CTRL0_ENLDO_SHIFT) - -/* - * ENADC (RW) - * - * set to enable adc analog function. user need set it after LDO stable, or wait at least 20us after setting enldo, then set this bit. - */ -#define ADC12_ANA_CTRL0_ENADC_MASK (0x20U) -#define ADC12_ANA_CTRL0_ENADC_SHIFT (5U) -#define ADC12_ANA_CTRL0_ENADC_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_ENADC_SHIFT) & ADC12_ANA_CTRL0_ENADC_MASK) -#define ADC12_ANA_CTRL0_ENADC_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_ENADC_MASK) >> ADC12_ANA_CTRL0_ENADC_SHIFT) - -/* - * RESETADC (RW) - * - * set to 1 to reset adc analog; default high. - */ -#define ADC12_ANA_CTRL0_RESETADC_MASK (0x10U) -#define ADC12_ANA_CTRL0_RESETADC_SHIFT (4U) -#define ADC12_ANA_CTRL0_RESETADC_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_RESETADC_SHIFT) & ADC12_ANA_CTRL0_RESETADC_MASK) -#define ADC12_ANA_CTRL0_RESETADC_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_RESETADC_MASK) >> ADC12_ANA_CTRL0_RESETADC_SHIFT) - -/* - * RESETCAL (RW) - * - * set to 1 to reset calibration logic; default high. - */ -#define ADC12_ANA_CTRL0_RESETCAL_MASK (0x8U) -#define ADC12_ANA_CTRL0_RESETCAL_SHIFT (3U) -#define ADC12_ANA_CTRL0_RESETCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_RESETCAL_SHIFT) & ADC12_ANA_CTRL0_RESETCAL_MASK) -#define ADC12_ANA_CTRL0_RESETCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_RESETCAL_MASK) >> ADC12_ANA_CTRL0_RESETCAL_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC12_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC12_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC12_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_STARTCAL_SHIFT) & ADC12_ANA_CTRL0_STARTCAL_MASK) -#define ADC12_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_STARTCAL_MASK) >> ADC12_ANA_CTRL0_STARTCAL_SHIFT) - -/* - * LOADCAL (RW) - * - * Signal that loads the offset calibration word into the internal registers (Active H) - */ -#define ADC12_ANA_CTRL0_LOADCAL_MASK (0x2U) -#define ADC12_ANA_CTRL0_LOADCAL_SHIFT (1U) -#define ADC12_ANA_CTRL0_LOADCAL_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL0_LOADCAL_SHIFT) & ADC12_ANA_CTRL0_LOADCAL_MASK) -#define ADC12_ANA_CTRL0_LOADCAL_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL0_LOADCAL_MASK) >> ADC12_ANA_CTRL0_LOADCAL_SHIFT) - -/* Bitfield definition for register: ANA_CTRL1 */ -/* - * SELRES (RW) - * - * 11-12bit - * 10-10bit - * 01-8bit - * 00-6bit - */ -#define ADC12_ANA_CTRL1_SELRES_MASK (0xC0U) -#define ADC12_ANA_CTRL1_SELRES_SHIFT (6U) -#define ADC12_ANA_CTRL1_SELRES_SET(x) (((uint32_t)(x) << ADC12_ANA_CTRL1_SELRES_SHIFT) & ADC12_ANA_CTRL1_SELRES_MASK) -#define ADC12_ANA_CTRL1_SELRES_GET(x) (((uint32_t)(x) & ADC12_ANA_CTRL1_SELRES_MASK) >> ADC12_ANA_CTRL1_SELRES_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC12_ANA_STATUS_CALON_MASK (0x80U) -#define ADC12_ANA_STATUS_CALON_SHIFT (7U) -#define ADC12_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC12_ANA_STATUS_CALON_SHIFT) & ADC12_ANA_STATUS_CALON_MASK) -#define ADC12_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC12_ANA_STATUS_CALON_MASK) >> ADC12_ANA_STATUS_CALON_SHIFT) - -/* - * CAL_OUT (RW) - * - */ -#define ADC12_ANA_STATUS_CAL_OUT_MASK (0x7FU) -#define ADC12_ANA_STATUS_CAL_OUT_SHIFT (0U) -#define ADC12_ANA_STATUS_CAL_OUT_SET(x) (((uint32_t)(x) << ADC12_ANA_STATUS_CAL_OUT_SHIFT) & ADC12_ANA_STATUS_CAL_OUT_MASK) -#define ADC12_ANA_STATUS_CAL_OUT_GET(x) (((uint32_t)(x) & ADC12_ANA_STATUS_CAL_OUT_MASK) >> ADC12_ANA_STATUS_CAL_OUT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC12_CONFIG_TRG0A (0UL) -#define ADC12_CONFIG_TRG0B (1UL) -#define ADC12_CONFIG_TRG0C (2UL) -#define ADC12_CONFIG_TRG1A (3UL) -#define ADC12_CONFIG_TRG1B (4UL) -#define ADC12_CONFIG_TRG1C (5UL) -#define ADC12_CONFIG_TRG2A (6UL) -#define ADC12_CONFIG_TRG2B (7UL) -#define ADC12_CONFIG_TRG2C (8UL) -#define ADC12_CONFIG_TRG3A (9UL) -#define ADC12_CONFIG_TRG3B (10UL) -#define ADC12_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC12_BUS_RESULT_CHN0 (0UL) -#define ADC12_BUS_RESULT_CHN1 (1UL) -#define ADC12_BUS_RESULT_CHN2 (2UL) -#define ADC12_BUS_RESULT_CHN3 (3UL) -#define ADC12_BUS_RESULT_CHN4 (4UL) -#define ADC12_BUS_RESULT_CHN5 (5UL) -#define ADC12_BUS_RESULT_CHN6 (6UL) -#define ADC12_BUS_RESULT_CHN7 (7UL) -#define ADC12_BUS_RESULT_CHN8 (8UL) -#define ADC12_BUS_RESULT_CHN9 (9UL) -#define ADC12_BUS_RESULT_CHN10 (10UL) -#define ADC12_BUS_RESULT_CHN11 (11UL) -#define ADC12_BUS_RESULT_CHN12 (12UL) -#define ADC12_BUS_RESULT_CHN13 (13UL) -#define ADC12_BUS_RESULT_CHN14 (14UL) -#define ADC12_BUS_RESULT_CHN15 (15UL) -#define ADC12_BUS_RESULT_CHN16 (16UL) -#define ADC12_BUS_RESULT_CHN17 (17UL) -#define ADC12_BUS_RESULT_CHN18 (18UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC12_SEQ_QUE_CFG0 (0UL) -#define ADC12_SEQ_QUE_CFG1 (1UL) -#define ADC12_SEQ_QUE_CFG2 (2UL) -#define ADC12_SEQ_QUE_CFG3 (3UL) -#define ADC12_SEQ_QUE_CFG4 (4UL) -#define ADC12_SEQ_QUE_CFG5 (5UL) -#define ADC12_SEQ_QUE_CFG6 (6UL) -#define ADC12_SEQ_QUE_CFG7 (7UL) -#define ADC12_SEQ_QUE_CFG8 (8UL) -#define ADC12_SEQ_QUE_CFG9 (9UL) -#define ADC12_SEQ_QUE_CFG10 (10UL) -#define ADC12_SEQ_QUE_CFG11 (11UL) -#define ADC12_SEQ_QUE_CFG12 (12UL) -#define ADC12_SEQ_QUE_CFG13 (13UL) -#define ADC12_SEQ_QUE_CFG14 (14UL) -#define ADC12_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC12_PRD_CFG_CHN0 (0UL) -#define ADC12_PRD_CFG_CHN1 (1UL) -#define ADC12_PRD_CFG_CHN2 (2UL) -#define ADC12_PRD_CFG_CHN3 (3UL) -#define ADC12_PRD_CFG_CHN4 (4UL) -#define ADC12_PRD_CFG_CHN5 (5UL) -#define ADC12_PRD_CFG_CHN6 (6UL) -#define ADC12_PRD_CFG_CHN7 (7UL) -#define ADC12_PRD_CFG_CHN8 (8UL) -#define ADC12_PRD_CFG_CHN9 (9UL) -#define ADC12_PRD_CFG_CHN10 (10UL) -#define ADC12_PRD_CFG_CHN11 (11UL) -#define ADC12_PRD_CFG_CHN12 (12UL) -#define ADC12_PRD_CFG_CHN13 (13UL) -#define ADC12_PRD_CFG_CHN14 (14UL) -#define ADC12_PRD_CFG_CHN15 (15UL) -#define ADC12_PRD_CFG_CHN16 (16UL) -#define ADC12_PRD_CFG_CHN17 (17UL) -#define ADC12_PRD_CFG_CHN18 (18UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC12_SAMPLE_CFG_CHN0 (0UL) -#define ADC12_SAMPLE_CFG_CHN1 (1UL) -#define ADC12_SAMPLE_CFG_CHN2 (2UL) -#define ADC12_SAMPLE_CFG_CHN3 (3UL) -#define ADC12_SAMPLE_CFG_CHN4 (4UL) -#define ADC12_SAMPLE_CFG_CHN5 (5UL) -#define ADC12_SAMPLE_CFG_CHN6 (6UL) -#define ADC12_SAMPLE_CFG_CHN7 (7UL) -#define ADC12_SAMPLE_CFG_CHN8 (8UL) -#define ADC12_SAMPLE_CFG_CHN9 (9UL) -#define ADC12_SAMPLE_CFG_CHN10 (10UL) -#define ADC12_SAMPLE_CFG_CHN11 (11UL) -#define ADC12_SAMPLE_CFG_CHN12 (12UL) -#define ADC12_SAMPLE_CFG_CHN13 (13UL) -#define ADC12_SAMPLE_CFG_CHN14 (14UL) -#define ADC12_SAMPLE_CFG_CHN15 (15UL) -#define ADC12_SAMPLE_CFG_CHN16 (16UL) -#define ADC12_SAMPLE_CFG_CHN17 (17UL) -#define ADC12_SAMPLE_CFG_CHN18 (18UL) - - -#endif /* HPM_ADC12_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_adc16_regs.h deleted file mode 100644 index a6af101e258..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_adc16_regs.h +++ /dev/null @@ -1,951 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC16_H -#define HPM_ADC16_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[8]; /* 0x400 - 0x41C: */ - __R uint8_t RESERVED1[224]; /* 0x420 - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint8_t RESERVED3[4]; /* 0x808 - 0x80B: Reserved */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __R uint8_t RESERVED4[944]; /* 0x850 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[8]; - __R uint8_t RESERVED5[896]; /* 0xC80 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[8]; /* 0x1000 - 0x101C: */ - __R uint8_t RESERVED6[228]; /* 0x1020 - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED7[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __R uint8_t RESERVED8[232]; /* 0x1118 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __R uint8_t RESERVED9[12]; /* 0x1204 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ - __R uint8_t RESERVED10[492]; /* 0x1214 - 0x13FF: Reserved */ - __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ - __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ - __R uint8_t RESERVED11[24]; /* 0x1448 - 0x145F: Reserved */ - __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ -} ADC16_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) -#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC16_CONFIG_INTEN3_SHIFT (29U) -#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) -#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC16_CONFIG_CHAN3_SHIFT (24U) -#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) -#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC16_CONFIG_INTEN2_SHIFT (21U) -#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) -#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC16_CONFIG_CHAN2_SHIFT (16U) -#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) -#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC16_CONFIG_INTEN1_MASK (0x2000U) -#define ADC16_CONFIG_INTEN1_SHIFT (13U) -#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) -#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC16_CONFIG_CHAN1_SHIFT (8U) -#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) -#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC16_CONFIG_INTEN0_MASK (0x20U) -#define ADC16_CONFIG_INTEN0_SHIFT (5U) -#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) -#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC16_CONFIG_CHAN0_MASK (0x1FU) -#define ADC16_CONFIG_CHAN0_SHIFT (0U) -#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) -#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC16_BUS_RESULT_VALID_SHIFT (16U) -#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) -#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) -#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) -#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample clock number - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); - * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - */ -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* - * PORT3_REALTIME (RW) - * - * set to enable trg queue stop other queues - */ -#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) -#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) -#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) -#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) -#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) -#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) -#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) -#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_STS_WDOG_MASK (0xFFFFU) -#define ADC16_INT_STS_WDOG_SHIFT (0U) -#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) -#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) -#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) -#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) -#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) -#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) -#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) -#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_EN_WDOG_MASK (0xFFFFU) -#define ADC16_INT_EN_WDOG_SHIFT (0U) -#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) -#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * ADC_CLK_ON (RW) - * - * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. - * MUST set clock_period to 0 or 1 for adc16 reg access - */ -#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) -#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC16_ANA_STATUS_CALON_MASK (0x80U) -#define ADC16_ANA_STATUS_CALON_SHIFT (7U) -#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) -#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) - -/* Bitfield definition for register array: ADC16_PARAMS */ -/* - * PARAM_VAL (RW) - * - */ -#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) -#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG0 */ -/* - * TEMPSNS_EN (RW) - * - * set to enable temp sensor - */ -#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK (0x2000000UL) -#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_SHIFT (25U) -#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_TEMPSNS_EN_SHIFT) & ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK) -#define ADC16_ADC16_CONFIG0_TEMPSNS_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_TEMPSNS_EN_MASK) >> ADC16_ADC16_CONFIG0_TEMPSNS_EN_SHIFT) - -/* - * REG_EN (RW) - * - * set to enable regulator - */ -#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) -#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) -#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) -#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) - -/* - * BANDGAP_EN (RW) - * - * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - */ -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) - -/* - * CAL_AVG_CFG (RW) - * - * for average the calibration result. - * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; - * 4- 16 loops; 5-32 loops; others reserved - */ -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) - -/* - * PREEMPT_EN (RW) - * - * set to enable preemption feature - */ -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) - -/* - * CONV_PARAM (RW) - * - * conversion parameter - */ -#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG1 */ -/* - * COV_END_CNT (RW) - * - * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number+1). - */ -#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC16_CONFIG_TRG0A (0UL) -#define ADC16_CONFIG_TRG0B (1UL) -#define ADC16_CONFIG_TRG0C (2UL) -#define ADC16_CONFIG_TRG1A (3UL) -#define ADC16_CONFIG_TRG1B (4UL) -#define ADC16_CONFIG_TRG1C (5UL) -#define ADC16_CONFIG_TRG2A (6UL) -#define ADC16_CONFIG_TRG2B (7UL) -#define ADC16_CONFIG_TRG2C (8UL) -#define ADC16_CONFIG_TRG3A (9UL) -#define ADC16_CONFIG_TRG3B (10UL) -#define ADC16_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC16_BUS_RESULT_CHN0 (0UL) -#define ADC16_BUS_RESULT_CHN1 (1UL) -#define ADC16_BUS_RESULT_CHN2 (2UL) -#define ADC16_BUS_RESULT_CHN3 (3UL) -#define ADC16_BUS_RESULT_CHN4 (4UL) -#define ADC16_BUS_RESULT_CHN5 (5UL) -#define ADC16_BUS_RESULT_CHN6 (6UL) -#define ADC16_BUS_RESULT_CHN7 (7UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC16_SEQ_QUE_CFG0 (0UL) -#define ADC16_SEQ_QUE_CFG1 (1UL) -#define ADC16_SEQ_QUE_CFG2 (2UL) -#define ADC16_SEQ_QUE_CFG3 (3UL) -#define ADC16_SEQ_QUE_CFG4 (4UL) -#define ADC16_SEQ_QUE_CFG5 (5UL) -#define ADC16_SEQ_QUE_CFG6 (6UL) -#define ADC16_SEQ_QUE_CFG7 (7UL) -#define ADC16_SEQ_QUE_CFG8 (8UL) -#define ADC16_SEQ_QUE_CFG9 (9UL) -#define ADC16_SEQ_QUE_CFG10 (10UL) -#define ADC16_SEQ_QUE_CFG11 (11UL) -#define ADC16_SEQ_QUE_CFG12 (12UL) -#define ADC16_SEQ_QUE_CFG13 (13UL) -#define ADC16_SEQ_QUE_CFG14 (14UL) -#define ADC16_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC16_PRD_CFG_CHN0 (0UL) -#define ADC16_PRD_CFG_CHN1 (1UL) -#define ADC16_PRD_CFG_CHN2 (2UL) -#define ADC16_PRD_CFG_CHN3 (3UL) -#define ADC16_PRD_CFG_CHN4 (4UL) -#define ADC16_PRD_CFG_CHN5 (5UL) -#define ADC16_PRD_CFG_CHN6 (6UL) -#define ADC16_PRD_CFG_CHN7 (7UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC16_SAMPLE_CFG_CHN0 (0UL) -#define ADC16_SAMPLE_CFG_CHN1 (1UL) -#define ADC16_SAMPLE_CFG_CHN2 (2UL) -#define ADC16_SAMPLE_CFG_CHN3 (3UL) -#define ADC16_SAMPLE_CFG_CHN4 (4UL) -#define ADC16_SAMPLE_CFG_CHN5 (5UL) -#define ADC16_SAMPLE_CFG_CHN6 (6UL) -#define ADC16_SAMPLE_CFG_CHN7 (7UL) - -/* ADC16_PARAMS register group index macro definition */ -#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) - - -#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bcfg_regs.h deleted file mode 100644 index 30b36db600e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bcfg_regs.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BCFG_H -#define HPM_BCFG_H - -typedef struct { - __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ - __RW uint32_t LDO_CFG; /* 0x4: LDO config */ - __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ - __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ - __RW uint32_t CLK_CFG; /* 0x10: Clock config */ -} BCFG_Type; - - -/* Bitfield definition for register: VBG_CFG */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) -#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) -#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) -#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) - -/* - * LP_MODE (RW) - * - * Bandgap works in low power mode - * 0: not in low power mode - * 1: bandgap work in low power mode - */ -#define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL) -#define BCFG_VBG_CFG_LP_MODE_SHIFT (25U) -#define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK) -#define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Bandgap works in power save mode - * 0: not in power save mode - * 1: bandgap work in power save mode - */ -#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) -#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) -#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) -#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) - -/* - * VBG_1P0 (RW) - * - * Bandgap 1.0V output trim - */ -#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) -#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) -#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) -#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) - -/* - * VBG_P65 (RW) - * - * Bandgap 0.65V output trim - */ -#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) -#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) -#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) -#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) - -/* - * VBG_P50 (RW) - * - * Bandgap 0.50V output trim - */ -#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) -#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) -#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) -#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) - -/* Bitfield definition for register: LDO_CFG */ -/* - * RES_TRIM (RW) - * - * Resistor trim - */ -#define BCFG_LDO_CFG_RES_TRIM_MASK (0x3000000UL) -#define BCFG_LDO_CFG_RES_TRIM_SHIFT (24U) -#define BCFG_LDO_CFG_RES_TRIM_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_RES_TRIM_SHIFT) & BCFG_LDO_CFG_RES_TRIM_MASK) -#define BCFG_LDO_CFG_RES_TRIM_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_RES_TRIM_MASK) >> BCFG_LDO_CFG_RES_TRIM_SHIFT) - -/* - * CP_TRIM (RW) - * - * Capacitor trim - */ -#define BCFG_LDO_CFG_CP_TRIM_MASK (0x300000UL) -#define BCFG_LDO_CFG_CP_TRIM_SHIFT (20U) -#define BCFG_LDO_CFG_CP_TRIM_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_CP_TRIM_SHIFT) & BCFG_LDO_CFG_CP_TRIM_MASK) -#define BCFG_LDO_CFG_CP_TRIM_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_CP_TRIM_MASK) >> BCFG_LDO_CFG_CP_TRIM_SHIFT) - -/* - * EN_SL (RW) - * - * enable selfload, this bit helps improve LDO performance when current less than 200nA - * 0: self load disabled - * 1: selfload enabled - */ -#define BCFG_LDO_CFG_EN_SL_MASK (0x40000UL) -#define BCFG_LDO_CFG_EN_SL_SHIFT (18U) -#define BCFG_LDO_CFG_EN_SL_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_EN_SL_SHIFT) & BCFG_LDO_CFG_EN_SL_MASK) -#define BCFG_LDO_CFG_EN_SL_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_EN_SL_MASK) >> BCFG_LDO_CFG_EN_SL_SHIFT) - -/* - * DIS_PD (RW) - * - * disable pull down resistor, enable pull down may lead to more power but better response - * 0: pulldown resistor enabled - * 1: pulldown resistor disabled - */ -#define BCFG_LDO_CFG_DIS_PD_MASK (0x20000UL) -#define BCFG_LDO_CFG_DIS_PD_SHIFT (17U) -#define BCFG_LDO_CFG_DIS_PD_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_DIS_PD_SHIFT) & BCFG_LDO_CFG_DIS_PD_MASK) -#define BCFG_LDO_CFG_DIS_PD_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_DIS_PD_MASK) >> BCFG_LDO_CFG_DIS_PD_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: LDO is disabled - * 1: LDO is enabled - */ -#define BCFG_LDO_CFG_ENABLE_MASK (0x10000UL) -#define BCFG_LDO_CFG_ENABLE_SHIFT (16U) -#define BCFG_LDO_CFG_ENABLE_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_ENABLE_SHIFT) & BCFG_LDO_CFG_ENABLE_MASK) -#define BCFG_LDO_CFG_ENABLE_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_ENABLE_MASK) >> BCFG_LDO_CFG_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO voltage setting in mV, valid range through 600mV to 1100mV, step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1100mV. - * 600: 600mV - * 620: 620mV - * . . . - * 1100:1100mV - */ -#define BCFG_LDO_CFG_VOLT_MASK (0xFFFU) -#define BCFG_LDO_CFG_VOLT_SHIFT (0U) -#define BCFG_LDO_CFG_VOLT_SET(x) (((uint32_t)(x) << BCFG_LDO_CFG_VOLT_SHIFT) & BCFG_LDO_CFG_VOLT_MASK) -#define BCFG_LDO_CFG_VOLT_GET(x) (((uint32_t)(x) & BCFG_LDO_CFG_VOLT_MASK) >> BCFG_LDO_CFG_VOLT_SHIFT) - -/* Bitfield definition for register: IRC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) -#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: XTAL32K_CFG */ -/* - * HYST_EN (RW) - * - * crystal 32k hysteres enable - */ -#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) -#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) -#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) -#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) - -/* - * GMSEL (RW) - * - * crystal 32k gm selection - */ -#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) -#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) -#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) -#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) - -/* - * CFG (RW) - * - * crystal 32k config - */ -#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) -#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) -#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) -#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) - -/* - * AMP (RW) - * - * crystal 32k amplifier - */ -#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) -#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) -#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) -#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) - -/* Bitfield definition for register: CLK_CFG */ -/* - * XTAL_SEL (RO) - * - * crystal selected - */ -#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) -#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) -#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) - -/* - * KEEP_IRC (RW) - * - * force irc32k run - */ -#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) -#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) -#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) -#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) - -/* - * FORCE_XTAL (RW) - * - * force switch to crystal - */ -#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) -#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) -#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) -#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) - - - - -#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bgpr_regs.h deleted file mode 100644 index 9d81aab19cf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bgpr_regs.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BGPR_H -#define HPM_BGPR_H - -typedef struct { - __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ -} BGPR_Type; - - -/* Bitfield definition for register array: GPR */ -/* - * DATA (RW) - * - * Generic control - */ -#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) -#define BGPR_GPR_DATA_SHIFT (0U) -#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) -#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) - - - -/* GPR register group index macro definition */ -#define BGPR_GPR_0 (0UL) -#define BGPR_GPR_1 (1UL) -#define BGPR_GPR_2 (2UL) -#define BGPR_GPR_3 (3UL) -#define BGPR_GPR_4 (4UL) -#define BGPR_GPR_5 (5UL) -#define BGPR_GPR_6 (6UL) -#define BGPR_GPR_7 (7UL) - - -#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bkey_regs.h deleted file mode 100644 index 1c82a4b90e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bkey_regs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BKEY_H -#define HPM_BKEY_H - -typedef struct { - struct { - __RW uint32_t DATA[8]; /* 0x0 - 0x1C: Key data */ - } KEY[2]; - __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ - __RW uint32_t SELECT; /* 0x48: Key selection */ -} BKEY_Type; - - -/* Bitfield definition for register of struct array KEY: 0 */ -/* - * DATA (RW) - * - * security key data - */ -#define BKEY_KEY_DATA_DATA_MASK (0xFFFFFFFFUL) -#define BKEY_KEY_DATA_DATA_SHIFT (0U) -#define BKEY_KEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_KEY_DATA_DATA_SHIFT) & BKEY_KEY_DATA_DATA_MASK) -#define BKEY_KEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_KEY_DATA_DATA_MASK) >> BKEY_KEY_DATA_DATA_SHIFT) - -/* Bitfield definition for register array: ECC */ -/* - * WLOCK (RW) - * - * write lock to key0 - * 0: write enable - * 1: write ignored - */ -#define BKEY_ECC_WLOCK_MASK (0x80000000UL) -#define BKEY_ECC_WLOCK_SHIFT (31U) -#define BKEY_ECC_WLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_WLOCK_SHIFT) & BKEY_ECC_WLOCK_MASK) -#define BKEY_ECC_WLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_WLOCK_MASK) >> BKEY_ECC_WLOCK_SHIFT) - -/* - * RLOCK (RW) - * - * read lock to key0 - * 0: key read enable - * 1: key always read as 0 - */ -#define BKEY_ECC_RLOCK_MASK (0x40000000UL) -#define BKEY_ECC_RLOCK_SHIFT (30U) -#define BKEY_ECC_RLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_RLOCK_SHIFT) & BKEY_ECC_RLOCK_MASK) -#define BKEY_ECC_RLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_RLOCK_MASK) >> BKEY_ECC_RLOCK_SHIFT) - -/* - * ECC (RW) - * - * Parity check bits for key0 - */ -#define BKEY_ECC_ECC_MASK (0xFFFFU) -#define BKEY_ECC_ECC_SHIFT (0U) -#define BKEY_ECC_ECC_SET(x) (((uint32_t)(x) << BKEY_ECC_ECC_SHIFT) & BKEY_ECC_ECC_MASK) -#define BKEY_ECC_ECC_GET(x) (((uint32_t)(x) & BKEY_ECC_ECC_MASK) >> BKEY_ECC_ECC_SHIFT) - -/* Bitfield definition for register: SELECT */ -/* - * SELECT (RW) - * - * select key, key0 treated as secure key, in non-scure mode, only key1 can be selected - * 0: select key0 in secure mode, key1 in non-secure mode - * 1: select key1 in secure or nonsecure mode - */ -#define BKEY_SELECT_SELECT_MASK (0x1U) -#define BKEY_SELECT_SELECT_SHIFT (0U) -#define BKEY_SELECT_SELECT_SET(x) (((uint32_t)(x) << BKEY_SELECT_SELECT_SHIFT) & BKEY_SELECT_SELECT_MASK) -#define BKEY_SELECT_SELECT_GET(x) (((uint32_t)(x) & BKEY_SELECT_SELECT_MASK) >> BKEY_SELECT_SELECT_SHIFT) - - - -/* DATA register group index macro definition */ -#define BKEY_KEY_DATA_0 (0UL) -#define BKEY_KEY_DATA_1 (1UL) -#define BKEY_KEY_DATA_2 (2UL) -#define BKEY_KEY_DATA_3 (3UL) -#define BKEY_KEY_DATA_4 (4UL) -#define BKEY_KEY_DATA_5 (5UL) -#define BKEY_KEY_DATA_6 (6UL) -#define BKEY_KEY_DATA_7 (7UL) - -/* KEY register group index macro definition */ -#define BKEY_KEY_0 (0UL) -#define BKEY_KEY_1 (1UL) - -/* ECC register group index macro definition */ -#define BKEY_ECC_KEY0 (0UL) -#define BKEY_ECC_KEY1 (1UL) - - -#endif /* HPM_BKEY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bmon_regs.h deleted file mode 100644 index f297a1dbb93..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bmon_regs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BMON_H -#define HPM_BMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - } MONITOR[2]; -} BMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define BMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define BMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define BMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ACTIVE_SHIFT) & BMON_MONITOR_CONTROL_ACTIVE_MASK) -#define BMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ACTIVE_MASK) >> BMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define BMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define BMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define BMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ENABLE_SHIFT) & BMON_MONITOR_CONTROL_ENABLE_MASK) -#define BMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ENABLE_MASK) >> BMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define BMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define BMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define BMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << BMON_MONITOR_STATUS_FLAG_SHIFT) & BMON_MONITOR_STATUS_FLAG_MASK) -#define BMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & BMON_MONITOR_STATUS_FLAG_MASK) >> BMON_MONITOR_STATUS_FLAG_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define BMON_MONITOR_GLITCH0 (0UL) -#define BMON_MONITOR_CLOCK0 (1UL) - - -#endif /* HPM_BMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bpor_regs.h deleted file mode 100644 index 4f48a15578d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bpor_regs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BPOR_H -#define HPM_BPOR_H - -typedef struct { - __RW uint32_t POR_CAUSE; /* 0x0: Power on cause */ - __RW uint32_t POR_SELECT; /* 0x4: Power on select */ - __RW uint32_t POR_CONFIG; /* 0x8: Power on reset config */ - __RW uint32_t POR_CONTROL; /* 0xC: Power down control */ -} BPOR_Type; - - -/* Bitfield definition for register: POR_CAUSE */ -/* - * CAUSE (RW) - * - * Power on cause, each bit represnts one cause, write 1 to clear each bit - * bit0: wakeup button - * bit1: security violation - * bit2: RTC alarm 0 - * bit3: RTC alarm 1 - * bit4: GPIO - */ -#define BPOR_POR_CAUSE_CAUSE_MASK (0x1FU) -#define BPOR_POR_CAUSE_CAUSE_SHIFT (0U) -#define BPOR_POR_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << BPOR_POR_CAUSE_CAUSE_SHIFT) & BPOR_POR_CAUSE_CAUSE_MASK) -#define BPOR_POR_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & BPOR_POR_CAUSE_CAUSE_MASK) >> BPOR_POR_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: POR_SELECT */ -/* - * SELECT (RW) - * - * Power on cause select, each bit represnts one cause, value 1 enables corresponding cause - * bit0: wakeup button - * bit1: security violation - * bit2: RTC alarm 0 - * bit3: RTC alarm 1 - * bit4: GPIO - */ -#define BPOR_POR_SELECT_SELECT_MASK (0x1FU) -#define BPOR_POR_SELECT_SELECT_SHIFT (0U) -#define BPOR_POR_SELECT_SELECT_SET(x) (((uint32_t)(x) << BPOR_POR_SELECT_SELECT_SHIFT) & BPOR_POR_SELECT_SELECT_MASK) -#define BPOR_POR_SELECT_SELECT_GET(x) (((uint32_t)(x) & BPOR_POR_SELECT_SELECT_MASK) >> BPOR_POR_SELECT_SELECT_SHIFT) - -/* Bitfield definition for register: POR_CONFIG */ -/* - * RETENTION (RW) - * - * retention battery domain setting - * 0: battery reset on reset pin reset happen - * 1: battery domain retention when reset pin reset happen - */ -#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) -#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) -#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) -#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) - -/* Bitfield definition for register: POR_CONTROL */ -/* - * COUNTER (RW) - * - * Chip power down counter, counter decreasing if value is not 0, power down of chip happens on counter value is 1 - */ -#define BPOR_POR_CONTROL_COUNTER_MASK (0xFFFFU) -#define BPOR_POR_CONTROL_COUNTER_SHIFT (0U) -#define BPOR_POR_CONTROL_COUNTER_SET(x) (((uint32_t)(x) << BPOR_POR_CONTROL_COUNTER_SHIFT) & BPOR_POR_CONTROL_COUNTER_MASK) -#define BPOR_POR_CONTROL_COUNTER_GET(x) (((uint32_t)(x) & BPOR_POR_CONTROL_COUNTER_MASK) >> BPOR_POR_CONTROL_COUNTER_SHIFT) - - - - -#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bsec_regs.h deleted file mode 100644 index 6167b47be78..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_bsec_regs.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BSEC_H -#define HPM_BSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ -} BSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * BATT_FAIL (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U) -#define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U) -#define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK) -#define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT) - -/* - * BATT_NSC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U) -#define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U) -#define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK) -#define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT) - -/* - * BATT_SEC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U) -#define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U) -#define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK) -#define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT) - -/* - * BATT_INS (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U) -#define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U) -#define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK) -#define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define BSEC_EVENT_EVENT_SHIFT (16U) -#define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT) - -/* - * BATT_ESC_NSC (RO) - * - * BATT is escalating non-secure event - */ -#define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U) -#define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U) -#define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT) - -/* - * BATT_ESC_SEC (RO) - * - * BATT is escalting ssecure event - */ -#define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U) -#define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U) -#define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT) - - - - -#endif /* HPM_BSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_butn_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_butn_regs.h deleted file mode 100644 index 03d711e0c58..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_butn_regs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BUTN_H -#define HPM_BUTN_H - -typedef struct { - __RW uint32_t BTN_STATUS; /* 0x0: Button status */ - __RW uint32_t BTN_IRQ_MASK; /* 0x4: Button interrupt mask */ - __RW uint32_t LED_INTENSE; /* 0x8: Debounce setting */ -} BUTN_Type; - - -/* Bitfield definition for register: BTN_STATUS */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_STATUS_XWCLICK_SHIFT (28U) -#define BUTN_BTN_STATUS_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XWCLICK_SHIFT) & BUTN_BTN_STATUS_XWCLICK_MASK) -#define BUTN_BTN_STATUS_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XWCLICK_MASK) >> BUTN_BTN_STATUS_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_STATUS_WCLICK_SHIFT (24U) -#define BUTN_BTN_STATUS_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WCLICK_SHIFT) & BUTN_BTN_STATUS_WCLICK_MASK) -#define BUTN_BTN_STATUS_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WCLICK_MASK) >> BUTN_BTN_STATUS_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_STATUS_XPCLICK_SHIFT (20U) -#define BUTN_BTN_STATUS_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XPCLICK_SHIFT) & BUTN_BTN_STATUS_XPCLICK_MASK) -#define BUTN_BTN_STATUS_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XPCLICK_MASK) >> BUTN_BTN_STATUS_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_STATUS_PCLICK_SHIFT (16U) -#define BUTN_BTN_STATUS_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PCLICK_SHIFT) & BUTN_BTN_STATUS_PCLICK_MASK) -#define BUTN_BTN_STATUS_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PCLICK_MASK) >> BUTN_BTN_STATUS_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_DBTN_MASK (0xF00U) -#define BUTN_BTN_STATUS_DBTN_SHIFT (8U) -#define BUTN_BTN_STATUS_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_DBTN_SHIFT) & BUTN_BTN_STATUS_DBTN_MASK) -#define BUTN_BTN_STATUS_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_DBTN_MASK) >> BUTN_BTN_STATUS_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_WBTN_MASK (0xF0U) -#define BUTN_BTN_STATUS_WBTN_SHIFT (4U) -#define BUTN_BTN_STATUS_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WBTN_SHIFT) & BUTN_BTN_STATUS_WBTN_MASK) -#define BUTN_BTN_STATUS_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WBTN_MASK) >> BUTN_BTN_STATUS_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_PBTN_MASK (0xFU) -#define BUTN_BTN_STATUS_PBTN_SHIFT (0U) -#define BUTN_BTN_STATUS_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PBTN_SHIFT) & BUTN_BTN_STATUS_PBTN_MASK) -#define BUTN_BTN_STATUS_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PBTN_MASK) >> BUTN_BTN_STATUS_PBTN_SHIFT) - -/* Bitfield definition for register: BTN_IRQ_MASK */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT (28U) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_IRQ_MASK_WCLICK_SHIFT (24U) -#define BUTN_BTN_IRQ_MASK_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) >> BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT (20U) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_IRQ_MASK_PCLICK_SHIFT (16U) -#define BUTN_BTN_IRQ_MASK_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) >> BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_DBTN_MASK (0xF00U) -#define BUTN_BTN_IRQ_MASK_DBTN_SHIFT (8U) -#define BUTN_BTN_IRQ_MASK_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_DBTN_SHIFT) & BUTN_BTN_IRQ_MASK_DBTN_MASK) -#define BUTN_BTN_IRQ_MASK_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_DBTN_MASK) >> BUTN_BTN_IRQ_MASK_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_WBTN_MASK (0xF0U) -#define BUTN_BTN_IRQ_MASK_WBTN_SHIFT (4U) -#define BUTN_BTN_IRQ_MASK_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WBTN_SHIFT) & BUTN_BTN_IRQ_MASK_WBTN_MASK) -#define BUTN_BTN_IRQ_MASK_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WBTN_MASK) >> BUTN_BTN_IRQ_MASK_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_PBTN_MASK (0xFU) -#define BUTN_BTN_IRQ_MASK_PBTN_SHIFT (0U) -#define BUTN_BTN_IRQ_MASK_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PBTN_SHIFT) & BUTN_BTN_IRQ_MASK_PBTN_MASK) -#define BUTN_BTN_IRQ_MASK_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PBTN_MASK) >> BUTN_BTN_IRQ_MASK_PBTN_SHIFT) - -/* Bitfield definition for register: LED_INTENSE */ -/* - * RLED (RW) - * - * Rbutton brightness 0 - */ -#define BUTN_LED_INTENSE_RLED_MASK (0xF0000UL) -#define BUTN_LED_INTENSE_RLED_SHIFT (16U) -#define BUTN_LED_INTENSE_RLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_RLED_SHIFT) & BUTN_LED_INTENSE_RLED_MASK) -#define BUTN_LED_INTENSE_RLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_RLED_MASK) >> BUTN_LED_INTENSE_RLED_SHIFT) - -/* - * PLED (RW) - * - * Pbutton brightness 0 - */ -#define BUTN_LED_INTENSE_PLED_MASK (0xFU) -#define BUTN_LED_INTENSE_PLED_SHIFT (0U) -#define BUTN_LED_INTENSE_PLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_PLED_SHIFT) & BUTN_LED_INTENSE_PLED_MASK) -#define BUTN_LED_INTENSE_PLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_PLED_MASK) >> BUTN_LED_INTENSE_PLED_SHIFT) - - - - -#endif /* HPM_BUTN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_cam_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_cam_regs.h deleted file mode 100644 index 59c638312ef..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_cam_regs.h +++ /dev/null @@ -1,1004 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CAM_H -#define HPM_CAM_H - -typedef struct { - __RW uint32_t CR1; /* 0x0: Control Register */ - __RW uint32_t INT_EN; /* 0x4: Interrupt Enable Register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t CR2; /* 0x10: Control 2 Register */ - __R uint8_t RESERVED1[16]; /* 0x14 - 0x23: Reserved */ - __RW uint32_t STA; /* 0x24: Status Register */ - __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ - __RW uint32_t DMASA_FB1; /* 0x30: Pixel DMA Frame Buffer 1 Address */ - __RW uint32_t DMASA_FB2; /* 0x34: Pixel DMA Frame Buffer 2 Address */ - __RW uint32_t BUF_PARA; /* 0x38: Buffer Parameters Register */ - __RW uint32_t IDEAL_WN_SIZE; /* 0x3C: Ideal Image Size Register */ - __R uint8_t RESERVED3[12]; /* 0x40 - 0x4B: Reserved */ - __RW uint32_t CR18; /* 0x4C: Control CR18 Register */ - __RW uint32_t DMASA_UV1; /* 0x50: Pixel UV DMA Frame Buffer 1 Address */ - __RW uint32_t DMASA_UV2; /* 0x54: Pixel UV DMA Frame Buffer 2 Address */ - __RW uint32_t CR20; /* 0x58: Control CR20 Register */ - __R uint8_t RESERVED4[20]; /* 0x5C - 0x6F: Reserved */ - __RW uint32_t CSC_COEF0; /* 0x70: Color Space Conversion Config Register 0 */ - __RW uint32_t CSC_COEF1; /* 0x74: Color Space Conversion Config Register 1 */ - __RW uint32_t CSC_COEF2; /* 0x78: Color Space Conversion Config Register 2 */ - __RW uint32_t CLRKEY_LOW; /* 0x7C: Low Color Key Register */ - __RW uint32_t CLRKEY_HIGH; /* 0x80: High Color Key Register */ - __R uint8_t RESERVED5[12]; /* 0x84 - 0x8F: Reserved */ - __R uint32_t HISTOGRAM_FIFO[256]; /* 0x90 - 0x48C: Histogram Registers */ -} CAM_Type; - - -/* Bitfield definition for register: CR1 */ -/* - * COLOR_EXT (RW) - * - * If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. - * The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - */ -#define CAM_CR1_COLOR_EXT_MASK (0x20000000UL) -#define CAM_CR1_COLOR_EXT_SHIFT (29U) -#define CAM_CR1_COLOR_EXT_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_EXT_SHIFT) & CAM_CR1_COLOR_EXT_MASK) -#define CAM_CR1_COLOR_EXT_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_EXT_MASK) >> CAM_CR1_COLOR_EXT_SHIFT) - -/* - * INV_PIXCLK (RW) - * - * invert pixclk pad input before it is used - */ -#define CAM_CR1_INV_PIXCLK_MASK (0x10000000UL) -#define CAM_CR1_INV_PIXCLK_SHIFT (28U) -#define CAM_CR1_INV_PIXCLK_SET(x) (((uint32_t)(x) << CAM_CR1_INV_PIXCLK_SHIFT) & CAM_CR1_INV_PIXCLK_MASK) -#define CAM_CR1_INV_PIXCLK_GET(x) (((uint32_t)(x) & CAM_CR1_INV_PIXCLK_MASK) >> CAM_CR1_INV_PIXCLK_SHIFT) - -/* - * INV_HSYNC (RW) - * - * invert hsync pad input before it is used - */ -#define CAM_CR1_INV_HSYNC_MASK (0x8000000UL) -#define CAM_CR1_INV_HSYNC_SHIFT (27U) -#define CAM_CR1_INV_HSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_HSYNC_SHIFT) & CAM_CR1_INV_HSYNC_MASK) -#define CAM_CR1_INV_HSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_HSYNC_MASK) >> CAM_CR1_INV_HSYNC_SHIFT) - -/* - * INV_VSYNC (RW) - * - * invert vsync pad input before it is used - */ -#define CAM_CR1_INV_VSYNC_MASK (0x4000000UL) -#define CAM_CR1_INV_VSYNC_SHIFT (26U) -#define CAM_CR1_INV_VSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_VSYNC_SHIFT) & CAM_CR1_INV_VSYNC_MASK) -#define CAM_CR1_INV_VSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_VSYNC_MASK) >> CAM_CR1_INV_VSYNC_SHIFT) - -/* - * SWAP16_EN (RW) - * - * SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. - * NOTE: Example of swapping enabled: - * Data input to FIFO = 0x11223344 - * Data in RX FIFO = 0x 33441122 - * NOTE: Example of swapping disabled: - * Data input to FIFO = 0x11223344 - * Data in RX FIFO = 0x11223344 - * 0 Disable swapping - * 1 Enable swapping - */ -#define CAM_CR1_SWAP16_EN_MASK (0x2000000UL) -#define CAM_CR1_SWAP16_EN_SHIFT (25U) -#define CAM_CR1_SWAP16_EN_SET(x) (((uint32_t)(x) << CAM_CR1_SWAP16_EN_SHIFT) & CAM_CR1_SWAP16_EN_MASK) -#define CAM_CR1_SWAP16_EN_GET(x) (((uint32_t)(x) & CAM_CR1_SWAP16_EN_MASK) >> CAM_CR1_SWAP16_EN_SHIFT) - -/* - * PACK_DIR (RW) - * - * Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. - * 0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. - * 1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - */ -#define CAM_CR1_PACK_DIR_MASK (0x1000000UL) -#define CAM_CR1_PACK_DIR_SHIFT (24U) -#define CAM_CR1_PACK_DIR_SET(x) (((uint32_t)(x) << CAM_CR1_PACK_DIR_SHIFT) & CAM_CR1_PACK_DIR_MASK) -#define CAM_CR1_PACK_DIR_GET(x) (((uint32_t)(x) & CAM_CR1_PACK_DIR_MASK) >> CAM_CR1_PACK_DIR_SHIFT) - -/* - * RESTART_BUSPTR (RW) - * - * force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - */ -#define CAM_CR1_RESTART_BUSPTR_MASK (0x800000UL) -#define CAM_CR1_RESTART_BUSPTR_SHIFT (23U) -#define CAM_CR1_RESTART_BUSPTR_SET(x) (((uint32_t)(x) << CAM_CR1_RESTART_BUSPTR_SHIFT) & CAM_CR1_RESTART_BUSPTR_MASK) -#define CAM_CR1_RESTART_BUSPTR_GET(x) (((uint32_t)(x) & CAM_CR1_RESTART_BUSPTR_MASK) >> CAM_CR1_RESTART_BUSPTR_SHIFT) - -/* - * ASYNC_RXFIFO_CLR (RW) - * - * ASynchronous Rx FIFO Clear. - * When asserted, this bit clears RXFIFO immediately. - * It will be auto-cleared. - */ -#define CAM_CR1_ASYNC_RXFIFO_CLR_MASK (0x100000UL) -#define CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT (20U) -#define CAM_CR1_ASYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) -#define CAM_CR1_ASYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) >> CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) - -/* - * SYNC_RXFIFO_CLR (RW) - * - * Synchronous Rx FIFO Clear. - * When asserted, this bit clears RXFIFO on every SOF. - */ -#define CAM_CR1_SYNC_RXFIFO_CLR_MASK (0x80000UL) -#define CAM_CR1_SYNC_RXFIFO_CLR_SHIFT (19U) -#define CAM_CR1_SYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) -#define CAM_CR1_SYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) >> CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) - -/* - * SOF_INT_POL (RW) - * - * SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. - * 0 SOF interrupt is generated on SOF falling edge - * 1 SOF interrupt is generated on SOF rising edge - */ -#define CAM_CR1_SOF_INT_POL_MASK (0x20000UL) -#define CAM_CR1_SOF_INT_POL_SHIFT (17U) -#define CAM_CR1_SOF_INT_POL_SET(x) (((uint32_t)(x) << CAM_CR1_SOF_INT_POL_SHIFT) & CAM_CR1_SOF_INT_POL_MASK) -#define CAM_CR1_SOF_INT_POL_GET(x) (((uint32_t)(x) & CAM_CR1_SOF_INT_POL_MASK) >> CAM_CR1_SOF_INT_POL_SHIFT) - -/* - * INV_DATA (RW) - * - * Invert Data Input. This bit enables or disables internal inverters on the data lines. - * 0 CAM_D data lines are directly applied to internal circuitry - * 1 CAM_D data lines are inverted before applied to internal circuitry - */ -#define CAM_CR1_INV_DATA_MASK (0x8000U) -#define CAM_CR1_INV_DATA_SHIFT (15U) -#define CAM_CR1_INV_DATA_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DATA_SHIFT) & CAM_CR1_INV_DATA_MASK) -#define CAM_CR1_INV_DATA_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DATA_MASK) >> CAM_CR1_INV_DATA_SHIFT) - -/* - * STORAGE_MODE (RW) - * - * 00: Normal Mode (one plane mode) - * 01: Two Plane Mode (Y, UV plane) - * 10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 - * 11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - */ -#define CAM_CR1_STORAGE_MODE_MASK (0xC00U) -#define CAM_CR1_STORAGE_MODE_SHIFT (10U) -#define CAM_CR1_STORAGE_MODE_SET(x) (((uint32_t)(x) << CAM_CR1_STORAGE_MODE_SHIFT) & CAM_CR1_STORAGE_MODE_MASK) -#define CAM_CR1_STORAGE_MODE_GET(x) (((uint32_t)(x) & CAM_CR1_STORAGE_MODE_MASK) >> CAM_CR1_STORAGE_MODE_SHIFT) - -/* - * COLOR_FORMATS (RW) - * - * input color formats: - * 0010b:24bit:RGB888 - * 0011b:24bit:RGB666 - * 0100b:16bit:RGB565 - * 0101b:16bit:RGB444 - * 0110b:16bit:RGB555 - * 0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) - * YUV - * YCrCb - * Note: YUV420 is not supported. - * 1000b: 24bit: YUV444 - */ -#define CAM_CR1_COLOR_FORMATS_MASK (0x78U) -#define CAM_CR1_COLOR_FORMATS_SHIFT (3U) -#define CAM_CR1_COLOR_FORMATS_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_FORMATS_SHIFT) & CAM_CR1_COLOR_FORMATS_MASK) -#define CAM_CR1_COLOR_FORMATS_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_FORMATS_MASK) >> CAM_CR1_COLOR_FORMATS_SHIFT) - -/* - * SENSOR_BIT_WIDTH (RW) - * - * the bit width of the sensor - * 0: 8 bits - * 1: 10 bits - * 3:24bits - * Others: Undefined - */ -#define CAM_CR1_SENSOR_BIT_WIDTH_MASK (0x7U) -#define CAM_CR1_SENSOR_BIT_WIDTH_SHIFT (0U) -#define CAM_CR1_SENSOR_BIT_WIDTH_SET(x) (((uint32_t)(x) << CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) -#define CAM_CR1_SENSOR_BIT_WIDTH_GET(x) (((uint32_t)(x) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) >> CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * ERR_CL_BWID_CFG_INT_EN (RW) - * - * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - */ -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK (0x2000U) -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT (13U) -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) >> CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) - -/* - * HIST_DONE_INT_EN (RW) - * - * Enable hist done int - */ -#define CAM_INT_EN_HIST_DONE_INT_EN_MASK (0x1000U) -#define CAM_INT_EN_HIST_DONE_INT_EN_SHIFT (12U) -#define CAM_INT_EN_HIST_DONE_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) -#define CAM_INT_EN_HIST_DONE_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) >> CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) - -/* - * HRESP_ERR_EN (RW) - * - * Hresponse Error Enable. This bit enables the hresponse error interrupt. - * 0 Disable hresponse error interrupt - * 1 Enable hresponse error interrupt - */ -#define CAM_INT_EN_HRESP_ERR_EN_MASK (0x800U) -#define CAM_INT_EN_HRESP_ERR_EN_SHIFT (11U) -#define CAM_INT_EN_HRESP_ERR_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HRESP_ERR_EN_SHIFT) & CAM_INT_EN_HRESP_ERR_EN_MASK) -#define CAM_INT_EN_HRESP_ERR_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HRESP_ERR_EN_MASK) >> CAM_INT_EN_HRESP_ERR_EN_SHIFT) - -/* - * EOF_INT_EN (RW) - * - * End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. - * 0 EOF interrupt is disabled. - * 1 EOF interrupt is generated when RX count value is reached. - */ -#define CAM_INT_EN_EOF_INT_EN_MASK (0x200U) -#define CAM_INT_EN_EOF_INT_EN_SHIFT (9U) -#define CAM_INT_EN_EOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_EOF_INT_EN_SHIFT) & CAM_INT_EN_EOF_INT_EN_MASK) -#define CAM_INT_EN_EOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_EOF_INT_EN_MASK) >> CAM_INT_EN_EOF_INT_EN_SHIFT) - -/* - * RF_OR_INTEN (RW) - * - * RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. - * 0 RxFIFO overrun interrupt is disabled - * 1 RxFIFO overrun interrupt is enabled - */ -#define CAM_INT_EN_RF_OR_INTEN_MASK (0x40U) -#define CAM_INT_EN_RF_OR_INTEN_SHIFT (6U) -#define CAM_INT_EN_RF_OR_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_RF_OR_INTEN_SHIFT) & CAM_INT_EN_RF_OR_INTEN_MASK) -#define CAM_INT_EN_RF_OR_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_RF_OR_INTEN_MASK) >> CAM_INT_EN_RF_OR_INTEN_SHIFT) - -/* - * FB2_DMA_DONE_INTEN (RW) - * - * Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA - * transfer done. - * 0 Frame Buffer2 DMA Transfer Done interrupt disable - * 1 Frame Buffer2 DMA Transfer Done interrupt enable - */ -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK (0x8U) -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT (3U) -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) - -/* - * FB1_DMA_DONE_INTEN (RW) - * - * Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA - * transfer done. - * 0 Frame Buffer1 DMA Transfer Done interrupt disable - * 1 Frame Buffer1 DMA Transfer Done interrupt enable - */ -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK (0x4U) -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT (2U) -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) - -/* - * SOF_INT_EN (RW) - * - * Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. - * 0 SOF interrupt disable - * 1 SOF interrupt enable - */ -#define CAM_INT_EN_SOF_INT_EN_MASK (0x1U) -#define CAM_INT_EN_SOF_INT_EN_SHIFT (0U) -#define CAM_INT_EN_SOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_SOF_INT_EN_SHIFT) & CAM_INT_EN_SOF_INT_EN_MASK) -#define CAM_INT_EN_SOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_SOF_INT_EN_MASK) >> CAM_INT_EN_SOF_INT_EN_SHIFT) - -/* Bitfield definition for register: CR2 */ -/* - * FRMCNT_15_0 (RO) - * - * Frame Counter. This is a 16-bit Frame Counter - * (Wraps around automatically after reaching the maximum) - */ -#define CAM_CR2_FRMCNT_15_0_MASK (0xFFFF0000UL) -#define CAM_CR2_FRMCNT_15_0_SHIFT (16U) -#define CAM_CR2_FRMCNT_15_0_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_15_0_MASK) >> CAM_CR2_FRMCNT_15_0_SHIFT) - -/* - * FRMCNT_RST (RW) - * - * Frame Count Reset. Resets the Frame Counter. - * 0 Do not reset - * 1 Reset frame counter immediately - */ -#define CAM_CR2_FRMCNT_RST_MASK (0x8000U) -#define CAM_CR2_FRMCNT_RST_SHIFT (15U) -#define CAM_CR2_FRMCNT_RST_SET(x) (((uint32_t)(x) << CAM_CR2_FRMCNT_RST_SHIFT) & CAM_CR2_FRMCNT_RST_MASK) -#define CAM_CR2_FRMCNT_RST_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_RST_MASK) >> CAM_CR2_FRMCNT_RST_SHIFT) - -/* - * RXFF_LEVEL (RW) - * - * RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. - * 000 4 Double words - * 001 8 Double words - * 010 16 Double words - * 011 24 Double words - * 100 32 Double words - * 101 48 Double words - * 110 64 Double words - * 111 96 Double words - */ -#define CAM_CR2_RXFF_LEVEL_MASK (0xE00U) -#define CAM_CR2_RXFF_LEVEL_SHIFT (9U) -#define CAM_CR2_RXFF_LEVEL_SET(x) (((uint32_t)(x) << CAM_CR2_RXFF_LEVEL_SHIFT) & CAM_CR2_RXFF_LEVEL_MASK) -#define CAM_CR2_RXFF_LEVEL_GET(x) (((uint32_t)(x) & CAM_CR2_RXFF_LEVEL_MASK) >> CAM_CR2_RXFF_LEVEL_SHIFT) - -/* - * DMA_REQ_EN_RFF (RW) - * - * DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. - * 0 Disable the dma request - * 1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - */ -#define CAM_CR2_DMA_REQ_EN_RFF_MASK (0x20U) -#define CAM_CR2_DMA_REQ_EN_RFF_SHIFT (5U) -#define CAM_CR2_DMA_REQ_EN_RFF_SET(x) (((uint32_t)(x) << CAM_CR2_DMA_REQ_EN_RFF_SHIFT) & CAM_CR2_DMA_REQ_EN_RFF_MASK) -#define CAM_CR2_DMA_REQ_EN_RFF_GET(x) (((uint32_t)(x) & CAM_CR2_DMA_REQ_EN_RFF_MASK) >> CAM_CR2_DMA_REQ_EN_RFF_SHIFT) - -/* - * CLRBITFORMAT (RW) - * - * Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - */ -#define CAM_CR2_CLRBITFORMAT_MASK (0xFU) -#define CAM_CR2_CLRBITFORMAT_SHIFT (0U) -#define CAM_CR2_CLRBITFORMAT_SET(x) (((uint32_t)(x) << CAM_CR2_CLRBITFORMAT_SHIFT) & CAM_CR2_CLRBITFORMAT_MASK) -#define CAM_CR2_CLRBITFORMAT_GET(x) (((uint32_t)(x) & CAM_CR2_CLRBITFORMAT_MASK) >> CAM_CR2_CLRBITFORMAT_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * ERR_CL_BWID_CFG (W1C) - * - * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - */ -#define CAM_STA_ERR_CL_BWID_CFG_MASK (0x80000UL) -#define CAM_STA_ERR_CL_BWID_CFG_SHIFT (19U) -#define CAM_STA_ERR_CL_BWID_CFG_SET(x) (((uint32_t)(x) << CAM_STA_ERR_CL_BWID_CFG_SHIFT) & CAM_STA_ERR_CL_BWID_CFG_MASK) -#define CAM_STA_ERR_CL_BWID_CFG_GET(x) (((uint32_t)(x) & CAM_STA_ERR_CL_BWID_CFG_MASK) >> CAM_STA_ERR_CL_BWID_CFG_SHIFT) - -/* - * HIST_DONE (W1C) - * - * hist cal done - */ -#define CAM_STA_HIST_DONE_MASK (0x40000UL) -#define CAM_STA_HIST_DONE_SHIFT (18U) -#define CAM_STA_HIST_DONE_SET(x) (((uint32_t)(x) << CAM_STA_HIST_DONE_SHIFT) & CAM_STA_HIST_DONE_MASK) -#define CAM_STA_HIST_DONE_GET(x) (((uint32_t)(x) & CAM_STA_HIST_DONE_MASK) >> CAM_STA_HIST_DONE_SHIFT) - -/* - * RF_OR_INT (W1C) - * - * RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing - * 1) - * 0 RXFIFO has not overflowed. - * 1 RXFIFO has overflowed. - */ -#define CAM_STA_RF_OR_INT_MASK (0x2000U) -#define CAM_STA_RF_OR_INT_SHIFT (13U) -#define CAM_STA_RF_OR_INT_SET(x) (((uint32_t)(x) << CAM_STA_RF_OR_INT_SHIFT) & CAM_STA_RF_OR_INT_MASK) -#define CAM_STA_RF_OR_INT_GET(x) (((uint32_t)(x) & CAM_STA_RF_OR_INT_MASK) >> CAM_STA_RF_OR_INT_SHIFT) - -/* - * DMA_TSF_DONE_FB2 (W1C) - * - * DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) - * 0 DMA transfer is not completed. - * 1 DMA transfer is completed. - */ -#define CAM_STA_DMA_TSF_DONE_FB2_MASK (0x400U) -#define CAM_STA_DMA_TSF_DONE_FB2_SHIFT (10U) -#define CAM_STA_DMA_TSF_DONE_FB2_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB2_SHIFT) & CAM_STA_DMA_TSF_DONE_FB2_MASK) -#define CAM_STA_DMA_TSF_DONE_FB2_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB2_MASK) >> CAM_STA_DMA_TSF_DONE_FB2_SHIFT) - -/* - * DMA_TSF_DONE_FB1 (W1C) - * - * DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) - * 0 DMA transfer is not completed. - * 1 DMA transfer is completed. - */ -#define CAM_STA_DMA_TSF_DONE_FB1_MASK (0x200U) -#define CAM_STA_DMA_TSF_DONE_FB1_SHIFT (9U) -#define CAM_STA_DMA_TSF_DONE_FB1_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB1_SHIFT) & CAM_STA_DMA_TSF_DONE_FB1_MASK) -#define CAM_STA_DMA_TSF_DONE_FB1_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB1_MASK) >> CAM_STA_DMA_TSF_DONE_FB1_SHIFT) - -/* - * EOF_INT (W1C) - * - * End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) - * 0 EOF is not detected. - * 1 EOF is detected. - */ -#define CAM_STA_EOF_INT_MASK (0x80U) -#define CAM_STA_EOF_INT_SHIFT (7U) -#define CAM_STA_EOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_EOF_INT_SHIFT) & CAM_STA_EOF_INT_MASK) -#define CAM_STA_EOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_EOF_INT_MASK) >> CAM_STA_EOF_INT_SHIFT) - -/* - * SOF_INT (W1C) - * - * Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) - * 0 SOF is not detected. - * 1 SOF is detected. - */ -#define CAM_STA_SOF_INT_MASK (0x40U) -#define CAM_STA_SOF_INT_SHIFT (6U) -#define CAM_STA_SOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_SOF_INT_SHIFT) & CAM_STA_SOF_INT_MASK) -#define CAM_STA_SOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_SOF_INT_MASK) >> CAM_STA_SOF_INT_SHIFT) - -/* - * HRESP_ERR_INT (W1C) - * - * Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing - * 1) - * 0 No hresponse error. - * 1 Hresponse error is detected. - */ -#define CAM_STA_HRESP_ERR_INT_MASK (0x4U) -#define CAM_STA_HRESP_ERR_INT_SHIFT (2U) -#define CAM_STA_HRESP_ERR_INT_SET(x) (((uint32_t)(x) << CAM_STA_HRESP_ERR_INT_SHIFT) & CAM_STA_HRESP_ERR_INT_MASK) -#define CAM_STA_HRESP_ERR_INT_GET(x) (((uint32_t)(x) & CAM_STA_HRESP_ERR_INT_MASK) >> CAM_STA_HRESP_ERR_INT_SHIFT) - -/* Bitfield definition for register: DMASA_FB1 */ -/* - * PTR (RW) - * - * DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. - * In Two-Plane Mode, Y buffer1 - */ -#define CAM_DMASA_FB1_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_FB1_PTR_SHIFT (2U) -#define CAM_DMASA_FB1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB1_PTR_SHIFT) & CAM_DMASA_FB1_PTR_MASK) -#define CAM_DMASA_FB1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB1_PTR_MASK) >> CAM_DMASA_FB1_PTR_SHIFT) - -/* Bitfield definition for register: DMASA_FB2 */ -/* - * PTR (RW) - * - * DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. - * In Two-Plane Mode, Y buffer2 - */ -#define CAM_DMASA_FB2_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_FB2_PTR_SHIFT (2U) -#define CAM_DMASA_FB2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB2_PTR_SHIFT) & CAM_DMASA_FB2_PTR_MASK) -#define CAM_DMASA_FB2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB2_PTR_MASK) >> CAM_DMASA_FB2_PTR_SHIFT) - -/* Bitfield definition for register: BUF_PARA */ -/* - * LINEBSP_STRIDE (RW) - * - * Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. - * The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - */ -#define CAM_BUF_PARA_LINEBSP_STRIDE_MASK (0xFFFFU) -#define CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT (0U) -#define CAM_BUF_PARA_LINEBSP_STRIDE_SET(x) (((uint32_t)(x) << CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) -#define CAM_BUF_PARA_LINEBSP_STRIDE_GET(x) (((uint32_t)(x) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) >> CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) - -/* Bitfield definition for register: IDEAL_WN_SIZE */ -/* - * HEIGHT (RW) - * - * Image Height. Indicates how many active pixels in a column of the image from the sensor. - */ -#define CAM_IDEAL_WN_SIZE_HEIGHT_MASK (0xFFFF0000UL) -#define CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT (16U) -#define CAM_IDEAL_WN_SIZE_HEIGHT_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) -#define CAM_IDEAL_WN_SIZE_HEIGHT_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) >> CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) - -/* - * WIDTH (RW) - * - * Image Width. Indicates how many active pixels in a line of the image from the sensor. - * The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. - * As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - */ -#define CAM_IDEAL_WN_SIZE_WIDTH_MASK (0xFFFFU) -#define CAM_IDEAL_WN_SIZE_WIDTH_SHIFT (0U) -#define CAM_IDEAL_WN_SIZE_WIDTH_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) -#define CAM_IDEAL_WN_SIZE_WIDTH_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) >> CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) - -/* Bitfield definition for register: CR18 */ -/* - * CAM_ENABLE (RW) - * - * CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - */ -#define CAM_CR18_CAM_ENABLE_MASK (0x80000000UL) -#define CAM_CR18_CAM_ENABLE_SHIFT (31U) -#define CAM_CR18_CAM_ENABLE_SET(x) (((uint32_t)(x) << CAM_CR18_CAM_ENABLE_SHIFT) & CAM_CR18_CAM_ENABLE_MASK) -#define CAM_CR18_CAM_ENABLE_GET(x) (((uint32_t)(x) & CAM_CR18_CAM_ENABLE_MASK) >> CAM_CR18_CAM_ENABLE_SHIFT) - -/* - * AWQOS (RW) - * - * AWQOS for bus fabric arbitration - */ -#define CAM_CR18_AWQOS_MASK (0x780U) -#define CAM_CR18_AWQOS_SHIFT (7U) -#define CAM_CR18_AWQOS_SET(x) (((uint32_t)(x) << CAM_CR18_AWQOS_SHIFT) & CAM_CR18_AWQOS_MASK) -#define CAM_CR18_AWQOS_GET(x) (((uint32_t)(x) & CAM_CR18_AWQOS_MASK) >> CAM_CR18_AWQOS_SHIFT) - -/* Bitfield definition for register: DMASA_UV1 */ -/* - * PTR (RW) - * - * Two Plane UV Buffer Start Address 1 - */ -#define CAM_DMASA_UV1_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_UV1_PTR_SHIFT (2U) -#define CAM_DMASA_UV1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV1_PTR_SHIFT) & CAM_DMASA_UV1_PTR_MASK) -#define CAM_DMASA_UV1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV1_PTR_MASK) >> CAM_DMASA_UV1_PTR_SHIFT) - -/* Bitfield definition for register: DMASA_UV2 */ -/* - * PTR (RW) - * - * Two Plane UV Buffer Start Address 2 - */ -#define CAM_DMASA_UV2_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_UV2_PTR_SHIFT (2U) -#define CAM_DMASA_UV2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV2_PTR_SHIFT) & CAM_DMASA_UV2_PTR_MASK) -#define CAM_DMASA_UV2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV2_PTR_MASK) >> CAM_DMASA_UV2_PTR_SHIFT) - -/* Bitfield definition for register: CR20 */ -/* - * BINARY_EN (RW) - * - * binary picture output enable - */ -#define CAM_CR20_BINARY_EN_MASK (0x80000000UL) -#define CAM_CR20_BINARY_EN_SHIFT (31U) -#define CAM_CR20_BINARY_EN_SET(x) (((uint32_t)(x) << CAM_CR20_BINARY_EN_SHIFT) & CAM_CR20_BINARY_EN_MASK) -#define CAM_CR20_BINARY_EN_GET(x) (((uint32_t)(x) & CAM_CR20_BINARY_EN_MASK) >> CAM_CR20_BINARY_EN_SHIFT) - -/* - * HISTOGRAM_EN (RW) - * - * histogarm enable - */ -#define CAM_CR20_HISTOGRAM_EN_MASK (0x40000000UL) -#define CAM_CR20_HISTOGRAM_EN_SHIFT (30U) -#define CAM_CR20_HISTOGRAM_EN_SET(x) (((uint32_t)(x) << CAM_CR20_HISTOGRAM_EN_SHIFT) & CAM_CR20_HISTOGRAM_EN_MASK) -#define CAM_CR20_HISTOGRAM_EN_GET(x) (((uint32_t)(x) & CAM_CR20_HISTOGRAM_EN_MASK) >> CAM_CR20_HISTOGRAM_EN_SHIFT) - -/* - * BIG_END (RW) - * - * Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - */ -#define CAM_CR20_BIG_END_MASK (0x100U) -#define CAM_CR20_BIG_END_SHIFT (8U) -#define CAM_CR20_BIG_END_SET(x) (((uint32_t)(x) << CAM_CR20_BIG_END_SHIFT) & CAM_CR20_BIG_END_MASK) -#define CAM_CR20_BIG_END_GET(x) (((uint32_t)(x) & CAM_CR20_BIG_END_MASK) >> CAM_CR20_BIG_END_SHIFT) - -/* - * THRESHOLD (RW) - * - * Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - */ -#define CAM_CR20_THRESHOLD_MASK (0xFFU) -#define CAM_CR20_THRESHOLD_SHIFT (0U) -#define CAM_CR20_THRESHOLD_SET(x) (((uint32_t)(x) << CAM_CR20_THRESHOLD_SHIFT) & CAM_CR20_THRESHOLD_MASK) -#define CAM_CR20_THRESHOLD_GET(x) (((uint32_t)(x) & CAM_CR20_THRESHOLD_MASK) >> CAM_CR20_THRESHOLD_SHIFT) - -/* Bitfield definition for register: CSC_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * This bit changes the behavior when performing U/V converting. - * 0b - Converting YUV to RGB data - * 1b - Converting YCbCr to RGB data - */ -#define CAM_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define CAM_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -#define CAM_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_YCBCR_MODE_SHIFT) & CAM_CSC_COEF0_YCBCR_MODE_MASK) -#define CAM_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_YCBCR_MODE_MASK) >> CAM_CSC_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Enable the CSC unit - * 0b - The CSC is bypassed and the input pixels are RGB data already - * 1b - The CSC is enabled and the pixels will be converted to RGB data - */ -#define CAM_CSC_COEF0_ENABLE_MASK (0x40000000UL) -#define CAM_CSC_COEF0_ENABLE_SHIFT (30U) -#define CAM_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_ENABLE_SHIFT) & CAM_CSC_COEF0_ENABLE_MASK) -#define CAM_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_ENABLE_MASK) >> CAM_CSC_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define CAM_CSC_COEF0_C0_MASK (0x1FFC0000UL) -#define CAM_CSC_COEF0_C0_SHIFT (18U) -#define CAM_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_C0_SHIFT) & CAM_CSC_COEF0_C0_MASK) -#define CAM_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_C0_MASK) >> CAM_CSC_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define CAM_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define CAM_CSC_COEF0_UV_OFFSET_SHIFT (9U) -#define CAM_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_UV_OFFSET_SHIFT) & CAM_CSC_COEF0_UV_OFFSET_MASK) -#define CAM_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_UV_OFFSET_MASK) >> CAM_CSC_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define CAM_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) -#define CAM_CSC_COEF0_Y_OFFSET_SHIFT (0U) -#define CAM_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_Y_OFFSET_SHIFT) & CAM_CSC_COEF0_Y_OFFSET_MASK) -#define CAM_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_Y_OFFSET_MASK) >> CAM_CSC_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: CSC_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define CAM_CSC_COEF1_C1_MASK (0x7FF0000UL) -#define CAM_CSC_COEF1_C1_SHIFT (16U) -#define CAM_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C1_SHIFT) & CAM_CSC_COEF1_C1_MASK) -#define CAM_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C1_MASK) >> CAM_CSC_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define CAM_CSC_COEF1_C4_MASK (0x7FFU) -#define CAM_CSC_COEF1_C4_SHIFT (0U) -#define CAM_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C4_SHIFT) & CAM_CSC_COEF1_C4_MASK) -#define CAM_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C4_MASK) >> CAM_CSC_COEF1_C4_SHIFT) - -/* Bitfield definition for register: CSC_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define CAM_CSC_COEF2_C2_MASK (0x7FF0000UL) -#define CAM_CSC_COEF2_C2_SHIFT (16U) -#define CAM_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C2_SHIFT) & CAM_CSC_COEF2_C2_MASK) -#define CAM_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C2_MASK) >> CAM_CSC_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define CAM_CSC_COEF2_C3_MASK (0x7FFU) -#define CAM_CSC_COEF2_C3_SHIFT (0U) -#define CAM_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C3_SHIFT) & CAM_CSC_COEF2_C3_MASK) -#define CAM_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C3_MASK) >> CAM_CSC_COEF2_C3_SHIFT) - -/* Bitfield definition for register: CLRKEY_LOW */ -/* - * LIMIT (RW) - * - * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - */ -#define CAM_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) -#define CAM_CLRKEY_LOW_LIMIT_SHIFT (0U) -#define CAM_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_LOW_LIMIT_SHIFT) & CAM_CLRKEY_LOW_LIMIT_MASK) -#define CAM_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_LOW_LIMIT_MASK) >> CAM_CLRKEY_LOW_LIMIT_SHIFT) - -/* Bitfield definition for register: CLRKEY_HIGH */ -/* - * LIMIT (RW) - * - * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - */ -#define CAM_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) -#define CAM_CLRKEY_HIGH_LIMIT_SHIFT (0U) -#define CAM_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_HIGH_LIMIT_SHIFT) & CAM_CLRKEY_HIGH_LIMIT_MASK) -#define CAM_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_HIGH_LIMIT_MASK) >> CAM_CLRKEY_HIGH_LIMIT_SHIFT) - -/* Bitfield definition for register array: HISTOGRAM_FIFO */ -/* - * HIST_Y (RO) - * - * the appearance of bin x (x=(address-DATA0)/4) - */ -#define CAM_HISTOGRAM_FIFO_HIST_Y_MASK (0xFFFFFFUL) -#define CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT (0U) -#define CAM_HISTOGRAM_FIFO_HIST_Y_GET(x) (((uint32_t)(x) & CAM_HISTOGRAM_FIFO_HIST_Y_MASK) >> CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT) - - - -/* HISTOGRAM_FIFO register group index macro definition */ -#define CAM_HISTOGRAM_FIFO_DATA0 (0UL) -#define CAM_HISTOGRAM_FIFO_DATA1 (1UL) -#define CAM_HISTOGRAM_FIFO_DATA2 (2UL) -#define CAM_HISTOGRAM_FIFO_DATA3 (3UL) -#define CAM_HISTOGRAM_FIFO_DATA4 (4UL) -#define CAM_HISTOGRAM_FIFO_DATA5 (5UL) -#define CAM_HISTOGRAM_FIFO_DATA6 (6UL) -#define CAM_HISTOGRAM_FIFO_DATA7 (7UL) -#define CAM_HISTOGRAM_FIFO_DATA8 (8UL) -#define CAM_HISTOGRAM_FIFO_DATA9 (9UL) -#define CAM_HISTOGRAM_FIFO_DATA10 (10UL) -#define CAM_HISTOGRAM_FIFO_DATA11 (11UL) -#define CAM_HISTOGRAM_FIFO_DATA12 (12UL) -#define CAM_HISTOGRAM_FIFO_DATA13 (13UL) -#define CAM_HISTOGRAM_FIFO_DATA14 (14UL) -#define CAM_HISTOGRAM_FIFO_DATA15 (15UL) -#define CAM_HISTOGRAM_FIFO_DATA16 (16UL) -#define CAM_HISTOGRAM_FIFO_DATA17 (17UL) -#define CAM_HISTOGRAM_FIFO_DATA18 (18UL) -#define CAM_HISTOGRAM_FIFO_DATA19 (19UL) -#define CAM_HISTOGRAM_FIFO_DATA20 (20UL) -#define CAM_HISTOGRAM_FIFO_DATA21 (21UL) -#define CAM_HISTOGRAM_FIFO_DATA22 (22UL) -#define CAM_HISTOGRAM_FIFO_DATA23 (23UL) -#define CAM_HISTOGRAM_FIFO_DATA24 (24UL) -#define CAM_HISTOGRAM_FIFO_DATA25 (25UL) -#define CAM_HISTOGRAM_FIFO_DATA26 (26UL) -#define CAM_HISTOGRAM_FIFO_DATA27 (27UL) -#define CAM_HISTOGRAM_FIFO_DATA28 (28UL) -#define CAM_HISTOGRAM_FIFO_DATA29 (29UL) -#define CAM_HISTOGRAM_FIFO_DATA30 (30UL) -#define CAM_HISTOGRAM_FIFO_DATA31 (31UL) -#define CAM_HISTOGRAM_FIFO_DATA32 (32UL) -#define CAM_HISTOGRAM_FIFO_DATA33 (33UL) -#define CAM_HISTOGRAM_FIFO_DATA34 (34UL) -#define CAM_HISTOGRAM_FIFO_DATA35 (35UL) -#define CAM_HISTOGRAM_FIFO_DATA36 (36UL) -#define CAM_HISTOGRAM_FIFO_DATA37 (37UL) -#define CAM_HISTOGRAM_FIFO_DATA38 (38UL) -#define CAM_HISTOGRAM_FIFO_DATA39 (39UL) -#define CAM_HISTOGRAM_FIFO_DATA40 (40UL) -#define CAM_HISTOGRAM_FIFO_DATA41 (41UL) -#define CAM_HISTOGRAM_FIFO_DATA42 (42UL) -#define CAM_HISTOGRAM_FIFO_DATA43 (43UL) -#define CAM_HISTOGRAM_FIFO_DATA44 (44UL) -#define CAM_HISTOGRAM_FIFO_DATA45 (45UL) -#define CAM_HISTOGRAM_FIFO_DATA46 (46UL) -#define CAM_HISTOGRAM_FIFO_DATA47 (47UL) -#define CAM_HISTOGRAM_FIFO_DATA48 (48UL) -#define CAM_HISTOGRAM_FIFO_DATA49 (49UL) -#define CAM_HISTOGRAM_FIFO_DATA50 (50UL) -#define CAM_HISTOGRAM_FIFO_DATA51 (51UL) -#define CAM_HISTOGRAM_FIFO_DATA52 (52UL) -#define CAM_HISTOGRAM_FIFO_DATA53 (53UL) -#define CAM_HISTOGRAM_FIFO_DATA54 (54UL) -#define CAM_HISTOGRAM_FIFO_DATA55 (55UL) -#define CAM_HISTOGRAM_FIFO_DATA56 (56UL) -#define CAM_HISTOGRAM_FIFO_DATA57 (57UL) -#define CAM_HISTOGRAM_FIFO_DATA58 (58UL) -#define CAM_HISTOGRAM_FIFO_DATA59 (59UL) -#define CAM_HISTOGRAM_FIFO_DATA60 (60UL) -#define CAM_HISTOGRAM_FIFO_DATA61 (61UL) -#define CAM_HISTOGRAM_FIFO_DATA62 (62UL) -#define CAM_HISTOGRAM_FIFO_DATA63 (63UL) -#define CAM_HISTOGRAM_FIFO_DATA64 (64UL) -#define CAM_HISTOGRAM_FIFO_DATA65 (65UL) -#define CAM_HISTOGRAM_FIFO_DATA66 (66UL) -#define CAM_HISTOGRAM_FIFO_DATA67 (67UL) -#define CAM_HISTOGRAM_FIFO_DATA68 (68UL) -#define CAM_HISTOGRAM_FIFO_DATA69 (69UL) -#define CAM_HISTOGRAM_FIFO_DATA70 (70UL) -#define CAM_HISTOGRAM_FIFO_DATA71 (71UL) -#define CAM_HISTOGRAM_FIFO_DATA72 (72UL) -#define CAM_HISTOGRAM_FIFO_DATA73 (73UL) -#define CAM_HISTOGRAM_FIFO_DATA74 (74UL) -#define CAM_HISTOGRAM_FIFO_DATA75 (75UL) -#define CAM_HISTOGRAM_FIFO_DATA76 (76UL) -#define CAM_HISTOGRAM_FIFO_DATA77 (77UL) -#define CAM_HISTOGRAM_FIFO_DATA78 (78UL) -#define CAM_HISTOGRAM_FIFO_DATA79 (79UL) -#define CAM_HISTOGRAM_FIFO_DATA80 (80UL) -#define CAM_HISTOGRAM_FIFO_DATA81 (81UL) -#define CAM_HISTOGRAM_FIFO_DATA82 (82UL) -#define CAM_HISTOGRAM_FIFO_DATA83 (83UL) -#define CAM_HISTOGRAM_FIFO_DATA84 (84UL) -#define CAM_HISTOGRAM_FIFO_DATA85 (85UL) -#define CAM_HISTOGRAM_FIFO_DATA86 (86UL) -#define CAM_HISTOGRAM_FIFO_DATA87 (87UL) -#define CAM_HISTOGRAM_FIFO_DATA88 (88UL) -#define CAM_HISTOGRAM_FIFO_DATA89 (89UL) -#define CAM_HISTOGRAM_FIFO_DATA90 (90UL) -#define CAM_HISTOGRAM_FIFO_DATA91 (91UL) -#define CAM_HISTOGRAM_FIFO_DATA92 (92UL) -#define CAM_HISTOGRAM_FIFO_DATA93 (93UL) -#define CAM_HISTOGRAM_FIFO_DATA94 (94UL) -#define CAM_HISTOGRAM_FIFO_DATA95 (95UL) -#define CAM_HISTOGRAM_FIFO_DATA96 (96UL) -#define CAM_HISTOGRAM_FIFO_DATA97 (97UL) -#define CAM_HISTOGRAM_FIFO_DATA98 (98UL) -#define CAM_HISTOGRAM_FIFO_DATA99 (99UL) -#define CAM_HISTOGRAM_FIFO_DATA100 (100UL) -#define CAM_HISTOGRAM_FIFO_DATA101 (101UL) -#define CAM_HISTOGRAM_FIFO_DATA102 (102UL) -#define CAM_HISTOGRAM_FIFO_DATA103 (103UL) -#define CAM_HISTOGRAM_FIFO_DATA104 (104UL) -#define CAM_HISTOGRAM_FIFO_DATA105 (105UL) -#define CAM_HISTOGRAM_FIFO_DATA106 (106UL) -#define CAM_HISTOGRAM_FIFO_DATA107 (107UL) -#define CAM_HISTOGRAM_FIFO_DATA108 (108UL) -#define CAM_HISTOGRAM_FIFO_DATA109 (109UL) -#define CAM_HISTOGRAM_FIFO_DATA110 (110UL) -#define CAM_HISTOGRAM_FIFO_DATA111 (111UL) -#define CAM_HISTOGRAM_FIFO_DATA112 (112UL) -#define CAM_HISTOGRAM_FIFO_DATA113 (113UL) -#define CAM_HISTOGRAM_FIFO_DATA114 (114UL) -#define CAM_HISTOGRAM_FIFO_DATA115 (115UL) -#define CAM_HISTOGRAM_FIFO_DATA116 (116UL) -#define CAM_HISTOGRAM_FIFO_DATA117 (117UL) -#define CAM_HISTOGRAM_FIFO_DATA118 (118UL) -#define CAM_HISTOGRAM_FIFO_DATA119 (119UL) -#define CAM_HISTOGRAM_FIFO_DATA120 (120UL) -#define CAM_HISTOGRAM_FIFO_DATA121 (121UL) -#define CAM_HISTOGRAM_FIFO_DATA122 (122UL) -#define CAM_HISTOGRAM_FIFO_DATA123 (123UL) -#define CAM_HISTOGRAM_FIFO_DATA124 (124UL) -#define CAM_HISTOGRAM_FIFO_DATA125 (125UL) -#define CAM_HISTOGRAM_FIFO_DATA126 (126UL) -#define CAM_HISTOGRAM_FIFO_DATA127 (127UL) -#define CAM_HISTOGRAM_FIFO_DATA128 (128UL) -#define CAM_HISTOGRAM_FIFO_DATA129 (129UL) -#define CAM_HISTOGRAM_FIFO_DATA130 (130UL) -#define CAM_HISTOGRAM_FIFO_DATA131 (131UL) -#define CAM_HISTOGRAM_FIFO_DATA132 (132UL) -#define CAM_HISTOGRAM_FIFO_DATA133 (133UL) -#define CAM_HISTOGRAM_FIFO_DATA134 (134UL) -#define CAM_HISTOGRAM_FIFO_DATA135 (135UL) -#define CAM_HISTOGRAM_FIFO_DATA136 (136UL) -#define CAM_HISTOGRAM_FIFO_DATA137 (137UL) -#define CAM_HISTOGRAM_FIFO_DATA138 (138UL) -#define CAM_HISTOGRAM_FIFO_DATA139 (139UL) -#define CAM_HISTOGRAM_FIFO_DATA140 (140UL) -#define CAM_HISTOGRAM_FIFO_DATA141 (141UL) -#define CAM_HISTOGRAM_FIFO_DATA142 (142UL) -#define CAM_HISTOGRAM_FIFO_DATA143 (143UL) -#define CAM_HISTOGRAM_FIFO_DATA144 (144UL) -#define CAM_HISTOGRAM_FIFO_DATA145 (145UL) -#define CAM_HISTOGRAM_FIFO_DATA146 (146UL) -#define CAM_HISTOGRAM_FIFO_DATA147 (147UL) -#define CAM_HISTOGRAM_FIFO_DATA148 (148UL) -#define CAM_HISTOGRAM_FIFO_DATA149 (149UL) -#define CAM_HISTOGRAM_FIFO_DATA150 (150UL) -#define CAM_HISTOGRAM_FIFO_DATA151 (151UL) -#define CAM_HISTOGRAM_FIFO_DATA152 (152UL) -#define CAM_HISTOGRAM_FIFO_DATA153 (153UL) -#define CAM_HISTOGRAM_FIFO_DATA154 (154UL) -#define CAM_HISTOGRAM_FIFO_DATA155 (155UL) -#define CAM_HISTOGRAM_FIFO_DATA156 (156UL) -#define CAM_HISTOGRAM_FIFO_DATA157 (157UL) -#define CAM_HISTOGRAM_FIFO_DATA158 (158UL) -#define CAM_HISTOGRAM_FIFO_DATA159 (159UL) -#define CAM_HISTOGRAM_FIFO_DATA160 (160UL) -#define CAM_HISTOGRAM_FIFO_DATA161 (161UL) -#define CAM_HISTOGRAM_FIFO_DATA162 (162UL) -#define CAM_HISTOGRAM_FIFO_DATA163 (163UL) -#define CAM_HISTOGRAM_FIFO_DATA164 (164UL) -#define CAM_HISTOGRAM_FIFO_DATA165 (165UL) -#define CAM_HISTOGRAM_FIFO_DATA166 (166UL) -#define CAM_HISTOGRAM_FIFO_DATA167 (167UL) -#define CAM_HISTOGRAM_FIFO_DATA168 (168UL) -#define CAM_HISTOGRAM_FIFO_DATA169 (169UL) -#define CAM_HISTOGRAM_FIFO_DATA170 (170UL) -#define CAM_HISTOGRAM_FIFO_DATA171 (171UL) -#define CAM_HISTOGRAM_FIFO_DATA172 (172UL) -#define CAM_HISTOGRAM_FIFO_DATA173 (173UL) -#define CAM_HISTOGRAM_FIFO_DATA174 (174UL) -#define CAM_HISTOGRAM_FIFO_DATA175 (175UL) -#define CAM_HISTOGRAM_FIFO_DATA176 (176UL) -#define CAM_HISTOGRAM_FIFO_DATA177 (177UL) -#define CAM_HISTOGRAM_FIFO_DATA178 (178UL) -#define CAM_HISTOGRAM_FIFO_DATA179 (179UL) -#define CAM_HISTOGRAM_FIFO_DATA180 (180UL) -#define CAM_HISTOGRAM_FIFO_DATA181 (181UL) -#define CAM_HISTOGRAM_FIFO_DATA182 (182UL) -#define CAM_HISTOGRAM_FIFO_DATA183 (183UL) -#define CAM_HISTOGRAM_FIFO_DATA184 (184UL) -#define CAM_HISTOGRAM_FIFO_DATA185 (185UL) -#define CAM_HISTOGRAM_FIFO_DATA186 (186UL) -#define CAM_HISTOGRAM_FIFO_DATA187 (187UL) -#define CAM_HISTOGRAM_FIFO_DATA188 (188UL) -#define CAM_HISTOGRAM_FIFO_DATA189 (189UL) -#define CAM_HISTOGRAM_FIFO_DATA190 (190UL) -#define CAM_HISTOGRAM_FIFO_DATA191 (191UL) -#define CAM_HISTOGRAM_FIFO_DATA192 (192UL) -#define CAM_HISTOGRAM_FIFO_DATA193 (193UL) -#define CAM_HISTOGRAM_FIFO_DATA194 (194UL) -#define CAM_HISTOGRAM_FIFO_DATA195 (195UL) -#define CAM_HISTOGRAM_FIFO_DATA196 (196UL) -#define CAM_HISTOGRAM_FIFO_DATA197 (197UL) -#define CAM_HISTOGRAM_FIFO_DATA198 (198UL) -#define CAM_HISTOGRAM_FIFO_DATA199 (199UL) -#define CAM_HISTOGRAM_FIFO_DATA200 (200UL) -#define CAM_HISTOGRAM_FIFO_DATA201 (201UL) -#define CAM_HISTOGRAM_FIFO_DATA202 (202UL) -#define CAM_HISTOGRAM_FIFO_DATA203 (203UL) -#define CAM_HISTOGRAM_FIFO_DATA204 (204UL) -#define CAM_HISTOGRAM_FIFO_DATA205 (205UL) -#define CAM_HISTOGRAM_FIFO_DATA206 (206UL) -#define CAM_HISTOGRAM_FIFO_DATA207 (207UL) -#define CAM_HISTOGRAM_FIFO_DATA208 (208UL) -#define CAM_HISTOGRAM_FIFO_DATA209 (209UL) -#define CAM_HISTOGRAM_FIFO_DATA210 (210UL) -#define CAM_HISTOGRAM_FIFO_DATA211 (211UL) -#define CAM_HISTOGRAM_FIFO_DATA212 (212UL) -#define CAM_HISTOGRAM_FIFO_DATA213 (213UL) -#define CAM_HISTOGRAM_FIFO_DATA214 (214UL) -#define CAM_HISTOGRAM_FIFO_DATA215 (215UL) -#define CAM_HISTOGRAM_FIFO_DATA216 (216UL) -#define CAM_HISTOGRAM_FIFO_DATA217 (217UL) -#define CAM_HISTOGRAM_FIFO_DATA218 (218UL) -#define CAM_HISTOGRAM_FIFO_DATA219 (219UL) -#define CAM_HISTOGRAM_FIFO_DATA220 (220UL) -#define CAM_HISTOGRAM_FIFO_DATA221 (221UL) -#define CAM_HISTOGRAM_FIFO_DATA222 (222UL) -#define CAM_HISTOGRAM_FIFO_DATA223 (223UL) -#define CAM_HISTOGRAM_FIFO_DATA224 (224UL) -#define CAM_HISTOGRAM_FIFO_DATA225 (225UL) -#define CAM_HISTOGRAM_FIFO_DATA226 (226UL) -#define CAM_HISTOGRAM_FIFO_DATA227 (227UL) -#define CAM_HISTOGRAM_FIFO_DATA228 (228UL) -#define CAM_HISTOGRAM_FIFO_DATA229 (229UL) -#define CAM_HISTOGRAM_FIFO_DATA230 (230UL) -#define CAM_HISTOGRAM_FIFO_DATA231 (231UL) -#define CAM_HISTOGRAM_FIFO_DATA232 (232UL) -#define CAM_HISTOGRAM_FIFO_DATA233 (233UL) -#define CAM_HISTOGRAM_FIFO_DATA234 (234UL) -#define CAM_HISTOGRAM_FIFO_DATA235 (235UL) -#define CAM_HISTOGRAM_FIFO_DATA236 (236UL) -#define CAM_HISTOGRAM_FIFO_DATA237 (237UL) -#define CAM_HISTOGRAM_FIFO_DATA238 (238UL) -#define CAM_HISTOGRAM_FIFO_DATA239 (239UL) -#define CAM_HISTOGRAM_FIFO_DATA240 (240UL) -#define CAM_HISTOGRAM_FIFO_DATA241 (241UL) -#define CAM_HISTOGRAM_FIFO_DATA242 (242UL) -#define CAM_HISTOGRAM_FIFO_DATA243 (243UL) -#define CAM_HISTOGRAM_FIFO_DATA244 (244UL) -#define CAM_HISTOGRAM_FIFO_DATA245 (245UL) -#define CAM_HISTOGRAM_FIFO_DATA246 (246UL) -#define CAM_HISTOGRAM_FIFO_DATA247 (247UL) -#define CAM_HISTOGRAM_FIFO_DATA248 (248UL) -#define CAM_HISTOGRAM_FIFO_DATA249 (249UL) -#define CAM_HISTOGRAM_FIFO_DATA250 (250UL) -#define CAM_HISTOGRAM_FIFO_DATA251 (251UL) -#define CAM_HISTOGRAM_FIFO_DATA252 (252UL) -#define CAM_HISTOGRAM_FIFO_DATA253 (253UL) -#define CAM_HISTOGRAM_FIFO_DATA254 (254UL) -#define CAM_HISTOGRAM_FIFO_DATA255 (255UL) - - -#endif /* HPM_CAM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_can_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_can_regs.h deleted file mode 100644 index 5da84c9ef71..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_can_regs.h +++ /dev/null @@ -1,1402 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CAN_H -#define HPM_CAN_H - -typedef struct { - __RW uint32_t RBUF[20]; /* 0x0 - 0x4C: receive buffer registers and reception time stamp */ - __RW uint32_t TBUF[18]; /* 0x50 - 0x94: transmit buffer register */ - __R uint32_t TTS[2]; /* 0x98 - 0x9C: transmission time stamp, LSB 32bit */ - __RW uint32_t CMD_STA_CMD_CTRL; /* 0xA0: config, status, command and control bits */ - __RW uint8_t RTIE; /* 0xA4: Receive and Transmit Interrupt Enable Register RTIE */ - __W uint8_t RTIF; /* 0xA5: Receive and Transmit Interrupt Flag Register RTIF (0xa5) */ - __RW uint8_t ERRINT; /* 0xA6: ERRor INTerrupt Enable and Flag Register ERRINT */ - __RW uint8_t LIMIT; /* 0xA7: Warning Limits Register LIMIT */ - __RW uint32_t S_PRESC; /* 0xA8: Bit Timing Register(Slow Speed) */ - __RW uint32_t F_PRESC; /* 0xAC: Bit Timing Register(Fast Speed) */ - __R uint8_t EALCAP; /* 0xB0: Error and Arbitration Lost Capture Register EALCAP */ - __RW uint8_t TDC; /* 0xB1: Transmitter Delay Compensation Register TDC */ - __R uint8_t RECNT; /* 0xB2: Error Counter Registers RECNT */ - __R uint8_t TECNT; /* 0xB3: Error Counter Registers TECNT */ - __RW uint8_t ACFCTRL; /* 0xB4: Acceptance Filter Control Register ACFCTRL */ - __RW uint8_t TIMECFG; /* 0xB5: CiA 603 Time-Stamping TIMECFG */ - __RW uint16_t ACF_EN; /* 0xB6: Acceptance Filter Enable ACF_EN */ - __RW uint32_t ACF; /* 0xB8: Acceptance CODE ACODE or ACMASK */ - __RW uint16_t VER; /* 0xBC: Version Information VER */ - __RW uint8_t TBSLOT; /* 0xBE: TTCAN: TB Slot Pointer TBSLOT */ - __RW uint8_t TTCFG; /* 0xBF: TTCAN: Time Trigger Configuration TTCFG */ - __RW uint32_t REF_MSG; /* 0xC0: TTCAN: Reference Message REF_MSG */ - __RW uint16_t TRIG_CFG; /* 0xC4: TTCAN: Trigger Configuration TRIG_CFG */ - __RW uint16_t TT_TRIG; /* 0xC6: TTCAN: Trigger Time TT_TRIG */ - __RW uint16_t TT_WTRIG; /* 0xC8: TTCAN: Watch Trigger Time TT_WTRIG */ -} CAN_Type; - - -/* Bitfield definition for register array: RBUF */ -/* - * RBUF (RW) - * - * receive buffer - */ -#define CAN_RBUF_RBUF_MASK (0xFFFFFFFFUL) -#define CAN_RBUF_RBUF_SHIFT (0U) -#define CAN_RBUF_RBUF_SET(x) (((uint32_t)(x) << CAN_RBUF_RBUF_SHIFT) & CAN_RBUF_RBUF_MASK) -#define CAN_RBUF_RBUF_GET(x) (((uint32_t)(x) & CAN_RBUF_RBUF_MASK) >> CAN_RBUF_RBUF_SHIFT) - -/* Bitfield definition for register array: TBUF */ -/* - * TBUF (RW) - * - * transmit buffer - */ -#define CAN_TBUF_TBUF_MASK (0xFFFFFFFFUL) -#define CAN_TBUF_TBUF_SHIFT (0U) -#define CAN_TBUF_TBUF_SET(x) (((uint32_t)(x) << CAN_TBUF_TBUF_SHIFT) & CAN_TBUF_TBUF_MASK) -#define CAN_TBUF_TBUF_GET(x) (((uint32_t)(x) & CAN_TBUF_TBUF_MASK) >> CAN_TBUF_TBUF_SHIFT) - -/* Bitfield definition for register array: TTS */ -/* - * TTS_WRD0 (RO) - * - * transmission time stamp, word 0, LSB 32bit - */ -#define CAN_TTS_TTS_WRD0_MASK (0xFFFFFFFFUL) -#define CAN_TTS_TTS_WRD0_SHIFT (0U) -#define CAN_TTS_TTS_WRD0_GET(x) (((uint32_t)(x) & CAN_TTS_TTS_WRD0_MASK) >> CAN_TTS_TTS_WRD0_SHIFT) - -/* Bitfield definition for register: CMD_STA_CMD_CTRL */ -/* - * SACK (RW) - * - * Self-ACKnowledge - * 0 – no self-ACK - * 1 – self-ACK when LBME=1 - */ -#define CAN_CMD_STA_CMD_CTRL_SACK_MASK (0x80000000UL) -#define CAN_CMD_STA_CMD_CTRL_SACK_SHIFT (31U) -#define CAN_CMD_STA_CMD_CTRL_SACK_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) -#define CAN_CMD_STA_CMD_CTRL_SACK_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_SACK_MASK) >> CAN_CMD_STA_CMD_CTRL_SACK_SHIFT) - -/* - * ROM (RW) - * - * Receive buffer Overflow Mode - * In case of a full RBUF when a new message is received, then ROM selects the following: - * 1 – The new message will not be stored. - * 0 – The oldest message will be overwritten. - */ -#define CAN_CMD_STA_CMD_CTRL_ROM_MASK (0x40000000UL) -#define CAN_CMD_STA_CMD_CTRL_ROM_SHIFT (30U) -#define CAN_CMD_STA_CMD_CTRL_ROM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) -#define CAN_CMD_STA_CMD_CTRL_ROM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROM_MASK) >> CAN_CMD_STA_CMD_CTRL_ROM_SHIFT) - -/* - * ROV (RO) - * - * Receive buffer OVerflow - * 1 – Overflow. At least one message is lost. - * 0 – No Overflow. - * ROV is cleared by setting RREL=1. - */ -#define CAN_CMD_STA_CMD_CTRL_ROV_MASK (0x20000000UL) -#define CAN_CMD_STA_CMD_CTRL_ROV_SHIFT (29U) -#define CAN_CMD_STA_CMD_CTRL_ROV_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_ROV_MASK) >> CAN_CMD_STA_CMD_CTRL_ROV_SHIFT) - -/* - * RREL (RW) - * - * Receive buffer RELease - * The host controller has read the actual RB slot and releases it. Afterwards the CAN-CTRL - * core points to the next RB slot. RSTAT gets updated. - * 1 – Release: The host has read the RB. - * 0 – No release - */ -#define CAN_CMD_STA_CMD_CTRL_RREL_MASK (0x10000000UL) -#define CAN_CMD_STA_CMD_CTRL_RREL_SHIFT (28U) -#define CAN_CMD_STA_CMD_CTRL_RREL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) -#define CAN_CMD_STA_CMD_CTRL_RREL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RREL_MASK) >> CAN_CMD_STA_CMD_CTRL_RREL_SHIFT) - -/* - * RBALL (RW) - * - * Receive Buffer stores ALL data frames - * 0 – normal operation - * 1 – RB stores correct data frames as well as data frames with error - */ -#define CAN_CMD_STA_CMD_CTRL_RBALL_MASK (0x8000000UL) -#define CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT (27U) -#define CAN_CMD_STA_CMD_CTRL_RBALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) -#define CAN_CMD_STA_CMD_CTRL_RBALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RBALL_MASK) >> CAN_CMD_STA_CMD_CTRL_RBALL_SHIFT) - -/* - * RSTAT (RO) - * - * Receive buffer STATus - * 00 - empty - * 01 - > empty and < almost full (AFWL) - * 10 -  almost full (programmable threshold by AFWL) but not full and no overflow - * 11 - full (stays set in case of overflow – for overflow signaling see ROV) - */ -#define CAN_CMD_STA_CMD_CTRL_RSTAT_MASK (0x3000000UL) -#define CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT (24U) -#define CAN_CMD_STA_CMD_CTRL_RSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_RSTAT_SHIFT) - -/* - * FD_ISO (RW) - * - * CAN FD ISO mode - * 0 - Bosch CAN FD (non-ISO) mode - * 1 - ISO CAN FD mode (ISO 11898-1:2015) - * ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count. - * Both modes are incompatible and must not be mixed in one CAN network. - * This bit has no impact to CAN 2.0B. - * This bit is only writeable if RESET=1. - */ -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK (0x800000UL) -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT (23U) -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) -#define CAN_CMD_STA_CMD_CTRL_FD_ISO_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_FD_ISO_MASK) >> CAN_CMD_STA_CMD_CTRL_FD_ISO_SHIFT) - -/* - * TSNEXT (RW) - * - * Transmit buffer Secondary NEXT - * 0 - no action - * 1 - STB slot filled, select next slot. - * After all frame bytes are written to the TBUF registers, the host controller has to set - * TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF - * registers to the next slot. Once a slot is marked as filled a transmission can be started - * using TSONE or TSALL. - * It is possible to set TSNEXT and TSONE or TSALL together in one write access. - * TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL - * core immediately after it was set. - * Setting TSNEXT is meaningless if TBSEL=0. In this case TSNEXT is ignored and - * automatically cleared. It does not do any harm. - * If all slots of the STB are filled, TSNEXT stays set until a slot becomes free. - * TSNEXT has no meaning in TTCAN mode and is fixed to 0. - */ -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK (0x400000UL) -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT (22U) -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSNEXT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSNEXT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSNEXT_SHIFT) - -/* - * TSMODE (RW) - * - * Transmit buffer Secondary operation MODE - * 0 - FIFO mode - * 1 - priority decision mode - * In FIFO mode frames are transmitted in the order in that they are written into the STB. - * In priority decision mode the frame with the highest priority in the STB is automatically - * transmitted first. The ID of a frame is used for the priority decision. A lower ID means a - * higher priority of a frame. A frame in the PTB has always the highest priority regardless of - * the ID. - * TSMODE shall be switched only if the STB if empty - */ -#define CAN_CMD_STA_CMD_CTRL_TSMODE_MASK (0x200000UL) -#define CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT (21U) -#define CAN_CMD_STA_CMD_CTRL_TSMODE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSMODE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSMODE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSMODE_SHIFT) - -/* - * TTTBM (RW) - * - * TTCAN Transmit Buffer Mode - * If TTEN=0 then TTTBM is ignored, otherwise the following is valid: - * 0 - separate PTB and STB, behavior defined by TSMODE - * 1 - full TTCAN support: buffer slots selectable by TBPTR and TTPTR - * For event-driven CAN communication (TTEN=0), the system provides PTB and STB and - * the behavior of the STB is defined by TSMODE. Then TTTBM is ignored. - * For time-triggered CAN communication (TTEN=1) with full support of all features including - * time-triggered transmissions, TTTBM=1 needs to be chosen. Then the all TB slots are - * addressable using TTPTR and TBPTR. - * For time-triggered CAN communication (TTEN=1) with only support of reception timestamps, TTTBM=0 can be chosen. Then the transmit buffer acts as in event-driven mode - * and the behavior can be selected by TSMODE. - * TTTBM shall be switched only if the TBUF is empty. - */ -#define CAN_CMD_STA_CMD_CTRL_TTTBM_MASK (0x100000UL) -#define CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT (20U) -#define CAN_CMD_STA_CMD_CTRL_TTTBM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) -#define CAN_CMD_STA_CMD_CTRL_TTTBM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TTTBM_MASK) >> CAN_CMD_STA_CMD_CTRL_TTTBM_SHIFT) - -/* - * TSSTAT (RO) - * - * Transmission Secondary STATus bits - * If TTEN=0 or TTTBM=0: - * 00 – STB is empty - * 01 – STB is less than or equal to half full - * 10 – STB is more than half full - * 11 – STB is full - * If the STB is disabled using STB_DISABLE, then TSSTAT=00. - * If TTEN=1 and TTTBM=1: - * 00 – PTB and STB are empty - * 01 – PTB and STB are not empty and not full - * 11 – PTB and STB are full - */ -#define CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK (0x30000UL) -#define CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT (16U) -#define CAN_CMD_STA_CMD_CTRL_TSSTAT_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSTAT_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSTAT_SHIFT) - -/* - * TBSEL (RW) - * - * Transmit Buffer Select - * Selects the transmit buffer to be loaded with a message. Use the TBUF registers for - * access. TBSEL needs to be stable all the time the TBUF registers are written and when - * TSNEXT is set. - * 0 - PTB (high-priority buffer) - * 1 - STB - * The bit will be reset to the hardware reset value if (TTEN=1 and TTTBM=1) - */ -#define CAN_CMD_STA_CMD_CTRL_TBSEL_MASK (0x8000U) -#define CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT (15U) -#define CAN_CMD_STA_CMD_CTRL_TBSEL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) -#define CAN_CMD_STA_CMD_CTRL_TBSEL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TBSEL_MASK) >> CAN_CMD_STA_CMD_CTRL_TBSEL_SHIFT) - -/* - * LOM (RW) - * - * Listen Only Mode - * 0 - Disabled - * 1 - Enabled - * LOM cannot be set if TPE, TSONE or TSALL is set. No transmission can be started if LOM - * is enabled and LBME is disabled. - * LOM=1 and LBME=0 disables all transmissions. - * LOM=1 and LBME=1 disables the ACK for received frames and error frames, but enables - * the transmission of own frames. - */ -#define CAN_CMD_STA_CMD_CTRL_LOM_MASK (0x4000U) -#define CAN_CMD_STA_CMD_CTRL_LOM_SHIFT (14U) -#define CAN_CMD_STA_CMD_CTRL_LOM_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) -#define CAN_CMD_STA_CMD_CTRL_LOM_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LOM_MASK) >> CAN_CMD_STA_CMD_CTRL_LOM_SHIFT) - -/* - * STBY (RW) - * - * Transceiver Standby Mode - * 0 - Disabled - * 1 - Enabled - * This register bit is connected to the output signal stby which can be used to control a - * standby mode of a transceiver. - * STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1. - * If the host sets STBY to 0 then the host needs to wait for the time required by the - * transceiver to start up before the host requests a new transmission. - */ -#define CAN_CMD_STA_CMD_CTRL_STBY_MASK (0x2000U) -#define CAN_CMD_STA_CMD_CTRL_STBY_SHIFT (13U) -#define CAN_CMD_STA_CMD_CTRL_STBY_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) -#define CAN_CMD_STA_CMD_CTRL_STBY_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_STBY_MASK) >> CAN_CMD_STA_CMD_CTRL_STBY_SHIFT) - -/* - * TPE (RW) - * - * Transmit Primary Enable - * 1 - Transmission enable for the message in the high-priority PTB - * 0 - No transmission for the PTB - * If TPE is set, the message from the PTB will be transmitted at the next possible transmit - * position. A started transmission from the STB will be completed before, but pending new - * messages are delayed until the PTB message has been transmitted. - * TPE stays set until the message has been transmitted successfully or it is aborted using - * TPA. - * The host controller can set TPE to 1 but can not reset it to 0. This would only be possible - * using TPA and aborting the message. - * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and - * LBME=0) or (TTEN=1 and TTTBM=1). - */ -#define CAN_CMD_STA_CMD_CTRL_TPE_MASK (0x1000U) -#define CAN_CMD_STA_CMD_CTRL_TPE_SHIFT (12U) -#define CAN_CMD_STA_CMD_CTRL_TPE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) -#define CAN_CMD_STA_CMD_CTRL_TPE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPE_MASK) >> CAN_CMD_STA_CMD_CTRL_TPE_SHIFT) - -/* - * TPA (RW) - * - * Transmit Primary Abort - * 1 – Aborts a transmission from PTB which has been requested by TPE=1 but not - * started yet. (The data bytes of the message remains in the PTB.) - * 0 – no abort - * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA - * automatically de-asserts TPE. - * The host controller can set TPA to 1 but can not reset it to 0. - * During the short time while the CAN-CTRL core resets the bit, it cannot be set by the - * host. - * The bit will be reset to the hardware reset value if RESET=1 or (TTEN=1 and TTTBM=1). - * TPA should not be set simultaneously with TPE. - */ -#define CAN_CMD_STA_CMD_CTRL_TPA_MASK (0x800U) -#define CAN_CMD_STA_CMD_CTRL_TPA_SHIFT (11U) -#define CAN_CMD_STA_CMD_CTRL_TPA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) -#define CAN_CMD_STA_CMD_CTRL_TPA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPA_MASK) >> CAN_CMD_STA_CMD_CTRL_TPA_SHIFT) - -/* - * TSONE (RW) - * - * Transmit Secondary ONE frame - * 1 – Transmission enable of one in the STB. In FIFO mode this is the oldest message - * and in priority mode this is the one with the highest priority. - * TSONE in priority mode is difficult to handle, because it is not always clear which - * message will be transmitted if new messages are written to the STB meanwhile. - * The controller starts the transmission as soon as the bus becomes vacant and - * no request of the PTB (bit TPE) is pending. - * 0 – No transmission for the STB. - * TSONE stays set until the message has been transmitted successfully or it is aborted - * using TSA. - * The host controller can set TSONE to 1 but can not reset it to 0. This would only be - * possible using TSA and aborting the message. - * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and - * LBME=0) or (TTEN=1 and TTTBM=1). - */ -#define CAN_CMD_STA_CMD_CTRL_TSONE_MASK (0x400U) -#define CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT (10U) -#define CAN_CMD_STA_CMD_CTRL_TSONE_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSONE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSONE_MASK) >> CAN_CMD_STA_CMD_CTRL_TSONE_SHIFT) - -/* - * TSALL (RW) - * - * Transmit Secondary ALL frames - * 1 – Transmission enable of all messages in the STB. - * The controller starts the transmission as soon as the bus becomes vacant and - * no request of the PTB (bit TPE) is pending. - * 0 – No transmission for the STB. - * TSALL stays set until all messages have been transmitted successfully or they are aborted - * using TSA. - * The host controller can set TSALL to 1 but can not reset it to 0. This would only be - * possible using TSA and aborting the messages. - * The bit will be reset to the hardware reset value if RESET=1, STBY=1, (LOM=1 and - * LBME=0) or (TTEN=1 and TTTBM=1). - * If during a transmission the STB is loaded with a new frame then the new frame will be - * transmitted too. In other words: a transmission initiated by TSALL is finished when the - * STB becomes empty. - */ -#define CAN_CMD_STA_CMD_CTRL_TSALL_MASK (0x200U) -#define CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT (9U) -#define CAN_CMD_STA_CMD_CTRL_TSALL_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSALL_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSALL_MASK) >> CAN_CMD_STA_CMD_CTRL_TSALL_SHIFT) - -/* - * TSA (RW) - * - * Transmit Secondary Abort - * 1 – Aborts a transmission from STB which has been requested but not started yet. - * For a TSONE transmission, only one frame is aborted while for a TSALL - * Transmission, all frames are aborted. - * One or all message slots will be released which updates TSSTAT. - * All aborted messages are lost because they are not accessible any more. - * If in priority mode a TSONE transmission is aborted, then it is not clear which - * frame will be aborted if new frames are written to the STB meanwhile. - * 0 – no abort - * The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,automatically de-asserts TSONE or TSALL respectively. - * The host controller can set TSA to 1 but can not reset it to 0. - * The bit will be reset to the hardware reset value if RESET=1. - * TSA should not be set simultaneously with TSONE or TSALL. - */ -#define CAN_CMD_STA_CMD_CTRL_TSA_MASK (0x100U) -#define CAN_CMD_STA_CMD_CTRL_TSA_SHIFT (8U) -#define CAN_CMD_STA_CMD_CTRL_TSA_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSA_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSA_MASK) >> CAN_CMD_STA_CMD_CTRL_TSA_SHIFT) - -/* - * RESET (RW) - * - * RESET request bit - * 1 - The host controller performs a local reset of CAN-CTRL. - * 0 - no local reset of CAN-CTRLThe some register (e.g for node configuration) can only be modified if RESET=1. - * Bit RESET forces several components to a reset state. - * RESET is automatically set if the node enters “bus off” state. - * Note that a CAN node will participate in CAN communication after RESET is switched to 0after 11 CAN bit times. - * This delay is required by the CAN standard (bus idle time).If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can beread as 0 and becomes inactive. - * The reason is clock domain crossing from host to CAN clockdomain. RESET is held active as long as needed depending on the relation between host andCAN clock. - */ -#define CAN_CMD_STA_CMD_CTRL_RESET_MASK (0x80U) -#define CAN_CMD_STA_CMD_CTRL_RESET_SHIFT (7U) -#define CAN_CMD_STA_CMD_CTRL_RESET_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) -#define CAN_CMD_STA_CMD_CTRL_RESET_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RESET_MASK) >> CAN_CMD_STA_CMD_CTRL_RESET_SHIFT) - -/* - * LBME (RW) - * - * Loop Back Mode, External - * 0 - Disabled - * 1 - EnabledLBME should not be enabled while a transmission is active - */ -#define CAN_CMD_STA_CMD_CTRL_LBME_MASK (0x40U) -#define CAN_CMD_STA_CMD_CTRL_LBME_SHIFT (6U) -#define CAN_CMD_STA_CMD_CTRL_LBME_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) -#define CAN_CMD_STA_CMD_CTRL_LBME_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBME_MASK) >> CAN_CMD_STA_CMD_CTRL_LBME_SHIFT) - -/* - * LBMI (RW) - * - * Loop Back Mode, Internal - * 0 - Disabled1 - EnabledLBMI should not be enabled while a transmission is active. - */ -#define CAN_CMD_STA_CMD_CTRL_LBMI_MASK (0x20U) -#define CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT (5U) -#define CAN_CMD_STA_CMD_CTRL_LBMI_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) -#define CAN_CMD_STA_CMD_CTRL_LBMI_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_LBMI_MASK) >> CAN_CMD_STA_CMD_CTRL_LBMI_SHIFT) - -/* - * TPSS (RW) - * - * Transmission Primary Single Shot mode for PTB - * 0 - Disabled - * 1 - Enabled - */ -#define CAN_CMD_STA_CMD_CTRL_TPSS_MASK (0x10U) -#define CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT (4U) -#define CAN_CMD_STA_CMD_CTRL_TPSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) -#define CAN_CMD_STA_CMD_CTRL_TPSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TPSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TPSS_SHIFT) - -/* - * TSSS (RW) - * - * Transmission Secondary Single Shot mode for STB - * 0 - Disabled - * 1 - Enabled - */ -#define CAN_CMD_STA_CMD_CTRL_TSSS_MASK (0x8U) -#define CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT (3U) -#define CAN_CMD_STA_CMD_CTRL_TSSS_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) -#define CAN_CMD_STA_CMD_CTRL_TSSS_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TSSS_MASK) >> CAN_CMD_STA_CMD_CTRL_TSSS_SHIFT) - -/* - * RACTIVE (RO) - * - * Reception ACTIVE (Receive Status bit) - * 1 - The controller is currently receiving a frame. - * 0 - No receive activity. - */ -#define CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK (0x4U) -#define CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT (2U) -#define CAN_CMD_STA_CMD_CTRL_RACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_RACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_RACTIVE_SHIFT) - -/* - * TACTIVE (RO) - * - * Transmission ACTIVE (Transmit Status bit) - * 1 - The controller is currently transmitting a frame. - * 0 - No transmit activity. - */ -#define CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK (0x2U) -#define CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT (1U) -#define CAN_CMD_STA_CMD_CTRL_TACTIVE_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_TACTIVE_MASK) >> CAN_CMD_STA_CMD_CTRL_TACTIVE_SHIFT) - -/* - * BUSOFF (RW) - * - * Bus Off (Bus Status bit) - * 1 - The controller status is “bus off”. - * 0 - The controller status is “bus on”. - * Writing a 1 to BUSOFF will reset TECNT and RECNT. This should be done only for debugging. - * See Chapter 3.9.10.6 for details. - */ -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK (0x1U) -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT (0U) -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_SET(x) (((uint32_t)(x) << CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) -#define CAN_CMD_STA_CMD_CTRL_BUSOFF_GET(x) (((uint32_t)(x) & CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK) >> CAN_CMD_STA_CMD_CTRL_BUSOFF_SHIFT) - -/* Bitfield definition for register: RTIE */ -/* - * RIE (RW) - * - * Receive Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_RIE_MASK (0x80U) -#define CAN_RTIE_RIE_SHIFT (7U) -#define CAN_RTIE_RIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RIE_SHIFT) & CAN_RTIE_RIE_MASK) -#define CAN_RTIE_RIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RIE_MASK) >> CAN_RTIE_RIE_SHIFT) - -/* - * ROIE (RW) - * - * RB Overrun Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_ROIE_MASK (0x40U) -#define CAN_RTIE_ROIE_SHIFT (6U) -#define CAN_RTIE_ROIE_SET(x) (((uint8_t)(x) << CAN_RTIE_ROIE_SHIFT) & CAN_RTIE_ROIE_MASK) -#define CAN_RTIE_ROIE_GET(x) (((uint8_t)(x) & CAN_RTIE_ROIE_MASK) >> CAN_RTIE_ROIE_SHIFT) - -/* - * RFIE (RW) - * - * RB Full Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_RFIE_MASK (0x20U) -#define CAN_RTIE_RFIE_SHIFT (5U) -#define CAN_RTIE_RFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RFIE_SHIFT) & CAN_RTIE_RFIE_MASK) -#define CAN_RTIE_RFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RFIE_MASK) >> CAN_RTIE_RFIE_SHIFT) - -/* - * RAFIE (RW) - * - * RB Almost Full Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_RAFIE_MASK (0x10U) -#define CAN_RTIE_RAFIE_SHIFT (4U) -#define CAN_RTIE_RAFIE_SET(x) (((uint8_t)(x) << CAN_RTIE_RAFIE_SHIFT) & CAN_RTIE_RAFIE_MASK) -#define CAN_RTIE_RAFIE_GET(x) (((uint8_t)(x) & CAN_RTIE_RAFIE_MASK) >> CAN_RTIE_RAFIE_SHIFT) - -/* - * TPIE (RW) - * - * Transmission Primary Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_TPIE_MASK (0x8U) -#define CAN_RTIE_TPIE_SHIFT (3U) -#define CAN_RTIE_TPIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TPIE_SHIFT) & CAN_RTIE_TPIE_MASK) -#define CAN_RTIE_TPIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TPIE_MASK) >> CAN_RTIE_TPIE_SHIFT) - -/* - * TSIE (RW) - * - * Transmission Secondary Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_TSIE_MASK (0x4U) -#define CAN_RTIE_TSIE_SHIFT (2U) -#define CAN_RTIE_TSIE_SET(x) (((uint8_t)(x) << CAN_RTIE_TSIE_SHIFT) & CAN_RTIE_TSIE_MASK) -#define CAN_RTIE_TSIE_GET(x) (((uint8_t)(x) & CAN_RTIE_TSIE_MASK) >> CAN_RTIE_TSIE_SHIFT) - -/* - * EIE (RW) - * - * Error Interrupt Enable - * 0 – Disabled, 1 – Enabled - */ -#define CAN_RTIE_EIE_MASK (0x2U) -#define CAN_RTIE_EIE_SHIFT (1U) -#define CAN_RTIE_EIE_SET(x) (((uint8_t)(x) << CAN_RTIE_EIE_SHIFT) & CAN_RTIE_EIE_MASK) -#define CAN_RTIE_EIE_GET(x) (((uint8_t)(x) & CAN_RTIE_EIE_MASK) >> CAN_RTIE_EIE_SHIFT) - -/* - * TSFF (RO) - * - * If TTEN=0 or TTTBM=0: Transmit Secondary buffer Full Flag - * 1 - The STB is filled with the maximal number of messages. - * 0 - The STB is not filled with the maximal number of messages. - * If the STB is disabled using STB_DISABLE, then TSFF=0. - * If TTEN=1 and TTTBM=1: Transmit buffer Slot Full Flag - * 1 - The buffer slot selected by TBPTR is filled. - * 0 - The buffer slot selected by TBPTR is empty. - */ -#define CAN_RTIE_TSFF_MASK (0x1U) -#define CAN_RTIE_TSFF_SHIFT (0U) -#define CAN_RTIE_TSFF_GET(x) (((uint8_t)(x) & CAN_RTIE_TSFF_MASK) >> CAN_RTIE_TSFF_SHIFT) - -/* Bitfield definition for register: RTIF */ -/* - * RIF (W1C) - * - * Receive Interrupt Flag - * 1 - Data or a remote frame has been received and is available in the receive buffer. - * 0 - No frame has been received. - */ -#define CAN_RTIF_RIF_MASK (0x80U) -#define CAN_RTIF_RIF_SHIFT (7U) -#define CAN_RTIF_RIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RIF_SHIFT) & CAN_RTIF_RIF_MASK) -#define CAN_RTIF_RIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RIF_MASK) >> CAN_RTIF_RIF_SHIFT) - -/* - * ROIF (W1C) - * - * RB Overrun Interrupt Flag - * 1 - At least one received message has been overwritten in the RB. - * 0 - No RB overwritten. - * In case of an overrun both ROIF and RFIF will be set. - */ -#define CAN_RTIF_ROIF_MASK (0x40U) -#define CAN_RTIF_ROIF_SHIFT (6U) -#define CAN_RTIF_ROIF_SET(x) (((uint8_t)(x) << CAN_RTIF_ROIF_SHIFT) & CAN_RTIF_ROIF_MASK) -#define CAN_RTIF_ROIF_GET(x) (((uint8_t)(x) & CAN_RTIF_ROIF_MASK) >> CAN_RTIF_ROIF_SHIFT) - -/* - * RFIF (W1C) - * - * RB Full Interrupt Flag - * 1 - All RBs are full. If no RB will be released until the next valid message is received, - * the oldest message will be lost. - * 0 - The RB FIFO is not full. - */ -#define CAN_RTIF_RFIF_MASK (0x20U) -#define CAN_RTIF_RFIF_SHIFT (5U) -#define CAN_RTIF_RFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RFIF_SHIFT) & CAN_RTIF_RFIF_MASK) -#define CAN_RTIF_RFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RFIF_MASK) >> CAN_RTIF_RFIF_SHIFT) - -/* - * RAFIF (W1C) - * - * RB Almost Full Interrupt Flag - * 1 - number of filled RB slots >= AFWL_i - * 0 - number of filled RB slots < AFWL_i - */ -#define CAN_RTIF_RAFIF_MASK (0x10U) -#define CAN_RTIF_RAFIF_SHIFT (4U) -#define CAN_RTIF_RAFIF_SET(x) (((uint8_t)(x) << CAN_RTIF_RAFIF_SHIFT) & CAN_RTIF_RAFIF_MASK) -#define CAN_RTIF_RAFIF_GET(x) (((uint8_t)(x) & CAN_RTIF_RAFIF_MASK) >> CAN_RTIF_RAFIF_SHIFT) - -/* - * TPIF (W1C) - * - * Transmission Primary Interrupt Flag - * 1 - The requested transmission of the PTB has been successfully completed. - * 0 - No transmission of the PTB has been completed. - * In TTCAN mode, TPIF will never be set. Then only TSIF is valid. - */ -#define CAN_RTIF_TPIF_MASK (0x8U) -#define CAN_RTIF_TPIF_SHIFT (3U) -#define CAN_RTIF_TPIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TPIF_SHIFT) & CAN_RTIF_TPIF_MASK) -#define CAN_RTIF_TPIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TPIF_MASK) >> CAN_RTIF_TPIF_SHIFT) - -/* - * TSIF (W1C) - * - * Transmission Secondary Interrupt Flag - * 1 - The requested transmission of the STB has been successfully completed. - * 0 - No transmission of the STB has been completed successfully. - * In TTCAN mode TSIF will signal all successful transmissions, regardless of storage location of - * the message. - */ -#define CAN_RTIF_TSIF_MASK (0x4U) -#define CAN_RTIF_TSIF_SHIFT (2U) -#define CAN_RTIF_TSIF_SET(x) (((uint8_t)(x) << CAN_RTIF_TSIF_SHIFT) & CAN_RTIF_TSIF_MASK) -#define CAN_RTIF_TSIF_GET(x) (((uint8_t)(x) & CAN_RTIF_TSIF_MASK) >> CAN_RTIF_TSIF_SHIFT) - -/* - * EIF (W1C) - * - * Error Interrupt Flag - * 1 - The border of the error warning limit has been crossed in either direction, - * or the BUSOFF bit has been changed in either direction. - * 0 - There has been no change. - */ -#define CAN_RTIF_EIF_MASK (0x2U) -#define CAN_RTIF_EIF_SHIFT (1U) -#define CAN_RTIF_EIF_SET(x) (((uint8_t)(x) << CAN_RTIF_EIF_SHIFT) & CAN_RTIF_EIF_MASK) -#define CAN_RTIF_EIF_GET(x) (((uint8_t)(x) & CAN_RTIF_EIF_MASK) >> CAN_RTIF_EIF_SHIFT) - -/* - * AIF (W1C) - * - * Abort Interrupt Flag - * 1 - After setting TPA or TSA the appropriated message(s) have been aborted. - * It is recommended to not set both TPA and TSA simultaneously because both - * source AIF. - * 0 - No abort has been executed. - * The AIF does not have an associated enable register. - */ -#define CAN_RTIF_AIF_MASK (0x1U) -#define CAN_RTIF_AIF_SHIFT (0U) -#define CAN_RTIF_AIF_SET(x) (((uint8_t)(x) << CAN_RTIF_AIF_SHIFT) & CAN_RTIF_AIF_MASK) -#define CAN_RTIF_AIF_GET(x) (((uint8_t)(x) & CAN_RTIF_AIF_MASK) >> CAN_RTIF_AIF_SHIFT) - -/* Bitfield definition for register: ERRINT */ -/* - * EWARN (RO) - * - * Error WARNing limit reached - * 1 - One of the error counters RECNT or TECNT is equal or bigger than EWL0 - The values in both counters are less than EWL. - */ -#define CAN_ERRINT_EWARN_MASK (0x80U) -#define CAN_ERRINT_EWARN_SHIFT (7U) -#define CAN_ERRINT_EWARN_GET(x) (((uint8_t)(x) & CAN_ERRINT_EWARN_MASK) >> CAN_ERRINT_EWARN_SHIFT) - -/* - * EPASS (RO) - * - * Error Passive mode active - * 0 - not active (node is error active) - * 1 - active (node is error passive) - */ -#define CAN_ERRINT_EPASS_MASK (0x40U) -#define CAN_ERRINT_EPASS_SHIFT (6U) -#define CAN_ERRINT_EPASS_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPASS_MASK) >> CAN_ERRINT_EPASS_SHIFT) - -/* - * EPIE (RW) - * - * Error Passive Interrupt Enable - */ -#define CAN_ERRINT_EPIE_MASK (0x20U) -#define CAN_ERRINT_EPIE_SHIFT (5U) -#define CAN_ERRINT_EPIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIE_SHIFT) & CAN_ERRINT_EPIE_MASK) -#define CAN_ERRINT_EPIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIE_MASK) >> CAN_ERRINT_EPIE_SHIFT) - -/* - * EPIF (W1C) - * - * Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error - * active to error passive or vice versa and if this interrupt is enabled. - */ -#define CAN_ERRINT_EPIF_MASK (0x10U) -#define CAN_ERRINT_EPIF_SHIFT (4U) -#define CAN_ERRINT_EPIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_EPIF_SHIFT) & CAN_ERRINT_EPIF_MASK) -#define CAN_ERRINT_EPIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_EPIF_MASK) >> CAN_ERRINT_EPIF_SHIFT) - -/* - * ALIE (RW) - * - * Arbitration Lost Interrupt Enable - */ -#define CAN_ERRINT_ALIE_MASK (0x8U) -#define CAN_ERRINT_ALIE_SHIFT (3U) -#define CAN_ERRINT_ALIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIE_SHIFT) & CAN_ERRINT_ALIE_MASK) -#define CAN_ERRINT_ALIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIE_MASK) >> CAN_ERRINT_ALIE_SHIFT) - -/* - * ALIF (W1C) - * - * Arbitration Lost Interrupt Flag - */ -#define CAN_ERRINT_ALIF_MASK (0x4U) -#define CAN_ERRINT_ALIF_SHIFT (2U) -#define CAN_ERRINT_ALIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_ALIF_SHIFT) & CAN_ERRINT_ALIF_MASK) -#define CAN_ERRINT_ALIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_ALIF_MASK) >> CAN_ERRINT_ALIF_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable - */ -#define CAN_ERRINT_BEIE_MASK (0x2U) -#define CAN_ERRINT_BEIE_SHIFT (1U) -#define CAN_ERRINT_BEIE_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIE_SHIFT) & CAN_ERRINT_BEIE_MASK) -#define CAN_ERRINT_BEIE_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIE_MASK) >> CAN_ERRINT_BEIE_SHIFT) - -/* - * BEIF (W1C) - * - * Bus Error Interrupt Flag - */ -#define CAN_ERRINT_BEIF_MASK (0x1U) -#define CAN_ERRINT_BEIF_SHIFT (0U) -#define CAN_ERRINT_BEIF_SET(x) (((uint8_t)(x) << CAN_ERRINT_BEIF_SHIFT) & CAN_ERRINT_BEIF_MASK) -#define CAN_ERRINT_BEIF_GET(x) (((uint8_t)(x) & CAN_ERRINT_BEIF_MASK) >> CAN_ERRINT_BEIF_SHIFT) - -/* Bitfield definition for register: LIMIT */ -/* - * AFWL (RW) - * - * receive buffer Almost Full Warning Limit - * AFWL defines the internal warning limit AFWL_i with being the number of availableRB slots. - * AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. Thevalid range of . - * AFWL = 0 is meaningless and automatically treated as 0x1. (Note that AFWL is meant in this rule and not AFWL_i.) - * AFWL_i > nRB is meaningless and automatically treated as nRB. - * AFWL_i = nRB is a valid value, but note that RFIF also exists. - */ -#define CAN_LIMIT_AFWL_MASK (0xF0U) -#define CAN_LIMIT_AFWL_SHIFT (4U) -#define CAN_LIMIT_AFWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_AFWL_SHIFT) & CAN_LIMIT_AFWL_MASK) -#define CAN_LIMIT_AFWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_AFWL_MASK) >> CAN_LIMIT_AFWL_SHIFT) - -/* - * EWL (RW) - * - * Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128. - * The value of EWL controls EIF. - */ -#define CAN_LIMIT_EWL_MASK (0xFU) -#define CAN_LIMIT_EWL_SHIFT (0U) -#define CAN_LIMIT_EWL_SET(x) (((uint8_t)(x) << CAN_LIMIT_EWL_SHIFT) & CAN_LIMIT_EWL_MASK) -#define CAN_LIMIT_EWL_GET(x) (((uint8_t)(x) & CAN_LIMIT_EWL_MASK) >> CAN_LIMIT_EWL_SHIFT) - -/* Bitfield definition for register: S_PRESC */ -/* - * S_PRESC (RW) - * - * Prescaler (slow speed) - * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - */ -#define CAN_S_PRESC_S_PRESC_MASK (0xFF000000UL) -#define CAN_S_PRESC_S_PRESC_SHIFT (24U) -#define CAN_S_PRESC_S_PRESC_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_PRESC_SHIFT) & CAN_S_PRESC_S_PRESC_MASK) -#define CAN_S_PRESC_S_PRESC_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_PRESC_MASK) >> CAN_S_PRESC_S_PRESC_SHIFT) - -/* - * S_SJW (RW) - * - * Synchronization Jump Width (slow speed) - * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - */ -#define CAN_S_PRESC_S_SJW_MASK (0x7F0000UL) -#define CAN_S_PRESC_S_SJW_SHIFT (16U) -#define CAN_S_PRESC_S_SJW_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SJW_SHIFT) & CAN_S_PRESC_S_SJW_MASK) -#define CAN_S_PRESC_S_SJW_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SJW_MASK) >> CAN_S_PRESC_S_SJW_SHIFT) - -/* - * S_SEG_2 (RW) - * - * Bit Timing Segment 2 (slow speed) - * Time after the sample point. - */ -#define CAN_S_PRESC_S_SEG_2_MASK (0x7F00U) -#define CAN_S_PRESC_S_SEG_2_SHIFT (8U) -#define CAN_S_PRESC_S_SEG_2_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_2_SHIFT) & CAN_S_PRESC_S_SEG_2_MASK) -#define CAN_S_PRESC_S_SEG_2_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_2_MASK) >> CAN_S_PRESC_S_SEG_2_SHIFT) - -/* - * S_SEG_1 (RW) - * - * Bit Timing Segment 1 (slow speed) - * The sample point will be set to after start of bit time. - */ -#define CAN_S_PRESC_S_SEG_1_MASK (0xFFU) -#define CAN_S_PRESC_S_SEG_1_SHIFT (0U) -#define CAN_S_PRESC_S_SEG_1_SET(x) (((uint32_t)(x) << CAN_S_PRESC_S_SEG_1_SHIFT) & CAN_S_PRESC_S_SEG_1_MASK) -#define CAN_S_PRESC_S_SEG_1_GET(x) (((uint32_t)(x) & CAN_S_PRESC_S_SEG_1_MASK) >> CAN_S_PRESC_S_SEG_1_SHIFT) - -/* Bitfield definition for register: F_PRESC */ -/* - * F_PRESC (RW) - * - * Prescaler (fast speed) - * The prescaler divides the system clock to get the time quanta clock tq_clk.Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256. - */ -#define CAN_F_PRESC_F_PRESC_MASK (0xFF000000UL) -#define CAN_F_PRESC_F_PRESC_SHIFT (24U) -#define CAN_F_PRESC_F_PRESC_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_PRESC_SHIFT) & CAN_F_PRESC_F_PRESC_MASK) -#define CAN_F_PRESC_F_PRESC_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_PRESC_MASK) >> CAN_F_PRESC_F_PRESC_SHIFT) - -/* - * F_SJW (RW) - * - * Synchronization Jump Width (fast speed) - * The Synchronization Jump Width is the maximum time forshortening or lengthening the Bit Time for resynchronization, where TQ is a timequanta. - */ -#define CAN_F_PRESC_F_SJW_MASK (0xF0000UL) -#define CAN_F_PRESC_F_SJW_SHIFT (16U) -#define CAN_F_PRESC_F_SJW_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SJW_SHIFT) & CAN_F_PRESC_F_SJW_MASK) -#define CAN_F_PRESC_F_SJW_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SJW_MASK) >> CAN_F_PRESC_F_SJW_SHIFT) - -/* - * F_SEG_2 (RW) - * - * Bit Timing Segment 2 (fast speed) - * Time after the sample point - */ -#define CAN_F_PRESC_F_SEG_2_MASK (0xF00U) -#define CAN_F_PRESC_F_SEG_2_SHIFT (8U) -#define CAN_F_PRESC_F_SEG_2_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_2_SHIFT) & CAN_F_PRESC_F_SEG_2_MASK) -#define CAN_F_PRESC_F_SEG_2_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_2_MASK) >> CAN_F_PRESC_F_SEG_2_SHIFT) - -/* - * F_SEG_1 (RW) - * - * Bit Timing Segment 1 (fast speed) - * The sample point will be set to after start of bit time. - */ -#define CAN_F_PRESC_F_SEG_1_MASK (0xFU) -#define CAN_F_PRESC_F_SEG_1_SHIFT (0U) -#define CAN_F_PRESC_F_SEG_1_SET(x) (((uint32_t)(x) << CAN_F_PRESC_F_SEG_1_SHIFT) & CAN_F_PRESC_F_SEG_1_MASK) -#define CAN_F_PRESC_F_SEG_1_GET(x) (((uint32_t)(x) & CAN_F_PRESC_F_SEG_1_MASK) >> CAN_F_PRESC_F_SEG_1_SHIFT) - -/* Bitfield definition for register: EALCAP */ -/* - * KOER (RO) - * - * Kind Of ERror (Error code) - * 000 - no error - * 001 - BIT ERROR - * 010 - FORM ERROR - * 011 - STUFF ERROR - * 100 - ACKNOWLEDGEMENT ERROR - * 101 - CRC ERROR - * 110 - OTHER ERROR(dominant bits after own error flag, received active Error Flag too long,dominant bit during Passive-Error-Flag after ACK error) - * 111 - not used - * KOER is updated with each new error. Therefore it stays untouched when frames aresuccessfully transmitted or received. - */ -#define CAN_EALCAP_KOER_MASK (0xE0U) -#define CAN_EALCAP_KOER_SHIFT (5U) -#define CAN_EALCAP_KOER_GET(x) (((uint8_t)(x) & CAN_EALCAP_KOER_MASK) >> CAN_EALCAP_KOER_SHIFT) - -/* - * ALC (RO) - * - * Arbitration Lost Capture (bit position in the frame where the arbitration has been lost) - */ -#define CAN_EALCAP_ALC_MASK (0x1FU) -#define CAN_EALCAP_ALC_SHIFT (0U) -#define CAN_EALCAP_ALC_GET(x) (((uint8_t)(x) & CAN_EALCAP_ALC_MASK) >> CAN_EALCAP_ALC_SHIFT) - -/* Bitfield definition for register: TDC */ -/* - * TDCEN (RW) - * - * Transmitter Delay Compensation ENable - * TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1. - */ -#define CAN_TDC_TDCEN_MASK (0x80U) -#define CAN_TDC_TDCEN_SHIFT (7U) -#define CAN_TDC_TDCEN_SET(x) (((uint8_t)(x) << CAN_TDC_TDCEN_SHIFT) & CAN_TDC_TDCEN_MASK) -#define CAN_TDC_TDCEN_GET(x) (((uint8_t)(x) & CAN_TDC_TDCEN_MASK) >> CAN_TDC_TDCEN_SHIFT) - -/* - * SSPOFF (RW) - * - * Secondary Sample Point OFFset - * The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC. - * SSPOFF is given as a number of TQ. - */ -#define CAN_TDC_SSPOFF_MASK (0x7FU) -#define CAN_TDC_SSPOFF_SHIFT (0U) -#define CAN_TDC_SSPOFF_SET(x) (((uint8_t)(x) << CAN_TDC_SSPOFF_SHIFT) & CAN_TDC_SSPOFF_MASK) -#define CAN_TDC_SSPOFF_GET(x) (((uint8_t)(x) & CAN_TDC_SSPOFF_MASK) >> CAN_TDC_SSPOFF_SHIFT) - -/* Bitfield definition for register: RECNT */ -/* - * RECNT (RO) - * - * Receive Error CouNT (number of errors during reception) - * RECNT is incremented and decremented as defined in the CAN specification. - * RECNT does not overflow. - * If TXB=1, then the error counters are frozen. - */ -#define CAN_RECNT_RECNT_MASK (0xFFU) -#define CAN_RECNT_RECNT_SHIFT (0U) -#define CAN_RECNT_RECNT_GET(x) (((uint8_t)(x) & CAN_RECNT_RECNT_MASK) >> CAN_RECNT_RECNT_SHIFT) - -/* Bitfield definition for register: TECNT */ -/* - * TECNT (RO) - * - * Transmit Error CouNT (number of errors during transmission) - * TECNT is incremented and decremented as defined in the CAN specification. - * In case of the “bus off state” TECNT may overflow. - * If TXB=1, then the error counters are frozen. - */ -#define CAN_TECNT_TECNT_MASK (0xFFU) -#define CAN_TECNT_TECNT_SHIFT (0U) -#define CAN_TECNT_TECNT_GET(x) (((uint8_t)(x) & CAN_TECNT_TECNT_MASK) >> CAN_TECNT_TECNT_SHIFT) - -/* Bitfield definition for register: ACFCTRL */ -/* - * SELMASK (RW) - * - * SELect acceptance MASK - * 0 - Registers ACF_x point to acceptance code - * 1 - Registers ACF_x point to acceptance mask. - * ACFADR selects one specific acceptance filter. - */ -#define CAN_ACFCTRL_SELMASK_MASK (0x20U) -#define CAN_ACFCTRL_SELMASK_SHIFT (5U) -#define CAN_ACFCTRL_SELMASK_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_SELMASK_SHIFT) & CAN_ACFCTRL_SELMASK_MASK) -#define CAN_ACFCTRL_SELMASK_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_SELMASK_MASK) >> CAN_ACFCTRL_SELMASK_SHIFT) - -/* - * ACFADR (RW) - * - * acceptance filter address - * ACFADR points to a specific acceptance filter. - * The selected filter is accessible using theregisters ACF_x. - * Bit SELMASK selects between acceptance code and mask for theselected acceptance filter. - * A value of ACFADR>ACF_NUMBER-1 is meaningless and automatically treated as value ACF_NUMBER-1. - * ACF_NUMBER = 16. - */ -#define CAN_ACFCTRL_ACFADR_MASK (0xFU) -#define CAN_ACFCTRL_ACFADR_SHIFT (0U) -#define CAN_ACFCTRL_ACFADR_SET(x) (((uint8_t)(x) << CAN_ACFCTRL_ACFADR_SHIFT) & CAN_ACFCTRL_ACFADR_MASK) -#define CAN_ACFCTRL_ACFADR_GET(x) (((uint8_t)(x) & CAN_ACFCTRL_ACFADR_MASK) >> CAN_ACFCTRL_ACFADR_SHIFT) - -/* Bitfield definition for register: TIMECFG */ -/* - * TIMEPOS (RW) - * - * TIME-stamping POSition - * 0 – SOF1 – EOF (see Chapter 7)TIMEPOS can only be changed if TIMEEN=0, but it is possible to modify TIMPOS withthe same write access that sets TIMEEN=1. - */ -#define CAN_TIMECFG_TIMEPOS_MASK (0x2U) -#define CAN_TIMECFG_TIMEPOS_SHIFT (1U) -#define CAN_TIMECFG_TIMEPOS_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEPOS_SHIFT) & CAN_TIMECFG_TIMEPOS_MASK) -#define CAN_TIMECFG_TIMEPOS_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEPOS_MASK) >> CAN_TIMECFG_TIMEPOS_SHIFT) - -/* - * TIMEEN (RW) - * - * TIME-stamping ENable - * 0 – disabled - * 1 – enabled - */ -#define CAN_TIMECFG_TIMEEN_MASK (0x1U) -#define CAN_TIMECFG_TIMEEN_SHIFT (0U) -#define CAN_TIMECFG_TIMEEN_SET(x) (((uint8_t)(x) << CAN_TIMECFG_TIMEEN_SHIFT) & CAN_TIMECFG_TIMEEN_MASK) -#define CAN_TIMECFG_TIMEEN_GET(x) (((uint8_t)(x) & CAN_TIMECFG_TIMEEN_MASK) >> CAN_TIMECFG_TIMEEN_SHIFT) - -/* Bitfield definition for register: ACF_EN */ -/* - * ACF_EN (RW) - * - * Acceptance filter Enable - * 1 - acceptance filter enabled - * 0 - acceptance filter disable - * Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. - * Disabled filters reject a message. Only enabled filters can accept a message if the - * appropriate AMASK / ACODE configuration matches. - */ -#define CAN_ACF_EN_ACF_EN_MASK (0xFFFFU) -#define CAN_ACF_EN_ACF_EN_SHIFT (0U) -#define CAN_ACF_EN_ACF_EN_SET(x) (((uint16_t)(x) << CAN_ACF_EN_ACF_EN_SHIFT) & CAN_ACF_EN_ACF_EN_MASK) -#define CAN_ACF_EN_ACF_EN_GET(x) (((uint16_t)(x) & CAN_ACF_EN_ACF_EN_MASK) >> CAN_ACF_EN_ACF_EN_SHIFT) - -/* Bitfield definition for register: ACF */ -/* - * AIDEE (RW) - * - * Acceptance mask IDE bit check enable - * 1 - acceptance filter accepts either standard or extended as defined by AIDE - * 0 - acceptance filter accepts both standard or extended frames - * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - */ -#define CAN_ACF_AIDEE_MASK (0x40000000UL) -#define CAN_ACF_AIDEE_SHIFT (30U) -#define CAN_ACF_AIDEE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDEE_SHIFT) & CAN_ACF_AIDEE_MASK) -#define CAN_ACF_AIDEE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDEE_MASK) >> CAN_ACF_AIDEE_SHIFT) - -/* - * AIDE (RW) - * - * Acceptance mask IDE bit value - * If AIDEE=1 then: - * 1 - acceptance filter accepts only extended frames - * 0 - acceptance filter accepts only standard frames - * Only filter 0 is affected by the power-on reset. All other filters stay uninitialized. - */ -#define CAN_ACF_AIDE_MASK (0x20000000UL) -#define CAN_ACF_AIDE_SHIFT (29U) -#define CAN_ACF_AIDE_SET(x) (((uint32_t)(x) << CAN_ACF_AIDE_SHIFT) & CAN_ACF_AIDE_MASK) -#define CAN_ACF_AIDE_GET(x) (((uint32_t)(x) & CAN_ACF_AIDE_MASK) >> CAN_ACF_AIDE_SHIFT) - -/* - * CODE_MASK (RW) - * - * Acceptance CODE - * 1 - ACC bit value to compare with ID bit of the received message - * 0 - ACC bit value to compare with ID bit of the received message - * ACODE_x(10:0) will be used for extended frames. - * ACODE_x(28:0) will be used for extended frames. - * Only filter 0 is affected by the power-on reset. - * Acceptance MASK(if SELMASK ==1 ) - * 1 - acceptance check for these bits of receive identifier disabled - * 0 - acceptance check for these bits of receive identifier enable - * AMASK_x(10:0) will be used for extended frames. - * AMASK_x(28:0) will be used for extended frames. - * Disabled bits result in accepting the message. Therefore the default configuration after - * reset for filter 0 accepts all messages. - * Only filter 0 is affected by the power-on reset. - */ -#define CAN_ACF_CODE_MASK_MASK (0x1FFFFFFFUL) -#define CAN_ACF_CODE_MASK_SHIFT (0U) -#define CAN_ACF_CODE_MASK_SET(x) (((uint32_t)(x) << CAN_ACF_CODE_MASK_SHIFT) & CAN_ACF_CODE_MASK_MASK) -#define CAN_ACF_CODE_MASK_GET(x) (((uint32_t)(x) & CAN_ACF_CODE_MASK_MASK) >> CAN_ACF_CODE_MASK_SHIFT) - -/* Bitfield definition for register: VER */ -/* - * VERSION (RW) - * - * Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and - * VER_0 the minor version.Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16 - */ -#define CAN_VER_VERSION_MASK (0xFFFFU) -#define CAN_VER_VERSION_SHIFT (0U) -#define CAN_VER_VERSION_SET(x) (((uint16_t)(x) << CAN_VER_VERSION_SHIFT) & CAN_VER_VERSION_MASK) -#define CAN_VER_VERSION_GET(x) (((uint16_t)(x) & CAN_VER_VERSION_MASK) >> CAN_VER_VERSION_SHIFT) - -/* Bitfield definition for register: TBSLOT */ -/* - * TBE (RW) - * - * set TB slot to “Empty” - * 1 - slot selected by TBPTR shall be marked as “empty” - * 0 - no actionTBE is automatically reset to 0 as soon as the slot is marked as empty and TSFF=0. - * If atransmission from this slot is active, then TBE stays set as long as either the transmission completes or after a transmission error or arbitration loss the - * transmissionis not active any more. - * If both TBF and TBE are set, then TBE wins - */ -#define CAN_TBSLOT_TBE_MASK (0x80U) -#define CAN_TBSLOT_TBE_SHIFT (7U) -#define CAN_TBSLOT_TBE_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBE_SHIFT) & CAN_TBSLOT_TBE_MASK) -#define CAN_TBSLOT_TBE_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBE_MASK) >> CAN_TBSLOT_TBE_SHIFT) - -/* - * TBF (RW) - * - * set TB slot to “Filled” - * 1 - slot selected by TBPTR shall be marked as “filled” - * 0 - no actionTBF is automatically reset to 0 as soon as the slot is marked as filled and TSFF=1. - * If both TBF and TBE are set, then TBE wins. - */ -#define CAN_TBSLOT_TBF_MASK (0x40U) -#define CAN_TBSLOT_TBF_SHIFT (6U) -#define CAN_TBSLOT_TBF_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBF_SHIFT) & CAN_TBSLOT_TBF_MASK) -#define CAN_TBSLOT_TBF_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBF_MASK) >> CAN_TBSLOT_TBF_SHIFT) - -/* - * TBPTR (RW) - * - * Pointer to a TB message slot. - * 0x00 - Pointer to the PTB - * others - Pointer to a slot in the STB - * The message slot pointed to by TBPTR is readable / writable using the TBUF registers. - * Write access is only possible if TSFF=0. - * Setting TBF to 1 marks the selected slot asfilled and setting TBE to 1 marks the selected slot as empty. - * TBSEL and TSNEXT are unused in TTCAN mode and have no meaning. - * TBPTR can only point to buffer slots, that exist in the hardware. - * Unusable bits ofTBPTR are fixed to 0. - * TBPTR is limited to the PTB and 63 STB slots. - * More slots cannot be used in TTCANmode.If TBPTR is too big and points to a slot that is not available, then TBF and TBE arereset automatically and no action takes place. - */ -#define CAN_TBSLOT_TBPTR_MASK (0x3FU) -#define CAN_TBSLOT_TBPTR_SHIFT (0U) -#define CAN_TBSLOT_TBPTR_SET(x) (((uint8_t)(x) << CAN_TBSLOT_TBPTR_SHIFT) & CAN_TBSLOT_TBPTR_MASK) -#define CAN_TBSLOT_TBPTR_GET(x) (((uint8_t)(x) & CAN_TBSLOT_TBPTR_MASK) >> CAN_TBSLOT_TBPTR_SHIFT) - -/* Bitfield definition for register: TTCFG */ -/* - * WTIE (RW) - * - * Watch Trigger Interrupt Enable - */ -#define CAN_TTCFG_WTIE_MASK (0x80U) -#define CAN_TTCFG_WTIE_SHIFT (7U) -#define CAN_TTCFG_WTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIE_SHIFT) & CAN_TTCFG_WTIE_MASK) -#define CAN_TTCFG_WTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIE_MASK) >> CAN_TTCFG_WTIE_SHIFT) - -/* - * WTIF (RW) - * - * Watch Trigger Interrupt Flag - * WTIF will be set if the cycle count reaches the limited defined by TT_WTRIG and WTIE is set. - */ -#define CAN_TTCFG_WTIF_MASK (0x40U) -#define CAN_TTCFG_WTIF_SHIFT (6U) -#define CAN_TTCFG_WTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_WTIF_SHIFT) & CAN_TTCFG_WTIF_MASK) -#define CAN_TTCFG_WTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_WTIF_MASK) >> CAN_TTCFG_WTIF_SHIFT) - -/* - * TEIF (RW) - * - * Trigger Error Interrupt Flag - * The conditions when TEIF will be set, are defined in Chapter 6.4. There is no bit toenable or disable the handling of TEIF - */ -#define CAN_TTCFG_TEIF_MASK (0x20U) -#define CAN_TTCFG_TEIF_SHIFT (5U) -#define CAN_TTCFG_TEIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TEIF_SHIFT) & CAN_TTCFG_TEIF_MASK) -#define CAN_TTCFG_TEIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TEIF_MASK) >> CAN_TTCFG_TEIF_SHIFT) - -/* - * TTIE (RW) - * - * Time Trigger Interrupt Enable - * If TTIE is set, then TTIF will be set if the cycle time is equal to the trigger timeTT_TRIG. - */ -#define CAN_TTCFG_TTIE_MASK (0x10U) -#define CAN_TTCFG_TTIE_SHIFT (4U) -#define CAN_TTCFG_TTIE_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIE_SHIFT) & CAN_TTCFG_TTIE_MASK) -#define CAN_TTCFG_TTIE_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIE_MASK) >> CAN_TTCFG_TTIE_SHIFT) - -/* - * TTIF (RW) - * - * Time Trigger Interrupt Flag - * TTIF will be set if TTIE is set and the cycle time is equal to the trigger time TT_TRIG. - * Writing a one to TTIF resets it. Writing a zero has no impact.TTIF will be set only once. - * If TT_TRIG gets not updated, then TTIF will be not setagain in the next basic cycle. - */ -#define CAN_TTCFG_TTIF_MASK (0x8U) -#define CAN_TTCFG_TTIF_SHIFT (3U) -#define CAN_TTCFG_TTIF_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTIF_SHIFT) & CAN_TTCFG_TTIF_MASK) -#define CAN_TTCFG_TTIF_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTIF_MASK) >> CAN_TTCFG_TTIF_SHIFT) - -/* - * T_PRESC (RW) - * - * TTCAN Timer PRESCaler - * 00b - 1 - * 01b - 2 - * 10b - 4 - * 11b - 8 - * The TTCAN time base is a CAN bittime defined by S_PRES, S_SEG_1 and S_SEG_2.With T_PRESC an additional prescaling factor of 1, 2, 4 or 8 is defined. - * T_PRESC can only be modified if TTEN=0, but it is possible to modify T_PRESC and setTTEN simultaneously with one write access. - */ -#define CAN_TTCFG_T_PRESC_MASK (0x6U) -#define CAN_TTCFG_T_PRESC_SHIFT (1U) -#define CAN_TTCFG_T_PRESC_SET(x) (((uint8_t)(x) << CAN_TTCFG_T_PRESC_SHIFT) & CAN_TTCFG_T_PRESC_MASK) -#define CAN_TTCFG_T_PRESC_GET(x) (((uint8_t)(x) & CAN_TTCFG_T_PRESC_MASK) >> CAN_TTCFG_T_PRESC_SHIFT) - -/* - * TTEN (RW) - * - * Time Trigger Enable - * 1 - TTCAN enabled, timer is running0 - disabled - */ -#define CAN_TTCFG_TTEN_MASK (0x1U) -#define CAN_TTCFG_TTEN_SHIFT (0U) -#define CAN_TTCFG_TTEN_SET(x) (((uint8_t)(x) << CAN_TTCFG_TTEN_SHIFT) & CAN_TTCFG_TTEN_MASK) -#define CAN_TTCFG_TTEN_GET(x) (((uint8_t)(x) & CAN_TTCFG_TTEN_MASK) >> CAN_TTCFG_TTEN_SHIFT) - -/* Bitfield definition for register: REF_MSG */ -/* - * REF_IDE (RW) - * - * REFerence message IDE bit. - */ -#define CAN_REF_MSG_REF_IDE_MASK (0x80000000UL) -#define CAN_REF_MSG_REF_IDE_SHIFT (31U) -#define CAN_REF_MSG_REF_IDE_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_IDE_SHIFT) & CAN_REF_MSG_REF_IDE_MASK) -#define CAN_REF_MSG_REF_IDE_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_IDE_MASK) >> CAN_REF_MSG_REF_IDE_SHIFT) - -/* - * REF_MSG (RW) - * - * REFerence message IDentifier. - * If REF_IDE is - * 1 - REF_ID(28:0) is valid (extended ID) - * 0 - REF_ID(10:0) is valid (standard ID) - * REF_ID is used in TTCAN mode to detect a reference message. This holds for time - * slaves (reception) as well as for the time master (transmission). If the reference - * message is detected and there are no errors, then the Sync_Mark of this frame will - * become the Ref_Mark. - * REF_ID(2:0) is not tested and therefore the appropriate register bits are forced to 0. - * These bits are used for up to 8 potential time masters. - * CAN-CTRL recognizes the reference message only by ID. The payload is not tested. - * Additional note: A time master will transmit a reference message in the same way as a - * normal frame. REF_ID is intended for detection of a successful transmission of a - * reference message. - */ -#define CAN_REF_MSG_REF_MSG_MASK (0x1FFFFFFFUL) -#define CAN_REF_MSG_REF_MSG_SHIFT (0U) -#define CAN_REF_MSG_REF_MSG_SET(x) (((uint32_t)(x) << CAN_REF_MSG_REF_MSG_SHIFT) & CAN_REF_MSG_REF_MSG_MASK) -#define CAN_REF_MSG_REF_MSG_GET(x) (((uint32_t)(x) & CAN_REF_MSG_REF_MSG_MASK) >> CAN_REF_MSG_REF_MSG_SHIFT) - -/* Bitfield definition for register: TRIG_CFG */ -/* - * TEW (RW) - * - * Transmit Enable Window - * For a single shot transmit trigger there is a time of up to 16 ticks of the cycle time - * where the frame is allowed to start. TWE+1 defines the number of ticks. - * TEW=0 is a valid setting and shortens the transmit enable window to 1 tick - */ -#define CAN_TRIG_CFG_TEW_MASK (0xF000U) -#define CAN_TRIG_CFG_TEW_SHIFT (12U) -#define CAN_TRIG_CFG_TEW_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TEW_SHIFT) & CAN_TRIG_CFG_TEW_MASK) -#define CAN_TRIG_CFG_TEW_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TEW_MASK) >> CAN_TRIG_CFG_TEW_SHIFT) - -/* - * TTYPE (RW) - * - * Trigger Type - * 000b - Immediate Trigger for immediate transmission - * 001b - Time Trigger for receive triggers - * 010b - Single Shot Transmit Trigger for exclusive time windows - * 011b - Transmit Start Trigger for merged arbitrating time windows - * 100b - Transmit Stop Trigger for merged arbitrating time windows - * others - no action - * The time of the trigger is defined by TT_TRIG. TTPTR selects the TB slot for the - * transmit triggers. See Chapter 6.4 for more details. - */ -#define CAN_TRIG_CFG_TTYPE_MASK (0x700U) -#define CAN_TRIG_CFG_TTYPE_SHIFT (8U) -#define CAN_TRIG_CFG_TTYPE_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTYPE_SHIFT) & CAN_TRIG_CFG_TTYPE_MASK) -#define CAN_TRIG_CFG_TTYPE_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTYPE_MASK) >> CAN_TRIG_CFG_TTYPE_SHIFT) - -/* - * TTPTR (RW) - * - * Transmit Trigger TB slot Pointer - * If TTPTR is too big and points to a slot that is not available, then TEIF is set and no - * new trigger can be activated after a write access to TT_TRIG_1. - * If TTPTR points to an empty slot, then TEIF will be set at the moment, when the - * trigger time is reached. - */ -#define CAN_TRIG_CFG_TTPTR_MASK (0x3FU) -#define CAN_TRIG_CFG_TTPTR_SHIFT (0U) -#define CAN_TRIG_CFG_TTPTR_SET(x) (((uint16_t)(x) << CAN_TRIG_CFG_TTPTR_SHIFT) & CAN_TRIG_CFG_TTPTR_MASK) -#define CAN_TRIG_CFG_TTPTR_GET(x) (((uint16_t)(x) & CAN_TRIG_CFG_TTPTR_MASK) >> CAN_TRIG_CFG_TTPTR_SHIFT) - -/* Bitfield definition for register: TT_TRIG */ -/* - * TT_TRIG (RW) - * - * Trigger Time - * TT_TRIG(15:0) defines the cycle time for a trigger. - * For a transmission trigger theearliest point of transmission of the SOF of the appropriate frame will be TT_TRIG+1. - */ -#define CAN_TT_TRIG_TT_TRIG_MASK (0xFFFFU) -#define CAN_TT_TRIG_TT_TRIG_SHIFT (0U) -#define CAN_TT_TRIG_TT_TRIG_SET(x) (((uint16_t)(x) << CAN_TT_TRIG_TT_TRIG_SHIFT) & CAN_TT_TRIG_TT_TRIG_MASK) -#define CAN_TT_TRIG_TT_TRIG_GET(x) (((uint16_t)(x) & CAN_TT_TRIG_TT_TRIG_MASK) >> CAN_TT_TRIG_TT_TRIG_SHIFT) - -/* Bitfield definition for register: TT_WTRIG */ -/* - * TT_WTRIG (RW) - * - * Watch Trigger Time - * TT_WTRIG(15:0) defines the cycle time for a watch trigger. The initial watch trigger isthe maximum cycle time 0xffff. - */ -#define CAN_TT_WTRIG_TT_WTRIG_MASK (0xFFFFU) -#define CAN_TT_WTRIG_TT_WTRIG_SHIFT (0U) -#define CAN_TT_WTRIG_TT_WTRIG_SET(x) (((uint16_t)(x) << CAN_TT_WTRIG_TT_WTRIG_SHIFT) & CAN_TT_WTRIG_TT_WTRIG_MASK) -#define CAN_TT_WTRIG_TT_WTRIG_GET(x) (((uint16_t)(x) & CAN_TT_WTRIG_TT_WTRIG_MASK) >> CAN_TT_WTRIG_TT_WTRIG_SHIFT) - - - -/* RBUF register group index macro definition */ -#define CAN_RBUF_BUF0 (0UL) -#define CAN_RBUF_BUF1 (1UL) -#define CAN_RBUF_BUF2 (2UL) -#define CAN_RBUF_BUF3 (3UL) -#define CAN_RBUF_BUF4 (4UL) -#define CAN_RBUF_BUF5 (5UL) -#define CAN_RBUF_BUF6 (6UL) -#define CAN_RBUF_BUF7 (7UL) -#define CAN_RBUF_BUF8 (8UL) -#define CAN_RBUF_BUF9 (9UL) -#define CAN_RBUF_BUF10 (10UL) -#define CAN_RBUF_BUF11 (11UL) -#define CAN_RBUF_BUF12 (12UL) -#define CAN_RBUF_BUF13 (13UL) -#define CAN_RBUF_BUF14 (14UL) -#define CAN_RBUF_BUF15 (15UL) -#define CAN_RBUF_BUF16 (16UL) -#define CAN_RBUF_BUF17 (17UL) -#define CAN_RBUF_BUF18 (18UL) -#define CAN_RBUF_BUF19 (19UL) - -/* TBUF register group index macro definition */ -#define CAN_TBUF_BUF0 (0UL) -#define CAN_TBUF_BUF1 (1UL) -#define CAN_TBUF_BUF2 (2UL) -#define CAN_TBUF_BUF3 (3UL) -#define CAN_TBUF_BUF4 (4UL) -#define CAN_TBUF_BUF5 (5UL) -#define CAN_TBUF_BUF6 (6UL) -#define CAN_TBUF_BUF7 (7UL) -#define CAN_TBUF_BUF8 (8UL) -#define CAN_TBUF_BUF9 (9UL) -#define CAN_TBUF_BUF10 (10UL) -#define CAN_TBUF_BUF11 (11UL) -#define CAN_TBUF_BUF12 (12UL) -#define CAN_TBUF_BUF13 (13UL) -#define CAN_TBUF_BUF14 (14UL) -#define CAN_TBUF_BUF15 (15UL) -#define CAN_TBUF_BUF16 (16UL) -#define CAN_TBUF_BUF17 (17UL) - -/* TTS register group index macro definition */ -#define CAN_TTS_WRD0 (0UL) -#define CAN_TTS_WRD1 (1UL) - - -#endif /* HPM_CAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_conctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_conctl_regs.h deleted file mode 100644 index 27da183d5e0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_conctl_regs.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CONCTL_H -#define HPM_CONCTL_H - -typedef struct { - __RW uint32_t CTRL0; /* 0x0: */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t CTRL2; /* 0x8: */ - __RW uint32_t CTRL3; /* 0xC: */ - __RW uint32_t CTRL4; /* 0x10: */ - __RW uint32_t CTRL5; /* 0x14: */ -} CONCTL_Type; - - -/* Bitfield definition for register: CTRL0 */ -/* - * ENET1_RXCLK_DLY_SEL (RW) - * - */ -#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK (0xF8000UL) -#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT (15U) -#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) -#define CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_RXCLK_DLY_SEL_SHIFT) - -/* - * ENET1_TXCLK_DLY_SEL (RW) - * - */ -#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK (0x7C00U) -#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT (10U) -#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) -#define CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET1_TXCLK_DLY_SEL_SHIFT) - -/* - * ENET0_RXCLK_DLY_SEL (RW) - * - */ -#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3E0U) -#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (5U) -#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) -#define CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) - -/* - * ENET0_TXCLK_DLY_SEL (RW) - * - */ -#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x1FU) -#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) -#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) -#define CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> CONCTL_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) - -/* Bitfield definition for register: CTRL2 */ -/* - * ENET0_LPI_IRQ_EN (RW) - * - * ENET0 LPI IRQ Enable - */ -#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) -#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) -#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) -#define CONCTL_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> CONCTL_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) - -/* - * ENET0_REFCLK_OE (RW) - * - */ -#define CONCTL_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) -#define CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) -#define CONCTL_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) -#define CONCTL_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_REFCLK_OE_MASK) >> CONCTL_CTRL2_ENET0_REFCLK_OE_SHIFT) - -/* - * ENET0_PHY_INTF_SEL (RW) - * - * 000:Reserved - * 001:RGMII - * 100:RMII - * 111:Reserved - */ -#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK (0xE000U) -#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT (13U) -#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) -#define CONCTL_CTRL2_ENET0_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_PHY_INTF_SEL_MASK) >> CONCTL_CTRL2_ENET0_PHY_INTF_SEL_SHIFT) - -/* - * ENET0_FLOWCTRL (RW) - * - */ -#define CONCTL_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) -#define CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) -#define CONCTL_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) -#define CONCTL_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_FLOWCTRL_MASK) >> CONCTL_CTRL2_ENET0_FLOWCTRL_SHIFT) - -/* - * ENET0_RMII_TXCLK_SEL (RW) - * - * default to use internal clk. - * set from pad， two option here: - * internal 50MHz clock out to pad then in; - * use external clock; - */ -#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) -#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) -#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) -#define CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) - -/* Bitfield definition for register: CTRL3 */ -/* - * ENET1_LPI_IRQ_EN (RW) - * - * ENET1 LPI Interrupt Enable - */ -#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK (0x20000000UL) -#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT (29U) -#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) -#define CONCTL_CTRL3_ENET1_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_LPI_IRQ_EN_MASK) >> CONCTL_CTRL3_ENET1_LPI_IRQ_EN_SHIFT) - -/* - * ENET1_REFCLK_OE (RW) - * - */ -#define CONCTL_CTRL3_ENET1_REFCLK_OE_MASK (0x80000UL) -#define CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT (19U) -#define CONCTL_CTRL3_ENET1_REFCLK_OE_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) -#define CONCTL_CTRL3_ENET1_REFCLK_OE_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_REFCLK_OE_MASK) >> CONCTL_CTRL3_ENET1_REFCLK_OE_SHIFT) - -/* - * ENET1_PHY_INTF_SEL (RW) - * - */ -#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK (0xE000U) -#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT (13U) -#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) -#define CONCTL_CTRL3_ENET1_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_PHY_INTF_SEL_MASK) >> CONCTL_CTRL3_ENET1_PHY_INTF_SEL_SHIFT) - -/* - * ENET1_FLOWCTRL (RW) - * - */ -#define CONCTL_CTRL3_ENET1_FLOWCTRL_MASK (0x1000U) -#define CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT (12U) -#define CONCTL_CTRL3_ENET1_FLOWCTRL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) -#define CONCTL_CTRL3_ENET1_FLOWCTRL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_FLOWCTRL_MASK) >> CONCTL_CTRL3_ENET1_FLOWCTRL_SHIFT) - -/* - * ENET1_RMII_TXCLK_SEL (RW) - * - */ -#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK (0x400U) -#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT (10U) -#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) -#define CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_MASK) >> CONCTL_CTRL3_ENET1_RMII_TXCLK_SEL_SHIFT) - -/* Bitfield definition for register: CTRL4 */ -/* - * SDXC0_SYS_IRQ_EN (RW) - * - * system irq enable - */ -#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK (0x80000000UL) -#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT (31U) -#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) -#define CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_SYS_IRQ_EN_SHIFT) - -/* - * SDXC0_WKP_IRQ_EN (RW) - * - * wakeup irq enable - */ -#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK (0x40000000UL) -#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT (30U) -#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) -#define CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_MASK) >> CONCTL_CTRL4_SDXC0_WKP_IRQ_EN_SHIFT) - -/* - * SDXC0_CARDCLK_INV_EN (RW) - * - * card clock inverter enable - */ -#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK (0x10000000UL) -#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT (28U) -#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) -#define CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL4_SDXC0_CARDCLK_INV_EN_SHIFT) - -/* - * SDXC0_GPR_TUNING_CARD_CLK_SEL (RW) - * - * for card clock DLL, default 0 - */ -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL) -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U) -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_CARD_CLK_SEL_SHIFT) - -/* - * SDXC0_GPR_TUNING_STROBE_SEL (RW) - * - * for strobe DLL, default 7taps(1ns) - */ -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL) -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT (18U) -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) -#define CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_TUNING_STROBE_SEL_SHIFT) - -/* - * SDXC0_GPR_STROBE_IN_ENABLE (RW) - * - * enable strobe clock, maybe used when update strobe DLL - */ -#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK (0x20000UL) -#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT (17U) -#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) -#define CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_STROBE_IN_ENABLE_SHIFT) - -/* - * SDXC0_GPR_CCLK_RX_DLY_SW_SEL (RW) - * - */ -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL) -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U) -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) - -/* - * SDXC0_GPR_CCLK_RX_DLY_SW_FORCE (RW) - * - * force use sw DLL config - */ -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U) -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U) -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) -#define CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL4_SDXC0_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) - -/* Bitfield definition for register: CTRL5 */ -/* - * SDXC1_SYS_IRQ_EN (RW) - * - * system irq enable - */ -#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK (0x80000000UL) -#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT (31U) -#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) -#define CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_SYS_IRQ_EN_SHIFT) - -/* - * SDXC1_WKP_IRQ_EN (RW) - * - * wakeup irq enable - */ -#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK (0x40000000UL) -#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT (30U) -#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) -#define CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_MASK) >> CONCTL_CTRL5_SDXC1_WKP_IRQ_EN_SHIFT) - -/* - * SDXC1_CARDCLK_INV_EN (RW) - * - * card clock inverter enable - */ -#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK (0x10000000UL) -#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT (28U) -#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) -#define CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_MASK) >> CONCTL_CTRL5_SDXC1_CARDCLK_INV_EN_SHIFT) - -/* - * SDXC1_GPR_TUNING_CARD_CLK_SEL (RW) - * - */ -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK (0xF800000UL) -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT (23U) -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_CARD_CLK_SEL_SHIFT) - -/* - * SDXC1_GPR_TUNING_STROBE_SEL (RW) - * - */ -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK (0x7C0000UL) -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT (18U) -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) -#define CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_TUNING_STROBE_SEL_SHIFT) - -/* - * SDXC1_GPR_STROBE_IN_ENABLE (RW) - * - */ -#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK (0x20000UL) -#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT (17U) -#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) -#define CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_STROBE_IN_ENABLE_SHIFT) - -/* - * SDXC1_GPR_CCLK_RX_DLY_SW_SEL (RW) - * - */ -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK (0x1F000UL) -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT (12U) -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_SEL_SHIFT) - -/* - * SDXC1_GPR_CCLK_RX_DLY_SW_FORCE (RW) - * - */ -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK (0x800U) -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT (11U) -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SET(x) (((uint32_t)(x) << CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) -#define CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_GET(x) (((uint32_t)(x) & CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_MASK) >> CONCTL_CTRL5_SDXC1_GPR_CCLK_RX_DLY_SW_FORCE_SHIFT) - - - - -#endif /* HPM_CONCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dao_regs.h deleted file mode 100644 index 671c35bdcf9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dao_regs.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAO_H -#define HPM_DAO_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t CMD; /* 0x8: Command Register */ - __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ - __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ - __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ -} DAO_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * HPF_EN (RW) - * - * Whether HPF is enabled. This HPF is used to filter out the DC part. - */ -#define DAO_CTRL_HPF_EN_MASK (0x20000UL) -#define DAO_CTRL_HPF_EN_SHIFT (17U) -#define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) -#define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) - -/* - * MONO (RW) - * - * Asserted to let the left and right channel output the same value. - */ -#define DAO_CTRL_MONO_MASK (0x80U) -#define DAO_CTRL_MONO_SHIFT (7U) -#define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) -#define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) - -/* - * RIGHT_EN (RW) - * - * Asserted to enable the right channel - */ -#define DAO_CTRL_RIGHT_EN_MASK (0x40U) -#define DAO_CTRL_RIGHT_EN_SHIFT (6U) -#define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) -#define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) - -/* - * LEFT_EN (RW) - * - * Asserted to enable the left channel - */ -#define DAO_CTRL_LEFT_EN_MASK (0x20U) -#define DAO_CTRL_LEFT_EN_SHIFT (5U) -#define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) -#define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) - -/* - * REMAP (RW) - * - * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative - * 0: Don't use remap pwm version - */ -#define DAO_CTRL_REMAP_MASK (0x10U) -#define DAO_CTRL_REMAP_SHIFT (4U) -#define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) -#define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) - -/* - * INVERT (RW) - * - * all the outputs are inverted before sending to pad - */ -#define DAO_CTRL_INVERT_MASK (0x8U) -#define DAO_CTRL_INVERT_SHIFT (3U) -#define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) -#define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) - -/* - * FALSE_LEVEL (RW) - * - * the pad output in False run mode, or when the module is disabled - * 0: all low - * 1: all high - * 2: P-high, N-low - * 3. output is not enabled - */ -#define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) -#define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) -#define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) -#define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) - -/* - * FALSE_RUN (RW) - * - * the module continues to consume data, but all the pads are constant, thus no audio out - */ -#define DAO_CTRL_FALSE_RUN_MASK (0x1U) -#define DAO_CTRL_FALSE_RUN_SHIFT (0U) -#define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) -#define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Self-clear - */ -#define DAO_CMD_SFTRST_MASK (0x2U) -#define DAO_CMD_SFTRST_SHIFT (1U) -#define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) -#define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) - -/* - * RUN (RW) - * - * Enable this module to run. - */ -#define DAO_CMD_RUN_MASK (0x1U) -#define DAO_CMD_RUN_SHIFT (0U) -#define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) -#define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) - -/* Bitfield definition for register: RX_CFGR */ -/* - * CH_MAX (RW) - * - * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 4'h2: 2 channels - * 4'h4: 4 channels - * etc - */ -#define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) -#define DAO_RX_CFGR_CH_MAX_SHIFT (6U) -#define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) -#define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) - -/* Bitfield definition for register: RXSLT */ -/* - * EN (RW) - * - * Slot enable for the channels. - */ -#define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) -#define DAO_RXSLT_EN_SHIFT (0U) -#define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) -#define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_MA_COEF_SHIFT (0U) -#define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) -#define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_B_COEF_SHIFT (0U) -#define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) -#define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_DAO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dma_regs.h deleted file mode 100644 index 214ed0213e0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dma_regs.h +++ /dev/null @@ -1,550 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMA_H -#define HPM_DMA_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ - __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ - __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ - __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ - __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ - __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel n Source Address Low Part Register */ - __RW uint32_t SRCADDRH; /* 0x4C: Channel n Source Address High Part Register */ - __RW uint32_t DSTADDR; /* 0x50: Channel n Destination Address Low Part Register */ - __RW uint32_t DSTADDRH; /* 0x54: Channel n Destination Address High Part Register */ - __RW uint32_t LLPOINTER; /* 0x58: Channel n Linked List Pointer Low Part Register */ - __RW uint32_t LLPOINTERH; /* 0x5C: Channel n Linked List Pointer High Part Register */ - } CHCTRL[8]; -} DMA_Type; - - -/* Bitfield definition for register: DMACFG */ -/* - * CHAINXFR (RO) - * - * Chain transfer - * 0x0: Chain transfer is not configured - * 0x1: Chain transfer is configured - */ -#define DMA_DMACFG_CHAINXFR_MASK (0x80000000UL) -#define DMA_DMACFG_CHAINXFR_SHIFT (31U) -#define DMA_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHAINXFR_MASK) >> DMA_DMACFG_CHAINXFR_SHIFT) - -/* - * REQSYNC (RO) - * - * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. - * 0x0: Request synchronization is not configured - * 0x1: Request synchronization is configured - */ -#define DMA_DMACFG_REQSYNC_MASK (0x40000000UL) -#define DMA_DMACFG_REQSYNC_SHIFT (30U) -#define DMA_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQSYNC_MASK) >> DMA_DMACFG_REQSYNC_SHIFT) - -/* - * DATAWIDTH (RO) - * - * AXI bus data width - * 0x0: 32 bits - * 0x1: 64 bits - * 0x2: 128 bits - * 0x3: 256 bits - */ -#define DMA_DMACFG_DATAWIDTH_MASK (0x3000000UL) -#define DMA_DMACFG_DATAWIDTH_SHIFT (24U) -#define DMA_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_DATAWIDTH_MASK) >> DMA_DMACFG_DATAWIDTH_SHIFT) - -/* - * ADDRWIDTH (RO) - * - * AXI bus address width - * 0x18: 24 bits - * 0x19: 25 bits - * ... - * 0x40: 64 bits - * Others: Invalid - */ -#define DMA_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) -#define DMA_DMACFG_ADDRWIDTH_SHIFT (17U) -#define DMA_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_ADDRWIDTH_MASK) >> DMA_DMACFG_ADDRWIDTH_SHIFT) - -/* - * CORENUM (RO) - * - * DMA core number - * 0x0: 1 core - * 0x1: 2 cores - */ -#define DMA_DMACFG_CORENUM_MASK (0x10000UL) -#define DMA_DMACFG_CORENUM_SHIFT (16U) -#define DMA_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CORENUM_MASK) >> DMA_DMACFG_CORENUM_SHIFT) - -/* - * BUSNUM (RO) - * - * AXI bus interface number - * 0x0: 1 AXI bus - * 0x1: 2 AXI busses - */ -#define DMA_DMACFG_BUSNUM_MASK (0x8000U) -#define DMA_DMACFG_BUSNUM_SHIFT (15U) -#define DMA_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_BUSNUM_MASK) >> DMA_DMACFG_BUSNUM_SHIFT) - -/* - * REQNUM (RO) - * - * Request/acknowledge pair number - * 0x0: 0 pair - * 0x1: 1 pair - * 0x2: 2 pairs - * ... - * 0x10: 16 pairs - */ -#define DMA_DMACFG_REQNUM_MASK (0x7C00U) -#define DMA_DMACFG_REQNUM_SHIFT (10U) -#define DMA_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQNUM_MASK) >> DMA_DMACFG_REQNUM_SHIFT) - -/* - * FIFODEPTH (RO) - * - * FIFO depth - * 0x4: 4 entries - * 0x8: 8 entries - * 0x10: 16 entries - * 0x20: 32 entries - * Others: Invalid - */ -#define DMA_DMACFG_FIFODEPTH_MASK (0x3F0U) -#define DMA_DMACFG_FIFODEPTH_SHIFT (4U) -#define DMA_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_FIFODEPTH_MASK) >> DMA_DMACFG_FIFODEPTH_SHIFT) - -/* - * CHANNELNUM (RO) - * - * Channel number - * 0x1: 1 channel - * 0x2: 2 channels - * ... - * 0x8: 8 channels - * Others: Invalid - */ -#define DMA_DMACFG_CHANNELNUM_MASK (0xFU) -#define DMA_DMACFG_CHANNELNUM_SHIFT (0U) -#define DMA_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHANNELNUM_MASK) >> DMA_DMACFG_CHANNELNUM_SHIFT) - -/* Bitfield definition for register: DMACTRL */ -/* - * RESET (WO) - * - * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. - * Note: The software reset may cause the in-completion of AXI transaction. - */ -#define DMA_DMACTRL_RESET_MASK (0x1U) -#define DMA_DMACTRL_RESET_SHIFT (0U) -#define DMA_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMA_DMACTRL_RESET_SHIFT) & DMA_DMACTRL_RESET_MASK) -#define DMA_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMA_DMACTRL_RESET_MASK) >> DMA_DMACTRL_RESET_SHIFT) - -/* Bitfield definition for register: CHABORT */ -/* - * CHABORT (WO) - * - * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - */ -#define DMA_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) -#define DMA_CHABORT_CHABORT_SHIFT (0U) -#define DMA_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMA_CHABORT_CHABORT_SHIFT) & DMA_CHABORT_CHABORT_MASK) -#define DMA_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMA_CHABORT_CHABORT_MASK) >> DMA_CHABORT_CHABORT_SHIFT) - -/* Bitfield definition for register: INTSTATUS */ -/* - * TC (W1C) - * - * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. - * 0x0: Channel n has no terminal count status - * 0x1: Channel n has terminal count status - */ -#define DMA_INTSTATUS_TC_MASK (0xFF0000UL) -#define DMA_INTSTATUS_TC_SHIFT (16U) -#define DMA_INTSTATUS_TC_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_TC_SHIFT) & DMA_INTSTATUS_TC_MASK) -#define DMA_INTSTATUS_TC_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_TC_MASK) >> DMA_INTSTATUS_TC_SHIFT) - -/* - * ABORT (W1C) - * - * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. - * 0x0: Channel n has no abort status - * 0x1: Channel n has abort status - */ -#define DMA_INTSTATUS_ABORT_MASK (0xFF00U) -#define DMA_INTSTATUS_ABORT_SHIFT (8U) -#define DMA_INTSTATUS_ABORT_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ABORT_SHIFT) & DMA_INTSTATUS_ABORT_MASK) -#define DMA_INTSTATUS_ABORT_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ABORT_MASK) >> DMA_INTSTATUS_ABORT_SHIFT) - -/* - * ERROR (W1C) - * - * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - * - Bus error - * - Unaligned address - * - Unaligned transfer width - * - Reserved configuration - * 0x0: Channel n has no error status - * 0x1: Channel n has error status - */ -#define DMA_INTSTATUS_ERROR_MASK (0xFFU) -#define DMA_INTSTATUS_ERROR_SHIFT (0U) -#define DMA_INTSTATUS_ERROR_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ERROR_SHIFT) & DMA_INTSTATUS_ERROR_MASK) -#define DMA_INTSTATUS_ERROR_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ERROR_MASK) >> DMA_INTSTATUS_ERROR_SHIFT) - -/* Bitfield definition for register: CHEN */ -/* - * CHEN (RO) - * - * Alias of the Enable field of all ChnCtrl registers - */ -#define DMA_CHEN_CHEN_MASK (0xFFFFFFFFUL) -#define DMA_CHEN_CHEN_SHIFT (0U) -#define DMA_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMA_CHEN_CHEN_MASK) >> DMA_CHEN_CHEN_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CTRL */ -/* - * SRCBUSINFIDX (RW) - * - * Bus interface index that source data is read from - * 0x0: Data is read from bus interface 0 - * 0x1: Data is read from bus interface - */ -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK (0x80000000UL) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT (31U) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) -#define DMA_CHCTRL_CTRL_SRCBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) - -/* - * DSTBUSINFIDX (RW) - * - * Bus interface index that destination data is written to - * 0x0: Data is written to bus interface 0 - * 0x1: Data is written to bus interface 1 - */ -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK (0x40000000UL) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT (30U) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) -#define DMA_CHCTRL_CTRL_DSTBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) - -/* - * PRIORITY (RW) - * - * Channel priority level - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define DMA_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) -#define DMA_CHCTRL_CTRL_PRIORITY_SHIFT (29U) -#define DMA_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_PRIORITY_SHIFT) & DMA_CHCTRL_CTRL_PRIORITY_MASK) -#define DMA_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_PRIORITY_MASK) >> DMA_CHCTRL_CTRL_PRIORITY_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. - * The burst transfer byte number is (SrcBurstSize * SrcWidth). - * 0x0: 1 transfer - * 0x1: 2 transfers - * 0x2: 4 transfers - * 0x3: 8 transfers - * 0x4: 16 transfers - * 0x5: 32 transfers - * 0x6: 64 transfers - * 0x7: 128 transfers - * 0x8: 256 transfers - * 0x9:512 transfers - * 0xa: 1024 transfers - * 0xb-0xf: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0xa; for HDMA, the maximum allowed value is 0x7 - */ -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) -#define DMA_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source transfer width - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - */ -#define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) -#define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) -#define DMA_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) -#define DMA_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination transfer width. - * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. - * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6-x7: Reserved, setting this field with a reserved value triggers the error exception - * for XDMA, the maximum allowed value is 0x3, for HDMA, the maximum allowed value is 0x2 - */ -#define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) -#define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) -#define DMA_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) -#define DMA_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * Source DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define DMA_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) -#define DMA_CHCTRL_CTRL_SRCMODE_SHIFT (17U) -#define DMA_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCMODE_SHIFT) & DMA_CHCTRL_CTRL_SRCMODE_MASK) -#define DMA_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCMODE_MASK) >> DMA_CHCTRL_CTRL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * Destination DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define DMA_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) -#define DMA_CHCTRL_CTRL_DSTMODE_SHIFT (16U) -#define DMA_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTMODE_SHIFT) & DMA_CHCTRL_CTRL_DSTMODE_MASK) -#define DMA_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTMODE_MASK) >> DMA_CHCTRL_CTRL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * Source address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) -#define DMA_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * Destination address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) -#define DMA_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) - -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define DMA_CHCTRL_CTRL_SRCREQSEL_MASK (0xF00U) -#define DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT (8U) -#define DMA_CHCTRL_CTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) -#define DMA_CHCTRL_CTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) >> DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define DMA_CHCTRL_CTRL_DSTREQSEL_MASK (0xF0U) -#define DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT (4U) -#define DMA_CHCTRL_CTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) -#define DMA_CHCTRL_CTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) >> DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) - -/* - * INTABTMASK (RW) - * - * Channel abort interrupt mask - * 0x0: Allow the abort interrupt to be triggered - * 0x1: Disable the abort interrupt - */ -#define DMA_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) -#define DMA_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) -#define DMA_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) -#define DMA_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) >> DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) - -/* - * INTERRMASK (RW) - * - * Channel error interrupt mask - * 0x0: Allow the error interrupt to be triggered - * 0x1: Disable the error interrupt - */ -#define DMA_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) -#define DMA_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) -#define DMA_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) -#define DMA_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) >> DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) - -/* - * INTTCMASK (RW) - * - * Channel terminal count interrupt mask - * 0x0: Allow the terminal count interrupt to be triggered - * 0x1: Disable the terminal count interrupt - */ -#define DMA_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) -#define DMA_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) -#define DMA_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) -#define DMA_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) >> DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) - -/* - * ENABLE (RW) - * - * Channel enable bit - * 0x0: Disable - * 0x1: Enable - */ -#define DMA_CHCTRL_CTRL_ENABLE_MASK (0x1U) -#define DMA_CHCTRL_CTRL_ENABLE_SHIFT (0U) -#define DMA_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_ENABLE_SHIFT) & DMA_CHCTRL_CTRL_ENABLE_MASK) -#define DMA_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_ENABLE_MASK) >> DMA_CHCTRL_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ -/* - * TRANSIZE (RW) - * - * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. - * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - */ -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) -#define DMA_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ -/* - * SRCADDRL (RW) - * - * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - */ -#define DMA_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) -#define DMA_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDRH */ -/* - * SRCADDRH (RW) - * - * High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT (0U) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) -#define DMA_CHCTRL_SRCADDRH_SRCADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) >> DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ -/* - * DSTADDRL (RW) - * - * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - */ -#define DMA_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) -#define DMA_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDRH */ -/* - * DSTADDRH (RW) - * - * High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT (0U) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) -#define DMA_CHCTRL_DSTADDRH_DSTADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) >> DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ -/* - * LLPOINTERL (RW) - * - * Low part of the pointer to the next descriptor. The pointer must be double word aligned. - */ -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) -#define DMA_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) - -/* - * LLDBUSINFIDX (RW) - * - * Bus interface index that the next descriptor is read from - * 0x0: The next descriptor is read from bus interface 0 - */ -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK (0x1U) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT (0U) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) -#define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) >> DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTERH */ -/* - * LLPOINTERH (RW) - * - * High part of the pointer to the next descriptor. - * This register exists only when the address bus width is wider than 32 bits. - */ -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK (0xFFFFFFFFUL) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT (0U) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) -#define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) >> DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) - - - -/* CHCTRL register group index macro definition */ -#define DMA_CHCTRL_CH0 (0UL) -#define DMA_CHCTRL_CH1 (1UL) -#define DMA_CHCTRL_CH2 (2UL) -#define DMA_CHCTRL_CH3 (3UL) -#define DMA_CHCTRL_CH4 (4UL) -#define DMA_CHCTRL_CH5 (5UL) -#define DMA_CHCTRL_CH6 (6UL) -#define DMA_CHCTRL_CH7 (7UL) - - -#endif /* HPM_DMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dmamux_regs.h deleted file mode 100644 index e7f67339ea4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_dmamux_regs.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_H -#define HPM_DMAMUX_H - -typedef struct { - __RW uint32_t MUXCFG[16]; /* 0x0 - 0x3C: HDMA MUX0 Configuration */ -} DMAMUX_Type; - - -/* Bitfield definition for register array: MUXCFG */ -/* - * ENABLE (RW) - * - * DMA Mux Channel Enable - * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be - * used to disable or reconfigure a DMA channel. - * 0b - DMA Mux channel is disabled - * 1b - DMA Mux channel is enabled - */ -#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) -#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) -#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) -#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) - -/* - * SOURCE (RW) - * - * DMA Channel Source - * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - */ -#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) -#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) -#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) - - - -/* MUXCFG register group index macro definition */ -#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) -#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) -#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) -#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) -#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) -#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) -#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) -#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) -#define DMAMUX_MUXCFG_XDMA_MUX0 (8UL) -#define DMAMUX_MUXCFG_XDMA_MUX1 (9UL) -#define DMAMUX_MUXCFG_XDMA_MUX2 (10UL) -#define DMAMUX_MUXCFG_XDMA_MUX3 (11UL) -#define DMAMUX_MUXCFG_XDMA_MUX4 (12UL) -#define DMAMUX_MUXCFG_XDMA_MUX5 (13UL) -#define DMAMUX_MUXCFG_XDMA_MUX6 (14UL) -#define DMAMUX_MUXCFG_XDMA_MUX7 (15UL) - - -#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_enet_regs.h deleted file mode 100644 index 2908c0cfdd9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_enet_regs.h +++ /dev/null @@ -1,6062 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ENET_H -#define HPM_ENET_H - -typedef struct { - __RW uint32_t MACCFG; /* 0x0: MAC Configuration Register */ - __RW uint32_t MACFF; /* 0x4: MAC Frame Filter */ - __RW uint32_t HASH_H; /* 0x8: Hash Table High Register */ - __RW uint32_t HASH_L; /* 0xC: Hash Table Low Register */ - __RW uint32_t GMII_ADDR; /* 0x10: GMII Address Register */ - __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ - __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ - __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ - __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ - __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ - __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ - __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Register */ - __RW uint32_t LPI_TCR; /* 0x34: LPI Timers Control Register */ - __R uint32_t INTR_STATUS; /* 0x38: Interrupt Status Register */ - __RW uint32_t INTR_MASK; /* 0x3C: Interrupt Mask Register */ - __RW uint32_t MAC_ADDR_0_HIGH; /* 0x40: MAC Address 0 High Register */ - __RW uint32_t MAC_ADDR_0_LOW; /* 0x44: MAC Address 0 Low Register */ - struct { - __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ - __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ - } MAC_ADDR[4]; - __R uint8_t RESERVED1[112]; /* 0x68 - 0xD7: Reserved */ - __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ - __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ - __R uint8_t RESERVED2[32]; /* 0xE0 - 0xFF: Reserved */ - __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ - __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt */ - __RW uint32_t MMC_INTR_TX; /* 0x108: MMC Transmit Interrupt */ - __RW uint32_t MMC_INTR_MASK_RX; /* 0x10C: MMC Receive Interrupt mask */ - __RW uint32_t MMC_INTR_MASK_TX; /* 0x110: MMC Transmit Interrupt Mask */ - __R uint8_t RESERVED3[16]; /* 0x114 - 0x123: Reserved */ - __RW uint32_t TX64OCTETS_GB; /* 0x124: Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. */ - __RW uint32_t TX65TO127OCTETS_GB; /* 0x128: Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX128TO255OCTETS_GB; /* 0x12C: Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX256TO511OCTETS_GB; /* 0x130: Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX512TO1023OCTETS_GB; /* 0x134: Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. */ - __R uint8_t RESERVED4[68]; /* 0x13C - 0x17F: Reserved */ - __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ - __R uint8_t RESERVED5[124]; /* 0x184 - 0x1FF: Reserved */ - __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. */ - __R uint8_t RESERVED6[4]; /* 0x204 - 0x207: Reserved */ - __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. */ - __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */ - __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload */ - __R uint8_t RESERVED8[492]; /* 0x214 - 0x3FF: Reserved */ - struct { - __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ - __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ - __R uint8_t RESERVED0[8]; /* 0x408 - 0x40F: Reserved */ - __RW uint32_t L3_ADDR_0; /* 0x410: Layer 3 Address 0 Register */ - __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ - __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ - __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ - } L3_L4_CFG[1]; - __R uint8_t RESERVED9[356]; /* 0x420 - 0x583: Reserved */ - __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ - __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ - __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ - __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ - __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ - __R uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ - __R uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ - __RW uint32_t SYST_SEC_UPD; /* 0x710: System Time - Seconds Update Register */ - __RW uint32_t SYST_NSEC_UPD; /* 0x714: System Time - Nanoseconds Update Register */ - __RW uint32_t TS_ADDEND; /* 0x718: Timestamp Addend Register */ - __RW uint32_t TGTTM_SEC; /* 0x71C: Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x720: Target Time Nanoseconds Register */ - __RW uint32_t SYSTM_H_SEC; /* 0x724: System Time - Higher Word Seconds Register */ - __R uint32_t TS_STATUS; /* 0x728: Timestamp Status Register */ - __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ - __R uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ - __R uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ - __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ - __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS Interval Register */ - __RW uint32_t PPS0_WIDTH; /* 0x764: PPS Width Register */ - __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ - struct { - __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ - __RW uint32_t INTERVAL; /* 0x788: PPS Interval Register */ - __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ - __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ - } PPS[3]; - __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ - __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ - __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ - __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ - __RW uint32_t DMA_RX_DESC_LIST_ADDR; /* 0x100C: Receive Descriptor List Address Register */ - __RW uint32_t DMA_TX_DESC_LIST_ADDR; /* 0x1010: Transmit Descriptor List Address Register */ - __RW uint32_t DMA_STATUS; /* 0x1014: Status Register */ - __RW uint32_t DMA_OP_MODE; /* 0x1018: Operation Mode Register */ - __RW uint32_t DMA_INTR_EN; /* 0x101C: Interrupt Enable Register */ - __RW uint32_t DMA_MISS_OVF_CNT; /* 0x1020: Missed Frame And Buffer Overflow Counter Register */ - __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ - __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ - __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ - __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ - __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ - __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ -} ENET_Type; - - -/* Bitfield definition for register: MACCFG */ -/* - * SARC (RW) - * - * Source Address Insertion or Replacement Control - * This field controls the source address insertion or replacement for all transmitted frames. - * Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: - * - 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. - * - 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * - 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * Note: - Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, - * that is, the current frame does not use the updated value. - * - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - */ -#define ENET_MACCFG_SARC_MASK (0x70000000UL) -#define ENET_MACCFG_SARC_SHIFT (28U) -#define ENET_MACCFG_SARC_SET(x) (((uint32_t)(x) << ENET_MACCFG_SARC_SHIFT) & ENET_MACCFG_SARC_MASK) -#define ENET_MACCFG_SARC_GET(x) (((uint32_t)(x) & ENET_MACCFG_SARC_MASK) >> ENET_MACCFG_SARC_SHIFT) - -/* - * TWOKPE (RW) - * - * IEEE 802.3as Support for 2K Packets - * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. - * When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. - * When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. - * When Bit 20 is set, setting this bit has no effect on Giant Frame status. - */ -#define ENET_MACCFG_TWOKPE_MASK (0x8000000UL) -#define ENET_MACCFG_TWOKPE_SHIFT (27U) -#define ENET_MACCFG_TWOKPE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TWOKPE_SHIFT) & ENET_MACCFG_TWOKPE_MASK) -#define ENET_MACCFG_TWOKPE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TWOKPE_MASK) >> ENET_MACCFG_TWOKPE_SHIFT) - -/* - * SFTERR (RW) - * - * SMII Force Transmit Error - * When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_SFTERR_MASK (0x4000000UL) -#define ENET_MACCFG_SFTERR_SHIFT (26U) -#define ENET_MACCFG_SFTERR_SET(x) (((uint32_t)(x) << ENET_MACCFG_SFTERR_SHIFT) & ENET_MACCFG_SFTERR_MASK) -#define ENET_MACCFG_SFTERR_GET(x) (((uint32_t)(x) & ENET_MACCFG_SFTERR_MASK) >> ENET_MACCFG_SFTERR_SHIFT) - -/* - * CST (RW) - * - * CRC Stripping for Type Frames - * When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. - * This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - */ -#define ENET_MACCFG_CST_MASK (0x2000000UL) -#define ENET_MACCFG_CST_SHIFT (25U) -#define ENET_MACCFG_CST_SET(x) (((uint32_t)(x) << ENET_MACCFG_CST_SHIFT) & ENET_MACCFG_CST_MASK) -#define ENET_MACCFG_CST_GET(x) (((uint32_t)(x) & ENET_MACCFG_CST_MASK) >> ENET_MACCFG_CST_SHIFT) - -/* - * TC (RW) - * - * Transmit Configuration in RGMII, SGMII, or SMII - * When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - * or SGMII port. When this bit is reset, no such information is driven to the PHY. - * This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_TC_MASK (0x1000000UL) -#define ENET_MACCFG_TC_SHIFT (24U) -#define ENET_MACCFG_TC_SET(x) (((uint32_t)(x) << ENET_MACCFG_TC_SHIFT) & ENET_MACCFG_TC_MASK) -#define ENET_MACCFG_TC_GET(x) (((uint32_t)(x) & ENET_MACCFG_TC_MASK) >> ENET_MACCFG_TC_SHIFT) - -/* - * WD (RW) - * - * Watchdog Disable - * When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - */ -#define ENET_MACCFG_WD_MASK (0x800000UL) -#define ENET_MACCFG_WD_SHIFT (23U) -#define ENET_MACCFG_WD_SET(x) (((uint32_t)(x) << ENET_MACCFG_WD_SHIFT) & ENET_MACCFG_WD_MASK) -#define ENET_MACCFG_WD_GET(x) (((uint32_t)(x) & ENET_MACCFG_WD_MASK) >> ENET_MACCFG_WD_SHIFT) - -/* - * JD (RW) - * - * Jabber Disable - * When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. - * When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - */ -#define ENET_MACCFG_JD_MASK (0x400000UL) -#define ENET_MACCFG_JD_SHIFT (22U) -#define ENET_MACCFG_JD_SET(x) (((uint32_t)(x) << ENET_MACCFG_JD_SHIFT) & ENET_MACCFG_JD_MASK) -#define ENET_MACCFG_JD_GET(x) (((uint32_t)(x) & ENET_MACCFG_JD_MASK) >> ENET_MACCFG_JD_SHIFT) - -/* - * BE (RW) - * - * Frame Burst Enable - * When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - */ -#define ENET_MACCFG_BE_MASK (0x200000UL) -#define ENET_MACCFG_BE_SHIFT (21U) -#define ENET_MACCFG_BE_SET(x) (((uint32_t)(x) << ENET_MACCFG_BE_SHIFT) & ENET_MACCFG_BE_MASK) -#define ENET_MACCFG_BE_GET(x) (((uint32_t)(x) & ENET_MACCFG_BE_MASK) >> ENET_MACCFG_BE_SHIFT) - -/* - * JE (RW) - * - * Jumbo Frame Enable - * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - */ -#define ENET_MACCFG_JE_MASK (0x100000UL) -#define ENET_MACCFG_JE_SHIFT (20U) -#define ENET_MACCFG_JE_SET(x) (((uint32_t)(x) << ENET_MACCFG_JE_SHIFT) & ENET_MACCFG_JE_MASK) -#define ENET_MACCFG_JE_GET(x) (((uint32_t)(x) & ENET_MACCFG_JE_MASK) >> ENET_MACCFG_JE_SHIFT) - -/* - * IFG (RW) - * - * Inter-Frame Gap - * These bits control the minimum IFG between frames during transmission. - * - 000: 96 bit times - * - 001: 88 bit times - * - 010: 80 bit times - ... - * - 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). - * Lower values are not considered. - * In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - * When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - */ -#define ENET_MACCFG_IFG_MASK (0xE0000UL) -#define ENET_MACCFG_IFG_SHIFT (17U) -#define ENET_MACCFG_IFG_SET(x) (((uint32_t)(x) << ENET_MACCFG_IFG_SHIFT) & ENET_MACCFG_IFG_MASK) -#define ENET_MACCFG_IFG_GET(x) (((uint32_t)(x) & ENET_MACCFG_IFG_MASK) >> ENET_MACCFG_IFG_SHIFT) - -/* - * DCRS (RW) - * - * Disable Carrier Sense During Transmission - * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - * This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. - * When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - */ -#define ENET_MACCFG_DCRS_MASK (0x10000UL) -#define ENET_MACCFG_DCRS_SHIFT (16U) -#define ENET_MACCFG_DCRS_SET(x) (((uint32_t)(x) << ENET_MACCFG_DCRS_SHIFT) & ENET_MACCFG_DCRS_MASK) -#define ENET_MACCFG_DCRS_GET(x) (((uint32_t)(x) & ENET_MACCFG_DCRS_MASK) >> ENET_MACCFG_DCRS_SHIFT) - -/* - * PS (RW) - * - * Port Select - * This bit selects the Ethernet line speed. - * - 0: For 1000 Mbps operations - * - 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. - * In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, - * this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - */ -#define ENET_MACCFG_PS_MASK (0x8000U) -#define ENET_MACCFG_PS_SHIFT (15U) -#define ENET_MACCFG_PS_SET(x) (((uint32_t)(x) << ENET_MACCFG_PS_SHIFT) & ENET_MACCFG_PS_MASK) -#define ENET_MACCFG_PS_GET(x) (((uint32_t)(x) & ENET_MACCFG_PS_MASK) >> ENET_MACCFG_PS_SHIFT) - -/* - * FES (RW) - * - * Speed - * This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: - * - 0: 10 Mbps - * - 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. - * This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. - * This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. - * In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. - * In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - */ -#define ENET_MACCFG_FES_MASK (0x4000U) -#define ENET_MACCFG_FES_SHIFT (14U) -#define ENET_MACCFG_FES_SET(x) (((uint32_t)(x) << ENET_MACCFG_FES_SHIFT) & ENET_MACCFG_FES_MASK) -#define ENET_MACCFG_FES_GET(x) (((uint32_t)(x) & ENET_MACCFG_FES_MASK) >> ENET_MACCFG_FES_SHIFT) - -/* - * DO (RW) - * - * Disable Receive Own - * When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. - * When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. - * This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - */ -#define ENET_MACCFG_DO_MASK (0x2000U) -#define ENET_MACCFG_DO_SHIFT (13U) -#define ENET_MACCFG_DO_SET(x) (((uint32_t)(x) << ENET_MACCFG_DO_SHIFT) & ENET_MACCFG_DO_MASK) -#define ENET_MACCFG_DO_GET(x) (((uint32_t)(x) & ENET_MACCFG_DO_MASK) >> ENET_MACCFG_DO_SHIFT) - -/* - * LM (RW) - * - * Loopback Mode - * When this bit is set, the MAC operates in the loopback mode at GMII or MII. - * The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - */ -#define ENET_MACCFG_LM_MASK (0x1000U) -#define ENET_MACCFG_LM_SHIFT (12U) -#define ENET_MACCFG_LM_SET(x) (((uint32_t)(x) << ENET_MACCFG_LM_SHIFT) & ENET_MACCFG_LM_MASK) -#define ENET_MACCFG_LM_GET(x) (((uint32_t)(x) & ENET_MACCFG_LM_MASK) >> ENET_MACCFG_LM_SHIFT) - -/* - * DM (RW) - * - * Duplex Mode - * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - */ -#define ENET_MACCFG_DM_MASK (0x800U) -#define ENET_MACCFG_DM_SHIFT (11U) -#define ENET_MACCFG_DM_SET(x) (((uint32_t)(x) << ENET_MACCFG_DM_SHIFT) & ENET_MACCFG_DM_MASK) -#define ENET_MACCFG_DM_GET(x) (((uint32_t)(x) & ENET_MACCFG_DM_MASK) >> ENET_MACCFG_DM_SHIFT) - -/* - * IPC (RW) - * - * Checksum Offload - * When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. - * It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) - * of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. - * The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) - * and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). - * When this bit is reset, this function is disabled. - * When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - */ -#define ENET_MACCFG_IPC_MASK (0x400U) -#define ENET_MACCFG_IPC_SHIFT (10U) -#define ENET_MACCFG_IPC_SET(x) (((uint32_t)(x) << ENET_MACCFG_IPC_SHIFT) & ENET_MACCFG_IPC_MASK) -#define ENET_MACCFG_IPC_GET(x) (((uint32_t)(x) & ENET_MACCFG_IPC_MASK) >> ENET_MACCFG_IPC_SHIFT) - -/* - * DR (RW) - * - * Disable Retry - * When this bit is set, the MAC attempts only one transmission. - * When a collision occurs on the GMII or MII interface, - * the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. - * When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - */ -#define ENET_MACCFG_DR_MASK (0x200U) -#define ENET_MACCFG_DR_SHIFT (9U) -#define ENET_MACCFG_DR_SET(x) (((uint32_t)(x) << ENET_MACCFG_DR_SHIFT) & ENET_MACCFG_DR_MASK) -#define ENET_MACCFG_DR_GET(x) (((uint32_t)(x) & ENET_MACCFG_DR_MASK) >> ENET_MACCFG_DR_SHIFT) - -/* - * LUD (RW) - * - * Link Up or Down - * This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: - * - 0: Link Down - * - 1: Link Up - */ -#define ENET_MACCFG_LUD_MASK (0x100U) -#define ENET_MACCFG_LUD_SHIFT (8U) -#define ENET_MACCFG_LUD_SET(x) (((uint32_t)(x) << ENET_MACCFG_LUD_SHIFT) & ENET_MACCFG_LUD_MASK) -#define ENET_MACCFG_LUD_GET(x) (((uint32_t)(x) & ENET_MACCFG_LUD_MASK) >> ENET_MACCFG_LUD_SHIFT) - -/* - * ACS (RW) - * - * Automatic Pad or CRC Stripping - * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. - * All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. - * When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - */ -#define ENET_MACCFG_ACS_MASK (0x80U) -#define ENET_MACCFG_ACS_SHIFT (7U) -#define ENET_MACCFG_ACS_SET(x) (((uint32_t)(x) << ENET_MACCFG_ACS_SHIFT) & ENET_MACCFG_ACS_MASK) -#define ENET_MACCFG_ACS_GET(x) (((uint32_t)(x) & ENET_MACCFG_ACS_MASK) >> ENET_MACCFG_ACS_SHIFT) - -/* - * BL (RW) - * - * Back-Off Limit - * The Back-Off limit determines the random integer number (r) of slot time delays - * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. - * This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. - * - 00: k= min (n, 10) - * - 01: k = min (n, 8) - * - 10: k = min (n, 4) - * - 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - */ -#define ENET_MACCFG_BL_MASK (0x60U) -#define ENET_MACCFG_BL_SHIFT (5U) -#define ENET_MACCFG_BL_SET(x) (((uint32_t)(x) << ENET_MACCFG_BL_SHIFT) & ENET_MACCFG_BL_MASK) -#define ENET_MACCFG_BL_GET(x) (((uint32_t)(x) & ENET_MACCFG_BL_MASK) >> ENET_MACCFG_BL_SHIFT) - -/* - * DC (RW) - * - * Deferral Check - * When this bit is set, the deferral check function is enabled in the MAC. - * The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, - * when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - * If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - * the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, - * but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. - * For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, - * the transmitter transmits and collision happens. - * Because of collision, the transmitter needs to back off and then defer again after back off completion. - * In such a scenario, the deferral timer is reset to 0 and it is restarted. - */ -#define ENET_MACCFG_DC_MASK (0x10U) -#define ENET_MACCFG_DC_SHIFT (4U) -#define ENET_MACCFG_DC_SET(x) (((uint32_t)(x) << ENET_MACCFG_DC_SHIFT) & ENET_MACCFG_DC_MASK) -#define ENET_MACCFG_DC_GET(x) (((uint32_t)(x) & ENET_MACCFG_DC_MASK) >> ENET_MACCFG_DC_SHIFT) - -/* - * TE (RW) - * - * Transmitter Enable - * When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - * the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - */ -#define ENET_MACCFG_TE_MASK (0x8U) -#define ENET_MACCFG_TE_SHIFT (3U) -#define ENET_MACCFG_TE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TE_SHIFT) & ENET_MACCFG_TE_MASK) -#define ENET_MACCFG_TE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TE_MASK) >> ENET_MACCFG_TE_SHIFT) - -/* - * RE (RW) - * - * Receiver Enable - * When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, - * the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - */ -#define ENET_MACCFG_RE_MASK (0x4U) -#define ENET_MACCFG_RE_SHIFT (2U) -#define ENET_MACCFG_RE_SET(x) (((uint32_t)(x) << ENET_MACCFG_RE_SHIFT) & ENET_MACCFG_RE_MASK) -#define ENET_MACCFG_RE_GET(x) (((uint32_t)(x) & ENET_MACCFG_RE_MASK) >> ENET_MACCFG_RE_SHIFT) - -/* - * PRELEN (RW) - * - * Preamble Length for Transmit frames - * These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - * The preamble reduction occurs only when the MAC is operating in the full-duplex mode. - * - 2'b00: 7 bytes of preamble - * - 2'b01: 5 bytes of preamble - * - 2'b10: 3 bytes of preamble - * - 2'b11: Reserved - */ -#define ENET_MACCFG_PRELEN_MASK (0x3U) -#define ENET_MACCFG_PRELEN_SHIFT (0U) -#define ENET_MACCFG_PRELEN_SET(x) (((uint32_t)(x) << ENET_MACCFG_PRELEN_SHIFT) & ENET_MACCFG_PRELEN_MASK) -#define ENET_MACCFG_PRELEN_GET(x) (((uint32_t)(x) & ENET_MACCFG_PRELEN_MASK) >> ENET_MACCFG_PRELEN_SHIFT) - -/* Bitfield definition for register: MACFF */ -/* - * RA (RW) - * - * Receive All - * When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. - * The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, - * the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - */ -#define ENET_MACFF_RA_MASK (0x80000000UL) -#define ENET_MACFF_RA_SHIFT (31U) -#define ENET_MACFF_RA_SET(x) (((uint32_t)(x) << ENET_MACFF_RA_SHIFT) & ENET_MACFF_RA_MASK) -#define ENET_MACFF_RA_GET(x) (((uint32_t)(x) & ENET_MACFF_RA_MASK) >> ENET_MACFF_RA_SHIFT) - -/* - * DNTU (RW) - * - * Drop non-TCP/UDP over IP Frames - * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. - * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - */ -#define ENET_MACFF_DNTU_MASK (0x200000UL) -#define ENET_MACFF_DNTU_SHIFT (21U) -#define ENET_MACFF_DNTU_SET(x) (((uint32_t)(x) << ENET_MACFF_DNTU_SHIFT) & ENET_MACFF_DNTU_MASK) -#define ENET_MACFF_DNTU_GET(x) (((uint32_t)(x) & ENET_MACFF_DNTU_MASK) >> ENET_MACFF_DNTU_SHIFT) - -/* - * IPFE (RW) - * - * Layer 3 and Layer 4 Filter Enable - * When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, - * this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - */ -#define ENET_MACFF_IPFE_MASK (0x100000UL) -#define ENET_MACFF_IPFE_SHIFT (20U) -#define ENET_MACFF_IPFE_SET(x) (((uint32_t)(x) << ENET_MACFF_IPFE_SHIFT) & ENET_MACFF_IPFE_MASK) -#define ENET_MACFF_IPFE_GET(x) (((uint32_t)(x) & ENET_MACFF_IPFE_MASK) >> ENET_MACFF_IPFE_SHIFT) - -/* - * VTFE (RW) - * - * VLAN Tag Filter Enable - * When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. - * When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - */ -#define ENET_MACFF_VTFE_MASK (0x8000U) -#define ENET_MACFF_VTFE_SHIFT (15U) -#define ENET_MACFF_VTFE_SET(x) (((uint32_t)(x) << ENET_MACFF_VTFE_SHIFT) & ENET_MACFF_VTFE_MASK) -#define ENET_MACFF_VTFE_GET(x) (((uint32_t)(x) & ENET_MACFF_VTFE_MASK) >> ENET_MACFF_VTFE_SHIFT) - -/* - * HPF (RW) - * - * Hash or Perfect Filter - * When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. - * When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - */ -#define ENET_MACFF_HPF_MASK (0x400U) -#define ENET_MACFF_HPF_SHIFT (10U) -#define ENET_MACFF_HPF_SET(x) (((uint32_t)(x) << ENET_MACFF_HPF_SHIFT) & ENET_MACFF_HPF_MASK) -#define ENET_MACFF_HPF_GET(x) (((uint32_t)(x) & ENET_MACFF_HPF_MASK) >> ENET_MACFF_HPF_SHIFT) - -/* - * SAF (RW) - * - * Source Address Filter Enable - * When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - * the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - */ -#define ENET_MACFF_SAF_MASK (0x200U) -#define ENET_MACFF_SAF_SHIFT (9U) -#define ENET_MACFF_SAF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAF_SHIFT) & ENET_MACFF_SAF_MASK) -#define ENET_MACFF_SAF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAF_MASK) >> ENET_MACFF_SAF_SHIFT) - -/* - * SAIF (RW) - * - * SA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. - * When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - */ -#define ENET_MACFF_SAIF_MASK (0x100U) -#define ENET_MACFF_SAIF_SHIFT (8U) -#define ENET_MACFF_SAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAIF_SHIFT) & ENET_MACFF_SAIF_MASK) -#define ENET_MACFF_SAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAIF_MASK) >> ENET_MACFF_SAIF_SHIFT) - -/* - * PCF (RW) - * - * Pass Control Frames - * These bits control the forwarding of all control frames (including unicast and multicast Pause frames). - * - 00: MAC filters all control frames from reaching the application. - * - 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. - * - 10: MAC forwards all control frames to application even if they fail the Address Filter. - * - 11: MAC forwards control frames that pass the Address Filter. - * The following conditions should be true for the Pause frames processing: - * - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - * - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - * - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. - * Note: This field should be set to 01 only when the Condition 1 is true, - * that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. - * Otherwise, the Pause frame filtering may be inconsistent. - * When Condition 1 is false, the Pause frames are considered as generic control frames. - * Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, - * you should set the PCF field to 10 or 11 (as required by the application). - */ -#define ENET_MACFF_PCF_MASK (0xC0U) -#define ENET_MACFF_PCF_SHIFT (6U) -#define ENET_MACFF_PCF_SET(x) (((uint32_t)(x) << ENET_MACFF_PCF_SHIFT) & ENET_MACFF_PCF_MASK) -#define ENET_MACFF_PCF_GET(x) (((uint32_t)(x) & ENET_MACFF_PCF_MASK) >> ENET_MACFF_PCF_SHIFT) - -/* - * DBF (RW) - * - * Disable Broadcast Frames - * When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. - * When this bit is reset, the AFM module passes all received broadcast frames. - */ -#define ENET_MACFF_DBF_MASK (0x20U) -#define ENET_MACFF_DBF_SHIFT (5U) -#define ENET_MACFF_DBF_SET(x) (((uint32_t)(x) << ENET_MACFF_DBF_SHIFT) & ENET_MACFF_DBF_MASK) -#define ENET_MACFF_DBF_GET(x) (((uint32_t)(x) & ENET_MACFF_DBF_MASK) >> ENET_MACFF_DBF_SHIFT) - -/* - * PM (RW) - * - * Pass All Multicast - * When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. - * When reset, filtering of multicast frame depends on HMC bit. - */ -#define ENET_MACFF_PM_MASK (0x10U) -#define ENET_MACFF_PM_SHIFT (4U) -#define ENET_MACFF_PM_SET(x) (((uint32_t)(x) << ENET_MACFF_PM_SHIFT) & ENET_MACFF_PM_MASK) -#define ENET_MACFF_PM_GET(x) (((uint32_t)(x) & ENET_MACFF_PM_MASK) >> ENET_MACFF_PM_SHIFT) - -/* - * DAIF (RW) - * - * DA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. - * When reset, normal filtering of frames is performed. - */ -#define ENET_MACFF_DAIF_MASK (0x8U) -#define ENET_MACFF_DAIF_SHIFT (3U) -#define ENET_MACFF_DAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_DAIF_SHIFT) & ENET_MACFF_DAIF_MASK) -#define ENET_MACFF_DAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_DAIF_MASK) >> ENET_MACFF_DAIF_SHIFT) - -/* - * HMC (RW) - * - * Hash Multicast - * When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, - * the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HMC_MASK (0x4U) -#define ENET_MACFF_HMC_SHIFT (2U) -#define ENET_MACFF_HMC_SET(x) (((uint32_t)(x) << ENET_MACFF_HMC_SHIFT) & ENET_MACFF_HMC_MASK) -#define ENET_MACFF_HMC_GET(x) (((uint32_t)(x) & ENET_MACFF_HMC_MASK) >> ENET_MACFF_HMC_SHIFT) - -/* - * HUC (RW) - * - * Hash Unicast - * When set, the MAC performs destination address filtering of unicast frames according to the hash table. - * When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HUC_MASK (0x2U) -#define ENET_MACFF_HUC_SHIFT (1U) -#define ENET_MACFF_HUC_SET(x) (((uint32_t)(x) << ENET_MACFF_HUC_SHIFT) & ENET_MACFF_HUC_MASK) -#define ENET_MACFF_HUC_GET(x) (((uint32_t)(x) & ENET_MACFF_HUC_MASK) >> ENET_MACFF_HUC_SHIFT) - -/* - * PR (RW) - * - * Promiscuous Mode - * When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - * The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - */ -#define ENET_MACFF_PR_MASK (0x1U) -#define ENET_MACFF_PR_SHIFT (0U) -#define ENET_MACFF_PR_SET(x) (((uint32_t)(x) << ENET_MACFF_PR_SHIFT) & ENET_MACFF_PR_MASK) -#define ENET_MACFF_PR_GET(x) (((uint32_t)(x) & ENET_MACFF_PR_MASK) >> ENET_MACFF_PR_SHIFT) - -/* Bitfield definition for register: HASH_H */ -/* - * HTH (RW) - * - * Hash Table High - * This field contains the upper 32 bits of the Hash table. - */ -#define ENET_HASH_H_HTH_MASK (0xFFFFFFFFUL) -#define ENET_HASH_H_HTH_SHIFT (0U) -#define ENET_HASH_H_HTH_SET(x) (((uint32_t)(x) << ENET_HASH_H_HTH_SHIFT) & ENET_HASH_H_HTH_MASK) -#define ENET_HASH_H_HTH_GET(x) (((uint32_t)(x) & ENET_HASH_H_HTH_MASK) >> ENET_HASH_H_HTH_SHIFT) - -/* Bitfield definition for register: HASH_L */ -/* - * HTL (RW) - * - * Hash Table Low - * This field contains the lower 32 bits of the Hash table. - */ -#define ENET_HASH_L_HTL_MASK (0xFFFFFFFFUL) -#define ENET_HASH_L_HTL_SHIFT (0U) -#define ENET_HASH_L_HTL_SET(x) (((uint32_t)(x) << ENET_HASH_L_HTL_SHIFT) & ENET_HASH_L_HTL_MASK) -#define ENET_HASH_L_HTL_GET(x) (((uint32_t)(x) & ENET_HASH_L_HTL_MASK) >> ENET_HASH_L_HTL_SHIFT) - -/* Bitfield definition for register: GMII_ADDR */ -/* - * PA (RW) - * - * Physical Layer Address - * This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - */ -#define ENET_GMII_ADDR_PA_MASK (0xF800U) -#define ENET_GMII_ADDR_PA_SHIFT (11U) -#define ENET_GMII_ADDR_PA_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_PA_SHIFT) & ENET_GMII_ADDR_PA_MASK) -#define ENET_GMII_ADDR_PA_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_PA_MASK) >> ENET_GMII_ADDR_PA_SHIFT) - -/* - * GR (RW) - * - * GMII Register - * These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - */ -#define ENET_GMII_ADDR_GR_MASK (0x7C0U) -#define ENET_GMII_ADDR_GR_SHIFT (6U) -#define ENET_GMII_ADDR_GR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GR_SHIFT) & ENET_GMII_ADDR_GR_MASK) -#define ENET_GMII_ADDR_GR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GR_MASK) >> ENET_GMII_ADDR_GR_SHIFT) - -/* - * CR (RW) - * - * CSR Clock Range - * The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. - * The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. - * The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) - * ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. - * - 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. - * - 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. - * - 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. - * - 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. - * - 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. - * - 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. - * - 0110, 0111: Reserved - * When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. - * For example, - * when CSR clock is of 100 MHz frequency and you program these bits as 1010, - * then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. - * Program the following values only if the interfacing chips support faster MDC clocks. - * - 1000: CSR clock/4 - * - 1001: CSR clock/6 - * - 1010: CSR clock/8 - * - 1011: CSR clock/10 - * - 1100: CSR clock/12 - * - 1101: CSR clock/14 - * - 1110: CSR clock/16 - * - 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - */ -#define ENET_GMII_ADDR_CR_MASK (0x3CU) -#define ENET_GMII_ADDR_CR_SHIFT (2U) -#define ENET_GMII_ADDR_CR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_CR_SHIFT) & ENET_GMII_ADDR_CR_MASK) -#define ENET_GMII_ADDR_CR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_CR_MASK) >> ENET_GMII_ADDR_CR_SHIFT) - -/* - * GW (RW) - * - * GMII Write - * When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, - * it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - */ -#define ENET_GMII_ADDR_GW_MASK (0x2U) -#define ENET_GMII_ADDR_GW_SHIFT (1U) -#define ENET_GMII_ADDR_GW_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GW_SHIFT) & ENET_GMII_ADDR_GW_MASK) -#define ENET_GMII_ADDR_GW_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GW_MASK) >> ENET_GMII_ADDR_GW_SHIFT) - -/* - * GB (RW) - * - * GMII Busy - * This bit should read logic 0 before writing to Register 4 and Register 5. - * During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - * Register 5 is invalid until this bit is cleared by the MAC. - * Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. - * Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. - * The subsequent read or write operation should happen only after the previous operation is complete. - * Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, - * there is no change in the functionality of this bit even when the PHY is not present. - */ -#define ENET_GMII_ADDR_GB_MASK (0x1U) -#define ENET_GMII_ADDR_GB_SHIFT (0U) -#define ENET_GMII_ADDR_GB_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GB_SHIFT) & ENET_GMII_ADDR_GB_MASK) -#define ENET_GMII_ADDR_GB_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GB_MASK) >> ENET_GMII_ADDR_GB_SHIFT) - -/* Bitfield definition for register: GMII_DATA */ -/* - * GD (RW) - * - * GMII Data - * This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation - * or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - */ -#define ENET_GMII_DATA_GD_MASK (0xFFFFU) -#define ENET_GMII_DATA_GD_SHIFT (0U) -#define ENET_GMII_DATA_GD_SET(x) (((uint32_t)(x) << ENET_GMII_DATA_GD_SHIFT) & ENET_GMII_DATA_GD_MASK) -#define ENET_GMII_DATA_GD_GET(x) (((uint32_t)(x) & ENET_GMII_DATA_GD_MASK) >> ENET_GMII_DATA_GD_SHIFT) - -/* Bitfield definition for register: FLOWCTRL */ -/* - * PT (RW) - * - * Pause Time - * This field holds the value to be used in the Pause Time field in the transmit control frame. - * If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - * then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - */ -#define ENET_FLOWCTRL_PT_MASK (0xFFFF0000UL) -#define ENET_FLOWCTRL_PT_SHIFT (16U) -#define ENET_FLOWCTRL_PT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PT_SHIFT) & ENET_FLOWCTRL_PT_MASK) -#define ENET_FLOWCTRL_PT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PT_MASK) >> ENET_FLOWCTRL_PT_SHIFT) - -/* - * DZPQ (RW) - * - * Disable Zero-Quanta Pause - * When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of - * the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). - * When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - */ -#define ENET_FLOWCTRL_DZPQ_MASK (0x80U) -#define ENET_FLOWCTRL_DZPQ_SHIFT (7U) -#define ENET_FLOWCTRL_DZPQ_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_DZPQ_SHIFT) & ENET_FLOWCTRL_DZPQ_MASK) -#define ENET_FLOWCTRL_DZPQ_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_DZPQ_MASK) >> ENET_FLOWCTRL_DZPQ_SHIFT) - -/* - * PLT (RW) - * - * Pause Low Threshold - * This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. - * The threshold values should be always less than the Pause Time configured in Bits[31:16]. - * For example, if PT = 100H (256 slot-times), and PLT = 01, - * then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. - * The following list provides the threshold values for different values: - * - 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). - * - 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). - * - 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). - * - 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - */ -#define ENET_FLOWCTRL_PLT_MASK (0x30U) -#define ENET_FLOWCTRL_PLT_SHIFT (4U) -#define ENET_FLOWCTRL_PLT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PLT_SHIFT) & ENET_FLOWCTRL_PLT_MASK) -#define ENET_FLOWCTRL_PLT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PLT_MASK) >> ENET_FLOWCTRL_PLT_SHIFT) - -/* - * UP (RW) - * - * Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. - * When this bit is set, the MAC can also detect Pause frames with unicast address of the station. - * This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. - * When this bit is reset, the MAC only detects Pause frames with unique multicast address. - */ -#define ENET_FLOWCTRL_UP_MASK (0x8U) -#define ENET_FLOWCTRL_UP_SHIFT (3U) -#define ENET_FLOWCTRL_UP_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_UP_SHIFT) & ENET_FLOWCTRL_UP_MASK) -#define ENET_FLOWCTRL_UP_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_UP_MASK) >> ENET_FLOWCTRL_UP_SHIFT) - -/* - * RFE (RW) - * - * Receive Flow Control Enable - * When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - */ -#define ENET_FLOWCTRL_RFE_MASK (0x4U) -#define ENET_FLOWCTRL_RFE_SHIFT (2U) -#define ENET_FLOWCTRL_RFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_RFE_SHIFT) & ENET_FLOWCTRL_RFE_MASK) -#define ENET_FLOWCTRL_RFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_RFE_MASK) >> ENET_FLOWCTRL_RFE_SHIFT) - -/* - * TFE (RW) - * - * Transmit Flow Control Enable - * In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. - * When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. - * In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - */ -#define ENET_FLOWCTRL_TFE_MASK (0x2U) -#define ENET_FLOWCTRL_TFE_SHIFT (1U) -#define ENET_FLOWCTRL_TFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_TFE_SHIFT) & ENET_FLOWCTRL_TFE_MASK) -#define ENET_FLOWCTRL_TFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_TFE_MASK) >> ENET_FLOWCTRL_TFE_SHIFT) - -/* - * FCB_BPA (RW) - * - * Flow Control Busy or Backpressure Activate - * This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. - * In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - * To initiate a Pause frame, the Application must set this bit to 1'b1. - * During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. - * After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. - * The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, - * when this bit is set (and TFE is set), then backpressure is asserted by the MAC. - * During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. - * This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. - * When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - */ -#define ENET_FLOWCTRL_FCB_BPA_MASK (0x1U) -#define ENET_FLOWCTRL_FCB_BPA_SHIFT (0U) -#define ENET_FLOWCTRL_FCB_BPA_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_FCB_BPA_SHIFT) & ENET_FLOWCTRL_FCB_BPA_MASK) -#define ENET_FLOWCTRL_FCB_BPA_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_FCB_BPA_MASK) >> ENET_FLOWCTRL_FCB_BPA_SHIFT) - -/* Bitfield definition for register: VLAN_TAG */ -/* - * VTHM (RW) - * - * VLAN Tag Hash Table Match Enable - * When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). - * A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. - * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, - * the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - */ -#define ENET_VLAN_TAG_VTHM_MASK (0x80000UL) -#define ENET_VLAN_TAG_VTHM_SHIFT (19U) -#define ENET_VLAN_TAG_VTHM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTHM_SHIFT) & ENET_VLAN_TAG_VTHM_MASK) -#define ENET_VLAN_TAG_VTHM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTHM_MASK) >> ENET_VLAN_TAG_VTHM_SHIFT) - -/* - * ESVL (RW) - * - * Enable S-VLAN - * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - */ -#define ENET_VLAN_TAG_ESVL_MASK (0x40000UL) -#define ENET_VLAN_TAG_ESVL_SHIFT (18U) -#define ENET_VLAN_TAG_ESVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ESVL_SHIFT) & ENET_VLAN_TAG_ESVL_MASK) -#define ENET_VLAN_TAG_ESVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ESVL_MASK) >> ENET_VLAN_TAG_ESVL_SHIFT) - -/* - * VTIM (RW) - * - * VLAN Tag Inverse Match Enable - * When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - * The frames with matched VLAN Tag are marked as matched. - */ -#define ENET_VLAN_TAG_VTIM_MASK (0x20000UL) -#define ENET_VLAN_TAG_VTIM_SHIFT (17U) -#define ENET_VLAN_TAG_VTIM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTIM_SHIFT) & ENET_VLAN_TAG_VTIM_MASK) -#define ENET_VLAN_TAG_VTIM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTIM_MASK) >> ENET_VLAN_TAG_VTIM_SHIFT) - -/* - * ETV (RW) - * - * Enable 12-Bit VLAN Tag Comparison - * When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - * Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, - * only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. - * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - */ -#define ENET_VLAN_TAG_ETV_MASK (0x10000UL) -#define ENET_VLAN_TAG_ETV_SHIFT (16U) -#define ENET_VLAN_TAG_ETV_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ETV_SHIFT) & ENET_VLAN_TAG_ETV_MASK) -#define ENET_VLAN_TAG_ETV_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ETV_MASK) >> ENET_VLAN_TAG_ETV_SHIFT) - -/* - * VL (RW) - * - * VLAN Tag Identifier for Receive Frames - * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. - * The following list describes the bits of this field: - * - Bits [15:13]: User Priority - * - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - * - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - * and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - */ -#define ENET_VLAN_TAG_VL_MASK (0xFFFFU) -#define ENET_VLAN_TAG_VL_SHIFT (0U) -#define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) -#define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) - -/* Bitfield definition for register: RWKFRMFILT */ -/* - * WKUPFRMFILT (RW) - * - * This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). - * The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. - * The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. - * Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - * Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - */ -#define ENET_RWKFRMFILT_WKUPFRMFILT_MASK (0xFFFFFFFFUL) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT (0U) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SET(x) (((uint32_t)(x) << ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) -#define ENET_RWKFRMFILT_WKUPFRMFILT_GET(x) (((uint32_t)(x) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) >> ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) - -/* Bitfield definition for register: PMT_CSR */ -/* - * RWKFILTRST (RW) - * - * Remote Wake-Up Frame Filter Register Pointer Reset - * When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - */ -#define ENET_PMT_CSR_RWKFILTRST_MASK (0x80000000UL) -#define ENET_PMT_CSR_RWKFILTRST_SHIFT (31U) -#define ENET_PMT_CSR_RWKFILTRST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKFILTRST_SHIFT) & ENET_PMT_CSR_RWKFILTRST_MASK) -#define ENET_PMT_CSR_RWKFILTRST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKFILTRST_MASK) >> ENET_PMT_CSR_RWKFILTRST_SHIFT) - -/* - * RWKPTR (RW) - * - * Remote Wake-up FIFO Pointer - * This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, - * the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - * The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - */ -#define ENET_PMT_CSR_RWKPTR_MASK (0x1F000000UL) -#define ENET_PMT_CSR_RWKPTR_SHIFT (24U) -#define ENET_PMT_CSR_RWKPTR_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPTR_SHIFT) & ENET_PMT_CSR_RWKPTR_MASK) -#define ENET_PMT_CSR_RWKPTR_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPTR_MASK) >> ENET_PMT_CSR_RWKPTR_SHIFT) - -/* - * GLBLUCAST (RW) - * - * Global Unicast - * When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - */ -#define ENET_PMT_CSR_GLBLUCAST_MASK (0x200U) -#define ENET_PMT_CSR_GLBLUCAST_SHIFT (9U) -#define ENET_PMT_CSR_GLBLUCAST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_GLBLUCAST_SHIFT) & ENET_PMT_CSR_GLBLUCAST_MASK) -#define ENET_PMT_CSR_GLBLUCAST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_GLBLUCAST_MASK) >> ENET_PMT_CSR_GLBLUCAST_SHIFT) - -/* - * RWKPRCVD (RW) - * - * Remote Wake-Up Frame Received - * When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_RWKPRCVD_MASK (0x40U) -#define ENET_PMT_CSR_RWKPRCVD_SHIFT (6U) -#define ENET_PMT_CSR_RWKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPRCVD_SHIFT) & ENET_PMT_CSR_RWKPRCVD_MASK) -#define ENET_PMT_CSR_RWKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPRCVD_MASK) >> ENET_PMT_CSR_RWKPRCVD_SHIFT) - -/* - * MGKPRCVD (RW) - * - * Magic Packet Received - * When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_MGKPRCVD_MASK (0x20U) -#define ENET_PMT_CSR_MGKPRCVD_SHIFT (5U) -#define ENET_PMT_CSR_MGKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPRCVD_SHIFT) & ENET_PMT_CSR_MGKPRCVD_MASK) -#define ENET_PMT_CSR_MGKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPRCVD_MASK) >> ENET_PMT_CSR_MGKPRCVD_SHIFT) - -/* - * RWKPKTEN (RW) - * - * Remote Wake-Up Frame Enable - * When set, enables generation of a power management event because of remote wake-up frame reception. - */ -#define ENET_PMT_CSR_RWKPKTEN_MASK (0x4U) -#define ENET_PMT_CSR_RWKPKTEN_SHIFT (2U) -#define ENET_PMT_CSR_RWKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPKTEN_SHIFT) & ENET_PMT_CSR_RWKPKTEN_MASK) -#define ENET_PMT_CSR_RWKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPKTEN_MASK) >> ENET_PMT_CSR_RWKPKTEN_SHIFT) - -/* - * MGKPKTEN (RW) - * - * Magic Packet Enable - * When set, enables generation of a power management event because of magic packet reception. - */ -#define ENET_PMT_CSR_MGKPKTEN_MASK (0x2U) -#define ENET_PMT_CSR_MGKPKTEN_SHIFT (1U) -#define ENET_PMT_CSR_MGKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPKTEN_SHIFT) & ENET_PMT_CSR_MGKPKTEN_MASK) -#define ENET_PMT_CSR_MGKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPKTEN_MASK) >> ENET_PMT_CSR_MGKPKTEN_SHIFT) - -/* - * PWRDWN (RW) - * - * Power Down - * When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. - * This bit is then self-cleared and the power-down mode is disabled. - * The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. - * The frames, received by the MAC after this bit is cleared, are forwarded to the application. - * This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. - * Note: You can gate-off the CSR clock during the power-down mode. - * However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - */ -#define ENET_PMT_CSR_PWRDWN_MASK (0x1U) -#define ENET_PMT_CSR_PWRDWN_SHIFT (0U) -#define ENET_PMT_CSR_PWRDWN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_PWRDWN_SHIFT) & ENET_PMT_CSR_PWRDWN_MASK) -#define ENET_PMT_CSR_PWRDWN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_PWRDWN_MASK) >> ENET_PMT_CSR_PWRDWN_SHIFT) - -/* Bitfield definition for register: LPI_CSR */ -/* - * LPITXA (RW) - * - * LPI TX Automate - * This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. - * This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, - * the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. - * The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - * In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. - * If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), - * when the MAC is in the LPI mode, the MAC exits the LPI mode. - * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - */ -#define ENET_LPI_CSR_LPITXA_MASK (0x80000UL) -#define ENET_LPI_CSR_LPITXA_SHIFT (19U) -#define ENET_LPI_CSR_LPITXA_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPITXA_SHIFT) & ENET_LPI_CSR_LPITXA_MASK) -#define ENET_LPI_CSR_LPITXA_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPITXA_MASK) >> ENET_LPI_CSR_LPITXA_SHIFT) - -/* - * PLSEN (RW) - * - * PHY Link Status Enable - * This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. - * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - * When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - */ -#define ENET_LPI_CSR_PLSEN_MASK (0x40000UL) -#define ENET_LPI_CSR_PLSEN_SHIFT (18U) -#define ENET_LPI_CSR_PLSEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLSEN_SHIFT) & ENET_LPI_CSR_PLSEN_MASK) -#define ENET_LPI_CSR_PLSEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLSEN_MASK) >> ENET_LPI_CSR_PLSEN_SHIFT) - -/* - * PLS (RW) - * - * PHY Link Status - * This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. - * When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - */ -#define ENET_LPI_CSR_PLS_MASK (0x20000UL) -#define ENET_LPI_CSR_PLS_SHIFT (17U) -#define ENET_LPI_CSR_PLS_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLS_SHIFT) & ENET_LPI_CSR_PLS_MASK) -#define ENET_LPI_CSR_PLS_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLS_MASK) >> ENET_LPI_CSR_PLS_SHIFT) - -/* - * LPIEN (RW) - * - * LPI Enable - * When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. - * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - */ -#define ENET_LPI_CSR_LPIEN_MASK (0x10000UL) -#define ENET_LPI_CSR_LPIEN_SHIFT (16U) -#define ENET_LPI_CSR_LPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPIEN_SHIFT) & ENET_LPI_CSR_LPIEN_MASK) -#define ENET_LPI_CSR_LPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPIEN_MASK) >> ENET_LPI_CSR_LPIEN_SHIFT) - -/* - * RLPIST (RW) - * - * Receive LPI State - * When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_RLPIST_MASK (0x200U) -#define ENET_LPI_CSR_RLPIST_SHIFT (9U) -#define ENET_LPI_CSR_RLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIST_SHIFT) & ENET_LPI_CSR_RLPIST_MASK) -#define ENET_LPI_CSR_RLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIST_MASK) >> ENET_LPI_CSR_RLPIST_SHIFT) - -/* - * TLPIST (RW) - * - * Transmit LPI State - * When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_TLPIST_MASK (0x100U) -#define ENET_LPI_CSR_TLPIST_SHIFT (8U) -#define ENET_LPI_CSR_TLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIST_SHIFT) & ENET_LPI_CSR_TLPIST_MASK) -#define ENET_LPI_CSR_TLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIST_MASK) >> ENET_LPI_CSR_TLPIST_SHIFT) - -/* - * RLPIEX (RW) - * - * Receive LPI Exit - * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. - * This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEX_MASK (0x8U) -#define ENET_LPI_CSR_RLPIEX_SHIFT (3U) -#define ENET_LPI_CSR_RLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEX_SHIFT) & ENET_LPI_CSR_RLPIEX_MASK) -#define ENET_LPI_CSR_RLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEX_MASK) >> ENET_LPI_CSR_RLPIEX_SHIFT) - -/* - * RLPIEN (RW) - * - * Receive LPI Entry - * When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEN_MASK (0x4U) -#define ENET_LPI_CSR_RLPIEN_SHIFT (2U) -#define ENET_LPI_CSR_RLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEN_SHIFT) & ENET_LPI_CSR_RLPIEN_MASK) -#define ENET_LPI_CSR_RLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEN_MASK) >> ENET_LPI_CSR_RLPIEN_SHIFT) - -/* - * TLPIEX (RW) - * - * Transmit LPI Exit - * When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEX_MASK (0x2U) -#define ENET_LPI_CSR_TLPIEX_SHIFT (1U) -#define ENET_LPI_CSR_TLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEX_SHIFT) & ENET_LPI_CSR_TLPIEX_MASK) -#define ENET_LPI_CSR_TLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEX_MASK) >> ENET_LPI_CSR_TLPIEX_SHIFT) - -/* - * TLPIEN (RW) - * - * Transmit LPI Entry - * When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEN_MASK (0x1U) -#define ENET_LPI_CSR_TLPIEN_SHIFT (0U) -#define ENET_LPI_CSR_TLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEN_SHIFT) & ENET_LPI_CSR_TLPIEN_MASK) -#define ENET_LPI_CSR_TLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEN_MASK) >> ENET_LPI_CSR_TLPIEN_SHIFT) - -/* Bitfield definition for register: LPI_TCR */ -/* - * LST (RW) - * - * LPI LS TIMER - * This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - * The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. - * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - */ -#define ENET_LPI_TCR_LST_MASK (0x3FF0000UL) -#define ENET_LPI_TCR_LST_SHIFT (16U) -#define ENET_LPI_TCR_LST_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_LST_SHIFT) & ENET_LPI_TCR_LST_MASK) -#define ENET_LPI_TCR_LST_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_LST_MASK) >> ENET_LPI_TCR_LST_SHIFT) - -/* - * TWT (RW) - * - * LPI TW TIMER - * This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - * the LPI pattern to the PHY and before it resumes the normal transmission. - * The TLPIEX status bit is set after the expiry of this timer. - */ -#define ENET_LPI_TCR_TWT_MASK (0xFFFFU) -#define ENET_LPI_TCR_TWT_SHIFT (0U) -#define ENET_LPI_TCR_TWT_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_TWT_SHIFT) & ENET_LPI_TCR_TWT_MASK) -#define ENET_LPI_TCR_TWT_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_TWT_MASK) >> ENET_LPI_TCR_TWT_SHIFT) - -/* Bitfield definition for register: INTR_STATUS */ -/* - * GPIIS (RO) - * - * GPI Interrupt Status - * When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - * of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. - * This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - * When the GPIO feature is not enabled, this bit is reserved. - */ -#define ENET_INTR_STATUS_GPIIS_MASK (0x800U) -#define ENET_INTR_STATUS_GPIIS_SHIFT (11U) -#define ENET_INTR_STATUS_GPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_GPIIS_MASK) >> ENET_INTR_STATUS_GPIIS_SHIFT) - -/* - * LPIIS (RO) - * - * LPI Interrupt Status - * When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. - * This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - */ -#define ENET_INTR_STATUS_LPIIS_MASK (0x400U) -#define ENET_INTR_STATUS_LPIIS_SHIFT (10U) -#define ENET_INTR_STATUS_LPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_LPIIS_MASK) >> ENET_INTR_STATUS_LPIIS_SHIFT) - -/* - * TSIS (RO) - * - * Timestamp Interrupt Status - * When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - * - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - * - There is an overflow in the seconds register. - * - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - */ -#define ENET_INTR_STATUS_TSIS_MASK (0x200U) -#define ENET_INTR_STATUS_TSIS_SHIFT (9U) -#define ENET_INTR_STATUS_TSIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_TSIS_MASK) >> ENET_INTR_STATUS_TSIS_SHIFT) - -/* - * MMCRXIPIS (RO) - * - * MMC Receive Checksum Offload Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIPIS_MASK (0x80U) -#define ENET_INTR_STATUS_MMCRXIPIS_SHIFT (7U) -#define ENET_INTR_STATUS_MMCRXIPIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIPIS_MASK) >> ENET_INTR_STATUS_MMCRXIPIS_SHIFT) - -/* - * MMCTXIS (RO) - * - * MMC Transmit Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCTXIS_MASK (0x40U) -#define ENET_INTR_STATUS_MMCTXIS_SHIFT (6U) -#define ENET_INTR_STATUS_MMCTXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCTXIS_MASK) >> ENET_INTR_STATUS_MMCTXIS_SHIFT) - -/* - * MMCRXIS (RO) - * - * MMC Receive Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIS_MASK (0x20U) -#define ENET_INTR_STATUS_MMCRXIS_SHIFT (5U) -#define ENET_INTR_STATUS_MMCRXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIS_MASK) >> ENET_INTR_STATUS_MMCRXIS_SHIFT) - -/* - * MMCIS (RO) - * - * MMC Interrupt Status - * This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - */ -#define ENET_INTR_STATUS_MMCIS_MASK (0x10U) -#define ENET_INTR_STATUS_MMCIS_SHIFT (4U) -#define ENET_INTR_STATUS_MMCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCIS_MASK) >> ENET_INTR_STATUS_MMCIS_SHIFT) - -/* - * PMTIS (RO) - * - * PMT Interrupt Status - * This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). - * This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - */ -#define ENET_INTR_STATUS_PMTIS_MASK (0x8U) -#define ENET_INTR_STATUS_PMTIS_SHIFT (3U) -#define ENET_INTR_STATUS_PMTIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PMTIS_MASK) >> ENET_INTR_STATUS_PMTIS_SHIFT) - -/* - * PCSANCIS (RO) - * - * PCS Auto-Negotiation Complete - * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation to the AN Status register. - */ -#define ENET_INTR_STATUS_PCSANCIS_MASK (0x4U) -#define ENET_INTR_STATUS_PCSANCIS_SHIFT (2U) -#define ENET_INTR_STATUS_PCSANCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSANCIS_MASK) >> ENET_INTR_STATUS_PCSANCIS_SHIFT) - -/* - * PCSLCHGIS (RO) - * - * PCS Link Status Changed - * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation on the AN Status register. - */ -#define ENET_INTR_STATUS_PCSLCHGIS_MASK (0x2U) -#define ENET_INTR_STATUS_PCSLCHGIS_SHIFT (1U) -#define ENET_INTR_STATUS_PCSLCHGIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSLCHGIS_MASK) >> ENET_INTR_STATUS_PCSLCHGIS_SHIFT) - -/* - * RGSMIIIS (RO) - * - * RGMII or SMII Interrupt Status - * This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). - * This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - */ -#define ENET_INTR_STATUS_RGSMIIIS_MASK (0x1U) -#define ENET_INTR_STATUS_RGSMIIIS_SHIFT (0U) -#define ENET_INTR_STATUS_RGSMIIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_RGSMIIIS_MASK) >> ENET_INTR_STATUS_RGSMIIIS_SHIFT) - -/* Bitfield definition for register: INTR_MASK */ -/* - * LPIIM (RW) - * - * LPI Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_LPIIM_MASK (0x400U) -#define ENET_INTR_MASK_LPIIM_SHIFT (10U) -#define ENET_INTR_MASK_LPIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_LPIIM_SHIFT) & ENET_INTR_MASK_LPIIM_MASK) -#define ENET_INTR_MASK_LPIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_LPIIM_MASK) >> ENET_INTR_MASK_LPIIM_SHIFT) - -/* - * TSIM (RW) - * - * Timestamp Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_TSIM_MASK (0x200U) -#define ENET_INTR_MASK_TSIM_SHIFT (9U) -#define ENET_INTR_MASK_TSIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_TSIM_SHIFT) & ENET_INTR_MASK_TSIM_MASK) -#define ENET_INTR_MASK_TSIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_TSIM_MASK) >> ENET_INTR_MASK_TSIM_SHIFT) - -/* - * PMTIM (RW) - * - * PMT Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PMTIM_MASK (0x8U) -#define ENET_INTR_MASK_PMTIM_SHIFT (3U) -#define ENET_INTR_MASK_PMTIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PMTIM_SHIFT) & ENET_INTR_MASK_PMTIM_MASK) -#define ENET_INTR_MASK_PMTIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PMTIM_MASK) >> ENET_INTR_MASK_PMTIM_SHIFT) - -/* - * PCSANCIM (RW) - * - * PCS AN Completion Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSANCIM_MASK (0x4U) -#define ENET_INTR_MASK_PCSANCIM_SHIFT (2U) -#define ENET_INTR_MASK_PCSANCIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSANCIM_SHIFT) & ENET_INTR_MASK_PCSANCIM_MASK) -#define ENET_INTR_MASK_PCSANCIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSANCIM_MASK) >> ENET_INTR_MASK_PCSANCIM_SHIFT) - -/* - * PCSLCHGIM (RW) - * - * PCS Link Status Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSLCHGIM_MASK (0x2U) -#define ENET_INTR_MASK_PCSLCHGIM_SHIFT (1U) -#define ENET_INTR_MASK_PCSLCHGIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSLCHGIM_SHIFT) & ENET_INTR_MASK_PCSLCHGIM_MASK) -#define ENET_INTR_MASK_PCSLCHGIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSLCHGIM_MASK) >> ENET_INTR_MASK_PCSLCHGIM_SHIFT) - -/* - * RGSMIIIM (RW) - * - * RGMII or SMII Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_RGSMIIIM_MASK (0x1U) -#define ENET_INTR_MASK_RGSMIIIM_SHIFT (0U) -#define ENET_INTR_MASK_RGSMIIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_RGSMIIIM_SHIFT) & ENET_INTR_MASK_RGSMIIIM_MASK) -#define ENET_INTR_MASK_RGSMIIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_RGSMIIIM_MASK) >> ENET_INTR_MASK_RGSMIIIM_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_HIGH */ -/* - * AE (RO) - * - * Address Enable - * This bit is RO. The bit value is fixed at 1. - */ -#define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_0_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_AE_MASK) >> ENET_MAC_ADDR_0_HIGH_AE_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address0 [47:32] - * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_LOW */ -/* - * ADDRLO (RW) - * - * MAC Address0 [31:0] - * This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: HIGH */ -/* - * AE (RW) - * - * Address Enable - * When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - */ -#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_AE_SHIFT) & ENET_MAC_ADDR_HIGH_AE_MASK) -#define ENET_MAC_ADDR_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_AE_MASK) >> ENET_MAC_ADDR_HIGH_AE_SHIFT) - -/* - * SA (RW) - * - * Source Address - * When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - */ -#define ENET_MAC_ADDR_HIGH_SA_MASK (0x40000000UL) -#define ENET_MAC_ADDR_HIGH_SA_SHIFT (30U) -#define ENET_MAC_ADDR_HIGH_SA_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_SA_SHIFT) & ENET_MAC_ADDR_HIGH_SA_MASK) -#define ENET_MAC_ADDR_HIGH_SA_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_SA_MASK) >> ENET_MAC_ADDR_HIGH_SA_SHIFT) - -/* - * MBC (RW) - * - * Mask Byte Control - * These bits are mask control bits for comparison of each of the MAC Address bytes. - * When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. - * Each bit controls the masking of the bytes as follows: - * - Bit 29: Register 18[15:8] - * - Bit 28: Register 18[7:0] - * - Bit 27: Register 19[31:24] - - * ... - * - Bit 24: Register 19[7:0] - * You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - */ -#define ENET_MAC_ADDR_HIGH_MBC_MASK (0x3F000000UL) -#define ENET_MAC_ADDR_HIGH_MBC_SHIFT (24U) -#define ENET_MAC_ADDR_HIGH_MBC_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_MBC_SHIFT) & ENET_MAC_ADDR_HIGH_MBC_MASK) -#define ENET_MAC_ADDR_HIGH_MBC_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_MBC_MASK) >> ENET_MAC_ADDR_HIGH_MBC_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address1 [47:32] - * This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - */ -#define ENET_MAC_ADDR_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: LOW */ -/* - * ADDRLO (RW) - * - * MAC Address1 [31:0] - * This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - */ -#define ENET_MAC_ADDR_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register: XMII_CSR */ -/* - * FALSCARDET (RW) - * - * False Carrier Detected - * This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_FALSCARDET_MASK (0x20U) -#define ENET_XMII_CSR_FALSCARDET_SHIFT (5U) -#define ENET_XMII_CSR_FALSCARDET_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_FALSCARDET_SHIFT) & ENET_XMII_CSR_FALSCARDET_MASK) -#define ENET_XMII_CSR_FALSCARDET_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_FALSCARDET_MASK) >> ENET_XMII_CSR_FALSCARDET_SHIFT) - -/* - * JABTO (RW) - * - * Jabber Timeout - * This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_JABTO_MASK (0x10U) -#define ENET_XMII_CSR_JABTO_SHIFT (4U) -#define ENET_XMII_CSR_JABTO_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_JABTO_SHIFT) & ENET_XMII_CSR_JABTO_MASK) -#define ENET_XMII_CSR_JABTO_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_JABTO_MASK) >> ENET_XMII_CSR_JABTO_SHIFT) - -/* - * LNKSTS (RW) - * - * Link Status - * This bit indicates whether the link between the local PHY and the remote PHY is up or down. - * It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. - * The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - */ -#define ENET_XMII_CSR_LNKSTS_MASK (0x8U) -#define ENET_XMII_CSR_LNKSTS_SHIFT (3U) -#define ENET_XMII_CSR_LNKSTS_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSTS_SHIFT) & ENET_XMII_CSR_LNKSTS_MASK) -#define ENET_XMII_CSR_LNKSTS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSTS_MASK) >> ENET_XMII_CSR_LNKSTS_SHIFT) - -/* - * LNKSPEED (RW) - * - * Link Speed - * This bit indicates the current speed of the link: - * - 00: 2.5 MHz - * - 01: 25 MHz - * - 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - */ -#define ENET_XMII_CSR_LNKSPEED_MASK (0x6U) -#define ENET_XMII_CSR_LNKSPEED_SHIFT (1U) -#define ENET_XMII_CSR_LNKSPEED_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSPEED_SHIFT) & ENET_XMII_CSR_LNKSPEED_MASK) -#define ENET_XMII_CSR_LNKSPEED_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSPEED_MASK) >> ENET_XMII_CSR_LNKSPEED_SHIFT) - -/* - * LNKMOD (RW) - * - * Link Mode - * This bit indicates the current mode of operation of the link: - * - 1’b0: Half-duplex mode - * - 1’b1: Full-duplex mode - */ -#define ENET_XMII_CSR_LNKMOD_MASK (0x1U) -#define ENET_XMII_CSR_LNKMOD_SHIFT (0U) -#define ENET_XMII_CSR_LNKMOD_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKMOD_SHIFT) & ENET_XMII_CSR_LNKMOD_MASK) -#define ENET_XMII_CSR_LNKMOD_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKMOD_MASK) >> ENET_XMII_CSR_LNKMOD_SHIFT) - -/* Bitfield definition for register: WDOG_WTO */ -/* - * PWE (RW) - * - * Programmable Watchdog Enable - * When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. - * When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - */ -#define ENET_WDOG_WTO_PWE_MASK (0x10000UL) -#define ENET_WDOG_WTO_PWE_SHIFT (16U) -#define ENET_WDOG_WTO_PWE_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_PWE_SHIFT) & ENET_WDOG_WTO_PWE_MASK) -#define ENET_WDOG_WTO_PWE_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_PWE_MASK) >> ENET_WDOG_WTO_PWE_SHIFT) - -/* - * WTO (RW) - * - * Watchdog Timeout - * When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * this field is used as watchdog timeout for a received frame. - * If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. - * Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). - * Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - */ -#define ENET_WDOG_WTO_WTO_MASK (0x3FFFU) -#define ENET_WDOG_WTO_WTO_SHIFT (0U) -#define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) -#define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) - -/* Bitfield definition for register: MMC_CNTRL */ -/* - * UCDBC (RW) - * - * Update MMC Counters for Dropped Broadcast Frames - * When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - * When reset, the MMC Counters are not updated for dropped Broadcast frames. - */ -#define ENET_MMC_CNTRL_UCDBC_MASK (0x100U) -#define ENET_MMC_CNTRL_UCDBC_SHIFT (8U) -#define ENET_MMC_CNTRL_UCDBC_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_UCDBC_SHIFT) & ENET_MMC_CNTRL_UCDBC_MASK) -#define ENET_MMC_CNTRL_UCDBC_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_UCDBC_MASK) >> ENET_MMC_CNTRL_UCDBC_SHIFT) - -/* - * CNTPRSTLVL (RW) - * - * Full-Half Preset - * When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - * - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - * - 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - * - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - * - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - */ -#define ENET_MMC_CNTRL_CNTPRSTLVL_MASK (0x20U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT (5U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) -#define ENET_MMC_CNTRL_CNTPRSTLVL_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) >> ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) - -/* - * CNTPRST (RW) - * - * Counters Preset - * When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. - * This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - */ -#define ENET_MMC_CNTRL_CNTPRST_MASK (0x10U) -#define ENET_MMC_CNTRL_CNTPRST_SHIFT (4U) -#define ENET_MMC_CNTRL_CNTPRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRST_SHIFT) & ENET_MMC_CNTRL_CNTPRST_MASK) -#define ENET_MMC_CNTRL_CNTPRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRST_MASK) >> ENET_MMC_CNTRL_CNTPRST_SHIFT) - -/* - * CNTFREEZ (RW) - * - * MMC Counter Freeze - * When this bit is set, it freezes all MMC counters to their current value. - * Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - * If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - */ -#define ENET_MMC_CNTRL_CNTFREEZ_MASK (0x8U) -#define ENET_MMC_CNTRL_CNTFREEZ_SHIFT (3U) -#define ENET_MMC_CNTRL_CNTFREEZ_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTFREEZ_SHIFT) & ENET_MMC_CNTRL_CNTFREEZ_MASK) -#define ENET_MMC_CNTRL_CNTFREEZ_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTFREEZ_MASK) >> ENET_MMC_CNTRL_CNTFREEZ_SHIFT) - -/* - * RSTONRD (RW) - * - * Reset on Read - * When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - */ -#define ENET_MMC_CNTRL_RSTONRD_MASK (0x4U) -#define ENET_MMC_CNTRL_RSTONRD_SHIFT (2U) -#define ENET_MMC_CNTRL_RSTONRD_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_RSTONRD_SHIFT) & ENET_MMC_CNTRL_RSTONRD_MASK) -#define ENET_MMC_CNTRL_RSTONRD_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_RSTONRD_MASK) >> ENET_MMC_CNTRL_RSTONRD_SHIFT) - -/* - * CNTSTOPRO (RW) - * - * Counter Stop Rollover - * When this bit is set, the counter does not roll over to zero after reaching the maximum value. - */ -#define ENET_MMC_CNTRL_CNTSTOPRO_MASK (0x2U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SHIFT (1U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) -#define ENET_MMC_CNTRL_CNTSTOPRO_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) >> ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) - -/* - * CNTRST (RW) - * - * Counters Reset - * When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - */ -#define ENET_MMC_CNTRL_CNTRST_MASK (0x1U) -#define ENET_MMC_CNTRL_CNTRST_SHIFT (0U) -#define ENET_MMC_CNTRL_CNTRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTRST_SHIFT) & ENET_MMC_CNTRL_CNTRST_MASK) -#define ENET_MMC_CNTRL_CNTRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTRST_MASK) >> ENET_MMC_CNTRL_CNTRST_SHIFT) - -/* Bitfield definition for register: MMC_INTR_RX */ -/* - * RXCTRLFIS (RW) - * - * MMC Receive Control Frame Counter Interrupt Status - * This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCTRLFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT (25U) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) -#define ENET_MMC_INTR_RX_RXCTRLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) >> ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) - -/* - * RXRCVERRFIS (RW) - * - * MMC Receive Error Frame Counter Interrupt Status - * This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRCVERRFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT (24U) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) >> ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) - -/* - * RXWDOGFIS (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Status - * This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXWDOGFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT (23U) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) -#define ENET_MMC_INTR_RX_RXWDOGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) >> ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) - -/* - * RXVLANGBFIS (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Status - * This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXVLANGBFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT (22U) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) >> ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) - -/* - * RXFOVFIS (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Status - * This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXFOVFIS_MASK (0x200000UL) -#define ENET_MMC_INTR_RX_RXFOVFIS_SHIFT (21U) -#define ENET_MMC_INTR_RX_RXFOVFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) -#define ENET_MMC_INTR_RX_RXFOVFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) >> ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) - -/* - * RXPAUSFIS (RW) - * - * MMC Receive Pause Frame Counter Interrupt Status - * This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXPAUSFIS_MASK (0x100000UL) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT (20U) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) -#define ENET_MMC_INTR_RX_RXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) >> ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) - -/* - * RXORANGEFIS (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Status. - * This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXORANGEFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT (19U) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) -#define ENET_MMC_INTR_RX_RXORANGEFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) >> ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) - -/* - * RXLENERFIS (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Status - * This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXLENERFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_RX_RXLENERFIS_SHIFT (18U) -#define ENET_MMC_INTR_RX_RXLENERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) -#define ENET_MMC_INTR_RX_RXLENERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) >> ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) - -/* - * RXUCGFIS (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Status - * This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUCGFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_RX_RXUCGFIS_SHIFT (17U) -#define ENET_MMC_INTR_RX_RXUCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) >> ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) - -/* - * RX1024TMAXOCTGBFIS (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. - * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT (16U) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) - -/* - * RX512T1023OCTGBFIS (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK (0x8000U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT (15U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) - -/* - * RX256T511OCTGBFIS (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK (0x4000U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT (14U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) - -/* - * RX128T255OCTGBFIS (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK (0x2000U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT (13U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) - -/* - * RX65T127OCTGBFIS (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) - -/* - * RX64OCTGBFIS (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) - -/* - * RXOSIZEGFIS (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Status - * This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK (0x400U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT (10U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) - -/* - * RXUSIZEGFIS (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Status - * This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK (0x200U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT (9U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) - -/* - * RXJABERFIS (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Status - * This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXJABERFIS_MASK (0x100U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SHIFT (8U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) -#define ENET_MMC_INTR_RX_RXJABERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) >> ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) - -/* - * RXRUNTFIS (RW) - * - * MMC Receive Runt Frame Counter Interrupt Status - * This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRUNTFIS_MASK (0x80U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT (7U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) -#define ENET_MMC_INTR_RX_RXRUNTFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) >> ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) - -/* - * RXALGNERFIS (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Status - * This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXALGNERFIS_MASK (0x40U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT (6U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) -#define ENET_MMC_INTR_RX_RXALGNERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) >> ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) - -/* - * RXCRCERFIS (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Status - * This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCRCERFIS_MASK (0x20U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT (5U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) -#define ENET_MMC_INTR_RX_RXCRCERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) >> ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) - -/* - * RXMCGFIS (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Status - * This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXMCGFIS_MASK (0x10U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SHIFT (4U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) >> ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) - -/* - * RXBCGFIS (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Status - * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXBCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) >> ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) - -/* - * RXGOCTIS (RW) - * - * MMC Receive Good Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGOCTIS_MASK (0x4U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SHIFT (2U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) - -/* - * RXGBOCTIS (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBOCTIS_MASK (0x2U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT (1U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) - -/* - * RXGBFRMIS (RW) - * - * MMC Receive Good Bad Frame Counter Interrupt Status - * This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBFRMIS_MASK (0x1U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT (0U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) -#define ENET_MMC_INTR_RX_RXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) >> ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_TX */ -/* - * TXOSIZEGFIS (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Status - * This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT (25U) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) >> ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) - -/* - * TXVLANGFIS (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Status - * This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXVLANGFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT (24U) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) -#define ENET_MMC_INTR_TX_TXVLANGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) >> ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) - -/* - * TXPAUSFIS (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Status - * This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXPAUSFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT (23U) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) -#define ENET_MMC_INTR_TX_TXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) >> ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) - -/* - * TXEXDEFFIS (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Status - * This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXDEFFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT (22U) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) - -/* - * TXGFRMIS (RW) - * - * MMC Transmit Good Frame Counter Interrupt Status - * This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGFRMIS_MASK (0x200000UL) -#define ENET_MMC_INTR_TX_TXGFRMIS_SHIFT (21U) -#define ENET_MMC_INTR_TX_TXGFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) - -/* - * TXGOCTIS (RW) - * - * MMC Transmit Good Octet Counter Interrupt Status - * This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGOCTIS_MASK (0x100000UL) -#define ENET_MMC_INTR_TX_TXGOCTIS_SHIFT (20U) -#define ENET_MMC_INTR_TX_TXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) - -/* - * TXCARERFIS (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Status - * This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXCARERFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_TX_TXCARERFIS_SHIFT (19U) -#define ENET_MMC_INTR_TX_TXCARERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) -#define ENET_MMC_INTR_TX_TXCARERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) >> ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) - -/* - * TXEXCOLFIS (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Status - * This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXCOLFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT (18U) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) - -/* - * TXLATCOLFIS (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Status - * This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXLATCOLFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT (17U) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) - -/* - * TXDEFFIS (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Status - * This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXDEFFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_TX_TXDEFFIS_SHIFT (16U) -#define ENET_MMC_INTR_TX_TXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) - -/* - * TXMCOLGFIS (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - * This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCOLGFIS_MASK (0x8000U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT (15U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) - -/* - * TXSCOLGFIS (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Status - * This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXSCOLGFIS_MASK (0x4000U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT (14U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) - -/* - * TXUFLOWERFIS (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Status - * This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK (0x2000U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT (13U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) >> ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) - -/* - * TXBCGBFIS (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) - -/* - * TXMCGBFIS (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - * The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) - -/* - * TXUCGBFIS (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - * This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUCGBFIS_MASK (0x400U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT (10U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXUCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) - -/* - * TX1024TMAXOCTGBFIS (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK (0x200U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT (9U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) - -/* - * TX512T1023OCTGBFIS (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK (0x100U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT (8U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) - -/* - * TX256T511OCTGBFIS (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK (0x80U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT (7U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) - -/* - * TX128T255OCTGBFIS (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK (0x40U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT (6U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) - -/* - * TX65T127OCTGBFIS (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - */ -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK (0x20U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT (5U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) - -/* - * TX64OCTGBFIS (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK (0x10U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT (4U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) - -/* - * TXMCGFIS (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Status - * This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) - -/* - * TXBCGFIS (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGFIS_MASK (0x4U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SHIFT (2U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) - -/* - * TXGBFRMIS (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Status - * This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBFRMIS_MASK (0x2U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT (1U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) - -/* - * TXGBOCTIS (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Status - * This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBOCTIS_MASK (0x1U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT (0U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_RX */ -/* - * RXCTRLFIM (RW) - * - * MMC Receive Control Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) - -/* - * RXRCVERRFIM (RW) - * - * MMC Receive Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) - -/* - * RXWDOGFIM (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) - -/* - * RXVLANGBFIM (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) - -/* - * RXFOVFIM (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) - -/* - * RXPAUSFIM (RW) - * - * MMC Receive Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) - -/* - * RXORANGEFIM (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) - -/* - * RXLENERFIM (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) - -/* - * RXUCGFIM (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) - -/* - * RX1024TMAXOCTGBFIM (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) - -/* - * RX512T1023OCTGBFIM (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) - -/* - * RX256T511OCTGBFIM (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) - -/* - * RX128T255OCTGBFIM (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) - -/* - * RX65T127OCTGBFIM (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) - -/* - * RX64OCTGBFIM (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) - -/* - * RXOSIZEGFIM (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) - -/* - * RXUSIZEGFIM (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) - -/* - * RXJABERFIM (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) - -/* - * RXRUNTFIM (RW) - * - * MMC Receive Runt Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) - -/* - * RXALGNERFIM (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) - -/* - * RXCRCERFIM (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) - -/* - * RXMCGFIM (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) - -/* - * RXBCGFIM (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) - -/* - * RXGOCTIM (RW) - * - * MMC Receive Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) - -/* - * RXGBOCTIM (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_TX */ -/* - * TXOSIZEGFIM (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) - -/* - * TXVLANGFIM (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) - -/* - * TXPAUSFIM (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) - -/* - * TXEXDEFFIM (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) - -/* - * TXGFRMIM (RW) - * - * MMC Transmit Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) - -/* - * TXGOCTIM (RW) - * - * MMC Transmit Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) - -/* - * TXCARERFIM (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) - -/* - * TXEXCOLFIM (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) - -/* - * TXLATCOLFIM (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) - -/* - * TXDEFFIM (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) - -/* - * TXMCOLGFIM (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) - -/* - * TXSCOLGFIM (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) - -/* - * TXUFLOWERFIM (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) - -/* - * TXBCGBFIM (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) - -/* - * TXMCGBFIM (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) - -/* - * TXUCGBFIM (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) - -/* - * TX1024TMAXOCTGBFIM (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) - -/* - * TX512T1023OCTGBFIM (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) - -/* - * TX256T511OCTGBFIM (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) - -/* - * TX128T255OCTGBFIM (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) - -/* - * TX65T127OCTGBFIM (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) - -/* - * TX64OCTGBFIM (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) - -/* - * TXMCGFIM (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) - -/* - * TXBCGFIM (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) - -/* - * TXGBFRMIM (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) - -/* - * TXGBOCTIM (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK (0x1U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT (0U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) - -/* Bitfield definition for register: TX64OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX64OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX64OCTETS_GB_FRMCNT_SHIFT) & ENET_TX64OCTETS_GB_FRMCNT_MASK) -#define ENET_TX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX64OCTETS_GB_FRMCNT_MASK) >> ENET_TX64OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX65TO127OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX128TO255OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX256TO511OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX512TO1023OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX1024TOMAXOCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFRAMECOUNT_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received. - */ -#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ -/* - * RXICMPEROIM (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT (29U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) - -/* - * RXICMPGOIM (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT (28U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) - -/* - * RXTCPEROIM (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT (27U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) - -/* - * RXTCPGOIM (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT (26U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) - -/* - * RXUDPEROIM (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT (25U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) - -/* - * RXUDPGOIM (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT (24U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) - -/* - * RXIPV6NOPAYOIM (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT (23U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) - -/* - * RXIPV6HEROIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT (22U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) - -/* - * RXIPV6GOIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT (21U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) - -/* - * RXIPV4UDSBLOIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT (20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) - -/* - * RXIPV4FRAGOIM (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT (19U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) - -/* - * RXIPV4NOPAYOIM (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT (18U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) - -/* - * RXIPV4HEROIM (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT (17U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) - -/* - * RXIPV4GOIM (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT (16U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) - -/* - * RXICMPERFIM (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT (13U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) - -/* - * RXICMPGFIM (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT (12U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) - -/* - * RXTCPERFIM (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK (0x800U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT (11U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) - -/* - * RXTCPGFIM (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK (0x400U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT (10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) - -/* - * RXUDPERFIM (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK (0x200U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT (9U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) - -/* - * RXUDPGFIM (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK (0x100U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT (8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) - -/* - * RXIPV6NOPAYFIM (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK (0x80U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT (7U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) - -/* - * RXIPV6HERFIM (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK (0x40U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT (6U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) - -/* - * RXIPV6GFIM (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK (0x20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT (5U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) - -/* - * RXIPV4UDSBLFIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK (0x10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT (4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) - -/* - * RXIPV4FRAGFIM (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK (0x8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT (3U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) - -/* - * RXIPV4NOPAYFIM (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK (0x4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT (2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) - -/* - * RXIPV4HERFIM (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK (0x2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT (1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) - -/* - * RXIPV4GFIM (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK (0x1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT (0U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_RX */ -/* - * RXICMPEROIS (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Status - * This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT (29U) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) - -/* - * RXICMPGOIS (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Status - * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT (28U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) - -/* - * RXTCPEROIS (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Status - * This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT (27U) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) - -/* - * RXTCPGOIS (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Status - * This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT (26U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) - -/* - * RXUDPEROIS (RW) - * - * MMC Receive UDP Error Octet Counter Interrupt Status - * This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT (25U) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) - -/* - * RXUDPGOIS (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Status - * This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT (24U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) - -/* - * RXIPV6NOPAYOIS (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT (23U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) - -/* - * RXIPV6HEROIS (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT (22U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) - -/* - * RXIPV6GOIS (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Status - * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT (21U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) - -/* - * RXIPV4UDSBLOIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT (20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) - -/* - * RXIPV4FRAGOIS (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT (19U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) - -/* - * RXIPV4NOPAYOIS (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT (18U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) - -/* - * RXIPV4HEROIS (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT (17U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) - -/* - * RXIPV4GOIS (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Status - * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT (16U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) - -/* - * RXICMPERFIS (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Status - * This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT (13U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) - -/* - * RXICMPGFIS (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Status - * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT (12U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) - -/* - * RXTCPERFIS (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Status - * This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK (0x800U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT (11U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) - -/* - * RXTCPGFIS (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Status - * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK (0x400U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT (10U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) - -/* - * RXUDPERFIS (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Status - * This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK (0x200U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT (9U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) - -/* - * RXUDPGFIS (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Status - * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK (0x100U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT (8U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) - -/* - * RXIPV6NOPAYFIS (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK (0x80U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT (7U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) - -/* - * RXIPV6HERFIS (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK (0x40U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT (6U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) - -/* - * RXIPV6GFIS (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Status - * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK (0x20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT (5U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) - -/* - * RXIPV4UDSBLFIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK (0x10U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT (4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) - -/* - * RXIPV4FRAGFIS (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK (0x8U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT (3U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) - -/* - * RXIPV4NOPAYFIS (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK (0x4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT (2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) - -/* - * RXIPV4HERFIS (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK (0x2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT (1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) - -/* - * RXIPV4GFIS (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Status - * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK (0x1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT (0U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) - -/* Bitfield definition for register: RXIPV4_GD_FMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - */ -#define ENET_RXIPV4_GD_FMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) -#define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ -/* - * L4DPIM0 (RW) - * - * Layer 4 Destination Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK (0x200000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT (21U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) - -/* - * L4DPM0 (RW) - * - * Layer 4 Destination Port Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. - * When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK (0x100000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT (20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) - -/* - * L4SPIM0 (RW) - * - * Layer 4 Source Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK (0x80000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT (19U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) - -/* - * L4SPM0 (RW) - * - * Layer 4 Source Port Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK (0x40000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT (18U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) - -/* - * L4PEN0 (RW) - * - * Layer 4 Protocol Enable - * When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. - * When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. - * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK (0x10000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT (16U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) - -/* - * L3HDBM0 (RW) - * - * Layer 3 IP DA Higher Bits Match - * IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, - * which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. - * The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - … - * - 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK (0xF800U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT (11U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) - -/* - * L3HSBM0 (RW) - * - * Layer 3 IP SA Higher Bits Match - * IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. - * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK (0x7C0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT (6U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) - -/* - * L3DAIM0 (RW) - * - * Layer 3 IP DA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK (0x20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT (5U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) - -/* - * L3DAM0 (RW) - * - * Layer 3 IP DA Match Enable - * When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. - * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK (0x10U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT (4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) - -/* - * L3SAIM0 (RW) - * - * Layer 3 IP SA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK (0x8U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT (3U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) - -/* - * L3SAM0 (RW) - * - * Layer 3 IP SA Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK (0x4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT (2U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) - -/* - * L3PEN0 (RW) - * - * Layer 3 Protocol Enable - * When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. - * When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. - * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK (0x1U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L4_ADDR */ -/* - * L4DP0 (RW) - * - * Layer 4 Destination Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK (0xFFFF0000UL) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT (16U) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) - -/* - * L4SP0 (RW) - * - * Layer 4 Source Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK (0xFFFFU) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT (0U) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_0 */ -/* - * L3A00 (RW) - * - * Layer 3 Address 0 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) >> ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_1 */ -/* - * L3A10 (RW) - * - * Layer 3 Address 1 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) >> ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_2 */ -/* - * L3A20 (RW) - * - * Layer 3 Address 2 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) >> ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_3 */ -/* - * L3A30 (RW) - * - * Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) - -/* Bitfield definition for register: VLAN_TAG_INC_RPL */ -/* - * CSVL (RW) - * - * C-VLAN or S-VLAN - * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - */ -#define ENET_VLAN_TAG_INC_RPL_CSVL_MASK (0x80000UL) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT (19U) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) -#define ENET_VLAN_TAG_INC_RPL_CSVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) >> ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) - -/* - * VLP (RW) - * - * VLAN Priority Control - * When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - */ -#define ENET_VLAN_TAG_INC_RPL_VLP_MASK (0x40000UL) -#define ENET_VLAN_TAG_INC_RPL_VLP_SHIFT (18U) -#define ENET_VLAN_TAG_INC_RPL_VLP_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLP_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) >> ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) - -/* - * VLC (RW) - * - * VLAN Tag Control in Transmit Frames - * - 2’b00: No VLAN tag deletion, insertion, or replacement - * - 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. - * - 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. - * This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. - * - 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). - * Note: Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - */ -#define ENET_VLAN_TAG_INC_RPL_VLC_MASK (0x30000UL) -#define ENET_VLAN_TAG_INC_RPL_VLC_SHIFT (16U) -#define ENET_VLAN_TAG_INC_RPL_VLC_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLC_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) >> ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) - -/* - * VLT (RW) - * - * VLAN Tag for Transmit Frames - * This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - * Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - */ -#define ENET_VLAN_TAG_INC_RPL_VLT_MASK (0xFFFFU) -#define ENET_VLAN_TAG_INC_RPL_VLT_SHIFT (0U) -#define ENET_VLAN_TAG_INC_RPL_VLT_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLT_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) >> ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) - -/* Bitfield definition for register: VLAN_HASH */ -/* - * VLHT (RW) - * - * VLAN Hash Table - * This field contains the 16-bit VLAN Hash Table. - */ -#define ENET_VLAN_HASH_VLHT_MASK (0xFFFFU) -#define ENET_VLAN_HASH_VLHT_SHIFT (0U) -#define ENET_VLAN_HASH_VLHT_SET(x) (((uint32_t)(x) << ENET_VLAN_HASH_VLHT_SHIFT) & ENET_VLAN_HASH_VLHT_MASK) -#define ENET_VLAN_HASH_VLHT_GET(x) (((uint32_t)(x) & ENET_VLAN_HASH_VLHT_MASK) >> ENET_VLAN_HASH_VLHT_SHIFT) - -/* Bitfield definition for register: TS_CTRL */ -/* - * ATSEN3 (RW) - * - * Auxiliary Snapshot 3 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - */ -#define ENET_TS_CTRL_ATSEN3_MASK (0x10000000UL) -#define ENET_TS_CTRL_ATSEN3_SHIFT (28U) -#define ENET_TS_CTRL_ATSEN3_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN3_SHIFT) & ENET_TS_CTRL_ATSEN3_MASK) -#define ENET_TS_CTRL_ATSEN3_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN3_MASK) >> ENET_TS_CTRL_ATSEN3_SHIFT) - -/* - * ATSEN2 (RW) - * - * Auxiliary Snapshot 2 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - */ -#define ENET_TS_CTRL_ATSEN2_MASK (0x8000000UL) -#define ENET_TS_CTRL_ATSEN2_SHIFT (27U) -#define ENET_TS_CTRL_ATSEN2_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN2_SHIFT) & ENET_TS_CTRL_ATSEN2_MASK) -#define ENET_TS_CTRL_ATSEN2_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN2_MASK) >> ENET_TS_CTRL_ATSEN2_SHIFT) - -/* - * ATSEN1 (RW) - * - * Auxiliary Snapshot 1 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - */ -#define ENET_TS_CTRL_ATSEN1_MASK (0x4000000UL) -#define ENET_TS_CTRL_ATSEN1_SHIFT (26U) -#define ENET_TS_CTRL_ATSEN1_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN1_SHIFT) & ENET_TS_CTRL_ATSEN1_MASK) -#define ENET_TS_CTRL_ATSEN1_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN1_MASK) >> ENET_TS_CTRL_ATSEN1_SHIFT) - -/* - * ATSEN0 (RW) - * - * Auxiliary Snapshot 0 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - */ -#define ENET_TS_CTRL_ATSEN0_MASK (0x2000000UL) -#define ENET_TS_CTRL_ATSEN0_SHIFT (25U) -#define ENET_TS_CTRL_ATSEN0_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN0_SHIFT) & ENET_TS_CTRL_ATSEN0_MASK) -#define ENET_TS_CTRL_ATSEN0_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN0_MASK) >> ENET_TS_CTRL_ATSEN0_SHIFT) - -/* - * ATSFC (RW) - * - * Auxiliary Snapshot FIFO Clear - * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - */ -#define ENET_TS_CTRL_ATSFC_MASK (0x1000000UL) -#define ENET_TS_CTRL_ATSFC_SHIFT (24U) -#define ENET_TS_CTRL_ATSFC_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSFC_SHIFT) & ENET_TS_CTRL_ATSFC_MASK) -#define ENET_TS_CTRL_ATSFC_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSFC_MASK) >> ENET_TS_CTRL_ATSFC_SHIFT) - -/* - * TSENMACADDR (RW) - * - * Enable MAC address for PTP Frame Filtering - * When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - */ -#define ENET_TS_CTRL_TSENMACADDR_MASK (0x40000UL) -#define ENET_TS_CTRL_TSENMACADDR_SHIFT (18U) -#define ENET_TS_CTRL_TSENMACADDR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENMACADDR_SHIFT) & ENET_TS_CTRL_TSENMACADDR_MASK) -#define ENET_TS_CTRL_TSENMACADDR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENMACADDR_MASK) >> ENET_TS_CTRL_TSENMACADDR_SHIFT) - -/* - * SNAPTYPSEL (RW) - * - * Select PTP packets for Taking Snapshots - * These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - */ -#define ENET_TS_CTRL_SNAPTYPSEL_MASK (0x30000UL) -#define ENET_TS_CTRL_SNAPTYPSEL_SHIFT (16U) -#define ENET_TS_CTRL_SNAPTYPSEL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_SNAPTYPSEL_SHIFT) & ENET_TS_CTRL_SNAPTYPSEL_MASK) -#define ENET_TS_CTRL_SNAPTYPSEL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_SNAPTYPSEL_MASK) >> ENET_TS_CTRL_SNAPTYPSEL_SHIFT) - -/* - * TSMSTRENA (RW) - * - * Enable Snapshot for Messages Relevant to Master - * When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - */ -#define ENET_TS_CTRL_TSMSTRENA_MASK (0x8000U) -#define ENET_TS_CTRL_TSMSTRENA_SHIFT (15U) -#define ENET_TS_CTRL_TSMSTRENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSMSTRENA_SHIFT) & ENET_TS_CTRL_TSMSTRENA_MASK) -#define ENET_TS_CTRL_TSMSTRENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSMSTRENA_MASK) >> ENET_TS_CTRL_TSMSTRENA_SHIFT) - -/* - * TSEVNTENA (RW) - * - * Enable Timestamp Snapshot for Event Messages - * When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - */ -#define ENET_TS_CTRL_TSEVNTENA_MASK (0x4000U) -#define ENET_TS_CTRL_TSEVNTENA_SHIFT (14U) -#define ENET_TS_CTRL_TSEVNTENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSEVNTENA_SHIFT) & ENET_TS_CTRL_TSEVNTENA_MASK) -#define ENET_TS_CTRL_TSEVNTENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSEVNTENA_MASK) >> ENET_TS_CTRL_TSEVNTENA_SHIFT) - -/* - * TSIPV4ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv4-UDP - * When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - */ -#define ENET_TS_CTRL_TSIPV4ENA_MASK (0x2000U) -#define ENET_TS_CTRL_TSIPV4ENA_SHIFT (13U) -#define ENET_TS_CTRL_TSIPV4ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV4ENA_SHIFT) & ENET_TS_CTRL_TSIPV4ENA_MASK) -#define ENET_TS_CTRL_TSIPV4ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV4ENA_MASK) >> ENET_TS_CTRL_TSIPV4ENA_SHIFT) - -/* - * TSIPV6ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv6-UDP - * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - */ -#define ENET_TS_CTRL_TSIPV6ENA_MASK (0x1000U) -#define ENET_TS_CTRL_TSIPV6ENA_SHIFT (12U) -#define ENET_TS_CTRL_TSIPV6ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV6ENA_SHIFT) & ENET_TS_CTRL_TSIPV6ENA_MASK) -#define ENET_TS_CTRL_TSIPV6ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV6ENA_MASK) >> ENET_TS_CTRL_TSIPV6ENA_SHIFT) - -/* - * TSIPENA (RW) - * - * Enable Processing of PTP over Ethernet Frames - * When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - */ -#define ENET_TS_CTRL_TSIPENA_MASK (0x800U) -#define ENET_TS_CTRL_TSIPENA_SHIFT (11U) -#define ENET_TS_CTRL_TSIPENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPENA_SHIFT) & ENET_TS_CTRL_TSIPENA_MASK) -#define ENET_TS_CTRL_TSIPENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPENA_MASK) >> ENET_TS_CTRL_TSIPENA_SHIFT) - -/* - * TSVER2ENA (RW) - * - * Enable PTP packet Processing for Version 2 Format - * When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - */ -#define ENET_TS_CTRL_TSVER2ENA_MASK (0x400U) -#define ENET_TS_CTRL_TSVER2ENA_SHIFT (10U) -#define ENET_TS_CTRL_TSVER2ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSVER2ENA_SHIFT) & ENET_TS_CTRL_TSVER2ENA_MASK) -#define ENET_TS_CTRL_TSVER2ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSVER2ENA_MASK) >> ENET_TS_CTRL_TSVER2ENA_SHIFT) - -/* - * TSCTRLSSR (RW) - * - * Timestamp Digital or Binary Rollover Control - * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - * When reset, the rollover value of sub-second register is 0x7FFF_FFFF. - * The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - */ -#define ENET_TS_CTRL_TSCTRLSSR_MASK (0x200U) -#define ENET_TS_CTRL_TSCTRLSSR_SHIFT (9U) -#define ENET_TS_CTRL_TSCTRLSSR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCTRLSSR_SHIFT) & ENET_TS_CTRL_TSCTRLSSR_MASK) -#define ENET_TS_CTRL_TSCTRLSSR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCTRLSSR_MASK) >> ENET_TS_CTRL_TSCTRLSSR_SHIFT) - -/* - * TSENALL (RW) - * - * Enable Timestamp for All Frames - * When set, the timestamp snapshot is enabled for all frames received by the MAC. - */ -#define ENET_TS_CTRL_TSENALL_MASK (0x100U) -#define ENET_TS_CTRL_TSENALL_SHIFT (8U) -#define ENET_TS_CTRL_TSENALL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENALL_SHIFT) & ENET_TS_CTRL_TSENALL_MASK) -#define ENET_TS_CTRL_TSENALL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENALL_MASK) >> ENET_TS_CTRL_TSENALL_SHIFT) - -/* - * TSADDREG (RW) - * - * Addend Reg Update - * When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. - * This register bit should be zero before setting it. - */ -#define ENET_TS_CTRL_TSADDREG_MASK (0x20U) -#define ENET_TS_CTRL_TSADDREG_SHIFT (5U) -#define ENET_TS_CTRL_TSADDREG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSADDREG_SHIFT) & ENET_TS_CTRL_TSADDREG_MASK) -#define ENET_TS_CTRL_TSADDREG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSADDREG_MASK) >> ENET_TS_CTRL_TSADDREG_SHIFT) - -/* - * TSTRIG (RW) - * - * Timestamp Interrupt Trigger Enable - * When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. - * This bit is reset after the generation of the Timestamp Trigger Interrupt. - */ -#define ENET_TS_CTRL_TSTRIG_MASK (0x10U) -#define ENET_TS_CTRL_TSTRIG_SHIFT (4U) -#define ENET_TS_CTRL_TSTRIG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSTRIG_SHIFT) & ENET_TS_CTRL_TSTRIG_MASK) -#define ENET_TS_CTRL_TSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSTRIG_MASK) >> ENET_TS_CTRL_TSTRIG_SHIFT) - -/* - * TSUPDT (RW) - * - * Timestamp Update - * When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - */ -#define ENET_TS_CTRL_TSUPDT_MASK (0x8U) -#define ENET_TS_CTRL_TSUPDT_SHIFT (3U) -#define ENET_TS_CTRL_TSUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSUPDT_SHIFT) & ENET_TS_CTRL_TSUPDT_MASK) -#define ENET_TS_CTRL_TSUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSUPDT_MASK) >> ENET_TS_CTRL_TSUPDT_SHIFT) - -/* - * TSINIT (RW) - * - * Timestamp Initialize - * When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the initialization is complete. - * The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - */ -#define ENET_TS_CTRL_TSINIT_MASK (0x4U) -#define ENET_TS_CTRL_TSINIT_SHIFT (2U) -#define ENET_TS_CTRL_TSINIT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSINIT_SHIFT) & ENET_TS_CTRL_TSINIT_MASK) -#define ENET_TS_CTRL_TSINIT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSINIT_MASK) >> ENET_TS_CTRL_TSINIT_SHIFT) - -/* - * TSCFUPDT (RW) - * - * Timestamp Fine or Coarse Update - * When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - */ -#define ENET_TS_CTRL_TSCFUPDT_MASK (0x2U) -#define ENET_TS_CTRL_TSCFUPDT_SHIFT (1U) -#define ENET_TS_CTRL_TSCFUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCFUPDT_SHIFT) & ENET_TS_CTRL_TSCFUPDT_MASK) -#define ENET_TS_CTRL_TSCFUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCFUPDT_MASK) >> ENET_TS_CTRL_TSCFUPDT_SHIFT) - -/* - * TSENA (RW) - * - * Timestamp Enable - * When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. - * You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - */ -#define ENET_TS_CTRL_TSENA_MASK (0x1U) -#define ENET_TS_CTRL_TSENA_SHIFT (0U) -#define ENET_TS_CTRL_TSENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENA_SHIFT) & ENET_TS_CTRL_TSENA_MASK) -#define ENET_TS_CTRL_TSENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENA_MASK) >> ENET_TS_CTRL_TSENA_SHIFT) - -/* Bitfield definition for register: SUB_SEC_INCR */ -/* - * SSINC (RW) - * - * Sub-second Increment Value - * The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. - * For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) - * when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. - * When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. - * In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - */ -#define ENET_SUB_SEC_INCR_SSINC_MASK (0xFFU) -#define ENET_SUB_SEC_INCR_SSINC_SHIFT (0U) -#define ENET_SUB_SEC_INCR_SSINC_SET(x) (((uint32_t)(x) << ENET_SUB_SEC_INCR_SSINC_SHIFT) & ENET_SUB_SEC_INCR_SSINC_MASK) -#define ENET_SUB_SEC_INCR_SSINC_GET(x) (((uint32_t)(x) & ENET_SUB_SEC_INCR_SSINC_MASK) >> ENET_SUB_SEC_INCR_SSINC_SHIFT) - -/* Bitfield definition for register: SYST_SEC */ -/* - * TSS (RO) - * - * Timestamp Second - * The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - */ -#define ENET_SYST_SEC_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_TSS_SHIFT (0U) -#define ENET_SYST_SEC_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_TSS_MASK) >> ENET_SYST_SEC_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC */ -/* - * TSSS (RO) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - */ -#define ENET_SYST_NSEC_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_TSSS_MASK) >> ENET_SYST_NSEC_TSSS_SHIFT) - -/* Bitfield definition for register: SYST_SEC_UPD */ -/* - * TSS (RW) - * - * Timestamp Second - * The value in this field indicates the time in seconds to be initialized or added to the system time. - */ -#define ENET_SYST_SEC_UPD_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_UPD_TSS_SHIFT (0U) -#define ENET_SYST_SEC_UPD_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_UPD_TSS_SHIFT) & ENET_SYST_SEC_UPD_TSS_MASK) -#define ENET_SYST_SEC_UPD_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_UPD_TSS_MASK) >> ENET_SYST_SEC_UPD_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC_UPD */ -/* - * ADDSUB (RW) - * - * Add or Subtract Time - * When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - */ -#define ENET_SYST_NSEC_UPD_ADDSUB_MASK (0x80000000UL) -#define ENET_SYST_NSEC_UPD_ADDSUB_SHIFT (31U) -#define ENET_SYST_NSEC_UPD_ADDSUB_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) -#define ENET_SYST_NSEC_UPD_ADDSUB_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) >> ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) - -/* - * TSSS (RW) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - */ -#define ENET_SYST_NSEC_UPD_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_UPD_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_UPD_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_TSSS_SHIFT) & ENET_SYST_NSEC_UPD_TSSS_MASK) -#define ENET_SYST_NSEC_UPD_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_TSSS_MASK) >> ENET_SYST_NSEC_UPD_TSSS_SHIFT) - -/* Bitfield definition for register: TS_ADDEND */ -/* - * TSAR (RW) - * - * Timestamp Addend Register - * This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - */ -#define ENET_TS_ADDEND_TSAR_MASK (0xFFFFFFFFUL) -#define ENET_TS_ADDEND_TSAR_SHIFT (0U) -#define ENET_TS_ADDEND_TSAR_SET(x) (((uint32_t)(x) << ENET_TS_ADDEND_TSAR_SHIFT) & ENET_TS_ADDEND_TSAR_MASK) -#define ENET_TS_ADDEND_TSAR_GET(x) (((uint32_t)(x) & ENET_TS_ADDEND_TSAR_MASK) >> ENET_TS_ADDEND_TSAR_SHIFT) - -/* Bitfield definition for register: TGTTM_SEC */ -/* - * TSTR (RW) - * - * Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_TGTTM_SEC_TSTR_MASK (0xFFFFFFFFUL) -#define ENET_TGTTM_SEC_TSTR_SHIFT (0U) -#define ENET_TGTTM_SEC_TSTR_SET(x) (((uint32_t)(x) << ENET_TGTTM_SEC_TSTR_SHIFT) & ENET_TGTTM_SEC_TSTR_MASK) -#define ENET_TGTTM_SEC_TSTR_GET(x) (((uint32_t)(x) & ENET_TGTTM_SEC_TSTR_MASK) >> ENET_TGTTM_SEC_TSTR_SHIFT) - -/* Bitfield definition for register: TGTTM_NSEC */ -/* - * TRGTBUSY (RW) - * - * Target Time Register Busy - * The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Target Time Registers when this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - */ -#define ENET_TGTTM_NSEC_TRGTBUSY_MASK (0x80000000UL) -#define ENET_TGTTM_NSEC_TRGTBUSY_SHIFT (31U) -#define ENET_TGTTM_NSEC_TRGTBUSY_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) -#define ENET_TGTTM_NSEC_TRGTBUSY_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) >> ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) - -/* - * TTSLO (RW) - * - * Target Timestamp Low Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_TGTTM_NSEC_TTSLO_MASK (0x7FFFFFFFUL) -#define ENET_TGTTM_NSEC_TTSLO_SHIFT (0U) -#define ENET_TGTTM_NSEC_TTSLO_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TTSLO_SHIFT) & ENET_TGTTM_NSEC_TTSLO_MASK) -#define ENET_TGTTM_NSEC_TTSLO_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TTSLO_MASK) >> ENET_TGTTM_NSEC_TTSLO_SHIFT) - -/* Bitfield definition for register: SYSTM_H_SEC */ -/* - * TSHWR (RW) - * - * Timestamp Higher Word Register - * This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. - * The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - */ -#define ENET_SYSTM_H_SEC_TSHWR_MASK (0xFFFFU) -#define ENET_SYSTM_H_SEC_TSHWR_SHIFT (0U) -#define ENET_SYSTM_H_SEC_TSHWR_SET(x) (((uint32_t)(x) << ENET_SYSTM_H_SEC_TSHWR_SHIFT) & ENET_SYSTM_H_SEC_TSHWR_MASK) -#define ENET_SYSTM_H_SEC_TSHWR_GET(x) (((uint32_t)(x) & ENET_SYSTM_H_SEC_TSHWR_MASK) >> ENET_SYSTM_H_SEC_TSHWR_SHIFT) - -/* Bitfield definition for register: TS_STATUS */ -/* - * ATSNS (RO) - * - * Number of Auxiliary Timestamp Snapshots - * This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. - * These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. - * This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSNS_MASK (0x3E000000UL) -#define ENET_TS_STATUS_ATSNS_SHIFT (25U) -#define ENET_TS_STATUS_ATSNS_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSNS_MASK) >> ENET_TS_STATUS_ATSNS_SHIFT) - -/* - * ATSSTM (RO) - * - * Auxiliary Timestamp Snapshot Trigger Missed - * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. - * This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSSTM_MASK (0x1000000UL) -#define ENET_TS_STATUS_ATSSTM_SHIFT (24U) -#define ENET_TS_STATUS_ATSSTM_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTM_MASK) >> ENET_TS_STATUS_ATSSTM_SHIFT) - -/* - * ATSSTN (RO) - * - * Auxiliary Timestamp Snapshot Trigger Identifier - * These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. - * When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. - * These bits are applicable only if the number of Auxiliary snapshots is more than one. - * One bit is assigned for each trigger as shown in the following list: - * - Bit 16: Auxiliary trigger 0 - * - Bit 17: Auxiliary trigger 1 - * - Bit 18: Auxiliary trigger 2 - * - Bit 19: Auxiliary trigger 3 - * The software can read this register to find the triggers that are set when the timestamp is taken. - */ -#define ENET_TS_STATUS_ATSSTN_MASK (0xF0000UL) -#define ENET_TS_STATUS_ATSSTN_SHIFT (16U) -#define ENET_TS_STATUS_ATSSTN_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTN_MASK) >> ENET_TS_STATUS_ATSSTN_SHIFT) - -/* - * TSTRGTERR3 (RO) - * - * Timestamp Target Time Error - * This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - */ -#define ENET_TS_STATUS_TSTRGTERR3_MASK (0x200U) -#define ENET_TS_STATUS_TSTRGTERR3_SHIFT (9U) -#define ENET_TS_STATUS_TSTRGTERR3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR3_MASK) >> ENET_TS_STATUS_TSTRGTERR3_SHIFT) - -/* - * TSTARGT3 (RO) - * - * Timestamp Target Time Reached for Target Time PPS3 - * When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - */ -#define ENET_TS_STATUS_TSTARGT3_MASK (0x100U) -#define ENET_TS_STATUS_TSTARGT3_SHIFT (8U) -#define ENET_TS_STATUS_TSTARGT3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT3_MASK) >> ENET_TS_STATUS_TSTARGT3_SHIFT) - -/* - * TSTRGTERR2 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR2_MASK (0x80U) -#define ENET_TS_STATUS_TSTRGTERR2_SHIFT (7U) -#define ENET_TS_STATUS_TSTRGTERR2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR2_MASK) >> ENET_TS_STATUS_TSTRGTERR2_SHIFT) - -/* - * TSTARGT2 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT2_MASK (0x40U) -#define ENET_TS_STATUS_TSTARGT2_SHIFT (6U) -#define ENET_TS_STATUS_TSTARGT2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT2_MASK) >> ENET_TS_STATUS_TSTARGT2_SHIFT) - -/* - * TSTRGTERR1 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR1_MASK (0x20U) -#define ENET_TS_STATUS_TSTRGTERR1_SHIFT (5U) -#define ENET_TS_STATUS_TSTRGTERR1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR1_MASK) >> ENET_TS_STATUS_TSTRGTERR1_SHIFT) - -/* - * TSTARGT1 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT1_MASK (0x10U) -#define ENET_TS_STATUS_TSTARGT1_SHIFT (4U) -#define ENET_TS_STATUS_TSTARGT1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT1_MASK) >> ENET_TS_STATUS_TSTARGT1_SHIFT) - -/* - * TSTRGTERR (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR_MASK (0x8U) -#define ENET_TS_STATUS_TSTRGTERR_SHIFT (3U) -#define ENET_TS_STATUS_TSTRGTERR_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR_MASK) >> ENET_TS_STATUS_TSTRGTERR_SHIFT) - -/* - * AUXTSTRIG (RO) - * - */ -#define ENET_TS_STATUS_AUXTSTRIG_MASK (0x4U) -#define ENET_TS_STATUS_AUXTSTRIG_SHIFT (2U) -#define ENET_TS_STATUS_AUXTSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_AUXTSTRIG_MASK) >> ENET_TS_STATUS_AUXTSTRIG_SHIFT) - -/* - * TSTARGT (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT_MASK (0x2U) -#define ENET_TS_STATUS_TSTARGT_SHIFT (1U) -#define ENET_TS_STATUS_TSTARGT_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT_MASK) >> ENET_TS_STATUS_TSTARGT_SHIFT) - -/* - * TSSOVF (RO) - * - */ -#define ENET_TS_STATUS_TSSOVF_MASK (0x1U) -#define ENET_TS_STATUS_TSSOVF_SHIFT (0U) -#define ENET_TS_STATUS_TSSOVF_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSSOVF_MASK) >> ENET_TS_STATUS_TSSOVF_SHIFT) - -/* Bitfield definition for register: PPS_CTRL */ -/* - * TRGTMODSEL3 (RW) - * - * Target Time Register Mode for PPS3 Output - * This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL3_MASK (0x60000000UL) -#define ENET_PPS_CTRL_TRGTMODSEL3_SHIFT (29U) -#define ENET_PPS_CTRL_TRGTMODSEL3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) >> ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) - -/* - * PPSCMD3 (WO) - * - * Flexible PPS3 Output Control - * This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD3_MASK (0x7000000UL) -#define ENET_PPS_CTRL_PPSCMD3_SHIFT (24U) -#define ENET_PPS_CTRL_PPSCMD3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD3_SHIFT) & ENET_PPS_CTRL_PPSCMD3_MASK) -#define ENET_PPS_CTRL_PPSCMD3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD3_MASK) >> ENET_PPS_CTRL_PPSCMD3_SHIFT) - -/* - * TRGTMODSEL2 (RW) - * - * Target Time Register Mode for PPS2 Output - * This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL2_MASK (0x600000UL) -#define ENET_PPS_CTRL_TRGTMODSEL2_SHIFT (21U) -#define ENET_PPS_CTRL_TRGTMODSEL2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) >> ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) - -/* - * PPSCMD2 (WO) - * - * Flexible PPS2 Output Control - * This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD2_MASK (0x70000UL) -#define ENET_PPS_CTRL_PPSCMD2_SHIFT (16U) -#define ENET_PPS_CTRL_PPSCMD2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD2_SHIFT) & ENET_PPS_CTRL_PPSCMD2_MASK) -#define ENET_PPS_CTRL_PPSCMD2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD2_MASK) >> ENET_PPS_CTRL_PPSCMD2_SHIFT) - -/* - * TRGTMODSEL1 (RW) - * - * Target Time Register Mode for PPS1 Output - * This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL1_MASK (0x6000U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SHIFT (13U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) - -/* - * PPSCMD1 (WO) - * - * Flexible PPS1 Output Control - * This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD1_MASK (0x700U) -#define ENET_PPS_CTRL_PPSCMD1_SHIFT (8U) -#define ENET_PPS_CTRL_PPSCMD1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD1_SHIFT) & ENET_PPS_CTRL_PPSCMD1_MASK) -#define ENET_PPS_CTRL_PPSCMD1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD1_MASK) >> ENET_PPS_CTRL_PPSCMD1_SHIFT) - -/* - * TRGTMODSEL0 (RW) - * - * Target Time Register Mode for PPS0 Output - * This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: - * - 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. - * - 01: Reserved - * - 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. - * - 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - */ -#define ENET_PPS_CTRL_TRGTMODSEL0_MASK (0x60U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SHIFT (5U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) >> ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) - -/* - * PPSEN0 (RW) - * - * Flexible PPS Output Mode Enable - * When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - */ -#define ENET_PPS_CTRL_PPSEN0_MASK (0x10U) -#define ENET_PPS_CTRL_PPSEN0_SHIFT (4U) -#define ENET_PPS_CTRL_PPSEN0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN0_SHIFT) & ENET_PPS_CTRL_PPSEN0_MASK) -#define ENET_PPS_CTRL_PPSEN0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN0_MASK) >> ENET_PPS_CTRL_PPSEN0_SHIFT) - -/* - * PPSCTRLCMD0 (RW/WO) - * - * PPSCTRL0: PPS0 Output Frequency Control - * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. - * The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. - * For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: - * - 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. - * - 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. - * - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. - * - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... - * - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. - * Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. - * In the digital rollover mode, the PPS output frequency is an average number. - * The actual clock is of different frequency that gets synchronized every second. For example: - * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - * - One clock of 50 percent duty cycle and 537 ms period - * - Second clock of 463 ms period (268 ms low and 195 ms high) - * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - * - Three clocks of 50 percent duty cycle and 268 ms period - * - Fourth clock of 195 ms period (134 ms low and 61 ms high) - * PPSCMD0: Flexible PPS0 Output Control - * 0000: No Command - * 0001: START Single Pulse - * This command generates single pulse rising at the start point defined in - * Target Time Registers and of a duration defined - * in the PPS0 Width Register. - * 0010: START Pulse Train - * This command generates the train of pulses rising at the start point - * defined in the Target Time Registers and of a duration defined in the - * PPS0 Width Register and repeated at interval defined in the PPS - * Interval Register. By default, the PPS pulse train is free-running unless - * stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train - * immediately’ commands. - * 0011: Cancel START - * This command cancels the START Single Pulse and START Pulse Train - * commands if the system time has not crossed the programmed start - * time. - * 0100: STOP Pulse train at time - * This command stops the train of pulses initiated by the START Pulse - * Train command (PPSCMD = 0010) after the time programmed in the - * Target Time registers elapses. - * 0101: STOP Pulse Train immediately - * This command immediately stops the train of pulses initiated by the - * START Pulse Train command (PPSCMD = 0010). - * 0110: Cancel STOP Pulse train - * This command cancels the STOP pulse train at time command if the - * programmed stop time has not elapsed. The PPS pulse train becomes - * free-running on the successful execution of this command. - * 0111-1111: Reserved - * Note: These bits get cleared automatically - */ -#define ENET_PPS_CTRL_PPSCTRLCMD0_MASK (0xFU) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT (0U) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) -#define ENET_PPS_CTRL_PPSCTRLCMD0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) >> ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) - -/* Bitfield definition for register: AUX_TS_NSEC */ -/* - * AUXTSLO (RO) - * - * Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - */ -#define ENET_AUX_TS_NSEC_AUXTSLO_MASK (0x7FFFFFFFUL) -#define ENET_AUX_TS_NSEC_AUXTSLO_SHIFT (0U) -#define ENET_AUX_TS_NSEC_AUXTSLO_GET(x) (((uint32_t)(x) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) >> ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) - -/* Bitfield definition for register: AUX_TS_SEC */ -/* - * AUXTSHI (RO) - * - * Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - */ -#define ENET_AUX_TS_SEC_AUXTSHI_MASK (0xFFFFFFFFUL) -#define ENET_AUX_TS_SEC_AUXTSHI_SHIFT (0U) -#define ENET_AUX_TS_SEC_AUXTSHI_GET(x) (((uint32_t)(x) & ENET_AUX_TS_SEC_AUXTSHI_MASK) >> ENET_AUX_TS_SEC_AUXTSHI_SHIFT) - -/* Bitfield definition for register: PPS0_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS0 Output Signal Interval - * These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS0 signal output is 100ns - * (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS0_INTERVAL_PPSINT_SHIFT) & ENET_PPS0_INTERVAL_PPSINT_MASK) -#define ENET_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS0_INTERVAL_PPSINT_MASK) >> ENET_PPS0_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PPS0_WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS0 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - * (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS0_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS0_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS0_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) >> ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_SEC */ -/* - * TSTRH1 (RW) - * - * PPS1 Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_PPS_TGTTM_SEC_TSTRH1_MASK (0xFFFFFFFFUL) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT (0U) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) -#define ENET_PPS_TGTTM_SEC_TSTRH1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) >> ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_NSEC */ -/* - * TRGTBUSY1 (RW) - * - * PPS1 Target Time Register Busy - * The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Targeers wht Time Registen this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. - */ -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK (0x80000000UL) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT (31U) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) >> ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) - -/* - * TTSL1 (RW) - * - * Target Time Low for PPS1 Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_PPS_TGTTM_NSEC_TTSL1_MASK (0x7FFFFFFFUL) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT (0U) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) -#define ENET_PPS_TGTTM_NSEC_TTSL1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) >> ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) - -/* Bitfield definition for register of struct array PPS: INTERVAL */ -/* - * PPSINT (RW) - * - * PPS1 Output Signal Interval - * These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), - * then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS_INTERVAL_PPSINT_SHIFT) & ENET_PPS_INTERVAL_PPSINT_MASK) -#define ENET_PPS_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS_INTERVAL_PPSINT_MASK) >> ENET_PPS_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register of struct array PPS: WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS1 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, - * if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), - * then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS_WIDTH_PPSWIDTH_MASK) >> ENET_PPS_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register: DMA_BUS_MODE */ -/* - * RIB (RW) - * - * Rebuild INCRx Burst - * When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - * the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. - * The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. - * By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - */ -#define ENET_DMA_BUS_MODE_RIB_MASK (0x80000000UL) -#define ENET_DMA_BUS_MODE_RIB_SHIFT (31U) -#define ENET_DMA_BUS_MODE_RIB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RIB_SHIFT) & ENET_DMA_BUS_MODE_RIB_MASK) -#define ENET_DMA_BUS_MODE_RIB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RIB_MASK) >> ENET_DMA_BUS_MODE_RIB_SHIFT) - -/* - * PRWG (RW) - * - * Channel Priority - * Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. - * - 00: The priority weight is 1. - * - 01: The priority weight is 2. - * - 10: The priority weight is 3. - * - 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_PRWG_MASK (0x30000000UL) -#define ENET_DMA_BUS_MODE_PRWG_SHIFT (28U) -#define ENET_DMA_BUS_MODE_PRWG_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PRWG_SHIFT) & ENET_DMA_BUS_MODE_PRWG_MASK) -#define ENET_DMA_BUS_MODE_PRWG_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PRWG_MASK) >> ENET_DMA_BUS_MODE_PRWG_SHIFT) - -/* - * TXPR (RW) - * - * Transmit Priority - * When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_TXPR_MASK (0x8000000UL) -#define ENET_DMA_BUS_MODE_TXPR_SHIFT (27U) -#define ENET_DMA_BUS_MODE_TXPR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_TXPR_SHIFT) & ENET_DMA_BUS_MODE_TXPR_MASK) -#define ENET_DMA_BUS_MODE_TXPR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_TXPR_MASK) >> ENET_DMA_BUS_MODE_TXPR_SHIFT) - -/* - * MB (RW) - * - * Mixed Burst - * When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), - * whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - */ -#define ENET_DMA_BUS_MODE_MB_MASK (0x4000000UL) -#define ENET_DMA_BUS_MODE_MB_SHIFT (26U) -#define ENET_DMA_BUS_MODE_MB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_MB_SHIFT) & ENET_DMA_BUS_MODE_MB_MASK) -#define ENET_DMA_BUS_MODE_MB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_MB_MASK) >> ENET_DMA_BUS_MODE_MB_SHIFT) - -/* - * AAL (RW) - * - * Address-Aligned Beats - * When this bit is set high and the FB bit is equal to 1, - * the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - * the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - */ -#define ENET_DMA_BUS_MODE_AAL_MASK (0x2000000UL) -#define ENET_DMA_BUS_MODE_AAL_SHIFT (25U) -#define ENET_DMA_BUS_MODE_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_AAL_SHIFT) & ENET_DMA_BUS_MODE_AAL_MASK) -#define ENET_DMA_BUS_MODE_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_AAL_MASK) >> ENET_DMA_BUS_MODE_AAL_SHIFT) - -/* - * PBLX8 (RW) - * - * PBLx8 Mode - * When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. - * Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - */ -#define ENET_DMA_BUS_MODE_PBLX8_MASK (0x1000000UL) -#define ENET_DMA_BUS_MODE_PBLX8_SHIFT (24U) -#define ENET_DMA_BUS_MODE_PBLX8_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBLX8_SHIFT) & ENET_DMA_BUS_MODE_PBLX8_MASK) -#define ENET_DMA_BUS_MODE_PBLX8_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBLX8_MASK) >> ENET_DMA_BUS_MODE_PBLX8_SHIFT) - -/* - * USP (RW) - * - * Use Separate PBL - * When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. - * The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. - * When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - */ -#define ENET_DMA_BUS_MODE_USP_MASK (0x800000UL) -#define ENET_DMA_BUS_MODE_USP_SHIFT (23U) -#define ENET_DMA_BUS_MODE_USP_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_USP_SHIFT) & ENET_DMA_BUS_MODE_USP_MASK) -#define ENET_DMA_BUS_MODE_USP_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_USP_MASK) >> ENET_DMA_BUS_MODE_USP_SHIFT) - -/* - * RPBL (RW) - * - * Rx DMA PBL - * This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - * You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. - * This field is valid and applicable only when USP is set high. - */ -#define ENET_DMA_BUS_MODE_RPBL_MASK (0x7E0000UL) -#define ENET_DMA_BUS_MODE_RPBL_SHIFT (17U) -#define ENET_DMA_BUS_MODE_RPBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RPBL_SHIFT) & ENET_DMA_BUS_MODE_RPBL_MASK) -#define ENET_DMA_BUS_MODE_RPBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RPBL_MASK) >> ENET_DMA_BUS_MODE_RPBL_SHIFT) - -/* - * FB (RW) - * - * Fixed Burst - * This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. - * When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. - * When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - */ -#define ENET_DMA_BUS_MODE_FB_MASK (0x10000UL) -#define ENET_DMA_BUS_MODE_FB_SHIFT (16U) -#define ENET_DMA_BUS_MODE_FB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_FB_SHIFT) & ENET_DMA_BUS_MODE_FB_MASK) -#define ENET_DMA_BUS_MODE_FB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_FB_MASK) >> ENET_DMA_BUS_MODE_FB_SHIFT) - -/* - * PR (RW) - * - * Priority Ratio - * These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - * These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. - * - 00: The Priority Ratio is 1:1. - * - 01: The Priority Ratio is 2:1. - * - 10: The Priority Ratio is 3:1. - * - 11: The Priority Ratio is 4:1. - */ -#define ENET_DMA_BUS_MODE_PR_MASK (0xC000U) -#define ENET_DMA_BUS_MODE_PR_SHIFT (14U) -#define ENET_DMA_BUS_MODE_PR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PR_SHIFT) & ENET_DMA_BUS_MODE_PR_MASK) -#define ENET_DMA_BUS_MODE_PR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PR_MASK) >> ENET_DMA_BUS_MODE_PR_SHIFT) - -/* - * PBL (RW) - * - * Programmable Burst Length - * These bits indicate the maximum number of beats to be transferred in one DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. - * PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. - * Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. - * If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - */ -#define ENET_DMA_BUS_MODE_PBL_MASK (0x3F00U) -#define ENET_DMA_BUS_MODE_PBL_SHIFT (8U) -#define ENET_DMA_BUS_MODE_PBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBL_SHIFT) & ENET_DMA_BUS_MODE_PBL_MASK) -#define ENET_DMA_BUS_MODE_PBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBL_MASK) >> ENET_DMA_BUS_MODE_PBL_SHIFT) - -/* - * ATDS (RW) - * - * Alternate Descriptor Size - * When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). - * This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. - * The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - * In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. - * This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - * - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. - * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - */ -#define ENET_DMA_BUS_MODE_ATDS_MASK (0x80U) -#define ENET_DMA_BUS_MODE_ATDS_SHIFT (7U) -#define ENET_DMA_BUS_MODE_ATDS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_ATDS_SHIFT) & ENET_DMA_BUS_MODE_ATDS_MASK) -#define ENET_DMA_BUS_MODE_ATDS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_ATDS_MASK) >> ENET_DMA_BUS_MODE_ATDS_SHIFT) - -/* - * DSL (RW) - * - * Descriptor Skip Length - * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. - * The address skipping starts from the end of current descriptor to the start of next descriptor. - * When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - */ -#define ENET_DMA_BUS_MODE_DSL_MASK (0x7CU) -#define ENET_DMA_BUS_MODE_DSL_SHIFT (2U) -#define ENET_DMA_BUS_MODE_DSL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DSL_SHIFT) & ENET_DMA_BUS_MODE_DSL_MASK) -#define ENET_DMA_BUS_MODE_DSL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DSL_MASK) >> ENET_DMA_BUS_MODE_DSL_SHIFT) - -/* - * DA (RW) - * - * DMA Arbitration Scheme - * This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. - * - 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). - * - 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - */ -#define ENET_DMA_BUS_MODE_DA_MASK (0x2U) -#define ENET_DMA_BUS_MODE_DA_SHIFT (1U) -#define ENET_DMA_BUS_MODE_DA_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DA_SHIFT) & ENET_DMA_BUS_MODE_DA_MASK) -#define ENET_DMA_BUS_MODE_DA_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DA_MASK) >> ENET_DMA_BUS_MODE_DA_SHIFT) - -/* - * SWR (RW) - * - * Software Reset - * When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. - * It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. - * Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. - * Note: - The Software reset function is driven only by this bit. - * Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - * - The reset operation is completed only when all resets in all active clock domains are de-asserted. - * Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. - * The time to complete the software reset operation depends on the frequency of the slowest active clock. - */ -#define ENET_DMA_BUS_MODE_SWR_MASK (0x1U) -#define ENET_DMA_BUS_MODE_SWR_SHIFT (0U) -#define ENET_DMA_BUS_MODE_SWR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_SWR_SHIFT) & ENET_DMA_BUS_MODE_SWR_MASK) -#define ENET_DMA_BUS_MODE_SWR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_SWR_MASK) >> ENET_DMA_BUS_MODE_SWR_SHIFT) - -/* Bitfield definition for register: DMA_TX_POLL_DEMAND */ -/* - * TPD (RW) - * - * Transmit Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the transmission resumes. - */ -#define ENET_DMA_TX_POLL_DEMAND_TPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT (0U) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SET(x) (((uint32_t)(x) << ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) -#define ENET_DMA_TX_POLL_DEMAND_TPD_GET(x) (((uint32_t)(x) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) >> ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_POLL_DEMAND */ -/* - * RPD (RW) - * - * Receive Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the Rx DMA returns to the active state. - */ -#define ENET_DMA_RX_POLL_DEMAND_RPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT (0U) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SET(x) (((uint32_t)(x) << ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) -#define ENET_DMA_RX_POLL_DEMAND_RPD_GET(x) (((uint32_t)(x) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) >> ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_DESC_LIST_ADDR */ -/* - * RDESLA (RW) - * - * Start of Receive List - * This field contains the base address of the first descriptor in the Receive Descriptor list. - * The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT (0U) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) >> ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) - -/* Bitfield definition for register: DMA_TX_DESC_LIST_ADDR */ -/* - * TDESLA (RW) - * - * Start of Transmit List - * This field contains the base address of the first descriptor in the Transmit Descriptor list. - * The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT (0U) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) >> ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) - -/* Bitfield definition for register: DMA_STATUS */ -/* - * GLPII (RW) - * - * GLPII: GMAC LPI Interrupt (for Channel 0) - * This bit indicates an interrupt event in the LPI logic of the MAC. - * To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. - * Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. - * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - * -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. - * To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. - * Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. - * Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - */ -#define ENET_DMA_STATUS_GLPII_MASK (0x40000000UL) -#define ENET_DMA_STATUS_GLPII_SHIFT (30U) -#define ENET_DMA_STATUS_GLPII_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLPII_SHIFT) & ENET_DMA_STATUS_GLPII_MASK) -#define ENET_DMA_STATUS_GLPII_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLPII_MASK) >> ENET_DMA_STATUS_GLPII_SHIFT) - -/* - * TTI (RW) - * - * Timestamp Trigger Interrupt - * This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - * When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. - * This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_TTI_MASK (0x20000000UL) -#define ENET_DMA_STATUS_TTI_SHIFT (29U) -#define ENET_DMA_STATUS_TTI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TTI_SHIFT) & ENET_DMA_STATUS_TTI_MASK) -#define ENET_DMA_STATUS_TTI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TTI_MASK) >> ENET_DMA_STATUS_TTI_SHIFT) - -/* - * GPI (RW) - * - * GMAC PMT Interrupt - * This bit indicates an interrupt event in the PMT module of the DWC_gmac. - * The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the Power Management feature is enabled. - * Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - */ -#define ENET_DMA_STATUS_GPI_MASK (0x10000000UL) -#define ENET_DMA_STATUS_GPI_SHIFT (28U) -#define ENET_DMA_STATUS_GPI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GPI_SHIFT) & ENET_DMA_STATUS_GPI_MASK) -#define ENET_DMA_STATUS_GPI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GPI_MASK) >> ENET_DMA_STATUS_GPI_SHIFT) - -/* - * GMI (RW) - * - * GMAC MMC Interrupt - * This bit reflects an interrupt event in the MMC module of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac - * to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_GMI_MASK (0x8000000UL) -#define ENET_DMA_STATUS_GMI_SHIFT (27U) -#define ENET_DMA_STATUS_GMI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GMI_SHIFT) & ENET_DMA_STATUS_GMI_MASK) -#define ENET_DMA_STATUS_GMI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GMI_MASK) >> ENET_DMA_STATUS_GMI_SHIFT) - -/* - * GLI (RW) - * - * GMAC Line Interface Interrupt - * When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - * - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - * - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - * Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - * the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - * read any of the following corresponding registers: - * - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - * - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - * - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - */ -#define ENET_DMA_STATUS_GLI_MASK (0x4000000UL) -#define ENET_DMA_STATUS_GLI_SHIFT (26U) -#define ENET_DMA_STATUS_GLI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLI_SHIFT) & ENET_DMA_STATUS_GLI_MASK) -#define ENET_DMA_STATUS_GLI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLI_MASK) >> ENET_DMA_STATUS_GLI_SHIFT) - -/* - * EB (RW) - * - * Error Bits - * This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - * This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. - * - 0 0 0: Error during Rx DMA Write Data Transfer - * - 0 1 1: Error during Tx DMA Read Data Transfer - * - 1 0 0: Error during Rx DMA Descriptor Write Access - * - 1 0 1: Error during Tx DMA Descriptor Write Access - * - 1 1 0: Error during Rx DMA Descriptor Read Access - * - 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - */ -#define ENET_DMA_STATUS_EB_MASK (0x3800000UL) -#define ENET_DMA_STATUS_EB_SHIFT (23U) -#define ENET_DMA_STATUS_EB_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_EB_SHIFT) & ENET_DMA_STATUS_EB_MASK) -#define ENET_DMA_STATUS_EB_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_EB_MASK) >> ENET_DMA_STATUS_EB_SHIFT) - -/* - * TS (RW) - * - * Transmit Process State - * This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped; Reset or Stop Transmit Command issued - * - 3’b001: Running; Fetching Transmit Transfer Descriptor - * - 3’b010: Running; Waiting for status - * - 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) - * - 3’b100: TIME_STAMP write state - * - 3’b101: Reserved for future use - * - 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow - * - 3’b111: Running; Closing Transmit Descriptor - */ -#define ENET_DMA_STATUS_TS_MASK (0x700000UL) -#define ENET_DMA_STATUS_TS_SHIFT (20U) -#define ENET_DMA_STATUS_TS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TS_SHIFT) & ENET_DMA_STATUS_TS_MASK) -#define ENET_DMA_STATUS_TS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TS_MASK) >> ENET_DMA_STATUS_TS_SHIFT) - -/* - * RS (RW) - * - * Receive Process State - * This field indicates the Receive DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped: Reset or Stop Receive Command issued - * - 3’b001: Running: Fetching Receive Transfer Descriptor - * - 3’b010: Reserved for future use - * - 3’b011: Running: Waiting for receive packet - * - 3’b100: Suspended: Receive Descriptor Unavailable - * - 3’b101: Running: Closing Receive Descriptor - * - 3’b110: TIME_STAMP write state - * - 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - */ -#define ENET_DMA_STATUS_RS_MASK (0xE0000UL) -#define ENET_DMA_STATUS_RS_SHIFT (17U) -#define ENET_DMA_STATUS_RS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RS_SHIFT) & ENET_DMA_STATUS_RS_MASK) -#define ENET_DMA_STATUS_RS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RS_MASK) >> ENET_DMA_STATUS_RS_SHIFT) - -/* - * NIS (RW) - * - * Normal Interrupt Summary - * Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in - * Register 7 (Interrupt Enable Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt Only unmasked bits - * (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_NIS_MASK (0x10000UL) -#define ENET_DMA_STATUS_NIS_SHIFT (16U) -#define ENET_DMA_STATUS_NIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_NIS_SHIFT) & ENET_DMA_STATUS_NIS_MASK) -#define ENET_DMA_STATUS_NIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_NIS_MASK) >> ENET_DMA_STATUS_NIS_SHIFT) - -/* - * AIS (RW) - * - * Abnormal Interrupt Summary - * Abnormal Interrupt Summary bit value is the logical OR of the following - * when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive FIFO Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_AIS_MASK (0x8000U) -#define ENET_DMA_STATUS_AIS_SHIFT (15U) -#define ENET_DMA_STATUS_AIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_AIS_SHIFT) & ENET_DMA_STATUS_AIS_MASK) -#define ENET_DMA_STATUS_AIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_AIS_MASK) >> ENET_DMA_STATUS_AIS_SHIFT) - -/* - * ERI (RW) - * - * Early Receive Interrupt - * This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - */ -#define ENET_DMA_STATUS_ERI_MASK (0x4000U) -#define ENET_DMA_STATUS_ERI_SHIFT (14U) -#define ENET_DMA_STATUS_ERI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ERI_SHIFT) & ENET_DMA_STATUS_ERI_MASK) -#define ENET_DMA_STATUS_ERI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ERI_MASK) >> ENET_DMA_STATUS_ERI_SHIFT) - -/* - * FBI (RW) - * - * Fatal Bus Error Interrupt - * This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - */ -#define ENET_DMA_STATUS_FBI_MASK (0x2000U) -#define ENET_DMA_STATUS_FBI_SHIFT (13U) -#define ENET_DMA_STATUS_FBI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_FBI_SHIFT) & ENET_DMA_STATUS_FBI_MASK) -#define ENET_DMA_STATUS_FBI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_FBI_MASK) >> ENET_DMA_STATUS_FBI_SHIFT) - -/* - * ETI (RW) - * - * Early Transmit Interrupt - * This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - */ -#define ENET_DMA_STATUS_ETI_MASK (0x400U) -#define ENET_DMA_STATUS_ETI_SHIFT (10U) -#define ENET_DMA_STATUS_ETI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ETI_SHIFT) & ENET_DMA_STATUS_ETI_MASK) -#define ENET_DMA_STATUS_ETI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ETI_MASK) >> ENET_DMA_STATUS_ETI_SHIFT) - -/* - * RWT (RW) - * - * Receive Watchdog Timeout - * When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - */ -#define ENET_DMA_STATUS_RWT_MASK (0x200U) -#define ENET_DMA_STATUS_RWT_SHIFT (9U) -#define ENET_DMA_STATUS_RWT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RWT_SHIFT) & ENET_DMA_STATUS_RWT_MASK) -#define ENET_DMA_STATUS_RWT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RWT_MASK) >> ENET_DMA_STATUS_RWT_SHIFT) - -/* - * RPS (RW) - * - * Receive Process Stopped - * This bit is asserted when the Receive Process enters the Stopped state. - */ -#define ENET_DMA_STATUS_RPS_MASK (0x100U) -#define ENET_DMA_STATUS_RPS_SHIFT (8U) -#define ENET_DMA_STATUS_RPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RPS_SHIFT) & ENET_DMA_STATUS_RPS_MASK) -#define ENET_DMA_STATUS_RPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RPS_MASK) >> ENET_DMA_STATUS_RPS_SHIFT) - -/* - * RU (RW) - * - * Receive Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. - * The Receive Process is suspended. To resume processing Receive descriptors, - * the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - * If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. - * This bit is set only when the previous Receive Descriptor is owned by the DMA. - */ -#define ENET_DMA_STATUS_RU_MASK (0x80U) -#define ENET_DMA_STATUS_RU_SHIFT (7U) -#define ENET_DMA_STATUS_RU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RU_SHIFT) & ENET_DMA_STATUS_RU_MASK) -#define ENET_DMA_STATUS_RU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RU_MASK) >> ENET_DMA_STATUS_RU_SHIFT) - -/* - * RI (RW) - * - * Receive Interrupt - * This bit indicates that the frame reception is complete. - * When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, - * and the specific frame status information is updated in the descriptor. - * The reception remains in the Running state. - */ -#define ENET_DMA_STATUS_RI_MASK (0x40U) -#define ENET_DMA_STATUS_RI_SHIFT (6U) -#define ENET_DMA_STATUS_RI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RI_SHIFT) & ENET_DMA_STATUS_RI_MASK) -#define ENET_DMA_STATUS_RI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RI_MASK) >> ENET_DMA_STATUS_RI_SHIFT) - -/* - * UNF (RW) - * - * Transmit Underflow - * This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - */ -#define ENET_DMA_STATUS_UNF_MASK (0x20U) -#define ENET_DMA_STATUS_UNF_SHIFT (5U) -#define ENET_DMA_STATUS_UNF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_UNF_SHIFT) & ENET_DMA_STATUS_UNF_MASK) -#define ENET_DMA_STATUS_UNF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_UNF_MASK) >> ENET_DMA_STATUS_UNF_SHIFT) - -/* - * OVF (RW) - * - * Receive Overflow - * This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - */ -#define ENET_DMA_STATUS_OVF_MASK (0x10U) -#define ENET_DMA_STATUS_OVF_SHIFT (4U) -#define ENET_DMA_STATUS_OVF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_OVF_SHIFT) & ENET_DMA_STATUS_OVF_MASK) -#define ENET_DMA_STATUS_OVF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_OVF_MASK) >> ENET_DMA_STATUS_OVF_SHIFT) - -/* - * TJT (RW) - * - * Transmit Jabber Timeout - * This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). - * When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - */ -#define ENET_DMA_STATUS_TJT_MASK (0x8U) -#define ENET_DMA_STATUS_TJT_SHIFT (3U) -#define ENET_DMA_STATUS_TJT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TJT_SHIFT) & ENET_DMA_STATUS_TJT_MASK) -#define ENET_DMA_STATUS_TJT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TJT_MASK) >> ENET_DMA_STATUS_TJT_SHIFT) - -/* - * TU (RW) - * - * Transmit Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. - * To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - */ -#define ENET_DMA_STATUS_TU_MASK (0x4U) -#define ENET_DMA_STATUS_TU_SHIFT (2U) -#define ENET_DMA_STATUS_TU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TU_SHIFT) & ENET_DMA_STATUS_TU_MASK) -#define ENET_DMA_STATUS_TU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TU_MASK) >> ENET_DMA_STATUS_TU_SHIFT) - -/* - * TPS (RW) - * - * Transmit Process Stopped - * This bit is set when the transmission is stopped. - */ -#define ENET_DMA_STATUS_TPS_MASK (0x2U) -#define ENET_DMA_STATUS_TPS_SHIFT (1U) -#define ENET_DMA_STATUS_TPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TPS_SHIFT) & ENET_DMA_STATUS_TPS_MASK) -#define ENET_DMA_STATUS_TPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TPS_MASK) >> ENET_DMA_STATUS_TPS_SHIFT) - -/* - * TI (RW) - * - * Transmit Interrupt - * This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - */ -#define ENET_DMA_STATUS_TI_MASK (0x1U) -#define ENET_DMA_STATUS_TI_SHIFT (0U) -#define ENET_DMA_STATUS_TI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TI_SHIFT) & ENET_DMA_STATUS_TI_MASK) -#define ENET_DMA_STATUS_TI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TI_MASK) >> ENET_DMA_STATUS_TI_SHIFT) - -/* Bitfield definition for register: DMA_OP_MODE */ -/* - * DT (RW) - * - * Disable Dropping of TCP/IP Checksum Error Frames - * When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - * Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. - * When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - */ -#define ENET_DMA_OP_MODE_DT_MASK (0x10000000UL) -#define ENET_DMA_OP_MODE_DT_SHIFT (28U) -#define ENET_DMA_OP_MODE_DT_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DT_SHIFT) & ENET_DMA_OP_MODE_DT_MASK) -#define ENET_DMA_OP_MODE_DT_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DT_MASK) >> ENET_DMA_OP_MODE_DT_SHIFT) - -/* - * RSF (RW) - * - * Receive Store and Forward - * When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - * When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - */ -#define ENET_DMA_OP_MODE_RSF_MASK (0x2000000UL) -#define ENET_DMA_OP_MODE_RSF_SHIFT (25U) -#define ENET_DMA_OP_MODE_RSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RSF_SHIFT) & ENET_DMA_OP_MODE_RSF_MASK) -#define ENET_DMA_OP_MODE_RSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RSF_MASK) >> ENET_DMA_OP_MODE_RSF_SHIFT) - -/* - * DFF (RW) - * - * Disable Flushing of Received Frames - * When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - */ -#define ENET_DMA_OP_MODE_DFF_MASK (0x1000000UL) -#define ENET_DMA_OP_MODE_DFF_SHIFT (24U) -#define ENET_DMA_OP_MODE_DFF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DFF_SHIFT) & ENET_DMA_OP_MODE_DFF_MASK) -#define ENET_DMA_OP_MODE_DFF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DFF_MASK) >> ENET_DMA_OP_MODE_DFF_SHIFT) - -/* - * RFA_2 (RW) - * - * MSB of Threshold for Activating Flow Control - * If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFA_2_MASK (0x800000UL) -#define ENET_DMA_OP_MODE_RFA_2_SHIFT (23U) -#define ENET_DMA_OP_MODE_RFA_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_2_SHIFT) & ENET_DMA_OP_MODE_RFA_2_MASK) -#define ENET_DMA_OP_MODE_RFA_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_2_MASK) >> ENET_DMA_OP_MODE_RFA_2_SHIFT) - -/* - * RFD_2 (RW) - * - * MSB of Threshold for Deactivating Flow Control - * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFD_2_MASK (0x400000UL) -#define ENET_DMA_OP_MODE_RFD_2_SHIFT (22U) -#define ENET_DMA_OP_MODE_RFD_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_2_SHIFT) & ENET_DMA_OP_MODE_RFD_2_MASK) -#define ENET_DMA_OP_MODE_RFD_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_2_MASK) >> ENET_DMA_OP_MODE_RFD_2_SHIFT) - -/* - * TSF (RW) - * - * Transmit Store and Forward - * When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. - * When this bit is set, the TTC values specified in Bits [16:14] are ignored. - * This bit should be changed only when the transmission is stopped. - */ -#define ENET_DMA_OP_MODE_TSF_MASK (0x200000UL) -#define ENET_DMA_OP_MODE_TSF_SHIFT (21U) -#define ENET_DMA_OP_MODE_TSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TSF_SHIFT) & ENET_DMA_OP_MODE_TSF_MASK) -#define ENET_DMA_OP_MODE_TSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TSF_MASK) >> ENET_DMA_OP_MODE_TSF_SHIFT) - -/* - * FTF (RW) - * - * Flush Transmit FIFO - * When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. - * This bit is cleared internally when the flushing operation is complete. - * The Operation Mode register should not be written to until this bit is cleared. - * The data which is already accepted by the MAC transmitter is not flushed. - * It is scheduled for transmission and results in underflow and runt frame transmission. - */ -#define ENET_DMA_OP_MODE_FTF_MASK (0x100000UL) -#define ENET_DMA_OP_MODE_FTF_SHIFT (20U) -#define ENET_DMA_OP_MODE_FTF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FTF_SHIFT) & ENET_DMA_OP_MODE_FTF_MASK) -#define ENET_DMA_OP_MODE_FTF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FTF_MASK) >> ENET_DMA_OP_MODE_FTF_SHIFT) - -/* - * TTC (RW) - * - * Transmit Threshold Control - * These bits control the threshold level of the MTL Transmit FIFO. - * Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. - * In addition, full frames with a length less than the threshold are also transmitted. - * These bits are used only when Bit 21 (TSF) is reset. - * - 000: 64 - * - 001: 128 - * - 010: 192 - * - 011: 256 - * - 100: 40 - * - 101: 32 - * - 110: 24 - * - 111: 16 - */ -#define ENET_DMA_OP_MODE_TTC_MASK (0x1C000UL) -#define ENET_DMA_OP_MODE_TTC_SHIFT (14U) -#define ENET_DMA_OP_MODE_TTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TTC_SHIFT) & ENET_DMA_OP_MODE_TTC_MASK) -#define ENET_DMA_OP_MODE_TTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TTC_MASK) >> ENET_DMA_OP_MODE_TTC_SHIFT) - -/* - * ST (RW) - * - * Start or Stop Transmission Command - * When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. - * Descriptor acquisition is attempted either from the current position in the list, - * which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), - * or from the position retained when transmission was stopped previously. - * If the DMA does not own the current descriptor, - * transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Transmission command is effective only when transmission is stopped. - * If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - * then the DMA behavior is unpredictable. When this bit is reset, - * the transmission process is placed in the Stopped state after completing the transmission of the current frame. - * The Next Descriptor position in the Transmit List is saved, - * and it becomes the current position when transmission is restarted. - * To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. - * The new value is considered when this bit is set again. - * The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - */ -#define ENET_DMA_OP_MODE_ST_MASK (0x2000U) -#define ENET_DMA_OP_MODE_ST_SHIFT (13U) -#define ENET_DMA_OP_MODE_ST_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_ST_SHIFT) & ENET_DMA_OP_MODE_ST_MASK) -#define ENET_DMA_OP_MODE_ST_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_ST_MASK) >> ENET_DMA_OP_MODE_ST_SHIFT) - -/* - * RFD (RW) - * - * Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. - * - 00: Full minus 1 KB, that is, FULL — 1 KB - * - 01: Full minus 2 KB, that is, FULL — 2 KB - * - 10: Full minus 3 KB, that is, FULL — 3 KB - * - 11: Full minus 4 KB, that is, FULL — 4 KB - * The de-assertion is effective only after flow control is asserted. - * If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. - * These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_RFD_MASK (0x1800U) -#define ENET_DMA_OP_MODE_RFD_SHIFT (11U) -#define ENET_DMA_OP_MODE_RFD_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_SHIFT) & ENET_DMA_OP_MODE_RFD_MASK) -#define ENET_DMA_OP_MODE_RFD_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_MASK) >> ENET_DMA_OP_MODE_RFD_SHIFT) - -/* - * RFA (RW) - * - * Threshold for Activating Flow Control (in half-duplex and full-duplex modes) - * These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. - * - 00: Full minus 1 KB, that is, FULL—1KB. - * - 01: Full minus 2 KB, that is, FULL—2KB. - * - 10: Full minus 3 KB, that is, FULL—3KB. - * - 11: Full minus 4 KB, that is, FULL—4KB. - * These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, - * an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. - * These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. - * Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, - * the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - */ -#define ENET_DMA_OP_MODE_RFA_MASK (0x600U) -#define ENET_DMA_OP_MODE_RFA_SHIFT (9U) -#define ENET_DMA_OP_MODE_RFA_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_SHIFT) & ENET_DMA_OP_MODE_RFA_MASK) -#define ENET_DMA_OP_MODE_RFA_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_MASK) >> ENET_DMA_OP_MODE_RFA_SHIFT) - -/* - * EFC (RW) - * - * Enable HW Flow Control - * When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. - * When reset, the flow control operation is disabled. - * This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_EFC_MASK (0x100U) -#define ENET_DMA_OP_MODE_EFC_SHIFT (8U) -#define ENET_DMA_OP_MODE_EFC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_EFC_SHIFT) & ENET_DMA_OP_MODE_EFC_MASK) -#define ENET_DMA_OP_MODE_EFC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_EFC_MASK) >> ENET_DMA_OP_MODE_EFC_SHIFT) - -/* - * FEF (RW) - * - * Forward Error Frames - * When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). - * However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), - * then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, - * the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. - * When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. - * If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, - * then the frame is dropped irrespective of the FEF bit setting. - * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. - * Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - * - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - * - The advanced timestamp feature is not selected but the extended status is selected. - * The extended status is available with the following features: - * - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - * - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - */ -#define ENET_DMA_OP_MODE_FEF_MASK (0x80U) -#define ENET_DMA_OP_MODE_FEF_SHIFT (7U) -#define ENET_DMA_OP_MODE_FEF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FEF_SHIFT) & ENET_DMA_OP_MODE_FEF_MASK) -#define ENET_DMA_OP_MODE_FEF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FEF_MASK) >> ENET_DMA_OP_MODE_FEF_SHIFT) - -/* - * FUF (RW) - * - * Forward Undersized Good Frames - * When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC - * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - */ -#define ENET_DMA_OP_MODE_FUF_MASK (0x40U) -#define ENET_DMA_OP_MODE_FUF_SHIFT (6U) -#define ENET_DMA_OP_MODE_FUF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FUF_SHIFT) & ENET_DMA_OP_MODE_FUF_MASK) -#define ENET_DMA_OP_MODE_FUF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FUF_MASK) >> ENET_DMA_OP_MODE_FUF_SHIFT) - -/* - * DGF (RW) - * - * Drop Giant Frames - * When set, the MAC drops the received giant frames in the Rx FIFO, - * that is, frames that are larger than the computed giant frame limit. - * When reset, the MAC does not drop the giant frames in the Rx FIFO. - * Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - * - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - * - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - * - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - */ -#define ENET_DMA_OP_MODE_DGF_MASK (0x20U) -#define ENET_DMA_OP_MODE_DGF_SHIFT (5U) -#define ENET_DMA_OP_MODE_DGF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DGF_SHIFT) & ENET_DMA_OP_MODE_DGF_MASK) -#define ENET_DMA_OP_MODE_DGF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DGF_MASK) >> ENET_DMA_OP_MODE_DGF_SHIFT) - -/* - * RTC (RW) - * - * Receive Threshold Control - * These two bits control the threshold level of the MTL Receive FIFO. - * Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. - * In addition, full frames with length less than the threshold are automatically transferred. - * The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. - * These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. - * - 00: 64 - * - 01: 32 - * - 10: 96 - * - 11: 128 - */ -#define ENET_DMA_OP_MODE_RTC_MASK (0x18U) -#define ENET_DMA_OP_MODE_RTC_SHIFT (3U) -#define ENET_DMA_OP_MODE_RTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RTC_SHIFT) & ENET_DMA_OP_MODE_RTC_MASK) -#define ENET_DMA_OP_MODE_RTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RTC_MASK) >> ENET_DMA_OP_MODE_RTC_SHIFT) - -/* - * OSF (RW) - * - * Operate on Second Frame - * When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - */ -#define ENET_DMA_OP_MODE_OSF_MASK (0x4U) -#define ENET_DMA_OP_MODE_OSF_SHIFT (2U) -#define ENET_DMA_OP_MODE_OSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_OSF_SHIFT) & ENET_DMA_OP_MODE_OSF_MASK) -#define ENET_DMA_OP_MODE_OSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_OSF_MASK) >> ENET_DMA_OP_MODE_OSF_SHIFT) - -/* - * SR (RW) - * - * Start or Stop Receive - * When this bit is set, the Receive process is placed in the Running state. - * The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. - * The descriptor acquisition is attempted from the current position in the list, - * which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. - * If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Receive command is effective only when the reception has stopped. - * If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. - * When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. - * The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. - * The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - */ -#define ENET_DMA_OP_MODE_SR_MASK (0x2U) -#define ENET_DMA_OP_MODE_SR_SHIFT (1U) -#define ENET_DMA_OP_MODE_SR_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_SR_SHIFT) & ENET_DMA_OP_MODE_SR_MASK) -#define ENET_DMA_OP_MODE_SR_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_SR_MASK) >> ENET_DMA_OP_MODE_SR_SHIFT) - -/* Bitfield definition for register: DMA_INTR_EN */ -/* - * NIE (RW) - * - * Normal Interrupt Summary Enable - * When this bit is set, normal interrupt summary is enabled. - * When this bit is reset, normal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt - */ -#define ENET_DMA_INTR_EN_NIE_MASK (0x10000UL) -#define ENET_DMA_INTR_EN_NIE_SHIFT (16U) -#define ENET_DMA_INTR_EN_NIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_NIE_SHIFT) & ENET_DMA_INTR_EN_NIE_MASK) -#define ENET_DMA_INTR_EN_NIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_NIE_MASK) >> ENET_DMA_INTR_EN_NIE_SHIFT) - -/* - * AIE (RW) - * - * Abnormal Interrupt Summary Enable - * When this bit is set, abnormal interrupt summary is enabled. - * When this bit is reset, the abnormal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error - */ -#define ENET_DMA_INTR_EN_AIE_MASK (0x8000U) -#define ENET_DMA_INTR_EN_AIE_SHIFT (15U) -#define ENET_DMA_INTR_EN_AIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_AIE_SHIFT) & ENET_DMA_INTR_EN_AIE_MASK) -#define ENET_DMA_INTR_EN_AIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_AIE_MASK) >> ENET_DMA_INTR_EN_AIE_SHIFT) - -/* - * ERE (RW) - * - * Early Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ERE_MASK (0x4000U) -#define ENET_DMA_INTR_EN_ERE_SHIFT (14U) -#define ENET_DMA_INTR_EN_ERE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ERE_SHIFT) & ENET_DMA_INTR_EN_ERE_MASK) -#define ENET_DMA_INTR_EN_ERE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ERE_MASK) >> ENET_DMA_INTR_EN_ERE_SHIFT) - -/* - * FBE (RW) - * - * Fatal Bus Error Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_FBE_MASK (0x2000U) -#define ENET_DMA_INTR_EN_FBE_SHIFT (13U) -#define ENET_DMA_INTR_EN_FBE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_FBE_SHIFT) & ENET_DMA_INTR_EN_FBE_MASK) -#define ENET_DMA_INTR_EN_FBE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_FBE_MASK) >> ENET_DMA_INTR_EN_FBE_SHIFT) - -/* - * ETE (RW) - * - * Early Transmit Interrupt Enable - * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ETE_MASK (0x400U) -#define ENET_DMA_INTR_EN_ETE_SHIFT (10U) -#define ENET_DMA_INTR_EN_ETE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ETE_SHIFT) & ENET_DMA_INTR_EN_ETE_MASK) -#define ENET_DMA_INTR_EN_ETE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ETE_MASK) >> ENET_DMA_INTR_EN_ETE_SHIFT) - -/* - * RWE (RW) - * - * Receive Watchdog Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RWE_MASK (0x200U) -#define ENET_DMA_INTR_EN_RWE_SHIFT (9U) -#define ENET_DMA_INTR_EN_RWE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RWE_SHIFT) & ENET_DMA_INTR_EN_RWE_MASK) -#define ENET_DMA_INTR_EN_RWE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RWE_MASK) >> ENET_DMA_INTR_EN_RWE_SHIFT) - -/* - * RSE (RW) - * - * Receive Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RSE_MASK (0x100U) -#define ENET_DMA_INTR_EN_RSE_SHIFT (8U) -#define ENET_DMA_INTR_EN_RSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RSE_SHIFT) & ENET_DMA_INTR_EN_RSE_MASK) -#define ENET_DMA_INTR_EN_RSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RSE_MASK) >> ENET_DMA_INTR_EN_RSE_SHIFT) - -/* - * RUE (RW) - * - * Receive Buffer Unavailable Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RUE_MASK (0x80U) -#define ENET_DMA_INTR_EN_RUE_SHIFT (7U) -#define ENET_DMA_INTR_EN_RUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RUE_SHIFT) & ENET_DMA_INTR_EN_RUE_MASK) -#define ENET_DMA_INTR_EN_RUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RUE_MASK) >> ENET_DMA_INTR_EN_RUE_SHIFT) - -/* - * RIE (RW) - * - * Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RIE_MASK (0x40U) -#define ENET_DMA_INTR_EN_RIE_SHIFT (6U) -#define ENET_DMA_INTR_EN_RIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RIE_SHIFT) & ENET_DMA_INTR_EN_RIE_MASK) -#define ENET_DMA_INTR_EN_RIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RIE_MASK) >> ENET_DMA_INTR_EN_RIE_SHIFT) - -/* - * UNE (RW) - * - * Underflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_UNE_MASK (0x20U) -#define ENET_DMA_INTR_EN_UNE_SHIFT (5U) -#define ENET_DMA_INTR_EN_UNE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_UNE_SHIFT) & ENET_DMA_INTR_EN_UNE_MASK) -#define ENET_DMA_INTR_EN_UNE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_UNE_MASK) >> ENET_DMA_INTR_EN_UNE_SHIFT) - -/* - * OVE (RW) - * - * Overflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_OVE_MASK (0x10U) -#define ENET_DMA_INTR_EN_OVE_SHIFT (4U) -#define ENET_DMA_INTR_EN_OVE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_OVE_SHIFT) & ENET_DMA_INTR_EN_OVE_MASK) -#define ENET_DMA_INTR_EN_OVE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_OVE_MASK) >> ENET_DMA_INTR_EN_OVE_SHIFT) - -/* - * TJE (RW) - * - * Transmit Jabber Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TJE_MASK (0x8U) -#define ENET_DMA_INTR_EN_TJE_SHIFT (3U) -#define ENET_DMA_INTR_EN_TJE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TJE_SHIFT) & ENET_DMA_INTR_EN_TJE_MASK) -#define ENET_DMA_INTR_EN_TJE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TJE_MASK) >> ENET_DMA_INTR_EN_TJE_SHIFT) - -/* - * TUE (RW) - * - * Transmit Buffer Unavailable Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TUE_MASK (0x4U) -#define ENET_DMA_INTR_EN_TUE_SHIFT (2U) -#define ENET_DMA_INTR_EN_TUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TUE_SHIFT) & ENET_DMA_INTR_EN_TUE_MASK) -#define ENET_DMA_INTR_EN_TUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TUE_MASK) >> ENET_DMA_INTR_EN_TUE_SHIFT) - -/* - * TSE (RW) - * - * Transmit Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TSE_MASK (0x2U) -#define ENET_DMA_INTR_EN_TSE_SHIFT (1U) -#define ENET_DMA_INTR_EN_TSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TSE_SHIFT) & ENET_DMA_INTR_EN_TSE_MASK) -#define ENET_DMA_INTR_EN_TSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TSE_MASK) >> ENET_DMA_INTR_EN_TSE_SHIFT) - -/* - * TIE (RW) - * - * Transmit Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TIE_MASK (0x1U) -#define ENET_DMA_INTR_EN_TIE_SHIFT (0U) -#define ENET_DMA_INTR_EN_TIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TIE_SHIFT) & ENET_DMA_INTR_EN_TIE_MASK) -#define ENET_DMA_INTR_EN_TIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TIE_MASK) >> ENET_DMA_INTR_EN_TIE_SHIFT) - -/* Bitfield definition for register: DMA_MISS_OVF_CNT */ -/* - * ONFCNTOVF (RW) - * - * Overflow Bit for FIFO Overflow Counter - * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, - * that is, the Rx FIFO overflows with the overflow frame counter at maximum value. - * In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK (0x10000000UL) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT (28U) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) - -/* - * OVFFRMCNT (RW) - * - * Overflow Frame Counter - * This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK (0xFFE0000UL) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT (17U) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) - -/* - * MISCNTOVF (RW) - * - * Overflow Bit for Missed Frame Counter - * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, - * that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - * the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK (0x10000UL) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT (16U) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) - -/* - * MISFRMCNT (RW) - * - * Missed Frame Counter - * This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. - * This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK (0xFFFFU) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT (0U) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) - -/* Bitfield definition for register: DMA_RX_INTR_WDOG */ -/* - * RIWT (RW) - * - * RI Watchdog Timer Count - * This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. - * The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer - * of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. - * When the watchdog timer runs out, the RI bit is set and the timer is stopped. - * The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - */ -#define ENET_DMA_RX_INTR_WDOG_RIWT_MASK (0xFFU) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT (0U) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SET(x) (((uint32_t)(x) << ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) -#define ENET_DMA_RX_INTR_WDOG_RIWT_GET(x) (((uint32_t)(x) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) >> ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) - -/* Bitfield definition for register: DMA_AXI_MODE */ -/* - * EN_LPI (RW) - * - * Enable Low Power Interface (LPI) - * When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. - * When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - */ -#define ENET_DMA_AXI_MODE_EN_LPI_MASK (0x80000000UL) -#define ENET_DMA_AXI_MODE_EN_LPI_SHIFT (31U) -#define ENET_DMA_AXI_MODE_EN_LPI_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_EN_LPI_SHIFT) & ENET_DMA_AXI_MODE_EN_LPI_MASK) -#define ENET_DMA_AXI_MODE_EN_LPI_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_EN_LPI_MASK) >> ENET_DMA_AXI_MODE_EN_LPI_SHIFT) - -/* - * LPI_XIT_FRM (RW) - * - * Unlock on Magic Packet or Remote Wake-Up Frame - * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. - * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - */ -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK (0x40000000UL) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT (30U) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) >> ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) - -/* - * WR_OSR_LMT (RW) - * - * AXI Maximum Write Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI write interface. - * Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK (0xF00000UL) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT (20U) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) - -/* - * RD_OSR_LMT (RW) - * - * AXI Maximum Read Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI read interface. - * Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK (0xF0000UL) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT (16U) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) - -/* - * ONEKBBE (RW) - * - * 1 KB Boundary Crossing Enable for the GMAC-AXI Master - * When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. - * When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - */ -#define ENET_DMA_AXI_MODE_ONEKBBE_MASK (0x2000U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SHIFT (13U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) -#define ENET_DMA_AXI_MODE_ONEKBBE_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) >> ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) - -/* - * AXI_AAL (RW) - * - * Address-Aligned Beats - * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). - * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - */ -#define ENET_DMA_AXI_MODE_AXI_AAL_MASK (0x1000U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SHIFT (12U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) -#define ENET_DMA_AXI_MODE_AXI_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) >> ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) - -/* - * BLEN256 (RW) - * - * AXI Burst Length 256 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN256_MASK (0x80U) -#define ENET_DMA_AXI_MODE_BLEN256_SHIFT (7U) -#define ENET_DMA_AXI_MODE_BLEN256_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN256_SHIFT) & ENET_DMA_AXI_MODE_BLEN256_MASK) -#define ENET_DMA_AXI_MODE_BLEN256_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN256_MASK) >> ENET_DMA_AXI_MODE_BLEN256_SHIFT) - -/* - * BLEN128 (RW) - * - * AXI Burst Length 128 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN128_MASK (0x40U) -#define ENET_DMA_AXI_MODE_BLEN128_SHIFT (6U) -#define ENET_DMA_AXI_MODE_BLEN128_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN128_SHIFT) & ENET_DMA_AXI_MODE_BLEN128_MASK) -#define ENET_DMA_AXI_MODE_BLEN128_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN128_MASK) >> ENET_DMA_AXI_MODE_BLEN128_SHIFT) - -/* - * BLEN64 (RW) - * - * AXI Burst Length 64 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN64_MASK (0x20U) -#define ENET_DMA_AXI_MODE_BLEN64_SHIFT (5U) -#define ENET_DMA_AXI_MODE_BLEN64_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN64_SHIFT) & ENET_DMA_AXI_MODE_BLEN64_MASK) -#define ENET_DMA_AXI_MODE_BLEN64_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN64_MASK) >> ENET_DMA_AXI_MODE_BLEN64_SHIFT) - -/* - * BLEN32 (RW) - * - * AXI Burst Length 32 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN32_MASK (0x10U) -#define ENET_DMA_AXI_MODE_BLEN32_SHIFT (4U) -#define ENET_DMA_AXI_MODE_BLEN32_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN32_SHIFT) & ENET_DMA_AXI_MODE_BLEN32_MASK) -#define ENET_DMA_AXI_MODE_BLEN32_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN32_MASK) >> ENET_DMA_AXI_MODE_BLEN32_SHIFT) - -/* - * BLEN16 (RW) - * - * AXI Burst Length 16 - * When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - */ -#define ENET_DMA_AXI_MODE_BLEN16_MASK (0x8U) -#define ENET_DMA_AXI_MODE_BLEN16_SHIFT (3U) -#define ENET_DMA_AXI_MODE_BLEN16_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN16_SHIFT) & ENET_DMA_AXI_MODE_BLEN16_MASK) -#define ENET_DMA_AXI_MODE_BLEN16_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN16_MASK) >> ENET_DMA_AXI_MODE_BLEN16_SHIFT) - -/* - * BLEN8 (RW) - * - * AXI Burst Length 8 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN8_MASK (0x4U) -#define ENET_DMA_AXI_MODE_BLEN8_SHIFT (2U) -#define ENET_DMA_AXI_MODE_BLEN8_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN8_SHIFT) & ENET_DMA_AXI_MODE_BLEN8_MASK) -#define ENET_DMA_AXI_MODE_BLEN8_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN8_MASK) >> ENET_DMA_AXI_MODE_BLEN8_SHIFT) - -/* - * BLEN4 (RW) - * - * AXI Burst Length 4 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN4_MASK (0x2U) -#define ENET_DMA_AXI_MODE_BLEN4_SHIFT (1U) -#define ENET_DMA_AXI_MODE_BLEN4_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN4_SHIFT) & ENET_DMA_AXI_MODE_BLEN4_MASK) -#define ENET_DMA_AXI_MODE_BLEN4_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN4_MASK) >> ENET_DMA_AXI_MODE_BLEN4_SHIFT) - -/* - * UNDEF (RW) - * - * AXI Undefined Burst Length - * This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - * - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - * - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. - * If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - */ -#define ENET_DMA_AXI_MODE_UNDEF_MASK (0x1U) -#define ENET_DMA_AXI_MODE_UNDEF_SHIFT (0U) -#define ENET_DMA_AXI_MODE_UNDEF_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_UNDEF_SHIFT) & ENET_DMA_AXI_MODE_UNDEF_MASK) -#define ENET_DMA_AXI_MODE_UNDEF_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_UNDEF_MASK) >> ENET_DMA_AXI_MODE_UNDEF_SHIFT) - -/* Bitfield definition for register: DMA_BUS_STATUS */ -/* - * AXIRDSTS (RW) - * - * AXI Master Read Channel Status - * When high, it indicates that AXI master's read channel is active and transferring data. - */ -#define ENET_DMA_BUS_STATUS_AXIRDSTS_MASK (0x2U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT (1U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) >> ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) - -/* - * AXWHSTS (RW) - * - * AXI Master Write Channel or AHB Master Status - * When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - * it indicates that the AHB master interface FSMs are in the non-idle state. - */ -#define ENET_DMA_BUS_STATUS_AXWHSTS_MASK (0x1U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT (0U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXWHSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) >> ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_DESC */ -/* - * CURTDESAPTR (RW) - * - * Host Transmit Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_DESC */ -/* - * CURRDESAPTR (RW) - * - * Host Receive Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_BUF */ -/* - * CURTBUFAPTR (RW) - * - * Host Transmit Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_BUF */ -/* - * CURRBUFAPTR (RW) - * - * Host Receive Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) - - - -/* MAC_ADDR register group index macro definition */ -#define ENET_MAC_ADDR_1 (0UL) -#define ENET_MAC_ADDR_2 (1UL) -#define ENET_MAC_ADDR_3 (2UL) -#define ENET_MAC_ADDR_4 (3UL) - -/* L3_L4_CFG register group index macro definition */ -#define ENET_L3_L4_CFG_0 (0UL) - -/* PPS register group index macro definition */ -#define ENET_PPS_1 (0UL) -#define ENET_PPS_2 (1UL) -#define ENET_PPS_3 (2UL) - - -#endif /* HPM_ENET_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_femc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_femc_regs.h deleted file mode 100644 index f450817a80b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_femc_regs.h +++ /dev/null @@ -1,981 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_FEMC_H -#define HPM_FEMC_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t IOCTRL; /* 0x4: IO Mux Control Register */ - __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ - __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ - __RW uint32_t BR[7]; /* 0x10 - 0x28: Base Register 0 (for SDRAM CS0 device) */ - __R uint8_t RESERVED0[12]; /* 0x2C - 0x37: Reserved */ - __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ - __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ - __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ - __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ - __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ - __R uint8_t RESERVED1[32]; /* 0x50 - 0x6F: Reserved */ - __RW uint32_t SRCTRL0; /* 0x70: SRAM control register 0 */ - __RW uint32_t SRCTRL1; /* 0x74: SRAM control register 1 */ - __R uint8_t RESERVED2[24]; /* 0x78 - 0x8F: Reserved */ - __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ - __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ - __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ - __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ - __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ - __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ - __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ - __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ - __R uint32_t STAT0; /* 0xC0: Status Register 0 */ - __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ - __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ -} FEMC_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * BTO (RW) - * - * Bus timeout cycles - * AXI Bus timeout cycle is as following (255*(2^BTO)): - * 00000b - 255*1 - * 00001-11110b - 255*2 - 255*2^30 - * 11111b - 255*2^31 - */ -#define FEMC_CTRL_BTO_MASK (0x1F000000UL) -#define FEMC_CTRL_BTO_SHIFT (24U) -#define FEMC_CTRL_BTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_BTO_SHIFT) & FEMC_CTRL_BTO_MASK) -#define FEMC_CTRL_BTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_BTO_MASK) >> FEMC_CTRL_BTO_SHIFT) - -/* - * CTO (RW) - * - * Command Execution timeout cycles - * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is - * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is - * CTO*1024 cycle. - */ -#define FEMC_CTRL_CTO_MASK (0xFF0000UL) -#define FEMC_CTRL_CTO_SHIFT (16U) -#define FEMC_CTRL_CTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_CTO_SHIFT) & FEMC_CTRL_CTO_MASK) -#define FEMC_CTRL_CTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_CTO_MASK) >> FEMC_CTRL_CTO_SHIFT) - -/* - * DQS (RW) - * - * DQS (read strobe) mode - * 0b - Dummy read strobe loopbacked internally - * 1b - Dummy read strobe loopbacked from DQS pad - */ -#define FEMC_CTRL_DQS_MASK (0x4U) -#define FEMC_CTRL_DQS_SHIFT (2U) -#define FEMC_CTRL_DQS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DQS_SHIFT) & FEMC_CTRL_DQS_MASK) -#define FEMC_CTRL_DQS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DQS_MASK) >> FEMC_CTRL_DQS_SHIFT) - -/* - * DIS (RW) - * - * Module Disable - * 0b - Module enabled - * 1b - Module disabled - */ -#define FEMC_CTRL_DIS_MASK (0x2U) -#define FEMC_CTRL_DIS_SHIFT (1U) -#define FEMC_CTRL_DIS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DIS_SHIFT) & FEMC_CTRL_DIS_MASK) -#define FEMC_CTRL_DIS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DIS_MASK) >> FEMC_CTRL_DIS_SHIFT) - -/* - * RST (RW) - * - * Software Reset - * Reset all internal logic in SEMC except configuration register - */ -#define FEMC_CTRL_RST_MASK (0x1U) -#define FEMC_CTRL_RST_SHIFT (0U) -#define FEMC_CTRL_RST_SET(x) (((uint32_t)(x) << FEMC_CTRL_RST_SHIFT) & FEMC_CTRL_RST_MASK) -#define FEMC_CTRL_RST_GET(x) (((uint32_t)(x) & FEMC_CTRL_RST_MASK) >> FEMC_CTRL_RST_SHIFT) - -/* Bitfield definition for register: IOCTRL */ -/* - * IO_CSX (RW) - * - * IO_CSX output selection - * 0001b - SDRAM CS1 - * 0110b - SRAM CE# - */ -#define FEMC_IOCTRL_IO_CSX_MASK (0xF0U) -#define FEMC_IOCTRL_IO_CSX_SHIFT (4U) -#define FEMC_IOCTRL_IO_CSX_SET(x) (((uint32_t)(x) << FEMC_IOCTRL_IO_CSX_SHIFT) & FEMC_IOCTRL_IO_CSX_MASK) -#define FEMC_IOCTRL_IO_CSX_GET(x) (((uint32_t)(x) & FEMC_IOCTRL_IO_CSX_MASK) >> FEMC_IOCTRL_IO_CSX_SHIFT) - -/* Bitfield definition for register: BMW0 */ -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define FEMC_BMW0_RWS_MASK (0xFF0000UL) -#define FEMC_BMW0_RWS_SHIFT (16U) -#define FEMC_BMW0_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW0_RWS_SHIFT) & FEMC_BMW0_RWS_MASK) -#define FEMC_BMW0_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW0_RWS_MASK) >> FEMC_BMW0_RWS_SHIFT) - -/* - * SH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define FEMC_BMW0_SH_MASK (0xFF00U) -#define FEMC_BMW0_SH_SHIFT (8U) -#define FEMC_BMW0_SH_SET(x) (((uint32_t)(x) << FEMC_BMW0_SH_SHIFT) & FEMC_BMW0_SH_MASK) -#define FEMC_BMW0_SH_GET(x) (((uint32_t)(x) & FEMC_BMW0_SH_MASK) >> FEMC_BMW0_SH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define FEMC_BMW0_AGE_MASK (0xF0U) -#define FEMC_BMW0_AGE_SHIFT (4U) -#define FEMC_BMW0_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW0_AGE_SHIFT) & FEMC_BMW0_AGE_MASK) -#define FEMC_BMW0_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW0_AGE_MASK) >> FEMC_BMW0_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define FEMC_BMW0_QOS_MASK (0xFU) -#define FEMC_BMW0_QOS_SHIFT (0U) -#define FEMC_BMW0_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW0_QOS_SHIFT) & FEMC_BMW0_QOS_MASK) -#define FEMC_BMW0_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW0_QOS_MASK) >> FEMC_BMW0_QOS_SHIFT) - -/* Bitfield definition for register: BMW1 */ -/* - * BR (RW) - * - * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current - * executing command. - */ -#define FEMC_BMW1_BR_MASK (0xFF000000UL) -#define FEMC_BMW1_BR_SHIFT (24U) -#define FEMC_BMW1_BR_SET(x) (((uint32_t)(x) << FEMC_BMW1_BR_SHIFT) & FEMC_BMW1_BR_MASK) -#define FEMC_BMW1_BR_GET(x) (((uint32_t)(x) & FEMC_BMW1_BR_MASK) >> FEMC_BMW1_BR_SHIFT) - -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define FEMC_BMW1_RWS_MASK (0xFF0000UL) -#define FEMC_BMW1_RWS_SHIFT (16U) -#define FEMC_BMW1_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW1_RWS_SHIFT) & FEMC_BMW1_RWS_MASK) -#define FEMC_BMW1_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW1_RWS_MASK) >> FEMC_BMW1_RWS_SHIFT) - -/* - * PH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define FEMC_BMW1_PH_MASK (0xFF00U) -#define FEMC_BMW1_PH_SHIFT (8U) -#define FEMC_BMW1_PH_SET(x) (((uint32_t)(x) << FEMC_BMW1_PH_SHIFT) & FEMC_BMW1_PH_MASK) -#define FEMC_BMW1_PH_GET(x) (((uint32_t)(x) & FEMC_BMW1_PH_MASK) >> FEMC_BMW1_PH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define FEMC_BMW1_AGE_MASK (0xF0U) -#define FEMC_BMW1_AGE_SHIFT (4U) -#define FEMC_BMW1_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW1_AGE_SHIFT) & FEMC_BMW1_AGE_MASK) -#define FEMC_BMW1_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW1_AGE_MASK) >> FEMC_BMW1_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define FEMC_BMW1_QOS_MASK (0xFU) -#define FEMC_BMW1_QOS_SHIFT (0U) -#define FEMC_BMW1_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW1_QOS_SHIFT) & FEMC_BMW1_QOS_MASK) -#define FEMC_BMW1_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW1_QOS_MASK) >> FEMC_BMW1_QOS_SHIFT) - -/* Bitfield definition for register array: BR */ -/* - * BASE (RW) - * - * Base Address - * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low - * position 12 bits are all zero. - */ -#define FEMC_BR_BASE_MASK (0xFFFFF000UL) -#define FEMC_BR_BASE_SHIFT (12U) -#define FEMC_BR_BASE_SET(x) (((uint32_t)(x) << FEMC_BR_BASE_SHIFT) & FEMC_BR_BASE_MASK) -#define FEMC_BR_BASE_GET(x) (((uint32_t)(x) & FEMC_BR_BASE_MASK) >> FEMC_BR_BASE_SHIFT) - -/* - * SIZE (RW) - * - * Memory size - * 00000b - 4KB - * 00001b - 8KB - * 00010b - 16KB - * 00011b - 32KB - * 00100b - 64KB - * 00101b - 128KB - * 00110b - 256KB - * 00111b - 512KB - * 01000b - 1MB - * 01001b - 2MB - * 01010b - 4MB - * 01011b - 8MB - * 01100b - 16MB - * 01101b - 32MB - * 01110b - 64MB - * 01111b - 128MB - * 10000b - 256MB - * 10001b - 512MB - * 10010b - 1GB - * 10011b - 2GB - * 10100-11111b - 4GB - */ -#define FEMC_BR_SIZE_MASK (0x3EU) -#define FEMC_BR_SIZE_SHIFT (1U) -#define FEMC_BR_SIZE_SET(x) (((uint32_t)(x) << FEMC_BR_SIZE_SHIFT) & FEMC_BR_SIZE_MASK) -#define FEMC_BR_SIZE_GET(x) (((uint32_t)(x) & FEMC_BR_SIZE_MASK) >> FEMC_BR_SIZE_SHIFT) - -/* - * VLD (RW) - * - * Valid - */ -#define FEMC_BR_VLD_MASK (0x1U) -#define FEMC_BR_VLD_SHIFT (0U) -#define FEMC_BR_VLD_SET(x) (((uint32_t)(x) << FEMC_BR_VLD_SHIFT) & FEMC_BR_VLD_MASK) -#define FEMC_BR_VLD_GET(x) (((uint32_t)(x) & FEMC_BR_VLD_MASK) >> FEMC_BR_VLD_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * AXIBUSERR (RW) - * - * AXI BUS error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_AXIBUSERR_MASK (0x8U) -#define FEMC_INTEN_AXIBUSERR_SHIFT (3U) -#define FEMC_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXIBUSERR_SHIFT) & FEMC_INTEN_AXIBUSERR_MASK) -#define FEMC_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXIBUSERR_MASK) >> FEMC_INTEN_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (RW) - * - * AXI command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_AXICMDERR_MASK (0x4U) -#define FEMC_INTEN_AXICMDERR_SHIFT (2U) -#define FEMC_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXICMDERR_SHIFT) & FEMC_INTEN_AXICMDERR_MASK) -#define FEMC_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXICMDERR_MASK) >> FEMC_INTEN_AXICMDERR_SHIFT) - -/* - * IPCMDERR (RW) - * - * IP command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_IPCMDERR_MASK (0x2U) -#define FEMC_INTEN_IPCMDERR_SHIFT (1U) -#define FEMC_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDERR_SHIFT) & FEMC_INTEN_IPCMDERR_MASK) -#define FEMC_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDERR_MASK) >> FEMC_INTEN_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (RW) - * - * IP command done interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_IPCMDDONE_MASK (0x1U) -#define FEMC_INTEN_IPCMDDONE_SHIFT (0U) -#define FEMC_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDDONE_SHIFT) & FEMC_INTEN_IPCMDDONE_MASK) -#define FEMC_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDDONE_MASK) >> FEMC_INTEN_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: INTR */ -/* - * AXIBUSERR (W1C) - * - * AXI bus error interrupt - * AXI Bus error interrupt is generated in following cases: - * • AXI address is invalid - * • AXI 8-bit or 16-bit WRAP write/read - */ -#define FEMC_INTR_AXIBUSERR_MASK (0x8U) -#define FEMC_INTR_AXIBUSERR_SHIFT (3U) -#define FEMC_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXIBUSERR_SHIFT) & FEMC_INTR_AXIBUSERR_MASK) -#define FEMC_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXIBUSERR_MASK) >> FEMC_INTR_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (W1C) - * - * AXI command error interrupt - * AXI command error interrupt is generated when AXI command execution timeout. - */ -#define FEMC_INTR_AXICMDERR_MASK (0x4U) -#define FEMC_INTR_AXICMDERR_SHIFT (2U) -#define FEMC_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXICMDERR_SHIFT) & FEMC_INTR_AXICMDERR_MASK) -#define FEMC_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXICMDERR_MASK) >> FEMC_INTR_AXICMDERR_SHIFT) - -/* - * IPCMDERR (W1C) - * - * IP command error done interrupt - * IP command error interrupt is generated in following case: - * • IP Command Address target invalid device space - * • IP Command Code unsupported - * • IP Command triggered when previous command - */ -#define FEMC_INTR_IPCMDERR_MASK (0x2U) -#define FEMC_INTR_IPCMDERR_SHIFT (1U) -#define FEMC_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDERR_SHIFT) & FEMC_INTR_IPCMDERR_MASK) -#define FEMC_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDERR_MASK) >> FEMC_INTR_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (W1C) - * - * IP command normal done interrupt - */ -#define FEMC_INTR_IPCMDDONE_MASK (0x1U) -#define FEMC_INTR_IPCMDDONE_SHIFT (0U) -#define FEMC_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDDONE_SHIFT) & FEMC_INTR_IPCMDDONE_MASK) -#define FEMC_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDDONE_MASK) >> FEMC_INTR_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: SDRCTRL0 */ -/* - * BANK2 (RW) - * - * 2 Bank selection bit - * 0b - SDRAM device has 4 banks. - * 1b - SDRAM device has 2 banks. - */ -#define FEMC_SDRCTRL0_BANK2_MASK (0x4000U) -#define FEMC_SDRCTRL0_BANK2_SHIFT (14U) -#define FEMC_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BANK2_SHIFT) & FEMC_SDRCTRL0_BANK2_MASK) -#define FEMC_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BANK2_MASK) >> FEMC_SDRCTRL0_BANK2_SHIFT) - -/* - * CAS (RW) - * - * CAS Latency - * 00b - 1 - * 01b - 1 - * 10b - 2 - * 11b - 3 - */ -#define FEMC_SDRCTRL0_CAS_MASK (0xC00U) -#define FEMC_SDRCTRL0_CAS_SHIFT (10U) -#define FEMC_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_CAS_SHIFT) & FEMC_SDRCTRL0_CAS_MASK) -#define FEMC_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_CAS_MASK) >> FEMC_SDRCTRL0_CAS_SHIFT) - -/* - * COL (RW) - * - * Column address bit number - * 00b - 12 bit - * 01b - 11 bit - * 10b - 10 bit - * 11b - 9 bit - */ -#define FEMC_SDRCTRL0_COL_MASK (0x300U) -#define FEMC_SDRCTRL0_COL_SHIFT (8U) -#define FEMC_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL_SHIFT) & FEMC_SDRCTRL0_COL_MASK) -#define FEMC_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL_MASK) >> FEMC_SDRCTRL0_COL_SHIFT) - -/* - * COL8 (RW) - * - * Column 8 selection bit - * 0b - Column address bit number is decided by COL field. - * 1b - Column address bit number is 8. COL field is ignored. - */ -#define FEMC_SDRCTRL0_COL8_MASK (0x80U) -#define FEMC_SDRCTRL0_COL8_SHIFT (7U) -#define FEMC_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL8_SHIFT) & FEMC_SDRCTRL0_COL8_MASK) -#define FEMC_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL8_MASK) >> FEMC_SDRCTRL0_COL8_SHIFT) - -/* - * BURSTLEN (RW) - * - * Burst Length - * 000b - 1 - * 001b - 2 - * 010b - 4 - * 011b - 8 - * 100b - 8 - * 101b - 8 - * 110b - 8 - * 111b - 8 - */ -#define FEMC_SDRCTRL0_BURSTLEN_MASK (0x70U) -#define FEMC_SDRCTRL0_BURSTLEN_SHIFT (4U) -#define FEMC_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BURSTLEN_SHIFT) & FEMC_SDRCTRL0_BURSTLEN_MASK) -#define FEMC_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BURSTLEN_MASK) >> FEMC_SDRCTRL0_BURSTLEN_SHIFT) - -/* - * HIGHBAND (RW) - * - * high band select - * 0: use data[15:0] for 16bit SDRAM; - * 1: use data[31:16] for 16bit SDRAM; - * only used when Port Size is 16bit(PORTSZ=01b) - */ -#define FEMC_SDRCTRL0_HIGHBAND_MASK (0x8U) -#define FEMC_SDRCTRL0_HIGHBAND_SHIFT (3U) -#define FEMC_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_HIGHBAND_SHIFT) & FEMC_SDRCTRL0_HIGHBAND_MASK) -#define FEMC_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_HIGHBAND_MASK) >> FEMC_SDRCTRL0_HIGHBAND_SHIFT) - -/* - * PORTSZ (RW) - * - * Port Size - * 00b - 8bit - * 01b - 16bit - * 10b - 32bit - */ -#define FEMC_SDRCTRL0_PORTSZ_MASK (0x3U) -#define FEMC_SDRCTRL0_PORTSZ_SHIFT (0U) -#define FEMC_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_PORTSZ_SHIFT) & FEMC_SDRCTRL0_PORTSZ_MASK) -#define FEMC_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_PORTSZ_MASK) >> FEMC_SDRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SDRCTRL1 */ -/* - * ACT2PRE (RW) - * - * ACT to Precharge minimum time - * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - */ -#define FEMC_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) -#define FEMC_SDRCTRL1_ACT2PRE_SHIFT (20U) -#define FEMC_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2PRE_SHIFT) & FEMC_SDRCTRL1_ACT2PRE_MASK) -#define FEMC_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2PRE_MASK) >> FEMC_SDRCTRL1_ACT2PRE_SHIFT) - -/* - * CKEOFF (RW) - * - * CKE OFF minimum time - * It is promised clock suspend last at leat CKEOFF+1 clock cycles. - */ -#define FEMC_SDRCTRL1_CKEOFF_MASK (0xF0000UL) -#define FEMC_SDRCTRL1_CKEOFF_SHIFT (16U) -#define FEMC_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_CKEOFF_SHIFT) & FEMC_SDRCTRL1_CKEOFF_MASK) -#define FEMC_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_CKEOFF_MASK) >> FEMC_SDRCTRL1_CKEOFF_SHIFT) - -/* - * WRC (RW) - * - * Write recovery time - * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_WRC_MASK (0xE000U) -#define FEMC_SDRCTRL1_WRC_SHIFT (13U) -#define FEMC_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_WRC_SHIFT) & FEMC_SDRCTRL1_WRC_MASK) -#define FEMC_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_WRC_MASK) >> FEMC_SDRCTRL1_WRC_SHIFT) - -/* - * RFRC (RW) - * - * Refresh recovery time - * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_RFRC_MASK (0x1F00U) -#define FEMC_SDRCTRL1_RFRC_SHIFT (8U) -#define FEMC_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_RFRC_SHIFT) & FEMC_SDRCTRL1_RFRC_MASK) -#define FEMC_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_RFRC_MASK) >> FEMC_SDRCTRL1_RFRC_SHIFT) - -/* - * ACT2RW (RW) - * - * ACT to Read/Write wait time - * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_ACT2RW_MASK (0xF0U) -#define FEMC_SDRCTRL1_ACT2RW_SHIFT (4U) -#define FEMC_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2RW_SHIFT) & FEMC_SDRCTRL1_ACT2RW_MASK) -#define FEMC_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2RW_MASK) >> FEMC_SDRCTRL1_ACT2RW_SHIFT) - -/* - * PRE2ACT (RW) - * - * PRECHARGE to ACT/Refresh wait time - * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_PRE2ACT_MASK (0xFU) -#define FEMC_SDRCTRL1_PRE2ACT_SHIFT (0U) -#define FEMC_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_PRE2ACT_SHIFT) & FEMC_SDRCTRL1_PRE2ACT_MASK) -#define FEMC_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_PRE2ACT_MASK) >> FEMC_SDRCTRL1_PRE2ACT_SHIFT) - -/* Bitfield definition for register: SDRCTRL2 */ -/* - * ITO (RW) - * - * SDRAM Idle timeout - * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is - * considered idle when there is no AXI Bus transfer and no SDRAM command pending. - * 00000000b - IDLE timeout period is 256*Prescale period. - * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. - */ -#define FEMC_SDRCTRL2_ITO_MASK (0xFF000000UL) -#define FEMC_SDRCTRL2_ITO_SHIFT (24U) -#define FEMC_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ITO_SHIFT) & FEMC_SDRCTRL2_ITO_MASK) -#define FEMC_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ITO_MASK) >> FEMC_SDRCTRL2_ITO_SHIFT) - -/* - * ACT2ACT (RW) - * - * ACT to ACT wait time - * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This - * could help to meet tRRD timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) -#define FEMC_SDRCTRL2_ACT2ACT_SHIFT (16U) -#define FEMC_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ACT2ACT_SHIFT) & FEMC_SDRCTRL2_ACT2ACT_MASK) -#define FEMC_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ACT2ACT_MASK) >> FEMC_SDRCTRL2_ACT2ACT_SHIFT) - -/* - * REF2REF (RW) - * - * Refresh to Refresh wait time - * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. - * This could help to meet tRFC timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL2_REF2REF_MASK (0xFF00U) -#define FEMC_SDRCTRL2_REF2REF_SHIFT (8U) -#define FEMC_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_REF2REF_SHIFT) & FEMC_SDRCTRL2_REF2REF_MASK) -#define FEMC_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_REF2REF_MASK) >> FEMC_SDRCTRL2_REF2REF_SHIFT) - -/* - * SRRC (RW) - * - * Self Refresh Recovery time - * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - */ -#define FEMC_SDRCTRL2_SRRC_MASK (0xFFU) -#define FEMC_SDRCTRL2_SRRC_SHIFT (0U) -#define FEMC_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_SRRC_SHIFT) & FEMC_SDRCTRL2_SRRC_MASK) -#define FEMC_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_SRRC_MASK) >> FEMC_SDRCTRL2_SRRC_SHIFT) - -/* Bitfield definition for register: SDRCTRL3 */ -/* - * UT (RW) - * - * Refresh urgent threshold - * Internal refresh request is generated on every Refresh period. Before internal request timer count up to - * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh - * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. - * When internal request timer count up to this urgent threshold, refresh request is considered as urgent - * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP - * command to SDRAM device. - * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as - * urgent refresh request. - * Refresh urgent threshold is as follwoing: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - UT*Prescaler period - */ -#define FEMC_SDRCTRL3_UT_MASK (0xFF000000UL) -#define FEMC_SDRCTRL3_UT_SHIFT (24U) -#define FEMC_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_UT_SHIFT) & FEMC_SDRCTRL3_UT_MASK) -#define FEMC_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_UT_MASK) >> FEMC_SDRCTRL3_UT_SHIFT) - -/* - * RT (RW) - * - * Refresh timer period - * Refresh timer period is as following: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - RT*Prescaler period - */ -#define FEMC_SDRCTRL3_RT_MASK (0xFF0000UL) -#define FEMC_SDRCTRL3_RT_SHIFT (16U) -#define FEMC_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_RT_SHIFT) & FEMC_SDRCTRL3_RT_MASK) -#define FEMC_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_RT_MASK) >> FEMC_SDRCTRL3_RT_SHIFT) - -/* - * PRESCALE (RW) - * - * Prescaler timer period - * Prescaler timer period is as following: - * 00000000b - 256*16 clock cycles - * 00000001-11111111b - PRESCALE*16 clock cycles - */ -#define FEMC_SDRCTRL3_PRESCALE_MASK (0xFF00U) -#define FEMC_SDRCTRL3_PRESCALE_SHIFT (8U) -#define FEMC_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_PRESCALE_SHIFT) & FEMC_SDRCTRL3_PRESCALE_MASK) -#define FEMC_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_PRESCALE_MASK) >> FEMC_SDRCTRL3_PRESCALE_SHIFT) - -/* - * REBL (RW) - * - * Refresh burst length - * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The - * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. - * 000b - 1 - * 001b - 2 - * 010b - 3 - * 011b - 4 - * 100b - 5 - * 101b - 6 - * 110b - 7 - * 111b - 8 - */ -#define FEMC_SDRCTRL3_REBL_MASK (0xEU) -#define FEMC_SDRCTRL3_REBL_SHIFT (1U) -#define FEMC_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REBL_SHIFT) & FEMC_SDRCTRL3_REBL_MASK) -#define FEMC_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REBL_MASK) >> FEMC_SDRCTRL3_REBL_SHIFT) - -/* - * REN (RW) - * - * Refresh enable - */ -#define FEMC_SDRCTRL3_REN_MASK (0x1U) -#define FEMC_SDRCTRL3_REN_SHIFT (0U) -#define FEMC_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REN_SHIFT) & FEMC_SDRCTRL3_REN_MASK) -#define FEMC_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REN_MASK) >> FEMC_SDRCTRL3_REN_SHIFT) - -/* Bitfield definition for register: SRCTRL0 */ -/* - * ADVH (RW) - * - * ADV hold state - * 0b - ADV is high during address hold state - * 1b - ADV is low during address hold state - */ -#define FEMC_SRCTRL0_ADVH_MASK (0x800U) -#define FEMC_SRCTRL0_ADVH_SHIFT (11U) -#define FEMC_SRCTRL0_ADVH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVH_SHIFT) & FEMC_SRCTRL0_ADVH_MASK) -#define FEMC_SRCTRL0_ADVH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVH_MASK) >> FEMC_SRCTRL0_ADVH_SHIFT) - -/* - * ADVP (RW) - * - * ADV polarity - * 0b - ADV is active low - * 1b - ADV is active high - */ -#define FEMC_SRCTRL0_ADVP_MASK (0x400U) -#define FEMC_SRCTRL0_ADVP_SHIFT (10U) -#define FEMC_SRCTRL0_ADVP_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVP_SHIFT) & FEMC_SRCTRL0_ADVP_MASK) -#define FEMC_SRCTRL0_ADVP_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVP_MASK) >> FEMC_SRCTRL0_ADVP_SHIFT) - -/* - * ADM (RW) - * - * address data mode - * 00b - address and data MUX mode - * 11b - address and data non-MUX mode - */ -#define FEMC_SRCTRL0_ADM_MASK (0x300U) -#define FEMC_SRCTRL0_ADM_SHIFT (8U) -#define FEMC_SRCTRL0_ADM_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADM_SHIFT) & FEMC_SRCTRL0_ADM_MASK) -#define FEMC_SRCTRL0_ADM_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADM_MASK) >> FEMC_SRCTRL0_ADM_SHIFT) - -/* - * PORTSZ (RW) - * - * port size - * 0b - 8bit - * 1b - 16bit - */ -#define FEMC_SRCTRL0_PORTSZ_MASK (0x1U) -#define FEMC_SRCTRL0_PORTSZ_SHIFT (0U) -#define FEMC_SRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_PORTSZ_SHIFT) & FEMC_SRCTRL0_PORTSZ_MASK) -#define FEMC_SRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_PORTSZ_MASK) >> FEMC_SRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SRCTRL1 */ -/* - * OEH (RW) - * - * OE high time, is OEH+1 clock cycles - */ -#define FEMC_SRCTRL1_OEH_MASK (0xF0000000UL) -#define FEMC_SRCTRL1_OEH_SHIFT (28U) -#define FEMC_SRCTRL1_OEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEH_SHIFT) & FEMC_SRCTRL1_OEH_MASK) -#define FEMC_SRCTRL1_OEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEH_MASK) >> FEMC_SRCTRL1_OEH_SHIFT) - -/* - * OEL (RW) - * - * OE low time, is OEL+1 clock cycles - */ -#define FEMC_SRCTRL1_OEL_MASK (0xF000000UL) -#define FEMC_SRCTRL1_OEL_SHIFT (24U) -#define FEMC_SRCTRL1_OEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEL_SHIFT) & FEMC_SRCTRL1_OEL_MASK) -#define FEMC_SRCTRL1_OEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEL_MASK) >> FEMC_SRCTRL1_OEL_SHIFT) - -/* - * WEH (RW) - * - * WE high time, is WEH+1 clock cycles - */ -#define FEMC_SRCTRL1_WEH_MASK (0xF00000UL) -#define FEMC_SRCTRL1_WEH_SHIFT (20U) -#define FEMC_SRCTRL1_WEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEH_SHIFT) & FEMC_SRCTRL1_WEH_MASK) -#define FEMC_SRCTRL1_WEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEH_MASK) >> FEMC_SRCTRL1_WEH_SHIFT) - -/* - * WEL (RW) - * - * WE low time, is WEL+1 clock cycles - */ -#define FEMC_SRCTRL1_WEL_MASK (0xF0000UL) -#define FEMC_SRCTRL1_WEL_SHIFT (16U) -#define FEMC_SRCTRL1_WEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEL_SHIFT) & FEMC_SRCTRL1_WEL_MASK) -#define FEMC_SRCTRL1_WEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEL_MASK) >> FEMC_SRCTRL1_WEL_SHIFT) - -/* - * AH (RW) - * - * Address hold time, is AH+1 clock cycles - */ -#define FEMC_SRCTRL1_AH_MASK (0xF000U) -#define FEMC_SRCTRL1_AH_SHIFT (12U) -#define FEMC_SRCTRL1_AH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AH_SHIFT) & FEMC_SRCTRL1_AH_MASK) -#define FEMC_SRCTRL1_AH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AH_MASK) >> FEMC_SRCTRL1_AH_SHIFT) - -/* - * AS (RW) - * - * Address setup time, is AS+1 clock cycles - */ -#define FEMC_SRCTRL1_AS_MASK (0xF00U) -#define FEMC_SRCTRL1_AS_SHIFT (8U) -#define FEMC_SRCTRL1_AS_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AS_SHIFT) & FEMC_SRCTRL1_AS_MASK) -#define FEMC_SRCTRL1_AS_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AS_MASK) >> FEMC_SRCTRL1_AS_SHIFT) - -/* - * CEH (RW) - * - * Chip enable hold time, is CEH+1 clock cycles - */ -#define FEMC_SRCTRL1_CEH_MASK (0xF0U) -#define FEMC_SRCTRL1_CEH_SHIFT (4U) -#define FEMC_SRCTRL1_CEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CEH_SHIFT) & FEMC_SRCTRL1_CEH_MASK) -#define FEMC_SRCTRL1_CEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CEH_MASK) >> FEMC_SRCTRL1_CEH_SHIFT) - -/* - * CES (RW) - * - * Chip enable setup time, is CES+1 clock cycles - */ -#define FEMC_SRCTRL1_CES_MASK (0xFU) -#define FEMC_SRCTRL1_CES_SHIFT (0U) -#define FEMC_SRCTRL1_CES_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CES_SHIFT) & FEMC_SRCTRL1_CES_MASK) -#define FEMC_SRCTRL1_CES_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CES_MASK) >> FEMC_SRCTRL1_CES_SHIFT) - -/* Bitfield definition for register: SADDR */ -/* - * SA (RW) - * - * Slave address - */ -#define FEMC_SADDR_SA_MASK (0xFFFFFFFFUL) -#define FEMC_SADDR_SA_SHIFT (0U) -#define FEMC_SADDR_SA_SET(x) (((uint32_t)(x) << FEMC_SADDR_SA_SHIFT) & FEMC_SADDR_SA_MASK) -#define FEMC_SADDR_SA_GET(x) (((uint32_t)(x) & FEMC_SADDR_SA_MASK) >> FEMC_SADDR_SA_SHIFT) - -/* Bitfield definition for register: DATSZ */ -/* - * DATSZ (RW) - * - * Data Size in Byte - * When IP command is not a write/read operation, DATSZ field would be ignored. - * 000b - 4 - * 001b - 1 - * 010b - 2 - * 011b - 3 - * 100b - 4 - * 101b - 4 - * 110b - 4 - * 111b - 4 - */ -#define FEMC_DATSZ_DATSZ_MASK (0x7U) -#define FEMC_DATSZ_DATSZ_SHIFT (0U) -#define FEMC_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << FEMC_DATSZ_DATSZ_SHIFT) & FEMC_DATSZ_DATSZ_MASK) -#define FEMC_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & FEMC_DATSZ_DATSZ_MASK) >> FEMC_DATSZ_DATSZ_SHIFT) - -/* Bitfield definition for register: BYTEMSK */ -/* - * BM3 (RW) - * - * Byte Mask for Byte 3 (IPTXD bit 31:24) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM3_MASK (0x8U) -#define FEMC_BYTEMSK_BM3_SHIFT (3U) -#define FEMC_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM3_SHIFT) & FEMC_BYTEMSK_BM3_MASK) -#define FEMC_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM3_MASK) >> FEMC_BYTEMSK_BM3_SHIFT) - -/* - * BM2 (RW) - * - * Byte Mask for Byte 2 (IPTXD bit 23:16) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM2_MASK (0x4U) -#define FEMC_BYTEMSK_BM2_SHIFT (2U) -#define FEMC_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM2_SHIFT) & FEMC_BYTEMSK_BM2_MASK) -#define FEMC_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM2_MASK) >> FEMC_BYTEMSK_BM2_SHIFT) - -/* - * BM1 (RW) - * - * Byte Mask for Byte 1 (IPTXD bit 15:8) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM1_MASK (0x2U) -#define FEMC_BYTEMSK_BM1_SHIFT (1U) -#define FEMC_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM1_SHIFT) & FEMC_BYTEMSK_BM1_MASK) -#define FEMC_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM1_MASK) >> FEMC_BYTEMSK_BM1_SHIFT) - -/* - * BM0 (RW) - * - * Byte Mask for Byte 0 (IPTXD bit 7:0) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM0_MASK (0x1U) -#define FEMC_BYTEMSK_BM0_SHIFT (0U) -#define FEMC_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM0_SHIFT) & FEMC_BYTEMSK_BM0_MASK) -#define FEMC_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM0_MASK) >> FEMC_BYTEMSK_BM0_SHIFT) - -/* Bitfield definition for register: IPCMD */ -/* - * KEY (WO) - * - * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory - * device is selected by BRx settings and IPCR0 registers. - */ -#define FEMC_IPCMD_KEY_MASK (0xFFFF0000UL) -#define FEMC_IPCMD_KEY_SHIFT (16U) -#define FEMC_IPCMD_KEY_SET(x) (((uint32_t)(x) << FEMC_IPCMD_KEY_SHIFT) & FEMC_IPCMD_KEY_MASK) -#define FEMC_IPCMD_KEY_GET(x) (((uint32_t)(x) & FEMC_IPCMD_KEY_MASK) >> FEMC_IPCMD_KEY_SHIFT) - -/* - * CMD (RW) - * - * SDRAM Commands: - * • 0x8: READ - * • 0x9: WRITE - * • 0xA: MODESET - * • 0xB: ACTIVE - * • 0xC: AUTO REFRESH - * • 0xD: SELF REFRESH - * • 0xE: PRECHARGE - * • 0xF: PRECHARGE ALL - * • Others: RSVD - * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - */ -#define FEMC_IPCMD_CMD_MASK (0xFFFFU) -#define FEMC_IPCMD_CMD_SHIFT (0U) -#define FEMC_IPCMD_CMD_SET(x) (((uint32_t)(x) << FEMC_IPCMD_CMD_SHIFT) & FEMC_IPCMD_CMD_MASK) -#define FEMC_IPCMD_CMD_GET(x) (((uint32_t)(x) & FEMC_IPCMD_CMD_MASK) >> FEMC_IPCMD_CMD_SHIFT) - -/* Bitfield definition for register: IPTX */ -/* - * DAT (RW) - * - * Data - */ -#define FEMC_IPTX_DAT_MASK (0xFFFFFFFFUL) -#define FEMC_IPTX_DAT_SHIFT (0U) -#define FEMC_IPTX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPTX_DAT_SHIFT) & FEMC_IPTX_DAT_MASK) -#define FEMC_IPTX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPTX_DAT_MASK) >> FEMC_IPTX_DAT_SHIFT) - -/* Bitfield definition for register: IPRX */ -/* - * DAT (RW) - * - * Data - */ -#define FEMC_IPRX_DAT_MASK (0xFFFFFFFFUL) -#define FEMC_IPRX_DAT_SHIFT (0U) -#define FEMC_IPRX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPRX_DAT_SHIFT) & FEMC_IPRX_DAT_MASK) -#define FEMC_IPRX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPRX_DAT_MASK) >> FEMC_IPRX_DAT_SHIFT) - -/* Bitfield definition for register: STAT0 */ -/* - * IDLE (RO) - * - * Indicating whether it is in IDLE state. - * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no - * pending device access. - */ -#define FEMC_STAT0_IDLE_MASK (0x1U) -#define FEMC_STAT0_IDLE_SHIFT (0U) -#define FEMC_STAT0_IDLE_GET(x) (((uint32_t)(x) & FEMC_STAT0_IDLE_MASK) >> FEMC_STAT0_IDLE_SHIFT) - -/* Bitfield definition for register: DLYCFG */ -/* - * OE (RW) - * - * delay clock output enable, should be set after setting DLYEN and DLYSEL - */ -#define FEMC_DLYCFG_OE_MASK (0x2000U) -#define FEMC_DLYCFG_OE_SHIFT (13U) -#define FEMC_DLYCFG_OE_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_OE_SHIFT) & FEMC_DLYCFG_OE_MASK) -#define FEMC_DLYCFG_OE_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_OE_MASK) >> FEMC_DLYCFG_OE_SHIFT) - -/* - * DLYSEL (RW) - * - * delay line select, 0 for 1 cell, 31 for all 32 cells - */ -#define FEMC_DLYCFG_DLYSEL_MASK (0x3EU) -#define FEMC_DLYCFG_DLYSEL_SHIFT (1U) -#define FEMC_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYSEL_SHIFT) & FEMC_DLYCFG_DLYSEL_MASK) -#define FEMC_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYSEL_MASK) >> FEMC_DLYCFG_DLYSEL_SHIFT) - -/* - * DLYEN (RW) - * - * delay line enable - */ -#define FEMC_DLYCFG_DLYEN_MASK (0x1U) -#define FEMC_DLYCFG_DLYEN_SHIFT (0U) -#define FEMC_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYEN_SHIFT) & FEMC_DLYCFG_DLYEN_MASK) -#define FEMC_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYEN_MASK) >> FEMC_DLYCFG_DLYEN_SHIFT) - - - -/* BR register group index macro definition */ -#define FEMC_BR_BASE0 (0UL) -#define FEMC_BR_BASE1 (1UL) -#define FEMC_BR_BASE6 (6UL) - - -#endif /* HPM_FEMC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gpio_regs.h deleted file mode 100644 index dcc90189c62..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gpio_regs.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIO_H -#define HPM_GPIO_H - -typedef struct { - struct { - __R uint32_t VALUE; /* 0x0: GPIO input value */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - } DI[16]; - struct { - __RW uint32_t VALUE; /* 0x100: GPIO output value */ - __RW uint32_t SET; /* 0x104: GPIO output set */ - __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ - __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ - } DO[16]; - struct { - __RW uint32_t VALUE; /* 0x200: GPIO direction value */ - __RW uint32_t SET; /* 0x204: GPIO direction set */ - __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ - __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ - } OE[16]; - struct { - __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ - } IF[16]; - struct { - __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ - __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ - __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ - } IE[16]; - struct { - __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ - __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ - __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ - __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ - } PL[16]; - struct { - __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ - __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ - __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ - __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ - } TP[16]; - struct { - __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ - __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ - __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ - __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ - } AS[16]; -} GPIO_Type; - - -/* Bitfield definition for register of struct array DI: VALUE */ -/* - * INPUT (RO) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: VALUE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) -#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) -#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: SET */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_SET_OUTPUT_SHIFT (0U) -#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) -#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: CLEAR */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) -#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) -#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: TOGGLE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) -#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) -#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array OE: VALUE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) -#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) -#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: SET */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_SET_DIRECTION_SHIFT (0U) -#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) -#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: CLEAR */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) -#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) -#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: TOGGLE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) -#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) -#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array IF: VALUE */ -/* - * IRQ_FLAG (W1C) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) -#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IE: VALUE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) -#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: SET */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) -#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) -#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: CLEAR */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) -#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) -#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: TOGGLE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) -#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array PL: VALUE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) -#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: SET */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) -#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) -#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: CLEAR */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) -#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) -#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: TOGGLE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) -#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array TP: VALUE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) -#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: SET */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) -#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: CLEAR */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) -#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: TOGGLE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) -#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array AS: VALUE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) -#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: SET */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) -#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: CLEAR */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) -#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: TOGGLE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) - - - -/* DI register group index macro definition */ -#define GPIO_DI_GPIOA (0UL) -#define GPIO_DI_GPIOB (1UL) -#define GPIO_DI_GPIOC (2UL) -#define GPIO_DI_GPIOD (3UL) -#define GPIO_DI_GPIOE (4UL) -#define GPIO_DI_GPIOF (5UL) -#define GPIO_DI_GPIOX (13UL) -#define GPIO_DI_GPIOY (14UL) -#define GPIO_DI_GPIOZ (15UL) - -/* DO register group index macro definition */ -#define GPIO_DO_GPIOA (0UL) -#define GPIO_DO_GPIOB (1UL) -#define GPIO_DO_GPIOC (2UL) -#define GPIO_DO_GPIOD (3UL) -#define GPIO_DO_GPIOE (4UL) -#define GPIO_DO_GPIOF (5UL) -#define GPIO_DO_GPIOX (13UL) -#define GPIO_DO_GPIOY (14UL) -#define GPIO_DO_GPIOZ (15UL) - -/* OE register group index macro definition */ -#define GPIO_OE_GPIOA (0UL) -#define GPIO_OE_GPIOB (1UL) -#define GPIO_OE_GPIOC (2UL) -#define GPIO_OE_GPIOD (3UL) -#define GPIO_OE_GPIOE (4UL) -#define GPIO_OE_GPIOF (5UL) -#define GPIO_OE_GPIOX (13UL) -#define GPIO_OE_GPIOY (14UL) -#define GPIO_OE_GPIOZ (15UL) - -/* IF register group index macro definition */ -#define GPIO_IF_GPIOA (0UL) -#define GPIO_IF_GPIOB (1UL) -#define GPIO_IF_GPIOC (2UL) -#define GPIO_IF_GPIOD (3UL) -#define GPIO_IF_GPIOE (4UL) -#define GPIO_IF_GPIOF (5UL) -#define GPIO_IF_GPIOX (13UL) -#define GPIO_IF_GPIOY (14UL) -#define GPIO_IF_GPIOZ (15UL) - -/* IE register group index macro definition */ -#define GPIO_IE_GPIOA (0UL) -#define GPIO_IE_GPIOB (1UL) -#define GPIO_IE_GPIOC (2UL) -#define GPIO_IE_GPIOD (3UL) -#define GPIO_IE_GPIOE (4UL) -#define GPIO_IE_GPIOF (5UL) -#define GPIO_IE_GPIOX (13UL) -#define GPIO_IE_GPIOY (14UL) -#define GPIO_IE_GPIOZ (15UL) - -/* PL register group index macro definition */ -#define GPIO_PL_GPIOA (0UL) -#define GPIO_PL_GPIOB (1UL) -#define GPIO_PL_GPIOC (2UL) -#define GPIO_PL_GPIOD (3UL) -#define GPIO_PL_GPIOE (4UL) -#define GPIO_PL_GPIOF (5UL) -#define GPIO_PL_GPIOX (13UL) -#define GPIO_PL_GPIOY (14UL) -#define GPIO_PL_GPIOZ (15UL) - -/* TP register group index macro definition */ -#define GPIO_TP_GPIOA (0UL) -#define GPIO_TP_GPIOB (1UL) -#define GPIO_TP_GPIOC (2UL) -#define GPIO_TP_GPIOD (3UL) -#define GPIO_TP_GPIOE (4UL) -#define GPIO_TP_GPIOF (5UL) -#define GPIO_TP_GPIOX (13UL) -#define GPIO_TP_GPIOY (14UL) -#define GPIO_TP_GPIOZ (15UL) - -/* AS register group index macro definition */ -#define GPIO_AS_GPIOA (0UL) -#define GPIO_AS_GPIOB (1UL) -#define GPIO_AS_GPIOC (2UL) -#define GPIO_AS_GPIOD (3UL) -#define GPIO_AS_GPIOE (4UL) -#define GPIO_AS_GPIOF (5UL) -#define GPIO_AS_GPIOX (13UL) -#define GPIO_AS_GPIOY (14UL) -#define GPIO_AS_GPIOZ (15UL) - - -#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gpiom_regs.h deleted file mode 100644 index d9924ef5f69..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gpiom_regs.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIOM_H -#define HPM_GPIOM_H - -typedef struct { - struct { - __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ - } ASSIGN[16]; -} GPIOM_Type; - - -/* Bitfield definition for register of struct array ASSIGN: PIN00 */ -/* - * LOCK (RW) - * - * lock fields in this register, lock can only be cleared by soc reset - * 0: fields can be changed - * 1: fields locked to current value, not changeable - */ -#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) -#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) -#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) - -/* - * HIDE (RW) - * - * pin value visibility to gpios, - * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 - * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 - * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - */ -#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) -#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) -#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) -#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) - -/* - * SELECT (RW) - * - * select which gpio controls chip pin, - * 0: soc gpio0; - * 1: soc gpio1; - * 2: cpu0 fastgpio - * 3: cpu1 fast gpio - */ -#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) -#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) -#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) -#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) - - - -/* PIN register group index macro definition */ -#define GPIOM_ASSIGN_PIN_PIN00 (0UL) -#define GPIOM_ASSIGN_PIN_PIN01 (1UL) -#define GPIOM_ASSIGN_PIN_PIN02 (2UL) -#define GPIOM_ASSIGN_PIN_PIN03 (3UL) -#define GPIOM_ASSIGN_PIN_PIN04 (4UL) -#define GPIOM_ASSIGN_PIN_PIN05 (5UL) -#define GPIOM_ASSIGN_PIN_PIN06 (6UL) -#define GPIOM_ASSIGN_PIN_PIN07 (7UL) -#define GPIOM_ASSIGN_PIN_PIN08 (8UL) -#define GPIOM_ASSIGN_PIN_PIN09 (9UL) -#define GPIOM_ASSIGN_PIN_PIN10 (10UL) -#define GPIOM_ASSIGN_PIN_PIN11 (11UL) -#define GPIOM_ASSIGN_PIN_PIN12 (12UL) -#define GPIOM_ASSIGN_PIN_PIN13 (13UL) -#define GPIOM_ASSIGN_PIN_PIN14 (14UL) -#define GPIOM_ASSIGN_PIN_PIN15 (15UL) -#define GPIOM_ASSIGN_PIN_PIN16 (16UL) -#define GPIOM_ASSIGN_PIN_PIN17 (17UL) -#define GPIOM_ASSIGN_PIN_PIN18 (18UL) -#define GPIOM_ASSIGN_PIN_PIN19 (19UL) -#define GPIOM_ASSIGN_PIN_PIN20 (20UL) -#define GPIOM_ASSIGN_PIN_PIN21 (21UL) -#define GPIOM_ASSIGN_PIN_PIN22 (22UL) -#define GPIOM_ASSIGN_PIN_PIN23 (23UL) -#define GPIOM_ASSIGN_PIN_PIN24 (24UL) -#define GPIOM_ASSIGN_PIN_PIN25 (25UL) -#define GPIOM_ASSIGN_PIN_PIN26 (26UL) -#define GPIOM_ASSIGN_PIN_PIN27 (27UL) -#define GPIOM_ASSIGN_PIN_PIN28 (28UL) -#define GPIOM_ASSIGN_PIN_PIN29 (29UL) -#define GPIOM_ASSIGN_PIN_PIN30 (30UL) -#define GPIOM_ASSIGN_PIN_PIN31 (31UL) - -/* ASSIGN register group index macro definition */ -#define GPIOM_ASSIGN_GPIOA (0UL) -#define GPIOM_ASSIGN_GPIOB (1UL) -#define GPIOM_ASSIGN_GPIOC (2UL) -#define GPIOM_ASSIGN_GPIOD (3UL) -#define GPIOM_ASSIGN_GPIOE (4UL) -#define GPIOM_ASSIGN_GPIOF (5UL) -#define GPIOM_ASSIGN_GPIOX (13UL) -#define GPIOM_ASSIGN_GPIOY (14UL) -#define GPIOM_ASSIGN_GPIOZ (15UL) - - -#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gptmr_regs.h deleted file mode 100644 index f87b1a75632..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_gptmr_regs.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPTMR_H -#define HPM_GPTMR_H - -typedef struct { - struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ - __RW uint32_t RLD; /* 0xC: Reload register */ - __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ - __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ - __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ - __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ - __R uint32_t CNT; /* 0x30: Counter */ - __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ - } CHANNEL[4]; - __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ - __RW uint32_t SR; /* 0x200: Status register */ - __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ - __RW uint32_t GCR; /* 0x208: Global control register */ -} GPTMR_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CR */ -/* - * CNTUPT (WO) - * - * 1- update counter to new value as CNTUPTVAL - * This bit will be auto cleared after 1 cycle - */ -#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) -#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) -#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) -#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) - -/* - * CNTRST (RW) - * - * 1- reset counter - */ -#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) -#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) -#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) -#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) - -/* - * SYNCFLW (RW) - * - * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. - * This bit is not valid for channel 0. - */ -#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) -#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) - -/* - * SYNCIFEN (RW) - * - * 1- SYNCI is valid on its falling edge - */ -#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) - -/* - * SYNCIREN (RW) - * - * 1- SYNCI is valid on its rising edge - */ -#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) - -/* - * CEN (RW) - * - * 1- counter enable - */ -#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) -#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) -#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) -#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) - -/* - * CMPINIT (RW) - * - * Output compare initial poliarity - * 1- The channel output initial level is high - * 0- The channel output initial level is low - * User should set this bit before set CMPEN to 1. - */ -#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) -#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) -#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) -#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) - -/* - * CMPEN (RW) - * - * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - */ -#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) -#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) -#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) -#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) - -/* - * DMASEL (RW) - * - * select one of DMA request: - * 00- CMP0 flag - * 01- CMP1 flag - * 10- Input signal toggle captured - * 11- RLD flag, counter reload; - */ -#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) -#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) -#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) -#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) - -/* - * DMAEN (RW) - * - * 1- enable dma - */ -#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) -#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) -#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) -#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) - -/* - * SWSYNCIEN (RW) - * - * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - */ -#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) - -/* - * DBGPAUSE (RW) - * - * 1- counter will pause if chip is in debug mode - */ -#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) -#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) - -/* - * CAPMODE (RW) - * - * This bitfield define the input capture mode - * 100: width measure mode, timer will calculate the input signal period and duty cycle - * 011: capture at both rising edge and falling edge - * 010: capture at falling edge - * 001: capture at rising edge - * 000: No capture - */ -#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) -#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) -#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) -#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CMP0 */ -/* - * CMP (RW) - * - * compare value 0 - */ -#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) -#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) -#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: RLD */ -/* - * RLD (RW) - * - * reload value - */ -#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) -#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) -#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ -/* - * CNTUPTVAL (RW) - * - * counter will be set to this value when software write cntupt bit in CR - */ -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ -/* - * CAPPOS (RO) - * - * This register contains the counter value captured at input signal rising edge - */ -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ -/* - * CAPNEG (RO) - * - * This register contains the counter value captured at input signal falling edge - */ -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ -/* - * CAPPRD (RO) - * - * This register contains the input signal period when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ -/* - * MEAS_HIGH (RO) - * - * This register contains the input signal duty cycle when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNT */ -/* - * COUNTER (RO) - * - * 32 bit counter value - */ -#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) -#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * CH3CMP1F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) -#define GPTMR_SR_CH3CMP1F_SHIFT (15U) -#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) -#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) - -/* - * CH3CMP0F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) -#define GPTMR_SR_CH3CMP0F_SHIFT (14U) -#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) -#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) - -/* - * CH3CAPF (W1C) - * - * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH3CAPF_MASK (0x2000U) -#define GPTMR_SR_CH3CAPF_SHIFT (13U) -#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) -#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) - -/* - * CH3RLDF (W1C) - * - * channel 3 counter reload flag - */ -#define GPTMR_SR_CH3RLDF_MASK (0x1000U) -#define GPTMR_SR_CH3RLDF_SHIFT (12U) -#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) -#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) - -/* - * CH2CMP1F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP1F_MASK (0x800U) -#define GPTMR_SR_CH2CMP1F_SHIFT (11U) -#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) -#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) - -/* - * CH2CMP0F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP0F_MASK (0x400U) -#define GPTMR_SR_CH2CMP0F_SHIFT (10U) -#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) -#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) - -/* - * CH2CAPF (W1C) - * - * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH2CAPF_MASK (0x200U) -#define GPTMR_SR_CH2CAPF_SHIFT (9U) -#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) -#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) - -/* - * CH2RLDF (W1C) - * - * channel 2 counter reload flag - */ -#define GPTMR_SR_CH2RLDF_MASK (0x100U) -#define GPTMR_SR_CH2RLDF_SHIFT (8U) -#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) -#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) - -/* - * CH1CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP1F_MASK (0x80U) -#define GPTMR_SR_CH1CMP1F_SHIFT (7U) -#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) -#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) - -/* - * CH1CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP0F_MASK (0x40U) -#define GPTMR_SR_CH1CMP0F_SHIFT (6U) -#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) -#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) - -/* - * CH1CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH1CAPF_MASK (0x20U) -#define GPTMR_SR_CH1CAPF_SHIFT (5U) -#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) -#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) - -/* - * CH1RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH1RLDF_MASK (0x10U) -#define GPTMR_SR_CH1RLDF_SHIFT (4U) -#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) -#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) - -/* - * CH0CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP1F_MASK (0x8U) -#define GPTMR_SR_CH0CMP1F_SHIFT (3U) -#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) -#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) - -/* - * CH0CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP0F_MASK (0x4U) -#define GPTMR_SR_CH0CMP0F_SHIFT (2U) -#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) -#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) - -/* - * CH0CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH0CAPF_MASK (0x2U) -#define GPTMR_SR_CH0CAPF_SHIFT (1U) -#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) -#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) - -/* - * CH0RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH0RLDF_MASK (0x1U) -#define GPTMR_SR_CH0RLDF_SHIFT (0U) -#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) -#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * CH3CMP1EN (RW) - * - * 1- generate interrupt request when ch3cmp1f flag is set - */ -#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) -#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) -#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) -#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) - -/* - * CH3CMP0EN (RW) - * - * 1- generate interrupt request when ch3cmp0f flag is set - */ -#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) -#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) -#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) -#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) - -/* - * CH3CAPEN (RW) - * - * 1- generate interrupt request when ch3capf flag is set - */ -#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) -#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) -#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) -#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) - -/* - * CH3RLDEN (RW) - * - * 1- generate interrupt request when ch3rldf flag is set - */ -#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) -#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) -#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) -#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) - -/* - * CH2CMP1EN (RW) - * - * 1- generate interrupt request when ch2cmp1f flag is set - */ -#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) -#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) -#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) -#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) - -/* - * CH2CMP0EN (RW) - * - * 1- generate interrupt request when ch2cmp0f flag is set - */ -#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) -#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) -#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) -#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) - -/* - * CH2CAPEN (RW) - * - * 1- generate interrupt request when ch2capf flag is set - */ -#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) -#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) -#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) -#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) - -/* - * CH2RLDEN (RW) - * - * 1- generate interrupt request when ch2rldf flag is set - */ -#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) -#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) -#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) -#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) - -/* - * CH1CMP1EN (RW) - * - * 1- generate interrupt request when ch1cmp1f flag is set - */ -#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) -#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) -#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) -#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) - -/* - * CH1CMP0EN (RW) - * - * 1- generate interrupt request when ch1cmp0f flag is set - */ -#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) -#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) -#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) -#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) - -/* - * CH1CAPEN (RW) - * - * 1- generate interrupt request when ch1capf flag is set - */ -#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) -#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) -#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) -#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) - -/* - * CH1RLDEN (RW) - * - * 1- generate interrupt request when ch1rldf flag is set - */ -#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) -#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) -#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) -#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) - -/* - * CH0CMP1EN (RW) - * - * 1- generate interrupt request when ch0cmp1f flag is set - */ -#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) -#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) -#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) -#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) - -/* - * CH0CMP0EN (RW) - * - * 1- generate interrupt request when ch0cmp0f flag is set - */ -#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) -#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) -#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) -#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) - -/* - * CH0CAPEN (RW) - * - * 1- generate interrupt request when ch0capf flag is set - */ -#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) -#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) -#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) -#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) - -/* - * CH0RLDEN (RW) - * - * 1- generate interrupt request when ch0rldf flag is set - */ -#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) -#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) -#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) -#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * SWSYNCT (RW) - * - * set this bitfield to trigger software counter sync event - */ -#define GPTMR_GCR_SWSYNCT_MASK (0xFU) -#define GPTMR_GCR_SWSYNCT_SHIFT (0U) -#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) -#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) - - - -/* CMP register group index macro definition */ -#define GPTMR_CHANNEL_CMP_CMP0 (0UL) -#define GPTMR_CHANNEL_CMP_CMP1 (1UL) - -/* CHANNEL register group index macro definition */ -#define GPTMR_CHANNEL_CH0 (0UL) -#define GPTMR_CHANNEL_CH1 (1UL) -#define GPTMR_CHANNEL_CH2 (2UL) -#define GPTMR_CHANNEL_CH3 (3UL) - - -#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_hall_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_hall_regs.h deleted file mode 100644 index 4b48f04c3d3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_hall_regs.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_HALL_H -#define HPM_HALL_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t UVWCFG; /* 0xC: U,V,W configure register */ - __RW uint32_t TRGOEN; /* 0x10: Trigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __R uint8_t RESERVED0[12]; /* 0x18 - 0x23: Reserved */ - __RW uint32_t DMAEN; /* 0x24: DMA enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request enable register */ - struct { - __R uint32_t W; /* 0x30: W counter */ - __R uint32_t V; /* 0x34: V counter */ - __R uint32_t U; /* 0x38: U counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - struct { - __R uint32_t HIS0; /* 0x70: history register 0 */ - __R uint32_t HIS1; /* 0x74: history register 1 */ - } HIS[3]; -} HALL_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load ucnt, vcnt, wcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define HALL_CR_READ_MASK (0x80000000UL) -#define HALL_CR_READ_SHIFT (31U) -#define HALL_CR_READ_SET(x) (((uint32_t)(x) << HALL_CR_READ_SHIFT) & HALL_CR_READ_MASK) -#define HALL_CR_READ_GET(x) (((uint32_t)(x) & HALL_CR_READ_MASK) >> HALL_CR_READ_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load ucnt, vcnt, wcnt and tmrcnt into their snap registers when snapi input assert - */ -#define HALL_CR_SNAPEN_MASK (0x800U) -#define HALL_CR_SNAPEN_SHIFT (11U) -#define HALL_CR_SNAPEN_SET(x) (((uint32_t)(x) << HALL_CR_SNAPEN_SHIFT) & HALL_CR_SNAPEN_MASK) -#define HALL_CR_SNAPEN_GET(x) (((uint32_t)(x) & HALL_CR_SNAPEN_MASK) >> HALL_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * set to reset all counter and related snapshots - */ -#define HALL_CR_RSTCNT_MASK (0x10U) -#define HALL_CR_RSTCNT_SHIFT (4U) -#define HALL_CR_RSTCNT_SET(x) (((uint32_t)(x) << HALL_CR_RSTCNT_SHIFT) & HALL_CR_RSTCNT_MASK) -#define HALL_CR_RSTCNT_GET(x) (((uint32_t)(x) & HALL_CR_RSTCNT_MASK) >> HALL_CR_RSTCNT_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * DLYSEL (RW) - * - * This bit select delay start time: - * 1- start counting delay after pre-trigger - * 0- start counting delay after u,v,w toggle - */ -#define HALL_PHCFG_DLYSEL_MASK (0x80000000UL) -#define HALL_PHCFG_DLYSEL_SHIFT (31U) -#define HALL_PHCFG_DLYSEL_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYSEL_SHIFT) & HALL_PHCFG_DLYSEL_MASK) -#define HALL_PHCFG_DLYSEL_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYSEL_MASK) >> HALL_PHCFG_DLYSEL_SHIFT) - -/* - * DLYCNT (RW) - * - * delay clock cycles number - */ -#define HALL_PHCFG_DLYCNT_MASK (0xFFFFFFUL) -#define HALL_PHCFG_DLYCNT_SHIFT (0U) -#define HALL_PHCFG_DLYCNT_SET(x) (((uint32_t)(x) << HALL_PHCFG_DLYCNT_SHIFT) & HALL_PHCFG_DLYCNT_MASK) -#define HALL_PHCFG_DLYCNT_GET(x) (((uint32_t)(x) & HALL_PHCFG_DLYCNT_MASK) >> HALL_PHCFG_DLYCNT_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define HALL_WDGCFG_WDGEN_MASK (0x80000000UL) -#define HALL_WDGCFG_WDGEN_SHIFT (31U) -#define HALL_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGEN_SHIFT) & HALL_WDGCFG_WDGEN_MASK) -#define HALL_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGEN_MASK) >> HALL_WDGCFG_WDGEN_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define HALL_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) -#define HALL_WDGCFG_WDGTO_SHIFT (0U) -#define HALL_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << HALL_WDGCFG_WDGTO_SHIFT) & HALL_WDGCFG_WDGTO_MASK) -#define HALL_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & HALL_WDGCFG_WDGTO_MASK) >> HALL_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: UVWCFG */ -/* - * PRECNT (RW) - * - * the clock cycle number which the pre flag will set before the next uvw transition - */ -#define HALL_UVWCFG_PRECNT_MASK (0xFFFFFFUL) -#define HALL_UVWCFG_PRECNT_SHIFT (0U) -#define HALL_UVWCFG_PRECNT_SET(x) (((uint32_t)(x) << HALL_UVWCFG_PRECNT_SHIFT) & HALL_UVWCFG_PRECNT_MASK) -#define HALL_UVWCFG_PRECNT_GET(x) (((uint32_t)(x) & HALL_UVWCFG_PRECNT_MASK) >> HALL_UVWCFG_PRECNT_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define HALL_TRGOEN_WDGEN_MASK (0x80000000UL) -#define HALL_TRGOEN_WDGEN_SHIFT (31U) -#define HALL_TRGOEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WDGEN_SHIFT) & HALL_TRGOEN_WDGEN_MASK) -#define HALL_TRGOEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WDGEN_MASK) >> HALL_TRGOEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- enable trigger output when phupt flag set - */ -#define HALL_TRGOEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_TRGOEN_PHUPTEN_SHIFT (30U) -#define HALL_TRGOEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHUPTEN_SHIFT) & HALL_TRGOEN_PHUPTEN_MASK) -#define HALL_TRGOEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHUPTEN_MASK) >> HALL_TRGOEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- enable trigger output when phpre flag set - */ -#define HALL_TRGOEN_PHPREEN_MASK (0x20000000UL) -#define HALL_TRGOEN_PHPREEN_SHIFT (29U) -#define HALL_TRGOEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHPREEN_SHIFT) & HALL_TRGOEN_PHPREEN_MASK) -#define HALL_TRGOEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHPREEN_MASK) >> HALL_TRGOEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- enable trigger output when phdly flag set - */ -#define HALL_TRGOEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_TRGOEN_PHDLYEN_SHIFT (28U) -#define HALL_TRGOEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_PHDLYEN_SHIFT) & HALL_TRGOEN_PHDLYEN_MASK) -#define HALL_TRGOEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_PHDLYEN_MASK) >> HALL_TRGOEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- enable trigger output when u flag set - */ -#define HALL_TRGOEN_UFEN_MASK (0x800000UL) -#define HALL_TRGOEN_UFEN_SHIFT (23U) -#define HALL_TRGOEN_UFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_UFEN_SHIFT) & HALL_TRGOEN_UFEN_MASK) -#define HALL_TRGOEN_UFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_UFEN_MASK) >> HALL_TRGOEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- enable trigger output when v flag set - */ -#define HALL_TRGOEN_VFEN_MASK (0x400000UL) -#define HALL_TRGOEN_VFEN_SHIFT (22U) -#define HALL_TRGOEN_VFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_VFEN_SHIFT) & HALL_TRGOEN_VFEN_MASK) -#define HALL_TRGOEN_VFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_VFEN_MASK) >> HALL_TRGOEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- enable trigger output when w flag set - */ -#define HALL_TRGOEN_WFEN_MASK (0x200000UL) -#define HALL_TRGOEN_WFEN_SHIFT (21U) -#define HALL_TRGOEN_WFEN_SET(x) (((uint32_t)(x) << HALL_TRGOEN_WFEN_SHIFT) & HALL_TRGOEN_WFEN_MASK) -#define HALL_TRGOEN_WFEN_GET(x) (((uint32_t)(x) & HALL_TRGOEN_WFEN_MASK) >> HALL_TRGOEN_WFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define HALL_READEN_WDGEN_MASK (0x80000000UL) -#define HALL_READEN_WDGEN_SHIFT (31U) -#define HALL_READEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_READEN_WDGEN_SHIFT) & HALL_READEN_WDGEN_MASK) -#define HALL_READEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_READEN_WDGEN_MASK) >> HALL_READEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- load counters to their read registers when phupt flag set - */ -#define HALL_READEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_READEN_PHUPTEN_SHIFT (30U) -#define HALL_READEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHUPTEN_SHIFT) & HALL_READEN_PHUPTEN_MASK) -#define HALL_READEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHUPTEN_MASK) >> HALL_READEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- load counters to their read registers when phpre flag set - */ -#define HALL_READEN_PHPREEN_MASK (0x20000000UL) -#define HALL_READEN_PHPREEN_SHIFT (29U) -#define HALL_READEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHPREEN_SHIFT) & HALL_READEN_PHPREEN_MASK) -#define HALL_READEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHPREEN_MASK) >> HALL_READEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- load counters to their read registers when phdly flag set - */ -#define HALL_READEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_READEN_PHDLYEN_SHIFT (28U) -#define HALL_READEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_READEN_PHDLYEN_SHIFT) & HALL_READEN_PHDLYEN_MASK) -#define HALL_READEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_READEN_PHDLYEN_MASK) >> HALL_READEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- load counters to their read registers when u flag set - */ -#define HALL_READEN_UFEN_MASK (0x800000UL) -#define HALL_READEN_UFEN_SHIFT (23U) -#define HALL_READEN_UFEN_SET(x) (((uint32_t)(x) << HALL_READEN_UFEN_SHIFT) & HALL_READEN_UFEN_MASK) -#define HALL_READEN_UFEN_GET(x) (((uint32_t)(x) & HALL_READEN_UFEN_MASK) >> HALL_READEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- load counters to their read registers when v flag set - */ -#define HALL_READEN_VFEN_MASK (0x400000UL) -#define HALL_READEN_VFEN_SHIFT (22U) -#define HALL_READEN_VFEN_SET(x) (((uint32_t)(x) << HALL_READEN_VFEN_SHIFT) & HALL_READEN_VFEN_MASK) -#define HALL_READEN_VFEN_GET(x) (((uint32_t)(x) & HALL_READEN_VFEN_MASK) >> HALL_READEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- load counters to their read registers when w flag set - */ -#define HALL_READEN_WFEN_MASK (0x200000UL) -#define HALL_READEN_WFEN_SHIFT (21U) -#define HALL_READEN_WFEN_SET(x) (((uint32_t)(x) << HALL_READEN_WFEN_SHIFT) & HALL_READEN_WFEN_MASK) -#define HALL_READEN_WFEN_GET(x) (((uint32_t)(x) & HALL_READEN_WFEN_MASK) >> HALL_READEN_WFEN_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define HALL_DMAEN_WDGEN_MASK (0x80000000UL) -#define HALL_DMAEN_WDGEN_SHIFT (31U) -#define HALL_DMAEN_WDGEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WDGEN_SHIFT) & HALL_DMAEN_WDGEN_MASK) -#define HALL_DMAEN_WDGEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WDGEN_MASK) >> HALL_DMAEN_WDGEN_SHIFT) - -/* - * PHUPTEN (RW) - * - * 1- generate dma request when phupt flag set - */ -#define HALL_DMAEN_PHUPTEN_MASK (0x40000000UL) -#define HALL_DMAEN_PHUPTEN_SHIFT (30U) -#define HALL_DMAEN_PHUPTEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHUPTEN_SHIFT) & HALL_DMAEN_PHUPTEN_MASK) -#define HALL_DMAEN_PHUPTEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHUPTEN_MASK) >> HALL_DMAEN_PHUPTEN_SHIFT) - -/* - * PHPREEN (RW) - * - * 1- generate dma request when phpre flag set - */ -#define HALL_DMAEN_PHPREEN_MASK (0x20000000UL) -#define HALL_DMAEN_PHPREEN_SHIFT (29U) -#define HALL_DMAEN_PHPREEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHPREEN_SHIFT) & HALL_DMAEN_PHPREEN_MASK) -#define HALL_DMAEN_PHPREEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHPREEN_MASK) >> HALL_DMAEN_PHPREEN_SHIFT) - -/* - * PHDLYEN (RW) - * - * 1- generate dma request when phdly flag set - */ -#define HALL_DMAEN_PHDLYEN_MASK (0x10000000UL) -#define HALL_DMAEN_PHDLYEN_SHIFT (28U) -#define HALL_DMAEN_PHDLYEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_PHDLYEN_SHIFT) & HALL_DMAEN_PHDLYEN_MASK) -#define HALL_DMAEN_PHDLYEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_PHDLYEN_MASK) >> HALL_DMAEN_PHDLYEN_SHIFT) - -/* - * UFEN (RW) - * - * 1- generate dma request when u flag set - */ -#define HALL_DMAEN_UFEN_MASK (0x800000UL) -#define HALL_DMAEN_UFEN_SHIFT (23U) -#define HALL_DMAEN_UFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_UFEN_SHIFT) & HALL_DMAEN_UFEN_MASK) -#define HALL_DMAEN_UFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_UFEN_MASK) >> HALL_DMAEN_UFEN_SHIFT) - -/* - * VFEN (RW) - * - * 1- generate dma request when v flag set - */ -#define HALL_DMAEN_VFEN_MASK (0x400000UL) -#define HALL_DMAEN_VFEN_SHIFT (22U) -#define HALL_DMAEN_VFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_VFEN_SHIFT) & HALL_DMAEN_VFEN_MASK) -#define HALL_DMAEN_VFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_VFEN_MASK) >> HALL_DMAEN_VFEN_SHIFT) - -/* - * WFEN (RW) - * - * 1- generate dma request when w flag set - */ -#define HALL_DMAEN_WFEN_MASK (0x200000UL) -#define HALL_DMAEN_WFEN_SHIFT (21U) -#define HALL_DMAEN_WFEN_SET(x) (((uint32_t)(x) << HALL_DMAEN_WFEN_SHIFT) & HALL_DMAEN_WFEN_MASK) -#define HALL_DMAEN_WFEN_GET(x) (((uint32_t)(x) & HALL_DMAEN_WFEN_MASK) >> HALL_DMAEN_WFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog count timeout flag - */ -#define HALL_SR_WDGF_MASK (0x80000000UL) -#define HALL_SR_WDGF_SHIFT (31U) -#define HALL_SR_WDGF_SET(x) (((uint32_t)(x) << HALL_SR_WDGF_SHIFT) & HALL_SR_WDGF_MASK) -#define HALL_SR_WDGF_GET(x) (((uint32_t)(x) & HALL_SR_WDGF_MASK) >> HALL_SR_WDGF_SHIFT) - -/* - * PHUPTF (RW) - * - * phase update flag, will set when any of u, v, w signal toggle - */ -#define HALL_SR_PHUPTF_MASK (0x40000000UL) -#define HALL_SR_PHUPTF_SHIFT (30U) -#define HALL_SR_PHUPTF_SET(x) (((uint32_t)(x) << HALL_SR_PHUPTF_SHIFT) & HALL_SR_PHUPTF_MASK) -#define HALL_SR_PHUPTF_GET(x) (((uint32_t)(x) & HALL_SR_PHUPTF_MASK) >> HALL_SR_PHUPTF_SHIFT) - -/* - * PHPREF (RW) - * - * phase update pre flag, will set PRECNT cycles before any of u, v, w signal toggle - */ -#define HALL_SR_PHPREF_MASK (0x20000000UL) -#define HALL_SR_PHPREF_SHIFT (29U) -#define HALL_SR_PHPREF_SET(x) (((uint32_t)(x) << HALL_SR_PHPREF_SHIFT) & HALL_SR_PHPREF_MASK) -#define HALL_SR_PHPREF_GET(x) (((uint32_t)(x) & HALL_SR_PHPREF_MASK) >> HALL_SR_PHPREF_SHIFT) - -/* - * PHDLYF (RW) - * - * phase update delay flag, will set DLYCNT cycles after any of u, v, w signal toggle or after the phpre flag depands on DLYSEL setting - */ -#define HALL_SR_PHDLYF_MASK (0x10000000UL) -#define HALL_SR_PHDLYF_SHIFT (28U) -#define HALL_SR_PHDLYF_SET(x) (((uint32_t)(x) << HALL_SR_PHDLYF_SHIFT) & HALL_SR_PHDLYF_MASK) -#define HALL_SR_PHDLYF_GET(x) (((uint32_t)(x) & HALL_SR_PHDLYF_MASK) >> HALL_SR_PHDLYF_SHIFT) - -/* - * UF (RW) - * - * u flag, will set when u signal toggle - */ -#define HALL_SR_UF_MASK (0x800000UL) -#define HALL_SR_UF_SHIFT (23U) -#define HALL_SR_UF_SET(x) (((uint32_t)(x) << HALL_SR_UF_SHIFT) & HALL_SR_UF_MASK) -#define HALL_SR_UF_GET(x) (((uint32_t)(x) & HALL_SR_UF_MASK) >> HALL_SR_UF_SHIFT) - -/* - * VF (RW) - * - * v flag, will set when v signal toggle - */ -#define HALL_SR_VF_MASK (0x400000UL) -#define HALL_SR_VF_SHIFT (22U) -#define HALL_SR_VF_SET(x) (((uint32_t)(x) << HALL_SR_VF_SHIFT) & HALL_SR_VF_MASK) -#define HALL_SR_VF_GET(x) (((uint32_t)(x) & HALL_SR_VF_MASK) >> HALL_SR_VF_SHIFT) - -/* - * WF (RW) - * - * w flag, will set when w signal toggle - */ -#define HALL_SR_WF_MASK (0x200000UL) -#define HALL_SR_WF_SHIFT (21U) -#define HALL_SR_WF_SET(x) (((uint32_t)(x) << HALL_SR_WF_SHIFT) & HALL_SR_WF_MASK) -#define HALL_SR_WF_GET(x) (((uint32_t)(x) & HALL_SR_WF_MASK) >> HALL_SR_WF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt request when wdg flag set - */ -#define HALL_IRQEN_WDGIE_MASK (0x80000000UL) -#define HALL_IRQEN_WDGIE_SHIFT (31U) -#define HALL_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WDGIE_SHIFT) & HALL_IRQEN_WDGIE_MASK) -#define HALL_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WDGIE_MASK) >> HALL_IRQEN_WDGIE_SHIFT) - -/* - * PHUPTIE (RW) - * - * 1- generate interrupt request when phupt flag set - */ -#define HALL_IRQEN_PHUPTIE_MASK (0x40000000UL) -#define HALL_IRQEN_PHUPTIE_SHIFT (30U) -#define HALL_IRQEN_PHUPTIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHUPTIE_SHIFT) & HALL_IRQEN_PHUPTIE_MASK) -#define HALL_IRQEN_PHUPTIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHUPTIE_MASK) >> HALL_IRQEN_PHUPTIE_SHIFT) - -/* - * PHPREIE (RW) - * - * 1- generate interrupt request when phpre flag set - */ -#define HALL_IRQEN_PHPREIE_MASK (0x20000000UL) -#define HALL_IRQEN_PHPREIE_SHIFT (29U) -#define HALL_IRQEN_PHPREIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHPREIE_SHIFT) & HALL_IRQEN_PHPREIE_MASK) -#define HALL_IRQEN_PHPREIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHPREIE_MASK) >> HALL_IRQEN_PHPREIE_SHIFT) - -/* - * PHDLYIE (RW) - * - * 1- generate interrupt request when phdly flag set - */ -#define HALL_IRQEN_PHDLYIE_MASK (0x10000000UL) -#define HALL_IRQEN_PHDLYIE_SHIFT (28U) -#define HALL_IRQEN_PHDLYIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_PHDLYIE_SHIFT) & HALL_IRQEN_PHDLYIE_MASK) -#define HALL_IRQEN_PHDLYIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_PHDLYIE_MASK) >> HALL_IRQEN_PHDLYIE_SHIFT) - -/* - * UFIE (RW) - * - * 1- generate interrupt request when u flag set - */ -#define HALL_IRQEN_UFIE_MASK (0x800000UL) -#define HALL_IRQEN_UFIE_SHIFT (23U) -#define HALL_IRQEN_UFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_UFIE_SHIFT) & HALL_IRQEN_UFIE_MASK) -#define HALL_IRQEN_UFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_UFIE_MASK) >> HALL_IRQEN_UFIE_SHIFT) - -/* - * VFIE (RW) - * - * 1- generate interrupt request when v flag set - */ -#define HALL_IRQEN_VFIE_MASK (0x400000UL) -#define HALL_IRQEN_VFIE_SHIFT (22U) -#define HALL_IRQEN_VFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_VFIE_SHIFT) & HALL_IRQEN_VFIE_MASK) -#define HALL_IRQEN_VFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_VFIE_MASK) >> HALL_IRQEN_VFIE_SHIFT) - -/* - * WFIE (RW) - * - * 1- generate interrupt request when w flag set - */ -#define HALL_IRQEN_WFIE_MASK (0x200000UL) -#define HALL_IRQEN_WFIE_SHIFT (21U) -#define HALL_IRQEN_WFIE_SET(x) (((uint32_t)(x) << HALL_IRQEN_WFIE_SHIFT) & HALL_IRQEN_WFIE_MASK) -#define HALL_IRQEN_WFIE_GET(x) (((uint32_t)(x) & HALL_IRQEN_WFIE_MASK) >> HALL_IRQEN_WFIE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: W */ -/* - * WCNT (RO) - * - * wcnt counter - */ -#define HALL_COUNT_W_WCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_W_WCNT_SHIFT (0U) -#define HALL_COUNT_W_WCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_W_WCNT_MASK) >> HALL_COUNT_W_WCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: V */ -/* - * VCNT (RO) - * - * vcnt counter - */ -#define HALL_COUNT_V_VCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_V_VCNT_SHIFT (0U) -#define HALL_COUNT_V_VCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_V_VCNT_MASK) >> HALL_COUNT_V_VCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: U */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define HALL_COUNT_U_DIR_MASK (0x80000000UL) -#define HALL_COUNT_U_DIR_SHIFT (31U) -#define HALL_COUNT_U_DIR_GET(x) (((uint32_t)(x) & HALL_COUNT_U_DIR_MASK) >> HALL_COUNT_U_DIR_SHIFT) - -/* - * USTAT (RO) - * - * this bit indicate U state - */ -#define HALL_COUNT_U_USTAT_MASK (0x40000000UL) -#define HALL_COUNT_U_USTAT_SHIFT (30U) -#define HALL_COUNT_U_USTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_USTAT_MASK) >> HALL_COUNT_U_USTAT_SHIFT) - -/* - * VSTAT (RO) - * - * this bit indicate V state - */ -#define HALL_COUNT_U_VSTAT_MASK (0x20000000UL) -#define HALL_COUNT_U_VSTAT_SHIFT (29U) -#define HALL_COUNT_U_VSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_VSTAT_MASK) >> HALL_COUNT_U_VSTAT_SHIFT) - -/* - * WSTAT (RO) - * - * this bit indicate W state - */ -#define HALL_COUNT_U_WSTAT_MASK (0x10000000UL) -#define HALL_COUNT_U_WSTAT_SHIFT (28U) -#define HALL_COUNT_U_WSTAT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_WSTAT_MASK) >> HALL_COUNT_U_WSTAT_SHIFT) - -/* - * UCNT (RO) - * - * ucnt counter - */ -#define HALL_COUNT_U_UCNT_MASK (0xFFFFFFFUL) -#define HALL_COUNT_U_UCNT_SHIFT (0U) -#define HALL_COUNT_U_UCNT_GET(x) (((uint32_t)(x) & HALL_COUNT_U_UCNT_MASK) >> HALL_COUNT_U_UCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TIMER (RO) - * - * 32 bit free run timer - */ -#define HALL_COUNT_TMR_TIMER_MASK (0xFFFFFFFFUL) -#define HALL_COUNT_TMR_TIMER_SHIFT (0U) -#define HALL_COUNT_TMR_TIMER_GET(x) (((uint32_t)(x) & HALL_COUNT_TMR_TIMER_MASK) >> HALL_COUNT_TMR_TIMER_SHIFT) - -/* Bitfield definition for register of struct array HIS: HIS0 */ -/* - * UHIS0 (RO) - * - * copy of ucnt when u signal transition from 0 to 1 - */ -#define HALL_HIS_HIS0_UHIS0_MASK (0xFFFFFFFFUL) -#define HALL_HIS_HIS0_UHIS0_SHIFT (0U) -#define HALL_HIS_HIS0_UHIS0_GET(x) (((uint32_t)(x) & HALL_HIS_HIS0_UHIS0_MASK) >> HALL_HIS_HIS0_UHIS0_SHIFT) - -/* Bitfield definition for register of struct array HIS: HIS1 */ -/* - * UHIS1 (RO) - * - * copy of ucnt when u signal transition from 1 to 0 - */ -#define HALL_HIS_HIS1_UHIS1_MASK (0xFFFFFFFFUL) -#define HALL_HIS_HIS1_UHIS1_SHIFT (0U) -#define HALL_HIS_HIS1_UHIS1_GET(x) (((uint32_t)(x) & HALL_HIS_HIS1_UHIS1_MASK) >> HALL_HIS_HIS1_UHIS1_SHIFT) - - - -/* COUNT register group index macro definition */ -#define HALL_COUNT_CURRENT (0UL) -#define HALL_COUNT_READ (1UL) -#define HALL_COUNT_SNAP0 (2UL) -#define HALL_COUNT_SNAP1 (3UL) - -/* HIS register group index macro definition */ -#define HALL_HIS_U (0UL) -#define HALL_HIS_V (1UL) -#define HALL_HIS_W (2UL) - - -#endif /* HPM_HALL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_i2c_regs.h deleted file mode 100644 index 5c5c0025996..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_i2c_regs.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2C_H -#define HPM_I2C_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ - __RW uint32_t STATUS; /* 0x18: Status Register */ - __RW uint32_t ADDR; /* 0x1C: Address Register */ - __RW uint32_t DATA; /* 0x20: Data Register */ - __RW uint32_t CTRL; /* 0x24: Control Register */ - __RW uint32_t CMD; /* 0x28: Command Register */ - __RW uint32_t SETUP; /* 0x2C: Setup Register */ - __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ -} I2C_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * FIFO Size: - * 0: 2 bytes - * 1: 4 bytes - * 2: 8 bytes - * 3: 16 bytes - */ -#define I2C_CFG_FIFOSIZE_MASK (0x3U) -#define I2C_CFG_FIFOSIZE_SHIFT (0U) -#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * CMPL (RW) - * - * Set to enable the Completion Interrupt. - * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. - * Slave: interrupts when a transaction addressing the controller is completed. - */ -#define I2C_INTEN_CMPL_MASK (0x200U) -#define I2C_INTEN_CMPL_SHIFT (9U) -#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) -#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) - -/* - * BYTERECV (RW) - * - * Set to enable the Byte Receive Interrupt. - * Interrupts when a byte of data is received - * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - */ -#define I2C_INTEN_BYTERECV_MASK (0x100U) -#define I2C_INTEN_BYTERECV_SHIFT (8U) -#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) -#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) - -/* - * BYTETRANS (RW) - * - * Set to enable the Byte Transmit Interrupt. - * Interrupts when a byte of data is transmitted. - */ -#define I2C_INTEN_BYTETRANS_MASK (0x80U) -#define I2C_INTEN_BYTETRANS_SHIFT (7U) -#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) -#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) - -/* - * START (RW) - * - * Set to enable the START Condition Interrupt. - * Interrupts when a START condition/repeated START condition is detected. - */ -#define I2C_INTEN_START_MASK (0x40U) -#define I2C_INTEN_START_SHIFT (6U) -#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) -#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) - -/* - * STOP (RW) - * - * Set to enable the STOP Condition Interrupt - * Interrupts when a STOP condition is detected. - */ -#define I2C_INTEN_STOP_MASK (0x20U) -#define I2C_INTEN_STOP_SHIFT (5U) -#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) -#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) - -/* - * ARBLOSE (RW) - * - * Set to enable the Arbitration Lose Interrupt. - * Master: interrupts when the controller loses the bus arbitration - * Slave: not available in this mode. - */ -#define I2C_INTEN_ARBLOSE_MASK (0x10U) -#define I2C_INTEN_ARBLOSE_SHIFT (4U) -#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) -#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) - -/* - * ADDRHIT (RW) - * - * Set to enable the Address Hit Interrupt. - * Master: interrupts when the addressed slave returned an ACK. - * Slave: interrupts when the controller is addressed. - */ -#define I2C_INTEN_ADDRHIT_MASK (0x8U) -#define I2C_INTEN_ADDRHIT_SHIFT (3U) -#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) -#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RW) - * - * Set to enable the FIFO Half Interrupt. - * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. - * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. - * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - */ -#define I2C_INTEN_FIFOHALF_MASK (0x4U) -#define I2C_INTEN_FIFOHALF_SHIFT (2U) -#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) -#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RW) - * - * Set to enable the FIFO Full Interrupt. - * Interrupts when the FIFO is full. - */ -#define I2C_INTEN_FIFOFULL_MASK (0x2U) -#define I2C_INTEN_FIFOFULL_SHIFT (1U) -#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) -#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RW) - * - * Set to enabled the FIFO Empty Interrupt - * Interrupts when the FIFO is empty. - */ -#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) -#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) -#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) -#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * LINESDA (RO) - * - * Indicates the current status of the SDA line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESDA_MASK (0x4000U) -#define I2C_STATUS_LINESDA_SHIFT (14U) -#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) - -/* - * LINESCL (RO) - * - * Indicates the current status of the SCL line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESCL_MASK (0x2000U) -#define I2C_STATUS_LINESCL_SHIFT (13U) -#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) - -/* - * GENCALL (RO) - * - * Indicates that the address of the current transaction is a general call address: - * 1: General call - * 0: Not general call - */ -#define I2C_STATUS_GENCALL_MASK (0x1000U) -#define I2C_STATUS_GENCALL_SHIFT (12U) -#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) - -/* - * BUSBUSY (RO) - * - * Indicates that the bus is busy - * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus - * 1: Busy - * 0: Not busy - */ -#define I2C_STATUS_BUSBUSY_MASK (0x800U) -#define I2C_STATUS_BUSBUSY_SHIFT (11U) -#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) - -/* - * ACK (RO) - * - * Indicates the type of the last received/transmitted acknowledgement bit: - * 1: ACK - * 0: NACK - */ -#define I2C_STATUS_ACK_MASK (0x400U) -#define I2C_STATUS_ACK_SHIFT (10U) -#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) - -/* - * CMPL (W1C) - * - * Transaction Completion - * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration - * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - */ -#define I2C_STATUS_CMPL_MASK (0x200U) -#define I2C_STATUS_CMPL_SHIFT (9U) -#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) -#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) - -/* - * BYTERECV (W1C) - * - * Indicates that a byte of data has been received. - */ -#define I2C_STATUS_BYTERECV_MASK (0x100U) -#define I2C_STATUS_BYTERECV_SHIFT (8U) -#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) -#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) - -/* - * BYTETRANS (W1C) - * - * Indicates that a byte of data has been transmitted. - */ -#define I2C_STATUS_BYTETRANS_MASK (0x80U) -#define I2C_STATUS_BYTETRANS_SHIFT (7U) -#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) -#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) - -/* - * START (W1C) - * - * Indicates that a START Condition or a repeated START condition has been transmitted/received. - */ -#define I2C_STATUS_START_MASK (0x40U) -#define I2C_STATUS_START_SHIFT (6U) -#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) -#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) - -/* - * STOP (W1C) - * - * Indicates that a STOP Condition has been transmitted/received. - */ -#define I2C_STATUS_STOP_MASK (0x20U) -#define I2C_STATUS_STOP_SHIFT (5U) -#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) -#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) - -/* - * ARBLOSE (W1C) - * - * Indicates that the controller has lost the bus arbitration. - */ -#define I2C_STATUS_ARBLOSE_MASK (0x10U) -#define I2C_STATUS_ARBLOSE_SHIFT (4U) -#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) -#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) - -/* - * ADDRHIT (W1C) - * - * Master: indicates that a slave has responded to the transaction. - * Slave: indicates that a transaction is targeting the controller (including the General Call). - */ -#define I2C_STATUS_ADDRHIT_MASK (0x8U) -#define I2C_STATUS_ADDRHIT_SHIFT (3U) -#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) -#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RO) - * - * Transmitter: Indicates that the FIFO is half-empty. - */ -#define I2C_STATUS_FIFOHALF_MASK (0x4U) -#define I2C_STATUS_FIFOHALF_SHIFT (2U) -#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RO) - * - * Indicates that the FIFO is full. - */ -#define I2C_STATUS_FIFOFULL_MASK (0x2U) -#define I2C_STATUS_FIFOFULL_SHIFT (1U) -#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RO) - * - * Indicates that the FIFO is empty. - */ -#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) -#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) -#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * The slave address. - * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - */ -#define I2C_ADDR_ADDR_MASK (0x3FFU) -#define I2C_ADDR_ADDR_SHIFT (0U) -#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) -#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Write this register to put one byte of data to the FIFO. - * Read this register to get one byte of data from the FIFO. - */ -#define I2C_DATA_DATA_MASK (0xFFU) -#define I2C_DATA_DATA_SHIFT (0U) -#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) -#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * PHASE_START (RW) - * - * Enable this bit to send a START condition at the beginning of transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_START_MASK (0x1000U) -#define I2C_CTRL_PHASE_START_SHIFT (12U) -#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) -#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) - -/* - * PHASE_ADDR (RW) - * - * Enable this bit to send the address after START condition. - * Master mode only. - */ -#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) -#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) -#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) -#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) - -/* - * PHASE_DATA (RW) - * - * Enable this bit to send the data after Address phase. - * Master mode only. - */ -#define I2C_CTRL_PHASE_DATA_MASK (0x400U) -#define I2C_CTRL_PHASE_DATA_SHIFT (10U) -#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) -#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) - -/* - * PHASE_STOP (RW) - * - * Enable this bit to send a STOP condition at the end of a transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_STOP_MASK (0x200U) -#define I2C_CTRL_PHASE_STOP_SHIFT (9U) -#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) -#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) - -/* - * DIR (RW) - * - * Transaction direction - * Master: Set this bit to determine the direction for the next transaction. - * 0: Transmitter - * 1: Receiver - * Slave: The direction of the last received transaction. - * 0: Receiver - * 1: Transmitter - */ -#define I2C_CTRL_DIR_MASK (0x100U) -#define I2C_CTRL_DIR_SHIFT (8U) -#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) -#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) - -/* - * DATACNT (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_MASK (0xFFU) -#define I2C_CTRL_DATACNT_SHIFT (0U) -#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) -#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * Write this register with the following values to perform the corresponding actions: - * 0x0: no action - * 0x1: issue a data transaction (Master only) - * 0x2: respond with an ACK to the received byte - * 0x3: respond with a NACK to the received byte - * 0x4: clear the FIFO - * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) - * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. - * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - */ -#define I2C_CMD_CMD_MASK (0x7U) -#define I2C_CMD_CMD_SHIFT (0U) -#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) -#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) - -/* Bitfield definition for register: SETUP */ -/* - * T_SUDAT (RW) - * - * T_SUDAT defines the data setup time before releasing the SCL. - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) - * tpclk = PCLK period - * TPM = The multiplier value in Timing Parameter Multiplier Register - */ -#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) -#define I2C_SETUP_T_SUDAT_SHIFT (24U) -#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) -#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) - -/* - * T_SP (RW) - * - * T_SP defines the pulse width of spikes that must be suppressed by the input filter. - * Pulse width = T_SP * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_SP_MASK (0xE00000UL) -#define I2C_SETUP_T_SP_SHIFT (21U) -#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) -#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) - -/* - * T_HDDAT (RW) - * - * T_HDDAT defines the data hold time after SCL goes LOW - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) -#define I2C_SETUP_T_HDDAT_SHIFT (16U) -#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) -#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) - -/* - * T_SCLRADIO (RW) - * - * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. - * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) - * 1: ratio = 2 - * 0: ratio = 1 - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) -#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) -#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) -#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) - -/* - * T_SCLHI (RW) - * - * The HIGH period of generated SCL clock is defined by T_SCLHi. - * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) - * The T_SCLHi value must be greater than T_SP and T_HDDAT values. - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) -#define I2C_SETUP_T_SCLHI_SHIFT (4U) -#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) -#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) - -/* - * DMAEN (RW) - * - * Enable the direct memory access mode data transfer. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_DMAEN_MASK (0x8U) -#define I2C_SETUP_DMAEN_SHIFT (3U) -#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) -#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) - -/* - * MASTER (RW) - * - * Configure this device as a master or a slave. - * 1: Master mode - * 0: Slave mode - */ -#define I2C_SETUP_MASTER_MASK (0x4U) -#define I2C_SETUP_MASTER_SHIFT (2U) -#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) -#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) - -/* - * ADDRESSING (RW) - * - * I2C addressing mode: - * 1: 10-bit addressing mode - * 0: 7-bit addressing mode - */ -#define I2C_SETUP_ADDRESSING_MASK (0x2U) -#define I2C_SETUP_ADDRESSING_SHIFT (1U) -#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) -#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) - -/* - * IICEN (RW) - * - * Enable the I2C controller. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_IICEN_MASK (0x1U) -#define I2C_SETUP_IICEN_SHIFT (0U) -#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) -#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) - -/* Bitfield definition for register: TPM */ -/* - * TPM (RW) - * - * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - */ -#define I2C_TPM_TPM_MASK (0x1FU) -#define I2C_TPM_TPM_SHIFT (0U) -#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) -#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) - - - - -#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_i2s_regs.h deleted file mode 100644 index 3d3b34d7aab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_i2s_regs.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2S_H -#define HPM_I2S_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint32_t RFIFO_FILLINGS; /* 0x4: Rx FIFO Filling Level */ - __R uint32_t TFIFO_FILLINGS; /* 0x8: Tx FIFO Filling Level */ - __RW uint32_t FIFO_THRESH; /* 0xC: TX/RX FIFO Threshold setting. */ - __RW uint32_t STA; /* 0x10: Status Registers */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXD[4]; /* 0x20 - 0x2C: Rx Data0 */ - __W uint32_t TXD[4]; /* 0x30 - 0x3C: Tx Data0 */ - __R uint8_t RESERVED1[16]; /* 0x40 - 0x4F: Reserved */ - __RW uint32_t CFGR; /* 0x50: Configruation Regsiters */ - __R uint8_t RESERVED2[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t MISC_CFGR; /* 0x58: Misc configuration Registers */ - __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */ - __RW uint32_t RXDSLOT[4]; /* 0x60 - 0x6C: Rx Slots Enable for Rx Data0 */ - __RW uint32_t TXDSLOT[4]; /* 0x70 - 0x7C: Tx Slots Enable for Tx Data0. */ -} I2S_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST_RX (RW) - * - * software reset the RX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_RX_MASK (0x40000UL) -#define I2S_CTRL_SFTRST_RX_SHIFT (18U) -#define I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK) -#define I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT) - -/* - * SFTRST_TX (RW) - * - * software reset the TX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_TX_MASK (0x20000UL) -#define I2S_CTRL_SFTRST_TX_SHIFT (17U) -#define I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK) -#define I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT) - -/* - * SFTRST_CLKGEN (RW) - * - * software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL) -#define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U) -#define I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK) -#define I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT) - -/* - * TXDNIE (RW) - * - * TX buffer data needed interrupt enable - * 0: TXE interrupt masked - * 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - */ -#define I2S_CTRL_TXDNIE_MASK (0x8000U) -#define I2S_CTRL_TXDNIE_SHIFT (15U) -#define I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK) -#define I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT) - -/* - * RXDAIE (RW) - * - * RX buffer data available interrupt enable - * 0: RXNE interrupt masked - * 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - */ -#define I2S_CTRL_RXDAIE_MASK (0x4000U) -#define I2S_CTRL_RXDAIE_SHIFT (14U) -#define I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK) -#define I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT) - -/* - * ERRIE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define I2S_CTRL_ERRIE_MASK (0x2000U) -#define I2S_CTRL_ERRIE_SHIFT (13U) -#define I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK) -#define I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT) - -/* - * TX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_TX_DMA_EN_MASK (0x1000U) -#define I2S_CTRL_TX_DMA_EN_SHIFT (12U) -#define I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK) -#define I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT) - -/* - * RX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_RX_DMA_EN_MASK (0x800U) -#define I2S_CTRL_RX_DMA_EN_SHIFT (11U) -#define I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK) -#define I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT) - -/* - * TXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_TXFIFOCLR_MASK (0x400U) -#define I2S_CTRL_TXFIFOCLR_SHIFT (10U) -#define I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK) -#define I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT) - -/* - * RXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_RXFIFOCLR_MASK (0x200U) -#define I2S_CTRL_RXFIFOCLR_SHIFT (9U) -#define I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK) -#define I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT) - -/* - * TX_EN (RW) - * - * enable for each TX data pad - */ -#define I2S_CTRL_TX_EN_MASK (0x1E0U) -#define I2S_CTRL_TX_EN_SHIFT (5U) -#define I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK) -#define I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT) - -/* - * RX_EN (RW) - * - * enable for each RX data pad - */ -#define I2S_CTRL_RX_EN_MASK (0x1EU) -#define I2S_CTRL_RX_EN_SHIFT (1U) -#define I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK) -#define I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT) - -/* - * I2S_EN (RW) - * - * enable for the module - */ -#define I2S_CTRL_I2S_EN_MASK (0x1U) -#define I2S_CTRL_I2S_EN_SHIFT (0U) -#define I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK) -#define I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT) - -/* Bitfield definition for register: RFIFO_FILLINGS */ -/* - * RX3 (RO) - * - * RX3 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL) -#define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U) -#define I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT) - -/* - * RX2 (RO) - * - * RX2 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL) -#define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U) -#define I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT) - -/* - * RX1 (RO) - * - * RX1 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U) -#define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U) -#define I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT) - -/* - * RX0 (RO) - * - * RX0 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU) -#define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U) -#define I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT) - -/* Bitfield definition for register: TFIFO_FILLINGS */ -/* - * TX3 (RO) - * - * TX3 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL) -#define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U) -#define I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT) - -/* - * TX2 (RO) - * - * TX2 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL) -#define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U) -#define I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT) - -/* - * TX1 (RO) - * - * TX1 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U) -#define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U) -#define I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT) - -/* - * TX0 (RO) - * - * TX0 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU) -#define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U) -#define I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT) - -/* Bitfield definition for register: FIFO_THRESH */ -/* - * TX (RW) - * - * TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - */ -#define I2S_FIFO_THRESH_TX_MASK (0xFF00U) -#define I2S_FIFO_THRESH_TX_SHIFT (8U) -#define I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK) -#define I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT) - -/* - * RX (RW) - * - * RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - */ -#define I2S_FIFO_THRESH_RX_MASK (0xFFU) -#define I2S_FIFO_THRESH_RX_SHIFT (0U) -#define I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK) -#define I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TX_UD (W1C) - * - * Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - */ -#define I2S_STA_TX_UD_MASK (0x1E000UL) -#define I2S_STA_TX_UD_SHIFT (13U) -#define I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK) -#define I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT) - -/* - * RX_OV (W1C) - * - * Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - */ -#define I2S_STA_RX_OV_MASK (0x1E00U) -#define I2S_STA_RX_OV_SHIFT (9U) -#define I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK) -#define I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT) - -/* - * TX_DN (RO) - * - * Asserted when tx fifo data are needed. - */ -#define I2S_STA_TX_DN_MASK (0x1E0U) -#define I2S_STA_TX_DN_SHIFT (5U) -#define I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT) - -/* - * RX_DA (RO) - * - * Asserted when rx fifo data are available. - */ -#define I2S_STA_RX_DA_MASK (0x1EU) -#define I2S_STA_RX_DA_SHIFT (1U) -#define I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT) - -/* Bitfield definition for register array: RXD */ -/* - * D (RO) - * - */ -#define I2S_RXD_D_MASK (0xFFFFFFFFUL) -#define I2S_RXD_D_SHIFT (0U) -#define I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT) - -/* Bitfield definition for register array: TXD */ -/* - * D (WO) - * - */ -#define I2S_TXD_D_MASK (0xFFFFFFFFUL) -#define I2S_TXD_D_SHIFT (0U) -#define I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK) -#define I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT) - -/* Bitfield definition for register: CFGR */ -/* - * BCLK_GATEOFF (RW) - * - * Gate off the bclk. Asserted to gate-off the BCLK. - */ -#define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL) -#define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U) -#define I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK) -#define I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT) - -/* - * BCLK_DIV (RW) - * - * Linear prescaler to generate BCLK from MCLK. - * BCLK_DIV [8:0] = 0: BCLK=No CLK. - * BCLK_DIV [8:0] = 1: BCLK=MCLK/1 - * BCLK_DIV [8:0] = n: BCLK=MCLK/(n). - * Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL) -#define I2S_CFGR_BCLK_DIV_SHIFT (21U) -#define I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK) -#define I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT) - -/* - * INV_BCLK_OUT (RW) - * - * Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - */ -#define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL) -#define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U) -#define I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK) -#define I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT) - -/* - * INV_BCLK_IN (RW) - * - * Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - */ -#define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL) -#define I2S_CFGR_INV_BCLK_IN_SHIFT (19U) -#define I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK) -#define I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT) - -/* - * INV_FCLK_OUT (RW) - * - * Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - */ -#define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL) -#define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U) -#define I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK) -#define I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT) - -/* - * INV_FCLK_IN (RW) - * - * Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - */ -#define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL) -#define I2S_CFGR_INV_FCLK_IN_SHIFT (17U) -#define I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK) -#define I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT) - -/* - * INV_MCLK_OUT (RW) - * - * Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - */ -#define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL) -#define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U) -#define I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK) -#define I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT) - -/* - * INV_MCLK_IN (RW) - * - * Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - */ -#define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U) -#define I2S_CFGR_INV_MCLK_IN_SHIFT (15U) -#define I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK) -#define I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT) - -/* - * BCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U) -#define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U) -#define I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK) -#define I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT) - -/* - * FCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U) -#define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U) -#define I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK) -#define I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT) - -/* - * MCK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U) -#define I2S_CFGR_MCK_SEL_OP_SHIFT (12U) -#define I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK) -#define I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT) - -/* - * FRAME_EDGE (RW) - * - * The start edge of a frame - * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) - * 1: Rising edge indicates a new frame - */ -#define I2S_CFGR_FRAME_EDGE_MASK (0x800U) -#define I2S_CFGR_FRAME_EDGE_SHIFT (11U) -#define I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK) -#define I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT) - -/* - * CH_MAX (RW) - * - * CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 5'h2: 2 channels - * 5'h4: 4 channels - * ... - * 5‘h10: 16 channels (max) - */ -#define I2S_CFGR_CH_MAX_MASK (0x7C0U) -#define I2S_CFGR_CH_MAX_SHIFT (6U) -#define I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK) -#define I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT) - -/* - * TDM_EN (RW) - * - * TDM mode - * 0: not TDM mode - * 1: TDM mode - */ -#define I2S_CFGR_TDM_EN_MASK (0x20U) -#define I2S_CFGR_TDM_EN_SHIFT (5U) -#define I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK) -#define I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT) - -/* - * STD (RW) - * - * I2S standard selection - * 00: I2S Philips standard. - * 01: MSB justified standard (left justified) - * 10: LSB justified standard (right justified) - * 11: PCM standard - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_STD_MASK (0x18U) -#define I2S_CFGR_STD_SHIFT (3U) -#define I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK) -#define I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT) - -/* - * DATSIZ (RW) - * - * Data length to be transferred - * 00: 16-bit data length - * 01: 24-bit data length - * 10: 32-bit data length - * 11: Not allowed - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_DATSIZ_MASK (0x6U) -#define I2S_CFGR_DATSIZ_SHIFT (1U) -#define I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK) -#define I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT) - -/* - * CHSIZ (RW) - * - * Channel length (number of bits per audio channel) - * 0: 16-bit wide - * 1: 32-bit wide - * The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. - * Note: For correct operation, this bit should be configured when the I2S is disabled. - */ -#define I2S_CFGR_CHSIZ_MASK (0x1U) -#define I2S_CFGR_CHSIZ_SHIFT (0U) -#define I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK) -#define I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT) - -/* Bitfield definition for register: MISC_CFGR */ -/* - * MCLK_GATEOFF (RW) - * - * Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - */ -#define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) -#define I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) - -/* - * MCLKOE (RW) - * - * Master clock output to pad enable - * 0: Master clock output is disabled - * 1: Master clock output is enabled - * Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_MISC_CFGR_MCLKOE_MASK (0x1U) -#define I2S_MISC_CFGR_MCLKOE_SHIFT (0U) -#define I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK) -#define I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT) - -/* Bitfield definition for register array: RXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_RXDSLOT_EN_MASK (0xFFFFU) -#define I2S_RXDSLOT_EN_SHIFT (0U) -#define I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK) -#define I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT) - -/* Bitfield definition for register array: TXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_TXDSLOT_EN_MASK (0xFFFFU) -#define I2S_TXDSLOT_EN_SHIFT (0U) -#define I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK) -#define I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT) - - - -/* RXD register group index macro definition */ -#define I2S_RXD_DATA0 (0UL) -#define I2S_RXD_DATA1 (1UL) -#define I2S_RXD_DATA2 (2UL) -#define I2S_RXD_DATA3 (3UL) - -/* TXD register group index macro definition */ -#define I2S_TXD_DATA0 (0UL) -#define I2S_TXD_DATA1 (1UL) -#define I2S_TXD_DATA2 (2UL) -#define I2S_TXD_DATA3 (3UL) - -/* RXDSLOT register group index macro definition */ -#define I2S_RXDSLOT_DATA0 (0UL) -#define I2S_RXDSLOT_DATA1 (1UL) -#define I2S_RXDSLOT_DATA2 (2UL) -#define I2S_RXDSLOT_DATA3 (3UL) - -/* TXDSLOT register group index macro definition */ -#define I2S_TXDSLOT_DATA0 (0UL) -#define I2S_TXDSLOT_DATA1 (1UL) -#define I2S_TXDSLOT_DATA2 (2UL) -#define I2S_TXDSLOT_DATA3 (3UL) - - -#endif /* HPM_I2S_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ioc_regs.h deleted file mode 100644 index de42be177c4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ioc_regs.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOC_H -#define HPM_IOC_H - -typedef struct { - struct { - __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ - __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[492]; -} IOC_Type; - - -/* Bitfield definition for register of struct array PAD: FUNC_CTL */ -/* - * LOOP_BACK (RW) - * - * force input on - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) - -/* - * ANALOG (RW) - * - * select analog pin in pad - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) -#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) -#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) -#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) - -/* - * ALT_SELECT (RW) - * - * alt select - * 0: ALT0 - * 1: ALT1 - * … - * 31:ALT31 - */ -#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) - -/* Bitfield definition for register of struct array PAD: PAD_CTL */ -/* - * MS (RW) - * - * pin voltage select, only available in high-speed IO - * 0: 3.3V - * 1: 1.8V - */ -#define IOC_PAD_PAD_CTL_MS_MASK (0x4000U) -#define IOC_PAD_PAD_CTL_MS_SHIFT (14U) -#define IOC_PAD_PAD_CTL_MS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_MS_SHIFT) & IOC_PAD_PAD_CTL_MS_MASK) -#define IOC_PAD_PAD_CTL_MS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_MS_MASK) >> IOC_PAD_PAD_CTL_MS_SHIFT) - -/* - * OD (RW) - * - * open drain - * 0: open drain disable - * 1: open drain enable - */ -#define IOC_PAD_PAD_CTL_OD_MASK (0x2000U) -#define IOC_PAD_PAD_CTL_OD_SHIFT (13U) -#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) -#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) - -/* - * SMT (RW) - * - * schmitt trigger enable, only available in high-speed IO - * 0: disable - * 1: enable - */ -#define IOC_PAD_PAD_CTL_SMT_MASK (0x1000U) -#define IOC_PAD_PAD_CTL_SMT_SHIFT (12U) -#define IOC_PAD_PAD_CTL_SMT_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SMT_SHIFT) & IOC_PAD_PAD_CTL_SMT_MASK) -#define IOC_PAD_PAD_CTL_SMT_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SMT_MASK) >> IOC_PAD_PAD_CTL_SMT_SHIFT) - -/* - * PS (RW) - * - * pull select - * 0: pull down - * 1: pull up - */ -#define IOC_PAD_PAD_CTL_PS_MASK (0x800U) -#define IOC_PAD_PAD_CTL_PS_SHIFT (11U) -#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) -#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) - -/* - * PE (RW) - * - * pull enable - * 0: pull disable - * 1: pull enable - */ -#define IOC_PAD_PAD_CTL_PE_MASK (0x10U) -#define IOC_PAD_PAD_CTL_PE_SHIFT (4U) -#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) -#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) - -/* - * DS (RW) - * - * drive strength - * for high-speed IO 3.3V: - * 000: 85.61Ohm - * 001: 61.2 Ohm - * 010: 42.88Ohm - * 011: 35.76Ohm - * 111: 30.67Ohm - * for high-speed IO 1.8V: - * 000: 84.07Ohm - * 001: 60.14Ohm - * 010: 42.15Ohm - * 011: 35.19Ohm - * 111: 30.2 Ohm - * for general IO: - * 00: 4mA - * 01: 8mA - * 11: 12mA - */ -#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) -#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) -#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) -#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) - - - -/* PAD register group index macro definition */ -#define IOC_PAD_PA00 (0UL) -#define IOC_PAD_PA01 (1UL) -#define IOC_PAD_PA02 (2UL) -#define IOC_PAD_PA03 (3UL) -#define IOC_PAD_PA04 (4UL) -#define IOC_PAD_PA05 (5UL) -#define IOC_PAD_PA06 (6UL) -#define IOC_PAD_PA07 (7UL) -#define IOC_PAD_PA08 (8UL) -#define IOC_PAD_PA09 (9UL) -#define IOC_PAD_PA10 (10UL) -#define IOC_PAD_PA11 (11UL) -#define IOC_PAD_PA12 (12UL) -#define IOC_PAD_PA13 (13UL) -#define IOC_PAD_PA14 (14UL) -#define IOC_PAD_PA15 (15UL) -#define IOC_PAD_PA16 (16UL) -#define IOC_PAD_PA17 (17UL) -#define IOC_PAD_PA18 (18UL) -#define IOC_PAD_PA19 (19UL) -#define IOC_PAD_PA20 (20UL) -#define IOC_PAD_PA21 (21UL) -#define IOC_PAD_PA22 (22UL) -#define IOC_PAD_PA23 (23UL) -#define IOC_PAD_PA24 (24UL) -#define IOC_PAD_PA25 (25UL) -#define IOC_PAD_PA26 (26UL) -#define IOC_PAD_PA27 (27UL) -#define IOC_PAD_PA28 (28UL) -#define IOC_PAD_PA29 (29UL) -#define IOC_PAD_PA30 (30UL) -#define IOC_PAD_PA31 (31UL) -#define IOC_PAD_PB00 (32UL) -#define IOC_PAD_PB01 (33UL) -#define IOC_PAD_PB02 (34UL) -#define IOC_PAD_PB03 (35UL) -#define IOC_PAD_PB04 (36UL) -#define IOC_PAD_PB05 (37UL) -#define IOC_PAD_PB06 (38UL) -#define IOC_PAD_PB07 (39UL) -#define IOC_PAD_PB08 (40UL) -#define IOC_PAD_PB09 (41UL) -#define IOC_PAD_PB10 (42UL) -#define IOC_PAD_PB11 (43UL) -#define IOC_PAD_PB12 (44UL) -#define IOC_PAD_PB13 (45UL) -#define IOC_PAD_PB14 (46UL) -#define IOC_PAD_PB15 (47UL) -#define IOC_PAD_PB16 (48UL) -#define IOC_PAD_PB17 (49UL) -#define IOC_PAD_PB18 (50UL) -#define IOC_PAD_PB19 (51UL) -#define IOC_PAD_PB20 (52UL) -#define IOC_PAD_PB21 (53UL) -#define IOC_PAD_PB22 (54UL) -#define IOC_PAD_PB23 (55UL) -#define IOC_PAD_PB24 (56UL) -#define IOC_PAD_PB25 (57UL) -#define IOC_PAD_PB26 (58UL) -#define IOC_PAD_PB27 (59UL) -#define IOC_PAD_PB28 (60UL) -#define IOC_PAD_PB29 (61UL) -#define IOC_PAD_PB30 (62UL) -#define IOC_PAD_PB31 (63UL) -#define IOC_PAD_PC00 (64UL) -#define IOC_PAD_PC01 (65UL) -#define IOC_PAD_PC02 (66UL) -#define IOC_PAD_PC03 (67UL) -#define IOC_PAD_PC04 (68UL) -#define IOC_PAD_PC05 (69UL) -#define IOC_PAD_PC06 (70UL) -#define IOC_PAD_PC07 (71UL) -#define IOC_PAD_PC08 (72UL) -#define IOC_PAD_PC09 (73UL) -#define IOC_PAD_PC10 (74UL) -#define IOC_PAD_PC11 (75UL) -#define IOC_PAD_PC12 (76UL) -#define IOC_PAD_PC13 (77UL) -#define IOC_PAD_PC14 (78UL) -#define IOC_PAD_PC15 (79UL) -#define IOC_PAD_PC16 (80UL) -#define IOC_PAD_PC17 (81UL) -#define IOC_PAD_PC18 (82UL) -#define IOC_PAD_PC19 (83UL) -#define IOC_PAD_PC20 (84UL) -#define IOC_PAD_PC21 (85UL) -#define IOC_PAD_PC22 (86UL) -#define IOC_PAD_PC23 (87UL) -#define IOC_PAD_PC24 (88UL) -#define IOC_PAD_PC25 (89UL) -#define IOC_PAD_PC26 (90UL) -#define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PC28 (92UL) -#define IOC_PAD_PC29 (93UL) -#define IOC_PAD_PC30 (94UL) -#define IOC_PAD_PC31 (95UL) -#define IOC_PAD_PD00 (96UL) -#define IOC_PAD_PD01 (97UL) -#define IOC_PAD_PD02 (98UL) -#define IOC_PAD_PD03 (99UL) -#define IOC_PAD_PD04 (100UL) -#define IOC_PAD_PD05 (101UL) -#define IOC_PAD_PD06 (102UL) -#define IOC_PAD_PD07 (103UL) -#define IOC_PAD_PD08 (104UL) -#define IOC_PAD_PD09 (105UL) -#define IOC_PAD_PD10 (106UL) -#define IOC_PAD_PD11 (107UL) -#define IOC_PAD_PD12 (108UL) -#define IOC_PAD_PD13 (109UL) -#define IOC_PAD_PD14 (110UL) -#define IOC_PAD_PD15 (111UL) -#define IOC_PAD_PD16 (112UL) -#define IOC_PAD_PD17 (113UL) -#define IOC_PAD_PD18 (114UL) -#define IOC_PAD_PD19 (115UL) -#define IOC_PAD_PD20 (116UL) -#define IOC_PAD_PD21 (117UL) -#define IOC_PAD_PD22 (118UL) -#define IOC_PAD_PD23 (119UL) -#define IOC_PAD_PD24 (120UL) -#define IOC_PAD_PD25 (121UL) -#define IOC_PAD_PD26 (122UL) -#define IOC_PAD_PD27 (123UL) -#define IOC_PAD_PD28 (124UL) -#define IOC_PAD_PD29 (125UL) -#define IOC_PAD_PD30 (126UL) -#define IOC_PAD_PD31 (127UL) -#define IOC_PAD_PE00 (128UL) -#define IOC_PAD_PE01 (129UL) -#define IOC_PAD_PE02 (130UL) -#define IOC_PAD_PE03 (131UL) -#define IOC_PAD_PE04 (132UL) -#define IOC_PAD_PE05 (133UL) -#define IOC_PAD_PE06 (134UL) -#define IOC_PAD_PE07 (135UL) -#define IOC_PAD_PE08 (136UL) -#define IOC_PAD_PE09 (137UL) -#define IOC_PAD_PE10 (138UL) -#define IOC_PAD_PE11 (139UL) -#define IOC_PAD_PE12 (140UL) -#define IOC_PAD_PE13 (141UL) -#define IOC_PAD_PE14 (142UL) -#define IOC_PAD_PE15 (143UL) -#define IOC_PAD_PE16 (144UL) -#define IOC_PAD_PE17 (145UL) -#define IOC_PAD_PE18 (146UL) -#define IOC_PAD_PE19 (147UL) -#define IOC_PAD_PE20 (148UL) -#define IOC_PAD_PE21 (149UL) -#define IOC_PAD_PE22 (150UL) -#define IOC_PAD_PE23 (151UL) -#define IOC_PAD_PE24 (152UL) -#define IOC_PAD_PE25 (153UL) -#define IOC_PAD_PE26 (154UL) -#define IOC_PAD_PE27 (155UL) -#define IOC_PAD_PE28 (156UL) -#define IOC_PAD_PE29 (157UL) -#define IOC_PAD_PE30 (158UL) -#define IOC_PAD_PE31 (159UL) -#define IOC_PAD_PF00 (160UL) -#define IOC_PAD_PF01 (161UL) -#define IOC_PAD_PF02 (162UL) -#define IOC_PAD_PF03 (163UL) -#define IOC_PAD_PF04 (164UL) -#define IOC_PAD_PF05 (165UL) -#define IOC_PAD_PF06 (166UL) -#define IOC_PAD_PF07 (167UL) -#define IOC_PAD_PF08 (168UL) -#define IOC_PAD_PF09 (169UL) -#define IOC_PAD_PF10 (170UL) -#define IOC_PAD_PX00 (416UL) -#define IOC_PAD_PX01 (417UL) -#define IOC_PAD_PX02 (418UL) -#define IOC_PAD_PX03 (419UL) -#define IOC_PAD_PX04 (420UL) -#define IOC_PAD_PX05 (421UL) -#define IOC_PAD_PX06 (422UL) -#define IOC_PAD_PX07 (423UL) -#define IOC_PAD_PX08 (424UL) -#define IOC_PAD_PX09 (425UL) -#define IOC_PAD_PX10 (426UL) -#define IOC_PAD_PX11 (427UL) -#define IOC_PAD_PY00 (448UL) -#define IOC_PAD_PY01 (449UL) -#define IOC_PAD_PY02 (450UL) -#define IOC_PAD_PY03 (451UL) -#define IOC_PAD_PY04 (452UL) -#define IOC_PAD_PY05 (453UL) -#define IOC_PAD_PY06 (454UL) -#define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PY08 (456UL) -#define IOC_PAD_PY09 (457UL) -#define IOC_PAD_PY10 (458UL) -#define IOC_PAD_PY11 (459UL) -#define IOC_PAD_PZ00 (480UL) -#define IOC_PAD_PZ01 (481UL) -#define IOC_PAD_PZ02 (482UL) -#define IOC_PAD_PZ03 (483UL) -#define IOC_PAD_PZ04 (484UL) -#define IOC_PAD_PZ05 (485UL) -#define IOC_PAD_PZ06 (486UL) -#define IOC_PAD_PZ07 (487UL) -#define IOC_PAD_PZ08 (488UL) -#define IOC_PAD_PZ09 (489UL) -#define IOC_PAD_PZ10 (490UL) -#define IOC_PAD_PZ11 (491UL) - - -#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_jpeg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_jpeg_regs.h deleted file mode 100644 index d29fe23e5c4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_jpeg_regs.h +++ /dev/null @@ -1,1095 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_JPEG_H -#define HPM_JPEG_H - -typedef struct { - __RW uint32_t INDMA_MISC; /* 0x0: In DMA Misc Control Register */ - __RW uint32_t INDMABASE; /* 0x4: In DMA Buf Address */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t INDMA_CTRL0; /* 0xC: In DMA Buf Control 0 Register */ - __RW uint32_t INDMA_CTRL1; /* 0x10: In DMA Buf Control 1 Register */ - __RW uint32_t INXT_CMD; /* 0x14: In DMA Next Command Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t OUTDMA_MISC; /* 0x20: Out DMA Misc Control Register */ - __RW uint32_t OUTDMABASE; /* 0x24: Out DMA Buf Address */ - __R uint8_t RESERVED2[4]; /* 0x28 - 0x2B: Reserved */ - __RW uint32_t OUTDMA_CTRL0; /* 0x2C: Out DMA Buf Control 0 Register */ - __RW uint32_t OUTDMA_CTRL1; /* 0x30: Out DMA Buf Control 1 Register */ - __RW uint32_t ONXT_CMD; /* 0x34: Out DMA Next Command Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t CFG; /* 0x40: Configuration Register */ - __RW uint32_t STAT; /* 0x44: Status Register */ - __RW uint32_t WIDTH; /* 0x48: Image width register */ - __RW uint32_t HEIGHT; /* 0x4C: Image height register */ - __RW uint32_t BUFADDR; /* 0x50: Buf Access Addr */ - __RW uint32_t BUFDATA; /* 0x54: Buf Access Data */ - __R uint32_t OUTDMACNT; /* 0x58: Out DMA Bytes Counter */ - __RW uint32_t CSC_COEF0; /* 0x5C: YUV2RGB coefficients Register 0 */ - __RW uint32_t CSC_COEF1; /* 0x60: YUV2RGB coefficients Register 1 */ - __RW uint32_t CSC_COEF2; /* 0x64: YUV2RGB coefficients Register 2 */ - __RW uint32_t RGB2YUV_COEF0; /* 0x68: RGB2YUV coefficients Register 0 */ - __RW uint32_t RGB2YUV_COEF1; /* 0x6C: RGB2YUV coefficients Register 1 */ - __RW uint32_t RGB2YUV_COEF2; /* 0x70: RGB2YUV coefficients Register 2 */ - __RW uint32_t RGB2YUV_COEF3; /* 0x74: RGB2YUV coefficients Register 3 */ - __RW uint32_t RGB2YUV_COEF4; /* 0x78: RGB2YUV coefficients Register 4 */ - __R uint8_t RESERVED4[8]; /* 0x7C - 0x83: Reserved */ - __RW uint32_t IMGREG1; /* 0x84: Image Control Register 1 */ - __RW uint32_t IMGREG2; /* 0x88: Image Control Register 2 */ - __RW uint32_t IMGREG3; /* 0x8C: Image Control Register 3 */ - __RW uint32_t IMGREG[4]; /* 0x90 - 0x9C: Image Control Register 40 */ -} JPEG_Type; - - -/* Bitfield definition for register: INDMA_MISC */ -/* - * ARQOS (RW) - * - * QoS for AXI read channel - */ -#define JPEG_INDMA_MISC_ARQOS_MASK (0x780000UL) -#define JPEG_INDMA_MISC_ARQOS_SHIFT (19U) -#define JPEG_INDMA_MISC_ARQOS_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_ARQOS_SHIFT) & JPEG_INDMA_MISC_ARQOS_MASK) -#define JPEG_INDMA_MISC_ARQOS_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_ARQOS_MASK) >> JPEG_INDMA_MISC_ARQOS_SHIFT) - -/* - * MAX_OT (RW) - * - * max_ot when input are RGB pixels. - * For 16 bits per pixel, it can be set as 4. - * For 32 bits per pixel, it will be set as 2. - */ -#define JPEG_INDMA_MISC_MAX_OT_MASK (0x78000UL) -#define JPEG_INDMA_MISC_MAX_OT_SHIFT (15U) -#define JPEG_INDMA_MISC_MAX_OT_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_MAX_OT_SHIFT) & JPEG_INDMA_MISC_MAX_OT_MASK) -#define JPEG_INDMA_MISC_MAX_OT_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_MAX_OT_MASK) >> JPEG_INDMA_MISC_MAX_OT_SHIFT) - -/* - * INB13_SWAP (RW) - * - * Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - */ -#define JPEG_INDMA_MISC_INB13_SWAP_MASK (0x4000U) -#define JPEG_INDMA_MISC_INB13_SWAP_SHIFT (14U) -#define JPEG_INDMA_MISC_INB13_SWAP_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INB13_SWAP_SHIFT) & JPEG_INDMA_MISC_INB13_SWAP_MASK) -#define JPEG_INDMA_MISC_INB13_SWAP_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INB13_SWAP_MASK) >> JPEG_INDMA_MISC_INB13_SWAP_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. - * 2'b00: no change {A3, A2, A1, A0} - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define JPEG_INDMA_MISC_PACK_DIR_MASK (0x3000U) -#define JPEG_INDMA_MISC_PACK_DIR_SHIFT (12U) -#define JPEG_INDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_PACK_DIR_SHIFT) & JPEG_INDMA_MISC_PACK_DIR_MASK) -#define JPEG_INDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_PACK_DIR_MASK) >> JPEG_INDMA_MISC_PACK_DIR_SHIFT) - -/* - * INDMA_RENEW (RW) - * - * Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - */ -#define JPEG_INDMA_MISC_INDMA_RENEW_MASK (0x800U) -#define JPEG_INDMA_MISC_INDMA_RENEW_SHIFT (11U) -#define JPEG_INDMA_MISC_INDMA_RENEW_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) -#define JPEG_INDMA_MISC_INDMA_RENEW_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) >> JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) - -/* - * NXT_IRQ_EN (RW) - * - * In DMA Next Interrupt Enable - */ -#define JPEG_INDMA_MISC_NXT_IRQ_EN_MASK (0x400U) -#define JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT (10U) -#define JPEG_INDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) - -/* - * IN_DMA_DONE_IRQ_EN (RW) - * - * In DMA Done enable - */ -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK (0x200U) -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT (9U) -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) - -/* - * AXI_ERR_IRQ_EN (RW) - * - * In DMA axi bus error inetrrupt enable - */ -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x100U) -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (8U) -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable for all interrupt sources of In DMA module - */ -#define JPEG_INDMA_MISC_IRQ_EN_MASK (0x80U) -#define JPEG_INDMA_MISC_IRQ_EN_SHIFT (7U) -#define JPEG_INDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IRQ_EN_SHIFT) - -/* - * IN_DMA_ID (RW) - * - * 0: Pixel (In) - * 1: ECS (In) - * 2: Qmem - * 3: HuffEnc - * 4: HuffMin - * 5: HuffBase - * 6: HuffSymb - */ -#define JPEG_INDMA_MISC_IN_DMA_ID_MASK (0x70U) -#define JPEG_INDMA_MISC_IN_DMA_ID_SHIFT (4U) -#define JPEG_INDMA_MISC_IN_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) -#define JPEG_INDMA_MISC_IN_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) >> JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) - -/* - * IN_DMA_REQ (RW) - * - * Asserted to request DMA. Automatically clear after DMA is done. - */ -#define JPEG_INDMA_MISC_IN_DMA_REQ_MASK (0x8U) -#define JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT (3U) -#define JPEG_INDMA_MISC_IN_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) -#define JPEG_INDMA_MISC_IN_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) >> JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) - -/* - * INDMA2D (RW) - * - * Asserted if In_DMA_ID=Pixel. - */ -#define JPEG_INDMA_MISC_INDMA2D_MASK (0x4U) -#define JPEG_INDMA_MISC_INDMA2D_SHIFT (2U) -#define JPEG_INDMA_MISC_INDMA2D_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA2D_SHIFT) & JPEG_INDMA_MISC_INDMA2D_MASK) -#define JPEG_INDMA_MISC_INDMA2D_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA2D_MASK) >> JPEG_INDMA_MISC_INDMA2D_SHIFT) - -/* Bitfield definition for register: INDMABASE */ -/* - * ADDR (RW) - * - * Y plane (or Encoded Bit Plane) - */ -#define JPEG_INDMABASE_ADDR_MASK (0xFFFFFFFFUL) -#define JPEG_INDMABASE_ADDR_SHIFT (0U) -#define JPEG_INDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_INDMABASE_ADDR_SHIFT) & JPEG_INDMABASE_ADDR_MASK) -#define JPEG_INDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_INDMABASE_ADDR_MASK) >> JPEG_INDMABASE_ADDR_SHIFT) - -/* Bitfield definition for register: INDMA_CTRL0 */ -/* - * TTLEN (RW) - * - * Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - */ -#define JPEG_INDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) -#define JPEG_INDMA_CTRL0_TTLEN_SHIFT (16U) -#define JPEG_INDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_TTLEN_SHIFT) & JPEG_INDMA_CTRL0_TTLEN_MASK) -#define JPEG_INDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_TTLEN_MASK) >> JPEG_INDMA_CTRL0_TTLEN_SHIFT) - -/* - * PITCH (RW) - * - * Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - */ -#define JPEG_INDMA_CTRL0_PITCH_MASK (0xFFFFU) -#define JPEG_INDMA_CTRL0_PITCH_SHIFT (0U) -#define JPEG_INDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_PITCH_SHIFT) & JPEG_INDMA_CTRL0_PITCH_MASK) -#define JPEG_INDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_PITCH_MASK) >> JPEG_INDMA_CTRL0_PITCH_SHIFT) - -/* Bitfield definition for register: INDMA_CTRL1 */ -/* - * ROWLEN (RW) - * - * Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - */ -#define JPEG_INDMA_CTRL1_ROWLEN_MASK (0xFFFFU) -#define JPEG_INDMA_CTRL1_ROWLEN_SHIFT (0U) -#define JPEG_INDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL1_ROWLEN_SHIFT) & JPEG_INDMA_CTRL1_ROWLEN_MASK) -#define JPEG_INDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL1_ROWLEN_MASK) >> JPEG_INDMA_CTRL1_ROWLEN_SHIFT) - -/* Bitfield definition for register: INXT_CMD */ -/* - * ADDR (RW) - * - * The address pointing to the next command - */ -#define JPEG_INXT_CMD_ADDR_MASK (0xFFFFFFFCUL) -#define JPEG_INXT_CMD_ADDR_SHIFT (2U) -#define JPEG_INXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_ADDR_SHIFT) & JPEG_INXT_CMD_ADDR_MASK) -#define JPEG_INXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_ADDR_MASK) >> JPEG_INXT_CMD_ADDR_SHIFT) - -/* - * OP_VALID (RW) - * - * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - */ -#define JPEG_INXT_CMD_OP_VALID_MASK (0x2U) -#define JPEG_INXT_CMD_OP_VALID_SHIFT (1U) -#define JPEG_INXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_OP_VALID_SHIFT) & JPEG_INXT_CMD_OP_VALID_MASK) -#define JPEG_INXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_OP_VALID_MASK) >> JPEG_INXT_CMD_OP_VALID_SHIFT) - -/* - * EN (RW) - * - * NXTCMD phase Enable Bit - */ -#define JPEG_INXT_CMD_EN_MASK (0x1U) -#define JPEG_INXT_CMD_EN_SHIFT (0U) -#define JPEG_INXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_EN_SHIFT) & JPEG_INXT_CMD_EN_MASK) -#define JPEG_INXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_EN_MASK) >> JPEG_INXT_CMD_EN_SHIFT) - -/* Bitfield definition for register: OUTDMA_MISC */ -/* - * AWQOS (RW) - * - */ -#define JPEG_OUTDMA_MISC_AWQOS_MASK (0x3C000UL) -#define JPEG_OUTDMA_MISC_AWQOS_SHIFT (14U) -#define JPEG_OUTDMA_MISC_AWQOS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AWQOS_SHIFT) & JPEG_OUTDMA_MISC_AWQOS_MASK) -#define JPEG_OUTDMA_MISC_AWQOS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AWQOS_MASK) >> JPEG_OUTDMA_MISC_AWQOS_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. - * 2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define JPEG_OUTDMA_MISC_PACK_DIR_MASK (0x3000U) -#define JPEG_OUTDMA_MISC_PACK_DIR_SHIFT (12U) -#define JPEG_OUTDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) -#define JPEG_OUTDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) >> JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) - -/* - * EN_OUTCNT (RW) - * - * Enable output counter (unit as bytes) - */ -#define JPEG_OUTDMA_MISC_EN_OUTCNT_MASK (0x800U) -#define JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT (11U) -#define JPEG_OUTDMA_MISC_EN_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) -#define JPEG_OUTDMA_MISC_EN_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) - -/* - * INI_OUTCNT (RW) - * - * Asserted to ini output counter - */ -#define JPEG_OUTDMA_MISC_INI_OUTCNT_MASK (0x400U) -#define JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT (10U) -#define JPEG_OUTDMA_MISC_INI_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) -#define JPEG_OUTDMA_MISC_INI_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) - -/* - * ADD_ODMA_ENDINGS (RW) - * - * Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - */ -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK (0x200U) -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT (9U) -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) >> JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) - -/* - * NXT_IRQ_EN (RW) - * - * Out DMA Next Interrupt Enable - */ -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK (0x100U) -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT (8U) -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) - -/* - * OUT_DMA_DONE_IRQ_EN (RW) - * - * Out DMA Done interrupt Enable - */ -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK (0x80U) -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT (7U) -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) - -/* - * AXI_ERR_IRQ_EN (RW) - * - * Out DMA axi bus error inetrrupt enable - */ -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x40U) -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (6U) -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable for all interrupt sources of Out DMA module - */ -#define JPEG_OUTDMA_MISC_IRQ_EN_MASK (0x20U) -#define JPEG_OUTDMA_MISC_IRQ_EN_SHIFT (5U) -#define JPEG_OUTDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) - -/* - * OUT_DMA_ID (RW) - * - * 0: Pixel (Out) - * 1: ECS (Out) - */ -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK (0x10U) -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT (4U) -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) - -/* - * OUT_DMA_REQ (RW) - * - * Asserted to enable Out DMA request - */ -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK (0x8U) -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT (3U) -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) - -/* - * OUTDMA2D (RW) - * - * Asserted if Out_DMA_ID==Pixel - */ -#define JPEG_OUTDMA_MISC_OUTDMA2D_MASK (0x4U) -#define JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT (2U) -#define JPEG_OUTDMA_MISC_OUTDMA2D_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) -#define JPEG_OUTDMA_MISC_OUTDMA2D_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) >> JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) - -/* Bitfield definition for register: OUTDMABASE */ -/* - * ADDR (RW) - * - * Y plane (or Encoded Bit Plane) - */ -#define JPEG_OUTDMABASE_ADDR_MASK (0xFFFFFFFFUL) -#define JPEG_OUTDMABASE_ADDR_SHIFT (0U) -#define JPEG_OUTDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_OUTDMABASE_ADDR_SHIFT) & JPEG_OUTDMABASE_ADDR_MASK) -#define JPEG_OUTDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_OUTDMABASE_ADDR_MASK) >> JPEG_OUTDMABASE_ADDR_SHIFT) - -/* Bitfield definition for register: OUTDMA_CTRL0 */ -/* - * TTLEN (RW) - * - * Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - */ -#define JPEG_OUTDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) -#define JPEG_OUTDMA_CTRL0_TTLEN_SHIFT (16U) -#define JPEG_OUTDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) -#define JPEG_OUTDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) >> JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) - -/* - * PITCH (RW) - * - * Pitch between the starting point of Rows when Out_DMA_ID==Pixel - */ -#define JPEG_OUTDMA_CTRL0_PITCH_MASK (0xFFFFU) -#define JPEG_OUTDMA_CTRL0_PITCH_SHIFT (0U) -#define JPEG_OUTDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_PITCH_SHIFT) & JPEG_OUTDMA_CTRL0_PITCH_MASK) -#define JPEG_OUTDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_PITCH_MASK) >> JPEG_OUTDMA_CTRL0_PITCH_SHIFT) - -/* Bitfield definition for register: OUTDMA_CTRL1 */ -/* - * ROWLEN (RW) - * - * Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - */ -#define JPEG_OUTDMA_CTRL1_ROWLEN_MASK (0xFFFFU) -#define JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT (0U) -#define JPEG_OUTDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) -#define JPEG_OUTDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) >> JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) - -/* Bitfield definition for register: ONXT_CMD */ -/* - * ADDR (RW) - * - * The address pointing to the next command - */ -#define JPEG_ONXT_CMD_ADDR_MASK (0xFFFFFFFCUL) -#define JPEG_ONXT_CMD_ADDR_SHIFT (2U) -#define JPEG_ONXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_ADDR_SHIFT) & JPEG_ONXT_CMD_ADDR_MASK) -#define JPEG_ONXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_ADDR_MASK) >> JPEG_ONXT_CMD_ADDR_SHIFT) - -/* - * OP_VALID (RW) - * - * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - */ -#define JPEG_ONXT_CMD_OP_VALID_MASK (0x2U) -#define JPEG_ONXT_CMD_OP_VALID_SHIFT (1U) -#define JPEG_ONXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_OP_VALID_SHIFT) & JPEG_ONXT_CMD_OP_VALID_MASK) -#define JPEG_ONXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_OP_VALID_MASK) >> JPEG_ONXT_CMD_OP_VALID_SHIFT) - -/* - * EN (RW) - * - * NXTCMD phase Enable Bit - */ -#define JPEG_ONXT_CMD_EN_MASK (0x1U) -#define JPEG_ONXT_CMD_EN_SHIFT (0U) -#define JPEG_ONXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_EN_SHIFT) & JPEG_ONXT_CMD_EN_MASK) -#define JPEG_ONXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_EN_MASK) >> JPEG_ONXT_CMD_EN_SHIFT) - -/* Bitfield definition for register: CFG */ -/* - * JD_UVSWAP (RW) - * - * Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - */ -#define JPEG_CFG_JD_UVSWAP_MASK (0x400000UL) -#define JPEG_CFG_JD_UVSWAP_SHIFT (22U) -#define JPEG_CFG_JD_UVSWAP_SET(x) (((uint32_t)(x) << JPEG_CFG_JD_UVSWAP_SHIFT) & JPEG_CFG_JD_UVSWAP_MASK) -#define JPEG_CFG_JD_UVSWAP_GET(x) (((uint32_t)(x) & JPEG_CFG_JD_UVSWAP_MASK) >> JPEG_CFG_JD_UVSWAP_SHIFT) - -/* - * CFG_IPATH_SEL (RW) - * - * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V - * 2'b01:ARGB8888, byte sequence as B,G,R,A - * 2'b10:RGB565, byte sequence as B,R - * 2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - */ -#define JPEG_CFG_CFG_IPATH_SEL_MASK (0x300000UL) -#define JPEG_CFG_CFG_IPATH_SEL_SHIFT (20U) -#define JPEG_CFG_CFG_IPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_IPATH_SEL_SHIFT) & JPEG_CFG_CFG_IPATH_SEL_MASK) -#define JPEG_CFG_CFG_IPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_IPATH_SEL_MASK) >> JPEG_CFG_CFG_IPATH_SEL_SHIFT) - -/* - * CODEC_OVER_IRQ_EN (RW) - * - * The jpg endec process done interrupt enable - */ -#define JPEG_CFG_CODEC_OVER_IRQ_EN_MASK (0x80000UL) -#define JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT (19U) -#define JPEG_CFG_CODEC_OVER_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) -#define JPEG_CFG_CODEC_OVER_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) >> JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) - -/* - * CODEC_RESTART_ERR_IRQ_EN (RW) - * - * The jpg endec restart error interrupt enable - */ -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK (0x40000UL) -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT (18U) -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) >> JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) - -/* - * MEM_DEBUG_CLK_SEL (RW) - * - * asserted to use APB clock, so that the memory contents could be read out through APB interface - */ -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK (0x20000UL) -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT (17U) -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) >> JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) - -/* - * CLKGATE (RW) - * - * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - */ -#define JPEG_CFG_CLKGATE_MASK (0x200U) -#define JPEG_CFG_CLKGATE_SHIFT (9U) -#define JPEG_CFG_CLKGATE_SET(x) (((uint32_t)(x) << JPEG_CFG_CLKGATE_SHIFT) & JPEG_CFG_CLKGATE_MASK) -#define JPEG_CFG_CLKGATE_GET(x) (((uint32_t)(x) & JPEG_CFG_CLKGATE_MASK) >> JPEG_CFG_CLKGATE_SHIFT) - -/* - * CFG_OPATH_SEL (RW) - * - * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V - * 2'b01:ARGB8888, byte sequence as B,G,R,A - * 2'b10:RGB565, byte sequence as R,B - * 2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - */ -#define JPEG_CFG_CFG_OPATH_SEL_MASK (0x180U) -#define JPEG_CFG_CFG_OPATH_SEL_SHIFT (7U) -#define JPEG_CFG_CFG_OPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_OPATH_SEL_SHIFT) & JPEG_CFG_CFG_OPATH_SEL_MASK) -#define JPEG_CFG_CFG_OPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_OPATH_SEL_MASK) >> JPEG_CFG_CFG_OPATH_SEL_SHIFT) - -/* - * JDATA_FORMAT (RW) - * - * 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU - * 3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU - * 3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU - * 3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU - * 3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU - * Others: Undefined - */ -#define JPEG_CFG_JDATA_FORMAT_MASK (0x70U) -#define JPEG_CFG_JDATA_FORMAT_SHIFT (4U) -#define JPEG_CFG_JDATA_FORMAT_SET(x) (((uint32_t)(x) << JPEG_CFG_JDATA_FORMAT_SHIFT) & JPEG_CFG_JDATA_FORMAT_MASK) -#define JPEG_CFG_JDATA_FORMAT_GET(x) (((uint32_t)(x) & JPEG_CFG_JDATA_FORMAT_MASK) >> JPEG_CFG_JDATA_FORMAT_SHIFT) - -/* - * JPEG_SFTRST (RW) - * - * Software Reset - */ -#define JPEG_CFG_JPEG_SFTRST_MASK (0x8U) -#define JPEG_CFG_JPEG_SFTRST_SHIFT (3U) -#define JPEG_CFG_JPEG_SFTRST_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_SFTRST_SHIFT) & JPEG_CFG_JPEG_SFTRST_MASK) -#define JPEG_CFG_JPEG_SFTRST_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_SFTRST_MASK) >> JPEG_CFG_JPEG_SFTRST_SHIFT) - -/* - * START (RW) - * - * Asserted if to start a new encoder/decoder conversion. - * It will at first stop the inner JPEG module, then reset it, and then re-run it. - * It is a different mode from DMA phase mode. - * It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. - * Auto clear. - */ -#define JPEG_CFG_START_MASK (0x4U) -#define JPEG_CFG_START_SHIFT (2U) -#define JPEG_CFG_START_SET(x) (((uint32_t)(x) << JPEG_CFG_START_SHIFT) & JPEG_CFG_START_MASK) -#define JPEG_CFG_START_GET(x) (((uint32_t)(x) & JPEG_CFG_START_MASK) >> JPEG_CFG_START_SHIFT) - -/* - * MODE (RW) - * - * 1: decoder, 0:encoder - */ -#define JPEG_CFG_MODE_MASK (0x2U) -#define JPEG_CFG_MODE_SHIFT (1U) -#define JPEG_CFG_MODE_SET(x) (((uint32_t)(x) << JPEG_CFG_MODE_SHIFT) & JPEG_CFG_MODE_MASK) -#define JPEG_CFG_MODE_GET(x) (((uint32_t)(x) & JPEG_CFG_MODE_MASK) >> JPEG_CFG_MODE_SHIFT) - -/* - * JPEG_EN (RW) - * - * 1b - Enabled - */ -#define JPEG_CFG_JPEG_EN_MASK (0x1U) -#define JPEG_CFG_JPEG_EN_SHIFT (0U) -#define JPEG_CFG_JPEG_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_EN_SHIFT) & JPEG_CFG_JPEG_EN_MASK) -#define JPEG_CFG_JPEG_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_EN_MASK) >> JPEG_CFG_JPEG_EN_SHIFT) - -/* Bitfield definition for register: STAT */ -/* - * BUSY (RO) - * - * When 1 means that the module is busy doing conversion and data transfer. - */ -#define JPEG_STAT_BUSY_MASK (0x80000000UL) -#define JPEG_STAT_BUSY_SHIFT (31U) -#define JPEG_STAT_BUSY_GET(x) (((uint32_t)(x) & JPEG_STAT_BUSY_MASK) >> JPEG_STAT_BUSY_SHIFT) - -/* - * AXI_ERR_ID (RO) - * - * the axi err id - */ -#define JPEG_STAT_AXI_ERR_ID_MASK (0x3C00U) -#define JPEG_STAT_AXI_ERR_ID_SHIFT (10U) -#define JPEG_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_ID_MASK) >> JPEG_STAT_AXI_ERR_ID_SHIFT) - -/* - * AXI_READ_ERR (RO) - * - * in-dma axi bus error - */ -#define JPEG_STAT_AXI_READ_ERR_MASK (0x200U) -#define JPEG_STAT_AXI_READ_ERR_SHIFT (9U) -#define JPEG_STAT_AXI_READ_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_READ_ERR_MASK) >> JPEG_STAT_AXI_READ_ERR_SHIFT) - -/* - * AXI_WRITE_ERR (RO) - * - * out-dma axi bus error - */ -#define JPEG_STAT_AXI_WRITE_ERR_MASK (0x100U) -#define JPEG_STAT_AXI_WRITE_ERR_SHIFT (8U) -#define JPEG_STAT_AXI_WRITE_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_WRITE_ERR_MASK) >> JPEG_STAT_AXI_WRITE_ERR_SHIFT) - -/* - * AXI_ERR (W1C) - * - * axi bus error - */ -#define JPEG_STAT_AXI_ERR_MASK (0x80U) -#define JPEG_STAT_AXI_ERR_SHIFT (7U) -#define JPEG_STAT_AXI_ERR_SET(x) (((uint32_t)(x) << JPEG_STAT_AXI_ERR_SHIFT) & JPEG_STAT_AXI_ERR_MASK) -#define JPEG_STAT_AXI_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_MASK) >> JPEG_STAT_AXI_ERR_SHIFT) - -/* - * ONXT_IRQ (W1C) - * - * OutDMA next interrupt - */ -#define JPEG_STAT_ONXT_IRQ_MASK (0x40U) -#define JPEG_STAT_ONXT_IRQ_SHIFT (6U) -#define JPEG_STAT_ONXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_ONXT_IRQ_SHIFT) & JPEG_STAT_ONXT_IRQ_MASK) -#define JPEG_STAT_ONXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_ONXT_IRQ_MASK) >> JPEG_STAT_ONXT_IRQ_SHIFT) - -/* - * INXT_IRQ (W1C) - * - * InDMA next interrupt - */ -#define JPEG_STAT_INXT_IRQ_MASK (0x20U) -#define JPEG_STAT_INXT_IRQ_SHIFT (5U) -#define JPEG_STAT_INXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_INXT_IRQ_SHIFT) & JPEG_STAT_INXT_IRQ_MASK) -#define JPEG_STAT_INXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_INXT_IRQ_MASK) >> JPEG_STAT_INXT_IRQ_SHIFT) - -/* - * OUT_DMA_TRANSFER_DONE (W1C) - * - * OutDMA process done - */ -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK (0x10U) -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT (4U) -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) - -/* - * IN_DMA_TRANSFER_DONE (W1C) - * - * InDMA process done - */ -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK (0x8U) -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT (3U) -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) - -/* - * CODEC_OVER (W1C) - * - * Coding or decoding process is over. DMA is not included. - * The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - */ -#define JPEG_STAT_CODEC_OVER_MASK (0x4U) -#define JPEG_STAT_CODEC_OVER_SHIFT (2U) -#define JPEG_STAT_CODEC_OVER_SET(x) (((uint32_t)(x) << JPEG_STAT_CODEC_OVER_SHIFT) & JPEG_STAT_CODEC_OVER_MASK) -#define JPEG_STAT_CODEC_OVER_GET(x) (((uint32_t)(x) & JPEG_STAT_CODEC_OVER_MASK) >> JPEG_STAT_CODEC_OVER_SHIFT) - -/* - * RESTART_MARKER_ERROR (W1C) - * - * codec restart marker error interrupt - */ -#define JPEG_STAT_RESTART_MARKER_ERROR_MASK (0x2U) -#define JPEG_STAT_RESTART_MARKER_ERROR_SHIFT (1U) -#define JPEG_STAT_RESTART_MARKER_ERROR_SET(x) (((uint32_t)(x) << JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) -#define JPEG_STAT_RESTART_MARKER_ERROR_GET(x) (((uint32_t)(x) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) >> JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) - -/* Bitfield definition for register: WIDTH */ -/* - * IMG (RW) - * - * Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - */ -#define JPEG_WIDTH_IMG_MASK (0xFFFFU) -#define JPEG_WIDTH_IMG_SHIFT (0U) -#define JPEG_WIDTH_IMG_SET(x) (((uint32_t)(x) << JPEG_WIDTH_IMG_SHIFT) & JPEG_WIDTH_IMG_MASK) -#define JPEG_WIDTH_IMG_GET(x) (((uint32_t)(x) & JPEG_WIDTH_IMG_MASK) >> JPEG_WIDTH_IMG_SHIFT) - -/* Bitfield definition for register: HEIGHT */ -/* - * IMG (RW) - * - * Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - */ -#define JPEG_HEIGHT_IMG_MASK (0xFFFFU) -#define JPEG_HEIGHT_IMG_SHIFT (0U) -#define JPEG_HEIGHT_IMG_SET(x) (((uint32_t)(x) << JPEG_HEIGHT_IMG_SHIFT) & JPEG_HEIGHT_IMG_MASK) -#define JPEG_HEIGHT_IMG_GET(x) (((uint32_t)(x) & JPEG_HEIGHT_IMG_MASK) >> JPEG_HEIGHT_IMG_SHIFT) - -/* Bitfield definition for register: BUFADDR */ -/* - * ADDR (RW) - * - * ADDR[31:28] denotes the buffer type: - * 0x2: Qmem - * 0x3: HuffEnc - * 0x4: HuffMin - * 0x5: HuffBase - * 0x6: HuffSymb - * ADDR[27:0] is the address inside the buffer - */ -#define JPEG_BUFADDR_ADDR_MASK (0xFFFFFFFFUL) -#define JPEG_BUFADDR_ADDR_SHIFT (0U) -#define JPEG_BUFADDR_ADDR_SET(x) (((uint32_t)(x) << JPEG_BUFADDR_ADDR_SHIFT) & JPEG_BUFADDR_ADDR_MASK) -#define JPEG_BUFADDR_ADDR_GET(x) (((uint32_t)(x) & JPEG_BUFADDR_ADDR_MASK) >> JPEG_BUFADDR_ADDR_SHIFT) - -/* Bitfield definition for register: BUFDATA */ -/* - * DATA (RW) - * - * The data write-to/read-from buffer. - * The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - */ -#define JPEG_BUFDATA_DATA_MASK (0xFFFFFFFFUL) -#define JPEG_BUFDATA_DATA_SHIFT (0U) -#define JPEG_BUFDATA_DATA_SET(x) (((uint32_t)(x) << JPEG_BUFDATA_DATA_SHIFT) & JPEG_BUFDATA_DATA_MASK) -#define JPEG_BUFDATA_DATA_GET(x) (((uint32_t)(x) & JPEG_BUFDATA_DATA_MASK) >> JPEG_BUFDATA_DATA_SHIFT) - -/* Bitfield definition for register: OUTDMACNT */ -/* - * VAL (RO) - * - * The out DMA counter - */ -#define JPEG_OUTDMACNT_VAL_MASK (0xFFFFFFFFUL) -#define JPEG_OUTDMACNT_VAL_SHIFT (0U) -#define JPEG_OUTDMACNT_VAL_GET(x) (((uint32_t)(x) & JPEG_OUTDMACNT_VAL_MASK) >> JPEG_OUTDMACNT_VAL_SHIFT) - -/* Bitfield definition for register: CSC_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * This bit changes the behavior when performing U/V converting. - * 0b - Converting YUV to RGB data - * 1b - Converting YCbCr to RGB data - */ -#define JPEG_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define JPEG_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -#define JPEG_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) -#define JPEG_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) >> JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Enable the CSC unit. - * 0b - The CSC is bypassed - * 1b - The CSC is enabled - */ -#define JPEG_CSC_COEF0_ENABLE_MASK (0x40000000UL) -#define JPEG_CSC_COEF0_ENABLE_SHIFT (30U) -#define JPEG_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_ENABLE_SHIFT) & JPEG_CSC_COEF0_ENABLE_MASK) -#define JPEG_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_ENABLE_MASK) >> JPEG_CSC_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define JPEG_CSC_COEF0_C0_MASK (0x1FFC0000UL) -#define JPEG_CSC_COEF0_C0_SHIFT (18U) -#define JPEG_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_C0_SHIFT) & JPEG_CSC_COEF0_C0_MASK) -#define JPEG_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_C0_MASK) >> JPEG_CSC_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define JPEG_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define JPEG_CSC_COEF0_UV_OFFSET_SHIFT (9U) -#define JPEG_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_UV_OFFSET_SHIFT) & JPEG_CSC_COEF0_UV_OFFSET_MASK) -#define JPEG_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_UV_OFFSET_MASK) >> JPEG_CSC_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define JPEG_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) -#define JPEG_CSC_COEF0_Y_OFFSET_SHIFT (0U) -#define JPEG_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_Y_OFFSET_SHIFT) & JPEG_CSC_COEF0_Y_OFFSET_MASK) -#define JPEG_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_Y_OFFSET_MASK) >> JPEG_CSC_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: CSC_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define JPEG_CSC_COEF1_C1_MASK (0x7FF0000UL) -#define JPEG_CSC_COEF1_C1_SHIFT (16U) -#define JPEG_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C1_SHIFT) & JPEG_CSC_COEF1_C1_MASK) -#define JPEG_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C1_MASK) >> JPEG_CSC_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define JPEG_CSC_COEF1_C4_MASK (0x7FFU) -#define JPEG_CSC_COEF1_C4_SHIFT (0U) -#define JPEG_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C4_SHIFT) & JPEG_CSC_COEF1_C4_MASK) -#define JPEG_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C4_MASK) >> JPEG_CSC_COEF1_C4_SHIFT) - -/* Bitfield definition for register: CSC_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define JPEG_CSC_COEF2_C2_MASK (0x7FF0000UL) -#define JPEG_CSC_COEF2_C2_SHIFT (16U) -#define JPEG_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C2_SHIFT) & JPEG_CSC_COEF2_C2_MASK) -#define JPEG_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C2_MASK) >> JPEG_CSC_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define JPEG_CSC_COEF2_C3_MASK (0x7FFU) -#define JPEG_CSC_COEF2_C3_SHIFT (0U) -#define JPEG_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C3_SHIFT) & JPEG_CSC_COEF2_C3_MASK) -#define JPEG_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C3_MASK) >> JPEG_CSC_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * Asserted to use YCrCb mode. Must be assigned as 1. - */ -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Asserted to enable this RGB2YCbCr CSC stage - */ -#define JPEG_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) -#define JPEG_RGB2YUV_COEF0_ENABLE_SHIFT (30U) -#define JPEG_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) -#define JPEG_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) >> JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * CSC parameters C0 - */ -#define JPEG_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) -#define JPEG_RGB2YUV_COEF0_C0_SHIFT (18U) -#define JPEG_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_C0_SHIFT) & JPEG_RGB2YUV_COEF0_C0_MASK) -#define JPEG_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_C0_MASK) >> JPEG_RGB2YUV_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * CSC parameters UV_OFFSET - */ -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * CSC parameters Y_OFFSET - */ -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF1 */ -/* - * C1 (RW) - * - * CSC parameters C1 - */ -#define JPEG_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF1_C1_SHIFT (16U) -#define JPEG_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C1_SHIFT) & JPEG_RGB2YUV_COEF1_C1_MASK) -#define JPEG_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C1_MASK) >> JPEG_RGB2YUV_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * CSC parameters C4 - */ -#define JPEG_RGB2YUV_COEF1_C4_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF1_C4_SHIFT (0U) -#define JPEG_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C4_SHIFT) & JPEG_RGB2YUV_COEF1_C4_MASK) -#define JPEG_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C4_MASK) >> JPEG_RGB2YUV_COEF1_C4_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF2 */ -/* - * C2 (RW) - * - * CSC parameters C2 - */ -#define JPEG_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF2_C2_SHIFT (16U) -#define JPEG_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C2_SHIFT) & JPEG_RGB2YUV_COEF2_C2_MASK) -#define JPEG_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C2_MASK) >> JPEG_RGB2YUV_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * CSC parameters C3 - */ -#define JPEG_RGB2YUV_COEF2_C3_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF2_C3_SHIFT (0U) -#define JPEG_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C3_SHIFT) & JPEG_RGB2YUV_COEF2_C3_MASK) -#define JPEG_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C3_MASK) >> JPEG_RGB2YUV_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF3 */ -/* - * C6 (RW) - * - * CSC parameters C6 - */ -#define JPEG_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF3_C6_SHIFT (16U) -#define JPEG_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C6_SHIFT) & JPEG_RGB2YUV_COEF3_C6_MASK) -#define JPEG_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C6_MASK) >> JPEG_RGB2YUV_COEF3_C6_SHIFT) - -/* - * C5 (RW) - * - * CSC parameters C5 - */ -#define JPEG_RGB2YUV_COEF3_C5_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF3_C5_SHIFT (0U) -#define JPEG_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C5_SHIFT) & JPEG_RGB2YUV_COEF3_C5_MASK) -#define JPEG_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C5_MASK) >> JPEG_RGB2YUV_COEF3_C5_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF4 */ -/* - * C8 (RW) - * - * CSC parameters C8 - */ -#define JPEG_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF4_C8_SHIFT (16U) -#define JPEG_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C8_SHIFT) & JPEG_RGB2YUV_COEF4_C8_MASK) -#define JPEG_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C8_MASK) >> JPEG_RGB2YUV_COEF4_C8_SHIFT) - -/* - * C7 (RW) - * - * CSC parameters C7 - */ -#define JPEG_RGB2YUV_COEF4_C7_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF4_C7_SHIFT (0U) -#define JPEG_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C7_SHIFT) & JPEG_RGB2YUV_COEF4_C7_MASK) -#define JPEG_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C7_MASK) >> JPEG_RGB2YUV_COEF4_C7_SHIFT) - -/* Bitfield definition for register: IMGREG1 */ -/* - * RE (RW) - * - * Encoder Use only. - * Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - */ -#define JPEG_IMGREG1_RE_MASK (0x4U) -#define JPEG_IMGREG1_RE_SHIFT (2U) -#define JPEG_IMGREG1_RE_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_RE_SHIFT) & JPEG_IMGREG1_RE_MASK) -#define JPEG_IMGREG1_RE_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_RE_MASK) >> JPEG_IMGREG1_RE_SHIFT) - -/* - * NCOL (RW) - * - * Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - */ -#define JPEG_IMGREG1_NCOL_MASK (0x3U) -#define JPEG_IMGREG1_NCOL_SHIFT (0U) -#define JPEG_IMGREG1_NCOL_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_NCOL_SHIFT) & JPEG_IMGREG1_NCOL_MASK) -#define JPEG_IMGREG1_NCOL_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_NCOL_MASK) >> JPEG_IMGREG1_NCOL_SHIFT) - -/* Bitfield definition for register: IMGREG2 */ -/* - * NMCU (RW) - * - * Encoder Use only. - * The number of NMCU to be generated in encoder mode - */ -#define JPEG_IMGREG2_NMCU_MASK (0x3FFFFFFUL) -#define JPEG_IMGREG2_NMCU_SHIFT (0U) -#define JPEG_IMGREG2_NMCU_SET(x) (((uint32_t)(x) << JPEG_IMGREG2_NMCU_SHIFT) & JPEG_IMGREG2_NMCU_MASK) -#define JPEG_IMGREG2_NMCU_GET(x) (((uint32_t)(x) & JPEG_IMGREG2_NMCU_MASK) >> JPEG_IMGREG2_NMCU_SHIFT) - -/* Bitfield definition for register: IMGREG3 */ -/* - * NRST (RW) - * - * Encoder use only. - * It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - */ -#define JPEG_IMGREG3_NRST_MASK (0xFFFFU) -#define JPEG_IMGREG3_NRST_SHIFT (0U) -#define JPEG_IMGREG3_NRST_SET(x) (((uint32_t)(x) << JPEG_IMGREG3_NRST_SHIFT) & JPEG_IMGREG3_NRST_MASK) -#define JPEG_IMGREG3_NRST_GET(x) (((uint32_t)(x) & JPEG_IMGREG3_NRST_MASK) >> JPEG_IMGREG3_NRST_SHIFT) - -/* Bitfield definition for register array: IMGREG */ -/* - * NBLOCK (RW) - * - * Encoder use only. - * The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - */ -#define JPEG_IMGREG_NBLOCK_MASK (0xF0U) -#define JPEG_IMGREG_NBLOCK_SHIFT (4U) -#define JPEG_IMGREG_NBLOCK_SET(x) (((uint32_t)(x) << JPEG_IMGREG_NBLOCK_SHIFT) & JPEG_IMGREG_NBLOCK_MASK) -#define JPEG_IMGREG_NBLOCK_GET(x) (((uint32_t)(x) & JPEG_IMGREG_NBLOCK_MASK) >> JPEG_IMGREG_NBLOCK_SHIFT) - -/* - * QT (RW) - * - * Encoder use only. - * The selection of the quantization table. - */ -#define JPEG_IMGREG_QT_MASK (0xCU) -#define JPEG_IMGREG_QT_SHIFT (2U) -#define JPEG_IMGREG_QT_SET(x) (((uint32_t)(x) << JPEG_IMGREG_QT_SHIFT) & JPEG_IMGREG_QT_MASK) -#define JPEG_IMGREG_QT_GET(x) (((uint32_t)(x) & JPEG_IMGREG_QT_MASK) >> JPEG_IMGREG_QT_SHIFT) - -/* - * HA (RW) - * - * Encoder use only. - * The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - */ -#define JPEG_IMGREG_HA_MASK (0x2U) -#define JPEG_IMGREG_HA_SHIFT (1U) -#define JPEG_IMGREG_HA_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HA_SHIFT) & JPEG_IMGREG_HA_MASK) -#define JPEG_IMGREG_HA_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HA_MASK) >> JPEG_IMGREG_HA_SHIFT) - -/* - * HD (RW) - * - * Encoder use only. - * The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - */ -#define JPEG_IMGREG_HD_MASK (0x1U) -#define JPEG_IMGREG_HD_SHIFT (0U) -#define JPEG_IMGREG_HD_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HD_SHIFT) & JPEG_IMGREG_HD_MASK) -#define JPEG_IMGREG_HD_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HD_MASK) >> JPEG_IMGREG_HD_SHIFT) - - - -/* IMGREG register group index macro definition */ -#define JPEG_IMGREG_REG40 (0UL) -#define JPEG_IMGREG_REG41 (1UL) -#define JPEG_IMGREG_REG42 (2UL) -#define JPEG_IMGREG_REG43 (3UL) - - -#endif /* HPM_JPEG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_keym_regs.h deleted file mode 100644 index 0d97ce1ecb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_keym_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_KEYM_H -#define HPM_KEYM_H - -typedef struct { - __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ - __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ - __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ - __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ - __RW uint32_t RNG; /* 0x48: Random number interface behavior */ - __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ -} KEYM_Type; - - -/* Bitfield definition for register array: SOFTMKEY */ -/* - * KEY (RW) - * - * software symmetric key - * key will be scambled to 4 variants for software to use, and replicable on same chip. - * scramble keys are chip different, and not replicable on different chip - * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - */ -#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTMKEY_KEY_SHIFT (0U) -#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) -#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) - -/* Bitfield definition for register array: SOFTPKEY */ -/* - * KEY (RW) - * - * software asymmetric key - * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. - * This key os read once, sencondary read will read out 0 - */ -#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTPKEY_KEY_SHIFT (0U) -#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) -#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) - -/* Bitfield definition for register: SEC_KEY_CTL */ -/* - * LOCK_SEC_CTL (RW) - * - * block secure state key setting being changed - */ -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use origin value in software symmetric key - * 1: use scramble version of software symmetric key - */ -#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use alnertave scramble of fuse symmetric key - */ -#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: NSC_KEY_CTL */ -/* - * LOCK_NSC_CTL (RW) - * - * block non-secure state key setting being changed - */ -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use origin value in fuse symmetric key - */ -#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * non-secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: RNG */ -/* - * BLOCK_RNG_XOR (RW) - * - * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset - * 0: RNG_XOR can be changed by software - * 1: RNG_XOR ignore software change from software - */ -#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) -#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) -#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) -#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) - -/* - * RNG_XOR (RW) - * - * control how SFK is accepted from random number generator - * 0: SFK value replaced by random number input - * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - */ -#define KEYM_RNG_RNG_XOR_MASK (0x1U) -#define KEYM_RNG_RNG_XOR_SHIFT (0U) -#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) -#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) - -/* Bitfield definition for register: READ_CONTROL */ -/* - * BLOCK_PK_READ (RW) - * - * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) - -/* - * BLOCK_SMK_READ (RW) - * - * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) - - - -/* SOFTMKEY register group index macro definition */ -#define KEYM_SOFTMKEY_SFK0 (0UL) -#define KEYM_SOFTMKEY_SFK1 (1UL) -#define KEYM_SOFTMKEY_SFK2 (2UL) -#define KEYM_SOFTMKEY_SFK3 (3UL) -#define KEYM_SOFTMKEY_SFK4 (4UL) -#define KEYM_SOFTMKEY_SFK5 (5UL) -#define KEYM_SOFTMKEY_SFK6 (6UL) -#define KEYM_SOFTMKEY_SFK7 (7UL) - -/* SOFTPKEY register group index macro definition */ -#define KEYM_SOFTPKEY_SPK0 (0UL) -#define KEYM_SOFTPKEY_SPK1 (1UL) -#define KEYM_SOFTPKEY_SPK2 (2UL) -#define KEYM_SOFTPKEY_SPK3 (3UL) -#define KEYM_SOFTPKEY_SPK4 (4UL) -#define KEYM_SOFTPKEY_SPK5 (5UL) -#define KEYM_SOFTPKEY_SPK6 (6UL) -#define KEYM_SOFTPKEY_SPK7 (7UL) - - -#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_lcdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_lcdc_regs.h deleted file mode 100644 index 1353a80f260..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_lcdc_regs.h +++ /dev/null @@ -1,835 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LCDC_H -#define HPM_LCDC_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t BGND_CL; /* 0x4: Background Color Register */ - __RW uint32_t DISP_WN_SIZE; /* 0x8: Display Window Size Register */ - __RW uint32_t HSYNC_PARA; /* 0xC: HSYNC Config Register */ - __RW uint32_t VSYNC_PARA; /* 0x10: VSYNC Config Register */ - __W uint32_t DMA_ST; /* 0x14: DMA Status Register */ - __W uint32_t ST; /* 0x18: Status Register */ - __RW uint32_t INT_EN; /* 0x1C: Interrupt Enable Register */ - __RW uint32_t TXFIFO; /* 0x20: TX FIFO Register */ - __R uint8_t RESERVED0[476]; /* 0x24 - 0x1FF: Reserved */ - struct { - __RW uint32_t LAYCTRL; /* 0x200: Layer Control Register */ - __RW uint32_t ALPHAS; /* 0x204: Layer Alpha Register */ - __RW uint32_t LAYSIZE; /* 0x208: Layer Size Register */ - __RW uint32_t LAYPOS; /* 0x20C: Layer Position Register */ - __RW uint32_t START0; /* 0x210: Layer Buffer Pointer Register */ - __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ - __RW uint32_t LINECFG; /* 0x218: Layer Bus Config Register */ - __RW uint32_t BG_CL; /* 0x21C: Layer Background Color Register */ - __RW uint32_t CSC_COEF0; /* 0x220: Layer Color Space Conversion Config Register 0 */ - __RW uint32_t CSC_COEF1; /* 0x224: Layer Color Space Conversion Config Register 1 */ - __RW uint32_t CSC_COEF2; /* 0x228: Layer Color Space Conversion Config Register 2 */ - __R uint8_t RESERVED1[20]; /* 0x22C - 0x23F: Reserved */ - } LAYER[8]; - __RW uint32_t CLUT_LOAD; /* 0x400: Clut Load Control Register */ -} LCDC_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SW_RST (RW) - * - * Software reset, high active. When write 1 ,all internal logical will be reset. - * 0b - No action - * 1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - */ -#define LCDC_CTRL_SW_RST_MASK (0x80000000UL) -#define LCDC_CTRL_SW_RST_SHIFT (31U) -#define LCDC_CTRL_SW_RST_SET(x) (((uint32_t)(x) << LCDC_CTRL_SW_RST_SHIFT) & LCDC_CTRL_SW_RST_MASK) -#define LCDC_CTRL_SW_RST_GET(x) (((uint32_t)(x) & LCDC_CTRL_SW_RST_MASK) >> LCDC_CTRL_SW_RST_SHIFT) - -/* - * DISP_ON (RW) - * - * Display panel On/Off mode. - * 0b - Display Off. - * 1b - Display On. - * Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. - * So a good procedure to stop and turn on the display is: - * 1) clr VS_BLANK status - * 2) assert software reset - * 3) de-assert software reset - * 4) set display off - * 5) check VS_BLANK status until it is asserted, - * 6)reset the module, change settings - * 7) set display on - */ -#define LCDC_CTRL_DISP_ON_MASK (0x40000000UL) -#define LCDC_CTRL_DISP_ON_SHIFT (30U) -#define LCDC_CTRL_DISP_ON_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_ON_SHIFT) & LCDC_CTRL_DISP_ON_MASK) -#define LCDC_CTRL_DISP_ON_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_ON_MASK) >> LCDC_CTRL_DISP_ON_SHIFT) - -/* - * LINE_PATTERN (RW) - * - * LCDIF line output order. - * 000b - RGB. - * 001b - RBG. - * 010b - GBR. - * 011b - GRB. - * 100b - BRG. - * 101b - BGR. - */ -#define LCDC_CTRL_LINE_PATTERN_MASK (0x38000000UL) -#define LCDC_CTRL_LINE_PATTERN_SHIFT (27U) -#define LCDC_CTRL_LINE_PATTERN_SET(x) (((uint32_t)(x) << LCDC_CTRL_LINE_PATTERN_SHIFT) & LCDC_CTRL_LINE_PATTERN_MASK) -#define LCDC_CTRL_LINE_PATTERN_GET(x) (((uint32_t)(x) & LCDC_CTRL_LINE_PATTERN_MASK) >> LCDC_CTRL_LINE_PATTERN_SHIFT) - -/* - * DISP_MODE (RW) - * - * LCDIF operating mode. - * 00b - Normal mode. Panel content controlled by layer configuration. - * 01b - Test Mode1.(BGND Color Display) - * 10b - Test Mode2.(Column Color Bar) - * 11b - Test Mode3.(Row Color Bar) - */ -#define LCDC_CTRL_DISP_MODE_MASK (0x6000000UL) -#define LCDC_CTRL_DISP_MODE_SHIFT (25U) -#define LCDC_CTRL_DISP_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_MODE_SHIFT) & LCDC_CTRL_DISP_MODE_MASK) -#define LCDC_CTRL_DISP_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_MODE_MASK) >> LCDC_CTRL_DISP_MODE_SHIFT) - -/* - * BGDCL4CLR (RW) - * - * background color for clear mode when the alpha channel is 0 - */ -#define LCDC_CTRL_BGDCL4CLR_MASK (0x1000000UL) -#define LCDC_CTRL_BGDCL4CLR_SHIFT (24U) -#define LCDC_CTRL_BGDCL4CLR_SET(x) (((uint32_t)(x) << LCDC_CTRL_BGDCL4CLR_SHIFT) & LCDC_CTRL_BGDCL4CLR_MASK) -#define LCDC_CTRL_BGDCL4CLR_GET(x) (((uint32_t)(x) & LCDC_CTRL_BGDCL4CLR_MASK) >> LCDC_CTRL_BGDCL4CLR_SHIFT) - -/* - * ARQOS (RW) - * - * ARQOS for bus fabric arbitration - */ -#define LCDC_CTRL_ARQOS_MASK (0xF00000UL) -#define LCDC_CTRL_ARQOS_SHIFT (20U) -#define LCDC_CTRL_ARQOS_SET(x) (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) -#define LCDC_CTRL_ARQOS_GET(x) (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) - -/* - * INV_PXDATA (RW) - * - * Indicates if value at the output (pixel data output) needs to be negated. - * 0b - Output is to remain same as the data inside memory - * 1b - Output to be negated from the data inside memory - */ -#define LCDC_CTRL_INV_PXDATA_MASK (0x10U) -#define LCDC_CTRL_INV_PXDATA_SHIFT (4U) -#define LCDC_CTRL_INV_PXDATA_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXDATA_SHIFT) & LCDC_CTRL_INV_PXDATA_MASK) -#define LCDC_CTRL_INV_PXDATA_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXDATA_MASK) >> LCDC_CTRL_INV_PXDATA_SHIFT) - -/* - * INV_PXCLK (RW) - * - * Polarity change of Pixel Clock. - * 0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge - * 1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - */ -#define LCDC_CTRL_INV_PXCLK_MASK (0x8U) -#define LCDC_CTRL_INV_PXCLK_SHIFT (3U) -#define LCDC_CTRL_INV_PXCLK_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXCLK_SHIFT) & LCDC_CTRL_INV_PXCLK_MASK) -#define LCDC_CTRL_INV_PXCLK_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXCLK_MASK) >> LCDC_CTRL_INV_PXCLK_SHIFT) - -/* - * INV_HREF (RW) - * - * Polarity of HREF - * 0b - HREF signal active HIGH, indicating active pixel data - * 1b - HREF signal active LOW - */ -#define LCDC_CTRL_INV_HREF_MASK (0x4U) -#define LCDC_CTRL_INV_HREF_SHIFT (2U) -#define LCDC_CTRL_INV_HREF_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HREF_SHIFT) & LCDC_CTRL_INV_HREF_MASK) -#define LCDC_CTRL_INV_HREF_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HREF_MASK) >> LCDC_CTRL_INV_HREF_SHIFT) - -/* - * INV_VSYNC (RW) - * - * Polarity of VSYNC - * 0b - VSYNC signal active HIGH - * 1b - VSYNC signal active LOW - */ -#define LCDC_CTRL_INV_VSYNC_MASK (0x2U) -#define LCDC_CTRL_INV_VSYNC_SHIFT (1U) -#define LCDC_CTRL_INV_VSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_VSYNC_SHIFT) & LCDC_CTRL_INV_VSYNC_MASK) -#define LCDC_CTRL_INV_VSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_VSYNC_MASK) >> LCDC_CTRL_INV_VSYNC_SHIFT) - -/* - * INV_HSYNC (RW) - * - * Polarity of HSYNC - * 0b - HSYNC signal active HIGH - * 1b - HSYNC signal active LOW - */ -#define LCDC_CTRL_INV_HSYNC_MASK (0x1U) -#define LCDC_CTRL_INV_HSYNC_SHIFT (0U) -#define LCDC_CTRL_INV_HSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HSYNC_SHIFT) & LCDC_CTRL_INV_HSYNC_MASK) -#define LCDC_CTRL_INV_HSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HSYNC_MASK) >> LCDC_CTRL_INV_HSYNC_SHIFT) - -/* Bitfield definition for register: BGND_CL */ -/* - * R (RW) - * - * Red component of the default color displayed in the sectors where no layer is active. - */ -#define LCDC_BGND_CL_R_MASK (0xFF0000UL) -#define LCDC_BGND_CL_R_SHIFT (16U) -#define LCDC_BGND_CL_R_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_R_SHIFT) & LCDC_BGND_CL_R_MASK) -#define LCDC_BGND_CL_R_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_R_MASK) >> LCDC_BGND_CL_R_SHIFT) - -/* - * G (RW) - * - * Green component of the default color displayed in the sectors where no layer is active. - */ -#define LCDC_BGND_CL_G_MASK (0xFF00U) -#define LCDC_BGND_CL_G_SHIFT (8U) -#define LCDC_BGND_CL_G_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_G_SHIFT) & LCDC_BGND_CL_G_MASK) -#define LCDC_BGND_CL_G_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_G_MASK) >> LCDC_BGND_CL_G_SHIFT) - -/* - * B (RW) - * - * Blue component of the default color displayed in the sectors where no layer is active. - */ -#define LCDC_BGND_CL_B_MASK (0xFFU) -#define LCDC_BGND_CL_B_SHIFT (0U) -#define LCDC_BGND_CL_B_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_B_SHIFT) & LCDC_BGND_CL_B_MASK) -#define LCDC_BGND_CL_B_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_B_MASK) >> LCDC_BGND_CL_B_SHIFT) - -/* Bitfield definition for register: DISP_WN_SIZE */ -/* - * Y (RW) - * - * Sets the display size vertical resolution in pixels. - */ -#define LCDC_DISP_WN_SIZE_Y_MASK (0xFFF0000UL) -#define LCDC_DISP_WN_SIZE_Y_SHIFT (16U) -#define LCDC_DISP_WN_SIZE_Y_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_Y_SHIFT) & LCDC_DISP_WN_SIZE_Y_MASK) -#define LCDC_DISP_WN_SIZE_Y_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_Y_MASK) >> LCDC_DISP_WN_SIZE_Y_SHIFT) - -/* - * X (RW) - * - * Sets the display size horizontal resolution in pixels. - */ -#define LCDC_DISP_WN_SIZE_X_MASK (0xFFFU) -#define LCDC_DISP_WN_SIZE_X_SHIFT (0U) -#define LCDC_DISP_WN_SIZE_X_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_X_SHIFT) & LCDC_DISP_WN_SIZE_X_MASK) -#define LCDC_DISP_WN_SIZE_X_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_X_MASK) >> LCDC_DISP_WN_SIZE_X_SHIFT) - -/* Bitfield definition for register: HSYNC_PARA */ -/* - * FP (RW) - * - * HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - */ -#define LCDC_HSYNC_PARA_FP_MASK (0x7FC00000UL) -#define LCDC_HSYNC_PARA_FP_SHIFT (22U) -#define LCDC_HSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_FP_SHIFT) & LCDC_HSYNC_PARA_FP_MASK) -#define LCDC_HSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_FP_MASK) >> LCDC_HSYNC_PARA_FP_SHIFT) - -/* - * BP (RW) - * - * HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - */ -#define LCDC_HSYNC_PARA_BP_MASK (0xFF800UL) -#define LCDC_HSYNC_PARA_BP_SHIFT (11U) -#define LCDC_HSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_BP_SHIFT) & LCDC_HSYNC_PARA_BP_MASK) -#define LCDC_HSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_BP_MASK) >> LCDC_HSYNC_PARA_BP_SHIFT) - -/* - * PW (RW) - * - * HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - */ -#define LCDC_HSYNC_PARA_PW_MASK (0x1FFU) -#define LCDC_HSYNC_PARA_PW_SHIFT (0U) -#define LCDC_HSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_PW_SHIFT) & LCDC_HSYNC_PARA_PW_MASK) -#define LCDC_HSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_PW_MASK) >> LCDC_HSYNC_PARA_PW_SHIFT) - -/* Bitfield definition for register: VSYNC_PARA */ -/* - * FP (RW) - * - * VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - */ -#define LCDC_VSYNC_PARA_FP_MASK (0x7FC00000UL) -#define LCDC_VSYNC_PARA_FP_SHIFT (22U) -#define LCDC_VSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_FP_SHIFT) & LCDC_VSYNC_PARA_FP_MASK) -#define LCDC_VSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_FP_MASK) >> LCDC_VSYNC_PARA_FP_SHIFT) - -/* - * BP (RW) - * - * VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - */ -#define LCDC_VSYNC_PARA_BP_MASK (0xFF800UL) -#define LCDC_VSYNC_PARA_BP_SHIFT (11U) -#define LCDC_VSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_BP_SHIFT) & LCDC_VSYNC_PARA_BP_MASK) -#define LCDC_VSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_BP_MASK) >> LCDC_VSYNC_PARA_BP_SHIFT) - -/* - * PW (RW) - * - * VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - */ -#define LCDC_VSYNC_PARA_PW_MASK (0x1FFU) -#define LCDC_VSYNC_PARA_PW_SHIFT (0U) -#define LCDC_VSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_PW_SHIFT) & LCDC_VSYNC_PARA_PW_MASK) -#define LCDC_VSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_PW_MASK) >> LCDC_VSYNC_PARA_PW_SHIFT) - -/* Bitfield definition for register: DMA_ST */ -/* - * DMA_ERR (W1C) - * - * plane n axi error. W1C. - */ -#define LCDC_DMA_ST_DMA_ERR_MASK (0xFF000000UL) -#define LCDC_DMA_ST_DMA_ERR_SHIFT (24U) -#define LCDC_DMA_ST_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA_ERR_SHIFT) & LCDC_DMA_ST_DMA_ERR_MASK) -#define LCDC_DMA_ST_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA_ERR_MASK) >> LCDC_DMA_ST_DMA_ERR_SHIFT) - -/* - * DMA1_DONE (W1C) - * - * Plane n frame 1 dma done. W1C. - */ -#define LCDC_DMA_ST_DMA1_DONE_MASK (0xFF0000UL) -#define LCDC_DMA_ST_DMA1_DONE_SHIFT (16U) -#define LCDC_DMA_ST_DMA1_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA1_DONE_SHIFT) & LCDC_DMA_ST_DMA1_DONE_MASK) -#define LCDC_DMA_ST_DMA1_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA1_DONE_MASK) >> LCDC_DMA_ST_DMA1_DONE_SHIFT) - -/* - * DMA0_DONE (W1C) - * - * Plane n frame 0 dma done. W1C. - */ -#define LCDC_DMA_ST_DMA0_DONE_MASK (0xFF00U) -#define LCDC_DMA_ST_DMA0_DONE_SHIFT (8U) -#define LCDC_DMA_ST_DMA0_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA0_DONE_SHIFT) & LCDC_DMA_ST_DMA0_DONE_MASK) -#define LCDC_DMA_ST_DMA0_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * URGENT_UNDERRUN (W1C) - * - * Asserted when the output buffer urgent underrun condition encountered - */ -#define LCDC_ST_URGENT_UNDERRUN_MASK (0x8U) -#define LCDC_ST_URGENT_UNDERRUN_SHIFT (3U) -#define LCDC_ST_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_URGENT_UNDERRUN_SHIFT) & LCDC_ST_URGENT_UNDERRUN_MASK) -#define LCDC_ST_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_URGENT_UNDERRUN_MASK) >> LCDC_ST_URGENT_UNDERRUN_SHIFT) - -/* - * VS_BLANK (W1C) - * - * Asserted when in vertical blanking period. At the start of VSYNC - */ -#define LCDC_ST_VS_BLANK_MASK (0x4U) -#define LCDC_ST_VS_BLANK_SHIFT (2U) -#define LCDC_ST_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_ST_VS_BLANK_SHIFT) & LCDC_ST_VS_BLANK_MASK) -#define LCDC_ST_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_ST_VS_BLANK_MASK) >> LCDC_ST_VS_BLANK_SHIFT) - -/* - * UNDERRUN (W1C) - * - * Asserted when the output buffer underrun condition encountered - */ -#define LCDC_ST_UNDERRUN_MASK (0x2U) -#define LCDC_ST_UNDERRUN_SHIFT (1U) -#define LCDC_ST_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_UNDERRUN_SHIFT) & LCDC_ST_UNDERRUN_MASK) -#define LCDC_ST_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_UNDERRUN_MASK) >> LCDC_ST_UNDERRUN_SHIFT) - -/* - * VSYNC (W1C) - * - * Asserted when in vertical blanking period. At the end of VSYNC - */ -#define LCDC_ST_VSYNC_MASK (0x1U) -#define LCDC_ST_VSYNC_SHIFT (0U) -#define LCDC_ST_VSYNC_SET(x) (((uint32_t)(x) << LCDC_ST_VSYNC_SHIFT) & LCDC_ST_VSYNC_MASK) -#define LCDC_ST_VSYNC_GET(x) (((uint32_t)(x) & LCDC_ST_VSYNC_MASK) >> LCDC_ST_VSYNC_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * DMA_ERR (RW) - * - * Interrupt enable for DMA error - */ -#define LCDC_INT_EN_DMA_ERR_MASK (0xFF000000UL) -#define LCDC_INT_EN_DMA_ERR_SHIFT (24U) -#define LCDC_INT_EN_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_ERR_SHIFT) & LCDC_INT_EN_DMA_ERR_MASK) -#define LCDC_INT_EN_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_ERR_MASK) >> LCDC_INT_EN_DMA_ERR_SHIFT) - -/* - * DMA_DONE (RW) - * - * Interrupt enable for DMA done - */ -#define LCDC_INT_EN_DMA_DONE_MASK (0xFF0000UL) -#define LCDC_INT_EN_DMA_DONE_SHIFT (16U) -#define LCDC_INT_EN_DMA_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_DONE_SHIFT) & LCDC_INT_EN_DMA_DONE_MASK) -#define LCDC_INT_EN_DMA_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) - -/* - * URGENT_UNDERRUN (RW) - * - * Asserted when the output buffer urgent underrun condition encountered - */ -#define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) -#define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) -#define LCDC_INT_EN_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) -#define LCDC_INT_EN_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) - -/* - * VS_BLANK (RW) - * - * Interrupt enable for start of sof - */ -#define LCDC_INT_EN_VS_BLANK_MASK (0x4U) -#define LCDC_INT_EN_VS_BLANK_SHIFT (2U) -#define LCDC_INT_EN_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VS_BLANK_SHIFT) & LCDC_INT_EN_VS_BLANK_MASK) -#define LCDC_INT_EN_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VS_BLANK_MASK) >> LCDC_INT_EN_VS_BLANK_SHIFT) - -/* - * UNDERRUN (RW) - * - * Interrupt enable for underrun - */ -#define LCDC_INT_EN_UNDERRUN_MASK (0x2U) -#define LCDC_INT_EN_UNDERRUN_SHIFT (1U) -#define LCDC_INT_EN_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_UNDERRUN_SHIFT) & LCDC_INT_EN_UNDERRUN_MASK) -#define LCDC_INT_EN_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_UNDERRUN_MASK) >> LCDC_INT_EN_UNDERRUN_SHIFT) - -/* - * VSYNC (RW) - * - * Interrupt enable for end of sof - */ -#define LCDC_INT_EN_VSYNC_MASK (0x1U) -#define LCDC_INT_EN_VSYNC_SHIFT (0U) -#define LCDC_INT_EN_VSYNC_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VSYNC_SHIFT) & LCDC_INT_EN_VSYNC_MASK) -#define LCDC_INT_EN_VSYNC_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VSYNC_MASK) >> LCDC_INT_EN_VSYNC_SHIFT) - -/* Bitfield definition for register: TXFIFO */ -/* - * THRSH (RW) - * - * Threshold to start the lcd raster (0--0x7F) - */ -#define LCDC_TXFIFO_THRSH_MASK (0xFFU) -#define LCDC_TXFIFO_THRSH_SHIFT (0U) -#define LCDC_TXFIFO_THRSH_SET(x) (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) -#define LCDC_TXFIFO_THRSH_GET(x) (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LAYCTRL */ -/* - * PACK_DIR (RW) - * - * The byte sequence of the 4 bytes in a 32-bit word. - * 1: {A0, A1, A2, A3} byte re-ordered. - * 0: {A3, A2, A1, A0} the normal case with no byte re-order - */ -#define LCDC_LAYER_LAYCTRL_PACK_DIR_MASK (0x80000UL) -#define LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT (19U) -#define LCDC_LAYER_LAYCTRL_PACK_DIR_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) -#define LCDC_LAYER_LAYCTRL_PACK_DIR_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) >> LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) - -/* - * SHADOW_LOAD_EN (RW) - * - * Shadow Load Enable - * The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - */ -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK (0x10000UL) -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT (16U) -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) >> LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) - -/* - * YUV_FORMAT (RW) - * - * The YUV422 input format selection. - * 00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 - * 01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 - * 10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 - * 11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 - * If not YUV422 mode, - * FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) - * FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - */ -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK (0xC000U) -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT (14U) -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) >> LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) - -/* - * PIXFORMAT (RW) - * - * Layer encoding format (bit per pixel) - * 0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. - * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. - * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. - * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. - * 0100b - 16 bpp (RGB565), the low byte contains the full R component. - * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] - * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A - * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - */ -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK (0x3C00U) -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT (10U) -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) >> LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) - -/* - * LOCALPHA_OP (RW) - * - * The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream - * 1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) - * 2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream - * Others: Reserved - */ -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK (0x300U) -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT (8U) -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) - -/* - * INALPHA_OP (RW) - * - * The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline - * 1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) - * 2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline - * Others: Reserved - */ -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK (0xC0U) -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT (6U) -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) - -/* - * AB_MODE (RW) - * - * Alpha Blending Mode - * 0: SKBlendMode_Clear; - * 1: SKBlendMode_Src ; - * 2: SKBlendMode_Dst - * 3: SKBlendMode_SrcOver - * 4: SKBlendMode_DstOver - * 5: SKBlendMode_SrcIn - * 6: SKBlendMode_DstIn - * 7: SKBlendMode_SrcOut - * 8: SKBlendMode_DstOut - * 9: SKBlendMode_SrcATop - * 10: SKBlendMode_DstATop - * 11: SKBlendMode_Xor - * 12: SKBlendMode_Plus (The conventional blending mode) - * 13: SKBlendMode_Modulate - * 14: SRC org - * 15: DST org - * Others: Reserved. - */ -#define LCDC_LAYER_LAYCTRL_AB_MODE_MASK (0x3CU) -#define LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT (2U) -#define LCDC_LAYER_LAYCTRL_AB_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) -#define LCDC_LAYER_LAYCTRL_AB_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) >> LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) - -/* - * EN (RW) - * - * Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - */ -#define LCDC_LAYER_LAYCTRL_EN_MASK (0x1U) -#define LCDC_LAYER_LAYCTRL_EN_SHIFT (0U) -#define LCDC_LAYER_LAYCTRL_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_EN_SHIFT) & LCDC_LAYER_LAYCTRL_EN_MASK) -#define LCDC_LAYER_LAYCTRL_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_EN_MASK) >> LCDC_LAYER_LAYCTRL_EN_SHIFT) - -/* Bitfield definition for register of struct array LAYER: ALPHAS */ -/* - * LOCD (RW) - * - * The system alpha value for the data stream of current layer stream (SRC) - */ -#define LCDC_LAYER_ALPHAS_LOCD_MASK (0xFF00U) -#define LCDC_LAYER_ALPHAS_LOCD_SHIFT (8U) -#define LCDC_LAYER_ALPHAS_LOCD_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_LOCD_SHIFT) & LCDC_LAYER_ALPHAS_LOCD_MASK) -#define LCDC_LAYER_ALPHAS_LOCD_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_LOCD_MASK) >> LCDC_LAYER_ALPHAS_LOCD_SHIFT) - -/* - * IND (RW) - * - * The system alpha value for the input stream from previous stage (DST) - */ -#define LCDC_LAYER_ALPHAS_IND_MASK (0xFFU) -#define LCDC_LAYER_ALPHAS_IND_SHIFT (0U) -#define LCDC_LAYER_ALPHAS_IND_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_IND_SHIFT) & LCDC_LAYER_ALPHAS_IND_MASK) -#define LCDC_LAYER_ALPHAS_IND_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_IND_MASK) >> LCDC_LAYER_ALPHAS_IND_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LAYSIZE */ -/* - * HEIGHT (RW) - * - * Height of the layer in pixels - */ -#define LCDC_LAYER_LAYSIZE_HEIGHT_MASK (0xFFF0000UL) -#define LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT (16U) -#define LCDC_LAYER_LAYSIZE_HEIGHT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) -#define LCDC_LAYER_LAYSIZE_HEIGHT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) >> LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) - -/* - * WIDTH (RW) - * - * Width of the layer in pixels (Note: not actual width-1) - * The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - */ -#define LCDC_LAYER_LAYSIZE_WIDTH_MASK (0xFFFU) -#define LCDC_LAYER_LAYSIZE_WIDTH_SHIFT (0U) -#define LCDC_LAYER_LAYSIZE_WIDTH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) -#define LCDC_LAYER_LAYSIZE_WIDTH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LAYPOS */ -/* - * Y (RW) - * - * The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - */ -#define LCDC_LAYER_LAYPOS_Y_MASK (0xFFFF0000UL) -#define LCDC_LAYER_LAYPOS_Y_SHIFT (16U) -#define LCDC_LAYER_LAYPOS_Y_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_Y_SHIFT) & LCDC_LAYER_LAYPOS_Y_MASK) -#define LCDC_LAYER_LAYPOS_Y_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_Y_MASK) >> LCDC_LAYER_LAYPOS_Y_SHIFT) - -/* - * X (RW) - * - * The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - */ -#define LCDC_LAYER_LAYPOS_X_MASK (0xFFFFU) -#define LCDC_LAYER_LAYPOS_X_SHIFT (0U) -#define LCDC_LAYER_LAYPOS_X_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_X_SHIFT) & LCDC_LAYER_LAYPOS_X_MASK) -#define LCDC_LAYER_LAYPOS_X_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_X_MASK) >> LCDC_LAYER_LAYPOS_X_SHIFT) - -/* Bitfield definition for register of struct array LAYER: START0 */ -/* - * ADDR0 (RW) - * - * Input buffer Start address 0 - */ -#define LCDC_LAYER_START0_ADDR0_MASK (0xFFFFFFFFUL) -#define LCDC_LAYER_START0_ADDR0_SHIFT (0U) -#define LCDC_LAYER_START0_ADDR0_SET(x) (((uint32_t)(x) << LCDC_LAYER_START0_ADDR0_SHIFT) & LCDC_LAYER_START0_ADDR0_MASK) -#define LCDC_LAYER_START0_ADDR0_GET(x) (((uint32_t)(x) & LCDC_LAYER_START0_ADDR0_MASK) >> LCDC_LAYER_START0_ADDR0_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LINECFG */ -/* - * MPT_SIZE (RW) - * - * Maximal Per Transfer Data Size: - * 0: 64 bytes - * 1: 128 bytes - * 2: 256 bytes - * 3: 512 bytes - * 4: 1024 bytes - */ -#define LCDC_LAYER_LINECFG_MPT_SIZE_MASK (0xE0000000UL) -#define LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT (29U) -#define LCDC_LAYER_LINECFG_MPT_SIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) -#define LCDC_LAYER_LINECFG_MPT_SIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) >> LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) - -/* - * MAX_OT (RW) - * - * the number of outstanding axi read transactions. - * If zero, it means max 8. - */ -#define LCDC_LAYER_LINECFG_MAX_OT_MASK (0xE00000UL) -#define LCDC_LAYER_LINECFG_MAX_OT_SHIFT (21U) -#define LCDC_LAYER_LINECFG_MAX_OT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MAX_OT_SHIFT) & LCDC_LAYER_LINECFG_MAX_OT_MASK) -#define LCDC_LAYER_LINECFG_MAX_OT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MAX_OT_MASK) >> LCDC_LAYER_LINECFG_MAX_OT_SHIFT) - -/* - * PITCH (RW) - * - * Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. - */ -#define LCDC_LAYER_LINECFG_PITCH_MASK (0xFFFFU) -#define LCDC_LAYER_LINECFG_PITCH_SHIFT (0U) -#define LCDC_LAYER_LINECFG_PITCH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_PITCH_SHIFT) & LCDC_LAYER_LINECFG_PITCH_MASK) -#define LCDC_LAYER_LINECFG_PITCH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_PITCH_MASK) >> LCDC_LAYER_LINECFG_PITCH_SHIFT) - -/* Bitfield definition for register of struct array LAYER: BG_CL */ -/* - * ARGB (RW) - * - * ARGB8888. It is only useful in the last active stage in the pipeline. - */ -#define LCDC_LAYER_BG_CL_ARGB_MASK (0xFFFFFFFFUL) -#define LCDC_LAYER_BG_CL_ARGB_SHIFT (0U) -#define LCDC_LAYER_BG_CL_ARGB_SET(x) (((uint32_t)(x) << LCDC_LAYER_BG_CL_ARGB_SHIFT) & LCDC_LAYER_BG_CL_ARGB_MASK) -#define LCDC_LAYER_BG_CL_ARGB_GET(x) (((uint32_t)(x) & LCDC_LAYER_BG_CL_ARGB_MASK) >> LCDC_LAYER_BG_CL_ARGB_SHIFT) - -/* Bitfield definition for register of struct array LAYER: CSC_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * This bit changes the behavior when performing U/V converting. - * 0b - Converting YUV to RGB data - * 1b - Converting YCbCr to RGB data - */ -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) >> LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Enable the CSC unit in the LCDC plane data path. - * 0b - The CSC is bypassed and the input pixels are RGB data already - * 1b - The CSC is enabled and the pixels will be converted to RGB data - * This bit will be shadowed. - */ -#define LCDC_LAYER_CSC_COEF0_ENABLE_MASK (0x40000000UL) -#define LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT (30U) -#define LCDC_LAYER_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) -#define LCDC_LAYER_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) >> LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define LCDC_LAYER_CSC_COEF0_C0_MASK (0x1FFC0000UL) -#define LCDC_LAYER_CSC_COEF0_C0_SHIFT (18U) -#define LCDC_LAYER_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_C0_SHIFT) & LCDC_LAYER_CSC_COEF0_C0_MASK) -#define LCDC_LAYER_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_C0_MASK) >> LCDC_LAYER_CSC_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT (9U) -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT (0U) -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register of struct array LAYER: CSC_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define LCDC_LAYER_CSC_COEF1_C1_MASK (0x7FF0000UL) -#define LCDC_LAYER_CSC_COEF1_C1_SHIFT (16U) -#define LCDC_LAYER_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C1_SHIFT) & LCDC_LAYER_CSC_COEF1_C1_MASK) -#define LCDC_LAYER_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C1_MASK) >> LCDC_LAYER_CSC_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define LCDC_LAYER_CSC_COEF1_C4_MASK (0x7FFU) -#define LCDC_LAYER_CSC_COEF1_C4_SHIFT (0U) -#define LCDC_LAYER_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C4_SHIFT) & LCDC_LAYER_CSC_COEF1_C4_MASK) -#define LCDC_LAYER_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C4_MASK) >> LCDC_LAYER_CSC_COEF1_C4_SHIFT) - -/* Bitfield definition for register of struct array LAYER: CSC_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define LCDC_LAYER_CSC_COEF2_C2_MASK (0x7FF0000UL) -#define LCDC_LAYER_CSC_COEF2_C2_SHIFT (16U) -#define LCDC_LAYER_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C2_SHIFT) & LCDC_LAYER_CSC_COEF2_C2_MASK) -#define LCDC_LAYER_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C2_MASK) >> LCDC_LAYER_CSC_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define LCDC_LAYER_CSC_COEF2_C3_MASK (0x7FFU) -#define LCDC_LAYER_CSC_COEF2_C3_SHIFT (0U) -#define LCDC_LAYER_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C3_SHIFT) & LCDC_LAYER_CSC_COEF2_C3_MASK) -#define LCDC_LAYER_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) - -/* Bitfield definition for register: CLUT_LOAD */ -/* - * SEL_NUM (RW) - * - * Selected CLUT Number - * The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. - * . 3'h0 - PLANE 0 - * . 3'h1 - PLANE 1 - * . ------ - * . 3'h7 - PLANE 7 - * CLUT 8 can be modified via APB even when display is on. - * Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - */ -#define LCDC_CLUT_LOAD_SEL_NUM_MASK (0x70U) -#define LCDC_CLUT_LOAD_SEL_NUM_SHIFT (4U) -#define LCDC_CLUT_LOAD_SEL_NUM_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_SEL_NUM_SHIFT) & LCDC_CLUT_LOAD_SEL_NUM_MASK) -#define LCDC_CLUT_LOAD_SEL_NUM_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_SEL_NUM_MASK) >> LCDC_CLUT_LOAD_SEL_NUM_SHIFT) - -/* - * UPDATE_EN (RW) - * - * CLUT Update Enable - * The bit is written to 1 when software want to update the Color Look Up Tables during display. - * If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. - * If set to 0, software can update CLUT8 directly according to the CLUT memory map. - * Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - */ -#define LCDC_CLUT_LOAD_UPDATE_EN_MASK (0x1U) -#define LCDC_CLUT_LOAD_UPDATE_EN_SHIFT (0U) -#define LCDC_CLUT_LOAD_UPDATE_EN_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) -#define LCDC_CLUT_LOAD_UPDATE_EN_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) >> LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) - - - -/* LAYER register group index macro definition */ -#define LCDC_LAYER_0 (0UL) -#define LCDC_LAYER_1 (1UL) -#define LCDC_LAYER_2 (2UL) -#define LCDC_LAYER_3 (3UL) -#define LCDC_LAYER_4 (4UL) -#define LCDC_LAYER_5 (5UL) -#define LCDC_LAYER_6 (6UL) -#define LCDC_LAYER_7 (7UL) - - -#endif /* HPM_LCDC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mbx_regs.h deleted file mode 100644 index d159b97303a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mbx_regs.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_H -#define HPM_MBX_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Command Registers */ - __RW uint32_t SR; /* 0x4: Status Registers */ - __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ - __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ - __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ -} MBX_Type; - - -/* Bitfield definition for register: CR */ -/* - * TXRESET (RW) - * - * Reset TX Fifo and word. - */ -#define MBX_CR_TXRESET_MASK (0x80000000UL) -#define MBX_CR_TXRESET_SHIFT (31U) -#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) -#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) - -/* - * BARCTL (RW) - * - * Bus Access Response Control, when bit 15:14= - * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. - * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. - * 11: reserved. - */ -#define MBX_CR_BARCTL_MASK (0xC000U) -#define MBX_CR_BARCTL_SHIFT (14U) -#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) -#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. - * 1, enable the bus access error interrupt. - * 0, disable the bus access error interrupt. - */ -#define MBX_CR_BEIE_MASK (0x100U) -#define MBX_CR_BEIE_SHIFT (8U) -#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) -#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) - -/* - * TFMAIE (RW) - * - * TX FIFO message available interrupt enable. - * 1, enable the TX FIFO massage available interrupt. - * 0, disable the TX FIFO message available interrupt. - */ -#define MBX_CR_TFMAIE_MASK (0x80U) -#define MBX_CR_TFMAIE_SHIFT (7U) -#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) -#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) - -/* - * TFMEIE (RW) - * - * TX FIFO message empty interrupt enable. - * 1, enable the TX FIFO massage empty interrupt. - * 0, disable the TX FIFO message empty interrupt. - */ -#define MBX_CR_TFMEIE_MASK (0x40U) -#define MBX_CR_TFMEIE_SHIFT (6U) -#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) -#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) - -/* - * RFMAIE (RW) - * - * RX FIFO message available interrupt enable. - * 1, enable the RX FIFO massage available interrupt. - * 0, disable the RX FIFO message available interrupt. - */ -#define MBX_CR_RFMAIE_MASK (0x20U) -#define MBX_CR_RFMAIE_SHIFT (5U) -#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) -#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) - -/* - * RFMFIE (RW) - * - * RX fifo message full interrupt enable. - * 1, enable the RX fifo message full interrupt. - * 0, disable the RX fifo message full interrupt. - */ -#define MBX_CR_RFMFIE_MASK (0x10U) -#define MBX_CR_RFMFIE_SHIFT (4U) -#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) -#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) - -/* - * TWMEIE (RW) - * - * TX word message empty interrupt enable. - * 1, enable the TX word massage empty interrupt. - * 0, disable the TX word message empty interrupt. - */ -#define MBX_CR_TWMEIE_MASK (0x2U) -#define MBX_CR_TWMEIE_SHIFT (1U) -#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) -#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) - -/* - * RWMVIE (RW) - * - * RX word message valid interrupt enable. - * 1, enable the RX word massage valid interrupt. - * 0, disable the RX word message valid interrupt. - */ -#define MBX_CR_RWMVIE_MASK (0x1U) -#define MBX_CR_RWMVIE_SHIFT (0U) -#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) -#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * RFVC (RO) - * - * RX FIFO valid message count - */ -#define MBX_SR_RFVC_MASK (0xF00000UL) -#define MBX_SR_RFVC_SHIFT (20U) -#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) - -/* - * TFEC (RO) - * - * TX FIFO empty message word count - */ -#define MBX_SR_TFEC_MASK (0xF0000UL) -#define MBX_SR_TFEC_SHIFT (16U) -#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) - -/* - * ERRRE (W1C) - * - * bus Error for read when rx word message are still invalid, this bit is W1C bit. - * 1, read from word message when the word message are still invalid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRRE_MASK (0x2000U) -#define MBX_SR_ERRRE_SHIFT (13U) -#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) -#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) - -/* - * EWTRF (W1C) - * - * bus Error for write when tx word message are still valid, this bit is W1C bit. - * 1, write to word message when the word message are still valid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTRF_MASK (0x1000U) -#define MBX_SR_EWTRF_SHIFT (12U) -#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) -#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) - -/* - * ERRFE (W1C) - * - * bus Error for read when rx fifo empty, this bit is W1C bit. - * 1, read from a empty rx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRFE_MASK (0x800U) -#define MBX_SR_ERRFE_SHIFT (11U) -#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) -#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) - -/* - * EWTFF (W1C) - * - * bus Error for write when tx fifo full, this bit is W1C bit. - * 1, write to a fulled tx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTFF_MASK (0x400U) -#define MBX_SR_EWTFF_SHIFT (10U) -#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) -#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) - -/* - * EAIVA (W1C) - * - * bus Error for Accessing Invalid Address; this bit is W1C bit. - * 1, read and write to invalid address in the bus of this block, will set this bit. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EAIVA_MASK (0x200U) -#define MBX_SR_EAIVA_SHIFT (9U) -#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) -#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) - -/* - * EW2RO (W1C) - * - * bus Error for Write to Read Only address; this bit is W1C bit. - * 1, write to read only address happened in the bus of this block. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EW2RO_MASK (0x100U) -#define MBX_SR_EW2RO_SHIFT (8U) -#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) -#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) - -/* - * TFMA (RW) - * - * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. - * 1, TXFIFO message buffer has slot available - * 0, no slot available (fifo full) - */ -#define MBX_SR_TFMA_MASK (0x80U) -#define MBX_SR_TFMA_SHIFT (7U) -#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) -#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) - -/* - * TFME (RW) - * - * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. - * 1, no any message data in TXFIFO from other core. - * 0, there are some data in the 4x32 TX FIFO from other core yet. - */ -#define MBX_SR_TFME_MASK (0x40U) -#define MBX_SR_TFME_SHIFT (6U) -#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) -#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) - -/* - * RFMA (RO) - * - * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, no any data in the 4x32 TXFIFO message buffer. - * 0, there are some data in the the 4x32 TXFIFO message buffer already. - */ -#define MBX_SR_RFMA_MASK (0x20U) -#define MBX_SR_RFMA_SHIFT (5U) -#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) - -/* - * RFMF (RO) - * - * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written 4x32 message in the RXFIFO. - * 0, no 4x32 RX FIFO message from other core yet. - */ -#define MBX_SR_RFMF_MASK (0x10U) -#define MBX_SR_RFMF_SHIFT (4U) -#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) - -/* - * TWME (RO) - * - * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, means this core had write word message to TXREG. - * 0, means no valid word message in the TXREG yet. - */ -#define MBX_SR_TWME_MASK (0x2U) -#define MBX_SR_TWME_SHIFT (1U) -#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) - -/* - * RWMV (RO) - * - * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written word message in the RXREG. - * 0, no valid word message yet in the RXREG. - */ -#define MBX_SR_RWMV_MASK (0x1U) -#define MBX_SR_RWMV_SHIFT (0U) -#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) - -/* Bitfield definition for register: TXREG */ -/* - * TXREG (WO) - * - * Transmit word message to other core. - */ -#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) -#define MBX_TXREG_TXREG_SHIFT (0U) -#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) -#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) - -/* Bitfield definition for register: RXREG */ -/* - * RXREG (RO) - * - * Receive word message from other core. - */ -#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) -#define MBX_RXREG_RXREG_SHIFT (0U) -#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) - -/* Bitfield definition for register array: TXWRD */ -/* - * TXFIFO (WO) - * - * TXFIFO for sending message to other core, FIFO size, 4x32 - * can write one of the word address to push data to the FIFO; - * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - */ -#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_TXWRD_TXFIFO_SHIFT (0U) -#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) -#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) - -/* Bitfield definition for register array: RXWRD */ -/* - * RXFIFO (RO) - * - * RXFIFO for receiving message from other core, FIFO size, 4x32 - * can read one of the word address to pop data to the FIFO; - * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - */ -#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_RXWRD_RXFIFO_SHIFT (0U) -#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) - - - -/* TXWRD register group index macro definition */ -#define MBX_TXWRD_TXFIFO0 (0UL) - -/* RXWRD register group index macro definition */ -#define MBX_RXWRD_RXFIFO0 (0UL) - - -#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mchtmr_regs.h deleted file mode 100644 index d9dfe58a7b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mchtmr_regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCHTMR_H -#define HPM_MCHTMR_H - -typedef struct { - __RW uint64_t MTIME; /* 0x0: Machine Time */ - __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ -} MCHTMR_Type; - - -/* Bitfield definition for register: MTIME */ -/* - * MTIME (RW) - * - * Machine time - */ -#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIME_MTIME_SHIFT (0U) -#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) -#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) - -/* Bitfield definition for register: MTIMECMP */ -/* - * MTIMECMP (RW) - * - * Machine time compare - */ -#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) -#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) -#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) - - - - -#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mono_regs.h deleted file mode 100644 index 2c6c3a3d2fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_mono_regs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MONO_H -#define HPM_MONO_H - -typedef struct { - __RW uint32_t MONOL; /* 0x0: Low part of monotonic counter */ - __RW uint32_t MONOH; /* 0x4: High part of monotonic counter */ -} MONO_Type; - - -/* Bitfield definition for register: MONOL */ -/* - * COUNTER (RW) - * - * low part of monotonica counter, write to this counter will cause counter increase by 1 - */ -#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) -#define MONO_MONOL_COUNTER_SHIFT (0U) -#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) -#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) - -/* Bitfield definition for register: MONOH */ -/* - * EPOCH (RW) - * - * Fuse value for high part of monotonica - */ -#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) -#define MONO_MONOH_EPOCH_SHIFT (16U) -#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) -#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) - -/* - * COUNTER (RW) - * - * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - */ -#define MONO_MONOH_COUNTER_MASK (0xFFFFU) -#define MONO_MONOH_COUNTER_SHIFT (0U) -#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) -#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) - - - - -#endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_otp_regs.h deleted file mode 100644 index feb5f9c2efe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_otp_regs.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OTP_H -#define HPM_OTP_H - -typedef struct { - __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ - __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ - __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ - __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ - __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ - __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ - __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ - __RW uint32_t DATA; /* 0x804: DATA */ - __RW uint32_t ADDR; /* 0x808: ADDR */ - __RW uint32_t CMD; /* 0x80C: CMD */ - __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ - __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ - __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ - __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ - __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ - __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ - __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ - __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ -} OTP_Type; - - -/* Bitfield definition for register array: SHADOW */ -/* - * SHADOW (RW) - * - * shadow register of fuse for pmic area - * for PMIC, index valid for 0-15, for SOC index valid for 16-128 - */ -#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_SHADOW_SHIFT (0U) -#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) -#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) - -/* Bitfield definition for register array: SHADOW_LOCK */ -/* - * LOCK (RW) - * - * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) -#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) -#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register array: FUSE */ -/* - * FUSE (RW) - * - * fuse array, valid in PMIC part only - * read operation will read out value in fuse array - * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - */ -#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_FUSE_SHIFT (0U) -#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) -#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) - -/* Bitfield definition for register array: FUSE_LOCK */ -/* - * LOCK (RW) - * - * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) -#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) -#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK (RW) - * - * unlock word for fuse array operation - * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. - * Please make sure 24M crystal is running and 2.5V LDO working properly - */ -#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) -#define OTP_UNLOCK_UNLOCK_SHIFT (0U) -#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) -#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * data register for non-blocking access - * this register hold dat read from fuse array or data to by programmed to fuse array - */ -#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) -#define OTP_DATA_DATA_SHIFT (0U) -#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) -#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * word address to be read or write - */ -#define OTP_ADDR_ADDR_MASK (0x7FU) -#define OTP_ADDR_ADDR_SHIFT (0U) -#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) -#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * command to access fure array - * "BLOW" will update fuse word at ADDR to value hold in DATA - * "READ" will fetch fuse value in at ADDR to DATA register - */ -#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) -#define OTP_CMD_CMD_SHIFT (0U) -#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) -#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) - -/* Bitfield definition for register: LOAD_REQ */ -/* - * REQUEST (RW) - * - * reload request for 4 regions - * bit0: region0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) -#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) -#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) -#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) - -/* Bitfield definition for register: LOAD_COMP */ -/* - * COMPLETE (RW) - * - * reload complete sign for 4 regions - * bit0: region 0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) -#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) -#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) -#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) - -/* Bitfield definition for register array: REGION */ -/* - * STOP (RW) - * - * stop address of load region, fuse word at end address will NOT be reloaded - * region0: fixed at 8 - * region1: fixed at 16 - * region2: fixed at 0, - * region3: usrer configurable - */ -#define OTP_REGION_STOP_MASK (0x7F00U) -#define OTP_REGION_STOP_SHIFT (8U) -#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) -#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) - -/* - * START (RW) - * - * start address of load region, fuse word at start address will be reloaded - * region0: fixed at 0 - * region1: fixed at 8 - * region2: fixed at 16, - * region3: usrer configurable - */ -#define OTP_REGION_START_MASK (0x7FU) -#define OTP_REGION_START_SHIFT (0U) -#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) -#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) - -/* Bitfield definition for register: INT_FLAG */ -/* - * WRITE (RW) - * - * fuse write flag, write 1 to clear - * 0: fuse is not written or writing - * 1: value in DATA register is programmed into fuse - */ -#define OTP_INT_FLAG_WRITE_MASK (0x4U) -#define OTP_INT_FLAG_WRITE_SHIFT (2U) -#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) -#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read flag, write 1 to clear - * 0: fuse is not read or reading - * 1: fuse value is put in DATA register - */ -#define OTP_INT_FLAG_READ_MASK (0x2U) -#define OTP_INT_FLAG_READ_SHIFT (1U) -#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) -#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load flag, write 1 to clear - * 0: fuse is not loaded or loading - * 1: fuse loaded - */ -#define OTP_INT_FLAG_LOAD_MASK (0x1U) -#define OTP_INT_FLAG_LOAD_SHIFT (0U) -#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) -#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRITE (RW) - * - * fuse write interrupt enable - * 0: fuse write interrupt is not enable - * 1: fuse write interrupt is enable - */ -#define OTP_INT_EN_WRITE_MASK (0x4U) -#define OTP_INT_EN_WRITE_SHIFT (2U) -#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) -#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read interrupt enable - * 0: fuse read interrupt is not enable - * 1: fuse read interrupt is enable - */ -#define OTP_INT_EN_READ_MASK (0x2U) -#define OTP_INT_EN_READ_SHIFT (1U) -#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) -#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load interrupt enable - * 0: fuse load interrupt is not enable - * 1: fuse load interrupt is enable - */ -#define OTP_INT_EN_LOAD_MASK (0x1U) -#define OTP_INT_EN_LOAD_SHIFT (0U) -#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) -#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) - - - -/* SHADOW register group index macro definition */ -#define OTP_SHADOW_SHADOW000 (0UL) -#define OTP_SHADOW_SHADOW001 (1UL) -#define OTP_SHADOW_SHADOW002 (2UL) -#define OTP_SHADOW_SHADOW003 (3UL) -#define OTP_SHADOW_SHADOW004 (4UL) -#define OTP_SHADOW_SHADOW005 (5UL) -#define OTP_SHADOW_SHADOW006 (6UL) -#define OTP_SHADOW_SHADOW007 (7UL) -#define OTP_SHADOW_SHADOW008 (8UL) -#define OTP_SHADOW_SHADOW009 (9UL) -#define OTP_SHADOW_SHADOW010 (10UL) -#define OTP_SHADOW_SHADOW011 (11UL) -#define OTP_SHADOW_SHADOW012 (12UL) -#define OTP_SHADOW_SHADOW013 (13UL) -#define OTP_SHADOW_SHADOW014 (14UL) -#define OTP_SHADOW_SHADOW015 (15UL) -#define OTP_SHADOW_SHADOW016 (16UL) -#define OTP_SHADOW_SHADOW017 (17UL) -#define OTP_SHADOW_SHADOW018 (18UL) -#define OTP_SHADOW_SHADOW019 (19UL) -#define OTP_SHADOW_SHADOW020 (20UL) -#define OTP_SHADOW_SHADOW021 (21UL) -#define OTP_SHADOW_SHADOW022 (22UL) -#define OTP_SHADOW_SHADOW023 (23UL) -#define OTP_SHADOW_SHADOW024 (24UL) -#define OTP_SHADOW_SHADOW025 (25UL) -#define OTP_SHADOW_SHADOW026 (26UL) -#define OTP_SHADOW_SHADOW027 (27UL) -#define OTP_SHADOW_SHADOW028 (28UL) -#define OTP_SHADOW_SHADOW029 (29UL) -#define OTP_SHADOW_SHADOW030 (30UL) -#define OTP_SHADOW_SHADOW031 (31UL) -#define OTP_SHADOW_SHADOW032 (32UL) -#define OTP_SHADOW_SHADOW033 (33UL) -#define OTP_SHADOW_SHADOW034 (34UL) -#define OTP_SHADOW_SHADOW035 (35UL) -#define OTP_SHADOW_SHADOW036 (36UL) -#define OTP_SHADOW_SHADOW037 (37UL) -#define OTP_SHADOW_SHADOW038 (38UL) -#define OTP_SHADOW_SHADOW039 (39UL) -#define OTP_SHADOW_SHADOW040 (40UL) -#define OTP_SHADOW_SHADOW041 (41UL) -#define OTP_SHADOW_SHADOW042 (42UL) -#define OTP_SHADOW_SHADOW043 (43UL) -#define OTP_SHADOW_SHADOW044 (44UL) -#define OTP_SHADOW_SHADOW045 (45UL) -#define OTP_SHADOW_SHADOW046 (46UL) -#define OTP_SHADOW_SHADOW047 (47UL) -#define OTP_SHADOW_SHADOW048 (48UL) -#define OTP_SHADOW_SHADOW049 (49UL) -#define OTP_SHADOW_SHADOW050 (50UL) -#define OTP_SHADOW_SHADOW051 (51UL) -#define OTP_SHADOW_SHADOW052 (52UL) -#define OTP_SHADOW_SHADOW053 (53UL) -#define OTP_SHADOW_SHADOW054 (54UL) -#define OTP_SHADOW_SHADOW055 (55UL) -#define OTP_SHADOW_SHADOW056 (56UL) -#define OTP_SHADOW_SHADOW057 (57UL) -#define OTP_SHADOW_SHADOW058 (58UL) -#define OTP_SHADOW_SHADOW059 (59UL) -#define OTP_SHADOW_SHADOW060 (60UL) -#define OTP_SHADOW_SHADOW061 (61UL) -#define OTP_SHADOW_SHADOW062 (62UL) -#define OTP_SHADOW_SHADOW063 (63UL) -#define OTP_SHADOW_SHADOW064 (64UL) -#define OTP_SHADOW_SHADOW065 (65UL) -#define OTP_SHADOW_SHADOW066 (66UL) -#define OTP_SHADOW_SHADOW067 (67UL) -#define OTP_SHADOW_SHADOW068 (68UL) -#define OTP_SHADOW_SHADOW069 (69UL) -#define OTP_SHADOW_SHADOW070 (70UL) -#define OTP_SHADOW_SHADOW071 (71UL) -#define OTP_SHADOW_SHADOW072 (72UL) -#define OTP_SHADOW_SHADOW073 (73UL) -#define OTP_SHADOW_SHADOW074 (74UL) -#define OTP_SHADOW_SHADOW075 (75UL) -#define OTP_SHADOW_SHADOW076 (76UL) -#define OTP_SHADOW_SHADOW077 (77UL) -#define OTP_SHADOW_SHADOW078 (78UL) -#define OTP_SHADOW_SHADOW079 (79UL) -#define OTP_SHADOW_SHADOW080 (80UL) -#define OTP_SHADOW_SHADOW081 (81UL) -#define OTP_SHADOW_SHADOW082 (82UL) -#define OTP_SHADOW_SHADOW083 (83UL) -#define OTP_SHADOW_SHADOW084 (84UL) -#define OTP_SHADOW_SHADOW085 (85UL) -#define OTP_SHADOW_SHADOW086 (86UL) -#define OTP_SHADOW_SHADOW087 (87UL) -#define OTP_SHADOW_SHADOW088 (88UL) -#define OTP_SHADOW_SHADOW089 (89UL) -#define OTP_SHADOW_SHADOW090 (90UL) -#define OTP_SHADOW_SHADOW091 (91UL) -#define OTP_SHADOW_SHADOW092 (92UL) -#define OTP_SHADOW_SHADOW093 (93UL) -#define OTP_SHADOW_SHADOW094 (94UL) -#define OTP_SHADOW_SHADOW095 (95UL) -#define OTP_SHADOW_SHADOW096 (96UL) -#define OTP_SHADOW_SHADOW097 (97UL) -#define OTP_SHADOW_SHADOW098 (98UL) -#define OTP_SHADOW_SHADOW099 (99UL) -#define OTP_SHADOW_SHADOW100 (100UL) -#define OTP_SHADOW_SHADOW101 (101UL) -#define OTP_SHADOW_SHADOW102 (102UL) -#define OTP_SHADOW_SHADOW103 (103UL) -#define OTP_SHADOW_SHADOW104 (104UL) -#define OTP_SHADOW_SHADOW105 (105UL) -#define OTP_SHADOW_SHADOW106 (106UL) -#define OTP_SHADOW_SHADOW107 (107UL) -#define OTP_SHADOW_SHADOW108 (108UL) -#define OTP_SHADOW_SHADOW109 (109UL) -#define OTP_SHADOW_SHADOW110 (110UL) -#define OTP_SHADOW_SHADOW111 (111UL) -#define OTP_SHADOW_SHADOW112 (112UL) -#define OTP_SHADOW_SHADOW113 (113UL) -#define OTP_SHADOW_SHADOW114 (114UL) -#define OTP_SHADOW_SHADOW115 (115UL) -#define OTP_SHADOW_SHADOW116 (116UL) -#define OTP_SHADOW_SHADOW117 (117UL) -#define OTP_SHADOW_SHADOW118 (118UL) -#define OTP_SHADOW_SHADOW119 (119UL) -#define OTP_SHADOW_SHADOW120 (120UL) -#define OTP_SHADOW_SHADOW121 (121UL) -#define OTP_SHADOW_SHADOW122 (122UL) -#define OTP_SHADOW_SHADOW123 (123UL) -#define OTP_SHADOW_SHADOW124 (124UL) -#define OTP_SHADOW_SHADOW125 (125UL) -#define OTP_SHADOW_SHADOW126 (126UL) -#define OTP_SHADOW_SHADOW127 (127UL) - -/* SHADOW_LOCK register group index macro definition */ -#define OTP_SHADOW_LOCK_LOCK00 (0UL) -#define OTP_SHADOW_LOCK_LOCK01 (1UL) -#define OTP_SHADOW_LOCK_LOCK02 (2UL) -#define OTP_SHADOW_LOCK_LOCK03 (3UL) -#define OTP_SHADOW_LOCK_LOCK04 (4UL) -#define OTP_SHADOW_LOCK_LOCK05 (5UL) -#define OTP_SHADOW_LOCK_LOCK06 (6UL) -#define OTP_SHADOW_LOCK_LOCK07 (7UL) - -/* FUSE register group index macro definition */ -#define OTP_FUSE_FUSE000 (0UL) -#define OTP_FUSE_FUSE001 (1UL) -#define OTP_FUSE_FUSE002 (2UL) -#define OTP_FUSE_FUSE003 (3UL) -#define OTP_FUSE_FUSE004 (4UL) -#define OTP_FUSE_FUSE005 (5UL) -#define OTP_FUSE_FUSE006 (6UL) -#define OTP_FUSE_FUSE007 (7UL) -#define OTP_FUSE_FUSE008 (8UL) -#define OTP_FUSE_FUSE009 (9UL) -#define OTP_FUSE_FUSE010 (10UL) -#define OTP_FUSE_FUSE011 (11UL) -#define OTP_FUSE_FUSE012 (12UL) -#define OTP_FUSE_FUSE013 (13UL) -#define OTP_FUSE_FUSE014 (14UL) -#define OTP_FUSE_FUSE015 (15UL) -#define OTP_FUSE_FUSE016 (16UL) -#define OTP_FUSE_FUSE017 (17UL) -#define OTP_FUSE_FUSE018 (18UL) -#define OTP_FUSE_FUSE019 (19UL) -#define OTP_FUSE_FUSE020 (20UL) -#define OTP_FUSE_FUSE021 (21UL) -#define OTP_FUSE_FUSE022 (22UL) -#define OTP_FUSE_FUSE023 (23UL) -#define OTP_FUSE_FUSE024 (24UL) -#define OTP_FUSE_FUSE025 (25UL) -#define OTP_FUSE_FUSE026 (26UL) -#define OTP_FUSE_FUSE027 (27UL) -#define OTP_FUSE_FUSE028 (28UL) -#define OTP_FUSE_FUSE029 (29UL) -#define OTP_FUSE_FUSE030 (30UL) -#define OTP_FUSE_FUSE031 (31UL) -#define OTP_FUSE_FUSE032 (32UL) -#define OTP_FUSE_FUSE033 (33UL) -#define OTP_FUSE_FUSE034 (34UL) -#define OTP_FUSE_FUSE035 (35UL) -#define OTP_FUSE_FUSE036 (36UL) -#define OTP_FUSE_FUSE037 (37UL) -#define OTP_FUSE_FUSE038 (38UL) -#define OTP_FUSE_FUSE039 (39UL) -#define OTP_FUSE_FUSE040 (40UL) -#define OTP_FUSE_FUSE041 (41UL) -#define OTP_FUSE_FUSE042 (42UL) -#define OTP_FUSE_FUSE043 (43UL) -#define OTP_FUSE_FUSE044 (44UL) -#define OTP_FUSE_FUSE045 (45UL) -#define OTP_FUSE_FUSE046 (46UL) -#define OTP_FUSE_FUSE047 (47UL) -#define OTP_FUSE_FUSE048 (48UL) -#define OTP_FUSE_FUSE049 (49UL) -#define OTP_FUSE_FUSE050 (50UL) -#define OTP_FUSE_FUSE051 (51UL) -#define OTP_FUSE_FUSE052 (52UL) -#define OTP_FUSE_FUSE053 (53UL) -#define OTP_FUSE_FUSE054 (54UL) -#define OTP_FUSE_FUSE055 (55UL) -#define OTP_FUSE_FUSE056 (56UL) -#define OTP_FUSE_FUSE057 (57UL) -#define OTP_FUSE_FUSE058 (58UL) -#define OTP_FUSE_FUSE059 (59UL) -#define OTP_FUSE_FUSE060 (60UL) -#define OTP_FUSE_FUSE061 (61UL) -#define OTP_FUSE_FUSE062 (62UL) -#define OTP_FUSE_FUSE063 (63UL) -#define OTP_FUSE_FUSE064 (64UL) -#define OTP_FUSE_FUSE065 (65UL) -#define OTP_FUSE_FUSE066 (66UL) -#define OTP_FUSE_FUSE067 (67UL) -#define OTP_FUSE_FUSE068 (68UL) -#define OTP_FUSE_FUSE069 (69UL) -#define OTP_FUSE_FUSE070 (70UL) -#define OTP_FUSE_FUSE071 (71UL) -#define OTP_FUSE_FUSE072 (72UL) -#define OTP_FUSE_FUSE073 (73UL) -#define OTP_FUSE_FUSE074 (74UL) -#define OTP_FUSE_FUSE075 (75UL) -#define OTP_FUSE_FUSE076 (76UL) -#define OTP_FUSE_FUSE077 (77UL) -#define OTP_FUSE_FUSE078 (78UL) -#define OTP_FUSE_FUSE079 (79UL) -#define OTP_FUSE_FUSE080 (80UL) -#define OTP_FUSE_FUSE081 (81UL) -#define OTP_FUSE_FUSE082 (82UL) -#define OTP_FUSE_FUSE083 (83UL) -#define OTP_FUSE_FUSE084 (84UL) -#define OTP_FUSE_FUSE085 (85UL) -#define OTP_FUSE_FUSE086 (86UL) -#define OTP_FUSE_FUSE087 (87UL) -#define OTP_FUSE_FUSE088 (88UL) -#define OTP_FUSE_FUSE089 (89UL) -#define OTP_FUSE_FUSE090 (90UL) -#define OTP_FUSE_FUSE091 (91UL) -#define OTP_FUSE_FUSE092 (92UL) -#define OTP_FUSE_FUSE093 (93UL) -#define OTP_FUSE_FUSE094 (94UL) -#define OTP_FUSE_FUSE095 (95UL) -#define OTP_FUSE_FUSE096 (96UL) -#define OTP_FUSE_FUSE097 (97UL) -#define OTP_FUSE_FUSE098 (98UL) -#define OTP_FUSE_FUSE099 (99UL) -#define OTP_FUSE_FUSE100 (100UL) -#define OTP_FUSE_FUSE101 (101UL) -#define OTP_FUSE_FUSE102 (102UL) -#define OTP_FUSE_FUSE103 (103UL) -#define OTP_FUSE_FUSE104 (104UL) -#define OTP_FUSE_FUSE105 (105UL) -#define OTP_FUSE_FUSE106 (106UL) -#define OTP_FUSE_FUSE107 (107UL) -#define OTP_FUSE_FUSE108 (108UL) -#define OTP_FUSE_FUSE109 (109UL) -#define OTP_FUSE_FUSE110 (110UL) -#define OTP_FUSE_FUSE111 (111UL) -#define OTP_FUSE_FUSE112 (112UL) -#define OTP_FUSE_FUSE113 (113UL) -#define OTP_FUSE_FUSE114 (114UL) -#define OTP_FUSE_FUSE115 (115UL) -#define OTP_FUSE_FUSE116 (116UL) -#define OTP_FUSE_FUSE117 (117UL) -#define OTP_FUSE_FUSE118 (118UL) -#define OTP_FUSE_FUSE119 (119UL) -#define OTP_FUSE_FUSE120 (120UL) -#define OTP_FUSE_FUSE121 (121UL) -#define OTP_FUSE_FUSE122 (122UL) -#define OTP_FUSE_FUSE123 (123UL) -#define OTP_FUSE_FUSE124 (124UL) -#define OTP_FUSE_FUSE125 (125UL) -#define OTP_FUSE_FUSE126 (126UL) -#define OTP_FUSE_FUSE127 (127UL) - -/* FUSE_LOCK register group index macro definition */ -#define OTP_FUSE_LOCK_LOCK00 (0UL) -#define OTP_FUSE_LOCK_LOCK01 (1UL) -#define OTP_FUSE_LOCK_LOCK02 (2UL) -#define OTP_FUSE_LOCK_LOCK03 (3UL) -#define OTP_FUSE_LOCK_LOCK04 (4UL) -#define OTP_FUSE_LOCK_LOCK05 (5UL) -#define OTP_FUSE_LOCK_LOCK06 (6UL) -#define OTP_FUSE_LOCK_LOCK07 (7UL) - -/* REGION register group index macro definition */ -#define OTP_REGION_LOAD_REGION0 (0UL) -#define OTP_REGION_LOAD_REGION1 (1UL) -#define OTP_REGION_LOAD_REGION2 (2UL) -#define OTP_REGION_LOAD_REGION3 (3UL) - - -#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pcfg_regs.h deleted file mode 100644 index cfc5f1eba37..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pcfg_regs.h +++ /dev/null @@ -1,902 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PCFG_H -#define HPM_PCFG_H - -typedef struct { - __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ - __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ - __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ - __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ - __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ - __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ - __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ - __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ - __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ - __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ - __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ - __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ - __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ - __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ - __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ - __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ - __RW uint32_t DEBUG_STOP; /* 0x50: Debug stop config */ - __R uint8_t RESERVED2[12]; /* 0x54 - 0x5F: Reserved */ - __RW uint32_t RC24M; /* 0x60: RC 24M config */ - __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ - __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ - __R uint32_t STATUS; /* 0x6C: RC 24M track status */ -} PCFG_Type; - - -/* Bitfield definition for register: BANDGAP */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) -#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) -#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) -#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) - -/* - * LOWPOWER_MODE (RW) - * - * Banggap work in low power mode, banggap function limited - * 0: banggap works in normal mode - * 1: banggap works in low power mode - */ -#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) -#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) -#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) -#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Banggap work in power save mode, banggap function normally - * 0: banggap works in high performance mode - * 1: banggap works in power saving mode - */ -#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) -#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) -#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) -#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) - -/* - * VBG_1P0_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) -#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) - -/* - * VBG_P65_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) - -/* - * VBG_P50_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) -#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) -#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) - -/* Bitfield definition for register: LDO1P1 */ -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. - * 700: 700mV - * 720: 720mV - * . . . - * 1320:1320mV - */ -#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) -#define PCFG_LDO1P1_VOLT_SHIFT (0U) -#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) -#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) - -/* Bitfield definition for register: LDO2P5 */ -/* - * READY (RO) - * - * Ready flag, will set 1ms after enabled or voltage change - * 0: LDO is not ready for use - * 1: LDO is ready - */ -#define PCFG_LDO2P5_READY_MASK (0x10000000UL) -#define PCFG_LDO2P5_READY_SHIFT (28U) -#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) -#define PCFG_LDO2P5_ENABLE_SHIFT (16U) -#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) -#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. - * 2125: 2125mV - * 2150: 2150mV - * . . . - * 2900:2900mV - */ -#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) -#define PCFG_LDO2P5_VOLT_SHIFT (0U) -#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) -#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDC is applying new change - * 1: DCDC is ready - */ -#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDC_MODE_READY_SHIFT (28U) -#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDC work mode - * XX0: turn off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDC_MODE_MODE_SHIFT (16U) -#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) -#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) -#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) - -/* - * DISABLE_POWER_LOSS (RW) - * - * disable power loss protection - * 0: power loss protection enabled, DCDC shuts down when power loss - * 1: power loss protection disabled, DCDC try working after power voltage drop - */ -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * output over voltage protection - * 0: protection enabled, DCDC will shut down is output voltage is unexpected high - * 1: protection disabled, DCDC continue to adjust output voltage - */ -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A, - * 1: 1.3A - */ -#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDC_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDC current level, current level is num * 50mA - */ -#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDC_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) -#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) -#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDC_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDC_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) -#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) -#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) -#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) -#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) -#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) -#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) -#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) -#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDC internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) -#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled, - * 1: steping enabled - */ -#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) -#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDC_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDC voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) -#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - */ -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: POWER_TRAP */ -/* - * TRIGGERED (RW) - * - * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. - * 0: low power trap is not triggered - * 1: low power trap triggered - */ -#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) -#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) -#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) -#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) - -/* - * RETENTION (RW) - * - * DCDC enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDC - * 1: reduce DCDC voltage - */ -#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) -#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) -#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) -#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) - -/* - * TRAP (RW) - * - * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered - * 0: trap not enabled, pmic side low power function disabled - * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - */ -#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) -#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) -#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) -#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) - -/* Bitfield definition for register: WAKE_CAUSE */ -/* - * CAUSE (RW) - * - * wake up cause, each bit represents one wake up source, write 1 to clear the register bit - * 0: wake up source is not active during last wakeup - * 1: wake up source is active furing last wakeup - * bit 0: pmic_enable - * bit 1: debug wakeup - * bit 4: fuse interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit11: Security monitor interrupt - * bit12: Security in PMIC event - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit18: BATT Button interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) -#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) -#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: WAKE_MASK */ -/* - * MASK (RW) - * - * mask for wake up sources, each bit represents one wakeup source - * 0: allow source to wake up system - * 1: disallow source to wakeup system - * bit 0: pmic_enable - * bit 1: debug wakeup - * bit 4: fuse interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit11: Security monitor interrupt - * bit12: Security in PMIC event - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit18: BATT Button interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_MASK_MASK_SHIFT (0U) -#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) -#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) - -/* Bitfield definition for register: SCG_CTRL */ -/* - * SCG (RW) - * - * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: reserved - * 10: clock is always off - * 11: clock is always on - * bit0-1: fuse - * bit2-3: sram - * bit4-5: vad - * bit6-7:gpio - * bit8-9:ioc - * bit10-11: timer - * bit12-13:wdog - * bit14-15:uart - * bit16-17:debug - */ -#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) -#define PCFG_SCG_CTRL_SCG_SHIFT (0U) -#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) -#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) - -/* Bitfield definition for register: DEBUG_STOP */ -/* - * CPU1 (RW) - * - * Stop peripheral when CPU1 enter debug mode - * 0: peripheral keep running when CPU1 in debug mode - * 1: peripheral enter debug mode when CPU1 enter debug - */ -#define PCFG_DEBUG_STOP_CPU1_MASK (0x2U) -#define PCFG_DEBUG_STOP_CPU1_SHIFT (1U) -#define PCFG_DEBUG_STOP_CPU1_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU1_SHIFT) & PCFG_DEBUG_STOP_CPU1_MASK) -#define PCFG_DEBUG_STOP_CPU1_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU1_MASK) >> PCFG_DEBUG_STOP_CPU1_SHIFT) - -/* - * CPU0 (RW) - * - * Stop peripheral when CPU0 enter debug mode - * 0: peripheral keep running when CPU0 in debug mode - * 1: peripheral enter debug mode when CPU0 enter debug - */ -#define PCFG_DEBUG_STOP_CPU0_MASK (0x1U) -#define PCFG_DEBUG_STOP_CPU0_SHIFT (0U) -#define PCFG_DEBUG_STOP_CPU0_SET(x) (((uint32_t)(x) << PCFG_DEBUG_STOP_CPU0_SHIFT) & PCFG_DEBUG_STOP_CPU0_MASK) -#define PCFG_DEBUG_STOP_CPU0_GET(x) (((uint32_t)(x) & PCFG_DEBUG_STOP_CPU0_MASK) >> PCFG_DEBUG_STOP_CPU0_SHIFT) - -/* Bitfield definition for register: RC24M */ -/* - * RC_TRIMMED (RW) - * - * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: RC is not trimmed - * 1: RC is trimmed - */ -#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) -#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) -#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) -#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) - -/* - * TRIM_C (RW) - * - * Coarse trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_C_MASK (0x700U) -#define PCFG_RC24M_TRIM_C_SHIFT (8U) -#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) -#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) - -/* - * TRIM_F (RW) - * - * Fine trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_F_MASK (0x1FU) -#define PCFG_RC24M_TRIM_F_SHIFT (0U) -#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) -#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) - -/* Bitfield definition for register: RC24M_TRACK */ -/* - * SEL24M (RW) - * - * Select track reference - * 0: select 32K as reference - * 1: select 24M XTAL as reference - */ -#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) -#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) -#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) -#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) - -/* - * RETURN (RW) - * - * Retrun default value when XTAL loss - * 0: remain last tracking value - * 1: switch to default value - */ -#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) -#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) -#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) -#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) - -/* - * TRACK (RW) - * - * track mode - * 0: RC24M free running - * 1: track RC24M to external XTAL - */ -#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) -#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) -#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) -#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) - -/* Bitfield definition for register: TRACK_TARGET */ -/* - * PRE_DIV (RW) - * - * Divider for reference source - */ -#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) -#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) -#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) -#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) - -/* - * TARGET (RW) - * - * Target frequency multiplier of divided source - */ -#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) -#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) -#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) -#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * SEL32K (RO) - * - * track is using XTAL32K - * 0: track is not using XTAL32K - * 1: track is using XTAL32K - */ -#define PCFG_STATUS_SEL32K_MASK (0x100000UL) -#define PCFG_STATUS_SEL32K_SHIFT (20U) -#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) - -/* - * SEL24M (RO) - * - * track is using XTAL24M - * 0: track is not using XTAL24M - * 1: track is using XTAL24M - */ -#define PCFG_STATUS_SEL24M_MASK (0x10000UL) -#define PCFG_STATUS_SEL24M_SHIFT (16U) -#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) - -/* - * EN_TRIM (RO) - * - * default value takes effect - * 0: default value is invalid - * 1: default value is valid - */ -#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) -#define PCFG_STATUS_EN_TRIM_SHIFT (15U) -#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) - -/* - * TRIM_C (RO) - * - * default coarse trim value - */ -#define PCFG_STATUS_TRIM_C_MASK (0x700U) -#define PCFG_STATUS_TRIM_C_SHIFT (8U) -#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) - -/* - * TRIM_F (RO) - * - * default fine trim value - */ -#define PCFG_STATUS_TRIM_F_MASK (0x1FU) -#define PCFG_STATUS_TRIM_F_SHIFT (0U) -#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) - - - - -#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pdm_regs.h deleted file mode 100644 index 94b550e0ee2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pdm_regs.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDM_H -#define HPM_PDM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t CH_CTRL; /* 0x4: Channel Control Register */ - __W uint32_t ST; /* 0x8: Status Register */ - __RW uint32_t CH_CFG; /* 0xC: Channel Configuration Register */ - __RW uint32_t CIC_CFG; /* 0x10: CIC configuration register */ - __RW uint32_t CTRL_INBUF; /* 0x14: In Buf Control Register */ - __RW uint32_t CTRL_FILT0; /* 0x18: Filter 0 Control Register */ - __RW uint32_t CTRL_FILT1; /* 0x1C: Filter 1 Control Register */ - __RW uint32_t RUN; /* 0x20: Run Register */ - __RW uint32_t MEMADDR; /* 0x24: Memory Access Address */ - __RW uint32_t MEMDATA; /* 0x28: Memory Access Data */ - __RW uint32_t HPF_MA; /* 0x2C: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x30: HPF B Coef Register */ -} PDM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module. Self-clear. - */ -#define PDM_CTRL_SFTRST_MASK (0x80000000UL) -#define PDM_CTRL_SFTRST_SHIFT (31U) -#define PDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PDM_CTRL_SFTRST_SHIFT) & PDM_CTRL_SFTRST_MASK) -#define PDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PDM_CTRL_SFTRST_MASK) >> PDM_CTRL_SFTRST_SHIFT) - -/* - * SOF_FEDGE (RW) - * - * asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - */ -#define PDM_CTRL_SOF_FEDGE_MASK (0x800000UL) -#define PDM_CTRL_SOF_FEDGE_SHIFT (23U) -#define PDM_CTRL_SOF_FEDGE_SET(x) (((uint32_t)(x) << PDM_CTRL_SOF_FEDGE_SHIFT) & PDM_CTRL_SOF_FEDGE_MASK) -#define PDM_CTRL_SOF_FEDGE_GET(x) (((uint32_t)(x) & PDM_CTRL_SOF_FEDGE_MASK) >> PDM_CTRL_SOF_FEDGE_SHIFT) - -/* - * USE_COEF_RAM (RW) - * - * Asserted to use Coef RAM instead of Coef ROM - */ -#define PDM_CTRL_USE_COEF_RAM_MASK (0x100000UL) -#define PDM_CTRL_USE_COEF_RAM_SHIFT (20U) -#define PDM_CTRL_USE_COEF_RAM_SET(x) (((uint32_t)(x) << PDM_CTRL_USE_COEF_RAM_SHIFT) & PDM_CTRL_USE_COEF_RAM_MASK) -#define PDM_CTRL_USE_COEF_RAM_GET(x) (((uint32_t)(x) & PDM_CTRL_USE_COEF_RAM_MASK) >> PDM_CTRL_USE_COEF_RAM_SHIFT) - -/* - * FILT_CRX_ERR_IE (RW) - * - * data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - */ -#define PDM_CTRL_FILT_CRX_ERR_IE_MASK (0x80000UL) -#define PDM_CTRL_FILT_CRX_ERR_IE_SHIFT (19U) -#define PDM_CTRL_FILT_CRX_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) -#define PDM_CTRL_FILT_CRX_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) >> PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) - -/* - * OFIFO_OVFL_ERR_IE (RW) - * - * output fifo overflow error interrupt enable - */ -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x40000UL) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (18U) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) - -/* - * CIC_OVLD_ERR_IE (RW) - * - * CIC overload error interrupt enable - */ -#define PDM_CTRL_CIC_OVLD_ERR_IE_MASK (0x20000UL) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT (17U) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) -#define PDM_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) >> PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) - -/* - * CIC_SAT_ERR_IE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define PDM_CTRL_CIC_SAT_ERR_IE_MASK (0x10000UL) -#define PDM_CTRL_CIC_SAT_ERR_IE_SHIFT (16U) -#define PDM_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) -#define PDM_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) >> PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) - -/* - * DEC_AFT_CIC (RW) - * - * decimation rate after CIC. Now it is forced to be 3. - */ -#define PDM_CTRL_DEC_AFT_CIC_MASK (0xF000U) -#define PDM_CTRL_DEC_AFT_CIC_SHIFT (12U) -#define PDM_CTRL_DEC_AFT_CIC_SET(x) (((uint32_t)(x) << PDM_CTRL_DEC_AFT_CIC_SHIFT) & PDM_CTRL_DEC_AFT_CIC_MASK) -#define PDM_CTRL_DEC_AFT_CIC_GET(x) (((uint32_t)(x) & PDM_CTRL_DEC_AFT_CIC_MASK) >> PDM_CTRL_DEC_AFT_CIC_SHIFT) - -/* - * CAPT_DLY (RW) - * - * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - */ -#define PDM_CTRL_CAPT_DLY_MASK (0x780U) -#define PDM_CTRL_CAPT_DLY_SHIFT (7U) -#define PDM_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << PDM_CTRL_CAPT_DLY_SHIFT) & PDM_CTRL_CAPT_DLY_MASK) -#define PDM_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & PDM_CTRL_CAPT_DLY_MASK) >> PDM_CTRL_CAPT_DLY_SHIFT) - -/* - * PDM_CLK_HFDIV (RW) - * - * The clock divider will work at least 4. - * 0: div-by-2, - * 1: div-by-4 - * . . . - * n: div-by-2*(n+1) - */ -#define PDM_CTRL_PDM_CLK_HFDIV_MASK (0x78U) -#define PDM_CTRL_PDM_CLK_HFDIV_SHIFT (3U) -#define PDM_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_HFDIV_SHIFT) & PDM_CTRL_PDM_CLK_HFDIV_MASK) -#define PDM_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_HFDIV_MASK) >> PDM_CTRL_PDM_CLK_HFDIV_SHIFT) - -/* - * PDM_CLK_DIV_BYPASS (RW) - * - * asserted to bypass the pdm clock divider - */ -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x4U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (2U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) - -/* - * PDM_CLK_OE (RW) - * - * pdm_clk_output_en - */ -#define PDM_CTRL_PDM_CLK_OE_MASK (0x2U) -#define PDM_CTRL_PDM_CLK_OE_SHIFT (1U) -#define PDM_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_OE_SHIFT) & PDM_CTRL_PDM_CLK_OE_MASK) -#define PDM_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_OE_MASK) >> PDM_CTRL_PDM_CLK_OE_SHIFT) - -/* - * HPF_EN (RW) - * - * pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - */ -#define PDM_CTRL_HPF_EN_MASK (0x1U) -#define PDM_CTRL_HPF_EN_SHIFT (0U) -#define PDM_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << PDM_CTRL_HPF_EN_SHIFT) & PDM_CTRL_HPF_EN_MASK) -#define PDM_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & PDM_CTRL_HPF_EN_MASK) >> PDM_CTRL_HPF_EN_SHIFT) - -/* Bitfield definition for register: CH_CTRL */ -/* - * CH_POL (RW) - * - * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - */ -#define PDM_CH_CTRL_CH_POL_MASK (0xFF0000UL) -#define PDM_CH_CTRL_CH_POL_SHIFT (16U) -#define PDM_CH_CTRL_CH_POL_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_POL_SHIFT) & PDM_CH_CTRL_CH_POL_MASK) -#define PDM_CH_CTRL_CH_POL_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_POL_MASK) >> PDM_CH_CTRL_CH_POL_SHIFT) - -/* - * CH_EN (RW) - * - * Asserted to enable the channel. - * Ch8 & 9 are refs. - * Ch0-7 are pdm mics. - */ -#define PDM_CH_CTRL_CH_EN_MASK (0x3FFU) -#define PDM_CH_CTRL_CH_EN_SHIFT (0U) -#define PDM_CH_CTRL_CH_EN_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_EN_SHIFT) & PDM_CH_CTRL_CH_EN_MASK) -#define PDM_CH_CTRL_CH_EN_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_EN_MASK) >> PDM_CH_CTRL_CH_EN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * FILT_CRX_ERR (W1C) - * - * data accessed out of boundary error - */ -#define PDM_ST_FILT_CRX_ERR_MASK (0x8U) -#define PDM_ST_FILT_CRX_ERR_SHIFT (3U) -#define PDM_ST_FILT_CRX_ERR_SET(x) (((uint32_t)(x) << PDM_ST_FILT_CRX_ERR_SHIFT) & PDM_ST_FILT_CRX_ERR_MASK) -#define PDM_ST_FILT_CRX_ERR_GET(x) (((uint32_t)(x) & PDM_ST_FILT_CRX_ERR_MASK) >> PDM_ST_FILT_CRX_ERR_SHIFT) - -/* - * OFIFO_OVFL_ERR (W1C) - * - * output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - */ -#define PDM_ST_OFIFO_OVFL_ERR_MASK (0x4U) -#define PDM_ST_OFIFO_OVFL_ERR_SHIFT (2U) -#define PDM_ST_OFIFO_OVFL_ERR_SET(x) (((uint32_t)(x) << PDM_ST_OFIFO_OVFL_ERR_SHIFT) & PDM_ST_OFIFO_OVFL_ERR_MASK) -#define PDM_ST_OFIFO_OVFL_ERR_GET(x) (((uint32_t)(x) & PDM_ST_OFIFO_OVFL_ERR_MASK) >> PDM_ST_OFIFO_OVFL_ERR_SHIFT) - -/* - * CIC_OVLD_ERR (W1C) - * - * CIC overload error. write 1 clear - */ -#define PDM_ST_CIC_OVLD_ERR_MASK (0x2U) -#define PDM_ST_CIC_OVLD_ERR_SHIFT (1U) -#define PDM_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_OVLD_ERR_SHIFT) & PDM_ST_CIC_OVLD_ERR_MASK) -#define PDM_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_OVLD_ERR_MASK) >> PDM_ST_CIC_OVLD_ERR_SHIFT) - -/* - * CIC_SAT_ERR (W1C) - * - * CIC saturation. Write 1 clear - */ -#define PDM_ST_CIC_SAT_ERR_MASK (0x1U) -#define PDM_ST_CIC_SAT_ERR_SHIFT (0U) -#define PDM_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_SAT_ERR_SHIFT) & PDM_ST_CIC_SAT_ERR_MASK) -#define PDM_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_SAT_ERR_MASK) >> PDM_ST_CIC_SAT_ERR_SHIFT) - -/* Bitfield definition for register: CH_CFG */ -/* - * CH9_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH9_TYPE_MASK (0xC0000UL) -#define PDM_CH_CFG_CH9_TYPE_SHIFT (18U) -#define PDM_CH_CFG_CH9_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH9_TYPE_SHIFT) & PDM_CH_CFG_CH9_TYPE_MASK) -#define PDM_CH_CFG_CH9_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH9_TYPE_MASK) >> PDM_CH_CFG_CH9_TYPE_SHIFT) - -/* - * CH8_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH8_TYPE_MASK (0x30000UL) -#define PDM_CH_CFG_CH8_TYPE_SHIFT (16U) -#define PDM_CH_CFG_CH8_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH8_TYPE_SHIFT) & PDM_CH_CFG_CH8_TYPE_MASK) -#define PDM_CH_CFG_CH8_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH8_TYPE_MASK) >> PDM_CH_CFG_CH8_TYPE_SHIFT) - -/* - * CH7_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH7_TYPE_MASK (0xC000U) -#define PDM_CH_CFG_CH7_TYPE_SHIFT (14U) -#define PDM_CH_CFG_CH7_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH7_TYPE_SHIFT) & PDM_CH_CFG_CH7_TYPE_MASK) -#define PDM_CH_CFG_CH7_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH7_TYPE_MASK) >> PDM_CH_CFG_CH7_TYPE_SHIFT) - -/* - * CH6_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH6_TYPE_MASK (0x3000U) -#define PDM_CH_CFG_CH6_TYPE_SHIFT (12U) -#define PDM_CH_CFG_CH6_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH6_TYPE_SHIFT) & PDM_CH_CFG_CH6_TYPE_MASK) -#define PDM_CH_CFG_CH6_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH6_TYPE_MASK) >> PDM_CH_CFG_CH6_TYPE_SHIFT) - -/* - * CH5_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH5_TYPE_MASK (0xC00U) -#define PDM_CH_CFG_CH5_TYPE_SHIFT (10U) -#define PDM_CH_CFG_CH5_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH5_TYPE_SHIFT) & PDM_CH_CFG_CH5_TYPE_MASK) -#define PDM_CH_CFG_CH5_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH5_TYPE_MASK) >> PDM_CH_CFG_CH5_TYPE_SHIFT) - -/* - * CH4_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH4_TYPE_MASK (0x300U) -#define PDM_CH_CFG_CH4_TYPE_SHIFT (8U) -#define PDM_CH_CFG_CH4_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH4_TYPE_SHIFT) & PDM_CH_CFG_CH4_TYPE_MASK) -#define PDM_CH_CFG_CH4_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH4_TYPE_MASK) >> PDM_CH_CFG_CH4_TYPE_SHIFT) - -/* - * CH3_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH3_TYPE_MASK (0xC0U) -#define PDM_CH_CFG_CH3_TYPE_SHIFT (6U) -#define PDM_CH_CFG_CH3_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH3_TYPE_SHIFT) & PDM_CH_CFG_CH3_TYPE_MASK) -#define PDM_CH_CFG_CH3_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH3_TYPE_MASK) >> PDM_CH_CFG_CH3_TYPE_SHIFT) - -/* - * CH2_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH2_TYPE_MASK (0x30U) -#define PDM_CH_CFG_CH2_TYPE_SHIFT (4U) -#define PDM_CH_CFG_CH2_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH2_TYPE_SHIFT) & PDM_CH_CFG_CH2_TYPE_MASK) -#define PDM_CH_CFG_CH2_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH2_TYPE_MASK) >> PDM_CH_CFG_CH2_TYPE_SHIFT) - -/* - * CH1_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH1_TYPE_MASK (0xCU) -#define PDM_CH_CFG_CH1_TYPE_SHIFT (2U) -#define PDM_CH_CFG_CH1_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH1_TYPE_SHIFT) & PDM_CH_CFG_CH1_TYPE_MASK) -#define PDM_CH_CFG_CH1_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH1_TYPE_MASK) >> PDM_CH_CFG_CH1_TYPE_SHIFT) - -/* - * CH0_TYPE (RW) - * - * Type of Channel 0 - * 2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) - * 2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - */ -#define PDM_CH_CFG_CH0_TYPE_MASK (0x3U) -#define PDM_CH_CFG_CH0_TYPE_SHIFT (0U) -#define PDM_CH_CFG_CH0_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH0_TYPE_SHIFT) & PDM_CH_CFG_CH0_TYPE_MASK) -#define PDM_CH_CFG_CH0_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH0_TYPE_MASK) >> PDM_CH_CFG_CH0_TYPE_SHIFT) - -/* Bitfield definition for register: CIC_CFG */ -/* - * POST_SCALE (RW) - * - * the shift value after CIC results. - */ -#define PDM_CIC_CFG_POST_SCALE_MASK (0xFC00U) -#define PDM_CIC_CFG_POST_SCALE_SHIFT (10U) -#define PDM_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_POST_SCALE_SHIFT) & PDM_CIC_CFG_POST_SCALE_MASK) -#define PDM_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_POST_SCALE_MASK) >> PDM_CIC_CFG_POST_SCALE_SHIFT) - -/* - * SGD (RW) - * - * Sigma_delta_order[1:0] - * 2'b00: 7 - * 2'b01: 6 - * 2'b10: 5 - * Others: unused - */ -#define PDM_CIC_CFG_SGD_MASK (0x300U) -#define PDM_CIC_CFG_SGD_SHIFT (8U) -#define PDM_CIC_CFG_SGD_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_SGD_SHIFT) & PDM_CIC_CFG_SGD_MASK) -#define PDM_CIC_CFG_SGD_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_SGD_MASK) >> PDM_CIC_CFG_SGD_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation factor - */ -#define PDM_CIC_CFG_CIC_DEC_RATIO_MASK (0xFFU) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT (0U) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) -#define PDM_CIC_CFG_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) >> PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) - -/* Bitfield definition for register: CTRL_INBUF */ -/* - * MAX_PTR (RW) - * - * The buf size-1 for each channel - */ -#define PDM_CTRL_INBUF_MAX_PTR_MASK (0x3FC00000UL) -#define PDM_CTRL_INBUF_MAX_PTR_SHIFT (22U) -#define PDM_CTRL_INBUF_MAX_PTR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_MAX_PTR_SHIFT) & PDM_CTRL_INBUF_MAX_PTR_MASK) -#define PDM_CTRL_INBUF_MAX_PTR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_MAX_PTR_MASK) >> PDM_CTRL_INBUF_MAX_PTR_SHIFT) - -/* - * PITCH (RW) - * - * The spacing between starting address of adjacent channels - */ -#define PDM_CTRL_INBUF_PITCH_MASK (0x3FF800UL) -#define PDM_CTRL_INBUF_PITCH_SHIFT (11U) -#define PDM_CTRL_INBUF_PITCH_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_PITCH_SHIFT) & PDM_CTRL_INBUF_PITCH_MASK) -#define PDM_CTRL_INBUF_PITCH_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_PITCH_MASK) >> PDM_CTRL_INBUF_PITCH_SHIFT) - -/* - * START_ADDR (RW) - * - * The starting address of channel 0 in filter data buffer - */ -#define PDM_CTRL_INBUF_START_ADDR_MASK (0x7FFU) -#define PDM_CTRL_INBUF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_INBUF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_START_ADDR_SHIFT) & PDM_CTRL_INBUF_START_ADDR_MASK) -#define PDM_CTRL_INBUF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_START_ADDR_MASK) >> PDM_CTRL_INBUF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT0 */ -/* - * COEF_LEN_M0 (RW) - * - * Coef length of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_LEN_M0_MASK (0xFF00U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT (8U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) -#define PDM_CTRL_FILT0_COEF_LEN_M0_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) >> PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT0_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT1 */ -/* - * COEF_LEN_M1 (RW) - * - * Coef length of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_LEN_M1_MASK (0xFF00U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT (8U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) -#define PDM_CTRL_FILT1_COEF_LEN_M1_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) >> PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT1_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: RUN */ -/* - * PDM_EN (RW) - * - * Asserted to enable the module - */ -#define PDM_RUN_PDM_EN_MASK (0x1U) -#define PDM_RUN_PDM_EN_SHIFT (0U) -#define PDM_RUN_PDM_EN_SET(x) (((uint32_t)(x) << PDM_RUN_PDM_EN_SHIFT) & PDM_RUN_PDM_EN_MASK) -#define PDM_RUN_PDM_EN_GET(x) (((uint32_t)(x) & PDM_RUN_PDM_EN_MASK) >> PDM_RUN_PDM_EN_SHIFT) - -/* Bitfield definition for register: MEMADDR */ -/* - * ADDR (RW) - * - * 0--0x0FFFFFFF: COEF_RAM - * 0x10000000--0x1FFFFFFF: DATA_RAM - */ -#define PDM_MEMADDR_ADDR_MASK (0xFFFFFFFFUL) -#define PDM_MEMADDR_ADDR_SHIFT (0U) -#define PDM_MEMADDR_ADDR_SET(x) (((uint32_t)(x) << PDM_MEMADDR_ADDR_SHIFT) & PDM_MEMADDR_ADDR_MASK) -#define PDM_MEMADDR_ADDR_GET(x) (((uint32_t)(x) & PDM_MEMADDR_ADDR_MASK) >> PDM_MEMADDR_ADDR_SHIFT) - -/* Bitfield definition for register: MEMDATA */ -/* - * DATA (RW) - * - * The data write-to/read-from buffer - */ -#define PDM_MEMDATA_DATA_MASK (0xFFFFFFFFUL) -#define PDM_MEMDATA_DATA_SHIFT (0U) -#define PDM_MEMDATA_DATA_SET(x) (((uint32_t)(x) << PDM_MEMDATA_DATA_SHIFT) & PDM_MEMDATA_DATA_MASK) -#define PDM_MEMDATA_DATA_GET(x) (((uint32_t)(x) & PDM_MEMDATA_DATA_MASK) >> PDM_MEMDATA_DATA_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define PDM_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_MA_COEF_SHIFT (0U) -#define PDM_HPF_MA_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_MA_COEF_SHIFT) & PDM_HPF_MA_COEF_MASK) -#define PDM_HPF_MA_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_MA_COEF_MASK) >> PDM_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define PDM_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_B_COEF_SHIFT (0U) -#define PDM_HPF_B_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_B_COEF_SHIFT) & PDM_HPF_B_COEF_MASK) -#define PDM_HPF_B_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_B_COEF_MASK) >> PDM_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_PDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pdma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pdma_regs.h deleted file mode 100644 index 10808f85cea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pdma_regs.h +++ /dev/null @@ -1,912 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDMA_H -#define HPM_PDMA_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t STAT; /* 0x4: Status Register */ - __RW uint32_t OUT_CTRL; /* 0x8: Out Layer Control Register */ - __RW uint32_t OUT_BUF; /* 0xC: Output buffer address */ - __R uint8_t RESERVED0[4]; /* 0x10 - 0x13: Reserved */ - __RW uint32_t OUT_PITCH; /* 0x14: Outlayer Pitch Register */ - __RW uint32_t OUT_LRC; /* 0x18: Output Lower Right Corner Register */ - struct { - __RW uint32_t ULC; /* 0x1C: Layer Upper Left Corner Register */ - __RW uint32_t LRC; /* 0x20: Layer Lower Right Corner Register */ - } OUT_PS[2]; - __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x30: Layer Control Register */ - __RW uint32_t BUF; /* 0x34: Layer data buffer address */ - __R uint8_t RESERVED0[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t PITCH; /* 0x40: Layer data pitch register */ - __RW uint32_t BKGD; /* 0x44: Layer background color register */ - __RW uint32_t SCALE; /* 0x48: Layer scale register */ - __RW uint32_t OFFSET; /* 0x4C: Layer offset register */ - __RW uint32_t CLRKEY_LOW; /* 0x50: Layer low color key register */ - __RW uint32_t CLRKEY_HIGH; /* 0x54: Layer high color key register */ - __RW uint32_t ORG; /* 0x58: Layer original size register */ - __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ - } PS[2]; - __R uint8_t RESERVED2[16]; /* 0x90 - 0x9F: Reserved */ - __RW uint32_t YUV2RGB_COEF0; /* 0xA0: YUV2RGB coefficients register 0 */ - __RW uint32_t YUV2RGB_COEF1; /* 0xA4: YUV2RGB coefficients register 1 */ - __RW uint32_t YUV2RGB_COEF2; /* 0xA8: YUV2RGB coefficients register 2 */ - __RW uint32_t RGB2YUV_COEF0; /* 0xAC: RGB2YUV coefficients register 0 */ - __RW uint32_t RGB2YUV_COEF1; /* 0xB0: RGB2YUV coefficients register 1 */ - __RW uint32_t RGB2YUV_COEF2; /* 0xB4: RGB2YUV coefficients register 2 */ - __RW uint32_t RGB2YUV_COEF3; /* 0xB8: RGB2YUV coefficients register 3 */ - __RW uint32_t RGB2YUV_COEF4; /* 0xBC: RGB2YUV coefficients register 4 */ -} PDMA_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * ARQOS (RW) - * - * QoS for AXI read bus - */ -#define PDMA_CTRL_ARQOS_MASK (0x780000UL) -#define PDMA_CTRL_ARQOS_SHIFT (19U) -#define PDMA_CTRL_ARQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_ARQOS_SHIFT) & PDMA_CTRL_ARQOS_MASK) -#define PDMA_CTRL_ARQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_ARQOS_MASK) >> PDMA_CTRL_ARQOS_SHIFT) - -/* - * AWQOS (RW) - * - * QoS for AXI write bus - */ -#define PDMA_CTRL_AWQOS_MASK (0x78000UL) -#define PDMA_CTRL_AWQOS_SHIFT (15U) -#define PDMA_CTRL_AWQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_AWQOS_SHIFT) & PDMA_CTRL_AWQOS_MASK) -#define PDMA_CTRL_AWQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_AWQOS_MASK) >> PDMA_CTRL_AWQOS_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. - * 2'b00: no change {A3, A2, A1, A0} - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define PDMA_CTRL_PACK_DIR_MASK (0x6000U) -#define PDMA_CTRL_PACK_DIR_SHIFT (13U) -#define PDMA_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_CTRL_PACK_DIR_SHIFT) & PDMA_CTRL_PACK_DIR_MASK) -#define PDMA_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_CTRL_PACK_DIR_MASK) >> PDMA_CTRL_PACK_DIR_SHIFT) - -/* - * AXIERR_IRQ_EN (RW) - * - * Enable interrupt of AXI bus error - */ -#define PDMA_CTRL_AXIERR_IRQ_EN_MASK (0x1000U) -#define PDMA_CTRL_AXIERR_IRQ_EN_SHIFT (12U) -#define PDMA_CTRL_AXIERR_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) -#define PDMA_CTRL_AXIERR_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) >> PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) - -/* - * PDMA_DONE_IRQ_EN (RW) - * - * Enable interrupt of PDMA_DONE - */ -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK (0x800U) -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT (11U) -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) >> PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) - -/* - * CLKGATE (RW) - * - * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - */ -#define PDMA_CTRL_CLKGATE_MASK (0x200U) -#define PDMA_CTRL_CLKGATE_SHIFT (9U) -#define PDMA_CTRL_CLKGATE_SET(x) (((uint32_t)(x) << PDMA_CTRL_CLKGATE_SHIFT) & PDMA_CTRL_CLKGATE_MASK) -#define PDMA_CTRL_CLKGATE_GET(x) (((uint32_t)(x) & PDMA_CTRL_CLKGATE_MASK) >> PDMA_CTRL_CLKGATE_SHIFT) - -/* - * IRQ_EN (RW) - * - * Enable normal interrupt - */ -#define PDMA_CTRL_IRQ_EN_MASK (0x40U) -#define PDMA_CTRL_IRQ_EN_SHIFT (6U) -#define PDMA_CTRL_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_IRQ_EN_SHIFT) & PDMA_CTRL_IRQ_EN_MASK) -#define PDMA_CTRL_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_IRQ_EN_MASK) >> PDMA_CTRL_IRQ_EN_SHIFT) - -/* - * BS16 (RW) - * - * Asserted when the Block Size is 16x16, else 8x8 - */ -#define PDMA_CTRL_BS16_MASK (0x20U) -#define PDMA_CTRL_BS16_SHIFT (5U) -#define PDMA_CTRL_BS16_SET(x) (((uint32_t)(x) << PDMA_CTRL_BS16_SHIFT) & PDMA_CTRL_BS16_MASK) -#define PDMA_CTRL_BS16_GET(x) (((uint32_t)(x) & PDMA_CTRL_BS16_MASK) >> PDMA_CTRL_BS16_SHIFT) - -/* - * P1_EN (RW) - * - * Plane 1 Enable - */ -#define PDMA_CTRL_P1_EN_MASK (0x10U) -#define PDMA_CTRL_P1_EN_SHIFT (4U) -#define PDMA_CTRL_P1_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P1_EN_SHIFT) & PDMA_CTRL_P1_EN_MASK) -#define PDMA_CTRL_P1_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P1_EN_MASK) >> PDMA_CTRL_P1_EN_SHIFT) - -/* - * P0_EN (RW) - * - * Plane 0 Enable - */ -#define PDMA_CTRL_P0_EN_MASK (0x8U) -#define PDMA_CTRL_P0_EN_SHIFT (3U) -#define PDMA_CTRL_P0_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P0_EN_SHIFT) & PDMA_CTRL_P0_EN_MASK) -#define PDMA_CTRL_P0_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P0_EN_MASK) >> PDMA_CTRL_P0_EN_SHIFT) - -/* - * PDMA_SFTRST (RW) - * - * Software Reset. - * Write 1 to clear PDMA internal logic. - * Write 0 to exit software reset mode. - */ -#define PDMA_CTRL_PDMA_SFTRST_MASK (0x2U) -#define PDMA_CTRL_PDMA_SFTRST_SHIFT (1U) -#define PDMA_CTRL_PDMA_SFTRST_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_SFTRST_SHIFT) & PDMA_CTRL_PDMA_SFTRST_MASK) -#define PDMA_CTRL_PDMA_SFTRST_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_SFTRST_MASK) >> PDMA_CTRL_PDMA_SFTRST_SHIFT) - -/* - * PDMA_EN (RW) - * - * 1b - Enabled - */ -#define PDMA_CTRL_PDMA_EN_MASK (0x1U) -#define PDMA_CTRL_PDMA_EN_SHIFT (0U) -#define PDMA_CTRL_PDMA_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_EN_SHIFT) & PDMA_CTRL_PDMA_EN_MASK) -#define PDMA_CTRL_PDMA_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_EN_MASK) >> PDMA_CTRL_PDMA_EN_SHIFT) - -/* Bitfield definition for register: STAT */ -/* - * BLOCKY (RO) - * - * Y block that is processing - */ -#define PDMA_STAT_BLOCKY_MASK (0xFF000000UL) -#define PDMA_STAT_BLOCKY_SHIFT (24U) -#define PDMA_STAT_BLOCKY_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKY_MASK) >> PDMA_STAT_BLOCKY_SHIFT) - -/* - * BLOCKX (RO) - * - * X block that is processing - */ -#define PDMA_STAT_BLOCKX_MASK (0xFF0000UL) -#define PDMA_STAT_BLOCKX_SHIFT (16U) -#define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) - -/* - * PDMA_DONE (W1C) - * - * PDMA one image done - */ -#define PDMA_STAT_PDMA_DONE_MASK (0x200U) -#define PDMA_STAT_PDMA_DONE_SHIFT (9U) -#define PDMA_STAT_PDMA_DONE_SET(x) (((uint32_t)(x) << PDMA_STAT_PDMA_DONE_SHIFT) & PDMA_STAT_PDMA_DONE_MASK) -#define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) - -/* - * AXI_ERR_ID (RO) - * - * AXI error ID - */ -#define PDMA_STAT_AXI_ERR_ID_MASK (0x1E0U) -#define PDMA_STAT_AXI_ERR_ID_SHIFT (5U) -#define PDMA_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_ERR_ID_MASK) >> PDMA_STAT_AXI_ERR_ID_SHIFT) - -/* - * AXI_0_WRITE_ERR (W1C) - * - * AXI0 write err - */ -#define PDMA_STAT_AXI_0_WRITE_ERR_MASK (0x10U) -#define PDMA_STAT_AXI_0_WRITE_ERR_SHIFT (4U) -#define PDMA_STAT_AXI_0_WRITE_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) -#define PDMA_STAT_AXI_0_WRITE_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) >> PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) - -/* - * AXI_1_READ_ERR (W1C) - * - * AXI1 read err - */ -#define PDMA_STAT_AXI_1_READ_ERR_MASK (0x8U) -#define PDMA_STAT_AXI_1_READ_ERR_SHIFT (3U) -#define PDMA_STAT_AXI_1_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_1_READ_ERR_SHIFT) & PDMA_STAT_AXI_1_READ_ERR_MASK) -#define PDMA_STAT_AXI_1_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_1_READ_ERR_MASK) >> PDMA_STAT_AXI_1_READ_ERR_SHIFT) - -/* - * AXI_0_READ_ERR (W1C) - * - * AXI0 read err - */ -#define PDMA_STAT_AXI_0_READ_ERR_MASK (0x4U) -#define PDMA_STAT_AXI_0_READ_ERR_SHIFT (2U) -#define PDMA_STAT_AXI_0_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_READ_ERR_SHIFT) & PDMA_STAT_AXI_0_READ_ERR_MASK) -#define PDMA_STAT_AXI_0_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_READ_ERR_MASK) >> PDMA_STAT_AXI_0_READ_ERR_SHIFT) - -/* - * IRQ (RO) - * - * Asserted to indicate a IRQ event - */ -#define PDMA_STAT_IRQ_MASK (0x1U) -#define PDMA_STAT_IRQ_SHIFT (0U) -#define PDMA_STAT_IRQ_GET(x) (((uint32_t)(x) & PDMA_STAT_IRQ_MASK) >> PDMA_STAT_IRQ_SHIFT) - -/* Bitfield definition for register: OUT_CTRL */ -/* - * DSTALPHA (RW) - * - * The destination (P1) system ALPHA value. - */ -#define PDMA_OUT_CTRL_DSTALPHA_MASK (0xFF000000UL) -#define PDMA_OUT_CTRL_DSTALPHA_SHIFT (24U) -#define PDMA_OUT_CTRL_DSTALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_MASK) -#define PDMA_OUT_CTRL_DSTALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_MASK) >> PDMA_OUT_CTRL_DSTALPHA_SHIFT) - -/* - * SRCALPHA (RW) - * - * The source (P0) system ALPHA value. - */ -#define PDMA_OUT_CTRL_SRCALPHA_MASK (0xFF0000UL) -#define PDMA_OUT_CTRL_SRCALPHA_SHIFT (16U) -#define PDMA_OUT_CTRL_SRCALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_MASK) -#define PDMA_OUT_CTRL_SRCALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_MASK) >> PDMA_OUT_CTRL_SRCALPHA_SHIFT) - -/* - * DSTALPHA_OP (RW) - * - * The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream - * 1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) - * 2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream - * Others: Reserved - */ -#define PDMA_OUT_CTRL_DSTALPHA_OP_MASK (0xC000U) -#define PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT (14U) -#define PDMA_OUT_CTRL_DSTALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) -#define PDMA_OUT_CTRL_DSTALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) >> PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) - -/* - * SRCALPHA_OP (RW) - * - * The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream - * 1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) - * 2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream - * Others: Reserved - */ -#define PDMA_OUT_CTRL_SRCALPHA_OP_MASK (0x3000U) -#define PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT (12U) -#define PDMA_OUT_CTRL_SRCALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) -#define PDMA_OUT_CTRL_SRCALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) >> PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) - -/* - * ABLEND_MODE (RW) - * - * Alpha Blending Mode - * 0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); - * 1: SKBlendMode_Src ; - * 2: SKBlendMode_Dst - * 3: SKBlendMode_SrcOver - * 4: SKBlendMode_DstOver - * 5: SKBlendMode_SrcIn - * 6: SKBlendMode_DstIn - * 7: SKBlendMode_SrcOut - * 8: SKBlendMode_DstOut - * 9: SKBlendMode_SrcATop - * 10: SKBlendMode_DstATop - * 11: SKBlendMode_Xor - * 12: SKBlendMode_Plus (The conventional belding mode) - * 13: SKBlendMode_Modulate - * 14: SRC org - * 15: DST org - * Others: Reserved. - */ -#define PDMA_OUT_CTRL_ABLEND_MODE_MASK (0xF00U) -#define PDMA_OUT_CTRL_ABLEND_MODE_SHIFT (8U) -#define PDMA_OUT_CTRL_ABLEND_MODE_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) -#define PDMA_OUT_CTRL_ABLEND_MODE_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) >> PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) - -/* - * FORMAT (RW) - * - * Output buffer format. - * 0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A - * 0xE RGB565 - 16-bit pixels, byte sequence as B,R - * 0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - */ -#define PDMA_OUT_CTRL_FORMAT_MASK (0x3FU) -#define PDMA_OUT_CTRL_FORMAT_SHIFT (0U) -#define PDMA_OUT_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_FORMAT_SHIFT) & PDMA_OUT_CTRL_FORMAT_MASK) -#define PDMA_OUT_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_FORMAT_MASK) >> PDMA_OUT_CTRL_FORMAT_SHIFT) - -/* Bitfield definition for register: OUT_BUF */ -/* - * ADDR (RW) - * - * Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - */ -#define PDMA_OUT_BUF_ADDR_MASK (0xFFFFFFFFUL) -#define PDMA_OUT_BUF_ADDR_SHIFT (0U) -#define PDMA_OUT_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_OUT_BUF_ADDR_SHIFT) & PDMA_OUT_BUF_ADDR_MASK) -#define PDMA_OUT_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_OUT_BUF_ADDR_MASK) >> PDMA_OUT_BUF_ADDR_SHIFT) - -/* Bitfield definition for register: OUT_PITCH */ -/* - * BYTELEN (RW) - * - * Indicates the number of bytes in memory between two vertically adjacent pixels. - */ -#define PDMA_OUT_PITCH_BYTELEN_MASK (0xFFFFU) -#define PDMA_OUT_PITCH_BYTELEN_SHIFT (0U) -#define PDMA_OUT_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_OUT_PITCH_BYTELEN_SHIFT) & PDMA_OUT_PITCH_BYTELEN_MASK) -#define PDMA_OUT_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_OUT_PITCH_BYTELEN_MASK) >> PDMA_OUT_PITCH_BYTELEN_SHIFT) - -/* Bitfield definition for register: OUT_LRC */ -/* - * Y (RW) - * - * This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. - * The value is the height of the output image size. - */ -#define PDMA_OUT_LRC_Y_MASK (0x3FFF0000UL) -#define PDMA_OUT_LRC_Y_SHIFT (16U) -#define PDMA_OUT_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_Y_SHIFT) & PDMA_OUT_LRC_Y_MASK) -#define PDMA_OUT_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_Y_MASK) >> PDMA_OUT_LRC_Y_SHIFT) - -/* - * X (RW) - * - * This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. - * Should be the width of the output image size. - */ -#define PDMA_OUT_LRC_X_MASK (0x3FFFU) -#define PDMA_OUT_LRC_X_SHIFT (0U) -#define PDMA_OUT_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_X_SHIFT) & PDMA_OUT_LRC_X_MASK) -#define PDMA_OUT_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_X_MASK) >> PDMA_OUT_LRC_X_SHIFT) - -/* Bitfield definition for register of struct array OUT_PS: ULC */ -/* - * Y (RW) - * - * This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_ULC_Y_MASK (0x3FFF0000UL) -#define PDMA_OUT_PS_ULC_Y_SHIFT (16U) -#define PDMA_OUT_PS_ULC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_Y_SHIFT) & PDMA_OUT_PS_ULC_Y_MASK) -#define PDMA_OUT_PS_ULC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_Y_MASK) >> PDMA_OUT_PS_ULC_Y_SHIFT) - -/* - * X (RW) - * - * This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_ULC_X_MASK (0x3FFFU) -#define PDMA_OUT_PS_ULC_X_SHIFT (0U) -#define PDMA_OUT_PS_ULC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_X_SHIFT) & PDMA_OUT_PS_ULC_X_MASK) -#define PDMA_OUT_PS_ULC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_X_MASK) >> PDMA_OUT_PS_ULC_X_SHIFT) - -/* Bitfield definition for register of struct array OUT_PS: LRC */ -/* - * Y (RW) - * - * This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_LRC_Y_MASK (0x3FFF0000UL) -#define PDMA_OUT_PS_LRC_Y_SHIFT (16U) -#define PDMA_OUT_PS_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_Y_SHIFT) & PDMA_OUT_PS_LRC_Y_MASK) -#define PDMA_OUT_PS_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_Y_MASK) >> PDMA_OUT_PS_LRC_Y_SHIFT) - -/* - * X (RW) - * - * This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_LRC_X_MASK (0x3FFFU) -#define PDMA_OUT_PS_LRC_X_SHIFT (0U) -#define PDMA_OUT_PS_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_X_SHIFT) & PDMA_OUT_PS_LRC_X_MASK) -#define PDMA_OUT_PS_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_X_MASK) >> PDMA_OUT_PS_LRC_X_SHIFT) - -/* Bitfield definition for register of struct array PS: CTRL */ -/* - * INB13_SWAP (RW) - * - * Swap bit[31:24] and bit [15:8] before pack_dir operation. - */ -#define PDMA_PS_CTRL_INB13_SWAP_MASK (0x100000UL) -#define PDMA_PS_CTRL_INB13_SWAP_SHIFT (20U) -#define PDMA_PS_CTRL_INB13_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_INB13_SWAP_SHIFT) & PDMA_PS_CTRL_INB13_SWAP_MASK) -#define PDMA_PS_CTRL_INB13_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_INB13_SWAP_MASK) >> PDMA_PS_CTRL_INB13_SWAP_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. - * 2'b00: no change {A3, A2, A1, A0} - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define PDMA_PS_CTRL_PACK_DIR_MASK (0xC0000UL) -#define PDMA_PS_CTRL_PACK_DIR_SHIFT (18U) -#define PDMA_PS_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PACK_DIR_SHIFT) & PDMA_PS_CTRL_PACK_DIR_MASK) -#define PDMA_PS_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PACK_DIR_MASK) >> PDMA_PS_CTRL_PACK_DIR_SHIFT) - -/* - * BKGCL4CLR (RW) - * - * Enable to use background color for clear area - */ -#define PDMA_PS_CTRL_BKGCL4CLR_MASK (0x20000UL) -#define PDMA_PS_CTRL_BKGCL4CLR_SHIFT (17U) -#define PDMA_PS_CTRL_BKGCL4CLR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BKGCL4CLR_SHIFT) & PDMA_PS_CTRL_BKGCL4CLR_MASK) -#define PDMA_PS_CTRL_BKGCL4CLR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BKGCL4CLR_MASK) >> PDMA_PS_CTRL_BKGCL4CLR_SHIFT) - -/* - * YCBCR_MODE (RW) - * - * YCbCr mode or YUV mode - */ -#define PDMA_PS_CTRL_YCBCR_MODE_MASK (0x10000UL) -#define PDMA_PS_CTRL_YCBCR_MODE_SHIFT (16U) -#define PDMA_PS_CTRL_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_YCBCR_MODE_SHIFT) & PDMA_PS_CTRL_YCBCR_MODE_MASK) -#define PDMA_PS_CTRL_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_YCBCR_MODE_MASK) >> PDMA_PS_CTRL_YCBCR_MODE_SHIFT) - -/* - * BYPASS (RW) - * - * Asserted to bypass the CSC stage - */ -#define PDMA_PS_CTRL_BYPASS_MASK (0x8000U) -#define PDMA_PS_CTRL_BYPASS_SHIFT (15U) -#define PDMA_PS_CTRL_BYPASS_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BYPASS_SHIFT) & PDMA_PS_CTRL_BYPASS_MASK) -#define PDMA_PS_CTRL_BYPASS_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BYPASS_MASK) >> PDMA_PS_CTRL_BYPASS_SHIFT) - -/* - * VFLIP (RW) - * - * Indicates that the input should be flipped vertically (effect applied before rotation). - */ -#define PDMA_PS_CTRL_VFLIP_MASK (0x4000U) -#define PDMA_PS_CTRL_VFLIP_SHIFT (14U) -#define PDMA_PS_CTRL_VFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_VFLIP_SHIFT) & PDMA_PS_CTRL_VFLIP_MASK) -#define PDMA_PS_CTRL_VFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_VFLIP_MASK) >> PDMA_PS_CTRL_VFLIP_SHIFT) - -/* - * HFLIP (RW) - * - * Indicates that the input should be flipped horizontally (effect applied before rotation). - */ -#define PDMA_PS_CTRL_HFLIP_MASK (0x2000U) -#define PDMA_PS_CTRL_HFLIP_SHIFT (13U) -#define PDMA_PS_CTRL_HFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HFLIP_SHIFT) & PDMA_PS_CTRL_HFLIP_MASK) -#define PDMA_PS_CTRL_HFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HFLIP_MASK) >> PDMA_PS_CTRL_HFLIP_SHIFT) - -/* - * ROTATE (RW) - * - * Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring - * after the FLIP_X and FLIP_Y permutation. - * 0x0 ROT_0 - * 0x1 ROT_90 - * 0x2 ROT_180 - * 0x3 ROT_270 - */ -#define PDMA_PS_CTRL_ROTATE_MASK (0x1800U) -#define PDMA_PS_CTRL_ROTATE_SHIFT (11U) -#define PDMA_PS_CTRL_ROTATE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_ROTATE_SHIFT) & PDMA_PS_CTRL_ROTATE_MASK) -#define PDMA_PS_CTRL_ROTATE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_ROTATE_MASK) >> PDMA_PS_CTRL_ROTATE_SHIFT) - -/* - * DECY (RW) - * - * Verticle pre decimation filter control. - * 0x0 DISABLE - Disable pre-decimation filter. - * 0x1 DECY2 - Decimate PS by 2. - * 0x2 DECY4 - Decimate PS by 4. - * 0x3 DECY8 - Decimate PS by 8. - */ -#define PDMA_PS_CTRL_DECY_MASK (0x600U) -#define PDMA_PS_CTRL_DECY_SHIFT (9U) -#define PDMA_PS_CTRL_DECY_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECY_SHIFT) & PDMA_PS_CTRL_DECY_MASK) -#define PDMA_PS_CTRL_DECY_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECY_MASK) >> PDMA_PS_CTRL_DECY_SHIFT) - -/* - * DECX (RW) - * - * Horizontal pre decimation filter control. - * 0x0 DISABLE - Disable pre-decimation filter. - * 0x1 DECX2 - Decimate PS by 2. - * 0x2 DECX4 - Decimate PS by 4. - * 0x3 DECX8 - Decimate PS by 8. - */ -#define PDMA_PS_CTRL_DECX_MASK (0x180U) -#define PDMA_PS_CTRL_DECX_SHIFT (7U) -#define PDMA_PS_CTRL_DECX_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECX_SHIFT) & PDMA_PS_CTRL_DECX_MASK) -#define PDMA_PS_CTRL_DECX_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECX_MASK) >> PDMA_PS_CTRL_DECX_SHIFT) - -/* - * HW_BYTE_SWAP (RW) - * - * Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - */ -#define PDMA_PS_CTRL_HW_BYTE_SWAP_MASK (0x40U) -#define PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT (6U) -#define PDMA_PS_CTRL_HW_BYTE_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) -#define PDMA_PS_CTRL_HW_BYTE_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) >> PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) - -/* - * FORMAT (RW) - * - * PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. - * 0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A - * 0xE RGB565 - 16-bit pixels, byte sequence as B,R - * 0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - */ -#define PDMA_PS_CTRL_FORMAT_MASK (0x3FU) -#define PDMA_PS_CTRL_FORMAT_SHIFT (0U) -#define PDMA_PS_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_FORMAT_SHIFT) & PDMA_PS_CTRL_FORMAT_MASK) -#define PDMA_PS_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_FORMAT_MASK) >> PDMA_PS_CTRL_FORMAT_SHIFT) - -/* Bitfield definition for register of struct array PS: BUF */ -/* - * ADDR (RW) - * - * Address pointer for the PS RGB or Y (luma) input buffer. - */ -#define PDMA_PS_BUF_ADDR_MASK (0xFFFFFFFFUL) -#define PDMA_PS_BUF_ADDR_SHIFT (0U) -#define PDMA_PS_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_PS_BUF_ADDR_SHIFT) & PDMA_PS_BUF_ADDR_MASK) -#define PDMA_PS_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_PS_BUF_ADDR_MASK) >> PDMA_PS_BUF_ADDR_SHIFT) - -/* Bitfield definition for register of struct array PS: PITCH */ -/* - * BYTELEN (RW) - * - * Indicates the number of bytes in memory between two vertically adjacent pixels. - */ -#define PDMA_PS_PITCH_BYTELEN_MASK (0xFFFFU) -#define PDMA_PS_PITCH_BYTELEN_SHIFT (0U) -#define PDMA_PS_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_PS_PITCH_BYTELEN_SHIFT) & PDMA_PS_PITCH_BYTELEN_MASK) -#define PDMA_PS_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_PS_PITCH_BYTELEN_MASK) >> PDMA_PS_PITCH_BYTELEN_SHIFT) - -/* Bitfield definition for register of struct array PS: BKGD */ -/* - * COLOR (RW) - * - * Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - */ -#define PDMA_PS_BKGD_COLOR_MASK (0xFFFFFFFFUL) -#define PDMA_PS_BKGD_COLOR_SHIFT (0U) -#define PDMA_PS_BKGD_COLOR_SET(x) (((uint32_t)(x) << PDMA_PS_BKGD_COLOR_SHIFT) & PDMA_PS_BKGD_COLOR_MASK) -#define PDMA_PS_BKGD_COLOR_GET(x) (((uint32_t)(x) & PDMA_PS_BKGD_COLOR_MASK) >> PDMA_PS_BKGD_COLOR_SHIFT) - -/* Bitfield definition for register of struct array PS: SCALE */ -/* - * Y (RW) - * - * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - */ -#define PDMA_PS_SCALE_Y_MASK (0x7FFF0000UL) -#define PDMA_PS_SCALE_Y_SHIFT (16U) -#define PDMA_PS_SCALE_Y_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_Y_SHIFT) & PDMA_PS_SCALE_Y_MASK) -#define PDMA_PS_SCALE_Y_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_Y_MASK) >> PDMA_PS_SCALE_Y_SHIFT) - -/* - * X (RW) - * - * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - */ -#define PDMA_PS_SCALE_X_MASK (0x7FFFU) -#define PDMA_PS_SCALE_X_SHIFT (0U) -#define PDMA_PS_SCALE_X_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_X_SHIFT) & PDMA_PS_SCALE_X_MASK) -#define PDMA_PS_SCALE_X_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_X_MASK) >> PDMA_PS_SCALE_X_SHIFT) - -/* Bitfield definition for register of struct array PS: OFFSET */ -/* - * Y (RW) - * - * This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. - * It is applied after the decimation filter stage, and before the bilinear filter stage. - */ -#define PDMA_PS_OFFSET_Y_MASK (0xFFF0000UL) -#define PDMA_PS_OFFSET_Y_SHIFT (16U) -#define PDMA_PS_OFFSET_Y_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_Y_SHIFT) & PDMA_PS_OFFSET_Y_MASK) -#define PDMA_PS_OFFSET_Y_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_Y_MASK) >> PDMA_PS_OFFSET_Y_SHIFT) - -/* - * X (RW) - * - * This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. - * It is applied after the decimation filter stage, and before the bilinear filter stage. - */ -#define PDMA_PS_OFFSET_X_MASK (0xFFFU) -#define PDMA_PS_OFFSET_X_SHIFT (0U) -#define PDMA_PS_OFFSET_X_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_X_SHIFT) & PDMA_PS_OFFSET_X_MASK) -#define PDMA_PS_OFFSET_X_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_X_MASK) >> PDMA_PS_OFFSET_X_SHIFT) - -/* Bitfield definition for register of struct array PS: CLRKEY_LOW */ -/* - * LIMIT (RW) - * - * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - */ -#define PDMA_PS_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) -#define PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT (0U) -#define PDMA_PS_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) -#define PDMA_PS_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) >> PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) - -/* Bitfield definition for register of struct array PS: CLRKEY_HIGH */ -/* - * LIMIT (RW) - * - * High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - */ -#define PDMA_PS_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) -#define PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT (0U) -#define PDMA_PS_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) -#define PDMA_PS_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) >> PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) - -/* Bitfield definition for register of struct array PS: ORG */ -/* - * HIGHT (RW) - * - * The number of vertical pixels of the original frame (not -1) - */ -#define PDMA_PS_ORG_HIGHT_MASK (0x3FFF0000UL) -#define PDMA_PS_ORG_HIGHT_SHIFT (16U) -#define PDMA_PS_ORG_HIGHT_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_HIGHT_SHIFT) & PDMA_PS_ORG_HIGHT_MASK) -#define PDMA_PS_ORG_HIGHT_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_HIGHT_MASK) >> PDMA_PS_ORG_HIGHT_SHIFT) - -/* - * WIDTH (RW) - * - * The number of horizontal pixels of the original frame (not -1) - */ -#define PDMA_PS_ORG_WIDTH_MASK (0x3FFFU) -#define PDMA_PS_ORG_WIDTH_SHIFT (0U) -#define PDMA_PS_ORG_WIDTH_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_WIDTH_SHIFT) & PDMA_PS_ORG_WIDTH_MASK) -#define PDMA_PS_ORG_WIDTH_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_WIDTH_MASK) >> PDMA_PS_ORG_WIDTH_SHIFT) - -/* Bitfield definition for register: YUV2RGB_COEF0 */ -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define PDMA_YUV2RGB_COEF0_C0_MASK (0x1FFC0000UL) -#define PDMA_YUV2RGB_COEF0_C0_SHIFT (18U) -#define PDMA_YUV2RGB_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_C0_SHIFT) & PDMA_YUV2RGB_COEF0_C0_MASK) -#define PDMA_YUV2RGB_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_C0_MASK) >> PDMA_YUV2RGB_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT (9U) -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK (0x1FFU) -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT (0U) -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: YUV2RGB_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define PDMA_YUV2RGB_COEF1_C1_MASK (0x7FF0000UL) -#define PDMA_YUV2RGB_COEF1_C1_SHIFT (16U) -#define PDMA_YUV2RGB_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C1_SHIFT) & PDMA_YUV2RGB_COEF1_C1_MASK) -#define PDMA_YUV2RGB_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C1_MASK) >> PDMA_YUV2RGB_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define PDMA_YUV2RGB_COEF1_C4_MASK (0x7FFU) -#define PDMA_YUV2RGB_COEF1_C4_SHIFT (0U) -#define PDMA_YUV2RGB_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C4_SHIFT) & PDMA_YUV2RGB_COEF1_C4_MASK) -#define PDMA_YUV2RGB_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C4_MASK) >> PDMA_YUV2RGB_COEF1_C4_SHIFT) - -/* Bitfield definition for register: YUV2RGB_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define PDMA_YUV2RGB_COEF2_C2_MASK (0x7FF0000UL) -#define PDMA_YUV2RGB_COEF2_C2_SHIFT (16U) -#define PDMA_YUV2RGB_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C2_SHIFT) & PDMA_YUV2RGB_COEF2_C2_MASK) -#define PDMA_YUV2RGB_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C2_MASK) >> PDMA_YUV2RGB_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define PDMA_YUV2RGB_COEF2_C3_MASK (0x7FFU) -#define PDMA_YUV2RGB_COEF2_C3_SHIFT (0U) -#define PDMA_YUV2RGB_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C3_SHIFT) & PDMA_YUV2RGB_COEF2_C3_MASK) -#define PDMA_YUV2RGB_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C3_MASK) >> PDMA_YUV2RGB_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * Asserted to use YCrCb mode - */ -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Asserted to enable this RGB2YUV CSC stage - */ -#define PDMA_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) -#define PDMA_RGB2YUV_COEF0_ENABLE_SHIFT (30U) -#define PDMA_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) -#define PDMA_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) >> PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * CSC parameters C0 - */ -#define PDMA_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) -#define PDMA_RGB2YUV_COEF0_C0_SHIFT (18U) -#define PDMA_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_C0_SHIFT) & PDMA_RGB2YUV_COEF0_C0_MASK) -#define PDMA_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_C0_MASK) >> PDMA_RGB2YUV_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * CSC parameters UV_OFFSET - */ -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * CSC parameters Y_OFFSET - */ -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF1 */ -/* - * C1 (RW) - * - * CSC parameters C1 - */ -#define PDMA_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF1_C1_SHIFT (16U) -#define PDMA_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C1_SHIFT) & PDMA_RGB2YUV_COEF1_C1_MASK) -#define PDMA_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C1_MASK) >> PDMA_RGB2YUV_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * CSC parameters C4 - */ -#define PDMA_RGB2YUV_COEF1_C4_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF1_C4_SHIFT (0U) -#define PDMA_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C4_SHIFT) & PDMA_RGB2YUV_COEF1_C4_MASK) -#define PDMA_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C4_MASK) >> PDMA_RGB2YUV_COEF1_C4_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF2 */ -/* - * C2 (RW) - * - * CSC parameters C2 - */ -#define PDMA_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF2_C2_SHIFT (16U) -#define PDMA_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C2_SHIFT) & PDMA_RGB2YUV_COEF2_C2_MASK) -#define PDMA_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C2_MASK) >> PDMA_RGB2YUV_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * CSC parameters C3 - */ -#define PDMA_RGB2YUV_COEF2_C3_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF2_C3_SHIFT (0U) -#define PDMA_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C3_SHIFT) & PDMA_RGB2YUV_COEF2_C3_MASK) -#define PDMA_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C3_MASK) >> PDMA_RGB2YUV_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF3 */ -/* - * C6 (RW) - * - * CSC parameters C6 - */ -#define PDMA_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF3_C6_SHIFT (16U) -#define PDMA_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C6_SHIFT) & PDMA_RGB2YUV_COEF3_C6_MASK) -#define PDMA_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C6_MASK) >> PDMA_RGB2YUV_COEF3_C6_SHIFT) - -/* - * C5 (RW) - * - * CSC parameters C5 - */ -#define PDMA_RGB2YUV_COEF3_C5_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF3_C5_SHIFT (0U) -#define PDMA_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C5_SHIFT) & PDMA_RGB2YUV_COEF3_C5_MASK) -#define PDMA_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C5_MASK) >> PDMA_RGB2YUV_COEF3_C5_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF4 */ -/* - * C8 (RW) - * - * CSC parameters C8 - */ -#define PDMA_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF4_C8_SHIFT (16U) -#define PDMA_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C8_SHIFT) & PDMA_RGB2YUV_COEF4_C8_MASK) -#define PDMA_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C8_MASK) >> PDMA_RGB2YUV_COEF4_C8_SHIFT) - -/* - * C7 (RW) - * - * CSC parameters C7 - */ -#define PDMA_RGB2YUV_COEF4_C7_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF4_C7_SHIFT (0U) -#define PDMA_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C7_SHIFT) & PDMA_RGB2YUV_COEF4_C7_MASK) -#define PDMA_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C7_MASK) >> PDMA_RGB2YUV_COEF4_C7_SHIFT) - - - -/* OUT_PS register group index macro definition */ -#define PDMA_OUT_PS_0 (0UL) -#define PDMA_OUT_PS_1 (1UL) - -/* PS register group index macro definition */ -#define PDMA_PS_0 (0UL) -#define PDMA_PS_1 (1UL) - - -#endif /* HPM_PDMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pgpr_regs.h deleted file mode 100644 index acf20cfecd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pgpr_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PGPR_H -#define HPM_PGPR_H - -typedef struct { - __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ - __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ - __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ - __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ - __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ - __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ - __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ - __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ - __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ - __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ - __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ - __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ - __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ - __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ - __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ - __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ -} PGPR_Type; - - -/* Bitfield definition for register: PMIC_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) -#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) -#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) -#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) -#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR04 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) -#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR05 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) -#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR06 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) -#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR07 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) -#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR08 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) -#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR09 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) -#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR10 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) -#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR11 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) -#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR12 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) -#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR13 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) -#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR14 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) -#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR15 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) -#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) - - - - -#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_plic_regs.h deleted file mode 100644 index eb5a6504d9c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_plic_regs.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_H -#define HPM_PLIC_H - -typedef struct { - __RW uint32_t FEATURE; /* 0x0: Feature enable register */ - __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ - __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ - __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ - __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ - __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ - __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ - __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ - __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ - __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ - struct { - __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ - __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ - } TARGETINT[2]; - __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */ - struct { - __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ - __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ - __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ - __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ - __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ - } TARGETCONFIG[2]; -} PLIC_Type; - - -/* Bitfield definition for register: FEATURE */ -/* - * VECTORED (RW) - * - * Vector mode enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_VECTORED_MASK (0x2U) -#define PLIC_FEATURE_VECTORED_SHIFT (1U) -#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) -#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) - -/* - * PREEMPT (RW) - * - * Preemptive priority interrupt enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_PREEMPT_MASK (0x1U) -#define PLIC_FEATURE_PREEMPT_SHIFT (0U) -#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) -#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) - -/* Bitfield definition for register array: PRIORITY */ -/* - * PRIORITY (RW) - * - * Interrupt source priority. The valid range of this field is 0-7. - * 0: Never interrupt - * 1-7: Interrupt source priority. The larger the value, the higher the priority. - */ -#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) -#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) -#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) -#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) - -/* Bitfield definition for register array: PENDING */ -/* - * INTERRUPT (RW) - * - * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - */ -#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_PENDING_INTERRUPT_SHIFT (0U) -#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) -#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register array: TRIGGER */ -/* - * INTERRUPT (RO) - * - * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. - * 0: Level-triggered interrupt - * 1: Edge-triggered interrupt - */ -#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) -#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) - -/* Bitfield definition for register: NUMBER */ -/* - * NUM_TARGET (RO) - * - * The number of supported targets - */ -#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) -#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) -#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) - -/* - * NUM_INTERRUPT (RO) - * - * The number of supported interrupt sources - */ -#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) -#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) -#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INFO */ -/* - * MAX_PRIORITY (RO) - * - * The maximum priority supported - */ -#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) -#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) -#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) - -/* - * VERSION (RO) - * - * The version of the PLIC design - */ -#define PLIC_INFO_VERSION_MASK (0xFFFFU) -#define PLIC_INFO_VERSION_SHIFT (0U) -#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) - -/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ -/* - * INTERRUPT (RW) - * - * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - */ -#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) -#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ -/* - * THRESHOLD (RW) - * - * Interrupt priority threshold. - */ -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ -/* - * PRIORITY_PREEMPTED (RW) - * - * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - */ -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) - - - -/* PRIORITY register group index macro definition */ -#define PLIC_PRIORITY_PRIORITY1 (0UL) -#define PLIC_PRIORITY_PRIORITY2 (1UL) -#define PLIC_PRIORITY_PRIORITY3 (2UL) -#define PLIC_PRIORITY_PRIORITY4 (3UL) -#define PLIC_PRIORITY_PRIORITY5 (4UL) -#define PLIC_PRIORITY_PRIORITY6 (5UL) -#define PLIC_PRIORITY_PRIORITY7 (6UL) -#define PLIC_PRIORITY_PRIORITY8 (7UL) -#define PLIC_PRIORITY_PRIORITY9 (8UL) -#define PLIC_PRIORITY_PRIORITY10 (9UL) -#define PLIC_PRIORITY_PRIORITY11 (10UL) -#define PLIC_PRIORITY_PRIORITY12 (11UL) -#define PLIC_PRIORITY_PRIORITY13 (12UL) -#define PLIC_PRIORITY_PRIORITY14 (13UL) -#define PLIC_PRIORITY_PRIORITY15 (14UL) -#define PLIC_PRIORITY_PRIORITY16 (15UL) -#define PLIC_PRIORITY_PRIORITY17 (16UL) -#define PLIC_PRIORITY_PRIORITY18 (17UL) -#define PLIC_PRIORITY_PRIORITY19 (18UL) -#define PLIC_PRIORITY_PRIORITY20 (19UL) -#define PLIC_PRIORITY_PRIORITY21 (20UL) -#define PLIC_PRIORITY_PRIORITY22 (21UL) -#define PLIC_PRIORITY_PRIORITY23 (22UL) -#define PLIC_PRIORITY_PRIORITY24 (23UL) -#define PLIC_PRIORITY_PRIORITY25 (24UL) -#define PLIC_PRIORITY_PRIORITY26 (25UL) -#define PLIC_PRIORITY_PRIORITY27 (26UL) -#define PLIC_PRIORITY_PRIORITY28 (27UL) -#define PLIC_PRIORITY_PRIORITY29 (28UL) -#define PLIC_PRIORITY_PRIORITY30 (29UL) -#define PLIC_PRIORITY_PRIORITY31 (30UL) -#define PLIC_PRIORITY_PRIORITY32 (31UL) -#define PLIC_PRIORITY_PRIORITY33 (32UL) -#define PLIC_PRIORITY_PRIORITY34 (33UL) -#define PLIC_PRIORITY_PRIORITY35 (34UL) -#define PLIC_PRIORITY_PRIORITY36 (35UL) -#define PLIC_PRIORITY_PRIORITY37 (36UL) -#define PLIC_PRIORITY_PRIORITY38 (37UL) -#define PLIC_PRIORITY_PRIORITY39 (38UL) -#define PLIC_PRIORITY_PRIORITY40 (39UL) -#define PLIC_PRIORITY_PRIORITY41 (40UL) -#define PLIC_PRIORITY_PRIORITY42 (41UL) -#define PLIC_PRIORITY_PRIORITY43 (42UL) -#define PLIC_PRIORITY_PRIORITY44 (43UL) -#define PLIC_PRIORITY_PRIORITY45 (44UL) -#define PLIC_PRIORITY_PRIORITY46 (45UL) -#define PLIC_PRIORITY_PRIORITY47 (46UL) -#define PLIC_PRIORITY_PRIORITY48 (47UL) -#define PLIC_PRIORITY_PRIORITY49 (48UL) -#define PLIC_PRIORITY_PRIORITY50 (49UL) -#define PLIC_PRIORITY_PRIORITY51 (50UL) -#define PLIC_PRIORITY_PRIORITY52 (51UL) -#define PLIC_PRIORITY_PRIORITY53 (52UL) -#define PLIC_PRIORITY_PRIORITY54 (53UL) -#define PLIC_PRIORITY_PRIORITY55 (54UL) -#define PLIC_PRIORITY_PRIORITY56 (55UL) -#define PLIC_PRIORITY_PRIORITY57 (56UL) -#define PLIC_PRIORITY_PRIORITY58 (57UL) -#define PLIC_PRIORITY_PRIORITY59 (58UL) -#define PLIC_PRIORITY_PRIORITY60 (59UL) -#define PLIC_PRIORITY_PRIORITY61 (60UL) -#define PLIC_PRIORITY_PRIORITY62 (61UL) -#define PLIC_PRIORITY_PRIORITY63 (62UL) -#define PLIC_PRIORITY_PRIORITY64 (63UL) -#define PLIC_PRIORITY_PRIORITY65 (64UL) -#define PLIC_PRIORITY_PRIORITY66 (65UL) -#define PLIC_PRIORITY_PRIORITY67 (66UL) -#define PLIC_PRIORITY_PRIORITY68 (67UL) -#define PLIC_PRIORITY_PRIORITY69 (68UL) -#define PLIC_PRIORITY_PRIORITY70 (69UL) -#define PLIC_PRIORITY_PRIORITY71 (70UL) -#define PLIC_PRIORITY_PRIORITY72 (71UL) -#define PLIC_PRIORITY_PRIORITY73 (72UL) -#define PLIC_PRIORITY_PRIORITY74 (73UL) -#define PLIC_PRIORITY_PRIORITY75 (74UL) -#define PLIC_PRIORITY_PRIORITY76 (75UL) -#define PLIC_PRIORITY_PRIORITY77 (76UL) -#define PLIC_PRIORITY_PRIORITY78 (77UL) -#define PLIC_PRIORITY_PRIORITY79 (78UL) -#define PLIC_PRIORITY_PRIORITY80 (79UL) -#define PLIC_PRIORITY_PRIORITY81 (80UL) -#define PLIC_PRIORITY_PRIORITY82 (81UL) -#define PLIC_PRIORITY_PRIORITY83 (82UL) -#define PLIC_PRIORITY_PRIORITY84 (83UL) -#define PLIC_PRIORITY_PRIORITY85 (84UL) -#define PLIC_PRIORITY_PRIORITY86 (85UL) -#define PLIC_PRIORITY_PRIORITY87 (86UL) -#define PLIC_PRIORITY_PRIORITY88 (87UL) -#define PLIC_PRIORITY_PRIORITY89 (88UL) -#define PLIC_PRIORITY_PRIORITY90 (89UL) -#define PLIC_PRIORITY_PRIORITY91 (90UL) -#define PLIC_PRIORITY_PRIORITY92 (91UL) -#define PLIC_PRIORITY_PRIORITY93 (92UL) -#define PLIC_PRIORITY_PRIORITY94 (93UL) -#define PLIC_PRIORITY_PRIORITY95 (94UL) -#define PLIC_PRIORITY_PRIORITY96 (95UL) -#define PLIC_PRIORITY_PRIORITY97 (96UL) -#define PLIC_PRIORITY_PRIORITY98 (97UL) -#define PLIC_PRIORITY_PRIORITY99 (98UL) -#define PLIC_PRIORITY_PRIORITY100 (99UL) -#define PLIC_PRIORITY_PRIORITY101 (100UL) -#define PLIC_PRIORITY_PRIORITY102 (101UL) -#define PLIC_PRIORITY_PRIORITY103 (102UL) -#define PLIC_PRIORITY_PRIORITY104 (103UL) -#define PLIC_PRIORITY_PRIORITY105 (104UL) -#define PLIC_PRIORITY_PRIORITY106 (105UL) -#define PLIC_PRIORITY_PRIORITY107 (106UL) -#define PLIC_PRIORITY_PRIORITY108 (107UL) -#define PLIC_PRIORITY_PRIORITY109 (108UL) -#define PLIC_PRIORITY_PRIORITY110 (109UL) -#define PLIC_PRIORITY_PRIORITY111 (110UL) -#define PLIC_PRIORITY_PRIORITY112 (111UL) -#define PLIC_PRIORITY_PRIORITY113 (112UL) -#define PLIC_PRIORITY_PRIORITY114 (113UL) -#define PLIC_PRIORITY_PRIORITY115 (114UL) -#define PLIC_PRIORITY_PRIORITY116 (115UL) -#define PLIC_PRIORITY_PRIORITY117 (116UL) -#define PLIC_PRIORITY_PRIORITY118 (117UL) -#define PLIC_PRIORITY_PRIORITY119 (118UL) -#define PLIC_PRIORITY_PRIORITY120 (119UL) -#define PLIC_PRIORITY_PRIORITY121 (120UL) -#define PLIC_PRIORITY_PRIORITY122 (121UL) -#define PLIC_PRIORITY_PRIORITY123 (122UL) -#define PLIC_PRIORITY_PRIORITY124 (123UL) -#define PLIC_PRIORITY_PRIORITY125 (124UL) -#define PLIC_PRIORITY_PRIORITY126 (125UL) -#define PLIC_PRIORITY_PRIORITY127 (126UL) - -/* PENDING register group index macro definition */ -#define PLIC_PENDING_PENDING0 (0UL) -#define PLIC_PENDING_PENDING1 (1UL) -#define PLIC_PENDING_PENDING2 (2UL) -#define PLIC_PENDING_PENDING3 (3UL) - -/* TRIGGER register group index macro definition */ -#define PLIC_TRIGGER_TRIGGER0 (0UL) -#define PLIC_TRIGGER_TRIGGER1 (1UL) -#define PLIC_TRIGGER_TRIGGER2 (2UL) -#define PLIC_TRIGGER_TRIGGER3 (3UL) - -/* INTEN register group index macro definition */ -#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) -#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) -#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) -#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) - -/* TARGETINT register group index macro definition */ -#define PLIC_TARGETINT_TARGET0 (0UL) -#define PLIC_TARGETINT_TARGET1 (1UL) - -/* TARGETCONFIG register group index macro definition */ -#define PLIC_TARGETCONFIG_TARGET0 (0UL) -#define PLIC_TARGETCONFIG_TARGET1 (1UL) - - -#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_plic_sw_regs.h deleted file mode 100644 index 998dafa2d57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_plic_sw_regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_SW_H -#define HPM_PLIC_SW_H - -typedef struct { - __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ - __RW uint32_t PENDING; /* 0x1000: Pending status */ - __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ - __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ - __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ - __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ -} PLIC_SW_Type; - - -/* Bitfield definition for register: PENDING */ -/* - * INTERRUPT (RW) - * - * writing 1 to trigger software interrupt - */ -#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) -#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) -#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) -#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * INTERRUPT (RW) - * - * enable software interrupt - */ -#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) -#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) -#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) - - - - -#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pllctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pllctl_regs.h deleted file mode 100644 index 6fe82c3f0fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pllctl_regs.h +++ /dev/null @@ -1,446 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLLCTL_H -#define HPM_PLLCTL_H - -typedef struct { - __RW uint32_t XTAL; /* 0x0: Crystal control and status */ - __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x80: PLLx config0 */ - __RW uint32_t CFG1; /* 0x84: PLLx config1 */ - __RW uint32_t CFG2; /* 0x88: PLLx config2 */ - __RW uint32_t FREQ; /* 0x8C: PLLx frac mode frequency adjust */ - __RW uint32_t LOCK; /* 0x90: PLLx lock control */ - __R uint8_t RESERVED0[12]; /* 0x94 - 0x9F: Reserved */ - __R uint32_t STATUS; /* 0xA0: PLLx status */ - __R uint8_t RESERVED1[28]; /* 0xA4 - 0xBF: Reserved */ - __RW uint32_t DIV0; /* 0xC0: PLLx divider0 control */ - __RW uint32_t DIV1; /* 0xC4: PLLx divider1 control */ - __R uint8_t RESERVED2[56]; /* 0xC8 - 0xFF: Reserved */ - } PLL[5]; -} PLLCTL_Type; - - -/* Bitfield definition for register: XTAL */ -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTL_XTAL_RESPONSE_MASK (0x20000000UL) -#define PLLCTL_XTAL_RESPONSE_SHIFT (29U) -#define PLLCTL_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_RESPONSE_MASK) >> PLLCTL_XTAL_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTL_XTAL_ENABLE_MASK (0x10000000UL) -#define PLLCTL_XTAL_ENABLE_SHIFT (28U) -#define PLLCTL_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_ENABLE_MASK) >> PLLCTL_XTAL_ENABLE_SHIFT) - -/* - * RAMP_TIME (RW) - * - * Rampup time of XTAL oscillator in cycles of IRC24M clock - * 0: 0 cycle - * 1: 1 cycle - * 2: 2 cycle - * 1048575: 1048575 cycles - */ -#define PLLCTL_XTAL_RAMP_TIME_MASK (0xFFFFFUL) -#define PLLCTL_XTAL_RAMP_TIME_SHIFT (0U) -#define PLLCTL_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTL_XTAL_RAMP_TIME_SHIFT) & PLLCTL_XTAL_RAMP_TIME_MASK) -#define PLLCTL_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTL_XTAL_RAMP_TIME_MASK) >> PLLCTL_XTAL_RAMP_TIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: CFG0 */ -/* - * SS_RSTPTR (RW) - * - * reset pointer, for sscg, lock when lock_en[31]&~pll_ana_pd&~pll_lock_comb - */ -#define PLLCTL_PLL_CFG0_SS_RSTPTR_MASK (0x80000000UL) -#define PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT (31U) -#define PLLCTL_PLL_CFG0_SS_RSTPTR_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) -#define PLLCTL_PLL_CFG0_SS_RSTPTR_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RSTPTR_MASK) >> PLLCTL_PLL_CFG0_SS_RSTPTR_SHIFT) - -/* - * REFDIV (RW) - * - * refclk diverder, lock when lock_en[24]&~pll_ana_pd - */ -#define PLLCTL_PLL_CFG0_REFDIV_MASK (0x3F000000UL) -#define PLLCTL_PLL_CFG0_REFDIV_SHIFT (24U) -#define PLLCTL_PLL_CFG0_REFDIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_REFDIV_SHIFT) & PLLCTL_PLL_CFG0_REFDIV_MASK) -#define PLLCTL_PLL_CFG0_REFDIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_REFDIV_MASK) >> PLLCTL_PLL_CFG0_REFDIV_SHIFT) - -/* - * POSTDIV1 (RW) - * - * lock when lock_en[20]&~pll_ana_pd - */ -#define PLLCTL_PLL_CFG0_POSTDIV1_MASK (0x700000UL) -#define PLLCTL_PLL_CFG0_POSTDIV1_SHIFT (20U) -#define PLLCTL_PLL_CFG0_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) -#define PLLCTL_PLL_CFG0_POSTDIV1_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_POSTDIV1_MASK) >> PLLCTL_PLL_CFG0_POSTDIV1_SHIFT) - -/* - * SS_SPREAD (RW) - * - * lock when lock_en[14]&~pll_ana_pd - */ -#define PLLCTL_PLL_CFG0_SS_SPREAD_MASK (0x7C000UL) -#define PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT (14U) -#define PLLCTL_PLL_CFG0_SS_SPREAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) -#define PLLCTL_PLL_CFG0_SS_SPREAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_SPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_SPREAD_SHIFT) - -/* - * SS_DIVVAL (RW) - * - * sscg divval, lock when lock_en[8]&~pll_ana_pd - */ -#define PLLCTL_PLL_CFG0_SS_DIVVAL_MASK (0x3F00U) -#define PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT (8U) -#define PLLCTL_PLL_CFG0_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) -#define PLLCTL_PLL_CFG0_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DIVVAL_MASK) >> PLLCTL_PLL_CFG0_SS_DIVVAL_SHIFT) - -/* - * SS_DOWNSPREAD (RW) - * - * Downspread control - * 1’b0 –> Center-Spread - * 1’b1 –> Downspread - */ -#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK (0x80U) -#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT (7U) -#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) -#define PLLCTL_PLL_CFG0_SS_DOWNSPREAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DOWNSPREAD_MASK) >> PLLCTL_PLL_CFG0_SS_DOWNSPREAD_SHIFT) - -/* - * SS_RESET (RW) - * - */ -#define PLLCTL_PLL_CFG0_SS_RESET_MASK (0x40U) -#define PLLCTL_PLL_CFG0_SS_RESET_SHIFT (6U) -#define PLLCTL_PLL_CFG0_SS_RESET_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_RESET_SHIFT) & PLLCTL_PLL_CFG0_SS_RESET_MASK) -#define PLLCTL_PLL_CFG0_SS_RESET_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_RESET_MASK) >> PLLCTL_PLL_CFG0_SS_RESET_SHIFT) - -/* - * SS_DISABLE_SSCG (RW) - * - */ -#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK (0x20U) -#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT (5U) -#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) -#define PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_MASK) >> PLLCTL_PLL_CFG0_SS_DISABLE_SSCG_SHIFT) - -/* - * DSMPD (RW) - * - * 1: int mode; 0: frac mode - */ -#define PLLCTL_PLL_CFG0_DSMPD_MASK (0x8U) -#define PLLCTL_PLL_CFG0_DSMPD_SHIFT (3U) -#define PLLCTL_PLL_CFG0_DSMPD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG0_DSMPD_SHIFT) & PLLCTL_PLL_CFG0_DSMPD_MASK) -#define PLLCTL_PLL_CFG0_DSMPD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG0_DSMPD_MASK) >> PLLCTL_PLL_CFG0_DSMPD_SHIFT) - -/* Bitfield definition for register of struct array PLL: CFG1 */ -/* - * PLLCTRL_HW_EN (RW) - * - * 1: hardware controll PLL settings, software can update register, but result unknown; suggested only update fbdiv and frac value - * 0: full software control PLL settings - */ -#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK (0x80000000UL) -#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT (31U) -#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) -#define PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_MASK) >> PLLCTL_PLL_CFG1_PLLCTRL_HW_EN_SHIFT) - -/* - * CLKEN_SW (RW) - * - * the clock enable used to gate pll output, should be set after lock, and clear before power down pll. - * pll_clock_enable = pllctrl_hw_en ? (pll_lock_comb & enable & pll_clk_enable_chg) : clken_sw; - */ -#define PLLCTL_PLL_CFG1_CLKEN_SW_MASK (0x4000000UL) -#define PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT (26U) -#define PLLCTL_PLL_CFG1_CLKEN_SW_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) -#define PLLCTL_PLL_CFG1_CLKEN_SW_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_CLKEN_SW_MASK) >> PLLCTL_PLL_CFG1_CLKEN_SW_SHIFT) - -/* - * PLLPD_SW (RW) - * - * pll power down. - * pll_ana_pd = pllctrl_hw_en ? (pll_pd_soc|pll_pd_chg) : pllpd_sw; - * pll_pd_soc is just delay of soc enable, for soc to control pll on/off; - * pll_pd_chg is used to power down pll when div_chg_mode is 1, if software update pll parameter(fbdiv or frac), pll_ctrl will power down pll, update parameter, then power up pll. response to soc will not de-asserted at this sequence - */ -#define PLLCTL_PLL_CFG1_PLLPD_SW_MASK (0x2000000UL) -#define PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT (25U) -#define PLLCTL_PLL_CFG1_PLLPD_SW_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) -#define PLLCTL_PLL_CFG1_PLLPD_SW_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_PLLPD_SW_MASK) >> PLLCTL_PLL_CFG1_PLLPD_SW_SHIFT) - -/* - * LOCK_CNT_CFG (RW) - * - * used to wait lock if set larger than lock time; - * default 1500 24M cycle if refdiv is 1, 4500 cycle if refdiv is 3 - */ -#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK (0x8000U) -#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT (15U) -#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) -#define PLLCTL_PLL_CFG1_LOCK_CNT_CFG_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG1_LOCK_CNT_CFG_MASK) >> PLLCTL_PLL_CFG1_LOCK_CNT_CFG_SHIFT) - -/* Bitfield definition for register of struct array PLL: CFG2 */ -/* - * FBDIV_INT (RW) - * - * fbdiv used in int mode - */ -#define PLLCTL_PLL_CFG2_FBDIV_INT_MASK (0xFFFU) -#define PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT (0U) -#define PLLCTL_PLL_CFG2_FBDIV_INT_SET(x) (((uint32_t)(x) << PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) -#define PLLCTL_PLL_CFG2_FBDIV_INT_GET(x) (((uint32_t)(x) & PLLCTL_PLL_CFG2_FBDIV_INT_MASK) >> PLLCTL_PLL_CFG2_FBDIV_INT_SHIFT) - -/* Bitfield definition for register of struct array PLL: FREQ */ -/* - * FRAC (RW) - * - * PLL output frequency is : - * Fout = Fref/refdiv*(fbdiv + frac/2^24)/postdiv1 - * for default refdiv=1 and postdiv1=1, 24MHz refclk - * Fout is 24*fbdiv in int mode - * if frac is set to 0x800000, Fout is 24*(fbdiv+0.5) - * Fout is 24*fbdiv in int mode - * if frac is set to 0x200000, Fout is 24*(fbdiv+0.125) - */ -#define PLLCTL_PLL_FREQ_FRAC_MASK (0xFFFFFF00UL) -#define PLLCTL_PLL_FREQ_FRAC_SHIFT (8U) -#define PLLCTL_PLL_FREQ_FRAC_SET(x) (((uint32_t)(x) << PLLCTL_PLL_FREQ_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FRAC_MASK) -#define PLLCTL_PLL_FREQ_FRAC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_FREQ_FRAC_MASK) >> PLLCTL_PLL_FREQ_FRAC_SHIFT) - -/* - * FBDIV_FRAC (RW) - * - * fbdiv used in frac mode - */ -#define PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK (0xFFU) -#define PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT (0U) -#define PLLCTL_PLL_FREQ_FBDIV_FRAC_SET(x) (((uint32_t)(x) << PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) -#define PLLCTL_PLL_FREQ_FBDIV_FRAC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_FREQ_FBDIV_FRAC_MASK) >> PLLCTL_PLL_FREQ_FBDIV_FRAC_SHIFT) - -/* Bitfield definition for register of struct array PLL: LOCK */ -/* - * LOCK_SS_RSTPTR (RW) - * - * lock bit of field ss_rstptr - * 0: field is open foe software to change - * 1: field is locked, not changeable - */ -#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK (0x80000000UL) -#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT (31U) -#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) -#define PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_SHIFT) - -/* - * LOCK_REFDIV (RW) - * - * lock bit of field refdiv - * 0: field is open foe software to change - * 1: field is locked, not changeable - */ -#define PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK (0x1000000UL) -#define PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT (24U) -#define PLLCTL_PLL_LOCK_LOCK_REFDIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) -#define PLLCTL_PLL_LOCK_LOCK_REFDIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK) >> PLLCTL_PLL_LOCK_LOCK_REFDIV_SHIFT) - -/* - * LOCK_POSTDIV1 (RW) - * - * lock bit of field postdiv1 - * 0: field is open foe software to change - * 1: field is locked, not changeable - */ -#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK (0x100000UL) -#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT (20U) -#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) -#define PLLCTL_PLL_LOCK_LOCK_POSTDIV1_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK) >> PLLCTL_PLL_LOCK_LOCK_POSTDIV1_SHIFT) - -/* - * LOCK_SS_SPEAD (RW) - * - * lock bit of field ss_spead - * 0: field is open foe software to change - * 1: field is locked, not changeable - */ -#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK (0x4000U) -#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT (14U) -#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) -#define PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_SPEAD_SHIFT) - -/* - * LOCK_SS_DIVVAL (RW) - * - * lock bit of field ss_divval - * 0: field is open foe software to change - * 1: field is locked, not changeable - */ -#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK (0x100U) -#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT (8U) -#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SET(x) (((uint32_t)(x) << PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) -#define PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_GET(x) (((uint32_t)(x) & PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK) >> PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_SHIFT) - -/* Bitfield definition for register of struct array PLL: STATUS */ -/* - * ENABLE (RO) - * - * enable from SYSCTL block - */ -#define PLLCTL_PLL_STATUS_ENABLE_MASK (0x8000000UL) -#define PLLCTL_PLL_STATUS_ENABLE_SHIFT (27U) -#define PLLCTL_PLL_STATUS_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_ENABLE_MASK) >> PLLCTL_PLL_STATUS_ENABLE_SHIFT) - -/* - * RESPONSE (RO) - * - * response to SYSCTL, PLL is power down when both enable and response are 0. - */ -#define PLLCTL_PLL_STATUS_RESPONSE_MASK (0x4U) -#define PLLCTL_PLL_STATUS_RESPONSE_SHIFT (2U) -#define PLLCTL_PLL_STATUS_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_RESPONSE_MASK) >> PLLCTL_PLL_STATUS_RESPONSE_SHIFT) - -/* - * PLL_LOCK_COMB (RO) - * - */ -#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK (0x2U) -#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT (1U) -#define PLLCTL_PLL_STATUS_PLL_LOCK_COMB_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_COMB_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_COMB_SHIFT) - -/* - * PLL_LOCK_SYNC (RO) - * - */ -#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK (0x1U) -#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT (0U) -#define PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_GET(x) (((uint32_t)(x) & PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_MASK) >> PLLCTL_PLL_STATUS_PLL_LOCK_SYNC_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV0 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTL_PLL_DIV0_BUSY_MASK (0x80000000UL) -#define PLLCTL_PLL_DIV0_BUSY_SHIFT (31U) -#define PLLCTL_PLL_DIV0_BUSY_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_BUSY_MASK) >> PLLCTL_PLL_DIV0_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTL_PLL_DIV0_RESPONSE_MASK (0x20000000UL) -#define PLLCTL_PLL_DIV0_RESPONSE_SHIFT (29U) -#define PLLCTL_PLL_DIV0_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_RESPONSE_MASK) >> PLLCTL_PLL_DIV0_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTL_PLL_DIV0_ENABLE_MASK (0x10000000UL) -#define PLLCTL_PLL_DIV0_ENABLE_SHIFT (28U) -#define PLLCTL_PLL_DIV0_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_ENABLE_MASK) >> PLLCTL_PLL_DIV0_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider - * 0: divide by 1 - * 1: divide by2 - * . . . - * 255: divide by 256 - */ -#define PLLCTL_PLL_DIV0_DIV_MASK (0xFFU) -#define PLLCTL_PLL_DIV0_DIV_SHIFT (0U) -#define PLLCTL_PLL_DIV0_DIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_DIV0_DIV_SHIFT) & PLLCTL_PLL_DIV0_DIV_MASK) -#define PLLCTL_PLL_DIV0_DIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV0_DIV_MASK) >> PLLCTL_PLL_DIV0_DIV_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV1 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTL_PLL_DIV1_BUSY_MASK (0x80000000UL) -#define PLLCTL_PLL_DIV1_BUSY_SHIFT (31U) -#define PLLCTL_PLL_DIV1_BUSY_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_BUSY_MASK) >> PLLCTL_PLL_DIV1_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTL_PLL_DIV1_RESPONSE_MASK (0x20000000UL) -#define PLLCTL_PLL_DIV1_RESPONSE_SHIFT (29U) -#define PLLCTL_PLL_DIV1_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_RESPONSE_MASK) >> PLLCTL_PLL_DIV1_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTL_PLL_DIV1_ENABLE_MASK (0x10000000UL) -#define PLLCTL_PLL_DIV1_ENABLE_SHIFT (28U) -#define PLLCTL_PLL_DIV1_ENABLE_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_ENABLE_MASK) >> PLLCTL_PLL_DIV1_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider - * 0: divide by 1 - * 1: divide by2 - * . . . - * 255: divide by 256 - */ -#define PLLCTL_PLL_DIV1_DIV_MASK (0xFFU) -#define PLLCTL_PLL_DIV1_DIV_SHIFT (0U) -#define PLLCTL_PLL_DIV1_DIV_SET(x) (((uint32_t)(x) << PLLCTL_PLL_DIV1_DIV_SHIFT) & PLLCTL_PLL_DIV1_DIV_MASK) -#define PLLCTL_PLL_DIV1_DIV_GET(x) (((uint32_t)(x) & PLLCTL_PLL_DIV1_DIV_MASK) >> PLLCTL_PLL_DIV1_DIV_SHIFT) - - - -/* PLL register group index macro definition */ -#define PLLCTL_PLL_PLL0 (0UL) -#define PLLCTL_PLL_PLL1 (1UL) -#define PLLCTL_PLL_PLL2 (2UL) -#define PLLCTL_PLL_PLL3 (3UL) -#define PLLCTL_PLL_PLL4 (4UL) - - -#endif /* HPM_PLLCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pmon_regs.h deleted file mode 100644 index 7e3a0798d2a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pmon_regs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMON_H -#define HPM_PMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[4]; - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - __RW uint32_t IRQ_FLAG; /* 0x40: */ - __RW uint32_t IRQ_ENABLE; /* 0x44: */ -} PMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define PMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define PMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define PMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ACTIVE_SHIFT) & PMON_MONITOR_CONTROL_ACTIVE_MASK) -#define PMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ACTIVE_MASK) >> PMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define PMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define PMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define PMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ENABLE_SHIFT) & PMON_MONITOR_CONTROL_ENABLE_MASK) -#define PMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ENABLE_MASK) >> PMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define PMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define PMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define PMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << PMON_MONITOR_STATUS_FLAG_SHIFT) & PMON_MONITOR_STATUS_FLAG_MASK) -#define PMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & PMON_MONITOR_STATUS_FLAG_MASK) >> PMON_MONITOR_STATUS_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_FLAG */ -/* - * FLAG (RW) - * - * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt - * 1: monitor interrupt happened - */ -#define PMON_IRQ_FLAG_FLAG_MASK (0xFU) -#define PMON_IRQ_FLAG_FLAG_SHIFT (0U) -#define PMON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << PMON_IRQ_FLAG_FLAG_SHIFT) & PMON_IRQ_FLAG_FLAG_MASK) -#define PMON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & PMON_IRQ_FLAG_FLAG_MASK) >> PMON_IRQ_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * ENABLE (RW) - * - * interrupt enable, each bit represents for one monitor - * 0: monitor interrupt disabled - * 1: monitor interrupt enabled - */ -#define PMON_IRQ_ENABLE_ENABLE_MASK (0xFU) -#define PMON_IRQ_ENABLE_ENABLE_SHIFT (0U) -#define PMON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PMON_IRQ_ENABLE_ENABLE_SHIFT) & PMON_IRQ_ENABLE_ENABLE_MASK) -#define PMON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PMON_IRQ_ENABLE_ENABLE_MASK) >> PMON_IRQ_ENABLE_ENABLE_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define PMON_MONITOR_GLITCH0 (0UL) -#define PMON_MONITOR_GLITCH1 (1UL) -#define PMON_MONITOR_CLOCK0 (2UL) -#define PMON_MONITOR_CLOCK1 (3UL) - - -#endif /* HPM_PMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ppor_regs.h deleted file mode 100644 index 7ce378b07da..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ppor_regs.h +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPOR_H -#define HPM_PPOR_H - -typedef struct { - __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ - __RW uint32_t RESET_STATUS; /* 0x4: reset source status */ - __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ - __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ - __RW uint32_t RESET_HOT; /* 0x10: reset type triggered by reset */ - __RW uint32_t RESET_COLD; /* 0x14: reset type attribute */ - __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ - __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ -} PPOR_Type; - - -/* Bitfield definition for register: RESET_FLAG */ -/* - * FLAG (W1C) - * - * reset reason of last hard reset, write 1 to clear each bit - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) -#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) -#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: RESET_STATUS */ -/* - * STATUS (RW) - * - * current status of reset sources - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) -#define PPOR_RESET_STATUS_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_STATUS_STATUS_SHIFT) & PPOR_RESET_STATUS_STATUS_MASK) -#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_HOLD */ -/* - * STATUS (RW) - * - * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_HOLD_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOLD_STATUS_SHIFT (0U) -#define PPOR_RESET_HOLD_STATUS_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_STATUS_SHIFT) & PPOR_RESET_HOLD_STATUS_MASK) -#define PPOR_RESET_HOLD_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_STATUS_MASK) >> PPOR_RESET_HOLD_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_ENABLE */ -/* - * ENABLE (RW) - * - * enable of reset sources - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) -#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) -#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) - -/* Bitfield definition for register: RESET_HOT */ -/* - * TYPE (RW) - * - * reset type of reset sources, 0 for cold/warm reset, all system control setting cleared including clock, ioc; 1 for hot reset, system control, ioc setting kept, peripheral setting cleared. - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_HOT_TYPE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOT_TYPE_SHIFT (0U) -#define PPOR_RESET_HOT_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_HOT_TYPE_SHIFT) & PPOR_RESET_HOT_TYPE_MASK) -#define PPOR_RESET_HOT_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_HOT_TYPE_MASK) >> PPOR_RESET_HOT_TYPE_SHIFT) - -/* Bitfield definition for register: RESET_COLD */ -/* - * FLAG (RW) - * - * perform cold or warm reset of chip, 0 for warm reset, fuse value and debug connection preserved; 1 for cold reset, fuse value reloaded and debug connection corrupted. This bit is ignored when hot reset selected - * 0: brownout - * 1: temperature(not available) - * 2: resetpin(not available) - * 4: debug reset - * 5: jtag reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2 - * 19: watch dog 3 - * 20: pmic watch dog - * 31: software - */ -#define PPOR_RESET_COLD_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_COLD_FLAG_SHIFT (0U) -#define PPOR_RESET_COLD_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_COLD_FLAG_SHIFT) & PPOR_RESET_COLD_FLAG_MASK) -#define PPOR_RESET_COLD_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_COLD_FLAG_MASK) >> PPOR_RESET_COLD_FLAG_SHIFT) - -/* Bitfield definition for register: SOFTWARE_RESET */ -/* - * COUNTER (RW) - * - * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - */ -#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) -#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) -#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) -#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) - - - - -#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_psec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_psec_regs.h deleted file mode 100644 index a848fbf5d13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_psec_regs.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PSEC_H -#define HPM_PSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ - __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ -} PSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define PSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define PSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define PSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_NSC_MASK) >> PSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define PSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define PSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define PSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_SEC_MASK) >> PSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * PMIC_FAIL (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define PSEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) -#define PSEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) >> PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) - -/* - * PMIC_NSC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define PSEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) -#define PSEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) -#define PSEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_NSC_SHIFT) & PSEC_SECURE_STATE_PMIC_NSC_MASK) -#define PSEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_NSC_MASK) >> PSEC_SECURE_STATE_PMIC_NSC_SHIFT) - -/* - * PMIC_SEC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define PSEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) -#define PSEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) -#define PSEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_SEC_SHIFT) & PSEC_SECURE_STATE_PMIC_SEC_MASK) -#define PSEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_SEC_MASK) >> PSEC_SECURE_STATE_PMIC_SEC_SHIFT) - -/* - * PMIC_INS (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define PSEC_SECURE_STATE_PMIC_INS_MASK (0x10U) -#define PSEC_SECURE_STATE_PMIC_INS_SHIFT (4U) -#define PSEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_INS_SHIFT) & PSEC_SECURE_STATE_PMIC_INS_MASK) -#define PSEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_INS_MASK) >> PSEC_SECURE_STATE_PMIC_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define PSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define PSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define PSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define PSEC_EVENT_EVENT_SHIFT (16U) -#define PSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & PSEC_EVENT_EVENT_MASK) >> PSEC_EVENT_EVENT_SHIFT) - -/* - * PMIC_ESC_NSC (RO) - * - * PMIC is escalating non-secure event - */ -#define PSEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) -#define PSEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) -#define PSEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_NSC_MASK) >> PSEC_EVENT_PMIC_ESC_NSC_SHIFT) - -/* - * PMIC_ESC_SEC (RO) - * - * PMIC is escalting secure event - */ -#define PSEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) -#define PSEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) -#define PSEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_SEC_MASK) >> PSEC_EVENT_PMIC_ESC_SEC_SHIFT) - -/* Bitfield definition for register: LIFECYCLE */ -/* - * LIFECYCLE (RO) - * - * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, - * bit0: lifecycle_unknow - */ -#define PSEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) -#define PSEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) -#define PSEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & PSEC_LIFECYCLE_LIFECYCLE_MASK) >> PSEC_LIFECYCLE_LIFECYCLE_SHIFT) - - - - -#endif /* HPM_PSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ptpc_regs.h deleted file mode 100644 index 5d9609c0c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_ptpc_regs.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PTPC_H -#define HPM_PTPC_H - -typedef struct { - struct { - __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ - __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ - __R uint32_t TIMEH; /* 0x8: timestamp high */ - __R uint32_t TIMEL; /* 0xC: timestamp low */ - __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ - __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ - __RW uint32_t ADDEND; /* 0x18: */ - __RW uint32_t TARH; /* 0x1C: */ - __RW uint32_t TARL; /* 0x20: */ - __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ - __RW uint32_t PPS_CTRL; /* 0x2C: */ - __R uint32_t CAPT_SNAPH; /* 0x30: */ - __RW uint32_t CAPT_SNAPL; /* 0x34: */ - __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ - } PTPC[2]; - __RW uint32_t TIME_SEL; /* 0x2000: */ - __W uint32_t INT_STS; /* 0x2004: */ - __RW uint32_t INT_EN; /* 0x2008: */ - __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ - __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ -} PTPC_Type; - - -/* Bitfield definition for register of struct array PTPC: CTRL0 */ -/* - * SUBSEC_DIGITAL_ROLLOVER (RW) - * - * Format for ns counter rollover, - * 1-digital, overflow time 1000000000/0x3B9ACA00 - * 0-binary, overflow time 0x7FFFFFFF - */ -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) - -/* - * CAPT_SNAP_KEEP (RW) - * - * set will keep capture snap till software read capt_snapl. - * If this bit is set, software should read capt_snaph first to avoid wrong result. - * If this bit is cleared, capture result will be updated at each capture event - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) - -/* - * CAPT_SNAP_POS_EN (RW) - * - * set will use posege of input capture signal to latch timestamp value - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) - -/* - * CAPT_SNAP_NEG_EN (RW) - * - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - -/* - * COMP_EN (RW) - * - * set to enable compare, will be cleared by HW when compare event triggered - */ -#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) -#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) -#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) -#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) - -/* - * UPDATE_TIMER (WO) - * - * update timer with +/- ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) - -/* - * INIT_TIMER (WO) - * - * initial timer with ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) -#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) - -/* - * FINE_COARSE_SEL (RW) - * - * 0: coarse update, ns counter add ss_incr[7:0] each clk - * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - */ -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - */ -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CTRL1 */ -/* - * SS_INCR (RW) - * - * constant value used to add ns counter; - * such as for 50MHz timer clock, set it to 8'd20 - */ -#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) -#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) -#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) -#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEH */ -/* - * TIMESTAMP_HIGH (RO) - * - */ -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEL */ -/* - * TIMESTAMP_LOW (RO) - * - */ -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ -/* - * SEC_UPDATE (RW) - * - * together with ts_updtl, used to initial or update timestamp - */ -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ -/* - * ADD_SUB (RW) - * - * 1 for sub; 0 for add, used only at update - */ -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) - -/* - * NS_UPDATE (RW) - * - */ -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: ADDEND */ -/* - * ADDEND (RW) - * - * used in fine update mode only - */ -#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) -#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) -#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARH */ -/* - * TARGET_TIME_HIGH (RW) - * - * used for generate compare signal if enabled - */ -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARL */ -/* - * TARGET_TIME_LOW (RW) - * - */ -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ -/* - * PPS_CTRL (RW) - * - */ -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ -/* - * CAPT_SNAP_HIGH (RO) - * - * take snapshot for input capture signal, at pos or neg or both; - * the result can be kept or updated at each event according to cfg0.bit8 - */ -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ -/* - * CAPT_SNAP_LOW (RW) - * - */ -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) - -/* Bitfield definition for register: TIME_SEL */ -/* - * CAN3_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) - -/* - * CAN2_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) - -/* - * CAN1_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) - -/* - * CAN0_TIME_SEL (RW) - * - * set to use ptpc1 for canx - * clr to use ptpc0 for canx - */ -#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * COMP_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) -#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) -#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) -#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) -#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * COMP_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) -#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) -#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) -#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) -#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: PTPC_CAN_TS_SEL */ -/* - * TSU_TBIN3_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) - -/* - * TSU_TBIN2_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) - -/* - * TSU_TBIN1_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) - -/* - * TSU_TBIN0_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) - - - -/* PTPC register group index macro definition */ -#define PTPC_PTPC_0 (0UL) -#define PTPC_PTPC_1 (1UL) - - -#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pwm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pwm_regs.h deleted file mode 100644 index d274aab733b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_pwm_regs.h +++ /dev/null @@ -1,938 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PWM_H -#define HPM_PWM_H - -typedef struct { - __RW uint32_t UNLK; /* 0x0: Shadow registers unlock register */ - union { - __RW uint32_t STA; /* 0x4: Counter start register */ - }; - union { - __RW uint32_t RLD; /* 0x8: Counter reload register */ - }; - union { - __RW uint32_t CMP[24]; /* 0xC - 0x68: Comparator register */ - }; - __R uint8_t RESERVED0[12]; /* 0x6C - 0x77: Reserved */ - __RW uint32_t FRCMD; /* 0x78: Force output mode register */ - __RW uint32_t SHLK; /* 0x7C: Shadow registers lock register */ - __RW uint32_t CHCFG[24]; /* 0x80 - 0xDC: Output channel configure register */ - __R uint8_t RESERVED1[16]; /* 0xE0 - 0xEF: Reserved */ - __RW uint32_t GCR; /* 0xF0: Global control register */ - __RW uint32_t SHCR; /* 0xF4: Shadow register control register */ - __R uint8_t RESERVED2[8]; /* 0xF8 - 0xFF: Reserved */ - __R uint32_t CAPPOS[24]; /* 0x100 - 0x15C: Capture rising edge register */ - __R uint8_t RESERVED3[16]; /* 0x160 - 0x16F: Reserved */ - __R uint32_t CNT; /* 0x170: Counter */ - __R uint8_t RESERVED4[12]; /* 0x174 - 0x17F: Reserved */ - __R uint32_t CAPNEG[24]; /* 0x180 - 0x1DC: Capture falling edge register */ - __R uint8_t RESERVED5[16]; /* 0x1E0 - 0x1EF: Reserved */ - __R uint32_t CNTCOPY; /* 0x1F0: Counter copy */ - __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ - __RW uint32_t PWMCFG[8]; /* 0x200 - 0x21C: PWM channel configure register */ - __W uint32_t SR; /* 0x220: Status register */ - __RW uint32_t IRQEN; /* 0x224: Interrupt request enable register */ - __R uint8_t RESERVED7[4]; /* 0x228 - 0x22B: Reserved */ - __RW uint32_t DMAEN; /* 0x22C: DMA request enable register */ - __RW uint32_t CMPCFG[24]; /* 0x230 - 0x28C: Comparator configure register */ -} PWM_Type; - - -/* Bitfield definition for register: UNLK */ -/* - * SHUNLK (RW) - * - * write 0xB0382607 to unlock the shadow registers of register offset from 0x04 to 0x78, - * otherwise the shadow registers can not be written. - */ -#define PWM_UNLK_SHUNLK_MASK (0xFFFFFFFFUL) -#define PWM_UNLK_SHUNLK_SHIFT (0U) -#define PWM_UNLK_SHUNLK_SET(x) (((uint32_t)(x) << PWM_UNLK_SHUNLK_SHIFT) & PWM_UNLK_SHUNLK_MASK) -#define PWM_UNLK_SHUNLK_GET(x) (((uint32_t)(x) & PWM_UNLK_SHUNLK_MASK) >> PWM_UNLK_SHUNLK_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * XSTA (RW) - * - * pwm timer counter extended start point, should back to this value after reach xrld - */ -#define PWM_STA_XSTA_MASK (0xF0000000UL) -#define PWM_STA_XSTA_SHIFT (28U) -#define PWM_STA_XSTA_SET(x) (((uint32_t)(x) << PWM_STA_XSTA_SHIFT) & PWM_STA_XSTA_MASK) -#define PWM_STA_XSTA_GET(x) (((uint32_t)(x) & PWM_STA_XSTA_MASK) >> PWM_STA_XSTA_SHIFT) - -/* - * STA (RW) - * - * pwm timer counter start value - * sta/rld will be loaded from shadow register to work register at main counter reload time, or software write unlk.shunlk - */ -#define PWM_STA_STA_MASK (0xFFFFFF0UL) -#define PWM_STA_STA_SHIFT (4U) -#define PWM_STA_STA_SET(x) (((uint32_t)(x) << PWM_STA_STA_SHIFT) & PWM_STA_STA_MASK) -#define PWM_STA_STA_GET(x) (((uint32_t)(x) & PWM_STA_STA_MASK) >> PWM_STA_STA_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * XRLD (RW) - * - * timeout counter extended reload point, counter will reload to xsta after reach this point - */ -#define PWM_RLD_XRLD_MASK (0xF0000000UL) -#define PWM_RLD_XRLD_SHIFT (28U) -#define PWM_RLD_XRLD_SET(x) (((uint32_t)(x) << PWM_RLD_XRLD_SHIFT) & PWM_RLD_XRLD_MASK) -#define PWM_RLD_XRLD_GET(x) (((uint32_t)(x) & PWM_RLD_XRLD_MASK) >> PWM_RLD_XRLD_SHIFT) - -/* - * RLD (RW) - * - * pwm timer counter reload value - */ -#define PWM_RLD_RLD_MASK (0xFFFFFF0UL) -#define PWM_RLD_RLD_SHIFT (4U) -#define PWM_RLD_RLD_SET(x) (((uint32_t)(x) << PWM_RLD_RLD_SHIFT) & PWM_RLD_RLD_MASK) -#define PWM_RLD_RLD_GET(x) (((uint32_t)(x) & PWM_RLD_RLD_MASK) >> PWM_RLD_RLD_SHIFT) - -/* Bitfield definition for register: 0 */ -/* - * XCMP (RW) - * - * extended counter compare value - */ -#define PWM_CMP_XCMP_MASK (0xF0000000UL) -#define PWM_CMP_XCMP_SHIFT (28U) -#define PWM_CMP_XCMP_SET(x) (((uint32_t)(x) << PWM_CMP_XCMP_SHIFT) & PWM_CMP_XCMP_MASK) -#define PWM_CMP_XCMP_GET(x) (((uint32_t)(x) & PWM_CMP_XCMP_MASK) >> PWM_CMP_XCMP_SHIFT) - -/* - * CMP (RW) - * - * clock counter compare value, the compare output is 0 at default, set to 1 when compare value meet, - * and clr to 0 when timer reload. Software can invert the output by setting chan_cfg.out_polarity. - */ -#define PWM_CMP_CMP_MASK (0xFFFFFF0UL) -#define PWM_CMP_CMP_SHIFT (4U) -#define PWM_CMP_CMP_SET(x) (((uint32_t)(x) << PWM_CMP_CMP_SHIFT) & PWM_CMP_CMP_MASK) -#define PWM_CMP_CMP_GET(x) (((uint32_t)(x) & PWM_CMP_CMP_MASK) >> PWM_CMP_CMP_SHIFT) - -/* - * CMPHLF (RW) - * - * half clock counter compare value - */ -#define PWM_CMP_CMPHLF_MASK (0x8U) -#define PWM_CMP_CMPHLF_SHIFT (3U) -#define PWM_CMP_CMPHLF_SET(x) (((uint32_t)(x) << PWM_CMP_CMPHLF_SHIFT) & PWM_CMP_CMPHLF_MASK) -#define PWM_CMP_CMPHLF_GET(x) (((uint32_t)(x) & PWM_CMP_CMPHLF_MASK) >> PWM_CMP_CMPHLF_SHIFT) - -/* - * CMPJIT (RW) - * - * jitter counter compare value - */ -#define PWM_CMP_CMPJIT_MASK (0x7U) -#define PWM_CMP_CMPJIT_SHIFT (0U) -#define PWM_CMP_CMPJIT_SET(x) (((uint32_t)(x) << PWM_CMP_CMPJIT_SHIFT) & PWM_CMP_CMPJIT_MASK) -#define PWM_CMP_CMPJIT_GET(x) (((uint32_t)(x) & PWM_CMP_CMPJIT_MASK) >> PWM_CMP_CMPJIT_SHIFT) - -/* Bitfield definition for register: FRCMD */ -/* - * FRCMD (RW) - * - * 2bit for each PWM output channel (0-7); - * 00: force output 0 - * 01: force output 1 - * 10: output highz - * 11: no force - */ -#define PWM_FRCMD_FRCMD_MASK (0xFFFFU) -#define PWM_FRCMD_FRCMD_SHIFT (0U) -#define PWM_FRCMD_FRCMD_SET(x) (((uint32_t)(x) << PWM_FRCMD_FRCMD_SHIFT) & PWM_FRCMD_FRCMD_MASK) -#define PWM_FRCMD_FRCMD_GET(x) (((uint32_t)(x) & PWM_FRCMD_FRCMD_MASK) >> PWM_FRCMD_FRCMD_SHIFT) - -/* Bitfield definition for register: SHLK */ -/* - * SHLK (RW) - * - * write 1 to lock all shawdow register, write access is not permitted - */ -#define PWM_SHLK_SHLK_MASK (0x80000000UL) -#define PWM_SHLK_SHLK_SHIFT (31U) -#define PWM_SHLK_SHLK_SET(x) (((uint32_t)(x) << PWM_SHLK_SHLK_SHIFT) & PWM_SHLK_SHLK_MASK) -#define PWM_SHLK_SHLK_GET(x) (((uint32_t)(x) & PWM_SHLK_SHLK_MASK) >> PWM_SHLK_SHLK_SHIFT) - -/* Bitfield definition for register array: CHCFG */ -/* - * CMPSELEND (RW) - * - * assign the last comparator for this output channel - */ -#define PWM_CHCFG_CMPSELEND_MASK (0x1F000000UL) -#define PWM_CHCFG_CMPSELEND_SHIFT (24U) -#define PWM_CHCFG_CMPSELEND_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELEND_SHIFT) & PWM_CHCFG_CMPSELEND_MASK) -#define PWM_CHCFG_CMPSELEND_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELEND_MASK) >> PWM_CHCFG_CMPSELEND_SHIFT) - -/* - * CMPSELBEG (RW) - * - * assign the first comparator for this output channel - */ -#define PWM_CHCFG_CMPSELBEG_MASK (0x1F0000UL) -#define PWM_CHCFG_CMPSELBEG_SHIFT (16U) -#define PWM_CHCFG_CMPSELBEG_SET(x) (((uint32_t)(x) << PWM_CHCFG_CMPSELBEG_SHIFT) & PWM_CHCFG_CMPSELBEG_MASK) -#define PWM_CHCFG_CMPSELBEG_GET(x) (((uint32_t)(x) & PWM_CHCFG_CMPSELBEG_MASK) >> PWM_CHCFG_CMPSELBEG_SHIFT) - -/* - * OUTPOL (RW) - * - * output polarity, set to 1 will invert the output - */ -#define PWM_CHCFG_OUTPOL_MASK (0x2U) -#define PWM_CHCFG_OUTPOL_SHIFT (1U) -#define PWM_CHCFG_OUTPOL_SET(x) (((uint32_t)(x) << PWM_CHCFG_OUTPOL_SHIFT) & PWM_CHCFG_OUTPOL_MASK) -#define PWM_CHCFG_OUTPOL_GET(x) (((uint32_t)(x) & PWM_CHCFG_OUTPOL_MASK) >> PWM_CHCFG_OUTPOL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * FAULTI3EN (RW) - * - * 1- enable the internal fault input 3 - */ -#define PWM_GCR_FAULTI3EN_MASK (0x80000000UL) -#define PWM_GCR_FAULTI3EN_SHIFT (31U) -#define PWM_GCR_FAULTI3EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI3EN_SHIFT) & PWM_GCR_FAULTI3EN_MASK) -#define PWM_GCR_FAULTI3EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI3EN_MASK) >> PWM_GCR_FAULTI3EN_SHIFT) - -/* - * FAULTI2EN (RW) - * - * 1- enable the internal fault input 2 - */ -#define PWM_GCR_FAULTI2EN_MASK (0x40000000UL) -#define PWM_GCR_FAULTI2EN_SHIFT (30U) -#define PWM_GCR_FAULTI2EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI2EN_SHIFT) & PWM_GCR_FAULTI2EN_MASK) -#define PWM_GCR_FAULTI2EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI2EN_MASK) >> PWM_GCR_FAULTI2EN_SHIFT) - -/* - * FAULTI1EN (RW) - * - * 1- enable the internal fault input 1 - */ -#define PWM_GCR_FAULTI1EN_MASK (0x20000000UL) -#define PWM_GCR_FAULTI1EN_SHIFT (29U) -#define PWM_GCR_FAULTI1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI1EN_SHIFT) & PWM_GCR_FAULTI1EN_MASK) -#define PWM_GCR_FAULTI1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI1EN_MASK) >> PWM_GCR_FAULTI1EN_SHIFT) - -/* - * FAULTI0EN (RW) - * - * 1- enable the internal fault input 0 - */ -#define PWM_GCR_FAULTI0EN_MASK (0x10000000UL) -#define PWM_GCR_FAULTI0EN_SHIFT (28U) -#define PWM_GCR_FAULTI0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTI0EN_SHIFT) & PWM_GCR_FAULTI0EN_MASK) -#define PWM_GCR_FAULTI0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTI0EN_MASK) >> PWM_GCR_FAULTI0EN_SHIFT) - -/* - * DEBUGFAULT (RW) - * - * 1- enable debug mode output protection - */ -#define PWM_GCR_DEBUGFAULT_MASK (0x8000000UL) -#define PWM_GCR_DEBUGFAULT_SHIFT (27U) -#define PWM_GCR_DEBUGFAULT_SET(x) (((uint32_t)(x) << PWM_GCR_DEBUGFAULT_SHIFT) & PWM_GCR_DEBUGFAULT_MASK) -#define PWM_GCR_DEBUGFAULT_GET(x) (((uint32_t)(x) & PWM_GCR_DEBUGFAULT_MASK) >> PWM_GCR_DEBUGFAULT_SHIFT) - -/* - * FRCPOL (RW) - * - * polarity of input pwm_force, - * 1- active low - * 0- active high - */ -#define PWM_GCR_FRCPOL_MASK (0x4000000UL) -#define PWM_GCR_FRCPOL_SHIFT (26U) -#define PWM_GCR_FRCPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FRCPOL_SHIFT) & PWM_GCR_FRCPOL_MASK) -#define PWM_GCR_FRCPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FRCPOL_MASK) >> PWM_GCR_FRCPOL_SHIFT) - -/* - * HWSHDWEDG (RW) - * - * When hardware event is selected as shawdow register effective time and the select comparator is configured as input capture mode. - * This bit assign its which edge is used as compare shadow register hardware load event. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_HWSHDWEDG_MASK (0x1000000UL) -#define PWM_GCR_HWSHDWEDG_SHIFT (24U) -#define PWM_GCR_HWSHDWEDG_SET(x) (((uint32_t)(x) << PWM_GCR_HWSHDWEDG_SHIFT) & PWM_GCR_HWSHDWEDG_MASK) -#define PWM_GCR_HWSHDWEDG_GET(x) (((uint32_t)(x) & PWM_GCR_HWSHDWEDG_MASK) >> PWM_GCR_HWSHDWEDG_SHIFT) - -/* - * CMPSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load comparator shadow registers - */ -#define PWM_GCR_CMPSHDWSEL_MASK (0xF80000UL) -#define PWM_GCR_CMPSHDWSEL_SHIFT (19U) -#define PWM_GCR_CMPSHDWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_CMPSHDWSEL_SHIFT) & PWM_GCR_CMPSHDWSEL_MASK) -#define PWM_GCR_CMPSHDWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_CMPSHDWSEL_MASK) >> PWM_GCR_CMPSHDWSEL_SHIFT) - -/* - * FAULTRECEDG (RW) - * - * When hardware load is selected as output fault recover trigger and the selected channel is capture mode. - * This bit assign its effective edge of fault recover trigger. - * 1- Falling edge - * 0- Rising edge - */ -#define PWM_GCR_FAULTRECEDG_MASK (0x40000UL) -#define PWM_GCR_FAULTRECEDG_SHIFT (18U) -#define PWM_GCR_FAULTRECEDG_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECEDG_SHIFT) & PWM_GCR_FAULTRECEDG_MASK) -#define PWM_GCR_FAULTRECEDG_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECEDG_MASK) >> PWM_GCR_FAULTRECEDG_SHIFT) - -/* - * FAULTRECHWSEL (RW) - * - * Selec one of the 24 comparators as fault output recover trigger. - */ -#define PWM_GCR_FAULTRECHWSEL_MASK (0x3E000UL) -#define PWM_GCR_FAULTRECHWSEL_SHIFT (13U) -#define PWM_GCR_FAULTRECHWSEL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTRECHWSEL_SHIFT) & PWM_GCR_FAULTRECHWSEL_MASK) -#define PWM_GCR_FAULTRECHWSEL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTRECHWSEL_MASK) >> PWM_GCR_FAULTRECHWSEL_SHIFT) - -/* - * FAULTE1EN (RW) - * - * 1- enable the external fault input 1 - */ -#define PWM_GCR_FAULTE1EN_MASK (0x1000U) -#define PWM_GCR_FAULTE1EN_SHIFT (12U) -#define PWM_GCR_FAULTE1EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE1EN_SHIFT) & PWM_GCR_FAULTE1EN_MASK) -#define PWM_GCR_FAULTE1EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE1EN_MASK) >> PWM_GCR_FAULTE1EN_SHIFT) - -/* - * FAULTE0EN (RW) - * - * 1- enable the external fault input 0 - */ -#define PWM_GCR_FAULTE0EN_MASK (0x800U) -#define PWM_GCR_FAULTE0EN_SHIFT (11U) -#define PWM_GCR_FAULTE0EN_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTE0EN_SHIFT) & PWM_GCR_FAULTE0EN_MASK) -#define PWM_GCR_FAULTE0EN_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTE0EN_MASK) >> PWM_GCR_FAULTE0EN_SHIFT) - -/* - * FAULTEXPOL (RW) - * - * external fault polarity - * 1-active low - * 0-active high - */ -#define PWM_GCR_FAULTEXPOL_MASK (0x600U) -#define PWM_GCR_FAULTEXPOL_SHIFT (9U) -#define PWM_GCR_FAULTEXPOL_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTEXPOL_SHIFT) & PWM_GCR_FAULTEXPOL_MASK) -#define PWM_GCR_FAULTEXPOL_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTEXPOL_MASK) >> PWM_GCR_FAULTEXPOL_SHIFT) - -/* - * RLDSYNCEN (RW) - * - * 1- pwm timer counter reset to reload value (rld) by synci is enabled - */ -#define PWM_GCR_RLDSYNCEN_MASK (0x100U) -#define PWM_GCR_RLDSYNCEN_SHIFT (8U) -#define PWM_GCR_RLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_RLDSYNCEN_SHIFT) & PWM_GCR_RLDSYNCEN_MASK) -#define PWM_GCR_RLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_RLDSYNCEN_MASK) >> PWM_GCR_RLDSYNCEN_SHIFT) - -/* - * CEN (RW) - * - * 1- enable the pwm timer counter - * 0- stop the pwm timer counter - */ -#define PWM_GCR_CEN_MASK (0x80U) -#define PWM_GCR_CEN_SHIFT (7U) -#define PWM_GCR_CEN_SET(x) (((uint32_t)(x) << PWM_GCR_CEN_SHIFT) & PWM_GCR_CEN_MASK) -#define PWM_GCR_CEN_GET(x) (((uint32_t)(x) & PWM_GCR_CEN_MASK) >> PWM_GCR_CEN_SHIFT) - -/* - * FAULTCLR (RW) - * - * 1- Write 1 to clear the fault condition. The output will recover if FAULTRECTIME is set to 2b'11. - * User should write 1 to this bit after the active FAULT signal de-assert and before it re-assert again. - */ -#define PWM_GCR_FAULTCLR_MASK (0x40U) -#define PWM_GCR_FAULTCLR_SHIFT (6U) -#define PWM_GCR_FAULTCLR_SET(x) (((uint32_t)(x) << PWM_GCR_FAULTCLR_SHIFT) & PWM_GCR_FAULTCLR_MASK) -#define PWM_GCR_FAULTCLR_GET(x) (((uint32_t)(x) & PWM_GCR_FAULTCLR_MASK) >> PWM_GCR_FAULTCLR_SHIFT) - -/* - * XRLDSYNCEN (RW) - * - * 1- pwm timer extended counter (xcnt) reset to extended reload value (xrld) by synci is enabled - */ -#define PWM_GCR_XRLDSYNCEN_MASK (0x20U) -#define PWM_GCR_XRLDSYNCEN_SHIFT (5U) -#define PWM_GCR_XRLDSYNCEN_SET(x) (((uint32_t)(x) << PWM_GCR_XRLDSYNCEN_SHIFT) & PWM_GCR_XRLDSYNCEN_MASK) -#define PWM_GCR_XRLDSYNCEN_GET(x) (((uint32_t)(x) & PWM_GCR_XRLDSYNCEN_MASK) >> PWM_GCR_XRLDSYNCEN_SHIFT) - -/* - * FRCTIME (WO) - * - * This bit field select the force effective time - * 00: force immediately - * 01: force at main counter reload time - * 10: force at FRCSYNCI - * 11: no force - */ -#define PWM_GCR_FRCTIME_MASK (0x6U) -#define PWM_GCR_FRCTIME_SHIFT (1U) -#define PWM_GCR_FRCTIME_SET(x) (((uint32_t)(x) << PWM_GCR_FRCTIME_SHIFT) & PWM_GCR_FRCTIME_MASK) -#define PWM_GCR_FRCTIME_GET(x) (((uint32_t)(x) & PWM_GCR_FRCTIME_MASK) >> PWM_GCR_FRCTIME_SHIFT) - -/* - * SWFRC (RW) - * - * 1- write 1 to enable software force, if the frcsrcsel is set to 0, force will take effect - */ -#define PWM_GCR_SWFRC_MASK (0x1U) -#define PWM_GCR_SWFRC_SHIFT (0U) -#define PWM_GCR_SWFRC_SET(x) (((uint32_t)(x) << PWM_GCR_SWFRC_SHIFT) & PWM_GCR_SWFRC_MASK) -#define PWM_GCR_SWFRC_GET(x) (((uint32_t)(x) & PWM_GCR_SWFRC_MASK) >> PWM_GCR_SWFRC_SHIFT) - -/* Bitfield definition for register: SHCR */ -/* - * FRCSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load FRCMD shadow registers - */ -#define PWM_SHCR_FRCSHDWSEL_MASK (0x1F00U) -#define PWM_SHCR_FRCSHDWSEL_SHIFT (8U) -#define PWM_SHCR_FRCSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_FRCSHDWSEL_SHIFT) & PWM_SHCR_FRCSHDWSEL_MASK) -#define PWM_SHCR_FRCSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_FRCSHDWSEL_MASK) >> PWM_SHCR_FRCSHDWSEL_SHIFT) - -/* - * CNTSHDWSEL (RW) - * - * This bitfield select one of the comparators as hardware event time to load the counter related shadow registers (STA and RLD) - */ -#define PWM_SHCR_CNTSHDWSEL_MASK (0xF8U) -#define PWM_SHCR_CNTSHDWSEL_SHIFT (3U) -#define PWM_SHCR_CNTSHDWSEL_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWSEL_SHIFT) & PWM_SHCR_CNTSHDWSEL_MASK) -#define PWM_SHCR_CNTSHDWSEL_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWSEL_MASK) >> PWM_SHCR_CNTSHDWSEL_SHIFT) - -/* - * CNTSHDWUPT (RW) - * - * This bitfield select when the counter related shadow registers (STA and RLD) will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_SHCR_CNTSHDWUPT_MASK (0x6U) -#define PWM_SHCR_CNTSHDWUPT_SHIFT (1U) -#define PWM_SHCR_CNTSHDWUPT_SET(x) (((uint32_t)(x) << PWM_SHCR_CNTSHDWUPT_SHIFT) & PWM_SHCR_CNTSHDWUPT_MASK) -#define PWM_SHCR_CNTSHDWUPT_GET(x) (((uint32_t)(x) & PWM_SHCR_CNTSHDWUPT_MASK) >> PWM_SHCR_CNTSHDWUPT_SHIFT) - -/* - * SHLKEN (RW) - * - * 1- enable shadow registers lock feature, - * 0- disable shadow registers lock, shlk bit will always be 0 - */ -#define PWM_SHCR_SHLKEN_MASK (0x1U) -#define PWM_SHCR_SHLKEN_SHIFT (0U) -#define PWM_SHCR_SHLKEN_SET(x) (((uint32_t)(x) << PWM_SHCR_SHLKEN_SHIFT) & PWM_SHCR_SHLKEN_MASK) -#define PWM_SHCR_SHLKEN_GET(x) (((uint32_t)(x) & PWM_SHCR_SHLKEN_MASK) >> PWM_SHCR_SHLKEN_SHIFT) - -/* Bitfield definition for register array: CAPPOS */ -/* - * CAPPOS (RO) - * - * counter value captured at input posedge - */ -#define PWM_CAPPOS_CAPPOS_MASK (0xFFFFFFF0UL) -#define PWM_CAPPOS_CAPPOS_SHIFT (4U) -#define PWM_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & PWM_CAPPOS_CAPPOS_MASK) >> PWM_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNT_XCNT_MASK (0xF0000000UL) -#define PWM_CNT_XCNT_SHIFT (28U) -#define PWM_CNT_XCNT_GET(x) (((uint32_t)(x) & PWM_CNT_XCNT_MASK) >> PWM_CNT_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNT_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNT_CNT_SHIFT (4U) -#define PWM_CNT_CNT_GET(x) (((uint32_t)(x) & PWM_CNT_CNT_MASK) >> PWM_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CAPNEG */ -/* - * CAPNEG (RO) - * - * counter value captured at input signal falling edge - */ -#define PWM_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define PWM_CAPNEG_CAPNEG_SHIFT (0U) -#define PWM_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & PWM_CAPNEG_CAPNEG_MASK) >> PWM_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register: CNTCOPY */ -/* - * XCNT (RO) - * - * current extended counter value - */ -#define PWM_CNTCOPY_XCNT_MASK (0xF0000000UL) -#define PWM_CNTCOPY_XCNT_SHIFT (28U) -#define PWM_CNTCOPY_XCNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_XCNT_MASK) >> PWM_CNTCOPY_XCNT_SHIFT) - -/* - * CNT (RO) - * - * current clock counter value - */ -#define PWM_CNTCOPY_CNT_MASK (0xFFFFFF0UL) -#define PWM_CNTCOPY_CNT_SHIFT (4U) -#define PWM_CNTCOPY_CNT_GET(x) (((uint32_t)(x) & PWM_CNTCOPY_CNT_MASK) >> PWM_CNTCOPY_CNT_SHIFT) - -/* Bitfield definition for register array: PWMCFG */ -/* - * OEN (RW) - * - * PWM output enable - * 1- output is enabled - * 0- output is disabled - */ -#define PWM_PWMCFG_OEN_MASK (0x10000000UL) -#define PWM_PWMCFG_OEN_SHIFT (28U) -#define PWM_PWMCFG_OEN_SET(x) (((uint32_t)(x) << PWM_PWMCFG_OEN_SHIFT) & PWM_PWMCFG_OEN_MASK) -#define PWM_PWMCFG_OEN_GET(x) (((uint32_t)(x) & PWM_PWMCFG_OEN_MASK) >> PWM_PWMCFG_OEN_SHIFT) - -/* - * FRCSHDWUPT (RW) - * - * This bitfield select when the FRCMD shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_PWMCFG_FRCSHDWUPT_MASK (0xC000000UL) -#define PWM_PWMCFG_FRCSHDWUPT_SHIFT (26U) -#define PWM_PWMCFG_FRCSHDWUPT_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSHDWUPT_SHIFT) & PWM_PWMCFG_FRCSHDWUPT_MASK) -#define PWM_PWMCFG_FRCSHDWUPT_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSHDWUPT_MASK) >> PWM_PWMCFG_FRCSHDWUPT_SHIFT) - -/* - * FAULTMODE (RW) - * - * This bitfield defines the PWM output status when fault condition happen - * 00: force output 0 - * 01: force output 1 - * 1x: output highz - */ -#define PWM_PWMCFG_FAULTMODE_MASK (0x3000000UL) -#define PWM_PWMCFG_FAULTMODE_SHIFT (24U) -#define PWM_PWMCFG_FAULTMODE_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTMODE_SHIFT) & PWM_PWMCFG_FAULTMODE_MASK) -#define PWM_PWMCFG_FAULTMODE_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTMODE_MASK) >> PWM_PWMCFG_FAULTMODE_SHIFT) - -/* - * FAULTRECTIME (RW) - * - * This bitfield select when to recover PWM output after fault condition removed. - * 00: immediately - * 01: after pwm timer counter reload time - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after software write faultclr bit in GCR register - */ -#define PWM_PWMCFG_FAULTRECTIME_MASK (0xC00000UL) -#define PWM_PWMCFG_FAULTRECTIME_SHIFT (22U) -#define PWM_PWMCFG_FAULTRECTIME_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FAULTRECTIME_SHIFT) & PWM_PWMCFG_FAULTRECTIME_MASK) -#define PWM_PWMCFG_FAULTRECTIME_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FAULTRECTIME_MASK) >> PWM_PWMCFG_FAULTRECTIME_SHIFT) - -/* - * FRCSRCSEL (RW) - * - * Select sources for force output - * 0- force output is enabled when FRCI assert - * 1- force output is enabled by software write swfrc to 1 - */ -#define PWM_PWMCFG_FRCSRCSEL_MASK (0x200000UL) -#define PWM_PWMCFG_FRCSRCSEL_SHIFT (21U) -#define PWM_PWMCFG_FRCSRCSEL_SET(x) (((uint32_t)(x) << PWM_PWMCFG_FRCSRCSEL_SHIFT) & PWM_PWMCFG_FRCSRCSEL_MASK) -#define PWM_PWMCFG_FRCSRCSEL_GET(x) (((uint32_t)(x) & PWM_PWMCFG_FRCSRCSEL_MASK) >> PWM_PWMCFG_FRCSRCSEL_SHIFT) - -/* - * PAIR (RW) - * - * 1- PWM output is in pair mode. Note the two PWM outputs need to be both set to pair mode. - * 0- PWM output is in indepandent mode. - */ -#define PWM_PWMCFG_PAIR_MASK (0x100000UL) -#define PWM_PWMCFG_PAIR_SHIFT (20U) -#define PWM_PWMCFG_PAIR_SET(x) (((uint32_t)(x) << PWM_PWMCFG_PAIR_SHIFT) & PWM_PWMCFG_PAIR_MASK) -#define PWM_PWMCFG_PAIR_GET(x) (((uint32_t)(x) & PWM_PWMCFG_PAIR_MASK) >> PWM_PWMCFG_PAIR_SHIFT) - -/* - * DEADAREA (RW) - * - * This bitfield define the PWM pair deadarea length. The unit is 0.5 cycle. The minimum length of deadarea is 1 cycle. - * Note: user should configure pair bit and this bitfield before PWM output is enabled. - */ -#define PWM_PWMCFG_DEADAREA_MASK (0xFFFFFUL) -#define PWM_PWMCFG_DEADAREA_SHIFT (0U) -#define PWM_PWMCFG_DEADAREA_SET(x) (((uint32_t)(x) << PWM_PWMCFG_DEADAREA_SHIFT) & PWM_PWMCFG_DEADAREA_MASK) -#define PWM_PWMCFG_DEADAREA_GET(x) (((uint32_t)(x) & PWM_PWMCFG_DEADAREA_MASK) >> PWM_PWMCFG_DEADAREA_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * FAULTF (W1C) - * - * fault condition flag - */ -#define PWM_SR_FAULTF_MASK (0x8000000UL) -#define PWM_SR_FAULTF_SHIFT (27U) -#define PWM_SR_FAULTF_SET(x) (((uint32_t)(x) << PWM_SR_FAULTF_SHIFT) & PWM_SR_FAULTF_MASK) -#define PWM_SR_FAULTF_GET(x) (((uint32_t)(x) & PWM_SR_FAULTF_MASK) >> PWM_SR_FAULTF_SHIFT) - -/* - * XRLDF (W1C) - * - * extended reload flag, this flag set when xcnt count to xrld value or when SYNCI assert - */ -#define PWM_SR_XRLDF_MASK (0x4000000UL) -#define PWM_SR_XRLDF_SHIFT (26U) -#define PWM_SR_XRLDF_SET(x) (((uint32_t)(x) << PWM_SR_XRLDF_SHIFT) & PWM_SR_XRLDF_MASK) -#define PWM_SR_XRLDF_GET(x) (((uint32_t)(x) & PWM_SR_XRLDF_MASK) >> PWM_SR_XRLDF_SHIFT) - -/* - * HALFRLDF (W1C) - * - * half reload flag, this flag set when cnt count to rld/2 - */ -#define PWM_SR_HALFRLDF_MASK (0x2000000UL) -#define PWM_SR_HALFRLDF_SHIFT (25U) -#define PWM_SR_HALFRLDF_SET(x) (((uint32_t)(x) << PWM_SR_HALFRLDF_SHIFT) & PWM_SR_HALFRLDF_MASK) -#define PWM_SR_HALFRLDF_GET(x) (((uint32_t)(x) & PWM_SR_HALFRLDF_MASK) >> PWM_SR_HALFRLDF_SHIFT) - -/* - * RLDF (W1C) - * - * reload flag, this flag set when cnt count to rld value or when SYNCI assert - */ -#define PWM_SR_RLDF_MASK (0x1000000UL) -#define PWM_SR_RLDF_SHIFT (24U) -#define PWM_SR_RLDF_SET(x) (((uint32_t)(x) << PWM_SR_RLDF_SHIFT) & PWM_SR_RLDF_MASK) -#define PWM_SR_RLDF_GET(x) (((uint32_t)(x) & PWM_SR_RLDF_MASK) >> PWM_SR_RLDF_SHIFT) - -/* - * CMPFX (W1C) - * - * comparator output compare or input capture flag - */ -#define PWM_SR_CMPFX_MASK (0xFFFFFFUL) -#define PWM_SR_CMPFX_SHIFT (0U) -#define PWM_SR_CMPFX_SET(x) (((uint32_t)(x) << PWM_SR_CMPFX_SHIFT) & PWM_SR_CMPFX_MASK) -#define PWM_SR_CMPFX_GET(x) (((uint32_t)(x) & PWM_SR_CMPFX_MASK) >> PWM_SR_CMPFX_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * FAULTIRQE (RW) - * - * fault condition interrupt enable - */ -#define PWM_IRQEN_FAULTIRQE_MASK (0x8000000UL) -#define PWM_IRQEN_FAULTIRQE_SHIFT (27U) -#define PWM_IRQEN_FAULTIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_FAULTIRQE_SHIFT) & PWM_IRQEN_FAULTIRQE_MASK) -#define PWM_IRQEN_FAULTIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_FAULTIRQE_MASK) >> PWM_IRQEN_FAULTIRQE_SHIFT) - -/* - * XRLDIRQE (RW) - * - * extended reload flag interrupt enable - */ -#define PWM_IRQEN_XRLDIRQE_MASK (0x4000000UL) -#define PWM_IRQEN_XRLDIRQE_SHIFT (26U) -#define PWM_IRQEN_XRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_XRLDIRQE_SHIFT) & PWM_IRQEN_XRLDIRQE_MASK) -#define PWM_IRQEN_XRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_XRLDIRQE_MASK) >> PWM_IRQEN_XRLDIRQE_SHIFT) - -/* - * HALFRLDIRQE (RW) - * - * half reload flag interrupt enable - */ -#define PWM_IRQEN_HALFRLDIRQE_MASK (0x2000000UL) -#define PWM_IRQEN_HALFRLDIRQE_SHIFT (25U) -#define PWM_IRQEN_HALFRLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_HALFRLDIRQE_SHIFT) & PWM_IRQEN_HALFRLDIRQE_MASK) -#define PWM_IRQEN_HALFRLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_HALFRLDIRQE_MASK) >> PWM_IRQEN_HALFRLDIRQE_SHIFT) - -/* - * RLDIRQE (RW) - * - * reload flag interrupt enable - */ -#define PWM_IRQEN_RLDIRQE_MASK (0x1000000UL) -#define PWM_IRQEN_RLDIRQE_SHIFT (24U) -#define PWM_IRQEN_RLDIRQE_SET(x) (((uint32_t)(x) << PWM_IRQEN_RLDIRQE_SHIFT) & PWM_IRQEN_RLDIRQE_MASK) -#define PWM_IRQEN_RLDIRQE_GET(x) (((uint32_t)(x) & PWM_IRQEN_RLDIRQE_MASK) >> PWM_IRQEN_RLDIRQE_SHIFT) - -/* - * CMPIRQEX (RW) - * - * comparator output compare or input capture flag interrupt enable - */ -#define PWM_IRQEN_CMPIRQEX_MASK (0xFFFFFFUL) -#define PWM_IRQEN_CMPIRQEX_SHIFT (0U) -#define PWM_IRQEN_CMPIRQEX_SET(x) (((uint32_t)(x) << PWM_IRQEN_CMPIRQEX_SHIFT) & PWM_IRQEN_CMPIRQEX_MASK) -#define PWM_IRQEN_CMPIRQEX_GET(x) (((uint32_t)(x) & PWM_IRQEN_CMPIRQEX_MASK) >> PWM_IRQEN_CMPIRQEX_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * FAULTEN (RW) - * - * fault condition DMA request enable - */ -#define PWM_DMAEN_FAULTEN_MASK (0x8000000UL) -#define PWM_DMAEN_FAULTEN_SHIFT (27U) -#define PWM_DMAEN_FAULTEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_FAULTEN_SHIFT) & PWM_DMAEN_FAULTEN_MASK) -#define PWM_DMAEN_FAULTEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_FAULTEN_MASK) >> PWM_DMAEN_FAULTEN_SHIFT) - -/* - * XRLDEN (RW) - * - * extended reload flag DMA request enable - */ -#define PWM_DMAEN_XRLDEN_MASK (0x4000000UL) -#define PWM_DMAEN_XRLDEN_SHIFT (26U) -#define PWM_DMAEN_XRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_XRLDEN_SHIFT) & PWM_DMAEN_XRLDEN_MASK) -#define PWM_DMAEN_XRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_XRLDEN_MASK) >> PWM_DMAEN_XRLDEN_SHIFT) - -/* - * HALFRLDEN (RW) - * - * half reload flag DMA request enable - */ -#define PWM_DMAEN_HALFRLDEN_MASK (0x2000000UL) -#define PWM_DMAEN_HALFRLDEN_SHIFT (25U) -#define PWM_DMAEN_HALFRLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_HALFRLDEN_SHIFT) & PWM_DMAEN_HALFRLDEN_MASK) -#define PWM_DMAEN_HALFRLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_HALFRLDEN_MASK) >> PWM_DMAEN_HALFRLDEN_SHIFT) - -/* - * RLDEN (RW) - * - * reload flag DMA request enable - */ -#define PWM_DMAEN_RLDEN_MASK (0x1000000UL) -#define PWM_DMAEN_RLDEN_SHIFT (24U) -#define PWM_DMAEN_RLDEN_SET(x) (((uint32_t)(x) << PWM_DMAEN_RLDEN_SHIFT) & PWM_DMAEN_RLDEN_MASK) -#define PWM_DMAEN_RLDEN_GET(x) (((uint32_t)(x) & PWM_DMAEN_RLDEN_MASK) >> PWM_DMAEN_RLDEN_SHIFT) - -/* - * CMPENX (RW) - * - * comparator output compare or input capture flag DMA request enable - */ -#define PWM_DMAEN_CMPENX_MASK (0xFFFFFFUL) -#define PWM_DMAEN_CMPENX_SHIFT (0U) -#define PWM_DMAEN_CMPENX_SET(x) (((uint32_t)(x) << PWM_DMAEN_CMPENX_SHIFT) & PWM_DMAEN_CMPENX_MASK) -#define PWM_DMAEN_CMPENX_GET(x) (((uint32_t)(x) & PWM_DMAEN_CMPENX_MASK) >> PWM_DMAEN_CMPENX_SHIFT) - -/* Bitfield definition for register array: CMPCFG */ -/* - * XCNTCMPEN (RW) - * - * This bitfield enable the comparator to compare xcmp with xcnt. - */ -#define PWM_CMPCFG_XCNTCMPEN_MASK (0xF0U) -#define PWM_CMPCFG_XCNTCMPEN_SHIFT (4U) -#define PWM_CMPCFG_XCNTCMPEN_SET(x) (((uint32_t)(x) << PWM_CMPCFG_XCNTCMPEN_SHIFT) & PWM_CMPCFG_XCNTCMPEN_MASK) -#define PWM_CMPCFG_XCNTCMPEN_GET(x) (((uint32_t)(x) & PWM_CMPCFG_XCNTCMPEN_MASK) >> PWM_CMPCFG_XCNTCMPEN_SHIFT) - -/* - * CMPSHDWUPT (RW) - * - * This bitfield select when the comparator shadow register will be loaded to its work register - * 00: after software set shlk bit of shlk register - * 01: immediately after the register being modified - * 10: after hardware event assert, user can select one of the comparators to generate this hardware event. - * The comparator can be either output compare mode or input capture mode. - * 11: after SHSYNCI assert - */ -#define PWM_CMPCFG_CMPSHDWUPT_MASK (0xCU) -#define PWM_CMPCFG_CMPSHDWUPT_SHIFT (2U) -#define PWM_CMPCFG_CMPSHDWUPT_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPSHDWUPT_SHIFT) & PWM_CMPCFG_CMPSHDWUPT_MASK) -#define PWM_CMPCFG_CMPSHDWUPT_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPSHDWUPT_MASK) >> PWM_CMPCFG_CMPSHDWUPT_SHIFT) - -/* - * CMPMODE (RW) - * - * comparator mode - * 0- output compare mode - * 1- input capture mode - */ -#define PWM_CMPCFG_CMPMODE_MASK (0x2U) -#define PWM_CMPCFG_CMPMODE_SHIFT (1U) -#define PWM_CMPCFG_CMPMODE_SET(x) (((uint32_t)(x) << PWM_CMPCFG_CMPMODE_SHIFT) & PWM_CMPCFG_CMPMODE_MASK) -#define PWM_CMPCFG_CMPMODE_GET(x) (((uint32_t)(x) & PWM_CMPCFG_CMPMODE_MASK) >> PWM_CMPCFG_CMPMODE_SHIFT) - - - -/* CMP register group index macro definition */ -#define PWM_CMP_0 (0UL) -#define PWM_CMP_1 (1UL) -#define PWM_CMP_2 (2UL) -#define PWM_CMP_3 (3UL) -#define PWM_CMP_4 (4UL) -#define PWM_CMP_5 (5UL) -#define PWM_CMP_6 (6UL) -#define PWM_CMP_7 (7UL) -#define PWM_CMP_8 (8UL) -#define PWM_CMP_9 (9UL) -#define PWM_CMP_10 (10UL) -#define PWM_CMP_11 (11UL) -#define PWM_CMP_12 (12UL) -#define PWM_CMP_13 (13UL) -#define PWM_CMP_14 (14UL) -#define PWM_CMP_15 (15UL) -#define PWM_CMP_16 (16UL) -#define PWM_CMP_17 (17UL) -#define PWM_CMP_18 (18UL) -#define PWM_CMP_19 (19UL) -#define PWM_CMP_20 (20UL) -#define PWM_CMP_21 (21UL) -#define PWM_CMP_22 (22UL) -#define PWM_CMP_23 (23UL) - -/* CHCFG register group index macro definition */ -#define PWM_CHCFG_0 (0UL) -#define PWM_CHCFG_1 (1UL) -#define PWM_CHCFG_2 (2UL) -#define PWM_CHCFG_3 (3UL) -#define PWM_CHCFG_4 (4UL) -#define PWM_CHCFG_5 (5UL) -#define PWM_CHCFG_6 (6UL) -#define PWM_CHCFG_7 (7UL) -#define PWM_CHCFG_8 (8UL) -#define PWM_CHCFG_9 (9UL) -#define PWM_CHCFG_10 (10UL) -#define PWM_CHCFG_11 (11UL) -#define PWM_CHCFG_12 (12UL) -#define PWM_CHCFG_13 (13UL) -#define PWM_CHCFG_14 (14UL) -#define PWM_CHCFG_15 (15UL) -#define PWM_CHCFG_16 (16UL) -#define PWM_CHCFG_17 (17UL) -#define PWM_CHCFG_18 (18UL) -#define PWM_CHCFG_19 (19UL) -#define PWM_CHCFG_20 (20UL) -#define PWM_CHCFG_21 (21UL) -#define PWM_CHCFG_22 (22UL) -#define PWM_CHCFG_23 (23UL) - -/* CAPPOS register group index macro definition */ -#define PWM_CAPPOS_0 (0UL) -#define PWM_CAPPOS_1 (1UL) -#define PWM_CAPPOS_2 (2UL) -#define PWM_CAPPOS_3 (3UL) -#define PWM_CAPPOS_4 (4UL) -#define PWM_CAPPOS_5 (5UL) -#define PWM_CAPPOS_6 (6UL) -#define PWM_CAPPOS_7 (7UL) -#define PWM_CAPPOS_8 (8UL) -#define PWM_CAPPOS_9 (9UL) -#define PWM_CAPPOS_10 (10UL) -#define PWM_CAPPOS_11 (11UL) -#define PWM_CAPPOS_12 (12UL) -#define PWM_CAPPOS_13 (13UL) -#define PWM_CAPPOS_14 (14UL) -#define PWM_CAPPOS_15 (15UL) -#define PWM_CAPPOS_16 (16UL) -#define PWM_CAPPOS_17 (17UL) -#define PWM_CAPPOS_18 (18UL) -#define PWM_CAPPOS_19 (19UL) -#define PWM_CAPPOS_20 (20UL) -#define PWM_CAPPOS_21 (21UL) -#define PWM_CAPPOS_22 (22UL) -#define PWM_CAPPOS_23 (23UL) - -/* CAPNEG register group index macro definition */ -#define PWM_CAPNEG_0 (0UL) -#define PWM_CAPNEG_1 (1UL) -#define PWM_CAPNEG_2 (2UL) -#define PWM_CAPNEG_3 (3UL) -#define PWM_CAPNEG_4 (4UL) -#define PWM_CAPNEG_5 (5UL) -#define PWM_CAPNEG_6 (6UL) -#define PWM_CAPNEG_7 (7UL) -#define PWM_CAPNEG_8 (8UL) -#define PWM_CAPNEG_9 (9UL) -#define PWM_CAPNEG_10 (10UL) -#define PWM_CAPNEG_11 (11UL) -#define PWM_CAPNEG_12 (12UL) -#define PWM_CAPNEG_13 (13UL) -#define PWM_CAPNEG_14 (14UL) -#define PWM_CAPNEG_15 (15UL) -#define PWM_CAPNEG_16 (16UL) -#define PWM_CAPNEG_17 (17UL) -#define PWM_CAPNEG_18 (18UL) -#define PWM_CAPNEG_19 (19UL) -#define PWM_CAPNEG_20 (20UL) -#define PWM_CAPNEG_21 (21UL) -#define PWM_CAPNEG_22 (22UL) -#define PWM_CAPNEG_23 (23UL) - -/* PWMCFG register group index macro definition */ -#define PWM_PWMCFG_0 (0UL) -#define PWM_PWMCFG_1 (1UL) -#define PWM_PWMCFG_2 (2UL) -#define PWM_PWMCFG_3 (3UL) -#define PWM_PWMCFG_4 (4UL) -#define PWM_PWMCFG_5 (5UL) -#define PWM_PWMCFG_6 (6UL) -#define PWM_PWMCFG_7 (7UL) - -/* CMPCFG register group index macro definition */ -#define PWM_CMPCFG_CMPCFG0 (0UL) -#define PWM_CMPCFG_1 (1UL) -#define PWM_CMPCFG_2 (2UL) -#define PWM_CMPCFG_3 (3UL) -#define PWM_CMPCFG_4 (4UL) -#define PWM_CMPCFG_5 (5UL) -#define PWM_CMPCFG_6 (6UL) -#define PWM_CMPCFG_7 (7UL) -#define PWM_CMPCFG_8 (8UL) -#define PWM_CMPCFG_9 (9UL) -#define PWM_CMPCFG_10 (10UL) -#define PWM_CMPCFG_11 (11UL) -#define PWM_CMPCFG_12 (12UL) -#define PWM_CMPCFG_13 (13UL) -#define PWM_CMPCFG_14 (14UL) -#define PWM_CMPCFG_15 (15UL) -#define PWM_CMPCFG_16 (16UL) -#define PWM_CMPCFG_17 (17UL) -#define PWM_CMPCFG_18 (18UL) -#define PWM_CMPCFG_19 (19UL) -#define PWM_CMPCFG_20 (20UL) -#define PWM_CMPCFG_21 (21UL) -#define PWM_CMPCFG_22 (22UL) -#define PWM_CMPCFG_23 (23UL) - - -#endif /* HPM_PWM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_qei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_qei_regs.h deleted file mode 100644 index cafcdfe2851..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_qei_regs.h +++ /dev/null @@ -1,636 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEI_H -#define HPM_QEI_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t PHIDX; /* 0xC: Phase index register */ - __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __RW uint32_t ZCMP; /* 0x18: Z comparator */ - __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ - __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ - __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ - struct { - __RW uint32_t Z; /* 0x30: Z counter */ - __R uint32_t PH; /* 0x34: Phase counter */ - __RW uint32_t SPD; /* 0x38: Speed counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - __R uint32_t SPDHIS[4]; /* 0x70 - 0x7C: Speed history */ -} QEI_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define QEI_CR_READ_MASK (0x80000000UL) -#define QEI_CR_READ_SHIFT (31U) -#define QEI_CR_READ_SET(x) (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK) -#define QEI_CR_READ_GET(x) (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT) - -/* - * HRSTSPD (RW) - * - * 1- reset spdcnt when H assert - */ -#define QEI_CR_HRSTSPD_MASK (0x40000UL) -#define QEI_CR_HRSTSPD_SHIFT (18U) -#define QEI_CR_HRSTSPD_SET(x) (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK) -#define QEI_CR_HRSTSPD_GET(x) (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT) - -/* - * HRSTPH (RW) - * - * 1- reset phcnt when H assert - */ -#define QEI_CR_HRSTPH_MASK (0x20000UL) -#define QEI_CR_HRSTPH_SHIFT (17U) -#define QEI_CR_HRSTPH_SET(x) (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK) -#define QEI_CR_HRSTPH_GET(x) (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT) - -/* - * HRSTZ (RW) - * - * 1- reset zcnt when H assert - */ -#define QEI_CR_HRSTZ_MASK (0x10000UL) -#define QEI_CR_HRSTZ_SHIFT (16U) -#define QEI_CR_HRSTZ_SET(x) (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK) -#define QEI_CR_HRSTZ_GET(x) (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT) - -/* - * PAUSESPD (RW) - * - * 1- pause spdcnt when PAUSE assert - */ -#define QEI_CR_PAUSESPD_MASK (0x4000U) -#define QEI_CR_PAUSESPD_SHIFT (14U) -#define QEI_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK) -#define QEI_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT) - -/* - * PAUSEPH (RW) - * - * 1- pause phcnt when PAUSE assert - */ -#define QEI_CR_PAUSEPH_MASK (0x2000U) -#define QEI_CR_PAUSEPH_SHIFT (13U) -#define QEI_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK) -#define QEI_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT) - -/* - * PAUSEZ (RW) - * - * 1- pause zcnt when PAUSE assert - */ -#define QEI_CR_PAUSEZ_MASK (0x1000U) -#define QEI_CR_PAUSEZ_SHIFT (12U) -#define QEI_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK) -#define QEI_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT) - -/* - * HRDIR1 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - */ -#define QEI_CR_HRDIR1_MASK (0x800U) -#define QEI_CR_HRDIR1_SHIFT (11U) -#define QEI_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK) -#define QEI_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT) - -/* - * HRDIR0 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - */ -#define QEI_CR_HRDIR0_MASK (0x400U) -#define QEI_CR_HRDIR0_SHIFT (10U) -#define QEI_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK) -#define QEI_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT) - -/* - * HFDIR1 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - */ -#define QEI_CR_HFDIR1_MASK (0x200U) -#define QEI_CR_HFDIR1_SHIFT (9U) -#define QEI_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK) -#define QEI_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT) - -/* - * HFDIR0 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - */ -#define QEI_CR_HFDIR0_MASK (0x100U) -#define QEI_CR_HFDIR0_SHIFT (8U) -#define QEI_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK) -#define QEI_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - */ -#define QEI_CR_SNAPEN_MASK (0x20U) -#define QEI_CR_SNAPEN_SHIFT (5U) -#define QEI_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK) -#define QEI_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - */ -#define QEI_CR_RSTCNT_MASK (0x10U) -#define QEI_CR_RSTCNT_SHIFT (4U) -#define QEI_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK) -#define QEI_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT) - -/* - * ENCTYP (RW) - * - * 00-abz; 01-pd; 10-ud; 11-reserved - */ -#define QEI_CR_ENCTYP_MASK (0x3U) -#define QEI_CR_ENCTYP_SHIFT (0U) -#define QEI_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK) -#define QEI_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * ZCNTCFG (RW) - * - * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * 0- zcnt will increment or decrement when Z input assert - */ -#define QEI_PHCFG_ZCNTCFG_MASK (0x400000UL) -#define QEI_PHCFG_ZCNTCFG_SHIFT (22U) -#define QEI_PHCFG_ZCNTCFG_SET(x) (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK) -#define QEI_PHCFG_ZCNTCFG_GET(x) (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT) - -/* - * PHCALIZ (RW) - * - * 1- phcnt will set to phidx when Z input assert - */ -#define QEI_PHCFG_PHCALIZ_MASK (0x200000UL) -#define QEI_PHCFG_PHCALIZ_SHIFT (21U) -#define QEI_PHCFG_PHCALIZ_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK) -#define QEI_PHCFG_PHCALIZ_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT) - -/* - * PHMAX (RW) - * - * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - */ -#define QEI_PHCFG_PHMAX_MASK (0x1FFFFFUL) -#define QEI_PHCFG_PHMAX_SHIFT (0U) -#define QEI_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK) -#define QEI_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define QEI_WDGCFG_WDGEN_MASK (0x80000000UL) -#define QEI_WDGCFG_WDGEN_SHIFT (31U) -#define QEI_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK) -#define QEI_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define QEI_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) -#define QEI_WDGCFG_WDGTO_SHIFT (0U) -#define QEI_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK) -#define QEI_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: PHIDX */ -/* - * PHIDX (RW) - * - * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - */ -#define QEI_PHIDX_PHIDX_MASK (0x1FFFFFUL) -#define QEI_PHIDX_PHIDX_SHIFT (0U) -#define QEI_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK) -#define QEI_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGFEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define QEI_TRGOEN_WDGFEN_MASK (0x80000000UL) -#define QEI_TRGOEN_WDGFEN_SHIFT (31U) -#define QEI_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK) -#define QEI_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- enable trigger output when homef flag set - */ -#define QEI_TRGOEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_TRGOEN_HOMEFEN_SHIFT (30U) -#define QEI_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK) -#define QEI_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- enable trigger output when poscmpf flag set - */ -#define QEI_TRGOEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_TRGOEN_POSCMPFEN_SHIFT (29U) -#define QEI_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK) -#define QEI_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- enable trigger output when zphf flag set - */ -#define QEI_TRGOEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_TRGOEN_ZPHFEN_SHIFT (28U) -#define QEI_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK) -#define QEI_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGFEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define QEI_READEN_WDGFEN_MASK (0x80000000UL) -#define QEI_READEN_WDGFEN_SHIFT (31U) -#define QEI_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK) -#define QEI_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- load counters to their read registers when homef flag set - */ -#define QEI_READEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_READEN_HOMEFEN_SHIFT (30U) -#define QEI_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK) -#define QEI_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- load counters to their read registers when poscmpf flag set - */ -#define QEI_READEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_READEN_POSCMPFEN_SHIFT (29U) -#define QEI_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK) -#define QEI_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- load counters to their read registers when zphf flag set - */ -#define QEI_READEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_READEN_ZPHFEN_SHIFT (28U) -#define QEI_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK) -#define QEI_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: ZCMP */ -/* - * ZCMP (RW) - * - * zcnt postion compare value - */ -#define QEI_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) -#define QEI_ZCMP_ZCMP_SHIFT (0U) -#define QEI_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK) -#define QEI_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT) - -/* Bitfield definition for register: PHCMP */ -/* - * ZCMPDIS (RW) - * - * 1- postion compare not include zcnt - */ -#define QEI_PHCMP_ZCMPDIS_MASK (0x80000000UL) -#define QEI_PHCMP_ZCMPDIS_SHIFT (31U) -#define QEI_PHCMP_ZCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK) -#define QEI_PHCMP_ZCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT) - -/* - * DIRCMPDIS (RW) - * - * 1- postion compare not include rotation direction - */ -#define QEI_PHCMP_DIRCMPDIS_MASK (0x40000000UL) -#define QEI_PHCMP_DIRCMPDIS_SHIFT (30U) -#define QEI_PHCMP_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK) -#define QEI_PHCMP_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT) - -/* - * DIRCMP (RW) - * - * 0- position compare need positive rotation - * 1- position compare need negative rotation - */ -#define QEI_PHCMP_DIRCMP_MASK (0x20000000UL) -#define QEI_PHCMP_DIRCMP_SHIFT (29U) -#define QEI_PHCMP_DIRCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK) -#define QEI_PHCMP_DIRCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT) - -/* - * PHCMP (RW) - * - * phcnt position compare value - */ -#define QEI_PHCMP_PHCMP_MASK (0x1FFFFFUL) -#define QEI_PHCMP_PHCMP_SHIFT (0U) -#define QEI_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK) -#define QEI_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT) - -/* Bitfield definition for register: SPDCMP */ -/* - * SPDCMP (RW) - * - * spdcnt position compare value - */ -#define QEI_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) -#define QEI_SPDCMP_SPDCMP_SHIFT (0U) -#define QEI_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK) -#define QEI_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGFEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define QEI_DMAEN_WDGFEN_MASK (0x80000000UL) -#define QEI_DMAEN_WDGFEN_SHIFT (31U) -#define QEI_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK) -#define QEI_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- generate dma request when homef flag set - */ -#define QEI_DMAEN_HOMEFEN_MASK (0x40000000UL) -#define QEI_DMAEN_HOMEFEN_SHIFT (30U) -#define QEI_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK) -#define QEI_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- generate dma request when poscmpf flag set - */ -#define QEI_DMAEN_POSCMPFEN_MASK (0x20000000UL) -#define QEI_DMAEN_POSCMPFEN_SHIFT (29U) -#define QEI_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK) -#define QEI_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- generate dma request when zphf flag set - */ -#define QEI_DMAEN_ZPHFEN_MASK (0x10000000UL) -#define QEI_DMAEN_ZPHFEN_SHIFT (28U) -#define QEI_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK) -#define QEI_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog flag - */ -#define QEI_SR_WDGF_MASK (0x80000000UL) -#define QEI_SR_WDGF_SHIFT (31U) -#define QEI_SR_WDGF_SET(x) (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK) -#define QEI_SR_WDGF_GET(x) (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT) - -/* - * HOMEF (RW) - * - * home flag - */ -#define QEI_SR_HOMEF_MASK (0x40000000UL) -#define QEI_SR_HOMEF_SHIFT (30U) -#define QEI_SR_HOMEF_SET(x) (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK) -#define QEI_SR_HOMEF_GET(x) (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT) - -/* - * POSCMPF (RW) - * - * postion compare match flag - */ -#define QEI_SR_POSCMPF_MASK (0x20000000UL) -#define QEI_SR_POSCMPF_SHIFT (29U) -#define QEI_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK) -#define QEI_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT) - -/* - * ZPHF (RW) - * - * z input flag - */ -#define QEI_SR_ZPHF_MASK (0x10000000UL) -#define QEI_SR_ZPHF_SHIFT (28U) -#define QEI_SR_ZPHF_SET(x) (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK) -#define QEI_SR_ZPHF_GET(x) (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt when wdg flag set - */ -#define QEI_IRQEN_WDGIE_MASK (0x80000000UL) -#define QEI_IRQEN_WDGIE_SHIFT (31U) -#define QEI_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK) -#define QEI_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT) - -/* - * HOMEIE (RW) - * - * 1- generate interrupt when homef flag set - */ -#define QEI_IRQEN_HOMEIE_MASK (0x40000000UL) -#define QEI_IRQEN_HOMEIE_SHIFT (30U) -#define QEI_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK) -#define QEI_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT) - -/* - * POSCMPIE (RW) - * - * 1- generate interrupt when poscmpf flag set - */ -#define QEI_IRQEN_POSCMPIE_MASK (0x20000000UL) -#define QEI_IRQEN_POSCMPIE_SHIFT (29U) -#define QEI_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK) -#define QEI_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT) - -/* - * ZPHIE (RW) - * - * 1- generate interrupt when zphf flag set - */ -#define QEI_IRQEN_ZPHIE_MASK (0x10000000UL) -#define QEI_IRQEN_ZPHIE_SHIFT (28U) -#define QEI_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK) -#define QEI_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: Z */ -/* - * ZCNT (RW) - * - * zcnt value - */ -#define QEI_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) -#define QEI_COUNT_Z_ZCNT_SHIFT (0U) -#define QEI_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK) -#define QEI_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: PH */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEI_COUNT_PH_DIR_MASK (0x40000000UL) -#define QEI_COUNT_PH_DIR_SHIFT (30U) -#define QEI_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEI_COUNT_PH_ASTAT_MASK (0x4000000UL) -#define QEI_COUNT_PH_ASTAT_SHIFT (26U) -#define QEI_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT) - -/* - * BSTAT (RO) - * - * 1- b input is high - * 0- b input is low - */ -#define QEI_COUNT_PH_BSTAT_MASK (0x2000000UL) -#define QEI_COUNT_PH_BSTAT_SHIFT (25U) -#define QEI_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT) - -/* - * PHCNT (RO) - * - * phcnt value - */ -#define QEI_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) -#define QEI_COUNT_PH_PHCNT_SHIFT (0U) -#define QEI_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: SPD */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEI_COUNT_SPD_DIR_MASK (0x80000000UL) -#define QEI_COUNT_SPD_DIR_SHIFT (31U) -#define QEI_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEI_COUNT_SPD_ASTAT_MASK (0x40000000UL) -#define QEI_COUNT_SPD_ASTAT_SHIFT (30U) -#define QEI_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT) - -/* - * BSTAT (RW) - * - * 1- b input is high - * 0- b input is low - */ -#define QEI_COUNT_SPD_BSTAT_MASK (0x20000000UL) -#define QEI_COUNT_SPD_BSTAT_SHIFT (29U) -#define QEI_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK) -#define QEI_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT) - -/* - * SPDCNT (RO) - * - * spdcnt value - */ -#define QEI_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) -#define QEI_COUNT_SPD_SPDCNT_SHIFT (0U) -#define QEI_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TMRCNT (RO) - * - * 32 bit free run timer - */ -#define QEI_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) -#define QEI_COUNT_TMR_TMRCNT_SHIFT (0U) -#define QEI_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT) - -/* Bitfield definition for register array: SPDHIS */ -/* - * SPDHIS0 (RO) - * - * copy of spdcnt, load from spdcnt after any transition from a = low, b = low - */ -#define QEI_SPDHIS_SPDHIS0_MASK (0xFFFFFFFFUL) -#define QEI_SPDHIS_SPDHIS0_SHIFT (0U) -#define QEI_SPDHIS_SPDHIS0_GET(x) (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT) - - - -/* COUNT register group index macro definition */ -#define QEI_COUNT_CURRENT (0UL) -#define QEI_COUNT_READ (1UL) -#define QEI_COUNT_SNAP0 (2UL) -#define QEI_COUNT_SNAP1 (3UL) - -/* SPDHIS register group index macro definition */ -#define QEI_SPDHIS_SPDHIS0 (0UL) -#define QEI_SPDHIS_SPDHIS1 (1UL) -#define QEI_SPDHIS_SPDHIS2 (2UL) -#define QEI_SPDHIS_SPDHIS3 (3UL) - - -#endif /* HPM_QEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_rng_regs.h deleted file mode 100644 index 1a847f5d090..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_rng_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RNG_H -#define HPM_RNG_H - -typedef struct { - __RW uint32_t CMD; /* 0x0: Command Register */ - __RW uint32_t CTRL; /* 0x4: Control Register */ - __R uint32_t STA; /* 0x8: Status Register */ - __R uint32_t ERR; /* 0xC: Error Registers */ - __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ -} RNG_Type; - - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. - * 0 Do not perform a software reset. - * 1 Software reset - */ -#define RNG_CMD_SFTRST_MASK (0x40U) -#define RNG_CMD_SFTRST_SHIFT (6U) -#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) -#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) - -/* - * CLRERR (RW) - * - * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. - * 0 Do not clear the errors and the interrupt. - * 1 Clear the errors and the interrupt. - */ -#define RNG_CMD_CLRERR_MASK (0x20U) -#define RNG_CMD_CLRERR_SHIFT (5U) -#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) -#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) - -/* - * CLRINT (RW) - * - * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. - * 0 Do not clear the interrupt. - * 1 Clear the interrupt - */ -#define RNG_CMD_CLRINT_MASK (0x10U) -#define RNG_CMD_CLRINT_SHIFT (4U) -#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) -#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) - -/* - * GENSD (RW) - * - * Generate Seed, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_GENSD_MASK (0x2U) -#define RNG_CMD_GENSD_SHIFT (1U) -#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) -#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) - -/* - * SLFCHK (RW) - * - * Self Test, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_SLFCHK_MASK (0x1U) -#define RNG_CMD_SLFCHK_SHIFT (0U) -#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) -#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * MIRQERR (RW) - * - * Mask Interrupt Request for Error - */ -#define RNG_CTRL_MIRQERR_MASK (0x40U) -#define RNG_CTRL_MIRQERR_SHIFT (6U) -#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) -#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) - -/* - * MIRQDN (RW) - * - * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: - * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). - * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - */ -#define RNG_CTRL_MIRQDN_MASK (0x20U) -#define RNG_CTRL_MIRQDN_SHIFT (5U) -#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) -#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) - -/* - * AUTRSD (RW) - * - * Auto Reseed - */ -#define RNG_CTRL_AUTRSD_MASK (0x10U) -#define RNG_CTRL_AUTRSD_SHIFT (4U) -#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) -#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) - -/* - * FUFMOD (RW) - * - * FIFO underflow response mode - * 00 Return all zeros and set the ESR[FUFE]. - * 01 Return all zeros and set the ESR[FUFE]. - * 10 Generate the bus transfer error - * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - */ -#define RNG_CTRL_FUFMOD_MASK (0x3U) -#define RNG_CTRL_FUFMOD_SHIFT (0U) -#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) -#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * SCPF (RO) - * - * Self Check Pass Fail - */ -#define RNG_STA_SCPF_MASK (0xE00000UL) -#define RNG_STA_SCPF_SHIFT (21U) -#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) - -/* - * FUNCERR (RO) - * - * Error was detected, check ESR register for details - */ -#define RNG_STA_FUNCERR_MASK (0x10000UL) -#define RNG_STA_FUNCERR_SHIFT (16U) -#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) - -/* - * FSIZE (RO) - * - * Fifo Size, it is 5 in this design. - */ -#define RNG_STA_FSIZE_MASK (0xF000U) -#define RNG_STA_FSIZE_SHIFT (12U) -#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) - -/* - * FRNNU (RO) - * - * Fifo Level, Indicates the number of random words currently in the output FIFO - */ -#define RNG_STA_FRNNU_MASK (0xF00U) -#define RNG_STA_FRNNU_SHIFT (8U) -#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) - -/* - * NSDDN (RO) - * - * New seed done. - */ -#define RNG_STA_NSDDN_MASK (0x40U) -#define RNG_STA_NSDDN_SHIFT (6U) -#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) - -/* - * FSDDN (RO) - * - * 1st Seed done - * When "1", Indicates that the RNG generated the first seed. - */ -#define RNG_STA_FSDDN_MASK (0x20U) -#define RNG_STA_FSDDN_SHIFT (5U) -#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) - -/* - * SCDN (RO) - * - * Self Check Done - * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is - * initiated by setting the CMD[ST]. - * 0 Self test not completed - * 1 Completed a self test since the last reset. - */ -#define RNG_STA_SCDN_MASK (0x10U) -#define RNG_STA_SCDN_SHIFT (4U) -#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) - -/* - * RSDREQ (RO) - * - * Reseed needed - * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or - * automatically if the CTRL[ARS] is set. - */ -#define RNG_STA_RSDREQ_MASK (0x8U) -#define RNG_STA_RSDREQ_SHIFT (3U) -#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) - -/* - * IDLE (RO) - * - * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - */ -#define RNG_STA_IDLE_MASK (0x4U) -#define RNG_STA_IDLE_SHIFT (2U) -#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) - -/* - * BUSY (RO) - * - * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - */ -#define RNG_STA_BUSY_MASK (0x2U) -#define RNG_STA_BUSY_SHIFT (1U) -#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) - -/* Bitfield definition for register: ERR */ -/* - * FUFE (RO) - * - * FIFO access error(underflow) - */ -#define RNG_ERR_FUFE_MASK (0x20U) -#define RNG_ERR_FUFE_SHIFT (5U) -#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) - -/* - * SCKERR (RO) - * - * Self-test error - * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a - * hardware reset or by writing 1 to the CMD[CE] - */ -#define RNG_ERR_SCKERR_MASK (0x8U) -#define RNG_ERR_SCKERR_SHIFT (3U) -#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) - -/* Bitfield definition for register: FO2B */ -/* - * FO2B (RO) - * - * SW read the FIFO output. - */ -#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) -#define RNG_FO2B_FO2B_SHIFT (0U) -#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) - -/* Bitfield definition for register array: R2SK */ -/* - * FO2S0 (RO) - * - * FIFO out to KMAN, will be SDP engine key. - */ -#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) -#define RNG_R2SK_FO2S0_SHIFT (0U) -#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) - - - -/* R2SK register group index macro definition */ -#define RNG_R2SK_FO2S0 (0UL) -#define RNG_R2SK_FO2S1 (1UL) -#define RNG_R2SK_FO2S2 (2UL) -#define RNG_R2SK_FO2S3 (3UL) -#define RNG_R2SK_FO2S4 (4UL) -#define RNG_R2SK_FO2S5 (5UL) -#define RNG_R2SK_FO2S6 (6UL) -#define RNG_R2SK_FO2S7 (7UL) - - -#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_rtc_regs.h deleted file mode 100644 index d2325b94590..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_rtc_regs.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTC_H -#define HPM_RTC_H - -typedef struct { - __RW uint32_t SECOND; /* 0x0: Second counter */ - __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ - __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ - __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ - __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ - __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ - __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ - __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ - __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ - __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ -} RTC_Type; - - -/* Bitfield definition for register: SECOND */ -/* - * SECOND (RW) - * - * second counter - */ -#define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) -#define RTC_SECOND_SECOND_SHIFT (0U) -#define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) -#define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) - -/* Bitfield definition for register: SUBSEC */ -/* - * SUBSEC (RO) - * - * sub second counter - */ -#define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) - -/* Bitfield definition for register: SEC_SNAP */ -/* - * SEC_SNAP (RW) - * - * second snap shot, write to take snap shot - */ -#define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) -#define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) -#define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) - -/* Bitfield definition for register: SUB_SNAP */ -/* - * SUB_SNAP (RW) - * - * sub second snap shot, write to take snap shot - */ -#define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) -#define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) -#define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) - -/* Bitfield definition for register: ALARM0 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_ALARM_SHIFT (0U) -#define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) -#define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM0_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) -#define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM1 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_ALARM_SHIFT (0U) -#define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) -#define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM1_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) -#define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM_FLAG */ -/* - * ALARM1 (RW) - * - * alarm1 happen - */ -#define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) -#define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) -#define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) -#define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) - -/* - * ALARM0 (RW) - * - * alarm0 happen - */ -#define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) -#define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) -#define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) -#define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) - -/* Bitfield definition for register: ALARM_EN */ -/* - * ENABLE1 (RW) - * - * alarm1 mask - * 0: alarm1 disabled - * 1: alarm1 enabled - */ -#define RTC_ALARM_EN_ENABLE1_MASK (0x2U) -#define RTC_ALARM_EN_ENABLE1_SHIFT (1U) -#define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) -#define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) - -/* - * ENABLE0 (RW) - * - * alarm0 mask - * 0: alarm0 disabled - * 1: alarm0 enabled - */ -#define RTC_ALARM_EN_ENABLE0_MASK (0x1U) -#define RTC_ALARM_EN_ENABLE0_SHIFT (0U) -#define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) -#define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) - - - - -#endif /* HPM_RTC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sdp_regs.h deleted file mode 100644 index a43c8135e9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sdp_regs.h +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDP_H -#define HPM_SDP_H - -typedef struct { - __RW uint32_t SDPCR; /* 0x0: SDP control register */ - __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ - __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ - __RW uint32_t STA; /* 0xC: Status Registers */ - __RW uint32_t KEYADDR; /* 0x10: Key Address */ - __RW uint32_t KEYDAT; /* 0x14: Key Data */ - __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ - __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ - __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ - __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ - __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ - __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ - __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ - __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ -} SDP_Type; - - -/* Bitfield definition for register: SDPCR */ -/* - * SFTRST (RW) - * - * soft reset. - * Write 1 then 0, to reset the SDP block. - */ -#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) -#define SDP_SDPCR_SFTRST_SHIFT (31U) -#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) -#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) - -/* - * CLKGAT (RW) - * - * Clock Gate for the SDP main logic. - * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - */ -#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) -#define SDP_SDPCR_CLKGAT_SHIFT (30U) -#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) -#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) - -/* - * CIPDIS (RO) - * - * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. - * 1, Cipher is disabled in this chip. - * 0, Cipher is enabled in this chip. - */ -#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) -#define SDP_SDPCR_CIPDIS_SHIFT (29U) -#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) - -/* - * HASDIS (RO) - * - * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. - * 1, HASH is disabled in this chip. - * 0, HASH is enabled in this chip. - */ -#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) -#define SDP_SDPCR_HASDIS_SHIFT (28U) -#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) - -/* - * CIPHEN (RW) - * - * Cipher Enablement, controlled by SW. - * 1, Cipher is Enabled. - * 0, Cipher is Disabled. - */ -#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) -#define SDP_SDPCR_CIPHEN_SHIFT (23U) -#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) -#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) - -/* - * HASHEN (RW) - * - * HASH Enablement, controlled by SW. - * 1, HASH is Enabled. - * 0, HASH is Disabled. - */ -#define SDP_SDPCR_HASHEN_MASK (0x400000UL) -#define SDP_SDPCR_HASHEN_SHIFT (22U) -#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) -#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) - -/* - * MCPEN (RW) - * - * Memory Copy Enablement, controlled by SW. - * 1, Memory copy is Enabled. - * 0, Memory copy is Disabled. - */ -#define SDP_SDPCR_MCPEN_MASK (0x200000UL) -#define SDP_SDPCR_MCPEN_SHIFT (21U) -#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) -#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) - -/* - * CONFEN (RW) - * - * Constant Fill to memory, controlled by SW. - * 1, Constant fill is Enabled. - * 0, Constant fill is Disabled. - */ -#define SDP_SDPCR_CONFEN_MASK (0x100000UL) -#define SDP_SDPCR_CONFEN_SHIFT (20U) -#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) -#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) - -/* - * DCRPDI (RW) - * - * Decryption Disable bit, Write to 1 to disable the decryption. - */ -#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) -#define SDP_SDPCR_DCRPDI_SHIFT (19U) -#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) -#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) - -/* - * TSTPKT0IRQ (RW) - * - * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - */ -#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) -#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) -#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) -#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) - -/* - * INTEN (RW) - * - * Interrupt Enablement, controlled by SW. - * 1, SDP interrupt is enabled. - * 0, SDP interrupt is disabled. - */ -#define SDP_SDPCR_INTEN_MASK (0x1U) -#define SDP_SDPCR_INTEN_SHIFT (0U) -#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) -#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) - -/* Bitfield definition for register: MODCTRL */ -/* - * AESALG (RW) - * - * AES algorithem selection. - * 0x0 = AES 128; - * 0x1 = AES 256; - * 0x8 = SM4； - * Others, reserved. - */ -#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) -#define SDP_MODCTRL_AESALG_SHIFT (28U) -#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) -#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) - -/* - * AESMOD (RW) - * - * AES mode selection. - * 0x0 = ECB; - * 0x1 = CBC; - * Others, reserved. - */ -#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) -#define SDP_MODCTRL_AESMOD_SHIFT (24U) -#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) -#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) - -/* - * AESKS (RW) - * - * AES Key Selection. - * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: - * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. - * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * .... - * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. - * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. - * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. - * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. - * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. - * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. - * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. - * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. - * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. - * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. - * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. - * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. - * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. - * Other values, reserved. - */ -#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) -#define SDP_MODCTRL_AESKS_SHIFT (18U) -#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) -#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) - -/* - * AESDIR (RW) - * - * AES direction - * 1x1, AES Decryption - * 1x0, AES Encryption. - */ -#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) -#define SDP_MODCTRL_AESDIR_SHIFT (16U) -#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) -#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) - -/* - * HASALG (RW) - * - * HASH Algorithem selection. - * 0x0 SHA1 — - * 0x1 CRC32 — - * 0x2 SHA256 — - */ -#define SDP_MODCTRL_HASALG_MASK (0xF000U) -#define SDP_MODCTRL_HASALG_SHIFT (12U) -#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) -#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) - -/* - * HASCHK (RW) - * - * HASH Check Enable Bit. - * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; - * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. - * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - */ -#define SDP_MODCTRL_HASCHK_MASK (0x400U) -#define SDP_MODCTRL_HASCHK_SHIFT (10U) -#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) -#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) - -/* - * HASOUT (RW) - * - * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. - * 0 INPUT HASH - * 1 OUTPUT HASH - */ -#define SDP_MODCTRL_HASOUT_MASK (0x200U) -#define SDP_MODCTRL_HASOUT_SHIFT (9U) -#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) -#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) - -/* - * DINSWP (RW) - * - * Decide whether the SDP byteswaps the input data (big-endian data); - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DINSWP_MASK (0x30U) -#define SDP_MODCTRL_DINSWP_SHIFT (4U) -#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) -#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) - -/* - * DOUTSWP (RW) - * - * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) -#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) -#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) -#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) - -/* - * KEYSWP (RW) - * - * Decide whether the SDP byteswaps the Key (big-endian data). - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_KEYSWP_MASK (0x3U) -#define SDP_MODCTRL_KEYSWP_SHIFT (0U) -#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) -#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) - -/* Bitfield definition for register: PKTCNT */ -/* - * CNTVAL (RO) - * - * This read-only field shows the current (instantaneous) value of the packet counter - */ -#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) -#define SDP_PKTCNT_CNTVAL_SHIFT (16U) -#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) - -/* - * CNTINCR (RW) - * - * The value written to this field is added to the spacket count. - */ -#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) -#define SDP_PKTCNT_CNTINCR_SHIFT (0U) -#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) -#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TAG (RO) - * - * packet tag. - */ -#define SDP_STA_TAG_MASK (0xFF000000UL) -#define SDP_STA_TAG_SHIFT (24U) -#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) - -/* - * IRQ (W1C) - * - * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - */ -#define SDP_STA_IRQ_MASK (0x800000UL) -#define SDP_STA_IRQ_SHIFT (23U) -#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) -#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) - -/* - * CHN1PKT0 (W1C) - * - * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - */ -#define SDP_STA_CHN1PKT0_MASK (0x100000UL) -#define SDP_STA_CHN1PKT0_SHIFT (20U) -#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) -#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) - -/* - * AESBSY (RO) - * - * AES Busy - */ -#define SDP_STA_AESBSY_MASK (0x80000UL) -#define SDP_STA_AESBSY_SHIFT (19U) -#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) - -/* - * HASBSY (RO) - * - * Hashing Busy - */ -#define SDP_STA_HASBSY_MASK (0x40000UL) -#define SDP_STA_HASBSY_SHIFT (18U) -#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) - -/* - * PKTCNT0 (W1C) - * - * Packet Counter registers reachs to ZERO now. - */ -#define SDP_STA_PKTCNT0_MASK (0x20000UL) -#define SDP_STA_PKTCNT0_SHIFT (17U) -#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) -#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) - -/* - * PKTDON (W1C) - * - * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - */ -#define SDP_STA_PKTDON_MASK (0x10000UL) -#define SDP_STA_PKTDON_SHIFT (16U) -#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) -#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) - -/* - * ERRSET (W1C) - * - * Working mode setup error. - */ -#define SDP_STA_ERRSET_MASK (0x20U) -#define SDP_STA_ERRSET_SHIFT (5U) -#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) -#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) - -/* - * ERRPKT (W1C) - * - * Packet head access error, or status update error. - */ -#define SDP_STA_ERRPKT_MASK (0x10U) -#define SDP_STA_ERRPKT_SHIFT (4U) -#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) -#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) - -/* - * ERRSRC (W1C) - * - * Source Buffer Access Error - */ -#define SDP_STA_ERRSRC_MASK (0x8U) -#define SDP_STA_ERRSRC_SHIFT (3U) -#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) -#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) - -/* - * ERRDST (W1C) - * - * Destination Buffer Error - */ -#define SDP_STA_ERRDST_MASK (0x4U) -#define SDP_STA_ERRDST_SHIFT (2U) -#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) -#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) - -/* - * ERRHAS (W1C) - * - * Hashing Check Error - */ -#define SDP_STA_ERRHAS_MASK (0x2U) -#define SDP_STA_ERRHAS_SHIFT (1U) -#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) -#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) - -/* - * ERRCHAIN (W1C) - * - * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - */ -#define SDP_STA_ERRCHAIN_MASK (0x1U) -#define SDP_STA_ERRCHAIN_SHIFT (0U) -#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) -#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) - -/* Bitfield definition for register: KEYADDR */ -/* - * INDEX (RW) - * - * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. - * Key index pointer. The valid indices are 0-[number_keys]. - * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - */ -#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) -#define SDP_KEYADDR_INDEX_SHIFT (16U) -#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) -#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) - -/* - * SUBWRD (RW) - * - * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field - * increments; To write a key, the software must first write the desired key index/subword to this register. - */ -#define SDP_KEYADDR_SUBWRD_MASK (0x3U) -#define SDP_KEYADDR_SUBWRD_SHIFT (0U) -#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) -#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) - -/* Bitfield definition for register: KEYDAT */ -/* - * KEYDAT (RW) - * - * This register provides the write access to the key/key subword specified by the key index register. - * Writing this location updates the selected subword for the key located at the index - * specified by the key index register. The write also triggers the SUBWORD field of the - * KEY register to increment to the next higher word in the key - */ -#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) -#define SDP_KEYDAT_KEYDAT_SHIFT (0U) -#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) -#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) - -/* Bitfield definition for register array: CIPHIV */ -/* - * CIPHIV (RW) - * - * cipher initialization vector. - */ -#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) -#define SDP_CIPHIV_CIPHIV_SHIFT (0U) -#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) -#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) - -/* Bitfield definition for register array: HASWRD */ -/* - * HASWRD (RW) - * - * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. - * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - */ -#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) -#define SDP_HASWRD_HASWRD_SHIFT (0U) -#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) -#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) - -/* Bitfield definition for register: CMDPTR */ -/* - * CMDPTR (RW) - * - * current command addresses the register points to the multiword - * descriptor that is to be executed (or is currently being executed) - */ -#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) -#define SDP_CMDPTR_CMDPTR_SHIFT (0U) -#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) -#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) - -/* Bitfield definition for register: NPKTPTR */ -/* - * NPKTPTR (RW) - * - * Next Packet Address Pointer - */ -#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) -#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) -#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) -#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) - -/* Bitfield definition for register: PKTCTL */ -/* - * PKTTAG (RW) - * - * packet tag - */ -#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) -#define SDP_PKTCTL_PKTTAG_SHIFT (24U) -#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) -#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) - -/* - * CIPHIV (RW) - * - * Load Initial Vector for the AES in this packet. - */ -#define SDP_PKTCTL_CIPHIV_MASK (0x40U) -#define SDP_PKTCTL_CIPHIV_SHIFT (6U) -#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) -#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) - -/* - * HASFNL (RW) - * - * Hash Termination packet - */ -#define SDP_PKTCTL_HASFNL_MASK (0x20U) -#define SDP_PKTCTL_HASFNL_SHIFT (5U) -#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) -#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) - -/* - * HASINI (RW) - * - * Hash Initialization packat - */ -#define SDP_PKTCTL_HASINI_MASK (0x10U) -#define SDP_PKTCTL_HASINI_SHIFT (4U) -#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) -#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) - -/* - * CHAIN (RW) - * - * whether the next command pointer register must be loaded into the channel's current descriptor - * pointer. - */ -#define SDP_PKTCTL_CHAIN_MASK (0x8U) -#define SDP_PKTCTL_CHAIN_SHIFT (3U) -#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) -#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) - -/* - * DCRSEMA (RW) - * - * whether the channel's semaphore must be decremented at the end of the current operation. - * When the semaphore reaches a value of zero, no more operations are issued from the channel. - */ -#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) -#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) -#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) -#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) - -/* - * PKTINT (RW) - * - * Reflects whether the channel must issue an interrupt upon the completion of the packet - */ -#define SDP_PKTCTL_PKTINT_MASK (0x2U) -#define SDP_PKTCTL_PKTINT_SHIFT (1U) -#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) -#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) - -/* Bitfield definition for register: PKTSRC */ -/* - * PKTSRC (RW) - * - * Packet Memory Source Address - */ -#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) -#define SDP_PKTSRC_PKTSRC_SHIFT (0U) -#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) -#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) - -/* Bitfield definition for register: PKTDST */ -/* - * PKTDST (RW) - * - * Packet Memory Destination Address - */ -#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) -#define SDP_PKTDST_PKTDST_SHIFT (0U) -#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) -#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) - -/* Bitfield definition for register: PKTBUF */ -/* - * PKTBUF (RW) - * - */ -#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) -#define SDP_PKTBUF_PKTBUF_SHIFT (0U) -#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) -#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) - - - -/* CIPHIV register group index macro definition */ -#define SDP_CIPHIV_CIPHIV0 (0UL) -#define SDP_CIPHIV_CIPHIV1 (1UL) -#define SDP_CIPHIV_CIPHIV2 (2UL) -#define SDP_CIPHIV_CIPHIV3 (3UL) - -/* HASWRD register group index macro definition */ -#define SDP_HASWRD_HASWRD0 (0UL) -#define SDP_HASWRD_HASWRD1 (1UL) -#define SDP_HASWRD_HASWRD2 (2UL) -#define SDP_HASWRD_HASWRD3 (3UL) -#define SDP_HASWRD_HASWRD4 (4UL) -#define SDP_HASWRD_HASWRD5 (5UL) -#define SDP_HASWRD_HASWRD6 (6UL) -#define SDP_HASWRD_HASWRD7 (7UL) - - -#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sdxc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sdxc_regs.h deleted file mode 100644 index 11984309b22..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sdxc_regs.h +++ /dev/null @@ -1,4315 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDXC_H -#define HPM_SDXC_H - -typedef struct { - __RW uint32_t SDMASA; /* 0x0: */ - __RW uint32_t BLK_ATTR; /* 0x4: */ - __RW uint32_t CMD_ARG; /* 0x8: */ - __RW uint32_t CMD_XFER; /* 0xC: */ - __R uint32_t RESP[4]; /* 0x10 - 0x1C: */ - __RW uint32_t BUF_DATA; /* 0x20: */ - __R uint32_t PSTATE; /* 0x24: */ - __RW uint32_t PROT_CTRL; /* 0x28: */ - __RW uint32_t SYS_CTRL; /* 0x2C: */ - __RW uint32_t INT_STAT; /* 0x30: */ - __RW uint32_t INT_STAT_EN; /* 0x34: */ - __RW uint32_t INT_SIGNAL_EN; /* 0x38: */ - __RW uint32_t AC_HOST_CTRL; /* 0x3C: */ - __R uint32_t CAPABILITIES1; /* 0x40: */ - __R uint32_t CAPABILITIES2; /* 0x44: */ - __R uint32_t CURR_CAPABILITIES1; /* 0x48: */ - __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */ - __W uint32_t FORCE_EVENT; /* 0x50: */ - __R uint32_t ADMA_ERR_STAT; /* 0x54: */ - __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */ - __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */ - __R uint16_t PRESET[11]; /* 0x60 - 0x74: */ - __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */ - __RW uint32_t ADMA_ID_ADDR; /* 0x78: */ - __R uint8_t RESERVED2[106]; /* 0x7C - 0xE5: Reserved */ - __R uint16_t P_EMBEDDED_CNTRL; /* 0xE6: */ - __R uint16_t P_VENDOR_SPECIFIC_AREA; /* 0xE8: */ - __R uint16_t P_VENDOR2_SPECIFIC_AREA; /* 0xEA: */ - __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */ - __R uint16_t SLOT_INTR_STATUS; /* 0xFC: */ - __R uint8_t RESERVED4[130]; /* 0xFE - 0x17F: Reserved */ - __R uint32_t CQVER; /* 0x180: */ - __R uint32_t CQCAP; /* 0x184: */ - __RW uint32_t CQCFG; /* 0x188: */ - __RW uint32_t CQCTL; /* 0x18C: */ - __RW uint32_t CQIS; /* 0x190: */ - __RW uint32_t CQISE; /* 0x194: */ - __RW uint32_t CQISGE; /* 0x198: */ - __RW uint32_t CQIC; /* 0x19C: */ - __RW uint32_t CQTDLBA; /* 0x1A0: */ - __R uint8_t RESERVED5[4]; /* 0x1A4 - 0x1A7: Reserved */ - __RW uint32_t CQTDBR; /* 0x1A8: */ - __RW uint32_t CQTCN; /* 0x1AC: */ - __RW uint32_t CQDQS; /* 0x1B0: */ - __RW uint32_t CQDPT; /* 0x1B4: */ - __RW uint32_t CQTCLR; /* 0x1B8: */ - __R uint8_t RESERVED6[4]; /* 0x1BC - 0x1BF: Reserved */ - __RW uint32_t CQSSC1; /* 0x1C0: */ - __RW uint32_t CQSSC2; /* 0x1C4: */ - __R uint32_t CQCRDCT; /* 0x1C8: */ - __R uint8_t RESERVED7[4]; /* 0x1CC - 0x1CF: Reserved */ - __RW uint32_t CQRMEM; /* 0x1D0: */ - __R uint32_t CQTERRI; /* 0x1D4: */ - __R uint32_t CQCRI; /* 0x1D8: */ - __R uint32_t CQCRA; /* 0x1DC: */ - __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */ - __R uint32_t MSHC_VER_ID; /* 0x500: */ - __R uint32_t MSHC_VER_TYPE; /* 0x504: */ - __R uint8_t RESERVED9[36]; /* 0x508 - 0x52B: Reserved */ - __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */ - __R uint8_t RESERVED10[16]; /* 0x530 - 0x53F: Reserved */ - __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */ - __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */ -} SDXC_Type; - - -/* Bitfield definition for register: SDMASA */ -/* - * BLOCKCNT_SDMASA (RW) - * - * 32-bit Block Count (SDMA System Address) - * - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. - * When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. - * It can be accessed only if no transaction is executing. Reading this register during data transfers may - * return an invalid value. - * - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. - * The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. - * This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. - * Following are the values for BLOCKCNT_SDMASA: - * - 0xFFFF_FFFF: 4G - 1 Block - * - - * - 0x0000_0002: 2 Blocks - * - 0x0000_0001: 1 Block - * - 0x0000_0000: Stop Count - * Note: - * - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. - * The system address must be programmed in the ADMA System Address register. - * - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. - * Auto CMD23 cannot be used with SDMA. - * - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - */ -#define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) - -/* Bitfield definition for register: BLK_ATTR */ -/* - * BLOCK_CNT (RW) - * - * 16-bit Block Count - * - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. - * - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. - * Following are the values for BLOCK_CNT: - * - 0x0: Stop Count - * - 0x1: 1 Block - * - 0x2: 2 Blocks - * - . - * - 0xFFFF: 65535 Blocks - * Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - */ -#define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL) -#define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U) -#define SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) -#define SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) - -/* - * SDMA_BUF_BDARY (RW) - * - * SDMA Buffer Boundary - * These bits specify the size of contiguous buffer in system memory. - * The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. - * Values: - * - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary - * - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary - * - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary - * - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary - * - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary - * - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary - * - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary - * - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - */ -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) - -/* - * XFER_BLOCK_SIZE (RW) - * - * Transfer Block Size - * These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. - * Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: - * - 0x1: 1 byte - * - 0x2: 2 bytes - * - 0x3: 3 bytes - * - . - * - 0x1FF: 511 byte - * - 0x200: 512 byt es - * - . - * - 0x800: 2048 bytes - * Note: This register must be programmed with a non-zero value for data transfer. - */ -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) - -/* Bitfield definition for register: CMD_ARG */ -/* - * ARGUMNET (RW) - * - * Command Argument - * These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - */ -#define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL) -#define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U) -#define SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK) -#define SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT) - -/* Bitfield definition for register: CMD_XFER */ -/* - * CMD_INDEX (RW) - * - * Command Index - * These bits are set to the command number that is specified in bits 45-40 of the Command Format. - */ -#define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL) -#define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U) -#define SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK) -#define SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT) - -/* - * CMD_TYPE (RW) - * - * Command Type - * These bits indicate the command type. - * Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. - * Values: - * 0x3 (ABORT_CMD): Abort - * 0x2 (RESUME_CMD): Resume - * 0x1 (SUSPEND_CMD): Suspend - * 0x0 (NORMAL_CMD): Normal - */ -#define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL) -#define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U) -#define SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK) -#define SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT) - -/* - * DATA_PRESENT_SEL (RW) - * - * Data Present Select - * This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: - * Command using the CMD line - * Command with no data transfer but using busy signal on the DAT[0] line - * Resume Command - * Values: - * 0x0 (NO_DATA): No Data Present - * 0x1 (DATA): Data Present - */ -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) - -/* - * CMD_IDX_CHK_ENABLE (RW) - * - * Command Index Check Enable - * This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. - * If the value is not the same, it is reported as a Command Index error. - * Note: - * Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. - * For the tuning command, this bit must always be set to enable the index check. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) - -/* - * CMD_CRC_CHK_ENABLE (RW) - * - * Command CRC Check Enable - * This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. - * Note: - * CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. - * For the tuning command, this bit must always be set to 1 to enable the CRC check. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) - -/* - * SUB_CMD_FLAG (RW) - * - * Sub Command Flag - * This bit distinguishes between a main command and a sub command. - * Values: - * 0x0 (MAIN): Main Command - * 0x1 (SUB): Sub Command - */ -#define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) - -/* - * RESP_TYPE_SELECT (RW) - * - * Response Type Select - * This bit indicates the type of response expected from the card. - * Values: - * 0x0 (NO_RESP): No Response - * 0x1 (RESP_LEN_136): Response Length 136 - * 0x2 (RESP_LEN_48): Response Length 48 - * 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - */ -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) - -/* - * RESP_INT_DISABLE (RW) - * - * Response Interrupt Disable - * The Host Controller supports response check function to avoid overhead of response error check by the Host driver. - * Response types of only R1 and R5 can be checked by the Controller. - * If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. - * If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. - * The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. - * Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. - * Values: - * - 0x0 (ENABLED): Response Interrupt is enabled - * - 0x1 (DISABLED): Response Interrupt is disabled - */ -#define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) - -/* - * RESP_ERR_CHK_ENABLE (RW) - * - * Response Error Check Enable - * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. - * If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. - * Note: - * - Response error check must not be enabled for any response type other than R1 and R5. - * - Response check must not be enabled for the tuning command. - * Values: - * - 0x0 (DISABLED): Response Error Check is disabled - * - 0x1 (ENABLED): Response Error Check is enabled - */ -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) - -/* - * RESP_TYPE (RW) - * - * Response Type R1/R5 - * This bit selects either R1 or R5 as a response type when the Response Error Check is selected. - * Error statuses checked in R1: - * OUT_OF_RANGE - * ADDRESS_ERROR - * BLOCK_LEN_ERROR - * WP_VIOLATION - * CARD_IS_LOCKED - * COM_CRC_ERROR - * CARD_ECC_FAILED - * CC_ERROR - * ERROR - * Response Flags checked in R5: - * COM_CRC_ERROR - * ERROR - * FUNCTION_NUMBER - * OUT_OF_RANGE - * Values: - * 0x0 (RESP_R1): R1 (Memory) - * 0x1 (RESP_R5): R5 (SDIO) - */ -#define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U) -#define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U) -#define SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK) -#define SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT) - -/* - * MULTI_BLK_SEL (RW) - * - * Multi/Single Block Select - * This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. - * Values: - * 0x0 (SINGLE): Single Block - * 0x1 (MULTI): Multiple Block - */ -#define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) - -/* - * DATA_XFER_DIR (RW) - * - * Data Transfer Direction Select - * This bit defines the direction of DAT line data transfers. - * This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. - * Values: - * 0x1 (READ): Read (Card to Host) - * 0x0 (WRITE): Write (Host to Card) - */ -#define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U) -#define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U) -#define SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) -#define SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) - -/* - * AUTO_CMD_ENABLE (RW) - * - * Auto Command Enable - * This field determines use of Auto Command functions. - * Note: In SDIO, this field must be set as 00b (Auto Command Disabled). - * Values: - * 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled - * 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable - * 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable - * 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - */ -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) - -/* - * BLOCK_COUNT_ENABLE (RW) - * - * Block Count Enable - * This bit is used to enable the Block Count register, which is relevant for multiple block transfers. - * If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. - * The Host Driver must set this bit to 0 when ADMA is used. - * Values: - * 0x1 (ENABLED): Enable - * 0x0 (DISABLED): Disable - */ -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) - -/* - * DMA_ENABLE (RW) - * - * DMA Enable - * This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. - * You can select one of the DMA modes by using DMA Select in the Host Control 1 register. - * Values: - * 0x1 (ENABLED): DMA Data transfer - * 0x0 (DISABLED): No data transfer or Non-DMA data transfer - */ -#define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U) -#define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U) -#define SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK) -#define SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT) - -/* Bitfield definition for register array: RESP */ -/* - * RESP01 (RO) - * - * Command Response - * These bits reflect 39-8 bits of SD/eMMC Response Field. - * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - */ -#define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL) -#define SDXC_RESP_RESP01_SHIFT (0U) -#define SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT) - -/* Bitfield definition for register: BUF_DATA */ -/* - * BUF_DATA (RW) - * - * Buffer Data - * These bits enable access to the Host Controller packet buffer. - */ -#define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL) -#define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U) -#define SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK) -#define SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT) - -/* Bitfield definition for register: PSTATE */ -/* - * SUB_CMD_STAT (RO) - * - * Sub Command Status - * This bit is used to distinguish between a main command and a sub command status. - * Values: - * 0x0 (FALSE): Main Command Status - * 0x1 (TRUE): Sub Command Status - */ -#define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL) -#define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U) -#define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT) - -/* - * CMD_ISSUE_ERR (RO) - * - * Command Not Issued by Error - * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. - * Values: - * 0x0 (FALSE): No error for issuing a command - * 0x1 (TRUE): Command cannot be issued - */ -#define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL) -#define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U) -#define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT) - -/* - * CMD_LINE_LVL (RO) - * - * Command-Line Signal Level - * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - */ -#define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL) -#define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U) -#define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT) - -/* - * DAT_3_0 (RO) - * - * DAT[3:0] Line Signal Level - * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - */ -#define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL) -#define SDXC_PSTATE_DAT_3_0_SHIFT (20U) -#define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT) - -/* - * WR_PROTECT_SW_LVL (RO) - * - * Write Protect Switch Pin Level - * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. - * Values: - * 0x0 (FALSE): Write protected - * 0x1 (TRUE): Write enabled - */ -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL) -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U) -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT) - -/* - * CARD_DETECT_PIN_LEVEL (RO) - * - * Card Detect Pin Level - * This bit reflects the inverse synchronized value of the card_detect_n signal. - * Values: - * 0x0 (FALSE): No card present - * 0x1 (TRUE): Card Present - */ -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL) -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U) -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT) - -/* - * CARD_STABLE (RO) - * - * Card Stable - * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. - * Values: - * 0x0 (FALSE): Reset or Debouncing - * 0x1 (TRUE): No Card or Inserted - */ -#define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL) -#define SDXC_PSTATE_CARD_STABLE_SHIFT (17U) -#define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT) - -/* - * CARD_INSERTED (RO) - * - * Card Inserted - * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. - * Values: - * 0x0 (FALSE): Reset, Debouncing, or No card - * 0x1 (TRUE): Card Inserted - */ -#define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL) -#define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U) -#define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT) - -/* - * BUF_RD_ENABLE (RO) - * - * Buffer Read Enable - * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. - * Values: - * 0x0 (DISABLED): Read disable - * 0x1 (ENABLED): Read enable - */ -#define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U) -#define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U) -#define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT) - -/* - * BUF_WR_ENABLE (RO) - * - * Buffer Write Enable - * This bit is used for non-DMA transfers. This bit is set if space is available for writing data. - * Values: - * 0x0 (DISABLED): Write disable - * 0x1 (ENABLED): Write enable - */ -#define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U) -#define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U) -#define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT) - -/* - * RD_XFER_ACTIVE (RO) - * - * Read Transfer Active - * This bit indicates whether a read transfer is active for SD/eMMC mode. - * Values: - * 0x0 (INACTIVE): No valid data - * 0x1 (ACTIVE): Transferring data - */ -#define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U) -#define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U) -#define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT) - -/* - * WR_XFER_ACTIVE (RO) - * - * Write Transfer Active - * This status indicates whether a write transfer is active for SD/eMMC mode. - * Values: - * 0x0 (INACTIVE): No valid data - * 0x1 (ACTIVE): Transferring data - */ -#define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U) -#define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U) -#define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT) - -/* - * DAT_7_4 (RO) - * - * DAT[7:4] Line Signal Level - * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - */ -#define SDXC_PSTATE_DAT_7_4_MASK (0xF0U) -#define SDXC_PSTATE_DAT_7_4_SHIFT (4U) -#define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT) - -/* - * RE_TUNE_REQ (RO) - * - * Re-Tuning Request - * SDXC does not generate retuning request. The software must maintain the Retuning timer. - */ -#define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U) -#define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U) -#define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT) - -/* - * DAT_LINE_ACTIVE (RO) - * - * DAT Line Active ( - * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. - * In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. - * In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. - * For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. - * Values: - * 0x0 (INACTIVE): DAT Line Inactive - * 0x1 (ACTIVE): DAT Line Active - */ -#define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U) -#define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U) -#define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT) - -/* - * DAT_INHIBIT (RO) - * - * Command Inhibit (DAT) - * This bit is generated if either DAT line active or Read transfer active is set to 1. - * If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. - * Values: - * 0x0 (READY): Can issue command which used DAT line - * 0x1 (NOT_READY): Cannot issue command which used DAT line - */ -#define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U) -#define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U) -#define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT) - -/* - * CMD_INHIBIT (RO) - * - * Command Inhibit (CMD) - * This bit indicates the following : - * If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. - * This bit is set when the command register is written. This bit is cleared when the command response is received. - * This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. - * Values: - * 0x0 (READY): Host Controller is ready to issue a command - * 0x1 (NOT_READY): Host Controller is not ready to issue a command - */ -#define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U) -#define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U) -#define SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT) - -/* Bitfield definition for register: PROT_CTRL */ -/* - * CARD_REMOVAL (RW) - * - * Wakeup Event Enable on SD Card Removal - * This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. - * For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL) -#define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U) -#define SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) -#define SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) - -/* - * CARD_INSERT (RW) - * - * Wakeup Event Enable on SD Card Insertion - * This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. - * FN_WUS (Wake Up Support) in CIS does not affect this bit. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL) -#define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U) -#define SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK) -#define SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT) - -/* - * CARD_INT (RW) - * - * Wakeup Event Enable on Card Interrupt - * This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. - * This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL) -#define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U) -#define SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK) -#define SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT) - -/* - * INT_AT_BGAP (RW) - * - * Interrupt At Block Gap - * This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. - * Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. - * Values: - * 0x0 (DISABLE): Disabled - * 0x1 (ENABLE): Enabled - */ -#define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL) -#define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U) -#define SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) -#define SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) - -/* - * RD_WAIT_CTRL (RW) - * - * Read Wait Control - * This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. - * Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. - * Values: - * 0x0 (DISABLE): Disable Read Wait Control - * 0x1 (ENABLE): Enable Read Wait Control - */ -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) - -/* - * CONTINUE_REQ (RW) - * - * Continue Request - * This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. - * The Host Controller automatically clears this bit when the transaction restarts. - * If stop at block gap request is set to 1, any write to this bit is ignored. - * Values: - * 0x0 (NO_AFFECT): No Affect - * 0x1 (RESTART): Restart - */ -#define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL) -#define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U) -#define SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) -#define SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) - -/* - * STOP_BG_REQ (RW) - * - * Stop At Block Gap Request - * This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. - * Values: - * 0x0 (XFER): Transfer - * 0x1 (STOP): Stop - */ -#define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL) -#define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U) -#define SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) -#define SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) - -/* - * SD_BUS_VOL_VDD1 (RW) - * - * SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD - * These bits enable the Host Driver to select the voltage level for an SD/eMMC card. - * Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. - * If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. - * The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. - * SD Bus Voltage Select options: - * 0x7 : 3.3V(Typical) - * 0x6 : 3.0V(Typical) - * 0x5 : 1.8V(Typical) for Embedded - * 0x4 : 0x0 - Reserved - * eMMC Bus Voltage Select options: - * 0x7 : 3.3V(Typical) - * 0x6 : 1.8V(Typical) - * 0x5 : 1.2V(Typical) - * 0x4 : 0x0 - Reserved - * Values: - * 0x7 (V_3_3): 3.3V (Typ.) - * 0x6 (V_3_0): 3.0V (Typ.) - * 0x5 (V_1_8): 1.8V (Typ.) for Embedded - * 0x4 (RSVD4): Reserved - * 0x3 (RSVD3): Reserved - * 0x2 (RSVD2): Reserved - * 0x1 (RSVD1): Reserved - * 0x0 (RSVD0): Reserved - */ -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) - -/* - * SD_BUS_PWR_VDD1 (RW) - * - * SD Bus Power for VDD1 - * This bit enables VDD1 power of the card. - * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. - * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. - * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. - * Values: - * 0x0 (OFF): Power off - * 0x1 (ON): Power on - */ -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) - -/* - * EXT_DAT_XFER (RW) - * - * Extended Data Transfer Width - * This bit controls 8-bit bus width mode of embedded device. - * Values: - * 0x1 (EIGHT_BIT): 8-bit Bus Width - * 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - */ -#define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) - -/* - * DMA_SEL (RW) - * - * DMA Select - * This field is used to select the DMA type. - * When Host Version 4 Enable is 1 in Host Control 2 register: - * 0x0 : SDMA is selected - * 0x1 : Reserved - * 0x2 : ADMA2 is selected - * 0x3 : ADMA2 or ADMA3 is selected - * When Host Version 4 Enable is 0 in Host Control 2 register: - * 0x0 : SDMA is selected - * 0x1 : Reserved - * 0x2 : 32-bit Address ADMA2 is selected - * 0x3 : 64-bit Address ADMA2 is selected - * Values: - * 0x0 (SDMA): SDMA is selected - * 0x1 (RSVD_BIT): Reserved - * 0x2 (ADMA2): ADMA2 is selected - * 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - */ -#define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U) -#define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U) -#define SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK) -#define SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT) - -/* - * HIGH_SPEED_EN (RW) - * - * High Speed Enable - * this bit is used to determine the selection of preset value for High Speed mode. - * Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. - * Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. - * Values: - * 0x1 (HIGH_SPEED): High Speed mode - * 0x0 (NORMAL_SPEED): Normal Speed mode - */ -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) - -/* - * DAT_XFER_WIDTH (RW) - * - * Data Transfer Width - * For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. - * The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. - * Values: - * 0x1 (FOUR_BIT): 4-bit mode - * 0x0 (ONE_BIT): 1-bit mode - */ -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) - -/* Bitfield definition for register: SYS_CTRL */ -/* - * SW_RST_DAT (RW) - * - * Software Reset For DAT line - * This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. - * The following registers and bits are cleared by this bit: - * Buffer Data Port register - * -Buffer is cleared and initialized. - * Present state register - * -Buffer Read Enable - * -Buffer Write Enable - * -Read Transfer Active - * -Write Transfer Active - * -DAT Line Active - * -Command Inhibit (DAT) - * Block Gap Control register - * -Continue Request - * -Stop At Block Gap Request - * Normal Interrupt status register - * -Buffer Read Ready - * -Buffer Write Ready - * -DMA Interrupt - * -Block Gap Event - * -Transfer Complete - * In UHS-II mode, this bit shall be set to 0 - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL) -#define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U) -#define SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) -#define SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) - -/* - * SW_RST_CMD (RW) - * - * Software Reset For CMD line - * This bit resets only a part of the command circuit to be able to issue a command. - * It bit is also used to initialize a UHS-II command circuit. - * This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. - * Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. - * The following registers and bits are cleared by this bit: - * Present State register : Command Inhibit (CMD) bit - * Normal Interrupt Status register : Command Complete bit - * Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL) -#define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U) -#define SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) -#define SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) - -/* - * SW_RST_ALL (RW) - * - * Software Reset For All - * This reset affects the entire Host Controller except for the card detection circuit. - * During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. - * All registers are reset except the capabilities register. - * If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL) -#define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U) -#define SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) -#define SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) - -/* - * TOUT_CNT (RW) - * - * Data Timeout Counter Value. - * This value determines the interval by which DAT line timeouts are detected. - * The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. - * When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). - * The values for these bits are: - * 0xF : Reserved - * 0xE : TMCLK x 2^27 - * ......... - * 0x1 : TMCLK x 2^14 - * 0x0 : TMCLK x 2^13 - * Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - */ -#define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL) -#define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U) -#define SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK) -#define SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT) - -/* - * FREQ_SEL (RW) - * - * SDCLK/RCLK Frequency Select - * These bits are used to select the frequency of the SDCLK signal. - * These bits depend on setting of Preset Value Enable in the Host Control 2 register. - * If Preset Value Enable = 0, these bits are set by the Host Driver. - * If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. - * The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. - * 10-bit Divided Clock Mode: - * 0x3FF : 1/2046 Divided clock - * .......... - * N : 1/2N Divided Clock - * .......... - * 0x002 : 1/4 Divided Clock - * 0x001 : 1/2 Divided Clock - * 0x000 : Base clock (10MHz - 255 MHz) - * Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: - * 0x3FF : Base clock * M /1024 - * .......... - * N-1 : Base clock * M /N - * .......... - * 0x002 : Base clock * M /3 - * 0x001 : Base clock * M /2 - * 0x000 : Base clock * M - */ -#define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U) -#define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U) -#define SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK) -#define SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT) - -/* - * UPPER_FREQ_SEL (RW) - * - * These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. - * The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - */ -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) - -/* - * CLK_GEN_SELECT (RW) - * - * Clock Generator Select - * This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. - * If Preset Value Enable = 0, this bit is set by the Host Driver. - * If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. - * The value is reflected on the card_clk_gen_sel signal. - * Values: - * 0x0 (FALSE): Divided Clock Mode - * 0x1 (TRUE): Programmable Clock Mode - */ -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) - -/* - * PLL_ENABLE (RW) - * - * PLL Enable - * This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). - * When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. - * Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . - * Values: - * 0x0 (FALSE): PLL is in low power mode - * 0x1 (TRUE): PLL is enabled - */ -#define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U) -#define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U) -#define SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) -#define SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) - -/* - * SD_CLK_EN (RW) - * - * SD/eMMC Clock Enable - * This bit stops the SDCLK or RCLK when set to 0. - * The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. - * The value is reflected on the clk2card_on pin. - * Values: - * 0x0 (FALSE): Disable providing SDCLK/RCLK - * 0x1 (TRUE): Enable providing SDCLK/RCLK - */ -#define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U) -#define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U) -#define SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) -#define SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) - -/* - * INTERNAL_CLK_STABLE (RW) - * - * Internal Clock Stable - * This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. - * This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, - * and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. - * Values: - * 0x0 (FALSE): Not Ready - * 0x1 (TRUE): Ready - */ -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) - -/* - * INTERNAL_CLK_EN (RW) - * - * Internal Clock Enable - * This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. - * The Host Controller must stop its internal clock to enter a very low power state. - * However, registers can still be read and written to. The value is reflected on the intclk_en signal. - * Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . - * Values: - * 0x0 (FALSE): Stop - * 0x1 (TRUE): Oscillate - */ -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) - -/* Bitfield definition for register: INT_STAT */ -/* - * BOOT_ACK_ERR (R/W1C) - * - * Boot Acknowledgment Error - * This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. - * In SD/UHS-II mode, this bit is irrelevant. - */ -#define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL) -#define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U) -#define SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) -#define SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) - -/* - * RESP_ERR (R/W1C) - * - * Response Error - * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. - * If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL) -#define SDXC_INT_STAT_RESP_ERR_SHIFT (27U) -#define SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK) -#define SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT) - -/* - * TUNING_ERR (R/W1C) - * - * Tuning Error - * This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure - * (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). - * By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. - * To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. - * The Tuning Error is higher priority than the other error interrupts generated during data transfer. - * By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. - * This is applicable in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL) -#define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U) -#define SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK) -#define SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT) - -/* - * ADMA_ERR (R/W1C) - * - * ADMA Error - * This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: - * Error response received from System bus (Master I/F) - * ADMA3,ADMA2 Descriptors invalid - * CQE Task or Transfer descriptors invalid - * When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. - * In eMMC CQE mode: - * The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. - * ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. - * The Host Driver may find that Valid bit is not set at the error descriptor. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL) -#define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U) -#define SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK) -#define SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT) - -/* - * AUTO_CMD_ERR (R/W1C) - * - * Auto CMD Error - * This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. - * This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. - * D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL) -#define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U) -#define SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) -#define SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) - -/* - * CUR_LMT_ERR (R/W1C) - * - * Current Limit Error - * By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. - * If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. - * A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. - * A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. - * The Host Controller may require some sampling time to detect the current limit. - * SDXC Host Controller does not support this function, this bit is always set to 0. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Power Fail - */ -#define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL) -#define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U) -#define SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) -#define SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) - -/* - * DATA_END_BIT_ERR (R/W1C) - * - * Data End Bit Error - * This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) - -/* - * DATA_CRC_ERR (R/W1C) - * - * Data CRC Error - * This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, - * when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL) -#define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U) -#define SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) -#define SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) - -/* - * DATA_TOUT_ERR (R/W1C) - * - * Data Timeout Error - * This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: - * Busy timeout for R1b, R5b type - * Busy timeout after Write CRC status - * Write CRC Status timeout - * Read Data timeout - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Time out - */ -#define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL) -#define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U) -#define SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) -#define SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) - -/* - * CMD_IDX_ERR (R/W1C) - * - * Command Index Error - * This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL) -#define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U) -#define SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) -#define SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) - -/* - * CMD_END_BIT_ERR (R/W1C) - * - * Command End Bit Error - * This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): End Bit error generated - */ -#define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) - -/* - * CMD_CRC_ERR (R/W1C) - * - * Command CRC Error - * Command CRC Error is generated in SD/eMMC mode for following two cases. - * If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. - * The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. - * If the Host Controller drives the CMD line to 1 level, - * but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. - * The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): CRC error generated - */ -#define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL) -#define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U) -#define SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) -#define SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) - -/* - * CMD_TOUT_ERR (R/W1C) - * - * Command Timeout Error - * In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. - * If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Time out - */ -#define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL) -#define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U) -#define SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) -#define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) - -/* - * ERR_INTERRUPT (RO) - * - * Error Interrupt - * If any of the bits in the Error Interrupt Status register are set, then this bit is set. - * Values: - * 0x0 (FALSE): No Error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U) -#define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U) -#define SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT) - -/* - * CQE_EVENT (R/W1C) - * - * Command Queuing Event - * This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. - * Values: - * 0x0 (FALSE): No Event - * 0x1 (TRUE): Command Queuing Event is detected - */ -#define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U) -#define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U) -#define SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK) -#define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT) - -/* - * FX_EVENT (RO) - * - * FX Event - * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. - * Values: - * 0x0 (FALSE): No Event - * 0x1 (TRUE): FX Event is detected - */ -#define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U) -#define SDXC_INT_STAT_FX_EVENT_SHIFT (13U) -#define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT) - -/* - * RE_TUNE_EVENT (RO) - * - * Re-tuning Event - * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - */ -#define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U) -#define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U) -#define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT) - -/* - * CARD_INTERRUPT (RO) - * - * Card Interrupt - * This bit reflects the synchronized value of: - * DAT[1] Interrupt Input for SD Mode - * DAT[2] Interrupt Input for UHS-II Mode - * Values: - * 0x0 (FALSE): No Card Interrupt - * 0x1 (TRUE): Generate Card Interrupt - */ -#define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U) -#define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U) -#define SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT) - -/* - * CARD_REMOVAL (R/W1C) - * - * Card Removal - * This bit is set if the Card Inserted in the Present State register changes from 1 to 0. - * Values: - * 0x0 (FALSE): Card state stable or Debouncing - * 0x1 (TRUE): Card Removed - */ -#define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U) -#define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U) -#define SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK) -#define SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT) - -/* - * CARD_INSERTION (R/W1C) - * - * Card Insertion - * This bit is set if the Card Inserted in the Present State register changes from 0 to 1. - * Values: - * 0x0 (FALSE): Card state stable or Debouncing - * 0x1 (TRUE): Card Inserted - */ -#define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U) -#define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U) -#define SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK) -#define SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT) - -/* - * BUF_RD_READY (R/W1C) - * - * Buffer Read Ready - * This bit is set if the Buffer Read Enable changes from 0 to 1. - * Values: - * 0x0 (FALSE): Not ready to read buffer - * 0x1 (TRUE): Ready to read buffer - */ -#define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U) -#define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U) -#define SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK) -#define SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT) - -/* - * BUF_WR_READY (R/W1C) - * - * Buffer Write Ready - * This bit is set if the Buffer Write Enable changes from 0 to 1. - * Values: - * 0x0 (FALSE): Not ready to write buffer - * 0x1 (TRUE): Ready to write buffer - */ -#define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U) -#define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U) -#define SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK) -#define SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT) - -/* - * DMA_INTERRUPT (R/W1C) - * - * DMA Interrupt - * This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. - * In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. - * This interrupt is not generated after a Transfer Complete. - * Values: - * 0x0 (FALSE): No DMA Interrupt - * 0x1 (TRUE): DMA Interrupt is generated - */ -#define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U) -#define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U) -#define SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) -#define SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) - -/* - * BGAP_EVENT (R/W1C) - * - * Block Gap Event - * This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. - * Values: - * 0x0 (FALSE): No Block Gap Event - * 0x1 (TRUE): Transaction stopped at block gap - */ -#define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U) -#define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U) -#define SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK) -#define SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT) - -/* - * XFER_COMPLETE (R/W1C) - * - * Transfer Complete - * This bit is set when a read/write transfer and a command with status busy is completed. - * Values: - * 0x0 (FALSE): Not complete - * 0x1 (TRUE): Command execution is completed - */ -#define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U) -#define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U) -#define SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK) -#define SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT) - -/* - * CMD_COMPLETE (R/W1C) - * - * Command Complete - * In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. - * This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. - * Values: - * 0x0 (FALSE): No command complete - * 0x1 (TRUE): Command Complete - */ -#define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U) -#define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U) -#define SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK) -#define SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT) - -/* Bitfield definition for register: INT_STAT_EN */ -/* - * BOOT_ACK_ERR_STAT_EN (RW) - * - * Boot Acknowledgment Error (eMMC Mode only) - * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) - -/* - * RESP_ERR_STAT_EN (RW) - * - * Response Error Status Enable (SD Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) - -/* - * TUNING_ERR_STAT_EN (RW) - * - * Tuning Error Status Enable (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) - -/* - * ADMA_ERR_STAT_EN (RW) - * - * ADMA Error Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) - -/* - * AUTO_CMD_ERR_STAT_EN (RW) - * - * Auto CMD Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) - -/* - * CUR_LMT_ERR_STAT_EN (RW) - * - * Current Limit Error Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) - -/* - * DATA_END_BIT_ERR_STAT_EN (RW) - * - * Data End Bit Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) - -/* - * DATA_CRC_ERR_STAT_EN (RW) - * - * Data CRC Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) - -/* - * DATA_TOUT_ERR_STAT_EN (RW) - * - * Data Timeout Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) - -/* - * CMD_IDX_ERR_STAT_EN (RW) - * - * Command Index Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) - -/* - * CMD_END_BIT_ERR_STAT_EN (RW) - * - * Command End Bit Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) - -/* - * CMD_CRC_ERR_STAT_EN (RW) - * - * Command CRC Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) - -/* - * CMD_TOUT_ERR_STAT_EN (RW) - * - * Command Timeout Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) - -/* - * CQE_EVENT_STAT_EN (RW) - * - * CQE Event Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) - -/* - * FX_EVENT_STAT_EN (RW) - * - * FX Event Status Enable - * This bit is added from Version 4.10. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) - -/* - * RE_TUNE_EVENT_STAT_EN (RW) - * - * Re-Tuning Event (UHS-I only) Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) - -/* - * CARD_INTERRUPT_STAT_EN (RW) - * - * Card Interrupt Status Enable - * If this bit is set to 0, the Host Controller clears the interrupt request to the System. - * The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. - * The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. - * By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) - -/* - * CARD_REMOVAL_STAT_EN (RW) - * - * Card Removal Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) - -/* - * CARD_INSERTION_STAT_EN (RW) - * - * Card Insertion Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) - -/* - * BUF_RD_READY_STAT_EN (RW) - * - * Buffer Read Ready Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) - -/* - * BUF_WR_READY_STAT_EN (RW) - * - * Buffer Write Ready Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) - -/* - * DMA_INTERRUPT_STAT_EN (RW) - * - * DMA Interrupt Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) - -/* - * BGAP_EVENT_STAT_EN (RW) - * - * Block Gap Event Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) - -/* - * XFER_COMPLETE_STAT_EN (RW) - * - * Transfer Complete Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) - -/* - * CMD_COMPLETE_STAT_EN (RW) - * - * Command Complete Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) - -/* Bitfield definition for register: INT_SIGNAL_EN */ -/* - * BOOT_ACK_ERR_SIGNAL_EN (RW) - * - * Boot Acknowledgment Error (eMMC Mode only). - * Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) - -/* - * RESP_ERR_SIGNAL_EN (RW) - * - * Response Error Signal Enable (SD Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) - -/* - * TUNING_ERR_SIGNAL_EN (RW) - * - * Tuning Error Signal Enable (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) - -/* - * ADMA_ERR_SIGNAL_EN (RW) - * - * ADMA Error Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) - -/* - * AUTO_CMD_ERR_SIGNAL_EN (RW) - * - * Auto CMD Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) - -/* - * CUR_LMT_ERR_SIGNAL_EN (RW) - * - * Current Limit Error Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_END_BIT_ERR_SIGNAL_EN (RW) - * - * Data End Bit Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_CRC_ERR_SIGNAL_EN (RW) - * - * Data CRC Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_TOUT_ERR_SIGNAL_EN (RW) - * - * Data Timeout Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_IDX_ERR_SIGNAL_EN (RW) - * - * Command Index Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_END_BIT_ERR_SIGNAL_EN (RW) - * - * Command End Bit Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_CRC_ERR_SIGNAL_EN (RW) - * - * Command CRC Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_TOUT_ERR_SIGNAL_EN (RW) - * - * Command Timeout Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) - -/* - * CQE_EVENT_SIGNAL_EN (RW) - * - * Command Queuing Engine Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) - -/* - * FX_EVENT_SIGNAL_EN (RW) - * - * FX Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) - -/* - * RE_TUNE_EVENT_SIGNAL_EN (RW) - * - * Re-Tuning Event (UHS-I only) Signal Enable. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) - -/* - * CARD_INTERRUPT_SIGNAL_EN (RW) - * - * Card Interrupt Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) - -/* - * CARD_REMOVAL_SIGNAL_EN (RW) - * - * Card Removal Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) - -/* - * CARD_INSERTION_SIGNAL_EN (RW) - * - * Card Insertion Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) - -/* - * BUF_RD_READY_SIGNAL_EN (RW) - * - * Buffer Read Ready Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) - -/* - * BUF_WR_READY_SIGNAL_EN (RW) - * - * Buffer Write Ready Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) - -/* - * DMA_INTERRUPT_SIGNAL_EN (RW) - * - * DMA Interrupt Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) - -/* - * BGAP_EVENT_SIGNAL_EN (RW) - * - * Block Gap Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) - -/* - * XFER_COMPLETE_SIGNAL_EN (RW) - * - * Transfer Complete Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) - -/* - * CMD_COMPLETE_SIGNAL_EN (RW) - * - * Command Complete Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) - -/* Bitfield definition for register: AC_HOST_CTRL */ -/* - * PRESET_VAL_ENABLE (RW) - * - * Preset Value Enable - * This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. - * When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. - * These values are selected from set of Preset Value registers based on selected speed mode. - * Values: - * 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver - * 0x1 (TRUE): Automatic Selection by Preset Value are Enabled - */ -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) - -/* - * ASYNC_INT_ENABLE (RW) - * - * Asynchronous Interrupt Enable - * This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. - * Values: - * 0x0 (FALSE): Disabled - * 0x1 (TRUE): Enabled - */ -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) - -/* - * HOST_VER4_ENABLE (RW) - * - * Host Version 4 Enable - * This bit selects either Version 3.00 compatible mode or Version 4 mode. - * Functions of following fields are modified for Host Version 4 mode: - * SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) - * ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register - * 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 - * Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register - * 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register - * Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, - * UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). - * Values: - * 0x0 (FALSE): Version 3.00 compatible mode - * 0x1 (TRUE): Version 4 mode - */ -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) - -/* - * CMD23_ENABLE (RW) - * - * CMD23 Enable - * If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. - * Values: - * 0x0 (FALSE): Auto CMD23 is disabled - * 0x1 (TRUE): Auto CMD23 is enabled - */ -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) - -/* - * ADMA2_LEN_MODE (RW) - * - * ADMA2 Length Mode - * This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. - * Values: - * 0x0 (FALSE): 16-bit Data Length Mode - * 0x1 (TRUE): 26-bit Data Length Mode - */ -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) - -/* - * SAMPLE_CLK_SEL (RW) - * - * Sampling Clock Select - * This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. - * This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). - * Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. - * The value is reflected on the sample_cclk_sel pin. - * Values: - * 0x0 (FALSE): Fixed clock is used to sample data - * 0x1 (TRUE): Tuned clock is used to sample data - */ -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) - -/* - * EXEC_TUNING (RW) - * - * Execute Tuning - * This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. - * Values: - * 0x0 (FALSE): Not Tuned or Tuning completed - * 0x1 (TRUE): Execute Tuning - */ -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) - -/* - * SIGNALING_EN (RW) - * - * 1.8V Signaling Enable - * This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. - * Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. - * Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. - * Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). - * Values: - * 0x0 (V_3_3): 3.3V Signalling - * 0x1 (V_1_8): 1.8V Signalling - */ -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) - -/* - * UHS_MODE_SEL (RW) - * - * UHS Mode/eMMC Speed Mode Select - * These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. - * UHS Mode (SD/UHS-II mode only): - * 0x0 (SDR12): SDR12/Legacy - * 0x1 (SDR25): SDR25/High Speed SDR - * 0x2 (SDR50): SDR50 - * 0x3 (SDR104): SDR104/HS200 - * 0x4 (DDR50): DDR50/High Speed DDR - * 0x5 (RSVD5): Reserved - * 0x6 (RSVD6): Reserved - * 0x7 (UHS2): UHS-II/HS400 - * eMMC Speed Mode (eMMC mode only): - * 0x0: Legacy - * 0x1: High Speed SDR - * 0x2: Reserved - * 0x3: HS200 - * 0x4: High Speed DDR - * 0x5: Reserved - * 0x6: Reserved - * 0x7: HS400 - */ -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) - -/* - * CMD_NOT_ISSUED_AUTO_CMD12 (RO) - * - * Command Not Issued By Auto CMD12 Error - * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. - * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. - * Values: - * 0x1 (TRUE): Not Issued - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) - -/* - * AUTO_CMD_RESP_ERR (RO) - * - * Auto CMD Response Error - * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. - * This status is ignored if any bit between D00 to D04 is set to 1. - * Values: - * 0x1 (TRUE): Error - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT) - -/* - * AUTO_CMD_IDX_ERR (RO) - * - * Auto CMD Index Error - * This bit is set if the command index error occurs in response to a command. - * Values: - * 0x1 (TRUE): Error - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT) - -/* - * AUTO_CMD_EBIT_ERR (RO) - * - * Auto CMD End Bit Error - * This bit is set when detecting that the end bit of command response is 0. - * Values: - * 0x1 (TRUE): End Bit Error Generated - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT) - -/* - * AUTO_CMD_CRC_ERR (RO) - * - * Auto CMD CRC Error - * This bit is set when detecting a CRC error in the command response. - * Values: - * 0x1 (TRUE): CRC Error Generated - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT) - -/* - * AUTO_CMD_TOUT_ERR (RO) - * - * Auto CMD Timeout Error - * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. - * If this bit is set to 1, error status bits (D04-D01) are meaningless. - * Values: - * 0x1 (TRUE): Time out - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT) - -/* - * AUTO_CMD12_NOT_EXEC (RO) - * - * Auto CMD12 Not Executed - * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. - * Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - * If this bit is set to 1, error status bits (D04-D01) is meaningless. - * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. - * Values: - * 0x1 (TRUE): Not Executed - * 0x0 (FALSE): Executed - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT) - -/* Bitfield definition for register: CAPABILITIES1 */ -/* - * SLOT_TYPE_R (RO) - * - * Slot Type - * These bits indicate usage of a slot by a specific Host System. - * Values: - * 0x0 (REMOVABLE_SLOT): Removable Card Slot - * 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device - * 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) - * 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - */ -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL) -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U) -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT) - -/* - * ASYNC_INT_SUPPORT (RO) - * - * Asynchronous Interrupt Support (SD Mode only) - * Values: - * 0x0 (FALSE): Asynchronous Interrupt Not Supported - * 0x1 (TRUE): Asynchronous Interrupt Supported - */ -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL) -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U) -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT) - -/* - * VOLT_18 (RO) - * - * Voltage Support for 1.8V - * Values: - * 0x0 (FALSE): 1.8V Not Supported - * 0x1 (TRUE): 1.8V Supported - */ -#define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL) -#define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U) -#define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT) - -/* - * VOLT_30 (RO) - * - * Voltage Support for SD 3.0V or Embedded 1.2V - * Values: - * 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported - * 0x1 (TRUE): SD 3.0V or Embedded Supported - */ -#define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL) -#define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U) -#define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT) - -/* - * VOLT_33 (RO) - * - * Voltage Support for 3.3V - * Values: - * 0x0 (FALSE): 3.3V Not Supported - * 0x1 (TRUE): 3.3V Supported - */ -#define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL) -#define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U) -#define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT) - -/* - * SUS_RES_SUPPORT (RO) - * - * Suspense/Resume Support - * This bit indicates whether the Host Controller supports Suspend/Resume functionality. - * If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. - * Values: - * 0x0 (FALSE): Not Supported - * 0x1 (TRUE): Supported - */ -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL) -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U) -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT) - -/* - * SDMA_SUPPORT (RO) - * - * SDMA Support - * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. - * Values: - * 0x0 (FALSE): SDMA not Supported - * 0x1 (TRUE): SDMA Supported - */ -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL) -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U) -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT) - -/* - * HIGH_SPEED_SUPPORT (RO) - * - * High Speed Support - * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. - * Values: - * 0x0 (FALSE): High Speed not Supported - * 0x1 (TRUE): High Speed Supported - */ -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL) -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U) -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT) - -/* - * ADMA2_SUPPORT (RO) - * - * ADMA2 Support - * This bit indicates whether the Host Controller is capable of using ADMA2. - * Values: - * 0x0 (FALSE): ADMA2 not Supported - * 0x1 (TRUE): ADMA2 Supported - */ -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL) -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U) -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT) - -/* - * EMBEDDED_8_BIT (RO) - * - * 8-bit Support for Embedded Device - * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. - * Values: - * 0x0 (FALSE): 8-bit Bus Width not Supported - * 0x1 (TRUE): 8-bit Bus Width Supported - */ -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL) -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U) -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT) - -/* - * MAX_BLK_LEN (RO) - * - * Maximum Block Length - * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. - * The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit - * Values: - * 0x0 (ZERO): 512 Byte - * 0x1 (ONE): 1024 Byte - * 0x2 (TWO): 2048 Byte - * 0x3 (THREE): Reserved - */ -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL) -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U) -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT) - -/* - * BASE_CLK_FREQ (RO) - * - * Base Clock Frequency for SD clock - * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. - * 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. - * The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. - * -0x00 : Get information through another method - * -0x01 : 1 MHz - * -0x02 : 2 MHz - * -............. - * -0x3F : 63 MHz - * -0x40-0xFF : Not Supported - * 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. - * -0x00 : Get information through another method - * -0x01 : 1 MHz - * -0x02 : 2 MHz - * -............ - * -0xFF : 255 MHz - * If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. - * If these bits are all 0, the Host system has to get information using a different method. - */ -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U) -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U) -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT) - -/* - * TOUT_CLK_UNIT (RO) - * - * Timeout Clock Unit - * This bit shows the unit of base clock frequency used to detect Data TImeout Error. - * Values: - * 0x0 (KHZ): KHz - * 0x1 (MHZ): MHz - */ -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U) -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U) -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT) - -/* - * TOUT_CLK_FREQ (RO) - * - * Timeout Clock Frequency - * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. - * 0x00 : Get information through another method - * 0x01 : 1KHz / 1MHz - * 0x02 : 2KHz / 2MHz - * 0x03 : 3KHz / 3MHz - * ........... - * 0x3F : 63KHz / 63MHz - */ -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU) -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U) -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT) - -/* Bitfield definition for register: CAPABILITIES2 */ -/* - * VDD2_18V_SUPPORT (RO) - * - * 1.8V VDD2 Support - * This bit indicates support of VDD2 for the Host System. - * 0x0 (FALSE): 1.8V VDD2 is not Supported - * 0x1 (TRUE): 1.8V VDD2 is Supported - */ -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL) -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U) -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT) - -/* - * ADMA3_SUPPORT (RO) - * - * ADMA3 Support - * This bit indicates whether the Host Controller is capable of using ADMA3. - * Values: - * 0x0 (FALSE): ADMA3 not Supported - * 0x1 (TRUE): ADMA3 Supported - */ -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL) -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U) -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT) - -/* - * CLK_MUL (RO) - * - * Clock Multiplier - * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. - * 0x0: Clock Multiplier is not Supported - * 0x1: Clock Multiplier M = 2 - * 0x2: Clock Multiplier M = 3 - * ......... - * 0xFF: Clock Multiplier M = 256 - */ -#define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL) -#define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U) -#define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT) - -/* - * RE_TUNING_MODES (RO) - * - * Re-Tuning Modes (UHS-I only) - * These bits select the re-tuning method and limit the maximum data length. - * Values: - * 0x0 (MODE1): Timer - * 0x1 (MODE2): Timer and Re-Tuning Request (Not supported) - * 0x2 (MODE3): Auto Re-Tuning (for transfer) - * 0x3 (RSVD_MODE): Reserved - */ -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U) -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U) -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT) - -/* - * USE_TUNING_SDR50 (RO) - * - * Use Tuning for SDR50 (UHS-I only) - * Values: - * 0x0 (ZERO): SDR50 does not require tuning - * 0x1 (ONE): SDR50 requires tuning - */ -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U) -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U) -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT) - -/* - * RETUNE_CNT (RO) - * - * Timer Count for Re-Tuning (UHS-I only) - * 0x0: Re-Tuning Timer disabled - * 0x1: 1 seconds - * 0x2: 2 seconds - * 0x3: 4 seconds - * ........ - * 0xB: 1024 seconds - * 0xC: Reserved - * 0xD: Reserved - * 0xE: Reserved - * 0xF: Get information from other source - */ -#define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U) -#define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U) -#define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT) - -/* - * DRV_TYPED (RO) - * - * Driver Type D Support (UHS-I only) - * This bit indicates support of Driver Type D for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type D is not supported - * 0x1 (TRUE): Driver Type D is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U) -#define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U) -#define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT) - -/* - * DRV_TYPEC (RO) - * - * Driver Type C Support (UHS-I only) - * This bit indicates support of Driver Type C for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type C is not supported - * 0x1 (TRUE): Driver Type C is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U) -#define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U) -#define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT) - -/* - * DRV_TYPEA (RO) - * - * Driver Type A Support (UHS-I only) - * This bit indicates support of Driver Type A for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type A is not supported - * 0x1 (TRUE): Driver Type A is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U) -#define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U) -#define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT) - -/* - * UHS2_SUPPORT (RO) - * - * UHS-II Support (UHS-II only) - * This bit indicates whether Host Controller supports UHS-II. - * Values: - * 0x0 (FALSE): UHS-II is not supported - * 0x1 (TRUE): UHS-II is supported - */ -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U) -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U) -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT) - -/* - * DDR50_SUPPORT (RO) - * - * DDR50 Support (UHS-I only) - * Values: - * 0x0 (FALSE): DDR50 is not supported - * 0x1 (TRUE): DDR50 is supported - */ -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U) -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U) -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT) - -/* - * SDR104_SUPPORT (RO) - * - * SDR104 Support (UHS-I only) - * This bit mentions that SDR104 requires tuning. - * Values: - * 0x0 (FALSE): SDR104 is not supported - * 0x1 (TRUE): SDR104 is supported - */ -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U) -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U) -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT) - -/* - * SDR50_SUPPORT (RO) - * - * SDR50 Support (UHS-I only) - * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. - * Values: - * 0x0 (FALSE): SDR50 is not supported - * 0x1 (TRUE): SDR50 is supported - */ -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U) -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U) -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT) - -/* Bitfield definition for register: CURR_CAPABILITIES1 */ -/* - * MAX_CUR_18V (RO) - * - * Maximum Current for 1.8V - * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT) - -/* - * MAX_CUR_30V (RO) - * - * Maximum Current for 3.0V - * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT) - -/* - * MAX_CUR_33V (RO) - * - * Maximum Current for 3.3V - * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT) - -/* Bitfield definition for register: CURR_CAPABILITIES2 */ -/* - * MAX_CUR_VDD2_18V (RO) - * - * Maximum Current for 1.8V VDD2 - * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU) -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U) -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT) - -/* Bitfield definition for register: FORCE_EVENT */ -/* - * FORCE_BOOT_ACK_ERR (WO) - * - * Force Event for Boot Ack error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Boot ack Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) - -/* - * FORCE_RESP_ERR (WO) - * - * Force Event for Response Error (SD Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Response Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) - -/* - * FORCE_TUNING_ERR (WO) - * - * Force Event for Tuning Error (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Tuning Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) - -/* - * FORCE_ADMA_ERR (WO) - * - * Force Event for ADMA Error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): ADMA Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_ERR (WO) - * - * Force Event for Auto CMD Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Auto CMD Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) - -/* - * FORCE_CUR_LMT_ERR (WO) - * - * Force Event for Current Limit Error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Current Limit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) - -/* - * FORCE_DATA_END_BIT_ERR (WO) - * - * Force Event for Data End Bit Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data End Bit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) - -/* - * FORCE_DATA_CRC_ERR (WO) - * - * Force Event for Data CRC Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data CRC Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) - -/* - * FORCE_DATA_TOUT_ERR (WO) - * - * Force Event for Data Timeout Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data Timeout Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) - -/* - * FORCE_CMD_IDX_ERR (WO) - * - * Force Event for Command Index Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command Index Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) - -/* - * FORCE_CMD_END_BIT_ERR (WO) - * - * Force Event for Command End Bit Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command End Bit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) - -/* - * FORCE_CMD_CRC_ERR (WO) - * - * Force Event for Command CRC Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command CRC Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) - -/* - * FORCE_CMD_TOUT_ERR (WO) - * - * Force Event for Command Timeout Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command Timeout Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) - -/* - * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (WO) - * - * Force Event for Command Not Issued By Auto CMD12 Error - * Values: - * 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) - -/* - * FORCE_AUTO_CMD_RESP_ERR (WO) - * - * Force Event for Auto CMD Response Error - * Values: - * 0x1 (TRUE): Auto CMD Response Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_IDX_ERR (WO) - * - * Force Event for Auto CMD Index Error - * Values: - * 0x1 (TRUE): Auto CMD Index Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_EBIT_ERR (WO) - * - * Force Event for Auto CMD End Bit Error - * Values: - * 0x1 (TRUE): Auto CMD End Bit Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_CRC_ERR (WO) - * - * Force Event for Auto CMD CRC Error - * Values: - * 0x1 (TRUE): Auto CMD CRC Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_TOUT_ERR (WO) - * - * Force Event for Auto CMD Timeout Error - * Values: - * 0x1 (TRUE): Auto CMD Timeout Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD12_NOT_EXEC (WO) - * - * Force Event for Auto CMD12 Not Executed - * Values: - * 0x1 (TRUE): Auto CMD12 Not Executed Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) - -/* Bitfield definition for register: ADMA_ERR_STAT */ -/* - * ADMA_LEN_ERR (RO) - * - * ADMA Length Mismatch Error States - * This error occurs in the following instances: - * While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length - * When the total data length cannot be divided by the block length - * Values: - * 0x0 (NO_ERR): No Error - * 0x1 (ERROR): Error - */ -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U) -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U) -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT) - -/* - * ADMA_ERR_STATES (RO) - * - * ADMA Error States - * These bits indicate the state of ADMA when an error occurs during ADMA data transfer. - * Values: - * 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor - * 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor - * 0x2 (UNUSED): Never set this state - * 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - */ -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U) -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U) -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT) - -/* Bitfield definition for register: ADMA_SYS_ADDR */ -/* - * ADMA_SA (RW) - * - * ADMA System Address - * These bits indicate the lower 32 bits of the ADMA system address. - * SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location - * ADMA2: This register stores the byte address of the executing command of the descriptor table - * ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - */ -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) - -/* Bitfield definition for register array: PRESET */ -/* - * CLK_GEN_SEL_VAL (RO) - * - * Clock Generator Select Value - * This bit is effective when the Host Controller supports a programmable clock generator. - * Values: - * 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator - * 0x1 (PROG): Programmable Clock Generator - */ -#define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U) -#define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U) -#define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT) - -/* - * FREQ_SEL_VAL (RO) - * - * SDCLK/RCLK Frequency Select Value - * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - */ -#define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU) -#define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U) -#define SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT) - -/* Bitfield definition for register: ADMA_ID_ADDR */ -/* - * ADMA_ID_ADDR (RW) - * - * ADMA Integrated Descriptor Address - * These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. - * The start address of Integrated Descriptor is set to these register bits. - * The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - */ -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) - -/* Bitfield definition for register: P_EMBEDDED_CNTRL */ -/* - * REG_OFFSET_ADDR (RO) - * - * Offset Address of Embedded Control register. - */ -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU) -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */ -/* - * REG_OFFSET_ADDR (RO) - * - * Base offset Address for Vendor-Specific registers. - */ -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU) -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */ -/* - * REG_OFFSET_ADDR (RO) - * - * Base offset Address for Command Queuing registers. - */ -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU) -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: SLOT_INTR_STATUS */ -/* - * INTR_SLOT (RO) - * - * Interrupt signal for each Slot - * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. - * A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - * By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. - * Bit 00: Slot 1 - * Bit 01: Slot 2 - * Bit 02: Slot 3 - * .......... - * .......... - * Bit 07: Slot 8 - * Note: MSHC Host Controller support single card slot. This register shall always return 0. - */ -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU) -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U) -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT) - -/* Bitfield definition for register: CQVER */ -/* - * EMMC_VER_MAHOR (RO) - * - * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U) -#define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U) -#define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT) - -/* - * EMMC_VER_MINOR (RO) - * - * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U) -#define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U) -#define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT) - -/* - * EMMC_VER_SUFFIX (RO) - * - * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU) -#define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U) -#define SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT) - -/* Bitfield definition for register: CQCAP */ -/* - * CRYPTO_SUPPORT (RO) - * - * Crypto Support - * This bit indicates whether the Host Controller supports cryptographic operations. - * Values: - * 0x0 (FALSE): Crypto not Supported - * 0x1 (TRUE): Crypto Supported - */ -#define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL) -#define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U) -#define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT) - -/* - * ITCFMUL (RO) - * - * Internal Timer Clock Frequency Multiplier (ITCFMUL) - * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS - * polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. - * Values: - * 0x0 (CLK_1KHz): 1KHz clock - * 0x1 (CLK_10KHz): 10KHz clock - * 0x2 (CLK_100KHz): 100KHz clock - * 0x3 (CLK_1MHz): 1MHz clock - * 0x4 (CLK_10MHz): 10MHz clock - */ -#define SDXC_CQCAP_ITCFMUL_MASK (0xF000U) -#define SDXC_CQCAP_ITCFMUL_SHIFT (12U) -#define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT) - -/* - * ITCFVAL (RO) - * - * Internal Timer Clock Frequency Value (ITCFVAL) - * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - */ -#define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU) -#define SDXC_CQCAP_ITCFVAL_SHIFT (0U) -#define SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT) - -/* Bitfield definition for register: CQCFG */ -/* - * DCMD_EN (RW) - * - * This bit indicates to the hardware whether the Task - * Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. - * Values: - * 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - * 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - */ -#define SDXC_CQCFG_DCMD_EN_MASK (0x1000U) -#define SDXC_CQCFG_DCMD_EN_SHIFT (12U) -#define SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK) -#define SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT) - -/* - * TASK_DESC_SIZE (RW) - * - * Bit Value Description - * This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). - * Values: - * 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - * 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - */ -#define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U) -#define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U) -#define SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) -#define SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) - -/* - * CQ_EN (RW) - * - */ -#define SDXC_CQCFG_CQ_EN_MASK (0x1U) -#define SDXC_CQCFG_CQ_EN_SHIFT (0U) -#define SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK) -#define SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT) - -/* Bitfield definition for register: CQCTL */ -/* - * CLR_ALL_TASKS (RW) - * - * Clear all tasks - * This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. - * Values: - * 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller - * 0x0 (NO_EFFECT): Programming 0 has no effect - */ -#define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U) -#define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U) -#define SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) -#define SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) - -/* - * HALT (RW) - * - * Halt request and resume - * Values: - * 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. - * For example, issuing a Discard Task command (CMDQ_TASK_MGMT). - * When the software writes 1, CQE completes the ongoing task (if any in progress). - * After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. - * The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. - * 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - */ -#define SDXC_CQCTL_HALT_MASK (0x1U) -#define SDXC_CQCTL_HALT_SHIFT (0U) -#define SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK) -#define SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT) - -/* Bitfield definition for register: CQIS */ -/* - * TCL (RW) - * - * Task cleared interrupt - * This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. - * The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): TCL Interrupt is set - * 0x0 (NOTSET): TCL Interrupt is not set - */ -#define SDXC_CQIS_TCL_MASK (0x8U) -#define SDXC_CQIS_TCL_SHIFT (3U) -#define SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK) -#define SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT) - -/* - * RED (RW) - * - * Response error detected interrupt - * This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status - * field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): RED Interrupt is set - * 0x0 (NOTSET): RED Interrupt is not set - */ -#define SDXC_CQIS_RED_MASK (0x4U) -#define SDXC_CQIS_RED_SHIFT (2U) -#define SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK) -#define SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT) - -/* - * TCC (RW) - * - * Task complete interrupt - * This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: - * A task is completed and the INT bit is set in its Task Descriptor - * Interrupt caused by Interrupt Coalescing logic due to timeout - * Interrupt Coalescing logic reached the configured threshold - * A value of 1 clears this status bit - */ -#define SDXC_CQIS_TCC_MASK (0x2U) -#define SDXC_CQIS_TCC_SHIFT (1U) -#define SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK) -#define SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT) - -/* - * HAC (RW) - * - * Halt complete interrupt - * This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): HAC Interrupt is set - * 0x0 (NOTSET): HAC Interrupt is not set - */ -#define SDXC_CQIS_HAC_MASK (0x1U) -#define SDXC_CQIS_HAC_SHIFT (0U) -#define SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK) -#define SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT) - -/* Bitfield definition for register: CQISE */ -/* - * TCL_STE (RW) - * - * Task cleared interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - */ -#define SDXC_CQISE_TCL_STE_MASK (0x8U) -#define SDXC_CQISE_TCL_STE_SHIFT (3U) -#define SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK) -#define SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT) - -/* - * RED_STE (RW) - * - * Response error detected interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.RED is disabled - */ -#define SDXC_CQISE_RED_STE_MASK (0x4U) -#define SDXC_CQISE_RED_STE_SHIFT (2U) -#define SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK) -#define SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT) - -/* - * TCC_STE (RW) - * - * Task complete interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - */ -#define SDXC_CQISE_TCC_STE_MASK (0x2U) -#define SDXC_CQISE_TCC_STE_SHIFT (1U) -#define SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK) -#define SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT) - -/* - * HAC_STE (RW) - * - * Halt complete interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - */ -#define SDXC_CQISE_HAC_STE_MASK (0x1U) -#define SDXC_CQISE_HAC_STE_SHIFT (0U) -#define SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK) -#define SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT) - -/* Bitfield definition for register: CQISGE */ -/* - * TCL_SGE (RW) - * - * Task cleared interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - */ -#define SDXC_CQISGE_TCL_SGE_MASK (0x8U) -#define SDXC_CQISGE_TCL_SGE_SHIFT (3U) -#define SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK) -#define SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT) - -/* - * RED_SGE (RW) - * - * Response error detected interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - */ -#define SDXC_CQISGE_RED_SGE_MASK (0x4U) -#define SDXC_CQISGE_RED_SGE_SHIFT (2U) -#define SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK) -#define SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT) - -/* - * TCC_SGE (RW) - * - * Task complete interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - */ -#define SDXC_CQISGE_TCC_SGE_MASK (0x2U) -#define SDXC_CQISGE_TCC_SGE_SHIFT (1U) -#define SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK) -#define SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT) - -/* - * HAC_SGE (RW) - * - * Halt complete interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - */ -#define SDXC_CQISGE_HAC_SGE_MASK (0x1U) -#define SDXC_CQISGE_HAC_SGE_SHIFT (0U) -#define SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK) -#define SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT) - -/* Bitfield definition for register: CQIC */ -/* - * INTC_EN (RW) - * - * Interrupt Coalescing Enable Bit - * Values: - * 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated - * 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - */ -#define SDXC_CQIC_INTC_EN_MASK (0x80000000UL) -#define SDXC_CQIC_INTC_EN_SHIFT (31U) -#define SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK) -#define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT) - -/* - * INTC_STAT (RO) - * - * Interrupt Coalescing Status Bit - * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt - * coalescing (that is, this is set if and only if INTC counter > 0). - * Values: - * 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) - * 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - */ -#define SDXC_CQIC_INTC_STAT_MASK (0x100000UL) -#define SDXC_CQIC_INTC_STAT_SHIFT (20U) -#define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT) - -/* - * INTC_RST (WO) - * - * Counter and Timer Reset - * When host driver writes 1, the interrupt coalescing timer and counter are reset. - * Values: - * 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset - * 0x0 (NO_EFFECT): No Effect - */ -#define SDXC_CQIC_INTC_RST_MASK (0x10000UL) -#define SDXC_CQIC_INTC_RST_SHIFT (16U) -#define SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK) -#define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT) - -/* - * INTC_TH_WEN (WO) - * - * Interrupt Coalescing Counter Threshold Write Enable - * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. - * Values: - * 0x1 (WEN_SET): Sets INTC_TH_WEN - * 0x0 (WEN_CLR): Clears INTC_TH_WEN - */ -#define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U) -#define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U) -#define SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK) -#define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT) - -/* - * INTC_TH (WO) - * - * Interrupt Coalescing Counter Threshold filed - * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. - * Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. - * The counter is reset by software during the interrupt service routine. - * The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. - * 0x0: Interrupt coalescing feature disabled - * 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes - * 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes - * ........ - * 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes - * To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - */ -#define SDXC_CQIC_INTC_TH_MASK (0x1F00U) -#define SDXC_CQIC_INTC_TH_SHIFT (8U) -#define SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK) -#define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT) - -/* - * TOUT_VAL_WEN (WO) - * - * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. - * Values: - * 0x1 (WEN_SET): Sets TOUT_VAL_WEN - * 0x0 (WEN_CLR): clears TOUT_VAL_WEN - */ -#define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U) -#define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U) -#define SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK) -#define SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT) - -/* - * TOUT_VAL (RW) - * - * Interrupt Coalescing Timeout Value - * Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. - * Timer Operation: The timer is reset by software during the interrupt service routine. - * It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. - * When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. - * The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. - * 0x0: Timer is disabled. Timeout-based interrupt is not generated - * 0x1: Timeout on 01x1024 cycles of timer clock frequency - * 0x2: Timeout on 02x1024 cycles of timer clock frequency - * ........ - * 0x7f: Timeout on 127x1024 cycles of timer clock frequency - * In order to write to this field, the TOUT_VAL_WEN bit must - * be set at the same write operation. - */ -#define SDXC_CQIC_TOUT_VAL_MASK (0x7FU) -#define SDXC_CQIC_TOUT_VAL_SHIFT (0U) -#define SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK) -#define SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT) - -/* Bitfield definition for register: CQTDLBA */ -/* - * TDLBA (RW) - * - * This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. - * The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. - * This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - */ -#define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL) -#define SDXC_CQTDLBA_TDLBA_SHIFT (0U) -#define SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK) -#define SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT) - -/* Bitfield definition for register: CQTDBR */ -/* - * DBR (RW) - * - * The software configures TDLBA and TDLBAU, and enable - * CQE in CQCFG before using this register. - * Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. - * Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. - * CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. - * CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to - * the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. - * The corresponding bit is cleared to 0 by CQE in one of the following events: - * A task execution is completed (with success or error). - * The task is cleared using CQTCLR register. - * All tasks are cleared using CQCTL register. - * CQE is disabled using CQCFG register. - * Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. - * In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. - * If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - */ -#define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL) -#define SDXC_CQTDBR_DBR_SHIFT (0U) -#define SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK) -#define SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT) - -/* Bitfield definition for register: CQTCN */ -/* - * TCN (RW) - * - * Task Completion Notification - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Task-N has completed execution (with success or errors) - * Bit-N(0): Task-N has not completed, could be pending or not submitted. - * On task completion, software may read this register to know tasks that have completed. After reading this register, - * software may clear the relevant bit fields by writing 1 to the corresponding bits. - */ -#define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL) -#define SDXC_CQTCN_TCN_SHIFT (0U) -#define SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK) -#define SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT) - -/* Bitfield definition for register: CQDQS */ -/* - * DQS (RW) - * - * Device Queue Status - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Device has marked task N as ready for execution - * Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. - * Host controller updates this register with response of the Device Queue Status command. - */ -#define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL) -#define SDXC_CQDQS_DQS_SHIFT (0U) -#define SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK) -#define SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT) - -/* Bitfield definition for register: CQDPT */ -/* - * DPT (RW) - * - * Device-Pending Tasks - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution - * Bit-N(0): Task-N is not yet queued. - * Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. - * The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. - * Software reads this register in the task-discard procedure to determine if the task is queued in the device - */ -#define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL) -#define SDXC_CQDPT_DPT_SHIFT (0U) -#define SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK) -#define SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT) - -/* Bitfield definition for register: CQTCLR */ -/* - * TCLR (RW) - * - * Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. - * This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. - * When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. - * CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. - * Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - */ -#define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL) -#define SDXC_CQTCLR_TCLR_SHIFT (0U) -#define SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK) -#define SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT) - -/* Bitfield definition for register: CQSSC1 */ -/* - * SQSCMD_BLK_CNT (RW) - * - * This field indicates when SQS CMD is sent while data transfer is in progress. - * A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. - * 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. - * 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. - * 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. - * 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. - * ........ - * 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. - * Should be programmed only when CQCFG.CQ_EN is 0 - */ -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) - -/* - * SQSCMD_IDLE_TMR (RW) - * - * This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. - * Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. - * When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. - * Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. - * The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). - * For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). - * If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. - * Should be programmed only when CQCFG.CQ_EN is '0' - */ -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) - -/* Bitfield definition for register: CQSSC2 */ -/* - * SQSCMD_RCA (RW) - * - * This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. - * CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - */ -#define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU) -#define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U) -#define SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK) -#define SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT) - -/* Bitfield definition for register: CQCRDCT */ -/* - * DCMD_RESP (RO) - * - * This register contains the response of the command generated by the last direct command (DCMD) task that was sent. - * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - */ -#define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL) -#define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U) -#define SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT) - -/* Bitfield definition for register: CQRMEM */ -/* - * RESP_ERR_MASK (RW) - * - * The bits of this field are bit mapped to the device response. - * This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. - * 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. - * 0: When a R1/R1b response is received, bit i in the device status is ignored. - * The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. - * Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - */ -#define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL) -#define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U) -#define SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) -#define SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) - -/* Bitfield definition for register: CQTERRI */ -/* - * TRANS_ERR_TASKID (RO) - * - * This field captures the ID of the task that was executed and whose data transfer has errors. - */ -#define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL) -#define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U) -#define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT) - -/* - * TRANS_ERR_CMD_INDX (RO) - * - * This field captures the index of the command that was executed and whose data transfer has errors. - */ -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL) -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U) -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT) - -/* - * RESP_ERR_FIELDS_VALID (RO) - * - * This bit is updated when an error is detected while a command transaction was in progress. - * Values: - * 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields - * 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - */ -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U) -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U) -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT) - -/* - * RESP_ERR_TASKID (RO) - * - * This field captures the ID of the task which was executed on the command line when the error occurred. - */ -#define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U) -#define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U) -#define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT) - -/* - * RESP_ERR_CMD_INDX (RO) - * - * This field captures the index of the command that was executed on the command line when the error occurred - */ -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU) -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U) -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT) - -/* Bitfield definition for register: CQCRI */ -/* - * CMD_RESP_INDX (RO) - * - * Last Command Response index - * This field stores the index of the last received command response. Controller updates the value every time a command response is received - */ -#define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU) -#define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U) -#define SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT) - -/* Bitfield definition for register: CQCRA */ -/* - * CMD_RESP_ARG (RO) - * - * Last Command Response argument - * This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - */ -#define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL) -#define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U) -#define SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT) - -/* Bitfield definition for register: MSHC_VER_ID */ -/* - * VER_ID (RO) - * - */ -#define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL) -#define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U) -#define SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT) - -/* Bitfield definition for register: MSHC_VER_TYPE */ -/* - * VER_TYPE (RO) - * - */ -#define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL) -#define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U) -#define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT) - -/* Bitfield definition for register: EMMC_BOOT_CTRL */ -/* - * BOOT_TOUT_CNT (RW) - * - * Boot Ack Timeout Counter Value. - * This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. - * 0xF : Reserved - * 0xE : TMCLK x 2^27 - * ............ - * 0x1 : TMCLK x 2^14 - * 0x0 : TMCLK x 2^13 - */ -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) - -/* - * BOOT_ACK_ENABLE (RW) - * - * Boot Acknowledge Enable - * When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. - * Values: - * 0x1 (TRUE): Boot Ack enable - * 0x0 (FALSE): Boot Ack disable - */ -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) - -/* - * VALIDATE_BOOT (WO) - * - * Validate Mandatory Boot Enable bit - * This bit is used to validate the MAN_BOOT_EN bit. - * Values: - * 0x1 (TRUE): Validate Mandatory boot enable bit - * 0x0 (FALSE): Ignore Mandatory boot Enable bit - */ -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) - -/* - * MAN_BOOT_EN (RW) - * - * Mandatory Boot Enable - * This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. - * Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. - * Values: - * 0x1 (MAN_BOOT_EN): Mandatory boot enable - * 0x0 (MAN_BOOT_DIS): Mandatory boot disable - */ -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) - -/* - * CQE_PREFETCH_DISABLE (RW) - * - * Enable or Disable CQE's PREFETCH feature - * This field allows Software to disable CQE's data prefetch feature when set to 1. - * Values: - * 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers - * 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - */ -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) - -/* - * CQE_ALGO_SEL (RW) - * - * Scheduler algorithm selected for execution - * This bit selects the Algorithm used for selecting one of the many ready tasks for execution. - * Values: - * 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks - * 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - */ -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) - -/* - * ENH_STROBE_ENABLE (RW) - * - * Enhanced Strobe Enable - * This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. - * Values: - * 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode - * 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - */ -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) - -/* - * EMMC_RST_N_OE (RW) - * - * Output Enable control for EMMC Device Reset signal PAD - * control. - * This field drived sd_rst_n_oe output of SDXC - * Values: - * 0x1 (ENABLE): sd_rst_n_oe is 1 - * 0x0 (DISABLE): sd_rst_n_oe is 0 - */ -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) - -/* - * EMMC_RST_N (RW) - * - * EMMC Device Reset signal control. - * This register field controls the sd_rst_n output of SDXC - * Values: - * 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted - * 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - */ -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) - -/* - * DISABLE_DATA_CRC_CHK (RW) - * - * Disable Data CRC Check - * This bit controls masking of CRC16 error for Card Write in eMMC mode. - * This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, - * which may generate CRC error. This CRC error can be masked using this bit during bus testing. - * Values: - * 0x1 (DISABLE): DATA CRC check is disabled - * 0x0 (ENABLE): DATA CRC check is enabled - */ -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) - -/* - * CARD_IS_EMMC (RW) - * - * eMMC Card present - * This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. - * Values: - * 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card - * 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - */ -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) - -/* Bitfield definition for register: AUTO_TUNING_CTRL */ -/* - * SWIN_TH_VAL (RW) - * - * Sampling window threshold value setting - * The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps - * can use values from 0x0 to 0x1F. - * This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' - * 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. - * 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. - * 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. - * ........ - * 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - */ -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) - -/* - * POST_CHANGE_DLY (RW) - * - * Time taken for phase switching and stable clock output. - * Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. - * Values: - * 0x0 (LATENCY_LT_1): Less than 1-cycle latency - * 0x1 (LATENCY_LT_2): Less than 2-cycle latency - * 0x2 (LATENCY_LT_3): Less than 3-cycle latency - * 0x3 (LATENCY_LT_4): Less than 4-cycle latency - */ -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) - -/* - * PRE_CHANGE_DLY (RW) - * - * Maximum Latency specification between cclk_tx and cclk_rx. - * Values: - * 0x0 (LATENCY_LT_1): Less than 1-cycle latency - * 0x1 (LATENCY_LT_2): Less than 2-cycle latency - * 0x2 (LATENCY_LT_3): Less than 3-cycle latency - * 0x3 (LATENCY_LT_4): Less than 4-cycle latency - */ -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) - -/* - * TUNE_CLK_STOP_EN (RW) - * - * Clock stopping control for Tuning and auto-tuning circuit. - * When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. - * This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - * Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. - * Values: - * 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change - * 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - */ -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) - -/* - * WIN_EDGE_SEL (RW) - * - * This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. - * 0x0: User selection disabled. Tuning calculated edges are used. - * 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. - * 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess - * ... - * 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - */ -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) - -/* - * SW_TUNE_EN (RW) - * - * This fields enables software-managed tuning flow. - * Values: - * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. - * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - */ -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) - -/* - * RPT_TUNE_ERR (RW) - * - * Framing errors are not generated when executing tuning. - * This debug bit allows users to report these errors. - * Values: - * 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors - * 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - */ -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) - -/* - * SWIN_TH_EN (RW) - * - * Sampling window Threshold enable - * Selects the tuning mode - * Field should be programmed only when SAMPLE_CLK_SEL is '0' - * Values: - * 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold - * set by SWIN_TH_VAL field - * 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - */ -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) - -/* - * CI_SEL (RW) - * - * Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. - * Values: - * 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval - * 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - */ -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) - -/* - * AT_EN (RW) - * - * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. - * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. - * This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. - * Values: - * 0x1 (AT_ENABLE): AutoTuning is enabled - * 0x0 (AT_DISABLE): AutoTuning is disabled - */ -#define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) - -/* Bitfield definition for register: AUTO_TUNING_STAT */ -/* - * L_EDGE_PH_CODE (RO) - * - * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - */ -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL) -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U) -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT) - -/* - * R_EDGE_PH_CODE (RO) - * - * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - */ -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U) -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U) -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT) - -/* - * CENTER_PH_CODE (RW) - * - * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - */ -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) - - - -/* RESP register group index macro definition */ -#define SDXC_RESP_RESP01 (0UL) -#define SDXC_RESP_RESP23 (1UL) -#define SDXC_RESP_RESP45 (2UL) -#define SDXC_RESP_RESP67 (3UL) - -/* PRESET register group index macro definition */ -#define SDXC_PRESET_INIT (0UL) -#define SDXC_PRESET_DS (1UL) -#define SDXC_PRESET_HS (2UL) -#define SDXC_PRESET_SDR12 (3UL) -#define SDXC_PRESET_SDR25 (4UL) -#define SDXC_PRESET_SDR50 (5UL) -#define SDXC_PRESET_SDR104 (6UL) -#define SDXC_PRESET_DDR50 (7UL) -#define SDXC_PRESET_UHS2 (10UL) - - -#endif /* HPM_SDXC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_spi_regs.h deleted file mode 100644 index 8ee088e0d91..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_spi_regs.h +++ /dev/null @@ -1,784 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SPI_H -#define HPM_SPI_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ - __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ - __RW uint32_t CMD; /* 0x24: Command Register */ - __RW uint32_t ADDR; /* 0x28: Address Register */ - __RW uint32_t DATA; /* 0x2C: Data Register */ - __RW uint32_t CTRL; /* 0x30: Control Register */ - __R uint32_t STATUS; /* 0x34: Status Register */ - __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ - __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED2[28]; /* 0x44 - 0x5F: Reserved */ - __RW uint32_t SLVST; /* 0x60: Slave Status Register */ - __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint8_t RESERVED3[20]; /* 0x68 - 0x7B: Reserved */ - __R uint32_t CONFIG; /* 0x7C: Configuration Register */ -} SPI_Type; - - -/* Bitfield definition for register: TRANSFMT */ -/* - * ADDRLEN (RW) - * - * Address length in bytes - * 0x0: 1 byte - * 0x1: 2 bytes - * 0x2: 3 bytes - * 0x3: 4 bytes - */ -#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) -#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) -#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) -#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) - -/* - * DATALEN (RW) - * - * The length of each data unit in bits - * The actual bit number of a data unit is (DataLen + 1) - */ -#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) -#define SPI_TRANSFMT_DATALEN_SHIFT (8U) -#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) -#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) - -/* - * DATAMERGE (RW) - * - * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. - * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. - * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - */ -#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) -#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) -#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) -#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) - -/* - * MOSIBIDIR (RW) - * - * Bi-directional MOSI in regular (single) mode - * 0x0: MOSI is uni-directional signal in regular mode. - * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - */ -#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) -#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) -#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) -#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) - -/* - * LSB (RW) - * - * Transfer data with the least significant bit first - * 0x0: Most significant bit first - * 0x1: Least significant bit first - */ -#define SPI_TRANSFMT_LSB_MASK (0x8U) -#define SPI_TRANSFMT_LSB_SHIFT (3U) -#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) -#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) - -/* - * SLVMODE (RW) - * - * SPI Master/Slave mode selection - * 0x0: Master mode - * 0x1: Slave mode - */ -#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) -#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) -#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) -#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) - -/* - * CPOL (RW) - * - * SPI Clock Polarity - * 0x0: SCLK is LOW in the idle states - * 0x1: SCLK is HIGH in the idle states - */ -#define SPI_TRANSFMT_CPOL_MASK (0x2U) -#define SPI_TRANSFMT_CPOL_SHIFT (1U) -#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) -#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) - -/* - * CPHA (RW) - * - * SPI Clock Phase - * 0x0: Sampling data at odd SCLK edges - * 0x1: Sampling data at even SCLK edges - */ -#define SPI_TRANSFMT_CPHA_MASK (0x1U) -#define SPI_TRANSFMT_CPHA_SHIFT (0U) -#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) -#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) - -/* Bitfield definition for register: TRANSCTRL */ -/* - * SLVDATAONLY (RW) - * - * Data-only mode (slave mode only) - * 0x0: Disable the data-only mode - * 0x1: Enable the data-only mode - * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - */ -#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) -#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) -#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) -#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) - -/* - * CMDEN (RW) - * - * SPI command phase enable (Master mode only) - * 0x0: Disable the command phase - * 0x1: Enable the command phase - */ -#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) -#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) -#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) -#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) - -/* - * ADDREN (RW) - * - * SPI address phase enable (Master mode only) - * 0x0: Disable the address phase - * 0x1: Enable the address phase - */ -#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) -#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) -#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) -#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) - -/* - * ADDRFMT (RW) - * - * SPI address phase format (Master mode only) - * 0x0: Address phase is the regular (single) mode - * 0x1: The format of the address phase is the same as the data phase (DualQuad). - */ -#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) -#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) -#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) -#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) - -/* - * TRANSMODE (RW) - * - * Transfer mode - * The transfer sequence could be - * 0x0: Write and read at the same time - * 0x1: Write only - * 0x2: Read only - * 0x3: Write, Read - * 0x4: Read, Write - * 0x5: Write, Dummy, Read - * 0x6: Read, Dummy, Write - * 0x7: None Data (must enable CmdEn or AddrEn in master mode) - * 0x8: Dummy, Write - * 0x9: Dummy, Read - * 0xa~0xf: Reserved - */ -#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) -#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) -#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) -#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) - -/* - * DUALQUAD (RW) - * - * SPI data phase format - * 0x0: Regular (Single) mode - * 0x1: Dual I/O mode - * 0x2: Quad I/O mode - * 0x3: Reserved - */ -#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) -#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) -#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) -#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) - -/* - * TOKENEN (RW) - * - * Token transfer enable (Master mode only) - * Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. - * 0x0: Disable the one-byte special token - * 0x1: Enable the one-byte special token - */ -#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) -#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) -#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) -#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) - -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) -#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) -#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) -#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) - -/* - * TOKENVALUE (RW) - * - * Token value (Master mode only) - * The value of the one-byte special token following the address phase for SPI read transfers. - * 0x0: token value = 0x00 - * 0x1: token value = 0x69 - */ -#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) -#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) -#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) -#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) - -/* - * DUMMYCNT (RW) - * - * Dummy data count. The actual dummy count is (DummyCnt +1). - * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) - * The Data pins are put into the high impedance during the dummy data phase. - * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - */ -#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) -#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) -#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) -#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) - -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) -#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) -#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) -#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * SPI Command - */ -#define SPI_CMD_CMD_MASK (0xFFU) -#define SPI_CMD_CMD_SHIFT (0U) -#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) -#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * SPI Address - * (Master mode only) - */ -#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define SPI_ADDR_ADDR_SHIFT (0U) -#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) -#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Data to transmit or the received data - * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. - * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - */ -#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SPI_DATA_DATA_SHIFT (0U) -#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) -#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * TXTHRES (RW) - * - * Transmit (TX) FIFO Threshold - * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - */ -#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) -#define SPI_CTRL_TXTHRES_SHIFT (16U) -#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) -#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) - -/* - * RXTHRES (RW) - * - * Receive (RX) FIFO Threshold - * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - */ -#define SPI_CTRL_RXTHRES_MASK (0xFF00U) -#define SPI_CTRL_RXTHRES_SHIFT (8U) -#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) -#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) - -/* - * TXDMAEN (RW) - * - * TX DMA enable - */ -#define SPI_CTRL_TXDMAEN_MASK (0x10U) -#define SPI_CTRL_TXDMAEN_SHIFT (4U) -#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) -#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) - -/* - * RXDMAEN (RW) - * - * RX DMA enable - */ -#define SPI_CTRL_RXDMAEN_MASK (0x8U) -#define SPI_CTRL_RXDMAEN_SHIFT (3U) -#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) -#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) - -/* - * TXFIFORST (RW) - * - * Transmit FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_TXFIFORST_MASK (0x4U) -#define SPI_CTRL_TXFIFORST_SHIFT (2U) -#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) -#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) - -/* - * RXFIFORST (RW) - * - * Receive FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_RXFIFORST_MASK (0x2U) -#define SPI_CTRL_RXFIFORST_SHIFT (1U) -#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) -#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) - -/* - * SPIRST (RW) - * - * SPI reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_SPIRST_MASK (0x1U) -#define SPI_CTRL_SPIRST_SHIFT (0U) -#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) -#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TXNUM_7_6 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) -#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) -#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) - -/* - * RXNUM_7_6 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) -#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) -#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) - -/* - * TXFULL (RO) - * - * Transmit FIFO Full flag - */ -#define SPI_STATUS_TXFULL_MASK (0x800000UL) -#define SPI_STATUS_TXFULL_SHIFT (23U) -#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) - -/* - * TXEMPTY (RO) - * - * Transmit FIFO Empty flag - */ -#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) -#define SPI_STATUS_TXEMPTY_SHIFT (22U) -#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) - -/* - * TXNUM_5_0 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) -#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) -#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) - -/* - * RXFULL (RO) - * - * Receive FIFO Full flag - */ -#define SPI_STATUS_RXFULL_MASK (0x8000U) -#define SPI_STATUS_RXFULL_SHIFT (15U) -#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) - -/* - * RXEMPTY (RO) - * - * Receive FIFO Empty flag - */ -#define SPI_STATUS_RXEMPTY_MASK (0x4000U) -#define SPI_STATUS_RXEMPTY_SHIFT (14U) -#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) - -/* - * RXNUM_5_0 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) -#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) -#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) - -/* - * SPIACTIVE (RO) - * - * SPI register programming is in progress. - * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. - * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. - * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. - * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - */ -#define SPI_STATUS_SPIACTIVE_MASK (0x1U) -#define SPI_STATUS_SPIACTIVE_SHIFT (0U) -#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) - -/* Bitfield definition for register: INTREN */ -/* - * SLVCMDEN (RW) - * - * Enable the Slave Command Interrupt. - * Control whether interrupts are triggered whenever slave commands are received. - * (Slave mode only) - */ -#define SPI_INTREN_SLVCMDEN_MASK (0x20U) -#define SPI_INTREN_SLVCMDEN_SHIFT (5U) -#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) -#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) - -/* - * ENDINTEN (RW) - * - * Enable the End of SPI Transfer interrupt. - * Control whether interrupts are triggered when SPI transfers end. - * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - */ -#define SPI_INTREN_ENDINTEN_MASK (0x10U) -#define SPI_INTREN_ENDINTEN_SHIFT (4U) -#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) -#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) - -/* - * TXFIFOINTEN (RW) - * - * Enable the SPI Transmit FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - */ -#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) -#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) -#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) -#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) - -/* - * RXFIFOINTEN (RW) - * - * Enable the SPI Receive FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - */ -#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) -#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) -#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) -#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) - -/* - * TXFIFOURINTEN (RW) - * - * Enable the SPI Transmit FIFO Underrun interrupt. - * Control whether interrupts are triggered when the Transmit FIFO run out of data. - * (Slave mode only) - */ -#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) -#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) -#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) -#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) - -/* - * RXFIFOORINTEN (RW) - * - * Enable the SPI Receive FIFO Overrun interrupt. - * Control whether interrupts are triggered when the Receive FIFO overflows. - * (Slave mode only) - */ -#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) -#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) -#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) -#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) - -/* Bitfield definition for register: INTRST */ -/* - * SLVCMDINT (W1C) - * - * Slave Command Interrupt. - * This bit is set when Slave Command interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_SLVCMDINT_MASK (0x20U) -#define SPI_INTRST_SLVCMDINT_SHIFT (5U) -#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) -#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) - -/* - * ENDINT (W1C) - * - * End of SPI Transfer interrupt. - * This bit is set when End of SPI Transfer interrupts occur. - */ -#define SPI_INTRST_ENDINT_MASK (0x10U) -#define SPI_INTRST_ENDINT_SHIFT (4U) -#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) -#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) - -/* - * TXFIFOINT (W1C) - * - * TX FIFO Threshold interrupt. - * This bit is set when TX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_TXFIFOINT_MASK (0x8U) -#define SPI_INTRST_TXFIFOINT_SHIFT (3U) -#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) -#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) - -/* - * RXFIFOINT (W1C) - * - * RX FIFO Threshold interrupt. - * This bit is set when RX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_RXFIFOINT_MASK (0x4U) -#define SPI_INTRST_RXFIFOINT_SHIFT (2U) -#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) -#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) - -/* - * TXFIFOURINT (W1C) - * - * TX FIFO Underrun interrupt. - * This bit is set when TX FIFO Underrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) -#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) -#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) -#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) - -/* - * RXFIFOORINT (W1C) - * - * RX FIFO Overrun interrupt. - * This bit is set when RX FIFO Overrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) -#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) -#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) -#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) - -/* Bitfield definition for register: TIMING */ -/* - * CS2SCLK (RW) - * - * The minimum time between the edges of SPI CS and the edges of SCLK. - * SCLK_period * (CS2SCLK + 1) / 2 - */ -#define SPI_TIMING_CS2SCLK_MASK (0x3000U) -#define SPI_TIMING_CS2SCLK_SHIFT (12U) -#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) -#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) - -/* - * CSHT (RW) - * - * The minimum time that SPI CS should stay HIGH. - * SCLK_period * (CSHT + 1) / 2 - */ -#define SPI_TIMING_CSHT_MASK (0xF00U) -#define SPI_TIMING_CSHT_SHIFT (8U) -#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) -#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) - -/* - * SCLK_DIV (RW) - * - * The clock frequency ratio between the clock source and SPI interface SCLK. - * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) - * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - */ -#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) -#define SPI_TIMING_SCLK_DIV_SHIFT (0U) -#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) -#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) - -/* Bitfield definition for register: SLVST */ -/* - * UNDERRUN (W1C) - * - * Data underrun occurs in the last transaction - */ -#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) -#define SPI_SLVST_UNDERRUN_SHIFT (18U) -#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) -#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) - -/* - * OVERRUN (RW) - * - * Data overrun occurs in the last transaction - */ -#define SPI_SLVST_OVERRUN_MASK (0x20000UL) -#define SPI_SLVST_OVERRUN_SHIFT (17U) -#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) -#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) - -/* - * READY (RW) - * - * Set this bit to indicate that the ATCSPI200 is ready for data transaction. - * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - */ -#define SPI_SLVST_READY_MASK (0x10000UL) -#define SPI_SLVST_READY_SHIFT (16U) -#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) -#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) - -/* - * USR_STATUS (RW) - * - * User defined status flags - */ -#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) -#define SPI_SLVST_USR_STATUS_SHIFT (0U) -#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) -#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) - -/* Bitfield definition for register: SLVDATACNT */ -/* - * WCNT (RO) - * - * Slave transmitted data count - */ -#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) -#define SPI_SLVDATACNT_WCNT_SHIFT (16U) -#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) - -/* - * RCNT (RO) - * - * Slave received data count - */ -#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) -#define SPI_SLVDATACNT_RCNT_SHIFT (0U) -#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * SLAVE (RO) - * - * Support for SPI Slave mode - */ -#define SPI_CONFIG_SLAVE_MASK (0x4000U) -#define SPI_CONFIG_SLAVE_SHIFT (14U) -#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) - -/* - * QUADSPI (RO) - * - * Support for Quad I/O SPI - */ -#define SPI_CONFIG_QUADSPI_MASK (0x200U) -#define SPI_CONFIG_QUADSPI_SHIFT (9U) -#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) - -/* - * DUALSPI (RO) - * - * Support for Dual I/O SPI - */ -#define SPI_CONFIG_DUALSPI_MASK (0x100U) -#define SPI_CONFIG_DUALSPI_SHIFT (8U) -#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) - -/* - * TXFIFOSIZE (RO) - * - * Depth of TX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) -#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) -#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) - -/* - * RXFIFOSIZE (RO) - * - * Depth of RX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) -#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) -#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) - - - - -#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_synt_regs.h deleted file mode 100644 index 6e88bde3e4e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_synt_regs.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYNT_H -#define HPM_SYNT_H - -typedef struct { - __RW uint32_t GCR; /* 0x0: Global control register */ - __RW uint32_t RLD; /* 0x4: Counter reload register */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ - __R uint32_t CNT; /* 0xC: Counter */ - __R uint8_t RESERVED1[16]; /* 0x10 - 0x1F: Reserved */ - __RW uint32_t CMP[4]; /* 0x20 - 0x2C: Comparator */ -} SYNT_Type; - - -/* Bitfield definition for register: GCR */ -/* - * CRST (RW) - * - * 1- Reset counter - */ -#define SYNT_GCR_CRST_MASK (0x2U) -#define SYNT_GCR_CRST_SHIFT (1U) -#define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK) -#define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT) - -/* - * CEN (RW) - * - * 1- Enable counter - */ -#define SYNT_GCR_CEN_MASK (0x1U) -#define SYNT_GCR_CEN_SHIFT (0U) -#define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK) -#define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * RLD (RW) - * - * counter reload value - */ -#define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL) -#define SYNT_RLD_RLD_SHIFT (0U) -#define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) -#define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * CNT (RO) - * - * counter - */ -#define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL) -#define SYNT_CNT_CNT_SHIFT (0U) -#define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: CMP */ -/* - * CMP (RW) - * - * comparator value, the output will assert when counter count to this value - */ -#define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL) -#define SYNT_CMP_CMP_SHIFT (0U) -#define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK) -#define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT) - - - -/* CMP register group index macro definition */ -#define SYNT_CMP_0 (0UL) -#define SYNT_CMP_1 (1UL) -#define SYNT_CMP_2 (2UL) -#define SYNT_CMP_3 (3UL) - - -#endif /* HPM_SYNT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sysctl_regs.h deleted file mode 100644 index 3f8e145154b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_sysctl_regs.h +++ /dev/null @@ -1,1331 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYSCTL_H -#define HPM_SYSCTL_H - -typedef struct { - __RW uint32_t RESOURCE[350]; /* 0x0 - 0x574: Resource control register for cpu0 */ - __R uint8_t RESERVED0[648]; /* 0x578 - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: Goup setting */ - __RW uint32_t SET; /* 0x804: Goup setting */ - __RW uint32_t CLEAR; /* 0x808: Goup setting */ - __RW uint32_t TOGGLE; /* 0x80C: Goup setting */ - } GROUP0[3]; - __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x840: Goup setting */ - __RW uint32_t SET; /* 0x844: Goup setting */ - __RW uint32_t CLEAR; /* 0x848: Goup setting */ - __RW uint32_t TOGGLE; /* 0x84C: Goup setting */ - } GROUP1[3]; - __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ - __RW uint32_t SET; /* 0x904: Affiliate of Group */ - __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ - __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ - } AFFILIATE[2]; - struct { - __RW uint32_t VALUE; /* 0x920: Retention Control */ - __RW uint32_t SET; /* 0x924: Retention Control */ - __RW uint32_t CLEAR; /* 0x928: Retention Control */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ - } RETENTION[2]; - __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */ - struct { - __RW uint32_t STATUS; /* 0x1000: Power Setting */ - __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ - __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ - __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ - } POWER[4]; - __R uint8_t RESERVED4[960]; /* 0x1040 - 0x13FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ - __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ - __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ - __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ - } RESET[5]; - __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */ - __RW uint32_t CLOCK[67]; /* 0x1800 - 0x1908: Clock setting */ - __R uint8_t RESERVED6[756]; /* 0x190C - 0x1BFF: Reserved */ - __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */ - __RW uint32_t I2SCLK[4]; /* 0x1C10 - 0x1C1C: Clock setting */ - __R uint8_t RESERVED7[992]; /* 0x1C20 - 0x1FFF: Reserved */ - __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ - __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ - __R uint32_t CURRENT; /* 0x2404: Clock measure result */ - __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ - __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ - __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ - } MONITOR[4]; - __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ - struct { - __RW uint32_t LP; /* 0x2800: */ - __RW uint32_t LOCK; /* 0x2804: */ - __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: */ - __R uint32_t WAKEUP_STATUS[8]; /* 0x2840 - 0x285C: */ - __R uint8_t RESERVED0[32]; /* 0x2860 - 0x287F: Reserved */ - __RW uint32_t WAKEUP_ENABLE[8]; /* 0x2880 - 0x289C: */ - __R uint8_t RESERVED1[864]; /* 0x28A0 - 0x2BFF: Reserved */ - } CPU[2]; -} SYSCTL_Type; - - -/* Bitfield definition for register array: RESOURCE */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any nodes - * 1: any of nodes is changing status - */ -#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) -#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: no change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) -#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) - -/* - * MODE (RW) - * - * resource work mode - * 0:auto turn on and off as system required(recommended) - * 1:always on - * 2:always off - * 3:reserved - */ -#define SYSCTL_RESOURCE_MODE_MASK (0x3U) -#define SYSCTL_RESOURCE_MODE_SHIFT (0U) -#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) -#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) -#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) -#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) -#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK) -#define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK) -#define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK) -#define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400),each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: VALUE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0 - * bit0: cpu0 depends on logic node0 - * bit1: cpu0 depends on logic node1 - * bit2: cpu0 depends on logic node2 - * bit3: cpu0 depends on logic node3 - */ -#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) -#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: SET */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0 - * bit0: cpu0 depends on logic node0 - * bit1: cpu0 depends on logic node1 - * bit2: cpu0 depends on logic node2 - * bit3: cpu0 depends on logic node3 - */ -#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) -#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0 - * bit0: cpu0 depends on logic node0 - * bit1: cpu0 depends on logic node1 - * bit2: cpu0 depends on logic node2 - * bit3: cpu0 depends on logic node3 - */ -#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) -#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0 - * bit0: cpu0 depends on logic node0 - * bit1: cpu0 depends on logic node1 - * bit2: cpu0 depends on logic node2 - * bit3: cpu0 depends on logic node3 - */ -#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: VALUE */ -/* - * LINK (RW) - * - * retention setting while system sleep, each bit represents a resource - * bit0: soc_pow - * bit1: soc_rst - * bit2: cpu0_pow - * bit3: cpu0_rst - * bit4: cpu1_pow - * bit5: cpu1_rst - * bit6: con_pow - * bit7: con_rst - * bit8: vis_pow - * bit9: vis_rst - * bit10: xtal - * bit11: pll0 - * bit12: pll1 - * bit13: pll2 - * bit14: pll3 - * bit15: pll4 - */ -#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFFFUL) -#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) -#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: SET */ -/* - * LINK (RW) - * - * retention setting while system sleep - */ -#define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFFFUL) -#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) -#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: CLEAR */ -/* - * LINK (RW) - * - * retention setting while system sleep - */ -#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFFFUL) -#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) -#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: TOGGLE */ -/* - * LINK (RW) - * - * retention setting while system sleep - */ -#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFFFUL) -#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) -#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array POWER: STATUS */ -/* - * FLAG (RW) - * - * flag represents power cycle happened from last clear of this bit - * 0: power domain did not edurance power cycle since last clear of this bit - * 1: power domain enduranced power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) -#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) -#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) -#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup power cycle happened from last clear of this bit - * 0: power domain did not edurance wakeup power cycle since last clear of this bit - * 1: power domain enduranced wakeup power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) - -/* - * LF_DISABLE (RO) - * - * low fanout power switch disable - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) - -/* - * LF_ACK (RO) - * - * low fanout power switch feedback - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) -#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) -#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) - -/* Bitfield definition for register of struct array POWER: LF_WAIT */ -/* - * WAIT (RW) - * - * wait time for low fan out power switch turn on, default value is 255 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: OFF_WAIT */ -/* - * WAIT (RW) - * - * wait time for power switch turn off, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONTROL */ -/* - * FLAG (RW) - * - * flag represents reset happened from last clear of this bit - * 0: domain did not edurance reset cycle since last clear of this bit - * 1: domain enduranced reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) -#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup reset happened from last clear of this bit - * 0: domain did not edurance wakeup reset cycle since last clear of this bit - * 1: domain enduranced wakeup reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) - -/* - * HOLD (RW) - * - * perform reset and hold in reset, until ths bit cleared by software - * 0: reset is released for function - * 1: reset is assert and hold - */ -#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) -#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) -#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) -#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) - -/* - * RESET (RW) - * - * perform reset and release imediately - * 0: reset is released - * 1 reset is asserted and will release automatically - */ -#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) -#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) -#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) -#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONFIG */ -/* - * PRE_WAIT (RW) - * - * wait cycle numbers before assert reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) - -/* - * RSTCLK_NUM (RW) - * - * reset clock number(must be even number) - * 0: 0 cycle - * 1: 0 cycles - * 2: 2 cycles - * 3: 2 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) - -/* - * POST_WAIT (RW) - * - * time guard band for reset release - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: COUNTER */ -/* - * COUNTER (RW) - * - * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) -#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) -#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) -#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) - -/* Bitfield definition for register array: CLOCK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) - -/* - * MUX (RW) - * - * clock source selection - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll1_clk0 - * 3:pll1_clk1 - * 4:pll2_clk0 - * 5:pll2_clk1 - * 6:pll3_clk0 - * 7:pll4_clk0 - */ -#define SYSCTL_CLOCK_MUX_MASK (0xF00U) -#define SYSCTL_CLOCK_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) -#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by1 - * 1: divider by 2 - * 2 divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) -#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) - -/* Bitfield definition for register array: ADCCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) - -/* - * MUX (RW) - * - * clock source selection - * 0: ahb clock - * 1: adc clock 0 - * 2: adc clock 1 - * 3: adc clock 2 - */ -#define SYSCTL_ADCCLK_MUX_MASK (0x700U) -#define SYSCTL_ADCCLK_MUX_SHIFT (8U) -#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) -#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) - -/* Bitfield definition for register array: I2SCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) - -/* - * MUX (RW) - * - * clock source selection - * 0: ahb clock - * 1: i2s clock 0 - * 2: i2s clock 1 - * 3: i2s clock 2 - */ -#define SYSCTL_I2SCLK_MUX_MASK (0x700U) -#define SYSCTL_I2SCLK_MUX_SHIFT (8U) -#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) -#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) - -/* Bitfield definition for register: GLOBAL00 */ -/* - * PRESET (RW) - * - * global clock override request - * bit0: override to preset0 - * bit1: override to preset1 - * bit2: override to preset2 - * bit3: override to preset3 - */ -#define SYSCTL_GLOBAL00_PRESET_MASK (0xFU) -#define SYSCTL_GLOBAL00_PRESET_SHIFT (0U) -#define SYSCTL_GLOBAL00_PRESET_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_PRESET_SHIFT) & SYSCTL_GLOBAL00_PRESET_MASK) -#define SYSCTL_GLOBAL00_PRESET_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_PRESET_MASK) >> SYSCTL_GLOBAL00_PRESET_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * VALID (RW) - * - * result is ready for read - * 0: not ready - * 1: result is ready - */ -#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) -#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) -#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) -#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) - -/* - * DIV_BUSY (RO) - * - * divider is applying new setting - */ -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) - -/* - * OUTEN (RW) - * - * enable clock output - */ -#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) -#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) - -/* - * DIV (RW) - * - * output divider - */ -#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) -#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) -#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) - -/* - * HIGH (RW) - * - * clock frequency higher than upper limit - */ -#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) -#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock frequency lower than lower limit - */ -#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) -#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) -#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) -#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) - -/* - * START (RW) - * - * start measurement - */ -#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) -#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) -#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) -#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) - -/* - * MODE (RW) - * - * work mode, - * 0: register value will be compared to measurement - * 1: upper and lower value will be recordered in register - */ -#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) -#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) -#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) -#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) - -/* - * ACCURACY (RW) - * - * measurement accuracy, - * 0: resolution is 1kHz - * 1: resolution is 1Hz - */ -#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) - -/* - * REFERENCE (RW) - * - * reference clock selection, - * 0: 32k - * 1: 24M - */ -#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) - -/* - * SELECTION (RW) - * - * clock measurement selection - */ -#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) -#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CURRENT */ -/* - * FREQUENCY (RO) - * - * self updating measure result - */ -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ -/* - * FREQUENCY (RW) - * - * lower frequency - */ -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ -/* - * FREQUENCY (RW) - * - * upper frequency - */ -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array CPU: LP */ -/* - * WAKE_CNT (RW) - * - * CPU0 wake up counter, counter saturated at 255, write 0x00 to clear - */ -#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) -#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) -#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) -#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) - -/* - * HALT (RW) - * - * halt request for CPU0, - * 0: CPU0 will start to execute after reset or receive wakeup request - * 1: CPU0 will not start after reset, or wakeup after WFI - */ -#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) -#define SYSCTL_CPU_LP_HALT_SHIFT (16U) -#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) -#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) - -/* - * WAKE (RO) - * - * CPU0 is waking up - * 0: CPU0 wake up not asserted - * 1: CPU0 wake up asserted - */ -#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) -#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) -#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) - -/* - * EXEC (RO) - * - * CPU0 is executing - * 0: CPU0 is not executing - * 1: CPU0 is executing - */ -#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) -#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) -#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) - -/* - * WAKE_FLAG (RW) - * - * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit - * 0: CPU0 wakeup not happened - * 1: CPU0 wakeup happened - */ -#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) -#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) - -/* - * SLEEP_FLAG (RW) - * - * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) -#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) - -/* - * RESET_FLAG (RW) - * - * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) -#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) -#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) -#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) - -/* - * MODE (RW) - * - * Low power mode, system behavior after WFI - * 00: CPU clock stop after WFI - * 01: System enter low power mode after WFI - * 10: Keep running after WFI - * 11: reserved - */ -#define SYSCTL_CPU_LP_MODE_MASK (0x3U) -#define SYSCTL_CPU_LP_MODE_SHIFT (0U) -#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) -#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) - -/* Bitfield definition for register of struct array CPU: LOCK */ -/* - * GPR (RW) - * - * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - */ -#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) -#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) -#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) -#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) - -/* - * LOCK (RW) - * - * Lock bit for CPU_LOCK - */ -#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) -#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) -#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) -#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register of struct array CPU: GPR0 */ -/* - * GPR (RW) - * - * register for software to handle resume, can save resume address or status - */ -#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) -#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) -#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) - -/* Bitfield definition for register of struct array CPU: STATUS0 */ -/* - * STATUS (RO) - * - * IRQ values - */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register of struct array CPU: ENABLE0 */ -/* - * ENABLE (RW) - * - * IRQ wakeup enable - */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) - - - -/* RESOURCE register group index macro definition */ -#define SYSCTL_RESOURCE_CPU0_CORE (0UL) -#define SYSCTL_RESOURCE_CPU0_SUBSYS (1UL) -#define SYSCTL_RESOURCE_CPU1_CORE (8UL) -#define SYSCTL_RESOURCE_CPX1_SUBSYS (9UL) -#define SYSCTL_RESOURCE_POW_CON (21UL) -#define SYSCTL_RESOURCE_POW_VIS (22UL) -#define SYSCTL_RESOURCE_POW_CPU0 (23UL) -#define SYSCTL_RESOURCE_POW_CPU1 (24UL) -#define SYSCTL_RESOURCE_RST_SOC (25UL) -#define SYSCTL_RESOURCE_RST_CON (26UL) -#define SYSCTL_RESOURCE_RST_VIS (27UL) -#define SYSCTL_RESOURCE_RST_CPU0 (28UL) -#define SYSCTL_RESOURCE_RST_CPU1 (29UL) -#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0CLK0 (34UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK0 (36UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1CLK1 (37UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK0 (39UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2CLK1 (40UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL3CLK0 (42UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL4CLK0 (44UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR1 (67UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXI (68UL) -#define SYSCTL_RESOURCE_CLK_TOP_CONN (69UL) -#define SYSCTL_RESOURCE_CLK_TOP_VIS (70UL) -#define SYSCTL_RESOURCE_CLK_TOP_AHB (71UL) -#define SYSCTL_RESOURCE_CLK_TOP_FEMC (72UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (73UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (74UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR0 (75UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR1 (76UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR2 (77UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR3 (78UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR4 (79UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR5 (80UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR6 (81UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPTMR7 (82UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART0 (83UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART1 (84UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART2 (85UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART3 (86UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART4 (87UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART5 (88UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART6 (89UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART7 (90UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART8 (91UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART9 (92UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART10 (93UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART11 (94UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART12 (95UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART13 (96UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART14 (97UL) -#define SYSCTL_RESOURCE_CLK_TOP_UART15 (98UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (99UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (100UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (101UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (102UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (103UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (104UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (105UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (106UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (107UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (108UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (109UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (110UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTPC (111UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (112UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (113UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (114UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (115UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (116UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD2 (117UL) -#define SYSCTL_RESOURCE_CLK_TOP_LCDC (118UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAM0 (119UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAM1 (120UL) -#define SYSCTL_RESOURCE_CLK_TOP_ENET0 (121UL) -#define SYSCTL_RESOURCE_CLK_TOP_ENET1 (122UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (123UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTP1 (124UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL) -#define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (127UL) -#define SYSCTL_RESOURCE_CLK_TOP_NTMR1 (128UL) -#define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (129UL) -#define SYSCTL_RESOURCE_CLK_TOP_SDXC1 (130UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (192UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (193UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (194UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC3 (195UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (196UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (197UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S2 (198UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S3 (199UL) -#define SYSCTL_RESOURCE_AHBAPB_BUS (256UL) -#define SYSCTL_RESOURCE_AXI_BUS (257UL) -#define SYSCTL_RESOURCE_CONN_BUS (258UL) -#define SYSCTL_RESOURCE_VIS_BUS (259UL) -#define SYSCTL_RESOURCE_FEMC (260UL) -#define SYSCTL_RESOURCE_ROM (261UL) -#define SYSCTL_RESOURCE_LMM0 (262UL) -#define SYSCTL_RESOURCE_LMM1 (263UL) -#define SYSCTL_RESOURCE_MCHTMR0 (264UL) -#define SYSCTL_RESOURCE_MCHTMR1 (265UL) -#define SYSCTL_RESOURCE_AXI_SRAM0 (266UL) -#define SYSCTL_RESOURCE_AXI_SRAM1 (267UL) -#define SYSCTL_RESOURCE_XPI0 (268UL) -#define SYSCTL_RESOURCE_XPI1 (269UL) -#define SYSCTL_RESOURCE_SDP (270UL) -#define SYSCTL_RESOURCE_RNG (271UL) -#define SYSCTL_RESOURCE_KEYM (272UL) -#define SYSCTL_RESOURCE_HDMA (273UL) -#define SYSCTL_RESOURCE_XDMA (274UL) -#define SYSCTL_RESOURCE_GPIO (275UL) -#define SYSCTL_RESOURCE_MBX0 (276UL) -#define SYSCTL_RESOURCE_MBX1 (277UL) -#define SYSCTL_RESOURCE_WDG0 (278UL) -#define SYSCTL_RESOURCE_WDG1 (279UL) -#define SYSCTL_RESOURCE_WDG2 (280UL) -#define SYSCTL_RESOURCE_WDG3 (281UL) -#define SYSCTL_RESOURCE_GPTMR0 (282UL) -#define SYSCTL_RESOURCE_GPTMR1 (283UL) -#define SYSCTL_RESOURCE_GPTMR2 (284UL) -#define SYSCTL_RESOURCE_GPTMR3 (285UL) -#define SYSCTL_RESOURCE_GPTMR4 (286UL) -#define SYSCTL_RESOURCE_GPTMR5 (287UL) -#define SYSCTL_RESOURCE_GPTMR6 (288UL) -#define SYSCTL_RESOURCE_GPTMR7 (289UL) -#define SYSCTL_RESOURCE_UART0 (290UL) -#define SYSCTL_RESOURCE_UART1 (291UL) -#define SYSCTL_RESOURCE_UART2 (292UL) -#define SYSCTL_RESOURCE_UART3 (293UL) -#define SYSCTL_RESOURCE_UART4 (294UL) -#define SYSCTL_RESOURCE_UART5 (295UL) -#define SYSCTL_RESOURCE_UART6 (296UL) -#define SYSCTL_RESOURCE_UART7 (297UL) -#define SYSCTL_RESOURCE_UART8 (298UL) -#define SYSCTL_RESOURCE_UART9 (299UL) -#define SYSCTL_RESOURCE_UART10 (300UL) -#define SYSCTL_RESOURCE_UART11 (301UL) -#define SYSCTL_RESOURCE_UART12 (302UL) -#define SYSCTL_RESOURCE_UART13 (303UL) -#define SYSCTL_RESOURCE_UART14 (304UL) -#define SYSCTL_RESOURCE_UART15 (305UL) -#define SYSCTL_RESOURCE_I2C0 (306UL) -#define SYSCTL_RESOURCE_I2C1 (307UL) -#define SYSCTL_RESOURCE_I2C2 (308UL) -#define SYSCTL_RESOURCE_I2C3 (309UL) -#define SYSCTL_RESOURCE_SPI0 (310UL) -#define SYSCTL_RESOURCE_SPI1 (311UL) -#define SYSCTL_RESOURCE_SPI2 (312UL) -#define SYSCTL_RESOURCE_SPI3 (313UL) -#define SYSCTL_RESOURCE_CAN0 (314UL) -#define SYSCTL_RESOURCE_CAN1 (315UL) -#define SYSCTL_RESOURCE_CAN2 (316UL) -#define SYSCTL_RESOURCE_CAN3 (317UL) -#define SYSCTL_RESOURCE_PTPC (318UL) -#define SYSCTL_RESOURCE_ADC0 (319UL) -#define SYSCTL_RESOURCE_ADC1 (320UL) -#define SYSCTL_RESOURCE_ADC2 (321UL) -#define SYSCTL_RESOURCE_ADC3 (322UL) -#define SYSCTL_RESOURCE_ACMP (323UL) -#define SYSCTL_RESOURCE_I2S0 (324UL) -#define SYSCTL_RESOURCE_I2S1 (325UL) -#define SYSCTL_RESOURCE_I2S2 (326UL) -#define SYSCTL_RESOURCE_I2S3 (327UL) -#define SYSCTL_RESOURCE_PDM (328UL) -#define SYSCTL_RESOURCE_DAO (329UL) -#define SYSCTL_RESOURCE_SYNT (330UL) -#define SYSCTL_RESOURCE_MOT0 (331UL) -#define SYSCTL_RESOURCE_MOT1 (332UL) -#define SYSCTL_RESOURCE_MOT2 (333UL) -#define SYSCTL_RESOURCE_MOT3 (334UL) -#define SYSCTL_RESOURCE_LCDC (335UL) -#define SYSCTL_RESOURCE_CAM0 (336UL) -#define SYSCTL_RESOURCE_CAM1 (337UL) -#define SYSCTL_RESOURCE_JPEG (338UL) -#define SYSCTL_RESOURCE_PDMA (339UL) -#define SYSCTL_RESOURCE_ENET0 (340UL) -#define SYSCTL_RESOURCE_ENET1 (341UL) -#define SYSCTL_RESOURCE_NTMR0 (342UL) -#define SYSCTL_RESOURCE_NTMR1 (343UL) -#define SYSCTL_RESOURCE_SDXC0 (344UL) -#define SYSCTL_RESOURCE_SDXC1 (345UL) -#define SYSCTL_RESOURCE_USB0 (346UL) -#define SYSCTL_RESOURCE_USB1 (347UL) -#define SYSCTL_RESOURCE_REF0 (348UL) -#define SYSCTL_RESOURCE_REF1 (349UL) - -/* GROUP0 register group index macro definition */ -#define SYSCTL_GROUP0_0 (0UL) -#define SYSCTL_GROUP0_1 (1UL) -#define SYSCTL_GROUP0_2 (2UL) - -/* GROUP1 register group index macro definition */ -#define SYSCTL_GROUP1_0 (0UL) -#define SYSCTL_GROUP1_1 (1UL) -#define SYSCTL_GROUP1_2 (2UL) - -/* AFFILIATE register group index macro definition */ -#define SYSCTL_AFFILIATE_CPU0 (0UL) -#define SYSCTL_AFFILIATE_CPU1 (1UL) - -/* RETENTION register group index macro definition */ -#define SYSCTL_RETENTION_CPU0 (0UL) -#define SYSCTL_RETENTION_CPU1 (1UL) - -/* POWER register group index macro definition */ -#define SYSCTL_POWER_CPU0 (0UL) -#define SYSCTL_POWER_CPU1 (1UL) -#define SYSCTL_POWER_CON (2UL) -#define SYSCTL_POWER_VIS (3UL) - -/* RESET register group index macro definition */ -#define SYSCTL_RESET_SOC (0UL) -#define SYSCTL_RESET_CON (1UL) -#define SYSCTL_RESET_VIS (2UL) -#define SYSCTL_RESET_CPU0 (3UL) -#define SYSCTL_RESET_CPU1 (4UL) - -/* CLOCK register group index macro definition */ -#define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_MCHTMR0 (1UL) -#define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL) -#define SYSCTL_CLOCK_CLK_TOP_MCHTMR (3UL) -#define SYSCTL_CLOCK_CLK_TOP_AXI (4UL) -#define SYSCTL_CLOCK_CLK_TOP_CONN (5UL) -#define SYSCTL_CLOCK_CLK_TOP_VIS (6UL) -#define SYSCTL_CLOCK_CLK_TOP_AHB (7UL) -#define SYSCTL_CLOCK_CLK_TOP_FEMC (8UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI0 (9UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI1 (10UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR0 (11UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR1 (12UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR2 (13UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR3 (14UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR4 (15UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR5 (16UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR6 (17UL) -#define SYSCTL_CLOCK_CLK_TOP_GPTMR7 (18UL) -#define SYSCTL_CLOCK_CLK_TOP_UART0 (19UL) -#define SYSCTL_CLOCK_CLK_TOP_UART1 (20UL) -#define SYSCTL_CLOCK_CLK_TOP_UART2 (21UL) -#define SYSCTL_CLOCK_CLK_TOP_UART3 (22UL) -#define SYSCTL_CLOCK_CLK_TOP_UART4 (23UL) -#define SYSCTL_CLOCK_CLK_TOP_UART5 (24UL) -#define SYSCTL_CLOCK_CLK_TOP_UART6 (25UL) -#define SYSCTL_CLOCK_CLK_TOP_UART7 (26UL) -#define SYSCTL_CLOCK_CLK_TOP_UART8 (27UL) -#define SYSCTL_CLOCK_CLK_TOP_UART9 (28UL) -#define SYSCTL_CLOCK_CLK_TOP_UART10 (29UL) -#define SYSCTL_CLOCK_CLK_TOP_UART11 (30UL) -#define SYSCTL_CLOCK_CLK_TOP_UART12 (31UL) -#define SYSCTL_CLOCK_CLK_TOP_UART13 (32UL) -#define SYSCTL_CLOCK_CLK_TOP_UART14 (33UL) -#define SYSCTL_CLOCK_CLK_TOP_UART15 (34UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C0 (35UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C1 (36UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C2 (37UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C3 (38UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI0 (39UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI1 (40UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI2 (41UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI3 (42UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN0 (43UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN1 (44UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN2 (45UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN3 (46UL) -#define SYSCTL_CLOCK_CLK_TOP_PTPC (47UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA0 (48UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA1 (49UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA2 (50UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD0 (51UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD1 (52UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD2 (53UL) -#define SYSCTL_CLOCK_CLK_TOP_LCDC (54UL) -#define SYSCTL_CLOCK_CLK_TOP_CAM0 (55UL) -#define SYSCTL_CLOCK_CLK_TOP_CAM1 (56UL) -#define SYSCTL_CLOCK_CLK_TOP_ENET0 (57UL) -#define SYSCTL_CLOCK_CLK_TOP_ENET1 (58UL) -#define SYSCTL_CLOCK_CLK_TOP_PTP0 (59UL) -#define SYSCTL_CLOCK_CLK_TOP_PTP1 (60UL) -#define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL) -#define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL) -#define SYSCTL_CLOCK_CLK_TOP_NTMR0 (63UL) -#define SYSCTL_CLOCK_CLK_TOP_NTMR1 (64UL) -#define SYSCTL_CLOCK_CLK_TOP_SDXC0 (65UL) -#define SYSCTL_CLOCK_CLK_TOP_SDXC1 (66UL) - -/* ADCCLK register group index macro definition */ -#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL) - -/* I2SCLK register group index macro definition */ -#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL) - -/* MONITOR register group index macro definition */ -#define SYSCTL_MONITOR_SLICE0 (0UL) -#define SYSCTL_MONITOR_SLICE1 (1UL) -#define SYSCTL_MONITOR_SLICE2 (2UL) -#define SYSCTL_MONITOR_SLICE3 (3UL) - -/* GPR register group index macro definition */ -#define SYSCTL_CPU_GPR_GPR0 (0UL) -#define SYSCTL_CPU_GPR_GPR1 (1UL) -#define SYSCTL_CPU_GPR_GPR2 (2UL) -#define SYSCTL_CPU_GPR_GPR3 (3UL) -#define SYSCTL_CPU_GPR_GPR4 (4UL) -#define SYSCTL_CPU_GPR_GPR5 (5UL) -#define SYSCTL_CPU_GPR_GPR6 (6UL) -#define SYSCTL_CPU_GPR_GPR7 (7UL) -#define SYSCTL_CPU_GPR_GPR8 (8UL) -#define SYSCTL_CPU_GPR_GPR9 (9UL) -#define SYSCTL_CPU_GPR_GPR10 (10UL) -#define SYSCTL_CPU_GPR_GPR11 (11UL) -#define SYSCTL_CPU_GPR_GPR12 (12UL) -#define SYSCTL_CPU_GPR_GPR13 (13UL) - -/* WAKEUP_STATUS register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS6 (6UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS7 (7UL) - -/* WAKEUP_ENABLE register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE6 (6UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE7 (7UL) - -/* CPU register group index macro definition */ -#define SYSCTL_CPU_CPU0 (0UL) -#define SYSCTL_CPU_CPU1 (1UL) - - -#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_tamp_regs.h deleted file mode 100644 index d8e5c299fa3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_tamp_regs.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TAMP_H -#define HPM_TAMP_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Tamper n control */ - __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */ - __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - } TAMP[6]; - __R uint8_t RESERVED0[32]; /* 0x60 - 0x7F: Reserved */ - __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */ - __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */ -} TAMP_Type; - - -/* Bitfield definition for register of struct array TAMP: CONTROL */ -/* - * LOCK (RW) - * - * lock tamper setting - * 0: tamper setting can be changed - * 1: tamper setting will last to next battery domain power cycle - */ -#define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL) -#define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U) -#define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK) -#define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT) - -/* - * BYPASS (RW) - * - * bypass tamper violation filter - * 0: filter applied - * 1: filter not used - */ -#define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL) -#define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U) -#define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK) -#define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT) - -/* - * FILTER (RW) - * - * filter length - * 0: 1 cycle - * 1: 2 cycle - * 15: 65526 cycle - */ -#define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL) -#define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U) -#define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK) -#define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT) - -/* - * VALUE (RW) - * - * pin value for passive tamper - */ -#define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U) -#define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U) -#define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK) -#define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT) - -/* - * SPEED (RW) - * - * tamper speed selection, (2^SPEED) changes per second - * 0: 1 shift per second - * 1: 2 shifts per second - * . . . - * 15: 32768 shifts per second - */ -#define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U) -#define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U) -#define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK) -#define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT) - -/* - * RECOVER (RW) - * - * tamper will recover itself if tamper LFSR goes wrong - * 0: tamper will not recover - * 1: tamper will recover - */ -#define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U) -#define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U) -#define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK) -#define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT) - -/* - * ACTIVE (RW) - * - * select active or passive tamper - * 0: passive tamper - * 1: active tamper - */ -#define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U) -#define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U) -#define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK) -#define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable tamper - * 0: tamper disableed - * 1: tamper enabled - */ -#define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U) -#define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U) -#define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK) -#define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array TAMP: POLY */ -/* - * POLY (RW) - * - * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - */ -#define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_POLY_POLY_SHIFT (0U) -#define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK) -#define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array TAMP: LFSR */ -/* - * LFSR (WO) - * - * LFSR for active tamper, write only register, always read 0 - */ -#define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_LFSR_LFSR_SHIFT (0U) -#define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK) -#define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT) - -/* Bitfield definition for register: TAMP_FLAG */ -/* - * FLAG (RW) - * - * tamper flag, each bit represents one tamper pin, write 1 to clear the flag - * Note, clear can only be cleared when tamper disappeared - */ -#define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU) -#define TAMP_TAMP_FLAG_FLAG_SHIFT (0U) -#define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK) -#define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * LOCK (RW) - * - * lock bit for IRQ enable - * 0: enable bits can be changed - * 1: enable bits hold until next battery domain power cycle - */ -#define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL) -#define TAMP_IRQ_EN_LOCK_SHIFT (31U) -#define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK) -#define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable, each bit represents one tamper pin - * 0: interrupt disabled - * 1: interrupt enabled - */ -#define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU) -#define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U) -#define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK) -#define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT) - - - -/* TAMP register group index macro definition */ -#define TAMP_TAMP_TAMP0 (0UL) -#define TAMP_TAMP_TAMP1 (1UL) -#define TAMP_TAMP_TAMP2 (2UL) -#define TAMP_TAMP_TAMP3 (3UL) -#define TAMP_TAMP_TAMP4 (4UL) -#define TAMP_TAMP_TAMP5 (5UL) - - -#endif /* HPM_TAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_trgm_regs.h deleted file mode 100644 index 6f996212bb6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_trgm_regs.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGM_H -#define HPM_TRGM_H - -typedef struct { - __RW uint32_t FILTCFG[20]; /* 0x0 - 0x4C: Filter configure register */ - __R uint8_t RESERVED0[176]; /* 0x50 - 0xFF: Reserved */ - __RW uint32_t TRGOCFG[64]; /* 0x100 - 0x1FC: Trigger manager output configure register */ - __RW uint32_t DMACFG[4]; /* 0x200 - 0x20C: DMA request configure register */ - __R uint8_t RESERVED1[496]; /* 0x210 - 0x3FF: Reserved */ - __RW uint32_t GCR; /* 0x400: General Control Register */ -} TRGM_Type; - - -/* Bitfield definition for register array: FILTCFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) -#define TRGM_FILTCFG_OUTINV_SHIFT (16U) -#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) -#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stalbe low mode; - * 111-stable high mode - */ -#define TRGM_FILTCFG_MODE_MASK (0xE000U) -#define TRGM_FILTCFG_MODE_SHIFT (13U) -#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) -#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) -#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) -#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) -#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) - -/* - * FILTLEN (RW) - * - * This bitfields defines the filter counter length. - */ -#define TRGM_FILTCFG_FILTLEN_MASK (0xFFFU) -#define TRGM_FILTCFG_FILTLEN_SHIFT (0U) -#define TRGM_FILTCFG_FILTLEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT) & TRGM_FILTCFG_FILTLEN_MASK) -#define TRGM_FILTCFG_FILTLEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT) - -/* Bitfield definition for register array: TRGOCFG */ -/* - * OUTINV (RW) - * - * 1- Invert the output - */ -#define TRGM_TRGOCFG_OUTINV_MASK (0x100U) -#define TRGM_TRGOCFG_OUTINV_SHIFT (8U) -#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) -#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) - -/* - * FEDG2PEN (RW) - * - * 1- The selected input signal falling edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x80U) -#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (7U) -#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) -#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) - -/* - * REDG2PEN (RW) - * - * 1- The selected input signal rising edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_REDG2PEN_MASK (0x40U) -#define TRGM_TRGOCFG_REDG2PEN_SHIFT (6U) -#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) -#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) - -/* - * TRIGOSEL (RW) - * - * This bitfield selects one of the TRGM inputs as output. - */ -#define TRGM_TRGOCFG_TRIGOSEL_MASK (0x3FU) -#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) -#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) -#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) - -/* Bitfield definition for register array: DMACFG */ -/* - * DMASRCSEL (RW) - * - * This field selects one of the DMA requests as the DMA request output. - */ -#define TRGM_DMACFG_DMASRCSEL_MASK (0x1FU) -#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) -#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) -#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * TRGOPEN (RW) - * - * The bitfield enable the TRGM outputs. - */ -#define TRGM_GCR_TRGOPEN_MASK (0xFFFU) -#define TRGM_GCR_TRGOPEN_SHIFT (0U) -#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) -#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) - - - -/* FILTCFG register group index macro definition */ -#define TRGM_FILTCFG_PWM_IN0 (0UL) -#define TRGM_FILTCFG_PWM_IN1 (1UL) -#define TRGM_FILTCFG_PWM_IN2 (2UL) -#define TRGM_FILTCFG_PWM_IN3 (3UL) -#define TRGM_FILTCFG_PWM_IN4 (4UL) -#define TRGM_FILTCFG_PWM_IN5 (5UL) -#define TRGM_FILTCFG_PWM_IN6 (6UL) -#define TRGM_FILTCFG_PWM_IN7 (7UL) -#define TRGM_FILTCFG_TRGM_IN0 (8UL) -#define TRGM_FILTCFG_TRGM_IN1 (9UL) -#define TRGM_FILTCFG_TRGM_IN2 (10UL) -#define TRGM_FILTCFG_TRGM_IN3 (11UL) -#define TRGM_FILTCFG_TRGM_IN4 (12UL) -#define TRGM_FILTCFG_TRGM_IN5 (13UL) -#define TRGM_FILTCFG_TRGM_IN6 (14UL) -#define TRGM_FILTCFG_TRGM_IN7 (15UL) -#define TRGM_FILTCFG_TRGM_IN8 (16UL) -#define TRGM_FILTCFG_TRGM_IN9 (17UL) -#define TRGM_FILTCFG_TRGM_IN10 (18UL) -#define TRGM_FILTCFG_TRGM_IN11 (19UL) - -/* TRGOCFG register group index macro definition */ -#define TRGM_TRGOCFG_TRGM_OUT0 (0UL) -#define TRGM_TRGOCFG_TRGM_OUT1 (1UL) -#define TRGM_TRGOCFG_TRGM_OUT2 (2UL) -#define TRGM_TRGOCFG_TRGM_OUT3 (3UL) -#define TRGM_TRGOCFG_TRGM_OUT4 (4UL) -#define TRGM_TRGOCFG_TRGM_OUT5 (5UL) -#define TRGM_TRGOCFG_TRGM_OUT6 (6UL) -#define TRGM_TRGOCFG_TRGM_OUT7 (7UL) -#define TRGM_TRGOCFG_TRGM_OUT8 (8UL) -#define TRGM_TRGOCFG_TRGM_OUT9 (9UL) -#define TRGM_TRGOCFG_TRGM_OUT10 (10UL) -#define TRGM_TRGOCFG_TRGM_OUT11 (11UL) -#define TRGM_TRGOCFG_TRGM_OUTX0 (12UL) -#define TRGM_TRGOCFG_TRGM_OUTX1 (13UL) -#define TRGM_TRGOCFG_PWM_SYNCI (14UL) -#define TRGM_TRGOCFG_PWM_FRCI (15UL) -#define TRGM_TRGOCFG_PWM_FRCSYNCI (16UL) -#define TRGM_TRGOCFG_PWM_SHRLDSYNCI (17UL) -#define TRGM_TRGOCFG_PWM_FAULTI0 (18UL) -#define TRGM_TRGOCFG_PWM_FAULTI1 (19UL) -#define TRGM_TRGOCFG_PWM_FAULTI2 (20UL) -#define TRGM_TRGOCFG_PWM_FAULTI3 (21UL) -#define TRGM_TRGOCFG_PWM_IN8 (22UL) -#define TRGM_TRGOCFG_PWM_IN9 (23UL) -#define TRGM_TRGOCFG_PWM_IN10 (24UL) -#define TRGM_TRGOCFG_PWM_IN11 (25UL) -#define TRGM_TRGOCFG_PWM_IN12 (26UL) -#define TRGM_TRGOCFG_PWM_IN13 (27UL) -#define TRGM_TRGOCFG_PWM_IN14 (28UL) -#define TRGM_TRGOCFG_PWM_IN15 (29UL) -#define TRGM_TRGOCFG_PWM_IN16 (30UL) -#define TRGM_TRGOCFG_PWM_IN17 (31UL) -#define TRGM_TRGOCFG_PWM_IN18 (32UL) -#define TRGM_TRGOCFG_PWM_IN19 (33UL) -#define TRGM_TRGOCFG_PWM_IN20 (34UL) -#define TRGM_TRGOCFG_PWM_IN21 (35UL) -#define TRGM_TRGOCFG_PWM_IN22 (36UL) -#define TRGM_TRGOCFG_PWM_IN23 (37UL) -#define TRGM_TRGOCFG_QEI_A (38UL) -#define TRGM_TRGOCFG_QEI_B (39UL) -#define TRGM_TRGOCFG_QEI_Z (40UL) -#define TRGM_TRGOCFG_QEI_H (41UL) -#define TRGM_TRGOCFG_QEI_PAUSE (42UL) -#define TRGM_TRGOCFG_QEI_SNAPI (43UL) -#define TRGM_TRGOCFG_HALL_U (44UL) -#define TRGM_TRGOCFG_HALL_V (45UL) -#define TRGM_TRGOCFG_HALL_W (46UL) -#define TRGM_TRGOCFG_HALL_SNAPI (47UL) -#define TRGM_TRGOCFG_ADC0_STRGI (48UL) -#define TRGM_TRGOCFG_ADC1_STRGI (49UL) -#define TRGM_TRGOCFG_ADC2_STRGI (50UL) -#define TRGM_TRGOCFG_ADC3_STRGI (51UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) -#define TRGM_TRGOCFG_GPTMRA_SYNCI (55UL) -#define TRGM_TRGOCFG_GPTMRA_IN2 (56UL) -#define TRGM_TRGOCFG_GPTMRA_IN3 (57UL) -#define TRGM_TRGOCFG_GPTMRB_SYNCI (58UL) -#define TRGM_TRGOCFG_GPTMRB_IN2 (59UL) -#define TRGM_TRGOCFG_GPTMRB_IN3 (60UL) -#define TRGM_TRGOCFG_CMPX_WIN (61UL) -#define TRGM_TRGOCFG_CAN_PTPC0_CAP (62UL) -#define TRGM_TRGOCFG_CAN_PTPC1_CAP (63UL) - -/* DMACFG register group index macro definition */ -#define TRGM_DMACFG_0 (0UL) -#define TRGM_DMACFG_1 (1UL) -#define TRGM_DMACFG_2 (2UL) -#define TRGM_DMACFG_3 (3UL) - - -#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_uart_regs.h deleted file mode 100644 index 86d725ce3b3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_uart_regs.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_UART_H -#define HPM_UART_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ - union { - __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ - __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ - __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ - __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ - }; - union { - __R uint32_t IIR; /* 0x28: Interrupt Identification Register */ - __W uint32_t FCR; /* 0x28: FIFO Control Register */ - }; - __RW uint32_t LCR; /* 0x2C: Line Control Register */ - __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ - __R uint32_t LSR; /* 0x34: Line Status Register */ - __R uint32_t MSR; /* 0x38: Modem Status Register */ - __RW uint32_t GPR; /* 0x3C: GPR Register */ -} UART_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * The depth of RXFIFO and TXFIFO - * 0: 16-byte FIFO - * 1: 32-byte FIFO - * 2: 64-byte FIFO - * 3: 128-byte FIFO - */ -#define UART_CFG_FIFOSIZE_MASK (0x3U) -#define UART_CFG_FIFOSIZE_SHIFT (0U) -#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: OSCR */ -/* - * OSC (RW) - * - * Over-sample control - * The value must be an even number; any odd value - * writes to this field will be converted to an even value. - * OSC=0: reserved - * OSC<=8: The over-sample ratio is 8 - * 8 < OSC< 32: The over sample ratio is OSC - */ -#define UART_OSCR_OSC_MASK (0x1FU) -#define UART_OSCR_OSC_SHIFT (0U) -#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) -#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RBR (RO) - * - * Receive data read port - */ -#define UART_RBR_RBR_MASK (0xFFU) -#define UART_RBR_RBR_SHIFT (0U) -#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) - -/* Bitfield definition for register: THR */ -/* - * THR (WO) - * - * Transmit data write port - */ -#define UART_THR_THR_MASK (0xFFU) -#define UART_THR_THR_SHIFT (0U) -#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) -#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) - -/* Bitfield definition for register: DLL */ -/* - * DLL (RW) - * - * Least significant byte of the Divisor Latch - */ -#define UART_DLL_DLL_MASK (0xFFU) -#define UART_DLL_DLL_SHIFT (0U) -#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) -#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) - -/* Bitfield definition for register: IER */ -/* - * EMSI (RW) - * - * Enable modem status interrupt - * The interrupt asserts when the status of one of the - * following occurs: - * The status of modem_rin, modem_dcdn, - * modem_dsrn or modem_ctsn (If the auto-cts mode is - * disabled) has been changed. - * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), - * modem_ctsn would be used to control the transmitter. - */ -#define UART_IER_EMSI_MASK (0x8U) -#define UART_IER_EMSI_SHIFT (3U) -#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) -#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) - -/* - * ELSI (RW) - * - * Enable receiver line status interrupt - */ -#define UART_IER_ELSI_MASK (0x4U) -#define UART_IER_ELSI_SHIFT (2U) -#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) -#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) - -/* - * ETHEI (RW) - * - * Enable transmitter holding register interrupt - */ -#define UART_IER_ETHEI_MASK (0x2U) -#define UART_IER_ETHEI_SHIFT (1U) -#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) -#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) - -/* - * ERBI (RW) - * - * Enable received data available interrupt and the - * character timeout interrupt - * 0: Disable - * 1: Enable - */ -#define UART_IER_ERBI_MASK (0x1U) -#define UART_IER_ERBI_SHIFT (0U) -#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) -#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) - -/* Bitfield definition for register: DLM */ -/* - * DLM (RW) - * - * Most significant byte of the Divisor Latch - */ -#define UART_DLM_DLM_MASK (0xFFU) -#define UART_DLM_DLM_SHIFT (0U) -#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) -#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) - -/* Bitfield definition for register: IIR */ -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR_FIFOED_MASK (0xC0U) -#define UART_IIR_FIFOED_SHIFT (6U) -#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR_INTRID_MASK (0xFU) -#define UART_IIR_INTRID_SHIFT (0U) -#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) - -/* Bitfield definition for register: FCR */ -/* - * RFIFOT (WO) - * - * Receiver FIFO trigger level - */ -#define UART_FCR_RFIFOT_MASK (0xC0U) -#define UART_FCR_RFIFOT_SHIFT (6U) -#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) -#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) - -/* - * TFIFOT (WO) - * - * Transmitter FIFO trigger level - */ -#define UART_FCR_TFIFOT_MASK (0x30U) -#define UART_FCR_TFIFOT_SHIFT (4U) -#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) -#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) - -/* - * DMAE (WO) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCR_DMAE_MASK (0x8U) -#define UART_FCR_DMAE_SHIFT (3U) -#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) -#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_TFIFORST_MASK (0x4U) -#define UART_FCR_TFIFORST_SHIFT (2U) -#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) -#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_RFIFORST_MASK (0x2U) -#define UART_FCR_RFIFORST_SHIFT (1U) -#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) -#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) - -/* - * FIFOE (WO) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCR_FIFOE_MASK (0x1U) -#define UART_FCR_FIFOE_SHIFT (0U) -#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) -#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) - -/* Bitfield definition for register: LCR */ -/* - * DLAB (RW) - * - * Divisor latch access bit - */ -#define UART_LCR_DLAB_MASK (0x80U) -#define UART_LCR_DLAB_SHIFT (7U) -#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) -#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) - -/* - * BC (RW) - * - * Break control - */ -#define UART_LCR_BC_MASK (0x40U) -#define UART_LCR_BC_SHIFT (6U) -#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) -#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) - -/* - * SPS (RW) - * - * Stick parity - * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). - * 0: Disable the sticky bit parity. - */ -#define UART_LCR_SPS_MASK (0x20U) -#define UART_LCR_SPS_SHIFT (5U) -#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) -#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) - -/* - * EPS (RW) - * - * Even parity select - * 1: Even parity (an even number of logic-1 is in the data - * and parity bits) - * 0: Old parity. - */ -#define UART_LCR_EPS_MASK (0x10U) -#define UART_LCR_EPS_SHIFT (4U) -#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) -#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) - -/* - * PEN (RW) - * - * Parity enable - * When this bit is set, a parity bit is generated in - * transmitted data before the first STOP bit and the parity - * bit would be checked for the received data. - */ -#define UART_LCR_PEN_MASK (0x8U) -#define UART_LCR_PEN_SHIFT (3U) -#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) -#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) - -/* - * STB (RW) - * - * Number of STOP bits - * 0: 1 bits - * 1: The number of STOP bit is based on the WLS setting - * When WLS = 0, STOP bit is 1.5 bits - * When WLS = 1, 2, 3, STOP bit is 2 bits - */ -#define UART_LCR_STB_MASK (0x4U) -#define UART_LCR_STB_SHIFT (2U) -#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) -#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) - -/* - * WLS (RW) - * - * Word length setting - * 0: 5 bits - * 1: 6 bits - * 2: 7 bits - * 3: 8 bits - */ -#define UART_LCR_WLS_MASK (0x3U) -#define UART_LCR_WLS_SHIFT (0U) -#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) -#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) - -/* Bitfield definition for register: MCR */ -/* - * AFE (RW) - * - * Auto flow control enable - * 0: Disable - * 1: The auto-CTS and auto-RTS setting is based on the - * RTS bit setting: - * When RTS = 0, auto-CTS only - * When RTS = 1, auto-CTS and auto-RTS - */ -#define UART_MCR_AFE_MASK (0x20U) -#define UART_MCR_AFE_SHIFT (5U) -#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) -#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) - -/* - * LOOP (RW) - * - * Enable loopback mode - * 0: Disable - * 1: Enable - */ -#define UART_MCR_LOOP_MASK (0x10U) -#define UART_MCR_LOOP_SHIFT (4U) -#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) -#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) - -/* - * RTS (RW) - * - * Request to send - * This bit controls the modem_rtsn output. - * 0: The modem_rtsn output signal will be driven HIGH - * 1: The modem_rtsn output signal will be driven LOW - */ -#define UART_MCR_RTS_MASK (0x2U) -#define UART_MCR_RTS_SHIFT (1U) -#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) -#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) - -/* Bitfield definition for register: LSR */ -/* - * ERRF (RO) - * - * Error in RXFIFO - * In the FIFO mode, this bit is set when there is at least - * one parity error, framing error, or line break - * associated with data in the RXFIFO. It is cleared when - * this register is read and there is no more error for the - * rest of data in the RXFIFO. - */ -#define UART_LSR_ERRF_MASK (0x80U) -#define UART_LSR_ERRF_SHIFT (7U) -#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) - -/* - * TEMT (RO) - * - * Transmitter empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) and the Transmitter Shift Register (TSR) are - * both empty. Otherwise, it is zero. - */ -#define UART_LSR_TEMT_MASK (0x40U) -#define UART_LSR_TEMT_SHIFT (6U) -#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) - -/* - * THRE (RO) - * - * Transmitter Holding Register empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) is empty. Otherwise, it is zero. - * If the THRE interrupt is enabled, an interrupt is - * triggered when THRE becomes 1. - */ -#define UART_LSR_THRE_MASK (0x20U) -#define UART_LSR_THRE_SHIFT (5U) -#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) - -/* - * LBREAK (RO) - * - * Line break - * This bit is set when the uart_sin input signal was held - * LOWfor longer than the time for a full-word - * transmission. A full-word transmission is the - * transmission of the START, data, parity, and STOP - * bits. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the line break for - * the received data at the top of the RXFIFO. - */ -#define UART_LSR_LBREAK_MASK (0x10U) -#define UART_LSR_LBREAK_SHIFT (4U) -#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) - -/* - * FE (RO) - * - * Framing error - * This bit is set when the received STOP bit is not - * HIGH. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the framing error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_FE_MASK (0x8U) -#define UART_LSR_FE_SHIFT (3U) -#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) - -/* - * PE (RO) - * - * Parity error - * This bit is set when the received parity does not match - * with the parity selected in the LCR[5:4]. It is cleared - * when this register is read. - * In the FIFO mode, this bit indicates the parity error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_PE_MASK (0x4U) -#define UART_LSR_PE_SHIFT (2U) -#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) - -/* - * OE (RO) - * - * Overrun error - * This bit indicates that data in the Receiver Buffer - * Register (RBR) is overrun. - */ -#define UART_LSR_OE_MASK (0x2U) -#define UART_LSR_OE_SHIFT (1U) -#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) - -/* - * DR (RO) - * - * Data ready. - * This bit is set when there are incoming received data - * in the Receiver Buffer Register (RBR). It is cleared - * when all of the received data are read. - */ -#define UART_LSR_DR_MASK (0x1U) -#define UART_LSR_DR_SHIFT (0U) -#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) - -/* Bitfield definition for register: MSR */ -/* - * CTS (RO) - * - * Clear to send - * 0: The modem_ctsn input signal is HIGH. - * 1: The modem_ctsn input signal is LOW. - */ -#define UART_MSR_CTS_MASK (0x10U) -#define UART_MSR_CTS_SHIFT (4U) -#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) - -/* - * DCTS (RC) - * - * Delta clear to send - * This bit is set when the state of the modem_ctsn input - * signal has been changed since the last time this - * register is read. - */ -#define UART_MSR_DCTS_MASK (0x1U) -#define UART_MSR_DCTS_SHIFT (0U) -#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) - -/* Bitfield definition for register: GPR */ -/* - * DATA (RW) - * - * A one-byte storage register - */ -#define UART_GPR_DATA_MASK (0xFFU) -#define UART_GPR_DATA_SHIFT (0U) -#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) -#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) - - - - -#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_usb_regs.h deleted file mode 100644 index ff2a137f826..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_usb_regs.h +++ /dev/null @@ -1,2253 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_USB_H -#define HPM_USB_H - -typedef struct { - __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ - __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ - __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ - __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ - __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ - __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ - __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ - __RW uint32_t USBCMD; /* 0x140: USB Command Register */ - __RW uint32_t USBSTS; /* 0x144: USB Status Register */ - __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ - __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ - __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ - union { - __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ - __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ - }; - union { - __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ - __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ - }; - __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ - __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ - __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ - __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ - __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ - __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ - __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ - __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ - __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ - __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ - __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ - __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ - __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ - __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ - __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ - __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[8]; /* 0x1C0 - 0x1DC: Endpoint Control0 Register... Endpoint Control7 Register */ - __R uint8_t RESERVED7[32]; /* 0x1E0 - 0x1FF: Reserved */ - __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED8[12]; /* 0x204 - 0x20F: Reserved */ - __RW uint32_t PHY_CTRL0; /* 0x210: */ - __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED9[8]; /* 0x218 - 0x21F: Reserved */ - __RW uint32_t TOP_STATUS; /* 0x220: */ - __RW uint32_t PHY_STATUS; /* 0x224: */ -} USB_Type; - - -/* Bitfield definition for register: GPTIMER0LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) -#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER0CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD - */ -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software; - * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the - * counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: GPTIMER1LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) -#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER1CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - */ -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and - * automatically reload the counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: SBUSCFG */ -/* - * AHBBRST (RW) - * - * AHBBRST - * AHB master interface Burst configuration - * These bits control AHB master transfer type sequence (or priority). - * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. - * 000 - Incremental burst of unspecified length only - * 001 - INCR4 burst, then single transfer - * 010 - INCR8 burst, INCR4 burst, then single transfer - * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer - * 100 - Reserved, don't use - * 101 - INCR4 burst, then incremental burst of unspecified length - * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length - * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) -#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) - -/* Bitfield definition for register: USBCMD */ -/* - * ITC (RW) - * - * ITC - * Interrupt Threshold Control -Read/Write. - * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. - * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are - * shown below. - * Value Maximum Interrupt Interval - * 00000000 - Immediate (no threshold) - * 00000001 - 1 micro-frame - * 00000010 - 2 micro-frames - * 00000100 - 4 micro-frames - * 00001000 - 8 micro-frames - * 00010000 - 16 micro-frames - * 00100000 - 32 micro-frames - * 01000000 - 64 micro-frames - */ -#define USB_USBCMD_ITC_MASK (0xFF0000UL) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) -#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) - -/* - * FS_2 (RW) - * - * FS_2 - * Frame List Size - (Read/Write or Read Only). [host mode only] - * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. - * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. - * NOTE: This field is made up from USBCMD bits 15, 3 and 2. - * Value Meaning - * 0b000 - 1024 elements (4096 bytes) Default value - * 0b001 - 512 elements (2048 bytes) - * 0b010 - 256 elements (1024 bytes) - * 0b011 - 128 elements (512 bytes) - * 0b100 - 64 elements (256 bytes) - * 0b101 - 32 elements (128 bytes) - * 0b110 - 16 elements (64 bytes) - * 0b111 - 8 elements (32 bytes) - */ -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) - -/* - * ATDTW (RW) - * - * ATDTW - * Add dTD TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's - * linked list. This bit is set and cleared by software. - * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD - * to a primed endpoint may go unrecognized. - */ -#define USB_USBCMD_ATDTW_MASK (0x4000U) -#define USB_USBCMD_ATDTW_SHIFT (14U) -#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) - -/* - * SUTW (RW) - * - * SUTW - * Setup TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. - * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then - * there is a hazard when new setup data arrives while the DCD is copying the setup data payload - * from the QH for a previous setup packet. This bit is set and cleared by software. - * This bit would also be cleared by hardware when a hazard detected. - */ -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) - -/* - * ASPE (RW) - * - * ASPE - * Asynchronous Schedule Park Mode Enable - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. - * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. - * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - * NOTE: ASPE bit reset value: '0b' for OTG controller . - */ -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) - -/* - * ASP (RW) - * - * ASP - * Asynchronous Schedule Park Mode Count - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. - * It contains a count of the number of successive transactions the host controller is allowed to - * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. - * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. - * This field is set to 3h in all controller core. - */ -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) - -/* - * IAA (RW) - * - * IAA - * Interrupt on Async Advance Doorbell - Read/Write. - * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. - * When the host controller has evicted all appropriate cached schedule states, - * it sets the Interrupt on Async Advance status bit in the USBSTS register. - * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. - * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. - * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. - * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - */ -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) - -/* - * ASE (RW) - * - * ASE - * Asynchronous Schedule Enable - Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Asynchronous Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Asynchronous Schedule. - * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - */ -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) - -/* - * PSE (RW) - * - * PSE - * Periodic Schedule Enable- Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Periodic Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Periodic Schedule - * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - */ -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) - -/* - * FS_1 (RW) - * - * FS_1 - * See description at bit 15 - */ -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) - -/* - * RST (RW) - * - * RST - * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. - * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. - * Host operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. - * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. - * Attempting to reset an actively running host controller will result in undefined behavior. - * Device operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. - * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - */ -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) - -/* - * RS (RW) - * - * RS - * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. - * Host operation mode: - * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. - * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. - * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. - * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). - * Device operation mode: - * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. - * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. - * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) - -/* Bitfield definition for register: USBSTS */ -/* - * TI1 (RWC) - * - * TI1 - * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. - * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this - * bit will clear it. - */ -#define USB_USBSTS_TI1_MASK (0x2000000UL) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) -#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) - -/* - * TI0 (RWC) - * - * TI0 - * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. - * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this - * bit clears it. - */ -#define USB_USBSTS_TI0_MASK (0x1000000UL) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) - -/* - * UPI (RWC) - * - * USB Host Periodic Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. - * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero. - */ -#define USB_USBSTS_UPI_MASK (0x80000UL) -#define USB_USBSTS_UPI_SHIFT (19U) -#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) -#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) - -/* - * UAI (RWC) - * - * USB Host Asynchronous Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. - * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero - */ -#define USB_USBSTS_UAI_MASK (0x40000UL) -#define USB_USBSTS_UAI_SHIFT (18U) -#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) -#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) - -/* - * NAKI (RO) - * - * NAKI - * NAK Interrupt Bit--RO. - * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and - * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware - * when all Enabled TX/RX Endpoint NAK bits are cleared. - */ -#define USB_USBSTS_NAKI_MASK (0x10000UL) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) - -/* - * AS (RO) - * - * AS - * Asynchronous Schedule Status - Read Only. - * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. - * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) - -/* - * PS (RO) - * - * PS - * Periodic Schedule Status - Read Only. - * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. - * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) - -/* - * RCL (RO) - * - * RCL - * Reclamation - Read Only. - * This is a read-only status bit used to detect an empty asynchronous schedule. - * Only used in the host operation mode. - */ -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) - -/* - * HCH (RO) - * - * HCH - * HCHaIted - Read Only. - * This bit is a zero whenever the Run/Stop bit is a one. - * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - * either by software or by the Controller hardware (for example, an internal error). - * Only used in the host operation mode. - * Default value is '0b' for OTG core . - * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE - * register. - * NOTE: HCH bit reset value: '0b' for OTG controller core . - */ -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) - -/* - * SLI (RWC) - * - * SLI - * DCSuspend - R/WC. - * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. - * Only used in device operation mode. - */ -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) - -/* - * SRI (RWC) - * - * SRI - * SOF Received - R/WC. - * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. - * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. - * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. - * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. - * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. - * Software writes a 1 to this bit to clear it. - */ -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) - -/* - * URI (RWC) - * - * URI - * USB Reset Received - R/WC. - * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. - * Software can write a 1 to this bit to clear the USB Reset Received status bit. - * Only used in device operation mode. - */ -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) - -/* - * AAI (RWC) - * - * AAI - * Interrupt on Async Advance - R/WC. - * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule - * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. - * Only used in host operation mode. - */ -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) - -/* - * SEI (RWC) - * - * System Error – RWC. Default = 0b. - * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. - * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - */ -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) - -/* - * FRI (RWC) - * - * FRI - * Frame List Rollover - R/WC. - * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to - * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the - * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the - * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host - * Controller sets this bit to a one every time FHINDEX [12] toggles. - * Only used in host operation mode. - */ -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) - -/* - * PCI (RWC) - * - * PCI - * Port Change Detect - R/WC. - * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, - * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. - * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. - * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, - * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - */ -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) - -/* - * UEI (RWC) - * - * UEI - * USB Error Interrupt (USBERRINT) - R/WC. - * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. - * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - */ -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) - -/* - * UI (RWC) - * - * UI - * USB Interrupt (USBINT) - R/WC. - * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB - * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. - * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when - * the actual number of bytes received was less than the expected number of bytes. - */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) - -/* Bitfield definition for register: USBINTR */ -/* - * TIE1 (RW) - * - * TIE1 - * General Purpose Timer #1 Interrupt Enable - * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE1_MASK (0x2000000UL) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) -#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) - -/* - * TIE0 (RW) - * - * TIE0 - * General Purpose Timer #0 Interrupt Enable - * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE0_MASK (0x1000000UL) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) - -/* - * UPIE (RW) - * - * UPIE - * USB Host Periodic Interrupt Enable - * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UPIE_MASK (0x80000UL) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) - -/* - * UAIE (RW) - * - * UAIE - * USB Host Asynchronous Interrupt Enable - * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UAIE_MASK (0x40000UL) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) - -/* - * NAKE (RO) - * - * NAKE - * NAK Interrupt Enable - * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_NAKE_MASK (0x10000UL) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) - -/* - * SLE (RW) - * - * SLE - * Sleep Interrupt Enable - * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) - -/* - * SRE (RW) - * - * SRE - * SOF Received Interrupt Enable - * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) - -/* - * URE (RW) - * - * URE - * USB Reset Interrupt Enable - * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) - -/* - * AAE (RW) - * - * AAE - * Async Advance Interrupt Enable - * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) - -/* - * SEE (RW) - * - * SEE - * System Error Interrupt Enable - * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) - -/* - * FRE (RW) - * - * FRE - * Frame List Rollover Interrupt Enable - * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) - -/* - * PCE (RW) - * - * PCE - * Port Change Detect Interrupt Enable - * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) - -/* - * UEE (RWC) - * - * UEE - * USB Error Interrupt Enable - * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) - -/* - * UE (RW) - * - * UE - * USB Interrupt Enable - * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) - -/* Bitfield definition for register: FRINDEX */ -/* - * FRINDEX (RW) - * - * FRINDEX - * Frame Index. - * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. - * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. - * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. - * USBCMD [Frame List Size] Number Elements N - * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. - * In either mode bits 2:0 indicate the current microframe. - * The bit field values description below is represented as (Frame List Size) Number Elements N. - * 00000000000000 - (1024) 12 - * 00000000000001 - (512) 11 - * 00000000000010 - (256) 10 - * 00000000000011 - (128) 9 - * 00000000000100 - (64) 8 - * 00000000000101 - (32) 7 - * 00000000000110 - (16) 6 - * 00000000000111 - (8) 5 - */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) -#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) - -/* Bitfield definition for register: DEVICEADDR */ -/* - * USBADR (RW) - * - * USBADR - * Device Address. - * These bits correspond to the USB device address - */ -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) -#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) - -/* - * USBADRA (RW) - * - * USBADRA - * Device Address Advance. Default=0. - * When this bit is '0', any writes to USBADR are instantaneous. - * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. - * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. - * Hardware will automatically clear this bit on the following conditions: - * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). - * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). - * 3) Device Reset occurs (USBADR is reset to 0). - * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. - * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. - * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), - * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) - -/* Bitfield definition for register: PERIODICLISTBASE */ -/* - * BASEADR (RW) - * - * BASEADR - * Base Address (Low). - * These bits correspond to memory address signals [31:12], respectively. - * Only used by the host controller. - */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) -#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) - -/* Bitfield definition for register: ASYNCLISTADDR */ -/* - * ASYBASE (RW) - * - * ASYBASE - * Link Pointer Low (LPL). - * These bits correspond to memory address signals [31:5], respectively. This field may only reference a - * Queue Head (QH). - * Only used by the host controller. - */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) -#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) - -/* Bitfield definition for register: ENDPTLISTADDR */ -/* - * EPBASE (RW) - * - * EPBASE - * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. - * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) -#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) - -/* Bitfield definition for register: BURSTSIZE */ -/* - * TXPBURST (RW) - * - * TXPBURST - * Programmable TX Burst Size. - * Default value is determined by TXBURST bits in n_HWTXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from system - * memory to the USB bus. - */ -#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) - -/* - * RXPBURST (RW) - * - * RXPBURST - * Programmable RX Burst Size. - * Default value is determined by TXBURST bits in n_HWRXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from the - * USB bus to system memory. - */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) - -/* Bitfield definition for register: TXFILLTUNING */ -/* - * TXFIFOTHRES (RW) - * - * TXFIFOTHRES - * FIFO Burst Threshold. (Read/Write) - * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. - * The minimum value is 2 and this value should be a low as possible to maximize USB performance. - * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth - * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. - * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - */ -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* - * TXSCHHEALTH (RWC) - * - * TXSCHHEALTH - * Scheduler Health Counter. (Read/Write To Clear) - * Table continues on the next page - * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES - * before running out of time to send the packet before the next Start-Of-Frame. - * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. - * Writing to this register will clear the counter and this counter will max. at 31. - */ -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) - -/* - * TXSCHOH (RW) - * - * TXSCHOH - * Scheduler Overhead. (Read/Write) [Default = 0] - * This register adds an additional fixed offset to the schedule time estimator described above as Tff. - * As an approximation, the value chosen for this register should limit the number of back-off events captured - * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. - * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. - * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. - * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. - * Default value is '08h' for OTG controller core . - */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) - -/* Bitfield definition for register: ENDPTNAK */ -/* - * EPTN (RWC) - * - * EPTN - * TX Endpoint NAK - R/WC. - * Each TX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received IN token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) -#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) - -/* - * EPRN (RWC) - * - * EPRN - * RX Endpoint NAK - R/WC. - * Each RX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) - -/* Bitfield definition for register: ENDPTNAKEN */ -/* - * EPTNE (RW) - * - * EPTNE - * TX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the - * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) - -/* - * EPRNE (RW) - * - * EPRNE - * RX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the - * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) - -/* Bitfield definition for register: PORTSC1 */ -/* - * STS (RW) - * - * STS - * Serial Transceiver Select - * 1 Serial Interface Engine is selected - * 0 Parallel Interface signals is selected - * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. - * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - */ -#define USB_PORTSC1_STS_MASK (0x20000000UL) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) - -/* - * PTW (RW) - * - * PTW - * Parallel Transceiver Width - * This bit has no effect if serial interface engine is used. - * 0 - Select the 8-bit UTMI interface [60MHz] - * 1 - Select the 16-bit UTMI interface [30MHz] - */ -#define USB_PORTSC1_PTW_MASK (0x10000000UL) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) - -/* - * PSPD (RO) - * - * PSPD - * Port Speed - Read Only. - * This register field indicates the speed at which the port is operating. - * 00 - Full Speed - * 01 - Low Speed - * 10 - High Speed - * 11 - Undefined - */ -#define USB_PORTSC1_PSPD_MASK (0xC000000UL) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) - -/* - * PFSC (RW) - * - * PFSC - * Port Force Full Speed Connect - Read/Write. Default = 0b. - * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp - * sequence that allows the port to identify itself as High Speed. - * 0 - Normal operation - * 1 - Forced to full speed - */ -#define USB_PORTSC1_PFSC_MASK (0x1000000UL) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) - -/* - * PHCD (RW) - * - * PHCD - * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. - * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY - * clock. - * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. - * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD - * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend - * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the - * device controller driver must clear this bit. - * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put - * into suspend mode or when no downstream device is connected. Low power suspend is completely - * under the control of software. - * 0 - Enable PHY clock - * 1 - Disable PHY clock - */ -#define USB_PORTSC1_PHCD_MASK (0x800000UL) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) - -/* - * WKOC (RW) - * - * WKOC - * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. - * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero. - */ -#define USB_PORTSC1_WKOC_MASK (0x400000UL) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) - -/* - * WKDC (RW) - * - * WKDC - * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables - * the port to be sensitive to device disconnects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKDC_MASK (0x200000UL) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) - -/* - * WKCN (RW) - * - * WKCN - * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. - * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKCN_MASK (0x100000UL) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) - -/* - * PTC (RW) - * - * PTC - * Port Test Control - Read/Write. Default = 0000b. - * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. - * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. - * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. - * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. - * NOTE: Low speed operations are not supported as a peripheral device. - * Any other value than zero indicates that the port is operating in test mode. - * Value Specific Test - * 0000 - TEST_MODE_DISABLE - * 0001 - J_STATE - * 0010 - K_STATE - * 0011 - SE0 (host) / NAK (device) - * 0100 - Packet - * 0101 - FORCE_ENABLE_HS - * 0110 - FORCE_ENABLE_FS - * 0111 - FORCE_ENABLE_LS - * 1000-1111 - Reserved - */ -#define USB_PORTSC1_PTC_MASK (0xF0000UL) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) - -/* - * PP (RW) - * - * PP - * Port Power (PP)-Read/Write or Read Only. - * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: - * PPC - * PP Operation - * 0 - * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. - * 1 - * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). - * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. - * When an over-current condition is detected on a powered port and PPC is a one, - * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). - * This feature is implemented in all controller cores (PPC = 1). - */ -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) - -/* - * LS (RO) - * - * LS - * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal - * lines. - * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because - * the port controller state machine and the port routing manage the connection of LS and FS. - * In device mode, the use of linestate by the device controller driver is not necessary. - * The encoding of the bits are: - * Bits [11:10] Meaning - * 00 - SE0 - * 01 - K-state - * 10 - J-state - * 11 - Undefined - */ -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) - -/* - * HSP (RO) - * - * HSP - * High-Speed Port - Read Only. Default = 0b. - * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the - * host/device connected to the port is not in a high-speed mode. - * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - */ -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) - -/* - * PR (RW) - * - * PR - * Port Reset - Read/Write or Read Only. Default = 0b. - * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. - * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. - * This bit will automatically change to zero after the reset sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. - * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - */ -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) - -/* - * SUSP (RW) - * - * SUSP - * Suspend - Read/Write or Read Only. Default = 0b. - * 1=Port in suspend state. 0=Port not in suspend state. - * In Host Mode: Read/Write. - * Port Enabled Bit and Suspend bit of this register define the port states as follows: - * Bits [Port Enabled, Suspend] Port State - * 0x Disable - * 10 Enable - * 11 Suspend - * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. - * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. - * In the suspend state, the port is sensitive to resume detection. - * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. - * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. - * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: Read Only. - * In device mode this bit is a read only status bit. - */ -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) - -/* - * FPR (RW) - * - * FPR - * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. - * In Host Mode: - * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. - * This bit will automatically change to zero after the resume sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. - * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. - * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. - * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * This bit is not-EHCI compatible. - * In Device mode: - * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. - * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * The bit will be cleared when the device returns to normal operation. - * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - */ -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) - -/* - * OCC (RW) - * - * OCC - * Over-current Change-R/WC. Default=0. - * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - */ -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) - -/* - * OCA (RO) - * - * OCA - * Over-current Active-Read Only. Default 0. - * This bit will automatically transition from one to zero when the over current condition is removed. - * 0 - This port does not have an over-current condition. - * 1 - This port currently has an over-current condition - */ -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) - -/* - * PEC (RWC) - * - * PEC - * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. - * In Host Mode: - * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or - * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). - * Software clears this by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero. - * In Device mode: - * The device port is always enabled, so this bit is always '0b'. - */ -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) - -/* - * PE (RWC) - * - * PE - * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. - * In Host Mode: - * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. - * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. - * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. - * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * The device port is always enabled, so this bit is always '1b'. - */ -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) - -/* - * CSC (RWC) - * - * CSC - * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. - * In Host Mode: - * Indicates a change has occurred in the port's Current Connect Status. - * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. - * For example, the insertion status changes twice before system software has cleared the changed condition, - * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * This bit is undefined in device controller mode. - */ -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) - -/* - * CCS (RWC) - * - * CCS - * Current Connect Status-Read Only. - * In Host Mode: - * 1=Device is present on port. 0=No device is present. Default = 0. - * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * 1=Attached. 0=Not Attached. Default=0. - * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. - * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. - * It does not state the device being disconnected or Suspended. - */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) - -/* Bitfield definition for register: OTGSC */ -/* - * ASVIE (RW) - * - * ASVIE - * A Session Valid Interrupt Enable - Read/Write. - */ -#define USB_OTGSC_ASVIE_MASK (0x4000000UL) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) - -/* - * AVVIE (RW) - * - * AVVIE - * A VBus Valid Interrupt Enable - Read/Write. - * Setting this bit enables the A VBus valid interrupt. - */ -#define USB_OTGSC_AVVIE_MASK (0x2000000UL) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) - -/* - * IDIE (RW) - * - * IDIE - * USB ID Interrupt Enable - Read/Write. - * Setting this bit enables the USB ID interrupt. - */ -#define USB_OTGSC_IDIE_MASK (0x1000000UL) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) - -/* - * ASVIS (RWC) - * - * ASVIS - * A Session Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the A session valid threshold. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_ASVIS_MASK (0x40000UL) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) - -/* - * AVVIS (RWC) - * - * AVVIS - * A VBus Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_AVVIS_MASK (0x20000UL) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) - -/* - * IDIS (RWC) - * - * IDIS - * USB ID Interrupt Status - Read/Write. - * This bit is set when a change on the ID input has been detected. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_IDIS_MASK (0x10000UL) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) - -/* - * ASV (RO) - * - * ASV - * A Session Valid - Read Only. - * Indicates VBus is above the A session valid threshold. - */ -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) - -/* - * AVV (RO) - * - * AVV - * A VBus Valid - Read Only. - * Indicates VBus is above the A VBus valid threshold. - */ -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) - -/* - * ID (RO) - * - * ID - * USB ID - Read Only. - * 0 = A device, 1 = B device - */ -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) - -/* - * IDPU (RW) - * - * IDPU - * ID Pullup - Read/Write - * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input - * will not be sampled. - */ -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) - -/* - * VC (RW) - * - * VC - * VBUS Charge - Read/Write. - * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - */ -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) - -/* - * VD (RW) - * - * VD - * VBUS_Discharge - Read/Write. - * Setting this bit causes VBus to discharge through a resistor. - */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) - -/* Bitfield definition for register: USBMODE */ -/* - * SDIS (RW) - * - * SDIS - * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) - * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. - * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. - * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. - * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems - * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. - * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for - * the scheduler when using this feature. - * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - */ -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) -#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) - -/* - * SLOM (RW) - * - * SLOM - * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . - * 0 - Setup Lockouts On (default); - * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - */ -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) - -/* - * ES (RW) - * - * ES - * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the - * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected - * by the value of this bit because they are based upon the 32-bit word. - * Bit Meaning - * 0 - Little Endian [Default] - * 1 - Big Endian - */ -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) - -/* - * CM (RW) - * - * CM - * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only - * implementations. For those designs that contain both host & device capability, the controller defaults to - * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ - * device controllers, this register can only be written once after reset. If it is necessary to switch modes, - * software must reset the controller by writing to the RESET bit in the USBCMD register before - * reprogramming this register. - * For OTG controller core, reset value is '00b'. - * 00 - Idle [Default for combination host/device] - * 01 - Reserved - * 10 - Device Controller [Default for device only controller] - * 11 - Host Controller [Default for host only controller] - */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) - -/* Bitfield definition for register: ENDPTSETUPSTAT */ -/* - * ENDPTSETUPSTAT (RWC) - * - * ENDPTSETUPSTAT - * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. - * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. - * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. - * This register is only used in device mode. - */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* Bitfield definition for register: ENDPTPRIME */ -/* - * PETB (RWS) - * - * PETB - * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a - * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. - * Software should write a one to the corresponding bit when posting a new transfer descriptor to an - * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor - * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated - * endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) -#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) - -/* - * PERB (RWS) - * - * PERB - * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. - * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. - * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. - * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) - -/* Bitfield definition for register: ENDPTFLUSH */ -/* - * FETB (RWS) - * - * FETB - * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) -#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) - -/* - * FERB (RWS) - * - * FERB - * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) - -/* Bitfield definition for register: ENDPTSTAT */ -/* - * ETBR (RO) - * - * ETBR - * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. - * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. - * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. - * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. - * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. - * ETBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) - -/* - * ERBR (RO) - * - * ERBR - * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective - * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a - * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the - * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB - * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the - * USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations - * when a dTD is retired, and the dQH is updated. - * ERBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) - -/* Bitfield definition for register: ENDPTCOMPLETE */ -/* - * ETCE (RWC) - * - * ETCE - * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. - * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. - * ETCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) - -/* - * ERCE (RWC) - * - * ERCE - * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred - * and software should read the corresponding endpoint queue to determine the transfer status. If the - * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the - * USBINT . Writing one clears the corresponding bit in this register. - * ERCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) - -/* Bitfield definition for register array: ENDPTCTRL */ -/* - * TXE (RW) - * - * TXE - * TX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) -#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) - -/* - * TXR (WS) - * - * TXR - * TX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the Host and device. - */ -#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) - -/* - * TXT (RW) - * - * TXT - * TX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) - -/* - * TXS (RW) - * - * TXS - * TX Endpoint Stall - Read/Write - * 0 End Point OK - * 1 End Point Stalled - * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured - * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. - * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. - * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: - * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - */ -#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) - -/* - * RXE (RW) - * - * RXE - * RX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) - -/* - * RXR (WS) - * - * RXR - * RX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the host and device. - */ -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) - -/* - * RXT (RW) - * - * RXT - * RX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) - -/* - * RXS (RW) - * - * RXS - * RX Endpoint Stall - Read/Write - * 0 End Point OK. [Default] - * 1 End Point Stalled - * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control - * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit - * is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This - * control will continue to STALL until this bit is either cleared by software or automatically cleared as above - * for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the - * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it - * is unlikely the DCD software will observe this delay. However, should the DCD observe that the - * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit - * until it is set or until a new setup has been received by checking the associated endptsetupstat - * Bit. - */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) - -/* Bitfield definition for register: OTG_CTRL0 */ -/* - * OTG_WKDPDMCHG_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) - -/* - * AUTORESUME_EN (RW) - * - */ -#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) -#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) -#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) -#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) - -/* - * OTG_VBUS_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) - -/* - * OTG_ID_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) - -/* - * OTG_VBUS_SOURCE_SEL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) - -/* - * OTG_UTMI_SUSPENDM_SW (RW) - * - * default 0 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) - -/* - * OTG_UTMI_RESET_SW (RW) - * - * default 1 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) - -/* - * OTG_WAKEUP_INT_ENABLE (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) - -/* - * OTG_POWER_MASK (RW) - * - */ -#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) -#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) - -/* - * OTG_OVER_CUR_POL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) - -/* - * OTG_OVER_CUR_DIS (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) - -/* - * SER_MODE_SUSPEND_EN (RW) - * - * for naneng usbphy, only switch to serial mode when suspend - */ -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL0 */ -/* - * GPIO_ID_SEL_N (RW) - * - */ -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) - -/* - * ID_DIG_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) - -/* - * SESS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) - -/* - * VBUS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) - -/* - * ID_DIG_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) - -/* - * SESS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) - -/* - * VBUS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL1 */ -/* - * UTMI_CFG_RST_N (RW) - * - */ -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) - -/* - * UTMI_OTG_SUSPENDM (RW) - * - * OTG suspend, not utmi_suspendm - */ -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) - -/* Bitfield definition for register: TOP_STATUS */ -/* - * WAKEUP_INT_STATUS (RW) - * - */ -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * UTMI_CLK_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) -#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) - -/* - * LINE_STATE (RW) - * - */ -#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) -#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) -#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) -#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) - -/* - * HOST_DISCONNECT (RW) - * - */ -#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) -#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) - -/* - * ID_DIG (RW) - * - */ -#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) -#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) -#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) -#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) - -/* - * UTMI_SESS_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) -#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) - -/* - * VBUS_VALID (RW) - * - */ -#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) -#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) -#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) -#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) - - - -/* ENDPTCTRL register group index macro definition */ -#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) -#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) -#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) -#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) -#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) -#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) -#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) -#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) - - -#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_vad_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_vad_regs.h deleted file mode 100644 index 8aad52aa969..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_vad_regs.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_VAD_H -#define HPM_VAD_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t FILTCTRL; /* 0x4: Filter Control Register */ - __RW uint32_t DEC_CTRL0; /* 0x8: Decision Control Register 0 */ - __RW uint32_t DEC_CTRL1; /* 0xC: Decision Control Register 1 */ - __RW uint32_t DEC_CTRL2; /* 0x10: Decision Control Register 2 */ - __R uint8_t RESERVED0[4]; /* 0x14 - 0x17: Reserved */ - __RW uint32_t ST; /* 0x18: Status */ - __RW uint32_t OFIFO; /* 0x1C: Out FIFO */ - __RW uint32_t RUN; /* 0x20: Run Command Register */ - __RW uint32_t OFIFO_CTRL; /* 0x24: Out FIFO Control Register */ - __RW uint32_t CIC_CFG; /* 0x28: CIC Configuration Register */ - __R uint8_t RESERVED1[116]; /* 0x2C - 0x9F: Reserved */ - __R uint32_t COEF[1]; /* 0xA0: Short Time Energy Register */ -} VAD_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * CAPT_DLY (RW) - * - * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - */ -#define VAD_CTRL_CAPT_DLY_MASK (0xF000000UL) -#define VAD_CTRL_CAPT_DLY_SHIFT (24U) -#define VAD_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << VAD_CTRL_CAPT_DLY_SHIFT) & VAD_CTRL_CAPT_DLY_MASK) -#define VAD_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & VAD_CTRL_CAPT_DLY_MASK) >> VAD_CTRL_CAPT_DLY_SHIFT) - -/* - * PDM_CLK_HFDIV (RW) - * - * The clock divider will work at least 4. - * 0: div-by-2, - * 1: div-by-4 - * . . . - * n: div-by-2*(n+1) - */ -#define VAD_CTRL_PDM_CLK_HFDIV_MASK (0xF00000UL) -#define VAD_CTRL_PDM_CLK_HFDIV_SHIFT (20U) -#define VAD_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_HFDIV_SHIFT) & VAD_CTRL_PDM_CLK_HFDIV_MASK) -#define VAD_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_HFDIV_MASK) >> VAD_CTRL_PDM_CLK_HFDIV_SHIFT) - -/* - * VAD_IE (RW) - * - * VAD event interrupt enable - */ -#define VAD_CTRL_VAD_IE_MASK (0x40000UL) -#define VAD_CTRL_VAD_IE_SHIFT (18U) -#define VAD_CTRL_VAD_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_VAD_IE_SHIFT) & VAD_CTRL_VAD_IE_MASK) -#define VAD_CTRL_VAD_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_VAD_IE_MASK) >> VAD_CTRL_VAD_IE_SHIFT) - -/* - * OFIFO_AV_IE (RW) - * - * OFIFO data available interrupt enable - */ -#define VAD_CTRL_OFIFO_AV_IE_MASK (0x20000UL) -#define VAD_CTRL_OFIFO_AV_IE_SHIFT (17U) -#define VAD_CTRL_OFIFO_AV_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_AV_IE_SHIFT) & VAD_CTRL_OFIFO_AV_IE_MASK) -#define VAD_CTRL_OFIFO_AV_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_AV_IE_MASK) >> VAD_CTRL_OFIFO_AV_IE_SHIFT) - -/* - * MEMBUF_EMPTY_IE (RW) - * - * Buf empty interrupt enable - */ -#define VAD_CTRL_MEMBUF_EMPTY_IE_MASK (0x10000UL) -#define VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT (16U) -#define VAD_CTRL_MEMBUF_EMPTY_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) -#define VAD_CTRL_MEMBUF_EMPTY_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) >> VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) - -/* - * OFIFO_OVFL_ERR_IE (RW) - * - * OFIFO overflow error interrupt enable - */ -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x8000U) -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (15U) -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) - -/* - * IIR_OVLD_ERR_IE (RW) - * - * IIR overload error interrupt enable - */ -#define VAD_CTRL_IIR_OVLD_ERR_IE_MASK (0x4000U) -#define VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT (14U) -#define VAD_CTRL_IIR_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) -#define VAD_CTRL_IIR_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) >> VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) - -/* - * IIR_OVFL_ERR_IE (RW) - * - * IIR overflow error interrupt enable - */ -#define VAD_CTRL_IIR_OVFL_ERR_IE_MASK (0x2000U) -#define VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT (13U) -#define VAD_CTRL_IIR_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) -#define VAD_CTRL_IIR_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) >> VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) - -/* - * CIC_OVLD_ERR_IE (RW) - * - * CIC overload Interrupt Enable - */ -#define VAD_CTRL_CIC_OVLD_ERR_IE_MASK (0x1000U) -#define VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT (12U) -#define VAD_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) -#define VAD_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) >> VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) - -/* - * CIC_SAT_ERR_IE (RW) - * - * CIC saturation Interrupt Enable - */ -#define VAD_CTRL_CIC_SAT_ERR_IE_MASK (0x800U) -#define VAD_CTRL_CIC_SAT_ERR_IE_SHIFT (11U) -#define VAD_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) -#define VAD_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) >> VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) - -/* - * MEMBUF_DISABLE (RW) - * - * asserted to disable membuf - */ -#define VAD_CTRL_MEMBUF_DISABLE_MASK (0x200U) -#define VAD_CTRL_MEMBUF_DISABLE_SHIFT (9U) -#define VAD_CTRL_MEMBUF_DISABLE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_DISABLE_SHIFT) & VAD_CTRL_MEMBUF_DISABLE_MASK) -#define VAD_CTRL_MEMBUF_DISABLE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_DISABLE_MASK) >> VAD_CTRL_MEMBUF_DISABLE_SHIFT) - -/* - * FIFO_THRSH (RW) - * - * OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - */ -#define VAD_CTRL_FIFO_THRSH_MASK (0x1E0U) -#define VAD_CTRL_FIFO_THRSH_SHIFT (5U) -#define VAD_CTRL_FIFO_THRSH_SET(x) (((uint32_t)(x) << VAD_CTRL_FIFO_THRSH_SHIFT) & VAD_CTRL_FIFO_THRSH_MASK) -#define VAD_CTRL_FIFO_THRSH_GET(x) (((uint32_t)(x) & VAD_CTRL_FIFO_THRSH_MASK) >> VAD_CTRL_FIFO_THRSH_SHIFT) - -/* - * PDM_CLK_DIV_BYPASS (RW) - * - * asserted to bypass the pdm clock divider - */ -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x10U) -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (4U) -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) - -/* - * PDM_CLK_OE (RW) - * - * pdm_clk_output_en - */ -#define VAD_CTRL_PDM_CLK_OE_MASK (0x8U) -#define VAD_CTRL_PDM_CLK_OE_SHIFT (3U) -#define VAD_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_OE_SHIFT) & VAD_CTRL_PDM_CLK_OE_MASK) -#define VAD_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_OE_MASK) >> VAD_CTRL_PDM_CLK_OE_SHIFT) - -/* - * CH_POL (RW) - * - * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - */ -#define VAD_CTRL_CH_POL_MASK (0x6U) -#define VAD_CTRL_CH_POL_SHIFT (1U) -#define VAD_CTRL_CH_POL_SET(x) (((uint32_t)(x) << VAD_CTRL_CH_POL_SHIFT) & VAD_CTRL_CH_POL_MASK) -#define VAD_CTRL_CH_POL_GET(x) (((uint32_t)(x) & VAD_CTRL_CH_POL_MASK) >> VAD_CTRL_CH_POL_SHIFT) - -/* - * CHNUM (RW) - * - * the number of channels to be stored in buffer. Asserted to enable 2 channels. - */ -#define VAD_CTRL_CHNUM_MASK (0x1U) -#define VAD_CTRL_CHNUM_SHIFT (0U) -#define VAD_CTRL_CHNUM_SET(x) (((uint32_t)(x) << VAD_CTRL_CHNUM_SHIFT) & VAD_CTRL_CHNUM_MASK) -#define VAD_CTRL_CHNUM_GET(x) (((uint32_t)(x) & VAD_CTRL_CHNUM_MASK) >> VAD_CTRL_CHNUM_SHIFT) - -/* Bitfield definition for register: FILTCTRL */ -/* - * DECRATIO (RW) - * - * the decimation ratio of iir after CIC -1 - * 2: means dec-by-3 - */ -#define VAD_FILTCTRL_DECRATIO_MASK (0x700U) -#define VAD_FILTCTRL_DECRATIO_SHIFT (8U) -#define VAD_FILTCTRL_DECRATIO_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_DECRATIO_SHIFT) & VAD_FILTCTRL_DECRATIO_MASK) -#define VAD_FILTCTRL_DECRATIO_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_DECRATIO_MASK) >> VAD_FILTCTRL_DECRATIO_SHIFT) - -/* - * IIR_SLOT_EN (RW) - * - * IIR slot enable - */ -#define VAD_FILTCTRL_IIR_SLOT_EN_MASK (0xFFU) -#define VAD_FILTCTRL_IIR_SLOT_EN_SHIFT (0U) -#define VAD_FILTCTRL_IIR_SLOT_EN_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) -#define VAD_FILTCTRL_IIR_SLOT_EN_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) >> VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) - -/* Bitfield definition for register: DEC_CTRL0 */ -/* - * NOISE_TOL (RW) - * - * the value of amplitude for noise determination when calculationg ZCR - */ -#define VAD_DEC_CTRL0_NOISE_TOL_MASK (0xFFFF0000UL) -#define VAD_DEC_CTRL0_NOISE_TOL_SHIFT (16U) -#define VAD_DEC_CTRL0_NOISE_TOL_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_NOISE_TOL_SHIFT) & VAD_DEC_CTRL0_NOISE_TOL_MASK) -#define VAD_DEC_CTRL0_NOISE_TOL_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_NOISE_TOL_MASK) >> VAD_DEC_CTRL0_NOISE_TOL_SHIFT) - -/* - * BLK_CFG (RW) - * - * asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - */ -#define VAD_DEC_CTRL0_BLK_CFG_MASK (0x200U) -#define VAD_DEC_CTRL0_BLK_CFG_SHIFT (9U) -#define VAD_DEC_CTRL0_BLK_CFG_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_BLK_CFG_SHIFT) & VAD_DEC_CTRL0_BLK_CFG_MASK) -#define VAD_DEC_CTRL0_BLK_CFG_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_BLK_CFG_MASK) >> VAD_DEC_CTRL0_BLK_CFG_SHIFT) - -/* - * SUBBLK_LEN (RW) - * - * length of sub-block - */ -#define VAD_DEC_CTRL0_SUBBLK_LEN_MASK (0x1FFU) -#define VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT (0U) -#define VAD_DEC_CTRL0_SUBBLK_LEN_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) -#define VAD_DEC_CTRL0_SUBBLK_LEN_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) >> VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) - -/* Bitfield definition for register: DEC_CTRL1 */ -/* - * ZCR_HIGH (RW) - * - * ZCR high limit - */ -#define VAD_DEC_CTRL1_ZCR_HIGH_MASK (0x3FF800UL) -#define VAD_DEC_CTRL1_ZCR_HIGH_SHIFT (11U) -#define VAD_DEC_CTRL1_ZCR_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) -#define VAD_DEC_CTRL1_ZCR_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) >> VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) - -/* - * ZCR_LOW (RW) - * - * ZCR low limit - */ -#define VAD_DEC_CTRL1_ZCR_LOW_MASK (0x7FFU) -#define VAD_DEC_CTRL1_ZCR_LOW_SHIFT (0U) -#define VAD_DEC_CTRL1_ZCR_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_LOW_SHIFT) & VAD_DEC_CTRL1_ZCR_LOW_MASK) -#define VAD_DEC_CTRL1_ZCR_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_LOW_MASK) >> VAD_DEC_CTRL1_ZCR_LOW_SHIFT) - -/* Bitfield definition for register: DEC_CTRL2 */ -/* - * AMP_HIGH (RW) - * - * amplitude high limit - */ -#define VAD_DEC_CTRL2_AMP_HIGH_MASK (0xFFFF0000UL) -#define VAD_DEC_CTRL2_AMP_HIGH_SHIFT (16U) -#define VAD_DEC_CTRL2_AMP_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_HIGH_SHIFT) & VAD_DEC_CTRL2_AMP_HIGH_MASK) -#define VAD_DEC_CTRL2_AMP_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_HIGH_MASK) >> VAD_DEC_CTRL2_AMP_HIGH_SHIFT) - -/* - * AMP_LOW (RW) - * - * amplitude low limit - */ -#define VAD_DEC_CTRL2_AMP_LOW_MASK (0xFFFFU) -#define VAD_DEC_CTRL2_AMP_LOW_SHIFT (0U) -#define VAD_DEC_CTRL2_AMP_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_LOW_SHIFT) & VAD_DEC_CTRL2_AMP_LOW_MASK) -#define VAD_DEC_CTRL2_AMP_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_LOW_MASK) >> VAD_DEC_CTRL2_AMP_LOW_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * VAD (W1C) - * - * VAD event found - */ -#define VAD_ST_VAD_MASK (0x80U) -#define VAD_ST_VAD_SHIFT (7U) -#define VAD_ST_VAD_SET(x) (((uint32_t)(x) << VAD_ST_VAD_SHIFT) & VAD_ST_VAD_MASK) -#define VAD_ST_VAD_GET(x) (((uint32_t)(x) & VAD_ST_VAD_MASK) >> VAD_ST_VAD_SHIFT) - -/* - * OFIFO_AV (RO) - * - * OFIFO data available - */ -#define VAD_ST_OFIFO_AV_MASK (0x40U) -#define VAD_ST_OFIFO_AV_SHIFT (6U) -#define VAD_ST_OFIFO_AV_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_AV_MASK) >> VAD_ST_OFIFO_AV_SHIFT) - -/* - * MEMBUF_EMPTY (W1C) - * - * Buf empty - */ -#define VAD_ST_MEMBUF_EMPTY_MASK (0x20U) -#define VAD_ST_MEMBUF_EMPTY_SHIFT (5U) -#define VAD_ST_MEMBUF_EMPTY_SET(x) (((uint32_t)(x) << VAD_ST_MEMBUF_EMPTY_SHIFT) & VAD_ST_MEMBUF_EMPTY_MASK) -#define VAD_ST_MEMBUF_EMPTY_GET(x) (((uint32_t)(x) & VAD_ST_MEMBUF_EMPTY_MASK) >> VAD_ST_MEMBUF_EMPTY_SHIFT) - -/* - * OFIFO_OVFL (W1C) - * - * OFIFO overflow - */ -#define VAD_ST_OFIFO_OVFL_MASK (0x10U) -#define VAD_ST_OFIFO_OVFL_SHIFT (4U) -#define VAD_ST_OFIFO_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_OFIFO_OVFL_SHIFT) & VAD_ST_OFIFO_OVFL_MASK) -#define VAD_ST_OFIFO_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_OVFL_MASK) >> VAD_ST_OFIFO_OVFL_SHIFT) - -/* - * IIR_OVLD (W1C) - * - * IIR overloading - */ -#define VAD_ST_IIR_OVLD_MASK (0x8U) -#define VAD_ST_IIR_OVLD_SHIFT (3U) -#define VAD_ST_IIR_OVLD_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVLD_SHIFT) & VAD_ST_IIR_OVLD_MASK) -#define VAD_ST_IIR_OVLD_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVLD_MASK) >> VAD_ST_IIR_OVLD_SHIFT) - -/* - * IIR_OVFL (W1C) - * - * IIR oberflow - */ -#define VAD_ST_IIR_OVFL_MASK (0x4U) -#define VAD_ST_IIR_OVFL_SHIFT (2U) -#define VAD_ST_IIR_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVFL_SHIFT) & VAD_ST_IIR_OVFL_MASK) -#define VAD_ST_IIR_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVFL_MASK) >> VAD_ST_IIR_OVFL_SHIFT) - -/* - * CIC_OVLD_ERR (W1C) - * - * CIC overload - */ -#define VAD_ST_CIC_OVLD_ERR_MASK (0x2U) -#define VAD_ST_CIC_OVLD_ERR_SHIFT (1U) -#define VAD_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_OVLD_ERR_SHIFT) & VAD_ST_CIC_OVLD_ERR_MASK) -#define VAD_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_OVLD_ERR_MASK) >> VAD_ST_CIC_OVLD_ERR_SHIFT) - -/* - * CIC_SAT_ERR (W1C) - * - * CIC saturation - */ -#define VAD_ST_CIC_SAT_ERR_MASK (0x1U) -#define VAD_ST_CIC_SAT_ERR_SHIFT (0U) -#define VAD_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_SAT_ERR_SHIFT) & VAD_ST_CIC_SAT_ERR_MASK) -#define VAD_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_SAT_ERR_MASK) >> VAD_ST_CIC_SAT_ERR_SHIFT) - -/* Bitfield definition for register: OFIFO */ -/* - * D (RW) - * - * The PCM data. - * When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). - * When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - */ -#define VAD_OFIFO_D_MASK (0xFFFFFFFFUL) -#define VAD_OFIFO_D_SHIFT (0U) -#define VAD_OFIFO_D_SET(x) (((uint32_t)(x) << VAD_OFIFO_D_SHIFT) & VAD_OFIFO_D_MASK) -#define VAD_OFIFO_D_GET(x) (((uint32_t)(x) & VAD_OFIFO_D_MASK) >> VAD_OFIFO_D_SHIFT) - -/* Bitfield definition for register: RUN */ -/* - * SFTRST (RW) - * - * software reset. Self-clear - */ -#define VAD_RUN_SFTRST_MASK (0x2U) -#define VAD_RUN_SFTRST_SHIFT (1U) -#define VAD_RUN_SFTRST_SET(x) (((uint32_t)(x) << VAD_RUN_SFTRST_SHIFT) & VAD_RUN_SFTRST_MASK) -#define VAD_RUN_SFTRST_GET(x) (((uint32_t)(x) & VAD_RUN_SFTRST_MASK) >> VAD_RUN_SFTRST_SHIFT) - -/* - * VAD_EN (RW) - * - * module enable - */ -#define VAD_RUN_VAD_EN_MASK (0x1U) -#define VAD_RUN_VAD_EN_SHIFT (0U) -#define VAD_RUN_VAD_EN_SET(x) (((uint32_t)(x) << VAD_RUN_VAD_EN_SHIFT) & VAD_RUN_VAD_EN_MASK) -#define VAD_RUN_VAD_EN_GET(x) (((uint32_t)(x) & VAD_RUN_VAD_EN_MASK) >> VAD_RUN_VAD_EN_SHIFT) - -/* Bitfield definition for register: OFIFO_CTRL */ -/* - * EN (RW) - * - * Asserted to enable OFIFO - */ -#define VAD_OFIFO_CTRL_EN_MASK (0x1U) -#define VAD_OFIFO_CTRL_EN_SHIFT (0U) -#define VAD_OFIFO_CTRL_EN_SET(x) (((uint32_t)(x) << VAD_OFIFO_CTRL_EN_SHIFT) & VAD_OFIFO_CTRL_EN_MASK) -#define VAD_OFIFO_CTRL_EN_GET(x) (((uint32_t)(x) & VAD_OFIFO_CTRL_EN_MASK) >> VAD_OFIFO_CTRL_EN_SHIFT) - -/* Bitfield definition for register: CIC_CFG */ -/* - * POST_SCALE (RW) - * - * the shift value after CIC results. - */ -#define VAD_CIC_CFG_POST_SCALE_MASK (0xFC00U) -#define VAD_CIC_CFG_POST_SCALE_SHIFT (10U) -#define VAD_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << VAD_CIC_CFG_POST_SCALE_SHIFT) & VAD_CIC_CFG_POST_SCALE_MASK) -#define VAD_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & VAD_CIC_CFG_POST_SCALE_MASK) >> VAD_CIC_CFG_POST_SCALE_SHIFT) - -/* Bitfield definition for register array: COEF */ -/* - * VAL (RO) - * - * The current detected short time energy - */ -#define VAD_COEF_VAL_MASK (0xFFFFFFFFUL) -#define VAD_COEF_VAL_SHIFT (0U) -#define VAD_COEF_VAL_GET(x) (((uint32_t)(x) & VAD_COEF_VAL_MASK) >> VAD_COEF_VAL_SHIFT) - - - -/* COEF register group index macro definition */ -#define VAD_COEF_STE_ACT (0UL) - - -#endif /* HPM_VAD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_wdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_wdg_regs.h deleted file mode 100644 index 89788a7ebce..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6700/ip/hpm_wdg_regs.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_WDG_H -#define HPM_WDG_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CTRL; /* 0x10: Control Register */ - __W uint32_t RESTART; /* 0x14: Restart Register */ - __W uint32_t WREN; /* 0x18: Write Protection Register */ - __W uint32_t ST; /* 0x1C: Status Register */ -} WDG_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * RSTTIME (RW) - * - * The time interval of the reset stage: - * 0: Clock period x 2^7 - * 1: Clock period x 2^8 - * 2: Clock period x 2^9 - * 3: Clock period x 2^10 - * 4: Clock period x 2^11 - * 5: Clock period x 2^12 - * 6: Clock period x 2^13 - * 7: Clock period x 2^14 - */ -#define WDG_CTRL_RSTTIME_MASK (0x700U) -#define WDG_CTRL_RSTTIME_SHIFT (8U) -#define WDG_CTRL_RSTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTTIME_SHIFT) & WDG_CTRL_RSTTIME_MASK) -#define WDG_CTRL_RSTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTTIME_MASK) >> WDG_CTRL_RSTTIME_SHIFT) - -/* - * INTTIME (RW) - * - * The timer interval of the interrupt stage: - * 0: Clock period x 2^6 - * 1: Clock period x 2^8 - * 2: Clock period x 2^10 - * 3: Clock period x 2^11 - * 4: Clock period x 2^12 - * 5: Clock period x 2^13 - * 6: Clock period x 2^14 - * 7: Clock period x 2^15 - * 8: Clock period x 2^17 - * 9: Clock period x 2^19 - * 10: Clock period x 2^21 - * 11: Clock period x 2^23 - * 12: Clock period x 2^25 - * 13: Clock period x 2^27 - * 14: Clock period x 2^29 - * 15: Clock period x 2^31 - */ -#define WDG_CTRL_INTTIME_MASK (0xF0U) -#define WDG_CTRL_INTTIME_SHIFT (4U) -#define WDG_CTRL_INTTIME_SET(x) (((uint32_t)(x) << WDG_CTRL_INTTIME_SHIFT) & WDG_CTRL_INTTIME_MASK) -#define WDG_CTRL_INTTIME_GET(x) (((uint32_t)(x) & WDG_CTRL_INTTIME_MASK) >> WDG_CTRL_INTTIME_SHIFT) - -/* - * RSTEN (RW) - * - * Enable or disable the watchdog reset - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_RSTEN_MASK (0x8U) -#define WDG_CTRL_RSTEN_SHIFT (3U) -#define WDG_CTRL_RSTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_RSTEN_SHIFT) & WDG_CTRL_RSTEN_MASK) -#define WDG_CTRL_RSTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_RSTEN_MASK) >> WDG_CTRL_RSTEN_SHIFT) - -/* - * INTEN (RW) - * - * Enable or disable the watchdog interrupt - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_INTEN_MASK (0x4U) -#define WDG_CTRL_INTEN_SHIFT (2U) -#define WDG_CTRL_INTEN_SET(x) (((uint32_t)(x) << WDG_CTRL_INTEN_SHIFT) & WDG_CTRL_INTEN_MASK) -#define WDG_CTRL_INTEN_GET(x) (((uint32_t)(x) & WDG_CTRL_INTEN_MASK) >> WDG_CTRL_INTEN_SHIFT) - -/* - * CLKSEL (RW) - * - * Clock source of timer: - * 0: EXTCLK - * 1: PCLK - */ -#define WDG_CTRL_CLKSEL_MASK (0x2U) -#define WDG_CTRL_CLKSEL_SHIFT (1U) -#define WDG_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << WDG_CTRL_CLKSEL_SHIFT) & WDG_CTRL_CLKSEL_MASK) -#define WDG_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & WDG_CTRL_CLKSEL_MASK) >> WDG_CTRL_CLKSEL_SHIFT) - -/* - * EN (RW) - * - * Enable or disable the watchdog timer - * 0: Disable - * 1: Enable - */ -#define WDG_CTRL_EN_MASK (0x1U) -#define WDG_CTRL_EN_SHIFT (0U) -#define WDG_CTRL_EN_SET(x) (((uint32_t)(x) << WDG_CTRL_EN_SHIFT) & WDG_CTRL_EN_MASK) -#define WDG_CTRL_EN_GET(x) (((uint32_t)(x) & WDG_CTRL_EN_MASK) >> WDG_CTRL_EN_SHIFT) - -/* Bitfield definition for register: RESTART */ -/* - * RESTART (WO) - * - * Write the magic number - * ATCWDT200_RESTART_NUM to restart the - * watchdog timer. - */ -#define WDG_RESTART_RESTART_MASK (0xFFFFU) -#define WDG_RESTART_RESTART_SHIFT (0U) -#define WDG_RESTART_RESTART_SET(x) (((uint32_t)(x) << WDG_RESTART_RESTART_SHIFT) & WDG_RESTART_RESTART_MASK) -#define WDG_RESTART_RESTART_GET(x) (((uint32_t)(x) & WDG_RESTART_RESTART_MASK) >> WDG_RESTART_RESTART_SHIFT) - -/* Bitfield definition for register: WREN */ -/* - * WEN (WO) - * - * Write the magic code to disable the write - * protection of the Control Register and the - * Restart Register. - */ -#define WDG_WREN_WEN_MASK (0xFFFFU) -#define WDG_WREN_WEN_SHIFT (0U) -#define WDG_WREN_WEN_SET(x) (((uint32_t)(x) << WDG_WREN_WEN_SHIFT) & WDG_WREN_WEN_MASK) -#define WDG_WREN_WEN_GET(x) (((uint32_t)(x) & WDG_WREN_WEN_MASK) >> WDG_WREN_WEN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * INTEXPIRED (W1C) - * - * The status of the watchdog interrupt timer - * 0: timer is not expired yet - * 1: timer is expired - */ -#define WDG_ST_INTEXPIRED_MASK (0x1U) -#define WDG_ST_INTEXPIRED_SHIFT (0U) -#define WDG_ST_INTEXPIRED_SET(x) (((uint32_t)(x) << WDG_ST_INTEXPIRED_SHIFT) & WDG_ST_INTEXPIRED_MASK) -#define WDG_ST_INTEXPIRED_GET(x) (((uint32_t)(x) & WDG_ST_INTEXPIRED_MASK) >> WDG_ST_INTEXPIRED_SHIFT) - - - - -#endif /* HPM_WDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/HPM6880_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/HPM6880_svd.xml deleted file mode 100644 index 334d8436044..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/HPM6880_svd.xml +++ /dev/null @@ -1,54804 +0,0 @@ - - - HPMICRO - HPM6880 - HPM6800 - 1.0 - HPM6800 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0xc0000 - - 0x0 - 0x800 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf00d0000 - - - PGPIO - PGPIO - GPIO - 0xf411c000 - - - BGPIO - BGPIO - GPIO - 0xf4214000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - CRC - CRC - CRC - 0xf000c000 - - 0x0 - 0x200 - registers - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - pre_set - &index0 pre set for crc setting - 0x0 - 32 - 0x00000000 - 0x000000FF - - - PRE_SET - 0: no pre set -1: CRC32 -2: CRC32-AUTOSAR -3: CRC16-CCITT -4: CRC16-XMODEM -5: CRC16-MODBUS -1: CRC32 -2: CRC32-autosar -3: CRC16-ccitt -4: CRC16-xmodem -5: CRC16-modbus -6: crc16_dnp -7: crc16_x25 -8: crc16_usb -9: crc16_maxim -10: crc16_ibm -11: crc8_maxim -12: crc8_rohc -13: crc8_itu -14: crc8 -15: crc5_usb - 0 - 8 - read-write - - - - - clr - chn&index0 clear crc result and setting - 0x4 - 32 - 0x00000000 - 0x00000001 - - - CLR - write 1 to clr crc setting and result for its channel. -always read 0. - 0 - 1 - read-write - - - - - poly - chn&index0 poly - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - poly setting - 0 - 32 - read-write - - - - - init_data - chn&index0 init_data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INIT_DATA - initial data of CRC - 0 - 32 - read-write - - - - - xorout - chn&index0 xorout - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XOROUT - XOR for CRC result - 0 - 32 - read-write - - - - - misc_setting - chn&index0 misc_setting - 0x14 - 32 - 0x00000000 - 0x0101013F - - - BYTE_REV - 0: no wrap input byte order -1: wrap input byte order - 24 - 1 - read-write - - - REV_OUT - 0: no wrap output bit order -1: wrap output bit order - 16 - 1 - read-write - - - REV_IN - 0: no wrap input bit order -1: wrap input bit order - 8 - 1 - read-write - - - POLY_WIDTH - crc data length - 0 - 6 - read-write - - - - - data - chn&index0 data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data for crc - 0 - 32 - read-write - - - - - result - chn&index0 result - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - crc result - 0 - 32 - read-write - - - - - - - - UART0 - UART0 - UART - 0xf0040000 - - 0x4 - 0x3c - registers - - - - IDLE_CFG - Idle Configuration Register - 0x4 - 32 - 0x00000000 - 0x00000BFF - - - RXEN - UART receive enable. -0 - hold RX input to high, avoide wrong data input when config pinmux -1 - bypass RX input from PIN -software should set it after config pinmux - 11 - 1 - read-write - - - RX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if RX pin is logic one -1 - Treat as idle if UART state machine state is idle - 9 - 1 - read-write - - - RX_IDLE_EN - UART Idle Detect Enable -0 - Disable -1 - Enable -it should be enabled if enable address match feature - 8 - 1 - read-write - - - RX_IDLE_THR - Threshold for UART Receive Idle detection (in terms of bits) - 0 - 8 - read-write - - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - FCRR - FIFO Control Register config - 0x18 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - read-write - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - read-write - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - read-write - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x8000000F - - - ERXIDLE - Enable Receive Idle interrupt -0 - Disable Idle interrupt -1 - Enable Idle interrupt - 31 - 1 - read-write - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x800000CF - - - RXIDLE_FLAG - UART IDLE Flag -0 - UART is busy -1 - UART is idle -NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - 31 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0x000000FF - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - PUART - PUART - UART - 0xf4124000 - - - I2C0 - I2C0 - I2C - 0xf0060000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00905E00 - 0xFFFFFFFF - - - DATACNT_HIGH - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 24 - 8 - read-write - - - RESET_LEN - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - 20 - 4 - read-write - - - RESET_HOLD_SCKIN - set to hold input clock to high when reset is active - 14 - 1 - read-write - - - RESET_ON - set to send reset signals(just toggle clock bus defined by reset_len). -this register is clered when reset is end, can't be cleared by software - 13 - 1 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf0064000 - - - I2C2 - I2C2 - I2C - 0xf0068000 - - - I2C3 - I2C3 - I2C - 0xf006c000 - - - SPI0 - SPI0 - SPI - 0xf0070000 - - 0x4 - 0x7c - registers - - - - wr_trans_cnt - Transfer count for write data - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 0 - 32 - read-write - - - - - rd_trans_cnt - Transfer count for read data - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 32 - read-write - - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - DirectIO - Direct IO Control Register - 0x14 - 32 - 0x00003100 - 0x013F3F3F - - - DIRECTIOEN - Enable Direct IO -0x0: Disable -0x1: Enable - 24 - 1 - read-write - - - HOLD_OE - Output enable for the SPI Flash hold signal - 21 - 1 - read-write - - - WP_OE - Output enable for the SPI Flash write protect signal - 20 - 1 - read-write - - - MISO_OE - Output enable fo the SPI MISO signal - 19 - 1 - read-write - - - MOSI_OE - Output enable for the SPI MOSI signal - 18 - 1 - read-write - - - SCLK_OE - Output enable for the SPI SCLK signal - 17 - 1 - read-write - - - CS_OE - Output enable for SPI CS (chip select) signal - 16 - 1 - read-write - - - HOLD_O - Output value for the SPI Flash hold signal - 13 - 1 - read-write - - - WP_O - Output value for the SPI Flash write protect signal - 12 - 1 - read-write - - - MISO_O - Output value for the SPI MISO signal - 11 - 1 - read-write - - - MOSI_O - Output value for the SPI MOSI signal - 10 - 1 - read-write - - - SCLK_O - Output value for the SPI SCLK signal - 9 - 1 - read-write - - - CS_O - Output value for the SPI CS (chip select) signal - 8 - 1 - read-write - - - HOLD_I - Status of the SPI Flash hold signal - 5 - 1 - read-only - - - WP_I - Status of the SPI Flash write protect signal - 4 - 1 - read-only - - - MISO_I - Status of the SPI MISO signal - 3 - 1 - read-only - - - MOSI_I - Status of the SPI MOSI signal - 2 - 1 - read-only - - - SCLK_I - Status of the SPI SCLK signal - 1 - 1 - read-only - - - CS_I - Status of the SPI CS (chip select) signal - 0 - 1 - read-only - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x0FFFFF1F - - - CS_EN - No description available - 24 - 4 - read-write - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - SlvDataWCnt - WCnt - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - SlvDataRCnt - RCnt - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0074000 - - - SPI2 - SPI2 - SPI - 0xf0078000 - - - SPI3 - SPI3 - SPI - 0xf007c000 - - - GPTMR0 - GPTMR0 - GPTMR - 0xf0080000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x8003FFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - OPMODE - 0: round mode -1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. -NOTE: reload irq will be always set at one-shot mode at end - 17 - 1 - read-write - - - MONITOR_SEL - set to monitor input signal high level time(chan_meas_high) -clr to monitor input signal period(chan_meas_prd) - 16 - 1 - read-write - - - MONITOR_EN - set to monitor input signal period or high level time. -When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts -* only can be used when trig_mode is selected as measure mode(100) -* the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. -if no posedge after reload for more than val_1, will also assert irq_capt - 15 - 1 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - GPTMR1 - GPTMR1 - GPTMR - 0xf0084000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf0088000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf008c000 - - - GPTMR4 - GPTMR4 - GPTMR - 0xf0090000 - - - GPTMR5 - GPTMR5 - GPTMR - 0xf0094000 - - - GPTMR6 - GPTMR6 - GPTMR - 0xf0098000 - - - GPTMR7 - GPTMR7 - GPTMR - 0xf009c000 - - - NTMR0 - NTMR0 - GPTMR - 0xf1110000 - - - PTMR - PTMR - GPTMR - 0xf4120000 - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - EWDG0 - EWDG0 - EWDG - 0xf00b0000 - - 0x0 - 0x28 - registers - - - - CTRL0 - wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x0 - 32 - 0x00000000 - 0x2FE2F03F - - - CLK_SEL - clock select -0：bus clock -1：ext clock - 29 - 1 - read-write - - - DIV_VALUE - clock divider, the clock divider works as 2 ^ div_value for wdt counter - 25 - 3 - read-write - - - WIN_EN - window mode enable - 24 - 1 - read-write - - - WIN_LOWER - Once window mode is opened, the lower counter value to refresh wdt -00: 4/8 overtime value -01: 5/8 of overtime value -10: 6/8 of overtime value -11: 7/8 of overtime value - 22 - 2 - read-write - - - CFG_LOCK - The register is locked and unlock is needed before re-config registers -Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. -The register update needs to be finished in the required period defined by UPD_OT_TIME register - 21 - 1 - read-write - - - OT_SELF_CLEAR - overtime reset can be self released after 32 function cycles - 17 - 1 - read-write - - - REF_OT_REQ - If refresh event has to be limited into a period after refresh unlocked. -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 15 - 1 - read-write - - - WIN_UPPER - The upper threshold of window value -The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value -If this register value is zero, then no upper level limitation - 12 - 3 - read-write - - - REF_LOCK - WDT refresh has to be unlocked firstly once refresh lock is enable. - 5 - 1 - read-write - - - REF_UNLOCK_MEC - Unlock refresh mechanism -00: the required unlock password is the same with refresh_psd_register -01: the required unlock password is a ring shift left value of refresh_psd_register -10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is -11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - 3 - 2 - read-write - - - EN_DBG - WTD enable or not in debug mode - 2 - 1 - read-write - - - EN_LP - WDT enable or not in low power mode -2'b00: wdt is halted once in low power mode -2'b01: wdt will work with 1/4 normal clock freq in low power mode -2'b10: wdt will work with 1/2 normal clock freq in low power mode -2'b11: wdt will work with normal clock freq in low power mode - 0 - 2 - read-write - - - - - CTRL1 - wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x4 - 32 - 0x00000000 - 0x00F200FC - - - REF_FAIL_RST_EN - Refresh violation will trigger an reset. -These event will be taken as a refresh violation: -1) Not refresh in the window once window mode is enabled -2) Not unlock refresh firstly if unlock is required -3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. -4) Not write the required word to refresh wdt. - 23 - 1 - read-write - - - REF_FAIL_INT_EN - Refresh violation will trigger an interrupt - 22 - 1 - read-write - - - UNL_REF_FAIL_RST_EN - Refresh unlock fail will trigger a reset - 21 - 1 - read-write - - - UNL_REF_FAIL_INT_EN - Refresh unlock fail will trigger a interrupt - 20 - 1 - read-write - - - OT_RST_EN - WDT overtime will generate a reset - 17 - 1 - read-write - - - CTL_VIO_RST_EN - Ctrl update violation will trigger a reset -The violation event is to try updating the locked register before unlock them - 7 - 1 - read-write - - - CTL_VIO_INT_EN - Ctrl update violation will trigger a interrupt - 6 - 1 - read-write - - - UNL_CTL_FAIL_RST_EN - Unlock register update failure will trigger a reset - 5 - 1 - read-write - - - UNL_CTL_FAIL_INT_EN - Unlock register update failure will trigger a interrupt - 4 - 1 - read-write - - - PARITY_FAIL_RST_EN - Parity error will trigger a reset -A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - 3 - 1 - read-write - - - PARITY_FAIL_INT_EN - Parity error will trigger a interrupt - 2 - 1 - read-write - - - - - OT_RST_VAL - wdog timeout reset counter value - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - OT_RST_VAL - WDT timeout reset value - 0 - 16 - read-write - - - - - WDT_REFRESH_REG - wdog refresh register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDT_REFRESH_REG - Write this register by 32'h5A45_524F to refresh wdog -Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - 0 - 32 - write-only - - - - - WDT_STATUS - wdog status register - 0x14 - 32 - 0x00000000 - 0x0000006F - - - PARITY_ERROR - parity error -Write one to clear the bit - 6 - 1 - write-only - - - OT_RST - Timeout happens, a reset will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 5 - 1 - write-only - - - CTL_UNL_FAIL - Unlock ctrl reg update protection fail -Write one to clear the bit - 3 - 1 - write-only - - - CTL_VIO - Violate register update protection mechanism -Write one to clear the bit - 2 - 1 - write-only - - - REF_UNL_FAIL - Refresh unlock fail -Write one to clear the bit - 1 - 1 - write-only - - - REF_VIO - Refresh fail -Write one to clear the bit - 0 - 1 - write-only - - - - - CFG_PROT - ctrl register protection register - 0x18 - 32 - 0x00000000 - 0x000FFFFF - - - UPD_OT_TIME - The period in which register update has to be in after unlock -The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - 16 - 4 - read-write - - - UPD_PSD - The password of unlocking register update - 0 - 16 - read-write - - - - - REF_PROT - refresh protection register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - REF_UNL_PSD - The password to unlock refreshing - 0 - 16 - read-write - - - - - WDT_EN - Wdog enable - 0x20 - 32 - 0x00000000 - 0x00000001 - - - WDOG_EN - Wdog is enabled, the re-written of this register is impacted by enable lock function - 0 - 1 - read-write - - - - - REF_TIME - Refresh period value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - REFRESH_PERIOD - The refresh period after refresh unlocked -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 0 - 16 - read-write - - - - - - - EWDG1 - EWDG1 - EWDG - 0xf00b4000 - - - PEWDG - PEWDG - EWDG - 0xf4128000 - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c4000 - - 0x0 - 0x100 - registers - - - - 64 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7,XDMA_MUX8,XDMA_MUX9,XDMA_MUX10,XDMA_MUX11,XDMA_MUX12,XDMA_MUX13,XDMA_MUX14,XDMA_MUX15,XDMA_MUX16,XDMA_MUX17,XDMA_MUX18,XDMA_MUX19,XDMA_MUX20,XDMA_MUX21,XDMA_MUX22,XDMA_MUX23,XDMA_MUX24,XDMA_MUX25,XDMA_MUX26,XDMA_MUX27,XDMA_MUX28,XDMA_MUX29,XDMA_MUX30,XDMA_MUX31 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - read-write - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - read-write - - - - - - - HDMA - HDMA - DMAV2 - 0xf00c8000 - - 0x4 - 0x43c - registers - - - - IDMisc - ID Misc - 0x4 - 32 - 0x00000000 - 0x0000FF00 - - - DMASTATE - DMA state machine -localparam ST_IDLE = 3'b000; -localparam ST_READ = 3'b001; -localparam ST_READ_ACK = 3'b010; -localparam ST_WRITE = 3'b011; -localparam ST_WRITE_ACK = 3'b100; -localparam ST_LL = 3'b101; -localparam ST_END = 3'b110; -localparam ST_END_WAIT = 3'b111; - 13 - 3 - read-only - - - CURCHAN - current channel in used - 8 - 5 - read-only - - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. -The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, -which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x14 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. -Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - INTHALFSTS - Harlf Complete Interrupt Status - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - half transfer done irq status - 0 - 32 - read-write - - - - - INTTCSTS - Trans Complete Interrupt Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 0 - 32 - write-only - - - - - INTABORTSTS - Abort Interrupt Status Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 0 - 32 - write-only - - - - - INTERRSTS - Error Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 32 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 32 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel &index0 Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFF01F - - - INFINITELOOP - set to loop current config infinitely - 31 - 1 - read-write - - - HANDSHAKEOPT - 0: one request to transfer one burst -1: one request to transfer all the data defined in ch_tts - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - BURSTOPT - set to change burst_size definition - 28 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; -otherwise the error event will be triggered. -For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -Normal mode is enabled and started by software set Enable bit; -Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -the difference bewteen Source/Destination handshake mode is: -the dma block will response hardware request after read in Source handshake mode; -the dma block will response hardware request after write in Destination handshake mode; -NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - INTHALFCNTMASK - Channel half interrupt mask -0x0: Allow the half interrupt to be triggered -0x1: Disable the half interrupt - 4 - 1 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel &index0Transfer Size Register - 0x4 - 32 - 0x00000000 - 0x0FFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 28 - read-write - - - - - SrcAddr - Channel &index0 Source Address Low Part Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - ChanReqCtrl - Channel &index0 DMA Request Control Register - 0xc - 32 - 0x00000000 - 0x1F1F0000 - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 24 - 5 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 16 - 5 - read-write - - - - - DstAddr - Channel &index0 Destination Address Low Part Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - LLPointer - Channel &index0 Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF8 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - - - - - - XDMA - XDMA - DMAV2 - 0xf3008000 - - - GPIOM - GPIOM - GPIOM - 0xf00d8000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,gpiox,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000303 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - 8 - 2 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -2: cpu0 fastgpio - 0 - 2 - read-write - - - - - - - - ADC0 - ADC0 - ADC16 - 0xf00e0000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000001 - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - seq_high_cfg - No description available - 0x850 - 32 - 0x00000000 - 0x00FFFFFF - - - STOP_POS_HIGH - No description available - 12 - 12 - read-write - - - BUF_LEN_HIGH - No description available - 0 - 12 - read-write - - - - - 16 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFE0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x00001004 - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x01F07FFF - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - I2S0 - I2S0 - I2S - 0xf0200000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - write-only - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - write-only - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXD[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -5'h2: 2 channels -5'h4: 4 channels -... -5‘h10: 16 channels (max) - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXDSLOT[%s] - no description available - 0x60 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXDSLOT[%s] - no description available - 0x70 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0204000 - - - I2S2 - I2S2 - I2S - 0xf0208000 - - - I2S3 - I2S3 - I2S - 0xf020c000 - - - DAO - DAO - DAO - 0xf0210000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000200FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to consume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x00000FFF - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -For more details on I2S standards. -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0214000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - write-only - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - write-only - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description available - 18 - 2 - read-write - - - CH8_TYPE - No description available - 16 - 2 - read-write - - - CH7_TYPE - No description available - 14 - 2 - read-write - - - CH6_TYPE - No description available - 12 - 2 - read-write - - - CH5_TYPE - No description available - 10 - 2 - read-write - - - CH4_TYPE - No description available - 8 - 2 - read-write - - - CH3_TYPE - No description available - 6 - 2 - read-write - - - CH2_TYPE - No description available - 4 - 2 - read-write - - - CH1_TYPE - No description available - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMAddr - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMData - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - SMIX - SMIX - SMIX - 0xf0218000 - - 0x0 - 0xac0 - registers - - - - DMAC_ID - DMAC_ID Register - 0x0 - 32 - 0x00000001 - 0x0007FFFF - - - REV - Revision - 0 - 19 - read-only - - - - - DMAC_TC_ST - Transfer Complete Status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH - The terminal count status is set when a channel transfer finishes without abort or error events - 0 - 26 - write-only - - - - - DMAC_ABRT_ST - Transfer Abort Status - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH - The abort status is set when a channel transfer is aborted - 0 - 26 - write-only - - - - - DMAC_ERR_ST - Transfer Error Status - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CH - The error status is set when a channel transfer encounters the following error events: -. Bus error -. Unaligned address -. Unaligned transfer width -. Reserved configuration - 0 - 26 - write-only - - - - - DMAC_CTRL - Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRST - Software Reset - 0 - 1 - read-write - - - - - DMAC_ABRT_CMD - Abort Command Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH - Write 1 to force the corresponding channel into abort status - 0 - 26 - write-only - - - - - DMAC_CHEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH - Write 1 to enable the corresponding channel - 0 - 26 - read-only - - - - - 26 - 0x20 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25 - DMA_CH[%s] - no description available - 0x40 - - CTL - Channel N Control Register - 0x0 - 32 - 0x00000000 - 0xFFEFFFEF - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 26 - 5 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 21 - 5 - read-write - - - PRIORITY - 0x0: Lower priority -0x1: Higher priority - 19 - 1 - read-write - - - SRCBURSTSIZE - 0x0: 1 beat per transfer -0x1: 2 beats per transfer -0x2: 4 beats per transfer -0x3: 8 beats per transfer -0x4: 16 beats per transfer -0x5: 32 beats per transfer -0x6: 64 beats per transfer -0x7: 128 beats per transfer - 15 - 4 - read-write - - - SRCWIDTH - Source Transfer Beat Size: -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer - 13 - 2 - read-write - - - DSTWIDTH - Destination Transfer Beat Size: -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer - 11 - 2 - read-write - - - SRCMODE - DMA Source handshake mode -0x0: Normal mode -0x1: Handshake mode - 10 - 1 - read-write - - - DSTMODE - DMA Destination handshake mode -0x0: Normal mode -0x1: Handshake mode - 9 - 1 - read-write - - - SRCADDRCTRL - 0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers an error exception - 7 - 2 - read-write - - - DSTADDRCTRL - 0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers an error exception - 5 - 2 - read-write - - - ABRT_INT_EN - Abort interrupt enable - 3 - 1 - read-write - - - ERR_INT_EN - Err interrupt enable - 2 - 1 - read-write - - - TC_INT_EN - TC interrupt enable - 1 - 1 - read-write - - - EN - channel enable bit - 0 - 1 - read-write - - - - - BURST_COUNT - Channel N Source Total Beats Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - NUM - the total number of source beats - 0 - 32 - read-write - - - - - SrcAddr - Channel N Source Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - source address - 0 - 32 - read-write - - - - - DstAddr - Channel N Destination Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - destination address - 0 - 32 - read-write - - - - - LLP - Channel N Linked List Pointer Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - the address pointer for the linked list descriptor - 0 - 32 - read-write - - - - - - CALSAT_ST - SMIX Cal Saturation Status Register - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - DST - DST CAL_SAT_ERR. W1C - 30 - 2 - write-only - - - SRC - SRC CAL_SAT_ERR. W1C - 0 - 14 - write-only - - - - - FDOT_DONE_ST - SMIX Fade-Out Done Status Register - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DST - DST fadeout done. W1C - 30 - 2 - write-only - - - SRC - SRC fadeout done. W1C - 0 - 14 - write-only - - - - - DATA_ST - SMIX Data Status Register - 0x808 - 32 - 0x00000000 - 0xFFFFFFFF - - - DST_DA - DST data available - 30 - 2 - read-only - - - DST_UNDL - DST data underflow - 28 - 2 - read-only - - - SRC_DN - SRC data needed - 0 - 14 - read-only - - - - - 2 - 0x40 - 0,1 - DST_CH[%s] - no description available - 0x840 - - CTRL - SMIX Dstination N Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_UNFL_IE - Data Underflow Error IntEn - 20 - 1 - read-write - - - THRSH - FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. - 12 - 8 - read-write - - - CALSAT_INT_EN - Cal Saturation IntEn - 11 - 1 - read-write - - - DA_INT_EN - Data Available IntEn - 10 - 1 - read-write - - - ADEACTFADEOUT_EN - AutoDeactAfterFadeOut_En: -Asserted to enter de-activated mode after fade-out done - 9 - 1 - read-write - - - FADEOUT_DONE_IE - Fade-Out interrupt enable - 8 - 1 - read-write - - - DST_DEACT - de-activate the destination channel - 7 - 1 - read-write - - - DST_ACT - activate the destination channel - 6 - 1 - read-write - - - DSTFADOUT_MEN - Manual FadeOut_Ctrl for destionation. Auto clear. - 5 - 1 - read-write - - - DSTFADOUT_AEN - Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value - 4 - 1 - read-write - - - DSTFADIN_EN - FadeIn_Ctrl for destionation. Auto clear. - 3 - 1 - read-write - - - DST_EN - Dst enabled. When disabled, clear the FIFO pointers. - 2 - 1 - read-write - - - SOFTRST - Soft reset - 1 - 1 - read-write - - - MIXER_EN - mixer function enable. - 0 - 1 - read-write - - - - - GAIN - SMIX Dstination N Gain Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] - 0 - 15 - read-write - - - - - BUFSIZE - SMIX Dstination N Max Index Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - MAX_IDX - The total length of the dst stream -1. If zero, means there is no end of the stream. - 0 - 32 - read-write - - - - - FADEIN - SMIX Dstination N Fade-In Configuration Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DELTA - Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) -(Using only top 14 bits for mul) - 0 - 20 - read-write - - - - - FADEOUT - SMIX Dstination N Fade-Out Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DELTA - Fade out in 2^DELTA samples. Now DELTA can be at most 14。 - 0 - 20 - read-write - - - - - ST - SMIX Dstination N Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFO_FILLINGS - destination channel output FIFO fillings - 6 - 9 - read-only - - - FDOUT_DONE - Fade-Out Done. W1C - 5 - 1 - read-only - - - CALSAT - Saturate Error Found. W1C - 4 - 1 - read-only - - - DA - Data Available - 3 - 1 - read-only - - - MODE - The modes are: -Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. -Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. -Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. -Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. -Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg -Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. -Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. - 0 - 3 - read-only - - - - - Data - SMIX Dstination N Data Out Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Output data buffer - 0 - 32 - read-only - - - - - SOURCE_EN - SMIX Dstination N Source Enable Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. - 0 - 8 - read-write - - - - - SOURCE_ACT - SMIX Dstination N Source Activation Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Manually Activate the channel - 0 - 8 - write-only - - - - - SOURCE_DEACT - SMIX Dstination N Source De-Activation Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Manually DeActivate the channel - 0 - 8 - write-only - - - - - SOURCE_FADEIN_CTRL - SMIX Dstination N Source Fade-in Control Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - AOP - Asserted to start fade-in operation. When the amplification factors are stable, auto clear. - 0 - 8 - read-write - - - - - DEACT_ST - SMIX Dstination N Source Deactivation Status Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - DST_DEACT - Asserted when in de-active mode - 31 - 1 - read-only - - - SRC_DEACT_ST - Asserted when in de-active mode - 0 - 8 - read-only - - - - - SOURCE_MFADEOUT_CTRL - SMIX Dstination N Source Manual Fade-out Control Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - OP - Asserted to start fade-out operation. When the amplification factors are stable, auto clear. - 0 - 8 - read-write - - - - - - 14 - 0x20 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13 - SOURCE_CH[%s] - no description available - 0x900 - - CTRL - SMIX Source N Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFC7 - - - FIFO_RESET - Asserted to reset FIFO pointer. Cleared to exit reset state. - 21 - 1 - read-write - - - THRSH - FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. - 13 - 8 - read-write - - - CALSAT_INT_EN - Cal Saturation IntEn - 12 - 1 - read-write - - - DN_INT_EN - Data Needed IntEn - 11 - 1 - read-write - - - SHFT_CTRL - Shift operation after FIR -0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) -1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) -2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) -7: /2 (when rate /2) -Other n: shift-left-by-n, but not suggested to be used. - 8 - 3 - read-write - - - AUTODEACTAFTERFADEOUT_EN - Asserted to enter de-activated mode after fade-out done - 7 - 1 - read-write - - - FADEOUT_DONE_IE - Fade-Out interrupt enable - 6 - 1 - read-write - - - RATECONV - 0: no rate conversion -1: up-conversion x2 -2: up-conversion x3 -3: up-conversion x4 -4: up-conversion x6 -5: up-conversion x8 -6: up-conversion x12 -7: down-conversion /2 - 0 - 3 - read-write - - - - - GAIN - SMIX Source N Gain Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. - 0 - 15 - read-write - - - - - FADEIN - SMIX Source N Fade-in Control Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DELTA - Fade -in confg. - 0 - 20 - read-write - - - - - FADEOUT - SMIX Source N Fade-out Control Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DELTA - Fade out in 2^DELTA samples. Now DELTA can be at most 14。 - 0 - 20 - read-write - - - - - BufSize - SMIX Source N Buffer Size Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - MAXIDX - unit as 16-bits per sample. Zero means no length limit. = Act Len-1. -The actual length is the up_rate*(input_data_length-4). -If the filter processing is down-sampling, the value of up_rate above is 1. -If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. - 0 - 32 - read-write - - - - - ST - SMIX Source N Status Register - 0x14 - 32 - 0x00000000 - 0x0007FFFF - - - FIFO_FILLINGS - The fillings of input FIFO. - 10 - 9 - read-only - - - FDOUT_DONE - Fade-Out Done. W1C - 9 - 1 - write-only - - - CALSAT - Calculation saturation status. W1C - 8 - 1 - write-only - - - DN - Data needed flag - 7 - 1 - read-only - - - FIRPHASE - the poly phase counter - 3 - 4 - read-only - - - MODE - The modes are: -Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. -Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD -Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. -Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. -Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. -Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg -Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. -Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. - 0 - 3 - read-only - - - - - Data - SMIX Source N Data Input Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Data input register - 0 - 32 - write-only - - - - - - - - MCAN0 - MCAN0 - MCAN - 0xf0280000 - - 0x4 - 0x29fc - registers - - - - ENDN - endian register - 0x4 - 32 - 0x87654321 - 0xFFFFFFFF - - - EVT - Endianness Test Value -The endianness test value is 0x87654321. - 0 - 32 - read-only - - - - - DBTP - data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set - 0xc - 32 - 0x00000A33 - 0x009F1FFF - - - TDC - transmitter delay compensation enable -0= Transmitter Delay Compensation disabled -1= Transmitter Delay Compensation enabled - 23 - 1 - read-write - - - DBRP - Data Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. -When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 5 - read-write - - - DTSEG1 - Data time segment before sample point -Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 5 - read-write - - - DTSEG2 - Data time segment after sample point -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 4 - 4 - read-write - - - DSJW - Data (Re)Synchronization Jump Width -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 0 - 4 - read-write - - - - - TEST - test register - 0x10 - 32 - 0x00000000 - 0x003F3FF0 - - - SVAL - Started Valid -0= Value of TXBNS not valid -1= Value of TXBNS valid - 21 - 1 - read-only - - - TXBNS - Tx Buffer Number Started -Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - 16 - 5 - read-only - - - PVAL - Prepared Valid -0= Value of TXBNP not valid -1= Value of TXBNP valid - 13 - 1 - read-only - - - TXBNP - Tx Buffer Number Prepared -Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - 8 - 5 - read-only - - - RX - Receive Pin -Monitors the actual value of pin m_can_rx -0= The CAN bus is dominant (m_can_rx = ‘0’) -1= The CAN bus is recessive (m_can_rx = ‘1’) - 7 - 1 - read-only - - - TX - Control of Transmit Pin -00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time -01 Sample Point can be monitored at pin m_can_tx -10 Dominant (‘0’) level at pin m_can_tx -11 Recessive (‘1’) at pin m_can_tx - 5 - 2 - read-write - - - LBCK - Loop Back Mode -0= Reset value, Loop Back Mode is disabled -1= Loop Back Mode is enabled - 4 - 1 - read-write - - - - - RWD - ram watchdog - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - WDV - Watchdog Value -Actual Message RAM Watchdog Counter Value. - 8 - 8 - read-only - - - WDC - Watchdog Configuration -Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - 0 - 8 - read-write - - - - - CCCR - CC control register - 0x18 - 32 - 0x00000001 - 0x0000FFFF - - - NISO - Non ISO Operation -If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD -Specification V1.0. -0= CAN FD frame format according to ISO 11898-1:2015 -1= CAN FD frame format according to Bosch CAN FD Specification V1.0 -Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - 15 - 1 - read-write - - - TXP - Transmit Pause -If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after -itself has successfully transmitted a frame (see Section 3.5). -0= Transmit pause disabled -1= Transmit pause enabled - 14 - 1 - read-write - - - EFBI - Edge Filtering during Bus Integration -0= Edge filtering disabled -1= Two consecutive dominant tq required to detect an edge for hard synchronization - 13 - 1 - read-write - - - PXHD - Protocol Exception Handling Disable -0= Protocol exception handling enabled -1= Protocol exception handling disabled -Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - 12 - 1 - read-write - - - WMM - Wide Message Marker -Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. -0= 8-bit Message Marker used -1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - 11 - 1 - read-write - - - UTSU - Use Timestamping Unit -When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. -0= Internal time stamping -1= External time stamping by TSU -Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. -In this case bit UTSU is fixed to zero by synthesis. - 10 - 1 - read-write - - - BRSE - Bit Rate Switch Enable -0= Bit rate switching for transmissions disabled -1= Bit rate switching for transmissions enabled -Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - 9 - 1 - read-write - - - FDOE - FD Operation Enable -0= FD operation disabled -1= FD operation enabled - 8 - 1 - read-write - - - TEST - Test Mode Enable -0= Normal operation, register TEST holds reset values -1= Test Mode, write access to register TEST enabled - 7 - 1 - read-write - - - DAR - Disable Automatic Retransmission -0= Automatic retransmission of messages not transmitted successfully enabled -1= Automatic retransmission disabled - 6 - 1 - read-write - - - MON - Bus Monitoring Mode -Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. -0= Bus Monitoring Mode is disabled -1= Bus Monitoring Mode is enabled - 5 - 1 - read-write - - - CSR - Clock Stop Request -0= No clock stop is requested -1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - 4 - 1 - read-write - - - CSA - Clock Stop Acknowledge -0= No clock stop acknowledged -1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - 3 - 1 - read-only - - - ASM - Restricted Operation Mode -Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. -0= Normal CAN operation -1= Restricted Operation Mode active - 2 - 1 - read-write - - - CCE - Configuration Change Enable -0= The CPU has no write access to the protected configuration registers -1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - 1 - 1 - read-write - - - INIT - Initialization -0= Normal Operation -1= Initialization is started - 0 - 1 - read-write - - - - - NBTP - nominal bit timing and prescaler register - 0x1c - 32 - 0x06000A03 - 0xFFFFFF7F - - - NSJW - Nominal (Re)Synchronization Jump Width -Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 25 - 7 - read-write - - - NBRP - Nominal Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is -such that one more than the value programmed here is used. - 16 - 9 - read-write - - - NTSEG1 - Nominal Time segment before sample point -Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 8 - read-write - - - NTSEG2 - Nominal Time segment after sample point -Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 0 - 7 - read-write - - - - - TSCC - timestamp counter configuration - 0x20 - 32 - 0x00000000 - 0x000F0003 - - - TCP - Timestamp Counter Prescaler -Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 4 - read-write - - - TSS - timestamp Select -00= Timestamp counter value always 0x0000 -01= Timestamp counter value incremented according to TCP -10= External timestamp counter value used -11= Same as “00” - 0 - 2 - read-write - - - - - TSCV - timestamp counter value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - TSC - Timestamp Counter -The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - 0 - 16 - read-only - - - - - TOCC - timeout counter configuration - 0x28 - 32 - 0xFFFF0000 - 0xFFFF0007 - - - TOP - Timeout Period -Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - 16 - 16 - read-write - - - TOS - Timeout Select -When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. -When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. -00= Continuous operation -01= Timeout controlled by Tx Event FIFO -10= Timeout controlled by Rx FIFO 0 -11= Timeout controlled by Rx FIFO 1 - 1 - 2 - read-write - - - RP - Enable Timeout Counter -0= Timeout Counter disabled -1= Timeout Counter enabled - 0 - 1 - read-write - - - - - TOCV - timeout counter value - 0x2c - 32 - 0x0000FFFF - 0x0000FFFF - - - TOC - Timeout Counter -The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. -Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - 0 - 16 - read-only - - - - - ECR - error counter register - 0x40 - 32 - 0x00000000 - 0x00FFFFFF - - - CEL - CAN Error Logging -The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. -The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. -The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. -Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - 16 - 8 - read-only - - - RP - Receive Error Passive -0= The Receive Error Counter is below the error passive level of 128 -1= The Receive Error Counter has reached the error passive level of 128 - 15 - 1 - read-only - - - REC - Receive Error Counter -Actual state of the Receive Error Counter, values between 0 and 127 - 8 - 7 - read-only - - - TEC - Transmit Error Counter -Actual state of the Transmit Error Counter, values between 0 and 255 -Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - 0 - 8 - read-only - - - - - PSR - protocol status register - 0x44 - 32 - 0x00000707 - 0x007F7FFF - - - TDCV - Transmitter Delay Compensation Value -Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. -The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - 16 - 7 - read-only - - - PXE - Protocol Exception Event -0= No protocol exception event occurred since last read access -1= Protocol exception event occurred -Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - 14 - 1 - read-only - - - RFDF - Received a CAN FD Message -This bit is set independent of acceptance filtering. -0= Since this bit was reset by the CPU, no CAN FD message has been received -1= Message in CAN FD format with FDF flag set has been received -Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - 13 - 1 - read-only - - - RBRS - BRS flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its BRS flag set -1= Last received CAN FD message had its BRS flag set -Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - 12 - 1 - read-only - - - RESI - ESI flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its ESI flag set -1= Last received CAN FD message had its ESI flag set -Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - 11 - 1 - read-only - - - DLEC - Data Phase Last Error Code -Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with -its BRS flag set has been transferred (reception or transmission) without error. -Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - 8 - 3 - read-only - - - BO - Bus_Off Status -0= The M_CAN is not Bus_Off -1= The M_CAN is in Bus_Off state - 7 - 1 - read-only - - - EW - Warning Status -0= Both error counters are below the Error_Warning limit of 96 -1= At least one of error counter has reached the Error_Warning limit of 96 - 6 - 1 - read-only - - - EP - Error Passive -0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected -1= The M_CAN is in the Error_Passive state - 5 - 1 - read-only - - - ACT - Activity -Monitors the module’s CAN communication state. -00= Synchronizing - node is synchronizing on CAN communication -01= Idle - node is neither receiver nor transmitter -10= Receiver - node is operating as receiver -11= Transmitter - node is operating as transmitter -Note: ACT is set to “00” by a Protocol Exception Event. - 3 - 2 - read-only - - - LEC - Last Error Code -The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. -0= No Error: No error occurred since LEC has been reset by successful reception or transmission. -1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. -2= Form Error: A fixed format part of a received frame has the wrong format. -3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. -4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), -the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus -value was dominant. -5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at -dominant or continuously disturbed). -6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. -7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. -Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. -Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. -At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, -enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. -Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - 0 - 3 - read-only - - - - - TDCR - transmitter delay compensation - 0x48 - 32 - 0x00000000 - 0x00007F7F - - - TDCO - Transmitter Delay Compensation SSP Offset -Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - 8 - 7 - read-write - - - TDCF - Transmitter Delay Compensation Filter Window Length -Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. -The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - 0 - 7 - read-write - - - - - IR - interrupt register - 0x50 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARA - Access to Reserved Address -0= No access to reserved address occurred -1= Access to reserved address occurred - 29 - 1 - read-write - - - PED - Protocol Error in Data Phase (Data Bit Time is used) -0= No protocol error in data phase -1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - 28 - 1 - read-write - - - PEA - Protocol Error in Arbitration Phase (Nominal Bit Time is used) -0= No protocol error in arbitration phase -1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - 27 - 1 - read-write - - - WDI - Watchdog Interrupt -0= No Message RAM Watchdog event occurred -1= Message RAM Watchdog event due to missing READY - 26 - 1 - read-write - - - BO - Bus_Off Status -0= Bus_Off status unchanged -1= Bus_Off status changed - 25 - 1 - read-write - - - EW - Warning Status -0= Error_Warning status unchanged -1= Error_Warning status changed - 24 - 1 - read-write - - - EP - Error Passive -0= Error_Passive status unchanged -1= Error_Passive status changed - 23 - 1 - read-write - - - ELO - Error Logging Overflow -0= CAN Error Logging Counter did not overflow -1= Overflow of CAN Error Logging Counter occurred - 22 - 1 - read-write - - - BEU - Bit Error Uncorrected -Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. -An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. -0= No bit error detected when reading from Message RAM -1= Bit error detected, uncorrected (e.g. parity logic) - 21 - 1 - read-write - - - BEC - Bit Error Corrected -Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. -0= No bit error detected when reading from Message RAM -1= Bit error detected and corrected (e.g. ECC) - 20 - 1 - read-write - - - DRX - Message stored to Dedicated Rx Buffer -The flag is set whenever a received message has been stored into a dedicated Rx Buffer. -0= No Rx Buffer updated -1= At least one received message stored into an Rx Buffer - 19 - 1 - read-write - - - TOO - Timeout Occurred -0= No timeout -1= Timeout reached - 18 - 1 - read-write - - - MRAF - Message RAM Access Failure -The flag is set, when the Rx Handler -.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message -storage is aborted and the Rx Handler starts processing of the following message. -.was not able to write a message to the Message RAM. In this case message storage is aborted. -In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. -The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the -M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. -0= No Message RAM access failure occurred -1= Message RAM access failure occurred - 17 - 1 - read-write - - - TSW - Timestamp Wraparound -0= No timestamp counter wrap-around -1= Timestamp counter wrapped around - 16 - 1 - read-write - - - TEFL - Tx Event FIFO Element Lost -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - 15 - 1 - read-write - - - TEFF - Tx Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 14 - 1 - read-write - - - TEFW - Tx Event FIFO Watermark Reached -0= Tx Event FIFO fill level below watermark -1= Tx Event FIFO fill level reached watermark - 13 - 1 - read-write - - - TEFN - Tx Event FIFO New Entry -0= Tx Event FIFO unchanged -1= Tx Handler wrote Tx Event FIFO element - 12 - 1 - read-write - - - TFE - Tx FIFO Empty -0= Tx FIFO non-empty -1= Tx FIFO empty - 11 - 1 - read-write - - - TCF - Transmission Cancellation Finished -0= No transmission cancellation finished -1= Transmission cancellation finished - 10 - 1 - read-write - - - TC - Transmission Completed -0= No transmission completed -1= Transmission completed - 9 - 1 - read-write - - - HPM - High Priority Message -0= No high priority message received -1= High priority message received - 8 - 1 - read-write - - - RF1L - Rx FIFO 1 Message Lost -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - 7 - 1 - read-write - - - RF1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 6 - 1 - read-write - - - RF1W - Rx FIFO 1 Watermark Reached -0= Rx FIFO 1 fill level below watermark -1= Rx FIFO 1 fill level reached watermark - 5 - 1 - read-write - - - RF1N - Rx FIFO 1 New Message -0= No new message written to Rx FIFO 1 -1= New message written to Rx FIFO 1 - 4 - 1 - read-write - - - RF0L - Rx FIFO 0 Message Lost -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - 3 - 1 - read-write - - - RF0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 2 - 1 - read-write - - - RF0W - Rx FIFO 0 Watermark Reached -0= Rx FIFO 0 fill level below watermark -1= Rx FIFO 0 fill level reached watermark - 1 - 1 - read-write - - - RF0N - Rx FIFO 0 New Message -0= No new message written to Rx FIFO 0 -1= New message written to Rx FIFO 0 - 0 - 1 - read-write - - - - - IE - interrupt enable - 0x54 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAE - Access to Reserved Address Enable - 29 - 1 - read-write - - - PEDE - Protocol Error in Data Phase Enable - 28 - 1 - read-write - - - PEAE - Protocol Error in Arbitration Phase Enable - 27 - 1 - read-write - - - WDIE - Watchdog Interrupt Enable - 26 - 1 - read-write - - - BOE - Bus_Off Status Interrupt Enable - 25 - 1 - read-write - - - EWE - Warning Status Interrupt Enable - 24 - 1 - read-write - - - EPE - Error Passive Interrupt Enable - 23 - 1 - read-write - - - ELOE - Error Logging Overflow Interrupt Enable - 22 - 1 - read-write - - - BEUE - Bit Error Uncorrected Interrupt Enable - 21 - 1 - read-write - - - BECE - Bit Error Corrected Interrupt Enable - 20 - 1 - read-write - - - DRXE - Message stored to Dedicated Rx Buffer Interrupt Enable - 19 - 1 - read-write - - - TOOE - Timeout Occurred Interrupt Enable - 18 - 1 - read-write - - - MRAFE - Message RAM Access Failure Interrupt Enable - 17 - 1 - read-write - - - TSWE - Timestamp Wraparound Interrupt Enable - 16 - 1 - read-write - - - TEFLE - Tx Event FIFO Event Lost Interrupt Enable - 15 - 1 - read-write - - - TEFFE - Tx Event FIFO Full Interrupt Enable - 14 - 1 - read-write - - - TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - 13 - 1 - read-write - - - TEFNE - Tx Event FIFO New Entry Interrupt Enable - 12 - 1 - read-write - - - TFEE - Tx FIFO Empty Interrupt Enable - 11 - 1 - read-write - - - TCFE - Transmission Cancellation Finished Interrupt Enable - 10 - 1 - read-write - - - TCE - Transmission Completed Interrupt Enable - 9 - 1 - read-write - - - HPME - High Priority Message Interrupt Enable - 8 - 1 - read-write - - - RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - 7 - 1 - read-write - - - RF1FE - Rx FIFO 1 Full Interrupt Enable - 6 - 1 - read-write - - - RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - 5 - 1 - read-write - - - RF1NE - Rx FIFO 1 New Message Interrupt Enable - 4 - 1 - read-write - - - RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - 3 - 1 - read-write - - - RF0FE - Rx FIFO 0 Full Interrupt Enable - 2 - 1 - read-write - - - RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - 1 - 1 - read-write - - - RF0NE - Rx FIFO 0 New Message Interrupt Enable - 0 - 1 - read-write - - - - - ILS - interrupt line select - 0x58 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAL - Access to Reserved Address Line - 29 - 1 - read-write - - - PEDL - Protocol Error in Data Phase Line - 28 - 1 - read-write - - - PEAL - Protocol Error in Arbitration Phase Line - 27 - 1 - read-write - - - WDIL - Watchdog Interrupt Line - 26 - 1 - read-write - - - BOL - Bus_Off Status Interrupt Line - 25 - 1 - read-write - - - EWL - Warning Status Interrupt Line - 24 - 1 - read-write - - - EPL - Error Passive Interrupt Line - 23 - 1 - read-write - - - ELOL - Error Logging Overflow Interrupt Line - 22 - 1 - read-write - - - BEUL - Bit Error Uncorrected Interrupt Line - 21 - 1 - read-write - - - BECL - Bit Error Corrected Interrupt Line - 20 - 1 - read-write - - - DRXL - Message stored to Dedicated Rx Buffer Interrupt Line - 19 - 1 - read-write - - - TOOL - Timeout Occurred Interrupt Line - 18 - 1 - read-write - - - MRAFL - Message RAM Access Failure Interrupt Line - 17 - 1 - read-write - - - TSWL - Timestamp Wraparound Interrupt Line - 16 - 1 - read-write - - - TEFLL - Tx Event FIFO Event Lost Interrupt Line - 15 - 1 - read-write - - - TEFFL - Tx Event FIFO Full Interrupt Line - 14 - 1 - read-write - - - TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - 13 - 1 - read-write - - - TEFNL - Tx Event FIFO New Entry Interrupt Line - 12 - 1 - read-write - - - TFEL - Tx FIFO Empty Interrupt Line - 11 - 1 - read-write - - - TCFL - Transmission Cancellation Finished Interrupt Line - 10 - 1 - read-write - - - TCL - Transmission Completed Interrupt Line - 9 - 1 - read-write - - - HPML - High Priority Message Interrupt Line - 8 - 1 - read-write - - - RF1LL - Rx FIFO 1 Message Lost Interrupt Line - 7 - 1 - read-write - - - RF1FL - Rx FIFO 1 Full Interrupt Line - 6 - 1 - read-write - - - RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - 5 - 1 - read-write - - - RF1NL - Rx FIFO 1 New Message Interrupt Line - 4 - 1 - read-write - - - RF0LL - Rx FIFO 0 Message Lost Interrupt Line - 3 - 1 - read-write - - - RF0FL - Rx FIFO 0 Full Interrupt Line - 2 - 1 - read-write - - - RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - 1 - 1 - read-write - - - RF0NL - Rx FIFO 0 New Message Interrupt Line - 0 - 1 - read-write - - - - - ILE - interrupt line enable - 0x5c - 32 - 0x00000000 - 0x00000003 - - - EINT1 - Enable Interrupt Line 1 -0= Interrupt line m_can_int1 disabled -1= Interrupt line m_can_int1 enabled - 1 - 1 - read-write - - - EINT0 - Enable Interrupt Line 0 -0= Interrupt line m_can_int0 disabled -1= Interrupt line m_can_int0 enabled - 0 - 1 - read-write - - - - - GFC - global filter configuration - 0x80 - 32 - 0x00000000 - 0x0000003F - - - ANFS - Accept Non-matching Frames Standard -Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 4 - 2 - read-write - - - ANFE - Accept Non-matching Frames Extended -Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 2 - 2 - read-write - - - RRFS - Reject Remote Frames Standard -0= Filter remote frames with 11-bit standard IDs -1= Reject all remote frames with 11-bit standard IDs - 1 - 1 - read-write - - - RRFE - Reject Remote Frames Extended -0= Filter remote frames with 29-bit extended IDs -1= Reject all remote frames with 29-bit extended IDs - 0 - 1 - read-write - - - - - SIDFC - standard ID filter configuration - 0x84 - 32 - 0x00000000 - 0x00FFFFFC - - - LSS - List Size Standard -0= No standard Message ID filter -1-128= Number of standard Message ID filter elements ->128= Values greater than 128 are interpreted as 128 - 16 - 8 - read-write - - - FLSSA - Filter List Standard Start Address -Start address of standard Message ID filter list (32-bit word address) - 2 - 14 - read-write - - - - - XIDFC - extended ID filter configuration - 0x88 - 32 - 0x00000000 - 0x007FFFFC - - - LSE - List Size Extended -0= No extended Message ID filter -1-64= Number of extended Message ID filter elements ->64= Values greater than 64 are interpreted as 64 - 16 - 7 - read-write - - - FLESA - Filter List Extended Start Address -Start address of extended Message ID filter list (32-bit word address). - 2 - 14 - read-write - - - - - XIDAM - extended id and mask - 0x90 - 32 - 0x1FFFFFFF - 0x1FFFFFFF - - - EIDM - Extended ID Mask -For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - 0 - 29 - read-write - - - - - HPMS - high priority message status - 0x94 - 32 - 0x00000000 - 0x0000FFFF - - - FLST - Filter List -Indicates the filter list of the matching filter element. -0= Standard Filter List -1= Extended Filter List - 15 - 1 - read-only - - - FIDX - Filter Index -Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - 8 - 7 - read-only - - - MSI - Message Storage Indicator -00= No FIFO selected -01= FIFO message lost -10= Message stored in FIFO 0 -11= Message stored in FIFO 1 - 6 - 2 - read-only - - - BIDX - Buffer Index -Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - 0 - 6 - read-only - - - - - NDAT1 - new data1 - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - ND1 - New Data[31:0] -The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - NDAT2 - new data2 - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - ND2 - New Data[63:32] -The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - RXF0C - rx fifo 0 configuration - 0xa0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F0OM - FIFO 0 Operation Mode -FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 0 blocking mode -1= FIFO 0 overwrite mode - 31 - 1 - read-write - - - F0WM - Rx FIFO 0 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F0S - Rx FIFO 0 Size -0= No Rx FIFO 0 -1-64= Number of Rx FIFO 0 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 0 elements are indexed from 0 to F0S-1 - 16 - 7 - read-write - - - F0SA - Rx FIFO 0 Start Address -Start address of Rx FIFO 0 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF0S - rx fifo 0 status - 0xa4 - 32 - 0x00000000 - 0x033F3F7F - - - RF0L - Rx FIFO 0 Message Lost -This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero -Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 24 - 1 - read-only - - - F0PI - Rx FIFO 0 Put Index -Rx FIFO 0 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F0GI - Rx FIFO 0 Get Index -Rx FIFO 0 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F0FL - Rx FIFO 0 Fill Level -Number of elements stored in Rx FIFO 0, range 0 to 64. - 0 - 7 - read-only - - - - - RXF0A - rx fifo0 acknowledge - 0xa8 - 32 - 0x00000000 - 0x0000003F - - - F0AI - Rx FIFO 0 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. -This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - 0 - 6 - read-write - - - - - RXBC - rx buffer configuration - 0xac - 32 - 0x00000000 - 0x0000FFFC - - - RBSA - Rx Buffer Start Address -Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - 2 - 14 - read-write - - - - - RXF1C - rx fifo1 configuration - 0xb0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F1OM - FIFO 1 Operation Mode -FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 1 blocking mode -1= FIFO 1 overwrite mode - 31 - 1 - read-write - - - F1WM - Rx FIFO 1 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F1S - Rx FIFO 1 Size -0= No Rx FIFO 1 -1-64= Number of Rx FIFO 1 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - 16 - 7 - read-write - - - F1SA - Rx FIFO 1 Start Address -Start address of Rx FIFO 1 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF1S - rx fifo1 status - 0xb4 - 32 - 0x00000000 - 0xC33F3F7F - - - DMS - Debug Message Status -00= Idle state, wait for reception of debug messages, DMA request is cleared -01= Debug message A received -10= Debug messages A, B received -11= Debug messages A, B, C received, DMA request is set - 30 - 2 - read-only - - - RF1L - Rx FIFO 1 Message Lost -This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero -Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 24 - 1 - read-only - - - F1PI - Rx FIFO 1 Put Index -Rx FIFO 1 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F1GI - Rx FIFO 1 Get Index -Rx FIFO 1 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F1FL - Rx FIFO 1 Fill Level -Number of elements stored in Rx FIFO 1, range 0 to 64. - 0 - 7 - read-only - - - - - RXF1A - rx fifo 1 acknowledge - 0xb8 - 32 - 0x00000000 - 0x0000003F - - - F1AI - Rx FIFO 1 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. -This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - 0 - 6 - read-write - - - - - RXESC - rx buffer/fifo element size configuration - 0xbc - 32 - 0x00000000 - 0x00000777 - - - RBDS - Rx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 8 - 3 - read-write - - - F1DS - Rx FIFO 1 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 4 - 3 - read-write - - - F0DS - Rx FIFO 0 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, -only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - 0 - 3 - read-write - - - - - TXBC - tx buffer configuration - 0xc0 - 32 - 0x00000000 - 0x7F3FFFFC - - - TFQM - Tx FIFO/Queue Mode -0= Tx FIFO operation -1= Tx Queue operation - 30 - 1 - read-write - - - TFQS - Transmit FIFO/Queue Size -0= No Tx FIFO/Queue -1-32= Number of Tx Buffers used for Tx FIFO/Queue ->32= Values greater than 32 are interpreted as 32 - 24 - 6 - read-write - - - NDTB - Number of Dedicated Transmit Buffers -0= No Dedicated Tx Buffers -1-32= Number of Dedicated Tx Buffers ->32= Values greater than 32 are interpreted as 32 - 16 - 6 - read-write - - - TBSA - Tx Buffers Start Address -Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). -Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - 2 - 14 - read-write - - - - - TXFQS - tx fifo/queue status - 0xc4 - 32 - 0x00000000 - 0x003F1F3F - - - TFQF - Tx FIFO/Queue Full -0= Tx FIFO/Queue not full -1= Tx FIFO/Queue full - 21 - 1 - read-only - - - TFQPI - Tx FIFO/Queue Put Index -Tx FIFO/Queue write index pointer, range 0 to 31. - 16 - 5 - read-only - - - TFGI - Tx FIFO Get Index -Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured -(TXBC.TFQM = ‘1’). - 8 - 5 - read-only - - - TFFL - Tx FIFO Free Level -Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) -Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with -the first dedicated Tx Buffers. -Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - 0 - 6 - read-only - - - - - TXESC - tx buffer element size configuration - 0xc8 - 32 - 0x00000000 - 0x00000007 - - - TBDS - Tx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - 0 - 3 - read-write - - - - - TXBRP - tx buffer request pending - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - TRP - Transmission Request Pending -Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register -TXBCR. -TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the -highest priority (Tx Buffer with lowest Message ID). -A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, -this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. -After a cancellation has been requested, a finished cancellation is signalled via TXBCF -? after successful transmission together with the corresponding TXBTO bit -? when the transmission has not yet been started at the point of cancellation -? when the transmission has been aborted due to lost arbitration -? when an error occurred during frame transmission -In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. -0= No transmission request pending -1= Transmission request pending -Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - 0 - 32 - read-only - - - - - TXBAR - tx buffer add request - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - AR - Add Request -Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx -Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. -When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. -0= No transmission request added -1= Transmission requested added -Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - 0 - 32 - read-write - - - - - TXBCR - tx buffer cancellation request - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR - Cancellation Request -Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. -This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. -0= No cancellation pending -1= Cancellation pending - 0 - 32 - read-write - - - - - TXBTO - tx buffer transmission occurred - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TO - Transmission Occurred -Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmission occurred -1= Transmission occurred - 0 - 32 - read-only - - - - - TXBCF - tx buffer cancellation finished - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - CF - Cancellation Finished -Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. -In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmit buffer cancellation -1= Transmit buffer cancellation finished - 0 - 32 - read-only - - - - - TXBTIE - tx buffer transmission interrupt enable - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIE - Transmission Interrupt Enable -Each Tx Buffer has its own Transmission Interrupt Enable bit. -0= Transmission interrupt disabled -1= Transmission interrupt enable - 0 - 32 - read-write - - - - - TXBCIE - tx buffer cancellation finished interrupt enable - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFIE - Cancellation Finished Interrupt Enable -Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. -0= Cancellation finished interrupt disabled -1= Cancellation finished interrupt enabled - 0 - 32 - read-write - - - - - TXEFC - tx event fifo configuration - 0xf0 - 32 - 0x00000000 - 0x3F3FFFFC - - - EFWM - Event FIFO Watermark -0= Watermark interrupt disabled -1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) ->32= Watermark interrupt disabled - 24 - 6 - read-write - - - EFS - Event FIFO Size -0= Tx Event FIFO disabled -1-32= Number of Tx Event FIFO elements ->32= Values greater than 32 are interpreted as 32 -The Tx Event FIFO elements are indexed from 0 to EFS - 1 - 16 - 6 - read-write - - - EFSA - Event FIFO Start Address -Start address of Tx Event FIFO in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - TXEFS - tx event fifo status - 0xf4 - 32 - 0x00000000 - 0x031F1F3F - - - TEFL - Tx Event FIFO Element Lost -This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - 25 - 1 - read-only - - - EFF - Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 24 - 1 - read-only - - - EFPI - Event FIFO Put Index -Tx Event FIFO write index pointer, range 0 to 31. - 16 - 5 - read-only - - - EFGI - Event FIFO Get Index -Tx Event FIFO read index pointer, range 0 to 31. - 8 - 5 - read-only - - - EFFL - Event FIFO Fill Level -Number of elements stored in Tx Event FIFO, range 0 to 32. - 0 - 6 - read-only - - - - - TXEFA - tx event fifo acknowledge - 0xf8 - 32 - 0x00000000 - 0x0000001F - - - EFAI - Event FIFO Acknowledge Index -After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get -Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - 0 - 5 - read-write - - - - - 16 - 0x4 - TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 - TS_SEL[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - TS - Timestamp Word TS -default can save 16 timestamps with 32bit; -if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - 0 - 32 - read-only - - - - - CREL - core release register - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - REL - Core Release -One digit, BCD-coded - 28 - 4 - read-only - - - STEP - Step of Core Release -One digit, BCD-coded. - 24 - 4 - read-only - - - SUBSTEP - Sub-step of Core Release -One digit, BCD-coded - 20 - 4 - read-only - - - YEAR - Timestamp Year -One digit, BCD-coded. This field is set by generic parameter on -synthesis. - 16 - 4 - read-only - - - MON - Timestamp Month -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 8 - 8 - read-only - - - DAY - Timestamp Day -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 0 - 8 - read-only - - - - - TSCFG - timestamp configuration - 0x244 - 32 - 0x00000000 - 0x0000FF0F - - - TBPRE - Timebase Prescaler -0x00 to 0xFF -The value by which the oscillator frequency is divided for -generating the timebase counter clock. Valid values for the -Timebase Prescaler are 0 to 255. The actual interpretation by -the hardware of this value is such that one more than the value -programmed here is used. Affects only the TSU internal -timebase. When the internal timebase is excluded by synthesis, -TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not -used. - 8 - 8 - read-write - - - EN64 - set to use 64bit timestamp. -when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. -TSP can be used to select different one - 3 - 1 - read-write - - - SCP - Select Capturing Position -0: Capture Timestamp at EOF -1: Capture Timestamp at SOF - 2 - 1 - read-write - - - TBCS - Timebase Counter Select -When the internal timebase is excluded by synthesis, TBCS is -fixed to ‘1’. -0: Timestamp value captured from internal timebase counter, - ATB.TB[31:0] is the internal timbase counter -1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - 1 - 1 - read-write - - - TSUE - Timestamp Unit Enable -0: TSU disabled -1: TSU enabled - 0 - 1 - read-write - - - - - TSS1 - timestamp status1 - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSL - Timestamp Lost -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. -Reading a Timestamp register resets the related bit. - 16 - 16 - read-only - - - TSN - Timestamp New -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related -Timestamp register. Reading a Timestamp register resets the related bit. - 0 - 16 - read-only - - - - - TSS2 - timestamp status2 - 0x24c - 32 - 0x00000000 - 0x0000000F - - - TSP - Timestamp Pointer -The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 -depending on number_ts_g), it is incremented to 0. -Value also signalled on output m_can_tsp[3:0]. - 0 - 4 - read-only - - - - - ATB - actual timebase - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - TB - timebase for timestamp generation 31-0 - 0 - 32 - read-only - - - - - ATBH - actual timebase high - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBH - timebase for timestamp generation 63-32 - 0 - 32 - read-only - - - - - GLB_CTL - global control - 0x400 - 32 - 0x00000000 - 0xE0000003 - - - M_CAN_STBY - m_can standby control - 31 - 1 - read-write - - - STBY_CLR_EN - m_can standby clear control -0:controlled by software by standby bit[bit31] -1:auto clear standby by hardware when rx data is 0 - 30 - 1 - read-write - - - STBY_POL - standby polarity selection - 29 - 1 - read-write - - - TSU_TBIN_SEL - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - 0 - 2 - read-write - - - - - GLB_STATUS - global status - 0x404 - 32 - 0x00000000 - 0x0000000C - - - M_CAN_INT1 - m_can interrupt status1 - 3 - 1 - read-only - - - M_CAN_INT0 - m_can interrupt status0 - 2 - 1 - read-only - - - - - 640 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,257,258,259,260,261,262,263,264,265,266,267,268,269,270,271,272,273,274,275,276,277,278,279,280,281,282,283,284,285,286,287,288,289,290,291,292,293,294,295,296,297,298,299,300,301,302,303,304,305,306,307,308,309,310,311,312,313,314,315,316,317,318,319,320,321,322,323,324,325,326,327,328,329,330,331,332,333,334,335,336,337,338,339,340,341,342,343,344,345,346,347,348,349,350,351,352,353,354,355,356,357,358,359,360,361,362,363,364,365,366,367,368,369,370,371,372,373,374,375,376,377,378,379,380,381,382,383,384,385,386,387,388,389,390,391,392,393,394,395,396,397,398,399,400,401,402,403,404,405,406,407,408,409,410,411,412,413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452,453,454,455,456,457,458,459,460,461,462,463,464,465,466,467,468,469,470,471,472,473,474,475,476,477,478,479,480,481,482,483,484,485,486,487,488,489,490,491,492,493,494,495,496,497,498,499,500,501,502,503,504,505,506,507,508,509,510,511,512,513,514,515,516,517,518,519,520,521,522,523,524,525,526,527,528,529,530,531,532,533,534,535,536,537,538,539,540,541,542,543,544,545,546,547,548,549,550,551,552,553,554,555,556,557,558,559,560,561,562,563,564,565,566,567,568,569,570,571,572,573,574,575,576,577,578,579,580,581,582,583,584,585,586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,621,622,623,624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639 - MESSAGE_BUFF[%s] - no description available - 0x2000 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - m_can message buffer - 0 - 32 - read-write - - - - - - - MCAN1 - MCAN1 - MCAN - 0xf0284000 - - - MCAN2 - MCAN2 - MCAN - 0xf0288000 - - - MCAN3 - MCAN3 - MCAN - 0xf028c000 - - - MCAN4 - MCAN4 - MCAN - 0xf0290000 - - - MCAN5 - MCAN5 - MCAN - 0xf0294000 - - - MCAN6 - MCAN6 - MCAN - 0xf0298000 - - - MCAN7 - MCAN7 - MCAN - 0xf029c000 - - - PTPC - PTPC - PTPC - 0xf02fc000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - LCDC - LCDC - LCDC - 0xf1000000 - - 0x0 - 0x404 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFF3E01F - - - SW_RST - Software reset, high active. When write 1 ,all internal logical will be reset. -0b - No action -1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - 31 - 1 - read-write - - - DISP_ON - Display panel On/Off mode. -0b - Display Off. -1b - Display On. -Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. -So a good procedure to stop and turn on the display is: -1) clr VS_BLANK status -2) assert software reset -3) de-assert software reset -4) set display off -5) check VS_BLANK status until it is asserted, -6)reset the module, change settings -7) set display on - 30 - 1 - read-write - - - LINE_PATTERN - LCDIF line output order. -000b - RGB. -001b - RBG. -010b - GBR. -011b - GRB. -100b - BRG. -101b - BGR. - 27 - 3 - read-write - - - DISP_MODE - LCDIF operating mode. -00b - Normal mode. Panel content controlled by layer configuration. -01b - Test Mode1.(BGND Color Display) -10b - Test Mode2.(Column Color Bar) -11b - Test Mode3.(Row Color Bar) - 25 - 2 - read-write - - - BGDCL4CLR - background color for clear mode when the alpha channel is 0 - 24 - 1 - read-write - - - ARQOS - ARQOS for bus fabric arbitration - 20 - 4 - read-write - - - SHADOW_OP - Shadow Option -1: Use physical VSYNC (ST[VS_BLANK]) as shadow time. -0: Use layer internal logic VSYNC as shadow time. In general, this type of shadow control will have longer memory read time, so less underflow risk. - 17 - 1 - read-write - - - B_LE_MODE - Endianness mode for Blue Color Pads -1: Little endian. Pad 0 --> Color LSB 0 -0: Big Endian. Pad 0--> Color MSB 7 - 16 - 1 - read-write - - - G_LE_MODE - Endianness mode for Green Color Pads -1: Little endian. Pad 0 --> Color LSB 0 -0: Big Endian. Pad 0--> Color MSB 7 - 15 - 1 - read-write - - - R_LE_MODE - Endianness mode for Red Color Pads -1: Little endian. Pad 0 --> Color LSB 0 -0: Big Endian. Pad 0--> Color MSB 7 - 14 - 1 - read-write - - - CAM_SYNC_EN - Enable the VSYNC synchronization of CAM and LCDC - 13 - 1 - read-write - - - INV_PXDATA - Indicates if value at the output (pixel data output) needs to be negated. -0b - Output is to remain same as the data inside memory -1b - Output to be negated from the data inside memory - 4 - 1 - read-write - - - INV_PXCLK - Polarity change of Pixel Clock. -0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge -1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - 3 - 1 - read-write - - - INV_HREF - Polarity of HREF -0b - HREF signal active HIGH, indicating active pixel data -1b - HREF signal active LOW - 2 - 1 - read-write - - - INV_VSYNC - Polarity of VSYNC -0b - VSYNC signal active HIGH -1b - VSYNC signal active LOW - 1 - 1 - read-write - - - INV_HSYNC - Polarity of HSYNC -0b - HSYNC signal active HIGH -1b - HSYNC signal active LOW - 0 - 1 - read-write - - - - - BGND_CL - Background Color Register - 0x4 - 32 - 0x00000000 - 0x00FFFFFF - - - R - Red component of the default color displayed in the sectors where no layer is active. - 16 - 8 - read-write - - - G - Green component of the default color displayed in the sectors where no layer is active. - 8 - 8 - read-write - - - B - Blue component of the default color displayed in the sectors where no layer is active. - 0 - 8 - read-write - - - - - DISP_WN_SIZE - Display Window Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - Sets the display size vertical resolution in pixels. - 16 - 12 - read-write - - - X - Sets the display size horizontal resolution in pixels. - 0 - 12 - read-write - - - - - HSYNC_PARA - HSYNC Config Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - 22 - 9 - read-write - - - BP - HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - 11 - 9 - read-write - - - PW - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - VSYNC_PARA - VSYNC Config Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FP - VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - 22 - 9 - read-write - - - BP - VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - 11 - 9 - read-write - - - PW - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - 0 - 9 - read-write - - - - - DMA_ST - DMA Status Register - 0x14 - 32 - 0x00000000 - 0xFFFFFF00 - - - DMA_ERR - plane n axi error. W1C. - 24 - 8 - write-only - - - DMA1_DONE - Plane n frame 1 dma done. W1C. - 16 - 8 - write-only - - - DMA0_DONE - Plane n frame 0 dma done. W1C. - 8 - 8 - write-only - - - - - ST - Status Register - 0x18 - 32 - 0x00000000 - 0x000001FF - - - P1_HANDSHAKE_ABORT - Plane 1 handshake abort error. W1C - 8 - 1 - write-only - - - P0_HANDSHAKE_ABORT - Plane 0 handshake abort error. W1C - 7 - 1 - write-only - - - CAM_HCNT_FAIL - During cam_vsync mode, sync fail due to hcnt out of acceptable ranges. W1C - 6 - 1 - write-only - - - CAM_VSYNC_FAIL - During cam_vsync mode, sync fail due to out of vsync parameters. W1C - 5 - 1 - write-only - - - SHADOW_DONE - Shadow done status. This is an OR-ed signals of all shadow_done signals of all planes, and it can only be cleared by writing 1 for all asserted bits in SHADOW_DONE_ST register. - 4 - 1 - read-only - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - write-only - - - VS_BLANK - Asserted when in vertical blanking period. At the start of VSYNC - 2 - 1 - write-only - - - UNDERRUN - Asserted when the output buffer underrun condition encountered - 1 - 1 - write-only - - - VSYNC - Asserted when in vertical blanking period. At the end of VSYNC - 0 - 1 - write-only - - - - - INT_EN - Interrupt Enable Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - DMA_ERR - Interrupt enable for DMA error - 24 - 8 - read-write - - - DMA_DONE - Interrupt enable for DMA done - 16 - 8 - read-write - - - HANDSHAKE_ABORT - Handshake abort error int enable - 7 - 1 - read-write - - - CAM_HCNT_FAIL - hcnt out of acceptable ranges interrupt enable - 6 - 1 - read-write - - - CAM_VSYNC_FAIL - cam_vsync fail interrupt enable - 5 - 1 - read-write - - - SHADOW_DONE - Shadow done interrupt enable - 4 - 1 - read-write - - - URGENT_UNDERRUN - Asserted when the output buffer urgent underrun condition encountered - 3 - 1 - read-write - - - VS_BLANK - Interrupt enable for start of sof - 2 - 1 - read-write - - - UNDERRUN - Interrupt enable for underrun - 1 - 1 - read-write - - - VSYNC - Interrupt enable for end of sof - 0 - 1 - read-write - - - - - TXFIFO - TX FIFO Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRSH - Threshold to start the lcd raster (0--0x7F) - 0 - 8 - read-write - - - - - CTRL_BP_V_RANGE - BP_V range for CAMSYNC mode - 0x24 - 32 - 0x00000000 - 0x07FFFFFF - - - MAX - Maximal BP_V values - 18 - 9 - read-write - - - BEST - Best BP_V values - 9 - 9 - read-write - - - MIN - Minimal BP_V values - 0 - 9 - read-write - - - - - CTRL_PW_V_RANGE - PW_V range for CAMSYNC mode - 0x28 - 32 - 0x00000000 - 0x07FFFFFF - - - MAX - Maximal PW_V values - 18 - 9 - read-write - - - BEST - Best PW_V values - 9 - 9 - read-write - - - MIN - Minimal PW_V values - 0 - 9 - read-write - - - - - CTRL_FP_V_RANGE - FP_V range for CAMSYNC mode - 0x2c - 32 - 0x00000000 - 0x07FFFFFF - - - MAX - Maximal FP_V values - 18 - 9 - read-write - - - BEST - Best FP_V values - 9 - 9 - read-write - - - MIN - Minimal FP_V values - 0 - 9 - read-write - - - - - CAM_SYNC_HCNT_MIN - min HCNT value for CAMSYNC mode - 0x30 - 32 - 0x00000000 - 0x0000FFFF - - - VAL - minimal acceptable HCNT Value - 0 - 16 - read-write - - - - - CAM_SYNC_HCNT_BEST - best HCNT value for CAMSYNC mode - 0x34 - 32 - 0x00000000 - 0x00FFFFFF - - - HYST - hysteresys of acceptable HCNT Value - 16 - 8 - read-write - - - VAL - best acceptable HCNT Value - 0 - 16 - read-write - - - - - CAM_SYNC_HCNT_MAX - max HCNT value for CAMSYNC mode - 0x38 - 32 - 0x00000000 - 0x0000FFFF - - - VAL - maximal acceptable HCNT Value - 0 - 16 - read-write - - - - - CAM_SYNC_HCNT_ST - current HCNT value for CAMSYNC mode - 0x3c - 32 - 0x00000000 - 0x0000FFFF - - - VAL - current HCNT value - 0 - 16 - read-only - - - - - SHADOW_DONE_ST - Shadow done status - 0x40 - 32 - 0x00000000 - 0x000000FF - - - VAL - current shadow_done value for plane 7,...,0 respectively - 0 - 8 - write-only - - - - - SHADOW_DONE_INT_EN - Shadow done interrupt enable - 0x44 - 32 - 0x00000000 - 0x000000FF - - - VAL - shadow_done interrupt enable for plane 7,...,0 respectively - 0 - 8 - read-write - - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - LAYER[%s] - no description available - 0x200 - - LAYCTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFD - - - RESAMPLE_VRATIO - Resample the input data stream in the verticle direction -0: don't resample -positive n: upsample-by-n+1 (2 to 8) -negtive n: downsample-by-n+1 (2 to 8) - 28 - 4 - read-write - - - RESAMPLE_HRATIO - Resample the input data stream in the horizontal direction -0: don't resample -positive n: upsample-by-n+1 (2 to 8) -negtive n: downsample-by-n+1 (2 to 8) - 24 - 4 - read-write - - - NORMLZ_OUT - Normalize the pixel out for the not-overlapped pixels - 23 - 1 - read-write - - - HANDSHAKE_ABORT_INT_EN - 1: Enable the handshake abort error interrupt. -0: don't Enable the handshake abort error interrupt. -Abort is generated when the LCDC is going to switch bank to a new bank, and the new bank data is not ready yet. -Abort is only useful when communicating with the offline calculator (such as PDMA as the active pixel generator mode). -PDMA as the active generator mode, means it is the first pixel generator with data sources from offline memory, and not from on-the-fly streaming data (such as camera captured data). -While with on-the-fly streaming data, error condition is indicated by display buffer underflow. - 22 - 1 - read-write - - - HANDSHAKE_BUFSIZE - 1: handshake buffer is 16 rows hight per ping or pang buf. -0: handshake buffer is 8 rows hight per ping or pang buf. - 21 - 1 - read-write - - - ENABLE_HANDSHAKE - Enable handshake with input pixel controller. When this is set, the LCDC will not process an entire framebuffer, -but will instead process rows of NxN blocks in a double-buffer handshake with the input pixel controlller. This enables -the use of the onboard SRAM for a partial frame buffer. Only valid for Plane 0 & 1. -1: handshake enabled -0: handshake disabled - 20 - 1 - read-write - - - PACK_DIR - The byte sequence of the 4 bytes in a 32-bit word. -1: {A0, A1, A2, A3} byte re-ordered. -0: {A3, A2, A1, A0} the normal case with no byte re-order - 19 - 1 - read-write - - - SHADOW_LOAD_EN - Shadow Load Enable -The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - 16 - 1 - read-write - - - YUV_FORMAT - The YUV422 input format selection. -00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 -01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 -10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 -11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 -If not YUV422 mode, -FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) -FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - 14 - 2 - read-write - - - PIXFORMAT - Layer encoding format (bit per pixel) -0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. -0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. -0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. -0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. -0100b - 16 bpp (RGB565), the low byte contains the full R component. -0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] -1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A -1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - 10 - 4 - read-write - - - LOCALPHA_OP - The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream -1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) -2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream -Others: Reserved - 8 - 2 - read-write - - - INALPHA_OP - The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline -1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) -2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline -Others: Reserved - 6 - 2 - read-write - - - AB_MODE - Alpha Blending Mode -0: SKBlendMode_Clear; -3: SKBlendMode_SrcOver -14: SRC org -15: DST org -Others: Reserved. - 2 - 4 - read-write - - - EN - Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - 0 - 1 - read-write - - - - - ALPHAS - Layer Alpha Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCD - The system alpha value for the data stream of current layer stream (SRC) - 8 - 8 - read-write - - - IND - The system alpha value for the input stream from previous stage (DST) - 0 - 8 - read-write - - - - - LAYSIZE - Layer Size Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Height of the layer in pixels - 16 - 12 - read-write - - - WIDTH - Width of the layer in pixels (Note: not actual width-1) -The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - 0 - 12 - read-write - - - - - LAYPOS - Layer Position Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - Y - The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - 16 - 16 - read-write - - - X - The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - 0 - 16 - read-write - - - - - START0 - Layer Buffer Pointer Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR0 - Input buffer Start address 0 - 0 - 32 - read-write - - - - - LINECFG - Layer Bus Config Register - 0x18 - 32 - 0x00000000 - 0xE0FFFFFF - - - MPT_SIZE - Maximal Per Transfer Data Size: -0: 64 bytes -1: 128 bytes -2: 256 bytes -3: 512 bytes -4: 1024 bytes - 29 - 3 - read-write - - - MAX_OT - the number of outstanding axi read transactions. -If zero, it means max 8. - 21 - 3 - read-write - - - PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. - 0 - 16 - read-write - - - - - BG_CL - Layer Background Color Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGB - ARGB8888. It is only useful in the last active stage in the pipeline. - 0 - 32 - read-write - - - - - CSC_COEF0 - Layer Color Space Conversion Config Register 0 - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit in the LCDC plane data path. -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data -This bit will be shadowed. - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Layer Color Space Conversion Config Register 1 - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Layer Color Space Conversion Config Register 2 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - - CLUT_LOAD - Clut Load Control Register - 0x400 - 32 - 0x00000000 - 0x8000007F - - - STR_HIGH - 1'b1: Store 8+ CLUT tables through APB -1'b0: Store 0-7 CLUT tables through APB - 31 - 1 - read-write - - - SEL_NUM - Selected CLUT Number -The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. -. 3'h0 - PLANE 0 -. 3'h1 - PLANE 1 -. ------ -. 3'h7 - PLANE 7 -CLUT 8 can be modified via APB even when display is on. -Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - 4 - 3 - read-write - - - UPDATE_EN - CLUT Update Enable -The bit is written to 1 when software want to update the Color Look Up Tables during display. -If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. -If set to 0, software can update CLUT8 directly according to the CLUT memory map. -Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - 0 - 1 - read-write - - - - - - - LCDC1 - LCDC1 - LCDC - 0xf1004000 - - - CAM0 - CAM0 - CAM - 0xf1008000 - - 0x0 - 0x4b0 - registers - - - - CR1 - Control Register - 0x0 - 32 - 0x00000000 - 0xFF9AAFFF - - - INV_DEN - invert den pad input before it is used - 30 - 1 - read-write - - - COLOR_EXT - If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. -The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - 29 - 1 - read-write - - - INV_PIXCLK - invert pixclk pad input before it is used - 28 - 1 - read-write - - - INV_HSYNC - invert hsync pad input before it is used - 27 - 1 - read-write - - - INV_VSYNC - invert vsync pad input before it is used - 26 - 1 - read-write - - - SWAP16_EN - SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. -NOTE: Example of swapping enabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x 33441122 -NOTE: Example of swapping disabled: -Data input to FIFO = 0x11223344 -Data in RX FIFO = 0x11223344 -0 Disable swapping -1 Enable swapping - 25 - 1 - read-write - - - PACK_DIR - Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. -0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. -1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - 24 - 1 - read-write - - - RESTART_BUSPTR - force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - 23 - 1 - read-write - - - ASYNC_RXFIFO_CLR - ASynchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO immediately. -It will be auto-cleared. - 20 - 1 - read-write - - - SYNC_RXFIFO_CLR - Synchronous Rx FIFO Clear. -When asserted, this bit clears RXFIFO on every SOF. - 19 - 1 - read-write - - - SOF_INT_POL - SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. -0 SOF interrupt is generated on SOF falling edge -1 SOF interrupt is generated on SOF rising edge - 17 - 1 - read-write - - - INV_DATA - Invert Data Input. This bit enables or disables internal inverters on the data lines. -0 CAM_D data lines are directly applied to internal circuitry -1 CAM_D data lines are inverted before applied to internal circuitry - 15 - 1 - read-write - - - STORAGE_MODE - 00: Normal Mode (one plane mode) -01: Two Plane Mode (Y, UV plane) -10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 -11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - 10 - 2 - read-write - - - COLOR_FORMATS - input color formats: -0010b:24bit:RGB888 -0011b:24bit:RGB666 -0100b:16bit:RGB565 -0101b:16bit:RGB444 -0110b:16bit:RGB555 -0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) -YUV -YCrCb -Note: YUV420 is not supported. -1000b: 24bit: YUV444 - 3 - 4 - read-write - - - SENSOR_BIT_WIDTH - the bit width of the sensor -0: 8 bits -1: 10 bits -3:24bits -Others: Undefined - 0 - 3 - read-write - - - - - INT_EN - Interrupt Enable Register - 0x4 - 32 - 0x00000000 - 0xFFFFFF5F - - - ERR_CL_BWID_CFG_INT_EN - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - 13 - 1 - read-write - - - HIST_DONE_INT_EN - Enable hist done int - 12 - 1 - read-write - - - HRESP_ERR_EN - Hresponse Error Enable. This bit enables the hresponse error interrupt. -0 Disable hresponse error interrupt -1 Enable hresponse error interrupt - 11 - 1 - read-write - - - EOF_INT_EN - End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. -0 EOF interrupt is disabled. -1 EOF interrupt is generated when RX count value is reached. - 9 - 1 - read-write - - - RF_OR_INTEN - RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. -0 RxFIFO overrun interrupt is disabled -1 RxFIFO overrun interrupt is enabled - 6 - 1 - read-write - - - FB2_DMA_DONE_INTEN - Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA -transfer done. -0 Frame Buffer2 DMA Transfer Done interrupt disable -1 Frame Buffer2 DMA Transfer Done interrupt enable - 3 - 1 - read-write - - - FB1_DMA_DONE_INTEN - Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA -transfer done. -0 Frame Buffer1 DMA Transfer Done interrupt disable -1 Frame Buffer1 DMA Transfer Done interrupt enable - 2 - 1 - read-write - - - SOF_INT_EN - Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. -0 SOF interrupt disable -1 SOF interrupt enable - 0 - 1 - read-write - - - - - CR2 - Control 2 Register - 0x10 - 32 - 0x00000000 - 0xFFFF8FEF - - - FRMCNT_15_0 - Frame Counter. This is a 16-bit Frame Counter -(Wraps around automatically after reaching the maximum) - 16 - 16 - read-only - - - FRMCNT_RST - Frame Count Reset. Resets the Frame Counter. -0 Do not reset -1 Reset frame counter immediately - 15 - 1 - read-write - - - RXFF_LEVEL - RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. -000 4 Double words -001 8 Double words -010 16 Double words -011 24 Double words -100 32 Double words -101 48 Double words -110 64 Double words -111 96 Double words - 9 - 3 - read-write - - - DMA_REQ_EN_RFF - DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. -0 Disable the dma request -1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - 5 - 1 - read-write - - - CLRBITFORMAT - Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - 0 - 4 - read-write - - - - - STA - Status Register - 0x24 - 32 - 0x00000000 - 0xFFFFA7FC - - - ERR_CL_BWID_CFG - The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - 19 - 1 - write-only - - - HIST_DONE - hist cal done - 18 - 1 - write-only - - - RF_OR_INT - RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing -1) -0 RXFIFO has not overflowed. -1 RXFIFO has overflowed. - 13 - 1 - write-only - - - DMA_TSF_DONE_FB2 - DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 10 - 1 - write-only - - - DMA_TSF_DONE_FB1 - DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) -0 DMA transfer is not completed. -1 DMA transfer is completed. - 9 - 1 - write-only - - - EOF_INT - End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) -0 EOF is not detected. -1 EOF is detected. - 7 - 1 - write-only - - - SOF_INT - Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) -0 SOF is not detected. -1 SOF is detected. - 6 - 1 - write-only - - - HRESP_ERR_INT - Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing -1) -0 No hresponse error. -1 Hresponse error is detected. - 2 - 1 - write-only - - - - - DMASA_FB1 - Pixel DMA Frame Buffer 1 Address - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer1 - 2 - 30 - read-write - - - - - DMASA_FB2 - Pixel DMA Frame Buffer 2 Address - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. -In Two-Plane Mode, Y buffer2 - 2 - 30 - read-write - - - - - BUF_PARA - Buffer Parameters Register - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINEBSP_STRIDE - Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. -The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - 0 - 16 - read-write - - - - - IDEAL_WN_SIZE - Ideal Image Size Register - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - HEIGHT - Image Height. Indicates how many active pixels in a column of the image from the sensor. - 16 - 16 - read-write - - - WIDTH - Image Width. Indicates how many active pixels in a line of the image from the sensor. -The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. -As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - 0 - 16 - read-write - - - - - CR18 - Control CR18 Register - 0x4c - 32 - 0x00000000 - 0xFFFFE7BF - - - CAM_ENABLE - CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - 31 - 1 - read-write - - - AWQOS - AWQOS for bus fabric arbitration - 7 - 4 - read-write - - - - - DMASA_UV1 - Pixel UV DMA Frame Buffer 1 Address - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 1 - 2 - 30 - read-write - - - - - DMASA_UV2 - Pixel UV DMA Frame Buffer 2 Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR - Two Plane UV Buffer Start Address 2 - 2 - 30 - read-write - - - - - CR20 - Control CR20 Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - BINARY_EN - binary picture output enable - 31 - 1 - read-write - - - HISTOGRAM_EN - histogarm enable - 30 - 1 - read-write - - - BIG_END - Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - 8 - 1 - read-write - - - THRESHOLD - Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - 0 - 8 - read-write - - - - - CSC_COEF0 - Color Space Conversion Config Register 0 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit -0b - The CSC is bypassed and the input pixels are RGB data already -1b - The CSC is enabled and the pixels will be converted to RGB data - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - Color Space Conversion Config Register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - Color Space Conversion Config Register 2 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - CLRKEY_LOW - Low Color Key Register - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - High Color Key Register - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - 256 - 0x4 - DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23,DATA24,DATA25,DATA26,DATA27,DATA28,DATA29,DATA30,DATA31,DATA32,DATA33,DATA34,DATA35,DATA36,DATA37,DATA38,DATA39,DATA40,DATA41,DATA42,DATA43,DATA44,DATA45,DATA46,DATA47,DATA48,DATA49,DATA50,DATA51,DATA52,DATA53,DATA54,DATA55,DATA56,DATA57,DATA58,DATA59,DATA60,DATA61,DATA62,DATA63,DATA64,DATA65,DATA66,DATA67,DATA68,DATA69,DATA70,DATA71,DATA72,DATA73,DATA74,DATA75,DATA76,DATA77,DATA78,DATA79,DATA80,DATA81,DATA82,DATA83,DATA84,DATA85,DATA86,DATA87,DATA88,DATA89,DATA90,DATA91,DATA92,DATA93,DATA94,DATA95,DATA96,DATA97,DATA98,DATA99,DATA100,DATA101,DATA102,DATA103,DATA104,DATA105,DATA106,DATA107,DATA108,DATA109,DATA110,DATA111,DATA112,DATA113,DATA114,DATA115,DATA116,DATA117,DATA118,DATA119,DATA120,DATA121,DATA122,DATA123,DATA124,DATA125,DATA126,DATA127,DATA128,DATA129,DATA130,DATA131,DATA132,DATA133,DATA134,DATA135,DATA136,DATA137,DATA138,DATA139,DATA140,DATA141,DATA142,DATA143,DATA144,DATA145,DATA146,DATA147,DATA148,DATA149,DATA150,DATA151,DATA152,DATA153,DATA154,DATA155,DATA156,DATA157,DATA158,DATA159,DATA160,DATA161,DATA162,DATA163,DATA164,DATA165,DATA166,DATA167,DATA168,DATA169,DATA170,DATA171,DATA172,DATA173,DATA174,DATA175,DATA176,DATA177,DATA178,DATA179,DATA180,DATA181,DATA182,DATA183,DATA184,DATA185,DATA186,DATA187,DATA188,DATA189,DATA190,DATA191,DATA192,DATA193,DATA194,DATA195,DATA196,DATA197,DATA198,DATA199,DATA200,DATA201,DATA202,DATA203,DATA204,DATA205,DATA206,DATA207,DATA208,DATA209,DATA210,DATA211,DATA212,DATA213,DATA214,DATA215,DATA216,DATA217,DATA218,DATA219,DATA220,DATA221,DATA222,DATA223,DATA224,DATA225,DATA226,DATA227,DATA228,DATA229,DATA230,DATA231,DATA232,DATA233,DATA234,DATA235,DATA236,DATA237,DATA238,DATA239,DATA240,DATA241,DATA242,DATA243,DATA244,DATA245,DATA246,DATA247,DATA248,DATA249,DATA250,DATA251,DATA252,DATA253,DATA254,DATA255 - HISTOGRAM_FIFO[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - HIST_Y - the appearance of bin x (x=(address-DATA0)/4) - 0 - 24 - read-only - - - - - ROI_WIDTH - Roi Width Config Register - 0x490 - 32 - 0x00000000 - 0xFFFFFFFF - - - ROI_WIDTH_END - end address of width for roi - 16 - 16 - read-write - - - ROI_WIDTH_START - start address of width for roi - 0 - 16 - read-write - - - - - ROI_HEIGHT - Roi Width Config Register - 0x494 - 32 - 0x00000000 - 0xFFFFFFFF - - - ROI_HEIGHT_END - end address of height for roi - 16 - 16 - read-write - - - ROI_HEIGHT_START - start address of height for roi - 0 - 16 - read-write - - - - - PRO_CTRL - Pro Config Register - 0x498 - 32 - 0x00000000 - 0xFFFF40FF - - - ERR_INJECT - 0 generate alarm in normal mode -1 force to generate fatal alarm - 14 - 1 - read-write - - - ROI_UPDATE - roi configration update - 7 - 1 - read-write - - - SCALE_UPDATE - scale configration update - 6 - 1 - read-write - - - SCALE_HEIGHT_SELECT - 000 keep all pixel for height -001 keep 1 for every 2 pixel for height -010 keep 1 for every 3 pixel for height -011 keep 1 for every 4 pixel for height -100 keep 1 for every 5 pixel for height -101 keep 1 for every 6 pixel for height -110 keep 1 for every 7 pixel for height -111 keep 1 for every 8 pixel for height - 3 - 3 - read-write - - - SCALE_WIDTH_SELECT - 000 keep all pixel for width -001 keep 1 for every 2 pixel for width -010 keep 1 for every 3 pixel for width -011 keep 1 for every 4 pixel for width -100 keep 1 for every 5 pixel for width -101 keep 1 for every 6 pixel for width -110 keep 1 for every 7 pixel for width -111 keep 1 for every 8 pixel for width - 0 - 3 - read-write - - - - - ACT_SIZE - actual size - 0x49c - 32 - 0x00000000 - 0xFFFFFFFF - - - ACT_HEIGHT - actual height after scale and/or roi - 16 - 16 - read-write - - - ACT_WIDTH - actual width after scale and/or roi - 0 - 16 - read-write - - - - - VSYNC_VALID_CNT - vsync valid counter - 0x4a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VSYNC_VALID_CNT - vsync valid counter - 0 - 32 - read-write - - - - - HSYNC_VALID_CNT - hsync valid counter - 0x4a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - HSYNC_VALID_CNT - hsync valid counter - 0 - 32 - read-write - - - - - VALID_MARGIN - valid margin - 0x4a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HSYNC_VALID_MARGIN - hsync valid margin - 16 - 16 - read-write - - - VSYNC_VALID_MARGIN - vsync valid margin - 0 - 16 - read-write - - - - - ALARM_SET - alarm set - 0x4ac - 32 - 0x00000000 - 0xFFFFFFFF - - - SIG_NORMAL - define signal duty cycles(base clock) -0x0: disable signal -0x1: high 1, low 15 -0x2: high 2, low 14 -…... -0xF: high 15, low 1 - 20 - 4 - read-write - - - FATAL_NORMAL - define signal duty cycles(base clock) -0x0: disable signal -0x1: high 1, low 15 -0x2: high 2, low 14 -…... -0xF: high 15, low 1 - 16 - 4 - read-write - - - PRE_DIV - frequency division - 0 - 16 - read-write - - - - - - - CAM1 - CAM1 - CAM - 0xf100c000 - - - PDMA - PDMA - PDMA - 0xf1010000 - - 0x0 - 0xc0 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARQOS - QoS for AXI read bus - 19 - 4 - read-write - - - AWQOS - QoS for AXI write bus - 15 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 13 - 2 - read-write - - - AXIERR_IRQ_EN - Enable interrupt of AXI bus error - 12 - 1 - read-write - - - PDMA_DONE_IRQ_EN - Enable interrupt of PDMA_DONE - 11 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - IRQ_EN - Enable normal interrupt - 6 - 1 - read-write - - - BS16 - Asserted when the Block Size is 16x16, else 8x8 - 5 - 1 - read-write - - - P1_EN - Plane 1 Enable - 4 - 1 - read-write - - - P0_EN - Plane 0 Enable - 3 - 1 - read-write - - - PDMA_SFTRST - Software Reset. -Write 1 to clear PDMA internal logic. -Write 0 to exit software reset mode. - 1 - 1 - read-write - - - PDMA_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKY - Y block that is processing - 24 - 8 - read-only - - - BLOCKX - X block that is processing - 16 - 8 - read-only - - - PDMA_DONE - PDMA one image done - 9 - 1 - write-only - - - AXI_ERR_ID - AXI error ID - 5 - 4 - read-only - - - AXI_0_WRITE_ERR - AXI0 write err - 4 - 1 - write-only - - - AXI_1_READ_ERR - AXI1 read err - 3 - 1 - write-only - - - AXI_0_READ_ERR - AXI0 read err - 2 - 1 - write-only - - - IRQ - Asserted to indicate a IRQ event - 0 - 1 - read-only - - - - - OUT_CTRL - Out Layer Control Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFBF - - - DSTALPHA - The destination (P1) system ALPHA value. - 24 - 8 - read-write - - - SRCALPHA - The source (P0) system ALPHA value. - 16 - 8 - read-write - - - DSTALPHA_OP - The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) -2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream -3: don't multiply the color data with any alpha values for blender inputs. - 14 - 2 - read-write - - - SRCALPHA_OP - The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) -0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream -1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) -2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream -3: don't multiply the color data with any alpha values for blender inputs. - 12 - 2 - read-write - - - ABLEND_MODE - Alpha Blending Mode -0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); -1: SKBlendMode_Src ; -2: SKBlendMode_Dst -3: SKBlendMode_SrcOver -4: SKBlendMode_DstOver -5: SKBlendMode_SrcIn -6: SKBlendMode_DstIn -7: SKBlendMode_SrcOut -8: SKBlendMode_DstOut -9: SKBlendMode_SrcATop -10: SKBlendMode_DstATop -11: SKBlendMode_Xor -12: SKBlendMode_Plus (The conventional belding mode) -13: SKBlendMode_Modulate -14: SRC org -15: DST org -Others: Reserved. - 8 - 4 - read-write - - - NORM_OUT - Asserted to normalize the output color channels with alpha channels - 7 - 1 - read-write - - - FORMAT - Output buffer format. -0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - 0 - 6 - read-write - - - - - OUT_BUF - Output buffer address - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - 0 - 32 - read-write - - - - - OUT_PITCH - Outlayer Pitch Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - OUT_LRC - Output Lower Right Corner Register - 0x18 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. -The value is the height of the output image size. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. -Should be the width of the output image size. - 0 - 14 - read-write - - - - - 2 - 0x8 - 0,1 - OUT_PS[%s] - no description available - 0x1c - - ULC - Layer Upper Left Corner Register - 0x0 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - LRC - Layer Lower Right Corner Register - 0x4 - 32 - 0x00000000 - 0x3FFF3FFF - - - Y - This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - 16 - 14 - read-write - - - X - This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - 0 - 14 - read-write - - - - - - 2 - 0x30 - 0,1 - PS[%s] - no description available - 0x30 - - CTRL - Layer Control Register - 0x0 - 32 - 0x00000000 - 0x011FFFFF - - - PL_ONLY_BLENDOP - 1: For those pixels that are this plane-only, use the colcor values and alpha values directly as blender output for un-normalized outputs configurations. -0: For those pixels that are this plane-only, the operations are determined by other operation configurations. - 24 - 1 - read-write - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack_dir operation. - 20 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 18 - 2 - read-write - - - BKGCL4CLR - Enable to use background color for clear area - 17 - 1 - read-write - - - YCBCR_MODE - YCbCr mode or YUV mode - 16 - 1 - read-write - - - BYPASS - Asserted to bypass the CSC stage - 15 - 1 - read-write - - - VFLIP - Indicates that the input should be flipped vertically (effect applied before rotation). - 14 - 1 - read-write - - - HFLIP - Indicates that the input should be flipped horizontally (effect applied before rotation). - 13 - 1 - read-write - - - ROTATE - Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring -after the FLIP_X and FLIP_Y permutation. -0x0 ROT_0 -0x1 ROT_90 -0x2 ROT_180 -0x3 ROT_270 - 11 - 2 - read-write - - - DECY - Verticle pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECY2 - Decimate PS by 2. -0x2 DECY4 - Decimate PS by 4. -0x3 DECY8 - Decimate PS by 8. - 9 - 2 - read-write - - - DECX - Horizontal pre decimation filter control. -0x0 DISABLE - Disable pre-decimation filter. -0x1 DECX2 - Decimate PS by 2. -0x2 DECX4 - Decimate PS by 4. -0x3 DECX8 - Decimate PS by 8. - 7 - 2 - read-write - - - HW_BYTE_SWAP - Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - 6 - 1 - read-write - - - FORMAT - PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. -0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A -0xE RGB565 - 16-bit pixels, byte sequence as B,R -0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - 0 - 6 - read-write - - - - - BUF - Layer data buffer address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Address pointer for the PS RGB or Y (luma) input buffer. - 0 - 32 - read-write - - - - - PITCH - Layer data pitch register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - BYTELEN - Indicates the number of bytes in memory between two vertically adjacent pixels. - 0 - 16 - read-write - - - - - BKGD - Layer background color register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COLOR - Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - 0 - 32 - read-write - - - - - SCALE - Layer scale register - 0x18 - 32 - 0x00000000 - 0x7FFF7FFF - - - Y - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 16 - 15 - read-write - - - X - This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - 0 - 15 - read-write - - - - - OFFSET - Layer offset register - 0x1c - 32 - 0x00000000 - 0x0FFF0FFF - - - Y - This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 16 - 12 - read-write - - - X - This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. -It is applied after the decimation filter stage, and before the bilinear filter stage. - 0 - 12 - read-write - - - - - CLRKEY_LOW - Layer low color key register - 0x20 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - 0 - 24 - read-write - - - - - CLRKEY_HIGH - Layer high color key register - 0x24 - 32 - 0x00000000 - 0x00FFFFFF - - - LIMIT - High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - 0 - 24 - read-write - - - - - ORG - Layer original size register - 0x28 - 32 - 0x00000000 - 0x3FFF3FFF - - - HIGHT - The number of vertical pixels of the original frame (not -1) - 16 - 14 - read-write - - - WIDTH - The number of horizontal pixels of the original frame (not -1) - 0 - 14 - read-write - - - - - - YUV2RGB_COEF0 - YUV2RGB coefficients register 0 - 0xa0 - 32 - 0x00000000 - 0x1FFFFFFF - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - YUV2RGB_COEF1 - YUV2RGB coefficients register 1 - 0xa4 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - YUV2RGB_COEF2 - YUV2RGB coefficients register 2 - 0xa8 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients register 0 - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YUV CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients register 1 - 0xb0 - 32 - 0x00000000 - 0x07FF07FF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients register 2 - 0xb4 - 32 - 0x00000000 - 0x07FF07FF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients register 3 - 0xb8 - 32 - 0x00000000 - 0x07FF07FF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients register 4 - 0xbc - 32 - 0x00000000 - 0x07FF07FF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - - - JPEG - JPEG - JPEG - 0xf1014000 - - 0x0 - 0xa0 - registers - - - - InDMA_MISC - In DMA Misc Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFC - - - ARQOS - QoS for AXI read channel - 19 - 4 - read-write - - - MAX_OT - max_ot when input are RGB pixels. -For 16 bits per pixel, it can be set as 4. -For 32 bits per pixel, it will be set as 2. - 15 - 4 - read-write - - - INB13_SWAP - Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - 14 - 1 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. -2'b00: no change {A3, A2, A1, A0} -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - INDMA_RENEW - Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - 11 - 1 - read-write - - - NXT_IRQ_EN - In DMA Next Interrupt Enable - 10 - 1 - read-write - - - IN_DMA_DONE_IRQ_EN - In DMA Done enable - 9 - 1 - read-write - - - AXI_ERR_IRQ_EN - In DMA axi bus error inetrrupt enable - 8 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of In DMA module - 7 - 1 - read-write - - - IN_DMA_ID - 0: Pixel (In) -1: ECS (In) -2: Qmem -3: HuffEnc -4: HuffMin -5: HuffBase -6: HuffSymb - 4 - 3 - read-write - - - IN_DMA_REQ - Asserted to request DMA. Automatically clear after DMA is done. - 3 - 1 - read-write - - - INDMA2D - Asserted if In_DMA_ID=Pixel. - 2 - 1 - read-write - - - - - InDMABase - In DMA Buf Address - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - InDMA_Ctrl0 - In DMA Buf Control 0 Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - 0 - 16 - read-write - - - - - InDMA_Ctrl1 - In DMA Buf Control 1 Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - INXT_CMD - In DMA Next Command Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - OutDMA_MISC - Out DMA Misc Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFC - - - AWQOS - No description available - 14 - 4 - read-write - - - PACK_DIR - Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. -2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) -2'b01: {A2, A3, A0, A1} -2'b10: {A1, A0, A3, A2} -2'b11: {A0, A1, A2, A3} - 12 - 2 - read-write - - - EN_OUTCNT - Enable output counter (unit as bytes) - 11 - 1 - read-write - - - INI_OUTCNT - Asserted to ini output counter - 10 - 1 - read-write - - - ADD_ODMA_ENDINGS - Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - 9 - 1 - read-write - - - NXT_IRQ_EN - Out DMA Next Interrupt Enable - 8 - 1 - read-write - - - OUT_DMA_DONE_IRQ_EN - Out DMA Done interrupt Enable - 7 - 1 - read-write - - - AXI_ERR_IRQ_EN - Out DMA axi bus error inetrrupt enable - 6 - 1 - read-write - - - IRQ_EN - interrupt enable for all interrupt sources of Out DMA module - 5 - 1 - read-write - - - OUT_DMA_ID - 0: Pixel (Out) -1: ECS (Out) - 4 - 1 - read-write - - - OUT_DMA_REQ - Asserted to enable Out DMA request - 3 - 1 - read-write - - - OUTDMA2D - Asserted if Out_DMA_ID==Pixel - 2 - 1 - read-write - - - - - OutDMABase - Out DMA Buf Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Y plane (or Encoded Bit Plane) - 0 - 32 - read-write - - - - - OutDMA_Ctrl0 - Out DMA Buf Control 0 Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TTLEN - Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - 16 - 16 - read-write - - - PITCH - Pitch between the starting point of Rows when Out_DMA_ID==Pixel - 0 - 16 - read-write - - - - - OutDMA_Ctrl1 - Out DMA Buf Control 1 Register - 0x30 - 32 - 0x00000000 - 0x0000FFFF - - - ROWLEN - Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - 0 - 16 - read-write - - - - - ONXT_CMD - Out DMA Next Command Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The address pointing to the next command - 2 - 30 - read-write - - - OP_VALID - asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - 1 - 1 - read-write - - - EN - NXTCMD phase Enable Bit - 0 - 1 - read-write - - - - - CFG - Configuration Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - JD_UVSWAP - Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - 22 - 1 - read-write - - - CFG_IPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as B,R -2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - 20 - 2 - read-write - - - CODEC_OVER_IRQ_EN - The jpg endec process done interrupt enable - 19 - 1 - read-write - - - CODEC_RESTART_ERR_IRQ_EN - The jpg endec restart error interrupt enable - 18 - 1 - read-write - - - MEM_DEBUG_CLK_SEL - asserted to use APB clock, so that the memory contents could be read out through APB interface - 17 - 1 - read-write - - - CLKGATE - Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - 9 - 1 - read-write - - - CFG_OPATH_SEL - 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V -2'b01:ARGB8888, byte sequence as B,G,R,A -2'b10:RGB565, byte sequence as R,B -2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - 7 - 2 - read-write - - - JDATA_FORMAT - 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU -3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU -3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU -3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU -3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU -Others: Undefined - 4 - 3 - read-write - - - JPEG_SFTRST - Software Reset - 3 - 1 - read-write - - - START - Asserted if to start a new encoder/decoder conversion. -It will at first stop the inner JPEG module, then reset it, and then re-run it. -It is a different mode from DMA phase mode. -It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. -Auto clear. - 2 - 1 - read-write - - - MODE - 1: decoder, 0:encoder - 1 - 1 - read-write - - - JPEG_EN - 1b - Enabled - 0 - 1 - read-write - - - - - STAT - Status Register - 0x44 - 32 - 0x00000000 - 0xFFFFBFFE - - - BUSY - When 1 means that the module is busy doing conversion and data transfer. - 31 - 1 - read-only - - - AXI_ERR_ID - the axi err id - 10 - 4 - read-only - - - AXI_READ_ERR - in-dma axi bus error - 9 - 1 - read-only - - - AXI_WRITE_ERR - out-dma axi bus error - 8 - 1 - read-only - - - AXI_ERR - axi bus error - 7 - 1 - write-only - - - ONXT_IRQ - OutDMA next interrupt - 6 - 1 - write-only - - - INXT_IRQ - InDMA next interrupt - 5 - 1 - write-only - - - OUT_DMA_TRANSFER_DONE - OutDMA process done - 4 - 1 - write-only - - - IN_DMA_TRANSFER_DONE - InDMA process done - 3 - 1 - write-only - - - CODEC_OVER - Coding or decoding process is over. DMA is not included. -The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - 2 - 1 - write-only - - - RESTART_MARKER_ERROR - codec restart marker error interrupt - 1 - 1 - write-only - - - - - Width - Image width register - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - Height - Image height register - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - IMG - Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - 0 - 16 - read-write - - - - - BufAddr - Buf Access Addr - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - ADDR[31:28] denotes the buffer type: -0x2: Qmem -0x3: HuffEnc -0x4: HuffMin -0x5: HuffBase -0x6: HuffSymb -ADDR[27:0] is the address inside the buffer - 0 - 32 - read-write - - - - - BufData - Buf Access Data - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer. -The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - 0 - 32 - read-write - - - - - OutDMACnt - Out DMA Bytes Counter - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The out DMA counter - 0 - 32 - read-only - - - - - CSC_COEF0 - YUV2RGB coefficients Register 0 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - This bit changes the behavior when performing U/V converting. -0b - Converting YUV to RGB data -1b - Converting YCbCr to RGB data - 31 - 1 - read-write - - - ENABLE - Enable the CSC unit. -0b - The CSC is bypassed -1b - The CSC is enabled - 30 - 1 - read-write - - - C0 - Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - 18 - 11 - read-write - - - UV_OFFSET - Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. -YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - 9 - 9 - read-write - - - Y_OFFSET - Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is -typically -16 (0x1F0). - 0 - 9 - read-write - - - - - CSC_COEF1 - YUV2RGB coefficients Register 1 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - 16 - 11 - read-write - - - C4 - Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - 0 - 11 - read-write - - - - - CSC_COEF2 - YUV2RGB coefficients Register 2 - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - 16 - 11 - read-write - - - C3 - Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - 0 - 11 - read-write - - - - - RGB2YUV_COEF0 - RGB2YUV coefficients Register 0 - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - YCBCR_MODE - Asserted to use YCrCb mode. Must be assigned as 1. - 31 - 1 - read-write - - - ENABLE - Asserted to enable this RGB2YCbCr CSC stage - 30 - 1 - read-write - - - C0 - CSC parameters C0 - 18 - 11 - read-write - - - UV_OFFSET - CSC parameters UV_OFFSET - 9 - 9 - read-write - - - Y_OFFSET - CSC parameters Y_OFFSET - 0 - 9 - read-write - - - - - RGB2YUV_COEF1 - RGB2YUV coefficients Register 1 - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - C1 - CSC parameters C1 - 16 - 11 - read-write - - - C4 - CSC parameters C4 - 0 - 11 - read-write - - - - - RGB2YUV_COEF2 - RGB2YUV coefficients Register 2 - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - C2 - CSC parameters C2 - 16 - 11 - read-write - - - C3 - CSC parameters C3 - 0 - 11 - read-write - - - - - RGB2YUV_COEF3 - RGB2YUV coefficients Register 3 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - C6 - CSC parameters C6 - 16 - 11 - read-write - - - C5 - CSC parameters C5 - 0 - 11 - read-write - - - - - RGB2YUV_COEF4 - RGB2YUV coefficients Register 4 - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - C8 - CSC parameters C8 - 16 - 11 - read-write - - - C7 - CSC parameters C7 - 0 - 11 - read-write - - - - - ImgReg1 - Image Control Register 1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFF7 - - - RE - Encoder Use only. -Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - 2 - 1 - read-write - - - NCOL - Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - 0 - 2 - read-write - - - - - ImgReg2 - Image Control Register 2 - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - NMCU - Encoder Use only. -The number of NMCU to be generated in encoder mode - 0 - 26 - read-write - - - - - ImgReg3 - Image Control Register 3 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - NRST - Encoder use only. -It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - 0 - 16 - read-write - - - - - 4 - 0x4 - Reg40,Reg41,Reg42,Reg43 - IMGREG[%s] - no description available - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - NBLOCK - Encoder use only. -The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - 4 - 4 - read-write - - - QT - Encoder use only. -The selection of the quantization table. - 2 - 2 - read-write - - - HA - Encoder use only. -The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - 1 - 1 - read-write - - - HD - Encoder use only. -The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - 0 - 1 - read-write - - - - - - - GWC0 - GWC0 - GWC - 0xf1018000 - - 0x0 - 0x1f0 - registers - - - - glb_ctrl - control reg - 0x0 - 32 - 0x00000000 - 0x00000081 - - - CLK_POL - graphic clock polarity. -set to invert input graphic clock - 7 - 1 - read-write - - - GWC_EN - graphic window check enable. -set to enable the whole block - 0 - 1 - read-write - - - - - irq_mask - interrupt enable - 0x4 - 32 - 0x00000000 - 0x0000000B - - - MASK_RREEZ - freeze mask, set to disable changing ERR_MASK and FUNC_MASK. -can only be cleared by system reset - 3 - 1 - read-write - - - FUNC_MASK - function interrupt mask - 1 - 1 - read-write - - - ERR_MASK - error interrupt mask - 0 - 1 - read-write - - - - - irq_sts - interrupt status - 0x8 - 32 - 0x00000000 - 0x0003FFFF - - - FUNC_STS - function interrupt status. -it's set when detect two VSYNC signals after the block is enabled(GWC_EN is set) -software write 1 to clear. - 17 - 1 - write-only - - - ERR_STS - error status, it's OR of GWC_FAIL_STS[15:0] - 16 - 1 - read-only - - - GWC_FAIL_STS - graphic window check fail interrupt status. -will be set if the calculated CRC not equal reference CRC. -one bit for each channel. -software write 1 to clear. - 0 - 16 - write-only - - - - - 2 - 0xf0 - ch0,ch15 - CHANNEL[%s] - no description available - 0x10 - - cfg0 - config reg 0 - 0x0 - 32 - 0x00000000 - 0xCFFF1FFF - - - ENABLE - channel enable - 31 - 1 - read-write - - - FREEZE - freeze config. set to freeze all other config registers for current channel. -can only be cleared by system reset - 30 - 1 - read-write - - - START_ROW - define the window start row number - 16 - 12 - read-write - - - START_COL - define the window start column number - 0 - 13 - read-write - - - - - cfg1 - config reg 1 - 0x4 - 32 - 0x00000000 - 0x0FFF1FFF - - - END_ROW - define the window end row number - 16 - 12 - read-write - - - END_COL - define the window end column number - 0 - 13 - read-write - - - - - refcrc - reference CRC - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - REF_CRC - reference CRC -polynomial function: 0x104C11DB7 - 0 - 32 - read-write - - - - - calcrc - calculated CRC - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CAL_CRC - calculated CRC for last frame - 0 - 32 - read-write - - - - - - - - GWC1 - GWC1 - GWC - 0xf101c000 - - - MIPI_DSI0 - MIPI_DSI0 - MIPI_DSI - 0xf1020000 - - 0x0 - 0x194 - registers - - - - version - version - 0x0 - 32 - 0x3134302A - 0xFFFFFFFF - - - VERSION - version of DSI - 0 - 32 - read-only - - - - - pwr_up - power up - 0x4 - 32 - 0x00000000 - 0x00000001 - - - SHUTDOWNZ - 0x0: reset the core -0x1: power up the core - 0 - 1 - read-write - - - - - clkmgr_cfg - divide lanebyteclk for timeout - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - TO_CLK_DIVISION - the timeout clock division factor for HS to LP and LP to HS transition error - 8 - 8 - read-write - - - TX_ESC_CLK_DIVISION - the division factor for the TX Escape clock source lanebyteclk - 0 - 8 - read-write - - - - - dpi_vcid - virtual channel ID for DPI traffic - 0xc - 32 - 0x00000000 - 0x00000003 - - - DPI_VCID - the DPI virtual channel id to the video mode packets - 0 - 2 - read-write - - - - - dpi_color_coding - dpi color coding - 0x10 - 32 - 0x00000000 - 0x0000010F - - - LOOSELY18_EN - when set to 1, this bit activates loosely packed variant to 18-bit configurations - 8 - 1 - read-write - - - DPI_COLOR_CODING - configures the DPI color for video mode - 0 - 4 - read-write - - - - - dpi_cfg_pol - the polarity of DPI signals - 0x14 - 32 - 0x00000000 - 0x0000001F - - - COLORM_ACTIVE_LOW - configures the color mode pin as active low - 4 - 1 - read-write - - - SHUTD_ACTIVE_LOW - configures the shutdown pin as active low - 3 - 1 - read-write - - - HSYNC_ACTIVE_LOW - configures the horizontal synchronism pin as active low - 2 - 1 - read-write - - - VSYNC_ACTIVE_LOW - configures the vertical synchronism pin as active low - 1 - 1 - read-write - - - DATAEN_ACTIVE_LOW - configures the data enable pin active low - 0 - 1 - read-write - - - - - dpi_lp_cmd_tim - the timing for low-power commands sent while in video mode - 0x18 - 32 - 0x00000000 - 0x00FF00FF - - - OUTVACT_LPCMD_TIME - transmission of commands in low-power mode, defines the size in bytes of the largest pachet that can fit in a line during the VSA VBP and VFP; - 16 - 8 - read-write - - - INVACT_LPCMD_TIME - transmission of commands in low-power mode, defines the size in bytes of the largest packet that can fit in a line during the VACT region. - 0 - 8 - read-write - - - - - pckhdl_cfg - configures how EoTp, BTA, CRC and ECC to be used - 0x2c - 32 - 0x00000000 - 0x0000003F - - - EOTP_TX_LP_EN - enable the EoTp transmission in low-power - 5 - 1 - read-write - - - CRC_RX_EN - enable the crc reception and error reporting - 4 - 1 - read-write - - - ECC_RX_EN - enable the ecc reception error correction and reporting - 3 - 1 - read-write - - - BTA_EN - enable the bus turn-around request - 2 - 1 - read-write - - - EOTP_RX_EN - enable the EoTp reception - 1 - 1 - read-write - - - EOTP_TX_EN - enable the EoTp transmission in high-speed - 0 - 1 - read-write - - - - - gen_vcid - configures the virtual channel ID of read response to store and return to generic interface - 0x30 - 32 - 0x00000000 - 0x00030303 - - - GEN_VCID_TX_AUTO - indicates the generic interface virtual channel identification where generic packet is automatically generated and transmitted - 16 - 2 - read-write - - - GEN_VCID_TEAR_AUTO - indicates the virtual channel identification for tear effect by hardware - 8 - 2 - read-write - - - GEN_VCID_RX - indicates the generic interface read-back virtual channel identication - 0 - 2 - read-write - - - - - mode_cfg - configures the mode of operation between video or command mode - 0x34 - 32 - 0x00000001 - 0x00000001 - - - CMD_VIDEO_MODE - 0x0: video mode -0x1: command mode - 0 - 1 - read-write - - - - - vid_mode_cfg - several aspect of video mode operation - 0x38 - 32 - 0x00000000 - 0x0111FF03 - - - VPG_ORIENTATION - indicates the color bar orientation : -0x0: vertical mode -0x1: horizontal mode - 24 - 1 - read-write - - - VPG_MODE - 0x0: colorbar -0x1: berpattern, vertical only - 20 - 1 - read-write - - - VPG_EN - enable video mode pattern generator - 16 - 1 - read-write - - - LP_CMD_EN - enable command transmission only in low-power mode - 15 - 1 - read-write - - - FRAME_BTA_ACK_EN - enable the request for an acknowledge response at the end of a frame - 14 - 1 - read-write - - - LP_HFP_EN - enable the return to low-power inside the HFP period when timing allows - 13 - 1 - read-write - - - LP_HBP_EN - enable the return to low-power inside the HBP period when timing allows - 12 - 1 - read-write - - - LP_VACT_EN - enable the return to low-power inside the VACT period when timing allows - 11 - 1 - read-write - - - LP_VFP_EN - enable the return to low-power inside the VFP period when timing allows - 10 - 1 - read-write - - - LP_VBP_EN - enable the return to low-power inside the VBP period when timing allows - 9 - 1 - read-write - - - LP_VSA_EN - enable the return to low-power inside the VSA period when timing allows - 8 - 1 - read-write - - - VID_MODE_TYPE - indicates the video mode transmission type - 0 - 2 - read-write - - - - - vid_pkt_size - configures the video packet size - 0x3c - 32 - 0x00000000 - 0x00003FFF - - - VID_PKT_SIZE - configures the number of pixels in a single video packet - 0 - 14 - read-write - - - - - vid_num_chunks - configures the number of chunks to use - 0x40 - 32 - 0x00000000 - 0x00001FFF - - - VID_NUM_CHUNKS - configures the number of chunks to be transmitted a line period - 0 - 13 - read-write - - - - - vid_null_size - configures the size of null packets - 0x44 - 32 - 0x00000000 - 0x00001FFF - - - VID_NULL_SIZE - configures the number of bytes inside a null packet - 0 - 13 - read-write - - - - - vid_hsa_time - configures the video HAS time - 0x48 - 32 - 0x00000000 - 0x00000FFF - - - VID_HSA_TIME - configure the Horizontal synchronism active period in lane byte clock cycles - 0 - 12 - read-write - - - - - vid_hbp_time - configure the video HBP time - 0x4c - 32 - 0x00000000 - 0x00000FFF - - - VID_HPB_TIME - configures the Horizontal back porch period in lane byte clock cycles - 0 - 12 - read-write - - - - - vid_hline_time - configures the overall time for each video line - 0x50 - 32 - 0x00000000 - 0x00007FFF - - - VID_HLINE_TIME - configures the size of the total line time in lane byte clock cycles - 0 - 15 - read-write - - - - - vid_vsa_lines - configures the vsa period - 0x54 - 32 - 0x00000000 - 0x000003FF - - - VSA_LINES - configures the verical synchronism active period measured in number of horizontal lines - 0 - 10 - read-write - - - - - vid_vbp_lines - configures the vbp period - 0x58 - 32 - 0x00000000 - 0x000003FF - - - VBP_LINES - configures the vertical back porch period measured in number of horizontal lines - 0 - 10 - read-write - - - - - vid_vfp_lines - configures the vfp period - 0x5c - 32 - 0x00000000 - 0x000003FF - - - VFP_LINIES - configures the vertical front porch period measured in number of horizontal lines - 0 - 10 - read-write - - - - - vid_vactive_lines - configures the vertical resolution of video - 0x60 - 32 - 0x00000000 - 0x00003FFF - - - V_ACTIVE_LINES - configures the vertical active period measured in number of horizontal lines - 0 - 14 - read-write - - - - - CMD_MODE_CFG - This register configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands. - 0x68 - 32 - 0x00000000 - 0x010F7F03 - - - MAX_RD_PKT_SIZE - This bit configures the maximum read packet size command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 24 - 1 - read-write - - - DCS_LW_TX - This bit configures the DCS long write packet command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 19 - 1 - read-write - - - DCS_SR_0P_TX - This bit configures the DCS short read packet with zero parameter command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 18 - 1 - read-write - - - DCS_SW_1P_TX - This bit configures the DCS short write packet with one parameter command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 17 - 1 - read-write - - - DCS_SW_0P_TX - This bit configures the DCS short write packet with zero parameter command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 16 - 1 - read-write - - - GEN_LW_TX - This bit configures the Generic long write packet command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 14 - 1 - read-write - - - GEN_SR_2P_TX - This bit configures the Generic short read packet with two parameters command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 13 - 1 - read-write - - - GEN_SR_1P_TX - This bit configures the Generic short read packet with two parameters command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 12 - 1 - read-write - - - GEN_SR_0P_TX - This bit configures the Generic short read packet with two parameters command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 11 - 1 - read-write - - - GEN_SW_2P_TX - This bit configures the Generic short read packet with two parameters command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 10 - 1 - read-write - - - GEN_SW_1P_TX - This bit configures the Generic short read packet with two parameters command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 9 - 1 - read-write - - - GEN_SW_0P_TX - This bit configures the Generic short read packet with two parameters command transmission type: -0x0 (HIGHSPEED): Transition type is High Speed -0x1 (LOWPOWER): Transition type is Low Power - 8 - 1 - read-write - - - ACK_RQST_EN - When set to 1, this bit enables the acknowledge request after each packet transmission. - 1 - 1 - read-write - - - TEAR_FX_EN - When set to 1, this bit enables the tearing effect acknowledge request. - 0 - 1 - read-write - - - - - gen_hdr - sets the header for new packets sent using the generic interface - 0x6c - 32 - 0x00000000 - 0x00FFFFFF - - - GEN_WC_MSBYTE - configures the most significant byte of the header packet's word count for long packets or data 1 for shout packets - 16 - 8 - read-write - - - GEN_WC_LSBYTE - configures the least significant byte of the header packet's word count for long packets or data0 for short packets - 8 - 8 - read-write - - - GEN_VC - configures the virtual channel ID of the header packet - 6 - 2 - read-write - - - GEN_DT - configures the packet data type of the header packet - 0 - 6 - read-write - - - - - gen_pld_data - sets the payload for packets sent using the generic interface - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - GEN_PLD_B4 - indicates byte4 of the packet payload - 24 - 8 - read-write - - - GEN_PLD_B3 - indicates byte3 of the packet payload - 16 - 8 - read-write - - - GEN_PLD_B2 - indicates byte2 of the packet payload - 8 - 8 - read-write - - - GEN_PLD_B1 - indicates byte1 of the packet payload - 0 - 8 - read-write - - - - - cmd_pkt_status - information about the status of FIFOs related to DBI and Generic interface - 0x74 - 32 - 0x00000000 - 0x000F007F - - - GEN_BUFF_PLD_FULL - the full status of the generic payload internal buffer - 19 - 1 - read-only - - - GEN_BUFF_PLD_EMPTY - the empty status of the generic payload internal buffer - 18 - 1 - read-only - - - GEN_BUFF_CMD_FULL - the full status of the generic command internal buffer - 17 - 1 - read-only - - - GEN_BUFF_CMD_EMPTY - the empty status of the generic command internal buffer - 16 - 1 - read-only - - - GEN_RD_CMD_BUSY - indicates a read command is issued and the entire response is not sotred in the FIFO - 6 - 1 - read-only - - - GEN_PLD_R_FULL - indicates the full status of the generic read payoad FIFO - 5 - 1 - read-only - - - GEN_PLD_R_EMPTY - indicates the empty status of the generic read payload FIFO - 4 - 1 - read-only - - - GEN_PLD_W_FULL - indicates the full status of the generic write payload FIFO - 3 - 1 - read-only - - - GEN_PLD_W_EMPTY - indicates the empty status of the generic write payload FIFO - 2 - 1 - read-only - - - GEN_CMD_FULL - indicates the full status of the generic command FIFO - 1 - 1 - read-only - - - GEN_CMD_EMPTY - indicates the empty status of the generic command FIFO - 0 - 1 - read-only - - - - - to_cnt_cfg - configures the trigger timeout errors - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - HSTX_TO_CNT - configures the timeout counter that triggers a high speed transmission timeout contention detection - 16 - 16 - read-write - - - LPRX_TO_CNT - configures the timeout counter that triggers a low power reception timeout contention detection - 0 - 16 - read-write - - - - - hs_rd_to_cnt - configures the peripheral response timeout after high speed read operations - 0x7c - 32 - 0x00000000 - 0x0000FFFF - - - HS_RD_TO_CNT - sets a period for which DWC_mipi_dsi_host keeps the link still after sending a high speed read operation; - 0 - 16 - read-write - - - - - lp_rd_to_cnt - configures the peripheral response timeout after low-power read operation - 0x80 - 32 - 0x00000000 - 0x0000FFFF - - - LP_RD_TO_CNT - sets a period for which dwc_mipi_dsi_host keeps the link still after sending a low power read operation - 0 - 16 - read-write - - - - - hs_wr_to_cnt - configures the peripheral response timeout after high speed write operations - 0x84 - 32 - 0x00000000 - 0x0000FFFF - - - HS_WR_TO_CNT - sets the period for which dwc_mipi_dsi_host keeps the link still after sending a high speed write operation - 0 - 16 - read-write - - - - - lp_wr_to_cnt - configures the peripheral response timeout after low power write operations - 0x88 - 32 - 0x00000000 - 0x0000FFFF - - - LP_WR_TO_CNT - sets the period for which dsi host keeps the link still after sending a low power write operation - 0 - 16 - read-write - - - - - bta_to_cnt - configures the periphera response timeout after bus turnaround - 0x8c - 32 - 0x00000000 - 0x0000FFFF - - - BTA_TO_CNT - sets the period for which dsi host keeps the link still after completing a bus turnaround. - 0 - 16 - read-write - - - - - sdf_3d - sotres 3d control information for vss packets in video mode - 0x90 - 32 - 0x00000000 - 0x0001003F - - - SEND_3D_CFG - set the next vss packet to include 3d control payload in every vss packet - 16 - 1 - read-write - - - RIGHT_FIRST - 0x0: left eye is sent first -0x1:right eye is sent first - 5 - 1 - read-write - - - SECOND_VSYNC - defines whether there is a second VSYNC pulse - 4 - 1 - read-write - - - FORMAT_3D - defines 3D image format - 2 - 2 - read-write - - - MODE_3D - defines 3D mode on/off - 0 - 2 - read-write - - - - - lpclk_ctrl - configures the possibility for using non continuous clock in the clock lane - 0x94 - 32 - 0x00000000 - 0x00000003 - - - AUTO_CLKLANE_CTRL - enables the automatic mechanism to stop providing clock in the clock lane - 1 - 1 - read-write - - - PHY_TXREQUESTCLKHS - controls the D-PHY PPI txrequestclkhs signal - 0 - 1 - read-write - - - - - phy_tmr_lpclk_cfg - sets the time that dsi host assumes in calculations for the clock lane to switch between high-speed and low-power - 0x98 - 32 - 0x00000000 - 0x03FF03FF - - - PHY_CLKHS2LP_TIME - configures the maximum time that the d-phy clock lane takes to go from high-speed to low-power transmission - 16 - 10 - read-write - - - PHY_CLKLP2HS_TIME - configures the maximum time that the d-phy clock lane takes to go from low-power to high-speed transmission - 0 - 10 - read-write - - - - - phy_tmr_cfg - sets the time that dsi host assumes in calculations for data lanes to switch between hs to lp - 0x9c - 32 - 0x00000000 - 0x03FF03FF - - - PHY_HS2LP_TIME - This field configures the maximum time that the D-PHY data -lanes take to go from high-speed to low-power transmission -measured in lane byte clock cycles - 16 - 10 - read-write - - - PHY_LP2HS_TIME - This field configures the maximum time that the D-PHY data -lanes take to go from low-power to high-speed transmission -measured in lane byte clock cycles. - 0 - 10 - read-write - - - - - phy_rstz - controls resets and the pll of d-phy - 0xa0 - 32 - 0x00000000 - 0x0000000F - - - PHY_FORCEPLL - when the d-phy is in ulps, enable the d-phy pll - 3 - 1 - read-write - - - PHY_ENABLECLK - enable dphy clock lane - 2 - 1 - read-write - - - PHY_RSTZ - make the dphy in reset state when set to 0 - 1 - 1 - read-write - - - PHY_SHUTDOWNZ - places the dphy macro in power down mode when set to 0 - 0 - 1 - read-write - - - - - phy_if_cfg - configures the number of active lanes - 0xa4 - 32 - 0x00000000 - 0x0000FF03 - - - PHY_STOP_WAIT_TIME - configures the minimum time phy needs to stay in stopstate before requesting an highspeed transmission - 8 - 8 - read-write - - - N_LANES - configures the number of active data lanes - 0 - 2 - read-write - - - - - phy_ulps_ctrl - configures entering and leaving ulps - 0xa8 - 32 - 0x00000000 - 0x0000000F - - - PHY_TXEXITULPSLAN - ulps mode exit on all active data lanes - 3 - 1 - read-write - - - PHY_TXREQULPSLAN - ulps mode request on all active data lanes - 2 - 1 - read-write - - - PHY_TXEXITULPSCLK - ulps mode exit on clock lane - 1 - 1 - read-write - - - PHY_TXREQULPSCLK - ulps mode request on clock lane - 0 - 1 - read-write - - - - - phy_tx_triggers - configures the pins that activate triggers in the d-phy - 0xac - 32 - 0x00000000 - 0x0000000F - - - PHY_TX_TRIGGERS - controls the trigger transmissions - 0 - 4 - read-write - - - - - phy_status - contains information about the status of the d-phy - 0xb0 - 32 - 0x00000000 - 0x00001FFF - - - PHY_ULPSACTIVENOT3LANE - indicates the status of ulpsactivenot3lane d-phy signal - 12 - 1 - read-only - - - PHY_STOPSTATE3LANE - This bit indicates the status of phystopstate3lane D-PHY -signal. - 11 - 1 - read-only - - - PHY_ULPSACTIVENOT2LANE - This bit indicates the status of ulpsactivenot2lane D-PHY -signa - 10 - 1 - read-only - - - PHY_STOPSTATE2LANE - This bit indicates the status of phystopstate2lane D-PHY -signal - 9 - 1 - read-only - - - PHY_ULPSACTIVENOT1LANE - This bit indicates the status of ulpsactivenot1lane D-PHY -signal - 8 - 1 - read-only - - - PHY_STOPSTATE1LANE - This bit indicates the status of phystopstate1lane D-PHY -signal - 7 - 1 - read-only - - - PHY_RXULPSESC0LANE - This bit indicates the status of rxulpsesc0lane D-PHY signa - 6 - 1 - read-only - - - PHY_ULPSACTIVENOT0LANE - This bit indicates the status of ulpsactivenot0lane D-PHY -signal - 5 - 1 - read-only - - - PHY_STOPSTATE0LANE - This bit indicates the status of phystopstate0lane D-PHY -signal - 4 - 1 - read-only - - - PHY_ULPSACTIVENOTCLK - This bit indicates the status of phyulpsactivenotclk D-PHY -signal - 3 - 1 - read-only - - - PHY_STOPSTATECLKLANE - This bit indicates the status of phystopstateclklane D-PHY -signal - 2 - 1 - read-only - - - PHY_DIRECTION - This bit indicates the status of phydirection D-PHY signal - 1 - 1 - read-only - - - PHY_LOCK - This bit indicates the status of phylock D-PHY signal - 0 - 1 - read-only - - - - - phy_tst_ctrl0 - controls clock and clear pins of the d-phy vendor specific interface - 0xb4 - 32 - 0x00000000 - 0x00000003 - - - PHY_TESTCLK - reserve - 1 - 1 - read-write - - - PHY_TESTCLR - reserve - 0 - 1 - read-write - - - - - phy_tst_ctrl1 - controls data and enable pins of the d-phy - 0xb8 - 32 - 0x00000000 - 0x0001FFFF - - - PHY_TESTEN - reserve - 16 - 1 - read-write - - - PHY_TESTDOUT - reserve - 8 - 8 - read-only - - - PHY_TESTDIN - reserve - 0 - 8 - read-write - - - - - int_st0 - controls the status of interrupt - 0xbc - 32 - 0x00000000 - 0x001FFFFF - - - DPHY_ERRORS_4 - indicates LP1 contention error ErrContentionLP1 from lane0 - 20 - 1 - read-only - - - DPHY_ERRORS_3 - indicates LP0 contention error ErrContentionLP0 from lane0 - 19 - 1 - read-only - - - DPHY_ERRORS_2 - indicates control error ErrControl from lane0 - 18 - 1 - read-only - - - DPHY_ERRORS_1 - indicates ErrSyncEsc low-power data transmission synchronization error from lane 0 - 17 - 1 - read-only - - - DPHY_ERRORS_0 - indicates ErrEsc escape entry error from lane0 - 16 - 1 - read-only - - - ACK_WITH_ERR_15 - retrives the DSI protocal violation from the acknowledge error report - 15 - 1 - read-only - - - ACK_WITH_ERR_14 - retrives the reserved from the acknowledge error report - 14 - 1 - read-only - - - ACK_WITH_ERR_13 - retrives the invalid transmission length from the acknowledge error report - 13 - 1 - read-only - - - ACK_WITH_ERR_12 - retrieves the dsi vc id invalid from the acknowledge error report - 12 - 1 - read-only - - - ACK_WITH_ERR_11 - retrives the not recongnized dsi data type from the acknowledge error report - 11 - 1 - read-only - - - ACK_WITH_ERR_10 - retrives the checksum error from the acknowledge error report - 10 - 1 - read-only - - - ACK_WITH_ERR_9 - retrives the ECC error multi-bit from the acknowledge error report - 9 - 1 - read-only - - - ACK_WITH_ERR8 - retrives the ecc error sigle-bit from the acknowledge error report - 8 - 1 - read-only - - - ACK_WITH_ERR7 - retrieves the reserved from the acknowledge error report - 7 - 1 - read-only - - - ACK_WITH_ERR6 - retrieves the false control error fro the acknowledge error report - 6 - 1 - read-only - - - ACK_WITH_ERR5 - retrives the peripheral timeout error from the acknowledge error report - 5 - 1 - read-only - - - ACK_WITH_ERR4 - retrives the LP transmit sync error from the acknowledge error report - 4 - 1 - read-only - - - ACK_WITH_ERR3 - retrives the Escap mode entry command error from the acknowledge error report - 3 - 1 - read-only - - - ACK_WITH_ERR2 - retrives the EoT sync error from the acknowledge error report - 2 - 1 - read-only - - - ACK_WITH_ERR1 - retrives the SoT sync error from the acknowledge error report - 1 - 1 - read-only - - - ACK_WITH_ERR0 - retrives the SoT serror from the acknowledge error report - 0 - 1 - read-only - - - - - int_st1 - the interrupt source related to timeout etc - 0xc0 - 32 - 0x00000000 - 0x00181FFF - - - TEAR_REQUEST_ERR - indicates tear_request has occurred but tear effect is not active in dsi host and device - 20 - 1 - read-only - - - DPI_BUFF_PLD_UNDER - indicates an underflow when reading payload to build dsi packet for video mode - 19 - 1 - read-only - - - GEN_PLD_RECEV_ERR - indicates that during a generic interface packet read back, the payload FIFO full - 12 - 1 - read-only - - - GEN_PLD_RD_ERR - indicates that during a DCS read data, the payload FIFO becomes empty - 11 - 1 - read-only - - - GEN_PLD_SEND_ERR - indicates the payload FIFO become empty when packet build - 10 - 1 - read-only - - - GEN_PLD_WR_ERR - indicates the system tried to write a payload and FIFO is full - 9 - 1 - read-only - - - GEN_CMD_WR_ERR - indicates the system tried to write a command and FIFO is full - 8 - 1 - read-only - - - DPI_BPLD_WR_ERR - indicates the payload FIFO is full during a DPI pixel line storage - 7 - 1 - read-only - - - EOPT_ERR - indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission - 6 - 1 - read-only - - - PKT_SIZE_ERR - indicates that the packet size error has been detected during the packet reception - 5 - 1 - read-only - - - CRC_ERR - indicates that the CRC error has been detected in the reveived packet payload - 4 - 1 - read-only - - - ECC_MULTI_ERR - indicates that the ECC multiple error has been detected in a revieved packet - 3 - 1 - read-only - - - ECC_SIGLE_ERR - indicates that the ECC single error has been detected and corrected in a reveived packet - 2 - 1 - read-only - - - TO_LP_TX - indicates that the low-power reception timeout counter reached the end and contention has been detected - 1 - 1 - read-only - - - TO_HS_TX - indicates that the high-speed transmission timeout counter reached the end and contention has been detected - 0 - 1 - read-only - - - - - int_msk0 - configures masks for the sources of interrupt that affec int_st0 - 0xc4 - 32 - 0x00000000 - 0x001FFFFF - - - MASK_DPHY_ERRORS_4 - disable LP1 contention error ErrContentionLP1 from lane0 - 20 - 1 - read-write - - - MASK_DPHY_ERRORS_3 - disable LP0 contention error ErrContentionLP0 from lane0 - 19 - 1 - read-write - - - MASK_DPHY_ERRORS_2 - disable control error ErrControl from lane0 - 18 - 1 - read-write - - - MASK_DPHY_ERRORS_1 - disable ErrSyncEsc low-power data transmission synchronization error from lane 0 - 17 - 1 - read-write - - - MASK_DPHY_ERRORS_0 - disable ErrEsc escape entry error from lane0 - 16 - 1 - read-write - - - MASK_ACK_WITH_ERR_15 - disable the DSI protocal violation from the acknowledge error report - 15 - 1 - read-write - - - MASK_ACK_WITH_ERR_14 - disable the reserved from the acknowledge error report - 14 - 1 - read-write - - - MASK_ACK_WITH_ERR_13 - disable the invalid transmission length from the acknowledge error report - 13 - 1 - read-write - - - MASK_ACK_WITH_ERR_12 - disable the dsi vc id invalid from the acknowledge error report - 12 - 1 - read-write - - - MASK_ACK_WITH_ERR_11 - disable the not recongnized dsi data type from the acknowledge error report - 11 - 1 - read-write - - - MASK_ACK_WITH_ERR_10 - disable the checksum error from the acknowledge error report - 10 - 1 - read-write - - - MASK_ACK_WITH_ERR_9 - disable the ECC error multi-bit from the acknowledge error report - 9 - 1 - read-write - - - MASK_ACK_WITH_ERR8 - disable the ecc error sigle-bit from the acknowledge error report - 8 - 1 - read-write - - - MASK_ACK_WITH_ERR7 - disable the reserved from the acknowledge error report - 7 - 1 - read-write - - - MASK_ACK_WITH_ERR6 - disable the false control error fro the acknowledge error report - 6 - 1 - read-write - - - MASK_ACK_WITH_ERR5 - disable the peripheral timeout error from the acknowledge error report - 5 - 1 - read-write - - - MASK_ACK_WITH_ERR4 - disable the LP transmit sync error from the acknowledge error report - 4 - 1 - read-write - - - MASK_ACK_WITH_ERR3 - disable the Escap mode entry command error from the acknowledge error report - 3 - 1 - read-write - - - MASK_ACK_WITH_ERR2 - disable the EoT sync error from the acknowledge error report - 2 - 1 - read-write - - - MASK_ACK_WITH_ERR1 - disable the SoT sync error from the acknowledge error report - 1 - 1 - read-write - - - MASK_ACK_WITH_ERR0 - disable the SoT serror from the acknowledge error report - 0 - 1 - read-write - - - - - int_msk1 - configures masks for int_st1 - 0xc8 - 32 - 0x00000000 - 0x00181FFF - - - MASK_TEAR_REQUEST_ERR - disable tear_request has occurred but tear effect is not active in dsi host and device - 20 - 1 - read-write - - - MASK_DPI_BUFF_PLD_UNDER - disable an underflow when reading payload to build dsi packet for video mode - 19 - 1 - read-write - - - MASK_GEN_PLD_RECEV_ERR - disable that during a generic interface packet read back, the payload FIFO full - 12 - 1 - read-write - - - MASK_GEN_PLD_RD_ERR - disable that during a DCS read data, the payload FIFO becomes empty - 11 - 1 - read-write - - - MASK_GEN_PLD_SEND_ERR - disable the payload FIFO become empty when packet build - 10 - 1 - read-write - - - MASK_GEN_PLD_WR_ERR - disable the system tried to write a payload and FIFO is full - 9 - 1 - read-write - - - MASK_GEN_CMD_WR_ERR - disable the system tried to write a command and FIFO is full - 8 - 1 - read-write - - - MASK_DPI_BPLD_WR_ERR - disable the payload FIFO is full during a DPI pixel line storage - 7 - 1 - read-write - - - MASK_EOPT_ERR - disable that the EoTp packet has not been received at the end of the incoming peripheral transmission - 6 - 1 - read-write - - - MASK_PKT_SIZE_ERR - disable that the packet size error has been detected during the packet reception - 5 - 1 - read-write - - - MASK_CRC_ERR - disable that the CRC error has been detected in the reveived packet payload - 4 - 1 - read-write - - - MASK_ECC_MULTI_ERR - disable that the ECC multiple error has been detected in a revieved packet - 3 - 1 - read-write - - - MASK_ECC_SIGLE_ERR - disable that the ECC single error has been detected and corrected in a reveived packet - 2 - 1 - read-write - - - MASK_TO_LP_TX - disable that the low-power reception timeout counter reached the end and contention has been detected - 1 - 1 - read-write - - - MASK_TO_HS_TX - disable that the high-speed transmission timeout counter reached the end and contention has been detected - 0 - 1 - read-write - - - - - phy_cal - controls the skew calibration of D-phy - 0xcc - 32 - 0x00000000 - 0x00000001 - - - TXSKEWCALHS - High-speed skew calibration is started when txskewcalhs is -set high (assuming that PHY is in Stop state) - 0 - 1 - read-write - - - - - int_force0 - forces that affect the int_st0 register - 0xd8 - 32 - 0x00000000 - 0x001FFFFF - - - FORCE_DPHY_ERRORS_4 - force LP1 contention error ErrContentionLP1 from lane0 - 20 - 1 - read-write - - - FORCE_DPHY_ERRORS_3 - force LP0 contention error ErrContentionLP0 from lane0 - 19 - 1 - read-write - - - FORCE_DPHY_ERRORS_2 - force control error ErrControl from lane0 - 18 - 1 - read-write - - - FORCE_DPHY_ERRORS_1 - force ErrSyncEsc low-power data transmission synchronization error from lane 0 - 17 - 1 - read-write - - - FORCE_DPHY_ERRORS_0 - force ErrEsc escape entry error from lane0 - 16 - 1 - read-write - - - FORCE_ACK_WITH_ERR_15 - force the DSI protocal violation from the acknowledge error report - 15 - 1 - read-write - - - FORCE_ACK_WITH_ERR_14 - force the reserved from the acknowledge error report - 14 - 1 - read-write - - - FORCE_ACK_WITH_ERR_13 - force the invalid transmission length from the acknowledge error report - 13 - 1 - read-write - - - FORCE_ACK_WITH_ERR_12 - force the dsi vc id invalid from the acknowledge error report - 12 - 1 - read-write - - - FORCE_ACK_WITH_ERR_11 - force the not recongnized dsi data type from the acknowledge error report - 11 - 1 - read-write - - - FORCE_ACK_WITH_ERR_10 - force the checksum error from the acknowledge error report - 10 - 1 - read-write - - - FORCE_ACK_WITH_ERR_9 - force the ECC error multi-bit from the acknowledge error report - 9 - 1 - read-write - - - FORCE_ACK_WITH_ERR8 - force the ecc error sigle-bit from the acknowledge error report - 8 - 1 - read-write - - - FORCE_ACK_WITH_ERR7 - force the reserved from the acknowledge error report - 7 - 1 - read-write - - - FORCE_ACK_WITH_ERR6 - force the false control error fro the acknowledge error report - 6 - 1 - read-write - - - FORCE_ACK_WITH_ERR5 - force the peripheral timeout error from the acknowledge error report - 5 - 1 - read-write - - - FORCE_ACK_WITH_ERR4 - force the LP transmit sync error from the acknowledge error report - 4 - 1 - read-write - - - FORCE_ACK_WITH_ERR3 - force the Escap mode entry command error from the acknowledge error report - 3 - 1 - read-write - - - FORCE_ACK_WITH_ERR2 - force the EoT sync error from the acknowledge error report - 2 - 1 - read-write - - - FORCE_ACK_WITH_ERR1 - force the SoT sync error from the acknowledge error report - 1 - 1 - read-write - - - FORCE_ACK_WITH_ERR0 - force the SoT serror from the acknowledge error report - 0 - 1 - read-write - - - - - int_force1 - forces interrupts that affect the int_st1 register - 0xdc - 32 - 0x00000000 - 0x00181FFF - - - FORCE_TEAR_REQUEST_ERR - force tear_request has occurred but tear effect is not active in dsi host and device - 20 - 1 - read-write - - - FORCE_DPI_BUFF_PLD_UNDER - force an underflow when reading payload to build dsi packet for video mode - 19 - 1 - read-write - - - FORCE_GEN_PLD_RECEV_ERR - force that during a generic interface packet read back, the payload FIFO full - 12 - 1 - read-write - - - FORCE_GEN_PLD_RD_ERR - force that during a DCS read data, the payload FIFO becomes empty - 11 - 1 - read-write - - - FORCE_GEN_PLD_SEND_ERR - force the payload FIFO become empty when packet build - 10 - 1 - read-write - - - FORCE_GEN_PLD_WR_ERR - force the system tried to write a payload and FIFO is full - 9 - 1 - read-write - - - FORCE_GEN_CMD_WR_ERR - force the system tried to write a command and FIFO is full - 8 - 1 - read-write - - - FORCE_DPI_BPLD_WR_ERR - force the payload FIFO is full during a DPI pixel line storage - 7 - 1 - read-write - - - FORCE_EOPT_ERR - force that the EoTp packet has not been received at the end of the incoming peripheral transmission - 6 - 1 - read-write - - - FORCE_PKT_SIZE_ERR - force that the packet size error has been detected during the packet reception - 5 - 1 - read-write - - - FORCE_CRC_ERR - force that the CRC error has been detected in the reveived packet payload - 4 - 1 - read-write - - - FORCE_ECC_MULTI_ERR - force that the ECC multiple error has been detected in a revieved packet - 3 - 1 - read-write - - - FORCE_ECC_SIGLE_ERR - force that the ECC single error has been detected and corrected in a reveived packet - 2 - 1 - read-write - - - FORCE_TO_LP_TX - force that the low-power reception timeout counter reached the end and contention has been detected - 1 - 1 - read-write - - - FORCE_TO_HS_TX - force that the high-speed transmission timeout counter reached the end and contention has been detected - 0 - 1 - read-write - - - - - phy_tmr_rd - configures times related to PHY to perform some operations in lane byte clock cycle - 0xf4 - 32 - 0x00000000 - 0x00007FFF - - - MAX_RD_TIME - the maximum time required to perform a read command in lane byte clock cycles. - 0 - 15 - read-write - - - - - auto_ulps_min_time - configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane - 0xf8 - 32 - 0x00000000 - 0x00000FFF - - - ULPS_MIN_TIME - configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane - 0 - 12 - read-write - - - - - phy_mode - select phy mode - 0xfc - 32 - 0x00000000 - 0x00000001 - - - PHY_MODE - sel DPHY or CPHY - 0 - 1 - read-write - - - - - vid_shadow_ctrl - controls dpi shadow feature - 0x100 - 32 - 0x00000000 - 0x00010101 - - - VID_SHADOW_PIN_REQ - when set to 1, the video request is done by external pin - 16 - 1 - read-write - - - VID_SHADOW_REQ - when set to 1, request that the dpi register from regbank are copied to the auxiliary registers - 8 - 1 - read-write - - - VID_SHADOW_EN - when set to 1, DPI receives the active configuration from the auxiliary register - 0 - 1 - read-write - - - - - dpi_vcid_act - holds the value that controller is using for DPI_VCID - 0x10c - 32 - 0x00000000 - 0x00000003 - - - DPI_VCID - specifies the DPI virtual channel id that is indexed to the video mode packets - 0 - 2 - read-only - - - - - dpi_color_coding_act - holds the value that controller is using for DPI_COLOR_CODING - 0x110 - 32 - 0x00000000 - 0x0000010F - - - LOOSELY18_EN - avtivates loosely packed variant to 18-bit configuration - 8 - 1 - read-only - - - DIP_COLOR_CODING - configures the DPI color for video mode - 0 - 4 - read-only - - - - - dpi_lp_cmd_tim_act - holds value that controller is using for dpi_lp_cmd_time - 0x118 - 32 - 0x00000000 - 0x00FF00FF - - - OUTVACT_LPCMD_TIME - transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the VSA VBP and VFP regions. - 16 - 8 - read-only - - - INVACT_LPCMD_TIME - transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the vact regions. - 0 - 8 - read-only - - - - - vid_mode_cfg_act - holds value that controller is using for vid_mode_cfg - 0x138 - 32 - 0x00000000 - 0x000003FF - - - LP_CMD_EN - enable the command transmission only in low-power mode - 9 - 1 - read-only - - - FRAME_BTA_ACK_EN - enable the request for an acknowledge response at the end of a frame - 8 - 1 - read-only - - - LP_HFP_EN - enable the returne to low-power inside the HFP period when timing allows - 7 - 1 - read-only - - - LP_HBP_EN - enable the returne to low-power inside the HBP period when timing allows - 6 - 1 - read-only - - - LP_VACT_EN - enable the returne to low-power inside the VACT period when timing allows - 5 - 1 - read-only - - - LP_VFP_EN - enable the returne to low-power inside the VFP period when timing allows - 4 - 1 - read-only - - - LP_VBP_EN - enable the returne to low-power inside the VBP period when timing allows - 3 - 1 - read-only - - - LP_VSA_EN - enable the returne to low-power inside the VSA period when timing allows - 2 - 1 - read-only - - - VID_MODE_TYPE - specifies the video mode transmission type - 0 - 2 - read-only - - - - - vid_pkt_size_act - holds value that controller is using for vid_pkt_size - 0x13c - 32 - 0x00000000 - 0x00003FFF - - - VID_PKT_SIZE - the number of pixels in a single video packet - 0 - 14 - read-only - - - - - vid_num_chunks_act - holds value that controller is using for vid_num_chunks - 0x140 - 32 - 0x00000000 - 0x00001FFF - - - VID_NUM_CHUNKS - the number of chunks to be transmitted during a line period - 0 - 13 - read-only - - - - - vid_null_size_act - holds the value that controller is using for vid_null_size - 0x144 - 32 - 0x00000000 - 0x00001FFF - - - VID_NULL_SIZE - the number of bytes in side a null packet - 0 - 13 - read-only - - - - - vid_hsa_time_act - the value of vid_hsa_time - 0x148 - 32 - 0x00000000 - 0x00000FFF - - - VID_HSA_TIME - the horizontal synchronism active period in lane byte clock cycles - 0 - 12 - read-only - - - - - vid_hbp_time_act - the value that controller is using for vid_hbp_time - 0x14c - 32 - 0x00000000 - 0x00000FFF - - - VID_HBP_TIME - the horizontal back porch period in lane byte clock cycles - 0 - 12 - read-only - - - - - vid_hline_time_act - the value for vid_hline_time - 0x150 - 32 - 0x00000000 - 0x00007FFF - - - VID_HLINE_TIME - the size of total line: hsa+hbp+hact+hfp - 0 - 15 - read-only - - - - - vid_vsa_lines_act - value for vid_vsa_lines - 0x154 - 32 - 0x00000000 - 0x000003FF - - - VSA_LINES - vertical synchronism active period - 0 - 10 - read-only - - - - - vid_vbp_lines_act - value for vid_vbp_lines - 0x158 - 32 - 0x00000000 - 0x000003FF - - - VBP_LINES - vertical back porch period - 0 - 10 - read-only - - - - - vid_vfp_lines_act - value for vid_vfp_lines - 0x15c - 32 - 0x00000000 - 0x000003FF - - - VFP_LINES - vertical porch period - 0 - 10 - read-only - - - - - vid_vactive_lines_act - value for vid_vactive_lines - 0x160 - 32 - 0x00000000 - 0x00003FFF - - - V_ACTIVE_LINES - vertical active period - 0 - 14 - read-only - - - - - vid_pkt_status - status of fifo related to dpi - 0x168 - 32 - 0x00000000 - 0x0003000F - - - DPI_BUFF_PLD_FULL - This bit indicates the full status of the payload internal buffer -for video Mode. This bit is set to 0 for command Mode - 17 - 1 - read-only - - - DPI_BUFF_PLD_EMPTY - This bit indicates the empty status of the payload internal -buffer for video Mode. This bit is set to 0 for command Mod - 16 - 1 - read-only - - - DPI_PLD_W_FULL - This bit indicates the full status of write payload FIFO for -video Mode. This bit is set to 0 for command Mode - 3 - 1 - read-only - - - DPI_PLD_W_EMPTY - This bit indicates the empty status of write payload FIFO for -video Mode. This bit is set to 0 for command Mode - 2 - 1 - read-only - - - DPI_CMD_W_FULL - This bit indicates the full status of write command FIFO for -video Mode. This bit is set to 0 for command Mode - 1 - 1 - read-only - - - DPI_CMD_W_EMPTY - This bit indicates the empty status of write command FIFO -for video Mode. This bit is set to 0 for command Mode - 0 - 1 - read-only - - - - - sdf_3d_act - value for sdf_3d - 0x190 - 32 - 0x00000000 - 0x0001003F - - - SEND_3D_CFG - When set, causes the next VSS packet to include 3D control -payload in every VSS packet. - 16 - 1 - read-only - - - RIGHT_FIRST - This bit specifies the left/right order - 5 - 1 - read-only - - - SECOND_VSYNC - This field specifies whether there is a second VSYNC pulse -between Left and Right Images, when 3D Image Format is -Frame-based - 4 - 1 - read-only - - - FORMAT_3D - This field specifies 3D Image Format - 2 - 2 - read-only - - - MODE_3D - This field specifies 3D Mode On/Off and Display Orientation - 0 - 2 - read-only - - - - - - - MIPI_DSI1 - MIPI_DSI1 - MIPI_DSI - 0xf1024000 - - - MIPI_CSI0 - MIPI_CSI0 - MIPI_CSI - 0xf1028000 - - 0x0 - 0x2bc - registers - - - - version - version code - 0x0 - 32 - 0x3134302A - 0xFFFFFFFF - - - VERSION - version code - 0 - 32 - read-only - - - - - n_lanes - the number of active lanes - 0x4 - 32 - 0x00000001 - 0x00000007 - - - N_LANES - number of active data lanes - 0 - 3 - read-write - - - - - csi2_resetn - the internal logic of the controller goes into the reset state when active - 0x8 - 32 - 0x00000000 - 0x00000001 - - - CSI2_RESETN - DWC_mipi_csi2_host reset output, active low - 0 - 1 - read-write - - - - - int_st_main - contains the stateus of individual interrupt sources - 0xc - 32 - 0x00000000 - 0x000700FF - - - STATUS_INT_IPI4_FATAL - status of int_st_ipi_fatal - 18 - 1 - read-only - - - STATUS_INT_LINE - status of int_st_line - 17 - 1 - read-only - - - STATUS_INT_PHY - status of int_st_phy - 16 - 1 - read-only - - - STATUS_INT_ECC_CORRECTED - status of status_int_ecc_corrected - 7 - 1 - read-only - - - STATUS_INT_DATA_ID - status of status_int_data_id - 6 - 1 - read-only - - - STATUS_INT_PLD_CRC_FATAL - status of status_int_pld_crc_fatal - 5 - 1 - read-only - - - STATUS_INT_CRC_FRAME_FATAL - status of status_int_crc_frame_fatal - 4 - 1 - read-only - - - STATUS_INT_SEQ_FRAME_FATAL - status of status_int_seq_frame_fatal - 3 - 1 - read-only - - - STATUS_INT_BNDRY_FRAME_FATAL - status of int_st_bndry_frame_fatal - 2 - 1 - read-only - - - STATUS_INT_PKT_FATAL - status of int_st_pkt_fatal - 1 - 1 - read-only - - - STATUS_INT_PHY_FATAL - status of int_st_phy_fatal - 0 - 1 - read-only - - - - - data_ids_1 - programs data type fields for data ID monitors - 0x10 - 32 - 0x00000000 - 0x3F3F3F3F - - - DI3_DT - data type for programmed data ID 3 - 24 - 6 - read-write - - - DI2_DT - data type for programmed data ID 2 - 16 - 6 - read-write - - - DI1_DT - data type for programmed data ID 1 - 8 - 6 - read-write - - - DI0_DT - data type for programmed data ID 0 - 0 - 6 - read-write - - - - - data_ids_2 - programs data type fields for data ID monitors - 0x14 - 32 - 0x00000000 - 0x3F3F3F3F - - - DI7_DT - data type for programmed data ID 7 - 24 - 6 - read-write - - - DI6_DT - data type for programmed data ID 6 - 16 - 6 - read-write - - - DI5_DT - data type for programmed data ID 5 - 8 - 6 - read-write - - - DI4_DT - data type for programmed data ID 4 - 0 - 6 - read-write - - - - - int_st_ap_main - contains the status of individual interrupt sources - 0x2c - 32 - 0x00000000 - 0x00001FFF - - - STATUS_INT_IPI_FATAL - status of int_st_ipi_fatal - 12 - 1 - read-only - - - STATUS_INT_ST_AP_IPI_FATAL - status of int_st_ap_ipi_fatal - 11 - 1 - read-only - - - STATUS_INT_LINE - status of int_st_line - 10 - 1 - read-only - - - STATUS_INT_ECC_CORRECTED - status of status_int_ecc_corrected - 9 - 1 - read-only - - - STATUS_INT_DATA_ID - status of status_int_data_id - 8 - 1 - read-only - - - STATUS_INT_PLD_CRC_FATAL - status of status_int_pld_crc_fatal - 7 - 1 - read-only - - - STATUS_INT_PHY - status of int_st_phy - 6 - 1 - read-only - - - STATUS_INT_CRC_FRAME_FATAL - status of status_int_crc_frame_fatal - 5 - 1 - read-only - - - STATUS_INT_SEQ_FRAME_FATAL - status of status_int_seq_frame_fatal - 4 - 1 - read-only - - - STATUS_INT_BNDRY_FRAME_FATAL - status of int_st_bndry_frame_fatal - 3 - 1 - read-only - - - STATUS_INT_PKT_FATAL - status of int_st_pkt_fatal - 2 - 1 - read-only - - - STATUS_INT_PHY_FATAL - status of int_st_phy_fatal - 1 - 1 - read-only - - - STATUS_INT_ST_AP_GENERIC - status of int_st_ap_generic - 0 - 1 - read-only - - - - - phy_shutdownz - controls the phy shutdown mode - 0x40 - 32 - 0x00000000 - 0x00000001 - - - PHY_SHUTDOWNZ - shutdown input,active low - 0 - 1 - read-write - - - - - dphy_rstz - controls the phy reset mode - 0x44 - 32 - 0x00000000 - 0x00000001 - - - DPHY_RSTZ - phy reset output, active low - 0 - 1 - read-write - - - - - phy_rx - contains the status of rx-related signals from phy - 0x48 - 32 - 0x00010000 - 0x00030003 - - - PHY_RXCLKACTIVEHS - indicates the d-phy clock lane is actively receiving a ddr clock - 17 - 1 - read-only - - - PHY_RXULPSCLKNOT - active low. Indicates the d-phy clock lane module has entered the Ultra low power state - 16 - 1 - read-only - - - PHY_RXULLPSESC_1 - lane module 1 has entered the ultra low power mode - 1 - 1 - read-only - - - PHY_RXULPSESC_0 - lane module 0 has entered the ultra low power mode - 0 - 1 - read-only - - - - - phy_stopstate - contains the stopstate signal status from phy - 0x4c - 32 - 0x00000000 - 0x00010003 - - - PHY_STOPSTATECLK - d-phy clock lane in stop state - 16 - 1 - read-only - - - PHY_STOPSTATEDATA_1 - data lane 1 in stop state - 1 - 1 - read-only - - - PHY_STOPSTATEDATA_0 - data lane 0 in stop state - 0 - 1 - read-only - - - - - ipi_mode - selects how the ipi interface generates the video frame - 0x80 - 32 - 0x00000000 - 0x01010101 - - - IPI_ENABLE - enables the interface - 24 - 1 - read-write - - - IPI_CUT_THROUGH - cut-through mode state active when high - 16 - 1 - read-write - - - IPI_COLOR_COM - if color mode components are deliverd as follows: 0x0 48bit intercase 0x1: 16bit interface - 8 - 1 - read-write - - - IPI_MODE - indicates the video mode transmission type 0x0: camera timing 0x1:controller timing - 0 - 1 - read-write - - - - - ipi_vcid - selects the vritual channel processed by ipi - 0x84 - 32 - 0x00000000 - 0x0000000F - - - IPI_VCX_0_1 - virtual channel extension of data to be processed by pixel interface - 2 - 2 - read-write - - - IP_VCID - virtual channel of data to be processed by pixel interface - 0 - 2 - read-write - - - - - ipi_data_type - selects the data type processed by ipi - 0x88 - 32 - 0x00000000 - 0x0000013F - - - EMBENDED_DATA - enable embedded data processing on ipi interface - 8 - 1 - read-write - - - IPI_DATA_TYPE - data type of data to be processed by pixel interface - 0 - 6 - read-write - - - - - ipi_mem_flash - control the flush of ipi memory - 0x8c - 32 - 0x00000000 - 0x00000101 - - - IPI_AUTO_FLUSH - memory is automatically flashed at each vsync - 8 - 1 - read-write - - - IPI_FLUSH - flush ipi memory, this bit is auto clear - 0 - 1 - read-write - - - - - ipi_hsa_time - configures the video horizontal synchronism active time - 0x90 - 32 - 0x00000000 - 0x00000FFF - - - IPI_HSA_TIME - configures the Horizontal Synchronism Active period in pixclk cycles - 0 - 12 - read-write - - - - - ipi_hbp_time - configures the video horizontal synchronism back porch time - 0x94 - 32 - 0x00000000 - 0x00000FFF - - - IPI_HBP_TIME - configures the Horizontal Synchronism back porch period in pixclk cycles - 0 - 12 - read-write - - - - - ipi_hsd_time - configures the vedeo Horizontal Sync Delay time - 0x98 - 32 - 0x00000000 - 0x00000FFF - - - IPI_HSD_TIME - configures the Horizontal Sync Porch delay period in pixclk cycles - 0 - 12 - read-write - - - - - ipi_hline_time - configures the overall tiem for each video line - 0x9c - 32 - 0x00000000 - 0x00007FFF - - - IPI_HLIN_TIME - configures the size of the line time counted in pixclk cycles - 0 - 15 - read-write - - - - - ipi_softrstn - congtrols the ipi logic reset state - 0xa0 - 32 - 0x00000001 - 0x00000001 - - - IPI_SOFTRSTN - resets ipi one, active low - 0 - 1 - read-write - - - - - ipi_adv_features - configures advanced features for ipi mode - 0xac - 32 - 0x00000000 - 0x013F3F01 - - - IPI_SYNC_EVENT_MODE - for camera mode: 0x0- frame start do not trigger any sync event - 24 - 1 - read-write - - - EN_EMBEDDED - allows the use of embendded packets for ipi synchronization events - 21 - 1 - read-write - - - EN_BLANKING - allows the use of blankong packets for IPI synchronization events - 20 - 1 - read-write - - - EN_NULL - allows the use of null packets for IPI synchronization events - 19 - 1 - read-write - - - EN_LINE_START - allows the use of line start packets for ipi synchronization events - 18 - 1 - read-write - - - EN_VIDEO - allows the use of video packets for ipi synchronization events - 17 - 1 - read-write - - - LINE_EVENT_SELECTION - for camero mode, allows manual selection of the packet fo line delimiter as follows: 0x0-controller seletc it automaticlly 0x1-select packets from list programmed in 17:21 - 16 - 1 - read-write - - - IPI_DT - datatype to overwrite - 8 - 6 - read-write - - - IPI_DT_OVERWRITE - ignore datatype of the header using the programmed datatype for decoding - 0 - 1 - read-write - - - - - ipi_vsa_lines - configures the vertical synchronism active period - 0xb0 - 32 - 0x00000000 - 0x000003FF - - - IPI_VSA_LINES - configures the vertical synchronism active period measured in number of horizontal lines - 0 - 10 - read-write - - - - - ipi_vbp_lines - configures the verticall back porch period - 0xb4 - 32 - 0x00000000 - 0x000003FF - - - IPI_VBP_LINES - configuress the vertical back porch period measured in number of horizontal lines - 0 - 10 - read-write - - - - - ipi_vfp_lines - configures the vertical front porch period - 0xb8 - 32 - 0x00000000 - 0x000003FF - - - IPI_VFP_LINES - configures the vertical front porch period measured in number of horizontall lines - 0 - 10 - read-write - - - - - ipi_vactive_lines - configures the vertical resolution of video - 0xbc - 32 - 0x00000000 - 0x00003FFF - - - IPI_VACTIVE_LINES - configures the vertical active period measured in bumber of horizontal lines - 0 - 14 - read-write - - - - - vc_extension - active extra bits for virtual channel - 0xc8 - 32 - 0x00000000 - 0x00000001 - - - VCX - indicates status of virtual channel extension: 0-virtual channel extension is enable 1-legacy mode - 0 - 1 - read-write - - - - - phy_cal - contains the calibration signal status from synopsys d-phy - 0xcc - 32 - 0x00000000 - 0x00000001 - - - RXSKEWCALHS - a low-to-high transition on rxskewcalhs signal means the the phy has initiated the de-skew calibration - 0 - 1 - read-only - - - - - int_st_phy_fatal - groups the phy interruptions caused by phy packets discarded - 0xe0 - 32 - 0x00000000 - 0x00000103 - - - ERR_DESKEW - reports whenever data is lost due to an existent skew between lanes greater than 2 rxwordclkhs - 8 - 1 - read-only - - - PHY_ERRSOTSYNCHS_1 - start of transmission error on data lane1 - 1 - 1 - read-only - - - PHY_ERRSOTSYNCHS_0 - start of transmission error on data lane0 - 0 - 1 - read-only - - - - - int_msk_phy_fatal - interrupt mask for int_st_phy_fatal - 0xe4 - 32 - 0x00000000 - 0x00000103 - - - ERR_DESKEW - mask for err_deskew - 8 - 1 - read-write - - - MASK_PHY_ERRSOTSYNCHS_1 - mask for phy_errsotsynchs_1 - 1 - 1 - read-write - - - MASK_PHY_ERRSOTSYNCHS_0 - mask for phy_errsotsynchs_0 - 0 - 1 - read-write - - - - - int_force_phy_fatal - interrupt force register for test purposes - 0xe8 - 32 - 0x00000000 - 0x00000103 - - - ERR_DESKEW - force err_deskew - 8 - 1 - read-write - - - FORCE_PHY_ERRSOTSYNCHS_1 - force phy_errsotsynchs_1 - 1 - 1 - read-write - - - FORCE_PHY_ERRSOTSYNCHS_0 - force phy_errsotsynchs_0 - 0 - 1 - read-write - - - - - int_st_pkt_fatal - groups the fatal interruption related with packet construction - 0xf0 - 32 - 0x00000000 - 0x00000001 - - - ERR_ECC_DOUBLE - header ecc contains at least 2 errors - 0 - 1 - read-only - - - - - int_msk_pkt_fatal - interrupt mask for int_st_pkt_fatal - 0xf4 - 32 - 0x00000000 - 0x00000001 - - - MASK_ERR_ECC_DOUBLE - mask for err_ecc_double - 0 - 1 - read-write - - - - - int_force_pkt_fatal - interrupt force register is used for test purpos - 0xf8 - 32 - 0x00000000 - 0x00000001 - - - FORCE_ERR_ECC_DOUBLE - force err_ecc_double - 0 - 1 - read-write - - - - - int_st_phy - interruption caused by phy - 0x110 - 32 - 0x00000000 - 0x00030003 - - - PHY_ERRESC_1 - start of transmission error on data lane 1 - 17 - 1 - read-only - - - PHY_ERRESC_0 - start of transmission error on data lane 0 - 16 - 1 - read-only - - - PHY_ERRSOTHS_1 - start of transmission error on data lane 1 - 1 - 1 - read-only - - - PHY_ERRSOTHS_0 - start of transmission error on data lane 0 - 0 - 1 - read-only - - - - - int_msk_phy - interrupt mask for int_st_phy - 0x114 - 32 - 0x00000000 - 0x00030003 - - - MASK_PHY_ERRESC_1 - mask for phy_erresc_1 - 17 - 1 - read-write - - - MASK_PHY_ERRESC_0 - mask for phy_erresc_0 - 16 - 1 - read-write - - - MASK_PHY_ERRSOTHS_1 - mask for phy_errsoths_1 - 1 - 1 - read-write - - - MASK_PHY_ERRSOTHS_0 - mask for phy_errsoths_0 - 0 - 1 - read-write - - - - - int_force_phy - interrupt force register - 0x118 - 32 - 0x00000000 - 0x00030003 - - - FORCE_PHY_ERRESC_1 - force phy_erresc_1 - 17 - 1 - read-write - - - FORCE_PHY_ERRESC_0 - force phy_erresc_0 - 16 - 1 - read-write - - - FORCE_PHY_ERRSOTHS_1 - force phy_errsoths_1 - 1 - 1 - read-write - - - FORCE_PHY_ERRSOTHS_0 - force phy_errsoths_0 - 0 - 1 - read-write - - - - - int_st_ipi_fatal - fatal interruption caused by ipi interface - 0x140 - 32 - 0x00000000 - 0x0000003F - - - INT_EVENT_FIFO_OVERFLOW - reporting internal fifo overflow - 5 - 1 - read-only - - - PIXEL_IF_HLINE_ERR - horizontal line time error - 4 - 1 - read-only - - - PIXEL_IF_FIFO_NEMPTY_FS - the fifo of pixel interface is not empty at the starat of a new frame - 3 - 1 - read-only - - - PIXEL_IF_FRAME_SYNC_ERR - whenever in controller mode, notifies if a new frame is received but previous has not been completed - 2 - 1 - read-only - - - PIXEL_IF_FIFO_OVERFLOW - the fifo of pixel interface has lost information because some data arrived and fifo is already full - 1 - 1 - read-only - - - PIXEL_IF_FIFO_UNDERFLOW - the fifo has become empty before the expected bumber of pixels could be extracted to the pixel intefcese - 0 - 1 - read-only - - - - - int_msk_ipi_fatal - interrupt mask for int_st_ipi_fatal - 0x144 - 32 - 0x00000000 - 0x0000003F - - - MSK_INT_EVENT_FIFO_OVERFLOW - mask int_event_fifo_overflow - 5 - 1 - read-write - - - MSK_PIXEL_IF_HLINE_ERR - mask pixel_if_hline_err - 4 - 1 - read-write - - - MSK_PIXEL_IF_FIFO_NEMPTY_FS - mask pixel_if_fifo_nempty_fs - 3 - 1 - read-write - - - MSK_FRAME_SYNC_ERR - mask for pixel_if_frame_sync_err - 2 - 1 - read-write - - - MSK_PIXEL_IF_FIFO_OVERFLOW - mask for pixel_if_fifo_overflow - 1 - 1 - read-write - - - MSK_PIXEL_IF_FIFO_UNDERFLOW - mask for pixel_if_fifo_unterflow - 0 - 1 - read-write - - - - - int_force_ipi_fatal - interrupt force register - 0x148 - 32 - 0x00000000 - 0x0000003F - - - FORCE_INT_EVENT_FIFO_OVERFLOW - force int_event_fifo_overflow - 5 - 1 - read-write - - - FORCE_PIXEL_IF_HLINE_ERR - force pixel_if_hline_err - 4 - 1 - read-write - - - FORCE_PIXEL_IF_FIFO_NEMPTY_FS - force pixel_if_fifo_nempty_fs - 3 - 1 - read-write - - - FORCE_FRAME_SYNC_ERR - force for frame_sync_err - 2 - 1 - read-write - - - FORCE_PIXEL_IF_FIFO_OVERFLOW - force for pixel_if_fifo_overflow - 1 - 1 - read-write - - - FORCE_PIXEL_IF_FIFO_UNDERFLOW - force for pixel_if_fifo_underflow - 0 - 1 - read-write - - - - - int_st_ap_generic - groups and notifies which interruption bits caused the interruption - 0x180 - 32 - 0x00000000 - 0x0001FFFF - - - SYNCHRONIZER_PIXCLK_AP_ERR - ap error in synchronizer block for pixclk domain - 16 - 1 - read-only - - - SYNCHRONIZER_RXBYTECLKHS_AP_ERR - ap error in synchronizer block for rxbyteclkhs domain - 15 - 1 - read-only - - - SYNCHRONIZER_FPCLK_AP_ERR - ap error in synchronizer block for fpclk domain - 14 - 1 - read-only - - - ERR_HANDLE_AP_ERR - ap error in error handler block - 13 - 1 - read-only - - - ERR_MSGR_AP_ERR - ap error in err msgr block - 12 - 1 - read-only - - - PREP_OUTS_AP_ERR - ap error in prepare outs block - 10 - 2 - read-only - - - PACKET_ANALYZER_AP_ERR - ap error in packet analyzer block - 8 - 2 - read-only - - - PHY_ADAPTER_AP_ERR - ap error in phy adapter block - 7 - 1 - read-only - - - DESCRAMBLER_AP_ERR - ap error in descrambler block - 6 - 1 - read-only - - - PIPELINE_DELAY_AP_ERR - ap error in pipeline delay block - 5 - 1 - read-only - - - DE_SKEW_AP_ERR - ap error in de-skew block - 4 - 1 - read-only - - - REG_BANK_AP_ERR - ap error in register bank block - 2 - 2 - read-only - - - APB_AP_ERR - ap error in apb block - 0 - 2 - read-only - - - - - int_msk_ap_generic - interrupt mask for int_st_ap_generic - 0x184 - 32 - 0x00000000 - 0x0001FFFF - - - MSK_SYNCHRONIZER_PIXCLK_AP_ERR - No description available - 16 - 1 - read-write - - - MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR - No description available - 15 - 1 - read-write - - - MSK_SYNCHRONIZER_FPCLK_AP_ERR - No description available - 14 - 1 - read-write - - - MSK_ERR_HANDLE_AP_ERR - No description available - 13 - 1 - read-write - - - MSK_ERR_MSGR_AP_ERR - No description available - 12 - 1 - read-write - - - MSK_PREP_OUTS_AP_ERR - No description available - 10 - 2 - read-write - - - MSK_PACKET_ANALYZER_AP_ERR - No description available - 8 - 2 - read-write - - - MSK_PHY_ADAPTER_AP_ERR - No description available - 7 - 1 - read-write - - - MSK_DESCRAMBLER_AP_ERR - No description available - 6 - 1 - read-write - - - MSK_PIPELINE_DELAY_AP_ERR - No description available - 5 - 1 - read-write - - - MSK_DE_SKEW_AP_ERR - No description available - 4 - 1 - read-write - - - MSK_REG_BANK_AP_ERR - No description available - 2 - 2 - read-write - - - MSK_APB_AP_ERR - No description available - 0 - 2 - read-write - - - - - int_force_ap_generic - interrupt force register used for test purposes - 0x188 - 32 - 0x00000000 - 0x0001FFFF - - - FORCE_SYNCHRONIZER_PIXCLK_AP_ERR - No description available - 16 - 1 - read-write - - - FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR - No description available - 15 - 1 - read-write - - - FORCE_SYNCHRONIZER_FPCLK_AP_ERR - No description available - 14 - 1 - read-write - - - FORCE_ERR_HANDLE_AP_ERR - No description available - 13 - 1 - read-write - - - FORCE_ERR_MSGR_AP_ERR - No description available - 12 - 1 - read-write - - - FORCE_PREP_OUTS_AP_ERR - No description available - 10 - 2 - read-write - - - FORCE_PACKET_ANALYZER_AP_ERR - No description available - 8 - 2 - read-write - - - FORCE_PHY_ADAPTER_AP_ERR - No description available - 7 - 1 - read-write - - - FORCE_DESCRAMBLER_AP_ERR - No description available - 6 - 1 - read-write - - - FORCE_PIPELINE_DELAY_AP_ERR - No description available - 5 - 1 - read-write - - - FORCE_DE_SKEW_AP_ERR - No description available - 4 - 1 - read-write - - - FORCE_REG_BANK_AP_ERR - No description available - 2 - 2 - read-write - - - FORCE_APB_AP_ERR - No description available - 0 - 2 - read-write - - - - - int_st_ap_ipi_fatal - groups and notifies which interruption bits - 0x190 - 32 - 0x00000000 - 0x0000003F - - - REDUNDANCY_ERR - ap redundancy error in ipi1 - 5 - 1 - read-only - - - CRC_ERR - ap crc error in ipi1 - 4 - 1 - read-only - - - ECC_MULTIPLE_ERR - ap ecc multiple error in ipi1 - 3 - 1 - read-only - - - ECC_SINGLE_ERR - ap ecc sigle error in ipi1 - 2 - 1 - read-only - - - PARITY_RX_ERR - ap parity rx error in ipi1 - 1 - 1 - read-only - - - PARITY_TX_ERR - ap parity tx error in ipi1 - 0 - 1 - read-only - - - - - int_msk_ap_ipi_fatal - interrupt mask for int_st_ap_ipi_fatal controls - 0x194 - 32 - 0x00000000 - 0x0000003F - - - MASK_REDUNDANCY_ERR - No description available - 5 - 1 - read-only - - - MASK_CRC_ERR - No description available - 4 - 1 - read-only - - - MASK_ECC_MULTIPLE_ERR - No description available - 3 - 1 - read-only - - - MASK_ECC_SINGLE_ERR - No description available - 2 - 1 - read-only - - - MASK_PARITY_RX_ERR - No description available - 1 - 1 - read-only - - - MASK_PARITY_TX_ERR - No description available - 0 - 1 - read-only - - - - - int_force_ap_ipi_fatal - interrupt force register - 0x198 - 32 - 0x00000000 - 0x0000003F - - - FORCE_REDUNDANCY_ERR - No description available - 5 - 1 - read-only - - - FORCE_CRC_ERR - No description available - 4 - 1 - read-only - - - FORCE_ECC_MULTIPLE_ERR - No description available - 3 - 1 - read-only - - - FORCE_ECC_SINGLE_ERR - No description available - 2 - 1 - read-only - - - FORCE_PARITY_RX_ERR - No description available - 1 - 1 - read-only - - - FORCE_PARITY_TX_ERR - No description available - 0 - 1 - read-only - - - - - int_st_bndry_frame_fatal - fatal interruption related with matching frame start with frame end for a specific virtual channel - 0x280 - 32 - 0x00000000 - 0x0000FFFF - - - ERR_F_BNDRY_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-only - - - ERR_F_BNDRY_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-only - - - - - int_msk_bndry_frame_fatal - interrupt mask for int_st_bndry_frame_fatal - 0x284 - 32 - 0x00000000 - 0x0000FFFF - - - MSK_ERR_F_BNDRY_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - MSK_ERR_F_BNDRY_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_force_bndry_frame_fatal - interrupt force register is used for test purposes - 0x288 - 32 - 0x00000000 - 0x0000FFFF - - - FORCE_ERR_F_BNDRY_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - FORCE_ERR_F_BNDRY_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_st_seq_frame_fatal - fatal interruption related with matching frame start with frame end for a specific virtual channel - 0x290 - 32 - 0x00000000 - 0x0000FFFF - - - ERR_F_SEQ_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-only - - - ERR_F_SEQ_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-only - - - - - int_msk_seq_frame_fatal - interrupt mask for int_st_seq_frame_fatal - 0x294 - 32 - 0x00000000 - 0x0000FFFF - - - MSK_ERR_F_SEQ_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - MSK_ERR_F_SEQ_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_force_seq_frame_fatal - interrupt force register is used for test purposes - 0x298 - 32 - 0x00000000 - 0x0000FFFF - - - FORCE_ERR_F_SEQ_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - FORCE_ERR_F_SEQ_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_st_crc_frame_fatal - fatal interruption related with matching frame start with frame end for a specific virtual channel - 0x2a0 - 32 - 0x00000000 - 0x0000FFFF - - - ERR_F_CRC_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-only - - - ERR_F_CRC_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-only - - - ERR_F_CRC_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-only - - - ERR_F_CRC_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-only - - - ERR_F_CRC_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-only - - - ERR_F_CRC_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-only - - - ERR_F_CRC_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-only - - - ERR_F_CRC_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-only - - - ERR_F_CRC_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-only - - - ERR_F_CRC_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-only - - - ERR_F_CRC_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-only - - - ERR_F_CRC_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-only - - - ERR_F_CRC_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-only - - - ERR_F_CRC_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-only - - - ERR_F_CRC_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-only - - - ERR_F_CRC_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-only - - - - - int_msk_crc_frame_fatal - interrupt mask for int_st_crc_frame_fatal - 0x2a4 - 32 - 0x00000000 - 0x0000FFFF - - - MSK_ERR_F_CRC_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - MSK_ERR_F_CRC_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_force_crc_frame_fatal - interrupt force register is used for test purposes - 0x2a8 - 32 - 0x00000000 - 0x0000FFFF - - - FORCE_ERR_F_CRC_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - FORCE_ERR_F_CRC_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_st_pld_crc_frame_fatal - fatal interruption related with matching frame start with frame end for a specific virtual channel - 0x2b0 - 32 - 0x00000000 - 0x0000FFFF - - - ERR_CRC_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-only - - - ERR_CRC_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-only - - - ERR_CRC_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-only - - - ERR_CRC_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-only - - - ERR_CRC_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-only - - - ERR_CRC_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-only - - - ERR_CRC_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-only - - - ERR_CRC_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-only - - - ERR_CRC_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-only - - - ERR_CRC_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-only - - - ERR_CRC_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-only - - - ERR_CRC_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-only - - - ERR_CRC_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-only - - - ERR_CRC_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-only - - - ERR_CRC_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-only - - - ERR_CRC_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-only - - - - - int_msk_pld_crc_frame_fatal - interrupt mask for int_st_crc_frame_fatal - 0x2b4 - 32 - 0x00000000 - 0x0000FFFF - - - MSK_ERR_CRC_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - MSK_ERR_CRC_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - int_force_pld_crc_frame_fatal - interrupt force register is used for test purposes - 0x2b8 - 32 - 0x00000000 - 0x0000FFFF - - - FORCE_ERR_CRC_MATCH_VC15 - error matching frame start with frame end for virtual channel 15 - 15 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC14 - error matching frame start with frame end for virtual channel 14 - 14 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC13 - error matching frame start with frame end for virtual channel 13 - 13 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC12 - error matching frame start with frame end for virtual channel 12 - 12 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC11 - error matching frame start with frame end for virtual channel 11 - 11 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC10 - error matching frame start with frame end for virtual channel 10 - 10 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC9 - error matching frame start with frame end for virtual channel 9 - 9 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC8 - error matching frame start with frame end for virtual channel 8 - 8 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC7 - error matching frame start with frame end for virtual channel 7 - 7 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC6 - error matching frame start with frame end for virtual channel 6 - 6 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC5 - error matching frame start with frame end for virtual channel 5 - 5 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC4 - error matching frame start with frame end for virtual channel 4 - 4 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC3 - error matching frame start with frame end for virtual channel 3 - 3 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC2 - error matching frame start with frame end for virtual channel 2 - 2 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC1 - error matching frame start with frame end for virtual channel 1 - 1 - 1 - read-write - - - FORCE_ERR_CRC_MATCH_VC0 - error matching frame start with frame end for virtual channel 0 - 0 - 1 - read-write - - - - - - - MIPI_CSI1 - MIPI_CSI1 - MIPI_CSI - 0xf102c000 - - - LVB - LVB - LVB - 0xf1030000 - - 0x0 - 0x6c - registers - - - - CTRL - control register - 0x0 - 32 - 0x00000000 - 0x0F0307AF - - - SPLIT_CH_REVERSE - Just for split mode, reverse two channel data - 27 - 1 - read-write - - - SPLIT_CH_MODE - Just for split mode -1: two channel pixel data are not aligned -0: two channel pixel data are aligned - 26 - 1 - read-write - - - SPLIT_HSWHBP_WIDTH - Just for split mode, the sum of HSW and HBP width is even -1: yes -0: no - 25 - 1 - read-write - - - SPLIT_MODE_EN - Split mode enable: -1: enable -0: disable -Note: when using split mode, ch0/1 should be enabled, and should select same DI - 24 - 1 - read-write - - - DI1_VSYNC_POLARITY - DI 1 vsync polarity: -1: active low -0: active high - 17 - 1 - read-write - - - DI0_VSYNC_POLARITY - DI 0 vsync polarity: -1: active low -0: active high - 16 - 1 - read-write - - - LVDS_TXCLK_SHIFT - Shift the LVDS TX PHY clock in relation to the data. -000: txck is 7'b1100011 -001: txck is 7‘b1110001 -010: txck is 7‘b1111000 -011: txck is 7‘b1000111 -100: txck is 7‘b0001111 -101: txck is 7‘b0011110 -110: txck is 7‘b0111100 -111: txck is 7‘b1100011 - 8 - 3 - read-write - - - CH1_BIT_MAPPING - Channel 1 data protocol: -1: JEIDA standard -0: SPWG standard - 7 - 1 - read-write - - - CH0_BIT_MAPPING - Channel 0 data protocol: -1: JEIDA standard -0: SPWG standard - 5 - 1 - read-write - - - CH1_SEL - Channel 1 select: -1: select DI 1 -0: select DI 0 - 3 - 1 - read-write - - - CH1_EN - Channel 1 enable: -1: enable -0: disable - 2 - 1 - read-write - - - CH0_SEL - Channel 0 select: -1: select DI 1 -0: select DI 0 - 1 - 1 - read-write - - - CH0_EN - Channel 0 enable: -1: enable -0: disable - 0 - 1 - read-write - - - - - PHY_STAT - LVDS TX PHY Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - LVDS1_TX_PHY_PLL_LOCK - LVDS1 TX PHY PLL Lock indication Signal, 1 means pll already locked - 1 - 1 - read-only - - - LVDS0_TX_PHY_PLL_LOCK - LVDS0 TX PHY PLL Lock indication Signal, 1 means pll already locked - 0 - 1 - read-only - - - - - 2 - 0x4 - lvds0,lvds1 - PHY_POW_CTRL[%s] - no description available - 0x14 - 32 - 0x0000001F - 0x0000003F - - - PWON_PLL - pll power on - 5 - 1 - read-write - - - TXCK_PD - Power down control signal of channel txck -0: Normal operation -1: Power down channel - 4 - 1 - read-write - - - TX3_PD - Power down control signal of channel tx3 -0: Normal operation -1: Power down channel - 3 - 1 - read-write - - - TX2_PD - Power down control signal of channel tx2 -0: Normal operation -1: Power down channel - 2 - 1 - read-write - - - TX1_PD - Power down control signal of channel tx1 -0: Normal operation -1: Power down channel - 1 - 1 - read-write - - - TX0_PD - Power down control signal of channel tx0 -0: Normal operation -1: Power down channel - 0 - 1 - read-write - - - - - 10 - 0x8 - lvds0_tx0,lvds0_tx1,lvds0_tx2,lvds0_tx3,lvds0_txck,lvds1_tx0,lvds1_tx1,lvds1_tx2,lvds1_tx3,lvds1_txck - TX_PHY[%s] - no description available - 0x1c - - CTL0 - TX PHY Setting - 0x0 - 32 - 0x000A0358 - 0x001FFFFF - - - TX_IDLE - Force the high-speed differential signal to common mode. -This signal can be set during IP power up stage to prevent unexpected leakage current in TXP/TXN -0: Normal operation -1: Force TXPN /TXMN to common mode - 20 - 1 - read-write - - - TX_RTERM_EN - Inner Terminal Resistance enable -0: Disable rterm 2000ohm -1: Enable rterm 100ohm - 19 - 1 - read-write - - - TX_BUS_WIDTH - Parallel data bus width select： -000: 4-bit mode, txN_data[3:0] are valid, txN_data[11:4] can be arbitrary state. -001: 6-bit mode, txN_data[5:0] are valid, txN_data[11:6] can be arbitrary state. -010: 7-bit mode. txN_data[6:0] are valid, txN_data[11:7] can be arbitrary state. -011: 8-bit mode. txN_data[7:0] are valid, txN_data[11:8] can be arbitrary state. -100: 9-bit mode. txN_data[8:0] are valid, txN_data[11:9] can be arbitrary state. -101: 10-bit mode. txN_data[9:0] are valid, txN_data[11:10] can be arbitrary state. -110: 11-bit mode. txN_data[10:0] are valid, txN_data[11] can be arbitrary state. -111: 12-bit mode. txN_data[11:0] are valid - 16 - 3 - read-write - - - TX_PHASE_SEL - data/clock lane output phase adjustment: -0000: 0 -0001: data lane is 1/32, clock lane is 1/16 -0010: data lane is 2/32, clock lane is 2/16 -0011: data lane is 3/32, clock lane is 3/16 -0100: data lane is 4/32, clock lane is 4/16 -0101: data lane is 5/32, clock lane is 5/16 -0110: data lane is 6/32, clock lane is 6/16 -0111: data lane is 7/32, clock lane is 7/16 -1000: data lane is 8/32, clock lane is 8/16 -1001: data lane is 9/32, clock lane is 9/16 -1010: data lane is 10/32, clock lane is 10/16 -1011: data lane is 11/32, clock lane is 11/16 -1100: data lane is 12/32, clock lane is 12/16 -1101: data lane is 13/32, clock lane is 13/16 -1110: data lane is 14/32, clock lane is 14/16 -1111: data lane is 15/32, clock lane is 15/16 - 12 - 4 - read-write - - - TX_VCOM - output Common Mode Voltage adjustment(Unit: V). -0000: 0.7 -0001: 0.8 -0010: 0.9 -0011: 1.0 -0100: 1.1 -0101: 1.2 -0110: 1.3 -0111: 1.4 -1000~1111: 1.5 - 8 - 4 - read-write - - - TX_AMP - Output voltage Adjustment(Unit: mV). -0000 : 50 -0001: 100 -0010: 150 -0011: 200 -0100: 250 -0101: 300 -0110: 350 -0111: 400 -1000: 450 -1001: 500 -1010: 550 -1011~1111: 600 - 4 - 4 - read-write - - - TX_SR - output slew-rate trimming -00: slowest slew-rate; -11: fastest slew-rate - 2 - 2 - read-write - - - TX_DEEMP - output de-emphasis level trimming(Unit: dB) -00: 0 -01: 2.5 -10: 6.0 -11: 6.0 - 0 - 2 - read-write - - - - - CTL1 - TX_PHY Setting - 0x4 - 32 - 0x00000080 - 0x000FFFFF - - - TX_CTL - No description available - 0 - 20 - read-write - - - - - - - - PIXEL_MUX - PIXEL_MUX - PIXELMUX - 0xf1034000 - - 0x0 - 0x64 - registers - - - - PIXMUX - pixel path mux register - 0x0 - 32 - 0x00000000 - 0x3FFF00FF - - - RGB_EN - RGB pixel bus enable - 29 - 1 - read-write - - - RGB_SEL - RGB pixel bus selection -1: LCDC1 -0: LCDC0 - 28 - 1 - read-write - - - GWC1_EN - GWC1 pixel bus enable - 27 - 1 - read-write - - - GWC1_SEL - GWC1 pixel bus selection -1: LCDC1 -0: LCDC0 - 26 - 1 - read-write - - - GWC0_EN - GWC0 pixel bus enable - 25 - 1 - read-write - - - GWC0_SEL - GWC0 pixel bus selection -1: LCDC1 -0: LCDC0 - 24 - 1 - read-write - - - LVB_DI1_EN - LVB DI1 pixel bus enable - 23 - 1 - read-write - - - LVB_DI1_SEL - LVB DI1 pixel bus selection -1: LCDC1 -0: LCDC0 - 22 - 1 - read-write - - - LVB_DI0_EN - LVB DI0 pixel bus enable - 21 - 1 - read-write - - - LVB_DI0_SEL - LVB DI0 pixel bus selection -1: LCDC1 -0: LCDC0 - 20 - 1 - read-write - - - DSI1_EN - DSI0 pixel bus enable - 19 - 1 - read-write - - - DSI1_SEL - DSI0 pixel bus selection -1: LCDC1 -0: LCDC0 - 18 - 1 - read-write - - - DSI0_EN - DSI1 pixel bus enable - 17 - 1 - read-write - - - DSI0_SEL - DSI1 pixel bus selection -1: LCDC1 -0: LCDC0 - 16 - 1 - read-write - - - CAM1_EN - CAM1 pixel bus enable - 7 - 1 - read-write - - - CAM1_SEL - CAM1 pixel bus selection -111: Reserved -110: LCB1 -101: LCB0 -100: LCDC1 -011: LCDC0 -010: CSI1 -001: CSI0 -000: DVP - 4 - 3 - read-write - - - CAM0_EN - CAM0 pixel bus enable - 3 - 1 - read-write - - - CAM0_SEL - CAM0 pixel bus selection -111: Reserved -110: LCB1 -101: LCB0 -100: LCDC1 -011: LCDC0 -010: CSI1 -001: CSI0 -000: DVP - 0 - 3 - read-write - - - - - 2 - 0x4 - DSI0_CFG,DSI1_CFG - DSI_SETTING[%s] - no description available - 0x4 - 32 - 0x00200005 - 0xFFFF000F - - - DSI_DATA_ENABLE - DSI pixel data type enable: -Bit0: RGB565_CFG1 -Bit1: RGB565_CFG2 -Bit2: RGB565_CFG3 -Bit3: RGB666_CFG1 -Bit4: RGB666_CFG2 -Bit5: RGB888 -Bit6: RGB_10BIT -Bit7: RGB_12BIT, no support -Bit8: YUV422_12BIT, no support -Bit9: YUV422_10BIT, no support -Bit10: YUV422_8BIT, no support -Bit11:YUV420_8BIT,no support -others: Reserved - 16 - 16 - read-write - - - DSI_DATA_TYPE - DSI input pixel data type: -‘h0: RGB565_CFG1 -‘h1: RGB565_CFG2 -‘h2: RGB565_CFG3 -‘h3: RGB666_CFG1 -‘h4: RGB666_CFG2 -‘h5: RGB888 -‘h6: RGB_10BIT -‘h7: RGB_12BIT, no support -‘h8:YUV422_12BIT,no support -‘h9: YUV422_10BIT, no support -‘ha: YUV422_8BIT, no support -‘hb: YUV420_8BIT,no support -‘hc~’hf: Reserved - 0 - 4 - read-write - - - - - MISC - common register - 0xc - 32 - 0x00000000 - 0x00000003 - - - LVB_DI1_CTL - LVB DI1 optional general purpose control which is usually unused by display - 1 - 1 - read-write - - - LVB_DI0_CTL - LVB DI0 optional general purpose control which is usually unused by display - 0 - 1 - read-write - - - - - GPR_WR_D0 - gpr write-read register 0 - 0x10 - 32 - 0x0000000F - 0x07F7F3FF - - - CSI1_CFG_AP_IF_CHECK_EN - csi1 apb interface parity check enable - 22 - 5 - read-write - - - CSI1_CFG_AP_IF_INT_EN - csi1 apb interface error interrupt enable - 21 - 1 - read-write - - - CSI1_CFG_APB_SLVERROR_EN - csi1 apb interface error check enable - 20 - 1 - read-write - - - CSI0_CFG_AP_IF_CHECK_EN - csi0 apb interface parity check enable - 14 - 5 - read-write - - - CSI0_CFG_AP_IF_INT_EN - csi0 apb interface error interrupt enable - 13 - 1 - read-write - - - CSI0_CFG_APB_SLVERROR_EN - csi0 apb interface error check enable - 12 - 1 - read-write - - - DSI1_DPIUPDATECFG - dsi1 dpi update configure - 9 - 1 - read-write - - - DSI1_DPICOLORM - dsi1 dpi cholor mode control - 8 - 1 - read-write - - - DSI1_DPISHUTDN - dsi1 dpi shuntdown control - 7 - 1 - read-write - - - DSI0_DPIUPDATECFG - dsi0 dpi update configure - 6 - 1 - read-write - - - DSI0_DPICOLORM - dsi0 dpi cholor mode control - 5 - 1 - read-write - - - DSI0_DPISHUTDN - dsi0 dpi shuntdown control - 4 - 1 - read-write - - - CSI1_SOFT_RESET_N - csi controller 1 reset, active low - 3 - 1 - read-write - - - CSI0_SOFT_RESET_N - csi controller 0 reset, active low - 2 - 1 - read-write - - - DSI1_SOFT_RESET_N - dsi controller 1 reset, active low - 1 - 1 - read-write - - - DSI0_SOFT_RESET_N - dsi controller 0 reset, active low - 0 - 1 - read-write - - - - - GPR_WR_D1 - gpr write-read register 1 - 0x14 - 32 - 0x00000000 - 0x0FFFFFFF - - - JPEG_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 24 - 4 - read-write - - - PDMA_P1_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 20 - 4 - read-write - - - PDMA_P0_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 16 - 4 - read-write - - - LCDC1_P1_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 12 - 4 - read-write - - - LCDC1_P0_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 8 - 4 - read-write - - - LCDC0_P1_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 4 - 4 - read-write - - - LCDC0_P0_CTRL - bit0: select cam0; -bit1: select cam1; -bit2: select jpeg; -bit3: select pdma - 0 - 4 - read-write - - - - - GPR_WR_D2 - gpr write-read register 2 - 0x18 - 32 - 0x20003800 - 0x3EFF7FFF - - - TX_PHY0_PORT_PLL_RDY_SEL - tx phy0 port_pll_rdy_sel - 29 - 1 - read-write - - - TX_PHY0_RATE_LVDS - tx phy0 rate_lvds - 27 - 2 - read-write - - - TX_PHY0_PHY_MODE - tx phy0 phy_mode - 25 - 2 - read-write - - - TX_PHY0_REFCLK_DIV - tx phy0 refclk_div - 20 - 4 - read-write - - - TX_PHY0_IDDQ_EN - tx phy0 iddq_en - 19 - 1 - read-write - - - TX_PHY0_RESET_N - tx phy0 reset, active low - 18 - 1 - read-write - - - TX_PHY0_SHUTDOWNZ - tx phy0 shutdownz, active low - 17 - 1 - read-write - - - TX_PHY0_BYPS_CKDET - tx phy0 byps_ckdet - 16 - 1 - read-write - - - TX_PHY0_PLL_DIV - tx phy0 pll_div - 0 - 15 - read-write - - - - - GPR_WR_D3 - gpr write-read register 3 - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_PHY0_PLL_CTRL - tx phy0 pll_ctrl - 0 - 32 - read-write - - - - - GPR_WR_D4 - gpr write-read register 4 - 0x20 - 32 - 0x00000900 - 0xFFFFFDFF - - - TX_PHY0_TXCK_BIST_EN - tx phy0 txck_bist_en - 31 - 1 - read-write - - - TX_PHY0_TX3_BIST_EN - tx phy0 tx3_bist_en - 30 - 1 - read-write - - - TX_PHY0_TX2_BIST_EN - tx phy0 tx2_bist_en - 29 - 1 - read-write - - - TX_PHY0_TX1_BIST_EN - tx phy0 tx1_bist_en - 28 - 1 - read-write - - - TX_PHY0_TX0_BIST_EN - tx phy0 tx0_bist_en - 27 - 1 - read-write - - - TX_PHY0_TXCK_LPBK_EN - tx_phy0 txck_lpbk_en - 26 - 1 - read-write - - - TX_PHY0_TX3_LPBK_EN - tx_phy0 tx3_lpbk_en - 25 - 1 - read-write - - - TX_PHY0_TX2_LPBK_EN - tx_phy0 tx2_lpbk_en - 24 - 1 - read-write - - - TX_PHY0_TX1_LPBK_EN - tx_phy0 tx1_lpbk_en - 23 - 1 - read-write - - - TX_PHY0_TX0_LPBK_EN - tx_phy0 tx0_lpbk_en - 22 - 1 - read-write - - - TX_PHY0_TXCK_PAT_SEL - tx phy0 txck_pat_sel - 20 - 2 - read-write - - - TX_PHY0_TX3_PAT_SEL - tx phy0 tx3_pat_sel - 18 - 2 - read-write - - - TX_PHY0_TX2_PAT_SEL - tx phy0 tx2_pat_sel - 16 - 2 - read-write - - - TX_PHY0_TX1_PAT_SEL - tx phy0 tx1_pat_sel - 14 - 2 - read-write - - - TX_PHY0_TX0_PAT_SEL - tx phy0 tx0_pat_sel - 12 - 2 - read-write - - - TX_PHY0_DSI0_PRBS_DISABLE - tx phy0 dsi0_prbs_disable - 11 - 1 - read-write - - - TX_PHY0_DSI0_PRBS_START - tx phy0 dsi0_prbs_start - 10 - 1 - read-write - - - TX_PHY0_CKPHY_CTL - tx phy0 ckphy_ctl - 0 - 9 - read-write - - - - - GPR_WR_D5 - gpr write-read register 5 - 0x24 - 32 - 0x20003800 - 0x3EFF7FFF - - - TX_PHY1_PORT_PLL_RDY_SEL - tx phy1 port_pll_rdy_sel - 29 - 1 - read-write - - - TX_PHY1_RATE_LVDS - tx phy1 rate_lvds - 27 - 2 - read-write - - - TX_PHY1_PHY_MODE - tx phy1 phy_mode - 25 - 2 - read-write - - - TX_PHY1_REFCLK_DIV - tx phy1 refclk_div - 20 - 4 - read-write - - - TX_PHY1_IDDQ_EN - tx phy1 iddq_en - 19 - 1 - read-write - - - TX_PHY1_RESET_N - tx phy1 reset, active low - 18 - 1 - read-write - - - TX_PHY1_SHUTDOWNZ - tx phy1 shutdownz, active low - 17 - 1 - read-write - - - TX_PHY1_BYPS_CKDET - tx phy1 byps_ckdet - 16 - 1 - read-write - - - TX_PHY1_PLL_DIV - tx phy1 pll_div - 0 - 15 - read-write - - - - - GPR_WR_D6 - gpr write-read register 6 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_PHY1_PLL_CTRL - tx phy1 pll_ctrl - 0 - 32 - read-write - - - - - GPR_WR_D7 - gpr write-read register 7 - 0x2c - 32 - 0x00000900 - 0xFFFFFDFF - - - TX_PHY1_TXCK_BIST_EN - tx phy1 txck_bist_en - 31 - 1 - read-write - - - TX_PHY1_TX3_BIST_EN - tx phy1 tx3_bist_en - 30 - 1 - read-write - - - TX_PHY1_TX2_BIST_EN - tx phy1 tx2_bist_en - 29 - 1 - read-write - - - TX_PHY1_TX1_BIST_EN - tx phy1 tx1_bist_en - 28 - 1 - read-write - - - TX_PHY1_TX0_BIST_EN - tx phy1 tx0_bist_en - 27 - 1 - read-write - - - TX_PHY1_TXCK_LPBK_EN - tx_phy1 txck_lpbk_en - 26 - 1 - read-write - - - TX_PHY1_TX3_LPBK_EN - tx_phy1 tx3_lpbk_en - 25 - 1 - read-write - - - TX_PHY1_TX2_LPBK_EN - tx_phy1 tx2_lpbk_en - 24 - 1 - read-write - - - TX_PHY1_TX1_LPBK_EN - tx_phy1 tx1_lpbk_en - 23 - 1 - read-write - - - TX_PHY1_TX0_LPBK_EN - tx_phy1 tx0_lpbk_en - 22 - 1 - read-write - - - TX_PHY1_TXCK_PAT_SEL - tx phy1 txck_pat_sel - 20 - 2 - read-write - - - TX_PHY1_TX3_PAT_SEL - tx phy1 tx3_pat_sel - 18 - 2 - read-write - - - TX_PHY1_TX2_PAT_SEL - tx phy1 tx2_pat_sel - 16 - 2 - read-write - - - TX_PHY1_TX1_PAT_SEL - tx phy1 tx1_pat_sel - 14 - 2 - read-write - - - TX_PHY1_TX0_PAT_SEL - tx phy1 tx0_pat_sel - 12 - 2 - read-write - - - TX_PHY1_DSI0_PRBS_DISABLE - tx phy1 dsi0_prbs_disable - 11 - 1 - read-write - - - TX_PHY1_DSI0_PRBS_START - tx phy1 dsi0_prbs_start - 10 - 1 - read-write - - - TX_PHY1_CKPHY_CTL - tx phy1 ckphy_ctl - 0 - 9 - read-write - - - - - GPR_WR_D8 - gpr write-read register 8 - 0x30 - 32 - 0x00000000 - 0xFF7C0003 - - - RX_PHY0_BRUN_IN_MODE - rx phy0 burn_in_mode - 31 - 1 - read-write - - - RX_PHY0_BURN_IN_EN_PAD - rx phy0 burn_in_en_pad - 30 - 1 - read-write - - - RX_PHY0_LPBK_MODE - rx phy0 lpbk_mode - 28 - 2 - read-write - - - RX_PHY0_BIST_FREQ_TRIM - rx phy0 bist_freq_trim - 24 - 4 - read-write - - - RX_PHY0_RX0_BIST_EN - rx phy0 rx0_bist_en rx1_bist_en - 22 - 1 - read-write - - - RX_PHY0_BIST_MODE - rx phy0 bist_mode - 21 - 1 - read-write - - - RX_PHY0_BIST_EN_PAD - rx phy0 bist_en_pad - 20 - 1 - read-write - - - RX_PHY0_BIST_EN - rx phy0 bist_en - 19 - 1 - read-write - - - RX_PHY0_BIST_CKIN_SEL - rx phy0 bist_ckin_sel - 18 - 1 - read-write - - - RX_PHY0_PHY_MODE - rx phy0 phy_mode - 0 - 2 - read-write - - - - - GPR_WR_D9 - gpr write-read register 9 - 0x34 - 32 - 0x00000000 - 0xFF7C0003 - - - RX_PHY1_BRUN_IN_MODE - rx phy1 burn_in_mode - 31 - 1 - read-write - - - RX_PHY1_BURN_IN_EN_PAD - rx phy1 burn_in_en_pad - 30 - 1 - read-write - - - RX_PHY1_LPBK_MODE - rx phy1 lpbk_mode - 28 - 2 - read-write - - - RX_PHY1_BIST_FREQ_TRIM - rx phy1 bist_freq_trim - 24 - 4 - read-write - - - RX_PHY1_RX0_BIST_EN - rx phy1 rx0_bist_en rx1_bist_en - 22 - 1 - read-write - - - RX_PHY1_BIST_MODE - rx phy1 bist_mode - 21 - 1 - read-write - - - RX_PHY1_BIST_EN_PAD - rx phy1 bist_en_pad - 20 - 1 - read-write - - - RX_PHY1_BIST_EN - rx phy1 bist_en - 19 - 1 - read-write - - - RX_PHY1_BIST_CKIN_SEL - rx phy1 bist_ckin_sel - 18 - 1 - read-write - - - RX_PHY1_PHY_MODE - rx phy1 phy_mode - 0 - 2 - read-write - - - - - GPR_RO_D0 - gpr read-only register 0 - 0x38 - 32 - 0x00000000 - 0x0000FFFF - - - TX_PHY1_CTL_O - {2'b0, -tx_phy1_tx3_ctl_o,tx_phy1_tx2_ctl_o, -tx_phy1_tx1_ctl_o,tx_phy1_tx0_ctl_o, -tx_phy1_txck_ctl_o,tx_phy1_pll_dtest_o} - 8 - 8 - read-only - - - TX_PHY0_CTL_O - {2'b0, -tx_phy0_tx3_ctl_o,tx_phy0_tx2_ctl_o, -tx_phy0_tx1_ctl_o,tx_phy0_tx0_ctl_o, -tx_phy0_txck_ctl_o,tx_phy0_pll_dtest_o} - 0 - 8 - read-only - - - - - GPR_RO_D1 - gpr read-only register 1 - 0x3c - 32 - 0x00000000 - 0x0003FFFF - - - IRQ_CSI0_AP - interrupt of csi0 ap - 17 - 1 - read-only - - - CSI0_CFG_CSI_AP_DIAG_FAULTS - csi0 ap diag faults - 5 - 12 - read-only - - - CSI0_STA_AP_IF_INT_STA - csi0 apb parity check interrupt satus - 0 - 5 - read-only - - - - - GPR_RO_D2 - gpr read-only register 2 - 0x40 - 32 - 0x00000000 - 0x0003FFFF - - - IRQ_CSI1_AP - interrupt of csi1 ap - 17 - 1 - read-only - - - CSI1_CFG_CSI_AP_DIAG_FAULTS - csi1 ap diag faults - 5 - 12 - read-only - - - CSI1_STA_AP_IF_INT_STA - csi1 apb parity check interrupt satus - 0 - 5 - read-only - - - - - GPR_RO_D3 - gpr read-only register 3 - 0x44 - 32 - 0x00000000 - 0x0000FFFF - - - RX_PHY0_RXCK_CTLO - rx phy0 rxck_ctlo - 8 - 8 - read-only - - - RX_PHY0_RX1_CTLO - rx phy0 rx1_ctlo - 4 - 4 - read-only - - - RX_PHY0_RX0_CTLO - rx phy0 rx0_ctlo - 0 - 4 - read-only - - - - - GPR_RO_D4 - gpr read-only register 4 - 0x48 - 32 - 0x00000000 - 0x0000FFFF - - - RX_PHY1_RXCK_CTLO - rx phy1 rxck_ctlo - 8 - 8 - read-only - - - RX_PHY1_RX1_CTLO - rx phy1 rx1_ctlo - 4 - 4 - read-only - - - RX_PHY1_RX0_CTLO - rx phy1 rx0_ctlo - 0 - 4 - read-only - - - - - GPR_RO_D5 - gpr read-only register 5 - 0x4c - 32 - 0x00000000 - 0x0000FFFF - - - DSI0_PRBS_STATE - dsi0_prbs_state for debug only - 12 - 4 - read-only - - - TX_PHY0_TXCK_BIST_DONE_PAD - tx phy0 txck_done_pad - 11 - 1 - read-only - - - TX_PHY0_TXCK_BIST_OK_PAD - tx phy0 txck_ok_pad - 10 - 1 - read-only - - - TX_PHY0_TXCK_BIST_DONE - tx phy0 txck_bist_done - 9 - 1 - read-only - - - TX_PHY0_TX3_BIST_DONE - tx phy0 tx3_bist_done - 8 - 1 - read-only - - - TX_PHY0_TX2_BIST_DONE - tx phy0 tx2_bist_done - 7 - 1 - read-only - - - TX_PHY0_TX1_BIST_DONE - tx phy0 tx1_bist_done - 6 - 1 - read-only - - - TX_PHY0_TX0_BIST_DONE - tx phy0 tx0_bist_done - 5 - 1 - read-only - - - TX_PHY0_TXCK_BIST_OUT - tx phy0 txck_bist_out - 4 - 1 - read-only - - - TX_PHY0_TX3_BIST_OUT - tx phy0 tx3_bist_out - 3 - 1 - read-only - - - TX_PHY0_TX2_BIST_OUT - tx phy0 tx2_bist_out - 2 - 1 - read-only - - - TX_PHY0_TX1_BIST_OUT - tx phy0 tx1_bist_out - 1 - 1 - read-only - - - TX_PHY0_TX0_BIST_OUT - tx phy0 tx0_bist_out - 0 - 1 - read-only - - - - - GPR_RO_D6 - gpr read-only register 6 - 0x50 - 32 - 0x00000000 - 0x0000FFFF - - - DSI1_PRBS_STATE - dsi1_prbs_state for debug only - 12 - 4 - read-only - - - TX_PHY1_TXCK_BIST_DONE_PAD - tx phy1 txck_done_pad - 11 - 1 - read-only - - - TX_PHY1_TXCK_BIST_OK_PAD - tx phy1 txck_ok_pad - 10 - 1 - read-only - - - TX_PHY1_TXCK_BIST_DONE - tx phy1 txck_bist_done - 9 - 1 - read-only - - - TX_PHY1_TX3_BIST_DONE - tx phy1 tx3_bist_done - 8 - 1 - read-only - - - TX_PHY1_TX2_BIST_DONE - tx phy1 tx2_bist_done - 7 - 1 - read-only - - - TX_PHY1_TX1_BIST_DONE - tx phy1 tx1_bist_done - 6 - 1 - read-only - - - TX_PHY1_TX0_BIST_DONE - tx phy1 tx0_bist_done - 5 - 1 - read-only - - - TX_PHY1_TXCK_BIST_OUT - tx phy1 txck_bist_out - 4 - 1 - read-only - - - TX_PHY1_TX3_BIST_OUT - tx phy1 tx3_bist_out - 3 - 1 - read-only - - - TX_PHY1_TX2_BIST_OUT - tx phy1 tx2_bist_out - 2 - 1 - read-only - - - TX_PHY1_TX1_BIST_OUT - tx phy1 tx1_bist_out - 1 - 1 - read-only - - - TX_PHY1_TX0_BIST_OUT - tx phy1 tx0_bist_out - 0 - 1 - read-only - - - - - GPR_RO_D7 - gpr read-only register 7 - 0x54 - 32 - 0x00000000 - 0x0000007F - - - RX_PHY0_BURN_IN_OK_PAD - rx_phy0_burn_in_ok_pad - 6 - 1 - read-only - - - RX_PHY0_RX1_BIST_DONE - rx phy0 rx1_bist_done - 5 - 1 - read-only - - - RX_PHY0_RX0_BIST_DONE - rx phy0 rx0_bist_done - 4 - 1 - read-only - - - RX_PHY0_RX1_BIST_OUT - rx phy0 rx1_bist_out - 3 - 1 - read-only - - - RX_PHY0_RX0_BIST_OUT - rx phy0 rx0_bist_out - 2 - 1 - read-only - - - RX_PHY0_BIST_OK_PAD - rx phy0 bist_ok_pad - 1 - 1 - read-only - - - RX_PHY0_BIST_DONE_PAD - rx phy0 bist_done_pad - 0 - 1 - read-only - - - - - GPR_RO_D8 - gpr read-only register 8 - 0x58 - 32 - 0x00000000 - 0x0000007F - - - RX_PHY1_BURN_IN_OK_PAD - rx_phy1_burn_in_ok_pad - 6 - 1 - read-only - - - RX_PHY1_RX1_BIST_DONE - rx phy1 rx1_bist_done - 5 - 1 - read-only - - - RX_PHY1_RX0_BIST_DONE - rx phy1 rx0_bist_done - 4 - 1 - read-only - - - RX_PHY1_RX1_BIST_OUT - rx phy1 rx1_bist_out - 3 - 1 - read-only - - - RX_PHY1_RX0_BIST_OUT - rx phy1 rx0_bist_out - 2 - 1 - read-only - - - RX_PHY1_BIST_OK_PAD - rx phy1 bist_ok_pad - 1 - 1 - read-only - - - RX_PHY1_BIST_DONE_PAD - rx phy1 bist_done_pad - 0 - 1 - read-only - - - - - GPR_RO_D9 - gpr read-only register 9 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - - - GPR_WR1_CLR_D0 - gpr write1 set/no-write clr register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR_WR1_CLR_DATA - gpr register, write 1 /no-write set/clr matching bit - 0 - 32 - read-write - - - - - - - LCB - LCB - LCB - 0xf1038000 - - 0x0 - 0x98 - registers - - - - CTRL - control register - 0x0 - 32 - 0x00000010 - 0x000001F3 - - - LVDS_RXCK_SEL - just for LVDS Display mode and CAM LINK mode, clock selection: -1: LVDS1 RXCK -0: LVDS0 RXCK - 8 - 1 - read-write - - - CAM_LINK_WIDTH - just for CAM LINK mode, data width: -00: 24bit -01: 30bit -10: 36bit -11: reserved - 6 - 2 - read-write - - - BIT_MAPPING - just for LVDS Display mode, data protocol: -1: JEIDA standard -0: SPWG standard - 5 - 1 - read-write - - - DATA_WIDTH - just for LVDS Display mode, data width: -1: 24bit -0: 18bit(3line) - 4 - 1 - read-write - - - MODE - mode selection： -00: lvds display(4 line), two LVDS RX PHY must be LVDS display mode -01: cam link(4 line), two LVDS RX PHY must be LVDS display mode -10: sync code(2 line), LVDS RX PHY must be LVDS cameral mode -11: sync code(1line), LVDS RX PHY must be LVDS cameral mode - 0 - 2 - read-write - - - - - PHY_STAT - LVDS RX PHY Status register - 0x64 - 32 - 0x00000000 - 0x00000003 - - - LVDS1_RX_PHY_DLL_LOCK - LVDS1 RX PHY DLL Lock indication Signal, 1 means dll already locked - 1 - 1 - read-only - - - LVDS0_RX_PHY_DLL_LOCK - LVDS0 RX PHY DLL Lock indication Signal, 1 means dll already locked - 0 - 1 - read-only - - - - - 2 - 0x4 - lvds0,lvds1 - PHY_POW_CTRL[%s] - no description available - 0x68 - 32 - 0x0000000F - 0x0000000F - - - IDDQ_EN - Power down control signal of channel rxck/rx1/rx0 -0: Normal operation -1: Power down channel - 3 - 1 - read-write - - - RXCK_PD - Power down control signal of channel rxck -0: Normal operation -1: Power down channel - 2 - 1 - read-write - - - RX1_PD - Power down control signal of channel rx1 -0: Normal operation -1: Power down channel - 1 - 1 - read-write - - - RX0_PD - Power down control signal of channel rx0 -0: Normal operation -1: Power down channel - 0 - 1 - read-write - - - - - 4 - 0x4 - lvds0_rx0,lvds0_rx1,lvds1_rx0,lvds1_rx1 - PHY_D_CTRL[%s] - no description available - 0x70 - 32 - 0x00080E29 - 0x003FFFFF - - - RX_VCOM - bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable -bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground - 20 - 2 - read-write - - - RX_RTERM - Terminal impedance regulation control signal -0000: hi-z; -0001: 150ohm; -1000:100ohm; -1111:75ohm - 16 - 4 - read-write - - - RX_CTL - bit 0 : Lane N Data MSB first enable signal. 0: LSB ; 1: MSB -bit 1 : Lane N Data Polarity signal. 0: Not inverting; 1: Inverting -bit [4:2] : Phase difference between the output first bit data (rxN[6:0]) and the input clock (RCKP/N) in LVDS Display Mode. -bit 5 : Reserved -bit 6 : Output data sampling clock control signal -0: Sampling using the rising edge of the clock pck. -1: Sampling using the falling edge of the clock pck. -bit 7 : Reserved -bit 8 : Data Lane N Skew adjust enable in LVDS Camera Mode. -bit [12:9] : Data Lane N Skew adjust; 0000: min; 0111: default; 1111: max. -bit [15:13] : Reserved - 0 - 16 - read-write - - - - - 2 - 0x4 - lvds0_rxck,lvds1_rxck - PHY_CK_CTRL[%s] - no description available - 0x80 - 32 - 0x00080435 - 0x003FFFFF - - - RX_VCOM - bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable -bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground - 20 - 2 - read-write - - - RX_RTERM - Terminal impedance regulation control signal -0000: hi-z; -0001: 150ohm; -1000:100ohm; -1111:75ohm - 16 - 4 - read-write - - - RX_CTL - bit 0 : DLL loop delay adjustment minimum control signal -0: used for RCKP/RCKN’s frequency is 40Mhz~70Mhz -1:used for RCKP/RCKN’s frequency is 70Mhz~110Mhz -bit [2:1] : DLL loop delay adjustment current regulation control signal. 00: min; 11: max -bit 3 : Reserved -bit 4 : Clock Lane Skew adjust enable in LVDS Camera Mode. -bit [7:5] : Bus width selection in LVDS Camera Mode -000: 4bit; 001:6bit; 010:7bit; 011:8bit; 100:9bit; 101:10bit; 110:11bit; 111:12bit. -bit [10:8] : DDR Clock duty cycle adjust in LVDS Camera Mode. -bit [15:11] : Reserved - 0 - 16 - read-write - - - - - 2 - 0x4 - lvds0,lvds1 - PHY_ADJ_CTRL[%s] - no description available - 0x88 - 32 - 0x414101FF - 0xFFFF01FF - - - LVDS_RX0_DLINE_ADJ - LVDS RX PHY RX0 line: -bit [7:0] : Lane N skew adjustment control signal between data and clock -0000000: max; 1111111: min -bit 8 : Reserved - 24 - 8 - read-write - - - LVDS_RX1_DLINE_ADJ - LVDS RX PHY RX1 line: -bit [7:0] : Lane N skew adjustment control signal between data and clock -0000000: max; 1111111: min -bit 8 : Reserved - 16 - 8 - read-write - - - LVDS_DLL_TUNING_INT - LVDS RX PHY RXCK line: -DLL loop delay coarse adjustment initial signal -00000000: min ; 11111111: max - 0 - 9 - read-write - - - - - 2 - 0x4 - lvds0,lvds1 - PHY_SU_CTRL[%s] - no description available - 0x90 - 32 - 0x00000001 - 0x000000FF - - - SU_CTRL - bit [2:0] : Reference voltage/current adjustment control signal. 000: min; 111: max -bit [3] : Internal bias circuit selection signal. 0: from Bandgap Mode; 1: from self-bias mode -bit [7:4] : Reserved - 0 - 8 - read-write - - - - - - - GPU - GPU - GPU - 0xf1080000 - - 0x0 - 0x50c - registers - - - - AQHiClockControl - clock control register - 0x0 - 32 - 0x00070100 - 0x000F3FFE - - - ISOLATE_GPU - isolate GPU bit, used for power on/off - 19 - 1 - read-write - - - IDLE_VG - vg pipe is idle - 18 - 1 - read-only - - - IDLE2_D - 2D pipe is idle or not present - 17 - 1 - read-only - - - IDLE3_D - 3D pipe is idle or not present - 16 - 1 - read-only - - - DISABLE_RAM_POWER_OPTIMIZATION - disables ram power optimization - 13 - 1 - read-write - - - SOFT_RESET - soft reset the IP - 12 - 1 - read-write - - - DISABLE_DEBUG_REGISTERS - disable debug registers - 11 - 1 - read-write - - - DISABLE_RAM_CLOCK_GATING - disables clock gating for rams - 10 - 1 - read-write - - - FSCALE_CMD_LOAD - core clock frequency scale value enable - 9 - 1 - read-write - - - FSCALE_VAL - core clock frequency scale value - 2 - 7 - read-write - - - CLK2D_DIS - disable 2D/VG clock - 1 - 1 - read-write - - - - - AQHildle - idle status register - 0x4 - 32 - 0x80001FFF - 0x80001FFF - - - AXI_LP - axi is in low power mode - 31 - 1 - read-only - - - IDLE_BLT - BLT is idle or not present - 12 - 1 - read-only - - - IDLE_TS - Tessellation Engine is idle - 11 - 1 - read-only - - - IDLE_FP - FP is idle or not present - 10 - 1 - read-only - - - IDLE_IM - Image Engine is idle - 9 - 1 - read-only - - - IDLE_VG - Vector Graphics Engine is idle - 8 - 1 - read-only - - - IDLE_TX - TX is idle or not present - 7 - 1 - read-only - - - IDLE_RA - RA is idle or not present - 6 - 1 - read-only - - - IDLE_SE - SE is idle or not present - 5 - 1 - read-only - - - IDLE_PA - PA is idle or not present - 4 - 1 - read-only - - - IDLE_SH - SH is idle or not present - 3 - 1 - read-only - - - IDLE_PE - Pixel engine is idle - 2 - 1 - read-only - - - IDLE_DE - DE is dile or not present - 1 - 1 - read-only - - - IDLE_FE - 0: fetch engine is busy 1:fetch engine is idle - 0 - 1 - read-only - - - - - AQIntrAcknowledge - interrupt acknoledge register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTR_VEC - for each interrupt event, 0=clear,1=interrupt active - 0 - 32 - read-only - - - - - AQIntrEnbl - interrupt enable register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTR_ENBL_VEC - 0=disable interrupt; 1=enable interrupt - 0 - 32 - read-write - - - - - GCChipRev - chip revison register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - revision - 0 - 32 - read-only - - - - - GCChipDate - chip date register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATE - date - 0 - 32 - read-only - - - - - gcregHIChipPatchRev - chip patch revision register - 0x98 - 32 - 0x00000000 - 0x000000FF - - - PATCH_REV - patch revision - 0 - 8 - read-only - - - - - gcProductID - product identification register - 0xa8 - 32 - 0x03002655 - 0x0FFFFFFF - - - TYPE - product type is 3:VG - 24 - 4 - read-only - - - NUM - product number is 265 - 4 - 20 - read-only - - - GRADE_LEVEL - 0:None_no extra letter on the product name for this core 1:nano 5:nano ultra - 0 - 4 - read-only - - - - - gcModulePowerControls - module power control register - 0x100 - 32 - 0x00000020 - 0xFFFF00F7 - - - TURN_OFF_COUNTER - counter value for clock gating the module if the module is idle for this amout of clock cycles - 16 - 16 - read-write - - - TURN_ON_COUNTER - number of clock cycle gating the module if the modules is idle for this amout of clockk cycles - 4 - 4 - read-write - - - DISABLE_STARVE_MODULE_CLOCK_GATING - disable module level clock gating for starve/idle condition - 2 - 1 - read-write - - - DISABLE_STALL_MODULE_CLOCK_GATING - disable module level clock gating for stall condition - 1 - 1 - read-write - - - ENABLE_MODULE_CLOCK_GATING - enable module level clock gating - 0 - 1 - read-write - - - - - gcModulePowerModuleControl - module power module control register - 0x104 - 32 - 0x00000000 - 0x00001B05 - - - DISABLE_MODULE_CLOCKGATING_FLEXA - disables module level clock gating for flexa, not supported for all variants - 12 - 1 - read-write - - - DISABLE_MODULE_CLOCK_GATING_TS - disables module level clock gating for TS - 11 - 1 - read-write - - - DISABLE_MODULE_CLOCK_GATING_IM - disables module level clock gating for IM - 9 - 1 - read-write - - - DISABLE_MODULE_CLOCK_GATING_VG - disables module lelvel clock gating for VG - 8 - 1 - read-write - - - DISABLE_MODULE_CLOCK_GATING_PE - disables module level clock gating for PE - 2 - 1 - read-write - - - DISABLE_MODULE_CLOCK_GATING_FE - disables module level clock gating for FE - 0 - 1 - read-write - - - - - gcModulePowerModuleStatus - module power module status register - 0x108 - 32 - 0x00000000 - 0x00001B05 - - - MODULE_CLOCK_GATED_FLEXA - module level ckock gating is on for flexa - 12 - 1 - read-only - - - MODULE_CLOCK_GATED_TS - module level ckock gating is on for ts - 11 - 1 - read-only - - - MODULE_CLOCK_GATED_IM - module level clock gating is on for IM - 9 - 1 - read-only - - - MODULE_CLOCK_GATED_VG - module level clock gating is on for VG - 8 - 1 - read-only - - - MODULE_CLOCK_GATED_PE - module level clock gating is on for PE - 2 - 1 - read-only - - - MODULE_CLOCK_GATED_FE - module level clock gating is on for FE - 0 - 1 - read-only - - - - - AQMemoryFePageTable - fetch engine page table base address register - 0x400 - 32 - 0x00000000 - 0xFFFFF000 - - - BASE_ADDRESS - base address for the FE virtual address lookup table - 12 - 20 - read-write - - - - - AQMemoryDebug - memory debug register - 0x414 - 32 - 0x3C000000 - 0x3F0000FF - - - ZCOMP_LIMIT - not relevant for vector graphics IP - 24 - 6 - read-write - - - MAX_OUTSTANDING_READS - limits the total number of outstanding read requests - 0 - 8 - read-write - - - - - AQRegisterTimingControl - timing control register - 0x42c - 32 - 0x00030000 - 0x001FFFFF - - - POWER_DOWN - powerdown memory - 20 - 1 - read-write - - - FAST_WTC - WTC for fast rams - 18 - 2 - read-write - - - FAST_RTC - RTC for fast rams - 16 - 2 - read-write - - - FOR_RF2P - for 2 port ram - 8 - 8 - read-write - - - FOR_RF1P - for 1 port ram - 0 - 8 - read-write - - - - - gcregFetchAddress - fetch command buffer base address register - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRESS - address of command buffer - 2 - 30 - read-write - - - TYPE - 0=system 2=vritual 1=local - 0 - 2 - read-write - - - - - gcregFetchControl - fetch control register - 0x504 - 32 - 0x00000000 - 0x001FFFFF - - - COUNT - number of 64bit words to fetch - 0 - 21 - read-write - - - - - gcregCurrentFetchAddress - current fetch command address register - 0x508 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRESS - address - 0 - 32 - read-only - - - - - - - ENET0 - ENET0 - ENET - 0xf1100000 - - 0x0 - 0x3028 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. -Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -Note: - Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, -that is, the current frame does not use the updated value. -- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. -When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. -When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. -When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. -This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - or SGMII port. When this bit is reset, no such information is driven to the PHY. -This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. -When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). -Lower values are not considered. -In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. -When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. -In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, -this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. -This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. -This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. -In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. -In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. -When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. -This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. -The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. -It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) -of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. -The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) -and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). -When this bit is reset, this function is disabled. -When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. -When a collision occurs on the GMII or MII interface, -the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. -When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. -All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. -When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays - (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. -This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. -The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, -when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, -but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. -For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, -the transmitter transmits and collision happens. -Because of collision, the transmitter needs to back off and then defer again after back off completion. -In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, -the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. -The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, -the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. -When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, -this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. -When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. -When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. -When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. -The following conditions should be true for the Pause frames processing: -- Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. -- Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. -- Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. -Note: This field should be set to 01 only when the Condition 1 is true, -that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. -Otherwise, the Pause frame filtering may be inconsistent. -When Condition 1 is false, the Pause frames are considered as generic control frames. -Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, -you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. -When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. -When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. -When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, -the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. -When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. -The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. -The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) -ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved -When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. -For example, -when CSR clock is of 100 MHz frequency and you program these bits as 1010, -then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. -Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, -it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. -During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - Register 5 is invalid until this bit is cleared by the MAC. -Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. -Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. -The subsequent read or write operation should happen only after the previous operation is complete. -Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, -there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation -or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. -If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of -the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). -When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. -The threshold values should be always less than the Pause Time configured in Bits[31:16]. - For example, if PT = 100H (256 slot-times), and PLT = 01, -then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. -The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. -When this bit is set, the MAC can also detect Pause frames with unicast address of the station. -This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. -When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. -When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. -In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. -In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - To initiate a Pause frame, the Application must set this bit to 1'b1. -During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. -After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. -The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, -when this bit is set (and TFE is set), then backpressure is asserted by the MAC. -During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. -This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. -When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). -A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. -When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, -the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, -only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. -When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. -The following list describes the bits of this field: - - Bits [15:13]: User Priority -- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) -- Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). -The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. -The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. -Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, -the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. -This bit is then self-cleared and the power-down mode is disabled. -The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. -The frames, received by the MAC after this bit is cleared, are forwarded to the application. -This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. -Note: You can gate-off the CSR clock during the power-down mode. -However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Register - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. -This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, -the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. -The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. -If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), -when the MAC is in the LPI mode, the MAC exits the LPI mode. -When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. -When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. -When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. -This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. -This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. -The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - the LPI pattern to the PHY and before it resumes the normal transmission. -The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. -This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. -This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: -- The system time value equals or exceeds the value specified in the Target Time High and Low registers. -- There is an overflow in the seconds register. - - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). -This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). -This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is RO. The bit value is fixed at 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - 4 - 0x8 - 1,2,3,4 - MAC_ADDR[%s] - no description available - 0x48 - - HIGH - MAC Address High Register - 0x0 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. -When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. -Each bit controls the masking of the bytes as follows: -- Bit 29: Register 18[15:8] -- Bit 28: Register 18[7:0] -- Bit 27: Register 19[31:24] - -... -- Bit 24: Register 19[7:0] -You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - LOW - MAC Address Low Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0000003F - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. -It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. -The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. -When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -this field is used as watchdog timeout for a received frame. - If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. -Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). -Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - mmc_cntrl - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. -This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. -Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - mmc_intr_rx - MMC Receive Interrupt - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_tx - MMC Transmit Interrupt - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_mask_rx - MMC Receive Interrupt mask - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - mmc_intr_mask_tx - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - tx64octets_gb - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx65to127octets_gb - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx128to255octets_gb - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx256to511octets_gb - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx512to1023octets_gb - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx1024tomaxoctets_gb - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - rxframecount_gb - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - mmc_ipc_intr_mask_rx - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_ipc_intr_rx - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - rxipv4_gd_fms - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - 1 - 0x20 - 0 - L3_L4_CFG[%s] - no description available - 0x400 - - L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x0 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. -When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. -This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. -When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. -The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, -which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. -The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. -This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. -When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. -Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. -This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. -When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. -The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L4_Addr - Layer 4 Address Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_Addr_0 - Layer 3 Address 0 Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_1 - Layer 3 Address 1 Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_2 - Layer 3 Address 2 Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_Addr_3 - Layer 3 Address 3 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. -This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). -Note: Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - When reset, the rollover value of sub-second register is 0x7FFF_FFFF. -The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. -This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. -This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the initialization is complete. -The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. -You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. -For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) -when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. -When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. -In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Target Time Registers when this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). -This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. -The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. -These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. -This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. -This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. -When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. -These bits are applicable only if the number of Auxiliary snapshots is more than one. -One bit is assigned for each trigger as shown in the following list: -- Bit 16: Auxiliary trigger 0 -- Bit 17: Auxiliary trigger 1 -- Bit 18: Auxiliary trigger 2 -- Bit 19: Auxiliary trigger 3 - The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description available - 7 - 1 - read-only - - - TSTARGT2 - No description available - 6 - 1 - read-only - - - TSTRGTERR1 - No description available - 5 - 1 - read-only - - - TSTARGT1 - No description available - 4 - 1 - read-only - - - TSTRGTERR - No description available - 3 - 1 - read-only - - - AUXTSTRIG - No description available - 2 - 1 - read-only - - - TSTARGT - No description available - 1 - 1 - read-only - - - TSSOVF - No description available - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - write-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - write-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - write-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. -The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. -For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. -Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. -In the digital rollover mode, the PPS output frequency is an average number. -The actual clock is of different frequency that gets synchronized every second. For example: -- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms -- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - - One clock of 50 percent duty cycle and 537 ms period - - Second clock of 463 ms period (268 ms low and 195 ms high) -- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - - Three clocks of 50 percent duty cycle and 268 ms period - - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-only - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-only - - - - - PPS0_INTERVAL - PPS Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if the PTP reference clock is 50 MHz (period of 20ns), -and desired interval between rising edges of PPS0 signal output is 100ns - (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - 3 - 0x20 - 1,2,3 - PPS[%s] - no description available - 0x780 - - TGTTM_SEC - PPS Target Time Seconds Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Targeers wht Time Registen this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - INTERVAL - PPS Interval Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), -then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - WIDTH - PPS Width Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, - if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), -then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. -The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. -By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), -whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, -the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. -Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. -The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. -When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. -This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. -When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. -When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. -PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. -Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. -If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). -This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. -The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. -This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: -- Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. -When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. -The address skipping starts from the end of current descriptor to the start of next descriptor. -When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. -It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. -Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. -Note: - The Software reset function is driven only by this bit. -Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. -- The reset operation is completed only when all resets in all active clock domains are de-asserted. -Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. -The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. -The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. -The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. -To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. -Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. -When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. --or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. -To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. -Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. -Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. -This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. - The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the Power Management feature is enabled. -Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac -to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): -- PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event -- SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - read any of the following corresponding registers: -- PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) -- SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) -- General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in -Register 7 (Interrupt Enable Register): -- Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt -- Register 5[14]: Early Receive Interrupt Only unmasked bits - (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following -when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive FIFO Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt -- Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. -This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. -The Receive Process is suspended. To resume processing Receive descriptors, - the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. -This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. -When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, -and the specific frame status information is updated in the descriptor. -The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). -When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. -To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. -When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, -this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. -This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. -When this bit is set, the TTC values specified in Bits [16:14] are ignored. -This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. -This bit is cleared internally when the flushing operation is complete. -The Operation Mode register should not be written to until this bit is cleared. -The data which is already accepted by the MAC transmitter is not flushed. -It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. - Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. -In addition, full frames with a length less than the threshold are also transmitted. - These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -Descriptor acquisition is attempted either from the current position in the list, -which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), -or from the position retained when transmission was stopped previously. - If the DMA does not own the current descriptor, -transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Transmission command is effective only when transmission is stopped. -If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - then the DMA behavior is unpredictable. When this bit is reset, -the transmission process is placed in the Stopped state after completing the transmission of the current frame. -The Next Descriptor position in the Transmit List is saved, -and it becomes the current position when transmission is restarted. -To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. -The new value is considered when this bit is set again. -The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB -The de-assertion is effective only after flow control is asserted. - If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. -These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) -These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. -These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, -an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. -These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. -Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, -the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. -When reset, the flow control operation is disabled. - This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). -However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), -then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, -the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. -When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. -If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, -then the frame is dropped irrespective of the FEF bit setting. -However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. -Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: -- The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - - The advanced timestamp feature is not selected but the extended status is selected. -The extended status is available with the following features: -- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations -- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC -When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, -that is, frames that are larger than the computed giant frame limit. -When reset, the MAC does not drop the giant frames in the Rx FIFO. -Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: -- Configurations in which IP Checksum Offload (Type 1) is selected in Rx -- Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format -- Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. -Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. -In addition, full frames with length less than the threshold are automatically transferred. -The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. -These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. -The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. -The descriptor acquisition is attempted from the current position in the list, -which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. -If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Receive command is effective only when the reception has stopped. - If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. -When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. -The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. -The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. -When this bit is reset, normal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): - - Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt - - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. -When this bit is reset, the abnormal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt - - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, -that is, the Rx FIFO overflows with the overflow frame counter at maximum value. -In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, -that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. -This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. -The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer -of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. -When the watchdog timer runs out, the RI bit is set and the timer is stopped. -The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. -When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. -When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. -Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. -Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. -When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). -When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). -- When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. -- When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. -If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - CTRL0 - Control Register 0 - 0x3000 - 32 - 0x00000000 - 0x00003F3F - - - ENET0_RXCLK_DLY_SEL - No description available - 8 - 6 - read-write - - - ENET0_TXCLK_DLY_SEL - No description available - 0 - 6 - read-write - - - - - CTRL2 - Control Register 1 - 0x3008 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt - 29 - 1 - read-write - - - ENET0_REFCLK_OE - set to enable output 50MHz clock to rmii phy. -User should set it if use soc internal clock as refclk - 19 - 1 - read-write - - - ENET0_PHY_INF_SEL - PHY mode select -001RGMII; 100RMII; -should be set before config IOMUX, otherwise may cause glitch for RGMII - 13 - 3 - read-write - - - ENET0_FLOWCTRL - flow control request - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - RMII mode output clock pad select -set to use txck as RMII refclk; -clr to use rxck as RMII refclk; default 0(rxck) -refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. - 10 - 1 - read-write - - - - - - - USB0 - USB0 - USB - 0xf1120000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFFB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - PRM - Asynchronous Schedule start- Write only， host mode only。 -this bit is used to notify hostcontroller to start async schedule immediately. - 12 - 1 - write-only - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 16 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - SDXC0 - SDXC0 - SDXC - 0xf1130000 - - 0x0 - 0x3008 - registers - - - - SDMASA - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BLOCKCNT_SDMASA - 32-bit Block Count (SDMA System Address) -- SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. -When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. -It can be accessed only if no transaction is executing. Reading this register during data transfers may -return an invalid value. -- 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. -The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. -This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. -Following are the values for BLOCKCNT_SDMASA: -- 0xFFFF_FFFF: 4G - 1 Block -- -- 0x0000_0002: 2 Blocks -- 0x0000_0001: 1 Block -- 0x0000_0000: Stop Count -Note: -- For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. -The system address must be programmed in the ADMA System Address register. -- For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. -Auto CMD23 cannot be used with SDMA. -- This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - 0 - 32 - read-write - - - - - BLK_ATTR - No description available - 0x4 - 32 - 0x00020210 - 0xFFFF7FFF - - - BLOCK_CNT - 16-bit Block Count -- If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. -- If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. -Following are the values for BLOCK_CNT: -- 0x0: Stop Count -- 0x1: 1 Block -- 0x2: 2 Blocks -- . -- 0xFFFF: 65535 Blocks -Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - 16 - 16 - read-write - - - SDMA_BUF_BDARY - SDMA Buffer Boundary -These bits specify the size of contiguous buffer in system memory. -The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. -Values: -- 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary -- 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary -- 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary -- 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary -- 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary -- 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary -- 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary -- 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - 12 - 3 - read-write - - - XFER_BLOCK_SIZE - Transfer Block Size -These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. -Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: -- 0x1: 1 byte -- 0x2: 2 bytes -- 0x3: 3 bytes -- . -- 0x1FF: 511 byte -- 0x200: 512 byt es -- . -- 0x800: 2048 bytes -Note: This register must be programmed with a non-zero value for data transfer. - 0 - 12 - read-write - - - - - CMD_ARG - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ARGUMNET - Command Argument -These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - 0 - 32 - read-write - - - - - CMD_XFER - No description available - 0xc - 32 - 0x00000000 - 0x3FFF01FF - - - CMD_INDEX - Command Index -These bits are set to the command number that is specified in bits 45-40 of the Command Format. - 24 - 6 - read-write - - - CMD_TYPE - Command Type -These bits indicate the command type. -Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. -Values: -0x3 (ABORT_CMD): Abort -0x2 (RESUME_CMD): Resume -0x1 (SUSPEND_CMD): Suspend -0x0 (NORMAL_CMD): Normal - 22 - 2 - read-write - - - DATA_PRESENT_SEL - Data Present Select -This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: -Command using the CMD line -Command with no data transfer but using busy signal on the DAT[0] line -Resume Command -Values: -0x0 (NO_DATA): No Data Present -0x1 (DATA): Data Present - 21 - 1 - read-write - - - CMD_IDX_CHK_ENABLE - Command Index Check Enable -This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. -If the value is not the same, it is reported as a Command Index error. -Note: -Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. -For the tuning command, this bit must always be set to enable the index check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 20 - 1 - read-write - - - CMD_CRC_CHK_ENABLE - Command CRC Check Enable -This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. -Note: -CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. -For the tuning command, this bit must always be set to 1 to enable the CRC check. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 19 - 1 - read-write - - - SUB_CMD_FLAG - Sub Command Flag -This bit distinguishes between a main command and a sub command. -Values: -0x0 (MAIN): Main Command -0x1 (SUB): Sub Command - 18 - 1 - read-write - - - RESP_TYPE_SELECT - Response Type Select -This bit indicates the type of response expected from the card. -Values: -0x0 (NO_RESP): No Response -0x1 (RESP_LEN_136): Response Length 136 -0x2 (RESP_LEN_48): Response Length 48 -0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - 16 - 2 - read-write - - - RESP_INT_DISABLE - Response Interrupt Disable -The Host Controller supports response check function to avoid overhead of response error check by the Host driver. -Response types of only R1 and R5 can be checked by the Controller. -If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. -If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. -The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. -Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. -Values: -- 0x0 (ENABLED): Response Interrupt is enabled -- 0x1 (DISABLED): Response Interrupt is disabled - 8 - 1 - read-write - - - RESP_ERR_CHK_ENABLE - Response Error Check Enable -The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. -If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. -Note: -- Response error check must not be enabled for any response type other than R1 and R5. -- Response check must not be enabled for the tuning command. -Values: -- 0x0 (DISABLED): Response Error Check is disabled -- 0x1 (ENABLED): Response Error Check is enabled - 7 - 1 - read-write - - - RESP_TYPE - Response Type R1/R5 -This bit selects either R1 or R5 as a response type when the Response Error Check is selected. -Error statuses checked in R1: -OUT_OF_RANGE -ADDRESS_ERROR -BLOCK_LEN_ERROR -WP_VIOLATION -CARD_IS_LOCKED -COM_CRC_ERROR -CARD_ECC_FAILED -CC_ERROR -ERROR -Response Flags checked in R5: -COM_CRC_ERROR -ERROR -FUNCTION_NUMBER -OUT_OF_RANGE -Values: -0x0 (RESP_R1): R1 (Memory) -0x1 (RESP_R5): R5 (SDIO) - 6 - 1 - read-write - - - MULTI_BLK_SEL - Multi/Single Block Select -This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. -Values: -0x0 (SINGLE): Single Block -0x1 (MULTI): Multiple Block - 5 - 1 - read-write - - - DATA_XFER_DIR - Data Transfer Direction Select -This bit defines the direction of DAT line data transfers. -This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. -Values: -0x1 (READ): Read (Card to Host) -0x0 (WRITE): Write (Host to Card) - 4 - 1 - read-write - - - AUTO_CMD_ENABLE - Auto Command Enable -This field determines use of Auto Command functions. -Note: In SDIO, this field must be set as 00b (Auto Command Disabled). -Values: -0x0 (AUTO_CMD_DISABLED): Auto Command Disabled -0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable -0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable -0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - 2 - 2 - read-write - - - BLOCK_COUNT_ENABLE - Block Count Enable -This bit is used to enable the Block Count register, which is relevant for multiple block transfers. -If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. -The Host Driver must set this bit to 0 when ADMA is used. -Values: -0x1 (ENABLED): Enable -0x0 (DISABLED): Disable - 1 - 1 - read-write - - - DMA_ENABLE - DMA Enable -This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. -You can select one of the DMA modes by using DMA Select in the Host Control 1 register. -Values: -0x1 (ENABLED): DMA Data transfer -0x0 (DISABLED): No data transfer or Non-DMA data transfer - 0 - 1 - read-write - - - - - 4 - 0x4 - RESP01,RESP23,RESP45,RESP67 - RESP[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP01 - Command Response -These bits reflect 39-8 bits of SD/eMMC Response Field. -Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - 0 - 32 - read-only - - - - - BUF_DATA - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUF_DATA - Buffer Data -These bits enable access to the Host Controller packet buffer. - 0 - 32 - read-write - - - - - PSTATE - No description available - 0x24 - 32 - 0x00000000 - 0x19FF0FFF - - - SUB_CMD_STAT - Sub Command Status -This bit is used to distinguish between a main command and a sub command status. -Values: -0x0 (FALSE): Main Command Status -0x1 (TRUE): Sub Command Status - 28 - 1 - read-only - - - CMD_ISSUE_ERR - Command Not Issued by Error -This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. -Values: -0x0 (FALSE): No error for issuing a command -0x1 (TRUE): Command cannot be issued - 27 - 1 - read-only - - - CMD_LINE_LVL - Command-Line Signal Level -This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - 24 - 1 - read-only - - - DAT_3_0 - DAT[3:0] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - 20 - 4 - read-only - - - WR_PROTECT_SW_LVL - Write Protect Switch Pin Level -This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. -Values: -0x0 (FALSE): Write protected -0x1 (TRUE): Write enabled - 19 - 1 - read-only - - - CARD_DETECT_PIN_LEVEL - Card Detect Pin Level -This bit reflects the inverse synchronized value of the card_detect_n signal. -Values: -0x0 (FALSE): No card present -0x1 (TRUE): Card Present - 18 - 1 - read-only - - - CARD_STABLE - Card Stable -This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. -Values: -0x0 (FALSE): Reset or Debouncing -0x1 (TRUE): No Card or Inserted - 17 - 1 - read-only - - - CARD_INSERTED - Card Inserted -This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. -Values: -0x0 (FALSE): Reset, Debouncing, or No card -0x1 (TRUE): Card Inserted - 16 - 1 - read-only - - - BUF_RD_ENABLE - Buffer Read Enable -This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. -Values: -0x0 (DISABLED): Read disable -0x1 (ENABLED): Read enable - 11 - 1 - read-only - - - BUF_WR_ENABLE - Buffer Write Enable -This bit is used for non-DMA transfers. This bit is set if space is available for writing data. -Values: -0x0 (DISABLED): Write disable -0x1 (ENABLED): Write enable - 10 - 1 - read-only - - - RD_XFER_ACTIVE - Read Transfer Active -This bit indicates whether a read transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 9 - 1 - read-only - - - WR_XFER_ACTIVE - Write Transfer Active -This status indicates whether a write transfer is active for SD/eMMC mode. -Values: -0x0 (INACTIVE): No valid data -0x1 (ACTIVE): Transferring data - 8 - 1 - read-only - - - DAT_7_4 - DAT[7:4] Line Signal Level -This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - 4 - 4 - read-only - - - RE_TUNE_REQ - Re-Tuning Request -SDXC does not generate retuning request. The software must maintain the Retuning timer. - 3 - 1 - read-only - - - DAT_LINE_ACTIVE - DAT Line Active ( -This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. -In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. -In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. -For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. -Values: -0x0 (INACTIVE): DAT Line Inactive -0x1 (ACTIVE): DAT Line Active - 2 - 1 - read-only - - - DAT_INHIBIT - Command Inhibit (DAT) -This bit is generated if either DAT line active or Read transfer active is set to 1. -If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. -Values: -0x0 (READY): Can issue command which used DAT line -0x1 (NOT_READY): Cannot issue command which used DAT line - 1 - 1 - read-only - - - CMD_INHIBIT - Command Inhibit (CMD) -This bit indicates the following : -If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. -This bit is set when the command register is written. This bit is cleared when the command response is received. -This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. -Values: -0x0 (READY): Host Controller is ready to issue a command -0x1 (NOT_READY): Host Controller is not ready to issue a command - 0 - 1 - read-only - - - - - PROT_CTRL - No description available - 0x28 - 32 - 0x00000000 - 0x070F0F3E - - - CARD_REMOVAL - Wakeup Event Enable on SD Card Removal -This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. -For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 26 - 1 - read-write - - - CARD_INSERT - Wakeup Event Enable on SD Card Insertion -This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. -FN_WUS (Wake Up Support) in CIS does not affect this bit. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 25 - 1 - read-write - - - CARD_INT - Wakeup Event Enable on Card Interrupt -This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. -This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. -Values: -0x0 (DISABLED): Disable -0x1 (ENABLED): Enable - 24 - 1 - read-write - - - INT_AT_BGAP - Interrupt At Block Gap -This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. -Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. -Values: -0x0 (DISABLE): Disabled -0x1 (ENABLE): Enabled - 19 - 1 - read-write - - - RD_WAIT_CTRL - Read Wait Control -This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. -Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. -Values: -0x0 (DISABLE): Disable Read Wait Control -0x1 (ENABLE): Enable Read Wait Control - 18 - 1 - read-write - - - CONTINUE_REQ - Continue Request -This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. -The Host Controller automatically clears this bit when the transaction restarts. -If stop at block gap request is set to 1, any write to this bit is ignored. -Values: -0x0 (NO_AFFECT): No Affect -0x1 (RESTART): Restart - 17 - 1 - read-write - - - STOP_BG_REQ - Stop At Block Gap Request -This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. -Values: -0x0 (XFER): Transfer -0x1 (STOP): Stop - 16 - 1 - read-write - - - SD_BUS_VOL_VDD1 - SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD -These bits enable the Host Driver to select the voltage level for an SD/eMMC card. -Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. -If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. -The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. -SD Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 3.0V(Typical) -0x5 : 1.8V(Typical) for Embedded -0x4 : 0x0 - Reserved -eMMC Bus Voltage Select options: -0x7 : 3.3V(Typical) -0x6 : 1.8V(Typical) -0x5 : 1.2V(Typical) -0x4 : 0x0 - Reserved -Values: -0x7 (V_3_3): 3.3V (Typ.) -0x6 (V_3_0): 3.0V (Typ.) -0x5 (V_1_8): 1.8V (Typ.) for Embedded -0x4 (RSVD4): Reserved -0x3 (RSVD3): Reserved -0x2 (RSVD2): Reserved -0x1 (RSVD1): Reserved -0x0 (RSVD0): Reserved - 9 - 3 - read-write - - - SD_BUS_PWR_VDD1 - SD Bus Power for VDD1 -This bit enables VDD1 power of the card. -This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. -Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. -In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. -Values: -0x0 (OFF): Power off -0x1 (ON): Power on - 8 - 1 - read-write - - - EXT_DAT_XFER - Extended Data Transfer Width -This bit controls 8-bit bus width mode of embedded device. -Values: -0x1 (EIGHT_BIT): 8-bit Bus Width -0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - 5 - 1 - read-write - - - DMA_SEL - DMA Select -This field is used to select the DMA type. -When Host Version 4 Enable is 1 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : ADMA2 is selected -0x3 : ADMA2 or ADMA3 is selected -When Host Version 4 Enable is 0 in Host Control 2 register: -0x0 : SDMA is selected -0x1 : Reserved -0x2 : 32-bit Address ADMA2 is selected -0x3 : 64-bit Address ADMA2 is selected -Values: -0x0 (SDMA): SDMA is selected -0x1 (RSVD_BIT): Reserved -0x2 (ADMA2): ADMA2 is selected -0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - 3 - 2 - read-write - - - HIGH_SPEED_EN - High Speed Enable -this bit is used to determine the selection of preset value for High Speed mode. -Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. -Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. -Values: -0x1 (HIGH_SPEED): High Speed mode -0x0 (NORMAL_SPEED): Normal Speed mode - 2 - 1 - read-write - - - DAT_XFER_WIDTH - Data Transfer Width -For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. -The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. -Values: -0x1 (FOUR_BIT): 4-bit mode -0x0 (ONE_BIT): 1-bit mode - 1 - 1 - read-write - - - - - SYS_CTRL - No description available - 0x2c - 32 - 0x00000000 - 0x070FFFEF - - - SW_RST_DAT - Software Reset For DAT line -This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. -The following registers and bits are cleared by this bit: -Buffer Data Port register --Buffer is cleared and initialized. -Present state register --Buffer Read Enable --Buffer Write Enable --Read Transfer Active --Write Transfer Active --DAT Line Active --Command Inhibit (DAT) -Block Gap Control register --Continue Request --Stop At Block Gap Request -Normal Interrupt status register --Buffer Read Ready --Buffer Write Ready --DMA Interrupt --Block Gap Event --Transfer Complete -In UHS-II mode, this bit shall be set to 0 -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 26 - 1 - read-write - - - SW_RST_CMD - Software Reset For CMD line -This bit resets only a part of the command circuit to be able to issue a command. -It bit is also used to initialize a UHS-II command circuit. -This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. -Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. -The following registers and bits are cleared by this bit: -Present State register : Command Inhibit (CMD) bit -Normal Interrupt Status register : Command Complete bit -Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 25 - 1 - read-write - - - SW_RST_ALL - Software Reset For All -This reset affects the entire Host Controller except for the card detection circuit. -During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. -All registers are reset except the capabilities register. -If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. -Values: -0x0 (FALSE): Work -0x1 (TRUE): Reset - 24 - 1 - read-write - - - TOUT_CNT - Data Timeout Counter Value. -This value determines the interval by which DAT line timeouts are detected. -The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. -When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). -The values for these bits are: -0xF : Reserved -0xE : TMCLK x 2^27 -......... -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 -Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - 16 - 4 - read-write - - - FREQ_SEL - SDCLK/RCLK Frequency Select -These bits are used to select the frequency of the SDCLK signal. -These bits depend on setting of Preset Value Enable in the Host Control 2 register. -If Preset Value Enable = 0, these bits are set by the Host Driver. -If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. -The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. -10-bit Divided Clock Mode: -0x3FF : 1/2046 Divided clock -.......... -N : 1/2N Divided Clock -.......... -0x002 : 1/4 Divided Clock -0x001 : 1/2 Divided Clock -0x000 : Base clock (10MHz - 255 MHz) -Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: -0x3FF : Base clock * M /1024 -.......... -N-1 : Base clock * M /N -.......... -0x002 : Base clock * M /3 -0x001 : Base clock * M /2 -0x000 : Base clock * M - 8 - 8 - read-write - - - UPPER_FREQ_SEL - These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. -The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - 6 - 2 - read-write - - - CLK_GEN_SELECT - Clock Generator Select -This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. -If Preset Value Enable = 0, this bit is set by the Host Driver. -If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. -The value is reflected on the card_clk_gen_sel signal. -Values: -0x0 (FALSE): Divided Clock Mode -0x1 (TRUE): Programmable Clock Mode - 5 - 1 - read-write - - - PLL_ENABLE - PLL Enable -This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). -When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. -Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): PLL is in low power mode -0x1 (TRUE): PLL is enabled - 3 - 1 - read-write - - - SD_CLK_EN - SD/eMMC Clock Enable -This bit stops the SDCLK or RCLK when set to 0. -The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. -The value is reflected on the clk2card_on pin. -Values: -0x0 (FALSE): Disable providing SDCLK/RCLK -0x1 (TRUE): Enable providing SDCLK/RCLK - 2 - 1 - read-write - - - INTERNAL_CLK_STABLE - Internal Clock Stable -This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. -This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, -and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. -Values: -0x0 (FALSE): Not Ready -0x1 (TRUE): Ready - 1 - 1 - read-write - - - INTERNAL_CLK_EN - Internal Clock Enable -This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. -The Host Controller must stop its internal clock to enter a very low power state. -However, registers can still be read and written to. The value is reflected on the intclk_en signal. -Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . -Values: -0x0 (FALSE): Stop -0x1 (TRUE): Oscillate - 0 - 1 - read-write - - - - - INT_STAT - No description available - 0x30 - 32 - 0x00000000 - 0x1FFFF1FF - - - BOOT_ACK_ERR - Boot Acknowledgment Error -This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. -In SD/UHS-II mode, this bit is irrelevant. - 28 - 1 - read-write - - - RESP_ERR - Response Error -Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. -If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 27 - 1 - read-write - - - TUNING_ERR - Tuning Error -This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure -(occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). -By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. -To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. -The Tuning Error is higher priority than the other error interrupts generated during data transfer. -By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. -This is applicable in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 26 - 1 - read-write - - - ADMA_ERR - ADMA Error -This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: -Error response received from System bus (Master I/F) -ADMA3,ADMA2 Descriptors invalid -CQE Task or Transfer descriptors invalid -When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. -In eMMC CQE mode: -The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. -ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. -The Host Driver may find that Valid bit is not set at the error descriptor. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 25 - 1 - read-write - - - AUTO_CMD_ERR - Auto CMD Error -This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. -This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. -D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 24 - 1 - read-write - - - CUR_LMT_ERR - Current Limit Error -By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. -If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. -A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. -A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. -The Host Controller may require some sampling time to detect the current limit. -SDXC Host Controller does not support this function, this bit is always set to 0. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Power Fail - 23 - 1 - read-write - - - DATA_END_BIT_ERR - Data End Bit Error -This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 22 - 1 - read-write - - - DATA_CRC_ERR - Data CRC Error -This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, -when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 21 - 1 - read-write - - - DATA_TOUT_ERR - Data Timeout Error -This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: -Busy timeout for R1b, R5b type -Busy timeout after Write CRC status -Write CRC Status timeout -Read Data timeout -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 20 - 1 - read-write - - - CMD_IDX_ERR - Command Index Error -This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR - Command End Bit Error -This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. -Values: -0x0 (FALSE): No error -0x1 (TRUE): End Bit error generated - 18 - 1 - read-write - - - CMD_CRC_ERR - Command CRC Error -Command CRC Error is generated in SD/eMMC mode for following two cases. -If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. -The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. -If the Host Controller drives the CMD line to 1 level, -but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. -The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. -Values: -0x0 (FALSE): No error -0x1 (TRUE): CRC error generated - 17 - 1 - read-write - - - CMD_TOUT_ERR - Command Timeout Error -In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. -If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. -Values: -0x0 (FALSE): No error -0x1 (TRUE): Time out - 16 - 1 - read-write - - - ERR_INTERRUPT - Error Interrupt -If any of the bits in the Error Interrupt Status register are set, then this bit is set. -Values: -0x0 (FALSE): No Error -0x1 (TRUE): Error - 15 - 1 - read-only - - - CQE_EVENT - Command Queuing Event -This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): Command Queuing Event is detected - 14 - 1 - read-write - - - FX_EVENT - FX Event -This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. -Values: -0x0 (FALSE): No Event -0x1 (TRUE): FX Event is detected - 13 - 1 - read-only - - - RE_TUNE_EVENT - Re-tuning Event -This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - 12 - 1 - read-only - - - CARD_INTERRUPT - Card Interrupt -This bit reflects the synchronized value of: -DAT[1] Interrupt Input for SD Mode -DAT[2] Interrupt Input for UHS-II Mode -Values: -0x0 (FALSE): No Card Interrupt -0x1 (TRUE): Generate Card Interrupt - 8 - 1 - read-only - - - CARD_REMOVAL - Card Removal -This bit is set if the Card Inserted in the Present State register changes from 1 to 0. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Removed - 7 - 1 - read-write - - - CARD_INSERTION - Card Insertion -This bit is set if the Card Inserted in the Present State register changes from 0 to 1. -Values: -0x0 (FALSE): Card state stable or Debouncing -0x1 (TRUE): Card Inserted - 6 - 1 - read-write - - - BUF_RD_READY - Buffer Read Ready -This bit is set if the Buffer Read Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to read buffer -0x1 (TRUE): Ready to read buffer - 5 - 1 - read-write - - - BUF_WR_READY - Buffer Write Ready -This bit is set if the Buffer Write Enable changes from 0 to 1. -Values: -0x0 (FALSE): Not ready to write buffer -0x1 (TRUE): Ready to write buffer - 4 - 1 - read-write - - - DMA_INTERRUPT - DMA Interrupt -This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. -In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. -This interrupt is not generated after a Transfer Complete. -Values: -0x0 (FALSE): No DMA Interrupt -0x1 (TRUE): DMA Interrupt is generated - 3 - 1 - read-write - - - BGAP_EVENT - Block Gap Event -This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. -Values: -0x0 (FALSE): No Block Gap Event -0x1 (TRUE): Transaction stopped at block gap - 2 - 1 - read-write - - - XFER_COMPLETE - Transfer Complete -This bit is set when a read/write transfer and a command with status busy is completed. -Values: -0x0 (FALSE): Not complete -0x1 (TRUE): Command execution is completed - 1 - 1 - read-write - - - CMD_COMPLETE - Command Complete -In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. -This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. -Values: -0x0 (FALSE): No command complete -0x1 (TRUE): Command Complete - 0 - 1 - read-write - - - - - INT_STAT_EN - No description available - 0x34 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_STAT_EN - Boot Acknowledgment Error (eMMC Mode only) -Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_STAT_EN - Response Error Status Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_STAT_EN - Tuning Error Status Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_STAT_EN - ADMA Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_STAT_EN - Auto CMD Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_STAT_EN - Current Limit Error Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_STAT_EN - Data End Bit Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_STAT_EN - Data CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_STAT_EN - Data Timeout Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_STAT_EN - Command Index Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 19 - 1 - read-write - - - CMD_END_BIT_ERR_STAT_EN - Command End Bit Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_STAT_EN - Command CRC Error Status Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_STAT_EN - Command Timeout Error Status Enable (SD/eMMC Mode only). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_STAT_EN - CQE Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_STAT_EN - FX Event Status Enable -This bit is added from Version 4.10. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_STAT_EN - Re-Tuning Event (UHS-I only) Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_STAT_EN - Card Interrupt Status Enable -If this bit is set to 0, the Host Controller clears the interrupt request to the System. -The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. -The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. -By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_STAT_EN - Card Removal Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_STAT_EN - Card Insertion Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_STAT_EN - Buffer Read Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_STAT_EN - Buffer Write Ready Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_STAT_EN - DMA Interrupt Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_STAT_EN - Block Gap Event Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_STAT_EN - Transfer Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_STAT_EN - Command Complete Status Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - INT_SIGNAL_EN - No description available - 0x38 - 32 - 0x00000000 - 0x1FFF71FF - - - BOOT_ACK_ERR_SIGNAL_EN - Boot Acknowledgment Error (eMMC Mode only). -Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 28 - 1 - read-write - - - RESP_ERR_SIGNAL_EN - Response Error Signal Enable (SD Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 27 - 1 - read-write - - - TUNING_ERR_SIGNAL_EN - Tuning Error Signal Enable (UHS-I Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 26 - 1 - read-write - - - ADMA_ERR_SIGNAL_EN - ADMA Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 25 - 1 - read-write - - - AUTO_CMD_ERR_SIGNAL_EN - Auto CMD Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 24 - 1 - read-write - - - CUR_LMT_ERR_SIGNAL_EN - Current Limit Error Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 23 - 1 - read-write - - - DATA_END_BIT_ERR_SIGNAL_EN - Data End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 22 - 1 - read-write - - - DATA_CRC_ERR_SIGNAL_EN - Data CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 21 - 1 - read-write - - - DATA_TOUT_ERR_SIGNAL_EN - Data Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 20 - 1 - read-write - - - CMD_IDX_ERR_SIGNAL_EN - Command Index Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): No error -0x1 (TRUE): Error - 19 - 1 - read-write - - - CMD_END_BIT_ERR_SIGNAL_EN - Command End Bit Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 18 - 1 - read-write - - - CMD_CRC_ERR_SIGNAL_EN - Command CRC Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 17 - 1 - read-write - - - CMD_TOUT_ERR_SIGNAL_EN - Command Timeout Error Signal Enable (SD/eMMC Mode only) -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 16 - 1 - read-write - - - CQE_EVENT_SIGNAL_EN - Command Queuing Engine Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 14 - 1 - read-write - - - FX_EVENT_SIGNAL_EN - FX Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 13 - 1 - read-write - - - RE_TUNE_EVENT_SIGNAL_EN - Re-Tuning Event (UHS-I only) Signal Enable. -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 12 - 1 - read-write - - - CARD_INTERRUPT_SIGNAL_EN - Card Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 8 - 1 - read-write - - - CARD_REMOVAL_SIGNAL_EN - Card Removal Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 7 - 1 - read-write - - - CARD_INSERTION_SIGNAL_EN - Card Insertion Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 6 - 1 - read-write - - - BUF_RD_READY_SIGNAL_EN - Buffer Read Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 5 - 1 - read-write - - - BUF_WR_READY_SIGNAL_EN - Buffer Write Ready Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 4 - 1 - read-write - - - DMA_INTERRUPT_SIGNAL_EN - DMA Interrupt Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 3 - 1 - read-write - - - BGAP_EVENT_SIGNAL_EN - Block Gap Event Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 2 - 1 - read-write - - - XFER_COMPLETE_SIGNAL_EN - Transfer Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 1 - 1 - read-write - - - CMD_COMPLETE_SIGNAL_EN - Command Complete Signal Enable -Values: -0x0 (FALSE): Masked -0x1 (TRUE): Enabled - 0 - 1 - read-write - - - - - AC_HOST_CTRL - No description available - 0x3c - 32 - 0x00000000 - 0xDCCF00BF - - - PRESET_VAL_ENABLE - Preset Value Enable -This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. -When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. -These values are selected from set of Preset Value registers based on selected speed mode. -Values: -0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver -0x1 (TRUE): Automatic Selection by Preset Value are Enabled - 31 - 1 - read-write - - - ASYNC_INT_ENABLE - Asynchronous Interrupt Enable -This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. -Values: -0x0 (FALSE): Disabled -0x1 (TRUE): Enabled - 30 - 1 - read-write - - - HOST_VER4_ENABLE - Host Version 4 Enable -This bit selects either Version 3.00 compatible mode or Version 4 mode. -Functions of following fields are modified for Host Version 4 mode: -SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) -ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register -64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 -Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register -32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register -Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, -UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). -Values: -0x0 (FALSE): Version 3.00 compatible mode -0x1 (TRUE): Version 4 mode - 28 - 1 - read-write - - - CMD23_ENABLE - CMD23 Enable -If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. -Values: -0x0 (FALSE): Auto CMD23 is disabled -0x1 (TRUE): Auto CMD23 is enabled - 27 - 1 - read-write - - - ADMA2_LEN_MODE - ADMA2 Length Mode -This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. -Values: -0x0 (FALSE): 16-bit Data Length Mode -0x1 (TRUE): 26-bit Data Length Mode - 26 - 1 - read-write - - - SAMPLE_CLK_SEL - Sampling Clock Select -This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. -This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). -Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. -The value is reflected on the sample_cclk_sel pin. -Values: -0x0 (FALSE): Fixed clock is used to sample data -0x1 (TRUE): Tuned clock is used to sample data - 23 - 1 - read-write - - - EXEC_TUNING - Execute Tuning -This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. -Values: -0x0 (FALSE): Not Tuned or Tuning completed -0x1 (TRUE): Execute Tuning - 22 - 1 - read-write - - - SIGNALING_EN - 1.8V Signaling Enable -This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. -Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. -Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. -Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). -Values: -0x0 (V_3_3): 3.3V Signalling -0x1 (V_1_8): 1.8V Signalling - 19 - 1 - read-write - - - UHS_MODE_SEL - UHS Mode/eMMC Speed Mode Select -These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. -UHS Mode (SD/UHS-II mode only): -0x0 (SDR12): SDR12/Legacy -0x1 (SDR25): SDR25/High Speed SDR -0x2 (SDR50): SDR50 -0x3 (SDR104): SDR104/HS200 -0x4 (DDR50): DDR50/High Speed DDR -0x5 (RSVD5): Reserved -0x6 (RSVD6): Reserved -0x7 (UHS2): UHS-II/HS400 -eMMC Speed Mode (eMMC mode only): -0x0: Legacy -0x1: High Speed SDR -0x2: Reserved -0x3: HS200 -0x4: High Speed DDR -0x5: Reserved -0x6: Reserved -0x7: HS400 - 16 - 3 - read-write - - - CMD_NOT_ISSUED_AUTO_CMD12 - Command Not Issued By Auto CMD12 Error -If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Issued -0x0 (FALSE): No Error - 7 - 1 - read-only - - - AUTO_CMD_RESP_ERR - Auto CMD Response Error -This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. -This status is ignored if any bit between D00 to D04 is set to 1. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 5 - 1 - read-only - - - AUTO_CMD_IDX_ERR - Auto CMD Index Error -This bit is set if the command index error occurs in response to a command. -Values: -0x1 (TRUE): Error -0x0 (FALSE): No Error - 4 - 1 - read-only - - - AUTO_CMD_EBIT_ERR - Auto CMD End Bit Error -This bit is set when detecting that the end bit of command response is 0. -Values: -0x1 (TRUE): End Bit Error Generated -0x0 (FALSE): No Error - 3 - 1 - read-only - - - AUTO_CMD_CRC_ERR - Auto CMD CRC Error -This bit is set when detecting a CRC error in the command response. -Values: -0x1 (TRUE): CRC Error Generated -0x0 (FALSE): No Error - 2 - 1 - read-only - - - AUTO_CMD_TOUT_ERR - Auto CMD Timeout Error -This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. -If this bit is set to 1, error status bits (D04-D01) are meaningless. -Values: -0x1 (TRUE): Time out -0x0 (FALSE): No Error - 1 - 1 - read-only - - - AUTO_CMD12_NOT_EXEC - Auto CMD12 Not Executed -If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. -Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - If this bit is set to 1, error status bits (D04-D01) is meaningless. -This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. -Values: -0x1 (TRUE): Not Executed -0x0 (FALSE): Executed - 0 - 1 - read-only - - - - - CAPABILITIES1 - No description available - 0x40 - 32 - 0x00000000 - 0xE7EFFFBF - - - SLOT_TYPE_R - Slot Type -These bits indicate usage of a slot by a specific Host System. -Values: -0x0 (REMOVABLE_SLOT): Removable Card Slot -0x1 (EMBEDDED_SLOT): Embedded Slot for one Device -0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) -0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - 30 - 2 - read-only - - - ASYNC_INT_SUPPORT - Asynchronous Interrupt Support (SD Mode only) -Values: -0x0 (FALSE): Asynchronous Interrupt Not Supported -0x1 (TRUE): Asynchronous Interrupt Supported - 29 - 1 - read-only - - - VOLT_18 - Voltage Support for 1.8V -Values: -0x0 (FALSE): 1.8V Not Supported -0x1 (TRUE): 1.8V Supported - 26 - 1 - read-only - - - VOLT_30 - Voltage Support for SD 3.0V or Embedded 1.2V -Values: -0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported -0x1 (TRUE): SD 3.0V or Embedded Supported - 25 - 1 - read-only - - - VOLT_33 - Voltage Support for 3.3V -Values: -0x0 (FALSE): 3.3V Not Supported -0x1 (TRUE): 3.3V Supported - 24 - 1 - read-only - - - SUS_RES_SUPPORT - Suspense/Resume Support -This bit indicates whether the Host Controller supports Suspend/Resume functionality. -If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. -Values: -0x0 (FALSE): Not Supported -0x1 (TRUE): Supported - 23 - 1 - read-only - - - SDMA_SUPPORT - SDMA Support -This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. -Values: -0x0 (FALSE): SDMA not Supported -0x1 (TRUE): SDMA Supported - 22 - 1 - read-only - - - HIGH_SPEED_SUPPORT - High Speed Support -This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. -Values: -0x0 (FALSE): High Speed not Supported -0x1 (TRUE): High Speed Supported - 21 - 1 - read-only - - - ADMA2_SUPPORT - ADMA2 Support -This bit indicates whether the Host Controller is capable of using ADMA2. -Values: -0x0 (FALSE): ADMA2 not Supported -0x1 (TRUE): ADMA2 Supported - 19 - 1 - read-only - - - EMBEDDED_8_BIT - 8-bit Support for Embedded Device -This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. -Values: -0x0 (FALSE): 8-bit Bus Width not Supported -0x1 (TRUE): 8-bit Bus Width Supported - 18 - 1 - read-only - - - MAX_BLK_LEN - Maximum Block Length -This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. -The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit -Values: -0x0 (ZERO): 512 Byte -0x1 (ONE): 1024 Byte -0x2 (TWO): 2048 Byte -0x3 (THREE): Reserved - 16 - 2 - read-only - - - BASE_CLK_FREQ - Base Clock Frequency for SD clock -These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. -6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. -The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............. --0x3F : 63 MHz --0x40-0xFF : Not Supported -8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. --0x00 : Get information through another method --0x01 : 1 MHz --0x02 : 2 MHz --............ --0xFF : 255 MHz -If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. -If these bits are all 0, the Host system has to get information using a different method. - 8 - 8 - read-only - - - TOUT_CLK_UNIT - Timeout Clock Unit -This bit shows the unit of base clock frequency used to detect Data TImeout Error. -Values: -0x0 (KHZ): KHz -0x1 (MHZ): MHz - 7 - 1 - read-only - - - TOUT_CLK_FREQ - Timeout Clock Frequency -This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. -0x00 : Get information through another method -0x01 : 1KHz / 1MHz -0x02 : 2KHz / 2MHz -0x03 : 3KHz / 3MHz - ........... -0x3F : 63KHz / 63MHz - 0 - 6 - read-only - - - - - CAPABILITIES2 - No description available - 0x44 - 32 - 0x00000000 - 0x18FFEF7F - - - VDD2_18V_SUPPORT - 1.8V VDD2 Support -This bit indicates support of VDD2 for the Host System. -0x0 (FALSE): 1.8V VDD2 is not Supported -0x1 (TRUE): 1.8V VDD2 is Supported - 28 - 1 - read-only - - - ADMA3_SUPPORT - ADMA3 Support -This bit indicates whether the Host Controller is capable of using ADMA3. -Values: -0x0 (FALSE): ADMA3 not Supported -0x1 (TRUE): ADMA3 Supported - 27 - 1 - read-only - - - CLK_MUL - Clock Multiplier -These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. -0x0: Clock Multiplier is not Supported -0x1: Clock Multiplier M = 2 -0x2: Clock Multiplier M = 3 - ......... -0xFF: Clock Multiplier M = 256 - 16 - 8 - read-only - - - RE_TUNING_MODES - Re-Tuning Modes (UHS-I only) -These bits select the re-tuning method and limit the maximum data length. -Values: -0x0 (MODE1): Timer -0x1 (MODE2): Timer and Re-Tuning Request (Not supported) -0x2 (MODE3): Auto Re-Tuning (for transfer) -0x3 (RSVD_MODE): Reserved - 14 - 2 - read-only - - - USE_TUNING_SDR50 - Use Tuning for SDR50 (UHS-I only) -Values: -0x0 (ZERO): SDR50 does not require tuning -0x1 (ONE): SDR50 requires tuning - 13 - 1 - read-only - - - RETUNE_CNT - Timer Count for Re-Tuning (UHS-I only) -0x0: Re-Tuning Timer disabled -0x1: 1 seconds -0x2: 2 seconds -0x3: 4 seconds - ........ -0xB: 1024 seconds -0xC: Reserved -0xD: Reserved -0xE: Reserved -0xF: Get information from other source - 8 - 4 - read-only - - - DRV_TYPED - Driver Type D Support (UHS-I only) -This bit indicates support of Driver Type D for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type D is not supported -0x1 (TRUE): Driver Type D is supported - 6 - 1 - read-only - - - DRV_TYPEC - Driver Type C Support (UHS-I only) -This bit indicates support of Driver Type C for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type C is not supported -0x1 (TRUE): Driver Type C is supported - 5 - 1 - read-only - - - DRV_TYPEA - Driver Type A Support (UHS-I only) -This bit indicates support of Driver Type A for 1.8 Signaling. -Values: -0x0 (FALSE): Driver Type A is not supported -0x1 (TRUE): Driver Type A is supported - 4 - 1 - read-only - - - UHS2_SUPPORT - UHS-II Support (UHS-II only) -This bit indicates whether Host Controller supports UHS-II. -Values: -0x0 (FALSE): UHS-II is not supported -0x1 (TRUE): UHS-II is supported - 3 - 1 - read-only - - - DDR50_SUPPORT - DDR50 Support (UHS-I only) -Values: -0x0 (FALSE): DDR50 is not supported -0x1 (TRUE): DDR50 is supported - 2 - 1 - read-only - - - SDR104_SUPPORT - SDR104 Support (UHS-I only) -This bit mentions that SDR104 requires tuning. -Values: -0x0 (FALSE): SDR104 is not supported -0x1 (TRUE): SDR104 is supported - 1 - 1 - read-only - - - SDR50_SUPPORT - SDR50 Support (UHS-I only) -This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. -Values: -0x0 (FALSE): SDR50 is not supported -0x1 (TRUE): SDR50 is supported - 0 - 1 - read-only - - - - - CURR_CAPABILITIES1 - No description available - 0x48 - 32 - 0x00000000 - 0x00FFFFFF - - - MAX_CUR_18V - Maximum Current for 1.8V -This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 16 - 8 - read-only - - - MAX_CUR_30V - Maximum Current for 3.0V -This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 8 - 8 - read-only - - - MAX_CUR_33V - Maximum Current for 3.3V -This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - CURR_CAPABILITIES2 - No description available - 0x4c - 32 - 0x00000000 - 0x000000FF - - - MAX_CUR_VDD2_18V - Maximum Current for 1.8V VDD2 -This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. -0: Get information through another method -1: 4mA -2: 8mA -3: 13mA -....... -255: 1020mA - 0 - 8 - read-only - - - - - FORCE_EVENT - No description available - 0x50 - 32 - 0x00000000 - 0x1FFF00BF - - - FORCE_BOOT_ACK_ERR - Force Event for Boot Ack error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Boot ack Error Status is set - 28 - 1 - write-only - - - FORCE_RESP_ERR - Force Event for Response Error (SD Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Response Error Status is set - 27 - 1 - write-only - - - FORCE_TUNING_ERR - Force Event for Tuning Error (UHS-I Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Tuning Error Status is set - 26 - 1 - write-only - - - FORCE_ADMA_ERR - Force Event for ADMA Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): ADMA Error Status is set - 25 - 1 - write-only - - - FORCE_AUTO_CMD_ERR - Force Event for Auto CMD Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Auto CMD Error Status is set - 24 - 1 - write-only - - - FORCE_CUR_LMT_ERR - Force Event for Current Limit Error -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Current Limit Error Status is set - 23 - 1 - write-only - - - FORCE_DATA_END_BIT_ERR - Force Event for Data End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data End Bit Error Status is set - 22 - 1 - write-only - - - FORCE_DATA_CRC_ERR - Force Event for Data CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data CRC Error Status is set - 21 - 1 - write-only - - - FORCE_DATA_TOUT_ERR - Force Event for Data Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Data Timeout Error Status is set - 20 - 1 - write-only - - - FORCE_CMD_IDX_ERR - Force Event for Command Index Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Index Error Status is set - 19 - 1 - write-only - - - FORCE_CMD_END_BIT_ERR - Force Event for Command End Bit Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command End Bit Error Status is set - 18 - 1 - write-only - - - FORCE_CMD_CRC_ERR - Force Event for Command CRC Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command CRC Error Status is set - 17 - 1 - write-only - - - FORCE_CMD_TOUT_ERR - Force Event for Command Timeout Error (SD/eMMC Mode only) -Values: -0x0 (FALSE): Not Affected -0x1 (TRUE): Command Timeout Error Status is set - 16 - 1 - write-only - - - FORCE_CMD_NOT_ISSUED_AUTO_CMD12 - Force Event for Command Not Issued By Auto CMD12 Error -Values: -0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set -0x0 (FALSE): Not Affected - 7 - 1 - write-only - - - FORCE_AUTO_CMD_RESP_ERR - Force Event for Auto CMD Response Error -Values: -0x1 (TRUE): Auto CMD Response Error Status is set -0x0 (FALSE): Not Affected - 5 - 1 - write-only - - - FORCE_AUTO_CMD_IDX_ERR - Force Event for Auto CMD Index Error -Values: -0x1 (TRUE): Auto CMD Index Error Status is set -0x0 (FALSE): Not Affected - 4 - 1 - write-only - - - FORCE_AUTO_CMD_EBIT_ERR - Force Event for Auto CMD End Bit Error -Values: -0x1 (TRUE): Auto CMD End Bit Error Status is set -0x0 (FALSE): Not Affected - 3 - 1 - write-only - - - FORCE_AUTO_CMD_CRC_ERR - Force Event for Auto CMD CRC Error -Values: -0x1 (TRUE): Auto CMD CRC Error Status is set -0x0 (FALSE): Not Affected - 2 - 1 - write-only - - - FORCE_AUTO_CMD_TOUT_ERR - Force Event for Auto CMD Timeout Error -Values: -0x1 (TRUE): Auto CMD Timeout Error Status is set -0x0 (FALSE): Not Affected - 1 - 1 - write-only - - - FORCE_AUTO_CMD12_NOT_EXEC - Force Event for Auto CMD12 Not Executed -Values: -0x1 (TRUE): Auto CMD12 Not Executed Status is set -0x0 (FALSE): Not Affected - 0 - 1 - write-only - - - - - ADMA_ERR_STAT - No description available - 0x54 - 32 - 0x00000000 - 0x00000007 - - - ADMA_LEN_ERR - ADMA Length Mismatch Error States -This error occurs in the following instances: -While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length -When the total data length cannot be divided by the block length -Values: -0x0 (NO_ERR): No Error -0x1 (ERROR): Error - 2 - 1 - read-only - - - ADMA_ERR_STATES - ADMA Error States -These bits indicate the state of ADMA when an error occurs during ADMA data transfer. -Values: -0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor -0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor -0x2 (UNUSED): Never set this state -0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - 0 - 2 - read-only - - - - - ADMA_SYS_ADDR - No description available - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_SA - ADMA System Address -These bits indicate the lower 32 bits of the ADMA system address. -SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location -ADMA2: This register stores the byte address of the executing command of the descriptor table -ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - 0 - 32 - read-write - - - - - 9 - 0x2 - INIT,DS,HS,SDR12,SDR25,SDR50,SDR104,DDR50,rsv8,rsv9,UHS2 - PRESET[%s] - no description available - 0x60 - 16 - 0x0000 - 0x07FF - - - CLK_GEN_SEL_VAL - Clock Generator Select Value -This bit is effective when the Host Controller supports a programmable clock generator. -Values: -0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator -0x1 (PROG): Programmable Clock Generator - 10 - 1 - read-only - - - FREQ_SEL_VAL - SDCLK/RCLK Frequency Select Value -10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - 0 - 10 - read-only - - - - - ADMA_ID_ADDR - No description available - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADMA_ID_ADDR - ADMA Integrated Descriptor Address -These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. -The start address of Integrated Descriptor is set to these register bits. -The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - 0 - 32 - read-write - - - - - P_EMBEDDED_CNTRL - No description available - 0xe6 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Offset Address of Embedded Control register. - 0 - 12 - read-only - - - - - P_VENDOR_SPECIFIC_AREA - No description available - 0xe8 - 16 - 0x0000 - 0x0FFF - - - REG_OFFSET_ADDR - Base offset Address for Vendor-Specific registers. - 0 - 12 - read-only - - - - - P_VENDOR2_SPECIFIC_AREA - No description available - 0xea - 16 - 0x0000 - 0xFFFF - - - REG_OFFSET_ADDR - Base offset Address for Command Queuing registers. - 0 - 16 - read-only - - - - - SLOT_INTR_STATUS - No description available - 0xfc - 16 - 0x0000 - 0x00FF - - - INTR_SLOT - Interrupt signal for each Slot -These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. -A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. -Bit 00: Slot 1 -Bit 01: Slot 2 -Bit 02: Slot 3 -.......... -.......... -Bit 07: Slot 8 -Note: MSHC Host Controller support single card slot. This register shall always return 0. - 0 - 8 - read-only - - - - - CQVER - No description available - 0x180 - 32 - 0x00000000 - 0x00000FFF - - - EMMC_VER_MAHOR - This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - 8 - 4 - read-only - - - EMMC_VER_MINOR - This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - 4 - 4 - read-only - - - EMMC_VER_SUFFIX - This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - 0 - 4 - read-only - - - - - CQCAP - No description available - 0x184 - 32 - 0x00000000 - 0x1000F3FF - - - CRYPTO_SUPPORT - Crypto Support -This bit indicates whether the Host Controller supports cryptographic operations. -Values: -0x0 (FALSE): Crypto not Supported -0x1 (TRUE): Crypto Supported - 28 - 1 - read-only - - - ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL) -This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS -polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. -Values: -0x0 (CLK_1KHz): 1KHz clock -0x1 (CLK_10KHz): 10KHz clock -0x2 (CLK_100KHz): 100KHz clock -0x3 (CLK_1MHz): 1MHz clock -0x4 (CLK_10MHz): 10MHz clock - 12 - 4 - read-only - - - ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) -This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - 0 - 10 - read-only - - - - - CQCFG - No description available - 0x188 - 32 - 0x00000000 - 0x00001101 - - - DCMD_EN - This bit indicates to the hardware whether the Task -Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. -Values: -0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor -0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - 12 - 1 - read-write - - - TASK_DESC_SIZE - Bit Value Description -This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). -Values: -0x1 (TASK_DESC_128b): Task descriptor size is 128 bits -0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - 8 - 1 - read-write - - - CQ_EN - No description available - 0 - 1 - read-write - - - - - CQCTL - No description available - 0x18c - 32 - 0x00000000 - 0x00000101 - - - CLR_ALL_TASKS - Clear all tasks -This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. -Values: -0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller -0x0 (NO_EFFECT): Programming 0 has no effect - 8 - 1 - read-write - - - HALT - Halt request and resume -Values: -0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. -For example, issuing a Discard Task command (CMDQ_TASK_MGMT). -When the software writes 1, CQE completes the ongoing task (if any in progress). -After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. -The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. -0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - 0 - 1 - read-write - - - - - CQIS - No description available - 0x190 - 32 - 0x00000000 - 0x0000000F - - - TCL - Task cleared interrupt -This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. -The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). -A value of 1 clears this status bit. -Values: -0x1 (SET): TCL Interrupt is set -0x0 (NOTSET): TCL Interrupt is not set - 3 - 1 - read-write - - - RED - Response error detected interrupt -This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status -field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. -A value of 1 clears this status bit. -Values: -0x1 (SET): RED Interrupt is set -0x0 (NOTSET): RED Interrupt is not set - 2 - 1 - read-write - - - TCC - Task complete interrupt -This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: -A task is completed and the INT bit is set in its Task Descriptor -Interrupt caused by Interrupt Coalescing logic due to timeout -Interrupt Coalescing logic reached the configured threshold -A value of 1 clears this status bit - 1 - 1 - read-write - - - HAC - Halt complete interrupt -This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. -A value of 1 clears this status bit. -Values: -0x1 (SET): HAC Interrupt is set -0x0 (NOTSET): HAC Interrupt is not set - 0 - 1 - read-write - - - - - CQISE - No description available - 0x194 - 32 - 0x00000000 - 0x0000000F - - - TCL_STE - Task cleared interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - 3 - 1 - read-write - - - RED_STE - Response error detected interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.RED is disabled - 2 - 1 - read-write - - - TCC_STE - Task complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - 1 - 1 - read-write - - - HAC_STE - Halt complete interrupt status enable -Values: -0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active -0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - 0 - 1 - read-write - - - - - CQISGE - No description available - 0x198 - 32 - 0x00000000 - 0x0000000F - - - TCL_SGE - Task cleared interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - 3 - 1 - read-write - - - RED_SGE - Response error detected interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - 2 - 1 - read-write - - - TCC_SGE - Task complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - 1 - 1 - read-write - - - HAC_SGE - Halt complete interrupt signal enable -Values: -0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active -0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - 0 - 1 - read-write - - - - - CQIC - No description available - 0x19c - 32 - 0x00000000 - 0x80119FFF - - - INTC_EN - Interrupt Coalescing Enable Bit -Values: -0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated -0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - 31 - 1 - read-write - - - INTC_STAT - Interrupt Coalescing Status Bit -This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt -coalescing (that is, this is set if and only if INTC counter > 0). -Values: -0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) -0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - 20 - 1 - read-only - - - INTC_RST - Counter and Timer Reset -When host driver writes 1, the interrupt coalescing timer and counter are reset. -Values: -0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset -0x0 (NO_EFFECT): No Effect - 16 - 1 - write-only - - - INTC_TH_WEN - Interrupt Coalescing Counter Threshold Write Enable -When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets INTC_TH_WEN -0x0 (WEN_CLR): Clears INTC_TH_WEN - 15 - 1 - write-only - - - INTC_TH - Interrupt Coalescing Counter Threshold filed -Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. -Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. -The counter is reset by software during the interrupt service routine. -The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. -0x0: Interrupt coalescing feature disabled -0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes -0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes -........ -0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes -To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - 8 - 5 - write-only - - - TOUT_VAL_WEN - When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. -Values: -0x1 (WEN_SET): Sets TOUT_VAL_WEN -0x0 (WEN_CLR): clears TOUT_VAL_WEN - 7 - 1 - write-only - - - TOUT_VAL - Interrupt Coalescing Timeout Value -Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. -Timer Operation: The timer is reset by software during the interrupt service routine. -It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. -When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. -The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -0x0: Timer is disabled. Timeout-based interrupt is not generated -0x1: Timeout on 01x1024 cycles of timer clock frequency -0x2: Timeout on 02x1024 cycles of timer clock frequency -........ -0x7f: Timeout on 127x1024 cycles of timer clock frequency -In order to write to this field, the TOUT_VAL_WEN bit must -be set at the same write operation. - 0 - 7 - read-write - - - - - CQTDLBA - No description available - 0x1a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDLBA - This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. -The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. -This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - 0 - 32 - read-write - - - - - CQTDBR - No description available - 0x1a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DBR - The software configures TDLBA and TDLBAU, and enable -CQE in CQCFG before using this register. -Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. -Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. -CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. -CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to -the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. -The corresponding bit is cleared to 0 by CQE in one of the following events: -A task execution is completed (with success or error). -The task is cleared using CQTCLR register. -All tasks are cleared using CQCTL register. -CQE is disabled using CQCFG register. -Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. -In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. -If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - 0 - 32 - read-write - - - - - CQTCN - No description available - 0x1ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TCN - Task Completion Notification -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has completed execution (with success or errors) -Bit-N(0): Task-N has not completed, could be pending or not submitted. -On task completion, software may read this register to know tasks that have completed. After reading this register, -software may clear the relevant bit fields by writing 1 to the corresponding bits. - 0 - 32 - read-write - - - - - CQDQS - No description available - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQS - Device Queue Status -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Device has marked task N as ready for execution -Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. -Host controller updates this register with response of the Device Queue Status command. - 0 - 32 - read-write - - - - - CQDPT - No description available - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DPT - Device-Pending Tasks -Each of the 32 bits are bit mapped to the 32 tasks. -Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution -Bit-N(0): Task-N is not yet queued. -Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. -The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. -Software reads this register in the task-discard procedure to determine if the task is queued in the device - 0 - 32 - read-write - - - - - CQTCLR - No description available - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCLR - Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. -This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. -When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. -CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. -Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - 0 - 32 - read-write - - - - - CQSSC1 - No description available - 0x1c0 - 32 - 0x00000000 - 0x000FFFFF - - - SQSCMD_BLK_CNT - This field indicates when SQS CMD is sent while data transfer is in progress. -A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. -0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. -0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. -0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. -0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. -........ -0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. -Should be programmed only when CQCFG.CQ_EN is 0 - 16 - 4 - read-write - - - SQSCMD_IDLE_TMR - This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. -Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. -When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. -Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. -The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). -For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). -If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. -Should be programmed only when CQCFG.CQ_EN is '0' - 0 - 16 - read-write - - - - - CQSSC2 - No description available - 0x1c4 - 32 - 0x00000000 - 0x0000FFFF - - - SQSCMD_RCA - This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. -CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - 0 - 16 - read-write - - - - - CQCRDCT - No description available - 0x1c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DCMD_RESP - This register contains the response of the command generated by the last direct command (DCMD) task that was sent. -Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - 0 - 32 - read-only - - - - - CQRMEM - No description available - 0x1d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RESP_ERR_MASK - The bits of this field are bit mapped to the device response. -This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. -1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. -0: When a R1/R1b response is received, bit i in the device status is ignored. -The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. -Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - 0 - 32 - read-write - - - - - CQTERRI - No description available - 0x1d4 - 32 - 0x00000000 - 0x1F3F9F3F - - - TRANS_ERR_TASKID - This field captures the ID of the task that was executed and whose data transfer has errors. - 24 - 5 - read-only - - - TRANS_ERR_CMD_INDX - This field captures the index of the command that was executed and whose data transfer has errors. - 16 - 6 - read-only - - - RESP_ERR_FIELDS_VALID - This bit is updated when an error is detected while a command transaction was in progress. -Values: -0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields -0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - 15 - 1 - read-only - - - RESP_ERR_TASKID - This field captures the ID of the task which was executed on the command line when the error occurred. - 8 - 5 - read-only - - - RESP_ERR_CMD_INDX - This field captures the index of the command that was executed on the command line when the error occurred - 0 - 6 - read-only - - - - - CQCRI - No description available - 0x1d8 - 32 - 0x00000000 - 0x0000003F - - - CMD_RESP_INDX - Last Command Response index -This field stores the index of the last received command response. Controller updates the value every time a command response is received - 0 - 6 - read-only - - - - - CQCRA - No description available - 0x1dc - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_RESP_ARG - Last Command Response argument -This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - 0 - 32 - read-only - - - - - MSHC_VER_ID - No description available - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_ID - No description available - 0 - 32 - read-only - - - - - MSHC_VER_TYPE - No description available - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_TYPE - No description available - 0 - 32 - read-only - - - - - EMMC_BOOT_CTRL - No description available - 0x52c - 32 - 0x00000000 - 0xF181070F - - - BOOT_TOUT_CNT - Boot Ack Timeout Counter Value. -This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. -0xF : Reserved -0xE : TMCLK x 2^27 - ............ -0x1 : TMCLK x 2^14 -0x0 : TMCLK x 2^13 - 28 - 4 - read-write - - - BOOT_ACK_ENABLE - Boot Acknowledge Enable -When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. -Values: -0x1 (TRUE): Boot Ack enable -0x0 (FALSE): Boot Ack disable - 24 - 1 - read-write - - - VALIDATE_BOOT - Validate Mandatory Boot Enable bit -This bit is used to validate the MAN_BOOT_EN bit. -Values: -0x1 (TRUE): Validate Mandatory boot enable bit -0x0 (FALSE): Ignore Mandatory boot Enable bit - 23 - 1 - write-only - - - MAN_BOOT_EN - Mandatory Boot Enable -This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. -Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. -Values: -0x1 (MAN_BOOT_EN): Mandatory boot enable -0x0 (MAN_BOOT_DIS): Mandatory boot disable - 16 - 1 - read-write - - - CQE_PREFETCH_DISABLE - Enable or Disable CQE's PREFETCH feature -This field allows Software to disable CQE's data prefetch feature when set to 1. -Values: -0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers -0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - 10 - 1 - read-write - - - CQE_ALGO_SEL - Scheduler algorithm selected for execution -This bit selects the Algorithm used for selecting one of the many ready tasks for execution. -Values: -0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks -0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - 9 - 1 - read-write - - - ENH_STROBE_ENABLE - Enhanced Strobe Enable -This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. -Values: -0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode -0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - 8 - 1 - read-write - - - EMMC_RST_N_OE - Output Enable control for EMMC Device Reset signal PAD -control. -This field drived sd_rst_n_oe output of SDXC -Values: -0x1 (ENABLE): sd_rst_n_oe is 1 -0x0 (DISABLE): sd_rst_n_oe is 0 - 3 - 1 - read-write - - - EMMC_RST_N - EMMC Device Reset signal control. -This register field controls the sd_rst_n output of SDXC -Values: -0x1 (RST_DEASSERT): Reset to eMMC device is deasserted -0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - 2 - 1 - read-write - - - DISABLE_DATA_CRC_CHK - Disable Data CRC Check -This bit controls masking of CRC16 error for Card Write in eMMC mode. -This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, -which may generate CRC error. This CRC error can be masked using this bit during bus testing. -Values: -0x1 (DISABLE): DATA CRC check is disabled -0x0 (ENABLE): DATA CRC check is enabled - 1 - 1 - read-write - - - CARD_IS_EMMC - eMMC Card present -This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. -Values: -0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card -0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - 0 - 1 - read-write - - - - - AUTO_TUNING_CTRL - No description available - 0x540 - 32 - 0x00000000 - 0x7F1F0F1F - - - SWIN_TH_VAL - Sampling window threshold value setting -The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps -can use values from 0x0 to 0x1F. -This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' -0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. -0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. -0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. -........ -0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - 24 - 7 - read-write - - - POST_CHANGE_DLY - Time taken for phase switching and stable clock output. -Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 19 - 2 - read-write - - - PRE_CHANGE_DLY - Maximum Latency specification between cclk_tx and cclk_rx. -Values: -0x0 (LATENCY_LT_1): Less than 1-cycle latency -0x1 (LATENCY_LT_2): Less than 2-cycle latency -0x2 (LATENCY_LT_3): Less than 3-cycle latency -0x3 (LATENCY_LT_4): Less than 4-cycle latency - 17 - 2 - read-write - - - TUNE_CLK_STOP_EN - Clock stopping control for Tuning and auto-tuning circuit. -When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. -This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. -Values: -0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change -0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - 16 - 1 - read-write - - - WIN_EDGE_SEL - This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. -0x0: User selection disabled. Tuning calculated edges are used. -0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. -0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess -... -0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - 8 - 4 - read-write - - - SW_TUNE_EN - This fields enables software-managed tuning flow. -Values: -0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. -0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - 4 - 1 - read-write - - - RPT_TUNE_ERR - Framing errors are not generated when executing tuning. -This debug bit allows users to report these errors. -Values: -0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors -0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - 3 - 1 - read-write - - - SWIN_TH_EN - Sampling window Threshold enable -Selects the tuning mode -Field should be programmed only when SAMPLE_CLK_SEL is '0' -Values: -0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold -set by SWIN_TH_VAL field -0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - 2 - 1 - read-write - - - CI_SEL - Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. -Values: -0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval -0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - 1 - 1 - read-write - - - AT_EN - Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. -Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. -This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. -Values: -0x1 (AT_ENABLE): AutoTuning is enabled -0x0 (AT_DISABLE): AutoTuning is disabled - 0 - 1 - read-write - - - - - AUTO_TUNING_STAT - No description available - 0x544 - 32 - 0x00000000 - 0x00FFFFFF - - - L_EDGE_PH_CODE - Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - 16 - 8 - read-only - - - R_EDGE_PH_CODE - Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - 8 - 8 - read-only - - - CENTER_PH_CODE - Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - 0 - 8 - read-write - - - - - MISC_CTRL0 - No description available - 0x3000 - 32 - 0x00000000 - 0x10020FFF - - - CARDCLK_INV_EN - set to invert card_clk, for slow speed card to meet 5ns setup timing. -May cause glitch on clock, should be set before enable clk(in core cfg) - 28 - 1 - read-write - - - PAD_CLK_SEL_B - set to use internal clock directly, may have timing issue; -clr to use clock loopback from pad. - 17 - 1 - read-write - - - FREQ_SEL_SW_EN - set to use FREQ_SEL_SW as card clock divider; -clear to use core logic as clock divider. - 11 - 1 - read-write - - - TMCLK_EN - set to force enable tmclk; -clear to use core signal intclk_en to control it - 10 - 1 - read-write - - - FREQ_SEL_SW - software card clock divider, it will be used only when FREQ_SEL_SW_EN is set - 0 - 10 - read-write - - - - - MISC_CTRL1 - No description available - 0x3004 - 32 - 0x00000000 - 0xB3F3F000 - - - CARD_ACTIVE - SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). -When counter finished, this bit will be cleared by hardware. -Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) - 31 - 1 - read-write - - - CARD_ACTIVE_PERIOD_SEL - card clock delay config. -00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle - 28 - 2 - read-write - - - CARDCLK_DLYSEL - for card clock DLL, default 0 - 20 - 6 - read-write - - - STROBE_DLYSEL - for strobe DLL, default 7taps(1ns) - 12 - 6 - read-write - - - - - - - SDXC1 - SDXC1 - SDXC - 0xf1134000 - - - DDRCTL - DDRCTL - DDRCTL - 0xf3010000 - - 0x0 - 0xf34 - registers - - - - MSTR - Description: Master Register - 0x0 - 32 - 0x03040001 - 0x0F0FB601 - - - ACTIVE_RANKS - Description: Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. -1 - populated -0 - unpopulated -LSB is the lowest rank number. -For 2 ranks following combinations are legal: -01 - One rank -11 - Two ranks -Others - Reserved. -For 4 ranks following combinations are legal: -0001 - One rank -0011 - Two ranks -1111 - Four ranks -Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF -:((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" -Exists: MEMC_NUM_RANKS>1 - 24 - 4 - read-write - - - BURST_RDWR - Description: SDRAM burst length used: -0001 - Burst length of 2 (only supported for mDDR) -0010 - Burst length of 4 -0100 - Burst length of 8 -1000 - Burst length of 16 (only supported for mDDR and LPDDR2) -All other values are reserved. -This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. -Value After Reset: 0x4 -Exists: Always - 16 - 4 - read-write - - - DLL_OFF_MODE - Description: Set to 1 when uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. -Set to 0 to put uMCTL2 and DRAM in DLL-on mode for normal frequency operation. -Value After Reset: 0x0 -Exists: MEMC_DDR3_OR_4==1 - 15 - 1 - read-write - - - DATA_BUS_WIDTH - Description: Selects proportion of DQ bus width that is used by the SDRAM -00 - Full DQ bus width to SDRAM -01 - Half DQ bus width to SDRAM -10 - Quarter DQ bus width to SDRAM -11 - Reserved. -Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). -Value After Reset: 0x0 -Exists: Always - 12 - 2 - read-write - - - EN_2T_TIMING_MODE - Description: If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command -Note: 2T timing is not supported in LPDDR2/LPDDR3 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set -Note: 2T timing is not supported in DDR4 geardown mode. -Value After Reset: 0x0 -Exists: MEMC_CMD_RTN2IDLE==0 - 10 - 1 - read-write - - - BURSTCHOP - Description: When set, enable burst-chop in DDR3/DDR4. This is only supported in full bus width mode (MSTR.data_bus_width = 00). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' -Value After Reset: 0x0 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 - 9 - 1 - read-write - - - DDR3 - Description: Select DDR3 SDRAM -1 - DDR3 SDRAM device in use -0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. -Value After Reset: "(MEMC_DDR3_EN==1) ? 0x1 : 0x0" -Exists: MEMC_DDR3==1 - 0 - 1 - read-write - - - - - STAT - Description: Operating Mode Status Register - 0x4 - 32 - 0x00000000 - 0x00000037 - - - SELFREF_TYPE - Description: Flags if Self Refresh is entered and if it was under Automatic Self Refresh control only or not. -00 - SDRAM is not in Self Refresh -11 - SDRAM is in Self Refresh and Self Refresh was caused by Automatic Self Refresh only -10 - SDRAM is in Self Refresh and Self Refresh was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). -Value After Reset: 0x0 -Exists: Always - 4 - 2 - read-only - - - OPERATING_MODE - Description: Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/DDR4 support and 2-bits in all other configurations. -non-mDDR/LPDDR2/LPDDR3 and non-DDR4 designs: -00 - Init -01 - Normal -10 - Power-down -11 - Self refresh -mDDR/LPDDR2/LPDDR3 or DDR4 designs: -000 - Init -001 - Normal -010 - Power-down -011 - Self refresh -1XX - Deep power-down / Maximum Power Saving Mode -Value After Reset: 0x0 -Exists: Always - 0 - 3 - read-only - - - - - MRCTRL0 - Description: Mode Register Read/Write Control Register 0 - 0x10 - 32 - 0x00000030 - 0x8000F0F0 - - - MR_WR - Description: Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL2 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power- down or MPSM operating modes. -Value After Reset: 0x0 -Exists: Always - 31 - 1 - read-write - - - MR_ADDR - Description: Address of the mode register that is to be written to. -0000 - MR0 -0001 - MR1 -0010 - MR2 -0011 - MR3 -0100 - MR4 -0101 - MR5 -0110 - MR6 -0111 - MR7 -Don't Care for LPDDR2/LPDDR3 (see MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3) -This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM -In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of RDIMMs. -Value After Reset: 0x0 -Exists: Always - 12 - 4 - read-write - - - MR_RANK - Description: Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. -Examples (assume uMCTL2 is configured for 4 ranks): -0x1 - select rank 0 only -0x2 - select rank 1 only -0x5 - select ranks 0 and 2 -0xA - select ranks 1 and 3 -0xF - select ranks 0, 1, 2 and 3 -Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF -:((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" -Exists: Always - 4 - 4 - read-write - - - - - MRCTRL1 - Description: Mode Register Read/Write Control Register 1 - 0x14 - 32 - 0x00000000 - 0x0003FFFF - - - MR_DATA - Description: Mode register write data for all non- LPDDR2/non-LPDDR3 modes. -For LPDDR2/LPDDR3, MRCTRL1[15:0] are interpreted as [15:8] MR Address and [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. -Value After Reset: 0x0 -Exists: Always - 0 - 18 - read-write - - - - - MRSTAT - Description: Mode Register Read/Write Status Register - 0x18 - 32 - 0x00000000 - 0x00000001 - - - MR_WR_BUSY - Description: The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. -0 - Indicates that the SoC core can initiate a mode register write operation -1 - Indicates that mode register write operation is in progress -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-only - - - - - PWRCTL - Description: Low Power Control Register - 0x30 - 32 - 0x00000000 - 0x0000002B - - - SELFREF_SW - Description: A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. -1 - Software Entry to Self Refresh -0 - Software Exit from Self Refresh -Value After Reset: 0x0 -Exists: Always - 5 - 1 - read-write - - - EN_DFI_DRAM_CLK_DISABLE - Description: Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. -If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: -In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: -in Self Refresh. -in Maximum Power Saving Mode -In mDDR/LPDDR2/LPDDR3, can be asserted in following: -in Self Refresh -in Power Down -in Deep Power Down -during Normal operation (Clock Stop) -Value After Reset: 0x0 -Exists: Always - 3 - 1 - read-write - - - POWERDOWN_EN - Description: If true then the uMCTL2 goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). -This register bit may be re-programmed during the course of normal operation. -Value After Reset: 0x0 -Exists: Always - 1 - 1 - read-write - - - SELFREF_EN - Description: If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re- programmed during the course of normal operation. -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - PWRTMG - Description: Low Power Timing Register - 0x34 - 32 - 0x00400010 - 0x00FF001F - - - SELFREF_TO_X32 - Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_en. -Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. -Value After Reset: 0x40 -Exists: Always - 16 - 8 - read-write - - - POWERDOWN_TO_X32 - Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_en. -Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. -Value After Reset: 0x10 -Exists: Always - 0 - 5 - read-write - - - - - HWLPCTL - Description: Hardware Low Power Control Register - 0x38 - 32 - 0x00000003 - 0x0FFF0003 - - - HW_LP_IDLE_X32 - Description: Hardware idle period. The cactive_ddrc output is driven low if the system is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The hardware idle function is disabled when hw_lp_idle_x32=0. -Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. -Value After Reset: 0x0 -Exists: Always - 16 - 12 - read-write - - - HW_LP_EXIT_IDLE_EN - Description: When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). -Value After Reset: 0x1 -Exists: Always - 1 - 1 - read-write - - - HW_LP_EN - Description: Enable for Hardware Low Power Interface. -Value After Reset: 0x1 -Exists: Always - 0 - 1 - read-write - - - - - RFSHCTL0 - Description: Refresh Control Register 0 - 0x50 - 32 - 0x00210000 - 0x00F1F1F0 - - - REFRESH_MARGIN - Description: Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. -Unit: Multiples of 32 clocks. Value After Reset: 0x2 Exists: Always - 20 - 4 - read-write - - - REFRESH_TO_X32 - Description: If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. -FOR PERFORMANCE ONLY. -Value After Reset: 0x10 -Exists: Always - 12 - 5 - read-write - - - REFRESH_BURST - Description: The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. -0 - single refresh -1 - burst-of-2 refresh -7 - burst-of-8 refresh -For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. -For DDR2/3, the refresh is always per-rank and not per- bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granuarity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY- initiated update is complete. -Value After Reset: 0x0 -Exists: Always - 4 - 5 - read-write - - - - - RFSHCTL1 - Description: Refresh Control Register 1 - 0x54 - 32 - 0x00000000 - 0x0FFF0FFF - - - REFRESH_TIMER1_START_VALUE_X32 - Description: Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. -Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. -Value After Reset: 0x0 -Exists: MEMC_NUM_RANKS>1 - 16 - 12 - read-write - - - REFRESH_TIMER0_START_VALUE_X32 - Description: Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. -Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. -Value After Reset: 0x0 -Exists: MEMC_NUM_RANKS>1 - 0 - 12 - read-write - - - - - RFSHCTL3 - Description: Refresh Control Register 0 - 0x60 - 32 - 0x00000000 - 0x00000003 - - - REFRESH_UPDATE_LEVEL - Description: Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. -The value is automatically updated when exiting soft reset, so it does not need to be toggled initially. -Value After Reset: 0x0 -Exists: Always - 1 - 1 - read-write - - - DIS_AUTO_REFRESH - Description: When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. -When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. -If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto- refresh is not supported, and this bit must be set to '0'. -This register field is changeable on the fly. -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - RFSHTMG - Description: Refresh Timing Register - 0x64 - 32 - 0x0062008C - 0x0FFF01FF - - - T_RFC_NOM_X32 - Description: tREFI: Average time interval between refreshes per rank (specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2 and LPDDR3). -For LPDDR2/LPDDR3: -if using all-bank refreshes (RFSHCTL0.per_bank_refresh -= 0), this register should be set to tREFIab -if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb -For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. -In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. -Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min. Unit: Multiples of 32 clocks. -Value After Reset: 0x62 -Exists: Always - 16 - 12 - read-write - - - T_RFC_MIN - Description: tRFC (min): Minimum time from refresh to refresh or activate. -For LPDDR2/LPDDR3: -if using all-bank refreshes (RFSHCTL0.per_bank_refresh -= 0), this register should be set to tRFCab -if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tRFCpb -For configurations with MEMC_FREQ_RATIO=2, program this to tRFC(min)/2 and round up to next integer value. -In DDR4 mode, tRFC(min) value is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. -Unit: Clocks. -Value After Reset: 0x8c -Exists: Always - 0 - 9 - read-write - - - - - ECCUADDR0 - Description: ECC Uncorrected Error Address Register 0 - 0xa4 - 32 - 0x00000000 - 0x0303FFFF - - - ECC_UNCORR_RANK - Description: Rank number of a read resulting in an uncorrected ECC error -Value After Reset: 0x0 -Exists: MEMC_NUM_RANKS>1 - 24 - 2 - read-only - - - ECC_UNCORR_ROW - Description: Page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. -Value After Reset: 0x0 -Exists: Always - 0 - 18 - read-only - - - - - CRCPARCTL0 - Description: CRC Parity Control Register0 - 0xc0 - 32 - 0x00000000 - 0x00000007 - - - DFI_ALERT_ERR_CNT_CLR - Description: DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the uMCTL2 automatically clears this bit. -Value After Reset: 0x0 -Exists: Always - 2 - 1 - read-write - - - DFI_ALERT_ERR_INT_CLR - Description: Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the uMCTL2 automatically clears this bit. -Value After Reset: 0x0 -Exists: Always - 1 - 1 - read-write - - - DFI_ALERT_ERR_INT_EN - Description: Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - CRCPARSTAT - Description: CRC Parity Status Register - 0xcc - 32 - 0x00000000 - 0x0001FFFF - - - DFI_ALERT_ERR_INT - Description: DFI alert error interrupt. -If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr -Value After Reset: 0x0 -Exists: Always - 16 - 1 - read-only - - - DFI_ALERT_ERR_CNT - Description: DFI alert error count. -If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. -Value After Reset: 0x0 -Exists: Always - 0 - 16 - read-only - - - - - INIT0 - Description: SDRAM Initialization Register 0 - 0xd0 - 32 - 0x0002004E - 0xC3FF03FF - - - SKIP_DRAM_INIT - Description: If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed -00 - SDRAM Initialization routine is run after power-up -01 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Normal Mode -11 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Self-refresh Mode -10 - SDRAM Initialization routine is run after power-up. -Value After Reset: 0x0 -Exists: Always - 30 - 2 - read-write - - - POST_CKE_X1024 - Description: Cycles to wait after driving CKE high to start the SDRAM initialization sequence. -Unit: 1024 clocks. -DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. -LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. -For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. -Value After Reset: 0x2 -Exists: Always - 16 - 10 - read-write - - - PRE_CKE_X1024 - Description: Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. -Unit: 1024 clock cycles. -DDR2 specifications typically require this to be programmed for a delay of >= 200 us. -LPDDR2/LPDDR3: tINIT1 of 100 ns (min) -For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. -Value After Reset: 0x4e -Exists: Always - 0 - 10 - read-write - - - - - INIT1 - Description: SDRAM Initialization Register 1 - 0xd4 - 32 - 0x00000000 - 0x00FF7F0F - - - DRAM_RSTN_X1024 - Description: Number of cycles to assert SDRAM reset signal during init sequence. -This is only present for designs supporting DDR3/DDR4 devices. For use with a Synopsys DDR PHY, this should be set to a minimum of 1 -Value After Reset: 0x0 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 - 16 - 8 - read-write - - - FINAL_WAIT_X32 - Description: Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. -Unit: Counts of a global timer that pulses every 32 clock cycles. -There is no known specific requirement for this; it may be set to zero. -Value After Reset: 0x0 -Exists: Always - 8 - 7 - read-write - - - PRE_OCD_X32 - Description: Wait period before driving the OCD complete command to SDRAM. -Unit: Counts of a global timer that pulses every 32 clock cycles. -There is no known specific requirement for this; it may be set to zero. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - INIT3 - Description: SDRAM Initialization Register 3 - 0xdc - 32 - 0x00000510 - 0xFFFFFFFF - - - MR - Description: DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. -DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. -LPDDR2/LPDDR3 - Value to write to MR1 register -Value After Reset: 0x0 -Exists: Always - 16 - 16 - read-write - - - EMR - Description: DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. -DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. -mDDR: Value to write to EMR register. LPDDR2/LPDDR3 - Value to write to MR2 register Value After Reset: 0x510 -Exists: Always - 0 - 16 - read-write - - - - - INIT4 - Description: SDRAM Initialization Register 4 - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EMR2 - Description: DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3: Value to write to MR3 register mDDR: Unused -Value After Reset: 0x0 -Exists: Always - 16 - 16 - read-write - - - EMR3 - Description: DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused -Value After Reset: 0x0 -Exists: Always - 0 - 16 - read-write - - - - - INIT5 - Description: SDRAM Initialization Register 5 - 0xe4 - 32 - 0x00100000 - 0x00FF0000 - - - DEV_ZQINIT_X32 - Description: ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. -Unit: 32 clock cycles. -DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. -LPDDR2/LPDDR3 requires 1 us. -Value After Reset: 0x10 -Exists: MEMC_DDR3==1 || MEMC_DDR4 == 1 || MEMC_LPDDR2==1 - 16 - 8 - read-write - - - - - DIMMCTL - Description: DIMM Control Register - 0xf0 - 32 - 0x00000000 - 0x00000003 - - - DIMM_ADDR_MIRR_EN - Description: Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). -Some UDIMMs and DDR4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), -(BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. -Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. -This is not supported for mDDR, LPDDR2 or LPDDR3 SDRAMs. -Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. -1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) -0 - Do not implement address mirroring -Value After Reset: 0x0 -Exists: Always - 1 - 1 - read-write - - - DIMM_STAGGER_CS_EN - Description: Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for DDR4, mDDR, LPDDR2 or LPDDR3 SDRAMs. -1 - Stagger accesses to even and odd ranks -0 - Do not stagger accesses -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - RANKCTL - Description: Rank Control Register - 0xf4 - 32 - 0x0000066F - 0x00000FFF - - - DIFF_RANK_WR_GAP - Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. -This is used to switch the delays in the PHY to match the rank requirements. -The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. -For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. -Value After Reset: 0x6 -Exists: MEMC_NUM_RANKS>1 - 8 - 4 - read-write - - - DIFF_RANK_RD_GAP - Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. -This is used to switch the delays in the PHY to match the rank requirements. -The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. -For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. -Value After Reset: 0x6 -Exists: MEMC_NUM_RANKS>1 - 4 - 4 - read-write - - - MAX_RANK_RD - Description: Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap -dictated by the register RANKCTL.diff_rank_rd_gap. This is -to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. -This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. -This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. -Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. -Feature limitation: max_rank_rd feature works as described only in the mode in which one command at the DDRC input results in one DFI command at the output. An example of this mode is: BL8 hardware configuration (MEMC_BURST_LENGTH=8) and Full bus width mode (MSTR.data_bus_width=2'b00) and BL8 mode of operation (MSTR.burst_rdwr=4'b0100). In modes where single HIF command results in multiple DFI commands (eg: Half Bus Width, BL4 etc.), the same rank commands would be serviced for as long as they are available, which is equivalent to this feature being disabled. -FOR PERFORMANCE ONLY. -Value After Reset: 0xf -Exists: MEMC_NUM_RANKS>1 - 0 - 4 - read-write - - - - - DRAMTMG0 - Description: SDRAM Timing Register 0 - 0x100 - 32 - 0x0F101B0F - 0x7F3F7F3F - - - WR2PRE - Description: Minimum time between write and precharge to same bank. -Unit: Clocks -Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: -WL = write latency -BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. -tWR = Write recovery time. This comes directly from the SDRAM specification. -Add one extra cycle for LPDDR2/LPDDR3 for this parameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. -For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up. -Value After Reset: 0xf -Exists: Always - 24 - 7 - read-write - - - T_FAW - Description: tFAW Valid only when 8 or more banks(or banks x bank groups) are present. -In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. -For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next integer value. -In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. -Unit: Clocks -Value After Reset: 0x10 -Exists: Always - 16 - 6 - read-write - - - T_RAS_MAX - Description: tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open -Minimum value of this register is 1. Zero is invalid. -For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2. No rounding up. -Unit: Multiples of 1024 clocks. Value After Reset: 0x1b Exists: Always - 8 - 7 - read-write - - - T_RAS_MIN - Description: tRAS(min): Minimum time between activate and precharge to the same bank. -For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRAS(min)/2. No rounding up. -For configurations with MEMC_FREQ_RATIO=2, 2T mode, program this to (tRAS(min)/2 + 1). No rounding up of the division operation. -Unit: Clocks -Value After Reset: 0xf -Exists: Always - 0 - 6 - read-write - - - - - DRAMTMG1 - Description: SDRAM Timing Register 1 - 0x104 - 32 - 0x00080414 - 0x001F1F7F - - - T_XP - Description: tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. -If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it up to the next integer value. -Units: Clocks -Value After Reset: 0x8 -Exists: Always - 16 - 5 - read-write - - - RD2PRE - Description: tRTP: Minimum time from read to precharge of same bank. -DDR2: tAL + BL/2 + max(tRTP, 2) - 2 -DDR3: tAL + max (tRTP, 4) -DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. -mDDR: BL/2 -LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. -LPDDR3: BL/2 + max(tRTP,4) - 4 -For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. -For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up of division operation. -Unit: Clocks. -Value After Reset: 0x4 -Exists: Always - 8 - 5 - read-write - - - T_RC - Description: tRC: Minimum time between activates to same bank. -For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next integer value. -Unit: Clocks. -Value After Reset: 0x14 -Exists: Always - 0 - 7 - read-write - - - - - DRAMTMG2 - Description: SDRAM Timing Register 2 - 0x108 - 32 - 0x0000060D - 0x00001F3F - - - RD2WR - Description: DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL -LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL. -Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. -Unit: Clocks. Where: -WL = write latency -BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM -RL = read latency = CAS latency -WR_PREAMBLE = write preamble. This is unique to DDR4. -For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. -Value After Reset: 0x6 -Exists: Always - 8 - 5 - read-write - - - WR2RD - Description: DDR4: WL + BL/2 + tWTR_L Others: WL + BL/2 + tWTR -In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. -Unit: Clocks. Where: -WL = write latency -BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM -tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. -tWTR = internal write to read command delay. This comes directly from the SDRAM specification. -Add one extra cycle for LPDDR2/LPDDR3 operation. -For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. -Value After Reset: 0xd -Exists: Always - 0 - 6 - read-write - - - - - DRAMTMG3 - Description: SDRAM Timing Register 3 - 0x10c - 32 - 0x0000400C - 0x0003F3FF - - - T_MRD - Description: tMRD: Cycles between load mode commands. If MEMC_DDR3_OR_4 = 0, this parameter is also used to define the cycles between load mode command and following non-load mode command. -For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. -If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead -Value After Reset: 0x4 -Exists: Always - 12 - 6 - read-write - - - T_MOD - Description: tMOD: Present if MEMC_DDR3_OR_4 = 1. Cycles between load mode command and following non-load mode command. This is required to be programmed even when a design that supports DDR3/4 is running in DDR2 mode. -If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead -Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip -Value After Reset: "(MEMC_DDR3_EN==1 || MEMC_DDR4_EN==1 ) ? 0xc : 0x0" -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 - 0 - 10 - read-write - - - - - DRAMTMG4 - Description: SDRAM Timing Register 4 - 0x110 - 32 - 0x05040405 - 0x1F070F1F - - - T_RCD - Description: tRCD - tAL: Minimum time from activate to read or write command to same bank. -For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD - tAL)/2) and round it up to the next integer value. -Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. -Unit: Clocks. -Value After Reset: 0x5 -Exists: Always - 24 - 5 - read-write - - - T_CCD - Description: DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads -or two writes. -For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. -Unit: clocks. -Value After Reset: 0x4 -Exists: Always - 16 - 3 - read-write - - - T_RRD - Description: DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank -"a" to bank "b" -For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. -Unit: Clocks. -Value After Reset: 0x4 -Exists: Always - 8 - 4 - read-write - - - T_RP - Description: tRP: Minimum time from precharge to activate of same bank. -For configurations with MEMC_FREQ_RATIO=2, program this to (tRP/2 + 1). No round up of the fraction. -Unit: Clocks. -Value After Reset: 0x5 -Exists: Always - 0 - 5 - read-write - - - - - DRAMTMG5 - Description: SDRAM Timing Register 5 - 0x114 - 32 - 0x05050403 - 0x0F0F3F1F - - - T_CKSRX - Description: This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. -Recommended settings: -mDDR: 1 -LPDDR2: 2 -LPDDR3: 2 -DDR2: 1 -DDR3: tCKSRX -DDR4: tCKSRX -For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. -Value After Reset: 0x5 -Exists: Always - 24 - 4 - read-write - - - T_CKSRE - Description: This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. -Recommended settings: -mDDR: 0 -LPDDR2: 2 -LPDDR3: 2 -DDR2: 1 -DDR3: max (10 ns, 5 tCK) -DDR4: max (10 ns, 5 tCK) -For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. -Value After Reset: 0x5 -Exists: Always - 16 - 4 - read-write - - - T_CKESR - Description: Minimum CKE low width for Self refresh entry to exit timing im memory clock cycles. -Recommended settings: -mDDR: tRFC -LPDDR2: tCKESR -LPDDR3: tCKESR -DDR2: tCKE -DDR3: tCKE + 1 -DDR4: tCKE + 1 -For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. -Value After Reset: 0x4 -Exists: Always - 8 - 6 - read-write - - - T_CKE - Description: Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR -Non-LPDDR2/non-LPDDR3 designs: Set this to tCKE value. -For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to the next integer value. -Unit: Clocks. -Value After Reset: 0x3 -Exists: Always - 0 - 5 - read-write - - - - - DRAMTMG8 - Description: SDRAM Timing Register 8 - 0x120 - 32 - 0x00004405 - 0x00007F7F - - - T_XS_DLL_X32 - Description: tXSDLL: Exit Self Refresh to commands requiring a locked DLL. -For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. -Unit: Multiples of 32 clocks. -Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. -Value After Reset: 0x44 -Exists: Always - 8 - 7 - read-write - - - T_XS_X32 - Description: tXS: Exit Self Refresh to commands not requiring a locked DLL. -For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. -Unit: Multiples of 32 clocks. -Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. -Value After Reset: 0x5 -Exists: Always - 0 - 7 - read-write - - - - - ZQCTL0 - Description: ZQ Control Register 0 - 0x180 - 32 - 0x02000040 - 0xE3FF03FF - - - DIS_AUTO_ZQ - Description: -1 - Disable uMCTL2 generation of ZQCS command. Register reg_ddrc_zq_calib_short can be used instead to control ZQ calibration commands. -0 - Internally generate ZQCS commands based on ZQCTL1.t_zq_short_interval_x1024. -This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. -Value After Reset: 0x0 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - 31 - 1 - read-write - - - DIS_SRX_ZQCL - Description: -1 - Disable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. -0 - Enable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. -This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. -Value After Reset: 0x0 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - 30 - 1 - read-write - - - ZQ_RESISTOR_SHARED - Description: -1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS timing met between commands so that commands to different ranks do not overlap. -0 - ZQ resistor is not shared. -This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. -Value After Reset: 0x0 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - 29 - 1 - read-write - - - T_ZQ_LONG_NOP - Description: tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM. -For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. -LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. -Unit: Clock cycles. -This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. -Value After Reset: 0x200 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - 16 - 10 - read-write - - - T_ZQ_SHORT_NOP - Description: tZQCS: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM. -For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to the next integer value. Unit: Clock cycles. -This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. -Value After Reset: 0x40 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - 0 - 10 - read-write - - - - - ZQCTL1 - Description: ZQ Control Register 1 - 0x184 - 32 - 0x00000100 - 0x000FFFFF - - - T_ZQ_SHORT_INTERVAL_X1024 - Description: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3/DDR4/LPDDR2/LPDDR3 devices. -Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. -This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. -Value After Reset: 0x100 -Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - 0 - 20 - read-write - - - - - ZQSTAT - Description: ZQ Status Register - 0x18c - 32 - 0x00000000 - 0x00000001 - - - ZQ_RESET_BUSY - Description: SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. -0 - Indicates that the SoC core can initiate a ZQ Reset operation -1 - Indicates that ZQ Reset operation is in progress -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-only - - - - - DFITMG0 - Description: DFI Timing Register 0 - 0x190 - 32 - 0x07020002 - 0x1FBFBF3F - - - DFI_T_CTRL_DELAY - Description: Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, depending on the PHY, it may be necessary to increment this parameter by 1. This is to compensate for the extra cycle of latency through the RDIMM -Value After Reset: 0x7 -Exists: Always - 24 - 5 - read-write - - - DFI_RDDATA_USE_SDR - Description: Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: -0 in terms of HDR clock cycles -1 in terms of SDR clock cycles -Refer to PHY specification for correct value. -Value After Reset: 0x0 -Exists: MEMC_FREQ_RATIO==2 - 23 - 1 - read-write - - - DFI_T_RDDATA_EN - Description: Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. -This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle of latency through the RDIMM. -Unit: Clocks -Value After Reset: 0x2 -Exists: Always - 16 - 6 - read-write - - - DFI_WRDATA_USE_SDR - Description: Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or HDR clock cycles -0 in terms of HDR clock cycles -1 in terms of SDR clock cycles -Refer to PHY specification for correct value. -Value After Reset: 0x0 -Exists: MEMC_FREQ_RATIO==2 - 15 - 1 - read-write - - - DFI_TPHY_WRDATA - Description: Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. -Unit: Clocks -Value After Reset: 0x0 -Exists: Always - 8 - 6 - read-write - - - DFI_TPHY_WRLAT - Description: Write latency -Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. The minimum supported value is as follows: -0 for configurations with MEMC_WL0 = 1 -1 for configurations with MEMC_WL0 = 0 -Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency through the RDIMM. -Value After Reset: 0x2 -Exists: Always - 0 - 6 - read-write - - - - - DFITMG1 - Description: DFI Timing Register 1 - 0x194 - 32 - 0x00000404 - 0x001F0F0F - - - DFI_T_WRDATA_DELAY - Description: Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. -Unit: Clocks -Value After Reset: 0x0 -Exists: Always - 16 - 5 - read-write - - - DFI_T_DRAM_CLK_DISABLE - Description: Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY- DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. -Value After Reset: 0x4 -Exists: Always - 8 - 4 - read-write - - - DFI_T_DRAM_CLK_ENABLE - Description: Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. -Value After Reset: 0x4 -Exists: Always - 0 - 4 - read-write - - - - - DFILPCFG0 - Description: DFI Low Power Configuration Register 0 - 0x198 - 32 - 0x07000000 - 0x0F00F1F1 - - - DFI_TLP_RESP - Description: Setting for DFI's tlp_resp time. -Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed -value of 7 always. -Value After Reset: 0x7 -Exists: Always - 24 - 4 - read-write - - - DFI_LP_WAKEUP_SR - Description: Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. -Determines the DFI's tlp_wakeup time: -0x0 - 16 cycles -0x1 - 32 cycles -0x2 - 64 cycles -0x3 - 128 cycles -0x4 - 256 cycles -0x5 - 512 cycles -0x6 - 1024 cycles -0x7 - 2048 cycles -0x8 - 4096 cycles -0x9 - 8192 cycles -0xA - 16384 cycles -0xB - 32768 cycles -0xC - 65536 cycles -0xD - 131072 cycles -0xE - 262144 cycles -0xF - Unlimited Value After Reset: 0x0 Exists: Always - 12 - 4 - read-write - - - DFI_LP_EN_SR - Description: Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. -0 - Disabled -1 - Enabled -Value After Reset: 0x0 -Exists: Always - 8 - 1 - read-write - - - DFI_LP_WAKEUP_PD - Description: Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. -Determines the DFI's tlp_wakeup time: -0x0 - 16 cycles -0x1 - 32 cycles -0x2 - 64 cycles -0x3 - 128 cycles -0x4 - 256 cycles -0x5 - 512 cycles -0x6 - 1024 cycles -0x7 - 2048 cycles -0x8 - 4096 cycles -0x9 - 8192 cycles -0xA - 16384 cycles -0xB - 32768 cycles -0xC - 65536 cycles -0xD - 131072 cycles -0xE - 262144 cycles -0xF - Unlimited Value After Reset: 0x0 Exists: Always - 4 - 4 - read-write - - - DFI_LP_EN_PD - Description: Enables DFI Low Power interface handshaking during Power Down Entry/Exit. -0 - Disabled -1 - Enabled -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - DFIUPD0 - Description: DFI Update Register 0 - 0x1a0 - 32 - 0x00400003 - 0x83FF03FF - - - DIS_AUTO_CTRLUPD - Description: When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. This register field is changeable on the fly. -When '0', uMCTL2 issues dfi_ctrlupd_req periodically. -Value After Reset: 0x0 -Exists: Always - 31 - 1 - read-write - - - DFI_T_CTRLUP_MAX - Description: Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. -Unit: Clocks -Value After Reset: 0x40 -Exists: Always - 16 - 10 - read-write - - - DFI_T_CTRLUP_MIN - Description: Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. -Unit: Clocks -Value After Reset: 0x3 -Exists: Always - 0 - 10 - read-write - - - - - DFIUPD1 - Description: DFI Update Register 1 - 0x1a4 - 32 - 0x00000000 - 0x00FF00FF - - - DFI_T_CTRLUPD_INTERVAL_MIN_X1024 - Description: This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. -Unit: 1024 clocks Value After Reset: 0x0 - Exists: Always - 16 - 8 - read-write - - - DFI_T_CTRLUPD_INTERVAL_MAX_X1024 - Description: This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. -Updates are required to maintain calibration over PVT, but frequent updates may impact performance. -Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. -Unit: 1024 clocks Value After Reset: 0x0 -Exists: Always - 0 - 8 - read-write - - - - - DFIUPD2 - Description: DFI Update Register 2 - 0x1a8 - 32 - 0x80100010 - 0x8FFF0FFF - - - DFI_PHYUPD_EN - Description: Enables the support for acknowledging PHY- initiated updates: -0 - Disabled -1 - Enabled -Value After Reset: 0x1 -Exists: Always - 31 - 1 - read-write - - - DFI_PHYUPD_TYPE1 - Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b01. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. -Value After Reset: 0x10 -Exists: Always - 16 - 12 - read-write - - - DFI_PHYUPD_TYPE0 - Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b00. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. -Value After Reset: 0x10 -Exists: Always - 0 - 12 - read-write - - - - - DFIUPD3 - Description: DFI Update Register 3 - 0x1ac - 32 - 0x00100010 - 0x0FFF0FFF - - - DFI_PHYUPD_TYPE3 - Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b11. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. -Value After Reset: 0x10 -Exists: Always - 16 - 12 - read-write - - - DFI_PHYUPD_TYPE2 - Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b10. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. -Value After Reset: 0x10 -Exists: Always - 0 - 12 - read-write - - - - - DFIMISC - Description: DFI Miscellaneous Control Register - 0x1b0 - 32 - 0x00000001 - 0x00000001 - - - DFI_INIT_COMPLETE_EN - Description: PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation -Value After Reset: 0x1 -Exists: Always - 0 - 1 - read-write - - - - - DFITMG2 - Description: DFI Timing Register 2 - 0x1b4 - 32 - 0x00000202 - 0x00003F3F - - - DFI_TPHY_RDCSLAT - Description: Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. -Value After Reset: 0x2 -Exists: Always - 8 - 6 - read-write - - - DFI_TPHY_WRCSLAT - Description: Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. The minimum supported value is as follows: -0 for configurations with MEMC_WL0 = 1 -1 for configurations with MEMC_WL0 = 0 Refer to PHY specification for correct value. Value After Reset: 0x2 -Exists: Always - 0 - 6 - read-write - - - - - ADDRMAP0 - Description: Address Map Register 0 - 0x200 - 32 - 0x00000000 - 0x0000001F - - - ADDRMAP_CS_BIT0 - Description: Selects the HIF address bit used as rank address bit 0. -Valid Range: 0 to 27, and 31 -Internal Base: 6 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 31, rank address bit 0 is set to 0. -Value After Reset: 0x0 -Exists: MEMC_NUM_RANKS>1 - 0 - 5 - read-write - - - - - ADDRMAP1 - Description: Address Map Register 1 - 0x204 - 32 - 0x00000000 - 0x001F1F1F - - - ADDRMAP_BANK_B2 - Description: Selects the HIF address bit used as bank address bit 2. -Valid Range: 0 to 29 and 31 -Internal Base: 4 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 31, bank address bit 2 is set to 0. -Value After Reset: 0x0 -Exists: Always - 16 - 5 - read-write - - - ADDRMAP_BANK_B1 - Description: Selects the HIF address bits used as bank address bit 1. -Valid Range: 0 to 30 -Internal Base: 3 -The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 8 - 5 - read-write - - - ADDRMAP_BANK_B0 - Description: Selects the HIF address bits used as bank address bit 0. -Valid Range: 0 to 30 -Internal Base: 2 -The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 0 - 5 - read-write - - - - - ADDRMAP2 - Description: Address Map Register 2 - 0x208 - 32 - 0x00000000 - 0x0F0F0F0F - - - ADDRMAP_COL_B5 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7, and 15 -Internal Base: 5 -The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. -Value After Reset: 0x0 -Exists: Always - 24 - 4 - read-write - - - ADDRMAP_COL_B4 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7, and 15 -Internal Base: 4 -The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. -Value After Reset: 0x0 -Exists: Always - 16 - 4 - read-write - - - ADDRMAP_COL_B3 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7 -Internal Base: 3 -The selected HIF address bit is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 8 - 4 - read-write - - - ADDRMAP_COL_B2 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 2 (if MEMC_BURST_LENGTH = 4) or 3 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7 -Internal Base: 2 -The selected HIF address bit is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - ADDRMAP3 - Description: Address Map Register 3 - 0x20c - 32 - 0x00000000 - 0x0F0F0F0F - - - ADDRMAP_COL_B9 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8) -Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). -(Column address bit 11 in LPDDR2/LPDDR3 mode) Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if -MEMC_BURST_LENGTH = 4) or UNUSED (if -MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7, and 15 -Internal Base: 9 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, this column address bit is set to 0. -Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. -In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 -Exists: Always - 24 - 4 - read-write - - - ADDRMAP_COL_B8 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7, and 15 -Internal Base: 8 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, this column address bit is set to 0. -Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. -In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 -Exists: Always - 16 - 4 - read-write - - - ADDRMAP_COL_B7 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7, and 15 -Internal Base: 7 -The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. -Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge and hence no source address bit can be mapped to column address bit 10. -In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 -Exists: Always - 8 - 4 - read-write - - - ADDRMAP_COL_B6 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if -MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). -Quarter bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). -Valid Range: 0 to 7, and 15 -Internal Base: 6 -The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - ADDRMAP4 - Description: Address Map Register 4 - 0x210 - 32 - 0x00000000 - 0x00000F0F - - - ADDRMAP_COL_B11 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8). -Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. -Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. -Valid Range: 0 to 7, and 15 -Internal Base: 11 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, this column address bit is set to 0. -Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. -In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 -Exists: Always - 8 - 4 - read-write - - - ADDRMAP_COL_B10 - Description: Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). -Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8) -Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. -Valid Range: 0 to 7, and 15 -Internal Base: 10 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, this column address bit is set to 0. -Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. -In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - ADDRMAP5 - Description: Address Map Register 5 - 0x214 - 32 - 0x00000000 - 0x0F0F0F0F - - - ADDRMAP_ROW_B11 - Description: Selects the HIF address bit used as row address bit 11. -Valid Range: 0 to 11, and 15 -Internal Base: 17 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, row address bit 11 is set to 0. -Value After Reset: 0x0 -Exists: Always - 24 - 4 - read-write - - - ADDRMAP_ROW_B2_10 - Description: Selects the HIF address bits used as row address bits 2 to 10. -Valid Range: 0 to 11 -Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row -address bit 10) -The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 16 - 4 - read-write - - - ADDRMAP_ROW_B1 - Description: Selects the HIF address bits used as row address bit 1. -Valid Range: 0 to 11 -Internal Base: 7 -The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 8 - 4 - read-write - - - ADDRMAP_ROW_B0 - Description: Selects the HIF address bits used as row address bit 0. -Valid Range: 0 to 11 -Internal Base: 6 -The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - ADDRMAP6 - Description: Address Map Register 6 - 0x218 - 32 - 0x00000000 - 0x0F0F0F0F - - - ADDRMAP_ROW_B15 - Description: Selects the HIF address bit used as row address bit 15. -Valid Range: 0 to 11, and 15 -Internal Base: 21 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, row address bit 15 is set to 0. -Value After Reset: 0x0 -Exists: Always - 24 - 4 - read-write - - - ADDRMAP_ROW_B14 - Description: Selects the HIF address bit used as row address bit 14. -Valid Range: 0 to 11, and 15 -Internal Base: 20 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, row address bit 14 is set to 0. -Value After Reset: 0x0 -Exists: Always - 16 - 4 - read-write - - - ADDRMAP_ROW_B13 - Description: Selects the HIF address bit used as row address bit 13. -Valid Range: 0 to 11, and 15 -Internal Base: 19 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, row address bit 13 is set to 0. -Value After Reset: 0x0 -Exists: Always - 8 - 4 - read-write - - - ADDRMAP_ROW_B12 - Description: Selects the HIF address bit used as row address bit 12. -Valid Range: 0 to 11, and 15 -Internal Base: 18 -The selected HIF address bit is determined by adding the internal base to the value of this field. -If set to 15, row address bit 12 is set to 0. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - ODTCFG - Description: ODT Configuration Register - 0x240 - 32 - 0x04000400 - 0x0F1F0F7C - - - WR_ODT_HOLD - Description: Cycles to hold ODT for a write command. The minimum supported value is 2. DDR2/DDR3/DDR4 -BL8 - 0x6 -BL4 - 0x4 -LPDDR3 - RU(tDQSSmax/tCK) + 4 -Value After Reset: 0x4 -Exists: Always - 24 - 4 - read-write - - - WR_ODT_DELAY - Description: The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. -Recommended values: -DDR2 -If (CWL + AL < 3), then 0. -If (CWL + AL >= 3), then (CWL + AL - 3) DDR3 - 0 -DDR4 - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) -LPDDR3 - (CWL - RU(tODToffmax/tCK)) -Value After Reset: 0x0 -Exists: Always - 16 - 5 - read-write - - - RD_ODT_HOLD - Description: Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2/DDR3 -BL8 - 0x6 -BL4 - 0x4 -DDR4 - 0x6, but needs to be reduced to 0x5 in CAL mode to avoid overlap of read and write ODT LPDDR3 - RU(tDQSCKmax/tCK) + 4 + 1 -Value After Reset: 0x4 -Exists: Always - 8 - 4 - read-write - - - RD_ODT_DELAY - Description: The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. -Recommended values: -DDR2 -If (CL + AL < 4), then 0. -If (CL + AL >= 4), then (CL + AL - 4) DDR3 -(CL - CWL) DDR4 -If CAL mode is enabled, CL - CWL + DFITMG1.dfi_t_cmd_lat -If CAL mode is not enabled, CL - CWL -1, or 0 if CL - CWL < 1 -LPDDR3, MEMC_FREQ_RATIO=2 -CL - RU(tODToffmax/tCK)) Value After Reset: 0x0 Exists: Always - 2 - 5 - read-write - - - - - ODTMAP - Description: ODT/Rank Map Register - 0x244 - 32 - 0x00002211 - 0x0000FFFF - - - RANK1_RD_ODT - Description: Indicates which remote ODTs must be turned on during a read from rank 1. -Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. -Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. -For each rank, set its bit to 1 to enable its ODT. -Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 - 12 - 4 - read-write - - - RANK1_WR_ODT - Description: Indicates which remote ODTs must be turned on during a write to rank 1. -Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. -Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. -For each rank, set its bit to 1 to enable its ODT. -Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 - 8 - 4 - read-write - - - RANK0_RD_ODT - Description: Indicates which remote ODTs must be turned on during a read from rank 0. -Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. -Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. -For each rank, set its bit to 1 to enable its ODT. -Value After Reset: 0x1 -Exists: Always - 4 - 4 - read-write - - - RANK0_WR_ODT - Description: Indicates which remote ODTs must be turned on during a write to rank 0. -Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. -Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. -For each rank, set its bit to 1 to enable its ODT. -Value After Reset: 0x1 -Exists: Always - 0 - 4 - read-write - - - - - SCHED - Description: Scheduler Control Register - 0x250 - 32 - 0x00000805 - 0x7FFF3F07 - - - RDWR_IDLE_GAP - Description: When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. -The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. -When prefer write over read is set this is reversed. -0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. -FOR PERFORMANCE ONLY -Value After Reset: 0x0 -Exists: Always - 24 - 7 - read-write - - - GO2CRITICAL_HYSTERESIS - Description: UNUSED Value After Reset: 0x0 Exists: Always - 16 - 8 - read-write - - - LPR_NUM_ENTRIES - Description: Number of entries in the low priority transaction store is this value + 1. -(MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. -Setting this to maximum value allocates all entries to low priority transaction store. -Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. -Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low- priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. -Value After Reset: "MEMC_NO_OF_ENTRY/2" -Exists: Always - 8 - 6 - read-write - - - PAGECLOSE - Description: If true, bank is kept open only until there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (co_ih_rxcmd_autopre). -The pageclose feature provids a midway between Open and Close page policies. -FOR PERFORMANCE ONLY. -Value After Reset: 0x1 -Exists: Always - 2 - 1 - read-write - - - PREFER_WRITE - Description: If set then the bank selector prefers writes over reads. -FOR DEBUG ONLY. -Value After Reset: 0x0 -Exists: Always - 1 - 1 - read-write - - - FORCE_LOW_PRI_N - Description: Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. -FOR PERFORMANCE ONLY. -Value After Reset: 0x1 -Exists: Always - 0 - 1 - read-write - - - - - SCHED1 - Description: Scheduler Control Register 1 - 0x254 - 32 - 0x00000000 - 0x000000FF - - - PAGECLOSE_TIMER - Description: This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. -If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. -If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. -Value After Reset: 0x0 -Exists: Always - 0 - 8 - read-write - - - - - PERFHPR1 - Description: High Priority Read CAM Register 1 - 0x25c - 32 - 0x0F000001 - 0xFF00FFFF - - - HPR_XACT_RUN_LENGTH - Description: Number of transactions that are serviced once the HPR queue goes critical is the smaller of: -This number -Number of transactions available Unit: Transaction. -FOR PERFORMANCE ONLY. -Value After Reset: 0xf -Exists: Always - 24 - 8 - read-write - - - HPR_MAX_STARVE - Description: Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. -Unit: Clock cycles. -FOR PERFORMANCE ONLY. -Value After Reset: 0x1 -Exists: Always - 0 - 16 - read-write - - - - - PERFLPR1 - Description: Low Priority Read CAM Register 1 - 0x264 - 32 - 0x0F00007F - 0xFF00FFFF - - - LPR_XACT_RUN_LENGTH - Description: Number of transactions that are serviced once the LPR queue goes critical is the smaller of: -This number -Number of transactions available. Unit: Transaction. -FOR PERFORMANCE ONLY. -Value After Reset: 0xf -Exists: Always - 24 - 8 - read-write - - - LPR_MAX_STARVE - Description: Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. -Unit: Clock cycles. -FOR PERFORMANCE ONLY. -Value After Reset: 0x7f -Exists: Always - 0 - 16 - read-write - - - - - PERFWR1 - Description: Write CAM Register 1 - 0x26c - 32 - 0x0F00007F - 0xFF00FFFF - - - W_XACT_RUN_LENGTH - Description: Number of transactions that are serviced once the WR queue goes critical is the smaller of: -This number -Number of transactions available. Unit: Transaction. -FOR PERFORMANCE ONLY. -Value After Reset: 0xf -Exists: Always - 24 - 8 - read-write - - - W_MAX_STARVE - Description: Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. -Unit: Clock cycles. -FOR PERFORMANCE ONLY. -Value After Reset: 0x7f -Exists: Always - 0 - 16 - read-write - - - - - PERFVPR1 - Description: Variable Priority Read CAM Register 1 - 0x274 - 32 - 0x00000000 - 0x000007FF - - - VPR_TIMEOUT_RANGE - Description: Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPR commands whose timeout counters are 15 or below will be considered as expired-VPR commands when the timeout value of any of the VPR commands reach 0. The expired-VPR commands, when present, are given higher priority than HPR commands. The VPR commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. -The Max value for this register is 0x7FF and the Min value is 0x0. -When programmed to the Max value of 0x7FF, all the VPR commands that come in to DDRC will time-out right-away and will be considered as expired-VPR. -When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPR. -Unit: Clock cycles. -FOR PERFORMANCE ONLY. -Value After Reset: 0x0 -Exists: UMCTL2_VPR_EN==1 - 0 - 11 - read-write - - - - - PERFVPW1 - Description: Variable Priority Write CAM Register 1 - 0x278 - 32 - 0x00000000 - 0x000007FF - - - VPW_TIMEOUT_RANGE - Description: Indicates the range of the timeout value that is used for grouping the expired VPW commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPW commands whose timeout counters are 15 or below will be considered as expired-VPW commands when the timeout value of any of the VPW commands reach 0. The expired-VPW commands, when present, are given higher priority than normal Write commands. The VPW commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. -The Max value for this register is 0x7FF and the Min value is 0x0. -When programmed to the Max value of 0x7FF, all the VPW commands that come in to DDRC will time-out right-away and will be considered as expired-VPW. -When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPW. -Unit: Clock cycles. -FOR PERFORMANCE ONLY. -Value After Reset: 0x0 -Exists: UMCTL2_VPW_EN==1 - 0 - 11 - read-write - - - - - DBG0 - Description: Debug Register 0 - 0x300 - 32 - 0x00000000 - 0x00000017 - - - DIS_COLLISION_PAGE_OPT - Description: When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). -FOR DEBUG ONLY. -Value After Reset: 0x0 -Exists: Always - 4 - 1 - read-write - - - DIS_ACT_BYPASS - Description: Only present in designs supporting activate bypass. -When 1, disable bypass path for high priority read activates FOR DEBUG ONLY. -Value After Reset: 0x0 -Exists: MEMC_BYPASS==1 - 2 - 1 - read-write - - - DIS_RD_BYPASS - Description: Only present in designs supporting read bypass. -When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY. -Value After Reset: 0x0 -Exists: MEMC_BYPASS==1 - 1 - 1 - read-write - - - DIS_WC - Description: When 1, disable write combine. FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - DBG1 - Description: Debug Register 1 - 0x304 - 32 - 0x00000000 - 0x00000003 - - - DIS_HIF - Description: When 1, uMCTL2 asserts the HIF command ih_co_stall. uMCTL2 will ignore the co_ih_rxcmd_valid and all other associated request signals. -This bit is intended to be switched on-the-fly. -Value After Reset: 0x0 -Exists: Always - 1 - 1 - read-write - - - DIS_DQ - Description: When 1, uMCTL2 will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. -This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. -This bit is intended to be switched on-the-fly. -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - DBGCAM - Description: CAM Debug Register - 0x308 - 32 - 0x00000000 - 0x377F7F7F - - - WR_DATA_PIPELINE_EMPTY - Description: This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. -Value After Reset: 0x0 -Exists: Always - 29 - 1 - read-only - - - RD_DATA_PIPELINE_EMPTY - Description: This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. -Value After Reset: 0x0 -Exists: Always - 28 - 1 - read-only - - - DBG_WR_Q_EMPTY - Description: When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. -An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. -FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 26 - 1 - read-only - - - DBG_RD_Q_EMPTY - Description: When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. -An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. -FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 25 - 1 - read-only - - - DBG_STALL - Description: Stall FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 24 - 1 - read-only - - - DBG_W_Q_DEPTH - Description: Write queue depth -Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth -= 32, then register width is 6 bits and bit 22 is reserved. FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 16 - 7 - read-only - - - DBG_LPR_Q_DEPTH - Description: Low priority read queue depth Note: The width of this field is dependent on -log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth -= 32, then register width is 6 bits and bit 14 is reserved FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 8 - 7 - read-only - - - DBG_HPR_Q_DEPTH - Description: High priority read queue depth Note: The width of this field is dependent on -log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth -= 32, then register width is 6 bits and bit 6 is reserved FOR DEBUG ONLY -Value After Reset: 0x0 -Exists: Always - 0 - 7 - read-only - - - - - DBGCMD - Description: Command Debug Register - 0x30c - 32 - 0x00000000 - 0x00000033 - - - CTRLUPD - Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. -Value After Reset: 0x0 -Exists: Always - 5 - 1 - read-write - - - ZQ_CALIB_SHORT - Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short) command to the SDRAM. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh and Deep power-down operating modes. -Value After Reset: 0x0 -Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 - 4 - 1 - read-write - - - RANK1_REFRESH - Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. -Value After Reset: 0x0 -Exists: MEMC_NUM_RANKS>1 - 1 - 1 - read-write - - - RANK0_REFRESH - Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - DBGSTAT - Description: Status Debug Register - 0x310 - 32 - 0x00000000 - 0x00000033 - - - CTRLUPD_BUSY - Description: SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in uMCTL2. It is recommended not to perform ctrlupd operations when this signal is high. -0 - Indicates that the SoC core can initiate a ctrlupd operation -1 - Indicates that ctrlupd operation has not been initiated yet in uMCTL2 -Value After Reset: 0x0 -Exists: Always - 5 - 1 - read-only - - - ZQ_CALIB_SHORT_BUSY - Description: SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. -0 - Indicates that the SoC core can initiate a ZQCS operation -1 - Indicates that ZQCS operation has not been initiated yet in uMCTL2 -Value After Reset: 0x0 -Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 - 4 - 1 - read-only - - - RANK1_REFRESH_BUSY - Description: SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in uMCTL2. It is recommended not to perform rank1_refresh operations when this signal is high. -0 - Indicates that the SoC core can initiate a rank1_refresh operation -1 - Indicates that rank1_refresh operation has not been stored yet in uMCTL2 -Value After Reset: 0x0 -Exists: MEMC_NUM_RANKS>1 - 1 - 1 - read-only - - - RANK0_REFRESH_BUSY - Description: SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in uMCTL2. It is recommended not to perform rank0_refresh operations when this signal is high. -0 - Indicates that the SoC core can initiate a rank0_refresh operation -1 - Indicates that rank0_refresh operation has not been stored yet in uMCTL2 -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-only - - - - - PSTAT - Description: Port Status Register - 0x3fc - 32 - 0x00000000 - 0xFFFFFFFF - - - WR_PORT_BUSY_15 - Description: Indicates if there are outstanding writes for port 15. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_15==1 - 31 - 1 - read-only - - - WR_PORT_BUSY_14 - Description: Indicates if there are outstanding writes for port 14. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_14==1 - 30 - 1 - read-only - - - WR_PORT_BUSY_13 - Description: Indicates if there are outstanding writes for port 13. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_13==1 - 29 - 1 - read-only - - - WR_PORT_BUSY_12 - Description: Indicates if there are outstanding writes for port 12. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_12==1 - 28 - 1 - read-only - - - WR_PORT_BUSY_11 - Description: Indicates if there are outstanding writes for port 11. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_11==1 - 27 - 1 - read-only - - - WR_PORT_BUSY_10 - Description: Indicates if there are outstanding writes for port 10. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_10==1 - 26 - 1 - read-only - - - WR_PORT_BUSY_9 - Description: Indicates if there are outstanding writes for port 9. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_9==1 - 25 - 1 - read-only - - - WR_PORT_BUSY_8 - Description: Indicates if there are outstanding writes for port 8. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_8==1 - 24 - 1 - read-only - - - WR_PORT_BUSY_7 - Description: Indicates if there are outstanding writes for port 7. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_7==1 - 23 - 1 - read-only - - - WR_PORT_BUSY_6 - Description: Indicates if there are outstanding writes for port 6. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_6==1 - 22 - 1 - read-only - - - WR_PORT_BUSY_5 - Description: Indicates if there are outstanding writes for port 5. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_5==1 - 21 - 1 - read-only - - - WR_PORT_BUSY_4 - Description: Indicates if there are outstanding writes for port 4. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_4==1 - 20 - 1 - read-only - - - WR_PORT_BUSY_3 - Description: Indicates if there are outstanding writes for port 3. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_3==1 - 19 - 1 - read-only - - - WR_PORT_BUSY_2 - Description: Indicates if there are outstanding writes for port 2. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_2==1 - 18 - 1 - read-only - - - WR_PORT_BUSY_1 - Description: Indicates if there are outstanding writes for port 1. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_1==1 - 17 - 1 - read-only - - - WR_PORT_BUSY_0 - Description: Indicates if there are outstanding writes for port 0. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_0==1 - 16 - 1 - read-only - - - RD_PORT_BUSY_15 - Description: Indicates if there are outstanding reads for port 15. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_15==1 - 15 - 1 - read-only - - - RD_PORT_BUSY_14 - Description: Indicates if there are outstanding reads for port 14. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_14==1 - 14 - 1 - read-only - - - RD_PORT_BUSY_13 - Description: Indicates if there are outstanding reads for port 13. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_13==1 - 13 - 1 - read-only - - - RD_PORT_BUSY_12 - Description: Indicates if there are outstanding reads for port 12. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_12==1 - 12 - 1 - read-only - - - RD_PORT_BUSY_11 - Description: Indicates if there are outstanding reads for port 11. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_11==1 - 11 - 1 - read-only - - - RD_PORT_BUSY_10 - Description: Indicates if there are outstanding reads for port 10. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_10==1 - 10 - 1 - read-only - - - RD_PORT_BUSY_9 - Description: Indicates if there are outstanding reads for port 9. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_9==1 - 9 - 1 - read-only - - - RD_PORT_BUSY_8 - Description: Indicates if there are outstanding reads for port 8. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_8==1 - 8 - 1 - read-only - - - RD_PORT_BUSY_7 - Description: Indicates if there are outstanding reads for port 7. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_7==1 - 7 - 1 - read-only - - - RD_PORT_BUSY_6 - Description: Indicates if there are outstanding reads for port 6. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_6==1 - 6 - 1 - read-only - - - RD_PORT_BUSY_5 - Description: Indicates if there are outstanding reads for port 5. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_5==1 - 5 - 1 - read-only - - - RD_PORT_BUSY_4 - Description: Indicates if there are outstanding reads for port 4. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_4==1 - 4 - 1 - read-only - - - RD_PORT_BUSY_3 - Description: Indicates if there are outstanding reads for port 3. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_3==1 - 3 - 1 - read-only - - - RD_PORT_BUSY_2 - Description: Indicates if there are outstanding reads for port 2. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_2==1 - 2 - 1 - read-only - - - RD_PORT_BUSY_1 - Description: Indicates if there are outstanding reads for port 1. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_1==1 - 1 - 1 - read-only - - - RD_PORT_BUSY_0 - Description: Indicates if there are outstanding reads for port 0. -Value After Reset: 0x0 -Exists: UMCTL2_PORT_0==1 - 0 - 1 - read-only - - - - - PCCFG - Description: Port Common Configuration Register - 0x400 - 32 - 0x00000000 - 0x00000011 - - - PAGEMATCH_LIMIT - Description: Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. -Value After Reset: 0x0 -Exists: Always - 4 - 1 - read-write - - - GO2CRITICAL_EN - Description: If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_rd signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_rd signals at DDRC are driven to 1b'0. -Value After Reset: 0x0 -Exists: Always - 0 - 1 - read-write - - - - - 16 - 0xb0 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - PCFG[%s] - no description available - 0x404 - - R - Description: Port n Configuration Read Register - 0x0 - 32 - 0x00004000 - 0x000073FF - - - RD_PORT_PAGEMATCH_EN - Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. -Value After Reset: "(MEMC_DDR4_EN==1) ? 0x0 : 0x1" -Exists: Always - 14 - 1 - read-write - - - RD_PORT_URGENT_EN - Description: If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_rd signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). -Value After Reset: 0x0 -Exists: Always - 13 - 1 - read-write - - - RD_PORT_AGING_EN - Description: If set to 1, enables aging function for the read channel of the port. -Value After Reset: 0x0 -Exists: Always - 12 - 1 - read-write - - - RD_PORT_PRIORITY - Description: Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. -When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition -- Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00. -Value After Reset: 0x0 -Exists: Always - 0 - 10 - read-write - - - - - W - Description: Port n Configuration Write Register - 0x4 - 32 - 0x00004000 - 0x000073FF - - - WR_PORT_PAGEMATCH_EN - Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. -Value After Reset: 0x1 -Exists: Always - 14 - 1 - read-write - - - WR_PORT_URGENT_EN - Description: If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). -Value After Reset: 0x0 -Exists: Always - 13 - 1 - read-write - - - WR_PORT_AGING_EN - Description: If set to 1, enables aging function for the write channel of the port. -Value After Reset: 0x0 -Exists: Always - 12 - 1 - read-write - - - WR_PORT_PRIORITY - Description: Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the -write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00. -Value After Reset: 0x0 -Exists: Always - 0 - 10 - read-write - - - - - C - Description: Port n Common Configuration Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - AHB_ENDIANNESS - Description: If set to 0, enables support for little endian on the AHB port. If set to 1, enables support for big endian (BE- 32) on the AHB port. If set to 2, enables support for big endian (BE-A) on the AHB port. -Value After Reset: 0x0 -Exists: UMCTL2_A_AHB_n==1 - 0 - 2 - read-write - - - - - 16 - 0x8 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - ID[%s] - no description available - 0xc - - MASKCH - Description: Port n Channel m Configuration ID Mask Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ID_MASK - Description: Determines the mask used in the ID mapping function for virtual channel m. -Value After Reset: 0x0 -Exists: Always - 0 - 32 - read-write - - - - - VALUECH - Description: Port n Channel m Configuration ID Value Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ID_VALUE - Description: Determines the value used in the ID mapping function for virtual channel m. -Value After Reset: 0x0 -Exists: Always - 0 - 32 - read-write - - - - - - CTRL - Description: Port n Control Register - 0x8c - 32 - 0x00000000 - 0x00000001 - - - PORT_EN - Description: Enables port n. -Value After Reset: "UMCTL2_PORT_EN_RESET_VALUE" -Exists: Always - 0 - 1 - read-write - - - - - QOS0 - Description: Port n Read QoS Configuration Register 0 - 0x90 - 32 - 0x00000000 - 0x0033000F - - - RQOS_MAP_REGION1 - Description: This bitfield indicates the traffic class of region -1. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. -Value After Reset: 0x0 -Exists: Always - 20 - 2 - read-write - - - RQOS_MAP_REGION0 - Description: This bitfield indicates the traffic class of region -0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. -Value After Reset: 0x0 -Exists: Always - 16 - 2 - read-write - - - RQOS_MAP_LEVEL1 - Description: Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13(for dual RAQ) or 0 to 14(for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - QOS1 - Description: Port n Read QoS Configuration Register 1 - 0x94 - 32 - 0x00000000 - 0x07FF07FF - - - RQOS_MAP_TIMEOUTR - Description: Specifies the timeout value for transactions mapped to the red address queue. -Value After Reset: 0x0 -Exists: Always - 16 - 11 - read-write - - - RQOS_MAP_TIMEOUTB - Description: Specifies the timeout value for transactions mapped to the blue address queue. -Value After Reset: 0x0 -Exists: Always - 0 - 11 - read-write - - - - - WQOS0 - Description: Port n Write QoS Configuration Register 0 - 0x98 - 32 - 0x00000000 - 0x0033000F - - - WQOS_MAP_REGION1 - Description: This bitfield indicates the traffic class of region -1. Valid values are: -0: NPW -1: VPW -When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. -Value After Reset: 0x0 -Exists: Always - 20 - 2 - read-write - - - WQOS_MAP_REGION0 - Description: This bitfield indicates the traffic class of region -0. Valid values are: -0: NPW -1: VPW -When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. -Value After Reset: 0x0 -Exists: Always - 16 - 2 - read-write - - - WQOS_MAP_LEVEL - Description: Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. -Value After Reset: 0x0 -Exists: Always - 0 - 4 - read-write - - - - - WQOS1 - Description: Port n Write QoS Configuration Register 1 - 0x9c - 32 - 0x00000000 - 0x000007FF - - - WQOS_MAP_TIMEOUT - Description: Specifies the timeout value for write transactions. -Value After Reset: 0x0 -Exists: Always - 0 - 11 - read-write - - - - - - 4 - 0x8 - 0,1,2,3 - SAR[%s] - no description available - 0xf04 - - BASE - Description: SAR Base Address Register n - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - BASE_ADDR - Description: Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). -Value After Reset: 0x0 -Exists: Always - 0 - 32 - read-write - - - - - SIZE - Description: SAR Size Register n - 0x4 - 32 - 0x00000000 - 0x000000FF - - - NBLOCKS - Description: Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. -Value After Reset: 0x0 -Exists: Always - 0 - 8 - read-write - - - - - - SBRCTL - Description: Scrubber Control Register - 0xf24 - 32 - 0x0000FF10 - 0x001FFF77 - - - SCRUB_INTERVAL - Description: Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0, scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full range of memory at once before or after SW controlled low power operations. After completing the full range of scrub while scrub_interval=0, scrub_done register is set and sbr_done_intr interrupt signal is asserted. -Value After Reset: 0xff -Exists: UMCTL2_SBR_EN_1==1 - 8 - 13 - read-write - - - SCRUB_BURST - Description: Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes. During low power, the period of the scrub burst becomes \"scrub_burst*scrub_interval\" cycles. -During normal operation mode of the controller (ie. not in power-down or self refresh), scrub_burst is ignored and only one scrub command is generated. Valid values are: 1: 1 read, 2: 4 reads, 3: 16 reads, 4: 64 reads, 5: 256 reads, -6: 1024 reads. -Value After Reset: 0x1 -Exists: UMCTL2_SBR_EN_1==1 - 4 - 3 - read-write - - - SCRUB_MODE - Description: scrub_mode:0 ECC scrubber will perform reads scrub_mode:1 ECC scrubber will perform writes Value After Reset: 0x0 -Exists: UMCTL2_SBR_EN_1==1 - 2 - 1 - read-write - - - SCRUB_DURING_LOWPOWER - Description: Continue scrubbing during low power. If set to 1, burst of scrubs will be issued in HW controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by HW low-power (LP) interface. If set to 0, the scrubber will not attempt to send commands while the DDRC is in HW controlled low power modes. In this case, the scrubber will remember the last address issued and will automatically continue from there when the DDRC exits the LP mode. -Value After Reset: 0x0 -Exists: UMCTL2_SBR_EN_1==1 - 1 - 1 - read-write - - - SCRUB_EN - Description: Enable ECC scrubber. If set to 1, enables the scrubber to generate background read commands after the memories are initialized. If set to 0, disables the scrubber, resets the address generator to 0 and clears the scrubber status. This bitfield must be accessed separately from the other bitfields in this register. -Value After Reset: 0x0 -Exists: UMCTL2_SBR_EN_1==1 - 0 - 1 - read-write - - - - - SBRSTAT - Description: Scrubber Status Register - 0xf28 - 32 - 0x00000000 - 0x00000003 - - - SCRUB_DONE - Description: Scrubber done. Controller sets this bit to 1, after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal scrub operation. The interrupt signal, sbr_done_intr, is equivalent to this status bitfield. -Value After Reset: 0x0 -Exists: UMCTL2_SBR_EN_1==1 - 1 - 1 - read-only - - - SCRUB_BUSY - Description: Scrubber busy. Controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. -Value After Reset: 0x0 -Exists: UMCTL2_SBR_EN_1==1 - 0 - 1 - read-only - - - - - SBRWDATA0 - Description: Scrubber Write Data Pattern0 - 0xf2c - 32 - 0x00000000 - 0xFFFFFFFF - - - SCRUB_PATTERN0 - Description: ECC Scrubber write data pattern for data bus[31:0] -Value After Reset: 0x0 -Exists: UMCTL2_SBR_EN_1==1 - 0 - 32 - read-write - - - - - - - FFA - FFA - FFA - 0xf3018000 - - 0x0 - 0x48 - registers - - - - CTRL - No description available - 0x0 - 32 - 0x00000000 - 0x80000001 - - - SFTRST - software reset the module if asserted to be 1. -EN is only active after this bit is zero. - 31 - 1 - read-write - - - EN - Asserted to enable the module - 0 - 1 - read-write - - - - - STATUS - No description available - 0x4 - 32 - 0x00000000 - 0x000000FF - - - FIR_OV - FIR Overflow err - 7 - 1 - write-only - - - FFT_OV - FFT Overflow Err - 6 - 1 - write-only - - - WR_ERR - AXI Data Write Error - 5 - 1 - write-only - - - RD_NXT_ERR - AXI Read Bus Error for NXT DATA - 4 - 1 - write-only - - - RD_ERR - AXI Data Read Error - 3 - 1 - write-only - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - write-only - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - write-only - - - - - INT_EN - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRSV1 - Reserved - 8 - 24 - read-write - - - FIR_OV - FIR Overflow err - 7 - 1 - read-write - - - FFT_OV - FFT Overflow Err - 6 - 1 - read-write - - - WR_ERR - Enable Data Write Error interrupt - 5 - 1 - read-write - - - RD_NXT_ERR - Enable Read Bus Error for NXT DATA interrupt - 4 - 1 - read-write - - - RD_ERR - Enable Data Read Error interrupt - 3 - 1 - read-write - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - read-write - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - read-write - - - - - OP_CTRL - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - NXT_ADDR - The address for the next command. -It will be processed after CUR_CMD is executed and done.. - 2 - 30 - read-write - - - NXT_EN - Whether NXT_CMD is enabled. -Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - 1 - 1 - read-write - - - EN - Whether CUR_CMD is enabled. -Asserted to enable the CUR_CMD - 0 - 1 - read-write - - - - - OP_CMD - No description available - 0x24 - 32 - 0x00000000 - 0x01FFFEFF - - - CONJ_C - asserted to have conjuate value for coefs in computation - 24 - 1 - read-write - - - CMD - The Command Used: -0: FIR -2: FFT -Others: Reserved - 18 - 6 - read-write - - - OUTD_TYPE - Output data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 15 - 3 - read-write - - - COEF_TYPE - Coef data type (used for FIR): -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 12 - 3 - read-write - - - IND_TYPE - Input data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 9 - 3 - read-write - - - NXT_CMD_LEN - The length of nxt commands in 32-bit words - 0 - 8 - read-write - - - - - OP_REG0 - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0x00003FFF - - - FIR_COEF_TAPS - Length of FIR coefs （max 256） - 0 - 14 - read-write - - - - - OP_FFT_MISC - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000007FF - - - FFT_LEN - FFT length -0:8, -..., -n:2^(3+n) - 7 - 4 - read-write - - - IFFT - Asserted to indicate IFFT - 6 - 1 - read-write - - - TMP_BLK - Memory block for indata. Should be assigned as 1 - 2 - 2 - read-write - - - IND_BLK - Memory block for indata. Should be assigned as 0 - 0 - 2 - read-write - - - - - OP_REG1 - No description available - UNION_2C - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC1 - No description available - UNION_2C - 0x2c - 32 - 0x00000000 - 0x003FFFFF - - - OUTD_MEM_BLK - Should be assigned as 0 - 20 - 2 - read-write - - - COEF_MEM_BLK - Should be assigned as 1 - 18 - 2 - read-write - - - IND_MEM_BLK - Should be assigned as 2 - 16 - 2 - read-write - - - FIR_DATA_TAPS - The input data data length - 0 - 16 - read-write - - - - - OP_REG2 - No description available - UNION_30 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FFT_INRBUF - No description available - UNION_30 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG3 - No description available - UNION_34 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_INBUF - No description available - UNION_34 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input data buffer pointer - 0 - 32 - read-write - - - - - OP_REG4 - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_COEFBUF - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The coef buf pointer - 0 - 32 - read-write - - - - - OP_FFT_OUTRBUF - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG5 - No description available - UNION_3C - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_OUTBUF - No description available - UNION_3C - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - 0 - 32 - read-write - - - - - OP_REG6 - No description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_REG7 - No description available - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - - - SDP - SDP - SDP - 0xf3040000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - SEC - SEC - SEC - 0xf3044000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - MON - MON - MON - 0xf3048000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - RNG - RNG - RNG - 0xf304c000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - OTP - OTP - OTP - 0xf3050000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - KEYM - KEYM - KEYM - 0xf3054000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x2c00 - registers - - - - 200 - 0x4 - cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_vis,pow_cpu0,pow_gpu,rsv24,rst_soc,rst_con,rst_vis,rst_cpu0,rst_gpu,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll3,clk_src_clk0_pll3,clk_src_pll4,clk_src_clk0_pll4,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,clk_src_pll3_ref,clk_src_pll4_ref,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_gpu0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axiv,clk_top_axid,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_lin4,clk_top_lin5,clk_top_lin6,clk_top_lin7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_xpi0,clk_top_xram,clk_top_ana0,clk_top_ana1,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_aud3,clk_top_eth0,clk_top_ptp0,clk_top_sdc0,clk_top_sdc1,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_cam0,clk_top_cam1,clk_top_lcd0,clk_top_lcd1,clk_top_csi0,clk_top_csi1,clk_top_adc0,clk_top_adc1,clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3,rsv139,rsv140,rsv141,rsv142,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,axis,axic,axiv,axig,lmm0,mct0,rom0,ddr0,xram,can0,can1,can2,can3,can4,can5,can6,can7,ptpc,crc0,oamp,lin0,lin1,lin2,lin3,lin4,lin5,lin6,lin7,i2c0,i2c1,i2c2,i2c3,spi0,spi1,spi2,spi3,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,wdg0,wdg1,mbx0,mbx1,tmr0,tmr1,tmr2,tmr3,tmr4,tmr5,tmr6,tmr7,i2s0,i2s1,i2s2,i2s3,pdm0,dao0,smix,rng0,sdp0,kman,gpio,adc0,adc1,sdm0,hdma,xdma,xpi0,ffa0,tsns,eth0,usb0,sdc0,sdc1,ntm0,ref0,ref1,cam0,cam1,pdma,jpeg,lcd0,lcd1,gwc0,gwc1,csi0,csi1,dsi0,dsi1,lvb0,lcb0,gpu0 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 4 - 0x10 - link0,link1,link2,link3 - GROUP0[%s] - no description available - 0x800 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 1 - 0x10 - cpu0 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - - 1 - 0x10 - cpu0 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Control - 0x0 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu0 stop -bit01: soc_ctx is kept on while cpu0 stop -bit02: cpu0_mem is kept on while cpu0 stop -bit03: cpu0_ctx is kept on while cpu0 stop -bit04: con_ctx is kept on while cpu0 stop -bit05: vis_mem is kept on while cpu0 stop -bit06: vis_ctx is kept on while cpu0 stop -bit07: gpu_mem is kept on while cpu0 stop -bit08: gpu_ctx is kept on while cpu0 stop -bit09: xtal_hold is kept on while cpu0 stop -bit10: pll0_hold is kept on while cpu0 stop -bit11: pll1_hold is kept on while cpu0 stop -bit12: pll2_hold is kept on while cpu0 stop -bit13: pll3 is kept on while cpu0 stop -bit14: pll4 is kept on while cpu0 stop - 0 - 15 - read-write - - - - - SET - Retention Control - 0x4 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 15 - read-write - - - - - CLEAR - Retention Control - 0x8 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 15 - read-write - - - - - TOGGLE - Retention Control - 0xc - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 15 - read-write - - - - - - 3 - 0x10 - vis,cpu0,gpu - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x000000FF - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x0000000F - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 5 - 0x10 - soc,con,vis,cpu0,gpu - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automatically - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00402003 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 69 - 0x4 - clk_top_cpu0,clk_top_mct0,clk_top_gpu0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axiv,clk_top_axid,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_lin0,clk_top_lin1,clk_top_lin2,clk_top_lin3,clk_top_lin4,clk_top_lin5,clk_top_lin6,clk_top_lin7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_xpi0,clk_top_xram,clk_top_ana0,clk_top_ana1,clk_top_aud0,clk_top_aud1,clk_top_aud2,clk_top_aud3,clk_top_eth0,clk_top_ptp0,clk_top_sdc0,clk_top_sdc1,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_cam0,clk_top_cam1,clk_top_lcd0,clk_top_lcd1,clk_top_csi0,clk_top_csi1 - CLOCK[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xD00007FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll1_clk0 -3:pll1_clk1 -4:pll2_clk0 -5:pll2_clk1 -6:pll3_clk0 -7:pll4_clk0 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 2 - 0x4 - clk_top_adc0,clk_top_adc1 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock N -1: axis clock - 8 - 1 - read-write - - - - - 4 - 0x4 - clk_top_i2s0,clk_top_i2s1,clk_top_i2s2,clk_top_i2s3 - I2SCLK[%s] - no description available - 0x1c08 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock N -1: aud clock 0 for others , aud clock 1 for i2s0 - 8 - 1 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x000000FF - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 -bit4: override to preset4 -bit5: override to preset5 -bit6: override to preset6 -bit7: override to preset7 - 0 - 8 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - reference clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 1 - 0x400 - cpu0 - CPU[%s] - no description available - 0x2800 - - LP - CPU0 LP control - 0x0 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - CPU0 Lock GPR - 0x4 - 32 - 0x00000000 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 4 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 4 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf80 - registers - - - - 496 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,pf11,pf12,pf13,pf14,pf15,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,rsv352,rsv353,rsv354,rsv355,rsv356,rsv357,rsv358,rsv359,rsv360,rsv361,rsv362,rsv363,rsv364,rsv365,rsv366,rsv367,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,rsv384,rsv385,rsv386,rsv387,rsv388,rsv389,rsv390,rsv391,rsv392,rsv393,rsv394,rsv395,rsv396,rsv397,rsv398,rsv399,rsv400,rsv401,rsv402,rsv403,rsv404,rsv405,rsv406,rsv407,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,px08,px09,px10,px11,px12,px13,px14,px15,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,py08,py09,py10,py11,py12,py13,py14,py15,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07,pz08,pz09,pz10,pz11,pz12,pz13,pz14,pz15 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -... -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf4118000 - - - BIOC - BIOC - IOC - 0xf4210000 - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf40c0000 - - 0x0 - 0x300 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 5 - 0x80 - pll0,pll1,pll2,pll3,pll4 - PLL[%s] - no description available - 0x80 - - MFI - PLL0 multiple register - 0x0 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - MFN - PLL0 fraction numerator register - 0x4 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - MFD - PLL0 fraction demoninator register - 0x8 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - SS_STEP - PLL0 spread spectrum step register - 0xc - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - SS_STOP - PLL0 spread spectrum stop register - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - CONFIG - PLL0 confguration register - 0x14 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - LOCKTIME - PLL0 lock time register - 0x18 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - STEPTIME - PLL0 step time register - 0x1c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - ADVANCED - PLL0 advance configuration register - 0x20 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - 3 - 0x4 - DIV0,DIV1,DIV2 - DIV[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - - PPOR - PPOR - PPOR - 0xf4100000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature(not available) -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature(not available) -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-only - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HOLD - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature(not available) -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature(not available) -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf4104000 - - 0x0 - 0xac - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x831F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - LOWPOWER_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 25 - 1 - read-write - - - POWER_SAVE - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 24 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x0003047E - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00000384 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000000 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDC shuts down when power loss -1: power loss protection disabled, DCDC try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x05120067 - 0x073F006F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00006E1C - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 5: VAD interrupt -bit 6: VAD wake interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 5: VAD interrupt -bit 6: VAD wake interrupt -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit16: Security violation in BATT -bit17: GPIO in BATT interrupt -bit19: RTC alarm interrupt - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart -bit16-17:VAD -bit18-19:SRAM - 0 - 32 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000310 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - DCDCM_MODE - DCDCM mode select - 0x80 - 32 - 0x00030546 - 0x10070FFF - - - READY - Ready flag -0: DCDCM is applying new change -1: DCDCM is ready - 28 - 1 - read-only - - - MODE - DCDCM work mode -XX0: turn off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDCM voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDCM_LPMODE - DCDCM low power mode - 0x84 - 32 - 0x00000546 - 0x00000FFF - - - STBY_VOLT - DCDCM voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDCM_PROT - DCDCM protection - 0x88 - 32 - 0x00000010 - 0x11818191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - DISABLE_POWER_LOSS - disable power loss protection -0: power loss protection enabled, DCDCM shuts down when power loss -1: power loss protection disabled, DCDCM try working after power voltage drop - 23 - 1 - read-write - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - output over voltage protection -0: protection enabled, DCDCM will shut down is output voltage is unexpected high -1: protection disabled, DCDCM continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDCM shut down if short circuit on output detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDCM_CURRENT - DCDCM current estimation - 0x8c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDCM current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDCM_ADVMODE - DCDCM advance setting - 0x90 - 32 - 0x05120067 - 0x073F007F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_AUTOLP - enable auto enter low power mode -0: do not enter low power mode -1: enter low power mode if current is detected low - 4 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDCM_ADVPARAM - DCDCM advance parameter - 0x94 - 32 - 0x0000701C - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDCM_MISC - DCDCM misc parameter - 0x98 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDCM internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDCM_DEBUG - DCDCM Debug - 0x9c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDCM voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDCM_START_TIME - DCDCM ramp time - 0xa0 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDCM to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDCM_RESUME_TIME - DCDCM resume time - 0xa4 - 32 - 0x000000F0 - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDCM to recover from low power mode, in 24M clock cycles, default value is 10uS - 0 - 20 - read-write - - - - - DCDCM_POWER_CONFIG - DCDCM power config - 0xa8 - 32 - 0x00000000 - 0x00010000 - - - RETENTION - DCDCM enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDCM -1: reduce DCDC voltage - 16 - 1 - read-write - - - - - - - PGPR0 - PGPR0 - PGPR - 0xf4110000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PGPR1 - PGPR1 - PGPR - 0xf4114000 - - - VAD - VAD - VAD - 0xf412c000 - - 0x0 - 0xa4 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x0FF7FBFF - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 24 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 20 - 4 - read-write - - - VAD_IE - VAD event interrupt enable - 18 - 1 - read-write - - - OFIFO_AV_IE - OFIFO data available interrupt enable - 17 - 1 - read-write - - - MEMBUF_EMPTY_IE - Buf empty interrupt enable - 16 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - OFIFO overflow error interrupt enable - 15 - 1 - read-write - - - IIR_OVLD_ERR_IE - IIR overload error interrupt enable - 14 - 1 - read-write - - - IIR_OVFL_ERR_IE - IIR overflow error interrupt enable - 13 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload Interrupt Enable - 12 - 1 - read-write - - - CIC_SAT_ERR_IE - CIC saturation Interrupt Enable - 11 - 1 - read-write - - - MEMBUF_DISABLE - asserted to disable membuf - 9 - 1 - read-write - - - FIFO_THRSH - OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - 5 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 4 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 3 - 1 - read-write - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 1 - 2 - read-write - - - CHNUM - the number of channels to be stored in buffer. Asserted to enable 2 channels. - 0 - 1 - read-write - - - - - FILTCTRL - Filter Control Register - 0x4 - 32 - 0x00000000 - 0x000007FF - - - DECRATIO - the decimation ratio of iir after CIC -1 -2: means dec-by-3 - 8 - 3 - read-write - - - IIR_SLOT_EN - IIR slot enable - 0 - 8 - read-write - - - - - DEC_CTRL0 - Decision Control Register 0 - 0x8 - 32 - 0x00000000 - 0xFFFF03FF - - - NOISE_TOL - the value of amplitude for noise determination when calculationg ZCR - 16 - 16 - read-write - - - BLK_CFG - asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - 9 - 1 - read-write - - - SUBBLK_LEN - length of sub-block - 0 - 9 - read-write - - - - - DEC_CTRL1 - Decision Control Register 1 - 0xc - 32 - 0x00000000 - 0x003FFFFF - - - ZCR_HIGH - ZCR high limit - 11 - 11 - read-write - - - ZCR_LOW - ZCR low limit - 0 - 11 - read-write - - - - - DEC_CTRL2 - Decision Control Register 2 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - AMP_HIGH - amplitude high limit - 16 - 16 - read-write - - - AMP_LOW - amplitude low limit - 0 - 16 - read-write - - - - - ST - Status - 0x18 - 32 - 0x00000000 - 0x000000FF - - - VAD - VAD event found - 7 - 1 - write-only - - - OFIFO_AV - OFIFO data available - 6 - 1 - read-only - - - MEMBUF_EMPTY - Buf empty - 5 - 1 - write-only - - - OFIFO_OVFL - OFIFO overflow - 4 - 1 - write-only - - - IIR_OVLD - IIR overloading - 3 - 1 - write-only - - - IIR_OVFL - IIR oberflow - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation - 0 - 1 - write-only - - - - - OFIFO - Out FIFO - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - D - The PCM data. -When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). -When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - 0 - 32 - read-write - - - - - RUN - Run Command Register - 0x20 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - software reset. Self-clear - 1 - 1 - read-write - - - VAD_EN - module enable - 0 - 1 - read-write - - - - - OFIFO_CTRL - Out FIFO Control Register - 0x24 - 32 - 0x00000000 - 0x00000001 - - - EN - Asserted to enable OFIFO - 0 - 1 - read-write - - - - - CIC_CFG - CIC Configuration Register - 0x28 - 32 - 0x00000000 - 0x0000FC00 - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - - - 1 - 0x4 - STE_ACT - COEF[%s] - no description available - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - The current detected short time energy - 0 - 32 - read-only - - - - - - - MIPI_DSI_PHY0 - MIPI_DSI_PHY0 - MIPI_DSI_PHY - 0xf4140000 - - 0x0 - 0x94 - registers - - - - clane_para0 - timer counter about clock lane parameter - 0x0 - 32 - 0x00000050 - 0x0000FFFF - - - T_RST2ENLPTX_C - the soft reset of clk_cfg domain - 0 - 16 - read-write - - - - - clane_para1 - timer counter about clock lane parameter - 0x4 - 32 - 0x00000100 - 0xFFFFFFFF - - - T_INITTIME_C - the number of byteclk cycles that clklane drive LP-11 during initialization period - 0 - 32 - read-write - - - - - clane_para2 - timer counter about clock lane parameter - 0x8 - 32 - 0x00808080 - 0x00FFFFFF - - - T_CLKPREPARE_C - the number of byteclk cycles that clock lane clkp/n lines are at the hs prepare state lp-00 during a hs clock transmission - 16 - 8 - read-write - - - T_CLKZERO_C - the number of byteclk cycles that clock lane clkp/n lines are at the hs-zero state hs-0 during a hs clock transmission - 8 - 8 - read-write - - - T_CLKPRE_C - the number of byteclk cycles that hs clock shall be driven prior to data lane beginning the transition from lp to hs mode - 0 - 8 - read-write - - - - - clane_para3 - timer counter about clock lane parameter - 0xc - 32 - 0x00808080 - 0x00FFFFFF - - - T_CLKPOST_C - the number of byteclk cycles that the clock lane should keep sending the hs-clock after the last associated data lane has transitioned to LP mode. - 16 - 8 - read-write - - - T_CLKTRIAL_C - the number of byteclk cycles that the clock lane clkp/n lines are at state hs-tail sate hs-0 during a hs clock transmission - 8 - 8 - read-write - - - T_HSEXIT_C - the number of byteclk cycles that the clock lane clkp/n lines are at hs-exit state after a hs clock transmission - 0 - 8 - read-write - - - - - dlane0_para0 - timer counter about datalane0 parameter - 0x10 - 32 - 0x00000050 - 0x0000FFFF - - - T_RST2ENLPTX_D0 - the number of byteclk cycles that datalane0 wait to enable lptx_en after reset release - 0 - 16 - read-write - - - - - dlane0_para1 - timer counter about datalane0 parameter - 0x14 - 32 - 0x00000014 - 0xFFFFFFFF - - - T_INITTIME_D0 - the number of byteclk cycles that datalane0 drive lp-11 during initiaalization period - 0 - 32 - read-write - - - - - dlane0_para2 - timer counter about datalane0 parameter - 0x18 - 32 - 0x80808080 - 0xFFFFFFFF - - - T_HSPREPARE_D0 - the number of byteclk cycles that the datalane0 stay at hs prepare state lp-00 during a hs transmission - 24 - 8 - read-write - - - T_HSZERO_D0 - the number of byteclk cycles that the datalane0 stay at hs-zero sate during a hs transmission - 16 - 8 - read-write - - - T_HSTRAIL_D0 - the number of byteclk cycles that the datalane0 stay at hs-trail state during a hs clock transmission - 8 - 8 - read-write - - - T_HSEXIT_D0 - the number of byteclk cycles that the datalane0 stay at state hs-exit sate after a hs clock transmission - 0 - 8 - read-write - - - - - dlane0_para3 - timer counter about datalane0 parameter - 0x1c - 32 - 0x00000100 - 0xFFFFFFFF - - - T_WAKEUP_D0 - the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - 0 - 32 - read-write - - - - - dlane0_para4 - timer counter about datalane0 parameter - 0x20 - 32 - 0x00808080 - 0x00FFFFFF - - - T_TAGO_D0 - the number of byteclk cycles that the tx drives the bridge state during a turnaroud procedure - 16 - 8 - read-write - - - T_TASURE_D0 - the number of byteclk cycles that the rx waits after a bridge state has been detected during a turnaround procedure - 8 - 8 - read-write - - - T_TAGET_D0 - the number of byteclk cycles that the new transmitter drivers the bridge state after accepting control during bta - 0 - 8 - read-write - - - - - dlane1_para0 - timer counter about datalane1 parameter - 0x24 - 32 - 0x00000050 - 0x0000FFFF - - - T_RST2ENLPTX_D1 - the number of byteclk cycles that datalane1 wait to enable lptx_en after reset release - 0 - 16 - read-write - - - - - dlane1_para1 - timer counter about datalane1 parameter - 0x28 - 32 - 0x00000014 - 0xFFFFFFFF - - - T_INITTIME_D1 - the number of byteclk cycles that datalane1 drive lp-11 during initiaalization period - 0 - 32 - read-write - - - - - dlane1_para2 - timer counter about datalane1 parameter - 0x2c - 32 - 0x80808080 - 0xFFFFFFFF - - - T_HSPREPARE_D1 - the number of byteclk cycles that the datalane1 stay at hs prepare state lp-00 during a hs transmission - 24 - 8 - read-write - - - T_HSZERO_D1 - the number of byteclk cycles that the datalane1 stay at hs-zero sate during a hs transmission - 16 - 8 - read-write - - - T_HSTRAIL_D1 - the number of byteclk cycles that the datalane1 stay at hs-trail state during a hs clock transmission - 8 - 8 - read-write - - - T_HSEXIT_D1 - the number of byteclk cycles that the datalane1 stay at state hs-exit sate after a hs clock transmission - 0 - 8 - read-write - - - - - dlane1_para3 - timer counter about datalane1 parameter - 0x30 - 32 - 0x00000100 - 0xFFFFFFFF - - - T_WAKEUP_D1 - the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - 0 - 32 - read-write - - - - - dlane2_para0 - timer counter about datalane2 parameter - 0x34 - 32 - 0x00000050 - 0x0000FFFF - - - T_RST2ENLPTX_D2 - the number of byteclk cycles that datalane2 wait to enable lptx_en after reset release - 0 - 16 - read-write - - - - - dlane2_para1 - timer counter about datalane2 parameter - 0x38 - 32 - 0x00000014 - 0xFFFFFFFF - - - T_INITTIME_D2 - the number of byteclk cycles that datalane2 drive lp-11 during initiaalization period - 0 - 32 - read-write - - - - - dlane2_para2 - timer counter about datalane2 parameter - 0x3c - 32 - 0x80808080 - 0xFFFFFFFF - - - T_HSPREPARE_D2 - the number of byteclk cycles that the datalane2 stay at hs prepare state lp-00 during a hs transmission - 24 - 8 - read-write - - - T_HSZERO_D2 - the number of byteclk cycles that the datalane2 stay at hs-zero sate during a hs transmission - 16 - 8 - read-write - - - T_HSTRAIL_D2 - the number of byteclk cycles that the datalane2 stay at hs-trail state during a hs clock transmission - 8 - 8 - read-write - - - T_HSEXIT_D2 - the number of byteclk cycles that the datalane2 stay at state hs-exit sate after a hs clock transmission - 0 - 8 - read-write - - - - - dlane2_para3 - timer counter about datalane2 parameter - 0x40 - 32 - 0x00000100 - 0xFFFFFFFF - - - T_WAKEUP_D2 - the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - 0 - 32 - read-write - - - - - dlane3_para0 - timer counter about datalane3 parameter - 0x44 - 32 - 0x00000050 - 0x0000FFFF - - - T_RST2ENLPTX_D3 - the number of byteclk cycles that datalane3 wait to enable lptx_en after reset release - 0 - 16 - read-write - - - - - dlane3_para1 - timer counter about datalane3 parameter - 0x48 - 32 - 0x00000014 - 0xFFFFFFFF - - - T_INITTIME_D3 - the number of byteclk cycles that datalane3 drive lp-11 during initiaalization period - 0 - 32 - read-write - - - - - dlane3_para2 - timer counter about datalane3 parameter - 0x4c - 32 - 0x80808080 - 0xFFFFFFFF - - - T_HSPREPARE_D3 - the number of byteclk cycles that the datalane3 stay at hs prepare state lp-00 during a hs transmission - 24 - 8 - read-write - - - T_HSZERO_D3 - the number of byteclk cycles that the datalane3 stay at hs-zero sate during a hs transmission - 16 - 8 - read-write - - - T_HSTRAIL_D3 - the number of byteclk cycles that the datalane3 stay at hs-trail state during a hs clock transmission - 8 - 8 - read-write - - - T_HSEXIT_D3 - the number of byteclk cycles that the datalane3 stay at state hs-exit sate after a hs clock transmission - 0 - 8 - read-write - - - - - dlane3_para3 - timer counter about datalane3 parameter - 0x50 - 32 - 0x00000100 - 0xFFFFFFFF - - - T_WAKEUP_D3 - the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - 0 - 32 - read-write - - - - - common_para0 - timing parameter for all lanes - 0x54 - 32 - 0x00000014 - 0x000000FF - - - T_LPX - the number of byteclk cycles of transmitted length of any low-power state period - 0 - 8 - read-write - - - - - ctrl_para0 - dphy control parameter - 0x58 - 32 - 0x000000E0 - 0x000000FF - - - VBG_RDY - the indicator signal of reference generator is ready - 7 - 1 - read-only - - - EN_ULPRX_D0 - ulp-rx enable for lane0 - 6 - 1 - read-write - - - EN_LPRX_D0 - lp-rx enable for lane0 - 5 - 1 - read-write - - - EN_LPCD_D0 - lp-cd enable for lane0 - 4 - 1 - read-write - - - PWON_SEL - select the cource of PMA power on control signals - 3 - 1 - read-write - - - PWON_PLL - power on pll high active - 2 - 1 - read-write - - - PWON_DSI - power on all dsi lane - 1 - 1 - read-write - - - SU_IDDQ_EN - power down all modules inside su includes ivref, r-calibration and pll, high effective - 0 - 1 - read-write - - - - - pll_ctrl_para0 - dphy pll control parameter - 0x5c - 32 - 0x01029AB6 - 0x0FFFFFFF - - - PLL_LOCK - pll lock indication - 27 - 1 - read-only - - - RATE - data reate control signal - 24 - 3 - read-write - - - REFCLK_DIV - input reference clock divider ratio control - 19 - 5 - read-write - - - PLL_DIV - pll loop divider ratio control - 4 - 15 - read-write - - - DSI_PIXELCLK_DIV - pixell clock divided from pll output - 0 - 4 - read-write - - - - - rcal_ctrl - dphy calibration control parameter - 0x64 - 32 - 0x00002E00 - 0x00003FFF - - - RCAL_EN - enable hs-tx output impedance trimming - 13 - 1 - read-write - - - RCAL_TRIM - default value of hs-tx output resistance configure - 9 - 4 - read-write - - - RCAL_CTRL - resistor calibration control, reserved for test - 1 - 8 - read-write - - - RCAL_DONE - hs-tx output impedance trimming done indicator signal - 0 - 1 - read-only - - - - - trim_para - dphy trimming parameter - 0x68 - 32 - 0x00003322 - 0x00003FFF - - - HSTX_AMP_TRIM - hs-tx output vod trimming for lane-0~4 - 11 - 3 - read-write - - - LPTX_SR_TRIM - lp-tx output slew-rate trimming for lane0~4 - 8 - 3 - read-write - - - LPRX_VREF_TRIM - lp-rx input threshold voltage trimming for lane0 - 4 - 4 - read-write - - - LPCD_VREF_TRIM - lp-cd input threshold voltage trimming for lane0 - 0 - 4 - read-write - - - - - test_para0 - dphy test control parameter - 0x6c - 32 - 0x00000000 - 0x007FFFFF - - - ERROR_NUM - the byte num of mismatch data of lane in bist mode - 17 - 6 - read-only - - - BIST_N_DONE - indicate prbs7 bist test is done - 12 - 5 - read-only - - - BIST_N_OK - indicate prbs7 bist test is ok - 7 - 5 - read-only - - - ATEST_EN - analog test signal enable - 6 - 1 - read-write - - - ATEST_SEL - analog test signal select - 4 - 2 - read-write - - - FSET_EN - enable fast transmission between lp-tx and hs-tx - 3 - 1 - read-write - - - FT_SEL - pt/ft test mode select - 0 - 3 - read-write - - - - - test_para1 - dphy bist test control parameter - 0x70 - 32 - 0x009C40C0 - 0xFFFFFFFF - - - CHECK_NUM - the byte num of prbs bist check num - 10 - 22 - read-write - - - ERR_THRESHOLD - the threshold of prbs bit error - 6 - 4 - read-write - - - BIST_BIT_ERROR - enable insert error in bist test pattern - 5 - 1 - read-write - - - BIST_EN - bist enable - 3 - 2 - read-write - - - BIST_SEL - bist mode select - 2 - 1 - read-write - - - PRBS_SEL - prbs generator and checker pattern select signal - 0 - 2 - read-write - - - - - misc_para - dphy control parameter - 0x74 - 32 - 0x0000007F - 0x000007FF - - - DLL_SEL - the phase select of clk_rxesc - 7 - 4 - read-write - - - LANE_NUM - the number of active data lanes - 5 - 2 - read-write - - - PHYERR_MASK - mask the phy error - 0 - 5 - read-write - - - - - clane_para4 - dphy clock lane control parameter - 0x78 - 32 - 0x00000100 - 0xFFFFFFFF - - - T_WAKEUP_C - the number of byteclk cycles from exiting ultra low power state to enabling the low-power driver - 0 - 32 - read-write - - - - - interface_para - dphy clock lane control parameter - 0x7c - 32 - 0x00000301 - 0x0000FFFF - - - TXREADYESC_EXTEND_VLD - the extend length of txreadyesc - 8 - 8 - read-write - - - RXVALIDESC_EXTEND_VLD - the extend length of rxvalidesc - 0 - 8 - read-write - - - - - pcs_reserved_pin_para - reserved the pins for pcs - 0x80 - 32 - 0x00000000 - 0x0000001F - - - CLK_TXHS_SEL_INNER - select the clock source of clk_txhs in pcs - 4 - 1 - read-write - - - INV_CLK_TXHS - clk_txhs inverter signal - 3 - 1 - read-write - - - INV_CLK_TXESC - clk_txesc inverter signal - 2 - 1 - read-write - - - INV_PCLK - pclk inverter signal - 1 - 1 - read-write - - - INV_DSI_RCLK - pma clock dsi_rclk_i inverter signal - 0 - 1 - read-write - - - - - clane_data_para - parallel data about clock lane parameter - 0x8c - 32 - 0x000000AA - 0x000001FF - - - CLANE_DATA_SEL - select the data about clock lane - 8 - 1 - read-write - - - CLANE_DATA - the parallel data about clock lane - 0 - 8 - read-write - - - - - pma_lane_sel_para - pma about clock lane select parameter - 0x90 - 32 - 0x0000000D - 0x0000000F - - - PMA_DLANE4_SEL - select the channel 4 as the data lane - 3 - 1 - read-write - - - PMA_DLANE3_SEL - select the channel 3 as the data lane - 2 - 1 - read-write - - - PMA_DLANE2_SEL - select the channel 2 as the data lane - 1 - 1 - read-write - - - PMA_DLANE1_SEL - select the channel 1 as the data lane - 0 - 1 - read-write - - - - - - - MIPI_DSI_PHY1 - MIPI_DSI_PHY1 - MIPI_DSI_PHY - 0xf4144000 - - - MIPI_CSI_PHY0 - MIPI_CSI_PHY0 - MIPI_CSI_PHY - 0xf4148000 - - 0x0 - 0xd28 - registers - - - - soft_rst - soft reset control - 0x0 - 32 - 0x00000000 - 0x00000003 - - - HS_CLK_SOFT_RST - the soft reset of clk_hs domain - 1 - 1 - read-write - - - CFG_CLK_SOFT_RST - the soft reset of clk_cfg domain - 0 - 1 - read-write - - - - - phy_rcal - dphy resistor calibration - 0x4 - 32 - 0x0000E00F - 0x0003FFFF - - - RCAL_DONE - hs-rx terminal trimming done indicator signal - 17 - 1 - read-only - - - RCAL_OUT - hs-rx terminal trimming results - 13 - 4 - read-only - - - RCAL_CTL - rcal function control - 5 - 8 - read-write - - - RCAL_TRIM - default value of HS-RX terminal configure - 1 - 4 - read-write - - - RCAL_EN - enable hs-rx terminal trimming - 0 - 1 - read-write - - - - - ulp_rx_en - enable lprx and ulprx - 0x8 - 32 - 0x000000E3 - 0x000000E3 - - - CSI_1_ULPRX_EN - data lane1 ulp-rx receiver enable control - 7 - 1 - read-write - - - CSI_0_ULPRX_EN - data lane0 ulp-rx receiver enable control - 6 - 1 - read-write - - - CSI_CLK_ULPRX_EN - clock lane ulp-rx receiver enable control - 5 - 1 - read-write - - - CSI_1_LPRX_EN - data lane1 lp-rx receiver enable control - 1 - 1 - read-write - - - CSI_CLK_LPRX_EN - clock lane lp=rx receiver enable control - 0 - 1 - read-write - - - - - voffcal_out - hs-rx dc-offset auto-calibration results - 0xc - 32 - 0x00000000 - 0x3FFFF000 - - - CSI_CLK_VOFFCAL_DONE - clock lane hs-rx dc-offset auto-calibration done - 29 - 1 - read-only - - - CSI_CLK_VOFFCAL_OUT - clock lane hs-rx dc-offset auto-calibration results - 24 - 5 - read-only - - - CSI_0_VOFFCAL_DONE - data lane0 hs-rx dc-offset auto-calibration done - 23 - 1 - read-only - - - CSI_O_VOFFCAL_OUT - data lane0 hs-rx dc-offset auto-calibration result - 18 - 5 - read-only - - - CSI_1_VOFFCAL_DONE - data lane1 hs-rx dc-offset auto-calibration done - 17 - 1 - read-only - - - CSI_1_VOFFCAL_OUT - data lane1 hs-rx dc-offset auto-calibration result - 12 - 5 - read-only - - - - - csi_ctl01 - dphy hardcore control - 0x10 - 32 - 0x00000000 - 0x3F7F3F7F - - - CSI_CTL1_7 - clock lane hs-rx dc-offset auto-calibration enable - 29 - 1 - read-write - - - CSI_CTL1_6 - clock lane hs-rx dc-offset trimming control - 24 - 5 - read-write - - - CSI_CTL1_5 - ulprx_vref_trim - 21 - 2 - read-write - - - CSI_CTL1_4 - bypass hs_rx_voffcal_en - 20 - 1 - read-write - - - CSI_CTL1_3 - hs_rx_voffcal_trim_polar - 19 - 1 - read-write - - - CSI_CTL1_2 - ulprx_lpen - 18 - 1 - read-write - - - CSI_CTL1_1 - force data lane-n and clock lane lp/ulprx to be normal operation - 17 - 1 - read-write - - - CSI_CTL1_0 - force data lane-n and clock lane hs-rx to be normal operation - 16 - 1 - read-write - - - CSI_CTL0_7 - clock lane hs-rx dc-offset auto-calibration enable - 13 - 1 - read-write - - - CSI_CTL0_6 - clock lane hs-rx dc-offset trimming control - 8 - 5 - read-write - - - CSI_CTL0_5 - ulprx_vref_trim - 5 - 2 - read-write - - - CSI_CTL0_4 - bypass hs_rx_voffcal_en - 4 - 1 - read-write - - - CSI_CTL0_3 - hs_rx_voffcal_trim_polar - 3 - 1 - read-write - - - CSI_CTL0_2 - ulprx_lpen - 2 - 1 - read-write - - - CSI_CTL0_1 - force data lane-n and clock lane lp/ulprx to be normal operation - 1 - 1 - read-write - - - CSI_CTL0_0 - force data lane-n and clock lane hs-rx to be normal operation - 0 - 1 - read-write - - - - - csi_ctl23 - dphy hardcore control - 0x14 - 32 - 0x00000000 - 0x1F1F0000 - - - CSI_CTL3_3 - data lane-1 skew trimming enable - 28 - 1 - read-write - - - CSI_CTL3_2 - data lane-1 hs-rx skew adjust with binary code - 24 - 4 - read-write - - - CSI_CTL3_1 - data lane-0 skew trimming enable - 20 - 1 - read-write - - - CSI_CTL3_0 - data lane-0 hs-rx skew adjust with binary code - 16 - 4 - read-write - - - - - csi_vinit - ulp lp-rx input threshold voltage trimming for data lane - 0x1c - 32 - 0x00200000 - 0x00FF00FF - - - CSI_LPRX_VREF_TRIM - pt ft indicator in csi clk data lane - 20 - 4 - read-write - - - CSI_CLK_LPRX_VINT - pt ft indicator in csi clk lane - 16 - 4 - read-only - - - CSI_1_LPRX_VINIT - pt ft indicator in csi lane-1 - 4 - 4 - read-only - - - CSI_0_LPRX_VINIT - pt ft indicator in csi lane-0 - 0 - 4 - read-only - - - - - clane_para - clock lane parameter - 0x20 - 32 - 0x00000314 - 0x0000FFFF - - - T_CLK_TERMEN - time for the clock lane receiver to enable the HS line termination - 8 - 8 - read-write - - - T_CLK_SETTLE - the value of tclk-settle of clklane - 0 - 8 - read-write - - - - - t_hs_termen - t-termen of all datalane - 0x24 - 32 - 0x00000303 - 0x0000FFFF - - - T_D1_TERMEN - the value of ths-termen of datalane1 - 8 - 8 - read-write - - - T_D0_TERMEN - the value of ths-termen of datalane0 - 0 - 8 - read-write - - - - - t_hs_settle - t-settle of all data lanes - 0x28 - 32 - 0x00000A0A - 0x0000FFFF - - - T_D1_SETTLE - the value of ths-settle of data lane1 - 8 - 8 - read-write - - - T_D0_SETTLE - the value of ths-settle of data lane0 - 0 - 8 - read-write - - - - - t_clane_init - t-init of clock lane - 0x30 - 32 - 0x00007530 - 0x00FFFFFF - - - T_CLK_INIT - initialization time of lock lane - 0 - 24 - read-write - - - - - t_lane_init0 - t-init of data lane0 - 0x34 - 32 - 0x00007530 - 0x00FFFFFF - - - T_D0_INIT - initialization time of data lane - 0 - 24 - read-write - - - - - t_lane_init1 - t-init of data lane1 - 0x38 - 32 - 0x00007530 - 0x00FFFFFF - - - T_D1_INIT - initialization time of data lane - 0 - 24 - read-write - - - - - tlpx_ctrl - the time of tlpx_ctrl of all lane - 0x44 - 32 - 0x00000002 - 0x000001FF - - - EN_TLPX_CHECK - enable the tlpx width check - 8 - 1 - read-write - - - TLPX - the width of tlpx - 0 - 8 - read-write - - - - - ne_swap - lane swap and dp/dn swap select - 0x48 - 32 - 0x00000004 - 0x0000030F - - - DPDN_SWAP_LANE1 - datalane1 dpdn swap - 9 - 1 - read-write - - - DPDN_SWAP_LAN0 - datalane0 dpdn swap - 8 - 1 - read-write - - - LANE_SWAP_LAN1 - data lane1 swap - 2 - 2 - read-write - - - LANE_SWAP_LANE0 - data lane0 swap - 0 - 2 - read-write - - - - - misc_info - misc info of dphyrx_pcs control - 0x4c - 32 - 0x00000000 - 0x00000003 - - - ULPS_LP10_SEL - the lp10 select signal in ulps_exit state - 1 - 1 - read-write - - - LONG_SOTSYNC_EN - at least six zero is checked before sot swquence "00011101" - 0 - 1 - read-write - - - - - bist_test0 - bist test control - 0x70 - 32 - 0x00000000 - 0x000000CF - - - BIST_DONE_LAN1 - bist_done of lane1 - 7 - 1 - read-only - - - BIST_DONE_LAN0 - bist_done of lane0 - 6 - 1 - read-only - - - BIST_OK_LANE1 - bist_ok of lane1 - 3 - 1 - read-only - - - BIST_OK_LANE0 - bist_ok of lane0 - 2 - 1 - read-only - - - BIST_EN_SEL - the source of bist_en sel - 1 - 1 - read-write - - - BIST_EN_SOFT - enable prbs bist test - 0 - 1 - read-write - - - - - bist_test1 - bist test control - 0x74 - 32 - 0x00000100 - 0xFFFFFFFF - - - PRBS_CHECK_NUM - the byte num of prbs bist check num - 0 - 32 - read-write - - - - - bist_test2 - bist test control - 0x78 - 32 - 0x007F0005 - 0x00FFFFFF - - - PRBS_SEED - the seed of prbs7 - 16 - 8 - read-write - - - PRBS_ERR_THRESHOLD - the threshold of prbs bist error - 0 - 16 - read-write - - - - - bist_test3 - bist test control - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - PRBS_ERR_NUM_LAN1 - the byte num of mismatch data of data lane1 in bist mode - 16 - 16 - read-only - - - PRBS_ERR_NUM_LAN0 - the byte num of mismatch data of data lane0 in bist mode - 0 - 16 - read-only - - - - - burn_in_test0 - burn-in test control - 0xa0 - 32 - 0x00000000 - 0x0000004F - - - BURN_IN_OK_CLAN - burn_in_ok of clock lane - 6 - 1 - read-only - - - BURN_IN_OK_LAN1 - burn_in_ok of lane1 - 3 - 1 - read-only - - - BURN_IN_OK_LAN0 - burn_in_ok of lane0 - 2 - 1 - read-only - - - BURN_IN_EN_SEL - the source of prbs burn_in_en sel - 1 - 1 - read-write - - - BURN_IN_EN_SOFT - enable prbs burn_in test - 0 - 1 - read-write - - - - - burn_in_test1 - burn-in test control - 0xa4 - 32 - 0x00000000 - 0x000000FF - - - BURN_IN_SEED - the seed of prbs7 for brun-in test - 0 - 8 - read-write - - - - - burn_in_test2 - bist test control - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BURN_IN_ERR_NUM_LAN1 - the bit num of mismatch data on data lan1 in burn-in mode - 16 - 16 - read-only - - - BURN_IN_ERR_NUM_LAN0 - the bit num of mismatch data on data lan0 in burn-in mode - 0 - 16 - read-only - - - - - burn_in_test4 - bist test control - 0xb0 - 32 - 0x00000000 - 0x0000FFFF - - - BURN_IN_ERR_NUM_CLAN - the bit num of mismatch data on clock lane in burn-in mode - 0 - 16 - read-only - - - - - burn_in_test5 - burn-in test control - 0xb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BURN_IN_CHECK_NUM_LAN0 - the checked bit num of lane0 - 0 - 32 - read-only - - - - - burn_in_test6 - burn-in test control - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - BURN_IN_CHECKED_NUM_LAN1 - the checked bit num of lane1 - 0 - 32 - read-only - - - - - burn_in_test9 - burn-in test control - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - BURN_IN_CHECK_NUM_CLAN - the checked bit num of clock lane - 0 - 32 - read-only - - - - - debug_info - debug data control - 0xd0 - 32 - 0x00000000 - 0x003F0000 - - - DEBUG_MODE_SEL - the debug bus sel - 16 - 6 - read-write - - - - - debug_cfg_reg0 - the hardcore interface control in debug mode - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_CFG_REG0 - debug config register0 - 0 - 32 - read-write - - - - - debug_cfg_reg1 - the hardcore interface control in debug mode - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_CFG_REG1 - debug config register1 - 0 - 32 - read-write - - - - - debug_cfg_reg2 - the hardcore interface control in debug mode - 0xd12 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_CFG_REG2 - debug config register2 - 0 - 32 - read-write - - - - - debug_cfg_reg3 - the hardcore interface control in debug mode - 0xd16 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_CFG_REG3 - debug config register3 - 0 - 32 - read-write - - - - - debug_cfg_reg4 - the hardcore interface control in debug mode - 0xd20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_CFG_REG4 - debug config register4 - 0 - 32 - read-write - - - - - debug_cfg_reg5 - the hardcore interface control in debug mode - 0xd24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DEBUG_CFG_REG5 - debug config register5 - 0 - 32 - read-write - - - - - - - MIPI_CSI_PHY1 - MIPI_CSI_PHY1 - MIPI_CSI_PHY - 0xf414c000 - - - DDRPHY - DDRPHY - DDRPHY - 0xf4150000 - - 0x0 - 0x400 - registers - - - - RIDR - Revision Identification Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - UDRID - User-Defined Revision ID: General purpose revision identification set by the user. - 24 - 8 - read-only - - - PHYMJR - PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions. - 20 - 4 - read-only - - - PHYMDR - PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions. - 16 - 4 - read-only - - - PHYMNR - PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included. - 12 - 4 - read-only - - - PUBMJR - PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions. - 8 - 4 - read-only - - - PUBMDR - PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions. - 4 - 4 - read-only - - - PUBMNR - PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included. - 0 - 4 - read-only - - - - - PIR - PHY Initialization Register (PIR) - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - INITBYP - Initialization Bypass: Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training. -Initialization may be triggered manually using INIT and the other relevant bits of the PIR register. This bit is self-clearing. - 31 - 1 - read-write - - - ZCALBYP - Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing. - 30 - 1 - read-write - - - DCALBYP - Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops, if set, DDL calibration that automatically triggers after reset. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit is self- clearing. - 29 - 1 - read-write - - - LOCKBYP - PLL Lock Bypass: Bypasses or stops, if set, the waiting of PLLs to lock. PLL lock wait is automatically triggered after reset. PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register. This bit is self-clearing. - 28 - 1 - read-write - - - CLRSR - Clear Status Registers: Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0. -This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1’b1) automatically clears the PGSR status bits associated with the initialization steps enabled. -The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1’b1 and which bits are not cleared: -The following bits are not cleared by PIR[27] (CLRSR): -PGSR0[31] (APLOCK) -PGSR0[29:28] (PLDONE_CHN) -PGSR0[23] (WLAERR) -PGSR0[21] (WLERR) -PGSR0[4] (DIDONE) -PGSR0[2] (DCDONE) -PGSR0[1] (PLDONE) -PGSR0[0] (IDONE) -The following bits are always zero: -PGSR0[30] (reserved) -PGSR0[19:12] (reserved) -The following bits are cleared unconditionally by PIR[27] (CLRSR): -PGSR0[27] (WEERR) -PGSR0[26] (REERR) -PGSR0[25] (WDERR) -PGSR0[24] (RDERR) -- PGSR0[22] (QSGERR) -- PGSR0[20] (ZCERR) -- PGSR0[11] (WEDONE) -- PGSR0[10] (REDONE) -- PGSR0[9] (WDDONE) -- PGSR0[8] (RDDONE) -- PGSR0[7] (WLADONE) -- PGSR0[6] (QSGDONE) -- PGSR0[5] (WLDONE) -- PGSR0[3] (ZCDONE) - 27 - 1 - read-write - - - RDIMMINIT - RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence. - 19 - 1 - read-write - - - CTLDINIT - Controller DRAM Initialization: Indicates, if set, that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. - 18 - 1 - read-write - - - PLLBYP - PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode. - 17 - 1 - read-write - - - ICPC - Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are: -0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete. -1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. - 16 - 1 - read-write - - - WREYE - Write Data Eye Training: Executes a PUB training routine to maximize the write data eye. - 15 - 1 - read-write - - - RDEYE - Read Data Eye Training: Executes a PUB training routine to maximize the read data eye. - 14 - 1 - read-write - - - WRDSKW - Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write. - 13 - 1 - read-write - - - RDDSKW - Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read. - 12 - 1 - read-write - - - WLADJ - Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency. -Note: Ensure that the DCU command cache is cleared prior to running WLADJ. - 11 - 1 - read-write - - - QSGATE - Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. - 10 - 1 - read-write - - - WL - Write Leveling (DDR3 Only): Executes a PUB write leveling routine. - 9 - 1 - read-write - - - DRAMINIT - DRAM Initialization: Executes the DRAM initialization sequence. - 8 - 1 - read-write - - - DRAMRST - DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence. - 7 - 1 - read-write - - - PHYRST - PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. - 6 - 1 - read-write - - - DCAL - Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration. - 5 - 1 - read-write - - - PLLINIT - PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. - 4 - 1 - read-write - - - ZCAL - Impedance Calibration: Performs PHY impedance calibration. When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset). - 1 - 1 - read-write - - - INIT - Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing. - 0 - 1 - read-write - - - - - PGCR0 - PHY General Configuration Registers 0-1 (PGCR0- 1) - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CKEN - CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the up to three CK pairs. Valid values for the two bits are: -00 = CK disabled (Driven to constant 0) 01 = CK toggling with inverted polarity -10 = CK toggling with normal polarity (This should be the default setting) 11 = CK disabled (Driven to constant 1) - 26 - 6 - read-write - - - PUBMODE - Enables, if set, the PUB to control the interface to the PHY and SDRAM. In this mode the DFI commands from the controller are ignored. The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller. When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training. - 25 - 1 - read-write - - - DTOSEL - Digital Test Output Select: Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are: -00000 = DATX8 0 PLL digital test output 00001 = DATX8 1 PLL digital test output 00010 = DATX8 2 PLL digital test output 00011 = DATX8 3 PLL digital test output 00100 = DATX8 4 PLL digital test output 00101 = DATX8 5 PLL digital test output 00110 = DATX8 6 PLL digital test output 00111 = DATX8 7 PLL digital test output 01000 = DATX8 8 PLL digital test output 01001 = AC PLL digital test output 01010 – 01111 = Reserved -10000 = DATX8 0 delay line digital test output 10001 = DATX8 1 delay line digital test output 10010 = DATX8 2 delay line digital test output 10011 = DATX8 3 delay line digital test output 10100 = DATX8 4 delay line digital test output 10101 = DATX8 5 delay line digital test output 10110 = DATX8 6 delay line digital test output 10111 = DATX8 7 delay line digital test output 11000 = DATX8 8 delay line digital test output 11001 = AC delay line digital test output 11010 – 11111 = Reserved - 14 - 5 - read-write - - - OSCWDL - Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: -00 = No WL LCDL is active 01 = DDR WL LCDL is active 10 = SDR WL LCDL is active 11 = Both LCDLs are active - 12 - 2 - read-write - - - OSCDIV - Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: -000 = Divide by 1 -001 = Divide by 256 -010 = Divide by 512 -011 = Divide by 1024 -100 = Divide by 2048 -101 = Divide by 4096 -110 = Divide by 8192 -111 = Divide by 65536 - 9 - 3 - read-write - - - OSCEN - Oscillator Enable: Enables, if set, the delay line oscillation. - 8 - 1 - read-write - - - DLTST - Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered. - 7 - 1 - read-write - - - DLTMODE - Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Setting this bit also clears all delay line register values. For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings. - 6 - 1 - read-write - - - RDBVT - Read Data BDL VT Compensation: Enables, if set, the VT drift compensation of the read data bit delay lines. - 5 - 1 - read-write - - - WDBVT - Write Data BDL VT Compensation: Enables, if set, the VT drift compensation of the write data bit delay lines. - 4 - 1 - read-write - - - RGLVT - Read DQS Gating LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS gating LCDL. - 3 - 1 - read-write - - - RDLVT - Read DQS LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS LCDL. - 2 - 1 - read-write - - - WDLVT - Write DQ LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write DQ LCDL. - 1 - 1 - read-write - - - WLLVT - Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL. - 0 - 1 - read-write - - - - - PGCR1 - PHY General Configuration Registers 0-1 (PGCR0- 1) - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LBMODE - Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode. - 31 - 1 - read-write - - - LBGDQS - Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are: -00 = DQS gate is always on -01 = DQS gate training will be triggered on the PUB 10 = DQS gate is set manually using software -11 = Reserved - 29 - 2 - read-write - - - LBDQSS - Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: -1b0 = PUB sets the read DQS LCDL to 0 (internally). DQS is already shifted 90 degrees by write path -1b1 = The read DQS shift is set manually through software - 28 - 1 - read-write - - - IOLB - I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: -0 = Loopback is after output buffer; output enable must be asserted 1 = Loopback is before output buffer; output enable is don’t care - 27 - 1 - read-write - - - INHVT - VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will inhibit the VT calculation. This bit should be set to 1 during writes to the delay line registers. - 26 - 1 - read-write - - - DXHRST - DX PHY High-Speed Reset: a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. - 25 - 1 - read-write - - - ZCKSEL - Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM. -Valid values are: -00 = Divide by 2 -01 = Divide by 8 -10 = Divide by 32 -11 = Divide by 64 -For more information, refer to “Impedance Calibration” on page 174. - 23 - 2 - read-write - - - DLDLMT - Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal. - 15 - 8 - read-write - - - FDEPTH - Filter Depth: Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged. Valid values are: -00 = 2 -01 = 4 -10 = 8 -11 = 16 - 13 - 2 - read-write - - - LPFDEPTH - Low-Pass Filter Depth: Specifies the number of measurements over which MDL period measurements are filtered. This determines the time constant of the low pass filter. Valid values are: -00 = 2 -01 = 4 -10 = 8 -11 = 16 - 11 - 2 - read-write - - - LPFEN - Low-Pass Filter Enable: Enables, if set, the low pass filtering of MDL period measurements. - 10 - 1 - read-write - - - MDLEN - Master Delay Line Enable: Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. - 9 - 1 - read-write - - - IODDRM - I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os. These bits connect to bits [2:1] of the IOM pin of the SSTL I/O. For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook. - 7 - 2 - read-write - - - WLSELT - Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines. Refer to the DDR PHY Databook for details of how the select type is used. Valid values are: -0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees 1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees - 6 - 1 - read-write - - - ACHRST - AC PHY High-Speed Reset: a Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. - 5 - 1 - read-write - - - WSLOPT - Write System Latency Optimization: controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible). -0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank -0x1 = Inserts a pipeline stage - 4 - 1 - read-write - - - WLSTEP - Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling. Valid values are: -0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value 1 = 1 step size - 2 - 1 - read-write - - - WLMODE - Write Leveling (Software) Mode: Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL. The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ. - 1 - 1 - read-write - - - PDDISDX - Power Down Disabled Byte: Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down. - 0 - 1 - read-write - - - - - PGSR0 - “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - APLOCK - AC PLL Lock: Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin. - 31 - 1 - read-only - - - PLDONE_CHN - PLL Lock Done per Channel: Indicates PLL locking has completed for each underlying channel. Bit 28 represents channel 0 while bit 29 represents channel 1. - 28 - 2 - read-only - - - WEERR - Write Eye Training Error: Indicates, if set, that there is an error in write eye training. - 27 - 1 - read-only - - - REERR - Read Data Eye Training Error: Indicates, if set, that there is an error in read eye training. - 26 - 1 - read-only - - - WDERR - Write Data Bit Deskew Error: Indicates, if set, that there is an error in write bit deskew. - 25 - 1 - read-only - - - RDERR - Read Data Bit Deskew Error: Indicates, if set, that there is an error in read bit deskew. - 24 - 1 - read-only - - - WLAERR - Write Data Leveling Adjustment Error: Indicates, if set, that there is an error in write leveling adjustment. - 23 - 1 - read-only - - - QSGERR - Read DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. - 22 - 1 - read-only - - - WLERR - Write Leveling Error: Indicates, if set, that there is an error in write leveling. - 21 - 1 - read-only - - - ZCERR - Impedance Calibration Error: Indicates, if set, that there is an error in impedance calibration. - 20 - 1 - read-only - - - WEDONE - Write Data Eye Training Done: Indicates, if set, that write eye training has completed. - 11 - 1 - read-only - - - REDONE - Read Data Eye Training Done: Indicates, if set, that read eye training has completed. - 10 - 1 - read-only - - - WDDONE - Write Data Bit Deskew Done: Indicates, if set, that write bit deskew has completed. - 9 - 1 - read-only - - - RDDONE - Read Data Bit Deskew Done: Indicates, if set, that read bit deskew has completed. - 8 - 1 - read-only - - - WLADONE - Write Leveling Adjustment Done: Indicates, if set, that write leveling adjustment has completed. - 7 - 1 - read-only - - - QSGDONE - Read DQS Gate Training Done: Indicates, if set, that DQS gate training has completed. - 6 - 1 - read-only - - - WLDONE - Write Leveling Done: Indicates, if set, that write leveling has completed. - 5 - 1 - read-only - - - DIDONE - DRAM Initialization Done: Indicates, if set, that DRAM initialization has completed. - 4 - 1 - read-only - - - ZCDONE - Impedance Calibration Done: Indicates, if set, that impedance calibration has completed. - 3 - 1 - read-only - - - DCDONE - Digital Delay Line (DDL) Calibration Done: Indicates, if set, that DDL calibration has completed. - 2 - 1 - read-only - - - PLDONE - PLL Lock Done: Indicates, if set, that PLL locking has completed. - 1 - 1 - read-only - - - IDONE - Initialization Done: Indicates, if set, that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed. - 0 - 1 - read-only - - - - - PGSR1 - “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PARERR - RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR. - 31 - 1 - read-only - - - VTSTOP - VT Stop: Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. - 30 - 1 - read-only - - - DLTCODE - Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. - 1 - 24 - read-only - - - DLTDONE - Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. - 0 - 1 - read-only - - - - - PLLCR - “PLL Control Register (PLLCR)” on page 91 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - BYP - PLL Bypass: Bypasses the PLL, if set, to 1. - 31 - 1 - read-write - - - PLLRST - PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the reset. - 30 - 1 - read-write - - - PLLPD - PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the power-down. - 29 - 1 - read-write - - - FRQSEL - PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that go up to 2133 Mbps are: -00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz 10 = Reserved -11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz -Valid values for PHYs that don’t go up to 2133 Mbps are: -00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250MHz to 400MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 300MHz 10 = Reserved -11 = Reserved - 18 - 2 - read-write - - - QPMODE - PLL Quadrature Phase Mode: Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY. - 17 - 1 - read-write - - - CPPC - Charge Pump Proportional Current Control - 13 - 4 - read-write - - - CPIC - Charge Pump Integrating Current Control - 11 - 2 - read-write - - - GSHIFT - Gear Shift: Enables, if set, rapid locking mode. - 10 - 1 - read-write - - - ATOEN - Analog Test Enable (ATOEN): Selects the analog test signal that is driven on the analog test output pin. Otherwise the analog test output is tri-stated. This allows analog test output pins from multiple PLLs to be connected together. Valid values are: -0000 = All PLL analog test signals are tri-stated 0001 = AC PLL analog test signal is driven out -0010 = DATX8 0 PLL analog test signal is driven out 0011 = DATX8 1 PLL analog test signal is driven out 0100 = DATX8 2 PLL analog test signal is driven out 0101 = DATX8 3 PLL analog test signal is driven out 0110 = DATX8 4 PLL analog test signal is driven out 0111 = DATX8 5 PLL analog test signal is driven out 1000 = DATX8 6 PLL analog test signal is driven out 1001 = DATX8 7 PLL analog test signal is driven out 1010 = DATX8 8 PLL analog test signal is driven out 1011 – 1111 = Reserved - 6 - 4 - read-write - - - ATC - Analog Test Control: Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato). Valid values are: -0000 = Reserved -0001 = vdd_ckin -0010 = vrfbf -0011 = vdd_cko -0100 = vp_cp -0101 = vpfil(vp) -0110 = Reserved -0111 = gd -1000 = vcntrl_atb -1001 = vref_atb -1010 = vpsf_atb -1011 – 1111 = Reserved - 2 - 4 - read-write - - - DTC - Digital Test Control: Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]). Valid values are: -00 = ‘0’ (Test output is disabled) 01 = PLL x1 clock (X1) -10 = PLL reference (input) clock (REF_CLK) 11 = PLL feedback clock (FB_X1) - 0 - 2 - read-write - - - - - PTR0 - PHY Timing Registers 0-4 (PTR0-4) - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TPLLPD - PLL Power-Down Time: Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us. - 21 - 11 - read-write - - - TPLLGS - PLL Gear Shift Time: Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us. - 6 - 15 - read-write - - - TPHYRST - PHY Reset Time: Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are from 1 to 63 (the value must be non-zero). - 0 - 6 - read-write - - - - - PTR1 - PHY Timing Registers 0-4 (PTR0-4) - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPLLLOCK - PLL Lock Time: Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. This must correspond to a value that is equal to or more than 100us. Default value corresponds to 100us. - 16 - 16 - read-write - - - TPLLRST - PLL Reset Time: Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted. -The setting must correspond to a value that is equal to, or greater than, 3us. - 0 - 13 - read-write - - - - - PTR2 - PHY Timing Registers 0-4 (PTR0-4) - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - TWLDLYS - Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. This allows the delay to settle. - 15 - 5 - read-write - - - TCALH - Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted). - 10 - 5 - read-write - - - TCALS - Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted). - 5 - 5 - read-write - - - TCALON - Calibration On Time: Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted). - 0 - 5 - read-write - - - - - PTR3 - PHY Timing Registers 0-4 (PTR0-4) - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDINIT1 - DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following: -DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns) -Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz. - 20 - 9 - read-write - - - TDINIT0 - DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following: -DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz. -During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times. However, this may cause a memory model error, due to a violation of the CKE setup sequence. This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model. - 0 - 20 - read-write - - - - - PTR4 - PHY Timing Registers 0-4 (PTR0-4) - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TDINIT3 - DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following: -DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz. - 18 - 10 - read-write - - - TDINIT2 - DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following: -DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz. - 0 - 18 - read-write - - - - - ACMDLR - “AC Master Delay Line Register (ACMDLR)” on page 96 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - MDLD - MDL Delay: Delay select for the LCDL for the Master Delay Line. - 16 - 8 - read-write - - - TPRD - Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. - 8 - 8 - read-write - - - IPRD - Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. - 0 - 8 - read-write - - - - - ACBDLR - “AC Bit Delay Line Register (ACBDLR)” on page 96 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACBD - Address/Command Bit Delay: Delay select for the BDLs on address and command signals. - 18 - 6 - read-write - - - CK2BD - CK2 Bit Delay: Delay select for the BDL on CK2. - 12 - 6 - read-write - - - CK1BD - CK1 Bit Delay: Delay select for the BDL on CK1. - 6 - 6 - read-write - - - CK0BD - CK0 Bit Delay: Delay select for the BDL on CK0. - 0 - 6 - read-write - - - - - ACIOCR - “AC I/O Configuration Register (ACIOCR)” on page 97 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACSR - Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins. - 30 - 2 - read-write - - - RSTIOM - SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. - 29 - 1 - read-write - - - RSTPDR - SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. - 28 - 1 - read-write - - - RSTPDD1 - SDRAM Reset Power Down Driver: Powers down, when set, the output driver on the I/O for SDRAM RST# pin. - 27 - 1 - read-write - - - RSTODT - SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. - 26 - 1 - read-write - - - RANKPDR - Rank Power Down Receiver: Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on. - 22 - 4 - read-write - - - CSPDD1 - CS# Power Down Driver: Powers down, when set, the output driver on the I/O for CS#[3:0] pins. CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on. CKE and ODT driver power down is controlled by DSGCR register. - 18 - 4 - read-write - - - RANKODT - Rank On-Die Termination: Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on. - 14 - 4 - read-write - - - CKPDR - CK Power Down Receiver: Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. - 11 - 3 - read-write - - - CKPDD1 - CK Power Down Driver: Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. - 8 - 3 - read-write - - - CKODT - CK On-Die Termination: Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. - 5 - 3 - read-write - - - ACPDR - AC Power Down Receiver: Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. - 4 - 1 - read-write - - - ACPDD1 - AC Power Down Driver: Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. - 3 - 1 - read-write - - - ACODT - Address/Command On-Die Termination: Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. - 2 - 1 - read-write - - - ACOE - Address/Command Output Enable: Enables, when set, the output driver on the I/O for all address and command pins. - 1 - 1 - read-write - - - ACIOM - Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins. This bit connects to bit -[0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O. - 0 - 1 - read-write - - - - - DXCCR - “DATX8 Common Configuration Register (DXCCR)” on page 99 - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - DDPDRCDO - Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up - 28 - 4 - read-write - - - DDPDDCDO - Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up - 24 - 4 - read-write - - - DYNDXPDR - Data Power Down Receiver: Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDR and DXnGCR.DXPDR are not set to 1. Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command. Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO). - 23 - 1 - read-write - - - DYNDXPDD1 - Dynamic Data Power Down Driver: Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDD and DXnGCR.DXPDD are not set to 1. Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command. Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO). - 22 - 1 - read-write - - - UDQIOM - Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins. - 21 - 1 - read-write - - - UDQPDR - Unused DQ Power Down Receiver: Powers down, when set, the input receiver on the I/O for unused DQ pins. - 20 - 1 - read-write - - - UDQPDD1 - Unused DQ Power Down Driver: Powers down, when set, the output driver on the I/O for unused DQ pins. - 19 - 1 - read-write - - - UDQODT - Unused DQ On-Die Termination: Enables, when set, the on-die termination on the I/O for unused DQ pins. - 18 - 1 - read-write - - - MSBUDQ - Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte. The used (valid) bits for this byte are [8-MSBDQ- 1:0]. To disable the whole byte, use the DXnGCR.DXEN register. - 15 - 3 - read-write - - - DXSR - Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. - 13 - 2 - read-write - - - DQSNRES - DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. -Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. - 9 - 4 - read-write - - - DQSRES - DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins. DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). DQSRES[2:0] selects the resistor value. -Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. - 5 - 4 - read-write - - - DXPDR - Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDR configuration bit of the individual DATX8. - 4 - 1 - read-write - - - DXPDD1 - Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8. - 3 - 1 - read-write - - - MDLEN - Master Delay Line Enable: Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the MDLEN bit in the individual DATX8. - 2 - 1 - read-write - - - DXIOM - Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8. - 1 - 1 - read-write - - - DXODT - Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8 (“DATX8 General Configuration Register (DXnGCR)” on page 148) - 0 - 1 - read-write - - - - - DSGCR - “DDR System General Configuration Register (DSGCR)” on page 101 - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CKEOE - SDRAM CKE Output Enable: Enables, when set, the output driver on the I/O for SDRAM CKE pins. - 31 - 1 - read-write - - - RSTOE - SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin. - 30 - 1 - read-write - - - ODTOE - SDRAM ODT Output Enable: Enables, when set, the output driver on the I/O for SDRAM ODT pins. - 29 - 1 - read-write - - - CKOE - SDRAM CK Output Enable: Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. - 28 - 1 - read-write - - - ODTPDD1 - ODT Power Down Driver: Powers down, when set, the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on. - 24 - 4 - read-write - - - CKEPDD1 - CKE Power Down Driver: Powers down, when set, the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on. - 20 - 4 - read-write - - - SDRMODE - Single Data Rate Mode: Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode. Otherwise if not set the controller is running in half data rate (HDR) mode. This bit not supported in the current version of the PUB. - 19 - 1 - read-write - - - RRMODE - Rise-to-Rise Mode: Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY mission mode is running in rise-to- fall mode. - 18 - 1 - read-write - - - ATOAE - ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O. - 17 - 1 - read-write - - - DTOOE - DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins. - 16 - 1 - read-write - - - DTOIOM - DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins. - 15 - 1 - read-write - - - DTOPDR - DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins. - 14 - 1 - read-write - - - DTOPDD1 - DTO Power Down Driver: Powers down, when set, the output driver on the I/O for DTO pins. - 13 - 1 - read-write - - - DTOODT - DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins. - 12 - 1 - read-write - - - PUAD - PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. - 8 - 4 - read-write - - - BRRMODE - Bypass Rise-to-Rise Mode: Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY bypass mode is running in rise-to-fall mode. - 7 - 1 - read-write - - - DQSGX - DQS Gate Extension: Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e. one clock cycle extension on either side. - 6 - 1 - read-write - - - CUAEN - Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update. - 5 - 1 - read-write - - - LPPLLPD - Low Power PLL Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time. - 4 - 1 - read-write - - - LPIOPD - Low Power I/O Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. - 3 - 1 - read-write - - - ZUEN - Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update). -Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request. -Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request. - 2 - 1 - read-write - - - BDISEN - Byte Disable Enable: Specifies, if set, that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register. - 1 - 1 - read-write - - - PUREN - PHY Update Request Enable: Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift. - 0 - 1 - read-write - - - - - DCR - “DRAM Configuration Register (DCR)” on page 103 - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - UDIMM - Un-buffered DIMM Address Mirroring: Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled. - 29 - 1 - read-write - - - DDR2T - DDR 2T Timing: Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions. - 28 - 1 - read-write - - - NOSRA - No Simultaneous Rank Access: Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems. - 27 - 1 - read-write - - - BYTEMASK - Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training. This allows training to be conducted based on selected bit(s) from the byte lanes. -Valid values for each bit are: -0 = Disable compare for that bit 1 = Enable compare for that bit -Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting. - 10 - 8 - read-write - - - MPRDQ - Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are: -0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’ 1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) - 7 - 1 - read-write - - - PDQ - Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively. - 4 - 3 - read-write - - - DDR8BNK - DDR 8-Bank: Indicates, if set, that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used. -Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters. - 3 - 1 - read-write - - - DDRMD - DDR Mode: SDRAM DDR mode. Valid values are: 000 = Reserved -001 = Reserved -010 = DDR2 -011 = DDR3 -100 – 111 = Reserved - 0 - 3 - read-write - - - - - DTPR0 - DRAM Timing Parameters Register 0-2 (DTPR0-2) - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRC - Activate to activate command delay (same bank). Valid values are 2 to 63. - 26 - 6 - read-write - - - TRRD - Activate to activate command delay (different banks). Valid values are 1 to 15. - 22 - 4 - read-write - - - TRAS - Activate to precharge command delay. Valid values are 2 to 63. - 16 - 6 - read-write - - - TRCD - Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 15. - 12 - 4 - read-write - - - TRP - Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 15. - 8 - 4 - read-write - - - TWTR - Internal write to read command delay. Valid values are 1 to 15. - 4 - 4 - read-write - - - TRTP - Internal read to precharge command delay. Valid values are 2 to 15. - 0 - 4 - read-write - - - - - DTPR1 - DRAM Timing Parameters Register 0-2 (DTPR0-2) - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - TAOND_TAOFD - ODT turn-on/turn-off delays (DDR2 only). Valid values are: 00 = 2/2.5 -01 = 3/3.5 -10 = 4/4.5 -11 = 5/5.5 -Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher. - 30 - 2 - read-write - - - TWLO - Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. - 26 - 4 - read-write - - - TWLMRD - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. - 20 - 6 - read-write - - - TRFC - Refresh-to-Refresh: Indicates the minimum time between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. - 11 - 9 - read-write - - - TFAW - 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63. - 5 - 6 - read-write - - - TMOD - Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values are: 000 = 12 -001 = 13 -010 = 14 -011 = 15 -100 = 16 -101 = 17 -110 – 111 = Reserved - 2 - 3 - read-write - - - TMRD - Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7. - 0 - 2 - read-write - - - - - DTPR2 - DRAM Timing Parameters Register 0-2 (DTPR0-2) - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - TCCD - Read to read and write to write command delay. Valid values are: 0 = BL/2 for DDR2 and 4 for DDR3 -1 = BL/2 + 1 for DDR2 and 5 for DDR3 - 31 - 1 - read-write - - - TRTW - Read to Write command delay. Valid values are: -0 = standard bus turn around delay -1 = add 1 clock to standard bus turn around delay -This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. - 30 - 1 - read-write - - - TRTODT - Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. Valid values are: -0 = ODT may be turned on immediately after read post-amble -1 = ODT may not be turned on until one clock after the read post-amble -If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. - 29 - 1 - read-write - - - TDLLK - DLL locking time. Valid values are 2 to 1023. - 19 - 10 - read-write - - - TCKE - CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15. - 15 - 4 - read-write - - - TXP - Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31. - 10 - 5 - read-write - - - TXS - Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023. - 0 - 10 - read-write - - - - - MR0 - “Mode Register 0 (MR0)” on page 108 - UNION_MR0 - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PD - Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: -0 = Slow exit (DLL off) 1 = Fast exit (DLL on) - 12 - 1 - read-write - - - WR - Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: -000 = 16 -001 = 5 -010 = 6 -011 = 7 -100 = 8 -101 = 10 -110 = 12 -111 = 14 -All other settings are reserved and should not be used. -NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. - 9 - 3 - read-write - - - DR - DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. - 8 - 1 - read-write - - - TM - Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. - 7 - 1 - read-write - - - CLH - CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: -0010 = 5 -0100 = 6 -0110 = 7 -1000 = 8 -1010 = 9 -1100 = 10 -1110 = 11 -0001 = 12 -0011 = 13 -0101 = 14 -All other settings are reserved and should not be used. - 4 - 3 - read-write - - - BT - Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). - 3 - 1 - read-write - - - CLL - CAS Latency low bit - 2 - 1 - read-write - - - BL - Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: -Valid values for DDR3 are: 00 = 8 (Fixed) -01 = 4 or 8 (On the fly) -10 = 4 (Fixed) -11 = Reserved - 0 - 2 - read-write - - - - - MR - No description available - UNION_MR0 - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PD - Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: -0 = Fast exit 1 = Slow exit - 12 - 1 - read-write - - - WR - Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: -001 = 2 -010 = 3 -011 = 4 -100 = 5 -101 = 6 -All other settings are reserved and should not be used. -NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. - 9 - 3 - read-write - - - DR - DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. - 8 - 1 - read-write - - - TM - Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. - 7 - 1 - read-write - - - CL - CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: -010 = 2 -011 = 3 -100 = 4 -101 = 5 -110 = 6 -111 = 7 -All other settings are reserved and should not be used. - 4 - 3 - read-write - - - BT - Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). - 3 - 1 - read-write - - - BL - Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: -010 = 4 -011 = 8 -All other settings are reserved and should not be used. - 0 - 3 - read-write - - - - - MR1 - “Mode Register 1 (MR1)” on page 111 - UNION_MR1 - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - QOFF - Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. - 12 - 1 - read-write - - - TDQS - Termination Data Strobe: When enabled (‘1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM datasheet for details. - 11 - 1 - read-write - - - RTTH - On Die Termination high bit - 9 - 1 - read-write - - - LEVEL - Write Leveling Enable: Enables write-leveling when set. - 7 - 1 - read-write - - - RTTM - On Die Termination mid bit: -Selects the effective resistance for SDRAM on die termination. Valid values are: -000 = ODT disabled 001 = RZQ/4 -010 = RZQ/2 -011 = RZQ/6 -100 = RZQ/12 -101 = RZQ/8 -All other settings are reserved and should not be used. -Bit on [9, 6,2] - 6 - 1 - read-write - - - DICH - Output Driver Impedance Control high bit: -Controls the output drive strength. Valid values are: -00 = RZQ/6 -01 = RZQ7 -10 = Reserved -11 = Reserved - 5 - 1 - read-write - - - AL - Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: -00 = 0 (AL disabled) -01 = CL - 1 -10 = CL - 2 -11 = Reserved - 3 - 2 - read-write - - - RTTL - On Die Termination low bit - 2 - 1 - read-write - - - DICL - Output Driver Impedance Control low bit - 1 - 1 - read-write - - - DE - DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. -Note: SDRAM DLL off mode is not supported - 0 - 1 - read-write - - - - - EMR - No description available - UNION_MR1 - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - QOFF - Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be -used for IDD characterization of read current and should not be used in normal operation. - 12 - 1 - read-write - - - RDQS - RDQS Enable/Disable: When enabled (‘1’), RDQS is identical in function and timing to data strobe DQS during a read, and ignored during a write. A ‘0’ disables the SDRAM from driving RDQS. The Controller does not allow the user to change this bit. - 11 - 1 - read-write - - - DQS - DQS_b Enable/Disable: When ‘0’, DQS_b is the complement of the differential data strobe pair DQS/DQS_b. When ‘1’, DQS is used in a single-ended mode and the DQS_b pin is disabled. Also used to similarly enable/disable RDQS_b if RDQS is enabled. The Controller does not allow the user to change this bit. - 10 - 1 - read-write - - - OCD - Off-Chip Driver (OCD) Impedance Calibration: Used to calibrate and match pull-up to pull- down impedance to 18  nominal (refer to the SDRAM datasheet for details). Valid values are: -000 = OCD calibration mode exit 001 = Drive (1) pull-up -010 = Drive (0) pull-down -100 = OCD enter adjust mode 111 = OCD calibration default -All other settings are reserved and should not be used. Note that OCD is not supported by all vendors. Refer to the SDRAM datasheet for details on the recommended OCD settings. - 7 - 3 - read-write - - - RTTH - On Die Termination high bit: -Selects the effective resistance for SDRAM on die termination. Valid values are: -00 = ODT disabled 01 = 75 -10 = 150 -11 = 50 (some vendors) - 6 - 1 - read-write - - - AL - Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: -000 = 0 -001 = 1 -010 = 2 -011 = 3 -100 = 4 -101 = 5 -All other settings are reserved and should not be used. The maximum allowed value of AL is tRCD-1. - 3 - 3 - read-write - - - RTTL - On Die Termination low bit: - 2 - 1 - read-write - - - DIC - Output Driver Impedance Control: Controls the output drive strength. Valid values are: -0 = Full strength -1 = Reduced strength - 1 - 1 - read-write - - - DE - DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. - 0 - 1 - read-write - - - - - MR2 - “Mode Register 2/Extended Mode Register 2 (MR2/EMR2)” on page 114 - UNION_MR2 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - RTTWR - Dynamic ODT: Selects RTT for dynamic ODT. Valid values are: 00 = Dynamic ODT off -01 = RZQ/4 -10 = RZQ/2 -11 = Reserved - 9 - 2 - read-write - - - SRT - Self-Refresh Temperature Range: Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh. - 7 - 1 - read-write - - - ASR - Auto Self-Refresh: When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. -Otherwise the SRT bit must be programmed to indicate the temperature range. - 6 - 1 - read-write - - - CWL - CAS Write Latency: The delay between when the SDRAM registers a write command to when write data is available. Valid values are: -000 = 5 (tCK > 2.5ns) -001 = 6 (2.5ns > tCK > 1.875ns) -010 = 7 (1.875ns > tCK> 1.5ns) -011 = 8 (1.5ns > tCK > 1.25ns) -100 = 9 (1.25ns > tCK > 1.07ns) -101 = 10 (1.07ns > tCK > 0.935ns) -110 = 11 (0.935ns > tCK > 0.833ns) -111 = 12 (0.833ns > tCK > 0.75ns) -All other settings are reserved and should not be used. - 3 - 3 - read-write - - - PASR - Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. -Valid settings for 4 banks are: -000 = Full Array -001 = Half Array (BA[1:0] = 00 & 01) -010 = Quarter Array (BA[1:0] = 00) 011 = Not defined -100 = 3/4 Array (BA[1:0] = 01, 10, & 11) -101 = Half Array (BA[1:0] = 10 & 11) -110 = Quarter Array (BA[1:0] = 11) 111 = Not defined -Valid settings for 8 banks are: -000 = Full Array -001 = Half Array (BA[2:0] = 000, 001, 010 & 011) -010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) -100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) -101 = Half Array (BA[2:0] = 100, 101, 110 & 111) -110 = Quarter Array (BA[2:0] = 110 & 111) -111 = 1/8 Array (BA[2:0] 111) - 0 - 3 - read-write - - - - - EMR2 - No description available - UNION_MR2 - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - SRF - Self Refresh Rate: Enables, if set, high temperature self refresh rate. - 7 - 1 - read-write - - - DCC - Duty Cycle Corrector: Enables, if set, duty cycle correction within SDRAM. - 3 - 1 - read-write - - - PASR - Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. -Valid settings for 4 banks are: -000 = Full Array -001 = Half Array (BA[1:0] = 00 & 01) -010 = Quarter Array (BA[1:0] = 00) 011 = Not defined -100 = 3/4 Array (BA[1:0] = 01, 10, & 11) -101 = Half Array (BA[1:0] = 10 & 11) -110 = Quarter Array (BA[1:0] = 11) 111 = Not defined -Valid settings for 8 banks are: -000 = Full Array -001 = Half Array (BA[2:0] = 000, 001, 010 & 011) -010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) -100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) -101 = Half Array (BA[2:0] = 100, 101, 110 & 111) -110 = Quarter Array (BA[2:0] = 110 & 111) -111 = 1/8 Array (BA[2:0] 111) - 0 - 3 - read-write - - - - - MR3 - “Mode Register 3 (MR3)” on page 116 - UNION_MR3 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - MPR - Multi-Purpose Register Enable: Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array. - 2 - 1 - read-write - - - MPRLOC - Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are: 00 = Predefined pattern for system calibration -All other settings are reserved and should not be used. - 0 - 2 - read-write - - - - - EMR3 - No description available - UNION_MR3 - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - - - ODTCR - “ODT Configuration Register (ODTCR)” on page 117 - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRODT3 - No description available - 28 - 4 - read-write - - - WRODT2 - No description available - 24 - 4 - read-write - - - WRODT1 - No description available - 20 - 4 - read-write - - - WRODT0 - Write ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a write command is sent to rank n. WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to enable ODT only on rank being written to. - 16 - 4 - read-write - - - RDODT3 - No description available - 12 - 4 - read-write - - - RDODT2 - No description available - 8 - 4 - read-write - - - RDODT1 - No description available - 4 - 4 - read-write - - - RDODT0 - Read ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a read command is sent to rank n. RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to disable ODT during reads. - 0 - 4 - read-write - - - - - DTCR - “Data Training Configuration Register (DTCR)” on page 118 - 0x68 - 32 - 0x00000000 - 0xFF7FFFFF - - - RFSHDT - Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. - 28 - 4 - read-write - - - RANKEN - Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0, bit 1 controls rank 1, bit 2 controls rank 2, and bit 3 controls rank 3. Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank. - 24 - 4 - read-write - - - DTEXD - Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes. -Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment. - 22 - 1 - read-write - - - DTDSTP - Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step. This bit is used to initiate one step of the data training algorithm in question. -This bit is self-clearing. To trigger the next step, this bit must be written to again. Note: The training steps must be repeated in order to get new data in the “Data Training Eye Data Register 0-1 (DTEDR0-1)” on page 122. For example, to see the -training results for a different lane, select that lane and repeat the training steps to -populate DTEDR0 and DTEDR1 with the correct data. - 21 - 1 - read-write - - - DTDEN - Data Training Debug Enable: Enables, if set, the data training single step debug mode. - 20 - 1 - read-write - - - DTDBS - Data Training Debug Byte Select: Selects the byte during data training single step debug mode. -Note: DTDEN is not used to enable this feature. - 16 - 4 - read-write - - - DTWDQMO - Data Training WDQ Margin Override: If set, the Training WDQ Margin value specified in DTCR[11:8] (DTWDQM) is used during data training. Otherwise the value is computed as ¼ of the ddr_clk period measurement found during calibration of the WDQ LCDL. - 14 - 1 - read-write - - - DTBDC - Data Training Bit Deskew Centering: Enables, if set, eye centering capability during write and read bit deskew training. - 13 - 1 - read-write - - - DTWBDDM - Data Training Write Bit Deskew Data Mask, if set, it enables write bit deskew of the data mask - 12 - 1 - read-write - - - DTWDQM - Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ LCDL can be moved during training. Basically defines how much timing margin. - 8 - 4 - read-write - - - DTCMPD - Read Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data-training only checks if the correct number of DQS edges were returned. - 7 - 1 - read-write - - - DTMPR - Read Data Training Using MPR (DDR3 Only): Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back. - 6 - 1 - read-write - - - DTRANK - Data Training Rank: Select the SDRAM rank to be used during Read DQS gate training, Read/Write Data Bit Deskew, Read/Write Eye Training. - 4 - 2 - read-write - - - DTRPTN - Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read. -Note: The minimum value should be 0x4 and the maximum value should be 0x14. - 0 - 4 - read-write - - - - - DTAR0 - Data Training Address Register 0-3 (DTAR0-3) - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - DTBANK - Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - 28 - 3 - read-write - - - DTROW - Data Training Row Address: Selects the SDRAM row address to be used during data training. - 12 - 16 - read-write - - - DTCOL - Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - 0 - 12 - read-write - - - - - DTAR1 - Data Training Address Register 0-3 (DTAR0-3) - 0x70 - 32 - 0x00000000 - 0xFFFFFFFF - - - DTBANK - Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - 28 - 3 - read-write - - - DTROW - Data Training Row Address: Selects the SDRAM row address to be used during data training. - 12 - 16 - read-write - - - DTCOL - Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - 0 - 12 - read-write - - - - - DTAR2 - Data Training Address Register 0-3 (DTAR0-3) - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - DTBANK - Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - 28 - 3 - read-write - - - DTROW - Data Training Row Address: Selects the SDRAM row address to be used during data training. - 12 - 16 - read-write - - - DTCOL - Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - 0 - 12 - read-write - - - - - DTAR3 - Data Training Address Register 0-3 (DTAR0-3) - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - DTBANK - Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - 28 - 3 - read-write - - - DTROW - Data Training Row Address: Selects the SDRAM row address to be used during data training. - 12 - 16 - read-write - - - DTCOL - Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - 0 - 12 - read-write - - - - - DTDR0 - Data Training Eye Data Register 0-1 (DTEDR0-1) - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - DTBYTE3 - No description available - 24 - 8 - read-write - - - DTBYTE2 - No description available - 16 - 8 - read-write - - - DTBYTE1 - No description available - 8 - 8 - read-write - - - DTBYTE0 - Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. - 0 - 8 - read-write - - - - - DTDR1 - Data Training Eye Data Register 0-1 (DTEDR0-1) - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - DTBYTE7 - No description available - 24 - 8 - read-write - - - DTBYTE6 - No description available - 16 - 8 - read-write - - - DTBYTE5 - No description available - 8 - 8 - read-write - - - DTBYTE4 - Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. - 0 - 8 - read-write - - - - - DTEDR0 - Data Training Eye Data Register 0-1 (DTEDR0-1) - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - DTWBMX - Data Training Write BDL Shift Maximum. - 24 - 8 - read-only - - - DTWBMN - Data Training Write BDL Shift Minimum. - 16 - 8 - read-only - - - DTWLMX - Data Training WDQ LCDL Maximum. - 8 - 8 - read-only - - - DTWLMN - Data Training WDQ LCDL Minimum. - 0 - 8 - read-only - - - - - DTEDR1 - Data Training Eye Data Register 0-1 (DTEDR0-1) - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - DTRBMX - Data Training Read BDL Shift Maximum. - 24 - 8 - read-only - - - DTRBMN - Data Training Read BDL Shift Minimum. - 16 - 8 - read-only - - - DTRLMX - Data Training RDQS LCDL Maximum. - 8 - 8 - read-only - - - DTRLMN - Data Training RDQS LCDL Minimum. - 0 - 8 - read-only - - - - - PGCR2 - “PHY General Configuration Register 2 (PGCR2)” on page 87 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - DYNACPDD1 - Dynamic AC Power Down Driver: Powers down, when set, the output driver on I/O for ADDR and BA. This bit is ORed with bit ACIOCR[3] (ACPDD). - 31 - 1 - read-write - - - LPMSTRC0 - Low-Power Master Channel 0: set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously. Only valid in shared-AC mode. - 30 - 1 - read-write - - - ACPDDC - AC Power-Down with Dual Channels: Set to 1 to power-down address/command lane when both data channels are powered-down. Only valid in shared-AC mode. - 29 - 1 - read-write - - - SHRAC - Shared-AC mode: set to 1 to enable shared address/command mode with two independent data channels – available only if shared address/command mode support is compiled in. - 28 - 1 - read-write - - - DTPMXTMR - Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. - 20 - 8 - read-write - - - FXDLAT - Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are: -0 = Disable fixed read latency 1 = Enable fixed read latency -Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR clock cycles - 19 - 1 - read-write - - - NOBUB - No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: 0 = Bubbles are allowed during reads -1 = Bubbles are not allowed during reads - 18 - 1 - read-write - - - TREFPRD - Refresh Period: Indicates the period, after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. The default corresponds to DDR3 9*7.8us at 1066MHz when a burst of 9 refreshes are issued at every refresh interval. - 0 - 18 - read-write - - - - - RDIMMGCR0 - RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRROR - RDIMM Mirror: Selects between two different ballouts of the RDIMM buffer chip for front or back operation. This register bit controls the buffer chip MIRROR signal. - 31 - 1 - read-only - - - QCSEN - RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal. - 30 - 1 - read-only - - - MIRROROE - MIRROR Output Enable: Enables, when set, the output driver on the I/O for MIRROR pin. - 29 - 1 - read-only - - - QCSENOE - QCSEN# Output Enable: Enables, when set, the output driver on the I/O for QCSEN# pin. - 28 - 1 - read-only - - - RDIMMIOM - RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. - 27 - 1 - read-only - - - RDIMMPDR - RDIMM Outputs Power Down Receiver: Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins. - 26 - 1 - read-only - - - RDIMMPDD - RDIMM Outputs Power Down Driver: Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins. - 25 - 1 - read-only - - - RDIMMODT - RDIMM Outputs On-Die Termination: Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins. - 24 - 1 - read-only - - - ERROUTOE - ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin. - 23 - 1 - read-only - - - ERROUTIOM - ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. - 22 - 1 - read-only - - - ERROUTPDR - ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin. - 21 - 1 - read-only - - - ERROUTPDD - ERROUT# Power Down Driver: Powers down, when set, the output driver on the I/O for ERROUT# pin. - 20 - 1 - read-only - - - ERROUTODT - ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin. - 19 - 1 - read-only - - - PARINOE - PAR_IN Output Enable: Enables, when set, the output driver on the I/O for PAR_IN pin. - 18 - 1 - read-only - - - PARINIOM - PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. - 17 - 1 - read-only - - - PARINPDR - PAR_IN Power Down Receiver: Powers down, when set, the input receiver on the I/O for PAR_IN pin. - 16 - 1 - read-only - - - PARINPDD - PAR_IN Power Down Driver: Powers down, when set, the output driver on the I/O for PAR_IN pin. - 15 - 1 - read-only - - - PARINODT - PAR_IN On-Die Termination: Enables, when set, the on-die termination on the I/O for PAR_IN pin. - 14 - 1 - read-only - - - SOPERR - Stop On Parity Error: Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error. Transactions can resume only after status is cleared via PIR.CLRSR. - 2 - 1 - read-only - - - ERRNOREG - Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized as shown in Figure 4-30 on page 262. - 1 - 1 - read-only - - - RDIMM - Registered DIMM: Indicates, if set, that a registered DIMM is used. In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM. The DCR.NOSRA register bit must be set to ‘1’ if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. - 0 - 1 - read-only - - - - - RDIMMGCR1 - RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) - 0xb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRINIT - Control Registers Initialization Enable: Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip. A setting of ‘1’ on CRINIT[n] bit means that CRn should be written during initialization. - 16 - 16 - read-only - - - TBCMRD - Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter. - 12 - 3 - read-only - - - TBCSTAB - Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz. - 0 - 12 - read-only - - - - - RDIMMCR0 - RDIMM Control Register 0-1 (RDIMMCR0-1) - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RC7 - Control Word 7: Reserved, free to use by vendor. - 28 - 4 - read-only - - - RC6 - Control Word 6: Reserved, free to use by vendor. - 24 - 4 - read-only - - - RC5 - Control Word 5 (CK Driver Characteristics Control Word): RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs. Bit definitions are: -00 = Light drive (4 or 5 DRAM loads) -01 = Moderate drive (8 or 10 DRAM loads) -10 = Strong drive (16 or 20 DRAM loads) -11 = Reserved - 20 - 4 - read-only - - - RC4 - Control Word 4 (Control Signals Driver Characteristics Control Word): RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs. Bit definitions are: -00 = Light drive (4 or 5 DRAM loads) -01 = Moderate drive (8 or 10 DRAM loads) -10 = Reserved -11 = Reserved - 16 - 4 - read-only - - - RC3 - Control Word 3 (Command/Address Signals Driver Characteristics Control Word): RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs. Bit definitions are: -00 = Light drive (4 or 5 DRAM loads) -01 = Moderate drive (8 or 10 DRAM loads) -10 = Strong drive (16 or 20 DRAM loads) -11 = Reserved - 12 - 4 - read-only - - - RC2 - Control Word 2 (Timing Control Word): Bit definitions are: -RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC12. RC2[1]: 0 = Reserved. -RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2. - 8 - 4 - read-only - - - RC1 - Control Word 1 (Clock Driver Enable Control Word): Bit definitions are: RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled. -RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled. - 4 - 4 - read-only - - - RC0 - Control Word 0 (Global Features Control Word): Bit definitions are: RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled. -RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled. - 0 - 4 - read-only - - - - - RDIMMCR1 - RDIMM Control Register 0-1 (RDIMMCR0-1) - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - RC15 - Control Word 15: Reserved for future use. - 28 - 4 - read-only - - - RC14 - Control Word 14: Reserved for future use. - 24 - 4 - read-only - - - RC13 - Control Word 13: Reserved for future use. - 20 - 4 - read-only - - - RC12 - Control Word 12: Reserved for future use. - 16 - 4 - read-only - - - RC11 - Control Word 11 (Operating Voltage VDD Control Word): RC10[1:0] is VDD operating voltage setting as follows: 00 = DDR3 1.5V mode -01 = DDR3L 1.35V mode -10 = Reserved -11 = Reserved RC10[3:2]: Reserved. - 12 - 4 - read-only - - - RC10 - Control Word 10 (RDIMM Operating Speed Control Word): RC10[2:0] is RDIMM operating speed setting as follows: 000 = DDR3/DDR3L-800 -001 = DDR3/DDR3L-1066 -010 = DDR3/DDR3L-1333 -011 = DDR3/DDR3L-1600 -100 = Reserved -101 = Reserved -110 = Reserved -111 = Reserved RC10[3]: Don’t care. - 8 - 4 - read-only - - - RC9 - Control Word 9 (Power Saving Settings Control Word): Bit definitions are: RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. RC9[1]: 0 = Reserved. -RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW. RC9[2] is valid only when RC9[3] is 1. -RC9[3]: 0 = CKE power down mode disabled, 1 = CKE power down mode enabled. - 4 - 4 - read-only - - - RC8 - Control Word 8 (Additional Input Bus Termination Setting Control Word): RC8[2:0] is Input Bus Termination (IBT) setting as follows: -000 = IBT as defined in RC2. 001 = Reserved -010 = 200 Ohm -011 = Reserved -100 = 300 Ohm -101 = Reserved -110 = Reserved -111 = Off -RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high - 0 - 4 - read-only - - - - - DCUAR - “DCU Address Register (DCUAR)” on page 129 - 0xc0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ATYPE - Access Type: Specifies the type of access to be performed using this address. Valid values are: -0 = Write access 1 = Read access - 11 - 1 - read-write - - - INCA - Increment Address: Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. - 10 - 1 - read-write - - - CSEL - Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache -01 = Expected data cache 10 = Read data cache -11 = Reserved - 8 - 2 - read-write - - - CSADDR - Cache Slice Address: Address of the cache slice to be accessed. - 4 - 4 - read-write - - - CWADDR - Cache Word Address: Address of the cache word to be accessed. - 0 - 4 - read-write - - - - - DCUDR - “DCU Data Register (DCUDR)” on page 130 - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CDATA - Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register. - 0 - 32 - read-write - - - - - DCURR - “DCU Run Register (DCURR)” on page 130 - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - XCEN - Expected Compare Enable: Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data. - 23 - 1 - read-write - - - RCEN - Read Capture Enable: Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache. - 22 - 1 - read-write - - - SCOF - Stop Capture On Full: Specifies, if set, that the capture of read data should stop when the capture cache is full. - 21 - 1 - read-write - - - SONF - Stop On Nth Fail: Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command. - 20 - 1 - read-write - - - NFAIL - Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. -Valid values are from 0 to 254. - 12 - 8 - read-write - - - EADDR - End Address: Cache word address where the execution of command should end. - 8 - 4 - read-write - - - SADDR - Start Address: Cache word address where the execution of commands should begin. - 4 - 4 - read-write - - - DINST - DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation -0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache. -0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See “DCU Status” on page 255 for details. -0101 – 1111 Reserved - 0 - 4 - read-write - - - - - DCULR - “DCU Loop Register (DCULR)” on page 131 - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - XLEADDR - Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address. -XLEADDR field uses only the following bits based on the cache depth: -DCU expected data cache = 4, XLEADDR[1:0] -DCU expected data cache = 8, XLEADDR[2:0] -DCU expected data cache = 16, XLEADDR[3:0] - 28 - 4 - read-write - - - IDA - Increment DRAM Address: Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. - 17 - 1 - read-write - - - LINF - Loop Infinite: Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times. - 16 - 1 - read-write - - - LCNT - Loop Count: The number of times that the loop should be executed if LINF is not set. - 8 - 8 - read-write - - - LEADDR - Loop End Address: Command cache word address where the loop should end. - 4 - 4 - read-write - - - LSADDR - Loop Start Address: Command cache word address where the loop should start. - 0 - 4 - read-write - - - - - DCUGCR - “DCU General Configuration Register (DCUGCR)” on page 132 - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RCSW - Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data. - 0 - 16 - read-write - - - - - DCUTPR - “DCU Timing Parameter Register (DCUTPR)” on page 132 - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDCUT3 - DCU Generic Timing Parameter 3 - 24 - 8 - read-write - - - TDCUT2 - DCU Generic Timing Parameter 2 - 16 - 8 - read-write - - - TDCUT1 - DCU Generic Timing Parameter 1 - 8 - 8 - read-write - - - TDCUT0 - DCU Generic Timing Parameter 0 - 0 - 8 - read-write - - - - - DCUSR0 - DCU Status Register 0-1 (DCUSR0-1) - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFULL - Capture Full: Indicates, if set, that the capture cache is full. - 2 - 1 - read-only - - - CFAIL - Capture Fail: Indicates, if set, that at least one read data word has failed. - 1 - 1 - read-only - - - RDONE - Run Done: Indicates, if set, that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. - 0 - 1 - read-only - - - - - DCUSR1 - DCU Status Register 0-1 (DCUSR0-1) - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - LPCNT - Loop Count: Indicates the value of the loop count. This is useful when the program has stopped because of failures to assess how many reads were executed before first fail. - 24 - 8 - read-only - - - FLCNT - Fail Count: Number of read words that have failed. - 16 - 8 - read-only - - - RDCNT - Read Count: Number of read words returned from the SDRAM. - 0 - 16 - read-only - - - - - BISTRR - “BIST Run Register (BISTRR)” on page 133 - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - BCCSEL - BIST Clock Cycle Select: Selects the clock numbers on which the AC loopback data is written into the FIFO. Data is written into the loopback FIFO once every four clock cycles. Valid values are: -00 = Clock cycle 0, 4, 8, 12, etc. -01 = Clock cycle 1, 5, 9, 13, etc. -10 = Clock cycle 2, 6, 10, 14, etc. -11 = Clock cycle 3, 7, 11, 15, etc. - 25 - 2 - read-write - - - BCKSEL - BIST CK Select: Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are: -00 = CK[0] -01 = CK[1] -10 = CK[2] -11 = Reserved - 23 - 2 - read-write - - - BDXSEL - BIST DATX8 Select: Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8. - 19 - 4 - read-write - - - BDPAT - BIST Data Pattern: Selects the data pattern used during BIST. Valid values are: 00 = Walking 0 -01 = Walking 1 -10 = LFSR-based pseudo-random -11 = User programmable (Not valid for AC loopback). - 17 - 2 - read-write - - - BDMEN - BIST Data Mask Enable: Enables, if set, that the data mask BIST should be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for loopback mode. - 16 - 1 - read-write - - - BACEN - BIST AC Enable: Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to ‘1’ at the same time. - 15 - 1 - read-write - - - BDXEN - BIST DATX8 Enable: Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to ‘1’ at the same time. - 14 - 1 - read-write - - - BSONF - BIST Stop On Nth Fail: Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered. - 13 - 1 - read-write - - - NFAIL - Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set. - 5 - 8 - read-write - - - BINF - BIST Infinite Run: Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered. Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated. - 4 - 1 - read-write - - - BMODE - BIST Mode: Selects the mode in which BIST is run. Valid values are: -0 = Loopback mode: Address, commands and data loop back at the PHY I/Os. -1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses. - 3 - 1 - read-write - - - BINST - BIST Instruction: Selects the BIST instruction to be executed: Valid values are: 000 = NOP: No operation -001 = Run: Triggers the running of the BIST. 010 = Stop: Stops the running of the BIST. -011 = Reset: Resets all BIST run-time registers, such as error counters. 100 – 111 Reserved - 0 - 3 - read-write - - - - - BISTWCR - “BIST Word Count Register (BISTWCR)” on page 136 - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - BWCNT - BIST Word Count: Indicates the number of words to generate during BIST. This must be a multiple of DRAM burst length (BL) divided by 2, e.g. for BL=8, valid values are 4, 8, 12, 16, and so on. - 0 - 16 - read-write - - - - - BISTMSKR0 - BIST Mask Register 0-2 (BISTMSKR0-2) - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - ODTMSK - Mask bit for each of the up to 4 ODT bits. - 28 - 4 - read-write - - - CSMSK - Mask bit for each of the up to 4 CS# bits. - 24 - 4 - read-write - - - CKEMSK - Mask bit for each of the up to 4 CKE bits. - 20 - 4 - read-write - - - WEMSK - Mask bit for the WE#. - 19 - 1 - read-write - - - BAMSK - Mask bit for each of the up to 3 bank address bits. - 16 - 3 - read-write - - - AMSK - Mask bit for each of the up to 16 address bits. - 0 - 16 - read-write - - - - - BISTMSKR1 - BIST Mask Register 0-2 (BISTMSKR0-2) - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - DMMSK - Mask bit for the data mask (DM) bit. - 28 - 4 - read-write - - - PARMSK - Mask bit for the PAR_IN. Only for DIMM parity support and only if the design is compiled for less than 3 ranks. - 27 - 1 - read-write - - - CASMSK - Mask bit for the CAS. - 1 - 1 - read-write - - - RASMSK - Mask bit for the RAS. - 0 - 1 - read-write - - - - - BISTMSKR2 - BIST Mask Register 0-2 (BISTMSKR0-2) - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQMSK - Mask bit for each of the 8 data (DQ) bits. - 0 - 32 - read-write - - - - - BISTLSR - “BIST LFSR Seed Register (BISTLSR)” on page 137 - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEED - LFSR seed for pseudo-random BIST patterns. - 0 - 32 - read-write - - - - - BISTAR0 - BIST Address Register 0-2 (BISTAR0-2) - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - BBANK - BIST Bank Address: Selects the SDRAM bank address to be used during BIST. - 28 - 3 - read-write - - - BROW - BIST Row Address: Selects the SDRAM row address to be used during BIST. - 12 - 16 - read-write - - - BCOL - BIST Column Address: Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. - 0 - 12 - read-write - - - - - BISTAR1 - BIST Address Register 0-2 (BISTAR0-2) - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - BAINC - BIST Address Increment: Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. - 4 - 12 - read-write - - - BMRANK - BIST Maximum Rank: Specifies the maximum SDRAM rank to be used during BIST. The default value is set to maximum ranks minus 1. Example default shown here is for a 4-rank system - 2 - 2 - read-write - - - BRANK - BIST Rank: Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1. - 0 - 2 - read-write - - - - - BISTAR2 - BIST Address Register 0-2 (BISTAR0-2) - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - BMBANK - BIST Maximum Bank Address: Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank. - 28 - 3 - read-write - - - BMROW - BIST Maximum Row Address: Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank. - 12 - 16 - read-write - - - BMCOL - BIST Maximum Column Address: Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row. - 0 - 12 - read-write - - - - - BISTUDPR - “BIST User Data Pattern Register (BISTUDPR)” on page 138 - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - BUDP1 - BIST User Data Pattern 1: Data to be applied on odd DQ pins during BIST. - 16 - 16 - read-write - - - BUDP0 - BIST User Data Pattern 0: Data to be applied on even DQ pins during BIST. - 0 - 16 - read-write - - - - - BISTGSR - “BIST General Status Register (BISTGSR)” on page 139 - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - CASBER - CAS Bit Error: Indicates the number of bit errors on CAS. - 30 - 2 - read-only - - - RASBER - RAS Bit Error: Indicates the number of bit errors on RAS. - 28 - 2 - read-only - - - DMBER - DM Bit Error: Indicates the number of bit errors on data mask (DM) bit. DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat. Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat. - 20 - 8 - read-only - - - PARBER - PAR_IN Bit Error (DIMM Only): Indicates the number of bit errors on PAR_IN - 16 - 2 - read-only - - - BDXERR - BIST Data Error: indicates, if set, that there is a data comparison error in the byte lane. - 2 - 1 - read-only - - - BACERR - BIST Address/Command Error: indicates, if set, that there is a data comparison error in the address/command lane. - 1 - 1 - read-only - - - BDONE - BIST Done: Indicates, if set, that the BIST has finished executing. This bit is reset to zero when BIST is triggered. - 0 - 1 - read-only - - - - - BISTWER - “BIST Word Error Register (BISTWER)” on page 139 - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - DXWER - Byte Word Error: Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count. - 16 - 16 - read-only - - - ACWER - Address/Command Word Error: Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count. - 0 - 16 - read-only - - - - - BISTBER0 - BIST Bit Error Register 0-3 (BISTBER0-3) - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - ABER - Address Bit Error: Each group of two bits indicate the bit error count on each of the - 0 - 32 - read-only - - - - - BISTBER1 - BIST Bit Error Register 0-3 (BISTBER0-3) - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - ODTBER - ODT Bit Error: Each group of two bits indicates the bit error count on each of the up to 4 ODT bits. [1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on. - 24 - 8 - read-only - - - CSBER - CS# Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CS# bits. [1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on. - 16 - 8 - read-only - - - CKEBER - CKE Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CKE bits. [1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on. - 8 - 8 - read-only - - - WEBER - WE# Bit Error: Indicates the number of bit errors on WE#. - 6 - 2 - read-only - - - BABER - Bank Address Bit Error: Each group of two bits indicate the bit error count on each of the up to 3 bank address bits. [1:0] is the error count for BA[0], [3:2] for BA[1], and so on. - 0 - 6 - read-only - - - - - BISTBER2 - BIST Bit Error Register 0-3 (BISTBER0-3) - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQBER0 - Data Bit Error: The error count for even DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. - 0 - 32 - read-only - - - - - BISTBER3 - BIST Bit Error Register 0-3 (BISTBER0-3) - 0x13c - 32 - 0x00000000 - 0xFFFFFFFF - - - DQBER1 - Data Bit Error: The error count for odd DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. - 0 - 32 - read-only - - - - - BISTWCSR - “BIST Word Count Status Register (BISTWCSR)” on page 141 - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - DXWCNT - Byte Word Count: Indicates the number of words received from the byte lane. - 16 - 16 - read-only - - - ACWCNT - Address/Command Word Count: Indicates the number of words received from the address/command lane. - 0 - 16 - read-only - - - - - BISTFWR0 - BIST Fail Word Register 0-2 (BISTFWR0-2) - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - ODTWEBS - Bit status during a word error for each of the up to 4 ODT bits. - 28 - 4 - read-only - - - CSWEBS - Bit status during a word error for each of the up to 4 CS# bits. - 24 - 4 - read-only - - - CKEWEBS - Bit status during a word error for each of the up to 4 CKE bits. - 20 - 4 - read-only - - - WEWEBS - Bit status during a word error for the WE#. - 19 - 1 - read-only - - - BAWEBS - Bit status during a word error for each of the up to 3 bank address bits. - 16 - 3 - read-only - - - AWEBS - Bit status during a word error for each of the up to 16 address bits. - 0 - 16 - read-only - - - - - BISTFWR1 - BIST Fail Word Register 0-2 (BISTFWR0-2) - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - DMWEBS - Bit status during a word error for the data mask (DM) bit. DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on. - 28 - 4 - read-only - - - PARWEBS - Bit status during a word error for the PAR_IN. Only for DIMM parity support - 26 - 1 - read-only - - - CASWEBS - Bit status during a word error for the CAS. - 1 - 1 - read-only - - - RASWEBS - Bit status during a word error for the RAS. - 0 - 1 - read-only - - - - - BISTFWR2 - BIST Fail Word Register 0-2 (BISTFWR0-2) - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - DQWEBS - Bit status during a word error for each of the 8 data (DQ) bits. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DQ[7:0] on the rising edge of DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on. For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on. - 0 - 32 - read-only - - - - - AACR - “Anti-Aging Control Register (AACR)” on page 143 - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - AAOENC - Anti-Aging PAD Output Enable Control: Enables, if set, anti-aging toggling on the pad output enable signal “ctl_oe_n” going into the DATX8s. This will increase power consumption for the anti-aging feature. - 31 - 1 - read-write - - - AAENC - Anti-Aging Enable Control: Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. - 30 - 1 - read-write - - - AATR - Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. -The default value correspond to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us. -The default value may also be overridden by the macro DWC_AACR_AATR_DFLT. - 0 - 30 - read-write - - - - - GPR0 - General Purpose Register 0-1 (GPR0-1) - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR0 - General Purpose Register 0: General purpose register bits. - 0 - 32 - read-write - - - - - GPR1 - General Purpose Register 0-1 (GPR0-1) - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR1 - General Purpose Register 1: General purpose register bits. - 0 - 32 - read-write - - - - - 4 - 0x10 - 0,1,2,3 - ZQ[%s] - no description available - 0x180 - - CR0 - Impedance Control Register 0-1 (ZQnCR0-1) - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZQPD - ZQ Power Down: Powers down, if set, the PZQ cell. - 31 - 1 - read-write - - - ZCALEN - Impedance Calibration Enable: Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. - 30 - 1 - read-write - - - ZCALBYP - Impedance Calibration Bypass: Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress. Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. - 29 - 1 - read-write - - - ZDEN - Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field. Otherwise, the control is generated automatically by the impedance control logic. - 28 - 1 - read-write - - - ZDATA - Impedance Over-Ride Data: Data used to directly drive the impedance control. -ZDATA field mapping for D3F I/Os is as follows: -ZDATA[27:21] is used to select the pull-up on-die termination impedance ZDATA[20:14] is used to select the pull-down on-die termination impedance ZDATA[13:7] is used to select the pull-up output impedance -ZDATA[6:0] is used to select the pull-down output impedance -ZDATA field mapping for D3A/B/R I/Os is as follows: ZDATA[27:20] is reserved and returns zeros on reads -ZDATA[19:15] is used to select the pull-up on-die termination impedance ZDATA[14:10] is used to select the pull-down on-die termination impedance ZDATA[9:5] is used to select the pull-up output impedance -ZDATA[4:0] is used to select the pull-down output impedance -The default value is 0x000014A for I/O type D3C/R and 0x0001830 for I/O type D3F. - 0 - 28 - read-write - - - - - CR1 - Impedance Control Register 0-1 (ZQnCR0-1) - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DFIPU1 - DFI Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. - 17 - 1 - read-write - - - DFIPU0 - DFI Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. - 16 - 1 - read-write - - - DFICCU - DFI Concurrent Controller Update Interface: Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock. This provides the ability to enable impedance calibration updates for the Address/Command lane. Only valid in shared-AC mode. - 14 - 1 - read-write - - - DFICU1 - DFI Controller Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. - 13 - 1 - read-write - - - DFICU0 - DFI Controller Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. - 12 - 1 - read-write - - - ZPROG - Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: -ZPROG[7:4] = On-die termination divide select ZPROG[3:0] = Output impedance divide select - 0 - 8 - read-write - - - - - SR0 - Impedance Status Register 0-1 (ZQnSR0-1) - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZDONE - Impedance Calibration Done: Indicates that impedance calibration has completed. - 31 - 1 - read-only - - - ZERR - Impedance Calibration Error: If set, indicates that there was an error during impedance calibration. - 30 - 1 - read-only - - - ZCTRL - Impedance Control: Current value of impedance control. ZCTRL field mapping for D3F I/Os is as follows: -ZCTRL[27:21] is used to select the pull-up on-die termination impedance ZCTRL[20:14] is used to select the pull-down on-die termination impedance ZCTRL[13:7] is used to select the pull-up output impedance -ZCTRL[6:0] is used to select the pull-down output impedance -ZCTRL field mapping for D3A/B/R I/Os is as follows: ZCTRL[27:20] is reserved and returns zeros on reads -ZCTRL[19:15] is used to select the pull-up on-die termination impedance ZCTRL[14:10] is used to select the pull-down on-die termination impedance ZCTRL[9:5] is used to select the pull-up output impedance -ZCTRL[4:0] is used to select the pull-down output impedance -Note: The default value is 0x000014A for I/O type D3C/D3R and 0x0001839 for I/O type D3F. - 0 - 28 - read-only - - - - - SR1 - Impedance Status Register 0-1 (ZQnSR0-1) - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OPU - On-die termination (ODT) pull-up calibration status. Similar status encodings as ZPD. - 6 - 2 - read-only - - - OPD - On-die termination (ODT) pull-down calibration status. Similar status encodings as ZPD. - 4 - 2 - read-only - - - ZPU - Output impedance pull-up calibration status. Similar status encodings as ZPD. - 2 - 2 - read-only - - - ZPD - Output impedance pull-down calibration status. Valid status encodings are: 00 = Completed with no errors -01 = Overflow error 10 = Underflow error -11 = Calibration in progress - 0 - 2 - read-only - - - - - - 9 - 0x40 - 0,1,2,3,4,5,6,7,8 - DX[%s] - no description available - 0x1c0 - - GCR - “DATX8 General Configuration Register (DXnGCR)” on page 148 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CALBYP - Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. - 31 - 1 - read-write - - - MDLEN - Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the common DATX8 MDL enable bit. - 30 - 1 - read-write - - - WLRKEN - Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte. Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks. -WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables -rank 3. - 26 - 4 - read-write - - - PLLBYP - PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin. This bit is not self-clearing and a '0' must be written to de-assert the bypass. This bit is ORed with the global BYP configuration bit (see Table 3-10 on page 91). - 19 - 1 - read-write - - - GSHIFT - Gear Shift: Enables, if set, rapid locking mode on the byte PLL. This bit is ORed with the global GSHIFT configuration bit (see Table 3-10 on page 91). - 18 - 1 - read-write - - - PLLPD - PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin. This bit is not self-clearing and a '0' must be written to de-assert the power-down. This bit is ORed with the global PLLPD configuration bit (see -Table 3-10 on page 91). - 17 - 1 - read-write - - - PLLRST - PLL Rest: Resets the byte PLL by driving the PLL reset pin. This bit is not self- clearing and a '0' must be written to de-assert the reset. This bit is ORed with the global PLLRST configuration bit (see Table 3-10 on page 91). - 16 - 1 - read-write - - - DXOEO - Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value. Valid values are: -00 = No override. Output enable is controlled by DFI transactions 01 = output enable is asserted (I/O is forced to output mode). -10 = Output enable is de-asserted (I/O is forced to input mode) 11 = Reserved - 14 - 2 - read-write - - - RTTOAL - RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are: -0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble -1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble - 13 - 1 - read-write - - - RTTOH - RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble. - 11 - 2 - read-write - - - DQRTT - DQ Dynamic RTT Control: If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). - 10 - 1 - read-write - - - DQSRTT - DQS Dynamic RTT Control: If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). - 9 - 1 - read-write - - - DSEN - Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. DQS# is always the inversion of DQS. These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. Valid settings are: -00 = Reserved -01 = DQS toggling with normal polarity (This should be the default setting) 10 = Reserved -11 = Reserved - 7 - 2 - read-write - - - DQSRPD - DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99) - 6 - 1 - read-write - - - DXPDR - Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). - 5 - 1 - read-write - - - DXPDD1 - Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). - 4 - 1 - read-write - - - DXIOM - Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the IOM configuration bit of the individual DATX8(see “DATX8 Common Configuration Register (DXCCR)” on page 99). - 3 - 1 - read-write - - - DQODT - Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). -Note: This bit is only valid when DXnGCR0[10] is '0'. - 2 - 1 - read-write - - - DQSODT - DQS On-Die Termination: Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). -Note: This bit is only valid when DXnGCR0[9] is '0'. - 1 - 1 - read-write - - - DXEN - Data Byte Enable: Enables, if set, the data byte. Setting this bit to '0' disables the byte, i.e. the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. - 0 - 1 - read-write - - - - - GSR0 - DATX8 General Status Registers 0-2 (DXnGSR0-2) - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - WLDQ - Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling. - 28 - 1 - read-only - - - QSGERR - DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. - 24 - 4 - read-only - - - GDQSPRD - Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration. This value is PVT compensated. - 16 - 8 - read-only - - - DPLOCK - DATX8 PLL Lock: Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. - 15 - 1 - read-only - - - WLPRD - Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration. The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period. This value is PVT compensated. - 7 - 8 - read-only - - - WLERR - Write Leveling Error: Indicates, if set, that there is a write leveling error in the DATX8. - 6 - 1 - read-only - - - WLDONE - Write Leveling Done: Indicates, if set, that the DATX8 has completed write leveling. - 5 - 1 - read-only - - - WLCAL - Write Leveling Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. - 4 - 1 - read-only - - - GDQSCAL - Read DQS gating Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. - 3 - 1 - read-only - - - RDQSNCAL - Read DQS# Calibration (Type B/B1 PHY Only): Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. - 2 - 1 - read-only - - - RDQSCAL - Read DQS Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. - 1 - 1 - read-only - - - WDQCAL - Write DQ Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. - 0 - 1 - read-only - - - - - GSR1 - DATX8 General Status Registers 0-2 (DXnGSR0-2) - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLTCODE - Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. - 1 - 24 - read-only - - - DLTDONE - Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. - 0 - 1 - read-only - - - - - BDLR0 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DQ4WBD - DQ4 Write Bit Delay: Delay select for the BDL on DQ4 write path. - 24 - 6 - read-write - - - DQ3WBD - DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path - 18 - 6 - read-write - - - DQ2WBD - DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path. - 12 - 6 - read-write - - - DQ1WBD - DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path. - 6 - 6 - read-write - - - DQ0WBD - DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path. - 0 - 6 - read-write - - - - - BDLR1 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSWBD - DQS Write Bit Delay: Delay select for the BDL on DQS write path - 24 - 6 - read-write - - - DMWBD - DM Write Bit Delay: Delay select for the BDL on DM write path. - 18 - 6 - read-write - - - DQ7WBD - DQ7 Write Bit Delay: Delay select for the BDL on DQ7 write path. - 12 - 6 - read-write - - - DQ6WBD - DQ6 Write Bit Delay: Delay select for the BDL on DQ6 write path. - 6 - 6 - read-write - - - DQ5WBD - DQ5 Write Bit Delay: Delay select for the BDL on DQ5 write path. - 0 - 6 - read-write - - - - - BDLR2 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSNRBD - DQSN Read Bit Delay (Type B/B1 PHY Only): Delay select for the BDL on DQSN read path - 18 - 6 - read-write - - - DSRBD - DQS Read Bit Delay: Delay select for the BDL on DQS read path - 12 - 6 - read-write - - - DQOEBD - DQ Output Enable Bit Delay: Delay select for the BDL on DQ/DM output enable path. - 6 - 6 - read-write - - - DSOEBD - DQS Output Enable Bit Delay: Delay select for the BDL on DQS output enable path - 0 - 6 - read-write - - - - - BDLR3 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DQ4RBD - DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path. - 24 - 6 - read-write - - - DQ3RBD - DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path - 18 - 6 - read-write - - - DQ2RBD - DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path. - 12 - 6 - read-write - - - DQ1RBD - DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path. - 6 - 6 - read-write - - - DQ0RBD - DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path. - 0 - 6 - read-write - - - - - BDLR4 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - DMRBD - DM Read Bit Delay: Delay select for the BDL on DM read path. - 18 - 6 - read-write - - - DQ7RBD - DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path. - 12 - 6 - read-write - - - DQ6RBD - DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path. - 6 - 6 - read-write - - - DQ5RBD - DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path. - 0 - 6 - read-write - - - - - LCDLR0 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - R3WLD - Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL - 24 - 8 - read-write - - - R2WLD - Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL - 16 - 8 - read-write - - - R1WLD - Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL - 8 - 8 - read-write - - - R0WLD - Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL - 0 - 8 - read-write - - - - - LCDLR1 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDQSND - Read DQSN Delay (Type B/B1 PHY Only): Delay select for the read DQSN (RDQS) LCDL - 16 - 8 - read-write - - - RDQSD - Read DQS Delay: Delay select for the read DQS (RDQS) LCDL - 8 - 8 - read-write - - - WDQD - Write Data Delay: Delay select for the write data (WDQ) LCDL - 0 - 8 - read-write - - - - - LCDLR2 - DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - R3DQSGD - Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL - 24 - 8 - read-write - - - R2DQSGD - Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL - 16 - 8 - read-write - - - R1DQSGD - Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL - 8 - 8 - read-write - - - R0DQSGD - Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL - 0 - 8 - read-write - - - - - MDLR - “DATX8 Master Delay Line Register (DXnMDLR)” on page 157 - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MDLD - MDL Delay: Delay select for the LCDL for the Master Delay Line. - 16 - 8 - read-write - - - TPRD - Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. - 8 - 8 - read-write - - - IPRD - Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. - 0 - 8 - read-write - - - - - GTR - “DATX8 General Timing Register (DXnGTR)” on page 159 - 0x30 - 32 - 0x00000000 - 0x000FFFFF - - - R3WLSL - No description available - 18 - 2 - read-write - - - R2WLSL - No description available - 16 - 2 - read-write - - - R1WLSL - No description available - 14 - 2 - read-write - - - R0WLSL - Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling. Power-up default is 01 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register. Every two bits of this register control the latency of each of the (up to) four ranks. R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on. Valid values: -00 = Write latency = WL - 1 01 = Write latency = WL -10 = Write latency = WL + 1 11 = Reserved - 12 - 2 - read-write - - - R3DGSL - No description available - 9 - 3 - read-write - - - R2DGSL - No description available - 6 - 3 - read-write - - - R1DGSL - No description available - 3 - 3 - read-write - - - R0DGSL - Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles. -This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register. Every three bits of this register control the latency of each of the (up to) four ranks. R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on. Valid values are 0 to 7: - 0 - 3 - read-write - - - - - GSR2 - “DATX8 General Status Register 2 (DXnGSR2)” on page 152 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ESTAT - Error Status: If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. - 8 - 4 - read-write - - - WEWN - Write Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. - 7 - 1 - read-write - - - WEERR - Write Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. - 6 - 1 - read-write - - - REWN - Read Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. - 5 - 1 - read-write - - - REERR - Read Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. - 4 - 1 - read-write - - - WDWN - Write Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. - 3 - 1 - read-write - - - WDERR - Write Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. - 2 - 1 - read-write - - - RDWN - Read Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. - 1 - 1 - read-write - - - RDERR - Read Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. - 0 - 1 - read-write - - - - - - - - TSNS - TSNS - TSNS - 0xf4154000 - - 0x0 - 0x3c - registers - - - - T - Temperature - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - Maximum Temperature - 0x4 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - Minimum Temperature - 0x8 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - Sample age - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - Status - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - write-only - - - - - CONFIG - Configuration - 0x14 - 32 - 0x00600300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valid from 24-255, default 96 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, default in 3 -0: measure and return -1: twice and average -2: 4 times and average -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - Sample validity - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - Temperature flag - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - Maximum temperature to interrupt - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - Minimum temperature to interrupt - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - Maximum temperature to reset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - Minimum temperature to reset - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - Configuration in asynchronous mode - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - Polarity of internal comparator - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - Advance configuration - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - BACC - BACC - BACC - 0xf4200000 - - 0x0 - 0x10 - registers - - - - CONFIG - Access timing for access - 0x0 - 32 - 0x00000000 - 0x3000FFFF - - - FAST_WRITE - Use fast write -0: Write normally -1: boost write - 29 - 1 - read-write - - - FAST_READ - Use fast read -0: Read normally -1: boost read - 28 - 1 - read-write - - - TIMING - Time in APB clock cycles, for battery timing penerate - 0 - 16 - read-write - - - - - PRE_TIME - Timing gap before rising edge - 0x8 - 32 - 0x00000000 - 0x000FFFFF - - - PRE_RATIO - Ratio of guard band before rising edge -0: 0 -1: 1/32768 of low level width -2: 1/16384 of low level width -14: 1/4 of low level width -15: 1/2 of low level width - 16 - 4 - read-write - - - PRE_OFFSET - guard band before rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - POST_TIME - Timing gap after rising edge - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - POST_RATIO - Ratio of guard band after rising edge -0: 0 -1: 1/32768 of high level width -2: 1/16384 of high level width -14: 1/4 of high level width -15: 1/2 of high level width - 16 - 4 - read-write - - - POST_OFFSET - guard band after rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - - - BPOR - BPOR - BPOR - 0xf4204000 - - 0x0 - 0x4 - registers - - - - POR_CONFIG - Power on reset config - 0x0 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf4208000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x811F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BUTN - BUTN - BUTN - 0xf420c000 - - 0x0 - 0xc - registers - - - - BTN_STATUS - Button status - 0x0 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click status, write 1 to clear flag -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press status, write 1 to clear flag -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - BTN_IRQ_MASK - Button interrupt mask - 0x4 - 32 - 0x00000000 - 0x77770FFF - - - XWCLICK - wake button click status when power button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 28 - 3 - read-write - - - WCLICK - wake button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 24 - 3 - read-write - - - XPCLICK - power button click status when wake button held interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 20 - 3 - read-write - - - PCLICK - power button click interrupt enable -bit0: clicked -bit1: double clicked -bit2: tripple clicked - 16 - 3 - read-write - - - DBTN - Dual button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 8 - 4 - read-write - - - WBTN - Wake button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 4 - 4 - read-write - - - PBTN - Power button press interrupt enable -bit0: button pressed -bit1: button confirmd -bit2: button long pressed -bit3: button long long pressed - 0 - 4 - read-write - - - - - LED_INTENSE - Debounce setting - 0x8 - 32 - 0x00000000 - 0x000F000F - - - RLED - Rbutton brightness 0 - 16 - 4 - read-write - - - PLED - Pbutton brightness 0 - 0 - 4 - read-write - - - - - - - BGPR - BGPR - BGPR - 0xf4218000 - - 0x0 - 0x20 - registers - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - RTCSHW - RTCSHW - RTC - 0xf421c000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - RTC - RTC - RTC - 0xf4244000 - - - BSEC - BSEC - BSEC - 0xf4240000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - BKEY - BKEY - BKEY - 0xf4248000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf424c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf4250000 - - 0x0 - 0x88 - registers - - - - 4 - 0x10 - tamp0,tamp1,tamp2,tamp3 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf4254000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/SConscript deleted file mode 100644 index 5717c3e6317..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/SConscript +++ /dev/null @@ -1,25 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_batt_iomux.h deleted file mode 100644 index bc71d89ab04..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_batt_iomux.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BATT_IOMUX_H -#define HPM_BATT_IOMUX_H - -/* BIOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_TAMP_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_TAMP_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_TAMP_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_TAMP_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_TAMP_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_TAMP_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_TAMP_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_TAMP_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_TAMP_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_TAMP_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_TAMP_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_TAMP_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_TAMP_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_TAMP_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_TAMP_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_BGPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_TAMP_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_TAMP_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ08_FUNC_CTL_SOC_PZ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_BGPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_TAMP_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_TAMP_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ09_FUNC_CTL_SOC_PZ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_BGPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_TAMP_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_TAMP_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ10_FUNC_CTL_SOC_PZ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_BGPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_TAMP_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_TAMP_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ11_FUNC_CTL_SOC_PZ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ12_FUNC_CTL function mux definitions */ -#define IOC_PZ12_FUNC_CTL_BGPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ12_FUNC_CTL_GPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ12_FUNC_CTL_BGPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ12_FUNC_CTL_TAMP_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ12_FUNC_CTL_TAMP_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ12_FUNC_CTL_SOC_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ12_FUNC_CTL_SOC_PZ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ13_FUNC_CTL function mux definitions */ -#define IOC_PZ13_FUNC_CTL_BGPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ13_FUNC_CTL_GPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ13_FUNC_CTL_BGPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ13_FUNC_CTL_TAMP_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ13_FUNC_CTL_TAMP_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ13_FUNC_CTL_SOC_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ13_FUNC_CTL_SOC_PZ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ14_FUNC_CTL function mux definitions */ -#define IOC_PZ14_FUNC_CTL_BGPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ14_FUNC_CTL_GPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ14_FUNC_CTL_BGPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ14_FUNC_CTL_TAMP_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ14_FUNC_CTL_TAMP_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ14_FUNC_CTL_SOC_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ14_FUNC_CTL_SOC_PZ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ15_FUNC_CTL function mux definitions */ -#define IOC_PZ15_FUNC_CTL_BGPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ15_FUNC_CTL_GPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ15_FUNC_CTL_BGPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ15_FUNC_CTL_TAMP_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ15_FUNC_CTL_TAMP_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ15_FUNC_CTL_SOC_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix BIOC_ */ -#define BIOC_PZ15_FUNC_CTL_SOC_PZ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_bcfg_drv.h deleted file mode 100644 index e477b5b543c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_bcfg_drv.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BCFG_DRV_H -#define HPM_BCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_bcfg_regs.h" - -/** - * - * @brief BCFG driver APIs - * @defgroup bcfg_interface BCFG driver APIs - * @ingroup io_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -/** - * @brief disable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BCFG_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_bpor_drv.h deleted file mode 100644 index b20cd5c3687..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_bpor_drv.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BPOR_DRV_H -#define HPM_BPOR_DRV_H - -#include "hpm_common.h" -#include "hpm_bpor_regs.h" - -/** - * - * @brief BPOR driver APIs - * @defgroup bpor_interface BPOR driver APIs - * @ingroup io_interfaces - * @{ - * - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Enable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Disable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; -} - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_clock_drv.c deleted file mode 100644 index 186efeb0ecd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_clock_drv.c +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_soc.h" -#include "hpm_common.h" -#include "hpm_pllctlv2_drv.h" -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (500000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (666666666UL) -#define FREQ_PRESET1_PLL2_CLK0 (600000000UL) -#define FREQ_PRESET1_PLL2_CLK1 (500000000UL) -#define FREQ_PRESET1_PLL3_CLK0 (516096000UL) -#define FREQ_PRESET1_PLL4_CLK0 (594000000UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) -#define WDG_INSTANCE_NUM (2U) -#define BUS_FREQ_MAX (200000000UL) -#define FREQ_1MHz (1000000UL) - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for ADC - */ -static uint32_t get_frequency_for_adc(uint32_t instance); - -/** - * @brief Get Clock frequency for I2S - */ -static uint32_t get_frequency_for_i2s(uint32_t instance); - -/** - * @brief Get Clock frequency for EWDG - */ -static uint32_t get_frequency_for_ewdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PEWDG - */ -static uint32_t get_frequency_for_pewdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ana0, - clock_node_axis, -}; - -static EWDG_Type *const s_wdgs[] = { HPM_EWDG0, HPM_EWDG1}; - -uint32_t hpm_core_clock; - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq = 0UL; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_adc(node_or_instance); - break; - case CLK_SRC_GROUP_I2S: - clk_freq = get_frequency_for_i2s(node_or_instance); - break; - case CLK_SRC_GROUP_EWDG: - clk_freq = get_frequency_for_ewdg(node_or_instance); - break; - case CLK_SRC_GROUP_PEWDG: - clk_freq = get_frequency_for_pewdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_AXI_SOC: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axis); - break; - case CLK_SRC_GROUP_AXI_FAST: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axif); - break; - case CLK_SRC_GROUP_AXI_VIDEO: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axiv); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq = 0UL; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); - break; - case clock_source_pll1_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); - break; - case clock_source_pll1_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); - break; - case clock_source_pll2_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); - break; - case clock_source_pll2_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); - break; - case clock_source_pll3_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 3U, 0U); - break; - case clock_source_pll4_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 4U, 0U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_ahb(void) -{ - return get_frequency_for_ip_in_common_group(clock_node_axis); -} - -static uint32_t get_frequency_for_adc(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - if (instance < ADC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[instance]); - if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { - node = s_adc_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node == clock_node_axis) { - clk_freq = get_frequency_for_ahb(); - } else { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_i2s(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - clock_node_t node; - uint32_t mux_in_reg; - - if (instance < I2S_INSTANCE_NUM) { - mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[instance]); - if (mux_in_reg == 0) { - node = clock_node_aud0 + instance; - } else if (instance == 0) { - node = clock_node_aud1; - } else { - node = clock_node_aud0; - } - clk_freq = get_frequency_for_ip_in_common_group(node); - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ewdg(uint32_t instance) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { - freq_in_hz = get_frequency_for_ahb(); - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -static uint32_t get_frequency_for_pewdg(void) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_I2S: - if (node_or_instance < I2S_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_I2S; - clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_EWDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_EWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); - } - break; - case CLK_SRC_GROUP_PEWDG: - clk_src_group = CLK_SRC_GROUP_PEWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_AXI_SOC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axis]); - break; - case CLK_SRC_GROUP_AXI_VIDEO: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axiv]); - break; - case CLK_SRC_GROUP_AXI_FAST: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axif]); - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -uint32_t clock_get_divider(clock_name_t clock_name) -{ - uint32_t clk_divider = CLOCK_DIV_INVALID; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_EWDG: - if (node_or_instance < WDG_INSTANCE_NUM) { - clk_divider = 1UL; - } - break; - case CLK_SRC_GROUP_PEWDG: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_PMIC: - clk_divider = 1UL; - break; - case CLK_SRC_GROUP_AXI_SOC: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axis]); - break; - case CLK_SRC_GROUP_AXI_VIDEO: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axiv]); - break; - case CLK_SRC_GROUP_AXI_FAST: - clk_divider = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[(uint32_t) clock_node_axif]); - break; - default: - clk_divider = CLOCK_DIV_INVALID; - break; - } - return clk_divider; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_i2s_src_aud0) || (src > clk_i2s_src_audx)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->I2SCLK[node_or_instance] = - (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_EWDG) && (clk_src_grp != CLK_SRC_GROUP_PEWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t clk_src = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, clk_src, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_I2S: - case CLK_SRC_GROUP_EWDG: - case CLK_SRC_GROUP_PEWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AXI_FAST: - status = status_clk_shared_axif; - break; - case CLK_SRC_GROUP_AXI_VIDEO: - status = status_clk_shared_axiv; - break; - case CLK_SRC_GROUP_AXI_SOC: - status = status_clk_shared_axis; - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - bool added = false; - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); - } - - return added; -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 1U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 1U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -static uint64_t get_core_mcycle(void) -{ - uint64_t result; - uint32_t resultl_first = read_csr(CSR_MCYCLE); - uint32_t resulth = read_csr(CSR_MCYCLEH); - uint32_t resultl_second = read_csr(CSR_MCYCLE); - if (resultl_first < resultl_second) { - result = ((uint64_t)resulth << 32) | resultl_first; /* if MCYCLE didn't roll over, return the value directly */ - } else { - resulth = read_csr(CSR_MCYCLEH); - result = ((uint64_t)resulth << 32) | resultl_second; /* if MCYCLE rolled over, need to get the MCYCLEH again */ - } - return result; - } - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ - uint64_t expected_ticks = get_core_mcycle() + ticks_per_us * us; - while (get_core_mcycle() < expected_ticks) { - } - write_csr(CSR_MCOUNTEREN, mcounteren); /* Restore MCOUNTEREN */ -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ - uint64_t expected_ticks = get_core_mcycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (get_core_mcycle() < expected_ticks) { - } - write_csr(CSR_MCOUNTEREN, mcounteren); /* Restore MCOUNTEREN */ -} - -void clock_update_core_clock(void) -{ - clock_name_t cpu_clk_name = clock_cpu0; - hpm_core_clock = clock_get_frequency(cpu_clk_name); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_clock_drv.h deleted file mode 100644 index 2621838f9eb..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_clock_drv.h +++ /dev/null @@ -1,411 +0,0 @@ -/* - * Copyright (c) 2022-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" -#include "hpm_csr_drv.h" - -#define CLOCK_DIV_INVALID (~0UL) - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), - status_clk_shared_axis = MAKE_STATUS(status_group_clk, 5), - status_clk_shared_axic = MAKE_STATUS(status_group_clk, 6), - status_clk_shared_axiv = MAKE_STATUS(status_group_clk, 7), - status_clk_shared_axif = MAKE_STATUS(status_group_clk, 8), - status_clk_shared_axid = MAKE_STATUS(status_group_clk, 9), - status_clk_fixed = MAKE_STATUS(status_group_clk, 10), - -}; - - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_I2S (2U) -#define CLK_SRC_GROUP_EWDG (3U) -#define CLK_SRC_GROUP_PEWDG (4U) -#define CLK_SRC_GROUP_PMIC (5U) -#define CLK_SRC_GROUP_AXI_SOC (6U) -#define CLK_SRC_GROUP_AXI_FAST (7U) -#define CLK_SRC_GROUP_AXI_VIDEO (8U) -#define CLK_SRC_GROUP_SRC (9U) -#define CLK_SRC_GROUP_INVALID (15U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src) >> 4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll3_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll4_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - - clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_aud2 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_aud3 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_audx = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - - -#define RESOURCE_INVALID (0xFFFFU) -#define RESOURCE_SHARED_AXI_SOC (0xFFFEU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_axif = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_axif), - clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_COMMON, clock_node_axis), - clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_COMMON, clock_node_axic), - clock_axiv = MAKE_CLOCK_NAME(sysctl_resource_axiv, CLK_SRC_GROUP_COMMON, clock_node_axiv), - clock_axig = MAKE_CLOCK_NAME(sysctl_resource_axig, CLK_SRC_GROUP_COMMON, clock_node_gpu0), - clock_axid = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_axid), - - /* Software definition for compatibility */ - clock_ahb = MAKE_CLOCK_NAME(RESOURCE_SHARED_AXI_SOC, CLK_SRC_GROUP_AXI_SOC, clock_node_axis), - - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_COMMON, clock_node_cpu0), - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_gpu0 = MAKE_CLOCK_NAME(sysctl_resource_gpu0, CLK_SRC_GROUP_COMMON, clock_node_gpu0), - - clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), - clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), - clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), - clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), - clock_can4 = MAKE_CLOCK_NAME(sysctl_resource_can4, CLK_SRC_GROUP_COMMON, clock_node_can4), - clock_can5 = MAKE_CLOCK_NAME(sysctl_resource_can5, CLK_SRC_GROUP_COMMON, clock_node_can5), - clock_can6 = MAKE_CLOCK_NAME(sysctl_resource_can6, CLK_SRC_GROUP_COMMON, clock_node_can6), - clock_can7 = MAKE_CLOCK_NAME(sysctl_resource_can7, CLK_SRC_GROUP_COMMON, clock_node_can7), - - clock_lin0 = MAKE_CLOCK_NAME(sysctl_resource_lin0, CLK_SRC_GROUP_COMMON, clock_node_lin0), - clock_lin1 = MAKE_CLOCK_NAME(sysctl_resource_lin1, CLK_SRC_GROUP_COMMON, clock_node_lin1), - clock_lin2 = MAKE_CLOCK_NAME(sysctl_resource_lin2, CLK_SRC_GROUP_COMMON, clock_node_lin2), - clock_lin3 = MAKE_CLOCK_NAME(sysctl_resource_lin3, CLK_SRC_GROUP_COMMON, clock_node_lin3), - clock_lin4 = MAKE_CLOCK_NAME(sysctl_resource_lin4, CLK_SRC_GROUP_COMMON, clock_node_lin4), - clock_lin5 = MAKE_CLOCK_NAME(sysctl_resource_lin5, CLK_SRC_GROUP_COMMON, clock_node_lin5), - clock_lin6 = MAKE_CLOCK_NAME(sysctl_resource_lin6, CLK_SRC_GROUP_COMMON, clock_node_lin6), - clock_lin7 = MAKE_CLOCK_NAME(sysctl_resource_lin7, CLK_SRC_GROUP_COMMON, clock_node_lin7), - - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), - clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), - clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), - - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), - clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), - clock_gptmr4 = MAKE_CLOCK_NAME(sysctl_resource_gptmr4, CLK_SRC_GROUP_COMMON, clock_node_gptmr4), - clock_gptmr5 = MAKE_CLOCK_NAME(sysctl_resource_gptmr5, CLK_SRC_GROUP_COMMON, clock_node_gptmr5), - clock_gptmr6 = MAKE_CLOCK_NAME(sysctl_resource_gptmr6, CLK_SRC_GROUP_COMMON, clock_node_gptmr6), - clock_gptmr7 = MAKE_CLOCK_NAME(sysctl_resource_gptmr7, CLK_SRC_GROUP_COMMON, clock_node_gptmr7), - - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - - clock_xram = MAKE_CLOCK_NAME(sysctl_resource_xram, CLK_SRC_GROUP_COMMON, clock_node_xram), - clock_ddr0 = MAKE_CLOCK_NAME(sysctl_resource_ddr0, CLK_SRC_GROUP_AXI_FAST, clock_node_axif), - - clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), - - clock_ptp0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ptp0), - - clock_sdxc0 = MAKE_CLOCK_NAME(sysctl_resource_sdc0, CLK_SRC_GROUP_COMMON, clock_node_sdc0), - clock_sdxc1 = MAKE_CLOCK_NAME(sysctl_resource_sdc1, CLK_SRC_GROUP_COMMON, clock_node_sdc1), - - clock_ntm0 = MAKE_CLOCK_NAME(sysctl_resource_ntm0, CLK_SRC_GROUP_COMMON, clock_node_ntm0), - - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - - clock_cam0 = MAKE_CLOCK_NAME(sysctl_resource_cam0, CLK_SRC_GROUP_COMMON, clock_node_cam0), - clock_cam1 = MAKE_CLOCK_NAME(sysctl_resource_cam1, CLK_SRC_GROUP_COMMON, clock_node_cam1), - - clock_lcd0 = MAKE_CLOCK_NAME(sysctl_resource_lcd0, CLK_SRC_GROUP_COMMON, clock_node_lcd0), - clock_lcd1 = MAKE_CLOCK_NAME(sysctl_resource_lcd1, CLK_SRC_GROUP_COMMON, clock_node_lcd1), - - clock_csi0 = MAKE_CLOCK_NAME(sysctl_resource_csi0, CLK_SRC_GROUP_COMMON, clock_node_csi0), - clock_csi1 = MAKE_CLOCK_NAME(sysctl_resource_csi1, CLK_SRC_GROUP_COMMON, clock_node_csi1), - clock_dsi0 = MAKE_CLOCK_NAME(sysctl_resource_dsi0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - clock_dsi1 = MAKE_CLOCK_NAME(sysctl_resource_dsi1, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - - clock_gwc0 = MAKE_CLOCK_NAME(sysctl_resource_gwc0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - clock_gwc1 = MAKE_CLOCK_NAME(sysctl_resource_gwc1, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - - clock_lvb = MAKE_CLOCK_NAME(sysctl_resource_lvb0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - clock_lcb = MAKE_CLOCK_NAME(sysctl_resource_lcb0, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - - clock_ffa = MAKE_CLOCK_NAME(sysctl_resource_ffa0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_PMIC, clock_node_invalid), - - clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), /* 0 - instance */ - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), /* 1 - instance */ - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, clock_node_invalid), - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, clock_node_invalid), - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, clock_node_invalid), - clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_dma1, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_rom = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_jpeg = MAKE_CLOCK_NAME(sysctl_resource_jpeg, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - clock_pdma = MAKE_CLOCK_NAME(sysctl_resource_pdma, CLK_SRC_GROUP_AXI_VIDEO, clock_node_invalid), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_dma0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_pdm0, CLK_SRC_GROUP_I2S, clock_node_invalid), - clock_dao = MAKE_CLOCK_NAME(sysctl_resource_dao0, CLK_SRC_GROUP_I2S, clock_node_invalid), - clock_smix = MAKE_CLOCK_NAME(sysctl_resource_smix, CLK_SRC_GROUP_I2S, clock_node_invalid), - - /* For ADC, there are 2-stage clock source and divider configuration */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), /* 0 - instance */ - clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), /* 1 - instance */ - - clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AXI_SOC, clock_node_invalid), - - /* For I2S, there are 2-stage clock source and divider configuration */ - clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), - clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), - clock_aud2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud2), - clock_aud3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud3), - clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), /* 0 - instance */ - clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), /* 1 - instance */ - clock_i2s2 = MAKE_CLOCK_NAME(sysctl_resource_i2s2, CLK_SRC_GROUP_I2S, 2), /* 2 - instance */ - clock_i2s3 = MAKE_CLOCK_NAME(sysctl_resource_i2s3, CLK_SRC_GROUP_I2S, 3), /* 3 - instance */ - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 2), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 3), - clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 4), - clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 5), - clk_pll3clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll3, CLK_SRC_GROUP_SRC, 6), - clk_pll4clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll4, CLK_SRC_GROUP_SRC, 7), - -} clock_name_t; - -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @param [in] clock_name clock name - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Get the IP clock divider - * Note:This API return the direct clock divider - * @param [in] clock_name clock name - * @return IP clock divider - */ -uint32_t clock_get_divider(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @return #status_success Setting ADC clock source is successful - * #status_clk_invalid Invalid ADC clock - * #status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set I2S clock source - * @param[in] clock_name I2S clock name - * @param[in] src I2S clock source - * - * @return #status_success Setting DAC clock source is successful - * #status_clk_invalid Invalid DAC clock - * #status_clk_src_invalid Invalid DAC clock source - */ -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @return #status_success Setting Clock source and divider is successful. - * #status_clk_src_invalid clock source is invalid. - * #status_clk_fixed clock source and divider is a fixed value - * #status_clk_shared_ahb Clock is shared with the AHB clock - * #status_clk_shared_axis Clock is shared with the AXI_SOC clock - * #status_clk_shared_axic CLock is shared with the AXI_CONNECTIVITY clock - * #status_clk_shared_axiv Clock is shared with the AXI_VIDEO clock - * #status_clk_shared_axif Clock is shared with the AXI_FAST clock - * #status_clk_shared_axid Clock is shared with the AXI_DISPLAY clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_csr_regs.h deleted file mode 100644 index 5f43b12bd1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_csr_regs.h +++ /dev/null @@ -1,6512 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_SSTATUS (0x100) -#define CSR_SEDELEG (0x102) -#define CSR_SIDELEG (0x103) -#define CSR_SIE (0x104) -#define CSR_STVEC (0x105) -#define CSR_SSCRATCH (0x140) -#define CSR_SEPC (0x141) -#define CSR_SCAUSE (0x142) -#define CSR_STVAL (0x143) -#define CSR_SIP (0x144) -#define CSR_SATP (0x180) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MEDELEG (0x302) -#define CSR_MIDELEG (0x303) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_PMACFG0 (0xBC0) -#define CSR_PMACFG1 (0xBC1) -#define CSR_PMACFG2 (0xBC2) -#define CSR_PMACFG3 (0xBC3) -#define CSR_PMAADDR0 (0xBD0) -#define CSR_PMAADDR1 (0xBD1) -#define CSR_PMAADDR2 (0xBD2) -#define CSR_PMAADDR3 (0xBD3) -#define CSR_PMAADDR4 (0xBD4) -#define CSR_PMAADDR5 (0xBD5) -#define CSR_PMAADDR6 (0xBD6) -#define CSR_PMAADDR7 (0xBD7) -#define CSR_PMAADDR8 (0xBD8) -#define CSR_PMAADDR9 (0xBD9) -#define CSR_PMAADDR10 (0xBDA) -#define CSR_PMAADDR11 (0xBDB) -#define CSR_PMAADDR12 (0xBDC) -#define CSR_PMAADDR13 (0xBDD) -#define CSR_PMAADDR14 (0xBDE) -#define CSR_PMAADDR15 (0xBDF) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_SCOUNTEREN (0x106) -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_MSLIDELEG (0x7D5) -#define CSR_MCLK_CTL (0x7DF) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_SLIE (0x9C4) -#define CSR_SLIP (0x9C5) -#define CSR_SDCAUSE (0x9C9) -#define CSR_SCCTLDATA (0x9CD) -#define CSR_SCOUNTERINTEN (0x9CF) -#define CSR_SCOUNTERMASK_M (0x9D1) -#define CSR_SCOUNTERMASK_S (0x9D2) -#define CSR_SCOUNTERMASK_U (0x9D3) -#define CSR_SCOUNTEROVF (0x9D4) -#define CSR_SCOUNTINHIBIT (0x9E0) -#define CSR_SHPMEVENT3 (0x9E3) -#define CSR_SHPMEVENT4 (0x9E4) -#define CSR_SHPMEVENT5 (0x9E5) -#define CSR_SHPMEVENT6 (0x9E6) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: SSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_SSTATUS_SD_MASK (0x80000000UL) -#define CSR_SSTATUS_SD_SHIFT (31U) -#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_SSTATUS_MXR_MASK (0x80000UL) -#define CSR_SSTATUS_MXR_SHIFT (19U) -#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) -#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_SSTATUS_SUM_MASK (0x40000UL) -#define CSR_SSTATUS_SUM_SHIFT (18U) -#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) -#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggeredwhen XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. - * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_XS_MASK (0x18000UL) -#define CSR_SSTATUS_XS_SHIFT (15U) -#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. - * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_FS_MASK (0x6000U) -#define CSR_SSTATUS_FS_SHIFT (13U) -#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) -#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_SSTATUS_SPP_MASK (0x100U) -#define CSR_SSTATUS_SPP_SHIFT (8U) -#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) -#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_SSTATUS_SPIE_MASK (0x20U) -#define CSR_SSTATUS_SPIE_SHIFT (5U) -#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) -#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_SSTATUS_UPIE_MASK (0x10U) -#define CSR_SSTATUS_UPIE_SHIFT (4U) -#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) -#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_SIE_MASK (0x2U) -#define CSR_SSTATUS_SIE_SHIFT (1U) -#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) -#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_UIE_MASK (0x1U) -#define CSR_SSTATUS_UIE_SHIFT (0U) -#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) -#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: SEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SPF_MASK (0x8000U) -#define CSR_SEDELEG_SPF_SHIFT (15U) -#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) -#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LPF_MASK (0x2000U) -#define CSR_SEDELEG_LPF_SHIFT (13U) -#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) -#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IPF_MASK (0x1000U) -#define CSR_SEDELEG_IPF_SHIFT (12U) -#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) -#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_UEC_MASK (0x100U) -#define CSR_SEDELEG_UEC_SHIFT (8U) -#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) -#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAF_MASK (0x80U) -#define CSR_SEDELEG_SAF_SHIFT (7U) -#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) -#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAM_MASK (0x40U) -#define CSR_SEDELEG_SAM_SHIFT (6U) -#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) -#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAF_MASK (0x20U) -#define CSR_SEDELEG_LAF_SHIFT (5U) -#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) -#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAM_MASK (0x10U) -#define CSR_SEDELEG_LAM_SHIFT (4U) -#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) -#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) - -/* - * B (RW) - * - * B indicates whether an exception triggered by breakpoint will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_B_MASK (0x8U) -#define CSR_SEDELEG_B_SHIFT (3U) -#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) -#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_II_MASK (0x4U) -#define CSR_SEDELEG_II_SHIFT (2U) -#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) -#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAF_MASK (0x2U) -#define CSR_SEDELEG_IAF_SHIFT (1U) -#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) -#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAM_MASK (0x1U) -#define CSR_SEDELEG_IAM_SHIFT (0U) -#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) -#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: SIDELEG */ -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UEI_MASK (0x100U) -#define CSR_SIDELEG_UEI_SHIFT (8U) -#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) -#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UTI_MASK (0x10U) -#define CSR_SIDELEG_UTI_SHIFT (4U) -#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) -#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_USI_MASK (0x1U) -#define CSR_SIDELEG_USI_SHIFT (0U) -#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) -#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) - -/* Bitfield definition for register: SIE */ -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SEIE_MASK (0x200U) -#define CSR_SIE_SEIE_SHIFT (9U) -#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) -#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UEIE_MASK (0x100U) -#define CSR_SIE_UEIE_SHIFT (8U) -#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) -#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_STIE_MASK (0x20U) -#define CSR_SIE_STIE_SHIFT (5U) -#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) -#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UTIE_MASK (0x10U) -#define CSR_SIE_UTIE_SHIFT (4U) -#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) -#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SSIE_MASK (0x2U) -#define CSR_SIE_SSIE_SHIFT (1U) -#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) -#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_USIE_MASK (0x1U) -#define CSR_SIE_USIE_SHIFT (0U) -#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) -#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) - -/* Bitfield definition for register: STVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_STVEC_BASE_31_2_SHIFT (2U) -#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) -#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: SSCRATCH */ -/* - * SSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) -#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) -#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) - -/* Bitfield definition for register: SEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_SEPC_EPC_SHIFT (1U) -#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) -#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) - -/* Bitfield definition for register: SCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) -#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 256+16:Slave port ECC error interrupt (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt(S-mode) - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:10:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) -#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: STVAL */ -/* - * STVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) -#define CSR_STVAL_STVAL_SHIFT (0U) -#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) -#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) - -/* Bitfield definition for register: SIP */ -/* - * SEIP (RO) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SEIP_MASK (0x200U) -#define CSR_SIP_SEIP_SHIFT (9U) -#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UEIP_MASK (0x100U) -#define CSR_SIP_UEIP_SHIFT (8U) -#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) -#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) - -/* - * STIP (RO) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_STIP_MASK (0x20U) -#define CSR_SIP_STIP_SHIFT (5U) -#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) - -/* - * UTIP (RO) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UTIP_MASK (0x10U) -#define CSR_SIP_UTIP_SHIFT (4U) -#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SSIP_MASK (0x2U) -#define CSR_SIP_SSIP_SHIFT (1U) -#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) -#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_USIP_MASK (0x1U) -#define CSR_SIP_USIP_SHIFT (0U) -#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) -#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) - -/* Bitfield definition for register: SATP */ -/* - * MODE (RW) - * - * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is - * not supported in the product, this CSR will be - * hardwired to 0. - * 0:No page translation - * 1:Page-based 32-bit virtual addressing - */ -#define CSR_SATP_MODE_MASK (0x80000000UL) -#define CSR_SATP_MODE_SHIFT (31U) -#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) -#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) - -/* - * ASID (RW) - * - * ASID holds the address space identifier. - */ -#define CSR_SATP_ASID_MASK (0x7FC00000UL) -#define CSR_SATP_ASID_SHIFT (22U) -#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) -#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) - -/* - * PPN (RW) - * - * PPN holds the physical page number of the root page table. - */ -#define CSR_SATP_PPN_MASK (0x3FFFFFUL) -#define CSR_SATP_PPN_SHIFT (0U) -#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) -#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * TSR (RW) - * - * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TSR_MASK (0x400000UL) -#define CSR_MSTATUS_TSR_SHIFT (22U) -#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) -#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) - -/* - * TW (RW) - * - * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TW_MASK (0x200000UL) -#define CSR_MSTATUS_TW_SHIFT (21U) -#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) -#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) - -/* - * TVM (RW) - * - * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. - * 0:Normal execution - * 1:Raising exceptions - */ -#define CSR_MSTATUS_TVM_MASK (0x100000UL) -#define CSR_MSTATUS_TVM_SHIFT (20U) -#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) -#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_MSTATUS_SUM_MASK (0x40000UL) -#define CSR_MSTATUS_SUM_SHIFT (18U) -#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) -#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_MSTATUS_SPP_MASK (0x100U) -#define CSR_MSTATUS_SPP_SHIFT (8U) -#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) -#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_MSTATUS_SPIE_MASK (0x20U) -#define CSR_MSTATUS_SPIE_SHIFT (5U) -#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) -#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_SIE_MASK (0x2U) -#define CSR_MSTATUS_SIE_SHIFT (1U) -#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) -#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SPF_MASK (0x8000U) -#define CSR_MEDELEG_SPF_SHIFT (15U) -#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) -#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LPF_MASK (0x2000U) -#define CSR_MEDELEG_LPF_SHIFT (13U) -#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) -#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IPF_MASK (0x1000U) -#define CSR_MEDELEG_IPF_SHIFT (12U) -#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) -#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) - -/* - * SEC (RW) - * - * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SEC_MASK (0x200U) -#define CSR_MEDELEG_SEC_SHIFT (9U) -#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) -#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_UEC_MASK (0x100U) -#define CSR_MEDELEG_UEC_SHIFT (8U) -#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) -#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAF_MASK (0x80U) -#define CSR_MEDELEG_SAF_SHIFT (7U) -#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) -#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAM_MASK (0x40U) -#define CSR_MEDELEG_SAM_SHIFT (6U) -#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) -#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAF_MASK (0x20U) -#define CSR_MEDELEG_LAF_SHIFT (5U) -#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) -#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAM_MASK (0x10U) -#define CSR_MEDELEG_LAM_SHIFT (4U) -#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) -#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_II_MASK (0x4U) -#define CSR_MEDELEG_II_SHIFT (2U) -#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) -#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAF_MASK (0x2U) -#define CSR_MEDELEG_IAF_SHIFT (1U) -#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) -#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAM_MASK (0x1U) -#define CSR_MEDELEG_IAM_SHIFT (0U) -#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) -#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: MIDELEG */ -/* - * SEI (RW) - * - * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SEI_MASK (0x200U) -#define CSR_MIDELEG_SEI_SHIFT (9U) -#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) -#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) - -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UEI_MASK (0x100U) -#define CSR_MIDELEG_UEI_SHIFT (8U) -#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) -#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) - -/* - * STI (RW) - * - * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_STI_MASK (0x20U) -#define CSR_MIDELEG_STI_SHIFT (5U) -#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) -#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UTI_MASK (0x10U) -#define CSR_MIDELEG_UTI_SHIFT (4U) -#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) -#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) - -/* - * SSI (RW) - * - * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SSI_MASK (0x2U) -#define CSR_MIDELEG_SSI_SHIFT (1U) -#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) -#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_USI_MASK (0x1U) -#define CSR_MIDELEG_USI_SHIFT (0U) -#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) -#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SEIE_MASK (0x200U) -#define CSR_MIE_SEIE_SHIFT (9U) -#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) -#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_STIE_MASK (0x20U) -#define CSR_MIE_STIE_SHIFT (5U) -#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) -#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SSIE_MASK (0x2U) -#define CSR_MIE_SSIE_SHIFT (1U) -#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) -#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_MCONTROL_S_MASK (0x10U) -#define CSR_MCONTROL_S_SHIFT (4U) -#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) -#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ICOUNT_S_MASK (0x80U) -#define CSR_ICOUNT_S_SHIFT (7U) -#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) -#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ITRIGGER_S_MASK (0x80U) -#define CSR_ITRIGGER_S_SHIFT (7U) -#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) -#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ETRIGGER_S_MASK (0x80U) -#define CSR_ETRIGGER_S_SHIFT (7U) -#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) -#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKS (RW) - * - * This bit controls the behavior of EBREAK instructions in Supervisor Mode. - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKS_MASK (0x2000U) -#define CSR_DCSR_EBREAKS_SHIFT (13U) -#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) -#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: PMACFG0 */ -/* - * PMA3CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) -#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) -#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) -#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) - -/* - * PMA2CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) -#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) -#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) -#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) - -/* - * PMA1CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) -#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) -#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) -#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) - -/* - * PMA0CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) -#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) -#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) -#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) - -/* Bitfield definition for register: PMACFG1 */ -/* - * PMA7CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) -#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) -#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) -#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) - -/* - * PMA6CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) -#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) -#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) -#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) - -/* - * PMA5CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) -#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) -#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) -#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) - -/* - * PMA4CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) -#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) -#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) -#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) - -/* Bitfield definition for register: PMACFG2 */ -/* - * PMA11CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) -#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) -#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) -#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) - -/* - * PMA10CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) -#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) -#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) -#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) - -/* - * PMA9CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) -#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) -#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) -#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) - -/* - * PMA8CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) -#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) -#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) -#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) - -/* Bitfield definition for register: PMACFG3 */ -/* - * PMA15CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) -#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) -#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) -#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) - -/* - * PMA14CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) -#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) -#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) -#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) - -/* - * PMA13CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) -#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) -#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) -#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) - -/* - * PMA12CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) -#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) -#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) -#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaaaaaaaaaa Reserved - * . . . . . . - * aaaa. . . aa011111111 Reserved - * aaaa. . . a0111111111 2^{12} - * aaaa. . . 01111111111 2^{13} - * . . . . . . - * aa01. . . 11111111111 2^{XLEN} - * a011. . . 11111111111 2^{XLEN+1} - * 0111. . . 11111111111 2^{XLEN+2} - * 1111. . . 11111111111 Reserved - */ -#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) -#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) -#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) -#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) -#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) -#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) -#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) -#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) -#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) -#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) -#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) -#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) -#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) -#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) -#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) -#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) -#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: SCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) -#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) -#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) -#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) -#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_IR_MASK (0x4U) -#define CSR_SCOUNTEREN_IR_SHIFT (2U) -#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) -#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_CY_MASK (0x1U) -#define CSR_SCOUNTEREN_CY_SHIFT (0U) -#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) -#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * PM (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MDCAUSE_PM_MASK (0x60U) -#define CSR_MDCAUSE_PM_SHIFT (5U) -#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) -#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) - -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * DC_WAROUND (RW) - * - * Cache Write-Around threshold - * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. - * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. - * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. - * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. - */ -#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) -#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) -#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) -#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) - -/* - * DC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) - -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * DPREF_EN (RW) - * - * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 - * 0:Disable hardware prefetch on load/store memory accesses - * 1:Enable hardware prefetch on load/store memory accesses - */ -#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) -#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) -#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) -#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) - -/* - * IPREF_EN (RW) - * - * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 - * 0:Disable hardware prefetch on instruction fetches - * 1:Enable hardware prefetch on instruction fetches - */ -#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) -#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) -#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) -#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * NBLD_EN (RW) - * - * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. - * 0:Load to memory regions are blocking. - * 1:Load to memory regions are non-blocking. - */ -#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) -#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) -#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) -#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) - -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: MSLIDELEG */ -/* - * PMOVI (RW) - * - * Delegate S-mode performance monitor overflow local interrupt to S-mode. - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) -#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) -#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) -#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Delegate S-mode bus read/write transaction error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) -#define CSR_MSLIDELEG_BWEI_SHIFT (17U) -#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) -#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Delegate S-mode slave-port ECC error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) -#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) -#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) -#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) - -/* Bitfield definition for register: MCLK_CTL */ -/* - * FUNIT (RW) - * - * Level 2 clock gating enable for function units listed in the following table. - * 16:integer arithmetic unit - * 17:integer permutation unit - * 18:integer mask unit - * 19:integer division unit - * 20:integer multiply and add unit - * 21:floating-point multiply and add - * unit - * 22:floating-point miscellaneous unit - * 23:floating-point division unit - * 24:load/store unit - * 31:25:Reserved - */ -#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) -#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) -#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) -#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) - -/* - * VI (RW) - * - * Level 1 clock gating enable for the vector/floating-point issue queues. - */ -#define CSR_MCLK_CTL_VI_MASK (0x8000U) -#define CSR_MCLK_CTL_VI_SHIFT (15U) -#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) -#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) - -/* - * VR (RW) - * - * Level 1 clock gating enable for the vector/floating-point register file. - */ -#define CSR_MCLK_CTL_VR_MASK (0x4000U) -#define CSR_MCLK_CTL_VR_SHIFT (14U) -#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) -#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) - -/* - * AQ (RW) - * - * Level 1 clock gating enable for ACE load/store queues. - */ -#define CSR_MCLK_CTL_AQ_MASK (0x2000U) -#define CSR_MCLK_CTL_AQ_SHIFT (13U) -#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) -#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) - -/* - * DQ (RW) - * - * Level 1 clock gating enable for data cache load/store queues. - */ -#define CSR_MCLK_CTL_DQ_MASK (0x1000U) -#define CSR_MCLK_CTL_DQ_SHIFT (12U) -#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) -#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) - -/* - * UQ (RW) - * - * Level 1 clock gating enable for uncached queues - */ -#define CSR_MCLK_CTL_UQ_MASK (0x800U) -#define CSR_MCLK_CTL_UQ_SHIFT (11U) -#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) -#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) - -/* - * FP (RW) - * - * Level 1 clock gating enable for scalar floating point issue unit and queues. - */ -#define CSR_MCLK_CTL_FP_MASK (0x400U) -#define CSR_MCLK_CTL_FP_SHIFT (10U) -#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) -#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) - -/* - * CLKGATE (RW) - * - * One-hot clock gating levels. - * 0:Level 1 clock gating in module level - * 1:Level 2 clock gating in unit level - * 2:Level 3 clock gating in VPU level - * 7:3:Reserved - */ -#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) -#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) -#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) -#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * SPF (RW) - * - * Indicates whether store page fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) -#define CSR_DEXC2DBG_SPF_SHIFT (18U) -#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) -#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) - -/* - * LPF (RW) - * - * Indicates whether load fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) -#define CSR_DEXC2DBG_LPF_SHIFT (17U) -#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) -#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) - -/* - * IPF (RW) - * - * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) -#define CSR_DEXC2DBG_IPF_SHIFT (16U) -#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) -#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * SEC (RW) - * - * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SEC_MASK (0x200U) -#define CSR_DEXC2DBG_SEC_SHIFT (9U) -#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) -#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: SLIE */ -/* - * PMOVI (RW) - * - * Enable S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_PMOVI_MASK (0x40000UL) -#define CSR_SLIE_PMOVI_SHIFT (18U) -#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) -#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_BWEI_MASK (0x20000UL) -#define CSR_SLIE_BWEI_SHIFT (17U) -#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) -#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Enable S-mode slave-port ECC error local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_IMECCI_MASK (0x10000UL) -#define CSR_SLIE_IMECCI_SHIFT (16U) -#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) -#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) - -/* Bitfield definition for register: SLIP */ -/* - * PMOVI (RW) - * - * Pending control and status of S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_PMOVI_MASK (0x40000UL) -#define CSR_SLIP_PMOVI_SHIFT (18U) -#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) -#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_BWEI_MASK (0x20000UL) -#define CSR_SLIP_BWEI_SHIFT (17U) -#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) -#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Pending control and status of S-mode slave-port ECC error local interrupt.. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_IMECCI_MASK (0x10000UL) -#define CSR_SLIP_IMECCI_SHIFT (16U) -#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) -#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) - -/* Bitfield definition for register: SDCAUSE */ -/* - * PM (RW) - * - * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0:User mode - * 1:Supervisor mode - * 2:Reserved - * 3:Machine mode - */ -#define CSR_SDCAUSE_PM_MASK (0x60U) -#define CSR_SDCAUSE_PM_SHIFT (5U) -#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) -#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) - -/* - * SDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. - * The value of SDCAUSE for precise exception: - * When scause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When scause == 2 (Illegal instruction): - * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When scause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When scause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of SDCAUSE for imprecise exception: - * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) -#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) -#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) -#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) - -/* Bitfield definition for register: SCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_SCCTLDATA_VA_MASK (0x1FU) -#define CSR_SCCTLDATA_VA_SHIFT (0U) -#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) -#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: SCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) -#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) -#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) -#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) -#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) -#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) -#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) -#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) -#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) -#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) -#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) -#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) -#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) -#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) -#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) -#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) -#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) -#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) -#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) -#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) -#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) -#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) -#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) -#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) -#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) -#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) -#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) -#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) -#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_IR_MASK (0x4U) -#define CSR_SCOUNTEROVF_IR_SHIFT (2U) -#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) -#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_CY_MASK (0x1U) -#define CSR_SCOUNTEROVF_CY_SHIFT (0U) -#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) -#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) -#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) -#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) -#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) -#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) -#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) -#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) -#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: SHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT3_SEL_SHIFT (4U) -#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) -#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) -#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT4_SEL_SHIFT (4U) -#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) -#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) -#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT5_SEL_SHIFT (4U) -#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) -#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) -#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT6_SEL_SHIFT (4U) -#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) -#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) -#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_dmamux_src.h deleted file mode 100644 index c6128331b47..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_dmamux_src.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_SPI0_RX (0x0UL) -#define HPM_DMA_SRC_SPI0_TX (0x1UL) -#define HPM_DMA_SRC_SPI1_RX (0x2UL) -#define HPM_DMA_SRC_SPI1_TX (0x3UL) -#define HPM_DMA_SRC_SPI2_RX (0x4UL) -#define HPM_DMA_SRC_SPI2_TX (0x5UL) -#define HPM_DMA_SRC_SPI3_RX (0x6UL) -#define HPM_DMA_SRC_SPI3_TX (0x7UL) -#define HPM_DMA_SRC_UART0_RX (0x8UL) -#define HPM_DMA_SRC_UART0_TX (0x9UL) -#define HPM_DMA_SRC_UART1_RX (0xAUL) -#define HPM_DMA_SRC_UART1_TX (0xBUL) -#define HPM_DMA_SRC_UART2_RX (0xCUL) -#define HPM_DMA_SRC_UART2_TX (0xDUL) -#define HPM_DMA_SRC_UART3_RX (0xEUL) -#define HPM_DMA_SRC_UART3_TX (0xFUL) -#define HPM_DMA_SRC_UART4_RX (0x10UL) -#define HPM_DMA_SRC_UART4_TX (0x11UL) -#define HPM_DMA_SRC_UART5_RX (0x12UL) -#define HPM_DMA_SRC_UART5_TX (0x13UL) -#define HPM_DMA_SRC_UART6_RX (0x14UL) -#define HPM_DMA_SRC_UART6_TX (0x15UL) -#define HPM_DMA_SRC_UART7_RX (0x16UL) -#define HPM_DMA_SRC_UART7_TX (0x17UL) -#define HPM_DMA_SRC_MCAN0 (0x18UL) -#define HPM_DMA_SRC_MCAN1 (0x19UL) -#define HPM_DMA_SRC_MCAN2 (0x1AUL) -#define HPM_DMA_SRC_MCAN3 (0x1BUL) -#define HPM_DMA_SRC_MCAN4 (0x1CUL) -#define HPM_DMA_SRC_MCAN5 (0x1DUL) -#define HPM_DMA_SRC_MCAN6 (0x1EUL) -#define HPM_DMA_SRC_MCAN7 (0x1FUL) -#define HPM_DMA_SRC_I2S0_RX (0x20UL) -#define HPM_DMA_SRC_I2S0_TX (0x21UL) -#define HPM_DMA_SRC_I2S1_RX (0x22UL) -#define HPM_DMA_SRC_I2S1_TX (0x23UL) -#define HPM_DMA_SRC_I2S2_RX (0x24UL) -#define HPM_DMA_SRC_I2S2_TX (0x25UL) -#define HPM_DMA_SRC_I2S3_RX (0x26UL) -#define HPM_DMA_SRC_I2S3_TX (0x27UL) -#define HPM_DMA_SRC_GPTMR0_0 (0x28UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x29UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x2AUL) -#define HPM_DMA_SRC_GPTMR0_3 (0x2BUL) -#define HPM_DMA_SRC_GPTMR1_0 (0x2CUL) -#define HPM_DMA_SRC_GPTMR1_1 (0x2DUL) -#define HPM_DMA_SRC_GPTMR1_2 (0x2EUL) -#define HPM_DMA_SRC_GPTMR1_3 (0x2FUL) -#define HPM_DMA_SRC_GPTMR2_0 (0x30UL) -#define HPM_DMA_SRC_GPTMR2_1 (0x31UL) -#define HPM_DMA_SRC_GPTMR2_2 (0x32UL) -#define HPM_DMA_SRC_GPTMR2_3 (0x33UL) -#define HPM_DMA_SRC_GPTMR3_0 (0x34UL) -#define HPM_DMA_SRC_GPTMR3_1 (0x35UL) -#define HPM_DMA_SRC_GPTMR3_2 (0x36UL) -#define HPM_DMA_SRC_GPTMR3_3 (0x37UL) -#define HPM_DMA_SRC_GPTMR4_0 (0x38UL) -#define HPM_DMA_SRC_GPTMR4_1 (0x39UL) -#define HPM_DMA_SRC_GPTMR4_2 (0x3AUL) -#define HPM_DMA_SRC_GPTMR4_3 (0x3BUL) -#define HPM_DMA_SRC_GPTMR5_0 (0x3CUL) -#define HPM_DMA_SRC_GPTMR5_1 (0x3DUL) -#define HPM_DMA_SRC_GPTMR5_2 (0x3EUL) -#define HPM_DMA_SRC_GPTMR5_3 (0x3FUL) -#define HPM_DMA_SRC_GPTMR6_0 (0x40UL) -#define HPM_DMA_SRC_GPTMR6_1 (0x41UL) -#define HPM_DMA_SRC_GPTMR6_2 (0x42UL) -#define HPM_DMA_SRC_GPTMR6_3 (0x43UL) -#define HPM_DMA_SRC_GPTMR7_0 (0x44UL) -#define HPM_DMA_SRC_GPTMR7_1 (0x45UL) -#define HPM_DMA_SRC_GPTMR7_2 (0x46UL) -#define HPM_DMA_SRC_GPTMR7_3 (0x47UL) -#define HPM_DMA_SRC_I2C0 (0x48UL) -#define HPM_DMA_SRC_I2C1 (0x49UL) -#define HPM_DMA_SRC_I2C2 (0x4AUL) -#define HPM_DMA_SRC_I2C3 (0x4BUL) -#define HPM_DMA_SRC_XPI0_RX (0x4CUL) -#define HPM_DMA_SRC_XPI0_TX (0x4DUL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_enet_soc_drv.h deleted file mode 100644 index fadee53a327..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_enet_soc_drv.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ENET_SOC_DRV_H -#define HPM_ENET_SOC_DRV_H - -#include "hpm_soc.h" - -#if defined __cplusplus -extern "C" { -#endif - -static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; - ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 |= ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL0 &= ~(ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); - ptr->CTRL0 |= ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) -{ - hpm_stat_t stat = status_success; - - /* use an internal PLL clock as reference clock for rmii mode */ - if (ptr == HPM_ENET0) { - if (internal == true) { - /* use a pll clock */ - ptr->CTRL2 |= ENET_CTRL2_ENET0_REFCLK_OE_MASK | ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else { - /* use an external clock as reference clock for rmii mode */ - ptr->CTRL2 |= ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ - } - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - /* use an internal PLL clock for rgmii mode */ - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -#if defined __cplusplus -} /* __cplusplus */ -#endif - -#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_gpiom_soc_drv.h deleted file mode 100644 index fcfcfce2aa4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_core0_fast = 2, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_interrupt.h deleted file mode 100644 index 92141f143a4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_interrupt.h +++ /dev/null @@ -1,1204 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Delegate IRQ handling - * - * @param[in] mask interrupt mask to be delegated - */ -ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) -{ - set_csr(CSR_MIDELEG, mask); -} - -/** - * @brief Undelegate IRQ handling - * - * @param[in] mask interrupt mask to be undelegated - */ -ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) -{ - clear_csr(CSR_MIDELEG, mask); -} - - -/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ - -/** - * @brief Enable global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return sstatus for supervisor mode - * - * @param[in] mask interrupt mask to be disabled - * @retval current sstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) -{ - set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ for supervisor mode - */ -ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) -{ - set_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) -{ - clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - - - -/* Supervisor mode */ - -/** - * @brief Enable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) -{ - set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Disable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Trigger software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) -{ - set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - - -/** - * @brief Complete software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) -{ - clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - -/* - * @brief Enable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Disable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -#define intc_set_s_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) - -/* - * @brief Complete IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Claim IRQ for supervisor mode - * - */ -#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) - -/* - * @brief Enable IRQ for supervisor mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_s_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_s_enable_irq(irq); \ - } while (0) - - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* Supervisor mode */ -extern int __vector_s_table[]; -extern void default_s_irq_entry(void); -/** - * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) -{ - __vector_s_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) -{ - __vector_s_table[irq] = (int) default_s_irq_entry; -} - - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else /*__riscv_flen == 64*/ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - - -#define ENTER_NESTED_IRQ_HANDLING_S() {\ - __asm volatile("\n\ - csrr s2, sepc \n\ - csrr s3, sstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi sstatus, 2"); \ -} -#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("csrci sstatus, 2"); \ - __asm volatile("lui a4, 0xe4201"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling at supervisor mode - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * SCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * SSTATUS = word offset 18 - */ -#define EXIT_NESTED_IRQ_HANDLING_S() { \ - __asm volatile("\n\ - csrw sstatus, s3 \n\ - csrw sepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define EXTERN_C extern "C" -#else -#define EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -#define ISR_NAME_S(irq_num) default_isr_s_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} -#else -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void ISR_NAME_S(irq_num)(void) {\ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_S();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_S(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_S();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("sret\n");\ -} -#endif -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) { \ - isr(); \ -} - -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_S(irq_num)(void) { \ - isr(); \ -} - -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) {\ - isr();\ -} - -/* Supervisor mode */ - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_s_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR_S(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_s_isr(void) {\ - isr();\ -} - -#define CSR_MSTATUS_MPP_S_MODE (0x1) -#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ -do { \ - if (label) { \ - write_csr(mepc, label); \ - } \ - clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ - set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ -} while(0) - -typedef void (*s_mode_entry)(void); - -/** - * @brief Switch mode to supervisor from machine - * - * @param[in] entry - entry point after mode is switched - */ -static inline void switch_to_s_mode(s_mode_entry entry) -{ - write_csr(CSR_SEPC, entry); - MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); - if (entry) { - __asm("mret"); - } -} -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_iomux.h deleted file mode 100644 index 2677132d897..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_iomux.h +++ /dev/null @@ -1,1965 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA00_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA01_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA02_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA03_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA08_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA09_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA10_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA10_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA10_FUNC_CTL_DIS0_G_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA10_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA11_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA11_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA11_FUNC_CTL_DIS0_G_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA11_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA12_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA12_FUNC_CTL_DIS0_G_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA12_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA13_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA13_FUNC_CTL_DIS0_G_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA13_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA14_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA14_FUNC_CTL_DIS0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA14_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA15_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA15_FUNC_CTL_DIS0_R_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA15_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA16_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA16_FUNC_CTL_DIS0_R_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA16_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA17_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA17_FUNC_CTL_DIS0_R_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA17_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA18_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA18_FUNC_CTL_DIS0_R_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA18_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA18_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA19_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA19_FUNC_CTL_DIS0_R_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA19_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA20_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA20_FUNC_CTL_DIS0_G_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA20_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA21_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA21_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA22_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA23_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA23_FUNC_CTL_SDC0_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA23_FUNC_CTL_CAM0_D_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA24_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA24_FUNC_CTL_SDC1_VON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA24_FUNC_CTL_CAM0_D_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA25_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PA25_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA25_FUNC_CTL_CAM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA26_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA26_FUNC_CTL_CAM0_PIXCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA27_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA27_FUNC_CTL_CAM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA28_FUNC_CTL_DIS0_R_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_CAM0_XCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_DIS0_R_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA31_FUNC_CTL_DIS0_R_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB00_FUNC_CTL_DIS0_G_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB01_FUNC_CTL_DIS0_G_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB02_FUNC_CTL_DIS0_B_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB03_FUNC_CTL_DIS0_B_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_GPTMR5_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB04_FUNC_CTL_DIS0_B_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB05_FUNC_CTL_DIS0_G_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB06_FUNC_CTL_DIS0_B_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_DIS0_B_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB08_FUNC_CTL_DIS0_B_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB09_FUNC_CTL_DIS0_B_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB10_FUNC_CTL_DIS0_EN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_GPTMR4_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_DIS0_B_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_GPTMR5_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB12_FUNC_CTL_DIS0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB13_FUNC_CTL_DIS0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_GPTMR4_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_DIS0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB14_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_SDC0_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB16_FUNC_CTL function mux definitions */ -#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB16_FUNC_CTL_CAM0_D_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB17_FUNC_CTL function mux definitions */ -#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB17_FUNC_CTL_CAM0_D_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB18_FUNC_CTL function mux definitions */ -#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB18_FUNC_CTL_CAM0_D_9 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB19_FUNC_CTL function mux definitions */ -#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB19_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB19_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB19_FUNC_CTL_CAM0_D_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB20_FUNC_CTL function mux definitions */ -#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB20_FUNC_CTL_GPTMR7_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB20_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB20_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB20_FUNC_CTL_CAM0_HSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB21_FUNC_CTL function mux definitions */ -#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB21_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB21_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB21_FUNC_CTL_CAM0_VSYNC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB22_FUNC_CTL function mux definitions */ -#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB22_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB22_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB22_FUNC_CTL_SDC0_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB23_FUNC_CTL function mux definitions */ -#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB23_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB23_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB23_FUNC_CTL_SDC0_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB24_FUNC_CTL function mux definitions */ -#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB24_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB24_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB24_FUNC_CTL_SDC0_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB25_FUNC_CTL function mux definitions */ -#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB25_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB25_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB25_FUNC_CTL_SDC0_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB26_FUNC_CTL function mux definitions */ -#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB26_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB26_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB26_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB27_FUNC_CTL function mux definitions */ -#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB27_FUNC_CTL_GPTMR6_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB27_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB27_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB27_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB28_FUNC_CTL function mux definitions */ -#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB28_FUNC_CTL_GPTMR7_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB28_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB28_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB28_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB28_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PB29_FUNC_CTL function mux definitions */ -#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB29_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB29_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB29_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB30_FUNC_CTL function mux definitions */ -#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB30_FUNC_CTL_GPTMR6_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB30_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB30_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PB31_FUNC_CTL function mux definitions */ -#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB31_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB31_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC00_FUNC_CTL function mux definitions */ -#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC00_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC00_FUNC_CTL_SDC0_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC00_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC01_FUNC_CTL function mux definitions */ -#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC01_FUNC_CTL_I2S2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC01_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC01_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PC01_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC02_FUNC_CTL function mux definitions */ -#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC02_FUNC_CTL_I2S2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC02_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC03_FUNC_CTL function mux definitions */ -#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC03_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC03_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC03_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC04_FUNC_CTL function mux definitions */ -#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC04_FUNC_CTL_I2S2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC04_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC04_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC05_FUNC_CTL function mux definitions */ -#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC05_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC05_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC05_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC06_FUNC_CTL function mux definitions */ -#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC06_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC06_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC06_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC07_FUNC_CTL function mux definitions */ -#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC07_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC07_FUNC_CTL_SDC0_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC08_FUNC_CTL function mux definitions */ -#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC08_FUNC_CTL_I2S2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC08_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC08_FUNC_CTL_SDC0_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC08_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC09_FUNC_CTL function mux definitions */ -#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC09_FUNC_CTL_I2S2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC09_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC09_FUNC_CTL_SDC0_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC09_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC10_FUNC_CTL function mux definitions */ -#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC10_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC10_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC10_FUNC_CTL_SDC0_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC11_FUNC_CTL function mux definitions */ -#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC11_FUNC_CTL_I2S2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC11_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC11_FUNC_CTL_SDC0_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC12_FUNC_CTL function mux definitions */ -#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC12_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC12_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC13_FUNC_CTL function mux definitions */ -#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC13_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC13_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC14_FUNC_CTL function mux definitions */ -#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC14_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC14_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC14_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC15_FUNC_CTL function mux definitions */ -#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC15_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC15_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC15_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC16_FUNC_CTL function mux definitions */ -#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC16_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC16_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC17_FUNC_CTL function mux definitions */ -#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC17_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC17_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC18_FUNC_CTL function mux definitions */ -#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC18_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC18_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC18_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC19_FUNC_CTL function mux definitions */ -#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC19_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC19_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC19_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC19_FUNC_CTL_ADC0_DBG IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC20_FUNC_CTL function mux definitions */ -#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC20_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC20_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC20_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC20_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC20_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC21_FUNC_CTL function mux definitions */ -#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC21_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC21_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC21_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC21_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC22_FUNC_CTL function mux definitions */ -#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC22_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC22_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC22_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC22_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC23_FUNC_CTL function mux definitions */ -#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC23_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC23_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC23_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC23_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC23_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC24_FUNC_CTL function mux definitions */ -#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC24_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC24_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC24_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC25_FUNC_CTL function mux definitions */ -#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC25_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC25_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC25_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC26_FUNC_CTL function mux definitions */ -#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC26_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC26_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC26_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC27_FUNC_CTL function mux definitions */ -#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC27_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC27_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC27_FUNC_CTL_SDC1_VON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC27_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC27_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC28_FUNC_CTL function mux definitions */ -#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC28_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC28_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC28_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC29_FUNC_CTL function mux definitions */ -#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC29_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PC29_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC30_FUNC_CTL function mux definitions */ -#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC30_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC30_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC30_FUNC_CTL_SDC1_CDN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC31_FUNC_CTL function mux definitions */ -#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC31_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC31_FUNC_CTL_SDC1_VSEL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD00_FUNC_CTL function mux definitions */ -#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD00_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD00_FUNC_CTL_SDC1_VON IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD01_FUNC_CTL function mux definitions */ -#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD01_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD01_FUNC_CTL_SDC1_WP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD02_FUNC_CTL function mux definitions */ -#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD02_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD03_FUNC_CTL function mux definitions */ -#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD03_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD04_FUNC_CTL function mux definitions */ -#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD04_FUNC_CTL_GPTMR5_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD04_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD04_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PD05_FUNC_CTL function mux definitions */ -#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD05_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD05_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PD06_FUNC_CTL function mux definitions */ -#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD06_FUNC_CTL_I2S2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD06_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD06_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD07_FUNC_CTL function mux definitions */ -#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD07_FUNC_CTL_I2S2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD07_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD07_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD08_FUNC_CTL function mux definitions */ -#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD08_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD08_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD08_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD09_FUNC_CTL function mux definitions */ -#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD09_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD09_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD09_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD10_FUNC_CTL function mux definitions */ -#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD10_FUNC_CTL_I2S2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD10_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD10_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD11_FUNC_CTL function mux definitions */ -#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD11_FUNC_CTL_GPTMR4_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD11_FUNC_CTL_I2S2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD11_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD11_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD12_FUNC_CTL function mux definitions */ -#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD12_FUNC_CTL_GPTMR5_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD12_FUNC_CTL_I2S2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD12_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD12_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD13_FUNC_CTL function mux definitions */ -#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD13_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD13_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD13_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD14_FUNC_CTL function mux definitions */ -#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD14_FUNC_CTL_GPTMR4_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD14_FUNC_CTL_I2S2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD14_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD14_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD15_FUNC_CTL function mux definitions */ -#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD15_FUNC_CTL_I2S2_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD15_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD15_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD16_FUNC_CTL function mux definitions */ -#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD16_FUNC_CTL_I2S2_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD16_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD16_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD17_FUNC_CTL function mux definitions */ -#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD17_FUNC_CTL_I2S2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD17_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PD17_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD18_FUNC_CTL function mux definitions */ -#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD18_FUNC_CTL_I2S2_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD18_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PD19_FUNC_CTL function mux definitions */ -#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD19_FUNC_CTL_I2S2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD19_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PD20_FUNC_CTL function mux definitions */ -#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD20_FUNC_CTL_GPTMR7_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD20_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD20_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD20_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD21_FUNC_CTL function mux definitions */ -#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD21_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD21_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD21_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD22_FUNC_CTL function mux definitions */ -#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD22_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD22_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD22_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD23_FUNC_CTL function mux definitions */ -#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD23_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD23_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD23_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD24_FUNC_CTL function mux definitions */ -#define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD24_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD24_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD25_FUNC_CTL function mux definitions */ -#define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD25_FUNC_CTL_I2S3_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD25_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PD26_FUNC_CTL function mux definitions */ -#define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD26_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD26_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD27_FUNC_CTL function mux definitions */ -#define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD27_FUNC_CTL_GPTMR6_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD27_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD27_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PD28_FUNC_CTL function mux definitions */ -#define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD28_FUNC_CTL_GPTMR7_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD28_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PD29_FUNC_CTL function mux definitions */ -#define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD29_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD29_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD30_FUNC_CTL function mux definitions */ -#define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD30_FUNC_CTL_GPTMR6_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD30_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD30_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD30_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD31_FUNC_CTL function mux definitions */ -#define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD31_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PD31_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PD31_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE00_FUNC_CTL function mux definitions */ -#define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE00_FUNC_CTL_I2S3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE00_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE01_FUNC_CTL function mux definitions */ -#define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE01_FUNC_CTL_I2S3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE01_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PE02_FUNC_CTL function mux definitions */ -#define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE02_FUNC_CTL_I2S3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE02_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE02_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE03_FUNC_CTL function mux definitions */ -#define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE03_FUNC_CTL_I2S3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE03_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE04_FUNC_CTL function mux definitions */ -#define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE04_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE04_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE04_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE05_FUNC_CTL function mux definitions */ -#define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE05_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE05_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PE06_FUNC_CTL function mux definitions */ -#define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE06_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PE07_FUNC_CTL function mux definitions */ -#define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE07_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PE08_FUNC_CTL function mux definitions */ -#define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE08_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE08_FUNC_CTL_I2S3_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE08_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE09_FUNC_CTL function mux definitions */ -#define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE09_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE09_FUNC_CTL_I2S3_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE09_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE10_FUNC_CTL function mux definitions */ -#define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE10_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE10_FUNC_CTL_I2S3_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE10_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE11_FUNC_CTL function mux definitions */ -#define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE11_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE11_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE11_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE12_FUNC_CTL function mux definitions */ -#define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE12_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE12_FUNC_CTL_I2S3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE12_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE12_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE13_FUNC_CTL function mux definitions */ -#define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE13_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE13_FUNC_CTL_I2S3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE13_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE13_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE14_FUNC_CTL function mux definitions */ -#define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE14_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE14_FUNC_CTL_I2S3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE14_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE14_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE14_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE15_FUNC_CTL function mux definitions */ -#define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE15_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE15_FUNC_CTL_I2S3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE15_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE15_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE16_FUNC_CTL function mux definitions */ -#define IOC_PE16_FUNC_CTL_GPIO_E_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE16_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE16_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE17_FUNC_CTL function mux definitions */ -#define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE17_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE17_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE18_FUNC_CTL function mux definitions */ -#define IOC_PE18_FUNC_CTL_GPIO_E_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE18_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE18_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE18_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE19_FUNC_CTL function mux definitions */ -#define IOC_PE19_FUNC_CTL_GPIO_E_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE19_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE19_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE19_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE20_FUNC_CTL function mux definitions */ -#define IOC_PE20_FUNC_CTL_GPIO_E_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE20_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE20_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE20_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE20_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE20_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE21_FUNC_CTL function mux definitions */ -#define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE21_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE21_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE21_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE22_FUNC_CTL function mux definitions */ -#define IOC_PE22_FUNC_CTL_GPIO_E_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE22_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE22_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE22_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PE23_FUNC_CTL function mux definitions */ -#define IOC_PE23_FUNC_CTL_GPIO_E_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE23_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE23_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE23_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PE23_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE24_FUNC_CTL function mux definitions */ -#define IOC_PE24_FUNC_CTL_GPIO_E_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE24_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE24_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE24_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE24_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE25_FUNC_CTL function mux definitions */ -#define IOC_PE25_FUNC_CTL_GPIO_E_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE25_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE25_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE25_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PE26_FUNC_CTL function mux definitions */ -#define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE26_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE26_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) - -/* IOC_PE27_FUNC_CTL function mux definitions */ -#define IOC_PE27_FUNC_CTL_GPIO_E_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE27_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE27_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE27_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE27_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE28_FUNC_CTL function mux definitions */ -#define IOC_PE28_FUNC_CTL_GPIO_E_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE28_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE28_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE28_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE28_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE29_FUNC_CTL function mux definitions */ -#define IOC_PE29_FUNC_CTL_GPIO_E_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE29_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE29_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE29_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PE30_FUNC_CTL function mux definitions */ -#define IOC_PE30_FUNC_CTL_GPIO_E_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE30_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE30_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE30_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE30_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PE31_FUNC_CTL function mux definitions */ -#define IOC_PE31_FUNC_CTL_GPIO_E_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE31_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE31_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PF00_FUNC_CTL function mux definitions */ -#define IOC_PF00_FUNC_CTL_GPIO_F_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF00_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF00_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF01_FUNC_CTL function mux definitions */ -#define IOC_PF01_FUNC_CTL_GPIO_F_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF01_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF01_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF02_FUNC_CTL function mux definitions */ -#define IOC_PF02_FUNC_CTL_GPIO_F_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF02_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF02_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF03_FUNC_CTL function mux definitions */ -#define IOC_PF03_FUNC_CTL_GPIO_F_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF03_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF03_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF03_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PF03_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF04_FUNC_CTL function mux definitions */ -#define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF04_FUNC_CTL_GPTMR5_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF04_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF04_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) -#define IOC_PF04_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF05_FUNC_CTL function mux definitions */ -#define IOC_PF05_FUNC_CTL_GPIO_F_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF05_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF05_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF06_FUNC_CTL function mux definitions */ -#define IOC_PF06_FUNC_CTL_GPIO_F_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF06_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF07_FUNC_CTL function mux definitions */ -#define IOC_PF07_FUNC_CTL_GPIO_F_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF07_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF08_FUNC_CTL function mux definitions */ -#define IOC_PF08_FUNC_CTL_GPIO_F_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF08_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF08_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF08_FUNC_CTL_ETH0_EVTI_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF09_FUNC_CTL function mux definitions */ -#define IOC_PF09_FUNC_CTL_GPIO_F_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF09_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF09_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF09_FUNC_CTL_ETH0_EVTI_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(19) - -/* IOC_PF10_FUNC_CTL function mux definitions */ -#define IOC_PF10_FUNC_CTL_GPIO_F_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PF11_FUNC_CTL function mux definitions */ -#define IOC_PF11_FUNC_CTL_GPIO_F_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF11_FUNC_CTL_GPTMR4_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PF12_FUNC_CTL function mux definitions */ -#define IOC_PF12_FUNC_CTL_GPIO_F_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF12_FUNC_CTL_GPTMR5_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PF13_FUNC_CTL function mux definitions */ -#define IOC_PF13_FUNC_CTL_GPIO_F_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PF14_FUNC_CTL function mux definitions */ -#define IOC_PF14_FUNC_CTL_GPIO_F_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF14_FUNC_CTL_GPTMR4_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF14_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PF15_FUNC_CTL function mux definitions */ -#define IOC_PF15_FUNC_CTL_GPIO_F_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF15_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX00_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX01_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX02_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX02_FUNC_CTL_SDC1_DATA_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX03_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX03_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX03_FUNC_CTL_SDC1_DATA_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_GPTMR7_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX04_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX04_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX04_FUNC_CTL_SDC1_DATA_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX05_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX05_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX05_FUNC_CTL_SDC1_DATA_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX06_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX07_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX08_FUNC_CTL function mux definitions */ -#define IOC_PX08_FUNC_CTL_GPIO_X_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX08_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX08_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX08_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX08_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX08_FUNC_CTL_SDC1_DATA_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX09_FUNC_CTL function mux definitions */ -#define IOC_PX09_FUNC_CTL_GPIO_X_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX09_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX09_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX09_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX09_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX09_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX09_FUNC_CTL_SDC1_DATA_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX10_FUNC_CTL function mux definitions */ -#define IOC_PX10_FUNC_CTL_GPIO_X_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX10_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX10_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX10_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX10_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX10_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX10_FUNC_CTL_SDC1_CMD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX11_FUNC_CTL function mux definitions */ -#define IOC_PX11_FUNC_CTL_GPIO_X_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX11_FUNC_CTL_GPTMR6_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX11_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX11_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX11_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX11_FUNC_CTL_SDC1_DS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX12_FUNC_CTL function mux definitions */ -#define IOC_PX12_FUNC_CTL_GPIO_X_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX12_FUNC_CTL_GPTMR7_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX12_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX12_FUNC_CTL_SDC1_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX13_FUNC_CTL function mux definitions */ -#define IOC_PX13_FUNC_CTL_GPIO_X_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX13_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX13_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX13_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX13_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX13_FUNC_CTL_SDC1_DATA_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX14_FUNC_CTL function mux definitions */ -#define IOC_PX14_FUNC_CTL_GPIO_X_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX14_FUNC_CTL_GPTMR6_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX14_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX14_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX14_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX14_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX14_FUNC_CTL_SDC1_DATA_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PX15_FUNC_CTL function mux definitions */ -#define IOC_PX15_FUNC_CTL_GPIO_X_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX15_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX15_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX15_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX15_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX15_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PX15_FUNC_CTL_SDC1_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY02_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY03_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_GPTMR1_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY04_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY04_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY05_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY10_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_GPTMR0_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY11_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PY12_FUNC_CTL function mux definitions */ -#define IOC_PY12_FUNC_CTL_GPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY12_FUNC_CTL_GPTMR1_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY12_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PY13_FUNC_CTL function mux definitions */ -#define IOC_PY13_FUNC_CTL_GPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY13_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY14_FUNC_CTL function mux definitions */ -#define IOC_PY14_FUNC_CTL_GPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY14_FUNC_CTL_GPTMR0_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY15_FUNC_CTL function mux definitions */ -#define IOC_PY15_FUNC_CTL_GPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PZ02_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PZ03_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_GPTMR3_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ04_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PZ04_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ05_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PZ05_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PZ08_FUNC_CTL function mux definitions */ -#define IOC_PZ08_FUNC_CTL_GPIO_Z_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ08_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ08_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ08_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ08_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ09_FUNC_CTL function mux definitions */ -#define IOC_PZ09_FUNC_CTL_GPIO_Z_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ09_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ09_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ09_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ09_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ10_FUNC_CTL function mux definitions */ -#define IOC_PZ10_FUNC_CTL_GPIO_Z_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ10_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ10_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ10_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ10_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ10_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ11_FUNC_CTL function mux definitions */ -#define IOC_PZ11_FUNC_CTL_GPIO_Z_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ11_FUNC_CTL_GPTMR2_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ11_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ11_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PZ12_FUNC_CTL function mux definitions */ -#define IOC_PZ12_FUNC_CTL_GPIO_Z_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ12_FUNC_CTL_GPTMR3_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ12_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ12_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PZ13_FUNC_CTL function mux definitions */ -#define IOC_PZ13_FUNC_CTL_GPIO_Z_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ13_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ13_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ13_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ13_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ13_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ13_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ14_FUNC_CTL function mux definitions */ -#define IOC_PZ14_FUNC_CTL_GPIO_Z_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ14_FUNC_CTL_GPTMR2_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ14_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ14_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ15_FUNC_CTL function mux definitions */ -#define IOC_PZ15_FUNC_CTL_GPIO_Z_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ15_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ15_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ15_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_l1c_drv.h deleted file mode 100644 index 1f1a21639a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 32KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 64B */ -#define HPM_L1C_CACHELINE_SIZE (64) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_mcan_soc.h deleted file mode 100644 index 2ed784db319..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_mcan_soc.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MCAN_SOC_H -#define HPM_MCAN_SOC_H - -#include -#include "hpm_mcan_regs.h" -#include "hpm_soc.h" -#include "hpm_soc_feature.h" - -#define MCAN_SOC_TSU_SRC_TWO_STAGES (1U) - -#define HPM_MCAN_EXT_TBSEL_NUM (4U) -#define HPM_MCAN_TBSEL_BASE (0xF02FF000UL) -#define HPM_MCAN_TBSEL (*(volatile uint32_t *)HPM_MCAN_TBSEL_BASE) -#define HPM_MCAN_TBSEL_BITWIDTH (6U) -#define HPM_MCAN_TBSEL_MASK ((1UL << HPM_MCAN_TBSEL_BITWIDTH) - 1UL) -#define HPM_MCAN_TBSEL0_SHIFT (8U) - -/** - * @brief MCAN MSG BUF base address (AHB_RAM) - */ -#define MCAN_MSG_BUF_SIZE_IN_WORDS (640U) -#define MCAN_IP_SLOT_SIZE (0x4000U) - -/** - * @brief TSU External Timebase Sources - */ -#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_1 (1U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_2 (2U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3 (3U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3) - -/** - * @brief MCAN TSU timebase option for each External Timebase - */ -#define MCAN_TSU_TBSEL_PTPC0 (0x20) -#define MCAN_TSU_TBSEL_MCAN0 (0x00) -#define MCAN_TSU_TBSEL_MCAN1 (0x01) -#define MCAN_TSU_TBSEL_MCAN2 (0x02) -#define MCAN_TSU_TBSEL_MCAN3 (0x03) -#define MCAN_TSU_TBSEL_MCAN4 (0x04) -#define MCAN_TSU_TBSEL_MCAN5 (0x05) -#define MCAN_TSU_TBSEL_MCAN6 (0x06) -#define MCAN_TSU_TBSEL_MCAN7 (0x07) - -ATTR_PLACE_AT(".ahb_sram") extern uint32_t mcan_soc_msg_buf[MCAN_MSG_BUF_SIZE_IN_WORDS * MCAN_SOC_MAX_COUNT]; - -#ifdef __cpluspus -extern "C" { -#endif - -/** - * @brief Set External Timebase Source for MCAN TSU - * @param [in] ptr MCAN base - * @param [in] src External Timebase source - */ -static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) -{ - if (src < HPM_MCAN_EXT_TBSEL_NUM) { - ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); - } -} - -/** - * @brief Set the Source for specified external timebase - * - * @param [in] ptr MCAN base - * @param [in] ext_tbsel External TBSEL index - * @param [in] tbsel_option Timebase source selection - */ -static inline void mcan_set_tsu_tbsel_option(MCAN_Type *ptr, uint8_t ext_tbsel, uint8_t tbsel_option) -{ - (void) ptr; - if (ext_tbsel < HPM_MCAN_EXT_TBSEL_NUM) { - uint32_t tbsel_shift = (ext_tbsel * HPM_MCAN_TBSEL_BITWIDTH) + HPM_MCAN_TBSEL0_SHIFT; - uint32_t tbsel_mask = HPM_MCAN_TBSEL_MASK << tbsel_shift; - HPM_MCAN_TBSEL = (HPM_MCAN_TBSEL & ~tbsel_mask) | (((uint32_t) tbsel_option << tbsel_shift) & tbsel_mask); - } -} - -/** - * @brief Enable Standby Pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Disable Standby pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Get RAM base for MCAN - * @param [in] ptr MCAN base - * @return RAM base for MCAN - */ -static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) -{ - (void) ptr; - return (uint32_t) &mcan_soc_msg_buf[0]; -} - -/** - * @brief Get the MCAN RAM offset in the dedicated/shared RAM for - * @param [in] ptr MCAN base - * @return RAM offset for MCAN - */ -static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) -{ - uint32_t index = ((uint32_t) ptr - HPM_MCAN0_BASE) / MCAN_IP_SLOT_SIZE; - - return (index * MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); -} - -/** - * @brief Get MCAN RAM size - * @param [in] ptr MCAN base - * @return RAM size in bytes - */ -static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) -{ - (void) ptr; - return (MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); -} - -#ifdef __cpluspus -} -#endif - -#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_misc.h deleted file mode 100644 index e81a74fa29f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_misc.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define ILM_LOCAL_BASE (0x0U) -#define ILM_SIZE_IN_BYTE (0x40000U) -#define DLM_LOCAL_BASE (0x80000U) -#define DLM_SIZE_IN_BYTE (0x40000U) -#define CORE0_ILM_SYSTEM_BASE (0x1040000U) -#define CORE0_DLM_SYSTEM_BASE (0x1060000U) -#define CORE1_ILM_SYSTEM_BASE (0x1180000U) -#define CORE1_DLM_SYSTEM_BASE (0x11C0000U) - -#define ADDRESS_IN_ILM(address) \ - ((ILM_LOCAL_BASE) <= (address)) && \ - ((ILM_LOCAL_BASE + ILM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_DLM(address) \ - ((DLM_LOCAL_BASE) <= (address)) && \ - ((DLM_LOCAL_BASE + DLM_SIZE_IN_BYTE) > (address)) -#define ADDRESS_IN_CORE0_DLM_SYSTEM(address) \ - ((CORE0_DLM_SYSTEM_BASE) <= (address)) && \ - ((CORE0_DLM_SYSTEM_BASE + DLM_SIZE_IN_BYTE) > (address)) - -#define DLM_TO_SYSTEM(address) \ - (CORE0_DLM_SYSTEM_BASE + (address) - (DLM_LOCAL_BASE)) -#define ILM_TO_SYSTEM(address) \ - (CORE0_ILM_SYSTEM_BASE + (address) - (ILM_LOCAL_BASE)) -#define SYSTEM_TO_DLM(address) \ - ((address) - CORE0_DLM_SYSTEM_BASE + (DLM_LOCAL_BASE)) - -#define HPM_CORE0 (0U) -#define HPM_CORE1 (1U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_otp_drv.c deleted file mode 100644 index 36c05c561f4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - /* Wait until LDO is ready */ - while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { - } - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = HPM_OTP; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_otp_drv.h deleted file mode 100644 index afb2f22de54..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_otp_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - -/** - * @brief Initialize OTP controller - */ -void otp_init(void); - -/** - * @brief De-initialize OTP controller - */ -void otp_deinit(void); - -/** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_shadow(uint32_t addr); - -/** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_ip(uint32_t addr); - -/** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - -/** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ -hpm_stat_t otp_reload(otp_region_t region); - -/** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - -/** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [in] val Data to be written - * @return API execution status - */ -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_pcfg_drv.h deleted file mode 100644 index b4d5a6068ed..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_pcfg_drv.h +++ /dev/null @@ -1,888 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -typedef enum { - pcfg_dcdc_oc_limit_2000ma = 0, - pcfg_dcdc_oc_limit_1300ma = 1, -} pcfg_dcdc_oc_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, - pcfg_pmc_periph_vad = 16, - pcfg_pmc_periph_pmic_mem = 18, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap enable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK; -} - -/** - * @brief bandgap disable power save mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief bandgap enable low power mode - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr) -{ - ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK; -} - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - * @param[in] over_limit unused - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) -{ - (void) over_limit; - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK)) - | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - -/** - * @brief disable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief enable power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover over voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over current protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_current_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_SHORT_MASK; -} - -/** - * @brief enable over current protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_over_current_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_SHORT_MASK; -} - -/** - * @brief set over current limit - * - * @param[in] ptr base address - * @param[in] limit reference pcfg_dcdc_oc_limit_t - */ -static inline void pcfg_dcdc_set_over_current_limit(PCFG_Type *ptr, pcfg_dcdc_oc_limit_t limit) -{ - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_SHORT_CURRENT_MASK) | PCFG_DCDC_PROT_SHORT_CURRENT_SET(limit); -} - -/** - * @brief checkover over current flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_current(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_SHORT_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get measured current level - * - * @param[in] ptr base address - * - * @retval measured current, unit 50mA - */ -static inline bool pcfg_dcdc_get_measured_current_level(PCFG_Type *ptr) -{ - return PCFG_DCDC_CURRENT_LEVEL_GET(ptr->DCDC_CURRENT); -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/* - * @brief check if DDR DCDC is stable or not - * @param[in] ptr base address - * @retval true if DDR DCDC is stable - */ -static inline bool pcfg_ddr_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDCM_MODE_READY_GET(ptr->DCDCM_MODE); -} - -/* - * @brief set DDR DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDCM_MODE = (ptr->DCDCM_MODE & ~PCFG_DCDCM_MODE_MODE_MASK) | PCFG_DCDCM_MODE_MODE_SET(mode); -} - - -/* - * @brief set on-chip DDR DCDC enable and voltage - * @param[in] ptr base address - * @param[in] voltage unit mv - */ -static inline void pcfg_ddr_dcdc_set_voltage_output(PCFG_Type *ptr, uint8_t voltage) -{ - ptr->DCDCM_MODE = (ptr->DCDCM_MODE & ~(PCFG_DCDCM_MODE_VOLT_MASK | PCFG_DCDCM_MODE_MODE_MASK)) - | PCFG_DCDCM_MODE_VOLT_SET(voltage) | PCFG_DCDCM_MODE_MODE_SET(pcfg_dcdc_mode_basic); -} - -/** - * @brief set ddr low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - */ -static inline void pcfg_ddr_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit) -{ - ptr->DCDCM_PROT = (ptr->DCDCM_PROT & ~(PCFG_DCDCM_PROT_ILIMIT_LP_MASK)) - | PCFG_DCDCM_PROT_ILIMIT_LP_SET(limit); -} - -/** - * @brief disable ddr power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_disable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief enable ddr power loss protection - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_enable_power_loss_prot(PCFG_Type *ptr) -{ - ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK; -} - -/** - * @brief check if ddr power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_ddr_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDCM_PROT_POWER_LOSS_FLAG_GET(ptr->DCDCM_PROT); -} - -/** - * @brief disable ddr over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable ddr over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_enable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover ddr over voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_ddr_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDCM_PROT_OVERVOLT_FLAG_GET(ptr->DCDCM_PROT); -} - -/** - * @brief disable ddr over current protection - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_disable_over_current_prot(PCFG_Type *ptr) -{ - ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_SHORT_MASK; -} - -/** - * @brief enable ddr over current protection - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_enable_over_current_prot(PCFG_Type *ptr) -{ - ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_SHORT_MASK; -} - -/** - * @brief set ddr over current limit - * - * @param[in] ptr base address - * @param[in] limit reference pcfg_dcdc_oc_limit_t - */ -static inline void pcfg_ddr_dcdc_set_over_current_limit(PCFG_Type *ptr, pcfg_dcdc_oc_limit_t limit) -{ - ptr->DCDCM_PROT = (ptr->DCDCM_PROT & ~PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) | PCFG_DCDCM_PROT_SHORT_CURRENT_SET(limit); -} - -/** - * @brief checkover ddr over current flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_ddr_dcdc_is_over_current(PCFG_Type *ptr) -{ - return PCFG_DCDCM_PROT_SHORT_FLAG_GET(ptr->DCDCM_PROT); -} - -/** - * @brief disable ddr current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDCM_CURRENT &= ~PCFG_DCDCM_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable ddr current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDCM_CURRENT |= PCFG_DCDCM_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured ddr current is valid - * - * @param[in] ptr base address - * - * @retval true if measured ddr current is valid - */ -static inline bool pcfg_ddr_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDCM_CURRENT & PCFG_DCDCM_CURRENT_VALID_MASK; -} - -/** - * @brief get measured ddr current level - * - * @param[in] ptr base address - * - * @retval measured ddr current, unit 50mA - */ -static inline bool pcfg_ddr_dcdc_get_measured_current_level(PCFG_Type *ptr) -{ - return PCFG_DCDCM_CURRENT_LEVEL_GET(ptr->DCDCM_CURRENT); -} - -/** - * @brief get ddr dcdc start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval ddr dcdc start time in cycles - */ -static inline uint32_t pcfg_ddr_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDCM_START_TIME_START_TIME_GET(ptr->DCDCM_START_TIME); -} - -/** - * @brief get ddr dcdc resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval ddr dcdc resuem time in cycles - */ -static inline uint32_t pcfg_ddr_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDCM_RESUME_TIME_RESUME_TIME_GET(ptr->DCDCM_RESUME_TIME); -} - -/** - * @brief set ddr dcdc start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_ddr_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDCM_START_TIME = PCFG_DCDCM_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set ddr dcdc resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_ddr_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDCM_RESUME_TIME = PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set ddr dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_ddr_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDCM_MISC = (ptr->DCDCM_MISC & (~PCFG_DCDCM_MISC_OL_HYST_MASK)) | PCFG_DCDCM_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable ddr dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_disable_retention(PCFG_Type *ptr) -{ - ptr->DCDCM_POWER_CONFIG &= ~PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK; -} - -/** - * @brief enable ddr dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_ddr_dcdc_enable_retention(PCFG_Type *ptr) -{ - ptr->DCDCM_POWER_CONFIG |= PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_plic_drv.h deleted file mode 100644 index 9595051f906..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_plic_drv.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_pmic_iomux.h deleted file mode 100644 index 8868e14aeb9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_pmic_iomux.h +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_PURT_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PURT_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_PURT_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PURT_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_PURT_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PURT_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_PURT_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PURT_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_PWDG_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PWDG_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_VAD_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_VAD_DAT IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY08_FUNC_CTL function mux definitions */ -#define IOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_GPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_PGPIO_Y_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY08_FUNC_CTL_SOC_PY_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY09_FUNC_CTL function mux definitions */ -#define IOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_GPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_PGPIO_Y_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY09_FUNC_CTL_SOC_PY_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY10_FUNC_CTL function mux definitions */ -#define IOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_GPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_PGPIO_Y_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY10_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY10_FUNC_CTL_SOC_PY_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY11_FUNC_CTL function mux definitions */ -#define IOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_GPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_PGPIO_Y_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY11_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY11_FUNC_CTL_SOC_PY_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY12_FUNC_CTL function mux definitions */ -#define IOC_PY12_FUNC_CTL_PGPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY12_FUNC_CTL_GPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY12_FUNC_CTL_PGPIO_Y_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY12_FUNC_CTL_SOC_PY_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY12_FUNC_CTL_SOC_PY_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY13_FUNC_CTL function mux definitions */ -#define IOC_PY13_FUNC_CTL_PGPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY13_FUNC_CTL_GPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY13_FUNC_CTL_PGPIO_Y_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY13_FUNC_CTL_SOC_PY_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY13_FUNC_CTL_SOC_PY_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY14_FUNC_CTL function mux definitions */ -#define IOC_PY14_FUNC_CTL_PGPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY14_FUNC_CTL_GPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY14_FUNC_CTL_PGPIO_Y_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY14_FUNC_CTL_SOC_PY_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY14_FUNC_CTL_SOC_PY_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY15_FUNC_CTL function mux definitions */ -#define IOC_PY15_FUNC_CTL_PGPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY15_FUNC_CTL_GPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY15_FUNC_CTL_PGPIO_Y_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY15_FUNC_CTL_SOC_PY_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) /* dropped macro, please use macro with prefix PIOC_ */ -#define PIOC_PY15_FUNC_CTL_SOC_PY_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ppor_drv.h deleted file mode 100644 index 1913a26aa1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ppor_drv.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_common.h" -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_wdog2 = 1 << 18, - ppor_reset_wdog3 = 1 << 19, - ppor_reset_pmic_wdog = 1 << 20, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = counter; -} - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - (void) ptr; - (void) mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - (void) ptr; - (void) mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - (void) ptr; - (void) mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - (void) ptr; - (void) mask; -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_romapi.h deleted file mode 100644 index 308a5d1f7df..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_romapi.h +++ /dev/null @@ -1,1016 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_sdp_drv.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, - uint32_t serial_root_clk_freq, - uint32_t data_valid_time, - xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t - (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t - (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t - (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t - (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t - (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t - (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief XPI RAM driver interface - */ -typedef struct { - /**< XPI RAM driver interface: API version */ - uint32_t version; - - /**< Get XPI RAM configuration based on cfg_option */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); - - /**< XPI RAM driver interface: Initialize XPI RAM */ - hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); -} xpi_ram_driver_interface_t; - -/** - * @brief SDP API interface - */ -typedef struct { - /**< SDP API interface: API version */ - uint32_t version; - /**< SDP API interface: Initialize IP */ - hpm_stat_t (*sdp_ip_init)(void); - /**< SDP API interface: Deinitialize IP */ - hpm_stat_t (*sdp_ip_deinit)(void); - /**< SDP API interface: Set AES key */ - hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: AES ECB crypto operation */ - hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API interface: AES CBC crypto operation */ - hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API interface: AES CTR crypto operation */ - hpm_stat_t - (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API interface: AES CCM encryption */ - hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: AES CCM Decrypt and verify */ - hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: memcpy */ - hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); - /**< SDP API interface: memset */ - hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); - /**< SDP API interface: HASH initialization */ - hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - /**< SDP API interface: HASH update */ - hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - /**< SDP API interface: HASH finish */ - hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); - /**< SDP API interface: Set SM4 Key */ - hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: SM4 Crypto ECB mode */ - hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API Interface: SM4 Crypto CBC mode*/ - hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API Interface: SM4 CTR mode */ - hpm_stat_t - (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API Interface: SM4 CCM Encryption */ - hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API Interface: SM4 CCM Decrypt and Verify */ - hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); -} sdp_driver_interface_t; - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const xpi_ram_driver_interface_t *xpi_ram_driver_if; - /**< Bootloader API table: sdp driver interface address */ - const sdp_driver_interface_t *sdp_driver_if; -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); - fencei(); - return status; -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); - fencei(); - return status; -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if - ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API execution address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, - xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - if ((base != HPM_XPI0) || ((start & 0xFFF) != 0) || ((len & 0xFFF) != 0) - || ((offset & 0xFFF) != 0)) { - return false; - } - static const uint8_t k_mc_xpi_remap_config[] = { - 0x2e, 0x96, 0x23, 0x22, 0xc5, 0x42, 0x23, 0x24, - 0xd5, 0x42, 0x93, 0xe5, 0x15, 0x00, 0x23, 0x20, - 0xb5, 0x42, 0x05, 0x45, 0x82, 0x80, - }; - typedef bool (*remap_config_cb_t)(XPI_Type *, uint32_t, uint32_t, uint32_t); - remap_config_cb_t cb = (remap_config_cb_t) &k_mc_xpi_remap_config; - bool result = cb(base, start, len, offset); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_disable[] = { - 0x83, 0x27, 0x05, 0x42, 0xf9, 0x9b, 0x23, 0x20, - 0xf5, 0x42, 0x82, 0x80, - }; - typedef void (*remap_disable_cb_t)(XPI_Type *); - remap_disable_cb_t cb = (remap_disable_cb_t) &k_mc_xpi_remap_disable; - cb(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - static const uint8_t k_mc_xpi_remap_enabled[] = { - 0x03, 0x25, 0x05, 0x42, 0x05, 0x89, 0x82, 0x80, - }; - typedef bool (*remap_chk_cb_t)(XPI_Type *); - remap_chk_cb_t chk_cb = (remap_chk_cb_t) &k_mc_xpi_remap_enabled; - return chk_cb(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - if (base != HPM_XPI0) { - return false; - } - static const uint8_t k_mc_exip_region_config[] = { - 0x18, 0x4a, 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, - 0xaa, 0x97, 0x23, 0xa4, 0xe7, 0xd0, 0x4c, 0x4a, - 0x14, 0x42, 0x58, 0x42, 0x23, 0xa6, 0xb7, 0xd0, - 0x4c, 0x46, 0x36, 0x97, 0x13, 0x77, 0x07, 0xc0, - 0x23, 0xa2, 0xb7, 0xd0, 0x0c, 0x46, 0x13, 0x67, - 0x37, 0x00, 0x05, 0x45, 0x23, 0xa0, 0xb7, 0xd0, - 0x0c, 0x4e, 0x23, 0xaa, 0xb7, 0xd0, 0x50, 0x4e, - 0x23, 0xa8, 0xc7, 0xd0, 0x23, 0xac, 0xd7, 0xd0, - 0x23, 0xae, 0xe7, 0xd0, 0x82, 0x80, - }; - typedef void (*exip_region_config_cb_t)(XPI_Type *, uint32_t, exip_region_param_t *); - exip_region_config_cb_t cb = (exip_region_config_cb_t) &k_mc_exip_region_config; - cb(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return true; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - static const uint8_t k_mc_exip_region_disable[] = { - 0x9a, 0x05, 0x2e, 0x95, 0x85, 0x67, 0xaa, 0x97, - 0x03, 0xa7, 0xc7, 0xd1, 0x75, 0x9b, 0x23, 0xae, - 0xe7, 0xd0, 0x82, 0x80 - }; - typedef void (*exip_region_disable_cb_t)(XPI_Type *, uint32_t); - exip_region_disable_cb_t cb = (exip_region_disable_cb_t) &k_mc_exip_region_disable; - cb(base, index); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_enable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x37, 0x07, 0x00, 0x80, 0xd9, 0x8f, 0x23, 0x20, - 0xf5, 0xc0, 0x82, 0x80 - }; - typedef void (*exip_enable_cb_t)(XPI_Type *); - exip_enable_cb_t cb = (exip_enable_cb_t) &k_mc_exip_enable; - cb(base); -} - -/** - * @brief Disable global EXiP logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - static const uint8_t k_mc_exip_disable[] = { - 0x85, 0x67, 0x3e, 0x95, 0x83, 0x27, 0x05, 0xc0, - 0x86, 0x07, 0x85, 0x83, 0x23, 0x20, 0xf5, 0xc0, - 0x82, 0x80 - }; - typedef void (*exip_disable_cb_t)(XPI_Type *); - exip_disable_cb_t cb = (exip_disable_cb_t) &k_mc_exip_disable; - cb(base); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); -} - -/*********************************************************************************************************************** - * - * - * XPI RAM Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Get XPI RAM configuration based on cfg_option - * @param [in] base XPI base address - * @param [out] ram_cfg XPI RAM configuration structure - * @param [in] cfg_option XPI RAM configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, - xpi_ram_config_t *ram_cfg, - xpi_ram_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); -} - -/** - * @brief Initialize XPI RAM - * @param [in] base XPI base address - * @param [in] ram_cfg XPI ram configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); -} - -/*********************************************************************************************************************** - * - * - * SDP Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Initialize SDP IP - */ -static inline void rom_sdp_init(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); -} - -/** - * @brief De-initialize SDP IP - */ -static inline void rom_sdp_deinit(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); -} - -/** - * @brief Set AES key to SDP - * @param [in] aes_ctx AES context - * @param [in] key AES key buffer - * @param [in] key_bits AES key-bit option - * @param[in] key_idx AES key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] len Data length for AES encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); -} - -/** - * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] length Data length for AES encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); -} - -/** - * @brief Set SM4 key to SDP - * @param [in] sm4_ctx SM4 context - * @param [in] key SM4 key buffer - * @param [in] key_bits SM4 key-bit option - * @param[in] key_idx SM4 key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, - const uint8_t *key, - sdp_sm4_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] len Data length for SM4 encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); -} - -/** - * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); -} - -/** - * @brief HASH initialization - * @param [in] hash_ctx HASH context - * @param [in] alg HASH algorithm - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); -} - -/** - * @brief HASH Update - * @param [in] hash_ctx HASH context - * @param [in] data Data for HASH operation - * @param [in] length of the data for HASH operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); -} - -/** - * @brief HASH finialize - * @param [in] hash_ctx HASH context - * @param [out] digest the output digest - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); -} - -/** - * @brief SDP memcpy operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memcpy - * @param [in] src Source address for memcpy - * @param [in] length Size of data for memcpy operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); -} - -/** - * @brief SDP memset operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memset - * @param [in] pattern pattern for memset - * @param [in] length Size of data for memset operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ea3ba9e8f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union { - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sdxc_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sdxc_soc_drv.h deleted file mode 100644 index 26782aa2e3f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sdxc_soc_drv.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SDXC_SOC_DRV_H -#define HPM_SDXC_SOC_DRV_H - -#include "hpm_soc.h" -#include "hpm_sdxc_regs.h" - -#if defined(__cplusplus) -extern "C" { -#endif - - -static inline void sdxc_enable_tm_clock(SDXC_Type *base) -{ - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_TMCLK_EN_MASK; -} - -static inline void sdxc_enable_freq_selection(SDXC_Type *base) -{ - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; -} - -static inline void sdxc_disable_freq_selection(SDXC_Type *base) -{ - base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; -} - -/** - * @brief Set SDXC clock divider - * @param [in] base SDXC base - * @param [in] div SDXC divider - */ -static inline void sdxc_set_clock_divider(SDXC_Type *base, uint32_t div) -{ - base->MISC_CTRL0 = - (base->MISC_CTRL0 & ~SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) | SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(div - 1U) | - SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK; -} - -/** - * @brief Get SDXC divider - * @param [in] base SDXC base - * @return SDXC divider value - */ -static inline uint32_t sdxc_get_clock_divider(SDXC_Type *base) -{ - return (1U + SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(base->MISC_CTRL0)); -} - -/** - * @brief Wait at least 74 clocks until card is ready to receive the first command - */ -static inline void sdxc_wait_card_active(SDXC_Type *base) -{ - base->SYS_CTRL |= SDXC_SYS_CTRL_SD_CLK_EN_MASK; - - base->MISC_CTRL1 |= SDXC_MISC_CTRL1_CARD_ACTIVE_MASK; - - while (!IS_HPM_BITMASK_SET(base->MISC_CTRL1, SDXC_MISC_CTRL1_CARD_ACTIVE_MASK)) { - } -} - -/** - * @brief Inverse SDXC clock - * @param [in] base SDXC base - * @param [in] enable Enable/disable SDXC inverse clock - */ -static inline void sdxc_enable_inverse_clock(SDXC_Type *base, bool enable) -{ - if (enable) { - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; - } else { - base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK; - } -} - -/** - * @brief Check whether SDXC inverse clock is enabled or not - * @param [in] base SDXC base - * - * @retval true if inverse clock is enabled - */ -static inline bool sdxc_is_inverse_clock_enabled(SDXC_Type *base) -{ - return ((base->MISC_CTRL0 & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) != 0U); -} - -/** - * @brief Select the Card Clock Delay source - * @param [in] base SDXC base - * @param [in] loopback_from_pad true if the delay source is loopback from pad - */ -static inline void sdxc_select_cardclk_delay_source(SDXC_Type *base, bool loopback_from_pad) -{ - if (loopback_from_pad) { - base->MISC_CTRL0 &= ~SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; - } else { - base->MISC_CTRL0 |= SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK; - } -} - -/** - * @brief Set Card Clock delay chain - * @param [in] base SDXC base - * @param [in] num_delaycells Number of delay cells - */ -static inline void sdxc_set_cardclk_delay_chain(SDXC_Type *base, uint32_t num_delaycells) -{ - base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) | - SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(num_delaycells); -} - -/** - * @brief Set SDXC data strobe delay chain - * @param [in] base SDXC base - * @param [in] num_of_delaycells Number of delay cells for Data strobe - */ -static inline void sdxc_set_data_strobe_delay(SDXC_Type *base, uint8_t num_of_delaycells) -{ - base->MISC_CTRL1 = (base->MISC_CTRL1 & ~SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) | - SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(num_of_delaycells); -} - -static inline uint32_t sdxc_get_default_strobe_delay(SDXC_Type *base) -{ - (void) base; - uint32_t num_delaycells = 0; - if (IOC_PAD_FUNC_CTL_ALT_SELECT_GET(HPM_IOC->PAD[IOC_PAD_PC00].FUNC_CTL) == IOC_PC00_FUNC_CTL_SDC0_DS) { - num_delaycells = 2; - } - return num_delaycells; -} - -static inline uint32_t sdxc_get_default_cardclk_delay_chain(SDXC_Type *base, uint32_t clock_freq) -{ - (void) base; - uint32_t num_delaycells = 3; - if (clock_freq <= 52000000) { - num_delaycells = 26; - } - return num_delaycells; -} - -static inline bool sdxc_is_ddr50_supported(SDXC_Type *base) -{ - (void) base; - return true; -} - - -#if defined(__cplusplus) -} -#endif - - -#endif /* HPM_SDXC_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ses_reg.xml deleted file mode 100644 index 064e0a73fbc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ses_reg.xml +++ /dev/null @@ -1,60226 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ses_riscv_cpu_regs.xml deleted file mode 100644 index ec5ba6cb980..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_ses_riscv_cpu_regs.xml +++ /dev/null @@ -1,1098 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc.h deleted file mode 100644 index 2253cdbd751..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc.h +++ /dev/null @@ -1,814 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ -#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ -#define IRQn_GPIO0_X 7 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 8 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 9 /* GPIO0_Z IRQ */ -#define IRQn_MCAN0 10 /* MCAN0 IRQ */ -#define IRQn_MCAN1 11 /* MCAN1 IRQ */ -#define IRQn_MCAN2 12 /* MCAN2 IRQ */ -#define IRQn_MCAN3 13 /* MCAN3 IRQ */ -#define IRQn_MCAN4 14 /* MCAN4 IRQ */ -#define IRQn_MCAN5 15 /* MCAN5 IRQ */ -#define IRQn_MCAN6 16 /* MCAN6 IRQ */ -#define IRQn_MCAN7 17 /* MCAN7 IRQ */ -#define IRQn_PTPC 18 /* PTPC IRQ */ -#define IRQn_UART0 27 /* UART0 IRQ */ -#define IRQn_UART1 28 /* UART1 IRQ */ -#define IRQn_UART2 29 /* UART2 IRQ */ -#define IRQn_UART3 30 /* UART3 IRQ */ -#define IRQn_UART4 31 /* UART4 IRQ */ -#define IRQn_UART5 32 /* UART5 IRQ */ -#define IRQn_UART6 33 /* UART6 IRQ */ -#define IRQn_UART7 34 /* UART7 IRQ */ -#define IRQn_I2C0 35 /* I2C0 IRQ */ -#define IRQn_I2C1 36 /* I2C1 IRQ */ -#define IRQn_I2C2 37 /* I2C2 IRQ */ -#define IRQn_I2C3 38 /* I2C3 IRQ */ -#define IRQn_SPI0 39 /* SPI0 IRQ */ -#define IRQn_SPI1 40 /* SPI1 IRQ */ -#define IRQn_SPI2 41 /* SPI2 IRQ */ -#define IRQn_SPI3 42 /* SPI3 IRQ */ -#define IRQn_GPTMR0 43 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 44 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 45 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 46 /* GPTMR3 IRQ */ -#define IRQn_GPTMR4 47 /* GPTMR4 IRQ */ -#define IRQn_GPTMR5 48 /* GPTMR5 IRQ */ -#define IRQn_GPTMR6 49 /* GPTMR6 IRQ */ -#define IRQn_GPTMR7 50 /* GPTMR7 IRQ */ -#define IRQn_EWDG0 51 /* EWDG0 IRQ */ -#define IRQn_EWDG1 52 /* EWDG1 IRQ */ -#define IRQn_MBX0A 53 /* MBX0A IRQ */ -#define IRQn_MBX0B 54 /* MBX0B IRQ */ -#define IRQn_MBX1A 55 /* MBX1A IRQ */ -#define IRQn_MBX1B 56 /* MBX1B IRQ */ -#define IRQn_RNG 57 /* RNG IRQ */ -#define IRQn_HDMA 58 /* HDMA IRQ */ -#define IRQn_ADC0 59 /* ADC0 IRQ */ -#define IRQn_ADC1 60 /* ADC1 IRQ */ -#define IRQn_SDM 61 /* SDM IRQ */ -#define IRQn_OPAMP 62 /* OPAMP IRQ */ -#define IRQn_I2S0 63 /* I2S0 IRQ */ -#define IRQn_I2S1 64 /* I2S1 IRQ */ -#define IRQn_I2S2 65 /* I2S2 IRQ */ -#define IRQn_I2S3 66 /* I2S3 IRQ */ -#define IRQn_DAO 67 /* DAO IRQ */ -#define IRQn_PDM 68 /* PDM IRQ */ -#define IRQn_SMIX_DMA 69 /* SMIX_DMA IRQ */ -#define IRQn_SMIX_ASRC 70 /* SMIX_ASRC IRQ */ -#define IRQn_CAM0 71 /* CAM0 IRQ */ -#define IRQn_CAM1 72 /* CAM1 IRQ */ -#define IRQn_LCDC 73 /* LCDC IRQ */ -#define IRQn_LCDC1 74 /* LCDC1 IRQ */ -#define IRQn_PDMA 75 /* PDMA IRQ */ -#define IRQn_JPEG 76 /* JPEG IRQ */ -#define IRQn_GWCK0_FUNC 77 /* GWCK0_FUNC IRQ */ -#define IRQn_GWCK0_ERR 78 /* GWCK0_ERR IRQ */ -#define IRQn_GWCK1_FUNC 79 /* GWCK1_FUNC IRQ */ -#define IRQn_GWCK1_ERR 80 /* GWCK1_ERR IRQ */ -#define IRQn_MIPI_DSI0 81 /* MIPI_DSI0 IRQ */ -#define IRQn_MIPI_DSI1 82 /* MIPI_DSI1 IRQ */ -#define IRQn_MIPI_CSI0 83 /* MIPI_CSI0 IRQ */ -#define IRQn_MIPI_CSI0_AP 84 /* MIPI_CSI0_AP IRQ */ -#define IRQn_MIPI_CSI0_DIAG 85 /* MIPI_CSI0_DIAG IRQ */ -#define IRQn_MIPI_CSI1_AP 86 /* MIPI_CSI1_AP IRQ */ -#define IRQn_MIPI_CSI1_DIAG 87 /* MIPI_CSI1_DIAG IRQ */ -#define IRQn_MIPI_CSI1 88 /* MIPI_CSI1 IRQ */ -#define IRQn_LCB0 89 /* LCB0 IRQ */ -#define IRQn_LCB1 90 /* LCB1 IRQ */ -#define IRQn_GPU 91 /* GPU IRQ */ -#define IRQn_ENET0 92 /* ENET0 IRQ */ -#define IRQn_NTMR0 93 /* NTMR0 IRQ */ -#define IRQn_USB0 94 /* USB0 IRQ */ -#define IRQn_SDXC0 95 /* SDXC0 IRQ */ -#define IRQn_SDXC1 96 /* SDXC1 IRQ */ -#define IRQn_SDP 97 /* SDP IRQ */ -#define IRQn_XPI0 98 /* XPI0 IRQ */ -#define IRQn_XDMA 99 /* XDMA IRQ */ -#define IRQn_DDR 100 /* DDR IRQ */ -#define IRQn_FFA 101 /* FFA IRQ */ -#define IRQn_PSEC 102 /* PSEC IRQ */ -#define IRQn_TSNS 103 /* TSNS IRQ */ -#define IRQn_VAD 104 /* VAD IRQ */ -#define IRQn_PGPIO 105 /* PGPIO IRQ */ -#define IRQn_PWDG 106 /* PWDG IRQ */ -#define IRQn_PTMR 107 /* PTMR IRQ */ -#define IRQn_PUART 108 /* PUART IRQ */ -#define IRQn_FUSE 109 /* FUSE IRQ */ -#define IRQn_SECMON 110 /* SECMON IRQ */ -#define IRQn_RTC 111 /* RTC IRQ */ -#define IRQn_BGPIO 112 /* BGPIO IRQ */ -#define IRQn_BVIO 113 /* BVIO IRQ */ -#define IRQn_BROWNOUT 114 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 115 /* SYSCTL IRQ */ -#define IRQn_DEBUG0 116 /* DEBUG0 IRQ */ -#define IRQn_DEBUG1 117 /* DEBUG1 IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0xC0000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF00D0000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF411C000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) -/* BGPIO base address */ -#define HPM_BGPIO_BASE (0xF4214000UL) -/* BGPIO base pointer */ -#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_crc_regs.h" -/* Address of CRC instances */ -/* CRC base address */ -#define HPM_CRC_BASE (0xF000C000UL) -/* CRC base pointer */ -#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* UART4 base address */ -#define HPM_UART4_BASE (0xF0050000UL) -/* UART4 base pointer */ -#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) -/* UART5 base address */ -#define HPM_UART5_BASE (0xF0054000UL) -/* UART5 base pointer */ -#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) -/* UART6 base address */ -#define HPM_UART6_BASE (0xF0058000UL) -/* UART6 base pointer */ -#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) -/* UART7 base address */ -#define HPM_UART7_BASE (0xF005C000UL) -/* UART7 base pointer */ -#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF4124000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF0060000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF0064000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF0068000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF006C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0070000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0074000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0078000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF007C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF0080000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF0084000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* GPTMR2 base address */ -#define HPM_GPTMR2_BASE (0xF0088000UL) -/* GPTMR2 base pointer */ -#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) -/* GPTMR3 base address */ -#define HPM_GPTMR3_BASE (0xF008C000UL) -/* GPTMR3 base pointer */ -#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) -/* GPTMR4 base address */ -#define HPM_GPTMR4_BASE (0xF0090000UL) -/* GPTMR4 base pointer */ -#define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE) -/* GPTMR5 base address */ -#define HPM_GPTMR5_BASE (0xF0094000UL) -/* GPTMR5 base pointer */ -#define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE) -/* GPTMR6 base address */ -#define HPM_GPTMR6_BASE (0xF0098000UL) -/* GPTMR6 base pointer */ -#define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE) -/* GPTMR7 base address */ -#define HPM_GPTMR7_BASE (0xF009C000UL) -/* GPTMR7 base pointer */ -#define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE) -/* NTMR0 base address */ -#define HPM_NTMR0_BASE (0xF1110000UL) -/* NTMR0 base pointer */ -#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF4120000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) -/* MBX1A base address */ -#define HPM_MBX1A_BASE (0xF00A8000UL) -/* MBX1A base pointer */ -#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) -/* MBX1B base address */ -#define HPM_MBX1B_BASE (0xF00AC000UL) -/* MBX1B base pointer */ -#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) - -#include "hpm_ewdg_regs.h" -/* Address of EWDG instances */ -/* EWDG0 base address */ -#define HPM_EWDG0_BASE (0xF00B0000UL) -/* EWDG0 base pointer */ -#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) -/* EWDG1 base address */ -#define HPM_EWDG1_BASE (0xF00B4000UL) -/* EWDG1 base pointer */ -#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) -/* PEWDG base address */ -#define HPM_PEWDG_BASE (0xF4128000UL) -/* PEWDG base pointer */ -#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C4000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dmav2_regs.h" -/* Address of DMAV2 instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C8000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) -/* XDMA base address */ -#define HPM_XDMA_BASE (0xF3008000UL) -/* XDMA base pointer */ -#define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF00D8000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF00E0000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) - -#include "hpm_i2s_regs.h" -/* Address of I2S instances */ -/* I2S0 base address */ -#define HPM_I2S0_BASE (0xF0200000UL) -/* I2S0 base pointer */ -#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) -/* I2S1 base address */ -#define HPM_I2S1_BASE (0xF0204000UL) -/* I2S1 base pointer */ -#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) -/* I2S2 base address */ -#define HPM_I2S2_BASE (0xF0208000UL) -/* I2S2 base pointer */ -#define HPM_I2S2 ((I2S_Type *) HPM_I2S2_BASE) -/* I2S3 base address */ -#define HPM_I2S3_BASE (0xF020C000UL) -/* I2S3 base pointer */ -#define HPM_I2S3 ((I2S_Type *) HPM_I2S3_BASE) - -#include "hpm_dao_regs.h" -/* Address of DAO instances */ -/* DAO base address */ -#define HPM_DAO_BASE (0xF0210000UL) -/* DAO base pointer */ -#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) - -#include "hpm_pdm_regs.h" -/* Address of PDM instances */ -/* PDM base address */ -#define HPM_PDM_BASE (0xF0214000UL) -/* PDM base pointer */ -#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) - -#include "hpm_smix_regs.h" -/* Address of SMIX instances */ -/* SMIX base address */ -#define HPM_SMIX_BASE (0xF0218000UL) -/* SMIX base pointer */ -#define HPM_SMIX ((SMIX_Type *) HPM_SMIX_BASE) - -#include "hpm_mcan_regs.h" -/* Address of MCAN instances */ -/* MCAN0 base address */ -#define HPM_MCAN0_BASE (0xF0280000UL) -/* MCAN0 base pointer */ -#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) -/* MCAN1 base address */ -#define HPM_MCAN1_BASE (0xF0284000UL) -/* MCAN1 base pointer */ -#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) -/* MCAN2 base address */ -#define HPM_MCAN2_BASE (0xF0288000UL) -/* MCAN2 base pointer */ -#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) -/* MCAN3 base address */ -#define HPM_MCAN3_BASE (0xF028C000UL) -/* MCAN3 base pointer */ -#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) -/* MCAN4 base address */ -#define HPM_MCAN4_BASE (0xF0290000UL) -/* MCAN4 base pointer */ -#define HPM_MCAN4 ((MCAN_Type *) HPM_MCAN4_BASE) -/* MCAN5 base address */ -#define HPM_MCAN5_BASE (0xF0294000UL) -/* MCAN5 base pointer */ -#define HPM_MCAN5 ((MCAN_Type *) HPM_MCAN5_BASE) -/* MCAN6 base address */ -#define HPM_MCAN6_BASE (0xF0298000UL) -/* MCAN6 base pointer */ -#define HPM_MCAN6 ((MCAN_Type *) HPM_MCAN6_BASE) -/* MCAN7 base address */ -#define HPM_MCAN7_BASE (0xF029C000UL) -/* MCAN7 base pointer */ -#define HPM_MCAN7 ((MCAN_Type *) HPM_MCAN7_BASE) - -#include "hpm_ptpc_regs.h" -/* Address of PTPC instances */ -/* PTPC base address */ -#define HPM_PTPC_BASE (0xF02FC000UL) -/* PTPC base pointer */ -#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) - -#include "hpm_lcdc_regs.h" -/* Address of LCDC instances */ -/* LCDC base address */ -#define HPM_LCDC_BASE (0xF1000000UL) -/* LCDC base pointer */ -#define HPM_LCDC ((LCDC_Type *) HPM_LCDC_BASE) -/* LCDC1 base address */ -#define HPM_LCDC1_BASE (0xF1004000UL) -/* LCDC1 base pointer */ -#define HPM_LCDC1 ((LCDC_Type *) HPM_LCDC1_BASE) - -#include "hpm_cam_regs.h" -/* Address of CAM instances */ -/* CAM0 base address */ -#define HPM_CAM0_BASE (0xF1008000UL) -/* CAM0 base pointer */ -#define HPM_CAM0 ((CAM_Type *) HPM_CAM0_BASE) -/* CAM1 base address */ -#define HPM_CAM1_BASE (0xF100C000UL) -/* CAM1 base pointer */ -#define HPM_CAM1 ((CAM_Type *) HPM_CAM1_BASE) - -#include "hpm_pdma_regs.h" -/* Address of PDMA instances */ -/* PDMA base address */ -#define HPM_PDMA_BASE (0xF1010000UL) -/* PDMA base pointer */ -#define HPM_PDMA ((PDMA_Type *) HPM_PDMA_BASE) - -#include "hpm_jpeg_regs.h" -/* Address of JPEG instances */ -/* JPEG base address */ -#define HPM_JPEG_BASE (0xF1014000UL) -/* JPEG base pointer */ -#define HPM_JPEG ((JPEG_Type *) HPM_JPEG_BASE) - -#include "hpm_gwc_regs.h" -/* Address of GWC instances */ -/* GWC0 base address */ -#define HPM_GWC0_BASE (0xF1018000UL) -/* GWC0 base pointer */ -#define HPM_GWC0 ((GWC_Type *) HPM_GWC0_BASE) -/* GWC1 base address */ -#define HPM_GWC1_BASE (0xF101C000UL) -/* GWC1 base pointer */ -#define HPM_GWC1 ((GWC_Type *) HPM_GWC1_BASE) - -#include "hpm_mipi_dsi_regs.h" -/* Address of MIPI_DSI instances */ -/* MIPI_DSI0 base address */ -#define HPM_MIPI_DSI0_BASE (0xF1020000UL) -/* MIPI_DSI0 base pointer */ -#define HPM_MIPI_DSI0 ((MIPI_DSI_Type *) HPM_MIPI_DSI0_BASE) -/* MIPI_DSI1 base address */ -#define HPM_MIPI_DSI1_BASE (0xF1024000UL) -/* MIPI_DSI1 base pointer */ -#define HPM_MIPI_DSI1 ((MIPI_DSI_Type *) HPM_MIPI_DSI1_BASE) - -#include "hpm_mipi_csi_regs.h" -/* Address of MIPI_CSI instances */ -/* MIPI_CSI0 base address */ -#define HPM_MIPI_CSI0_BASE (0xF1028000UL) -/* MIPI_CSI0 base pointer */ -#define HPM_MIPI_CSI0 ((MIPI_CSI_Type *) HPM_MIPI_CSI0_BASE) -/* MIPI_CSI1 base address */ -#define HPM_MIPI_CSI1_BASE (0xF102C000UL) -/* MIPI_CSI1 base pointer */ -#define HPM_MIPI_CSI1 ((MIPI_CSI_Type *) HPM_MIPI_CSI1_BASE) - -#include "hpm_lvb_regs.h" -/* Address of LVB instances */ -/* LVB base address */ -#define HPM_LVB_BASE (0xF1030000UL) -/* LVB base pointer */ -#define HPM_LVB ((LVB_Type *) HPM_LVB_BASE) - -#include "hpm_pixelmux_regs.h" -/* Address of PIXELMUX instances */ -/* PIXEL_MUX base address */ -#define HPM_PIXEL_MUX_BASE (0xF1034000UL) -/* PIXEL_MUX base pointer */ -#define HPM_PIXEL_MUX ((PIXELMUX_Type *) HPM_PIXEL_MUX_BASE) - -#include "hpm_lcb_regs.h" -/* Address of LCB instances */ -/* LCB base address */ -#define HPM_LCB_BASE (0xF1038000UL) -/* LCB base pointer */ -#define HPM_LCB ((LCB_Type *) HPM_LCB_BASE) - -#include "hpm_gpu_regs.h" -/* Address of GPU instances */ -/* GPU base address */ -#define HPM_GPU_BASE (0xF1080000UL) -/* GPU base pointer */ -#define HPM_GPU ((GPU_Type *) HPM_GPU_BASE) - -#include "hpm_enet_regs.h" -/* Address of ENET instances */ -/* ENET0 base address */ -#define HPM_ENET0_BASE (0xF1100000UL) -/* ENET0 base pointer */ -#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF1120000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) - -#include "hpm_sdxc_regs.h" -/* Address of SDXC instances */ -/* SDXC0 base address */ -#define HPM_SDXC0_BASE (0xF1130000UL) -/* SDXC0 base pointer */ -#define HPM_SDXC0 ((SDXC_Type *) HPM_SDXC0_BASE) -/* SDXC1 base address */ -#define HPM_SDXC1_BASE (0xF1134000UL) -/* SDXC1 base pointer */ -#define HPM_SDXC1 ((SDXC_Type *) HPM_SDXC1_BASE) - -#include "hpm_ddrctl_regs.h" -/* Address of DDRCTL instances */ -/* DDRCTL base address */ -#define HPM_DDRCTL_BASE (0xF3010000UL) -/* DDRCTL base pointer */ -#define HPM_DDRCTL ((DDRCTL_Type *) HPM_DDRCTL_BASE) - -/* Address of ROMC instances */ -/* ROMC base address */ -#define HPM_ROMC_BASE (0xF3014000UL) - -#include "hpm_ffa_regs.h" -/* Address of FFA instances */ -/* FFA base address */ -#define HPM_FFA_BASE (0xF3018000UL) -/* FFA base pointer */ -#define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) - -#include "hpm_sdp_regs.h" -/* Address of SDP instances */ -/* SDP base address */ -#define HPM_SDP_BASE (0xF3040000UL) -/* SDP base pointer */ -#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) - -#include "hpm_sec_regs.h" -/* Address of SEC instances */ -/* SEC base address */ -#define HPM_SEC_BASE (0xF3044000UL) -/* SEC base pointer */ -#define HPM_SEC ((SEC_Type *) HPM_SEC_BASE) - -#include "hpm_mon_regs.h" -/* Address of MON instances */ -/* MON base address */ -#define HPM_MON_BASE (0xF3048000UL) -/* MON base pointer */ -#define HPM_MON ((MON_Type *) HPM_MON_BASE) - -#include "hpm_rng_regs.h" -/* Address of RNG instances */ -/* RNG base address */ -#define HPM_RNG_BASE (0xF304C000UL) -/* RNG base pointer */ -#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTP base address */ -#define HPM_OTP_BASE (0xF3050000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF3054000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF4118000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) -/* BIOC base address */ -#define HPM_BIOC_BASE (0xF4210000UL) -/* BIOC base pointer */ -#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) - -#include "hpm_pllctlv2_regs.h" -/* Address of PLLCTLV2 instances */ -/* PLLCTLV2 base address */ -#define HPM_PLLCTLV2_BASE (0xF40C0000UL) -/* PLLCTLV2 base pointer */ -#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF4100000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF4104000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR0 base address */ -#define HPM_PGPR0_BASE (0xF4110000UL) -/* PGPR0 base pointer */ -#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) -/* PGPR1 base address */ -#define HPM_PGPR1_BASE (0xF4114000UL) -/* PGPR1 base pointer */ -#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) - -#include "hpm_vad_regs.h" -/* Address of VAD instances */ -/* VAD base address */ -#define HPM_VAD_BASE (0xF412C000UL) -/* VAD base pointer */ -#define HPM_VAD ((VAD_Type *) HPM_VAD_BASE) - -#include "hpm_mipi_dsi_phy_regs.h" -/* Address of MIPI_DSI_PHY instances */ -/* MIPI_DSI_PHY0 base address */ -#define HPM_MIPI_DSI_PHY0_BASE (0xF4140000UL) -/* MIPI_DSI_PHY0 base pointer */ -#define HPM_MIPI_DSI_PHY0 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY0_BASE) -/* MIPI_DSI_PHY1 base address */ -#define HPM_MIPI_DSI_PHY1_BASE (0xF4144000UL) -/* MIPI_DSI_PHY1 base pointer */ -#define HPM_MIPI_DSI_PHY1 ((MIPI_DSI_PHY_Type *) HPM_MIPI_DSI_PHY1_BASE) - -#include "hpm_mipi_csi_phy_regs.h" -/* Address of MIPI_CSI_PHY instances */ -/* MIPI_CSI_PHY0 base address */ -#define HPM_MIPI_CSI_PHY0_BASE (0xF4148000UL) -/* MIPI_CSI_PHY0 base pointer */ -#define HPM_MIPI_CSI_PHY0 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY0_BASE) -/* MIPI_CSI_PHY1 base address */ -#define HPM_MIPI_CSI_PHY1_BASE (0xF414C000UL) -/* MIPI_CSI_PHY1 base pointer */ -#define HPM_MIPI_CSI_PHY1 ((MIPI_CSI_PHY_Type *) HPM_MIPI_CSI_PHY1_BASE) - -#include "hpm_ddrphy_regs.h" -/* Address of DDRPHY instances */ -/* DDRPHY base address */ -#define HPM_DDRPHY_BASE (0xF4150000UL) -/* DDRPHY base pointer */ -#define HPM_DDRPHY ((DDRPHY_Type *) HPM_DDRPHY_BASE) - -#include "hpm_tsns_regs.h" -/* Address of TSNS instances */ -/* TSNS base address */ -#define HPM_TSNS_BASE (0xF4154000UL) -/* TSNS base pointer */ -#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) - -#include "hpm_bacc_regs.h" -/* Address of BACC instances */ -/* BACC base address */ -#define HPM_BACC_BASE (0xF4200000UL) -/* BACC base pointer */ -#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) - -#include "hpm_bpor_regs.h" -/* Address of BPOR instances */ -/* BPOR base address */ -#define HPM_BPOR_BASE (0xF4204000UL) -/* BPOR base pointer */ -#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) - -#include "hpm_bcfg_regs.h" -/* Address of BCFG instances */ -/* BCFG base address */ -#define HPM_BCFG_BASE (0xF4208000UL) -/* BCFG base pointer */ -#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) - -#include "hpm_butn_regs.h" -/* Address of BUTN instances */ -/* BUTN base address */ -#define HPM_BUTN_BASE (0xF420C000UL) -/* BUTN base pointer */ -#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE) - -#include "hpm_bgpr_regs.h" -/* Address of BGPR instances */ -/* BGPR base address */ -#define HPM_BGPR_BASE (0xF4218000UL) -/* BGPR base pointer */ -#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE) - -#include "hpm_rtc_regs.h" -/* Address of RTC instances */ -/* RTCSHW base address */ -#define HPM_RTCSHW_BASE (0xF421C000UL) -/* RTCSHW base pointer */ -#define HPM_RTCSHW ((RTC_Type *) HPM_RTCSHW_BASE) -/* RTC base address */ -#define HPM_RTC_BASE (0xF4244000UL) -/* RTC base pointer */ -#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) - -#include "hpm_bsec_regs.h" -/* Address of BSEC instances */ -/* BSEC base address */ -#define HPM_BSEC_BASE (0xF4240000UL) -/* BSEC base pointer */ -#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) - -#include "hpm_bkey_regs.h" -/* Address of BKEY instances */ -/* BKEY base address */ -#define HPM_BKEY_BASE (0xF4248000UL) -/* BKEY base pointer */ -#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) - -#include "hpm_bmon_regs.h" -/* Address of BMON instances */ -/* BMON base address */ -#define HPM_BMON_BASE (0xF424C000UL) -/* BMON base pointer */ -#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) - -#include "hpm_tamp_regs.h" -/* Address of TAMP instances */ -/* TAMP base address */ -#define HPM_TAMP_BASE (0xF4250000UL) -/* TAMP base pointer */ -#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) - -#include "hpm_mono_regs.h" -/* Address of MONO instances */ -/* MONO base address */ -#define HPM_MONO_BASE (0xF4254000UL) -/* MONO base pointer */ -#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc_feature.h deleted file mode 100644 index 7525cdf9b43..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc_feature.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" -#include "hpm_soc_ip_feature.h" - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * I2S Section - */ -#define I2S_SOC_MAX_CHANNEL_NUM (16U) -#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) -#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) -#define PDM_I2S HPM_I2S0 -#define DAO_I2S HPM_I2S1 -#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) -#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) -#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (5U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (24U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) -#define PWM_SOC_OUTPUT_MAX_COUNT (24U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (32U) -#define DMA_SOC_MAX_COUNT (2U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) -#define DMA_SOC_HAS_IDLE_FLAG (1U) - -/* - * PDMA Section - */ -#define PDMA_SOC_PS_MAX_COUNT (2U) -#define PDMA_SOC_SUPPORT_BS16 (0U) - -/* - * LCDC Section - */ -#define LCDC_SOC_MAX_LAYER_COUNT (8U) -#define LCDC_SOC_MAX_CSC_LAYER_COUNT (2U) -#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) -#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) - -/* - * USB Section - */ -#define USB_SOC_MAX_COUNT (1U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* - * ENET Section - */ -#define ENET_SOC_RGMII_EN (1U) -#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) -#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) -#define ENET_SOC_ADDR_MAX_COUNT (5U) -#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) -#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) -#define ENET_SOC_ALT_EHD_DES_LEN (8U) -#define ENET_SOC_PPS_MAX_COUNT (4L) -#define ENET_SOC_PPS1_EN (0U) - -/* - * ADC Section - */ -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_SEQ_HCFG_EN (1U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) -#define ADC_SOC_NO_HW_TRIG_SRC (1U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_TEMP_CH_EN (0U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * SDP Section - */ -#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) -#define SDP_HAS_SM3_SUPPORT (1U) -#define SDP_HAS_SM4_SUPPORT (1U) - -/* - * SOC Privilege mode - */ -#define SOC_HAS_S_MODE (1U) - -/* - * DAC Section - */ -#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) -#define DAC_SOC_MAX_DATA (4095U) -#define DAC_SOC_MAX_BUFF_COUNT (65536U) -#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) - - -/* - * SDXC Section - */ -#define SDXC_SOC_HAS_MISC_CTRL0 (1) -#define SDXC_SOC_HAS_MISC_CTRL1 (1) -#define SDXC_SOC_MAX_COUNT (2) - -/* - * UART Section - */ -#define UART_SOC_FIFO_SIZE (16U) - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU) -#define SPI_SOC_FIFO_DEPTH (8U) - -/* - * EWDG Section - */ -#define EWDG_SOC_CLK_DIV_VAL_MAX (5U) -#define EWDG_SOC_OVERTIME_REG_WIDTH (16U) -#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (0U) - - -/* - * MCAN Section - */ -#define MCAN_SOC_MSG_BUF_IN_IP (0U) -#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) -#define MCAN_SOC_MAX_COUNT (8U) -#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT - -/* - * OTP Section - */ -#define OTP_SOC_MAC0_IDX (65U) -#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ - -#define OTP_SOC_UUID_IDX (88U) -#define OTP_SOC_UUID_LEN (16U) /* in bytes */ - -/** - * PWM Section - * - */ -#define PWM_SOC_HRPWM_SUPPORT (0U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) -#define PWM_SOC_TIMER_RESET_SUPPORT (0U) - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc_ip_feature.h deleted file mode 100644 index 48d27578337..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_soc_ip_feature.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* UART related feature */ -#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 -#define HPM_IP_FEATURE_UART_FCRR 1 -#define HPM_IP_FEATURE_UART_RX_EN 1 - -/* I2C related feature */ -#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 - -/* SPI related feature */ -#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 -#define HPM_IP_FEATURE_SPI_CS_SELECT 1 -#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 - -/* GPTMR related feature */ -#define HPM_IP_FEATURE_GPTMR_MONITOR 1 -#define HPM_IP_FEATURE_GPTMR_OP_MODE 1 - -/* DAO related feature */ -#define HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG 1 - -/* CAM related feature */ -#define HPM_IP_FEATURE_CAM_INV_DEN 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sysctl_drv.c deleted file mode 100644 index fed8e823434..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sysctl_drv.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | ((cpu & 1) << 24)) - -hpm_stat_t sysctl_get_cpu0_gpr(SYSCTL_Type *ptr, uint32_t *data, uint32_t size) -{ - uint32_t i; - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[0].GPR[i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[0].GPR); - if ((data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[0].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[0].GPR); - uint32_t gpr_mask; - if ((data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[0].GPR[start + i] = *(data + i); - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return status_success; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config) -{ - ptr->MONITOR[monitor_index].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & - ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | - SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | - (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | - SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | - SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | - SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | - SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | - SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t -sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_target_t target, bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = { 0 }; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -hpm_stat_t sysctl_set_cpu0_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - ptr->CPU[0].GPR[0] = entry; - ptr->CPU[0].GPR[1] = SYSCTL_CPU_RELEASE_KEY(0); - return status_success; -} - -hpm_stat_t sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - ptr->CPU[0].LP = (ptr->CPU[0].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); - return status_success; -} - -hpm_stat_t -sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable) -{ - uint32_t index, offset; - if (resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource) -{ - uint32_t index, offset; - bool enable; - - index = (resource - sysctl_resource_linkable_start) / 32; - offset = (resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by) -{ - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | - (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) -{ - if (source >= clock_source_adc_clk_end) { - return status_invalid_argument; - } - uint32_t adc_index = (uint32_t)(node - clock_node_adc_start); - if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { - return status_invalid_argument; - } - - ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); - - return status_success; -} - -hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source) -{ - if (source >= clock_source_i2s_clk_end) { - return status_invalid_argument; - } - uint32_t i2s_index = (uint32_t)(node - clock_node_i2s_start); - if (i2s_index >= ARRAY_SIZE(ptr->I2SCLK)) { - return status_invalid_argument; - } - - ptr->I2SCLK[i2s_index] = (ptr->I2SCLK[i2s_index] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(source); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sysctl_drv.h deleted file mode 100644 index 1aff71cb26b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/hpm_sysctl_drv.h +++ /dev/null @@ -1,1220 +0,0 @@ -/** - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */ -typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - sysctl_retention_domain_con = 4, - sysctl_retention_domain_vis = 5, - sysctl_retention_domain_gpu = 7, - sysctl_retention_domain_xtal24m = 9, - sysctl_retention_domain_pll0 = 10, - sysctl_retention_domain_pll1 = 11, - sysctl_retention_domain_pll2 = 12, - sysctl_retention_domain_pll3 = 13, - sysctl_retention_domain_pll4 = 14, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_con, - sysctl_reset_domain_vis, - sysctl_reset_domain_cpu0, - sysctl_reset_domain_gpu -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0, - sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0, - sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0, - sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC, - sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0, - sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL, - sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0, - sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0, - sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1, - sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1, - sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1, - sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2, - sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2, - sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2, - sysctl_resource_pll3 = SYSCTL_RESOURCE_CLK_SRC_PLL3, - sysctl_resource_clk0_pll3 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL3, - sysctl_resource_pll4 = SYSCTL_RESOURCE_CLK_SRC_PLL4, - sysctl_resource_clk0_pll4 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL4, - sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF, - sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF, - sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF, - sysctl_resource_pll3_ref = SYSCTL_RESOURCE_CLK_SRC_PLL3_REF, - sysctl_resource_pll4_ref = SYSCTL_RESOURCE_CLK_SRC_PLL4_REF, - - sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0, - sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0, - sysctl_resource_clk_top_gpu0 = SYSCTL_RESOURCE_CLK_TOP_GPU0, - sysctl_resource_clk_top_axif = SYSCTL_RESOURCE_CLK_TOP_AXIF, - sysctl_resource_clk_top_axis = SYSCTL_RESOURCE_CLK_TOP_AXIS, - sysctl_resource_clk_top_axic = SYSCTL_RESOURCE_CLK_TOP_AXIC, - sysctl_resource_clk_top_axiv = SYSCTL_RESOURCE_CLK_TOP_AXIV, - sysctl_resource_clk_top_axid = SYSCTL_RESOURCE_CLK_TOP_AXID, - sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0, - sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1, - sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2, - sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3, - sysctl_resource_clk_top_can4 = SYSCTL_RESOURCE_CLK_TOP_CAN4, - sysctl_resource_clk_top_can5 = SYSCTL_RESOURCE_CLK_TOP_CAN5, - sysctl_resource_clk_top_can6 = SYSCTL_RESOURCE_CLK_TOP_CAN6, - sysctl_resource_clk_top_can7 = SYSCTL_RESOURCE_CLK_TOP_CAN7, - sysctl_resource_clk_top_lin0 = SYSCTL_RESOURCE_CLK_TOP_LIN0, - sysctl_resource_clk_top_lin1 = SYSCTL_RESOURCE_CLK_TOP_LIN1, - sysctl_resource_clk_top_lin2 = SYSCTL_RESOURCE_CLK_TOP_LIN2, - sysctl_resource_clk_top_lin3 = SYSCTL_RESOURCE_CLK_TOP_LIN3, - sysctl_resource_clk_top_lin4 = SYSCTL_RESOURCE_CLK_TOP_LIN4, - sysctl_resource_clk_top_lin5 = SYSCTL_RESOURCE_CLK_TOP_LIN5, - sysctl_resource_clk_top_lin6 = SYSCTL_RESOURCE_CLK_TOP_LIN6, - sysctl_resource_clk_top_lin7 = SYSCTL_RESOURCE_CLK_TOP_LIN7, - sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0, - sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1, - sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2, - sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3, - sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0, - sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1, - sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2, - sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3, - sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0, - sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1, - sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2, - sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3, - sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4, - sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5, - sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6, - sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7, - sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0, - sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1, - sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2, - sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3, - sysctl_resource_clk_top_gptmr4 = SYSCTL_RESOURCE_CLK_TOP_TMR4, - sysctl_resource_clk_top_gptmr5 = SYSCTL_RESOURCE_CLK_TOP_TMR5, - sysctl_resource_clk_top_gptmr6 = SYSCTL_RESOURCE_CLK_TOP_TMR6, - sysctl_resource_clk_top_gptmr7 = SYSCTL_RESOURCE_CLK_TOP_TMR7, - sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0, - sysctl_resource_clk_top_xram = SYSCTL_RESOURCE_CLK_TOP_XRAM, - sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0, - sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1, - sysctl_resource_clk_top_aud0 = SYSCTL_RESOURCE_CLK_TOP_AUD0, - sysctl_resource_clk_top_aud1 = SYSCTL_RESOURCE_CLK_TOP_AUD1, - sysctl_resource_clk_top_aud2 = SYSCTL_RESOURCE_CLK_TOP_AUD2, - sysctl_resource_clk_top_aud3 = SYSCTL_RESOURCE_CLK_TOP_AUD3, - sysctl_resource_clk_top_eth0 = SYSCTL_RESOURCE_CLK_TOP_ETH0, - sysctl_resource_clk_top_ptp0 = SYSCTL_RESOURCE_CLK_TOP_PTP0, - sysctl_resource_clk_top_sdc0 = SYSCTL_RESOURCE_CLK_TOP_SDC0, - sysctl_resource_clk_top_sdc1 = SYSCTL_RESOURCE_CLK_TOP_SDC1, - sysctl_resource_clk_top_ntm0 = SYSCTL_RESOURCE_CLK_TOP_NTM0, - sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0, - sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1, - sysctl_resource_clk_top_cam0 = SYSCTL_RESOURCE_CLK_TOP_CAM0, - sysctl_resource_clk_top_cam1 = SYSCTL_RESOURCE_CLK_TOP_CAM1, - sysctl_resource_clk_top_lcd0 = SYSCTL_RESOURCE_CLK_TOP_LCD0, - sysctl_resource_clk_top_lcd1 = SYSCTL_RESOURCE_CLK_TOP_LCD1, - sysctl_resource_clk_top_csi0 = SYSCTL_RESOURCE_CLK_TOP_CSI0, - sysctl_resource_clk_top_csi1 = SYSCTL_RESOURCE_CLK_TOP_CSI1, - sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0, - sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1, - sysctl_resource_clk_top_i2s0 = SYSCTL_RESOURCE_CLK_TOP_I2S0, - sysctl_resource_clk_top_i2s1 = SYSCTL_RESOURCE_CLK_TOP_I2S1, - sysctl_resource_clk_top_i2s2 = SYSCTL_RESOURCE_CLK_TOP_I2S2, - sysctl_resource_clk_top_i2s3 = SYSCTL_RESOURCE_CLK_TOP_I2S3, - - - sysctl_resource_linkable_start = 256, - sysctl_resource_axis = SYSCTL_RESOURCE_AXIS, - sysctl_resource_axic = SYSCTL_RESOURCE_AXIC, - sysctl_resource_axiv = SYSCTL_RESOURCE_AXIV, - sysctl_resource_axig = SYSCTL_RESOURCE_AXIG, - sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0, - sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0, - sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0, - sysctl_resource_ddr0 = SYSCTL_RESOURCE_DDR0, - sysctl_resource_xram = SYSCTL_RESOURCE_XRAM, - sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0, - sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1, - sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2, - sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3, - sysctl_resource_can4 = SYSCTL_RESOURCE_CAN4, - sysctl_resource_can5 = SYSCTL_RESOURCE_CAN5, - sysctl_resource_can6 = SYSCTL_RESOURCE_CAN6, - sysctl_resource_can7 = SYSCTL_RESOURCE_CAN7, - sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC, - sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0, - sysctl_resource_oamp = SYSCTL_RESOURCE_OAMP, - sysctl_resource_lin0 = SYSCTL_RESOURCE_LIN0, - sysctl_resource_lin1 = SYSCTL_RESOURCE_LIN1, - sysctl_resource_lin2 = SYSCTL_RESOURCE_LIN2, - sysctl_resource_lin3 = SYSCTL_RESOURCE_LIN3, - sysctl_resource_lin4 = SYSCTL_RESOURCE_LIN4, - sysctl_resource_lin5 = SYSCTL_RESOURCE_LIN5, - sysctl_resource_lin6 = SYSCTL_RESOURCE_LIN6, - sysctl_resource_lin7 = SYSCTL_RESOURCE_LIN7, - sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0, - sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1, - sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2, - sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3, - sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0, - sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1, - sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2, - sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3, - sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0, - sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1, - sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2, - sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3, - sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4, - sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5, - sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6, - sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7, - sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0, - sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1, - sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0, - sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1, - sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0, - sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1, - sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2, - sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3, - sysctl_resource_gptmr4 = SYSCTL_RESOURCE_TMR4, - sysctl_resource_gptmr5 = SYSCTL_RESOURCE_TMR5, - sysctl_resource_gptmr6 = SYSCTL_RESOURCE_TMR6, - sysctl_resource_gptmr7 = SYSCTL_RESOURCE_TMR7, - sysctl_resource_i2s0 = SYSCTL_RESOURCE_I2S0, - sysctl_resource_i2s1 = SYSCTL_RESOURCE_I2S1, - sysctl_resource_i2s2 = SYSCTL_RESOURCE_I2S2, - sysctl_resource_i2s3 = SYSCTL_RESOURCE_I2S3, - sysctl_resource_pdm0 = SYSCTL_RESOURCE_PDM0, - sysctl_resource_dao0 = SYSCTL_RESOURCE_DAO0, - sysctl_resource_smix = SYSCTL_RESOURCE_SMIX, - sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0, - sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0, - sysctl_resource_kman = SYSCTL_RESOURCE_KMAN, - sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO, - sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0, - sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1, - sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0, - sysctl_resource_dma0 = SYSCTL_RESOURCE_HDMA, - sysctl_resource_dma1 = SYSCTL_RESOURCE_XDMA, - sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0, - sysctl_resource_ffa0 = SYSCTL_RESOURCE_FFA0, - sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS, - sysctl_resource_eth0 = SYSCTL_RESOURCE_ETH0, - sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0, - sysctl_resource_sdc0 = SYSCTL_RESOURCE_SDC0, - sysctl_resource_sdc1 = SYSCTL_RESOURCE_SDC1, - sysctl_resource_ntm0 = SYSCTL_RESOURCE_NTM0, - sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0, - sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1, - sysctl_resource_cam0 = SYSCTL_RESOURCE_CAM0, - sysctl_resource_cam1 = SYSCTL_RESOURCE_CAM1, - sysctl_resource_pdma = SYSCTL_RESOURCE_PDMA, - sysctl_resource_jpeg = SYSCTL_RESOURCE_JPEG, - sysctl_resource_lcd0 = SYSCTL_RESOURCE_LCD0, - sysctl_resource_lcd1 = SYSCTL_RESOURCE_LCD1, - sysctl_resource_gwc0 = SYSCTL_RESOURCE_GWC0, - sysctl_resource_gwc1 = SYSCTL_RESOURCE_GWC1, - sysctl_resource_csi0 = SYSCTL_RESOURCE_CSI0, - sysctl_resource_csi1 = SYSCTL_RESOURCE_CSI1, - sysctl_resource_dsi0 = SYSCTL_RESOURCE_DSI0, - sysctl_resource_dsi1 = SYSCTL_RESOURCE_DSI1, - sysctl_resource_lvb0 = SYSCTL_RESOURCE_LVB0, - sysctl_resource_lcb0 = SYSCTL_RESOURCE_LCB0, - sysctl_resource_gpu0 = SYSCTL_RESOURCE_GPU0, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, - sysctl_resource_mode_force_on, - sysctl_resource_mode_force_off, -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_cpu0 = SYSCTL_CLOCK_CLK_TOP_CPU0, - clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, - clock_node_gpu0 = SYSCTL_CLOCK_CLK_TOP_GPU0, - clock_node_axif, - clock_node_axis, - clock_node_axic, - clock_node_axiv, - clock_node_axid, - clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, - clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, - clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, - clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, - clock_node_can4, - clock_node_can5, - clock_node_can6, - clock_node_can7, - clock_node_lin0 = SYSCTL_CLOCK_CLK_TOP_LIN0, - clock_node_lin1 = SYSCTL_CLOCK_CLK_TOP_LIN1, - clock_node_lin2 = SYSCTL_CLOCK_CLK_TOP_LIN2, - clock_node_lin3 = SYSCTL_CLOCK_CLK_TOP_LIN3, - clock_node_lin4, - clock_node_lin5, - clock_node_lin6, - clock_node_lin7, - clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, - clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, - clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, - clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, - clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, - clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, - clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, - clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, - clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, - clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, - clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, - clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, - clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, - clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, - clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, - clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, - - clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, - clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, - clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, - clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, - clock_node_gptmr4 = SYSCTL_CLOCK_CLK_TOP_TMR4, - clock_node_gptmr5 = SYSCTL_CLOCK_CLK_TOP_TMR5, - clock_node_gptmr6 = SYSCTL_CLOCK_CLK_TOP_TMR6, - clock_node_gptmr7 = SYSCTL_CLOCK_CLK_TOP_TMR7, - clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, - clock_node_xram, - clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, - clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, - clock_node_aud0, - clock_node_aud1, - clock_node_aud2, - clock_node_aud3, - clock_node_eth0, - clock_node_ptp0, - clock_node_sdc0, - clock_node_sdc1, - clock_node_ntm0, - clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, - clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, - clock_node_cam0, - clock_node_cam1, - clock_node_lcd0, - clock_node_lcd1, - clock_node_csi0, - clock_node_csi1, - - clock_node_adc_start, - clock_node_adc0 = clock_node_adc_start, - clock_node_adc1, - - clock_node_i2s_start, - clock_node_i2s0 = clock_node_i2s_start, - clock_node_i2s1, - clock_node_i2s2, - clock_node_i2s3, - - clock_node_end, - clock_node_invalid = 0xff, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll1_clk0 = 2, - clock_source_pll1_clk1 = 3, - clock_source_pll2_clk0 = 4, - clock_source_pll2_clk1 = 5, - clock_source_pll3_clk0 = 6, - clock_source_pll4_clk0 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC clock sources - */ -typedef enum { - clock_source_adc_ana_clock = 0, - clock_source_adc_ahb_clock = 1, - clock_source_adc_clk_end, -} clock_source_adc_t; - -/** - * @brief I2S clock sources - */ -typedef enum { - clock_source_i2s_audn_clock = 0, - clock_source_i2s_audx_clock = 1, - clock_source_i2s_clk_end, -} clock_source_i2s_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -/* FIXME */ -typedef enum { - monitor_target_clk_32k = 0, - monitor_target_clk_irc24m = 1, - monitor_target_clk_xtal_24m = 2, - monitor_target_clk_usb0_phy = 3, - monitor_target_clk_usb1_phy = 4, - monitor_target_clk0_osc0 = 8, - monitor_target_clk0_pll0 = 9, - monitor_target_clk0_pll1 = 10, - monitor_target_clk1_pll1 = 11, - monitor_target_clk0_pll2 = 12, - monitor_target_clk1_pll2 = 13, - monitor_target_clk0_pll3 = 14, - monitor_target_clk0_pll4 = 15, - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_cpu1 = 130, - monitor_target_clk_top_mchtmr1 = 131, - monitor_target_clk_top_axi0 = 132, - monitor_target_clk_top_axi1 = 133, - monitor_target_clk_top_axi2 = 134, - monitor_target_clk_top_ahb0 = 135, - monitor_target_clk_top_dram = 136, - monitor_target_clk_top_xpi0 = 137, - monitor_target_clk_top_xpi1 = 138, - monitor_target_clk_top_gptmr0 = 139, - monitor_target_clk_top_gptmr1 = 140, - monitor_target_clk_top_gptmr2 = 141, - monitor_target_clk_top_gptmr3 = 142, - monitor_target_clk_top_gptmr4 = 143, - monitor_target_clk_top_gptmr5 = 144, - monitor_target_clk_top_gptmr6 = 145, - monitor_target_clk_top_gptmr7 = 146, - monitor_target_clk_top_uart0 = 147, - monitor_target_clk_top_uart1 = 148, - monitor_target_clk_top_uart2 = 149, - monitor_target_clk_top_uart3 = 150, - monitor_target_clk_top_uart4 = 151, - monitor_target_clk_top_uart5 = 152, - monitor_target_clk_top_uart6 = 153, - monitor_target_clk_top_uart7 = 154, - monitor_target_clk_top_uart8 = 155, - monitor_target_clk_top_uart9 = 156, - monitor_target_clk_top_uarta = 157, - monitor_target_clk_top_uartb = 158, - monitor_target_clk_top_uartc = 159, - monitor_target_clk_top_uartd = 160, - monitor_target_clk_top_uarte = 161, - monitor_target_clk_top_uartf = 162, - monitor_target_clk_top_i2c0 = 163, - monitor_target_clk_top_i2c1 = 164, - monitor_target_clk_top_i2c2 = 165, - monitor_target_clk_top_i2c3 = 166, - monitor_target_clk_top_spi0 = 167, - monitor_target_clk_top_spi1 = 168, - monitor_target_clk_top_spi2 = 169, - monitor_target_clk_top_spi3 = 170, - monitor_target_clk_top_can0 = 171, - monitor_target_clk_top_can1 = 172, - monitor_target_clk_top_can2 = 173, - monitor_target_clk_top_can3 = 174, - monitor_target_clk_top_ptpc = 175, - monitor_target_clk_top_ana0 = 176, - monitor_target_clk_top_ana1 = 177, - monitor_target_clk_top_ana2 = 178, - monitor_target_clk_top_aud0 = 179, - monitor_target_clk_top_aud1 = 180, - monitor_target_clk_top_aud2 = 181, - monitor_target_clk_top_dis0 = 182, - monitor_target_clk_top_cam0 = 183, - monitor_target_clk_top_cam1 = 184, - monitor_target_clk_top_eth0 = 185, - monitor_target_clk_top_eth1 = 186, - monitor_target_clk_top_ptp0 = 187, - monitor_target_clk_top_ptp1 = 188, - monitor_target_clk_top_ref0 = 189, - monitor_target_clk_top_ref1 = 190, - monitor_target_clk_top_ntmr0 = 191, - monitor_target_clk_top_ntmr1 = 192, - monitor_target_clk_top_sdxc0 = 193, - monitor_target_clk_top_sdxc1 = 194, -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | - (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit_high, - uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_cpu_lp_clear_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_cpu_lp_set_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_cpu_lp_retain_domain(SYSCTL_Type *ptr, - uint8_t cpu_index, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - uint8_t set_mask = 0x1; - if ((domain < sysctl_retention_domain_xtal24m) && (domain != sysctl_retention_domain_con)) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, clock_node_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Preserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Unpreserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index, - uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num % 32); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - ptr->CPU[0].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); - -/** - * @brief Set ADC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); - - -/** - * @brief Set I2S clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source); - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode); - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource, bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); - -/** - * @brief Save data to CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved from CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/soc_modules.list deleted file mode 100644 index 3ca99879b6d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/soc_modules.list +++ /dev/null @@ -1,73 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_CRC=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_EWDG=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMAV2=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_I2S=y -HPMSOC_HAS_HPMSDK_DAO=y -HPMSOC_HAS_HPMSDK_PDM=y -HPMSOC_HAS_HPMSDK_SMIX=y -HPMSOC_HAS_HPMSDK_MCAN=y -HPMSOC_HAS_HPMSDK_PTPC=y -HPMSOC_HAS_HPMSDK_LCDC=y -HPMSOC_HAS_HPMSDK_CAM=y -HPMSOC_HAS_HPMSDK_PDMA=y -HPMSOC_HAS_HPMSDK_JPEG=y -HPMSOC_HAS_HPMSDK_GWC=y -HPMSOC_HAS_HPMSDK_MIPI_DSI=y -HPMSOC_HAS_HPMSDK_MIPI_CSI=y -HPMSOC_HAS_HPMSDK_LVB=y -HPMSOC_HAS_HPMSDK_PIXELMUX=y -HPMSOC_HAS_HPMSDK_LCB=y -HPMSOC_HAS_HPMSDK_GPU=y -HPMSOC_HAS_HPMSDK_ENET=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_SDXC=y -HPMSOC_HAS_HPMSDK_DDRCTL=y -HPMSOC_HAS_HPMSDK_FFA=y -HPMSOC_HAS_HPMSDK_SDP=y -HPMSOC_HAS_HPMSDK_SEC=y -HPMSOC_HAS_HPMSDK_MON=y -HPMSOC_HAS_HPMSDK_RNG=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_PLLCTLV2=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_VAD=y -HPMSOC_HAS_HPMSDK_MIPI_DSI_PHY=y -HPMSOC_HAS_HPMSDK_MIPI_CSI_PHY=y -HPMSOC_HAS_HPMSDK_DDRPHY=y -HPMSOC_HAS_HPMSDK_TSNS=y -HPMSOC_HAS_HPMSDK_BACC=y -HPMSOC_HAS_HPMSDK_BPOR=y -HPMSOC_HAS_HPMSDK_BCFG=y -HPMSOC_HAS_HPMSDK_BUTN=y -HPMSOC_HAS_HPMSDK_BGPR=y -HPMSOC_HAS_HPMSDK_RTC=y -HPMSOC_HAS_HPMSDK_BSEC=y -HPMSOC_HAS_HPMSDK_BKEY=y -HPMSOC_HAS_HPMSDK_BMON=y -HPMSOC_HAS_HPMSDK_TAMP=y -HPMSOC_HAS_HPMSDK_MONO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/system.c deleted file mode 100644 index 7bf5544bc08..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/system.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif - -#ifdef USE_S_MODE_IRQ - disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#else - disable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - - disable_irq_from_intc(); -#ifdef USE_S_MODE_IRQ - disable_s_irq_from_intc(); -#endif - - enable_plic_feature(); - enable_irq_from_intc(); - -#ifdef USE_S_MODE_IRQ - delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); - enable_s_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#endif -#else -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash.ld deleted file mode 100644 index a82c0f8bd7f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash.ld +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x0120000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_sdram_uf2.ld deleted file mode 100644 index 49bfb334a31..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_sdram_uf2.ld +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 32M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 32M), LENGTH = 32M - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_sdram_xip.ld deleted file mode 100644 index d7cadce830e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_sdram_xip.ld +++ /dev/null @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x1200000, LENGTH = 512K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 32M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 32M), LENGTH = 32M - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index f47b1aa292d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_xip.ld deleted file mode 100644 index eee332fa3ed..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/flash_xip.ld +++ /dev/null @@ -1,303 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/ram.ld deleted file mode 100644 index d4ababea030..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/ram.ld +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00080000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01240000, LENGTH = 256K - AHB_SRAM (w) : ORIGIN = 0xF0400000, LENGTH = 32k - APB_SRAM (w): ORIGIN = 0xF4130000, LENGTH = 16k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .apb_sram (NOLOAD) : { - KEEP(*(.backup_sram)) - } > APB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/start.S deleted file mode 100644 index 531d6f5e481..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/gcc/start.S +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_sdram_uf2.icf deleted file mode 100644 index 3208e3322d0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_sdram_uf2.icf +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 256M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 512k]; /* AXI SRAM */ -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 32M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 32M size 32M]; -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; -define region APB_SRAM = mem:[from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_sdram_xip.icf deleted file mode 100644 index cdc518f7ea9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_sdram_xip.icf +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 256M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x2000 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 512k]; /* AXI SRAM */ -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 32M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 32M size 32M]; -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; -define region APB_SRAM = mem:[from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_uf2.icf deleted file mode 100644 index dbf17c4cbe3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01240000 size 256k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x01200000 size 256k]; /* AXI SRAM0 */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; -define region APB_SRAM = mem:[from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_xip.icf deleted file mode 100644 index 10e2474314b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x10000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 256k]; -define region NONCACHEABLE_RAM = mem:[from 0x01240000 size 256k]; -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; -define region APB_SRAM = mem:[from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/ram.icf deleted file mode 100644 index 1e0ace778c5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/ram.icf +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00080000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01240000 size 256k]; /* AXI SRAM */ -define region AXI_SRAM = mem:[from 0x01200000 size 256k]; /* AXI SRAM0 */ -define region AHB_SRAM = mem:[from 0xF0400000 size 32k]; -define region APB_SRAM = mem:[from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/startup.s deleted file mode 100644 index 81175908610..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/iar/startup.s +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - EXTERN _init_ext_ram -__iar_cstart_init_ext_ram: - la t0, SFE(SAFESTACK) - mv sp, t0 - call _init_ext_ram -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/reset.c deleted file mode 100644 index a503d6984b0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash.icf deleted file mode 100644 index c3d8d729873..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash.icf +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x01240000 size 256k]; -define region AHB_SRAM = [from 0xF0400000 size 32k]; -define region APB_SRAM = [from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_sdram_uf2.icf deleted file mode 100644 index 35bba37c6e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_sdram_uf2.icf +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2023 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512K]; -define region DRAM = [from 0x40000000 size _extram_size - 32M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 32M size 32M]; -define region AHB_SRAM = [from 0xF0400000 size 32k]; -define region APB_SRAM = [from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DRAM { block cherryusb_usbh_class_info }; -place in DRAM { block framebuffer }; -place in AXI_SRAM then DRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_sdram_xip.icf deleted file mode 100644 index 9d463c79f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_sdram_xip.icf +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright 2023 hpmicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512K]; -define region DRAM = [from 0x40000000 size _extram_size - 32M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 32M size 32M]; -define region AHB_SRAM = [from 0xF0400000 size 32k]; -define region APB_SRAM = [from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in DRAM { block cherryusb_usbh_class_info }; -place in DRAM { block framebuffer }; -place in AXI_SRAM then DRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_xip.icf deleted file mode 100644 index 14c5c7a4009..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/flash_xip.icf +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x01240000 size 256k]; -define region AHB_SRAM = [from 0xF0400000 size 32k]; -define region APB_SRAM = [from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/ram.icf deleted file mode 100644 index bcb5ad7be03..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/ram.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00080000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 256k]; -define region NONCACHEABLE_RAM = [from 0x01240000 size 256k]; -define region AHB_SRAM = [from 0xF0400000 size 32k]; -define region APB_SRAM = [from 0xF4130000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; - -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs -do not initialize { section .backup_sram}; - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) // It is intended placing RO here - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in APB_SRAM { section .backup_sram}; // Backup SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/startup.s deleted file mode 100644 index 8a7036e137d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/segger/startup.s +++ /dev/null @@ -1,419 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/trap.c deleted file mode 100644 index 539c77c4804..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/trap.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ -#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ -#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ -#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ -#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ -#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -__attribute__((weak)) long exception_s_handler(long cause, long epc) -{ - (void) cause; - return epc; -} - -__attribute__((weak)) void swi_s_isr(void) -{ -} - -__attribute__((weak)) void mchtmr_s_isr(void) -{ -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} - - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_s_table[]; -HPM_ATTR_SUPERVISOR_INTERRUPT -#endif -void irq_handler_s_trap(void) -{ - long scause = read_csr(CSR_SCAUSE); - long sepc = read_csr(CSR_SEPC); - long sstatus = read_csr(CSR_SSTATUS); - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : :"t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : :"a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { - /* Machine timer interrupt */ - mchtmr_s_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_s_global_irq(CSR_SSTATUS_SIE_MASK); -#endif - ((isr_func_t)__vector_s_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); - - } -#endif - - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_s_isr(); - intc_s_complete_swi(); - } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : :"r"(syscall_handler) : "a4" - ); - sepc += 4; - } else { - sepc = exception_s_handler(scause, sepc); - } - - /* Restore CSR */ - write_csr(CSR_SSTATUS, sstatus); - write_csr(CSR_SEPC, sepc); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/vectors.h deleted file mode 100644 index 8a930b6363c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/HPM6880/toolchains/vectors.h +++ /dev/null @@ -1,825 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(9) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 10 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 11 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 12 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_HANDLER 13 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* MCAN4 IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* MCAN5 IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* MCAN6 IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* MCAN7 IRQ handler */ - IRQ_DEFAULT_HANDLER 18 /* PTPC IRQ handler */ - IRQ_DEFAULT_HANDLER 19 /* Reserved */ - IRQ_DEFAULT_HANDLER 20 /* Reserved */ - IRQ_DEFAULT_HANDLER 21 /* Reserved */ - IRQ_DEFAULT_HANDLER 22 /* Reserved */ - IRQ_DEFAULT_HANDLER 23 /* Reserved */ - IRQ_DEFAULT_HANDLER 24 /* Reserved */ - IRQ_DEFAULT_HANDLER 25 /* Reserved */ - IRQ_DEFAULT_HANDLER 26 /* Reserved */ - IRQ_DEFAULT_HANDLER 27 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* UART4 IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* UART5 IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* UART6 IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* UART7 IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 36 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 37 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 38 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 39 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 40 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 41 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 42 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 43 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 44 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 45 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_HANDLER 46 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_HANDLER 47 /* GPTMR4 IRQ handler */ - IRQ_DEFAULT_HANDLER 48 /* GPTMR5 IRQ handler */ - IRQ_DEFAULT_HANDLER 49 /* GPTMR6 IRQ handler */ - IRQ_DEFAULT_HANDLER 50 /* GPTMR7 IRQ handler */ - IRQ_DEFAULT_HANDLER 51 /* EWDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* EWDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 54 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* MBX1A IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* MBX1B IRQ handler */ - IRQ_DEFAULT_HANDLER 57 /* RNG IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 60 /* ADC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 61 /* SDM IRQ handler */ - IRQ_DEFAULT_HANDLER 62 /* OPAMP IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* I2S0 IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* I2S1 IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* I2S2 IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* I2S3 IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* DAO IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* PDM IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* SMIX_DMA IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* SMIX_ASRC IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* CAM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* CAM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 73 /* LCDC IRQ handler */ - IRQ_DEFAULT_HANDLER 74 /* LCDC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 75 /* PDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 76 /* JPEG IRQ handler */ - IRQ_DEFAULT_HANDLER 77 /* GWCK0_FUNC IRQ handler */ - IRQ_DEFAULT_HANDLER 78 /* GWCK0_ERR IRQ handler */ - IRQ_DEFAULT_HANDLER 79 /* GWCK1_FUNC IRQ handler */ - IRQ_DEFAULT_HANDLER 80 /* GWCK1_ERR IRQ handler */ - IRQ_DEFAULT_HANDLER 81 /* MIPI_DSI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 82 /* MIPI_DSI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 83 /* MIPI_CSI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ - IRQ_DEFAULT_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ - IRQ_DEFAULT_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ - IRQ_DEFAULT_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ - IRQ_DEFAULT_HANDLER 88 /* MIPI_CSI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 89 /* LCB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 90 /* LCB1 IRQ handler */ - IRQ_DEFAULT_HANDLER 91 /* GPU IRQ handler */ - IRQ_DEFAULT_HANDLER 92 /* ENET0 IRQ handler */ - IRQ_DEFAULT_HANDLER 93 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 94 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 95 /* SDXC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 96 /* SDXC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 97 /* SDP IRQ handler */ - IRQ_DEFAULT_HANDLER 98 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 99 /* XDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 100 /* DDR IRQ handler */ - IRQ_DEFAULT_HANDLER 101 /* FFA IRQ handler */ - IRQ_DEFAULT_HANDLER 102 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 103 /* TSNS IRQ handler */ - IRQ_DEFAULT_HANDLER 104 /* VAD IRQ handler */ - IRQ_DEFAULT_HANDLER 105 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 106 /* PWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 107 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 108 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 109 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 110 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 111 /* RTC IRQ handler */ - IRQ_DEFAULT_HANDLER 112 /* BGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 113 /* BVIO IRQ handler */ - IRQ_DEFAULT_HANDLER 114 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 115 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 116 /* DEBUG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 117 /* DEBUG1 IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(9) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 10 /* MCAN0 IRQ handler */ - IRQ_HANDLER 11 /* MCAN1 IRQ handler */ - IRQ_HANDLER 12 /* MCAN2 IRQ handler */ - IRQ_HANDLER 13 /* MCAN3 IRQ handler */ - IRQ_HANDLER 14 /* MCAN4 IRQ handler */ - IRQ_HANDLER 15 /* MCAN5 IRQ handler */ - IRQ_HANDLER 16 /* MCAN6 IRQ handler */ - IRQ_HANDLER 17 /* MCAN7 IRQ handler */ - IRQ_HANDLER 18 /* PTPC IRQ handler */ - IRQ_HANDLER 19 /* Reserved */ - IRQ_HANDLER 20 /* Reserved */ - IRQ_HANDLER 21 /* Reserved */ - IRQ_HANDLER 22 /* Reserved */ - IRQ_HANDLER 23 /* Reserved */ - IRQ_HANDLER 24 /* Reserved */ - IRQ_HANDLER 25 /* Reserved */ - IRQ_HANDLER 26 /* Reserved */ - IRQ_HANDLER 27 /* UART0 IRQ handler */ - IRQ_HANDLER 28 /* UART1 IRQ handler */ - IRQ_HANDLER 29 /* UART2 IRQ handler */ - IRQ_HANDLER 30 /* UART3 IRQ handler */ - IRQ_HANDLER 31 /* UART4 IRQ handler */ - IRQ_HANDLER 32 /* UART5 IRQ handler */ - IRQ_HANDLER 33 /* UART6 IRQ handler */ - IRQ_HANDLER 34 /* UART7 IRQ handler */ - IRQ_HANDLER 35 /* I2C0 IRQ handler */ - IRQ_HANDLER 36 /* I2C1 IRQ handler */ - IRQ_HANDLER 37 /* I2C2 IRQ handler */ - IRQ_HANDLER 38 /* I2C3 IRQ handler */ - IRQ_HANDLER 39 /* SPI0 IRQ handler */ - IRQ_HANDLER 40 /* SPI1 IRQ handler */ - IRQ_HANDLER 41 /* SPI2 IRQ handler */ - IRQ_HANDLER 42 /* SPI3 IRQ handler */ - IRQ_HANDLER 43 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 44 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 45 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 46 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 47 /* GPTMR4 IRQ handler */ - IRQ_HANDLER 48 /* GPTMR5 IRQ handler */ - IRQ_HANDLER 49 /* GPTMR6 IRQ handler */ - IRQ_HANDLER 50 /* GPTMR7 IRQ handler */ - IRQ_HANDLER 51 /* EWDG0 IRQ handler */ - IRQ_HANDLER 52 /* EWDG1 IRQ handler */ - IRQ_HANDLER 53 /* MBX0A IRQ handler */ - IRQ_HANDLER 54 /* MBX0B IRQ handler */ - IRQ_HANDLER 55 /* MBX1A IRQ handler */ - IRQ_HANDLER 56 /* MBX1B IRQ handler */ - IRQ_HANDLER 57 /* RNG IRQ handler */ - IRQ_HANDLER 58 /* HDMA IRQ handler */ - IRQ_HANDLER 59 /* ADC0 IRQ handler */ - IRQ_HANDLER 60 /* ADC1 IRQ handler */ - IRQ_HANDLER 61 /* SDM IRQ handler */ - IRQ_HANDLER 62 /* OPAMP IRQ handler */ - IRQ_HANDLER 63 /* I2S0 IRQ handler */ - IRQ_HANDLER 64 /* I2S1 IRQ handler */ - IRQ_HANDLER 65 /* I2S2 IRQ handler */ - IRQ_HANDLER 66 /* I2S3 IRQ handler */ - IRQ_HANDLER 67 /* DAO IRQ handler */ - IRQ_HANDLER 68 /* PDM IRQ handler */ - IRQ_HANDLER 69 /* SMIX_DMA IRQ handler */ - IRQ_HANDLER 70 /* SMIX_ASRC IRQ handler */ - IRQ_HANDLER 71 /* CAM0 IRQ handler */ - IRQ_HANDLER 72 /* CAM1 IRQ handler */ - IRQ_HANDLER 73 /* LCDC IRQ handler */ - IRQ_HANDLER 74 /* LCDC1 IRQ handler */ - IRQ_HANDLER 75 /* PDMA IRQ handler */ - IRQ_HANDLER 76 /* JPEG IRQ handler */ - IRQ_HANDLER 77 /* GWCK0_FUNC IRQ handler */ - IRQ_HANDLER 78 /* GWCK0_ERR IRQ handler */ - IRQ_HANDLER 79 /* GWCK1_FUNC IRQ handler */ - IRQ_HANDLER 80 /* GWCK1_ERR IRQ handler */ - IRQ_HANDLER 81 /* MIPI_DSI0 IRQ handler */ - IRQ_HANDLER 82 /* MIPI_DSI1 IRQ handler */ - IRQ_HANDLER 83 /* MIPI_CSI0 IRQ handler */ - IRQ_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ - IRQ_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ - IRQ_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ - IRQ_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ - IRQ_HANDLER 88 /* MIPI_CSI1 IRQ handler */ - IRQ_HANDLER 89 /* LCB0 IRQ handler */ - IRQ_HANDLER 90 /* LCB1 IRQ handler */ - IRQ_HANDLER 91 /* GPU IRQ handler */ - IRQ_HANDLER 92 /* ENET0 IRQ handler */ - IRQ_HANDLER 93 /* NTMR0 IRQ handler */ - IRQ_HANDLER 94 /* USB0 IRQ handler */ - IRQ_HANDLER 95 /* SDXC0 IRQ handler */ - IRQ_HANDLER 96 /* SDXC1 IRQ handler */ - IRQ_HANDLER 97 /* SDP IRQ handler */ - IRQ_HANDLER 98 /* XPI0 IRQ handler */ - IRQ_HANDLER 99 /* XDMA IRQ handler */ - IRQ_HANDLER 100 /* DDR IRQ handler */ - IRQ_HANDLER 101 /* FFA IRQ handler */ - IRQ_HANDLER 102 /* PSEC IRQ handler */ - IRQ_HANDLER 103 /* TSNS IRQ handler */ - IRQ_HANDLER 104 /* VAD IRQ handler */ - IRQ_HANDLER 105 /* PGPIO IRQ handler */ - IRQ_HANDLER 106 /* PWDG IRQ handler */ - IRQ_HANDLER 107 /* PTMR IRQ handler */ - IRQ_HANDLER 108 /* PUART IRQ handler */ - IRQ_HANDLER 109 /* FUSE IRQ handler */ - IRQ_HANDLER 110 /* SECMON IRQ handler */ - IRQ_HANDLER 111 /* RTC IRQ handler */ - IRQ_HANDLER 112 /* BGPIO IRQ handler */ - IRQ_HANDLER 113 /* BVIO IRQ handler */ - IRQ_HANDLER 114 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 115 /* SYSCTL IRQ handler */ - IRQ_HANDLER 116 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 117 /* DEBUG1 IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 10 /* MCAN0 IRQ handler */ - IRQ_HANDLER 11 /* MCAN1 IRQ handler */ - IRQ_HANDLER 12 /* MCAN2 IRQ handler */ - IRQ_HANDLER 13 /* MCAN3 IRQ handler */ - IRQ_HANDLER 14 /* MCAN4 IRQ handler */ - IRQ_HANDLER 15 /* MCAN5 IRQ handler */ - IRQ_HANDLER 16 /* MCAN6 IRQ handler */ - IRQ_HANDLER 17 /* MCAN7 IRQ handler */ - IRQ_HANDLER 18 /* PTPC IRQ handler */ - IRQ_HANDLER 19 /* Reserved */ - IRQ_HANDLER 20 /* Reserved */ - IRQ_HANDLER 21 /* Reserved */ - IRQ_HANDLER 22 /* Reserved */ - IRQ_HANDLER 23 /* Reserved */ - IRQ_HANDLER 24 /* Reserved */ - IRQ_HANDLER 25 /* Reserved */ - IRQ_HANDLER 26 /* Reserved */ - IRQ_HANDLER 27 /* UART0 IRQ handler */ - IRQ_HANDLER 28 /* UART1 IRQ handler */ - IRQ_HANDLER 29 /* UART2 IRQ handler */ - IRQ_HANDLER 30 /* UART3 IRQ handler */ - IRQ_HANDLER 31 /* UART4 IRQ handler */ - IRQ_HANDLER 32 /* UART5 IRQ handler */ - IRQ_HANDLER 33 /* UART6 IRQ handler */ - IRQ_HANDLER 34 /* UART7 IRQ handler */ - IRQ_HANDLER 35 /* I2C0 IRQ handler */ - IRQ_HANDLER 36 /* I2C1 IRQ handler */ - IRQ_HANDLER 37 /* I2C2 IRQ handler */ - IRQ_HANDLER 38 /* I2C3 IRQ handler */ - IRQ_HANDLER 39 /* SPI0 IRQ handler */ - IRQ_HANDLER 40 /* SPI1 IRQ handler */ - IRQ_HANDLER 41 /* SPI2 IRQ handler */ - IRQ_HANDLER 42 /* SPI3 IRQ handler */ - IRQ_HANDLER 43 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 44 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 45 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 46 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 47 /* GPTMR4 IRQ handler */ - IRQ_HANDLER 48 /* GPTMR5 IRQ handler */ - IRQ_HANDLER 49 /* GPTMR6 IRQ handler */ - IRQ_HANDLER 50 /* GPTMR7 IRQ handler */ - IRQ_HANDLER 51 /* EWDG0 IRQ handler */ - IRQ_HANDLER 52 /* EWDG1 IRQ handler */ - IRQ_HANDLER 53 /* MBX0A IRQ handler */ - IRQ_HANDLER 54 /* MBX0B IRQ handler */ - IRQ_HANDLER 55 /* MBX1A IRQ handler */ - IRQ_HANDLER 56 /* MBX1B IRQ handler */ - IRQ_HANDLER 57 /* RNG IRQ handler */ - IRQ_HANDLER 58 /* HDMA IRQ handler */ - IRQ_HANDLER 59 /* ADC0 IRQ handler */ - IRQ_HANDLER 60 /* ADC1 IRQ handler */ - IRQ_HANDLER 61 /* SDM IRQ handler */ - IRQ_HANDLER 62 /* OPAMP IRQ handler */ - IRQ_HANDLER 63 /* I2S0 IRQ handler */ - IRQ_HANDLER 64 /* I2S1 IRQ handler */ - IRQ_HANDLER 65 /* I2S2 IRQ handler */ - IRQ_HANDLER 66 /* I2S3 IRQ handler */ - IRQ_HANDLER 67 /* DAO IRQ handler */ - IRQ_HANDLER 68 /* PDM IRQ handler */ - IRQ_HANDLER 69 /* SMIX_DMA IRQ handler */ - IRQ_HANDLER 70 /* SMIX_ASRC IRQ handler */ - IRQ_HANDLER 71 /* CAM0 IRQ handler */ - IRQ_HANDLER 72 /* CAM1 IRQ handler */ - IRQ_HANDLER 73 /* LCDC IRQ handler */ - IRQ_HANDLER 74 /* LCDC1 IRQ handler */ - IRQ_HANDLER 75 /* PDMA IRQ handler */ - IRQ_HANDLER 76 /* JPEG IRQ handler */ - IRQ_HANDLER 77 /* GWCK0_FUNC IRQ handler */ - IRQ_HANDLER 78 /* GWCK0_ERR IRQ handler */ - IRQ_HANDLER 79 /* GWCK1_FUNC IRQ handler */ - IRQ_HANDLER 80 /* GWCK1_ERR IRQ handler */ - IRQ_HANDLER 81 /* MIPI_DSI0 IRQ handler */ - IRQ_HANDLER 82 /* MIPI_DSI1 IRQ handler */ - IRQ_HANDLER 83 /* MIPI_CSI0 IRQ handler */ - IRQ_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ - IRQ_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ - IRQ_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ - IRQ_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ - IRQ_HANDLER 88 /* MIPI_CSI1 IRQ handler */ - IRQ_HANDLER 89 /* LCB0 IRQ handler */ - IRQ_HANDLER 90 /* LCB1 IRQ handler */ - IRQ_HANDLER 91 /* GPU IRQ handler */ - IRQ_HANDLER 92 /* ENET0 IRQ handler */ - IRQ_HANDLER 93 /* NTMR0 IRQ handler */ - IRQ_HANDLER 94 /* USB0 IRQ handler */ - IRQ_HANDLER 95 /* SDXC0 IRQ handler */ - IRQ_HANDLER 96 /* SDXC1 IRQ handler */ - IRQ_HANDLER 97 /* SDP IRQ handler */ - IRQ_HANDLER 98 /* XPI0 IRQ handler */ - IRQ_HANDLER 99 /* XDMA IRQ handler */ - IRQ_HANDLER 100 /* DDR IRQ handler */ - IRQ_HANDLER 101 /* FFA IRQ handler */ - IRQ_HANDLER 102 /* PSEC IRQ handler */ - IRQ_HANDLER 103 /* TSNS IRQ handler */ - IRQ_HANDLER 104 /* VAD IRQ handler */ - IRQ_HANDLER 105 /* PGPIO IRQ handler */ - IRQ_HANDLER 106 /* PWDG IRQ handler */ - IRQ_HANDLER 107 /* PTMR IRQ handler */ - IRQ_HANDLER 108 /* PUART IRQ handler */ - IRQ_HANDLER 109 /* FUSE IRQ handler */ - IRQ_HANDLER 110 /* SECMON IRQ handler */ - IRQ_HANDLER 111 /* RTC IRQ handler */ - IRQ_HANDLER 112 /* BGPIO IRQ handler */ - IRQ_HANDLER 113 /* BVIO IRQ handler */ - IRQ_HANDLER 114 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 115 /* SYSCTL IRQ handler */ - IRQ_HANDLER 116 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 117 /* DEBUG1 IRQ handler */ - -#endif - -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_S_HANDLER macro - dc32 default_isr_s_\1 - endm - -IRQ_DEFAULT_S_HANDLER macro - PUBWEAK default_isr_s_\1 -default_isr_s_\1 - j default_irq_s_handler - endm - - SECTION `.isr_s_vector`:CODE:ROOT(9) - PUBWEAK default_irq_s_handler -default_irq_s_handler - j default_irq_s_handler - IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_S_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_S_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_S_HANDLER 10 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 11 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 12 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 13 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 14 /* MCAN4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 15 /* MCAN5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 16 /* MCAN6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 17 /* MCAN7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 18 /* PTPC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 19 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 20 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 21 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 22 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 23 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 24 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 25 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 26 /* Reserved */ - IRQ_DEFAULT_S_HANDLER 27 /* UART0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 28 /* UART1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 29 /* UART2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 30 /* UART3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 31 /* UART4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 32 /* UART5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 33 /* UART6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 34 /* UART7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 35 /* I2C0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 36 /* I2C1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 37 /* I2C2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 38 /* I2C3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 39 /* SPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 40 /* SPI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 41 /* SPI2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 42 /* SPI3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 43 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 44 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 45 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 46 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 47 /* GPTMR4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 48 /* GPTMR5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 49 /* GPTMR6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 50 /* GPTMR7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 51 /* EWDG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 52 /* EWDG1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 53 /* MBX0A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 54 /* MBX0B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 55 /* MBX1A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 56 /* MBX1B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 57 /* RNG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 58 /* HDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 59 /* ADC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 60 /* ADC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 61 /* SDM IRQ handler */ - IRQ_DEFAULT_S_HANDLER 62 /* OPAMP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 63 /* I2S0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 64 /* I2S1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 65 /* I2S2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 66 /* I2S3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 67 /* DAO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 68 /* PDM IRQ handler */ - IRQ_DEFAULT_S_HANDLER 69 /* SMIX_DMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 70 /* SMIX_ASRC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 71 /* CAM0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 72 /* CAM1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 73 /* LCDC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 74 /* LCDC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 75 /* PDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 76 /* JPEG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 77 /* GWCK0_FUNC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 78 /* GWCK0_ERR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 79 /* GWCK1_FUNC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 80 /* GWCK1_ERR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 81 /* MIPI_DSI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 82 /* MIPI_DSI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 83 /* MIPI_CSI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 88 /* MIPI_CSI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 89 /* LCB0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 90 /* LCB1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 91 /* GPU IRQ handler */ - IRQ_DEFAULT_S_HANDLER 92 /* ENET0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 93 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 94 /* USB0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 95 /* SDXC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 96 /* SDXC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 97 /* SDP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 98 /* XPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 99 /* XDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 100 /* DDR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 101 /* FFA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 102 /* PSEC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 103 /* TSNS IRQ handler */ - IRQ_DEFAULT_S_HANDLER 104 /* VAD IRQ handler */ - IRQ_DEFAULT_S_HANDLER 105 /* PGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 106 /* PWDG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 107 /* PTMR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 108 /* PUART IRQ handler */ - IRQ_DEFAULT_S_HANDLER 109 /* FUSE IRQ handler */ - IRQ_DEFAULT_S_HANDLER 110 /* SECMON IRQ handler */ - IRQ_DEFAULT_S_HANDLER 111 /* RTC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 112 /* BGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 113 /* BVIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 114 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_S_HANDLER 115 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_S_HANDLER 116 /* DEBUG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 117 /* DEBUG1 IRQ handler */ - - EXTERN irq_handler_s_trap - SECTION `.vector_s_table`:CODE:ROOT(9) - PUBLIC __vector_s_table - DATA - -__vector_s_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_s_trap -#endif - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 10 /* MCAN0 IRQ handler */ - IRQ_S_HANDLER 11 /* MCAN1 IRQ handler */ - IRQ_S_HANDLER 12 /* MCAN2 IRQ handler */ - IRQ_S_HANDLER 13 /* MCAN3 IRQ handler */ - IRQ_S_HANDLER 14 /* MCAN4 IRQ handler */ - IRQ_S_HANDLER 15 /* MCAN5 IRQ handler */ - IRQ_S_HANDLER 16 /* MCAN6 IRQ handler */ - IRQ_S_HANDLER 17 /* MCAN7 IRQ handler */ - IRQ_S_HANDLER 18 /* PTPC IRQ handler */ - IRQ_S_HANDLER 19 /* Reserved */ - IRQ_S_HANDLER 20 /* Reserved */ - IRQ_S_HANDLER 21 /* Reserved */ - IRQ_S_HANDLER 22 /* Reserved */ - IRQ_S_HANDLER 23 /* Reserved */ - IRQ_S_HANDLER 24 /* Reserved */ - IRQ_S_HANDLER 25 /* Reserved */ - IRQ_S_HANDLER 26 /* Reserved */ - IRQ_S_HANDLER 27 /* UART0 IRQ handler */ - IRQ_S_HANDLER 28 /* UART1 IRQ handler */ - IRQ_S_HANDLER 29 /* UART2 IRQ handler */ - IRQ_S_HANDLER 30 /* UART3 IRQ handler */ - IRQ_S_HANDLER 31 /* UART4 IRQ handler */ - IRQ_S_HANDLER 32 /* UART5 IRQ handler */ - IRQ_S_HANDLER 33 /* UART6 IRQ handler */ - IRQ_S_HANDLER 34 /* UART7 IRQ handler */ - IRQ_S_HANDLER 35 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 36 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 37 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 38 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 39 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 40 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 41 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 42 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 43 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 44 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 45 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 46 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 47 /* GPTMR4 IRQ handler */ - IRQ_S_HANDLER 48 /* GPTMR5 IRQ handler */ - IRQ_S_HANDLER 49 /* GPTMR6 IRQ handler */ - IRQ_S_HANDLER 50 /* GPTMR7 IRQ handler */ - IRQ_S_HANDLER 51 /* EWDG0 IRQ handler */ - IRQ_S_HANDLER 52 /* EWDG1 IRQ handler */ - IRQ_S_HANDLER 53 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 54 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 55 /* MBX1A IRQ handler */ - IRQ_S_HANDLER 56 /* MBX1B IRQ handler */ - IRQ_S_HANDLER 57 /* RNG IRQ handler */ - IRQ_S_HANDLER 58 /* HDMA IRQ handler */ - IRQ_S_HANDLER 59 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 60 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 61 /* SDM IRQ handler */ - IRQ_S_HANDLER 62 /* OPAMP IRQ handler */ - IRQ_S_HANDLER 63 /* I2S0 IRQ handler */ - IRQ_S_HANDLER 64 /* I2S1 IRQ handler */ - IRQ_S_HANDLER 65 /* I2S2 IRQ handler */ - IRQ_S_HANDLER 66 /* I2S3 IRQ handler */ - IRQ_S_HANDLER 67 /* DAO IRQ handler */ - IRQ_S_HANDLER 68 /* PDM IRQ handler */ - IRQ_S_HANDLER 69 /* SMIX_DMA IRQ handler */ - IRQ_S_HANDLER 70 /* SMIX_ASRC IRQ handler */ - IRQ_S_HANDLER 71 /* CAM0 IRQ handler */ - IRQ_S_HANDLER 72 /* CAM1 IRQ handler */ - IRQ_S_HANDLER 73 /* LCDC IRQ handler */ - IRQ_S_HANDLER 74 /* LCDC1 IRQ handler */ - IRQ_S_HANDLER 75 /* PDMA IRQ handler */ - IRQ_S_HANDLER 76 /* JPEG IRQ handler */ - IRQ_S_HANDLER 77 /* GWCK0_FUNC IRQ handler */ - IRQ_S_HANDLER 78 /* GWCK0_ERR IRQ handler */ - IRQ_S_HANDLER 79 /* GWCK1_FUNC IRQ handler */ - IRQ_S_HANDLER 80 /* GWCK1_ERR IRQ handler */ - IRQ_S_HANDLER 81 /* MIPI_DSI0 IRQ handler */ - IRQ_S_HANDLER 82 /* MIPI_DSI1 IRQ handler */ - IRQ_S_HANDLER 83 /* MIPI_CSI0 IRQ handler */ - IRQ_S_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ - IRQ_S_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ - IRQ_S_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ - IRQ_S_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ - IRQ_S_HANDLER 88 /* MIPI_CSI1 IRQ handler */ - IRQ_S_HANDLER 89 /* LCB0 IRQ handler */ - IRQ_S_HANDLER 90 /* LCB1 IRQ handler */ - IRQ_S_HANDLER 91 /* GPU IRQ handler */ - IRQ_S_HANDLER 92 /* ENET0 IRQ handler */ - IRQ_S_HANDLER 93 /* NTMR0 IRQ handler */ - IRQ_S_HANDLER 94 /* USB0 IRQ handler */ - IRQ_S_HANDLER 95 /* SDXC0 IRQ handler */ - IRQ_S_HANDLER 96 /* SDXC1 IRQ handler */ - IRQ_S_HANDLER 97 /* SDP IRQ handler */ - IRQ_S_HANDLER 98 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 99 /* XDMA IRQ handler */ - IRQ_S_HANDLER 100 /* DDR IRQ handler */ - IRQ_S_HANDLER 101 /* FFA IRQ handler */ - IRQ_S_HANDLER 102 /* PSEC IRQ handler */ - IRQ_S_HANDLER 103 /* TSNS IRQ handler */ - IRQ_S_HANDLER 104 /* VAD IRQ handler */ - IRQ_S_HANDLER 105 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 106 /* PWDG IRQ handler */ - IRQ_S_HANDLER 107 /* PTMR IRQ handler */ - IRQ_S_HANDLER 108 /* PUART IRQ handler */ - IRQ_S_HANDLER 109 /* FUSE IRQ handler */ - IRQ_S_HANDLER 110 /* SECMON IRQ handler */ - IRQ_S_HANDLER 111 /* RTC IRQ handler */ - IRQ_S_HANDLER 112 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 113 /* BVIO IRQ handler */ - IRQ_S_HANDLER 114 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 115 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 116 /* DEBUG0 IRQ handler */ - IRQ_S_HANDLER 117 /* DEBUG1 IRQ handler */ - -#else - -.global default_irq_s_handler -.weak default_irq_s_handler -.align 2 -default_irq_s_handler: -1: j 1b - -.macro IRQ_S_HANDLER irq - .weak default_isr_s_\irq - .set default_isr_s_\irq, default_irq_s_handler - .long default_isr_s_\irq -.endm - -.section .vector_s_table, "a" -.global __vector_s_table -.align 9 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_s_trap, freertos_risc_v_trap_handler -#else - .set default_isr_s_trap, irq_handler_s_trap -#endif - -__vector_s_table: - .weak default_isr_s_trap - .long default_isr_s_trap - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 8 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 9 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 10 /* MCAN0 IRQ handler */ - IRQ_S_HANDLER 11 /* MCAN1 IRQ handler */ - IRQ_S_HANDLER 12 /* MCAN2 IRQ handler */ - IRQ_S_HANDLER 13 /* MCAN3 IRQ handler */ - IRQ_S_HANDLER 14 /* MCAN4 IRQ handler */ - IRQ_S_HANDLER 15 /* MCAN5 IRQ handler */ - IRQ_S_HANDLER 16 /* MCAN6 IRQ handler */ - IRQ_S_HANDLER 17 /* MCAN7 IRQ handler */ - IRQ_S_HANDLER 18 /* PTPC IRQ handler */ - IRQ_S_HANDLER 19 /* Reserved */ - IRQ_S_HANDLER 20 /* Reserved */ - IRQ_S_HANDLER 21 /* Reserved */ - IRQ_S_HANDLER 22 /* Reserved */ - IRQ_S_HANDLER 23 /* Reserved */ - IRQ_S_HANDLER 24 /* Reserved */ - IRQ_S_HANDLER 25 /* Reserved */ - IRQ_S_HANDLER 26 /* Reserved */ - IRQ_S_HANDLER 27 /* UART0 IRQ handler */ - IRQ_S_HANDLER 28 /* UART1 IRQ handler */ - IRQ_S_HANDLER 29 /* UART2 IRQ handler */ - IRQ_S_HANDLER 30 /* UART3 IRQ handler */ - IRQ_S_HANDLER 31 /* UART4 IRQ handler */ - IRQ_S_HANDLER 32 /* UART5 IRQ handler */ - IRQ_S_HANDLER 33 /* UART6 IRQ handler */ - IRQ_S_HANDLER 34 /* UART7 IRQ handler */ - IRQ_S_HANDLER 35 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 36 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 37 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 38 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 39 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 40 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 41 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 42 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 43 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 44 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 45 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 46 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 47 /* GPTMR4 IRQ handler */ - IRQ_S_HANDLER 48 /* GPTMR5 IRQ handler */ - IRQ_S_HANDLER 49 /* GPTMR6 IRQ handler */ - IRQ_S_HANDLER 50 /* GPTMR7 IRQ handler */ - IRQ_S_HANDLER 51 /* EWDG0 IRQ handler */ - IRQ_S_HANDLER 52 /* EWDG1 IRQ handler */ - IRQ_S_HANDLER 53 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 54 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 55 /* MBX1A IRQ handler */ - IRQ_S_HANDLER 56 /* MBX1B IRQ handler */ - IRQ_S_HANDLER 57 /* RNG IRQ handler */ - IRQ_S_HANDLER 58 /* HDMA IRQ handler */ - IRQ_S_HANDLER 59 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 60 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 61 /* SDM IRQ handler */ - IRQ_S_HANDLER 62 /* OPAMP IRQ handler */ - IRQ_S_HANDLER 63 /* I2S0 IRQ handler */ - IRQ_S_HANDLER 64 /* I2S1 IRQ handler */ - IRQ_S_HANDLER 65 /* I2S2 IRQ handler */ - IRQ_S_HANDLER 66 /* I2S3 IRQ handler */ - IRQ_S_HANDLER 67 /* DAO IRQ handler */ - IRQ_S_HANDLER 68 /* PDM IRQ handler */ - IRQ_S_HANDLER 69 /* SMIX_DMA IRQ handler */ - IRQ_S_HANDLER 70 /* SMIX_ASRC IRQ handler */ - IRQ_S_HANDLER 71 /* CAM0 IRQ handler */ - IRQ_S_HANDLER 72 /* CAM1 IRQ handler */ - IRQ_S_HANDLER 73 /* LCDC IRQ handler */ - IRQ_S_HANDLER 74 /* LCDC1 IRQ handler */ - IRQ_S_HANDLER 75 /* PDMA IRQ handler */ - IRQ_S_HANDLER 76 /* JPEG IRQ handler */ - IRQ_S_HANDLER 77 /* GWCK0_FUNC IRQ handler */ - IRQ_S_HANDLER 78 /* GWCK0_ERR IRQ handler */ - IRQ_S_HANDLER 79 /* GWCK1_FUNC IRQ handler */ - IRQ_S_HANDLER 80 /* GWCK1_ERR IRQ handler */ - IRQ_S_HANDLER 81 /* MIPI_DSI0 IRQ handler */ - IRQ_S_HANDLER 82 /* MIPI_DSI1 IRQ handler */ - IRQ_S_HANDLER 83 /* MIPI_CSI0 IRQ handler */ - IRQ_S_HANDLER 84 /* MIPI_CSI0_AP IRQ handler */ - IRQ_S_HANDLER 85 /* MIPI_CSI0_DIAG IRQ handler */ - IRQ_S_HANDLER 86 /* MIPI_CSI1_AP IRQ handler */ - IRQ_S_HANDLER 87 /* MIPI_CSI1_DIAG IRQ handler */ - IRQ_S_HANDLER 88 /* MIPI_CSI1 IRQ handler */ - IRQ_S_HANDLER 89 /* LCB0 IRQ handler */ - IRQ_S_HANDLER 90 /* LCB1 IRQ handler */ - IRQ_S_HANDLER 91 /* GPU IRQ handler */ - IRQ_S_HANDLER 92 /* ENET0 IRQ handler */ - IRQ_S_HANDLER 93 /* NTMR0 IRQ handler */ - IRQ_S_HANDLER 94 /* USB0 IRQ handler */ - IRQ_S_HANDLER 95 /* SDXC0 IRQ handler */ - IRQ_S_HANDLER 96 /* SDXC1 IRQ handler */ - IRQ_S_HANDLER 97 /* SDP IRQ handler */ - IRQ_S_HANDLER 98 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 99 /* XDMA IRQ handler */ - IRQ_S_HANDLER 100 /* DDR IRQ handler */ - IRQ_S_HANDLER 101 /* FFA IRQ handler */ - IRQ_S_HANDLER 102 /* PSEC IRQ handler */ - IRQ_S_HANDLER 103 /* TSNS IRQ handler */ - IRQ_S_HANDLER 104 /* VAD IRQ handler */ - IRQ_S_HANDLER 105 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 106 /* PWDG IRQ handler */ - IRQ_S_HANDLER 107 /* PTMR IRQ handler */ - IRQ_S_HANDLER 108 /* PUART IRQ handler */ - IRQ_S_HANDLER 109 /* FUSE IRQ handler */ - IRQ_S_HANDLER 110 /* SECMON IRQ handler */ - IRQ_S_HANDLER 111 /* RTC IRQ handler */ - IRQ_S_HANDLER 112 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 113 /* BVIO IRQ handler */ - IRQ_S_HANDLER 114 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 115 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 116 /* DEBUG0 IRQ handler */ - IRQ_S_HANDLER 117 /* DEBUG1 IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_adc16_regs.h deleted file mode 100644 index 75883336f7c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_adc16_regs.h +++ /dev/null @@ -1,1006 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC16_H -#define HPM_ADC16_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ - __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint32_t SEQ_WR_ADDR; /* 0x808: */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __RW uint32_t SEQ_HIGH_CFG; /* 0x850: */ - __R uint8_t RESERVED3[940]; /* 0x854 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[16]; - __R uint8_t RESERVED4[768]; /* 0xD00 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */ - __R uint8_t RESERVED5[196]; /* 0x1040 - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __R uint8_t RESERVED7[232]; /* 0x1118 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __R uint8_t RESERVED8[12]; /* 0x1204 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ - __R uint8_t RESERVED9[492]; /* 0x1214 - 0x13FF: Reserved */ - __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ - __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ - __R uint8_t RESERVED10[24]; /* 0x1448 - 0x145F: Reserved */ - __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ -} ADC16_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) -#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC16_CONFIG_INTEN3_SHIFT (29U) -#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) -#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC16_CONFIG_CHAN3_SHIFT (24U) -#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) -#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC16_CONFIG_INTEN2_SHIFT (21U) -#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) -#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC16_CONFIG_CHAN2_SHIFT (16U) -#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) -#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC16_CONFIG_INTEN1_MASK (0x2000U) -#define ADC16_CONFIG_INTEN1_SHIFT (13U) -#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) -#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC16_CONFIG_CHAN1_SHIFT (8U) -#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) -#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) - -/* - * QUEUE_EN (RW) - * - * preemption queue enable control - */ -#define ADC16_CONFIG_QUEUE_EN_MASK (0x40U) -#define ADC16_CONFIG_QUEUE_EN_SHIFT (6U) -#define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK) -#define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC16_CONFIG_INTEN0_MASK (0x20U) -#define ADC16_CONFIG_INTEN0_SHIFT (5U) -#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) -#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC16_CONFIG_CHAN0_MASK (0x1FU) -#define ADC16_CONFIG_CHAN0_SHIFT (0U) -#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) -#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC16_BUS_RESULT_VALID_SHIFT (16U) -#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) -#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) -#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) -#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_WR_ADDR */ -/* - * SEQ_WR_POINTER (RO) - * - * HW update this field after each dma write, it indicate the next dma write pointer. - * dma write address is (tar_addr+seq_wr_pointer)*4 - */ -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFFFFUL) -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register: SEQ_HIGH_CFG */ -/* - * STOP_POS_HIGH (RW) - * - */ -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK (0xFFF000UL) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT (12U) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) - -/* - * BUF_LEN_HIGH (RW) - * - */ -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK (0xFFFU) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT (0U) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample clock number - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); - * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - */ -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* - * PORT3_REALTIME (RW) - * - * set to enable trg queue stop other queues - */ -#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) -#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) -#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) -#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) -#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) -#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) -#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) -#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_STS_WDOG_MASK (0xFFFFU) -#define ADC16_INT_STS_WDOG_SHIFT (0U) -#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) -#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) -#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) -#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) -#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) -#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) -#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) -#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_EN_WDOG_MASK (0xFFFFU) -#define ADC16_INT_EN_WDOG_SHIFT (0U) -#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) -#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * ADC_CLK_ON (RW) - * - * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. - * MUST set clock_period to 0 or 1 for adc16 reg access - */ -#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) -#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC16_ANA_STATUS_CALON_MASK (0x80U) -#define ADC16_ANA_STATUS_CALON_SHIFT (7U) -#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) -#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) - -/* Bitfield definition for register array: ADC16_PARAMS */ -/* - * PARAM_VAL (RW) - * - */ -#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) -#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG0 */ -/* - * REG_EN (RW) - * - * set to enable regulator - */ -#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) -#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) -#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) -#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) - -/* - * BANDGAP_EN (RW) - * - * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - */ -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) - -/* - * CAL_AVG_CFG (RW) - * - * for average the calibration result. - * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; - * 4- 16 loops; 5-32 loops; others reserved - */ -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) - -/* - * PREEMPT_EN (RW) - * - * set to enable preemption feature - */ -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) - -/* - * CONV_PARAM (RW) - * - * conversion parameter - */ -#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG1 */ -/* - * COV_END_CNT (RW) - * - * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number+1). - */ -#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC16_CONFIG_TRG0A (0UL) -#define ADC16_CONFIG_TRG0B (1UL) -#define ADC16_CONFIG_TRG0C (2UL) -#define ADC16_CONFIG_TRG1A (3UL) -#define ADC16_CONFIG_TRG1B (4UL) -#define ADC16_CONFIG_TRG1C (5UL) -#define ADC16_CONFIG_TRG2A (6UL) -#define ADC16_CONFIG_TRG2B (7UL) -#define ADC16_CONFIG_TRG2C (8UL) -#define ADC16_CONFIG_TRG3A (9UL) -#define ADC16_CONFIG_TRG3B (10UL) -#define ADC16_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC16_BUS_RESULT_CHN0 (0UL) -#define ADC16_BUS_RESULT_CHN1 (1UL) -#define ADC16_BUS_RESULT_CHN2 (2UL) -#define ADC16_BUS_RESULT_CHN3 (3UL) -#define ADC16_BUS_RESULT_CHN4 (4UL) -#define ADC16_BUS_RESULT_CHN5 (5UL) -#define ADC16_BUS_RESULT_CHN6 (6UL) -#define ADC16_BUS_RESULT_CHN7 (7UL) -#define ADC16_BUS_RESULT_CHN8 (8UL) -#define ADC16_BUS_RESULT_CHN9 (9UL) -#define ADC16_BUS_RESULT_CHN10 (10UL) -#define ADC16_BUS_RESULT_CHN11 (11UL) -#define ADC16_BUS_RESULT_CHN12 (12UL) -#define ADC16_BUS_RESULT_CHN13 (13UL) -#define ADC16_BUS_RESULT_CHN14 (14UL) -#define ADC16_BUS_RESULT_CHN15 (15UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC16_SEQ_QUE_CFG0 (0UL) -#define ADC16_SEQ_QUE_CFG1 (1UL) -#define ADC16_SEQ_QUE_CFG2 (2UL) -#define ADC16_SEQ_QUE_CFG3 (3UL) -#define ADC16_SEQ_QUE_CFG4 (4UL) -#define ADC16_SEQ_QUE_CFG5 (5UL) -#define ADC16_SEQ_QUE_CFG6 (6UL) -#define ADC16_SEQ_QUE_CFG7 (7UL) -#define ADC16_SEQ_QUE_CFG8 (8UL) -#define ADC16_SEQ_QUE_CFG9 (9UL) -#define ADC16_SEQ_QUE_CFG10 (10UL) -#define ADC16_SEQ_QUE_CFG11 (11UL) -#define ADC16_SEQ_QUE_CFG12 (12UL) -#define ADC16_SEQ_QUE_CFG13 (13UL) -#define ADC16_SEQ_QUE_CFG14 (14UL) -#define ADC16_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC16_PRD_CFG_CHN0 (0UL) -#define ADC16_PRD_CFG_CHN1 (1UL) -#define ADC16_PRD_CFG_CHN2 (2UL) -#define ADC16_PRD_CFG_CHN3 (3UL) -#define ADC16_PRD_CFG_CHN4 (4UL) -#define ADC16_PRD_CFG_CHN5 (5UL) -#define ADC16_PRD_CFG_CHN6 (6UL) -#define ADC16_PRD_CFG_CHN7 (7UL) -#define ADC16_PRD_CFG_CHN8 (8UL) -#define ADC16_PRD_CFG_CHN9 (9UL) -#define ADC16_PRD_CFG_CHN10 (10UL) -#define ADC16_PRD_CFG_CHN11 (11UL) -#define ADC16_PRD_CFG_CHN12 (12UL) -#define ADC16_PRD_CFG_CHN13 (13UL) -#define ADC16_PRD_CFG_CHN14 (14UL) -#define ADC16_PRD_CFG_CHN15 (15UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC16_SAMPLE_CFG_CHN0 (0UL) -#define ADC16_SAMPLE_CFG_CHN1 (1UL) -#define ADC16_SAMPLE_CFG_CHN2 (2UL) -#define ADC16_SAMPLE_CFG_CHN3 (3UL) -#define ADC16_SAMPLE_CFG_CHN4 (4UL) -#define ADC16_SAMPLE_CFG_CHN5 (5UL) -#define ADC16_SAMPLE_CFG_CHN6 (6UL) -#define ADC16_SAMPLE_CFG_CHN7 (7UL) -#define ADC16_SAMPLE_CFG_CHN8 (8UL) -#define ADC16_SAMPLE_CFG_CHN9 (9UL) -#define ADC16_SAMPLE_CFG_CHN10 (10UL) -#define ADC16_SAMPLE_CFG_CHN11 (11UL) -#define ADC16_SAMPLE_CFG_CHN12 (12UL) -#define ADC16_SAMPLE_CFG_CHN13 (13UL) -#define ADC16_SAMPLE_CFG_CHN14 (14UL) -#define ADC16_SAMPLE_CFG_CHN15 (15UL) - -/* ADC16_PARAMS register group index macro definition */ -#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) - - -#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bacc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bacc_regs.h deleted file mode 100644 index 597f50ed16c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bacc_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BACC_H -#define HPM_BACC_H - -typedef struct { - __RW uint32_t CONFIG; /* 0x0: Access timing for access */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t PRE_TIME; /* 0x8: Timing gap before rising edge */ - __RW uint32_t POST_TIME; /* 0xC: Timing gap after rising edge */ -} BACC_Type; - - -/* Bitfield definition for register: CONFIG */ -/* - * FAST_WRITE (RW) - * - * Use fast write - * 0: Write normally - * 1: boost write - */ -#define BACC_CONFIG_FAST_WRITE_MASK (0x20000000UL) -#define BACC_CONFIG_FAST_WRITE_SHIFT (29U) -#define BACC_CONFIG_FAST_WRITE_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_WRITE_SHIFT) & BACC_CONFIG_FAST_WRITE_MASK) -#define BACC_CONFIG_FAST_WRITE_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_WRITE_MASK) >> BACC_CONFIG_FAST_WRITE_SHIFT) - -/* - * FAST_READ (RW) - * - * Use fast read - * 0: Read normally - * 1: boost read - */ -#define BACC_CONFIG_FAST_READ_MASK (0x10000000UL) -#define BACC_CONFIG_FAST_READ_SHIFT (28U) -#define BACC_CONFIG_FAST_READ_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_READ_SHIFT) & BACC_CONFIG_FAST_READ_MASK) -#define BACC_CONFIG_FAST_READ_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_READ_MASK) >> BACC_CONFIG_FAST_READ_SHIFT) - -/* - * TIMING (RW) - * - * Time in APB clock cycles, for battery timing penerate - */ -#define BACC_CONFIG_TIMING_MASK (0xFFFFU) -#define BACC_CONFIG_TIMING_SHIFT (0U) -#define BACC_CONFIG_TIMING_SET(x) (((uint32_t)(x) << BACC_CONFIG_TIMING_SHIFT) & BACC_CONFIG_TIMING_MASK) -#define BACC_CONFIG_TIMING_GET(x) (((uint32_t)(x) & BACC_CONFIG_TIMING_MASK) >> BACC_CONFIG_TIMING_SHIFT) - -/* Bitfield definition for register: PRE_TIME */ -/* - * PRE_RATIO (RW) - * - * Ratio of guard band before rising edge - * 0: 0 - * 1: 1/32768 of low level width - * 2: 1/16384 of low level width - * 14: 1/4 of low level width - * 15: 1/2 of low level width - */ -#define BACC_PRE_TIME_PRE_RATIO_MASK (0xF0000UL) -#define BACC_PRE_TIME_PRE_RATIO_SHIFT (16U) -#define BACC_PRE_TIME_PRE_RATIO_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_RATIO_SHIFT) & BACC_PRE_TIME_PRE_RATIO_MASK) -#define BACC_PRE_TIME_PRE_RATIO_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_RATIO_MASK) >> BACC_PRE_TIME_PRE_RATIO_SHIFT) - -/* - * PRE_OFFSET (RW) - * - * guard band before rising edge - * this value will be added to ratio number - */ -#define BACC_PRE_TIME_PRE_OFFSET_MASK (0xFFFFU) -#define BACC_PRE_TIME_PRE_OFFSET_SHIFT (0U) -#define BACC_PRE_TIME_PRE_OFFSET_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_OFFSET_SHIFT) & BACC_PRE_TIME_PRE_OFFSET_MASK) -#define BACC_PRE_TIME_PRE_OFFSET_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_OFFSET_MASK) >> BACC_PRE_TIME_PRE_OFFSET_SHIFT) - -/* Bitfield definition for register: POST_TIME */ -/* - * POST_RATIO (RW) - * - * Ratio of guard band after rising edge - * 0: 0 - * 1: 1/32768 of high level width - * 2: 1/16384 of high level width - * 14: 1/4 of high level width - * 15: 1/2 of high level width - */ -#define BACC_POST_TIME_POST_RATIO_MASK (0xF0000UL) -#define BACC_POST_TIME_POST_RATIO_SHIFT (16U) -#define BACC_POST_TIME_POST_RATIO_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_RATIO_SHIFT) & BACC_POST_TIME_POST_RATIO_MASK) -#define BACC_POST_TIME_POST_RATIO_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_RATIO_MASK) >> BACC_POST_TIME_POST_RATIO_SHIFT) - -/* - * POST_OFFSET (RW) - * - * guard band after rising edge - * this value will be added to ratio number - */ -#define BACC_POST_TIME_POST_OFFSET_MASK (0xFFFFU) -#define BACC_POST_TIME_POST_OFFSET_SHIFT (0U) -#define BACC_POST_TIME_POST_OFFSET_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_OFFSET_SHIFT) & BACC_POST_TIME_POST_OFFSET_MASK) -#define BACC_POST_TIME_POST_OFFSET_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_OFFSET_MASK) >> BACC_POST_TIME_POST_OFFSET_SHIFT) - - - - -#endif /* HPM_BACC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bcfg_regs.h deleted file mode 100644 index 059283c4cee..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bcfg_regs.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BCFG_H -#define HPM_BCFG_H - -typedef struct { - __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ - __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ - __RW uint32_t CLK_CFG; /* 0x10: Clock config */ -} BCFG_Type; - - -/* Bitfield definition for register: VBG_CFG */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) -#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) -#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) -#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Bandgap works in power save mode - * 0: not in power save mode - * 1: bandgap work in power save mode - */ -#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) -#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) -#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) -#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) - -/* - * VBG_1P0 (RW) - * - * Bandgap 1.0V output trim - */ -#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) -#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) -#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) -#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) - -/* - * VBG_P65 (RW) - * - * Bandgap 0.65V output trim - */ -#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) -#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) -#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) -#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) - -/* - * VBG_P50 (RW) - * - * Bandgap 0.50V output trim - */ -#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) -#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) -#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) -#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) - -/* Bitfield definition for register: IRC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) -#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: XTAL32K_CFG */ -/* - * HYST_EN (RW) - * - * crystal 32k hysteres enable - */ -#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) -#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) -#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) -#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) - -/* - * GMSEL (RW) - * - * crystal 32k gm selection - */ -#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) -#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) -#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) -#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) - -/* - * CFG (RW) - * - * crystal 32k config - */ -#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) -#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) -#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) -#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) - -/* - * AMP (RW) - * - * crystal 32k amplifier - */ -#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) -#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) -#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) -#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) - -/* Bitfield definition for register: CLK_CFG */ -/* - * XTAL_SEL (RO) - * - * crystal selected - */ -#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) -#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) -#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) - -/* - * KEEP_IRC (RW) - * - * force irc32k run - */ -#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) -#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) -#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) -#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) - -/* - * FORCE_XTAL (RW) - * - * force switch to crystal - */ -#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) -#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) -#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) -#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) - - - - -#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bgpr_regs.h deleted file mode 100644 index 9d81aab19cf..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bgpr_regs.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BGPR_H -#define HPM_BGPR_H - -typedef struct { - __RW uint32_t GPR[8]; /* 0x0 - 0x1C: Generic control */ -} BGPR_Type; - - -/* Bitfield definition for register array: GPR */ -/* - * DATA (RW) - * - * Generic control - */ -#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) -#define BGPR_GPR_DATA_SHIFT (0U) -#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) -#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) - - - -/* GPR register group index macro definition */ -#define BGPR_GPR_0 (0UL) -#define BGPR_GPR_1 (1UL) -#define BGPR_GPR_2 (2UL) -#define BGPR_GPR_3 (3UL) -#define BGPR_GPR_4 (4UL) -#define BGPR_GPR_5 (5UL) -#define BGPR_GPR_6 (6UL) -#define BGPR_GPR_7 (7UL) - - -#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bkey_regs.h deleted file mode 100644 index 1c82a4b90e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bkey_regs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BKEY_H -#define HPM_BKEY_H - -typedef struct { - struct { - __RW uint32_t DATA[8]; /* 0x0 - 0x1C: Key data */ - } KEY[2]; - __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ - __RW uint32_t SELECT; /* 0x48: Key selection */ -} BKEY_Type; - - -/* Bitfield definition for register of struct array KEY: 0 */ -/* - * DATA (RW) - * - * security key data - */ -#define BKEY_KEY_DATA_DATA_MASK (0xFFFFFFFFUL) -#define BKEY_KEY_DATA_DATA_SHIFT (0U) -#define BKEY_KEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_KEY_DATA_DATA_SHIFT) & BKEY_KEY_DATA_DATA_MASK) -#define BKEY_KEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_KEY_DATA_DATA_MASK) >> BKEY_KEY_DATA_DATA_SHIFT) - -/* Bitfield definition for register array: ECC */ -/* - * WLOCK (RW) - * - * write lock to key0 - * 0: write enable - * 1: write ignored - */ -#define BKEY_ECC_WLOCK_MASK (0x80000000UL) -#define BKEY_ECC_WLOCK_SHIFT (31U) -#define BKEY_ECC_WLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_WLOCK_SHIFT) & BKEY_ECC_WLOCK_MASK) -#define BKEY_ECC_WLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_WLOCK_MASK) >> BKEY_ECC_WLOCK_SHIFT) - -/* - * RLOCK (RW) - * - * read lock to key0 - * 0: key read enable - * 1: key always read as 0 - */ -#define BKEY_ECC_RLOCK_MASK (0x40000000UL) -#define BKEY_ECC_RLOCK_SHIFT (30U) -#define BKEY_ECC_RLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_RLOCK_SHIFT) & BKEY_ECC_RLOCK_MASK) -#define BKEY_ECC_RLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_RLOCK_MASK) >> BKEY_ECC_RLOCK_SHIFT) - -/* - * ECC (RW) - * - * Parity check bits for key0 - */ -#define BKEY_ECC_ECC_MASK (0xFFFFU) -#define BKEY_ECC_ECC_SHIFT (0U) -#define BKEY_ECC_ECC_SET(x) (((uint32_t)(x) << BKEY_ECC_ECC_SHIFT) & BKEY_ECC_ECC_MASK) -#define BKEY_ECC_ECC_GET(x) (((uint32_t)(x) & BKEY_ECC_ECC_MASK) >> BKEY_ECC_ECC_SHIFT) - -/* Bitfield definition for register: SELECT */ -/* - * SELECT (RW) - * - * select key, key0 treated as secure key, in non-scure mode, only key1 can be selected - * 0: select key0 in secure mode, key1 in non-secure mode - * 1: select key1 in secure or nonsecure mode - */ -#define BKEY_SELECT_SELECT_MASK (0x1U) -#define BKEY_SELECT_SELECT_SHIFT (0U) -#define BKEY_SELECT_SELECT_SET(x) (((uint32_t)(x) << BKEY_SELECT_SELECT_SHIFT) & BKEY_SELECT_SELECT_MASK) -#define BKEY_SELECT_SELECT_GET(x) (((uint32_t)(x) & BKEY_SELECT_SELECT_MASK) >> BKEY_SELECT_SELECT_SHIFT) - - - -/* DATA register group index macro definition */ -#define BKEY_KEY_DATA_0 (0UL) -#define BKEY_KEY_DATA_1 (1UL) -#define BKEY_KEY_DATA_2 (2UL) -#define BKEY_KEY_DATA_3 (3UL) -#define BKEY_KEY_DATA_4 (4UL) -#define BKEY_KEY_DATA_5 (5UL) -#define BKEY_KEY_DATA_6 (6UL) -#define BKEY_KEY_DATA_7 (7UL) - -/* KEY register group index macro definition */ -#define BKEY_KEY_0 (0UL) -#define BKEY_KEY_1 (1UL) - -/* ECC register group index macro definition */ -#define BKEY_ECC_KEY0 (0UL) -#define BKEY_ECC_KEY1 (1UL) - - -#endif /* HPM_BKEY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bmon_regs.h deleted file mode 100644 index f297a1dbb93..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bmon_regs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BMON_H -#define HPM_BMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - } MONITOR[2]; -} BMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define BMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define BMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define BMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ACTIVE_SHIFT) & BMON_MONITOR_CONTROL_ACTIVE_MASK) -#define BMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ACTIVE_MASK) >> BMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define BMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define BMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define BMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ENABLE_SHIFT) & BMON_MONITOR_CONTROL_ENABLE_MASK) -#define BMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ENABLE_MASK) >> BMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define BMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define BMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define BMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << BMON_MONITOR_STATUS_FLAG_SHIFT) & BMON_MONITOR_STATUS_FLAG_MASK) -#define BMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & BMON_MONITOR_STATUS_FLAG_MASK) >> BMON_MONITOR_STATUS_FLAG_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define BMON_MONITOR_GLITCH0 (0UL) -#define BMON_MONITOR_CLOCK0 (1UL) - - -#endif /* HPM_BMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bpor_regs.h deleted file mode 100644 index 8d0c023fdb9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bpor_regs.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BPOR_H -#define HPM_BPOR_H - -typedef struct { - __RW uint32_t POR_CONFIG; /* 0x0: Power on reset config */ -} BPOR_Type; - - -/* Bitfield definition for register: POR_CONFIG */ -/* - * RETENTION (RW) - * - * retention battery domain setting - * 0: battery reset on reset pin reset happen - * 1: battery domain retention when reset pin reset happen - */ -#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) -#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) -#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) -#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) - - - - -#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bsec_regs.h deleted file mode 100644 index 6167b47be78..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_bsec_regs.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BSEC_H -#define HPM_BSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ -} BSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * BATT_FAIL (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U) -#define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U) -#define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK) -#define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT) - -/* - * BATT_NSC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U) -#define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U) -#define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK) -#define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT) - -/* - * BATT_SEC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U) -#define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U) -#define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK) -#define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT) - -/* - * BATT_INS (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U) -#define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U) -#define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK) -#define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define BSEC_EVENT_EVENT_SHIFT (16U) -#define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT) - -/* - * BATT_ESC_NSC (RO) - * - * BATT is escalating non-secure event - */ -#define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U) -#define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U) -#define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT) - -/* - * BATT_ESC_SEC (RO) - * - * BATT is escalting ssecure event - */ -#define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U) -#define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U) -#define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT) - - - - -#endif /* HPM_BSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_butn_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_butn_regs.h deleted file mode 100644 index 03d711e0c58..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_butn_regs.h +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BUTN_H -#define HPM_BUTN_H - -typedef struct { - __RW uint32_t BTN_STATUS; /* 0x0: Button status */ - __RW uint32_t BTN_IRQ_MASK; /* 0x4: Button interrupt mask */ - __RW uint32_t LED_INTENSE; /* 0x8: Debounce setting */ -} BUTN_Type; - - -/* Bitfield definition for register: BTN_STATUS */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_STATUS_XWCLICK_SHIFT (28U) -#define BUTN_BTN_STATUS_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XWCLICK_SHIFT) & BUTN_BTN_STATUS_XWCLICK_MASK) -#define BUTN_BTN_STATUS_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XWCLICK_MASK) >> BUTN_BTN_STATUS_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_STATUS_WCLICK_SHIFT (24U) -#define BUTN_BTN_STATUS_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WCLICK_SHIFT) & BUTN_BTN_STATUS_WCLICK_MASK) -#define BUTN_BTN_STATUS_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WCLICK_MASK) >> BUTN_BTN_STATUS_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_STATUS_XPCLICK_SHIFT (20U) -#define BUTN_BTN_STATUS_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_XPCLICK_SHIFT) & BUTN_BTN_STATUS_XPCLICK_MASK) -#define BUTN_BTN_STATUS_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_XPCLICK_MASK) >> BUTN_BTN_STATUS_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click status, write 1 to clear flag - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_STATUS_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_STATUS_PCLICK_SHIFT (16U) -#define BUTN_BTN_STATUS_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PCLICK_SHIFT) & BUTN_BTN_STATUS_PCLICK_MASK) -#define BUTN_BTN_STATUS_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PCLICK_MASK) >> BUTN_BTN_STATUS_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_DBTN_MASK (0xF00U) -#define BUTN_BTN_STATUS_DBTN_SHIFT (8U) -#define BUTN_BTN_STATUS_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_DBTN_SHIFT) & BUTN_BTN_STATUS_DBTN_MASK) -#define BUTN_BTN_STATUS_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_DBTN_MASK) >> BUTN_BTN_STATUS_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_WBTN_MASK (0xF0U) -#define BUTN_BTN_STATUS_WBTN_SHIFT (4U) -#define BUTN_BTN_STATUS_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_WBTN_SHIFT) & BUTN_BTN_STATUS_WBTN_MASK) -#define BUTN_BTN_STATUS_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_WBTN_MASK) >> BUTN_BTN_STATUS_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press status, write 1 to clear flag - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_STATUS_PBTN_MASK (0xFU) -#define BUTN_BTN_STATUS_PBTN_SHIFT (0U) -#define BUTN_BTN_STATUS_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_STATUS_PBTN_SHIFT) & BUTN_BTN_STATUS_PBTN_MASK) -#define BUTN_BTN_STATUS_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_STATUS_PBTN_MASK) >> BUTN_BTN_STATUS_PBTN_SHIFT) - -/* Bitfield definition for register: BTN_IRQ_MASK */ -/* - * XWCLICK (RW) - * - * wake button click status when power button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XWCLICK_MASK (0x70000000UL) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT (28U) -#define BUTN_BTN_IRQ_MASK_XWCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XWCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XWCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XWCLICK_SHIFT) - -/* - * WCLICK (RW) - * - * wake button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_WCLICK_MASK (0x7000000UL) -#define BUTN_BTN_IRQ_MASK_WCLICK_SHIFT (24U) -#define BUTN_BTN_IRQ_MASK_WCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_WCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WCLICK_MASK) >> BUTN_BTN_IRQ_MASK_WCLICK_SHIFT) - -/* - * XPCLICK (RW) - * - * power button click status when wake button held interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_XPCLICK_MASK (0x700000UL) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT (20U) -#define BUTN_BTN_IRQ_MASK_XPCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_XPCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_XPCLICK_MASK) >> BUTN_BTN_IRQ_MASK_XPCLICK_SHIFT) - -/* - * PCLICK (RW) - * - * power button click interrupt enable - * bit0: clicked - * bit1: double clicked - * bit2: tripple clicked - */ -#define BUTN_BTN_IRQ_MASK_PCLICK_MASK (0x70000UL) -#define BUTN_BTN_IRQ_MASK_PCLICK_SHIFT (16U) -#define BUTN_BTN_IRQ_MASK_PCLICK_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) -#define BUTN_BTN_IRQ_MASK_PCLICK_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PCLICK_MASK) >> BUTN_BTN_IRQ_MASK_PCLICK_SHIFT) - -/* - * DBTN (RW) - * - * Dual button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_DBTN_MASK (0xF00U) -#define BUTN_BTN_IRQ_MASK_DBTN_SHIFT (8U) -#define BUTN_BTN_IRQ_MASK_DBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_DBTN_SHIFT) & BUTN_BTN_IRQ_MASK_DBTN_MASK) -#define BUTN_BTN_IRQ_MASK_DBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_DBTN_MASK) >> BUTN_BTN_IRQ_MASK_DBTN_SHIFT) - -/* - * WBTN (RW) - * - * Wake button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_WBTN_MASK (0xF0U) -#define BUTN_BTN_IRQ_MASK_WBTN_SHIFT (4U) -#define BUTN_BTN_IRQ_MASK_WBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_WBTN_SHIFT) & BUTN_BTN_IRQ_MASK_WBTN_MASK) -#define BUTN_BTN_IRQ_MASK_WBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_WBTN_MASK) >> BUTN_BTN_IRQ_MASK_WBTN_SHIFT) - -/* - * PBTN (RW) - * - * Power button press interrupt enable - * bit0: button pressed - * bit1: button confirmd - * bit2: button long pressed - * bit3: button long long pressed - */ -#define BUTN_BTN_IRQ_MASK_PBTN_MASK (0xFU) -#define BUTN_BTN_IRQ_MASK_PBTN_SHIFT (0U) -#define BUTN_BTN_IRQ_MASK_PBTN_SET(x) (((uint32_t)(x) << BUTN_BTN_IRQ_MASK_PBTN_SHIFT) & BUTN_BTN_IRQ_MASK_PBTN_MASK) -#define BUTN_BTN_IRQ_MASK_PBTN_GET(x) (((uint32_t)(x) & BUTN_BTN_IRQ_MASK_PBTN_MASK) >> BUTN_BTN_IRQ_MASK_PBTN_SHIFT) - -/* Bitfield definition for register: LED_INTENSE */ -/* - * RLED (RW) - * - * Rbutton brightness 0 - */ -#define BUTN_LED_INTENSE_RLED_MASK (0xF0000UL) -#define BUTN_LED_INTENSE_RLED_SHIFT (16U) -#define BUTN_LED_INTENSE_RLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_RLED_SHIFT) & BUTN_LED_INTENSE_RLED_MASK) -#define BUTN_LED_INTENSE_RLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_RLED_MASK) >> BUTN_LED_INTENSE_RLED_SHIFT) - -/* - * PLED (RW) - * - * Pbutton brightness 0 - */ -#define BUTN_LED_INTENSE_PLED_MASK (0xFU) -#define BUTN_LED_INTENSE_PLED_SHIFT (0U) -#define BUTN_LED_INTENSE_PLED_SET(x) (((uint32_t)(x) << BUTN_LED_INTENSE_PLED_SHIFT) & BUTN_LED_INTENSE_PLED_MASK) -#define BUTN_LED_INTENSE_PLED_GET(x) (((uint32_t)(x) & BUTN_LED_INTENSE_PLED_MASK) >> BUTN_LED_INTENSE_PLED_SHIFT) - - - - -#endif /* HPM_BUTN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_cam_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_cam_regs.h deleted file mode 100644 index 1003b1b89a6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_cam_regs.h +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CAM_H -#define HPM_CAM_H - -typedef struct { - __RW uint32_t CR1; /* 0x0: Control Register */ - __RW uint32_t INT_EN; /* 0x4: Interrupt Enable Register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t CR2; /* 0x10: Control 2 Register */ - __R uint8_t RESERVED1[16]; /* 0x14 - 0x23: Reserved */ - __RW uint32_t STA; /* 0x24: Status Register */ - __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ - __RW uint32_t DMASA_FB1; /* 0x30: Pixel DMA Frame Buffer 1 Address */ - __RW uint32_t DMASA_FB2; /* 0x34: Pixel DMA Frame Buffer 2 Address */ - __RW uint32_t BUF_PARA; /* 0x38: Buffer Parameters Register */ - __RW uint32_t IDEAL_WN_SIZE; /* 0x3C: Ideal Image Size Register */ - __R uint8_t RESERVED3[12]; /* 0x40 - 0x4B: Reserved */ - __RW uint32_t CR18; /* 0x4C: Control CR18 Register */ - __RW uint32_t DMASA_UV1; /* 0x50: Pixel UV DMA Frame Buffer 1 Address */ - __RW uint32_t DMASA_UV2; /* 0x54: Pixel UV DMA Frame Buffer 2 Address */ - __RW uint32_t CR20; /* 0x58: Control CR20 Register */ - __R uint8_t RESERVED4[20]; /* 0x5C - 0x6F: Reserved */ - __RW uint32_t CSC_COEF0; /* 0x70: Color Space Conversion Config Register 0 */ - __RW uint32_t CSC_COEF1; /* 0x74: Color Space Conversion Config Register 1 */ - __RW uint32_t CSC_COEF2; /* 0x78: Color Space Conversion Config Register 2 */ - __RW uint32_t CLRKEY_LOW; /* 0x7C: Low Color Key Register */ - __RW uint32_t CLRKEY_HIGH; /* 0x80: High Color Key Register */ - __R uint8_t RESERVED5[12]; /* 0x84 - 0x8F: Reserved */ - __R uint32_t HISTOGRAM_FIFO[256]; /* 0x90 - 0x48C: Histogram Registers */ - __RW uint32_t ROI_WIDTH; /* 0x490: Roi Width Config Register */ - __RW uint32_t ROI_HEIGHT; /* 0x494: Roi Width Config Register */ - __RW uint32_t PRO_CTRL; /* 0x498: Pro Config Register */ - __RW uint32_t ACT_SIZE; /* 0x49C: actual size */ - __RW uint32_t VSYNC_VALID_CNT; /* 0x4A0: vsync valid counter */ - __RW uint32_t HSYNC_VALID_CNT; /* 0x4A4: hsync valid counter */ - __RW uint32_t VALID_MARGIN; /* 0x4A8: valid margin */ - __RW uint32_t ALARM_SET; /* 0x4AC: alarm set */ -} CAM_Type; - - -/* Bitfield definition for register: CR1 */ -/* - * INV_DEN (RW) - * - * invert den pad input before it is used - */ -#define CAM_CR1_INV_DEN_MASK (0x40000000UL) -#define CAM_CR1_INV_DEN_SHIFT (30U) -#define CAM_CR1_INV_DEN_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DEN_SHIFT) & CAM_CR1_INV_DEN_MASK) -#define CAM_CR1_INV_DEN_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DEN_MASK) >> CAM_CR1_INV_DEN_SHIFT) - -/* - * COLOR_EXT (RW) - * - * If asserted, will change the output color to ARGB8888 mode. Used by input color as RGB565, RGB888, YUV888, etc. - * The byte sequence is B,G,R,A. Depends on correct CR2[ClrBitFormat] configuration. - */ -#define CAM_CR1_COLOR_EXT_MASK (0x20000000UL) -#define CAM_CR1_COLOR_EXT_SHIFT (29U) -#define CAM_CR1_COLOR_EXT_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_EXT_SHIFT) & CAM_CR1_COLOR_EXT_MASK) -#define CAM_CR1_COLOR_EXT_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_EXT_MASK) >> CAM_CR1_COLOR_EXT_SHIFT) - -/* - * INV_PIXCLK (RW) - * - * invert pixclk pad input before it is used - */ -#define CAM_CR1_INV_PIXCLK_MASK (0x10000000UL) -#define CAM_CR1_INV_PIXCLK_SHIFT (28U) -#define CAM_CR1_INV_PIXCLK_SET(x) (((uint32_t)(x) << CAM_CR1_INV_PIXCLK_SHIFT) & CAM_CR1_INV_PIXCLK_MASK) -#define CAM_CR1_INV_PIXCLK_GET(x) (((uint32_t)(x) & CAM_CR1_INV_PIXCLK_MASK) >> CAM_CR1_INV_PIXCLK_SHIFT) - -/* - * INV_HSYNC (RW) - * - * invert hsync pad input before it is used - */ -#define CAM_CR1_INV_HSYNC_MASK (0x8000000UL) -#define CAM_CR1_INV_HSYNC_SHIFT (27U) -#define CAM_CR1_INV_HSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_HSYNC_SHIFT) & CAM_CR1_INV_HSYNC_MASK) -#define CAM_CR1_INV_HSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_HSYNC_MASK) >> CAM_CR1_INV_HSYNC_SHIFT) - -/* - * INV_VSYNC (RW) - * - * invert vsync pad input before it is used - */ -#define CAM_CR1_INV_VSYNC_MASK (0x4000000UL) -#define CAM_CR1_INV_VSYNC_SHIFT (26U) -#define CAM_CR1_INV_VSYNC_SET(x) (((uint32_t)(x) << CAM_CR1_INV_VSYNC_SHIFT) & CAM_CR1_INV_VSYNC_MASK) -#define CAM_CR1_INV_VSYNC_GET(x) (((uint32_t)(x) & CAM_CR1_INV_VSYNC_MASK) >> CAM_CR1_INV_VSYNC_SHIFT) - -/* - * SWAP16_EN (RW) - * - * SWAP 16-Bit Enable. This bit enables the swapping of 16-bit data. Data is packed from 8-bit or 10-bit to 32-bit first (according to the setting of PACK_DIR) and then swapped as 16-bit words before being put into the RX FIFO. The action of the bit only affects the RX FIFO. - * NOTE: Example of swapping enabled: - * Data input to FIFO = 0x11223344 - * Data in RX FIFO = 0x 33441122 - * NOTE: Example of swapping disabled: - * Data input to FIFO = 0x11223344 - * Data in RX FIFO = 0x11223344 - * 0 Disable swapping - * 1 Enable swapping - */ -#define CAM_CR1_SWAP16_EN_MASK (0x2000000UL) -#define CAM_CR1_SWAP16_EN_SHIFT (25U) -#define CAM_CR1_SWAP16_EN_SET(x) (((uint32_t)(x) << CAM_CR1_SWAP16_EN_SHIFT) & CAM_CR1_SWAP16_EN_MASK) -#define CAM_CR1_SWAP16_EN_GET(x) (((uint32_t)(x) & CAM_CR1_SWAP16_EN_MASK) >> CAM_CR1_SWAP16_EN_SHIFT) - -/* - * PACK_DIR (RW) - * - * Data Packing Direction. This bit Controls how 8-bit/10-bit image data is packed into 32-bit RX FIFO. - * 0 Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. - * 1 Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. - */ -#define CAM_CR1_PACK_DIR_MASK (0x1000000UL) -#define CAM_CR1_PACK_DIR_SHIFT (24U) -#define CAM_CR1_PACK_DIR_SET(x) (((uint32_t)(x) << CAM_CR1_PACK_DIR_SHIFT) & CAM_CR1_PACK_DIR_MASK) -#define CAM_CR1_PACK_DIR_GET(x) (((uint32_t)(x) & CAM_CR1_PACK_DIR_MASK) >> CAM_CR1_PACK_DIR_SHIFT) - -/* - * RESTART_BUSPTR (RW) - * - * force to restart the bus pointer at the every end of the sof period, and at the same time, clr the fifo pointer - */ -#define CAM_CR1_RESTART_BUSPTR_MASK (0x800000UL) -#define CAM_CR1_RESTART_BUSPTR_SHIFT (23U) -#define CAM_CR1_RESTART_BUSPTR_SET(x) (((uint32_t)(x) << CAM_CR1_RESTART_BUSPTR_SHIFT) & CAM_CR1_RESTART_BUSPTR_MASK) -#define CAM_CR1_RESTART_BUSPTR_GET(x) (((uint32_t)(x) & CAM_CR1_RESTART_BUSPTR_MASK) >> CAM_CR1_RESTART_BUSPTR_SHIFT) - -/* - * ASYNC_RXFIFO_CLR (RW) - * - * ASynchronous Rx FIFO Clear. - * When asserted, this bit clears RXFIFO immediately. - * It will be auto-cleared. - */ -#define CAM_CR1_ASYNC_RXFIFO_CLR_MASK (0x100000UL) -#define CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT (20U) -#define CAM_CR1_ASYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) -#define CAM_CR1_ASYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_ASYNC_RXFIFO_CLR_MASK) >> CAM_CR1_ASYNC_RXFIFO_CLR_SHIFT) - -/* - * SYNC_RXFIFO_CLR (RW) - * - * Synchronous Rx FIFO Clear. - * When asserted, this bit clears RXFIFO on every SOF. - */ -#define CAM_CR1_SYNC_RXFIFO_CLR_MASK (0x80000UL) -#define CAM_CR1_SYNC_RXFIFO_CLR_SHIFT (19U) -#define CAM_CR1_SYNC_RXFIFO_CLR_SET(x) (((uint32_t)(x) << CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) -#define CAM_CR1_SYNC_RXFIFO_CLR_GET(x) (((uint32_t)(x) & CAM_CR1_SYNC_RXFIFO_CLR_MASK) >> CAM_CR1_SYNC_RXFIFO_CLR_SHIFT) - -/* - * SOF_INT_POL (RW) - * - * SOF Interrupt Polarity. This bit controls the condition that generates an SOF interrupt. - * 0 SOF interrupt is generated on SOF falling edge - * 1 SOF interrupt is generated on SOF rising edge - */ -#define CAM_CR1_SOF_INT_POL_MASK (0x20000UL) -#define CAM_CR1_SOF_INT_POL_SHIFT (17U) -#define CAM_CR1_SOF_INT_POL_SET(x) (((uint32_t)(x) << CAM_CR1_SOF_INT_POL_SHIFT) & CAM_CR1_SOF_INT_POL_MASK) -#define CAM_CR1_SOF_INT_POL_GET(x) (((uint32_t)(x) & CAM_CR1_SOF_INT_POL_MASK) >> CAM_CR1_SOF_INT_POL_SHIFT) - -/* - * INV_DATA (RW) - * - * Invert Data Input. This bit enables or disables internal inverters on the data lines. - * 0 CAM_D data lines are directly applied to internal circuitry - * 1 CAM_D data lines are inverted before applied to internal circuitry - */ -#define CAM_CR1_INV_DATA_MASK (0x8000U) -#define CAM_CR1_INV_DATA_SHIFT (15U) -#define CAM_CR1_INV_DATA_SET(x) (((uint32_t)(x) << CAM_CR1_INV_DATA_SHIFT) & CAM_CR1_INV_DATA_MASK) -#define CAM_CR1_INV_DATA_GET(x) (((uint32_t)(x) & CAM_CR1_INV_DATA_MASK) >> CAM_CR1_INV_DATA_SHIFT) - -/* - * STORAGE_MODE (RW) - * - * 00: Normal Mode (one plane mode) - * 01: Two Plane Mode (Y, UV plane) - * 10: Y-only Mode, byte sequence as Y0,Y1,Y2,Y3 - * 11: Binary Mode, bit sequence is from LSB to MSB when CR20[BIG_END]=0 - */ -#define CAM_CR1_STORAGE_MODE_MASK (0xC00U) -#define CAM_CR1_STORAGE_MODE_SHIFT (10U) -#define CAM_CR1_STORAGE_MODE_SET(x) (((uint32_t)(x) << CAM_CR1_STORAGE_MODE_SHIFT) & CAM_CR1_STORAGE_MODE_MASK) -#define CAM_CR1_STORAGE_MODE_GET(x) (((uint32_t)(x) & CAM_CR1_STORAGE_MODE_MASK) >> CAM_CR1_STORAGE_MODE_SHIFT) - -/* - * COLOR_FORMATS (RW) - * - * input color formats: - * 0010b:24bit:RGB888 - * 0011b:24bit:RGB666 - * 0100b:16bit:RGB565 - * 0101b:16bit:RGB444 - * 0110b:16bit:RGB555 - * 0111b: 16bit: YCbCr422 (Y0 Cb Y1 Cr, each 8-bit) - * YUV - * YCrCb - * Note: YUV420 is not supported. - * 1000b: 24bit: YUV444 - */ -#define CAM_CR1_COLOR_FORMATS_MASK (0x78U) -#define CAM_CR1_COLOR_FORMATS_SHIFT (3U) -#define CAM_CR1_COLOR_FORMATS_SET(x) (((uint32_t)(x) << CAM_CR1_COLOR_FORMATS_SHIFT) & CAM_CR1_COLOR_FORMATS_MASK) -#define CAM_CR1_COLOR_FORMATS_GET(x) (((uint32_t)(x) & CAM_CR1_COLOR_FORMATS_MASK) >> CAM_CR1_COLOR_FORMATS_SHIFT) - -/* - * SENSOR_BIT_WIDTH (RW) - * - * the bit width of the sensor - * 0: 8 bits - * 1: 10 bits - * 3:24bits - * Others: Undefined - */ -#define CAM_CR1_SENSOR_BIT_WIDTH_MASK (0x7U) -#define CAM_CR1_SENSOR_BIT_WIDTH_SHIFT (0U) -#define CAM_CR1_SENSOR_BIT_WIDTH_SET(x) (((uint32_t)(x) << CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) -#define CAM_CR1_SENSOR_BIT_WIDTH_GET(x) (((uint32_t)(x) & CAM_CR1_SENSOR_BIT_WIDTH_MASK) >> CAM_CR1_SENSOR_BIT_WIDTH_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * ERR_CL_BWID_CFG_INT_EN (RW) - * - * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation interrupt enable - */ -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK (0x2000U) -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT (13U) -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) -#define CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_MASK) >> CAM_INT_EN_ERR_CL_BWID_CFG_INT_EN_SHIFT) - -/* - * HIST_DONE_INT_EN (RW) - * - * Enable hist done int - */ -#define CAM_INT_EN_HIST_DONE_INT_EN_MASK (0x1000U) -#define CAM_INT_EN_HIST_DONE_INT_EN_SHIFT (12U) -#define CAM_INT_EN_HIST_DONE_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) -#define CAM_INT_EN_HIST_DONE_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HIST_DONE_INT_EN_MASK) >> CAM_INT_EN_HIST_DONE_INT_EN_SHIFT) - -/* - * HRESP_ERR_EN (RW) - * - * Hresponse Error Enable. This bit enables the hresponse error interrupt. - * 0 Disable hresponse error interrupt - * 1 Enable hresponse error interrupt - */ -#define CAM_INT_EN_HRESP_ERR_EN_MASK (0x800U) -#define CAM_INT_EN_HRESP_ERR_EN_SHIFT (11U) -#define CAM_INT_EN_HRESP_ERR_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_HRESP_ERR_EN_SHIFT) & CAM_INT_EN_HRESP_ERR_EN_MASK) -#define CAM_INT_EN_HRESP_ERR_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_HRESP_ERR_EN_MASK) >> CAM_INT_EN_HRESP_ERR_EN_SHIFT) - -/* - * EOF_INT_EN (RW) - * - * End-of-Frame Interrupt Enable. This bit enables and disables the EOF interrupt. - * 0 EOF interrupt is disabled. - * 1 EOF interrupt is generated when RX count value is reached. - */ -#define CAM_INT_EN_EOF_INT_EN_MASK (0x200U) -#define CAM_INT_EN_EOF_INT_EN_SHIFT (9U) -#define CAM_INT_EN_EOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_EOF_INT_EN_SHIFT) & CAM_INT_EN_EOF_INT_EN_MASK) -#define CAM_INT_EN_EOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_EOF_INT_EN_MASK) >> CAM_INT_EN_EOF_INT_EN_SHIFT) - -/* - * RF_OR_INTEN (RW) - * - * RxFIFO Overrun Interrupt Enable. This bit enables the RX FIFO overrun interrupt. - * 0 RxFIFO overrun interrupt is disabled - * 1 RxFIFO overrun interrupt is enabled - */ -#define CAM_INT_EN_RF_OR_INTEN_MASK (0x40U) -#define CAM_INT_EN_RF_OR_INTEN_SHIFT (6U) -#define CAM_INT_EN_RF_OR_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_RF_OR_INTEN_SHIFT) & CAM_INT_EN_RF_OR_INTEN_MASK) -#define CAM_INT_EN_RF_OR_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_RF_OR_INTEN_MASK) >> CAM_INT_EN_RF_OR_INTEN_SHIFT) - -/* - * FB2_DMA_DONE_INTEN (RW) - * - * Frame Buffer2 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer2 DMA - * transfer done. - * 0 Frame Buffer2 DMA Transfer Done interrupt disable - * 1 Frame Buffer2 DMA Transfer Done interrupt enable - */ -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK (0x8U) -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT (3U) -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) -#define CAM_INT_EN_FB2_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB2_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB2_DMA_DONE_INTEN_SHIFT) - -/* - * FB1_DMA_DONE_INTEN (RW) - * - * Frame Buffer1 DMA Transfer Done Interrupt Enable. This bit enables the interrupt of Frame Buffer1 DMA - * transfer done. - * 0 Frame Buffer1 DMA Transfer Done interrupt disable - * 1 Frame Buffer1 DMA Transfer Done interrupt enable - */ -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK (0x4U) -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT (2U) -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_SET(x) (((uint32_t)(x) << CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) -#define CAM_INT_EN_FB1_DMA_DONE_INTEN_GET(x) (((uint32_t)(x) & CAM_INT_EN_FB1_DMA_DONE_INTEN_MASK) >> CAM_INT_EN_FB1_DMA_DONE_INTEN_SHIFT) - -/* - * SOF_INT_EN (RW) - * - * Start Of Frame (SOF) Interrupt Enable. This bit enables the SOF interrupt. - * 0 SOF interrupt disable - * 1 SOF interrupt enable - */ -#define CAM_INT_EN_SOF_INT_EN_MASK (0x1U) -#define CAM_INT_EN_SOF_INT_EN_SHIFT (0U) -#define CAM_INT_EN_SOF_INT_EN_SET(x) (((uint32_t)(x) << CAM_INT_EN_SOF_INT_EN_SHIFT) & CAM_INT_EN_SOF_INT_EN_MASK) -#define CAM_INT_EN_SOF_INT_EN_GET(x) (((uint32_t)(x) & CAM_INT_EN_SOF_INT_EN_MASK) >> CAM_INT_EN_SOF_INT_EN_SHIFT) - -/* Bitfield definition for register: CR2 */ -/* - * FRMCNT_15_0 (RO) - * - * Frame Counter. This is a 16-bit Frame Counter - * (Wraps around automatically after reaching the maximum) - */ -#define CAM_CR2_FRMCNT_15_0_MASK (0xFFFF0000UL) -#define CAM_CR2_FRMCNT_15_0_SHIFT (16U) -#define CAM_CR2_FRMCNT_15_0_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_15_0_MASK) >> CAM_CR2_FRMCNT_15_0_SHIFT) - -/* - * FRMCNT_RST (RW) - * - * Frame Count Reset. Resets the Frame Counter. - * 0 Do not reset - * 1 Reset frame counter immediately - */ -#define CAM_CR2_FRMCNT_RST_MASK (0x8000U) -#define CAM_CR2_FRMCNT_RST_SHIFT (15U) -#define CAM_CR2_FRMCNT_RST_SET(x) (((uint32_t)(x) << CAM_CR2_FRMCNT_RST_SHIFT) & CAM_CR2_FRMCNT_RST_MASK) -#define CAM_CR2_FRMCNT_RST_GET(x) (((uint32_t)(x) & CAM_CR2_FRMCNT_RST_MASK) >> CAM_CR2_FRMCNT_RST_SHIFT) - -/* - * RXFF_LEVEL (RW) - * - * RxFIFO Full Level. When the number of data in RxFIFO reaches this level, a RxFIFO full interrupt is generated, or an RXFIFO DMA request is sent. - * 000 4 Double words - * 001 8 Double words - * 010 16 Double words - * 011 24 Double words - * 100 32 Double words - * 101 48 Double words - * 110 64 Double words - * 111 96 Double words - */ -#define CAM_CR2_RXFF_LEVEL_MASK (0xE00U) -#define CAM_CR2_RXFF_LEVEL_SHIFT (9U) -#define CAM_CR2_RXFF_LEVEL_SET(x) (((uint32_t)(x) << CAM_CR2_RXFF_LEVEL_SHIFT) & CAM_CR2_RXFF_LEVEL_MASK) -#define CAM_CR2_RXFF_LEVEL_GET(x) (((uint32_t)(x) & CAM_CR2_RXFF_LEVEL_MASK) >> CAM_CR2_RXFF_LEVEL_SHIFT) - -/* - * DMA_REQ_EN_RFF (RW) - * - * DMA Request Enable for RxFIFO. This bit enables the dma request from RxFIFO to the embedded DMA controller. - * 0 Disable the dma request - * 1 Enable the dma request. The UV Rx FIFO is only enabled to filling data in 2 plane mode. - */ -#define CAM_CR2_DMA_REQ_EN_RFF_MASK (0x20U) -#define CAM_CR2_DMA_REQ_EN_RFF_SHIFT (5U) -#define CAM_CR2_DMA_REQ_EN_RFF_SET(x) (((uint32_t)(x) << CAM_CR2_DMA_REQ_EN_RFF_SHIFT) & CAM_CR2_DMA_REQ_EN_RFF_MASK) -#define CAM_CR2_DMA_REQ_EN_RFF_GET(x) (((uint32_t)(x) & CAM_CR2_DMA_REQ_EN_RFF_MASK) >> CAM_CR2_DMA_REQ_EN_RFF_SHIFT) - -/* - * CLRBITFORMAT (RW) - * - * Input Byte & bit sequence same as OV5640, except for Raw mode. Used only for internal ARGB conversion. - */ -#define CAM_CR2_CLRBITFORMAT_MASK (0xFU) -#define CAM_CR2_CLRBITFORMAT_SHIFT (0U) -#define CAM_CR2_CLRBITFORMAT_SET(x) (((uint32_t)(x) << CAM_CR2_CLRBITFORMAT_SHIFT) & CAM_CR2_CLRBITFORMAT_MASK) -#define CAM_CR2_CLRBITFORMAT_GET(x) (((uint32_t)(x) & CAM_CR2_CLRBITFORMAT_MASK) >> CAM_CR2_CLRBITFORMAT_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * ERR_CL_BWID_CFG (W1C) - * - * The unsupported color (color_formats[3:0]) and bitwidth (sensor_bit_width[2:0]) configuation found - */ -#define CAM_STA_ERR_CL_BWID_CFG_MASK (0x80000UL) -#define CAM_STA_ERR_CL_BWID_CFG_SHIFT (19U) -#define CAM_STA_ERR_CL_BWID_CFG_SET(x) (((uint32_t)(x) << CAM_STA_ERR_CL_BWID_CFG_SHIFT) & CAM_STA_ERR_CL_BWID_CFG_MASK) -#define CAM_STA_ERR_CL_BWID_CFG_GET(x) (((uint32_t)(x) & CAM_STA_ERR_CL_BWID_CFG_MASK) >> CAM_STA_ERR_CL_BWID_CFG_SHIFT) - -/* - * HIST_DONE (W1C) - * - * hist cal done - */ -#define CAM_STA_HIST_DONE_MASK (0x40000UL) -#define CAM_STA_HIST_DONE_SHIFT (18U) -#define CAM_STA_HIST_DONE_SET(x) (((uint32_t)(x) << CAM_STA_HIST_DONE_SHIFT) & CAM_STA_HIST_DONE_MASK) -#define CAM_STA_HIST_DONE_GET(x) (((uint32_t)(x) & CAM_STA_HIST_DONE_MASK) >> CAM_STA_HIST_DONE_SHIFT) - -/* - * RF_OR_INT (W1C) - * - * RxFIFO Overrun Interrupt Status. Indicates the overflow status of the RxFIFO register. (Cleared by writing - * 1) - * 0 RXFIFO has not overflowed. - * 1 RXFIFO has overflowed. - */ -#define CAM_STA_RF_OR_INT_MASK (0x2000U) -#define CAM_STA_RF_OR_INT_SHIFT (13U) -#define CAM_STA_RF_OR_INT_SET(x) (((uint32_t)(x) << CAM_STA_RF_OR_INT_SHIFT) & CAM_STA_RF_OR_INT_MASK) -#define CAM_STA_RF_OR_INT_GET(x) (((uint32_t)(x) & CAM_STA_RF_OR_INT_MASK) >> CAM_STA_RF_OR_INT_SHIFT) - -/* - * DMA_TSF_DONE_FB2 (W1C) - * - * DMA Transfer Done in Frame Buffer2. Indicates that the DMA transfer from RxFIFO to Frame Buffer2 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) - * 0 DMA transfer is not completed. - * 1 DMA transfer is completed. - */ -#define CAM_STA_DMA_TSF_DONE_FB2_MASK (0x400U) -#define CAM_STA_DMA_TSF_DONE_FB2_SHIFT (10U) -#define CAM_STA_DMA_TSF_DONE_FB2_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB2_SHIFT) & CAM_STA_DMA_TSF_DONE_FB2_MASK) -#define CAM_STA_DMA_TSF_DONE_FB2_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB2_MASK) >> CAM_STA_DMA_TSF_DONE_FB2_SHIFT) - -/* - * DMA_TSF_DONE_FB1 (W1C) - * - * DMA Transfer Done in Frame Buffer1. Indicates that the DMA transfer from RxFIFO to Frame Buffer1 is completed. It can trigger an interrupt if the corresponding enable bit is set in CAM_CR1. This bit can be cleared by by writing 1 or reflashing the RxFIFO dma controller in CAM_CR3. (Cleared by writing 1) - * 0 DMA transfer is not completed. - * 1 DMA transfer is completed. - */ -#define CAM_STA_DMA_TSF_DONE_FB1_MASK (0x200U) -#define CAM_STA_DMA_TSF_DONE_FB1_SHIFT (9U) -#define CAM_STA_DMA_TSF_DONE_FB1_SET(x) (((uint32_t)(x) << CAM_STA_DMA_TSF_DONE_FB1_SHIFT) & CAM_STA_DMA_TSF_DONE_FB1_MASK) -#define CAM_STA_DMA_TSF_DONE_FB1_GET(x) (((uint32_t)(x) & CAM_STA_DMA_TSF_DONE_FB1_MASK) >> CAM_STA_DMA_TSF_DONE_FB1_SHIFT) - -/* - * EOF_INT (W1C) - * - * End of Frame (EOF) Interrupt Status. Indicates when EOF is detected. (Cleared by writing 1) - * 0 EOF is not detected. - * 1 EOF is detected. - */ -#define CAM_STA_EOF_INT_MASK (0x80U) -#define CAM_STA_EOF_INT_SHIFT (7U) -#define CAM_STA_EOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_EOF_INT_SHIFT) & CAM_STA_EOF_INT_MASK) -#define CAM_STA_EOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_EOF_INT_MASK) >> CAM_STA_EOF_INT_SHIFT) - -/* - * SOF_INT (W1C) - * - * Start of Frame Interrupt Status. Indicates when SOF is detected. (Cleared by writing 1) - * 0 SOF is not detected. - * 1 SOF is detected. - */ -#define CAM_STA_SOF_INT_MASK (0x40U) -#define CAM_STA_SOF_INT_SHIFT (6U) -#define CAM_STA_SOF_INT_SET(x) (((uint32_t)(x) << CAM_STA_SOF_INT_SHIFT) & CAM_STA_SOF_INT_MASK) -#define CAM_STA_SOF_INT_GET(x) (((uint32_t)(x) & CAM_STA_SOF_INT_MASK) >> CAM_STA_SOF_INT_SHIFT) - -/* - * HRESP_ERR_INT (W1C) - * - * Hresponse Error Interrupt Status. Indicates that a hresponse error has been detected. (Cleared by writing - * 1) - * 0 No hresponse error. - * 1 Hresponse error is detected. - */ -#define CAM_STA_HRESP_ERR_INT_MASK (0x4U) -#define CAM_STA_HRESP_ERR_INT_SHIFT (2U) -#define CAM_STA_HRESP_ERR_INT_SET(x) (((uint32_t)(x) << CAM_STA_HRESP_ERR_INT_SHIFT) & CAM_STA_HRESP_ERR_INT_MASK) -#define CAM_STA_HRESP_ERR_INT_GET(x) (((uint32_t)(x) & CAM_STA_HRESP_ERR_INT_MASK) >> CAM_STA_HRESP_ERR_INT_SHIFT) - -/* Bitfield definition for register: DMASA_FB1 */ -/* - * PTR (RW) - * - * DMA Start Address in Frame Buffer1. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. - * In Two-Plane Mode, Y buffer1 - */ -#define CAM_DMASA_FB1_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_FB1_PTR_SHIFT (2U) -#define CAM_DMASA_FB1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB1_PTR_SHIFT) & CAM_DMASA_FB1_PTR_MASK) -#define CAM_DMASA_FB1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB1_PTR_MASK) >> CAM_DMASA_FB1_PTR_SHIFT) - -/* Bitfield definition for register: DMASA_FB2 */ -/* - * PTR (RW) - * - * DMA Start Address in Frame Buffer2. Indicates the start address to write data. The embedded DMA controller will read data from RxFIFO and write it from this address through AHB bus. The address should be double words aligned. - * In Two-Plane Mode, Y buffer2 - */ -#define CAM_DMASA_FB2_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_FB2_PTR_SHIFT (2U) -#define CAM_DMASA_FB2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_FB2_PTR_SHIFT) & CAM_DMASA_FB2_PTR_MASK) -#define CAM_DMASA_FB2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_FB2_PTR_MASK) >> CAM_DMASA_FB2_PTR_SHIFT) - -/* Bitfield definition for register: BUF_PARA */ -/* - * LINEBSP_STRIDE (RW) - * - * Line Blank Space Stride. Indicates the space between the end of line image storage and the start of a new line storage in the frame buffer. - * The width of the line storage in frame buffer(in double words) minus the width of the image(in double words) is the stride. The stride should be double words aligned. The embedded DMA controller will skip the stride before starting to write the next row of the image. - */ -#define CAM_BUF_PARA_LINEBSP_STRIDE_MASK (0xFFFFU) -#define CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT (0U) -#define CAM_BUF_PARA_LINEBSP_STRIDE_SET(x) (((uint32_t)(x) << CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) -#define CAM_BUF_PARA_LINEBSP_STRIDE_GET(x) (((uint32_t)(x) & CAM_BUF_PARA_LINEBSP_STRIDE_MASK) >> CAM_BUF_PARA_LINEBSP_STRIDE_SHIFT) - -/* Bitfield definition for register: IDEAL_WN_SIZE */ -/* - * HEIGHT (RW) - * - * Image Height. Indicates how many active pixels in a column of the image from the sensor. - */ -#define CAM_IDEAL_WN_SIZE_HEIGHT_MASK (0xFFFF0000UL) -#define CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT (16U) -#define CAM_IDEAL_WN_SIZE_HEIGHT_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) -#define CAM_IDEAL_WN_SIZE_HEIGHT_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_HEIGHT_MASK) >> CAM_IDEAL_WN_SIZE_HEIGHT_SHIFT) - -/* - * WIDTH (RW) - * - * Image Width. Indicates how many active pixels in a line of the image from the sensor. - * The number of bytes to be transferred is re-calculated automatically in hardware based on cr1[color_ext] and cr1[store_mode]. Default value is 2*pixel number. - * As the input data from the sensor is 8-bit/pixel format, the IMAGE_WIDTH should be a multiple of 8 pixels. - */ -#define CAM_IDEAL_WN_SIZE_WIDTH_MASK (0xFFFFU) -#define CAM_IDEAL_WN_SIZE_WIDTH_SHIFT (0U) -#define CAM_IDEAL_WN_SIZE_WIDTH_SET(x) (((uint32_t)(x) << CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) -#define CAM_IDEAL_WN_SIZE_WIDTH_GET(x) (((uint32_t)(x) & CAM_IDEAL_WN_SIZE_WIDTH_MASK) >> CAM_IDEAL_WN_SIZE_WIDTH_SHIFT) - -/* Bitfield definition for register: CR18 */ -/* - * CAM_ENABLE (RW) - * - * CAM global enable signal. Only when this bit is 1, CAM can start to receive the data and store to memory. - */ -#define CAM_CR18_CAM_ENABLE_MASK (0x80000000UL) -#define CAM_CR18_CAM_ENABLE_SHIFT (31U) -#define CAM_CR18_CAM_ENABLE_SET(x) (((uint32_t)(x) << CAM_CR18_CAM_ENABLE_SHIFT) & CAM_CR18_CAM_ENABLE_MASK) -#define CAM_CR18_CAM_ENABLE_GET(x) (((uint32_t)(x) & CAM_CR18_CAM_ENABLE_MASK) >> CAM_CR18_CAM_ENABLE_SHIFT) - -/* - * AWQOS (RW) - * - * AWQOS for bus fabric arbitration - */ -#define CAM_CR18_AWQOS_MASK (0x780U) -#define CAM_CR18_AWQOS_SHIFT (7U) -#define CAM_CR18_AWQOS_SET(x) (((uint32_t)(x) << CAM_CR18_AWQOS_SHIFT) & CAM_CR18_AWQOS_MASK) -#define CAM_CR18_AWQOS_GET(x) (((uint32_t)(x) & CAM_CR18_AWQOS_MASK) >> CAM_CR18_AWQOS_SHIFT) - -/* Bitfield definition for register: DMASA_UV1 */ -/* - * PTR (RW) - * - * Two Plane UV Buffer Start Address 1 - */ -#define CAM_DMASA_UV1_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_UV1_PTR_SHIFT (2U) -#define CAM_DMASA_UV1_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV1_PTR_SHIFT) & CAM_DMASA_UV1_PTR_MASK) -#define CAM_DMASA_UV1_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV1_PTR_MASK) >> CAM_DMASA_UV1_PTR_SHIFT) - -/* Bitfield definition for register: DMASA_UV2 */ -/* - * PTR (RW) - * - * Two Plane UV Buffer Start Address 2 - */ -#define CAM_DMASA_UV2_PTR_MASK (0xFFFFFFFCUL) -#define CAM_DMASA_UV2_PTR_SHIFT (2U) -#define CAM_DMASA_UV2_PTR_SET(x) (((uint32_t)(x) << CAM_DMASA_UV2_PTR_SHIFT) & CAM_DMASA_UV2_PTR_MASK) -#define CAM_DMASA_UV2_PTR_GET(x) (((uint32_t)(x) & CAM_DMASA_UV2_PTR_MASK) >> CAM_DMASA_UV2_PTR_SHIFT) - -/* Bitfield definition for register: CR20 */ -/* - * BINARY_EN (RW) - * - * binary picture output enable - */ -#define CAM_CR20_BINARY_EN_MASK (0x80000000UL) -#define CAM_CR20_BINARY_EN_SHIFT (31U) -#define CAM_CR20_BINARY_EN_SET(x) (((uint32_t)(x) << CAM_CR20_BINARY_EN_SHIFT) & CAM_CR20_BINARY_EN_MASK) -#define CAM_CR20_BINARY_EN_GET(x) (((uint32_t)(x) & CAM_CR20_BINARY_EN_MASK) >> CAM_CR20_BINARY_EN_SHIFT) - -/* - * HISTOGRAM_EN (RW) - * - * histogarm enable - */ -#define CAM_CR20_HISTOGRAM_EN_MASK (0x40000000UL) -#define CAM_CR20_HISTOGRAM_EN_SHIFT (30U) -#define CAM_CR20_HISTOGRAM_EN_SET(x) (((uint32_t)(x) << CAM_CR20_HISTOGRAM_EN_SHIFT) & CAM_CR20_HISTOGRAM_EN_MASK) -#define CAM_CR20_HISTOGRAM_EN_GET(x) (((uint32_t)(x) & CAM_CR20_HISTOGRAM_EN_MASK) >> CAM_CR20_HISTOGRAM_EN_SHIFT) - -/* - * BIG_END (RW) - * - * Asserted when binary output is in big-endian type, which mean the right most data is at the LSBs. Take function only inside the 32-bit word. - */ -#define CAM_CR20_BIG_END_MASK (0x100U) -#define CAM_CR20_BIG_END_SHIFT (8U) -#define CAM_CR20_BIG_END_SET(x) (((uint32_t)(x) << CAM_CR20_BIG_END_SHIFT) & CAM_CR20_BIG_END_MASK) -#define CAM_CR20_BIG_END_GET(x) (((uint32_t)(x) & CAM_CR20_BIG_END_MASK) >> CAM_CR20_BIG_END_SHIFT) - -/* - * THRESHOLD (RW) - * - * Threshold to generate binary color. Bin 1 is output if the pixel is greater than the threshold. - */ -#define CAM_CR20_THRESHOLD_MASK (0xFFU) -#define CAM_CR20_THRESHOLD_SHIFT (0U) -#define CAM_CR20_THRESHOLD_SET(x) (((uint32_t)(x) << CAM_CR20_THRESHOLD_SHIFT) & CAM_CR20_THRESHOLD_MASK) -#define CAM_CR20_THRESHOLD_GET(x) (((uint32_t)(x) & CAM_CR20_THRESHOLD_MASK) >> CAM_CR20_THRESHOLD_SHIFT) - -/* Bitfield definition for register: CSC_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * This bit changes the behavior when performing U/V converting. - * 0b - Converting YUV to RGB data - * 1b - Converting YCbCr to RGB data - */ -#define CAM_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define CAM_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -#define CAM_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_YCBCR_MODE_SHIFT) & CAM_CSC_COEF0_YCBCR_MODE_MASK) -#define CAM_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_YCBCR_MODE_MASK) >> CAM_CSC_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Enable the CSC unit - * 0b - The CSC is bypassed and the input pixels are RGB data already - * 1b - The CSC is enabled and the pixels will be converted to RGB data - */ -#define CAM_CSC_COEF0_ENABLE_MASK (0x40000000UL) -#define CAM_CSC_COEF0_ENABLE_SHIFT (30U) -#define CAM_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_ENABLE_SHIFT) & CAM_CSC_COEF0_ENABLE_MASK) -#define CAM_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_ENABLE_MASK) >> CAM_CSC_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define CAM_CSC_COEF0_C0_MASK (0x1FFC0000UL) -#define CAM_CSC_COEF0_C0_SHIFT (18U) -#define CAM_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_C0_SHIFT) & CAM_CSC_COEF0_C0_MASK) -#define CAM_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_C0_MASK) >> CAM_CSC_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define CAM_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define CAM_CSC_COEF0_UV_OFFSET_SHIFT (9U) -#define CAM_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_UV_OFFSET_SHIFT) & CAM_CSC_COEF0_UV_OFFSET_MASK) -#define CAM_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_UV_OFFSET_MASK) >> CAM_CSC_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define CAM_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) -#define CAM_CSC_COEF0_Y_OFFSET_SHIFT (0U) -#define CAM_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << CAM_CSC_COEF0_Y_OFFSET_SHIFT) & CAM_CSC_COEF0_Y_OFFSET_MASK) -#define CAM_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & CAM_CSC_COEF0_Y_OFFSET_MASK) >> CAM_CSC_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: CSC_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define CAM_CSC_COEF1_C1_MASK (0x7FF0000UL) -#define CAM_CSC_COEF1_C1_SHIFT (16U) -#define CAM_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C1_SHIFT) & CAM_CSC_COEF1_C1_MASK) -#define CAM_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C1_MASK) >> CAM_CSC_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define CAM_CSC_COEF1_C4_MASK (0x7FFU) -#define CAM_CSC_COEF1_C4_SHIFT (0U) -#define CAM_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << CAM_CSC_COEF1_C4_SHIFT) & CAM_CSC_COEF1_C4_MASK) -#define CAM_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & CAM_CSC_COEF1_C4_MASK) >> CAM_CSC_COEF1_C4_SHIFT) - -/* Bitfield definition for register: CSC_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define CAM_CSC_COEF2_C2_MASK (0x7FF0000UL) -#define CAM_CSC_COEF2_C2_SHIFT (16U) -#define CAM_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C2_SHIFT) & CAM_CSC_COEF2_C2_MASK) -#define CAM_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C2_MASK) >> CAM_CSC_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define CAM_CSC_COEF2_C3_MASK (0x7FFU) -#define CAM_CSC_COEF2_C3_SHIFT (0U) -#define CAM_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << CAM_CSC_COEF2_C3_SHIFT) & CAM_CSC_COEF2_C3_MASK) -#define CAM_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & CAM_CSC_COEF2_C3_MASK) >> CAM_CSC_COEF2_C3_SHIFT) - -/* Bitfield definition for register: CLRKEY_LOW */ -/* - * LIMIT (RW) - * - * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - */ -#define CAM_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) -#define CAM_CLRKEY_LOW_LIMIT_SHIFT (0U) -#define CAM_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_LOW_LIMIT_SHIFT) & CAM_CLRKEY_LOW_LIMIT_MASK) -#define CAM_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_LOW_LIMIT_MASK) >> CAM_CLRKEY_LOW_LIMIT_SHIFT) - -/* Bitfield definition for register: CLRKEY_HIGH */ -/* - * LIMIT (RW) - * - * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - */ -#define CAM_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) -#define CAM_CLRKEY_HIGH_LIMIT_SHIFT (0U) -#define CAM_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << CAM_CLRKEY_HIGH_LIMIT_SHIFT) & CAM_CLRKEY_HIGH_LIMIT_MASK) -#define CAM_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & CAM_CLRKEY_HIGH_LIMIT_MASK) >> CAM_CLRKEY_HIGH_LIMIT_SHIFT) - -/* Bitfield definition for register array: HISTOGRAM_FIFO */ -/* - * HIST_Y (RO) - * - * the appearance of bin x (x=(address-DATA0)/4) - */ -#define CAM_HISTOGRAM_FIFO_HIST_Y_MASK (0xFFFFFFUL) -#define CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT (0U) -#define CAM_HISTOGRAM_FIFO_HIST_Y_GET(x) (((uint32_t)(x) & CAM_HISTOGRAM_FIFO_HIST_Y_MASK) >> CAM_HISTOGRAM_FIFO_HIST_Y_SHIFT) - -/* Bitfield definition for register: ROI_WIDTH */ -/* - * ROI_WIDTH_END (RW) - * - * end address of width for roi - */ -#define CAM_ROI_WIDTH_ROI_WIDTH_END_MASK (0xFFFF0000UL) -#define CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT (16U) -#define CAM_ROI_WIDTH_ROI_WIDTH_END_SET(x) (((uint32_t)(x) << CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT) & CAM_ROI_WIDTH_ROI_WIDTH_END_MASK) -#define CAM_ROI_WIDTH_ROI_WIDTH_END_GET(x) (((uint32_t)(x) & CAM_ROI_WIDTH_ROI_WIDTH_END_MASK) >> CAM_ROI_WIDTH_ROI_WIDTH_END_SHIFT) - -/* - * ROI_WIDTH_START (RW) - * - * start address of width for roi - */ -#define CAM_ROI_WIDTH_ROI_WIDTH_START_MASK (0xFFFFU) -#define CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT (0U) -#define CAM_ROI_WIDTH_ROI_WIDTH_START_SET(x) (((uint32_t)(x) << CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT) & CAM_ROI_WIDTH_ROI_WIDTH_START_MASK) -#define CAM_ROI_WIDTH_ROI_WIDTH_START_GET(x) (((uint32_t)(x) & CAM_ROI_WIDTH_ROI_WIDTH_START_MASK) >> CAM_ROI_WIDTH_ROI_WIDTH_START_SHIFT) - -/* Bitfield definition for register: ROI_HEIGHT */ -/* - * ROI_HEIGHT_END (RW) - * - * end address of height for roi - */ -#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK (0xFFFF0000UL) -#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT (16U) -#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_SET(x) (((uint32_t)(x) << CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT) & CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK) -#define CAM_ROI_HEIGHT_ROI_HEIGHT_END_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_END_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_END_SHIFT) - -/* - * ROI_HEIGHT_START (RW) - * - * start address of height for roi - */ -#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK (0xFFFFU) -#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT (0U) -#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_SET(x) (((uint32_t)(x) << CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) -#define CAM_ROI_HEIGHT_ROI_HEIGHT_START_GET(x) (((uint32_t)(x) & CAM_ROI_HEIGHT_ROI_HEIGHT_START_MASK) >> CAM_ROI_HEIGHT_ROI_HEIGHT_START_SHIFT) - -/* Bitfield definition for register: PRO_CTRL */ -/* - * ERR_INJECT (RW) - * - * 0 generate alarm in normal mode - * 1 force to generate fatal alarm - */ -#define CAM_PRO_CTRL_ERR_INJECT_MASK (0x4000U) -#define CAM_PRO_CTRL_ERR_INJECT_SHIFT (14U) -#define CAM_PRO_CTRL_ERR_INJECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ERR_INJECT_SHIFT) & CAM_PRO_CTRL_ERR_INJECT_MASK) -#define CAM_PRO_CTRL_ERR_INJECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ERR_INJECT_MASK) >> CAM_PRO_CTRL_ERR_INJECT_SHIFT) - -/* - * ROI_UPDATE (RW) - * - * roi configration update - */ -#define CAM_PRO_CTRL_ROI_UPDATE_MASK (0x80U) -#define CAM_PRO_CTRL_ROI_UPDATE_SHIFT (7U) -#define CAM_PRO_CTRL_ROI_UPDATE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_ROI_UPDATE_SHIFT) & CAM_PRO_CTRL_ROI_UPDATE_MASK) -#define CAM_PRO_CTRL_ROI_UPDATE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_ROI_UPDATE_MASK) >> CAM_PRO_CTRL_ROI_UPDATE_SHIFT) - -/* - * SCALE_UPDATE (RW) - * - * scale configration update - */ -#define CAM_PRO_CTRL_SCALE_UPDATE_MASK (0x40U) -#define CAM_PRO_CTRL_SCALE_UPDATE_SHIFT (6U) -#define CAM_PRO_CTRL_SCALE_UPDATE_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_UPDATE_SHIFT) & CAM_PRO_CTRL_SCALE_UPDATE_MASK) -#define CAM_PRO_CTRL_SCALE_UPDATE_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_UPDATE_MASK) >> CAM_PRO_CTRL_SCALE_UPDATE_SHIFT) - -/* - * SCALE_HEIGHT_SELECT (RW) - * - * 000 keep all pixel for height - * 001 keep 1 for every 2 pixel for height - * 010 keep 1 for every 3 pixel for height - * 011 keep 1 for every 4 pixel for height - * 100 keep 1 for every 5 pixel for height - * 101 keep 1 for every 6 pixel for height - * 110 keep 1 for every 7 pixel for height - * 111 keep 1 for every 8 pixel for height - */ -#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK (0x38U) -#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT (3U) -#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT) & CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK) -#define CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_MASK) >> CAM_PRO_CTRL_SCALE_HEIGHT_SELECT_SHIFT) - -/* - * SCALE_WIDTH_SELECT (RW) - * - * 000 keep all pixel for width - * 001 keep 1 for every 2 pixel for width - * 010 keep 1 for every 3 pixel for width - * 011 keep 1 for every 4 pixel for width - * 100 keep 1 for every 5 pixel for width - * 101 keep 1 for every 6 pixel for width - * 110 keep 1 for every 7 pixel for width - * 111 keep 1 for every 8 pixel for width - */ -#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK (0x7U) -#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT (0U) -#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SET(x) (((uint32_t)(x) << CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT) & CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK) -#define CAM_PRO_CTRL_SCALE_WIDTH_SELECT_GET(x) (((uint32_t)(x) & CAM_PRO_CTRL_SCALE_WIDTH_SELECT_MASK) >> CAM_PRO_CTRL_SCALE_WIDTH_SELECT_SHIFT) - -/* Bitfield definition for register: ACT_SIZE */ -/* - * ACT_HEIGHT (RW) - * - * actual height after scale and/or roi - */ -#define CAM_ACT_SIZE_ACT_HEIGHT_MASK (0xFFFF0000UL) -#define CAM_ACT_SIZE_ACT_HEIGHT_SHIFT (16U) -#define CAM_ACT_SIZE_ACT_HEIGHT_SET(x) (((uint32_t)(x) << CAM_ACT_SIZE_ACT_HEIGHT_SHIFT) & CAM_ACT_SIZE_ACT_HEIGHT_MASK) -#define CAM_ACT_SIZE_ACT_HEIGHT_GET(x) (((uint32_t)(x) & CAM_ACT_SIZE_ACT_HEIGHT_MASK) >> CAM_ACT_SIZE_ACT_HEIGHT_SHIFT) - -/* - * ACT_WIDTH (RW) - * - * actual width after scale and/or roi - */ -#define CAM_ACT_SIZE_ACT_WIDTH_MASK (0xFFFFU) -#define CAM_ACT_SIZE_ACT_WIDTH_SHIFT (0U) -#define CAM_ACT_SIZE_ACT_WIDTH_SET(x) (((uint32_t)(x) << CAM_ACT_SIZE_ACT_WIDTH_SHIFT) & CAM_ACT_SIZE_ACT_WIDTH_MASK) -#define CAM_ACT_SIZE_ACT_WIDTH_GET(x) (((uint32_t)(x) & CAM_ACT_SIZE_ACT_WIDTH_MASK) >> CAM_ACT_SIZE_ACT_WIDTH_SHIFT) - -/* Bitfield definition for register: VSYNC_VALID_CNT */ -/* - * VSYNC_VALID_CNT (RW) - * - * vsync valid counter - */ -#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK (0xFFFFFFFFUL) -#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT (0U) -#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SET(x) (((uint32_t)(x) << CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT) & CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK) -#define CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_GET(x) (((uint32_t)(x) & CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_MASK) >> CAM_VSYNC_VALID_CNT_VSYNC_VALID_CNT_SHIFT) - -/* Bitfield definition for register: HSYNC_VALID_CNT */ -/* - * HSYNC_VALID_CNT (RW) - * - * hsync valid counter - */ -#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK (0xFFFFFFFFUL) -#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT (0U) -#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SET(x) (((uint32_t)(x) << CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT) & CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK) -#define CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_GET(x) (((uint32_t)(x) & CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_MASK) >> CAM_HSYNC_VALID_CNT_HSYNC_VALID_CNT_SHIFT) - -/* Bitfield definition for register: VALID_MARGIN */ -/* - * HSYNC_VALID_MARGIN (RW) - * - * hsync valid margin - */ -#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK (0xFFFF0000UL) -#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT (16U) -#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SET(x) (((uint32_t)(x) << CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT) & CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK) -#define CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_GET(x) (((uint32_t)(x) & CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_MASK) >> CAM_VALID_MARGIN_HSYNC_VALID_MARGIN_SHIFT) - -/* - * VSYNC_VALID_MARGIN (RW) - * - * vsync valid margin - */ -#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK (0xFFFFU) -#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT (0U) -#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SET(x) (((uint32_t)(x) << CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT) & CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK) -#define CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_GET(x) (((uint32_t)(x) & CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_MASK) >> CAM_VALID_MARGIN_VSYNC_VALID_MARGIN_SHIFT) - -/* Bitfield definition for register: ALARM_SET */ -/* - * SIG_NORMAL (RW) - * - * define signal duty cycles(base clock) - * 0x0: disable signal - * 0x1: high 1, low 15 - * 0x2: high 2, low 14 - * …... - * 0xF: high 15, low 1 - */ -#define CAM_ALARM_SET_SIG_NORMAL_MASK (0xF00000UL) -#define CAM_ALARM_SET_SIG_NORMAL_SHIFT (20U) -#define CAM_ALARM_SET_SIG_NORMAL_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_SIG_NORMAL_SHIFT) & CAM_ALARM_SET_SIG_NORMAL_MASK) -#define CAM_ALARM_SET_SIG_NORMAL_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_SIG_NORMAL_MASK) >> CAM_ALARM_SET_SIG_NORMAL_SHIFT) - -/* - * FATAL_NORMAL (RW) - * - * define signal duty cycles(base clock) - * 0x0: disable signal - * 0x1: high 1, low 15 - * 0x2: high 2, low 14 - * …... - * 0xF: high 15, low 1 - */ -#define CAM_ALARM_SET_FATAL_NORMAL_MASK (0xF0000UL) -#define CAM_ALARM_SET_FATAL_NORMAL_SHIFT (16U) -#define CAM_ALARM_SET_FATAL_NORMAL_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_FATAL_NORMAL_SHIFT) & CAM_ALARM_SET_FATAL_NORMAL_MASK) -#define CAM_ALARM_SET_FATAL_NORMAL_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_FATAL_NORMAL_MASK) >> CAM_ALARM_SET_FATAL_NORMAL_SHIFT) - -/* - * PRE_DIV (RW) - * - * frequency division - */ -#define CAM_ALARM_SET_PRE_DIV_MASK (0xFFFFU) -#define CAM_ALARM_SET_PRE_DIV_SHIFT (0U) -#define CAM_ALARM_SET_PRE_DIV_SET(x) (((uint32_t)(x) << CAM_ALARM_SET_PRE_DIV_SHIFT) & CAM_ALARM_SET_PRE_DIV_MASK) -#define CAM_ALARM_SET_PRE_DIV_GET(x) (((uint32_t)(x) & CAM_ALARM_SET_PRE_DIV_MASK) >> CAM_ALARM_SET_PRE_DIV_SHIFT) - - - -/* HISTOGRAM_FIFO register group index macro definition */ -#define CAM_HISTOGRAM_FIFO_DATA0 (0UL) -#define CAM_HISTOGRAM_FIFO_DATA1 (1UL) -#define CAM_HISTOGRAM_FIFO_DATA2 (2UL) -#define CAM_HISTOGRAM_FIFO_DATA3 (3UL) -#define CAM_HISTOGRAM_FIFO_DATA4 (4UL) -#define CAM_HISTOGRAM_FIFO_DATA5 (5UL) -#define CAM_HISTOGRAM_FIFO_DATA6 (6UL) -#define CAM_HISTOGRAM_FIFO_DATA7 (7UL) -#define CAM_HISTOGRAM_FIFO_DATA8 (8UL) -#define CAM_HISTOGRAM_FIFO_DATA9 (9UL) -#define CAM_HISTOGRAM_FIFO_DATA10 (10UL) -#define CAM_HISTOGRAM_FIFO_DATA11 (11UL) -#define CAM_HISTOGRAM_FIFO_DATA12 (12UL) -#define CAM_HISTOGRAM_FIFO_DATA13 (13UL) -#define CAM_HISTOGRAM_FIFO_DATA14 (14UL) -#define CAM_HISTOGRAM_FIFO_DATA15 (15UL) -#define CAM_HISTOGRAM_FIFO_DATA16 (16UL) -#define CAM_HISTOGRAM_FIFO_DATA17 (17UL) -#define CAM_HISTOGRAM_FIFO_DATA18 (18UL) -#define CAM_HISTOGRAM_FIFO_DATA19 (19UL) -#define CAM_HISTOGRAM_FIFO_DATA20 (20UL) -#define CAM_HISTOGRAM_FIFO_DATA21 (21UL) -#define CAM_HISTOGRAM_FIFO_DATA22 (22UL) -#define CAM_HISTOGRAM_FIFO_DATA23 (23UL) -#define CAM_HISTOGRAM_FIFO_DATA24 (24UL) -#define CAM_HISTOGRAM_FIFO_DATA25 (25UL) -#define CAM_HISTOGRAM_FIFO_DATA26 (26UL) -#define CAM_HISTOGRAM_FIFO_DATA27 (27UL) -#define CAM_HISTOGRAM_FIFO_DATA28 (28UL) -#define CAM_HISTOGRAM_FIFO_DATA29 (29UL) -#define CAM_HISTOGRAM_FIFO_DATA30 (30UL) -#define CAM_HISTOGRAM_FIFO_DATA31 (31UL) -#define CAM_HISTOGRAM_FIFO_DATA32 (32UL) -#define CAM_HISTOGRAM_FIFO_DATA33 (33UL) -#define CAM_HISTOGRAM_FIFO_DATA34 (34UL) -#define CAM_HISTOGRAM_FIFO_DATA35 (35UL) -#define CAM_HISTOGRAM_FIFO_DATA36 (36UL) -#define CAM_HISTOGRAM_FIFO_DATA37 (37UL) -#define CAM_HISTOGRAM_FIFO_DATA38 (38UL) -#define CAM_HISTOGRAM_FIFO_DATA39 (39UL) -#define CAM_HISTOGRAM_FIFO_DATA40 (40UL) -#define CAM_HISTOGRAM_FIFO_DATA41 (41UL) -#define CAM_HISTOGRAM_FIFO_DATA42 (42UL) -#define CAM_HISTOGRAM_FIFO_DATA43 (43UL) -#define CAM_HISTOGRAM_FIFO_DATA44 (44UL) -#define CAM_HISTOGRAM_FIFO_DATA45 (45UL) -#define CAM_HISTOGRAM_FIFO_DATA46 (46UL) -#define CAM_HISTOGRAM_FIFO_DATA47 (47UL) -#define CAM_HISTOGRAM_FIFO_DATA48 (48UL) -#define CAM_HISTOGRAM_FIFO_DATA49 (49UL) -#define CAM_HISTOGRAM_FIFO_DATA50 (50UL) -#define CAM_HISTOGRAM_FIFO_DATA51 (51UL) -#define CAM_HISTOGRAM_FIFO_DATA52 (52UL) -#define CAM_HISTOGRAM_FIFO_DATA53 (53UL) -#define CAM_HISTOGRAM_FIFO_DATA54 (54UL) -#define CAM_HISTOGRAM_FIFO_DATA55 (55UL) -#define CAM_HISTOGRAM_FIFO_DATA56 (56UL) -#define CAM_HISTOGRAM_FIFO_DATA57 (57UL) -#define CAM_HISTOGRAM_FIFO_DATA58 (58UL) -#define CAM_HISTOGRAM_FIFO_DATA59 (59UL) -#define CAM_HISTOGRAM_FIFO_DATA60 (60UL) -#define CAM_HISTOGRAM_FIFO_DATA61 (61UL) -#define CAM_HISTOGRAM_FIFO_DATA62 (62UL) -#define CAM_HISTOGRAM_FIFO_DATA63 (63UL) -#define CAM_HISTOGRAM_FIFO_DATA64 (64UL) -#define CAM_HISTOGRAM_FIFO_DATA65 (65UL) -#define CAM_HISTOGRAM_FIFO_DATA66 (66UL) -#define CAM_HISTOGRAM_FIFO_DATA67 (67UL) -#define CAM_HISTOGRAM_FIFO_DATA68 (68UL) -#define CAM_HISTOGRAM_FIFO_DATA69 (69UL) -#define CAM_HISTOGRAM_FIFO_DATA70 (70UL) -#define CAM_HISTOGRAM_FIFO_DATA71 (71UL) -#define CAM_HISTOGRAM_FIFO_DATA72 (72UL) -#define CAM_HISTOGRAM_FIFO_DATA73 (73UL) -#define CAM_HISTOGRAM_FIFO_DATA74 (74UL) -#define CAM_HISTOGRAM_FIFO_DATA75 (75UL) -#define CAM_HISTOGRAM_FIFO_DATA76 (76UL) -#define CAM_HISTOGRAM_FIFO_DATA77 (77UL) -#define CAM_HISTOGRAM_FIFO_DATA78 (78UL) -#define CAM_HISTOGRAM_FIFO_DATA79 (79UL) -#define CAM_HISTOGRAM_FIFO_DATA80 (80UL) -#define CAM_HISTOGRAM_FIFO_DATA81 (81UL) -#define CAM_HISTOGRAM_FIFO_DATA82 (82UL) -#define CAM_HISTOGRAM_FIFO_DATA83 (83UL) -#define CAM_HISTOGRAM_FIFO_DATA84 (84UL) -#define CAM_HISTOGRAM_FIFO_DATA85 (85UL) -#define CAM_HISTOGRAM_FIFO_DATA86 (86UL) -#define CAM_HISTOGRAM_FIFO_DATA87 (87UL) -#define CAM_HISTOGRAM_FIFO_DATA88 (88UL) -#define CAM_HISTOGRAM_FIFO_DATA89 (89UL) -#define CAM_HISTOGRAM_FIFO_DATA90 (90UL) -#define CAM_HISTOGRAM_FIFO_DATA91 (91UL) -#define CAM_HISTOGRAM_FIFO_DATA92 (92UL) -#define CAM_HISTOGRAM_FIFO_DATA93 (93UL) -#define CAM_HISTOGRAM_FIFO_DATA94 (94UL) -#define CAM_HISTOGRAM_FIFO_DATA95 (95UL) -#define CAM_HISTOGRAM_FIFO_DATA96 (96UL) -#define CAM_HISTOGRAM_FIFO_DATA97 (97UL) -#define CAM_HISTOGRAM_FIFO_DATA98 (98UL) -#define CAM_HISTOGRAM_FIFO_DATA99 (99UL) -#define CAM_HISTOGRAM_FIFO_DATA100 (100UL) -#define CAM_HISTOGRAM_FIFO_DATA101 (101UL) -#define CAM_HISTOGRAM_FIFO_DATA102 (102UL) -#define CAM_HISTOGRAM_FIFO_DATA103 (103UL) -#define CAM_HISTOGRAM_FIFO_DATA104 (104UL) -#define CAM_HISTOGRAM_FIFO_DATA105 (105UL) -#define CAM_HISTOGRAM_FIFO_DATA106 (106UL) -#define CAM_HISTOGRAM_FIFO_DATA107 (107UL) -#define CAM_HISTOGRAM_FIFO_DATA108 (108UL) -#define CAM_HISTOGRAM_FIFO_DATA109 (109UL) -#define CAM_HISTOGRAM_FIFO_DATA110 (110UL) -#define CAM_HISTOGRAM_FIFO_DATA111 (111UL) -#define CAM_HISTOGRAM_FIFO_DATA112 (112UL) -#define CAM_HISTOGRAM_FIFO_DATA113 (113UL) -#define CAM_HISTOGRAM_FIFO_DATA114 (114UL) -#define CAM_HISTOGRAM_FIFO_DATA115 (115UL) -#define CAM_HISTOGRAM_FIFO_DATA116 (116UL) -#define CAM_HISTOGRAM_FIFO_DATA117 (117UL) -#define CAM_HISTOGRAM_FIFO_DATA118 (118UL) -#define CAM_HISTOGRAM_FIFO_DATA119 (119UL) -#define CAM_HISTOGRAM_FIFO_DATA120 (120UL) -#define CAM_HISTOGRAM_FIFO_DATA121 (121UL) -#define CAM_HISTOGRAM_FIFO_DATA122 (122UL) -#define CAM_HISTOGRAM_FIFO_DATA123 (123UL) -#define CAM_HISTOGRAM_FIFO_DATA124 (124UL) -#define CAM_HISTOGRAM_FIFO_DATA125 (125UL) -#define CAM_HISTOGRAM_FIFO_DATA126 (126UL) -#define CAM_HISTOGRAM_FIFO_DATA127 (127UL) -#define CAM_HISTOGRAM_FIFO_DATA128 (128UL) -#define CAM_HISTOGRAM_FIFO_DATA129 (129UL) -#define CAM_HISTOGRAM_FIFO_DATA130 (130UL) -#define CAM_HISTOGRAM_FIFO_DATA131 (131UL) -#define CAM_HISTOGRAM_FIFO_DATA132 (132UL) -#define CAM_HISTOGRAM_FIFO_DATA133 (133UL) -#define CAM_HISTOGRAM_FIFO_DATA134 (134UL) -#define CAM_HISTOGRAM_FIFO_DATA135 (135UL) -#define CAM_HISTOGRAM_FIFO_DATA136 (136UL) -#define CAM_HISTOGRAM_FIFO_DATA137 (137UL) -#define CAM_HISTOGRAM_FIFO_DATA138 (138UL) -#define CAM_HISTOGRAM_FIFO_DATA139 (139UL) -#define CAM_HISTOGRAM_FIFO_DATA140 (140UL) -#define CAM_HISTOGRAM_FIFO_DATA141 (141UL) -#define CAM_HISTOGRAM_FIFO_DATA142 (142UL) -#define CAM_HISTOGRAM_FIFO_DATA143 (143UL) -#define CAM_HISTOGRAM_FIFO_DATA144 (144UL) -#define CAM_HISTOGRAM_FIFO_DATA145 (145UL) -#define CAM_HISTOGRAM_FIFO_DATA146 (146UL) -#define CAM_HISTOGRAM_FIFO_DATA147 (147UL) -#define CAM_HISTOGRAM_FIFO_DATA148 (148UL) -#define CAM_HISTOGRAM_FIFO_DATA149 (149UL) -#define CAM_HISTOGRAM_FIFO_DATA150 (150UL) -#define CAM_HISTOGRAM_FIFO_DATA151 (151UL) -#define CAM_HISTOGRAM_FIFO_DATA152 (152UL) -#define CAM_HISTOGRAM_FIFO_DATA153 (153UL) -#define CAM_HISTOGRAM_FIFO_DATA154 (154UL) -#define CAM_HISTOGRAM_FIFO_DATA155 (155UL) -#define CAM_HISTOGRAM_FIFO_DATA156 (156UL) -#define CAM_HISTOGRAM_FIFO_DATA157 (157UL) -#define CAM_HISTOGRAM_FIFO_DATA158 (158UL) -#define CAM_HISTOGRAM_FIFO_DATA159 (159UL) -#define CAM_HISTOGRAM_FIFO_DATA160 (160UL) -#define CAM_HISTOGRAM_FIFO_DATA161 (161UL) -#define CAM_HISTOGRAM_FIFO_DATA162 (162UL) -#define CAM_HISTOGRAM_FIFO_DATA163 (163UL) -#define CAM_HISTOGRAM_FIFO_DATA164 (164UL) -#define CAM_HISTOGRAM_FIFO_DATA165 (165UL) -#define CAM_HISTOGRAM_FIFO_DATA166 (166UL) -#define CAM_HISTOGRAM_FIFO_DATA167 (167UL) -#define CAM_HISTOGRAM_FIFO_DATA168 (168UL) -#define CAM_HISTOGRAM_FIFO_DATA169 (169UL) -#define CAM_HISTOGRAM_FIFO_DATA170 (170UL) -#define CAM_HISTOGRAM_FIFO_DATA171 (171UL) -#define CAM_HISTOGRAM_FIFO_DATA172 (172UL) -#define CAM_HISTOGRAM_FIFO_DATA173 (173UL) -#define CAM_HISTOGRAM_FIFO_DATA174 (174UL) -#define CAM_HISTOGRAM_FIFO_DATA175 (175UL) -#define CAM_HISTOGRAM_FIFO_DATA176 (176UL) -#define CAM_HISTOGRAM_FIFO_DATA177 (177UL) -#define CAM_HISTOGRAM_FIFO_DATA178 (178UL) -#define CAM_HISTOGRAM_FIFO_DATA179 (179UL) -#define CAM_HISTOGRAM_FIFO_DATA180 (180UL) -#define CAM_HISTOGRAM_FIFO_DATA181 (181UL) -#define CAM_HISTOGRAM_FIFO_DATA182 (182UL) -#define CAM_HISTOGRAM_FIFO_DATA183 (183UL) -#define CAM_HISTOGRAM_FIFO_DATA184 (184UL) -#define CAM_HISTOGRAM_FIFO_DATA185 (185UL) -#define CAM_HISTOGRAM_FIFO_DATA186 (186UL) -#define CAM_HISTOGRAM_FIFO_DATA187 (187UL) -#define CAM_HISTOGRAM_FIFO_DATA188 (188UL) -#define CAM_HISTOGRAM_FIFO_DATA189 (189UL) -#define CAM_HISTOGRAM_FIFO_DATA190 (190UL) -#define CAM_HISTOGRAM_FIFO_DATA191 (191UL) -#define CAM_HISTOGRAM_FIFO_DATA192 (192UL) -#define CAM_HISTOGRAM_FIFO_DATA193 (193UL) -#define CAM_HISTOGRAM_FIFO_DATA194 (194UL) -#define CAM_HISTOGRAM_FIFO_DATA195 (195UL) -#define CAM_HISTOGRAM_FIFO_DATA196 (196UL) -#define CAM_HISTOGRAM_FIFO_DATA197 (197UL) -#define CAM_HISTOGRAM_FIFO_DATA198 (198UL) -#define CAM_HISTOGRAM_FIFO_DATA199 (199UL) -#define CAM_HISTOGRAM_FIFO_DATA200 (200UL) -#define CAM_HISTOGRAM_FIFO_DATA201 (201UL) -#define CAM_HISTOGRAM_FIFO_DATA202 (202UL) -#define CAM_HISTOGRAM_FIFO_DATA203 (203UL) -#define CAM_HISTOGRAM_FIFO_DATA204 (204UL) -#define CAM_HISTOGRAM_FIFO_DATA205 (205UL) -#define CAM_HISTOGRAM_FIFO_DATA206 (206UL) -#define CAM_HISTOGRAM_FIFO_DATA207 (207UL) -#define CAM_HISTOGRAM_FIFO_DATA208 (208UL) -#define CAM_HISTOGRAM_FIFO_DATA209 (209UL) -#define CAM_HISTOGRAM_FIFO_DATA210 (210UL) -#define CAM_HISTOGRAM_FIFO_DATA211 (211UL) -#define CAM_HISTOGRAM_FIFO_DATA212 (212UL) -#define CAM_HISTOGRAM_FIFO_DATA213 (213UL) -#define CAM_HISTOGRAM_FIFO_DATA214 (214UL) -#define CAM_HISTOGRAM_FIFO_DATA215 (215UL) -#define CAM_HISTOGRAM_FIFO_DATA216 (216UL) -#define CAM_HISTOGRAM_FIFO_DATA217 (217UL) -#define CAM_HISTOGRAM_FIFO_DATA218 (218UL) -#define CAM_HISTOGRAM_FIFO_DATA219 (219UL) -#define CAM_HISTOGRAM_FIFO_DATA220 (220UL) -#define CAM_HISTOGRAM_FIFO_DATA221 (221UL) -#define CAM_HISTOGRAM_FIFO_DATA222 (222UL) -#define CAM_HISTOGRAM_FIFO_DATA223 (223UL) -#define CAM_HISTOGRAM_FIFO_DATA224 (224UL) -#define CAM_HISTOGRAM_FIFO_DATA225 (225UL) -#define CAM_HISTOGRAM_FIFO_DATA226 (226UL) -#define CAM_HISTOGRAM_FIFO_DATA227 (227UL) -#define CAM_HISTOGRAM_FIFO_DATA228 (228UL) -#define CAM_HISTOGRAM_FIFO_DATA229 (229UL) -#define CAM_HISTOGRAM_FIFO_DATA230 (230UL) -#define CAM_HISTOGRAM_FIFO_DATA231 (231UL) -#define CAM_HISTOGRAM_FIFO_DATA232 (232UL) -#define CAM_HISTOGRAM_FIFO_DATA233 (233UL) -#define CAM_HISTOGRAM_FIFO_DATA234 (234UL) -#define CAM_HISTOGRAM_FIFO_DATA235 (235UL) -#define CAM_HISTOGRAM_FIFO_DATA236 (236UL) -#define CAM_HISTOGRAM_FIFO_DATA237 (237UL) -#define CAM_HISTOGRAM_FIFO_DATA238 (238UL) -#define CAM_HISTOGRAM_FIFO_DATA239 (239UL) -#define CAM_HISTOGRAM_FIFO_DATA240 (240UL) -#define CAM_HISTOGRAM_FIFO_DATA241 (241UL) -#define CAM_HISTOGRAM_FIFO_DATA242 (242UL) -#define CAM_HISTOGRAM_FIFO_DATA243 (243UL) -#define CAM_HISTOGRAM_FIFO_DATA244 (244UL) -#define CAM_HISTOGRAM_FIFO_DATA245 (245UL) -#define CAM_HISTOGRAM_FIFO_DATA246 (246UL) -#define CAM_HISTOGRAM_FIFO_DATA247 (247UL) -#define CAM_HISTOGRAM_FIFO_DATA248 (248UL) -#define CAM_HISTOGRAM_FIFO_DATA249 (249UL) -#define CAM_HISTOGRAM_FIFO_DATA250 (250UL) -#define CAM_HISTOGRAM_FIFO_DATA251 (251UL) -#define CAM_HISTOGRAM_FIFO_DATA252 (252UL) -#define CAM_HISTOGRAM_FIFO_DATA253 (253UL) -#define CAM_HISTOGRAM_FIFO_DATA254 (254UL) -#define CAM_HISTOGRAM_FIFO_DATA255 (255UL) - - -#endif /* HPM_CAM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_crc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_crc_regs.h deleted file mode 100644 index 7c06d3e0e4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_crc_regs.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CRC_H -#define HPM_CRC_H - -typedef struct { - struct { - __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ - __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ - __RW uint32_t POLY; /* 0x8: chn poly */ - __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ - __RW uint32_t XOROUT; /* 0x10: chn xorout */ - __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ - __RW uint32_t DATA; /* 0x18: chn data */ - __RW uint32_t RESULT; /* 0x1C: chn result */ - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - } CHN[8]; -} CRC_Type; - - -/* Bitfield definition for register of struct array CHN: PRE_SET */ -/* - * PRE_SET (RW) - * - * 0: no pre set - * 1: CRC32 - * 2: CRC32-AUTOSAR - * 3: CRC16-CCITT - * 4: CRC16-XMODEM - * 5: CRC16-MODBUS - * 1: CRC32 - * 2: CRC32-autosar - * 3: CRC16-ccitt - * 4: CRC16-xmodem - * 5: CRC16-modbus - * 6: crc16_dnp - * 7: crc16_x25 - * 8: crc16_usb - * 9: crc16_maxim - * 10: crc16_ibm - * 11: crc8_maxim - * 12: crc8_rohc - * 13: crc8_itu - * 14: crc8 - * 15: crc5_usb - */ -#define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) -#define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) -#define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) -#define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) - -/* Bitfield definition for register of struct array CHN: CLR */ -/* - * CLR (RW) - * - * write 1 to clr crc setting and result for its channel. - * always read 0. - */ -#define CRC_CHN_CLR_CLR_MASK (0x1U) -#define CRC_CHN_CLR_CLR_SHIFT (0U) -#define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) -#define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) - -/* Bitfield definition for register of struct array CHN: POLY */ -/* - * POLY (RW) - * - * poly setting - */ -#define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) -#define CRC_CHN_POLY_POLY_SHIFT (0U) -#define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) -#define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array CHN: INIT_DATA */ -/* - * INIT_DATA (RW) - * - * initial data of CRC - */ -#define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) -#define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) -#define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: XOROUT */ -/* - * XOROUT (RW) - * - * XOR for CRC result - */ -#define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) -#define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) -#define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) - -/* Bitfield definition for register of struct array CHN: MISC_SETTING */ -/* - * BYTE_REV (RW) - * - * 0: no wrap input byte order - * 1: wrap input byte order - */ -#define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) -#define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) - -/* - * REV_OUT (RW) - * - * 0: no wrap output bit order - * 1: wrap output bit order - */ -#define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) -#define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) -#define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) -#define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) - -/* - * REV_IN (RW) - * - * 0: no wrap input bit order - * 1: wrap input bit order - */ -#define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) -#define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) -#define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) -#define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) - -/* - * POLY_WIDTH (RW) - * - * crc data length - */ -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) - -/* Bitfield definition for register of struct array CHN: DATA */ -/* - * DATA (RW) - * - * data for crc - */ -#define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_DATA_DATA_SHIFT (0U) -#define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) -#define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: RESULT */ -/* - * RESULT (RW) - * - * crc result - */ -#define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_RESULT_RESULT_SHIFT (0U) -#define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) -#define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) - - - -/* CHN register group index macro definition */ -#define CRC_CHN_0 (0UL) -#define CRC_CHN_1 (1UL) -#define CRC_CHN_2 (2UL) -#define CRC_CHN_3 (3UL) -#define CRC_CHN_4 (4UL) -#define CRC_CHN_5 (5UL) -#define CRC_CHN_6 (6UL) -#define CRC_CHN_7 (7UL) - - -#endif /* HPM_CRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dao_regs.h deleted file mode 100644 index a0bdf2f15d1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dao_regs.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAO_H -#define HPM_DAO_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t CMD; /* 0x8: Command Register */ - __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ - __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ - __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ -} DAO_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * HPF_EN (RW) - * - * Whether HPF is enabled. This HPF is used to filter out the DC part. - */ -#define DAO_CTRL_HPF_EN_MASK (0x20000UL) -#define DAO_CTRL_HPF_EN_SHIFT (17U) -#define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) -#define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) - -/* - * MONO (RW) - * - * Asserted to let the left and right channel output the same value. - */ -#define DAO_CTRL_MONO_MASK (0x80U) -#define DAO_CTRL_MONO_SHIFT (7U) -#define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) -#define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) - -/* - * RIGHT_EN (RW) - * - * Asserted to enable the right channel - */ -#define DAO_CTRL_RIGHT_EN_MASK (0x40U) -#define DAO_CTRL_RIGHT_EN_SHIFT (6U) -#define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) -#define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) - -/* - * LEFT_EN (RW) - * - * Asserted to enable the left channel - */ -#define DAO_CTRL_LEFT_EN_MASK (0x20U) -#define DAO_CTRL_LEFT_EN_SHIFT (5U) -#define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) -#define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) - -/* - * REMAP (RW) - * - * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative - * 0: Don't use remap pwm version - */ -#define DAO_CTRL_REMAP_MASK (0x10U) -#define DAO_CTRL_REMAP_SHIFT (4U) -#define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) -#define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) - -/* - * INVERT (RW) - * - * all the outputs are inverted before sending to pad - */ -#define DAO_CTRL_INVERT_MASK (0x8U) -#define DAO_CTRL_INVERT_SHIFT (3U) -#define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) -#define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) - -/* - * FALSE_LEVEL (RW) - * - * the pad output in False run mode, or when the module is disabled - * 0: all low - * 1: all high - * 2: P-high, N-low - * 3. output is not enabled - */ -#define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) -#define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) -#define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) -#define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) - -/* - * FALSE_RUN (RW) - * - * the module continues to consume data, but all the pads are constant, thus no audio out - */ -#define DAO_CTRL_FALSE_RUN_MASK (0x1U) -#define DAO_CTRL_FALSE_RUN_SHIFT (0U) -#define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) -#define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Self-clear - */ -#define DAO_CMD_SFTRST_MASK (0x2U) -#define DAO_CMD_SFTRST_SHIFT (1U) -#define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) -#define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) - -/* - * RUN (RW) - * - * Enable this module to run. - */ -#define DAO_CMD_RUN_MASK (0x1U) -#define DAO_CMD_RUN_SHIFT (0U) -#define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) -#define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) - -/* Bitfield definition for register: RX_CFGR */ -/* - * FRAME_EDGE (RW) - * - * The start edge of a frame - * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) - * 1: Rising edge indicates a new frame - */ -#define DAO_RX_CFGR_FRAME_EDGE_MASK (0x800U) -#define DAO_RX_CFGR_FRAME_EDGE_SHIFT (11U) -#define DAO_RX_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_FRAME_EDGE_SHIFT) & DAO_RX_CFGR_FRAME_EDGE_MASK) -#define DAO_RX_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_FRAME_EDGE_MASK) >> DAO_RX_CFGR_FRAME_EDGE_SHIFT) - -/* - * CH_MAX (RW) - * - * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 4'h2: 2 channels - * 4'h4: 4 channels - * etc - */ -#define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) -#define DAO_RX_CFGR_CH_MAX_SHIFT (6U) -#define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) -#define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) - -/* - * TDM_EN (RW) - * - * TDM mode - * 0: not TDM mode - * 1: TDM mode - */ -#define DAO_RX_CFGR_TDM_EN_MASK (0x20U) -#define DAO_RX_CFGR_TDM_EN_SHIFT (5U) -#define DAO_RX_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_TDM_EN_SHIFT) & DAO_RX_CFGR_TDM_EN_MASK) -#define DAO_RX_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_TDM_EN_MASK) >> DAO_RX_CFGR_TDM_EN_SHIFT) - -/* - * STD (RW) - * - * I2S standard selection - * 00: I2S Philips standard. - * 01: MSB justified standard (left justified) - * 10: LSB justified standard (right justified) - * 11: PCM standard - * For more details on I2S standards. - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define DAO_RX_CFGR_STD_MASK (0x18U) -#define DAO_RX_CFGR_STD_SHIFT (3U) -#define DAO_RX_CFGR_STD_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_STD_SHIFT) & DAO_RX_CFGR_STD_MASK) -#define DAO_RX_CFGR_STD_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_STD_MASK) >> DAO_RX_CFGR_STD_SHIFT) - -/* - * DATSIZ (RW) - * - * Data length to be transferred - * 00: 16-bit data length - * 01: 24-bit data length - * 10: 32-bit data length - * 11: Not allowed - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define DAO_RX_CFGR_DATSIZ_MASK (0x6U) -#define DAO_RX_CFGR_DATSIZ_SHIFT (1U) -#define DAO_RX_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_DATSIZ_SHIFT) & DAO_RX_CFGR_DATSIZ_MASK) -#define DAO_RX_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_DATSIZ_MASK) >> DAO_RX_CFGR_DATSIZ_SHIFT) - -/* - * CHSIZ (RW) - * - * Channel length (number of bits per audio channel) - * 0: 16-bit wide - * 1: 32-bit wide - * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. - * Note: For correct operation, this bit should be configured when the I2S is disabled. - */ -#define DAO_RX_CFGR_CHSIZ_MASK (0x1U) -#define DAO_RX_CFGR_CHSIZ_SHIFT (0U) -#define DAO_RX_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CHSIZ_SHIFT) & DAO_RX_CFGR_CHSIZ_MASK) -#define DAO_RX_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CHSIZ_MASK) >> DAO_RX_CFGR_CHSIZ_SHIFT) - -/* Bitfield definition for register: RXSLT */ -/* - * EN (RW) - * - * Slot enable for the channels. - */ -#define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) -#define DAO_RXSLT_EN_SHIFT (0U) -#define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) -#define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_MA_COEF_SHIFT (0U) -#define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) -#define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_B_COEF_SHIFT (0U) -#define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) -#define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_DAO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ddrctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ddrctl_regs.h deleted file mode 100644 index e777d2a75a1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ddrctl_regs.h +++ /dev/null @@ -1,3636 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DDRCTL_H -#define HPM_DDRCTL_H - -typedef struct { - __RW uint32_t MSTR; /* 0x0: Description: Master Register */ - __R uint32_t STAT; /* 0x4: Description: Operating Mode Status Register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t MRCTRL0; /* 0x10: Description: Mode Register Read/Write Control Register 0 */ - __RW uint32_t MRCTRL1; /* 0x14: Description: Mode Register Read/Write Control Register 1 */ - __R uint32_t MRSTAT; /* 0x18: Description: Mode Register Read/Write Status Register */ - __R uint8_t RESERVED1[20]; /* 0x1C - 0x2F: Reserved */ - __RW uint32_t PWRCTL; /* 0x30: Description: Low Power Control Register */ - __RW uint32_t PWRTMG; /* 0x34: Description: Low Power Timing Register */ - __RW uint32_t HWLPCTL; /* 0x38: Description: Hardware Low Power Control Register */ - __R uint8_t RESERVED2[20]; /* 0x3C - 0x4F: Reserved */ - __RW uint32_t RFSHCTL0; /* 0x50: Description: Refresh Control Register 0 */ - __RW uint32_t RFSHCTL1; /* 0x54: Description: Refresh Control Register 1 */ - __R uint8_t RESERVED3[8]; /* 0x58 - 0x5F: Reserved */ - __RW uint32_t RFSHCTL3; /* 0x60: Description: Refresh Control Register 0 */ - __RW uint32_t RFSHTMG; /* 0x64: Description: Refresh Timing Register */ - __R uint8_t RESERVED4[60]; /* 0x68 - 0xA3: Reserved */ - __R uint32_t ECCUADDR0; /* 0xA4: Description: ECC Uncorrected Error Address Register 0 */ - __R uint8_t RESERVED5[24]; /* 0xA8 - 0xBF: Reserved */ - __RW uint32_t CRCPARCTL0; /* 0xC0: Description: CRC Parity Control Register0 */ - __R uint8_t RESERVED6[8]; /* 0xC4 - 0xCB: Reserved */ - __R uint32_t CRCPARSTAT; /* 0xCC: Description: CRC Parity Status Register */ - __RW uint32_t INIT0; /* 0xD0: Description: SDRAM Initialization Register 0 */ - __RW uint32_t INIT1; /* 0xD4: Description: SDRAM Initialization Register 1 */ - __R uint8_t RESERVED7[4]; /* 0xD8 - 0xDB: Reserved */ - __RW uint32_t INIT3; /* 0xDC: Description: SDRAM Initialization Register 3 */ - __RW uint32_t INIT4; /* 0xE0: Description: SDRAM Initialization Register 4 */ - __RW uint32_t INIT5; /* 0xE4: Description: SDRAM Initialization Register 5 */ - __R uint8_t RESERVED8[8]; /* 0xE8 - 0xEF: Reserved */ - __RW uint32_t DIMMCTL; /* 0xF0: Description: DIMM Control Register */ - __RW uint32_t RANKCTL; /* 0xF4: Description: Rank Control Register */ - __R uint8_t RESERVED9[8]; /* 0xF8 - 0xFF: Reserved */ - __RW uint32_t DRAMTMG0; /* 0x100: Description: SDRAM Timing Register 0 */ - __RW uint32_t DRAMTMG1; /* 0x104: Description: SDRAM Timing Register 1 */ - __RW uint32_t DRAMTMG2; /* 0x108: Description: SDRAM Timing Register 2 */ - __RW uint32_t DRAMTMG3; /* 0x10C: Description: SDRAM Timing Register 3 */ - __RW uint32_t DRAMTMG4; /* 0x110: Description: SDRAM Timing Register 4 */ - __RW uint32_t DRAMTMG5; /* 0x114: Description: SDRAM Timing Register 5 */ - __R uint8_t RESERVED10[8]; /* 0x118 - 0x11F: Reserved */ - __RW uint32_t DRAMTMG8; /* 0x120: Description: SDRAM Timing Register 8 */ - __R uint8_t RESERVED11[92]; /* 0x124 - 0x17F: Reserved */ - __RW uint32_t ZQCTL0; /* 0x180: Description: ZQ Control Register 0 */ - __RW uint32_t ZQCTL1; /* 0x184: Description: ZQ Control Register 1 */ - __R uint8_t RESERVED12[4]; /* 0x188 - 0x18B: Reserved */ - __R uint32_t ZQSTAT; /* 0x18C: Description: ZQ Status Register */ - __RW uint32_t DFITMG0; /* 0x190: Description: DFI Timing Register 0 */ - __RW uint32_t DFITMG1; /* 0x194: Description: DFI Timing Register 1 */ - __RW uint32_t DFILPCFG0; /* 0x198: Description: DFI Low Power Configuration Register 0 */ - __R uint8_t RESERVED13[4]; /* 0x19C - 0x19F: Reserved */ - __RW uint32_t DFIUPD0; /* 0x1A0: Description: DFI Update Register 0 */ - __RW uint32_t DFIUPD1; /* 0x1A4: Description: DFI Update Register 1 */ - __RW uint32_t DFIUPD2; /* 0x1A8: Description: DFI Update Register 2 */ - __RW uint32_t DFIUPD3; /* 0x1AC: Description: DFI Update Register 3 */ - __RW uint32_t DFIMISC; /* 0x1B0: Description: DFI Miscellaneous Control Register */ - __RW uint32_t DFITMG2; /* 0x1B4: Description: DFI Timing Register 2 */ - __R uint8_t RESERVED14[72]; /* 0x1B8 - 0x1FF: Reserved */ - __RW uint32_t ADDRMAP0; /* 0x200: Description: Address Map Register 0 */ - __RW uint32_t ADDRMAP1; /* 0x204: Description: Address Map Register 1 */ - __RW uint32_t ADDRMAP2; /* 0x208: Description: Address Map Register 2 */ - __RW uint32_t ADDRMAP3; /* 0x20C: Description: Address Map Register 3 */ - __RW uint32_t ADDRMAP4; /* 0x210: Description: Address Map Register 4 */ - __RW uint32_t ADDRMAP5; /* 0x214: Description: Address Map Register 5 */ - __RW uint32_t ADDRMAP6; /* 0x218: Description: Address Map Register 6 */ - __R uint8_t RESERVED15[36]; /* 0x21C - 0x23F: Reserved */ - __RW uint32_t ODTCFG; /* 0x240: Description: ODT Configuration Register */ - __RW uint32_t ODTMAP; /* 0x244: Description: ODT/Rank Map Register */ - __R uint8_t RESERVED16[8]; /* 0x248 - 0x24F: Reserved */ - __RW uint32_t SCHED; /* 0x250: Description: Scheduler Control Register */ - __RW uint32_t SCHED1; /* 0x254: Description: Scheduler Control Register 1 */ - __R uint8_t RESERVED17[4]; /* 0x258 - 0x25B: Reserved */ - __RW uint32_t PERFHPR1; /* 0x25C: Description: High Priority Read CAM Register 1 */ - __R uint8_t RESERVED18[4]; /* 0x260 - 0x263: Reserved */ - __RW uint32_t PERFLPR1; /* 0x264: Description: Low Priority Read CAM Register 1 */ - __R uint8_t RESERVED19[4]; /* 0x268 - 0x26B: Reserved */ - __RW uint32_t PERFWR1; /* 0x26C: Description: Write CAM Register 1 */ - __R uint8_t RESERVED20[4]; /* 0x270 - 0x273: Reserved */ - __RW uint32_t PERFVPR1; /* 0x274: Description: Variable Priority Read CAM Register 1 */ - __RW uint32_t PERFVPW1; /* 0x278: Description: Variable Priority Write CAM Register 1 */ - __R uint8_t RESERVED21[132]; /* 0x27C - 0x2FF: Reserved */ - __RW uint32_t DBG0; /* 0x300: Description: Debug Register 0 */ - __RW uint32_t DBG1; /* 0x304: Description: Debug Register 1 */ - __R uint32_t DBGCAM; /* 0x308: Description: CAM Debug Register */ - __RW uint32_t DBGCMD; /* 0x30C: Description: Command Debug Register */ - __R uint32_t DBGSTAT; /* 0x310: Description: Status Debug Register */ - __R uint8_t RESERVED22[232]; /* 0x314 - 0x3FB: Reserved */ - __R uint32_t PSTAT; /* 0x3FC: Description: Port Status Register */ - __RW uint32_t PCCFG; /* 0x400: Description: Port Common Configuration Register */ - struct { - __RW uint32_t R; /* 0x404: Description: Port n Configuration Read Register */ - __RW uint32_t W; /* 0x408: Description: Port n Configuration Write Register */ - __RW uint32_t C; /* 0x40C: Description: Port n Common Configuration Register */ - struct { - __RW uint32_t MASKCH; /* 0x410: Description: Port n Channel m Configuration ID Mask Register */ - __RW uint32_t VALUECH; /* 0x414: Description: Port n Channel m Configuration ID Value Register */ - } ID[16]; - __RW uint32_t CTRL; /* 0x490: Description: Port n Control Register */ - __RW uint32_t QOS0; /* 0x494: Description: Port n Read QoS Configuration Register 0 */ - __RW uint32_t QOS1; /* 0x498: Description: Port n Read QoS Configuration Register 1 */ - __RW uint32_t WQOS0; /* 0x49C: Description: Port n Write QoS Configuration Register 0 */ - __RW uint32_t WQOS1; /* 0x4A0: Description: Port n Write QoS Configuration Register 1 */ - __R uint8_t RESERVED0[16]; /* 0x4A4 - 0x4B3: Reserved */ - } PCFG[16]; - struct { - __RW uint32_t BASE; /* 0xF04: Description: SAR Base Address Register n */ - __RW uint32_t SIZE; /* 0xF08: Description: SAR Size Register n */ - } SAR[4]; - __RW uint32_t SBRCTL; /* 0xF24: Description: Scrubber Control Register */ - __R uint32_t SBRSTAT; /* 0xF28: Description: Scrubber Status Register */ - __RW uint32_t SBRWDATA0; /* 0xF2C: Description: Scrubber Write Data Pattern0 */ - __R uint8_t RESERVED23[4]; /* 0xF30 - 0xF33: Reserved */ -} DDRCTL_Type; - - -/* Bitfield definition for register: MSTR */ -/* - * ACTIVE_RANKS (R/W) - * - * Description: Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are present. - * 1 - populated - * 0 - unpopulated - * LSB is the lowest rank number. - * For 2 ranks following combinations are legal: - * 01 - One rank - * 11 - Two ranks - * Others - Reserved. - * For 4 ranks following combinations are legal: - * 0001 - One rank - * 0011 - Two ranks - * 1111 - Four ranks - * Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF - * :((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_MSTR_ACTIVE_RANKS_MASK (0xF000000UL) -#define DDRCTL_MSTR_ACTIVE_RANKS_SHIFT (24U) -#define DDRCTL_MSTR_ACTIVE_RANKS_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_ACTIVE_RANKS_SHIFT) & DDRCTL_MSTR_ACTIVE_RANKS_MASK) -#define DDRCTL_MSTR_ACTIVE_RANKS_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_ACTIVE_RANKS_MASK) >> DDRCTL_MSTR_ACTIVE_RANKS_SHIFT) - -/* - * BURST_RDWR (R/W) - * - * Description: SDRAM burst length used: - * 0001 - Burst length of 2 (only supported for mDDR) - * 0010 - Burst length of 4 - * 0100 - Burst length of 8 - * 1000 - Burst length of 16 (only supported for mDDR and LPDDR2) - * All other values are reserved. - * This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH is 8. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_MSTR_BURST_RDWR_MASK (0xF0000UL) -#define DDRCTL_MSTR_BURST_RDWR_SHIFT (16U) -#define DDRCTL_MSTR_BURST_RDWR_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_BURST_RDWR_SHIFT) & DDRCTL_MSTR_BURST_RDWR_MASK) -#define DDRCTL_MSTR_BURST_RDWR_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_BURST_RDWR_MASK) >> DDRCTL_MSTR_BURST_RDWR_SHIFT) - -/* - * DLL_OFF_MODE (R/W) - * - * Description: Set to 1 when uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. - * Set to 0 to put uMCTL2 and DRAM in DLL-on mode for normal frequency operation. - * Value After Reset: 0x0 - * Exists: MEMC_DDR3_OR_4==1 - */ -#define DDRCTL_MSTR_DLL_OFF_MODE_MASK (0x8000U) -#define DDRCTL_MSTR_DLL_OFF_MODE_SHIFT (15U) -#define DDRCTL_MSTR_DLL_OFF_MODE_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DLL_OFF_MODE_SHIFT) & DDRCTL_MSTR_DLL_OFF_MODE_MASK) -#define DDRCTL_MSTR_DLL_OFF_MODE_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DLL_OFF_MODE_MASK) >> DDRCTL_MSTR_DLL_OFF_MODE_SHIFT) - -/* - * DATA_BUS_WIDTH (R/W) - * - * Description: Selects proportion of DQ bus width that is used by the SDRAM - * 00 - Full DQ bus width to SDRAM - * 01 - Half DQ bus width to SDRAM - * 10 - Quarter DQ bus width to SDRAM - * 11 - Reserved. - * Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_MSTR_DATA_BUS_WIDTH_MASK (0x3000U) -#define DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT (12U) -#define DDRCTL_MSTR_DATA_BUS_WIDTH_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK) -#define DDRCTL_MSTR_DATA_BUS_WIDTH_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DATA_BUS_WIDTH_MASK) >> DDRCTL_MSTR_DATA_BUS_WIDTH_SHIFT) - -/* - * EN_2T_TIMING_MODE (R/W) - * - * Description: If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command - * Note: 2T timing is not supported in LPDDR2/LPDDR3 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set - * Note: 2T timing is not supported in DDR4 geardown mode. - * Value After Reset: 0x0 - * Exists: MEMC_CMD_RTN2IDLE==0 - */ -#define DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK (0x400U) -#define DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT (10U) -#define DDRCTL_MSTR_EN_2T_TIMING_MODE_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK) -#define DDRCTL_MSTR_EN_2T_TIMING_MODE_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_EN_2T_TIMING_MODE_MASK) >> DDRCTL_MSTR_EN_2T_TIMING_MODE_SHIFT) - -/* - * BURSTCHOP (R/W) - * - * Description: When set, enable burst-chop in DDR3/DDR4. This is only supported in full bus width mode (MSTR.data_bus_width = 00). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' - * Value After Reset: 0x0 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 - */ -#define DDRCTL_MSTR_BURSTCHOP_MASK (0x200U) -#define DDRCTL_MSTR_BURSTCHOP_SHIFT (9U) -#define DDRCTL_MSTR_BURSTCHOP_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_BURSTCHOP_SHIFT) & DDRCTL_MSTR_BURSTCHOP_MASK) -#define DDRCTL_MSTR_BURSTCHOP_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_BURSTCHOP_MASK) >> DDRCTL_MSTR_BURSTCHOP_SHIFT) - -/* - * DDR3 (R/W) - * - * Description: Select DDR3 SDRAM - * 1 - DDR3 SDRAM device in use - * 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3. - * Value After Reset: "(MEMC_DDR3_EN==1) ? 0x1 : 0x0" - * Exists: MEMC_DDR3==1 - */ -#define DDRCTL_MSTR_DDR3_MASK (0x1U) -#define DDRCTL_MSTR_DDR3_SHIFT (0U) -#define DDRCTL_MSTR_DDR3_SET(x) (((uint32_t)(x) << DDRCTL_MSTR_DDR3_SHIFT) & DDRCTL_MSTR_DDR3_MASK) -#define DDRCTL_MSTR_DDR3_GET(x) (((uint32_t)(x) & DDRCTL_MSTR_DDR3_MASK) >> DDRCTL_MSTR_DDR3_SHIFT) - -/* Bitfield definition for register: STAT */ -/* - * SELFREF_TYPE (R) - * - * Description: Flags if Self Refresh is entered and if it was under Automatic Self Refresh control only or not. - * 00 - SDRAM is not in Self Refresh - * 11 - SDRAM is in Self Refresh and Self Refresh was caused by Automatic Self Refresh only - * 10 - SDRAM is in Self Refresh and Self Refresh was not caused solely under Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software (reg_ddrc_selfref_sw). - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_STAT_SELFREF_TYPE_MASK (0x30U) -#define DDRCTL_STAT_SELFREF_TYPE_SHIFT (4U) -#define DDRCTL_STAT_SELFREF_TYPE_GET(x) (((uint32_t)(x) & DDRCTL_STAT_SELFREF_TYPE_MASK) >> DDRCTL_STAT_SELFREF_TYPE_SHIFT) - -/* - * OPERATING_MODE (R) - * - * Description: Operating mode. This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/DDR4 support and 2-bits in all other configurations. - * non-mDDR/LPDDR2/LPDDR3 and non-DDR4 designs: - * 00 - Init - * 01 - Normal - * 10 - Power-down - * 11 - Self refresh - * mDDR/LPDDR2/LPDDR3 or DDR4 designs: - * 000 - Init - * 001 - Normal - * 010 - Power-down - * 011 - Self refresh - * 1XX - Deep power-down / Maximum Power Saving Mode - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_STAT_OPERATING_MODE_MASK (0x7U) -#define DDRCTL_STAT_OPERATING_MODE_SHIFT (0U) -#define DDRCTL_STAT_OPERATING_MODE_GET(x) (((uint32_t)(x) & DDRCTL_STAT_OPERATING_MODE_MASK) >> DDRCTL_STAT_OPERATING_MODE_SHIFT) - -/* Bitfield definition for register: MRCTRL0 */ -/* - * MR_WR (R/W) - * - * Description: Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL2 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power- down or MPSM operating modes. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_MRCTRL0_MR_WR_MASK (0x80000000UL) -#define DDRCTL_MRCTRL0_MR_WR_SHIFT (31U) -#define DDRCTL_MRCTRL0_MR_WR_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_WR_SHIFT) & DDRCTL_MRCTRL0_MR_WR_MASK) -#define DDRCTL_MRCTRL0_MR_WR_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_WR_MASK) >> DDRCTL_MRCTRL0_MR_WR_SHIFT) - -/* - * MR_ADDR (R/W) - * - * Description: Address of the mode register that is to be written to. - * 0000 - MR0 - * 0001 - MR1 - * 0010 - MR2 - * 0011 - MR3 - * 0100 - MR4 - * 0101 - MR5 - * 0110 - MR6 - * 0111 - MR7 - * Don't Care for LPDDR2/LPDDR3 (see MRCTRL1.mr_data for mode register addressing in LPDDR2/LPDDR3) - * This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM - * In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well as the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of RDIMMs. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_MRCTRL0_MR_ADDR_MASK (0xF000U) -#define DDRCTL_MRCTRL0_MR_ADDR_SHIFT (12U) -#define DDRCTL_MRCTRL0_MR_ADDR_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_ADDR_SHIFT) & DDRCTL_MRCTRL0_MR_ADDR_MASK) -#define DDRCTL_MRCTRL0_MR_ADDR_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_ADDR_MASK) >> DDRCTL_MRCTRL0_MR_ADDR_SHIFT) - -/* - * MR_RANK (R/W) - * - * Description: Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. - * Examples (assume uMCTL2 is configured for 4 ranks): - * 0x1 - select rank 0 only - * 0x2 - select rank 1 only - * 0x5 - select ranks 0 and 2 - * 0xA - select ranks 1 and 3 - * 0xF - select ranks 0, 1, 2 and 3 - * Value After Reset: "(MEMC_NUM_RANKS==4) ? 0xF - * :((MEMC_NUM_RANKS==2) ? 0x3 : 0x1)" - * Exists: Always - */ -#define DDRCTL_MRCTRL0_MR_RANK_MASK (0xF0U) -#define DDRCTL_MRCTRL0_MR_RANK_SHIFT (4U) -#define DDRCTL_MRCTRL0_MR_RANK_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL0_MR_RANK_SHIFT) & DDRCTL_MRCTRL0_MR_RANK_MASK) -#define DDRCTL_MRCTRL0_MR_RANK_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL0_MR_RANK_MASK) >> DDRCTL_MRCTRL0_MR_RANK_SHIFT) - -/* Bitfield definition for register: MRCTRL1 */ -/* - * MR_DATA (R/W) - * - * Description: Mode register write data for all non- LPDDR2/non-LPDDR3 modes. - * For LPDDR2/LPDDR3, MRCTRL1[15:0] are interpreted as [15:8] MR Address and [7:0] MR data for writes, don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_MRCTRL1_MR_DATA_MASK (0x3FFFFUL) -#define DDRCTL_MRCTRL1_MR_DATA_SHIFT (0U) -#define DDRCTL_MRCTRL1_MR_DATA_SET(x) (((uint32_t)(x) << DDRCTL_MRCTRL1_MR_DATA_SHIFT) & DDRCTL_MRCTRL1_MR_DATA_MASK) -#define DDRCTL_MRCTRL1_MR_DATA_GET(x) (((uint32_t)(x) & DDRCTL_MRCTRL1_MR_DATA_MASK) >> DDRCTL_MRCTRL1_MR_DATA_SHIFT) - -/* Bitfield definition for register: MRSTAT */ -/* - * MR_WR_BUSY (R) - * - * Description: The SoC core may initiate a MR write operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the MRW/MRR request. It goes low when the MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when 'MRSTAT.mr_wr_busy' is high. - * 0 - Indicates that the SoC core can initiate a mode register write operation - * 1 - Indicates that mode register write operation is in progress - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_MRSTAT_MR_WR_BUSY_MASK (0x1U) -#define DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT (0U) -#define DDRCTL_MRSTAT_MR_WR_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_MRSTAT_MR_WR_BUSY_MASK) >> DDRCTL_MRSTAT_MR_WR_BUSY_SHIFT) - -/* Bitfield definition for register: PWRCTL */ -/* - * SELFREF_SW (R/W) - * - * Description: A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - * 1 - Software Entry to Self Refresh - * 0 - Software Exit from Self Refresh - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PWRCTL_SELFREF_SW_MASK (0x20U) -#define DDRCTL_PWRCTL_SELFREF_SW_SHIFT (5U) -#define DDRCTL_PWRCTL_SELFREF_SW_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_SW_SHIFT) & DDRCTL_PWRCTL_SELFREF_SW_MASK) -#define DDRCTL_PWRCTL_SELFREF_SW_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_SW_MASK) >> DDRCTL_PWRCTL_SELFREF_SW_SHIFT) - -/* - * EN_DFI_DRAM_CLK_DISABLE (R/W) - * - * Description: Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. - * If set to 0, dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: - * In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can be asserted in following: - * in Self Refresh. - * in Maximum Power Saving Mode - * In mDDR/LPDDR2/LPDDR3, can be asserted in following: - * in Self Refresh - * in Power Down - * in Deep Power Down - * during Normal operation (Clock Stop) - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK (0x8U) -#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT (3U) -#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK) -#define DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK) >> DDRCTL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT) - -/* - * POWERDOWN_EN (R/W) - * - * Description: If true then the uMCTL2 goes into power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). - * This register bit may be re-programmed during the course of normal operation. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PWRCTL_POWERDOWN_EN_MASK (0x2U) -#define DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT (1U) -#define DDRCTL_PWRCTL_POWERDOWN_EN_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK) -#define DDRCTL_PWRCTL_POWERDOWN_EN_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_POWERDOWN_EN_MASK) >> DDRCTL_PWRCTL_POWERDOWN_EN_SHIFT) - -/* - * SELFREF_EN (R/W) - * - * Description: If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re- programmed during the course of normal operation. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PWRCTL_SELFREF_EN_MASK (0x1U) -#define DDRCTL_PWRCTL_SELFREF_EN_SHIFT (0U) -#define DDRCTL_PWRCTL_SELFREF_EN_SET(x) (((uint32_t)(x) << DDRCTL_PWRCTL_SELFREF_EN_SHIFT) & DDRCTL_PWRCTL_SELFREF_EN_MASK) -#define DDRCTL_PWRCTL_SELFREF_EN_GET(x) (((uint32_t)(x) & DDRCTL_PWRCTL_SELFREF_EN_MASK) >> DDRCTL_PWRCTL_SELFREF_EN_SHIFT) - -/* Bitfield definition for register: PWRTMG */ -/* - * SELFREF_TO_X32 (R/W) - * - * Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_en. - * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - * Value After Reset: 0x40 - * Exists: Always - */ -#define DDRCTL_PWRTMG_SELFREF_TO_X32_MASK (0xFF0000UL) -#define DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT (16U) -#define DDRCTL_PWRTMG_SELFREF_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK) -#define DDRCTL_PWRTMG_SELFREF_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_PWRTMG_SELFREF_TO_X32_MASK) >> DDRCTL_PWRTMG_SELFREF_TO_X32_SHIFT) - -/* - * POWERDOWN_TO_X32 (R/W) - * - * Description: After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_en. - * Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK (0x1FU) -#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT (0U) -#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK) -#define DDRCTL_PWRTMG_POWERDOWN_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_PWRTMG_POWERDOWN_TO_X32_MASK) >> DDRCTL_PWRTMG_POWERDOWN_TO_X32_SHIFT) - -/* Bitfield definition for register: HWLPCTL */ -/* - * HW_LP_IDLE_X32 (R/W) - * - * Description: Hardware idle period. The cactive_ddrc output is driven low if the system is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The hardware idle function is disabled when hw_lp_idle_x32=0. - * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK (0xFFF0000UL) -#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT (16U) -#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK) -#define DDRCTL_HWLPCTL_HW_LP_IDLE_X32_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_IDLE_X32_MASK) >> DDRCTL_HWLPCTL_HW_LP_IDLE_X32_SHIFT) - -/* - * HW_LP_EXIT_IDLE_EN (R/W) - * - * Description: When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop, automatic power down or automatic self-refresh modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK (0x2U) -#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT (1U) -#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK) -#define DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EXIT_IDLE_EN_SHIFT) - -/* - * HW_LP_EN (R/W) - * - * Description: Enable for Hardware Low Power Interface. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_HWLPCTL_HW_LP_EN_MASK (0x1U) -#define DDRCTL_HWLPCTL_HW_LP_EN_SHIFT (0U) -#define DDRCTL_HWLPCTL_HW_LP_EN_SET(x) (((uint32_t)(x) << DDRCTL_HWLPCTL_HW_LP_EN_SHIFT) & DDRCTL_HWLPCTL_HW_LP_EN_MASK) -#define DDRCTL_HWLPCTL_HW_LP_EN_GET(x) (((uint32_t)(x) & DDRCTL_HWLPCTL_HW_LP_EN_MASK) >> DDRCTL_HWLPCTL_HW_LP_EN_SHIFT) - -/* Bitfield definition for register: RFSHCTL0 */ -/* - * REFRESH_MARGIN (R/W) - * - * Description: Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3, internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to RFSHTMG.t_rfc_nom_x32. - * Unit: Multiples of 32 clocks. Value After Reset: 0x2 Exists: Always - */ -#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK (0xF00000UL) -#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT (20U) -#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK) -#define DDRCTL_RFSHCTL0_REFRESH_MARGIN_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_MARGIN_MASK) >> DDRCTL_RFSHCTL0_REFRESH_MARGIN_SHIFT) - -/* - * REFRESH_TO_X32 (R/W) - * - * Description: If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the uMCTL2. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK (0x1F000UL) -#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT (12U) -#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK) -#define DDRCTL_RFSHCTL0_REFRESH_TO_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_TO_X32_MASK) >> DDRCTL_RFSHCTL0_REFRESH_TO_X32_SHIFT) - -/* - * REFRESH_BURST (R/W) - * - * Description: The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. - * 0 - single refresh - * 1 - burst-of-2 refresh - * 7 - burst-of-8 refresh - * For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. - * For DDR2/3, the refresh is always per-rank and not per- bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granuarity feature, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiated update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY- initiated update is complete. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_RFSHCTL0_REFRESH_BURST_MASK (0x1F0U) -#define DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT (4U) -#define DDRCTL_RFSHCTL0_REFRESH_BURST_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK) -#define DDRCTL_RFSHCTL0_REFRESH_BURST_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL0_REFRESH_BURST_MASK) >> DDRCTL_RFSHCTL0_REFRESH_BURST_SHIFT) - -/* Bitfield definition for register: RFSHCTL1 */ -/* - * REFRESH_TIMER1_START_VALUE_X32 (R/W) - * - * Description: Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. - * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - * Value After Reset: 0x0 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK (0xFFF0000UL) -#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT (16U) -#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) -#define DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT) - -/* - * REFRESH_TIMER0_START_VALUE_X32 (R/W) - * - * Description: Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of architecture chapter. - * Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - * Value After Reset: 0x0 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK (0xFFFU) -#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT (0U) -#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) -#define DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK) >> DDRCTL_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT) - -/* Bitfield definition for register: RFSHCTL3 */ -/* - * REFRESH_UPDATE_LEVEL (R/W) - * - * Description: Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. - * The value is automatically updated when exiting soft reset, so it does not need to be toggled initially. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK (0x2U) -#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT (1U) -#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK) -#define DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK) >> DDRCTL_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT) - -/* - * DIS_AUTO_REFRESH (R/W) - * - * Description: When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. - * When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. - * If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto- refresh is not supported, and this bit must be set to '0'. - * This register field is changeable on the fly. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK (0x1U) -#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT (0U) -#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK) -#define DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_MASK) >> DDRCTL_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT) - -/* Bitfield definition for register: RFSHTMG */ -/* - * T_RFC_NOM_X32 (R/W) - * - * Description: tREFI: Average time interval between refreshes per rank (specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2 and LPDDR3). - * For LPDDR2/LPDDR3: - * if using all-bank refreshes (RFSHCTL0.per_bank_refresh - * = 0), this register should be set to tREFIab - * if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tREFIpb - * For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. - * In DDR4 mode, tREFI value is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value programmed in the refresh mode register. - * Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min. Unit: Multiples of 32 clocks. - * Value After Reset: 0x62 - * Exists: Always - */ -#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK (0xFFF0000UL) -#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT (16U) -#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_SET(x) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK) -#define DDRCTL_RFSHTMG_T_RFC_NOM_X32_GET(x) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_NOM_X32_MASK) >> DDRCTL_RFSHTMG_T_RFC_NOM_X32_SHIFT) - -/* - * T_RFC_MIN (R/W) - * - * Description: tRFC (min): Minimum time from refresh to refresh or activate. - * For LPDDR2/LPDDR3: - * if using all-bank refreshes (RFSHCTL0.per_bank_refresh - * = 0), this register should be set to tRFCab - * if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should be set to tRFCpb - * For configurations with MEMC_FREQ_RATIO=2, program this to tRFC(min)/2 and round up to next integer value. - * In DDR4 mode, tRFC(min) value is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the appropriate value from the spec based on the 'refresh_mode' and the device density that is used. - * Unit: Clocks. - * Value After Reset: 0x8c - * Exists: Always - */ -#define DDRCTL_RFSHTMG_T_RFC_MIN_MASK (0x1FFU) -#define DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT (0U) -#define DDRCTL_RFSHTMG_T_RFC_MIN_SET(x) (((uint32_t)(x) << DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK) -#define DDRCTL_RFSHTMG_T_RFC_MIN_GET(x) (((uint32_t)(x) & DDRCTL_RFSHTMG_T_RFC_MIN_MASK) >> DDRCTL_RFSHTMG_T_RFC_MIN_SHIFT) - -/* Bitfield definition for register: ECCUADDR0 */ -/* - * ECC_UNCORR_RANK (R) - * - * Description: Rank number of a read resulting in an uncorrected ECC error - * Value After Reset: 0x0 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK (0x3000000UL) -#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT (24U) -#define DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_GET(x) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_RANK_SHIFT) - -/* - * ECC_UNCORR_ROW (R) - * - * Description: Page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK (0x3FFFFUL) -#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT (0U) -#define DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_GET(x) (((uint32_t)(x) & DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_MASK) >> DDRCTL_ECCUADDR0_ECC_UNCORR_ROW_SHIFT) - -/* Bitfield definition for register: CRCPARCTL0 */ -/* - * DFI_ALERT_ERR_CNT_CLR (R/W1C) - * - * Description: DFI alert error count clear. Clear bit for DFI alert error counter. Asserting this bit will clear the DFI alert error counter, CRCPARSTAT.dfi_alert_err_cnt. When the clear operation is complete, the uMCTL2 automatically clears this bit. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK (0x4U) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT (2U) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_CNT_CLR_SHIFT) - -/* - * DFI_ALERT_ERR_INT_CLR (R/W1C) - * - * Description: Interrupt clear bit for DFI alert error. If this bit is set, the alert error interrupt on CRCPARSTAT.dfi_alert_err_int will be cleared. When the clear operation is complete, the uMCTL2 automatically clears this bit. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK (0x2U) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT (1U) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_CLR_SHIFT) - -/* - * DFI_ALERT_ERR_INT_EN (R/W) - * - * Description: Interrupt enable bit for DFI alert error. If this bit is set, any parity/CRC error detected on the dfi_alert_n input will result in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK (0x1U) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT (0U) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SET(x) (((uint32_t)(x) << DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK) -#define DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_MASK) >> DDRCTL_CRCPARCTL0_DFI_ALERT_ERR_INT_EN_SHIFT) - -/* Bitfield definition for register: CRCPARSTAT */ -/* - * DFI_ALERT_ERR_INT (R) - * - * Description: DFI alert error interrupt. - * If a parity/CRC error is detected on dfi_alert_n, and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en, this interrupt bit will be set. It will remain set until cleared by CRCPARCTL0.dfi_alert_err_int_clr - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK (0x10000UL) -#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT (16U) -#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_INT_SHIFT) - -/* - * DFI_ALERT_ERR_CNT (R) - * - * Description: DFI alert error count. - * If a parity/CRC error is detected on dfi_alert_n, this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It will saturate at 0xFFFF, and can be cleared by asserting CRCPARCTL0.dfi_alert_err_cnt_clr. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK (0xFFFFU) -#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT (0U) -#define DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_GET(x) (((uint32_t)(x) & DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_MASK) >> DDRCTL_CRCPARSTAT_DFI_ALERT_ERR_CNT_SHIFT) - -/* Bitfield definition for register: INIT0 */ -/* - * SKIP_DRAM_INIT (R/W) - * - * Description: If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed - * 00 - SDRAM Initialization routine is run after power-up - * 01 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Normal Mode - * 11 - SDRAM Initialization routine is skipped after power- up. Controller starts up in Self-refresh Mode - * 10 - SDRAM Initialization routine is run after power-up. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_INIT0_SKIP_DRAM_INIT_MASK (0xC0000000UL) -#define DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT (30U) -#define DDRCTL_INIT0_SKIP_DRAM_INIT_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK) -#define DDRCTL_INIT0_SKIP_DRAM_INIT_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_SKIP_DRAM_INIT_MASK) >> DDRCTL_INIT0_SKIP_DRAM_INIT_SHIFT) - -/* - * POST_CKE_X1024 (R/W) - * - * Description: Cycles to wait after driving CKE high to start the SDRAM initialization sequence. - * Unit: 1024 clocks. - * DDR2 typically requires a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. - * LPDDR2/LPDDR3 typically requires this to be programmed for a delay of 200 us. - * For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. - * Value After Reset: 0x2 - * Exists: Always - */ -#define DDRCTL_INIT0_POST_CKE_X1024_MASK (0x3FF0000UL) -#define DDRCTL_INIT0_POST_CKE_X1024_SHIFT (16U) -#define DDRCTL_INIT0_POST_CKE_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_POST_CKE_X1024_SHIFT) & DDRCTL_INIT0_POST_CKE_X1024_MASK) -#define DDRCTL_INIT0_POST_CKE_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_POST_CKE_X1024_MASK) >> DDRCTL_INIT0_POST_CKE_X1024_SHIFT) - -/* - * PRE_CKE_X1024 (R/W) - * - * Description: Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. - * Unit: 1024 clock cycles. - * DDR2 specifications typically require this to be programmed for a delay of >= 200 us. - * LPDDR2/LPDDR3: tINIT1 of 100 ns (min) - * For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. - * Value After Reset: 0x4e - * Exists: Always - */ -#define DDRCTL_INIT0_PRE_CKE_X1024_MASK (0x3FFU) -#define DDRCTL_INIT0_PRE_CKE_X1024_SHIFT (0U) -#define DDRCTL_INIT0_PRE_CKE_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT0_PRE_CKE_X1024_SHIFT) & DDRCTL_INIT0_PRE_CKE_X1024_MASK) -#define DDRCTL_INIT0_PRE_CKE_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT0_PRE_CKE_X1024_MASK) >> DDRCTL_INIT0_PRE_CKE_X1024_SHIFT) - -/* Bitfield definition for register: INIT1 */ -/* - * DRAM_RSTN_X1024 (R/W) - * - * Description: Number of cycles to assert SDRAM reset signal during init sequence. - * This is only present for designs supporting DDR3/DDR4 devices. For use with a Synopsys DDR PHY, this should be set to a minimum of 1 - * Value After Reset: 0x0 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 - */ -#define DDRCTL_INIT1_DRAM_RSTN_X1024_MASK (0xFF0000UL) -#define DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT (16U) -#define DDRCTL_INIT1_DRAM_RSTN_X1024_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK) -#define DDRCTL_INIT1_DRAM_RSTN_X1024_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_DRAM_RSTN_X1024_MASK) >> DDRCTL_INIT1_DRAM_RSTN_X1024_SHIFT) - -/* - * FINAL_WAIT_X32 (R/W) - * - * Description: Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. - * Unit: Counts of a global timer that pulses every 32 clock cycles. - * There is no known specific requirement for this; it may be set to zero. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_INIT1_FINAL_WAIT_X32_MASK (0x7F00U) -#define DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT (8U) -#define DDRCTL_INIT1_FINAL_WAIT_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK) -#define DDRCTL_INIT1_FINAL_WAIT_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_FINAL_WAIT_X32_MASK) >> DDRCTL_INIT1_FINAL_WAIT_X32_SHIFT) - -/* - * PRE_OCD_X32 (R/W) - * - * Description: Wait period before driving the OCD complete command to SDRAM. - * Unit: Counts of a global timer that pulses every 32 clock cycles. - * There is no known specific requirement for this; it may be set to zero. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_INIT1_PRE_OCD_X32_MASK (0xFU) -#define DDRCTL_INIT1_PRE_OCD_X32_SHIFT (0U) -#define DDRCTL_INIT1_PRE_OCD_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT1_PRE_OCD_X32_SHIFT) & DDRCTL_INIT1_PRE_OCD_X32_MASK) -#define DDRCTL_INIT1_PRE_OCD_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT1_PRE_OCD_X32_MASK) >> DDRCTL_INIT1_PRE_OCD_X32_SHIFT) - -/* Bitfield definition for register: INIT3 */ -/* - * MR (R/W) - * - * Description: DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. - * DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. - * LPDDR2/LPDDR3 - Value to write to MR1 register - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_INIT3_MR_MASK (0xFFFF0000UL) -#define DDRCTL_INIT3_MR_SHIFT (16U) -#define DDRCTL_INIT3_MR_SET(x) (((uint32_t)(x) << DDRCTL_INIT3_MR_SHIFT) & DDRCTL_INIT3_MR_MASK) -#define DDRCTL_INIT3_MR_GET(x) (((uint32_t)(x) & DDRCTL_INIT3_MR_MASK) >> DDRCTL_INIT3_MR_SHIFT) - -/* - * EMR (R/W) - * - * Description: DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. - * DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by the uMCTL2 during write leveling. - * mDDR: Value to write to EMR register. LPDDR2/LPDDR3 - Value to write to MR2 register Value After Reset: 0x510 - * Exists: Always - */ -#define DDRCTL_INIT3_EMR_MASK (0xFFFFU) -#define DDRCTL_INIT3_EMR_SHIFT (0U) -#define DDRCTL_INIT3_EMR_SET(x) (((uint32_t)(x) << DDRCTL_INIT3_EMR_SHIFT) & DDRCTL_INIT3_EMR_MASK) -#define DDRCTL_INIT3_EMR_GET(x) (((uint32_t)(x) & DDRCTL_INIT3_EMR_MASK) >> DDRCTL_INIT3_EMR_SHIFT) - -/* Bitfield definition for register: INIT4 */ -/* - * EMR2 (R/W) - * - * Description: DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3: Value to write to MR3 register mDDR: Unused - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_INIT4_EMR2_MASK (0xFFFF0000UL) -#define DDRCTL_INIT4_EMR2_SHIFT (16U) -#define DDRCTL_INIT4_EMR2_SET(x) (((uint32_t)(x) << DDRCTL_INIT4_EMR2_SHIFT) & DDRCTL_INIT4_EMR2_MASK) -#define DDRCTL_INIT4_EMR2_GET(x) (((uint32_t)(x) & DDRCTL_INIT4_EMR2_MASK) >> DDRCTL_INIT4_EMR2_SHIFT) - -/* - * EMR3 (R/W) - * - * Description: DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_INIT4_EMR3_MASK (0xFFFFU) -#define DDRCTL_INIT4_EMR3_SHIFT (0U) -#define DDRCTL_INIT4_EMR3_SET(x) (((uint32_t)(x) << DDRCTL_INIT4_EMR3_SHIFT) & DDRCTL_INIT4_EMR3_MASK) -#define DDRCTL_INIT4_EMR3_GET(x) (((uint32_t)(x) & DDRCTL_INIT4_EMR3_MASK) >> DDRCTL_INIT4_EMR3_SHIFT) - -/* Bitfield definition for register: INIT5 */ -/* - * DEV_ZQINIT_X32 (R/W) - * - * Description: ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. - * Unit: 32 clock cycles. - * DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. - * LPDDR2/LPDDR3 requires 1 us. - * Value After Reset: 0x10 - * Exists: MEMC_DDR3==1 || MEMC_DDR4 == 1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_INIT5_DEV_ZQINIT_X32_MASK (0xFF0000UL) -#define DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT (16U) -#define DDRCTL_INIT5_DEV_ZQINIT_X32_SET(x) (((uint32_t)(x) << DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK) -#define DDRCTL_INIT5_DEV_ZQINIT_X32_GET(x) (((uint32_t)(x) & DDRCTL_INIT5_DEV_ZQINIT_X32_MASK) >> DDRCTL_INIT5_DEV_ZQINIT_X32_SHIFT) - -/* Bitfield definition for register: DIMMCTL */ -/* - * DIMM_ADDR_MIRR_EN (R/W) - * - * Description: Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). - * Some UDIMMs and DDR4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), - * (BG0, BG1) for the DDR4. Setting this bit ensures that, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compensate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. - * Note: This has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - * This is not supported for mDDR, LPDDR2 or LPDDR3 SDRAMs. - * Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1. - * 1 - For odd ranks, implement address mirroring for MRS commands to during initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - * 0 - Do not implement address mirroring - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK (0x2U) -#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT (1U) -#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SET(x) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK) -#define DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_GET(x) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT) - -/* - * DIMM_STAGGER_CS_EN (R/W) - * - * Description: Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for DDR4, mDDR, LPDDR2 or LPDDR3 SDRAMs. - * 1 - Stagger accesses to even and odd ranks - * 0 - Do not stagger accesses - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK (0x1U) -#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT (0U) -#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SET(x) (((uint32_t)(x) << DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK) -#define DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_GET(x) (((uint32_t)(x) & DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_MASK) >> DDRCTL_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT) - -/* Bitfield definition for register: RANKCTL */ -/* - * DIFF_RANK_WR_GAP (R/W) - * - * Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. - * This is used to switch the delays in the PHY to match the rank requirements. - * The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during writes. - * For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. - * Value After Reset: 0x6 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK (0xF00U) -#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT (8U) -#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK) -#define DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_WR_GAP_SHIFT) - -/* - * DIFF_RANK_RD_GAP (R/W) - * - * Description: Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. - * This is used to switch the delays in the PHY to match the rank requirements. - * The value programmed in this register takes care of the ODT switch off timing requirement when switching ranks during reads. - * For configurations with MEMC_FREQ_RATIO=2, program this to (N/2) and round it up to the next integer value. N is value required by PHY, in terms of PHY clocks. - * Value After Reset: 0x6 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK (0xF0U) -#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT (4U) -#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK) -#define DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_MASK) >> DDRCTL_RANKCTL_DIFF_RANK_RD_GAP_SHIFT) - -/* - * MAX_RANK_RD (R/W) - * - * Description: Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap - * dictated by the register RANKCTL.diff_rank_rd_gap. This is - * to avoid possible data bus contention as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on diff_rank_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. - * This parameter represents the maximum number of reads that can be scheduled consecutively to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. - * This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as long as commands are available for it. - * Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0xF. - * Feature limitation: max_rank_rd feature works as described only in the mode in which one command at the DDRC input results in one DFI command at the output. An example of this mode is: BL8 hardware configuration (MEMC_BURST_LENGTH=8) and Full bus width mode (MSTR.data_bus_width=2'b00) and BL8 mode of operation (MSTR.burst_rdwr=4'b0100). In modes where single HIF command results in multiple DFI commands (eg: Half Bus Width, BL4 etc.), the same rank commands would be serviced for as long as they are available, which is equivalent to this feature being disabled. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0xf - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_RANKCTL_MAX_RANK_RD_MASK (0xFU) -#define DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT (0U) -#define DDRCTL_RANKCTL_MAX_RANK_RD_SET(x) (((uint32_t)(x) << DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK) -#define DDRCTL_RANKCTL_MAX_RANK_RD_GET(x) (((uint32_t)(x) & DDRCTL_RANKCTL_MAX_RANK_RD_MASK) >> DDRCTL_RANKCTL_MAX_RANK_RD_SHIFT) - -/* Bitfield definition for register: DRAMTMG0 */ -/* - * WR2PRE (R/W) - * - * Description: Minimum time between write and precharge to same bank. - * Unit: Clocks - * Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies where: - * WL = write latency - * BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - * tWR = Write recovery time. This comes directly from the SDRAM specification. - * Add one extra cycle for LPDDR2/LPDDR3 for this parameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. - * For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up. - * Value After Reset: 0xf - * Exists: Always - */ -#define DDRCTL_DRAMTMG0_WR2PRE_MASK (0x7F000000UL) -#define DDRCTL_DRAMTMG0_WR2PRE_SHIFT (24U) -#define DDRCTL_DRAMTMG0_WR2PRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_WR2PRE_SHIFT) & DDRCTL_DRAMTMG0_WR2PRE_MASK) -#define DDRCTL_DRAMTMG0_WR2PRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_WR2PRE_MASK) >> DDRCTL_DRAMTMG0_WR2PRE_SHIFT) - -/* - * T_FAW (R/W) - * - * Description: tFAW Valid only when 8 or more banks(or banks x bank groups) are present. - * In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles. - * For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next integer value. - * In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. - * Unit: Clocks - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_DRAMTMG0_T_FAW_MASK (0x3F0000UL) -#define DDRCTL_DRAMTMG0_T_FAW_SHIFT (16U) -#define DDRCTL_DRAMTMG0_T_FAW_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_FAW_SHIFT) & DDRCTL_DRAMTMG0_T_FAW_MASK) -#define DDRCTL_DRAMTMG0_T_FAW_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_FAW_MASK) >> DDRCTL_DRAMTMG0_T_FAW_SHIFT) - -/* - * T_RAS_MAX (R/W) - * - * Description: tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open - * Minimum value of this register is 1. Zero is invalid. - * For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2. No rounding up. - * Unit: Multiples of 1024 clocks. Value After Reset: 0x1b Exists: Always - */ -#define DDRCTL_DRAMTMG0_T_RAS_MAX_MASK (0x7F00U) -#define DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT (8U) -#define DDRCTL_DRAMTMG0_T_RAS_MAX_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK) -#define DDRCTL_DRAMTMG0_T_RAS_MAX_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MAX_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MAX_SHIFT) - -/* - * T_RAS_MIN (R/W) - * - * Description: tRAS(min): Minimum time between activate and precharge to the same bank. - * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRAS(min)/2. No rounding up. - * For configurations with MEMC_FREQ_RATIO=2, 2T mode, program this to (tRAS(min)/2 + 1). No rounding up of the division operation. - * Unit: Clocks - * Value After Reset: 0xf - * Exists: Always - */ -#define DDRCTL_DRAMTMG0_T_RAS_MIN_MASK (0x3FU) -#define DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT (0U) -#define DDRCTL_DRAMTMG0_T_RAS_MIN_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK) -#define DDRCTL_DRAMTMG0_T_RAS_MIN_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG0_T_RAS_MIN_MASK) >> DDRCTL_DRAMTMG0_T_RAS_MIN_SHIFT) - -/* Bitfield definition for register: DRAMTMG1 */ -/* - * T_XP (R/W) - * - * Description: tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. - * If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it up to the next integer value. - * Units: Clocks - * Value After Reset: 0x8 - * Exists: Always - */ -#define DDRCTL_DRAMTMG1_T_XP_MASK (0x1F0000UL) -#define DDRCTL_DRAMTMG1_T_XP_SHIFT (16U) -#define DDRCTL_DRAMTMG1_T_XP_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_XP_SHIFT) & DDRCTL_DRAMTMG1_T_XP_MASK) -#define DDRCTL_DRAMTMG1_T_XP_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_XP_MASK) >> DDRCTL_DRAMTMG1_T_XP_SHIFT) - -/* - * RD2PRE (R/W) - * - * Description: tRTP: Minimum time from read to precharge of same bank. - * DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - * DDR3: tAL + max (tRTP, 4) - * DDR4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - * mDDR: BL/2 - * LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - * LPDDR3: BL/2 + max(tRTP,4) - 4 - * For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. - * For configurations with MEMC_FREQ_RATIO=2, 2T mode, divide the above value by 2 and add 1. No rounding up of division operation. - * Unit: Clocks. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DRAMTMG1_RD2PRE_MASK (0x1F00U) -#define DDRCTL_DRAMTMG1_RD2PRE_SHIFT (8U) -#define DDRCTL_DRAMTMG1_RD2PRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_RD2PRE_SHIFT) & DDRCTL_DRAMTMG1_RD2PRE_MASK) -#define DDRCTL_DRAMTMG1_RD2PRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_RD2PRE_MASK) >> DDRCTL_DRAMTMG1_RD2PRE_SHIFT) - -/* - * T_RC (R/W) - * - * Description: tRC: Minimum time between activates to same bank. - * For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next integer value. - * Unit: Clocks. - * Value After Reset: 0x14 - * Exists: Always - */ -#define DDRCTL_DRAMTMG1_T_RC_MASK (0x7FU) -#define DDRCTL_DRAMTMG1_T_RC_SHIFT (0U) -#define DDRCTL_DRAMTMG1_T_RC_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG1_T_RC_SHIFT) & DDRCTL_DRAMTMG1_T_RC_MASK) -#define DDRCTL_DRAMTMG1_T_RC_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG1_T_RC_MASK) >> DDRCTL_DRAMTMG1_T_RC_SHIFT) - -/* Bitfield definition for register: DRAMTMG2 */ -/* - * RD2WR (R/W) - * - * Description: DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL - * LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL. - * Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. - * Unit: Clocks. Where: - * WL = write latency - * BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - * RL = read latency = CAS latency - * WR_PREAMBLE = write preamble. This is unique to DDR4. - * For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - * Value After Reset: 0x6 - * Exists: Always - */ -#define DDRCTL_DRAMTMG2_RD2WR_MASK (0x1F00U) -#define DDRCTL_DRAMTMG2_RD2WR_SHIFT (8U) -#define DDRCTL_DRAMTMG2_RD2WR_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG2_RD2WR_SHIFT) & DDRCTL_DRAMTMG2_RD2WR_MASK) -#define DDRCTL_DRAMTMG2_RD2WR_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG2_RD2WR_MASK) >> DDRCTL_DRAMTMG2_RD2WR_SHIFT) - -/* - * WR2RD (R/W) - * - * Description: DDR4: WL + BL/2 + tWTR_L Others: WL + BL/2 + tWTR - * In DDR4, minimum time from write command to read command for same bank group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and global constraints. - * Unit: Clocks. Where: - * WL = write latency - * BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - * tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification. - * tWTR = internal write to read command delay. This comes directly from the SDRAM specification. - * Add one extra cycle for LPDDR2/LPDDR3 operation. - * For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - * Value After Reset: 0xd - * Exists: Always - */ -#define DDRCTL_DRAMTMG2_WR2RD_MASK (0x3FU) -#define DDRCTL_DRAMTMG2_WR2RD_SHIFT (0U) -#define DDRCTL_DRAMTMG2_WR2RD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG2_WR2RD_SHIFT) & DDRCTL_DRAMTMG2_WR2RD_MASK) -#define DDRCTL_DRAMTMG2_WR2RD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG2_WR2RD_MASK) >> DDRCTL_DRAMTMG2_WR2RD_SHIFT) - -/* Bitfield definition for register: DRAMTMG3 */ -/* - * T_MRD (R/W) - * - * Description: tMRD: Cycles between load mode commands. If MEMC_DDR3_OR_4 = 0, this parameter is also used to define the cycles between load mode command and following non-load mode command. - * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. - * If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DRAMTMG3_T_MRD_MASK (0x3F000UL) -#define DDRCTL_DRAMTMG3_T_MRD_SHIFT (12U) -#define DDRCTL_DRAMTMG3_T_MRD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MRD_SHIFT) & DDRCTL_DRAMTMG3_T_MRD_MASK) -#define DDRCTL_DRAMTMG3_T_MRD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MRD_MASK) >> DDRCTL_DRAMTMG3_T_MRD_SHIFT) - -/* - * T_MOD (R/W) - * - * Description: tMOD: Present if MEMC_DDR3_OR_4 = 1. Cycles between load mode command and following non-load mode command. This is required to be programmed even when a design that supports DDR3/4 is running in DDR2 mode. - * If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead - * Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip - * Value After Reset: "(MEMC_DDR3_EN==1 || MEMC_DDR4_EN==1 ) ? 0xc : 0x0" - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 - */ -#define DDRCTL_DRAMTMG3_T_MOD_MASK (0x3FFU) -#define DDRCTL_DRAMTMG3_T_MOD_SHIFT (0U) -#define DDRCTL_DRAMTMG3_T_MOD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG3_T_MOD_SHIFT) & DDRCTL_DRAMTMG3_T_MOD_MASK) -#define DDRCTL_DRAMTMG3_T_MOD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG3_T_MOD_MASK) >> DDRCTL_DRAMTMG3_T_MOD_SHIFT) - -/* Bitfield definition for register: DRAMTMG4 */ -/* - * T_RCD (R/W) - * - * Description: tRCD - tAL: Minimum time from activate to read or write command to same bank. - * For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD - tAL)/2) and round it up to the next integer value. - * Minimum value allowed for this register is 1, which implies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. - * Unit: Clocks. - * Value After Reset: 0x5 - * Exists: Always - */ -#define DDRCTL_DRAMTMG4_T_RCD_MASK (0x1F000000UL) -#define DDRCTL_DRAMTMG4_T_RCD_SHIFT (24U) -#define DDRCTL_DRAMTMG4_T_RCD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RCD_SHIFT) & DDRCTL_DRAMTMG4_T_RCD_MASK) -#define DDRCTL_DRAMTMG4_T_RCD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RCD_MASK) >> DDRCTL_DRAMTMG4_T_RCD_SHIFT) - -/* - * T_CCD (R/W) - * - * Description: DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads - * or two writes. - * For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. - * Unit: clocks. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DRAMTMG4_T_CCD_MASK (0x70000UL) -#define DDRCTL_DRAMTMG4_T_CCD_SHIFT (16U) -#define DDRCTL_DRAMTMG4_T_CCD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_CCD_SHIFT) & DDRCTL_DRAMTMG4_T_CCD_MASK) -#define DDRCTL_DRAMTMG4_T_CCD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_CCD_MASK) >> DDRCTL_DRAMTMG4_T_CCD_SHIFT) - -/* - * T_RRD (R/W) - * - * Description: DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank group. Others: tRRD: Minimum time between activates from bank - * "a" to bank "b" - * For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. - * Unit: Clocks. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DRAMTMG4_T_RRD_MASK (0xF00U) -#define DDRCTL_DRAMTMG4_T_RRD_SHIFT (8U) -#define DDRCTL_DRAMTMG4_T_RRD_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RRD_SHIFT) & DDRCTL_DRAMTMG4_T_RRD_MASK) -#define DDRCTL_DRAMTMG4_T_RRD_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RRD_MASK) >> DDRCTL_DRAMTMG4_T_RRD_SHIFT) - -/* - * T_RP (R/W) - * - * Description: tRP: Minimum time from precharge to activate of same bank. - * For configurations with MEMC_FREQ_RATIO=2, program this to (tRP/2 + 1). No round up of the fraction. - * Unit: Clocks. - * Value After Reset: 0x5 - * Exists: Always - */ -#define DDRCTL_DRAMTMG4_T_RP_MASK (0x1FU) -#define DDRCTL_DRAMTMG4_T_RP_SHIFT (0U) -#define DDRCTL_DRAMTMG4_T_RP_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG4_T_RP_SHIFT) & DDRCTL_DRAMTMG4_T_RP_MASK) -#define DDRCTL_DRAMTMG4_T_RP_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG4_T_RP_MASK) >> DDRCTL_DRAMTMG4_T_RP_SHIFT) - -/* Bitfield definition for register: DRAMTMG5 */ -/* - * T_CKSRX (R/W) - * - * Description: This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. - * Recommended settings: - * mDDR: 1 - * LPDDR2: 2 - * LPDDR3: 2 - * DDR2: 1 - * DDR3: tCKSRX - * DDR4: tCKSRX - * For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. - * Value After Reset: 0x5 - * Exists: Always - */ -#define DDRCTL_DRAMTMG5_T_CKSRX_MASK (0xF000000UL) -#define DDRCTL_DRAMTMG5_T_CKSRX_SHIFT (24U) -#define DDRCTL_DRAMTMG5_T_CKSRX_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRX_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRX_MASK) -#define DDRCTL_DRAMTMG5_T_CKSRX_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRX_MASK) >> DDRCTL_DRAMTMG5_T_CKSRX_SHIFT) - -/* - * T_CKSRE (R/W) - * - * Description: This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. - * Recommended settings: - * mDDR: 0 - * LPDDR2: 2 - * LPDDR3: 2 - * DDR2: 1 - * DDR3: max (10 ns, 5 tCK) - * DDR4: max (10 ns, 5 tCK) - * For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. - * Value After Reset: 0x5 - * Exists: Always - */ -#define DDRCTL_DRAMTMG5_T_CKSRE_MASK (0xF0000UL) -#define DDRCTL_DRAMTMG5_T_CKSRE_SHIFT (16U) -#define DDRCTL_DRAMTMG5_T_CKSRE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKSRE_SHIFT) & DDRCTL_DRAMTMG5_T_CKSRE_MASK) -#define DDRCTL_DRAMTMG5_T_CKSRE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKSRE_MASK) >> DDRCTL_DRAMTMG5_T_CKSRE_SHIFT) - -/* - * T_CKESR (R/W) - * - * Description: Minimum CKE low width for Self refresh entry to exit timing im memory clock cycles. - * Recommended settings: - * mDDR: tRFC - * LPDDR2: tCKESR - * LPDDR3: tCKESR - * DDR2: tCKE - * DDR3: tCKE + 1 - * DDR4: tCKE + 1 - * For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next integer. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DRAMTMG5_T_CKESR_MASK (0x3F00U) -#define DDRCTL_DRAMTMG5_T_CKESR_SHIFT (8U) -#define DDRCTL_DRAMTMG5_T_CKESR_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKESR_SHIFT) & DDRCTL_DRAMTMG5_T_CKESR_MASK) -#define DDRCTL_DRAMTMG5_T_CKESR_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKESR_MASK) >> DDRCTL_DRAMTMG5_T_CKESR_SHIFT) - -/* - * T_CKE (R/W) - * - * Description: Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - * Non-LPDDR2/non-LPDDR3 designs: Set this to tCKE value. - * For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to the next integer value. - * Unit: Clocks. - * Value After Reset: 0x3 - * Exists: Always - */ -#define DDRCTL_DRAMTMG5_T_CKE_MASK (0x1FU) -#define DDRCTL_DRAMTMG5_T_CKE_SHIFT (0U) -#define DDRCTL_DRAMTMG5_T_CKE_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG5_T_CKE_SHIFT) & DDRCTL_DRAMTMG5_T_CKE_MASK) -#define DDRCTL_DRAMTMG5_T_CKE_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG5_T_CKE_MASK) >> DDRCTL_DRAMTMG5_T_CKE_SHIFT) - -/* Bitfield definition for register: DRAMTMG8 */ -/* - * T_XS_DLL_X32 (R/W) - * - * Description: tXSDLL: Exit Self Refresh to commands requiring a locked DLL. - * For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. - * Unit: Multiples of 32 clocks. - * Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. - * Value After Reset: 0x44 - * Exists: Always - */ -#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK (0x7F00U) -#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT (8U) -#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK) -#define DDRCTL_DRAMTMG8_T_XS_DLL_X32_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_DLL_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_DLL_X32_SHIFT) - -/* - * T_XS_X32 (R/W) - * - * Description: tXS: Exit Self Refresh to commands not requiring a locked DLL. - * For configurations with MEMC_FREQ_RATIO=2, program this to the above value divided by 2 and round up to next integer value. - * Unit: Multiples of 32 clocks. - * Note: In LPDDR2/LPDDR3/Mobile DDR mode, t_xs_x32 and t_xs_dll_x32 must be set the same values derived from tXSR. - * Value After Reset: 0x5 - * Exists: Always - */ -#define DDRCTL_DRAMTMG8_T_XS_X32_MASK (0x7FU) -#define DDRCTL_DRAMTMG8_T_XS_X32_SHIFT (0U) -#define DDRCTL_DRAMTMG8_T_XS_X32_SET(x) (((uint32_t)(x) << DDRCTL_DRAMTMG8_T_XS_X32_SHIFT) & DDRCTL_DRAMTMG8_T_XS_X32_MASK) -#define DDRCTL_DRAMTMG8_T_XS_X32_GET(x) (((uint32_t)(x) & DDRCTL_DRAMTMG8_T_XS_X32_MASK) >> DDRCTL_DRAMTMG8_T_XS_X32_SHIFT) - -/* Bitfield definition for register: ZQCTL0 */ -/* - * DIS_AUTO_ZQ (R/W) - * - * Description: - * 1 - Disable uMCTL2 generation of ZQCS command. Register reg_ddrc_zq_calib_short can be used instead to control ZQ calibration commands. - * 0 - Internally generate ZQCS commands based on ZQCTL1.t_zq_short_interval_x1024. - * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. - * Value After Reset: 0x0 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK (0x80000000UL) -#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT (31U) -#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK) -#define DDRCTL_ZQCTL0_DIS_AUTO_ZQ_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_AUTO_ZQ_MASK) >> DDRCTL_ZQCTL0_DIS_AUTO_ZQ_SHIFT) - -/* - * DIS_SRX_ZQCL (R/W) - * - * Description: - * 1 - Disable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. - * 0 - Enable issuing of ZQCL command at Self-Refresh exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 mode. - * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. - * Value After Reset: 0x0 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK (0x40000000UL) -#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT (30U) -#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK) -#define DDRCTL_ZQCTL0_DIS_SRX_ZQCL_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_DIS_SRX_ZQCL_MASK) >> DDRCTL_ZQCTL0_DIS_SRX_ZQCL_SHIFT) - -/* - * ZQ_RESISTOR_SHARED (R/W) - * - * Description: - * 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS timing met between commands so that commands to different ranks do not overlap. - * 0 - ZQ resistor is not shared. - * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. - * Value After Reset: 0x0 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK (0x20000000UL) -#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT (29U) -#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK) -#define DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_MASK) >> DDRCTL_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT) - -/* - * T_ZQ_LONG_NOP (R/W) - * - * Description: tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to SDRAM. - * For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next integer value. - * LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer value. - * Unit: Clock cycles. - * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. - * Value After Reset: 0x200 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK (0x3FF0000UL) -#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT (16U) -#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK) -#define DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_LONG_NOP_SHIFT) - -/* - * T_ZQ_SHORT_NOP (R/W) - * - * Description: tZQCS: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to SDRAM. - * For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to the next integer value. Unit: Clock cycles. - * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. - * Value After Reset: 0x40 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK (0x3FFU) -#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT (0U) -#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK) -#define DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_MASK) >> DDRCTL_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT) - -/* Bitfield definition for register: ZQCTL1 */ -/* - * T_ZQ_SHORT_INTERVAL_X1024 (R/W) - * - * Description: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3/DDR4/LPDDR2/LPDDR3 devices. - * Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. - * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 devices. - * Value After Reset: 0x100 - * Exists: MEMC_DDR3==1 || MEMC_DDR4==1 || MEMC_LPDDR2==1 - */ -#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK (0xFFFFFUL) -#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT (0U) -#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SET(x) (((uint32_t)(x) << DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) -#define DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_GET(x) (((uint32_t)(x) & DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK) >> DDRCTL_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT) - -/* Bitfield definition for register: ZQSTAT */ -/* - * ZQ_RESET_BUSY (R) - * - * Description: SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high. - * 0 - Indicates that the SoC core can initiate a ZQ Reset operation - * 1 - Indicates that ZQ Reset operation is in progress - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK (0x1U) -#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT (0U) -#define DDRCTL_ZQSTAT_ZQ_RESET_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_ZQSTAT_ZQ_RESET_BUSY_MASK) >> DDRCTL_ZQSTAT_ZQ_RESET_BUSY_SHIFT) - -/* Bitfield definition for register: DFITMG0 */ -/* - * DFI_T_CTRL_DELAY (R/W) - * - * Description: Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, depending on the PHY, it may be necessary to increment this parameter by 1. This is to compensate for the extra cycle of latency through the RDIMM - * Value After Reset: 0x7 - * Exists: Always - */ -#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK (0x1F000000UL) -#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT (24U) -#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK) -#define DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_MASK) >> DDRCTL_DFITMG0_DFI_T_CTRL_DELAY_SHIFT) - -/* - * DFI_RDDATA_USE_SDR (R/W) - * - * Description: Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - * 0 in terms of HDR clock cycles - * 1 in terms of SDR clock cycles - * Refer to PHY specification for correct value. - * Value After Reset: 0x0 - * Exists: MEMC_FREQ_RATIO==2 - */ -#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK (0x800000UL) -#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT (23U) -#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK) -#define DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT) - -/* - * DFI_T_RDDATA_EN (R/W) - * - * Description: Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. - * This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle of latency through the RDIMM. - * Unit: Clocks - * Value After Reset: 0x2 - * Exists: Always - */ -#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK (0x3F0000UL) -#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT (16U) -#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK) -#define DDRCTL_DFITMG0_DFI_T_RDDATA_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_T_RDDATA_EN_MASK) >> DDRCTL_DFITMG0_DFI_T_RDDATA_EN_SHIFT) - -/* - * DFI_WRDATA_USE_SDR (R/W) - * - * Description: Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or HDR clock cycles - * 0 in terms of HDR clock cycles - * 1 in terms of SDR clock cycles - * Refer to PHY specification for correct value. - * Value After Reset: 0x0 - * Exists: MEMC_FREQ_RATIO==2 - */ -#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK (0x8000U) -#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT (15U) -#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK) -#define DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_MASK) >> DDRCTL_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT) - -/* - * DFI_TPHY_WRDATA (R/W) - * - * Description: Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8. - * Unit: Clocks - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK (0x3F00U) -#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT (8U) -#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK) -#define DDRCTL_DFITMG0_DFI_TPHY_WRDATA_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRDATA_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRDATA_SHIFT) - -/* - * DFI_TPHY_WRLAT (R/W) - * - * Description: Write latency - * Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. The minimum supported value is as follows: - * 0 for configurations with MEMC_WL0 = 1 - * 1 for configurations with MEMC_WL0 = 0 - * Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency through the RDIMM. - * Value After Reset: 0x2 - * Exists: Always - */ -#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK (0x3FU) -#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT (0U) -#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK) -#define DDRCTL_DFITMG0_DFI_TPHY_WRLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG0_DFI_TPHY_WRLAT_MASK) >> DDRCTL_DFITMG0_DFI_TPHY_WRLAT_SHIFT) - -/* Bitfield definition for register: DFITMG1 */ -/* - * DFI_T_WRDATA_DELAY (R/W) - * - * Description: Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. - * Unit: Clocks - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK (0x1F0000UL) -#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT (16U) -#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK) -#define DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_MASK) >> DDRCTL_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT) - -/* - * DFI_T_DRAM_CLK_DISABLE (R/W) - * - * Description: Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY- DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK (0xF00U) -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT (8U) -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT) - -/* - * DFI_T_DRAM_CLK_ENABLE (R/W) - * - * Description: Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK (0xFU) -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT (0U) -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) -#define DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK) >> DDRCTL_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT) - -/* Bitfield definition for register: DFILPCFG0 */ -/* - * DFI_TLP_RESP (R/W) - * - * Description: Setting for DFI's tlp_resp time. - * Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 specification onwards, recommends using a fixed - * value of 7 always. - * Value After Reset: 0x7 - * Exists: Always - */ -#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK (0xF000000UL) -#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT (24U) -#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK) -#define DDRCTL_DFILPCFG0_DFI_TLP_RESP_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_TLP_RESP_MASK) >> DDRCTL_DFILPCFG0_DFI_TLP_RESP_SHIFT) - -/* - * DFI_LP_WAKEUP_SR (R/W) - * - * Description: Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. - * Determines the DFI's tlp_wakeup time: - * 0x0 - 16 cycles - * 0x1 - 32 cycles - * 0x2 - 64 cycles - * 0x3 - 128 cycles - * 0x4 - 256 cycles - * 0x5 - 512 cycles - * 0x6 - 1024 cycles - * 0x7 - 2048 cycles - * 0x8 - 4096 cycles - * 0x9 - 8192 cycles - * 0xA - 16384 cycles - * 0xB - 32768 cycles - * 0xC - 65536 cycles - * 0xD - 131072 cycles - * 0xE - 262144 cycles - * 0xF - Unlimited Value After Reset: 0x0 Exists: Always - */ -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK (0xF000U) -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT (12U) -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT) - -/* - * DFI_LP_EN_SR (R/W) - * - * Description: Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - * 0 - Disabled - * 1 - Enabled - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK (0x100U) -#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT (8U) -#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK) -#define DDRCTL_DFILPCFG0_DFI_LP_EN_SR_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_SR_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_SR_SHIFT) - -/* - * DFI_LP_WAKEUP_PD (R/W) - * - * Description: Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. - * Determines the DFI's tlp_wakeup time: - * 0x0 - 16 cycles - * 0x1 - 32 cycles - * 0x2 - 64 cycles - * 0x3 - 128 cycles - * 0x4 - 256 cycles - * 0x5 - 512 cycles - * 0x6 - 1024 cycles - * 0x7 - 2048 cycles - * 0x8 - 4096 cycles - * 0x9 - 8192 cycles - * 0xA - 16384 cycles - * 0xB - 32768 cycles - * 0xC - 65536 cycles - * 0xD - 131072 cycles - * 0xE - 262144 cycles - * 0xF - Unlimited Value After Reset: 0x0 Exists: Always - */ -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK (0xF0U) -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT (4U) -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) -#define DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT) - -/* - * DFI_LP_EN_PD (R/W) - * - * Description: Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - * 0 - Disabled - * 1 - Enabled - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK (0x1U) -#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT (0U) -#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SET(x) (((uint32_t)(x) << DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK) -#define DDRCTL_DFILPCFG0_DFI_LP_EN_PD_GET(x) (((uint32_t)(x) & DDRCTL_DFILPCFG0_DFI_LP_EN_PD_MASK) >> DDRCTL_DFILPCFG0_DFI_LP_EN_PD_SHIFT) - -/* Bitfield definition for register: DFIUPD0 */ -/* - * DIS_AUTO_CTRLUPD (R/W) - * - * Description: When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The core must issue the dfi_ctrlupd_req signal using register reg_ddrc_ctrlupd. This register field is changeable on the fly. - * When '0', uMCTL2 issues dfi_ctrlupd_req periodically. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK (0x80000000UL) -#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT (31U) -#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK) -#define DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_MASK) >> DDRCTL_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT) - -/* - * DFI_T_CTRLUP_MAX (R/W) - * - * Description: Specifies the maximum number of clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. - * Unit: Clocks - * Value After Reset: 0x40 - * Exists: Always - */ -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK (0x3FF0000UL) -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT (16U) -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT) - -/* - * DFI_T_CTRLUP_MIN (R/W) - * - * Description: Specifies the minimum number of clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this variable is 0x3. - * Unit: Clocks - * Value After Reset: 0x3 - * Exists: Always - */ -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK (0x3FFU) -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT (0U) -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) -#define DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_MASK) >> DDRCTL_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT) - -/* Bitfield definition for register: DFIUPD1 */ -/* - * DFI_T_CTRLUPD_INTERVAL_MIN_X1024 (R/W) - * - * Description: This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the uMCTL2 is idle. - * Unit: 1024 clocks Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK (0xFF0000UL) -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT (16U) -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT) - -/* - * DFI_T_CTRLUPD_INTERVAL_MAX_X1024 (R/W) - * - * Description: This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in case of data capture errors. - * Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. - * Unit: 1024 clocks Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK (0xFFU) -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT (0U) -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) -#define DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK) >> DDRCTL_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT) - -/* Bitfield definition for register: DFIUPD2 */ -/* - * DFI_PHYUPD_EN (R/W) - * - * Description: Enables the support for acknowledging PHY- initiated updates: - * 0 - Disabled - * 1 - Enabled - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK (0x80000000UL) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT (31U) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_EN_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_EN_SHIFT) - -/* - * DFI_PHYUPD_TYPE1 (R/W) - * - * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b01. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK (0xFFF0000UL) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT (16U) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE1_SHIFT) - -/* - * DFI_PHYUPD_TYPE0 (R/W) - * - * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b00. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK (0xFFFU) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT (0U) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) -#define DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_MASK) >> DDRCTL_DFIUPD2_DFI_PHYUPD_TYPE0_SHIFT) - -/* Bitfield definition for register: DFIUPD3 */ -/* - * DFI_PHYUPD_TYPE3 (R/W) - * - * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b11. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK (0xFFF0000UL) -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT (16U) -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE3_SHIFT) - -/* - * DFI_PHYUPD_TYPE2 (R/W) - * - * Description: Specifies the maximum number of DFI clock cycles that the dfi_phyupd_req signal may remain asserted after the assertion of the dfi_phyupd_ack signal for dfi_phyupd_type = 2'b10. The dfi_phyupd_req signal may de-assert at any cycle after the assertion of the dfi_phyupd_ack signal. - * Value After Reset: 0x10 - * Exists: Always - */ -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK (0xFFFU) -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT (0U) -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SET(x) (((uint32_t)(x) << DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) -#define DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_GET(x) (((uint32_t)(x) & DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_MASK) >> DDRCTL_DFIUPD3_DFI_PHYUPD_TYPE2_SHIFT) - -/* Bitfield definition for register: DFIMISC */ -/* - * DFI_INIT_COMPLETE_EN (R/W) - * - * Description: PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK (0x1U) -#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT (0U) -#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SET(x) (((uint32_t)(x) << DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK) -#define DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_GET(x) (((uint32_t)(x) & DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_MASK) >> DDRCTL_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT) - -/* Bitfield definition for register: DFITMG2 */ -/* - * DFI_TPHY_RDCSLAT (R/W) - * - * Description: Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. - * Value After Reset: 0x2 - * Exists: Always - */ -#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK (0x3F00U) -#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT (8U) -#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK) -#define DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT) - -/* - * DFI_TPHY_WRCSLAT (R/W) - * - * Description: Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs_n signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. The minimum supported value is as follows: - * 0 for configurations with MEMC_WL0 = 1 - * 1 for configurations with MEMC_WL0 = 0 Refer to PHY specification for correct value. Value After Reset: 0x2 - * Exists: Always - */ -#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK (0x3FU) -#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT (0U) -#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SET(x) (((uint32_t)(x) << DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK) -#define DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_GET(x) (((uint32_t)(x) & DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_MASK) >> DDRCTL_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT) - -/* Bitfield definition for register: ADDRMAP0 */ -/* - * ADDRMAP_CS_BIT0 (R/W) - * - * Description: Selects the HIF address bit used as rank address bit 0. - * Valid Range: 0 to 27, and 31 - * Internal Base: 6 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 31, rank address bit 0 is set to 0. - * Value After Reset: 0x0 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK (0x1FU) -#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT (0U) -#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) -#define DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_MASK) >> DDRCTL_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT) - -/* Bitfield definition for register: ADDRMAP1 */ -/* - * ADDRMAP_BANK_B2 (R/W) - * - * Description: Selects the HIF address bit used as bank address bit 2. - * Valid Range: 0 to 29 and 31 - * Internal Base: 4 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 31, bank address bit 2 is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK (0x1F0000UL) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT (16U) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT) - -/* - * ADDRMAP_BANK_B1 (R/W) - * - * Description: Selects the HIF address bits used as bank address bit 1. - * Valid Range: 0 to 30 - * Internal Base: 3 - * The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK (0x1F00U) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT (8U) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT) - -/* - * ADDRMAP_BANK_B0 (R/W) - * - * Description: Selects the HIF address bits used as bank address bit 0. - * Valid Range: 0 to 30 - * Internal Base: 2 - * The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK (0x1FU) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT (0U) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK) -#define DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_MASK) >> DDRCTL_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT) - -/* Bitfield definition for register: ADDRMAP2 */ -/* - * ADDRMAP_COL_B5 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7, and 15 - * Internal Base: 5 - * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK (0xF000000UL) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT (24U) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B5_SHIFT) - -/* - * ADDRMAP_COL_B4 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7, and 15 - * Internal Base: 4 - * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK (0xF0000UL) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT (16U) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B4_SHIFT) - -/* - * ADDRMAP_COL_B3 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 5 (if MEMC_BURST_LENGTH = 4) or 6 (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7 - * Internal Base: 3 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK (0xF00U) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT (8U) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B3_SHIFT) - -/* - * ADDRMAP_COL_B2 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 2 (if MEMC_BURST_LENGTH = 4) or 3 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 3 (if MEMC_BURST_LENGTH = 4) or 4 (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 4 (if MEMC_BURST_LENGTH = 4) or 5 (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7 - * Internal Base: 2 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK (0xFU) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT (0U) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK) -#define DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_MASK) >> DDRCTL_ADDRMAP2_ADDRMAP_COL_B2_SHIFT) - -/* Bitfield definition for register: ADDRMAP3 */ -/* - * ADDRMAP_COL_B9 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8) - * Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). - * (Column address bit 11 in LPDDR2/LPDDR3 mode) Quarter bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if - * MEMC_BURST_LENGTH = 4) or UNUSED (if - * MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7, and 15 - * Internal Base: 9 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, this column address bit is set to 0. - * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. - * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK (0xF000000UL) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT (24U) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B9_SHIFT) - -/* - * ADDRMAP_COL_B8 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7, and 15 - * Internal Base: 8 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, this column address bit is set to 0. - * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. - * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK (0xF0000UL) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT (16U) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B8_SHIFT) - -/* - * ADDRMAP_COL_B7 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 9 (if MEMC_BURST_LENGTH = 4) or 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7, and 15 - * Internal Base: 7 - * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. - * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge and hence no source address bit can be mapped to column address bit 10. - * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK (0xF00U) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT (8U) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B7_SHIFT) - -/* - * ADDRMAP_COL_B6 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 6 (if MEMC_BURST_LENGTH = 4) or 7 (if - * MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 7 (if MEMC_BURST_LENGTH = 4) or 8 (if MEMC_BURST_LENGTH = 8). - * Quarter bus width mode: Selects the HIF address bit used as column address bit 8 (if MEMC_BURST_LENGTH = 4) or 9 (if MEMC_BURST_LENGTH = 8). - * Valid Range: 0 to 7, and 15 - * Internal Base: 6 - * The selected HIF address bit is determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK (0xFU) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT (0U) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK) -#define DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_MASK) >> DDRCTL_ADDRMAP3_ADDRMAP_COL_B6_SHIFT) - -/* Bitfield definition for register: ADDRMAP4 */ -/* - * ADDRMAP_COL_B11 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8). - * Half bus width mode: Unused. To make it unused, this should be tied to 4'hF. - * Quarter bus width mode: Unused. To make it unused, this must be tied to 4'hF. - * Valid Range: 0 to 7, and 15 - * Internal Base: 11 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, this column address bit is set to 0. - * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. - * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK (0xF00U) -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT (8U) -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK) -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B11_SHIFT) - -/* - * ADDRMAP_COL_B10 (R/W) - * - * Description: Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 8). - * Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) (if MEMC_BURST_LENGTH = 4) or UNUSED (if MEMC_BURST_LENGTH = 8) - * Quarter bus width mode: UNUSED. To make it unused, this must be tied to 4'hF. - * Valid Range: 0 to 7, and 15 - * Internal Base: 10 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, this column address bit is set to 0. - * Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. - * In LPDDR2/LPDDR3, there is a dedicated bit for auto- precharge in the CA bus and hence column bit 10 is used. Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK (0xFU) -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT (0U) -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK) -#define DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_MASK) >> DDRCTL_ADDRMAP4_ADDRMAP_COL_B10_SHIFT) - -/* Bitfield definition for register: ADDRMAP5 */ -/* - * ADDRMAP_ROW_B11 (R/W) - * - * Description: Selects the HIF address bit used as row address bit 11. - * Valid Range: 0 to 11, and 15 - * Internal Base: 17 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, row address bit 11 is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK (0xF000000UL) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT (24U) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT) - -/* - * ADDRMAP_ROW_B2_10 (R/W) - * - * Description: Selects the HIF address bits used as row address bits 2 to 10. - * Valid Range: 0 to 11 - * Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row - * address bit 10) - * The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK (0xF0000UL) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT (16U) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT) - -/* - * ADDRMAP_ROW_B1 (R/W) - * - * Description: Selects the HIF address bits used as row address bit 1. - * Valid Range: 0 to 11 - * Internal Base: 7 - * The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK (0xF00U) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT (8U) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT) - -/* - * ADDRMAP_ROW_B0 (R/W) - * - * Description: Selects the HIF address bits used as row address bit 0. - * Valid Range: 0 to 11 - * Internal Base: 6 - * The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK (0xFU) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT (0U) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK) -#define DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_MASK) >> DDRCTL_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT) - -/* Bitfield definition for register: ADDRMAP6 */ -/* - * ADDRMAP_ROW_B15 (R/W) - * - * Description: Selects the HIF address bit used as row address bit 15. - * Valid Range: 0 to 11, and 15 - * Internal Base: 21 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, row address bit 15 is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK (0xF000000UL) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT (24U) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT) - -/* - * ADDRMAP_ROW_B14 (R/W) - * - * Description: Selects the HIF address bit used as row address bit 14. - * Valid Range: 0 to 11, and 15 - * Internal Base: 20 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, row address bit 14 is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK (0xF0000UL) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT (16U) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT) - -/* - * ADDRMAP_ROW_B13 (R/W) - * - * Description: Selects the HIF address bit used as row address bit 13. - * Valid Range: 0 to 11, and 15 - * Internal Base: 19 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, row address bit 13 is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK (0xF00U) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT (8U) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT) - -/* - * ADDRMAP_ROW_B12 (R/W) - * - * Description: Selects the HIF address bit used as row address bit 12. - * Valid Range: 0 to 11, and 15 - * Internal Base: 18 - * The selected HIF address bit is determined by adding the internal base to the value of this field. - * If set to 15, row address bit 12 is set to 0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK (0xFU) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT (0U) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SET(x) (((uint32_t)(x) << DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK) -#define DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_GET(x) (((uint32_t)(x) & DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_MASK) >> DDRCTL_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT) - -/* Bitfield definition for register: ODTCFG */ -/* - * WR_ODT_HOLD (R/W) - * - * Description: Cycles to hold ODT for a write command. The minimum supported value is 2. DDR2/DDR3/DDR4 - * BL8 - 0x6 - * BL4 - 0x4 - * LPDDR3 - RU(tDQSSmax/tCK) + 4 - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_ODTCFG_WR_ODT_HOLD_MASK (0xF000000UL) -#define DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT (24U) -#define DDRCTL_ODTCFG_WR_ODT_HOLD_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK) -#define DDRCTL_ODTCFG_WR_ODT_HOLD_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_WR_ODT_HOLD_SHIFT) - -/* - * WR_ODT_DELAY (R/W) - * - * Description: The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. - * Recommended values: - * DDR2 - * If (CWL + AL < 3), then 0. - * If (CWL + AL >= 3), then (CWL + AL - 3) DDR3 - 0 - * DDR4 - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) - * LPDDR3 - (CWL - RU(tODToffmax/tCK)) - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_ODTCFG_WR_ODT_DELAY_MASK (0x1F0000UL) -#define DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT (16U) -#define DDRCTL_ODTCFG_WR_ODT_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK) -#define DDRCTL_ODTCFG_WR_ODT_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_WR_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_WR_ODT_DELAY_SHIFT) - -/* - * RD_ODT_HOLD (R/W) - * - * Description: Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2/DDR3 - * BL8 - 0x6 - * BL4 - 0x4 - * DDR4 - 0x6, but needs to be reduced to 0x5 in CAL mode to avoid overlap of read and write ODT LPDDR3 - RU(tDQSCKmax/tCK) + 4 + 1 - * Value After Reset: 0x4 - * Exists: Always - */ -#define DDRCTL_ODTCFG_RD_ODT_HOLD_MASK (0xF00U) -#define DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT (8U) -#define DDRCTL_ODTCFG_RD_ODT_HOLD_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK) -#define DDRCTL_ODTCFG_RD_ODT_HOLD_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_HOLD_MASK) >> DDRCTL_ODTCFG_RD_ODT_HOLD_SHIFT) - -/* - * RD_ODT_DELAY (R/W) - * - * Description: The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. ODT is used only in DDR2, DDR3, DDR4 and LPDDR3 designs. - * Recommended values: - * DDR2 - * If (CL + AL < 4), then 0. - * If (CL + AL >= 4), then (CL + AL - 4) DDR3 - * (CL - CWL) DDR4 - * If CAL mode is enabled, CL - CWL + DFITMG1.dfi_t_cmd_lat - * If CAL mode is not enabled, CL - CWL -1, or 0 if CL - CWL < 1 - * LPDDR3, MEMC_FREQ_RATIO=2 - * CL - RU(tODToffmax/tCK)) Value After Reset: 0x0 Exists: Always - */ -#define DDRCTL_ODTCFG_RD_ODT_DELAY_MASK (0x7CU) -#define DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT (2U) -#define DDRCTL_ODTCFG_RD_ODT_DELAY_SET(x) (((uint32_t)(x) << DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK) -#define DDRCTL_ODTCFG_RD_ODT_DELAY_GET(x) (((uint32_t)(x) & DDRCTL_ODTCFG_RD_ODT_DELAY_MASK) >> DDRCTL_ODTCFG_RD_ODT_DELAY_SHIFT) - -/* Bitfield definition for register: ODTMAP */ -/* - * RANK1_RD_ODT (R/W) - * - * Description: Indicates which remote ODTs must be turned on during a read from rank 1. - * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. - * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. - * For each rank, set its bit to 1 to enable its ODT. - * Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_ODTMAP_RANK1_RD_ODT_MASK (0xF000U) -#define DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT (12U) -#define DDRCTL_ODTMAP_RANK1_RD_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK) -#define DDRCTL_ODTMAP_RANK1_RD_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_RD_ODT_SHIFT) - -/* - * RANK1_WR_ODT (R/W) - * - * Description: Indicates which remote ODTs must be turned on during a write to rank 1. - * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. - * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. - * For each rank, set its bit to 1 to enable its ODT. - * Present only in configurations that have 2 or more ranks Value After Reset: "(MEMC_NUM_RANKS>1) ? 0x2 : 0x0" Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_ODTMAP_RANK1_WR_ODT_MASK (0xF00U) -#define DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT (8U) -#define DDRCTL_ODTMAP_RANK1_WR_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK) -#define DDRCTL_ODTMAP_RANK1_WR_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK1_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK1_WR_ODT_SHIFT) - -/* - * RANK0_RD_ODT (R/W) - * - * Description: Indicates which remote ODTs must be turned on during a read from rank 0. - * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. - * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. - * For each rank, set its bit to 1 to enable its ODT. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_ODTMAP_RANK0_RD_ODT_MASK (0xF0U) -#define DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT (4U) -#define DDRCTL_ODTMAP_RANK0_RD_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK) -#define DDRCTL_ODTMAP_RANK0_RD_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_RD_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_RD_ODT_SHIFT) - -/* - * RANK0_WR_ODT (R/W) - * - * Description: Indicates which remote ODTs must be turned on during a write to rank 0. - * Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. - * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. - * For each rank, set its bit to 1 to enable its ODT. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_ODTMAP_RANK0_WR_ODT_MASK (0xFU) -#define DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT (0U) -#define DDRCTL_ODTMAP_RANK0_WR_ODT_SET(x) (((uint32_t)(x) << DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK) -#define DDRCTL_ODTMAP_RANK0_WR_ODT_GET(x) (((uint32_t)(x) & DDRCTL_ODTMAP_RANK0_WR_ODT_MASK) >> DDRCTL_ODTMAP_RANK0_WR_ODT_SHIFT) - -/* Bitfield definition for register: SCHED */ -/* - * RDWR_IDLE_GAP (R/W) - * - * Description: When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty. - * The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store. - * When prefer write over read is set this is reversed. - * 0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - * FOR PERFORMANCE ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_SCHED_RDWR_IDLE_GAP_MASK (0x7F000000UL) -#define DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT (24U) -#define DDRCTL_SCHED_RDWR_IDLE_GAP_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK) -#define DDRCTL_SCHED_RDWR_IDLE_GAP_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_RDWR_IDLE_GAP_MASK) >> DDRCTL_SCHED_RDWR_IDLE_GAP_SHIFT) - -/* - * GO2CRITICAL_HYSTERESIS (R/W) - * - * Description: UNUSED Value After Reset: 0x0 Exists: Always - */ -#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK (0xFF0000UL) -#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT (16U) -#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK) -#define DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_MASK) >> DDRCTL_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT) - -/* - * LPR_NUM_ENTRIES (R/W) - * - * Description: Number of entries in the low priority transaction store is this value + 1. - * (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. - * Setting this to maximum value allocates all entries to low priority transaction store. - * Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store. - * Note: In ECC configurations, the numbers of write and low priority read credits issued is one less than in the non-ECC case. One entry each is reserved in the write and low- priority read CAMs for storing the RMW requests arising out of single bit error correction RMW operation. - * Value After Reset: "MEMC_NO_OF_ENTRY/2" - * Exists: Always - */ -#define DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK (0x3F00U) -#define DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT (8U) -#define DDRCTL_SCHED_LPR_NUM_ENTRIES_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK) -#define DDRCTL_SCHED_LPR_NUM_ENTRIES_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_LPR_NUM_ENTRIES_MASK) >> DDRCTL_SCHED_LPR_NUM_ENTRIES_SHIFT) - -/* - * PAGECLOSE (R/W) - * - * Description: If true, bank is kept open only until there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed as part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (co_ih_rxcmd_autopre). - * The pageclose feature provids a midway between Open and Close page policies. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_SCHED_PAGECLOSE_MASK (0x4U) -#define DDRCTL_SCHED_PAGECLOSE_SHIFT (2U) -#define DDRCTL_SCHED_PAGECLOSE_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_PAGECLOSE_SHIFT) & DDRCTL_SCHED_PAGECLOSE_MASK) -#define DDRCTL_SCHED_PAGECLOSE_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_PAGECLOSE_MASK) >> DDRCTL_SCHED_PAGECLOSE_SHIFT) - -/* - * PREFER_WRITE (R/W) - * - * Description: If set then the bank selector prefers writes over reads. - * FOR DEBUG ONLY. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_SCHED_PREFER_WRITE_MASK (0x2U) -#define DDRCTL_SCHED_PREFER_WRITE_SHIFT (1U) -#define DDRCTL_SCHED_PREFER_WRITE_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_PREFER_WRITE_SHIFT) & DDRCTL_SCHED_PREFER_WRITE_MASK) -#define DDRCTL_SCHED_PREFER_WRITE_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_PREFER_WRITE_MASK) >> DDRCTL_SCHED_PREFER_WRITE_SHIFT) - -/* - * FORCE_LOW_PRI_N (R/W) - * - * Description: Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK (0x1U) -#define DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT (0U) -#define DDRCTL_SCHED_FORCE_LOW_PRI_N_SET(x) (((uint32_t)(x) << DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK) -#define DDRCTL_SCHED_FORCE_LOW_PRI_N_GET(x) (((uint32_t)(x) & DDRCTL_SCHED_FORCE_LOW_PRI_N_MASK) >> DDRCTL_SCHED_FORCE_LOW_PRI_N_SHIFT) - -/* Bitfield definition for register: SCHED1 */ -/* - * PAGECLOSE_TIMER (R/W) - * - * Description: This field works in conjunction with SCHED.pageclose. It only has meaning if SCHED.pageclose==1. - * If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for details of when this may happen. - * If SCHED.pageclose==1 and pageclose_timer>0, then an auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit. Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a page hit. Once the timer has reached zero, an explcit precharge will be attempted to be scheduled. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK (0xFFU) -#define DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT (0U) -#define DDRCTL_SCHED1_PAGECLOSE_TIMER_SET(x) (((uint32_t)(x) << DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK) -#define DDRCTL_SCHED1_PAGECLOSE_TIMER_GET(x) (((uint32_t)(x) & DDRCTL_SCHED1_PAGECLOSE_TIMER_MASK) >> DDRCTL_SCHED1_PAGECLOSE_TIMER_SHIFT) - -/* Bitfield definition for register: PERFHPR1 */ -/* - * HPR_XACT_RUN_LENGTH (R/W) - * - * Description: Number of transactions that are serviced once the HPR queue goes critical is the smaller of: - * This number - * Number of transactions available Unit: Transaction. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0xf - * Exists: Always - */ -#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK (0xFF000000UL) -#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT (24U) -#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) -#define DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFHPR1_HPR_XACT_RUN_LENGTH_SHIFT) - -/* - * HPR_MAX_STARVE (R/W) - * - * Description: Number of clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. - * Unit: Clock cycles. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK (0xFFFFU) -#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT (0U) -#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK) -#define DDRCTL_PERFHPR1_HPR_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFHPR1_HPR_MAX_STARVE_MASK) >> DDRCTL_PERFHPR1_HPR_MAX_STARVE_SHIFT) - -/* Bitfield definition for register: PERFLPR1 */ -/* - * LPR_XACT_RUN_LENGTH (R/W) - * - * Description: Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - * This number - * Number of transactions available. Unit: Transaction. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0xf - * Exists: Always - */ -#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK (0xFF000000UL) -#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT (24U) -#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) -#define DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT) - -/* - * LPR_MAX_STARVE (R/W) - * - * Description: Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. - * Unit: Clock cycles. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x7f - * Exists: Always - */ -#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK (0xFFFFU) -#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT (0U) -#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK) -#define DDRCTL_PERFLPR1_LPR_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFLPR1_LPR_MAX_STARVE_MASK) >> DDRCTL_PERFLPR1_LPR_MAX_STARVE_SHIFT) - -/* Bitfield definition for register: PERFWR1 */ -/* - * W_XACT_RUN_LENGTH (R/W) - * - * Description: Number of transactions that are serviced once the WR queue goes critical is the smaller of: - * This number - * Number of transactions available. Unit: Transaction. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0xf - * Exists: Always - */ -#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK (0xFF000000UL) -#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT (24U) -#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SET(x) (((uint32_t)(x) << DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK) -#define DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_GET(x) (((uint32_t)(x) & DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_MASK) >> DDRCTL_PERFWR1_W_XACT_RUN_LENGTH_SHIFT) - -/* - * W_MAX_STARVE (R/W) - * - * Description: Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies. - * Unit: Clock cycles. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x7f - * Exists: Always - */ -#define DDRCTL_PERFWR1_W_MAX_STARVE_MASK (0xFFFFU) -#define DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT (0U) -#define DDRCTL_PERFWR1_W_MAX_STARVE_SET(x) (((uint32_t)(x) << DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK) -#define DDRCTL_PERFWR1_W_MAX_STARVE_GET(x) (((uint32_t)(x) & DDRCTL_PERFWR1_W_MAX_STARVE_MASK) >> DDRCTL_PERFWR1_W_MAX_STARVE_SHIFT) - -/* Bitfield definition for register: PERFVPR1 */ -/* - * VPR_TIMEOUT_RANGE (R/W) - * - * Description: Indicates the range of the timeout value that is used for grouping the expired VPR commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPR commands whose timeout counters are 15 or below will be considered as expired-VPR commands when the timeout value of any of the VPR commands reach 0. The expired-VPR commands, when present, are given higher priority than HPR commands. The VPR commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. - * The Max value for this register is 0x7FF and the Min value is 0x0. - * When programmed to the Max value of 0x7FF, all the VPR commands that come in to DDRC will time-out right-away and will be considered as expired-VPR. - * When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPR. - * Unit: Clock cycles. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x0 - * Exists: UMCTL2_VPR_EN==1 - */ -#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK (0x7FFU) -#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT (0U) -#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SET(x) (((uint32_t)(x) << DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) -#define DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_GET(x) (((uint32_t)(x) & DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPR1_VPR_TIMEOUT_RANGE_SHIFT) - -/* Bitfield definition for register: PERFVPW1 */ -/* - * VPW_TIMEOUT_RANGE (R/W) - * - * Description: Indicates the range of the timeout value that is used for grouping the expired VPW commands in the CAM in DDRC. For example, if the register value is set to 0xF, then the priorities of all the VPW commands whose timeout counters are 15 or below will be considered as expired-VPW commands when the timeout value of any of the VPW commands reach 0. The expired-VPW commands, when present, are given higher priority than normal Write commands. The VPW commands are expected to consist of largely page hit traffic and by grouping them together the bus utilization is expected to increase. This register applies to transactions inside the DDRC only. - * The Max value for this register is 0x7FF and the Min value is 0x0. - * When programmed to the Max value of 0x7FF, all the VPW commands that come in to DDRC will time-out right-away and will be considered as expired-VPW. - * When programmed to the Min value of 0x0, the timer of each command would have to reach a value of 0 before it will be considered as expired-VPW. - * Unit: Clock cycles. - * FOR PERFORMANCE ONLY. - * Value After Reset: 0x0 - * Exists: UMCTL2_VPW_EN==1 - */ -#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK (0x7FFU) -#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT (0U) -#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SET(x) (((uint32_t)(x) << DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) -#define DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_GET(x) (((uint32_t)(x) & DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_MASK) >> DDRCTL_PERFVPW1_VPW_TIMEOUT_RANGE_SHIFT) - -/* Bitfield definition for register: DBG0 */ -/* - * DIS_COLLISION_PAGE_OPT (R/W) - * - * Description: When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). - * FOR DEBUG ONLY. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK (0x10U) -#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT (4U) -#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK) -#define DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_MASK) >> DDRCTL_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT) - -/* - * DIS_ACT_BYPASS (R/W) - * - * Description: Only present in designs supporting activate bypass. - * When 1, disable bypass path for high priority read activates FOR DEBUG ONLY. - * Value After Reset: 0x0 - * Exists: MEMC_BYPASS==1 - */ -#define DDRCTL_DBG0_DIS_ACT_BYPASS_MASK (0x4U) -#define DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT (2U) -#define DDRCTL_DBG0_DIS_ACT_BYPASS_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK) -#define DDRCTL_DBG0_DIS_ACT_BYPASS_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_ACT_BYPASS_MASK) >> DDRCTL_DBG0_DIS_ACT_BYPASS_SHIFT) - -/* - * DIS_RD_BYPASS (R/W) - * - * Description: Only present in designs supporting read bypass. - * When 1, disable bypass path for high priority read page hits FOR DEBUG ONLY. - * Value After Reset: 0x0 - * Exists: MEMC_BYPASS==1 - */ -#define DDRCTL_DBG0_DIS_RD_BYPASS_MASK (0x2U) -#define DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT (1U) -#define DDRCTL_DBG0_DIS_RD_BYPASS_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK) -#define DDRCTL_DBG0_DIS_RD_BYPASS_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_RD_BYPASS_MASK) >> DDRCTL_DBG0_DIS_RD_BYPASS_SHIFT) - -/* - * DIS_WC (R/W) - * - * Description: When 1, disable write combine. FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBG0_DIS_WC_MASK (0x1U) -#define DDRCTL_DBG0_DIS_WC_SHIFT (0U) -#define DDRCTL_DBG0_DIS_WC_SET(x) (((uint32_t)(x) << DDRCTL_DBG0_DIS_WC_SHIFT) & DDRCTL_DBG0_DIS_WC_MASK) -#define DDRCTL_DBG0_DIS_WC_GET(x) (((uint32_t)(x) & DDRCTL_DBG0_DIS_WC_MASK) >> DDRCTL_DBG0_DIS_WC_SHIFT) - -/* Bitfield definition for register: DBG1 */ -/* - * DIS_HIF (R/W) - * - * Description: When 1, uMCTL2 asserts the HIF command ih_co_stall. uMCTL2 will ignore the co_ih_rxcmd_valid and all other associated request signals. - * This bit is intended to be switched on-the-fly. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBG1_DIS_HIF_MASK (0x2U) -#define DDRCTL_DBG1_DIS_HIF_SHIFT (1U) -#define DDRCTL_DBG1_DIS_HIF_SET(x) (((uint32_t)(x) << DDRCTL_DBG1_DIS_HIF_SHIFT) & DDRCTL_DBG1_DIS_HIF_MASK) -#define DDRCTL_DBG1_DIS_HIF_GET(x) (((uint32_t)(x) & DDRCTL_DBG1_DIS_HIF_MASK) >> DDRCTL_DBG1_DIS_HIF_SHIFT) - -/* - * DIS_DQ (R/W) - * - * Description: When 1, uMCTL2 will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. - * This bit may be used to prevent reads or writes being issued by the uMCTL2, which makes it safe to modify certain register fields associated with reads and writes (see User Guide for details). After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. - * This bit is intended to be switched on-the-fly. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBG1_DIS_DQ_MASK (0x1U) -#define DDRCTL_DBG1_DIS_DQ_SHIFT (0U) -#define DDRCTL_DBG1_DIS_DQ_SET(x) (((uint32_t)(x) << DDRCTL_DBG1_DIS_DQ_SHIFT) & DDRCTL_DBG1_DIS_DQ_MASK) -#define DDRCTL_DBG1_DIS_DQ_GET(x) (((uint32_t)(x) & DDRCTL_DBG1_DIS_DQ_MASK) >> DDRCTL_DBG1_DIS_DQ_SHIFT) - -/* Bitfield definition for register: DBGCAM */ -/* - * WR_DATA_PIPELINE_EMPTY (R) - * - * Description: This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK (0x20000000UL) -#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT (29U) -#define DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_WR_DATA_PIPELINE_EMPTY_SHIFT) - -/* - * RD_DATA_PIPELINE_EMPTY (R) - * - * Description: This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK (0x10000000UL) -#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT (28U) -#define DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_MASK) >> DDRCTL_DBGCAM_RD_DATA_PIPELINE_EMPTY_SHIFT) - -/* - * DBG_WR_Q_EMPTY (R) - * - * Description: When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. - * An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. - * FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK (0x4000000UL) -#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT (26U) -#define DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_WR_Q_EMPTY_SHIFT) - -/* - * DBG_RD_Q_EMPTY (R) - * - * Description: When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. - * An example use-case scenario: When Controller enters Self- Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time. - * FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK (0x2000000UL) -#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT (25U) -#define DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_MASK) >> DDRCTL_DBGCAM_DBG_RD_Q_EMPTY_SHIFT) - -/* - * DBG_STALL (R) - * - * Description: Stall FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_DBG_STALL_MASK (0x1000000UL) -#define DDRCTL_DBGCAM_DBG_STALL_SHIFT (24U) -#define DDRCTL_DBGCAM_DBG_STALL_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_STALL_MASK) >> DDRCTL_DBGCAM_DBG_STALL_SHIFT) - -/* - * DBG_W_Q_DEPTH (R) - * - * Description: Write queue depth - * Note: The width of this field is dependent on log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth - * = 32, then register width is 6 bits and bit 22 is reserved. FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK (0x7F0000UL) -#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT (16U) -#define DDRCTL_DBGCAM_DBG_W_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_W_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_W_Q_DEPTH_SHIFT) - -/* - * DBG_LPR_Q_DEPTH (R) - * - * Description: Low priority read queue depth Note: The width of this field is dependent on - * log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth - * = 32, then register width is 6 bits and bit 14 is reserved FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK (0x7F00U) -#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT (8U) -#define DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_LPR_Q_DEPTH_SHIFT) - -/* - * DBG_HPR_Q_DEPTH (R) - * - * Description: High priority read queue depth Note: The width of this field is dependent on - * log(MEMC_NO_OF_ENTRY+1). For example, if CAM depth - * = 32, then register width is 6 bits and bit 6 is reserved FOR DEBUG ONLY - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK (0x7FU) -#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT (0U) -#define DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_MASK) >> DDRCTL_DBGCAM_DBG_HPR_Q_DEPTH_SHIFT) - -/* Bitfield definition for register: DBGCMD */ -/* - * CTRLUPD (R/WSC) - * - * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCMD_CTRLUPD_MASK (0x20U) -#define DDRCTL_DBGCMD_CTRLUPD_SHIFT (5U) -#define DDRCTL_DBGCMD_CTRLUPD_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_CTRLUPD_SHIFT) & DDRCTL_DBGCMD_CTRLUPD_MASK) -#define DDRCTL_DBGCMD_CTRLUPD_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_CTRLUPD_MASK) >> DDRCTL_DBGCMD_CTRLUPD_SHIFT) - -/* - * ZQ_CALIB_SHORT (R/WSC) - * - * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short) command to the SDRAM. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignored when in Self-Refresh and Deep power-down operating modes. - * Value After Reset: 0x0 - * Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 - */ -#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK (0x10U) -#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT (4U) -#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK) -#define DDRCTL_DBGCMD_ZQ_CALIB_SHORT_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_ZQ_CALIB_SHORT_MASK) >> DDRCTL_DBGCMD_ZQ_CALIB_SHORT_SHIFT) - -/* - * RANK1_REFRESH (R/WSC) - * - * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. - * Value After Reset: 0x0 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_DBGCMD_RANK1_REFRESH_MASK (0x2U) -#define DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT (1U) -#define DDRCTL_DBGCMD_RANK1_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK) -#define DDRCTL_DBGCMD_RANK1_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK1_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK1_REFRESH_SHIFT) - -/* - * RANK0_REFRESH (R/WSC) - * - * Description: Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. When this request is stored in uMCTL2, the bit is automatically cleared. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGCMD_RANK0_REFRESH_MASK (0x1U) -#define DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT (0U) -#define DDRCTL_DBGCMD_RANK0_REFRESH_SET(x) (((uint32_t)(x) << DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK) -#define DDRCTL_DBGCMD_RANK0_REFRESH_GET(x) (((uint32_t)(x) & DDRCTL_DBGCMD_RANK0_REFRESH_MASK) >> DDRCTL_DBGCMD_RANK0_REFRESH_SHIFT) - -/* Bitfield definition for register: DBGSTAT */ -/* - * CTRLUPD_BUSY (R) - * - * Description: SoC core may initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in uMCTL2. It is recommended not to perform ctrlupd operations when this signal is high. - * 0 - Indicates that the SoC core can initiate a ctrlupd operation - * 1 - Indicates that ctrlupd operation has not been initiated yet in uMCTL2 - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK (0x20U) -#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT (5U) -#define DDRCTL_DBGSTAT_CTRLUPD_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_CTRLUPD_BUSY_MASK) >> DDRCTL_DBGSTAT_CTRLUPD_BUSY_SHIFT) - -/* - * ZQ_CALIB_SHORT_BUSY (R) - * - * Description: SoC core may initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in uMCTL2. It is recommended not to perform ZQCS operations when this signal is high. - * 0 - Indicates that the SoC core can initiate a ZQCS operation - * 1 - Indicates that ZQCS operation has not been initiated yet in uMCTL2 - * Value After Reset: 0x0 - * Exists: MEMC_DDR3_OR_4_OR_LPDDR2==1 - */ -#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK (0x10U) -#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT (4U) -#define DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_MASK) >> DDRCTL_DBGSTAT_ZQ_CALIB_SHORT_BUSY_SHIFT) - -/* - * RANK1_REFRESH_BUSY (R) - * - * Description: SoC core may initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored in uMCTL2. It is recommended not to perform rank1_refresh operations when this signal is high. - * 0 - Indicates that the SoC core can initiate a rank1_refresh operation - * 1 - Indicates that rank1_refresh operation has not been stored yet in uMCTL2 - * Value After Reset: 0x0 - * Exists: MEMC_NUM_RANKS>1 - */ -#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK (0x2U) -#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT (1U) -#define DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK1_REFRESH_BUSY_SHIFT) - -/* - * RANK0_REFRESH_BUSY (R) - * - * Description: SoC core may initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored in uMCTL2. It is recommended not to perform rank0_refresh operations when this signal is high. - * 0 - Indicates that the SoC core can initiate a rank0_refresh operation - * 1 - Indicates that rank0_refresh operation has not been stored yet in uMCTL2 - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK (0x1U) -#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT (0U) -#define DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_MASK) >> DDRCTL_DBGSTAT_RANK0_REFRESH_BUSY_SHIFT) - -/* Bitfield definition for register: PSTAT */ -/* - * WR_PORT_BUSY_15 (R) - * - * Description: Indicates if there are outstanding writes for port 15. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_15==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK (0x80000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT (31U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_15_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_15_SHIFT) - -/* - * WR_PORT_BUSY_14 (R) - * - * Description: Indicates if there are outstanding writes for port 14. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_14==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK (0x40000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT (30U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_14_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_14_SHIFT) - -/* - * WR_PORT_BUSY_13 (R) - * - * Description: Indicates if there are outstanding writes for port 13. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_13==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK (0x20000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT (29U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_13_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_13_SHIFT) - -/* - * WR_PORT_BUSY_12 (R) - * - * Description: Indicates if there are outstanding writes for port 12. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_12==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK (0x10000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT (28U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_12_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_12_SHIFT) - -/* - * WR_PORT_BUSY_11 (R) - * - * Description: Indicates if there are outstanding writes for port 11. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_11==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK (0x8000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT (27U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_11_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_11_SHIFT) - -/* - * WR_PORT_BUSY_10 (R) - * - * Description: Indicates if there are outstanding writes for port 10. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_10==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK (0x4000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT (26U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_10_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_10_SHIFT) - -/* - * WR_PORT_BUSY_9 (R) - * - * Description: Indicates if there are outstanding writes for port 9. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_9==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK (0x2000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT (25U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_9_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_9_SHIFT) - -/* - * WR_PORT_BUSY_8 (R) - * - * Description: Indicates if there are outstanding writes for port 8. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_8==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK (0x1000000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT (24U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_8_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_8_SHIFT) - -/* - * WR_PORT_BUSY_7 (R) - * - * Description: Indicates if there are outstanding writes for port 7. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_7==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK (0x800000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT (23U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_7_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_7_SHIFT) - -/* - * WR_PORT_BUSY_6 (R) - * - * Description: Indicates if there are outstanding writes for port 6. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_6==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK (0x400000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT (22U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_6_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_6_SHIFT) - -/* - * WR_PORT_BUSY_5 (R) - * - * Description: Indicates if there are outstanding writes for port 5. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_5==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK (0x200000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT (21U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_5_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_5_SHIFT) - -/* - * WR_PORT_BUSY_4 (R) - * - * Description: Indicates if there are outstanding writes for port 4. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_4==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK (0x100000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT (20U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_4_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_4_SHIFT) - -/* - * WR_PORT_BUSY_3 (R) - * - * Description: Indicates if there are outstanding writes for port 3. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_3==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK (0x80000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT (19U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_3_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_3_SHIFT) - -/* - * WR_PORT_BUSY_2 (R) - * - * Description: Indicates if there are outstanding writes for port 2. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_2==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK (0x40000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT (18U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_2_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_2_SHIFT) - -/* - * WR_PORT_BUSY_1 (R) - * - * Description: Indicates if there are outstanding writes for port 1. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_1==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK (0x20000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT (17U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_1_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_1_SHIFT) - -/* - * WR_PORT_BUSY_0 (R) - * - * Description: Indicates if there are outstanding writes for port 0. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_0==1 - */ -#define DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK (0x10000UL) -#define DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT (16U) -#define DDRCTL_PSTAT_WR_PORT_BUSY_0_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_WR_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_WR_PORT_BUSY_0_SHIFT) - -/* - * RD_PORT_BUSY_15 (R) - * - * Description: Indicates if there are outstanding reads for port 15. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_15==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK (0x8000U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT (15U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_15_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_15_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_15_SHIFT) - -/* - * RD_PORT_BUSY_14 (R) - * - * Description: Indicates if there are outstanding reads for port 14. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_14==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK (0x4000U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT (14U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_14_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_14_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_14_SHIFT) - -/* - * RD_PORT_BUSY_13 (R) - * - * Description: Indicates if there are outstanding reads for port 13. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_13==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK (0x2000U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT (13U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_13_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_13_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_13_SHIFT) - -/* - * RD_PORT_BUSY_12 (R) - * - * Description: Indicates if there are outstanding reads for port 12. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_12==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK (0x1000U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT (12U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_12_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_12_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_12_SHIFT) - -/* - * RD_PORT_BUSY_11 (R) - * - * Description: Indicates if there are outstanding reads for port 11. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_11==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK (0x800U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT (11U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_11_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_11_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_11_SHIFT) - -/* - * RD_PORT_BUSY_10 (R) - * - * Description: Indicates if there are outstanding reads for port 10. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_10==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK (0x400U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT (10U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_10_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_10_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_10_SHIFT) - -/* - * RD_PORT_BUSY_9 (R) - * - * Description: Indicates if there are outstanding reads for port 9. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_9==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK (0x200U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT (9U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_9_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_9_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_9_SHIFT) - -/* - * RD_PORT_BUSY_8 (R) - * - * Description: Indicates if there are outstanding reads for port 8. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_8==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK (0x100U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT (8U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_8_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_8_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_8_SHIFT) - -/* - * RD_PORT_BUSY_7 (R) - * - * Description: Indicates if there are outstanding reads for port 7. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_7==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK (0x80U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT (7U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_7_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_7_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_7_SHIFT) - -/* - * RD_PORT_BUSY_6 (R) - * - * Description: Indicates if there are outstanding reads for port 6. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_6==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK (0x40U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT (6U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_6_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_6_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_6_SHIFT) - -/* - * RD_PORT_BUSY_5 (R) - * - * Description: Indicates if there are outstanding reads for port 5. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_5==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK (0x20U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT (5U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_5_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_5_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_5_SHIFT) - -/* - * RD_PORT_BUSY_4 (R) - * - * Description: Indicates if there are outstanding reads for port 4. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_4==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK (0x10U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT (4U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_4_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_4_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_4_SHIFT) - -/* - * RD_PORT_BUSY_3 (R) - * - * Description: Indicates if there are outstanding reads for port 3. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_3==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK (0x8U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT (3U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_3_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_3_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_3_SHIFT) - -/* - * RD_PORT_BUSY_2 (R) - * - * Description: Indicates if there are outstanding reads for port 2. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_2==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK (0x4U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT (2U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_2_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_2_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_2_SHIFT) - -/* - * RD_PORT_BUSY_1 (R) - * - * Description: Indicates if there are outstanding reads for port 1. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_1==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK (0x2U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT (1U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_1_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_1_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_1_SHIFT) - -/* - * RD_PORT_BUSY_0 (R) - * - * Description: Indicates if there are outstanding reads for port 0. - * Value After Reset: 0x0 - * Exists: UMCTL2_PORT_0==1 - */ -#define DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK (0x1U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT (0U) -#define DDRCTL_PSTAT_RD_PORT_BUSY_0_GET(x) (((uint32_t)(x) & DDRCTL_PSTAT_RD_PORT_BUSY_0_MASK) >> DDRCTL_PSTAT_RD_PORT_BUSY_0_SHIFT) - -/* Bitfield definition for register: PCCFG */ -/* - * PAGEMATCH_LIMIT (R/W) - * - * Description: Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK (0x10U) -#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT (4U) -#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_SET(x) (((uint32_t)(x) << DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK) -#define DDRCTL_PCCFG_PAGEMATCH_LIMIT_GET(x) (((uint32_t)(x) & DDRCTL_PCCFG_PAGEMATCH_LIMIT_MASK) >> DDRCTL_PCCFG_PAGEMATCH_LIMIT_SHIFT) - -/* - * GO2CRITICAL_EN (R/W) - * - * Description: If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_rd signals going to DDRC based on urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critical_rd signals at DDRC are driven to 1b'0. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCCFG_GO2CRITICAL_EN_MASK (0x1U) -#define DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT (0U) -#define DDRCTL_PCCFG_GO2CRITICAL_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK) -#define DDRCTL_PCCFG_GO2CRITICAL_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCCFG_GO2CRITICAL_EN_MASK) >> DDRCTL_PCCFG_GO2CRITICAL_EN_SHIFT) - -/* Bitfield definition for register of struct array PCFG: R */ -/* - * RD_PORT_PAGEMATCH_EN (R/W) - * - * Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. - * Value After Reset: "(MEMC_DDR4_EN==1) ? 0x0 : 0x1" - * Exists: Always - */ -#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK (0x4000U) -#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT (14U) -#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK) -#define DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_PAGEMATCH_EN_SHIFT) - -/* - * RD_PORT_URGENT_EN (R/W) - * - * Description: If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_rd signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK (0x2000U) -#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT (13U) -#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK) -#define DDRCTL_PCFG_R_RD_PORT_URGENT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_URGENT_EN_SHIFT) - -/* - * RD_PORT_AGING_EN (R/W) - * - * Description: If set to 1, enables aging function for the read channel of the port. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK (0x1000U) -#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT (12U) -#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK) -#define DDRCTL_PCFG_R_RD_PORT_AGING_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_R_RD_PORT_AGING_EN_SHIFT) - -/* - * RD_PORT_PRIORITY (R/W) - * - * Description: Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. - * When the aging counter becomes 0, the corresponding port channel will have the highest priority level (timeout condition - * - Priority0). For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: The two LSBs of this register field are tied internally to 2'b00. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK (0x3FFU) -#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT (0U) -#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK) -#define DDRCTL_PCFG_R_RD_PORT_PRIORITY_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_R_RD_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_R_RD_PORT_PRIORITY_SHIFT) - -/* Bitfield definition for register of struct array PCFG: W */ -/* - * WR_PORT_PAGEMATCH_EN (R/W) - * - * Description: If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be granted if the following immediate commands are to the same memory page (i.e. same bank and same row). See also related PCCFG.pagematch_limit register. - * Value After Reset: 0x1 - * Exists: Always - */ -#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK (0x4000U) -#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT (14U) -#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK) -#define DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_PAGEMATCH_EN_SHIFT) - -/* - * WR_PORT_URGENT_EN (R/W) - * - * Description: If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is not associated with any particular command). - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK (0x2000U) -#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT (13U) -#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK) -#define DDRCTL_PCFG_W_WR_PORT_URGENT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_URGENT_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_URGENT_EN_SHIFT) - -/* - * WR_PORT_AGING_EN (R/W) - * - * Description: If set to 1, enables aging function for the write channel of the port. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK (0x1000U) -#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT (12U) -#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK) -#define DDRCTL_PCFG_W_WR_PORT_AGING_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_AGING_EN_MASK) >> DDRCTL_PCFG_W_WR_PORT_AGING_EN_SHIFT) - -/* - * WR_PORT_PRIORITY (R/W) - * - * Description: Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. The higher significant 5-bits of the write aging counter sets the initial priority of the - * write channel of a given port. Port's priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters cannot be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register field are tied internally to 2'b00. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK (0x3FFU) -#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT (0U) -#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK) -#define DDRCTL_PCFG_W_WR_PORT_PRIORITY_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_W_WR_PORT_PRIORITY_MASK) >> DDRCTL_PCFG_W_WR_PORT_PRIORITY_SHIFT) - -/* Bitfield definition for register of struct array PCFG: C */ -/* - * AHB_ENDIANNESS (R/W) - * - * Description: If set to 0, enables support for little endian on the AHB port. If set to 1, enables support for big endian (BE- 32) on the AHB port. If set to 2, enables support for big endian (BE-A) on the AHB port. - * Value After Reset: 0x0 - * Exists: UMCTL2_A_AHB_n==1 - */ -#define DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK (0x3U) -#define DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT (0U) -#define DDRCTL_PCFG_C_AHB_ENDIANNESS_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK) -#define DDRCTL_PCFG_C_AHB_ENDIANNESS_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_C_AHB_ENDIANNESS_MASK) >> DDRCTL_PCFG_C_AHB_ENDIANNESS_SHIFT) - -/* Bitfield definition for register of struct array PCFG: MASKCH */ -/* - * ID_MASK (R/W) - * - * Description: Determines the mask used in the ID mapping function for virtual channel m. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK (0xFFFFFFFFUL) -#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT (0U) -#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK) -#define DDRCTL_PCFG_ID_MASKCH_ID_MASK_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_ID_MASKCH_ID_MASK_MASK) >> DDRCTL_PCFG_ID_MASKCH_ID_MASK_SHIFT) - -/* Bitfield definition for register of struct array PCFG: VALUECH */ -/* - * ID_VALUE (R/W) - * - * Description: Determines the value used in the ID mapping function for virtual channel m. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK (0xFFFFFFFFUL) -#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT (0U) -#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK) -#define DDRCTL_PCFG_ID_VALUECH_ID_VALUE_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_ID_VALUECH_ID_VALUE_MASK) >> DDRCTL_PCFG_ID_VALUECH_ID_VALUE_SHIFT) - -/* Bitfield definition for register of struct array PCFG: CTRL */ -/* - * PORT_EN (R/W) - * - * Description: Enables port n. - * Value After Reset: "UMCTL2_PORT_EN_RESET_VALUE" - * Exists: Always - */ -#define DDRCTL_PCFG_CTRL_PORT_EN_MASK (0x1U) -#define DDRCTL_PCFG_CTRL_PORT_EN_SHIFT (0U) -#define DDRCTL_PCFG_CTRL_PORT_EN_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_CTRL_PORT_EN_SHIFT) & DDRCTL_PCFG_CTRL_PORT_EN_MASK) -#define DDRCTL_PCFG_CTRL_PORT_EN_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_CTRL_PORT_EN_MASK) >> DDRCTL_PCFG_CTRL_PORT_EN_SHIFT) - -/* Bitfield definition for register of struct array PCFG: QOS0 */ -/* - * RQOS_MAP_REGION1 (R/W) - * - * Description: This bitfield indicates the traffic class of region - * 1. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK (0x300000UL) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT (20U) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION1_SHIFT) - -/* - * RQOS_MAP_REGION0 (R/W) - * - * Description: This bitfield indicates the traffic class of region - * 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR) then VPR traffic is aliased to LPR traffic. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK (0x30000UL) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT (16U) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_REGION0_SHIFT) - -/* - * RQOS_MAP_LEVEL1 (R/W) - * - * Description: Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13(for dual RAQ) or 0 to 14(for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinct values. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK (0xFU) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT (0U) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK) -#define DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_MASK) >> DDRCTL_PCFG_QOS0_RQOS_MAP_LEVEL1_SHIFT) - -/* Bitfield definition for register of struct array PCFG: QOS1 */ -/* - * RQOS_MAP_TIMEOUTR (R/W) - * - * Description: Specifies the timeout value for transactions mapped to the red address queue. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK (0x7FF0000UL) -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT (16U) -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK) -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTR_SHIFT) - -/* - * RQOS_MAP_TIMEOUTB (R/W) - * - * Description: Specifies the timeout value for transactions mapped to the blue address queue. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK (0x7FFU) -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT (0U) -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK) -#define DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_MASK) >> DDRCTL_PCFG_QOS1_RQOS_MAP_TIMEOUTB_SHIFT) - -/* Bitfield definition for register of struct array PCFG: WQOS0 */ -/* - * WQOS_MAP_REGION1 (R/W) - * - * Description: This bitfield indicates the traffic class of region - * 1. Valid values are: - * 0: NPW - * 1: VPW - * When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK (0x300000UL) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT (20U) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION1_SHIFT) - -/* - * WQOS_MAP_REGION0 (R/W) - * - * Description: This bitfield indicates the traffic class of region - * 0. Valid values are: - * 0: NPW - * 1: VPW - * When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region0 is set to 1 (VPW) then VPW traffic is aliased to NPW traffic. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK (0x30000UL) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT (16U) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_REGION0_SHIFT) - -/* - * WQOS_MAP_LEVEL (R/W) - * - * Description: Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value corresponds to higher port priority. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK (0xFU) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT (0U) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK) -#define DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_MASK) >> DDRCTL_PCFG_WQOS0_WQOS_MAP_LEVEL_SHIFT) - -/* Bitfield definition for register of struct array PCFG: WQOS1 */ -/* - * WQOS_MAP_TIMEOUT (R/W) - * - * Description: Specifies the timeout value for write transactions. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK (0x7FFU) -#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT (0U) -#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SET(x) (((uint32_t)(x) << DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK) -#define DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_GET(x) (((uint32_t)(x) & DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_MASK) >> DDRCTL_PCFG_WQOS1_WQOS_MAP_TIMEOUT_SHIFT) - -/* Bitfield definition for register of struct array SAR: BASE */ -/* - * BASE_ADDR (R/W) - * - * Description: Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_SAR_BASE_BASE_ADDR_MASK (0xFFFFFFFFUL) -#define DDRCTL_SAR_BASE_BASE_ADDR_SHIFT (0U) -#define DDRCTL_SAR_BASE_BASE_ADDR_SET(x) (((uint32_t)(x) << DDRCTL_SAR_BASE_BASE_ADDR_SHIFT) & DDRCTL_SAR_BASE_BASE_ADDR_MASK) -#define DDRCTL_SAR_BASE_BASE_ADDR_GET(x) (((uint32_t)(x) & DDRCTL_SAR_BASE_BASE_ADDR_MASK) >> DDRCTL_SAR_BASE_BASE_ADDR_SHIFT) - -/* Bitfield definition for register of struct array SAR: SIZE */ -/* - * NBLOCKS (R/W) - * - * Description: Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - * Value After Reset: 0x0 - * Exists: Always - */ -#define DDRCTL_SAR_SIZE_NBLOCKS_MASK (0xFFU) -#define DDRCTL_SAR_SIZE_NBLOCKS_SHIFT (0U) -#define DDRCTL_SAR_SIZE_NBLOCKS_SET(x) (((uint32_t)(x) << DDRCTL_SAR_SIZE_NBLOCKS_SHIFT) & DDRCTL_SAR_SIZE_NBLOCKS_MASK) -#define DDRCTL_SAR_SIZE_NBLOCKS_GET(x) (((uint32_t)(x) & DDRCTL_SAR_SIZE_NBLOCKS_MASK) >> DDRCTL_SAR_SIZE_NBLOCKS_SHIFT) - -/* Bitfield definition for register: SBRCTL */ -/* - * SCRUB_INTERVAL (R/W) - * - * Description: Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0, scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full range of memory at once before or after SW controlled low power operations. After completing the full range of scrub while scrub_interval=0, scrub_done register is set and sbr_done_intr interrupt signal is asserted. - * Value After Reset: 0xff - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK (0x1FFF00UL) -#define DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT (8U) -#define DDRCTL_SBRCTL_SCRUB_INTERVAL_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK) -#define DDRCTL_SBRCTL_SCRUB_INTERVAL_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_INTERVAL_MASK) >> DDRCTL_SBRCTL_SCRUB_INTERVAL_SHIFT) - -/* - * SCRUB_BURST (R/W) - * - * Description: Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes. During low power, the period of the scrub burst becomes \"scrub_burst*scrub_interval\" cycles. - * During normal operation mode of the controller (ie. not in power-down or self refresh), scrub_burst is ignored and only one scrub command is generated. Valid values are: 1: 1 read, 2: 4 reads, 3: 16 reads, 4: 64 reads, 5: 256 reads, - * 6: 1024 reads. - * Value After Reset: 0x1 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRCTL_SCRUB_BURST_MASK (0x70U) -#define DDRCTL_SBRCTL_SCRUB_BURST_SHIFT (4U) -#define DDRCTL_SBRCTL_SCRUB_BURST_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_BURST_SHIFT) & DDRCTL_SBRCTL_SCRUB_BURST_MASK) -#define DDRCTL_SBRCTL_SCRUB_BURST_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_BURST_MASK) >> DDRCTL_SBRCTL_SCRUB_BURST_SHIFT) - -/* - * SCRUB_MODE (R/W) - * - * Description: scrub_mode:0 ECC scrubber will perform reads scrub_mode:1 ECC scrubber will perform writes Value After Reset: 0x0 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRCTL_SCRUB_MODE_MASK (0x4U) -#define DDRCTL_SBRCTL_SCRUB_MODE_SHIFT (2U) -#define DDRCTL_SBRCTL_SCRUB_MODE_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_MODE_SHIFT) & DDRCTL_SBRCTL_SCRUB_MODE_MASK) -#define DDRCTL_SBRCTL_SCRUB_MODE_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_MODE_MASK) >> DDRCTL_SBRCTL_SCRUB_MODE_SHIFT) - -/* - * SCRUB_DURING_LOWPOWER (R/W) - * - * Description: Continue scrubbing during low power. If set to 1, burst of scrubs will be issued in HW controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by HW low-power (LP) interface. If set to 0, the scrubber will not attempt to send commands while the DDRC is in HW controlled low power modes. In this case, the scrubber will remember the last address issued and will automatically continue from there when the DDRC exits the LP mode. - * Value After Reset: 0x0 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK (0x2U) -#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT (1U) -#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK) -#define DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_MASK) >> DDRCTL_SBRCTL_SCRUB_DURING_LOWPOWER_SHIFT) - -/* - * SCRUB_EN (R/W) - * - * Description: Enable ECC scrubber. If set to 1, enables the scrubber to generate background read commands after the memories are initialized. If set to 0, disables the scrubber, resets the address generator to 0 and clears the scrubber status. This bitfield must be accessed separately from the other bitfields in this register. - * Value After Reset: 0x0 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRCTL_SCRUB_EN_MASK (0x1U) -#define DDRCTL_SBRCTL_SCRUB_EN_SHIFT (0U) -#define DDRCTL_SBRCTL_SCRUB_EN_SET(x) (((uint32_t)(x) << DDRCTL_SBRCTL_SCRUB_EN_SHIFT) & DDRCTL_SBRCTL_SCRUB_EN_MASK) -#define DDRCTL_SBRCTL_SCRUB_EN_GET(x) (((uint32_t)(x) & DDRCTL_SBRCTL_SCRUB_EN_MASK) >> DDRCTL_SBRCTL_SCRUB_EN_SHIFT) - -/* Bitfield definition for register: SBRSTAT */ -/* - * SCRUB_DONE (R) - * - * Description: Scrubber done. Controller sets this bit to 1, after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal scrub operation. The interrupt signal, sbr_done_intr, is equivalent to this status bitfield. - * Value After Reset: 0x0 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRSTAT_SCRUB_DONE_MASK (0x2U) -#define DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT (1U) -#define DDRCTL_SBRSTAT_SCRUB_DONE_GET(x) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_DONE_MASK) >> DDRCTL_SBRSTAT_SCRUB_DONE_SHIFT) - -/* - * SCRUB_BUSY (R) - * - * Description: Scrubber busy. Controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. - * Value After Reset: 0x0 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRSTAT_SCRUB_BUSY_MASK (0x1U) -#define DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT (0U) -#define DDRCTL_SBRSTAT_SCRUB_BUSY_GET(x) (((uint32_t)(x) & DDRCTL_SBRSTAT_SCRUB_BUSY_MASK) >> DDRCTL_SBRSTAT_SCRUB_BUSY_SHIFT) - -/* Bitfield definition for register: SBRWDATA0 */ -/* - * SCRUB_PATTERN0 (R/W) - * - * Description: ECC Scrubber write data pattern for data bus[31:0] - * Value After Reset: 0x0 - * Exists: UMCTL2_SBR_EN_1==1 - */ -#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK (0xFFFFFFFFUL) -#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT (0U) -#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SET(x) (((uint32_t)(x) << DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK) -#define DDRCTL_SBRWDATA0_SCRUB_PATTERN0_GET(x) (((uint32_t)(x) & DDRCTL_SBRWDATA0_SCRUB_PATTERN0_MASK) >> DDRCTL_SBRWDATA0_SCRUB_PATTERN0_SHIFT) - - - -/* ID register group index macro definition */ -#define DDRCTL_ID_0 (0UL) -#define DDRCTL_ID_1 (1UL) -#define DDRCTL_ID_2 (2UL) -#define DDRCTL_ID_3 (3UL) -#define DDRCTL_ID_4 (4UL) -#define DDRCTL_ID_5 (5UL) -#define DDRCTL_ID_6 (6UL) -#define DDRCTL_ID_7 (7UL) -#define DDRCTL_ID_8 (8UL) -#define DDRCTL_ID_9 (9UL) -#define DDRCTL_ID_10 (10UL) -#define DDRCTL_ID_11 (11UL) -#define DDRCTL_ID_12 (12UL) -#define DDRCTL_ID_13 (13UL) -#define DDRCTL_ID_14 (14UL) -#define DDRCTL_ID_15 (15UL) - -/* PCFG register group index macro definition */ -#define DDRCTL_PCFG_0 (0UL) -#define DDRCTL_PCFG_1 (1UL) -#define DDRCTL_PCFG_2 (2UL) -#define DDRCTL_PCFG_3 (3UL) -#define DDRCTL_PCFG_4 (4UL) -#define DDRCTL_PCFG_5 (5UL) -#define DDRCTL_PCFG_6 (6UL) -#define DDRCTL_PCFG_7 (7UL) -#define DDRCTL_PCFG_8 (8UL) -#define DDRCTL_PCFG_9 (9UL) -#define DDRCTL_PCFG_10 (10UL) -#define DDRCTL_PCFG_11 (11UL) -#define DDRCTL_PCFG_12 (12UL) -#define DDRCTL_PCFG_13 (13UL) -#define DDRCTL_PCFG_14 (14UL) -#define DDRCTL_PCFG_15 (15UL) - -/* SAR register group index macro definition */ -#define DDRCTL_SAR_0 (0UL) -#define DDRCTL_SAR_1 (1UL) -#define DDRCTL_SAR_2 (2UL) -#define DDRCTL_SAR_3 (3UL) - - -#endif /* HPM_DDRCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ddrphy_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ddrphy_regs.h deleted file mode 100644 index fa6b6e32ec1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ddrphy_regs.h +++ /dev/null @@ -1,5989 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DDRPHY_H -#define HPM_DDRPHY_H - -typedef struct { - __R uint32_t RIDR; /* 0x0: Revision Identification Register */ - __RW uint32_t PIR; /* 0x4: PHY Initialization Register (PIR) */ - __RW uint32_t PGCR0; /* 0x8: PHY General Configuration Registers 0-1 (PGCR0- 1) */ - __RW uint32_t PGCR1; /* 0xC: PHY General Configuration Registers 0-1 (PGCR0- 1) */ - __R uint32_t PGSR0; /* 0x10: “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 */ - __R uint32_t PGSR1; /* 0x14: “PHY General Status Registers 0-1 (PGSR0-1)” on page 89 */ - __RW uint32_t PLLCR; /* 0x18: “PLL Control Register (PLLCR)” on page 91 */ - __RW uint32_t PTR0; /* 0x1C: PHY Timing Registers 0-4 (PTR0-4) */ - __RW uint32_t PTR1; /* 0x20: PHY Timing Registers 0-4 (PTR0-4) */ - __RW uint32_t PTR2; /* 0x24: PHY Timing Registers 0-4 (PTR0-4) */ - __RW uint32_t PTR3; /* 0x28: PHY Timing Registers 0-4 (PTR0-4) */ - __RW uint32_t PTR4; /* 0x2C: PHY Timing Registers 0-4 (PTR0-4) */ - __RW uint32_t ACMDLR; /* 0x30: “AC Master Delay Line Register (ACMDLR)” on page 96 */ - __RW uint32_t ACBDLR; /* 0x34: “AC Bit Delay Line Register (ACBDLR)” on page 96 */ - __RW uint32_t ACIOCR; /* 0x38: “AC I/O Configuration Register (ACIOCR)” on page 97 */ - __RW uint32_t DXCCR; /* 0x3C: “DATX8 Common Configuration Register (DXCCR)” on page 99 */ - __RW uint32_t DSGCR; /* 0x40: “DDR System General Configuration Register (DSGCR)” on page 101 */ - __RW uint32_t DCR; /* 0x44: “DRAM Configuration Register (DCR)” on page 103 */ - __RW uint32_t DTPR0; /* 0x48: DRAM Timing Parameters Register 0-2 (DTPR0-2) */ - __RW uint32_t DTPR1; /* 0x4C: DRAM Timing Parameters Register 0-2 (DTPR0-2) */ - __RW uint32_t DTPR2; /* 0x50: DRAM Timing Parameters Register 0-2 (DTPR0-2) */ - union { - __RW uint32_t MR0; /* 0x54: “Mode Register 0 (MR0)” on page 108 */ - __RW uint32_t MR; /* 0x54: */ - }; - union { - __RW uint32_t MR1; /* 0x58: “Mode Register 1 (MR1)” on page 111 */ - __RW uint32_t EMR; /* 0x58: */ - }; - union { - __RW uint32_t MR2; /* 0x5C: “Mode Register 2/Extended Mode Register 2 (MR2/EMR2)” on page 114 */ - __RW uint32_t EMR2; /* 0x5C: */ - }; - union { - __RW uint32_t MR3; /* 0x60: “Mode Register 3 (MR3)” on page 116 */ - __RW uint32_t EMR3; /* 0x60: */ - }; - __RW uint32_t ODTCR; /* 0x64: “ODT Configuration Register (ODTCR)” on page 117 */ - __RW uint32_t DTCR; /* 0x68: “Data Training Configuration Register (DTCR)” on page 118 */ - __RW uint32_t DTAR0; /* 0x6C: Data Training Address Register 0-3 (DTAR0-3) */ - __RW uint32_t DTAR1; /* 0x70: Data Training Address Register 0-3 (DTAR0-3) */ - __RW uint32_t DTAR2; /* 0x74: Data Training Address Register 0-3 (DTAR0-3) */ - __RW uint32_t DTAR3; /* 0x78: Data Training Address Register 0-3 (DTAR0-3) */ - __RW uint32_t DTDR0; /* 0x7C: Data Training Eye Data Register 0-1 (DTEDR0-1) */ - __RW uint32_t DTDR1; /* 0x80: Data Training Eye Data Register 0-1 (DTEDR0-1) */ - __R uint32_t DTEDR0; /* 0x84: Data Training Eye Data Register 0-1 (DTEDR0-1) */ - __R uint32_t DTEDR1; /* 0x88: Data Training Eye Data Register 0-1 (DTEDR0-1) */ - __RW uint32_t PGCR2; /* 0x8C: “PHY General Configuration Register 2 (PGCR2)” on page 87 */ - __R uint8_t RESERVED0[32]; /* 0x90 - 0xAF: Reserved */ - __R uint32_t RDIMMGCR0; /* 0xB0: RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) */ - __R uint32_t RDIMMGCR1; /* 0xB4: RDIMM General Configuration Register 0-1 (RDIMMGCR0-1) */ - __R uint32_t RDIMMCR0; /* 0xB8: RDIMM Control Register 0-1 (RDIMMCR0-1) */ - __R uint32_t RDIMMCR1; /* 0xBC: RDIMM Control Register 0-1 (RDIMMCR0-1) */ - __RW uint32_t DCUAR; /* 0xC0: “DCU Address Register (DCUAR)” on page 129 */ - __RW uint32_t DCUDR; /* 0xC4: “DCU Data Register (DCUDR)” on page 130 */ - __RW uint32_t DCURR; /* 0xC8: “DCU Run Register (DCURR)” on page 130 */ - __RW uint32_t DCULR; /* 0xCC: “DCU Loop Register (DCULR)” on page 131 */ - __RW uint32_t DCUGCR; /* 0xD0: “DCU General Configuration Register (DCUGCR)” on page 132 */ - __RW uint32_t DCUTPR; /* 0xD4: “DCU Timing Parameter Register (DCUTPR)” on page 132 */ - __R uint32_t DCUSR0; /* 0xD8: DCU Status Register 0-1 (DCUSR0-1) */ - __R uint32_t DCUSR1; /* 0xDC: DCU Status Register 0-1 (DCUSR0-1) */ - __R uint8_t RESERVED1[32]; /* 0xE0 - 0xFF: Reserved */ - __RW uint32_t BISTRR; /* 0x100: “BIST Run Register (BISTRR)” on page 133 */ - __RW uint32_t BISTWCR; /* 0x104: “BIST Word Count Register (BISTWCR)” on page 136 */ - __RW uint32_t BISTMSKR0; /* 0x108: BIST Mask Register 0-2 (BISTMSKR0-2) */ - __RW uint32_t BISTMSKR1; /* 0x10C: BIST Mask Register 0-2 (BISTMSKR0-2) */ - __RW uint32_t BISTMSKR2; /* 0x110: BIST Mask Register 0-2 (BISTMSKR0-2) */ - __RW uint32_t BISTLSR; /* 0x114: “BIST LFSR Seed Register (BISTLSR)” on page 137 */ - __RW uint32_t BISTAR0; /* 0x118: BIST Address Register 0-2 (BISTAR0-2) */ - __RW uint32_t BISTAR1; /* 0x11C: BIST Address Register 0-2 (BISTAR0-2) */ - __RW uint32_t BISTAR2; /* 0x120: BIST Address Register 0-2 (BISTAR0-2) */ - __RW uint32_t BISTUDPR; /* 0x124: “BIST User Data Pattern Register (BISTUDPR)” on page 138 */ - __R uint32_t BISTGSR; /* 0x128: “BIST General Status Register (BISTGSR)” on page 139 */ - __R uint32_t BISTWER; /* 0x12C: “BIST Word Error Register (BISTWER)” on page 139 */ - __R uint32_t BISTBER0; /* 0x130: BIST Bit Error Register 0-3 (BISTBER0-3) */ - __R uint32_t BISTBER1; /* 0x134: BIST Bit Error Register 0-3 (BISTBER0-3) */ - __R uint32_t BISTBER2; /* 0x138: BIST Bit Error Register 0-3 (BISTBER0-3) */ - __R uint32_t BISTBER3; /* 0x13C: BIST Bit Error Register 0-3 (BISTBER0-3) */ - __R uint32_t BISTWCSR; /* 0x140: “BIST Word Count Status Register (BISTWCSR)” on page 141 */ - __R uint32_t BISTFWR0; /* 0x144: BIST Fail Word Register 0-2 (BISTFWR0-2) */ - __R uint32_t BISTFWR1; /* 0x148: BIST Fail Word Register 0-2 (BISTFWR0-2) */ - __R uint32_t BISTFWR2; /* 0x14C: BIST Fail Word Register 0-2 (BISTFWR0-2) */ - __R uint8_t RESERVED2[36]; /* 0x150 - 0x173: Reserved */ - __RW uint32_t AACR; /* 0x174: “Anti-Aging Control Register (AACR)” on page 143 */ - __RW uint32_t GPR0; /* 0x178: General Purpose Register 0-1 (GPR0-1) */ - __RW uint32_t GPR1; /* 0x17C: General Purpose Register 0-1 (GPR0-1) */ - struct { - __RW uint32_t CR0; /* 0x180: Impedance Control Register 0-1 (ZQnCR0-1) */ - __RW uint32_t CR1; /* 0x184: Impedance Control Register 0-1 (ZQnCR0-1) */ - __R uint32_t SR0; /* 0x188: Impedance Status Register 0-1 (ZQnSR0-1) */ - __R uint32_t SR1; /* 0x18C: Impedance Status Register 0-1 (ZQnSR0-1) */ - } ZQ[4]; - struct { - __RW uint32_t GCR; /* 0x1C0: “DATX8 General Configuration Register (DXnGCR)” on page 148 */ - __R uint32_t GSR0; /* 0x1C4: DATX8 General Status Registers 0-2 (DXnGSR0-2) */ - __R uint32_t GSR1; /* 0x1C8: DATX8 General Status Registers 0-2 (DXnGSR0-2) */ - __RW uint32_t BDLR0; /* 0x1CC: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t BDLR1; /* 0x1D0: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t BDLR2; /* 0x1D4: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t BDLR3; /* 0x1D8: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t BDLR4; /* 0x1DC: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t LCDLR0; /* 0x1E0: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t LCDLR1; /* 0x1E4: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t LCDLR2; /* 0x1E8: DATX8 Bit Delay Line Register 0-4 (DXnBDLR0-4) */ - __RW uint32_t MDLR; /* 0x1EC: “DATX8 Master Delay Line Register (DXnMDLR)” on page 157 */ - __RW uint32_t GTR; /* 0x1F0: “DATX8 General Timing Register (DXnGTR)” on page 159 */ - __RW uint32_t GSR2; /* 0x1F4: “DATX8 General Status Register 2 (DXnGSR2)” on page 152 */ - __R uint8_t RESERVED0[8]; /* 0x1F8 - 0x1FF: Reserved */ - } DX[9]; -} DDRPHY_Type; - - -/* Bitfield definition for register: RIDR */ -/* - * UDRID (R) - * - * User-Defined Revision ID: General purpose revision identification set by the user. - */ -#define DDRPHY_RIDR_UDRID_MASK (0xFF000000UL) -#define DDRPHY_RIDR_UDRID_SHIFT (24U) -#define DDRPHY_RIDR_UDRID_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_UDRID_MASK) >> DDRPHY_RIDR_UDRID_SHIFT) - -/* - * PHYMJR (R) - * - * PHY Major Revision: Indicates major revision of the PHY such addition of the features that make the new version not compatible with previous versions. - */ -#define DDRPHY_RIDR_PHYMJR_MASK (0xF00000UL) -#define DDRPHY_RIDR_PHYMJR_SHIFT (20U) -#define DDRPHY_RIDR_PHYMJR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMJR_MASK) >> DDRPHY_RIDR_PHYMJR_SHIFT) - -/* - * PHYMDR (R) - * - * PHY Moderate Revision: Indicates moderate revision of the PHY such as addition of new features. Normally the new version is still compatible with previous versions. - */ -#define DDRPHY_RIDR_PHYMDR_MASK (0xF0000UL) -#define DDRPHY_RIDR_PHYMDR_SHIFT (16U) -#define DDRPHY_RIDR_PHYMDR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMDR_MASK) >> DDRPHY_RIDR_PHYMDR_SHIFT) - -/* - * PHYMNR (R) - * - * PHY Minor Revision: Indicates minor update of the PHY such as bug fixes. Normally no new features are included. - */ -#define DDRPHY_RIDR_PHYMNR_MASK (0xF000U) -#define DDRPHY_RIDR_PHYMNR_SHIFT (12U) -#define DDRPHY_RIDR_PHYMNR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PHYMNR_MASK) >> DDRPHY_RIDR_PHYMNR_SHIFT) - -/* - * PUBMJR (R) - * - * PUB Major Revision: Indicates major revision of the PUB such addition of the features that make the new version not compatible with previous versions. - */ -#define DDRPHY_RIDR_PUBMJR_MASK (0xF00U) -#define DDRPHY_RIDR_PUBMJR_SHIFT (8U) -#define DDRPHY_RIDR_PUBMJR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMJR_MASK) >> DDRPHY_RIDR_PUBMJR_SHIFT) - -/* - * PUBMDR (R) - * - * PUB Moderate Revision: Indicates moderate revision of the PUB such as addition of new features. Normally the new version is still compatible with previous versions. - */ -#define DDRPHY_RIDR_PUBMDR_MASK (0xF0U) -#define DDRPHY_RIDR_PUBMDR_SHIFT (4U) -#define DDRPHY_RIDR_PUBMDR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMDR_MASK) >> DDRPHY_RIDR_PUBMDR_SHIFT) - -/* - * PUBMNR (R) - * - * PUB Minor Revision: Indicates minor update of the PUB such as bug fixes. Normally no new features are included. - */ -#define DDRPHY_RIDR_PUBMNR_MASK (0xFU) -#define DDRPHY_RIDR_PUBMNR_SHIFT (0U) -#define DDRPHY_RIDR_PUBMNR_GET(x) (((uint32_t)(x) & DDRPHY_RIDR_PUBMNR_MASK) >> DDRPHY_RIDR_PUBMNR_SHIFT) - -/* Bitfield definition for register: PIR */ -/* - * INITBYP (R/W) - * - * Initialization Bypass: Bypasses or stops, if set, all initialization routines currently running, including PHY initialization, DRAM initialization, and PHY training. - * Initialization may be triggered manually using INIT and the other relevant bits of the PIR register. This bit is self-clearing. - */ -#define DDRPHY_PIR_INITBYP_MASK (0x80000000UL) -#define DDRPHY_PIR_INITBYP_SHIFT (31U) -#define DDRPHY_PIR_INITBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_INITBYP_SHIFT) & DDRPHY_PIR_INITBYP_MASK) -#define DDRPHY_PIR_INITBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_INITBYP_MASK) >> DDRPHY_PIR_INITBYP_SHIFT) - -/* - * ZCALBYP (R/W) - * - * Impedance Calibration Bypass: Bypasses or stops, if set, impedance calibration of all ZQ control blocks that automatically triggers after reset. Impedance calibration may be triggered manually using INIT and ZCAL bits of the PIR register. This bit is self-clearing. - */ -#define DDRPHY_PIR_ZCALBYP_MASK (0x40000000UL) -#define DDRPHY_PIR_ZCALBYP_SHIFT (30U) -#define DDRPHY_PIR_ZCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ZCALBYP_SHIFT) & DDRPHY_PIR_ZCALBYP_MASK) -#define DDRPHY_PIR_ZCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ZCALBYP_MASK) >> DDRPHY_PIR_ZCALBYP_SHIFT) - -/* - * DCALBYP (R/W) - * - * Digital Delay Line (DDL) Calibration Bypass: Bypasses or stops, if set, DDL calibration that automatically triggers after reset. DDL calibration may be triggered manually using INIT and DCAL bits of the PIR register. This bit is self- clearing. - */ -#define DDRPHY_PIR_DCALBYP_MASK (0x20000000UL) -#define DDRPHY_PIR_DCALBYP_SHIFT (29U) -#define DDRPHY_PIR_DCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DCALBYP_SHIFT) & DDRPHY_PIR_DCALBYP_MASK) -#define DDRPHY_PIR_DCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DCALBYP_MASK) >> DDRPHY_PIR_DCALBYP_SHIFT) - -/* - * LOCKBYP (R/W) - * - * PLL Lock Bypass: Bypasses or stops, if set, the waiting of PLLs to lock. PLL lock wait is automatically triggered after reset. PLL lock wait may be triggered manually using INIT and PLLINIT bits of the PIR register. This bit is self-clearing. - */ -#define DDRPHY_PIR_LOCKBYP_MASK (0x10000000UL) -#define DDRPHY_PIR_LOCKBYP_SHIFT (28U) -#define DDRPHY_PIR_LOCKBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_LOCKBYP_SHIFT) & DDRPHY_PIR_LOCKBYP_MASK) -#define DDRPHY_PIR_LOCKBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_LOCKBYP_MASK) >> DDRPHY_PIR_LOCKBYP_SHIFT) - -/* - * CLRSR (R/W) - * - * Clear Status Registers: Writing 1 to this bit clears (reset to 0) select status bits in register PGSR0. - * This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when PGSR.IDONE=1, to manually clear a selection of the PGSR status bits, although starting a new initialization process (PIR[0].INIT = 1’b1) automatically clears the PGSR status bits associated with the initialization steps enabled. - * The following list describes which bits within the PGSR0 register are cleared when CLRSR is set to 1’b1 and which bits are not cleared: - * The following bits are not cleared by PIR[27] (CLRSR): - * PGSR0[31] (APLOCK) - * PGSR0[29:28] (PLDONE_CHN) - * PGSR0[23] (WLAERR) - * PGSR0[21] (WLERR) - * PGSR0[4] (DIDONE) - * PGSR0[2] (DCDONE) - * PGSR0[1] (PLDONE) - * PGSR0[0] (IDONE) - * The following bits are always zero: - * PGSR0[30] (reserved) - * PGSR0[19:12] (reserved) - * The following bits are cleared unconditionally by PIR[27] (CLRSR): - * PGSR0[27] (WEERR) - * PGSR0[26] (REERR) - * PGSR0[25] (WDERR) - * PGSR0[24] (RDERR) - * - PGSR0[22] (QSGERR) - * - PGSR0[20] (ZCERR) - * - PGSR0[11] (WEDONE) - * - PGSR0[10] (REDONE) - * - PGSR0[9] (WDDONE) - * - PGSR0[8] (RDDONE) - * - PGSR0[7] (WLADONE) - * - PGSR0[6] (QSGDONE) - * - PGSR0[5] (WLDONE) - * - PGSR0[3] (ZCDONE) - */ -#define DDRPHY_PIR_CLRSR_MASK (0x8000000UL) -#define DDRPHY_PIR_CLRSR_SHIFT (27U) -#define DDRPHY_PIR_CLRSR_SET(x) (((uint32_t)(x) << DDRPHY_PIR_CLRSR_SHIFT) & DDRPHY_PIR_CLRSR_MASK) -#define DDRPHY_PIR_CLRSR_GET(x) (((uint32_t)(x) & DDRPHY_PIR_CLRSR_MASK) >> DDRPHY_PIR_CLRSR_SHIFT) - -/* - * RDIMMINIT (R/W) - * - * RDIMM Initialization: Executes the RDIMM buffer chip initialization before executing DRAM initialization. The RDIMM buffer chip initialization is run after the DRAM is reset and CKE have been driven high by the DRAM initialization sequence. - */ -#define DDRPHY_PIR_RDIMMINIT_MASK (0x80000UL) -#define DDRPHY_PIR_RDIMMINIT_SHIFT (19U) -#define DDRPHY_PIR_RDIMMINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDIMMINIT_SHIFT) & DDRPHY_PIR_RDIMMINIT_MASK) -#define DDRPHY_PIR_RDIMMINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDIMMINIT_MASK) >> DDRPHY_PIR_RDIMMINIT_SHIFT) - -/* - * CTLDINIT (R/W) - * - * Controller DRAM Initialization: Indicates, if set, that DRAM initialization will be performed by the controller. Otherwise if not set it indicates that DRAM initialization will be performed using the built-in initialization sequence or using software through the configuration port. - */ -#define DDRPHY_PIR_CTLDINIT_MASK (0x40000UL) -#define DDRPHY_PIR_CTLDINIT_SHIFT (18U) -#define DDRPHY_PIR_CTLDINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_CTLDINIT_SHIFT) & DDRPHY_PIR_CTLDINIT_MASK) -#define DDRPHY_PIR_CTLDINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_CTLDINIT_MASK) >> DDRPHY_PIR_CTLDINIT_SHIFT) - -/* - * PLLBYP (R/W) - * - * PLL Bypass: A setting of 1 on this bit will put all PHY PLLs in bypass mode. - */ -#define DDRPHY_PIR_PLLBYP_MASK (0x20000UL) -#define DDRPHY_PIR_PLLBYP_SHIFT (17U) -#define DDRPHY_PIR_PLLBYP_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PLLBYP_SHIFT) & DDRPHY_PIR_PLLBYP_MASK) -#define DDRPHY_PIR_PLLBYP_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PLLBYP_MASK) >> DDRPHY_PIR_PLLBYP_SHIFT) - -/* - * ICPC (R/W) - * - * Initialization Complete Pin Configuration: Specifies how the DFI initialization complete output pin (dfi_init_complete) should be used to indicate the status of initialization. Valid value are: - * 0 = Asserted after PHY initialization (DLL locking and impedance calibration) is complete. - * 1 = Asserted after PHY initialization is complete and the triggered the PUB initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. - */ -#define DDRPHY_PIR_ICPC_MASK (0x10000UL) -#define DDRPHY_PIR_ICPC_SHIFT (16U) -#define DDRPHY_PIR_ICPC_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ICPC_SHIFT) & DDRPHY_PIR_ICPC_MASK) -#define DDRPHY_PIR_ICPC_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ICPC_MASK) >> DDRPHY_PIR_ICPC_SHIFT) - -/* - * WREYE (R/W) - * - * Write Data Eye Training: Executes a PUB training routine to maximize the write data eye. - */ -#define DDRPHY_PIR_WREYE_MASK (0x8000U) -#define DDRPHY_PIR_WREYE_SHIFT (15U) -#define DDRPHY_PIR_WREYE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WREYE_SHIFT) & DDRPHY_PIR_WREYE_MASK) -#define DDRPHY_PIR_WREYE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WREYE_MASK) >> DDRPHY_PIR_WREYE_SHIFT) - -/* - * RDEYE (R/W) - * - * Read Data Eye Training: Executes a PUB training routine to maximize the read data eye. - */ -#define DDRPHY_PIR_RDEYE_MASK (0x4000U) -#define DDRPHY_PIR_RDEYE_SHIFT (14U) -#define DDRPHY_PIR_RDEYE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDEYE_SHIFT) & DDRPHY_PIR_RDEYE_MASK) -#define DDRPHY_PIR_RDEYE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDEYE_MASK) >> DDRPHY_PIR_RDEYE_SHIFT) - -/* - * WRDSKW (R/W) - * - * Write Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during write. - */ -#define DDRPHY_PIR_WRDSKW_MASK (0x2000U) -#define DDRPHY_PIR_WRDSKW_SHIFT (13U) -#define DDRPHY_PIR_WRDSKW_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WRDSKW_SHIFT) & DDRPHY_PIR_WRDSKW_MASK) -#define DDRPHY_PIR_WRDSKW_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WRDSKW_MASK) >> DDRPHY_PIR_WRDSKW_SHIFT) - -/* - * RDDSKW (R/W) - * - * Read Data Bit Deskew: Executes a PUB training routine to deskew the DQ bits during read. - */ -#define DDRPHY_PIR_RDDSKW_MASK (0x1000U) -#define DDRPHY_PIR_RDDSKW_SHIFT (12U) -#define DDRPHY_PIR_RDDSKW_SET(x) (((uint32_t)(x) << DDRPHY_PIR_RDDSKW_SHIFT) & DDRPHY_PIR_RDDSKW_MASK) -#define DDRPHY_PIR_RDDSKW_GET(x) (((uint32_t)(x) & DDRPHY_PIR_RDDSKW_MASK) >> DDRPHY_PIR_RDDSKW_SHIFT) - -/* - * WLADJ (R/W) - * - * Write Leveling Adjust (DDR3 Only): Executes a PUB training routine that re- adjusts the write latency used during write in case the write leveling routine changed the expected latency. - * Note: Ensure that the DCU command cache is cleared prior to running WLADJ. - */ -#define DDRPHY_PIR_WLADJ_MASK (0x800U) -#define DDRPHY_PIR_WLADJ_SHIFT (11U) -#define DDRPHY_PIR_WLADJ_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WLADJ_SHIFT) & DDRPHY_PIR_WLADJ_MASK) -#define DDRPHY_PIR_WLADJ_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WLADJ_MASK) >> DDRPHY_PIR_WLADJ_SHIFT) - -/* - * QSGATE (R/W) - * - * Read DQS Gate Training: Executes a PUB training routine to determine the optimum position of the read data DQS strobe for maximum system timing margins. - */ -#define DDRPHY_PIR_QSGATE_MASK (0x400U) -#define DDRPHY_PIR_QSGATE_SHIFT (10U) -#define DDRPHY_PIR_QSGATE_SET(x) (((uint32_t)(x) << DDRPHY_PIR_QSGATE_SHIFT) & DDRPHY_PIR_QSGATE_MASK) -#define DDRPHY_PIR_QSGATE_GET(x) (((uint32_t)(x) & DDRPHY_PIR_QSGATE_MASK) >> DDRPHY_PIR_QSGATE_SHIFT) - -/* - * WL (R/W) - * - * Write Leveling (DDR3 Only): Executes a PUB write leveling routine. - */ -#define DDRPHY_PIR_WL_MASK (0x200U) -#define DDRPHY_PIR_WL_SHIFT (9U) -#define DDRPHY_PIR_WL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_WL_SHIFT) & DDRPHY_PIR_WL_MASK) -#define DDRPHY_PIR_WL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_WL_MASK) >> DDRPHY_PIR_WL_SHIFT) - -/* - * DRAMINIT (R/W) - * - * DRAM Initialization: Executes the DRAM initialization sequence. - */ -#define DDRPHY_PIR_DRAMINIT_MASK (0x100U) -#define DDRPHY_PIR_DRAMINIT_SHIFT (8U) -#define DDRPHY_PIR_DRAMINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DRAMINIT_SHIFT) & DDRPHY_PIR_DRAMINIT_MASK) -#define DDRPHY_PIR_DRAMINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DRAMINIT_MASK) >> DDRPHY_PIR_DRAMINIT_SHIFT) - -/* - * DRAMRST (R/W) - * - * DRAM Reset (DDR3 Only): Issues a reset to the DRAM (by driving the DRAM reset pin low) and wait 200us. This can be triggered in isolation or with the full DRAM initialization (DRAMINIT). For the later case, the reset is issued and 200us is waited before starting the full initialization sequence. - */ -#define DDRPHY_PIR_DRAMRST_MASK (0x80U) -#define DDRPHY_PIR_DRAMRST_SHIFT (7U) -#define DDRPHY_PIR_DRAMRST_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DRAMRST_SHIFT) & DDRPHY_PIR_DRAMRST_MASK) -#define DDRPHY_PIR_DRAMRST_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DRAMRST_MASK) >> DDRPHY_PIR_DRAMRST_SHIFT) - -/* - * PHYRST (R/W) - * - * PHY Reset: Resets the AC and DATX8 modules by asserting the AC/DATX8 reset pin. - */ -#define DDRPHY_PIR_PHYRST_MASK (0x40U) -#define DDRPHY_PIR_PHYRST_SHIFT (6U) -#define DDRPHY_PIR_PHYRST_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PHYRST_SHIFT) & DDRPHY_PIR_PHYRST_MASK) -#define DDRPHY_PIR_PHYRST_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PHYRST_MASK) >> DDRPHY_PIR_PHYRST_SHIFT) - -/* - * DCAL (R/W) - * - * Digital Delay Line (DDL) Calibration: Performs PHY delay line calibration. - */ -#define DDRPHY_PIR_DCAL_MASK (0x20U) -#define DDRPHY_PIR_DCAL_SHIFT (5U) -#define DDRPHY_PIR_DCAL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_DCAL_SHIFT) & DDRPHY_PIR_DCAL_MASK) -#define DDRPHY_PIR_DCAL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_DCAL_MASK) >> DDRPHY_PIR_DCAL_SHIFT) - -/* - * PLLINIT (R/W) - * - * PLL Initialization: Executes the PLL initialization sequence which includes correct driving of PLL power-down, reset and gear shift pins, and then waiting for the PHY PLLs to lock. - */ -#define DDRPHY_PIR_PLLINIT_MASK (0x10U) -#define DDRPHY_PIR_PLLINIT_SHIFT (4U) -#define DDRPHY_PIR_PLLINIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_PLLINIT_SHIFT) & DDRPHY_PIR_PLLINIT_MASK) -#define DDRPHY_PIR_PLLINIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_PLLINIT_MASK) >> DDRPHY_PIR_PLLINIT_SHIFT) - -/* - * ZCAL (R/W) - * - * Impedance Calibration: Performs PHY impedance calibration. When set the impedance calibration will be performed in parallel with PHY initialization (PLL initialization + DDL calibration + PHY reset). - */ -#define DDRPHY_PIR_ZCAL_MASK (0x2U) -#define DDRPHY_PIR_ZCAL_SHIFT (1U) -#define DDRPHY_PIR_ZCAL_SET(x) (((uint32_t)(x) << DDRPHY_PIR_ZCAL_SHIFT) & DDRPHY_PIR_ZCAL_MASK) -#define DDRPHY_PIR_ZCAL_GET(x) (((uint32_t)(x) & DDRPHY_PIR_ZCAL_MASK) >> DDRPHY_PIR_ZCAL_SHIFT) - -/* - * INIT (R/W) - * - * Initialization Trigger: A write of '1' to this bit triggers the DDR system initialization, including PHY initialization, DRAM initialization, and PHY training. The exact initialization steps to be executed are specified in bits 1 to 15 of this register. A bit setting of 1 means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing. - */ -#define DDRPHY_PIR_INIT_MASK (0x1U) -#define DDRPHY_PIR_INIT_SHIFT (0U) -#define DDRPHY_PIR_INIT_SET(x) (((uint32_t)(x) << DDRPHY_PIR_INIT_SHIFT) & DDRPHY_PIR_INIT_MASK) -#define DDRPHY_PIR_INIT_GET(x) (((uint32_t)(x) & DDRPHY_PIR_INIT_MASK) >> DDRPHY_PIR_INIT_SHIFT) - -/* Bitfield definition for register: PGCR0 */ -/* - * CKEN (R/W) - * - * CK Enable: Controls whether the CK going to the SDRAM is enabled (toggling) or disabled (static value) and whether the CK is inverted. Two bits for each of the up to three CK pairs. Valid values for the two bits are: - * 00 = CK disabled (Driven to constant 0) 01 = CK toggling with inverted polarity - * 10 = CK toggling with normal polarity (This should be the default setting) 11 = CK disabled (Driven to constant 1) - */ -#define DDRPHY_PGCR0_CKEN_MASK (0xFC000000UL) -#define DDRPHY_PGCR0_CKEN_SHIFT (26U) -#define DDRPHY_PGCR0_CKEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_CKEN_SHIFT) & DDRPHY_PGCR0_CKEN_MASK) -#define DDRPHY_PGCR0_CKEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_CKEN_MASK) >> DDRPHY_PGCR0_CKEN_SHIFT) - -/* - * PUBMODE (R/W) - * - * Enables, if set, the PUB to control the interface to the PHY and SDRAM. In this mode the DFI commands from the controller are ignored. The bit must be set to 0 after the system determines it is convenient to pass control of the DFI bus to the controller. When set to 0 the DFI interface has control of the PHY and SDRAM interface except when triggering pub operations such as BIST, DCU or data training. - */ -#define DDRPHY_PGCR0_PUBMODE_MASK (0x2000000UL) -#define DDRPHY_PGCR0_PUBMODE_SHIFT (25U) -#define DDRPHY_PGCR0_PUBMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_PUBMODE_SHIFT) & DDRPHY_PGCR0_PUBMODE_MASK) -#define DDRPHY_PGCR0_PUBMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_PUBMODE_MASK) >> DDRPHY_PGCR0_PUBMODE_SHIFT) - -/* - * DTOSEL (R/W) - * - * Digital Test Output Select: Selects the PHY digital test output that is driven onto PHY digital test output (phy_dto) pin: Valid values are: - * 00000 = DATX8 0 PLL digital test output 00001 = DATX8 1 PLL digital test output 00010 = DATX8 2 PLL digital test output 00011 = DATX8 3 PLL digital test output 00100 = DATX8 4 PLL digital test output 00101 = DATX8 5 PLL digital test output 00110 = DATX8 6 PLL digital test output 00111 = DATX8 7 PLL digital test output 01000 = DATX8 8 PLL digital test output 01001 = AC PLL digital test output 01010 – 01111 = Reserved - * 10000 = DATX8 0 delay line digital test output 10001 = DATX8 1 delay line digital test output 10010 = DATX8 2 delay line digital test output 10011 = DATX8 3 delay line digital test output 10100 = DATX8 4 delay line digital test output 10101 = DATX8 5 delay line digital test output 10110 = DATX8 6 delay line digital test output 10111 = DATX8 7 delay line digital test output 11000 = DATX8 8 delay line digital test output 11001 = AC delay line digital test output 11010 – 11111 = Reserved - */ -#define DDRPHY_PGCR0_DTOSEL_MASK (0x7C000UL) -#define DDRPHY_PGCR0_DTOSEL_SHIFT (14U) -#define DDRPHY_PGCR0_DTOSEL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DTOSEL_SHIFT) & DDRPHY_PGCR0_DTOSEL_MASK) -#define DDRPHY_PGCR0_DTOSEL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DTOSEL_MASK) >> DDRPHY_PGCR0_DTOSEL_SHIFT) - -/* - * OSCWDL (R/W) - * - * Oscillator Mode Write-Leveling Delay Line Select: Selects which of the two write leveling LCDLs is active. The delay select value of the inactive LCDL is set to zero while the delay select value of the active LCDL can be varied by the input write leveling delay select pin. Valid values are: - * 00 = No WL LCDL is active 01 = DDR WL LCDL is active 10 = SDR WL LCDL is active 11 = Both LCDLs are active - */ -#define DDRPHY_PGCR0_OSCWDL_MASK (0x3000U) -#define DDRPHY_PGCR0_OSCWDL_SHIFT (12U) -#define DDRPHY_PGCR0_OSCWDL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCWDL_SHIFT) & DDRPHY_PGCR0_OSCWDL_MASK) -#define DDRPHY_PGCR0_OSCWDL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCWDL_MASK) >> DDRPHY_PGCR0_OSCWDL_SHIFT) - -/* - * OSCDIV (R/W) - * - * Oscillator Mode Division: Specifies the factor by which the delay line oscillator mode output is divided down before it is output on the delay line digital test output pin dl_dto. Valid values are: - * 000 = Divide by 1 - * 001 = Divide by 256 - * 010 = Divide by 512 - * 011 = Divide by 1024 - * 100 = Divide by 2048 - * 101 = Divide by 4096 - * 110 = Divide by 8192 - * 111 = Divide by 65536 - */ -#define DDRPHY_PGCR0_OSCDIV_MASK (0xE00U) -#define DDRPHY_PGCR0_OSCDIV_SHIFT (9U) -#define DDRPHY_PGCR0_OSCDIV_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCDIV_SHIFT) & DDRPHY_PGCR0_OSCDIV_MASK) -#define DDRPHY_PGCR0_OSCDIV_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCDIV_MASK) >> DDRPHY_PGCR0_OSCDIV_SHIFT) - -/* - * OSCEN (R/W) - * - * Oscillator Enable: Enables, if set, the delay line oscillation. - */ -#define DDRPHY_PGCR0_OSCEN_MASK (0x100U) -#define DDRPHY_PGCR0_OSCEN_SHIFT (8U) -#define DDRPHY_PGCR0_OSCEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_OSCEN_SHIFT) & DDRPHY_PGCR0_OSCEN_MASK) -#define DDRPHY_PGCR0_OSCEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_OSCEN_MASK) >> DDRPHY_PGCR0_OSCEN_SHIFT) - -/* - * DLTST (R/W) - * - * Delay Line Test Start: A write of '1' to this bit will trigger delay line oscillator mode period measurement. This bit is not self clearing and needs to be reset to '0' before the measurement can be re-triggered. - */ -#define DDRPHY_PGCR0_DLTST_MASK (0x80U) -#define DDRPHY_PGCR0_DLTST_SHIFT (7U) -#define DDRPHY_PGCR0_DLTST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DLTST_SHIFT) & DDRPHY_PGCR0_DLTST_MASK) -#define DDRPHY_PGCR0_DLTST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DLTST_MASK) >> DDRPHY_PGCR0_DLTST_SHIFT) - -/* - * DLTMODE (R/W) - * - * Delay Line Test Mode: Selects, if set, the delay line oscillator test mode. Setting this bit also clears all delay line register values. For DL oscillator testing, first set this bit, then apply desired non-zero LCDL and BDL register programmings. - */ -#define DDRPHY_PGCR0_DLTMODE_MASK (0x40U) -#define DDRPHY_PGCR0_DLTMODE_SHIFT (6U) -#define DDRPHY_PGCR0_DLTMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_DLTMODE_SHIFT) & DDRPHY_PGCR0_DLTMODE_MASK) -#define DDRPHY_PGCR0_DLTMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_DLTMODE_MASK) >> DDRPHY_PGCR0_DLTMODE_SHIFT) - -/* - * RDBVT (R/W) - * - * Read Data BDL VT Compensation: Enables, if set, the VT drift compensation of the read data bit delay lines. - */ -#define DDRPHY_PGCR0_RDBVT_MASK (0x20U) -#define DDRPHY_PGCR0_RDBVT_SHIFT (5U) -#define DDRPHY_PGCR0_RDBVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RDBVT_SHIFT) & DDRPHY_PGCR0_RDBVT_MASK) -#define DDRPHY_PGCR0_RDBVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RDBVT_MASK) >> DDRPHY_PGCR0_RDBVT_SHIFT) - -/* - * WDBVT (R/W) - * - * Write Data BDL VT Compensation: Enables, if set, the VT drift compensation of the write data bit delay lines. - */ -#define DDRPHY_PGCR0_WDBVT_MASK (0x10U) -#define DDRPHY_PGCR0_WDBVT_SHIFT (4U) -#define DDRPHY_PGCR0_WDBVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WDBVT_SHIFT) & DDRPHY_PGCR0_WDBVT_MASK) -#define DDRPHY_PGCR0_WDBVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WDBVT_MASK) >> DDRPHY_PGCR0_WDBVT_SHIFT) - -/* - * RGLVT (R/W) - * - * Read DQS Gating LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS gating LCDL. - */ -#define DDRPHY_PGCR0_RGLVT_MASK (0x8U) -#define DDRPHY_PGCR0_RGLVT_SHIFT (3U) -#define DDRPHY_PGCR0_RGLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RGLVT_SHIFT) & DDRPHY_PGCR0_RGLVT_MASK) -#define DDRPHY_PGCR0_RGLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RGLVT_MASK) >> DDRPHY_PGCR0_RGLVT_SHIFT) - -/* - * RDLVT (R/W) - * - * Read DQS LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the read DQS LCDL. - */ -#define DDRPHY_PGCR0_RDLVT_MASK (0x4U) -#define DDRPHY_PGCR0_RDLVT_SHIFT (2U) -#define DDRPHY_PGCR0_RDLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_RDLVT_SHIFT) & DDRPHY_PGCR0_RDLVT_MASK) -#define DDRPHY_PGCR0_RDLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_RDLVT_MASK) >> DDRPHY_PGCR0_RDLVT_SHIFT) - -/* - * WDLVT (R/W) - * - * Write DQ LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write DQ LCDL. - */ -#define DDRPHY_PGCR0_WDLVT_MASK (0x2U) -#define DDRPHY_PGCR0_WDLVT_SHIFT (1U) -#define DDRPHY_PGCR0_WDLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WDLVT_SHIFT) & DDRPHY_PGCR0_WDLVT_MASK) -#define DDRPHY_PGCR0_WDLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WDLVT_MASK) >> DDRPHY_PGCR0_WDLVT_SHIFT) - -/* - * WLLVT (R/W) - * - * Write Leveling LCDL Delay VT Compensation: Enables, if set, the VT drift compensation of the write leveling LCDL. - */ -#define DDRPHY_PGCR0_WLLVT_MASK (0x1U) -#define DDRPHY_PGCR0_WLLVT_SHIFT (0U) -#define DDRPHY_PGCR0_WLLVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR0_WLLVT_SHIFT) & DDRPHY_PGCR0_WLLVT_MASK) -#define DDRPHY_PGCR0_WLLVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR0_WLLVT_MASK) >> DDRPHY_PGCR0_WLLVT_SHIFT) - -/* Bitfield definition for register: PGCR1 */ -/* - * LBMODE (R/W) - * - * Loopback Mode: Indicates, if set, that the PHY/PUB is in loopback mode. - */ -#define DDRPHY_PGCR1_LBMODE_MASK (0x80000000UL) -#define DDRPHY_PGCR1_LBMODE_SHIFT (31U) -#define DDRPHY_PGCR1_LBMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBMODE_SHIFT) & DDRPHY_PGCR1_LBMODE_MASK) -#define DDRPHY_PGCR1_LBMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBMODE_MASK) >> DDRPHY_PGCR1_LBMODE_SHIFT) - -/* - * LBGDQS (R/W) - * - * Loopback DQS Gating: Selects the DQS gating mode that should be used when the PHY is in loopback mode, including BIST loopback mode. Valid values are: - * 00 = DQS gate is always on - * 01 = DQS gate training will be triggered on the PUB 10 = DQS gate is set manually using software - * 11 = Reserved - */ -#define DDRPHY_PGCR1_LBGDQS_MASK (0x60000000UL) -#define DDRPHY_PGCR1_LBGDQS_SHIFT (29U) -#define DDRPHY_PGCR1_LBGDQS_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBGDQS_SHIFT) & DDRPHY_PGCR1_LBGDQS_MASK) -#define DDRPHY_PGCR1_LBGDQS_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBGDQS_MASK) >> DDRPHY_PGCR1_LBGDQS_SHIFT) - -/* - * LBDQSS (R/W) - * - * Loopback DQS Shift: Selects how the read DQS is shifted during loopback to ensure that the read DQS is centered into the read data eye. Valid values are: - * 1b0 = PUB sets the read DQS LCDL to 0 (internally). DQS is already shifted 90 degrees by write path - * 1b1 = The read DQS shift is set manually through software - */ -#define DDRPHY_PGCR1_LBDQSS_MASK (0x10000000UL) -#define DDRPHY_PGCR1_LBDQSS_SHIFT (28U) -#define DDRPHY_PGCR1_LBDQSS_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LBDQSS_SHIFT) & DDRPHY_PGCR1_LBDQSS_MASK) -#define DDRPHY_PGCR1_LBDQSS_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LBDQSS_MASK) >> DDRPHY_PGCR1_LBDQSS_SHIFT) - -/* - * IOLB (R/W) - * - * I/O Loop-Back Select: Selects where inside the I/O the loop-back of signals happens. Valid values are: - * 0 = Loopback is after output buffer; output enable must be asserted 1 = Loopback is before output buffer; output enable is don’t care - */ -#define DDRPHY_PGCR1_IOLB_MASK (0x8000000UL) -#define DDRPHY_PGCR1_IOLB_SHIFT (27U) -#define DDRPHY_PGCR1_IOLB_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_IOLB_SHIFT) & DDRPHY_PGCR1_IOLB_MASK) -#define DDRPHY_PGCR1_IOLB_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_IOLB_MASK) >> DDRPHY_PGCR1_IOLB_SHIFT) - -/* - * INHVT (R/W) - * - * VT Calculation Inhibit: Inhibits calculation of the next VT compensated delay line values. A value of 1 will inhibit the VT calculation. This bit should be set to 1 during writes to the delay line registers. - */ -#define DDRPHY_PGCR1_INHVT_MASK (0x4000000UL) -#define DDRPHY_PGCR1_INHVT_SHIFT (26U) -#define DDRPHY_PGCR1_INHVT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_INHVT_SHIFT) & DDRPHY_PGCR1_INHVT_MASK) -#define DDRPHY_PGCR1_INHVT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_INHVT_MASK) >> DDRPHY_PGCR1_INHVT_SHIFT) - -/* - * DXHRST (R/W) - * - * DX PHY High-Speed Reset: a Write of '0' to this bit resets the DX macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. - */ -#define DDRPHY_PGCR1_DXHRST_MASK (0x2000000UL) -#define DDRPHY_PGCR1_DXHRST_SHIFT (25U) -#define DDRPHY_PGCR1_DXHRST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_DXHRST_SHIFT) & DDRPHY_PGCR1_DXHRST_MASK) -#define DDRPHY_PGCR1_DXHRST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_DXHRST_MASK) >> DDRPHY_PGCR1_DXHRST_SHIFT) - -/* - * ZCKSEL (R/W) - * - * Impedance Clock Divider Select: Selects the divide ratio for the clock used by the impedance control logic relative to the clock used by the memory controller and SDRAM. - * Valid values are: - * 00 = Divide by 2 - * 01 = Divide by 8 - * 10 = Divide by 32 - * 11 = Divide by 64 - * For more information, refer to “Impedance Calibration” on page 174. - */ -#define DDRPHY_PGCR1_ZCKSEL_MASK (0x1800000UL) -#define DDRPHY_PGCR1_ZCKSEL_SHIFT (23U) -#define DDRPHY_PGCR1_ZCKSEL_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_ZCKSEL_SHIFT) & DDRPHY_PGCR1_ZCKSEL_MASK) -#define DDRPHY_PGCR1_ZCKSEL_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_ZCKSEL_MASK) >> DDRPHY_PGCR1_ZCKSEL_SHIFT) - -/* - * DLDLMT (R/W) - * - * Delay Line VT Drift Limit: Specifies the minimum change in the delay line VT drift in one direction which should result in the assertion of the delay line VT drift status signal (vt_drift). The limit is specified in terms of delay select values. A value of 0 disables the assertion of delay line VT drift status signal. - */ -#define DDRPHY_PGCR1_DLDLMT_MASK (0x7F8000UL) -#define DDRPHY_PGCR1_DLDLMT_SHIFT (15U) -#define DDRPHY_PGCR1_DLDLMT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_DLDLMT_SHIFT) & DDRPHY_PGCR1_DLDLMT_MASK) -#define DDRPHY_PGCR1_DLDLMT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_DLDLMT_MASK) >> DDRPHY_PGCR1_DLDLMT_SHIFT) - -/* - * FDEPTH (R/W) - * - * Filter Depth: Specifies the number of measurements over which all AC and DATX8 initial period measurements, that happen after reset or when calibration is manually triggered, are averaged. Valid values are: - * 00 = 2 - * 01 = 4 - * 10 = 8 - * 11 = 16 - */ -#define DDRPHY_PGCR1_FDEPTH_MASK (0x6000U) -#define DDRPHY_PGCR1_FDEPTH_SHIFT (13U) -#define DDRPHY_PGCR1_FDEPTH_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_FDEPTH_SHIFT) & DDRPHY_PGCR1_FDEPTH_MASK) -#define DDRPHY_PGCR1_FDEPTH_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_FDEPTH_MASK) >> DDRPHY_PGCR1_FDEPTH_SHIFT) - -/* - * LPFDEPTH (R/W) - * - * Low-Pass Filter Depth: Specifies the number of measurements over which MDL period measurements are filtered. This determines the time constant of the low pass filter. Valid values are: - * 00 = 2 - * 01 = 4 - * 10 = 8 - * 11 = 16 - */ -#define DDRPHY_PGCR1_LPFDEPTH_MASK (0x1800U) -#define DDRPHY_PGCR1_LPFDEPTH_SHIFT (11U) -#define DDRPHY_PGCR1_LPFDEPTH_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LPFDEPTH_SHIFT) & DDRPHY_PGCR1_LPFDEPTH_MASK) -#define DDRPHY_PGCR1_LPFDEPTH_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LPFDEPTH_MASK) >> DDRPHY_PGCR1_LPFDEPTH_SHIFT) - -/* - * LPFEN (R/W) - * - * Low-Pass Filter Enable: Enables, if set, the low pass filtering of MDL period measurements. - */ -#define DDRPHY_PGCR1_LPFEN_MASK (0x400U) -#define DDRPHY_PGCR1_LPFEN_SHIFT (10U) -#define DDRPHY_PGCR1_LPFEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_LPFEN_SHIFT) & DDRPHY_PGCR1_LPFEN_MASK) -#define DDRPHY_PGCR1_LPFEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_LPFEN_MASK) >> DDRPHY_PGCR1_LPFEN_SHIFT) - -/* - * MDLEN (R/W) - * - * Master Delay Line Enable: Enables, if set, the AC master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. - */ -#define DDRPHY_PGCR1_MDLEN_MASK (0x200U) -#define DDRPHY_PGCR1_MDLEN_SHIFT (9U) -#define DDRPHY_PGCR1_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_MDLEN_SHIFT) & DDRPHY_PGCR1_MDLEN_MASK) -#define DDRPHY_PGCR1_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_MDLEN_MASK) >> DDRPHY_PGCR1_MDLEN_SHIFT) - -/* - * IODDRM (R/W) - * - * I/O DDR Mode (D3F I/O Only): Selects the DDR mode for the I/Os. These bits connect to bits [2:1] of the IOM pin of the SSTL I/O. For more information, refer to the SSTL I/O chapter in the DWC DDR PHY Databook. - */ -#define DDRPHY_PGCR1_IODDRM_MASK (0x180U) -#define DDRPHY_PGCR1_IODDRM_SHIFT (7U) -#define DDRPHY_PGCR1_IODDRM_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_IODDRM_SHIFT) & DDRPHY_PGCR1_IODDRM_MASK) -#define DDRPHY_PGCR1_IODDRM_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_IODDRM_MASK) >> DDRPHY_PGCR1_IODDRM_SHIFT) - -/* - * WLSELT (R/W) - * - * Write Leveling Select Type: Selects the encoding type for the write leveling select signal depending on the desired setup/hold margins for the internal pipelines. Refer to the DDR PHY Databook for details of how the select type is used. Valid values are: - * 0 = Type 1: Setup margin of 90 degrees and hold margin of 90 degrees 1 = Type 2: Setup margin of 135 degrees and hold margin of 45 degrees - */ -#define DDRPHY_PGCR1_WLSELT_MASK (0x40U) -#define DDRPHY_PGCR1_WLSELT_SHIFT (6U) -#define DDRPHY_PGCR1_WLSELT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLSELT_SHIFT) & DDRPHY_PGCR1_WLSELT_MASK) -#define DDRPHY_PGCR1_WLSELT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLSELT_MASK) >> DDRPHY_PGCR1_WLSELT_SHIFT) - -/* - * ACHRST (R/W) - * - * AC PHY High-Speed Reset: a Write of '0' to this bit resets the AC macro without resetting the PUB RTL logic. This bit is not self-clearing and a '1' must be written to de-assert the reset. - */ -#define DDRPHY_PGCR1_ACHRST_MASK (0x20U) -#define DDRPHY_PGCR1_ACHRST_SHIFT (5U) -#define DDRPHY_PGCR1_ACHRST_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_ACHRST_SHIFT) & DDRPHY_PGCR1_ACHRST_MASK) -#define DDRPHY_PGCR1_ACHRST_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_ACHRST_MASK) >> DDRPHY_PGCR1_ACHRST_SHIFT) - -/* - * WSLOPT (R/W) - * - * Write System Latency Optimization: controls the insertion of a pipeline stage on the AC signals from the DFI interface to the PHY to cater for a negative write system latency (WSL) value (only -1 possible). - * 0x0 = A pipeline stage is inserted only if WL2 training results in a WSL of -1 for any rank - * 0x1 = Inserts a pipeline stage - */ -#define DDRPHY_PGCR1_WSLOPT_MASK (0x10U) -#define DDRPHY_PGCR1_WSLOPT_SHIFT (4U) -#define DDRPHY_PGCR1_WSLOPT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WSLOPT_SHIFT) & DDRPHY_PGCR1_WSLOPT_MASK) -#define DDRPHY_PGCR1_WSLOPT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WSLOPT_MASK) >> DDRPHY_PGCR1_WSLOPT_SHIFT) - -/* - * WLSTEP (R/W) - * - * Write Leveling Step: Specifies the number of delay step-size increments during each step of write leveling. Valid values are: - * 0 = computed to be 1/2 of the associated lane's DXnGSR0.WLPRD value 1 = 1 step size - */ -#define DDRPHY_PGCR1_WLSTEP_MASK (0x4U) -#define DDRPHY_PGCR1_WLSTEP_SHIFT (2U) -#define DDRPHY_PGCR1_WLSTEP_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLSTEP_SHIFT) & DDRPHY_PGCR1_WLSTEP_MASK) -#define DDRPHY_PGCR1_WLSTEP_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLSTEP_MASK) >> DDRPHY_PGCR1_WLSTEP_SHIFT) - -/* - * WLMODE (R/W) - * - * Write Leveling (Software) Mode: Indicates, if set, that the PUB is in software write leveling mode in which software executes single steps of DQS pulsing by writing '1' to PIR.WL. The write leveling DQ status from the DRAM is captured in DXnGSR0.WLDQ. - */ -#define DDRPHY_PGCR1_WLMODE_MASK (0x2U) -#define DDRPHY_PGCR1_WLMODE_SHIFT (1U) -#define DDRPHY_PGCR1_WLMODE_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_WLMODE_SHIFT) & DDRPHY_PGCR1_WLMODE_MASK) -#define DDRPHY_PGCR1_WLMODE_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_WLMODE_MASK) >> DDRPHY_PGCR1_WLMODE_SHIFT) - -/* - * PDDISDX (R/W) - * - * Power Down Disabled Byte: Indicates, if set, that the PLL and I/Os of a disabled byte should be powered down. - */ -#define DDRPHY_PGCR1_PDDISDX_MASK (0x1U) -#define DDRPHY_PGCR1_PDDISDX_SHIFT (0U) -#define DDRPHY_PGCR1_PDDISDX_SET(x) (((uint32_t)(x) << DDRPHY_PGCR1_PDDISDX_SHIFT) & DDRPHY_PGCR1_PDDISDX_MASK) -#define DDRPHY_PGCR1_PDDISDX_GET(x) (((uint32_t)(x) & DDRPHY_PGCR1_PDDISDX_MASK) >> DDRPHY_PGCR1_PDDISDX_SHIFT) - -/* Bitfield definition for register: PGSR0 */ -/* - * APLOCK (R) - * - * AC PLL Lock: Indicates, if set, that AC PLL has locked. This is a direct status of the AC PLL lock pin. - */ -#define DDRPHY_PGSR0_APLOCK_MASK (0x80000000UL) -#define DDRPHY_PGSR0_APLOCK_SHIFT (31U) -#define DDRPHY_PGSR0_APLOCK_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_APLOCK_MASK) >> DDRPHY_PGSR0_APLOCK_SHIFT) - -/* - * PLDONE_CHN (R) - * - * PLL Lock Done per Channel: Indicates PLL locking has completed for each underlying channel. Bit 28 represents channel 0 while bit 29 represents channel 1. - */ -#define DDRPHY_PGSR0_PLDONE_CHN_MASK (0x30000000UL) -#define DDRPHY_PGSR0_PLDONE_CHN_SHIFT (28U) -#define DDRPHY_PGSR0_PLDONE_CHN_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_PLDONE_CHN_MASK) >> DDRPHY_PGSR0_PLDONE_CHN_SHIFT) - -/* - * WEERR (R) - * - * Write Eye Training Error: Indicates, if set, that there is an error in write eye training. - */ -#define DDRPHY_PGSR0_WEERR_MASK (0x8000000UL) -#define DDRPHY_PGSR0_WEERR_SHIFT (27U) -#define DDRPHY_PGSR0_WEERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WEERR_MASK) >> DDRPHY_PGSR0_WEERR_SHIFT) - -/* - * REERR (R) - * - * Read Data Eye Training Error: Indicates, if set, that there is an error in read eye training. - */ -#define DDRPHY_PGSR0_REERR_MASK (0x4000000UL) -#define DDRPHY_PGSR0_REERR_SHIFT (26U) -#define DDRPHY_PGSR0_REERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_REERR_MASK) >> DDRPHY_PGSR0_REERR_SHIFT) - -/* - * WDERR (R) - * - * Write Data Bit Deskew Error: Indicates, if set, that there is an error in write bit deskew. - */ -#define DDRPHY_PGSR0_WDERR_MASK (0x2000000UL) -#define DDRPHY_PGSR0_WDERR_SHIFT (25U) -#define DDRPHY_PGSR0_WDERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WDERR_MASK) >> DDRPHY_PGSR0_WDERR_SHIFT) - -/* - * RDERR (R) - * - * Read Data Bit Deskew Error: Indicates, if set, that there is an error in read bit deskew. - */ -#define DDRPHY_PGSR0_RDERR_MASK (0x1000000UL) -#define DDRPHY_PGSR0_RDERR_SHIFT (24U) -#define DDRPHY_PGSR0_RDERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_RDERR_MASK) >> DDRPHY_PGSR0_RDERR_SHIFT) - -/* - * WLAERR (R) - * - * Write Data Leveling Adjustment Error: Indicates, if set, that there is an error in write leveling adjustment. - */ -#define DDRPHY_PGSR0_WLAERR_MASK (0x800000UL) -#define DDRPHY_PGSR0_WLAERR_SHIFT (23U) -#define DDRPHY_PGSR0_WLAERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLAERR_MASK) >> DDRPHY_PGSR0_WLAERR_SHIFT) - -/* - * QSGERR (R) - * - * Read DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. - */ -#define DDRPHY_PGSR0_QSGERR_MASK (0x400000UL) -#define DDRPHY_PGSR0_QSGERR_SHIFT (22U) -#define DDRPHY_PGSR0_QSGERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_QSGERR_MASK) >> DDRPHY_PGSR0_QSGERR_SHIFT) - -/* - * WLERR (R) - * - * Write Leveling Error: Indicates, if set, that there is an error in write leveling. - */ -#define DDRPHY_PGSR0_WLERR_MASK (0x200000UL) -#define DDRPHY_PGSR0_WLERR_SHIFT (21U) -#define DDRPHY_PGSR0_WLERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLERR_MASK) >> DDRPHY_PGSR0_WLERR_SHIFT) - -/* - * ZCERR (R) - * - * Impedance Calibration Error: Indicates, if set, that there is an error in impedance calibration. - */ -#define DDRPHY_PGSR0_ZCERR_MASK (0x100000UL) -#define DDRPHY_PGSR0_ZCERR_SHIFT (20U) -#define DDRPHY_PGSR0_ZCERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_ZCERR_MASK) >> DDRPHY_PGSR0_ZCERR_SHIFT) - -/* - * WEDONE (R) - * - * Write Data Eye Training Done: Indicates, if set, that write eye training has completed. - */ -#define DDRPHY_PGSR0_WEDONE_MASK (0x800U) -#define DDRPHY_PGSR0_WEDONE_SHIFT (11U) -#define DDRPHY_PGSR0_WEDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WEDONE_MASK) >> DDRPHY_PGSR0_WEDONE_SHIFT) - -/* - * REDONE (R) - * - * Read Data Eye Training Done: Indicates, if set, that read eye training has completed. - */ -#define DDRPHY_PGSR0_REDONE_MASK (0x400U) -#define DDRPHY_PGSR0_REDONE_SHIFT (10U) -#define DDRPHY_PGSR0_REDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_REDONE_MASK) >> DDRPHY_PGSR0_REDONE_SHIFT) - -/* - * WDDONE (R) - * - * Write Data Bit Deskew Done: Indicates, if set, that write bit deskew has completed. - */ -#define DDRPHY_PGSR0_WDDONE_MASK (0x200U) -#define DDRPHY_PGSR0_WDDONE_SHIFT (9U) -#define DDRPHY_PGSR0_WDDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WDDONE_MASK) >> DDRPHY_PGSR0_WDDONE_SHIFT) - -/* - * RDDONE (R) - * - * Read Data Bit Deskew Done: Indicates, if set, that read bit deskew has completed. - */ -#define DDRPHY_PGSR0_RDDONE_MASK (0x100U) -#define DDRPHY_PGSR0_RDDONE_SHIFT (8U) -#define DDRPHY_PGSR0_RDDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_RDDONE_MASK) >> DDRPHY_PGSR0_RDDONE_SHIFT) - -/* - * WLADONE (R) - * - * Write Leveling Adjustment Done: Indicates, if set, that write leveling adjustment has completed. - */ -#define DDRPHY_PGSR0_WLADONE_MASK (0x80U) -#define DDRPHY_PGSR0_WLADONE_SHIFT (7U) -#define DDRPHY_PGSR0_WLADONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLADONE_MASK) >> DDRPHY_PGSR0_WLADONE_SHIFT) - -/* - * QSGDONE (R) - * - * Read DQS Gate Training Done: Indicates, if set, that DQS gate training has completed. - */ -#define DDRPHY_PGSR0_QSGDONE_MASK (0x40U) -#define DDRPHY_PGSR0_QSGDONE_SHIFT (6U) -#define DDRPHY_PGSR0_QSGDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_QSGDONE_MASK) >> DDRPHY_PGSR0_QSGDONE_SHIFT) - -/* - * WLDONE (R) - * - * Write Leveling Done: Indicates, if set, that write leveling has completed. - */ -#define DDRPHY_PGSR0_WLDONE_MASK (0x20U) -#define DDRPHY_PGSR0_WLDONE_SHIFT (5U) -#define DDRPHY_PGSR0_WLDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_WLDONE_MASK) >> DDRPHY_PGSR0_WLDONE_SHIFT) - -/* - * DIDONE (R) - * - * DRAM Initialization Done: Indicates, if set, that DRAM initialization has completed. - */ -#define DDRPHY_PGSR0_DIDONE_MASK (0x10U) -#define DDRPHY_PGSR0_DIDONE_SHIFT (4U) -#define DDRPHY_PGSR0_DIDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_DIDONE_MASK) >> DDRPHY_PGSR0_DIDONE_SHIFT) - -/* - * ZCDONE (R) - * - * Impedance Calibration Done: Indicates, if set, that impedance calibration has completed. - */ -#define DDRPHY_PGSR0_ZCDONE_MASK (0x8U) -#define DDRPHY_PGSR0_ZCDONE_SHIFT (3U) -#define DDRPHY_PGSR0_ZCDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_ZCDONE_MASK) >> DDRPHY_PGSR0_ZCDONE_SHIFT) - -/* - * DCDONE (R) - * - * Digital Delay Line (DDL) Calibration Done: Indicates, if set, that DDL calibration has completed. - */ -#define DDRPHY_PGSR0_DCDONE_MASK (0x4U) -#define DDRPHY_PGSR0_DCDONE_SHIFT (2U) -#define DDRPHY_PGSR0_DCDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_DCDONE_MASK) >> DDRPHY_PGSR0_DCDONE_SHIFT) - -/* - * PLDONE (R) - * - * PLL Lock Done: Indicates, if set, that PLL locking has completed. - */ -#define DDRPHY_PGSR0_PLDONE_MASK (0x2U) -#define DDRPHY_PGSR0_PLDONE_SHIFT (1U) -#define DDRPHY_PGSR0_PLDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_PLDONE_MASK) >> DDRPHY_PGSR0_PLDONE_SHIFT) - -/* - * IDONE (R) - * - * Initialization Done: Indicates, if set, that the DDR system initialization has completed. This bit is set after all the selected initialization routines in PIR register have completed. - */ -#define DDRPHY_PGSR0_IDONE_MASK (0x1U) -#define DDRPHY_PGSR0_IDONE_SHIFT (0U) -#define DDRPHY_PGSR0_IDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR0_IDONE_MASK) >> DDRPHY_PGSR0_IDONE_SHIFT) - -/* Bitfield definition for register: PGSR1 */ -/* - * PARERR (R) - * - * RDIMM Parity Error: Indicates, if set, that there was a parity error (i.e. err_out_n was sampled low) during one of the transactions to the RDIMM buffer chip. This bit remains asserted until cleared by the PIR.CLRSR. - */ -#define DDRPHY_PGSR1_PARERR_MASK (0x80000000UL) -#define DDRPHY_PGSR1_PARERR_SHIFT (31U) -#define DDRPHY_PGSR1_PARERR_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_PARERR_MASK) >> DDRPHY_PGSR1_PARERR_SHIFT) - -/* - * VTSTOP (R) - * - * VT Stop: Indicates, if set, that the VT calculation logic has stopped computing the next values for the VT compensated delay line values. After assertion of the PGCR.INHVT, the VTSTOP bit should be read to ensure all VT compensation logic has stopped computations before writing to the delay line registers. - */ -#define DDRPHY_PGSR1_VTSTOP_MASK (0x40000000UL) -#define DDRPHY_PGSR1_VTSTOP_SHIFT (30U) -#define DDRPHY_PGSR1_VTSTOP_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_VTSTOP_MASK) >> DDRPHY_PGSR1_VTSTOP_SHIFT) - -/* - * DLTCODE (R) - * - * Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the AC delay line digital test output. - */ -#define DDRPHY_PGSR1_DLTCODE_MASK (0x1FFFFFEUL) -#define DDRPHY_PGSR1_DLTCODE_SHIFT (1U) -#define DDRPHY_PGSR1_DLTCODE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_DLTCODE_MASK) >> DDRPHY_PGSR1_DLTCODE_SHIFT) - -/* - * DLTDONE (R) - * - * Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the AC delay line digital test output. - */ -#define DDRPHY_PGSR1_DLTDONE_MASK (0x1U) -#define DDRPHY_PGSR1_DLTDONE_SHIFT (0U) -#define DDRPHY_PGSR1_DLTDONE_GET(x) (((uint32_t)(x) & DDRPHY_PGSR1_DLTDONE_MASK) >> DDRPHY_PGSR1_DLTDONE_SHIFT) - -/* Bitfield definition for register: PLLCR */ -/* - * BYP (R/W) - * - * PLL Bypass: Bypasses the PLL, if set, to 1. - */ -#define DDRPHY_PLLCR_BYP_MASK (0x80000000UL) -#define DDRPHY_PLLCR_BYP_SHIFT (31U) -#define DDRPHY_PLLCR_BYP_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_BYP_SHIFT) & DDRPHY_PLLCR_BYP_MASK) -#define DDRPHY_PLLCR_BYP_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_BYP_MASK) >> DDRPHY_PLLCR_BYP_SHIFT) - -/* - * PLLRST (R/W) - * - * PLL Rest: Resets the PLLs by driving the PLL reset pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the reset. - */ -#define DDRPHY_PLLCR_PLLRST_MASK (0x40000000UL) -#define DDRPHY_PLLCR_PLLRST_SHIFT (30U) -#define DDRPHY_PLLCR_PLLRST_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_PLLRST_SHIFT) & DDRPHY_PLLCR_PLLRST_MASK) -#define DDRPHY_PLLCR_PLLRST_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_PLLRST_MASK) >> DDRPHY_PLLCR_PLLRST_SHIFT) - -/* - * PLLPD (R/W) - * - * PLL Power Down: Puts the PLLs in power down mode by driving the PLL power down pin. This bit is not self-clearing and a ‘0’ must be written to de-assert the power-down. - */ -#define DDRPHY_PLLCR_PLLPD_MASK (0x20000000UL) -#define DDRPHY_PLLCR_PLLPD_SHIFT (29U) -#define DDRPHY_PLLCR_PLLPD_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_PLLPD_SHIFT) & DDRPHY_PLLCR_PLLPD_MASK) -#define DDRPHY_PLLCR_PLLPD_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_PLLPD_MASK) >> DDRPHY_PLLCR_PLLPD_SHIFT) - -/* - * FRQSEL (R/W) - * - * PLL Frequency Select: Selects the operating range of the PLL. Valid values for PHYs that go up to 2133 Mbps are: - * 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 335MHz to 533MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 225MHz to 385MHz 10 = Reserved - * 11 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 275MHz - * Valid values for PHYs that don’t go up to 2133 Mbps are: - * 00 = PLL reference clock (ctl_clk/REF_CLK) ranges from 250MHz to 400MHz 01 = PLL reference clock (ctl_clk/REF_CLK) ranges from 166MHz to 300MHz 10 = Reserved - * 11 = Reserved - */ -#define DDRPHY_PLLCR_FRQSEL_MASK (0xC0000UL) -#define DDRPHY_PLLCR_FRQSEL_SHIFT (18U) -#define DDRPHY_PLLCR_FRQSEL_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_FRQSEL_SHIFT) & DDRPHY_PLLCR_FRQSEL_MASK) -#define DDRPHY_PLLCR_FRQSEL_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_FRQSEL_MASK) >> DDRPHY_PLLCR_FRQSEL_SHIFT) - -/* - * QPMODE (R/W) - * - * PLL Quadrature Phase Mode: Enables, if set, the quadrature phase clock outputs. This mode is not used in this version of the PHY. - */ -#define DDRPHY_PLLCR_QPMODE_MASK (0x20000UL) -#define DDRPHY_PLLCR_QPMODE_SHIFT (17U) -#define DDRPHY_PLLCR_QPMODE_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_QPMODE_SHIFT) & DDRPHY_PLLCR_QPMODE_MASK) -#define DDRPHY_PLLCR_QPMODE_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_QPMODE_MASK) >> DDRPHY_PLLCR_QPMODE_SHIFT) - -/* - * CPPC (R/W) - * - * Charge Pump Proportional Current Control - */ -#define DDRPHY_PLLCR_CPPC_MASK (0x1E000UL) -#define DDRPHY_PLLCR_CPPC_SHIFT (13U) -#define DDRPHY_PLLCR_CPPC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_CPPC_SHIFT) & DDRPHY_PLLCR_CPPC_MASK) -#define DDRPHY_PLLCR_CPPC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_CPPC_MASK) >> DDRPHY_PLLCR_CPPC_SHIFT) - -/* - * CPIC (R/W) - * - * Charge Pump Integrating Current Control - */ -#define DDRPHY_PLLCR_CPIC_MASK (0x1800U) -#define DDRPHY_PLLCR_CPIC_SHIFT (11U) -#define DDRPHY_PLLCR_CPIC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_CPIC_SHIFT) & DDRPHY_PLLCR_CPIC_MASK) -#define DDRPHY_PLLCR_CPIC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_CPIC_MASK) >> DDRPHY_PLLCR_CPIC_SHIFT) - -/* - * GSHIFT (R/W) - * - * Gear Shift: Enables, if set, rapid locking mode. - */ -#define DDRPHY_PLLCR_GSHIFT_MASK (0x400U) -#define DDRPHY_PLLCR_GSHIFT_SHIFT (10U) -#define DDRPHY_PLLCR_GSHIFT_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_GSHIFT_SHIFT) & DDRPHY_PLLCR_GSHIFT_MASK) -#define DDRPHY_PLLCR_GSHIFT_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_GSHIFT_MASK) >> DDRPHY_PLLCR_GSHIFT_SHIFT) - -/* - * ATOEN (R/W) - * - * Analog Test Enable (ATOEN): Selects the analog test signal that is driven on the analog test output pin. Otherwise the analog test output is tri-stated. This allows analog test output pins from multiple PLLs to be connected together. Valid values are: - * 0000 = All PLL analog test signals are tri-stated 0001 = AC PLL analog test signal is driven out - * 0010 = DATX8 0 PLL analog test signal is driven out 0011 = DATX8 1 PLL analog test signal is driven out 0100 = DATX8 2 PLL analog test signal is driven out 0101 = DATX8 3 PLL analog test signal is driven out 0110 = DATX8 4 PLL analog test signal is driven out 0111 = DATX8 5 PLL analog test signal is driven out 1000 = DATX8 6 PLL analog test signal is driven out 1001 = DATX8 7 PLL analog test signal is driven out 1010 = DATX8 8 PLL analog test signal is driven out 1011 – 1111 = Reserved - */ -#define DDRPHY_PLLCR_ATOEN_MASK (0x3C0U) -#define DDRPHY_PLLCR_ATOEN_SHIFT (6U) -#define DDRPHY_PLLCR_ATOEN_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_ATOEN_SHIFT) & DDRPHY_PLLCR_ATOEN_MASK) -#define DDRPHY_PLLCR_ATOEN_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_ATOEN_MASK) >> DDRPHY_PLLCR_ATOEN_SHIFT) - -/* - * ATC (R/W) - * - * Analog Test Control: Selects various PLL analog test signals to be brought out via PLL analog test output pin (pll_ato). Valid values are: - * 0000 = Reserved - * 0001 = vdd_ckin - * 0010 = vrfbf - * 0011 = vdd_cko - * 0100 = vp_cp - * 0101 = vpfil(vp) - * 0110 = Reserved - * 0111 = gd - * 1000 = vcntrl_atb - * 1001 = vref_atb - * 1010 = vpsf_atb - * 1011 – 1111 = Reserved - */ -#define DDRPHY_PLLCR_ATC_MASK (0x3CU) -#define DDRPHY_PLLCR_ATC_SHIFT (2U) -#define DDRPHY_PLLCR_ATC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_ATC_SHIFT) & DDRPHY_PLLCR_ATC_MASK) -#define DDRPHY_PLLCR_ATC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_ATC_MASK) >> DDRPHY_PLLCR_ATC_SHIFT) - -/* - * DTC (R/W) - * - * Digital Test Control: Selects various PLL digital test signals and other test mode signals to be brought out via bit [1] of the PLL digital test output (pll_dto[1]). Valid values are: - * 00 = ‘0’ (Test output is disabled) 01 = PLL x1 clock (X1) - * 10 = PLL reference (input) clock (REF_CLK) 11 = PLL feedback clock (FB_X1) - */ -#define DDRPHY_PLLCR_DTC_MASK (0x3U) -#define DDRPHY_PLLCR_DTC_SHIFT (0U) -#define DDRPHY_PLLCR_DTC_SET(x) (((uint32_t)(x) << DDRPHY_PLLCR_DTC_SHIFT) & DDRPHY_PLLCR_DTC_MASK) -#define DDRPHY_PLLCR_DTC_GET(x) (((uint32_t)(x) & DDRPHY_PLLCR_DTC_MASK) >> DDRPHY_PLLCR_DTC_SHIFT) - -/* Bitfield definition for register: PTR0 */ -/* - * TPLLPD (R/W) - * - * PLL Power-Down Time: Number of configuration or APB clock cycles that the PLL must remain in power-down mode, i.e. number of clock cycles from when PLL power-down pin is asserted to when PLL power-down pin is de-asserted. This must correspond to a value that is equal to or more than 1us. Default value corresponds to 1us. - */ -#define DDRPHY_PTR0_TPLLPD_MASK (0xFFE00000UL) -#define DDRPHY_PTR0_TPLLPD_SHIFT (21U) -#define DDRPHY_PTR0_TPLLPD_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPLLPD_SHIFT) & DDRPHY_PTR0_TPLLPD_MASK) -#define DDRPHY_PTR0_TPLLPD_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPLLPD_MASK) >> DDRPHY_PTR0_TPLLPD_SHIFT) - -/* - * TPLLGS (R/W) - * - * PLL Gear Shift Time: Number of configuration or APB clock cycles from when the PLL reset pin is de-asserted to when the PLL gear shift pin is de-asserted. This must correspond to a value that is equal to or more than 4us. Default value corresponds to 4us. - */ -#define DDRPHY_PTR0_TPLLGS_MASK (0x1FFFC0UL) -#define DDRPHY_PTR0_TPLLGS_SHIFT (6U) -#define DDRPHY_PTR0_TPLLGS_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPLLGS_SHIFT) & DDRPHY_PTR0_TPLLGS_MASK) -#define DDRPHY_PTR0_TPLLGS_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPLLGS_MASK) >> DDRPHY_PTR0_TPLLGS_SHIFT) - -/* - * TPHYRST (R/W) - * - * PHY Reset Time: Number of configuration or APB clock cycles that the PHY reset must remain asserted after PHY calibration is done before the reset to the PHY is de-asserted. This is used to extend the reset to the PHY so that the reset is asserted for some clock cycles after the clocks are stable. Valid values are from 1 to 63 (the value must be non-zero). - */ -#define DDRPHY_PTR0_TPHYRST_MASK (0x3FU) -#define DDRPHY_PTR0_TPHYRST_SHIFT (0U) -#define DDRPHY_PTR0_TPHYRST_SET(x) (((uint32_t)(x) << DDRPHY_PTR0_TPHYRST_SHIFT) & DDRPHY_PTR0_TPHYRST_MASK) -#define DDRPHY_PTR0_TPHYRST_GET(x) (((uint32_t)(x) & DDRPHY_PTR0_TPHYRST_MASK) >> DDRPHY_PTR0_TPHYRST_SHIFT) - -/* Bitfield definition for register: PTR1 */ -/* - * TPLLLOCK (R/W) - * - * PLL Lock Time: Number of configuration or APB clock cycles for the PLL to stabilize and lock, i.e. number of clock cycles from when the PLL reset pin is de-asserted to when the PLL has lock and is ready for use. This must correspond to a value that is equal to or more than 100us. Default value corresponds to 100us. - */ -#define DDRPHY_PTR1_TPLLLOCK_MASK (0xFFFF0000UL) -#define DDRPHY_PTR1_TPLLLOCK_SHIFT (16U) -#define DDRPHY_PTR1_TPLLLOCK_SET(x) (((uint32_t)(x) << DDRPHY_PTR1_TPLLLOCK_SHIFT) & DDRPHY_PTR1_TPLLLOCK_MASK) -#define DDRPHY_PTR1_TPLLLOCK_GET(x) (((uint32_t)(x) & DDRPHY_PTR1_TPLLLOCK_MASK) >> DDRPHY_PTR1_TPLLLOCK_SHIFT) - -/* - * TPLLRST (R/W) - * - * PLL Reset Time: Number of configuration or APB clock cycles that the PLL must remain in reset mode, i.e. number of clock cycles from when PLL power-down pin is de-asserted and PLL reset pin is asserted to when PLL reset pin is de-asserted. - * The setting must correspond to a value that is equal to, or greater than, 3us. - */ -#define DDRPHY_PTR1_TPLLRST_MASK (0x1FFFU) -#define DDRPHY_PTR1_TPLLRST_SHIFT (0U) -#define DDRPHY_PTR1_TPLLRST_SET(x) (((uint32_t)(x) << DDRPHY_PTR1_TPLLRST_SHIFT) & DDRPHY_PTR1_TPLLRST_MASK) -#define DDRPHY_PTR1_TPLLRST_GET(x) (((uint32_t)(x) & DDRPHY_PTR1_TPLLRST_MASK) >> DDRPHY_PTR1_TPLLRST_SHIFT) - -/* Bitfield definition for register: PTR2 */ -/* - * TWLDLYS (R/W) - * - * Write Leveling Delay Settling Time: Number of controller clock cycles from when a new value of the write leveling delay is applies to the LCDL to when to DQS high is driven high. This allows the delay to settle. - */ -#define DDRPHY_PTR2_TWLDLYS_MASK (0xF8000UL) -#define DDRPHY_PTR2_TWLDLYS_SHIFT (15U) -#define DDRPHY_PTR2_TWLDLYS_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TWLDLYS_SHIFT) & DDRPHY_PTR2_TWLDLYS_MASK) -#define DDRPHY_PTR2_TWLDLYS_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TWLDLYS_MASK) >> DDRPHY_PTR2_TWLDLYS_SHIFT) - -/* - * TCALH (R/W) - * - * Calibration Hold Time: Number of controller clock cycles from when the clock was disabled (cal_clk_en deasserted) to when calibration is enable (cal_en asserted). - */ -#define DDRPHY_PTR2_TCALH_MASK (0x7C00U) -#define DDRPHY_PTR2_TCALH_SHIFT (10U) -#define DDRPHY_PTR2_TCALH_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALH_SHIFT) & DDRPHY_PTR2_TCALH_MASK) -#define DDRPHY_PTR2_TCALH_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALH_MASK) >> DDRPHY_PTR2_TCALH_SHIFT) - -/* - * TCALS (R/W) - * - * Calibration Setup Time: Number of controller clock cycles from when calibration is enabled (cal_en asserted) to when the calibration clock is asserted again (cal_clk_en asserted). - */ -#define DDRPHY_PTR2_TCALS_MASK (0x3E0U) -#define DDRPHY_PTR2_TCALS_SHIFT (5U) -#define DDRPHY_PTR2_TCALS_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALS_SHIFT) & DDRPHY_PTR2_TCALS_MASK) -#define DDRPHY_PTR2_TCALS_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALS_MASK) >> DDRPHY_PTR2_TCALS_SHIFT) - -/* - * TCALON (R/W) - * - * Calibration On Time: Number of clock cycles that the calibration clock is enabled (cal_clk_en asserted). - */ -#define DDRPHY_PTR2_TCALON_MASK (0x1FU) -#define DDRPHY_PTR2_TCALON_SHIFT (0U) -#define DDRPHY_PTR2_TCALON_SET(x) (((uint32_t)(x) << DDRPHY_PTR2_TCALON_SHIFT) & DDRPHY_PTR2_TCALON_MASK) -#define DDRPHY_PTR2_TCALON_GET(x) (((uint32_t)(x) & DDRPHY_PTR2_TCALON_MASK) >> DDRPHY_PTR2_TCALON_SHIFT) - -/* Bitfield definition for register: PTR3 */ -/* - * TDINIT1 (R/W) - * - * DRAM Initialization Time 1: DRAM initialization time in DRAM clock cycles corresponding to the following: - * DDR3 = CKE high time to first command (tRFC + 10 ns or 5 tCK, whichever is bigger) DDR2 = CKE high time to first command (400 ns) - * Default value corresponds to DDR3 tRFC of 360ns at 1066 MHz. - */ -#define DDRPHY_PTR3_TDINIT1_MASK (0x1FF00000UL) -#define DDRPHY_PTR3_TDINIT1_SHIFT (20U) -#define DDRPHY_PTR3_TDINIT1_SET(x) (((uint32_t)(x) << DDRPHY_PTR3_TDINIT1_SHIFT) & DDRPHY_PTR3_TDINIT1_MASK) -#define DDRPHY_PTR3_TDINIT1_GET(x) (((uint32_t)(x) & DDRPHY_PTR3_TDINIT1_MASK) >> DDRPHY_PTR3_TDINIT1_SHIFT) - -/* - * TDINIT0 (R/W) - * - * DRAM Initialization Time 0: DRAM initialization time in DRAM clock cycles corresponding to the following: - * DDR3 = CKE low time with power and clock stable (500 us) DDR2 = CKE low time with power and clock stable (200 us) Default value corresponds to DDR3 500 us at 1066 MHz. - * During Verilog simulations, it is recommended that this value is changed to a much smaller value in order to avoid long simulation times. However, this may cause a memory model error, due to a violation of the CKE setup sequence. This violation is expected if this value is not programmed to the required SDRAM CKE low time, but memory models should be able to tolerate this violation without malfunction of the model. - */ -#define DDRPHY_PTR3_TDINIT0_MASK (0xFFFFFUL) -#define DDRPHY_PTR3_TDINIT0_SHIFT (0U) -#define DDRPHY_PTR3_TDINIT0_SET(x) (((uint32_t)(x) << DDRPHY_PTR3_TDINIT0_SHIFT) & DDRPHY_PTR3_TDINIT0_MASK) -#define DDRPHY_PTR3_TDINIT0_GET(x) (((uint32_t)(x) & DDRPHY_PTR3_TDINIT0_MASK) >> DDRPHY_PTR3_TDINIT0_SHIFT) - -/* Bitfield definition for register: PTR4 */ -/* - * TDINIT3 (R/W) - * - * DRAM Initialization Time 3: DRAM initialization time in DRAM clock cycles corresponding to the following: - * DDR3 = Time from ZQ initialization command to first command (1 us) Default value corresponds to the DDR3 640ns at 1066 MHz. - */ -#define DDRPHY_PTR4_TDINIT3_MASK (0xFFC0000UL) -#define DDRPHY_PTR4_TDINIT3_SHIFT (18U) -#define DDRPHY_PTR4_TDINIT3_SET(x) (((uint32_t)(x) << DDRPHY_PTR4_TDINIT3_SHIFT) & DDRPHY_PTR4_TDINIT3_MASK) -#define DDRPHY_PTR4_TDINIT3_GET(x) (((uint32_t)(x) & DDRPHY_PTR4_TDINIT3_MASK) >> DDRPHY_PTR4_TDINIT3_SHIFT) - -/* - * TDINIT2 (R/W) - * - * DRAM Initialization Time 2: DRAM initialization time in DRAM clock cycles corresponding to the following: - * DDR3 = Reset low time (200 us on power-up or 100 ns after power-up) Default value corresponds to DDR3 200 us at 1066 MHz. - */ -#define DDRPHY_PTR4_TDINIT2_MASK (0x3FFFFUL) -#define DDRPHY_PTR4_TDINIT2_SHIFT (0U) -#define DDRPHY_PTR4_TDINIT2_SET(x) (((uint32_t)(x) << DDRPHY_PTR4_TDINIT2_SHIFT) & DDRPHY_PTR4_TDINIT2_MASK) -#define DDRPHY_PTR4_TDINIT2_GET(x) (((uint32_t)(x) & DDRPHY_PTR4_TDINIT2_MASK) >> DDRPHY_PTR4_TDINIT2_SHIFT) - -/* Bitfield definition for register: ACMDLR */ -/* - * MDLD (R/W) - * - * MDL Delay: Delay select for the LCDL for the Master Delay Line. - */ -#define DDRPHY_ACMDLR_MDLD_MASK (0xFF0000UL) -#define DDRPHY_ACMDLR_MDLD_SHIFT (16U) -#define DDRPHY_ACMDLR_MDLD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_MDLD_SHIFT) & DDRPHY_ACMDLR_MDLD_MASK) -#define DDRPHY_ACMDLR_MDLD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_MDLD_MASK) >> DDRPHY_ACMDLR_MDLD_SHIFT) - -/* - * TPRD (R/W) - * - * Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. - */ -#define DDRPHY_ACMDLR_TPRD_MASK (0xFF00U) -#define DDRPHY_ACMDLR_TPRD_SHIFT (8U) -#define DDRPHY_ACMDLR_TPRD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_TPRD_SHIFT) & DDRPHY_ACMDLR_TPRD_MASK) -#define DDRPHY_ACMDLR_TPRD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_TPRD_MASK) >> DDRPHY_ACMDLR_TPRD_SHIFT) - -/* - * IPRD (R/W) - * - * Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. - */ -#define DDRPHY_ACMDLR_IPRD_MASK (0xFFU) -#define DDRPHY_ACMDLR_IPRD_SHIFT (0U) -#define DDRPHY_ACMDLR_IPRD_SET(x) (((uint32_t)(x) << DDRPHY_ACMDLR_IPRD_SHIFT) & DDRPHY_ACMDLR_IPRD_MASK) -#define DDRPHY_ACMDLR_IPRD_GET(x) (((uint32_t)(x) & DDRPHY_ACMDLR_IPRD_MASK) >> DDRPHY_ACMDLR_IPRD_SHIFT) - -/* Bitfield definition for register: ACBDLR */ -/* - * ACBD (R/W) - * - * Address/Command Bit Delay: Delay select for the BDLs on address and command signals. - */ -#define DDRPHY_ACBDLR_ACBD_MASK (0xFC0000UL) -#define DDRPHY_ACBDLR_ACBD_SHIFT (18U) -#define DDRPHY_ACBDLR_ACBD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_ACBD_SHIFT) & DDRPHY_ACBDLR_ACBD_MASK) -#define DDRPHY_ACBDLR_ACBD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_ACBD_MASK) >> DDRPHY_ACBDLR_ACBD_SHIFT) - -/* - * CK2BD (R/W) - * - * CK2 Bit Delay: Delay select for the BDL on CK2. - */ -#define DDRPHY_ACBDLR_CK2BD_MASK (0x3F000UL) -#define DDRPHY_ACBDLR_CK2BD_SHIFT (12U) -#define DDRPHY_ACBDLR_CK2BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK2BD_SHIFT) & DDRPHY_ACBDLR_CK2BD_MASK) -#define DDRPHY_ACBDLR_CK2BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK2BD_MASK) >> DDRPHY_ACBDLR_CK2BD_SHIFT) - -/* - * CK1BD (R/W) - * - * CK1 Bit Delay: Delay select for the BDL on CK1. - */ -#define DDRPHY_ACBDLR_CK1BD_MASK (0xFC0U) -#define DDRPHY_ACBDLR_CK1BD_SHIFT (6U) -#define DDRPHY_ACBDLR_CK1BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK1BD_SHIFT) & DDRPHY_ACBDLR_CK1BD_MASK) -#define DDRPHY_ACBDLR_CK1BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK1BD_MASK) >> DDRPHY_ACBDLR_CK1BD_SHIFT) - -/* - * CK0BD (R/W) - * - * CK0 Bit Delay: Delay select for the BDL on CK0. - */ -#define DDRPHY_ACBDLR_CK0BD_MASK (0x3FU) -#define DDRPHY_ACBDLR_CK0BD_SHIFT (0U) -#define DDRPHY_ACBDLR_CK0BD_SET(x) (((uint32_t)(x) << DDRPHY_ACBDLR_CK0BD_SHIFT) & DDRPHY_ACBDLR_CK0BD_MASK) -#define DDRPHY_ACBDLR_CK0BD_GET(x) (((uint32_t)(x) & DDRPHY_ACBDLR_CK0BD_MASK) >> DDRPHY_ACBDLR_CK0BD_SHIFT) - -/* Bitfield definition for register: ACIOCR */ -/* - * ACSR (R/W) - * - * Address/Command Slew Rate (D3F I/O Only): Selects slew rate of the I/O for all address and command pins. - */ -#define DDRPHY_ACIOCR_ACSR_MASK (0xC0000000UL) -#define DDRPHY_ACIOCR_ACSR_SHIFT (30U) -#define DDRPHY_ACIOCR_ACSR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACSR_SHIFT) & DDRPHY_ACIOCR_ACSR_MASK) -#define DDRPHY_ACIOCR_ACSR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACSR_MASK) >> DDRPHY_ACIOCR_ACSR_SHIFT) - -/* - * RSTIOM (R/W) - * - * SDRAM Reset I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for SDRAM Reset. - */ -#define DDRPHY_ACIOCR_RSTIOM_MASK (0x20000000UL) -#define DDRPHY_ACIOCR_RSTIOM_SHIFT (29U) -#define DDRPHY_ACIOCR_RSTIOM_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTIOM_SHIFT) & DDRPHY_ACIOCR_RSTIOM_MASK) -#define DDRPHY_ACIOCR_RSTIOM_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTIOM_MASK) >> DDRPHY_ACIOCR_RSTIOM_SHIFT) - -/* - * RSTPDR (R/W) - * - * SDRAM Reset Power Down Receiver: Powers down, when set, the input receiver on the I/O for SDRAM RST# pin. - */ -#define DDRPHY_ACIOCR_RSTPDR_MASK (0x10000000UL) -#define DDRPHY_ACIOCR_RSTPDR_SHIFT (28U) -#define DDRPHY_ACIOCR_RSTPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTPDR_SHIFT) & DDRPHY_ACIOCR_RSTPDR_MASK) -#define DDRPHY_ACIOCR_RSTPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTPDR_MASK) >> DDRPHY_ACIOCR_RSTPDR_SHIFT) - -/* - * RSTPDD1 (R/W) - * - * SDRAM Reset Power Down Driver: Powers down, when set, the output driver on the I/O for SDRAM RST# pin. - */ -#define DDRPHY_ACIOCR_RSTPDD1_MASK (0x8000000UL) -#define DDRPHY_ACIOCR_RSTPDD1_SHIFT (27U) -#define DDRPHY_ACIOCR_RSTPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTPDD1_SHIFT) & DDRPHY_ACIOCR_RSTPDD1_MASK) -#define DDRPHY_ACIOCR_RSTPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTPDD1_MASK) >> DDRPHY_ACIOCR_RSTPDD1_SHIFT) - -/* - * RSTODT (R/W) - * - * SDRAM Reset On-Die Termination: Enables, when set, the on-die termination on the I/O for SDRAM RST# pin. - */ -#define DDRPHY_ACIOCR_RSTODT_MASK (0x4000000UL) -#define DDRPHY_ACIOCR_RSTODT_SHIFT (26U) -#define DDRPHY_ACIOCR_RSTODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RSTODT_SHIFT) & DDRPHY_ACIOCR_RSTODT_MASK) -#define DDRPHY_ACIOCR_RSTODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RSTODT_MASK) >> DDRPHY_ACIOCR_RSTODT_SHIFT) - -/* - * RANKPDR (R/W) - * - * Rank Power Down Receiver: Powers down, when set, the input receiver on the I/O CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKPDR[0] controls the power down for CKE[0], ODT[0], and CS#[0], RANKPDR[1] controls the power down for CKE[1], ODT[1], and CS#[1], and so on. - */ -#define DDRPHY_ACIOCR_RANKPDR_MASK (0x3C00000UL) -#define DDRPHY_ACIOCR_RANKPDR_SHIFT (22U) -#define DDRPHY_ACIOCR_RANKPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RANKPDR_SHIFT) & DDRPHY_ACIOCR_RANKPDR_MASK) -#define DDRPHY_ACIOCR_RANKPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RANKPDR_MASK) >> DDRPHY_ACIOCR_RANKPDR_SHIFT) - -/* - * CSPDD1 (R/W) - * - * CS# Power Down Driver: Powers down, when set, the output driver on the I/O for CS#[3:0] pins. CSPDD[0] controls the power down for CS#[0], CSPDD[1] controls the power down for CS#[1], and so on. CKE and ODT driver power down is controlled by DSGCR register. - */ -#define DDRPHY_ACIOCR_CSPDD1_MASK (0x3C0000UL) -#define DDRPHY_ACIOCR_CSPDD1_SHIFT (18U) -#define DDRPHY_ACIOCR_CSPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CSPDD1_SHIFT) & DDRPHY_ACIOCR_CSPDD1_MASK) -#define DDRPHY_ACIOCR_CSPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CSPDD1_MASK) >> DDRPHY_ACIOCR_CSPDD1_SHIFT) - -/* - * RANKODT (R/W) - * - * Rank On-Die Termination: Enables, when set, the on-die termination on the I/O for CKE[3:0], ODT[3:0], and CS#[3:0] pins. RANKODT[0] controls the on-die termination for CKE[0], ODT[0], and CS#[0], RANKODT[1] controls the on-die termination for CKE[1], ODT[1], and CS#[1], and so on. - */ -#define DDRPHY_ACIOCR_RANKODT_MASK (0x3C000UL) -#define DDRPHY_ACIOCR_RANKODT_SHIFT (14U) -#define DDRPHY_ACIOCR_RANKODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_RANKODT_SHIFT) & DDRPHY_ACIOCR_RANKODT_MASK) -#define DDRPHY_ACIOCR_RANKODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_RANKODT_MASK) >> DDRPHY_ACIOCR_RANKODT_SHIFT) - -/* - * CKPDR (R/W) - * - * CK Power Down Receiver: Powers down, when set, the input receiver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. - */ -#define DDRPHY_ACIOCR_CKPDR_MASK (0x3800U) -#define DDRPHY_ACIOCR_CKPDR_SHIFT (11U) -#define DDRPHY_ACIOCR_CKPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKPDR_SHIFT) & DDRPHY_ACIOCR_CKPDR_MASK) -#define DDRPHY_ACIOCR_CKPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKPDR_MASK) >> DDRPHY_ACIOCR_CKPDR_SHIFT) - -/* - * CKPDD1 (R/W) - * - * CK Power Down Driver: Powers down, when set, the output driver on the I/O for CK[0], CK[1], and CK[2] pins, respectively. - */ -#define DDRPHY_ACIOCR_CKPDD1_MASK (0x700U) -#define DDRPHY_ACIOCR_CKPDD1_SHIFT (8U) -#define DDRPHY_ACIOCR_CKPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKPDD1_SHIFT) & DDRPHY_ACIOCR_CKPDD1_MASK) -#define DDRPHY_ACIOCR_CKPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKPDD1_MASK) >> DDRPHY_ACIOCR_CKPDD1_SHIFT) - -/* - * CKODT (R/W) - * - * CK On-Die Termination: Enables, when set, the on-die termination on the I/O for CK[0], CK[1], and CK[2] pins, respectively. - */ -#define DDRPHY_ACIOCR_CKODT_MASK (0xE0U) -#define DDRPHY_ACIOCR_CKODT_SHIFT (5U) -#define DDRPHY_ACIOCR_CKODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_CKODT_SHIFT) & DDRPHY_ACIOCR_CKODT_MASK) -#define DDRPHY_ACIOCR_CKODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_CKODT_MASK) >> DDRPHY_ACIOCR_CKODT_SHIFT) - -/* - * ACPDR (R/W) - * - * AC Power Down Receiver: Powers down, when set, the input receiver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. - */ -#define DDRPHY_ACIOCR_ACPDR_MASK (0x10U) -#define DDRPHY_ACIOCR_ACPDR_SHIFT (4U) -#define DDRPHY_ACIOCR_ACPDR_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACPDR_SHIFT) & DDRPHY_ACIOCR_ACPDR_MASK) -#define DDRPHY_ACIOCR_ACPDR_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACPDR_MASK) >> DDRPHY_ACIOCR_ACPDR_SHIFT) - -/* - * ACPDD1 (R/W) - * - * AC Power Down Driver: Powers down, when set, the output driver on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. - */ -#define DDRPHY_ACIOCR_ACPDD1_MASK (0x8U) -#define DDRPHY_ACIOCR_ACPDD1_SHIFT (3U) -#define DDRPHY_ACIOCR_ACPDD1_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACPDD1_SHIFT) & DDRPHY_ACIOCR_ACPDD1_MASK) -#define DDRPHY_ACIOCR_ACPDD1_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACPDD1_MASK) >> DDRPHY_ACIOCR_ACPDD1_SHIFT) - -/* - * ACODT (R/W) - * - * Address/Command On-Die Termination: Enables, when set, the on-die termination on the I/O for RAS#, CAS#, WE#, BA[2:0], and A[15:0] pins. - */ -#define DDRPHY_ACIOCR_ACODT_MASK (0x4U) -#define DDRPHY_ACIOCR_ACODT_SHIFT (2U) -#define DDRPHY_ACIOCR_ACODT_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACODT_SHIFT) & DDRPHY_ACIOCR_ACODT_MASK) -#define DDRPHY_ACIOCR_ACODT_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACODT_MASK) >> DDRPHY_ACIOCR_ACODT_SHIFT) - -/* - * ACOE (R/W) - * - * Address/Command Output Enable: Enables, when set, the output driver on the I/O for all address and command pins. - */ -#define DDRPHY_ACIOCR_ACOE_MASK (0x2U) -#define DDRPHY_ACIOCR_ACOE_SHIFT (1U) -#define DDRPHY_ACIOCR_ACOE_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACOE_SHIFT) & DDRPHY_ACIOCR_ACOE_MASK) -#define DDRPHY_ACIOCR_ACOE_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACOE_MASK) >> DDRPHY_ACIOCR_ACOE_SHIFT) - -/* - * ACIOM (R/W) - * - * Address/Command I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for all address and command pins. This bit connects to bit - * [0] of the IOM pin on the D3F I/Os, and for other I/O libraries, it connects to the IOM pin of the I/O. - */ -#define DDRPHY_ACIOCR_ACIOM_MASK (0x1U) -#define DDRPHY_ACIOCR_ACIOM_SHIFT (0U) -#define DDRPHY_ACIOCR_ACIOM_SET(x) (((uint32_t)(x) << DDRPHY_ACIOCR_ACIOM_SHIFT) & DDRPHY_ACIOCR_ACIOM_MASK) -#define DDRPHY_ACIOCR_ACIOM_GET(x) (((uint32_t)(x) & DDRPHY_ACIOCR_ACIOM_MASK) >> DDRPHY_ACIOCR_ACIOM_SHIFT) - -/* Bitfield definition for register: DXCCR */ -/* - * DDPDRCDO (R/W) - * - * Dynamic Data Power Down Receiver Count Down Offset: Offset applied in calculating window of time where receiver is powered up - */ -#define DDRPHY_DXCCR_DDPDRCDO_MASK (0xF0000000UL) -#define DDRPHY_DXCCR_DDPDRCDO_SHIFT (28U) -#define DDRPHY_DXCCR_DDPDRCDO_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DDPDRCDO_SHIFT) & DDRPHY_DXCCR_DDPDRCDO_MASK) -#define DDRPHY_DXCCR_DDPDRCDO_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DDPDRCDO_MASK) >> DDRPHY_DXCCR_DDPDRCDO_SHIFT) - -/* - * DDPDDCDO (R/W) - * - * Dynamic Data Power Down Driver Count Down Offset: Offset applied in calculating window of time where driver is powered up - */ -#define DDRPHY_DXCCR_DDPDDCDO_MASK (0xF000000UL) -#define DDRPHY_DXCCR_DDPDDCDO_SHIFT (24U) -#define DDRPHY_DXCCR_DDPDDCDO_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DDPDDCDO_SHIFT) & DDRPHY_DXCCR_DDPDDCDO_MASK) -#define DDRPHY_DXCCR_DDPDDCDO_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DDPDDCDO_MASK) >> DDRPHY_DXCCR_DDPDDCDO_SHIFT) - -/* - * DYNDXPDR (R/W) - * - * Data Power Down Receiver: Dynamically powers down, when set, the input receiver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDR and DXnGCR.DXPDR are not set to 1. Receiver is powered-up on a DFI READ command and powered-down (trddata_en + fixed_read_latency + n) HDR cycles after the last DFI READ command. Note that n is defined by the register bit field DXCCR[31:28] (DDPDRCDO). - */ -#define DDRPHY_DXCCR_DYNDXPDR_MASK (0x800000UL) -#define DDRPHY_DXCCR_DYNDXPDR_SHIFT (23U) -#define DDRPHY_DXCCR_DYNDXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DYNDXPDR_SHIFT) & DDRPHY_DXCCR_DYNDXPDR_MASK) -#define DDRPHY_DXCCR_DYNDXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DYNDXPDR_MASK) >> DDRPHY_DXCCR_DYNDXPDR_SHIFT) - -/* - * DYNDXPDD1 (R/W) - * - * Dynamic Data Power Down Driver: Dynamically powers down, when set, the output driver on I/O for the DQ pins of the active DATX8 macros. Applies only when DXPDD and DXnGCR.DXPDD are not set to 1. Driver is powered-up on a DFI WRITE command and powered-down (twrlat + WL/2 + n) HDR cycles after the last DFI WRITE command. Note that n is defined by the register bit field DXCCR[27:24] (DDPDDCDO). - */ -#define DDRPHY_DXCCR_DYNDXPDD1_MASK (0x400000UL) -#define DDRPHY_DXCCR_DYNDXPDD1_SHIFT (22U) -#define DDRPHY_DXCCR_DYNDXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DYNDXPDD1_SHIFT) & DDRPHY_DXCCR_DYNDXPDD1_MASK) -#define DDRPHY_DXCCR_DYNDXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DYNDXPDD1_MASK) >> DDRPHY_DXCCR_DYNDXPDD1_SHIFT) - -/* - * UDQIOM (R/W) - * - * Unused DQ I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for unused DQ pins. - */ -#define DDRPHY_DXCCR_UDQIOM_MASK (0x200000UL) -#define DDRPHY_DXCCR_UDQIOM_SHIFT (21U) -#define DDRPHY_DXCCR_UDQIOM_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQIOM_SHIFT) & DDRPHY_DXCCR_UDQIOM_MASK) -#define DDRPHY_DXCCR_UDQIOM_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQIOM_MASK) >> DDRPHY_DXCCR_UDQIOM_SHIFT) - -/* - * UDQPDR (R/W) - * - * Unused DQ Power Down Receiver: Powers down, when set, the input receiver on the I/O for unused DQ pins. - */ -#define DDRPHY_DXCCR_UDQPDR_MASK (0x100000UL) -#define DDRPHY_DXCCR_UDQPDR_SHIFT (20U) -#define DDRPHY_DXCCR_UDQPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQPDR_SHIFT) & DDRPHY_DXCCR_UDQPDR_MASK) -#define DDRPHY_DXCCR_UDQPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQPDR_MASK) >> DDRPHY_DXCCR_UDQPDR_SHIFT) - -/* - * UDQPDD1 (R/W) - * - * Unused DQ Power Down Driver: Powers down, when set, the output driver on the I/O for unused DQ pins. - */ -#define DDRPHY_DXCCR_UDQPDD1_MASK (0x80000UL) -#define DDRPHY_DXCCR_UDQPDD1_SHIFT (19U) -#define DDRPHY_DXCCR_UDQPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQPDD1_SHIFT) & DDRPHY_DXCCR_UDQPDD1_MASK) -#define DDRPHY_DXCCR_UDQPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQPDD1_MASK) >> DDRPHY_DXCCR_UDQPDD1_SHIFT) - -/* - * UDQODT (R/W) - * - * Unused DQ On-Die Termination: Enables, when set, the on-die termination on the I/O for unused DQ pins. - */ -#define DDRPHY_DXCCR_UDQODT_MASK (0x40000UL) -#define DDRPHY_DXCCR_UDQODT_SHIFT (18U) -#define DDRPHY_DXCCR_UDQODT_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_UDQODT_SHIFT) & DDRPHY_DXCCR_UDQODT_MASK) -#define DDRPHY_DXCCR_UDQODT_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_UDQODT_MASK) >> DDRPHY_DXCCR_UDQODT_SHIFT) - -/* - * MSBUDQ (R/W) - * - * Most Significant Byte Unused DQs: Specifies the number of DQ bits that are not used in the most significant byte. The used (valid) bits for this byte are [8-MSBDQ- 1:0]. To disable the whole byte, use the DXnGCR.DXEN register. - */ -#define DDRPHY_DXCCR_MSBUDQ_MASK (0x38000UL) -#define DDRPHY_DXCCR_MSBUDQ_SHIFT (15U) -#define DDRPHY_DXCCR_MSBUDQ_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_MSBUDQ_SHIFT) & DDRPHY_DXCCR_MSBUDQ_MASK) -#define DDRPHY_DXCCR_MSBUDQ_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_MSBUDQ_MASK) >> DDRPHY_DXCCR_MSBUDQ_SHIFT) - -/* - * DXSR (R/W) - * - * Data Slew Rate (D3F I/O Only): Selects slew rate of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. - */ -#define DDRPHY_DXCCR_DXSR_MASK (0x6000U) -#define DDRPHY_DXCCR_DXSR_SHIFT (13U) -#define DDRPHY_DXCCR_DXSR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXSR_SHIFT) & DDRPHY_DXCCR_DXSR_MASK) -#define DDRPHY_DXCCR_DXSR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXSR_MASK) >> DDRPHY_DXCCR_DXSR_SHIFT) - -/* - * DQSNRES (R/W) - * - * DQS# Resistor: Selects the on-die pull-up/pull-down resistor for DQS# pins. Same encoding as DQSRES. - * Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. - */ -#define DDRPHY_DXCCR_DQSNRES_MASK (0x1E00U) -#define DDRPHY_DXCCR_DQSNRES_SHIFT (9U) -#define DDRPHY_DXCCR_DQSNRES_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DQSNRES_SHIFT) & DDRPHY_DXCCR_DQSNRES_MASK) -#define DDRPHY_DXCCR_DQSNRES_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DQSNRES_MASK) >> DDRPHY_DXCCR_DQSNRES_SHIFT) - -/* - * DQSRES (R/W) - * - * DQS Resistor: Selects the on-die pull-down/pull-up resistor for DQS pins. DQSRES[3] selects pull-down (when set to 0) or pull-up (when set to 1). DQSRES[2:0] selects the resistor value. - * Refer PHY databook for pull-down/pull-up resistor values (RA_SEL/RB_SEL) for DQS/DQS_b. - */ -#define DDRPHY_DXCCR_DQSRES_MASK (0x1E0U) -#define DDRPHY_DXCCR_DQSRES_SHIFT (5U) -#define DDRPHY_DXCCR_DQSRES_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DQSRES_SHIFT) & DDRPHY_DXCCR_DQSRES_MASK) -#define DDRPHY_DXCCR_DQSRES_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DQSRES_MASK) >> DDRPHY_DXCCR_DQSRES_SHIFT) - -/* - * DXPDR (R/W) - * - * Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDR configuration bit of the individual DATX8. - */ -#define DDRPHY_DXCCR_DXPDR_MASK (0x10U) -#define DDRPHY_DXCCR_DXPDR_SHIFT (4U) -#define DDRPHY_DXCCR_DXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXPDR_SHIFT) & DDRPHY_DXCCR_DXPDR_MASK) -#define DDRPHY_DXCCR_DXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXPDR_MASK) >> DDRPHY_DXCCR_DXPDR_SHIFT) - -/* - * DXPDD1 (R/W) - * - * Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the PDD configuration bit of the individual DATX8. - */ -#define DDRPHY_DXCCR_DXPDD1_MASK (0x8U) -#define DDRPHY_DXCCR_DXPDD1_SHIFT (3U) -#define DDRPHY_DXCCR_DXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXPDD1_SHIFT) & DDRPHY_DXCCR_DXPDD1_MASK) -#define DDRPHY_DXCCR_DXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXPDD1_MASK) >> DDRPHY_DXCCR_DXPDD1_SHIFT) - -/* - * MDLEN (R/W) - * - * Master Delay Line Enable: Enables, if set, all DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or on when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the MDLEN bit in the individual DATX8. - */ -#define DDRPHY_DXCCR_MDLEN_MASK (0x4U) -#define DDRPHY_DXCCR_MDLEN_SHIFT (2U) -#define DDRPHY_DXCCR_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_MDLEN_SHIFT) & DDRPHY_DXCCR_MDLEN_MASK) -#define DDRPHY_DXCCR_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_MDLEN_MASK) >> DDRPHY_DXCCR_MDLEN_SHIFT) - -/* - * DXIOM (R/W) - * - * Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the IOM configuration bit of the individual DATX8. - */ -#define DDRPHY_DXCCR_DXIOM_MASK (0x2U) -#define DDRPHY_DXCCR_DXIOM_SHIFT (1U) -#define DDRPHY_DXCCR_DXIOM_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXIOM_SHIFT) & DDRPHY_DXCCR_DXIOM_MASK) -#define DDRPHY_DXCCR_DXIOM_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXIOM_MASK) >> DDRPHY_DXCCR_DXIOM_SHIFT) - -/* - * DXODT (R/W) - * - * Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ, DM, and DQS/DQS# pins of all DATX8 macros. This bit is ORed with the ODT configuration bit of the individual DATX8 (“DATX8 General Configuration Register (DXnGCR)” on page 148) - */ -#define DDRPHY_DXCCR_DXODT_MASK (0x1U) -#define DDRPHY_DXCCR_DXODT_SHIFT (0U) -#define DDRPHY_DXCCR_DXODT_SET(x) (((uint32_t)(x) << DDRPHY_DXCCR_DXODT_SHIFT) & DDRPHY_DXCCR_DXODT_MASK) -#define DDRPHY_DXCCR_DXODT_GET(x) (((uint32_t)(x) & DDRPHY_DXCCR_DXODT_MASK) >> DDRPHY_DXCCR_DXODT_SHIFT) - -/* Bitfield definition for register: DSGCR */ -/* - * CKEOE (R/W) - * - * SDRAM CKE Output Enable: Enables, when set, the output driver on the I/O for SDRAM CKE pins. - */ -#define DDRPHY_DSGCR_CKEOE_MASK (0x80000000UL) -#define DDRPHY_DSGCR_CKEOE_SHIFT (31U) -#define DDRPHY_DSGCR_CKEOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKEOE_SHIFT) & DDRPHY_DSGCR_CKEOE_MASK) -#define DDRPHY_DSGCR_CKEOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKEOE_MASK) >> DDRPHY_DSGCR_CKEOE_SHIFT) - -/* - * RSTOE (R/W) - * - * SDRAM Reset Output Enable: Enables, when set, the output driver on the I/O for SDRAM RST# pin. - */ -#define DDRPHY_DSGCR_RSTOE_MASK (0x40000000UL) -#define DDRPHY_DSGCR_RSTOE_SHIFT (30U) -#define DDRPHY_DSGCR_RSTOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_RSTOE_SHIFT) & DDRPHY_DSGCR_RSTOE_MASK) -#define DDRPHY_DSGCR_RSTOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_RSTOE_MASK) >> DDRPHY_DSGCR_RSTOE_SHIFT) - -/* - * ODTOE (R/W) - * - * SDRAM ODT Output Enable: Enables, when set, the output driver on the I/O for SDRAM ODT pins. - */ -#define DDRPHY_DSGCR_ODTOE_MASK (0x20000000UL) -#define DDRPHY_DSGCR_ODTOE_SHIFT (29U) -#define DDRPHY_DSGCR_ODTOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ODTOE_SHIFT) & DDRPHY_DSGCR_ODTOE_MASK) -#define DDRPHY_DSGCR_ODTOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ODTOE_MASK) >> DDRPHY_DSGCR_ODTOE_SHIFT) - -/* - * CKOE (R/W) - * - * SDRAM CK Output Enable: Enables, when set, the output driver on the I/O for SDRAM CK/CK# pins. - */ -#define DDRPHY_DSGCR_CKOE_MASK (0x10000000UL) -#define DDRPHY_DSGCR_CKOE_SHIFT (28U) -#define DDRPHY_DSGCR_CKOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKOE_SHIFT) & DDRPHY_DSGCR_CKOE_MASK) -#define DDRPHY_DSGCR_CKOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKOE_MASK) >> DDRPHY_DSGCR_CKOE_SHIFT) - -/* - * ODTPDD1 (R/W) - * - * ODT Power Down Driver: Powers down, when set, the output driver on the I/O for ODT[3:0] pins. ODTPDD[0] controls the power down for ODT[0], ODTPDD[1] controls the power down for ODT[1], and so on. - */ -#define DDRPHY_DSGCR_ODTPDD1_MASK (0xF000000UL) -#define DDRPHY_DSGCR_ODTPDD1_SHIFT (24U) -#define DDRPHY_DSGCR_ODTPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ODTPDD1_SHIFT) & DDRPHY_DSGCR_ODTPDD1_MASK) -#define DDRPHY_DSGCR_ODTPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ODTPDD1_MASK) >> DDRPHY_DSGCR_ODTPDD1_SHIFT) - -/* - * CKEPDD1 (R/W) - * - * CKE Power Down Driver: Powers down, when set, the output driver on the I/O for CKE[3:0] pins. CKEPDD[0] controls the power down for CKE[0], CKEPDD[1] controls the power down for CKE[1], and so on. - */ -#define DDRPHY_DSGCR_CKEPDD1_MASK (0xF00000UL) -#define DDRPHY_DSGCR_CKEPDD1_SHIFT (20U) -#define DDRPHY_DSGCR_CKEPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CKEPDD1_SHIFT) & DDRPHY_DSGCR_CKEPDD1_MASK) -#define DDRPHY_DSGCR_CKEPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CKEPDD1_MASK) >> DDRPHY_DSGCR_CKEPDD1_SHIFT) - -/* - * SDRMODE (R/W) - * - * Single Data Rate Mode: Indicates, if set, that the external controller is configured to run in single data rate (SDR) mode. Otherwise if not set the controller is running in half data rate (HDR) mode. This bit not supported in the current version of the PUB. - */ -#define DDRPHY_DSGCR_SDRMODE_MASK (0x80000UL) -#define DDRPHY_DSGCR_SDRMODE_SHIFT (19U) -#define DDRPHY_DSGCR_SDRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_SDRMODE_SHIFT) & DDRPHY_DSGCR_SDRMODE_MASK) -#define DDRPHY_DSGCR_SDRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_SDRMODE_MASK) >> DDRPHY_DSGCR_SDRMODE_SHIFT) - -/* - * RRMODE (R/W) - * - * Rise-to-Rise Mode: Indicates, if set, that the PHY mission mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY mission mode is running in rise-to- fall mode. - */ -#define DDRPHY_DSGCR_RRMODE_MASK (0x40000UL) -#define DDRPHY_DSGCR_RRMODE_SHIFT (18U) -#define DDRPHY_DSGCR_RRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_RRMODE_SHIFT) & DDRPHY_DSGCR_RRMODE_MASK) -#define DDRPHY_DSGCR_RRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_RRMODE_MASK) >> DDRPHY_DSGCR_RRMODE_SHIFT) - -/* - * ATOAE (R/W) - * - * ATO Analog Test Enable: Enables, if set, the analog test output (ATO) I/O. - */ -#define DDRPHY_DSGCR_ATOAE_MASK (0x20000UL) -#define DDRPHY_DSGCR_ATOAE_SHIFT (17U) -#define DDRPHY_DSGCR_ATOAE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ATOAE_SHIFT) & DDRPHY_DSGCR_ATOAE_MASK) -#define DDRPHY_DSGCR_ATOAE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ATOAE_MASK) >> DDRPHY_DSGCR_ATOAE_SHIFT) - -/* - * DTOOE (R/W) - * - * DTO Output Enable: Enables, when set, the output driver on the I/O for DTO pins. - */ -#define DDRPHY_DSGCR_DTOOE_MASK (0x10000UL) -#define DDRPHY_DSGCR_DTOOE_SHIFT (16U) -#define DDRPHY_DSGCR_DTOOE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOOE_SHIFT) & DDRPHY_DSGCR_DTOOE_MASK) -#define DDRPHY_DSGCR_DTOOE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOOE_MASK) >> DDRPHY_DSGCR_DTOOE_SHIFT) - -/* - * DTOIOM (R/W) - * - * DTO I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DTO pins. - */ -#define DDRPHY_DSGCR_DTOIOM_MASK (0x8000U) -#define DDRPHY_DSGCR_DTOIOM_SHIFT (15U) -#define DDRPHY_DSGCR_DTOIOM_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOIOM_SHIFT) & DDRPHY_DSGCR_DTOIOM_MASK) -#define DDRPHY_DSGCR_DTOIOM_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOIOM_MASK) >> DDRPHY_DSGCR_DTOIOM_SHIFT) - -/* - * DTOPDR (R/W) - * - * DTO Power Down Receiver: Powers down, when set, the input receiver on the I/O for DTO pins. - */ -#define DDRPHY_DSGCR_DTOPDR_MASK (0x4000U) -#define DDRPHY_DSGCR_DTOPDR_SHIFT (14U) -#define DDRPHY_DSGCR_DTOPDR_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOPDR_SHIFT) & DDRPHY_DSGCR_DTOPDR_MASK) -#define DDRPHY_DSGCR_DTOPDR_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOPDR_MASK) >> DDRPHY_DSGCR_DTOPDR_SHIFT) - -/* - * DTOPDD1 (R/W) - * - * DTO Power Down Driver: Powers down, when set, the output driver on the I/O for DTO pins. - */ -#define DDRPHY_DSGCR_DTOPDD1_MASK (0x2000U) -#define DDRPHY_DSGCR_DTOPDD1_SHIFT (13U) -#define DDRPHY_DSGCR_DTOPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOPDD1_SHIFT) & DDRPHY_DSGCR_DTOPDD1_MASK) -#define DDRPHY_DSGCR_DTOPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOPDD1_MASK) >> DDRPHY_DSGCR_DTOPDD1_SHIFT) - -/* - * DTOODT (R/W) - * - * DTO On-Die Termination: Enables, when set, the on-die termination on the I/O for DTO pins. - */ -#define DDRPHY_DSGCR_DTOODT_MASK (0x1000U) -#define DDRPHY_DSGCR_DTOODT_SHIFT (12U) -#define DDRPHY_DSGCR_DTOODT_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DTOODT_SHIFT) & DDRPHY_DSGCR_DTOODT_MASK) -#define DDRPHY_DSGCR_DTOODT_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DTOODT_MASK) >> DDRPHY_DSGCR_DTOODT_SHIFT) - -/* - * PUAD (R/W) - * - * PHY Update Acknowledge Delay: Specifies the number of clock cycles that the indication for the completion of PHY update from the PHY to the controller should be delayed. This essentially delays, by this many clock cycles, the de-assertion of dfi_ctrlup_ack and dfi_phyupd_req signals relative to the time when the delay lines or I/Os are updated. - */ -#define DDRPHY_DSGCR_PUAD_MASK (0xF00U) -#define DDRPHY_DSGCR_PUAD_SHIFT (8U) -#define DDRPHY_DSGCR_PUAD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_PUAD_SHIFT) & DDRPHY_DSGCR_PUAD_MASK) -#define DDRPHY_DSGCR_PUAD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_PUAD_MASK) >> DDRPHY_DSGCR_PUAD_SHIFT) - -/* - * BRRMODE (R/W) - * - * Bypass Rise-to-Rise Mode: Indicates, if set, that the PHY bypass mode is configured to run in rise-to-rise mode. Otherwise if not set the PHY bypass mode is running in rise-to-fall mode. - */ -#define DDRPHY_DSGCR_BRRMODE_MASK (0x80U) -#define DDRPHY_DSGCR_BRRMODE_SHIFT (7U) -#define DDRPHY_DSGCR_BRRMODE_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_BRRMODE_SHIFT) & DDRPHY_DSGCR_BRRMODE_MASK) -#define DDRPHY_DSGCR_BRRMODE_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_BRRMODE_MASK) >> DDRPHY_DSGCR_BRRMODE_SHIFT) - -/* - * DQSGX (R/W) - * - * DQS Gate Extension: Specifies, if set, that the DQS gating must be extended by two DRAM clock cycles and then re-centered, i.e. one clock cycle extension on either side. - */ -#define DDRPHY_DSGCR_DQSGX_MASK (0x40U) -#define DDRPHY_DSGCR_DQSGX_SHIFT (6U) -#define DDRPHY_DSGCR_DQSGX_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_DQSGX_SHIFT) & DDRPHY_DSGCR_DQSGX_MASK) -#define DDRPHY_DSGCR_DQSGX_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_DQSGX_MASK) >> DDRPHY_DSGCR_DQSGX_SHIFT) - -/* - * CUAEN (R/W) - * - * Controller Update Acknowledge Enable: Specifies, if set, that the PHY should issue controller update acknowledge when the DFI controller update request is asserted. By default the PHY does not acknowledge controller initiated update requests but simply does an update whenever there is a controller update request. This speeds up the update. - */ -#define DDRPHY_DSGCR_CUAEN_MASK (0x20U) -#define DDRPHY_DSGCR_CUAEN_SHIFT (5U) -#define DDRPHY_DSGCR_CUAEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_CUAEN_SHIFT) & DDRPHY_DSGCR_CUAEN_MASK) -#define DDRPHY_DSGCR_CUAEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_CUAEN_MASK) >> DDRPHY_DSGCR_CUAEN_SHIFT) - -/* - * LPPLLPD (R/W) - * - * Low Power PLL Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the PLL of the byte if the wakeup time request satisfies the PLL lock time. - */ -#define DDRPHY_DSGCR_LPPLLPD_MASK (0x10U) -#define DDRPHY_DSGCR_LPPLLPD_SHIFT (4U) -#define DDRPHY_DSGCR_LPPLLPD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_LPPLLPD_SHIFT) & DDRPHY_DSGCR_LPPLLPD_MASK) -#define DDRPHY_DSGCR_LPPLLPD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_LPPLLPD_MASK) >> DDRPHY_DSGCR_LPPLLPD_SHIFT) - -/* - * LPIOPD (R/W) - * - * Low Power I/O Power Down: Specifies, if set, that the PHY should respond to the DFI low power opportunity request and power down the I/Os of the byte. - */ -#define DDRPHY_DSGCR_LPIOPD_MASK (0x8U) -#define DDRPHY_DSGCR_LPIOPD_SHIFT (3U) -#define DDRPHY_DSGCR_LPIOPD_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_LPIOPD_SHIFT) & DDRPHY_DSGCR_LPIOPD_MASK) -#define DDRPHY_DSGCR_LPIOPD_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_LPIOPD_MASK) >> DDRPHY_DSGCR_LPIOPD_SHIFT) - -/* - * ZUEN (R/W) - * - * Impedance Update Enable: Specifies, if set, that in addition to DDL VT update, the PHY could also perform impedance calibration (update). - * Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFICU0, DFICU1 and DFICCU bits to control if an impedance calibration is performed (update) with a DFI controller update request. - * Refer to the “Impedance Control Register 0-1 (ZQnCR0-1)” on page 145 bit fields DFIPU0 and DFIPU1 bits to control if an impedance calibration is performed (update) with a DFI PHY update request. - */ -#define DDRPHY_DSGCR_ZUEN_MASK (0x4U) -#define DDRPHY_DSGCR_ZUEN_SHIFT (2U) -#define DDRPHY_DSGCR_ZUEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_ZUEN_SHIFT) & DDRPHY_DSGCR_ZUEN_MASK) -#define DDRPHY_DSGCR_ZUEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_ZUEN_MASK) >> DDRPHY_DSGCR_ZUEN_SHIFT) - -/* - * BDISEN (R/W) - * - * Byte Disable Enable: Specifies, if set, that the PHY should respond to DFI byte disable request. Otherwise the byte disable from the DFI is ignored in which case bytes can only be disabled using the DXnGCR register. - */ -#define DDRPHY_DSGCR_BDISEN_MASK (0x2U) -#define DDRPHY_DSGCR_BDISEN_SHIFT (1U) -#define DDRPHY_DSGCR_BDISEN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_BDISEN_SHIFT) & DDRPHY_DSGCR_BDISEN_MASK) -#define DDRPHY_DSGCR_BDISEN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_BDISEN_MASK) >> DDRPHY_DSGCR_BDISEN_SHIFT) - -/* - * PUREN (R/W) - * - * PHY Update Request Enable: Specifies if set, that the PHY should issue PHY- initiated update request when there is DDL VT drift. - */ -#define DDRPHY_DSGCR_PUREN_MASK (0x1U) -#define DDRPHY_DSGCR_PUREN_SHIFT (0U) -#define DDRPHY_DSGCR_PUREN_SET(x) (((uint32_t)(x) << DDRPHY_DSGCR_PUREN_SHIFT) & DDRPHY_DSGCR_PUREN_MASK) -#define DDRPHY_DSGCR_PUREN_GET(x) (((uint32_t)(x) & DDRPHY_DSGCR_PUREN_MASK) >> DDRPHY_DSGCR_PUREN_SHIFT) - -/* Bitfield definition for register: DCR */ -/* - * UDIMM (R/W) - * - * Un-buffered DIMM Address Mirroring: Indicates, if set, that there is address mirroring on the second rank of an un-buffered DIMM (the rank connected to CS#[1]). In this case, the PUB re-scrambles the bank and address when sending mode register commands to the second rank. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments when using an un-buffered DIMM. DCR[NOSRA] must be set if address mirroring is enabled. - */ -#define DDRPHY_DCR_UDIMM_MASK (0x20000000UL) -#define DDRPHY_DCR_UDIMM_SHIFT (29U) -#define DDRPHY_DCR_UDIMM_SET(x) (((uint32_t)(x) << DDRPHY_DCR_UDIMM_SHIFT) & DDRPHY_DCR_UDIMM_MASK) -#define DDRPHY_DCR_UDIMM_GET(x) (((uint32_t)(x) & DDRPHY_DCR_UDIMM_MASK) >> DDRPHY_DCR_UDIMM_SHIFT) - -/* - * DDR2T (R/W) - * - * DDR 2T Timing: Indicates, if set, that 2T timing should be used by PUB internally generated SDRAM transactions. - */ -#define DDRPHY_DCR_DDR2T_MASK (0x10000000UL) -#define DDRPHY_DCR_DDR2T_SHIFT (28U) -#define DDRPHY_DCR_DDR2T_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDR2T_SHIFT) & DDRPHY_DCR_DDR2T_MASK) -#define DDRPHY_DCR_DDR2T_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDR2T_MASK) >> DDRPHY_DCR_DDR2T_SHIFT) - -/* - * NOSRA (R/W) - * - * No Simultaneous Rank Access: Specifies, if set, that simultaneous rank access on the same clock cycle is not allowed. This means that multiple chip select signals should not be asserted at the same time. This may be required on some DIMM systems. - */ -#define DDRPHY_DCR_NOSRA_MASK (0x8000000UL) -#define DDRPHY_DCR_NOSRA_SHIFT (27U) -#define DDRPHY_DCR_NOSRA_SET(x) (((uint32_t)(x) << DDRPHY_DCR_NOSRA_SHIFT) & DDRPHY_DCR_NOSRA_MASK) -#define DDRPHY_DCR_NOSRA_GET(x) (((uint32_t)(x) & DDRPHY_DCR_NOSRA_MASK) >> DDRPHY_DCR_NOSRA_SHIFT) - -/* - * BYTEMASK (R/W) - * - * Byte Mask: Mask applied to all beats of read data on all bytes lanes during read DQS gate training. This allows training to be conducted based on selected bit(s) from the byte lanes. - * Valid values for each bit are: - * 0 = Disable compare for that bit 1 = Enable compare for that bit - * Note that this mask applies in DDR3 MPR operation mode as well and must be in keeping with the PDQ field setting. - */ -#define DDRPHY_DCR_BYTEMASK_MASK (0x3FC00UL) -#define DDRPHY_DCR_BYTEMASK_SHIFT (10U) -#define DDRPHY_DCR_BYTEMASK_SET(x) (((uint32_t)(x) << DDRPHY_DCR_BYTEMASK_SHIFT) & DDRPHY_DCR_BYTEMASK_MASK) -#define DDRPHY_DCR_BYTEMASK_GET(x) (((uint32_t)(x) & DDRPHY_DCR_BYTEMASK_MASK) >> DDRPHY_DCR_BYTEMASK_SHIFT) - -/* - * MPRDQ (R/W) - * - * Multi-Purpose Register (MPR) DQ (DDR3 Only): Specifies the value that is driven on non-primary DQ pins during MPR reads. Valid values are: - * 0 = Primary DQ drives out the data from MPR (0-1-0-1); non-primary DQs drive ‘0’ 1 = Primary DQ and non-primary DQs all drive the same data from MPR (0-1-0-1) - */ -#define DDRPHY_DCR_MPRDQ_MASK (0x80U) -#define DDRPHY_DCR_MPRDQ_SHIFT (7U) -#define DDRPHY_DCR_MPRDQ_SET(x) (((uint32_t)(x) << DDRPHY_DCR_MPRDQ_SHIFT) & DDRPHY_DCR_MPRDQ_MASK) -#define DDRPHY_DCR_MPRDQ_GET(x) (((uint32_t)(x) & DDRPHY_DCR_MPRDQ_MASK) >> DDRPHY_DCR_MPRDQ_SHIFT) - -/* - * PDQ (R/W) - * - * Primary DQ (DDR3 Only): Specifies the DQ pin in a byte that is designated as a primary pin for Multi-Purpose Register (MPR) reads. Valid values are 0 to 7 for DQ[0] to DQ[7], respectively. - */ -#define DDRPHY_DCR_PDQ_MASK (0x70U) -#define DDRPHY_DCR_PDQ_SHIFT (4U) -#define DDRPHY_DCR_PDQ_SET(x) (((uint32_t)(x) << DDRPHY_DCR_PDQ_SHIFT) & DDRPHY_DCR_PDQ_MASK) -#define DDRPHY_DCR_PDQ_GET(x) (((uint32_t)(x) & DDRPHY_DCR_PDQ_MASK) >> DDRPHY_DCR_PDQ_SHIFT) - -/* - * DDR8BNK (R/W) - * - * DDR 8-Bank: Indicates, if set, that the SDRAM used has 8 banks. tRPA = tRP+1 and tFAW are used for 8-bank DRAMs, otherwise tRPA = tRP and no tFAW is used. - * Note that a setting of 1 for DRAMs that have fewer than 8 banks results in correct functionality, but less tight DRAM command spacing for the parameters. - */ -#define DDRPHY_DCR_DDR8BNK_MASK (0x8U) -#define DDRPHY_DCR_DDR8BNK_SHIFT (3U) -#define DDRPHY_DCR_DDR8BNK_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDR8BNK_SHIFT) & DDRPHY_DCR_DDR8BNK_MASK) -#define DDRPHY_DCR_DDR8BNK_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDR8BNK_MASK) >> DDRPHY_DCR_DDR8BNK_SHIFT) - -/* - * DDRMD (R/W) - * - * DDR Mode: SDRAM DDR mode. Valid values are: 000 = Reserved - * 001 = Reserved - * 010 = DDR2 - * 011 = DDR3 - * 100 – 111 = Reserved - */ -#define DDRPHY_DCR_DDRMD_MASK (0x7U) -#define DDRPHY_DCR_DDRMD_SHIFT (0U) -#define DDRPHY_DCR_DDRMD_SET(x) (((uint32_t)(x) << DDRPHY_DCR_DDRMD_SHIFT) & DDRPHY_DCR_DDRMD_MASK) -#define DDRPHY_DCR_DDRMD_GET(x) (((uint32_t)(x) & DDRPHY_DCR_DDRMD_MASK) >> DDRPHY_DCR_DDRMD_SHIFT) - -/* Bitfield definition for register: DTPR0 */ -/* - * TRC (R/W) - * - * Activate to activate command delay (same bank). Valid values are 2 to 63. - */ -#define DDRPHY_DTPR0_TRC_MASK (0xFC000000UL) -#define DDRPHY_DTPR0_TRC_SHIFT (26U) -#define DDRPHY_DTPR0_TRC_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRC_SHIFT) & DDRPHY_DTPR0_TRC_MASK) -#define DDRPHY_DTPR0_TRC_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRC_MASK) >> DDRPHY_DTPR0_TRC_SHIFT) - -/* - * TRRD (R/W) - * - * Activate to activate command delay (different banks). Valid values are 1 to 15. - */ -#define DDRPHY_DTPR0_TRRD_MASK (0x3C00000UL) -#define DDRPHY_DTPR0_TRRD_SHIFT (22U) -#define DDRPHY_DTPR0_TRRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRRD_SHIFT) & DDRPHY_DTPR0_TRRD_MASK) -#define DDRPHY_DTPR0_TRRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRRD_MASK) >> DDRPHY_DTPR0_TRRD_SHIFT) - -/* - * TRAS (R/W) - * - * Activate to precharge command delay. Valid values are 2 to 63. - */ -#define DDRPHY_DTPR0_TRAS_MASK (0x3F0000UL) -#define DDRPHY_DTPR0_TRAS_SHIFT (16U) -#define DDRPHY_DTPR0_TRAS_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRAS_SHIFT) & DDRPHY_DTPR0_TRAS_MASK) -#define DDRPHY_DTPR0_TRAS_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRAS_MASK) >> DDRPHY_DTPR0_TRAS_SHIFT) - -/* - * TRCD (R/W) - * - * Activate to read or write delay. Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 15. - */ -#define DDRPHY_DTPR0_TRCD_MASK (0xF000U) -#define DDRPHY_DTPR0_TRCD_SHIFT (12U) -#define DDRPHY_DTPR0_TRCD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRCD_SHIFT) & DDRPHY_DTPR0_TRCD_MASK) -#define DDRPHY_DTPR0_TRCD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRCD_MASK) >> DDRPHY_DTPR0_TRCD_SHIFT) - -/* - * TRP (R/W) - * - * Precharge command period: The minimum time between a precharge command and any other command. Note that the Controller automatically derives tRPA for 8- bank DDR2 devices by adding 1 to tRP. Valid values are 2 to 15. - */ -#define DDRPHY_DTPR0_TRP_MASK (0xF00U) -#define DDRPHY_DTPR0_TRP_SHIFT (8U) -#define DDRPHY_DTPR0_TRP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRP_SHIFT) & DDRPHY_DTPR0_TRP_MASK) -#define DDRPHY_DTPR0_TRP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRP_MASK) >> DDRPHY_DTPR0_TRP_SHIFT) - -/* - * TWTR (R/W) - * - * Internal write to read command delay. Valid values are 1 to 15. - */ -#define DDRPHY_DTPR0_TWTR_MASK (0xF0U) -#define DDRPHY_DTPR0_TWTR_SHIFT (4U) -#define DDRPHY_DTPR0_TWTR_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TWTR_SHIFT) & DDRPHY_DTPR0_TWTR_MASK) -#define DDRPHY_DTPR0_TWTR_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TWTR_MASK) >> DDRPHY_DTPR0_TWTR_SHIFT) - -/* - * TRTP (R/W) - * - * Internal read to precharge command delay. Valid values are 2 to 15. - */ -#define DDRPHY_DTPR0_TRTP_MASK (0xFU) -#define DDRPHY_DTPR0_TRTP_SHIFT (0U) -#define DDRPHY_DTPR0_TRTP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR0_TRTP_SHIFT) & DDRPHY_DTPR0_TRTP_MASK) -#define DDRPHY_DTPR0_TRTP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR0_TRTP_MASK) >> DDRPHY_DTPR0_TRTP_SHIFT) - -/* Bitfield definition for register: DTPR1 */ -/* - * TAOND_TAOFD (R/W) - * - * ODT turn-on/turn-off delays (DDR2 only). Valid values are: 00 = 2/2.5 - * 01 = 3/3.5 - * 10 = 4/4.5 - * 11 = 5/5.5 - * Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational Write Latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a Write Latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher. - */ -#define DDRPHY_DTPR1_TAOND_TAOFD_MASK (0xC0000000UL) -#define DDRPHY_DTPR1_TAOND_TAOFD_SHIFT (30U) -#define DDRPHY_DTPR1_TAOND_TAOFD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TAOND_TAOFD_SHIFT) & DDRPHY_DTPR1_TAOND_TAOFD_MASK) -#define DDRPHY_DTPR1_TAOND_TAOFD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TAOND_TAOFD_MASK) >> DDRPHY_DTPR1_TAOND_TAOFD_SHIFT) - -/* - * TWLO (R/W) - * - * Write leveling output delay: Number of clock cycles from when write leveling DQS is driven high by the control block to when the results from the SDRAM on DQ is sampled by the control block. This must include the SDRAM tWLO timing parameter plus the round trip delay from control block to SDRAM back to control block. - */ -#define DDRPHY_DTPR1_TWLO_MASK (0x3C000000UL) -#define DDRPHY_DTPR1_TWLO_SHIFT (26U) -#define DDRPHY_DTPR1_TWLO_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TWLO_SHIFT) & DDRPHY_DTPR1_TWLO_MASK) -#define DDRPHY_DTPR1_TWLO_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TWLO_MASK) >> DDRPHY_DTPR1_TWLO_SHIFT) - -/* - * TWLMRD (R/W) - * - * Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. - */ -#define DDRPHY_DTPR1_TWLMRD_MASK (0x3F00000UL) -#define DDRPHY_DTPR1_TWLMRD_SHIFT (20U) -#define DDRPHY_DTPR1_TWLMRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TWLMRD_SHIFT) & DDRPHY_DTPR1_TWLMRD_MASK) -#define DDRPHY_DTPR1_TWLMRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TWLMRD_MASK) >> DDRPHY_DTPR1_TWLMRD_SHIFT) - -/* - * TRFC (R/W) - * - * Refresh-to-Refresh: Indicates the minimum time between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, tRFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC tRFC(min parameter value supported. - */ -#define DDRPHY_DTPR1_TRFC_MASK (0xFF800UL) -#define DDRPHY_DTPR1_TRFC_SHIFT (11U) -#define DDRPHY_DTPR1_TRFC_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TRFC_SHIFT) & DDRPHY_DTPR1_TRFC_MASK) -#define DDRPHY_DTPR1_TRFC_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TRFC_MASK) >> DDRPHY_DTPR1_TRFC_SHIFT) - -/* - * TFAW (R/W) - * - * 4-bank activate period. No more than 4-bank activate commands may be issued in a given tFAW period. Only applies to 8-bank devices. Valid values are 2 to 63. - */ -#define DDRPHY_DTPR1_TFAW_MASK (0x7E0U) -#define DDRPHY_DTPR1_TFAW_SHIFT (5U) -#define DDRPHY_DTPR1_TFAW_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TFAW_SHIFT) & DDRPHY_DTPR1_TFAW_MASK) -#define DDRPHY_DTPR1_TFAW_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TFAW_MASK) >> DDRPHY_DTPR1_TFAW_SHIFT) - -/* - * TMOD (R/W) - * - * Load mode update delay (DDR3 only). The minimum time between a load mode register command and a non-load mode register command. Valid values are: 000 = 12 - * 001 = 13 - * 010 = 14 - * 011 = 15 - * 100 = 16 - * 101 = 17 - * 110 – 111 = Reserved - */ -#define DDRPHY_DTPR1_TMOD_MASK (0x1CU) -#define DDRPHY_DTPR1_TMOD_SHIFT (2U) -#define DDRPHY_DTPR1_TMOD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TMOD_SHIFT) & DDRPHY_DTPR1_TMOD_MASK) -#define DDRPHY_DTPR1_TMOD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TMOD_MASK) >> DDRPHY_DTPR1_TMOD_SHIFT) - -/* - * TMRD (R/W) - * - * Load mode cycle time: The minimum time between a load mode register command and any other command. For DDR3 this is the minimum time between two load mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for tMRD is 4 plus the value programmed in these bits, i.e. tMRD value for DDR3 ranges from 4 to 7. - */ -#define DDRPHY_DTPR1_TMRD_MASK (0x3U) -#define DDRPHY_DTPR1_TMRD_SHIFT (0U) -#define DDRPHY_DTPR1_TMRD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR1_TMRD_SHIFT) & DDRPHY_DTPR1_TMRD_MASK) -#define DDRPHY_DTPR1_TMRD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR1_TMRD_MASK) >> DDRPHY_DTPR1_TMRD_SHIFT) - -/* Bitfield definition for register: DTPR2 */ -/* - * TCCD (R/W) - * - * Read to read and write to write command delay. Valid values are: 0 = BL/2 for DDR2 and 4 for DDR3 - * 1 = BL/2 + 1 for DDR2 and 5 for DDR3 - */ -#define DDRPHY_DTPR2_TCCD_MASK (0x80000000UL) -#define DDRPHY_DTPR2_TCCD_SHIFT (31U) -#define DDRPHY_DTPR2_TCCD_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TCCD_SHIFT) & DDRPHY_DTPR2_TCCD_MASK) -#define DDRPHY_DTPR2_TCCD_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TCCD_MASK) >> DDRPHY_DTPR2_TCCD_SHIFT) - -/* - * TRTW (R/W) - * - * Read to Write command delay. Valid values are: - * 0 = standard bus turn around delay - * 1 = add 1 clock to standard bus turn around delay - * This parameter allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turn-around margin for high frequency systems. - */ -#define DDRPHY_DTPR2_TRTW_MASK (0x40000000UL) -#define DDRPHY_DTPR2_TRTW_SHIFT (30U) -#define DDRPHY_DTPR2_TRTW_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TRTW_SHIFT) & DDRPHY_DTPR2_TRTW_MASK) -#define DDRPHY_DTPR2_TRTW_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TRTW_MASK) >> DDRPHY_DTPR2_TRTW_SHIFT) - -/* - * TRTODT (R/W) - * - * Read to ODT delay (DDR3 only). Specifies whether ODT can be enabled immediately after the read post-amble or one clock delay has to be added. Valid values are: - * 0 = ODT may be turned on immediately after read post-amble - * 1 = ODT may not be turned on until one clock after the read post-amble - * If tRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled. - */ -#define DDRPHY_DTPR2_TRTODT_MASK (0x20000000UL) -#define DDRPHY_DTPR2_TRTODT_SHIFT (29U) -#define DDRPHY_DTPR2_TRTODT_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TRTODT_SHIFT) & DDRPHY_DTPR2_TRTODT_MASK) -#define DDRPHY_DTPR2_TRTODT_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TRTODT_MASK) >> DDRPHY_DTPR2_TRTODT_SHIFT) - -/* - * TDLLK (R/W) - * - * DLL locking time. Valid values are 2 to 1023. - */ -#define DDRPHY_DTPR2_TDLLK_MASK (0x1FF80000UL) -#define DDRPHY_DTPR2_TDLLK_SHIFT (19U) -#define DDRPHY_DTPR2_TDLLK_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TDLLK_SHIFT) & DDRPHY_DTPR2_TDLLK_MASK) -#define DDRPHY_DTPR2_TDLLK_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TDLLK_MASK) >> DDRPHY_DTPR2_TDLLK_SHIFT) - -/* - * TCKE (R/W) - * - * CKE minimum pulse width. Also specifies the minimum time that the SDRAM must remain in power down or self refresh mode. For DDR3 this parameter must be set to the value of tCKESR which is usually bigger than the value of tCKE. Valid values are 2 to 15. - */ -#define DDRPHY_DTPR2_TCKE_MASK (0x78000UL) -#define DDRPHY_DTPR2_TCKE_SHIFT (15U) -#define DDRPHY_DTPR2_TCKE_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TCKE_SHIFT) & DDRPHY_DTPR2_TCKE_MASK) -#define DDRPHY_DTPR2_TCKE_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TCKE_MASK) >> DDRPHY_DTPR2_TCKE_SHIFT) - -/* - * TXP (R/W) - * - * Power down exit delay. The minimum time between a power down exit command and any other command. This parameter must be set to the maximum of the various minimum power down exit delay parameters specified in the SDRAM datasheet, i.e. max(tXP, tXARD, tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3. Valid values are 2 to 31. - */ -#define DDRPHY_DTPR2_TXP_MASK (0x7C00U) -#define DDRPHY_DTPR2_TXP_SHIFT (10U) -#define DDRPHY_DTPR2_TXP_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TXP_SHIFT) & DDRPHY_DTPR2_TXP_MASK) -#define DDRPHY_DTPR2_TXP_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TXP_MASK) >> DDRPHY_DTPR2_TXP_SHIFT) - -/* - * TXS (R/W) - * - * Self refresh exit delay. The minimum time between a self refresh exit command and any other command. This parameter must be set to the maximum of the various minimum self refresh exit delay parameters specified in the SDRAM datasheet, i.e. max(tXSNR, tXSRD) for DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to 1023. - */ -#define DDRPHY_DTPR2_TXS_MASK (0x3FFU) -#define DDRPHY_DTPR2_TXS_SHIFT (0U) -#define DDRPHY_DTPR2_TXS_SET(x) (((uint32_t)(x) << DDRPHY_DTPR2_TXS_SHIFT) & DDRPHY_DTPR2_TXS_MASK) -#define DDRPHY_DTPR2_TXS_GET(x) (((uint32_t)(x) & DDRPHY_DTPR2_TXS_MASK) >> DDRPHY_DTPR2_TXS_SHIFT) - -/* Bitfield definition for register: MR0 */ -/* - * PD (R/W) - * - * Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: - * 0 = Slow exit (DLL off) 1 = Fast exit (DLL on) - */ -#define DDRPHY_MR0_PD_MASK (0x1000U) -#define DDRPHY_MR0_PD_SHIFT (12U) -#define DDRPHY_MR0_PD_SET(x) (((uint32_t)(x) << DDRPHY_MR0_PD_SHIFT) & DDRPHY_MR0_PD_MASK) -#define DDRPHY_MR0_PD_GET(x) (((uint32_t)(x) & DDRPHY_MR0_PD_MASK) >> DDRPHY_MR0_PD_SHIFT) - -/* - * WR (R/W) - * - * Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: - * 000 = 16 - * 001 = 5 - * 010 = 6 - * 011 = 7 - * 100 = 8 - * 101 = 10 - * 110 = 12 - * 111 = 14 - * All other settings are reserved and should not be used. - * NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. - */ -#define DDRPHY_MR0_WR_MASK (0xE00U) -#define DDRPHY_MR0_WR_SHIFT (9U) -#define DDRPHY_MR0_WR_SET(x) (((uint32_t)(x) << DDRPHY_MR0_WR_SHIFT) & DDRPHY_MR0_WR_MASK) -#define DDRPHY_MR0_WR_GET(x) (((uint32_t)(x) & DDRPHY_MR0_WR_MASK) >> DDRPHY_MR0_WR_SHIFT) - -/* - * DR (R/W) - * - * DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. - */ -#define DDRPHY_MR0_DR_MASK (0x100U) -#define DDRPHY_MR0_DR_SHIFT (8U) -#define DDRPHY_MR0_DR_SET(x) (((uint32_t)(x) << DDRPHY_MR0_DR_SHIFT) & DDRPHY_MR0_DR_MASK) -#define DDRPHY_MR0_DR_GET(x) (((uint32_t)(x) & DDRPHY_MR0_DR_MASK) >> DDRPHY_MR0_DR_SHIFT) - -/* - * TM (R/W) - * - * Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. - */ -#define DDRPHY_MR0_TM_MASK (0x80U) -#define DDRPHY_MR0_TM_SHIFT (7U) -#define DDRPHY_MR0_TM_SET(x) (((uint32_t)(x) << DDRPHY_MR0_TM_SHIFT) & DDRPHY_MR0_TM_MASK) -#define DDRPHY_MR0_TM_GET(x) (((uint32_t)(x) & DDRPHY_MR0_TM_MASK) >> DDRPHY_MR0_TM_SHIFT) - -/* - * CLH (R/W) - * - * CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: - * 0010 = 5 - * 0100 = 6 - * 0110 = 7 - * 1000 = 8 - * 1010 = 9 - * 1100 = 10 - * 1110 = 11 - * 0001 = 12 - * 0011 = 13 - * 0101 = 14 - * All other settings are reserved and should not be used. - */ -#define DDRPHY_MR0_CLH_MASK (0x70U) -#define DDRPHY_MR0_CLH_SHIFT (4U) -#define DDRPHY_MR0_CLH_SET(x) (((uint32_t)(x) << DDRPHY_MR0_CLH_SHIFT) & DDRPHY_MR0_CLH_MASK) -#define DDRPHY_MR0_CLH_GET(x) (((uint32_t)(x) & DDRPHY_MR0_CLH_MASK) >> DDRPHY_MR0_CLH_SHIFT) - -/* - * BT (R/W) - * - * Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). - */ -#define DDRPHY_MR0_BT_MASK (0x8U) -#define DDRPHY_MR0_BT_SHIFT (3U) -#define DDRPHY_MR0_BT_SET(x) (((uint32_t)(x) << DDRPHY_MR0_BT_SHIFT) & DDRPHY_MR0_BT_MASK) -#define DDRPHY_MR0_BT_GET(x) (((uint32_t)(x) & DDRPHY_MR0_BT_MASK) >> DDRPHY_MR0_BT_SHIFT) - -/* - * CLL (R/W) - * - * CAS Latency low bit - */ -#define DDRPHY_MR0_CLL_MASK (0x4U) -#define DDRPHY_MR0_CLL_SHIFT (2U) -#define DDRPHY_MR0_CLL_SET(x) (((uint32_t)(x) << DDRPHY_MR0_CLL_SHIFT) & DDRPHY_MR0_CLL_MASK) -#define DDRPHY_MR0_CLL_GET(x) (((uint32_t)(x) & DDRPHY_MR0_CLL_MASK) >> DDRPHY_MR0_CLL_SHIFT) - -/* - * BL (R/W) - * - * Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: - * Valid values for DDR3 are: 00 = 8 (Fixed) - * 01 = 4 or 8 (On the fly) - * 10 = 4 (Fixed) - * 11 = Reserved - */ -#define DDRPHY_MR0_BL_MASK (0x3U) -#define DDRPHY_MR0_BL_SHIFT (0U) -#define DDRPHY_MR0_BL_SET(x) (((uint32_t)(x) << DDRPHY_MR0_BL_SHIFT) & DDRPHY_MR0_BL_MASK) -#define DDRPHY_MR0_BL_GET(x) (((uint32_t)(x) & DDRPHY_MR0_BL_MASK) >> DDRPHY_MR0_BL_SHIFT) - -/* Bitfield definition for register: MR */ -/* - * PD (R/W) - * - * Power-Down Control: Controls the exit time for power-down modes. Refer to the SDRAM datasheet for details on power-down modes. Valid values are: - * 0 = Fast exit 1 = Slow exit - */ -#define DDRPHY_MR_PD_MASK (0x1000U) -#define DDRPHY_MR_PD_SHIFT (12U) -#define DDRPHY_MR_PD_SET(x) (((uint32_t)(x) << DDRPHY_MR_PD_SHIFT) & DDRPHY_MR_PD_MASK) -#define DDRPHY_MR_PD_GET(x) (((uint32_t)(x) & DDRPHY_MR_PD_MASK) >> DDRPHY_MR_PD_SHIFT) - -/* - * WR (R/W) - * - * Write Recovery: This is the value of the write recovery. It is calculated by dividing the datasheet write recovery time, tWR (ns) by the datasheet clock cycle time, tCK (ns) and rounding up a non-integer value to the next integer. Valid values are: - * 001 = 2 - * 010 = 3 - * 011 = 4 - * 100 = 5 - * 101 = 6 - * All other settings are reserved and should not be used. - * NOTE: tWR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued. - */ -#define DDRPHY_MR_WR_MASK (0xE00U) -#define DDRPHY_MR_WR_SHIFT (9U) -#define DDRPHY_MR_WR_SET(x) (((uint32_t)(x) << DDRPHY_MR_WR_SHIFT) & DDRPHY_MR_WR_MASK) -#define DDRPHY_MR_WR_GET(x) (((uint32_t)(x) & DDRPHY_MR_WR_MASK) >> DDRPHY_MR_WR_SHIFT) - -/* - * DR (R/W) - * - * DLL Reset: Writing a ‘1’ to this bit will reset the SDRAM DLL. This bit is self- clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued. - */ -#define DDRPHY_MR_DR_MASK (0x100U) -#define DDRPHY_MR_DR_SHIFT (8U) -#define DDRPHY_MR_DR_SET(x) (((uint32_t)(x) << DDRPHY_MR_DR_SHIFT) & DDRPHY_MR_DR_MASK) -#define DDRPHY_MR_DR_GET(x) (((uint32_t)(x) & DDRPHY_MR_DR_MASK) >> DDRPHY_MR_DR_SHIFT) - -/* - * TM (R/W) - * - * Operating Mode: Selects either normal operating mode (0) or test mode (1). Test mode is reserved for the manufacturer and should not be used. - */ -#define DDRPHY_MR_TM_MASK (0x80U) -#define DDRPHY_MR_TM_SHIFT (7U) -#define DDRPHY_MR_TM_SET(x) (((uint32_t)(x) << DDRPHY_MR_TM_SHIFT) & DDRPHY_MR_TM_MASK) -#define DDRPHY_MR_TM_GET(x) (((uint32_t)(x) & DDRPHY_MR_TM_MASK) >> DDRPHY_MR_TM_SHIFT) - -/* - * CL (R/W) - * - * CAS Latency: The delay between when the SDRAM registers a read command to when data is available. Valid values are: - * 010 = 2 - * 011 = 3 - * 100 = 4 - * 101 = 5 - * 110 = 6 - * 111 = 7 - * All other settings are reserved and should not be used. - */ -#define DDRPHY_MR_CL_MASK (0x70U) -#define DDRPHY_MR_CL_SHIFT (4U) -#define DDRPHY_MR_CL_SET(x) (((uint32_t)(x) << DDRPHY_MR_CL_SHIFT) & DDRPHY_MR_CL_MASK) -#define DDRPHY_MR_CL_GET(x) (((uint32_t)(x) & DDRPHY_MR_CL_MASK) >> DDRPHY_MR_CL_SHIFT) - -/* - * BT (R/W) - * - * Burst Type: Indicates whether a burst is sequential (0) or interleaved (1). - */ -#define DDRPHY_MR_BT_MASK (0x8U) -#define DDRPHY_MR_BT_SHIFT (3U) -#define DDRPHY_MR_BT_SET(x) (((uint32_t)(x) << DDRPHY_MR_BT_SHIFT) & DDRPHY_MR_BT_MASK) -#define DDRPHY_MR_BT_GET(x) (((uint32_t)(x) & DDRPHY_MR_BT_MASK) >> DDRPHY_MR_BT_SHIFT) - -/* - * BL (R/W) - * - * Burst Length: Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are: - * 010 = 4 - * 011 = 8 - * All other settings are reserved and should not be used. - */ -#define DDRPHY_MR_BL_MASK (0x7U) -#define DDRPHY_MR_BL_SHIFT (0U) -#define DDRPHY_MR_BL_SET(x) (((uint32_t)(x) << DDRPHY_MR_BL_SHIFT) & DDRPHY_MR_BL_MASK) -#define DDRPHY_MR_BL_GET(x) (((uint32_t)(x) & DDRPHY_MR_BL_MASK) >> DDRPHY_MR_BL_SHIFT) - -/* Bitfield definition for register: MR1 */ -/* - * QOFF (R/W) - * - * Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and should not be used in normal operation. - */ -#define DDRPHY_MR1_QOFF_MASK (0x1000U) -#define DDRPHY_MR1_QOFF_SHIFT (12U) -#define DDRPHY_MR1_QOFF_SET(x) (((uint32_t)(x) << DDRPHY_MR1_QOFF_SHIFT) & DDRPHY_MR1_QOFF_MASK) -#define DDRPHY_MR1_QOFF_GET(x) (((uint32_t)(x) & DDRPHY_MR1_QOFF_MASK) >> DDRPHY_MR1_QOFF_SHIFT) - -/* - * TDQS (R/W) - * - * Termination Data Strobe: When enabled (‘1’) TDQS provides additional termination resistance outputs that may be useful in some system configurations. Refer to the SDRAM datasheet for details. - */ -#define DDRPHY_MR1_TDQS_MASK (0x800U) -#define DDRPHY_MR1_TDQS_SHIFT (11U) -#define DDRPHY_MR1_TDQS_SET(x) (((uint32_t)(x) << DDRPHY_MR1_TDQS_SHIFT) & DDRPHY_MR1_TDQS_MASK) -#define DDRPHY_MR1_TDQS_GET(x) (((uint32_t)(x) & DDRPHY_MR1_TDQS_MASK) >> DDRPHY_MR1_TDQS_SHIFT) - -/* - * RTTH (R/W) - * - * On Die Termination high bit - */ -#define DDRPHY_MR1_RTTH_MASK (0x200U) -#define DDRPHY_MR1_RTTH_SHIFT (9U) -#define DDRPHY_MR1_RTTH_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTH_SHIFT) & DDRPHY_MR1_RTTH_MASK) -#define DDRPHY_MR1_RTTH_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTH_MASK) >> DDRPHY_MR1_RTTH_SHIFT) - -/* - * LEVEL (R/W) - * - * Write Leveling Enable: Enables write-leveling when set. - */ -#define DDRPHY_MR1_LEVEL_MASK (0x80U) -#define DDRPHY_MR1_LEVEL_SHIFT (7U) -#define DDRPHY_MR1_LEVEL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_LEVEL_SHIFT) & DDRPHY_MR1_LEVEL_MASK) -#define DDRPHY_MR1_LEVEL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_LEVEL_MASK) >> DDRPHY_MR1_LEVEL_SHIFT) - -/* - * RTTM (R/W) - * - * On Die Termination mid bit: - * Selects the effective resistance for SDRAM on die termination. Valid values are: - * 000 = ODT disabled 001 = RZQ/4 - * 010 = RZQ/2 - * 011 = RZQ/6 - * 100 = RZQ/12 - * 101 = RZQ/8 - * All other settings are reserved and should not be used. - * Bit on [9, 6,2] - */ -#define DDRPHY_MR1_RTTM_MASK (0x40U) -#define DDRPHY_MR1_RTTM_SHIFT (6U) -#define DDRPHY_MR1_RTTM_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTM_SHIFT) & DDRPHY_MR1_RTTM_MASK) -#define DDRPHY_MR1_RTTM_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTM_MASK) >> DDRPHY_MR1_RTTM_SHIFT) - -/* - * DICH (R/W) - * - * Output Driver Impedance Control high bit: - * Controls the output drive strength. Valid values are: - * 00 = RZQ/6 - * 01 = RZQ7 - * 10 = Reserved - * 11 = Reserved - */ -#define DDRPHY_MR1_DICH_MASK (0x20U) -#define DDRPHY_MR1_DICH_SHIFT (5U) -#define DDRPHY_MR1_DICH_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DICH_SHIFT) & DDRPHY_MR1_DICH_MASK) -#define DDRPHY_MR1_DICH_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DICH_MASK) >> DDRPHY_MR1_DICH_SHIFT) - -/* - * AL (R/W) - * - * Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: - * 00 = 0 (AL disabled) - * 01 = CL - 1 - * 10 = CL - 2 - * 11 = Reserved - */ -#define DDRPHY_MR1_AL_MASK (0x18U) -#define DDRPHY_MR1_AL_SHIFT (3U) -#define DDRPHY_MR1_AL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_AL_SHIFT) & DDRPHY_MR1_AL_MASK) -#define DDRPHY_MR1_AL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_AL_MASK) >> DDRPHY_MR1_AL_SHIFT) - -/* - * RTTL (R/W) - * - * On Die Termination low bit - */ -#define DDRPHY_MR1_RTTL_MASK (0x4U) -#define DDRPHY_MR1_RTTL_SHIFT (2U) -#define DDRPHY_MR1_RTTL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_RTTL_SHIFT) & DDRPHY_MR1_RTTL_MASK) -#define DDRPHY_MR1_RTTL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_RTTL_MASK) >> DDRPHY_MR1_RTTL_SHIFT) - -/* - * DICL (R/W) - * - * Output Driver Impedance Control low bit - */ -#define DDRPHY_MR1_DICL_MASK (0x2U) -#define DDRPHY_MR1_DICL_SHIFT (1U) -#define DDRPHY_MR1_DICL_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DICL_SHIFT) & DDRPHY_MR1_DICL_MASK) -#define DDRPHY_MR1_DICL_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DICL_MASK) >> DDRPHY_MR1_DICL_SHIFT) - -/* - * DE (R/W) - * - * DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. - * Note: SDRAM DLL off mode is not supported - */ -#define DDRPHY_MR1_DE_MASK (0x1U) -#define DDRPHY_MR1_DE_SHIFT (0U) -#define DDRPHY_MR1_DE_SET(x) (((uint32_t)(x) << DDRPHY_MR1_DE_SHIFT) & DDRPHY_MR1_DE_MASK) -#define DDRPHY_MR1_DE_GET(x) (((uint32_t)(x) & DDRPHY_MR1_DE_MASK) >> DDRPHY_MR1_DE_SHIFT) - -/* Bitfield definition for register: EMR */ -/* - * QOFF (R/W) - * - * Output Enable/Disable: When ‘0’, all outputs function normal; when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be - * used for IDD characterization of read current and should not be used in normal operation. - */ -#define DDRPHY_EMR_QOFF_MASK (0x1000U) -#define DDRPHY_EMR_QOFF_SHIFT (12U) -#define DDRPHY_EMR_QOFF_SET(x) (((uint32_t)(x) << DDRPHY_EMR_QOFF_SHIFT) & DDRPHY_EMR_QOFF_MASK) -#define DDRPHY_EMR_QOFF_GET(x) (((uint32_t)(x) & DDRPHY_EMR_QOFF_MASK) >> DDRPHY_EMR_QOFF_SHIFT) - -/* - * RDQS (R/W) - * - * RDQS Enable/Disable: When enabled (‘1’), RDQS is identical in function and timing to data strobe DQS during a read, and ignored during a write. A ‘0’ disables the SDRAM from driving RDQS. The Controller does not allow the user to change this bit. - */ -#define DDRPHY_EMR_RDQS_MASK (0x800U) -#define DDRPHY_EMR_RDQS_SHIFT (11U) -#define DDRPHY_EMR_RDQS_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RDQS_SHIFT) & DDRPHY_EMR_RDQS_MASK) -#define DDRPHY_EMR_RDQS_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RDQS_MASK) >> DDRPHY_EMR_RDQS_SHIFT) - -/* - * DQS (R/W) - * - * DQS_b Enable/Disable: When ‘0’, DQS_b is the complement of the differential data strobe pair DQS/DQS_b. When ‘1’, DQS is used in a single-ended mode and the DQS_b pin is disabled. Also used to similarly enable/disable RDQS_b if RDQS is enabled. The Controller does not allow the user to change this bit. - */ -#define DDRPHY_EMR_DQS_MASK (0x400U) -#define DDRPHY_EMR_DQS_SHIFT (10U) -#define DDRPHY_EMR_DQS_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DQS_SHIFT) & DDRPHY_EMR_DQS_MASK) -#define DDRPHY_EMR_DQS_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DQS_MASK) >> DDRPHY_EMR_DQS_SHIFT) - -/* - * OCD (R/W) - * - * Off-Chip Driver (OCD) Impedance Calibration: Used to calibrate and match pull-up to pull- down impedance to 18  nominal (refer to the SDRAM datasheet for details). Valid values are: - * 000 = OCD calibration mode exit 001 = Drive (1) pull-up - * 010 = Drive (0) pull-down - * 100 = OCD enter adjust mode 111 = OCD calibration default - * All other settings are reserved and should not be used. Note that OCD is not supported by all vendors. Refer to the SDRAM datasheet for details on the recommended OCD settings. - */ -#define DDRPHY_EMR_OCD_MASK (0x380U) -#define DDRPHY_EMR_OCD_SHIFT (7U) -#define DDRPHY_EMR_OCD_SET(x) (((uint32_t)(x) << DDRPHY_EMR_OCD_SHIFT) & DDRPHY_EMR_OCD_MASK) -#define DDRPHY_EMR_OCD_GET(x) (((uint32_t)(x) & DDRPHY_EMR_OCD_MASK) >> DDRPHY_EMR_OCD_SHIFT) - -/* - * RTTH (R/W) - * - * On Die Termination high bit: - * Selects the effective resistance for SDRAM on die termination. Valid values are: - * 00 = ODT disabled 01 = 75 - * 10 = 150 - * 11 = 50 (some vendors) - */ -#define DDRPHY_EMR_RTTH_MASK (0x40U) -#define DDRPHY_EMR_RTTH_SHIFT (6U) -#define DDRPHY_EMR_RTTH_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RTTH_SHIFT) & DDRPHY_EMR_RTTH_MASK) -#define DDRPHY_EMR_RTTH_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RTTH_MASK) >> DDRPHY_EMR_RTTH_SHIFT) - -/* - * AL (R/W) - * - * Posted CAS Additive Latency: Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM datasheet for details). Valid values are: - * 000 = 0 - * 001 = 1 - * 010 = 2 - * 011 = 3 - * 100 = 4 - * 101 = 5 - * All other settings are reserved and should not be used. The maximum allowed value of AL is tRCD-1. - */ -#define DDRPHY_EMR_AL_MASK (0x38U) -#define DDRPHY_EMR_AL_SHIFT (3U) -#define DDRPHY_EMR_AL_SET(x) (((uint32_t)(x) << DDRPHY_EMR_AL_SHIFT) & DDRPHY_EMR_AL_MASK) -#define DDRPHY_EMR_AL_GET(x) (((uint32_t)(x) & DDRPHY_EMR_AL_MASK) >> DDRPHY_EMR_AL_SHIFT) - -/* - * RTTL (R/W) - * - * On Die Termination low bit: - */ -#define DDRPHY_EMR_RTTL_MASK (0x4U) -#define DDRPHY_EMR_RTTL_SHIFT (2U) -#define DDRPHY_EMR_RTTL_SET(x) (((uint32_t)(x) << DDRPHY_EMR_RTTL_SHIFT) & DDRPHY_EMR_RTTL_MASK) -#define DDRPHY_EMR_RTTL_GET(x) (((uint32_t)(x) & DDRPHY_EMR_RTTL_MASK) >> DDRPHY_EMR_RTTL_SHIFT) - -/* - * DIC (R/W) - * - * Output Driver Impedance Control: Controls the output drive strength. Valid values are: - * 0 = Full strength - * 1 = Reduced strength - */ -#define DDRPHY_EMR_DIC_MASK (0x2U) -#define DDRPHY_EMR_DIC_SHIFT (1U) -#define DDRPHY_EMR_DIC_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DIC_SHIFT) & DDRPHY_EMR_DIC_MASK) -#define DDRPHY_EMR_DIC_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DIC_MASK) >> DDRPHY_EMR_DIC_SHIFT) - -/* - * DE (R/W) - * - * DLL Enable/Disable: Enable (0) or disable (1) the DLL. DLL must be enabled for normal operation. - */ -#define DDRPHY_EMR_DE_MASK (0x1U) -#define DDRPHY_EMR_DE_SHIFT (0U) -#define DDRPHY_EMR_DE_SET(x) (((uint32_t)(x) << DDRPHY_EMR_DE_SHIFT) & DDRPHY_EMR_DE_MASK) -#define DDRPHY_EMR_DE_GET(x) (((uint32_t)(x) & DDRPHY_EMR_DE_MASK) >> DDRPHY_EMR_DE_SHIFT) - -/* Bitfield definition for register: MR2 */ -/* - * RTTWR (R/W) - * - * Dynamic ODT: Selects RTT for dynamic ODT. Valid values are: 00 = Dynamic ODT off - * 01 = RZQ/4 - * 10 = RZQ/2 - * 11 = Reserved - */ -#define DDRPHY_MR2_RTTWR_MASK (0x600U) -#define DDRPHY_MR2_RTTWR_SHIFT (9U) -#define DDRPHY_MR2_RTTWR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_RTTWR_SHIFT) & DDRPHY_MR2_RTTWR_MASK) -#define DDRPHY_MR2_RTTWR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_RTTWR_MASK) >> DDRPHY_MR2_RTTWR_SHIFT) - -/* - * SRT (R/W) - * - * Self-Refresh Temperature Range: Selects either normal (‘0’) or extended (‘1’) operating temperature range during self-refresh. - */ -#define DDRPHY_MR2_SRT_MASK (0x80U) -#define DDRPHY_MR2_SRT_SHIFT (7U) -#define DDRPHY_MR2_SRT_SET(x) (((uint32_t)(x) << DDRPHY_MR2_SRT_SHIFT) & DDRPHY_MR2_SRT_MASK) -#define DDRPHY_MR2_SRT_GET(x) (((uint32_t)(x) & DDRPHY_MR2_SRT_MASK) >> DDRPHY_MR2_SRT_SHIFT) - -/* - * ASR (R/W) - * - * Auto Self-Refresh: When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. - * Otherwise the SRT bit must be programmed to indicate the temperature range. - */ -#define DDRPHY_MR2_ASR_MASK (0x40U) -#define DDRPHY_MR2_ASR_SHIFT (6U) -#define DDRPHY_MR2_ASR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_ASR_SHIFT) & DDRPHY_MR2_ASR_MASK) -#define DDRPHY_MR2_ASR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_ASR_MASK) >> DDRPHY_MR2_ASR_SHIFT) - -/* - * CWL (R/W) - * - * CAS Write Latency: The delay between when the SDRAM registers a write command to when write data is available. Valid values are: - * 000 = 5 (tCK > 2.5ns) - * 001 = 6 (2.5ns > tCK > 1.875ns) - * 010 = 7 (1.875ns > tCK> 1.5ns) - * 011 = 8 (1.5ns > tCK > 1.25ns) - * 100 = 9 (1.25ns > tCK > 1.07ns) - * 101 = 10 (1.07ns > tCK > 0.935ns) - * 110 = 11 (0.935ns > tCK > 0.833ns) - * 111 = 12 (0.833ns > tCK > 0.75ns) - * All other settings are reserved and should not be used. - */ -#define DDRPHY_MR2_CWL_MASK (0x38U) -#define DDRPHY_MR2_CWL_SHIFT (3U) -#define DDRPHY_MR2_CWL_SET(x) (((uint32_t)(x) << DDRPHY_MR2_CWL_SHIFT) & DDRPHY_MR2_CWL_MASK) -#define DDRPHY_MR2_CWL_GET(x) (((uint32_t)(x) & DDRPHY_MR2_CWL_MASK) >> DDRPHY_MR2_CWL_SHIFT) - -/* - * PASR (R/W) - * - * Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. - * Valid settings for 4 banks are: - * 000 = Full Array - * 001 = Half Array (BA[1:0] = 00 & 01) - * 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined - * 100 = 3/4 Array (BA[1:0] = 01, 10, & 11) - * 101 = Half Array (BA[1:0] = 10 & 11) - * 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined - * Valid settings for 8 banks are: - * 000 = Full Array - * 001 = Half Array (BA[2:0] = 000, 001, 010 & 011) - * 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) - * 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) - * 101 = Half Array (BA[2:0] = 100, 101, 110 & 111) - * 110 = Quarter Array (BA[2:0] = 110 & 111) - * 111 = 1/8 Array (BA[2:0] 111) - */ -#define DDRPHY_MR2_PASR_MASK (0x7U) -#define DDRPHY_MR2_PASR_SHIFT (0U) -#define DDRPHY_MR2_PASR_SET(x) (((uint32_t)(x) << DDRPHY_MR2_PASR_SHIFT) & DDRPHY_MR2_PASR_MASK) -#define DDRPHY_MR2_PASR_GET(x) (((uint32_t)(x) & DDRPHY_MR2_PASR_MASK) >> DDRPHY_MR2_PASR_SHIFT) - -/* Bitfield definition for register: EMR2 */ -/* - * SRF (R/W) - * - * Self Refresh Rate: Enables, if set, high temperature self refresh rate. - */ -#define DDRPHY_EMR2_SRF_MASK (0x80U) -#define DDRPHY_EMR2_SRF_SHIFT (7U) -#define DDRPHY_EMR2_SRF_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_SRF_SHIFT) & DDRPHY_EMR2_SRF_MASK) -#define DDRPHY_EMR2_SRF_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_SRF_MASK) >> DDRPHY_EMR2_SRF_SHIFT) - -/* - * DCC (R/W) - * - * Duty Cycle Corrector: Enables, if set, duty cycle correction within SDRAM. - */ -#define DDRPHY_EMR2_DCC_MASK (0x8U) -#define DDRPHY_EMR2_DCC_SHIFT (3U) -#define DDRPHY_EMR2_DCC_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_DCC_SHIFT) & DDRPHY_EMR2_DCC_MASK) -#define DDRPHY_EMR2_DCC_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_DCC_MASK) >> DDRPHY_EMR2_DCC_SHIFT) - -/* - * PASR (R/W) - * - * Partial Array Self Refresh: Specifies that data located in areas of the array beyond the specified location will be lost if self refresh is entered. - * Valid settings for 4 banks are: - * 000 = Full Array - * 001 = Half Array (BA[1:0] = 00 & 01) - * 010 = Quarter Array (BA[1:0] = 00) 011 = Not defined - * 100 = 3/4 Array (BA[1:0] = 01, 10, & 11) - * 101 = Half Array (BA[1:0] = 10 & 11) - * 110 = Quarter Array (BA[1:0] = 11) 111 = Not defined - * Valid settings for 8 banks are: - * 000 = Full Array - * 001 = Half Array (BA[2:0] = 000, 001, 010 & 011) - * 010 = Quarter Array (BA[2:0] = 000, 001) 011 = 1/8 Array (BA[2:0] = 000) - * 100 = 3/4 Array (BA[2:0] = 010, 011, 100, 101, 110 & 111) - * 101 = Half Array (BA[2:0] = 100, 101, 110 & 111) - * 110 = Quarter Array (BA[2:0] = 110 & 111) - * 111 = 1/8 Array (BA[2:0] 111) - */ -#define DDRPHY_EMR2_PASR_MASK (0x7U) -#define DDRPHY_EMR2_PASR_SHIFT (0U) -#define DDRPHY_EMR2_PASR_SET(x) (((uint32_t)(x) << DDRPHY_EMR2_PASR_SHIFT) & DDRPHY_EMR2_PASR_MASK) -#define DDRPHY_EMR2_PASR_GET(x) (((uint32_t)(x) & DDRPHY_EMR2_PASR_MASK) >> DDRPHY_EMR2_PASR_SHIFT) - -/* Bitfield definition for register: MR3 */ -/* - * MPR (R/W) - * - * Multi-Purpose Register Enable: Enables, if set, that read data should come from the Multi-Purpose Register. Otherwise read data come from the DRAM array. - */ -#define DDRPHY_MR3_MPR_MASK (0x4U) -#define DDRPHY_MR3_MPR_SHIFT (2U) -#define DDRPHY_MR3_MPR_SET(x) (((uint32_t)(x) << DDRPHY_MR3_MPR_SHIFT) & DDRPHY_MR3_MPR_MASK) -#define DDRPHY_MR3_MPR_GET(x) (((uint32_t)(x) & DDRPHY_MR3_MPR_MASK) >> DDRPHY_MR3_MPR_SHIFT) - -/* - * MPRLOC (R/W) - * - * Multi-Purpose Register (MPR) Location: Selects MPR data location: Valid value are: 00 = Predefined pattern for system calibration - * All other settings are reserved and should not be used. - */ -#define DDRPHY_MR3_MPRLOC_MASK (0x3U) -#define DDRPHY_MR3_MPRLOC_SHIFT (0U) -#define DDRPHY_MR3_MPRLOC_SET(x) (((uint32_t)(x) << DDRPHY_MR3_MPRLOC_SHIFT) & DDRPHY_MR3_MPRLOC_MASK) -#define DDRPHY_MR3_MPRLOC_GET(x) (((uint32_t)(x) & DDRPHY_MR3_MPRLOC_MASK) >> DDRPHY_MR3_MPRLOC_SHIFT) - -/* Bitfield definition for register: EMR3 */ -/* Bitfield definition for register: ODTCR */ -/* - * WRODT3 (R/W) - * - */ -#define DDRPHY_ODTCR_WRODT3_MASK (0xF0000000UL) -#define DDRPHY_ODTCR_WRODT3_SHIFT (28U) -#define DDRPHY_ODTCR_WRODT3_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT3_SHIFT) & DDRPHY_ODTCR_WRODT3_MASK) -#define DDRPHY_ODTCR_WRODT3_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT3_MASK) >> DDRPHY_ODTCR_WRODT3_SHIFT) - -/* - * WRODT2 (R/W) - * - */ -#define DDRPHY_ODTCR_WRODT2_MASK (0xF000000UL) -#define DDRPHY_ODTCR_WRODT2_SHIFT (24U) -#define DDRPHY_ODTCR_WRODT2_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT2_SHIFT) & DDRPHY_ODTCR_WRODT2_MASK) -#define DDRPHY_ODTCR_WRODT2_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT2_MASK) >> DDRPHY_ODTCR_WRODT2_SHIFT) - -/* - * WRODT1 (R/W) - * - */ -#define DDRPHY_ODTCR_WRODT1_MASK (0xF00000UL) -#define DDRPHY_ODTCR_WRODT1_SHIFT (20U) -#define DDRPHY_ODTCR_WRODT1_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT1_SHIFT) & DDRPHY_ODTCR_WRODT1_MASK) -#define DDRPHY_ODTCR_WRODT1_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT1_MASK) >> DDRPHY_ODTCR_WRODT1_SHIFT) - -/* - * WRODT0 (R/W) - * - * Write ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a write command is sent to rank n. WRODT0, WRODT1, WRODT2, and WRODT3 specify ODT settings when a write is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to enable ODT only on rank being written to. - */ -#define DDRPHY_ODTCR_WRODT0_MASK (0xF0000UL) -#define DDRPHY_ODTCR_WRODT0_SHIFT (16U) -#define DDRPHY_ODTCR_WRODT0_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_WRODT0_SHIFT) & DDRPHY_ODTCR_WRODT0_MASK) -#define DDRPHY_ODTCR_WRODT0_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_WRODT0_MASK) >> DDRPHY_ODTCR_WRODT0_SHIFT) - -/* - * RDODT3 (R/W) - * - */ -#define DDRPHY_ODTCR_RDODT3_MASK (0xF000U) -#define DDRPHY_ODTCR_RDODT3_SHIFT (12U) -#define DDRPHY_ODTCR_RDODT3_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT3_SHIFT) & DDRPHY_ODTCR_RDODT3_MASK) -#define DDRPHY_ODTCR_RDODT3_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT3_MASK) >> DDRPHY_ODTCR_RDODT3_SHIFT) - -/* - * RDODT2 (R/W) - * - */ -#define DDRPHY_ODTCR_RDODT2_MASK (0xF00U) -#define DDRPHY_ODTCR_RDODT2_SHIFT (8U) -#define DDRPHY_ODTCR_RDODT2_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT2_SHIFT) & DDRPHY_ODTCR_RDODT2_MASK) -#define DDRPHY_ODTCR_RDODT2_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT2_MASK) >> DDRPHY_ODTCR_RDODT2_SHIFT) - -/* - * RDODT1 (R/W) - * - */ -#define DDRPHY_ODTCR_RDODT1_MASK (0xF0U) -#define DDRPHY_ODTCR_RDODT1_SHIFT (4U) -#define DDRPHY_ODTCR_RDODT1_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT1_SHIFT) & DDRPHY_ODTCR_RDODT1_MASK) -#define DDRPHY_ODTCR_RDODT1_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT1_MASK) >> DDRPHY_ODTCR_RDODT1_SHIFT) - -/* - * RDODT0 (R/W) - * - * Read ODT: Specifies whether ODT should be enabled (‘1’) or disabled (‘0’) on each of the up to four ranks when a read command is sent to rank n. RDODT0, RDODT1, RDODT2, and RDODT3 specify ODT settings when a read is to rank 0, rank 1, rank 2, and rank 3, respectively. The four bits of each field each represent a rank, the LSB being rank 0 and the MSB being rank 3. Default is to disable ODT during reads. - */ -#define DDRPHY_ODTCR_RDODT0_MASK (0xFU) -#define DDRPHY_ODTCR_RDODT0_SHIFT (0U) -#define DDRPHY_ODTCR_RDODT0_SET(x) (((uint32_t)(x) << DDRPHY_ODTCR_RDODT0_SHIFT) & DDRPHY_ODTCR_RDODT0_MASK) -#define DDRPHY_ODTCR_RDODT0_GET(x) (((uint32_t)(x) & DDRPHY_ODTCR_RDODT0_MASK) >> DDRPHY_ODTCR_RDODT0_SHIFT) - -/* Bitfield definition for register: DTCR */ -/* - * RFSHDT (R/W) - * - * Refresh During Training: A non-zero value specifies that a burst of refreshes equal to the number specified in this field should be sent to the SDRAM after training each rank except the last rank. - */ -#define DDRPHY_DTCR_RFSHDT_MASK (0xF0000000UL) -#define DDRPHY_DTCR_RFSHDT_SHIFT (28U) -#define DDRPHY_DTCR_RFSHDT_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_RFSHDT_SHIFT) & DDRPHY_DTCR_RFSHDT_MASK) -#define DDRPHY_DTCR_RFSHDT_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_RFSHDT_MASK) >> DDRPHY_DTCR_RFSHDT_SHIFT) - -/* - * RANKEN (R/W) - * - * Rank Enable: Specifies the ranks that are enabled for data-training. Bit 0 controls rank 0, bit 1 controls rank 1, bit 2 controls rank 2, and bit 3 controls rank 3. Setting the bit to ‘1’ enables the rank, and setting it to ‘0’ disables the rank. - */ -#define DDRPHY_DTCR_RANKEN_MASK (0xF000000UL) -#define DDRPHY_DTCR_RANKEN_SHIFT (24U) -#define DDRPHY_DTCR_RANKEN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_RANKEN_SHIFT) & DDRPHY_DTCR_RANKEN_MASK) -#define DDRPHY_DTCR_RANKEN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_RANKEN_MASK) >> DDRPHY_DTCR_RANKEN_SHIFT) - -/* - * DTEXD (R/W) - * - * Data Training Extended Write DQS: Enables, if set, an extended write DQS whereby two additional pulses of DQS are added as post-amble to a burst of writes. - * Generally this should only be enabled when running read bit deskew with the intention of performing read eye deskew prior to running write leveling adjustment. - */ -#define DDRPHY_DTCR_DTEXD_MASK (0x400000UL) -#define DDRPHY_DTCR_DTEXD_SHIFT (22U) -#define DDRPHY_DTCR_DTEXD_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTEXD_SHIFT) & DDRPHY_DTCR_DTEXD_MASK) -#define DDRPHY_DTCR_DTEXD_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTEXD_MASK) >> DDRPHY_DTCR_DTEXD_SHIFT) - -/* - * DTDSTP (R/W) - * - * Data Training Debug Step: A write of 1 to this bit steps the data training algorithm through a single step. This bit is used to initiate one step of the data training algorithm in question. - * This bit is self-clearing. To trigger the next step, this bit must be written to again. Note: The training steps must be repeated in order to get new data in the “Data Training Eye Data Register 0-1 (DTEDR0-1)” on page 122. For example, to see the - * training results for a different lane, select that lane and repeat the training steps to - * populate DTEDR0 and DTEDR1 with the correct data. - */ -#define DDRPHY_DTCR_DTDSTP_MASK (0x200000UL) -#define DDRPHY_DTCR_DTDSTP_SHIFT (21U) -#define DDRPHY_DTCR_DTDSTP_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDSTP_SHIFT) & DDRPHY_DTCR_DTDSTP_MASK) -#define DDRPHY_DTCR_DTDSTP_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDSTP_MASK) >> DDRPHY_DTCR_DTDSTP_SHIFT) - -/* - * DTDEN (R/W) - * - * Data Training Debug Enable: Enables, if set, the data training single step debug mode. - */ -#define DDRPHY_DTCR_DTDEN_MASK (0x100000UL) -#define DDRPHY_DTCR_DTDEN_SHIFT (20U) -#define DDRPHY_DTCR_DTDEN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDEN_SHIFT) & DDRPHY_DTCR_DTDEN_MASK) -#define DDRPHY_DTCR_DTDEN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDEN_MASK) >> DDRPHY_DTCR_DTDEN_SHIFT) - -/* - * DTDBS (R/W) - * - * Data Training Debug Byte Select: Selects the byte during data training single step debug mode. - * Note: DTDEN is not used to enable this feature. - */ -#define DDRPHY_DTCR_DTDBS_MASK (0xF0000UL) -#define DDRPHY_DTCR_DTDBS_SHIFT (16U) -#define DDRPHY_DTCR_DTDBS_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTDBS_SHIFT) & DDRPHY_DTCR_DTDBS_MASK) -#define DDRPHY_DTCR_DTDBS_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTDBS_MASK) >> DDRPHY_DTCR_DTDBS_SHIFT) - -/* - * DTWDQMO (R/W) - * - * Data Training WDQ Margin Override: If set, the Training WDQ Margin value specified in DTCR[11:8] (DTWDQM) is used during data training. Otherwise the value is computed as ¼ of the ddr_clk period measurement found during calibration of the WDQ LCDL. - */ -#define DDRPHY_DTCR_DTWDQMO_MASK (0x4000U) -#define DDRPHY_DTCR_DTWDQMO_SHIFT (14U) -#define DDRPHY_DTCR_DTWDQMO_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWDQMO_SHIFT) & DDRPHY_DTCR_DTWDQMO_MASK) -#define DDRPHY_DTCR_DTWDQMO_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWDQMO_MASK) >> DDRPHY_DTCR_DTWDQMO_SHIFT) - -/* - * DTBDC (R/W) - * - * Data Training Bit Deskew Centering: Enables, if set, eye centering capability during write and read bit deskew training. - */ -#define DDRPHY_DTCR_DTBDC_MASK (0x2000U) -#define DDRPHY_DTCR_DTBDC_SHIFT (13U) -#define DDRPHY_DTCR_DTBDC_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTBDC_SHIFT) & DDRPHY_DTCR_DTBDC_MASK) -#define DDRPHY_DTCR_DTBDC_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTBDC_MASK) >> DDRPHY_DTCR_DTBDC_SHIFT) - -/* - * DTWBDDM (R/W) - * - * Data Training Write Bit Deskew Data Mask, if set, it enables write bit deskew of the data mask - */ -#define DDRPHY_DTCR_DTWBDDM_MASK (0x1000U) -#define DDRPHY_DTCR_DTWBDDM_SHIFT (12U) -#define DDRPHY_DTCR_DTWBDDM_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWBDDM_SHIFT) & DDRPHY_DTCR_DTWBDDM_MASK) -#define DDRPHY_DTCR_DTWBDDM_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWBDDM_MASK) >> DDRPHY_DTCR_DTWBDDM_SHIFT) - -/* - * DTWDQM (R/W) - * - * Training WDQ Margin: Defines how close to 0 or how close to 2*(wdq calibration_value) the WDQ LCDL can be moved during training. Basically defines how much timing margin. - */ -#define DDRPHY_DTCR_DTWDQM_MASK (0xF00U) -#define DDRPHY_DTCR_DTWDQM_SHIFT (8U) -#define DDRPHY_DTCR_DTWDQM_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTWDQM_SHIFT) & DDRPHY_DTCR_DTWDQM_MASK) -#define DDRPHY_DTCR_DTWDQM_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTWDQM_MASK) >> DDRPHY_DTCR_DTWDQM_SHIFT) - -/* - * DTCMPD (R/W) - * - * Read Data Training Compare Data: Specifies, if set, that DQS gate training should also check if the returning read data is correct. Otherwise data-training only checks if the correct number of DQS edges were returned. - */ -#define DDRPHY_DTCR_DTCMPD_MASK (0x80U) -#define DDRPHY_DTCR_DTCMPD_SHIFT (7U) -#define DDRPHY_DTCR_DTCMPD_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTCMPD_SHIFT) & DDRPHY_DTCR_DTCMPD_MASK) -#define DDRPHY_DTCR_DTCMPD_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTCMPD_MASK) >> DDRPHY_DTCR_DTCMPD_SHIFT) - -/* - * DTMPR (R/W) - * - * Read Data Training Using MPR (DDR3 Only): Specifies, if set, that DQS gate training should use the SDRAM Multi-Purpose Register (MPR) register. Otherwise data-training is performed by first writing to some locations in the SDRAM and then reading them back. - */ -#define DDRPHY_DTCR_DTMPR_MASK (0x40U) -#define DDRPHY_DTCR_DTMPR_SHIFT (6U) -#define DDRPHY_DTCR_DTMPR_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTMPR_SHIFT) & DDRPHY_DTCR_DTMPR_MASK) -#define DDRPHY_DTCR_DTMPR_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTMPR_MASK) >> DDRPHY_DTCR_DTMPR_SHIFT) - -/* - * DTRANK (R/W) - * - * Data Training Rank: Select the SDRAM rank to be used during Read DQS gate training, Read/Write Data Bit Deskew, Read/Write Eye Training. - */ -#define DDRPHY_DTCR_DTRANK_MASK (0x30U) -#define DDRPHY_DTCR_DTRANK_SHIFT (4U) -#define DDRPHY_DTCR_DTRANK_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTRANK_SHIFT) & DDRPHY_DTCR_DTRANK_MASK) -#define DDRPHY_DTCR_DTRANK_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTRANK_MASK) >> DDRPHY_DTCR_DTRANK_SHIFT) - -/* - * DTRPTN (R/W) - * - * Data Training Repeat Number: Repeat number used to confirm stability of DDR write or read. - * Note: The minimum value should be 0x4 and the maximum value should be 0x14. - */ -#define DDRPHY_DTCR_DTRPTN_MASK (0xFU) -#define DDRPHY_DTCR_DTRPTN_SHIFT (0U) -#define DDRPHY_DTCR_DTRPTN_SET(x) (((uint32_t)(x) << DDRPHY_DTCR_DTRPTN_SHIFT) & DDRPHY_DTCR_DTRPTN_MASK) -#define DDRPHY_DTCR_DTRPTN_GET(x) (((uint32_t)(x) & DDRPHY_DTCR_DTRPTN_MASK) >> DDRPHY_DTCR_DTRPTN_SHIFT) - -/* Bitfield definition for register: DTAR0 */ -/* - * DTBANK (R/W) - * - * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - */ -#define DDRPHY_DTAR0_DTBANK_MASK (0x70000000UL) -#define DDRPHY_DTAR0_DTBANK_SHIFT (28U) -#define DDRPHY_DTAR0_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTBANK_SHIFT) & DDRPHY_DTAR0_DTBANK_MASK) -#define DDRPHY_DTAR0_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTBANK_MASK) >> DDRPHY_DTAR0_DTBANK_SHIFT) - -/* - * DTROW (R/W) - * - * Data Training Row Address: Selects the SDRAM row address to be used during data training. - */ -#define DDRPHY_DTAR0_DTROW_MASK (0xFFFF000UL) -#define DDRPHY_DTAR0_DTROW_SHIFT (12U) -#define DDRPHY_DTAR0_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTROW_SHIFT) & DDRPHY_DTAR0_DTROW_MASK) -#define DDRPHY_DTAR0_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTROW_MASK) >> DDRPHY_DTAR0_DTROW_SHIFT) - -/* - * DTCOL (R/W) - * - * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - */ -#define DDRPHY_DTAR0_DTCOL_MASK (0xFFFU) -#define DDRPHY_DTAR0_DTCOL_SHIFT (0U) -#define DDRPHY_DTAR0_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR0_DTCOL_SHIFT) & DDRPHY_DTAR0_DTCOL_MASK) -#define DDRPHY_DTAR0_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR0_DTCOL_MASK) >> DDRPHY_DTAR0_DTCOL_SHIFT) - -/* Bitfield definition for register: DTAR1 */ -/* - * DTBANK (R/W) - * - * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - */ -#define DDRPHY_DTAR1_DTBANK_MASK (0x70000000UL) -#define DDRPHY_DTAR1_DTBANK_SHIFT (28U) -#define DDRPHY_DTAR1_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTBANK_SHIFT) & DDRPHY_DTAR1_DTBANK_MASK) -#define DDRPHY_DTAR1_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTBANK_MASK) >> DDRPHY_DTAR1_DTBANK_SHIFT) - -/* - * DTROW (R/W) - * - * Data Training Row Address: Selects the SDRAM row address to be used during data training. - */ -#define DDRPHY_DTAR1_DTROW_MASK (0xFFFF000UL) -#define DDRPHY_DTAR1_DTROW_SHIFT (12U) -#define DDRPHY_DTAR1_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTROW_SHIFT) & DDRPHY_DTAR1_DTROW_MASK) -#define DDRPHY_DTAR1_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTROW_MASK) >> DDRPHY_DTAR1_DTROW_SHIFT) - -/* - * DTCOL (R/W) - * - * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - */ -#define DDRPHY_DTAR1_DTCOL_MASK (0xFFFU) -#define DDRPHY_DTAR1_DTCOL_SHIFT (0U) -#define DDRPHY_DTAR1_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR1_DTCOL_SHIFT) & DDRPHY_DTAR1_DTCOL_MASK) -#define DDRPHY_DTAR1_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR1_DTCOL_MASK) >> DDRPHY_DTAR1_DTCOL_SHIFT) - -/* Bitfield definition for register: DTAR2 */ -/* - * DTBANK (R/W) - * - * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - */ -#define DDRPHY_DTAR2_DTBANK_MASK (0x70000000UL) -#define DDRPHY_DTAR2_DTBANK_SHIFT (28U) -#define DDRPHY_DTAR2_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTBANK_SHIFT) & DDRPHY_DTAR2_DTBANK_MASK) -#define DDRPHY_DTAR2_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTBANK_MASK) >> DDRPHY_DTAR2_DTBANK_SHIFT) - -/* - * DTROW (R/W) - * - * Data Training Row Address: Selects the SDRAM row address to be used during data training. - */ -#define DDRPHY_DTAR2_DTROW_MASK (0xFFFF000UL) -#define DDRPHY_DTAR2_DTROW_SHIFT (12U) -#define DDRPHY_DTAR2_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTROW_SHIFT) & DDRPHY_DTAR2_DTROW_MASK) -#define DDRPHY_DTAR2_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTROW_MASK) >> DDRPHY_DTAR2_DTROW_SHIFT) - -/* - * DTCOL (R/W) - * - * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - */ -#define DDRPHY_DTAR2_DTCOL_MASK (0xFFFU) -#define DDRPHY_DTAR2_DTCOL_SHIFT (0U) -#define DDRPHY_DTAR2_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR2_DTCOL_SHIFT) & DDRPHY_DTAR2_DTCOL_MASK) -#define DDRPHY_DTAR2_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR2_DTCOL_MASK) >> DDRPHY_DTAR2_DTCOL_SHIFT) - -/* Bitfield definition for register: DTAR3 */ -/* - * DTBANK (R/W) - * - * Data Training Bank Address: Selects the SDRAM bank address to be used during data training. - */ -#define DDRPHY_DTAR3_DTBANK_MASK (0x70000000UL) -#define DDRPHY_DTAR3_DTBANK_SHIFT (28U) -#define DDRPHY_DTAR3_DTBANK_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTBANK_SHIFT) & DDRPHY_DTAR3_DTBANK_MASK) -#define DDRPHY_DTAR3_DTBANK_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTBANK_MASK) >> DDRPHY_DTAR3_DTBANK_SHIFT) - -/* - * DTROW (R/W) - * - * Data Training Row Address: Selects the SDRAM row address to be used during data training. - */ -#define DDRPHY_DTAR3_DTROW_MASK (0xFFFF000UL) -#define DDRPHY_DTAR3_DTROW_SHIFT (12U) -#define DDRPHY_DTAR3_DTROW_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTROW_SHIFT) & DDRPHY_DTAR3_DTROW_MASK) -#define DDRPHY_DTAR3_DTROW_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTROW_MASK) >> DDRPHY_DTAR3_DTROW_SHIFT) - -/* - * DTCOL (R/W) - * - * Data Training Column Address: Selects the SDRAM column address to be used during data training. The lower four bits of this address must always be “000”. - */ -#define DDRPHY_DTAR3_DTCOL_MASK (0xFFFU) -#define DDRPHY_DTAR3_DTCOL_SHIFT (0U) -#define DDRPHY_DTAR3_DTCOL_SET(x) (((uint32_t)(x) << DDRPHY_DTAR3_DTCOL_SHIFT) & DDRPHY_DTAR3_DTCOL_MASK) -#define DDRPHY_DTAR3_DTCOL_GET(x) (((uint32_t)(x) & DDRPHY_DTAR3_DTCOL_MASK) >> DDRPHY_DTAR3_DTCOL_SHIFT) - -/* Bitfield definition for register: DTDR0 */ -/* - * DTBYTE3 (R/W) - * - */ -#define DDRPHY_DTDR0_DTBYTE3_MASK (0xFF000000UL) -#define DDRPHY_DTDR0_DTBYTE3_SHIFT (24U) -#define DDRPHY_DTDR0_DTBYTE3_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE3_SHIFT) & DDRPHY_DTDR0_DTBYTE3_MASK) -#define DDRPHY_DTDR0_DTBYTE3_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE3_MASK) >> DDRPHY_DTDR0_DTBYTE3_SHIFT) - -/* - * DTBYTE2 (R/W) - * - */ -#define DDRPHY_DTDR0_DTBYTE2_MASK (0xFF0000UL) -#define DDRPHY_DTDR0_DTBYTE2_SHIFT (16U) -#define DDRPHY_DTDR0_DTBYTE2_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE2_SHIFT) & DDRPHY_DTDR0_DTBYTE2_MASK) -#define DDRPHY_DTDR0_DTBYTE2_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE2_MASK) >> DDRPHY_DTDR0_DTBYTE2_SHIFT) - -/* - * DTBYTE1 (R/W) - * - */ -#define DDRPHY_DTDR0_DTBYTE1_MASK (0xFF00U) -#define DDRPHY_DTDR0_DTBYTE1_SHIFT (8U) -#define DDRPHY_DTDR0_DTBYTE1_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE1_SHIFT) & DDRPHY_DTDR0_DTBYTE1_MASK) -#define DDRPHY_DTDR0_DTBYTE1_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE1_MASK) >> DDRPHY_DTDR0_DTBYTE1_SHIFT) - -/* - * DTBYTE0 (R/W) - * - * Data Training Data: The first 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. - */ -#define DDRPHY_DTDR0_DTBYTE0_MASK (0xFFU) -#define DDRPHY_DTDR0_DTBYTE0_SHIFT (0U) -#define DDRPHY_DTDR0_DTBYTE0_SET(x) (((uint32_t)(x) << DDRPHY_DTDR0_DTBYTE0_SHIFT) & DDRPHY_DTDR0_DTBYTE0_MASK) -#define DDRPHY_DTDR0_DTBYTE0_GET(x) (((uint32_t)(x) & DDRPHY_DTDR0_DTBYTE0_MASK) >> DDRPHY_DTDR0_DTBYTE0_SHIFT) - -/* Bitfield definition for register: DTDR1 */ -/* - * DTBYTE7 (R/W) - * - */ -#define DDRPHY_DTDR1_DTBYTE7_MASK (0xFF000000UL) -#define DDRPHY_DTDR1_DTBYTE7_SHIFT (24U) -#define DDRPHY_DTDR1_DTBYTE7_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE7_SHIFT) & DDRPHY_DTDR1_DTBYTE7_MASK) -#define DDRPHY_DTDR1_DTBYTE7_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE7_MASK) >> DDRPHY_DTDR1_DTBYTE7_SHIFT) - -/* - * DTBYTE6 (R/W) - * - */ -#define DDRPHY_DTDR1_DTBYTE6_MASK (0xFF0000UL) -#define DDRPHY_DTDR1_DTBYTE6_SHIFT (16U) -#define DDRPHY_DTDR1_DTBYTE6_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE6_SHIFT) & DDRPHY_DTDR1_DTBYTE6_MASK) -#define DDRPHY_DTDR1_DTBYTE6_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE6_MASK) >> DDRPHY_DTDR1_DTBYTE6_SHIFT) - -/* - * DTBYTE5 (R/W) - * - */ -#define DDRPHY_DTDR1_DTBYTE5_MASK (0xFF00U) -#define DDRPHY_DTDR1_DTBYTE5_SHIFT (8U) -#define DDRPHY_DTDR1_DTBYTE5_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE5_SHIFT) & DDRPHY_DTDR1_DTBYTE5_MASK) -#define DDRPHY_DTDR1_DTBYTE5_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE5_MASK) >> DDRPHY_DTDR1_DTBYTE5_SHIFT) - -/* - * DTBYTE4 (R/W) - * - * Data Training Data: The second 4 bytes of data used during data training. This same data byte is used for each Byte Lane. Default sequence is a walking 1 while toggling data every data cycle. - */ -#define DDRPHY_DTDR1_DTBYTE4_MASK (0xFFU) -#define DDRPHY_DTDR1_DTBYTE4_SHIFT (0U) -#define DDRPHY_DTDR1_DTBYTE4_SET(x) (((uint32_t)(x) << DDRPHY_DTDR1_DTBYTE4_SHIFT) & DDRPHY_DTDR1_DTBYTE4_MASK) -#define DDRPHY_DTDR1_DTBYTE4_GET(x) (((uint32_t)(x) & DDRPHY_DTDR1_DTBYTE4_MASK) >> DDRPHY_DTDR1_DTBYTE4_SHIFT) - -/* Bitfield definition for register: DTEDR0 */ -/* - * DTWBMX (R) - * - * Data Training Write BDL Shift Maximum. - */ -#define DDRPHY_DTEDR0_DTWBMX_MASK (0xFF000000UL) -#define DDRPHY_DTEDR0_DTWBMX_SHIFT (24U) -#define DDRPHY_DTEDR0_DTWBMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWBMX_MASK) >> DDRPHY_DTEDR0_DTWBMX_SHIFT) - -/* - * DTWBMN (R) - * - * Data Training Write BDL Shift Minimum. - */ -#define DDRPHY_DTEDR0_DTWBMN_MASK (0xFF0000UL) -#define DDRPHY_DTEDR0_DTWBMN_SHIFT (16U) -#define DDRPHY_DTEDR0_DTWBMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWBMN_MASK) >> DDRPHY_DTEDR0_DTWBMN_SHIFT) - -/* - * DTWLMX (R) - * - * Data Training WDQ LCDL Maximum. - */ -#define DDRPHY_DTEDR0_DTWLMX_MASK (0xFF00U) -#define DDRPHY_DTEDR0_DTWLMX_SHIFT (8U) -#define DDRPHY_DTEDR0_DTWLMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWLMX_MASK) >> DDRPHY_DTEDR0_DTWLMX_SHIFT) - -/* - * DTWLMN (R) - * - * Data Training WDQ LCDL Minimum. - */ -#define DDRPHY_DTEDR0_DTWLMN_MASK (0xFFU) -#define DDRPHY_DTEDR0_DTWLMN_SHIFT (0U) -#define DDRPHY_DTEDR0_DTWLMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR0_DTWLMN_MASK) >> DDRPHY_DTEDR0_DTWLMN_SHIFT) - -/* Bitfield definition for register: DTEDR1 */ -/* - * DTRBMX (R) - * - * Data Training Read BDL Shift Maximum. - */ -#define DDRPHY_DTEDR1_DTRBMX_MASK (0xFF000000UL) -#define DDRPHY_DTEDR1_DTRBMX_SHIFT (24U) -#define DDRPHY_DTEDR1_DTRBMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRBMX_MASK) >> DDRPHY_DTEDR1_DTRBMX_SHIFT) - -/* - * DTRBMN (R) - * - * Data Training Read BDL Shift Minimum. - */ -#define DDRPHY_DTEDR1_DTRBMN_MASK (0xFF0000UL) -#define DDRPHY_DTEDR1_DTRBMN_SHIFT (16U) -#define DDRPHY_DTEDR1_DTRBMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRBMN_MASK) >> DDRPHY_DTEDR1_DTRBMN_SHIFT) - -/* - * DTRLMX (R) - * - * Data Training RDQS LCDL Maximum. - */ -#define DDRPHY_DTEDR1_DTRLMX_MASK (0xFF00U) -#define DDRPHY_DTEDR1_DTRLMX_SHIFT (8U) -#define DDRPHY_DTEDR1_DTRLMX_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRLMX_MASK) >> DDRPHY_DTEDR1_DTRLMX_SHIFT) - -/* - * DTRLMN (R) - * - * Data Training RDQS LCDL Minimum. - */ -#define DDRPHY_DTEDR1_DTRLMN_MASK (0xFFU) -#define DDRPHY_DTEDR1_DTRLMN_SHIFT (0U) -#define DDRPHY_DTEDR1_DTRLMN_GET(x) (((uint32_t)(x) & DDRPHY_DTEDR1_DTRLMN_MASK) >> DDRPHY_DTEDR1_DTRLMN_SHIFT) - -/* Bitfield definition for register: PGCR2 */ -/* - * DYNACPDD1 (R/W) - * - * Dynamic AC Power Down Driver: Powers down, when set, the output driver on I/O for ADDR and BA. This bit is ORed with bit ACIOCR[3] (ACPDD). - */ -#define DDRPHY_PGCR2_DYNACPDD1_MASK (0x80000000UL) -#define DDRPHY_PGCR2_DYNACPDD1_SHIFT (31U) -#define DDRPHY_PGCR2_DYNACPDD1_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_DYNACPDD1_SHIFT) & DDRPHY_PGCR2_DYNACPDD1_MASK) -#define DDRPHY_PGCR2_DYNACPDD1_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_DYNACPDD1_MASK) >> DDRPHY_PGCR2_DYNACPDD1_SHIFT) - -/* - * LPMSTRC0 (R/W) - * - * Low-Power Master Channel 0: set to 1 to have channel 0 act as master to drive channel 1 low-power functions simultaneously. Only valid in shared-AC mode. - */ -#define DDRPHY_PGCR2_LPMSTRC0_MASK (0x40000000UL) -#define DDRPHY_PGCR2_LPMSTRC0_SHIFT (30U) -#define DDRPHY_PGCR2_LPMSTRC0_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_LPMSTRC0_SHIFT) & DDRPHY_PGCR2_LPMSTRC0_MASK) -#define DDRPHY_PGCR2_LPMSTRC0_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_LPMSTRC0_MASK) >> DDRPHY_PGCR2_LPMSTRC0_SHIFT) - -/* - * ACPDDC (R/W) - * - * AC Power-Down with Dual Channels: Set to 1 to power-down address/command lane when both data channels are powered-down. Only valid in shared-AC mode. - */ -#define DDRPHY_PGCR2_ACPDDC_MASK (0x20000000UL) -#define DDRPHY_PGCR2_ACPDDC_SHIFT (29U) -#define DDRPHY_PGCR2_ACPDDC_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_ACPDDC_SHIFT) & DDRPHY_PGCR2_ACPDDC_MASK) -#define DDRPHY_PGCR2_ACPDDC_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_ACPDDC_MASK) >> DDRPHY_PGCR2_ACPDDC_SHIFT) - -/* - * SHRAC (R/W) - * - * Shared-AC mode: set to 1 to enable shared address/command mode with two independent data channels – available only if shared address/command mode support is compiled in. - */ -#define DDRPHY_PGCR2_SHRAC_MASK (0x10000000UL) -#define DDRPHY_PGCR2_SHRAC_SHIFT (28U) -#define DDRPHY_PGCR2_SHRAC_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_SHRAC_SHIFT) & DDRPHY_PGCR2_SHRAC_MASK) -#define DDRPHY_PGCR2_SHRAC_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_SHRAC_MASK) >> DDRPHY_PGCR2_SHRAC_SHIFT) - -/* - * DTPMXTMR (R/W) - * - * Data Training PUB Mode Timer Exit: Specifies the number of controller clocks to wait when entering and exiting pub mode data training. The default value ensures controller refreshes do not cause memory model errors when entering and exiting data training. The value should be increased if controller initiated SDRAM ZQ short or long operation may occur just before or just after the execution of data training. - */ -#define DDRPHY_PGCR2_DTPMXTMR_MASK (0xFF00000UL) -#define DDRPHY_PGCR2_DTPMXTMR_SHIFT (20U) -#define DDRPHY_PGCR2_DTPMXTMR_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_DTPMXTMR_SHIFT) & DDRPHY_PGCR2_DTPMXTMR_MASK) -#define DDRPHY_PGCR2_DTPMXTMR_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_DTPMXTMR_MASK) >> DDRPHY_PGCR2_DTPMXTMR_SHIFT) - -/* - * FXDLAT (R/W) - * - * Fixed Latency: Specified whether all reads should be returned to the controller with a fixed read latency. Enabling fixed read latency increases the read latency. Valid values are: - * 0 = Disable fixed read latency 1 = Enable fixed read latency - * Fixed read latency is calculated as (12 + (maximum DXnGTR.RxDGSL)/2) HDR clock cycles - */ -#define DDRPHY_PGCR2_FXDLAT_MASK (0x80000UL) -#define DDRPHY_PGCR2_FXDLAT_SHIFT (19U) -#define DDRPHY_PGCR2_FXDLAT_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_FXDLAT_SHIFT) & DDRPHY_PGCR2_FXDLAT_MASK) -#define DDRPHY_PGCR2_FXDLAT_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_FXDLAT_MASK) >> DDRPHY_PGCR2_FXDLAT_SHIFT) - -/* - * NOBUB (R/W) - * - * No Bubbles: Specified whether reads should be returned to the controller with no bubbles. Enabling no-bubble reads increases the read latency. Valid values are: 0 = Bubbles are allowed during reads - * 1 = Bubbles are not allowed during reads - */ -#define DDRPHY_PGCR2_NOBUB_MASK (0x40000UL) -#define DDRPHY_PGCR2_NOBUB_SHIFT (18U) -#define DDRPHY_PGCR2_NOBUB_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_NOBUB_SHIFT) & DDRPHY_PGCR2_NOBUB_MASK) -#define DDRPHY_PGCR2_NOBUB_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_NOBUB_MASK) >> DDRPHY_PGCR2_NOBUB_SHIFT) - -/* - * TREFPRD (R/W) - * - * Refresh Period: Indicates the period, after which the PUB has to issue a refresh command to the SDRAM. This is derived from the maximum refresh interval from the datasheet, tRFC(max) or REFI, divided by the clock cycle time. A further 400 clocks must be subtracted from the derived number to account for command flow and missed slots of refreshes in the internal PUB blocks. The default corresponds to DDR3 9*7.8us at 1066MHz when a burst of 9 refreshes are issued at every refresh interval. - */ -#define DDRPHY_PGCR2_TREFPRD_MASK (0x3FFFFUL) -#define DDRPHY_PGCR2_TREFPRD_SHIFT (0U) -#define DDRPHY_PGCR2_TREFPRD_SET(x) (((uint32_t)(x) << DDRPHY_PGCR2_TREFPRD_SHIFT) & DDRPHY_PGCR2_TREFPRD_MASK) -#define DDRPHY_PGCR2_TREFPRD_GET(x) (((uint32_t)(x) & DDRPHY_PGCR2_TREFPRD_MASK) >> DDRPHY_PGCR2_TREFPRD_SHIFT) - -/* Bitfield definition for register: RDIMMGCR0 */ -/* - * MIRROR (R) - * - * RDIMM Mirror: Selects between two different ballouts of the RDIMM buffer chip for front or back operation. This register bit controls the buffer chip MIRROR signal. - */ -#define DDRPHY_RDIMMGCR0_MIRROR_MASK (0x80000000UL) -#define DDRPHY_RDIMMGCR0_MIRROR_SHIFT (31U) -#define DDRPHY_RDIMMGCR0_MIRROR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_MIRROR_MASK) >> DDRPHY_RDIMMGCR0_MIRROR_SHIFT) - -/* - * QCSEN (R) - * - * RDMIMM Quad CS Enable: Enables, if set, the Quad CS mode for the RDIMM registering buffer chip. This register bit controls the buffer chip QCSEN# signal. - */ -#define DDRPHY_RDIMMGCR0_QCSEN_MASK (0x40000000UL) -#define DDRPHY_RDIMMGCR0_QCSEN_SHIFT (30U) -#define DDRPHY_RDIMMGCR0_QCSEN_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_QCSEN_MASK) >> DDRPHY_RDIMMGCR0_QCSEN_SHIFT) - -/* - * MIRROROE (R) - * - * MIRROR Output Enable: Enables, when set, the output driver on the I/O for MIRROR pin. - */ -#define DDRPHY_RDIMMGCR0_MIRROROE_MASK (0x20000000UL) -#define DDRPHY_RDIMMGCR0_MIRROROE_SHIFT (29U) -#define DDRPHY_RDIMMGCR0_MIRROROE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_MIRROROE_MASK) >> DDRPHY_RDIMMGCR0_MIRROROE_SHIFT) - -/* - * QCSENOE (R) - * - * QCSEN# Output Enable: Enables, when set, the output driver on the I/O for QCSEN# pin. - */ -#define DDRPHY_RDIMMGCR0_QCSENOE_MASK (0x10000000UL) -#define DDRPHY_RDIMMGCR0_QCSENOE_SHIFT (28U) -#define DDRPHY_RDIMMGCR0_QCSENOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_QCSENOE_MASK) >> DDRPHY_RDIMMGCR0_QCSENOE_SHIFT) - -/* - * RDIMMIOM (R) - * - * RDIMM Outputs I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for QCSEN# and MIRROR pins. - */ -#define DDRPHY_RDIMMGCR0_RDIMMIOM_MASK (0x8000000UL) -#define DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT (27U) -#define DDRPHY_RDIMMGCR0_RDIMMIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMIOM_MASK) >> DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT) - -/* - * RDIMMPDR (R) - * - * RDIMM Outputs Power Down Receiver: Powers down, when set, the input receiver on the I/O for QCSEN# and MIRROR pins. - */ -#define DDRPHY_RDIMMGCR0_RDIMMPDR_MASK (0x4000000UL) -#define DDRPHY_RDIMMGCR0_RDIMMPDR_SHIFT (26U) -#define DDRPHY_RDIMMGCR0_RDIMMPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMPDR_MASK) >> DDRPHY_RDIMMGCR0_RDIMMPDR_SHIFT) - -/* - * RDIMMPDD (R) - * - * RDIMM Outputs Power Down Driver: Powers down, when set, the output driver on the I/O for QCSEN# and MIRROR pins. - */ -#define DDRPHY_RDIMMGCR0_RDIMMPDD_MASK (0x2000000UL) -#define DDRPHY_RDIMMGCR0_RDIMMPDD_SHIFT (25U) -#define DDRPHY_RDIMMGCR0_RDIMMPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMPDD_MASK) >> DDRPHY_RDIMMGCR0_RDIMMPDD_SHIFT) - -/* - * RDIMMODT (R) - * - * RDIMM Outputs On-Die Termination: Enables, when set, the on-die termination on the I/O for QCSEN# and MIRROR pins. - */ -#define DDRPHY_RDIMMGCR0_RDIMMODT_MASK (0x1000000UL) -#define DDRPHY_RDIMMGCR0_RDIMMODT_SHIFT (24U) -#define DDRPHY_RDIMMGCR0_RDIMMODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMMODT_MASK) >> DDRPHY_RDIMMGCR0_RDIMMODT_SHIFT) - -/* - * ERROUTOE (R) - * - * ERROUT# Output Enable: Enables, when set, the output driver on the I/O for ERROUT# pin. - */ -#define DDRPHY_RDIMMGCR0_ERROUTOE_MASK (0x800000UL) -#define DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT (23U) -#define DDRPHY_RDIMMGCR0_ERROUTOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTOE_MASK) >> DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT) - -/* - * ERROUTIOM (R) - * - * ERROUT# I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for ERROUT# pin. - */ -#define DDRPHY_RDIMMGCR0_ERROUTIOM_MASK (0x400000UL) -#define DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT (22U) -#define DDRPHY_RDIMMGCR0_ERROUTIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTIOM_MASK) >> DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT) - -/* - * ERROUTPDR (R) - * - * ERROUT# Power Down Receiver: Powers down, when set, the input receiver on the I/O for ERROUT# pin. - */ -#define DDRPHY_RDIMMGCR0_ERROUTPDR_MASK (0x200000UL) -#define DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT (21U) -#define DDRPHY_RDIMMGCR0_ERROUTPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTPDR_MASK) >> DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT) - -/* - * ERROUTPDD (R) - * - * ERROUT# Power Down Driver: Powers down, when set, the output driver on the I/O for ERROUT# pin. - */ -#define DDRPHY_RDIMMGCR0_ERROUTPDD_MASK (0x100000UL) -#define DDRPHY_RDIMMGCR0_ERROUTPDD_SHIFT (20U) -#define DDRPHY_RDIMMGCR0_ERROUTPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTPDD_MASK) >> DDRPHY_RDIMMGCR0_ERROUTPDD_SHIFT) - -/* - * ERROUTODT (R) - * - * ERROUT# On-Die Termination: Enables, when set, the on-die termination on the I/O for ERROUT# pin. - */ -#define DDRPHY_RDIMMGCR0_ERROUTODT_MASK (0x80000UL) -#define DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT (19U) -#define DDRPHY_RDIMMGCR0_ERROUTODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERROUTODT_MASK) >> DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT) - -/* - * PARINOE (R) - * - * PAR_IN Output Enable: Enables, when set, the output driver on the I/O for PAR_IN pin. - */ -#define DDRPHY_RDIMMGCR0_PARINOE_MASK (0x40000UL) -#define DDRPHY_RDIMMGCR0_PARINOE_SHIFT (18U) -#define DDRPHY_RDIMMGCR0_PARINOE_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINOE_MASK) >> DDRPHY_RDIMMGCR0_PARINOE_SHIFT) - -/* - * PARINIOM (R) - * - * PAR_IN I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for PAR_IN pin. - */ -#define DDRPHY_RDIMMGCR0_PARINIOM_MASK (0x20000UL) -#define DDRPHY_RDIMMGCR0_PARINIOM_SHIFT (17U) -#define DDRPHY_RDIMMGCR0_PARINIOM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINIOM_MASK) >> DDRPHY_RDIMMGCR0_PARINIOM_SHIFT) - -/* - * PARINPDR (R) - * - * PAR_IN Power Down Receiver: Powers down, when set, the input receiver on the I/O for PAR_IN pin. - */ -#define DDRPHY_RDIMMGCR0_PARINPDR_MASK (0x10000UL) -#define DDRPHY_RDIMMGCR0_PARINPDR_SHIFT (16U) -#define DDRPHY_RDIMMGCR0_PARINPDR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINPDR_MASK) >> DDRPHY_RDIMMGCR0_PARINPDR_SHIFT) - -/* - * PARINPDD (R) - * - * PAR_IN Power Down Driver: Powers down, when set, the output driver on the I/O for PAR_IN pin. - */ -#define DDRPHY_RDIMMGCR0_PARINPDD_MASK (0x8000U) -#define DDRPHY_RDIMMGCR0_PARINPDD_SHIFT (15U) -#define DDRPHY_RDIMMGCR0_PARINPDD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINPDD_MASK) >> DDRPHY_RDIMMGCR0_PARINPDD_SHIFT) - -/* - * PARINODT (R) - * - * PAR_IN On-Die Termination: Enables, when set, the on-die termination on the I/O for PAR_IN pin. - */ -#define DDRPHY_RDIMMGCR0_PARINODT_MASK (0x4000U) -#define DDRPHY_RDIMMGCR0_PARINODT_SHIFT (14U) -#define DDRPHY_RDIMMGCR0_PARINODT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_PARINODT_MASK) >> DDRPHY_RDIMMGCR0_PARINODT_SHIFT) - -/* - * SOPERR (R) - * - * Stop On Parity Error: Indicates, if set, that the PUB is to stop driving commands to the DRAM upon encountering a parity error. Transactions can resume only after status is cleared via PIR.CLRSR. - */ -#define DDRPHY_RDIMMGCR0_SOPERR_MASK (0x4U) -#define DDRPHY_RDIMMGCR0_SOPERR_SHIFT (2U) -#define DDRPHY_RDIMMGCR0_SOPERR_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_SOPERR_MASK) >> DDRPHY_RDIMMGCR0_SOPERR_SHIFT) - -/* - * ERRNOREG (R) - * - * Parity Error No Registering: Indicates, if set, that parity error signal from the RDIMM should be passed to the DFI controller without any synchronization or registering. Otherwise, the error signal is synchronized as shown in Figure 4-30 on page 262. - */ -#define DDRPHY_RDIMMGCR0_ERRNOREG_MASK (0x2U) -#define DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT (1U) -#define DDRPHY_RDIMMGCR0_ERRNOREG_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_ERRNOREG_MASK) >> DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT) - -/* - * RDIMM (R) - * - * Registered DIMM: Indicates, if set, that a registered DIMM is used. In this case, the PUB increases the SDRAM write and read latencies (WL/RL) by 1 and also enforces that accesses adhere to RDIMM buffer chip. This only applies to PUB internal SDRAM transactions. Transactions generated by the controller must make its own adjustments to WL/RL when using a registered DIMM. The DCR.NOSRA register bit must be set to ‘1’ if using the standard RDIMM buffer chip so that normal DRAM accesses do not assert multiple chip select bits at the same time. - */ -#define DDRPHY_RDIMMGCR0_RDIMM_MASK (0x1U) -#define DDRPHY_RDIMMGCR0_RDIMM_SHIFT (0U) -#define DDRPHY_RDIMMGCR0_RDIMM_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR0_RDIMM_MASK) >> DDRPHY_RDIMMGCR0_RDIMM_SHIFT) - -/* Bitfield definition for register: RDIMMGCR1 */ -/* - * CRINIT (R) - * - * Control Registers Initialization Enable: Indicates which RDIMM buffer chip control registers (RC0 to RC15) should be initialized (written) when the PUB is triggered to initialize the buffer chip. A setting of ‘1’ on CRINIT[n] bit means that CRn should be written during initialization. - */ -#define DDRPHY_RDIMMGCR1_CRINIT_MASK (0xFFFF0000UL) -#define DDRPHY_RDIMMGCR1_CRINIT_SHIFT (16U) -#define DDRPHY_RDIMMGCR1_CRINIT_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_CRINIT_MASK) >> DDRPHY_RDIMMGCR1_CRINIT_SHIFT) - -/* - * TBCMRD (R) - * - * Command word to command word programming delay: Number of DRAM clock cycles between two RDIMM buffer chip command programming accesses. The value used for tBCMRD is 8 plus the value programmed in these bits, i.e. tBCMRD value ranges from 8 to 15. This parameter corresponds to the buffer chip tMRD parameter. - */ -#define DDRPHY_RDIMMGCR1_TBCMRD_MASK (0x7000U) -#define DDRPHY_RDIMMGCR1_TBCMRD_SHIFT (12U) -#define DDRPHY_RDIMMGCR1_TBCMRD_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_TBCMRD_MASK) >> DDRPHY_RDIMMGCR1_TBCMRD_SHIFT) - -/* - * TBCSTAB (R) - * - * Stabilization time: Number of DRAM clock cycles for the RDIMM buffer chip to stabilize. This parameter corresponds to the buffer chip tSTAB parameter. Default value is in decimal format and corresponds to 6us at 533MHz. - */ -#define DDRPHY_RDIMMGCR1_TBCSTAB_MASK (0xFFFU) -#define DDRPHY_RDIMMGCR1_TBCSTAB_SHIFT (0U) -#define DDRPHY_RDIMMGCR1_TBCSTAB_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMGCR1_TBCSTAB_MASK) >> DDRPHY_RDIMMGCR1_TBCSTAB_SHIFT) - -/* Bitfield definition for register: RDIMMCR0 */ -/* - * RC7 (R) - * - * Control Word 7: Reserved, free to use by vendor. - */ -#define DDRPHY_RDIMMCR0_RC7_MASK (0xF0000000UL) -#define DDRPHY_RDIMMCR0_RC7_SHIFT (28U) -#define DDRPHY_RDIMMCR0_RC7_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC7_MASK) >> DDRPHY_RDIMMCR0_RC7_SHIFT) - -/* - * RC6 (R) - * - * Control Word 6: Reserved, free to use by vendor. - */ -#define DDRPHY_RDIMMCR0_RC6_MASK (0xF000000UL) -#define DDRPHY_RDIMMCR0_RC6_SHIFT (24U) -#define DDRPHY_RDIMMCR0_RC6_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC6_MASK) >> DDRPHY_RDIMMCR0_RC6_SHIFT) - -/* - * RC5 (R) - * - * Control Word 5 (CK Driver Characteristics Control Word): RC5[1:0] is driver settings for clock Y1, Y1#, Y3, and Y3# outputs, and RC5[3:2] is driver settings for clock Y0, Y0#, Y2, and Y2# outputs. Bit definitions are: - * 00 = Light drive (4 or 5 DRAM loads) - * 01 = Moderate drive (8 or 10 DRAM loads) - * 10 = Strong drive (16 or 20 DRAM loads) - * 11 = Reserved - */ -#define DDRPHY_RDIMMCR0_RC5_MASK (0xF00000UL) -#define DDRPHY_RDIMMCR0_RC5_SHIFT (20U) -#define DDRPHY_RDIMMCR0_RC5_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC5_MASK) >> DDRPHY_RDIMMCR0_RC5_SHIFT) - -/* - * RC4 (R) - * - * Control Word 4 (Control Signals Driver Characteristics Control Word): RC4[1:0] is driver settings for control A outputs, and RC4[3:2] is driver settings for control B outputs. Bit definitions are: - * 00 = Light drive (4 or 5 DRAM loads) - * 01 = Moderate drive (8 or 10 DRAM loads) - * 10 = Reserved - * 11 = Reserved - */ -#define DDRPHY_RDIMMCR0_RC4_MASK (0xF0000UL) -#define DDRPHY_RDIMMCR0_RC4_SHIFT (16U) -#define DDRPHY_RDIMMCR0_RC4_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC4_MASK) >> DDRPHY_RDIMMCR0_RC4_SHIFT) - -/* - * RC3 (R) - * - * Control Word 3 (Command/Address Signals Driver Characteristics Control Word): RC3[1:0] is driver settings for command/address A outputs, and RC3[3:2] is driver settings for command/address B outputs. Bit definitions are: - * 00 = Light drive (4 or 5 DRAM loads) - * 01 = Moderate drive (8 or 10 DRAM loads) - * 10 = Strong drive (16 or 20 DRAM loads) - * 11 = Reserved - */ -#define DDRPHY_RDIMMCR0_RC3_MASK (0xF000U) -#define DDRPHY_RDIMMCR0_RC3_SHIFT (12U) -#define DDRPHY_RDIMMCR0_RC3_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC3_MASK) >> DDRPHY_RDIMMCR0_RC3_SHIFT) - -/* - * RC2 (R) - * - * Control Word 2 (Timing Control Word): Bit definitions are: - * RC2[0]: 0 = Standard (1/2 clock) pre-launch, 1 = Prelaunch controlled by RC12. RC2[1]: 0 = Reserved. - * RC2[2]: 0 = 100 Ohm input bus termination, 1 = 150 Ohm input bus termination. RC2[3]: 0 = Operation frequency band 1, 1 = Test mode frequency band 2. - */ -#define DDRPHY_RDIMMCR0_RC2_MASK (0xF00U) -#define DDRPHY_RDIMMCR0_RC2_SHIFT (8U) -#define DDRPHY_RDIMMCR0_RC2_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC2_MASK) >> DDRPHY_RDIMMCR0_RC2_SHIFT) - -/* - * RC1 (R) - * - * Control Word 1 (Clock Driver Enable Control Word): Bit definitions are: RC1[0]: 0 = Y0/Y0# clock enabled, 1 = Y0/Y0# clock disabled. - * RC1[1]: 0 = Y1/Y1# clock enabled, 1 = Y1/Y1# clock disabled. RC1[2]: 0 = Y2/Y2# clock enabled, 1 = Y2/Y2# clock disabled. RC1[3]: 0 = Y3/Y3# clock enabled, 1 = Y3/Y3# clock disabled. - */ -#define DDRPHY_RDIMMCR0_RC1_MASK (0xF0U) -#define DDRPHY_RDIMMCR0_RC1_SHIFT (4U) -#define DDRPHY_RDIMMCR0_RC1_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC1_MASK) >> DDRPHY_RDIMMCR0_RC1_SHIFT) - -/* - * RC0 (R) - * - * Control Word 0 (Global Features Control Word): Bit definitions are: RC0[0]: 0 = Output inversion enabled, 1 = Output inversion disabled. RC0[1]: 0 = Floating outputs disabled, 1 = Floating outputs enabled. RC0[2]: 0 = A outputs enabled, 1 = A outputs disabled. - * RC0[3]: 0 = B outputs enabled, 1 = B outputs disabled. - */ -#define DDRPHY_RDIMMCR0_RC0_MASK (0xFU) -#define DDRPHY_RDIMMCR0_RC0_SHIFT (0U) -#define DDRPHY_RDIMMCR0_RC0_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR0_RC0_MASK) >> DDRPHY_RDIMMCR0_RC0_SHIFT) - -/* Bitfield definition for register: RDIMMCR1 */ -/* - * RC15 (R) - * - * Control Word 15: Reserved for future use. - */ -#define DDRPHY_RDIMMCR1_RC15_MASK (0xF0000000UL) -#define DDRPHY_RDIMMCR1_RC15_SHIFT (28U) -#define DDRPHY_RDIMMCR1_RC15_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC15_MASK) >> DDRPHY_RDIMMCR1_RC15_SHIFT) - -/* - * RC14 (R) - * - * Control Word 14: Reserved for future use. - */ -#define DDRPHY_RDIMMCR1_RC14_MASK (0xF000000UL) -#define DDRPHY_RDIMMCR1_RC14_SHIFT (24U) -#define DDRPHY_RDIMMCR1_RC14_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC14_MASK) >> DDRPHY_RDIMMCR1_RC14_SHIFT) - -/* - * RC13 (R) - * - * Control Word 13: Reserved for future use. - */ -#define DDRPHY_RDIMMCR1_RC13_MASK (0xF00000UL) -#define DDRPHY_RDIMMCR1_RC13_SHIFT (20U) -#define DDRPHY_RDIMMCR1_RC13_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC13_MASK) >> DDRPHY_RDIMMCR1_RC13_SHIFT) - -/* - * RC12 (R) - * - * Control Word 12: Reserved for future use. - */ -#define DDRPHY_RDIMMCR1_RC12_MASK (0xF0000UL) -#define DDRPHY_RDIMMCR1_RC12_SHIFT (16U) -#define DDRPHY_RDIMMCR1_RC12_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC12_MASK) >> DDRPHY_RDIMMCR1_RC12_SHIFT) - -/* - * RC11 (R) - * - * Control Word 11 (Operating Voltage VDD Control Word): RC10[1:0] is VDD operating voltage setting as follows: 00 = DDR3 1.5V mode - * 01 = DDR3L 1.35V mode - * 10 = Reserved - * 11 = Reserved RC10[3:2]: Reserved. - */ -#define DDRPHY_RDIMMCR1_RC11_MASK (0xF000U) -#define DDRPHY_RDIMMCR1_RC11_SHIFT (12U) -#define DDRPHY_RDIMMCR1_RC11_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC11_MASK) >> DDRPHY_RDIMMCR1_RC11_SHIFT) - -/* - * RC10 (R) - * - * Control Word 10 (RDIMM Operating Speed Control Word): RC10[2:0] is RDIMM operating speed setting as follows: 000 = DDR3/DDR3L-800 - * 001 = DDR3/DDR3L-1066 - * 010 = DDR3/DDR3L-1333 - * 011 = DDR3/DDR3L-1600 - * 100 = Reserved - * 101 = Reserved - * 110 = Reserved - * 111 = Reserved RC10[3]: Don’t care. - */ -#define DDRPHY_RDIMMCR1_RC10_MASK (0xF00U) -#define DDRPHY_RDIMMCR1_RC10_SHIFT (8U) -#define DDRPHY_RDIMMCR1_RC10_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC10_MASK) >> DDRPHY_RDIMMCR1_RC10_SHIFT) - -/* - * RC9 (R) - * - * Control Word 9 (Power Saving Settings Control Word): Bit definitions are: RC9[0]: 0 = Floating outputs as defined in RC0, 1 = Weak drive enabled. RC9[1]: 0 = Reserved. - * RC9[2]: 0 = CKE power down with IBT ON, QxODT is a function of DxODT, 1 = CKE power down with IBT off, QxODT held LOW. RC9[2] is valid only when RC9[3] is 1. - * RC9[3]: 0 = CKE power down mode disabled, 1 = CKE power down mode enabled. - */ -#define DDRPHY_RDIMMCR1_RC9_MASK (0xF0U) -#define DDRPHY_RDIMMCR1_RC9_SHIFT (4U) -#define DDRPHY_RDIMMCR1_RC9_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC9_MASK) >> DDRPHY_RDIMMCR1_RC9_SHIFT) - -/* - * RC8 (R) - * - * Control Word 8 (Additional Input Bus Termination Setting Control Word): RC8[2:0] is Input Bus Termination (IBT) setting as follows: - * 000 = IBT as defined in RC2. 001 = Reserved - * 010 = 200 Ohm - * 011 = Reserved - * 100 = 300 Ohm - * 101 = Reserved - * 110 = Reserved - * 111 = Off - * RC8[3]: 0 = IBT off when MIRROR is HIGH, 1 = IBT on when MIRROR is high - */ -#define DDRPHY_RDIMMCR1_RC8_MASK (0xFU) -#define DDRPHY_RDIMMCR1_RC8_SHIFT (0U) -#define DDRPHY_RDIMMCR1_RC8_GET(x) (((uint32_t)(x) & DDRPHY_RDIMMCR1_RC8_MASK) >> DDRPHY_RDIMMCR1_RC8_SHIFT) - -/* Bitfield definition for register: DCUAR */ -/* - * ATYPE (R/W) - * - * Access Type: Specifies the type of access to be performed using this address. Valid values are: - * 0 = Write access 1 = Read access - */ -#define DDRPHY_DCUAR_ATYPE_MASK (0x800U) -#define DDRPHY_DCUAR_ATYPE_SHIFT (11U) -#define DDRPHY_DCUAR_ATYPE_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_ATYPE_SHIFT) & DDRPHY_DCUAR_ATYPE_MASK) -#define DDRPHY_DCUAR_ATYPE_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_ATYPE_MASK) >> DDRPHY_DCUAR_ATYPE_SHIFT) - -/* - * INCA (R/W) - * - * Increment Address: Specifies, if set, that the cache address specified in WADDR and SADDR should be automatically incremented after each access of the cache. The increment happens in such a way that all the slices of a selected word are first accessed before going to the next word. - */ -#define DDRPHY_DCUAR_INCA_MASK (0x400U) -#define DDRPHY_DCUAR_INCA_SHIFT (10U) -#define DDRPHY_DCUAR_INCA_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_INCA_SHIFT) & DDRPHY_DCUAR_INCA_MASK) -#define DDRPHY_DCUAR_INCA_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_INCA_MASK) >> DDRPHY_DCUAR_INCA_SHIFT) - -/* - * CSEL (R/W) - * - * Cache Select: Selects the cache to be accessed. Valid values are: 00 = Command cache - * 01 = Expected data cache 10 = Read data cache - * 11 = Reserved - */ -#define DDRPHY_DCUAR_CSEL_MASK (0x300U) -#define DDRPHY_DCUAR_CSEL_SHIFT (8U) -#define DDRPHY_DCUAR_CSEL_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CSEL_SHIFT) & DDRPHY_DCUAR_CSEL_MASK) -#define DDRPHY_DCUAR_CSEL_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CSEL_MASK) >> DDRPHY_DCUAR_CSEL_SHIFT) - -/* - * CSADDR (R/W) - * - * Cache Slice Address: Address of the cache slice to be accessed. - */ -#define DDRPHY_DCUAR_CSADDR_MASK (0xF0U) -#define DDRPHY_DCUAR_CSADDR_SHIFT (4U) -#define DDRPHY_DCUAR_CSADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CSADDR_SHIFT) & DDRPHY_DCUAR_CSADDR_MASK) -#define DDRPHY_DCUAR_CSADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CSADDR_MASK) >> DDRPHY_DCUAR_CSADDR_SHIFT) - -/* - * CWADDR (R/W) - * - * Cache Word Address: Address of the cache word to be accessed. - */ -#define DDRPHY_DCUAR_CWADDR_MASK (0xFU) -#define DDRPHY_DCUAR_CWADDR_SHIFT (0U) -#define DDRPHY_DCUAR_CWADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCUAR_CWADDR_SHIFT) & DDRPHY_DCUAR_CWADDR_MASK) -#define DDRPHY_DCUAR_CWADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCUAR_CWADDR_MASK) >> DDRPHY_DCUAR_CWADDR_SHIFT) - -/* Bitfield definition for register: DCUDR */ -/* - * CDATA (R/W) - * - * Cache Data: Data to be written to or read from a cache. This data corresponds to the cache word slice specified by the DCU Address Register. - */ -#define DDRPHY_DCUDR_CDATA_MASK (0xFFFFFFFFUL) -#define DDRPHY_DCUDR_CDATA_SHIFT (0U) -#define DDRPHY_DCUDR_CDATA_SET(x) (((uint32_t)(x) << DDRPHY_DCUDR_CDATA_SHIFT) & DDRPHY_DCUDR_CDATA_MASK) -#define DDRPHY_DCUDR_CDATA_GET(x) (((uint32_t)(x) & DDRPHY_DCUDR_CDATA_MASK) >> DDRPHY_DCUDR_CDATA_SHIFT) - -/* Bitfield definition for register: DCURR */ -/* - * XCEN (R/W) - * - * Expected Compare Enable: Indicates, if set, that read data coming back from the SDRAM should be should be compared with the expected data. - */ -#define DDRPHY_DCURR_XCEN_MASK (0x800000UL) -#define DDRPHY_DCURR_XCEN_SHIFT (23U) -#define DDRPHY_DCURR_XCEN_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_XCEN_SHIFT) & DDRPHY_DCURR_XCEN_MASK) -#define DDRPHY_DCURR_XCEN_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_XCEN_MASK) >> DDRPHY_DCURR_XCEN_SHIFT) - -/* - * RCEN (R/W) - * - * Read Capture Enable: Indicates, if set, that read data coming back from the SDRAM should be captured into the read data cache. - */ -#define DDRPHY_DCURR_RCEN_MASK (0x400000UL) -#define DDRPHY_DCURR_RCEN_SHIFT (22U) -#define DDRPHY_DCURR_RCEN_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_RCEN_SHIFT) & DDRPHY_DCURR_RCEN_MASK) -#define DDRPHY_DCURR_RCEN_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_RCEN_MASK) >> DDRPHY_DCURR_RCEN_SHIFT) - -/* - * SCOF (R/W) - * - * Stop Capture On Full: Specifies, if set, that the capture of read data should stop when the capture cache is full. - */ -#define DDRPHY_DCURR_SCOF_MASK (0x200000UL) -#define DDRPHY_DCURR_SCOF_SHIFT (21U) -#define DDRPHY_DCURR_SCOF_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SCOF_SHIFT) & DDRPHY_DCURR_SCOF_MASK) -#define DDRPHY_DCURR_SCOF_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SCOF_MASK) >> DDRPHY_DCURR_SCOF_SHIFT) - -/* - * SONF (R/W) - * - * Stop On Nth Fail: Specifies, if set, that the execution of commands and the capture of read data should stop when there are N read data failures. The number of failures is specified by NFAIL. Otherwise commands execute until the end of the program or until manually stopped using a STOP command. - */ -#define DDRPHY_DCURR_SONF_MASK (0x100000UL) -#define DDRPHY_DCURR_SONF_SHIFT (20U) -#define DDRPHY_DCURR_SONF_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SONF_SHIFT) & DDRPHY_DCURR_SONF_MASK) -#define DDRPHY_DCURR_SONF_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SONF_MASK) >> DDRPHY_DCURR_SONF_SHIFT) - -/* - * NFAIL (R/W) - * - * Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if SONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if SONF is set. - * Valid values are from 0 to 254. - */ -#define DDRPHY_DCURR_NFAIL_MASK (0xFF000UL) -#define DDRPHY_DCURR_NFAIL_SHIFT (12U) -#define DDRPHY_DCURR_NFAIL_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_NFAIL_SHIFT) & DDRPHY_DCURR_NFAIL_MASK) -#define DDRPHY_DCURR_NFAIL_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_NFAIL_MASK) >> DDRPHY_DCURR_NFAIL_SHIFT) - -/* - * EADDR (R/W) - * - * End Address: Cache word address where the execution of command should end. - */ -#define DDRPHY_DCURR_EADDR_MASK (0xF00U) -#define DDRPHY_DCURR_EADDR_SHIFT (8U) -#define DDRPHY_DCURR_EADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_EADDR_SHIFT) & DDRPHY_DCURR_EADDR_MASK) -#define DDRPHY_DCURR_EADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_EADDR_MASK) >> DDRPHY_DCURR_EADDR_SHIFT) - -/* - * SADDR (R/W) - * - * Start Address: Cache word address where the execution of commands should begin. - */ -#define DDRPHY_DCURR_SADDR_MASK (0xF0U) -#define DDRPHY_DCURR_SADDR_SHIFT (4U) -#define DDRPHY_DCURR_SADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_SADDR_SHIFT) & DDRPHY_DCURR_SADDR_MASK) -#define DDRPHY_DCURR_SADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_SADDR_MASK) >> DDRPHY_DCURR_SADDR_SHIFT) - -/* - * DINST (R/W) - * - * DCU Instruction: Selects the DCU command to be executed: Valid values are: 0000 = NOP: No operation - * 0001 = Run: Triggers the execution of commands in the command cache. 0010 = Stop: Stops the execution of commands in the command cache. - * 0011 = Stop Loop: Stops the execution of an infinite loop in the command cache. 0100 = Reset: Resets all DCU run time registers. See “DCU Status” on page 255 for details. - * 0101 – 1111 Reserved - */ -#define DDRPHY_DCURR_DINST_MASK (0xFU) -#define DDRPHY_DCURR_DINST_SHIFT (0U) -#define DDRPHY_DCURR_DINST_SET(x) (((uint32_t)(x) << DDRPHY_DCURR_DINST_SHIFT) & DDRPHY_DCURR_DINST_MASK) -#define DDRPHY_DCURR_DINST_GET(x) (((uint32_t)(x) & DDRPHY_DCURR_DINST_MASK) >> DDRPHY_DCURR_DINST_SHIFT) - -/* Bitfield definition for register: DCULR */ -/* - * XLEADDR (R/W) - * - * Expected Data Loop End Address: The last expected data cache word address that contains valid expected data. Expected data should looped between 0 and this address. - * XLEADDR field uses only the following bits based on the cache depth: - * DCU expected data cache = 4, XLEADDR[1:0] - * DCU expected data cache = 8, XLEADDR[2:0] - * DCU expected data cache = 16, XLEADDR[3:0] - */ -#define DDRPHY_DCULR_XLEADDR_MASK (0xF0000000UL) -#define DDRPHY_DCULR_XLEADDR_SHIFT (28U) -#define DDRPHY_DCULR_XLEADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_XLEADDR_SHIFT) & DDRPHY_DCULR_XLEADDR_MASK) -#define DDRPHY_DCULR_XLEADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_XLEADDR_MASK) >> DDRPHY_DCULR_XLEADDR_SHIFT) - -/* - * IDA (R/W) - * - * Increment DRAM Address: Indicates, if set, that DRAM addresses should be incremented every time a DRAM read/write command inside the loop is executed. - */ -#define DDRPHY_DCULR_IDA_MASK (0x20000UL) -#define DDRPHY_DCULR_IDA_SHIFT (17U) -#define DDRPHY_DCULR_IDA_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_IDA_SHIFT) & DDRPHY_DCULR_IDA_MASK) -#define DDRPHY_DCULR_IDA_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_IDA_MASK) >> DDRPHY_DCULR_IDA_SHIFT) - -/* - * LINF (R/W) - * - * Loop Infinite: Indicates, if set, that the loop should be executed indefinitely until stopped by the STOP command. Otherwise the loop is execute LCNT times. - */ -#define DDRPHY_DCULR_LINF_MASK (0x10000UL) -#define DDRPHY_DCULR_LINF_SHIFT (16U) -#define DDRPHY_DCULR_LINF_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LINF_SHIFT) & DDRPHY_DCULR_LINF_MASK) -#define DDRPHY_DCULR_LINF_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LINF_MASK) >> DDRPHY_DCULR_LINF_SHIFT) - -/* - * LCNT (R/W) - * - * Loop Count: The number of times that the loop should be executed if LINF is not set. - */ -#define DDRPHY_DCULR_LCNT_MASK (0xFF00U) -#define DDRPHY_DCULR_LCNT_SHIFT (8U) -#define DDRPHY_DCULR_LCNT_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LCNT_SHIFT) & DDRPHY_DCULR_LCNT_MASK) -#define DDRPHY_DCULR_LCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LCNT_MASK) >> DDRPHY_DCULR_LCNT_SHIFT) - -/* - * LEADDR (R/W) - * - * Loop End Address: Command cache word address where the loop should end. - */ -#define DDRPHY_DCULR_LEADDR_MASK (0xF0U) -#define DDRPHY_DCULR_LEADDR_SHIFT (4U) -#define DDRPHY_DCULR_LEADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LEADDR_SHIFT) & DDRPHY_DCULR_LEADDR_MASK) -#define DDRPHY_DCULR_LEADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LEADDR_MASK) >> DDRPHY_DCULR_LEADDR_SHIFT) - -/* - * LSADDR (R/W) - * - * Loop Start Address: Command cache word address where the loop should start. - */ -#define DDRPHY_DCULR_LSADDR_MASK (0xFU) -#define DDRPHY_DCULR_LSADDR_SHIFT (0U) -#define DDRPHY_DCULR_LSADDR_SET(x) (((uint32_t)(x) << DDRPHY_DCULR_LSADDR_SHIFT) & DDRPHY_DCULR_LSADDR_MASK) -#define DDRPHY_DCULR_LSADDR_GET(x) (((uint32_t)(x) & DDRPHY_DCULR_LSADDR_MASK) >> DDRPHY_DCULR_LSADDR_SHIFT) - -/* Bitfield definition for register: DCUGCR */ -/* - * RCSW (R/W) - * - * Read Capture Start Word: The capture and compare of read data should start after Nth word. For example setting this value to 12 will skip the first 12 read data. - */ -#define DDRPHY_DCUGCR_RCSW_MASK (0xFFFFU) -#define DDRPHY_DCUGCR_RCSW_SHIFT (0U) -#define DDRPHY_DCUGCR_RCSW_SET(x) (((uint32_t)(x) << DDRPHY_DCUGCR_RCSW_SHIFT) & DDRPHY_DCUGCR_RCSW_MASK) -#define DDRPHY_DCUGCR_RCSW_GET(x) (((uint32_t)(x) & DDRPHY_DCUGCR_RCSW_MASK) >> DDRPHY_DCUGCR_RCSW_SHIFT) - -/* Bitfield definition for register: DCUTPR */ -/* - * TDCUT3 (R/W) - * - * DCU Generic Timing Parameter 3 - */ -#define DDRPHY_DCUTPR_TDCUT3_MASK (0xFF000000UL) -#define DDRPHY_DCUTPR_TDCUT3_SHIFT (24U) -#define DDRPHY_DCUTPR_TDCUT3_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT3_SHIFT) & DDRPHY_DCUTPR_TDCUT3_MASK) -#define DDRPHY_DCUTPR_TDCUT3_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT3_MASK) >> DDRPHY_DCUTPR_TDCUT3_SHIFT) - -/* - * TDCUT2 (R/W) - * - * DCU Generic Timing Parameter 2 - */ -#define DDRPHY_DCUTPR_TDCUT2_MASK (0xFF0000UL) -#define DDRPHY_DCUTPR_TDCUT2_SHIFT (16U) -#define DDRPHY_DCUTPR_TDCUT2_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT2_SHIFT) & DDRPHY_DCUTPR_TDCUT2_MASK) -#define DDRPHY_DCUTPR_TDCUT2_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT2_MASK) >> DDRPHY_DCUTPR_TDCUT2_SHIFT) - -/* - * TDCUT1 (R/W) - * - * DCU Generic Timing Parameter 1 - */ -#define DDRPHY_DCUTPR_TDCUT1_MASK (0xFF00U) -#define DDRPHY_DCUTPR_TDCUT1_SHIFT (8U) -#define DDRPHY_DCUTPR_TDCUT1_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT1_SHIFT) & DDRPHY_DCUTPR_TDCUT1_MASK) -#define DDRPHY_DCUTPR_TDCUT1_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT1_MASK) >> DDRPHY_DCUTPR_TDCUT1_SHIFT) - -/* - * TDCUT0 (R/W) - * - * DCU Generic Timing Parameter 0 - */ -#define DDRPHY_DCUTPR_TDCUT0_MASK (0xFFU) -#define DDRPHY_DCUTPR_TDCUT0_SHIFT (0U) -#define DDRPHY_DCUTPR_TDCUT0_SET(x) (((uint32_t)(x) << DDRPHY_DCUTPR_TDCUT0_SHIFT) & DDRPHY_DCUTPR_TDCUT0_MASK) -#define DDRPHY_DCUTPR_TDCUT0_GET(x) (((uint32_t)(x) & DDRPHY_DCUTPR_TDCUT0_MASK) >> DDRPHY_DCUTPR_TDCUT0_SHIFT) - -/* Bitfield definition for register: DCUSR0 */ -/* - * CFULL (R) - * - * Capture Full: Indicates, if set, that the capture cache is full. - */ -#define DDRPHY_DCUSR0_CFULL_MASK (0x4U) -#define DDRPHY_DCUSR0_CFULL_SHIFT (2U) -#define DDRPHY_DCUSR0_CFULL_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_CFULL_MASK) >> DDRPHY_DCUSR0_CFULL_SHIFT) - -/* - * CFAIL (R) - * - * Capture Fail: Indicates, if set, that at least one read data word has failed. - */ -#define DDRPHY_DCUSR0_CFAIL_MASK (0x2U) -#define DDRPHY_DCUSR0_CFAIL_SHIFT (1U) -#define DDRPHY_DCUSR0_CFAIL_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_CFAIL_MASK) >> DDRPHY_DCUSR0_CFAIL_SHIFT) - -/* - * RDONE (R) - * - * Run Done: Indicates, if set, that the DCU has finished executing the commands in the command cache. This bit is also set to indicate that a STOP command has successfully been executed and command execution has stopped. - */ -#define DDRPHY_DCUSR0_RDONE_MASK (0x1U) -#define DDRPHY_DCUSR0_RDONE_SHIFT (0U) -#define DDRPHY_DCUSR0_RDONE_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR0_RDONE_MASK) >> DDRPHY_DCUSR0_RDONE_SHIFT) - -/* Bitfield definition for register: DCUSR1 */ -/* - * LPCNT (R) - * - * Loop Count: Indicates the value of the loop count. This is useful when the program has stopped because of failures to assess how many reads were executed before first fail. - */ -#define DDRPHY_DCUSR1_LPCNT_MASK (0xFF000000UL) -#define DDRPHY_DCUSR1_LPCNT_SHIFT (24U) -#define DDRPHY_DCUSR1_LPCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_LPCNT_MASK) >> DDRPHY_DCUSR1_LPCNT_SHIFT) - -/* - * FLCNT (R) - * - * Fail Count: Number of read words that have failed. - */ -#define DDRPHY_DCUSR1_FLCNT_MASK (0xFF0000UL) -#define DDRPHY_DCUSR1_FLCNT_SHIFT (16U) -#define DDRPHY_DCUSR1_FLCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_FLCNT_MASK) >> DDRPHY_DCUSR1_FLCNT_SHIFT) - -/* - * RDCNT (R) - * - * Read Count: Number of read words returned from the SDRAM. - */ -#define DDRPHY_DCUSR1_RDCNT_MASK (0xFFFFU) -#define DDRPHY_DCUSR1_RDCNT_SHIFT (0U) -#define DDRPHY_DCUSR1_RDCNT_GET(x) (((uint32_t)(x) & DDRPHY_DCUSR1_RDCNT_MASK) >> DDRPHY_DCUSR1_RDCNT_SHIFT) - -/* Bitfield definition for register: BISTRR */ -/* - * BCCSEL (R/W) - * - * BIST Clock Cycle Select: Selects the clock numbers on which the AC loopback data is written into the FIFO. Data is written into the loopback FIFO once every four clock cycles. Valid values are: - * 00 = Clock cycle 0, 4, 8, 12, etc. - * 01 = Clock cycle 1, 5, 9, 13, etc. - * 10 = Clock cycle 2, 6, 10, 14, etc. - * 11 = Clock cycle 3, 7, 11, 15, etc. - */ -#define DDRPHY_BISTRR_BCCSEL_MASK (0x6000000UL) -#define DDRPHY_BISTRR_BCCSEL_SHIFT (25U) -#define DDRPHY_BISTRR_BCCSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BCCSEL_SHIFT) & DDRPHY_BISTRR_BCCSEL_MASK) -#define DDRPHY_BISTRR_BCCSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BCCSEL_MASK) >> DDRPHY_BISTRR_BCCSEL_SHIFT) - -/* - * BCKSEL (R/W) - * - * BIST CK Select: Selects the CK that should be used to register the AC loopback signals from the I/Os. Valid values are: - * 00 = CK[0] - * 01 = CK[1] - * 10 = CK[2] - * 11 = Reserved - */ -#define DDRPHY_BISTRR_BCKSEL_MASK (0x1800000UL) -#define DDRPHY_BISTRR_BCKSEL_SHIFT (23U) -#define DDRPHY_BISTRR_BCKSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BCKSEL_SHIFT) & DDRPHY_BISTRR_BCKSEL_MASK) -#define DDRPHY_BISTRR_BCKSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BCKSEL_MASK) >> DDRPHY_BISTRR_BCKSEL_SHIFT) - -/* - * BDXSEL (R/W) - * - * BIST DATX8 Select: Select the byte lane for comparison of loopback/read data. Valid values are 0 to 8. - */ -#define DDRPHY_BISTRR_BDXSEL_MASK (0x780000UL) -#define DDRPHY_BISTRR_BDXSEL_SHIFT (19U) -#define DDRPHY_BISTRR_BDXSEL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDXSEL_SHIFT) & DDRPHY_BISTRR_BDXSEL_MASK) -#define DDRPHY_BISTRR_BDXSEL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDXSEL_MASK) >> DDRPHY_BISTRR_BDXSEL_SHIFT) - -/* - * BDPAT (R/W) - * - * BIST Data Pattern: Selects the data pattern used during BIST. Valid values are: 00 = Walking 0 - * 01 = Walking 1 - * 10 = LFSR-based pseudo-random - * 11 = User programmable (Not valid for AC loopback). - */ -#define DDRPHY_BISTRR_BDPAT_MASK (0x60000UL) -#define DDRPHY_BISTRR_BDPAT_SHIFT (17U) -#define DDRPHY_BISTRR_BDPAT_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDPAT_SHIFT) & DDRPHY_BISTRR_BDPAT_MASK) -#define DDRPHY_BISTRR_BDPAT_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDPAT_MASK) >> DDRPHY_BISTRR_BDPAT_SHIFT) - -/* - * BDMEN (R/W) - * - * BIST Data Mask Enable: Enables, if set, that the data mask BIST should be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for loopback mode. - */ -#define DDRPHY_BISTRR_BDMEN_MASK (0x10000UL) -#define DDRPHY_BISTRR_BDMEN_SHIFT (16U) -#define DDRPHY_BISTRR_BDMEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDMEN_SHIFT) & DDRPHY_BISTRR_BDMEN_MASK) -#define DDRPHY_BISTRR_BDMEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDMEN_MASK) >> DDRPHY_BISTRR_BDMEN_SHIFT) - -/* - * BACEN (R/W) - * - * BIST AC Enable: Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to ‘1’ at the same time. - */ -#define DDRPHY_BISTRR_BACEN_MASK (0x8000U) -#define DDRPHY_BISTRR_BACEN_SHIFT (15U) -#define DDRPHY_BISTRR_BACEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BACEN_SHIFT) & DDRPHY_BISTRR_BACEN_MASK) -#define DDRPHY_BISTRR_BACEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BACEN_MASK) >> DDRPHY_BISTRR_BACEN_SHIFT) - -/* - * BDXEN (R/W) - * - * BIST DATX8 Enable: Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to ‘1’ at the same time. - */ -#define DDRPHY_BISTRR_BDXEN_MASK (0x4000U) -#define DDRPHY_BISTRR_BDXEN_SHIFT (14U) -#define DDRPHY_BISTRR_BDXEN_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BDXEN_SHIFT) & DDRPHY_BISTRR_BDXEN_MASK) -#define DDRPHY_BISTRR_BDXEN_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BDXEN_MASK) >> DDRPHY_BISTRR_BDXEN_SHIFT) - -/* - * BSONF (R/W) - * - * BIST Stop On Nth Fail: Specifies, if set, that the BIST should stop when an nth data word or address/command comparison error has been encountered. - */ -#define DDRPHY_BISTRR_BSONF_MASK (0x2000U) -#define DDRPHY_BISTRR_BSONF_SHIFT (13U) -#define DDRPHY_BISTRR_BSONF_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BSONF_SHIFT) & DDRPHY_BISTRR_BSONF_MASK) -#define DDRPHY_BISTRR_BSONF_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BSONF_MASK) >> DDRPHY_BISTRR_BSONF_SHIFT) - -/* - * NFAIL (R/W) - * - * Number of Failures: Specifies the number of failures after which the execution of commands and the capture of read data should stop if BSONF bit of this register is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set. - */ -#define DDRPHY_BISTRR_NFAIL_MASK (0x1FE0U) -#define DDRPHY_BISTRR_NFAIL_SHIFT (5U) -#define DDRPHY_BISTRR_NFAIL_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_NFAIL_SHIFT) & DDRPHY_BISTRR_NFAIL_MASK) -#define DDRPHY_BISTRR_NFAIL_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_NFAIL_MASK) >> DDRPHY_BISTRR_NFAIL_SHIFT) - -/* - * BINF (R/W) - * - * BIST Infinite Run: Specifies, if set, that the BIST should be run indefinitely until when it is either stopped or a failure has been encountered. Otherwise BIST is run until number of BIST words specified in the BISTWCR register has been generated. - */ -#define DDRPHY_BISTRR_BINF_MASK (0x10U) -#define DDRPHY_BISTRR_BINF_SHIFT (4U) -#define DDRPHY_BISTRR_BINF_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BINF_SHIFT) & DDRPHY_BISTRR_BINF_MASK) -#define DDRPHY_BISTRR_BINF_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BINF_MASK) >> DDRPHY_BISTRR_BINF_SHIFT) - -/* - * BMODE (R/W) - * - * BIST Mode: Selects the mode in which BIST is run. Valid values are: - * 0 = Loopback mode: Address, commands and data loop back at the PHY I/Os. - * 1 = DRAM mode: Address, commands and data go to DRAM for normal memory accesses. - */ -#define DDRPHY_BISTRR_BMODE_MASK (0x8U) -#define DDRPHY_BISTRR_BMODE_SHIFT (3U) -#define DDRPHY_BISTRR_BMODE_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BMODE_SHIFT) & DDRPHY_BISTRR_BMODE_MASK) -#define DDRPHY_BISTRR_BMODE_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BMODE_MASK) >> DDRPHY_BISTRR_BMODE_SHIFT) - -/* - * BINST (R/W) - * - * BIST Instruction: Selects the BIST instruction to be executed: Valid values are: 000 = NOP: No operation - * 001 = Run: Triggers the running of the BIST. 010 = Stop: Stops the running of the BIST. - * 011 = Reset: Resets all BIST run-time registers, such as error counters. 100 – 111 Reserved - */ -#define DDRPHY_BISTRR_BINST_MASK (0x7U) -#define DDRPHY_BISTRR_BINST_SHIFT (0U) -#define DDRPHY_BISTRR_BINST_SET(x) (((uint32_t)(x) << DDRPHY_BISTRR_BINST_SHIFT) & DDRPHY_BISTRR_BINST_MASK) -#define DDRPHY_BISTRR_BINST_GET(x) (((uint32_t)(x) & DDRPHY_BISTRR_BINST_MASK) >> DDRPHY_BISTRR_BINST_SHIFT) - -/* Bitfield definition for register: BISTWCR */ -/* - * BWCNT (R/W) - * - * BIST Word Count: Indicates the number of words to generate during BIST. This must be a multiple of DRAM burst length (BL) divided by 2, e.g. for BL=8, valid values are 4, 8, 12, 16, and so on. - */ -#define DDRPHY_BISTWCR_BWCNT_MASK (0xFFFFU) -#define DDRPHY_BISTWCR_BWCNT_SHIFT (0U) -#define DDRPHY_BISTWCR_BWCNT_SET(x) (((uint32_t)(x) << DDRPHY_BISTWCR_BWCNT_SHIFT) & DDRPHY_BISTWCR_BWCNT_MASK) -#define DDRPHY_BISTWCR_BWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCR_BWCNT_MASK) >> DDRPHY_BISTWCR_BWCNT_SHIFT) - -/* Bitfield definition for register: BISTMSKR0 */ -/* - * ODTMSK (R/W) - * - * Mask bit for each of the up to 4 ODT bits. - */ -#define DDRPHY_BISTMSKR0_ODTMSK_MASK (0xF0000000UL) -#define DDRPHY_BISTMSKR0_ODTMSK_SHIFT (28U) -#define DDRPHY_BISTMSKR0_ODTMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_ODTMSK_SHIFT) & DDRPHY_BISTMSKR0_ODTMSK_MASK) -#define DDRPHY_BISTMSKR0_ODTMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_ODTMSK_MASK) >> DDRPHY_BISTMSKR0_ODTMSK_SHIFT) - -/* - * CSMSK (R/W) - * - * Mask bit for each of the up to 4 CS# bits. - */ -#define DDRPHY_BISTMSKR0_CSMSK_MASK (0xF000000UL) -#define DDRPHY_BISTMSKR0_CSMSK_SHIFT (24U) -#define DDRPHY_BISTMSKR0_CSMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_CSMSK_SHIFT) & DDRPHY_BISTMSKR0_CSMSK_MASK) -#define DDRPHY_BISTMSKR0_CSMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_CSMSK_MASK) >> DDRPHY_BISTMSKR0_CSMSK_SHIFT) - -/* - * CKEMSK (R/W) - * - * Mask bit for each of the up to 4 CKE bits. - */ -#define DDRPHY_BISTMSKR0_CKEMSK_MASK (0xF00000UL) -#define DDRPHY_BISTMSKR0_CKEMSK_SHIFT (20U) -#define DDRPHY_BISTMSKR0_CKEMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_CKEMSK_SHIFT) & DDRPHY_BISTMSKR0_CKEMSK_MASK) -#define DDRPHY_BISTMSKR0_CKEMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_CKEMSK_MASK) >> DDRPHY_BISTMSKR0_CKEMSK_SHIFT) - -/* - * WEMSK (R/W) - * - * Mask bit for the WE#. - */ -#define DDRPHY_BISTMSKR0_WEMSK_MASK (0x80000UL) -#define DDRPHY_BISTMSKR0_WEMSK_SHIFT (19U) -#define DDRPHY_BISTMSKR0_WEMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_WEMSK_SHIFT) & DDRPHY_BISTMSKR0_WEMSK_MASK) -#define DDRPHY_BISTMSKR0_WEMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_WEMSK_MASK) >> DDRPHY_BISTMSKR0_WEMSK_SHIFT) - -/* - * BAMSK (R/W) - * - * Mask bit for each of the up to 3 bank address bits. - */ -#define DDRPHY_BISTMSKR0_BAMSK_MASK (0x70000UL) -#define DDRPHY_BISTMSKR0_BAMSK_SHIFT (16U) -#define DDRPHY_BISTMSKR0_BAMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_BAMSK_SHIFT) & DDRPHY_BISTMSKR0_BAMSK_MASK) -#define DDRPHY_BISTMSKR0_BAMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_BAMSK_MASK) >> DDRPHY_BISTMSKR0_BAMSK_SHIFT) - -/* - * AMSK (R/W) - * - * Mask bit for each of the up to 16 address bits. - */ -#define DDRPHY_BISTMSKR0_AMSK_MASK (0xFFFFU) -#define DDRPHY_BISTMSKR0_AMSK_SHIFT (0U) -#define DDRPHY_BISTMSKR0_AMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR0_AMSK_SHIFT) & DDRPHY_BISTMSKR0_AMSK_MASK) -#define DDRPHY_BISTMSKR0_AMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR0_AMSK_MASK) >> DDRPHY_BISTMSKR0_AMSK_SHIFT) - -/* Bitfield definition for register: BISTMSKR1 */ -/* - * DMMSK (R/W) - * - * Mask bit for the data mask (DM) bit. - */ -#define DDRPHY_BISTMSKR1_DMMSK_MASK (0xF0000000UL) -#define DDRPHY_BISTMSKR1_DMMSK_SHIFT (28U) -#define DDRPHY_BISTMSKR1_DMMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_DMMSK_SHIFT) & DDRPHY_BISTMSKR1_DMMSK_MASK) -#define DDRPHY_BISTMSKR1_DMMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_DMMSK_MASK) >> DDRPHY_BISTMSKR1_DMMSK_SHIFT) - -/* - * PARMSK (R/W) - * - * Mask bit for the PAR_IN. Only for DIMM parity support and only if the design is compiled for less than 3 ranks. - */ -#define DDRPHY_BISTMSKR1_PARMSK_MASK (0x8000000UL) -#define DDRPHY_BISTMSKR1_PARMSK_SHIFT (27U) -#define DDRPHY_BISTMSKR1_PARMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_PARMSK_SHIFT) & DDRPHY_BISTMSKR1_PARMSK_MASK) -#define DDRPHY_BISTMSKR1_PARMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_PARMSK_MASK) >> DDRPHY_BISTMSKR1_PARMSK_SHIFT) - -/* - * CASMSK (R/W) - * - * Mask bit for the CAS. - */ -#define DDRPHY_BISTMSKR1_CASMSK_MASK (0x2U) -#define DDRPHY_BISTMSKR1_CASMSK_SHIFT (1U) -#define DDRPHY_BISTMSKR1_CASMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_CASMSK_SHIFT) & DDRPHY_BISTMSKR1_CASMSK_MASK) -#define DDRPHY_BISTMSKR1_CASMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_CASMSK_MASK) >> DDRPHY_BISTMSKR1_CASMSK_SHIFT) - -/* - * RASMSK (R/W) - * - * Mask bit for the RAS. - */ -#define DDRPHY_BISTMSKR1_RASMSK_MASK (0x1U) -#define DDRPHY_BISTMSKR1_RASMSK_SHIFT (0U) -#define DDRPHY_BISTMSKR1_RASMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR1_RASMSK_SHIFT) & DDRPHY_BISTMSKR1_RASMSK_MASK) -#define DDRPHY_BISTMSKR1_RASMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR1_RASMSK_MASK) >> DDRPHY_BISTMSKR1_RASMSK_SHIFT) - -/* Bitfield definition for register: BISTMSKR2 */ -/* - * DQMSK (R/W) - * - * Mask bit for each of the 8 data (DQ) bits. - */ -#define DDRPHY_BISTMSKR2_DQMSK_MASK (0xFFFFFFFFUL) -#define DDRPHY_BISTMSKR2_DQMSK_SHIFT (0U) -#define DDRPHY_BISTMSKR2_DQMSK_SET(x) (((uint32_t)(x) << DDRPHY_BISTMSKR2_DQMSK_SHIFT) & DDRPHY_BISTMSKR2_DQMSK_MASK) -#define DDRPHY_BISTMSKR2_DQMSK_GET(x) (((uint32_t)(x) & DDRPHY_BISTMSKR2_DQMSK_MASK) >> DDRPHY_BISTMSKR2_DQMSK_SHIFT) - -/* Bitfield definition for register: BISTLSR */ -/* - * SEED (R/W) - * - * LFSR seed for pseudo-random BIST patterns. - */ -#define DDRPHY_BISTLSR_SEED_MASK (0xFFFFFFFFUL) -#define DDRPHY_BISTLSR_SEED_SHIFT (0U) -#define DDRPHY_BISTLSR_SEED_SET(x) (((uint32_t)(x) << DDRPHY_BISTLSR_SEED_SHIFT) & DDRPHY_BISTLSR_SEED_MASK) -#define DDRPHY_BISTLSR_SEED_GET(x) (((uint32_t)(x) & DDRPHY_BISTLSR_SEED_MASK) >> DDRPHY_BISTLSR_SEED_SHIFT) - -/* Bitfield definition for register: BISTAR0 */ -/* - * BBANK (R/W) - * - * BIST Bank Address: Selects the SDRAM bank address to be used during BIST. - */ -#define DDRPHY_BISTAR0_BBANK_MASK (0x70000000UL) -#define DDRPHY_BISTAR0_BBANK_SHIFT (28U) -#define DDRPHY_BISTAR0_BBANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BBANK_SHIFT) & DDRPHY_BISTAR0_BBANK_MASK) -#define DDRPHY_BISTAR0_BBANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BBANK_MASK) >> DDRPHY_BISTAR0_BBANK_SHIFT) - -/* - * BROW (R/W) - * - * BIST Row Address: Selects the SDRAM row address to be used during BIST. - */ -#define DDRPHY_BISTAR0_BROW_MASK (0xFFFF000UL) -#define DDRPHY_BISTAR0_BROW_SHIFT (12U) -#define DDRPHY_BISTAR0_BROW_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BROW_SHIFT) & DDRPHY_BISTAR0_BROW_MASK) -#define DDRPHY_BISTAR0_BROW_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BROW_MASK) >> DDRPHY_BISTAR0_BROW_SHIFT) - -/* - * BCOL (R/W) - * - * BIST Column Address: Selects the SDRAM column address to be used during BIST. The lower bits of this address must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. - */ -#define DDRPHY_BISTAR0_BCOL_MASK (0xFFFU) -#define DDRPHY_BISTAR0_BCOL_SHIFT (0U) -#define DDRPHY_BISTAR0_BCOL_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR0_BCOL_SHIFT) & DDRPHY_BISTAR0_BCOL_MASK) -#define DDRPHY_BISTAR0_BCOL_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR0_BCOL_MASK) >> DDRPHY_BISTAR0_BCOL_SHIFT) - -/* Bitfield definition for register: BISTAR1 */ -/* - * BAINC (R/W) - * - * BIST Address Increment: Selects the value by which the SDRAM address is incremented for each write/read access. This value must be at the beginning of a burst boundary, i.e. the lower bits must be “0000” for BL16, “000” for BL8, “00” for BL4 and “0” for BL2. - */ -#define DDRPHY_BISTAR1_BAINC_MASK (0xFFF0U) -#define DDRPHY_BISTAR1_BAINC_SHIFT (4U) -#define DDRPHY_BISTAR1_BAINC_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BAINC_SHIFT) & DDRPHY_BISTAR1_BAINC_MASK) -#define DDRPHY_BISTAR1_BAINC_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BAINC_MASK) >> DDRPHY_BISTAR1_BAINC_SHIFT) - -/* - * BMRANK (R/W) - * - * BIST Maximum Rank: Specifies the maximum SDRAM rank to be used during BIST. The default value is set to maximum ranks minus 1. Example default shown here is for a 4-rank system - */ -#define DDRPHY_BISTAR1_BMRANK_MASK (0xCU) -#define DDRPHY_BISTAR1_BMRANK_SHIFT (2U) -#define DDRPHY_BISTAR1_BMRANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BMRANK_SHIFT) & DDRPHY_BISTAR1_BMRANK_MASK) -#define DDRPHY_BISTAR1_BMRANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BMRANK_MASK) >> DDRPHY_BISTAR1_BMRANK_SHIFT) - -/* - * BRANK (R/W) - * - * BIST Rank: Selects the SDRAM rank to be used during BIST. Valid values range from 0 to maximum ranks minus 1. - */ -#define DDRPHY_BISTAR1_BRANK_MASK (0x3U) -#define DDRPHY_BISTAR1_BRANK_SHIFT (0U) -#define DDRPHY_BISTAR1_BRANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR1_BRANK_SHIFT) & DDRPHY_BISTAR1_BRANK_MASK) -#define DDRPHY_BISTAR1_BRANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR1_BRANK_MASK) >> DDRPHY_BISTAR1_BRANK_SHIFT) - -/* Bitfield definition for register: BISTAR2 */ -/* - * BMBANK (R/W) - * - * BIST Maximum Bank Address: Specifies the maximum SDRAM bank address to be used during BIST before the address increments to the next rank. - */ -#define DDRPHY_BISTAR2_BMBANK_MASK (0x70000000UL) -#define DDRPHY_BISTAR2_BMBANK_SHIFT (28U) -#define DDRPHY_BISTAR2_BMBANK_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMBANK_SHIFT) & DDRPHY_BISTAR2_BMBANK_MASK) -#define DDRPHY_BISTAR2_BMBANK_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMBANK_MASK) >> DDRPHY_BISTAR2_BMBANK_SHIFT) - -/* - * BMROW (R/W) - * - * BIST Maximum Row Address: Specifies the maximum SDRAM row address to be used during BIST before the address increments to the next bank. - */ -#define DDRPHY_BISTAR2_BMROW_MASK (0xFFFF000UL) -#define DDRPHY_BISTAR2_BMROW_SHIFT (12U) -#define DDRPHY_BISTAR2_BMROW_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMROW_SHIFT) & DDRPHY_BISTAR2_BMROW_MASK) -#define DDRPHY_BISTAR2_BMROW_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMROW_MASK) >> DDRPHY_BISTAR2_BMROW_SHIFT) - -/* - * BMCOL (R/W) - * - * BIST Maximum Column Address: Specifies the maximum SDRAM column address to be used during BIST before the address increments to the next row. - */ -#define DDRPHY_BISTAR2_BMCOL_MASK (0xFFFU) -#define DDRPHY_BISTAR2_BMCOL_SHIFT (0U) -#define DDRPHY_BISTAR2_BMCOL_SET(x) (((uint32_t)(x) << DDRPHY_BISTAR2_BMCOL_SHIFT) & DDRPHY_BISTAR2_BMCOL_MASK) -#define DDRPHY_BISTAR2_BMCOL_GET(x) (((uint32_t)(x) & DDRPHY_BISTAR2_BMCOL_MASK) >> DDRPHY_BISTAR2_BMCOL_SHIFT) - -/* Bitfield definition for register: BISTUDPR */ -/* - * BUDP1 (R/W) - * - * BIST User Data Pattern 1: Data to be applied on odd DQ pins during BIST. - */ -#define DDRPHY_BISTUDPR_BUDP1_MASK (0xFFFF0000UL) -#define DDRPHY_BISTUDPR_BUDP1_SHIFT (16U) -#define DDRPHY_BISTUDPR_BUDP1_SET(x) (((uint32_t)(x) << DDRPHY_BISTUDPR_BUDP1_SHIFT) & DDRPHY_BISTUDPR_BUDP1_MASK) -#define DDRPHY_BISTUDPR_BUDP1_GET(x) (((uint32_t)(x) & DDRPHY_BISTUDPR_BUDP1_MASK) >> DDRPHY_BISTUDPR_BUDP1_SHIFT) - -/* - * BUDP0 (R/W) - * - * BIST User Data Pattern 0: Data to be applied on even DQ pins during BIST. - */ -#define DDRPHY_BISTUDPR_BUDP0_MASK (0xFFFFU) -#define DDRPHY_BISTUDPR_BUDP0_SHIFT (0U) -#define DDRPHY_BISTUDPR_BUDP0_SET(x) (((uint32_t)(x) << DDRPHY_BISTUDPR_BUDP0_SHIFT) & DDRPHY_BISTUDPR_BUDP0_MASK) -#define DDRPHY_BISTUDPR_BUDP0_GET(x) (((uint32_t)(x) & DDRPHY_BISTUDPR_BUDP0_MASK) >> DDRPHY_BISTUDPR_BUDP0_SHIFT) - -/* Bitfield definition for register: BISTGSR */ -/* - * CASBER (R) - * - * CAS Bit Error: Indicates the number of bit errors on CAS. - */ -#define DDRPHY_BISTGSR_CASBER_MASK (0xC0000000UL) -#define DDRPHY_BISTGSR_CASBER_SHIFT (30U) -#define DDRPHY_BISTGSR_CASBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_CASBER_MASK) >> DDRPHY_BISTGSR_CASBER_SHIFT) - -/* - * RASBER (R) - * - * RAS Bit Error: Indicates the number of bit errors on RAS. - */ -#define DDRPHY_BISTGSR_RASBER_MASK (0x30000000UL) -#define DDRPHY_BISTGSR_RASBER_SHIFT (28U) -#define DDRPHY_BISTGSR_RASBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_RASBER_MASK) >> DDRPHY_BISTGSR_RASBER_SHIFT) - -/* - * DMBER (R) - * - * DM Bit Error: Indicates the number of bit errors on data mask (DM) bit. DMBER[1:0] are for even DQS cycles first DM beat, and DMBER[3:2] are for even DQS cycles second DM beat. Similarly, DMBER[5:4] are for odd DQS cycles first DM beat, and DMBER[7:6] are for odd DQS cycles second DM beat. - */ -#define DDRPHY_BISTGSR_DMBER_MASK (0xFF00000UL) -#define DDRPHY_BISTGSR_DMBER_SHIFT (20U) -#define DDRPHY_BISTGSR_DMBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_DMBER_MASK) >> DDRPHY_BISTGSR_DMBER_SHIFT) - -/* - * PARBER (R) - * - * PAR_IN Bit Error (DIMM Only): Indicates the number of bit errors on PAR_IN - */ -#define DDRPHY_BISTGSR_PARBER_MASK (0x30000UL) -#define DDRPHY_BISTGSR_PARBER_SHIFT (16U) -#define DDRPHY_BISTGSR_PARBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_PARBER_MASK) >> DDRPHY_BISTGSR_PARBER_SHIFT) - -/* - * BDXERR (R) - * - * BIST Data Error: indicates, if set, that there is a data comparison error in the byte lane. - */ -#define DDRPHY_BISTGSR_BDXERR_MASK (0x4U) -#define DDRPHY_BISTGSR_BDXERR_SHIFT (2U) -#define DDRPHY_BISTGSR_BDXERR_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BDXERR_MASK) >> DDRPHY_BISTGSR_BDXERR_SHIFT) - -/* - * BACERR (R) - * - * BIST Address/Command Error: indicates, if set, that there is a data comparison error in the address/command lane. - */ -#define DDRPHY_BISTGSR_BACERR_MASK (0x2U) -#define DDRPHY_BISTGSR_BACERR_SHIFT (1U) -#define DDRPHY_BISTGSR_BACERR_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BACERR_MASK) >> DDRPHY_BISTGSR_BACERR_SHIFT) - -/* - * BDONE (R) - * - * BIST Done: Indicates, if set, that the BIST has finished executing. This bit is reset to zero when BIST is triggered. - */ -#define DDRPHY_BISTGSR_BDONE_MASK (0x1U) -#define DDRPHY_BISTGSR_BDONE_SHIFT (0U) -#define DDRPHY_BISTGSR_BDONE_GET(x) (((uint32_t)(x) & DDRPHY_BISTGSR_BDONE_MASK) >> DDRPHY_BISTGSR_BDONE_SHIFT) - -/* Bitfield definition for register: BISTWER */ -/* - * DXWER (R) - * - * Byte Word Error: Indicates the number of word errors on the byte lane. An error on any bit of the data bus including the data mask bit increments the error count. - */ -#define DDRPHY_BISTWER_DXWER_MASK (0xFFFF0000UL) -#define DDRPHY_BISTWER_DXWER_SHIFT (16U) -#define DDRPHY_BISTWER_DXWER_GET(x) (((uint32_t)(x) & DDRPHY_BISTWER_DXWER_MASK) >> DDRPHY_BISTWER_DXWER_SHIFT) - -/* - * ACWER (R) - * - * Address/Command Word Error: Indicates the number of word errors on the address/command lane. An error on any bit of the address/command bus increments the error count. - */ -#define DDRPHY_BISTWER_ACWER_MASK (0xFFFFU) -#define DDRPHY_BISTWER_ACWER_SHIFT (0U) -#define DDRPHY_BISTWER_ACWER_GET(x) (((uint32_t)(x) & DDRPHY_BISTWER_ACWER_MASK) >> DDRPHY_BISTWER_ACWER_SHIFT) - -/* Bitfield definition for register: BISTBER0 */ -/* - * ABER (R) - * - * Address Bit Error: Each group of two bits indicate the bit error count on each of the - */ -#define DDRPHY_BISTBER0_ABER_MASK (0xFFFFFFFFUL) -#define DDRPHY_BISTBER0_ABER_SHIFT (0U) -#define DDRPHY_BISTBER0_ABER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER0_ABER_MASK) >> DDRPHY_BISTBER0_ABER_SHIFT) - -/* Bitfield definition for register: BISTBER1 */ -/* - * ODTBER (R) - * - * ODT Bit Error: Each group of two bits indicates the bit error count on each of the up to 4 ODT bits. [1:0] is the error count for ODT[0], [3:2] for ODT[1], and so on. - */ -#define DDRPHY_BISTBER1_ODTBER_MASK (0xFF000000UL) -#define DDRPHY_BISTBER1_ODTBER_SHIFT (24U) -#define DDRPHY_BISTBER1_ODTBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_ODTBER_MASK) >> DDRPHY_BISTBER1_ODTBER_SHIFT) - -/* - * CSBER (R) - * - * CS# Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CS# bits. [1:0] is the error count for CS#[0], [3:2] for CS#[1], and so on. - */ -#define DDRPHY_BISTBER1_CSBER_MASK (0xFF0000UL) -#define DDRPHY_BISTBER1_CSBER_SHIFT (16U) -#define DDRPHY_BISTBER1_CSBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_CSBER_MASK) >> DDRPHY_BISTBER1_CSBER_SHIFT) - -/* - * CKEBER (R) - * - * CKE Bit Error: Each group of two bits indicate the bit error count on each of the up to 4 CKE bits. [1:0] is the error count for CKE[0], [3:2] for CKE[1], and so on. - */ -#define DDRPHY_BISTBER1_CKEBER_MASK (0xFF00U) -#define DDRPHY_BISTBER1_CKEBER_SHIFT (8U) -#define DDRPHY_BISTBER1_CKEBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_CKEBER_MASK) >> DDRPHY_BISTBER1_CKEBER_SHIFT) - -/* - * WEBER (R) - * - * WE# Bit Error: Indicates the number of bit errors on WE#. - */ -#define DDRPHY_BISTBER1_WEBER_MASK (0xC0U) -#define DDRPHY_BISTBER1_WEBER_SHIFT (6U) -#define DDRPHY_BISTBER1_WEBER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_WEBER_MASK) >> DDRPHY_BISTBER1_WEBER_SHIFT) - -/* - * BABER (R) - * - * Bank Address Bit Error: Each group of two bits indicate the bit error count on each of the up to 3 bank address bits. [1:0] is the error count for BA[0], [3:2] for BA[1], and so on. - */ -#define DDRPHY_BISTBER1_BABER_MASK (0x3FU) -#define DDRPHY_BISTBER1_BABER_SHIFT (0U) -#define DDRPHY_BISTBER1_BABER_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER1_BABER_MASK) >> DDRPHY_BISTBER1_BABER_SHIFT) - -/* Bitfield definition for register: BISTBER2 */ -/* - * DQBER0 (R) - * - * Data Bit Error: The error count for even DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. - */ -#define DDRPHY_BISTBER2_DQBER0_MASK (0xFFFFFFFFUL) -#define DDRPHY_BISTBER2_DQBER0_SHIFT (0U) -#define DDRPHY_BISTBER2_DQBER0_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER2_DQBER0_MASK) >> DDRPHY_BISTBER2_DQBER0_SHIFT) - -/* Bitfield definition for register: BISTBER3 */ -/* - * DQBER1 (R) - * - * Data Bit Error: The error count for odd DQS cycles. The first 16 bits indicate the error count for the first data beat (i.e. the data driven out on DQ[7:0] on the rising edge of DQS). The second 16 bits indicate the error on the second data beat (i.e. the error count of the data driven out on DQ[7:0] on the falling edge of DQS). For each of the 16-bit group, the first 2 bits are for DQ[0], the second for DQ[1], and so on. - */ -#define DDRPHY_BISTBER3_DQBER1_MASK (0xFFFFFFFFUL) -#define DDRPHY_BISTBER3_DQBER1_SHIFT (0U) -#define DDRPHY_BISTBER3_DQBER1_GET(x) (((uint32_t)(x) & DDRPHY_BISTBER3_DQBER1_MASK) >> DDRPHY_BISTBER3_DQBER1_SHIFT) - -/* Bitfield definition for register: BISTWCSR */ -/* - * DXWCNT (R) - * - * Byte Word Count: Indicates the number of words received from the byte lane. - */ -#define DDRPHY_BISTWCSR_DXWCNT_MASK (0xFFFF0000UL) -#define DDRPHY_BISTWCSR_DXWCNT_SHIFT (16U) -#define DDRPHY_BISTWCSR_DXWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCSR_DXWCNT_MASK) >> DDRPHY_BISTWCSR_DXWCNT_SHIFT) - -/* - * ACWCNT (R) - * - * Address/Command Word Count: Indicates the number of words received from the address/command lane. - */ -#define DDRPHY_BISTWCSR_ACWCNT_MASK (0xFFFFU) -#define DDRPHY_BISTWCSR_ACWCNT_SHIFT (0U) -#define DDRPHY_BISTWCSR_ACWCNT_GET(x) (((uint32_t)(x) & DDRPHY_BISTWCSR_ACWCNT_MASK) >> DDRPHY_BISTWCSR_ACWCNT_SHIFT) - -/* Bitfield definition for register: BISTFWR0 */ -/* - * ODTWEBS (R) - * - * Bit status during a word error for each of the up to 4 ODT bits. - */ -#define DDRPHY_BISTFWR0_ODTWEBS_MASK (0xF0000000UL) -#define DDRPHY_BISTFWR0_ODTWEBS_SHIFT (28U) -#define DDRPHY_BISTFWR0_ODTWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_ODTWEBS_MASK) >> DDRPHY_BISTFWR0_ODTWEBS_SHIFT) - -/* - * CSWEBS (R) - * - * Bit status during a word error for each of the up to 4 CS# bits. - */ -#define DDRPHY_BISTFWR0_CSWEBS_MASK (0xF000000UL) -#define DDRPHY_BISTFWR0_CSWEBS_SHIFT (24U) -#define DDRPHY_BISTFWR0_CSWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_CSWEBS_MASK) >> DDRPHY_BISTFWR0_CSWEBS_SHIFT) - -/* - * CKEWEBS (R) - * - * Bit status during a word error for each of the up to 4 CKE bits. - */ -#define DDRPHY_BISTFWR0_CKEWEBS_MASK (0xF00000UL) -#define DDRPHY_BISTFWR0_CKEWEBS_SHIFT (20U) -#define DDRPHY_BISTFWR0_CKEWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_CKEWEBS_MASK) >> DDRPHY_BISTFWR0_CKEWEBS_SHIFT) - -/* - * WEWEBS (R) - * - * Bit status during a word error for the WE#. - */ -#define DDRPHY_BISTFWR0_WEWEBS_MASK (0x80000UL) -#define DDRPHY_BISTFWR0_WEWEBS_SHIFT (19U) -#define DDRPHY_BISTFWR0_WEWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_WEWEBS_MASK) >> DDRPHY_BISTFWR0_WEWEBS_SHIFT) - -/* - * BAWEBS (R) - * - * Bit status during a word error for each of the up to 3 bank address bits. - */ -#define DDRPHY_BISTFWR0_BAWEBS_MASK (0x70000UL) -#define DDRPHY_BISTFWR0_BAWEBS_SHIFT (16U) -#define DDRPHY_BISTFWR0_BAWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_BAWEBS_MASK) >> DDRPHY_BISTFWR0_BAWEBS_SHIFT) - -/* - * AWEBS (R) - * - * Bit status during a word error for each of the up to 16 address bits. - */ -#define DDRPHY_BISTFWR0_AWEBS_MASK (0xFFFFU) -#define DDRPHY_BISTFWR0_AWEBS_SHIFT (0U) -#define DDRPHY_BISTFWR0_AWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR0_AWEBS_MASK) >> DDRPHY_BISTFWR0_AWEBS_SHIFT) - -/* Bitfield definition for register: BISTFWR1 */ -/* - * DMWEBS (R) - * - * Bit status during a word error for the data mask (DM) bit. DMWEBS [0] is for the first DM beat, DMWEBS [1] is for the second DM beat, and so on. - */ -#define DDRPHY_BISTFWR1_DMWEBS_MASK (0xF0000000UL) -#define DDRPHY_BISTFWR1_DMWEBS_SHIFT (28U) -#define DDRPHY_BISTFWR1_DMWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_DMWEBS_MASK) >> DDRPHY_BISTFWR1_DMWEBS_SHIFT) - -/* - * PARWEBS (R) - * - * Bit status during a word error for the PAR_IN. Only for DIMM parity support - */ -#define DDRPHY_BISTFWR1_PARWEBS_MASK (0x4000000UL) -#define DDRPHY_BISTFWR1_PARWEBS_SHIFT (26U) -#define DDRPHY_BISTFWR1_PARWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_PARWEBS_MASK) >> DDRPHY_BISTFWR1_PARWEBS_SHIFT) - -/* - * CASWEBS (R) - * - * Bit status during a word error for the CAS. - */ -#define DDRPHY_BISTFWR1_CASWEBS_MASK (0x2U) -#define DDRPHY_BISTFWR1_CASWEBS_SHIFT (1U) -#define DDRPHY_BISTFWR1_CASWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_CASWEBS_MASK) >> DDRPHY_BISTFWR1_CASWEBS_SHIFT) - -/* - * RASWEBS (R) - * - * Bit status during a word error for the RAS. - */ -#define DDRPHY_BISTFWR1_RASWEBS_MASK (0x1U) -#define DDRPHY_BISTFWR1_RASWEBS_SHIFT (0U) -#define DDRPHY_BISTFWR1_RASWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR1_RASWEBS_MASK) >> DDRPHY_BISTFWR1_RASWEBS_SHIFT) - -/* Bitfield definition for register: BISTFWR2 */ -/* - * DQWEBS (R) - * - * Bit status during a word error for each of the 8 data (DQ) bits. The first 8 bits indicate the status of the first data beat (i.e. the status of the data driven out on DQ[7:0] on the rising edge of DQS). The second 8 bits indicate the status of the second data beat (i.e. the status of the data driven out on DQ[7:0] on the falling edge of DQS), and so on. For each of the 8-bit group, the first bit is for DQ[0], the second bit is for DQ[1], and so on. - */ -#define DDRPHY_BISTFWR2_DQWEBS_MASK (0xFFFFFFFFUL) -#define DDRPHY_BISTFWR2_DQWEBS_SHIFT (0U) -#define DDRPHY_BISTFWR2_DQWEBS_GET(x) (((uint32_t)(x) & DDRPHY_BISTFWR2_DQWEBS_MASK) >> DDRPHY_BISTFWR2_DQWEBS_SHIFT) - -/* Bitfield definition for register: AACR */ -/* - * AAOENC (R/W) - * - * Anti-Aging PAD Output Enable Control: Enables, if set, anti-aging toggling on the pad output enable signal “ctl_oe_n” going into the DATX8s. This will increase power consumption for the anti-aging feature. - */ -#define DDRPHY_AACR_AAOENC_MASK (0x80000000UL) -#define DDRPHY_AACR_AAOENC_SHIFT (31U) -#define DDRPHY_AACR_AAOENC_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AAOENC_SHIFT) & DDRPHY_AACR_AAOENC_MASK) -#define DDRPHY_AACR_AAOENC_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AAOENC_MASK) >> DDRPHY_AACR_AAOENC_SHIFT) - -/* - * AAENC (R/W) - * - * Anti-Aging Enable Control: Enables, if set, the automatic toggling of the data going to the DATX8 when the data channel from the controller/PUB to DATX8 is idle for programmable number of clock cycles. - */ -#define DDRPHY_AACR_AAENC_MASK (0x40000000UL) -#define DDRPHY_AACR_AAENC_SHIFT (30U) -#define DDRPHY_AACR_AAENC_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AAENC_SHIFT) & DDRPHY_AACR_AAENC_MASK) -#define DDRPHY_AACR_AAENC_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AAENC_MASK) >> DDRPHY_AACR_AAENC_SHIFT) - -/* - * AATR (R/W) - * - * Anti-Aging Toggle Rate: Defines the number of controller clock (ctl_clk) cycles after which the PUB will toggle the data going to DATX8 if the data channel between the controller/PUB and DATX8 has been idle for this long. - * The default value correspond to a toggling count of 4096 ctl_clk cycles. For a ctl_clk running at 533MHz the toggle rate will be approximately 7.68us. - * The default value may also be overridden by the macro DWC_AACR_AATR_DFLT. - */ -#define DDRPHY_AACR_AATR_MASK (0x3FFFFFFFUL) -#define DDRPHY_AACR_AATR_SHIFT (0U) -#define DDRPHY_AACR_AATR_SET(x) (((uint32_t)(x) << DDRPHY_AACR_AATR_SHIFT) & DDRPHY_AACR_AATR_MASK) -#define DDRPHY_AACR_AATR_GET(x) (((uint32_t)(x) & DDRPHY_AACR_AATR_MASK) >> DDRPHY_AACR_AATR_SHIFT) - -/* Bitfield definition for register: GPR0 */ -/* - * GPR0 (R/W) - * - * General Purpose Register 0: General purpose register bits. - */ -#define DDRPHY_GPR0_GPR0_MASK (0xFFFFFFFFUL) -#define DDRPHY_GPR0_GPR0_SHIFT (0U) -#define DDRPHY_GPR0_GPR0_SET(x) (((uint32_t)(x) << DDRPHY_GPR0_GPR0_SHIFT) & DDRPHY_GPR0_GPR0_MASK) -#define DDRPHY_GPR0_GPR0_GET(x) (((uint32_t)(x) & DDRPHY_GPR0_GPR0_MASK) >> DDRPHY_GPR0_GPR0_SHIFT) - -/* Bitfield definition for register: GPR1 */ -/* - * GPR1 (R/W) - * - * General Purpose Register 1: General purpose register bits. - */ -#define DDRPHY_GPR1_GPR1_MASK (0xFFFFFFFFUL) -#define DDRPHY_GPR1_GPR1_SHIFT (0U) -#define DDRPHY_GPR1_GPR1_SET(x) (((uint32_t)(x) << DDRPHY_GPR1_GPR1_SHIFT) & DDRPHY_GPR1_GPR1_MASK) -#define DDRPHY_GPR1_GPR1_GET(x) (((uint32_t)(x) & DDRPHY_GPR1_GPR1_MASK) >> DDRPHY_GPR1_GPR1_SHIFT) - -/* Bitfield definition for register of struct array ZQ: CR0 */ -/* - * ZQPD (R/W) - * - * ZQ Power Down: Powers down, if set, the PZQ cell. - */ -#define DDRPHY_ZQ_CR0_ZQPD_MASK (0x80000000UL) -#define DDRPHY_ZQ_CR0_ZQPD_SHIFT (31U) -#define DDRPHY_ZQ_CR0_ZQPD_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZQPD_SHIFT) & DDRPHY_ZQ_CR0_ZQPD_MASK) -#define DDRPHY_ZQ_CR0_ZQPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZQPD_MASK) >> DDRPHY_ZQ_CR0_ZQPD_SHIFT) - -/* - * ZCALEN (R/W) - * - * Impedance Calibration Enable: Enables, if set, the impedance calibration of this ZQ control block when impedance calibration is triggered using either the ZCAL bit of PIR register or the DFI update interface. - */ -#define DDRPHY_ZQ_CR0_ZCALEN_MASK (0x40000000UL) -#define DDRPHY_ZQ_CR0_ZCALEN_SHIFT (30U) -#define DDRPHY_ZQ_CR0_ZCALEN_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZCALEN_SHIFT) & DDRPHY_ZQ_CR0_ZCALEN_MASK) -#define DDRPHY_ZQ_CR0_ZCALEN_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZCALEN_MASK) >> DDRPHY_ZQ_CR0_ZCALEN_SHIFT) - -/* - * ZCALBYP (R/W) - * - * Impedance Calibration Bypass: Bypasses, if set, impedance calibration of this ZQ control block when impedance calibration is already in progress. Impedance calibration can be disabled prior to trigger by using the ZCALEN bit. - */ -#define DDRPHY_ZQ_CR0_ZCALBYP_MASK (0x20000000UL) -#define DDRPHY_ZQ_CR0_ZCALBYP_SHIFT (29U) -#define DDRPHY_ZQ_CR0_ZCALBYP_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZCALBYP_SHIFT) & DDRPHY_ZQ_CR0_ZCALBYP_MASK) -#define DDRPHY_ZQ_CR0_ZCALBYP_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZCALBYP_MASK) >> DDRPHY_ZQ_CR0_ZCALBYP_SHIFT) - -/* - * ZDEN (R/W) - * - * Impedance Over-ride Enable: When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZDATA field. Otherwise, the control is generated automatically by the impedance control logic. - */ -#define DDRPHY_ZQ_CR0_ZDEN_MASK (0x10000000UL) -#define DDRPHY_ZQ_CR0_ZDEN_SHIFT (28U) -#define DDRPHY_ZQ_CR0_ZDEN_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZDEN_SHIFT) & DDRPHY_ZQ_CR0_ZDEN_MASK) -#define DDRPHY_ZQ_CR0_ZDEN_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZDEN_MASK) >> DDRPHY_ZQ_CR0_ZDEN_SHIFT) - -/* - * ZDATA (R/W) - * - * Impedance Over-Ride Data: Data used to directly drive the impedance control. - * ZDATA field mapping for D3F I/Os is as follows: - * ZDATA[27:21] is used to select the pull-up on-die termination impedance ZDATA[20:14] is used to select the pull-down on-die termination impedance ZDATA[13:7] is used to select the pull-up output impedance - * ZDATA[6:0] is used to select the pull-down output impedance - * ZDATA field mapping for D3A/B/R I/Os is as follows: ZDATA[27:20] is reserved and returns zeros on reads - * ZDATA[19:15] is used to select the pull-up on-die termination impedance ZDATA[14:10] is used to select the pull-down on-die termination impedance ZDATA[9:5] is used to select the pull-up output impedance - * ZDATA[4:0] is used to select the pull-down output impedance - * The default value is 0x000014A for I/O type D3C/R and 0x0001830 for I/O type D3F. - */ -#define DDRPHY_ZQ_CR0_ZDATA_MASK (0xFFFFFFFUL) -#define DDRPHY_ZQ_CR0_ZDATA_SHIFT (0U) -#define DDRPHY_ZQ_CR0_ZDATA_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR0_ZDATA_SHIFT) & DDRPHY_ZQ_CR0_ZDATA_MASK) -#define DDRPHY_ZQ_CR0_ZDATA_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR0_ZDATA_MASK) >> DDRPHY_ZQ_CR0_ZDATA_SHIFT) - -/* Bitfield definition for register of struct array ZQ: CR1 */ -/* - * DFIPU1 (R/W) - * - * DFI Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. - */ -#define DDRPHY_ZQ_CR1_DFIPU1_MASK (0x20000UL) -#define DDRPHY_ZQ_CR1_DFIPU1_SHIFT (17U) -#define DDRPHY_ZQ_CR1_DFIPU1_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFIPU1_SHIFT) & DDRPHY_ZQ_CR1_DFIPU1_MASK) -#define DDRPHY_ZQ_CR1_DFIPU1_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFIPU1_MASK) >> DDRPHY_ZQ_CR1_DFIPU1_SHIFT) - -/* - * DFIPU0 (R/W) - * - * DFI Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI PHY update interface 0 (channel 0) requests an update. - */ -#define DDRPHY_ZQ_CR1_DFIPU0_MASK (0x10000UL) -#define DDRPHY_ZQ_CR1_DFIPU0_SHIFT (16U) -#define DDRPHY_ZQ_CR1_DFIPU0_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFIPU0_SHIFT) & DDRPHY_ZQ_CR1_DFIPU0_MASK) -#define DDRPHY_ZQ_CR1_DFIPU0_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFIPU0_MASK) >> DDRPHY_ZQ_CR1_DFIPU0_SHIFT) - -/* - * DFICCU (R/W) - * - * DFI Concurrent Controller Update Interface: Sets this impedance controller to be enabled for calibration when both of the DFI controller update interfaces request an update on the same clock. This provides the ability to enable impedance calibration updates for the Address/Command lane. Only valid in shared-AC mode. - */ -#define DDRPHY_ZQ_CR1_DFICCU_MASK (0x4000U) -#define DDRPHY_ZQ_CR1_DFICCU_SHIFT (14U) -#define DDRPHY_ZQ_CR1_DFICCU_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICCU_SHIFT) & DDRPHY_ZQ_CR1_DFICCU_MASK) -#define DDRPHY_ZQ_CR1_DFICCU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICCU_MASK) >> DDRPHY_ZQ_CR1_DFICCU_SHIFT) - -/* - * DFICU1 (R/W) - * - * DFI Controller Update Interface 1: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 1 (channel 1) requests an update. Only valid in shared-AC mode. - */ -#define DDRPHY_ZQ_CR1_DFICU1_MASK (0x2000U) -#define DDRPHY_ZQ_CR1_DFICU1_SHIFT (13U) -#define DDRPHY_ZQ_CR1_DFICU1_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICU1_SHIFT) & DDRPHY_ZQ_CR1_DFICU1_MASK) -#define DDRPHY_ZQ_CR1_DFICU1_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICU1_MASK) >> DDRPHY_ZQ_CR1_DFICU1_SHIFT) - -/* - * DFICU0 (R/W) - * - * DFI Controller Update Interface 0: Sets this impedance controller to be enabled for calibration when the DFI controller update interface 0 (channel 0) requests an update. - */ -#define DDRPHY_ZQ_CR1_DFICU0_MASK (0x1000U) -#define DDRPHY_ZQ_CR1_DFICU0_SHIFT (12U) -#define DDRPHY_ZQ_CR1_DFICU0_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_DFICU0_SHIFT) & DDRPHY_ZQ_CR1_DFICU0_MASK) -#define DDRPHY_ZQ_CR1_DFICU0_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_DFICU0_MASK) >> DDRPHY_ZQ_CR1_DFICU0_SHIFT) - -/* - * ZPROG (R/W) - * - * Impedance Divide Ratio: Selects the external resistor divide ratio to be used to set the output impedance and the on-die termination as follows: - * ZPROG[7:4] = On-die termination divide select ZPROG[3:0] = Output impedance divide select - */ -#define DDRPHY_ZQ_CR1_ZPROG_MASK (0xFFU) -#define DDRPHY_ZQ_CR1_ZPROG_SHIFT (0U) -#define DDRPHY_ZQ_CR1_ZPROG_SET(x) (((uint32_t)(x) << DDRPHY_ZQ_CR1_ZPROG_SHIFT) & DDRPHY_ZQ_CR1_ZPROG_MASK) -#define DDRPHY_ZQ_CR1_ZPROG_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_CR1_ZPROG_MASK) >> DDRPHY_ZQ_CR1_ZPROG_SHIFT) - -/* Bitfield definition for register of struct array ZQ: SR0 */ -/* - * ZDONE (R) - * - * Impedance Calibration Done: Indicates that impedance calibration has completed. - */ -#define DDRPHY_ZQ_SR0_ZDONE_MASK (0x80000000UL) -#define DDRPHY_ZQ_SR0_ZDONE_SHIFT (31U) -#define DDRPHY_ZQ_SR0_ZDONE_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZDONE_MASK) >> DDRPHY_ZQ_SR0_ZDONE_SHIFT) - -/* - * ZERR (R) - * - * Impedance Calibration Error: If set, indicates that there was an error during impedance calibration. - */ -#define DDRPHY_ZQ_SR0_ZERR_MASK (0x40000000UL) -#define DDRPHY_ZQ_SR0_ZERR_SHIFT (30U) -#define DDRPHY_ZQ_SR0_ZERR_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZERR_MASK) >> DDRPHY_ZQ_SR0_ZERR_SHIFT) - -/* - * ZCTRL (R) - * - * Impedance Control: Current value of impedance control. ZCTRL field mapping for D3F I/Os is as follows: - * ZCTRL[27:21] is used to select the pull-up on-die termination impedance ZCTRL[20:14] is used to select the pull-down on-die termination impedance ZCTRL[13:7] is used to select the pull-up output impedance - * ZCTRL[6:0] is used to select the pull-down output impedance - * ZCTRL field mapping for D3A/B/R I/Os is as follows: ZCTRL[27:20] is reserved and returns zeros on reads - * ZCTRL[19:15] is used to select the pull-up on-die termination impedance ZCTRL[14:10] is used to select the pull-down on-die termination impedance ZCTRL[9:5] is used to select the pull-up output impedance - * ZCTRL[4:0] is used to select the pull-down output impedance - * Note: The default value is 0x000014A for I/O type D3C/D3R and 0x0001839 for I/O type D3F. - */ -#define DDRPHY_ZQ_SR0_ZCTRL_MASK (0xFFFFFFFUL) -#define DDRPHY_ZQ_SR0_ZCTRL_SHIFT (0U) -#define DDRPHY_ZQ_SR0_ZCTRL_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR0_ZCTRL_MASK) >> DDRPHY_ZQ_SR0_ZCTRL_SHIFT) - -/* Bitfield definition for register of struct array ZQ: SR1 */ -/* - * OPU (R) - * - * On-die termination (ODT) pull-up calibration status. Similar status encodings as ZPD. - */ -#define DDRPHY_ZQ_SR1_OPU_MASK (0xC0U) -#define DDRPHY_ZQ_SR1_OPU_SHIFT (6U) -#define DDRPHY_ZQ_SR1_OPU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_OPU_MASK) >> DDRPHY_ZQ_SR1_OPU_SHIFT) - -/* - * OPD (R) - * - * On-die termination (ODT) pull-down calibration status. Similar status encodings as ZPD. - */ -#define DDRPHY_ZQ_SR1_OPD_MASK (0x30U) -#define DDRPHY_ZQ_SR1_OPD_SHIFT (4U) -#define DDRPHY_ZQ_SR1_OPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_OPD_MASK) >> DDRPHY_ZQ_SR1_OPD_SHIFT) - -/* - * ZPU (R) - * - * Output impedance pull-up calibration status. Similar status encodings as ZPD. - */ -#define DDRPHY_ZQ_SR1_ZPU_MASK (0xCU) -#define DDRPHY_ZQ_SR1_ZPU_SHIFT (2U) -#define DDRPHY_ZQ_SR1_ZPU_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_ZPU_MASK) >> DDRPHY_ZQ_SR1_ZPU_SHIFT) - -/* - * ZPD (R) - * - * Output impedance pull-down calibration status. Valid status encodings are: 00 = Completed with no errors - * 01 = Overflow error 10 = Underflow error - * 11 = Calibration in progress - */ -#define DDRPHY_ZQ_SR1_ZPD_MASK (0x3U) -#define DDRPHY_ZQ_SR1_ZPD_SHIFT (0U) -#define DDRPHY_ZQ_SR1_ZPD_GET(x) (((uint32_t)(x) & DDRPHY_ZQ_SR1_ZPD_MASK) >> DDRPHY_ZQ_SR1_ZPD_SHIFT) - -/* Bitfield definition for register of struct array DX: GCR */ -/* - * CALBYP (R/W) - * - * Calibration Bypass: Prevents, if set, period measurement calibration from automatically triggering after PHY initialization. - */ -#define DDRPHY_DX_GCR_CALBYP_MASK (0x80000000UL) -#define DDRPHY_DX_GCR_CALBYP_SHIFT (31U) -#define DDRPHY_DX_GCR_CALBYP_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_CALBYP_SHIFT) & DDRPHY_DX_GCR_CALBYP_MASK) -#define DDRPHY_DX_GCR_CALBYP_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_CALBYP_MASK) >> DDRPHY_DX_GCR_CALBYP_SHIFT) - -/* - * MDLEN (R/W) - * - * Master Delay Line Enable: Enables, if set, the DATX8 master delay line calibration to perform subsequent period measurements following the initial period measurements that are performed after reset or when calibration is manually triggered. These additional measurements are accumulated and filtered as long as this bit remains high. This bit is ANDed with the common DATX8 MDL enable bit. - */ -#define DDRPHY_DX_GCR_MDLEN_MASK (0x40000000UL) -#define DDRPHY_DX_GCR_MDLEN_SHIFT (30U) -#define DDRPHY_DX_GCR_MDLEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_MDLEN_SHIFT) & DDRPHY_DX_GCR_MDLEN_MASK) -#define DDRPHY_DX_GCR_MDLEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_MDLEN_MASK) >> DDRPHY_DX_GCR_MDLEN_SHIFT) - -/* - * WLRKEN (R/W) - * - * Write Level Rank Enable: Specifies the ranks that should be write leveled for this byte. Write leveling responses from ranks that are not enabled for write leveling for a particular byte are ignored and write leveling is flagged as done for these ranks. - * WLRKEN[0] enables rank 0, [1] enables rank 1, [2] enables rank 2, and [3] enables - * rank 3. - */ -#define DDRPHY_DX_GCR_WLRKEN_MASK (0x3C000000UL) -#define DDRPHY_DX_GCR_WLRKEN_SHIFT (26U) -#define DDRPHY_DX_GCR_WLRKEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_WLRKEN_SHIFT) & DDRPHY_DX_GCR_WLRKEN_MASK) -#define DDRPHY_DX_GCR_WLRKEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_WLRKEN_MASK) >> DDRPHY_DX_GCR_WLRKEN_SHIFT) - -/* - * PLLBYP (R/W) - * - * PLL Bypass: Puts the byte PLL in bypass mode by driving the PLL bypass pin. This bit is not self-clearing and a '0' must be written to de-assert the bypass. This bit is ORed with the global BYP configuration bit (see Table 3-10 on page 91). - */ -#define DDRPHY_DX_GCR_PLLBYP_MASK (0x80000UL) -#define DDRPHY_DX_GCR_PLLBYP_SHIFT (19U) -#define DDRPHY_DX_GCR_PLLBYP_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLBYP_SHIFT) & DDRPHY_DX_GCR_PLLBYP_MASK) -#define DDRPHY_DX_GCR_PLLBYP_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLBYP_MASK) >> DDRPHY_DX_GCR_PLLBYP_SHIFT) - -/* - * GSHIFT (R/W) - * - * Gear Shift: Enables, if set, rapid locking mode on the byte PLL. This bit is ORed with the global GSHIFT configuration bit (see Table 3-10 on page 91). - */ -#define DDRPHY_DX_GCR_GSHIFT_MASK (0x40000UL) -#define DDRPHY_DX_GCR_GSHIFT_SHIFT (18U) -#define DDRPHY_DX_GCR_GSHIFT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_GSHIFT_SHIFT) & DDRPHY_DX_GCR_GSHIFT_MASK) -#define DDRPHY_DX_GCR_GSHIFT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_GSHIFT_MASK) >> DDRPHY_DX_GCR_GSHIFT_SHIFT) - -/* - * PLLPD (R/W) - * - * PLL Power Down: Puts the byte PLL in power down mode by driving the PLL power down pin. This bit is not self-clearing and a '0' must be written to de-assert the power-down. This bit is ORed with the global PLLPD configuration bit (see - * Table 3-10 on page 91). - */ -#define DDRPHY_DX_GCR_PLLPD_MASK (0x20000UL) -#define DDRPHY_DX_GCR_PLLPD_SHIFT (17U) -#define DDRPHY_DX_GCR_PLLPD_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLPD_SHIFT) & DDRPHY_DX_GCR_PLLPD_MASK) -#define DDRPHY_DX_GCR_PLLPD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLPD_MASK) >> DDRPHY_DX_GCR_PLLPD_SHIFT) - -/* - * PLLRST (R/W) - * - * PLL Rest: Resets the byte PLL by driving the PLL reset pin. This bit is not self- clearing and a '0' must be written to de-assert the reset. This bit is ORed with the global PLLRST configuration bit (see Table 3-10 on page 91). - */ -#define DDRPHY_DX_GCR_PLLRST_MASK (0x10000UL) -#define DDRPHY_DX_GCR_PLLRST_SHIFT (16U) -#define DDRPHY_DX_GCR_PLLRST_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_PLLRST_SHIFT) & DDRPHY_DX_GCR_PLLRST_MASK) -#define DDRPHY_DX_GCR_PLLRST_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_PLLRST_MASK) >> DDRPHY_DX_GCR_PLLRST_SHIFT) - -/* - * DXOEO (R/W) - * - * Data Byte Output Enable Override: Specifies whether the output I/O output enable for the byte lane should be set to a fixed value. Valid values are: - * 00 = No override. Output enable is controlled by DFI transactions 01 = output enable is asserted (I/O is forced to output mode). - * 10 = Output enable is de-asserted (I/O is forced to input mode) 11 = Reserved - */ -#define DDRPHY_DX_GCR_DXOEO_MASK (0xC000U) -#define DDRPHY_DX_GCR_DXOEO_SHIFT (14U) -#define DDRPHY_DX_GCR_DXOEO_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXOEO_SHIFT) & DDRPHY_DX_GCR_DXOEO_MASK) -#define DDRPHY_DX_GCR_DXOEO_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXOEO_MASK) >> DDRPHY_DX_GCR_DXOEO_SHIFT) - -/* - * RTTOAL (R/W) - * - * RTT On Additive Latency: Indicates when the ODT control of DQ/DQS SSTL I/Os is set to the value in DQODT/DQSODT during read cycles. Valid values are: - * 0 = ODT control is set to DQSODT/DQODT almost two cycles before read data preamble - * 1 = ODT control is set to DQSODT/DQODT almost one cycle before read data preamble - */ -#define DDRPHY_DX_GCR_RTTOAL_MASK (0x2000U) -#define DDRPHY_DX_GCR_RTTOAL_SHIFT (13U) -#define DDRPHY_DX_GCR_RTTOAL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_RTTOAL_SHIFT) & DDRPHY_DX_GCR_RTTOAL_MASK) -#define DDRPHY_DX_GCR_RTTOAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_RTTOAL_MASK) >> DDRPHY_DX_GCR_RTTOAL_SHIFT) - -/* - * RTTOH (R/W) - * - * RTT Output Hold: Indicates the number of clock cycles (from 0 to 3) after the read data postamble for which ODT control should remain set to DQSODT for DQS or DQODT for DQ/DM before disabling it (setting it to ‘0’) when using dynamic ODT control. ODT is disabled almost RTTOH clock cycles after the read postamble. - */ -#define DDRPHY_DX_GCR_RTTOH_MASK (0x1800U) -#define DDRPHY_DX_GCR_RTTOH_SHIFT (11U) -#define DDRPHY_DX_GCR_RTTOH_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_RTTOH_SHIFT) & DDRPHY_DX_GCR_RTTOH_MASK) -#define DDRPHY_DX_GCR_RTTOH_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_RTTOH_MASK) >> DDRPHY_DX_GCR_RTTOH_SHIFT) - -/* - * DQRTT (R/W) - * - * DQ Dynamic RTT Control: If set, the on die termination (ODT) control of the DQ/DM SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[2] (DQODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). - */ -#define DDRPHY_DX_GCR_DQRTT_MASK (0x400U) -#define DDRPHY_DX_GCR_DQRTT_SHIFT (10U) -#define DDRPHY_DX_GCR_DQRTT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQRTT_SHIFT) & DDRPHY_DX_GCR_DQRTT_MASK) -#define DDRPHY_DX_GCR_DQRTT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQRTT_MASK) >> DDRPHY_DX_GCR_DQRTT_SHIFT) - -/* - * DQSRTT (R/W) - * - * DQS Dynamic RTT Control: If set, the on die termination (ODT) control of the DQS/DQS# SSTL I/O is dynamically generated to enable the ODT during read operation and disabled otherwise. By setting this bit to '0' the dynamic ODT feature is disabled. To control ODT statically this bit must be set to '0' and DXnGCR0[1] (DQSODT) is used to enable ODT (when set to '1') or disable ODT(when set to '0'). - */ -#define DDRPHY_DX_GCR_DQSRTT_MASK (0x200U) -#define DDRPHY_DX_GCR_DQSRTT_SHIFT (9U) -#define DDRPHY_DX_GCR_DQSRTT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSRTT_SHIFT) & DDRPHY_DX_GCR_DQSRTT_MASK) -#define DDRPHY_DX_GCR_DQSRTT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSRTT_MASK) >> DDRPHY_DX_GCR_DQSRTT_SHIFT) - -/* - * DSEN (R/W) - * - * Write DQS Enable: Controls whether the write DQS going to the SDRAM is enabled (toggling) or disabled (static value) and whether the DQS is inverted. DQS# is always the inversion of DQS. These values are valid only when DQS/DQS# output enable is on, otherwise the DQS/DQS# is tristated. Valid settings are: - * 00 = Reserved - * 01 = DQS toggling with normal polarity (This should be the default setting) 10 = Reserved - * 11 = Reserved - */ -#define DDRPHY_DX_GCR_DSEN_MASK (0x180U) -#define DDRPHY_DX_GCR_DSEN_SHIFT (7U) -#define DDRPHY_DX_GCR_DSEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DSEN_SHIFT) & DDRPHY_DX_GCR_DSEN_MASK) -#define DDRPHY_DX_GCR_DSEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DSEN_MASK) >> DDRPHY_DX_GCR_DSEN_SHIFT) - -/* - * DQSRPD (R/W) - * - * DQSR Power Down: Powers down, if set, the PDQSR cell. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99) - */ -#define DDRPHY_DX_GCR_DQSRPD_MASK (0x40U) -#define DDRPHY_DX_GCR_DQSRPD_SHIFT (6U) -#define DDRPHY_DX_GCR_DQSRPD_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSRPD_SHIFT) & DDRPHY_DX_GCR_DQSRPD_MASK) -#define DDRPHY_DX_GCR_DQSRPD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSRPD_MASK) >> DDRPHY_DX_GCR_DQSRPD_SHIFT) - -/* - * DXPDR (R/W) - * - * Data Power Down Receiver: Powers down, when set, the input receiver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDR configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). - */ -#define DDRPHY_DX_GCR_DXPDR_MASK (0x20U) -#define DDRPHY_DX_GCR_DXPDR_SHIFT (5U) -#define DDRPHY_DX_GCR_DXPDR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXPDR_SHIFT) & DDRPHY_DX_GCR_DXPDR_MASK) -#define DDRPHY_DX_GCR_DXPDR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXPDR_MASK) >> DDRPHY_DX_GCR_DXPDR_SHIFT) - -/* - * DXPDD1 (R/W) - * - * Data Power Down Driver: Powers down, when set, the output driver on I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the common PDD configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). - */ -#define DDRPHY_DX_GCR_DXPDD1_MASK (0x10U) -#define DDRPHY_DX_GCR_DXPDD1_SHIFT (4U) -#define DDRPHY_DX_GCR_DXPDD1_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXPDD1_SHIFT) & DDRPHY_DX_GCR_DXPDD1_MASK) -#define DDRPHY_DX_GCR_DXPDD1_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXPDD1_MASK) >> DDRPHY_DX_GCR_DXPDD1_SHIFT) - -/* - * DXIOM (R/W) - * - * Data I/O Mode: Selects SSTL mode (when set to 0) or CMOS mode (when set to 1) of the I/O for DQ, DM, and DQS/DQS# pins of the byte. This bit is ORed with the IOM configuration bit of the individual DATX8(see “DATX8 Common Configuration Register (DXCCR)” on page 99). - */ -#define DDRPHY_DX_GCR_DXIOM_MASK (0x8U) -#define DDRPHY_DX_GCR_DXIOM_SHIFT (3U) -#define DDRPHY_DX_GCR_DXIOM_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXIOM_SHIFT) & DDRPHY_DX_GCR_DXIOM_MASK) -#define DDRPHY_DX_GCR_DXIOM_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXIOM_MASK) >> DDRPHY_DX_GCR_DXIOM_SHIFT) - -/* - * DQODT (R/W) - * - * Data On-Die Termination: Enables, when set, the on-die termination on the I/O for DQ and DM pins of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). - * Note: This bit is only valid when DXnGCR0[10] is '0'. - */ -#define DDRPHY_DX_GCR_DQODT_MASK (0x4U) -#define DDRPHY_DX_GCR_DQODT_SHIFT (2U) -#define DDRPHY_DX_GCR_DQODT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQODT_SHIFT) & DDRPHY_DX_GCR_DQODT_MASK) -#define DDRPHY_DX_GCR_DQODT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQODT_MASK) >> DDRPHY_DX_GCR_DQODT_SHIFT) - -/* - * DQSODT (R/W) - * - * DQS On-Die Termination: Enables, when set, the on-die termination on the I/O for DQS/DQS# pin of the byte. This bit is ORed with the common DATX8 ODT configuration bit (see “DATX8 Common Configuration Register (DXCCR)” on page 99). - * Note: This bit is only valid when DXnGCR0[9] is '0'. - */ -#define DDRPHY_DX_GCR_DQSODT_MASK (0x2U) -#define DDRPHY_DX_GCR_DQSODT_SHIFT (1U) -#define DDRPHY_DX_GCR_DQSODT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DQSODT_SHIFT) & DDRPHY_DX_GCR_DQSODT_MASK) -#define DDRPHY_DX_GCR_DQSODT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DQSODT_MASK) >> DDRPHY_DX_GCR_DQSODT_SHIFT) - -/* - * DXEN (R/W) - * - * Data Byte Enable: Enables, if set, the data byte. Setting this bit to '0' disables the byte, i.e. the byte is not used in PHY initialization or training and is ignored during SDRAM read/write operations. - */ -#define DDRPHY_DX_GCR_DXEN_MASK (0x1U) -#define DDRPHY_DX_GCR_DXEN_SHIFT (0U) -#define DDRPHY_DX_GCR_DXEN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GCR_DXEN_SHIFT) & DDRPHY_DX_GCR_DXEN_MASK) -#define DDRPHY_DX_GCR_DXEN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GCR_DXEN_MASK) >> DDRPHY_DX_GCR_DXEN_SHIFT) - -/* Bitfield definition for register of struct array DX: GSR0 */ -/* - * WLDQ (R) - * - * Write Leveling DQ Status: Captures the write leveling DQ status from the DRAM during software write leveling. - */ -#define DDRPHY_DX_GSR0_WLDQ_MASK (0x10000000UL) -#define DDRPHY_DX_GSR0_WLDQ_SHIFT (28U) -#define DDRPHY_DX_GSR0_WLDQ_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLDQ_MASK) >> DDRPHY_DX_GSR0_WLDQ_SHIFT) - -/* - * QSGERR (R) - * - * DQS Gate Training Error: Indicates, if set, that there is an error in DQS gate training. One bit for each of the up to 4 ranks. - */ -#define DDRPHY_DX_GSR0_QSGERR_MASK (0xF000000UL) -#define DDRPHY_DX_GSR0_QSGERR_SHIFT (24U) -#define DDRPHY_DX_GSR0_QSGERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_QSGERR_MASK) >> DDRPHY_DX_GSR0_QSGERR_SHIFT) - -/* - * GDQSPRD (R) - * - * Read DQS gating Period: Returns the DDR clock period measured by the read DQS gating LCDL during calibration. This value is PVT compensated. - */ -#define DDRPHY_DX_GSR0_GDQSPRD_MASK (0xFF0000UL) -#define DDRPHY_DX_GSR0_GDQSPRD_SHIFT (16U) -#define DDRPHY_DX_GSR0_GDQSPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_GDQSPRD_MASK) >> DDRPHY_DX_GSR0_GDQSPRD_SHIFT) - -/* - * DPLOCK (R) - * - * DATX8 PLL Lock: Indicates, if set, that the DATX8 PLL has locked. This is a direct status of the DATX8 PLL lock pin. - */ -#define DDRPHY_DX_GSR0_DPLOCK_MASK (0x8000U) -#define DDRPHY_DX_GSR0_DPLOCK_SHIFT (15U) -#define DDRPHY_DX_GSR0_DPLOCK_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_DPLOCK_MASK) >> DDRPHY_DX_GSR0_DPLOCK_SHIFT) - -/* - * WLPRD (R) - * - * Write Leveling Period: Returns the DDR clock period measured by the write leveling LCDL during calibration. The measured period is used to generate the control of the write leveling pipeline which is a function of the write-leveling delay and the clock period. This value is PVT compensated. - */ -#define DDRPHY_DX_GSR0_WLPRD_MASK (0x7F80U) -#define DDRPHY_DX_GSR0_WLPRD_SHIFT (7U) -#define DDRPHY_DX_GSR0_WLPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLPRD_MASK) >> DDRPHY_DX_GSR0_WLPRD_SHIFT) - -/* - * WLERR (R) - * - * Write Leveling Error: Indicates, if set, that there is a write leveling error in the DATX8. - */ -#define DDRPHY_DX_GSR0_WLERR_MASK (0x40U) -#define DDRPHY_DX_GSR0_WLERR_SHIFT (6U) -#define DDRPHY_DX_GSR0_WLERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLERR_MASK) >> DDRPHY_DX_GSR0_WLERR_SHIFT) - -/* - * WLDONE (R) - * - * Write Leveling Done: Indicates, if set, that the DATX8 has completed write leveling. - */ -#define DDRPHY_DX_GSR0_WLDONE_MASK (0x20U) -#define DDRPHY_DX_GSR0_WLDONE_SHIFT (5U) -#define DDRPHY_DX_GSR0_WLDONE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLDONE_MASK) >> DDRPHY_DX_GSR0_WLDONE_SHIFT) - -/* - * WLCAL (R) - * - * Write Leveling Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write leveling slave delay line. - */ -#define DDRPHY_DX_GSR0_WLCAL_MASK (0x10U) -#define DDRPHY_DX_GSR0_WLCAL_SHIFT (4U) -#define DDRPHY_DX_GSR0_WLCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WLCAL_MASK) >> DDRPHY_DX_GSR0_WLCAL_SHIFT) - -/* - * GDQSCAL (R) - * - * Read DQS gating Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS gating LCDL. - */ -#define DDRPHY_DX_GSR0_GDQSCAL_MASK (0x8U) -#define DDRPHY_DX_GSR0_GDQSCAL_SHIFT (3U) -#define DDRPHY_DX_GSR0_GDQSCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_GDQSCAL_MASK) >> DDRPHY_DX_GSR0_GDQSCAL_SHIFT) - -/* - * RDQSNCAL (R) - * - * Read DQS# Calibration (Type B/B1 PHY Only): Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS# LCDL. - */ -#define DDRPHY_DX_GSR0_RDQSNCAL_MASK (0x4U) -#define DDRPHY_DX_GSR0_RDQSNCAL_SHIFT (2U) -#define DDRPHY_DX_GSR0_RDQSNCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_RDQSNCAL_MASK) >> DDRPHY_DX_GSR0_RDQSNCAL_SHIFT) - -/* - * RDQSCAL (R) - * - * Read DQS Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the read DQS LCDL. - */ -#define DDRPHY_DX_GSR0_RDQSCAL_MASK (0x2U) -#define DDRPHY_DX_GSR0_RDQSCAL_SHIFT (1U) -#define DDRPHY_DX_GSR0_RDQSCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_RDQSCAL_MASK) >> DDRPHY_DX_GSR0_RDQSCAL_SHIFT) - -/* - * WDQCAL (R) - * - * Write DQ Calibration: Indicates, if set, that the DATX8 has finished doing period measurement calibration for the write DQ LCDL. - */ -#define DDRPHY_DX_GSR0_WDQCAL_MASK (0x1U) -#define DDRPHY_DX_GSR0_WDQCAL_SHIFT (0U) -#define DDRPHY_DX_GSR0_WDQCAL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR0_WDQCAL_MASK) >> DDRPHY_DX_GSR0_WDQCAL_SHIFT) - -/* Bitfield definition for register of struct array DX: GSR1 */ -/* - * DLTCODE (R) - * - * Delay Line Test Code: Returns the code measured by the PHY control block that corresponds to the period of the DATX8 delay line digital test output. - */ -#define DDRPHY_DX_GSR1_DLTCODE_MASK (0x1FFFFFEUL) -#define DDRPHY_DX_GSR1_DLTCODE_SHIFT (1U) -#define DDRPHY_DX_GSR1_DLTCODE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR1_DLTCODE_MASK) >> DDRPHY_DX_GSR1_DLTCODE_SHIFT) - -/* - * DLTDONE (R) - * - * Delay Line Test Done: Indicates, if set, that the PHY control block has finished doing period measurement of the DATX8 delay line digital test output. - */ -#define DDRPHY_DX_GSR1_DLTDONE_MASK (0x1U) -#define DDRPHY_DX_GSR1_DLTDONE_SHIFT (0U) -#define DDRPHY_DX_GSR1_DLTDONE_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR1_DLTDONE_MASK) >> DDRPHY_DX_GSR1_DLTDONE_SHIFT) - -/* Bitfield definition for register of struct array DX: BDLR0 */ -/* - * DQ4WBD (R/W) - * - * DQ4 Write Bit Delay: Delay select for the BDL on DQ4 write path. - */ -#define DDRPHY_DX_BDLR0_DQ4WBD_MASK (0x3F000000UL) -#define DDRPHY_DX_BDLR0_DQ4WBD_SHIFT (24U) -#define DDRPHY_DX_BDLR0_DQ4WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ4WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ4WBD_MASK) -#define DDRPHY_DX_BDLR0_DQ4WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ4WBD_MASK) >> DDRPHY_DX_BDLR0_DQ4WBD_SHIFT) - -/* - * DQ3WBD (R/W) - * - * DQ3 Write Bit Delay: Delay select for the BDL on DQ3 write path - */ -#define DDRPHY_DX_BDLR0_DQ3WBD_MASK (0xFC0000UL) -#define DDRPHY_DX_BDLR0_DQ3WBD_SHIFT (18U) -#define DDRPHY_DX_BDLR0_DQ3WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ3WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ3WBD_MASK) -#define DDRPHY_DX_BDLR0_DQ3WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ3WBD_MASK) >> DDRPHY_DX_BDLR0_DQ3WBD_SHIFT) - -/* - * DQ2WBD (R/W) - * - * DQ2 Write Bit Delay: Delay select for the BDL on DQ2 write path. - */ -#define DDRPHY_DX_BDLR0_DQ2WBD_MASK (0x3F000UL) -#define DDRPHY_DX_BDLR0_DQ2WBD_SHIFT (12U) -#define DDRPHY_DX_BDLR0_DQ2WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ2WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ2WBD_MASK) -#define DDRPHY_DX_BDLR0_DQ2WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ2WBD_MASK) >> DDRPHY_DX_BDLR0_DQ2WBD_SHIFT) - -/* - * DQ1WBD (R/W) - * - * DQ1 Write Bit Delay: Delay select for the BDL on DQ1 write path. - */ -#define DDRPHY_DX_BDLR0_DQ1WBD_MASK (0xFC0U) -#define DDRPHY_DX_BDLR0_DQ1WBD_SHIFT (6U) -#define DDRPHY_DX_BDLR0_DQ1WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ1WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ1WBD_MASK) -#define DDRPHY_DX_BDLR0_DQ1WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ1WBD_MASK) >> DDRPHY_DX_BDLR0_DQ1WBD_SHIFT) - -/* - * DQ0WBD (R/W) - * - * DQ0 Write Bit Delay: Delay select for the BDL on DQ0 write path. - */ -#define DDRPHY_DX_BDLR0_DQ0WBD_MASK (0x3FU) -#define DDRPHY_DX_BDLR0_DQ0WBD_SHIFT (0U) -#define DDRPHY_DX_BDLR0_DQ0WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR0_DQ0WBD_SHIFT) & DDRPHY_DX_BDLR0_DQ0WBD_MASK) -#define DDRPHY_DX_BDLR0_DQ0WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR0_DQ0WBD_MASK) >> DDRPHY_DX_BDLR0_DQ0WBD_SHIFT) - -/* Bitfield definition for register of struct array DX: BDLR1 */ -/* - * DSWBD (R/W) - * - * DQS Write Bit Delay: Delay select for the BDL on DQS write path - */ -#define DDRPHY_DX_BDLR1_DSWBD_MASK (0x3F000000UL) -#define DDRPHY_DX_BDLR1_DSWBD_SHIFT (24U) -#define DDRPHY_DX_BDLR1_DSWBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DSWBD_SHIFT) & DDRPHY_DX_BDLR1_DSWBD_MASK) -#define DDRPHY_DX_BDLR1_DSWBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DSWBD_MASK) >> DDRPHY_DX_BDLR1_DSWBD_SHIFT) - -/* - * DMWBD (R/W) - * - * DM Write Bit Delay: Delay select for the BDL on DM write path. - */ -#define DDRPHY_DX_BDLR1_DMWBD_MASK (0xFC0000UL) -#define DDRPHY_DX_BDLR1_DMWBD_SHIFT (18U) -#define DDRPHY_DX_BDLR1_DMWBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DMWBD_SHIFT) & DDRPHY_DX_BDLR1_DMWBD_MASK) -#define DDRPHY_DX_BDLR1_DMWBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DMWBD_MASK) >> DDRPHY_DX_BDLR1_DMWBD_SHIFT) - -/* - * DQ7WBD (R/W) - * - * DQ7 Write Bit Delay: Delay select for the BDL on DQ7 write path. - */ -#define DDRPHY_DX_BDLR1_DQ7WBD_MASK (0x3F000UL) -#define DDRPHY_DX_BDLR1_DQ7WBD_SHIFT (12U) -#define DDRPHY_DX_BDLR1_DQ7WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ7WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ7WBD_MASK) -#define DDRPHY_DX_BDLR1_DQ7WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ7WBD_MASK) >> DDRPHY_DX_BDLR1_DQ7WBD_SHIFT) - -/* - * DQ6WBD (R/W) - * - * DQ6 Write Bit Delay: Delay select for the BDL on DQ6 write path. - */ -#define DDRPHY_DX_BDLR1_DQ6WBD_MASK (0xFC0U) -#define DDRPHY_DX_BDLR1_DQ6WBD_SHIFT (6U) -#define DDRPHY_DX_BDLR1_DQ6WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ6WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ6WBD_MASK) -#define DDRPHY_DX_BDLR1_DQ6WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ6WBD_MASK) >> DDRPHY_DX_BDLR1_DQ6WBD_SHIFT) - -/* - * DQ5WBD (R/W) - * - * DQ5 Write Bit Delay: Delay select for the BDL on DQ5 write path. - */ -#define DDRPHY_DX_BDLR1_DQ5WBD_MASK (0x3FU) -#define DDRPHY_DX_BDLR1_DQ5WBD_SHIFT (0U) -#define DDRPHY_DX_BDLR1_DQ5WBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR1_DQ5WBD_SHIFT) & DDRPHY_DX_BDLR1_DQ5WBD_MASK) -#define DDRPHY_DX_BDLR1_DQ5WBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR1_DQ5WBD_MASK) >> DDRPHY_DX_BDLR1_DQ5WBD_SHIFT) - -/* Bitfield definition for register of struct array DX: BDLR2 */ -/* - * DSNRBD (R/W) - * - * DQSN Read Bit Delay (Type B/B1 PHY Only): Delay select for the BDL on DQSN read path - */ -#define DDRPHY_DX_BDLR2_DSNRBD_MASK (0xFC0000UL) -#define DDRPHY_DX_BDLR2_DSNRBD_SHIFT (18U) -#define DDRPHY_DX_BDLR2_DSNRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSNRBD_SHIFT) & DDRPHY_DX_BDLR2_DSNRBD_MASK) -#define DDRPHY_DX_BDLR2_DSNRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSNRBD_MASK) >> DDRPHY_DX_BDLR2_DSNRBD_SHIFT) - -/* - * DSRBD (R/W) - * - * DQS Read Bit Delay: Delay select for the BDL on DQS read path - */ -#define DDRPHY_DX_BDLR2_DSRBD_MASK (0x3F000UL) -#define DDRPHY_DX_BDLR2_DSRBD_SHIFT (12U) -#define DDRPHY_DX_BDLR2_DSRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSRBD_SHIFT) & DDRPHY_DX_BDLR2_DSRBD_MASK) -#define DDRPHY_DX_BDLR2_DSRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSRBD_MASK) >> DDRPHY_DX_BDLR2_DSRBD_SHIFT) - -/* - * DQOEBD (R/W) - * - * DQ Output Enable Bit Delay: Delay select for the BDL on DQ/DM output enable path. - */ -#define DDRPHY_DX_BDLR2_DQOEBD_MASK (0xFC0U) -#define DDRPHY_DX_BDLR2_DQOEBD_SHIFT (6U) -#define DDRPHY_DX_BDLR2_DQOEBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DQOEBD_SHIFT) & DDRPHY_DX_BDLR2_DQOEBD_MASK) -#define DDRPHY_DX_BDLR2_DQOEBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DQOEBD_MASK) >> DDRPHY_DX_BDLR2_DQOEBD_SHIFT) - -/* - * DSOEBD (R/W) - * - * DQS Output Enable Bit Delay: Delay select for the BDL on DQS output enable path - */ -#define DDRPHY_DX_BDLR2_DSOEBD_MASK (0x3FU) -#define DDRPHY_DX_BDLR2_DSOEBD_SHIFT (0U) -#define DDRPHY_DX_BDLR2_DSOEBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR2_DSOEBD_SHIFT) & DDRPHY_DX_BDLR2_DSOEBD_MASK) -#define DDRPHY_DX_BDLR2_DSOEBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR2_DSOEBD_MASK) >> DDRPHY_DX_BDLR2_DSOEBD_SHIFT) - -/* Bitfield definition for register of struct array DX: BDLR3 */ -/* - * DQ4RBD (R/W) - * - * DQ4 Read Bit Delay: Delay select for the BDL on DQ4 read path. - */ -#define DDRPHY_DX_BDLR3_DQ4RBD_MASK (0x3F000000UL) -#define DDRPHY_DX_BDLR3_DQ4RBD_SHIFT (24U) -#define DDRPHY_DX_BDLR3_DQ4RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ4RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ4RBD_MASK) -#define DDRPHY_DX_BDLR3_DQ4RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ4RBD_MASK) >> DDRPHY_DX_BDLR3_DQ4RBD_SHIFT) - -/* - * DQ3RBD (R/W) - * - * DQ3 Read Bit Delay: Delay select for the BDL on DQ3 read path - */ -#define DDRPHY_DX_BDLR3_DQ3RBD_MASK (0xFC0000UL) -#define DDRPHY_DX_BDLR3_DQ3RBD_SHIFT (18U) -#define DDRPHY_DX_BDLR3_DQ3RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ3RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ3RBD_MASK) -#define DDRPHY_DX_BDLR3_DQ3RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ3RBD_MASK) >> DDRPHY_DX_BDLR3_DQ3RBD_SHIFT) - -/* - * DQ2RBD (R/W) - * - * DQ2 Read Bit Delay: Delay select for the BDL on DQ2 read path. - */ -#define DDRPHY_DX_BDLR3_DQ2RBD_MASK (0x3F000UL) -#define DDRPHY_DX_BDLR3_DQ2RBD_SHIFT (12U) -#define DDRPHY_DX_BDLR3_DQ2RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ2RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ2RBD_MASK) -#define DDRPHY_DX_BDLR3_DQ2RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ2RBD_MASK) >> DDRPHY_DX_BDLR3_DQ2RBD_SHIFT) - -/* - * DQ1RBD (R/W) - * - * DQ1 Read Bit Delay: Delay select for the BDL on DQ1 read path. - */ -#define DDRPHY_DX_BDLR3_DQ1RBD_MASK (0xFC0U) -#define DDRPHY_DX_BDLR3_DQ1RBD_SHIFT (6U) -#define DDRPHY_DX_BDLR3_DQ1RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ1RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ1RBD_MASK) -#define DDRPHY_DX_BDLR3_DQ1RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ1RBD_MASK) >> DDRPHY_DX_BDLR3_DQ1RBD_SHIFT) - -/* - * DQ0RBD (R/W) - * - * DQ0 Read Bit Delay: Delay select for the BDL on DQ0 read path. - */ -#define DDRPHY_DX_BDLR3_DQ0RBD_MASK (0x3FU) -#define DDRPHY_DX_BDLR3_DQ0RBD_SHIFT (0U) -#define DDRPHY_DX_BDLR3_DQ0RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR3_DQ0RBD_SHIFT) & DDRPHY_DX_BDLR3_DQ0RBD_MASK) -#define DDRPHY_DX_BDLR3_DQ0RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR3_DQ0RBD_MASK) >> DDRPHY_DX_BDLR3_DQ0RBD_SHIFT) - -/* Bitfield definition for register of struct array DX: BDLR4 */ -/* - * DMRBD (R/W) - * - * DM Read Bit Delay: Delay select for the BDL on DM read path. - */ -#define DDRPHY_DX_BDLR4_DMRBD_MASK (0xFC0000UL) -#define DDRPHY_DX_BDLR4_DMRBD_SHIFT (18U) -#define DDRPHY_DX_BDLR4_DMRBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DMRBD_SHIFT) & DDRPHY_DX_BDLR4_DMRBD_MASK) -#define DDRPHY_DX_BDLR4_DMRBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DMRBD_MASK) >> DDRPHY_DX_BDLR4_DMRBD_SHIFT) - -/* - * DQ7RBD (R/W) - * - * DQ7 Read Bit Delay: Delay select for the BDL on DQ7 read path. - */ -#define DDRPHY_DX_BDLR4_DQ7RBD_MASK (0x3F000UL) -#define DDRPHY_DX_BDLR4_DQ7RBD_SHIFT (12U) -#define DDRPHY_DX_BDLR4_DQ7RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ7RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ7RBD_MASK) -#define DDRPHY_DX_BDLR4_DQ7RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ7RBD_MASK) >> DDRPHY_DX_BDLR4_DQ7RBD_SHIFT) - -/* - * DQ6RBD (R/W) - * - * DQ6 Read Bit Delay: Delay select for the BDL on DQ6 read path. - */ -#define DDRPHY_DX_BDLR4_DQ6RBD_MASK (0xFC0U) -#define DDRPHY_DX_BDLR4_DQ6RBD_SHIFT (6U) -#define DDRPHY_DX_BDLR4_DQ6RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ6RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ6RBD_MASK) -#define DDRPHY_DX_BDLR4_DQ6RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ6RBD_MASK) >> DDRPHY_DX_BDLR4_DQ6RBD_SHIFT) - -/* - * DQ5RBD (R/W) - * - * DQ5 Read Bit Delay: Delay select for the BDL on DQ5 read path. - */ -#define DDRPHY_DX_BDLR4_DQ5RBD_MASK (0x3FU) -#define DDRPHY_DX_BDLR4_DQ5RBD_SHIFT (0U) -#define DDRPHY_DX_BDLR4_DQ5RBD_SET(x) (((uint32_t)(x) << DDRPHY_DX_BDLR4_DQ5RBD_SHIFT) & DDRPHY_DX_BDLR4_DQ5RBD_MASK) -#define DDRPHY_DX_BDLR4_DQ5RBD_GET(x) (((uint32_t)(x) & DDRPHY_DX_BDLR4_DQ5RBD_MASK) >> DDRPHY_DX_BDLR4_DQ5RBD_SHIFT) - -/* Bitfield definition for register of struct array DX: LCDLR0 */ -/* - * R3WLD (R/W) - * - * Rank 3 Write Leveling Delay: Rank 3 delay select for the write leveling (WL) LCDL - */ -#define DDRPHY_DX_LCDLR0_R3WLD_MASK (0xFF000000UL) -#define DDRPHY_DX_LCDLR0_R3WLD_SHIFT (24U) -#define DDRPHY_DX_LCDLR0_R3WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R3WLD_SHIFT) & DDRPHY_DX_LCDLR0_R3WLD_MASK) -#define DDRPHY_DX_LCDLR0_R3WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R3WLD_MASK) >> DDRPHY_DX_LCDLR0_R3WLD_SHIFT) - -/* - * R2WLD (R/W) - * - * Rank 2 Write Leveling Delay: Rank 2 delay select for the write leveling (WL) LCDL - */ -#define DDRPHY_DX_LCDLR0_R2WLD_MASK (0xFF0000UL) -#define DDRPHY_DX_LCDLR0_R2WLD_SHIFT (16U) -#define DDRPHY_DX_LCDLR0_R2WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R2WLD_SHIFT) & DDRPHY_DX_LCDLR0_R2WLD_MASK) -#define DDRPHY_DX_LCDLR0_R2WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R2WLD_MASK) >> DDRPHY_DX_LCDLR0_R2WLD_SHIFT) - -/* - * R1WLD (R/W) - * - * Rank 1 Write Leveling Delay: Rank 1 delay select for the write leveling (WL) LCDL - */ -#define DDRPHY_DX_LCDLR0_R1WLD_MASK (0xFF00U) -#define DDRPHY_DX_LCDLR0_R1WLD_SHIFT (8U) -#define DDRPHY_DX_LCDLR0_R1WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R1WLD_SHIFT) & DDRPHY_DX_LCDLR0_R1WLD_MASK) -#define DDRPHY_DX_LCDLR0_R1WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R1WLD_MASK) >> DDRPHY_DX_LCDLR0_R1WLD_SHIFT) - -/* - * R0WLD (R/W) - * - * Rank 0 Write Leveling Delay: Rank 0 delay select for the write leveling (WL) LCDL - */ -#define DDRPHY_DX_LCDLR0_R0WLD_MASK (0xFFU) -#define DDRPHY_DX_LCDLR0_R0WLD_SHIFT (0U) -#define DDRPHY_DX_LCDLR0_R0WLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR0_R0WLD_SHIFT) & DDRPHY_DX_LCDLR0_R0WLD_MASK) -#define DDRPHY_DX_LCDLR0_R0WLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR0_R0WLD_MASK) >> DDRPHY_DX_LCDLR0_R0WLD_SHIFT) - -/* Bitfield definition for register of struct array DX: LCDLR1 */ -/* - * RDQSND (R/W) - * - * Read DQSN Delay (Type B/B1 PHY Only): Delay select for the read DQSN (RDQS) LCDL - */ -#define DDRPHY_DX_LCDLR1_RDQSND_MASK (0xFF0000UL) -#define DDRPHY_DX_LCDLR1_RDQSND_SHIFT (16U) -#define DDRPHY_DX_LCDLR1_RDQSND_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_RDQSND_SHIFT) & DDRPHY_DX_LCDLR1_RDQSND_MASK) -#define DDRPHY_DX_LCDLR1_RDQSND_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_RDQSND_MASK) >> DDRPHY_DX_LCDLR1_RDQSND_SHIFT) - -/* - * RDQSD (R/W) - * - * Read DQS Delay: Delay select for the read DQS (RDQS) LCDL - */ -#define DDRPHY_DX_LCDLR1_RDQSD_MASK (0xFF00U) -#define DDRPHY_DX_LCDLR1_RDQSD_SHIFT (8U) -#define DDRPHY_DX_LCDLR1_RDQSD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_RDQSD_SHIFT) & DDRPHY_DX_LCDLR1_RDQSD_MASK) -#define DDRPHY_DX_LCDLR1_RDQSD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_RDQSD_MASK) >> DDRPHY_DX_LCDLR1_RDQSD_SHIFT) - -/* - * WDQD (R/W) - * - * Write Data Delay: Delay select for the write data (WDQ) LCDL - */ -#define DDRPHY_DX_LCDLR1_WDQD_MASK (0xFFU) -#define DDRPHY_DX_LCDLR1_WDQD_SHIFT (0U) -#define DDRPHY_DX_LCDLR1_WDQD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR1_WDQD_SHIFT) & DDRPHY_DX_LCDLR1_WDQD_MASK) -#define DDRPHY_DX_LCDLR1_WDQD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR1_WDQD_MASK) >> DDRPHY_DX_LCDLR1_WDQD_SHIFT) - -/* Bitfield definition for register of struct array DX: LCDLR2 */ -/* - * R3DQSGD (R/W) - * - * Rank 3 Read DQS Gating Delay: Rank 3 delay select for the read DQS gating (DQSG) LCDL - */ -#define DDRPHY_DX_LCDLR2_R3DQSGD_MASK (0xFF000000UL) -#define DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT (24U) -#define DDRPHY_DX_LCDLR2_R3DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R3DQSGD_MASK) -#define DDRPHY_DX_LCDLR2_R3DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R3DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R3DQSGD_SHIFT) - -/* - * R2DQSGD (R/W) - * - * Rank 2 Read DQS Gating Delay: Rank 2 delay select for the read DQS gating (DQSG) LCDL - */ -#define DDRPHY_DX_LCDLR2_R2DQSGD_MASK (0xFF0000UL) -#define DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT (16U) -#define DDRPHY_DX_LCDLR2_R2DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R2DQSGD_MASK) -#define DDRPHY_DX_LCDLR2_R2DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R2DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R2DQSGD_SHIFT) - -/* - * R1DQSGD (R/W) - * - * Rank 1 Read DQS Gating Delay: Rank 1 delay select for the read DQS gating (DQSG) LCDL - */ -#define DDRPHY_DX_LCDLR2_R1DQSGD_MASK (0xFF00U) -#define DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT (8U) -#define DDRPHY_DX_LCDLR2_R1DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R1DQSGD_MASK) -#define DDRPHY_DX_LCDLR2_R1DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R1DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R1DQSGD_SHIFT) - -/* - * R0DQSGD (R/W) - * - * Rank 0 Read DQS Gating Delay: Rank 0 delay select for the read DQS gating (DQSG) LCDL - */ -#define DDRPHY_DX_LCDLR2_R0DQSGD_MASK (0xFFU) -#define DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT (0U) -#define DDRPHY_DX_LCDLR2_R0DQSGD_SET(x) (((uint32_t)(x) << DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT) & DDRPHY_DX_LCDLR2_R0DQSGD_MASK) -#define DDRPHY_DX_LCDLR2_R0DQSGD_GET(x) (((uint32_t)(x) & DDRPHY_DX_LCDLR2_R0DQSGD_MASK) >> DDRPHY_DX_LCDLR2_R0DQSGD_SHIFT) - -/* Bitfield definition for register of struct array DX: MDLR */ -/* - * MDLD (R/W) - * - * MDL Delay: Delay select for the LCDL for the Master Delay Line. - */ -#define DDRPHY_DX_MDLR_MDLD_MASK (0xFF0000UL) -#define DDRPHY_DX_MDLR_MDLD_SHIFT (16U) -#define DDRPHY_DX_MDLR_MDLD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_MDLD_SHIFT) & DDRPHY_DX_MDLR_MDLD_MASK) -#define DDRPHY_DX_MDLR_MDLD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_MDLD_MASK) >> DDRPHY_DX_MDLR_MDLD_SHIFT) - -/* - * TPRD (R/W) - * - * Target Period: Target period measured by the master delay line calibration for VT drift compensation. This is the current measured value of the period and is continuously updated if the MDL is enabled to do so. - */ -#define DDRPHY_DX_MDLR_TPRD_MASK (0xFF00U) -#define DDRPHY_DX_MDLR_TPRD_SHIFT (8U) -#define DDRPHY_DX_MDLR_TPRD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_TPRD_SHIFT) & DDRPHY_DX_MDLR_TPRD_MASK) -#define DDRPHY_DX_MDLR_TPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_TPRD_MASK) >> DDRPHY_DX_MDLR_TPRD_SHIFT) - -/* - * IPRD (R/W) - * - * Initial Period: Initial period measured by the master delay line calibration for VT drift compensation. This value is used as the denominator when calculating the ratios of updates during VT compensation. - */ -#define DDRPHY_DX_MDLR_IPRD_MASK (0xFFU) -#define DDRPHY_DX_MDLR_IPRD_SHIFT (0U) -#define DDRPHY_DX_MDLR_IPRD_SET(x) (((uint32_t)(x) << DDRPHY_DX_MDLR_IPRD_SHIFT) & DDRPHY_DX_MDLR_IPRD_MASK) -#define DDRPHY_DX_MDLR_IPRD_GET(x) (((uint32_t)(x) & DDRPHY_DX_MDLR_IPRD_MASK) >> DDRPHY_DX_MDLR_IPRD_SHIFT) - -/* Bitfield definition for register of struct array DX: GTR */ -/* - * R3WLSL (R/W) - * - */ -#define DDRPHY_DX_GTR_R3WLSL_MASK (0xC0000UL) -#define DDRPHY_DX_GTR_R3WLSL_SHIFT (18U) -#define DDRPHY_DX_GTR_R3WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R3WLSL_SHIFT) & DDRPHY_DX_GTR_R3WLSL_MASK) -#define DDRPHY_DX_GTR_R3WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R3WLSL_MASK) >> DDRPHY_DX_GTR_R3WLSL_SHIFT) - -/* - * R2WLSL (R/W) - * - */ -#define DDRPHY_DX_GTR_R2WLSL_MASK (0x30000UL) -#define DDRPHY_DX_GTR_R2WLSL_SHIFT (16U) -#define DDRPHY_DX_GTR_R2WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R2WLSL_SHIFT) & DDRPHY_DX_GTR_R2WLSL_MASK) -#define DDRPHY_DX_GTR_R2WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R2WLSL_MASK) >> DDRPHY_DX_GTR_R2WLSL_SHIFT) - -/* - * R1WLSL (R/W) - * - */ -#define DDRPHY_DX_GTR_R1WLSL_MASK (0xC000U) -#define DDRPHY_DX_GTR_R1WLSL_SHIFT (14U) -#define DDRPHY_DX_GTR_R1WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R1WLSL_SHIFT) & DDRPHY_DX_GTR_R1WLSL_MASK) -#define DDRPHY_DX_GTR_R1WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R1WLSL_MASK) >> DDRPHY_DX_GTR_R1WLSL_SHIFT) - -/* - * R0WLSL (R/W) - * - * Rank n Write Leveling System Latency: This is used to adjust the write latency after write leveling. Power-up default is 01 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic write leveling but these values can be overwritten by a direct write to this register. Every two bits of this register control the latency of each of the (up to) four ranks. R0WLSL controls the latency of rank 0, R1WLSL controls rank 1, and so on. Valid values: - * 00 = Write latency = WL - 1 01 = Write latency = WL - * 10 = Write latency = WL + 1 11 = Reserved - */ -#define DDRPHY_DX_GTR_R0WLSL_MASK (0x3000U) -#define DDRPHY_DX_GTR_R0WLSL_SHIFT (12U) -#define DDRPHY_DX_GTR_R0WLSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R0WLSL_SHIFT) & DDRPHY_DX_GTR_R0WLSL_MASK) -#define DDRPHY_DX_GTR_R0WLSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R0WLSL_MASK) >> DDRPHY_DX_GTR_R0WLSL_SHIFT) - -/* - * R3DGSL (R/W) - * - */ -#define DDRPHY_DX_GTR_R3DGSL_MASK (0xE00U) -#define DDRPHY_DX_GTR_R3DGSL_SHIFT (9U) -#define DDRPHY_DX_GTR_R3DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R3DGSL_SHIFT) & DDRPHY_DX_GTR_R3DGSL_MASK) -#define DDRPHY_DX_GTR_R3DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R3DGSL_MASK) >> DDRPHY_DX_GTR_R3DGSL_SHIFT) - -/* - * R2DGSL (R/W) - * - */ -#define DDRPHY_DX_GTR_R2DGSL_MASK (0x1C0U) -#define DDRPHY_DX_GTR_R2DGSL_SHIFT (6U) -#define DDRPHY_DX_GTR_R2DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R2DGSL_SHIFT) & DDRPHY_DX_GTR_R2DGSL_MASK) -#define DDRPHY_DX_GTR_R2DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R2DGSL_MASK) >> DDRPHY_DX_GTR_R2DGSL_SHIFT) - -/* - * R1DGSL (R/W) - * - */ -#define DDRPHY_DX_GTR_R1DGSL_MASK (0x38U) -#define DDRPHY_DX_GTR_R1DGSL_SHIFT (3U) -#define DDRPHY_DX_GTR_R1DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R1DGSL_SHIFT) & DDRPHY_DX_GTR_R1DGSL_MASK) -#define DDRPHY_DX_GTR_R1DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R1DGSL_MASK) >> DDRPHY_DX_GTR_R1DGSL_SHIFT) - -/* - * R0DGSL (R/W) - * - * Rank n DQS Gating System Latency: This is used to increase the number of clock cycles needed to expect valid DDR read data by up to seven extra clock cycles. - * This is used to compensate for board delays and other system delays. Power-up default is 000 (i.e. no extra clock cycles required). The SL fields are initially set by the PUB during automatic DQS data training but these values can be overwritten by a direct write to this register. Every three bits of this register control the latency of each of the (up to) four ranks. R0DGSL controls the latency of rank 0, R1DGSL controls rank 1, and so on. Valid values are 0 to 7: - */ -#define DDRPHY_DX_GTR_R0DGSL_MASK (0x7U) -#define DDRPHY_DX_GTR_R0DGSL_SHIFT (0U) -#define DDRPHY_DX_GTR_R0DGSL_SET(x) (((uint32_t)(x) << DDRPHY_DX_GTR_R0DGSL_SHIFT) & DDRPHY_DX_GTR_R0DGSL_MASK) -#define DDRPHY_DX_GTR_R0DGSL_GET(x) (((uint32_t)(x) & DDRPHY_DX_GTR_R0DGSL_MASK) >> DDRPHY_DX_GTR_R0DGSL_SHIFT) - -/* Bitfield definition for register of struct array DX: GSR2 */ -/* - * ESTAT (R/W) - * - * Error Status: If an error occurred for this lane as indicated by RDERR, WDERR, REERR or WEERR the error status code can provide additional information regard when the error occurred during the algorithm execution. - */ -#define DDRPHY_DX_GSR2_ESTAT_MASK (0xF00U) -#define DDRPHY_DX_GSR2_ESTAT_SHIFT (8U) -#define DDRPHY_DX_GSR2_ESTAT_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_ESTAT_SHIFT) & DDRPHY_DX_GSR2_ESTAT_MASK) -#define DDRPHY_DX_GSR2_ESTAT_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_ESTAT_MASK) >> DDRPHY_DX_GSR2_ESTAT_SHIFT) - -/* - * WEWN (R/W) - * - * Write Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write data eye training. - */ -#define DDRPHY_DX_GSR2_WEWN_MASK (0x80U) -#define DDRPHY_DX_GSR2_WEWN_SHIFT (7U) -#define DDRPHY_DX_GSR2_WEWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WEWN_SHIFT) & DDRPHY_DX_GSR2_WEWN_MASK) -#define DDRPHY_DX_GSR2_WEWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WEWN_MASK) >> DDRPHY_DX_GSR2_WEWN_SHIFT) - -/* - * WEERR (R/W) - * - * Write Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write data eye training. - */ -#define DDRPHY_DX_GSR2_WEERR_MASK (0x40U) -#define DDRPHY_DX_GSR2_WEERR_SHIFT (6U) -#define DDRPHY_DX_GSR2_WEERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WEERR_SHIFT) & DDRPHY_DX_GSR2_WEERR_MASK) -#define DDRPHY_DX_GSR2_WEERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WEERR_MASK) >> DDRPHY_DX_GSR2_WEERR_SHIFT) - -/* - * REWN (R/W) - * - * Read Data Eye Training Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read data eye training. - */ -#define DDRPHY_DX_GSR2_REWN_MASK (0x20U) -#define DDRPHY_DX_GSR2_REWN_SHIFT (5U) -#define DDRPHY_DX_GSR2_REWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_REWN_SHIFT) & DDRPHY_DX_GSR2_REWN_MASK) -#define DDRPHY_DX_GSR2_REWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_REWN_MASK) >> DDRPHY_DX_GSR2_REWN_SHIFT) - -/* - * REERR (R/W) - * - * Read Data Eye Training Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read data eye training. - */ -#define DDRPHY_DX_GSR2_REERR_MASK (0x10U) -#define DDRPHY_DX_GSR2_REERR_SHIFT (4U) -#define DDRPHY_DX_GSR2_REERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_REERR_SHIFT) & DDRPHY_DX_GSR2_REERR_MASK) -#define DDRPHY_DX_GSR2_REERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_REERR_MASK) >> DDRPHY_DX_GSR2_REERR_SHIFT) - -/* - * WDWN (R/W) - * - * Write Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the write bit deskew training. - */ -#define DDRPHY_DX_GSR2_WDWN_MASK (0x8U) -#define DDRPHY_DX_GSR2_WDWN_SHIFT (3U) -#define DDRPHY_DX_GSR2_WDWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WDWN_SHIFT) & DDRPHY_DX_GSR2_WDWN_MASK) -#define DDRPHY_DX_GSR2_WDWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WDWN_MASK) >> DDRPHY_DX_GSR2_WDWN_SHIFT) - -/* - * WDERR (R/W) - * - * Write Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the write bit deskew training. - */ -#define DDRPHY_DX_GSR2_WDERR_MASK (0x4U) -#define DDRPHY_DX_GSR2_WDERR_SHIFT (2U) -#define DDRPHY_DX_GSR2_WDERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_WDERR_SHIFT) & DDRPHY_DX_GSR2_WDERR_MASK) -#define DDRPHY_DX_GSR2_WDERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_WDERR_MASK) >> DDRPHY_DX_GSR2_WDERR_SHIFT) - -/* - * RDWN (R/W) - * - * Read Bit Deskew Warning: Indicates, if set, that the DATX8 has encountered a warning during execution of the read bit deskew training. - */ -#define DDRPHY_DX_GSR2_RDWN_MASK (0x2U) -#define DDRPHY_DX_GSR2_RDWN_SHIFT (1U) -#define DDRPHY_DX_GSR2_RDWN_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_RDWN_SHIFT) & DDRPHY_DX_GSR2_RDWN_MASK) -#define DDRPHY_DX_GSR2_RDWN_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_RDWN_MASK) >> DDRPHY_DX_GSR2_RDWN_SHIFT) - -/* - * RDERR (R/W) - * - * Read Bit Deskew Error: Indicates, if set, that the DATX8 has encountered an error during execution of the read bit deskew training. - */ -#define DDRPHY_DX_GSR2_RDERR_MASK (0x1U) -#define DDRPHY_DX_GSR2_RDERR_SHIFT (0U) -#define DDRPHY_DX_GSR2_RDERR_SET(x) (((uint32_t)(x) << DDRPHY_DX_GSR2_RDERR_SHIFT) & DDRPHY_DX_GSR2_RDERR_MASK) -#define DDRPHY_DX_GSR2_RDERR_GET(x) (((uint32_t)(x) & DDRPHY_DX_GSR2_RDERR_MASK) >> DDRPHY_DX_GSR2_RDERR_SHIFT) - - - -/* ZQ register group index macro definition */ -#define DDRPHY_ZQ_0 (0UL) -#define DDRPHY_ZQ_1 (1UL) -#define DDRPHY_ZQ_2 (2UL) -#define DDRPHY_ZQ_3 (3UL) - -/* DX register group index macro definition */ -#define DDRPHY_DX_0 (0UL) -#define DDRPHY_DX_1 (1UL) -#define DDRPHY_DX_2 (2UL) -#define DDRPHY_DX_3 (3UL) -#define DDRPHY_DX_4 (4UL) -#define DDRPHY_DX_5 (5UL) -#define DDRPHY_DX_6 (6UL) -#define DDRPHY_DX_7 (7UL) -#define DDRPHY_DX_8 (8UL) - - -#endif /* HPM_DDRPHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dmamux_regs.h deleted file mode 100644 index 781a9b7a4f8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dmamux_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_H -#define HPM_DMAMUX_H - -typedef struct { - __RW uint32_t MUXCFG[64]; /* 0x0 - 0xFC: HDMA MUX0 Configuration */ -} DMAMUX_Type; - - -/* Bitfield definition for register array: MUXCFG */ -/* - * ENABLE (RW) - * - * DMA Mux Channel Enable - * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be - * used to disable or reconfigure a DMA channel. - * 0b - DMA Mux channel is disabled - * 1b - DMA Mux channel is enabled - */ -#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) -#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) -#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) -#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) - -/* - * SOURCE (RW) - * - * DMA Channel Source - * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - */ -#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) -#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) -#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) - - - -/* MUXCFG register group index macro definition */ -#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) -#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) -#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) -#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) -#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) -#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) -#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) -#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) -#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) -#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) -#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) -#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) -#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) -#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) -#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) -#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) -#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) -#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) -#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) -#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) -#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) -#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) -#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) -#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) -#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) -#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) -#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) -#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) -#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) -#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) -#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) -#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) -#define DMAMUX_MUXCFG_XDMA_MUX0 (32UL) -#define DMAMUX_MUXCFG_XDMA_MUX1 (33UL) -#define DMAMUX_MUXCFG_XDMA_MUX2 (34UL) -#define DMAMUX_MUXCFG_XDMA_MUX3 (35UL) -#define DMAMUX_MUXCFG_XDMA_MUX4 (36UL) -#define DMAMUX_MUXCFG_XDMA_MUX5 (37UL) -#define DMAMUX_MUXCFG_XDMA_MUX6 (38UL) -#define DMAMUX_MUXCFG_XDMA_MUX7 (39UL) -#define DMAMUX_MUXCFG_XDMA_MUX8 (40UL) -#define DMAMUX_MUXCFG_XDMA_MUX9 (41UL) -#define DMAMUX_MUXCFG_XDMA_MUX10 (42UL) -#define DMAMUX_MUXCFG_XDMA_MUX11 (43UL) -#define DMAMUX_MUXCFG_XDMA_MUX12 (44UL) -#define DMAMUX_MUXCFG_XDMA_MUX13 (45UL) -#define DMAMUX_MUXCFG_XDMA_MUX14 (46UL) -#define DMAMUX_MUXCFG_XDMA_MUX15 (47UL) -#define DMAMUX_MUXCFG_XDMA_MUX16 (48UL) -#define DMAMUX_MUXCFG_XDMA_MUX17 (49UL) -#define DMAMUX_MUXCFG_XDMA_MUX18 (50UL) -#define DMAMUX_MUXCFG_XDMA_MUX19 (51UL) -#define DMAMUX_MUXCFG_XDMA_MUX20 (52UL) -#define DMAMUX_MUXCFG_XDMA_MUX21 (53UL) -#define DMAMUX_MUXCFG_XDMA_MUX22 (54UL) -#define DMAMUX_MUXCFG_XDMA_MUX23 (55UL) -#define DMAMUX_MUXCFG_XDMA_MUX24 (56UL) -#define DMAMUX_MUXCFG_XDMA_MUX25 (57UL) -#define DMAMUX_MUXCFG_XDMA_MUX26 (58UL) -#define DMAMUX_MUXCFG_XDMA_MUX27 (59UL) -#define DMAMUX_MUXCFG_XDMA_MUX28 (60UL) -#define DMAMUX_MUXCFG_XDMA_MUX29 (61UL) -#define DMAMUX_MUXCFG_XDMA_MUX30 (62UL) -#define DMAMUX_MUXCFG_XDMA_MUX31 (63UL) - - -#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dmav2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dmav2_regs.h deleted file mode 100644 index dbedcaadb10..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_dmav2_regs.h +++ /dev/null @@ -1,598 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAV2_H -#define HPM_DMAV2_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t IDMISC; /* 0x4: ID Misc */ - __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ - __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */ - __W uint32_t CHABORT; /* 0x18: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */ - __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */ - __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */ - __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */ - __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */ - __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x40: Channel Control Register */ - __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */ - __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */ - __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */ - __R uint8_t RESERVED0[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */ - __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ - } CHCTRL[32]; -} DMAV2_Type; - - -/* Bitfield definition for register: IDMISC */ -/* - * DMASTATE (RO) - * - * DMA state machine - * localparam ST_IDLE = 3'b000; - * localparam ST_READ = 3'b001; - * localparam ST_READ_ACK = 3'b010; - * localparam ST_WRITE = 3'b011; - * localparam ST_WRITE_ACK = 3'b100; - * localparam ST_LL = 3'b101; - * localparam ST_END = 3'b110; - * localparam ST_END_WAIT = 3'b111; - */ -#define DMAV2_IDMISC_DMASTATE_MASK (0xE000U) -#define DMAV2_IDMISC_DMASTATE_SHIFT (13U) -#define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT) - -/* - * CURCHAN (RO) - * - * current channel in used - */ -#define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U) -#define DMAV2_IDMISC_CURCHAN_SHIFT (8U) -#define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT) - -/* Bitfield definition for register: DMACFG */ -/* - * CHAINXFR (RO) - * - * Chain transfer - * 0x0: Chain transfer is not configured - * 0x1: Chain transfer is configured - */ -#define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL) -#define DMAV2_DMACFG_CHAINXFR_SHIFT (31U) -#define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT) - -/* - * REQSYNC (RO) - * - * DMA request synchronization. - * The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, - * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. - * 0x0: Request synchronization is not configured - * 0x1: Request synchronization is configured - */ -#define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL) -#define DMAV2_DMACFG_REQSYNC_SHIFT (30U) -#define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT) - -/* - * DATAWIDTH (RO) - * - * AXI bus data width - * 0x0: 32 bits - * 0x1: 64 bits - * 0x2: 128 bits - * 0x3: 256 bits - */ -#define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL) -#define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U) -#define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT) - -/* - * ADDRWIDTH (RO) - * - * AXI bus address width - * 0x18: 24 bits - * 0x19: 25 bits - * ... - * 0x40: 64 bits - * Others: Invalid - */ -#define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) -#define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U) -#define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT) - -/* - * CORENUM (RO) - * - * DMA core number - * 0x0: 1 core - * 0x1: 2 cores - */ -#define DMAV2_DMACFG_CORENUM_MASK (0x10000UL) -#define DMAV2_DMACFG_CORENUM_SHIFT (16U) -#define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT) - -/* - * BUSNUM (RO) - * - * AXI bus interface number - * 0x0: 1 AXI bus - * 0x1: 2 AXI busses - */ -#define DMAV2_DMACFG_BUSNUM_MASK (0x8000U) -#define DMAV2_DMACFG_BUSNUM_SHIFT (15U) -#define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT) - -/* - * REQNUM (RO) - * - * Request/acknowledge pair number - * 0x0: 0 pair - * 0x1: 1 pair - * 0x2: 2 pairs - * ... - * 0x10: 16 pairs - */ -#define DMAV2_DMACFG_REQNUM_MASK (0x7C00U) -#define DMAV2_DMACFG_REQNUM_SHIFT (10U) -#define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT) - -/* - * FIFODEPTH (RO) - * - * FIFO depth - * 0x4: 4 entries - * 0x8: 8 entries - * 0x10: 16 entries - * 0x20: 32 entries - * Others: Invalid - */ -#define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U) -#define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U) -#define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT) - -/* - * CHANNELNUM (RO) - * - * Channel number - * 0x1: 1 channel - * 0x2: 2 channels - * ... - * 0x8: 8 channels - * Others: Invalid - */ -#define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU) -#define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U) -#define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT) - -/* Bitfield definition for register: DMACTRL */ -/* - * RESET (WO) - * - * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. - * Note: The software reset may cause the in-completion of AXI transaction. - */ -#define DMAV2_DMACTRL_RESET_MASK (0x1U) -#define DMAV2_DMACTRL_RESET_SHIFT (0U) -#define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK) -#define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT) - -/* Bitfield definition for register: CHABORT */ -/* - * CHABORT (WO) - * - * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. - * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - */ -#define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) -#define DMAV2_CHABORT_CHABORT_SHIFT (0U) -#define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK) -#define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT) - -/* Bitfield definition for register: INTHALFSTS */ -/* - * STS (RW) - * - * half transfer done irq status - */ -#define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTHALFSTS_STS_SHIFT (0U) -#define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK) -#define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT) - -/* Bitfield definition for register: INTTCSTS */ -/* - * STS (W1C) - * - * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. - * 0x0: Channel n has no terminal count status - * 0x1: Channel n has terminal count status - */ -#define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTTCSTS_STS_SHIFT (0U) -#define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK) -#define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT) - -/* Bitfield definition for register: INTABORTSTS */ -/* - * STS (W1C) - * - * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. - * 0x0: Channel n has no abort status - * 0x1: Channel n has abort status - */ -#define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTABORTSTS_STS_SHIFT (0U) -#define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK) -#define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT) - -/* Bitfield definition for register: INTERRSTS */ -/* - * STS (W1C) - * - * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - * - Bus error - * - Unaligned address - * - Unaligned transfer width - * - Reserved configuration - * 0x0: Channel n has no error status - * 0x1: Channel n has error status - */ -#define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTERRSTS_STS_SHIFT (0U) -#define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK) -#define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT) - -/* Bitfield definition for register: CHEN */ -/* - * CHEN (RO) - * - * Alias of the Enable field of all ChnCtrl registers - */ -#define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL) -#define DMAV2_CHEN_CHEN_SHIFT (0U) -#define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CTRL */ -/* - * INFINITELOOP (RW) - * - * set to loop current config infinitely - */ -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) - -/* - * HANDSHAKEOPT (RW) - * - * 0: one request to transfer one burst - * 1: one request to transfer all the data defined in ch_tts - */ -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) - -/* - * PRIORITY (RW) - * - * Channel priority level - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) -#define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U) -#define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) -#define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) - -/* - * BURSTOPT (RW) - * - * set to change burst_size definition - */ -#define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. - * The burst transfer byte number is (SrcBurstSize * SrcWidth). - * 0x0: 1 transfer - * 0x1: 2 transfers - * 0x2: 4 transfers - * 0x3: 8 transfers - * 0x4: 16 transfers - * 0x5: 32 transfers - * 0x6: 64 transfers - * 0x7: 128 transfers - * 0x8: 256 transfers - * 0x9:512 transfers - * 0xa: 1024 transfers - * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source transfer width - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination transfer width. - * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; - * otherwise the error event will be triggered. - * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. - * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * Source DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - * Normal mode is enabled and started by software set Enable bit; - * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - */ -#define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) -#define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U) -#define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) -#define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * Destination DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - * the difference bewteen Source/Destination handshake mode is: - * the dma block will response hardware request after read in Source handshake mode; - * the dma block will response hardware request after write in Destination handshake mode; - * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - */ -#define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) -#define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U) -#define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) -#define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * Source address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * Destination address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) - -/* - * INTHALFCNTMASK (RW) - * - * Channel half interrupt mask - * 0x0: Allow the half interrupt to be triggered - * 0x1: Disable the half interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) - -/* - * INTABTMASK (RW) - * - * Channel abort interrupt mask - * 0x0: Allow the abort interrupt to be triggered - * 0x1: Disable the abort interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) - -/* - * INTERRMASK (RW) - * - * Channel error interrupt mask - * 0x0: Allow the error interrupt to be triggered - * 0x1: Disable the error interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) - -/* - * INTTCMASK (RW) - * - * Channel terminal count interrupt mask - * 0x0: Allow the terminal count interrupt to be triggered - * 0x1: Disable the terminal count interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) - -/* - * ENABLE (RW) - * - * Channel enable bit - * 0x0: Disable - * 0x1: Enable - */ -#define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U) -#define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U) -#define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) -#define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ -/* - * TRANSIZE (RW) - * - * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. - * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - */ -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ -/* - * SRCADDRL (RW) - * - * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - */ -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */ -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ -/* - * DSTADDRL (RW) - * - * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - */ -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ -/* - * LLPOINTERL (RW) - * - * Low part of the pointer to the next descriptor. The pointer must be double word aligned. - */ -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) - - - -/* CHCTRL register group index macro definition */ -#define DMAV2_CHCTRL_CH0 (0UL) -#define DMAV2_CHCTRL_CH1 (1UL) -#define DMAV2_CHCTRL_CH2 (2UL) -#define DMAV2_CHCTRL_CH3 (3UL) -#define DMAV2_CHCTRL_CH4 (4UL) -#define DMAV2_CHCTRL_CH5 (5UL) -#define DMAV2_CHCTRL_CH6 (6UL) -#define DMAV2_CHCTRL_CH7 (7UL) -#define DMAV2_CHCTRL_CH8 (8UL) -#define DMAV2_CHCTRL_CH9 (9UL) -#define DMAV2_CHCTRL_CH10 (10UL) -#define DMAV2_CHCTRL_CH11 (11UL) -#define DMAV2_CHCTRL_CH12 (12UL) -#define DMAV2_CHCTRL_CH13 (13UL) -#define DMAV2_CHCTRL_CH14 (14UL) -#define DMAV2_CHCTRL_CH15 (15UL) -#define DMAV2_CHCTRL_CH16 (16UL) -#define DMAV2_CHCTRL_CH17 (17UL) -#define DMAV2_CHCTRL_CH18 (18UL) -#define DMAV2_CHCTRL_CH19 (19UL) -#define DMAV2_CHCTRL_CH20 (20UL) -#define DMAV2_CHCTRL_CH21 (21UL) -#define DMAV2_CHCTRL_CH22 (22UL) -#define DMAV2_CHCTRL_CH23 (23UL) -#define DMAV2_CHCTRL_CH24 (24UL) -#define DMAV2_CHCTRL_CH25 (25UL) -#define DMAV2_CHCTRL_CH26 (26UL) -#define DMAV2_CHCTRL_CH27 (27UL) -#define DMAV2_CHCTRL_CH28 (28UL) -#define DMAV2_CHCTRL_CH29 (29UL) -#define DMAV2_CHCTRL_CH30 (30UL) -#define DMAV2_CHCTRL_CH31 (31UL) - - -#endif /* HPM_DMAV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_enet_regs.h deleted file mode 100644 index 27b298941e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_enet_regs.h +++ /dev/null @@ -1,6143 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ENET_H -#define HPM_ENET_H - -typedef struct { - __RW uint32_t MACCFG; /* 0x0: MAC Configuration Register */ - __RW uint32_t MACFF; /* 0x4: MAC Frame Filter */ - __RW uint32_t HASH_H; /* 0x8: Hash Table High Register */ - __RW uint32_t HASH_L; /* 0xC: Hash Table Low Register */ - __RW uint32_t GMII_ADDR; /* 0x10: GMII Address Register */ - __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ - __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ - __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ - __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ - __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ - __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ - __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Register */ - __RW uint32_t LPI_TCR; /* 0x34: LPI Timers Control Register */ - __R uint32_t INTR_STATUS; /* 0x38: Interrupt Status Register */ - __RW uint32_t INTR_MASK; /* 0x3C: Interrupt Mask Register */ - __RW uint32_t MAC_ADDR_0_HIGH; /* 0x40: MAC Address 0 High Register */ - __RW uint32_t MAC_ADDR_0_LOW; /* 0x44: MAC Address 0 Low Register */ - struct { - __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ - __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ - } MAC_ADDR[4]; - __R uint8_t RESERVED1[112]; /* 0x68 - 0xD7: Reserved */ - __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ - __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ - __R uint8_t RESERVED2[32]; /* 0xE0 - 0xFF: Reserved */ - __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ - __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt */ - __RW uint32_t MMC_INTR_TX; /* 0x108: MMC Transmit Interrupt */ - __RW uint32_t MMC_INTR_MASK_RX; /* 0x10C: MMC Receive Interrupt mask */ - __RW uint32_t MMC_INTR_MASK_TX; /* 0x110: MMC Transmit Interrupt Mask */ - __R uint8_t RESERVED3[16]; /* 0x114 - 0x123: Reserved */ - __RW uint32_t TX64OCTETS_GB; /* 0x124: Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. */ - __RW uint32_t TX65TO127OCTETS_GB; /* 0x128: Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX128TO255OCTETS_GB; /* 0x12C: Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX256TO511OCTETS_GB; /* 0x130: Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX512TO1023OCTETS_GB; /* 0x134: Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. */ - __R uint8_t RESERVED4[68]; /* 0x13C - 0x17F: Reserved */ - __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ - __R uint8_t RESERVED5[124]; /* 0x184 - 0x1FF: Reserved */ - __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. */ - __R uint8_t RESERVED6[4]; /* 0x204 - 0x207: Reserved */ - __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. */ - __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */ - __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload */ - __R uint8_t RESERVED8[492]; /* 0x214 - 0x3FF: Reserved */ - struct { - __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ - __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ - __R uint8_t RESERVED0[8]; /* 0x408 - 0x40F: Reserved */ - __RW uint32_t L3_ADDR_0; /* 0x410: Layer 3 Address 0 Register */ - __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ - __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ - __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ - } L3_L4_CFG[1]; - __R uint8_t RESERVED9[356]; /* 0x420 - 0x583: Reserved */ - __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ - __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ - __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ - __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ - __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ - __R uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ - __R uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ - __RW uint32_t SYST_SEC_UPD; /* 0x710: System Time - Seconds Update Register */ - __RW uint32_t SYST_NSEC_UPD; /* 0x714: System Time - Nanoseconds Update Register */ - __RW uint32_t TS_ADDEND; /* 0x718: Timestamp Addend Register */ - __RW uint32_t TGTTM_SEC; /* 0x71C: Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x720: Target Time Nanoseconds Register */ - __RW uint32_t SYSTM_H_SEC; /* 0x724: System Time - Higher Word Seconds Register */ - __R uint32_t TS_STATUS; /* 0x728: Timestamp Status Register */ - __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ - __R uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ - __R uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ - __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ - __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS Interval Register */ - __RW uint32_t PPS0_WIDTH; /* 0x764: PPS Width Register */ - __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ - struct { - __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ - __RW uint32_t INTERVAL; /* 0x788: PPS Interval Register */ - __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ - __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ - } PPS[3]; - __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ - __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ - __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ - __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ - __RW uint32_t DMA_RX_DESC_LIST_ADDR; /* 0x100C: Receive Descriptor List Address Register */ - __RW uint32_t DMA_TX_DESC_LIST_ADDR; /* 0x1010: Transmit Descriptor List Address Register */ - __RW uint32_t DMA_STATUS; /* 0x1014: Status Register */ - __RW uint32_t DMA_OP_MODE; /* 0x1018: Operation Mode Register */ - __RW uint32_t DMA_INTR_EN; /* 0x101C: Interrupt Enable Register */ - __RW uint32_t DMA_MISS_OVF_CNT; /* 0x1020: Missed Frame And Buffer Overflow Counter Register */ - __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ - __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ - __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ - __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ - __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ - __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ - __R uint8_t RESERVED15[8104]; /* 0x1058 - 0x2FFF: Reserved */ - __RW uint32_t CTRL0; /* 0x3000: Control Register 0 */ - __R uint8_t RESERVED16[4]; /* 0x3004 - 0x3007: Reserved */ - __RW uint32_t CTRL2; /* 0x3008: Control Register 1 */ - __R uint8_t RESERVED17[28]; /* 0x300C - 0x3027: Reserved */ -} ENET_Type; - - -/* Bitfield definition for register: MACCFG */ -/* - * SARC (RW) - * - * Source Address Insertion or Replacement Control - * This field controls the source address insertion or replacement for all transmitted frames. - * Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: - * - 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. - * - 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * - 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * Note: - Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, - * that is, the current frame does not use the updated value. - * - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - */ -#define ENET_MACCFG_SARC_MASK (0x70000000UL) -#define ENET_MACCFG_SARC_SHIFT (28U) -#define ENET_MACCFG_SARC_SET(x) (((uint32_t)(x) << ENET_MACCFG_SARC_SHIFT) & ENET_MACCFG_SARC_MASK) -#define ENET_MACCFG_SARC_GET(x) (((uint32_t)(x) & ENET_MACCFG_SARC_MASK) >> ENET_MACCFG_SARC_SHIFT) - -/* - * TWOKPE (RW) - * - * IEEE 802.3as Support for 2K Packets - * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. - * When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. - * When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. - * When Bit 20 is set, setting this bit has no effect on Giant Frame status. - */ -#define ENET_MACCFG_TWOKPE_MASK (0x8000000UL) -#define ENET_MACCFG_TWOKPE_SHIFT (27U) -#define ENET_MACCFG_TWOKPE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TWOKPE_SHIFT) & ENET_MACCFG_TWOKPE_MASK) -#define ENET_MACCFG_TWOKPE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TWOKPE_MASK) >> ENET_MACCFG_TWOKPE_SHIFT) - -/* - * SFTERR (RW) - * - * SMII Force Transmit Error - * When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_SFTERR_MASK (0x4000000UL) -#define ENET_MACCFG_SFTERR_SHIFT (26U) -#define ENET_MACCFG_SFTERR_SET(x) (((uint32_t)(x) << ENET_MACCFG_SFTERR_SHIFT) & ENET_MACCFG_SFTERR_MASK) -#define ENET_MACCFG_SFTERR_GET(x) (((uint32_t)(x) & ENET_MACCFG_SFTERR_MASK) >> ENET_MACCFG_SFTERR_SHIFT) - -/* - * CST (RW) - * - * CRC Stripping for Type Frames - * When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. - * This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - */ -#define ENET_MACCFG_CST_MASK (0x2000000UL) -#define ENET_MACCFG_CST_SHIFT (25U) -#define ENET_MACCFG_CST_SET(x) (((uint32_t)(x) << ENET_MACCFG_CST_SHIFT) & ENET_MACCFG_CST_MASK) -#define ENET_MACCFG_CST_GET(x) (((uint32_t)(x) & ENET_MACCFG_CST_MASK) >> ENET_MACCFG_CST_SHIFT) - -/* - * TC (RW) - * - * Transmit Configuration in RGMII, SGMII, or SMII - * When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - * or SGMII port. When this bit is reset, no such information is driven to the PHY. - * This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_TC_MASK (0x1000000UL) -#define ENET_MACCFG_TC_SHIFT (24U) -#define ENET_MACCFG_TC_SET(x) (((uint32_t)(x) << ENET_MACCFG_TC_SHIFT) & ENET_MACCFG_TC_MASK) -#define ENET_MACCFG_TC_GET(x) (((uint32_t)(x) & ENET_MACCFG_TC_MASK) >> ENET_MACCFG_TC_SHIFT) - -/* - * WD (RW) - * - * Watchdog Disable - * When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - */ -#define ENET_MACCFG_WD_MASK (0x800000UL) -#define ENET_MACCFG_WD_SHIFT (23U) -#define ENET_MACCFG_WD_SET(x) (((uint32_t)(x) << ENET_MACCFG_WD_SHIFT) & ENET_MACCFG_WD_MASK) -#define ENET_MACCFG_WD_GET(x) (((uint32_t)(x) & ENET_MACCFG_WD_MASK) >> ENET_MACCFG_WD_SHIFT) - -/* - * JD (RW) - * - * Jabber Disable - * When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. - * When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - */ -#define ENET_MACCFG_JD_MASK (0x400000UL) -#define ENET_MACCFG_JD_SHIFT (22U) -#define ENET_MACCFG_JD_SET(x) (((uint32_t)(x) << ENET_MACCFG_JD_SHIFT) & ENET_MACCFG_JD_MASK) -#define ENET_MACCFG_JD_GET(x) (((uint32_t)(x) & ENET_MACCFG_JD_MASK) >> ENET_MACCFG_JD_SHIFT) - -/* - * BE (RW) - * - * Frame Burst Enable - * When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - */ -#define ENET_MACCFG_BE_MASK (0x200000UL) -#define ENET_MACCFG_BE_SHIFT (21U) -#define ENET_MACCFG_BE_SET(x) (((uint32_t)(x) << ENET_MACCFG_BE_SHIFT) & ENET_MACCFG_BE_MASK) -#define ENET_MACCFG_BE_GET(x) (((uint32_t)(x) & ENET_MACCFG_BE_MASK) >> ENET_MACCFG_BE_SHIFT) - -/* - * JE (RW) - * - * Jumbo Frame Enable - * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - */ -#define ENET_MACCFG_JE_MASK (0x100000UL) -#define ENET_MACCFG_JE_SHIFT (20U) -#define ENET_MACCFG_JE_SET(x) (((uint32_t)(x) << ENET_MACCFG_JE_SHIFT) & ENET_MACCFG_JE_MASK) -#define ENET_MACCFG_JE_GET(x) (((uint32_t)(x) & ENET_MACCFG_JE_MASK) >> ENET_MACCFG_JE_SHIFT) - -/* - * IFG (RW) - * - * Inter-Frame Gap - * These bits control the minimum IFG between frames during transmission. - * - 000: 96 bit times - * - 001: 88 bit times - * - 010: 80 bit times - ... - * - 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). - * Lower values are not considered. - * In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - * When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - */ -#define ENET_MACCFG_IFG_MASK (0xE0000UL) -#define ENET_MACCFG_IFG_SHIFT (17U) -#define ENET_MACCFG_IFG_SET(x) (((uint32_t)(x) << ENET_MACCFG_IFG_SHIFT) & ENET_MACCFG_IFG_MASK) -#define ENET_MACCFG_IFG_GET(x) (((uint32_t)(x) & ENET_MACCFG_IFG_MASK) >> ENET_MACCFG_IFG_SHIFT) - -/* - * DCRS (RW) - * - * Disable Carrier Sense During Transmission - * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - * This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. - * When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - */ -#define ENET_MACCFG_DCRS_MASK (0x10000UL) -#define ENET_MACCFG_DCRS_SHIFT (16U) -#define ENET_MACCFG_DCRS_SET(x) (((uint32_t)(x) << ENET_MACCFG_DCRS_SHIFT) & ENET_MACCFG_DCRS_MASK) -#define ENET_MACCFG_DCRS_GET(x) (((uint32_t)(x) & ENET_MACCFG_DCRS_MASK) >> ENET_MACCFG_DCRS_SHIFT) - -/* - * PS (RW) - * - * Port Select - * This bit selects the Ethernet line speed. - * - 0: For 1000 Mbps operations - * - 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. - * In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, - * this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - */ -#define ENET_MACCFG_PS_MASK (0x8000U) -#define ENET_MACCFG_PS_SHIFT (15U) -#define ENET_MACCFG_PS_SET(x) (((uint32_t)(x) << ENET_MACCFG_PS_SHIFT) & ENET_MACCFG_PS_MASK) -#define ENET_MACCFG_PS_GET(x) (((uint32_t)(x) & ENET_MACCFG_PS_MASK) >> ENET_MACCFG_PS_SHIFT) - -/* - * FES (RW) - * - * Speed - * This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: - * - 0: 10 Mbps - * - 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. - * This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. - * This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. - * In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. - * In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - */ -#define ENET_MACCFG_FES_MASK (0x4000U) -#define ENET_MACCFG_FES_SHIFT (14U) -#define ENET_MACCFG_FES_SET(x) (((uint32_t)(x) << ENET_MACCFG_FES_SHIFT) & ENET_MACCFG_FES_MASK) -#define ENET_MACCFG_FES_GET(x) (((uint32_t)(x) & ENET_MACCFG_FES_MASK) >> ENET_MACCFG_FES_SHIFT) - -/* - * DO (RW) - * - * Disable Receive Own - * When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. - * When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. - * This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - */ -#define ENET_MACCFG_DO_MASK (0x2000U) -#define ENET_MACCFG_DO_SHIFT (13U) -#define ENET_MACCFG_DO_SET(x) (((uint32_t)(x) << ENET_MACCFG_DO_SHIFT) & ENET_MACCFG_DO_MASK) -#define ENET_MACCFG_DO_GET(x) (((uint32_t)(x) & ENET_MACCFG_DO_MASK) >> ENET_MACCFG_DO_SHIFT) - -/* - * LM (RW) - * - * Loopback Mode - * When this bit is set, the MAC operates in the loopback mode at GMII or MII. - * The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - */ -#define ENET_MACCFG_LM_MASK (0x1000U) -#define ENET_MACCFG_LM_SHIFT (12U) -#define ENET_MACCFG_LM_SET(x) (((uint32_t)(x) << ENET_MACCFG_LM_SHIFT) & ENET_MACCFG_LM_MASK) -#define ENET_MACCFG_LM_GET(x) (((uint32_t)(x) & ENET_MACCFG_LM_MASK) >> ENET_MACCFG_LM_SHIFT) - -/* - * DM (RW) - * - * Duplex Mode - * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - */ -#define ENET_MACCFG_DM_MASK (0x800U) -#define ENET_MACCFG_DM_SHIFT (11U) -#define ENET_MACCFG_DM_SET(x) (((uint32_t)(x) << ENET_MACCFG_DM_SHIFT) & ENET_MACCFG_DM_MASK) -#define ENET_MACCFG_DM_GET(x) (((uint32_t)(x) & ENET_MACCFG_DM_MASK) >> ENET_MACCFG_DM_SHIFT) - -/* - * IPC (RW) - * - * Checksum Offload - * When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. - * It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) - * of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. - * The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) - * and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). - * When this bit is reset, this function is disabled. - * When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - */ -#define ENET_MACCFG_IPC_MASK (0x400U) -#define ENET_MACCFG_IPC_SHIFT (10U) -#define ENET_MACCFG_IPC_SET(x) (((uint32_t)(x) << ENET_MACCFG_IPC_SHIFT) & ENET_MACCFG_IPC_MASK) -#define ENET_MACCFG_IPC_GET(x) (((uint32_t)(x) & ENET_MACCFG_IPC_MASK) >> ENET_MACCFG_IPC_SHIFT) - -/* - * DR (RW) - * - * Disable Retry - * When this bit is set, the MAC attempts only one transmission. - * When a collision occurs on the GMII or MII interface, - * the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. - * When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - */ -#define ENET_MACCFG_DR_MASK (0x200U) -#define ENET_MACCFG_DR_SHIFT (9U) -#define ENET_MACCFG_DR_SET(x) (((uint32_t)(x) << ENET_MACCFG_DR_SHIFT) & ENET_MACCFG_DR_MASK) -#define ENET_MACCFG_DR_GET(x) (((uint32_t)(x) & ENET_MACCFG_DR_MASK) >> ENET_MACCFG_DR_SHIFT) - -/* - * LUD (RW) - * - * Link Up or Down - * This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: - * - 0: Link Down - * - 1: Link Up - */ -#define ENET_MACCFG_LUD_MASK (0x100U) -#define ENET_MACCFG_LUD_SHIFT (8U) -#define ENET_MACCFG_LUD_SET(x) (((uint32_t)(x) << ENET_MACCFG_LUD_SHIFT) & ENET_MACCFG_LUD_MASK) -#define ENET_MACCFG_LUD_GET(x) (((uint32_t)(x) & ENET_MACCFG_LUD_MASK) >> ENET_MACCFG_LUD_SHIFT) - -/* - * ACS (RW) - * - * Automatic Pad or CRC Stripping - * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. - * All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. - * When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - */ -#define ENET_MACCFG_ACS_MASK (0x80U) -#define ENET_MACCFG_ACS_SHIFT (7U) -#define ENET_MACCFG_ACS_SET(x) (((uint32_t)(x) << ENET_MACCFG_ACS_SHIFT) & ENET_MACCFG_ACS_MASK) -#define ENET_MACCFG_ACS_GET(x) (((uint32_t)(x) & ENET_MACCFG_ACS_MASK) >> ENET_MACCFG_ACS_SHIFT) - -/* - * BL (RW) - * - * Back-Off Limit - * The Back-Off limit determines the random integer number (r) of slot time delays - * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. - * This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. - * - 00: k= min (n, 10) - * - 01: k = min (n, 8) - * - 10: k = min (n, 4) - * - 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - */ -#define ENET_MACCFG_BL_MASK (0x60U) -#define ENET_MACCFG_BL_SHIFT (5U) -#define ENET_MACCFG_BL_SET(x) (((uint32_t)(x) << ENET_MACCFG_BL_SHIFT) & ENET_MACCFG_BL_MASK) -#define ENET_MACCFG_BL_GET(x) (((uint32_t)(x) & ENET_MACCFG_BL_MASK) >> ENET_MACCFG_BL_SHIFT) - -/* - * DC (RW) - * - * Deferral Check - * When this bit is set, the deferral check function is enabled in the MAC. - * The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, - * when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - * If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - * the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, - * but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. - * For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, - * the transmitter transmits and collision happens. - * Because of collision, the transmitter needs to back off and then defer again after back off completion. - * In such a scenario, the deferral timer is reset to 0 and it is restarted. - */ -#define ENET_MACCFG_DC_MASK (0x10U) -#define ENET_MACCFG_DC_SHIFT (4U) -#define ENET_MACCFG_DC_SET(x) (((uint32_t)(x) << ENET_MACCFG_DC_SHIFT) & ENET_MACCFG_DC_MASK) -#define ENET_MACCFG_DC_GET(x) (((uint32_t)(x) & ENET_MACCFG_DC_MASK) >> ENET_MACCFG_DC_SHIFT) - -/* - * TE (RW) - * - * Transmitter Enable - * When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - * the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - */ -#define ENET_MACCFG_TE_MASK (0x8U) -#define ENET_MACCFG_TE_SHIFT (3U) -#define ENET_MACCFG_TE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TE_SHIFT) & ENET_MACCFG_TE_MASK) -#define ENET_MACCFG_TE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TE_MASK) >> ENET_MACCFG_TE_SHIFT) - -/* - * RE (RW) - * - * Receiver Enable - * When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, - * the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - */ -#define ENET_MACCFG_RE_MASK (0x4U) -#define ENET_MACCFG_RE_SHIFT (2U) -#define ENET_MACCFG_RE_SET(x) (((uint32_t)(x) << ENET_MACCFG_RE_SHIFT) & ENET_MACCFG_RE_MASK) -#define ENET_MACCFG_RE_GET(x) (((uint32_t)(x) & ENET_MACCFG_RE_MASK) >> ENET_MACCFG_RE_SHIFT) - -/* - * PRELEN (RW) - * - * Preamble Length for Transmit frames - * These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - * The preamble reduction occurs only when the MAC is operating in the full-duplex mode. - * - 2'b00: 7 bytes of preamble - * - 2'b01: 5 bytes of preamble - * - 2'b10: 3 bytes of preamble - * - 2'b11: Reserved - */ -#define ENET_MACCFG_PRELEN_MASK (0x3U) -#define ENET_MACCFG_PRELEN_SHIFT (0U) -#define ENET_MACCFG_PRELEN_SET(x) (((uint32_t)(x) << ENET_MACCFG_PRELEN_SHIFT) & ENET_MACCFG_PRELEN_MASK) -#define ENET_MACCFG_PRELEN_GET(x) (((uint32_t)(x) & ENET_MACCFG_PRELEN_MASK) >> ENET_MACCFG_PRELEN_SHIFT) - -/* Bitfield definition for register: MACFF */ -/* - * RA (RW) - * - * Receive All - * When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. - * The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, - * the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - */ -#define ENET_MACFF_RA_MASK (0x80000000UL) -#define ENET_MACFF_RA_SHIFT (31U) -#define ENET_MACFF_RA_SET(x) (((uint32_t)(x) << ENET_MACFF_RA_SHIFT) & ENET_MACFF_RA_MASK) -#define ENET_MACFF_RA_GET(x) (((uint32_t)(x) & ENET_MACFF_RA_MASK) >> ENET_MACFF_RA_SHIFT) - -/* - * DNTU (RW) - * - * Drop non-TCP/UDP over IP Frames - * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. - * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - */ -#define ENET_MACFF_DNTU_MASK (0x200000UL) -#define ENET_MACFF_DNTU_SHIFT (21U) -#define ENET_MACFF_DNTU_SET(x) (((uint32_t)(x) << ENET_MACFF_DNTU_SHIFT) & ENET_MACFF_DNTU_MASK) -#define ENET_MACFF_DNTU_GET(x) (((uint32_t)(x) & ENET_MACFF_DNTU_MASK) >> ENET_MACFF_DNTU_SHIFT) - -/* - * IPFE (RW) - * - * Layer 3 and Layer 4 Filter Enable - * When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, - * this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - */ -#define ENET_MACFF_IPFE_MASK (0x100000UL) -#define ENET_MACFF_IPFE_SHIFT (20U) -#define ENET_MACFF_IPFE_SET(x) (((uint32_t)(x) << ENET_MACFF_IPFE_SHIFT) & ENET_MACFF_IPFE_MASK) -#define ENET_MACFF_IPFE_GET(x) (((uint32_t)(x) & ENET_MACFF_IPFE_MASK) >> ENET_MACFF_IPFE_SHIFT) - -/* - * VTFE (RW) - * - * VLAN Tag Filter Enable - * When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. - * When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - */ -#define ENET_MACFF_VTFE_MASK (0x8000U) -#define ENET_MACFF_VTFE_SHIFT (15U) -#define ENET_MACFF_VTFE_SET(x) (((uint32_t)(x) << ENET_MACFF_VTFE_SHIFT) & ENET_MACFF_VTFE_MASK) -#define ENET_MACFF_VTFE_GET(x) (((uint32_t)(x) & ENET_MACFF_VTFE_MASK) >> ENET_MACFF_VTFE_SHIFT) - -/* - * HPF (RW) - * - * Hash or Perfect Filter - * When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. - * When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - */ -#define ENET_MACFF_HPF_MASK (0x400U) -#define ENET_MACFF_HPF_SHIFT (10U) -#define ENET_MACFF_HPF_SET(x) (((uint32_t)(x) << ENET_MACFF_HPF_SHIFT) & ENET_MACFF_HPF_MASK) -#define ENET_MACFF_HPF_GET(x) (((uint32_t)(x) & ENET_MACFF_HPF_MASK) >> ENET_MACFF_HPF_SHIFT) - -/* - * SAF (RW) - * - * Source Address Filter Enable - * When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - * the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - */ -#define ENET_MACFF_SAF_MASK (0x200U) -#define ENET_MACFF_SAF_SHIFT (9U) -#define ENET_MACFF_SAF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAF_SHIFT) & ENET_MACFF_SAF_MASK) -#define ENET_MACFF_SAF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAF_MASK) >> ENET_MACFF_SAF_SHIFT) - -/* - * SAIF (RW) - * - * SA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. - * When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - */ -#define ENET_MACFF_SAIF_MASK (0x100U) -#define ENET_MACFF_SAIF_SHIFT (8U) -#define ENET_MACFF_SAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAIF_SHIFT) & ENET_MACFF_SAIF_MASK) -#define ENET_MACFF_SAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAIF_MASK) >> ENET_MACFF_SAIF_SHIFT) - -/* - * PCF (RW) - * - * Pass Control Frames - * These bits control the forwarding of all control frames (including unicast and multicast Pause frames). - * - 00: MAC filters all control frames from reaching the application. - * - 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. - * - 10: MAC forwards all control frames to application even if they fail the Address Filter. - * - 11: MAC forwards control frames that pass the Address Filter. - * The following conditions should be true for the Pause frames processing: - * - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - * - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - * - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. - * Note: This field should be set to 01 only when the Condition 1 is true, - * that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. - * Otherwise, the Pause frame filtering may be inconsistent. - * When Condition 1 is false, the Pause frames are considered as generic control frames. - * Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, - * you should set the PCF field to 10 or 11 (as required by the application). - */ -#define ENET_MACFF_PCF_MASK (0xC0U) -#define ENET_MACFF_PCF_SHIFT (6U) -#define ENET_MACFF_PCF_SET(x) (((uint32_t)(x) << ENET_MACFF_PCF_SHIFT) & ENET_MACFF_PCF_MASK) -#define ENET_MACFF_PCF_GET(x) (((uint32_t)(x) & ENET_MACFF_PCF_MASK) >> ENET_MACFF_PCF_SHIFT) - -/* - * DBF (RW) - * - * Disable Broadcast Frames - * When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. - * When this bit is reset, the AFM module passes all received broadcast frames. - */ -#define ENET_MACFF_DBF_MASK (0x20U) -#define ENET_MACFF_DBF_SHIFT (5U) -#define ENET_MACFF_DBF_SET(x) (((uint32_t)(x) << ENET_MACFF_DBF_SHIFT) & ENET_MACFF_DBF_MASK) -#define ENET_MACFF_DBF_GET(x) (((uint32_t)(x) & ENET_MACFF_DBF_MASK) >> ENET_MACFF_DBF_SHIFT) - -/* - * PM (RW) - * - * Pass All Multicast - * When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. - * When reset, filtering of multicast frame depends on HMC bit. - */ -#define ENET_MACFF_PM_MASK (0x10U) -#define ENET_MACFF_PM_SHIFT (4U) -#define ENET_MACFF_PM_SET(x) (((uint32_t)(x) << ENET_MACFF_PM_SHIFT) & ENET_MACFF_PM_MASK) -#define ENET_MACFF_PM_GET(x) (((uint32_t)(x) & ENET_MACFF_PM_MASK) >> ENET_MACFF_PM_SHIFT) - -/* - * DAIF (RW) - * - * DA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. - * When reset, normal filtering of frames is performed. - */ -#define ENET_MACFF_DAIF_MASK (0x8U) -#define ENET_MACFF_DAIF_SHIFT (3U) -#define ENET_MACFF_DAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_DAIF_SHIFT) & ENET_MACFF_DAIF_MASK) -#define ENET_MACFF_DAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_DAIF_MASK) >> ENET_MACFF_DAIF_SHIFT) - -/* - * HMC (RW) - * - * Hash Multicast - * When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, - * the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HMC_MASK (0x4U) -#define ENET_MACFF_HMC_SHIFT (2U) -#define ENET_MACFF_HMC_SET(x) (((uint32_t)(x) << ENET_MACFF_HMC_SHIFT) & ENET_MACFF_HMC_MASK) -#define ENET_MACFF_HMC_GET(x) (((uint32_t)(x) & ENET_MACFF_HMC_MASK) >> ENET_MACFF_HMC_SHIFT) - -/* - * HUC (RW) - * - * Hash Unicast - * When set, the MAC performs destination address filtering of unicast frames according to the hash table. - * When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HUC_MASK (0x2U) -#define ENET_MACFF_HUC_SHIFT (1U) -#define ENET_MACFF_HUC_SET(x) (((uint32_t)(x) << ENET_MACFF_HUC_SHIFT) & ENET_MACFF_HUC_MASK) -#define ENET_MACFF_HUC_GET(x) (((uint32_t)(x) & ENET_MACFF_HUC_MASK) >> ENET_MACFF_HUC_SHIFT) - -/* - * PR (RW) - * - * Promiscuous Mode - * When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - * The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - */ -#define ENET_MACFF_PR_MASK (0x1U) -#define ENET_MACFF_PR_SHIFT (0U) -#define ENET_MACFF_PR_SET(x) (((uint32_t)(x) << ENET_MACFF_PR_SHIFT) & ENET_MACFF_PR_MASK) -#define ENET_MACFF_PR_GET(x) (((uint32_t)(x) & ENET_MACFF_PR_MASK) >> ENET_MACFF_PR_SHIFT) - -/* Bitfield definition for register: HASH_H */ -/* - * HTH (RW) - * - * Hash Table High - * This field contains the upper 32 bits of the Hash table. - */ -#define ENET_HASH_H_HTH_MASK (0xFFFFFFFFUL) -#define ENET_HASH_H_HTH_SHIFT (0U) -#define ENET_HASH_H_HTH_SET(x) (((uint32_t)(x) << ENET_HASH_H_HTH_SHIFT) & ENET_HASH_H_HTH_MASK) -#define ENET_HASH_H_HTH_GET(x) (((uint32_t)(x) & ENET_HASH_H_HTH_MASK) >> ENET_HASH_H_HTH_SHIFT) - -/* Bitfield definition for register: HASH_L */ -/* - * HTL (RW) - * - * Hash Table Low - * This field contains the lower 32 bits of the Hash table. - */ -#define ENET_HASH_L_HTL_MASK (0xFFFFFFFFUL) -#define ENET_HASH_L_HTL_SHIFT (0U) -#define ENET_HASH_L_HTL_SET(x) (((uint32_t)(x) << ENET_HASH_L_HTL_SHIFT) & ENET_HASH_L_HTL_MASK) -#define ENET_HASH_L_HTL_GET(x) (((uint32_t)(x) & ENET_HASH_L_HTL_MASK) >> ENET_HASH_L_HTL_SHIFT) - -/* Bitfield definition for register: GMII_ADDR */ -/* - * PA (RW) - * - * Physical Layer Address - * This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - */ -#define ENET_GMII_ADDR_PA_MASK (0xF800U) -#define ENET_GMII_ADDR_PA_SHIFT (11U) -#define ENET_GMII_ADDR_PA_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_PA_SHIFT) & ENET_GMII_ADDR_PA_MASK) -#define ENET_GMII_ADDR_PA_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_PA_MASK) >> ENET_GMII_ADDR_PA_SHIFT) - -/* - * GR (RW) - * - * GMII Register - * These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - */ -#define ENET_GMII_ADDR_GR_MASK (0x7C0U) -#define ENET_GMII_ADDR_GR_SHIFT (6U) -#define ENET_GMII_ADDR_GR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GR_SHIFT) & ENET_GMII_ADDR_GR_MASK) -#define ENET_GMII_ADDR_GR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GR_MASK) >> ENET_GMII_ADDR_GR_SHIFT) - -/* - * CR (RW) - * - * CSR Clock Range - * The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. - * The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. - * The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) - * ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. - * - 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. - * - 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. - * - 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. - * - 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. - * - 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. - * - 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. - * - 0110, 0111: Reserved - * When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. - * For example, - * when CSR clock is of 100 MHz frequency and you program these bits as 1010, - * then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. - * Program the following values only if the interfacing chips support faster MDC clocks. - * - 1000: CSR clock/4 - * - 1001: CSR clock/6 - * - 1010: CSR clock/8 - * - 1011: CSR clock/10 - * - 1100: CSR clock/12 - * - 1101: CSR clock/14 - * - 1110: CSR clock/16 - * - 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - */ -#define ENET_GMII_ADDR_CR_MASK (0x3CU) -#define ENET_GMII_ADDR_CR_SHIFT (2U) -#define ENET_GMII_ADDR_CR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_CR_SHIFT) & ENET_GMII_ADDR_CR_MASK) -#define ENET_GMII_ADDR_CR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_CR_MASK) >> ENET_GMII_ADDR_CR_SHIFT) - -/* - * GW (RW) - * - * GMII Write - * When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, - * it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - */ -#define ENET_GMII_ADDR_GW_MASK (0x2U) -#define ENET_GMII_ADDR_GW_SHIFT (1U) -#define ENET_GMII_ADDR_GW_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GW_SHIFT) & ENET_GMII_ADDR_GW_MASK) -#define ENET_GMII_ADDR_GW_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GW_MASK) >> ENET_GMII_ADDR_GW_SHIFT) - -/* - * GB (RW) - * - * GMII Busy - * This bit should read logic 0 before writing to Register 4 and Register 5. - * During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - * Register 5 is invalid until this bit is cleared by the MAC. - * Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. - * Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. - * The subsequent read or write operation should happen only after the previous operation is complete. - * Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, - * there is no change in the functionality of this bit even when the PHY is not present. - */ -#define ENET_GMII_ADDR_GB_MASK (0x1U) -#define ENET_GMII_ADDR_GB_SHIFT (0U) -#define ENET_GMII_ADDR_GB_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GB_SHIFT) & ENET_GMII_ADDR_GB_MASK) -#define ENET_GMII_ADDR_GB_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GB_MASK) >> ENET_GMII_ADDR_GB_SHIFT) - -/* Bitfield definition for register: GMII_DATA */ -/* - * GD (RW) - * - * GMII Data - * This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation - * or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - */ -#define ENET_GMII_DATA_GD_MASK (0xFFFFU) -#define ENET_GMII_DATA_GD_SHIFT (0U) -#define ENET_GMII_DATA_GD_SET(x) (((uint32_t)(x) << ENET_GMII_DATA_GD_SHIFT) & ENET_GMII_DATA_GD_MASK) -#define ENET_GMII_DATA_GD_GET(x) (((uint32_t)(x) & ENET_GMII_DATA_GD_MASK) >> ENET_GMII_DATA_GD_SHIFT) - -/* Bitfield definition for register: FLOWCTRL */ -/* - * PT (RW) - * - * Pause Time - * This field holds the value to be used in the Pause Time field in the transmit control frame. - * If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - * then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - */ -#define ENET_FLOWCTRL_PT_MASK (0xFFFF0000UL) -#define ENET_FLOWCTRL_PT_SHIFT (16U) -#define ENET_FLOWCTRL_PT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PT_SHIFT) & ENET_FLOWCTRL_PT_MASK) -#define ENET_FLOWCTRL_PT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PT_MASK) >> ENET_FLOWCTRL_PT_SHIFT) - -/* - * DZPQ (RW) - * - * Disable Zero-Quanta Pause - * When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of - * the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). - * When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - */ -#define ENET_FLOWCTRL_DZPQ_MASK (0x80U) -#define ENET_FLOWCTRL_DZPQ_SHIFT (7U) -#define ENET_FLOWCTRL_DZPQ_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_DZPQ_SHIFT) & ENET_FLOWCTRL_DZPQ_MASK) -#define ENET_FLOWCTRL_DZPQ_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_DZPQ_MASK) >> ENET_FLOWCTRL_DZPQ_SHIFT) - -/* - * PLT (RW) - * - * Pause Low Threshold - * This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. - * The threshold values should be always less than the Pause Time configured in Bits[31:16]. - * For example, if PT = 100H (256 slot-times), and PLT = 01, - * then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. - * The following list provides the threshold values for different values: - * - 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). - * - 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). - * - 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). - * - 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - */ -#define ENET_FLOWCTRL_PLT_MASK (0x30U) -#define ENET_FLOWCTRL_PLT_SHIFT (4U) -#define ENET_FLOWCTRL_PLT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PLT_SHIFT) & ENET_FLOWCTRL_PLT_MASK) -#define ENET_FLOWCTRL_PLT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PLT_MASK) >> ENET_FLOWCTRL_PLT_SHIFT) - -/* - * UP (RW) - * - * Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. - * When this bit is set, the MAC can also detect Pause frames with unicast address of the station. - * This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. - * When this bit is reset, the MAC only detects Pause frames with unique multicast address. - */ -#define ENET_FLOWCTRL_UP_MASK (0x8U) -#define ENET_FLOWCTRL_UP_SHIFT (3U) -#define ENET_FLOWCTRL_UP_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_UP_SHIFT) & ENET_FLOWCTRL_UP_MASK) -#define ENET_FLOWCTRL_UP_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_UP_MASK) >> ENET_FLOWCTRL_UP_SHIFT) - -/* - * RFE (RW) - * - * Receive Flow Control Enable - * When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - */ -#define ENET_FLOWCTRL_RFE_MASK (0x4U) -#define ENET_FLOWCTRL_RFE_SHIFT (2U) -#define ENET_FLOWCTRL_RFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_RFE_SHIFT) & ENET_FLOWCTRL_RFE_MASK) -#define ENET_FLOWCTRL_RFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_RFE_MASK) >> ENET_FLOWCTRL_RFE_SHIFT) - -/* - * TFE (RW) - * - * Transmit Flow Control Enable - * In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. - * When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. - * In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - */ -#define ENET_FLOWCTRL_TFE_MASK (0x2U) -#define ENET_FLOWCTRL_TFE_SHIFT (1U) -#define ENET_FLOWCTRL_TFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_TFE_SHIFT) & ENET_FLOWCTRL_TFE_MASK) -#define ENET_FLOWCTRL_TFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_TFE_MASK) >> ENET_FLOWCTRL_TFE_SHIFT) - -/* - * FCB_BPA (RW) - * - * Flow Control Busy or Backpressure Activate - * This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. - * In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - * To initiate a Pause frame, the Application must set this bit to 1'b1. - * During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. - * After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. - * The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, - * when this bit is set (and TFE is set), then backpressure is asserted by the MAC. - * During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. - * This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. - * When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - */ -#define ENET_FLOWCTRL_FCB_BPA_MASK (0x1U) -#define ENET_FLOWCTRL_FCB_BPA_SHIFT (0U) -#define ENET_FLOWCTRL_FCB_BPA_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_FCB_BPA_SHIFT) & ENET_FLOWCTRL_FCB_BPA_MASK) -#define ENET_FLOWCTRL_FCB_BPA_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_FCB_BPA_MASK) >> ENET_FLOWCTRL_FCB_BPA_SHIFT) - -/* Bitfield definition for register: VLAN_TAG */ -/* - * VTHM (RW) - * - * VLAN Tag Hash Table Match Enable - * When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). - * A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. - * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, - * the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - */ -#define ENET_VLAN_TAG_VTHM_MASK (0x80000UL) -#define ENET_VLAN_TAG_VTHM_SHIFT (19U) -#define ENET_VLAN_TAG_VTHM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTHM_SHIFT) & ENET_VLAN_TAG_VTHM_MASK) -#define ENET_VLAN_TAG_VTHM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTHM_MASK) >> ENET_VLAN_TAG_VTHM_SHIFT) - -/* - * ESVL (RW) - * - * Enable S-VLAN - * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - */ -#define ENET_VLAN_TAG_ESVL_MASK (0x40000UL) -#define ENET_VLAN_TAG_ESVL_SHIFT (18U) -#define ENET_VLAN_TAG_ESVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ESVL_SHIFT) & ENET_VLAN_TAG_ESVL_MASK) -#define ENET_VLAN_TAG_ESVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ESVL_MASK) >> ENET_VLAN_TAG_ESVL_SHIFT) - -/* - * VTIM (RW) - * - * VLAN Tag Inverse Match Enable - * When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - * The frames with matched VLAN Tag are marked as matched. - */ -#define ENET_VLAN_TAG_VTIM_MASK (0x20000UL) -#define ENET_VLAN_TAG_VTIM_SHIFT (17U) -#define ENET_VLAN_TAG_VTIM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTIM_SHIFT) & ENET_VLAN_TAG_VTIM_MASK) -#define ENET_VLAN_TAG_VTIM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTIM_MASK) >> ENET_VLAN_TAG_VTIM_SHIFT) - -/* - * ETV (RW) - * - * Enable 12-Bit VLAN Tag Comparison - * When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - * Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, - * only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. - * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - */ -#define ENET_VLAN_TAG_ETV_MASK (0x10000UL) -#define ENET_VLAN_TAG_ETV_SHIFT (16U) -#define ENET_VLAN_TAG_ETV_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ETV_SHIFT) & ENET_VLAN_TAG_ETV_MASK) -#define ENET_VLAN_TAG_ETV_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ETV_MASK) >> ENET_VLAN_TAG_ETV_SHIFT) - -/* - * VL (RW) - * - * VLAN Tag Identifier for Receive Frames - * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. - * The following list describes the bits of this field: - * - Bits [15:13]: User Priority - * - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - * - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - * and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - */ -#define ENET_VLAN_TAG_VL_MASK (0xFFFFU) -#define ENET_VLAN_TAG_VL_SHIFT (0U) -#define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) -#define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) - -/* Bitfield definition for register: RWKFRMFILT */ -/* - * WKUPFRMFILT (RW) - * - * This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). - * The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. - * The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. - * Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - * Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - */ -#define ENET_RWKFRMFILT_WKUPFRMFILT_MASK (0xFFFFFFFFUL) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT (0U) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SET(x) (((uint32_t)(x) << ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) -#define ENET_RWKFRMFILT_WKUPFRMFILT_GET(x) (((uint32_t)(x) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) >> ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) - -/* Bitfield definition for register: PMT_CSR */ -/* - * RWKFILTRST (RW) - * - * Remote Wake-Up Frame Filter Register Pointer Reset - * When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - */ -#define ENET_PMT_CSR_RWKFILTRST_MASK (0x80000000UL) -#define ENET_PMT_CSR_RWKFILTRST_SHIFT (31U) -#define ENET_PMT_CSR_RWKFILTRST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKFILTRST_SHIFT) & ENET_PMT_CSR_RWKFILTRST_MASK) -#define ENET_PMT_CSR_RWKFILTRST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKFILTRST_MASK) >> ENET_PMT_CSR_RWKFILTRST_SHIFT) - -/* - * RWKPTR (RW) - * - * Remote Wake-up FIFO Pointer - * This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, - * the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - * The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - */ -#define ENET_PMT_CSR_RWKPTR_MASK (0x1F000000UL) -#define ENET_PMT_CSR_RWKPTR_SHIFT (24U) -#define ENET_PMT_CSR_RWKPTR_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPTR_SHIFT) & ENET_PMT_CSR_RWKPTR_MASK) -#define ENET_PMT_CSR_RWKPTR_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPTR_MASK) >> ENET_PMT_CSR_RWKPTR_SHIFT) - -/* - * GLBLUCAST (RW) - * - * Global Unicast - * When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - */ -#define ENET_PMT_CSR_GLBLUCAST_MASK (0x200U) -#define ENET_PMT_CSR_GLBLUCAST_SHIFT (9U) -#define ENET_PMT_CSR_GLBLUCAST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_GLBLUCAST_SHIFT) & ENET_PMT_CSR_GLBLUCAST_MASK) -#define ENET_PMT_CSR_GLBLUCAST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_GLBLUCAST_MASK) >> ENET_PMT_CSR_GLBLUCAST_SHIFT) - -/* - * RWKPRCVD (RW) - * - * Remote Wake-Up Frame Received - * When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_RWKPRCVD_MASK (0x40U) -#define ENET_PMT_CSR_RWKPRCVD_SHIFT (6U) -#define ENET_PMT_CSR_RWKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPRCVD_SHIFT) & ENET_PMT_CSR_RWKPRCVD_MASK) -#define ENET_PMT_CSR_RWKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPRCVD_MASK) >> ENET_PMT_CSR_RWKPRCVD_SHIFT) - -/* - * MGKPRCVD (RW) - * - * Magic Packet Received - * When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_MGKPRCVD_MASK (0x20U) -#define ENET_PMT_CSR_MGKPRCVD_SHIFT (5U) -#define ENET_PMT_CSR_MGKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPRCVD_SHIFT) & ENET_PMT_CSR_MGKPRCVD_MASK) -#define ENET_PMT_CSR_MGKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPRCVD_MASK) >> ENET_PMT_CSR_MGKPRCVD_SHIFT) - -/* - * RWKPKTEN (RW) - * - * Remote Wake-Up Frame Enable - * When set, enables generation of a power management event because of remote wake-up frame reception. - */ -#define ENET_PMT_CSR_RWKPKTEN_MASK (0x4U) -#define ENET_PMT_CSR_RWKPKTEN_SHIFT (2U) -#define ENET_PMT_CSR_RWKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPKTEN_SHIFT) & ENET_PMT_CSR_RWKPKTEN_MASK) -#define ENET_PMT_CSR_RWKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPKTEN_MASK) >> ENET_PMT_CSR_RWKPKTEN_SHIFT) - -/* - * MGKPKTEN (RW) - * - * Magic Packet Enable - * When set, enables generation of a power management event because of magic packet reception. - */ -#define ENET_PMT_CSR_MGKPKTEN_MASK (0x2U) -#define ENET_PMT_CSR_MGKPKTEN_SHIFT (1U) -#define ENET_PMT_CSR_MGKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPKTEN_SHIFT) & ENET_PMT_CSR_MGKPKTEN_MASK) -#define ENET_PMT_CSR_MGKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPKTEN_MASK) >> ENET_PMT_CSR_MGKPKTEN_SHIFT) - -/* - * PWRDWN (RW) - * - * Power Down - * When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. - * This bit is then self-cleared and the power-down mode is disabled. - * The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. - * The frames, received by the MAC after this bit is cleared, are forwarded to the application. - * This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. - * Note: You can gate-off the CSR clock during the power-down mode. - * However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - */ -#define ENET_PMT_CSR_PWRDWN_MASK (0x1U) -#define ENET_PMT_CSR_PWRDWN_SHIFT (0U) -#define ENET_PMT_CSR_PWRDWN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_PWRDWN_SHIFT) & ENET_PMT_CSR_PWRDWN_MASK) -#define ENET_PMT_CSR_PWRDWN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_PWRDWN_MASK) >> ENET_PMT_CSR_PWRDWN_SHIFT) - -/* Bitfield definition for register: LPI_CSR */ -/* - * LPITXA (RW) - * - * LPI TX Automate - * This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. - * This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, - * the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. - * The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - * In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. - * If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), - * when the MAC is in the LPI mode, the MAC exits the LPI mode. - * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - */ -#define ENET_LPI_CSR_LPITXA_MASK (0x80000UL) -#define ENET_LPI_CSR_LPITXA_SHIFT (19U) -#define ENET_LPI_CSR_LPITXA_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPITXA_SHIFT) & ENET_LPI_CSR_LPITXA_MASK) -#define ENET_LPI_CSR_LPITXA_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPITXA_MASK) >> ENET_LPI_CSR_LPITXA_SHIFT) - -/* - * PLSEN (RW) - * - * PHY Link Status Enable - * This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. - * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - * When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - */ -#define ENET_LPI_CSR_PLSEN_MASK (0x40000UL) -#define ENET_LPI_CSR_PLSEN_SHIFT (18U) -#define ENET_LPI_CSR_PLSEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLSEN_SHIFT) & ENET_LPI_CSR_PLSEN_MASK) -#define ENET_LPI_CSR_PLSEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLSEN_MASK) >> ENET_LPI_CSR_PLSEN_SHIFT) - -/* - * PLS (RW) - * - * PHY Link Status - * This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. - * When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - */ -#define ENET_LPI_CSR_PLS_MASK (0x20000UL) -#define ENET_LPI_CSR_PLS_SHIFT (17U) -#define ENET_LPI_CSR_PLS_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLS_SHIFT) & ENET_LPI_CSR_PLS_MASK) -#define ENET_LPI_CSR_PLS_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLS_MASK) >> ENET_LPI_CSR_PLS_SHIFT) - -/* - * LPIEN (RW) - * - * LPI Enable - * When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. - * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - */ -#define ENET_LPI_CSR_LPIEN_MASK (0x10000UL) -#define ENET_LPI_CSR_LPIEN_SHIFT (16U) -#define ENET_LPI_CSR_LPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPIEN_SHIFT) & ENET_LPI_CSR_LPIEN_MASK) -#define ENET_LPI_CSR_LPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPIEN_MASK) >> ENET_LPI_CSR_LPIEN_SHIFT) - -/* - * RLPIST (RW) - * - * Receive LPI State - * When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_RLPIST_MASK (0x200U) -#define ENET_LPI_CSR_RLPIST_SHIFT (9U) -#define ENET_LPI_CSR_RLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIST_SHIFT) & ENET_LPI_CSR_RLPIST_MASK) -#define ENET_LPI_CSR_RLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIST_MASK) >> ENET_LPI_CSR_RLPIST_SHIFT) - -/* - * TLPIST (RW) - * - * Transmit LPI State - * When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_TLPIST_MASK (0x100U) -#define ENET_LPI_CSR_TLPIST_SHIFT (8U) -#define ENET_LPI_CSR_TLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIST_SHIFT) & ENET_LPI_CSR_TLPIST_MASK) -#define ENET_LPI_CSR_TLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIST_MASK) >> ENET_LPI_CSR_TLPIST_SHIFT) - -/* - * RLPIEX (RW) - * - * Receive LPI Exit - * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. - * This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEX_MASK (0x8U) -#define ENET_LPI_CSR_RLPIEX_SHIFT (3U) -#define ENET_LPI_CSR_RLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEX_SHIFT) & ENET_LPI_CSR_RLPIEX_MASK) -#define ENET_LPI_CSR_RLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEX_MASK) >> ENET_LPI_CSR_RLPIEX_SHIFT) - -/* - * RLPIEN (RW) - * - * Receive LPI Entry - * When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEN_MASK (0x4U) -#define ENET_LPI_CSR_RLPIEN_SHIFT (2U) -#define ENET_LPI_CSR_RLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEN_SHIFT) & ENET_LPI_CSR_RLPIEN_MASK) -#define ENET_LPI_CSR_RLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEN_MASK) >> ENET_LPI_CSR_RLPIEN_SHIFT) - -/* - * TLPIEX (RW) - * - * Transmit LPI Exit - * When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEX_MASK (0x2U) -#define ENET_LPI_CSR_TLPIEX_SHIFT (1U) -#define ENET_LPI_CSR_TLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEX_SHIFT) & ENET_LPI_CSR_TLPIEX_MASK) -#define ENET_LPI_CSR_TLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEX_MASK) >> ENET_LPI_CSR_TLPIEX_SHIFT) - -/* - * TLPIEN (RW) - * - * Transmit LPI Entry - * When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEN_MASK (0x1U) -#define ENET_LPI_CSR_TLPIEN_SHIFT (0U) -#define ENET_LPI_CSR_TLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEN_SHIFT) & ENET_LPI_CSR_TLPIEN_MASK) -#define ENET_LPI_CSR_TLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEN_MASK) >> ENET_LPI_CSR_TLPIEN_SHIFT) - -/* Bitfield definition for register: LPI_TCR */ -/* - * LST (RW) - * - * LPI LS TIMER - * This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - * The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. - * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - */ -#define ENET_LPI_TCR_LST_MASK (0x3FF0000UL) -#define ENET_LPI_TCR_LST_SHIFT (16U) -#define ENET_LPI_TCR_LST_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_LST_SHIFT) & ENET_LPI_TCR_LST_MASK) -#define ENET_LPI_TCR_LST_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_LST_MASK) >> ENET_LPI_TCR_LST_SHIFT) - -/* - * TWT (RW) - * - * LPI TW TIMER - * This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - * the LPI pattern to the PHY and before it resumes the normal transmission. - * The TLPIEX status bit is set after the expiry of this timer. - */ -#define ENET_LPI_TCR_TWT_MASK (0xFFFFU) -#define ENET_LPI_TCR_TWT_SHIFT (0U) -#define ENET_LPI_TCR_TWT_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_TWT_SHIFT) & ENET_LPI_TCR_TWT_MASK) -#define ENET_LPI_TCR_TWT_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_TWT_MASK) >> ENET_LPI_TCR_TWT_SHIFT) - -/* Bitfield definition for register: INTR_STATUS */ -/* - * GPIIS (RO) - * - * GPI Interrupt Status - * When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - * of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. - * This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - * When the GPIO feature is not enabled, this bit is reserved. - */ -#define ENET_INTR_STATUS_GPIIS_MASK (0x800U) -#define ENET_INTR_STATUS_GPIIS_SHIFT (11U) -#define ENET_INTR_STATUS_GPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_GPIIS_MASK) >> ENET_INTR_STATUS_GPIIS_SHIFT) - -/* - * LPIIS (RO) - * - * LPI Interrupt Status - * When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. - * This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - */ -#define ENET_INTR_STATUS_LPIIS_MASK (0x400U) -#define ENET_INTR_STATUS_LPIIS_SHIFT (10U) -#define ENET_INTR_STATUS_LPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_LPIIS_MASK) >> ENET_INTR_STATUS_LPIIS_SHIFT) - -/* - * TSIS (RO) - * - * Timestamp Interrupt Status - * When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - * - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - * - There is an overflow in the seconds register. - * - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - */ -#define ENET_INTR_STATUS_TSIS_MASK (0x200U) -#define ENET_INTR_STATUS_TSIS_SHIFT (9U) -#define ENET_INTR_STATUS_TSIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_TSIS_MASK) >> ENET_INTR_STATUS_TSIS_SHIFT) - -/* - * MMCRXIPIS (RO) - * - * MMC Receive Checksum Offload Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIPIS_MASK (0x80U) -#define ENET_INTR_STATUS_MMCRXIPIS_SHIFT (7U) -#define ENET_INTR_STATUS_MMCRXIPIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIPIS_MASK) >> ENET_INTR_STATUS_MMCRXIPIS_SHIFT) - -/* - * MMCTXIS (RO) - * - * MMC Transmit Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCTXIS_MASK (0x40U) -#define ENET_INTR_STATUS_MMCTXIS_SHIFT (6U) -#define ENET_INTR_STATUS_MMCTXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCTXIS_MASK) >> ENET_INTR_STATUS_MMCTXIS_SHIFT) - -/* - * MMCRXIS (RO) - * - * MMC Receive Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIS_MASK (0x20U) -#define ENET_INTR_STATUS_MMCRXIS_SHIFT (5U) -#define ENET_INTR_STATUS_MMCRXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIS_MASK) >> ENET_INTR_STATUS_MMCRXIS_SHIFT) - -/* - * MMCIS (RO) - * - * MMC Interrupt Status - * This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - */ -#define ENET_INTR_STATUS_MMCIS_MASK (0x10U) -#define ENET_INTR_STATUS_MMCIS_SHIFT (4U) -#define ENET_INTR_STATUS_MMCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCIS_MASK) >> ENET_INTR_STATUS_MMCIS_SHIFT) - -/* - * PMTIS (RO) - * - * PMT Interrupt Status - * This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). - * This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - */ -#define ENET_INTR_STATUS_PMTIS_MASK (0x8U) -#define ENET_INTR_STATUS_PMTIS_SHIFT (3U) -#define ENET_INTR_STATUS_PMTIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PMTIS_MASK) >> ENET_INTR_STATUS_PMTIS_SHIFT) - -/* - * PCSANCIS (RO) - * - * PCS Auto-Negotiation Complete - * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation to the AN Status register. - */ -#define ENET_INTR_STATUS_PCSANCIS_MASK (0x4U) -#define ENET_INTR_STATUS_PCSANCIS_SHIFT (2U) -#define ENET_INTR_STATUS_PCSANCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSANCIS_MASK) >> ENET_INTR_STATUS_PCSANCIS_SHIFT) - -/* - * PCSLCHGIS (RO) - * - * PCS Link Status Changed - * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation on the AN Status register. - */ -#define ENET_INTR_STATUS_PCSLCHGIS_MASK (0x2U) -#define ENET_INTR_STATUS_PCSLCHGIS_SHIFT (1U) -#define ENET_INTR_STATUS_PCSLCHGIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSLCHGIS_MASK) >> ENET_INTR_STATUS_PCSLCHGIS_SHIFT) - -/* - * RGSMIIIS (RO) - * - * RGMII or SMII Interrupt Status - * This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). - * This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - */ -#define ENET_INTR_STATUS_RGSMIIIS_MASK (0x1U) -#define ENET_INTR_STATUS_RGSMIIIS_SHIFT (0U) -#define ENET_INTR_STATUS_RGSMIIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_RGSMIIIS_MASK) >> ENET_INTR_STATUS_RGSMIIIS_SHIFT) - -/* Bitfield definition for register: INTR_MASK */ -/* - * LPIIM (RW) - * - * LPI Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_LPIIM_MASK (0x400U) -#define ENET_INTR_MASK_LPIIM_SHIFT (10U) -#define ENET_INTR_MASK_LPIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_LPIIM_SHIFT) & ENET_INTR_MASK_LPIIM_MASK) -#define ENET_INTR_MASK_LPIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_LPIIM_MASK) >> ENET_INTR_MASK_LPIIM_SHIFT) - -/* - * TSIM (RW) - * - * Timestamp Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_TSIM_MASK (0x200U) -#define ENET_INTR_MASK_TSIM_SHIFT (9U) -#define ENET_INTR_MASK_TSIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_TSIM_SHIFT) & ENET_INTR_MASK_TSIM_MASK) -#define ENET_INTR_MASK_TSIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_TSIM_MASK) >> ENET_INTR_MASK_TSIM_SHIFT) - -/* - * PMTIM (RW) - * - * PMT Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PMTIM_MASK (0x8U) -#define ENET_INTR_MASK_PMTIM_SHIFT (3U) -#define ENET_INTR_MASK_PMTIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PMTIM_SHIFT) & ENET_INTR_MASK_PMTIM_MASK) -#define ENET_INTR_MASK_PMTIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PMTIM_MASK) >> ENET_INTR_MASK_PMTIM_SHIFT) - -/* - * PCSANCIM (RW) - * - * PCS AN Completion Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSANCIM_MASK (0x4U) -#define ENET_INTR_MASK_PCSANCIM_SHIFT (2U) -#define ENET_INTR_MASK_PCSANCIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSANCIM_SHIFT) & ENET_INTR_MASK_PCSANCIM_MASK) -#define ENET_INTR_MASK_PCSANCIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSANCIM_MASK) >> ENET_INTR_MASK_PCSANCIM_SHIFT) - -/* - * PCSLCHGIM (RW) - * - * PCS Link Status Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSLCHGIM_MASK (0x2U) -#define ENET_INTR_MASK_PCSLCHGIM_SHIFT (1U) -#define ENET_INTR_MASK_PCSLCHGIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSLCHGIM_SHIFT) & ENET_INTR_MASK_PCSLCHGIM_MASK) -#define ENET_INTR_MASK_PCSLCHGIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSLCHGIM_MASK) >> ENET_INTR_MASK_PCSLCHGIM_SHIFT) - -/* - * RGSMIIIM (RW) - * - * RGMII or SMII Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_RGSMIIIM_MASK (0x1U) -#define ENET_INTR_MASK_RGSMIIIM_SHIFT (0U) -#define ENET_INTR_MASK_RGSMIIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_RGSMIIIM_SHIFT) & ENET_INTR_MASK_RGSMIIIM_MASK) -#define ENET_INTR_MASK_RGSMIIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_RGSMIIIM_MASK) >> ENET_INTR_MASK_RGSMIIIM_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_HIGH */ -/* - * AE (RO) - * - * Address Enable - * This bit is RO. The bit value is fixed at 1. - */ -#define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_0_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_AE_MASK) >> ENET_MAC_ADDR_0_HIGH_AE_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address0 [47:32] - * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_LOW */ -/* - * ADDRLO (RW) - * - * MAC Address0 [31:0] - * This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: HIGH */ -/* - * AE (RW) - * - * Address Enable - * When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - */ -#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_AE_SHIFT) & ENET_MAC_ADDR_HIGH_AE_MASK) -#define ENET_MAC_ADDR_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_AE_MASK) >> ENET_MAC_ADDR_HIGH_AE_SHIFT) - -/* - * SA (RW) - * - * Source Address - * When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - */ -#define ENET_MAC_ADDR_HIGH_SA_MASK (0x40000000UL) -#define ENET_MAC_ADDR_HIGH_SA_SHIFT (30U) -#define ENET_MAC_ADDR_HIGH_SA_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_SA_SHIFT) & ENET_MAC_ADDR_HIGH_SA_MASK) -#define ENET_MAC_ADDR_HIGH_SA_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_SA_MASK) >> ENET_MAC_ADDR_HIGH_SA_SHIFT) - -/* - * MBC (RW) - * - * Mask Byte Control - * These bits are mask control bits for comparison of each of the MAC Address bytes. - * When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. - * Each bit controls the masking of the bytes as follows: - * - Bit 29: Register 18[15:8] - * - Bit 28: Register 18[7:0] - * - Bit 27: Register 19[31:24] - - * ... - * - Bit 24: Register 19[7:0] - * You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - */ -#define ENET_MAC_ADDR_HIGH_MBC_MASK (0x3F000000UL) -#define ENET_MAC_ADDR_HIGH_MBC_SHIFT (24U) -#define ENET_MAC_ADDR_HIGH_MBC_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_MBC_SHIFT) & ENET_MAC_ADDR_HIGH_MBC_MASK) -#define ENET_MAC_ADDR_HIGH_MBC_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_MBC_MASK) >> ENET_MAC_ADDR_HIGH_MBC_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address1 [47:32] - * This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - */ -#define ENET_MAC_ADDR_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: LOW */ -/* - * ADDRLO (RW) - * - * MAC Address1 [31:0] - * This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - */ -#define ENET_MAC_ADDR_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register: XMII_CSR */ -/* - * FALSCARDET (RW) - * - * False Carrier Detected - * This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_FALSCARDET_MASK (0x20U) -#define ENET_XMII_CSR_FALSCARDET_SHIFT (5U) -#define ENET_XMII_CSR_FALSCARDET_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_FALSCARDET_SHIFT) & ENET_XMII_CSR_FALSCARDET_MASK) -#define ENET_XMII_CSR_FALSCARDET_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_FALSCARDET_MASK) >> ENET_XMII_CSR_FALSCARDET_SHIFT) - -/* - * JABTO (RW) - * - * Jabber Timeout - * This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_JABTO_MASK (0x10U) -#define ENET_XMII_CSR_JABTO_SHIFT (4U) -#define ENET_XMII_CSR_JABTO_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_JABTO_SHIFT) & ENET_XMII_CSR_JABTO_MASK) -#define ENET_XMII_CSR_JABTO_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_JABTO_MASK) >> ENET_XMII_CSR_JABTO_SHIFT) - -/* - * LNKSTS (RW) - * - * Link Status - * This bit indicates whether the link between the local PHY and the remote PHY is up or down. - * It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. - * The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - */ -#define ENET_XMII_CSR_LNKSTS_MASK (0x8U) -#define ENET_XMII_CSR_LNKSTS_SHIFT (3U) -#define ENET_XMII_CSR_LNKSTS_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSTS_SHIFT) & ENET_XMII_CSR_LNKSTS_MASK) -#define ENET_XMII_CSR_LNKSTS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSTS_MASK) >> ENET_XMII_CSR_LNKSTS_SHIFT) - -/* - * LNKSPEED (RW) - * - * Link Speed - * This bit indicates the current speed of the link: - * - 00: 2.5 MHz - * - 01: 25 MHz - * - 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - */ -#define ENET_XMII_CSR_LNKSPEED_MASK (0x6U) -#define ENET_XMII_CSR_LNKSPEED_SHIFT (1U) -#define ENET_XMII_CSR_LNKSPEED_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSPEED_SHIFT) & ENET_XMII_CSR_LNKSPEED_MASK) -#define ENET_XMII_CSR_LNKSPEED_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSPEED_MASK) >> ENET_XMII_CSR_LNKSPEED_SHIFT) - -/* - * LNKMOD (RW) - * - * Link Mode - * This bit indicates the current mode of operation of the link: - * - 1’b0: Half-duplex mode - * - 1’b1: Full-duplex mode - */ -#define ENET_XMII_CSR_LNKMOD_MASK (0x1U) -#define ENET_XMII_CSR_LNKMOD_SHIFT (0U) -#define ENET_XMII_CSR_LNKMOD_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKMOD_SHIFT) & ENET_XMII_CSR_LNKMOD_MASK) -#define ENET_XMII_CSR_LNKMOD_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKMOD_MASK) >> ENET_XMII_CSR_LNKMOD_SHIFT) - -/* Bitfield definition for register: WDOG_WTO */ -/* - * PWE (RW) - * - * Programmable Watchdog Enable - * When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. - * When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - */ -#define ENET_WDOG_WTO_PWE_MASK (0x10000UL) -#define ENET_WDOG_WTO_PWE_SHIFT (16U) -#define ENET_WDOG_WTO_PWE_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_PWE_SHIFT) & ENET_WDOG_WTO_PWE_MASK) -#define ENET_WDOG_WTO_PWE_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_PWE_MASK) >> ENET_WDOG_WTO_PWE_SHIFT) - -/* - * WTO (RW) - * - * Watchdog Timeout - * When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * this field is used as watchdog timeout for a received frame. - * If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. - * Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). - * Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - */ -#define ENET_WDOG_WTO_WTO_MASK (0x3FFFU) -#define ENET_WDOG_WTO_WTO_SHIFT (0U) -#define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) -#define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) - -/* Bitfield definition for register: MMC_CNTRL */ -/* - * UCDBC (RW) - * - * Update MMC Counters for Dropped Broadcast Frames - * When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - * When reset, the MMC Counters are not updated for dropped Broadcast frames. - */ -#define ENET_MMC_CNTRL_UCDBC_MASK (0x100U) -#define ENET_MMC_CNTRL_UCDBC_SHIFT (8U) -#define ENET_MMC_CNTRL_UCDBC_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_UCDBC_SHIFT) & ENET_MMC_CNTRL_UCDBC_MASK) -#define ENET_MMC_CNTRL_UCDBC_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_UCDBC_MASK) >> ENET_MMC_CNTRL_UCDBC_SHIFT) - -/* - * CNTPRSTLVL (RW) - * - * Full-Half Preset - * When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - * - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - * - 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - * - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - * - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - */ -#define ENET_MMC_CNTRL_CNTPRSTLVL_MASK (0x20U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT (5U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) -#define ENET_MMC_CNTRL_CNTPRSTLVL_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) >> ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) - -/* - * CNTPRST (RW) - * - * Counters Preset - * When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. - * This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - */ -#define ENET_MMC_CNTRL_CNTPRST_MASK (0x10U) -#define ENET_MMC_CNTRL_CNTPRST_SHIFT (4U) -#define ENET_MMC_CNTRL_CNTPRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRST_SHIFT) & ENET_MMC_CNTRL_CNTPRST_MASK) -#define ENET_MMC_CNTRL_CNTPRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRST_MASK) >> ENET_MMC_CNTRL_CNTPRST_SHIFT) - -/* - * CNTFREEZ (RW) - * - * MMC Counter Freeze - * When this bit is set, it freezes all MMC counters to their current value. - * Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - * If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - */ -#define ENET_MMC_CNTRL_CNTFREEZ_MASK (0x8U) -#define ENET_MMC_CNTRL_CNTFREEZ_SHIFT (3U) -#define ENET_MMC_CNTRL_CNTFREEZ_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTFREEZ_SHIFT) & ENET_MMC_CNTRL_CNTFREEZ_MASK) -#define ENET_MMC_CNTRL_CNTFREEZ_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTFREEZ_MASK) >> ENET_MMC_CNTRL_CNTFREEZ_SHIFT) - -/* - * RSTONRD (RW) - * - * Reset on Read - * When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - */ -#define ENET_MMC_CNTRL_RSTONRD_MASK (0x4U) -#define ENET_MMC_CNTRL_RSTONRD_SHIFT (2U) -#define ENET_MMC_CNTRL_RSTONRD_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_RSTONRD_SHIFT) & ENET_MMC_CNTRL_RSTONRD_MASK) -#define ENET_MMC_CNTRL_RSTONRD_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_RSTONRD_MASK) >> ENET_MMC_CNTRL_RSTONRD_SHIFT) - -/* - * CNTSTOPRO (RW) - * - * Counter Stop Rollover - * When this bit is set, the counter does not roll over to zero after reaching the maximum value. - */ -#define ENET_MMC_CNTRL_CNTSTOPRO_MASK (0x2U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SHIFT (1U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) -#define ENET_MMC_CNTRL_CNTSTOPRO_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) >> ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) - -/* - * CNTRST (RW) - * - * Counters Reset - * When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - */ -#define ENET_MMC_CNTRL_CNTRST_MASK (0x1U) -#define ENET_MMC_CNTRL_CNTRST_SHIFT (0U) -#define ENET_MMC_CNTRL_CNTRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTRST_SHIFT) & ENET_MMC_CNTRL_CNTRST_MASK) -#define ENET_MMC_CNTRL_CNTRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTRST_MASK) >> ENET_MMC_CNTRL_CNTRST_SHIFT) - -/* Bitfield definition for register: MMC_INTR_RX */ -/* - * RXCTRLFIS (RW) - * - * MMC Receive Control Frame Counter Interrupt Status - * This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCTRLFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT (25U) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) -#define ENET_MMC_INTR_RX_RXCTRLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) >> ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) - -/* - * RXRCVERRFIS (RW) - * - * MMC Receive Error Frame Counter Interrupt Status - * This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRCVERRFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT (24U) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) >> ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) - -/* - * RXWDOGFIS (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Status - * This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXWDOGFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT (23U) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) -#define ENET_MMC_INTR_RX_RXWDOGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) >> ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) - -/* - * RXVLANGBFIS (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Status - * This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXVLANGBFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT (22U) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) >> ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) - -/* - * RXFOVFIS (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Status - * This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXFOVFIS_MASK (0x200000UL) -#define ENET_MMC_INTR_RX_RXFOVFIS_SHIFT (21U) -#define ENET_MMC_INTR_RX_RXFOVFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) -#define ENET_MMC_INTR_RX_RXFOVFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) >> ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) - -/* - * RXPAUSFIS (RW) - * - * MMC Receive Pause Frame Counter Interrupt Status - * This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXPAUSFIS_MASK (0x100000UL) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT (20U) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) -#define ENET_MMC_INTR_RX_RXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) >> ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) - -/* - * RXORANGEFIS (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Status. - * This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXORANGEFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT (19U) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) -#define ENET_MMC_INTR_RX_RXORANGEFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) >> ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) - -/* - * RXLENERFIS (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Status - * This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXLENERFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_RX_RXLENERFIS_SHIFT (18U) -#define ENET_MMC_INTR_RX_RXLENERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) -#define ENET_MMC_INTR_RX_RXLENERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) >> ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) - -/* - * RXUCGFIS (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Status - * This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUCGFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_RX_RXUCGFIS_SHIFT (17U) -#define ENET_MMC_INTR_RX_RXUCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) >> ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) - -/* - * RX1024TMAXOCTGBFIS (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. - * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT (16U) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) - -/* - * RX512T1023OCTGBFIS (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK (0x8000U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT (15U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) - -/* - * RX256T511OCTGBFIS (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK (0x4000U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT (14U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) - -/* - * RX128T255OCTGBFIS (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK (0x2000U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT (13U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) - -/* - * RX65T127OCTGBFIS (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) - -/* - * RX64OCTGBFIS (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) - -/* - * RXOSIZEGFIS (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Status - * This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK (0x400U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT (10U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) - -/* - * RXUSIZEGFIS (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Status - * This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK (0x200U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT (9U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) - -/* - * RXJABERFIS (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Status - * This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXJABERFIS_MASK (0x100U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SHIFT (8U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) -#define ENET_MMC_INTR_RX_RXJABERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) >> ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) - -/* - * RXRUNTFIS (RW) - * - * MMC Receive Runt Frame Counter Interrupt Status - * This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRUNTFIS_MASK (0x80U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT (7U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) -#define ENET_MMC_INTR_RX_RXRUNTFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) >> ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) - -/* - * RXALGNERFIS (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Status - * This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXALGNERFIS_MASK (0x40U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT (6U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) -#define ENET_MMC_INTR_RX_RXALGNERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) >> ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) - -/* - * RXCRCERFIS (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Status - * This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCRCERFIS_MASK (0x20U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT (5U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) -#define ENET_MMC_INTR_RX_RXCRCERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) >> ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) - -/* - * RXMCGFIS (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Status - * This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXMCGFIS_MASK (0x10U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SHIFT (4U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) >> ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) - -/* - * RXBCGFIS (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Status - * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXBCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) >> ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) - -/* - * RXGOCTIS (RW) - * - * MMC Receive Good Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGOCTIS_MASK (0x4U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SHIFT (2U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) - -/* - * RXGBOCTIS (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBOCTIS_MASK (0x2U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT (1U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) - -/* - * RXGBFRMIS (RW) - * - * MMC Receive Good Bad Frame Counter Interrupt Status - * This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBFRMIS_MASK (0x1U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT (0U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) -#define ENET_MMC_INTR_RX_RXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) >> ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_TX */ -/* - * TXOSIZEGFIS (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Status - * This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT (25U) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) >> ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) - -/* - * TXVLANGFIS (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Status - * This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXVLANGFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT (24U) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) -#define ENET_MMC_INTR_TX_TXVLANGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) >> ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) - -/* - * TXPAUSFIS (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Status - * This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXPAUSFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT (23U) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) -#define ENET_MMC_INTR_TX_TXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) >> ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) - -/* - * TXEXDEFFIS (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Status - * This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXDEFFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT (22U) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) - -/* - * TXGFRMIS (RW) - * - * MMC Transmit Good Frame Counter Interrupt Status - * This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGFRMIS_MASK (0x200000UL) -#define ENET_MMC_INTR_TX_TXGFRMIS_SHIFT (21U) -#define ENET_MMC_INTR_TX_TXGFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) - -/* - * TXGOCTIS (RW) - * - * MMC Transmit Good Octet Counter Interrupt Status - * This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGOCTIS_MASK (0x100000UL) -#define ENET_MMC_INTR_TX_TXGOCTIS_SHIFT (20U) -#define ENET_MMC_INTR_TX_TXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) - -/* - * TXCARERFIS (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Status - * This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXCARERFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_TX_TXCARERFIS_SHIFT (19U) -#define ENET_MMC_INTR_TX_TXCARERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) -#define ENET_MMC_INTR_TX_TXCARERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) >> ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) - -/* - * TXEXCOLFIS (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Status - * This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXCOLFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT (18U) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) - -/* - * TXLATCOLFIS (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Status - * This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXLATCOLFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT (17U) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) - -/* - * TXDEFFIS (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Status - * This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXDEFFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_TX_TXDEFFIS_SHIFT (16U) -#define ENET_MMC_INTR_TX_TXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) - -/* - * TXMCOLGFIS (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - * This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCOLGFIS_MASK (0x8000U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT (15U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) - -/* - * TXSCOLGFIS (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Status - * This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXSCOLGFIS_MASK (0x4000U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT (14U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) - -/* - * TXUFLOWERFIS (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Status - * This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK (0x2000U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT (13U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) >> ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) - -/* - * TXBCGBFIS (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) - -/* - * TXMCGBFIS (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - * The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) - -/* - * TXUCGBFIS (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - * This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUCGBFIS_MASK (0x400U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT (10U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXUCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) - -/* - * TX1024TMAXOCTGBFIS (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK (0x200U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT (9U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) - -/* - * TX512T1023OCTGBFIS (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK (0x100U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT (8U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) - -/* - * TX256T511OCTGBFIS (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK (0x80U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT (7U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) - -/* - * TX128T255OCTGBFIS (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK (0x40U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT (6U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) - -/* - * TX65T127OCTGBFIS (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - */ -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK (0x20U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT (5U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) - -/* - * TX64OCTGBFIS (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK (0x10U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT (4U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) - -/* - * TXMCGFIS (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Status - * This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) - -/* - * TXBCGFIS (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGFIS_MASK (0x4U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SHIFT (2U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) - -/* - * TXGBFRMIS (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Status - * This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBFRMIS_MASK (0x2U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT (1U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) - -/* - * TXGBOCTIS (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Status - * This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBOCTIS_MASK (0x1U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT (0U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_RX */ -/* - * RXCTRLFIM (RW) - * - * MMC Receive Control Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) - -/* - * RXRCVERRFIM (RW) - * - * MMC Receive Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) - -/* - * RXWDOGFIM (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) - -/* - * RXVLANGBFIM (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) - -/* - * RXFOVFIM (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) - -/* - * RXPAUSFIM (RW) - * - * MMC Receive Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) - -/* - * RXORANGEFIM (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) - -/* - * RXLENERFIM (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) - -/* - * RXUCGFIM (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) - -/* - * RX1024TMAXOCTGBFIM (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) - -/* - * RX512T1023OCTGBFIM (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) - -/* - * RX256T511OCTGBFIM (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) - -/* - * RX128T255OCTGBFIM (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) - -/* - * RX65T127OCTGBFIM (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) - -/* - * RX64OCTGBFIM (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) - -/* - * RXOSIZEGFIM (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) - -/* - * RXUSIZEGFIM (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) - -/* - * RXJABERFIM (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) - -/* - * RXRUNTFIM (RW) - * - * MMC Receive Runt Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) - -/* - * RXALGNERFIM (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) - -/* - * RXCRCERFIM (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) - -/* - * RXMCGFIM (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) - -/* - * RXBCGFIM (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) - -/* - * RXGOCTIM (RW) - * - * MMC Receive Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) - -/* - * RXGBOCTIM (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_TX */ -/* - * TXOSIZEGFIM (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) - -/* - * TXVLANGFIM (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) - -/* - * TXPAUSFIM (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) - -/* - * TXEXDEFFIM (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) - -/* - * TXGFRMIM (RW) - * - * MMC Transmit Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) - -/* - * TXGOCTIM (RW) - * - * MMC Transmit Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) - -/* - * TXCARERFIM (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) - -/* - * TXEXCOLFIM (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) - -/* - * TXLATCOLFIM (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) - -/* - * TXDEFFIM (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) - -/* - * TXMCOLGFIM (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) - -/* - * TXSCOLGFIM (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) - -/* - * TXUFLOWERFIM (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) - -/* - * TXBCGBFIM (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) - -/* - * TXMCGBFIM (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) - -/* - * TXUCGBFIM (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) - -/* - * TX1024TMAXOCTGBFIM (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) - -/* - * TX512T1023OCTGBFIM (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) - -/* - * TX256T511OCTGBFIM (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) - -/* - * TX128T255OCTGBFIM (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) - -/* - * TX65T127OCTGBFIM (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) - -/* - * TX64OCTGBFIM (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) - -/* - * TXMCGFIM (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) - -/* - * TXBCGFIM (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) - -/* - * TXGBFRMIM (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) - -/* - * TXGBOCTIM (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK (0x1U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT (0U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) - -/* Bitfield definition for register: TX64OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX64OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX64OCTETS_GB_FRMCNT_SHIFT) & ENET_TX64OCTETS_GB_FRMCNT_MASK) -#define ENET_TX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX64OCTETS_GB_FRMCNT_MASK) >> ENET_TX64OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX65TO127OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX128TO255OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX256TO511OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX512TO1023OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX1024TOMAXOCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFRAMECOUNT_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received. - */ -#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ -/* - * RXICMPEROIM (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT (29U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) - -/* - * RXICMPGOIM (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT (28U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) - -/* - * RXTCPEROIM (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT (27U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) - -/* - * RXTCPGOIM (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT (26U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) - -/* - * RXUDPEROIM (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT (25U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) - -/* - * RXUDPGOIM (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT (24U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) - -/* - * RXIPV6NOPAYOIM (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT (23U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) - -/* - * RXIPV6HEROIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT (22U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) - -/* - * RXIPV6GOIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT (21U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) - -/* - * RXIPV4UDSBLOIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT (20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) - -/* - * RXIPV4FRAGOIM (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT (19U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) - -/* - * RXIPV4NOPAYOIM (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT (18U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) - -/* - * RXIPV4HEROIM (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT (17U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) - -/* - * RXIPV4GOIM (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT (16U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) - -/* - * RXICMPERFIM (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT (13U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) - -/* - * RXICMPGFIM (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT (12U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) - -/* - * RXTCPERFIM (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK (0x800U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT (11U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) - -/* - * RXTCPGFIM (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK (0x400U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT (10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) - -/* - * RXUDPERFIM (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK (0x200U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT (9U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) - -/* - * RXUDPGFIM (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK (0x100U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT (8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) - -/* - * RXIPV6NOPAYFIM (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK (0x80U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT (7U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) - -/* - * RXIPV6HERFIM (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK (0x40U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT (6U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) - -/* - * RXIPV6GFIM (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK (0x20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT (5U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) - -/* - * RXIPV4UDSBLFIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK (0x10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT (4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) - -/* - * RXIPV4FRAGFIM (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK (0x8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT (3U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) - -/* - * RXIPV4NOPAYFIM (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK (0x4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT (2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) - -/* - * RXIPV4HERFIM (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK (0x2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT (1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) - -/* - * RXIPV4GFIM (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK (0x1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT (0U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_RX */ -/* - * RXICMPEROIS (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Status - * This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT (29U) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) - -/* - * RXICMPGOIS (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Status - * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT (28U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) - -/* - * RXTCPEROIS (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Status - * This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT (27U) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) - -/* - * RXTCPGOIS (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Status - * This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT (26U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) - -/* - * RXUDPEROIS (RW) - * - * MMC Receive UDP Error Octet Counter Interrupt Status - * This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT (25U) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) - -/* - * RXUDPGOIS (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Status - * This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT (24U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) - -/* - * RXIPV6NOPAYOIS (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT (23U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) - -/* - * RXIPV6HEROIS (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT (22U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) - -/* - * RXIPV6GOIS (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Status - * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT (21U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) - -/* - * RXIPV4UDSBLOIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT (20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) - -/* - * RXIPV4FRAGOIS (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT (19U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) - -/* - * RXIPV4NOPAYOIS (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT (18U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) - -/* - * RXIPV4HEROIS (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT (17U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) - -/* - * RXIPV4GOIS (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Status - * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT (16U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) - -/* - * RXICMPERFIS (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Status - * This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT (13U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) - -/* - * RXICMPGFIS (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Status - * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT (12U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) - -/* - * RXTCPERFIS (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Status - * This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK (0x800U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT (11U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) - -/* - * RXTCPGFIS (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Status - * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK (0x400U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT (10U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) - -/* - * RXUDPERFIS (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Status - * This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK (0x200U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT (9U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) - -/* - * RXUDPGFIS (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Status - * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK (0x100U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT (8U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) - -/* - * RXIPV6NOPAYFIS (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK (0x80U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT (7U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) - -/* - * RXIPV6HERFIS (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK (0x40U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT (6U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) - -/* - * RXIPV6GFIS (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Status - * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK (0x20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT (5U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) - -/* - * RXIPV4UDSBLFIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK (0x10U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT (4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) - -/* - * RXIPV4FRAGFIS (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK (0x8U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT (3U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) - -/* - * RXIPV4NOPAYFIS (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK (0x4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT (2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) - -/* - * RXIPV4HERFIS (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK (0x2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT (1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) - -/* - * RXIPV4GFIS (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Status - * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK (0x1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT (0U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) - -/* Bitfield definition for register: RXIPV4_GD_FMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - */ -#define ENET_RXIPV4_GD_FMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) -#define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ -/* - * L4DPIM0 (RW) - * - * Layer 4 Destination Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK (0x200000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT (21U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) - -/* - * L4DPM0 (RW) - * - * Layer 4 Destination Port Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. - * When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK (0x100000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT (20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) - -/* - * L4SPIM0 (RW) - * - * Layer 4 Source Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK (0x80000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT (19U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) - -/* - * L4SPM0 (RW) - * - * Layer 4 Source Port Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK (0x40000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT (18U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) - -/* - * L4PEN0 (RW) - * - * Layer 4 Protocol Enable - * When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. - * When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. - * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK (0x10000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT (16U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) - -/* - * L3HDBM0 (RW) - * - * Layer 3 IP DA Higher Bits Match - * IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, - * which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. - * The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - … - * - 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK (0xF800U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT (11U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) - -/* - * L3HSBM0 (RW) - * - * Layer 3 IP SA Higher Bits Match - * IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. - * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK (0x7C0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT (6U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) - -/* - * L3DAIM0 (RW) - * - * Layer 3 IP DA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK (0x20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT (5U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) - -/* - * L3DAM0 (RW) - * - * Layer 3 IP DA Match Enable - * When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. - * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK (0x10U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT (4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) - -/* - * L3SAIM0 (RW) - * - * Layer 3 IP SA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK (0x8U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT (3U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) - -/* - * L3SAM0 (RW) - * - * Layer 3 IP SA Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK (0x4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT (2U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) - -/* - * L3PEN0 (RW) - * - * Layer 3 Protocol Enable - * When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. - * When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. - * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK (0x1U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L4_ADDR */ -/* - * L4DP0 (RW) - * - * Layer 4 Destination Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK (0xFFFF0000UL) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT (16U) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) - -/* - * L4SP0 (RW) - * - * Layer 4 Source Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK (0xFFFFU) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT (0U) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_0 */ -/* - * L3A00 (RW) - * - * Layer 3 Address 0 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) >> ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_1 */ -/* - * L3A10 (RW) - * - * Layer 3 Address 1 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) >> ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_2 */ -/* - * L3A20 (RW) - * - * Layer 3 Address 2 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) >> ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_3 */ -/* - * L3A30 (RW) - * - * Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) - -/* Bitfield definition for register: VLAN_TAG_INC_RPL */ -/* - * CSVL (RW) - * - * C-VLAN or S-VLAN - * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - */ -#define ENET_VLAN_TAG_INC_RPL_CSVL_MASK (0x80000UL) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT (19U) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) -#define ENET_VLAN_TAG_INC_RPL_CSVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) >> ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) - -/* - * VLP (RW) - * - * VLAN Priority Control - * When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - */ -#define ENET_VLAN_TAG_INC_RPL_VLP_MASK (0x40000UL) -#define ENET_VLAN_TAG_INC_RPL_VLP_SHIFT (18U) -#define ENET_VLAN_TAG_INC_RPL_VLP_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLP_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) >> ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) - -/* - * VLC (RW) - * - * VLAN Tag Control in Transmit Frames - * - 2’b00: No VLAN tag deletion, insertion, or replacement - * - 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. - * - 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. - * This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. - * - 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). - * Note: Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - */ -#define ENET_VLAN_TAG_INC_RPL_VLC_MASK (0x30000UL) -#define ENET_VLAN_TAG_INC_RPL_VLC_SHIFT (16U) -#define ENET_VLAN_TAG_INC_RPL_VLC_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLC_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) >> ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) - -/* - * VLT (RW) - * - * VLAN Tag for Transmit Frames - * This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - * Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - */ -#define ENET_VLAN_TAG_INC_RPL_VLT_MASK (0xFFFFU) -#define ENET_VLAN_TAG_INC_RPL_VLT_SHIFT (0U) -#define ENET_VLAN_TAG_INC_RPL_VLT_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLT_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) >> ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) - -/* Bitfield definition for register: VLAN_HASH */ -/* - * VLHT (RW) - * - * VLAN Hash Table - * This field contains the 16-bit VLAN Hash Table. - */ -#define ENET_VLAN_HASH_VLHT_MASK (0xFFFFU) -#define ENET_VLAN_HASH_VLHT_SHIFT (0U) -#define ENET_VLAN_HASH_VLHT_SET(x) (((uint32_t)(x) << ENET_VLAN_HASH_VLHT_SHIFT) & ENET_VLAN_HASH_VLHT_MASK) -#define ENET_VLAN_HASH_VLHT_GET(x) (((uint32_t)(x) & ENET_VLAN_HASH_VLHT_MASK) >> ENET_VLAN_HASH_VLHT_SHIFT) - -/* Bitfield definition for register: TS_CTRL */ -/* - * ATSEN3 (RW) - * - * Auxiliary Snapshot 3 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - */ -#define ENET_TS_CTRL_ATSEN3_MASK (0x10000000UL) -#define ENET_TS_CTRL_ATSEN3_SHIFT (28U) -#define ENET_TS_CTRL_ATSEN3_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN3_SHIFT) & ENET_TS_CTRL_ATSEN3_MASK) -#define ENET_TS_CTRL_ATSEN3_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN3_MASK) >> ENET_TS_CTRL_ATSEN3_SHIFT) - -/* - * ATSEN2 (RW) - * - * Auxiliary Snapshot 2 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - */ -#define ENET_TS_CTRL_ATSEN2_MASK (0x8000000UL) -#define ENET_TS_CTRL_ATSEN2_SHIFT (27U) -#define ENET_TS_CTRL_ATSEN2_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN2_SHIFT) & ENET_TS_CTRL_ATSEN2_MASK) -#define ENET_TS_CTRL_ATSEN2_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN2_MASK) >> ENET_TS_CTRL_ATSEN2_SHIFT) - -/* - * ATSEN1 (RW) - * - * Auxiliary Snapshot 1 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - */ -#define ENET_TS_CTRL_ATSEN1_MASK (0x4000000UL) -#define ENET_TS_CTRL_ATSEN1_SHIFT (26U) -#define ENET_TS_CTRL_ATSEN1_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN1_SHIFT) & ENET_TS_CTRL_ATSEN1_MASK) -#define ENET_TS_CTRL_ATSEN1_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN1_MASK) >> ENET_TS_CTRL_ATSEN1_SHIFT) - -/* - * ATSEN0 (RW) - * - * Auxiliary Snapshot 0 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - */ -#define ENET_TS_CTRL_ATSEN0_MASK (0x2000000UL) -#define ENET_TS_CTRL_ATSEN0_SHIFT (25U) -#define ENET_TS_CTRL_ATSEN0_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN0_SHIFT) & ENET_TS_CTRL_ATSEN0_MASK) -#define ENET_TS_CTRL_ATSEN0_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN0_MASK) >> ENET_TS_CTRL_ATSEN0_SHIFT) - -/* - * ATSFC (RW) - * - * Auxiliary Snapshot FIFO Clear - * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - */ -#define ENET_TS_CTRL_ATSFC_MASK (0x1000000UL) -#define ENET_TS_CTRL_ATSFC_SHIFT (24U) -#define ENET_TS_CTRL_ATSFC_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSFC_SHIFT) & ENET_TS_CTRL_ATSFC_MASK) -#define ENET_TS_CTRL_ATSFC_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSFC_MASK) >> ENET_TS_CTRL_ATSFC_SHIFT) - -/* - * TSENMACADDR (RW) - * - * Enable MAC address for PTP Frame Filtering - * When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - */ -#define ENET_TS_CTRL_TSENMACADDR_MASK (0x40000UL) -#define ENET_TS_CTRL_TSENMACADDR_SHIFT (18U) -#define ENET_TS_CTRL_TSENMACADDR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENMACADDR_SHIFT) & ENET_TS_CTRL_TSENMACADDR_MASK) -#define ENET_TS_CTRL_TSENMACADDR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENMACADDR_MASK) >> ENET_TS_CTRL_TSENMACADDR_SHIFT) - -/* - * SNAPTYPSEL (RW) - * - * Select PTP packets for Taking Snapshots - * These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - */ -#define ENET_TS_CTRL_SNAPTYPSEL_MASK (0x30000UL) -#define ENET_TS_CTRL_SNAPTYPSEL_SHIFT (16U) -#define ENET_TS_CTRL_SNAPTYPSEL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_SNAPTYPSEL_SHIFT) & ENET_TS_CTRL_SNAPTYPSEL_MASK) -#define ENET_TS_CTRL_SNAPTYPSEL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_SNAPTYPSEL_MASK) >> ENET_TS_CTRL_SNAPTYPSEL_SHIFT) - -/* - * TSMSTRENA (RW) - * - * Enable Snapshot for Messages Relevant to Master - * When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - */ -#define ENET_TS_CTRL_TSMSTRENA_MASK (0x8000U) -#define ENET_TS_CTRL_TSMSTRENA_SHIFT (15U) -#define ENET_TS_CTRL_TSMSTRENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSMSTRENA_SHIFT) & ENET_TS_CTRL_TSMSTRENA_MASK) -#define ENET_TS_CTRL_TSMSTRENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSMSTRENA_MASK) >> ENET_TS_CTRL_TSMSTRENA_SHIFT) - -/* - * TSEVNTENA (RW) - * - * Enable Timestamp Snapshot for Event Messages - * When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - */ -#define ENET_TS_CTRL_TSEVNTENA_MASK (0x4000U) -#define ENET_TS_CTRL_TSEVNTENA_SHIFT (14U) -#define ENET_TS_CTRL_TSEVNTENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSEVNTENA_SHIFT) & ENET_TS_CTRL_TSEVNTENA_MASK) -#define ENET_TS_CTRL_TSEVNTENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSEVNTENA_MASK) >> ENET_TS_CTRL_TSEVNTENA_SHIFT) - -/* - * TSIPV4ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv4-UDP - * When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - */ -#define ENET_TS_CTRL_TSIPV4ENA_MASK (0x2000U) -#define ENET_TS_CTRL_TSIPV4ENA_SHIFT (13U) -#define ENET_TS_CTRL_TSIPV4ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV4ENA_SHIFT) & ENET_TS_CTRL_TSIPV4ENA_MASK) -#define ENET_TS_CTRL_TSIPV4ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV4ENA_MASK) >> ENET_TS_CTRL_TSIPV4ENA_SHIFT) - -/* - * TSIPV6ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv6-UDP - * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - */ -#define ENET_TS_CTRL_TSIPV6ENA_MASK (0x1000U) -#define ENET_TS_CTRL_TSIPV6ENA_SHIFT (12U) -#define ENET_TS_CTRL_TSIPV6ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV6ENA_SHIFT) & ENET_TS_CTRL_TSIPV6ENA_MASK) -#define ENET_TS_CTRL_TSIPV6ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV6ENA_MASK) >> ENET_TS_CTRL_TSIPV6ENA_SHIFT) - -/* - * TSIPENA (RW) - * - * Enable Processing of PTP over Ethernet Frames - * When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - */ -#define ENET_TS_CTRL_TSIPENA_MASK (0x800U) -#define ENET_TS_CTRL_TSIPENA_SHIFT (11U) -#define ENET_TS_CTRL_TSIPENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPENA_SHIFT) & ENET_TS_CTRL_TSIPENA_MASK) -#define ENET_TS_CTRL_TSIPENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPENA_MASK) >> ENET_TS_CTRL_TSIPENA_SHIFT) - -/* - * TSVER2ENA (RW) - * - * Enable PTP packet Processing for Version 2 Format - * When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - */ -#define ENET_TS_CTRL_TSVER2ENA_MASK (0x400U) -#define ENET_TS_CTRL_TSVER2ENA_SHIFT (10U) -#define ENET_TS_CTRL_TSVER2ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSVER2ENA_SHIFT) & ENET_TS_CTRL_TSVER2ENA_MASK) -#define ENET_TS_CTRL_TSVER2ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSVER2ENA_MASK) >> ENET_TS_CTRL_TSVER2ENA_SHIFT) - -/* - * TSCTRLSSR (RW) - * - * Timestamp Digital or Binary Rollover Control - * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - * When reset, the rollover value of sub-second register is 0x7FFF_FFFF. - * The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - */ -#define ENET_TS_CTRL_TSCTRLSSR_MASK (0x200U) -#define ENET_TS_CTRL_TSCTRLSSR_SHIFT (9U) -#define ENET_TS_CTRL_TSCTRLSSR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCTRLSSR_SHIFT) & ENET_TS_CTRL_TSCTRLSSR_MASK) -#define ENET_TS_CTRL_TSCTRLSSR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCTRLSSR_MASK) >> ENET_TS_CTRL_TSCTRLSSR_SHIFT) - -/* - * TSENALL (RW) - * - * Enable Timestamp for All Frames - * When set, the timestamp snapshot is enabled for all frames received by the MAC. - */ -#define ENET_TS_CTRL_TSENALL_MASK (0x100U) -#define ENET_TS_CTRL_TSENALL_SHIFT (8U) -#define ENET_TS_CTRL_TSENALL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENALL_SHIFT) & ENET_TS_CTRL_TSENALL_MASK) -#define ENET_TS_CTRL_TSENALL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENALL_MASK) >> ENET_TS_CTRL_TSENALL_SHIFT) - -/* - * TSADDREG (RW) - * - * Addend Reg Update - * When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. - * This register bit should be zero before setting it. - */ -#define ENET_TS_CTRL_TSADDREG_MASK (0x20U) -#define ENET_TS_CTRL_TSADDREG_SHIFT (5U) -#define ENET_TS_CTRL_TSADDREG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSADDREG_SHIFT) & ENET_TS_CTRL_TSADDREG_MASK) -#define ENET_TS_CTRL_TSADDREG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSADDREG_MASK) >> ENET_TS_CTRL_TSADDREG_SHIFT) - -/* - * TSTRIG (RW) - * - * Timestamp Interrupt Trigger Enable - * When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. - * This bit is reset after the generation of the Timestamp Trigger Interrupt. - */ -#define ENET_TS_CTRL_TSTRIG_MASK (0x10U) -#define ENET_TS_CTRL_TSTRIG_SHIFT (4U) -#define ENET_TS_CTRL_TSTRIG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSTRIG_SHIFT) & ENET_TS_CTRL_TSTRIG_MASK) -#define ENET_TS_CTRL_TSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSTRIG_MASK) >> ENET_TS_CTRL_TSTRIG_SHIFT) - -/* - * TSUPDT (RW) - * - * Timestamp Update - * When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - */ -#define ENET_TS_CTRL_TSUPDT_MASK (0x8U) -#define ENET_TS_CTRL_TSUPDT_SHIFT (3U) -#define ENET_TS_CTRL_TSUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSUPDT_SHIFT) & ENET_TS_CTRL_TSUPDT_MASK) -#define ENET_TS_CTRL_TSUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSUPDT_MASK) >> ENET_TS_CTRL_TSUPDT_SHIFT) - -/* - * TSINIT (RW) - * - * Timestamp Initialize - * When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the initialization is complete. - * The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - */ -#define ENET_TS_CTRL_TSINIT_MASK (0x4U) -#define ENET_TS_CTRL_TSINIT_SHIFT (2U) -#define ENET_TS_CTRL_TSINIT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSINIT_SHIFT) & ENET_TS_CTRL_TSINIT_MASK) -#define ENET_TS_CTRL_TSINIT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSINIT_MASK) >> ENET_TS_CTRL_TSINIT_SHIFT) - -/* - * TSCFUPDT (RW) - * - * Timestamp Fine or Coarse Update - * When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - */ -#define ENET_TS_CTRL_TSCFUPDT_MASK (0x2U) -#define ENET_TS_CTRL_TSCFUPDT_SHIFT (1U) -#define ENET_TS_CTRL_TSCFUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCFUPDT_SHIFT) & ENET_TS_CTRL_TSCFUPDT_MASK) -#define ENET_TS_CTRL_TSCFUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCFUPDT_MASK) >> ENET_TS_CTRL_TSCFUPDT_SHIFT) - -/* - * TSENA (RW) - * - * Timestamp Enable - * When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. - * You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - */ -#define ENET_TS_CTRL_TSENA_MASK (0x1U) -#define ENET_TS_CTRL_TSENA_SHIFT (0U) -#define ENET_TS_CTRL_TSENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENA_SHIFT) & ENET_TS_CTRL_TSENA_MASK) -#define ENET_TS_CTRL_TSENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENA_MASK) >> ENET_TS_CTRL_TSENA_SHIFT) - -/* Bitfield definition for register: SUB_SEC_INCR */ -/* - * SSINC (RW) - * - * Sub-second Increment Value - * The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. - * For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) - * when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. - * When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. - * In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - */ -#define ENET_SUB_SEC_INCR_SSINC_MASK (0xFFU) -#define ENET_SUB_SEC_INCR_SSINC_SHIFT (0U) -#define ENET_SUB_SEC_INCR_SSINC_SET(x) (((uint32_t)(x) << ENET_SUB_SEC_INCR_SSINC_SHIFT) & ENET_SUB_SEC_INCR_SSINC_MASK) -#define ENET_SUB_SEC_INCR_SSINC_GET(x) (((uint32_t)(x) & ENET_SUB_SEC_INCR_SSINC_MASK) >> ENET_SUB_SEC_INCR_SSINC_SHIFT) - -/* Bitfield definition for register: SYST_SEC */ -/* - * TSS (RO) - * - * Timestamp Second - * The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - */ -#define ENET_SYST_SEC_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_TSS_SHIFT (0U) -#define ENET_SYST_SEC_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_TSS_MASK) >> ENET_SYST_SEC_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC */ -/* - * TSSS (RO) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - */ -#define ENET_SYST_NSEC_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_TSSS_MASK) >> ENET_SYST_NSEC_TSSS_SHIFT) - -/* Bitfield definition for register: SYST_SEC_UPD */ -/* - * TSS (RW) - * - * Timestamp Second - * The value in this field indicates the time in seconds to be initialized or added to the system time. - */ -#define ENET_SYST_SEC_UPD_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_UPD_TSS_SHIFT (0U) -#define ENET_SYST_SEC_UPD_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_UPD_TSS_SHIFT) & ENET_SYST_SEC_UPD_TSS_MASK) -#define ENET_SYST_SEC_UPD_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_UPD_TSS_MASK) >> ENET_SYST_SEC_UPD_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC_UPD */ -/* - * ADDSUB (RW) - * - * Add or Subtract Time - * When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - */ -#define ENET_SYST_NSEC_UPD_ADDSUB_MASK (0x80000000UL) -#define ENET_SYST_NSEC_UPD_ADDSUB_SHIFT (31U) -#define ENET_SYST_NSEC_UPD_ADDSUB_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) -#define ENET_SYST_NSEC_UPD_ADDSUB_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) >> ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) - -/* - * TSSS (RW) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - */ -#define ENET_SYST_NSEC_UPD_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_UPD_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_UPD_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_TSSS_SHIFT) & ENET_SYST_NSEC_UPD_TSSS_MASK) -#define ENET_SYST_NSEC_UPD_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_TSSS_MASK) >> ENET_SYST_NSEC_UPD_TSSS_SHIFT) - -/* Bitfield definition for register: TS_ADDEND */ -/* - * TSAR (RW) - * - * Timestamp Addend Register - * This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - */ -#define ENET_TS_ADDEND_TSAR_MASK (0xFFFFFFFFUL) -#define ENET_TS_ADDEND_TSAR_SHIFT (0U) -#define ENET_TS_ADDEND_TSAR_SET(x) (((uint32_t)(x) << ENET_TS_ADDEND_TSAR_SHIFT) & ENET_TS_ADDEND_TSAR_MASK) -#define ENET_TS_ADDEND_TSAR_GET(x) (((uint32_t)(x) & ENET_TS_ADDEND_TSAR_MASK) >> ENET_TS_ADDEND_TSAR_SHIFT) - -/* Bitfield definition for register: TGTTM_SEC */ -/* - * TSTR (RW) - * - * Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_TGTTM_SEC_TSTR_MASK (0xFFFFFFFFUL) -#define ENET_TGTTM_SEC_TSTR_SHIFT (0U) -#define ENET_TGTTM_SEC_TSTR_SET(x) (((uint32_t)(x) << ENET_TGTTM_SEC_TSTR_SHIFT) & ENET_TGTTM_SEC_TSTR_MASK) -#define ENET_TGTTM_SEC_TSTR_GET(x) (((uint32_t)(x) & ENET_TGTTM_SEC_TSTR_MASK) >> ENET_TGTTM_SEC_TSTR_SHIFT) - -/* Bitfield definition for register: TGTTM_NSEC */ -/* - * TRGTBUSY (RW) - * - * Target Time Register Busy - * The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Target Time Registers when this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - */ -#define ENET_TGTTM_NSEC_TRGTBUSY_MASK (0x80000000UL) -#define ENET_TGTTM_NSEC_TRGTBUSY_SHIFT (31U) -#define ENET_TGTTM_NSEC_TRGTBUSY_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) -#define ENET_TGTTM_NSEC_TRGTBUSY_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) >> ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) - -/* - * TTSLO (RW) - * - * Target Timestamp Low Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_TGTTM_NSEC_TTSLO_MASK (0x7FFFFFFFUL) -#define ENET_TGTTM_NSEC_TTSLO_SHIFT (0U) -#define ENET_TGTTM_NSEC_TTSLO_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TTSLO_SHIFT) & ENET_TGTTM_NSEC_TTSLO_MASK) -#define ENET_TGTTM_NSEC_TTSLO_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TTSLO_MASK) >> ENET_TGTTM_NSEC_TTSLO_SHIFT) - -/* Bitfield definition for register: SYSTM_H_SEC */ -/* - * TSHWR (RW) - * - * Timestamp Higher Word Register - * This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. - * The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - */ -#define ENET_SYSTM_H_SEC_TSHWR_MASK (0xFFFFU) -#define ENET_SYSTM_H_SEC_TSHWR_SHIFT (0U) -#define ENET_SYSTM_H_SEC_TSHWR_SET(x) (((uint32_t)(x) << ENET_SYSTM_H_SEC_TSHWR_SHIFT) & ENET_SYSTM_H_SEC_TSHWR_MASK) -#define ENET_SYSTM_H_SEC_TSHWR_GET(x) (((uint32_t)(x) & ENET_SYSTM_H_SEC_TSHWR_MASK) >> ENET_SYSTM_H_SEC_TSHWR_SHIFT) - -/* Bitfield definition for register: TS_STATUS */ -/* - * ATSNS (RO) - * - * Number of Auxiliary Timestamp Snapshots - * This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. - * These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. - * This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSNS_MASK (0x3E000000UL) -#define ENET_TS_STATUS_ATSNS_SHIFT (25U) -#define ENET_TS_STATUS_ATSNS_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSNS_MASK) >> ENET_TS_STATUS_ATSNS_SHIFT) - -/* - * ATSSTM (RO) - * - * Auxiliary Timestamp Snapshot Trigger Missed - * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. - * This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSSTM_MASK (0x1000000UL) -#define ENET_TS_STATUS_ATSSTM_SHIFT (24U) -#define ENET_TS_STATUS_ATSSTM_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTM_MASK) >> ENET_TS_STATUS_ATSSTM_SHIFT) - -/* - * ATSSTN (RO) - * - * Auxiliary Timestamp Snapshot Trigger Identifier - * These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. - * When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. - * These bits are applicable only if the number of Auxiliary snapshots is more than one. - * One bit is assigned for each trigger as shown in the following list: - * - Bit 16: Auxiliary trigger 0 - * - Bit 17: Auxiliary trigger 1 - * - Bit 18: Auxiliary trigger 2 - * - Bit 19: Auxiliary trigger 3 - * The software can read this register to find the triggers that are set when the timestamp is taken. - */ -#define ENET_TS_STATUS_ATSSTN_MASK (0xF0000UL) -#define ENET_TS_STATUS_ATSSTN_SHIFT (16U) -#define ENET_TS_STATUS_ATSSTN_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTN_MASK) >> ENET_TS_STATUS_ATSSTN_SHIFT) - -/* - * TSTRGTERR3 (RO) - * - * Timestamp Target Time Error - * This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - */ -#define ENET_TS_STATUS_TSTRGTERR3_MASK (0x200U) -#define ENET_TS_STATUS_TSTRGTERR3_SHIFT (9U) -#define ENET_TS_STATUS_TSTRGTERR3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR3_MASK) >> ENET_TS_STATUS_TSTRGTERR3_SHIFT) - -/* - * TSTARGT3 (RO) - * - * Timestamp Target Time Reached for Target Time PPS3 - * When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - */ -#define ENET_TS_STATUS_TSTARGT3_MASK (0x100U) -#define ENET_TS_STATUS_TSTARGT3_SHIFT (8U) -#define ENET_TS_STATUS_TSTARGT3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT3_MASK) >> ENET_TS_STATUS_TSTARGT3_SHIFT) - -/* - * TSTRGTERR2 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR2_MASK (0x80U) -#define ENET_TS_STATUS_TSTRGTERR2_SHIFT (7U) -#define ENET_TS_STATUS_TSTRGTERR2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR2_MASK) >> ENET_TS_STATUS_TSTRGTERR2_SHIFT) - -/* - * TSTARGT2 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT2_MASK (0x40U) -#define ENET_TS_STATUS_TSTARGT2_SHIFT (6U) -#define ENET_TS_STATUS_TSTARGT2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT2_MASK) >> ENET_TS_STATUS_TSTARGT2_SHIFT) - -/* - * TSTRGTERR1 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR1_MASK (0x20U) -#define ENET_TS_STATUS_TSTRGTERR1_SHIFT (5U) -#define ENET_TS_STATUS_TSTRGTERR1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR1_MASK) >> ENET_TS_STATUS_TSTRGTERR1_SHIFT) - -/* - * TSTARGT1 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT1_MASK (0x10U) -#define ENET_TS_STATUS_TSTARGT1_SHIFT (4U) -#define ENET_TS_STATUS_TSTARGT1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT1_MASK) >> ENET_TS_STATUS_TSTARGT1_SHIFT) - -/* - * TSTRGTERR (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR_MASK (0x8U) -#define ENET_TS_STATUS_TSTRGTERR_SHIFT (3U) -#define ENET_TS_STATUS_TSTRGTERR_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR_MASK) >> ENET_TS_STATUS_TSTRGTERR_SHIFT) - -/* - * AUXTSTRIG (RO) - * - */ -#define ENET_TS_STATUS_AUXTSTRIG_MASK (0x4U) -#define ENET_TS_STATUS_AUXTSTRIG_SHIFT (2U) -#define ENET_TS_STATUS_AUXTSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_AUXTSTRIG_MASK) >> ENET_TS_STATUS_AUXTSTRIG_SHIFT) - -/* - * TSTARGT (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT_MASK (0x2U) -#define ENET_TS_STATUS_TSTARGT_SHIFT (1U) -#define ENET_TS_STATUS_TSTARGT_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT_MASK) >> ENET_TS_STATUS_TSTARGT_SHIFT) - -/* - * TSSOVF (RO) - * - */ -#define ENET_TS_STATUS_TSSOVF_MASK (0x1U) -#define ENET_TS_STATUS_TSSOVF_SHIFT (0U) -#define ENET_TS_STATUS_TSSOVF_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSSOVF_MASK) >> ENET_TS_STATUS_TSSOVF_SHIFT) - -/* Bitfield definition for register: PPS_CTRL */ -/* - * TRGTMODSEL3 (RW) - * - * Target Time Register Mode for PPS3 Output - * This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL3_MASK (0x60000000UL) -#define ENET_PPS_CTRL_TRGTMODSEL3_SHIFT (29U) -#define ENET_PPS_CTRL_TRGTMODSEL3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) >> ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) - -/* - * PPSCMD3 (WO) - * - * Flexible PPS3 Output Control - * This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD3_MASK (0x7000000UL) -#define ENET_PPS_CTRL_PPSCMD3_SHIFT (24U) -#define ENET_PPS_CTRL_PPSCMD3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD3_SHIFT) & ENET_PPS_CTRL_PPSCMD3_MASK) -#define ENET_PPS_CTRL_PPSCMD3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD3_MASK) >> ENET_PPS_CTRL_PPSCMD3_SHIFT) - -/* - * TRGTMODSEL2 (RW) - * - * Target Time Register Mode for PPS2 Output - * This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL2_MASK (0x600000UL) -#define ENET_PPS_CTRL_TRGTMODSEL2_SHIFT (21U) -#define ENET_PPS_CTRL_TRGTMODSEL2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) >> ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) - -/* - * PPSCMD2 (WO) - * - * Flexible PPS2 Output Control - * This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD2_MASK (0x70000UL) -#define ENET_PPS_CTRL_PPSCMD2_SHIFT (16U) -#define ENET_PPS_CTRL_PPSCMD2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD2_SHIFT) & ENET_PPS_CTRL_PPSCMD2_MASK) -#define ENET_PPS_CTRL_PPSCMD2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD2_MASK) >> ENET_PPS_CTRL_PPSCMD2_SHIFT) - -/* - * TRGTMODSEL1 (RW) - * - * Target Time Register Mode for PPS1 Output - * This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL1_MASK (0x6000U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SHIFT (13U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) - -/* - * PPSCMD1 (WO) - * - * Flexible PPS1 Output Control - * This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD1_MASK (0x700U) -#define ENET_PPS_CTRL_PPSCMD1_SHIFT (8U) -#define ENET_PPS_CTRL_PPSCMD1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD1_SHIFT) & ENET_PPS_CTRL_PPSCMD1_MASK) -#define ENET_PPS_CTRL_PPSCMD1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD1_MASK) >> ENET_PPS_CTRL_PPSCMD1_SHIFT) - -/* - * TRGTMODSEL0 (RW) - * - * Target Time Register Mode for PPS0 Output - * This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: - * - 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. - * - 01: Reserved - * - 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. - * - 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - */ -#define ENET_PPS_CTRL_TRGTMODSEL0_MASK (0x60U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SHIFT (5U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) >> ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) - -/* - * PPSEN0 (RW) - * - * Flexible PPS Output Mode Enable - * When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - */ -#define ENET_PPS_CTRL_PPSEN0_MASK (0x10U) -#define ENET_PPS_CTRL_PPSEN0_SHIFT (4U) -#define ENET_PPS_CTRL_PPSEN0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN0_SHIFT) & ENET_PPS_CTRL_PPSEN0_MASK) -#define ENET_PPS_CTRL_PPSEN0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN0_MASK) >> ENET_PPS_CTRL_PPSEN0_SHIFT) - -/* - * PPSCTRLCMD0 (RW/WO) - * - * PPSCTRL0: PPS0 Output Frequency Control - * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. - * The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. - * For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: - * - 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. - * - 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. - * - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. - * - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... - * - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. - * Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. - * In the digital rollover mode, the PPS output frequency is an average number. - * The actual clock is of different frequency that gets synchronized every second. For example: - * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - * - One clock of 50 percent duty cycle and 537 ms period - * - Second clock of 463 ms period (268 ms low and 195 ms high) - * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - * - Three clocks of 50 percent duty cycle and 268 ms period - * - Fourth clock of 195 ms period (134 ms low and 61 ms high) - * PPSCMD0: Flexible PPS0 Output Control - * 0000: No Command - * 0001: START Single Pulse - * This command generates single pulse rising at the start point defined in - * Target Time Registers and of a duration defined - * in the PPS0 Width Register. - * 0010: START Pulse Train - * This command generates the train of pulses rising at the start point - * defined in the Target Time Registers and of a duration defined in the - * PPS0 Width Register and repeated at interval defined in the PPS - * Interval Register. By default, the PPS pulse train is free-running unless - * stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train - * immediately’ commands. - * 0011: Cancel START - * This command cancels the START Single Pulse and START Pulse Train - * commands if the system time has not crossed the programmed start - * time. - * 0100: STOP Pulse train at time - * This command stops the train of pulses initiated by the START Pulse - * Train command (PPSCMD = 0010) after the time programmed in the - * Target Time registers elapses. - * 0101: STOP Pulse Train immediately - * This command immediately stops the train of pulses initiated by the - * START Pulse Train command (PPSCMD = 0010). - * 0110: Cancel STOP Pulse train - * This command cancels the STOP pulse train at time command if the - * programmed stop time has not elapsed. The PPS pulse train becomes - * free-running on the successful execution of this command. - * 0111-1111: Reserved - * Note: These bits get cleared automatically - */ -#define ENET_PPS_CTRL_PPSCTRLCMD0_MASK (0xFU) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT (0U) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) -#define ENET_PPS_CTRL_PPSCTRLCMD0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) >> ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) - -/* Bitfield definition for register: AUX_TS_NSEC */ -/* - * AUXTSLO (RO) - * - * Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - */ -#define ENET_AUX_TS_NSEC_AUXTSLO_MASK (0x7FFFFFFFUL) -#define ENET_AUX_TS_NSEC_AUXTSLO_SHIFT (0U) -#define ENET_AUX_TS_NSEC_AUXTSLO_GET(x) (((uint32_t)(x) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) >> ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) - -/* Bitfield definition for register: AUX_TS_SEC */ -/* - * AUXTSHI (RO) - * - * Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - */ -#define ENET_AUX_TS_SEC_AUXTSHI_MASK (0xFFFFFFFFUL) -#define ENET_AUX_TS_SEC_AUXTSHI_SHIFT (0U) -#define ENET_AUX_TS_SEC_AUXTSHI_GET(x) (((uint32_t)(x) & ENET_AUX_TS_SEC_AUXTSHI_MASK) >> ENET_AUX_TS_SEC_AUXTSHI_SHIFT) - -/* Bitfield definition for register: PPS0_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS0 Output Signal Interval - * These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS0 signal output is 100ns - * (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS0_INTERVAL_PPSINT_SHIFT) & ENET_PPS0_INTERVAL_PPSINT_MASK) -#define ENET_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS0_INTERVAL_PPSINT_MASK) >> ENET_PPS0_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PPS0_WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS0 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - * (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS0_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS0_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS0_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) >> ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_SEC */ -/* - * TSTRH1 (RW) - * - * PPS1 Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_PPS_TGTTM_SEC_TSTRH1_MASK (0xFFFFFFFFUL) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT (0U) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) -#define ENET_PPS_TGTTM_SEC_TSTRH1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) >> ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_NSEC */ -/* - * TRGTBUSY1 (RW) - * - * PPS1 Target Time Register Busy - * The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Targeers wht Time Registen this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. - */ -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK (0x80000000UL) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT (31U) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) >> ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) - -/* - * TTSL1 (RW) - * - * Target Time Low for PPS1 Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_PPS_TGTTM_NSEC_TTSL1_MASK (0x7FFFFFFFUL) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT (0U) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) -#define ENET_PPS_TGTTM_NSEC_TTSL1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) >> ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) - -/* Bitfield definition for register of struct array PPS: INTERVAL */ -/* - * PPSINT (RW) - * - * PPS1 Output Signal Interval - * These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), - * then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS_INTERVAL_PPSINT_SHIFT) & ENET_PPS_INTERVAL_PPSINT_MASK) -#define ENET_PPS_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS_INTERVAL_PPSINT_MASK) >> ENET_PPS_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register of struct array PPS: WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS1 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, - * if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), - * then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS_WIDTH_PPSWIDTH_MASK) >> ENET_PPS_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register: DMA_BUS_MODE */ -/* - * RIB (RW) - * - * Rebuild INCRx Burst - * When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - * the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. - * The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. - * By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - */ -#define ENET_DMA_BUS_MODE_RIB_MASK (0x80000000UL) -#define ENET_DMA_BUS_MODE_RIB_SHIFT (31U) -#define ENET_DMA_BUS_MODE_RIB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RIB_SHIFT) & ENET_DMA_BUS_MODE_RIB_MASK) -#define ENET_DMA_BUS_MODE_RIB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RIB_MASK) >> ENET_DMA_BUS_MODE_RIB_SHIFT) - -/* - * PRWG (RW) - * - * Channel Priority - * Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. - * - 00: The priority weight is 1. - * - 01: The priority weight is 2. - * - 10: The priority weight is 3. - * - 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_PRWG_MASK (0x30000000UL) -#define ENET_DMA_BUS_MODE_PRWG_SHIFT (28U) -#define ENET_DMA_BUS_MODE_PRWG_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PRWG_SHIFT) & ENET_DMA_BUS_MODE_PRWG_MASK) -#define ENET_DMA_BUS_MODE_PRWG_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PRWG_MASK) >> ENET_DMA_BUS_MODE_PRWG_SHIFT) - -/* - * TXPR (RW) - * - * Transmit Priority - * When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_TXPR_MASK (0x8000000UL) -#define ENET_DMA_BUS_MODE_TXPR_SHIFT (27U) -#define ENET_DMA_BUS_MODE_TXPR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_TXPR_SHIFT) & ENET_DMA_BUS_MODE_TXPR_MASK) -#define ENET_DMA_BUS_MODE_TXPR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_TXPR_MASK) >> ENET_DMA_BUS_MODE_TXPR_SHIFT) - -/* - * MB (RW) - * - * Mixed Burst - * When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), - * whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - */ -#define ENET_DMA_BUS_MODE_MB_MASK (0x4000000UL) -#define ENET_DMA_BUS_MODE_MB_SHIFT (26U) -#define ENET_DMA_BUS_MODE_MB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_MB_SHIFT) & ENET_DMA_BUS_MODE_MB_MASK) -#define ENET_DMA_BUS_MODE_MB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_MB_MASK) >> ENET_DMA_BUS_MODE_MB_SHIFT) - -/* - * AAL (RW) - * - * Address-Aligned Beats - * When this bit is set high and the FB bit is equal to 1, - * the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - * the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - */ -#define ENET_DMA_BUS_MODE_AAL_MASK (0x2000000UL) -#define ENET_DMA_BUS_MODE_AAL_SHIFT (25U) -#define ENET_DMA_BUS_MODE_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_AAL_SHIFT) & ENET_DMA_BUS_MODE_AAL_MASK) -#define ENET_DMA_BUS_MODE_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_AAL_MASK) >> ENET_DMA_BUS_MODE_AAL_SHIFT) - -/* - * PBLX8 (RW) - * - * PBLx8 Mode - * When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. - * Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - */ -#define ENET_DMA_BUS_MODE_PBLX8_MASK (0x1000000UL) -#define ENET_DMA_BUS_MODE_PBLX8_SHIFT (24U) -#define ENET_DMA_BUS_MODE_PBLX8_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBLX8_SHIFT) & ENET_DMA_BUS_MODE_PBLX8_MASK) -#define ENET_DMA_BUS_MODE_PBLX8_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBLX8_MASK) >> ENET_DMA_BUS_MODE_PBLX8_SHIFT) - -/* - * USP (RW) - * - * Use Separate PBL - * When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. - * The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. - * When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - */ -#define ENET_DMA_BUS_MODE_USP_MASK (0x800000UL) -#define ENET_DMA_BUS_MODE_USP_SHIFT (23U) -#define ENET_DMA_BUS_MODE_USP_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_USP_SHIFT) & ENET_DMA_BUS_MODE_USP_MASK) -#define ENET_DMA_BUS_MODE_USP_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_USP_MASK) >> ENET_DMA_BUS_MODE_USP_SHIFT) - -/* - * RPBL (RW) - * - * Rx DMA PBL - * This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - * You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. - * This field is valid and applicable only when USP is set high. - */ -#define ENET_DMA_BUS_MODE_RPBL_MASK (0x7E0000UL) -#define ENET_DMA_BUS_MODE_RPBL_SHIFT (17U) -#define ENET_DMA_BUS_MODE_RPBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RPBL_SHIFT) & ENET_DMA_BUS_MODE_RPBL_MASK) -#define ENET_DMA_BUS_MODE_RPBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RPBL_MASK) >> ENET_DMA_BUS_MODE_RPBL_SHIFT) - -/* - * FB (RW) - * - * Fixed Burst - * This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. - * When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. - * When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - */ -#define ENET_DMA_BUS_MODE_FB_MASK (0x10000UL) -#define ENET_DMA_BUS_MODE_FB_SHIFT (16U) -#define ENET_DMA_BUS_MODE_FB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_FB_SHIFT) & ENET_DMA_BUS_MODE_FB_MASK) -#define ENET_DMA_BUS_MODE_FB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_FB_MASK) >> ENET_DMA_BUS_MODE_FB_SHIFT) - -/* - * PR (RW) - * - * Priority Ratio - * These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - * These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. - * - 00: The Priority Ratio is 1:1. - * - 01: The Priority Ratio is 2:1. - * - 10: The Priority Ratio is 3:1. - * - 11: The Priority Ratio is 4:1. - */ -#define ENET_DMA_BUS_MODE_PR_MASK (0xC000U) -#define ENET_DMA_BUS_MODE_PR_SHIFT (14U) -#define ENET_DMA_BUS_MODE_PR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PR_SHIFT) & ENET_DMA_BUS_MODE_PR_MASK) -#define ENET_DMA_BUS_MODE_PR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PR_MASK) >> ENET_DMA_BUS_MODE_PR_SHIFT) - -/* - * PBL (RW) - * - * Programmable Burst Length - * These bits indicate the maximum number of beats to be transferred in one DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. - * PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. - * Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. - * If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - */ -#define ENET_DMA_BUS_MODE_PBL_MASK (0x3F00U) -#define ENET_DMA_BUS_MODE_PBL_SHIFT (8U) -#define ENET_DMA_BUS_MODE_PBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBL_SHIFT) & ENET_DMA_BUS_MODE_PBL_MASK) -#define ENET_DMA_BUS_MODE_PBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBL_MASK) >> ENET_DMA_BUS_MODE_PBL_SHIFT) - -/* - * ATDS (RW) - * - * Alternate Descriptor Size - * When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). - * This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. - * The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - * In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. - * This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - * - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. - * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - */ -#define ENET_DMA_BUS_MODE_ATDS_MASK (0x80U) -#define ENET_DMA_BUS_MODE_ATDS_SHIFT (7U) -#define ENET_DMA_BUS_MODE_ATDS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_ATDS_SHIFT) & ENET_DMA_BUS_MODE_ATDS_MASK) -#define ENET_DMA_BUS_MODE_ATDS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_ATDS_MASK) >> ENET_DMA_BUS_MODE_ATDS_SHIFT) - -/* - * DSL (RW) - * - * Descriptor Skip Length - * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. - * The address skipping starts from the end of current descriptor to the start of next descriptor. - * When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - */ -#define ENET_DMA_BUS_MODE_DSL_MASK (0x7CU) -#define ENET_DMA_BUS_MODE_DSL_SHIFT (2U) -#define ENET_DMA_BUS_MODE_DSL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DSL_SHIFT) & ENET_DMA_BUS_MODE_DSL_MASK) -#define ENET_DMA_BUS_MODE_DSL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DSL_MASK) >> ENET_DMA_BUS_MODE_DSL_SHIFT) - -/* - * DA (RW) - * - * DMA Arbitration Scheme - * This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. - * - 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). - * - 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - */ -#define ENET_DMA_BUS_MODE_DA_MASK (0x2U) -#define ENET_DMA_BUS_MODE_DA_SHIFT (1U) -#define ENET_DMA_BUS_MODE_DA_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DA_SHIFT) & ENET_DMA_BUS_MODE_DA_MASK) -#define ENET_DMA_BUS_MODE_DA_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DA_MASK) >> ENET_DMA_BUS_MODE_DA_SHIFT) - -/* - * SWR (RW) - * - * Software Reset - * When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. - * It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. - * Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. - * Note: - The Software reset function is driven only by this bit. - * Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - * - The reset operation is completed only when all resets in all active clock domains are de-asserted. - * Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. - * The time to complete the software reset operation depends on the frequency of the slowest active clock. - */ -#define ENET_DMA_BUS_MODE_SWR_MASK (0x1U) -#define ENET_DMA_BUS_MODE_SWR_SHIFT (0U) -#define ENET_DMA_BUS_MODE_SWR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_SWR_SHIFT) & ENET_DMA_BUS_MODE_SWR_MASK) -#define ENET_DMA_BUS_MODE_SWR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_SWR_MASK) >> ENET_DMA_BUS_MODE_SWR_SHIFT) - -/* Bitfield definition for register: DMA_TX_POLL_DEMAND */ -/* - * TPD (RW) - * - * Transmit Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the transmission resumes. - */ -#define ENET_DMA_TX_POLL_DEMAND_TPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT (0U) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SET(x) (((uint32_t)(x) << ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) -#define ENET_DMA_TX_POLL_DEMAND_TPD_GET(x) (((uint32_t)(x) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) >> ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_POLL_DEMAND */ -/* - * RPD (RW) - * - * Receive Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the Rx DMA returns to the active state. - */ -#define ENET_DMA_RX_POLL_DEMAND_RPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT (0U) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SET(x) (((uint32_t)(x) << ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) -#define ENET_DMA_RX_POLL_DEMAND_RPD_GET(x) (((uint32_t)(x) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) >> ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_DESC_LIST_ADDR */ -/* - * RDESLA (RW) - * - * Start of Receive List - * This field contains the base address of the first descriptor in the Receive Descriptor list. - * The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT (0U) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) >> ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) - -/* Bitfield definition for register: DMA_TX_DESC_LIST_ADDR */ -/* - * TDESLA (RW) - * - * Start of Transmit List - * This field contains the base address of the first descriptor in the Transmit Descriptor list. - * The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT (0U) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) >> ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) - -/* Bitfield definition for register: DMA_STATUS */ -/* - * GLPII (RW) - * - * GLPII: GMAC LPI Interrupt (for Channel 0) - * This bit indicates an interrupt event in the LPI logic of the MAC. - * To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. - * Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. - * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - * -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. - * To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. - * Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. - * Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - */ -#define ENET_DMA_STATUS_GLPII_MASK (0x40000000UL) -#define ENET_DMA_STATUS_GLPII_SHIFT (30U) -#define ENET_DMA_STATUS_GLPII_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLPII_SHIFT) & ENET_DMA_STATUS_GLPII_MASK) -#define ENET_DMA_STATUS_GLPII_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLPII_MASK) >> ENET_DMA_STATUS_GLPII_SHIFT) - -/* - * TTI (RW) - * - * Timestamp Trigger Interrupt - * This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - * When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. - * This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_TTI_MASK (0x20000000UL) -#define ENET_DMA_STATUS_TTI_SHIFT (29U) -#define ENET_DMA_STATUS_TTI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TTI_SHIFT) & ENET_DMA_STATUS_TTI_MASK) -#define ENET_DMA_STATUS_TTI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TTI_MASK) >> ENET_DMA_STATUS_TTI_SHIFT) - -/* - * GPI (RW) - * - * GMAC PMT Interrupt - * This bit indicates an interrupt event in the PMT module of the DWC_gmac. - * The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the Power Management feature is enabled. - * Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - */ -#define ENET_DMA_STATUS_GPI_MASK (0x10000000UL) -#define ENET_DMA_STATUS_GPI_SHIFT (28U) -#define ENET_DMA_STATUS_GPI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GPI_SHIFT) & ENET_DMA_STATUS_GPI_MASK) -#define ENET_DMA_STATUS_GPI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GPI_MASK) >> ENET_DMA_STATUS_GPI_SHIFT) - -/* - * GMI (RW) - * - * GMAC MMC Interrupt - * This bit reflects an interrupt event in the MMC module of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac - * to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_GMI_MASK (0x8000000UL) -#define ENET_DMA_STATUS_GMI_SHIFT (27U) -#define ENET_DMA_STATUS_GMI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GMI_SHIFT) & ENET_DMA_STATUS_GMI_MASK) -#define ENET_DMA_STATUS_GMI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GMI_MASK) >> ENET_DMA_STATUS_GMI_SHIFT) - -/* - * GLI (RW) - * - * GMAC Line Interface Interrupt - * When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - * - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - * - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - * Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - * the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - * read any of the following corresponding registers: - * - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - * - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - * - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - */ -#define ENET_DMA_STATUS_GLI_MASK (0x4000000UL) -#define ENET_DMA_STATUS_GLI_SHIFT (26U) -#define ENET_DMA_STATUS_GLI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLI_SHIFT) & ENET_DMA_STATUS_GLI_MASK) -#define ENET_DMA_STATUS_GLI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLI_MASK) >> ENET_DMA_STATUS_GLI_SHIFT) - -/* - * EB (RW) - * - * Error Bits - * This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - * This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. - * - 0 0 0: Error during Rx DMA Write Data Transfer - * - 0 1 1: Error during Tx DMA Read Data Transfer - * - 1 0 0: Error during Rx DMA Descriptor Write Access - * - 1 0 1: Error during Tx DMA Descriptor Write Access - * - 1 1 0: Error during Rx DMA Descriptor Read Access - * - 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - */ -#define ENET_DMA_STATUS_EB_MASK (0x3800000UL) -#define ENET_DMA_STATUS_EB_SHIFT (23U) -#define ENET_DMA_STATUS_EB_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_EB_SHIFT) & ENET_DMA_STATUS_EB_MASK) -#define ENET_DMA_STATUS_EB_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_EB_MASK) >> ENET_DMA_STATUS_EB_SHIFT) - -/* - * TS (RW) - * - * Transmit Process State - * This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped; Reset or Stop Transmit Command issued - * - 3’b001: Running; Fetching Transmit Transfer Descriptor - * - 3’b010: Running; Waiting for status - * - 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) - * - 3’b100: TIME_STAMP write state - * - 3’b101: Reserved for future use - * - 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow - * - 3’b111: Running; Closing Transmit Descriptor - */ -#define ENET_DMA_STATUS_TS_MASK (0x700000UL) -#define ENET_DMA_STATUS_TS_SHIFT (20U) -#define ENET_DMA_STATUS_TS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TS_SHIFT) & ENET_DMA_STATUS_TS_MASK) -#define ENET_DMA_STATUS_TS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TS_MASK) >> ENET_DMA_STATUS_TS_SHIFT) - -/* - * RS (RW) - * - * Receive Process State - * This field indicates the Receive DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped: Reset or Stop Receive Command issued - * - 3’b001: Running: Fetching Receive Transfer Descriptor - * - 3’b010: Reserved for future use - * - 3’b011: Running: Waiting for receive packet - * - 3’b100: Suspended: Receive Descriptor Unavailable - * - 3’b101: Running: Closing Receive Descriptor - * - 3’b110: TIME_STAMP write state - * - 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - */ -#define ENET_DMA_STATUS_RS_MASK (0xE0000UL) -#define ENET_DMA_STATUS_RS_SHIFT (17U) -#define ENET_DMA_STATUS_RS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RS_SHIFT) & ENET_DMA_STATUS_RS_MASK) -#define ENET_DMA_STATUS_RS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RS_MASK) >> ENET_DMA_STATUS_RS_SHIFT) - -/* - * NIS (RW) - * - * Normal Interrupt Summary - * Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in - * Register 7 (Interrupt Enable Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt Only unmasked bits - * (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_NIS_MASK (0x10000UL) -#define ENET_DMA_STATUS_NIS_SHIFT (16U) -#define ENET_DMA_STATUS_NIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_NIS_SHIFT) & ENET_DMA_STATUS_NIS_MASK) -#define ENET_DMA_STATUS_NIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_NIS_MASK) >> ENET_DMA_STATUS_NIS_SHIFT) - -/* - * AIS (RW) - * - * Abnormal Interrupt Summary - * Abnormal Interrupt Summary bit value is the logical OR of the following - * when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive FIFO Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_AIS_MASK (0x8000U) -#define ENET_DMA_STATUS_AIS_SHIFT (15U) -#define ENET_DMA_STATUS_AIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_AIS_SHIFT) & ENET_DMA_STATUS_AIS_MASK) -#define ENET_DMA_STATUS_AIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_AIS_MASK) >> ENET_DMA_STATUS_AIS_SHIFT) - -/* - * ERI (RW) - * - * Early Receive Interrupt - * This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - */ -#define ENET_DMA_STATUS_ERI_MASK (0x4000U) -#define ENET_DMA_STATUS_ERI_SHIFT (14U) -#define ENET_DMA_STATUS_ERI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ERI_SHIFT) & ENET_DMA_STATUS_ERI_MASK) -#define ENET_DMA_STATUS_ERI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ERI_MASK) >> ENET_DMA_STATUS_ERI_SHIFT) - -/* - * FBI (RW) - * - * Fatal Bus Error Interrupt - * This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - */ -#define ENET_DMA_STATUS_FBI_MASK (0x2000U) -#define ENET_DMA_STATUS_FBI_SHIFT (13U) -#define ENET_DMA_STATUS_FBI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_FBI_SHIFT) & ENET_DMA_STATUS_FBI_MASK) -#define ENET_DMA_STATUS_FBI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_FBI_MASK) >> ENET_DMA_STATUS_FBI_SHIFT) - -/* - * ETI (RW) - * - * Early Transmit Interrupt - * This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - */ -#define ENET_DMA_STATUS_ETI_MASK (0x400U) -#define ENET_DMA_STATUS_ETI_SHIFT (10U) -#define ENET_DMA_STATUS_ETI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ETI_SHIFT) & ENET_DMA_STATUS_ETI_MASK) -#define ENET_DMA_STATUS_ETI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ETI_MASK) >> ENET_DMA_STATUS_ETI_SHIFT) - -/* - * RWT (RW) - * - * Receive Watchdog Timeout - * When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - */ -#define ENET_DMA_STATUS_RWT_MASK (0x200U) -#define ENET_DMA_STATUS_RWT_SHIFT (9U) -#define ENET_DMA_STATUS_RWT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RWT_SHIFT) & ENET_DMA_STATUS_RWT_MASK) -#define ENET_DMA_STATUS_RWT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RWT_MASK) >> ENET_DMA_STATUS_RWT_SHIFT) - -/* - * RPS (RW) - * - * Receive Process Stopped - * This bit is asserted when the Receive Process enters the Stopped state. - */ -#define ENET_DMA_STATUS_RPS_MASK (0x100U) -#define ENET_DMA_STATUS_RPS_SHIFT (8U) -#define ENET_DMA_STATUS_RPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RPS_SHIFT) & ENET_DMA_STATUS_RPS_MASK) -#define ENET_DMA_STATUS_RPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RPS_MASK) >> ENET_DMA_STATUS_RPS_SHIFT) - -/* - * RU (RW) - * - * Receive Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. - * The Receive Process is suspended. To resume processing Receive descriptors, - * the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - * If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. - * This bit is set only when the previous Receive Descriptor is owned by the DMA. - */ -#define ENET_DMA_STATUS_RU_MASK (0x80U) -#define ENET_DMA_STATUS_RU_SHIFT (7U) -#define ENET_DMA_STATUS_RU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RU_SHIFT) & ENET_DMA_STATUS_RU_MASK) -#define ENET_DMA_STATUS_RU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RU_MASK) >> ENET_DMA_STATUS_RU_SHIFT) - -/* - * RI (RW) - * - * Receive Interrupt - * This bit indicates that the frame reception is complete. - * When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, - * and the specific frame status information is updated in the descriptor. - * The reception remains in the Running state. - */ -#define ENET_DMA_STATUS_RI_MASK (0x40U) -#define ENET_DMA_STATUS_RI_SHIFT (6U) -#define ENET_DMA_STATUS_RI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RI_SHIFT) & ENET_DMA_STATUS_RI_MASK) -#define ENET_DMA_STATUS_RI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RI_MASK) >> ENET_DMA_STATUS_RI_SHIFT) - -/* - * UNF (RW) - * - * Transmit Underflow - * This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - */ -#define ENET_DMA_STATUS_UNF_MASK (0x20U) -#define ENET_DMA_STATUS_UNF_SHIFT (5U) -#define ENET_DMA_STATUS_UNF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_UNF_SHIFT) & ENET_DMA_STATUS_UNF_MASK) -#define ENET_DMA_STATUS_UNF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_UNF_MASK) >> ENET_DMA_STATUS_UNF_SHIFT) - -/* - * OVF (RW) - * - * Receive Overflow - * This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - */ -#define ENET_DMA_STATUS_OVF_MASK (0x10U) -#define ENET_DMA_STATUS_OVF_SHIFT (4U) -#define ENET_DMA_STATUS_OVF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_OVF_SHIFT) & ENET_DMA_STATUS_OVF_MASK) -#define ENET_DMA_STATUS_OVF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_OVF_MASK) >> ENET_DMA_STATUS_OVF_SHIFT) - -/* - * TJT (RW) - * - * Transmit Jabber Timeout - * This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). - * When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - */ -#define ENET_DMA_STATUS_TJT_MASK (0x8U) -#define ENET_DMA_STATUS_TJT_SHIFT (3U) -#define ENET_DMA_STATUS_TJT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TJT_SHIFT) & ENET_DMA_STATUS_TJT_MASK) -#define ENET_DMA_STATUS_TJT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TJT_MASK) >> ENET_DMA_STATUS_TJT_SHIFT) - -/* - * TU (RW) - * - * Transmit Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. - * To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - */ -#define ENET_DMA_STATUS_TU_MASK (0x4U) -#define ENET_DMA_STATUS_TU_SHIFT (2U) -#define ENET_DMA_STATUS_TU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TU_SHIFT) & ENET_DMA_STATUS_TU_MASK) -#define ENET_DMA_STATUS_TU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TU_MASK) >> ENET_DMA_STATUS_TU_SHIFT) - -/* - * TPS (RW) - * - * Transmit Process Stopped - * This bit is set when the transmission is stopped. - */ -#define ENET_DMA_STATUS_TPS_MASK (0x2U) -#define ENET_DMA_STATUS_TPS_SHIFT (1U) -#define ENET_DMA_STATUS_TPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TPS_SHIFT) & ENET_DMA_STATUS_TPS_MASK) -#define ENET_DMA_STATUS_TPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TPS_MASK) >> ENET_DMA_STATUS_TPS_SHIFT) - -/* - * TI (RW) - * - * Transmit Interrupt - * This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - */ -#define ENET_DMA_STATUS_TI_MASK (0x1U) -#define ENET_DMA_STATUS_TI_SHIFT (0U) -#define ENET_DMA_STATUS_TI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TI_SHIFT) & ENET_DMA_STATUS_TI_MASK) -#define ENET_DMA_STATUS_TI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TI_MASK) >> ENET_DMA_STATUS_TI_SHIFT) - -/* Bitfield definition for register: DMA_OP_MODE */ -/* - * DT (RW) - * - * Disable Dropping of TCP/IP Checksum Error Frames - * When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - * Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. - * When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - */ -#define ENET_DMA_OP_MODE_DT_MASK (0x10000000UL) -#define ENET_DMA_OP_MODE_DT_SHIFT (28U) -#define ENET_DMA_OP_MODE_DT_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DT_SHIFT) & ENET_DMA_OP_MODE_DT_MASK) -#define ENET_DMA_OP_MODE_DT_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DT_MASK) >> ENET_DMA_OP_MODE_DT_SHIFT) - -/* - * RSF (RW) - * - * Receive Store and Forward - * When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - * When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - */ -#define ENET_DMA_OP_MODE_RSF_MASK (0x2000000UL) -#define ENET_DMA_OP_MODE_RSF_SHIFT (25U) -#define ENET_DMA_OP_MODE_RSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RSF_SHIFT) & ENET_DMA_OP_MODE_RSF_MASK) -#define ENET_DMA_OP_MODE_RSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RSF_MASK) >> ENET_DMA_OP_MODE_RSF_SHIFT) - -/* - * DFF (RW) - * - * Disable Flushing of Received Frames - * When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - */ -#define ENET_DMA_OP_MODE_DFF_MASK (0x1000000UL) -#define ENET_DMA_OP_MODE_DFF_SHIFT (24U) -#define ENET_DMA_OP_MODE_DFF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DFF_SHIFT) & ENET_DMA_OP_MODE_DFF_MASK) -#define ENET_DMA_OP_MODE_DFF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DFF_MASK) >> ENET_DMA_OP_MODE_DFF_SHIFT) - -/* - * RFA_2 (RW) - * - * MSB of Threshold for Activating Flow Control - * If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFA_2_MASK (0x800000UL) -#define ENET_DMA_OP_MODE_RFA_2_SHIFT (23U) -#define ENET_DMA_OP_MODE_RFA_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_2_SHIFT) & ENET_DMA_OP_MODE_RFA_2_MASK) -#define ENET_DMA_OP_MODE_RFA_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_2_MASK) >> ENET_DMA_OP_MODE_RFA_2_SHIFT) - -/* - * RFD_2 (RW) - * - * MSB of Threshold for Deactivating Flow Control - * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFD_2_MASK (0x400000UL) -#define ENET_DMA_OP_MODE_RFD_2_SHIFT (22U) -#define ENET_DMA_OP_MODE_RFD_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_2_SHIFT) & ENET_DMA_OP_MODE_RFD_2_MASK) -#define ENET_DMA_OP_MODE_RFD_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_2_MASK) >> ENET_DMA_OP_MODE_RFD_2_SHIFT) - -/* - * TSF (RW) - * - * Transmit Store and Forward - * When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. - * When this bit is set, the TTC values specified in Bits [16:14] are ignored. - * This bit should be changed only when the transmission is stopped. - */ -#define ENET_DMA_OP_MODE_TSF_MASK (0x200000UL) -#define ENET_DMA_OP_MODE_TSF_SHIFT (21U) -#define ENET_DMA_OP_MODE_TSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TSF_SHIFT) & ENET_DMA_OP_MODE_TSF_MASK) -#define ENET_DMA_OP_MODE_TSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TSF_MASK) >> ENET_DMA_OP_MODE_TSF_SHIFT) - -/* - * FTF (RW) - * - * Flush Transmit FIFO - * When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. - * This bit is cleared internally when the flushing operation is complete. - * The Operation Mode register should not be written to until this bit is cleared. - * The data which is already accepted by the MAC transmitter is not flushed. - * It is scheduled for transmission and results in underflow and runt frame transmission. - */ -#define ENET_DMA_OP_MODE_FTF_MASK (0x100000UL) -#define ENET_DMA_OP_MODE_FTF_SHIFT (20U) -#define ENET_DMA_OP_MODE_FTF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FTF_SHIFT) & ENET_DMA_OP_MODE_FTF_MASK) -#define ENET_DMA_OP_MODE_FTF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FTF_MASK) >> ENET_DMA_OP_MODE_FTF_SHIFT) - -/* - * TTC (RW) - * - * Transmit Threshold Control - * These bits control the threshold level of the MTL Transmit FIFO. - * Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. - * In addition, full frames with a length less than the threshold are also transmitted. - * These bits are used only when Bit 21 (TSF) is reset. - * - 000: 64 - * - 001: 128 - * - 010: 192 - * - 011: 256 - * - 100: 40 - * - 101: 32 - * - 110: 24 - * - 111: 16 - */ -#define ENET_DMA_OP_MODE_TTC_MASK (0x1C000UL) -#define ENET_DMA_OP_MODE_TTC_SHIFT (14U) -#define ENET_DMA_OP_MODE_TTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TTC_SHIFT) & ENET_DMA_OP_MODE_TTC_MASK) -#define ENET_DMA_OP_MODE_TTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TTC_MASK) >> ENET_DMA_OP_MODE_TTC_SHIFT) - -/* - * ST (RW) - * - * Start or Stop Transmission Command - * When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. - * Descriptor acquisition is attempted either from the current position in the list, - * which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), - * or from the position retained when transmission was stopped previously. - * If the DMA does not own the current descriptor, - * transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Transmission command is effective only when transmission is stopped. - * If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - * then the DMA behavior is unpredictable. When this bit is reset, - * the transmission process is placed in the Stopped state after completing the transmission of the current frame. - * The Next Descriptor position in the Transmit List is saved, - * and it becomes the current position when transmission is restarted. - * To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. - * The new value is considered when this bit is set again. - * The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - */ -#define ENET_DMA_OP_MODE_ST_MASK (0x2000U) -#define ENET_DMA_OP_MODE_ST_SHIFT (13U) -#define ENET_DMA_OP_MODE_ST_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_ST_SHIFT) & ENET_DMA_OP_MODE_ST_MASK) -#define ENET_DMA_OP_MODE_ST_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_ST_MASK) >> ENET_DMA_OP_MODE_ST_SHIFT) - -/* - * RFD (RW) - * - * Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. - * - 00: Full minus 1 KB, that is, FULL — 1 KB - * - 01: Full minus 2 KB, that is, FULL — 2 KB - * - 10: Full minus 3 KB, that is, FULL — 3 KB - * - 11: Full minus 4 KB, that is, FULL — 4 KB - * The de-assertion is effective only after flow control is asserted. - * If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. - * These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_RFD_MASK (0x1800U) -#define ENET_DMA_OP_MODE_RFD_SHIFT (11U) -#define ENET_DMA_OP_MODE_RFD_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_SHIFT) & ENET_DMA_OP_MODE_RFD_MASK) -#define ENET_DMA_OP_MODE_RFD_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_MASK) >> ENET_DMA_OP_MODE_RFD_SHIFT) - -/* - * RFA (RW) - * - * Threshold for Activating Flow Control (in half-duplex and full-duplex modes) - * These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. - * - 00: Full minus 1 KB, that is, FULL—1KB. - * - 01: Full minus 2 KB, that is, FULL—2KB. - * - 10: Full minus 3 KB, that is, FULL—3KB. - * - 11: Full minus 4 KB, that is, FULL—4KB. - * These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, - * an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. - * These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. - * Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, - * the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - */ -#define ENET_DMA_OP_MODE_RFA_MASK (0x600U) -#define ENET_DMA_OP_MODE_RFA_SHIFT (9U) -#define ENET_DMA_OP_MODE_RFA_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_SHIFT) & ENET_DMA_OP_MODE_RFA_MASK) -#define ENET_DMA_OP_MODE_RFA_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_MASK) >> ENET_DMA_OP_MODE_RFA_SHIFT) - -/* - * EFC (RW) - * - * Enable HW Flow Control - * When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. - * When reset, the flow control operation is disabled. - * This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_EFC_MASK (0x100U) -#define ENET_DMA_OP_MODE_EFC_SHIFT (8U) -#define ENET_DMA_OP_MODE_EFC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_EFC_SHIFT) & ENET_DMA_OP_MODE_EFC_MASK) -#define ENET_DMA_OP_MODE_EFC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_EFC_MASK) >> ENET_DMA_OP_MODE_EFC_SHIFT) - -/* - * FEF (RW) - * - * Forward Error Frames - * When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). - * However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), - * then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, - * the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. - * When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. - * If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, - * then the frame is dropped irrespective of the FEF bit setting. - * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. - * Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - * - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - * - The advanced timestamp feature is not selected but the extended status is selected. - * The extended status is available with the following features: - * - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - * - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - */ -#define ENET_DMA_OP_MODE_FEF_MASK (0x80U) -#define ENET_DMA_OP_MODE_FEF_SHIFT (7U) -#define ENET_DMA_OP_MODE_FEF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FEF_SHIFT) & ENET_DMA_OP_MODE_FEF_MASK) -#define ENET_DMA_OP_MODE_FEF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FEF_MASK) >> ENET_DMA_OP_MODE_FEF_SHIFT) - -/* - * FUF (RW) - * - * Forward Undersized Good Frames - * When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC - * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - */ -#define ENET_DMA_OP_MODE_FUF_MASK (0x40U) -#define ENET_DMA_OP_MODE_FUF_SHIFT (6U) -#define ENET_DMA_OP_MODE_FUF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FUF_SHIFT) & ENET_DMA_OP_MODE_FUF_MASK) -#define ENET_DMA_OP_MODE_FUF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FUF_MASK) >> ENET_DMA_OP_MODE_FUF_SHIFT) - -/* - * DGF (RW) - * - * Drop Giant Frames - * When set, the MAC drops the received giant frames in the Rx FIFO, - * that is, frames that are larger than the computed giant frame limit. - * When reset, the MAC does not drop the giant frames in the Rx FIFO. - * Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - * - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - * - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - * - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - */ -#define ENET_DMA_OP_MODE_DGF_MASK (0x20U) -#define ENET_DMA_OP_MODE_DGF_SHIFT (5U) -#define ENET_DMA_OP_MODE_DGF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DGF_SHIFT) & ENET_DMA_OP_MODE_DGF_MASK) -#define ENET_DMA_OP_MODE_DGF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DGF_MASK) >> ENET_DMA_OP_MODE_DGF_SHIFT) - -/* - * RTC (RW) - * - * Receive Threshold Control - * These two bits control the threshold level of the MTL Receive FIFO. - * Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. - * In addition, full frames with length less than the threshold are automatically transferred. - * The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. - * These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. - * - 00: 64 - * - 01: 32 - * - 10: 96 - * - 11: 128 - */ -#define ENET_DMA_OP_MODE_RTC_MASK (0x18U) -#define ENET_DMA_OP_MODE_RTC_SHIFT (3U) -#define ENET_DMA_OP_MODE_RTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RTC_SHIFT) & ENET_DMA_OP_MODE_RTC_MASK) -#define ENET_DMA_OP_MODE_RTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RTC_MASK) >> ENET_DMA_OP_MODE_RTC_SHIFT) - -/* - * OSF (RW) - * - * Operate on Second Frame - * When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - */ -#define ENET_DMA_OP_MODE_OSF_MASK (0x4U) -#define ENET_DMA_OP_MODE_OSF_SHIFT (2U) -#define ENET_DMA_OP_MODE_OSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_OSF_SHIFT) & ENET_DMA_OP_MODE_OSF_MASK) -#define ENET_DMA_OP_MODE_OSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_OSF_MASK) >> ENET_DMA_OP_MODE_OSF_SHIFT) - -/* - * SR (RW) - * - * Start or Stop Receive - * When this bit is set, the Receive process is placed in the Running state. - * The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. - * The descriptor acquisition is attempted from the current position in the list, - * which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. - * If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Receive command is effective only when the reception has stopped. - * If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. - * When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. - * The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. - * The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - */ -#define ENET_DMA_OP_MODE_SR_MASK (0x2U) -#define ENET_DMA_OP_MODE_SR_SHIFT (1U) -#define ENET_DMA_OP_MODE_SR_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_SR_SHIFT) & ENET_DMA_OP_MODE_SR_MASK) -#define ENET_DMA_OP_MODE_SR_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_SR_MASK) >> ENET_DMA_OP_MODE_SR_SHIFT) - -/* Bitfield definition for register: DMA_INTR_EN */ -/* - * NIE (RW) - * - * Normal Interrupt Summary Enable - * When this bit is set, normal interrupt summary is enabled. - * When this bit is reset, normal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt - */ -#define ENET_DMA_INTR_EN_NIE_MASK (0x10000UL) -#define ENET_DMA_INTR_EN_NIE_SHIFT (16U) -#define ENET_DMA_INTR_EN_NIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_NIE_SHIFT) & ENET_DMA_INTR_EN_NIE_MASK) -#define ENET_DMA_INTR_EN_NIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_NIE_MASK) >> ENET_DMA_INTR_EN_NIE_SHIFT) - -/* - * AIE (RW) - * - * Abnormal Interrupt Summary Enable - * When this bit is set, abnormal interrupt summary is enabled. - * When this bit is reset, the abnormal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error - */ -#define ENET_DMA_INTR_EN_AIE_MASK (0x8000U) -#define ENET_DMA_INTR_EN_AIE_SHIFT (15U) -#define ENET_DMA_INTR_EN_AIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_AIE_SHIFT) & ENET_DMA_INTR_EN_AIE_MASK) -#define ENET_DMA_INTR_EN_AIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_AIE_MASK) >> ENET_DMA_INTR_EN_AIE_SHIFT) - -/* - * ERE (RW) - * - * Early Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ERE_MASK (0x4000U) -#define ENET_DMA_INTR_EN_ERE_SHIFT (14U) -#define ENET_DMA_INTR_EN_ERE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ERE_SHIFT) & ENET_DMA_INTR_EN_ERE_MASK) -#define ENET_DMA_INTR_EN_ERE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ERE_MASK) >> ENET_DMA_INTR_EN_ERE_SHIFT) - -/* - * FBE (RW) - * - * Fatal Bus Error Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_FBE_MASK (0x2000U) -#define ENET_DMA_INTR_EN_FBE_SHIFT (13U) -#define ENET_DMA_INTR_EN_FBE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_FBE_SHIFT) & ENET_DMA_INTR_EN_FBE_MASK) -#define ENET_DMA_INTR_EN_FBE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_FBE_MASK) >> ENET_DMA_INTR_EN_FBE_SHIFT) - -/* - * ETE (RW) - * - * Early Transmit Interrupt Enable - * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ETE_MASK (0x400U) -#define ENET_DMA_INTR_EN_ETE_SHIFT (10U) -#define ENET_DMA_INTR_EN_ETE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ETE_SHIFT) & ENET_DMA_INTR_EN_ETE_MASK) -#define ENET_DMA_INTR_EN_ETE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ETE_MASK) >> ENET_DMA_INTR_EN_ETE_SHIFT) - -/* - * RWE (RW) - * - * Receive Watchdog Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RWE_MASK (0x200U) -#define ENET_DMA_INTR_EN_RWE_SHIFT (9U) -#define ENET_DMA_INTR_EN_RWE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RWE_SHIFT) & ENET_DMA_INTR_EN_RWE_MASK) -#define ENET_DMA_INTR_EN_RWE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RWE_MASK) >> ENET_DMA_INTR_EN_RWE_SHIFT) - -/* - * RSE (RW) - * - * Receive Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RSE_MASK (0x100U) -#define ENET_DMA_INTR_EN_RSE_SHIFT (8U) -#define ENET_DMA_INTR_EN_RSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RSE_SHIFT) & ENET_DMA_INTR_EN_RSE_MASK) -#define ENET_DMA_INTR_EN_RSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RSE_MASK) >> ENET_DMA_INTR_EN_RSE_SHIFT) - -/* - * RUE (RW) - * - * Receive Buffer Unavailable Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RUE_MASK (0x80U) -#define ENET_DMA_INTR_EN_RUE_SHIFT (7U) -#define ENET_DMA_INTR_EN_RUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RUE_SHIFT) & ENET_DMA_INTR_EN_RUE_MASK) -#define ENET_DMA_INTR_EN_RUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RUE_MASK) >> ENET_DMA_INTR_EN_RUE_SHIFT) - -/* - * RIE (RW) - * - * Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RIE_MASK (0x40U) -#define ENET_DMA_INTR_EN_RIE_SHIFT (6U) -#define ENET_DMA_INTR_EN_RIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RIE_SHIFT) & ENET_DMA_INTR_EN_RIE_MASK) -#define ENET_DMA_INTR_EN_RIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RIE_MASK) >> ENET_DMA_INTR_EN_RIE_SHIFT) - -/* - * UNE (RW) - * - * Underflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_UNE_MASK (0x20U) -#define ENET_DMA_INTR_EN_UNE_SHIFT (5U) -#define ENET_DMA_INTR_EN_UNE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_UNE_SHIFT) & ENET_DMA_INTR_EN_UNE_MASK) -#define ENET_DMA_INTR_EN_UNE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_UNE_MASK) >> ENET_DMA_INTR_EN_UNE_SHIFT) - -/* - * OVE (RW) - * - * Overflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_OVE_MASK (0x10U) -#define ENET_DMA_INTR_EN_OVE_SHIFT (4U) -#define ENET_DMA_INTR_EN_OVE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_OVE_SHIFT) & ENET_DMA_INTR_EN_OVE_MASK) -#define ENET_DMA_INTR_EN_OVE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_OVE_MASK) >> ENET_DMA_INTR_EN_OVE_SHIFT) - -/* - * TJE (RW) - * - * Transmit Jabber Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TJE_MASK (0x8U) -#define ENET_DMA_INTR_EN_TJE_SHIFT (3U) -#define ENET_DMA_INTR_EN_TJE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TJE_SHIFT) & ENET_DMA_INTR_EN_TJE_MASK) -#define ENET_DMA_INTR_EN_TJE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TJE_MASK) >> ENET_DMA_INTR_EN_TJE_SHIFT) - -/* - * TUE (RW) - * - * Transmit Buffer Unavailable Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TUE_MASK (0x4U) -#define ENET_DMA_INTR_EN_TUE_SHIFT (2U) -#define ENET_DMA_INTR_EN_TUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TUE_SHIFT) & ENET_DMA_INTR_EN_TUE_MASK) -#define ENET_DMA_INTR_EN_TUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TUE_MASK) >> ENET_DMA_INTR_EN_TUE_SHIFT) - -/* - * TSE (RW) - * - * Transmit Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TSE_MASK (0x2U) -#define ENET_DMA_INTR_EN_TSE_SHIFT (1U) -#define ENET_DMA_INTR_EN_TSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TSE_SHIFT) & ENET_DMA_INTR_EN_TSE_MASK) -#define ENET_DMA_INTR_EN_TSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TSE_MASK) >> ENET_DMA_INTR_EN_TSE_SHIFT) - -/* - * TIE (RW) - * - * Transmit Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TIE_MASK (0x1U) -#define ENET_DMA_INTR_EN_TIE_SHIFT (0U) -#define ENET_DMA_INTR_EN_TIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TIE_SHIFT) & ENET_DMA_INTR_EN_TIE_MASK) -#define ENET_DMA_INTR_EN_TIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TIE_MASK) >> ENET_DMA_INTR_EN_TIE_SHIFT) - -/* Bitfield definition for register: DMA_MISS_OVF_CNT */ -/* - * ONFCNTOVF (RW) - * - * Overflow Bit for FIFO Overflow Counter - * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, - * that is, the Rx FIFO overflows with the overflow frame counter at maximum value. - * In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK (0x10000000UL) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT (28U) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) - -/* - * OVFFRMCNT (RW) - * - * Overflow Frame Counter - * This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK (0xFFE0000UL) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT (17U) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) - -/* - * MISCNTOVF (RW) - * - * Overflow Bit for Missed Frame Counter - * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, - * that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - * the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK (0x10000UL) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT (16U) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) - -/* - * MISFRMCNT (RW) - * - * Missed Frame Counter - * This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. - * This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK (0xFFFFU) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT (0U) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) - -/* Bitfield definition for register: DMA_RX_INTR_WDOG */ -/* - * RIWT (RW) - * - * RI Watchdog Timer Count - * This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. - * The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer - * of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. - * When the watchdog timer runs out, the RI bit is set and the timer is stopped. - * The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - */ -#define ENET_DMA_RX_INTR_WDOG_RIWT_MASK (0xFFU) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT (0U) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SET(x) (((uint32_t)(x) << ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) -#define ENET_DMA_RX_INTR_WDOG_RIWT_GET(x) (((uint32_t)(x) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) >> ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) - -/* Bitfield definition for register: DMA_AXI_MODE */ -/* - * EN_LPI (RW) - * - * Enable Low Power Interface (LPI) - * When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. - * When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - */ -#define ENET_DMA_AXI_MODE_EN_LPI_MASK (0x80000000UL) -#define ENET_DMA_AXI_MODE_EN_LPI_SHIFT (31U) -#define ENET_DMA_AXI_MODE_EN_LPI_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_EN_LPI_SHIFT) & ENET_DMA_AXI_MODE_EN_LPI_MASK) -#define ENET_DMA_AXI_MODE_EN_LPI_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_EN_LPI_MASK) >> ENET_DMA_AXI_MODE_EN_LPI_SHIFT) - -/* - * LPI_XIT_FRM (RW) - * - * Unlock on Magic Packet or Remote Wake-Up Frame - * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. - * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - */ -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK (0x40000000UL) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT (30U) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) >> ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) - -/* - * WR_OSR_LMT (RW) - * - * AXI Maximum Write Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI write interface. - * Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK (0xF00000UL) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT (20U) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) - -/* - * RD_OSR_LMT (RW) - * - * AXI Maximum Read Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI read interface. - * Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK (0xF0000UL) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT (16U) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) - -/* - * ONEKBBE (RW) - * - * 1 KB Boundary Crossing Enable for the GMAC-AXI Master - * When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. - * When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - */ -#define ENET_DMA_AXI_MODE_ONEKBBE_MASK (0x2000U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SHIFT (13U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) -#define ENET_DMA_AXI_MODE_ONEKBBE_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) >> ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) - -/* - * AXI_AAL (RW) - * - * Address-Aligned Beats - * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). - * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - */ -#define ENET_DMA_AXI_MODE_AXI_AAL_MASK (0x1000U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SHIFT (12U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) -#define ENET_DMA_AXI_MODE_AXI_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) >> ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) - -/* - * BLEN256 (RW) - * - * AXI Burst Length 256 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN256_MASK (0x80U) -#define ENET_DMA_AXI_MODE_BLEN256_SHIFT (7U) -#define ENET_DMA_AXI_MODE_BLEN256_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN256_SHIFT) & ENET_DMA_AXI_MODE_BLEN256_MASK) -#define ENET_DMA_AXI_MODE_BLEN256_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN256_MASK) >> ENET_DMA_AXI_MODE_BLEN256_SHIFT) - -/* - * BLEN128 (RW) - * - * AXI Burst Length 128 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN128_MASK (0x40U) -#define ENET_DMA_AXI_MODE_BLEN128_SHIFT (6U) -#define ENET_DMA_AXI_MODE_BLEN128_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN128_SHIFT) & ENET_DMA_AXI_MODE_BLEN128_MASK) -#define ENET_DMA_AXI_MODE_BLEN128_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN128_MASK) >> ENET_DMA_AXI_MODE_BLEN128_SHIFT) - -/* - * BLEN64 (RW) - * - * AXI Burst Length 64 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN64_MASK (0x20U) -#define ENET_DMA_AXI_MODE_BLEN64_SHIFT (5U) -#define ENET_DMA_AXI_MODE_BLEN64_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN64_SHIFT) & ENET_DMA_AXI_MODE_BLEN64_MASK) -#define ENET_DMA_AXI_MODE_BLEN64_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN64_MASK) >> ENET_DMA_AXI_MODE_BLEN64_SHIFT) - -/* - * BLEN32 (RW) - * - * AXI Burst Length 32 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN32_MASK (0x10U) -#define ENET_DMA_AXI_MODE_BLEN32_SHIFT (4U) -#define ENET_DMA_AXI_MODE_BLEN32_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN32_SHIFT) & ENET_DMA_AXI_MODE_BLEN32_MASK) -#define ENET_DMA_AXI_MODE_BLEN32_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN32_MASK) >> ENET_DMA_AXI_MODE_BLEN32_SHIFT) - -/* - * BLEN16 (RW) - * - * AXI Burst Length 16 - * When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - */ -#define ENET_DMA_AXI_MODE_BLEN16_MASK (0x8U) -#define ENET_DMA_AXI_MODE_BLEN16_SHIFT (3U) -#define ENET_DMA_AXI_MODE_BLEN16_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN16_SHIFT) & ENET_DMA_AXI_MODE_BLEN16_MASK) -#define ENET_DMA_AXI_MODE_BLEN16_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN16_MASK) >> ENET_DMA_AXI_MODE_BLEN16_SHIFT) - -/* - * BLEN8 (RW) - * - * AXI Burst Length 8 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN8_MASK (0x4U) -#define ENET_DMA_AXI_MODE_BLEN8_SHIFT (2U) -#define ENET_DMA_AXI_MODE_BLEN8_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN8_SHIFT) & ENET_DMA_AXI_MODE_BLEN8_MASK) -#define ENET_DMA_AXI_MODE_BLEN8_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN8_MASK) >> ENET_DMA_AXI_MODE_BLEN8_SHIFT) - -/* - * BLEN4 (RW) - * - * AXI Burst Length 4 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN4_MASK (0x2U) -#define ENET_DMA_AXI_MODE_BLEN4_SHIFT (1U) -#define ENET_DMA_AXI_MODE_BLEN4_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN4_SHIFT) & ENET_DMA_AXI_MODE_BLEN4_MASK) -#define ENET_DMA_AXI_MODE_BLEN4_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN4_MASK) >> ENET_DMA_AXI_MODE_BLEN4_SHIFT) - -/* - * UNDEF (RW) - * - * AXI Undefined Burst Length - * This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - * - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - * - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. - * If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - */ -#define ENET_DMA_AXI_MODE_UNDEF_MASK (0x1U) -#define ENET_DMA_AXI_MODE_UNDEF_SHIFT (0U) -#define ENET_DMA_AXI_MODE_UNDEF_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_UNDEF_SHIFT) & ENET_DMA_AXI_MODE_UNDEF_MASK) -#define ENET_DMA_AXI_MODE_UNDEF_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_UNDEF_MASK) >> ENET_DMA_AXI_MODE_UNDEF_SHIFT) - -/* Bitfield definition for register: DMA_BUS_STATUS */ -/* - * AXIRDSTS (RW) - * - * AXI Master Read Channel Status - * When high, it indicates that AXI master's read channel is active and transferring data. - */ -#define ENET_DMA_BUS_STATUS_AXIRDSTS_MASK (0x2U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT (1U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) >> ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) - -/* - * AXWHSTS (RW) - * - * AXI Master Write Channel or AHB Master Status - * When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - * it indicates that the AHB master interface FSMs are in the non-idle state. - */ -#define ENET_DMA_BUS_STATUS_AXWHSTS_MASK (0x1U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT (0U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXWHSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) >> ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_DESC */ -/* - * CURTDESAPTR (RW) - * - * Host Transmit Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_DESC */ -/* - * CURRDESAPTR (RW) - * - * Host Receive Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_BUF */ -/* - * CURTBUFAPTR (RW) - * - * Host Transmit Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_BUF */ -/* - * CURRBUFAPTR (RW) - * - * Host Receive Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) - -/* Bitfield definition for register: CTRL0 */ -/* - * ENET0_RXCLK_DLY_SEL (RW) - * - */ -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3F00U) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (8U) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) - -/* - * ENET0_TXCLK_DLY_SEL (RW) - * - */ -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x3FU) -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) - -/* Bitfield definition for register: CTRL2 */ -/* - * ENET0_LPI_IRQ_EN (RW) - * - * lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt - */ -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) - -/* - * ENET0_REFCLK_OE (RW) - * - * set to enable output 50MHz clock to rmii phy. - * User should set it if use soc internal clock as refclk - */ -#define ENET_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) -#define ENET_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) -#define ENET_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) -#define ENET_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) >> ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) - -/* - * ENET0_PHY_INF_SEL (RW) - * - * PHY mode select - * 001RGMII; 100RMII; - * should be set before config IOMUX, otherwise may cause glitch for RGMII - */ -#define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK (0xE000U) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT (13U) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) >> ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) - -/* - * ENET0_FLOWCTRL (RW) - * - * flow control request - */ -#define ENET_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) -#define ENET_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) -#define ENET_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) -#define ENET_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) >> ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) - -/* - * ENET0_RMII_TXCLK_SEL (RW) - * - * RMII mode output clock pad select - * set to use txck as RMII refclk; - * clr to use rxck as RMII refclk; default 0(rxck) - * refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. - */ -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) - - - -/* MAC_ADDR register group index macro definition */ -#define ENET_MAC_ADDR_1 (0UL) -#define ENET_MAC_ADDR_2 (1UL) -#define ENET_MAC_ADDR_3 (2UL) -#define ENET_MAC_ADDR_4 (3UL) - -/* L3_L4_CFG register group index macro definition */ -#define ENET_L3_L4_CFG_0 (0UL) - -/* PPS register group index macro definition */ -#define ENET_PPS_1 (0UL) -#define ENET_PPS_2 (1UL) -#define ENET_PPS_3 (2UL) - - -#endif /* HPM_ENET_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ewdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ewdg_regs.h deleted file mode 100644 index 6716877a361..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ewdg_regs.h +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_EWDG_H -#define HPM_EWDG_H - -typedef struct { - __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ - __RW uint32_t CTRL1; /* 0x4: wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t OT_RST_VAL; /* 0xC: wdog timeout reset counter value */ - __W uint32_t WDT_REFRESH_REG; /* 0x10: wdog refresh register */ - __W uint32_t WDT_STATUS; /* 0x14: wdog status register */ - __RW uint32_t CFG_PROT; /* 0x18: ctrl register protection register */ - __RW uint32_t REF_PROT; /* 0x1C: refresh protection register */ - __RW uint32_t WDT_EN; /* 0x20: Wdog enable */ - __RW uint32_t REF_TIME; /* 0x24: Refresh period value */ -} EWDG_Type; - - -/* Bitfield definition for register: CTRL0 */ -/* - * CLK_SEL (RW) - * - * clock select - * 0：bus clock - * 1：ext clock - */ -#define EWDG_CTRL0_CLK_SEL_MASK (0x20000000UL) -#define EWDG_CTRL0_CLK_SEL_SHIFT (29U) -#define EWDG_CTRL0_CLK_SEL_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK) -#define EWDG_CTRL0_CLK_SEL_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT) - -/* - * DIV_VALUE (RW) - * - * clock divider, the clock divider works as 2 ^ div_value for wdt counter - */ -#define EWDG_CTRL0_DIV_VALUE_MASK (0xE000000UL) -#define EWDG_CTRL0_DIV_VALUE_SHIFT (25U) -#define EWDG_CTRL0_DIV_VALUE_SET(x) (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK) -#define EWDG_CTRL0_DIV_VALUE_GET(x) (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT) - -/* - * WIN_EN (RW) - * - * window mode enable - */ -#define EWDG_CTRL0_WIN_EN_MASK (0x1000000UL) -#define EWDG_CTRL0_WIN_EN_SHIFT (24U) -#define EWDG_CTRL0_WIN_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK) -#define EWDG_CTRL0_WIN_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT) - -/* - * WIN_LOWER (RW) - * - * Once window mode is opened, the lower counter value to refresh wdt - * 00: 4/8 overtime value - * 01: 5/8 of overtime value - * 10: 6/8 of overtime value - * 11: 7/8 of overtime value - */ -#define EWDG_CTRL0_WIN_LOWER_MASK (0xC00000UL) -#define EWDG_CTRL0_WIN_LOWER_SHIFT (22U) -#define EWDG_CTRL0_WIN_LOWER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK) -#define EWDG_CTRL0_WIN_LOWER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT) - -/* - * CFG_LOCK (RW) - * - * The register is locked and unlock is needed before re-config registers - * Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. - * The register update needs to be finished in the required period defined by UPD_OT_TIME register - */ -#define EWDG_CTRL0_CFG_LOCK_MASK (0x200000UL) -#define EWDG_CTRL0_CFG_LOCK_SHIFT (21U) -#define EWDG_CTRL0_CFG_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK) -#define EWDG_CTRL0_CFG_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT) - -/* - * OT_SELF_CLEAR (RW) - * - * overtime reset can be self released after 32 function cycles - */ -#define EWDG_CTRL0_OT_SELF_CLEAR_MASK (0x20000UL) -#define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT (17U) -#define EWDG_CTRL0_OT_SELF_CLEAR_SET(x) (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) -#define EWDG_CTRL0_OT_SELF_CLEAR_GET(x) (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) - -/* - * REF_OT_REQ (RW) - * - * If refresh event has to be limited into a period after refresh unlocked. - * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - */ -#define EWDG_CTRL0_REF_OT_REQ_MASK (0x8000U) -#define EWDG_CTRL0_REF_OT_REQ_SHIFT (15U) -#define EWDG_CTRL0_REF_OT_REQ_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK) -#define EWDG_CTRL0_REF_OT_REQ_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT) - -/* - * WIN_UPPER (RW) - * - * The upper threshold of window value - * The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value - * If this register value is zero, then no upper level limitation - */ -#define EWDG_CTRL0_WIN_UPPER_MASK (0x7000U) -#define EWDG_CTRL0_WIN_UPPER_SHIFT (12U) -#define EWDG_CTRL0_WIN_UPPER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK) -#define EWDG_CTRL0_WIN_UPPER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT) - -/* - * REF_LOCK (RW) - * - * WDT refresh has to be unlocked firstly once refresh lock is enable. - */ -#define EWDG_CTRL0_REF_LOCK_MASK (0x20U) -#define EWDG_CTRL0_REF_LOCK_SHIFT (5U) -#define EWDG_CTRL0_REF_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK) -#define EWDG_CTRL0_REF_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT) - -/* - * REF_UNLOCK_MEC (RW) - * - * Unlock refresh mechanism - * 00: the required unlock password is the same with refresh_psd_register - * 01: the required unlock password is a ring shift left value of refresh_psd_register - * 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is - * 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - */ -#define EWDG_CTRL0_REF_UNLOCK_MEC_MASK (0x18U) -#define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT (3U) -#define EWDG_CTRL0_REF_UNLOCK_MEC_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) -#define EWDG_CTRL0_REF_UNLOCK_MEC_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) - -/* - * EN_DBG (RW) - * - * WTD enable or not in debug mode - */ -#define EWDG_CTRL0_EN_DBG_MASK (0x4U) -#define EWDG_CTRL0_EN_DBG_SHIFT (2U) -#define EWDG_CTRL0_EN_DBG_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK) -#define EWDG_CTRL0_EN_DBG_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT) - -/* - * EN_LP (RW) - * - * WDT enable or not in low power mode - * 2'b00: wdt is halted once in low power mode - * 2'b01: wdt will work with 1/4 normal clock freq in low power mode - * 2'b10: wdt will work with 1/2 normal clock freq in low power mode - * 2'b11: wdt will work with normal clock freq in low power mode - */ -#define EWDG_CTRL0_EN_LP_MASK (0x3U) -#define EWDG_CTRL0_EN_LP_SHIFT (0U) -#define EWDG_CTRL0_EN_LP_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK) -#define EWDG_CTRL0_EN_LP_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT) - -/* Bitfield definition for register: CTRL1 */ -/* - * REF_FAIL_RST_EN (RW) - * - * Refresh violation will trigger an reset. - * These event will be taken as a refresh violation: - * 1) Not refresh in the window once window mode is enabled - * 2) Not unlock refresh firstly if unlock is required - * 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. - * 4) Not write the required word to refresh wdt. - */ -#define EWDG_CTRL1_REF_FAIL_RST_EN_MASK (0x800000UL) -#define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT (23U) -#define EWDG_CTRL1_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) - -/* - * REF_FAIL_INT_EN (RW) - * - * Refresh violation will trigger an interrupt - */ -#define EWDG_CTRL1_REF_FAIL_INT_EN_MASK (0x400000UL) -#define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT (22U) -#define EWDG_CTRL1_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) - -/* - * UNL_REF_FAIL_RST_EN (RW) - * - * Refresh unlock fail will trigger a reset - */ -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK (0x200000UL) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT (21U) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) - -/* - * UNL_REF_FAIL_INT_EN (RW) - * - * Refresh unlock fail will trigger a interrupt - */ -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK (0x100000UL) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT (20U) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) - -/* - * OT_RST_EN (RW) - * - * WDT overtime will generate a reset - */ -#define EWDG_CTRL1_OT_RST_EN_MASK (0x20000UL) -#define EWDG_CTRL1_OT_RST_EN_SHIFT (17U) -#define EWDG_CTRL1_OT_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK) -#define EWDG_CTRL1_OT_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT) - -/* - * CTL_VIO_RST_EN (RW) - * - * Ctrl update violation will trigger a reset - * The violation event is to try updating the locked register before unlock them - */ -#define EWDG_CTRL1_CTL_VIO_RST_EN_MASK (0x80U) -#define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT (7U) -#define EWDG_CTRL1_CTL_VIO_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) -#define EWDG_CTRL1_CTL_VIO_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) - -/* - * CTL_VIO_INT_EN (RW) - * - * Ctrl update violation will trigger a interrupt - */ -#define EWDG_CTRL1_CTL_VIO_INT_EN_MASK (0x40U) -#define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT (6U) -#define EWDG_CTRL1_CTL_VIO_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) -#define EWDG_CTRL1_CTL_VIO_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) - -/* - * UNL_CTL_FAIL_RST_EN (RW) - * - * Unlock register update failure will trigger a reset - */ -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK (0x20U) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT (5U) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) - -/* - * UNL_CTL_FAIL_INT_EN (RW) - * - * Unlock register update failure will trigger a interrupt - */ -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK (0x10U) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT (4U) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) - -/* - * PARITY_FAIL_RST_EN (RW) - * - * Parity error will trigger a reset - * A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - */ -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK (0x8U) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT (3U) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) - -/* - * PARITY_FAIL_INT_EN (RW) - * - * Parity error will trigger a interrupt - */ -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK (0x4U) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT (2U) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) - -/* Bitfield definition for register: OT_RST_VAL */ -/* - * OT_RST_VAL (RW) - * - * WDT timeout reset value - */ -#define EWDG_OT_RST_VAL_OT_RST_VAL_MASK (0xFFFFU) -#define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT (0U) -#define EWDG_OT_RST_VAL_OT_RST_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) -#define EWDG_OT_RST_VAL_OT_RST_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) - -/* Bitfield definition for register: WDT_REFRESH_REG */ -/* - * WDT_REFRESH_REG (WO) - * - * Write this register by 32'h5A45_524F to refresh wdog - * Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - */ -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK (0xFFFFFFFFUL) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT (0U) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x) (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x) (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) - -/* Bitfield definition for register: WDT_STATUS */ -/* - * PARITY_ERROR (W1C) - * - * parity error - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_PARITY_ERROR_MASK (0x40U) -#define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT (6U) -#define EWDG_WDT_STATUS_PARITY_ERROR_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) -#define EWDG_WDT_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) - -/* - * OT_RST (W1C) - * - * Timeout happens, a reset will happen once enable bit set - * This bit can be cleared only by refreshing wdt or reset - */ -#define EWDG_WDT_STATUS_OT_RST_MASK (0x20U) -#define EWDG_WDT_STATUS_OT_RST_SHIFT (5U) -#define EWDG_WDT_STATUS_OT_RST_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_OT_RST_SHIFT) & EWDG_WDT_STATUS_OT_RST_MASK) -#define EWDG_WDT_STATUS_OT_RST_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT) - -/* - * CTL_UNL_FAIL (W1C) - * - * Unlock ctrl reg update protection fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK (0x8U) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT (3U) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) - -/* - * CTL_VIO (W1C) - * - * Violate register update protection mechanism - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_CTL_VIO_MASK (0x4U) -#define EWDG_WDT_STATUS_CTL_VIO_SHIFT (2U) -#define EWDG_WDT_STATUS_CTL_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK) -#define EWDG_WDT_STATUS_CTL_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT) - -/* - * REF_UNL_FAIL (W1C) - * - * Refresh unlock fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK (0x2U) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT (1U) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) - -/* - * REF_VIO (W1C) - * - * Refresh fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_REF_VIO_MASK (0x1U) -#define EWDG_WDT_STATUS_REF_VIO_SHIFT (0U) -#define EWDG_WDT_STATUS_REF_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK) -#define EWDG_WDT_STATUS_REF_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT) - -/* Bitfield definition for register: CFG_PROT */ -/* - * UPD_OT_TIME (RW) - * - * The period in which register update has to be in after unlock - * The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - */ -#define EWDG_CFG_PROT_UPD_OT_TIME_MASK (0xF0000UL) -#define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT (16U) -#define EWDG_CFG_PROT_UPD_OT_TIME_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) -#define EWDG_CFG_PROT_UPD_OT_TIME_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) - -/* - * UPD_PSD (RW) - * - * The password of unlocking register update - */ -#define EWDG_CFG_PROT_UPD_PSD_MASK (0xFFFFU) -#define EWDG_CFG_PROT_UPD_PSD_SHIFT (0U) -#define EWDG_CFG_PROT_UPD_PSD_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK) -#define EWDG_CFG_PROT_UPD_PSD_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT) - -/* Bitfield definition for register: REF_PROT */ -/* - * REF_UNL_PSD (RW) - * - * The password to unlock refreshing - */ -#define EWDG_REF_PROT_REF_UNL_PSD_MASK (0xFFFFU) -#define EWDG_REF_PROT_REF_UNL_PSD_SHIFT (0U) -#define EWDG_REF_PROT_REF_UNL_PSD_SET(x) (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK) -#define EWDG_REF_PROT_REF_UNL_PSD_GET(x) (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT) - -/* Bitfield definition for register: WDT_EN */ -/* - * WDOG_EN (RW) - * - * Wdog is enabled, the re-written of this register is impacted by enable lock function - */ -#define EWDG_WDT_EN_WDOG_EN_MASK (0x1U) -#define EWDG_WDT_EN_WDOG_EN_SHIFT (0U) -#define EWDG_WDT_EN_WDOG_EN_SET(x) (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK) -#define EWDG_WDT_EN_WDOG_EN_GET(x) (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT) - -/* Bitfield definition for register: REF_TIME */ -/* - * REFRESH_PERIOD (RW) - * - * The refresh period after refresh unlocked - * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - */ -#define EWDG_REF_TIME_REFRESH_PERIOD_MASK (0xFFFFU) -#define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT (0U) -#define EWDG_REF_TIME_REFRESH_PERIOD_SET(x) (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) -#define EWDG_REF_TIME_REFRESH_PERIOD_GET(x) (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) - - - - -#endif /* HPM_EWDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ffa_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ffa_regs.h deleted file mode 100644 index 432aab85c2c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ffa_regs.h +++ /dev/null @@ -1,570 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_FFA_H -#define HPM_FFA_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: */ - __RW uint32_t STATUS; /* 0x4: */ - __RW uint32_t INT_EN; /* 0x8: */ - __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ - __RW uint32_t OP_CTRL; /* 0x20: */ - __RW uint32_t OP_CMD; /* 0x24: */ - union { - __RW uint32_t OP_REG0; /* 0x28: */ - __RW uint32_t OP_FIR_MISC; /* 0x28: */ - __RW uint32_t OP_FFT_MISC; /* 0x28: */ - }; - union { - __RW uint32_t OP_REG1; /* 0x2C: */ - __RW uint32_t OP_FIR_MISC1; /* 0x2C: */ - }; - union { - __RW uint32_t OP_REG2; /* 0x30: */ - __RW uint32_t OP_FFT_INRBUF; /* 0x30: */ - }; - union { - __RW uint32_t OP_REG3; /* 0x34: */ - __RW uint32_t OP_FIR_INBUF; /* 0x34: */ - }; - union { - __RW uint32_t OP_REG4; /* 0x38: */ - __RW uint32_t OP_FIR_COEFBUF; /* 0x38: */ - __RW uint32_t OP_FFT_OUTRBUF; /* 0x38: */ - }; - union { - __RW uint32_t OP_REG5; /* 0x3C: */ - __RW uint32_t OP_FIR_OUTBUF; /* 0x3C: */ - }; - __RW uint32_t OP_REG6; /* 0x40: */ - __RW uint32_t OP_REG7; /* 0x44: */ -} FFA_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module if asserted to be 1. - * EN is only active after this bit is zero. - */ -#define FFA_CTRL_SFTRST_MASK (0x80000000UL) -#define FFA_CTRL_SFTRST_SHIFT (31U) -#define FFA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << FFA_CTRL_SFTRST_SHIFT) & FFA_CTRL_SFTRST_MASK) -#define FFA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & FFA_CTRL_SFTRST_MASK) >> FFA_CTRL_SFTRST_SHIFT) - -/* - * EN (RW) - * - * Asserted to enable the module - */ -#define FFA_CTRL_EN_MASK (0x1U) -#define FFA_CTRL_EN_SHIFT (0U) -#define FFA_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_CTRL_EN_SHIFT) & FFA_CTRL_EN_MASK) -#define FFA_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_CTRL_EN_MASK) >> FFA_CTRL_EN_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * FIR_OV (W1C) - * - * FIR Overflow err - */ -#define FFA_STATUS_FIR_OV_MASK (0x80U) -#define FFA_STATUS_FIR_OV_SHIFT (7U) -#define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) -#define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) - -/* - * FFT_OV (W1C) - * - * FFT Overflow Err - */ -#define FFA_STATUS_FFT_OV_MASK (0x40U) -#define FFA_STATUS_FFT_OV_SHIFT (6U) -#define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) -#define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) - -/* - * WR_ERR (W1C) - * - * AXI Data Write Error - */ -#define FFA_STATUS_WR_ERR_MASK (0x20U) -#define FFA_STATUS_WR_ERR_SHIFT (5U) -#define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) -#define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) - -/* - * RD_NXT_ERR (W1C) - * - * AXI Read Bus Error for NXT DATA - */ -#define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) -#define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) -#define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) -#define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) - -/* - * RD_ERR (W1C) - * - * AXI Data Read Error - */ -#define FFA_STATUS_RD_ERR_MASK (0x8U) -#define FFA_STATUS_RD_ERR_SHIFT (3U) -#define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) -#define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) - -/* - * NXT_CMD_RD_DONE (W1C) - * - * Indicate that next command sequence is already read into the module. - */ -#define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) -#define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) -#define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) -#define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) - -/* - * OP_CMD_DONE (W1C) - * - * Indicate that operation cmd is done, and data are available in system memory. - */ -#define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) -#define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) -#define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) -#define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRSV1 (RW) - * - * Reserved - */ -#define FFA_INT_EN_WRSV1_MASK (0xFFFFFF00UL) -#define FFA_INT_EN_WRSV1_SHIFT (8U) -#define FFA_INT_EN_WRSV1_SET(x) (((uint32_t)(x) << FFA_INT_EN_WRSV1_SHIFT) & FFA_INT_EN_WRSV1_MASK) -#define FFA_INT_EN_WRSV1_GET(x) (((uint32_t)(x) & FFA_INT_EN_WRSV1_MASK) >> FFA_INT_EN_WRSV1_SHIFT) - -/* - * FIR_OV (RW) - * - * FIR Overflow err - */ -#define FFA_INT_EN_FIR_OV_MASK (0x80U) -#define FFA_INT_EN_FIR_OV_SHIFT (7U) -#define FFA_INT_EN_FIR_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FIR_OV_SHIFT) & FFA_INT_EN_FIR_OV_MASK) -#define FFA_INT_EN_FIR_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FIR_OV_MASK) >> FFA_INT_EN_FIR_OV_SHIFT) - -/* - * FFT_OV (RW) - * - * FFT Overflow Err - */ -#define FFA_INT_EN_FFT_OV_MASK (0x40U) -#define FFA_INT_EN_FFT_OV_SHIFT (6U) -#define FFA_INT_EN_FFT_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FFT_OV_SHIFT) & FFA_INT_EN_FFT_OV_MASK) -#define FFA_INT_EN_FFT_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FFT_OV_MASK) >> FFA_INT_EN_FFT_OV_SHIFT) - -/* - * WR_ERR (RW) - * - * Enable Data Write Error interrupt - */ -#define FFA_INT_EN_WR_ERR_MASK (0x20U) -#define FFA_INT_EN_WR_ERR_SHIFT (5U) -#define FFA_INT_EN_WR_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_WR_ERR_SHIFT) & FFA_INT_EN_WR_ERR_MASK) -#define FFA_INT_EN_WR_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_WR_ERR_MASK) >> FFA_INT_EN_WR_ERR_SHIFT) - -/* - * RD_NXT_ERR (RW) - * - * Enable Read Bus Error for NXT DATA interrupt - */ -#define FFA_INT_EN_RD_NXT_ERR_MASK (0x10U) -#define FFA_INT_EN_RD_NXT_ERR_SHIFT (4U) -#define FFA_INT_EN_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_NXT_ERR_SHIFT) & FFA_INT_EN_RD_NXT_ERR_MASK) -#define FFA_INT_EN_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_NXT_ERR_MASK) >> FFA_INT_EN_RD_NXT_ERR_SHIFT) - -/* - * RD_ERR (RW) - * - * Enable Data Read Error interrupt - */ -#define FFA_INT_EN_RD_ERR_MASK (0x8U) -#define FFA_INT_EN_RD_ERR_SHIFT (3U) -#define FFA_INT_EN_RD_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_ERR_SHIFT) & FFA_INT_EN_RD_ERR_MASK) -#define FFA_INT_EN_RD_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_ERR_MASK) >> FFA_INT_EN_RD_ERR_SHIFT) - -/* - * NXT_CMD_RD_DONE (RW) - * - * Indicate that next command sequence is already read into the module. - */ -#define FFA_INT_EN_NXT_CMD_RD_DONE_MASK (0x2U) -#define FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT (1U) -#define FFA_INT_EN_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) -#define FFA_INT_EN_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) >> FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) - -/* - * OP_CMD_DONE (RW) - * - * Indicate that operation cmd is done, and data are available in system memory. - */ -#define FFA_INT_EN_OP_CMD_DONE_MASK (0x1U) -#define FFA_INT_EN_OP_CMD_DONE_SHIFT (0U) -#define FFA_INT_EN_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_OP_CMD_DONE_SHIFT) & FFA_INT_EN_OP_CMD_DONE_MASK) -#define FFA_INT_EN_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_OP_CMD_DONE_MASK) >> FFA_INT_EN_OP_CMD_DONE_SHIFT) - -/* Bitfield definition for register: OP_CTRL */ -/* - * NXT_ADDR (RW) - * - * The address for the next command. - * It will be processed after CUR_CMD is executed and done.. - */ -#define FFA_OP_CTRL_NXT_ADDR_MASK (0xFFFFFFFCUL) -#define FFA_OP_CTRL_NXT_ADDR_SHIFT (2U) -#define FFA_OP_CTRL_NXT_ADDR_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_ADDR_SHIFT) & FFA_OP_CTRL_NXT_ADDR_MASK) -#define FFA_OP_CTRL_NXT_ADDR_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_ADDR_MASK) >> FFA_OP_CTRL_NXT_ADDR_SHIFT) - -/* - * NXT_EN (RW) - * - * Whether NXT_CMD is enabled. - * Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - */ -#define FFA_OP_CTRL_NXT_EN_MASK (0x2U) -#define FFA_OP_CTRL_NXT_EN_SHIFT (1U) -#define FFA_OP_CTRL_NXT_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_EN_SHIFT) & FFA_OP_CTRL_NXT_EN_MASK) -#define FFA_OP_CTRL_NXT_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_EN_MASK) >> FFA_OP_CTRL_NXT_EN_SHIFT) - -/* - * EN (RW) - * - * Whether CUR_CMD is enabled. - * Asserted to enable the CUR_CMD - */ -#define FFA_OP_CTRL_EN_MASK (0x1U) -#define FFA_OP_CTRL_EN_SHIFT (0U) -#define FFA_OP_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_EN_SHIFT) & FFA_OP_CTRL_EN_MASK) -#define FFA_OP_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_EN_MASK) >> FFA_OP_CTRL_EN_SHIFT) - -/* Bitfield definition for register: OP_CMD */ -/* - * CONJ_C (RW) - * - * asserted to have conjuate value for coefs in computation - */ -#define FFA_OP_CMD_CONJ_C_MASK (0x1000000UL) -#define FFA_OP_CMD_CONJ_C_SHIFT (24U) -#define FFA_OP_CMD_CONJ_C_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CONJ_C_SHIFT) & FFA_OP_CMD_CONJ_C_MASK) -#define FFA_OP_CMD_CONJ_C_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CONJ_C_MASK) >> FFA_OP_CMD_CONJ_C_SHIFT) - -/* - * CMD (RW) - * - * The Command Used: - * 0: FIR - * 2: FFT - * Others: Reserved - */ -#define FFA_OP_CMD_CMD_MASK (0xFC0000UL) -#define FFA_OP_CMD_CMD_SHIFT (18U) -#define FFA_OP_CMD_CMD_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CMD_SHIFT) & FFA_OP_CMD_CMD_MASK) -#define FFA_OP_CMD_CMD_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CMD_MASK) >> FFA_OP_CMD_CMD_SHIFT) - -/* - * OUTD_TYPE (RW) - * - * Output data type: - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_OUTD_TYPE_MASK (0x38000UL) -#define FFA_OP_CMD_OUTD_TYPE_SHIFT (15U) -#define FFA_OP_CMD_OUTD_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_OUTD_TYPE_SHIFT) & FFA_OP_CMD_OUTD_TYPE_MASK) -#define FFA_OP_CMD_OUTD_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_OUTD_TYPE_MASK) >> FFA_OP_CMD_OUTD_TYPE_SHIFT) - -/* - * COEF_TYPE (RW) - * - * Coef data type (used for FIR): - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_COEF_TYPE_MASK (0x7000U) -#define FFA_OP_CMD_COEF_TYPE_SHIFT (12U) -#define FFA_OP_CMD_COEF_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_COEF_TYPE_SHIFT) & FFA_OP_CMD_COEF_TYPE_MASK) -#define FFA_OP_CMD_COEF_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_COEF_TYPE_MASK) >> FFA_OP_CMD_COEF_TYPE_SHIFT) - -/* - * IND_TYPE (RW) - * - * Input data type: - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_IND_TYPE_MASK (0xE00U) -#define FFA_OP_CMD_IND_TYPE_SHIFT (9U) -#define FFA_OP_CMD_IND_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_IND_TYPE_SHIFT) & FFA_OP_CMD_IND_TYPE_MASK) -#define FFA_OP_CMD_IND_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_IND_TYPE_MASK) >> FFA_OP_CMD_IND_TYPE_SHIFT) - -/* - * NXT_CMD_LEN (RW) - * - * The length of nxt commands in 32-bit words - */ -#define FFA_OP_CMD_NXT_CMD_LEN_MASK (0xFFU) -#define FFA_OP_CMD_NXT_CMD_LEN_SHIFT (0U) -#define FFA_OP_CMD_NXT_CMD_LEN_SET(x) (((uint32_t)(x) << FFA_OP_CMD_NXT_CMD_LEN_SHIFT) & FFA_OP_CMD_NXT_CMD_LEN_MASK) -#define FFA_OP_CMD_NXT_CMD_LEN_GET(x) (((uint32_t)(x) & FFA_OP_CMD_NXT_CMD_LEN_MASK) >> FFA_OP_CMD_NXT_CMD_LEN_SHIFT) - -/* Bitfield definition for register: OP_REG0 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG0_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG0_CT_SHIFT (0U) -#define FFA_OP_REG0_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG0_CT_SHIFT) & FFA_OP_REG0_CT_MASK) -#define FFA_OP_REG0_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG0_CT_MASK) >> FFA_OP_REG0_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_MISC */ -/* - * FIR_COEF_TAPS (RW) - * - * Length of FIR coefs （max 256） - */ -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) >> FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) - -/* Bitfield definition for register: OP_FFT_MISC */ -/* - * FFT_LEN (RW) - * - * FFT length - * 0:8, - * ..., - * n:2^(3+n) - */ -#define FFA_OP_FFT_MISC_FFT_LEN_MASK (0x780U) -#define FFA_OP_FFT_MISC_FFT_LEN_SHIFT (7U) -#define FFA_OP_FFT_MISC_FFT_LEN_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_FFT_LEN_SHIFT) & FFA_OP_FFT_MISC_FFT_LEN_MASK) -#define FFA_OP_FFT_MISC_FFT_LEN_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_FFT_LEN_MASK) >> FFA_OP_FFT_MISC_FFT_LEN_SHIFT) - -/* - * IFFT (RW) - * - * Asserted to indicate IFFT - */ -#define FFA_OP_FFT_MISC_IFFT_MASK (0x40U) -#define FFA_OP_FFT_MISC_IFFT_SHIFT (6U) -#define FFA_OP_FFT_MISC_IFFT_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IFFT_SHIFT) & FFA_OP_FFT_MISC_IFFT_MASK) -#define FFA_OP_FFT_MISC_IFFT_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IFFT_MASK) >> FFA_OP_FFT_MISC_IFFT_SHIFT) - -/* - * TMP_BLK (RW) - * - * Memory block for indata. Should be assigned as 1 - */ -#define FFA_OP_FFT_MISC_TMP_BLK_MASK (0xCU) -#define FFA_OP_FFT_MISC_TMP_BLK_SHIFT (2U) -#define FFA_OP_FFT_MISC_TMP_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_TMP_BLK_SHIFT) & FFA_OP_FFT_MISC_TMP_BLK_MASK) -#define FFA_OP_FFT_MISC_TMP_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_TMP_BLK_MASK) >> FFA_OP_FFT_MISC_TMP_BLK_SHIFT) - -/* - * IND_BLK (RW) - * - * Memory block for indata. Should be assigned as 0 - */ -#define FFA_OP_FFT_MISC_IND_BLK_MASK (0x3U) -#define FFA_OP_FFT_MISC_IND_BLK_SHIFT (0U) -#define FFA_OP_FFT_MISC_IND_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IND_BLK_SHIFT) & FFA_OP_FFT_MISC_IND_BLK_MASK) -#define FFA_OP_FFT_MISC_IND_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IND_BLK_MASK) >> FFA_OP_FFT_MISC_IND_BLK_SHIFT) - -/* Bitfield definition for register: OP_REG1 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG1_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG1_CT_SHIFT (0U) -#define FFA_OP_REG1_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG1_CT_SHIFT) & FFA_OP_REG1_CT_MASK) -#define FFA_OP_REG1_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG1_CT_MASK) >> FFA_OP_REG1_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_MISC1 */ -/* - * OUTD_MEM_BLK (RW) - * - * Should be assigned as 0 - */ -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK (0x300000UL) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT (20U) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) - -/* - * COEF_MEM_BLK (RW) - * - * Should be assigned as 1 - */ -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK (0xC0000UL) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT (18U) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) - -/* - * IND_MEM_BLK (RW) - * - * Should be assigned as 2 - */ -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK (0x30000UL) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT (16U) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) - -/* - * FIR_DATA_TAPS (RW) - * - * The input data data length - */ -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK (0xFFFFU) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT (0U) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) >> FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) - -/* Bitfield definition for register: OP_REG2 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG2_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG2_CT_SHIFT (0U) -#define FFA_OP_REG2_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG2_CT_SHIFT) & FFA_OP_REG2_CT_MASK) -#define FFA_OP_REG2_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG2_CT_MASK) >> FFA_OP_REG2_CT_SHIFT) - -/* Bitfield definition for register: OP_FFT_INRBUF */ -/* - * LOC (RW) - * - * The input (real) data buffer pointer - */ -#define FFA_OP_FFT_INRBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FFT_INRBUF_LOC_SHIFT (0U) -#define FFA_OP_FFT_INRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_INRBUF_LOC_SHIFT) & FFA_OP_FFT_INRBUF_LOC_MASK) -#define FFA_OP_FFT_INRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_INRBUF_LOC_MASK) >> FFA_OP_FFT_INRBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG3 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG3_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG3_CT_SHIFT (0U) -#define FFA_OP_REG3_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG3_CT_SHIFT) & FFA_OP_REG3_CT_MASK) -#define FFA_OP_REG3_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG3_CT_MASK) >> FFA_OP_REG3_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_INBUF */ -/* - * LOC (RW) - * - * The input data buffer pointer - */ -#define FFA_OP_FIR_INBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_INBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_INBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_INBUF_LOC_SHIFT) & FFA_OP_FIR_INBUF_LOC_MASK) -#define FFA_OP_FIR_INBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_INBUF_LOC_MASK) >> FFA_OP_FIR_INBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG4 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG4_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG4_CT_SHIFT (0U) -#define FFA_OP_REG4_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG4_CT_SHIFT) & FFA_OP_REG4_CT_MASK) -#define FFA_OP_REG4_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG4_CT_MASK) >> FFA_OP_REG4_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_COEFBUF */ -/* - * LOC (RW) - * - * The coef buf pointer - */ -#define FFA_OP_FIR_COEFBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_COEFBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_COEFBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_COEFBUF_LOC_SHIFT) & FFA_OP_FIR_COEFBUF_LOC_MASK) -#define FFA_OP_FIR_COEFBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_COEFBUF_LOC_MASK) >> FFA_OP_FIR_COEFBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_FFT_OUTRBUF */ -/* - * LOC (RW) - * - * The output (real) data buffer pointer - */ -#define FFA_OP_FFT_OUTRBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FFT_OUTRBUF_LOC_SHIFT (0U) -#define FFA_OP_FFT_OUTRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_OUTRBUF_LOC_SHIFT) & FFA_OP_FFT_OUTRBUF_LOC_MASK) -#define FFA_OP_FFT_OUTRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_OUTRBUF_LOC_MASK) >> FFA_OP_FFT_OUTRBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG5 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG5_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG5_CT_SHIFT (0U) -#define FFA_OP_REG5_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG5_CT_SHIFT) & FFA_OP_REG5_CT_MASK) -#define FFA_OP_REG5_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG5_CT_MASK) >> FFA_OP_REG5_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_OUTBUF */ -/* - * LOC (RW) - * - * The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - */ -#define FFA_OP_FIR_OUTBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_OUTBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_OUTBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_OUTBUF_LOC_SHIFT) & FFA_OP_FIR_OUTBUF_LOC_MASK) -#define FFA_OP_FIR_OUTBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_OUTBUF_LOC_MASK) >> FFA_OP_FIR_OUTBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG6 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG6_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG6_CT_SHIFT (0U) -#define FFA_OP_REG6_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG6_CT_SHIFT) & FFA_OP_REG6_CT_MASK) -#define FFA_OP_REG6_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG6_CT_MASK) >> FFA_OP_REG6_CT_SHIFT) - -/* Bitfield definition for register: OP_REG7 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG7_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG7_CT_SHIFT (0U) -#define FFA_OP_REG7_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG7_CT_SHIFT) & FFA_OP_REG7_CT_MASK) -#define FFA_OP_REG7_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG7_CT_MASK) >> FFA_OP_REG7_CT_SHIFT) - - - - -#endif /* HPM_FFA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpio_regs.h deleted file mode 100644 index dcc90189c62..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpio_regs.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIO_H -#define HPM_GPIO_H - -typedef struct { - struct { - __R uint32_t VALUE; /* 0x0: GPIO input value */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - } DI[16]; - struct { - __RW uint32_t VALUE; /* 0x100: GPIO output value */ - __RW uint32_t SET; /* 0x104: GPIO output set */ - __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ - __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ - } DO[16]; - struct { - __RW uint32_t VALUE; /* 0x200: GPIO direction value */ - __RW uint32_t SET; /* 0x204: GPIO direction set */ - __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ - __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ - } OE[16]; - struct { - __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ - } IF[16]; - struct { - __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ - __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ - __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ - } IE[16]; - struct { - __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ - __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ - __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ - __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ - } PL[16]; - struct { - __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ - __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ - __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ - __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ - } TP[16]; - struct { - __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ - __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ - __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ - __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ - } AS[16]; -} GPIO_Type; - - -/* Bitfield definition for register of struct array DI: VALUE */ -/* - * INPUT (RO) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: VALUE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) -#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) -#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: SET */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_SET_OUTPUT_SHIFT (0U) -#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) -#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: CLEAR */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) -#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) -#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: TOGGLE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) -#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) -#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array OE: VALUE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) -#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) -#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: SET */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_SET_DIRECTION_SHIFT (0U) -#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) -#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: CLEAR */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) -#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) -#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: TOGGLE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) -#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) -#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array IF: VALUE */ -/* - * IRQ_FLAG (W1C) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) -#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IE: VALUE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) -#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: SET */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) -#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) -#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: CLEAR */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) -#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) -#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: TOGGLE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) -#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array PL: VALUE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) -#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: SET */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) -#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) -#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: CLEAR */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) -#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) -#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: TOGGLE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) -#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array TP: VALUE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) -#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: SET */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) -#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: CLEAR */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) -#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: TOGGLE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) -#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array AS: VALUE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) -#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: SET */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) -#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: CLEAR */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) -#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: TOGGLE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) - - - -/* DI register group index macro definition */ -#define GPIO_DI_GPIOA (0UL) -#define GPIO_DI_GPIOB (1UL) -#define GPIO_DI_GPIOC (2UL) -#define GPIO_DI_GPIOD (3UL) -#define GPIO_DI_GPIOE (4UL) -#define GPIO_DI_GPIOF (5UL) -#define GPIO_DI_GPIOX (13UL) -#define GPIO_DI_GPIOY (14UL) -#define GPIO_DI_GPIOZ (15UL) - -/* DO register group index macro definition */ -#define GPIO_DO_GPIOA (0UL) -#define GPIO_DO_GPIOB (1UL) -#define GPIO_DO_GPIOC (2UL) -#define GPIO_DO_GPIOD (3UL) -#define GPIO_DO_GPIOE (4UL) -#define GPIO_DO_GPIOF (5UL) -#define GPIO_DO_GPIOX (13UL) -#define GPIO_DO_GPIOY (14UL) -#define GPIO_DO_GPIOZ (15UL) - -/* OE register group index macro definition */ -#define GPIO_OE_GPIOA (0UL) -#define GPIO_OE_GPIOB (1UL) -#define GPIO_OE_GPIOC (2UL) -#define GPIO_OE_GPIOD (3UL) -#define GPIO_OE_GPIOE (4UL) -#define GPIO_OE_GPIOF (5UL) -#define GPIO_OE_GPIOX (13UL) -#define GPIO_OE_GPIOY (14UL) -#define GPIO_OE_GPIOZ (15UL) - -/* IF register group index macro definition */ -#define GPIO_IF_GPIOA (0UL) -#define GPIO_IF_GPIOB (1UL) -#define GPIO_IF_GPIOC (2UL) -#define GPIO_IF_GPIOD (3UL) -#define GPIO_IF_GPIOE (4UL) -#define GPIO_IF_GPIOF (5UL) -#define GPIO_IF_GPIOX (13UL) -#define GPIO_IF_GPIOY (14UL) -#define GPIO_IF_GPIOZ (15UL) - -/* IE register group index macro definition */ -#define GPIO_IE_GPIOA (0UL) -#define GPIO_IE_GPIOB (1UL) -#define GPIO_IE_GPIOC (2UL) -#define GPIO_IE_GPIOD (3UL) -#define GPIO_IE_GPIOE (4UL) -#define GPIO_IE_GPIOF (5UL) -#define GPIO_IE_GPIOX (13UL) -#define GPIO_IE_GPIOY (14UL) -#define GPIO_IE_GPIOZ (15UL) - -/* PL register group index macro definition */ -#define GPIO_PL_GPIOA (0UL) -#define GPIO_PL_GPIOB (1UL) -#define GPIO_PL_GPIOC (2UL) -#define GPIO_PL_GPIOD (3UL) -#define GPIO_PL_GPIOE (4UL) -#define GPIO_PL_GPIOF (5UL) -#define GPIO_PL_GPIOX (13UL) -#define GPIO_PL_GPIOY (14UL) -#define GPIO_PL_GPIOZ (15UL) - -/* TP register group index macro definition */ -#define GPIO_TP_GPIOA (0UL) -#define GPIO_TP_GPIOB (1UL) -#define GPIO_TP_GPIOC (2UL) -#define GPIO_TP_GPIOD (3UL) -#define GPIO_TP_GPIOE (4UL) -#define GPIO_TP_GPIOF (5UL) -#define GPIO_TP_GPIOX (13UL) -#define GPIO_TP_GPIOY (14UL) -#define GPIO_TP_GPIOZ (15UL) - -/* AS register group index macro definition */ -#define GPIO_AS_GPIOA (0UL) -#define GPIO_AS_GPIOB (1UL) -#define GPIO_AS_GPIOC (2UL) -#define GPIO_AS_GPIOD (3UL) -#define GPIO_AS_GPIOE (4UL) -#define GPIO_AS_GPIOF (5UL) -#define GPIO_AS_GPIOX (13UL) -#define GPIO_AS_GPIOY (14UL) -#define GPIO_AS_GPIOZ (15UL) - - -#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpiom_regs.h deleted file mode 100644 index c138b4451f8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpiom_regs.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIOM_H -#define HPM_GPIOM_H - -typedef struct { - struct { - __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ - } ASSIGN[16]; -} GPIOM_Type; - - -/* Bitfield definition for register of struct array ASSIGN: PIN00 */ -/* - * LOCK (RW) - * - * lock fields in this register, lock can only be cleared by soc reset - * 0: fields can be changed - * 1: fields locked to current value, not changeable - */ -#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) -#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) -#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) - -/* - * HIDE (RW) - * - * pin value visibility to gpios, - * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 - * bit1: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - */ -#define GPIOM_ASSIGN_PIN_HIDE_MASK (0x300U) -#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) -#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) -#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) - -/* - * SELECT (RW) - * - * select which gpio controls chip pin, - * 0: soc gpio0; - * 2: cpu0 fastgpio - */ -#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) -#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) -#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) -#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) - - - -/* PIN register group index macro definition */ -#define GPIOM_ASSIGN_PIN_PIN00 (0UL) -#define GPIOM_ASSIGN_PIN_PIN01 (1UL) -#define GPIOM_ASSIGN_PIN_PIN02 (2UL) -#define GPIOM_ASSIGN_PIN_PIN03 (3UL) -#define GPIOM_ASSIGN_PIN_PIN04 (4UL) -#define GPIOM_ASSIGN_PIN_PIN05 (5UL) -#define GPIOM_ASSIGN_PIN_PIN06 (6UL) -#define GPIOM_ASSIGN_PIN_PIN07 (7UL) -#define GPIOM_ASSIGN_PIN_PIN08 (8UL) -#define GPIOM_ASSIGN_PIN_PIN09 (9UL) -#define GPIOM_ASSIGN_PIN_PIN10 (10UL) -#define GPIOM_ASSIGN_PIN_PIN11 (11UL) -#define GPIOM_ASSIGN_PIN_PIN12 (12UL) -#define GPIOM_ASSIGN_PIN_PIN13 (13UL) -#define GPIOM_ASSIGN_PIN_PIN14 (14UL) -#define GPIOM_ASSIGN_PIN_PIN15 (15UL) -#define GPIOM_ASSIGN_PIN_PIN16 (16UL) -#define GPIOM_ASSIGN_PIN_PIN17 (17UL) -#define GPIOM_ASSIGN_PIN_PIN18 (18UL) -#define GPIOM_ASSIGN_PIN_PIN19 (19UL) -#define GPIOM_ASSIGN_PIN_PIN20 (20UL) -#define GPIOM_ASSIGN_PIN_PIN21 (21UL) -#define GPIOM_ASSIGN_PIN_PIN22 (22UL) -#define GPIOM_ASSIGN_PIN_PIN23 (23UL) -#define GPIOM_ASSIGN_PIN_PIN24 (24UL) -#define GPIOM_ASSIGN_PIN_PIN25 (25UL) -#define GPIOM_ASSIGN_PIN_PIN26 (26UL) -#define GPIOM_ASSIGN_PIN_PIN27 (27UL) -#define GPIOM_ASSIGN_PIN_PIN28 (28UL) -#define GPIOM_ASSIGN_PIN_PIN29 (29UL) -#define GPIOM_ASSIGN_PIN_PIN30 (30UL) -#define GPIOM_ASSIGN_PIN_PIN31 (31UL) - -/* ASSIGN register group index macro definition */ -#define GPIOM_ASSIGN_GPIOA (0UL) -#define GPIOM_ASSIGN_GPIOB (1UL) -#define GPIOM_ASSIGN_GPIOC (2UL) -#define GPIOM_ASSIGN_GPIOD (3UL) -#define GPIOM_ASSIGN_GPIOE (4UL) -#define GPIOM_ASSIGN_GPIOF (5UL) -#define GPIOM_ASSIGN_GPIOX (13UL) -#define GPIOM_ASSIGN_GPIOY (14UL) -#define GPIOM_ASSIGN_GPIOZ (15UL) - - -#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gptmr_regs.h deleted file mode 100644 index 50e6e586e4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gptmr_regs.h +++ /dev/null @@ -1,644 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPTMR_H -#define HPM_GPTMR_H - -typedef struct { - struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ - __RW uint32_t RLD; /* 0xC: Reload register */ - __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ - __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ - __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ - __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ - __R uint32_t CNT; /* 0x30: Counter */ - __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ - } CHANNEL[4]; - __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ - __RW uint32_t SR; /* 0x200: Status register */ - __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ - __RW uint32_t GCR; /* 0x208: Global control register */ -} GPTMR_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CR */ -/* - * CNTUPT (WO) - * - * 1- update counter to new value as CNTUPTVAL - * This bit will be auto cleared after 1 cycle - */ -#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) -#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) -#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) -#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) - -/* - * OPMODE (RW) - * - * 0: round mode - * 1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. - * NOTE: reload irq will be always set at one-shot mode at end - */ -#define GPTMR_CHANNEL_CR_OPMODE_MASK (0x20000UL) -#define GPTMR_CHANNEL_CR_OPMODE_SHIFT (17U) -#define GPTMR_CHANNEL_CR_OPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_OPMODE_SHIFT) & GPTMR_CHANNEL_CR_OPMODE_MASK) -#define GPTMR_CHANNEL_CR_OPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_OPMODE_MASK) >> GPTMR_CHANNEL_CR_OPMODE_SHIFT) - -/* - * MONITOR_SEL (RW) - * - * set to monitor input signal high level time(chan_meas_high) - * clr to monitor input signal period(chan_meas_prd) - */ -#define GPTMR_CHANNEL_CR_MONITOR_SEL_MASK (0x10000UL) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT (16U) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) >> GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) - -/* - * MONITOR_EN (RW) - * - * set to monitor input signal period or high level time. - * When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts - * * only can be used when trig_mode is selected as measure mode(100) - * * the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. - * if no posedge after reload for more than val_1, will also assert irq_capt - */ -#define GPTMR_CHANNEL_CR_MONITOR_EN_MASK (0x8000U) -#define GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT (15U) -#define GPTMR_CHANNEL_CR_MONITOR_EN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) -#define GPTMR_CHANNEL_CR_MONITOR_EN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) >> GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) - -/* - * CNTRST (RW) - * - * 1- reset counter - */ -#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) -#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) -#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) -#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) - -/* - * SYNCFLW (RW) - * - * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. - * This bit is not valid for channel 0. - */ -#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) -#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) - -/* - * SYNCIFEN (RW) - * - * 1- SYNCI is valid on its falling edge - */ -#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) - -/* - * SYNCIREN (RW) - * - * 1- SYNCI is valid on its rising edge - */ -#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) - -/* - * CEN (RW) - * - * 1- counter enable - */ -#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) -#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) -#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) -#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) - -/* - * CMPINIT (RW) - * - * Output compare initial poliarity - * 1- The channel output initial level is high - * 0- The channel output initial level is low - * User should set this bit before set CMPEN to 1. - */ -#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) -#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) -#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) -#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) - -/* - * CMPEN (RW) - * - * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - */ -#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) -#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) -#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) -#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) - -/* - * DMASEL (RW) - * - * select one of DMA request: - * 00- CMP0 flag - * 01- CMP1 flag - * 10- Input signal toggle captured - * 11- RLD flag, counter reload; - */ -#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) -#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) -#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) -#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) - -/* - * DMAEN (RW) - * - * 1- enable dma - */ -#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) -#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) -#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) -#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) - -/* - * SWSYNCIEN (RW) - * - * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - */ -#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) - -/* - * DBGPAUSE (RW) - * - * 1- counter will pause if chip is in debug mode - */ -#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) -#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) - -/* - * CAPMODE (RW) - * - * This bitfield define the input capture mode - * 100: width measure mode, timer will calculate the input signal period and duty cycle - * 011: capture at both rising edge and falling edge - * 010: capture at falling edge - * 001: capture at rising edge - * 000: No capture - */ -#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) -#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) -#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) -#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CMP0 */ -/* - * CMP (RW) - * - * compare value 0 - */ -#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) -#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) -#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: RLD */ -/* - * RLD (RW) - * - * reload value - */ -#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) -#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) -#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ -/* - * CNTUPTVAL (RW) - * - * counter will be set to this value when software write cntupt bit in CR - */ -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ -/* - * CAPPOS (RO) - * - * This register contains the counter value captured at input signal rising edge - */ -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ -/* - * CAPNEG (RO) - * - * This register contains the counter value captured at input signal falling edge - */ -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ -/* - * CAPPRD (RO) - * - * This register contains the input signal period when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ -/* - * MEAS_HIGH (RO) - * - * This register contains the input signal duty cycle when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNT */ -/* - * COUNTER (RO) - * - * 32 bit counter value - */ -#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) -#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * CH3CMP1F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) -#define GPTMR_SR_CH3CMP1F_SHIFT (15U) -#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) -#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) - -/* - * CH3CMP0F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) -#define GPTMR_SR_CH3CMP0F_SHIFT (14U) -#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) -#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) - -/* - * CH3CAPF (W1C) - * - * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH3CAPF_MASK (0x2000U) -#define GPTMR_SR_CH3CAPF_SHIFT (13U) -#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) -#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) - -/* - * CH3RLDF (W1C) - * - * channel 3 counter reload flag - */ -#define GPTMR_SR_CH3RLDF_MASK (0x1000U) -#define GPTMR_SR_CH3RLDF_SHIFT (12U) -#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) -#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) - -/* - * CH2CMP1F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP1F_MASK (0x800U) -#define GPTMR_SR_CH2CMP1F_SHIFT (11U) -#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) -#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) - -/* - * CH2CMP0F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP0F_MASK (0x400U) -#define GPTMR_SR_CH2CMP0F_SHIFT (10U) -#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) -#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) - -/* - * CH2CAPF (W1C) - * - * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH2CAPF_MASK (0x200U) -#define GPTMR_SR_CH2CAPF_SHIFT (9U) -#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) -#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) - -/* - * CH2RLDF (W1C) - * - * channel 2 counter reload flag - */ -#define GPTMR_SR_CH2RLDF_MASK (0x100U) -#define GPTMR_SR_CH2RLDF_SHIFT (8U) -#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) -#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) - -/* - * CH1CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP1F_MASK (0x80U) -#define GPTMR_SR_CH1CMP1F_SHIFT (7U) -#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) -#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) - -/* - * CH1CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP0F_MASK (0x40U) -#define GPTMR_SR_CH1CMP0F_SHIFT (6U) -#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) -#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) - -/* - * CH1CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH1CAPF_MASK (0x20U) -#define GPTMR_SR_CH1CAPF_SHIFT (5U) -#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) -#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) - -/* - * CH1RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH1RLDF_MASK (0x10U) -#define GPTMR_SR_CH1RLDF_SHIFT (4U) -#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) -#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) - -/* - * CH0CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP1F_MASK (0x8U) -#define GPTMR_SR_CH0CMP1F_SHIFT (3U) -#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) -#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) - -/* - * CH0CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP0F_MASK (0x4U) -#define GPTMR_SR_CH0CMP0F_SHIFT (2U) -#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) -#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) - -/* - * CH0CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH0CAPF_MASK (0x2U) -#define GPTMR_SR_CH0CAPF_SHIFT (1U) -#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) -#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) - -/* - * CH0RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH0RLDF_MASK (0x1U) -#define GPTMR_SR_CH0RLDF_SHIFT (0U) -#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) -#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * CH3CMP1EN (RW) - * - * 1- generate interrupt request when ch3cmp1f flag is set - */ -#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) -#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) -#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) -#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) - -/* - * CH3CMP0EN (RW) - * - * 1- generate interrupt request when ch3cmp0f flag is set - */ -#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) -#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) -#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) -#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) - -/* - * CH3CAPEN (RW) - * - * 1- generate interrupt request when ch3capf flag is set - */ -#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) -#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) -#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) -#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) - -/* - * CH3RLDEN (RW) - * - * 1- generate interrupt request when ch3rldf flag is set - */ -#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) -#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) -#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) -#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) - -/* - * CH2CMP1EN (RW) - * - * 1- generate interrupt request when ch2cmp1f flag is set - */ -#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) -#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) -#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) -#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) - -/* - * CH2CMP0EN (RW) - * - * 1- generate interrupt request when ch2cmp0f flag is set - */ -#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) -#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) -#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) -#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) - -/* - * CH2CAPEN (RW) - * - * 1- generate interrupt request when ch2capf flag is set - */ -#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) -#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) -#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) -#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) - -/* - * CH2RLDEN (RW) - * - * 1- generate interrupt request when ch2rldf flag is set - */ -#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) -#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) -#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) -#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) - -/* - * CH1CMP1EN (RW) - * - * 1- generate interrupt request when ch1cmp1f flag is set - */ -#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) -#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) -#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) -#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) - -/* - * CH1CMP0EN (RW) - * - * 1- generate interrupt request when ch1cmp0f flag is set - */ -#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) -#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) -#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) -#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) - -/* - * CH1CAPEN (RW) - * - * 1- generate interrupt request when ch1capf flag is set - */ -#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) -#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) -#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) -#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) - -/* - * CH1RLDEN (RW) - * - * 1- generate interrupt request when ch1rldf flag is set - */ -#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) -#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) -#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) -#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) - -/* - * CH0CMP1EN (RW) - * - * 1- generate interrupt request when ch0cmp1f flag is set - */ -#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) -#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) -#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) -#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) - -/* - * CH0CMP0EN (RW) - * - * 1- generate interrupt request when ch0cmp0f flag is set - */ -#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) -#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) -#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) -#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) - -/* - * CH0CAPEN (RW) - * - * 1- generate interrupt request when ch0capf flag is set - */ -#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) -#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) -#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) -#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) - -/* - * CH0RLDEN (RW) - * - * 1- generate interrupt request when ch0rldf flag is set - */ -#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) -#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) -#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) -#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * SWSYNCT (RW) - * - * set this bitfield to trigger software counter sync event - */ -#define GPTMR_GCR_SWSYNCT_MASK (0xFU) -#define GPTMR_GCR_SWSYNCT_SHIFT (0U) -#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) -#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) - - - -/* CMP register group index macro definition */ -#define GPTMR_CHANNEL_CMP_CMP0 (0UL) -#define GPTMR_CHANNEL_CMP_CMP1 (1UL) - -/* CHANNEL register group index macro definition */ -#define GPTMR_CHANNEL_CH0 (0UL) -#define GPTMR_CHANNEL_CH1 (1UL) -#define GPTMR_CHANNEL_CH2 (2UL) -#define GPTMR_CHANNEL_CH3 (3UL) - - -#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpu_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpu_regs.h deleted file mode 100644 index d53de182402..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gpu_regs.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPU_H -#define HPM_GPU_H - -typedef struct { - __RW uint32_t AQHICLOCKCONTROL; /* 0x0: clock control register */ - __R uint32_t AQHILDLE; /* 0x4: idle status register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __R uint32_t AQINTRACKNOWLEDGE; /* 0x10: interrupt acknoledge register */ - __RW uint32_t AQINTRENBL; /* 0x14: interrupt enable register */ - __R uint8_t RESERVED1[12]; /* 0x18 - 0x23: Reserved */ - __R uint32_t GCCHIPREV; /* 0x24: chip revison register */ - __R uint32_t GCCHIPDATE; /* 0x28: chip date register */ - __R uint8_t RESERVED2[108]; /* 0x2C - 0x97: Reserved */ - __R uint32_t GCREGHICHIPPATCHREV; /* 0x98: chip patch revision register */ - __R uint8_t RESERVED3[12]; /* 0x9C - 0xA7: Reserved */ - __R uint32_t GCPRODUCTID; /* 0xA8: product identification register */ - __R uint8_t RESERVED4[84]; /* 0xAC - 0xFF: Reserved */ - __RW uint32_t GCMODULEPOWERCONTROLS; /* 0x100: module power control register */ - __RW uint32_t GCMODULEPOWERMODULECONTROL; /* 0x104: module power module control register */ - __R uint32_t GCMODULEPOWERMODULESTATUS; /* 0x108: module power module status register */ - __R uint8_t RESERVED5[756]; /* 0x10C - 0x3FF: Reserved */ - __RW uint32_t AQMEMORYFEPAGETABLE; /* 0x400: fetch engine page table base address register */ - __R uint8_t RESERVED6[16]; /* 0x404 - 0x413: Reserved */ - __RW uint32_t AQMEMORYDEBUG; /* 0x414: memory debug register */ - __R uint8_t RESERVED7[20]; /* 0x418 - 0x42B: Reserved */ - __RW uint32_t AQREGISTERTIMINGCONTROL; /* 0x42C: timing control register */ - __R uint8_t RESERVED8[208]; /* 0x430 - 0x4FF: Reserved */ - __RW uint32_t GCREGFETCHADDRESS; /* 0x500: fetch command buffer base address register */ - __RW uint32_t GCREGFETCHCONTROL; /* 0x504: fetch control register */ - __R uint32_t GCREGCURRENTFETCHADDRESS; /* 0x508: current fetch command address register */ -} GPU_Type; - - -/* Bitfield definition for register: AQHICLOCKCONTROL */ -/* - * ISOLATE_GPU (RW) - * - * isolate GPU bit, used for power on/off - */ -#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK (0x80000UL) -#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT (19U) -#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) -#define GPU_AQHICLOCKCONTROL_ISOLATE_GPU_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_ISOLATE_GPU_MASK) >> GPU_AQHICLOCKCONTROL_ISOLATE_GPU_SHIFT) - -/* - * IDLE_VG (R) - * - * vg pipe is idle - */ -#define GPU_AQHICLOCKCONTROL_IDLE_VG_MASK (0x40000UL) -#define GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT (18U) -#define GPU_AQHICLOCKCONTROL_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE_VG_MASK) >> GPU_AQHICLOCKCONTROL_IDLE_VG_SHIFT) - -/* - * IDLE2_D (R) - * - * 2D pipe is idle or not present - */ -#define GPU_AQHICLOCKCONTROL_IDLE2_D_MASK (0x20000UL) -#define GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT (17U) -#define GPU_AQHICLOCKCONTROL_IDLE2_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE2_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE2_D_SHIFT) - -/* - * IDLE3_D (R) - * - * 3D pipe is idle or not present - */ -#define GPU_AQHICLOCKCONTROL_IDLE3_D_MASK (0x10000UL) -#define GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT (16U) -#define GPU_AQHICLOCKCONTROL_IDLE3_D_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_IDLE3_D_MASK) >> GPU_AQHICLOCKCONTROL_IDLE3_D_SHIFT) - -/* - * DISABLE_RAM_POWER_OPTIMIZATION (RW) - * - * disables ram power optimization - */ -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK (0x2000U) -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT (13U) -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_POWER_OPTIMIZATION_SHIFT) - -/* - * SOFT_RESET (RW) - * - * soft reset the IP - */ -#define GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK (0x1000U) -#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT (12U) -#define GPU_AQHICLOCKCONTROL_SOFT_RESET_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) -#define GPU_AQHICLOCKCONTROL_SOFT_RESET_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_SOFT_RESET_MASK) >> GPU_AQHICLOCKCONTROL_SOFT_RESET_SHIFT) - -/* - * DISABLE_DEBUG_REGISTERS (RW) - * - * disable debug registers - */ -#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK (0x800U) -#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT (11U) -#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) -#define GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_DEBUG_REGISTERS_SHIFT) - -/* - * DISABLE_RAM_CLOCK_GATING (RW) - * - * disables clock gating for rams - */ -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK (0x400U) -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT (10U) -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) -#define GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_MASK) >> GPU_AQHICLOCKCONTROL_DISABLE_RAM_CLOCK_GATING_SHIFT) - -/* - * FSCALE_CMD_LOAD (RW) - * - * core clock frequency scale value enable - */ -#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK (0x200U) -#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT (9U) -#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) -#define GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_CMD_LOAD_SHIFT) - -/* - * FSCALE_VAL (RW) - * - * core clock frequency scale value - */ -#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK (0x1FCU) -#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT (2U) -#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) -#define GPU_AQHICLOCKCONTROL_FSCALE_VAL_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_FSCALE_VAL_MASK) >> GPU_AQHICLOCKCONTROL_FSCALE_VAL_SHIFT) - -/* - * CLK2D_DIS (RW) - * - * disable 2D/VG clock - */ -#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK (0x2U) -#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT (1U) -#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_SET(x) (((uint32_t)(x) << GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) -#define GPU_AQHICLOCKCONTROL_CLK2D_DIS_GET(x) (((uint32_t)(x) & GPU_AQHICLOCKCONTROL_CLK2D_DIS_MASK) >> GPU_AQHICLOCKCONTROL_CLK2D_DIS_SHIFT) - -/* Bitfield definition for register: AQHILDLE */ -/* - * AXI_LP (R) - * - * axi is in low power mode - */ -#define GPU_AQHILDLE_AXI_LP_MASK (0x80000000UL) -#define GPU_AQHILDLE_AXI_LP_SHIFT (31U) -#define GPU_AQHILDLE_AXI_LP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_AXI_LP_MASK) >> GPU_AQHILDLE_AXI_LP_SHIFT) - -/* - * IDLE_BLT (R) - * - * BLT is idle or not present - */ -#define GPU_AQHILDLE_IDLE_BLT_MASK (0x1000U) -#define GPU_AQHILDLE_IDLE_BLT_SHIFT (12U) -#define GPU_AQHILDLE_IDLE_BLT_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_BLT_MASK) >> GPU_AQHILDLE_IDLE_BLT_SHIFT) - -/* - * IDLE_TS (R) - * - * Tessellation Engine is idle - */ -#define GPU_AQHILDLE_IDLE_TS_MASK (0x800U) -#define GPU_AQHILDLE_IDLE_TS_SHIFT (11U) -#define GPU_AQHILDLE_IDLE_TS_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TS_MASK) >> GPU_AQHILDLE_IDLE_TS_SHIFT) - -/* - * IDLE_FP (R) - * - * FP is idle or not present - */ -#define GPU_AQHILDLE_IDLE_FP_MASK (0x400U) -#define GPU_AQHILDLE_IDLE_FP_SHIFT (10U) -#define GPU_AQHILDLE_IDLE_FP_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FP_MASK) >> GPU_AQHILDLE_IDLE_FP_SHIFT) - -/* - * IDLE_IM (R) - * - * Image Engine is idle - */ -#define GPU_AQHILDLE_IDLE_IM_MASK (0x200U) -#define GPU_AQHILDLE_IDLE_IM_SHIFT (9U) -#define GPU_AQHILDLE_IDLE_IM_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_IM_MASK) >> GPU_AQHILDLE_IDLE_IM_SHIFT) - -/* - * IDLE_VG (R) - * - * Vector Graphics Engine is idle - */ -#define GPU_AQHILDLE_IDLE_VG_MASK (0x100U) -#define GPU_AQHILDLE_IDLE_VG_SHIFT (8U) -#define GPU_AQHILDLE_IDLE_VG_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_VG_MASK) >> GPU_AQHILDLE_IDLE_VG_SHIFT) - -/* - * IDLE_TX (R) - * - * TX is idle or not present - */ -#define GPU_AQHILDLE_IDLE_TX_MASK (0x80U) -#define GPU_AQHILDLE_IDLE_TX_SHIFT (7U) -#define GPU_AQHILDLE_IDLE_TX_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_TX_MASK) >> GPU_AQHILDLE_IDLE_TX_SHIFT) - -/* - * IDLE_RA (R) - * - * RA is idle or not present - */ -#define GPU_AQHILDLE_IDLE_RA_MASK (0x40U) -#define GPU_AQHILDLE_IDLE_RA_SHIFT (6U) -#define GPU_AQHILDLE_IDLE_RA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_RA_MASK) >> GPU_AQHILDLE_IDLE_RA_SHIFT) - -/* - * IDLE_SE (R) - * - * SE is idle or not present - */ -#define GPU_AQHILDLE_IDLE_SE_MASK (0x20U) -#define GPU_AQHILDLE_IDLE_SE_SHIFT (5U) -#define GPU_AQHILDLE_IDLE_SE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SE_MASK) >> GPU_AQHILDLE_IDLE_SE_SHIFT) - -/* - * IDLE_PA (R) - * - * PA is idle or not present - */ -#define GPU_AQHILDLE_IDLE_PA_MASK (0x10U) -#define GPU_AQHILDLE_IDLE_PA_SHIFT (4U) -#define GPU_AQHILDLE_IDLE_PA_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PA_MASK) >> GPU_AQHILDLE_IDLE_PA_SHIFT) - -/* - * IDLE_SH (R) - * - * SH is idle or not present - */ -#define GPU_AQHILDLE_IDLE_SH_MASK (0x8U) -#define GPU_AQHILDLE_IDLE_SH_SHIFT (3U) -#define GPU_AQHILDLE_IDLE_SH_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_SH_MASK) >> GPU_AQHILDLE_IDLE_SH_SHIFT) - -/* - * IDLE_PE (R) - * - * Pixel engine is idle - */ -#define GPU_AQHILDLE_IDLE_PE_MASK (0x4U) -#define GPU_AQHILDLE_IDLE_PE_SHIFT (2U) -#define GPU_AQHILDLE_IDLE_PE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_PE_MASK) >> GPU_AQHILDLE_IDLE_PE_SHIFT) - -/* - * IDLE_DE (R) - * - * DE is dile or not present - */ -#define GPU_AQHILDLE_IDLE_DE_MASK (0x2U) -#define GPU_AQHILDLE_IDLE_DE_SHIFT (1U) -#define GPU_AQHILDLE_IDLE_DE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_DE_MASK) >> GPU_AQHILDLE_IDLE_DE_SHIFT) - -/* - * IDLE_FE (R) - * - * 0: fetch engine is busy 1:fetch engine is idle - */ -#define GPU_AQHILDLE_IDLE_FE_MASK (0x1U) -#define GPU_AQHILDLE_IDLE_FE_SHIFT (0U) -#define GPU_AQHILDLE_IDLE_FE_GET(x) (((uint32_t)(x) & GPU_AQHILDLE_IDLE_FE_MASK) >> GPU_AQHILDLE_IDLE_FE_SHIFT) - -/* Bitfield definition for register: AQINTRACKNOWLEDGE */ -/* - * INTR_VEC (R) - * - * for each interrupt event, 0=clear,1=interrupt active - */ -#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK (0xFFFFFFFFUL) -#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT (0U) -#define GPU_AQINTRACKNOWLEDGE_INTR_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRACKNOWLEDGE_INTR_VEC_MASK) >> GPU_AQINTRACKNOWLEDGE_INTR_VEC_SHIFT) - -/* Bitfield definition for register: AQINTRENBL */ -/* - * INTR_ENBL_VEC (RW) - * - * 0=disable interrupt; 1=enable interrupt - */ -#define GPU_AQINTRENBL_INTR_ENBL_VEC_MASK (0xFFFFFFFFUL) -#define GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT (0U) -#define GPU_AQINTRENBL_INTR_ENBL_VEC_SET(x) (((uint32_t)(x) << GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) -#define GPU_AQINTRENBL_INTR_ENBL_VEC_GET(x) (((uint32_t)(x) & GPU_AQINTRENBL_INTR_ENBL_VEC_MASK) >> GPU_AQINTRENBL_INTR_ENBL_VEC_SHIFT) - -/* Bitfield definition for register: GCCHIPREV */ -/* - * REV (R) - * - * revision - */ -#define GPU_GCCHIPREV_REV_MASK (0xFFFFFFFFUL) -#define GPU_GCCHIPREV_REV_SHIFT (0U) -#define GPU_GCCHIPREV_REV_GET(x) (((uint32_t)(x) & GPU_GCCHIPREV_REV_MASK) >> GPU_GCCHIPREV_REV_SHIFT) - -/* Bitfield definition for register: GCCHIPDATE */ -/* - * DATE (R) - * - * date - */ -#define GPU_GCCHIPDATE_DATE_MASK (0xFFFFFFFFUL) -#define GPU_GCCHIPDATE_DATE_SHIFT (0U) -#define GPU_GCCHIPDATE_DATE_GET(x) (((uint32_t)(x) & GPU_GCCHIPDATE_DATE_MASK) >> GPU_GCCHIPDATE_DATE_SHIFT) - -/* Bitfield definition for register: GCREGHICHIPPATCHREV */ -/* - * PATCH_REV (R) - * - * patch revision - */ -#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK (0xFFU) -#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT (0U) -#define GPU_GCREGHICHIPPATCHREV_PATCH_REV_GET(x) (((uint32_t)(x) & GPU_GCREGHICHIPPATCHREV_PATCH_REV_MASK) >> GPU_GCREGHICHIPPATCHREV_PATCH_REV_SHIFT) - -/* Bitfield definition for register: GCPRODUCTID */ -/* - * TYPE (R) - * - * product type is 3:VG - */ -#define GPU_GCPRODUCTID_TYPE_MASK (0xF000000UL) -#define GPU_GCPRODUCTID_TYPE_SHIFT (24U) -#define GPU_GCPRODUCTID_TYPE_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_TYPE_MASK) >> GPU_GCPRODUCTID_TYPE_SHIFT) - -/* - * NUM (R) - * - * product number is 265 - */ -#define GPU_GCPRODUCTID_NUM_MASK (0xFFFFF0UL) -#define GPU_GCPRODUCTID_NUM_SHIFT (4U) -#define GPU_GCPRODUCTID_NUM_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_NUM_MASK) >> GPU_GCPRODUCTID_NUM_SHIFT) - -/* - * GRADE_LEVEL (R) - * - * 0:None_no extra letter on the product name for this core 1:nano 5:nano ultra - */ -#define GPU_GCPRODUCTID_GRADE_LEVEL_MASK (0xFU) -#define GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT (0U) -#define GPU_GCPRODUCTID_GRADE_LEVEL_GET(x) (((uint32_t)(x) & GPU_GCPRODUCTID_GRADE_LEVEL_MASK) >> GPU_GCPRODUCTID_GRADE_LEVEL_SHIFT) - -/* Bitfield definition for register: GCMODULEPOWERCONTROLS */ -/* - * TURN_OFF_COUNTER (RW) - * - * counter value for clock gating the module if the module is idle for this amout of clock cycles - */ -#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK (0xFFFF0000UL) -#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT (16U) -#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) -#define GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_OFF_COUNTER_SHIFT) - -/* - * TURN_ON_COUNTER (RW) - * - * number of clock cycle gating the module if the modules is idle for this amout of clockk cycles - */ -#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK (0xF0U) -#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT (4U) -#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) -#define GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_MASK) >> GPU_GCMODULEPOWERCONTROLS_TURN_ON_COUNTER_SHIFT) - -/* - * DISABLE_STARVE_MODULE_CLOCK_GATING (RW) - * - * disable module level clock gating for starve/idle condition - */ -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK (0x4U) -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT (2U) -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING_SHIFT) - -/* - * DISABLE_STALL_MODULE_CLOCK_GATING (RW) - * - * disable module level clock gating for stall condition - */ -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK (0x2U) -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT (1U) -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) -#define GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING_SHIFT) - -/* - * ENABLE_MODULE_CLOCK_GATING (RW) - * - * enable module level clock gating - */ -#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK (0x1U) -#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT (0U) -#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) -#define GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_MASK) >> GPU_GCMODULEPOWERCONTROLS_ENABLE_MODULE_CLOCK_GATING_SHIFT) - -/* Bitfield definition for register: GCMODULEPOWERMODULECONTROL */ -/* - * DISABLE_MODULE_CLOCKGATING_FLEXA (RW) - * - * disables module level clock gating for flexa, not supported for all variants - */ -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK (0x1000U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT (12U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCKGATING_FLEXA_SHIFT) - -/* - * DISABLE_MODULE_CLOCK_GATING_TS (RW) - * - * disables module level clock gating for TS - */ -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK (0x800U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT (11U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_TS_SHIFT) - -/* - * DISABLE_MODULE_CLOCK_GATING_IM (RW) - * - * disables module level clock gating for IM - */ -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK (0x200U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT (9U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_IM_SHIFT) - -/* - * DISABLE_MODULE_CLOCK_GATING_VG (RW) - * - * disables module lelvel clock gating for VG - */ -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK (0x100U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT (8U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_VG_SHIFT) - -/* - * DISABLE_MODULE_CLOCK_GATING_PE (RW) - * - * disables module level clock gating for PE - */ -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK (0x4U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT (2U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_PE_SHIFT) - -/* - * DISABLE_MODULE_CLOCK_GATING_FE (RW) - * - * disables module level clock gating for FE - */ -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK (0x1U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT (0U) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SET(x) (((uint32_t)(x) << GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) -#define GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_MASK) >> GPU_GCMODULEPOWERMODULECONTROL_DISABLE_MODULE_CLOCK_GATING_FE_SHIFT) - -/* Bitfield definition for register: GCMODULEPOWERMODULESTATUS */ -/* - * MODULE_CLOCK_GATED_FLEXA (R) - * - * module level ckock gating is on for flexa - */ -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK (0x1000U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT (12U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FLEXA_SHIFT) - -/* - * MODULE_CLOCK_GATED_TS (R) - * - * module level ckock gating is on for ts - */ -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK (0x800U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT (11U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_TS_SHIFT) - -/* - * MODULE_CLOCK_GATED_IM (R) - * - * module level clock gating is on for IM - */ -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK (0x200U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT (9U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_IM_SHIFT) - -/* - * MODULE_CLOCK_GATED_VG (R) - * - * module level clock gating is on for VG - */ -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK (0x100U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT (8U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_VG_SHIFT) - -/* - * MODULE_CLOCK_GATED_PE (R) - * - * module level clock gating is on for PE - */ -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK (0x4U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT (2U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_PE_SHIFT) - -/* - * MODULE_CLOCK_GATED_FE (R) - * - * module level clock gating is on for FE - */ -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK (0x1U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT (0U) -#define GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_GET(x) (((uint32_t)(x) & GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_MASK) >> GPU_GCMODULEPOWERMODULESTATUS_MODULE_CLOCK_GATED_FE_SHIFT) - -/* Bitfield definition for register: AQMEMORYFEPAGETABLE */ -/* - * BASE_ADDRESS (RW) - * - * base address for the FE virtual address lookup table - */ -#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK (0xFFFFF000UL) -#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT (12U) -#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) -#define GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_MASK) >> GPU_AQMEMORYFEPAGETABLE_BASE_ADDRESS_SHIFT) - -/* Bitfield definition for register: AQMEMORYDEBUG */ -/* - * ZCOMP_LIMIT (RW) - * - * not relevant for vector graphics IP - */ -#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK (0x3F000000UL) -#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT (24U) -#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) -#define GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_MASK) >> GPU_AQMEMORYDEBUG_ZCOMP_LIMIT_SHIFT) - -/* - * MAX_OUTSTANDING_READS (RW) - * - * limits the total number of outstanding read requests - */ -#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK (0xFFU) -#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT (0U) -#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SET(x) (((uint32_t)(x) << GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) -#define GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_GET(x) (((uint32_t)(x) & GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_MASK) >> GPU_AQMEMORYDEBUG_MAX_OUTSTANDING_READS_SHIFT) - -/* Bitfield definition for register: AQREGISTERTIMINGCONTROL */ -/* - * POWER_DOWN (RW) - * - * powerdown memory - */ -#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK (0x100000UL) -#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT (20U) -#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) -#define GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_MASK) >> GPU_AQREGISTERTIMINGCONTROL_POWER_DOWN_SHIFT) - -/* - * FAST_WTC (RW) - * - * WTC for fast rams - */ -#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK (0xC0000UL) -#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT (18U) -#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) -#define GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_WTC_SHIFT) - -/* - * FAST_RTC (RW) - * - * RTC for fast rams - */ -#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK (0x30000UL) -#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT (16U) -#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) -#define GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FAST_RTC_SHIFT) - -/* - * FOR_RF2P (RW) - * - * for 2 port ram - */ -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK (0xFF00U) -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT (8U) -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF2P_SHIFT) - -/* - * FOR_RF1P (RW) - * - * for 1 port ram - */ -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK (0xFFU) -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT (0U) -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SET(x) (((uint32_t)(x) << GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) -#define GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_GET(x) (((uint32_t)(x) & GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_MASK) >> GPU_AQREGISTERTIMINGCONTROL_FOR_RF1P_SHIFT) - -/* Bitfield definition for register: GCREGFETCHADDRESS */ -/* - * ADDRESS (RW) - * - * address of command buffer - */ -#define GPU_GCREGFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFCUL) -#define GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT (2U) -#define GPU_GCREGFETCHADDRESS_ADDRESS_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) -#define GPU_GCREGFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGFETCHADDRESS_ADDRESS_SHIFT) - -/* - * TYPE (RW) - * - * 0=system 2=vritual 1=local - */ -#define GPU_GCREGFETCHADDRESS_TYPE_MASK (0x3U) -#define GPU_GCREGFETCHADDRESS_TYPE_SHIFT (0U) -#define GPU_GCREGFETCHADDRESS_TYPE_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHADDRESS_TYPE_SHIFT) & GPU_GCREGFETCHADDRESS_TYPE_MASK) -#define GPU_GCREGFETCHADDRESS_TYPE_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHADDRESS_TYPE_MASK) >> GPU_GCREGFETCHADDRESS_TYPE_SHIFT) - -/* Bitfield definition for register: GCREGFETCHCONTROL */ -/* - * COUNT (RW) - * - * number of 64bit words to fetch - */ -#define GPU_GCREGFETCHCONTROL_COUNT_MASK (0x1FFFFFUL) -#define GPU_GCREGFETCHCONTROL_COUNT_SHIFT (0U) -#define GPU_GCREGFETCHCONTROL_COUNT_SET(x) (((uint32_t)(x) << GPU_GCREGFETCHCONTROL_COUNT_SHIFT) & GPU_GCREGFETCHCONTROL_COUNT_MASK) -#define GPU_GCREGFETCHCONTROL_COUNT_GET(x) (((uint32_t)(x) & GPU_GCREGFETCHCONTROL_COUNT_MASK) >> GPU_GCREGFETCHCONTROL_COUNT_SHIFT) - -/* Bitfield definition for register: GCREGCURRENTFETCHADDRESS */ -/* - * ADDRESS (R) - * - * address - */ -#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK (0xFFFFFFFFUL) -#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT (0U) -#define GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_GET(x) (((uint32_t)(x) & GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_MASK) >> GPU_GCREGCURRENTFETCHADDRESS_ADDRESS_SHIFT) - - - - -#endif /* HPM_GPU_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gwc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gwc_regs.h deleted file mode 100644 index 4a7ba443c09..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_gwc_regs.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GWC_H -#define HPM_GWC_H - -typedef struct { - __RW uint32_t GLB_CTRL; /* 0x0: control reg */ - __RW uint32_t IRQ_MASK; /* 0x4: interrupt enable */ - __RW uint32_t IRQ_STS; /* 0x8: interrupt status */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x10: config reg 0 */ - __RW uint32_t CFG1; /* 0x14: config reg 1 */ - __RW uint32_t REFCRC; /* 0x18: reference CRC */ - __RW uint32_t CALCRC; /* 0x1C: calculated CRC */ - } CHANNEL[16]; -} GWC_Type; - - -/* Bitfield definition for register: GLB_CTRL */ -/* - * CLK_POL (RW) - * - * graphic clock polarity. - * set to invert input graphic clock - */ -#define GWC_GLB_CTRL_CLK_POL_MASK (0x80U) -#define GWC_GLB_CTRL_CLK_POL_SHIFT (7U) -#define GWC_GLB_CTRL_CLK_POL_SET(x) (((uint32_t)(x) << GWC_GLB_CTRL_CLK_POL_SHIFT) & GWC_GLB_CTRL_CLK_POL_MASK) -#define GWC_GLB_CTRL_CLK_POL_GET(x) (((uint32_t)(x) & GWC_GLB_CTRL_CLK_POL_MASK) >> GWC_GLB_CTRL_CLK_POL_SHIFT) - -/* - * GWC_EN (RW) - * - * graphic window check enable. - * set to enable the whole block - */ -#define GWC_GLB_CTRL_GWC_EN_MASK (0x1U) -#define GWC_GLB_CTRL_GWC_EN_SHIFT (0U) -#define GWC_GLB_CTRL_GWC_EN_SET(x) (((uint32_t)(x) << GWC_GLB_CTRL_GWC_EN_SHIFT) & GWC_GLB_CTRL_GWC_EN_MASK) -#define GWC_GLB_CTRL_GWC_EN_GET(x) (((uint32_t)(x) & GWC_GLB_CTRL_GWC_EN_MASK) >> GWC_GLB_CTRL_GWC_EN_SHIFT) - -/* Bitfield definition for register: IRQ_MASK */ -/* - * MASK_RREEZ (RW) - * - * freeze mask, set to disable changing ERR_MASK and FUNC_MASK. - * can only be cleared by system reset - */ -#define GWC_IRQ_MASK_MASK_RREEZ_MASK (0x8U) -#define GWC_IRQ_MASK_MASK_RREEZ_SHIFT (3U) -#define GWC_IRQ_MASK_MASK_RREEZ_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_MASK_RREEZ_SHIFT) & GWC_IRQ_MASK_MASK_RREEZ_MASK) -#define GWC_IRQ_MASK_MASK_RREEZ_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_MASK_RREEZ_MASK) >> GWC_IRQ_MASK_MASK_RREEZ_SHIFT) - -/* - * FUNC_MASK (RW) - * - * function interrupt mask - */ -#define GWC_IRQ_MASK_FUNC_MASK_MASK (0x2U) -#define GWC_IRQ_MASK_FUNC_MASK_SHIFT (1U) -#define GWC_IRQ_MASK_FUNC_MASK_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_FUNC_MASK_SHIFT) & GWC_IRQ_MASK_FUNC_MASK_MASK) -#define GWC_IRQ_MASK_FUNC_MASK_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_FUNC_MASK_MASK) >> GWC_IRQ_MASK_FUNC_MASK_SHIFT) - -/* - * ERR_MASK (RW) - * - * error interrupt mask - */ -#define GWC_IRQ_MASK_ERR_MASK_MASK (0x1U) -#define GWC_IRQ_MASK_ERR_MASK_SHIFT (0U) -#define GWC_IRQ_MASK_ERR_MASK_SET(x) (((uint32_t)(x) << GWC_IRQ_MASK_ERR_MASK_SHIFT) & GWC_IRQ_MASK_ERR_MASK_MASK) -#define GWC_IRQ_MASK_ERR_MASK_GET(x) (((uint32_t)(x) & GWC_IRQ_MASK_ERR_MASK_MASK) >> GWC_IRQ_MASK_ERR_MASK_SHIFT) - -/* Bitfield definition for register: IRQ_STS */ -/* - * FUNC_STS (W1C) - * - * function interrupt status. - * it's set when detect two VSYNC signals after the block is enabled(GWC_EN is set) - * software write 1 to clear. - */ -#define GWC_IRQ_STS_FUNC_STS_MASK (0x20000UL) -#define GWC_IRQ_STS_FUNC_STS_SHIFT (17U) -#define GWC_IRQ_STS_FUNC_STS_SET(x) (((uint32_t)(x) << GWC_IRQ_STS_FUNC_STS_SHIFT) & GWC_IRQ_STS_FUNC_STS_MASK) -#define GWC_IRQ_STS_FUNC_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_FUNC_STS_MASK) >> GWC_IRQ_STS_FUNC_STS_SHIFT) - -/* - * ERR_STS (RO) - * - * error status, it's OR of GWC_FAIL_STS[15:0] - */ -#define GWC_IRQ_STS_ERR_STS_MASK (0x10000UL) -#define GWC_IRQ_STS_ERR_STS_SHIFT (16U) -#define GWC_IRQ_STS_ERR_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_ERR_STS_MASK) >> GWC_IRQ_STS_ERR_STS_SHIFT) - -/* - * GWC_FAIL_STS (W1C) - * - * graphic window check fail interrupt status. - * will be set if the calculated CRC not equal reference CRC. - * one bit for each channel. - * software write 1 to clear. - */ -#define GWC_IRQ_STS_GWC_FAIL_STS_MASK (0xFFFFU) -#define GWC_IRQ_STS_GWC_FAIL_STS_SHIFT (0U) -#define GWC_IRQ_STS_GWC_FAIL_STS_SET(x) (((uint32_t)(x) << GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) -#define GWC_IRQ_STS_GWC_FAIL_STS_GET(x) (((uint32_t)(x) & GWC_IRQ_STS_GWC_FAIL_STS_MASK) >> GWC_IRQ_STS_GWC_FAIL_STS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CFG0 */ -/* - * ENABLE (RW) - * - * channel enable - */ -#define GWC_CHANNEL_CFG0_ENABLE_MASK (0x80000000UL) -#define GWC_CHANNEL_CFG0_ENABLE_SHIFT (31U) -#define GWC_CHANNEL_CFG0_ENABLE_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_ENABLE_SHIFT) & GWC_CHANNEL_CFG0_ENABLE_MASK) -#define GWC_CHANNEL_CFG0_ENABLE_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_ENABLE_MASK) >> GWC_CHANNEL_CFG0_ENABLE_SHIFT) - -/* - * FREEZE (RW) - * - * freeze config. set to freeze all other config registers for current channel. - * can only be cleared by system reset - */ -#define GWC_CHANNEL_CFG0_FREEZE_MASK (0x40000000UL) -#define GWC_CHANNEL_CFG0_FREEZE_SHIFT (30U) -#define GWC_CHANNEL_CFG0_FREEZE_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_FREEZE_SHIFT) & GWC_CHANNEL_CFG0_FREEZE_MASK) -#define GWC_CHANNEL_CFG0_FREEZE_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_FREEZE_MASK) >> GWC_CHANNEL_CFG0_FREEZE_SHIFT) - -/* - * START_ROW (RW) - * - * define the window start row number - */ -#define GWC_CHANNEL_CFG0_START_ROW_MASK (0xFFF0000UL) -#define GWC_CHANNEL_CFG0_START_ROW_SHIFT (16U) -#define GWC_CHANNEL_CFG0_START_ROW_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_ROW_SHIFT) & GWC_CHANNEL_CFG0_START_ROW_MASK) -#define GWC_CHANNEL_CFG0_START_ROW_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_ROW_MASK) >> GWC_CHANNEL_CFG0_START_ROW_SHIFT) - -/* - * START_COL (RW) - * - * define the window start column number - */ -#define GWC_CHANNEL_CFG0_START_COL_MASK (0x1FFFU) -#define GWC_CHANNEL_CFG0_START_COL_SHIFT (0U) -#define GWC_CHANNEL_CFG0_START_COL_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG0_START_COL_SHIFT) & GWC_CHANNEL_CFG0_START_COL_MASK) -#define GWC_CHANNEL_CFG0_START_COL_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG0_START_COL_MASK) >> GWC_CHANNEL_CFG0_START_COL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CFG1 */ -/* - * END_ROW (RW) - * - * define the window end row number - */ -#define GWC_CHANNEL_CFG1_END_ROW_MASK (0xFFF0000UL) -#define GWC_CHANNEL_CFG1_END_ROW_SHIFT (16U) -#define GWC_CHANNEL_CFG1_END_ROW_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_ROW_SHIFT) & GWC_CHANNEL_CFG1_END_ROW_MASK) -#define GWC_CHANNEL_CFG1_END_ROW_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_ROW_MASK) >> GWC_CHANNEL_CFG1_END_ROW_SHIFT) - -/* - * END_COL (RW) - * - * define the window end column number - */ -#define GWC_CHANNEL_CFG1_END_COL_MASK (0x1FFFU) -#define GWC_CHANNEL_CFG1_END_COL_SHIFT (0U) -#define GWC_CHANNEL_CFG1_END_COL_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CFG1_END_COL_SHIFT) & GWC_CHANNEL_CFG1_END_COL_MASK) -#define GWC_CHANNEL_CFG1_END_COL_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CFG1_END_COL_MASK) >> GWC_CHANNEL_CFG1_END_COL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: REFCRC */ -/* - * REF_CRC (RW) - * - * reference CRC - * polynomial function: 0x104C11DB7 - */ -#define GWC_CHANNEL_REFCRC_REF_CRC_MASK (0xFFFFFFFFUL) -#define GWC_CHANNEL_REFCRC_REF_CRC_SHIFT (0U) -#define GWC_CHANNEL_REFCRC_REF_CRC_SET(x) (((uint32_t)(x) << GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) -#define GWC_CHANNEL_REFCRC_REF_CRC_GET(x) (((uint32_t)(x) & GWC_CHANNEL_REFCRC_REF_CRC_MASK) >> GWC_CHANNEL_REFCRC_REF_CRC_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CALCRC */ -/* - * CAL_CRC (RW) - * - * calculated CRC for last frame - */ -#define GWC_CHANNEL_CALCRC_CAL_CRC_MASK (0xFFFFFFFFUL) -#define GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT (0U) -#define GWC_CHANNEL_CALCRC_CAL_CRC_SET(x) (((uint32_t)(x) << GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) -#define GWC_CHANNEL_CALCRC_CAL_CRC_GET(x) (((uint32_t)(x) & GWC_CHANNEL_CALCRC_CAL_CRC_MASK) >> GWC_CHANNEL_CALCRC_CAL_CRC_SHIFT) - - - -/* CHANNEL register group index macro definition */ -#define GWC_CHANNEL_CH0 (0UL) -#define GWC_CHANNEL_CH15 (15UL) - - -#endif /* HPM_GWC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_i2c_regs.h deleted file mode 100644 index 1446ec912e7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_i2c_regs.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2C_H -#define HPM_I2C_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ - __RW uint32_t STATUS; /* 0x18: Status Register */ - __RW uint32_t ADDR; /* 0x1C: Address Register */ - __RW uint32_t DATA; /* 0x20: Data Register */ - __RW uint32_t CTRL; /* 0x24: Control Register */ - __RW uint32_t CMD; /* 0x28: Command Register */ - __RW uint32_t SETUP; /* 0x2C: Setup Register */ - __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ -} I2C_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * FIFO Size: - * 0: 2 bytes - * 1: 4 bytes - * 2: 8 bytes - * 3: 16 bytes - */ -#define I2C_CFG_FIFOSIZE_MASK (0x3U) -#define I2C_CFG_FIFOSIZE_SHIFT (0U) -#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * CMPL (RW) - * - * Set to enable the Completion Interrupt. - * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. - * Slave: interrupts when a transaction addressing the controller is completed. - */ -#define I2C_INTEN_CMPL_MASK (0x200U) -#define I2C_INTEN_CMPL_SHIFT (9U) -#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) -#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) - -/* - * BYTERECV (RW) - * - * Set to enable the Byte Receive Interrupt. - * Interrupts when a byte of data is received - * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - */ -#define I2C_INTEN_BYTERECV_MASK (0x100U) -#define I2C_INTEN_BYTERECV_SHIFT (8U) -#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) -#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) - -/* - * BYTETRANS (RW) - * - * Set to enable the Byte Transmit Interrupt. - * Interrupts when a byte of data is transmitted. - */ -#define I2C_INTEN_BYTETRANS_MASK (0x80U) -#define I2C_INTEN_BYTETRANS_SHIFT (7U) -#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) -#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) - -/* - * START (RW) - * - * Set to enable the START Condition Interrupt. - * Interrupts when a START condition/repeated START condition is detected. - */ -#define I2C_INTEN_START_MASK (0x40U) -#define I2C_INTEN_START_SHIFT (6U) -#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) -#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) - -/* - * STOP (RW) - * - * Set to enable the STOP Condition Interrupt - * Interrupts when a STOP condition is detected. - */ -#define I2C_INTEN_STOP_MASK (0x20U) -#define I2C_INTEN_STOP_SHIFT (5U) -#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) -#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) - -/* - * ARBLOSE (RW) - * - * Set to enable the Arbitration Lose Interrupt. - * Master: interrupts when the controller loses the bus arbitration - * Slave: not available in this mode. - */ -#define I2C_INTEN_ARBLOSE_MASK (0x10U) -#define I2C_INTEN_ARBLOSE_SHIFT (4U) -#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) -#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) - -/* - * ADDRHIT (RW) - * - * Set to enable the Address Hit Interrupt. - * Master: interrupts when the addressed slave returned an ACK. - * Slave: interrupts when the controller is addressed. - */ -#define I2C_INTEN_ADDRHIT_MASK (0x8U) -#define I2C_INTEN_ADDRHIT_SHIFT (3U) -#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) -#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RW) - * - * Set to enable the FIFO Half Interrupt. - * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. - * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. - * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - */ -#define I2C_INTEN_FIFOHALF_MASK (0x4U) -#define I2C_INTEN_FIFOHALF_SHIFT (2U) -#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) -#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RW) - * - * Set to enable the FIFO Full Interrupt. - * Interrupts when the FIFO is full. - */ -#define I2C_INTEN_FIFOFULL_MASK (0x2U) -#define I2C_INTEN_FIFOFULL_SHIFT (1U) -#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) -#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RW) - * - * Set to enabled the FIFO Empty Interrupt - * Interrupts when the FIFO is empty. - */ -#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) -#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) -#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) -#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * LINESDA (RO) - * - * Indicates the current status of the SDA line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESDA_MASK (0x4000U) -#define I2C_STATUS_LINESDA_SHIFT (14U) -#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) - -/* - * LINESCL (RO) - * - * Indicates the current status of the SCL line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESCL_MASK (0x2000U) -#define I2C_STATUS_LINESCL_SHIFT (13U) -#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) - -/* - * GENCALL (RO) - * - * Indicates that the address of the current transaction is a general call address: - * 1: General call - * 0: Not general call - */ -#define I2C_STATUS_GENCALL_MASK (0x1000U) -#define I2C_STATUS_GENCALL_SHIFT (12U) -#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) - -/* - * BUSBUSY (RO) - * - * Indicates that the bus is busy - * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus - * 1: Busy - * 0: Not busy - */ -#define I2C_STATUS_BUSBUSY_MASK (0x800U) -#define I2C_STATUS_BUSBUSY_SHIFT (11U) -#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) - -/* - * ACK (RO) - * - * Indicates the type of the last received/transmitted acknowledgement bit: - * 1: ACK - * 0: NACK - */ -#define I2C_STATUS_ACK_MASK (0x400U) -#define I2C_STATUS_ACK_SHIFT (10U) -#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) - -/* - * CMPL (W1C) - * - * Transaction Completion - * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration - * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - */ -#define I2C_STATUS_CMPL_MASK (0x200U) -#define I2C_STATUS_CMPL_SHIFT (9U) -#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) -#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) - -/* - * BYTERECV (W1C) - * - * Indicates that a byte of data has been received. - */ -#define I2C_STATUS_BYTERECV_MASK (0x100U) -#define I2C_STATUS_BYTERECV_SHIFT (8U) -#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) -#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) - -/* - * BYTETRANS (W1C) - * - * Indicates that a byte of data has been transmitted. - */ -#define I2C_STATUS_BYTETRANS_MASK (0x80U) -#define I2C_STATUS_BYTETRANS_SHIFT (7U) -#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) -#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) - -/* - * START (W1C) - * - * Indicates that a START Condition or a repeated START condition has been transmitted/received. - */ -#define I2C_STATUS_START_MASK (0x40U) -#define I2C_STATUS_START_SHIFT (6U) -#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) -#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) - -/* - * STOP (W1C) - * - * Indicates that a STOP Condition has been transmitted/received. - */ -#define I2C_STATUS_STOP_MASK (0x20U) -#define I2C_STATUS_STOP_SHIFT (5U) -#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) -#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) - -/* - * ARBLOSE (W1C) - * - * Indicates that the controller has lost the bus arbitration. - */ -#define I2C_STATUS_ARBLOSE_MASK (0x10U) -#define I2C_STATUS_ARBLOSE_SHIFT (4U) -#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) -#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) - -/* - * ADDRHIT (W1C) - * - * Master: indicates that a slave has responded to the transaction. - * Slave: indicates that a transaction is targeting the controller (including the General Call). - */ -#define I2C_STATUS_ADDRHIT_MASK (0x8U) -#define I2C_STATUS_ADDRHIT_SHIFT (3U) -#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) -#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RO) - * - * Transmitter: Indicates that the FIFO is half-empty. - */ -#define I2C_STATUS_FIFOHALF_MASK (0x4U) -#define I2C_STATUS_FIFOHALF_SHIFT (2U) -#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RO) - * - * Indicates that the FIFO is full. - */ -#define I2C_STATUS_FIFOFULL_MASK (0x2U) -#define I2C_STATUS_FIFOFULL_SHIFT (1U) -#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RO) - * - * Indicates that the FIFO is empty. - */ -#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) -#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) -#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * The slave address. - * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - */ -#define I2C_ADDR_ADDR_MASK (0x3FFU) -#define I2C_ADDR_ADDR_SHIFT (0U) -#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) -#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Write this register to put one byte of data to the FIFO. - * Read this register to get one byte of data from the FIFO. - */ -#define I2C_DATA_DATA_MASK (0xFFU) -#define I2C_DATA_DATA_SHIFT (0U) -#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) -#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * DATACNT_HIGH (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_HIGH_MASK (0xFF000000UL) -#define I2C_CTRL_DATACNT_HIGH_SHIFT (24U) -#define I2C_CTRL_DATACNT_HIGH_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_HIGH_SHIFT) & I2C_CTRL_DATACNT_HIGH_MASK) -#define I2C_CTRL_DATACNT_HIGH_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_HIGH_MASK) >> I2C_CTRL_DATACNT_HIGH_SHIFT) - -/* - * RESET_LEN (RW) - * - * reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - */ -#define I2C_CTRL_RESET_LEN_MASK (0xF00000UL) -#define I2C_CTRL_RESET_LEN_SHIFT (20U) -#define I2C_CTRL_RESET_LEN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_LEN_SHIFT) & I2C_CTRL_RESET_LEN_MASK) -#define I2C_CTRL_RESET_LEN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_LEN_MASK) >> I2C_CTRL_RESET_LEN_SHIFT) - -/* - * RESET_HOLD_SCKIN (RW) - * - * set to hold input clock to high when reset is active - */ -#define I2C_CTRL_RESET_HOLD_SCKIN_MASK (0x4000U) -#define I2C_CTRL_RESET_HOLD_SCKIN_SHIFT (14U) -#define I2C_CTRL_RESET_HOLD_SCKIN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) -#define I2C_CTRL_RESET_HOLD_SCKIN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) >> I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) - -/* - * RESET_ON (RW) - * - * set to send reset signals(just toggle clock bus defined by reset_len). - * this register is clered when reset is end, can't be cleared by software - */ -#define I2C_CTRL_RESET_ON_MASK (0x2000U) -#define I2C_CTRL_RESET_ON_SHIFT (13U) -#define I2C_CTRL_RESET_ON_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_ON_SHIFT) & I2C_CTRL_RESET_ON_MASK) -#define I2C_CTRL_RESET_ON_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_ON_MASK) >> I2C_CTRL_RESET_ON_SHIFT) - -/* - * PHASE_START (RW) - * - * Enable this bit to send a START condition at the beginning of transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_START_MASK (0x1000U) -#define I2C_CTRL_PHASE_START_SHIFT (12U) -#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) -#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) - -/* - * PHASE_ADDR (RW) - * - * Enable this bit to send the address after START condition. - * Master mode only. - */ -#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) -#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) -#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) -#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) - -/* - * PHASE_DATA (RW) - * - * Enable this bit to send the data after Address phase. - * Master mode only. - */ -#define I2C_CTRL_PHASE_DATA_MASK (0x400U) -#define I2C_CTRL_PHASE_DATA_SHIFT (10U) -#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) -#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) - -/* - * PHASE_STOP (RW) - * - * Enable this bit to send a STOP condition at the end of a transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_STOP_MASK (0x200U) -#define I2C_CTRL_PHASE_STOP_SHIFT (9U) -#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) -#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) - -/* - * DIR (RW) - * - * Transaction direction - * Master: Set this bit to determine the direction for the next transaction. - * 0: Transmitter - * 1: Receiver - * Slave: The direction of the last received transaction. - * 0: Receiver - * 1: Transmitter - */ -#define I2C_CTRL_DIR_MASK (0x100U) -#define I2C_CTRL_DIR_SHIFT (8U) -#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) -#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) - -/* - * DATACNT (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_MASK (0xFFU) -#define I2C_CTRL_DATACNT_SHIFT (0U) -#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) -#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * Write this register with the following values to perform the corresponding actions: - * 0x0: no action - * 0x1: issue a data transaction (Master only) - * 0x2: respond with an ACK to the received byte - * 0x3: respond with a NACK to the received byte - * 0x4: clear the FIFO - * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) - * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. - * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - */ -#define I2C_CMD_CMD_MASK (0x7U) -#define I2C_CMD_CMD_SHIFT (0U) -#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) -#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) - -/* Bitfield definition for register: SETUP */ -/* - * T_SUDAT (RW) - * - * T_SUDAT defines the data setup time before releasing the SCL. - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) - * tpclk = PCLK period - * TPM = The multiplier value in Timing Parameter Multiplier Register - */ -#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) -#define I2C_SETUP_T_SUDAT_SHIFT (24U) -#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) -#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) - -/* - * T_SP (RW) - * - * T_SP defines the pulse width of spikes that must be suppressed by the input filter. - * Pulse width = T_SP * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_SP_MASK (0xE00000UL) -#define I2C_SETUP_T_SP_SHIFT (21U) -#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) -#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) - -/* - * T_HDDAT (RW) - * - * T_HDDAT defines the data hold time after SCL goes LOW - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) -#define I2C_SETUP_T_HDDAT_SHIFT (16U) -#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) -#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) - -/* - * T_SCLRADIO (RW) - * - * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. - * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) - * 1: ratio = 2 - * 0: ratio = 1 - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) -#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) -#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) -#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) - -/* - * T_SCLHI (RW) - * - * The HIGH period of generated SCL clock is defined by T_SCLHi. - * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) - * The T_SCLHi value must be greater than T_SP and T_HDDAT values. - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) -#define I2C_SETUP_T_SCLHI_SHIFT (4U) -#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) -#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) - -/* - * DMAEN (RW) - * - * Enable the direct memory access mode data transfer. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_DMAEN_MASK (0x8U) -#define I2C_SETUP_DMAEN_SHIFT (3U) -#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) -#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) - -/* - * MASTER (RW) - * - * Configure this device as a master or a slave. - * 1: Master mode - * 0: Slave mode - */ -#define I2C_SETUP_MASTER_MASK (0x4U) -#define I2C_SETUP_MASTER_SHIFT (2U) -#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) -#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) - -/* - * ADDRESSING (RW) - * - * I2C addressing mode: - * 1: 10-bit addressing mode - * 0: 7-bit addressing mode - */ -#define I2C_SETUP_ADDRESSING_MASK (0x2U) -#define I2C_SETUP_ADDRESSING_SHIFT (1U) -#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) -#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) - -/* - * IICEN (RW) - * - * Enable the I2C controller. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_IICEN_MASK (0x1U) -#define I2C_SETUP_IICEN_SHIFT (0U) -#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) -#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) - -/* Bitfield definition for register: TPM */ -/* - * TPM (RW) - * - * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - */ -#define I2C_TPM_TPM_MASK (0x1FU) -#define I2C_TPM_TPM_SHIFT (0U) -#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) -#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) - - - - -#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_i2s_regs.h deleted file mode 100644 index 3d3b34d7aab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_i2s_regs.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2S_H -#define HPM_I2S_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint32_t RFIFO_FILLINGS; /* 0x4: Rx FIFO Filling Level */ - __R uint32_t TFIFO_FILLINGS; /* 0x8: Tx FIFO Filling Level */ - __RW uint32_t FIFO_THRESH; /* 0xC: TX/RX FIFO Threshold setting. */ - __RW uint32_t STA; /* 0x10: Status Registers */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXD[4]; /* 0x20 - 0x2C: Rx Data0 */ - __W uint32_t TXD[4]; /* 0x30 - 0x3C: Tx Data0 */ - __R uint8_t RESERVED1[16]; /* 0x40 - 0x4F: Reserved */ - __RW uint32_t CFGR; /* 0x50: Configruation Regsiters */ - __R uint8_t RESERVED2[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t MISC_CFGR; /* 0x58: Misc configuration Registers */ - __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */ - __RW uint32_t RXDSLOT[4]; /* 0x60 - 0x6C: Rx Slots Enable for Rx Data0 */ - __RW uint32_t TXDSLOT[4]; /* 0x70 - 0x7C: Tx Slots Enable for Tx Data0. */ -} I2S_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST_RX (RW) - * - * software reset the RX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_RX_MASK (0x40000UL) -#define I2S_CTRL_SFTRST_RX_SHIFT (18U) -#define I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK) -#define I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT) - -/* - * SFTRST_TX (RW) - * - * software reset the TX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_TX_MASK (0x20000UL) -#define I2S_CTRL_SFTRST_TX_SHIFT (17U) -#define I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK) -#define I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT) - -/* - * SFTRST_CLKGEN (RW) - * - * software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL) -#define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U) -#define I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK) -#define I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT) - -/* - * TXDNIE (RW) - * - * TX buffer data needed interrupt enable - * 0: TXE interrupt masked - * 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - */ -#define I2S_CTRL_TXDNIE_MASK (0x8000U) -#define I2S_CTRL_TXDNIE_SHIFT (15U) -#define I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK) -#define I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT) - -/* - * RXDAIE (RW) - * - * RX buffer data available interrupt enable - * 0: RXNE interrupt masked - * 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - */ -#define I2S_CTRL_RXDAIE_MASK (0x4000U) -#define I2S_CTRL_RXDAIE_SHIFT (14U) -#define I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK) -#define I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT) - -/* - * ERRIE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define I2S_CTRL_ERRIE_MASK (0x2000U) -#define I2S_CTRL_ERRIE_SHIFT (13U) -#define I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK) -#define I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT) - -/* - * TX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_TX_DMA_EN_MASK (0x1000U) -#define I2S_CTRL_TX_DMA_EN_SHIFT (12U) -#define I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK) -#define I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT) - -/* - * RX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_RX_DMA_EN_MASK (0x800U) -#define I2S_CTRL_RX_DMA_EN_SHIFT (11U) -#define I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK) -#define I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT) - -/* - * TXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_TXFIFOCLR_MASK (0x400U) -#define I2S_CTRL_TXFIFOCLR_SHIFT (10U) -#define I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK) -#define I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT) - -/* - * RXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_RXFIFOCLR_MASK (0x200U) -#define I2S_CTRL_RXFIFOCLR_SHIFT (9U) -#define I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK) -#define I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT) - -/* - * TX_EN (RW) - * - * enable for each TX data pad - */ -#define I2S_CTRL_TX_EN_MASK (0x1E0U) -#define I2S_CTRL_TX_EN_SHIFT (5U) -#define I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK) -#define I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT) - -/* - * RX_EN (RW) - * - * enable for each RX data pad - */ -#define I2S_CTRL_RX_EN_MASK (0x1EU) -#define I2S_CTRL_RX_EN_SHIFT (1U) -#define I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK) -#define I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT) - -/* - * I2S_EN (RW) - * - * enable for the module - */ -#define I2S_CTRL_I2S_EN_MASK (0x1U) -#define I2S_CTRL_I2S_EN_SHIFT (0U) -#define I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK) -#define I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT) - -/* Bitfield definition for register: RFIFO_FILLINGS */ -/* - * RX3 (RO) - * - * RX3 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL) -#define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U) -#define I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT) - -/* - * RX2 (RO) - * - * RX2 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL) -#define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U) -#define I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT) - -/* - * RX1 (RO) - * - * RX1 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U) -#define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U) -#define I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT) - -/* - * RX0 (RO) - * - * RX0 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU) -#define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U) -#define I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT) - -/* Bitfield definition for register: TFIFO_FILLINGS */ -/* - * TX3 (RO) - * - * TX3 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL) -#define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U) -#define I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT) - -/* - * TX2 (RO) - * - * TX2 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL) -#define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U) -#define I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT) - -/* - * TX1 (RO) - * - * TX1 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U) -#define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U) -#define I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT) - -/* - * TX0 (RO) - * - * TX0 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU) -#define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U) -#define I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT) - -/* Bitfield definition for register: FIFO_THRESH */ -/* - * TX (RW) - * - * TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - */ -#define I2S_FIFO_THRESH_TX_MASK (0xFF00U) -#define I2S_FIFO_THRESH_TX_SHIFT (8U) -#define I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK) -#define I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT) - -/* - * RX (RW) - * - * RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - */ -#define I2S_FIFO_THRESH_RX_MASK (0xFFU) -#define I2S_FIFO_THRESH_RX_SHIFT (0U) -#define I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK) -#define I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TX_UD (W1C) - * - * Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - */ -#define I2S_STA_TX_UD_MASK (0x1E000UL) -#define I2S_STA_TX_UD_SHIFT (13U) -#define I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK) -#define I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT) - -/* - * RX_OV (W1C) - * - * Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - */ -#define I2S_STA_RX_OV_MASK (0x1E00U) -#define I2S_STA_RX_OV_SHIFT (9U) -#define I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK) -#define I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT) - -/* - * TX_DN (RO) - * - * Asserted when tx fifo data are needed. - */ -#define I2S_STA_TX_DN_MASK (0x1E0U) -#define I2S_STA_TX_DN_SHIFT (5U) -#define I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT) - -/* - * RX_DA (RO) - * - * Asserted when rx fifo data are available. - */ -#define I2S_STA_RX_DA_MASK (0x1EU) -#define I2S_STA_RX_DA_SHIFT (1U) -#define I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT) - -/* Bitfield definition for register array: RXD */ -/* - * D (RO) - * - */ -#define I2S_RXD_D_MASK (0xFFFFFFFFUL) -#define I2S_RXD_D_SHIFT (0U) -#define I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT) - -/* Bitfield definition for register array: TXD */ -/* - * D (WO) - * - */ -#define I2S_TXD_D_MASK (0xFFFFFFFFUL) -#define I2S_TXD_D_SHIFT (0U) -#define I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK) -#define I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT) - -/* Bitfield definition for register: CFGR */ -/* - * BCLK_GATEOFF (RW) - * - * Gate off the bclk. Asserted to gate-off the BCLK. - */ -#define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL) -#define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U) -#define I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK) -#define I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT) - -/* - * BCLK_DIV (RW) - * - * Linear prescaler to generate BCLK from MCLK. - * BCLK_DIV [8:0] = 0: BCLK=No CLK. - * BCLK_DIV [8:0] = 1: BCLK=MCLK/1 - * BCLK_DIV [8:0] = n: BCLK=MCLK/(n). - * Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL) -#define I2S_CFGR_BCLK_DIV_SHIFT (21U) -#define I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK) -#define I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT) - -/* - * INV_BCLK_OUT (RW) - * - * Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - */ -#define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL) -#define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U) -#define I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK) -#define I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT) - -/* - * INV_BCLK_IN (RW) - * - * Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - */ -#define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL) -#define I2S_CFGR_INV_BCLK_IN_SHIFT (19U) -#define I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK) -#define I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT) - -/* - * INV_FCLK_OUT (RW) - * - * Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - */ -#define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL) -#define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U) -#define I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK) -#define I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT) - -/* - * INV_FCLK_IN (RW) - * - * Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - */ -#define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL) -#define I2S_CFGR_INV_FCLK_IN_SHIFT (17U) -#define I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK) -#define I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT) - -/* - * INV_MCLK_OUT (RW) - * - * Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - */ -#define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL) -#define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U) -#define I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK) -#define I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT) - -/* - * INV_MCLK_IN (RW) - * - * Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - */ -#define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U) -#define I2S_CFGR_INV_MCLK_IN_SHIFT (15U) -#define I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK) -#define I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT) - -/* - * BCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U) -#define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U) -#define I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK) -#define I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT) - -/* - * FCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U) -#define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U) -#define I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK) -#define I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT) - -/* - * MCK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U) -#define I2S_CFGR_MCK_SEL_OP_SHIFT (12U) -#define I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK) -#define I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT) - -/* - * FRAME_EDGE (RW) - * - * The start edge of a frame - * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) - * 1: Rising edge indicates a new frame - */ -#define I2S_CFGR_FRAME_EDGE_MASK (0x800U) -#define I2S_CFGR_FRAME_EDGE_SHIFT (11U) -#define I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK) -#define I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT) - -/* - * CH_MAX (RW) - * - * CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 5'h2: 2 channels - * 5'h4: 4 channels - * ... - * 5‘h10: 16 channels (max) - */ -#define I2S_CFGR_CH_MAX_MASK (0x7C0U) -#define I2S_CFGR_CH_MAX_SHIFT (6U) -#define I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK) -#define I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT) - -/* - * TDM_EN (RW) - * - * TDM mode - * 0: not TDM mode - * 1: TDM mode - */ -#define I2S_CFGR_TDM_EN_MASK (0x20U) -#define I2S_CFGR_TDM_EN_SHIFT (5U) -#define I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK) -#define I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT) - -/* - * STD (RW) - * - * I2S standard selection - * 00: I2S Philips standard. - * 01: MSB justified standard (left justified) - * 10: LSB justified standard (right justified) - * 11: PCM standard - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_STD_MASK (0x18U) -#define I2S_CFGR_STD_SHIFT (3U) -#define I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK) -#define I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT) - -/* - * DATSIZ (RW) - * - * Data length to be transferred - * 00: 16-bit data length - * 01: 24-bit data length - * 10: 32-bit data length - * 11: Not allowed - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_DATSIZ_MASK (0x6U) -#define I2S_CFGR_DATSIZ_SHIFT (1U) -#define I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK) -#define I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT) - -/* - * CHSIZ (RW) - * - * Channel length (number of bits per audio channel) - * 0: 16-bit wide - * 1: 32-bit wide - * The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. - * Note: For correct operation, this bit should be configured when the I2S is disabled. - */ -#define I2S_CFGR_CHSIZ_MASK (0x1U) -#define I2S_CFGR_CHSIZ_SHIFT (0U) -#define I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK) -#define I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT) - -/* Bitfield definition for register: MISC_CFGR */ -/* - * MCLK_GATEOFF (RW) - * - * Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - */ -#define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) -#define I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) - -/* - * MCLKOE (RW) - * - * Master clock output to pad enable - * 0: Master clock output is disabled - * 1: Master clock output is enabled - * Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_MISC_CFGR_MCLKOE_MASK (0x1U) -#define I2S_MISC_CFGR_MCLKOE_SHIFT (0U) -#define I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK) -#define I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT) - -/* Bitfield definition for register array: RXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_RXDSLOT_EN_MASK (0xFFFFU) -#define I2S_RXDSLOT_EN_SHIFT (0U) -#define I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK) -#define I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT) - -/* Bitfield definition for register array: TXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_TXDSLOT_EN_MASK (0xFFFFU) -#define I2S_TXDSLOT_EN_SHIFT (0U) -#define I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK) -#define I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT) - - - -/* RXD register group index macro definition */ -#define I2S_RXD_DATA0 (0UL) -#define I2S_RXD_DATA1 (1UL) -#define I2S_RXD_DATA2 (2UL) -#define I2S_RXD_DATA3 (3UL) - -/* TXD register group index macro definition */ -#define I2S_TXD_DATA0 (0UL) -#define I2S_TXD_DATA1 (1UL) -#define I2S_TXD_DATA2 (2UL) -#define I2S_TXD_DATA3 (3UL) - -/* RXDSLOT register group index macro definition */ -#define I2S_RXDSLOT_DATA0 (0UL) -#define I2S_RXDSLOT_DATA1 (1UL) -#define I2S_RXDSLOT_DATA2 (2UL) -#define I2S_RXDSLOT_DATA3 (3UL) - -/* TXDSLOT register group index macro definition */ -#define I2S_TXDSLOT_DATA0 (0UL) -#define I2S_TXDSLOT_DATA1 (1UL) -#define I2S_TXDSLOT_DATA2 (2UL) -#define I2S_TXDSLOT_DATA3 (3UL) - - -#endif /* HPM_I2S_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ioc_regs.h deleted file mode 100644 index 26042597d8c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ioc_regs.h +++ /dev/null @@ -1,419 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOC_H -#define HPM_IOC_H - -typedef struct { - struct { - __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ - __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[496]; -} IOC_Type; - - -/* Bitfield definition for register of struct array PAD: FUNC_CTL */ -/* - * LOOP_BACK (RW) - * - * force input on - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) - -/* - * ANALOG (RW) - * - * select analog pin in pad - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) -#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) -#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) -#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) - -/* - * ALT_SELECT (RW) - * - * alt select - * 0: ALT0 - * 1: ALT1 - * ... - * 31:ALT31 - */ -#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) - -/* Bitfield definition for register of struct array PAD: PAD_CTL */ -/* - * HYS (RW) - * - * schmitt trigger enable - * 0: disable - * 1: enable - */ -#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) -#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) -#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) -#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) - -/* - * PRS (RW) - * - * select pull up/down internal resistance strength: - * For pull down, only have 100 Kohm resistance - * For pull up: - * 00: 100 KOhm - * 01: 47 KOhm - * 10: 22 KOhm - * 11: 22 KOhm - */ -#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) -#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) -#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) -#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) - -/* - * PS (RW) - * - * pull select - * 0: pull down - * 1: pull up - */ -#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) -#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) -#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) -#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) - -/* - * PE (RW) - * - * pull enable - * 0: pull disable - * 1: pull enable - */ -#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) -#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) -#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) -#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) - -/* - * KE (RW) - * - * keeper capability enable - * 0: keeper disable - * 1: keeper enable - */ -#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) -#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) -#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) -#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) - -/* - * OD (RW) - * - * open drain - * 0: open drain disable - * 1: open drain enable - */ -#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) -#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) -#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) -#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) - -/* - * SR (RW) - * - * slew rate - * 0: Slow slew rate - * 1: Fast slew rate - */ -#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) -#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) -#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) -#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) - -/* - * SPD (RW) - * - * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise - * 00: Slow frequency slew rate(50Mhz) - * 01: Medium frequency slew rate(100 Mhz) - * 10: Fast frequency slew rate(150 Mhz) - * 11: Max frequency slew rate(200Mhz) - */ -#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) -#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) -#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) -#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) - -/* - * DS (RW) - * - * drive strength - * 1.8V Mode: - * 000: 260 Ohm - * 001: 260 Ohm - * 010: 130 Ohm - * 011: 88 Ohm - * 100: 65 Ohm - * 101: 52 Ohm - * 110: 43 Ohm - * 111: 37 Ohm - * 3.3V Mode: - * 000: 157 Ohm - * 001: 157 Ohm - * 010: 78 Ohm - * 011: 53 Ohm - * 100: 39 Ohm - * 101: 32 Ohm - * 110: 26 Ohm - * 111: 23 Ohm - */ -#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) -#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) -#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) -#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) - - - -/* PAD register group index macro definition */ -#define IOC_PAD_PA00 (0UL) -#define IOC_PAD_PA01 (1UL) -#define IOC_PAD_PA02 (2UL) -#define IOC_PAD_PA03 (3UL) -#define IOC_PAD_PA04 (4UL) -#define IOC_PAD_PA05 (5UL) -#define IOC_PAD_PA06 (6UL) -#define IOC_PAD_PA07 (7UL) -#define IOC_PAD_PA08 (8UL) -#define IOC_PAD_PA09 (9UL) -#define IOC_PAD_PA10 (10UL) -#define IOC_PAD_PA11 (11UL) -#define IOC_PAD_PA12 (12UL) -#define IOC_PAD_PA13 (13UL) -#define IOC_PAD_PA14 (14UL) -#define IOC_PAD_PA15 (15UL) -#define IOC_PAD_PA16 (16UL) -#define IOC_PAD_PA17 (17UL) -#define IOC_PAD_PA18 (18UL) -#define IOC_PAD_PA19 (19UL) -#define IOC_PAD_PA20 (20UL) -#define IOC_PAD_PA21 (21UL) -#define IOC_PAD_PA22 (22UL) -#define IOC_PAD_PA23 (23UL) -#define IOC_PAD_PA24 (24UL) -#define IOC_PAD_PA25 (25UL) -#define IOC_PAD_PA26 (26UL) -#define IOC_PAD_PA27 (27UL) -#define IOC_PAD_PA28 (28UL) -#define IOC_PAD_PA29 (29UL) -#define IOC_PAD_PA30 (30UL) -#define IOC_PAD_PA31 (31UL) -#define IOC_PAD_PB00 (32UL) -#define IOC_PAD_PB01 (33UL) -#define IOC_PAD_PB02 (34UL) -#define IOC_PAD_PB03 (35UL) -#define IOC_PAD_PB04 (36UL) -#define IOC_PAD_PB05 (37UL) -#define IOC_PAD_PB06 (38UL) -#define IOC_PAD_PB07 (39UL) -#define IOC_PAD_PB08 (40UL) -#define IOC_PAD_PB09 (41UL) -#define IOC_PAD_PB10 (42UL) -#define IOC_PAD_PB11 (43UL) -#define IOC_PAD_PB12 (44UL) -#define IOC_PAD_PB13 (45UL) -#define IOC_PAD_PB14 (46UL) -#define IOC_PAD_PB15 (47UL) -#define IOC_PAD_PB16 (48UL) -#define IOC_PAD_PB17 (49UL) -#define IOC_PAD_PB18 (50UL) -#define IOC_PAD_PB19 (51UL) -#define IOC_PAD_PB20 (52UL) -#define IOC_PAD_PB21 (53UL) -#define IOC_PAD_PB22 (54UL) -#define IOC_PAD_PB23 (55UL) -#define IOC_PAD_PB24 (56UL) -#define IOC_PAD_PB25 (57UL) -#define IOC_PAD_PB26 (58UL) -#define IOC_PAD_PB27 (59UL) -#define IOC_PAD_PB28 (60UL) -#define IOC_PAD_PB29 (61UL) -#define IOC_PAD_PB30 (62UL) -#define IOC_PAD_PB31 (63UL) -#define IOC_PAD_PC00 (64UL) -#define IOC_PAD_PC01 (65UL) -#define IOC_PAD_PC02 (66UL) -#define IOC_PAD_PC03 (67UL) -#define IOC_PAD_PC04 (68UL) -#define IOC_PAD_PC05 (69UL) -#define IOC_PAD_PC06 (70UL) -#define IOC_PAD_PC07 (71UL) -#define IOC_PAD_PC08 (72UL) -#define IOC_PAD_PC09 (73UL) -#define IOC_PAD_PC10 (74UL) -#define IOC_PAD_PC11 (75UL) -#define IOC_PAD_PC12 (76UL) -#define IOC_PAD_PC13 (77UL) -#define IOC_PAD_PC14 (78UL) -#define IOC_PAD_PC15 (79UL) -#define IOC_PAD_PC16 (80UL) -#define IOC_PAD_PC17 (81UL) -#define IOC_PAD_PC18 (82UL) -#define IOC_PAD_PC19 (83UL) -#define IOC_PAD_PC20 (84UL) -#define IOC_PAD_PC21 (85UL) -#define IOC_PAD_PC22 (86UL) -#define IOC_PAD_PC23 (87UL) -#define IOC_PAD_PC24 (88UL) -#define IOC_PAD_PC25 (89UL) -#define IOC_PAD_PC26 (90UL) -#define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PC28 (92UL) -#define IOC_PAD_PC29 (93UL) -#define IOC_PAD_PC30 (94UL) -#define IOC_PAD_PC31 (95UL) -#define IOC_PAD_PD00 (96UL) -#define IOC_PAD_PD01 (97UL) -#define IOC_PAD_PD02 (98UL) -#define IOC_PAD_PD03 (99UL) -#define IOC_PAD_PD04 (100UL) -#define IOC_PAD_PD05 (101UL) -#define IOC_PAD_PD06 (102UL) -#define IOC_PAD_PD07 (103UL) -#define IOC_PAD_PD08 (104UL) -#define IOC_PAD_PD09 (105UL) -#define IOC_PAD_PD10 (106UL) -#define IOC_PAD_PD11 (107UL) -#define IOC_PAD_PD12 (108UL) -#define IOC_PAD_PD13 (109UL) -#define IOC_PAD_PD14 (110UL) -#define IOC_PAD_PD15 (111UL) -#define IOC_PAD_PD16 (112UL) -#define IOC_PAD_PD17 (113UL) -#define IOC_PAD_PD18 (114UL) -#define IOC_PAD_PD19 (115UL) -#define IOC_PAD_PD20 (116UL) -#define IOC_PAD_PD21 (117UL) -#define IOC_PAD_PD22 (118UL) -#define IOC_PAD_PD23 (119UL) -#define IOC_PAD_PD24 (120UL) -#define IOC_PAD_PD25 (121UL) -#define IOC_PAD_PD26 (122UL) -#define IOC_PAD_PD27 (123UL) -#define IOC_PAD_PD28 (124UL) -#define IOC_PAD_PD29 (125UL) -#define IOC_PAD_PD30 (126UL) -#define IOC_PAD_PD31 (127UL) -#define IOC_PAD_PE00 (128UL) -#define IOC_PAD_PE01 (129UL) -#define IOC_PAD_PE02 (130UL) -#define IOC_PAD_PE03 (131UL) -#define IOC_PAD_PE04 (132UL) -#define IOC_PAD_PE05 (133UL) -#define IOC_PAD_PE06 (134UL) -#define IOC_PAD_PE07 (135UL) -#define IOC_PAD_PE08 (136UL) -#define IOC_PAD_PE09 (137UL) -#define IOC_PAD_PE10 (138UL) -#define IOC_PAD_PE11 (139UL) -#define IOC_PAD_PE12 (140UL) -#define IOC_PAD_PE13 (141UL) -#define IOC_PAD_PE14 (142UL) -#define IOC_PAD_PE15 (143UL) -#define IOC_PAD_PE16 (144UL) -#define IOC_PAD_PE17 (145UL) -#define IOC_PAD_PE18 (146UL) -#define IOC_PAD_PE19 (147UL) -#define IOC_PAD_PE20 (148UL) -#define IOC_PAD_PE21 (149UL) -#define IOC_PAD_PE22 (150UL) -#define IOC_PAD_PE23 (151UL) -#define IOC_PAD_PE24 (152UL) -#define IOC_PAD_PE25 (153UL) -#define IOC_PAD_PE26 (154UL) -#define IOC_PAD_PE27 (155UL) -#define IOC_PAD_PE28 (156UL) -#define IOC_PAD_PE29 (157UL) -#define IOC_PAD_PE30 (158UL) -#define IOC_PAD_PE31 (159UL) -#define IOC_PAD_PF00 (160UL) -#define IOC_PAD_PF01 (161UL) -#define IOC_PAD_PF02 (162UL) -#define IOC_PAD_PF03 (163UL) -#define IOC_PAD_PF04 (164UL) -#define IOC_PAD_PF05 (165UL) -#define IOC_PAD_PF06 (166UL) -#define IOC_PAD_PF07 (167UL) -#define IOC_PAD_PF08 (168UL) -#define IOC_PAD_PF09 (169UL) -#define IOC_PAD_PF10 (170UL) -#define IOC_PAD_PF11 (171UL) -#define IOC_PAD_PF12 (172UL) -#define IOC_PAD_PF13 (173UL) -#define IOC_PAD_PF14 (174UL) -#define IOC_PAD_PF15 (175UL) -#define IOC_PAD_PX00 (416UL) -#define IOC_PAD_PX01 (417UL) -#define IOC_PAD_PX02 (418UL) -#define IOC_PAD_PX03 (419UL) -#define IOC_PAD_PX04 (420UL) -#define IOC_PAD_PX05 (421UL) -#define IOC_PAD_PX06 (422UL) -#define IOC_PAD_PX07 (423UL) -#define IOC_PAD_PX08 (424UL) -#define IOC_PAD_PX09 (425UL) -#define IOC_PAD_PX10 (426UL) -#define IOC_PAD_PX11 (427UL) -#define IOC_PAD_PX12 (428UL) -#define IOC_PAD_PX13 (429UL) -#define IOC_PAD_PX14 (430UL) -#define IOC_PAD_PX15 (431UL) -#define IOC_PAD_PY00 (448UL) -#define IOC_PAD_PY01 (449UL) -#define IOC_PAD_PY02 (450UL) -#define IOC_PAD_PY03 (451UL) -#define IOC_PAD_PY04 (452UL) -#define IOC_PAD_PY05 (453UL) -#define IOC_PAD_PY06 (454UL) -#define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PY08 (456UL) -#define IOC_PAD_PY09 (457UL) -#define IOC_PAD_PY10 (458UL) -#define IOC_PAD_PY11 (459UL) -#define IOC_PAD_PY12 (460UL) -#define IOC_PAD_PY13 (461UL) -#define IOC_PAD_PY14 (462UL) -#define IOC_PAD_PY15 (463UL) -#define IOC_PAD_PZ00 (480UL) -#define IOC_PAD_PZ01 (481UL) -#define IOC_PAD_PZ02 (482UL) -#define IOC_PAD_PZ03 (483UL) -#define IOC_PAD_PZ04 (484UL) -#define IOC_PAD_PZ05 (485UL) -#define IOC_PAD_PZ06 (486UL) -#define IOC_PAD_PZ07 (487UL) -#define IOC_PAD_PZ08 (488UL) -#define IOC_PAD_PZ09 (489UL) -#define IOC_PAD_PZ10 (490UL) -#define IOC_PAD_PZ11 (491UL) -#define IOC_PAD_PZ12 (492UL) -#define IOC_PAD_PZ13 (493UL) -#define IOC_PAD_PZ14 (494UL) -#define IOC_PAD_PZ15 (495UL) - - -#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_jpeg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_jpeg_regs.h deleted file mode 100644 index d29fe23e5c4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_jpeg_regs.h +++ /dev/null @@ -1,1095 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_JPEG_H -#define HPM_JPEG_H - -typedef struct { - __RW uint32_t INDMA_MISC; /* 0x0: In DMA Misc Control Register */ - __RW uint32_t INDMABASE; /* 0x4: In DMA Buf Address */ - __R uint8_t RESERVED0[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t INDMA_CTRL0; /* 0xC: In DMA Buf Control 0 Register */ - __RW uint32_t INDMA_CTRL1; /* 0x10: In DMA Buf Control 1 Register */ - __RW uint32_t INXT_CMD; /* 0x14: In DMA Next Command Register */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t OUTDMA_MISC; /* 0x20: Out DMA Misc Control Register */ - __RW uint32_t OUTDMABASE; /* 0x24: Out DMA Buf Address */ - __R uint8_t RESERVED2[4]; /* 0x28 - 0x2B: Reserved */ - __RW uint32_t OUTDMA_CTRL0; /* 0x2C: Out DMA Buf Control 0 Register */ - __RW uint32_t OUTDMA_CTRL1; /* 0x30: Out DMA Buf Control 1 Register */ - __RW uint32_t ONXT_CMD; /* 0x34: Out DMA Next Command Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t CFG; /* 0x40: Configuration Register */ - __RW uint32_t STAT; /* 0x44: Status Register */ - __RW uint32_t WIDTH; /* 0x48: Image width register */ - __RW uint32_t HEIGHT; /* 0x4C: Image height register */ - __RW uint32_t BUFADDR; /* 0x50: Buf Access Addr */ - __RW uint32_t BUFDATA; /* 0x54: Buf Access Data */ - __R uint32_t OUTDMACNT; /* 0x58: Out DMA Bytes Counter */ - __RW uint32_t CSC_COEF0; /* 0x5C: YUV2RGB coefficients Register 0 */ - __RW uint32_t CSC_COEF1; /* 0x60: YUV2RGB coefficients Register 1 */ - __RW uint32_t CSC_COEF2; /* 0x64: YUV2RGB coefficients Register 2 */ - __RW uint32_t RGB2YUV_COEF0; /* 0x68: RGB2YUV coefficients Register 0 */ - __RW uint32_t RGB2YUV_COEF1; /* 0x6C: RGB2YUV coefficients Register 1 */ - __RW uint32_t RGB2YUV_COEF2; /* 0x70: RGB2YUV coefficients Register 2 */ - __RW uint32_t RGB2YUV_COEF3; /* 0x74: RGB2YUV coefficients Register 3 */ - __RW uint32_t RGB2YUV_COEF4; /* 0x78: RGB2YUV coefficients Register 4 */ - __R uint8_t RESERVED4[8]; /* 0x7C - 0x83: Reserved */ - __RW uint32_t IMGREG1; /* 0x84: Image Control Register 1 */ - __RW uint32_t IMGREG2; /* 0x88: Image Control Register 2 */ - __RW uint32_t IMGREG3; /* 0x8C: Image Control Register 3 */ - __RW uint32_t IMGREG[4]; /* 0x90 - 0x9C: Image Control Register 40 */ -} JPEG_Type; - - -/* Bitfield definition for register: INDMA_MISC */ -/* - * ARQOS (RW) - * - * QoS for AXI read channel - */ -#define JPEG_INDMA_MISC_ARQOS_MASK (0x780000UL) -#define JPEG_INDMA_MISC_ARQOS_SHIFT (19U) -#define JPEG_INDMA_MISC_ARQOS_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_ARQOS_SHIFT) & JPEG_INDMA_MISC_ARQOS_MASK) -#define JPEG_INDMA_MISC_ARQOS_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_ARQOS_MASK) >> JPEG_INDMA_MISC_ARQOS_SHIFT) - -/* - * MAX_OT (RW) - * - * max_ot when input are RGB pixels. - * For 16 bits per pixel, it can be set as 4. - * For 32 bits per pixel, it will be set as 2. - */ -#define JPEG_INDMA_MISC_MAX_OT_MASK (0x78000UL) -#define JPEG_INDMA_MISC_MAX_OT_SHIFT (15U) -#define JPEG_INDMA_MISC_MAX_OT_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_MAX_OT_SHIFT) & JPEG_INDMA_MISC_MAX_OT_MASK) -#define JPEG_INDMA_MISC_MAX_OT_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_MAX_OT_MASK) >> JPEG_INDMA_MISC_MAX_OT_SHIFT) - -/* - * INB13_SWAP (RW) - * - * Swap bit[31:24] and bit [15:8] before pack dir operation. Only work for pixel data. - */ -#define JPEG_INDMA_MISC_INB13_SWAP_MASK (0x4000U) -#define JPEG_INDMA_MISC_INB13_SWAP_SHIFT (14U) -#define JPEG_INDMA_MISC_INB13_SWAP_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INB13_SWAP_SHIFT) & JPEG_INDMA_MISC_INB13_SWAP_MASK) -#define JPEG_INDMA_MISC_INB13_SWAP_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INB13_SWAP_MASK) >> JPEG_INDMA_MISC_INB13_SWAP_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. Only work for pixel data. - * 2'b00: no change {A3, A2, A1, A0} - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define JPEG_INDMA_MISC_PACK_DIR_MASK (0x3000U) -#define JPEG_INDMA_MISC_PACK_DIR_SHIFT (12U) -#define JPEG_INDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_PACK_DIR_SHIFT) & JPEG_INDMA_MISC_PACK_DIR_MASK) -#define JPEG_INDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_PACK_DIR_MASK) >> JPEG_INDMA_MISC_PACK_DIR_SHIFT) - -/* - * INDMA_RENEW (RW) - * - * Renew In DMA. Default is to continue the write address counter when a new DMA request comes. Asserted to reset the write address counter. - */ -#define JPEG_INDMA_MISC_INDMA_RENEW_MASK (0x800U) -#define JPEG_INDMA_MISC_INDMA_RENEW_SHIFT (11U) -#define JPEG_INDMA_MISC_INDMA_RENEW_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) -#define JPEG_INDMA_MISC_INDMA_RENEW_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA_RENEW_MASK) >> JPEG_INDMA_MISC_INDMA_RENEW_SHIFT) - -/* - * NXT_IRQ_EN (RW) - * - * In DMA Next Interrupt Enable - */ -#define JPEG_INDMA_MISC_NXT_IRQ_EN_MASK (0x400U) -#define JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT (10U) -#define JPEG_INDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_INDMA_MISC_NXT_IRQ_EN_SHIFT) - -/* - * IN_DMA_DONE_IRQ_EN (RW) - * - * In DMA Done enable - */ -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK (0x200U) -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT (9U) -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IN_DMA_DONE_IRQ_EN_SHIFT) - -/* - * AXI_ERR_IRQ_EN (RW) - * - * In DMA axi bus error inetrrupt enable - */ -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x100U) -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (8U) -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_INDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable for all interrupt sources of In DMA module - */ -#define JPEG_INDMA_MISC_IRQ_EN_MASK (0x80U) -#define JPEG_INDMA_MISC_IRQ_EN_SHIFT (7U) -#define JPEG_INDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IRQ_EN_SHIFT) & JPEG_INDMA_MISC_IRQ_EN_MASK) -#define JPEG_INDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IRQ_EN_MASK) >> JPEG_INDMA_MISC_IRQ_EN_SHIFT) - -/* - * IN_DMA_ID (RW) - * - * 0: Pixel (In) - * 1: ECS (In) - * 2: Qmem - * 3: HuffEnc - * 4: HuffMin - * 5: HuffBase - * 6: HuffSymb - */ -#define JPEG_INDMA_MISC_IN_DMA_ID_MASK (0x70U) -#define JPEG_INDMA_MISC_IN_DMA_ID_SHIFT (4U) -#define JPEG_INDMA_MISC_IN_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) -#define JPEG_INDMA_MISC_IN_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_ID_MASK) >> JPEG_INDMA_MISC_IN_DMA_ID_SHIFT) - -/* - * IN_DMA_REQ (RW) - * - * Asserted to request DMA. Automatically clear after DMA is done. - */ -#define JPEG_INDMA_MISC_IN_DMA_REQ_MASK (0x8U) -#define JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT (3U) -#define JPEG_INDMA_MISC_IN_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) -#define JPEG_INDMA_MISC_IN_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_IN_DMA_REQ_MASK) >> JPEG_INDMA_MISC_IN_DMA_REQ_SHIFT) - -/* - * INDMA2D (RW) - * - * Asserted if In_DMA_ID=Pixel. - */ -#define JPEG_INDMA_MISC_INDMA2D_MASK (0x4U) -#define JPEG_INDMA_MISC_INDMA2D_SHIFT (2U) -#define JPEG_INDMA_MISC_INDMA2D_SET(x) (((uint32_t)(x) << JPEG_INDMA_MISC_INDMA2D_SHIFT) & JPEG_INDMA_MISC_INDMA2D_MASK) -#define JPEG_INDMA_MISC_INDMA2D_GET(x) (((uint32_t)(x) & JPEG_INDMA_MISC_INDMA2D_MASK) >> JPEG_INDMA_MISC_INDMA2D_SHIFT) - -/* Bitfield definition for register: INDMABASE */ -/* - * ADDR (RW) - * - * Y plane (or Encoded Bit Plane) - */ -#define JPEG_INDMABASE_ADDR_MASK (0xFFFFFFFFUL) -#define JPEG_INDMABASE_ADDR_SHIFT (0U) -#define JPEG_INDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_INDMABASE_ADDR_SHIFT) & JPEG_INDMABASE_ADDR_MASK) -#define JPEG_INDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_INDMABASE_ADDR_MASK) >> JPEG_INDMABASE_ADDR_SHIFT) - -/* Bitfield definition for register: INDMA_CTRL0 */ -/* - * TTLEN (RW) - * - * Total length (Low 16 bits) in Bytes -1 for transfer when In_DMA_ID!=Pixel. - */ -#define JPEG_INDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) -#define JPEG_INDMA_CTRL0_TTLEN_SHIFT (16U) -#define JPEG_INDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_TTLEN_SHIFT) & JPEG_INDMA_CTRL0_TTLEN_MASK) -#define JPEG_INDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_TTLEN_MASK) >> JPEG_INDMA_CTRL0_TTLEN_SHIFT) - -/* - * PITCH (RW) - * - * Pitch between the starting point of Rows. Only active when In_DMA_ID=Pixel.. - */ -#define JPEG_INDMA_CTRL0_PITCH_MASK (0xFFFFU) -#define JPEG_INDMA_CTRL0_PITCH_SHIFT (0U) -#define JPEG_INDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL0_PITCH_SHIFT) & JPEG_INDMA_CTRL0_PITCH_MASK) -#define JPEG_INDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL0_PITCH_MASK) >> JPEG_INDMA_CTRL0_PITCH_SHIFT) - -/* Bitfield definition for register: INDMA_CTRL1 */ -/* - * ROWLEN (RW) - * - * Total length (High 16 bits) in Bytes -1 for transfer. See reference in InDMA_Ctrl0[TTLEN] - */ -#define JPEG_INDMA_CTRL1_ROWLEN_MASK (0xFFFFU) -#define JPEG_INDMA_CTRL1_ROWLEN_SHIFT (0U) -#define JPEG_INDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_INDMA_CTRL1_ROWLEN_SHIFT) & JPEG_INDMA_CTRL1_ROWLEN_MASK) -#define JPEG_INDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_INDMA_CTRL1_ROWLEN_MASK) >> JPEG_INDMA_CTRL1_ROWLEN_SHIFT) - -/* Bitfield definition for register: INXT_CMD */ -/* - * ADDR (RW) - * - * The address pointing to the next command - */ -#define JPEG_INXT_CMD_ADDR_MASK (0xFFFFFFFCUL) -#define JPEG_INXT_CMD_ADDR_SHIFT (2U) -#define JPEG_INXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_ADDR_SHIFT) & JPEG_INXT_CMD_ADDR_MASK) -#define JPEG_INXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_ADDR_MASK) >> JPEG_INXT_CMD_ADDR_SHIFT) - -/* - * OP_VALID (RW) - * - * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the InDMA transfer if CFG[JPEG_EN] is 1. - */ -#define JPEG_INXT_CMD_OP_VALID_MASK (0x2U) -#define JPEG_INXT_CMD_OP_VALID_SHIFT (1U) -#define JPEG_INXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_OP_VALID_SHIFT) & JPEG_INXT_CMD_OP_VALID_MASK) -#define JPEG_INXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_OP_VALID_MASK) >> JPEG_INXT_CMD_OP_VALID_SHIFT) - -/* - * EN (RW) - * - * NXTCMD phase Enable Bit - */ -#define JPEG_INXT_CMD_EN_MASK (0x1U) -#define JPEG_INXT_CMD_EN_SHIFT (0U) -#define JPEG_INXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_INXT_CMD_EN_SHIFT) & JPEG_INXT_CMD_EN_MASK) -#define JPEG_INXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_INXT_CMD_EN_MASK) >> JPEG_INXT_CMD_EN_SHIFT) - -/* Bitfield definition for register: OUTDMA_MISC */ -/* - * AWQOS (RW) - * - */ -#define JPEG_OUTDMA_MISC_AWQOS_MASK (0x3C000UL) -#define JPEG_OUTDMA_MISC_AWQOS_SHIFT (14U) -#define JPEG_OUTDMA_MISC_AWQOS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AWQOS_SHIFT) & JPEG_OUTDMA_MISC_AWQOS_MASK) -#define JPEG_OUTDMA_MISC_AWQOS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AWQOS_MASK) >> JPEG_OUTDMA_MISC_AWQOS_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence in a byte is not changed. All outdma data are impacted. - * 2'b00: no change {A3, A2, A1, A0} (This is used for ecs stream) - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define JPEG_OUTDMA_MISC_PACK_DIR_MASK (0x3000U) -#define JPEG_OUTDMA_MISC_PACK_DIR_SHIFT (12U) -#define JPEG_OUTDMA_MISC_PACK_DIR_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) -#define JPEG_OUTDMA_MISC_PACK_DIR_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_PACK_DIR_MASK) >> JPEG_OUTDMA_MISC_PACK_DIR_SHIFT) - -/* - * EN_OUTCNT (RW) - * - * Enable output counter (unit as bytes) - */ -#define JPEG_OUTDMA_MISC_EN_OUTCNT_MASK (0x800U) -#define JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT (11U) -#define JPEG_OUTDMA_MISC_EN_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) -#define JPEG_OUTDMA_MISC_EN_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_EN_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_EN_OUTCNT_SHIFT) - -/* - * INI_OUTCNT (RW) - * - * Asserted to ini output counter - */ -#define JPEG_OUTDMA_MISC_INI_OUTCNT_MASK (0x400U) -#define JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT (10U) -#define JPEG_OUTDMA_MISC_INI_OUTCNT_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) -#define JPEG_OUTDMA_MISC_INI_OUTCNT_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_INI_OUTCNT_MASK) >> JPEG_OUTDMA_MISC_INI_OUTCNT_SHIFT) - -/* - * ADD_ODMA_ENDINGS (RW) - * - * Add 0xFFD9 to the ending of the odma stream when all original image pixels are processed by the encoder module. - */ -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK (0x200U) -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT (9U) -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) -#define JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_MASK) >> JPEG_OUTDMA_MISC_ADD_ODMA_ENDINGS_SHIFT) - -/* - * NXT_IRQ_EN (RW) - * - * Out DMA Next Interrupt Enable - */ -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK (0x100U) -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT (8U) -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_NXT_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_NXT_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_NXT_IRQ_EN_SHIFT) - -/* - * OUT_DMA_DONE_IRQ_EN (RW) - * - * Out DMA Done interrupt Enable - */ -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK (0x80U) -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT (7U) -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_DONE_IRQ_EN_SHIFT) - -/* - * AXI_ERR_IRQ_EN (RW) - * - * Out DMA axi bus error inetrrupt enable - */ -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK (0x40U) -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT (6U) -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_AXI_ERR_IRQ_EN_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable for all interrupt sources of Out DMA module - */ -#define JPEG_OUTDMA_MISC_IRQ_EN_MASK (0x20U) -#define JPEG_OUTDMA_MISC_IRQ_EN_SHIFT (5U) -#define JPEG_OUTDMA_MISC_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) -#define JPEG_OUTDMA_MISC_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_IRQ_EN_MASK) >> JPEG_OUTDMA_MISC_IRQ_EN_SHIFT) - -/* - * OUT_DMA_ID (RW) - * - * 0: Pixel (Out) - * 1: ECS (Out) - */ -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK (0x10U) -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT (4U) -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) -#define JPEG_OUTDMA_MISC_OUT_DMA_ID_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_ID_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_ID_SHIFT) - -/* - * OUT_DMA_REQ (RW) - * - * Asserted to enable Out DMA request - */ -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK (0x8U) -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT (3U) -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) -#define JPEG_OUTDMA_MISC_OUT_DMA_REQ_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUT_DMA_REQ_MASK) >> JPEG_OUTDMA_MISC_OUT_DMA_REQ_SHIFT) - -/* - * OUTDMA2D (RW) - * - * Asserted if Out_DMA_ID==Pixel - */ -#define JPEG_OUTDMA_MISC_OUTDMA2D_MASK (0x4U) -#define JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT (2U) -#define JPEG_OUTDMA_MISC_OUTDMA2D_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) -#define JPEG_OUTDMA_MISC_OUTDMA2D_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_MISC_OUTDMA2D_MASK) >> JPEG_OUTDMA_MISC_OUTDMA2D_SHIFT) - -/* Bitfield definition for register: OUTDMABASE */ -/* - * ADDR (RW) - * - * Y plane (or Encoded Bit Plane) - */ -#define JPEG_OUTDMABASE_ADDR_MASK (0xFFFFFFFFUL) -#define JPEG_OUTDMABASE_ADDR_SHIFT (0U) -#define JPEG_OUTDMABASE_ADDR_SET(x) (((uint32_t)(x) << JPEG_OUTDMABASE_ADDR_SHIFT) & JPEG_OUTDMABASE_ADDR_MASK) -#define JPEG_OUTDMABASE_ADDR_GET(x) (((uint32_t)(x) & JPEG_OUTDMABASE_ADDR_MASK) >> JPEG_OUTDMABASE_ADDR_SHIFT) - -/* Bitfield definition for register: OUTDMA_CTRL0 */ -/* - * TTLEN (RW) - * - * Total length (Low 16 bits) in Bytes -1 for transfer when Out_DMA_ID!=Pixel. If Out_DMA_ID=ECS, it can be any value greater than the length of the ECS, for example, the number of encoded bytes. - */ -#define JPEG_OUTDMA_CTRL0_TTLEN_MASK (0xFFFF0000UL) -#define JPEG_OUTDMA_CTRL0_TTLEN_SHIFT (16U) -#define JPEG_OUTDMA_CTRL0_TTLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) -#define JPEG_OUTDMA_CTRL0_TTLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_TTLEN_MASK) >> JPEG_OUTDMA_CTRL0_TTLEN_SHIFT) - -/* - * PITCH (RW) - * - * Pitch between the starting point of Rows when Out_DMA_ID==Pixel - */ -#define JPEG_OUTDMA_CTRL0_PITCH_MASK (0xFFFFU) -#define JPEG_OUTDMA_CTRL0_PITCH_SHIFT (0U) -#define JPEG_OUTDMA_CTRL0_PITCH_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL0_PITCH_SHIFT) & JPEG_OUTDMA_CTRL0_PITCH_MASK) -#define JPEG_OUTDMA_CTRL0_PITCH_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL0_PITCH_MASK) >> JPEG_OUTDMA_CTRL0_PITCH_SHIFT) - -/* Bitfield definition for register: OUTDMA_CTRL1 */ -/* - * ROWLEN (RW) - * - * Total length (High 16 bits) in Bytes -1 for transfer. See reference in OutDMA_Ctrl0[TTLEN] - */ -#define JPEG_OUTDMA_CTRL1_ROWLEN_MASK (0xFFFFU) -#define JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT (0U) -#define JPEG_OUTDMA_CTRL1_ROWLEN_SET(x) (((uint32_t)(x) << JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) -#define JPEG_OUTDMA_CTRL1_ROWLEN_GET(x) (((uint32_t)(x) & JPEG_OUTDMA_CTRL1_ROWLEN_MASK) >> JPEG_OUTDMA_CTRL1_ROWLEN_SHIFT) - -/* Bitfield definition for register: ONXT_CMD */ -/* - * ADDR (RW) - * - * The address pointing to the next command - */ -#define JPEG_ONXT_CMD_ADDR_MASK (0xFFFFFFFCUL) -#define JPEG_ONXT_CMD_ADDR_SHIFT (2U) -#define JPEG_ONXT_CMD_ADDR_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_ADDR_SHIFT) & JPEG_ONXT_CMD_ADDR_MASK) -#define JPEG_ONXT_CMD_ADDR_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_ADDR_MASK) >> JPEG_ONXT_CMD_ADDR_SHIFT) - -/* - * OP_VALID (RW) - * - * asserted if there is either a DATA DMA phase or NXTCMD phase. Automatically cleared. Will trigger the OutDMA and NXTCMD phase transfer if CFG[JPEG_EN] is 1. - */ -#define JPEG_ONXT_CMD_OP_VALID_MASK (0x2U) -#define JPEG_ONXT_CMD_OP_VALID_SHIFT (1U) -#define JPEG_ONXT_CMD_OP_VALID_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_OP_VALID_SHIFT) & JPEG_ONXT_CMD_OP_VALID_MASK) -#define JPEG_ONXT_CMD_OP_VALID_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_OP_VALID_MASK) >> JPEG_ONXT_CMD_OP_VALID_SHIFT) - -/* - * EN (RW) - * - * NXTCMD phase Enable Bit - */ -#define JPEG_ONXT_CMD_EN_MASK (0x1U) -#define JPEG_ONXT_CMD_EN_SHIFT (0U) -#define JPEG_ONXT_CMD_EN_SET(x) (((uint32_t)(x) << JPEG_ONXT_CMD_EN_SHIFT) & JPEG_ONXT_CMD_EN_MASK) -#define JPEG_ONXT_CMD_EN_GET(x) (((uint32_t)(x) & JPEG_ONXT_CMD_EN_MASK) >> JPEG_ONXT_CMD_EN_SHIFT) - -/* Bitfield definition for register: CFG */ -/* - * JD_UVSWAP (RW) - * - * Normally the default CbCr sequence is that Cb macro block coming before Cr macro blk. If Cr macro block is first, set this bit to 1'b1. This bit only impact the color space conversion from/to RGB. - */ -#define JPEG_CFG_JD_UVSWAP_MASK (0x400000UL) -#define JPEG_CFG_JD_UVSWAP_SHIFT (22U) -#define JPEG_CFG_JD_UVSWAP_SET(x) (((uint32_t)(x) << JPEG_CFG_JD_UVSWAP_SHIFT) & JPEG_CFG_JD_UVSWAP_MASK) -#define JPEG_CFG_JD_UVSWAP_GET(x) (((uint32_t)(x) & JPEG_CFG_JD_UVSWAP_MASK) >> JPEG_CFG_JD_UVSWAP_SHIFT) - -/* - * CFG_IPATH_SEL (RW) - * - * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V - * 2'b01:ARGB8888, byte sequence as B,G,R,A - * 2'b10:RGB565, byte sequence as B,R - * 2'b11: YUV422H, byte sequence as Y0,U0,Y1,V0 - */ -#define JPEG_CFG_CFG_IPATH_SEL_MASK (0x300000UL) -#define JPEG_CFG_CFG_IPATH_SEL_SHIFT (20U) -#define JPEG_CFG_CFG_IPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_IPATH_SEL_SHIFT) & JPEG_CFG_CFG_IPATH_SEL_MASK) -#define JPEG_CFG_CFG_IPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_IPATH_SEL_MASK) >> JPEG_CFG_CFG_IPATH_SEL_SHIFT) - -/* - * CODEC_OVER_IRQ_EN (RW) - * - * The jpg endec process done interrupt enable - */ -#define JPEG_CFG_CODEC_OVER_IRQ_EN_MASK (0x80000UL) -#define JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT (19U) -#define JPEG_CFG_CODEC_OVER_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) -#define JPEG_CFG_CODEC_OVER_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_OVER_IRQ_EN_MASK) >> JPEG_CFG_CODEC_OVER_IRQ_EN_SHIFT) - -/* - * CODEC_RESTART_ERR_IRQ_EN (RW) - * - * The jpg endec restart error interrupt enable - */ -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK (0x40000UL) -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT (18U) -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) -#define JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_MASK) >> JPEG_CFG_CODEC_RESTART_ERR_IRQ_EN_SHIFT) - -/* - * MEM_DEBUG_CLK_SEL (RW) - * - * asserted to use APB clock, so that the memory contents could be read out through APB interface - */ -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK (0x20000UL) -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT (17U) -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) -#define JPEG_CFG_MEM_DEBUG_CLK_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_MEM_DEBUG_CLK_SEL_MASK) >> JPEG_CFG_MEM_DEBUG_CLK_SEL_SHIFT) - -/* - * CLKGATE (RW) - * - * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - */ -#define JPEG_CFG_CLKGATE_MASK (0x200U) -#define JPEG_CFG_CLKGATE_SHIFT (9U) -#define JPEG_CFG_CLKGATE_SET(x) (((uint32_t)(x) << JPEG_CFG_CLKGATE_SHIFT) & JPEG_CFG_CLKGATE_MASK) -#define JPEG_CFG_CLKGATE_GET(x) (((uint32_t)(x) & JPEG_CFG_CLKGATE_MASK) >> JPEG_CFG_CLKGATE_SHIFT) - -/* - * CFG_OPATH_SEL (RW) - * - * 2'b0:2-plane (Y- and UV- plane) or 1-plane (Y-only) as determined by the original data, byte sequence as Y0,Y1, or U,V - * 2'b01:ARGB8888, byte sequence as B,G,R,A - * 2'b10:RGB565, byte sequence as R,B - * 2'b11: YUV422H1P, byte sequence as Y0,U0,Y1,V0 - */ -#define JPEG_CFG_CFG_OPATH_SEL_MASK (0x180U) -#define JPEG_CFG_CFG_OPATH_SEL_SHIFT (7U) -#define JPEG_CFG_CFG_OPATH_SEL_SET(x) (((uint32_t)(x) << JPEG_CFG_CFG_OPATH_SEL_SHIFT) & JPEG_CFG_CFG_OPATH_SEL_MASK) -#define JPEG_CFG_CFG_OPATH_SEL_GET(x) (((uint32_t)(x) & JPEG_CFG_CFG_OPATH_SEL_MASK) >> JPEG_CFG_CFG_OPATH_SEL_SHIFT) - -/* - * JDATA_FORMAT (RW) - * - * 3'b000: for 420, hy=2, vy=2, hc=1, vc=1 // 6 sub-blocks per MCU - * 3'b001: for 422h, hy=2, vy=1, hc=1, vc=1 // 4 sub-blocks per MCU - * 3'b010: for 422v, hy=1, vy=2, hc=1, vc=1 // 4 sub-blocks per MCU - * 3'b011: for 444, hy=1, vy=1, hc=1, vc=1 // 3 sub-blocks per MCU - * 3'b100: for 400, hy=2, vy=2, hc=0, vc=0 // 4 sub-blocks per MCU - * Others: Undefined - */ -#define JPEG_CFG_JDATA_FORMAT_MASK (0x70U) -#define JPEG_CFG_JDATA_FORMAT_SHIFT (4U) -#define JPEG_CFG_JDATA_FORMAT_SET(x) (((uint32_t)(x) << JPEG_CFG_JDATA_FORMAT_SHIFT) & JPEG_CFG_JDATA_FORMAT_MASK) -#define JPEG_CFG_JDATA_FORMAT_GET(x) (((uint32_t)(x) & JPEG_CFG_JDATA_FORMAT_MASK) >> JPEG_CFG_JDATA_FORMAT_SHIFT) - -/* - * JPEG_SFTRST (RW) - * - * Software Reset - */ -#define JPEG_CFG_JPEG_SFTRST_MASK (0x8U) -#define JPEG_CFG_JPEG_SFTRST_SHIFT (3U) -#define JPEG_CFG_JPEG_SFTRST_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_SFTRST_SHIFT) & JPEG_CFG_JPEG_SFTRST_MASK) -#define JPEG_CFG_JPEG_SFTRST_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_SFTRST_MASK) >> JPEG_CFG_JPEG_SFTRST_SHIFT) - -/* - * START (RW) - * - * Asserted if to start a new encoder/decoder conversion. - * It will at first stop the inner JPEG module, then reset it, and then re-run it. - * It is a different mode from DMA phase mode. - * It cannot be configured in the DMA chain descriptor. It should be configured by the core processor. - * Auto clear. - */ -#define JPEG_CFG_START_MASK (0x4U) -#define JPEG_CFG_START_SHIFT (2U) -#define JPEG_CFG_START_SET(x) (((uint32_t)(x) << JPEG_CFG_START_SHIFT) & JPEG_CFG_START_MASK) -#define JPEG_CFG_START_GET(x) (((uint32_t)(x) & JPEG_CFG_START_MASK) >> JPEG_CFG_START_SHIFT) - -/* - * MODE (RW) - * - * 1: decoder, 0:encoder - */ -#define JPEG_CFG_MODE_MASK (0x2U) -#define JPEG_CFG_MODE_SHIFT (1U) -#define JPEG_CFG_MODE_SET(x) (((uint32_t)(x) << JPEG_CFG_MODE_SHIFT) & JPEG_CFG_MODE_MASK) -#define JPEG_CFG_MODE_GET(x) (((uint32_t)(x) & JPEG_CFG_MODE_MASK) >> JPEG_CFG_MODE_SHIFT) - -/* - * JPEG_EN (RW) - * - * 1b - Enabled - */ -#define JPEG_CFG_JPEG_EN_MASK (0x1U) -#define JPEG_CFG_JPEG_EN_SHIFT (0U) -#define JPEG_CFG_JPEG_EN_SET(x) (((uint32_t)(x) << JPEG_CFG_JPEG_EN_SHIFT) & JPEG_CFG_JPEG_EN_MASK) -#define JPEG_CFG_JPEG_EN_GET(x) (((uint32_t)(x) & JPEG_CFG_JPEG_EN_MASK) >> JPEG_CFG_JPEG_EN_SHIFT) - -/* Bitfield definition for register: STAT */ -/* - * BUSY (RO) - * - * When 1 means that the module is busy doing conversion and data transfer. - */ -#define JPEG_STAT_BUSY_MASK (0x80000000UL) -#define JPEG_STAT_BUSY_SHIFT (31U) -#define JPEG_STAT_BUSY_GET(x) (((uint32_t)(x) & JPEG_STAT_BUSY_MASK) >> JPEG_STAT_BUSY_SHIFT) - -/* - * AXI_ERR_ID (RO) - * - * the axi err id - */ -#define JPEG_STAT_AXI_ERR_ID_MASK (0x3C00U) -#define JPEG_STAT_AXI_ERR_ID_SHIFT (10U) -#define JPEG_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_ID_MASK) >> JPEG_STAT_AXI_ERR_ID_SHIFT) - -/* - * AXI_READ_ERR (RO) - * - * in-dma axi bus error - */ -#define JPEG_STAT_AXI_READ_ERR_MASK (0x200U) -#define JPEG_STAT_AXI_READ_ERR_SHIFT (9U) -#define JPEG_STAT_AXI_READ_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_READ_ERR_MASK) >> JPEG_STAT_AXI_READ_ERR_SHIFT) - -/* - * AXI_WRITE_ERR (RO) - * - * out-dma axi bus error - */ -#define JPEG_STAT_AXI_WRITE_ERR_MASK (0x100U) -#define JPEG_STAT_AXI_WRITE_ERR_SHIFT (8U) -#define JPEG_STAT_AXI_WRITE_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_WRITE_ERR_MASK) >> JPEG_STAT_AXI_WRITE_ERR_SHIFT) - -/* - * AXI_ERR (W1C) - * - * axi bus error - */ -#define JPEG_STAT_AXI_ERR_MASK (0x80U) -#define JPEG_STAT_AXI_ERR_SHIFT (7U) -#define JPEG_STAT_AXI_ERR_SET(x) (((uint32_t)(x) << JPEG_STAT_AXI_ERR_SHIFT) & JPEG_STAT_AXI_ERR_MASK) -#define JPEG_STAT_AXI_ERR_GET(x) (((uint32_t)(x) & JPEG_STAT_AXI_ERR_MASK) >> JPEG_STAT_AXI_ERR_SHIFT) - -/* - * ONXT_IRQ (W1C) - * - * OutDMA next interrupt - */ -#define JPEG_STAT_ONXT_IRQ_MASK (0x40U) -#define JPEG_STAT_ONXT_IRQ_SHIFT (6U) -#define JPEG_STAT_ONXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_ONXT_IRQ_SHIFT) & JPEG_STAT_ONXT_IRQ_MASK) -#define JPEG_STAT_ONXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_ONXT_IRQ_MASK) >> JPEG_STAT_ONXT_IRQ_SHIFT) - -/* - * INXT_IRQ (W1C) - * - * InDMA next interrupt - */ -#define JPEG_STAT_INXT_IRQ_MASK (0x20U) -#define JPEG_STAT_INXT_IRQ_SHIFT (5U) -#define JPEG_STAT_INXT_IRQ_SET(x) (((uint32_t)(x) << JPEG_STAT_INXT_IRQ_SHIFT) & JPEG_STAT_INXT_IRQ_MASK) -#define JPEG_STAT_INXT_IRQ_GET(x) (((uint32_t)(x) & JPEG_STAT_INXT_IRQ_MASK) >> JPEG_STAT_INXT_IRQ_SHIFT) - -/* - * OUT_DMA_TRANSFER_DONE (W1C) - * - * OutDMA process done - */ -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK (0x10U) -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT (4U) -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) -#define JPEG_STAT_OUT_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_OUT_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_OUT_DMA_TRANSFER_DONE_SHIFT) - -/* - * IN_DMA_TRANSFER_DONE (W1C) - * - * InDMA process done - */ -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK (0x8U) -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT (3U) -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_SET(x) (((uint32_t)(x) << JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) -#define JPEG_STAT_IN_DMA_TRANSFER_DONE_GET(x) (((uint32_t)(x) & JPEG_STAT_IN_DMA_TRANSFER_DONE_MASK) >> JPEG_STAT_IN_DMA_TRANSFER_DONE_SHIFT) - -/* - * CODEC_OVER (W1C) - * - * Coding or decoding process is over. DMA is not included. - * The module is completely not busy only when in_dma_transfer_done and out_dma_transfer_done, and codec_over are all asserted. - */ -#define JPEG_STAT_CODEC_OVER_MASK (0x4U) -#define JPEG_STAT_CODEC_OVER_SHIFT (2U) -#define JPEG_STAT_CODEC_OVER_SET(x) (((uint32_t)(x) << JPEG_STAT_CODEC_OVER_SHIFT) & JPEG_STAT_CODEC_OVER_MASK) -#define JPEG_STAT_CODEC_OVER_GET(x) (((uint32_t)(x) & JPEG_STAT_CODEC_OVER_MASK) >> JPEG_STAT_CODEC_OVER_SHIFT) - -/* - * RESTART_MARKER_ERROR (W1C) - * - * codec restart marker error interrupt - */ -#define JPEG_STAT_RESTART_MARKER_ERROR_MASK (0x2U) -#define JPEG_STAT_RESTART_MARKER_ERROR_SHIFT (1U) -#define JPEG_STAT_RESTART_MARKER_ERROR_SET(x) (((uint32_t)(x) << JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) -#define JPEG_STAT_RESTART_MARKER_ERROR_GET(x) (((uint32_t)(x) & JPEG_STAT_RESTART_MARKER_ERROR_MASK) >> JPEG_STAT_RESTART_MARKER_ERROR_SHIFT) - -/* Bitfield definition for register: WIDTH */ -/* - * IMG (RW) - * - * Image Width (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - */ -#define JPEG_WIDTH_IMG_MASK (0xFFFFU) -#define JPEG_WIDTH_IMG_SHIFT (0U) -#define JPEG_WIDTH_IMG_SET(x) (((uint32_t)(x) << JPEG_WIDTH_IMG_SHIFT) & JPEG_WIDTH_IMG_MASK) -#define JPEG_WIDTH_IMG_GET(x) (((uint32_t)(x) & JPEG_WIDTH_IMG_MASK) >> JPEG_WIDTH_IMG_SHIFT) - -/* Bitfield definition for register: HEIGHT */ -/* - * IMG (RW) - * - * Image Height (it is the max index of pixel counting from 0, assuming the top left pixel is indexed as [0,0]) - */ -#define JPEG_HEIGHT_IMG_MASK (0xFFFFU) -#define JPEG_HEIGHT_IMG_SHIFT (0U) -#define JPEG_HEIGHT_IMG_SET(x) (((uint32_t)(x) << JPEG_HEIGHT_IMG_SHIFT) & JPEG_HEIGHT_IMG_MASK) -#define JPEG_HEIGHT_IMG_GET(x) (((uint32_t)(x) & JPEG_HEIGHT_IMG_MASK) >> JPEG_HEIGHT_IMG_SHIFT) - -/* Bitfield definition for register: BUFADDR */ -/* - * ADDR (RW) - * - * ADDR[31:28] denotes the buffer type: - * 0x2: Qmem - * 0x3: HuffEnc - * 0x4: HuffMin - * 0x5: HuffBase - * 0x6: HuffSymb - * ADDR[27:0] is the address inside the buffer - */ -#define JPEG_BUFADDR_ADDR_MASK (0xFFFFFFFFUL) -#define JPEG_BUFADDR_ADDR_SHIFT (0U) -#define JPEG_BUFADDR_ADDR_SET(x) (((uint32_t)(x) << JPEG_BUFADDR_ADDR_SHIFT) & JPEG_BUFADDR_ADDR_MASK) -#define JPEG_BUFADDR_ADDR_GET(x) (((uint32_t)(x) & JPEG_BUFADDR_ADDR_MASK) >> JPEG_BUFADDR_ADDR_SHIFT) - -/* Bitfield definition for register: BUFDATA */ -/* - * DATA (RW) - * - * The data write-to/read-from buffer. - * The n-th address read will be actually the data written for n-1 th address, and the actual stored location is n-1 th address. - */ -#define JPEG_BUFDATA_DATA_MASK (0xFFFFFFFFUL) -#define JPEG_BUFDATA_DATA_SHIFT (0U) -#define JPEG_BUFDATA_DATA_SET(x) (((uint32_t)(x) << JPEG_BUFDATA_DATA_SHIFT) & JPEG_BUFDATA_DATA_MASK) -#define JPEG_BUFDATA_DATA_GET(x) (((uint32_t)(x) & JPEG_BUFDATA_DATA_MASK) >> JPEG_BUFDATA_DATA_SHIFT) - -/* Bitfield definition for register: OUTDMACNT */ -/* - * VAL (RO) - * - * The out DMA counter - */ -#define JPEG_OUTDMACNT_VAL_MASK (0xFFFFFFFFUL) -#define JPEG_OUTDMACNT_VAL_SHIFT (0U) -#define JPEG_OUTDMACNT_VAL_GET(x) (((uint32_t)(x) & JPEG_OUTDMACNT_VAL_MASK) >> JPEG_OUTDMACNT_VAL_SHIFT) - -/* Bitfield definition for register: CSC_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * This bit changes the behavior when performing U/V converting. - * 0b - Converting YUV to RGB data - * 1b - Converting YCbCr to RGB data - */ -#define JPEG_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define JPEG_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -#define JPEG_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) -#define JPEG_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_YCBCR_MODE_MASK) >> JPEG_CSC_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Enable the CSC unit. - * 0b - The CSC is bypassed - * 1b - The CSC is enabled - */ -#define JPEG_CSC_COEF0_ENABLE_MASK (0x40000000UL) -#define JPEG_CSC_COEF0_ENABLE_SHIFT (30U) -#define JPEG_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_ENABLE_SHIFT) & JPEG_CSC_COEF0_ENABLE_MASK) -#define JPEG_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_ENABLE_MASK) >> JPEG_CSC_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define JPEG_CSC_COEF0_C0_MASK (0x1FFC0000UL) -#define JPEG_CSC_COEF0_C0_SHIFT (18U) -#define JPEG_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_C0_SHIFT) & JPEG_CSC_COEF0_C0_MASK) -#define JPEG_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_C0_MASK) >> JPEG_CSC_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define JPEG_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define JPEG_CSC_COEF0_UV_OFFSET_SHIFT (9U) -#define JPEG_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_UV_OFFSET_SHIFT) & JPEG_CSC_COEF0_UV_OFFSET_MASK) -#define JPEG_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_UV_OFFSET_MASK) >> JPEG_CSC_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define JPEG_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) -#define JPEG_CSC_COEF0_Y_OFFSET_SHIFT (0U) -#define JPEG_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF0_Y_OFFSET_SHIFT) & JPEG_CSC_COEF0_Y_OFFSET_MASK) -#define JPEG_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF0_Y_OFFSET_MASK) >> JPEG_CSC_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: CSC_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define JPEG_CSC_COEF1_C1_MASK (0x7FF0000UL) -#define JPEG_CSC_COEF1_C1_SHIFT (16U) -#define JPEG_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C1_SHIFT) & JPEG_CSC_COEF1_C1_MASK) -#define JPEG_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C1_MASK) >> JPEG_CSC_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define JPEG_CSC_COEF1_C4_MASK (0x7FFU) -#define JPEG_CSC_COEF1_C4_SHIFT (0U) -#define JPEG_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF1_C4_SHIFT) & JPEG_CSC_COEF1_C4_MASK) -#define JPEG_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF1_C4_MASK) >> JPEG_CSC_COEF1_C4_SHIFT) - -/* Bitfield definition for register: CSC_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define JPEG_CSC_COEF2_C2_MASK (0x7FF0000UL) -#define JPEG_CSC_COEF2_C2_SHIFT (16U) -#define JPEG_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C2_SHIFT) & JPEG_CSC_COEF2_C2_MASK) -#define JPEG_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C2_MASK) >> JPEG_CSC_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define JPEG_CSC_COEF2_C3_MASK (0x7FFU) -#define JPEG_CSC_COEF2_C3_SHIFT (0U) -#define JPEG_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_CSC_COEF2_C3_SHIFT) & JPEG_CSC_COEF2_C3_MASK) -#define JPEG_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_CSC_COEF2_C3_MASK) >> JPEG_CSC_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * Asserted to use YCrCb mode. Must be assigned as 1. - */ -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) -#define JPEG_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> JPEG_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Asserted to enable this RGB2YCbCr CSC stage - */ -#define JPEG_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) -#define JPEG_RGB2YUV_COEF0_ENABLE_SHIFT (30U) -#define JPEG_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) -#define JPEG_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_ENABLE_MASK) >> JPEG_RGB2YUV_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * CSC parameters C0 - */ -#define JPEG_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) -#define JPEG_RGB2YUV_COEF0_C0_SHIFT (18U) -#define JPEG_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_C0_SHIFT) & JPEG_RGB2YUV_COEF0_C0_MASK) -#define JPEG_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_C0_MASK) >> JPEG_RGB2YUV_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * CSC parameters UV_OFFSET - */ -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) -#define JPEG_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_UV_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * CSC parameters Y_OFFSET - */ -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) -#define JPEG_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF0_Y_OFFSET_MASK) >> JPEG_RGB2YUV_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF1 */ -/* - * C1 (RW) - * - * CSC parameters C1 - */ -#define JPEG_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF1_C1_SHIFT (16U) -#define JPEG_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C1_SHIFT) & JPEG_RGB2YUV_COEF1_C1_MASK) -#define JPEG_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C1_MASK) >> JPEG_RGB2YUV_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * CSC parameters C4 - */ -#define JPEG_RGB2YUV_COEF1_C4_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF1_C4_SHIFT (0U) -#define JPEG_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF1_C4_SHIFT) & JPEG_RGB2YUV_COEF1_C4_MASK) -#define JPEG_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF1_C4_MASK) >> JPEG_RGB2YUV_COEF1_C4_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF2 */ -/* - * C2 (RW) - * - * CSC parameters C2 - */ -#define JPEG_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF2_C2_SHIFT (16U) -#define JPEG_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C2_SHIFT) & JPEG_RGB2YUV_COEF2_C2_MASK) -#define JPEG_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C2_MASK) >> JPEG_RGB2YUV_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * CSC parameters C3 - */ -#define JPEG_RGB2YUV_COEF2_C3_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF2_C3_SHIFT (0U) -#define JPEG_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF2_C3_SHIFT) & JPEG_RGB2YUV_COEF2_C3_MASK) -#define JPEG_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF2_C3_MASK) >> JPEG_RGB2YUV_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF3 */ -/* - * C6 (RW) - * - * CSC parameters C6 - */ -#define JPEG_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF3_C6_SHIFT (16U) -#define JPEG_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C6_SHIFT) & JPEG_RGB2YUV_COEF3_C6_MASK) -#define JPEG_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C6_MASK) >> JPEG_RGB2YUV_COEF3_C6_SHIFT) - -/* - * C5 (RW) - * - * CSC parameters C5 - */ -#define JPEG_RGB2YUV_COEF3_C5_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF3_C5_SHIFT (0U) -#define JPEG_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF3_C5_SHIFT) & JPEG_RGB2YUV_COEF3_C5_MASK) -#define JPEG_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF3_C5_MASK) >> JPEG_RGB2YUV_COEF3_C5_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF4 */ -/* - * C8 (RW) - * - * CSC parameters C8 - */ -#define JPEG_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) -#define JPEG_RGB2YUV_COEF4_C8_SHIFT (16U) -#define JPEG_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C8_SHIFT) & JPEG_RGB2YUV_COEF4_C8_MASK) -#define JPEG_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C8_MASK) >> JPEG_RGB2YUV_COEF4_C8_SHIFT) - -/* - * C7 (RW) - * - * CSC parameters C7 - */ -#define JPEG_RGB2YUV_COEF4_C7_MASK (0x7FFU) -#define JPEG_RGB2YUV_COEF4_C7_SHIFT (0U) -#define JPEG_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << JPEG_RGB2YUV_COEF4_C7_SHIFT) & JPEG_RGB2YUV_COEF4_C7_MASK) -#define JPEG_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & JPEG_RGB2YUV_COEF4_C7_MASK) >> JPEG_RGB2YUV_COEF4_C7_SHIFT) - -/* Bitfield definition for register: IMGREG1 */ -/* - * RE (RW) - * - * Encoder Use only. - * Asseted to enable the Restart Marker processing. A Restart Marker is inserted in the outputted ECS (Entropy Coded Segment) every NRST+1 MCUs - */ -#define JPEG_IMGREG1_RE_MASK (0x4U) -#define JPEG_IMGREG1_RE_SHIFT (2U) -#define JPEG_IMGREG1_RE_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_RE_SHIFT) & JPEG_IMGREG1_RE_MASK) -#define JPEG_IMGREG1_RE_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_RE_MASK) >> JPEG_IMGREG1_RE_SHIFT) - -/* - * NCOL (RW) - * - * Ncol is the number of color components in the image data to process minus 1. For example, for a grayscale image Ncol=0, for an RGB image, Ncol=2 - */ -#define JPEG_IMGREG1_NCOL_MASK (0x3U) -#define JPEG_IMGREG1_NCOL_SHIFT (0U) -#define JPEG_IMGREG1_NCOL_SET(x) (((uint32_t)(x) << JPEG_IMGREG1_NCOL_SHIFT) & JPEG_IMGREG1_NCOL_MASK) -#define JPEG_IMGREG1_NCOL_GET(x) (((uint32_t)(x) & JPEG_IMGREG1_NCOL_MASK) >> JPEG_IMGREG1_NCOL_SHIFT) - -/* Bitfield definition for register: IMGREG2 */ -/* - * NMCU (RW) - * - * Encoder Use only. - * The number of NMCU to be generated in encoder mode - */ -#define JPEG_IMGREG2_NMCU_MASK (0x3FFFFFFUL) -#define JPEG_IMGREG2_NMCU_SHIFT (0U) -#define JPEG_IMGREG2_NMCU_SET(x) (((uint32_t)(x) << JPEG_IMGREG2_NMCU_SHIFT) & JPEG_IMGREG2_NMCU_MASK) -#define JPEG_IMGREG2_NMCU_GET(x) (((uint32_t)(x) & JPEG_IMGREG2_NMCU_MASK) >> JPEG_IMGREG2_NMCU_SHIFT) - -/* Bitfield definition for register: IMGREG3 */ -/* - * NRST (RW) - * - * Encoder use only. - * It is the number of MCUs between two Restart Markers (if enabled) minus 1. The content of this register is ignored if the Re bit inregister 1 is not set. - */ -#define JPEG_IMGREG3_NRST_MASK (0xFFFFU) -#define JPEG_IMGREG3_NRST_SHIFT (0U) -#define JPEG_IMGREG3_NRST_SET(x) (((uint32_t)(x) << JPEG_IMGREG3_NRST_SHIFT) & JPEG_IMGREG3_NRST_MASK) -#define JPEG_IMGREG3_NRST_GET(x) (((uint32_t)(x) & JPEG_IMGREG3_NRST_MASK) >> JPEG_IMGREG3_NRST_SHIFT) - -/* Bitfield definition for register array: IMGREG */ -/* - * NBLOCK (RW) - * - * Encoder use only. - * The number of data units (8x8 blocks of data) of the color componet contained in the MCU minus 1. - */ -#define JPEG_IMGREG_NBLOCK_MASK (0xF0U) -#define JPEG_IMGREG_NBLOCK_SHIFT (4U) -#define JPEG_IMGREG_NBLOCK_SET(x) (((uint32_t)(x) << JPEG_IMGREG_NBLOCK_SHIFT) & JPEG_IMGREG_NBLOCK_MASK) -#define JPEG_IMGREG_NBLOCK_GET(x) (((uint32_t)(x) & JPEG_IMGREG_NBLOCK_MASK) >> JPEG_IMGREG_NBLOCK_SHIFT) - -/* - * QT (RW) - * - * Encoder use only. - * The selection of the quantization table. - */ -#define JPEG_IMGREG_QT_MASK (0xCU) -#define JPEG_IMGREG_QT_SHIFT (2U) -#define JPEG_IMGREG_QT_SET(x) (((uint32_t)(x) << JPEG_IMGREG_QT_SHIFT) & JPEG_IMGREG_QT_MASK) -#define JPEG_IMGREG_QT_GET(x) (((uint32_t)(x) & JPEG_IMGREG_QT_MASK) >> JPEG_IMGREG_QT_SHIFT) - -/* - * HA (RW) - * - * Encoder use only. - * The selection of the Huffman table for the encoding of the AC coefficients in the data units belonging to the color component. - */ -#define JPEG_IMGREG_HA_MASK (0x2U) -#define JPEG_IMGREG_HA_SHIFT (1U) -#define JPEG_IMGREG_HA_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HA_SHIFT) & JPEG_IMGREG_HA_MASK) -#define JPEG_IMGREG_HA_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HA_MASK) >> JPEG_IMGREG_HA_SHIFT) - -/* - * HD (RW) - * - * Encoder use only. - * The selection of the Huffman table for the encoding of the DC coefficients in the data units belonging to the color component. - */ -#define JPEG_IMGREG_HD_MASK (0x1U) -#define JPEG_IMGREG_HD_SHIFT (0U) -#define JPEG_IMGREG_HD_SET(x) (((uint32_t)(x) << JPEG_IMGREG_HD_SHIFT) & JPEG_IMGREG_HD_MASK) -#define JPEG_IMGREG_HD_GET(x) (((uint32_t)(x) & JPEG_IMGREG_HD_MASK) >> JPEG_IMGREG_HD_SHIFT) - - - -/* IMGREG register group index macro definition */ -#define JPEG_IMGREG_REG40 (0UL) -#define JPEG_IMGREG_REG41 (1UL) -#define JPEG_IMGREG_REG42 (2UL) -#define JPEG_IMGREG_REG43 (3UL) - - -#endif /* HPM_JPEG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_keym_regs.h deleted file mode 100644 index 0d97ce1ecb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_keym_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_KEYM_H -#define HPM_KEYM_H - -typedef struct { - __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ - __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ - __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ - __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ - __RW uint32_t RNG; /* 0x48: Random number interface behavior */ - __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ -} KEYM_Type; - - -/* Bitfield definition for register array: SOFTMKEY */ -/* - * KEY (RW) - * - * software symmetric key - * key will be scambled to 4 variants for software to use, and replicable on same chip. - * scramble keys are chip different, and not replicable on different chip - * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - */ -#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTMKEY_KEY_SHIFT (0U) -#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) -#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) - -/* Bitfield definition for register array: SOFTPKEY */ -/* - * KEY (RW) - * - * software asymmetric key - * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. - * This key os read once, sencondary read will read out 0 - */ -#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTPKEY_KEY_SHIFT (0U) -#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) -#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) - -/* Bitfield definition for register: SEC_KEY_CTL */ -/* - * LOCK_SEC_CTL (RW) - * - * block secure state key setting being changed - */ -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use origin value in software symmetric key - * 1: use scramble version of software symmetric key - */ -#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use alnertave scramble of fuse symmetric key - */ -#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: NSC_KEY_CTL */ -/* - * LOCK_NSC_CTL (RW) - * - * block non-secure state key setting being changed - */ -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use origin value in fuse symmetric key - */ -#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * non-secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: RNG */ -/* - * BLOCK_RNG_XOR (RW) - * - * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset - * 0: RNG_XOR can be changed by software - * 1: RNG_XOR ignore software change from software - */ -#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) -#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) -#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) -#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) - -/* - * RNG_XOR (RW) - * - * control how SFK is accepted from random number generator - * 0: SFK value replaced by random number input - * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - */ -#define KEYM_RNG_RNG_XOR_MASK (0x1U) -#define KEYM_RNG_RNG_XOR_SHIFT (0U) -#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) -#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) - -/* Bitfield definition for register: READ_CONTROL */ -/* - * BLOCK_PK_READ (RW) - * - * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) - -/* - * BLOCK_SMK_READ (RW) - * - * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) - - - -/* SOFTMKEY register group index macro definition */ -#define KEYM_SOFTMKEY_SFK0 (0UL) -#define KEYM_SOFTMKEY_SFK1 (1UL) -#define KEYM_SOFTMKEY_SFK2 (2UL) -#define KEYM_SOFTMKEY_SFK3 (3UL) -#define KEYM_SOFTMKEY_SFK4 (4UL) -#define KEYM_SOFTMKEY_SFK5 (5UL) -#define KEYM_SOFTMKEY_SFK6 (6UL) -#define KEYM_SOFTMKEY_SFK7 (7UL) - -/* SOFTPKEY register group index macro definition */ -#define KEYM_SOFTPKEY_SPK0 (0UL) -#define KEYM_SOFTPKEY_SPK1 (1UL) -#define KEYM_SOFTPKEY_SPK2 (2UL) -#define KEYM_SOFTPKEY_SPK3 (3UL) -#define KEYM_SOFTPKEY_SPK4 (4UL) -#define KEYM_SOFTPKEY_SPK5 (5UL) -#define KEYM_SOFTPKEY_SPK6 (6UL) -#define KEYM_SOFTPKEY_SPK7 (7UL) - - -#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lcb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lcb_regs.h deleted file mode 100644 index e564cd97662..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lcb_regs.h +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LCB_H -#define HPM_LCB_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: control register */ - __R uint8_t RESERVED0[96]; /* 0x4 - 0x63: Reserved */ - __R uint32_t PHY_STAT; /* 0x64: LVDS RX PHY Status register */ - __RW uint32_t PHY_POW_CTRL[2]; /* 0x68 - 0x6C: LVDS0 PHY power control register */ - __RW uint32_t PHY_D_CTRL[4]; /* 0x70 - 0x7C: LVDS0 PHY Data Channel RX0 Setting */ - __RW uint32_t PHY_CK_CTRL[2]; /* 0x80 - 0x84: LVDS0 PHY CK Channel Setting */ - __RW uint32_t PHY_ADJ_CTRL[2]; /* 0x88 - 0x8C: LVDS0 PHY ADJ Setting */ - __RW uint32_t PHY_SU_CTRL[2]; /* 0x90 - 0x94: LVDS0 PHY SU CTRL */ -} LCB_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * LVDS_RXCK_SEL (RW) - * - * just for LVDS Display mode and CAM LINK mode, clock selection: - * 1: LVDS1 RXCK - * 0: LVDS0 RXCK - */ -#define LCB_CTRL_LVDS_RXCK_SEL_MASK (0x100U) -#define LCB_CTRL_LVDS_RXCK_SEL_SHIFT (8U) -#define LCB_CTRL_LVDS_RXCK_SEL_SET(x) (((uint32_t)(x) << LCB_CTRL_LVDS_RXCK_SEL_SHIFT) & LCB_CTRL_LVDS_RXCK_SEL_MASK) -#define LCB_CTRL_LVDS_RXCK_SEL_GET(x) (((uint32_t)(x) & LCB_CTRL_LVDS_RXCK_SEL_MASK) >> LCB_CTRL_LVDS_RXCK_SEL_SHIFT) - -/* - * CAM_LINK_WIDTH (RW) - * - * just for CAM LINK mode, data width: - * 00: 24bit - * 01: 30bit - * 10: 36bit - * 11: reserved - */ -#define LCB_CTRL_CAM_LINK_WIDTH_MASK (0xC0U) -#define LCB_CTRL_CAM_LINK_WIDTH_SHIFT (6U) -#define LCB_CTRL_CAM_LINK_WIDTH_SET(x) (((uint32_t)(x) << LCB_CTRL_CAM_LINK_WIDTH_SHIFT) & LCB_CTRL_CAM_LINK_WIDTH_MASK) -#define LCB_CTRL_CAM_LINK_WIDTH_GET(x) (((uint32_t)(x) & LCB_CTRL_CAM_LINK_WIDTH_MASK) >> LCB_CTRL_CAM_LINK_WIDTH_SHIFT) - -/* - * BIT_MAPPING (RW) - * - * just for LVDS Display mode, data protocol: - * 1: JEIDA standard - * 0: SPWG standard - */ -#define LCB_CTRL_BIT_MAPPING_MASK (0x20U) -#define LCB_CTRL_BIT_MAPPING_SHIFT (5U) -#define LCB_CTRL_BIT_MAPPING_SET(x) (((uint32_t)(x) << LCB_CTRL_BIT_MAPPING_SHIFT) & LCB_CTRL_BIT_MAPPING_MASK) -#define LCB_CTRL_BIT_MAPPING_GET(x) (((uint32_t)(x) & LCB_CTRL_BIT_MAPPING_MASK) >> LCB_CTRL_BIT_MAPPING_SHIFT) - -/* - * DATA_WIDTH (RW) - * - * just for LVDS Display mode, data width: - * 1: 24bit - * 0: 18bit(3line) - */ -#define LCB_CTRL_DATA_WIDTH_MASK (0x10U) -#define LCB_CTRL_DATA_WIDTH_SHIFT (4U) -#define LCB_CTRL_DATA_WIDTH_SET(x) (((uint32_t)(x) << LCB_CTRL_DATA_WIDTH_SHIFT) & LCB_CTRL_DATA_WIDTH_MASK) -#define LCB_CTRL_DATA_WIDTH_GET(x) (((uint32_t)(x) & LCB_CTRL_DATA_WIDTH_MASK) >> LCB_CTRL_DATA_WIDTH_SHIFT) - -/* - * MODE (RW) - * - * mode selection： - * 00: lvds display(4 line), two LVDS RX PHY must be LVDS display mode - * 01: cam link(4 line), two LVDS RX PHY must be LVDS display mode - * 10: sync code(2 line), LVDS RX PHY must be LVDS cameral mode - * 11: sync code(1line), LVDS RX PHY must be LVDS cameral mode - */ -#define LCB_CTRL_MODE_MASK (0x3U) -#define LCB_CTRL_MODE_SHIFT (0U) -#define LCB_CTRL_MODE_SET(x) (((uint32_t)(x) << LCB_CTRL_MODE_SHIFT) & LCB_CTRL_MODE_MASK) -#define LCB_CTRL_MODE_GET(x) (((uint32_t)(x) & LCB_CTRL_MODE_MASK) >> LCB_CTRL_MODE_SHIFT) - -/* Bitfield definition for register: PHY_STAT */ -/* - * LVDS1_RX_PHY_DLL_LOCK (RO) - * - * LVDS1 RX PHY DLL Lock indication Signal, 1 means dll already locked - */ -#define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_MASK (0x2U) -#define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_SHIFT (1U) -#define LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_GET(x) (((uint32_t)(x) & LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_MASK) >> LCB_PHY_STAT_LVDS1_RX_PHY_DLL_LOCK_SHIFT) - -/* - * LVDS0_RX_PHY_DLL_LOCK (RO) - * - * LVDS0 RX PHY DLL Lock indication Signal, 1 means dll already locked - */ -#define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_MASK (0x1U) -#define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_SHIFT (0U) -#define LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_GET(x) (((uint32_t)(x) & LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_MASK) >> LCB_PHY_STAT_LVDS0_RX_PHY_DLL_LOCK_SHIFT) - -/* Bitfield definition for register array: PHY_POW_CTRL */ -/* - * IDDQ_EN (RW) - * - * Power down control signal of channel rxck/rx1/rx0 - * 0: Normal operation - * 1: Power down channel - */ -#define LCB_PHY_POW_CTRL_IDDQ_EN_MASK (0x8U) -#define LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT (3U) -#define LCB_PHY_POW_CTRL_IDDQ_EN_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT) & LCB_PHY_POW_CTRL_IDDQ_EN_MASK) -#define LCB_PHY_POW_CTRL_IDDQ_EN_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_IDDQ_EN_MASK) >> LCB_PHY_POW_CTRL_IDDQ_EN_SHIFT) - -/* - * RXCK_PD (RW) - * - * Power down control signal of channel rxck - * 0: Normal operation - * 1: Power down channel - */ -#define LCB_PHY_POW_CTRL_RXCK_PD_MASK (0x4U) -#define LCB_PHY_POW_CTRL_RXCK_PD_SHIFT (2U) -#define LCB_PHY_POW_CTRL_RXCK_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RXCK_PD_SHIFT) & LCB_PHY_POW_CTRL_RXCK_PD_MASK) -#define LCB_PHY_POW_CTRL_RXCK_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RXCK_PD_MASK) >> LCB_PHY_POW_CTRL_RXCK_PD_SHIFT) - -/* - * RX1_PD (RW) - * - * Power down control signal of channel rx1 - * 0: Normal operation - * 1: Power down channel - */ -#define LCB_PHY_POW_CTRL_RX1_PD_MASK (0x2U) -#define LCB_PHY_POW_CTRL_RX1_PD_SHIFT (1U) -#define LCB_PHY_POW_CTRL_RX1_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RX1_PD_SHIFT) & LCB_PHY_POW_CTRL_RX1_PD_MASK) -#define LCB_PHY_POW_CTRL_RX1_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RX1_PD_MASK) >> LCB_PHY_POW_CTRL_RX1_PD_SHIFT) - -/* - * RX0_PD (RW) - * - * Power down control signal of channel rx0 - * 0: Normal operation - * 1: Power down channel - */ -#define LCB_PHY_POW_CTRL_RX0_PD_MASK (0x1U) -#define LCB_PHY_POW_CTRL_RX0_PD_SHIFT (0U) -#define LCB_PHY_POW_CTRL_RX0_PD_SET(x) (((uint32_t)(x) << LCB_PHY_POW_CTRL_RX0_PD_SHIFT) & LCB_PHY_POW_CTRL_RX0_PD_MASK) -#define LCB_PHY_POW_CTRL_RX0_PD_GET(x) (((uint32_t)(x) & LCB_PHY_POW_CTRL_RX0_PD_MASK) >> LCB_PHY_POW_CTRL_RX0_PD_SHIFT) - -/* Bitfield definition for register array: PHY_D_CTRL */ -/* - * RX_VCOM (RW) - * - * bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable - * bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground - */ -#define LCB_PHY_D_CTRL_RX_VCOM_MASK (0x300000UL) -#define LCB_PHY_D_CTRL_RX_VCOM_SHIFT (20U) -#define LCB_PHY_D_CTRL_RX_VCOM_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_VCOM_SHIFT) & LCB_PHY_D_CTRL_RX_VCOM_MASK) -#define LCB_PHY_D_CTRL_RX_VCOM_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_VCOM_MASK) >> LCB_PHY_D_CTRL_RX_VCOM_SHIFT) - -/* - * RX_RTERM (RW) - * - * Terminal impedance regulation control signal - * 0000: hi-z; - * 0001: 150ohm; - * 1000:100ohm; - * 1111:75ohm - */ -#define LCB_PHY_D_CTRL_RX_RTERM_MASK (0xF0000UL) -#define LCB_PHY_D_CTRL_RX_RTERM_SHIFT (16U) -#define LCB_PHY_D_CTRL_RX_RTERM_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_RTERM_SHIFT) & LCB_PHY_D_CTRL_RX_RTERM_MASK) -#define LCB_PHY_D_CTRL_RX_RTERM_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_RTERM_MASK) >> LCB_PHY_D_CTRL_RX_RTERM_SHIFT) - -/* - * RX_CTL (RW) - * - * bit 0 : Lane N Data MSB first enable signal. 0: LSB ; 1: MSB - * bit 1 : Lane N Data Polarity signal. 0: Not inverting; 1: Inverting - * bit [4:2] : Phase difference between the output first bit data (rxN[6:0]) and the input clock (RCKP/N) in LVDS Display Mode. - * bit 5 : Reserved - * bit 6 : Output data sampling clock control signal - * 0: Sampling using the rising edge of the clock pck. - * 1: Sampling using the falling edge of the clock pck. - * bit 7 : Reserved - * bit 8 : Data Lane N Skew adjust enable in LVDS Camera Mode. - * bit [12:9] : Data Lane N Skew adjust; 0000: min; 0111: default; 1111: max. - * bit [15:13] : Reserved - */ -#define LCB_PHY_D_CTRL_RX_CTL_MASK (0xFFFFU) -#define LCB_PHY_D_CTRL_RX_CTL_SHIFT (0U) -#define LCB_PHY_D_CTRL_RX_CTL_SET(x) (((uint32_t)(x) << LCB_PHY_D_CTRL_RX_CTL_SHIFT) & LCB_PHY_D_CTRL_RX_CTL_MASK) -#define LCB_PHY_D_CTRL_RX_CTL_GET(x) (((uint32_t)(x) & LCB_PHY_D_CTRL_RX_CTL_MASK) >> LCB_PHY_D_CTRL_RX_CTL_SHIFT) - -/* Bitfield definition for register array: PHY_CK_CTRL */ -/* - * RX_VCOM (RW) - * - * bit 1: Receiver hysteresis enable signal. 0: enable; 1: disable - * bit 0: Terminal impedance common mode selection control signal. 0: floating; 1: Ground - */ -#define LCB_PHY_CK_CTRL_RX_VCOM_MASK (0x300000UL) -#define LCB_PHY_CK_CTRL_RX_VCOM_SHIFT (20U) -#define LCB_PHY_CK_CTRL_RX_VCOM_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_VCOM_SHIFT) & LCB_PHY_CK_CTRL_RX_VCOM_MASK) -#define LCB_PHY_CK_CTRL_RX_VCOM_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_VCOM_MASK) >> LCB_PHY_CK_CTRL_RX_VCOM_SHIFT) - -/* - * RX_RTERM (RW) - * - * Terminal impedance regulation control signal - * 0000: hi-z; - * 0001: 150ohm; - * 1000:100ohm; - * 1111:75ohm - */ -#define LCB_PHY_CK_CTRL_RX_RTERM_MASK (0xF0000UL) -#define LCB_PHY_CK_CTRL_RX_RTERM_SHIFT (16U) -#define LCB_PHY_CK_CTRL_RX_RTERM_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_RTERM_SHIFT) & LCB_PHY_CK_CTRL_RX_RTERM_MASK) -#define LCB_PHY_CK_CTRL_RX_RTERM_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_RTERM_MASK) >> LCB_PHY_CK_CTRL_RX_RTERM_SHIFT) - -/* - * RX_CTL (RW) - * - * bit 0 : DLL loop delay adjustment minimum control signal - * 0: used for RCKP/RCKN’s frequency is 40Mhz~70Mhz - * 1:used for RCKP/RCKN’s frequency is 70Mhz~110Mhz - * bit [2:1] : DLL loop delay adjustment current regulation control signal. 00: min; 11: max - * bit 3 : Reserved - * bit 4 : Clock Lane Skew adjust enable in LVDS Camera Mode. - * bit [7:5] : Bus width selection in LVDS Camera Mode - * 000: 4bit; 001:6bit; 010:7bit; 011:8bit; 100:9bit; 101:10bit; 110:11bit; 111:12bit. - * bit [10:8] : DDR Clock duty cycle adjust in LVDS Camera Mode. - * bit [15:11] : Reserved - */ -#define LCB_PHY_CK_CTRL_RX_CTL_MASK (0xFFFFU) -#define LCB_PHY_CK_CTRL_RX_CTL_SHIFT (0U) -#define LCB_PHY_CK_CTRL_RX_CTL_SET(x) (((uint32_t)(x) << LCB_PHY_CK_CTRL_RX_CTL_SHIFT) & LCB_PHY_CK_CTRL_RX_CTL_MASK) -#define LCB_PHY_CK_CTRL_RX_CTL_GET(x) (((uint32_t)(x) & LCB_PHY_CK_CTRL_RX_CTL_MASK) >> LCB_PHY_CK_CTRL_RX_CTL_SHIFT) - -/* Bitfield definition for register array: PHY_ADJ_CTRL */ -/* - * LVDS_RX0_DLINE_ADJ (RW) - * - * LVDS RX PHY RX0 line: - * bit [7:0] : Lane N skew adjustment control signal between data and clock - * 0000000: max; 1111111: min - * bit 8 : Reserved - */ -#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK (0xFF000000UL) -#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT (24U) -#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK) -#define LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_RX0_DLINE_ADJ_SHIFT) - -/* - * LVDS_RX1_DLINE_ADJ (RW) - * - * LVDS RX PHY RX1 line: - * bit [7:0] : Lane N skew adjustment control signal between data and clock - * 0000000: max; 1111111: min - * bit 8 : Reserved - */ -#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK (0xFF0000UL) -#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT (16U) -#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK) -#define LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_RX1_DLINE_ADJ_SHIFT) - -/* - * LVDS_DLL_TUNING_INT (RW) - * - * LVDS RX PHY RXCK line: - * DLL loop delay coarse adjustment initial signal - * 00000000: min ; 11111111: max - */ -#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK (0x1FFU) -#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT (0U) -#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SET(x) (((uint32_t)(x) << LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT) & LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK) -#define LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_GET(x) (((uint32_t)(x) & LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_MASK) >> LCB_PHY_ADJ_CTRL_LVDS_DLL_TUNING_INT_SHIFT) - -/* Bitfield definition for register array: PHY_SU_CTRL */ -/* - * SU_CTRL (RW) - * - * bit [2:0] : Reference voltage/current adjustment control signal. 000: min; 111: max - * bit [3] : Internal bias circuit selection signal. 0: from Bandgap Mode; 1: from self-bias mode - * bit [7:4] : Reserved - */ -#define LCB_PHY_SU_CTRL_SU_CTRL_MASK (0xFFU) -#define LCB_PHY_SU_CTRL_SU_CTRL_SHIFT (0U) -#define LCB_PHY_SU_CTRL_SU_CTRL_SET(x) (((uint32_t)(x) << LCB_PHY_SU_CTRL_SU_CTRL_SHIFT) & LCB_PHY_SU_CTRL_SU_CTRL_MASK) -#define LCB_PHY_SU_CTRL_SU_CTRL_GET(x) (((uint32_t)(x) & LCB_PHY_SU_CTRL_SU_CTRL_MASK) >> LCB_PHY_SU_CTRL_SU_CTRL_SHIFT) - - - -/* PHY_POW_CTRL register group index macro definition */ -#define LCB_PHY_POW_CTRL_LVDS0 (0UL) -#define LCB_PHY_POW_CTRL_LVDS1 (1UL) - -/* PHY_D_CTRL register group index macro definition */ -#define LCB_PHY_D_CTRL_LVDS0_RX0 (0UL) -#define LCB_PHY_D_CTRL_LVDS0_RX1 (1UL) -#define LCB_PHY_D_CTRL_LVDS1_RX0 (2UL) -#define LCB_PHY_D_CTRL_LVDS1_RX1 (3UL) - -/* PHY_CK_CTRL register group index macro definition */ -#define LCB_PHY_CK_CTRL_LVDS0_RXCK (0UL) -#define LCB_PHY_CK_CTRL_LVDS1_RXCK (1UL) - -/* PHY_ADJ_CTRL register group index macro definition */ -#define LCB_PHY_ADJ_CTRL_LVDS0 (0UL) -#define LCB_PHY_ADJ_CTRL_LVDS1 (1UL) - -/* PHY_SU_CTRL register group index macro definition */ -#define LCB_PHY_SU_CTRL_LVDS0 (0UL) -#define LCB_PHY_SU_CTRL_LVDS1 (1UL) - - -#endif /* HPM_LCB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lcdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lcdc_regs.h deleted file mode 100644 index 5570d2096a7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lcdc_regs.h +++ /dev/null @@ -1,1234 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LCDC_H -#define HPM_LCDC_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t BGND_CL; /* 0x4: Background Color Register */ - __RW uint32_t DISP_WN_SIZE; /* 0x8: Display Window Size Register */ - __RW uint32_t HSYNC_PARA; /* 0xC: HSYNC Config Register */ - __RW uint32_t VSYNC_PARA; /* 0x10: VSYNC Config Register */ - __W uint32_t DMA_ST; /* 0x14: DMA Status Register */ - __RW uint32_t ST; /* 0x18: Status Register */ - __RW uint32_t INT_EN; /* 0x1C: Interrupt Enable Register */ - __RW uint32_t TXFIFO; /* 0x20: TX FIFO Register */ - __RW uint32_t CTRL_BP_V_RANGE; /* 0x24: BP_V range for CAMSYNC mode */ - __RW uint32_t CTRL_PW_V_RANGE; /* 0x28: PW_V range for CAMSYNC mode */ - __RW uint32_t CTRL_FP_V_RANGE; /* 0x2C: FP_V range for CAMSYNC mode */ - __RW uint32_t CAM_SYNC_HCNT_MIN; /* 0x30: min HCNT value for CAMSYNC mode */ - __RW uint32_t CAM_SYNC_HCNT_BEST; /* 0x34: best HCNT value for CAMSYNC mode */ - __RW uint32_t CAM_SYNC_HCNT_MAX; /* 0x38: max HCNT value for CAMSYNC mode */ - __R uint32_t CAM_SYNC_HCNT_ST; /* 0x3C: current HCNT value for CAMSYNC mode */ - __W uint32_t SHADOW_DONE_ST; /* 0x40: Shadow done status */ - __RW uint32_t SHADOW_DONE_INT_EN; /* 0x44: Shadow done interrupt enable */ - __R uint8_t RESERVED0[440]; /* 0x48 - 0x1FF: Reserved */ - struct { - __RW uint32_t LAYCTRL; /* 0x200: Layer Control Register */ - __RW uint32_t ALPHAS; /* 0x204: Layer Alpha Register */ - __RW uint32_t LAYSIZE; /* 0x208: Layer Size Register */ - __RW uint32_t LAYPOS; /* 0x20C: Layer Position Register */ - __RW uint32_t START0; /* 0x210: Layer Buffer Pointer Register */ - __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ - __RW uint32_t LINECFG; /* 0x218: Layer Bus Config Register */ - __RW uint32_t BG_CL; /* 0x21C: Layer Background Color Register */ - __RW uint32_t CSC_COEF0; /* 0x220: Layer Color Space Conversion Config Register 0 */ - __RW uint32_t CSC_COEF1; /* 0x224: Layer Color Space Conversion Config Register 1 */ - __RW uint32_t CSC_COEF2; /* 0x228: Layer Color Space Conversion Config Register 2 */ - __R uint8_t RESERVED1[20]; /* 0x22C - 0x23F: Reserved */ - } LAYER[8]; - __RW uint32_t CLUT_LOAD; /* 0x400: Clut Load Control Register */ -} LCDC_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SW_RST (RW) - * - * Software reset, high active. When write 1 ,all internal logical will be reset. - * 0b - No action - * 1b - All LCDC internal registers are forced into their reset state. Interface registers are not affected. - */ -#define LCDC_CTRL_SW_RST_MASK (0x80000000UL) -#define LCDC_CTRL_SW_RST_SHIFT (31U) -#define LCDC_CTRL_SW_RST_SET(x) (((uint32_t)(x) << LCDC_CTRL_SW_RST_SHIFT) & LCDC_CTRL_SW_RST_MASK) -#define LCDC_CTRL_SW_RST_GET(x) (((uint32_t)(x) & LCDC_CTRL_SW_RST_MASK) >> LCDC_CTRL_SW_RST_SHIFT) - -/* - * DISP_ON (RW) - * - * Display panel On/Off mode. - * 0b - Display Off. - * 1b - Display On. - * Display can be set off at any time, but it can only be set on after VS_BLANK status is asserted. - * So a good procedure to stop and turn on the display is: - * 1) clr VS_BLANK status - * 2) assert software reset - * 3) de-assert software reset - * 4) set display off - * 5) check VS_BLANK status until it is asserted, - * 6)reset the module, change settings - * 7) set display on - */ -#define LCDC_CTRL_DISP_ON_MASK (0x40000000UL) -#define LCDC_CTRL_DISP_ON_SHIFT (30U) -#define LCDC_CTRL_DISP_ON_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_ON_SHIFT) & LCDC_CTRL_DISP_ON_MASK) -#define LCDC_CTRL_DISP_ON_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_ON_MASK) >> LCDC_CTRL_DISP_ON_SHIFT) - -/* - * LINE_PATTERN (RW) - * - * LCDIF line output order. - * 000b - RGB. - * 001b - RBG. - * 010b - GBR. - * 011b - GRB. - * 100b - BRG. - * 101b - BGR. - */ -#define LCDC_CTRL_LINE_PATTERN_MASK (0x38000000UL) -#define LCDC_CTRL_LINE_PATTERN_SHIFT (27U) -#define LCDC_CTRL_LINE_PATTERN_SET(x) (((uint32_t)(x) << LCDC_CTRL_LINE_PATTERN_SHIFT) & LCDC_CTRL_LINE_PATTERN_MASK) -#define LCDC_CTRL_LINE_PATTERN_GET(x) (((uint32_t)(x) & LCDC_CTRL_LINE_PATTERN_MASK) >> LCDC_CTRL_LINE_PATTERN_SHIFT) - -/* - * DISP_MODE (RW) - * - * LCDIF operating mode. - * 00b - Normal mode. Panel content controlled by layer configuration. - * 01b - Test Mode1.(BGND Color Display) - * 10b - Test Mode2.(Column Color Bar) - * 11b - Test Mode3.(Row Color Bar) - */ -#define LCDC_CTRL_DISP_MODE_MASK (0x6000000UL) -#define LCDC_CTRL_DISP_MODE_SHIFT (25U) -#define LCDC_CTRL_DISP_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_DISP_MODE_SHIFT) & LCDC_CTRL_DISP_MODE_MASK) -#define LCDC_CTRL_DISP_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_DISP_MODE_MASK) >> LCDC_CTRL_DISP_MODE_SHIFT) - -/* - * BGDCL4CLR (RW) - * - * background color for clear mode when the alpha channel is 0 - */ -#define LCDC_CTRL_BGDCL4CLR_MASK (0x1000000UL) -#define LCDC_CTRL_BGDCL4CLR_SHIFT (24U) -#define LCDC_CTRL_BGDCL4CLR_SET(x) (((uint32_t)(x) << LCDC_CTRL_BGDCL4CLR_SHIFT) & LCDC_CTRL_BGDCL4CLR_MASK) -#define LCDC_CTRL_BGDCL4CLR_GET(x) (((uint32_t)(x) & LCDC_CTRL_BGDCL4CLR_MASK) >> LCDC_CTRL_BGDCL4CLR_SHIFT) - -/* - * ARQOS (RW) - * - * ARQOS for bus fabric arbitration - */ -#define LCDC_CTRL_ARQOS_MASK (0xF00000UL) -#define LCDC_CTRL_ARQOS_SHIFT (20U) -#define LCDC_CTRL_ARQOS_SET(x) (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) -#define LCDC_CTRL_ARQOS_GET(x) (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) - -/* - * SHADOW_OP (RW) - * - * Shadow Option - * 1: Use physical VSYNC (ST[VS_BLANK]) as shadow time. - * 0: Use layer internal logic VSYNC as shadow time. In general, this type of shadow control will have longer memory read time, so less underflow risk. - */ -#define LCDC_CTRL_SHADOW_OP_MASK (0x20000UL) -#define LCDC_CTRL_SHADOW_OP_SHIFT (17U) -#define LCDC_CTRL_SHADOW_OP_SET(x) (((uint32_t)(x) << LCDC_CTRL_SHADOW_OP_SHIFT) & LCDC_CTRL_SHADOW_OP_MASK) -#define LCDC_CTRL_SHADOW_OP_GET(x) (((uint32_t)(x) & LCDC_CTRL_SHADOW_OP_MASK) >> LCDC_CTRL_SHADOW_OP_SHIFT) - -/* - * B_LE_MODE (RW) - * - * Endianness mode for Blue Color Pads - * 1: Little endian. Pad 0 --> Color LSB 0 - * 0: Big Endian. Pad 0--> Color MSB 7 - */ -#define LCDC_CTRL_B_LE_MODE_MASK (0x10000UL) -#define LCDC_CTRL_B_LE_MODE_SHIFT (16U) -#define LCDC_CTRL_B_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_B_LE_MODE_SHIFT) & LCDC_CTRL_B_LE_MODE_MASK) -#define LCDC_CTRL_B_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_B_LE_MODE_MASK) >> LCDC_CTRL_B_LE_MODE_SHIFT) - -/* - * G_LE_MODE (RW) - * - * Endianness mode for Green Color Pads - * 1: Little endian. Pad 0 --> Color LSB 0 - * 0: Big Endian. Pad 0--> Color MSB 7 - */ -#define LCDC_CTRL_G_LE_MODE_MASK (0x8000U) -#define LCDC_CTRL_G_LE_MODE_SHIFT (15U) -#define LCDC_CTRL_G_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_G_LE_MODE_SHIFT) & LCDC_CTRL_G_LE_MODE_MASK) -#define LCDC_CTRL_G_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_G_LE_MODE_MASK) >> LCDC_CTRL_G_LE_MODE_SHIFT) - -/* - * R_LE_MODE (RW) - * - * Endianness mode for Red Color Pads - * 1: Little endian. Pad 0 --> Color LSB 0 - * 0: Big Endian. Pad 0--> Color MSB 7 - */ -#define LCDC_CTRL_R_LE_MODE_MASK (0x4000U) -#define LCDC_CTRL_R_LE_MODE_SHIFT (14U) -#define LCDC_CTRL_R_LE_MODE_SET(x) (((uint32_t)(x) << LCDC_CTRL_R_LE_MODE_SHIFT) & LCDC_CTRL_R_LE_MODE_MASK) -#define LCDC_CTRL_R_LE_MODE_GET(x) (((uint32_t)(x) & LCDC_CTRL_R_LE_MODE_MASK) >> LCDC_CTRL_R_LE_MODE_SHIFT) - -/* - * CAM_SYNC_EN (RW) - * - * Enable the VSYNC synchronization of CAM and LCDC - */ -#define LCDC_CTRL_CAM_SYNC_EN_MASK (0x2000U) -#define LCDC_CTRL_CAM_SYNC_EN_SHIFT (13U) -#define LCDC_CTRL_CAM_SYNC_EN_SET(x) (((uint32_t)(x) << LCDC_CTRL_CAM_SYNC_EN_SHIFT) & LCDC_CTRL_CAM_SYNC_EN_MASK) -#define LCDC_CTRL_CAM_SYNC_EN_GET(x) (((uint32_t)(x) & LCDC_CTRL_CAM_SYNC_EN_MASK) >> LCDC_CTRL_CAM_SYNC_EN_SHIFT) - -/* - * INV_PXDATA (RW) - * - * Indicates if value at the output (pixel data output) needs to be negated. - * 0b - Output is to remain same as the data inside memory - * 1b - Output to be negated from the data inside memory - */ -#define LCDC_CTRL_INV_PXDATA_MASK (0x10U) -#define LCDC_CTRL_INV_PXDATA_SHIFT (4U) -#define LCDC_CTRL_INV_PXDATA_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXDATA_SHIFT) & LCDC_CTRL_INV_PXDATA_MASK) -#define LCDC_CTRL_INV_PXDATA_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXDATA_MASK) >> LCDC_CTRL_INV_PXDATA_SHIFT) - -/* - * INV_PXCLK (RW) - * - * Polarity change of Pixel Clock. - * 0b - LCDC outputs data on the rising edge, and Display samples data on the falling edge - * 1b - LCDC outputs data on the falling edge, Display samples data on the rising edge - */ -#define LCDC_CTRL_INV_PXCLK_MASK (0x8U) -#define LCDC_CTRL_INV_PXCLK_SHIFT (3U) -#define LCDC_CTRL_INV_PXCLK_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_PXCLK_SHIFT) & LCDC_CTRL_INV_PXCLK_MASK) -#define LCDC_CTRL_INV_PXCLK_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_PXCLK_MASK) >> LCDC_CTRL_INV_PXCLK_SHIFT) - -/* - * INV_HREF (RW) - * - * Polarity of HREF - * 0b - HREF signal active HIGH, indicating active pixel data - * 1b - HREF signal active LOW - */ -#define LCDC_CTRL_INV_HREF_MASK (0x4U) -#define LCDC_CTRL_INV_HREF_SHIFT (2U) -#define LCDC_CTRL_INV_HREF_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HREF_SHIFT) & LCDC_CTRL_INV_HREF_MASK) -#define LCDC_CTRL_INV_HREF_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HREF_MASK) >> LCDC_CTRL_INV_HREF_SHIFT) - -/* - * INV_VSYNC (RW) - * - * Polarity of VSYNC - * 0b - VSYNC signal active HIGH - * 1b - VSYNC signal active LOW - */ -#define LCDC_CTRL_INV_VSYNC_MASK (0x2U) -#define LCDC_CTRL_INV_VSYNC_SHIFT (1U) -#define LCDC_CTRL_INV_VSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_VSYNC_SHIFT) & LCDC_CTRL_INV_VSYNC_MASK) -#define LCDC_CTRL_INV_VSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_VSYNC_MASK) >> LCDC_CTRL_INV_VSYNC_SHIFT) - -/* - * INV_HSYNC (RW) - * - * Polarity of HSYNC - * 0b - HSYNC signal active HIGH - * 1b - HSYNC signal active LOW - */ -#define LCDC_CTRL_INV_HSYNC_MASK (0x1U) -#define LCDC_CTRL_INV_HSYNC_SHIFT (0U) -#define LCDC_CTRL_INV_HSYNC_SET(x) (((uint32_t)(x) << LCDC_CTRL_INV_HSYNC_SHIFT) & LCDC_CTRL_INV_HSYNC_MASK) -#define LCDC_CTRL_INV_HSYNC_GET(x) (((uint32_t)(x) & LCDC_CTRL_INV_HSYNC_MASK) >> LCDC_CTRL_INV_HSYNC_SHIFT) - -/* Bitfield definition for register: BGND_CL */ -/* - * R (RW) - * - * Red component of the default color displayed in the sectors where no layer is active. - */ -#define LCDC_BGND_CL_R_MASK (0xFF0000UL) -#define LCDC_BGND_CL_R_SHIFT (16U) -#define LCDC_BGND_CL_R_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_R_SHIFT) & LCDC_BGND_CL_R_MASK) -#define LCDC_BGND_CL_R_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_R_MASK) >> LCDC_BGND_CL_R_SHIFT) - -/* - * G (RW) - * - * Green component of the default color displayed in the sectors where no layer is active. - */ -#define LCDC_BGND_CL_G_MASK (0xFF00U) -#define LCDC_BGND_CL_G_SHIFT (8U) -#define LCDC_BGND_CL_G_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_G_SHIFT) & LCDC_BGND_CL_G_MASK) -#define LCDC_BGND_CL_G_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_G_MASK) >> LCDC_BGND_CL_G_SHIFT) - -/* - * B (RW) - * - * Blue component of the default color displayed in the sectors where no layer is active. - */ -#define LCDC_BGND_CL_B_MASK (0xFFU) -#define LCDC_BGND_CL_B_SHIFT (0U) -#define LCDC_BGND_CL_B_SET(x) (((uint32_t)(x) << LCDC_BGND_CL_B_SHIFT) & LCDC_BGND_CL_B_MASK) -#define LCDC_BGND_CL_B_GET(x) (((uint32_t)(x) & LCDC_BGND_CL_B_MASK) >> LCDC_BGND_CL_B_SHIFT) - -/* Bitfield definition for register: DISP_WN_SIZE */ -/* - * Y (RW) - * - * Sets the display size vertical resolution in pixels. - */ -#define LCDC_DISP_WN_SIZE_Y_MASK (0xFFF0000UL) -#define LCDC_DISP_WN_SIZE_Y_SHIFT (16U) -#define LCDC_DISP_WN_SIZE_Y_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_Y_SHIFT) & LCDC_DISP_WN_SIZE_Y_MASK) -#define LCDC_DISP_WN_SIZE_Y_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_Y_MASK) >> LCDC_DISP_WN_SIZE_Y_SHIFT) - -/* - * X (RW) - * - * Sets the display size horizontal resolution in pixels. - */ -#define LCDC_DISP_WN_SIZE_X_MASK (0xFFFU) -#define LCDC_DISP_WN_SIZE_X_SHIFT (0U) -#define LCDC_DISP_WN_SIZE_X_SET(x) (((uint32_t)(x) << LCDC_DISP_WN_SIZE_X_SHIFT) & LCDC_DISP_WN_SIZE_X_MASK) -#define LCDC_DISP_WN_SIZE_X_GET(x) (((uint32_t)(x) & LCDC_DISP_WN_SIZE_X_MASK) >> LCDC_DISP_WN_SIZE_X_SHIFT) - -/* Bitfield definition for register: HSYNC_PARA */ -/* - * FP (RW) - * - * HSYNC front-porch pulse width (in pixel clock cycles). If zero, indicates no front-porch for HSYNC - */ -#define LCDC_HSYNC_PARA_FP_MASK (0x7FC00000UL) -#define LCDC_HSYNC_PARA_FP_SHIFT (22U) -#define LCDC_HSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_FP_SHIFT) & LCDC_HSYNC_PARA_FP_MASK) -#define LCDC_HSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_FP_MASK) >> LCDC_HSYNC_PARA_FP_SHIFT) - -/* - * BP (RW) - * - * HSYNC back-porch pulse width (in pixel clock cycles). If zero, indicates no back-porch for HSYNC - */ -#define LCDC_HSYNC_PARA_BP_MASK (0xFF800UL) -#define LCDC_HSYNC_PARA_BP_SHIFT (11U) -#define LCDC_HSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_BP_SHIFT) & LCDC_HSYNC_PARA_BP_MASK) -#define LCDC_HSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_BP_MASK) >> LCDC_HSYNC_PARA_BP_SHIFT) - -/* - * PW (RW) - * - * HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. - */ -#define LCDC_HSYNC_PARA_PW_MASK (0x1FFU) -#define LCDC_HSYNC_PARA_PW_SHIFT (0U) -#define LCDC_HSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_HSYNC_PARA_PW_SHIFT) & LCDC_HSYNC_PARA_PW_MASK) -#define LCDC_HSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_HSYNC_PARA_PW_MASK) >> LCDC_HSYNC_PARA_PW_SHIFT) - -/* Bitfield definition for register: VSYNC_PARA */ -/* - * FP (RW) - * - * VSYNC front-porch pulse width (in horizontal line cycles). If zero, means no front-porch for VSYNC - */ -#define LCDC_VSYNC_PARA_FP_MASK (0x7FC00000UL) -#define LCDC_VSYNC_PARA_FP_SHIFT (22U) -#define LCDC_VSYNC_PARA_FP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_FP_SHIFT) & LCDC_VSYNC_PARA_FP_MASK) -#define LCDC_VSYNC_PARA_FP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_FP_MASK) >> LCDC_VSYNC_PARA_FP_SHIFT) - -/* - * BP (RW) - * - * VSYNC back-porch pulse width (in horizontal line cycles). If zero, means no back-porch for VSYNC - */ -#define LCDC_VSYNC_PARA_BP_MASK (0xFF800UL) -#define LCDC_VSYNC_PARA_BP_SHIFT (11U) -#define LCDC_VSYNC_PARA_BP_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_BP_SHIFT) & LCDC_VSYNC_PARA_BP_MASK) -#define LCDC_VSYNC_PARA_BP_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_BP_MASK) >> LCDC_VSYNC_PARA_BP_SHIFT) - -/* - * PW (RW) - * - * VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. - */ -#define LCDC_VSYNC_PARA_PW_MASK (0x1FFU) -#define LCDC_VSYNC_PARA_PW_SHIFT (0U) -#define LCDC_VSYNC_PARA_PW_SET(x) (((uint32_t)(x) << LCDC_VSYNC_PARA_PW_SHIFT) & LCDC_VSYNC_PARA_PW_MASK) -#define LCDC_VSYNC_PARA_PW_GET(x) (((uint32_t)(x) & LCDC_VSYNC_PARA_PW_MASK) >> LCDC_VSYNC_PARA_PW_SHIFT) - -/* Bitfield definition for register: DMA_ST */ -/* - * DMA_ERR (W1C) - * - * plane n axi error. W1C. - */ -#define LCDC_DMA_ST_DMA_ERR_MASK (0xFF000000UL) -#define LCDC_DMA_ST_DMA_ERR_SHIFT (24U) -#define LCDC_DMA_ST_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA_ERR_SHIFT) & LCDC_DMA_ST_DMA_ERR_MASK) -#define LCDC_DMA_ST_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA_ERR_MASK) >> LCDC_DMA_ST_DMA_ERR_SHIFT) - -/* - * DMA1_DONE (W1C) - * - * Plane n frame 1 dma done. W1C. - */ -#define LCDC_DMA_ST_DMA1_DONE_MASK (0xFF0000UL) -#define LCDC_DMA_ST_DMA1_DONE_SHIFT (16U) -#define LCDC_DMA_ST_DMA1_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA1_DONE_SHIFT) & LCDC_DMA_ST_DMA1_DONE_MASK) -#define LCDC_DMA_ST_DMA1_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA1_DONE_MASK) >> LCDC_DMA_ST_DMA1_DONE_SHIFT) - -/* - * DMA0_DONE (W1C) - * - * Plane n frame 0 dma done. W1C. - */ -#define LCDC_DMA_ST_DMA0_DONE_MASK (0xFF00U) -#define LCDC_DMA_ST_DMA0_DONE_SHIFT (8U) -#define LCDC_DMA_ST_DMA0_DONE_SET(x) (((uint32_t)(x) << LCDC_DMA_ST_DMA0_DONE_SHIFT) & LCDC_DMA_ST_DMA0_DONE_MASK) -#define LCDC_DMA_ST_DMA0_DONE_GET(x) (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * P1_HANDSHAKE_ABORT (W1C) - * - * Plane 1 handshake abort error. W1C - */ -#define LCDC_ST_P1_HANDSHAKE_ABORT_MASK (0x100U) -#define LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT (8U) -#define LCDC_ST_P1_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT) & LCDC_ST_P1_HANDSHAKE_ABORT_MASK) -#define LCDC_ST_P1_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_ST_P1_HANDSHAKE_ABORT_MASK) >> LCDC_ST_P1_HANDSHAKE_ABORT_SHIFT) - -/* - * P0_HANDSHAKE_ABORT (W1C) - * - * Plane 0 handshake abort error. W1C - */ -#define LCDC_ST_P0_HANDSHAKE_ABORT_MASK (0x80U) -#define LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT (7U) -#define LCDC_ST_P0_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT) & LCDC_ST_P0_HANDSHAKE_ABORT_MASK) -#define LCDC_ST_P0_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_ST_P0_HANDSHAKE_ABORT_MASK) >> LCDC_ST_P0_HANDSHAKE_ABORT_SHIFT) - -/* - * CAM_HCNT_FAIL (W1C) - * - * During cam_vsync mode, sync fail due to hcnt out of acceptable ranges. W1C - */ -#define LCDC_ST_CAM_HCNT_FAIL_MASK (0x40U) -#define LCDC_ST_CAM_HCNT_FAIL_SHIFT (6U) -#define LCDC_ST_CAM_HCNT_FAIL_SET(x) (((uint32_t)(x) << LCDC_ST_CAM_HCNT_FAIL_SHIFT) & LCDC_ST_CAM_HCNT_FAIL_MASK) -#define LCDC_ST_CAM_HCNT_FAIL_GET(x) (((uint32_t)(x) & LCDC_ST_CAM_HCNT_FAIL_MASK) >> LCDC_ST_CAM_HCNT_FAIL_SHIFT) - -/* - * CAM_VSYNC_FAIL (W1C) - * - * During cam_vsync mode, sync fail due to out of vsync parameters. W1C - */ -#define LCDC_ST_CAM_VSYNC_FAIL_MASK (0x20U) -#define LCDC_ST_CAM_VSYNC_FAIL_SHIFT (5U) -#define LCDC_ST_CAM_VSYNC_FAIL_SET(x) (((uint32_t)(x) << LCDC_ST_CAM_VSYNC_FAIL_SHIFT) & LCDC_ST_CAM_VSYNC_FAIL_MASK) -#define LCDC_ST_CAM_VSYNC_FAIL_GET(x) (((uint32_t)(x) & LCDC_ST_CAM_VSYNC_FAIL_MASK) >> LCDC_ST_CAM_VSYNC_FAIL_SHIFT) - -/* - * SHADOW_DONE (RO) - * - * Shadow done status. This is an OR-ed signals of all shadow_done signals of all planes, and it can only be cleared by writing 1 for all asserted bits in SHADOW_DONE_ST register. - */ -#define LCDC_ST_SHADOW_DONE_MASK (0x10U) -#define LCDC_ST_SHADOW_DONE_SHIFT (4U) -#define LCDC_ST_SHADOW_DONE_GET(x) (((uint32_t)(x) & LCDC_ST_SHADOW_DONE_MASK) >> LCDC_ST_SHADOW_DONE_SHIFT) - -/* - * URGENT_UNDERRUN (W1C) - * - * Asserted when the output buffer urgent underrun condition encountered - */ -#define LCDC_ST_URGENT_UNDERRUN_MASK (0x8U) -#define LCDC_ST_URGENT_UNDERRUN_SHIFT (3U) -#define LCDC_ST_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_URGENT_UNDERRUN_SHIFT) & LCDC_ST_URGENT_UNDERRUN_MASK) -#define LCDC_ST_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_URGENT_UNDERRUN_MASK) >> LCDC_ST_URGENT_UNDERRUN_SHIFT) - -/* - * VS_BLANK (W1C) - * - * Asserted when in vertical blanking period. At the start of VSYNC - */ -#define LCDC_ST_VS_BLANK_MASK (0x4U) -#define LCDC_ST_VS_BLANK_SHIFT (2U) -#define LCDC_ST_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_ST_VS_BLANK_SHIFT) & LCDC_ST_VS_BLANK_MASK) -#define LCDC_ST_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_ST_VS_BLANK_MASK) >> LCDC_ST_VS_BLANK_SHIFT) - -/* - * UNDERRUN (W1C) - * - * Asserted when the output buffer underrun condition encountered - */ -#define LCDC_ST_UNDERRUN_MASK (0x2U) -#define LCDC_ST_UNDERRUN_SHIFT (1U) -#define LCDC_ST_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_ST_UNDERRUN_SHIFT) & LCDC_ST_UNDERRUN_MASK) -#define LCDC_ST_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_ST_UNDERRUN_MASK) >> LCDC_ST_UNDERRUN_SHIFT) - -/* - * VSYNC (W1C) - * - * Asserted when in vertical blanking period. At the end of VSYNC - */ -#define LCDC_ST_VSYNC_MASK (0x1U) -#define LCDC_ST_VSYNC_SHIFT (0U) -#define LCDC_ST_VSYNC_SET(x) (((uint32_t)(x) << LCDC_ST_VSYNC_SHIFT) & LCDC_ST_VSYNC_MASK) -#define LCDC_ST_VSYNC_GET(x) (((uint32_t)(x) & LCDC_ST_VSYNC_MASK) >> LCDC_ST_VSYNC_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * DMA_ERR (RW) - * - * Interrupt enable for DMA error - */ -#define LCDC_INT_EN_DMA_ERR_MASK (0xFF000000UL) -#define LCDC_INT_EN_DMA_ERR_SHIFT (24U) -#define LCDC_INT_EN_DMA_ERR_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_ERR_SHIFT) & LCDC_INT_EN_DMA_ERR_MASK) -#define LCDC_INT_EN_DMA_ERR_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_ERR_MASK) >> LCDC_INT_EN_DMA_ERR_SHIFT) - -/* - * DMA_DONE (RW) - * - * Interrupt enable for DMA done - */ -#define LCDC_INT_EN_DMA_DONE_MASK (0xFF0000UL) -#define LCDC_INT_EN_DMA_DONE_SHIFT (16U) -#define LCDC_INT_EN_DMA_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_DMA_DONE_SHIFT) & LCDC_INT_EN_DMA_DONE_MASK) -#define LCDC_INT_EN_DMA_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) - -/* - * HANDSHAKE_ABORT (RW) - * - * Handshake abort error int enable - */ -#define LCDC_INT_EN_HANDSHAKE_ABORT_MASK (0x80U) -#define LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT (7U) -#define LCDC_INT_EN_HANDSHAKE_ABORT_SET(x) (((uint32_t)(x) << LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT) & LCDC_INT_EN_HANDSHAKE_ABORT_MASK) -#define LCDC_INT_EN_HANDSHAKE_ABORT_GET(x) (((uint32_t)(x) & LCDC_INT_EN_HANDSHAKE_ABORT_MASK) >> LCDC_INT_EN_HANDSHAKE_ABORT_SHIFT) - -/* - * CAM_HCNT_FAIL (RW) - * - * hcnt out of acceptable ranges interrupt enable - */ -#define LCDC_INT_EN_CAM_HCNT_FAIL_MASK (0x40U) -#define LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT (6U) -#define LCDC_INT_EN_CAM_HCNT_FAIL_SET(x) (((uint32_t)(x) << LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT) & LCDC_INT_EN_CAM_HCNT_FAIL_MASK) -#define LCDC_INT_EN_CAM_HCNT_FAIL_GET(x) (((uint32_t)(x) & LCDC_INT_EN_CAM_HCNT_FAIL_MASK) >> LCDC_INT_EN_CAM_HCNT_FAIL_SHIFT) - -/* - * CAM_VSYNC_FAIL (RW) - * - * cam_vsync fail interrupt enable - */ -#define LCDC_INT_EN_CAM_VSYNC_FAIL_MASK (0x20U) -#define LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT (5U) -#define LCDC_INT_EN_CAM_VSYNC_FAIL_SET(x) (((uint32_t)(x) << LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT) & LCDC_INT_EN_CAM_VSYNC_FAIL_MASK) -#define LCDC_INT_EN_CAM_VSYNC_FAIL_GET(x) (((uint32_t)(x) & LCDC_INT_EN_CAM_VSYNC_FAIL_MASK) >> LCDC_INT_EN_CAM_VSYNC_FAIL_SHIFT) - -/* - * SHADOW_DONE (RW) - * - * Shadow done interrupt enable - */ -#define LCDC_INT_EN_SHADOW_DONE_MASK (0x10U) -#define LCDC_INT_EN_SHADOW_DONE_SHIFT (4U) -#define LCDC_INT_EN_SHADOW_DONE_SET(x) (((uint32_t)(x) << LCDC_INT_EN_SHADOW_DONE_SHIFT) & LCDC_INT_EN_SHADOW_DONE_MASK) -#define LCDC_INT_EN_SHADOW_DONE_GET(x) (((uint32_t)(x) & LCDC_INT_EN_SHADOW_DONE_MASK) >> LCDC_INT_EN_SHADOW_DONE_SHIFT) - -/* - * URGENT_UNDERRUN (RW) - * - * Asserted when the output buffer urgent underrun condition encountered - */ -#define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) -#define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) -#define LCDC_INT_EN_URGENT_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) -#define LCDC_INT_EN_URGENT_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) - -/* - * VS_BLANK (RW) - * - * Interrupt enable for start of sof - */ -#define LCDC_INT_EN_VS_BLANK_MASK (0x4U) -#define LCDC_INT_EN_VS_BLANK_SHIFT (2U) -#define LCDC_INT_EN_VS_BLANK_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VS_BLANK_SHIFT) & LCDC_INT_EN_VS_BLANK_MASK) -#define LCDC_INT_EN_VS_BLANK_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VS_BLANK_MASK) >> LCDC_INT_EN_VS_BLANK_SHIFT) - -/* - * UNDERRUN (RW) - * - * Interrupt enable for underrun - */ -#define LCDC_INT_EN_UNDERRUN_MASK (0x2U) -#define LCDC_INT_EN_UNDERRUN_SHIFT (1U) -#define LCDC_INT_EN_UNDERRUN_SET(x) (((uint32_t)(x) << LCDC_INT_EN_UNDERRUN_SHIFT) & LCDC_INT_EN_UNDERRUN_MASK) -#define LCDC_INT_EN_UNDERRUN_GET(x) (((uint32_t)(x) & LCDC_INT_EN_UNDERRUN_MASK) >> LCDC_INT_EN_UNDERRUN_SHIFT) - -/* - * VSYNC (RW) - * - * Interrupt enable for end of sof - */ -#define LCDC_INT_EN_VSYNC_MASK (0x1U) -#define LCDC_INT_EN_VSYNC_SHIFT (0U) -#define LCDC_INT_EN_VSYNC_SET(x) (((uint32_t)(x) << LCDC_INT_EN_VSYNC_SHIFT) & LCDC_INT_EN_VSYNC_MASK) -#define LCDC_INT_EN_VSYNC_GET(x) (((uint32_t)(x) & LCDC_INT_EN_VSYNC_MASK) >> LCDC_INT_EN_VSYNC_SHIFT) - -/* Bitfield definition for register: TXFIFO */ -/* - * THRSH (RW) - * - * Threshold to start the lcd raster (0--0x7F) - */ -#define LCDC_TXFIFO_THRSH_MASK (0xFFU) -#define LCDC_TXFIFO_THRSH_SHIFT (0U) -#define LCDC_TXFIFO_THRSH_SET(x) (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) -#define LCDC_TXFIFO_THRSH_GET(x) (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) - -/* Bitfield definition for register: CTRL_BP_V_RANGE */ -/* - * MAX (RW) - * - * Maximal BP_V values - */ -#define LCDC_CTRL_BP_V_RANGE_MAX_MASK (0x7FC0000UL) -#define LCDC_CTRL_BP_V_RANGE_MAX_SHIFT (18U) -#define LCDC_CTRL_BP_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_MAX_SHIFT) & LCDC_CTRL_BP_V_RANGE_MAX_MASK) -#define LCDC_CTRL_BP_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_MAX_MASK) >> LCDC_CTRL_BP_V_RANGE_MAX_SHIFT) - -/* - * BEST (RW) - * - * Best BP_V values - */ -#define LCDC_CTRL_BP_V_RANGE_BEST_MASK (0x3FE00UL) -#define LCDC_CTRL_BP_V_RANGE_BEST_SHIFT (9U) -#define LCDC_CTRL_BP_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_BEST_SHIFT) & LCDC_CTRL_BP_V_RANGE_BEST_MASK) -#define LCDC_CTRL_BP_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_BEST_MASK) >> LCDC_CTRL_BP_V_RANGE_BEST_SHIFT) - -/* - * MIN (RW) - * - * Minimal BP_V values - */ -#define LCDC_CTRL_BP_V_RANGE_MIN_MASK (0x1FFU) -#define LCDC_CTRL_BP_V_RANGE_MIN_SHIFT (0U) -#define LCDC_CTRL_BP_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_BP_V_RANGE_MIN_SHIFT) & LCDC_CTRL_BP_V_RANGE_MIN_MASK) -#define LCDC_CTRL_BP_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_BP_V_RANGE_MIN_MASK) >> LCDC_CTRL_BP_V_RANGE_MIN_SHIFT) - -/* Bitfield definition for register: CTRL_PW_V_RANGE */ -/* - * MAX (RW) - * - * Maximal PW_V values - */ -#define LCDC_CTRL_PW_V_RANGE_MAX_MASK (0x7FC0000UL) -#define LCDC_CTRL_PW_V_RANGE_MAX_SHIFT (18U) -#define LCDC_CTRL_PW_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_MAX_SHIFT) & LCDC_CTRL_PW_V_RANGE_MAX_MASK) -#define LCDC_CTRL_PW_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_MAX_MASK) >> LCDC_CTRL_PW_V_RANGE_MAX_SHIFT) - -/* - * BEST (RW) - * - * Best PW_V values - */ -#define LCDC_CTRL_PW_V_RANGE_BEST_MASK (0x3FE00UL) -#define LCDC_CTRL_PW_V_RANGE_BEST_SHIFT (9U) -#define LCDC_CTRL_PW_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_BEST_SHIFT) & LCDC_CTRL_PW_V_RANGE_BEST_MASK) -#define LCDC_CTRL_PW_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_BEST_MASK) >> LCDC_CTRL_PW_V_RANGE_BEST_SHIFT) - -/* - * MIN (RW) - * - * Minimal PW_V values - */ -#define LCDC_CTRL_PW_V_RANGE_MIN_MASK (0x1FFU) -#define LCDC_CTRL_PW_V_RANGE_MIN_SHIFT (0U) -#define LCDC_CTRL_PW_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_PW_V_RANGE_MIN_SHIFT) & LCDC_CTRL_PW_V_RANGE_MIN_MASK) -#define LCDC_CTRL_PW_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_PW_V_RANGE_MIN_MASK) >> LCDC_CTRL_PW_V_RANGE_MIN_SHIFT) - -/* Bitfield definition for register: CTRL_FP_V_RANGE */ -/* - * MAX (RW) - * - * Maximal FP_V values - */ -#define LCDC_CTRL_FP_V_RANGE_MAX_MASK (0x7FC0000UL) -#define LCDC_CTRL_FP_V_RANGE_MAX_SHIFT (18U) -#define LCDC_CTRL_FP_V_RANGE_MAX_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_MAX_SHIFT) & LCDC_CTRL_FP_V_RANGE_MAX_MASK) -#define LCDC_CTRL_FP_V_RANGE_MAX_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_MAX_MASK) >> LCDC_CTRL_FP_V_RANGE_MAX_SHIFT) - -/* - * BEST (RW) - * - * Best FP_V values - */ -#define LCDC_CTRL_FP_V_RANGE_BEST_MASK (0x3FE00UL) -#define LCDC_CTRL_FP_V_RANGE_BEST_SHIFT (9U) -#define LCDC_CTRL_FP_V_RANGE_BEST_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_BEST_SHIFT) & LCDC_CTRL_FP_V_RANGE_BEST_MASK) -#define LCDC_CTRL_FP_V_RANGE_BEST_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_BEST_MASK) >> LCDC_CTRL_FP_V_RANGE_BEST_SHIFT) - -/* - * MIN (RW) - * - * Minimal FP_V values - */ -#define LCDC_CTRL_FP_V_RANGE_MIN_MASK (0x1FFU) -#define LCDC_CTRL_FP_V_RANGE_MIN_SHIFT (0U) -#define LCDC_CTRL_FP_V_RANGE_MIN_SET(x) (((uint32_t)(x) << LCDC_CTRL_FP_V_RANGE_MIN_SHIFT) & LCDC_CTRL_FP_V_RANGE_MIN_MASK) -#define LCDC_CTRL_FP_V_RANGE_MIN_GET(x) (((uint32_t)(x) & LCDC_CTRL_FP_V_RANGE_MIN_MASK) >> LCDC_CTRL_FP_V_RANGE_MIN_SHIFT) - -/* Bitfield definition for register: CAM_SYNC_HCNT_MIN */ -/* - * VAL (RW) - * - * minimal acceptable HCNT Value - */ -#define LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK (0xFFFFU) -#define LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT (0U) -#define LCDC_CAM_SYNC_HCNT_MIN_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK) -#define LCDC_CAM_SYNC_HCNT_MIN_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_MIN_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_MIN_VAL_SHIFT) - -/* Bitfield definition for register: CAM_SYNC_HCNT_BEST */ -/* - * HYST (RW) - * - * hysteresys of acceptable HCNT Value - */ -#define LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK (0xFF0000UL) -#define LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT (16U) -#define LCDC_CAM_SYNC_HCNT_BEST_HYST_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT) & LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK) -#define LCDC_CAM_SYNC_HCNT_BEST_HYST_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_BEST_HYST_MASK) >> LCDC_CAM_SYNC_HCNT_BEST_HYST_SHIFT) - -/* - * VAL (RW) - * - * best acceptable HCNT Value - */ -#define LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK (0xFFFFU) -#define LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT (0U) -#define LCDC_CAM_SYNC_HCNT_BEST_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK) -#define LCDC_CAM_SYNC_HCNT_BEST_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_BEST_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_BEST_VAL_SHIFT) - -/* Bitfield definition for register: CAM_SYNC_HCNT_MAX */ -/* - * VAL (RW) - * - * maximal acceptable HCNT Value - */ -#define LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK (0xFFFFU) -#define LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT (0U) -#define LCDC_CAM_SYNC_HCNT_MAX_VAL_SET(x) (((uint32_t)(x) << LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT) & LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK) -#define LCDC_CAM_SYNC_HCNT_MAX_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_MAX_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_MAX_VAL_SHIFT) - -/* Bitfield definition for register: CAM_SYNC_HCNT_ST */ -/* - * VAL (RO) - * - * current HCNT value - */ -#define LCDC_CAM_SYNC_HCNT_ST_VAL_MASK (0xFFFFU) -#define LCDC_CAM_SYNC_HCNT_ST_VAL_SHIFT (0U) -#define LCDC_CAM_SYNC_HCNT_ST_VAL_GET(x) (((uint32_t)(x) & LCDC_CAM_SYNC_HCNT_ST_VAL_MASK) >> LCDC_CAM_SYNC_HCNT_ST_VAL_SHIFT) - -/* Bitfield definition for register: SHADOW_DONE_ST */ -/* - * VAL (W1C) - * - * current shadow_done value for plane 7,...,0 respectively - */ -#define LCDC_SHADOW_DONE_ST_VAL_MASK (0xFFU) -#define LCDC_SHADOW_DONE_ST_VAL_SHIFT (0U) -#define LCDC_SHADOW_DONE_ST_VAL_SET(x) (((uint32_t)(x) << LCDC_SHADOW_DONE_ST_VAL_SHIFT) & LCDC_SHADOW_DONE_ST_VAL_MASK) -#define LCDC_SHADOW_DONE_ST_VAL_GET(x) (((uint32_t)(x) & LCDC_SHADOW_DONE_ST_VAL_MASK) >> LCDC_SHADOW_DONE_ST_VAL_SHIFT) - -/* Bitfield definition for register: SHADOW_DONE_INT_EN */ -/* - * VAL (RW) - * - * shadow_done interrupt enable for plane 7,...,0 respectively - */ -#define LCDC_SHADOW_DONE_INT_EN_VAL_MASK (0xFFU) -#define LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT (0U) -#define LCDC_SHADOW_DONE_INT_EN_VAL_SET(x) (((uint32_t)(x) << LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT) & LCDC_SHADOW_DONE_INT_EN_VAL_MASK) -#define LCDC_SHADOW_DONE_INT_EN_VAL_GET(x) (((uint32_t)(x) & LCDC_SHADOW_DONE_INT_EN_VAL_MASK) >> LCDC_SHADOW_DONE_INT_EN_VAL_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LAYCTRL */ -/* - * RESAMPLE_VRATIO (RW) - * - * Resample the input data stream in the verticle direction - * 0: don't resample - * positive n: upsample-by-n+1 (2 to 8) - * negtive n: downsample-by-n+1 (2 to 8) - */ -#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK (0xF0000000UL) -#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT (28U) -#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT) & LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK) -#define LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_MASK) >> LCDC_LAYER_LAYCTRL_RESAMPLE_VRATIO_SHIFT) - -/* - * RESAMPLE_HRATIO (RW) - * - * Resample the input data stream in the horizontal direction - * 0: don't resample - * positive n: upsample-by-n+1 (2 to 8) - * negtive n: downsample-by-n+1 (2 to 8) - */ -#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK (0xF000000UL) -#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT (24U) -#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT) & LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK) -#define LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_MASK) >> LCDC_LAYER_LAYCTRL_RESAMPLE_HRATIO_SHIFT) - -/* - * NORMLZ_OUT (RW) - * - * Normalize the pixel out for the not-overlapped pixels - */ -#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK (0x800000UL) -#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT (23U) -#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT) & LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK) -#define LCDC_LAYER_LAYCTRL_NORMLZ_OUT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_NORMLZ_OUT_MASK) >> LCDC_LAYER_LAYCTRL_NORMLZ_OUT_SHIFT) - -/* - * HANDSHAKE_ABORT_INT_EN (RW) - * - * 1: Enable the handshake abort error interrupt. - * 0: don't Enable the handshake abort error interrupt. - * Abort is generated when the LCDC is going to switch bank to a new bank, and the new bank data is not ready yet. - * Abort is only useful when communicating with the offline calculator (such as PDMA as the active pixel generator mode). - * PDMA as the active generator mode, means it is the first pixel generator with data sources from offline memory, and not from on-the-fly streaming data (such as camera captured data). - * While with on-the-fly streaming data, error condition is indicated by display buffer underflow. - */ -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK (0x400000UL) -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT (22U) -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT) & LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK) -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_MASK) >> LCDC_LAYER_LAYCTRL_HANDSHAKE_ABORT_INT_EN_SHIFT) - -/* - * HANDSHAKE_BUFSIZE (RW) - * - * 1: handshake buffer is 16 rows hight per ping or pang buf. - * 0: handshake buffer is 8 rows hight per ping or pang buf. - */ -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK (0x200000UL) -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT (21U) -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT) & LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK) -#define LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_MASK) >> LCDC_LAYER_LAYCTRL_HANDSHAKE_BUFSIZE_SHIFT) - -/* - * ENABLE_HANDSHAKE (RW) - * - * Enable handshake with input pixel controller. When this is set, the LCDC will not process an entire framebuffer, - * but will instead process rows of NxN blocks in a double-buffer handshake with the input pixel controlller. This enables - * the use of the onboard SRAM for a partial frame buffer. Only valid for Plane 0 & 1. - * 1: handshake enabled - * 0: handshake disabled - */ -#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK (0x100000UL) -#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT (20U) -#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT) & LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK) -#define LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_MASK) >> LCDC_LAYER_LAYCTRL_ENABLE_HANDSHAKE_SHIFT) - -/* - * PACK_DIR (RW) - * - * The byte sequence of the 4 bytes in a 32-bit word. - * 1: {A0, A1, A2, A3} byte re-ordered. - * 0: {A3, A2, A1, A0} the normal case with no byte re-order - */ -#define LCDC_LAYER_LAYCTRL_PACK_DIR_MASK (0x80000UL) -#define LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT (19U) -#define LCDC_LAYER_LAYCTRL_PACK_DIR_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) -#define LCDC_LAYER_LAYCTRL_PACK_DIR_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) >> LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) - -/* - * SHADOW_LOAD_EN (RW) - * - * Shadow Load Enable - * The SHADOW_LOAD_EN bit is written to 1 by software after all DMA control registers are written. If set to 1, shadowed control registers are updated to the active control registers on internal logical VSYNC of next frame. If set to 0, shadowed control registers are not loaded into the active control registers. The previous active control register settings will be used to process the next frame. Hardware will automatically clear this bit, when the shadow registers are loaded to the active control regsisters. - */ -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK (0x10000UL) -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT (16U) -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) -#define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) >> LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) - -/* - * YUV_FORMAT (RW) - * - * The YUV422 input format selection. - * 00b - The YVYU422 8bit sequence is U1,Y1,V1,Y2 - * 01b - The YVYU422 8bit sequence is V1,Y1,U1,Y2 - * 10b - The YVYU422 8bit sequence is Y1,U1,Y2,V1 - * 11b - The YVYU422 8bit sequence is Y1,V1,Y2,U1 - * If not YUV422 mode, - * FORMAT[0]: asserted to exchange sequence inside the bytes. Org [15:8]-->New[8:15], Org [7:0]-->New[0:7]. (First exchange) - * FORMAT[1]: asserted to exchange the sequence of the odd and even 8 bits. Org Even [7:0]-->New[15:8], Org Odd [15:8]-->New[7:0]. (Second exchange) - */ -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK (0xC000U) -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT (14U) -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) -#define LCDC_LAYER_LAYCTRL_YUV_FORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) >> LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) - -/* - * PIXFORMAT (RW) - * - * Layer encoding format (bit per pixel) - * 0000b - 1 bpp (pixel width must be multiples of 32), pixel sequence is from LSB to MSB in 32b word. - * 0001b - 2 bpp (pixel width must be multiples of 16), pixel sequence is from LSB to MSB in 32b word. - * 0010b - 4 bpp (pixel width must be multiples of 8), pixel sequence is from LSB to MSB in 32b word. - * 0011b - 8 bpp (pixel width must be multiples of 4), pixel sequence is from LSB to MSB in 32b word. - * 0100b - 16 bpp (RGB565), the low byte contains the full R component. - * 0111b - YCbCr422 (Only layer 0/1 can support this format), byte sequence determined by LAYCTRL[YUV_FORMAT] - * 1001b - 32 bpp (ARGB8888), byte sequence as B,G,R,A - * 1011b - Y8 (pixel width must be multiples of 4), byte sequence as Y1,Y2,Y3,Y4 - */ -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK (0x3C00U) -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT (10U) -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) -#define LCDC_LAYER_LAYCTRL_PIXFORMAT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) >> LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) - -/* - * LOCALPHA_OP (RW) - * - * The usage of the LOCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the LOCALPHA[7:0] is invalid, use the alpha value from the data stream - * 1: the LOCALPHA[7:0] is used to override the alpha value in the data stream (useful when the data stream has no alpha info) - * 2: the LOCALPHA[7:0] is used to scale the alpha value from the data stream - * Others: Reserved - */ -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK (0x300U) -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT (8U) -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) -#define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) - -/* - * INALPHA_OP (RW) - * - * The usage of the INALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the INALPHA[7:0] is invalid, use the alpha value from previous pipeline - * 1: the INALPHA[7:0] is used to override the alpha value from previous pipeline. (useful when the corresponding data stream has no alpha info) - * 2: the INALPHA[7:0] is used to scale the alpha value from previous pipeline - * Others: Reserved - */ -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK (0xC0U) -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT (6U) -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) -#define LCDC_LAYER_LAYCTRL_INALPHA_OP_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) - -/* - * AB_MODE (RW) - * - * Alpha Blending Mode - * 0: SKBlendMode_Clear; - * 3: SKBlendMode_SrcOver - * 14: SRC org - * 15: DST org - * Others: Reserved. - */ -#define LCDC_LAYER_LAYCTRL_AB_MODE_MASK (0x3CU) -#define LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT (2U) -#define LCDC_LAYER_LAYCTRL_AB_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) -#define LCDC_LAYER_LAYCTRL_AB_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) >> LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) - -/* - * EN (RW) - * - * Asserted when the layer is enabled. If this layer is not enabled, it means a bypassing plane. - */ -#define LCDC_LAYER_LAYCTRL_EN_MASK (0x1U) -#define LCDC_LAYER_LAYCTRL_EN_SHIFT (0U) -#define LCDC_LAYER_LAYCTRL_EN_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_EN_SHIFT) & LCDC_LAYER_LAYCTRL_EN_MASK) -#define LCDC_LAYER_LAYCTRL_EN_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_EN_MASK) >> LCDC_LAYER_LAYCTRL_EN_SHIFT) - -/* Bitfield definition for register of struct array LAYER: ALPHAS */ -/* - * LOCD (RW) - * - * The system alpha value for the data stream of current layer stream (SRC) - */ -#define LCDC_LAYER_ALPHAS_LOCD_MASK (0xFF00U) -#define LCDC_LAYER_ALPHAS_LOCD_SHIFT (8U) -#define LCDC_LAYER_ALPHAS_LOCD_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_LOCD_SHIFT) & LCDC_LAYER_ALPHAS_LOCD_MASK) -#define LCDC_LAYER_ALPHAS_LOCD_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_LOCD_MASK) >> LCDC_LAYER_ALPHAS_LOCD_SHIFT) - -/* - * IND (RW) - * - * The system alpha value for the input stream from previous stage (DST) - */ -#define LCDC_LAYER_ALPHAS_IND_MASK (0xFFU) -#define LCDC_LAYER_ALPHAS_IND_SHIFT (0U) -#define LCDC_LAYER_ALPHAS_IND_SET(x) (((uint32_t)(x) << LCDC_LAYER_ALPHAS_IND_SHIFT) & LCDC_LAYER_ALPHAS_IND_MASK) -#define LCDC_LAYER_ALPHAS_IND_GET(x) (((uint32_t)(x) & LCDC_LAYER_ALPHAS_IND_MASK) >> LCDC_LAYER_ALPHAS_IND_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LAYSIZE */ -/* - * HEIGHT (RW) - * - * Height of the layer in pixels - */ -#define LCDC_LAYER_LAYSIZE_HEIGHT_MASK (0xFFF0000UL) -#define LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT (16U) -#define LCDC_LAYER_LAYSIZE_HEIGHT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) -#define LCDC_LAYER_LAYSIZE_HEIGHT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) >> LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) - -/* - * WIDTH (RW) - * - * Width of the layer in pixels (Note: not actual width-1) - * The layer width must be in multiples of the number of pixels that can be stored in 32 bits, and therefore differs depending on color encoding. For example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. - */ -#define LCDC_LAYER_LAYSIZE_WIDTH_MASK (0xFFFU) -#define LCDC_LAYER_LAYSIZE_WIDTH_SHIFT (0U) -#define LCDC_LAYER_LAYSIZE_WIDTH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) -#define LCDC_LAYER_LAYSIZE_WIDTH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LAYPOS */ -/* - * Y (RW) - * - * The vertical position of top row of the layer, where 0 is the top row of the panel, positive values are below the top row of the panel. - */ -#define LCDC_LAYER_LAYPOS_Y_MASK (0xFFFF0000UL) -#define LCDC_LAYER_LAYPOS_Y_SHIFT (16U) -#define LCDC_LAYER_LAYPOS_Y_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_Y_SHIFT) & LCDC_LAYER_LAYPOS_Y_MASK) -#define LCDC_LAYER_LAYPOS_Y_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_Y_MASK) >> LCDC_LAYER_LAYPOS_Y_SHIFT) - -/* - * X (RW) - * - * The horizontal position of left-hand column of the layer, where 0 is the left-hand column of the panel, positive values are to the right the left-hand column of the panel. - */ -#define LCDC_LAYER_LAYPOS_X_MASK (0xFFFFU) -#define LCDC_LAYER_LAYPOS_X_SHIFT (0U) -#define LCDC_LAYER_LAYPOS_X_SET(x) (((uint32_t)(x) << LCDC_LAYER_LAYPOS_X_SHIFT) & LCDC_LAYER_LAYPOS_X_MASK) -#define LCDC_LAYER_LAYPOS_X_GET(x) (((uint32_t)(x) & LCDC_LAYER_LAYPOS_X_MASK) >> LCDC_LAYER_LAYPOS_X_SHIFT) - -/* Bitfield definition for register of struct array LAYER: START0 */ -/* - * ADDR0 (RW) - * - * Input buffer Start address 0 - */ -#define LCDC_LAYER_START0_ADDR0_MASK (0xFFFFFFFFUL) -#define LCDC_LAYER_START0_ADDR0_SHIFT (0U) -#define LCDC_LAYER_START0_ADDR0_SET(x) (((uint32_t)(x) << LCDC_LAYER_START0_ADDR0_SHIFT) & LCDC_LAYER_START0_ADDR0_MASK) -#define LCDC_LAYER_START0_ADDR0_GET(x) (((uint32_t)(x) & LCDC_LAYER_START0_ADDR0_MASK) >> LCDC_LAYER_START0_ADDR0_SHIFT) - -/* Bitfield definition for register of struct array LAYER: LINECFG */ -/* - * MPT_SIZE (RW) - * - * Maximal Per Transfer Data Size: - * 0: 64 bytes - * 1: 128 bytes - * 2: 256 bytes - * 3: 512 bytes - * 4: 1024 bytes - */ -#define LCDC_LAYER_LINECFG_MPT_SIZE_MASK (0xE0000000UL) -#define LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT (29U) -#define LCDC_LAYER_LINECFG_MPT_SIZE_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) -#define LCDC_LAYER_LINECFG_MPT_SIZE_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) >> LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) - -/* - * MAX_OT (RW) - * - * the number of outstanding axi read transactions. - * If zero, it means max 8. - */ -#define LCDC_LAYER_LINECFG_MAX_OT_MASK (0xE00000UL) -#define LCDC_LAYER_LINECFG_MAX_OT_SHIFT (21U) -#define LCDC_LAYER_LINECFG_MAX_OT_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_MAX_OT_SHIFT) & LCDC_LAYER_LINECFG_MAX_OT_MASK) -#define LCDC_LAYER_LINECFG_MAX_OT_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_MAX_OT_MASK) >> LCDC_LAYER_LINECFG_MAX_OT_SHIFT) - -/* - * PITCH (RW) - * - * Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity is supported, but SW should align to 64B boundary. - */ -#define LCDC_LAYER_LINECFG_PITCH_MASK (0xFFFFU) -#define LCDC_LAYER_LINECFG_PITCH_SHIFT (0U) -#define LCDC_LAYER_LINECFG_PITCH_SET(x) (((uint32_t)(x) << LCDC_LAYER_LINECFG_PITCH_SHIFT) & LCDC_LAYER_LINECFG_PITCH_MASK) -#define LCDC_LAYER_LINECFG_PITCH_GET(x) (((uint32_t)(x) & LCDC_LAYER_LINECFG_PITCH_MASK) >> LCDC_LAYER_LINECFG_PITCH_SHIFT) - -/* Bitfield definition for register of struct array LAYER: BG_CL */ -/* - * ARGB (RW) - * - * ARGB8888. It is only useful in the last active stage in the pipeline. - */ -#define LCDC_LAYER_BG_CL_ARGB_MASK (0xFFFFFFFFUL) -#define LCDC_LAYER_BG_CL_ARGB_SHIFT (0U) -#define LCDC_LAYER_BG_CL_ARGB_SET(x) (((uint32_t)(x) << LCDC_LAYER_BG_CL_ARGB_SHIFT) & LCDC_LAYER_BG_CL_ARGB_MASK) -#define LCDC_LAYER_BG_CL_ARGB_GET(x) (((uint32_t)(x) & LCDC_LAYER_BG_CL_ARGB_MASK) >> LCDC_LAYER_BG_CL_ARGB_SHIFT) - -/* Bitfield definition for register of struct array LAYER: CSC_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * This bit changes the behavior when performing U/V converting. - * 0b - Converting YUV to RGB data - * 1b - Converting YCbCr to RGB data - */ -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) -#define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) >> LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Enable the CSC unit in the LCDC plane data path. - * 0b - The CSC is bypassed and the input pixels are RGB data already - * 1b - The CSC is enabled and the pixels will be converted to RGB data - * This bit will be shadowed. - */ -#define LCDC_LAYER_CSC_COEF0_ENABLE_MASK (0x40000000UL) -#define LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT (30U) -#define LCDC_LAYER_CSC_COEF0_ENABLE_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) -#define LCDC_LAYER_CSC_COEF0_ENABLE_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) >> LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define LCDC_LAYER_CSC_COEF0_C0_MASK (0x1FFC0000UL) -#define LCDC_LAYER_CSC_COEF0_C0_SHIFT (18U) -#define LCDC_LAYER_CSC_COEF0_C0_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_C0_SHIFT) & LCDC_LAYER_CSC_COEF0_C0_MASK) -#define LCDC_LAYER_CSC_COEF0_C0_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_C0_MASK) >> LCDC_LAYER_CSC_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT (9U) -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) -#define LCDC_LAYER_CSC_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT (0U) -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) -#define LCDC_LAYER_CSC_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register of struct array LAYER: CSC_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define LCDC_LAYER_CSC_COEF1_C1_MASK (0x7FF0000UL) -#define LCDC_LAYER_CSC_COEF1_C1_SHIFT (16U) -#define LCDC_LAYER_CSC_COEF1_C1_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C1_SHIFT) & LCDC_LAYER_CSC_COEF1_C1_MASK) -#define LCDC_LAYER_CSC_COEF1_C1_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C1_MASK) >> LCDC_LAYER_CSC_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define LCDC_LAYER_CSC_COEF1_C4_MASK (0x7FFU) -#define LCDC_LAYER_CSC_COEF1_C4_SHIFT (0U) -#define LCDC_LAYER_CSC_COEF1_C4_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C4_SHIFT) & LCDC_LAYER_CSC_COEF1_C4_MASK) -#define LCDC_LAYER_CSC_COEF1_C4_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C4_MASK) >> LCDC_LAYER_CSC_COEF1_C4_SHIFT) - -/* Bitfield definition for register of struct array LAYER: CSC_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define LCDC_LAYER_CSC_COEF2_C2_MASK (0x7FF0000UL) -#define LCDC_LAYER_CSC_COEF2_C2_SHIFT (16U) -#define LCDC_LAYER_CSC_COEF2_C2_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C2_SHIFT) & LCDC_LAYER_CSC_COEF2_C2_MASK) -#define LCDC_LAYER_CSC_COEF2_C2_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C2_MASK) >> LCDC_LAYER_CSC_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define LCDC_LAYER_CSC_COEF2_C3_MASK (0x7FFU) -#define LCDC_LAYER_CSC_COEF2_C3_SHIFT (0U) -#define LCDC_LAYER_CSC_COEF2_C3_SET(x) (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C3_SHIFT) & LCDC_LAYER_CSC_COEF2_C3_MASK) -#define LCDC_LAYER_CSC_COEF2_C3_GET(x) (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) - -/* Bitfield definition for register: CLUT_LOAD */ -/* - * STR_HIGH (RW) - * - * 1'b1: Store 8+ CLUT tables through APB - * 1'b0: Store 0-7 CLUT tables through APB - */ -#define LCDC_CLUT_LOAD_STR_HIGH_MASK (0x80000000UL) -#define LCDC_CLUT_LOAD_STR_HIGH_SHIFT (31U) -#define LCDC_CLUT_LOAD_STR_HIGH_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_STR_HIGH_SHIFT) & LCDC_CLUT_LOAD_STR_HIGH_MASK) -#define LCDC_CLUT_LOAD_STR_HIGH_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_STR_HIGH_MASK) >> LCDC_CLUT_LOAD_STR_HIGH_SHIFT) - -/* - * SEL_NUM (RW) - * - * Selected CLUT Number - * The SEL_CLUT_NUM is used to select which plane's CLUT need to be updated. The hardware can only backup one CLUT setting and load, so the SEL_CLUT_NUM can't be changed when CLUT_LOAD[UPDATE_EN] is 1. - * . 3'h0 - PLANE 0 - * . 3'h1 - PLANE 1 - * . ------ - * . 3'h7 - PLANE 7 - * CLUT 8 can be modified via APB even when display is on. - * Currently CLUT for plane 0..7 cannot be modified via APB when display is on. Can only be updated via CLUT_LOAD[UPDATE_EN] bit. - */ -#define LCDC_CLUT_LOAD_SEL_NUM_MASK (0x70U) -#define LCDC_CLUT_LOAD_SEL_NUM_SHIFT (4U) -#define LCDC_CLUT_LOAD_SEL_NUM_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_SEL_NUM_SHIFT) & LCDC_CLUT_LOAD_SEL_NUM_MASK) -#define LCDC_CLUT_LOAD_SEL_NUM_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_SEL_NUM_MASK) >> LCDC_CLUT_LOAD_SEL_NUM_SHIFT) - -/* - * UPDATE_EN (RW) - * - * CLUT Update Enable - * The bit is written to 1 when software want to update the Color Look Up Tables during display. - * If set to 1, software update selected CLUT due to SEL_CLUT_NUM setting, the table will be copied from CLUT8 during vertical blanking period after SHADOW_LOAD_EN is set to 1. - * If set to 0, software can update CLUT8 directly according to the CLUT memory map. - * Hardware will automatically clear this bit when selected CLUT is updated according to SEL_CLUT_NUM. - */ -#define LCDC_CLUT_LOAD_UPDATE_EN_MASK (0x1U) -#define LCDC_CLUT_LOAD_UPDATE_EN_SHIFT (0U) -#define LCDC_CLUT_LOAD_UPDATE_EN_SET(x) (((uint32_t)(x) << LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) -#define LCDC_CLUT_LOAD_UPDATE_EN_GET(x) (((uint32_t)(x) & LCDC_CLUT_LOAD_UPDATE_EN_MASK) >> LCDC_CLUT_LOAD_UPDATE_EN_SHIFT) - - - -/* LAYER register group index macro definition */ -#define LCDC_LAYER_0 (0UL) -#define LCDC_LAYER_1 (1UL) -#define LCDC_LAYER_2 (2UL) -#define LCDC_LAYER_3 (3UL) -#define LCDC_LAYER_4 (4UL) -#define LCDC_LAYER_5 (5UL) -#define LCDC_LAYER_6 (6UL) -#define LCDC_LAYER_7 (7UL) - - -#endif /* HPM_LCDC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lvb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lvb_regs.h deleted file mode 100644 index 5b6f9870a3a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_lvb_regs.h +++ /dev/null @@ -1,442 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LVB_H -#define HPM_LVB_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: control register */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - __R uint32_t PHY_STAT; /* 0x10: LVDS TX PHY Status register */ - __RW uint32_t PHY_POW_CTRL[2]; /* 0x14 - 0x18: LVDS0 PHY power control register */ - struct { - __RW uint32_t CTL0; /* 0x1C: TX PHY Setting */ - __RW uint32_t CTL1; /* 0x20: TX_PHY Setting */ - } TX_PHY[10]; -} LVB_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SPLIT_CH_REVERSE (RW) - * - * Just for split mode, reverse two channel data - */ -#define LVB_CTRL_SPLIT_CH_REVERSE_MASK (0x8000000UL) -#define LVB_CTRL_SPLIT_CH_REVERSE_SHIFT (27U) -#define LVB_CTRL_SPLIT_CH_REVERSE_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) -#define LVB_CTRL_SPLIT_CH_REVERSE_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_REVERSE_MASK) >> LVB_CTRL_SPLIT_CH_REVERSE_SHIFT) - -/* - * SPLIT_CH_MODE (RW) - * - * Just for split mode - * 1: two channel pixel data are not aligned - * 0: two channel pixel data are aligned - */ -#define LVB_CTRL_SPLIT_CH_MODE_MASK (0x4000000UL) -#define LVB_CTRL_SPLIT_CH_MODE_SHIFT (26U) -#define LVB_CTRL_SPLIT_CH_MODE_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_CH_MODE_SHIFT) & LVB_CTRL_SPLIT_CH_MODE_MASK) -#define LVB_CTRL_SPLIT_CH_MODE_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_CH_MODE_MASK) >> LVB_CTRL_SPLIT_CH_MODE_SHIFT) - -/* - * SPLIT_HSWHBP_WIDTH (RW) - * - * Just for split mode, the sum of HSW and HBP width is even - * 1: yes - * 0: no - */ -#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK (0x2000000UL) -#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT (25U) -#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) -#define LVB_CTRL_SPLIT_HSWHBP_WIDTH_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_HSWHBP_WIDTH_MASK) >> LVB_CTRL_SPLIT_HSWHBP_WIDTH_SHIFT) - -/* - * SPLIT_MODE_EN (RW) - * - * Split mode enable: - * 1: enable - * 0: disable - * Note: when using split mode, ch0/1 should be enabled, and should select same DI - */ -#define LVB_CTRL_SPLIT_MODE_EN_MASK (0x1000000UL) -#define LVB_CTRL_SPLIT_MODE_EN_SHIFT (24U) -#define LVB_CTRL_SPLIT_MODE_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_SPLIT_MODE_EN_SHIFT) & LVB_CTRL_SPLIT_MODE_EN_MASK) -#define LVB_CTRL_SPLIT_MODE_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_SPLIT_MODE_EN_MASK) >> LVB_CTRL_SPLIT_MODE_EN_SHIFT) - -/* - * DI1_VSYNC_POLARITY (RW) - * - * DI 1 vsync polarity: - * 1: active low - * 0: active high - */ -#define LVB_CTRL_DI1_VSYNC_POLARITY_MASK (0x20000UL) -#define LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT (17U) -#define LVB_CTRL_DI1_VSYNC_POLARITY_SET(x) (((uint32_t)(x) << LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) -#define LVB_CTRL_DI1_VSYNC_POLARITY_GET(x) (((uint32_t)(x) & LVB_CTRL_DI1_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI1_VSYNC_POLARITY_SHIFT) - -/* - * DI0_VSYNC_POLARITY (RW) - * - * DI 0 vsync polarity: - * 1: active low - * 0: active high - */ -#define LVB_CTRL_DI0_VSYNC_POLARITY_MASK (0x10000UL) -#define LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT (16U) -#define LVB_CTRL_DI0_VSYNC_POLARITY_SET(x) (((uint32_t)(x) << LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) -#define LVB_CTRL_DI0_VSYNC_POLARITY_GET(x) (((uint32_t)(x) & LVB_CTRL_DI0_VSYNC_POLARITY_MASK) >> LVB_CTRL_DI0_VSYNC_POLARITY_SHIFT) - -/* - * LVDS_TXCLK_SHIFT (RW) - * - * Shift the LVDS TX PHY clock in relation to the data. - * 000: txck is 7'b1100011 - * 001: txck is 7‘b1110001 - * 010: txck is 7‘b1111000 - * 011: txck is 7‘b1000111 - * 100: txck is 7‘b0001111 - * 101: txck is 7‘b0011110 - * 110: txck is 7‘b0111100 - * 111: txck is 7‘b1100011 - */ -#define LVB_CTRL_LVDS_TXCLK_SHIFT_MASK (0x700U) -#define LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT (8U) -#define LVB_CTRL_LVDS_TXCLK_SHIFT_SET(x) (((uint32_t)(x) << LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) -#define LVB_CTRL_LVDS_TXCLK_SHIFT_GET(x) (((uint32_t)(x) & LVB_CTRL_LVDS_TXCLK_SHIFT_MASK) >> LVB_CTRL_LVDS_TXCLK_SHIFT_SHIFT) - -/* - * CH1_BIT_MAPPING (RW) - * - * Channel 1 data protocol: - * 1: JEIDA standard - * 0: SPWG standard - */ -#define LVB_CTRL_CH1_BIT_MAPPING_MASK (0x80U) -#define LVB_CTRL_CH1_BIT_MAPPING_SHIFT (7U) -#define LVB_CTRL_CH1_BIT_MAPPING_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_BIT_MAPPING_SHIFT) & LVB_CTRL_CH1_BIT_MAPPING_MASK) -#define LVB_CTRL_CH1_BIT_MAPPING_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_BIT_MAPPING_MASK) >> LVB_CTRL_CH1_BIT_MAPPING_SHIFT) - -/* - * CH0_BIT_MAPPING (RW) - * - * Channel 0 data protocol: - * 1: JEIDA standard - * 0: SPWG standard - */ -#define LVB_CTRL_CH0_BIT_MAPPING_MASK (0x20U) -#define LVB_CTRL_CH0_BIT_MAPPING_SHIFT (5U) -#define LVB_CTRL_CH0_BIT_MAPPING_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_BIT_MAPPING_SHIFT) & LVB_CTRL_CH0_BIT_MAPPING_MASK) -#define LVB_CTRL_CH0_BIT_MAPPING_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_BIT_MAPPING_MASK) >> LVB_CTRL_CH0_BIT_MAPPING_SHIFT) - -/* - * CH1_SEL (RW) - * - * Channel 1 select: - * 1: select DI 1 - * 0: select DI 0 - */ -#define LVB_CTRL_CH1_SEL_MASK (0x8U) -#define LVB_CTRL_CH1_SEL_SHIFT (3U) -#define LVB_CTRL_CH1_SEL_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_SEL_SHIFT) & LVB_CTRL_CH1_SEL_MASK) -#define LVB_CTRL_CH1_SEL_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_SEL_MASK) >> LVB_CTRL_CH1_SEL_SHIFT) - -/* - * CH1_EN (RW) - * - * Channel 1 enable: - * 1: enable - * 0: disable - */ -#define LVB_CTRL_CH1_EN_MASK (0x4U) -#define LVB_CTRL_CH1_EN_SHIFT (2U) -#define LVB_CTRL_CH1_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_CH1_EN_SHIFT) & LVB_CTRL_CH1_EN_MASK) -#define LVB_CTRL_CH1_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_CH1_EN_MASK) >> LVB_CTRL_CH1_EN_SHIFT) - -/* - * CH0_SEL (RW) - * - * Channel 0 select: - * 1: select DI 1 - * 0: select DI 0 - */ -#define LVB_CTRL_CH0_SEL_MASK (0x2U) -#define LVB_CTRL_CH0_SEL_SHIFT (1U) -#define LVB_CTRL_CH0_SEL_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_SEL_SHIFT) & LVB_CTRL_CH0_SEL_MASK) -#define LVB_CTRL_CH0_SEL_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_SEL_MASK) >> LVB_CTRL_CH0_SEL_SHIFT) - -/* - * CH0_EN (RW) - * - * Channel 0 enable: - * 1: enable - * 0: disable - */ -#define LVB_CTRL_CH0_EN_MASK (0x1U) -#define LVB_CTRL_CH0_EN_SHIFT (0U) -#define LVB_CTRL_CH0_EN_SET(x) (((uint32_t)(x) << LVB_CTRL_CH0_EN_SHIFT) & LVB_CTRL_CH0_EN_MASK) -#define LVB_CTRL_CH0_EN_GET(x) (((uint32_t)(x) & LVB_CTRL_CH0_EN_MASK) >> LVB_CTRL_CH0_EN_SHIFT) - -/* Bitfield definition for register: PHY_STAT */ -/* - * LVDS1_TX_PHY_PLL_LOCK (RO) - * - * LVDS1 TX PHY PLL Lock indication Signal, 1 means pll already locked - */ -#define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK (0x2U) -#define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT (1U) -#define LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_GET(x) (((uint32_t)(x) & LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS1_TX_PHY_PLL_LOCK_SHIFT) - -/* - * LVDS0_TX_PHY_PLL_LOCK (RO) - * - * LVDS0 TX PHY PLL Lock indication Signal, 1 means pll already locked - */ -#define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK (0x1U) -#define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT (0U) -#define LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_GET(x) (((uint32_t)(x) & LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_MASK) >> LVB_PHY_STAT_LVDS0_TX_PHY_PLL_LOCK_SHIFT) - -/* Bitfield definition for register array: PHY_POW_CTRL */ -/* - * PWON_PLL (RW) - * - * pll power on - */ -#define LVB_PHY_POW_CTRL_PWON_PLL_MASK (0x20U) -#define LVB_PHY_POW_CTRL_PWON_PLL_SHIFT (5U) -#define LVB_PHY_POW_CTRL_PWON_PLL_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) -#define LVB_PHY_POW_CTRL_PWON_PLL_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_PWON_PLL_MASK) >> LVB_PHY_POW_CTRL_PWON_PLL_SHIFT) - -/* - * TXCK_PD (RW) - * - * Power down control signal of channel txck - * 0: Normal operation - * 1: Power down channel - */ -#define LVB_PHY_POW_CTRL_TXCK_PD_MASK (0x10U) -#define LVB_PHY_POW_CTRL_TXCK_PD_SHIFT (4U) -#define LVB_PHY_POW_CTRL_TXCK_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) -#define LVB_PHY_POW_CTRL_TXCK_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TXCK_PD_MASK) >> LVB_PHY_POW_CTRL_TXCK_PD_SHIFT) - -/* - * TX3_PD (RW) - * - * Power down control signal of channel tx3 - * 0: Normal operation - * 1: Power down channel - */ -#define LVB_PHY_POW_CTRL_TX3_PD_MASK (0x8U) -#define LVB_PHY_POW_CTRL_TX3_PD_SHIFT (3U) -#define LVB_PHY_POW_CTRL_TX3_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX3_PD_SHIFT) & LVB_PHY_POW_CTRL_TX3_PD_MASK) -#define LVB_PHY_POW_CTRL_TX3_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX3_PD_MASK) >> LVB_PHY_POW_CTRL_TX3_PD_SHIFT) - -/* - * TX2_PD (RW) - * - * Power down control signal of channel tx2 - * 0: Normal operation - * 1: Power down channel - */ -#define LVB_PHY_POW_CTRL_TX2_PD_MASK (0x4U) -#define LVB_PHY_POW_CTRL_TX2_PD_SHIFT (2U) -#define LVB_PHY_POW_CTRL_TX2_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX2_PD_SHIFT) & LVB_PHY_POW_CTRL_TX2_PD_MASK) -#define LVB_PHY_POW_CTRL_TX2_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX2_PD_MASK) >> LVB_PHY_POW_CTRL_TX2_PD_SHIFT) - -/* - * TX1_PD (RW) - * - * Power down control signal of channel tx1 - * 0: Normal operation - * 1: Power down channel - */ -#define LVB_PHY_POW_CTRL_TX1_PD_MASK (0x2U) -#define LVB_PHY_POW_CTRL_TX1_PD_SHIFT (1U) -#define LVB_PHY_POW_CTRL_TX1_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX1_PD_SHIFT) & LVB_PHY_POW_CTRL_TX1_PD_MASK) -#define LVB_PHY_POW_CTRL_TX1_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX1_PD_MASK) >> LVB_PHY_POW_CTRL_TX1_PD_SHIFT) - -/* - * TX0_PD (RW) - * - * Power down control signal of channel tx0 - * 0: Normal operation - * 1: Power down channel - */ -#define LVB_PHY_POW_CTRL_TX0_PD_MASK (0x1U) -#define LVB_PHY_POW_CTRL_TX0_PD_SHIFT (0U) -#define LVB_PHY_POW_CTRL_TX0_PD_SET(x) (((uint32_t)(x) << LVB_PHY_POW_CTRL_TX0_PD_SHIFT) & LVB_PHY_POW_CTRL_TX0_PD_MASK) -#define LVB_PHY_POW_CTRL_TX0_PD_GET(x) (((uint32_t)(x) & LVB_PHY_POW_CTRL_TX0_PD_MASK) >> LVB_PHY_POW_CTRL_TX0_PD_SHIFT) - -/* Bitfield definition for register of struct array TX_PHY: CTL0 */ -/* - * TX_IDLE (RW) - * - * Force the high-speed differential signal to common mode. - * This signal can be set during IP power up stage to prevent unexpected leakage current in TXP/TXN - * 0: Normal operation - * 1: Force TXPN /TXMN to common mode - */ -#define LVB_TX_PHY_CTL0_TX_IDLE_MASK (0x100000UL) -#define LVB_TX_PHY_CTL0_TX_IDLE_SHIFT (20U) -#define LVB_TX_PHY_CTL0_TX_IDLE_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) -#define LVB_TX_PHY_CTL0_TX_IDLE_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_IDLE_MASK) >> LVB_TX_PHY_CTL0_TX_IDLE_SHIFT) - -/* - * TX_RTERM_EN (RW) - * - * Inner Terminal Resistance enable - * 0: Disable rterm 2000ohm - * 1: Enable rterm 100ohm - */ -#define LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK (0x80000UL) -#define LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT (19U) -#define LVB_TX_PHY_CTL0_TX_RTERM_EN_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) -#define LVB_TX_PHY_CTL0_TX_RTERM_EN_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_RTERM_EN_MASK) >> LVB_TX_PHY_CTL0_TX_RTERM_EN_SHIFT) - -/* - * TX_BUS_WIDTH (RW) - * - * Parallel data bus width select： - * 000: 4-bit mode, txN_data[3:0] are valid, txN_data[11:4] can be arbitrary state. - * 001: 6-bit mode, txN_data[5:0] are valid, txN_data[11:6] can be arbitrary state. - * 010: 7-bit mode. txN_data[6:0] are valid, txN_data[11:7] can be arbitrary state. - * 011: 8-bit mode. txN_data[7:0] are valid, txN_data[11:8] can be arbitrary state. - * 100: 9-bit mode. txN_data[8:0] are valid, txN_data[11:9] can be arbitrary state. - * 101: 10-bit mode. txN_data[9:0] are valid, txN_data[11:10] can be arbitrary state. - * 110: 11-bit mode. txN_data[10:0] are valid, txN_data[11] can be arbitrary state. - * 111: 12-bit mode. txN_data[11:0] are valid - */ -#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK (0x70000UL) -#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT (16U) -#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) -#define LVB_TX_PHY_CTL0_TX_BUS_WIDTH_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_BUS_WIDTH_MASK) >> LVB_TX_PHY_CTL0_TX_BUS_WIDTH_SHIFT) - -/* - * TX_PHASE_SEL (RW) - * - * data/clock lane output phase adjustment: - * 0000: 0 - * 0001: data lane is 1/32, clock lane is 1/16 - * 0010: data lane is 2/32, clock lane is 2/16 - * 0011: data lane is 3/32, clock lane is 3/16 - * 0100: data lane is 4/32, clock lane is 4/16 - * 0101: data lane is 5/32, clock lane is 5/16 - * 0110: data lane is 6/32, clock lane is 6/16 - * 0111: data lane is 7/32, clock lane is 7/16 - * 1000: data lane is 8/32, clock lane is 8/16 - * 1001: data lane is 9/32, clock lane is 9/16 - * 1010: data lane is 10/32, clock lane is 10/16 - * 1011: data lane is 11/32, clock lane is 11/16 - * 1100: data lane is 12/32, clock lane is 12/16 - * 1101: data lane is 13/32, clock lane is 13/16 - * 1110: data lane is 14/32, clock lane is 14/16 - * 1111: data lane is 15/32, clock lane is 15/16 - */ -#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK (0xF000U) -#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT (12U) -#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) -#define LVB_TX_PHY_CTL0_TX_PHASE_SEL_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_PHASE_SEL_MASK) >> LVB_TX_PHY_CTL0_TX_PHASE_SEL_SHIFT) - -/* - * TX_VCOM (RW) - * - * output Common Mode Voltage adjustment(Unit: V). - * 0000: 0.7 - * 0001: 0.8 - * 0010: 0.9 - * 0011: 1.0 - * 0100: 1.1 - * 0101: 1.2 - * 0110: 1.3 - * 0111: 1.4 - * 1000~1111: 1.5 - */ -#define LVB_TX_PHY_CTL0_TX_VCOM_MASK (0xF00U) -#define LVB_TX_PHY_CTL0_TX_VCOM_SHIFT (8U) -#define LVB_TX_PHY_CTL0_TX_VCOM_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) -#define LVB_TX_PHY_CTL0_TX_VCOM_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_VCOM_MASK) >> LVB_TX_PHY_CTL0_TX_VCOM_SHIFT) - -/* - * TX_AMP (RW) - * - * Output voltage Adjustment(Unit: mV). - * 0000 : 50 - * 0001: 100 - * 0010: 150 - * 0011: 200 - * 0100: 250 - * 0101: 300 - * 0110: 350 - * 0111: 400 - * 1000: 450 - * 1001: 500 - * 1010: 550 - * 1011~1111: 600 - */ -#define LVB_TX_PHY_CTL0_TX_AMP_MASK (0xF0U) -#define LVB_TX_PHY_CTL0_TX_AMP_SHIFT (4U) -#define LVB_TX_PHY_CTL0_TX_AMP_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_AMP_SHIFT) & LVB_TX_PHY_CTL0_TX_AMP_MASK) -#define LVB_TX_PHY_CTL0_TX_AMP_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_AMP_MASK) >> LVB_TX_PHY_CTL0_TX_AMP_SHIFT) - -/* - * TX_SR (RW) - * - * output slew-rate trimming - * 00: slowest slew-rate; - * 11: fastest slew-rate - */ -#define LVB_TX_PHY_CTL0_TX_SR_MASK (0xCU) -#define LVB_TX_PHY_CTL0_TX_SR_SHIFT (2U) -#define LVB_TX_PHY_CTL0_TX_SR_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_SR_SHIFT) & LVB_TX_PHY_CTL0_TX_SR_MASK) -#define LVB_TX_PHY_CTL0_TX_SR_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_SR_MASK) >> LVB_TX_PHY_CTL0_TX_SR_SHIFT) - -/* - * TX_DEEMP (RW) - * - * output de-emphasis level trimming(Unit: dB) - * 00: 0 - * 01: 2.5 - * 10: 6.0 - * 11: 6.0 - */ -#define LVB_TX_PHY_CTL0_TX_DEEMP_MASK (0x3U) -#define LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT (0U) -#define LVB_TX_PHY_CTL0_TX_DEEMP_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) -#define LVB_TX_PHY_CTL0_TX_DEEMP_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL0_TX_DEEMP_MASK) >> LVB_TX_PHY_CTL0_TX_DEEMP_SHIFT) - -/* Bitfield definition for register of struct array TX_PHY: CTL1 */ -/* - * TX_CTL (RW) - * - */ -#define LVB_TX_PHY_CTL1_TX_CTL_MASK (0xFFFFFUL) -#define LVB_TX_PHY_CTL1_TX_CTL_SHIFT (0U) -#define LVB_TX_PHY_CTL1_TX_CTL_SET(x) (((uint32_t)(x) << LVB_TX_PHY_CTL1_TX_CTL_SHIFT) & LVB_TX_PHY_CTL1_TX_CTL_MASK) -#define LVB_TX_PHY_CTL1_TX_CTL_GET(x) (((uint32_t)(x) & LVB_TX_PHY_CTL1_TX_CTL_MASK) >> LVB_TX_PHY_CTL1_TX_CTL_SHIFT) - - - -/* PHY_POW_CTRL register group index macro definition */ -#define LVB_PHY_POW_CTRL_LVDS0 (0UL) -#define LVB_PHY_POW_CTRL_LVDS1 (1UL) - -/* TX_PHY register group index macro definition */ -#define LVB_TX_PHY_LVDS0_TX0 (0UL) -#define LVB_TX_PHY_LVDS0_TX1 (1UL) -#define LVB_TX_PHY_LVDS0_TX2 (1UL) -#define LVB_TX_PHY_LVDS0_TX3 (3UL) -#define LVB_TX_PHY_LVDS0_TXCK (4UL) -#define LVB_TX_PHY_LVDS1_TX0 (5UL) -#define LVB_TX_PHY_LVDS1_TX1 (6UL) -#define LVB_TX_PHY_LVDS1_TX2 (7UL) -#define LVB_TX_PHY_LVDS1_TX3 (8UL) -#define LVB_TX_PHY_LVDS1_TXCK (9UL) - - -#endif /* HPM_LVB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mbx_regs.h deleted file mode 100644 index d159b97303a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mbx_regs.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_H -#define HPM_MBX_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Command Registers */ - __RW uint32_t SR; /* 0x4: Status Registers */ - __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ - __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ - __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ -} MBX_Type; - - -/* Bitfield definition for register: CR */ -/* - * TXRESET (RW) - * - * Reset TX Fifo and word. - */ -#define MBX_CR_TXRESET_MASK (0x80000000UL) -#define MBX_CR_TXRESET_SHIFT (31U) -#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) -#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) - -/* - * BARCTL (RW) - * - * Bus Access Response Control, when bit 15:14= - * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. - * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. - * 11: reserved. - */ -#define MBX_CR_BARCTL_MASK (0xC000U) -#define MBX_CR_BARCTL_SHIFT (14U) -#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) -#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. - * 1, enable the bus access error interrupt. - * 0, disable the bus access error interrupt. - */ -#define MBX_CR_BEIE_MASK (0x100U) -#define MBX_CR_BEIE_SHIFT (8U) -#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) -#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) - -/* - * TFMAIE (RW) - * - * TX FIFO message available interrupt enable. - * 1, enable the TX FIFO massage available interrupt. - * 0, disable the TX FIFO message available interrupt. - */ -#define MBX_CR_TFMAIE_MASK (0x80U) -#define MBX_CR_TFMAIE_SHIFT (7U) -#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) -#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) - -/* - * TFMEIE (RW) - * - * TX FIFO message empty interrupt enable. - * 1, enable the TX FIFO massage empty interrupt. - * 0, disable the TX FIFO message empty interrupt. - */ -#define MBX_CR_TFMEIE_MASK (0x40U) -#define MBX_CR_TFMEIE_SHIFT (6U) -#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) -#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) - -/* - * RFMAIE (RW) - * - * RX FIFO message available interrupt enable. - * 1, enable the RX FIFO massage available interrupt. - * 0, disable the RX FIFO message available interrupt. - */ -#define MBX_CR_RFMAIE_MASK (0x20U) -#define MBX_CR_RFMAIE_SHIFT (5U) -#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) -#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) - -/* - * RFMFIE (RW) - * - * RX fifo message full interrupt enable. - * 1, enable the RX fifo message full interrupt. - * 0, disable the RX fifo message full interrupt. - */ -#define MBX_CR_RFMFIE_MASK (0x10U) -#define MBX_CR_RFMFIE_SHIFT (4U) -#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) -#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) - -/* - * TWMEIE (RW) - * - * TX word message empty interrupt enable. - * 1, enable the TX word massage empty interrupt. - * 0, disable the TX word message empty interrupt. - */ -#define MBX_CR_TWMEIE_MASK (0x2U) -#define MBX_CR_TWMEIE_SHIFT (1U) -#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) -#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) - -/* - * RWMVIE (RW) - * - * RX word message valid interrupt enable. - * 1, enable the RX word massage valid interrupt. - * 0, disable the RX word message valid interrupt. - */ -#define MBX_CR_RWMVIE_MASK (0x1U) -#define MBX_CR_RWMVIE_SHIFT (0U) -#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) -#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * RFVC (RO) - * - * RX FIFO valid message count - */ -#define MBX_SR_RFVC_MASK (0xF00000UL) -#define MBX_SR_RFVC_SHIFT (20U) -#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) - -/* - * TFEC (RO) - * - * TX FIFO empty message word count - */ -#define MBX_SR_TFEC_MASK (0xF0000UL) -#define MBX_SR_TFEC_SHIFT (16U) -#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) - -/* - * ERRRE (W1C) - * - * bus Error for read when rx word message are still invalid, this bit is W1C bit. - * 1, read from word message when the word message are still invalid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRRE_MASK (0x2000U) -#define MBX_SR_ERRRE_SHIFT (13U) -#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) -#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) - -/* - * EWTRF (W1C) - * - * bus Error for write when tx word message are still valid, this bit is W1C bit. - * 1, write to word message when the word message are still valid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTRF_MASK (0x1000U) -#define MBX_SR_EWTRF_SHIFT (12U) -#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) -#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) - -/* - * ERRFE (W1C) - * - * bus Error for read when rx fifo empty, this bit is W1C bit. - * 1, read from a empty rx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRFE_MASK (0x800U) -#define MBX_SR_ERRFE_SHIFT (11U) -#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) -#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) - -/* - * EWTFF (W1C) - * - * bus Error for write when tx fifo full, this bit is W1C bit. - * 1, write to a fulled tx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTFF_MASK (0x400U) -#define MBX_SR_EWTFF_SHIFT (10U) -#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) -#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) - -/* - * EAIVA (W1C) - * - * bus Error for Accessing Invalid Address; this bit is W1C bit. - * 1, read and write to invalid address in the bus of this block, will set this bit. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EAIVA_MASK (0x200U) -#define MBX_SR_EAIVA_SHIFT (9U) -#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) -#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) - -/* - * EW2RO (W1C) - * - * bus Error for Write to Read Only address; this bit is W1C bit. - * 1, write to read only address happened in the bus of this block. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EW2RO_MASK (0x100U) -#define MBX_SR_EW2RO_SHIFT (8U) -#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) -#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) - -/* - * TFMA (RW) - * - * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. - * 1, TXFIFO message buffer has slot available - * 0, no slot available (fifo full) - */ -#define MBX_SR_TFMA_MASK (0x80U) -#define MBX_SR_TFMA_SHIFT (7U) -#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) -#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) - -/* - * TFME (RW) - * - * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. - * 1, no any message data in TXFIFO from other core. - * 0, there are some data in the 4x32 TX FIFO from other core yet. - */ -#define MBX_SR_TFME_MASK (0x40U) -#define MBX_SR_TFME_SHIFT (6U) -#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) -#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) - -/* - * RFMA (RO) - * - * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, no any data in the 4x32 TXFIFO message buffer. - * 0, there are some data in the the 4x32 TXFIFO message buffer already. - */ -#define MBX_SR_RFMA_MASK (0x20U) -#define MBX_SR_RFMA_SHIFT (5U) -#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) - -/* - * RFMF (RO) - * - * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written 4x32 message in the RXFIFO. - * 0, no 4x32 RX FIFO message from other core yet. - */ -#define MBX_SR_RFMF_MASK (0x10U) -#define MBX_SR_RFMF_SHIFT (4U) -#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) - -/* - * TWME (RO) - * - * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, means this core had write word message to TXREG. - * 0, means no valid word message in the TXREG yet. - */ -#define MBX_SR_TWME_MASK (0x2U) -#define MBX_SR_TWME_SHIFT (1U) -#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) - -/* - * RWMV (RO) - * - * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written word message in the RXREG. - * 0, no valid word message yet in the RXREG. - */ -#define MBX_SR_RWMV_MASK (0x1U) -#define MBX_SR_RWMV_SHIFT (0U) -#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) - -/* Bitfield definition for register: TXREG */ -/* - * TXREG (WO) - * - * Transmit word message to other core. - */ -#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) -#define MBX_TXREG_TXREG_SHIFT (0U) -#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) -#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) - -/* Bitfield definition for register: RXREG */ -/* - * RXREG (RO) - * - * Receive word message from other core. - */ -#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) -#define MBX_RXREG_RXREG_SHIFT (0U) -#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) - -/* Bitfield definition for register array: TXWRD */ -/* - * TXFIFO (WO) - * - * TXFIFO for sending message to other core, FIFO size, 4x32 - * can write one of the word address to push data to the FIFO; - * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - */ -#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_TXWRD_TXFIFO_SHIFT (0U) -#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) -#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) - -/* Bitfield definition for register array: RXWRD */ -/* - * RXFIFO (RO) - * - * RXFIFO for receiving message from other core, FIFO size, 4x32 - * can read one of the word address to pop data to the FIFO; - * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - */ -#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_RXWRD_RXFIFO_SHIFT (0U) -#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) - - - -/* TXWRD register group index macro definition */ -#define MBX_TXWRD_TXFIFO0 (0UL) - -/* RXWRD register group index macro definition */ -#define MBX_RXWRD_RXFIFO0 (0UL) - - -#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mcan_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mcan_regs.h deleted file mode 100644 index ad873392ba7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mcan_regs.h +++ /dev/null @@ -1,3605 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCAN_H -#define HPM_MCAN_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t ENDN; /* 0x4: endian register */ - __R uint8_t RESERVED1[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t DBTP; /* 0xC: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set */ - __RW uint32_t TEST; /* 0x10: test register */ - __RW uint32_t RWD; /* 0x14: ram watchdog */ - __RW uint32_t CCCR; /* 0x18: CC control register */ - __RW uint32_t NBTP; /* 0x1C: nominal bit timing and prescaler register */ - __RW uint32_t TSCC; /* 0x20: timestamp counter configuration */ - __R uint32_t TSCV; /* 0x24: timestamp counter value */ - __RW uint32_t TOCC; /* 0x28: timeout counter configuration */ - __R uint32_t TOCV; /* 0x2C: timeout counter value */ - __R uint8_t RESERVED2[16]; /* 0x30 - 0x3F: Reserved */ - __R uint32_t ECR; /* 0x40: error counter register */ - __R uint32_t PSR; /* 0x44: protocol status register */ - __RW uint32_t TDCR; /* 0x48: transmitter delay compensation */ - __R uint8_t RESERVED3[4]; /* 0x4C - 0x4F: Reserved */ - __RW uint32_t IR; /* 0x50: interrupt register */ - __RW uint32_t IE; /* 0x54: interrupt enable */ - __RW uint32_t ILS; /* 0x58: interrupt line select */ - __RW uint32_t ILE; /* 0x5C: interrupt line enable */ - __R uint8_t RESERVED4[32]; /* 0x60 - 0x7F: Reserved */ - __RW uint32_t GFC; /* 0x80: global filter configuration */ - __RW uint32_t SIDFC; /* 0x84: standard ID filter configuration */ - __RW uint32_t XIDFC; /* 0x88: extended ID filter configuration */ - __R uint8_t RESERVED5[4]; /* 0x8C - 0x8F: Reserved */ - __RW uint32_t XIDAM; /* 0x90: extended id and mask */ - __R uint32_t HPMS; /* 0x94: high priority message status */ - __RW uint32_t NDAT1; /* 0x98: new data1 */ - __RW uint32_t NDAT2; /* 0x9C: new data2 */ - __RW uint32_t RXF0C; /* 0xA0: rx fifo 0 configuration */ - __R uint32_t RXF0S; /* 0xA4: rx fifo 0 status */ - __RW uint32_t RXF0A; /* 0xA8: rx fifo0 acknowledge */ - __RW uint32_t RXBC; /* 0xAC: rx buffer configuration */ - __RW uint32_t RXF1C; /* 0xB0: rx fifo1 configuration */ - __R uint32_t RXF1S; /* 0xB4: rx fifo1 status */ - __RW uint32_t RXF1A; /* 0xB8: rx fifo 1 acknowledge */ - __RW uint32_t RXESC; /* 0xBC: rx buffer/fifo element size configuration */ - __RW uint32_t TXBC; /* 0xC0: tx buffer configuration */ - __R uint32_t TXFQS; /* 0xC4: tx fifo/queue status */ - __RW uint32_t TXESC; /* 0xC8: tx buffer element size configuration */ - __R uint32_t TXBRP; /* 0xCC: tx buffer request pending */ - __RW uint32_t TXBAR; /* 0xD0: tx buffer add request */ - __RW uint32_t TXBCR; /* 0xD4: tx buffer cancellation request */ - __R uint32_t TXBTO; /* 0xD8: tx buffer transmission occurred */ - __R uint32_t TXBCF; /* 0xDC: tx buffer cancellation finished */ - __RW uint32_t TXBTIE; /* 0xE0: tx buffer transmission interrupt enable */ - __RW uint32_t TXBCIE; /* 0xE4: tx buffer cancellation finished interrupt enable */ - __R uint8_t RESERVED6[8]; /* 0xE8 - 0xEF: Reserved */ - __RW uint32_t TXEFC; /* 0xF0: tx event fifo configuration */ - __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ - __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ - __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ - __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0 */ - __R uint32_t CREL; /* 0x240: core release register */ - __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ - __R uint32_t TSS1; /* 0x248: timestamp status1 */ - __R uint32_t TSS2; /* 0x24C: timestamp status2 */ - __R uint32_t ATB; /* 0x250: actual timebase */ - __R uint32_t ATBH; /* 0x254: actual timebase high */ - __R uint8_t RESERVED8[424]; /* 0x258 - 0x3FF: Reserved */ - __RW uint32_t GLB_CTL; /* 0x400: global control */ - __R uint32_t GLB_STATUS; /* 0x404: global status */ - __R uint8_t RESERVED9[7160]; /* 0x408 - 0x1FFF: Reserved */ - __RW uint32_t MESSAGE_BUFF[640]; /* 0x2000 - 0x29FC: message buff */ -} MCAN_Type; - - -/* Bitfield definition for register: ENDN */ -/* - * EVT (R) - * - * Endianness Test Value - * The endianness test value is 0x87654321. - */ -#define MCAN_ENDN_EVT_MASK (0xFFFFFFFFUL) -#define MCAN_ENDN_EVT_SHIFT (0U) -#define MCAN_ENDN_EVT_GET(x) (((uint32_t)(x) & MCAN_ENDN_EVT_MASK) >> MCAN_ENDN_EVT_SHIFT) - -/* Bitfield definition for register: DBTP */ -/* - * TDC (RW) - * - * transmitter delay compensation enable - * 0= Transmitter Delay Compensation disabled - * 1= Transmitter Delay Compensation enabled - */ -#define MCAN_DBTP_TDC_MASK (0x800000UL) -#define MCAN_DBTP_TDC_SHIFT (23U) -#define MCAN_DBTP_TDC_SET(x) (((uint32_t)(x) << MCAN_DBTP_TDC_SHIFT) & MCAN_DBTP_TDC_MASK) -#define MCAN_DBTP_TDC_GET(x) (((uint32_t)(x) & MCAN_DBTP_TDC_MASK) >> MCAN_DBTP_TDC_SHIFT) - -/* - * DBRP (RW) - * - * Data Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. - * When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DBRP_MASK (0x1F0000UL) -#define MCAN_DBTP_DBRP_SHIFT (16U) -#define MCAN_DBTP_DBRP_SET(x) (((uint32_t)(x) << MCAN_DBTP_DBRP_SHIFT) & MCAN_DBTP_DBRP_MASK) -#define MCAN_DBTP_DBRP_GET(x) (((uint32_t)(x) & MCAN_DBTP_DBRP_MASK) >> MCAN_DBTP_DBRP_SHIFT) - -/* - * DTSEG1 (RW) - * - * Data time segment before sample point - * Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG1_MASK (0x1F00U) -#define MCAN_DBTP_DTSEG1_SHIFT (8U) -#define MCAN_DBTP_DTSEG1_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG1_SHIFT) & MCAN_DBTP_DTSEG1_MASK) -#define MCAN_DBTP_DTSEG1_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG1_MASK) >> MCAN_DBTP_DTSEG1_SHIFT) - -/* - * DTSEG2 (RW) - * - * Data time segment after sample point - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG2_MASK (0xF0U) -#define MCAN_DBTP_DTSEG2_SHIFT (4U) -#define MCAN_DBTP_DTSEG2_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG2_SHIFT) & MCAN_DBTP_DTSEG2_MASK) -#define MCAN_DBTP_DTSEG2_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG2_MASK) >> MCAN_DBTP_DTSEG2_SHIFT) - -/* - * DSJW (RW) - * - * Data (Re)Synchronization Jump Width - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DSJW_MASK (0xFU) -#define MCAN_DBTP_DSJW_SHIFT (0U) -#define MCAN_DBTP_DSJW_SET(x) (((uint32_t)(x) << MCAN_DBTP_DSJW_SHIFT) & MCAN_DBTP_DSJW_MASK) -#define MCAN_DBTP_DSJW_GET(x) (((uint32_t)(x) & MCAN_DBTP_DSJW_MASK) >> MCAN_DBTP_DSJW_SHIFT) - -/* Bitfield definition for register: TEST */ -/* - * SVAL (R) - * - * Started Valid - * 0= Value of TXBNS not valid - * 1= Value of TXBNS valid - */ -#define MCAN_TEST_SVAL_MASK (0x200000UL) -#define MCAN_TEST_SVAL_SHIFT (21U) -#define MCAN_TEST_SVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_SVAL_MASK) >> MCAN_TEST_SVAL_SHIFT) - -/* - * TXBNS (R) - * - * Tx Buffer Number Started - * Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNS_MASK (0x1F0000UL) -#define MCAN_TEST_TXBNS_SHIFT (16U) -#define MCAN_TEST_TXBNS_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNS_MASK) >> MCAN_TEST_TXBNS_SHIFT) - -/* - * PVAL (R) - * - * Prepared Valid - * 0= Value of TXBNP not valid - * 1= Value of TXBNP valid - */ -#define MCAN_TEST_PVAL_MASK (0x2000U) -#define MCAN_TEST_PVAL_SHIFT (13U) -#define MCAN_TEST_PVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_PVAL_MASK) >> MCAN_TEST_PVAL_SHIFT) - -/* - * TXBNP (R) - * - * Tx Buffer Number Prepared - * Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNP_MASK (0x1F00U) -#define MCAN_TEST_TXBNP_SHIFT (8U) -#define MCAN_TEST_TXBNP_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNP_MASK) >> MCAN_TEST_TXBNP_SHIFT) - -/* - * RX (R) - * - * Receive Pin - * Monitors the actual value of pin m_can_rx - * 0= The CAN bus is dominant (m_can_rx = ‘0’) - * 1= The CAN bus is recessive (m_can_rx = ‘1’) - */ -#define MCAN_TEST_RX_MASK (0x80U) -#define MCAN_TEST_RX_SHIFT (7U) -#define MCAN_TEST_RX_GET(x) (((uint32_t)(x) & MCAN_TEST_RX_MASK) >> MCAN_TEST_RX_SHIFT) - -/* - * TX (RW) - * - * Control of Transmit Pin - * 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time - * 01 Sample Point can be monitored at pin m_can_tx - * 10 Dominant (‘0’) level at pin m_can_tx - * 11 Recessive (‘1’) at pin m_can_tx - */ -#define MCAN_TEST_TX_MASK (0x60U) -#define MCAN_TEST_TX_SHIFT (5U) -#define MCAN_TEST_TX_SET(x) (((uint32_t)(x) << MCAN_TEST_TX_SHIFT) & MCAN_TEST_TX_MASK) -#define MCAN_TEST_TX_GET(x) (((uint32_t)(x) & MCAN_TEST_TX_MASK) >> MCAN_TEST_TX_SHIFT) - -/* - * LBCK (RW) - * - * Loop Back Mode - * 0= Reset value, Loop Back Mode is disabled - * 1= Loop Back Mode is enabled - */ -#define MCAN_TEST_LBCK_MASK (0x10U) -#define MCAN_TEST_LBCK_SHIFT (4U) -#define MCAN_TEST_LBCK_SET(x) (((uint32_t)(x) << MCAN_TEST_LBCK_SHIFT) & MCAN_TEST_LBCK_MASK) -#define MCAN_TEST_LBCK_GET(x) (((uint32_t)(x) & MCAN_TEST_LBCK_MASK) >> MCAN_TEST_LBCK_SHIFT) - -/* Bitfield definition for register: RWD */ -/* - * WDV (R) - * - * Watchdog Value - * Actual Message RAM Watchdog Counter Value. - */ -#define MCAN_RWD_WDV_MASK (0xFF00U) -#define MCAN_RWD_WDV_SHIFT (8U) -#define MCAN_RWD_WDV_GET(x) (((uint32_t)(x) & MCAN_RWD_WDV_MASK) >> MCAN_RWD_WDV_SHIFT) - -/* - * WDC (RW) - * - * Watchdog Configuration - * Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - */ -#define MCAN_RWD_WDC_MASK (0xFFU) -#define MCAN_RWD_WDC_SHIFT (0U) -#define MCAN_RWD_WDC_SET(x) (((uint32_t)(x) << MCAN_RWD_WDC_SHIFT) & MCAN_RWD_WDC_MASK) -#define MCAN_RWD_WDC_GET(x) (((uint32_t)(x) & MCAN_RWD_WDC_MASK) >> MCAN_RWD_WDC_SHIFT) - -/* Bitfield definition for register: CCCR */ -/* - * NISO (RW) - * - * Non ISO Operation - * If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD - * Specification V1.0. - * 0= CAN FD frame format according to ISO 11898-1:2015 - * 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 - * Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - */ -#define MCAN_CCCR_NISO_MASK (0x8000U) -#define MCAN_CCCR_NISO_SHIFT (15U) -#define MCAN_CCCR_NISO_SET(x) (((uint32_t)(x) << MCAN_CCCR_NISO_SHIFT) & MCAN_CCCR_NISO_MASK) -#define MCAN_CCCR_NISO_GET(x) (((uint32_t)(x) & MCAN_CCCR_NISO_MASK) >> MCAN_CCCR_NISO_SHIFT) - -/* - * TXP (RW) - * - * Transmit Pause - * If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after - * itself has successfully transmitted a frame (see Section 3.5). - * 0= Transmit pause disabled - * 1= Transmit pause enabled - */ -#define MCAN_CCCR_TXP_MASK (0x4000U) -#define MCAN_CCCR_TXP_SHIFT (14U) -#define MCAN_CCCR_TXP_SET(x) (((uint32_t)(x) << MCAN_CCCR_TXP_SHIFT) & MCAN_CCCR_TXP_MASK) -#define MCAN_CCCR_TXP_GET(x) (((uint32_t)(x) & MCAN_CCCR_TXP_MASK) >> MCAN_CCCR_TXP_SHIFT) - -/* - * EFBI (RW) - * - * Edge Filtering during Bus Integration - * 0= Edge filtering disabled - * 1= Two consecutive dominant tq required to detect an edge for hard synchronization - */ -#define MCAN_CCCR_EFBI_MASK (0x2000U) -#define MCAN_CCCR_EFBI_SHIFT (13U) -#define MCAN_CCCR_EFBI_SET(x) (((uint32_t)(x) << MCAN_CCCR_EFBI_SHIFT) & MCAN_CCCR_EFBI_MASK) -#define MCAN_CCCR_EFBI_GET(x) (((uint32_t)(x) & MCAN_CCCR_EFBI_MASK) >> MCAN_CCCR_EFBI_SHIFT) - -/* - * PXHD (RW) - * - * Protocol Exception Handling Disable - * 0= Protocol exception handling enabled - * 1= Protocol exception handling disabled - * Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - */ -#define MCAN_CCCR_PXHD_MASK (0x1000U) -#define MCAN_CCCR_PXHD_SHIFT (12U) -#define MCAN_CCCR_PXHD_SET(x) (((uint32_t)(x) << MCAN_CCCR_PXHD_SHIFT) & MCAN_CCCR_PXHD_MASK) -#define MCAN_CCCR_PXHD_GET(x) (((uint32_t)(x) & MCAN_CCCR_PXHD_MASK) >> MCAN_CCCR_PXHD_SHIFT) - -/* - * WMM (RW) - * - * Wide Message Marker - * Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. - * 0= 8-bit Message Marker used - * 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - */ -#define MCAN_CCCR_WMM_MASK (0x800U) -#define MCAN_CCCR_WMM_SHIFT (11U) -#define MCAN_CCCR_WMM_SET(x) (((uint32_t)(x) << MCAN_CCCR_WMM_SHIFT) & MCAN_CCCR_WMM_MASK) -#define MCAN_CCCR_WMM_GET(x) (((uint32_t)(x) & MCAN_CCCR_WMM_MASK) >> MCAN_CCCR_WMM_SHIFT) - -/* - * UTSU (RW) - * - * Use Timestamping Unit - * When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. - * 0= Internal time stamping - * 1= External time stamping by TSU - * Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. - * In this case bit UTSU is fixed to zero by synthesis. - */ -#define MCAN_CCCR_UTSU_MASK (0x400U) -#define MCAN_CCCR_UTSU_SHIFT (10U) -#define MCAN_CCCR_UTSU_SET(x) (((uint32_t)(x) << MCAN_CCCR_UTSU_SHIFT) & MCAN_CCCR_UTSU_MASK) -#define MCAN_CCCR_UTSU_GET(x) (((uint32_t)(x) & MCAN_CCCR_UTSU_MASK) >> MCAN_CCCR_UTSU_SHIFT) - -/* - * BRSE (RW) - * - * Bit Rate Switch Enable - * 0= Bit rate switching for transmissions disabled - * 1= Bit rate switching for transmissions enabled - * Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - */ -#define MCAN_CCCR_BRSE_MASK (0x200U) -#define MCAN_CCCR_BRSE_SHIFT (9U) -#define MCAN_CCCR_BRSE_SET(x) (((uint32_t)(x) << MCAN_CCCR_BRSE_SHIFT) & MCAN_CCCR_BRSE_MASK) -#define MCAN_CCCR_BRSE_GET(x) (((uint32_t)(x) & MCAN_CCCR_BRSE_MASK) >> MCAN_CCCR_BRSE_SHIFT) - -/* - * FDOE (RW) - * - * FD Operation Enable - * 0= FD operation disabled - * 1= FD operation enabled - */ -#define MCAN_CCCR_FDOE_MASK (0x100U) -#define MCAN_CCCR_FDOE_SHIFT (8U) -#define MCAN_CCCR_FDOE_SET(x) (((uint32_t)(x) << MCAN_CCCR_FDOE_SHIFT) & MCAN_CCCR_FDOE_MASK) -#define MCAN_CCCR_FDOE_GET(x) (((uint32_t)(x) & MCAN_CCCR_FDOE_MASK) >> MCAN_CCCR_FDOE_SHIFT) - -/* - * TEST (RW) - * - * Test Mode Enable - * 0= Normal operation, register TEST holds reset values - * 1= Test Mode, write access to register TEST enabled - */ -#define MCAN_CCCR_TEST_MASK (0x80U) -#define MCAN_CCCR_TEST_SHIFT (7U) -#define MCAN_CCCR_TEST_SET(x) (((uint32_t)(x) << MCAN_CCCR_TEST_SHIFT) & MCAN_CCCR_TEST_MASK) -#define MCAN_CCCR_TEST_GET(x) (((uint32_t)(x) & MCAN_CCCR_TEST_MASK) >> MCAN_CCCR_TEST_SHIFT) - -/* - * DAR (RW) - * - * Disable Automatic Retransmission - * 0= Automatic retransmission of messages not transmitted successfully enabled - * 1= Automatic retransmission disabled - */ -#define MCAN_CCCR_DAR_MASK (0x40U) -#define MCAN_CCCR_DAR_SHIFT (6U) -#define MCAN_CCCR_DAR_SET(x) (((uint32_t)(x) << MCAN_CCCR_DAR_SHIFT) & MCAN_CCCR_DAR_MASK) -#define MCAN_CCCR_DAR_GET(x) (((uint32_t)(x) & MCAN_CCCR_DAR_MASK) >> MCAN_CCCR_DAR_SHIFT) - -/* - * MON (RW) - * - * Bus Monitoring Mode - * Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. - * 0= Bus Monitoring Mode is disabled - * 1= Bus Monitoring Mode is enabled - */ -#define MCAN_CCCR_MON_MASK (0x20U) -#define MCAN_CCCR_MON_SHIFT (5U) -#define MCAN_CCCR_MON_SET(x) (((uint32_t)(x) << MCAN_CCCR_MON_SHIFT) & MCAN_CCCR_MON_MASK) -#define MCAN_CCCR_MON_GET(x) (((uint32_t)(x) & MCAN_CCCR_MON_MASK) >> MCAN_CCCR_MON_SHIFT) - -/* - * CSR (RW) - * - * Clock Stop Request - * 0= No clock stop is requested - * 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - */ -#define MCAN_CCCR_CSR_MASK (0x10U) -#define MCAN_CCCR_CSR_SHIFT (4U) -#define MCAN_CCCR_CSR_SET(x) (((uint32_t)(x) << MCAN_CCCR_CSR_SHIFT) & MCAN_CCCR_CSR_MASK) -#define MCAN_CCCR_CSR_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSR_MASK) >> MCAN_CCCR_CSR_SHIFT) - -/* - * CSA (R) - * - * Clock Stop Acknowledge - * 0= No clock stop acknowledged - * 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - */ -#define MCAN_CCCR_CSA_MASK (0x8U) -#define MCAN_CCCR_CSA_SHIFT (3U) -#define MCAN_CCCR_CSA_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSA_MASK) >> MCAN_CCCR_CSA_SHIFT) - -/* - * ASM (RW) - * - * Restricted Operation Mode - * Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. - * 0= Normal CAN operation - * 1= Restricted Operation Mode active - */ -#define MCAN_CCCR_ASM_MASK (0x4U) -#define MCAN_CCCR_ASM_SHIFT (2U) -#define MCAN_CCCR_ASM_SET(x) (((uint32_t)(x) << MCAN_CCCR_ASM_SHIFT) & MCAN_CCCR_ASM_MASK) -#define MCAN_CCCR_ASM_GET(x) (((uint32_t)(x) & MCAN_CCCR_ASM_MASK) >> MCAN_CCCR_ASM_SHIFT) - -/* - * CCE (RW) - * - * Configuration Change Enable - * 0= The CPU has no write access to the protected configuration registers - * 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - */ -#define MCAN_CCCR_CCE_MASK (0x2U) -#define MCAN_CCCR_CCE_SHIFT (1U) -#define MCAN_CCCR_CCE_SET(x) (((uint32_t)(x) << MCAN_CCCR_CCE_SHIFT) & MCAN_CCCR_CCE_MASK) -#define MCAN_CCCR_CCE_GET(x) (((uint32_t)(x) & MCAN_CCCR_CCE_MASK) >> MCAN_CCCR_CCE_SHIFT) - -/* - * INIT (RW) - * - * Initialization - * 0= Normal Operation - * 1= Initialization is started - */ -#define MCAN_CCCR_INIT_MASK (0x1U) -#define MCAN_CCCR_INIT_SHIFT (0U) -#define MCAN_CCCR_INIT_SET(x) (((uint32_t)(x) << MCAN_CCCR_INIT_SHIFT) & MCAN_CCCR_INIT_MASK) -#define MCAN_CCCR_INIT_GET(x) (((uint32_t)(x) & MCAN_CCCR_INIT_MASK) >> MCAN_CCCR_INIT_SHIFT) - -/* Bitfield definition for register: NBTP */ -/* - * NSJW (RW) - * - * Nominal (Re)Synchronization Jump Width - * Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NSJW_MASK (0xFE000000UL) -#define MCAN_NBTP_NSJW_SHIFT (25U) -#define MCAN_NBTP_NSJW_SET(x) (((uint32_t)(x) << MCAN_NBTP_NSJW_SHIFT) & MCAN_NBTP_NSJW_MASK) -#define MCAN_NBTP_NSJW_GET(x) (((uint32_t)(x) & MCAN_NBTP_NSJW_MASK) >> MCAN_NBTP_NSJW_SHIFT) - -/* - * NBRP (RW) - * - * Nominal Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is - * such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NBRP_MASK (0x1FF0000UL) -#define MCAN_NBTP_NBRP_SHIFT (16U) -#define MCAN_NBTP_NBRP_SET(x) (((uint32_t)(x) << MCAN_NBTP_NBRP_SHIFT) & MCAN_NBTP_NBRP_MASK) -#define MCAN_NBTP_NBRP_GET(x) (((uint32_t)(x) & MCAN_NBTP_NBRP_MASK) >> MCAN_NBTP_NBRP_SHIFT) - -/* - * NTSEG1 (RW) - * - * Nominal Time segment before sample point - * Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG1_MASK (0xFF00U) -#define MCAN_NBTP_NTSEG1_SHIFT (8U) -#define MCAN_NBTP_NTSEG1_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG1_SHIFT) & MCAN_NBTP_NTSEG1_MASK) -#define MCAN_NBTP_NTSEG1_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG1_MASK) >> MCAN_NBTP_NTSEG1_SHIFT) - -/* - * NTSEG2 (RW) - * - * Nominal Time segment after sample point - * Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG2_MASK (0x7FU) -#define MCAN_NBTP_NTSEG2_SHIFT (0U) -#define MCAN_NBTP_NTSEG2_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG2_SHIFT) & MCAN_NBTP_NTSEG2_MASK) -#define MCAN_NBTP_NTSEG2_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG2_MASK) >> MCAN_NBTP_NTSEG2_SHIFT) - -/* Bitfield definition for register: TSCC */ -/* - * TCP (RW) - * - * Timestamp Counter Prescaler - * Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_TSCC_TCP_MASK (0xF0000UL) -#define MCAN_TSCC_TCP_SHIFT (16U) -#define MCAN_TSCC_TCP_SET(x) (((uint32_t)(x) << MCAN_TSCC_TCP_SHIFT) & MCAN_TSCC_TCP_MASK) -#define MCAN_TSCC_TCP_GET(x) (((uint32_t)(x) & MCAN_TSCC_TCP_MASK) >> MCAN_TSCC_TCP_SHIFT) - -/* - * TSS (RW) - * - * timestamp Select - * 00= Timestamp counter value always 0x0000 - * 01= Timestamp counter value incremented according to TCP - * 10= External timestamp counter value used - * 11= Same as “00” - */ -#define MCAN_TSCC_TSS_MASK (0x3U) -#define MCAN_TSCC_TSS_SHIFT (0U) -#define MCAN_TSCC_TSS_SET(x) (((uint32_t)(x) << MCAN_TSCC_TSS_SHIFT) & MCAN_TSCC_TSS_MASK) -#define MCAN_TSCC_TSS_GET(x) (((uint32_t)(x) & MCAN_TSCC_TSS_MASK) >> MCAN_TSCC_TSS_SHIFT) - -/* Bitfield definition for register: TSCV */ -/* - * TSC (RC) - * - * Timestamp Counter - * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - */ -#define MCAN_TSCV_TSC_MASK (0xFFFFU) -#define MCAN_TSCV_TSC_SHIFT (0U) -#define MCAN_TSCV_TSC_GET(x) (((uint32_t)(x) & MCAN_TSCV_TSC_MASK) >> MCAN_TSCV_TSC_SHIFT) - -/* Bitfield definition for register: TOCC */ -/* - * TOP (RW) - * - * Timeout Period - * Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - */ -#define MCAN_TOCC_TOP_MASK (0xFFFF0000UL) -#define MCAN_TOCC_TOP_SHIFT (16U) -#define MCAN_TOCC_TOP_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOP_SHIFT) & MCAN_TOCC_TOP_MASK) -#define MCAN_TOCC_TOP_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOP_MASK) >> MCAN_TOCC_TOP_SHIFT) - -/* - * TOS (RW) - * - * Timeout Select - * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. - * When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. - * 00= Continuous operation - * 01= Timeout controlled by Tx Event FIFO - * 10= Timeout controlled by Rx FIFO 0 - * 11= Timeout controlled by Rx FIFO 1 - */ -#define MCAN_TOCC_TOS_MASK (0x6U) -#define MCAN_TOCC_TOS_SHIFT (1U) -#define MCAN_TOCC_TOS_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOS_SHIFT) & MCAN_TOCC_TOS_MASK) -#define MCAN_TOCC_TOS_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOS_MASK) >> MCAN_TOCC_TOS_SHIFT) - -/* - * RP (RW) - * - * Enable Timeout Counter - * 0= Timeout Counter disabled - * 1= Timeout Counter enabled - */ -#define MCAN_TOCC_RP_MASK (0x1U) -#define MCAN_TOCC_RP_SHIFT (0U) -#define MCAN_TOCC_RP_SET(x) (((uint32_t)(x) << MCAN_TOCC_RP_SHIFT) & MCAN_TOCC_RP_MASK) -#define MCAN_TOCC_RP_GET(x) (((uint32_t)(x) & MCAN_TOCC_RP_MASK) >> MCAN_TOCC_RP_SHIFT) - -/* Bitfield definition for register: TOCV */ -/* - * TOC (RC) - * - * Timeout Counter - * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. - * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - */ -#define MCAN_TOCV_TOC_MASK (0xFFFFU) -#define MCAN_TOCV_TOC_SHIFT (0U) -#define MCAN_TOCV_TOC_GET(x) (((uint32_t)(x) & MCAN_TOCV_TOC_MASK) >> MCAN_TOCV_TOC_SHIFT) - -/* Bitfield definition for register: ECR */ -/* - * CEL (X) - * - * CAN Error Logging - * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. - * The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. - * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. - * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - */ -#define MCAN_ECR_CEL_MASK (0xFF0000UL) -#define MCAN_ECR_CEL_SHIFT (16U) -#define MCAN_ECR_CEL_GET(x) (((uint32_t)(x) & MCAN_ECR_CEL_MASK) >> MCAN_ECR_CEL_SHIFT) - -/* - * RP (R) - * - * Receive Error Passive - * 0= The Receive Error Counter is below the error passive level of 128 - * 1= The Receive Error Counter has reached the error passive level of 128 - */ -#define MCAN_ECR_RP_MASK (0x8000U) -#define MCAN_ECR_RP_SHIFT (15U) -#define MCAN_ECR_RP_GET(x) (((uint32_t)(x) & MCAN_ECR_RP_MASK) >> MCAN_ECR_RP_SHIFT) - -/* - * REC (R) - * - * Receive Error Counter - * Actual state of the Receive Error Counter, values between 0 and 127 - */ -#define MCAN_ECR_REC_MASK (0x7F00U) -#define MCAN_ECR_REC_SHIFT (8U) -#define MCAN_ECR_REC_GET(x) (((uint32_t)(x) & MCAN_ECR_REC_MASK) >> MCAN_ECR_REC_SHIFT) - -/* - * TEC (R) - * - * Transmit Error Counter - * Actual state of the Transmit Error Counter, values between 0 and 255 - * Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - */ -#define MCAN_ECR_TEC_MASK (0xFFU) -#define MCAN_ECR_TEC_SHIFT (0U) -#define MCAN_ECR_TEC_GET(x) (((uint32_t)(x) & MCAN_ECR_TEC_MASK) >> MCAN_ECR_TEC_SHIFT) - -/* Bitfield definition for register: PSR */ -/* - * TDCV (R) - * - * Transmitter Delay Compensation Value - * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. - * The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_PSR_TDCV_MASK (0x7F0000UL) -#define MCAN_PSR_TDCV_SHIFT (16U) -#define MCAN_PSR_TDCV_GET(x) (((uint32_t)(x) & MCAN_PSR_TDCV_MASK) >> MCAN_PSR_TDCV_SHIFT) - -/* - * PXE (X) - * - * Protocol Exception Event - * 0= No protocol exception event occurred since last read access - * 1= Protocol exception event occurred - * Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_PXE_MASK (0x4000U) -#define MCAN_PSR_PXE_SHIFT (14U) -#define MCAN_PSR_PXE_GET(x) (((uint32_t)(x) & MCAN_PSR_PXE_MASK) >> MCAN_PSR_PXE_SHIFT) - -/* - * RFDF (X) - * - * Received a CAN FD Message - * This bit is set independent of acceptance filtering. - * 0= Since this bit was reset by the CPU, no CAN FD message has been received - * 1= Message in CAN FD format with FDF flag set has been received - * Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RFDF_MASK (0x2000U) -#define MCAN_PSR_RFDF_SHIFT (13U) -#define MCAN_PSR_RFDF_GET(x) (((uint32_t)(x) & MCAN_PSR_RFDF_MASK) >> MCAN_PSR_RFDF_SHIFT) - -/* - * RBRS (X) - * - * BRS flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its BRS flag set - * 1= Last received CAN FD message had its BRS flag set - * Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RBRS_MASK (0x1000U) -#define MCAN_PSR_RBRS_SHIFT (12U) -#define MCAN_PSR_RBRS_GET(x) (((uint32_t)(x) & MCAN_PSR_RBRS_MASK) >> MCAN_PSR_RBRS_SHIFT) - -/* - * RESI (X) - * - * ESI flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its ESI flag set - * 1= Last received CAN FD message had its ESI flag set - * Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RESI_MASK (0x800U) -#define MCAN_PSR_RESI_SHIFT (11U) -#define MCAN_PSR_RESI_GET(x) (((uint32_t)(x) & MCAN_PSR_RESI_MASK) >> MCAN_PSR_RESI_SHIFT) - -/* - * DLEC (S) - * - * Data Phase Last Error Code - * Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with - * its BRS flag set has been transferred (reception or transmission) without error. - * Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_DLEC_MASK (0x700U) -#define MCAN_PSR_DLEC_SHIFT (8U) -#define MCAN_PSR_DLEC_GET(x) (((uint32_t)(x) & MCAN_PSR_DLEC_MASK) >> MCAN_PSR_DLEC_SHIFT) - -/* - * BO (R) - * - * Bus_Off Status - * 0= The M_CAN is not Bus_Off - * 1= The M_CAN is in Bus_Off state - */ -#define MCAN_PSR_BO_MASK (0x80U) -#define MCAN_PSR_BO_SHIFT (7U) -#define MCAN_PSR_BO_GET(x) (((uint32_t)(x) & MCAN_PSR_BO_MASK) >> MCAN_PSR_BO_SHIFT) - -/* - * EW (R) - * - * Warning Status - * 0= Both error counters are below the Error_Warning limit of 96 - * 1= At least one of error counter has reached the Error_Warning limit of 96 - */ -#define MCAN_PSR_EW_MASK (0x40U) -#define MCAN_PSR_EW_SHIFT (6U) -#define MCAN_PSR_EW_GET(x) (((uint32_t)(x) & MCAN_PSR_EW_MASK) >> MCAN_PSR_EW_SHIFT) - -/* - * EP (R) - * - * Error Passive - * 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected - * 1= The M_CAN is in the Error_Passive state - */ -#define MCAN_PSR_EP_MASK (0x20U) -#define MCAN_PSR_EP_SHIFT (5U) -#define MCAN_PSR_EP_GET(x) (((uint32_t)(x) & MCAN_PSR_EP_MASK) >> MCAN_PSR_EP_SHIFT) - -/* - * ACT (R) - * - * Activity - * Monitors the module’s CAN communication state. - * 00= Synchronizing - node is synchronizing on CAN communication - * 01= Idle - node is neither receiver nor transmitter - * 10= Receiver - node is operating as receiver - * 11= Transmitter - node is operating as transmitter - * Note: ACT is set to “00” by a Protocol Exception Event. - */ -#define MCAN_PSR_ACT_MASK (0x18U) -#define MCAN_PSR_ACT_SHIFT (3U) -#define MCAN_PSR_ACT_GET(x) (((uint32_t)(x) & MCAN_PSR_ACT_MASK) >> MCAN_PSR_ACT_SHIFT) - -/* - * LEC (S) - * - * Last Error Code - * The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. - * 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. - * 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. - * 2= Form Error: A fixed format part of a received frame has the wrong format. - * 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. - * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), - * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus - * value was dominant. - * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - * During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at - * dominant or continuously disturbed). - * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. - * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. - * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. - * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - * Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. - * At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, - * enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. - * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_LEC_MASK (0x7U) -#define MCAN_PSR_LEC_SHIFT (0U) -#define MCAN_PSR_LEC_GET(x) (((uint32_t)(x) & MCAN_PSR_LEC_MASK) >> MCAN_PSR_LEC_SHIFT) - -/* Bitfield definition for register: TDCR */ -/* - * TDCO (RW) - * - * Transmitter Delay Compensation SSP Offset - * Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCO_MASK (0x7F00U) -#define MCAN_TDCR_TDCO_SHIFT (8U) -#define MCAN_TDCR_TDCO_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCO_SHIFT) & MCAN_TDCR_TDCO_MASK) -#define MCAN_TDCR_TDCO_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCO_MASK) >> MCAN_TDCR_TDCO_SHIFT) - -/* - * TDCF (RW) - * - * Transmitter Delay Compensation Filter Window Length - * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. - * The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCF_MASK (0x7FU) -#define MCAN_TDCR_TDCF_SHIFT (0U) -#define MCAN_TDCR_TDCF_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCF_SHIFT) & MCAN_TDCR_TDCF_MASK) -#define MCAN_TDCR_TDCF_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCF_MASK) >> MCAN_TDCR_TDCF_SHIFT) - -/* Bitfield definition for register: IR */ -/* - * ARA (RW) - * - * Access to Reserved Address - * 0= No access to reserved address occurred - * 1= Access to reserved address occurred - */ -#define MCAN_IR_ARA_MASK (0x20000000UL) -#define MCAN_IR_ARA_SHIFT (29U) -#define MCAN_IR_ARA_SET(x) (((uint32_t)(x) << MCAN_IR_ARA_SHIFT) & MCAN_IR_ARA_MASK) -#define MCAN_IR_ARA_GET(x) (((uint32_t)(x) & MCAN_IR_ARA_MASK) >> MCAN_IR_ARA_SHIFT) - -/* - * PED (RW) - * - * Protocol Error in Data Phase (Data Bit Time is used) - * 0= No protocol error in data phase - * 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - */ -#define MCAN_IR_PED_MASK (0x10000000UL) -#define MCAN_IR_PED_SHIFT (28U) -#define MCAN_IR_PED_SET(x) (((uint32_t)(x) << MCAN_IR_PED_SHIFT) & MCAN_IR_PED_MASK) -#define MCAN_IR_PED_GET(x) (((uint32_t)(x) & MCAN_IR_PED_MASK) >> MCAN_IR_PED_SHIFT) - -/* - * PEA (RW) - * - * Protocol Error in Arbitration Phase (Nominal Bit Time is used) - * 0= No protocol error in arbitration phase - * 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - */ -#define MCAN_IR_PEA_MASK (0x8000000UL) -#define MCAN_IR_PEA_SHIFT (27U) -#define MCAN_IR_PEA_SET(x) (((uint32_t)(x) << MCAN_IR_PEA_SHIFT) & MCAN_IR_PEA_MASK) -#define MCAN_IR_PEA_GET(x) (((uint32_t)(x) & MCAN_IR_PEA_MASK) >> MCAN_IR_PEA_SHIFT) - -/* - * WDI (RW) - * - * Watchdog Interrupt - * 0= No Message RAM Watchdog event occurred - * 1= Message RAM Watchdog event due to missing READY - */ -#define MCAN_IR_WDI_MASK (0x4000000UL) -#define MCAN_IR_WDI_SHIFT (26U) -#define MCAN_IR_WDI_SET(x) (((uint32_t)(x) << MCAN_IR_WDI_SHIFT) & MCAN_IR_WDI_MASK) -#define MCAN_IR_WDI_GET(x) (((uint32_t)(x) & MCAN_IR_WDI_MASK) >> MCAN_IR_WDI_SHIFT) - -/* - * BO (RW) - * - * Bus_Off Status - * 0= Bus_Off status unchanged - * 1= Bus_Off status changed - */ -#define MCAN_IR_BO_MASK (0x2000000UL) -#define MCAN_IR_BO_SHIFT (25U) -#define MCAN_IR_BO_SET(x) (((uint32_t)(x) << MCAN_IR_BO_SHIFT) & MCAN_IR_BO_MASK) -#define MCAN_IR_BO_GET(x) (((uint32_t)(x) & MCAN_IR_BO_MASK) >> MCAN_IR_BO_SHIFT) - -/* - * EW (RW) - * - * Warning Status - * 0= Error_Warning status unchanged - * 1= Error_Warning status changed - */ -#define MCAN_IR_EW_MASK (0x1000000UL) -#define MCAN_IR_EW_SHIFT (24U) -#define MCAN_IR_EW_SET(x) (((uint32_t)(x) << MCAN_IR_EW_SHIFT) & MCAN_IR_EW_MASK) -#define MCAN_IR_EW_GET(x) (((uint32_t)(x) & MCAN_IR_EW_MASK) >> MCAN_IR_EW_SHIFT) - -/* - * EP (RW) - * - * Error Passive - * 0= Error_Passive status unchanged - * 1= Error_Passive status changed - */ -#define MCAN_IR_EP_MASK (0x800000UL) -#define MCAN_IR_EP_SHIFT (23U) -#define MCAN_IR_EP_SET(x) (((uint32_t)(x) << MCAN_IR_EP_SHIFT) & MCAN_IR_EP_MASK) -#define MCAN_IR_EP_GET(x) (((uint32_t)(x) & MCAN_IR_EP_MASK) >> MCAN_IR_EP_SHIFT) - -/* - * ELO (RW) - * - * Error Logging Overflow - * 0= CAN Error Logging Counter did not overflow - * 1= Overflow of CAN Error Logging Counter occurred - */ -#define MCAN_IR_ELO_MASK (0x400000UL) -#define MCAN_IR_ELO_SHIFT (22U) -#define MCAN_IR_ELO_SET(x) (((uint32_t)(x) << MCAN_IR_ELO_SHIFT) & MCAN_IR_ELO_MASK) -#define MCAN_IR_ELO_GET(x) (((uint32_t)(x) & MCAN_IR_ELO_MASK) >> MCAN_IR_ELO_SHIFT) - -/* - * BEU (RW) - * - * Bit Error Uncorrected - * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. - * An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected, uncorrected (e.g. parity logic) - */ -#define MCAN_IR_BEU_MASK (0x200000UL) -#define MCAN_IR_BEU_SHIFT (21U) -#define MCAN_IR_BEU_SET(x) (((uint32_t)(x) << MCAN_IR_BEU_SHIFT) & MCAN_IR_BEU_MASK) -#define MCAN_IR_BEU_GET(x) (((uint32_t)(x) & MCAN_IR_BEU_MASK) >> MCAN_IR_BEU_SHIFT) - -/* - * BEC (RW) - * - * Bit Error Corrected - * Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected and corrected (e.g. ECC) - */ -#define MCAN_IR_BEC_MASK (0x100000UL) -#define MCAN_IR_BEC_SHIFT (20U) -#define MCAN_IR_BEC_SET(x) (((uint32_t)(x) << MCAN_IR_BEC_SHIFT) & MCAN_IR_BEC_MASK) -#define MCAN_IR_BEC_GET(x) (((uint32_t)(x) & MCAN_IR_BEC_MASK) >> MCAN_IR_BEC_SHIFT) - -/* - * DRX (RW) - * - * Message stored to Dedicated Rx Buffer - * The flag is set whenever a received message has been stored into a dedicated Rx Buffer. - * 0= No Rx Buffer updated - * 1= At least one received message stored into an Rx Buffer - */ -#define MCAN_IR_DRX_MASK (0x80000UL) -#define MCAN_IR_DRX_SHIFT (19U) -#define MCAN_IR_DRX_SET(x) (((uint32_t)(x) << MCAN_IR_DRX_SHIFT) & MCAN_IR_DRX_MASK) -#define MCAN_IR_DRX_GET(x) (((uint32_t)(x) & MCAN_IR_DRX_MASK) >> MCAN_IR_DRX_SHIFT) - -/* - * TOO (RW) - * - * Timeout Occurred - * 0= No timeout - * 1= Timeout reached - */ -#define MCAN_IR_TOO_MASK (0x40000UL) -#define MCAN_IR_TOO_SHIFT (18U) -#define MCAN_IR_TOO_SET(x) (((uint32_t)(x) << MCAN_IR_TOO_SHIFT) & MCAN_IR_TOO_MASK) -#define MCAN_IR_TOO_GET(x) (((uint32_t)(x) & MCAN_IR_TOO_MASK) >> MCAN_IR_TOO_SHIFT) - -/* - * MRAF (RW) - * - * Message RAM Access Failure - * The flag is set, when the Rx Handler - * .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message - * storage is aborted and the Rx Handler starts processing of the following message. - * .was not able to write a message to the Message RAM. In this case message storage is aborted. - * In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. - * The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the - * M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. - * 0= No Message RAM access failure occurred - * 1= Message RAM access failure occurred - */ -#define MCAN_IR_MRAF_MASK (0x20000UL) -#define MCAN_IR_MRAF_SHIFT (17U) -#define MCAN_IR_MRAF_SET(x) (((uint32_t)(x) << MCAN_IR_MRAF_SHIFT) & MCAN_IR_MRAF_MASK) -#define MCAN_IR_MRAF_GET(x) (((uint32_t)(x) & MCAN_IR_MRAF_MASK) >> MCAN_IR_MRAF_SHIFT) - -/* - * TSW (RW) - * - * Timestamp Wraparound - * 0= No timestamp counter wrap-around - * 1= Timestamp counter wrapped around - */ -#define MCAN_IR_TSW_MASK (0x10000UL) -#define MCAN_IR_TSW_SHIFT (16U) -#define MCAN_IR_TSW_SET(x) (((uint32_t)(x) << MCAN_IR_TSW_SHIFT) & MCAN_IR_TSW_MASK) -#define MCAN_IR_TSW_GET(x) (((uint32_t)(x) & MCAN_IR_TSW_MASK) >> MCAN_IR_TSW_SHIFT) - -/* - * TEFL (RW) - * - * Tx Event FIFO Element Lost - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - */ -#define MCAN_IR_TEFL_MASK (0x8000U) -#define MCAN_IR_TEFL_SHIFT (15U) -#define MCAN_IR_TEFL_SET(x) (((uint32_t)(x) << MCAN_IR_TEFL_SHIFT) & MCAN_IR_TEFL_MASK) -#define MCAN_IR_TEFL_GET(x) (((uint32_t)(x) & MCAN_IR_TEFL_MASK) >> MCAN_IR_TEFL_SHIFT) - -/* - * TEFF (RW) - * - * Tx Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_IR_TEFF_MASK (0x4000U) -#define MCAN_IR_TEFF_SHIFT (14U) -#define MCAN_IR_TEFF_SET(x) (((uint32_t)(x) << MCAN_IR_TEFF_SHIFT) & MCAN_IR_TEFF_MASK) -#define MCAN_IR_TEFF_GET(x) (((uint32_t)(x) & MCAN_IR_TEFF_MASK) >> MCAN_IR_TEFF_SHIFT) - -/* - * TEFW (RW) - * - * Tx Event FIFO Watermark Reached - * 0= Tx Event FIFO fill level below watermark - * 1= Tx Event FIFO fill level reached watermark - */ -#define MCAN_IR_TEFW_MASK (0x2000U) -#define MCAN_IR_TEFW_SHIFT (13U) -#define MCAN_IR_TEFW_SET(x) (((uint32_t)(x) << MCAN_IR_TEFW_SHIFT) & MCAN_IR_TEFW_MASK) -#define MCAN_IR_TEFW_GET(x) (((uint32_t)(x) & MCAN_IR_TEFW_MASK) >> MCAN_IR_TEFW_SHIFT) - -/* - * TEFN (RW) - * - * Tx Event FIFO New Entry - * 0= Tx Event FIFO unchanged - * 1= Tx Handler wrote Tx Event FIFO element - */ -#define MCAN_IR_TEFN_MASK (0x1000U) -#define MCAN_IR_TEFN_SHIFT (12U) -#define MCAN_IR_TEFN_SET(x) (((uint32_t)(x) << MCAN_IR_TEFN_SHIFT) & MCAN_IR_TEFN_MASK) -#define MCAN_IR_TEFN_GET(x) (((uint32_t)(x) & MCAN_IR_TEFN_MASK) >> MCAN_IR_TEFN_SHIFT) - -/* - * TFE (RW) - * - * Tx FIFO Empty - * 0= Tx FIFO non-empty - * 1= Tx FIFO empty - */ -#define MCAN_IR_TFE_MASK (0x800U) -#define MCAN_IR_TFE_SHIFT (11U) -#define MCAN_IR_TFE_SET(x) (((uint32_t)(x) << MCAN_IR_TFE_SHIFT) & MCAN_IR_TFE_MASK) -#define MCAN_IR_TFE_GET(x) (((uint32_t)(x) & MCAN_IR_TFE_MASK) >> MCAN_IR_TFE_SHIFT) - -/* - * TCF (RW) - * - * Transmission Cancellation Finished - * 0= No transmission cancellation finished - * 1= Transmission cancellation finished - */ -#define MCAN_IR_TCF_MASK (0x400U) -#define MCAN_IR_TCF_SHIFT (10U) -#define MCAN_IR_TCF_SET(x) (((uint32_t)(x) << MCAN_IR_TCF_SHIFT) & MCAN_IR_TCF_MASK) -#define MCAN_IR_TCF_GET(x) (((uint32_t)(x) & MCAN_IR_TCF_MASK) >> MCAN_IR_TCF_SHIFT) - -/* - * TC (RW) - * - * Transmission Completed - * 0= No transmission completed - * 1= Transmission completed - */ -#define MCAN_IR_TC_MASK (0x200U) -#define MCAN_IR_TC_SHIFT (9U) -#define MCAN_IR_TC_SET(x) (((uint32_t)(x) << MCAN_IR_TC_SHIFT) & MCAN_IR_TC_MASK) -#define MCAN_IR_TC_GET(x) (((uint32_t)(x) & MCAN_IR_TC_MASK) >> MCAN_IR_TC_SHIFT) - -/* - * HPM (RW) - * - * High Priority Message - * 0= No high priority message received - * 1= High priority message received - */ -#define MCAN_IR_HPM_MASK (0x100U) -#define MCAN_IR_HPM_SHIFT (8U) -#define MCAN_IR_HPM_SET(x) (((uint32_t)(x) << MCAN_IR_HPM_SHIFT) & MCAN_IR_HPM_MASK) -#define MCAN_IR_HPM_GET(x) (((uint32_t)(x) & MCAN_IR_HPM_MASK) >> MCAN_IR_HPM_SHIFT) - -/* - * RF1L (RW) - * - * Rx FIFO 1 Message Lost - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - */ -#define MCAN_IR_RF1L_MASK (0x80U) -#define MCAN_IR_RF1L_SHIFT (7U) -#define MCAN_IR_RF1L_SET(x) (((uint32_t)(x) << MCAN_IR_RF1L_SHIFT) & MCAN_IR_RF1L_MASK) -#define MCAN_IR_RF1L_GET(x) (((uint32_t)(x) & MCAN_IR_RF1L_MASK) >> MCAN_IR_RF1L_SHIFT) - -/* - * RF1F (RW) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_IR_RF1F_MASK (0x40U) -#define MCAN_IR_RF1F_SHIFT (6U) -#define MCAN_IR_RF1F_SET(x) (((uint32_t)(x) << MCAN_IR_RF1F_SHIFT) & MCAN_IR_RF1F_MASK) -#define MCAN_IR_RF1F_GET(x) (((uint32_t)(x) & MCAN_IR_RF1F_MASK) >> MCAN_IR_RF1F_SHIFT) - -/* - * RF1W (RW) - * - * Rx FIFO 1 Watermark Reached - * 0= Rx FIFO 1 fill level below watermark - * 1= Rx FIFO 1 fill level reached watermark - */ -#define MCAN_IR_RF1W_MASK (0x20U) -#define MCAN_IR_RF1W_SHIFT (5U) -#define MCAN_IR_RF1W_SET(x) (((uint32_t)(x) << MCAN_IR_RF1W_SHIFT) & MCAN_IR_RF1W_MASK) -#define MCAN_IR_RF1W_GET(x) (((uint32_t)(x) & MCAN_IR_RF1W_MASK) >> MCAN_IR_RF1W_SHIFT) - -/* - * RF1N (RW) - * - * Rx FIFO 1 New Message - * 0= No new message written to Rx FIFO 1 - * 1= New message written to Rx FIFO 1 - */ -#define MCAN_IR_RF1N_MASK (0x10U) -#define MCAN_IR_RF1N_SHIFT (4U) -#define MCAN_IR_RF1N_SET(x) (((uint32_t)(x) << MCAN_IR_RF1N_SHIFT) & MCAN_IR_RF1N_MASK) -#define MCAN_IR_RF1N_GET(x) (((uint32_t)(x) & MCAN_IR_RF1N_MASK) >> MCAN_IR_RF1N_SHIFT) - -/* - * RF0L (RW) - * - * Rx FIFO 0 Message Lost - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - */ -#define MCAN_IR_RF0L_MASK (0x8U) -#define MCAN_IR_RF0L_SHIFT (3U) -#define MCAN_IR_RF0L_SET(x) (((uint32_t)(x) << MCAN_IR_RF0L_SHIFT) & MCAN_IR_RF0L_MASK) -#define MCAN_IR_RF0L_GET(x) (((uint32_t)(x) & MCAN_IR_RF0L_MASK) >> MCAN_IR_RF0L_SHIFT) - -/* - * RF0F (RW) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_IR_RF0F_MASK (0x4U) -#define MCAN_IR_RF0F_SHIFT (2U) -#define MCAN_IR_RF0F_SET(x) (((uint32_t)(x) << MCAN_IR_RF0F_SHIFT) & MCAN_IR_RF0F_MASK) -#define MCAN_IR_RF0F_GET(x) (((uint32_t)(x) & MCAN_IR_RF0F_MASK) >> MCAN_IR_RF0F_SHIFT) - -/* - * RF0W (RW) - * - * Rx FIFO 0 Watermark Reached - * 0= Rx FIFO 0 fill level below watermark - * 1= Rx FIFO 0 fill level reached watermark - */ -#define MCAN_IR_RF0W_MASK (0x2U) -#define MCAN_IR_RF0W_SHIFT (1U) -#define MCAN_IR_RF0W_SET(x) (((uint32_t)(x) << MCAN_IR_RF0W_SHIFT) & MCAN_IR_RF0W_MASK) -#define MCAN_IR_RF0W_GET(x) (((uint32_t)(x) & MCAN_IR_RF0W_MASK) >> MCAN_IR_RF0W_SHIFT) - -/* - * RF0N (RW) - * - * Rx FIFO 0 New Message - * 0= No new message written to Rx FIFO 0 - * 1= New message written to Rx FIFO 0 - */ -#define MCAN_IR_RF0N_MASK (0x1U) -#define MCAN_IR_RF0N_SHIFT (0U) -#define MCAN_IR_RF0N_SET(x) (((uint32_t)(x) << MCAN_IR_RF0N_SHIFT) & MCAN_IR_RF0N_MASK) -#define MCAN_IR_RF0N_GET(x) (((uint32_t)(x) & MCAN_IR_RF0N_MASK) >> MCAN_IR_RF0N_SHIFT) - -/* Bitfield definition for register: IE */ -/* - * ARAE (RW) - * - * Access to Reserved Address Enable - */ -#define MCAN_IE_ARAE_MASK (0x20000000UL) -#define MCAN_IE_ARAE_SHIFT (29U) -#define MCAN_IE_ARAE_SET(x) (((uint32_t)(x) << MCAN_IE_ARAE_SHIFT) & MCAN_IE_ARAE_MASK) -#define MCAN_IE_ARAE_GET(x) (((uint32_t)(x) & MCAN_IE_ARAE_MASK) >> MCAN_IE_ARAE_SHIFT) - -/* - * PEDE (RW) - * - * Protocol Error in Data Phase Enable - */ -#define MCAN_IE_PEDE_MASK (0x10000000UL) -#define MCAN_IE_PEDE_SHIFT (28U) -#define MCAN_IE_PEDE_SET(x) (((uint32_t)(x) << MCAN_IE_PEDE_SHIFT) & MCAN_IE_PEDE_MASK) -#define MCAN_IE_PEDE_GET(x) (((uint32_t)(x) & MCAN_IE_PEDE_MASK) >> MCAN_IE_PEDE_SHIFT) - -/* - * PEAE (RW) - * - * Protocol Error in Arbitration Phase Enable - */ -#define MCAN_IE_PEAE_MASK (0x8000000UL) -#define MCAN_IE_PEAE_SHIFT (27U) -#define MCAN_IE_PEAE_SET(x) (((uint32_t)(x) << MCAN_IE_PEAE_SHIFT) & MCAN_IE_PEAE_MASK) -#define MCAN_IE_PEAE_GET(x) (((uint32_t)(x) & MCAN_IE_PEAE_MASK) >> MCAN_IE_PEAE_SHIFT) - -/* - * WDIE (RW) - * - * Watchdog Interrupt Enable - */ -#define MCAN_IE_WDIE_MASK (0x4000000UL) -#define MCAN_IE_WDIE_SHIFT (26U) -#define MCAN_IE_WDIE_SET(x) (((uint32_t)(x) << MCAN_IE_WDIE_SHIFT) & MCAN_IE_WDIE_MASK) -#define MCAN_IE_WDIE_GET(x) (((uint32_t)(x) & MCAN_IE_WDIE_MASK) >> MCAN_IE_WDIE_SHIFT) - -/* - * BOE (RW) - * - * Bus_Off Status Interrupt Enable - */ -#define MCAN_IE_BOE_MASK (0x2000000UL) -#define MCAN_IE_BOE_SHIFT (25U) -#define MCAN_IE_BOE_SET(x) (((uint32_t)(x) << MCAN_IE_BOE_SHIFT) & MCAN_IE_BOE_MASK) -#define MCAN_IE_BOE_GET(x) (((uint32_t)(x) & MCAN_IE_BOE_MASK) >> MCAN_IE_BOE_SHIFT) - -/* - * EWE (RW) - * - * Warning Status Interrupt Enable - */ -#define MCAN_IE_EWE_MASK (0x1000000UL) -#define MCAN_IE_EWE_SHIFT (24U) -#define MCAN_IE_EWE_SET(x) (((uint32_t)(x) << MCAN_IE_EWE_SHIFT) & MCAN_IE_EWE_MASK) -#define MCAN_IE_EWE_GET(x) (((uint32_t)(x) & MCAN_IE_EWE_MASK) >> MCAN_IE_EWE_SHIFT) - -/* - * EPE (RW) - * - * Error Passive Interrupt Enable - */ -#define MCAN_IE_EPE_MASK (0x800000UL) -#define MCAN_IE_EPE_SHIFT (23U) -#define MCAN_IE_EPE_SET(x) (((uint32_t)(x) << MCAN_IE_EPE_SHIFT) & MCAN_IE_EPE_MASK) -#define MCAN_IE_EPE_GET(x) (((uint32_t)(x) & MCAN_IE_EPE_MASK) >> MCAN_IE_EPE_SHIFT) - -/* - * ELOE (RW) - * - * Error Logging Overflow Interrupt Enable - */ -#define MCAN_IE_ELOE_MASK (0x400000UL) -#define MCAN_IE_ELOE_SHIFT (22U) -#define MCAN_IE_ELOE_SET(x) (((uint32_t)(x) << MCAN_IE_ELOE_SHIFT) & MCAN_IE_ELOE_MASK) -#define MCAN_IE_ELOE_GET(x) (((uint32_t)(x) & MCAN_IE_ELOE_MASK) >> MCAN_IE_ELOE_SHIFT) - -/* - * BEUE (RW) - * - * Bit Error Uncorrected Interrupt Enable - */ -#define MCAN_IE_BEUE_MASK (0x200000UL) -#define MCAN_IE_BEUE_SHIFT (21U) -#define MCAN_IE_BEUE_SET(x) (((uint32_t)(x) << MCAN_IE_BEUE_SHIFT) & MCAN_IE_BEUE_MASK) -#define MCAN_IE_BEUE_GET(x) (((uint32_t)(x) & MCAN_IE_BEUE_MASK) >> MCAN_IE_BEUE_SHIFT) - -/* - * BECE (RW) - * - * Bit Error Corrected Interrupt Enable - */ -#define MCAN_IE_BECE_MASK (0x100000UL) -#define MCAN_IE_BECE_SHIFT (20U) -#define MCAN_IE_BECE_SET(x) (((uint32_t)(x) << MCAN_IE_BECE_SHIFT) & MCAN_IE_BECE_MASK) -#define MCAN_IE_BECE_GET(x) (((uint32_t)(x) & MCAN_IE_BECE_MASK) >> MCAN_IE_BECE_SHIFT) - -/* - * DRXE (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Enable - */ -#define MCAN_IE_DRXE_MASK (0x80000UL) -#define MCAN_IE_DRXE_SHIFT (19U) -#define MCAN_IE_DRXE_SET(x) (((uint32_t)(x) << MCAN_IE_DRXE_SHIFT) & MCAN_IE_DRXE_MASK) -#define MCAN_IE_DRXE_GET(x) (((uint32_t)(x) & MCAN_IE_DRXE_MASK) >> MCAN_IE_DRXE_SHIFT) - -/* - * TOOE (RW) - * - * Timeout Occurred Interrupt Enable - */ -#define MCAN_IE_TOOE_MASK (0x40000UL) -#define MCAN_IE_TOOE_SHIFT (18U) -#define MCAN_IE_TOOE_SET(x) (((uint32_t)(x) << MCAN_IE_TOOE_SHIFT) & MCAN_IE_TOOE_MASK) -#define MCAN_IE_TOOE_GET(x) (((uint32_t)(x) & MCAN_IE_TOOE_MASK) >> MCAN_IE_TOOE_SHIFT) - -/* - * MRAFE (RW) - * - * Message RAM Access Failure Interrupt Enable - */ -#define MCAN_IE_MRAFE_MASK (0x20000UL) -#define MCAN_IE_MRAFE_SHIFT (17U) -#define MCAN_IE_MRAFE_SET(x) (((uint32_t)(x) << MCAN_IE_MRAFE_SHIFT) & MCAN_IE_MRAFE_MASK) -#define MCAN_IE_MRAFE_GET(x) (((uint32_t)(x) & MCAN_IE_MRAFE_MASK) >> MCAN_IE_MRAFE_SHIFT) - -/* - * TSWE (RW) - * - * Timestamp Wraparound Interrupt Enable - */ -#define MCAN_IE_TSWE_MASK (0x10000UL) -#define MCAN_IE_TSWE_SHIFT (16U) -#define MCAN_IE_TSWE_SET(x) (((uint32_t)(x) << MCAN_IE_TSWE_SHIFT) & MCAN_IE_TSWE_MASK) -#define MCAN_IE_TSWE_GET(x) (((uint32_t)(x) & MCAN_IE_TSWE_MASK) >> MCAN_IE_TSWE_SHIFT) - -/* - * TEFLE (RW) - * - * Tx Event FIFO Event Lost Interrupt Enable - */ -#define MCAN_IE_TEFLE_MASK (0x8000U) -#define MCAN_IE_TEFLE_SHIFT (15U) -#define MCAN_IE_TEFLE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFLE_SHIFT) & MCAN_IE_TEFLE_MASK) -#define MCAN_IE_TEFLE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFLE_MASK) >> MCAN_IE_TEFLE_SHIFT) - -/* - * TEFFE (RW) - * - * Tx Event FIFO Full Interrupt Enable - */ -#define MCAN_IE_TEFFE_MASK (0x4000U) -#define MCAN_IE_TEFFE_SHIFT (14U) -#define MCAN_IE_TEFFE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFFE_SHIFT) & MCAN_IE_TEFFE_MASK) -#define MCAN_IE_TEFFE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFFE_MASK) >> MCAN_IE_TEFFE_SHIFT) - -/* - * TEFWE (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Enable - */ -#define MCAN_IE_TEFWE_MASK (0x2000U) -#define MCAN_IE_TEFWE_SHIFT (13U) -#define MCAN_IE_TEFWE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFWE_SHIFT) & MCAN_IE_TEFWE_MASK) -#define MCAN_IE_TEFWE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFWE_MASK) >> MCAN_IE_TEFWE_SHIFT) - -/* - * TEFNE (RW) - * - * Tx Event FIFO New Entry Interrupt Enable - */ -#define MCAN_IE_TEFNE_MASK (0x1000U) -#define MCAN_IE_TEFNE_SHIFT (12U) -#define MCAN_IE_TEFNE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFNE_SHIFT) & MCAN_IE_TEFNE_MASK) -#define MCAN_IE_TEFNE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFNE_MASK) >> MCAN_IE_TEFNE_SHIFT) - -/* - * TFEE (RW) - * - * Tx FIFO Empty Interrupt Enable - */ -#define MCAN_IE_TFEE_MASK (0x800U) -#define MCAN_IE_TFEE_SHIFT (11U) -#define MCAN_IE_TFEE_SET(x) (((uint32_t)(x) << MCAN_IE_TFEE_SHIFT) & MCAN_IE_TFEE_MASK) -#define MCAN_IE_TFEE_GET(x) (((uint32_t)(x) & MCAN_IE_TFEE_MASK) >> MCAN_IE_TFEE_SHIFT) - -/* - * TCFE (RW) - * - * Transmission Cancellation Finished Interrupt Enable - */ -#define MCAN_IE_TCFE_MASK (0x400U) -#define MCAN_IE_TCFE_SHIFT (10U) -#define MCAN_IE_TCFE_SET(x) (((uint32_t)(x) << MCAN_IE_TCFE_SHIFT) & MCAN_IE_TCFE_MASK) -#define MCAN_IE_TCFE_GET(x) (((uint32_t)(x) & MCAN_IE_TCFE_MASK) >> MCAN_IE_TCFE_SHIFT) - -/* - * TCE (RW) - * - * Transmission Completed Interrupt Enable - */ -#define MCAN_IE_TCE_MASK (0x200U) -#define MCAN_IE_TCE_SHIFT (9U) -#define MCAN_IE_TCE_SET(x) (((uint32_t)(x) << MCAN_IE_TCE_SHIFT) & MCAN_IE_TCE_MASK) -#define MCAN_IE_TCE_GET(x) (((uint32_t)(x) & MCAN_IE_TCE_MASK) >> MCAN_IE_TCE_SHIFT) - -/* - * HPME (RW) - * - * High Priority Message Interrupt Enable - */ -#define MCAN_IE_HPME_MASK (0x100U) -#define MCAN_IE_HPME_SHIFT (8U) -#define MCAN_IE_HPME_SET(x) (((uint32_t)(x) << MCAN_IE_HPME_SHIFT) & MCAN_IE_HPME_MASK) -#define MCAN_IE_HPME_GET(x) (((uint32_t)(x) & MCAN_IE_HPME_MASK) >> MCAN_IE_HPME_SHIFT) - -/* - * RF1LE (RW) - * - * Rx FIFO 1 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF1LE_MASK (0x80U) -#define MCAN_IE_RF1LE_SHIFT (7U) -#define MCAN_IE_RF1LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1LE_SHIFT) & MCAN_IE_RF1LE_MASK) -#define MCAN_IE_RF1LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1LE_MASK) >> MCAN_IE_RF1LE_SHIFT) - -/* - * RF1FE (RW) - * - * Rx FIFO 1 Full Interrupt Enable - */ -#define MCAN_IE_RF1FE_MASK (0x40U) -#define MCAN_IE_RF1FE_SHIFT (6U) -#define MCAN_IE_RF1FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1FE_SHIFT) & MCAN_IE_RF1FE_MASK) -#define MCAN_IE_RF1FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1FE_MASK) >> MCAN_IE_RF1FE_SHIFT) - -/* - * RF1WE (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF1WE_MASK (0x20U) -#define MCAN_IE_RF1WE_SHIFT (5U) -#define MCAN_IE_RF1WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1WE_SHIFT) & MCAN_IE_RF1WE_MASK) -#define MCAN_IE_RF1WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1WE_MASK) >> MCAN_IE_RF1WE_SHIFT) - -/* - * RF1NE (RW) - * - * Rx FIFO 1 New Message Interrupt Enable - */ -#define MCAN_IE_RF1NE_MASK (0x10U) -#define MCAN_IE_RF1NE_SHIFT (4U) -#define MCAN_IE_RF1NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1NE_SHIFT) & MCAN_IE_RF1NE_MASK) -#define MCAN_IE_RF1NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1NE_MASK) >> MCAN_IE_RF1NE_SHIFT) - -/* - * RF0LE (RW) - * - * Rx FIFO 0 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF0LE_MASK (0x8U) -#define MCAN_IE_RF0LE_SHIFT (3U) -#define MCAN_IE_RF0LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0LE_SHIFT) & MCAN_IE_RF0LE_MASK) -#define MCAN_IE_RF0LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0LE_MASK) >> MCAN_IE_RF0LE_SHIFT) - -/* - * RF0FE (RW) - * - * Rx FIFO 0 Full Interrupt Enable - */ -#define MCAN_IE_RF0FE_MASK (0x4U) -#define MCAN_IE_RF0FE_SHIFT (2U) -#define MCAN_IE_RF0FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0FE_SHIFT) & MCAN_IE_RF0FE_MASK) -#define MCAN_IE_RF0FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0FE_MASK) >> MCAN_IE_RF0FE_SHIFT) - -/* - * RF0WE (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF0WE_MASK (0x2U) -#define MCAN_IE_RF0WE_SHIFT (1U) -#define MCAN_IE_RF0WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0WE_SHIFT) & MCAN_IE_RF0WE_MASK) -#define MCAN_IE_RF0WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0WE_MASK) >> MCAN_IE_RF0WE_SHIFT) - -/* - * RF0NE (RW) - * - * Rx FIFO 0 New Message Interrupt Enable - */ -#define MCAN_IE_RF0NE_MASK (0x1U) -#define MCAN_IE_RF0NE_SHIFT (0U) -#define MCAN_IE_RF0NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0NE_SHIFT) & MCAN_IE_RF0NE_MASK) -#define MCAN_IE_RF0NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0NE_MASK) >> MCAN_IE_RF0NE_SHIFT) - -/* Bitfield definition for register: ILS */ -/* - * ARAL (RW) - * - * Access to Reserved Address Line - */ -#define MCAN_ILS_ARAL_MASK (0x20000000UL) -#define MCAN_ILS_ARAL_SHIFT (29U) -#define MCAN_ILS_ARAL_SET(x) (((uint32_t)(x) << MCAN_ILS_ARAL_SHIFT) & MCAN_ILS_ARAL_MASK) -#define MCAN_ILS_ARAL_GET(x) (((uint32_t)(x) & MCAN_ILS_ARAL_MASK) >> MCAN_ILS_ARAL_SHIFT) - -/* - * PEDL (RW) - * - * Protocol Error in Data Phase Line - */ -#define MCAN_ILS_PEDL_MASK (0x10000000UL) -#define MCAN_ILS_PEDL_SHIFT (28U) -#define MCAN_ILS_PEDL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEDL_SHIFT) & MCAN_ILS_PEDL_MASK) -#define MCAN_ILS_PEDL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEDL_MASK) >> MCAN_ILS_PEDL_SHIFT) - -/* - * PEAL (RW) - * - * Protocol Error in Arbitration Phase Line - */ -#define MCAN_ILS_PEAL_MASK (0x8000000UL) -#define MCAN_ILS_PEAL_SHIFT (27U) -#define MCAN_ILS_PEAL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEAL_SHIFT) & MCAN_ILS_PEAL_MASK) -#define MCAN_ILS_PEAL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEAL_MASK) >> MCAN_ILS_PEAL_SHIFT) - -/* - * WDIL (RW) - * - * Watchdog Interrupt Line - */ -#define MCAN_ILS_WDIL_MASK (0x4000000UL) -#define MCAN_ILS_WDIL_SHIFT (26U) -#define MCAN_ILS_WDIL_SET(x) (((uint32_t)(x) << MCAN_ILS_WDIL_SHIFT) & MCAN_ILS_WDIL_MASK) -#define MCAN_ILS_WDIL_GET(x) (((uint32_t)(x) & MCAN_ILS_WDIL_MASK) >> MCAN_ILS_WDIL_SHIFT) - -/* - * BOL (RW) - * - * Bus_Off Status Interrupt Line - */ -#define MCAN_ILS_BOL_MASK (0x2000000UL) -#define MCAN_ILS_BOL_SHIFT (25U) -#define MCAN_ILS_BOL_SET(x) (((uint32_t)(x) << MCAN_ILS_BOL_SHIFT) & MCAN_ILS_BOL_MASK) -#define MCAN_ILS_BOL_GET(x) (((uint32_t)(x) & MCAN_ILS_BOL_MASK) >> MCAN_ILS_BOL_SHIFT) - -/* - * EWL (RW) - * - * Warning Status Interrupt Line - */ -#define MCAN_ILS_EWL_MASK (0x1000000UL) -#define MCAN_ILS_EWL_SHIFT (24U) -#define MCAN_ILS_EWL_SET(x) (((uint32_t)(x) << MCAN_ILS_EWL_SHIFT) & MCAN_ILS_EWL_MASK) -#define MCAN_ILS_EWL_GET(x) (((uint32_t)(x) & MCAN_ILS_EWL_MASK) >> MCAN_ILS_EWL_SHIFT) - -/* - * EPL (RW) - * - * Error Passive Interrupt Line - */ -#define MCAN_ILS_EPL_MASK (0x800000UL) -#define MCAN_ILS_EPL_SHIFT (23U) -#define MCAN_ILS_EPL_SET(x) (((uint32_t)(x) << MCAN_ILS_EPL_SHIFT) & MCAN_ILS_EPL_MASK) -#define MCAN_ILS_EPL_GET(x) (((uint32_t)(x) & MCAN_ILS_EPL_MASK) >> MCAN_ILS_EPL_SHIFT) - -/* - * ELOL (RW) - * - * Error Logging Overflow Interrupt Line - */ -#define MCAN_ILS_ELOL_MASK (0x400000UL) -#define MCAN_ILS_ELOL_SHIFT (22U) -#define MCAN_ILS_ELOL_SET(x) (((uint32_t)(x) << MCAN_ILS_ELOL_SHIFT) & MCAN_ILS_ELOL_MASK) -#define MCAN_ILS_ELOL_GET(x) (((uint32_t)(x) & MCAN_ILS_ELOL_MASK) >> MCAN_ILS_ELOL_SHIFT) - -/* - * BEUL (RW) - * - * Bit Error Uncorrected Interrupt Line - */ -#define MCAN_ILS_BEUL_MASK (0x200000UL) -#define MCAN_ILS_BEUL_SHIFT (21U) -#define MCAN_ILS_BEUL_SET(x) (((uint32_t)(x) << MCAN_ILS_BEUL_SHIFT) & MCAN_ILS_BEUL_MASK) -#define MCAN_ILS_BEUL_GET(x) (((uint32_t)(x) & MCAN_ILS_BEUL_MASK) >> MCAN_ILS_BEUL_SHIFT) - -/* - * BECL (RW) - * - * Bit Error Corrected Interrupt Line - */ -#define MCAN_ILS_BECL_MASK (0x100000UL) -#define MCAN_ILS_BECL_SHIFT (20U) -#define MCAN_ILS_BECL_SET(x) (((uint32_t)(x) << MCAN_ILS_BECL_SHIFT) & MCAN_ILS_BECL_MASK) -#define MCAN_ILS_BECL_GET(x) (((uint32_t)(x) & MCAN_ILS_BECL_MASK) >> MCAN_ILS_BECL_SHIFT) - -/* - * DRXL (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Line - */ -#define MCAN_ILS_DRXL_MASK (0x80000UL) -#define MCAN_ILS_DRXL_SHIFT (19U) -#define MCAN_ILS_DRXL_SET(x) (((uint32_t)(x) << MCAN_ILS_DRXL_SHIFT) & MCAN_ILS_DRXL_MASK) -#define MCAN_ILS_DRXL_GET(x) (((uint32_t)(x) & MCAN_ILS_DRXL_MASK) >> MCAN_ILS_DRXL_SHIFT) - -/* - * TOOL (RW) - * - * Timeout Occurred Interrupt Line - */ -#define MCAN_ILS_TOOL_MASK (0x40000UL) -#define MCAN_ILS_TOOL_SHIFT (18U) -#define MCAN_ILS_TOOL_SET(x) (((uint32_t)(x) << MCAN_ILS_TOOL_SHIFT) & MCAN_ILS_TOOL_MASK) -#define MCAN_ILS_TOOL_GET(x) (((uint32_t)(x) & MCAN_ILS_TOOL_MASK) >> MCAN_ILS_TOOL_SHIFT) - -/* - * MRAFL (RW) - * - * Message RAM Access Failure Interrupt Line - */ -#define MCAN_ILS_MRAFL_MASK (0x20000UL) -#define MCAN_ILS_MRAFL_SHIFT (17U) -#define MCAN_ILS_MRAFL_SET(x) (((uint32_t)(x) << MCAN_ILS_MRAFL_SHIFT) & MCAN_ILS_MRAFL_MASK) -#define MCAN_ILS_MRAFL_GET(x) (((uint32_t)(x) & MCAN_ILS_MRAFL_MASK) >> MCAN_ILS_MRAFL_SHIFT) - -/* - * TSWL (RW) - * - * Timestamp Wraparound Interrupt Line - */ -#define MCAN_ILS_TSWL_MASK (0x10000UL) -#define MCAN_ILS_TSWL_SHIFT (16U) -#define MCAN_ILS_TSWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TSWL_SHIFT) & MCAN_ILS_TSWL_MASK) -#define MCAN_ILS_TSWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TSWL_MASK) >> MCAN_ILS_TSWL_SHIFT) - -/* - * TEFLL (RW) - * - * Tx Event FIFO Event Lost Interrupt Line - */ -#define MCAN_ILS_TEFLL_MASK (0x8000U) -#define MCAN_ILS_TEFLL_SHIFT (15U) -#define MCAN_ILS_TEFLL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFLL_SHIFT) & MCAN_ILS_TEFLL_MASK) -#define MCAN_ILS_TEFLL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFLL_MASK) >> MCAN_ILS_TEFLL_SHIFT) - -/* - * TEFFL (RW) - * - * Tx Event FIFO Full Interrupt Line - */ -#define MCAN_ILS_TEFFL_MASK (0x4000U) -#define MCAN_ILS_TEFFL_SHIFT (14U) -#define MCAN_ILS_TEFFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFFL_SHIFT) & MCAN_ILS_TEFFL_MASK) -#define MCAN_ILS_TEFFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFFL_MASK) >> MCAN_ILS_TEFFL_SHIFT) - -/* - * TEFWL (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Line - */ -#define MCAN_ILS_TEFWL_MASK (0x2000U) -#define MCAN_ILS_TEFWL_SHIFT (13U) -#define MCAN_ILS_TEFWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFWL_SHIFT) & MCAN_ILS_TEFWL_MASK) -#define MCAN_ILS_TEFWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFWL_MASK) >> MCAN_ILS_TEFWL_SHIFT) - -/* - * TEFNL (RW) - * - * Tx Event FIFO New Entry Interrupt Line - */ -#define MCAN_ILS_TEFNL_MASK (0x1000U) -#define MCAN_ILS_TEFNL_SHIFT (12U) -#define MCAN_ILS_TEFNL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFNL_SHIFT) & MCAN_ILS_TEFNL_MASK) -#define MCAN_ILS_TEFNL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFNL_MASK) >> MCAN_ILS_TEFNL_SHIFT) - -/* - * TFEL (RW) - * - * Tx FIFO Empty Interrupt Line - */ -#define MCAN_ILS_TFEL_MASK (0x800U) -#define MCAN_ILS_TFEL_SHIFT (11U) -#define MCAN_ILS_TFEL_SET(x) (((uint32_t)(x) << MCAN_ILS_TFEL_SHIFT) & MCAN_ILS_TFEL_MASK) -#define MCAN_ILS_TFEL_GET(x) (((uint32_t)(x) & MCAN_ILS_TFEL_MASK) >> MCAN_ILS_TFEL_SHIFT) - -/* - * TCFL (RW) - * - * Transmission Cancellation Finished Interrupt Line - */ -#define MCAN_ILS_TCFL_MASK (0x400U) -#define MCAN_ILS_TCFL_SHIFT (10U) -#define MCAN_ILS_TCFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCFL_SHIFT) & MCAN_ILS_TCFL_MASK) -#define MCAN_ILS_TCFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCFL_MASK) >> MCAN_ILS_TCFL_SHIFT) - -/* - * TCL (RW) - * - * Transmission Completed Interrupt Line - */ -#define MCAN_ILS_TCL_MASK (0x200U) -#define MCAN_ILS_TCL_SHIFT (9U) -#define MCAN_ILS_TCL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCL_SHIFT) & MCAN_ILS_TCL_MASK) -#define MCAN_ILS_TCL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCL_MASK) >> MCAN_ILS_TCL_SHIFT) - -/* - * HPML (RW) - * - * High Priority Message Interrupt Line - */ -#define MCAN_ILS_HPML_MASK (0x100U) -#define MCAN_ILS_HPML_SHIFT (8U) -#define MCAN_ILS_HPML_SET(x) (((uint32_t)(x) << MCAN_ILS_HPML_SHIFT) & MCAN_ILS_HPML_MASK) -#define MCAN_ILS_HPML_GET(x) (((uint32_t)(x) & MCAN_ILS_HPML_MASK) >> MCAN_ILS_HPML_SHIFT) - -/* - * RF1LL (RW) - * - * Rx FIFO 1 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF1LL_MASK (0x80U) -#define MCAN_ILS_RF1LL_SHIFT (7U) -#define MCAN_ILS_RF1LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1LL_SHIFT) & MCAN_ILS_RF1LL_MASK) -#define MCAN_ILS_RF1LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1LL_MASK) >> MCAN_ILS_RF1LL_SHIFT) - -/* - * RF1FL (RW) - * - * Rx FIFO 1 Full Interrupt Line - */ -#define MCAN_ILS_RF1FL_MASK (0x40U) -#define MCAN_ILS_RF1FL_SHIFT (6U) -#define MCAN_ILS_RF1FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1FL_SHIFT) & MCAN_ILS_RF1FL_MASK) -#define MCAN_ILS_RF1FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1FL_MASK) >> MCAN_ILS_RF1FL_SHIFT) - -/* - * RF1WL (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF1WL_MASK (0x20U) -#define MCAN_ILS_RF1WL_SHIFT (5U) -#define MCAN_ILS_RF1WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1WL_SHIFT) & MCAN_ILS_RF1WL_MASK) -#define MCAN_ILS_RF1WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1WL_MASK) >> MCAN_ILS_RF1WL_SHIFT) - -/* - * RF1NL (RW) - * - * Rx FIFO 1 New Message Interrupt Line - */ -#define MCAN_ILS_RF1NL_MASK (0x10U) -#define MCAN_ILS_RF1NL_SHIFT (4U) -#define MCAN_ILS_RF1NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1NL_SHIFT) & MCAN_ILS_RF1NL_MASK) -#define MCAN_ILS_RF1NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1NL_MASK) >> MCAN_ILS_RF1NL_SHIFT) - -/* - * RF0LL (RW) - * - * Rx FIFO 0 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF0LL_MASK (0x8U) -#define MCAN_ILS_RF0LL_SHIFT (3U) -#define MCAN_ILS_RF0LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0LL_SHIFT) & MCAN_ILS_RF0LL_MASK) -#define MCAN_ILS_RF0LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0LL_MASK) >> MCAN_ILS_RF0LL_SHIFT) - -/* - * RF0FL (RW) - * - * Rx FIFO 0 Full Interrupt Line - */ -#define MCAN_ILS_RF0FL_MASK (0x4U) -#define MCAN_ILS_RF0FL_SHIFT (2U) -#define MCAN_ILS_RF0FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0FL_SHIFT) & MCAN_ILS_RF0FL_MASK) -#define MCAN_ILS_RF0FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0FL_MASK) >> MCAN_ILS_RF0FL_SHIFT) - -/* - * RF0WL (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF0WL_MASK (0x2U) -#define MCAN_ILS_RF0WL_SHIFT (1U) -#define MCAN_ILS_RF0WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0WL_SHIFT) & MCAN_ILS_RF0WL_MASK) -#define MCAN_ILS_RF0WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0WL_MASK) >> MCAN_ILS_RF0WL_SHIFT) - -/* - * RF0NL (RW) - * - * Rx FIFO 0 New Message Interrupt Line - */ -#define MCAN_ILS_RF0NL_MASK (0x1U) -#define MCAN_ILS_RF0NL_SHIFT (0U) -#define MCAN_ILS_RF0NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0NL_SHIFT) & MCAN_ILS_RF0NL_MASK) -#define MCAN_ILS_RF0NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0NL_MASK) >> MCAN_ILS_RF0NL_SHIFT) - -/* Bitfield definition for register: ILE */ -/* - * EINT1 (RW) - * - * Enable Interrupt Line 1 - * 0= Interrupt line m_can_int1 disabled - * 1= Interrupt line m_can_int1 enabled - */ -#define MCAN_ILE_EINT1_MASK (0x2U) -#define MCAN_ILE_EINT1_SHIFT (1U) -#define MCAN_ILE_EINT1_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT1_SHIFT) & MCAN_ILE_EINT1_MASK) -#define MCAN_ILE_EINT1_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT1_MASK) >> MCAN_ILE_EINT1_SHIFT) - -/* - * EINT0 (RW) - * - * Enable Interrupt Line 0 - * 0= Interrupt line m_can_int0 disabled - * 1= Interrupt line m_can_int0 enabled - */ -#define MCAN_ILE_EINT0_MASK (0x1U) -#define MCAN_ILE_EINT0_SHIFT (0U) -#define MCAN_ILE_EINT0_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT0_SHIFT) & MCAN_ILE_EINT0_MASK) -#define MCAN_ILE_EINT0_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT0_MASK) >> MCAN_ILE_EINT0_SHIFT) - -/* Bitfield definition for register: GFC */ -/* - * ANFS (RW) - * - * Accept Non-matching Frames Standard - * Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFS_MASK (0x30U) -#define MCAN_GFC_ANFS_SHIFT (4U) -#define MCAN_GFC_ANFS_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFS_SHIFT) & MCAN_GFC_ANFS_MASK) -#define MCAN_GFC_ANFS_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFS_MASK) >> MCAN_GFC_ANFS_SHIFT) - -/* - * ANFE (RW) - * - * Accept Non-matching Frames Extended - * Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFE_MASK (0xCU) -#define MCAN_GFC_ANFE_SHIFT (2U) -#define MCAN_GFC_ANFE_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFE_SHIFT) & MCAN_GFC_ANFE_MASK) -#define MCAN_GFC_ANFE_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFE_MASK) >> MCAN_GFC_ANFE_SHIFT) - -/* - * RRFS (RW) - * - * Reject Remote Frames Standard - * 0= Filter remote frames with 11-bit standard IDs - * 1= Reject all remote frames with 11-bit standard IDs - */ -#define MCAN_GFC_RRFS_MASK (0x2U) -#define MCAN_GFC_RRFS_SHIFT (1U) -#define MCAN_GFC_RRFS_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFS_SHIFT) & MCAN_GFC_RRFS_MASK) -#define MCAN_GFC_RRFS_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFS_MASK) >> MCAN_GFC_RRFS_SHIFT) - -/* - * RRFE (RW) - * - * Reject Remote Frames Extended - * 0= Filter remote frames with 29-bit extended IDs - * 1= Reject all remote frames with 29-bit extended IDs - */ -#define MCAN_GFC_RRFE_MASK (0x1U) -#define MCAN_GFC_RRFE_SHIFT (0U) -#define MCAN_GFC_RRFE_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFE_SHIFT) & MCAN_GFC_RRFE_MASK) -#define MCAN_GFC_RRFE_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFE_MASK) >> MCAN_GFC_RRFE_SHIFT) - -/* Bitfield definition for register: SIDFC */ -/* - * LSS (RW) - * - * List Size Standard - * 0= No standard Message ID filter - * 1-128= Number of standard Message ID filter elements - * >128= Values greater than 128 are interpreted as 128 - */ -#define MCAN_SIDFC_LSS_MASK (0xFF0000UL) -#define MCAN_SIDFC_LSS_SHIFT (16U) -#define MCAN_SIDFC_LSS_SET(x) (((uint32_t)(x) << MCAN_SIDFC_LSS_SHIFT) & MCAN_SIDFC_LSS_MASK) -#define MCAN_SIDFC_LSS_GET(x) (((uint32_t)(x) & MCAN_SIDFC_LSS_MASK) >> MCAN_SIDFC_LSS_SHIFT) - -/* - * FLSSA (RW) - * - * Filter List Standard Start Address - * Start address of standard Message ID filter list (32-bit word address) - */ -#define MCAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define MCAN_SIDFC_FLSSA_SHIFT (2U) -#define MCAN_SIDFC_FLSSA_SET(x) (((uint32_t)(x) << MCAN_SIDFC_FLSSA_SHIFT) & MCAN_SIDFC_FLSSA_MASK) -#define MCAN_SIDFC_FLSSA_GET(x) (((uint32_t)(x) & MCAN_SIDFC_FLSSA_MASK) >> MCAN_SIDFC_FLSSA_SHIFT) - -/* Bitfield definition for register: XIDFC */ -/* - * LSE (RW) - * - * List Size Extended - * 0= No extended Message ID filter - * 1-64= Number of extended Message ID filter elements - * >64= Values greater than 64 are interpreted as 64 - */ -#define MCAN_XIDFC_LSE_MASK (0x7F0000UL) -#define MCAN_XIDFC_LSE_SHIFT (16U) -#define MCAN_XIDFC_LSE_SET(x) (((uint32_t)(x) << MCAN_XIDFC_LSE_SHIFT) & MCAN_XIDFC_LSE_MASK) -#define MCAN_XIDFC_LSE_GET(x) (((uint32_t)(x) & MCAN_XIDFC_LSE_MASK) >> MCAN_XIDFC_LSE_SHIFT) - -/* - * FLESA (RW) - * - * Filter List Extended Start Address - * Start address of extended Message ID filter list (32-bit word address). - */ -#define MCAN_XIDFC_FLESA_MASK (0xFFFCU) -#define MCAN_XIDFC_FLESA_SHIFT (2U) -#define MCAN_XIDFC_FLESA_SET(x) (((uint32_t)(x) << MCAN_XIDFC_FLESA_SHIFT) & MCAN_XIDFC_FLESA_MASK) -#define MCAN_XIDFC_FLESA_GET(x) (((uint32_t)(x) & MCAN_XIDFC_FLESA_MASK) >> MCAN_XIDFC_FLESA_SHIFT) - -/* Bitfield definition for register: XIDAM */ -/* - * EIDM (RW) - * - * Extended ID Mask - * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - * Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - */ -#define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) -#define MCAN_XIDAM_EIDM_SHIFT (0U) -#define MCAN_XIDAM_EIDM_SET(x) (((uint32_t)(x) << MCAN_XIDAM_EIDM_SHIFT) & MCAN_XIDAM_EIDM_MASK) -#define MCAN_XIDAM_EIDM_GET(x) (((uint32_t)(x) & MCAN_XIDAM_EIDM_MASK) >> MCAN_XIDAM_EIDM_SHIFT) - -/* Bitfield definition for register: HPMS */ -/* - * FLST (R) - * - * Filter List - * Indicates the filter list of the matching filter element. - * 0= Standard Filter List - * 1= Extended Filter List - */ -#define MCAN_HPMS_FLST_MASK (0x8000U) -#define MCAN_HPMS_FLST_SHIFT (15U) -#define MCAN_HPMS_FLST_GET(x) (((uint32_t)(x) & MCAN_HPMS_FLST_MASK) >> MCAN_HPMS_FLST_SHIFT) - -/* - * FIDX (R) - * - * Filter Index - * Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - */ -#define MCAN_HPMS_FIDX_MASK (0x7F00U) -#define MCAN_HPMS_FIDX_SHIFT (8U) -#define MCAN_HPMS_FIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_FIDX_MASK) >> MCAN_HPMS_FIDX_SHIFT) - -/* - * MSI (R) - * - * Message Storage Indicator - * 00= No FIFO selected - * 01= FIFO message lost - * 10= Message stored in FIFO 0 - * 11= Message stored in FIFO 1 - */ -#define MCAN_HPMS_MSI_MASK (0xC0U) -#define MCAN_HPMS_MSI_SHIFT (6U) -#define MCAN_HPMS_MSI_GET(x) (((uint32_t)(x) & MCAN_HPMS_MSI_MASK) >> MCAN_HPMS_MSI_SHIFT) - -/* - * BIDX (R) - * - * Buffer Index - * Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - */ -#define MCAN_HPMS_BIDX_MASK (0x3FU) -#define MCAN_HPMS_BIDX_SHIFT (0U) -#define MCAN_HPMS_BIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_BIDX_MASK) >> MCAN_HPMS_BIDX_SHIFT) - -/* Bitfield definition for register: NDAT1 */ -/* - * ND1 (RW) - * - * New Data[31:0] - * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT1_ND1_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT1_ND1_SHIFT (0U) -#define MCAN_NDAT1_ND1_SET(x) (((uint32_t)(x) << MCAN_NDAT1_ND1_SHIFT) & MCAN_NDAT1_ND1_MASK) -#define MCAN_NDAT1_ND1_GET(x) (((uint32_t)(x) & MCAN_NDAT1_ND1_MASK) >> MCAN_NDAT1_ND1_SHIFT) - -/* Bitfield definition for register: NDAT2 */ -/* - * ND2 (RW) - * - * New Data[63:32] - * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT2_ND2_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT2_ND2_SHIFT (0U) -#define MCAN_NDAT2_ND2_SET(x) (((uint32_t)(x) << MCAN_NDAT2_ND2_SHIFT) & MCAN_NDAT2_ND2_MASK) -#define MCAN_NDAT2_ND2_GET(x) (((uint32_t)(x) & MCAN_NDAT2_ND2_MASK) >> MCAN_NDAT2_ND2_SHIFT) - -/* Bitfield definition for register: RXF0C */ -/* - * F0OM (RW) - * - * FIFO 0 Operation Mode - * FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 0 blocking mode - * 1= FIFO 0 overwrite mode - */ -#define MCAN_RXF0C_F0OM_MASK (0x80000000UL) -#define MCAN_RXF0C_F0OM_SHIFT (31U) -#define MCAN_RXF0C_F0OM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0OM_SHIFT) & MCAN_RXF0C_F0OM_MASK) -#define MCAN_RXF0C_F0OM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0OM_MASK) >> MCAN_RXF0C_F0OM_SHIFT) - -/* - * F0WM (RW) - * - * Rx FIFO 0 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF0C_F0WM_MASK (0x7F000000UL) -#define MCAN_RXF0C_F0WM_SHIFT (24U) -#define MCAN_RXF0C_F0WM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0WM_SHIFT) & MCAN_RXF0C_F0WM_MASK) -#define MCAN_RXF0C_F0WM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0WM_MASK) >> MCAN_RXF0C_F0WM_SHIFT) - -/* - * F0S (RW) - * - * Rx FIFO 0 Size - * 0= No Rx FIFO 0 - * 1-64= Number of Rx FIFO 0 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 0 elements are indexed from 0 to F0S-1 - */ -#define MCAN_RXF0C_F0S_MASK (0x7F0000UL) -#define MCAN_RXF0C_F0S_SHIFT (16U) -#define MCAN_RXF0C_F0S_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0S_SHIFT) & MCAN_RXF0C_F0S_MASK) -#define MCAN_RXF0C_F0S_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0S_MASK) >> MCAN_RXF0C_F0S_SHIFT) - -/* - * F0SA (RW) - * - * Rx FIFO 0 Start Address - * Start address of Rx FIFO 0 in Message RAM (32-bit word address) - */ -#define MCAN_RXF0C_F0SA_MASK (0xFFFCU) -#define MCAN_RXF0C_F0SA_SHIFT (2U) -#define MCAN_RXF0C_F0SA_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0SA_SHIFT) & MCAN_RXF0C_F0SA_MASK) -#define MCAN_RXF0C_F0SA_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0SA_MASK) >> MCAN_RXF0C_F0SA_SHIFT) - -/* Bitfield definition for register: RXF0S */ -/* - * RF0L (R) - * - * Rx FIFO 0 Message Lost - * This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - * Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF0S_RF0L_MASK (0x2000000UL) -#define MCAN_RXF0S_RF0L_SHIFT (25U) -#define MCAN_RXF0S_RF0L_GET(x) (((uint32_t)(x) & MCAN_RXF0S_RF0L_MASK) >> MCAN_RXF0S_RF0L_SHIFT) - -/* - * F0F (R) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_RXF0S_F0F_MASK (0x1000000UL) -#define MCAN_RXF0S_F0F_SHIFT (24U) -#define MCAN_RXF0S_F0F_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0F_MASK) >> MCAN_RXF0S_F0F_SHIFT) - -/* - * F0PI (R) - * - * Rx FIFO 0 Put Index - * Rx FIFO 0 write index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0PI_MASK (0x3F0000UL) -#define MCAN_RXF0S_F0PI_SHIFT (16U) -#define MCAN_RXF0S_F0PI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0PI_MASK) >> MCAN_RXF0S_F0PI_SHIFT) - -/* - * F0GI (R) - * - * Rx FIFO 0 Get Index - * Rx FIFO 0 read index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0GI_MASK (0x3F00U) -#define MCAN_RXF0S_F0GI_SHIFT (8U) -#define MCAN_RXF0S_F0GI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT) - -/* - * F0FL (R) - * - * Rx FIFO 0 Fill Level - * Number of elements stored in Rx FIFO 0, range 0 to 64. - */ -#define MCAN_RXF0S_F0FL_MASK (0x7FU) -#define MCAN_RXF0S_F0FL_SHIFT (0U) -#define MCAN_RXF0S_F0FL_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT) - -/* Bitfield definition for register: RXF0A */ -/* - * F0AI (RW) - * - * Rx FIFO 0 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. - * This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - */ -#define MCAN_RXF0A_F0AI_MASK (0x3FU) -#define MCAN_RXF0A_F0AI_SHIFT (0U) -#define MCAN_RXF0A_F0AI_SET(x) (((uint32_t)(x) << MCAN_RXF0A_F0AI_SHIFT) & MCAN_RXF0A_F0AI_MASK) -#define MCAN_RXF0A_F0AI_GET(x) (((uint32_t)(x) & MCAN_RXF0A_F0AI_MASK) >> MCAN_RXF0A_F0AI_SHIFT) - -/* Bitfield definition for register: RXBC */ -/* - * RBSA (RW) - * - * Rx Buffer Start Address - * Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - */ -#define MCAN_RXBC_RBSA_MASK (0xFFFCU) -#define MCAN_RXBC_RBSA_SHIFT (2U) -#define MCAN_RXBC_RBSA_SET(x) (((uint32_t)(x) << MCAN_RXBC_RBSA_SHIFT) & MCAN_RXBC_RBSA_MASK) -#define MCAN_RXBC_RBSA_GET(x) (((uint32_t)(x) & MCAN_RXBC_RBSA_MASK) >> MCAN_RXBC_RBSA_SHIFT) - -/* Bitfield definition for register: RXF1C */ -/* - * F1OM (RW) - * - * FIFO 1 Operation Mode - * FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 1 blocking mode - * 1= FIFO 1 overwrite mode - */ -#define MCAN_RXF1C_F1OM_MASK (0x80000000UL) -#define MCAN_RXF1C_F1OM_SHIFT (31U) -#define MCAN_RXF1C_F1OM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1OM_SHIFT) & MCAN_RXF1C_F1OM_MASK) -#define MCAN_RXF1C_F1OM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1OM_MASK) >> MCAN_RXF1C_F1OM_SHIFT) - -/* - * F1WM (RW) - * - * Rx FIFO 1 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF1C_F1WM_MASK (0x7F000000UL) -#define MCAN_RXF1C_F1WM_SHIFT (24U) -#define MCAN_RXF1C_F1WM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1WM_SHIFT) & MCAN_RXF1C_F1WM_MASK) -#define MCAN_RXF1C_F1WM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1WM_MASK) >> MCAN_RXF1C_F1WM_SHIFT) - -/* - * F1S (RW) - * - * Rx FIFO 1 Size - * 0= No Rx FIFO 1 - * 1-64= Number of Rx FIFO 1 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - */ -#define MCAN_RXF1C_F1S_MASK (0x7F0000UL) -#define MCAN_RXF1C_F1S_SHIFT (16U) -#define MCAN_RXF1C_F1S_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1S_SHIFT) & MCAN_RXF1C_F1S_MASK) -#define MCAN_RXF1C_F1S_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1S_MASK) >> MCAN_RXF1C_F1S_SHIFT) - -/* - * F1SA (RW) - * - * Rx FIFO 1 Start Address - * Start address of Rx FIFO 1 in Message RAM (32-bit word address) - */ -#define MCAN_RXF1C_F1SA_MASK (0xFFFCU) -#define MCAN_RXF1C_F1SA_SHIFT (2U) -#define MCAN_RXF1C_F1SA_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1SA_SHIFT) & MCAN_RXF1C_F1SA_MASK) -#define MCAN_RXF1C_F1SA_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1SA_MASK) >> MCAN_RXF1C_F1SA_SHIFT) - -/* Bitfield definition for register: RXF1S */ -/* - * DMS (R) - * - * Debug Message Status - * 00= Idle state, wait for reception of debug messages, DMA request is cleared - * 01= Debug message A received - * 10= Debug messages A, B received - * 11= Debug messages A, B, C received, DMA request is set - */ -#define MCAN_RXF1S_DMS_MASK (0xC0000000UL) -#define MCAN_RXF1S_DMS_SHIFT (30U) -#define MCAN_RXF1S_DMS_GET(x) (((uint32_t)(x) & MCAN_RXF1S_DMS_MASK) >> MCAN_RXF1S_DMS_SHIFT) - -/* - * RF1L (R) - * - * Rx FIFO 1 Message Lost - * This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - * Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF1S_RF1L_MASK (0x2000000UL) -#define MCAN_RXF1S_RF1L_SHIFT (25U) -#define MCAN_RXF1S_RF1L_GET(x) (((uint32_t)(x) & MCAN_RXF1S_RF1L_MASK) >> MCAN_RXF1S_RF1L_SHIFT) - -/* - * F1F (R) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_RXF1S_F1F_MASK (0x1000000UL) -#define MCAN_RXF1S_F1F_SHIFT (24U) -#define MCAN_RXF1S_F1F_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1F_MASK) >> MCAN_RXF1S_F1F_SHIFT) - -/* - * F1PI (R) - * - * Rx FIFO 1 Put Index - * Rx FIFO 1 write index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1PI_MASK (0x3F0000UL) -#define MCAN_RXF1S_F1PI_SHIFT (16U) -#define MCAN_RXF1S_F1PI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1PI_MASK) >> MCAN_RXF1S_F1PI_SHIFT) - -/* - * F1GI (R) - * - * Rx FIFO 1 Get Index - * Rx FIFO 1 read index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1GI_MASK (0x3F00U) -#define MCAN_RXF1S_F1GI_SHIFT (8U) -#define MCAN_RXF1S_F1GI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT) - -/* - * F1FL (R) - * - * Rx FIFO 1 Fill Level - * Number of elements stored in Rx FIFO 1, range 0 to 64. - */ -#define MCAN_RXF1S_F1FL_MASK (0x7FU) -#define MCAN_RXF1S_F1FL_SHIFT (0U) -#define MCAN_RXF1S_F1FL_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT) - -/* Bitfield definition for register: RXF1A */ -/* - * F1AI (RW) - * - * Rx FIFO 1 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. - * This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - */ -#define MCAN_RXF1A_F1AI_MASK (0x3FU) -#define MCAN_RXF1A_F1AI_SHIFT (0U) -#define MCAN_RXF1A_F1AI_SET(x) (((uint32_t)(x) << MCAN_RXF1A_F1AI_SHIFT) & MCAN_RXF1A_F1AI_MASK) -#define MCAN_RXF1A_F1AI_GET(x) (((uint32_t)(x) & MCAN_RXF1A_F1AI_MASK) >> MCAN_RXF1A_F1AI_SHIFT) - -/* Bitfield definition for register: RXESC */ -/* - * RBDS (RW) - * - * Rx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_RBDS_MASK (0x700U) -#define MCAN_RXESC_RBDS_SHIFT (8U) -#define MCAN_RXESC_RBDS_SET(x) (((uint32_t)(x) << MCAN_RXESC_RBDS_SHIFT) & MCAN_RXESC_RBDS_MASK) -#define MCAN_RXESC_RBDS_GET(x) (((uint32_t)(x) & MCAN_RXESC_RBDS_MASK) >> MCAN_RXESC_RBDS_SHIFT) - -/* - * F1DS (RW) - * - * Rx FIFO 1 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_F1DS_MASK (0x70U) -#define MCAN_RXESC_F1DS_SHIFT (4U) -#define MCAN_RXESC_F1DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F1DS_SHIFT) & MCAN_RXESC_F1DS_MASK) -#define MCAN_RXESC_F1DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F1DS_MASK) >> MCAN_RXESC_F1DS_SHIFT) - -/* - * F0DS (RW) - * - * Rx FIFO 0 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, - * only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - */ -#define MCAN_RXESC_F0DS_MASK (0x7U) -#define MCAN_RXESC_F0DS_SHIFT (0U) -#define MCAN_RXESC_F0DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F0DS_SHIFT) & MCAN_RXESC_F0DS_MASK) -#define MCAN_RXESC_F0DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F0DS_MASK) >> MCAN_RXESC_F0DS_SHIFT) - -/* Bitfield definition for register: TXBC */ -/* - * TFQM (RW) - * - * Tx FIFO/Queue Mode - * 0= Tx FIFO operation - * 1= Tx Queue operation - */ -#define MCAN_TXBC_TFQM_MASK (0x40000000UL) -#define MCAN_TXBC_TFQM_SHIFT (30U) -#define MCAN_TXBC_TFQM_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQM_SHIFT) & MCAN_TXBC_TFQM_MASK) -#define MCAN_TXBC_TFQM_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQM_MASK) >> MCAN_TXBC_TFQM_SHIFT) - -/* - * TFQS (RW) - * - * Transmit FIFO/Queue Size - * 0= No Tx FIFO/Queue - * 1-32= Number of Tx Buffers used for Tx FIFO/Queue - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_TFQS_MASK (0x3F000000UL) -#define MCAN_TXBC_TFQS_SHIFT (24U) -#define MCAN_TXBC_TFQS_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQS_SHIFT) & MCAN_TXBC_TFQS_MASK) -#define MCAN_TXBC_TFQS_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQS_MASK) >> MCAN_TXBC_TFQS_SHIFT) - -/* - * NDTB (RW) - * - * Number of Dedicated Transmit Buffers - * 0= No Dedicated Tx Buffers - * 1-32= Number of Dedicated Tx Buffers - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_NDTB_MASK (0x3F0000UL) -#define MCAN_TXBC_NDTB_SHIFT (16U) -#define MCAN_TXBC_NDTB_SET(x) (((uint32_t)(x) << MCAN_TXBC_NDTB_SHIFT) & MCAN_TXBC_NDTB_MASK) -#define MCAN_TXBC_NDTB_GET(x) (((uint32_t)(x) & MCAN_TXBC_NDTB_MASK) >> MCAN_TXBC_NDTB_SHIFT) - -/* - * TBSA (RW) - * - * Tx Buffers Start Address - * Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). - * Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - */ -#define MCAN_TXBC_TBSA_MASK (0xFFFCU) -#define MCAN_TXBC_TBSA_SHIFT (2U) -#define MCAN_TXBC_TBSA_SET(x) (((uint32_t)(x) << MCAN_TXBC_TBSA_SHIFT) & MCAN_TXBC_TBSA_MASK) -#define MCAN_TXBC_TBSA_GET(x) (((uint32_t)(x) & MCAN_TXBC_TBSA_MASK) >> MCAN_TXBC_TBSA_SHIFT) - -/* Bitfield definition for register: TXFQS */ -/* - * TFQF (R) - * - * Tx FIFO/Queue Full - * 0= Tx FIFO/Queue not full - * 1= Tx FIFO/Queue full - */ -#define MCAN_TXFQS_TFQF_MASK (0x200000UL) -#define MCAN_TXFQS_TFQF_SHIFT (21U) -#define MCAN_TXFQS_TFQF_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQF_MASK) >> MCAN_TXFQS_TFQF_SHIFT) - -/* - * TFQPI (R) - * - * Tx FIFO/Queue Put Index - * Tx FIFO/Queue write index pointer, range 0 to 31. - */ -#define MCAN_TXFQS_TFQPI_MASK (0x1F0000UL) -#define MCAN_TXFQS_TFQPI_SHIFT (16U) -#define MCAN_TXFQS_TFQPI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQPI_MASK) >> MCAN_TXFQS_TFQPI_SHIFT) - -/* - * TFGI (R) - * - * Tx FIFO Get Index - * Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured - * (TXBC.TFQM = ‘1’). - */ -#define MCAN_TXFQS_TFGI_MASK (0x1F00U) -#define MCAN_TXFQS_TFGI_SHIFT (8U) -#define MCAN_TXFQS_TFGI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFGI_MASK) >> MCAN_TXFQS_TFGI_SHIFT) - -/* - * TFFL (R) - * - * Tx FIFO Free Level - * Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) - * Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with - * the first dedicated Tx Buffers. - * Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - */ -#define MCAN_TXFQS_TFFL_MASK (0x3FU) -#define MCAN_TXFQS_TFFL_SHIFT (0U) -#define MCAN_TXFQS_TFFL_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFFL_MASK) >> MCAN_TXFQS_TFFL_SHIFT) - -/* Bitfield definition for register: TXESC */ -/* - * TBDS (RW) - * - * Tx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - */ -#define MCAN_TXESC_TBDS_MASK (0x7U) -#define MCAN_TXESC_TBDS_SHIFT (0U) -#define MCAN_TXESC_TBDS_SET(x) (((uint32_t)(x) << MCAN_TXESC_TBDS_SHIFT) & MCAN_TXESC_TBDS_MASK) -#define MCAN_TXESC_TBDS_GET(x) (((uint32_t)(x) & MCAN_TXESC_TBDS_MASK) >> MCAN_TXESC_TBDS_SHIFT) - -/* Bitfield definition for register: TXBRP */ -/* - * TRP (R) - * - * Transmission Request Pending - * Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register - * TXBCR. - * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the - * highest priority (Tx Buffer with lowest Message ID). - * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, - * this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. - * After a cancellation has been requested, a finished cancellation is signalled via TXBCF - * ? after successful transmission together with the corresponding TXBTO bit - * ? when the transmission has not yet been started at the point of cancellation - * ? when the transmission has been aborted due to lost arbitration - * ? when an error occurred during frame transmission - * In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. - * 0= No transmission request pending - * 1= Transmission request pending - * Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - */ -#define MCAN_TXBRP_TRP_MASK (0xFFFFFFFFUL) -#define MCAN_TXBRP_TRP_SHIFT (0U) -#define MCAN_TXBRP_TRP_GET(x) (((uint32_t)(x) & MCAN_TXBRP_TRP_MASK) >> MCAN_TXBRP_TRP_SHIFT) - -/* Bitfield definition for register: TXBAR */ -/* - * AR (RW) - * - * Add Request - * Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx - * Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. - * When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. - * 0= No transmission request added - * 1= Transmission requested added - * Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - */ -#define MCAN_TXBAR_AR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBAR_AR_SHIFT (0U) -#define MCAN_TXBAR_AR_SET(x) (((uint32_t)(x) << MCAN_TXBAR_AR_SHIFT) & MCAN_TXBAR_AR_MASK) -#define MCAN_TXBAR_AR_GET(x) (((uint32_t)(x) & MCAN_TXBAR_AR_MASK) >> MCAN_TXBAR_AR_SHIFT) - -/* Bitfield definition for register: TXBCR */ -/* - * CR (RW) - * - * Cancellation Request - * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. - * This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. - * 0= No cancellation pending - * 1= Cancellation pending - */ -#define MCAN_TXBCR_CR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCR_CR_SHIFT (0U) -#define MCAN_TXBCR_CR_SET(x) (((uint32_t)(x) << MCAN_TXBCR_CR_SHIFT) & MCAN_TXBCR_CR_MASK) -#define MCAN_TXBCR_CR_GET(x) (((uint32_t)(x) & MCAN_TXBCR_CR_MASK) >> MCAN_TXBCR_CR_SHIFT) - -/* Bitfield definition for register: TXBTO */ -/* - * TO (R) - * - * Transmission Occurred - * Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmission occurred - * 1= Transmission occurred - */ -#define MCAN_TXBTO_TO_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTO_TO_SHIFT (0U) -#define MCAN_TXBTO_TO_GET(x) (((uint32_t)(x) & MCAN_TXBTO_TO_MASK) >> MCAN_TXBTO_TO_SHIFT) - -/* Bitfield definition for register: TXBCF */ -/* - * CF (R) - * - * Cancellation Finished - * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. - * In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmit buffer cancellation - * 1= Transmit buffer cancellation finished - */ -#define MCAN_TXBCF_CF_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCF_CF_SHIFT (0U) -#define MCAN_TXBCF_CF_GET(x) (((uint32_t)(x) & MCAN_TXBCF_CF_MASK) >> MCAN_TXBCF_CF_SHIFT) - -/* Bitfield definition for register: TXBTIE */ -/* - * TIE (RW) - * - * Transmission Interrupt Enable - * Each Tx Buffer has its own Transmission Interrupt Enable bit. - * 0= Transmission interrupt disabled - * 1= Transmission interrupt enable - */ -#define MCAN_TXBTIE_TIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTIE_TIE_SHIFT (0U) -#define MCAN_TXBTIE_TIE_SET(x) (((uint32_t)(x) << MCAN_TXBTIE_TIE_SHIFT) & MCAN_TXBTIE_TIE_MASK) -#define MCAN_TXBTIE_TIE_GET(x) (((uint32_t)(x) & MCAN_TXBTIE_TIE_MASK) >> MCAN_TXBTIE_TIE_SHIFT) - -/* Bitfield definition for register: TXBCIE */ -/* - * CFIE (RW) - * - * Cancellation Finished Interrupt Enable - * Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. - * 0= Cancellation finished interrupt disabled - * 1= Cancellation finished interrupt enabled - */ -#define MCAN_TXBCIE_CFIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCIE_CFIE_SHIFT (0U) -#define MCAN_TXBCIE_CFIE_SET(x) (((uint32_t)(x) << MCAN_TXBCIE_CFIE_SHIFT) & MCAN_TXBCIE_CFIE_MASK) -#define MCAN_TXBCIE_CFIE_GET(x) (((uint32_t)(x) & MCAN_TXBCIE_CFIE_MASK) >> MCAN_TXBCIE_CFIE_SHIFT) - -/* Bitfield definition for register: TXEFC */ -/* - * EFWM (RW) - * - * Event FIFO Watermark - * 0= Watermark interrupt disabled - * 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) - * >32= Watermark interrupt disabled - */ -#define MCAN_TXEFC_EFWM_MASK (0x3F000000UL) -#define MCAN_TXEFC_EFWM_SHIFT (24U) -#define MCAN_TXEFC_EFWM_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFWM_SHIFT) & MCAN_TXEFC_EFWM_MASK) -#define MCAN_TXEFC_EFWM_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFWM_MASK) >> MCAN_TXEFC_EFWM_SHIFT) - -/* - * EFS (RW) - * - * Event FIFO Size - * 0= Tx Event FIFO disabled - * 1-32= Number of Tx Event FIFO elements - * >32= Values greater than 32 are interpreted as 32 - * The Tx Event FIFO elements are indexed from 0 to EFS - 1 - */ -#define MCAN_TXEFC_EFS_MASK (0x3F0000UL) -#define MCAN_TXEFC_EFS_SHIFT (16U) -#define MCAN_TXEFC_EFS_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFS_SHIFT) & MCAN_TXEFC_EFS_MASK) -#define MCAN_TXEFC_EFS_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFS_MASK) >> MCAN_TXEFC_EFS_SHIFT) - -/* - * EFSA (RW) - * - * Event FIFO Start Address - * Start address of Tx Event FIFO in Message RAM (32-bit word address) - */ -#define MCAN_TXEFC_EFSA_MASK (0xFFFCU) -#define MCAN_TXEFC_EFSA_SHIFT (2U) -#define MCAN_TXEFC_EFSA_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFSA_SHIFT) & MCAN_TXEFC_EFSA_MASK) -#define MCAN_TXEFC_EFSA_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFSA_MASK) >> MCAN_TXEFC_EFSA_SHIFT) - -/* Bitfield definition for register: TXEFS */ -/* - * TEFL (R) - * - * Tx Event FIFO Element Lost - * This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - */ -#define MCAN_TXEFS_TEFL_MASK (0x2000000UL) -#define MCAN_TXEFS_TEFL_SHIFT (25U) -#define MCAN_TXEFS_TEFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_TEFL_MASK) >> MCAN_TXEFS_TEFL_SHIFT) - -/* - * EFF (R) - * - * Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_TXEFS_EFF_MASK (0x1000000UL) -#define MCAN_TXEFS_EFF_SHIFT (24U) -#define MCAN_TXEFS_EFF_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFF_MASK) >> MCAN_TXEFS_EFF_SHIFT) - -/* - * EFPI (R) - * - * Event FIFO Put Index - * Tx Event FIFO write index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFPI_MASK (0x1F0000UL) -#define MCAN_TXEFS_EFPI_SHIFT (16U) -#define MCAN_TXEFS_EFPI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFPI_MASK) >> MCAN_TXEFS_EFPI_SHIFT) - -/* - * EFGI (R) - * - * Event FIFO Get Index - * Tx Event FIFO read index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFGI_MASK (0x1F00U) -#define MCAN_TXEFS_EFGI_SHIFT (8U) -#define MCAN_TXEFS_EFGI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFGI_MASK) >> MCAN_TXEFS_EFGI_SHIFT) - -/* - * EFFL (R) - * - * Event FIFO Fill Level - * Number of elements stored in Tx Event FIFO, range 0 to 32. - */ -#define MCAN_TXEFS_EFFL_MASK (0x3FU) -#define MCAN_TXEFS_EFFL_SHIFT (0U) -#define MCAN_TXEFS_EFFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFFL_MASK) >> MCAN_TXEFS_EFFL_SHIFT) - -/* Bitfield definition for register: TXEFA */ -/* - * EFAI (RW) - * - * Event FIFO Acknowledge Index - * After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get - * Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - */ -#define MCAN_TXEFA_EFAI_MASK (0x1FU) -#define MCAN_TXEFA_EFAI_SHIFT (0U) -#define MCAN_TXEFA_EFAI_SET(x) (((uint32_t)(x) << MCAN_TXEFA_EFAI_SHIFT) & MCAN_TXEFA_EFAI_MASK) -#define MCAN_TXEFA_EFAI_GET(x) (((uint32_t)(x) & MCAN_TXEFA_EFAI_MASK) >> MCAN_TXEFA_EFAI_SHIFT) - -/* Bitfield definition for register array: TS_SEL */ -/* - * TS (R) - * - * Timestamp Word TS - * default can save 16 timestamps with 32bit; - * if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - */ -#define MCAN_TS_SEL_TS_MASK (0xFFFFFFFFUL) -#define MCAN_TS_SEL_TS_SHIFT (0U) -#define MCAN_TS_SEL_TS_GET(x) (((uint32_t)(x) & MCAN_TS_SEL_TS_MASK) >> MCAN_TS_SEL_TS_SHIFT) - -/* Bitfield definition for register: CREL */ -/* - * REL (R) - * - * Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_REL_MASK (0xF0000000UL) -#define MCAN_CREL_REL_SHIFT (28U) -#define MCAN_CREL_REL_GET(x) (((uint32_t)(x) & MCAN_CREL_REL_MASK) >> MCAN_CREL_REL_SHIFT) - -/* - * STEP (R) - * - * Step of Core Release - * One digit, BCD-coded. - */ -#define MCAN_CREL_STEP_MASK (0xF000000UL) -#define MCAN_CREL_STEP_SHIFT (24U) -#define MCAN_CREL_STEP_GET(x) (((uint32_t)(x) & MCAN_CREL_STEP_MASK) >> MCAN_CREL_STEP_SHIFT) - -/* - * SUBSTEP (R) - * - * Sub-step of Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_SUBSTEP_MASK (0xF00000UL) -#define MCAN_CREL_SUBSTEP_SHIFT (20U) -#define MCAN_CREL_SUBSTEP_GET(x) (((uint32_t)(x) & MCAN_CREL_SUBSTEP_MASK) >> MCAN_CREL_SUBSTEP_SHIFT) - -/* - * YEAR (R) - * - * Timestamp Year - * One digit, BCD-coded. This field is set by generic parameter on - * synthesis. - */ -#define MCAN_CREL_YEAR_MASK (0xF0000UL) -#define MCAN_CREL_YEAR_SHIFT (16U) -#define MCAN_CREL_YEAR_GET(x) (((uint32_t)(x) & MCAN_CREL_YEAR_MASK) >> MCAN_CREL_YEAR_SHIFT) - -/* - * MON (R) - * - * Timestamp Month - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_MON_MASK (0xFF00U) -#define MCAN_CREL_MON_SHIFT (8U) -#define MCAN_CREL_MON_GET(x) (((uint32_t)(x) & MCAN_CREL_MON_MASK) >> MCAN_CREL_MON_SHIFT) - -/* - * DAY (R) - * - * Timestamp Day - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_DAY_MASK (0xFFU) -#define MCAN_CREL_DAY_SHIFT (0U) -#define MCAN_CREL_DAY_GET(x) (((uint32_t)(x) & MCAN_CREL_DAY_MASK) >> MCAN_CREL_DAY_SHIFT) - -/* Bitfield definition for register: TSCFG */ -/* - * TBPRE (RW) - * - * Timebase Prescaler - * 0x00 to 0xFF - * The value by which the oscillator frequency is divided for - * generating the timebase counter clock. Valid values for the - * Timebase Prescaler are 0 to 255. The actual interpretation by - * the hardware of this value is such that one more than the value - * programmed here is used. Affects only the TSU internal - * timebase. When the internal timebase is excluded by synthesis, - * TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not - * used. - */ -#define MCAN_TSCFG_TBPRE_MASK (0xFF00U) -#define MCAN_TSCFG_TBPRE_SHIFT (8U) -#define MCAN_TSCFG_TBPRE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBPRE_SHIFT) & MCAN_TSCFG_TBPRE_MASK) -#define MCAN_TSCFG_TBPRE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBPRE_MASK) >> MCAN_TSCFG_TBPRE_SHIFT) - -/* - * EN64 (RW) - * - * set to use 64bit timestamp. - * when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. - * TSP can be used to select different one - */ -#define MCAN_TSCFG_EN64_MASK (0x8U) -#define MCAN_TSCFG_EN64_SHIFT (3U) -#define MCAN_TSCFG_EN64_SET(x) (((uint32_t)(x) << MCAN_TSCFG_EN64_SHIFT) & MCAN_TSCFG_EN64_MASK) -#define MCAN_TSCFG_EN64_GET(x) (((uint32_t)(x) & MCAN_TSCFG_EN64_MASK) >> MCAN_TSCFG_EN64_SHIFT) - -/* - * SCP (RW) - * - * Select Capturing Position - * 0: Capture Timestamp at EOF - * 1: Capture Timestamp at SOF - */ -#define MCAN_TSCFG_SCP_MASK (0x4U) -#define MCAN_TSCFG_SCP_SHIFT (2U) -#define MCAN_TSCFG_SCP_SET(x) (((uint32_t)(x) << MCAN_TSCFG_SCP_SHIFT) & MCAN_TSCFG_SCP_MASK) -#define MCAN_TSCFG_SCP_GET(x) (((uint32_t)(x) & MCAN_TSCFG_SCP_MASK) >> MCAN_TSCFG_SCP_SHIFT) - -/* - * TBCS (RW) - * - * Timebase Counter Select - * When the internal timebase is excluded by synthesis, TBCS is - * fixed to ‘1’. - * 0: Timestamp value captured from internal timebase counter, - * ATB.TB[31:0] is the internal timbase counter - * 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - */ -#define MCAN_TSCFG_TBCS_MASK (0x2U) -#define MCAN_TSCFG_TBCS_SHIFT (1U) -#define MCAN_TSCFG_TBCS_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBCS_SHIFT) & MCAN_TSCFG_TBCS_MASK) -#define MCAN_TSCFG_TBCS_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBCS_MASK) >> MCAN_TSCFG_TBCS_SHIFT) - -/* - * TSUE (RW) - * - * Timestamp Unit Enable - * 0: TSU disabled - * 1: TSU enabled - */ -#define MCAN_TSCFG_TSUE_MASK (0x1U) -#define MCAN_TSCFG_TSUE_SHIFT (0U) -#define MCAN_TSCFG_TSUE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TSUE_SHIFT) & MCAN_TSCFG_TSUE_MASK) -#define MCAN_TSCFG_TSUE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TSUE_MASK) >> MCAN_TSCFG_TSUE_SHIFT) - -/* Bitfield definition for register: TSS1 */ -/* - * TSL (R) - * - * Timestamp Lost - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. - * Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSL_MASK (0xFFFF0000UL) -#define MCAN_TSS1_TSL_SHIFT (16U) -#define MCAN_TSS1_TSL_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSL_MASK) >> MCAN_TSS1_TSL_SHIFT) - -/* - * TSN (R) - * - * Timestamp New - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related - * Timestamp register. Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSN_MASK (0xFFFFU) -#define MCAN_TSS1_TSN_SHIFT (0U) -#define MCAN_TSS1_TSN_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSN_MASK) >> MCAN_TSS1_TSN_SHIFT) - -/* Bitfield definition for register: TSS2 */ -/* - * TSP (R) - * - * Timestamp Pointer - * The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 - * depending on number_ts_g), it is incremented to 0. - * Value also signalled on output m_can_tsp[3:0]. - */ -#define MCAN_TSS2_TSP_MASK (0xFU) -#define MCAN_TSS2_TSP_SHIFT (0U) -#define MCAN_TSS2_TSP_GET(x) (((uint32_t)(x) & MCAN_TSS2_TSP_MASK) >> MCAN_TSS2_TSP_SHIFT) - -/* Bitfield definition for register: ATB */ -/* - * TB (RC) - * - * timebase for timestamp generation 31-0 - */ -#define MCAN_ATB_TB_MASK (0xFFFFFFFFUL) -#define MCAN_ATB_TB_SHIFT (0U) -#define MCAN_ATB_TB_GET(x) (((uint32_t)(x) & MCAN_ATB_TB_MASK) >> MCAN_ATB_TB_SHIFT) - -/* Bitfield definition for register: ATBH */ -/* - * TBH (RC) - * - * timebase for timestamp generation 63-32 - */ -#define MCAN_ATBH_TBH_MASK (0xFFFFFFFFUL) -#define MCAN_ATBH_TBH_SHIFT (0U) -#define MCAN_ATBH_TBH_GET(x) (((uint32_t)(x) & MCAN_ATBH_TBH_MASK) >> MCAN_ATBH_TBH_SHIFT) - -/* Bitfield definition for register: GLB_CTL */ -/* - * M_CAN_STBY (RW) - * - * m_can standby control - */ -#define MCAN_GLB_CTL_M_CAN_STBY_MASK (0x80000000UL) -#define MCAN_GLB_CTL_M_CAN_STBY_SHIFT (31U) -#define MCAN_GLB_CTL_M_CAN_STBY_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_M_CAN_STBY_SHIFT) & MCAN_GLB_CTL_M_CAN_STBY_MASK) -#define MCAN_GLB_CTL_M_CAN_STBY_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_M_CAN_STBY_MASK) >> MCAN_GLB_CTL_M_CAN_STBY_SHIFT) - -/* - * STBY_CLR_EN (RW) - * - * m_can standby clear control - * 0:controlled by software by standby bit[bit31] - * 1:auto clear standby by hardware when rx data is 0 - */ -#define MCAN_GLB_CTL_STBY_CLR_EN_MASK (0x40000000UL) -#define MCAN_GLB_CTL_STBY_CLR_EN_SHIFT (30U) -#define MCAN_GLB_CTL_STBY_CLR_EN_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) -#define MCAN_GLB_CTL_STBY_CLR_EN_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) >> MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) - -/* - * STBY_POL (RW) - * - * standby polarity selection - */ -#define MCAN_GLB_CTL_STBY_POL_MASK (0x20000000UL) -#define MCAN_GLB_CTL_STBY_POL_SHIFT (29U) -#define MCAN_GLB_CTL_STBY_POL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_POL_SHIFT) & MCAN_GLB_CTL_STBY_POL_MASK) -#define MCAN_GLB_CTL_STBY_POL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_POL_MASK) >> MCAN_GLB_CTL_STBY_POL_SHIFT) - -/* - * TSU_TBIN_SEL (RW) - * - * external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - */ -#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x3U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) - -/* Bitfield definition for register: GLB_STATUS */ -/* - * M_CAN_INT1 (R) - * - * m_can interrupt status1 - */ -#define MCAN_GLB_STATUS_M_CAN_INT1_MASK (0x8U) -#define MCAN_GLB_STATUS_M_CAN_INT1_SHIFT (3U) -#define MCAN_GLB_STATUS_M_CAN_INT1_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT1_MASK) >> MCAN_GLB_STATUS_M_CAN_INT1_SHIFT) - -/* - * M_CAN_INT0 (R) - * - * m_can interrupt status0 - */ -#define MCAN_GLB_STATUS_M_CAN_INT0_MASK (0x4U) -#define MCAN_GLB_STATUS_M_CAN_INT0_SHIFT (2U) -#define MCAN_GLB_STATUS_M_CAN_INT0_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT0_MASK) >> MCAN_GLB_STATUS_M_CAN_INT0_SHIFT) - -/* Bitfield definition for register array: MESSAGE_BUFF */ -/* - * DATA (RW) - * - * m_can message buffer - */ -#define MCAN_MESSAGE_BUFF_DATA_MASK (0xFFFFFFFFUL) -#define MCAN_MESSAGE_BUFF_DATA_SHIFT (0U) -#define MCAN_MESSAGE_BUFF_DATA_SET(x) (((uint32_t)(x) << MCAN_MESSAGE_BUFF_DATA_SHIFT) & MCAN_MESSAGE_BUFF_DATA_MASK) -#define MCAN_MESSAGE_BUFF_DATA_GET(x) (((uint32_t)(x) & MCAN_MESSAGE_BUFF_DATA_MASK) >> MCAN_MESSAGE_BUFF_DATA_SHIFT) - - - -/* TS_SEL register group index macro definition */ -#define MCAN_TS_SEL_TS_SEL0 (0UL) -#define MCAN_TS_SEL_TS_SEL1 (1UL) -#define MCAN_TS_SEL_TS_SEL2 (2UL) -#define MCAN_TS_SEL_TS_SEL3 (3UL) -#define MCAN_TS_SEL_TS_SEL4 (4UL) -#define MCAN_TS_SEL_TS_SEL5 (5UL) -#define MCAN_TS_SEL_TS_SEL6 (6UL) -#define MCAN_TS_SEL_TS_SEL7 (7UL) -#define MCAN_TS_SEL_TS_SEL8 (8UL) -#define MCAN_TS_SEL_TS_SEL9 (9UL) -#define MCAN_TS_SEL_TS_SEL10 (10UL) -#define MCAN_TS_SEL_TS_SEL11 (11UL) -#define MCAN_TS_SEL_TS_SEL12 (12UL) -#define MCAN_TS_SEL_TS_SEL13 (13UL) -#define MCAN_TS_SEL_TS_SEL14 (14UL) -#define MCAN_TS_SEL_TS_SEL15 (15UL) - -/* MESSAGE_BUFF register group index macro definition */ -#define MCAN_MESSAGE_BUFF_0 (0UL) -#define MCAN_MESSAGE_BUFF_1 (1UL) -#define MCAN_MESSAGE_BUFF_2 (2UL) -#define MCAN_MESSAGE_BUFF_3 (3UL) -#define MCAN_MESSAGE_BUFF_4 (4UL) -#define MCAN_MESSAGE_BUFF_5 (5UL) -#define MCAN_MESSAGE_BUFF_6 (6UL) -#define MCAN_MESSAGE_BUFF_7 (7UL) -#define MCAN_MESSAGE_BUFF_8 (8UL) -#define MCAN_MESSAGE_BUFF_9 (9UL) -#define MCAN_MESSAGE_BUFF_10 (10UL) -#define MCAN_MESSAGE_BUFF_11 (11UL) -#define MCAN_MESSAGE_BUFF_12 (12UL) -#define MCAN_MESSAGE_BUFF_13 (13UL) -#define MCAN_MESSAGE_BUFF_14 (14UL) -#define MCAN_MESSAGE_BUFF_15 (15UL) -#define MCAN_MESSAGE_BUFF_16 (16UL) -#define MCAN_MESSAGE_BUFF_17 (17UL) -#define MCAN_MESSAGE_BUFF_18 (18UL) -#define MCAN_MESSAGE_BUFF_19 (19UL) -#define MCAN_MESSAGE_BUFF_20 (20UL) -#define MCAN_MESSAGE_BUFF_21 (21UL) -#define MCAN_MESSAGE_BUFF_22 (22UL) -#define MCAN_MESSAGE_BUFF_23 (23UL) -#define MCAN_MESSAGE_BUFF_24 (24UL) -#define MCAN_MESSAGE_BUFF_25 (25UL) -#define MCAN_MESSAGE_BUFF_26 (26UL) -#define MCAN_MESSAGE_BUFF_27 (27UL) -#define MCAN_MESSAGE_BUFF_28 (28UL) -#define MCAN_MESSAGE_BUFF_29 (29UL) -#define MCAN_MESSAGE_BUFF_30 (30UL) -#define MCAN_MESSAGE_BUFF_31 (31UL) -#define MCAN_MESSAGE_BUFF_32 (32UL) -#define MCAN_MESSAGE_BUFF_33 (33UL) -#define MCAN_MESSAGE_BUFF_34 (34UL) -#define MCAN_MESSAGE_BUFF_35 (35UL) -#define MCAN_MESSAGE_BUFF_36 (36UL) -#define MCAN_MESSAGE_BUFF_37 (37UL) -#define MCAN_MESSAGE_BUFF_38 (38UL) -#define MCAN_MESSAGE_BUFF_39 (39UL) -#define MCAN_MESSAGE_BUFF_40 (40UL) -#define MCAN_MESSAGE_BUFF_41 (41UL) -#define MCAN_MESSAGE_BUFF_42 (42UL) -#define MCAN_MESSAGE_BUFF_43 (43UL) -#define MCAN_MESSAGE_BUFF_44 (44UL) -#define MCAN_MESSAGE_BUFF_45 (45UL) -#define MCAN_MESSAGE_BUFF_46 (46UL) -#define MCAN_MESSAGE_BUFF_47 (47UL) -#define MCAN_MESSAGE_BUFF_48 (48UL) -#define MCAN_MESSAGE_BUFF_49 (49UL) -#define MCAN_MESSAGE_BUFF_50 (50UL) -#define MCAN_MESSAGE_BUFF_51 (51UL) -#define MCAN_MESSAGE_BUFF_52 (52UL) -#define MCAN_MESSAGE_BUFF_53 (53UL) -#define MCAN_MESSAGE_BUFF_54 (54UL) -#define MCAN_MESSAGE_BUFF_55 (55UL) -#define MCAN_MESSAGE_BUFF_56 (56UL) -#define MCAN_MESSAGE_BUFF_57 (57UL) -#define MCAN_MESSAGE_BUFF_58 (58UL) -#define MCAN_MESSAGE_BUFF_59 (59UL) -#define MCAN_MESSAGE_BUFF_60 (60UL) -#define MCAN_MESSAGE_BUFF_61 (61UL) -#define MCAN_MESSAGE_BUFF_62 (62UL) -#define MCAN_MESSAGE_BUFF_63 (63UL) -#define MCAN_MESSAGE_BUFF_64 (64UL) -#define MCAN_MESSAGE_BUFF_65 (65UL) -#define MCAN_MESSAGE_BUFF_66 (66UL) -#define MCAN_MESSAGE_BUFF_67 (67UL) -#define MCAN_MESSAGE_BUFF_68 (68UL) -#define MCAN_MESSAGE_BUFF_69 (69UL) -#define MCAN_MESSAGE_BUFF_70 (70UL) -#define MCAN_MESSAGE_BUFF_71 (71UL) -#define MCAN_MESSAGE_BUFF_72 (72UL) -#define MCAN_MESSAGE_BUFF_73 (73UL) -#define MCAN_MESSAGE_BUFF_74 (74UL) -#define MCAN_MESSAGE_BUFF_75 (75UL) -#define MCAN_MESSAGE_BUFF_76 (76UL) -#define MCAN_MESSAGE_BUFF_77 (77UL) -#define MCAN_MESSAGE_BUFF_78 (78UL) -#define MCAN_MESSAGE_BUFF_79 (79UL) -#define MCAN_MESSAGE_BUFF_80 (80UL) -#define MCAN_MESSAGE_BUFF_81 (81UL) -#define MCAN_MESSAGE_BUFF_82 (82UL) -#define MCAN_MESSAGE_BUFF_83 (83UL) -#define MCAN_MESSAGE_BUFF_84 (84UL) -#define MCAN_MESSAGE_BUFF_85 (85UL) -#define MCAN_MESSAGE_BUFF_86 (86UL) -#define MCAN_MESSAGE_BUFF_87 (87UL) -#define MCAN_MESSAGE_BUFF_88 (88UL) -#define MCAN_MESSAGE_BUFF_89 (89UL) -#define MCAN_MESSAGE_BUFF_90 (90UL) -#define MCAN_MESSAGE_BUFF_91 (91UL) -#define MCAN_MESSAGE_BUFF_92 (92UL) -#define MCAN_MESSAGE_BUFF_93 (93UL) -#define MCAN_MESSAGE_BUFF_94 (94UL) -#define MCAN_MESSAGE_BUFF_95 (95UL) -#define MCAN_MESSAGE_BUFF_96 (96UL) -#define MCAN_MESSAGE_BUFF_97 (97UL) -#define MCAN_MESSAGE_BUFF_98 (98UL) -#define MCAN_MESSAGE_BUFF_99 (99UL) -#define MCAN_MESSAGE_BUFF_100 (100UL) -#define MCAN_MESSAGE_BUFF_101 (101UL) -#define MCAN_MESSAGE_BUFF_102 (102UL) -#define MCAN_MESSAGE_BUFF_103 (103UL) -#define MCAN_MESSAGE_BUFF_104 (104UL) -#define MCAN_MESSAGE_BUFF_105 (105UL) -#define MCAN_MESSAGE_BUFF_106 (106UL) -#define MCAN_MESSAGE_BUFF_107 (107UL) -#define MCAN_MESSAGE_BUFF_108 (108UL) -#define MCAN_MESSAGE_BUFF_109 (109UL) -#define MCAN_MESSAGE_BUFF_110 (110UL) -#define MCAN_MESSAGE_BUFF_111 (111UL) -#define MCAN_MESSAGE_BUFF_112 (112UL) -#define MCAN_MESSAGE_BUFF_113 (113UL) -#define MCAN_MESSAGE_BUFF_114 (114UL) -#define MCAN_MESSAGE_BUFF_115 (115UL) -#define MCAN_MESSAGE_BUFF_116 (116UL) -#define MCAN_MESSAGE_BUFF_117 (117UL) -#define MCAN_MESSAGE_BUFF_118 (118UL) -#define MCAN_MESSAGE_BUFF_119 (119UL) -#define MCAN_MESSAGE_BUFF_120 (120UL) -#define MCAN_MESSAGE_BUFF_121 (121UL) -#define MCAN_MESSAGE_BUFF_122 (122UL) -#define MCAN_MESSAGE_BUFF_123 (123UL) -#define MCAN_MESSAGE_BUFF_124 (124UL) -#define MCAN_MESSAGE_BUFF_125 (125UL) -#define MCAN_MESSAGE_BUFF_126 (126UL) -#define MCAN_MESSAGE_BUFF_127 (127UL) -#define MCAN_MESSAGE_BUFF_128 (128UL) -#define MCAN_MESSAGE_BUFF_129 (129UL) -#define MCAN_MESSAGE_BUFF_130 (130UL) -#define MCAN_MESSAGE_BUFF_131 (131UL) -#define MCAN_MESSAGE_BUFF_132 (132UL) -#define MCAN_MESSAGE_BUFF_133 (133UL) -#define MCAN_MESSAGE_BUFF_134 (134UL) -#define MCAN_MESSAGE_BUFF_135 (135UL) -#define MCAN_MESSAGE_BUFF_136 (136UL) -#define MCAN_MESSAGE_BUFF_137 (137UL) -#define MCAN_MESSAGE_BUFF_138 (138UL) -#define MCAN_MESSAGE_BUFF_139 (139UL) -#define MCAN_MESSAGE_BUFF_140 (140UL) -#define MCAN_MESSAGE_BUFF_141 (141UL) -#define MCAN_MESSAGE_BUFF_142 (142UL) -#define MCAN_MESSAGE_BUFF_143 (143UL) -#define MCAN_MESSAGE_BUFF_144 (144UL) -#define MCAN_MESSAGE_BUFF_145 (145UL) -#define MCAN_MESSAGE_BUFF_146 (146UL) -#define MCAN_MESSAGE_BUFF_147 (147UL) -#define MCAN_MESSAGE_BUFF_148 (148UL) -#define MCAN_MESSAGE_BUFF_149 (149UL) -#define MCAN_MESSAGE_BUFF_150 (150UL) -#define MCAN_MESSAGE_BUFF_151 (151UL) -#define MCAN_MESSAGE_BUFF_152 (152UL) -#define MCAN_MESSAGE_BUFF_153 (153UL) -#define MCAN_MESSAGE_BUFF_154 (154UL) -#define MCAN_MESSAGE_BUFF_155 (155UL) -#define MCAN_MESSAGE_BUFF_156 (156UL) -#define MCAN_MESSAGE_BUFF_157 (157UL) -#define MCAN_MESSAGE_BUFF_158 (158UL) -#define MCAN_MESSAGE_BUFF_159 (159UL) -#define MCAN_MESSAGE_BUFF_160 (160UL) -#define MCAN_MESSAGE_BUFF_161 (161UL) -#define MCAN_MESSAGE_BUFF_162 (162UL) -#define MCAN_MESSAGE_BUFF_163 (163UL) -#define MCAN_MESSAGE_BUFF_164 (164UL) -#define MCAN_MESSAGE_BUFF_165 (165UL) -#define MCAN_MESSAGE_BUFF_166 (166UL) -#define MCAN_MESSAGE_BUFF_167 (167UL) -#define MCAN_MESSAGE_BUFF_168 (168UL) -#define MCAN_MESSAGE_BUFF_169 (169UL) -#define MCAN_MESSAGE_BUFF_170 (170UL) -#define MCAN_MESSAGE_BUFF_171 (171UL) -#define MCAN_MESSAGE_BUFF_172 (172UL) -#define MCAN_MESSAGE_BUFF_173 (173UL) -#define MCAN_MESSAGE_BUFF_174 (174UL) -#define MCAN_MESSAGE_BUFF_175 (175UL) -#define MCAN_MESSAGE_BUFF_176 (176UL) -#define MCAN_MESSAGE_BUFF_177 (177UL) -#define MCAN_MESSAGE_BUFF_178 (178UL) -#define MCAN_MESSAGE_BUFF_179 (179UL) -#define MCAN_MESSAGE_BUFF_180 (180UL) -#define MCAN_MESSAGE_BUFF_181 (181UL) -#define MCAN_MESSAGE_BUFF_182 (182UL) -#define MCAN_MESSAGE_BUFF_183 (183UL) -#define MCAN_MESSAGE_BUFF_184 (184UL) -#define MCAN_MESSAGE_BUFF_185 (185UL) -#define MCAN_MESSAGE_BUFF_186 (186UL) -#define MCAN_MESSAGE_BUFF_187 (187UL) -#define MCAN_MESSAGE_BUFF_188 (188UL) -#define MCAN_MESSAGE_BUFF_189 (189UL) -#define MCAN_MESSAGE_BUFF_190 (190UL) -#define MCAN_MESSAGE_BUFF_191 (191UL) -#define MCAN_MESSAGE_BUFF_192 (192UL) -#define MCAN_MESSAGE_BUFF_193 (193UL) -#define MCAN_MESSAGE_BUFF_194 (194UL) -#define MCAN_MESSAGE_BUFF_195 (195UL) -#define MCAN_MESSAGE_BUFF_196 (196UL) -#define MCAN_MESSAGE_BUFF_197 (197UL) -#define MCAN_MESSAGE_BUFF_198 (198UL) -#define MCAN_MESSAGE_BUFF_199 (199UL) -#define MCAN_MESSAGE_BUFF_200 (200UL) -#define MCAN_MESSAGE_BUFF_201 (201UL) -#define MCAN_MESSAGE_BUFF_202 (202UL) -#define MCAN_MESSAGE_BUFF_203 (203UL) -#define MCAN_MESSAGE_BUFF_204 (204UL) -#define MCAN_MESSAGE_BUFF_205 (205UL) -#define MCAN_MESSAGE_BUFF_206 (206UL) -#define MCAN_MESSAGE_BUFF_207 (207UL) -#define MCAN_MESSAGE_BUFF_208 (208UL) -#define MCAN_MESSAGE_BUFF_209 (209UL) -#define MCAN_MESSAGE_BUFF_210 (210UL) -#define MCAN_MESSAGE_BUFF_211 (211UL) -#define MCAN_MESSAGE_BUFF_212 (212UL) -#define MCAN_MESSAGE_BUFF_213 (213UL) -#define MCAN_MESSAGE_BUFF_214 (214UL) -#define MCAN_MESSAGE_BUFF_215 (215UL) -#define MCAN_MESSAGE_BUFF_216 (216UL) -#define MCAN_MESSAGE_BUFF_217 (217UL) -#define MCAN_MESSAGE_BUFF_218 (218UL) -#define MCAN_MESSAGE_BUFF_219 (219UL) -#define MCAN_MESSAGE_BUFF_220 (220UL) -#define MCAN_MESSAGE_BUFF_221 (221UL) -#define MCAN_MESSAGE_BUFF_222 (222UL) -#define MCAN_MESSAGE_BUFF_223 (223UL) -#define MCAN_MESSAGE_BUFF_224 (224UL) -#define MCAN_MESSAGE_BUFF_225 (225UL) -#define MCAN_MESSAGE_BUFF_226 (226UL) -#define MCAN_MESSAGE_BUFF_227 (227UL) -#define MCAN_MESSAGE_BUFF_228 (228UL) -#define MCAN_MESSAGE_BUFF_229 (229UL) -#define MCAN_MESSAGE_BUFF_230 (230UL) -#define MCAN_MESSAGE_BUFF_231 (231UL) -#define MCAN_MESSAGE_BUFF_232 (232UL) -#define MCAN_MESSAGE_BUFF_233 (233UL) -#define MCAN_MESSAGE_BUFF_234 (234UL) -#define MCAN_MESSAGE_BUFF_235 (235UL) -#define MCAN_MESSAGE_BUFF_236 (236UL) -#define MCAN_MESSAGE_BUFF_237 (237UL) -#define MCAN_MESSAGE_BUFF_238 (238UL) -#define MCAN_MESSAGE_BUFF_239 (239UL) -#define MCAN_MESSAGE_BUFF_240 (240UL) -#define MCAN_MESSAGE_BUFF_241 (241UL) -#define MCAN_MESSAGE_BUFF_242 (242UL) -#define MCAN_MESSAGE_BUFF_243 (243UL) -#define MCAN_MESSAGE_BUFF_244 (244UL) -#define MCAN_MESSAGE_BUFF_245 (245UL) -#define MCAN_MESSAGE_BUFF_246 (246UL) -#define MCAN_MESSAGE_BUFF_247 (247UL) -#define MCAN_MESSAGE_BUFF_248 (248UL) -#define MCAN_MESSAGE_BUFF_249 (249UL) -#define MCAN_MESSAGE_BUFF_250 (250UL) -#define MCAN_MESSAGE_BUFF_251 (251UL) -#define MCAN_MESSAGE_BUFF_252 (252UL) -#define MCAN_MESSAGE_BUFF_253 (253UL) -#define MCAN_MESSAGE_BUFF_254 (254UL) -#define MCAN_MESSAGE_BUFF_255 (255UL) -#define MCAN_MESSAGE_BUFF_256 (256UL) -#define MCAN_MESSAGE_BUFF_257 (257UL) -#define MCAN_MESSAGE_BUFF_258 (258UL) -#define MCAN_MESSAGE_BUFF_259 (259UL) -#define MCAN_MESSAGE_BUFF_260 (260UL) -#define MCAN_MESSAGE_BUFF_261 (261UL) -#define MCAN_MESSAGE_BUFF_262 (262UL) -#define MCAN_MESSAGE_BUFF_263 (263UL) -#define MCAN_MESSAGE_BUFF_264 (264UL) -#define MCAN_MESSAGE_BUFF_265 (265UL) -#define MCAN_MESSAGE_BUFF_266 (266UL) -#define MCAN_MESSAGE_BUFF_267 (267UL) -#define MCAN_MESSAGE_BUFF_268 (268UL) -#define MCAN_MESSAGE_BUFF_269 (269UL) -#define MCAN_MESSAGE_BUFF_270 (270UL) -#define MCAN_MESSAGE_BUFF_271 (271UL) -#define MCAN_MESSAGE_BUFF_272 (272UL) -#define MCAN_MESSAGE_BUFF_273 (273UL) -#define MCAN_MESSAGE_BUFF_274 (274UL) -#define MCAN_MESSAGE_BUFF_275 (275UL) -#define MCAN_MESSAGE_BUFF_276 (276UL) -#define MCAN_MESSAGE_BUFF_277 (277UL) -#define MCAN_MESSAGE_BUFF_278 (278UL) -#define MCAN_MESSAGE_BUFF_279 (279UL) -#define MCAN_MESSAGE_BUFF_280 (280UL) -#define MCAN_MESSAGE_BUFF_281 (281UL) -#define MCAN_MESSAGE_BUFF_282 (282UL) -#define MCAN_MESSAGE_BUFF_283 (283UL) -#define MCAN_MESSAGE_BUFF_284 (284UL) -#define MCAN_MESSAGE_BUFF_285 (285UL) -#define MCAN_MESSAGE_BUFF_286 (286UL) -#define MCAN_MESSAGE_BUFF_287 (287UL) -#define MCAN_MESSAGE_BUFF_288 (288UL) -#define MCAN_MESSAGE_BUFF_289 (289UL) -#define MCAN_MESSAGE_BUFF_290 (290UL) -#define MCAN_MESSAGE_BUFF_291 (291UL) -#define MCAN_MESSAGE_BUFF_292 (292UL) -#define MCAN_MESSAGE_BUFF_293 (293UL) -#define MCAN_MESSAGE_BUFF_294 (294UL) -#define MCAN_MESSAGE_BUFF_295 (295UL) -#define MCAN_MESSAGE_BUFF_296 (296UL) -#define MCAN_MESSAGE_BUFF_297 (297UL) -#define MCAN_MESSAGE_BUFF_298 (298UL) -#define MCAN_MESSAGE_BUFF_299 (299UL) -#define MCAN_MESSAGE_BUFF_300 (300UL) -#define MCAN_MESSAGE_BUFF_301 (301UL) -#define MCAN_MESSAGE_BUFF_302 (302UL) -#define MCAN_MESSAGE_BUFF_303 (303UL) -#define MCAN_MESSAGE_BUFF_304 (304UL) -#define MCAN_MESSAGE_BUFF_305 (305UL) -#define MCAN_MESSAGE_BUFF_306 (306UL) -#define MCAN_MESSAGE_BUFF_307 (307UL) -#define MCAN_MESSAGE_BUFF_308 (308UL) -#define MCAN_MESSAGE_BUFF_309 (309UL) -#define MCAN_MESSAGE_BUFF_310 (310UL) -#define MCAN_MESSAGE_BUFF_311 (311UL) -#define MCAN_MESSAGE_BUFF_312 (312UL) -#define MCAN_MESSAGE_BUFF_313 (313UL) -#define MCAN_MESSAGE_BUFF_314 (314UL) -#define MCAN_MESSAGE_BUFF_315 (315UL) -#define MCAN_MESSAGE_BUFF_316 (316UL) -#define MCAN_MESSAGE_BUFF_317 (317UL) -#define MCAN_MESSAGE_BUFF_318 (318UL) -#define MCAN_MESSAGE_BUFF_319 (319UL) -#define MCAN_MESSAGE_BUFF_320 (320UL) -#define MCAN_MESSAGE_BUFF_321 (321UL) -#define MCAN_MESSAGE_BUFF_322 (322UL) -#define MCAN_MESSAGE_BUFF_323 (323UL) -#define MCAN_MESSAGE_BUFF_324 (324UL) -#define MCAN_MESSAGE_BUFF_325 (325UL) -#define MCAN_MESSAGE_BUFF_326 (326UL) -#define MCAN_MESSAGE_BUFF_327 (327UL) -#define MCAN_MESSAGE_BUFF_328 (328UL) -#define MCAN_MESSAGE_BUFF_329 (329UL) -#define MCAN_MESSAGE_BUFF_330 (330UL) -#define MCAN_MESSAGE_BUFF_331 (331UL) -#define MCAN_MESSAGE_BUFF_332 (332UL) -#define MCAN_MESSAGE_BUFF_333 (333UL) -#define MCAN_MESSAGE_BUFF_334 (334UL) -#define MCAN_MESSAGE_BUFF_335 (335UL) -#define MCAN_MESSAGE_BUFF_336 (336UL) -#define MCAN_MESSAGE_BUFF_337 (337UL) -#define MCAN_MESSAGE_BUFF_338 (338UL) -#define MCAN_MESSAGE_BUFF_339 (339UL) -#define MCAN_MESSAGE_BUFF_340 (340UL) -#define MCAN_MESSAGE_BUFF_341 (341UL) -#define MCAN_MESSAGE_BUFF_342 (342UL) -#define MCAN_MESSAGE_BUFF_343 (343UL) -#define MCAN_MESSAGE_BUFF_344 (344UL) -#define MCAN_MESSAGE_BUFF_345 (345UL) -#define MCAN_MESSAGE_BUFF_346 (346UL) -#define MCAN_MESSAGE_BUFF_347 (347UL) -#define MCAN_MESSAGE_BUFF_348 (348UL) -#define MCAN_MESSAGE_BUFF_349 (349UL) -#define MCAN_MESSAGE_BUFF_350 (350UL) -#define MCAN_MESSAGE_BUFF_351 (351UL) -#define MCAN_MESSAGE_BUFF_352 (352UL) -#define MCAN_MESSAGE_BUFF_353 (353UL) -#define MCAN_MESSAGE_BUFF_354 (354UL) -#define MCAN_MESSAGE_BUFF_355 (355UL) -#define MCAN_MESSAGE_BUFF_356 (356UL) -#define MCAN_MESSAGE_BUFF_357 (357UL) -#define MCAN_MESSAGE_BUFF_358 (358UL) -#define MCAN_MESSAGE_BUFF_359 (359UL) -#define MCAN_MESSAGE_BUFF_360 (360UL) -#define MCAN_MESSAGE_BUFF_361 (361UL) -#define MCAN_MESSAGE_BUFF_362 (362UL) -#define MCAN_MESSAGE_BUFF_363 (363UL) -#define MCAN_MESSAGE_BUFF_364 (364UL) -#define MCAN_MESSAGE_BUFF_365 (365UL) -#define MCAN_MESSAGE_BUFF_366 (366UL) -#define MCAN_MESSAGE_BUFF_367 (367UL) -#define MCAN_MESSAGE_BUFF_368 (368UL) -#define MCAN_MESSAGE_BUFF_369 (369UL) -#define MCAN_MESSAGE_BUFF_370 (370UL) -#define MCAN_MESSAGE_BUFF_371 (371UL) -#define MCAN_MESSAGE_BUFF_372 (372UL) -#define MCAN_MESSAGE_BUFF_373 (373UL) -#define MCAN_MESSAGE_BUFF_374 (374UL) -#define MCAN_MESSAGE_BUFF_375 (375UL) -#define MCAN_MESSAGE_BUFF_376 (376UL) -#define MCAN_MESSAGE_BUFF_377 (377UL) -#define MCAN_MESSAGE_BUFF_378 (378UL) -#define MCAN_MESSAGE_BUFF_379 (379UL) -#define MCAN_MESSAGE_BUFF_380 (380UL) -#define MCAN_MESSAGE_BUFF_381 (381UL) -#define MCAN_MESSAGE_BUFF_382 (382UL) -#define MCAN_MESSAGE_BUFF_383 (383UL) -#define MCAN_MESSAGE_BUFF_384 (384UL) -#define MCAN_MESSAGE_BUFF_385 (385UL) -#define MCAN_MESSAGE_BUFF_386 (386UL) -#define MCAN_MESSAGE_BUFF_387 (387UL) -#define MCAN_MESSAGE_BUFF_388 (388UL) -#define MCAN_MESSAGE_BUFF_389 (389UL) -#define MCAN_MESSAGE_BUFF_390 (390UL) -#define MCAN_MESSAGE_BUFF_391 (391UL) -#define MCAN_MESSAGE_BUFF_392 (392UL) -#define MCAN_MESSAGE_BUFF_393 (393UL) -#define MCAN_MESSAGE_BUFF_394 (394UL) -#define MCAN_MESSAGE_BUFF_395 (395UL) -#define MCAN_MESSAGE_BUFF_396 (396UL) -#define MCAN_MESSAGE_BUFF_397 (397UL) -#define MCAN_MESSAGE_BUFF_398 (398UL) -#define MCAN_MESSAGE_BUFF_399 (399UL) -#define MCAN_MESSAGE_BUFF_400 (400UL) -#define MCAN_MESSAGE_BUFF_401 (401UL) -#define MCAN_MESSAGE_BUFF_402 (402UL) -#define MCAN_MESSAGE_BUFF_403 (403UL) -#define MCAN_MESSAGE_BUFF_404 (404UL) -#define MCAN_MESSAGE_BUFF_405 (405UL) -#define MCAN_MESSAGE_BUFF_406 (406UL) -#define MCAN_MESSAGE_BUFF_407 (407UL) -#define MCAN_MESSAGE_BUFF_408 (408UL) -#define MCAN_MESSAGE_BUFF_409 (409UL) -#define MCAN_MESSAGE_BUFF_410 (410UL) -#define MCAN_MESSAGE_BUFF_411 (411UL) -#define MCAN_MESSAGE_BUFF_412 (412UL) -#define MCAN_MESSAGE_BUFF_413 (413UL) -#define MCAN_MESSAGE_BUFF_414 (414UL) -#define MCAN_MESSAGE_BUFF_415 (415UL) -#define MCAN_MESSAGE_BUFF_416 (416UL) -#define MCAN_MESSAGE_BUFF_417 (417UL) -#define MCAN_MESSAGE_BUFF_418 (418UL) -#define MCAN_MESSAGE_BUFF_419 (419UL) -#define MCAN_MESSAGE_BUFF_420 (420UL) -#define MCAN_MESSAGE_BUFF_421 (421UL) -#define MCAN_MESSAGE_BUFF_422 (422UL) -#define MCAN_MESSAGE_BUFF_423 (423UL) -#define MCAN_MESSAGE_BUFF_424 (424UL) -#define MCAN_MESSAGE_BUFF_425 (425UL) -#define MCAN_MESSAGE_BUFF_426 (426UL) -#define MCAN_MESSAGE_BUFF_427 (427UL) -#define MCAN_MESSAGE_BUFF_428 (428UL) -#define MCAN_MESSAGE_BUFF_429 (429UL) -#define MCAN_MESSAGE_BUFF_430 (430UL) -#define MCAN_MESSAGE_BUFF_431 (431UL) -#define MCAN_MESSAGE_BUFF_432 (432UL) -#define MCAN_MESSAGE_BUFF_433 (433UL) -#define MCAN_MESSAGE_BUFF_434 (434UL) -#define MCAN_MESSAGE_BUFF_435 (435UL) -#define MCAN_MESSAGE_BUFF_436 (436UL) -#define MCAN_MESSAGE_BUFF_437 (437UL) -#define MCAN_MESSAGE_BUFF_438 (438UL) -#define MCAN_MESSAGE_BUFF_439 (439UL) -#define MCAN_MESSAGE_BUFF_440 (440UL) -#define MCAN_MESSAGE_BUFF_441 (441UL) -#define MCAN_MESSAGE_BUFF_442 (442UL) -#define MCAN_MESSAGE_BUFF_443 (443UL) -#define MCAN_MESSAGE_BUFF_444 (444UL) -#define MCAN_MESSAGE_BUFF_445 (445UL) -#define MCAN_MESSAGE_BUFF_446 (446UL) -#define MCAN_MESSAGE_BUFF_447 (447UL) -#define MCAN_MESSAGE_BUFF_448 (448UL) -#define MCAN_MESSAGE_BUFF_449 (449UL) -#define MCAN_MESSAGE_BUFF_450 (450UL) -#define MCAN_MESSAGE_BUFF_451 (451UL) -#define MCAN_MESSAGE_BUFF_452 (452UL) -#define MCAN_MESSAGE_BUFF_453 (453UL) -#define MCAN_MESSAGE_BUFF_454 (454UL) -#define MCAN_MESSAGE_BUFF_455 (455UL) -#define MCAN_MESSAGE_BUFF_456 (456UL) -#define MCAN_MESSAGE_BUFF_457 (457UL) -#define MCAN_MESSAGE_BUFF_458 (458UL) -#define MCAN_MESSAGE_BUFF_459 (459UL) -#define MCAN_MESSAGE_BUFF_460 (460UL) -#define MCAN_MESSAGE_BUFF_461 (461UL) -#define MCAN_MESSAGE_BUFF_462 (462UL) -#define MCAN_MESSAGE_BUFF_463 (463UL) -#define MCAN_MESSAGE_BUFF_464 (464UL) -#define MCAN_MESSAGE_BUFF_465 (465UL) -#define MCAN_MESSAGE_BUFF_466 (466UL) -#define MCAN_MESSAGE_BUFF_467 (467UL) -#define MCAN_MESSAGE_BUFF_468 (468UL) -#define MCAN_MESSAGE_BUFF_469 (469UL) -#define MCAN_MESSAGE_BUFF_470 (470UL) -#define MCAN_MESSAGE_BUFF_471 (471UL) -#define MCAN_MESSAGE_BUFF_472 (472UL) -#define MCAN_MESSAGE_BUFF_473 (473UL) -#define MCAN_MESSAGE_BUFF_474 (474UL) -#define MCAN_MESSAGE_BUFF_475 (475UL) -#define MCAN_MESSAGE_BUFF_476 (476UL) -#define MCAN_MESSAGE_BUFF_477 (477UL) -#define MCAN_MESSAGE_BUFF_478 (478UL) -#define MCAN_MESSAGE_BUFF_479 (479UL) -#define MCAN_MESSAGE_BUFF_480 (480UL) -#define MCAN_MESSAGE_BUFF_481 (481UL) -#define MCAN_MESSAGE_BUFF_482 (482UL) -#define MCAN_MESSAGE_BUFF_483 (483UL) -#define MCAN_MESSAGE_BUFF_484 (484UL) -#define MCAN_MESSAGE_BUFF_485 (485UL) -#define MCAN_MESSAGE_BUFF_486 (486UL) -#define MCAN_MESSAGE_BUFF_487 (487UL) -#define MCAN_MESSAGE_BUFF_488 (488UL) -#define MCAN_MESSAGE_BUFF_489 (489UL) -#define MCAN_MESSAGE_BUFF_490 (490UL) -#define MCAN_MESSAGE_BUFF_491 (491UL) -#define MCAN_MESSAGE_BUFF_492 (492UL) -#define MCAN_MESSAGE_BUFF_493 (493UL) -#define MCAN_MESSAGE_BUFF_494 (494UL) -#define MCAN_MESSAGE_BUFF_495 (495UL) -#define MCAN_MESSAGE_BUFF_496 (496UL) -#define MCAN_MESSAGE_BUFF_497 (497UL) -#define MCAN_MESSAGE_BUFF_498 (498UL) -#define MCAN_MESSAGE_BUFF_499 (499UL) -#define MCAN_MESSAGE_BUFF_500 (500UL) -#define MCAN_MESSAGE_BUFF_501 (501UL) -#define MCAN_MESSAGE_BUFF_502 (502UL) -#define MCAN_MESSAGE_BUFF_503 (503UL) -#define MCAN_MESSAGE_BUFF_504 (504UL) -#define MCAN_MESSAGE_BUFF_505 (505UL) -#define MCAN_MESSAGE_BUFF_506 (506UL) -#define MCAN_MESSAGE_BUFF_507 (507UL) -#define MCAN_MESSAGE_BUFF_508 (508UL) -#define MCAN_MESSAGE_BUFF_509 (509UL) -#define MCAN_MESSAGE_BUFF_510 (510UL) -#define MCAN_MESSAGE_BUFF_511 (511UL) -#define MCAN_MESSAGE_BUFF_512 (512UL) -#define MCAN_MESSAGE_BUFF_513 (513UL) -#define MCAN_MESSAGE_BUFF_514 (514UL) -#define MCAN_MESSAGE_BUFF_515 (515UL) -#define MCAN_MESSAGE_BUFF_516 (516UL) -#define MCAN_MESSAGE_BUFF_517 (517UL) -#define MCAN_MESSAGE_BUFF_518 (518UL) -#define MCAN_MESSAGE_BUFF_519 (519UL) -#define MCAN_MESSAGE_BUFF_520 (520UL) -#define MCAN_MESSAGE_BUFF_521 (521UL) -#define MCAN_MESSAGE_BUFF_522 (522UL) -#define MCAN_MESSAGE_BUFF_523 (523UL) -#define MCAN_MESSAGE_BUFF_524 (524UL) -#define MCAN_MESSAGE_BUFF_525 (525UL) -#define MCAN_MESSAGE_BUFF_526 (526UL) -#define MCAN_MESSAGE_BUFF_527 (527UL) -#define MCAN_MESSAGE_BUFF_528 (528UL) -#define MCAN_MESSAGE_BUFF_529 (529UL) -#define MCAN_MESSAGE_BUFF_530 (530UL) -#define MCAN_MESSAGE_BUFF_531 (531UL) -#define MCAN_MESSAGE_BUFF_532 (532UL) -#define MCAN_MESSAGE_BUFF_533 (533UL) -#define MCAN_MESSAGE_BUFF_534 (534UL) -#define MCAN_MESSAGE_BUFF_535 (535UL) -#define MCAN_MESSAGE_BUFF_536 (536UL) -#define MCAN_MESSAGE_BUFF_537 (537UL) -#define MCAN_MESSAGE_BUFF_538 (538UL) -#define MCAN_MESSAGE_BUFF_539 (539UL) -#define MCAN_MESSAGE_BUFF_540 (540UL) -#define MCAN_MESSAGE_BUFF_541 (541UL) -#define MCAN_MESSAGE_BUFF_542 (542UL) -#define MCAN_MESSAGE_BUFF_543 (543UL) -#define MCAN_MESSAGE_BUFF_544 (544UL) -#define MCAN_MESSAGE_BUFF_545 (545UL) -#define MCAN_MESSAGE_BUFF_546 (546UL) -#define MCAN_MESSAGE_BUFF_547 (547UL) -#define MCAN_MESSAGE_BUFF_548 (548UL) -#define MCAN_MESSAGE_BUFF_549 (549UL) -#define MCAN_MESSAGE_BUFF_550 (550UL) -#define MCAN_MESSAGE_BUFF_551 (551UL) -#define MCAN_MESSAGE_BUFF_552 (552UL) -#define MCAN_MESSAGE_BUFF_553 (553UL) -#define MCAN_MESSAGE_BUFF_554 (554UL) -#define MCAN_MESSAGE_BUFF_555 (555UL) -#define MCAN_MESSAGE_BUFF_556 (556UL) -#define MCAN_MESSAGE_BUFF_557 (557UL) -#define MCAN_MESSAGE_BUFF_558 (558UL) -#define MCAN_MESSAGE_BUFF_559 (559UL) -#define MCAN_MESSAGE_BUFF_560 (560UL) -#define MCAN_MESSAGE_BUFF_561 (561UL) -#define MCAN_MESSAGE_BUFF_562 (562UL) -#define MCAN_MESSAGE_BUFF_563 (563UL) -#define MCAN_MESSAGE_BUFF_564 (564UL) -#define MCAN_MESSAGE_BUFF_565 (565UL) -#define MCAN_MESSAGE_BUFF_566 (566UL) -#define MCAN_MESSAGE_BUFF_567 (567UL) -#define MCAN_MESSAGE_BUFF_568 (568UL) -#define MCAN_MESSAGE_BUFF_569 (569UL) -#define MCAN_MESSAGE_BUFF_570 (570UL) -#define MCAN_MESSAGE_BUFF_571 (571UL) -#define MCAN_MESSAGE_BUFF_572 (572UL) -#define MCAN_MESSAGE_BUFF_573 (573UL) -#define MCAN_MESSAGE_BUFF_574 (574UL) -#define MCAN_MESSAGE_BUFF_575 (575UL) -#define MCAN_MESSAGE_BUFF_576 (576UL) -#define MCAN_MESSAGE_BUFF_577 (577UL) -#define MCAN_MESSAGE_BUFF_578 (578UL) -#define MCAN_MESSAGE_BUFF_579 (579UL) -#define MCAN_MESSAGE_BUFF_580 (580UL) -#define MCAN_MESSAGE_BUFF_581 (581UL) -#define MCAN_MESSAGE_BUFF_582 (582UL) -#define MCAN_MESSAGE_BUFF_583 (583UL) -#define MCAN_MESSAGE_BUFF_584 (584UL) -#define MCAN_MESSAGE_BUFF_585 (585UL) -#define MCAN_MESSAGE_BUFF_586 (586UL) -#define MCAN_MESSAGE_BUFF_587 (587UL) -#define MCAN_MESSAGE_BUFF_588 (588UL) -#define MCAN_MESSAGE_BUFF_589 (589UL) -#define MCAN_MESSAGE_BUFF_590 (590UL) -#define MCAN_MESSAGE_BUFF_591 (591UL) -#define MCAN_MESSAGE_BUFF_592 (592UL) -#define MCAN_MESSAGE_BUFF_593 (593UL) -#define MCAN_MESSAGE_BUFF_594 (594UL) -#define MCAN_MESSAGE_BUFF_595 (595UL) -#define MCAN_MESSAGE_BUFF_596 (596UL) -#define MCAN_MESSAGE_BUFF_597 (597UL) -#define MCAN_MESSAGE_BUFF_598 (598UL) -#define MCAN_MESSAGE_BUFF_599 (599UL) -#define MCAN_MESSAGE_BUFF_600 (600UL) -#define MCAN_MESSAGE_BUFF_601 (601UL) -#define MCAN_MESSAGE_BUFF_602 (602UL) -#define MCAN_MESSAGE_BUFF_603 (603UL) -#define MCAN_MESSAGE_BUFF_604 (604UL) -#define MCAN_MESSAGE_BUFF_605 (605UL) -#define MCAN_MESSAGE_BUFF_606 (606UL) -#define MCAN_MESSAGE_BUFF_607 (607UL) -#define MCAN_MESSAGE_BUFF_608 (608UL) -#define MCAN_MESSAGE_BUFF_609 (609UL) -#define MCAN_MESSAGE_BUFF_610 (610UL) -#define MCAN_MESSAGE_BUFF_611 (611UL) -#define MCAN_MESSAGE_BUFF_612 (612UL) -#define MCAN_MESSAGE_BUFF_613 (613UL) -#define MCAN_MESSAGE_BUFF_614 (614UL) -#define MCAN_MESSAGE_BUFF_615 (615UL) -#define MCAN_MESSAGE_BUFF_616 (616UL) -#define MCAN_MESSAGE_BUFF_617 (617UL) -#define MCAN_MESSAGE_BUFF_618 (618UL) -#define MCAN_MESSAGE_BUFF_619 (619UL) -#define MCAN_MESSAGE_BUFF_620 (620UL) -#define MCAN_MESSAGE_BUFF_621 (621UL) -#define MCAN_MESSAGE_BUFF_622 (622UL) -#define MCAN_MESSAGE_BUFF_623 (623UL) -#define MCAN_MESSAGE_BUFF_624 (624UL) -#define MCAN_MESSAGE_BUFF_625 (625UL) -#define MCAN_MESSAGE_BUFF_626 (626UL) -#define MCAN_MESSAGE_BUFF_627 (627UL) -#define MCAN_MESSAGE_BUFF_628 (628UL) -#define MCAN_MESSAGE_BUFF_629 (629UL) -#define MCAN_MESSAGE_BUFF_630 (630UL) -#define MCAN_MESSAGE_BUFF_631 (631UL) -#define MCAN_MESSAGE_BUFF_632 (632UL) -#define MCAN_MESSAGE_BUFF_633 (633UL) -#define MCAN_MESSAGE_BUFF_634 (634UL) -#define MCAN_MESSAGE_BUFF_635 (635UL) -#define MCAN_MESSAGE_BUFF_636 (636UL) -#define MCAN_MESSAGE_BUFF_637 (637UL) -#define MCAN_MESSAGE_BUFF_638 (638UL) -#define MCAN_MESSAGE_BUFF_639 (639UL) - - -#endif /* HPM_MCAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mchtmr_regs.h deleted file mode 100644 index d9dfe58a7b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mchtmr_regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCHTMR_H -#define HPM_MCHTMR_H - -typedef struct { - __RW uint64_t MTIME; /* 0x0: Machine Time */ - __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ -} MCHTMR_Type; - - -/* Bitfield definition for register: MTIME */ -/* - * MTIME (RW) - * - * Machine time - */ -#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIME_MTIME_SHIFT (0U) -#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) -#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) - -/* Bitfield definition for register: MTIMECMP */ -/* - * MTIMECMP (RW) - * - * Machine time compare - */ -#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) -#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) -#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) - - - - -#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_csi_phy_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_csi_phy_regs.h deleted file mode 100644 index 3c04524ca34..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_csi_phy_regs.h +++ /dev/null @@ -1,961 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MIPI_CSI_PHY_H -#define HPM_MIPI_CSI_PHY_H - -typedef struct { - __RW uint32_t SOFT_RST; /* 0x0: soft reset control */ - __RW uint32_t PHY_RCAL; /* 0x4: dphy resistor calibration */ - __RW uint32_t ULP_RX_EN; /* 0x8: enable lprx and ulprx */ - __R uint32_t VOFFCAL_OUT; /* 0xC: hs-rx dc-offset auto-calibration results */ - __RW uint32_t CSI_CTL01; /* 0x10: dphy hardcore control */ - __RW uint32_t CSI_CTL23; /* 0x14: dphy hardcore control */ - __R uint8_t RESERVED0[4]; /* 0x18 - 0x1B: Reserved */ - __RW uint32_t CSI_VINIT; /* 0x1C: ulp lp-rx input threshold voltage trimming for data lane */ - __RW uint32_t CLANE_PARA; /* 0x20: clock lane parameter */ - __RW uint32_t T_HS_TERMEN; /* 0x24: t-termen of all datalane */ - __RW uint32_t T_HS_SETTLE; /* 0x28: t-settle of all data lanes */ - __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ - __RW uint32_t T_CLANE_INIT; /* 0x30: t-init of clock lane */ - __RW uint32_t T_LANE_INIT0; /* 0x34: t-init of data lane0 */ - __RW uint32_t T_LANE_INIT1; /* 0x38: t-init of data lane1 */ - __R uint8_t RESERVED2[8]; /* 0x3C - 0x43: Reserved */ - __RW uint32_t TLPX_CTRL; /* 0x44: the time of tlpx_ctrl of all lane */ - __RW uint32_t NE_SWAP; /* 0x48: lane swap and dp/dn swap select */ - __RW uint32_t MISC_INFO; /* 0x4C: misc info of dphyrx_pcs control */ - __R uint8_t RESERVED3[32]; /* 0x50 - 0x6F: Reserved */ - __RW uint32_t BIST_TEST0; /* 0x70: bist test control */ - __RW uint32_t BIST_TEST1; /* 0x74: bist test control */ - __RW uint32_t BIST_TEST2; /* 0x78: bist test control */ - __R uint32_t BIST_TEST3; /* 0x7C: bist test control */ - __R uint8_t RESERVED4[32]; /* 0x80 - 0x9F: Reserved */ - __RW uint32_t BURN_IN_TEST0; /* 0xA0: burn-in test control */ - __RW uint32_t BURN_IN_TEST1; /* 0xA4: burn-in test control */ - __R uint32_t BURN_IN_TEST2; /* 0xA8: bist test control */ - __R uint8_t RESERVED5[4]; /* 0xAC - 0xAF: Reserved */ - __R uint32_t BURN_IN_TEST4; /* 0xB0: bist test control */ - __R uint32_t BURN_IN_TEST5; /* 0xB4: burn-in test control */ - __R uint32_t BURN_IN_TEST6; /* 0xB8: burn-in test control */ - __R uint8_t RESERVED6[8]; /* 0xBC - 0xC3: Reserved */ - __R uint32_t BURN_IN_TEST9; /* 0xC4: burn-in test control */ - __R uint8_t RESERVED7[8]; /* 0xC8 - 0xCF: Reserved */ - __RW uint32_t DEBUG_INFO; /* 0xD0: debug data control */ - __RW uint32_t DEBUG_CFG_REG0; /* 0xD4: the hardcore interface control in debug mode */ - __RW uint32_t DEBUG_CFG_REG1; /* 0xD8: the hardcore interface control in debug mode */ - __R uint8_t RESERVED8[3126]; /* 0xDC - 0xD11: Reserved */ - __RW uint32_t DEBUG_CFG_REG2; /* 0xD12: the hardcore interface control in debug mode */ - __RW uint32_t DEBUG_CFG_REG3; /* 0xD16: the hardcore interface control in debug mode */ - __R uint8_t RESERVED9[6]; /* 0xD1A - 0xD1F: Reserved */ - __RW uint32_t DEBUG_CFG_REG4; /* 0xD20: the hardcore interface control in debug mode */ - __RW uint32_t DEBUG_CFG_REG5; /* 0xD24: the hardcore interface control in debug mode */ -} MIPI_CSI_PHY_Type; - - -/* Bitfield definition for register: SOFT_RST */ -/* - * HS_CLK_SOFT_RST (RW) - * - * the soft reset of clk_hs domain - */ -#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK (0x2U) -#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT (1U) -#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) -#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) - -/* - * CFG_CLK_SOFT_RST (RW) - * - * the soft reset of clk_cfg domain - */ -#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK (0x1U) -#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT (0U) -#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) -#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) - -/* Bitfield definition for register: PHY_RCAL */ -/* - * RCAL_DONE (RO) - * - * hs-rx terminal trimming done indicator signal - */ -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK (0x20000UL) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT (17U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT) - -/* - * RCAL_OUT (RO) - * - * hs-rx terminal trimming results - */ -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK (0x1E000UL) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT (13U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT) - -/* - * RCAL_CTL (RW) - * - * rcal function control - */ -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK (0x1FE0U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT (5U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) - -/* - * RCAL_TRIM (RW) - * - * default value of HS-RX terminal configure - */ -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK (0x1EU) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT (1U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) - -/* - * RCAL_EN (RW) - * - * enable hs-rx terminal trimming - */ -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK (0x1U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT (0U) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) -#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) - -/* Bitfield definition for register: ULP_RX_EN */ -/* - * CSI_1_ULPRX_EN (RW) - * - * data lane1 ulp-rx receiver enable control - */ -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK (0x80U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT (7U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) - -/* - * CSI_0_ULPRX_EN (RW) - * - * data lane0 ulp-rx receiver enable control - */ -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK (0x40U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT (6U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) - -/* - * CSI_CLK_ULPRX_EN (RW) - * - * clock lane ulp-rx receiver enable control - */ -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK (0x20U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT (5U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) - -/* - * CSI_1_LPRX_EN (RW) - * - * data lane1 lp-rx receiver enable control - */ -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK (0x2U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT (1U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) - -/* - * CSI_CLK_LPRX_EN (RW) - * - * clock lane lp=rx receiver enable control - */ -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK (0x1U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT (0U) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) -#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) - -/* Bitfield definition for register: VOFFCAL_OUT */ -/* - * CSI_CLK_VOFFCAL_DONE (RO) - * - * clock lane hs-rx dc-offset auto-calibration done - */ -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK (0x20000000UL) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT (29U) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT) - -/* - * CSI_CLK_VOFFCAL_OUT (RO) - * - * clock lane hs-rx dc-offset auto-calibration results - */ -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK (0x1F000000UL) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT (24U) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT) - -/* - * CSI_0_VOFFCAL_DONE (RO) - * - * data lane0 hs-rx dc-offset auto-calibration done - */ -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK (0x800000UL) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT (23U) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT) - -/* - * CSI_O_VOFFCAL_OUT (RO) - * - * data lane0 hs-rx dc-offset auto-calibration result - */ -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK (0x7C0000UL) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT (18U) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT) - -/* - * CSI_1_VOFFCAL_DONE (RO) - * - * data lane1 hs-rx dc-offset auto-calibration done - */ -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK (0x20000UL) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT (17U) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT) - -/* - * CSI_1_VOFFCAL_OUT (RO) - * - * data lane1 hs-rx dc-offset auto-calibration result - */ -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK (0x1F000UL) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT (12U) -#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT) - -/* Bitfield definition for register: CSI_CTL01 */ -/* - * CSI_CTL1_7 (RW) - * - * clock lane hs-rx dc-offset auto-calibration enable - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK (0x20000000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT (29U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) - -/* - * CSI_CTL1_6 (RW) - * - * clock lane hs-rx dc-offset trimming control - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK (0x1F000000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT (24U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) - -/* - * CSI_CTL1_5 (RW) - * - * ulprx_vref_trim - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK (0x600000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT (21U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) - -/* - * CSI_CTL1_4 (RW) - * - * bypass hs_rx_voffcal_en - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK (0x100000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT (20U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) - -/* - * CSI_CTL1_3 (RW) - * - * hs_rx_voffcal_trim_polar - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK (0x80000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT (19U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) - -/* - * CSI_CTL1_2 (RW) - * - * ulprx_lpen - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK (0x40000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT (18U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) - -/* - * CSI_CTL1_1 (RW) - * - * force data lane-n and clock lane lp/ulprx to be normal operation - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK (0x20000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT (17U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) - -/* - * CSI_CTL1_0 (RW) - * - * force data lane-n and clock lane hs-rx to be normal operation - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK (0x10000UL) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT (16U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) - -/* - * CSI_CTL0_7 (RW) - * - * clock lane hs-rx dc-offset auto-calibration enable - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK (0x2000U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT (13U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) - -/* - * CSI_CTL0_6 (RW) - * - * clock lane hs-rx dc-offset trimming control - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK (0x1F00U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT (8U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) - -/* - * CSI_CTL0_5 (RW) - * - * ulprx_vref_trim - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK (0x60U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT (5U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) - -/* - * CSI_CTL0_4 (RW) - * - * bypass hs_rx_voffcal_en - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK (0x10U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT (4U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) - -/* - * CSI_CTL0_3 (RW) - * - * hs_rx_voffcal_trim_polar - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK (0x8U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT (3U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) - -/* - * CSI_CTL0_2 (RW) - * - * ulprx_lpen - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK (0x4U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT (2U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) - -/* - * CSI_CTL0_1 (RW) - * - * force data lane-n and clock lane lp/ulprx to be normal operation - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK (0x2U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT (1U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) - -/* - * CSI_CTL0_0 (RW) - * - * force data lane-n and clock lane hs-rx to be normal operation - */ -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK (0x1U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT (0U) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) -#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) - -/* Bitfield definition for register: CSI_CTL23 */ -/* - * CSI_CTL3_3 (RW) - * - * data lane-1 skew trimming enable - */ -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK (0x10000000UL) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT (28U) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) - -/* - * CSI_CTL3_2 (RW) - * - * data lane-1 hs-rx skew adjust with binary code - */ -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK (0xF000000UL) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT (24U) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) - -/* - * CSI_CTL3_1 (RW) - * - * data lane-0 skew trimming enable - */ -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK (0x100000UL) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT (20U) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) - -/* - * CSI_CTL3_0 (RW) - * - * data lane-0 hs-rx skew adjust with binary code - */ -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK (0xF0000UL) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT (16U) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) -#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) - -/* Bitfield definition for register: CSI_VINIT */ -/* - * CSI_LPRX_VREF_TRIM (RW) - * - * pt ft indicator in csi clk data lane - */ -#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK (0xF00000UL) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT (20U) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) - -/* - * CSI_CLK_LPRX_VINT (RO) - * - * pt ft indicator in csi clk lane - */ -#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK (0xF0000UL) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT (16U) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT) - -/* - * CSI_1_LPRX_VINIT (RO) - * - * pt ft indicator in csi lane-1 - */ -#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK (0xF0U) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT (4U) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT) - -/* - * CSI_0_LPRX_VINIT (RO) - * - * pt ft indicator in csi lane-0 - */ -#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK (0xFU) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT (0U) -#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT) - -/* Bitfield definition for register: CLANE_PARA */ -/* - * T_CLK_TERMEN (RW) - * - * time for the clock lane receiver to enable the HS line termination - */ -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK (0xFF00U) -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT (8U) -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) - -/* - * T_CLK_SETTLE (RW) - * - * the value of tclk-settle of clklane - */ -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK (0xFFU) -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT (0U) -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) -#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) - -/* Bitfield definition for register: T_HS_TERMEN */ -/* - * T_D1_TERMEN (RW) - * - * the value of ths-termen of datalane1 - */ -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK (0xFF00U) -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT (8U) -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) - -/* - * T_D0_TERMEN (RW) - * - * the value of ths-termen of datalane0 - */ -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK (0xFFU) -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT (0U) -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) -#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) - -/* Bitfield definition for register: T_HS_SETTLE */ -/* - * T_D1_SETTLE (RW) - * - * the value of ths-settle of data lane1 - */ -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK (0xFF00U) -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT (8U) -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) - -/* - * T_D0_SETTLE (RW) - * - * the value of ths-settle of data lane0 - */ -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK (0xFFU) -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT (0U) -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) -#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) - -/* Bitfield definition for register: T_CLANE_INIT */ -/* - * T_CLK_INIT (RW) - * - * initialization time of lock lane - */ -#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK (0xFFFFFFUL) -#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT (0U) -#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) -#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) >> MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) - -/* Bitfield definition for register: T_LANE_INIT0 */ -/* - * T_D0_INIT (RW) - * - * initialization time of data lane - */ -#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK (0xFFFFFFUL) -#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT (0U) -#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) -#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) - -/* Bitfield definition for register: T_LANE_INIT1 */ -/* - * T_D1_INIT (RW) - * - * initialization time of data lane - */ -#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK (0xFFFFFFUL) -#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT (0U) -#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) -#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) - -/* Bitfield definition for register: TLPX_CTRL */ -/* - * EN_TLPX_CHECK (RW) - * - * enable the tlpx width check - */ -#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK (0x100U) -#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT (8U) -#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) -#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) - -/* - * TLPX (RW) - * - * the width of tlpx - */ -#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK (0xFFU) -#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT (0U) -#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) -#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) - -/* Bitfield definition for register: NE_SWAP */ -/* - * DPDN_SWAP_LANE1 (RW) - * - * datalane1 dpdn swap - */ -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK (0x200U) -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT (9U) -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) - -/* - * DPDN_SWAP_LAN0 (RW) - * - * datalane0 dpdn swap - */ -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK (0x100U) -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT (8U) -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) -#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) - -/* - * LANE_SWAP_LAN1 (RW) - * - * data lane1 swap - */ -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK (0xCU) -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT (2U) -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) - -/* - * LANE_SWAP_LANE0 (RW) - * - * data lane0 swap - */ -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK (0x3U) -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT (0U) -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) -#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) - -/* Bitfield definition for register: MISC_INFO */ -/* - * ULPS_LP10_SEL (RW) - * - * the lp10 select signal in ulps_exit state - */ -#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK (0x2U) -#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT (1U) -#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) -#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) >> MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) - -/* - * LONG_SOTSYNC_EN (RW) - * - * at least six zero is checked before sot swquence "00011101" - */ -#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK (0x1U) -#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT (0U) -#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) -#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) >> MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) - -/* Bitfield definition for register: BIST_TEST0 */ -/* - * BIST_DONE_LAN1 (RO) - * - * bist_done of lane1 - */ -#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK (0x80U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT (7U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT) - -/* - * BIST_DONE_LAN0 (RO) - * - * bist_done of lane0 - */ -#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK (0x40U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT (6U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT) - -/* - * BIST_OK_LANE1 (RO) - * - * bist_ok of lane1 - */ -#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK (0x8U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT (3U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT) - -/* - * BIST_OK_LANE0 (RO) - * - * bist_ok of lane0 - */ -#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK (0x4U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT (2U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT) - -/* - * BIST_EN_SEL (RW) - * - * the source of bist_en sel - */ -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK (0x2U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT (1U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) - -/* - * BIST_EN_SOFT (RW) - * - * enable prbs bist test - */ -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK (0x1U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT (0U) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) -#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) - -/* Bitfield definition for register: BIST_TEST1 */ -/* - * PRBS_CHECK_NUM (RW) - * - * the byte num of prbs bist check num - */ -#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT (0U) -#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) -#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) >> MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) - -/* Bitfield definition for register: BIST_TEST2 */ -/* - * PRBS_SEED (RW) - * - * the seed of prbs7 - */ -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK (0xFF0000UL) -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT (16U) -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) - -/* - * PRBS_ERR_THRESHOLD (RW) - * - * the threshold of prbs bist error - */ -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK (0xFFFFU) -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT (0U) -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) -#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) - -/* Bitfield definition for register: BIST_TEST3 */ -/* - * PRBS_ERR_NUM_LAN1 (RO) - * - * the byte num of mismatch data of data lane1 in bist mode - */ -#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK (0xFFFF0000UL) -#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT (16U) -#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT) - -/* - * PRBS_ERR_NUM_LAN0 (RO) - * - * the byte num of mismatch data of data lane0 in bist mode - */ -#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK (0xFFFFU) -#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT (0U) -#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST0 */ -/* - * BURN_IN_OK_CLAN (RO) - * - * burn_in_ok of clock lane - */ -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK (0x40U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT (6U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT) - -/* - * BURN_IN_OK_LAN1 (RO) - * - * burn_in_ok of lane1 - */ -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK (0x8U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT (3U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT) - -/* - * BURN_IN_OK_LAN0 (RO) - * - * burn_in_ok of lane0 - */ -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK (0x4U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT (2U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT) - -/* - * BURN_IN_EN_SEL (RW) - * - * the source of prbs burn_in_en sel - */ -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK (0x2U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT (1U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) - -/* - * BURN_IN_EN_SOFT (RW) - * - * enable prbs burn_in test - */ -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK (0x1U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) -#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST1 */ -/* - * BURN_IN_SEED (RW) - * - * the seed of prbs7 for brun-in test - */ -#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK (0xFFU) -#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) -#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST2 */ -/* - * BURN_IN_ERR_NUM_LAN1 (RO) - * - * the bit num of mismatch data on data lan1 in burn-in mode - */ -#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK (0xFFFF0000UL) -#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT (16U) -#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT) - -/* - * BURN_IN_ERR_NUM_LAN0 (RO) - * - * the bit num of mismatch data on data lan0 in burn-in mode - */ -#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK (0xFFFFU) -#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST4 */ -/* - * BURN_IN_ERR_NUM_CLAN (RO) - * - * the bit num of mismatch data on clock lane in burn-in mode - */ -#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK (0xFFFFU) -#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST5 */ -/* - * BURN_IN_CHECK_NUM_LAN0 (RO) - * - * the checked bit num of lane0 - */ -#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST6 */ -/* - * BURN_IN_CHECKED_NUM_LAN1 (RO) - * - * the checked bit num of lane1 - */ -#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT) - -/* Bitfield definition for register: BURN_IN_TEST9 */ -/* - * BURN_IN_CHECK_NUM_CLAN (RO) - * - * the checked bit num of clock lane - */ -#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT (0U) -#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT) - -/* Bitfield definition for register: DEBUG_INFO */ -/* - * DEBUG_MODE_SEL (RW) - * - * the debug bus sel - */ -#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK (0x3F0000UL) -#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT (16U) -#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) -#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) >> MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) - -/* Bitfield definition for register: DEBUG_CFG_REG0 */ -/* - * DEBUG_CFG_REG0 (RW) - * - * debug config register0 - */ -#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT (0U) -#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) -#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) - -/* Bitfield definition for register: DEBUG_CFG_REG1 */ -/* - * DEBUG_CFG_REG1 (RW) - * - * debug config register1 - */ -#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT (0U) -#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) -#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) - -/* Bitfield definition for register: DEBUG_CFG_REG2 */ -/* - * DEBUG_CFG_REG2 (RW) - * - * debug config register2 - */ -#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT (0U) -#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) -#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) - -/* Bitfield definition for register: DEBUG_CFG_REG3 */ -/* - * DEBUG_CFG_REG3 (RW) - * - * debug config register3 - */ -#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT (0U) -#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) -#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) - -/* Bitfield definition for register: DEBUG_CFG_REG4 */ -/* - * DEBUG_CFG_REG4 (RW) - * - * debug config register4 - */ -#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT (0U) -#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) -#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) - -/* Bitfield definition for register: DEBUG_CFG_REG5 */ -/* - * DEBUG_CFG_REG5 (RW) - * - * debug config register5 - */ -#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT (0U) -#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) -#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) - - - - -#endif /* HPM_MIPI_CSI_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_csi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_csi_regs.h deleted file mode 100644 index efe70076c46..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_csi_regs.h +++ /dev/null @@ -1,3618 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MIPI_CSI_H -#define HPM_MIPI_CSI_H - -typedef struct { - __R uint32_t VERSION; /* 0x0: version code */ - __RW uint32_t N_LANES; /* 0x4: the number of active lanes */ - __RW uint32_t CSI2_RESETN; /* 0x8: the internal logic of the controller goes into the reset state when active */ - __R uint32_t INT_ST_MAIN; /* 0xC: contains the stateus of individual interrupt sources */ - __RW uint32_t DATA_IDS_1; /* 0x10: programs data type fields for data ID monitors */ - __RW uint32_t DATA_IDS_2; /* 0x14: programs data type fields for data ID monitors */ - __R uint8_t RESERVED0[20]; /* 0x18 - 0x2B: Reserved */ - __R uint32_t INT_ST_AP_MAIN; /* 0x2C: contains the status of individual interrupt sources */ - __R uint8_t RESERVED1[16]; /* 0x30 - 0x3F: Reserved */ - __RW uint32_t PHY_SHUTDOWNZ; /* 0x40: controls the phy shutdown mode */ - __RW uint32_t DPHY_RSTZ; /* 0x44: controls the phy reset mode */ - __R uint32_t PHY_RX; /* 0x48: contains the status of rx-related signals from phy */ - __R uint32_t PHY_STOPSTATE; /* 0x4C: contains the stopstate signal status from phy */ - __R uint8_t RESERVED2[48]; /* 0x50 - 0x7F: Reserved */ - __RW uint32_t IPI_MODE; /* 0x80: selects how the ipi interface generates the video frame */ - __RW uint32_t IPI_VCID; /* 0x84: selects the vritual channel processed by ipi */ - __RW uint32_t IPI_DATA_TYPE; /* 0x88: selects the data type processed by ipi */ - __RW uint32_t IPI_MEM_FLASH; /* 0x8C: control the flush of ipi memory */ - __RW uint32_t IPI_HSA_TIME; /* 0x90: configures the video horizontal synchronism active time */ - __RW uint32_t IPI_HBP_TIME; /* 0x94: configures the video horizontal synchronism back porch time */ - __RW uint32_t IPI_HSD_TIME; /* 0x98: configures the vedeo Horizontal Sync Delay time */ - __RW uint32_t IPI_HLINE_TIME; /* 0x9C: configures the overall tiem for each video line */ - __RW uint32_t IPI_SOFTRSTN; /* 0xA0: congtrols the ipi logic reset state */ - __R uint8_t RESERVED3[8]; /* 0xA4 - 0xAB: Reserved */ - __RW uint32_t IPI_ADV_FEATURES; /* 0xAC: configures advanced features for ipi mode */ - __RW uint32_t IPI_VSA_LINES; /* 0xB0: configures the vertical synchronism active period */ - __RW uint32_t IPI_VBP_LINES; /* 0xB4: configures the verticall back porch period */ - __RW uint32_t IPI_VFP_LINES; /* 0xB8: configures the vertical front porch period */ - __RW uint32_t IPI_VACTIVE_LINES; /* 0xBC: configures the vertical resolution of video */ - __R uint8_t RESERVED4[8]; /* 0xC0 - 0xC7: Reserved */ - __RW uint32_t VC_EXTENSION; /* 0xC8: active extra bits for virtual channel */ - __R uint32_t PHY_CAL; /* 0xCC: contains the calibration signal status from synopsys d-phy */ - __R uint8_t RESERVED5[16]; /* 0xD0 - 0xDF: Reserved */ - __R uint32_t INT_ST_PHY_FATAL; /* 0xE0: groups the phy interruptions caused by phy packets discarded */ - __RW uint32_t INT_MSK_PHY_FATAL; /* 0xE4: interrupt mask for int_st_phy_fatal */ - __RW uint32_t INT_FORCE_PHY_FATAL; /* 0xE8: interrupt force register for test purposes */ - __R uint8_t RESERVED6[4]; /* 0xEC - 0xEF: Reserved */ - __R uint32_t INT_ST_PKT_FATAL; /* 0xF0: groups the fatal interruption related with packet construction */ - __RW uint32_t INT_MSK_PKT_FATAL; /* 0xF4: interrupt mask for int_st_pkt_fatal */ - __RW uint32_t INT_FORCE_PKT_FATAL; /* 0xF8: interrupt force register is used for test purpos */ - __R uint8_t RESERVED7[20]; /* 0xFC - 0x10F: Reserved */ - __R uint32_t INT_ST_PHY; /* 0x110: interruption caused by phy */ - __RW uint32_t INT_MSK_PHY; /* 0x114: interrupt mask for int_st_phy */ - __RW uint32_t INT_FORCE_PHY; /* 0x118: interrupt force register */ - __R uint8_t RESERVED8[36]; /* 0x11C - 0x13F: Reserved */ - __R uint32_t INT_ST_IPI_FATAL; /* 0x140: fatal interruption caused by ipi interface */ - __RW uint32_t INT_MSK_IPI_FATAL; /* 0x144: interrupt mask for int_st_ipi_fatal */ - __RW uint32_t INT_FORCE_IPI_FATAL; /* 0x148: interrupt force register */ - __R uint8_t RESERVED9[52]; /* 0x14C - 0x17F: Reserved */ - __R uint32_t INT_ST_AP_GENERIC; /* 0x180: groups and notifies which interruption bits caused the interruption */ - __RW uint32_t INT_MSK_AP_GENERIC; /* 0x184: interrupt mask for int_st_ap_generic */ - __RW uint32_t INT_FORCE_AP_GENERIC; /* 0x188: interrupt force register used for test purposes */ - __R uint8_t RESERVED10[4]; /* 0x18C - 0x18F: Reserved */ - __R uint32_t INT_ST_AP_IPI_FATAL; /* 0x190: groups and notifies which interruption bits */ - __R uint32_t INT_MSK_AP_IPI_FATAL; /* 0x194: interrupt mask for int_st_ap_ipi_fatal controls */ - __R uint32_t INT_FORCE_AP_IPI_FATAL; /* 0x198: interrupt force register */ - __R uint8_t RESERVED11[228]; /* 0x19C - 0x27F: Reserved */ - __R uint32_t INT_ST_BNDRY_FRAME_FATAL; /* 0x280: fatal interruption related with matching frame start with frame end for a specific virtual channel */ - __RW uint32_t INT_MSK_BNDRY_FRAME_FATAL; /* 0x284: interrupt mask for int_st_bndry_frame_fatal */ - __RW uint32_t INT_FORCE_BNDRY_FRAME_FATAL; /* 0x288: interrupt force register is used for test purposes */ - __R uint8_t RESERVED12[4]; /* 0x28C - 0x28F: Reserved */ - __R uint32_t INT_ST_SEQ_FRAME_FATAL; /* 0x290: fatal interruption related with matching frame start with frame end for a specific virtual channel */ - __RW uint32_t INT_MSK_SEQ_FRAME_FATAL; /* 0x294: interrupt mask for int_st_seq_frame_fatal */ - __RW uint32_t INT_FORCE_SEQ_FRAME_FATAL; /* 0x298: interrupt force register is used for test purposes */ - __R uint8_t RESERVED13[4]; /* 0x29C - 0x29F: Reserved */ - __R uint32_t INT_ST_CRC_FRAME_FATAL; /* 0x2A0: fatal interruption related with matching frame start with frame end for a specific virtual channel */ - __RW uint32_t INT_MSK_CRC_FRAME_FATAL; /* 0x2A4: interrupt mask for int_st_crc_frame_fatal */ - __RW uint32_t INT_FORCE_CRC_FRAME_FATAL; /* 0x2A8: interrupt force register is used for test purposes */ - __R uint8_t RESERVED14[4]; /* 0x2AC - 0x2AF: Reserved */ - __R uint32_t INT_ST_PLD_CRC_FRAME_FATAL; /* 0x2B0: fatal interruption related with matching frame start with frame end for a specific virtual channel */ - __RW uint32_t INT_MSK_PLD_CRC_FRAME_FATAL; /* 0x2B4: interrupt mask for int_st_crc_frame_fatal */ - __RW uint32_t INT_FORCE_PLD_CRC_FRAME_FATAL; /* 0x2B8: interrupt force register is used for test purposes */ -} MIPI_CSI_Type; - - -/* Bitfield definition for register: VERSION */ -/* - * VERSION (RO) - * - * version code - */ -#define MIPI_CSI_VERSION_VERSION_MASK (0xFFFFFFFFUL) -#define MIPI_CSI_VERSION_VERSION_SHIFT (0U) -#define MIPI_CSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_CSI_VERSION_VERSION_MASK) >> MIPI_CSI_VERSION_VERSION_SHIFT) - -/* Bitfield definition for register: N_LANES */ -/* - * N_LANES (RW) - * - * number of active data lanes - */ -#define MIPI_CSI_N_LANES_N_LANES_MASK (0x7U) -#define MIPI_CSI_N_LANES_N_LANES_SHIFT (0U) -#define MIPI_CSI_N_LANES_N_LANES_SET(x) (((uint32_t)(x) << MIPI_CSI_N_LANES_N_LANES_SHIFT) & MIPI_CSI_N_LANES_N_LANES_MASK) -#define MIPI_CSI_N_LANES_N_LANES_GET(x) (((uint32_t)(x) & MIPI_CSI_N_LANES_N_LANES_MASK) >> MIPI_CSI_N_LANES_N_LANES_SHIFT) - -/* Bitfield definition for register: CSI2_RESETN */ -/* - * CSI2_RESETN (RW) - * - * DWC_mipi_csi2_host reset output, active low - */ -#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK (0x1U) -#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT (0U) -#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SET(x) (((uint32_t)(x) << MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT) & MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK) -#define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_GET(x) (((uint32_t)(x) & MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK) >> MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT) - -/* Bitfield definition for register: INT_ST_MAIN */ -/* - * STATUS_INT_IPI4_FATAL (RC) - * - * status of int_st_ipi_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_MASK (0x40000UL) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_SHIFT (18U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_SHIFT) - -/* - * STATUS_INT_LINE (RC) - * - * status of int_st_line - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_MASK (0x20000UL) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_SHIFT (17U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_SHIFT) - -/* - * STATUS_INT_PHY (RC) - * - * status of int_st_phy - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_MASK (0x10000UL) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_SHIFT (16U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_SHIFT) - -/* - * STATUS_INT_ECC_CORRECTED (RC) - * - * status of status_int_ecc_corrected - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_MASK (0x80U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT (7U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT) - -/* - * STATUS_INT_DATA_ID (RC) - * - * status of status_int_data_id - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_MASK (0x40U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_SHIFT (6U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_SHIFT) - -/* - * STATUS_INT_PLD_CRC_FATAL (RC) - * - * status of status_int_pld_crc_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK (0x20U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT (5U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT) - -/* - * STATUS_INT_CRC_FRAME_FATAL (RC) - * - * status of status_int_crc_frame_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK (0x10U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT (4U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT) - -/* - * STATUS_INT_SEQ_FRAME_FATAL (RC) - * - * status of status_int_seq_frame_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK (0x8U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT (3U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT) - -/* - * STATUS_INT_BNDRY_FRAME_FATAL (RC) - * - * status of int_st_bndry_frame_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK (0x4U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT (2U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT) - -/* - * STATUS_INT_PKT_FATAL (RC) - * - * status of int_st_pkt_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_MASK (0x2U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_SHIFT (1U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_SHIFT) - -/* - * STATUS_INT_PHY_FATAL (RC) - * - * status of int_st_phy_fatal - */ -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_MASK (0x1U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_SHIFT (0U) -#define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_SHIFT) - -/* Bitfield definition for register: DATA_IDS_1 */ -/* - * DI3_DT (RW) - * - * data type for programmed data ID 3 - */ -#define MIPI_CSI_DATA_IDS_1_DI3_DT_MASK (0x3F000000UL) -#define MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT (24U) -#define MIPI_CSI_DATA_IDS_1_DI3_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI3_DT_MASK) -#define MIPI_CSI_DATA_IDS_1_DI3_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI3_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT) - -/* - * DI2_DT (RW) - * - * data type for programmed data ID 2 - */ -#define MIPI_CSI_DATA_IDS_1_DI2_DT_MASK (0x3F0000UL) -#define MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT (16U) -#define MIPI_CSI_DATA_IDS_1_DI2_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI2_DT_MASK) -#define MIPI_CSI_DATA_IDS_1_DI2_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI2_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT) - -/* - * DI1_DT (RW) - * - * data type for programmed data ID 1 - */ -#define MIPI_CSI_DATA_IDS_1_DI1_DT_MASK (0x3F00U) -#define MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT (8U) -#define MIPI_CSI_DATA_IDS_1_DI1_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI1_DT_MASK) -#define MIPI_CSI_DATA_IDS_1_DI1_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI1_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT) - -/* - * DI0_DT (RW) - * - * data type for programmed data ID 0 - */ -#define MIPI_CSI_DATA_IDS_1_DI0_DT_MASK (0x3FU) -#define MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT (0U) -#define MIPI_CSI_DATA_IDS_1_DI0_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI0_DT_MASK) -#define MIPI_CSI_DATA_IDS_1_DI0_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI0_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT) - -/* Bitfield definition for register: DATA_IDS_2 */ -/* - * DI7_DT (RW) - * - * data type for programmed data ID 7 - */ -#define MIPI_CSI_DATA_IDS_2_DI7_DT_MASK (0x3F000000UL) -#define MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT (24U) -#define MIPI_CSI_DATA_IDS_2_DI7_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI7_DT_MASK) -#define MIPI_CSI_DATA_IDS_2_DI7_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI7_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT) - -/* - * DI6_DT (RW) - * - * data type for programmed data ID 6 - */ -#define MIPI_CSI_DATA_IDS_2_DI6_DT_MASK (0x3F0000UL) -#define MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT (16U) -#define MIPI_CSI_DATA_IDS_2_DI6_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI6_DT_MASK) -#define MIPI_CSI_DATA_IDS_2_DI6_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI6_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT) - -/* - * DI5_DT (RW) - * - * data type for programmed data ID 5 - */ -#define MIPI_CSI_DATA_IDS_2_DI5_DT_MASK (0x3F00U) -#define MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT (8U) -#define MIPI_CSI_DATA_IDS_2_DI5_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI5_DT_MASK) -#define MIPI_CSI_DATA_IDS_2_DI5_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI5_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT) - -/* - * DI4_DT (RW) - * - * data type for programmed data ID 4 - */ -#define MIPI_CSI_DATA_IDS_2_DI4_DT_MASK (0x3FU) -#define MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT (0U) -#define MIPI_CSI_DATA_IDS_2_DI4_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI4_DT_MASK) -#define MIPI_CSI_DATA_IDS_2_DI4_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI4_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT) - -/* Bitfield definition for register: INT_ST_AP_MAIN */ -/* - * STATUS_INT_IPI_FATAL (RC) - * - * status of int_st_ipi_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_MASK (0x1000U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_SHIFT (12U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_SHIFT) - -/* - * STATUS_INT_ST_AP_IPI_FATAL (RC) - * - * status of int_st_ap_ipi_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_MASK (0x800U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_SHIFT (11U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_SHIFT) - -/* - * STATUS_INT_LINE (RC) - * - * status of int_st_line - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_MASK (0x400U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_SHIFT (10U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_SHIFT) - -/* - * STATUS_INT_ECC_CORRECTED (RC) - * - * status of status_int_ecc_corrected - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_MASK (0x200U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT (9U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT) - -/* - * STATUS_INT_DATA_ID (RC) - * - * status of status_int_data_id - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_MASK (0x100U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_SHIFT (8U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_SHIFT) - -/* - * STATUS_INT_PLD_CRC_FATAL (RC) - * - * status of status_int_pld_crc_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK (0x80U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT (7U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT) - -/* - * STATUS_INT_PHY (RC) - * - * status of int_st_phy - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_MASK (0x40U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_SHIFT (6U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_SHIFT) - -/* - * STATUS_INT_CRC_FRAME_FATAL (RC) - * - * status of status_int_crc_frame_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK (0x20U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT (5U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT) - -/* - * STATUS_INT_SEQ_FRAME_FATAL (RC) - * - * status of status_int_seq_frame_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK (0x10U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT (4U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT) - -/* - * STATUS_INT_BNDRY_FRAME_FATAL (RC) - * - * status of int_st_bndry_frame_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK (0x8U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT (3U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT) - -/* - * STATUS_INT_PKT_FATAL (RC) - * - * status of int_st_pkt_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_MASK (0x4U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_SHIFT (2U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_SHIFT) - -/* - * STATUS_INT_PHY_FATAL (RC) - * - * status of int_st_phy_fatal - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_MASK (0x2U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_SHIFT (1U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_SHIFT) - -/* - * STATUS_INT_ST_AP_GENERIC (RC) - * - * status of int_st_ap_generic - */ -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_MASK (0x1U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_SHIFT (0U) -#define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_SHIFT) - -/* Bitfield definition for register: PHY_SHUTDOWNZ */ -/* - * PHY_SHUTDOWNZ (RW) - * - * shutdown input,active low - */ -#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK (0x1U) -#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT (0U) -#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK) -#define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK) >> MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT) - -/* Bitfield definition for register: DPHY_RSTZ */ -/* - * DPHY_RSTZ (RW) - * - * phy reset output, active low - */ -#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK (0x1U) -#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT (0U) -#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT) & MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK) -#define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK) >> MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT) - -/* Bitfield definition for register: PHY_RX */ -/* - * PHY_RXCLKACTIVEHS (RO) - * - * indicates the d-phy clock lane is actively receiving a ddr clock - */ -#define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK (0x20000UL) -#define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_SHIFT (17U) -#define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK) >> MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_SHIFT) - -/* - * PHY_RXULPSCLKNOT (RO) - * - * active low. Indicates the d-phy clock lane module has entered the Ultra low power state - */ -#define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_MASK (0x10000UL) -#define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_SHIFT (16U) -#define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_SHIFT) - -/* - * PHY_RXULLPSESC_1 (RO) - * - * lane module 1 has entered the ultra low power mode - */ -#define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_MASK (0x2U) -#define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_SHIFT (1U) -#define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_SHIFT) - -/* - * PHY_RXULPSESC_0 (RO) - * - * lane module 0 has entered the ultra low power mode - */ -#define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_MASK (0x1U) -#define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_SHIFT (0U) -#define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_SHIFT) - -/* Bitfield definition for register: PHY_STOPSTATE */ -/* - * PHY_STOPSTATECLK (RO) - * - * d-phy clock lane in stop state - */ -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_MASK (0x10000UL) -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_SHIFT (16U) -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_SHIFT) - -/* - * PHY_STOPSTATEDATA_1 (RO) - * - * data lane 1 in stop state - */ -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_MASK (0x2U) -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_SHIFT (1U) -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_SHIFT) - -/* - * PHY_STOPSTATEDATA_0 (RO) - * - * data lane 0 in stop state - */ -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_MASK (0x1U) -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_SHIFT (0U) -#define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_SHIFT) - -/* Bitfield definition for register: IPI_MODE */ -/* - * IPI_ENABLE (RW) - * - * enables the interface - */ -#define MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK (0x1000000UL) -#define MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT (24U) -#define MIPI_CSI_IPI_MODE_IPI_ENABLE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT) & MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK) -#define MIPI_CSI_IPI_MODE_IPI_ENABLE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK) >> MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT) - -/* - * IPI_CUT_THROUGH (RW) - * - * cut-through mode state active when high - */ -#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK (0x10000UL) -#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT (16U) -#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT) & MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK) -#define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK) >> MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT) - -/* - * IPI_COLOR_COM (RW) - * - * if color mode components are deliverd as follows: 0x0 48bit intercase 0x1: 16bit interface - */ -#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK (0x100U) -#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT (8U) -#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT) & MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK) -#define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK) >> MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT) - -/* - * IPI_MODE (RW) - * - * indicates the video mode transmission type 0x0: camera timing 0x1:controller timing - */ -#define MIPI_CSI_IPI_MODE_IPI_MODE_MASK (0x1U) -#define MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT (0U) -#define MIPI_CSI_IPI_MODE_IPI_MODE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT) & MIPI_CSI_IPI_MODE_IPI_MODE_MASK) -#define MIPI_CSI_IPI_MODE_IPI_MODE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_MODE_MASK) >> MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT) - -/* Bitfield definition for register: IPI_VCID */ -/* - * IPI_VCX_0_1 (RW) - * - * virtual channel extension of data to be processed by pixel interface - */ -#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK (0xCU) -#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT (2U) -#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT) & MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK) -#define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK) >> MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT) - -/* - * IP_VCID (RW) - * - * virtual channel of data to be processed by pixel interface - */ -#define MIPI_CSI_IPI_VCID_IP_VCID_MASK (0x3U) -#define MIPI_CSI_IPI_VCID_IP_VCID_SHIFT (0U) -#define MIPI_CSI_IPI_VCID_IP_VCID_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VCID_IP_VCID_SHIFT) & MIPI_CSI_IPI_VCID_IP_VCID_MASK) -#define MIPI_CSI_IPI_VCID_IP_VCID_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VCID_IP_VCID_MASK) >> MIPI_CSI_IPI_VCID_IP_VCID_SHIFT) - -/* Bitfield definition for register: IPI_DATA_TYPE */ -/* - * EMBENDED_DATA (RW) - * - * enable embedded data processing on ipi interface - */ -#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK (0x100U) -#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT (8U) -#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT) & MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK) -#define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK) >> MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT) - -/* - * IPI_DATA_TYPE (RW) - * - * data type of data to be processed by pixel interface - */ -#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK (0x3FU) -#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT (0U) -#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT) & MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK) -#define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK) >> MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT) - -/* Bitfield definition for register: IPI_MEM_FLASH */ -/* - * IPI_AUTO_FLUSH (RW) - * - * memory is automatically flashed at each vsync - */ -#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK (0x100U) -#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT (8U) -#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT) & MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK) -#define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK) >> MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT) - -/* - * IPI_FLUSH (RW) - * - * flush ipi memory, this bit is auto clear - */ -#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK (0x1U) -#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT (0U) -#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT) & MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK) -#define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK) >> MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT) - -/* Bitfield definition for register: IPI_HSA_TIME */ -/* - * IPI_HSA_TIME (RW) - * - * configures the Horizontal Synchronism Active period in pixclk cycles - */ -#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK (0xFFFU) -#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT (0U) -#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT) & MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK) -#define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK) >> MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT) - -/* Bitfield definition for register: IPI_HBP_TIME */ -/* - * IPI_HBP_TIME (RW) - * - * configures the Horizontal Synchronism back porch period in pixclk cycles - */ -#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK (0xFFFU) -#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT (0U) -#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT) & MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK) -#define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK) >> MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT) - -/* Bitfield definition for register: IPI_HSD_TIME */ -/* - * IPI_HSD_TIME (RW) - * - * configures the Horizontal Sync Porch delay period in pixclk cycles - */ -#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK (0xFFFU) -#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT (0U) -#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT) & MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK) -#define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK) >> MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT) - -/* Bitfield definition for register: IPI_HLINE_TIME */ -/* - * IPI_HLIN_TIME (RW) - * - * configures the size of the line time counted in pixclk cycles - */ -#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK (0x7FFFU) -#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT (0U) -#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT) & MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK) -#define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK) >> MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT) - -/* Bitfield definition for register: IPI_SOFTRSTN */ -/* - * IPI_SOFTRSTN (RW) - * - * resets ipi one, active low - */ -#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK (0x1U) -#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT (0U) -#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT) & MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK) -#define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK) >> MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT) - -/* Bitfield definition for register: IPI_ADV_FEATURES */ -/* - * IPI_SYNC_EVENT_MODE (RW) - * - * for camera mode: 0x0- frame start do not trigger any sync event - */ -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK (0x1000000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT (24U) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT) - -/* - * EN_EMBEDDED (RW) - * - * allows the use of embendded packets for ipi synchronization events - */ -#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK (0x200000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT (21U) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT) - -/* - * EN_BLANKING (RW) - * - * allows the use of blankong packets for IPI synchronization events - */ -#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK (0x100000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT (20U) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT) - -/* - * EN_NULL (RW) - * - * allows the use of null packets for IPI synchronization events - */ -#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK (0x80000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT (19U) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT) - -/* - * EN_LINE_START (RW) - * - * allows the use of line start packets for ipi synchronization events - */ -#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK (0x40000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT (18U) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT) - -/* - * EN_VIDEO (RW) - * - * allows the use of video packets for ipi synchronization events - */ -#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK (0x20000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT (17U) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT) - -/* - * LINE_EVENT_SELECTION (RW) - * - * for camero mode, allows manual selection of the packet fo line delimiter as follows: 0x0-controller seletc it automaticlly 0x1-select packets from list programmed in 17:21 - */ -#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK (0x10000UL) -#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT (16U) -#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT) - -/* - * IPI_DT (RW) - * - * datatype to overwrite - */ -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK (0x3F00U) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT (8U) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT) - -/* - * IPI_DT_OVERWRITE (RW) - * - * ignore datatype of the header using the programmed datatype for decoding - */ -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK (0x1U) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT (0U) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK) -#define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT) - -/* Bitfield definition for register: IPI_VSA_LINES */ -/* - * IPI_VSA_LINES (RW) - * - * configures the vertical synchronism active period measured in number of horizontal lines - */ -#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK (0x3FFU) -#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT (0U) -#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT) & MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK) -#define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK) >> MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT) - -/* Bitfield definition for register: IPI_VBP_LINES */ -/* - * IPI_VBP_LINES (RW) - * - * configuress the vertical back porch period measured in number of horizontal lines - */ -#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK (0x3FFU) -#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT (0U) -#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT) & MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK) -#define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK) >> MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT) - -/* Bitfield definition for register: IPI_VFP_LINES */ -/* - * IPI_VFP_LINES (RW) - * - * configures the vertical front porch period measured in number of horizontall lines - */ -#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK (0x3FFU) -#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT (0U) -#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT) & MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK) -#define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK) >> MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT) - -/* Bitfield definition for register: IPI_VACTIVE_LINES */ -/* - * IPI_VACTIVE_LINES (RW) - * - * configures the vertical active period measured in bumber of horizontal lines - */ -#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK (0x3FFFU) -#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT (0U) -#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT) & MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK) -#define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK) >> MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT) - -/* Bitfield definition for register: VC_EXTENSION */ -/* - * VCX (RW) - * - * indicates status of virtual channel extension: 0-virtual channel extension is enable 1-legacy mode - */ -#define MIPI_CSI_VC_EXTENSION_VCX_MASK (0x1U) -#define MIPI_CSI_VC_EXTENSION_VCX_SHIFT (0U) -#define MIPI_CSI_VC_EXTENSION_VCX_SET(x) (((uint32_t)(x) << MIPI_CSI_VC_EXTENSION_VCX_SHIFT) & MIPI_CSI_VC_EXTENSION_VCX_MASK) -#define MIPI_CSI_VC_EXTENSION_VCX_GET(x) (((uint32_t)(x) & MIPI_CSI_VC_EXTENSION_VCX_MASK) >> MIPI_CSI_VC_EXTENSION_VCX_SHIFT) - -/* Bitfield definition for register: PHY_CAL */ -/* - * RXSKEWCALHS (RC) - * - * a low-to-high transition on rxskewcalhs signal means the the phy has initiated the de-skew calibration - */ -#define MIPI_CSI_PHY_CAL_RXSKEWCALHS_MASK (0x1U) -#define MIPI_CSI_PHY_CAL_RXSKEWCALHS_SHIFT (0U) -#define MIPI_CSI_PHY_CAL_RXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CAL_RXSKEWCALHS_MASK) >> MIPI_CSI_PHY_CAL_RXSKEWCALHS_SHIFT) - -/* Bitfield definition for register: INT_ST_PHY_FATAL */ -/* - * ERR_DESKEW (RC) - * - * reports whenever data is lost due to an existent skew between lanes greater than 2 rxwordclkhs - */ -#define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_MASK (0x100U) -#define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_SHIFT (8U) -#define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_SHIFT) - -/* - * PHY_ERRSOTSYNCHS_1 (RC) - * - * start of transmission error on data lane1 - */ -#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_MASK (0x2U) -#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_SHIFT (1U) -#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_SHIFT) - -/* - * PHY_ERRSOTSYNCHS_0 (RC) - * - * start of transmission error on data lane0 - */ -#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_MASK (0x1U) -#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_SHIFT (0U) -#define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_SHIFT) - -/* Bitfield definition for register: INT_MSK_PHY_FATAL */ -/* - * ERR_DESKEW (RW) - * - * mask for err_deskew - */ -#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK (0x100U) -#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT (8U) -#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK) -#define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT) - -/* - * MASK_PHY_ERRSOTSYNCHS_1 (RW) - * - * mask for phy_errsotsynchs_1 - */ -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK (0x2U) -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT (1U) -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK) -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT) - -/* - * MASK_PHY_ERRSOTSYNCHS_0 (RW) - * - * mask for phy_errsotsynchs_0 - */ -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK (0x1U) -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT (0U) -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK) -#define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT) - -/* Bitfield definition for register: INT_FORCE_PHY_FATAL */ -/* - * ERR_DESKEW (RW) - * - * force err_deskew - */ -#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK (0x100U) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT (8U) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT) - -/* - * FORCE_PHY_ERRSOTSYNCHS_1 (RW) - * - * force phy_errsotsynchs_1 - */ -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT) - -/* - * FORCE_PHY_ERRSOTSYNCHS_0 (RW) - * - * force phy_errsotsynchs_0 - */ -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT) - -/* Bitfield definition for register: INT_ST_PKT_FATAL */ -/* - * ERR_ECC_DOUBLE (RC) - * - * header ecc contains at least 2 errors - */ -#define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_MASK (0x1U) -#define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_SHIFT (0U) -#define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_SHIFT) - -/* Bitfield definition for register: INT_MSK_PKT_FATAL */ -/* - * MASK_ERR_ECC_DOUBLE (RW) - * - * mask for err_ecc_double - */ -#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK (0x1U) -#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT (0U) -#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT) & MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK) -#define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT) - -/* Bitfield definition for register: INT_FORCE_PKT_FATAL */ -/* - * FORCE_ERR_ECC_DOUBLE (RW) - * - * force err_ecc_double - */ -#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT) & MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK) -#define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT) - -/* Bitfield definition for register: INT_ST_PHY */ -/* - * PHY_ERRESC_1 (RC) - * - * start of transmission error on data lane 1 - */ -#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_MASK (0x20000UL) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_SHIFT (17U) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_SHIFT) - -/* - * PHY_ERRESC_0 (RC) - * - * start of transmission error on data lane 0 - */ -#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_MASK (0x10000UL) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_SHIFT (16U) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_SHIFT) - -/* - * PHY_ERRSOTHS_1 (RC) - * - * start of transmission error on data lane 1 - */ -#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_MASK (0x2U) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_SHIFT (1U) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_SHIFT) - -/* - * PHY_ERRSOTHS_0 (RC) - * - * start of transmission error on data lane 0 - */ -#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_MASK (0x1U) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_SHIFT (0U) -#define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_SHIFT) - -/* Bitfield definition for register: INT_MSK_PHY */ -/* - * MASK_PHY_ERRESC_1 (RW) - * - * mask for phy_erresc_1 - */ -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK (0x20000UL) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT (17U) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT) - -/* - * MASK_PHY_ERRESC_0 (RW) - * - * mask for phy_erresc_0 - */ -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK (0x10000UL) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT (16U) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT) - -/* - * MASK_PHY_ERRSOTHS_1 (RW) - * - * mask for phy_errsoths_1 - */ -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK (0x2U) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT (1U) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT) - -/* - * MASK_PHY_ERRSOTHS_0 (RW) - * - * mask for phy_errsoths_0 - */ -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK (0x1U) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT (0U) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK) -#define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT) - -/* Bitfield definition for register: INT_FORCE_PHY */ -/* - * FORCE_PHY_ERRESC_1 (RW) - * - * force phy_erresc_1 - */ -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK (0x20000UL) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT (17U) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT) - -/* - * FORCE_PHY_ERRESC_0 (RW) - * - * force phy_erresc_0 - */ -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK (0x10000UL) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT (16U) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT) - -/* - * FORCE_PHY_ERRSOTHS_1 (RW) - * - * force phy_errsoths_1 - */ -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT) - -/* - * FORCE_PHY_ERRSOTHS_0 (RW) - * - * force phy_errsoths_0 - */ -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK) -#define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT) - -/* Bitfield definition for register: INT_ST_IPI_FATAL */ -/* - * INT_EVENT_FIFO_OVERFLOW (RC) - * - * reporting internal fifo overflow - */ -#define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U) -#define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U) -#define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_SHIFT) - -/* - * PIXEL_IF_HLINE_ERR (RC) - * - * horizontal line time error - */ -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_MASK (0x10U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_SHIFT (4U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_SHIFT) - -/* - * PIXEL_IF_FIFO_NEMPTY_FS (RC) - * - * the fifo of pixel interface is not empty at the starat of a new frame - */ -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) - -/* - * PIXEL_IF_FRAME_SYNC_ERR (RC) - * - * whenever in controller mode, notifies if a new frame is received but previous has not been completed - */ -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_MASK (0x4U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_SHIFT (2U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_SHIFT) - -/* - * PIXEL_IF_FIFO_OVERFLOW (RC) - * - * the fifo of pixel interface has lost information because some data arrived and fifo is already full - */ -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_SHIFT) - -/* - * PIXEL_IF_FIFO_UNDERFLOW (RC) - * - * the fifo has become empty before the expected bumber of pixels could be extracted to the pixel intefcese - */ -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U) -#define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) - -/* Bitfield definition for register: INT_MSK_IPI_FATAL */ -/* - * MSK_INT_EVENT_FIFO_OVERFLOW (RW) - * - * mask int_event_fifo_overflow - */ -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT) - -/* - * MSK_PIXEL_IF_HLINE_ERR (RW) - * - * mask pixel_if_hline_err - */ -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK (0x10U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT (4U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT) - -/* - * MSK_PIXEL_IF_FIFO_NEMPTY_FS (RW) - * - * mask pixel_if_fifo_nempty_fs - */ -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) - -/* - * MSK_FRAME_SYNC_ERR (RW) - * - * mask for pixel_if_frame_sync_err - */ -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK (0x4U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT (2U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT) - -/* - * MSK_PIXEL_IF_FIFO_OVERFLOW (RW) - * - * mask for pixel_if_fifo_overflow - */ -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT) - -/* - * MSK_PIXEL_IF_FIFO_UNDERFLOW (RW) - * - * mask for pixel_if_fifo_unterflow - */ -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK) -#define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) - -/* Bitfield definition for register: INT_FORCE_IPI_FATAL */ -/* - * FORCE_INT_EVENT_FIFO_OVERFLOW (RW) - * - * force int_event_fifo_overflow - */ -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT) - -/* - * FORCE_PIXEL_IF_HLINE_ERR (RW) - * - * force pixel_if_hline_err - */ -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT) - -/* - * FORCE_PIXEL_IF_FIFO_NEMPTY_FS (RW) - * - * force pixel_if_fifo_nempty_fs - */ -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) - -/* - * FORCE_FRAME_SYNC_ERR (RW) - * - * force for frame_sync_err - */ -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK (0x4U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT) - -/* - * FORCE_PIXEL_IF_FIFO_OVERFLOW (RW) - * - * force for pixel_if_fifo_overflow - */ -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT) - -/* - * FORCE_PIXEL_IF_FIFO_UNDERFLOW (RW) - * - * force for pixel_if_fifo_underflow - */ -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK) -#define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) - -/* Bitfield definition for register: INT_ST_AP_GENERIC */ -/* - * SYNCHRONIZER_PIXCLK_AP_ERR (RC) - * - * ap error in synchronizer block for pixclk domain - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL) -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U) -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) - -/* - * SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RC) - * - * ap error in synchronizer block for rxbyteclkhs domain - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U) -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U) -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) - -/* - * SYNCHRONIZER_FPCLK_AP_ERR (RC) - * - * ap error in synchronizer block for fpclk domain - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U) -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U) -#define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) - -/* - * ERR_HANDLE_AP_ERR (RC) - * - * ap error in error handler block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_MASK (0x2000U) -#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_SHIFT (13U) -#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_SHIFT) - -/* - * ERR_MSGR_AP_ERR (RC) - * - * ap error in err msgr block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_MASK (0x1000U) -#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_SHIFT (12U) -#define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_SHIFT) - -/* - * PREP_OUTS_AP_ERR (RC) - * - * ap error in prepare outs block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_MASK (0xC00U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_SHIFT (10U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_SHIFT) - -/* - * PACKET_ANALYZER_AP_ERR (RC) - * - * ap error in packet analyzer block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_MASK (0x300U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_SHIFT (8U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_SHIFT) - -/* - * PHY_ADAPTER_AP_ERR (RC) - * - * ap error in phy adapter block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_MASK (0x80U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_SHIFT (7U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_SHIFT) - -/* - * DESCRAMBLER_AP_ERR (RC) - * - * ap error in descrambler block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_MASK (0x40U) -#define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_SHIFT (6U) -#define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_SHIFT) - -/* - * PIPELINE_DELAY_AP_ERR (RC) - * - * ap error in pipeline delay block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_MASK (0x20U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_SHIFT (5U) -#define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_SHIFT) - -/* - * DE_SKEW_AP_ERR (RC) - * - * ap error in de-skew block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_MASK (0x10U) -#define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_SHIFT (4U) -#define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_SHIFT) - -/* - * REG_BANK_AP_ERR (RC) - * - * ap error in register bank block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_MASK (0xCU) -#define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_SHIFT (2U) -#define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_SHIFT) - -/* - * APB_AP_ERR (RC) - * - * ap error in apb block - */ -#define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_MASK (0x3U) -#define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_SHIFT (0U) -#define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_SHIFT) - -/* Bitfield definition for register: INT_MSK_AP_GENERIC */ -/* - * MSK_SYNCHRONIZER_PIXCLK_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) - -/* - * MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) - -/* - * MSK_SYNCHRONIZER_FPCLK_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) - -/* - * MSK_ERR_HANDLE_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK (0x2000U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT (13U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT) - -/* - * MSK_ERR_MSGR_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK (0x1000U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT (12U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT) - -/* - * MSK_PREP_OUTS_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK (0xC00U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT (10U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT) - -/* - * MSK_PACKET_ANALYZER_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK (0x300U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT (8U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT) - -/* - * MSK_PHY_ADAPTER_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK (0x80U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT (7U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT) - -/* - * MSK_DESCRAMBLER_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK (0x40U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT (6U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT) - -/* - * MSK_PIPELINE_DELAY_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK (0x20U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT (5U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT) - -/* - * MSK_DE_SKEW_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK (0x10U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT (4U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT) - -/* - * MSK_REG_BANK_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK (0xCU) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT (2U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT) - -/* - * MSK_APB_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK (0x3U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT (0U) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK) -#define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT) - -/* Bitfield definition for register: INT_FORCE_AP_GENERIC */ -/* - * FORCE_SYNCHRONIZER_PIXCLK_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) - -/* - * FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) - -/* - * FORCE_SYNCHRONIZER_FPCLK_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) - -/* - * FORCE_ERR_HANDLE_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK (0x2000U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT (13U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT) - -/* - * FORCE_ERR_MSGR_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK (0x1000U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT (12U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT) - -/* - * FORCE_PREP_OUTS_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK (0xC00U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT (10U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT) - -/* - * FORCE_PACKET_ANALYZER_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK (0x300U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT (8U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT) - -/* - * FORCE_PHY_ADAPTER_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK (0x80U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT (7U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT) - -/* - * FORCE_DESCRAMBLER_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK (0x40U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT (6U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT) - -/* - * FORCE_PIPELINE_DELAY_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT) - -/* - * FORCE_DE_SKEW_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT) - -/* - * FORCE_REG_BANK_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK (0xCU) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT) - -/* - * FORCE_APB_AP_ERR (RW) - * - */ -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK (0x3U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK) -#define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT) - -/* Bitfield definition for register: INT_ST_AP_IPI_FATAL */ -/* - * REDUNDANCY_ERR (RC) - * - * ap redundancy error in ipi1 - */ -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_MASK (0x20U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_SHIFT (5U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_SHIFT) - -/* - * CRC_ERR (RC) - * - * ap crc error in ipi1 - */ -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_MASK (0x10U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_SHIFT (4U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_SHIFT) - -/* - * ECC_MULTIPLE_ERR (RC) - * - * ap ecc multiple error in ipi1 - */ -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_MASK (0x8U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_SHIFT (3U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_SHIFT) - -/* - * ECC_SINGLE_ERR (RC) - * - * ap ecc sigle error in ipi1 - */ -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_MASK (0x4U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_SHIFT (2U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_SHIFT) - -/* - * PARITY_RX_ERR (RC) - * - * ap parity rx error in ipi1 - */ -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_MASK (0x2U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_SHIFT (1U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_SHIFT) - -/* - * PARITY_TX_ERR (RC) - * - * ap parity tx error in ipi1 - */ -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_MASK (0x1U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_SHIFT (0U) -#define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_SHIFT) - -/* Bitfield definition for register: INT_MSK_AP_IPI_FATAL */ -/* - * MASK_REDUNDANCY_ERR (RC) - * - */ -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_MASK (0x20U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_SHIFT (5U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_SHIFT) - -/* - * MASK_CRC_ERR (RC) - * - */ -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_MASK (0x10U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_SHIFT (4U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_SHIFT) - -/* - * MASK_ECC_MULTIPLE_ERR (RC) - * - */ -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_MASK (0x8U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_SHIFT (3U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_SHIFT) - -/* - * MASK_ECC_SINGLE_ERR (RC) - * - */ -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_MASK (0x4U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_SHIFT (2U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_SHIFT) - -/* - * MASK_PARITY_RX_ERR (RC) - * - */ -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_MASK (0x2U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_SHIFT (1U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_SHIFT) - -/* - * MASK_PARITY_TX_ERR (RC) - * - */ -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_MASK (0x1U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_SHIFT (0U) -#define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_SHIFT) - -/* Bitfield definition for register: INT_FORCE_AP_IPI_FATAL */ -/* - * FORCE_REDUNDANCY_ERR (RC) - * - */ -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_SHIFT) - -/* - * FORCE_CRC_ERR (RC) - * - */ -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_SHIFT) - -/* - * FORCE_ECC_MULTIPLE_ERR (RC) - * - */ -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_MASK (0x8U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_SHIFT (3U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_SHIFT) - -/* - * FORCE_ECC_SINGLE_ERR (RC) - * - */ -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_MASK (0x4U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_SHIFT) - -/* - * FORCE_PARITY_RX_ERR (RC) - * - */ -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_SHIFT) - -/* - * FORCE_PARITY_TX_ERR (RC) - * - */ -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_SHIFT) - -/* Bitfield definition for register: INT_ST_BNDRY_FRAME_FATAL */ -/* - * ERR_F_BNDRY_MATCH_VC15 (RC) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC14 (RC) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC13 (RC) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC12 (RC) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC11 (RC) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC10 (RC) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC9 (RC) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC8 (RC) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC7 (RC) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC6 (RC) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC5 (RC) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC4 (RC) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC3 (RC) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC2 (RC) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC1 (RC) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_SHIFT) - -/* - * ERR_F_BNDRY_MATCH_VC0 (RC) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_MSK_BNDRY_FRAME_FATAL */ -/* - * MSK_ERR_F_BNDRY_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT) - -/* - * MSK_ERR_F_BNDRY_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK) -#define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_FORCE_BNDRY_FRAME_FATAL */ -/* - * FORCE_ERR_F_BNDRY_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT) - -/* - * FORCE_ERR_F_BNDRY_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK) -#define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_ST_SEQ_FRAME_FATAL */ -/* - * ERR_F_SEQ_MATCH_VC15 (RC) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC14 (RC) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC13 (RC) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC12 (RC) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC11 (RC) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC10 (RC) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC9 (RC) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC8 (RC) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC7 (RC) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC6 (RC) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC5 (RC) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC4 (RC) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC3 (RC) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC2 (RC) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC1 (RC) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_SHIFT) - -/* - * ERR_F_SEQ_MATCH_VC0 (RC) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_MSK_SEQ_FRAME_FATAL */ -/* - * MSK_ERR_F_SEQ_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT) - -/* - * MSK_ERR_F_SEQ_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK) -#define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_FORCE_SEQ_FRAME_FATAL */ -/* - * FORCE_ERR_F_SEQ_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT) - -/* - * FORCE_ERR_F_SEQ_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK) -#define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_ST_CRC_FRAME_FATAL */ -/* - * ERR_F_CRC_MATCH_VC15 (RC) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC14 (RC) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC13 (RC) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC12 (RC) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC11 (RC) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC10 (RC) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC9 (RC) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC8 (RC) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC7 (RC) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC6 (RC) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC5 (RC) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC4 (RC) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC3 (RC) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC2 (RC) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC1 (RC) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_SHIFT) - -/* - * ERR_F_CRC_MATCH_VC0 (RC) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_MSK_CRC_FRAME_FATAL */ -/* - * MSK_ERR_F_CRC_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT) - -/* - * MSK_ERR_F_CRC_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK) -#define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_FORCE_CRC_FRAME_FATAL */ -/* - * FORCE_ERR_F_CRC_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT) - -/* - * FORCE_ERR_F_CRC_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK) -#define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_ST_PLD_CRC_FRAME_FATAL */ -/* - * ERR_CRC_MATCH_VC15 (RC) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_SHIFT) - -/* - * ERR_CRC_MATCH_VC14 (RC) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_SHIFT) - -/* - * ERR_CRC_MATCH_VC13 (RC) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_SHIFT) - -/* - * ERR_CRC_MATCH_VC12 (RC) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_SHIFT) - -/* - * ERR_CRC_MATCH_VC11 (RC) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_SHIFT) - -/* - * ERR_CRC_MATCH_VC10 (RC) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_SHIFT) - -/* - * ERR_CRC_MATCH_VC9 (RC) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_SHIFT) - -/* - * ERR_CRC_MATCH_VC8 (RC) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_SHIFT) - -/* - * ERR_CRC_MATCH_VC7 (RC) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_SHIFT) - -/* - * ERR_CRC_MATCH_VC6 (RC) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_SHIFT) - -/* - * ERR_CRC_MATCH_VC5 (RC) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_SHIFT) - -/* - * ERR_CRC_MATCH_VC4 (RC) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_SHIFT) - -/* - * ERR_CRC_MATCH_VC3 (RC) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_SHIFT) - -/* - * ERR_CRC_MATCH_VC2 (RC) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_SHIFT) - -/* - * ERR_CRC_MATCH_VC1 (RC) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_SHIFT) - -/* - * ERR_CRC_MATCH_VC0 (RC) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_MSK_PLD_CRC_FRAME_FATAL */ -/* - * MSK_ERR_CRC_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT) - -/* - * MSK_ERR_CRC_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK) -#define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT) - -/* Bitfield definition for register: INT_FORCE_PLD_CRC_FRAME_FATAL */ -/* - * FORCE_ERR_CRC_MATCH_VC15 (RW) - * - * error matching frame start with frame end for virtual channel 15 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK (0x8000U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT (15U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC14 (RW) - * - * error matching frame start with frame end for virtual channel 14 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK (0x4000U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT (14U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC13 (RW) - * - * error matching frame start with frame end for virtual channel 13 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK (0x2000U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT (13U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC12 (RW) - * - * error matching frame start with frame end for virtual channel 12 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK (0x1000U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT (12U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC11 (RW) - * - * error matching frame start with frame end for virtual channel 11 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK (0x800U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT (11U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC10 (RW) - * - * error matching frame start with frame end for virtual channel 10 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK (0x400U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT (10U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC9 (RW) - * - * error matching frame start with frame end for virtual channel 9 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK (0x200U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT (9U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC8 (RW) - * - * error matching frame start with frame end for virtual channel 8 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK (0x100U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT (8U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC7 (RW) - * - * error matching frame start with frame end for virtual channel 7 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK (0x80U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT (7U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC6 (RW) - * - * error matching frame start with frame end for virtual channel 6 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK (0x40U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT (6U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC5 (RW) - * - * error matching frame start with frame end for virtual channel 5 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK (0x20U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT (5U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC4 (RW) - * - * error matching frame start with frame end for virtual channel 4 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK (0x10U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT (4U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC3 (RW) - * - * error matching frame start with frame end for virtual channel 3 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK (0x8U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT (3U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC2 (RW) - * - * error matching frame start with frame end for virtual channel 2 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK (0x4U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT (2U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC1 (RW) - * - * error matching frame start with frame end for virtual channel 1 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK (0x2U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT (1U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT) - -/* - * FORCE_ERR_CRC_MATCH_VC0 (RW) - * - * error matching frame start with frame end for virtual channel 0 - */ -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK (0x1U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT (0U) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK) -#define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT) - - - - -#endif /* HPM_MIPI_CSI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_dsi_phy_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_dsi_phy_regs.h deleted file mode 100644 index 2295fce8b70..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_dsi_phy_regs.h +++ /dev/null @@ -1,993 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MIPI_DSI_PHY_H -#define HPM_MIPI_DSI_PHY_H - -typedef struct { - __RW uint32_t CLANE_PARA0; /* 0x0: timer counter about clock lane parameter */ - __RW uint32_t CLANE_PARA1; /* 0x4: timer counter about clock lane parameter */ - __RW uint32_t CLANE_PARA2; /* 0x8: timer counter about clock lane parameter */ - __RW uint32_t CLANE_PARA3; /* 0xC: timer counter about clock lane parameter */ - __RW uint32_t DLANE0_PARA0; /* 0x10: timer counter about datalane0 parameter */ - __RW uint32_t DLANE0_PARA1; /* 0x14: timer counter about datalane0 parameter */ - __RW uint32_t DLANE0_PARA2; /* 0x18: timer counter about datalane0 parameter */ - __RW uint32_t DLANE0_PARA3; /* 0x1C: timer counter about datalane0 parameter */ - __RW uint32_t DLANE0_PARA4; /* 0x20: timer counter about datalane0 parameter */ - __RW uint32_t DLANE1_PARA0; /* 0x24: timer counter about datalane1 parameter */ - __RW uint32_t DLANE1_PARA1; /* 0x28: timer counter about datalane1 parameter */ - __RW uint32_t DLANE1_PARA2; /* 0x2C: timer counter about datalane1 parameter */ - __RW uint32_t DLANE1_PARA3; /* 0x30: timer counter about datalane1 parameter */ - __RW uint32_t DLANE2_PARA0; /* 0x34: timer counter about datalane2 parameter */ - __RW uint32_t DLANE2_PARA1; /* 0x38: timer counter about datalane2 parameter */ - __RW uint32_t DLANE2_PARA2; /* 0x3C: timer counter about datalane2 parameter */ - __RW uint32_t DLANE2_PARA3; /* 0x40: timer counter about datalane2 parameter */ - __RW uint32_t DLANE3_PARA0; /* 0x44: timer counter about datalane3 parameter */ - __RW uint32_t DLANE3_PARA1; /* 0x48: timer counter about datalane3 parameter */ - __RW uint32_t DLANE3_PARA2; /* 0x4C: timer counter about datalane3 parameter */ - __RW uint32_t DLANE3_PARA3; /* 0x50: timer counter about datalane3 parameter */ - __RW uint32_t COMMON_PARA0; /* 0x54: timing parameter for all lanes */ - __RW uint32_t CTRL_PARA0; /* 0x58: dphy control parameter */ - __RW uint32_t PLL_CTRL_PARA0; /* 0x5C: dphy pll control parameter */ - __R uint8_t RESERVED0[4]; /* 0x60 - 0x63: Reserved */ - __RW uint32_t RCAL_CTRL; /* 0x64: dphy calibration control parameter */ - __RW uint32_t TRIM_PARA; /* 0x68: dphy trimming parameter */ - __RW uint32_t TEST_PARA0; /* 0x6C: dphy test control parameter */ - __RW uint32_t TEST_PARA1; /* 0x70: dphy bist test control parameter */ - __RW uint32_t MISC_PARA; /* 0x74: dphy control parameter */ - __RW uint32_t CLANE_PARA4; /* 0x78: dphy clock lane control parameter */ - __RW uint32_t INTERFACE_PARA; /* 0x7C: dphy clock lane control parameter */ - __RW uint32_t PCS_RESERVED_PIN_PARA; /* 0x80: reserved the pins for pcs */ - __R uint8_t RESERVED1[8]; /* 0x84 - 0x8B: Reserved */ - __RW uint32_t CLANE_DATA_PARA; /* 0x8C: parallel data about clock lane parameter */ - __RW uint32_t PMA_LANE_SEL_PARA; /* 0x90: pma about clock lane select parameter */ -} MIPI_DSI_PHY_Type; - - -/* Bitfield definition for register: CLANE_PARA0 */ -/* - * T_RST2ENLPTX_C (RW) - * - * the soft reset of clk_cfg domain - */ -#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK (0xFFFFU) -#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT (0U) -#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA0_T_RST2ENLPTX_C_SHIFT) - -/* Bitfield definition for register: CLANE_PARA1 */ -/* - * T_INITTIME_C (RW) - * - * the number of byteclk cycles that clklane drive LP-11 during initialization period - */ -#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT (0U) -#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA1_T_INITTIME_C_SHIFT) - -/* Bitfield definition for register: CLANE_PARA2 */ -/* - * T_CLKPREPARE_C (RW) - * - * the number of byteclk cycles that clock lane clkp/n lines are at the hs prepare state lp-00 during a hs clock transmission - */ -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT (16U) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPREPARE_C_SHIFT) - -/* - * T_CLKZERO_C (RW) - * - * the number of byteclk cycles that clock lane clkp/n lines are at the hs-zero state hs-0 during a hs clock transmission - */ -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK (0xFF00U) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT (8U) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKZERO_C_SHIFT) - -/* - * T_CLKPRE_C (RW) - * - * the number of byteclk cycles that hs clock shall be driven prior to data lane beginning the transition from lp to hs mode - */ -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK (0xFFU) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT (0U) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA2_T_CLKPRE_C_SHIFT) - -/* Bitfield definition for register: CLANE_PARA3 */ -/* - * T_CLKPOST_C (RW) - * - * the number of byteclk cycles that the clock lane should keep sending the hs-clock after the last associated data lane has transitioned to LP mode. - */ -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT (16U) -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKPOST_C_SHIFT) - -/* - * T_CLKTRIAL_C (RW) - * - * the number of byteclk cycles that the clock lane clkp/n lines are at state hs-tail sate hs-0 during a hs clock transmission - */ -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK (0xFF00U) -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT (8U) -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_CLKTRIAL_C_SHIFT) - -/* - * T_HSEXIT_C (RW) - * - * the number of byteclk cycles that the clock lane clkp/n lines are at hs-exit state after a hs clock transmission - */ -#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK (0xFFU) -#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT (0U) -#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA3_T_HSEXIT_C_SHIFT) - -/* Bitfield definition for register: DLANE0_PARA0 */ -/* - * T_RST2ENLPTX_D0 (RW) - * - * the number of byteclk cycles that datalane0 wait to enable lptx_en after reset release - */ -#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK (0xFFFFU) -#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA0_T_RST2ENLPTX_D0_SHIFT) - -/* Bitfield definition for register: DLANE0_PARA1 */ -/* - * T_INITTIME_D0 (RW) - * - * the number of byteclk cycles that datalane0 drive lp-11 during initiaalization period - */ -#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA1_T_INITTIME_D0_SHIFT) - -/* Bitfield definition for register: DLANE0_PARA2 */ -/* - * T_HSPREPARE_D0 (RW) - * - * the number of byteclk cycles that the datalane0 stay at hs prepare state lp-00 during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK (0xFF000000UL) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT (24U) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSPREPARE_D0_SHIFT) - -/* - * T_HSZERO_D0 (RW) - * - * the number of byteclk cycles that the datalane0 stay at hs-zero sate during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT (16U) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSZERO_D0_SHIFT) - -/* - * T_HSTRAIL_D0 (RW) - * - * the number of byteclk cycles that the datalane0 stay at hs-trail state during a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK (0xFF00U) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT (8U) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSTRAIL_D0_SHIFT) - -/* - * T_HSEXIT_D0 (RW) - * - * the number of byteclk cycles that the datalane0 stay at state hs-exit sate after a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK (0xFFU) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA2_T_HSEXIT_D0_SHIFT) - -/* Bitfield definition for register: DLANE0_PARA3 */ -/* - * T_WAKEUP_D0 (RW) - * - * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - */ -#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA3_T_WAKEUP_D0_SHIFT) - -/* Bitfield definition for register: DLANE0_PARA4 */ -/* - * T_TAGO_D0 (RW) - * - * the number of byteclk cycles that the tx drives the bridge state during a turnaroud procedure - */ -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT (16U) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGO_D0_SHIFT) - -/* - * T_TASURE_D0 (RW) - * - * the number of byteclk cycles that the rx waits after a bridge state has been detected during a turnaround procedure - */ -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK (0xFF00U) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT (8U) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TASURE_D0_SHIFT) - -/* - * T_TAGET_D0 (RW) - * - * the number of byteclk cycles that the new transmitter drivers the bridge state after accepting control during bta - */ -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK (0xFFU) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) -#define MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_MASK) >> MIPI_DSI_PHY_DLANE0_PARA4_T_TAGET_D0_SHIFT) - -/* Bitfield definition for register: DLANE1_PARA0 */ -/* - * T_RST2ENLPTX_D1 (RW) - * - * the number of byteclk cycles that datalane1 wait to enable lptx_en after reset release - */ -#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK (0xFFFFU) -#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA0_T_RST2ENLPTX_D1_SHIFT) - -/* Bitfield definition for register: DLANE1_PARA1 */ -/* - * T_INITTIME_D1 (RW) - * - * the number of byteclk cycles that datalane1 drive lp-11 during initiaalization period - */ -#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA1_T_INITTIME_D1_SHIFT) - -/* Bitfield definition for register: DLANE1_PARA2 */ -/* - * T_HSPREPARE_D1 (RW) - * - * the number of byteclk cycles that the datalane1 stay at hs prepare state lp-00 during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK (0xFF000000UL) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT (24U) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSPREPARE_D1_SHIFT) - -/* - * T_HSZERO_D1 (RW) - * - * the number of byteclk cycles that the datalane1 stay at hs-zero sate during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT (16U) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSZERO_D1_SHIFT) - -/* - * T_HSTRAIL_D1 (RW) - * - * the number of byteclk cycles that the datalane1 stay at hs-trail state during a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK (0xFF00U) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT (8U) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSTRAIL_D1_SHIFT) - -/* - * T_HSEXIT_D1 (RW) - * - * the number of byteclk cycles that the datalane1 stay at state hs-exit sate after a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK (0xFFU) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA2_T_HSEXIT_D1_SHIFT) - -/* Bitfield definition for register: DLANE1_PARA3 */ -/* - * T_WAKEUP_D1 (RW) - * - * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - */ -#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) -#define MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_MASK) >> MIPI_DSI_PHY_DLANE1_PARA3_T_WAKEUP_D1_SHIFT) - -/* Bitfield definition for register: DLANE2_PARA0 */ -/* - * T_RST2ENLPTX_D2 (RW) - * - * the number of byteclk cycles that datalane2 wait to enable lptx_en after reset release - */ -#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK (0xFFFFU) -#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA0_T_RST2ENLPTX_D2_SHIFT) - -/* Bitfield definition for register: DLANE2_PARA1 */ -/* - * T_INITTIME_D2 (RW) - * - * the number of byteclk cycles that datalane2 drive lp-11 during initiaalization period - */ -#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA1_T_INITTIME_D2_SHIFT) - -/* Bitfield definition for register: DLANE2_PARA2 */ -/* - * T_HSPREPARE_D2 (RW) - * - * the number of byteclk cycles that the datalane2 stay at hs prepare state lp-00 during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK (0xFF000000UL) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT (24U) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSPREPARE_D2_SHIFT) - -/* - * T_HSZERO_D2 (RW) - * - * the number of byteclk cycles that the datalane2 stay at hs-zero sate during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT (16U) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSZERO_D2_SHIFT) - -/* - * T_HSTRAIL_D2 (RW) - * - * the number of byteclk cycles that the datalane2 stay at hs-trail state during a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK (0xFF00U) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT (8U) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSTRAIL_D2_SHIFT) - -/* - * T_HSEXIT_D2 (RW) - * - * the number of byteclk cycles that the datalane2 stay at state hs-exit sate after a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK (0xFFU) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA2_T_HSEXIT_D2_SHIFT) - -/* Bitfield definition for register: DLANE2_PARA3 */ -/* - * T_WAKEUP_D2 (RW) - * - * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - */ -#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) -#define MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_MASK) >> MIPI_DSI_PHY_DLANE2_PARA3_T_WAKEUP_D2_SHIFT) - -/* Bitfield definition for register: DLANE3_PARA0 */ -/* - * T_RST2ENLPTX_D3 (RW) - * - * the number of byteclk cycles that datalane3 wait to enable lptx_en after reset release - */ -#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK (0xFFFFU) -#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA0_T_RST2ENLPTX_D3_SHIFT) - -/* Bitfield definition for register: DLANE3_PARA1 */ -/* - * T_INITTIME_D3 (RW) - * - * the number of byteclk cycles that datalane3 drive lp-11 during initiaalization period - */ -#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA1_T_INITTIME_D3_SHIFT) - -/* Bitfield definition for register: DLANE3_PARA2 */ -/* - * T_HSPREPARE_D3 (RW) - * - * the number of byteclk cycles that the datalane3 stay at hs prepare state lp-00 during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK (0xFF000000UL) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT (24U) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSPREPARE_D3_SHIFT) - -/* - * T_HSZERO_D3 (RW) - * - * the number of byteclk cycles that the datalane3 stay at hs-zero sate during a hs transmission - */ -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK (0xFF0000UL) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT (16U) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSZERO_D3_SHIFT) - -/* - * T_HSTRAIL_D3 (RW) - * - * the number of byteclk cycles that the datalane3 stay at hs-trail state during a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK (0xFF00U) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT (8U) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSTRAIL_D3_SHIFT) - -/* - * T_HSEXIT_D3 (RW) - * - * the number of byteclk cycles that the datalane3 stay at state hs-exit sate after a hs clock transmission - */ -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK (0xFFU) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA2_T_HSEXIT_D3_SHIFT) - -/* Bitfield definition for register: DLANE3_PARA3 */ -/* - * T_WAKEUP_D3 (RW) - * - * the number of byteclk cycles from exiting ultra low power sate to enabling the low-power driver - */ -#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT (0U) -#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) -#define MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_MASK) >> MIPI_DSI_PHY_DLANE3_PARA3_T_WAKEUP_D3_SHIFT) - -/* Bitfield definition for register: COMMON_PARA0 */ -/* - * T_LPX (RW) - * - * the number of byteclk cycles of transmitted length of any low-power state period - */ -#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK (0xFFU) -#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT (0U) -#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) -#define MIPI_DSI_PHY_COMMON_PARA0_T_LPX_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_COMMON_PARA0_T_LPX_MASK) >> MIPI_DSI_PHY_COMMON_PARA0_T_LPX_SHIFT) - -/* Bitfield definition for register: CTRL_PARA0 */ -/* - * VBG_RDY (RO) - * - * the indicator signal of reference generator is ready - */ -#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK (0x80U) -#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT (7U) -#define MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_VBG_RDY_SHIFT) - -/* - * EN_ULPRX_D0 (RW) - * - * ulp-rx enable for lane0 - */ -#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK (0x40U) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT (6U) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_ULPRX_D0_SHIFT) - -/* - * EN_LPRX_D0 (RW) - * - * lp-rx enable for lane0 - */ -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK (0x20U) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT (5U) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPRX_D0_SHIFT) - -/* - * EN_LPCD_D0 (RW) - * - * lp-cd enable for lane0 - */ -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK (0x10U) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT (4U) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_EN_LPCD_D0_SHIFT) - -/* - * PWON_SEL (RW) - * - * select the cource of PMA power on control signals - */ -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK (0x8U) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT (3U) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_SEL_SHIFT) - -/* - * PWON_PLL (RW) - * - * power on pll high active - */ -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK (0x4U) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT (2U) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_PLL_SHIFT) - -/* - * PWON_DSI (RW) - * - * power on all dsi lane - */ -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK (0x2U) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT (1U) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_PWON_DSI_SHIFT) - -/* - * SU_IDDQ_EN (RW) - * - * power down all modules inside su includes ivref, r-calibration and pll, high effective - */ -#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK (0x1U) -#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT (0U) -#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) -#define MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_MASK) >> MIPI_DSI_PHY_CTRL_PARA0_SU_IDDQ_EN_SHIFT) - -/* Bitfield definition for register: PLL_CTRL_PARA0 */ -/* - * PLL_LOCK (RO) - * - * pll lock indication - */ -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK (0x8000000UL) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT (27U) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_LOCK_SHIFT) - -/* - * RATE (RW) - * - * data reate control signal - */ -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK (0x7000000UL) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT (24U) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_RATE_SHIFT) - -/* - * REFCLK_DIV (RW) - * - * input reference clock divider ratio control - */ -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK (0xF80000UL) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT (19U) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_REFCLK_DIV_SHIFT) - -/* - * PLL_DIV (RW) - * - * pll loop divider ratio control - */ -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK (0x7FFF0UL) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT (4U) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_PLL_DIV_SHIFT) - -/* - * DSI_PIXELCLK_DIV (RW) - * - * pixell clock divided from pll output - */ -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK (0xFU) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT (0U) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) -#define MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_MASK) >> MIPI_DSI_PHY_PLL_CTRL_PARA0_DSI_PIXELCLK_DIV_SHIFT) - -/* Bitfield definition for register: RCAL_CTRL */ -/* - * RCAL_EN (RW) - * - * enable hs-tx output impedance trimming - */ -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK (0x2000U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT (13U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_EN_SHIFT) - -/* - * RCAL_TRIM (RW) - * - * default value of hs-tx output resistance configure - */ -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK (0x1E00U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT (9U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_TRIM_SHIFT) - -/* - * RCAL_CTRL (RW) - * - * resistor calibration control, reserved for test - */ -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK (0x1FEU) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT (1U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_CTRL_SHIFT) - -/* - * RCAL_DONE (RO) - * - * hs-tx output impedance trimming done indicator signal - */ -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK (0x1U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT (0U) -#define MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_MASK) >> MIPI_DSI_PHY_RCAL_CTRL_RCAL_DONE_SHIFT) - -/* Bitfield definition for register: TRIM_PARA */ -/* - * HSTX_AMP_TRIM (RW) - * - * hs-tx output vod trimming for lane-0~4 - */ -#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK (0x3800U) -#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT (11U) -#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) -#define MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_HSTX_AMP_TRIM_SHIFT) - -/* - * LPTX_SR_TRIM (RW) - * - * lp-tx output slew-rate trimming for lane0~4 - */ -#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK (0x700U) -#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT (8U) -#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) -#define MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPTX_SR_TRIM_SHIFT) - -/* - * LPRX_VREF_TRIM (RW) - * - * lp-rx input threshold voltage trimming for lane0 - */ -#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK (0xF0U) -#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT (4U) -#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) -#define MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPRX_VREF_TRIM_SHIFT) - -/* - * LPCD_VREF_TRIM (RW) - * - * lp-cd input threshold voltage trimming for lane0 - */ -#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK (0xFU) -#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT (0U) -#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) -#define MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_MASK) >> MIPI_DSI_PHY_TRIM_PARA_LPCD_VREF_TRIM_SHIFT) - -/* Bitfield definition for register: TEST_PARA0 */ -/* - * ERROR_NUM (RO) - * - * the byte num of mismatch data of lane in bist mode - */ -#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK (0x7E0000UL) -#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT (17U) -#define MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ERROR_NUM_SHIFT) - -/* - * BIST_N_DONE (RO) - * - * indicate prbs7 bist test is done - */ -#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK (0x1F000UL) -#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT (12U) -#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_DONE_SHIFT) - -/* - * BIST_N_OK (RO) - * - * indicate prbs7 bist test is ok - */ -#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK (0xF80U) -#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT (7U) -#define MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_MASK) >> MIPI_DSI_PHY_TEST_PARA0_BIST_N_OK_SHIFT) - -/* - * ATEST_EN (RW) - * - * analog test signal enable - */ -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK (0x40U) -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT (6U) -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_EN_SHIFT) - -/* - * ATEST_SEL (RW) - * - * analog test signal select - */ -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK (0x30U) -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT (4U) -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) -#define MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_ATEST_SEL_SHIFT) - -/* - * FSET_EN (RW) - * - * enable fast transmission between lp-tx and hs-tx - */ -#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK (0x8U) -#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT (3U) -#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) -#define MIPI_DSI_PHY_TEST_PARA0_FSET_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FSET_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FSET_EN_SHIFT) - -/* - * FT_SEL (RW) - * - * pt/ft test mode select - */ -#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK (0x7U) -#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT (0U) -#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) -#define MIPI_DSI_PHY_TEST_PARA0_FT_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA0_FT_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA0_FT_SEL_SHIFT) - -/* Bitfield definition for register: TEST_PARA1 */ -/* - * CHECK_NUM (RW) - * - * the byte num of prbs bist check num - */ -#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK (0xFFFFFC00UL) -#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT (10U) -#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) -#define MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_MASK) >> MIPI_DSI_PHY_TEST_PARA1_CHECK_NUM_SHIFT) - -/* - * ERR_THRESHOLD (RW) - * - * the threshold of prbs bit error - */ -#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK (0x3C0U) -#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT (6U) -#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) -#define MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_MASK) >> MIPI_DSI_PHY_TEST_PARA1_ERR_THRESHOLD_SHIFT) - -/* - * BIST_BIT_ERROR (RW) - * - * enable insert error in bist test pattern - */ -#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK (0x20U) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT (5U) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_BIT_ERROR_SHIFT) - -/* - * BIST_EN (RW) - * - * bist enable - */ -#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK (0x18U) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT (3U) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_EN_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_EN_SHIFT) - -/* - * BIST_SEL (RW) - * - * bist mode select - */ -#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK (0x4U) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT (2U) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) -#define MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_BIST_SEL_SHIFT) - -/* - * PRBS_SEL (RW) - * - * prbs generator and checker pattern select signal - */ -#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK (0x3U) -#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT (0U) -#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) -#define MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_MASK) >> MIPI_DSI_PHY_TEST_PARA1_PRBS_SEL_SHIFT) - -/* Bitfield definition for register: MISC_PARA */ -/* - * DLL_SEL (RW) - * - * the phase select of clk_rxesc - */ -#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK (0x780U) -#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT (7U) -#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) -#define MIPI_DSI_PHY_MISC_PARA_DLL_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_DLL_SEL_MASK) >> MIPI_DSI_PHY_MISC_PARA_DLL_SEL_SHIFT) - -/* - * LANE_NUM (RW) - * - * the number of active data lanes - */ -#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK (0x60U) -#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT (5U) -#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) -#define MIPI_DSI_PHY_MISC_PARA_LANE_NUM_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_LANE_NUM_MASK) >> MIPI_DSI_PHY_MISC_PARA_LANE_NUM_SHIFT) - -/* - * PHYERR_MASK (RW) - * - * mask the phy error - */ -#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK (0x1FU) -#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT (0U) -#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) -#define MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_MASK) >> MIPI_DSI_PHY_MISC_PARA_PHYERR_MASK_SHIFT) - -/* Bitfield definition for register: CLANE_PARA4 */ -/* - * T_WAKEUP_C (RW) - * - * the number of byteclk cycles from exiting ultra low power state to enabling the low-power driver - */ -#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT (0U) -#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) -#define MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_MASK) >> MIPI_DSI_PHY_CLANE_PARA4_T_WAKEUP_C_SHIFT) - -/* Bitfield definition for register: INTERFACE_PARA */ -/* - * TXREADYESC_EXTEND_VLD (RW) - * - * the extend length of txreadyesc - */ -#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK (0xFF00U) -#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT (8U) -#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) -#define MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_TXREADYESC_EXTEND_VLD_SHIFT) - -/* - * RXVALIDESC_EXTEND_VLD (RW) - * - * the extend length of rxvalidesc - */ -#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK (0xFFU) -#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT (0U) -#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) -#define MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_MASK) >> MIPI_DSI_PHY_INTERFACE_PARA_RXVALIDESC_EXTEND_VLD_SHIFT) - -/* Bitfield definition for register: PCS_RESERVED_PIN_PARA */ -/* - * CLK_TXHS_SEL_INNER (RW) - * - * select the clock source of clk_txhs in pcs - */ -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK (0x10U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT (4U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_CLK_TXHS_SEL_INNER_SHIFT) - -/* - * INV_CLK_TXHS (RW) - * - * clk_txhs inverter signal - */ -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK (0x8U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT (3U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXHS_SHIFT) - -/* - * INV_CLK_TXESC (RW) - * - * clk_txesc inverter signal - */ -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK (0x4U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT (2U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_CLK_TXESC_SHIFT) - -/* - * INV_PCLK (RW) - * - * pclk inverter signal - */ -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK (0x2U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT (1U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_PCLK_SHIFT) - -/* - * INV_DSI_RCLK (RW) - * - * pma clock dsi_rclk_i inverter signal - */ -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK (0x1U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT (0U) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) -#define MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_MASK) >> MIPI_DSI_PHY_PCS_RESERVED_PIN_PARA_INV_DSI_RCLK_SHIFT) - -/* Bitfield definition for register: CLANE_DATA_PARA */ -/* - * CLANE_DATA_SEL (RW) - * - * select the data about clock lane - */ -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK (0x100U) -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT (8U) -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SEL_SHIFT) - -/* - * CLANE_DATA (RW) - * - * the parallel data about clock lane - */ -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK (0xFFU) -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT (0U) -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) -#define MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_MASK) >> MIPI_DSI_PHY_CLANE_DATA_PARA_CLANE_DATA_SHIFT) - -/* Bitfield definition for register: PMA_LANE_SEL_PARA */ -/* - * PMA_DLANE4_SEL (RW) - * - * select the channel 4 as the data lane - */ -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK (0x8U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT (3U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE4_SEL_SHIFT) - -/* - * PMA_DLANE3_SEL (RW) - * - * select the channel 3 as the data lane - */ -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK (0x4U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT (2U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE3_SEL_SHIFT) - -/* - * PMA_DLANE2_SEL (RW) - * - * select the channel 2 as the data lane - */ -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK (0x2U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT (1U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE2_SEL_SHIFT) - -/* - * PMA_DLANE1_SEL (RW) - * - * select the channel 1 as the data lane - */ -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK (0x1U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT (0U) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) -#define MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_MASK) >> MIPI_DSI_PHY_PMA_LANE_SEL_PARA_PMA_DLANE1_SEL_SHIFT) - - - - -#endif /* HPM_MIPI_DSI_PHY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_dsi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_dsi_regs.h deleted file mode 100644 index 7d3a3fe1494..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mipi_dsi_regs.h +++ /dev/null @@ -1,2882 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MIPI_DSI_H -#define HPM_MIPI_DSI_H - -typedef struct { - __R uint32_t VERSION; /* 0x0: version */ - __RW uint32_t PWR_UP; /* 0x4: power up */ - __RW uint32_t CLKMGR_CFG; /* 0x8: divide lanebyteclk for timeout */ - __RW uint32_t DPI_VCID; /* 0xC: virtual channel ID for DPI traffic */ - __RW uint32_t DPI_COLOR_CODING; /* 0x10: dpi color coding */ - __RW uint32_t DPI_CFG_POL; /* 0x14: the polarity of DPI signals */ - __RW uint32_t DPI_LP_CMD_TIM; /* 0x18: the timing for low-power commands sent while in video mode */ - __R uint8_t RESERVED0[16]; /* 0x1C - 0x2B: Reserved */ - __RW uint32_t PCKHDL_CFG; /* 0x2C: configures how EoTp, BTA, CRC and ECC to be used */ - __RW uint32_t GEN_VCID; /* 0x30: configures the virtual channel ID of read response to store and return to generic interface */ - __RW uint32_t MODE_CFG; /* 0x34: configures the mode of operation between video or command mode */ - __RW uint32_t VID_MODE_CFG; /* 0x38: several aspect of video mode operation */ - __RW uint32_t VID_PKT_SIZE; /* 0x3C: configures the video packet size */ - __RW uint32_t VID_NUM_CHUNKS; /* 0x40: configures the number of chunks to use */ - __RW uint32_t VID_NULL_SIZE; /* 0x44: configures the size of null packets */ - __RW uint32_t VID_HSA_TIME; /* 0x48: configures the video HAS time */ - __RW uint32_t VID_HBP_TIME; /* 0x4C: configure the video HBP time */ - __RW uint32_t VID_HLINE_TIME; /* 0x50: configures the overall time for each video line */ - __RW uint32_t VID_VSA_LINES; /* 0x54: configures the vsa period */ - __RW uint32_t VID_VBP_LINES; /* 0x58: configures the vbp period */ - __RW uint32_t VID_VFP_LINES; /* 0x5C: configures the vfp period */ - __RW uint32_t VID_VACTIVE_LINES; /* 0x60: configures the vertical resolution of video */ - __R uint8_t RESERVED1[4]; /* 0x64 - 0x67: Reserved */ - __RW uint32_t CMD_MODE_CFG; /* 0x68: This register configures several aspect of command mode operation, tearing effect, acknowledge for each packet and the speed mode to transmit each Data Type related to commands. */ - __RW uint32_t GEN_HDR; /* 0x6C: sets the header for new packets sent using the generic interface */ - __RW uint32_t GEN_PLD_DATA; /* 0x70: sets the payload for packets sent using the generic interface */ - __R uint32_t CMD_PKT_STATUS; /* 0x74: information about the status of FIFOs related to DBI and Generic interface */ - __RW uint32_t TO_CNT_CFG; /* 0x78: configures the trigger timeout errors */ - __RW uint32_t HS_RD_TO_CNT; /* 0x7C: configures the peripheral response timeout after high speed read operations */ - __RW uint32_t LP_RD_TO_CNT; /* 0x80: configures the peripheral response timeout after low-power read operation */ - __RW uint32_t HS_WR_TO_CNT; /* 0x84: configures the peripheral response timeout after high speed write operations */ - __RW uint32_t LP_WR_TO_CNT; /* 0x88: configures the peripheral response timeout after low power write operations */ - __RW uint32_t BTA_TO_CNT; /* 0x8C: configures the periphera response timeout after bus turnaround */ - __RW uint32_t SDF_3D; /* 0x90: sotres 3d control information for vss packets in video mode */ - __RW uint32_t LPCLK_CTRL; /* 0x94: configures the possibility for using non continuous clock in the clock lane */ - __RW uint32_t PHY_TMR_LPCLK_CFG; /* 0x98: sets the time that dsi host assumes in calculations for the clock lane to switch between high-speed and low-power */ - __RW uint32_t PHY_TMR_CFG; /* 0x9C: sets the time that dsi host assumes in calculations for data lanes to switch between hs to lp */ - __RW uint32_t PHY_RSTZ; /* 0xA0: controls resets and the pll of d-phy */ - __RW uint32_t PHY_IF_CFG; /* 0xA4: configures the number of active lanes */ - __RW uint32_t PHY_ULPS_CTRL; /* 0xA8: configures entering and leaving ulps */ - __RW uint32_t PHY_TX_TRIGGERS; /* 0xAC: configures the pins that activate triggers in the d-phy */ - __R uint32_t PHY_STATUS; /* 0xB0: contains information about the status of the d-phy */ - __RW uint32_t PHY_TST_CTRL0; /* 0xB4: controls clock and clear pins of the d-phy vendor specific interface */ - __RW uint32_t PHY_TST_CTRL1; /* 0xB8: controls data and enable pins of the d-phy */ - __R uint32_t INT_ST0; /* 0xBC: controls the status of interrupt */ - __R uint32_t INT_ST1; /* 0xC0: the interrupt source related to timeout etc */ - __RW uint32_t INT_MSK0; /* 0xC4: configures masks for the sources of interrupt that affec int_st0 */ - __RW uint32_t INT_MSK1; /* 0xC8: configures masks for int_st1 */ - __RW uint32_t PHY_CAL; /* 0xCC: controls the skew calibration of D-phy */ - __R uint8_t RESERVED2[8]; /* 0xD0 - 0xD7: Reserved */ - __RW uint32_t INT_FORCE0; /* 0xD8: forces that affect the int_st0 register */ - __RW uint32_t INT_FORCE1; /* 0xDC: forces interrupts that affect the int_st1 register */ - __R uint8_t RESERVED3[20]; /* 0xE0 - 0xF3: Reserved */ - __RW uint32_t PHY_TMR_RD; /* 0xF4: configures times related to PHY to perform some operations in lane byte clock cycle */ - __RW uint32_t AUTO_ULPS_MIN_TIME; /* 0xF8: configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane */ - __RW uint32_t PHY_MODE; /* 0xFC: select phy mode */ - __RW uint32_t VID_SHADOW_CTRL; /* 0x100: controls dpi shadow feature */ - __R uint8_t RESERVED4[8]; /* 0x104 - 0x10B: Reserved */ - __R uint32_t DPI_VCID_ACT; /* 0x10C: holds the value that controller is using for DPI_VCID */ - __R uint32_t DPI_COLOR_CODING_ACT; /* 0x110: holds the value that controller is using for DPI_COLOR_CODING */ - __R uint8_t RESERVED5[4]; /* 0x114 - 0x117: Reserved */ - __R uint32_t DPI_LP_CMD_TIM_ACT; /* 0x118: holds value that controller is using for dpi_lp_cmd_time */ - __R uint8_t RESERVED6[28]; /* 0x11C - 0x137: Reserved */ - __R uint32_t VID_MODE_CFG_ACT; /* 0x138: holds value that controller is using for vid_mode_cfg */ - __R uint32_t VID_PKT_SIZE_ACT; /* 0x13C: holds value that controller is using for vid_pkt_size */ - __R uint32_t VID_NUM_CHUNKS_ACT; /* 0x140: holds value that controller is using for vid_num_chunks */ - __R uint32_t VID_NULL_SIZE_ACT; /* 0x144: holds the value that controller is using for vid_null_size */ - __R uint32_t VID_HSA_TIME_ACT; /* 0x148: the value of vid_hsa_time */ - __R uint32_t VID_HBP_TIME_ACT; /* 0x14C: the value that controller is using for vid_hbp_time */ - __R uint32_t VID_HLINE_TIME_ACT; /* 0x150: the value for vid_hline_time */ - __R uint32_t VID_VSA_LINES_ACT; /* 0x154: value for vid_vsa_lines */ - __R uint32_t VID_VBP_LINES_ACT; /* 0x158: value for vid_vbp_lines */ - __R uint32_t VID_VFP_LINES_ACT; /* 0x15C: value for vid_vfp_lines */ - __R uint32_t VID_VACTIVE_LINES_ACT; /* 0x160: value for vid_vactive_lines */ - __R uint8_t RESERVED7[4]; /* 0x164 - 0x167: Reserved */ - __R uint32_t VID_PKT_STATUS; /* 0x168: status of fifo related to dpi */ - __R uint8_t RESERVED8[36]; /* 0x16C - 0x18F: Reserved */ - __R uint32_t SDF_3D_ACT; /* 0x190: value for sdf_3d */ -} MIPI_DSI_Type; - - -/* Bitfield definition for register: VERSION */ -/* - * VERSION (RO) - * - * version of DSI - */ -#define MIPI_DSI_VERSION_VERSION_MASK (0xFFFFFFFFUL) -#define MIPI_DSI_VERSION_VERSION_SHIFT (0U) -#define MIPI_DSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_DSI_VERSION_VERSION_MASK) >> MIPI_DSI_VERSION_VERSION_SHIFT) - -/* Bitfield definition for register: PWR_UP */ -/* - * SHUTDOWNZ (RW) - * - * 0x0: reset the core - * 0x1: power up the core - */ -#define MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK (0x1U) -#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT (0U) -#define MIPI_DSI_PWR_UP_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) -#define MIPI_DSI_PWR_UP_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PWR_UP_SHUTDOWNZ_MASK) >> MIPI_DSI_PWR_UP_SHUTDOWNZ_SHIFT) - -/* Bitfield definition for register: CLKMGR_CFG */ -/* - * TO_CLK_DIVISION (RW) - * - * the timeout clock division factor for HS to LP and LP to HS transition error - */ -#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK (0xFF00U) -#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT (8U) -#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) -#define MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TO_CLK_DIVISION_SHIFT) - -/* - * TX_ESC_CLK_DIVISION (RW) - * - * the division factor for the TX Escape clock source lanebyteclk - */ -#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK (0xFFU) -#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT (0U) -#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SET(x) (((uint32_t)(x) << MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) -#define MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_GET(x) (((uint32_t)(x) & MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_MASK) >> MIPI_DSI_CLKMGR_CFG_TX_ESC_CLK_DIVISION_SHIFT) - -/* Bitfield definition for register: DPI_VCID */ -/* - * DPI_VCID (RW) - * - * the DPI virtual channel id to the video mode packets - */ -#define MIPI_DSI_DPI_VCID_DPI_VCID_MASK (0x3U) -#define MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT (0U) -#define MIPI_DSI_DPI_VCID_DPI_VCID_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) -#define MIPI_DSI_DPI_VCID_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_DPI_VCID_SHIFT) - -/* Bitfield definition for register: DPI_COLOR_CODING */ -/* - * LOOSELY18_EN (RW) - * - * when set to 1, this bit activates loosely packed variant to 18-bit configurations - */ -#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK (0x100U) -#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT (8U) -#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) -#define MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_LOOSELY18_EN_SHIFT) - -/* - * DPI_COLOR_CODING (RW) - * - * configures the DPI color for video mode - */ -#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK (0xFU) -#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT (0U) -#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) -#define MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_DPI_COLOR_CODING_SHIFT) - -/* Bitfield definition for register: DPI_CFG_POL */ -/* - * COLORM_ACTIVE_LOW (RW) - * - * configures the color mode pin as active low - */ -#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK (0x10U) -#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT (4U) -#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) -#define MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_COLORM_ACTIVE_LOW_SHIFT) - -/* - * SHUTD_ACTIVE_LOW (RW) - * - * configures the shutdown pin as active low - */ -#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK (0x8U) -#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT (3U) -#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) -#define MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_SHUTD_ACTIVE_LOW_SHIFT) - -/* - * HSYNC_ACTIVE_LOW (RW) - * - * configures the horizontal synchronism pin as active low - */ -#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK (0x4U) -#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT (2U) -#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) -#define MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_HSYNC_ACTIVE_LOW_SHIFT) - -/* - * VSYNC_ACTIVE_LOW (RW) - * - * configures the vertical synchronism pin as active low - */ -#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK (0x2U) -#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT (1U) -#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) -#define MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_VSYNC_ACTIVE_LOW_SHIFT) - -/* - * DATAEN_ACTIVE_LOW (RW) - * - * configures the data enable pin active low - */ -#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK (0x1U) -#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT (0U) -#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) -#define MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_MASK) >> MIPI_DSI_DPI_CFG_POL_DATAEN_ACTIVE_LOW_SHIFT) - -/* Bitfield definition for register: DPI_LP_CMD_TIM */ -/* - * OUTVACT_LPCMD_TIME (RW) - * - * transmission of commands in low-power mode, defines the size in bytes of the largest pachet that can fit in a line during the VSA VBP and VFP; - */ -#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) -#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT (16U) -#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) -#define MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_OUTVACT_LPCMD_TIME_SHIFT) - -/* - * INVACT_LPCMD_TIME (RW) - * - * transmission of commands in low-power mode, defines the size in bytes of the largest packet that can fit in a line during the VACT region. - */ -#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK (0xFFU) -#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT (0U) -#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) -#define MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_INVACT_LPCMD_TIME_SHIFT) - -/* Bitfield definition for register: PCKHDL_CFG */ -/* - * EOTP_TX_LP_EN (RW) - * - * enable the EoTp transmission in low-power - */ -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK (0x20U) -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT (5U) -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_LP_EN_SHIFT) - -/* - * CRC_RX_EN (RW) - * - * enable the crc reception and error reporting - */ -#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK (0x10U) -#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT (4U) -#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) -#define MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_CRC_RX_EN_SHIFT) - -/* - * ECC_RX_EN (RW) - * - * enable the ecc reception error correction and reporting - */ -#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK (0x8U) -#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT (3U) -#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) -#define MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_ECC_RX_EN_SHIFT) - -/* - * BTA_EN (RW) - * - * enable the bus turn-around request - */ -#define MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK (0x4U) -#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT (2U) -#define MIPI_DSI_PCKHDL_CFG_BTA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) -#define MIPI_DSI_PCKHDL_CFG_BTA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_BTA_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_BTA_EN_SHIFT) - -/* - * EOTP_RX_EN (RW) - * - * enable the EoTp reception - */ -#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK (0x2U) -#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT (1U) -#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) -#define MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_RX_EN_SHIFT) - -/* - * EOTP_TX_EN (RW) - * - * enable the EoTp transmission in high-speed - */ -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK (0x1U) -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT (0U) -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) -#define MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_MASK) >> MIPI_DSI_PCKHDL_CFG_EOTP_TX_EN_SHIFT) - -/* Bitfield definition for register: GEN_VCID */ -/* - * GEN_VCID_TX_AUTO (RW) - * - * indicates the generic interface virtual channel identification where generic packet is automatically generated and transmitted - */ -#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK (0x30000UL) -#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT (16U) -#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) -#define MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TX_AUTO_SHIFT) - -/* - * GEN_VCID_TEAR_AUTO (RW) - * - * indicates the virtual channel identification for tear effect by hardware - */ -#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK (0x300U) -#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT (8U) -#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) -#define MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_TEAR_AUTO_SHIFT) - -/* - * GEN_VCID_RX (RW) - * - * indicates the generic interface read-back virtual channel identication - */ -#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK (0x3U) -#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT (0U) -#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) -#define MIPI_DSI_GEN_VCID_GEN_VCID_RX_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_VCID_GEN_VCID_RX_MASK) >> MIPI_DSI_GEN_VCID_GEN_VCID_RX_SHIFT) - -/* Bitfield definition for register: MODE_CFG */ -/* - * CMD_VIDEO_MODE (RW) - * - * 0x0: video mode - * 0x1: command mode - */ -#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK (0x1U) -#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT (0U) -#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) -#define MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_MASK) >> MIPI_DSI_MODE_CFG_CMD_VIDEO_MODE_SHIFT) - -/* Bitfield definition for register: VID_MODE_CFG */ -/* - * VPG_ORIENTATION (RW) - * - * indicates the color bar orientation : - * 0x0: vertical mode - * 0x1: horizontal mode - */ -#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK (0x1000000UL) -#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT (24U) -#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) -#define MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_ORIENTATION_SHIFT) - -/* - * VPG_MODE (RW) - * - * 0x0: colorbar - * 0x1: berpattern, vertical only - */ -#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK (0x100000UL) -#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT (20U) -#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) -#define MIPI_DSI_VID_MODE_CFG_VPG_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_MODE_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_MODE_SHIFT) - -/* - * VPG_EN (RW) - * - * enable video mode pattern generator - */ -#define MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK (0x10000UL) -#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT (16U) -#define MIPI_DSI_VID_MODE_CFG_VPG_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_VPG_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VPG_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_VPG_EN_SHIFT) - -/* - * LP_CMD_EN (RW) - * - * enable command transmission only in low-power mode - */ -#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK (0x8000U) -#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT (15U) -#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_CMD_EN_SHIFT) - -/* - * FRAME_BTA_ACK_EN (RW) - * - * enable the request for an acknowledge response at the end of a frame - */ -#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK (0x4000U) -#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT (14U) -#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_FRAME_BTA_ACK_EN_SHIFT) - -/* - * LP_HFP_EN (RW) - * - * enable the return to low-power inside the HFP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK (0x2000U) -#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT (13U) -#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HFP_EN_SHIFT) - -/* - * LP_HBP_EN (RW) - * - * enable the return to low-power inside the HBP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK (0x1000U) -#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT (12U) -#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_HBP_EN_SHIFT) - -/* - * LP_VACT_EN (RW) - * - * enable the return to low-power inside the VACT period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK (0x800U) -#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT (11U) -#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VACT_EN_SHIFT) - -/* - * LP_VFP_EN (RW) - * - * enable the return to low-power inside the VFP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK (0x400U) -#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT (10U) -#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VFP_EN_SHIFT) - -/* - * LP_VBP_EN (RW) - * - * enable the return to low-power inside the VBP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK (0x200U) -#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT (9U) -#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VBP_EN_SHIFT) - -/* - * LP_VSA_EN (RW) - * - * enable the return to low-power inside the VSA period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK (0x100U) -#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT (8U) -#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) -#define MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_LP_VSA_EN_SHIFT) - -/* - * VID_MODE_TYPE (RW) - * - * indicates the video mode transmission type - */ -#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK (0x3U) -#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT (0U) -#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) -#define MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_VID_MODE_TYPE_SHIFT) - -/* Bitfield definition for register: VID_PKT_SIZE */ -/* - * VID_PKT_SIZE (RW) - * - * configures the number of pixels in a single video packet - */ -#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK (0x3FFFU) -#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT (0U) -#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) -#define MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_VID_PKT_SIZE_SHIFT) - -/* Bitfield definition for register: VID_NUM_CHUNKS */ -/* - * VID_NUM_CHUNKS (RW) - * - * configures the number of chunks to be transmitted a line period - */ -#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK (0x1FFFU) -#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT (0U) -#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) -#define MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_VID_NUM_CHUNKS_SHIFT) - -/* Bitfield definition for register: VID_NULL_SIZE */ -/* - * VID_NULL_SIZE (RW) - * - * configures the number of bytes inside a null packet - */ -#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK (0x1FFFU) -#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT (0U) -#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) -#define MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_VID_NULL_SIZE_SHIFT) - -/* Bitfield definition for register: VID_HSA_TIME */ -/* - * VID_HSA_TIME (RW) - * - * configure the Horizontal synchronism active period in lane byte clock cycles - */ -#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK (0xFFFU) -#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT (0U) -#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) -#define MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_VID_HSA_TIME_SHIFT) - -/* Bitfield definition for register: VID_HBP_TIME */ -/* - * VID_HPB_TIME (RW) - * - * configures the Horizontal back porch period in lane byte clock cycles - */ -#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK (0xFFFU) -#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT (0U) -#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) -#define MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_VID_HPB_TIME_SHIFT) - -/* Bitfield definition for register: VID_HLINE_TIME */ -/* - * VID_HLINE_TIME (RW) - * - * configures the size of the total line time in lane byte clock cycles - */ -#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK (0x7FFFU) -#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT (0U) -#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) -#define MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_VID_HLINE_TIME_SHIFT) - -/* Bitfield definition for register: VID_VSA_LINES */ -/* - * VSA_LINES (RW) - * - * configures the verical synchronism active period measured in number of horizontal lines - */ -#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK (0x3FFU) -#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) -#define MIPI_DSI_VID_VSA_LINES_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_VSA_LINES_SHIFT) - -/* Bitfield definition for register: VID_VBP_LINES */ -/* - * VBP_LINES (RW) - * - * configures the vertical back porch period measured in number of horizontal lines - */ -#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK (0x3FFU) -#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) -#define MIPI_DSI_VID_VBP_LINES_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_VBP_LINES_SHIFT) - -/* Bitfield definition for register: VID_VFP_LINES */ -/* - * VFP_LINIES (RW) - * - * configures the vertical front porch period measured in number of horizontal lines - */ -#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK (0x3FFU) -#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT (0U) -#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) -#define MIPI_DSI_VID_VFP_LINES_VFP_LINIES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_VFP_LINIES_MASK) >> MIPI_DSI_VID_VFP_LINES_VFP_LINIES_SHIFT) - -/* Bitfield definition for register: VID_VACTIVE_LINES */ -/* - * V_ACTIVE_LINES (RW) - * - * configures the vertical active period measured in number of horizontal lines - */ -#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK (0x3FFFU) -#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) -#define MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_V_ACTIVE_LINES_SHIFT) - -/* Bitfield definition for register: CMD_MODE_CFG */ -/* - * MAX_RD_PKT_SIZE (RW) - * - * This bit configures the maximum read packet size command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK (0x1000000UL) -#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT (24U) -#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) -#define MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_MASK) >> MIPI_DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE_SHIFT) - -/* - * DCS_LW_TX (RW) - * - * This bit configures the DCS long write packet command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK (0x80000UL) -#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT (19U) -#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_LW_TX_SHIFT) - -/* - * DCS_SR_0P_TX (RW) - * - * This bit configures the DCS short read packet with zero parameter command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK (0x40000UL) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT (18U) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SR_0P_TX_SHIFT) - -/* - * DCS_SW_1P_TX (RW) - * - * This bit configures the DCS short write packet with one parameter command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK (0x20000UL) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT (17U) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_1P_TX_SHIFT) - -/* - * DCS_SW_0P_TX (RW) - * - * This bit configures the DCS short write packet with zero parameter command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK (0x10000UL) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT (16U) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_DCS_SW_0P_TX_SHIFT) - -/* - * GEN_LW_TX (RW) - * - * This bit configures the Generic long write packet command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK (0x4000U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT (14U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_LW_TX_SHIFT) - -/* - * GEN_SR_2P_TX (RW) - * - * This bit configures the Generic short read packet with two parameters command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK (0x2000U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT (13U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_2P_TX_SHIFT) - -/* - * GEN_SR_1P_TX (RW) - * - * This bit configures the Generic short read packet with two parameters command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK (0x1000U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT (12U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_1P_TX_SHIFT) - -/* - * GEN_SR_0P_TX (RW) - * - * This bit configures the Generic short read packet with two parameters command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK (0x800U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT (11U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SR_0P_TX_SHIFT) - -/* - * GEN_SW_2P_TX (RW) - * - * This bit configures the Generic short read packet with two parameters command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK (0x400U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT (10U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_2P_TX_SHIFT) - -/* - * GEN_SW_1P_TX (RW) - * - * This bit configures the Generic short read packet with two parameters command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK (0x200U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT (9U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_1P_TX_SHIFT) - -/* - * GEN_SW_0P_TX (RW) - * - * This bit configures the Generic short read packet with two parameters command transmission type: - * 0x0 (HIGHSPEED): Transition type is High Speed - * 0x1 (LOWPOWER): Transition type is Low Power - */ -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK (0x100U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT (8U) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) -#define MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_MASK) >> MIPI_DSI_CMD_MODE_CFG_GEN_SW_0P_TX_SHIFT) - -/* - * ACK_RQST_EN (RW) - * - * When set to 1, this bit enables the acknowledge request after each packet transmission. - */ -#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK (0x2U) -#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT (1U) -#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) -#define MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_ACK_RQST_EN_SHIFT) - -/* - * TEAR_FX_EN (RW) - * - * When set to 1, this bit enables the tearing effect acknowledge request. - */ -#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK (0x1U) -#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT (0U) -#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) -#define MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_MASK) >> MIPI_DSI_CMD_MODE_CFG_TEAR_FX_EN_SHIFT) - -/* Bitfield definition for register: GEN_HDR */ -/* - * GEN_WC_MSBYTE (RW) - * - * configures the most significant byte of the header packet's word count for long packets or data 1 for shout packets - */ -#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK (0xFF0000UL) -#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT (16U) -#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) -#define MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_MSBYTE_SHIFT) - -/* - * GEN_WC_LSBYTE (RW) - * - * configures the least significant byte of the header packet's word count for long packets or data0 for short packets - */ -#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK (0xFF00U) -#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT (8U) -#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) -#define MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_MASK) >> MIPI_DSI_GEN_HDR_GEN_WC_LSBYTE_SHIFT) - -/* - * GEN_VC (RW) - * - * configures the virtual channel ID of the header packet - */ -#define MIPI_DSI_GEN_HDR_GEN_VC_MASK (0xC0U) -#define MIPI_DSI_GEN_HDR_GEN_VC_SHIFT (6U) -#define MIPI_DSI_GEN_HDR_GEN_VC_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) -#define MIPI_DSI_GEN_HDR_GEN_VC_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_VC_MASK) >> MIPI_DSI_GEN_HDR_GEN_VC_SHIFT) - -/* - * GEN_DT (RW) - * - * configures the packet data type of the header packet - */ -#define MIPI_DSI_GEN_HDR_GEN_DT_MASK (0x3FU) -#define MIPI_DSI_GEN_HDR_GEN_DT_SHIFT (0U) -#define MIPI_DSI_GEN_HDR_GEN_DT_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) -#define MIPI_DSI_GEN_HDR_GEN_DT_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_HDR_GEN_DT_MASK) >> MIPI_DSI_GEN_HDR_GEN_DT_SHIFT) - -/* Bitfield definition for register: GEN_PLD_DATA */ -/* - * GEN_PLD_B4 (RW) - * - * indicates byte4 of the packet payload - */ -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK (0xFF000000UL) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT (24U) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B4_SHIFT) - -/* - * GEN_PLD_B3 (RW) - * - * indicates byte3 of the packet payload - */ -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK (0xFF0000UL) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT (16U) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B3_SHIFT) - -/* - * GEN_PLD_B2 (RW) - * - * indicates byte2 of the packet payload - */ -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK (0xFF00U) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT (8U) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B2_SHIFT) - -/* - * GEN_PLD_B1 (RW) - * - * indicates byte1 of the packet payload - */ -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK (0xFFU) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT (0U) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SET(x) (((uint32_t)(x) << MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) -#define MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_GET(x) (((uint32_t)(x) & MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_MASK) >> MIPI_DSI_GEN_PLD_DATA_GEN_PLD_B1_SHIFT) - -/* Bitfield definition for register: CMD_PKT_STATUS */ -/* - * GEN_BUFF_PLD_FULL (R) - * - * the full status of the generic payload internal buffer - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK (0x80000UL) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT (19U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_FULL_SHIFT) - -/* - * GEN_BUFF_PLD_EMPTY (R) - * - * the empty status of the generic payload internal buffer - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK (0x40000UL) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT (18U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_PLD_EMPTY_SHIFT) - -/* - * GEN_BUFF_CMD_FULL (R) - * - * the full status of the generic command internal buffer - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK (0x20000UL) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT (17U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_FULL_SHIFT) - -/* - * GEN_BUFF_CMD_EMPTY (R) - * - * the empty status of the generic command internal buffer - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK (0x10000UL) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT (16U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_BUFF_CMD_EMPTY_SHIFT) - -/* - * GEN_RD_CMD_BUSY (R) - * - * indicates a read command is issued and the entire response is not sotred in the FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK (0x40U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT (6U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY_SHIFT) - -/* - * GEN_PLD_R_FULL (R) - * - * indicates the full status of the generic read payoad FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK (0x20U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT (5U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_FULL_SHIFT) - -/* - * GEN_PLD_R_EMPTY (R) - * - * indicates the empty status of the generic read payload FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK (0x10U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT (4U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY_SHIFT) - -/* - * GEN_PLD_W_FULL (R) - * - * indicates the full status of the generic write payload FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK (0x8U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT (3U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL_SHIFT) - -/* - * GEN_PLD_W_EMPTY (R) - * - * indicates the empty status of the generic write payload FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK (0x4U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT (2U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY_SHIFT) - -/* - * GEN_CMD_FULL (R) - * - * indicates the full status of the generic command FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK (0x2U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT (1U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_FULL_SHIFT) - -/* - * GEN_CMD_EMPTY (R) - * - * indicates the empty status of the generic command FIFO - */ -#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK (0x1U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT (0U) -#define MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_MASK) >> MIPI_DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY_SHIFT) - -/* Bitfield definition for register: TO_CNT_CFG */ -/* - * HSTX_TO_CNT (RW) - * - * configures the timeout counter that triggers a high speed transmission timeout contention detection - */ -#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK (0xFFFF0000UL) -#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT (16U) -#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) -#define MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_HSTX_TO_CNT_SHIFT) - -/* - * LPRX_TO_CNT (RW) - * - * configures the timeout counter that triggers a low power reception timeout contention detection - */ -#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK (0xFFFFU) -#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT (0U) -#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) -#define MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_MASK) >> MIPI_DSI_TO_CNT_CFG_LPRX_TO_CNT_SHIFT) - -/* Bitfield definition for register: HS_RD_TO_CNT */ -/* - * HS_RD_TO_CNT (RW) - * - * sets a period for which DWC_mipi_dsi_host keeps the link still after sending a high speed read operation; - */ -#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK (0xFFFFU) -#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT (0U) -#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) -#define MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_MASK) >> MIPI_DSI_HS_RD_TO_CNT_HS_RD_TO_CNT_SHIFT) - -/* Bitfield definition for register: LP_RD_TO_CNT */ -/* - * LP_RD_TO_CNT (RW) - * - * sets a period for which dwc_mipi_dsi_host keeps the link still after sending a low power read operation - */ -#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK (0xFFFFU) -#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT (0U) -#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) -#define MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_MASK) >> MIPI_DSI_LP_RD_TO_CNT_LP_RD_TO_CNT_SHIFT) - -/* Bitfield definition for register: HS_WR_TO_CNT */ -/* - * HS_WR_TO_CNT (RW) - * - * sets the period for which dwc_mipi_dsi_host keeps the link still after sending a high speed write operation - */ -#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK (0xFFFFU) -#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT (0U) -#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) -#define MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_MASK) >> MIPI_DSI_HS_WR_TO_CNT_HS_WR_TO_CNT_SHIFT) - -/* Bitfield definition for register: LP_WR_TO_CNT */ -/* - * LP_WR_TO_CNT (RW) - * - * sets the period for which dsi host keeps the link still after sending a low power write operation - */ -#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK (0xFFFFU) -#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT (0U) -#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) -#define MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_MASK) >> MIPI_DSI_LP_WR_TO_CNT_LP_WR_TO_CNT_SHIFT) - -/* Bitfield definition for register: BTA_TO_CNT */ -/* - * BTA_TO_CNT (RW) - * - * sets the period for which dsi host keeps the link still after completing a bus turnaround. - */ -#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK (0xFFFFU) -#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT (0U) -#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SET(x) (((uint32_t)(x) << MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) -#define MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_GET(x) (((uint32_t)(x) & MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_MASK) >> MIPI_DSI_BTA_TO_CNT_BTA_TO_CNT_SHIFT) - -/* Bitfield definition for register: SDF_3D */ -/* - * SEND_3D_CFG (RW) - * - * set the next vss packet to include 3d control payload in every vss packet - */ -#define MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK (0x10000UL) -#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT (16U) -#define MIPI_DSI_SDF_3D_SEND_3D_CFG_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) -#define MIPI_DSI_SDF_3D_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_SEND_3D_CFG_SHIFT) - -/* - * RIGHT_FIRST (RW) - * - * 0x0: left eye is sent first - * 0x1:right eye is sent first - */ -#define MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK (0x20U) -#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT (5U) -#define MIPI_DSI_SDF_3D_RIGHT_FIRST_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) -#define MIPI_DSI_SDF_3D_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_RIGHT_FIRST_SHIFT) - -/* - * SECOND_VSYNC (RW) - * - * defines whether there is a second VSYNC pulse - */ -#define MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK (0x10U) -#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT (4U) -#define MIPI_DSI_SDF_3D_SECOND_VSYNC_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) -#define MIPI_DSI_SDF_3D_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_SECOND_VSYNC_SHIFT) - -/* - * FORMAT_3D (RW) - * - * defines 3D image format - */ -#define MIPI_DSI_SDF_3D_FORMAT_3D_MASK (0xCU) -#define MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT (2U) -#define MIPI_DSI_SDF_3D_FORMAT_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) -#define MIPI_DSI_SDF_3D_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_FORMAT_3D_SHIFT) - -/* - * MODE_3D (RW) - * - * defines 3D mode on/off - */ -#define MIPI_DSI_SDF_3D_MODE_3D_MASK (0x3U) -#define MIPI_DSI_SDF_3D_MODE_3D_SHIFT (0U) -#define MIPI_DSI_SDF_3D_MODE_3D_SET(x) (((uint32_t)(x) << MIPI_DSI_SDF_3D_MODE_3D_SHIFT) & MIPI_DSI_SDF_3D_MODE_3D_MASK) -#define MIPI_DSI_SDF_3D_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_MODE_3D_SHIFT) - -/* Bitfield definition for register: LPCLK_CTRL */ -/* - * AUTO_CLKLANE_CTRL (RW) - * - * enables the automatic mechanism to stop providing clock in the clock lane - */ -#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK (0x2U) -#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT (1U) -#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) -#define MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_MASK) >> MIPI_DSI_LPCLK_CTRL_AUTO_CLKLANE_CTRL_SHIFT) - -/* - * PHY_TXREQUESTCLKHS (RW) - * - * controls the D-PHY PPI txrequestclkhs signal - */ -#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK (0x1U) -#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT (0U) -#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SET(x) (((uint32_t)(x) << MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) -#define MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_GET(x) (((uint32_t)(x) & MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_MASK) >> MIPI_DSI_LPCLK_CTRL_PHY_TXREQUESTCLKHS_SHIFT) - -/* Bitfield definition for register: PHY_TMR_LPCLK_CFG */ -/* - * PHY_CLKHS2LP_TIME (RW) - * - * configures the maximum time that the d-phy clock lane takes to go from high-speed to low-power transmission - */ -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK (0x3FF0000UL) -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT (16U) -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKHS2LP_TIME_SHIFT) - -/* - * PHY_CLKLP2HS_TIME (RW) - * - * configures the maximum time that the d-phy clock lane takes to go from low-power to high-speed transmission - */ -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK (0x3FFU) -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT (0U) -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) -#define MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_LPCLK_CFG_PHY_CLKLP2HS_TIME_SHIFT) - -/* Bitfield definition for register: PHY_TMR_CFG */ -/* - * PHY_HS2LP_TIME (RW) - * - * This field configures the maximum time that the D-PHY data - * lanes take to go from high-speed to low-power transmission - * measured in lane byte clock cycles - */ -#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK (0x3FF0000UL) -#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT (16U) -#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) -#define MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_HS2LP_TIME_SHIFT) - -/* - * PHY_LP2HS_TIME (RW) - * - * This field configures the maximum time that the D-PHY data - * lanes take to go from low-power to high-speed transmission - * measured in lane byte clock cycles. - */ -#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK (0x3FFU) -#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT (0U) -#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) -#define MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_MASK) >> MIPI_DSI_PHY_TMR_CFG_PHY_LP2HS_TIME_SHIFT) - -/* Bitfield definition for register: PHY_RSTZ */ -/* - * PHY_FORCEPLL (RW) - * - * when the d-phy is in ulps, enable the d-phy pll - */ -#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK (0x8U) -#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT (3U) -#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) -#define MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_FORCEPLL_SHIFT) - -/* - * PHY_ENABLECLK (RW) - * - * enable dphy clock lane - */ -#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK (0x4U) -#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT (2U) -#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) -#define MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_ENABLECLK_SHIFT) - -/* - * PHY_RSTZ (RW) - * - * make the dphy in reset state when set to 0 - */ -#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK (0x2U) -#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT (1U) -#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) -#define MIPI_DSI_PHY_RSTZ_PHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_RSTZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_RSTZ_SHIFT) - -/* - * PHY_SHUTDOWNZ (RW) - * - * places the dphy macro in power down mode when set to 0 - */ -#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK (0x1U) -#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT (0U) -#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) -#define MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_MASK) >> MIPI_DSI_PHY_RSTZ_PHY_SHUTDOWNZ_SHIFT) - -/* Bitfield definition for register: PHY_IF_CFG */ -/* - * PHY_STOP_WAIT_TIME (RW) - * - * configures the minimum time phy needs to stay in stopstate before requesting an highspeed transmission - */ -#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK (0xFF00U) -#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT (8U) -#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) -#define MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_MASK) >> MIPI_DSI_PHY_IF_CFG_PHY_STOP_WAIT_TIME_SHIFT) - -/* - * N_LANES (RW) - * - * configures the number of active data lanes - */ -#define MIPI_DSI_PHY_IF_CFG_N_LANES_MASK (0x3U) -#define MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT (0U) -#define MIPI_DSI_PHY_IF_CFG_N_LANES_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) -#define MIPI_DSI_PHY_IF_CFG_N_LANES_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_IF_CFG_N_LANES_MASK) >> MIPI_DSI_PHY_IF_CFG_N_LANES_SHIFT) - -/* Bitfield definition for register: PHY_ULPS_CTRL */ -/* - * PHY_TXEXITULPSLAN (RW) - * - * ulps mode exit on all active data lanes - */ -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK (0x8U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT (3U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSLAN_SHIFT) - -/* - * PHY_TXREQULPSLAN (RW) - * - * ulps mode request on all active data lanes - */ -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK (0x4U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT (2U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSLAN_SHIFT) - -/* - * PHY_TXEXITULPSCLK (RW) - * - * ulps mode exit on clock lane - */ -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK (0x2U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT (1U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXEXITULPSCLK_SHIFT) - -/* - * PHY_TXREQULPSCLK (RW) - * - * ulps mode request on clock lane - */ -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK (0x1U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT (0U) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) -#define MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_MASK) >> MIPI_DSI_PHY_ULPS_CTRL_PHY_TXREQULPSCLK_SHIFT) - -/* Bitfield definition for register: PHY_TX_TRIGGERS */ -/* - * PHY_TX_TRIGGERS (RW) - * - * controls the trigger transmissions - */ -#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK (0xFU) -#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT (0U) -#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) -#define MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_MASK) >> MIPI_DSI_PHY_TX_TRIGGERS_PHY_TX_TRIGGERS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * PHY_ULPSACTIVENOT3LANE (R) - * - * indicates the status of ulpsactivenot3lane d-phy signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK (0x1000U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT (12U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT3LANE_SHIFT) - -/* - * PHY_STOPSTATE3LANE (R) - * - * This bit indicates the status of phystopstate3lane D-PHY - * signal. - */ -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK (0x800U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT (11U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE3LANE_SHIFT) - -/* - * PHY_ULPSACTIVENOT2LANE (R) - * - * This bit indicates the status of ulpsactivenot2lane D-PHY - * signa - */ -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK (0x400U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT (10U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT2LANE_SHIFT) - -/* - * PHY_STOPSTATE2LANE (R) - * - * This bit indicates the status of phystopstate2lane D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK (0x200U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT (9U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE2LANE_SHIFT) - -/* - * PHY_ULPSACTIVENOT1LANE (R) - * - * This bit indicates the status of ulpsactivenot1lane D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK (0x100U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT (8U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT1LANE_SHIFT) - -/* - * PHY_STOPSTATE1LANE (R) - * - * This bit indicates the status of phystopstate1lane D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK (0x80U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT (7U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE1LANE_SHIFT) - -/* - * PHY_RXULPSESC0LANE (R) - * - * This bit indicates the status of rxulpsesc0lane D-PHY signa - */ -#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK (0x40U) -#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT (6U) -#define MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_RXULPSESC0LANE_SHIFT) - -/* - * PHY_ULPSACTIVENOT0LANE (R) - * - * This bit indicates the status of ulpsactivenot0lane D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK (0x20U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT (5U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOT0LANE_SHIFT) - -/* - * PHY_STOPSTATE0LANE (R) - * - * This bit indicates the status of phystopstate0lane D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK (0x10U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT (4U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATE0LANE_SHIFT) - -/* - * PHY_ULPSACTIVENOTCLK (R) - * - * This bit indicates the status of phyulpsactivenotclk D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK (0x8U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT (3U) -#define MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_ULPSACTIVENOTCLK_SHIFT) - -/* - * PHY_STOPSTATECLKLANE (R) - * - * This bit indicates the status of phystopstateclklane D-PHY - * signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK (0x4U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT (2U) -#define MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_MASK) >> MIPI_DSI_PHY_STATUS_PHY_STOPSTATECLKLANE_SHIFT) - -/* - * PHY_DIRECTION (R) - * - * This bit indicates the status of phydirection D-PHY signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK (0x2U) -#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT (1U) -#define MIPI_DSI_PHY_STATUS_PHY_DIRECTION_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_DIRECTION_MASK) >> MIPI_DSI_PHY_STATUS_PHY_DIRECTION_SHIFT) - -/* - * PHY_LOCK (R) - * - * This bit indicates the status of phylock D-PHY signal - */ -#define MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK (0x1U) -#define MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT (0U) -#define MIPI_DSI_PHY_STATUS_PHY_LOCK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_STATUS_PHY_LOCK_MASK) >> MIPI_DSI_PHY_STATUS_PHY_LOCK_SHIFT) - -/* Bitfield definition for register: PHY_TST_CTRL0 */ -/* - * PHY_TESTCLK (RW) - * - * reserve - */ -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK (0x2U) -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT (1U) -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLK_SHIFT) - -/* - * PHY_TESTCLR (RW) - * - * reserve - */ -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK (0x1U) -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT (0U) -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) -#define MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_MASK) >> MIPI_DSI_PHY_TST_CTRL0_PHY_TESTCLR_SHIFT) - -/* Bitfield definition for register: PHY_TST_CTRL1 */ -/* - * PHY_TESTEN (RW) - * - * reserve - */ -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK (0x10000UL) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT (16U) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTEN_SHIFT) - -/* - * PHY_TESTDOUT (R) - * - * reserve - */ -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK (0xFF00U) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT (8U) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDOUT_SHIFT) - -/* - * PHY_TESTDIN (RW) - * - * reserve - */ -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK (0xFFU) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT (0U) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) -#define MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_MASK) >> MIPI_DSI_PHY_TST_CTRL1_PHY_TESTDIN_SHIFT) - -/* Bitfield definition for register: INT_ST0 */ -/* - * DPHY_ERRORS_4 (R) - * - * indicates LP1 contention error ErrContentionLP1 from lane0 - */ -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK (0x100000UL) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT (20U) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_4_SHIFT) - -/* - * DPHY_ERRORS_3 (R) - * - * indicates LP0 contention error ErrContentionLP0 from lane0 - */ -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK (0x80000UL) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT (19U) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_3_SHIFT) - -/* - * DPHY_ERRORS_2 (R) - * - * indicates control error ErrControl from lane0 - */ -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK (0x40000UL) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT (18U) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_2_SHIFT) - -/* - * DPHY_ERRORS_1 (R) - * - * indicates ErrSyncEsc low-power data transmission synchronization error from lane 0 - */ -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK (0x20000UL) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT (17U) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_1_SHIFT) - -/* - * DPHY_ERRORS_0 (R) - * - * indicates ErrEsc escape entry error from lane0 - */ -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK (0x10000UL) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT (16U) -#define MIPI_DSI_INT_ST0_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_ST0_DPHY_ERRORS_0_SHIFT) - -/* - * ACK_WITH_ERR_15 (R) - * - * retrives the DSI protocal violation from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK (0x8000U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT (15U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_15_SHIFT) - -/* - * ACK_WITH_ERR_14 (R) - * - * retrives the reserved from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK (0x4000U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT (14U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_14_SHIFT) - -/* - * ACK_WITH_ERR_13 (R) - * - * retrives the invalid transmission length from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK (0x2000U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT (13U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_13_SHIFT) - -/* - * ACK_WITH_ERR_12 (R) - * - * retrieves the dsi vc id invalid from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK (0x1000U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT (12U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_12_SHIFT) - -/* - * ACK_WITH_ERR_11 (R) - * - * retrives the not recongnized dsi data type from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK (0x800U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT (11U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_11_SHIFT) - -/* - * ACK_WITH_ERR_10 (R) - * - * retrives the checksum error from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK (0x400U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT (10U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_10_SHIFT) - -/* - * ACK_WITH_ERR_9 (R) - * - * retrives the ECC error multi-bit from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK (0x200U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT (9U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR_9_SHIFT) - -/* - * ACK_WITH_ERR8 (R) - * - * retrives the ecc error sigle-bit from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK (0x100U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT (8U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR8_SHIFT) - -/* - * ACK_WITH_ERR7 (R) - * - * retrieves the reserved from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK (0x80U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT (7U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR7_SHIFT) - -/* - * ACK_WITH_ERR6 (R) - * - * retrieves the false control error fro the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK (0x40U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT (6U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR6_SHIFT) - -/* - * ACK_WITH_ERR5 (R) - * - * retrives the peripheral timeout error from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK (0x20U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT (5U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR5_SHIFT) - -/* - * ACK_WITH_ERR4 (R) - * - * retrives the LP transmit sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK (0x10U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT (4U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR4_SHIFT) - -/* - * ACK_WITH_ERR3 (R) - * - * retrives the Escap mode entry command error from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK (0x8U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT (3U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR3_SHIFT) - -/* - * ACK_WITH_ERR2 (R) - * - * retrives the EoT sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK (0x4U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT (2U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR2_SHIFT) - -/* - * ACK_WITH_ERR1 (R) - * - * retrives the SoT sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK (0x2U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT (1U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR1_SHIFT) - -/* - * ACK_WITH_ERR0 (R) - * - * retrives the SoT serror from the acknowledge error report - */ -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK (0x1U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT (0U) -#define MIPI_DSI_INT_ST0_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST0_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_ST0_ACK_WITH_ERR0_SHIFT) - -/* Bitfield definition for register: INT_ST1 */ -/* - * TEAR_REQUEST_ERR (R) - * - * indicates tear_request has occurred but tear effect is not active in dsi host and device - */ -#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK (0x100000UL) -#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT (20U) -#define MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_ST1_TEAR_REQUEST_ERR_SHIFT) - -/* - * DPI_BUFF_PLD_UNDER (R) - * - * indicates an underflow when reading payload to build dsi packet for video mode - */ -#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) -#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT (19U) -#define MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_ST1_DPI_BUFF_PLD_UNDER_SHIFT) - -/* - * GEN_PLD_RECEV_ERR (R) - * - * indicates that during a generic interface packet read back, the payload FIFO full - */ -#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK (0x1000U) -#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT (12U) -#define MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RECEV_ERR_SHIFT) - -/* - * GEN_PLD_RD_ERR (R) - * - * indicates that during a DCS read data, the payload FIFO becomes empty - */ -#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK (0x800U) -#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT (11U) -#define MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_RD_ERR_SHIFT) - -/* - * GEN_PLD_SEND_ERR (R) - * - * indicates the payload FIFO become empty when packet build - */ -#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK (0x400U) -#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT (10U) -#define MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_SEND_ERR_SHIFT) - -/* - * GEN_PLD_WR_ERR (R) - * - * indicates the system tried to write a payload and FIFO is full - */ -#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK (0x200U) -#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT (9U) -#define MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_PLD_WR_ERR_SHIFT) - -/* - * GEN_CMD_WR_ERR (R) - * - * indicates the system tried to write a command and FIFO is full - */ -#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK (0x100U) -#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT (8U) -#define MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_GEN_CMD_WR_ERR_SHIFT) - -/* - * DPI_BPLD_WR_ERR (R) - * - * indicates the payload FIFO is full during a DPI pixel line storage - */ -#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK (0x80U) -#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT (7U) -#define MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_ST1_DPI_BPLD_WR_ERR_SHIFT) - -/* - * EOPT_ERR (R) - * - * indicates that the EoTp packet has not been received at the end of the incoming peripheral transmission - */ -#define MIPI_DSI_INT_ST1_EOPT_ERR_MASK (0x40U) -#define MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT (6U) -#define MIPI_DSI_INT_ST1_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_EOPT_ERR_MASK) >> MIPI_DSI_INT_ST1_EOPT_ERR_SHIFT) - -/* - * PKT_SIZE_ERR (R) - * - * indicates that the packet size error has been detected during the packet reception - */ -#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK (0x20U) -#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT (5U) -#define MIPI_DSI_INT_ST1_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_ST1_PKT_SIZE_ERR_SHIFT) - -/* - * CRC_ERR (R) - * - * indicates that the CRC error has been detected in the reveived packet payload - */ -#define MIPI_DSI_INT_ST1_CRC_ERR_MASK (0x10U) -#define MIPI_DSI_INT_ST1_CRC_ERR_SHIFT (4U) -#define MIPI_DSI_INT_ST1_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_CRC_ERR_MASK) >> MIPI_DSI_INT_ST1_CRC_ERR_SHIFT) - -/* - * ECC_MULTI_ERR (R) - * - * indicates that the ECC multiple error has been detected in a revieved packet - */ -#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK (0x8U) -#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT (3U) -#define MIPI_DSI_INT_ST1_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_MULTI_ERR_SHIFT) - -/* - * ECC_SIGLE_ERR (R) - * - * indicates that the ECC single error has been detected and corrected in a reveived packet - */ -#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK (0x4U) -#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT (2U) -#define MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_ST1_ECC_SIGLE_ERR_SHIFT) - -/* - * TO_LP_TX (R) - * - * indicates that the low-power reception timeout counter reached the end and contention has been detected - */ -#define MIPI_DSI_INT_ST1_TO_LP_TX_MASK (0x2U) -#define MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT (1U) -#define MIPI_DSI_INT_ST1_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_LP_TX_MASK) >> MIPI_DSI_INT_ST1_TO_LP_TX_SHIFT) - -/* - * TO_HS_TX (R) - * - * indicates that the high-speed transmission timeout counter reached the end and contention has been detected - */ -#define MIPI_DSI_INT_ST1_TO_HS_TX_MASK (0x1U) -#define MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT (0U) -#define MIPI_DSI_INT_ST1_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_ST1_TO_HS_TX_MASK) >> MIPI_DSI_INT_ST1_TO_HS_TX_SHIFT) - -/* Bitfield definition for register: INT_MSK0 */ -/* - * MASK_DPHY_ERRORS_4 (RW) - * - * disable LP1 contention error ErrContentionLP1 from lane0 - */ -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK (0x100000UL) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT (20U) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_4_SHIFT) - -/* - * MASK_DPHY_ERRORS_3 (RW) - * - * disable LP0 contention error ErrContentionLP0 from lane0 - */ -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK (0x80000UL) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT (19U) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_3_SHIFT) - -/* - * MASK_DPHY_ERRORS_2 (RW) - * - * disable control error ErrControl from lane0 - */ -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK (0x40000UL) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT (18U) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_2_SHIFT) - -/* - * MASK_DPHY_ERRORS_1 (RW) - * - * disable ErrSyncEsc low-power data transmission synchronization error from lane 0 - */ -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK (0x20000UL) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT (17U) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_1_SHIFT) - -/* - * MASK_DPHY_ERRORS_0 (RW) - * - * disable ErrEsc escape entry error from lane0 - */ -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK (0x10000UL) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT (16U) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) -#define MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_MSK0_MASK_DPHY_ERRORS_0_SHIFT) - -/* - * MASK_ACK_WITH_ERR_15 (RW) - * - * disable the DSI protocal violation from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK (0x8000U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT (15U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_15_SHIFT) - -/* - * MASK_ACK_WITH_ERR_14 (RW) - * - * disable the reserved from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK (0x4000U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT (14U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_14_SHIFT) - -/* - * MASK_ACK_WITH_ERR_13 (RW) - * - * disable the invalid transmission length from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK (0x2000U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT (13U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_13_SHIFT) - -/* - * MASK_ACK_WITH_ERR_12 (RW) - * - * disable the dsi vc id invalid from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK (0x1000U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT (12U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_12_SHIFT) - -/* - * MASK_ACK_WITH_ERR_11 (RW) - * - * disable the not recongnized dsi data type from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK (0x800U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT (11U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_11_SHIFT) - -/* - * MASK_ACK_WITH_ERR_10 (RW) - * - * disable the checksum error from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK (0x400U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT (10U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_10_SHIFT) - -/* - * MASK_ACK_WITH_ERR_9 (RW) - * - * disable the ECC error multi-bit from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK (0x200U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT (9U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR_9_SHIFT) - -/* - * MASK_ACK_WITH_ERR8 (RW) - * - * disable the ecc error sigle-bit from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK (0x100U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT (8U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR8_SHIFT) - -/* - * MASK_ACK_WITH_ERR7 (RW) - * - * disable the reserved from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK (0x80U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT (7U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR7_SHIFT) - -/* - * MASK_ACK_WITH_ERR6 (RW) - * - * disable the false control error fro the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK (0x40U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT (6U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR6_SHIFT) - -/* - * MASK_ACK_WITH_ERR5 (RW) - * - * disable the peripheral timeout error from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK (0x20U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT (5U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR5_SHIFT) - -/* - * MASK_ACK_WITH_ERR4 (RW) - * - * disable the LP transmit sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK (0x10U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT (4U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR4_SHIFT) - -/* - * MASK_ACK_WITH_ERR3 (RW) - * - * disable the Escap mode entry command error from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK (0x8U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT (3U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR3_SHIFT) - -/* - * MASK_ACK_WITH_ERR2 (RW) - * - * disable the EoT sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK (0x4U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT (2U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR2_SHIFT) - -/* - * MASK_ACK_WITH_ERR1 (RW) - * - * disable the SoT sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK (0x2U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT (1U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR1_SHIFT) - -/* - * MASK_ACK_WITH_ERR0 (RW) - * - * disable the SoT serror from the acknowledge error report - */ -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK (0x1U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT (0U) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) -#define MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_MSK0_MASK_ACK_WITH_ERR0_SHIFT) - -/* Bitfield definition for register: INT_MSK1 */ -/* - * MASK_TEAR_REQUEST_ERR (RW) - * - * disable tear_request has occurred but tear effect is not active in dsi host and device - */ -#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK (0x100000UL) -#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT (20U) -#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_TEAR_REQUEST_ERR_SHIFT) - -/* - * MASK_DPI_BUFF_PLD_UNDER (RW) - * - * disable an underflow when reading payload to build dsi packet for video mode - */ -#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) -#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT (19U) -#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) -#define MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BUFF_PLD_UNDER_SHIFT) - -/* - * MASK_GEN_PLD_RECEV_ERR (RW) - * - * disable that during a generic interface packet read back, the payload FIFO full - */ -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK (0x1000U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT (12U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RECEV_ERR_SHIFT) - -/* - * MASK_GEN_PLD_RD_ERR (RW) - * - * disable that during a DCS read data, the payload FIFO becomes empty - */ -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK (0x800U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT (11U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_RD_ERR_SHIFT) - -/* - * MASK_GEN_PLD_SEND_ERR (RW) - * - * disable the payload FIFO become empty when packet build - */ -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK (0x400U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT (10U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_SEND_ERR_SHIFT) - -/* - * MASK_GEN_PLD_WR_ERR (RW) - * - * disable the system tried to write a payload and FIFO is full - */ -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK (0x200U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT (9U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_PLD_WR_ERR_SHIFT) - -/* - * MASK_GEN_CMD_WR_ERR (RW) - * - * disable the system tried to write a command and FIFO is full - */ -#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK (0x100U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT (8U) -#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_GEN_CMD_WR_ERR_SHIFT) - -/* - * MASK_DPI_BPLD_WR_ERR (RW) - * - * disable the payload FIFO is full during a DPI pixel line storage - */ -#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK (0x80U) -#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT (7U) -#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_DPI_BPLD_WR_ERR_SHIFT) - -/* - * MASK_EOPT_ERR (RW) - * - * disable that the EoTp packet has not been received at the end of the incoming peripheral transmission - */ -#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK (0x40U) -#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT (6U) -#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_EOPT_ERR_SHIFT) - -/* - * MASK_PKT_SIZE_ERR (RW) - * - * disable that the packet size error has been detected during the packet reception - */ -#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK (0x20U) -#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT (5U) -#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_PKT_SIZE_ERR_SHIFT) - -/* - * MASK_CRC_ERR (RW) - * - * disable that the CRC error has been detected in the reveived packet payload - */ -#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK (0x10U) -#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT (4U) -#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_CRC_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_CRC_ERR_SHIFT) - -/* - * MASK_ECC_MULTI_ERR (RW) - * - * disable that the ECC multiple error has been detected in a revieved packet - */ -#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK (0x8U) -#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT (3U) -#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_MULTI_ERR_SHIFT) - -/* - * MASK_ECC_SIGLE_ERR (RW) - * - * disable that the ECC single error has been detected and corrected in a reveived packet - */ -#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK (0x4U) -#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT (2U) -#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) -#define MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_MSK1_MASK_ECC_SIGLE_ERR_SHIFT) - -/* - * MASK_TO_LP_TX (RW) - * - * disable that the low-power reception timeout counter reached the end and contention has been detected - */ -#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK (0x2U) -#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT (1U) -#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) -#define MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_LP_TX_SHIFT) - -/* - * MASK_TO_HS_TX (RW) - * - * disable that the high-speed transmission timeout counter reached the end and contention has been detected - */ -#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK (0x1U) -#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT (0U) -#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) -#define MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_MASK) >> MIPI_DSI_INT_MSK1_MASK_TO_HS_TX_SHIFT) - -/* Bitfield definition for register: PHY_CAL */ -/* - * TXSKEWCALHS (RW) - * - * High-speed skew calibration is started when txskewcalhs is - * set high (assuming that PHY is in Stop state) - */ -#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK (0x1U) -#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT (0U) -#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) -#define MIPI_DSI_PHY_CAL_TXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_CAL_TXSKEWCALHS_MASK) >> MIPI_DSI_PHY_CAL_TXSKEWCALHS_SHIFT) - -/* Bitfield definition for register: INT_FORCE0 */ -/* - * FORCE_DPHY_ERRORS_4 (RW) - * - * force LP1 contention error ErrContentionLP1 from lane0 - */ -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK (0x100000UL) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT (20U) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_4_SHIFT) - -/* - * FORCE_DPHY_ERRORS_3 (RW) - * - * force LP0 contention error ErrContentionLP0 from lane0 - */ -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK (0x80000UL) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT (19U) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_3_SHIFT) - -/* - * FORCE_DPHY_ERRORS_2 (RW) - * - * force control error ErrControl from lane0 - */ -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK (0x40000UL) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT (18U) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_2_SHIFT) - -/* - * FORCE_DPHY_ERRORS_1 (RW) - * - * force ErrSyncEsc low-power data transmission synchronization error from lane 0 - */ -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK (0x20000UL) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT (17U) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_1_SHIFT) - -/* - * FORCE_DPHY_ERRORS_0 (RW) - * - * force ErrEsc escape entry error from lane0 - */ -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK (0x10000UL) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT (16U) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_DPHY_ERRORS_0_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_15 (RW) - * - * force the DSI protocal violation from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK (0x8000U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT (15U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_15_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_14 (RW) - * - * force the reserved from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK (0x4000U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT (14U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_14_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_13 (RW) - * - * force the invalid transmission length from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK (0x2000U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT (13U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_13_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_12 (RW) - * - * force the dsi vc id invalid from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK (0x1000U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT (12U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_12_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_11 (RW) - * - * force the not recongnized dsi data type from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK (0x800U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT (11U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_11_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_10 (RW) - * - * force the checksum error from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK (0x400U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT (10U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_10_SHIFT) - -/* - * FORCE_ACK_WITH_ERR_9 (RW) - * - * force the ECC error multi-bit from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK (0x200U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT (9U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR_9_SHIFT) - -/* - * FORCE_ACK_WITH_ERR8 (RW) - * - * force the ecc error sigle-bit from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK (0x100U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT (8U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR8_SHIFT) - -/* - * FORCE_ACK_WITH_ERR7 (RW) - * - * force the reserved from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK (0x80U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT (7U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR7_SHIFT) - -/* - * FORCE_ACK_WITH_ERR6 (RW) - * - * force the false control error fro the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK (0x40U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT (6U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR6_SHIFT) - -/* - * FORCE_ACK_WITH_ERR5 (RW) - * - * force the peripheral timeout error from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK (0x20U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT (5U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR5_SHIFT) - -/* - * FORCE_ACK_WITH_ERR4 (RW) - * - * force the LP transmit sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK (0x10U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT (4U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR4_SHIFT) - -/* - * FORCE_ACK_WITH_ERR3 (RW) - * - * force the Escap mode entry command error from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK (0x8U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT (3U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR3_SHIFT) - -/* - * FORCE_ACK_WITH_ERR2 (RW) - * - * force the EoT sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK (0x4U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT (2U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR2_SHIFT) - -/* - * FORCE_ACK_WITH_ERR1 (RW) - * - * force the SoT sync error from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK (0x2U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT (1U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR1_SHIFT) - -/* - * FORCE_ACK_WITH_ERR0 (RW) - * - * force the SoT serror from the acknowledge error report - */ -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK (0x1U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT (0U) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) -#define MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_MASK) >> MIPI_DSI_INT_FORCE0_FORCE_ACK_WITH_ERR0_SHIFT) - -/* Bitfield definition for register: INT_FORCE1 */ -/* - * FORCE_TEAR_REQUEST_ERR (RW) - * - * force tear_request has occurred but tear effect is not active in dsi host and device - */ -#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK (0x100000UL) -#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT (20U) -#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TEAR_REQUEST_ERR_SHIFT) - -/* - * FORCE_DPI_BUFF_PLD_UNDER (RW) - * - * force an underflow when reading payload to build dsi packet for video mode - */ -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK (0x80000UL) -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT (19U) -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BUFF_PLD_UNDER_SHIFT) - -/* - * FORCE_GEN_PLD_RECEV_ERR (RW) - * - * force that during a generic interface packet read back, the payload FIFO full - */ -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK (0x1000U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT (12U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RECEV_ERR_SHIFT) - -/* - * FORCE_GEN_PLD_RD_ERR (RW) - * - * force that during a DCS read data, the payload FIFO becomes empty - */ -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK (0x800U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT (11U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_RD_ERR_SHIFT) - -/* - * FORCE_GEN_PLD_SEND_ERR (RW) - * - * force the payload FIFO become empty when packet build - */ -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK (0x400U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT (10U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_SEND_ERR_SHIFT) - -/* - * FORCE_GEN_PLD_WR_ERR (RW) - * - * force the system tried to write a payload and FIFO is full - */ -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK (0x200U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT (9U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_PLD_WR_ERR_SHIFT) - -/* - * FORCE_GEN_CMD_WR_ERR (RW) - * - * force the system tried to write a command and FIFO is full - */ -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK (0x100U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT (8U) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_GEN_CMD_WR_ERR_SHIFT) - -/* - * FORCE_DPI_BPLD_WR_ERR (RW) - * - * force the payload FIFO is full during a DPI pixel line storage - */ -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK (0x80U) -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT (7U) -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_DPI_BPLD_WR_ERR_SHIFT) - -/* - * FORCE_EOPT_ERR (RW) - * - * force that the EoTp packet has not been received at the end of the incoming peripheral transmission - */ -#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK (0x40U) -#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT (6U) -#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_EOPT_ERR_SHIFT) - -/* - * FORCE_PKT_SIZE_ERR (RW) - * - * force that the packet size error has been detected during the packet reception - */ -#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK (0x20U) -#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT (5U) -#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_PKT_SIZE_ERR_SHIFT) - -/* - * FORCE_CRC_ERR (RW) - * - * force that the CRC error has been detected in the reveived packet payload - */ -#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK (0x10U) -#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT (4U) -#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_CRC_ERR_SHIFT) - -/* - * FORCE_ECC_MULTI_ERR (RW) - * - * force that the ECC multiple error has been detected in a revieved packet - */ -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK (0x8U) -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT (3U) -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_MULTI_ERR_SHIFT) - -/* - * FORCE_ECC_SIGLE_ERR (RW) - * - * force that the ECC single error has been detected and corrected in a reveived packet - */ -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK (0x4U) -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT (2U) -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_ECC_SIGLE_ERR_SHIFT) - -/* - * FORCE_TO_LP_TX (RW) - * - * force that the low-power reception timeout counter reached the end and contention has been detected - */ -#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK (0x2U) -#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT (1U) -#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_LP_TX_SHIFT) - -/* - * FORCE_TO_HS_TX (RW) - * - * force that the high-speed transmission timeout counter reached the end and contention has been detected - */ -#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK (0x1U) -#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT (0U) -#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SET(x) (((uint32_t)(x) << MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) -#define MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_GET(x) (((uint32_t)(x) & MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_MASK) >> MIPI_DSI_INT_FORCE1_FORCE_TO_HS_TX_SHIFT) - -/* Bitfield definition for register: PHY_TMR_RD */ -/* - * MAX_RD_TIME (RW) - * - * the maximum time required to perform a read command in lane byte clock cycles. - */ -#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK (0x7FFFU) -#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT (0U) -#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) -#define MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_MASK) >> MIPI_DSI_PHY_TMR_RD_MAX_RD_TIME_SHIFT) - -/* Bitfield definition for register: AUTO_ULPS_MIN_TIME */ -/* - * ULPS_MIN_TIME (RW) - * - * configures the minimum time required by phy between ulpsactivenot and ulpsexitreq for clock and data lane - */ -#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK (0xFFFU) -#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT (0U) -#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SET(x) (((uint32_t)(x) << MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) -#define MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_MASK) >> MIPI_DSI_AUTO_ULPS_MIN_TIME_ULPS_MIN_TIME_SHIFT) - -/* Bitfield definition for register: PHY_MODE */ -/* - * PHY_MODE (RW) - * - * sel DPHY or CPHY - */ -#define MIPI_DSI_PHY_MODE_PHY_MODE_MASK (0x1U) -#define MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT (0U) -#define MIPI_DSI_PHY_MODE_PHY_MODE_SET(x) (((uint32_t)(x) << MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) -#define MIPI_DSI_PHY_MODE_PHY_MODE_GET(x) (((uint32_t)(x) & MIPI_DSI_PHY_MODE_PHY_MODE_MASK) >> MIPI_DSI_PHY_MODE_PHY_MODE_SHIFT) - -/* Bitfield definition for register: VID_SHADOW_CTRL */ -/* - * VID_SHADOW_PIN_REQ (RW) - * - * when set to 1, the video request is done by external pin - */ -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK (0x10000UL) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT (16U) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_PIN_REQ_SHIFT) - -/* - * VID_SHADOW_REQ (RW) - * - * when set to 1, request that the dpi register from regbank are copied to the auxiliary registers - */ -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK (0x100U) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT (8U) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_REQ_SHIFT) - -/* - * VID_SHADOW_EN (RW) - * - * when set to 1, DPI receives the active configuration from the auxiliary register - */ -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK (0x1U) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT (0U) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SET(x) (((uint32_t)(x) << MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) -#define MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_MASK) >> MIPI_DSI_VID_SHADOW_CTRL_VID_SHADOW_EN_SHIFT) - -/* Bitfield definition for register: DPI_VCID_ACT */ -/* - * DPI_VCID (R) - * - * specifies the DPI virtual channel id that is indexed to the video mode packets - */ -#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK (0x3U) -#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT (0U) -#define MIPI_DSI_DPI_VCID_ACT_DPI_VCID_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_VCID_ACT_DPI_VCID_MASK) >> MIPI_DSI_DPI_VCID_ACT_DPI_VCID_SHIFT) - -/* Bitfield definition for register: DPI_COLOR_CODING_ACT */ -/* - * LOOSELY18_EN (R) - * - * avtivates loosely packed variant to 18-bit configuration - */ -#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK (0x100U) -#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT (8U) -#define MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_LOOSELY18_EN_SHIFT) - -/* - * DIP_COLOR_CODING (R) - * - * configures the DPI color for video mode - */ -#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK (0xFU) -#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT (0U) -#define MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_MASK) >> MIPI_DSI_DPI_COLOR_CODING_ACT_DIP_COLOR_CODING_SHIFT) - -/* Bitfield definition for register: DPI_LP_CMD_TIM_ACT */ -/* - * OUTVACT_LPCMD_TIME (R) - * - * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the VSA VBP and VFP regions. - */ -#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK (0xFF0000UL) -#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT (16U) -#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_OUTVACT_LPCMD_TIME_SHIFT) - -/* - * INVACT_LPCMD_TIME (R) - * - * transmission of commands in low-power mode, it specifies the size in bytes of the lagest packet that can fit in a line during the vact regions. - */ -#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK (0xFFU) -#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT (0U) -#define MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_MASK) >> MIPI_DSI_DPI_LP_CMD_TIM_ACT_INVACT_LPCMD_TIME_SHIFT) - -/* Bitfield definition for register: VID_MODE_CFG_ACT */ -/* - * LP_CMD_EN (R) - * - * enable the command transmission only in low-power mode - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK (0x200U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT (9U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_CMD_EN_SHIFT) - -/* - * FRAME_BTA_ACK_EN (R) - * - * enable the request for an acknowledge response at the end of a frame - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK (0x100U) -#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT (8U) -#define MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_FRAME_BTA_ACK_EN_SHIFT) - -/* - * LP_HFP_EN (R) - * - * enable the returne to low-power inside the HFP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK (0x80U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT (7U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HFP_EN_SHIFT) - -/* - * LP_HBP_EN (R) - * - * enable the returne to low-power inside the HBP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK (0x40U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT (6U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_HBP_EN_SHIFT) - -/* - * LP_VACT_EN (R) - * - * enable the returne to low-power inside the VACT period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK (0x20U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT (5U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VACT_EN_SHIFT) - -/* - * LP_VFP_EN (R) - * - * enable the returne to low-power inside the VFP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK (0x10U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT (4U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VFP_EN_SHIFT) - -/* - * LP_VBP_EN (R) - * - * enable the returne to low-power inside the VBP period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK (0x8U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT (3U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VBP_EN_SHIFT) - -/* - * LP_VSA_EN (R) - * - * enable the returne to low-power inside the VSA period when timing allows - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK (0x4U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT (2U) -#define MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_LP_VSA_EN_SHIFT) - -/* - * VID_MODE_TYPE (R) - * - * specifies the video mode transmission type - */ -#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK (0x3U) -#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT (0U) -#define MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_MASK) >> MIPI_DSI_VID_MODE_CFG_ACT_VID_MODE_TYPE_SHIFT) - -/* Bitfield definition for register: VID_PKT_SIZE_ACT */ -/* - * VID_PKT_SIZE (R) - * - * the number of pixels in a single video packet - */ -#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK (0x3FFFU) -#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT (0U) -#define MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_MASK) >> MIPI_DSI_VID_PKT_SIZE_ACT_VID_PKT_SIZE_SHIFT) - -/* Bitfield definition for register: VID_NUM_CHUNKS_ACT */ -/* - * VID_NUM_CHUNKS (R) - * - * the number of chunks to be transmitted during a line period - */ -#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK (0x1FFFU) -#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT (0U) -#define MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_MASK) >> MIPI_DSI_VID_NUM_CHUNKS_ACT_VID_NUM_CHUNKS_SHIFT) - -/* Bitfield definition for register: VID_NULL_SIZE_ACT */ -/* - * VID_NULL_SIZE (R) - * - * the number of bytes in side a null packet - */ -#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK (0x1FFFU) -#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT (0U) -#define MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_MASK) >> MIPI_DSI_VID_NULL_SIZE_ACT_VID_NULL_SIZE_SHIFT) - -/* Bitfield definition for register: VID_HSA_TIME_ACT */ -/* - * VID_HSA_TIME (R) - * - * the horizontal synchronism active period in lane byte clock cycles - */ -#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK (0xFFFU) -#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT (0U) -#define MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_MASK) >> MIPI_DSI_VID_HSA_TIME_ACT_VID_HSA_TIME_SHIFT) - -/* Bitfield definition for register: VID_HBP_TIME_ACT */ -/* - * VID_HBP_TIME (R) - * - * the horizontal back porch period in lane byte clock cycles - */ -#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK (0xFFFU) -#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT (0U) -#define MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_MASK) >> MIPI_DSI_VID_HBP_TIME_ACT_VID_HBP_TIME_SHIFT) - -/* Bitfield definition for register: VID_HLINE_TIME_ACT */ -/* - * VID_HLINE_TIME (R) - * - * the size of total line: hsa+hbp+hact+hfp - */ -#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK (0x7FFFU) -#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT (0U) -#define MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_MASK) >> MIPI_DSI_VID_HLINE_TIME_ACT_VID_HLINE_TIME_SHIFT) - -/* Bitfield definition for register: VID_VSA_LINES_ACT */ -/* - * VSA_LINES (R) - * - * vertical synchronism active period - */ -#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK (0x3FFU) -#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_MASK) >> MIPI_DSI_VID_VSA_LINES_ACT_VSA_LINES_SHIFT) - -/* Bitfield definition for register: VID_VBP_LINES_ACT */ -/* - * VBP_LINES (R) - * - * vertical back porch period - */ -#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK (0x3FFU) -#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_MASK) >> MIPI_DSI_VID_VBP_LINES_ACT_VBP_LINES_SHIFT) - -/* Bitfield definition for register: VID_VFP_LINES_ACT */ -/* - * VFP_LINES (R) - * - * vertical porch period - */ -#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK (0x3FFU) -#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_MASK) >> MIPI_DSI_VID_VFP_LINES_ACT_VFP_LINES_SHIFT) - -/* Bitfield definition for register: VID_VACTIVE_LINES_ACT */ -/* - * V_ACTIVE_LINES (R) - * - * vertical active period - */ -#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK (0x3FFFU) -#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT (0U) -#define MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_MASK) >> MIPI_DSI_VID_VACTIVE_LINES_ACT_V_ACTIVE_LINES_SHIFT) - -/* Bitfield definition for register: VID_PKT_STATUS */ -/* - * DPI_BUFF_PLD_FULL (R) - * - * This bit indicates the full status of the payload internal buffer - * for video Mode. This bit is set to 0 for command Mode - */ -#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK (0x20000UL) -#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT (17U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_FULL_SHIFT) - -/* - * DPI_BUFF_PLD_EMPTY (R) - * - * This bit indicates the empty status of the payload internal - * buffer for video Mode. This bit is set to 0 for command Mod - */ -#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK (0x10000UL) -#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT (16U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_BUFF_PLD_EMPTY_SHIFT) - -/* - * DPI_PLD_W_FULL (R) - * - * This bit indicates the full status of write payload FIFO for - * video Mode. This bit is set to 0 for command Mode - */ -#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK (0x8U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT (3U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_FULL_SHIFT) - -/* - * DPI_PLD_W_EMPTY (R) - * - * This bit indicates the empty status of write payload FIFO for - * video Mode. This bit is set to 0 for command Mode - */ -#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK (0x4U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT (2U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_PLD_W_EMPTY_SHIFT) - -/* - * DPI_CMD_W_FULL (R) - * - * This bit indicates the full status of write command FIFO for - * video Mode. This bit is set to 0 for command Mode - */ -#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK (0x2U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT (1U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_FULL_SHIFT) - -/* - * DPI_CMD_W_EMPTY (R) - * - * This bit indicates the empty status of write command FIFO - * for video Mode. This bit is set to 0 for command Mode - */ -#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK (0x1U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT (0U) -#define MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_GET(x) (((uint32_t)(x) & MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_MASK) >> MIPI_DSI_VID_PKT_STATUS_DPI_CMD_W_EMPTY_SHIFT) - -/* Bitfield definition for register: SDF_3D_ACT */ -/* - * SEND_3D_CFG (R) - * - * When set, causes the next VSS packet to include 3D control - * payload in every VSS packet. - */ -#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK (0x10000UL) -#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT (16U) -#define MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_MASK) >> MIPI_DSI_SDF_3D_ACT_SEND_3D_CFG_SHIFT) - -/* - * RIGHT_FIRST (R) - * - * This bit specifies the left/right order - */ -#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK (0x20U) -#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT (5U) -#define MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_MASK) >> MIPI_DSI_SDF_3D_ACT_RIGHT_FIRST_SHIFT) - -/* - * SECOND_VSYNC (R) - * - * This field specifies whether there is a second VSYNC pulse - * between Left and Right Images, when 3D Image Format is - * Frame-based - */ -#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK (0x10U) -#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT (4U) -#define MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_MASK) >> MIPI_DSI_SDF_3D_ACT_SECOND_VSYNC_SHIFT) - -/* - * FORMAT_3D (R) - * - * This field specifies 3D Image Format - */ -#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK (0xCU) -#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT (2U) -#define MIPI_DSI_SDF_3D_ACT_FORMAT_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_FORMAT_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_FORMAT_3D_SHIFT) - -/* - * MODE_3D (R) - * - * This field specifies 3D Mode On/Off and Display Orientation - */ -#define MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK (0x3U) -#define MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT (0U) -#define MIPI_DSI_SDF_3D_ACT_MODE_3D_GET(x) (((uint32_t)(x) & MIPI_DSI_SDF_3D_ACT_MODE_3D_MASK) >> MIPI_DSI_SDF_3D_ACT_MODE_3D_SHIFT) - - - - -#endif /* HPM_MIPI_DSI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mon_regs.h deleted file mode 100644 index ddc1f854707..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mon_regs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MON_H -#define HPM_MON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[4]; - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - __RW uint32_t IRQ_FLAG; /* 0x40: */ - __RW uint32_t IRQ_ENABLE; /* 0x44: */ -} MON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define MON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define MON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define MON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << MON_MONITOR_CONTROL_ACTIVE_SHIFT) & MON_MONITOR_CONTROL_ACTIVE_MASK) -#define MON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & MON_MONITOR_CONTROL_ACTIVE_MASK) >> MON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define MON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define MON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define MON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MON_MONITOR_CONTROL_ENABLE_SHIFT) & MON_MONITOR_CONTROL_ENABLE_MASK) -#define MON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MON_MONITOR_CONTROL_ENABLE_MASK) >> MON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define MON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define MON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define MON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << MON_MONITOR_STATUS_FLAG_SHIFT) & MON_MONITOR_STATUS_FLAG_MASK) -#define MON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & MON_MONITOR_STATUS_FLAG_MASK) >> MON_MONITOR_STATUS_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_FLAG */ -/* - * FLAG (RW) - * - * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt - * 1: monitor interrupt happened - */ -#define MON_IRQ_FLAG_FLAG_MASK (0xFU) -#define MON_IRQ_FLAG_FLAG_SHIFT (0U) -#define MON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << MON_IRQ_FLAG_FLAG_SHIFT) & MON_IRQ_FLAG_FLAG_MASK) -#define MON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & MON_IRQ_FLAG_FLAG_MASK) >> MON_IRQ_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * ENABLE (RW) - * - * interrupt enable, each bit represents for one monitor - * 0: monitor interrupt disabled - * 1: monitor interrupt enabled - */ -#define MON_IRQ_ENABLE_ENABLE_MASK (0xFU) -#define MON_IRQ_ENABLE_ENABLE_SHIFT (0U) -#define MON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << MON_IRQ_ENABLE_ENABLE_SHIFT) & MON_IRQ_ENABLE_ENABLE_MASK) -#define MON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & MON_IRQ_ENABLE_ENABLE_MASK) >> MON_IRQ_ENABLE_ENABLE_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define MON_MONITOR_GLITCH0 (0UL) -#define MON_MONITOR_GLITCH1 (1UL) -#define MON_MONITOR_CLOCK0 (2UL) -#define MON_MONITOR_CLOCK1 (3UL) - - -#endif /* HPM_MON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mono_regs.h deleted file mode 100644 index 2c6c3a3d2fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_mono_regs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MONO_H -#define HPM_MONO_H - -typedef struct { - __RW uint32_t MONOL; /* 0x0: Low part of monotonic counter */ - __RW uint32_t MONOH; /* 0x4: High part of monotonic counter */ -} MONO_Type; - - -/* Bitfield definition for register: MONOL */ -/* - * COUNTER (RW) - * - * low part of monotonica counter, write to this counter will cause counter increase by 1 - */ -#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) -#define MONO_MONOL_COUNTER_SHIFT (0U) -#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) -#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) - -/* Bitfield definition for register: MONOH */ -/* - * EPOCH (RW) - * - * Fuse value for high part of monotonica - */ -#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) -#define MONO_MONOH_EPOCH_SHIFT (16U) -#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) -#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) - -/* - * COUNTER (RW) - * - * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - */ -#define MONO_MONOH_COUNTER_MASK (0xFFFFU) -#define MONO_MONOH_COUNTER_SHIFT (0U) -#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) -#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) - - - - -#endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_otp_regs.h deleted file mode 100644 index feb5f9c2efe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_otp_regs.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OTP_H -#define HPM_OTP_H - -typedef struct { - __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ - __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ - __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ - __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ - __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ - __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ - __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ - __RW uint32_t DATA; /* 0x804: DATA */ - __RW uint32_t ADDR; /* 0x808: ADDR */ - __RW uint32_t CMD; /* 0x80C: CMD */ - __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ - __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ - __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ - __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ - __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ - __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ - __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ - __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ -} OTP_Type; - - -/* Bitfield definition for register array: SHADOW */ -/* - * SHADOW (RW) - * - * shadow register of fuse for pmic area - * for PMIC, index valid for 0-15, for SOC index valid for 16-128 - */ -#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_SHADOW_SHIFT (0U) -#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) -#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) - -/* Bitfield definition for register array: SHADOW_LOCK */ -/* - * LOCK (RW) - * - * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) -#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) -#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register array: FUSE */ -/* - * FUSE (RW) - * - * fuse array, valid in PMIC part only - * read operation will read out value in fuse array - * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - */ -#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_FUSE_SHIFT (0U) -#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) -#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) - -/* Bitfield definition for register array: FUSE_LOCK */ -/* - * LOCK (RW) - * - * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) -#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) -#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK (RW) - * - * unlock word for fuse array operation - * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. - * Please make sure 24M crystal is running and 2.5V LDO working properly - */ -#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) -#define OTP_UNLOCK_UNLOCK_SHIFT (0U) -#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) -#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * data register for non-blocking access - * this register hold dat read from fuse array or data to by programmed to fuse array - */ -#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) -#define OTP_DATA_DATA_SHIFT (0U) -#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) -#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * word address to be read or write - */ -#define OTP_ADDR_ADDR_MASK (0x7FU) -#define OTP_ADDR_ADDR_SHIFT (0U) -#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) -#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * command to access fure array - * "BLOW" will update fuse word at ADDR to value hold in DATA - * "READ" will fetch fuse value in at ADDR to DATA register - */ -#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) -#define OTP_CMD_CMD_SHIFT (0U) -#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) -#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) - -/* Bitfield definition for register: LOAD_REQ */ -/* - * REQUEST (RW) - * - * reload request for 4 regions - * bit0: region0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) -#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) -#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) -#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) - -/* Bitfield definition for register: LOAD_COMP */ -/* - * COMPLETE (RW) - * - * reload complete sign for 4 regions - * bit0: region 0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) -#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) -#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) -#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) - -/* Bitfield definition for register array: REGION */ -/* - * STOP (RW) - * - * stop address of load region, fuse word at end address will NOT be reloaded - * region0: fixed at 8 - * region1: fixed at 16 - * region2: fixed at 0, - * region3: usrer configurable - */ -#define OTP_REGION_STOP_MASK (0x7F00U) -#define OTP_REGION_STOP_SHIFT (8U) -#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) -#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) - -/* - * START (RW) - * - * start address of load region, fuse word at start address will be reloaded - * region0: fixed at 0 - * region1: fixed at 8 - * region2: fixed at 16, - * region3: usrer configurable - */ -#define OTP_REGION_START_MASK (0x7FU) -#define OTP_REGION_START_SHIFT (0U) -#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) -#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) - -/* Bitfield definition for register: INT_FLAG */ -/* - * WRITE (RW) - * - * fuse write flag, write 1 to clear - * 0: fuse is not written or writing - * 1: value in DATA register is programmed into fuse - */ -#define OTP_INT_FLAG_WRITE_MASK (0x4U) -#define OTP_INT_FLAG_WRITE_SHIFT (2U) -#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) -#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read flag, write 1 to clear - * 0: fuse is not read or reading - * 1: fuse value is put in DATA register - */ -#define OTP_INT_FLAG_READ_MASK (0x2U) -#define OTP_INT_FLAG_READ_SHIFT (1U) -#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) -#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load flag, write 1 to clear - * 0: fuse is not loaded or loading - * 1: fuse loaded - */ -#define OTP_INT_FLAG_LOAD_MASK (0x1U) -#define OTP_INT_FLAG_LOAD_SHIFT (0U) -#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) -#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRITE (RW) - * - * fuse write interrupt enable - * 0: fuse write interrupt is not enable - * 1: fuse write interrupt is enable - */ -#define OTP_INT_EN_WRITE_MASK (0x4U) -#define OTP_INT_EN_WRITE_SHIFT (2U) -#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) -#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read interrupt enable - * 0: fuse read interrupt is not enable - * 1: fuse read interrupt is enable - */ -#define OTP_INT_EN_READ_MASK (0x2U) -#define OTP_INT_EN_READ_SHIFT (1U) -#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) -#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load interrupt enable - * 0: fuse load interrupt is not enable - * 1: fuse load interrupt is enable - */ -#define OTP_INT_EN_LOAD_MASK (0x1U) -#define OTP_INT_EN_LOAD_SHIFT (0U) -#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) -#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) - - - -/* SHADOW register group index macro definition */ -#define OTP_SHADOW_SHADOW000 (0UL) -#define OTP_SHADOW_SHADOW001 (1UL) -#define OTP_SHADOW_SHADOW002 (2UL) -#define OTP_SHADOW_SHADOW003 (3UL) -#define OTP_SHADOW_SHADOW004 (4UL) -#define OTP_SHADOW_SHADOW005 (5UL) -#define OTP_SHADOW_SHADOW006 (6UL) -#define OTP_SHADOW_SHADOW007 (7UL) -#define OTP_SHADOW_SHADOW008 (8UL) -#define OTP_SHADOW_SHADOW009 (9UL) -#define OTP_SHADOW_SHADOW010 (10UL) -#define OTP_SHADOW_SHADOW011 (11UL) -#define OTP_SHADOW_SHADOW012 (12UL) -#define OTP_SHADOW_SHADOW013 (13UL) -#define OTP_SHADOW_SHADOW014 (14UL) -#define OTP_SHADOW_SHADOW015 (15UL) -#define OTP_SHADOW_SHADOW016 (16UL) -#define OTP_SHADOW_SHADOW017 (17UL) -#define OTP_SHADOW_SHADOW018 (18UL) -#define OTP_SHADOW_SHADOW019 (19UL) -#define OTP_SHADOW_SHADOW020 (20UL) -#define OTP_SHADOW_SHADOW021 (21UL) -#define OTP_SHADOW_SHADOW022 (22UL) -#define OTP_SHADOW_SHADOW023 (23UL) -#define OTP_SHADOW_SHADOW024 (24UL) -#define OTP_SHADOW_SHADOW025 (25UL) -#define OTP_SHADOW_SHADOW026 (26UL) -#define OTP_SHADOW_SHADOW027 (27UL) -#define OTP_SHADOW_SHADOW028 (28UL) -#define OTP_SHADOW_SHADOW029 (29UL) -#define OTP_SHADOW_SHADOW030 (30UL) -#define OTP_SHADOW_SHADOW031 (31UL) -#define OTP_SHADOW_SHADOW032 (32UL) -#define OTP_SHADOW_SHADOW033 (33UL) -#define OTP_SHADOW_SHADOW034 (34UL) -#define OTP_SHADOW_SHADOW035 (35UL) -#define OTP_SHADOW_SHADOW036 (36UL) -#define OTP_SHADOW_SHADOW037 (37UL) -#define OTP_SHADOW_SHADOW038 (38UL) -#define OTP_SHADOW_SHADOW039 (39UL) -#define OTP_SHADOW_SHADOW040 (40UL) -#define OTP_SHADOW_SHADOW041 (41UL) -#define OTP_SHADOW_SHADOW042 (42UL) -#define OTP_SHADOW_SHADOW043 (43UL) -#define OTP_SHADOW_SHADOW044 (44UL) -#define OTP_SHADOW_SHADOW045 (45UL) -#define OTP_SHADOW_SHADOW046 (46UL) -#define OTP_SHADOW_SHADOW047 (47UL) -#define OTP_SHADOW_SHADOW048 (48UL) -#define OTP_SHADOW_SHADOW049 (49UL) -#define OTP_SHADOW_SHADOW050 (50UL) -#define OTP_SHADOW_SHADOW051 (51UL) -#define OTP_SHADOW_SHADOW052 (52UL) -#define OTP_SHADOW_SHADOW053 (53UL) -#define OTP_SHADOW_SHADOW054 (54UL) -#define OTP_SHADOW_SHADOW055 (55UL) -#define OTP_SHADOW_SHADOW056 (56UL) -#define OTP_SHADOW_SHADOW057 (57UL) -#define OTP_SHADOW_SHADOW058 (58UL) -#define OTP_SHADOW_SHADOW059 (59UL) -#define OTP_SHADOW_SHADOW060 (60UL) -#define OTP_SHADOW_SHADOW061 (61UL) -#define OTP_SHADOW_SHADOW062 (62UL) -#define OTP_SHADOW_SHADOW063 (63UL) -#define OTP_SHADOW_SHADOW064 (64UL) -#define OTP_SHADOW_SHADOW065 (65UL) -#define OTP_SHADOW_SHADOW066 (66UL) -#define OTP_SHADOW_SHADOW067 (67UL) -#define OTP_SHADOW_SHADOW068 (68UL) -#define OTP_SHADOW_SHADOW069 (69UL) -#define OTP_SHADOW_SHADOW070 (70UL) -#define OTP_SHADOW_SHADOW071 (71UL) -#define OTP_SHADOW_SHADOW072 (72UL) -#define OTP_SHADOW_SHADOW073 (73UL) -#define OTP_SHADOW_SHADOW074 (74UL) -#define OTP_SHADOW_SHADOW075 (75UL) -#define OTP_SHADOW_SHADOW076 (76UL) -#define OTP_SHADOW_SHADOW077 (77UL) -#define OTP_SHADOW_SHADOW078 (78UL) -#define OTP_SHADOW_SHADOW079 (79UL) -#define OTP_SHADOW_SHADOW080 (80UL) -#define OTP_SHADOW_SHADOW081 (81UL) -#define OTP_SHADOW_SHADOW082 (82UL) -#define OTP_SHADOW_SHADOW083 (83UL) -#define OTP_SHADOW_SHADOW084 (84UL) -#define OTP_SHADOW_SHADOW085 (85UL) -#define OTP_SHADOW_SHADOW086 (86UL) -#define OTP_SHADOW_SHADOW087 (87UL) -#define OTP_SHADOW_SHADOW088 (88UL) -#define OTP_SHADOW_SHADOW089 (89UL) -#define OTP_SHADOW_SHADOW090 (90UL) -#define OTP_SHADOW_SHADOW091 (91UL) -#define OTP_SHADOW_SHADOW092 (92UL) -#define OTP_SHADOW_SHADOW093 (93UL) -#define OTP_SHADOW_SHADOW094 (94UL) -#define OTP_SHADOW_SHADOW095 (95UL) -#define OTP_SHADOW_SHADOW096 (96UL) -#define OTP_SHADOW_SHADOW097 (97UL) -#define OTP_SHADOW_SHADOW098 (98UL) -#define OTP_SHADOW_SHADOW099 (99UL) -#define OTP_SHADOW_SHADOW100 (100UL) -#define OTP_SHADOW_SHADOW101 (101UL) -#define OTP_SHADOW_SHADOW102 (102UL) -#define OTP_SHADOW_SHADOW103 (103UL) -#define OTP_SHADOW_SHADOW104 (104UL) -#define OTP_SHADOW_SHADOW105 (105UL) -#define OTP_SHADOW_SHADOW106 (106UL) -#define OTP_SHADOW_SHADOW107 (107UL) -#define OTP_SHADOW_SHADOW108 (108UL) -#define OTP_SHADOW_SHADOW109 (109UL) -#define OTP_SHADOW_SHADOW110 (110UL) -#define OTP_SHADOW_SHADOW111 (111UL) -#define OTP_SHADOW_SHADOW112 (112UL) -#define OTP_SHADOW_SHADOW113 (113UL) -#define OTP_SHADOW_SHADOW114 (114UL) -#define OTP_SHADOW_SHADOW115 (115UL) -#define OTP_SHADOW_SHADOW116 (116UL) -#define OTP_SHADOW_SHADOW117 (117UL) -#define OTP_SHADOW_SHADOW118 (118UL) -#define OTP_SHADOW_SHADOW119 (119UL) -#define OTP_SHADOW_SHADOW120 (120UL) -#define OTP_SHADOW_SHADOW121 (121UL) -#define OTP_SHADOW_SHADOW122 (122UL) -#define OTP_SHADOW_SHADOW123 (123UL) -#define OTP_SHADOW_SHADOW124 (124UL) -#define OTP_SHADOW_SHADOW125 (125UL) -#define OTP_SHADOW_SHADOW126 (126UL) -#define OTP_SHADOW_SHADOW127 (127UL) - -/* SHADOW_LOCK register group index macro definition */ -#define OTP_SHADOW_LOCK_LOCK00 (0UL) -#define OTP_SHADOW_LOCK_LOCK01 (1UL) -#define OTP_SHADOW_LOCK_LOCK02 (2UL) -#define OTP_SHADOW_LOCK_LOCK03 (3UL) -#define OTP_SHADOW_LOCK_LOCK04 (4UL) -#define OTP_SHADOW_LOCK_LOCK05 (5UL) -#define OTP_SHADOW_LOCK_LOCK06 (6UL) -#define OTP_SHADOW_LOCK_LOCK07 (7UL) - -/* FUSE register group index macro definition */ -#define OTP_FUSE_FUSE000 (0UL) -#define OTP_FUSE_FUSE001 (1UL) -#define OTP_FUSE_FUSE002 (2UL) -#define OTP_FUSE_FUSE003 (3UL) -#define OTP_FUSE_FUSE004 (4UL) -#define OTP_FUSE_FUSE005 (5UL) -#define OTP_FUSE_FUSE006 (6UL) -#define OTP_FUSE_FUSE007 (7UL) -#define OTP_FUSE_FUSE008 (8UL) -#define OTP_FUSE_FUSE009 (9UL) -#define OTP_FUSE_FUSE010 (10UL) -#define OTP_FUSE_FUSE011 (11UL) -#define OTP_FUSE_FUSE012 (12UL) -#define OTP_FUSE_FUSE013 (13UL) -#define OTP_FUSE_FUSE014 (14UL) -#define OTP_FUSE_FUSE015 (15UL) -#define OTP_FUSE_FUSE016 (16UL) -#define OTP_FUSE_FUSE017 (17UL) -#define OTP_FUSE_FUSE018 (18UL) -#define OTP_FUSE_FUSE019 (19UL) -#define OTP_FUSE_FUSE020 (20UL) -#define OTP_FUSE_FUSE021 (21UL) -#define OTP_FUSE_FUSE022 (22UL) -#define OTP_FUSE_FUSE023 (23UL) -#define OTP_FUSE_FUSE024 (24UL) -#define OTP_FUSE_FUSE025 (25UL) -#define OTP_FUSE_FUSE026 (26UL) -#define OTP_FUSE_FUSE027 (27UL) -#define OTP_FUSE_FUSE028 (28UL) -#define OTP_FUSE_FUSE029 (29UL) -#define OTP_FUSE_FUSE030 (30UL) -#define OTP_FUSE_FUSE031 (31UL) -#define OTP_FUSE_FUSE032 (32UL) -#define OTP_FUSE_FUSE033 (33UL) -#define OTP_FUSE_FUSE034 (34UL) -#define OTP_FUSE_FUSE035 (35UL) -#define OTP_FUSE_FUSE036 (36UL) -#define OTP_FUSE_FUSE037 (37UL) -#define OTP_FUSE_FUSE038 (38UL) -#define OTP_FUSE_FUSE039 (39UL) -#define OTP_FUSE_FUSE040 (40UL) -#define OTP_FUSE_FUSE041 (41UL) -#define OTP_FUSE_FUSE042 (42UL) -#define OTP_FUSE_FUSE043 (43UL) -#define OTP_FUSE_FUSE044 (44UL) -#define OTP_FUSE_FUSE045 (45UL) -#define OTP_FUSE_FUSE046 (46UL) -#define OTP_FUSE_FUSE047 (47UL) -#define OTP_FUSE_FUSE048 (48UL) -#define OTP_FUSE_FUSE049 (49UL) -#define OTP_FUSE_FUSE050 (50UL) -#define OTP_FUSE_FUSE051 (51UL) -#define OTP_FUSE_FUSE052 (52UL) -#define OTP_FUSE_FUSE053 (53UL) -#define OTP_FUSE_FUSE054 (54UL) -#define OTP_FUSE_FUSE055 (55UL) -#define OTP_FUSE_FUSE056 (56UL) -#define OTP_FUSE_FUSE057 (57UL) -#define OTP_FUSE_FUSE058 (58UL) -#define OTP_FUSE_FUSE059 (59UL) -#define OTP_FUSE_FUSE060 (60UL) -#define OTP_FUSE_FUSE061 (61UL) -#define OTP_FUSE_FUSE062 (62UL) -#define OTP_FUSE_FUSE063 (63UL) -#define OTP_FUSE_FUSE064 (64UL) -#define OTP_FUSE_FUSE065 (65UL) -#define OTP_FUSE_FUSE066 (66UL) -#define OTP_FUSE_FUSE067 (67UL) -#define OTP_FUSE_FUSE068 (68UL) -#define OTP_FUSE_FUSE069 (69UL) -#define OTP_FUSE_FUSE070 (70UL) -#define OTP_FUSE_FUSE071 (71UL) -#define OTP_FUSE_FUSE072 (72UL) -#define OTP_FUSE_FUSE073 (73UL) -#define OTP_FUSE_FUSE074 (74UL) -#define OTP_FUSE_FUSE075 (75UL) -#define OTP_FUSE_FUSE076 (76UL) -#define OTP_FUSE_FUSE077 (77UL) -#define OTP_FUSE_FUSE078 (78UL) -#define OTP_FUSE_FUSE079 (79UL) -#define OTP_FUSE_FUSE080 (80UL) -#define OTP_FUSE_FUSE081 (81UL) -#define OTP_FUSE_FUSE082 (82UL) -#define OTP_FUSE_FUSE083 (83UL) -#define OTP_FUSE_FUSE084 (84UL) -#define OTP_FUSE_FUSE085 (85UL) -#define OTP_FUSE_FUSE086 (86UL) -#define OTP_FUSE_FUSE087 (87UL) -#define OTP_FUSE_FUSE088 (88UL) -#define OTP_FUSE_FUSE089 (89UL) -#define OTP_FUSE_FUSE090 (90UL) -#define OTP_FUSE_FUSE091 (91UL) -#define OTP_FUSE_FUSE092 (92UL) -#define OTP_FUSE_FUSE093 (93UL) -#define OTP_FUSE_FUSE094 (94UL) -#define OTP_FUSE_FUSE095 (95UL) -#define OTP_FUSE_FUSE096 (96UL) -#define OTP_FUSE_FUSE097 (97UL) -#define OTP_FUSE_FUSE098 (98UL) -#define OTP_FUSE_FUSE099 (99UL) -#define OTP_FUSE_FUSE100 (100UL) -#define OTP_FUSE_FUSE101 (101UL) -#define OTP_FUSE_FUSE102 (102UL) -#define OTP_FUSE_FUSE103 (103UL) -#define OTP_FUSE_FUSE104 (104UL) -#define OTP_FUSE_FUSE105 (105UL) -#define OTP_FUSE_FUSE106 (106UL) -#define OTP_FUSE_FUSE107 (107UL) -#define OTP_FUSE_FUSE108 (108UL) -#define OTP_FUSE_FUSE109 (109UL) -#define OTP_FUSE_FUSE110 (110UL) -#define OTP_FUSE_FUSE111 (111UL) -#define OTP_FUSE_FUSE112 (112UL) -#define OTP_FUSE_FUSE113 (113UL) -#define OTP_FUSE_FUSE114 (114UL) -#define OTP_FUSE_FUSE115 (115UL) -#define OTP_FUSE_FUSE116 (116UL) -#define OTP_FUSE_FUSE117 (117UL) -#define OTP_FUSE_FUSE118 (118UL) -#define OTP_FUSE_FUSE119 (119UL) -#define OTP_FUSE_FUSE120 (120UL) -#define OTP_FUSE_FUSE121 (121UL) -#define OTP_FUSE_FUSE122 (122UL) -#define OTP_FUSE_FUSE123 (123UL) -#define OTP_FUSE_FUSE124 (124UL) -#define OTP_FUSE_FUSE125 (125UL) -#define OTP_FUSE_FUSE126 (126UL) -#define OTP_FUSE_FUSE127 (127UL) - -/* FUSE_LOCK register group index macro definition */ -#define OTP_FUSE_LOCK_LOCK00 (0UL) -#define OTP_FUSE_LOCK_LOCK01 (1UL) -#define OTP_FUSE_LOCK_LOCK02 (2UL) -#define OTP_FUSE_LOCK_LOCK03 (3UL) -#define OTP_FUSE_LOCK_LOCK04 (4UL) -#define OTP_FUSE_LOCK_LOCK05 (5UL) -#define OTP_FUSE_LOCK_LOCK06 (6UL) -#define OTP_FUSE_LOCK_LOCK07 (7UL) - -/* REGION register group index macro definition */ -#define OTP_REGION_LOAD_REGION0 (0UL) -#define OTP_REGION_LOAD_REGION1 (1UL) -#define OTP_REGION_LOAD_REGION2 (2UL) -#define OTP_REGION_LOAD_REGION3 (3UL) - - -#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pcfg_regs.h deleted file mode 100644 index 6ba4922766e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pcfg_regs.h +++ /dev/null @@ -1,1363 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PCFG_H -#define HPM_PCFG_H - -typedef struct { - __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ - __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ - __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ - __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ - __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ - __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ - __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ - __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ - __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ - __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ - __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ - __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ - __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t POWER_TRAP; /* 0x40: power trap */ - __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ - __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ - __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ - __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ - __RW uint32_t RC24M; /* 0x60: RC 24M config */ - __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ - __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ - __R uint32_t STATUS; /* 0x6C: RC 24M track status */ - __R uint8_t RESERVED3[16]; /* 0x70 - 0x7F: Reserved */ - __RW uint32_t DCDCM_MODE; /* 0x80: DCDCM mode select */ - __RW uint32_t DCDCM_LPMODE; /* 0x84: DCDCM low power mode */ - __RW uint32_t DCDCM_PROT; /* 0x88: DCDCM protection */ - __RW uint32_t DCDCM_CURRENT; /* 0x8C: DCDCM current estimation */ - __RW uint32_t DCDCM_ADVMODE; /* 0x90: DCDCM advance setting */ - __RW uint32_t DCDCM_ADVPARAM; /* 0x94: DCDCM advance parameter */ - __RW uint32_t DCDCM_MISC; /* 0x98: DCDCM misc parameter */ - __RW uint32_t DCDCM_DEBUG; /* 0x9C: DCDCM Debug */ - __RW uint32_t DCDCM_START_TIME; /* 0xA0: DCDCM ramp time */ - __RW uint32_t DCDCM_RESUME_TIME; /* 0xA4: DCDCM resume time */ - __RW uint32_t DCDCM_POWER_CONFIG; /* 0xA8: DCDCM power config */ -} PCFG_Type; - - -/* Bitfield definition for register: BANDGAP */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) -#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) -#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) -#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) - -/* - * LOWPOWER_MODE (RW) - * - * Banggap work in low power mode, banggap function limited - * 0: banggap works in normal mode - * 1: banggap works in low power mode - */ -#define PCFG_BANDGAP_LOWPOWER_MODE_MASK (0x2000000UL) -#define PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25U) -#define PCFG_BANDGAP_LOWPOWER_MODE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) -#define PCFG_BANDGAP_LOWPOWER_MODE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_LOWPOWER_MODE_MASK) >> PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Banggap work in power save mode, banggap function normally - * 0: banggap works in high performance mode - * 1: banggap works in power saving mode - */ -#define PCFG_BANDGAP_POWER_SAVE_MASK (0x1000000UL) -#define PCFG_BANDGAP_POWER_SAVE_SHIFT (24U) -#define PCFG_BANDGAP_POWER_SAVE_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_POWER_SAVE_SHIFT) & PCFG_BANDGAP_POWER_SAVE_MASK) -#define PCFG_BANDGAP_POWER_SAVE_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_POWER_SAVE_MASK) >> PCFG_BANDGAP_POWER_SAVE_SHIFT) - -/* - * VBG_1P0_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) -#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) - -/* - * VBG_P65_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) - -/* - * VBG_P50_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) -#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) -#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) - -/* Bitfield definition for register: LDO1P1 */ -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. - * 700: 700mV - * 720: 720mV - * . . . - * 1320:1320mV - */ -#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) -#define PCFG_LDO1P1_VOLT_SHIFT (0U) -#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) -#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) - -/* Bitfield definition for register: LDO2P5 */ -/* - * READY (RO) - * - * Ready flag, will set 1ms after enabled or voltage change - * 0: LDO is not ready for use - * 1: LDO is ready - */ -#define PCFG_LDO2P5_READY_MASK (0x10000000UL) -#define PCFG_LDO2P5_READY_SHIFT (28U) -#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) -#define PCFG_LDO2P5_ENABLE_SHIFT (16U) -#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) -#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. - * 2125: 2125mV - * 2150: 2150mV - * . . . - * 2900:2900mV - */ -#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) -#define PCFG_LDO2P5_VOLT_SHIFT (0U) -#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) -#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDC is applying new change - * 1: DCDC is ready - */ -#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDC_MODE_READY_SHIFT (28U) -#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDC work mode - * XX0: turn off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDC_MODE_MODE_SHIFT (16U) -#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) -#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) -#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) - -/* - * DISABLE_POWER_LOSS (RW) - * - * disable power loss protection - * 0: power loss protection enabled, DCDC shuts down when power loss - * 1: power loss protection disabled, DCDC try working after power voltage drop - */ -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT (23U) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) -#define PCFG_DCDC_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDC_PROT_DISABLE_POWER_LOSS_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * output over voltage protection - * 0: protection enabled, DCDC will shut down is output voltage is unexpected high - * 1: protection disabled, DCDC continue to adjust output voltage - */ -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on output detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A, - * 1: 1.3A - */ -#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDC_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDC current level, current level is num * 50mA - */ -#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDC_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) -#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) -#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDC_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDC_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) -#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) -#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) -#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) -#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) -#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) -#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) -#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) -#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDC internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) -#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled, - * 1: steping enabled - */ -#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) -#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDC_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDC voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) -#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - */ -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: POWER_TRAP */ -/* - * TRIGGERED (RW) - * - * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. - * 0: low power trap is not triggered - * 1: low power trap triggered - */ -#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) -#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) -#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) -#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) - -/* - * RETENTION (RW) - * - * DCDC enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDC - * 1: reduce DCDC voltage - */ -#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) -#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) -#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) -#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) - -/* - * TRAP (RW) - * - * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered - * 0: trap not enabled, pmic side low power function disabled - * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - */ -#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) -#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) -#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) -#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) - -/* Bitfield definition for register: WAKE_CAUSE */ -/* - * CAUSE (RW) - * - * wake up cause, each bit represents one wake up source, write 1 to clear the register bit - * 0: wake up source is not active during last wakeup - * 1: wake up source is active furing last wakeup - * bit 0: pmic_enable - * bit 5: VAD interrupt - * bit 6: VAD wake interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) -#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) -#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: WAKE_MASK */ -/* - * MASK (RW) - * - * mask for wake up sources, each bit represents one wakeup source - * 0: allow source to wake up system - * 1: disallow source to wakeup system - * bit 0: pmic_enable - * bit 5: VAD interrupt - * bit 6: VAD wake interrupt - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit16: Security violation in BATT - * bit17: GPIO in BATT interrupt - * bit19: RTC alarm interrupt - */ -#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_MASK_MASK_SHIFT (0U) -#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) -#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) - -/* Bitfield definition for register: SCG_CTRL */ -/* - * SCG (RW) - * - * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: reserved - * 10: clock is always off - * 11: clock is always on - * bit6-7:gpio - * bit8-9:ioc - * bit10-11: timer - * bit12-13:wdog - * bit14-15:uart - * bit16-17:VAD - * bit18-19:SRAM - */ -#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) -#define PCFG_SCG_CTRL_SCG_SHIFT (0U) -#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) -#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) - -/* Bitfield definition for register: RC24M */ -/* - * RC_TRIMMED (RW) - * - * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: RC is not trimmed - * 1: RC is trimmed - */ -#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) -#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) -#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) -#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) - -/* - * TRIM_C (RW) - * - * Coarse trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_C_MASK (0x700U) -#define PCFG_RC24M_TRIM_C_SHIFT (8U) -#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) -#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) - -/* - * TRIM_F (RW) - * - * Fine trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_F_MASK (0x1FU) -#define PCFG_RC24M_TRIM_F_SHIFT (0U) -#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) -#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) - -/* Bitfield definition for register: RC24M_TRACK */ -/* - * SEL24M (RW) - * - * Select track reference - * 0: select 32K as reference - * 1: select 24M XTAL as reference - */ -#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) -#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) -#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) -#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) - -/* - * RETURN (RW) - * - * Retrun default value when XTAL loss - * 0: remain last tracking value - * 1: switch to default value - */ -#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) -#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) -#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) -#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) - -/* - * TRACK (RW) - * - * track mode - * 0: RC24M free running - * 1: track RC24M to external XTAL - */ -#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) -#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) -#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) -#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) - -/* Bitfield definition for register: TRACK_TARGET */ -/* - * PRE_DIV (RW) - * - * Divider for reference source - */ -#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) -#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) -#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) -#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) - -/* - * TARGET (RW) - * - * Target frequency multiplier of divided source - */ -#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) -#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) -#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) -#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * SEL32K (RO) - * - * track is using XTAL32K - * 0: track is not using XTAL32K - * 1: track is using XTAL32K - */ -#define PCFG_STATUS_SEL32K_MASK (0x100000UL) -#define PCFG_STATUS_SEL32K_SHIFT (20U) -#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) - -/* - * SEL24M (RO) - * - * track is using XTAL24M - * 0: track is not using XTAL24M - * 1: track is using XTAL24M - */ -#define PCFG_STATUS_SEL24M_MASK (0x10000UL) -#define PCFG_STATUS_SEL24M_SHIFT (16U) -#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) - -/* - * EN_TRIM (RO) - * - * default value takes effect - * 0: default value is invalid - * 1: default value is valid - */ -#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) -#define PCFG_STATUS_EN_TRIM_SHIFT (15U) -#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) - -/* - * TRIM_C (RO) - * - * default coarse trim value - */ -#define PCFG_STATUS_TRIM_C_MASK (0x700U) -#define PCFG_STATUS_TRIM_C_SHIFT (8U) -#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) - -/* - * TRIM_F (RO) - * - * default fine trim value - */ -#define PCFG_STATUS_TRIM_F_MASK (0x1FU) -#define PCFG_STATUS_TRIM_F_SHIFT (0U) -#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) - -/* Bitfield definition for register: DCDCM_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDCM is applying new change - * 1: DCDCM is ready - */ -#define PCFG_DCDCM_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDCM_MODE_READY_SHIFT (28U) -#define PCFG_DCDCM_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MODE_READY_MASK) >> PCFG_DCDCM_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDCM work mode - * XX0: turn off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDCM_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDCM_MODE_MODE_SHIFT (16U) -#define PCFG_DCDCM_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MODE_MODE_SHIFT) & PCFG_DCDCM_MODE_MODE_MASK) -#define PCFG_DCDCM_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MODE_MODE_MASK) >> PCFG_DCDCM_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDCM voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDCM_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDCM_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDCM_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MODE_VOLT_SHIFT) & PCFG_DCDCM_MODE_VOLT_MASK) -#define PCFG_DCDCM_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MODE_VOLT_MASK) >> PCFG_DCDCM_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDCM_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDCM voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDCM_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDCM_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDCM_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDCM_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDCM_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDCM_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDCM_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDCM_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDCM_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDCM_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDCM_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDCM_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_ILIMIT_LP_MASK) >> PCFG_DCDCM_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDCM_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDCM_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDCM_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDCM_PROT_OVERLOAD_LP_SHIFT) - -/* - * DISABLE_POWER_LOSS (RW) - * - * disable power loss protection - * 0: power loss protection enabled, DCDCM shuts down when power loss - * 1: power loss protection disabled, DCDCM try working after power voltage drop - */ -#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK (0x800000UL) -#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SHIFT (23U) -#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SHIFT) & PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK) -#define PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK) >> PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDCM_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDCM_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDCM_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDCM_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * output over voltage protection - * 0: protection enabled, DCDCM will shut down is output voltage is unexpected high - * 1: protection disabled, DCDCM continue to adjust output voltage - */ -#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDCM_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDCM_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDCM_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDCM_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDCM shut down if short circuit on output detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDCM_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDCM_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDCM_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDCM_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDCM_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDCM_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A - * 1: 1.3A - */ -#define PCFG_DCDCM_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDCM_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDCM_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDCM_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDCM_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDCM_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDCM_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDCM_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDCM_PROT_SHORT_FLAG_MASK) >> PCFG_DCDCM_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDCM_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDCM_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDCM_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDCM_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDCM_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDCM_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDCM_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDCM_CURRENT_ESTI_EN_MASK) >> PCFG_DCDCM_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDCM_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDCM_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDCM_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDCM_CURRENT_VALID_MASK) >> PCFG_DCDCM_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDCM current level, current level is num * 50mA - */ -#define PCFG_DCDCM_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDCM_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDCM_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDCM_CURRENT_LEVEL_MASK) >> PCFG_DCDCM_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDCM_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDCM_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDCM_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDCM_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDCM_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDCM_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDCM_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_DC_C_SHIFT) & PCFG_DCDCM_ADVMODE_DC_C_MASK) -#define PCFG_DCDCM_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_DC_C_MASK) >> PCFG_DCDCM_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDCM_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDCM_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDCM_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_DC_R_SHIFT) & PCFG_DCDCM_ADVMODE_DC_R_MASK) -#define PCFG_DCDCM_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_DC_R_MASK) >> PCFG_DCDCM_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDCM_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDCM_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDCM_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDCM_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDCM_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDCM_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDCM_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDCM_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDCM_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_AUTOLP (RW) - * - * enable auto enter low power mode - * 0: do not enter low power mode - * 1: enter low power mode if current is detected low - */ -#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_MASK (0x10U) -#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_SHIFT (4U) -#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDCM_ADVMODE_EN_AUTOLP_MASK) -#define PCFG_DCDCM_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDCM_ADVMODE_EN_AUTOLP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDCM_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDCM_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDCM_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDCM_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDCM_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDCM_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDCM_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDCM_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDCM_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDCM_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDCM_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDCM_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDCM_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDCM_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDCM_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDCM_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDCM_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDCM_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVMODE_EN_DCM_MASK) >> PCFG_DCDCM_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDCM_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDCM_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDCM_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDCM_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDCM_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDCM_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDCM_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDCM_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDCM_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDCM_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDCM_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDCM_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDCM_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDCM_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDCM_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDCM_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDCM_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDCM_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDCM_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_EN_HYST_SHIFT) & PCFG_DCDCM_MISC_EN_HYST_MASK) -#define PCFG_DCDCM_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_EN_HYST_MASK) >> PCFG_DCDCM_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDCM_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDCM_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDCM_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_HYST_SIGN_SHIFT) & PCFG_DCDCM_MISC_HYST_SIGN_MASK) -#define PCFG_DCDCM_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_HYST_SIGN_MASK) >> PCFG_DCDCM_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDCM_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDCM_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDCM_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_HYST_THRS_SHIFT) & PCFG_DCDCM_MISC_HYST_THRS_MASK) -#define PCFG_DCDCM_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_HYST_THRS_MASK) >> PCFG_DCDCM_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDCM_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDCM_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDCM_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_RC_SCALE_SHIFT) & PCFG_DCDCM_MISC_RC_SCALE_MASK) -#define PCFG_DCDCM_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_RC_SCALE_MASK) >> PCFG_DCDCM_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDCM_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDCM_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDCM_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_DC_FF_SHIFT) & PCFG_DCDCM_MISC_DC_FF_MASK) -#define PCFG_DCDCM_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_DC_FF_MASK) >> PCFG_DCDCM_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDCM_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDCM_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDCM_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_OL_THRE_SHIFT) & PCFG_DCDCM_MISC_OL_THRE_MASK) -#define PCFG_DCDCM_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_OL_THRE_MASK) >> PCFG_DCDCM_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDCM_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDCM_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDCM_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_OL_HYST_SHIFT) & PCFG_DCDCM_MISC_OL_HYST_MASK) -#define PCFG_DCDCM_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_OL_HYST_MASK) >> PCFG_DCDCM_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDCM_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDCM_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDCM_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_DELAY_SHIFT) & PCFG_DCDCM_MISC_DELAY_MASK) -#define PCFG_DCDCM_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_DELAY_MASK) >> PCFG_DCDCM_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDCM internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDCM_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDCM_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDCM_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_CLK_SEL_SHIFT) & PCFG_DCDCM_MISC_CLK_SEL_MASK) -#define PCFG_DCDCM_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_CLK_SEL_MASK) >> PCFG_DCDCM_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled, - * 1: steping enabled - */ -#define PCFG_DCDCM_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDCM_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDCM_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDCM_MISC_EN_STEP_SHIFT) & PCFG_DCDCM_MISC_EN_STEP_MASK) -#define PCFG_DCDCM_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDCM_MISC_EN_STEP_MASK) >> PCFG_DCDCM_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDCM_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDCM voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDCM_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDCM_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDCM_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDCM_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDCM_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDCM_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDCM_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDCM_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDCM_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDCM to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDCM_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDCM_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDCM_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDCM_START_TIME_START_TIME_SHIFT) & PCFG_DCDCM_START_TIME_START_TIME_MASK) -#define PCFG_DCDCM_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDCM_START_TIME_START_TIME_MASK) >> PCFG_DCDCM_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDCM_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDCM to recover from low power mode, in 24M clock cycles, default value is 10uS - */ -#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDCM_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDCM_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDCM_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: DCDCM_POWER_CONFIG */ -/* - * RETENTION (RW) - * - * DCDCM enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDCM - * 1: reduce DCDC voltage - */ -#define PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK (0x10000UL) -#define PCFG_DCDCM_POWER_CONFIG_RETENTION_SHIFT (16U) -#define PCFG_DCDCM_POWER_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << PCFG_DCDCM_POWER_CONFIG_RETENTION_SHIFT) & PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK) -#define PCFG_DCDCM_POWER_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK) >> PCFG_DCDCM_POWER_CONFIG_RETENTION_SHIFT) - - - - -#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pdm_regs.h deleted file mode 100644 index 94b550e0ee2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pdm_regs.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDM_H -#define HPM_PDM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t CH_CTRL; /* 0x4: Channel Control Register */ - __W uint32_t ST; /* 0x8: Status Register */ - __RW uint32_t CH_CFG; /* 0xC: Channel Configuration Register */ - __RW uint32_t CIC_CFG; /* 0x10: CIC configuration register */ - __RW uint32_t CTRL_INBUF; /* 0x14: In Buf Control Register */ - __RW uint32_t CTRL_FILT0; /* 0x18: Filter 0 Control Register */ - __RW uint32_t CTRL_FILT1; /* 0x1C: Filter 1 Control Register */ - __RW uint32_t RUN; /* 0x20: Run Register */ - __RW uint32_t MEMADDR; /* 0x24: Memory Access Address */ - __RW uint32_t MEMDATA; /* 0x28: Memory Access Data */ - __RW uint32_t HPF_MA; /* 0x2C: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x30: HPF B Coef Register */ -} PDM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module. Self-clear. - */ -#define PDM_CTRL_SFTRST_MASK (0x80000000UL) -#define PDM_CTRL_SFTRST_SHIFT (31U) -#define PDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PDM_CTRL_SFTRST_SHIFT) & PDM_CTRL_SFTRST_MASK) -#define PDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PDM_CTRL_SFTRST_MASK) >> PDM_CTRL_SFTRST_SHIFT) - -/* - * SOF_FEDGE (RW) - * - * asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - */ -#define PDM_CTRL_SOF_FEDGE_MASK (0x800000UL) -#define PDM_CTRL_SOF_FEDGE_SHIFT (23U) -#define PDM_CTRL_SOF_FEDGE_SET(x) (((uint32_t)(x) << PDM_CTRL_SOF_FEDGE_SHIFT) & PDM_CTRL_SOF_FEDGE_MASK) -#define PDM_CTRL_SOF_FEDGE_GET(x) (((uint32_t)(x) & PDM_CTRL_SOF_FEDGE_MASK) >> PDM_CTRL_SOF_FEDGE_SHIFT) - -/* - * USE_COEF_RAM (RW) - * - * Asserted to use Coef RAM instead of Coef ROM - */ -#define PDM_CTRL_USE_COEF_RAM_MASK (0x100000UL) -#define PDM_CTRL_USE_COEF_RAM_SHIFT (20U) -#define PDM_CTRL_USE_COEF_RAM_SET(x) (((uint32_t)(x) << PDM_CTRL_USE_COEF_RAM_SHIFT) & PDM_CTRL_USE_COEF_RAM_MASK) -#define PDM_CTRL_USE_COEF_RAM_GET(x) (((uint32_t)(x) & PDM_CTRL_USE_COEF_RAM_MASK) >> PDM_CTRL_USE_COEF_RAM_SHIFT) - -/* - * FILT_CRX_ERR_IE (RW) - * - * data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - */ -#define PDM_CTRL_FILT_CRX_ERR_IE_MASK (0x80000UL) -#define PDM_CTRL_FILT_CRX_ERR_IE_SHIFT (19U) -#define PDM_CTRL_FILT_CRX_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) -#define PDM_CTRL_FILT_CRX_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) >> PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) - -/* - * OFIFO_OVFL_ERR_IE (RW) - * - * output fifo overflow error interrupt enable - */ -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x40000UL) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (18U) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) - -/* - * CIC_OVLD_ERR_IE (RW) - * - * CIC overload error interrupt enable - */ -#define PDM_CTRL_CIC_OVLD_ERR_IE_MASK (0x20000UL) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT (17U) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) -#define PDM_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) >> PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) - -/* - * CIC_SAT_ERR_IE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define PDM_CTRL_CIC_SAT_ERR_IE_MASK (0x10000UL) -#define PDM_CTRL_CIC_SAT_ERR_IE_SHIFT (16U) -#define PDM_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) -#define PDM_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) >> PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) - -/* - * DEC_AFT_CIC (RW) - * - * decimation rate after CIC. Now it is forced to be 3. - */ -#define PDM_CTRL_DEC_AFT_CIC_MASK (0xF000U) -#define PDM_CTRL_DEC_AFT_CIC_SHIFT (12U) -#define PDM_CTRL_DEC_AFT_CIC_SET(x) (((uint32_t)(x) << PDM_CTRL_DEC_AFT_CIC_SHIFT) & PDM_CTRL_DEC_AFT_CIC_MASK) -#define PDM_CTRL_DEC_AFT_CIC_GET(x) (((uint32_t)(x) & PDM_CTRL_DEC_AFT_CIC_MASK) >> PDM_CTRL_DEC_AFT_CIC_SHIFT) - -/* - * CAPT_DLY (RW) - * - * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - */ -#define PDM_CTRL_CAPT_DLY_MASK (0x780U) -#define PDM_CTRL_CAPT_DLY_SHIFT (7U) -#define PDM_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << PDM_CTRL_CAPT_DLY_SHIFT) & PDM_CTRL_CAPT_DLY_MASK) -#define PDM_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & PDM_CTRL_CAPT_DLY_MASK) >> PDM_CTRL_CAPT_DLY_SHIFT) - -/* - * PDM_CLK_HFDIV (RW) - * - * The clock divider will work at least 4. - * 0: div-by-2, - * 1: div-by-4 - * . . . - * n: div-by-2*(n+1) - */ -#define PDM_CTRL_PDM_CLK_HFDIV_MASK (0x78U) -#define PDM_CTRL_PDM_CLK_HFDIV_SHIFT (3U) -#define PDM_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_HFDIV_SHIFT) & PDM_CTRL_PDM_CLK_HFDIV_MASK) -#define PDM_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_HFDIV_MASK) >> PDM_CTRL_PDM_CLK_HFDIV_SHIFT) - -/* - * PDM_CLK_DIV_BYPASS (RW) - * - * asserted to bypass the pdm clock divider - */ -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x4U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (2U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) - -/* - * PDM_CLK_OE (RW) - * - * pdm_clk_output_en - */ -#define PDM_CTRL_PDM_CLK_OE_MASK (0x2U) -#define PDM_CTRL_PDM_CLK_OE_SHIFT (1U) -#define PDM_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_OE_SHIFT) & PDM_CTRL_PDM_CLK_OE_MASK) -#define PDM_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_OE_MASK) >> PDM_CTRL_PDM_CLK_OE_SHIFT) - -/* - * HPF_EN (RW) - * - * pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - */ -#define PDM_CTRL_HPF_EN_MASK (0x1U) -#define PDM_CTRL_HPF_EN_SHIFT (0U) -#define PDM_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << PDM_CTRL_HPF_EN_SHIFT) & PDM_CTRL_HPF_EN_MASK) -#define PDM_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & PDM_CTRL_HPF_EN_MASK) >> PDM_CTRL_HPF_EN_SHIFT) - -/* Bitfield definition for register: CH_CTRL */ -/* - * CH_POL (RW) - * - * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - */ -#define PDM_CH_CTRL_CH_POL_MASK (0xFF0000UL) -#define PDM_CH_CTRL_CH_POL_SHIFT (16U) -#define PDM_CH_CTRL_CH_POL_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_POL_SHIFT) & PDM_CH_CTRL_CH_POL_MASK) -#define PDM_CH_CTRL_CH_POL_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_POL_MASK) >> PDM_CH_CTRL_CH_POL_SHIFT) - -/* - * CH_EN (RW) - * - * Asserted to enable the channel. - * Ch8 & 9 are refs. - * Ch0-7 are pdm mics. - */ -#define PDM_CH_CTRL_CH_EN_MASK (0x3FFU) -#define PDM_CH_CTRL_CH_EN_SHIFT (0U) -#define PDM_CH_CTRL_CH_EN_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_EN_SHIFT) & PDM_CH_CTRL_CH_EN_MASK) -#define PDM_CH_CTRL_CH_EN_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_EN_MASK) >> PDM_CH_CTRL_CH_EN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * FILT_CRX_ERR (W1C) - * - * data accessed out of boundary error - */ -#define PDM_ST_FILT_CRX_ERR_MASK (0x8U) -#define PDM_ST_FILT_CRX_ERR_SHIFT (3U) -#define PDM_ST_FILT_CRX_ERR_SET(x) (((uint32_t)(x) << PDM_ST_FILT_CRX_ERR_SHIFT) & PDM_ST_FILT_CRX_ERR_MASK) -#define PDM_ST_FILT_CRX_ERR_GET(x) (((uint32_t)(x) & PDM_ST_FILT_CRX_ERR_MASK) >> PDM_ST_FILT_CRX_ERR_SHIFT) - -/* - * OFIFO_OVFL_ERR (W1C) - * - * output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - */ -#define PDM_ST_OFIFO_OVFL_ERR_MASK (0x4U) -#define PDM_ST_OFIFO_OVFL_ERR_SHIFT (2U) -#define PDM_ST_OFIFO_OVFL_ERR_SET(x) (((uint32_t)(x) << PDM_ST_OFIFO_OVFL_ERR_SHIFT) & PDM_ST_OFIFO_OVFL_ERR_MASK) -#define PDM_ST_OFIFO_OVFL_ERR_GET(x) (((uint32_t)(x) & PDM_ST_OFIFO_OVFL_ERR_MASK) >> PDM_ST_OFIFO_OVFL_ERR_SHIFT) - -/* - * CIC_OVLD_ERR (W1C) - * - * CIC overload error. write 1 clear - */ -#define PDM_ST_CIC_OVLD_ERR_MASK (0x2U) -#define PDM_ST_CIC_OVLD_ERR_SHIFT (1U) -#define PDM_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_OVLD_ERR_SHIFT) & PDM_ST_CIC_OVLD_ERR_MASK) -#define PDM_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_OVLD_ERR_MASK) >> PDM_ST_CIC_OVLD_ERR_SHIFT) - -/* - * CIC_SAT_ERR (W1C) - * - * CIC saturation. Write 1 clear - */ -#define PDM_ST_CIC_SAT_ERR_MASK (0x1U) -#define PDM_ST_CIC_SAT_ERR_SHIFT (0U) -#define PDM_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_SAT_ERR_SHIFT) & PDM_ST_CIC_SAT_ERR_MASK) -#define PDM_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_SAT_ERR_MASK) >> PDM_ST_CIC_SAT_ERR_SHIFT) - -/* Bitfield definition for register: CH_CFG */ -/* - * CH9_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH9_TYPE_MASK (0xC0000UL) -#define PDM_CH_CFG_CH9_TYPE_SHIFT (18U) -#define PDM_CH_CFG_CH9_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH9_TYPE_SHIFT) & PDM_CH_CFG_CH9_TYPE_MASK) -#define PDM_CH_CFG_CH9_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH9_TYPE_MASK) >> PDM_CH_CFG_CH9_TYPE_SHIFT) - -/* - * CH8_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH8_TYPE_MASK (0x30000UL) -#define PDM_CH_CFG_CH8_TYPE_SHIFT (16U) -#define PDM_CH_CFG_CH8_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH8_TYPE_SHIFT) & PDM_CH_CFG_CH8_TYPE_MASK) -#define PDM_CH_CFG_CH8_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH8_TYPE_MASK) >> PDM_CH_CFG_CH8_TYPE_SHIFT) - -/* - * CH7_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH7_TYPE_MASK (0xC000U) -#define PDM_CH_CFG_CH7_TYPE_SHIFT (14U) -#define PDM_CH_CFG_CH7_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH7_TYPE_SHIFT) & PDM_CH_CFG_CH7_TYPE_MASK) -#define PDM_CH_CFG_CH7_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH7_TYPE_MASK) >> PDM_CH_CFG_CH7_TYPE_SHIFT) - -/* - * CH6_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH6_TYPE_MASK (0x3000U) -#define PDM_CH_CFG_CH6_TYPE_SHIFT (12U) -#define PDM_CH_CFG_CH6_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH6_TYPE_SHIFT) & PDM_CH_CFG_CH6_TYPE_MASK) -#define PDM_CH_CFG_CH6_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH6_TYPE_MASK) >> PDM_CH_CFG_CH6_TYPE_SHIFT) - -/* - * CH5_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH5_TYPE_MASK (0xC00U) -#define PDM_CH_CFG_CH5_TYPE_SHIFT (10U) -#define PDM_CH_CFG_CH5_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH5_TYPE_SHIFT) & PDM_CH_CFG_CH5_TYPE_MASK) -#define PDM_CH_CFG_CH5_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH5_TYPE_MASK) >> PDM_CH_CFG_CH5_TYPE_SHIFT) - -/* - * CH4_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH4_TYPE_MASK (0x300U) -#define PDM_CH_CFG_CH4_TYPE_SHIFT (8U) -#define PDM_CH_CFG_CH4_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH4_TYPE_SHIFT) & PDM_CH_CFG_CH4_TYPE_MASK) -#define PDM_CH_CFG_CH4_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH4_TYPE_MASK) >> PDM_CH_CFG_CH4_TYPE_SHIFT) - -/* - * CH3_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH3_TYPE_MASK (0xC0U) -#define PDM_CH_CFG_CH3_TYPE_SHIFT (6U) -#define PDM_CH_CFG_CH3_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH3_TYPE_SHIFT) & PDM_CH_CFG_CH3_TYPE_MASK) -#define PDM_CH_CFG_CH3_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH3_TYPE_MASK) >> PDM_CH_CFG_CH3_TYPE_SHIFT) - -/* - * CH2_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH2_TYPE_MASK (0x30U) -#define PDM_CH_CFG_CH2_TYPE_SHIFT (4U) -#define PDM_CH_CFG_CH2_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH2_TYPE_SHIFT) & PDM_CH_CFG_CH2_TYPE_MASK) -#define PDM_CH_CFG_CH2_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH2_TYPE_MASK) >> PDM_CH_CFG_CH2_TYPE_SHIFT) - -/* - * CH1_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH1_TYPE_MASK (0xCU) -#define PDM_CH_CFG_CH1_TYPE_SHIFT (2U) -#define PDM_CH_CFG_CH1_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH1_TYPE_SHIFT) & PDM_CH_CFG_CH1_TYPE_MASK) -#define PDM_CH_CFG_CH1_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH1_TYPE_MASK) >> PDM_CH_CFG_CH1_TYPE_SHIFT) - -/* - * CH0_TYPE (RW) - * - * Type of Channel 0 - * 2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) - * 2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - */ -#define PDM_CH_CFG_CH0_TYPE_MASK (0x3U) -#define PDM_CH_CFG_CH0_TYPE_SHIFT (0U) -#define PDM_CH_CFG_CH0_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH0_TYPE_SHIFT) & PDM_CH_CFG_CH0_TYPE_MASK) -#define PDM_CH_CFG_CH0_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH0_TYPE_MASK) >> PDM_CH_CFG_CH0_TYPE_SHIFT) - -/* Bitfield definition for register: CIC_CFG */ -/* - * POST_SCALE (RW) - * - * the shift value after CIC results. - */ -#define PDM_CIC_CFG_POST_SCALE_MASK (0xFC00U) -#define PDM_CIC_CFG_POST_SCALE_SHIFT (10U) -#define PDM_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_POST_SCALE_SHIFT) & PDM_CIC_CFG_POST_SCALE_MASK) -#define PDM_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_POST_SCALE_MASK) >> PDM_CIC_CFG_POST_SCALE_SHIFT) - -/* - * SGD (RW) - * - * Sigma_delta_order[1:0] - * 2'b00: 7 - * 2'b01: 6 - * 2'b10: 5 - * Others: unused - */ -#define PDM_CIC_CFG_SGD_MASK (0x300U) -#define PDM_CIC_CFG_SGD_SHIFT (8U) -#define PDM_CIC_CFG_SGD_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_SGD_SHIFT) & PDM_CIC_CFG_SGD_MASK) -#define PDM_CIC_CFG_SGD_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_SGD_MASK) >> PDM_CIC_CFG_SGD_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation factor - */ -#define PDM_CIC_CFG_CIC_DEC_RATIO_MASK (0xFFU) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT (0U) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) -#define PDM_CIC_CFG_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) >> PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) - -/* Bitfield definition for register: CTRL_INBUF */ -/* - * MAX_PTR (RW) - * - * The buf size-1 for each channel - */ -#define PDM_CTRL_INBUF_MAX_PTR_MASK (0x3FC00000UL) -#define PDM_CTRL_INBUF_MAX_PTR_SHIFT (22U) -#define PDM_CTRL_INBUF_MAX_PTR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_MAX_PTR_SHIFT) & PDM_CTRL_INBUF_MAX_PTR_MASK) -#define PDM_CTRL_INBUF_MAX_PTR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_MAX_PTR_MASK) >> PDM_CTRL_INBUF_MAX_PTR_SHIFT) - -/* - * PITCH (RW) - * - * The spacing between starting address of adjacent channels - */ -#define PDM_CTRL_INBUF_PITCH_MASK (0x3FF800UL) -#define PDM_CTRL_INBUF_PITCH_SHIFT (11U) -#define PDM_CTRL_INBUF_PITCH_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_PITCH_SHIFT) & PDM_CTRL_INBUF_PITCH_MASK) -#define PDM_CTRL_INBUF_PITCH_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_PITCH_MASK) >> PDM_CTRL_INBUF_PITCH_SHIFT) - -/* - * START_ADDR (RW) - * - * The starting address of channel 0 in filter data buffer - */ -#define PDM_CTRL_INBUF_START_ADDR_MASK (0x7FFU) -#define PDM_CTRL_INBUF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_INBUF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_START_ADDR_SHIFT) & PDM_CTRL_INBUF_START_ADDR_MASK) -#define PDM_CTRL_INBUF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_START_ADDR_MASK) >> PDM_CTRL_INBUF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT0 */ -/* - * COEF_LEN_M0 (RW) - * - * Coef length of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_LEN_M0_MASK (0xFF00U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT (8U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) -#define PDM_CTRL_FILT0_COEF_LEN_M0_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) >> PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT0_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT1 */ -/* - * COEF_LEN_M1 (RW) - * - * Coef length of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_LEN_M1_MASK (0xFF00U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT (8U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) -#define PDM_CTRL_FILT1_COEF_LEN_M1_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) >> PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT1_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: RUN */ -/* - * PDM_EN (RW) - * - * Asserted to enable the module - */ -#define PDM_RUN_PDM_EN_MASK (0x1U) -#define PDM_RUN_PDM_EN_SHIFT (0U) -#define PDM_RUN_PDM_EN_SET(x) (((uint32_t)(x) << PDM_RUN_PDM_EN_SHIFT) & PDM_RUN_PDM_EN_MASK) -#define PDM_RUN_PDM_EN_GET(x) (((uint32_t)(x) & PDM_RUN_PDM_EN_MASK) >> PDM_RUN_PDM_EN_SHIFT) - -/* Bitfield definition for register: MEMADDR */ -/* - * ADDR (RW) - * - * 0--0x0FFFFFFF: COEF_RAM - * 0x10000000--0x1FFFFFFF: DATA_RAM - */ -#define PDM_MEMADDR_ADDR_MASK (0xFFFFFFFFUL) -#define PDM_MEMADDR_ADDR_SHIFT (0U) -#define PDM_MEMADDR_ADDR_SET(x) (((uint32_t)(x) << PDM_MEMADDR_ADDR_SHIFT) & PDM_MEMADDR_ADDR_MASK) -#define PDM_MEMADDR_ADDR_GET(x) (((uint32_t)(x) & PDM_MEMADDR_ADDR_MASK) >> PDM_MEMADDR_ADDR_SHIFT) - -/* Bitfield definition for register: MEMDATA */ -/* - * DATA (RW) - * - * The data write-to/read-from buffer - */ -#define PDM_MEMDATA_DATA_MASK (0xFFFFFFFFUL) -#define PDM_MEMDATA_DATA_SHIFT (0U) -#define PDM_MEMDATA_DATA_SET(x) (((uint32_t)(x) << PDM_MEMDATA_DATA_SHIFT) & PDM_MEMDATA_DATA_MASK) -#define PDM_MEMDATA_DATA_GET(x) (((uint32_t)(x) & PDM_MEMDATA_DATA_MASK) >> PDM_MEMDATA_DATA_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define PDM_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_MA_COEF_SHIFT (0U) -#define PDM_HPF_MA_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_MA_COEF_SHIFT) & PDM_HPF_MA_COEF_MASK) -#define PDM_HPF_MA_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_MA_COEF_MASK) >> PDM_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define PDM_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_B_COEF_SHIFT (0U) -#define PDM_HPF_B_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_B_COEF_SHIFT) & PDM_HPF_B_COEF_MASK) -#define PDM_HPF_B_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_B_COEF_MASK) >> PDM_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_PDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pdma_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pdma_regs.h deleted file mode 100644 index 1970ce84348..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pdma_regs.h +++ /dev/null @@ -1,933 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDMA_H -#define HPM_PDMA_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t STAT; /* 0x4: Status Register */ - __RW uint32_t OUT_CTRL; /* 0x8: Out Layer Control Register */ - __RW uint32_t OUT_BUF; /* 0xC: Output buffer address */ - __R uint8_t RESERVED0[4]; /* 0x10 - 0x13: Reserved */ - __RW uint32_t OUT_PITCH; /* 0x14: Outlayer Pitch Register */ - __RW uint32_t OUT_LRC; /* 0x18: Output Lower Right Corner Register */ - struct { - __RW uint32_t ULC; /* 0x1C: Layer Upper Left Corner Register */ - __RW uint32_t LRC; /* 0x20: Layer Lower Right Corner Register */ - } OUT_PS[2]; - __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x30: Layer Control Register */ - __RW uint32_t BUF; /* 0x34: Layer data buffer address */ - __R uint8_t RESERVED0[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t PITCH; /* 0x40: Layer data pitch register */ - __RW uint32_t BKGD; /* 0x44: Layer background color register */ - __RW uint32_t SCALE; /* 0x48: Layer scale register */ - __RW uint32_t OFFSET; /* 0x4C: Layer offset register */ - __RW uint32_t CLRKEY_LOW; /* 0x50: Layer low color key register */ - __RW uint32_t CLRKEY_HIGH; /* 0x54: Layer high color key register */ - __RW uint32_t ORG; /* 0x58: Layer original size register */ - __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */ - } PS[2]; - __R uint8_t RESERVED2[16]; /* 0x90 - 0x9F: Reserved */ - __RW uint32_t YUV2RGB_COEF0; /* 0xA0: YUV2RGB coefficients register 0 */ - __RW uint32_t YUV2RGB_COEF1; /* 0xA4: YUV2RGB coefficients register 1 */ - __RW uint32_t YUV2RGB_COEF2; /* 0xA8: YUV2RGB coefficients register 2 */ - __RW uint32_t RGB2YUV_COEF0; /* 0xAC: RGB2YUV coefficients register 0 */ - __RW uint32_t RGB2YUV_COEF1; /* 0xB0: RGB2YUV coefficients register 1 */ - __RW uint32_t RGB2YUV_COEF2; /* 0xB4: RGB2YUV coefficients register 2 */ - __RW uint32_t RGB2YUV_COEF3; /* 0xB8: RGB2YUV coefficients register 3 */ - __RW uint32_t RGB2YUV_COEF4; /* 0xBC: RGB2YUV coefficients register 4 */ -} PDMA_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * ARQOS (RW) - * - * QoS for AXI read bus - */ -#define PDMA_CTRL_ARQOS_MASK (0x780000UL) -#define PDMA_CTRL_ARQOS_SHIFT (19U) -#define PDMA_CTRL_ARQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_ARQOS_SHIFT) & PDMA_CTRL_ARQOS_MASK) -#define PDMA_CTRL_ARQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_ARQOS_MASK) >> PDMA_CTRL_ARQOS_SHIFT) - -/* - * AWQOS (RW) - * - * QoS for AXI write bus - */ -#define PDMA_CTRL_AWQOS_MASK (0x78000UL) -#define PDMA_CTRL_AWQOS_SHIFT (15U) -#define PDMA_CTRL_AWQOS_SET(x) (((uint32_t)(x) << PDMA_CTRL_AWQOS_SHIFT) & PDMA_CTRL_AWQOS_MASK) -#define PDMA_CTRL_AWQOS_GET(x) (((uint32_t)(x) & PDMA_CTRL_AWQOS_MASK) >> PDMA_CTRL_AWQOS_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit output word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. - * 2'b00: no change {A3, A2, A1, A0} - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define PDMA_CTRL_PACK_DIR_MASK (0x6000U) -#define PDMA_CTRL_PACK_DIR_SHIFT (13U) -#define PDMA_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_CTRL_PACK_DIR_SHIFT) & PDMA_CTRL_PACK_DIR_MASK) -#define PDMA_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_CTRL_PACK_DIR_MASK) >> PDMA_CTRL_PACK_DIR_SHIFT) - -/* - * AXIERR_IRQ_EN (RW) - * - * Enable interrupt of AXI bus error - */ -#define PDMA_CTRL_AXIERR_IRQ_EN_MASK (0x1000U) -#define PDMA_CTRL_AXIERR_IRQ_EN_SHIFT (12U) -#define PDMA_CTRL_AXIERR_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) -#define PDMA_CTRL_AXIERR_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_AXIERR_IRQ_EN_MASK) >> PDMA_CTRL_AXIERR_IRQ_EN_SHIFT) - -/* - * PDMA_DONE_IRQ_EN (RW) - * - * Enable interrupt of PDMA_DONE - */ -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK (0x800U) -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT (11U) -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) -#define PDMA_CTRL_PDMA_DONE_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_DONE_IRQ_EN_MASK) >> PDMA_CTRL_PDMA_DONE_IRQ_EN_SHIFT) - -/* - * CLKGATE (RW) - * - * Assert this bit to gate off clock when the module is not working. If reset to zero, the internal clock is always on. - */ -#define PDMA_CTRL_CLKGATE_MASK (0x200U) -#define PDMA_CTRL_CLKGATE_SHIFT (9U) -#define PDMA_CTRL_CLKGATE_SET(x) (((uint32_t)(x) << PDMA_CTRL_CLKGATE_SHIFT) & PDMA_CTRL_CLKGATE_MASK) -#define PDMA_CTRL_CLKGATE_GET(x) (((uint32_t)(x) & PDMA_CTRL_CLKGATE_MASK) >> PDMA_CTRL_CLKGATE_SHIFT) - -/* - * IRQ_EN (RW) - * - * Enable normal interrupt - */ -#define PDMA_CTRL_IRQ_EN_MASK (0x40U) -#define PDMA_CTRL_IRQ_EN_SHIFT (6U) -#define PDMA_CTRL_IRQ_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_IRQ_EN_SHIFT) & PDMA_CTRL_IRQ_EN_MASK) -#define PDMA_CTRL_IRQ_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_IRQ_EN_MASK) >> PDMA_CTRL_IRQ_EN_SHIFT) - -/* - * BS16 (RW) - * - * Asserted when the Block Size is 16x16, else 8x8 - */ -#define PDMA_CTRL_BS16_MASK (0x20U) -#define PDMA_CTRL_BS16_SHIFT (5U) -#define PDMA_CTRL_BS16_SET(x) (((uint32_t)(x) << PDMA_CTRL_BS16_SHIFT) & PDMA_CTRL_BS16_MASK) -#define PDMA_CTRL_BS16_GET(x) (((uint32_t)(x) & PDMA_CTRL_BS16_MASK) >> PDMA_CTRL_BS16_SHIFT) - -/* - * P1_EN (RW) - * - * Plane 1 Enable - */ -#define PDMA_CTRL_P1_EN_MASK (0x10U) -#define PDMA_CTRL_P1_EN_SHIFT (4U) -#define PDMA_CTRL_P1_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P1_EN_SHIFT) & PDMA_CTRL_P1_EN_MASK) -#define PDMA_CTRL_P1_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P1_EN_MASK) >> PDMA_CTRL_P1_EN_SHIFT) - -/* - * P0_EN (RW) - * - * Plane 0 Enable - */ -#define PDMA_CTRL_P0_EN_MASK (0x8U) -#define PDMA_CTRL_P0_EN_SHIFT (3U) -#define PDMA_CTRL_P0_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_P0_EN_SHIFT) & PDMA_CTRL_P0_EN_MASK) -#define PDMA_CTRL_P0_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_P0_EN_MASK) >> PDMA_CTRL_P0_EN_SHIFT) - -/* - * PDMA_SFTRST (RW) - * - * Software Reset. - * Write 1 to clear PDMA internal logic. - * Write 0 to exit software reset mode. - */ -#define PDMA_CTRL_PDMA_SFTRST_MASK (0x2U) -#define PDMA_CTRL_PDMA_SFTRST_SHIFT (1U) -#define PDMA_CTRL_PDMA_SFTRST_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_SFTRST_SHIFT) & PDMA_CTRL_PDMA_SFTRST_MASK) -#define PDMA_CTRL_PDMA_SFTRST_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_SFTRST_MASK) >> PDMA_CTRL_PDMA_SFTRST_SHIFT) - -/* - * PDMA_EN (RW) - * - * 1b - Enabled - */ -#define PDMA_CTRL_PDMA_EN_MASK (0x1U) -#define PDMA_CTRL_PDMA_EN_SHIFT (0U) -#define PDMA_CTRL_PDMA_EN_SET(x) (((uint32_t)(x) << PDMA_CTRL_PDMA_EN_SHIFT) & PDMA_CTRL_PDMA_EN_MASK) -#define PDMA_CTRL_PDMA_EN_GET(x) (((uint32_t)(x) & PDMA_CTRL_PDMA_EN_MASK) >> PDMA_CTRL_PDMA_EN_SHIFT) - -/* Bitfield definition for register: STAT */ -/* - * BLOCKY (RO) - * - * Y block that is processing - */ -#define PDMA_STAT_BLOCKY_MASK (0xFF000000UL) -#define PDMA_STAT_BLOCKY_SHIFT (24U) -#define PDMA_STAT_BLOCKY_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKY_MASK) >> PDMA_STAT_BLOCKY_SHIFT) - -/* - * BLOCKX (RO) - * - * X block that is processing - */ -#define PDMA_STAT_BLOCKX_MASK (0xFF0000UL) -#define PDMA_STAT_BLOCKX_SHIFT (16U) -#define PDMA_STAT_BLOCKX_GET(x) (((uint32_t)(x) & PDMA_STAT_BLOCKX_MASK) >> PDMA_STAT_BLOCKX_SHIFT) - -/* - * PDMA_DONE (W1C) - * - * PDMA one image done - */ -#define PDMA_STAT_PDMA_DONE_MASK (0x200U) -#define PDMA_STAT_PDMA_DONE_SHIFT (9U) -#define PDMA_STAT_PDMA_DONE_SET(x) (((uint32_t)(x) << PDMA_STAT_PDMA_DONE_SHIFT) & PDMA_STAT_PDMA_DONE_MASK) -#define PDMA_STAT_PDMA_DONE_GET(x) (((uint32_t)(x) & PDMA_STAT_PDMA_DONE_MASK) >> PDMA_STAT_PDMA_DONE_SHIFT) - -/* - * AXI_ERR_ID (RO) - * - * AXI error ID - */ -#define PDMA_STAT_AXI_ERR_ID_MASK (0x1E0U) -#define PDMA_STAT_AXI_ERR_ID_SHIFT (5U) -#define PDMA_STAT_AXI_ERR_ID_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_ERR_ID_MASK) >> PDMA_STAT_AXI_ERR_ID_SHIFT) - -/* - * AXI_0_WRITE_ERR (W1C) - * - * AXI0 write err - */ -#define PDMA_STAT_AXI_0_WRITE_ERR_MASK (0x10U) -#define PDMA_STAT_AXI_0_WRITE_ERR_SHIFT (4U) -#define PDMA_STAT_AXI_0_WRITE_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) -#define PDMA_STAT_AXI_0_WRITE_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_WRITE_ERR_MASK) >> PDMA_STAT_AXI_0_WRITE_ERR_SHIFT) - -/* - * AXI_1_READ_ERR (W1C) - * - * AXI1 read err - */ -#define PDMA_STAT_AXI_1_READ_ERR_MASK (0x8U) -#define PDMA_STAT_AXI_1_READ_ERR_SHIFT (3U) -#define PDMA_STAT_AXI_1_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_1_READ_ERR_SHIFT) & PDMA_STAT_AXI_1_READ_ERR_MASK) -#define PDMA_STAT_AXI_1_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_1_READ_ERR_MASK) >> PDMA_STAT_AXI_1_READ_ERR_SHIFT) - -/* - * AXI_0_READ_ERR (W1C) - * - * AXI0 read err - */ -#define PDMA_STAT_AXI_0_READ_ERR_MASK (0x4U) -#define PDMA_STAT_AXI_0_READ_ERR_SHIFT (2U) -#define PDMA_STAT_AXI_0_READ_ERR_SET(x) (((uint32_t)(x) << PDMA_STAT_AXI_0_READ_ERR_SHIFT) & PDMA_STAT_AXI_0_READ_ERR_MASK) -#define PDMA_STAT_AXI_0_READ_ERR_GET(x) (((uint32_t)(x) & PDMA_STAT_AXI_0_READ_ERR_MASK) >> PDMA_STAT_AXI_0_READ_ERR_SHIFT) - -/* - * IRQ (RO) - * - * Asserted to indicate a IRQ event - */ -#define PDMA_STAT_IRQ_MASK (0x1U) -#define PDMA_STAT_IRQ_SHIFT (0U) -#define PDMA_STAT_IRQ_GET(x) (((uint32_t)(x) & PDMA_STAT_IRQ_MASK) >> PDMA_STAT_IRQ_SHIFT) - -/* Bitfield definition for register: OUT_CTRL */ -/* - * DSTALPHA (RW) - * - * The destination (P1) system ALPHA value. - */ -#define PDMA_OUT_CTRL_DSTALPHA_MASK (0xFF000000UL) -#define PDMA_OUT_CTRL_DSTALPHA_SHIFT (24U) -#define PDMA_OUT_CTRL_DSTALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_MASK) -#define PDMA_OUT_CTRL_DSTALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_MASK) >> PDMA_OUT_CTRL_DSTALPHA_SHIFT) - -/* - * SRCALPHA (RW) - * - * The source (P0) system ALPHA value. - */ -#define PDMA_OUT_CTRL_SRCALPHA_MASK (0xFF0000UL) -#define PDMA_OUT_CTRL_SRCALPHA_SHIFT (16U) -#define PDMA_OUT_CTRL_SRCALPHA_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_MASK) -#define PDMA_OUT_CTRL_SRCALPHA_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_MASK) >> PDMA_OUT_CTRL_SRCALPHA_SHIFT) - -/* - * DSTALPHA_OP (RW) - * - * The usage of the DSTALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the DSTALPHA[7:0] is invalid, use the alpha value embedded in the stream - * 1: the DSTALPHA[7:0] is used to override the alpha value embedded in the stream. (useful when the corresponding data stream has no alpha info) - * 2: the DSTALPHA[7:0] is used to scale the alpha value embedded in the stream - * 3: don't multiply the color data with any alpha values for blender inputs. - */ -#define PDMA_OUT_CTRL_DSTALPHA_OP_MASK (0xC000U) -#define PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT (14U) -#define PDMA_OUT_CTRL_DSTALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) -#define PDMA_OUT_CTRL_DSTALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_DSTALPHA_OP_MASK) >> PDMA_OUT_CTRL_DSTALPHA_OP_SHIFT) - -/* - * SRCALPHA_OP (RW) - * - * The usage of the SRCALPHA[7:0]: (The system alpha value is not the data valid mask, the non-zero alpha value per pixel embedded in the stream indicates a valid pixel. If no such per pixel alpha value, it means all the pixels are valid) - * 0: the SRCALPHA[7:0] is invalid, use the alpha value embedded in the stream - * 1: the SRCALPHA[7:0] is used to override the alpha value embedded in the stream . (useful when the corresponding data stream has no alpha info) - * 2: the SRCALPHA[7:0] is used to scale the alpha value embedded in the stream - * 3: don't multiply the color data with any alpha values for blender inputs. - */ -#define PDMA_OUT_CTRL_SRCALPHA_OP_MASK (0x3000U) -#define PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT (12U) -#define PDMA_OUT_CTRL_SRCALPHA_OP_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) -#define PDMA_OUT_CTRL_SRCALPHA_OP_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_SRCALPHA_OP_MASK) >> PDMA_OUT_CTRL_SRCALPHA_OP_SHIFT) - -/* - * ABLEND_MODE (RW) - * - * Alpha Blending Mode - * 0: SKBlendMode_Clear (If PS1_CTRL[BKGNDCL4CLR] is asserted, use PS1_BKGRND color to fill the range determined by PS1, else fill the range determined by PS1 with zero); - * 1: SKBlendMode_Src ; - * 2: SKBlendMode_Dst - * 3: SKBlendMode_SrcOver - * 4: SKBlendMode_DstOver - * 5: SKBlendMode_SrcIn - * 6: SKBlendMode_DstIn - * 7: SKBlendMode_SrcOut - * 8: SKBlendMode_DstOut - * 9: SKBlendMode_SrcATop - * 10: SKBlendMode_DstATop - * 11: SKBlendMode_Xor - * 12: SKBlendMode_Plus (The conventional belding mode) - * 13: SKBlendMode_Modulate - * 14: SRC org - * 15: DST org - * Others: Reserved. - */ -#define PDMA_OUT_CTRL_ABLEND_MODE_MASK (0xF00U) -#define PDMA_OUT_CTRL_ABLEND_MODE_SHIFT (8U) -#define PDMA_OUT_CTRL_ABLEND_MODE_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) -#define PDMA_OUT_CTRL_ABLEND_MODE_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_ABLEND_MODE_MASK) >> PDMA_OUT_CTRL_ABLEND_MODE_SHIFT) - -/* - * NORM_OUT (RW) - * - * Asserted to normalize the output color channels with alpha channels - */ -#define PDMA_OUT_CTRL_NORM_OUT_MASK (0x80U) -#define PDMA_OUT_CTRL_NORM_OUT_SHIFT (7U) -#define PDMA_OUT_CTRL_NORM_OUT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_NORM_OUT_SHIFT) & PDMA_OUT_CTRL_NORM_OUT_MASK) -#define PDMA_OUT_CTRL_NORM_OUT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_NORM_OUT_MASK) >> PDMA_OUT_CTRL_NORM_OUT_SHIFT) - -/* - * FORMAT (RW) - * - * Output buffer format. - * 0x0 ARGB8888 - 32-bit pixles, byte sequence as B,G,R,A - * 0xE RGB565 - 16-bit pixels, byte sequence as B,R - * 0x12 UYVY1P422 - 16-bit pixels (1-plane , byte sequence as U0,Y0,V0,Y1) - */ -#define PDMA_OUT_CTRL_FORMAT_MASK (0x3FU) -#define PDMA_OUT_CTRL_FORMAT_SHIFT (0U) -#define PDMA_OUT_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_OUT_CTRL_FORMAT_SHIFT) & PDMA_OUT_CTRL_FORMAT_MASK) -#define PDMA_OUT_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_OUT_CTRL_FORMAT_MASK) >> PDMA_OUT_CTRL_FORMAT_SHIFT) - -/* Bitfield definition for register: OUT_BUF */ -/* - * ADDR (RW) - * - * Current address pointer for the output frame buffer. The address can have any byte alignment. 64B alignment is recommended for optimal performance. - */ -#define PDMA_OUT_BUF_ADDR_MASK (0xFFFFFFFFUL) -#define PDMA_OUT_BUF_ADDR_SHIFT (0U) -#define PDMA_OUT_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_OUT_BUF_ADDR_SHIFT) & PDMA_OUT_BUF_ADDR_MASK) -#define PDMA_OUT_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_OUT_BUF_ADDR_MASK) >> PDMA_OUT_BUF_ADDR_SHIFT) - -/* Bitfield definition for register: OUT_PITCH */ -/* - * BYTELEN (RW) - * - * Indicates the number of bytes in memory between two vertically adjacent pixels. - */ -#define PDMA_OUT_PITCH_BYTELEN_MASK (0xFFFFU) -#define PDMA_OUT_PITCH_BYTELEN_SHIFT (0U) -#define PDMA_OUT_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_OUT_PITCH_BYTELEN_SHIFT) & PDMA_OUT_PITCH_BYTELEN_MASK) -#define PDMA_OUT_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_OUT_PITCH_BYTELEN_MASK) >> PDMA_OUT_PITCH_BYTELEN_SHIFT) - -/* Bitfield definition for register: OUT_LRC */ -/* - * Y (RW) - * - * This field indicates the lower right Y-coordinate (in pixels) of the output frame buffer. - * The value is the height of the output image size. - */ -#define PDMA_OUT_LRC_Y_MASK (0x3FFF0000UL) -#define PDMA_OUT_LRC_Y_SHIFT (16U) -#define PDMA_OUT_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_Y_SHIFT) & PDMA_OUT_LRC_Y_MASK) -#define PDMA_OUT_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_Y_MASK) >> PDMA_OUT_LRC_Y_SHIFT) - -/* - * X (RW) - * - * This field indicates the lower right X-coordinate (in pixels) of the output frame buffer. - * Should be the width of the output image size. - */ -#define PDMA_OUT_LRC_X_MASK (0x3FFFU) -#define PDMA_OUT_LRC_X_SHIFT (0U) -#define PDMA_OUT_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_LRC_X_SHIFT) & PDMA_OUT_LRC_X_MASK) -#define PDMA_OUT_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_LRC_X_MASK) >> PDMA_OUT_LRC_X_SHIFT) - -/* Bitfield definition for register of struct array OUT_PS: ULC */ -/* - * Y (RW) - * - * This field indicates the upper left Y-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_ULC_Y_MASK (0x3FFF0000UL) -#define PDMA_OUT_PS_ULC_Y_SHIFT (16U) -#define PDMA_OUT_PS_ULC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_Y_SHIFT) & PDMA_OUT_PS_ULC_Y_MASK) -#define PDMA_OUT_PS_ULC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_Y_MASK) >> PDMA_OUT_PS_ULC_Y_SHIFT) - -/* - * X (RW) - * - * This field indicates the upper left X-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_ULC_X_MASK (0x3FFFU) -#define PDMA_OUT_PS_ULC_X_SHIFT (0U) -#define PDMA_OUT_PS_ULC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_ULC_X_SHIFT) & PDMA_OUT_PS_ULC_X_MASK) -#define PDMA_OUT_PS_ULC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_ULC_X_MASK) >> PDMA_OUT_PS_ULC_X_SHIFT) - -/* Bitfield definition for register of struct array OUT_PS: LRC */ -/* - * Y (RW) - * - * This field indicates the lower right Y-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_LRC_Y_MASK (0x3FFF0000UL) -#define PDMA_OUT_PS_LRC_Y_SHIFT (16U) -#define PDMA_OUT_PS_LRC_Y_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_Y_SHIFT) & PDMA_OUT_PS_LRC_Y_MASK) -#define PDMA_OUT_PS_LRC_Y_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_Y_MASK) >> PDMA_OUT_PS_LRC_Y_SHIFT) - -/* - * X (RW) - * - * This field indicates the lower right X-coordinate (in pixels) of the processed surface in the output frame buffer. - */ -#define PDMA_OUT_PS_LRC_X_MASK (0x3FFFU) -#define PDMA_OUT_PS_LRC_X_SHIFT (0U) -#define PDMA_OUT_PS_LRC_X_SET(x) (((uint32_t)(x) << PDMA_OUT_PS_LRC_X_SHIFT) & PDMA_OUT_PS_LRC_X_MASK) -#define PDMA_OUT_PS_LRC_X_GET(x) (((uint32_t)(x) & PDMA_OUT_PS_LRC_X_MASK) >> PDMA_OUT_PS_LRC_X_SHIFT) - -/* Bitfield definition for register of struct array PS: CTRL */ -/* - * PL_ONLY_BLENDOP (RW) - * - * 1: For those pixels that are this plane-only, use the colcor values and alpha values directly as blender output for un-normalized outputs configurations. - * 0: For those pixels that are this plane-only, the operations are determined by other operation configurations. - */ -#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK (0x1000000UL) -#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT (24U) -#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT) & PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK) -#define PDMA_PS_CTRL_PL_ONLY_BLENDOP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PL_ONLY_BLENDOP_MASK) >> PDMA_PS_CTRL_PL_ONLY_BLENDOP_SHIFT) - -/* - * INB13_SWAP (RW) - * - * Swap bit[31:24] and bit [15:8] before pack_dir operation. - */ -#define PDMA_PS_CTRL_INB13_SWAP_MASK (0x100000UL) -#define PDMA_PS_CTRL_INB13_SWAP_SHIFT (20U) -#define PDMA_PS_CTRL_INB13_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_INB13_SWAP_SHIFT) & PDMA_PS_CTRL_INB13_SWAP_MASK) -#define PDMA_PS_CTRL_INB13_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_INB13_SWAP_MASK) >> PDMA_PS_CTRL_INB13_SWAP_SHIFT) - -/* - * PACK_DIR (RW) - * - * Decide the byte sequence of the 32-bit word {A3, A2, A1, A0}. The bit sequence ina byte is not changed. - * 2'b00: no change {A3, A2, A1, A0} - * 2'b01: {A2, A3, A0, A1} - * 2'b10: {A1, A0, A3, A2} - * 2'b11: {A0, A1, A2, A3} - */ -#define PDMA_PS_CTRL_PACK_DIR_MASK (0xC0000UL) -#define PDMA_PS_CTRL_PACK_DIR_SHIFT (18U) -#define PDMA_PS_CTRL_PACK_DIR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_PACK_DIR_SHIFT) & PDMA_PS_CTRL_PACK_DIR_MASK) -#define PDMA_PS_CTRL_PACK_DIR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_PACK_DIR_MASK) >> PDMA_PS_CTRL_PACK_DIR_SHIFT) - -/* - * BKGCL4CLR (RW) - * - * Enable to use background color for clear area - */ -#define PDMA_PS_CTRL_BKGCL4CLR_MASK (0x20000UL) -#define PDMA_PS_CTRL_BKGCL4CLR_SHIFT (17U) -#define PDMA_PS_CTRL_BKGCL4CLR_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BKGCL4CLR_SHIFT) & PDMA_PS_CTRL_BKGCL4CLR_MASK) -#define PDMA_PS_CTRL_BKGCL4CLR_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BKGCL4CLR_MASK) >> PDMA_PS_CTRL_BKGCL4CLR_SHIFT) - -/* - * YCBCR_MODE (RW) - * - * YCbCr mode or YUV mode - */ -#define PDMA_PS_CTRL_YCBCR_MODE_MASK (0x10000UL) -#define PDMA_PS_CTRL_YCBCR_MODE_SHIFT (16U) -#define PDMA_PS_CTRL_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_YCBCR_MODE_SHIFT) & PDMA_PS_CTRL_YCBCR_MODE_MASK) -#define PDMA_PS_CTRL_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_YCBCR_MODE_MASK) >> PDMA_PS_CTRL_YCBCR_MODE_SHIFT) - -/* - * BYPASS (RW) - * - * Asserted to bypass the CSC stage - */ -#define PDMA_PS_CTRL_BYPASS_MASK (0x8000U) -#define PDMA_PS_CTRL_BYPASS_SHIFT (15U) -#define PDMA_PS_CTRL_BYPASS_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_BYPASS_SHIFT) & PDMA_PS_CTRL_BYPASS_MASK) -#define PDMA_PS_CTRL_BYPASS_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_BYPASS_MASK) >> PDMA_PS_CTRL_BYPASS_SHIFT) - -/* - * VFLIP (RW) - * - * Indicates that the input should be flipped vertically (effect applied before rotation). - */ -#define PDMA_PS_CTRL_VFLIP_MASK (0x4000U) -#define PDMA_PS_CTRL_VFLIP_SHIFT (14U) -#define PDMA_PS_CTRL_VFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_VFLIP_SHIFT) & PDMA_PS_CTRL_VFLIP_MASK) -#define PDMA_PS_CTRL_VFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_VFLIP_MASK) >> PDMA_PS_CTRL_VFLIP_SHIFT) - -/* - * HFLIP (RW) - * - * Indicates that the input should be flipped horizontally (effect applied before rotation). - */ -#define PDMA_PS_CTRL_HFLIP_MASK (0x2000U) -#define PDMA_PS_CTRL_HFLIP_SHIFT (13U) -#define PDMA_PS_CTRL_HFLIP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HFLIP_SHIFT) & PDMA_PS_CTRL_HFLIP_MASK) -#define PDMA_PS_CTRL_HFLIP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HFLIP_MASK) >> PDMA_PS_CTRL_HFLIP_SHIFT) - -/* - * ROTATE (RW) - * - * Indicates the clockwise rotation to be applied at the input buffer. The rotation effect is defined as occurring - * after the FLIP_X and FLIP_Y permutation. - * 0x0 ROT_0 - * 0x1 ROT_90 - * 0x2 ROT_180 - * 0x3 ROT_270 - */ -#define PDMA_PS_CTRL_ROTATE_MASK (0x1800U) -#define PDMA_PS_CTRL_ROTATE_SHIFT (11U) -#define PDMA_PS_CTRL_ROTATE_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_ROTATE_SHIFT) & PDMA_PS_CTRL_ROTATE_MASK) -#define PDMA_PS_CTRL_ROTATE_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_ROTATE_MASK) >> PDMA_PS_CTRL_ROTATE_SHIFT) - -/* - * DECY (RW) - * - * Verticle pre decimation filter control. - * 0x0 DISABLE - Disable pre-decimation filter. - * 0x1 DECY2 - Decimate PS by 2. - * 0x2 DECY4 - Decimate PS by 4. - * 0x3 DECY8 - Decimate PS by 8. - */ -#define PDMA_PS_CTRL_DECY_MASK (0x600U) -#define PDMA_PS_CTRL_DECY_SHIFT (9U) -#define PDMA_PS_CTRL_DECY_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECY_SHIFT) & PDMA_PS_CTRL_DECY_MASK) -#define PDMA_PS_CTRL_DECY_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECY_MASK) >> PDMA_PS_CTRL_DECY_SHIFT) - -/* - * DECX (RW) - * - * Horizontal pre decimation filter control. - * 0x0 DISABLE - Disable pre-decimation filter. - * 0x1 DECX2 - Decimate PS by 2. - * 0x2 DECX4 - Decimate PS by 4. - * 0x3 DECX8 - Decimate PS by 8. - */ -#define PDMA_PS_CTRL_DECX_MASK (0x180U) -#define PDMA_PS_CTRL_DECX_SHIFT (7U) -#define PDMA_PS_CTRL_DECX_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_DECX_SHIFT) & PDMA_PS_CTRL_DECX_MASK) -#define PDMA_PS_CTRL_DECX_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_DECX_MASK) >> PDMA_PS_CTRL_DECX_SHIFT) - -/* - * HW_BYTE_SWAP (RW) - * - * Swap bytes in half-words. For each 16 bit half-word, the two bytes will be swapped. - */ -#define PDMA_PS_CTRL_HW_BYTE_SWAP_MASK (0x40U) -#define PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT (6U) -#define PDMA_PS_CTRL_HW_BYTE_SWAP_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) -#define PDMA_PS_CTRL_HW_BYTE_SWAP_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_HW_BYTE_SWAP_MASK) >> PDMA_PS_CTRL_HW_BYTE_SWAP_SHIFT) - -/* - * FORMAT (RW) - * - * PS buffer format. To select between YUV and YCbCr formats, see bit 16 of this register. - * 0x0 ARGB888 - 32-bit pixels, byte sequence as B,G,R,A - * 0xE RGB565 - 16-bit pixels, byte sequence as B,R - * 0x13 YUYV1P422 - 16-bit pixels (1-plane byte sequence Y0,U0,Y1,V0 interleaved bytes) - */ -#define PDMA_PS_CTRL_FORMAT_MASK (0x3FU) -#define PDMA_PS_CTRL_FORMAT_SHIFT (0U) -#define PDMA_PS_CTRL_FORMAT_SET(x) (((uint32_t)(x) << PDMA_PS_CTRL_FORMAT_SHIFT) & PDMA_PS_CTRL_FORMAT_MASK) -#define PDMA_PS_CTRL_FORMAT_GET(x) (((uint32_t)(x) & PDMA_PS_CTRL_FORMAT_MASK) >> PDMA_PS_CTRL_FORMAT_SHIFT) - -/* Bitfield definition for register of struct array PS: BUF */ -/* - * ADDR (RW) - * - * Address pointer for the PS RGB or Y (luma) input buffer. - */ -#define PDMA_PS_BUF_ADDR_MASK (0xFFFFFFFFUL) -#define PDMA_PS_BUF_ADDR_SHIFT (0U) -#define PDMA_PS_BUF_ADDR_SET(x) (((uint32_t)(x) << PDMA_PS_BUF_ADDR_SHIFT) & PDMA_PS_BUF_ADDR_MASK) -#define PDMA_PS_BUF_ADDR_GET(x) (((uint32_t)(x) & PDMA_PS_BUF_ADDR_MASK) >> PDMA_PS_BUF_ADDR_SHIFT) - -/* Bitfield definition for register of struct array PS: PITCH */ -/* - * BYTELEN (RW) - * - * Indicates the number of bytes in memory between two vertically adjacent pixels. - */ -#define PDMA_PS_PITCH_BYTELEN_MASK (0xFFFFU) -#define PDMA_PS_PITCH_BYTELEN_SHIFT (0U) -#define PDMA_PS_PITCH_BYTELEN_SET(x) (((uint32_t)(x) << PDMA_PS_PITCH_BYTELEN_SHIFT) & PDMA_PS_PITCH_BYTELEN_MASK) -#define PDMA_PS_PITCH_BYTELEN_GET(x) (((uint32_t)(x) & PDMA_PS_PITCH_BYTELEN_MASK) >> PDMA_PS_PITCH_BYTELEN_SHIFT) - -/* Bitfield definition for register of struct array PS: BKGD */ -/* - * COLOR (RW) - * - * Background color (in 32bpp format) for any pixels not within the scaled range of the picture, but within the buffer range specified by the PS ULC/LRC. The top 8-bit is the alpha channel. - */ -#define PDMA_PS_BKGD_COLOR_MASK (0xFFFFFFFFUL) -#define PDMA_PS_BKGD_COLOR_SHIFT (0U) -#define PDMA_PS_BKGD_COLOR_SET(x) (((uint32_t)(x) << PDMA_PS_BKGD_COLOR_SHIFT) & PDMA_PS_BKGD_COLOR_MASK) -#define PDMA_PS_BKGD_COLOR_GET(x) (((uint32_t)(x) & PDMA_PS_BKGD_COLOR_MASK) >> PDMA_PS_BKGD_COLOR_SHIFT) - -/* Bitfield definition for register of struct array PS: SCALE */ -/* - * Y (RW) - * - * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the X scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - */ -#define PDMA_PS_SCALE_Y_MASK (0x7FFF0000UL) -#define PDMA_PS_SCALE_Y_SHIFT (16U) -#define PDMA_PS_SCALE_Y_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_Y_SHIFT) & PDMA_PS_SCALE_Y_MASK) -#define PDMA_PS_SCALE_Y_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_Y_MASK) >> PDMA_PS_SCALE_Y_SHIFT) - -/* - * X (RW) - * - * This is a two bit integer and 12 bit fractional representation (##.####_####_####) of the Y scaling factor for the PS source buffer. The maximum value programmed should be 2 since scaling down by a factor greater than 2 is not supported with the bilinear filter. Decimation and the bilinear filter should be used together to achieve scaling by more than a factor of 2. - */ -#define PDMA_PS_SCALE_X_MASK (0x7FFFU) -#define PDMA_PS_SCALE_X_SHIFT (0U) -#define PDMA_PS_SCALE_X_SET(x) (((uint32_t)(x) << PDMA_PS_SCALE_X_SHIFT) & PDMA_PS_SCALE_X_MASK) -#define PDMA_PS_SCALE_X_GET(x) (((uint32_t)(x) & PDMA_PS_SCALE_X_MASK) >> PDMA_PS_SCALE_X_SHIFT) - -/* Bitfield definition for register of struct array PS: OFFSET */ -/* - * Y (RW) - * - * This is a 12 bit fractional representation (0.####_####_####) of the Y scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. - * It is applied after the decimation filter stage, and before the bilinear filter stage. - */ -#define PDMA_PS_OFFSET_Y_MASK (0xFFF0000UL) -#define PDMA_PS_OFFSET_Y_SHIFT (16U) -#define PDMA_PS_OFFSET_Y_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_Y_SHIFT) & PDMA_PS_OFFSET_Y_MASK) -#define PDMA_PS_OFFSET_Y_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_Y_MASK) >> PDMA_PS_OFFSET_Y_SHIFT) - -/* - * X (RW) - * - * This is a 12 bit fractional representation (0.####_####_####) of the X scaling offset. This represents a fixed pixel offset which gets added to the scaled address to determine source data for the scaling engine. - * It is applied after the decimation filter stage, and before the bilinear filter stage. - */ -#define PDMA_PS_OFFSET_X_MASK (0xFFFU) -#define PDMA_PS_OFFSET_X_SHIFT (0U) -#define PDMA_PS_OFFSET_X_SET(x) (((uint32_t)(x) << PDMA_PS_OFFSET_X_SHIFT) & PDMA_PS_OFFSET_X_MASK) -#define PDMA_PS_OFFSET_X_GET(x) (((uint32_t)(x) & PDMA_PS_OFFSET_X_MASK) >> PDMA_PS_OFFSET_X_SHIFT) - -/* Bitfield definition for register of struct array PS: CLRKEY_LOW */ -/* - * LIMIT (RW) - * - * Low range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000. - */ -#define PDMA_PS_CLRKEY_LOW_LIMIT_MASK (0xFFFFFFUL) -#define PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT (0U) -#define PDMA_PS_CLRKEY_LOW_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) -#define PDMA_PS_CLRKEY_LOW_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_LOW_LIMIT_MASK) >> PDMA_PS_CLRKEY_LOW_LIMIT_SHIFT) - -/* Bitfield definition for register of struct array PS: CLRKEY_HIGH */ -/* - * LIMIT (RW) - * - * High range of color key applied to PS buffer. To disable PS colorkeying, set the low colorkey to 0xFFFFFF and the high colorkey to 0x000000 - */ -#define PDMA_PS_CLRKEY_HIGH_LIMIT_MASK (0xFFFFFFUL) -#define PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT (0U) -#define PDMA_PS_CLRKEY_HIGH_LIMIT_SET(x) (((uint32_t)(x) << PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) -#define PDMA_PS_CLRKEY_HIGH_LIMIT_GET(x) (((uint32_t)(x) & PDMA_PS_CLRKEY_HIGH_LIMIT_MASK) >> PDMA_PS_CLRKEY_HIGH_LIMIT_SHIFT) - -/* Bitfield definition for register of struct array PS: ORG */ -/* - * HIGHT (RW) - * - * The number of vertical pixels of the original frame (not -1) - */ -#define PDMA_PS_ORG_HIGHT_MASK (0x3FFF0000UL) -#define PDMA_PS_ORG_HIGHT_SHIFT (16U) -#define PDMA_PS_ORG_HIGHT_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_HIGHT_SHIFT) & PDMA_PS_ORG_HIGHT_MASK) -#define PDMA_PS_ORG_HIGHT_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_HIGHT_MASK) >> PDMA_PS_ORG_HIGHT_SHIFT) - -/* - * WIDTH (RW) - * - * The number of horizontal pixels of the original frame (not -1) - */ -#define PDMA_PS_ORG_WIDTH_MASK (0x3FFFU) -#define PDMA_PS_ORG_WIDTH_SHIFT (0U) -#define PDMA_PS_ORG_WIDTH_SET(x) (((uint32_t)(x) << PDMA_PS_ORG_WIDTH_SHIFT) & PDMA_PS_ORG_WIDTH_MASK) -#define PDMA_PS_ORG_WIDTH_GET(x) (((uint32_t)(x) & PDMA_PS_ORG_WIDTH_MASK) >> PDMA_PS_ORG_WIDTH_SHIFT) - -/* Bitfield definition for register: YUV2RGB_COEF0 */ -/* - * C0 (RW) - * - * Two's compliment Y multiplier coefficient C0. YUV=0x100 (1.000) YCbCr=0x12A (1.164) - */ -#define PDMA_YUV2RGB_COEF0_C0_MASK (0x1FFC0000UL) -#define PDMA_YUV2RGB_COEF0_C0_SHIFT (18U) -#define PDMA_YUV2RGB_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_C0_SHIFT) & PDMA_YUV2RGB_COEF0_C0_MASK) -#define PDMA_YUV2RGB_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_C0_MASK) >> PDMA_YUV2RGB_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * Two's compliment phase offset implicit for CbCr data UV_OFFSET. Generally used for YCbCr to RGB conversion. - * YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to 0.5 range). - */ -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT (9U) -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) -#define PDMA_YUV2RGB_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_UV_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * Two's compliment amplitude offset implicit in the Y data Y_OFFSET. For YUV, this is typically 0 and for YCbCr, this is - * typically -16 (0x1F0). - */ -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK (0x1FFU) -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT (0U) -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) -#define PDMA_YUV2RGB_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF0_Y_OFFSET_MASK) >> PDMA_YUV2RGB_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: YUV2RGB_COEF1 */ -/* - * C1 (RW) - * - * Two's compliment Red V/Cr multiplier coefficient C1. YUV=0x123 (1.140) YCbCr=0x198 (1.596). - */ -#define PDMA_YUV2RGB_COEF1_C1_MASK (0x7FF0000UL) -#define PDMA_YUV2RGB_COEF1_C1_SHIFT (16U) -#define PDMA_YUV2RGB_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C1_SHIFT) & PDMA_YUV2RGB_COEF1_C1_MASK) -#define PDMA_YUV2RGB_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C1_MASK) >> PDMA_YUV2RGB_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * Two's compliment Blue U/Cb multiplier coefficient C4. YUV=0x208 (2.032) YCbCr=0x204 (2.017). - */ -#define PDMA_YUV2RGB_COEF1_C4_MASK (0x7FFU) -#define PDMA_YUV2RGB_COEF1_C4_SHIFT (0U) -#define PDMA_YUV2RGB_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF1_C4_SHIFT) & PDMA_YUV2RGB_COEF1_C4_MASK) -#define PDMA_YUV2RGB_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF1_C4_MASK) >> PDMA_YUV2RGB_COEF1_C4_SHIFT) - -/* Bitfield definition for register: YUV2RGB_COEF2 */ -/* - * C2 (RW) - * - * Two's compliment Green V/Cr multiplier coefficient C2. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). - */ -#define PDMA_YUV2RGB_COEF2_C2_MASK (0x7FF0000UL) -#define PDMA_YUV2RGB_COEF2_C2_SHIFT (16U) -#define PDMA_YUV2RGB_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C2_SHIFT) & PDMA_YUV2RGB_COEF2_C2_MASK) -#define PDMA_YUV2RGB_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C2_MASK) >> PDMA_YUV2RGB_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * Two's compliment Green U/Cb multiplier coefficient C3. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). - */ -#define PDMA_YUV2RGB_COEF2_C3_MASK (0x7FFU) -#define PDMA_YUV2RGB_COEF2_C3_SHIFT (0U) -#define PDMA_YUV2RGB_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_YUV2RGB_COEF2_C3_SHIFT) & PDMA_YUV2RGB_COEF2_C3_MASK) -#define PDMA_YUV2RGB_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_YUV2RGB_COEF2_C3_MASK) >> PDMA_YUV2RGB_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF0 */ -/* - * YCBCR_MODE (RW) - * - * Asserted to use YCrCb mode - */ -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK (0x80000000UL) -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT (31U) -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) -#define PDMA_RGB2YUV_COEF0_YCBCR_MODE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_YCBCR_MODE_MASK) >> PDMA_RGB2YUV_COEF0_YCBCR_MODE_SHIFT) - -/* - * ENABLE (RW) - * - * Asserted to enable this RGB2YUV CSC stage - */ -#define PDMA_RGB2YUV_COEF0_ENABLE_MASK (0x40000000UL) -#define PDMA_RGB2YUV_COEF0_ENABLE_SHIFT (30U) -#define PDMA_RGB2YUV_COEF0_ENABLE_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) -#define PDMA_RGB2YUV_COEF0_ENABLE_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_ENABLE_MASK) >> PDMA_RGB2YUV_COEF0_ENABLE_SHIFT) - -/* - * C0 (RW) - * - * CSC parameters C0 - */ -#define PDMA_RGB2YUV_COEF0_C0_MASK (0x1FFC0000UL) -#define PDMA_RGB2YUV_COEF0_C0_SHIFT (18U) -#define PDMA_RGB2YUV_COEF0_C0_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_C0_SHIFT) & PDMA_RGB2YUV_COEF0_C0_MASK) -#define PDMA_RGB2YUV_COEF0_C0_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_C0_MASK) >> PDMA_RGB2YUV_COEF0_C0_SHIFT) - -/* - * UV_OFFSET (RW) - * - * CSC parameters UV_OFFSET - */ -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK (0x3FE00UL) -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT (9U) -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) -#define PDMA_RGB2YUV_COEF0_UV_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_UV_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_UV_OFFSET_SHIFT) - -/* - * Y_OFFSET (RW) - * - * CSC parameters Y_OFFSET - */ -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK (0x1FFU) -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT (0U) -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) -#define PDMA_RGB2YUV_COEF0_Y_OFFSET_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF0_Y_OFFSET_MASK) >> PDMA_RGB2YUV_COEF0_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF1 */ -/* - * C1 (RW) - * - * CSC parameters C1 - */ -#define PDMA_RGB2YUV_COEF1_C1_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF1_C1_SHIFT (16U) -#define PDMA_RGB2YUV_COEF1_C1_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C1_SHIFT) & PDMA_RGB2YUV_COEF1_C1_MASK) -#define PDMA_RGB2YUV_COEF1_C1_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C1_MASK) >> PDMA_RGB2YUV_COEF1_C1_SHIFT) - -/* - * C4 (RW) - * - * CSC parameters C4 - */ -#define PDMA_RGB2YUV_COEF1_C4_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF1_C4_SHIFT (0U) -#define PDMA_RGB2YUV_COEF1_C4_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF1_C4_SHIFT) & PDMA_RGB2YUV_COEF1_C4_MASK) -#define PDMA_RGB2YUV_COEF1_C4_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF1_C4_MASK) >> PDMA_RGB2YUV_COEF1_C4_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF2 */ -/* - * C2 (RW) - * - * CSC parameters C2 - */ -#define PDMA_RGB2YUV_COEF2_C2_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF2_C2_SHIFT (16U) -#define PDMA_RGB2YUV_COEF2_C2_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C2_SHIFT) & PDMA_RGB2YUV_COEF2_C2_MASK) -#define PDMA_RGB2YUV_COEF2_C2_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C2_MASK) >> PDMA_RGB2YUV_COEF2_C2_SHIFT) - -/* - * C3 (RW) - * - * CSC parameters C3 - */ -#define PDMA_RGB2YUV_COEF2_C3_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF2_C3_SHIFT (0U) -#define PDMA_RGB2YUV_COEF2_C3_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF2_C3_SHIFT) & PDMA_RGB2YUV_COEF2_C3_MASK) -#define PDMA_RGB2YUV_COEF2_C3_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF2_C3_MASK) >> PDMA_RGB2YUV_COEF2_C3_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF3 */ -/* - * C6 (RW) - * - * CSC parameters C6 - */ -#define PDMA_RGB2YUV_COEF3_C6_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF3_C6_SHIFT (16U) -#define PDMA_RGB2YUV_COEF3_C6_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C6_SHIFT) & PDMA_RGB2YUV_COEF3_C6_MASK) -#define PDMA_RGB2YUV_COEF3_C6_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C6_MASK) >> PDMA_RGB2YUV_COEF3_C6_SHIFT) - -/* - * C5 (RW) - * - * CSC parameters C5 - */ -#define PDMA_RGB2YUV_COEF3_C5_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF3_C5_SHIFT (0U) -#define PDMA_RGB2YUV_COEF3_C5_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF3_C5_SHIFT) & PDMA_RGB2YUV_COEF3_C5_MASK) -#define PDMA_RGB2YUV_COEF3_C5_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF3_C5_MASK) >> PDMA_RGB2YUV_COEF3_C5_SHIFT) - -/* Bitfield definition for register: RGB2YUV_COEF4 */ -/* - * C8 (RW) - * - * CSC parameters C8 - */ -#define PDMA_RGB2YUV_COEF4_C8_MASK (0x7FF0000UL) -#define PDMA_RGB2YUV_COEF4_C8_SHIFT (16U) -#define PDMA_RGB2YUV_COEF4_C8_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C8_SHIFT) & PDMA_RGB2YUV_COEF4_C8_MASK) -#define PDMA_RGB2YUV_COEF4_C8_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C8_MASK) >> PDMA_RGB2YUV_COEF4_C8_SHIFT) - -/* - * C7 (RW) - * - * CSC parameters C7 - */ -#define PDMA_RGB2YUV_COEF4_C7_MASK (0x7FFU) -#define PDMA_RGB2YUV_COEF4_C7_SHIFT (0U) -#define PDMA_RGB2YUV_COEF4_C7_SET(x) (((uint32_t)(x) << PDMA_RGB2YUV_COEF4_C7_SHIFT) & PDMA_RGB2YUV_COEF4_C7_MASK) -#define PDMA_RGB2YUV_COEF4_C7_GET(x) (((uint32_t)(x) & PDMA_RGB2YUV_COEF4_C7_MASK) >> PDMA_RGB2YUV_COEF4_C7_SHIFT) - - - -/* OUT_PS register group index macro definition */ -#define PDMA_OUT_PS_0 (0UL) -#define PDMA_OUT_PS_1 (1UL) - -/* PS register group index macro definition */ -#define PDMA_PS_0 (0UL) -#define PDMA_PS_1 (1UL) - - -#endif /* HPM_PDMA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pgpr_regs.h deleted file mode 100644 index acf20cfecd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pgpr_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PGPR_H -#define HPM_PGPR_H - -typedef struct { - __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ - __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ - __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ - __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ - __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ - __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ - __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ - __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ - __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ - __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ - __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ - __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ - __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ - __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ - __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ - __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ -} PGPR_Type; - - -/* Bitfield definition for register: PMIC_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) -#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) -#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) -#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) -#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR04 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) -#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR05 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) -#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR06 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) -#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR07 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) -#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR08 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) -#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR09 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) -#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR10 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) -#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR11 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) -#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR12 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) -#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR13 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) -#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR14 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) -#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR15 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) -#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) - - - - -#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pixelmux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pixelmux_regs.h deleted file mode 100644 index aeb75d2e7a0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pixelmux_regs.h +++ /dev/null @@ -1,1860 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PIXELMUX_H -#define HPM_PIXELMUX_H - -typedef struct { - __RW uint32_t PIXMUX; /* 0x0: pixel path mux register */ - __RW uint32_t DSI_SETTING[2]; /* 0x4 - 0x8: DSI0 config register */ - __RW uint32_t MISC; /* 0xC: common register */ - __RW uint32_t GPR_WR_D0; /* 0x10: gpr write-read register 0 */ - __RW uint32_t GPR_WR_D1; /* 0x14: gpr write-read register 1 */ - __RW uint32_t GPR_WR_D2; /* 0x18: gpr write-read register 2 */ - __RW uint32_t GPR_WR_D3; /* 0x1C: gpr write-read register 3 */ - __RW uint32_t GPR_WR_D4; /* 0x20: gpr write-read register 4 */ - __RW uint32_t GPR_WR_D5; /* 0x24: gpr write-read register 5 */ - __RW uint32_t GPR_WR_D6; /* 0x28: gpr write-read register 6 */ - __RW uint32_t GPR_WR_D7; /* 0x2C: gpr write-read register 7 */ - __RW uint32_t GPR_WR_D8; /* 0x30: gpr write-read register 8 */ - __RW uint32_t GPR_WR_D9; /* 0x34: gpr write-read register 9 */ - __R uint32_t GPR_RO_D0; /* 0x38: gpr read-only register 0 */ - __R uint32_t GPR_RO_D1; /* 0x3C: gpr read-only register 1 */ - __R uint32_t GPR_RO_D2; /* 0x40: gpr read-only register 2 */ - __R uint32_t GPR_RO_D3; /* 0x44: gpr read-only register 3 */ - __R uint32_t GPR_RO_D4; /* 0x48: gpr read-only register 4 */ - __R uint32_t GPR_RO_D5; /* 0x4C: gpr read-only register 5 */ - __R uint32_t GPR_RO_D6; /* 0x50: gpr read-only register 6 */ - __R uint32_t GPR_RO_D7; /* 0x54: gpr read-only register 7 */ - __R uint32_t GPR_RO_D8; /* 0x58: gpr read-only register 8 */ - __R uint32_t GPR_RO_D9; /* 0x5C: gpr read-only register 9 */ - __RW uint32_t GPR_WR1_CLR_D0; /* 0x60: gpr write1 set/no-write clr register */ -} PIXELMUX_Type; - - -/* Bitfield definition for register: PIXMUX */ -/* - * RGB_EN (RW) - * - * RGB pixel bus enable - */ -#define PIXELMUX_PIXMUX_RGB_EN_MASK (0x20000000UL) -#define PIXELMUX_PIXMUX_RGB_EN_SHIFT (29U) -#define PIXELMUX_PIXMUX_RGB_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_EN_SHIFT) & PIXELMUX_PIXMUX_RGB_EN_MASK) -#define PIXELMUX_PIXMUX_RGB_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_EN_MASK) >> PIXELMUX_PIXMUX_RGB_EN_SHIFT) - -/* - * RGB_SEL (RW) - * - * RGB pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_RGB_SEL_MASK (0x10000000UL) -#define PIXELMUX_PIXMUX_RGB_SEL_SHIFT (28U) -#define PIXELMUX_PIXMUX_RGB_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_RGB_SEL_SHIFT) & PIXELMUX_PIXMUX_RGB_SEL_MASK) -#define PIXELMUX_PIXMUX_RGB_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_RGB_SEL_MASK) >> PIXELMUX_PIXMUX_RGB_SEL_SHIFT) - -/* - * GWC1_EN (RW) - * - * GWC1 pixel bus enable - */ -#define PIXELMUX_PIXMUX_GWC1_EN_MASK (0x8000000UL) -#define PIXELMUX_PIXMUX_GWC1_EN_SHIFT (27U) -#define PIXELMUX_PIXMUX_GWC1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_EN_SHIFT) & PIXELMUX_PIXMUX_GWC1_EN_MASK) -#define PIXELMUX_PIXMUX_GWC1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_EN_MASK) >> PIXELMUX_PIXMUX_GWC1_EN_SHIFT) - -/* - * GWC1_SEL (RW) - * - * GWC1 pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_GWC1_SEL_MASK (0x4000000UL) -#define PIXELMUX_PIXMUX_GWC1_SEL_SHIFT (26U) -#define PIXELMUX_PIXMUX_GWC1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) -#define PIXELMUX_PIXMUX_GWC1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC1_SEL_MASK) >> PIXELMUX_PIXMUX_GWC1_SEL_SHIFT) - -/* - * GWC0_EN (RW) - * - * GWC0 pixel bus enable - */ -#define PIXELMUX_PIXMUX_GWC0_EN_MASK (0x2000000UL) -#define PIXELMUX_PIXMUX_GWC0_EN_SHIFT (25U) -#define PIXELMUX_PIXMUX_GWC0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_EN_SHIFT) & PIXELMUX_PIXMUX_GWC0_EN_MASK) -#define PIXELMUX_PIXMUX_GWC0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_EN_MASK) >> PIXELMUX_PIXMUX_GWC0_EN_SHIFT) - -/* - * GWC0_SEL (RW) - * - * GWC0 pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_GWC0_SEL_MASK (0x1000000UL) -#define PIXELMUX_PIXMUX_GWC0_SEL_SHIFT (24U) -#define PIXELMUX_PIXMUX_GWC0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) -#define PIXELMUX_PIXMUX_GWC0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_GWC0_SEL_MASK) >> PIXELMUX_PIXMUX_GWC0_SEL_SHIFT) - -/* - * LVB_DI1_EN (RW) - * - * LVB DI1 pixel bus enable - */ -#define PIXELMUX_PIXMUX_LVB_DI1_EN_MASK (0x800000UL) -#define PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT (23U) -#define PIXELMUX_PIXMUX_LVB_DI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) -#define PIXELMUX_PIXMUX_LVB_DI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_EN_SHIFT) - -/* - * LVB_DI1_SEL (RW) - * - * LVB DI1 pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK (0x400000UL) -#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT (22U) -#define PIXELMUX_PIXMUX_LVB_DI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) -#define PIXELMUX_PIXMUX_LVB_DI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI1_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI1_SEL_SHIFT) - -/* - * LVB_DI0_EN (RW) - * - * LVB DI0 pixel bus enable - */ -#define PIXELMUX_PIXMUX_LVB_DI0_EN_MASK (0x200000UL) -#define PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT (21U) -#define PIXELMUX_PIXMUX_LVB_DI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) -#define PIXELMUX_PIXMUX_LVB_DI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_EN_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_EN_SHIFT) - -/* - * LVB_DI0_SEL (RW) - * - * LVB DI0 pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK (0x100000UL) -#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT (20U) -#define PIXELMUX_PIXMUX_LVB_DI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) -#define PIXELMUX_PIXMUX_LVB_DI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_LVB_DI0_SEL_MASK) >> PIXELMUX_PIXMUX_LVB_DI0_SEL_SHIFT) - -/* - * DSI1_EN (RW) - * - * DSI0 pixel bus enable - */ -#define PIXELMUX_PIXMUX_DSI1_EN_MASK (0x80000UL) -#define PIXELMUX_PIXMUX_DSI1_EN_SHIFT (19U) -#define PIXELMUX_PIXMUX_DSI1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_EN_SHIFT) & PIXELMUX_PIXMUX_DSI1_EN_MASK) -#define PIXELMUX_PIXMUX_DSI1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_EN_MASK) >> PIXELMUX_PIXMUX_DSI1_EN_SHIFT) - -/* - * DSI1_SEL (RW) - * - * DSI0 pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_DSI1_SEL_MASK (0x40000UL) -#define PIXELMUX_PIXMUX_DSI1_SEL_SHIFT (18U) -#define PIXELMUX_PIXMUX_DSI1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) -#define PIXELMUX_PIXMUX_DSI1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI1_SEL_MASK) >> PIXELMUX_PIXMUX_DSI1_SEL_SHIFT) - -/* - * DSI0_EN (RW) - * - * DSI1 pixel bus enable - */ -#define PIXELMUX_PIXMUX_DSI0_EN_MASK (0x20000UL) -#define PIXELMUX_PIXMUX_DSI0_EN_SHIFT (17U) -#define PIXELMUX_PIXMUX_DSI0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_EN_SHIFT) & PIXELMUX_PIXMUX_DSI0_EN_MASK) -#define PIXELMUX_PIXMUX_DSI0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_EN_MASK) >> PIXELMUX_PIXMUX_DSI0_EN_SHIFT) - -/* - * DSI0_SEL (RW) - * - * DSI1 pixel bus selection - * 1: LCDC1 - * 0: LCDC0 - */ -#define PIXELMUX_PIXMUX_DSI0_SEL_MASK (0x10000UL) -#define PIXELMUX_PIXMUX_DSI0_SEL_SHIFT (16U) -#define PIXELMUX_PIXMUX_DSI0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) -#define PIXELMUX_PIXMUX_DSI0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_DSI0_SEL_MASK) >> PIXELMUX_PIXMUX_DSI0_SEL_SHIFT) - -/* - * CAM1_EN (RW) - * - * CAM1 pixel bus enable - */ -#define PIXELMUX_PIXMUX_CAM1_EN_MASK (0x80U) -#define PIXELMUX_PIXMUX_CAM1_EN_SHIFT (7U) -#define PIXELMUX_PIXMUX_CAM1_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_EN_SHIFT) & PIXELMUX_PIXMUX_CAM1_EN_MASK) -#define PIXELMUX_PIXMUX_CAM1_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_EN_MASK) >> PIXELMUX_PIXMUX_CAM1_EN_SHIFT) - -/* - * CAM1_SEL (RW) - * - * CAM1 pixel bus selection - * 111: Reserved - * 110: LCB1 - * 101: LCB0 - * 100: LCDC1 - * 011: LCDC0 - * 010: CSI1 - * 001: CSI0 - * 000: DVP - */ -#define PIXELMUX_PIXMUX_CAM1_SEL_MASK (0x70U) -#define PIXELMUX_PIXMUX_CAM1_SEL_SHIFT (4U) -#define PIXELMUX_PIXMUX_CAM1_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) -#define PIXELMUX_PIXMUX_CAM1_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM1_SEL_MASK) >> PIXELMUX_PIXMUX_CAM1_SEL_SHIFT) - -/* - * CAM0_EN (RW) - * - * CAM0 pixel bus enable - */ -#define PIXELMUX_PIXMUX_CAM0_EN_MASK (0x8U) -#define PIXELMUX_PIXMUX_CAM0_EN_SHIFT (3U) -#define PIXELMUX_PIXMUX_CAM0_EN_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_EN_SHIFT) & PIXELMUX_PIXMUX_CAM0_EN_MASK) -#define PIXELMUX_PIXMUX_CAM0_EN_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_EN_MASK) >> PIXELMUX_PIXMUX_CAM0_EN_SHIFT) - -/* - * CAM0_SEL (RW) - * - * CAM0 pixel bus selection - * 111: Reserved - * 110: LCB1 - * 101: LCB0 - * 100: LCDC1 - * 011: LCDC0 - * 010: CSI1 - * 001: CSI0 - * 000: DVP - */ -#define PIXELMUX_PIXMUX_CAM0_SEL_MASK (0x7U) -#define PIXELMUX_PIXMUX_CAM0_SEL_SHIFT (0U) -#define PIXELMUX_PIXMUX_CAM0_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) -#define PIXELMUX_PIXMUX_CAM0_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_PIXMUX_CAM0_SEL_MASK) >> PIXELMUX_PIXMUX_CAM0_SEL_SHIFT) - -/* Bitfield definition for register array: DSI_SETTING */ -/* - * DSI_DATA_ENABLE (RW) - * - * DSI pixel data type enable: - * Bit0: RGB565_CFG1 - * Bit1: RGB565_CFG2 - * Bit2: RGB565_CFG3 - * Bit3: RGB666_CFG1 - * Bit4: RGB666_CFG2 - * Bit5: RGB888 - * Bit6: RGB_10BIT - * Bit7: RGB_12BIT, no support - * Bit8: YUV422_12BIT, no support - * Bit9: YUV422_10BIT, no support - * Bit10: YUV422_8BIT, no support - * Bit11:YUV420_8BIT,no support - * others: Reserved - */ -#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK (0xFFFF0000UL) -#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT (16U) -#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) -#define PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_ENABLE_SHIFT) - -/* - * DSI_DATA_TYPE (RW) - * - * DSI input pixel data type: - * ‘h0: RGB565_CFG1 - * ‘h1: RGB565_CFG2 - * ‘h2: RGB565_CFG3 - * ‘h3: RGB666_CFG1 - * ‘h4: RGB666_CFG2 - * ‘h5: RGB888 - * ‘h6: RGB_10BIT - * ‘h7: RGB_12BIT, no support - * ‘h8:YUV422_12BIT,no support - * ‘h9: YUV422_10BIT, no support - * ‘ha: YUV422_8BIT, no support - * ‘hb: YUV420_8BIT,no support - * ‘hc~’hf: Reserved - */ -#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK (0xFU) -#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT (0U) -#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SET(x) (((uint32_t)(x) << PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) -#define PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_GET(x) (((uint32_t)(x) & PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_MASK) >> PIXELMUX_DSI_SETTING_DSI_DATA_TYPE_SHIFT) - -/* Bitfield definition for register: MISC */ -/* - * LVB_DI1_CTL (RW) - * - * LVB DI1 optional general purpose control which is usually unused by display - */ -#define PIXELMUX_MISC_LVB_DI1_CTL_MASK (0x2U) -#define PIXELMUX_MISC_LVB_DI1_CTL_SHIFT (1U) -#define PIXELMUX_MISC_LVB_DI1_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) -#define PIXELMUX_MISC_LVB_DI1_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI1_CTL_MASK) >> PIXELMUX_MISC_LVB_DI1_CTL_SHIFT) - -/* - * LVB_DI0_CTL (RW) - * - * LVB DI0 optional general purpose control which is usually unused by display - */ -#define PIXELMUX_MISC_LVB_DI0_CTL_MASK (0x1U) -#define PIXELMUX_MISC_LVB_DI0_CTL_SHIFT (0U) -#define PIXELMUX_MISC_LVB_DI0_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) -#define PIXELMUX_MISC_LVB_DI0_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_MISC_LVB_DI0_CTL_MASK) >> PIXELMUX_MISC_LVB_DI0_CTL_SHIFT) - -/* Bitfield definition for register: GPR_WR_D0 */ -/* - * CSI1_CFG_AP_IF_CHECK_EN (RW) - * - * csi1 apb interface parity check enable - */ -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK (0x7C00000UL) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT (22U) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_CHECK_EN_SHIFT) - -/* - * CSI1_CFG_AP_IF_INT_EN (RW) - * - * csi1 apb interface error interrupt enable - */ -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK (0x200000UL) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT (21U) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_AP_IF_INT_EN_SHIFT) - -/* - * CSI1_CFG_APB_SLVERROR_EN (RW) - * - * csi1 apb interface error check enable - */ -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK (0x100000UL) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT (20U) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) -#define PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_CFG_APB_SLVERROR_EN_SHIFT) - -/* - * CSI0_CFG_AP_IF_CHECK_EN (RW) - * - * csi0 apb interface parity check enable - */ -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK (0x7C000UL) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT (14U) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_CHECK_EN_SHIFT) - -/* - * CSI0_CFG_AP_IF_INT_EN (RW) - * - * csi0 apb interface error interrupt enable - */ -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK (0x2000U) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT (13U) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_AP_IF_INT_EN_SHIFT) - -/* - * CSI0_CFG_APB_SLVERROR_EN (RW) - * - * csi0 apb interface error check enable - */ -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK (0x1000U) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT (12U) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) -#define PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_CFG_APB_SLVERROR_EN_SHIFT) - -/* - * DSI1_DPIUPDATECFG (RW) - * - * dsi1 dpi update configure - */ -#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK (0x200U) -#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT (9U) -#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) -#define PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPIUPDATECFG_SHIFT) - -/* - * DSI1_DPICOLORM (RW) - * - * dsi1 dpi cholor mode control - */ -#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK (0x100U) -#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT (8U) -#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) -#define PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPICOLORM_SHIFT) - -/* - * DSI1_DPISHUTDN (RW) - * - * dsi1 dpi shuntdown control - */ -#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK (0x80U) -#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT (7U) -#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) -#define PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_DPISHUTDN_SHIFT) - -/* - * DSI0_DPIUPDATECFG (RW) - * - * dsi0 dpi update configure - */ -#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK (0x40U) -#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT (6U) -#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) -#define PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPIUPDATECFG_SHIFT) - -/* - * DSI0_DPICOLORM (RW) - * - * dsi0 dpi cholor mode control - */ -#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK (0x20U) -#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT (5U) -#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) -#define PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPICOLORM_SHIFT) - -/* - * DSI0_DPISHUTDN (RW) - * - * dsi0 dpi shuntdown control - */ -#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK (0x10U) -#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT (4U) -#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) -#define PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_DPISHUTDN_SHIFT) - -/* - * CSI1_SOFT_RESET_N (RW) - * - * csi controller 1 reset, active low - */ -#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK (0x8U) -#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT (3U) -#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) -#define PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI1_SOFT_RESET_N_SHIFT) - -/* - * CSI0_SOFT_RESET_N (RW) - * - * csi controller 0 reset, active low - */ -#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK (0x4U) -#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT (2U) -#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) -#define PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_CSI0_SOFT_RESET_N_SHIFT) - -/* - * DSI1_SOFT_RESET_N (RW) - * - * dsi controller 1 reset, active low - */ -#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK (0x2U) -#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT (1U) -#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) -#define PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI1_SOFT_RESET_N_SHIFT) - -/* - * DSI0_SOFT_RESET_N (RW) - * - * dsi controller 0 reset, active low - */ -#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK (0x1U) -#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT (0U) -#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) -#define PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_MASK) >> PIXELMUX_GPR_WR_D0_DSI0_SOFT_RESET_N_SHIFT) - -/* Bitfield definition for register: GPR_WR_D1 */ -/* - * JPEG_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK (0xF000000UL) -#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT (24U) -#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_JPEG_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_JPEG_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_JPEG_CTRL_SHIFT) - -/* - * PDMA_P1_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK (0xF00000UL) -#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT (20U) -#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P1_CTRL_SHIFT) - -/* - * PDMA_P0_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK (0xF0000UL) -#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT (16U) -#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_PDMA_P0_CTRL_SHIFT) - -/* - * LCDC1_P1_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK (0xF000U) -#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT (12U) -#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P1_CTRL_SHIFT) - -/* - * LCDC1_P0_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK (0xF00U) -#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT (8U) -#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC1_P0_CTRL_SHIFT) - -/* - * LCDC0_P1_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK (0xF0U) -#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT (4U) -#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P1_CTRL_SHIFT) - -/* - * LCDC0_P0_CTRL (RW) - * - * bit0: select cam0; - * bit1: select cam1; - * bit2: select jpeg; - * bit3: select pdma - */ -#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK (0xFU) -#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT (0U) -#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) -#define PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_MASK) >> PIXELMUX_GPR_WR_D1_LCDC0_P0_CTRL_SHIFT) - -/* Bitfield definition for register: GPR_WR_D2 */ -/* - * TX_PHY0_PORT_PLL_RDY_SEL (RW) - * - * tx phy0 port_pll_rdy_sel - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK (0x20000000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT (29U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PORT_PLL_RDY_SEL_SHIFT) - -/* - * TX_PHY0_RATE_LVDS (RW) - * - * tx phy0 rate_lvds - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK (0x18000000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT (27U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RATE_LVDS_SHIFT) - -/* - * TX_PHY0_PHY_MODE (RW) - * - * tx phy0 phy_mode - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK (0x6000000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT (25U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PHY_MODE_SHIFT) - -/* - * TX_PHY0_REFCLK_DIV (RW) - * - * tx phy0 refclk_div - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK (0xF00000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT (20U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_REFCLK_DIV_SHIFT) - -/* - * TX_PHY0_IDDQ_EN (RW) - * - * tx phy0 iddq_en - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK (0x80000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT (19U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_IDDQ_EN_SHIFT) - -/* - * TX_PHY0_RESET_N (RW) - * - * tx phy0 reset, active low - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK (0x40000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT (18U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_RESET_N_SHIFT) - -/* - * TX_PHY0_SHUTDOWNZ (RW) - * - * tx phy0 shutdownz, active low - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK (0x20000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT (17U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_SHUTDOWNZ_SHIFT) - -/* - * TX_PHY0_BYPS_CKDET (RW) - * - * tx phy0 byps_ckdet - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK (0x10000UL) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT (16U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_BYPS_CKDET_SHIFT) - -/* - * TX_PHY0_PLL_DIV (RW) - * - * tx phy0 pll_div - */ -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK (0x7FFFU) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT (0U) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) -#define PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D2_TX_PHY0_PLL_DIV_SHIFT) - -/* Bitfield definition for register: GPR_WR_D3 */ -/* - * TX_PHY0_PLL_CTRL (RW) - * - * tx phy0 pll_ctrl - */ -#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK (0xFFFFFFFFUL) -#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT (0U) -#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) -#define PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D3_TX_PHY0_PLL_CTRL_SHIFT) - -/* Bitfield definition for register: GPR_WR_D4 */ -/* - * TX_PHY0_TXCK_BIST_EN (RW) - * - * tx phy0 txck_bist_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK (0x80000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT (31U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_BIST_EN_SHIFT) - -/* - * TX_PHY0_TX3_BIST_EN (RW) - * - * tx phy0 tx3_bist_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK (0x40000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT (30U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_BIST_EN_SHIFT) - -/* - * TX_PHY0_TX2_BIST_EN (RW) - * - * tx phy0 tx2_bist_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK (0x20000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT (29U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_BIST_EN_SHIFT) - -/* - * TX_PHY0_TX1_BIST_EN (RW) - * - * tx phy0 tx1_bist_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK (0x10000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT (28U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_BIST_EN_SHIFT) - -/* - * TX_PHY0_TX0_BIST_EN (RW) - * - * tx phy0 tx0_bist_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK (0x8000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT (27U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_BIST_EN_SHIFT) - -/* - * TX_PHY0_TXCK_LPBK_EN (RW) - * - * tx_phy0 txck_lpbk_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK (0x4000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT (26U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_LPBK_EN_SHIFT) - -/* - * TX_PHY0_TX3_LPBK_EN (RW) - * - * tx_phy0 tx3_lpbk_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK (0x2000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT (25U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_LPBK_EN_SHIFT) - -/* - * TX_PHY0_TX2_LPBK_EN (RW) - * - * tx_phy0 tx2_lpbk_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK (0x1000000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT (24U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_LPBK_EN_SHIFT) - -/* - * TX_PHY0_TX1_LPBK_EN (RW) - * - * tx_phy0 tx1_lpbk_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK (0x800000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT (23U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_LPBK_EN_SHIFT) - -/* - * TX_PHY0_TX0_LPBK_EN (RW) - * - * tx_phy0 tx0_lpbk_en - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK (0x400000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT (22U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_LPBK_EN_SHIFT) - -/* - * TX_PHY0_TXCK_PAT_SEL (RW) - * - * tx phy0 txck_pat_sel - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK (0x300000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT (20U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TXCK_PAT_SEL_SHIFT) - -/* - * TX_PHY0_TX3_PAT_SEL (RW) - * - * tx phy0 tx3_pat_sel - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK (0xC0000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT (18U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX3_PAT_SEL_SHIFT) - -/* - * TX_PHY0_TX2_PAT_SEL (RW) - * - * tx phy0 tx2_pat_sel - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK (0x30000UL) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT (16U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX2_PAT_SEL_SHIFT) - -/* - * TX_PHY0_TX1_PAT_SEL (RW) - * - * tx phy0 tx1_pat_sel - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK (0xC000U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT (14U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX1_PAT_SEL_SHIFT) - -/* - * TX_PHY0_TX0_PAT_SEL (RW) - * - * tx phy0 tx0_pat_sel - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK (0x3000U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT (12U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_TX0_PAT_SEL_SHIFT) - -/* - * TX_PHY0_DSI0_PRBS_DISABLE (RW) - * - * tx phy0 dsi0_prbs_disable - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK (0x800U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT (11U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_DISABLE_SHIFT) - -/* - * TX_PHY0_DSI0_PRBS_START (RW) - * - * tx phy0 dsi0_prbs_start - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK (0x400U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT (10U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_DSI0_PRBS_START_SHIFT) - -/* - * TX_PHY0_CKPHY_CTL (RW) - * - * tx phy0 ckphy_ctl - */ -#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK (0x1FFU) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT (0U) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) -#define PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D4_TX_PHY0_CKPHY_CTL_SHIFT) - -/* Bitfield definition for register: GPR_WR_D5 */ -/* - * TX_PHY1_PORT_PLL_RDY_SEL (RW) - * - * tx phy1 port_pll_rdy_sel - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK (0x20000000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT (29U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PORT_PLL_RDY_SEL_SHIFT) - -/* - * TX_PHY1_RATE_LVDS (RW) - * - * tx phy1 rate_lvds - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK (0x18000000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT (27U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RATE_LVDS_SHIFT) - -/* - * TX_PHY1_PHY_MODE (RW) - * - * tx phy1 phy_mode - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK (0x6000000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT (25U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PHY_MODE_SHIFT) - -/* - * TX_PHY1_REFCLK_DIV (RW) - * - * tx phy1 refclk_div - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK (0xF00000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT (20U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_REFCLK_DIV_SHIFT) - -/* - * TX_PHY1_IDDQ_EN (RW) - * - * tx phy1 iddq_en - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK (0x80000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT (19U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_IDDQ_EN_SHIFT) - -/* - * TX_PHY1_RESET_N (RW) - * - * tx phy1 reset, active low - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK (0x40000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT (18U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_RESET_N_SHIFT) - -/* - * TX_PHY1_SHUTDOWNZ (RW) - * - * tx phy1 shutdownz, active low - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK (0x20000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT (17U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_SHUTDOWNZ_SHIFT) - -/* - * TX_PHY1_BYPS_CKDET (RW) - * - * tx phy1 byps_ckdet - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK (0x10000UL) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT (16U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_BYPS_CKDET_SHIFT) - -/* - * TX_PHY1_PLL_DIV (RW) - * - * tx phy1 pll_div - */ -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK (0x7FFFU) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT (0U) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) -#define PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_MASK) >> PIXELMUX_GPR_WR_D5_TX_PHY1_PLL_DIV_SHIFT) - -/* Bitfield definition for register: GPR_WR_D6 */ -/* - * TX_PHY1_PLL_CTRL (RW) - * - * tx phy1 pll_ctrl - */ -#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK (0xFFFFFFFFUL) -#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT (0U) -#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) -#define PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_MASK) >> PIXELMUX_GPR_WR_D6_TX_PHY1_PLL_CTRL_SHIFT) - -/* Bitfield definition for register: GPR_WR_D7 */ -/* - * TX_PHY1_TXCK_BIST_EN (RW) - * - * tx phy1 txck_bist_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK (0x80000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT (31U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_BIST_EN_SHIFT) - -/* - * TX_PHY1_TX3_BIST_EN (RW) - * - * tx phy1 tx3_bist_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK (0x40000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT (30U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_BIST_EN_SHIFT) - -/* - * TX_PHY1_TX2_BIST_EN (RW) - * - * tx phy1 tx2_bist_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK (0x20000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT (29U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_BIST_EN_SHIFT) - -/* - * TX_PHY1_TX1_BIST_EN (RW) - * - * tx phy1 tx1_bist_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK (0x10000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT (28U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_BIST_EN_SHIFT) - -/* - * TX_PHY1_TX0_BIST_EN (RW) - * - * tx phy1 tx0_bist_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK (0x8000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT (27U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_BIST_EN_SHIFT) - -/* - * TX_PHY1_TXCK_LPBK_EN (RW) - * - * tx_phy1 txck_lpbk_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK (0x4000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT (26U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_LPBK_EN_SHIFT) - -/* - * TX_PHY1_TX3_LPBK_EN (RW) - * - * tx_phy1 tx3_lpbk_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK (0x2000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT (25U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_LPBK_EN_SHIFT) - -/* - * TX_PHY1_TX2_LPBK_EN (RW) - * - * tx_phy1 tx2_lpbk_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK (0x1000000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT (24U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_LPBK_EN_SHIFT) - -/* - * TX_PHY1_TX1_LPBK_EN (RW) - * - * tx_phy1 tx1_lpbk_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK (0x800000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT (23U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_LPBK_EN_SHIFT) - -/* - * TX_PHY1_TX0_LPBK_EN (RW) - * - * tx_phy1 tx0_lpbk_en - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK (0x400000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT (22U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_LPBK_EN_SHIFT) - -/* - * TX_PHY1_TXCK_PAT_SEL (RW) - * - * tx phy1 txck_pat_sel - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK (0x300000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT (20U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TXCK_PAT_SEL_SHIFT) - -/* - * TX_PHY1_TX3_PAT_SEL (RW) - * - * tx phy1 tx3_pat_sel - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK (0xC0000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT (18U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX3_PAT_SEL_SHIFT) - -/* - * TX_PHY1_TX2_PAT_SEL (RW) - * - * tx phy1 tx2_pat_sel - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK (0x30000UL) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT (16U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX2_PAT_SEL_SHIFT) - -/* - * TX_PHY1_TX1_PAT_SEL (RW) - * - * tx phy1 tx1_pat_sel - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK (0xC000U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT (14U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX1_PAT_SEL_SHIFT) - -/* - * TX_PHY1_TX0_PAT_SEL (RW) - * - * tx phy1 tx0_pat_sel - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK (0x3000U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT (12U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_TX0_PAT_SEL_SHIFT) - -/* - * TX_PHY1_DSI0_PRBS_DISABLE (RW) - * - * tx phy1 dsi0_prbs_disable - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK (0x800U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT (11U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_DISABLE_SHIFT) - -/* - * TX_PHY1_DSI0_PRBS_START (RW) - * - * tx phy1 dsi0_prbs_start - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK (0x400U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT (10U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_DSI0_PRBS_START_SHIFT) - -/* - * TX_PHY1_CKPHY_CTL (RW) - * - * tx phy1 ckphy_ctl - */ -#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK (0x1FFU) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT (0U) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) -#define PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_MASK) >> PIXELMUX_GPR_WR_D7_TX_PHY1_CKPHY_CTL_SHIFT) - -/* Bitfield definition for register: GPR_WR_D8 */ -/* - * RX_PHY0_BRUN_IN_MODE (RW) - * - * rx phy0 burn_in_mode - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK (0x80000000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT (31U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BRUN_IN_MODE_SHIFT) - -/* - * RX_PHY0_BURN_IN_EN_PAD (RW) - * - * rx phy0 burn_in_en_pad - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK (0x40000000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT (30U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BURN_IN_EN_PAD_SHIFT) - -/* - * RX_PHY0_LPBK_MODE (RW) - * - * rx phy0 lpbk_mode - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK (0x30000000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT (28U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_LPBK_MODE_SHIFT) - -/* - * RX_PHY0_BIST_FREQ_TRIM (RW) - * - * rx phy0 bist_freq_trim - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK (0xF000000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT (24U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_FREQ_TRIM_SHIFT) - -/* - * RX_PHY0_RX0_BIST_EN (RW) - * - * rx phy0 rx0_bist_en rx1_bist_en - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK (0x400000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT (22U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_RX0_BIST_EN_SHIFT) - -/* - * RX_PHY0_BIST_MODE (RW) - * - * rx phy0 bist_mode - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK (0x200000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT (21U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_MODE_SHIFT) - -/* - * RX_PHY0_BIST_EN_PAD (RW) - * - * rx phy0 bist_en_pad - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK (0x100000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT (20U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_PAD_SHIFT) - -/* - * RX_PHY0_BIST_EN (RW) - * - * rx phy0 bist_en - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK (0x80000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT (19U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_EN_SHIFT) - -/* - * RX_PHY0_BIST_CKIN_SEL (RW) - * - * rx phy0 bist_ckin_sel - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK (0x40000UL) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT (18U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_BIST_CKIN_SEL_SHIFT) - -/* - * RX_PHY0_PHY_MODE (RW) - * - * rx phy0 phy_mode - */ -#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK (0x3U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT (0U) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) -#define PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D8_RX_PHY0_PHY_MODE_SHIFT) - -/* Bitfield definition for register: GPR_WR_D9 */ -/* - * RX_PHY1_BRUN_IN_MODE (RW) - * - * rx phy1 burn_in_mode - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK (0x80000000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT (31U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BRUN_IN_MODE_SHIFT) - -/* - * RX_PHY1_BURN_IN_EN_PAD (RW) - * - * rx phy1 burn_in_en_pad - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK (0x40000000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT (30U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BURN_IN_EN_PAD_SHIFT) - -/* - * RX_PHY1_LPBK_MODE (RW) - * - * rx phy1 lpbk_mode - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK (0x30000000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT (28U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_LPBK_MODE_SHIFT) - -/* - * RX_PHY1_BIST_FREQ_TRIM (RW) - * - * rx phy1 bist_freq_trim - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK (0xF000000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT (24U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_FREQ_TRIM_SHIFT) - -/* - * RX_PHY1_RX0_BIST_EN (RW) - * - * rx phy1 rx0_bist_en rx1_bist_en - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK (0x400000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT (22U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_RX0_BIST_EN_SHIFT) - -/* - * RX_PHY1_BIST_MODE (RW) - * - * rx phy1 bist_mode - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK (0x200000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT (21U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_MODE_SHIFT) - -/* - * RX_PHY1_BIST_EN_PAD (RW) - * - * rx phy1 bist_en_pad - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK (0x100000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT (20U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_PAD_SHIFT) - -/* - * RX_PHY1_BIST_EN (RW) - * - * rx phy1 bist_en - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK (0x80000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT (19U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_EN_SHIFT) - -/* - * RX_PHY1_BIST_CKIN_SEL (RW) - * - * rx phy1 bist_ckin_sel - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK (0x40000UL) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT (18U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_BIST_CKIN_SEL_SHIFT) - -/* - * RX_PHY1_PHY_MODE (RW) - * - * rx phy1 phy_mode - */ -#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK (0x3U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT (0U) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) -#define PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_MASK) >> PIXELMUX_GPR_WR_D9_RX_PHY1_PHY_MODE_SHIFT) - -/* Bitfield definition for register: GPR_RO_D0 */ -/* - * TX_PHY1_CTL_O (RO) - * - * {2'b0, - * tx_phy1_tx3_ctl_o,tx_phy1_tx2_ctl_o, - * tx_phy1_tx1_ctl_o,tx_phy1_tx0_ctl_o, - * tx_phy1_txck_ctl_o,tx_phy1_pll_dtest_o} - */ -#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK (0xFF00U) -#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT (8U) -#define PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY1_CTL_O_SHIFT) - -/* - * TX_PHY0_CTL_O (RO) - * - * {2'b0, - * tx_phy0_tx3_ctl_o,tx_phy0_tx2_ctl_o, - * tx_phy0_tx1_ctl_o,tx_phy0_tx0_ctl_o, - * tx_phy0_txck_ctl_o,tx_phy0_pll_dtest_o} - */ -#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK (0xFFU) -#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT (0U) -#define PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_MASK) >> PIXELMUX_GPR_RO_D0_TX_PHY0_CTL_O_SHIFT) - -/* Bitfield definition for register: GPR_RO_D1 */ -/* - * IRQ_CSI0_AP (RO) - * - * interrupt of csi0 ap - */ -#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK (0x20000UL) -#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT (17U) -#define PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_MASK) >> PIXELMUX_GPR_RO_D1_IRQ_CSI0_AP_SHIFT) - -/* - * CSI0_CFG_CSI_AP_DIAG_FAULTS (RO) - * - * csi0 ap diag faults - */ -#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL) -#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U) -#define PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_CFG_CSI_AP_DIAG_FAULTS_SHIFT) - -/* - * CSI0_STA_AP_IF_INT_STA (RO) - * - * csi0 apb parity check interrupt satus - */ -#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK (0x1FU) -#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT (0U) -#define PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D1_CSI0_STA_AP_IF_INT_STA_SHIFT) - -/* Bitfield definition for register: GPR_RO_D2 */ -/* - * IRQ_CSI1_AP (RO) - * - * interrupt of csi1 ap - */ -#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK (0x20000UL) -#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT (17U) -#define PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_MASK) >> PIXELMUX_GPR_RO_D2_IRQ_CSI1_AP_SHIFT) - -/* - * CSI1_CFG_CSI_AP_DIAG_FAULTS (RO) - * - * csi1 ap diag faults - */ -#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK (0x1FFE0UL) -#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT (5U) -#define PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_CFG_CSI_AP_DIAG_FAULTS_SHIFT) - -/* - * CSI1_STA_AP_IF_INT_STA (RO) - * - * csi1 apb parity check interrupt satus - */ -#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK (0x1FU) -#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT (0U) -#define PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_MASK) >> PIXELMUX_GPR_RO_D2_CSI1_STA_AP_IF_INT_STA_SHIFT) - -/* Bitfield definition for register: GPR_RO_D3 */ -/* - * RX_PHY0_RXCK_CTLO (RO) - * - * rx phy0 rxck_ctlo - */ -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK (0xFF00U) -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT (8U) -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RXCK_CTLO_SHIFT) - -/* - * RX_PHY0_RX1_CTLO (RO) - * - * rx phy0 rx1_ctlo - */ -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK (0xF0U) -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT (4U) -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX1_CTLO_SHIFT) - -/* - * RX_PHY0_RX0_CTLO (RO) - * - * rx phy0 rx0_ctlo - */ -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK (0xFU) -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT (0U) -#define PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D3_RX_PHY0_RX0_CTLO_SHIFT) - -/* Bitfield definition for register: GPR_RO_D4 */ -/* - * RX_PHY1_RXCK_CTLO (RO) - * - * rx phy1 rxck_ctlo - */ -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK (0xFF00U) -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT (8U) -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RXCK_CTLO_SHIFT) - -/* - * RX_PHY1_RX1_CTLO (RO) - * - * rx phy1 rx1_ctlo - */ -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK (0xF0U) -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT (4U) -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX1_CTLO_SHIFT) - -/* - * RX_PHY1_RX0_CTLO (RO) - * - * rx phy1 rx0_ctlo - */ -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK (0xFU) -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT (0U) -#define PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_MASK) >> PIXELMUX_GPR_RO_D4_RX_PHY1_RX0_CTLO_SHIFT) - -/* Bitfield definition for register: GPR_RO_D5 */ -/* - * DSI0_PRBS_STATE (RO) - * - * dsi0_prbs_state for debug only - */ -#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK (0xF000U) -#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT (12U) -#define PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D5_DSI0_PRBS_STATE_SHIFT) - -/* - * TX_PHY0_TXCK_BIST_DONE_PAD (RO) - * - * tx phy0 txck_done_pad - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK (0x800U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT (11U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_PAD_SHIFT) - -/* - * TX_PHY0_TXCK_BIST_OK_PAD (RO) - * - * tx phy0 txck_ok_pad - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK (0x400U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT (10U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OK_PAD_SHIFT) - -/* - * TX_PHY0_TXCK_BIST_DONE (RO) - * - * tx phy0 txck_bist_done - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK (0x200U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT (9U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_DONE_SHIFT) - -/* - * TX_PHY0_TX3_BIST_DONE (RO) - * - * tx phy0 tx3_bist_done - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK (0x100U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT (8U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_DONE_SHIFT) - -/* - * TX_PHY0_TX2_BIST_DONE (RO) - * - * tx phy0 tx2_bist_done - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK (0x80U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT (7U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_DONE_SHIFT) - -/* - * TX_PHY0_TX1_BIST_DONE (RO) - * - * tx phy0 tx1_bist_done - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK (0x40U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT (6U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_DONE_SHIFT) - -/* - * TX_PHY0_TX0_BIST_DONE (RO) - * - * tx phy0 tx0_bist_done - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK (0x20U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT (5U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_DONE_SHIFT) - -/* - * TX_PHY0_TXCK_BIST_OUT (RO) - * - * tx phy0 txck_bist_out - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK (0x10U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT (4U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TXCK_BIST_OUT_SHIFT) - -/* - * TX_PHY0_TX3_BIST_OUT (RO) - * - * tx phy0 tx3_bist_out - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK (0x8U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT (3U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX3_BIST_OUT_SHIFT) - -/* - * TX_PHY0_TX2_BIST_OUT (RO) - * - * tx phy0 tx2_bist_out - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK (0x4U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT (2U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX2_BIST_OUT_SHIFT) - -/* - * TX_PHY0_TX1_BIST_OUT (RO) - * - * tx phy0 tx1_bist_out - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK (0x2U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT (1U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX1_BIST_OUT_SHIFT) - -/* - * TX_PHY0_TX0_BIST_OUT (RO) - * - * tx phy0 tx0_bist_out - */ -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK (0x1U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT (0U) -#define PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D5_TX_PHY0_TX0_BIST_OUT_SHIFT) - -/* Bitfield definition for register: GPR_RO_D6 */ -/* - * DSI1_PRBS_STATE (RO) - * - * dsi1_prbs_state for debug only - */ -#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK (0xF000U) -#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT (12U) -#define PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_MASK) >> PIXELMUX_GPR_RO_D6_DSI1_PRBS_STATE_SHIFT) - -/* - * TX_PHY1_TXCK_BIST_DONE_PAD (RO) - * - * tx phy1 txck_done_pad - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK (0x800U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT (11U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_PAD_SHIFT) - -/* - * TX_PHY1_TXCK_BIST_OK_PAD (RO) - * - * tx phy1 txck_ok_pad - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK (0x400U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT (10U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OK_PAD_SHIFT) - -/* - * TX_PHY1_TXCK_BIST_DONE (RO) - * - * tx phy1 txck_bist_done - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK (0x200U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT (9U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_DONE_SHIFT) - -/* - * TX_PHY1_TX3_BIST_DONE (RO) - * - * tx phy1 tx3_bist_done - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK (0x100U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT (8U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_DONE_SHIFT) - -/* - * TX_PHY1_TX2_BIST_DONE (RO) - * - * tx phy1 tx2_bist_done - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK (0x80U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT (7U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_DONE_SHIFT) - -/* - * TX_PHY1_TX1_BIST_DONE (RO) - * - * tx phy1 tx1_bist_done - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK (0x40U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT (6U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_DONE_SHIFT) - -/* - * TX_PHY1_TX0_BIST_DONE (RO) - * - * tx phy1 tx0_bist_done - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK (0x20U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT (5U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_DONE_SHIFT) - -/* - * TX_PHY1_TXCK_BIST_OUT (RO) - * - * tx phy1 txck_bist_out - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK (0x10U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT (4U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TXCK_BIST_OUT_SHIFT) - -/* - * TX_PHY1_TX3_BIST_OUT (RO) - * - * tx phy1 tx3_bist_out - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK (0x8U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT (3U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX3_BIST_OUT_SHIFT) - -/* - * TX_PHY1_TX2_BIST_OUT (RO) - * - * tx phy1 tx2_bist_out - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK (0x4U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT (2U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX2_BIST_OUT_SHIFT) - -/* - * TX_PHY1_TX1_BIST_OUT (RO) - * - * tx phy1 tx1_bist_out - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK (0x2U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT (1U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX1_BIST_OUT_SHIFT) - -/* - * TX_PHY1_TX0_BIST_OUT (RO) - * - * tx phy1 tx0_bist_out - */ -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK (0x1U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT (0U) -#define PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D6_TX_PHY1_TX0_BIST_OUT_SHIFT) - -/* Bitfield definition for register: GPR_RO_D7 */ -/* - * RX_PHY0_BURN_IN_OK_PAD (RO) - * - * rx_phy0_burn_in_ok_pad - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK (0x40U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT (6U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BURN_IN_OK_PAD_SHIFT) - -/* - * RX_PHY0_RX1_BIST_DONE (RO) - * - * rx phy0 rx1_bist_done - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK (0x20U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT (5U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_DONE_SHIFT) - -/* - * RX_PHY0_RX0_BIST_DONE (RO) - * - * rx phy0 rx0_bist_done - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK (0x10U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT (4U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_DONE_SHIFT) - -/* - * RX_PHY0_RX1_BIST_OUT (RO) - * - * rx phy0 rx1_bist_out - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK (0x8U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT (3U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX1_BIST_OUT_SHIFT) - -/* - * RX_PHY0_RX0_BIST_OUT (RO) - * - * rx phy0 rx0_bist_out - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK (0x4U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT (2U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_RX0_BIST_OUT_SHIFT) - -/* - * RX_PHY0_BIST_OK_PAD (RO) - * - * rx phy0 bist_ok_pad - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK (0x2U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT (1U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_OK_PAD_SHIFT) - -/* - * RX_PHY0_BIST_DONE_PAD (RO) - * - * rx phy0 bist_done_pad - */ -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK (0x1U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT (0U) -#define PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D7_RX_PHY0_BIST_DONE_PAD_SHIFT) - -/* Bitfield definition for register: GPR_RO_D8 */ -/* - * RX_PHY1_BURN_IN_OK_PAD (RO) - * - * rx_phy1_burn_in_ok_pad - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK (0x40U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT (6U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BURN_IN_OK_PAD_SHIFT) - -/* - * RX_PHY1_RX1_BIST_DONE (RO) - * - * rx phy1 rx1_bist_done - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK (0x20U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT (5U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_DONE_SHIFT) - -/* - * RX_PHY1_RX0_BIST_DONE (RO) - * - * rx phy1 rx0_bist_done - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK (0x10U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT (4U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_DONE_SHIFT) - -/* - * RX_PHY1_RX1_BIST_OUT (RO) - * - * rx phy1 rx1_bist_out - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK (0x8U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT (3U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX1_BIST_OUT_SHIFT) - -/* - * RX_PHY1_RX0_BIST_OUT (RO) - * - * rx phy1 rx0_bist_out - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK (0x4U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT (2U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_RX0_BIST_OUT_SHIFT) - -/* - * RX_PHY1_BIST_OK_PAD (RO) - * - * rx phy1 bist_ok_pad - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK (0x2U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT (1U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_OK_PAD_SHIFT) - -/* - * RX_PHY1_BIST_DONE_PAD (RO) - * - * rx phy1 bist_done_pad - */ -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK (0x1U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT (0U) -#define PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_MASK) >> PIXELMUX_GPR_RO_D8_RX_PHY1_BIST_DONE_PAD_SHIFT) - -/* Bitfield definition for register: GPR_RO_D9 */ -/* Bitfield definition for register: GPR_WR1_CLR_D0 */ -/* - * GPR_WR1_CLR_DATA (RW) - * - * gpr register, write 1 /no-write set/clr matching bit - */ -#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK (0xFFFFFFFFUL) -#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT (0U) -#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SET(x) (((uint32_t)(x) << PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) -#define PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_GET(x) (((uint32_t)(x) & PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_MASK) >> PIXELMUX_GPR_WR1_CLR_D0_GPR_WR1_CLR_DATA_SHIFT) - - - -/* DSI_SETTING register group index macro definition */ -#define PIXELMUX_DSI_SETTING_DSI0_CFG (0UL) -#define PIXELMUX_DSI_SETTING_DSI1_CFG (1UL) - - -#endif /* HPM_PIXELMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_plic_regs.h deleted file mode 100644 index eb5a6504d9c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_plic_regs.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_H -#define HPM_PLIC_H - -typedef struct { - __RW uint32_t FEATURE; /* 0x0: Feature enable register */ - __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ - __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ - __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ - __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ - __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ - __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ - __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ - __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ - __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ - struct { - __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ - __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ - } TARGETINT[2]; - __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */ - struct { - __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ - __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ - __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ - __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ - __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ - } TARGETCONFIG[2]; -} PLIC_Type; - - -/* Bitfield definition for register: FEATURE */ -/* - * VECTORED (RW) - * - * Vector mode enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_VECTORED_MASK (0x2U) -#define PLIC_FEATURE_VECTORED_SHIFT (1U) -#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) -#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) - -/* - * PREEMPT (RW) - * - * Preemptive priority interrupt enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_PREEMPT_MASK (0x1U) -#define PLIC_FEATURE_PREEMPT_SHIFT (0U) -#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) -#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) - -/* Bitfield definition for register array: PRIORITY */ -/* - * PRIORITY (RW) - * - * Interrupt source priority. The valid range of this field is 0-7. - * 0: Never interrupt - * 1-7: Interrupt source priority. The larger the value, the higher the priority. - */ -#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) -#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) -#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) -#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) - -/* Bitfield definition for register array: PENDING */ -/* - * INTERRUPT (RW) - * - * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - */ -#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_PENDING_INTERRUPT_SHIFT (0U) -#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) -#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register array: TRIGGER */ -/* - * INTERRUPT (RO) - * - * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. - * 0: Level-triggered interrupt - * 1: Edge-triggered interrupt - */ -#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) -#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) - -/* Bitfield definition for register: NUMBER */ -/* - * NUM_TARGET (RO) - * - * The number of supported targets - */ -#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) -#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) -#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) - -/* - * NUM_INTERRUPT (RO) - * - * The number of supported interrupt sources - */ -#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) -#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) -#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INFO */ -/* - * MAX_PRIORITY (RO) - * - * The maximum priority supported - */ -#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) -#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) -#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) - -/* - * VERSION (RO) - * - * The version of the PLIC design - */ -#define PLIC_INFO_VERSION_MASK (0xFFFFU) -#define PLIC_INFO_VERSION_SHIFT (0U) -#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) - -/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ -/* - * INTERRUPT (RW) - * - * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - */ -#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) -#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ -/* - * THRESHOLD (RW) - * - * Interrupt priority threshold. - */ -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ -/* - * PRIORITY_PREEMPTED (RW) - * - * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - */ -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) - - - -/* PRIORITY register group index macro definition */ -#define PLIC_PRIORITY_PRIORITY1 (0UL) -#define PLIC_PRIORITY_PRIORITY2 (1UL) -#define PLIC_PRIORITY_PRIORITY3 (2UL) -#define PLIC_PRIORITY_PRIORITY4 (3UL) -#define PLIC_PRIORITY_PRIORITY5 (4UL) -#define PLIC_PRIORITY_PRIORITY6 (5UL) -#define PLIC_PRIORITY_PRIORITY7 (6UL) -#define PLIC_PRIORITY_PRIORITY8 (7UL) -#define PLIC_PRIORITY_PRIORITY9 (8UL) -#define PLIC_PRIORITY_PRIORITY10 (9UL) -#define PLIC_PRIORITY_PRIORITY11 (10UL) -#define PLIC_PRIORITY_PRIORITY12 (11UL) -#define PLIC_PRIORITY_PRIORITY13 (12UL) -#define PLIC_PRIORITY_PRIORITY14 (13UL) -#define PLIC_PRIORITY_PRIORITY15 (14UL) -#define PLIC_PRIORITY_PRIORITY16 (15UL) -#define PLIC_PRIORITY_PRIORITY17 (16UL) -#define PLIC_PRIORITY_PRIORITY18 (17UL) -#define PLIC_PRIORITY_PRIORITY19 (18UL) -#define PLIC_PRIORITY_PRIORITY20 (19UL) -#define PLIC_PRIORITY_PRIORITY21 (20UL) -#define PLIC_PRIORITY_PRIORITY22 (21UL) -#define PLIC_PRIORITY_PRIORITY23 (22UL) -#define PLIC_PRIORITY_PRIORITY24 (23UL) -#define PLIC_PRIORITY_PRIORITY25 (24UL) -#define PLIC_PRIORITY_PRIORITY26 (25UL) -#define PLIC_PRIORITY_PRIORITY27 (26UL) -#define PLIC_PRIORITY_PRIORITY28 (27UL) -#define PLIC_PRIORITY_PRIORITY29 (28UL) -#define PLIC_PRIORITY_PRIORITY30 (29UL) -#define PLIC_PRIORITY_PRIORITY31 (30UL) -#define PLIC_PRIORITY_PRIORITY32 (31UL) -#define PLIC_PRIORITY_PRIORITY33 (32UL) -#define PLIC_PRIORITY_PRIORITY34 (33UL) -#define PLIC_PRIORITY_PRIORITY35 (34UL) -#define PLIC_PRIORITY_PRIORITY36 (35UL) -#define PLIC_PRIORITY_PRIORITY37 (36UL) -#define PLIC_PRIORITY_PRIORITY38 (37UL) -#define PLIC_PRIORITY_PRIORITY39 (38UL) -#define PLIC_PRIORITY_PRIORITY40 (39UL) -#define PLIC_PRIORITY_PRIORITY41 (40UL) -#define PLIC_PRIORITY_PRIORITY42 (41UL) -#define PLIC_PRIORITY_PRIORITY43 (42UL) -#define PLIC_PRIORITY_PRIORITY44 (43UL) -#define PLIC_PRIORITY_PRIORITY45 (44UL) -#define PLIC_PRIORITY_PRIORITY46 (45UL) -#define PLIC_PRIORITY_PRIORITY47 (46UL) -#define PLIC_PRIORITY_PRIORITY48 (47UL) -#define PLIC_PRIORITY_PRIORITY49 (48UL) -#define PLIC_PRIORITY_PRIORITY50 (49UL) -#define PLIC_PRIORITY_PRIORITY51 (50UL) -#define PLIC_PRIORITY_PRIORITY52 (51UL) -#define PLIC_PRIORITY_PRIORITY53 (52UL) -#define PLIC_PRIORITY_PRIORITY54 (53UL) -#define PLIC_PRIORITY_PRIORITY55 (54UL) -#define PLIC_PRIORITY_PRIORITY56 (55UL) -#define PLIC_PRIORITY_PRIORITY57 (56UL) -#define PLIC_PRIORITY_PRIORITY58 (57UL) -#define PLIC_PRIORITY_PRIORITY59 (58UL) -#define PLIC_PRIORITY_PRIORITY60 (59UL) -#define PLIC_PRIORITY_PRIORITY61 (60UL) -#define PLIC_PRIORITY_PRIORITY62 (61UL) -#define PLIC_PRIORITY_PRIORITY63 (62UL) -#define PLIC_PRIORITY_PRIORITY64 (63UL) -#define PLIC_PRIORITY_PRIORITY65 (64UL) -#define PLIC_PRIORITY_PRIORITY66 (65UL) -#define PLIC_PRIORITY_PRIORITY67 (66UL) -#define PLIC_PRIORITY_PRIORITY68 (67UL) -#define PLIC_PRIORITY_PRIORITY69 (68UL) -#define PLIC_PRIORITY_PRIORITY70 (69UL) -#define PLIC_PRIORITY_PRIORITY71 (70UL) -#define PLIC_PRIORITY_PRIORITY72 (71UL) -#define PLIC_PRIORITY_PRIORITY73 (72UL) -#define PLIC_PRIORITY_PRIORITY74 (73UL) -#define PLIC_PRIORITY_PRIORITY75 (74UL) -#define PLIC_PRIORITY_PRIORITY76 (75UL) -#define PLIC_PRIORITY_PRIORITY77 (76UL) -#define PLIC_PRIORITY_PRIORITY78 (77UL) -#define PLIC_PRIORITY_PRIORITY79 (78UL) -#define PLIC_PRIORITY_PRIORITY80 (79UL) -#define PLIC_PRIORITY_PRIORITY81 (80UL) -#define PLIC_PRIORITY_PRIORITY82 (81UL) -#define PLIC_PRIORITY_PRIORITY83 (82UL) -#define PLIC_PRIORITY_PRIORITY84 (83UL) -#define PLIC_PRIORITY_PRIORITY85 (84UL) -#define PLIC_PRIORITY_PRIORITY86 (85UL) -#define PLIC_PRIORITY_PRIORITY87 (86UL) -#define PLIC_PRIORITY_PRIORITY88 (87UL) -#define PLIC_PRIORITY_PRIORITY89 (88UL) -#define PLIC_PRIORITY_PRIORITY90 (89UL) -#define PLIC_PRIORITY_PRIORITY91 (90UL) -#define PLIC_PRIORITY_PRIORITY92 (91UL) -#define PLIC_PRIORITY_PRIORITY93 (92UL) -#define PLIC_PRIORITY_PRIORITY94 (93UL) -#define PLIC_PRIORITY_PRIORITY95 (94UL) -#define PLIC_PRIORITY_PRIORITY96 (95UL) -#define PLIC_PRIORITY_PRIORITY97 (96UL) -#define PLIC_PRIORITY_PRIORITY98 (97UL) -#define PLIC_PRIORITY_PRIORITY99 (98UL) -#define PLIC_PRIORITY_PRIORITY100 (99UL) -#define PLIC_PRIORITY_PRIORITY101 (100UL) -#define PLIC_PRIORITY_PRIORITY102 (101UL) -#define PLIC_PRIORITY_PRIORITY103 (102UL) -#define PLIC_PRIORITY_PRIORITY104 (103UL) -#define PLIC_PRIORITY_PRIORITY105 (104UL) -#define PLIC_PRIORITY_PRIORITY106 (105UL) -#define PLIC_PRIORITY_PRIORITY107 (106UL) -#define PLIC_PRIORITY_PRIORITY108 (107UL) -#define PLIC_PRIORITY_PRIORITY109 (108UL) -#define PLIC_PRIORITY_PRIORITY110 (109UL) -#define PLIC_PRIORITY_PRIORITY111 (110UL) -#define PLIC_PRIORITY_PRIORITY112 (111UL) -#define PLIC_PRIORITY_PRIORITY113 (112UL) -#define PLIC_PRIORITY_PRIORITY114 (113UL) -#define PLIC_PRIORITY_PRIORITY115 (114UL) -#define PLIC_PRIORITY_PRIORITY116 (115UL) -#define PLIC_PRIORITY_PRIORITY117 (116UL) -#define PLIC_PRIORITY_PRIORITY118 (117UL) -#define PLIC_PRIORITY_PRIORITY119 (118UL) -#define PLIC_PRIORITY_PRIORITY120 (119UL) -#define PLIC_PRIORITY_PRIORITY121 (120UL) -#define PLIC_PRIORITY_PRIORITY122 (121UL) -#define PLIC_PRIORITY_PRIORITY123 (122UL) -#define PLIC_PRIORITY_PRIORITY124 (123UL) -#define PLIC_PRIORITY_PRIORITY125 (124UL) -#define PLIC_PRIORITY_PRIORITY126 (125UL) -#define PLIC_PRIORITY_PRIORITY127 (126UL) - -/* PENDING register group index macro definition */ -#define PLIC_PENDING_PENDING0 (0UL) -#define PLIC_PENDING_PENDING1 (1UL) -#define PLIC_PENDING_PENDING2 (2UL) -#define PLIC_PENDING_PENDING3 (3UL) - -/* TRIGGER register group index macro definition */ -#define PLIC_TRIGGER_TRIGGER0 (0UL) -#define PLIC_TRIGGER_TRIGGER1 (1UL) -#define PLIC_TRIGGER_TRIGGER2 (2UL) -#define PLIC_TRIGGER_TRIGGER3 (3UL) - -/* INTEN register group index macro definition */ -#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) -#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) -#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) -#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) - -/* TARGETINT register group index macro definition */ -#define PLIC_TARGETINT_TARGET0 (0UL) -#define PLIC_TARGETINT_TARGET1 (1UL) - -/* TARGETCONFIG register group index macro definition */ -#define PLIC_TARGETCONFIG_TARGET0 (0UL) -#define PLIC_TARGETCONFIG_TARGET1 (1UL) - - -#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_plic_sw_regs.h deleted file mode 100644 index 998dafa2d57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_plic_sw_regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_SW_H -#define HPM_PLIC_SW_H - -typedef struct { - __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ - __RW uint32_t PENDING; /* 0x1000: Pending status */ - __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ - __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ - __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ - __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ -} PLIC_SW_Type; - - -/* Bitfield definition for register: PENDING */ -/* - * INTERRUPT (RW) - * - * writing 1 to trigger software interrupt - */ -#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) -#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) -#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) -#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * INTERRUPT (RW) - * - * enable software interrupt - */ -#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) -#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) -#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) - - - - -#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pllctlv2_regs.h deleted file mode 100644 index 074fb9549fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_pllctlv2_regs.h +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLLCTLV2_H -#define HPM_PLLCTLV2_H - -typedef struct { - __RW uint32_t XTAL; /* 0x0: OSC configuration */ - __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ - struct { - __RW uint32_t MFI; /* 0x80: PLL0 multiple register */ - __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */ - __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */ - __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */ - __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */ - __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */ - __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */ - __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */ - __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */ - __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ - __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ - __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ - } PLL[5]; -} PLLCTLV2_Type; - - -/* Bitfield definition for register: XTAL */ -/* - * BUSY (RO) - * - * Busy flag - * 0: Oscillator is working or shutdown - * 1: Oscillator is changing status - */ -#define PLLCTLV2_XTAL_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_XTAL_BUSY_SHIFT (31U) -#define PLLCTLV2_XTAL_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTLV2_XTAL_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_XTAL_RESPONSE_SHIFT (29U) -#define PLLCTLV2_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTLV2_XTAL_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_XTAL_ENABLE_SHIFT (28U) -#define PLLCTLV2_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT) - -/* - * RAMP_TIME (RW) - * - * Rampup time of XTAL oscillator in cycles of RC24M clock - * 0: 0 cycle - * 1: 1 cycle - * 2: 2 cycle - * 1048575: 1048575 cycles - */ -#define PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) -#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) -#define PLLCTLV2_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK) -#define PLLCTLV2_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFI */ -/* - * BUSY (RO) - * - * Busy flag - * 0: PLL is stable or shutdown - * 1: PLL is changing status - */ -#define PLLCTLV2_PLL_MFI_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_MFI_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_MFI_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * PLL status - * 0: PLL is not stable - * 1: PLL is stable for use - */ -#define PLLCTLV2_PLL_MFI_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_MFI_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * PLL enable status - * 0: PLL is off - * 1: PLL is on - */ -#define PLLCTLV2_PLL_MFI_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_MFI_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT) - -/* - * MFI (RW) - * - * loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) - * 0-15: invalid - * 16: divide by 16 - * 17: divide by17 - * . . . - * 42: divide by 42 - * 43~:invalid - */ -#define PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) -#define PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) -#define PLLCTLV2_PLL_MFI_MFI_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK) -#define PLLCTLV2_PLL_MFI_MFI_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFN */ -/* - * MFN (RW) - * - * Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - */ -#define PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) -#define PLLCTLV2_PLL_MFN_MFN_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK) -#define PLLCTLV2_PLL_MFN_MFN_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFD */ -/* - * MFD (RW) - * - * Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - */ -#define PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) -#define PLLCTLV2_PLL_MFD_MFD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK) -#define PLLCTLV2_PLL_MFD_MFD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STEP */ -/* - * STEP (RW) - * - * Step of spread spectrum modulator. - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STEP_STEP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) -#define PLLCTLV2_PLL_SS_STEP_STEP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STOP */ -/* - * STOP (RW) - * - * Stop point of spread spectrum modulator - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STOP_STOP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) -#define PLLCTLV2_PLL_SS_STOP_STOP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) - -/* Bitfield definition for register of struct array PLL: CONFIG */ -/* - * SPREAD (RW) - * - * Enable spread spectrum function. This field supports changing during PLL running. - */ -#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK (0x100U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT (8U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) -#define PLLCTLV2_PLL_CONFIG_SPREAD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) - -/* - * REFSEL (RW) - * - * Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. - * 0: XTAL24M - * 1: IRC24M - */ -#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK (0x1U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT (0U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) -#define PLLCTLV2_PLL_CONFIG_REFSEL_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) - -/* Bitfield definition for register of struct array PLL: LOCKTIME */ -/* - * LOCKTIME (RW) - * - * Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - */ -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: STEPTIME */ -/* - * STEPTIME (RW) - * - * Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - */ -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: ADVANCED */ -/* - * SLOW (RW) - * - * Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. - * 0: fast lock enabled, lock time is 100us - * 1: fast lock disabled, lock time is 400us - */ -#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK (0x10000000UL) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT (28U) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) -#define PLLCTLV2_PLL_ADVANCED_SLOW_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither function - */ -#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK (0x1000000UL) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT (24U) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) -#define PLLCTLV2_PLL_ADVANCED_DITHER_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV0 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTLV2_PLL_DIV_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_DIV_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Divider response status - * 0: Divider is not stable - * 1: Divider is stable for use - */ -#define PLLCTLV2_PLL_DIV_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Divider enable status - * 0: Divider is off - * 1: Divider is on - */ -#define PLLCTLV2_PLL_DIV_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider factor, divider factor is DIV/5 + 1 - * 0: divide by 1 - * 1: divide by 1.2 - * 2: divide by 1.4 - * . . . - * 63: divide by 13.6 - */ -#define PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) -#define PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) -#define PLLCTLV2_PLL_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK) -#define PLLCTLV2_PLL_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT) - - - -/* DIV register group index macro definition */ -#define PLLCTLV2_PLL_DIV_DIV0 (0UL) -#define PLLCTLV2_PLL_DIV_DIV1 (1UL) -#define PLLCTLV2_PLL_DIV_DIV2 (2UL) - -/* PLL register group index macro definition */ -#define PLLCTLV2_PLL_PLL0 (0UL) -#define PLLCTLV2_PLL_PLL1 (1UL) -#define PLLCTLV2_PLL_PLL2 (2UL) -#define PLLCTLV2_PLL_PLL3 (3UL) -#define PLLCTLV2_PLL_PLL4 (4UL) - - -#endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ppor_regs.h deleted file mode 100644 index 11181004dbd..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ppor_regs.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPOR_H -#define HPM_PPOR_H - -typedef struct { - __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ - __R uint32_t RESET_STATUS; /* 0x4: reset source status */ - __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ - __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ - __R uint8_t RESERVED0[12]; /* 0x10 - 0x1B: Reserved */ - __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ -} PPOR_Type; - - -/* Bitfield definition for register: RESET_FLAG */ -/* - * FLAG (W1C) - * - * reset reason of last hard reset, write 1 to clear each bit - * 0: brownout - * 1: temperature(not available) - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) -#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) -#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: RESET_STATUS */ -/* - * STATUS (RO) - * - * current status of reset sources - * 0: brownout - * 1: temperature(not available) - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) -#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_HOLD */ -/* - * HOLD (RW) - * - * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status - * 0: brownout - * 1: temperature(not available) - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) -#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) -#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) - -/* Bitfield definition for register: RESET_ENABLE */ -/* - * ENABLE (RW) - * - * enable of reset sources - * 0: brownout - * 1: temperature(not available) - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) -#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) -#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) - -/* Bitfield definition for register: SOFTWARE_RESET */ -/* - * COUNTER (RW) - * - * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - */ -#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) -#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) -#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) -#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) - - - - -#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ptpc_regs.h deleted file mode 100644 index 5d9609c0c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_ptpc_regs.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PTPC_H -#define HPM_PTPC_H - -typedef struct { - struct { - __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ - __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ - __R uint32_t TIMEH; /* 0x8: timestamp high */ - __R uint32_t TIMEL; /* 0xC: timestamp low */ - __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ - __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ - __RW uint32_t ADDEND; /* 0x18: */ - __RW uint32_t TARH; /* 0x1C: */ - __RW uint32_t TARL; /* 0x20: */ - __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ - __RW uint32_t PPS_CTRL; /* 0x2C: */ - __R uint32_t CAPT_SNAPH; /* 0x30: */ - __RW uint32_t CAPT_SNAPL; /* 0x34: */ - __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ - } PTPC[2]; - __RW uint32_t TIME_SEL; /* 0x2000: */ - __W uint32_t INT_STS; /* 0x2004: */ - __RW uint32_t INT_EN; /* 0x2008: */ - __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ - __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ -} PTPC_Type; - - -/* Bitfield definition for register of struct array PTPC: CTRL0 */ -/* - * SUBSEC_DIGITAL_ROLLOVER (RW) - * - * Format for ns counter rollover, - * 1-digital, overflow time 1000000000/0x3B9ACA00 - * 0-binary, overflow time 0x7FFFFFFF - */ -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) - -/* - * CAPT_SNAP_KEEP (RW) - * - * set will keep capture snap till software read capt_snapl. - * If this bit is set, software should read capt_snaph first to avoid wrong result. - * If this bit is cleared, capture result will be updated at each capture event - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) - -/* - * CAPT_SNAP_POS_EN (RW) - * - * set will use posege of input capture signal to latch timestamp value - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) - -/* - * CAPT_SNAP_NEG_EN (RW) - * - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - -/* - * COMP_EN (RW) - * - * set to enable compare, will be cleared by HW when compare event triggered - */ -#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) -#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) -#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) -#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) - -/* - * UPDATE_TIMER (WO) - * - * update timer with +/- ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) - -/* - * INIT_TIMER (WO) - * - * initial timer with ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) -#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) - -/* - * FINE_COARSE_SEL (RW) - * - * 0: coarse update, ns counter add ss_incr[7:0] each clk - * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - */ -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - */ -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CTRL1 */ -/* - * SS_INCR (RW) - * - * constant value used to add ns counter; - * such as for 50MHz timer clock, set it to 8'd20 - */ -#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) -#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) -#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) -#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEH */ -/* - * TIMESTAMP_HIGH (RO) - * - */ -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEL */ -/* - * TIMESTAMP_LOW (RO) - * - */ -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ -/* - * SEC_UPDATE (RW) - * - * together with ts_updtl, used to initial or update timestamp - */ -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ -/* - * ADD_SUB (RW) - * - * 1 for sub; 0 for add, used only at update - */ -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) - -/* - * NS_UPDATE (RW) - * - */ -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: ADDEND */ -/* - * ADDEND (RW) - * - * used in fine update mode only - */ -#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) -#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) -#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARH */ -/* - * TARGET_TIME_HIGH (RW) - * - * used for generate compare signal if enabled - */ -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARL */ -/* - * TARGET_TIME_LOW (RW) - * - */ -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ -/* - * PPS_CTRL (RW) - * - */ -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ -/* - * CAPT_SNAP_HIGH (RO) - * - * take snapshot for input capture signal, at pos or neg or both; - * the result can be kept or updated at each event according to cfg0.bit8 - */ -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ -/* - * CAPT_SNAP_LOW (RW) - * - */ -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) - -/* Bitfield definition for register: TIME_SEL */ -/* - * CAN3_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) - -/* - * CAN2_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) - -/* - * CAN1_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) - -/* - * CAN0_TIME_SEL (RW) - * - * set to use ptpc1 for canx - * clr to use ptpc0 for canx - */ -#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * COMP_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) -#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) -#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) -#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) -#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * COMP_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) -#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) -#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) -#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) -#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: PTPC_CAN_TS_SEL */ -/* - * TSU_TBIN3_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) - -/* - * TSU_TBIN2_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) - -/* - * TSU_TBIN1_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) - -/* - * TSU_TBIN0_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) - - - -/* PTPC register group index macro definition */ -#define PTPC_PTPC_0 (0UL) -#define PTPC_PTPC_1 (1UL) - - -#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_rng_regs.h deleted file mode 100644 index 1a847f5d090..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_rng_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RNG_H -#define HPM_RNG_H - -typedef struct { - __RW uint32_t CMD; /* 0x0: Command Register */ - __RW uint32_t CTRL; /* 0x4: Control Register */ - __R uint32_t STA; /* 0x8: Status Register */ - __R uint32_t ERR; /* 0xC: Error Registers */ - __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ -} RNG_Type; - - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. - * 0 Do not perform a software reset. - * 1 Software reset - */ -#define RNG_CMD_SFTRST_MASK (0x40U) -#define RNG_CMD_SFTRST_SHIFT (6U) -#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) -#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) - -/* - * CLRERR (RW) - * - * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. - * 0 Do not clear the errors and the interrupt. - * 1 Clear the errors and the interrupt. - */ -#define RNG_CMD_CLRERR_MASK (0x20U) -#define RNG_CMD_CLRERR_SHIFT (5U) -#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) -#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) - -/* - * CLRINT (RW) - * - * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. - * 0 Do not clear the interrupt. - * 1 Clear the interrupt - */ -#define RNG_CMD_CLRINT_MASK (0x10U) -#define RNG_CMD_CLRINT_SHIFT (4U) -#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) -#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) - -/* - * GENSD (RW) - * - * Generate Seed, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_GENSD_MASK (0x2U) -#define RNG_CMD_GENSD_SHIFT (1U) -#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) -#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) - -/* - * SLFCHK (RW) - * - * Self Test, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_SLFCHK_MASK (0x1U) -#define RNG_CMD_SLFCHK_SHIFT (0U) -#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) -#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * MIRQERR (RW) - * - * Mask Interrupt Request for Error - */ -#define RNG_CTRL_MIRQERR_MASK (0x40U) -#define RNG_CTRL_MIRQERR_SHIFT (6U) -#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) -#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) - -/* - * MIRQDN (RW) - * - * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: - * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). - * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - */ -#define RNG_CTRL_MIRQDN_MASK (0x20U) -#define RNG_CTRL_MIRQDN_SHIFT (5U) -#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) -#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) - -/* - * AUTRSD (RW) - * - * Auto Reseed - */ -#define RNG_CTRL_AUTRSD_MASK (0x10U) -#define RNG_CTRL_AUTRSD_SHIFT (4U) -#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) -#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) - -/* - * FUFMOD (RW) - * - * FIFO underflow response mode - * 00 Return all zeros and set the ESR[FUFE]. - * 01 Return all zeros and set the ESR[FUFE]. - * 10 Generate the bus transfer error - * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - */ -#define RNG_CTRL_FUFMOD_MASK (0x3U) -#define RNG_CTRL_FUFMOD_SHIFT (0U) -#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) -#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * SCPF (RO) - * - * Self Check Pass Fail - */ -#define RNG_STA_SCPF_MASK (0xE00000UL) -#define RNG_STA_SCPF_SHIFT (21U) -#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) - -/* - * FUNCERR (RO) - * - * Error was detected, check ESR register for details - */ -#define RNG_STA_FUNCERR_MASK (0x10000UL) -#define RNG_STA_FUNCERR_SHIFT (16U) -#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) - -/* - * FSIZE (RO) - * - * Fifo Size, it is 5 in this design. - */ -#define RNG_STA_FSIZE_MASK (0xF000U) -#define RNG_STA_FSIZE_SHIFT (12U) -#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) - -/* - * FRNNU (RO) - * - * Fifo Level, Indicates the number of random words currently in the output FIFO - */ -#define RNG_STA_FRNNU_MASK (0xF00U) -#define RNG_STA_FRNNU_SHIFT (8U) -#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) - -/* - * NSDDN (RO) - * - * New seed done. - */ -#define RNG_STA_NSDDN_MASK (0x40U) -#define RNG_STA_NSDDN_SHIFT (6U) -#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) - -/* - * FSDDN (RO) - * - * 1st Seed done - * When "1", Indicates that the RNG generated the first seed. - */ -#define RNG_STA_FSDDN_MASK (0x20U) -#define RNG_STA_FSDDN_SHIFT (5U) -#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) - -/* - * SCDN (RO) - * - * Self Check Done - * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is - * initiated by setting the CMD[ST]. - * 0 Self test not completed - * 1 Completed a self test since the last reset. - */ -#define RNG_STA_SCDN_MASK (0x10U) -#define RNG_STA_SCDN_SHIFT (4U) -#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) - -/* - * RSDREQ (RO) - * - * Reseed needed - * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or - * automatically if the CTRL[ARS] is set. - */ -#define RNG_STA_RSDREQ_MASK (0x8U) -#define RNG_STA_RSDREQ_SHIFT (3U) -#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) - -/* - * IDLE (RO) - * - * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - */ -#define RNG_STA_IDLE_MASK (0x4U) -#define RNG_STA_IDLE_SHIFT (2U) -#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) - -/* - * BUSY (RO) - * - * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - */ -#define RNG_STA_BUSY_MASK (0x2U) -#define RNG_STA_BUSY_SHIFT (1U) -#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) - -/* Bitfield definition for register: ERR */ -/* - * FUFE (RO) - * - * FIFO access error(underflow) - */ -#define RNG_ERR_FUFE_MASK (0x20U) -#define RNG_ERR_FUFE_SHIFT (5U) -#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) - -/* - * SCKERR (RO) - * - * Self-test error - * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a - * hardware reset or by writing 1 to the CMD[CE] - */ -#define RNG_ERR_SCKERR_MASK (0x8U) -#define RNG_ERR_SCKERR_SHIFT (3U) -#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) - -/* Bitfield definition for register: FO2B */ -/* - * FO2B (RO) - * - * SW read the FIFO output. - */ -#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) -#define RNG_FO2B_FO2B_SHIFT (0U) -#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) - -/* Bitfield definition for register array: R2SK */ -/* - * FO2S0 (RO) - * - * FIFO out to KMAN, will be SDP engine key. - */ -#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) -#define RNG_R2SK_FO2S0_SHIFT (0U) -#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) - - - -/* R2SK register group index macro definition */ -#define RNG_R2SK_FO2S0 (0UL) -#define RNG_R2SK_FO2S1 (1UL) -#define RNG_R2SK_FO2S2 (2UL) -#define RNG_R2SK_FO2S3 (3UL) -#define RNG_R2SK_FO2S4 (4UL) -#define RNG_R2SK_FO2S5 (5UL) -#define RNG_R2SK_FO2S6 (6UL) -#define RNG_R2SK_FO2S7 (7UL) - - -#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_rtc_regs.h deleted file mode 100644 index d2325b94590..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_rtc_regs.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTC_H -#define HPM_RTC_H - -typedef struct { - __RW uint32_t SECOND; /* 0x0: Second counter */ - __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ - __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ - __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ - __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ - __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ - __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ - __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ - __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ - __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ -} RTC_Type; - - -/* Bitfield definition for register: SECOND */ -/* - * SECOND (RW) - * - * second counter - */ -#define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) -#define RTC_SECOND_SECOND_SHIFT (0U) -#define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) -#define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) - -/* Bitfield definition for register: SUBSEC */ -/* - * SUBSEC (RO) - * - * sub second counter - */ -#define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) - -/* Bitfield definition for register: SEC_SNAP */ -/* - * SEC_SNAP (RW) - * - * second snap shot, write to take snap shot - */ -#define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) -#define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) -#define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) - -/* Bitfield definition for register: SUB_SNAP */ -/* - * SUB_SNAP (RW) - * - * sub second snap shot, write to take snap shot - */ -#define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) -#define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) -#define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) - -/* Bitfield definition for register: ALARM0 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_ALARM_SHIFT (0U) -#define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) -#define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM0_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) -#define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM1 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_ALARM_SHIFT (0U) -#define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) -#define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM1_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) -#define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM_FLAG */ -/* - * ALARM1 (RW) - * - * alarm1 happen - */ -#define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) -#define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) -#define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) -#define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) - -/* - * ALARM0 (RW) - * - * alarm0 happen - */ -#define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) -#define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) -#define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) -#define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) - -/* Bitfield definition for register: ALARM_EN */ -/* - * ENABLE1 (RW) - * - * alarm1 mask - * 0: alarm1 disabled - * 1: alarm1 enabled - */ -#define RTC_ALARM_EN_ENABLE1_MASK (0x2U) -#define RTC_ALARM_EN_ENABLE1_SHIFT (1U) -#define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) -#define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) - -/* - * ENABLE0 (RW) - * - * alarm0 mask - * 0: alarm0 disabled - * 1: alarm0 enabled - */ -#define RTC_ALARM_EN_ENABLE0_MASK (0x1U) -#define RTC_ALARM_EN_ENABLE0_SHIFT (0U) -#define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) -#define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) - - - - -#endif /* HPM_RTC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sdp_regs.h deleted file mode 100644 index 7562ad654a5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sdp_regs.h +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDP_H -#define HPM_SDP_H - -typedef struct { - __RW uint32_t SDPCR; /* 0x0: SDP control register */ - __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ - __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ - __RW uint32_t STA; /* 0xC: Status Registers */ - __RW uint32_t KEYADDR; /* 0x10: Key Address */ - __RW uint32_t KEYDAT; /* 0x14: Key Data */ - __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ - __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ - __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ - __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ - __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ - __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ - __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ - __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ -} SDP_Type; - - -/* Bitfield definition for register: SDPCR */ -/* - * SFTRST (RW) - * - * soft reset. - * Write 1 then 0, to reset the SDP block. - */ -#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) -#define SDP_SDPCR_SFTRST_SHIFT (31U) -#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) -#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) - -/* - * CLKGAT (RW) - * - * Clock Gate for the SDP main logic. - * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - */ -#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) -#define SDP_SDPCR_CLKGAT_SHIFT (30U) -#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) -#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) - -/* - * CIPDIS (RO) - * - * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. - * 1, Cipher is disabled in this chip. - * 0, Cipher is enabled in this chip. - */ -#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) -#define SDP_SDPCR_CIPDIS_SHIFT (29U) -#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) - -/* - * HASDIS (RO) - * - * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. - * 1, HASH is disabled in this chip. - * 0, HASH is enabled in this chip. - */ -#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) -#define SDP_SDPCR_HASDIS_SHIFT (28U) -#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) - -/* - * CIPHEN (RW) - * - * Cipher Enablement, controlled by SW. - * 1, Cipher is Enabled. - * 0, Cipher is Disabled. - */ -#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) -#define SDP_SDPCR_CIPHEN_SHIFT (23U) -#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) -#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) - -/* - * HASHEN (RW) - * - * HASH Enablement, controlled by SW. - * 1, HASH is Enabled. - * 0, HASH is Disabled. - */ -#define SDP_SDPCR_HASHEN_MASK (0x400000UL) -#define SDP_SDPCR_HASHEN_SHIFT (22U) -#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) -#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) - -/* - * MCPEN (RW) - * - * Memory Copy Enablement, controlled by SW. - * 1, Memory copy is Enabled. - * 0, Memory copy is Disabled. - */ -#define SDP_SDPCR_MCPEN_MASK (0x200000UL) -#define SDP_SDPCR_MCPEN_SHIFT (21U) -#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) -#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) - -/* - * CONFEN (RW) - * - * Constant Fill to memory, controlled by SW. - * 1, Constant fill is Enabled. - * 0, Constant fill is Disabled. - */ -#define SDP_SDPCR_CONFEN_MASK (0x100000UL) -#define SDP_SDPCR_CONFEN_SHIFT (20U) -#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) -#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) - -/* - * DCRPDI (RW) - * - * Decryption Disable bit, Write to 1 to disable the decryption. - */ -#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) -#define SDP_SDPCR_DCRPDI_SHIFT (19U) -#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) -#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) - -/* - * TSTPKT0IRQ (RW) - * - * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - */ -#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) -#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) -#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) -#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) - -/* - * RDSCEN (RW) - * - * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) - * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - */ -#define SDP_SDPCR_RDSCEN_MASK (0x100U) -#define SDP_SDPCR_RDSCEN_SHIFT (8U) -#define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK) -#define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT) - -/* - * INTEN (RW) - * - * Interrupt Enablement, controlled by SW. - * 1, SDP interrupt is enabled. - * 0, SDP interrupt is disabled. - */ -#define SDP_SDPCR_INTEN_MASK (0x1U) -#define SDP_SDPCR_INTEN_SHIFT (0U) -#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) -#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) - -/* Bitfield definition for register: MODCTRL */ -/* - * AESALG (RW) - * - * AES algorithem selection. - * 0x0 = AES 128; - * 0x1 = AES 256; - * 0x8 = SM4； - * Others, reserved. - */ -#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) -#define SDP_MODCTRL_AESALG_SHIFT (28U) -#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) -#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) - -/* - * AESMOD (RW) - * - * AES mode selection. - * 0x0 = ECB; - * 0x1 = CBC; - * Others, reserved. - */ -#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) -#define SDP_MODCTRL_AESMOD_SHIFT (24U) -#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) -#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) - -/* - * AESKS (RW) - * - * AES Key Selection. - * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: - * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. - * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * .... - * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. - * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. - * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. - * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. - * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. - * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. - * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. - * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. - * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. - * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. - * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. - * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. - * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. - * Other values, reserved. - */ -#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) -#define SDP_MODCTRL_AESKS_SHIFT (18U) -#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) -#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) - -/* - * AESDIR (RW) - * - * AES direction - * 1x1, AES Decryption - * 1x0, AES Encryption. - */ -#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) -#define SDP_MODCTRL_AESDIR_SHIFT (16U) -#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) -#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) - -/* - * HASALG (RW) - * - * HASH Algorithem selection. - * 0x0 SHA1 — - * 0x1 CRC32 — - * 0x2 SHA256 — - */ -#define SDP_MODCTRL_HASALG_MASK (0xF000U) -#define SDP_MODCTRL_HASALG_SHIFT (12U) -#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) -#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) - -/* - * HASCHK (RW) - * - * HASH Check Enable Bit. - * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; - * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. - * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - */ -#define SDP_MODCTRL_HASCHK_MASK (0x400U) -#define SDP_MODCTRL_HASCHK_SHIFT (10U) -#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) -#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) - -/* - * HASOUT (RW) - * - * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. - * 0 INPUT HASH - * 1 OUTPUT HASH - */ -#define SDP_MODCTRL_HASOUT_MASK (0x200U) -#define SDP_MODCTRL_HASOUT_SHIFT (9U) -#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) -#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) - -/* - * DINSWP (RW) - * - * Decide whether the SDP byteswaps the input data (big-endian data); - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DINSWP_MASK (0x30U) -#define SDP_MODCTRL_DINSWP_SHIFT (4U) -#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) -#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) - -/* - * DOUTSWP (RW) - * - * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) -#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) -#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) -#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) - -/* - * KEYSWP (RW) - * - * Decide whether the SDP byteswaps the Key (big-endian data). - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_KEYSWP_MASK (0x3U) -#define SDP_MODCTRL_KEYSWP_SHIFT (0U) -#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) -#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) - -/* Bitfield definition for register: PKTCNT */ -/* - * CNTVAL (RO) - * - * This read-only field shows the current (instantaneous) value of the packet counter - */ -#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) -#define SDP_PKTCNT_CNTVAL_SHIFT (16U) -#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) - -/* - * CNTINCR (RW) - * - * The value written to this field is added to the spacket count. - */ -#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) -#define SDP_PKTCNT_CNTINCR_SHIFT (0U) -#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) -#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TAG (RO) - * - * packet tag. - */ -#define SDP_STA_TAG_MASK (0xFF000000UL) -#define SDP_STA_TAG_SHIFT (24U) -#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) - -/* - * IRQ (W1C) - * - * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - */ -#define SDP_STA_IRQ_MASK (0x800000UL) -#define SDP_STA_IRQ_SHIFT (23U) -#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) -#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) - -/* - * CHN1PKT0 (W1C) - * - * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - */ -#define SDP_STA_CHN1PKT0_MASK (0x100000UL) -#define SDP_STA_CHN1PKT0_SHIFT (20U) -#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) -#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) - -/* - * AESBSY (RO) - * - * AES Busy - */ -#define SDP_STA_AESBSY_MASK (0x80000UL) -#define SDP_STA_AESBSY_SHIFT (19U) -#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) - -/* - * HASBSY (RO) - * - * Hashing Busy - */ -#define SDP_STA_HASBSY_MASK (0x40000UL) -#define SDP_STA_HASBSY_SHIFT (18U) -#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) - -/* - * PKTCNT0 (W1C) - * - * Packet Counter registers reachs to ZERO now. - */ -#define SDP_STA_PKTCNT0_MASK (0x20000UL) -#define SDP_STA_PKTCNT0_SHIFT (17U) -#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) -#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) - -/* - * PKTDON (W1C) - * - * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - */ -#define SDP_STA_PKTDON_MASK (0x10000UL) -#define SDP_STA_PKTDON_SHIFT (16U) -#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) -#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) - -/* - * ERRSET (W1C) - * - * Working mode setup error. - */ -#define SDP_STA_ERRSET_MASK (0x20U) -#define SDP_STA_ERRSET_SHIFT (5U) -#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) -#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) - -/* - * ERRPKT (W1C) - * - * Packet head access error, or status update error. - */ -#define SDP_STA_ERRPKT_MASK (0x10U) -#define SDP_STA_ERRPKT_SHIFT (4U) -#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) -#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) - -/* - * ERRSRC (W1C) - * - * Source Buffer Access Error - */ -#define SDP_STA_ERRSRC_MASK (0x8U) -#define SDP_STA_ERRSRC_SHIFT (3U) -#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) -#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) - -/* - * ERRDST (W1C) - * - * Destination Buffer Error - */ -#define SDP_STA_ERRDST_MASK (0x4U) -#define SDP_STA_ERRDST_SHIFT (2U) -#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) -#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) - -/* - * ERRHAS (W1C) - * - * Hashing Check Error - */ -#define SDP_STA_ERRHAS_MASK (0x2U) -#define SDP_STA_ERRHAS_SHIFT (1U) -#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) -#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) - -/* - * ERRCHAIN (W1C) - * - * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - */ -#define SDP_STA_ERRCHAIN_MASK (0x1U) -#define SDP_STA_ERRCHAIN_SHIFT (0U) -#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) -#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) - -/* Bitfield definition for register: KEYADDR */ -/* - * INDEX (RW) - * - * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. - * Key index pointer. The valid indices are 0-[number_keys]. - * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - */ -#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) -#define SDP_KEYADDR_INDEX_SHIFT (16U) -#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) -#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) - -/* - * SUBWRD (RW) - * - * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field - * increments; To write a key, the software must first write the desired key index/subword to this register. - */ -#define SDP_KEYADDR_SUBWRD_MASK (0x3U) -#define SDP_KEYADDR_SUBWRD_SHIFT (0U) -#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) -#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) - -/* Bitfield definition for register: KEYDAT */ -/* - * KEYDAT (RW) - * - * This register provides the write access to the key/key subword specified by the key index register. - * Writing this location updates the selected subword for the key located at the index - * specified by the key index register. The write also triggers the SUBWORD field of the - * KEY register to increment to the next higher word in the key - */ -#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) -#define SDP_KEYDAT_KEYDAT_SHIFT (0U) -#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) -#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) - -/* Bitfield definition for register array: CIPHIV */ -/* - * CIPHIV (RW) - * - * cipher initialization vector. - */ -#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) -#define SDP_CIPHIV_CIPHIV_SHIFT (0U) -#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) -#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) - -/* Bitfield definition for register array: HASWRD */ -/* - * HASWRD (RW) - * - * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. - * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - */ -#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) -#define SDP_HASWRD_HASWRD_SHIFT (0U) -#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) -#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) - -/* Bitfield definition for register: CMDPTR */ -/* - * CMDPTR (RW) - * - * current command addresses the register points to the multiword - * descriptor that is to be executed (or is currently being executed) - */ -#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) -#define SDP_CMDPTR_CMDPTR_SHIFT (0U) -#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) -#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) - -/* Bitfield definition for register: NPKTPTR */ -/* - * NPKTPTR (RW) - * - * Next Packet Address Pointer - */ -#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) -#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) -#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) -#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) - -/* Bitfield definition for register: PKTCTL */ -/* - * PKTTAG (RW) - * - * packet tag - */ -#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) -#define SDP_PKTCTL_PKTTAG_SHIFT (24U) -#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) -#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) - -/* - * CIPHIV (RW) - * - * Load Initial Vector for the AES in this packet. - */ -#define SDP_PKTCTL_CIPHIV_MASK (0x40U) -#define SDP_PKTCTL_CIPHIV_SHIFT (6U) -#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) -#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) - -/* - * HASFNL (RW) - * - * Hash Termination packet - */ -#define SDP_PKTCTL_HASFNL_MASK (0x20U) -#define SDP_PKTCTL_HASFNL_SHIFT (5U) -#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) -#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) - -/* - * HASINI (RW) - * - * Hash Initialization packat - */ -#define SDP_PKTCTL_HASINI_MASK (0x10U) -#define SDP_PKTCTL_HASINI_SHIFT (4U) -#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) -#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) - -/* - * CHAIN (RW) - * - * whether the next command pointer register must be loaded into the channel's current descriptor - * pointer. - */ -#define SDP_PKTCTL_CHAIN_MASK (0x8U) -#define SDP_PKTCTL_CHAIN_SHIFT (3U) -#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) -#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) - -/* - * DCRSEMA (RW) - * - * whether the channel's semaphore must be decremented at the end of the current operation. - * When the semaphore reaches a value of zero, no more operations are issued from the channel. - */ -#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) -#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) -#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) -#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) - -/* - * PKTINT (RW) - * - * Reflects whether the channel must issue an interrupt upon the completion of the packet - */ -#define SDP_PKTCTL_PKTINT_MASK (0x2U) -#define SDP_PKTCTL_PKTINT_SHIFT (1U) -#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) -#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) - -/* Bitfield definition for register: PKTSRC */ -/* - * PKTSRC (RW) - * - * Packet Memory Source Address - */ -#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) -#define SDP_PKTSRC_PKTSRC_SHIFT (0U) -#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) -#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) - -/* Bitfield definition for register: PKTDST */ -/* - * PKTDST (RW) - * - * Packet Memory Destination Address - */ -#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) -#define SDP_PKTDST_PKTDST_SHIFT (0U) -#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) -#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) - -/* Bitfield definition for register: PKTBUF */ -/* - * PKTBUF (RW) - * - */ -#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) -#define SDP_PKTBUF_PKTBUF_SHIFT (0U) -#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) -#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) - - - -/* CIPHIV register group index macro definition */ -#define SDP_CIPHIV_CIPHIV0 (0UL) -#define SDP_CIPHIV_CIPHIV1 (1UL) -#define SDP_CIPHIV_CIPHIV2 (2UL) -#define SDP_CIPHIV_CIPHIV3 (3UL) - -/* HASWRD register group index macro definition */ -#define SDP_HASWRD_HASWRD0 (0UL) -#define SDP_HASWRD_HASWRD1 (1UL) -#define SDP_HASWRD_HASWRD2 (2UL) -#define SDP_HASWRD_HASWRD3 (3UL) -#define SDP_HASWRD_HASWRD4 (4UL) -#define SDP_HASWRD_HASWRD5 (5UL) -#define SDP_HASWRD_HASWRD6 (6UL) -#define SDP_HASWRD_HASWRD7 (7UL) - - -#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sdxc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sdxc_regs.h deleted file mode 100644 index 7537bdd8e6b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sdxc_regs.h +++ /dev/null @@ -1,4417 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDXC_H -#define HPM_SDXC_H - -typedef struct { - __RW uint32_t SDMASA; /* 0x0: */ - __RW uint32_t BLK_ATTR; /* 0x4: */ - __RW uint32_t CMD_ARG; /* 0x8: */ - __RW uint32_t CMD_XFER; /* 0xC: */ - __R uint32_t RESP[4]; /* 0x10 - 0x1C: */ - __RW uint32_t BUF_DATA; /* 0x20: */ - __R uint32_t PSTATE; /* 0x24: */ - __RW uint32_t PROT_CTRL; /* 0x28: */ - __RW uint32_t SYS_CTRL; /* 0x2C: */ - __RW uint32_t INT_STAT; /* 0x30: */ - __RW uint32_t INT_STAT_EN; /* 0x34: */ - __RW uint32_t INT_SIGNAL_EN; /* 0x38: */ - __RW uint32_t AC_HOST_CTRL; /* 0x3C: */ - __R uint32_t CAPABILITIES1; /* 0x40: */ - __R uint32_t CAPABILITIES2; /* 0x44: */ - __R uint32_t CURR_CAPABILITIES1; /* 0x48: */ - __R uint32_t CURR_CAPABILITIES2; /* 0x4C: */ - __W uint32_t FORCE_EVENT; /* 0x50: */ - __R uint32_t ADMA_ERR_STAT; /* 0x54: */ - __RW uint32_t ADMA_SYS_ADDR; /* 0x58: */ - __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */ - __R uint16_t PRESET[11]; /* 0x60 - 0x74: */ - __R uint8_t RESERVED1[2]; /* 0x76 - 0x77: Reserved */ - __RW uint32_t ADMA_ID_ADDR; /* 0x78: */ - __R uint8_t RESERVED2[106]; /* 0x7C - 0xE5: Reserved */ - __R uint16_t P_EMBEDDED_CNTRL; /* 0xE6: */ - __R uint16_t P_VENDOR_SPECIFIC_AREA; /* 0xE8: */ - __R uint16_t P_VENDOR2_SPECIFIC_AREA; /* 0xEA: */ - __R uint8_t RESERVED3[16]; /* 0xEC - 0xFB: Reserved */ - __R uint16_t SLOT_INTR_STATUS; /* 0xFC: */ - __R uint8_t RESERVED4[130]; /* 0xFE - 0x17F: Reserved */ - __R uint32_t CQVER; /* 0x180: */ - __R uint32_t CQCAP; /* 0x184: */ - __RW uint32_t CQCFG; /* 0x188: */ - __RW uint32_t CQCTL; /* 0x18C: */ - __RW uint32_t CQIS; /* 0x190: */ - __RW uint32_t CQISE; /* 0x194: */ - __RW uint32_t CQISGE; /* 0x198: */ - __RW uint32_t CQIC; /* 0x19C: */ - __RW uint32_t CQTDLBA; /* 0x1A0: */ - __R uint8_t RESERVED5[4]; /* 0x1A4 - 0x1A7: Reserved */ - __RW uint32_t CQTDBR; /* 0x1A8: */ - __RW uint32_t CQTCN; /* 0x1AC: */ - __RW uint32_t CQDQS; /* 0x1B0: */ - __RW uint32_t CQDPT; /* 0x1B4: */ - __RW uint32_t CQTCLR; /* 0x1B8: */ - __R uint8_t RESERVED6[4]; /* 0x1BC - 0x1BF: Reserved */ - __RW uint32_t CQSSC1; /* 0x1C0: */ - __RW uint32_t CQSSC2; /* 0x1C4: */ - __R uint32_t CQCRDCT; /* 0x1C8: */ - __R uint8_t RESERVED7[4]; /* 0x1CC - 0x1CF: Reserved */ - __RW uint32_t CQRMEM; /* 0x1D0: */ - __R uint32_t CQTERRI; /* 0x1D4: */ - __R uint32_t CQCRI; /* 0x1D8: */ - __R uint32_t CQCRA; /* 0x1DC: */ - __R uint8_t RESERVED8[800]; /* 0x1E0 - 0x4FF: Reserved */ - __R uint32_t MSHC_VER_ID; /* 0x500: */ - __R uint32_t MSHC_VER_TYPE; /* 0x504: */ - __R uint8_t RESERVED9[36]; /* 0x508 - 0x52B: Reserved */ - __RW uint32_t EMMC_BOOT_CTRL; /* 0x52C: */ - __R uint8_t RESERVED10[16]; /* 0x530 - 0x53F: Reserved */ - __RW uint32_t AUTO_TUNING_CTRL; /* 0x540: */ - __RW uint32_t AUTO_TUNING_STAT; /* 0x544: */ - __R uint8_t RESERVED11[10936]; /* 0x548 - 0x2FFF: Reserved */ - __RW uint32_t MISC_CTRL0; /* 0x3000: */ - __RW uint32_t MISC_CTRL1; /* 0x3004: */ -} SDXC_Type; - - -/* Bitfield definition for register: SDMASA */ -/* - * BLOCKCNT_SDMASA (RW) - * - * 32-bit Block Count (SDMA System Address) - * - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. - * When the Host Controller stops an SDMA transfer, this register points to the system address of the next contiguous data position. - * It can be accessed only if no transaction is executing. Reading this register during data transfers may - * return an invalid value. - * - 32-bit Block Count (Host Version 4 Enable = 1): From the Host Controller Version 4.10 specification, this register is redefined as 32-bit Block Count. - * The Host Controller decrements the block count of this register for every block transfer and the data transfer stops when the count reaches zero. - * This register must be accessed when no transaction is executing. Reading this register during data transfers may return invalid value. - * Following are the values for BLOCKCNT_SDMASA: - * - 0xFFFF_FFFF: 4G - 1 Block - * - - * - 0x0000_0002: 2 Blocks - * - 0x0000_0001: 1 Block - * - 0x0000_0000: Stop Count - * Note: - * - For Host Version 4 Enable = 0, the Host driver does not program the system address in this register while operating in ADMA mode. - * The system address must be programmed in the ADMA System Address register. - * - For Host Version 4 Enable = 0, the Host driver programs a non-zero 32-bit block count value in this register when Auto CMD23 is enabled for non-DMA and ADMA modes. - * Auto CMD23 cannot be used with SDMA. - * - This register must be programmed with a non-zero value for data transfer if the 32-bit Block count register is used instead of the 16-bit Block count register. - */ -#define SDXC_SDMASA_BLOCKCNT_SDMASA_MASK (0xFFFFFFFFUL) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT (0U) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_SET(x) (((uint32_t)(x) << SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) -#define SDXC_SDMASA_BLOCKCNT_SDMASA_GET(x) (((uint32_t)(x) & SDXC_SDMASA_BLOCKCNT_SDMASA_MASK) >> SDXC_SDMASA_BLOCKCNT_SDMASA_SHIFT) - -/* Bitfield definition for register: BLK_ATTR */ -/* - * BLOCK_CNT (RW) - * - * 16-bit Block Count - * - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero, the 16-bit Block Count register is selected. - * - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register is set to zero, the 32-bit Block Count register is selected. - * Following are the values for BLOCK_CNT: - * - 0x0: Stop Count - * - 0x1: 1 Block - * - 0x2: 2 Blocks - * - . - * - 0xFFFF: 65535 Blocks - * Note: For Host Version 4 Enable = 0, this register must be set to 0000h before programming the 32-bit block count register when Auto CMD23 is enabled for non-DMA and ADMA modes. - */ -#define SDXC_BLK_ATTR_BLOCK_CNT_MASK (0xFFFF0000UL) -#define SDXC_BLK_ATTR_BLOCK_CNT_SHIFT (16U) -#define SDXC_BLK_ATTR_BLOCK_CNT_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) -#define SDXC_BLK_ATTR_BLOCK_CNT_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_BLOCK_CNT_MASK) >> SDXC_BLK_ATTR_BLOCK_CNT_SHIFT) - -/* - * SDMA_BUF_BDARY (RW) - * - * SDMA Buffer Boundary - * These bits specify the size of contiguous buffer in system memory. - * The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to update the SDMA System Address register. - * Values: - * - 0x0 (BYTES_4K): 4K bytes SDMA Buffer Boundary - * - 0x1 (BYTES_8K): 8K bytes SDMA Buffer Boundary - * - 0x2 (BYTES_16K): 16K bytes SDMA Buffer Boundary - * - 0x3 (BYTES_32K): 32K bytes SDMA Buffer Boundary - * - 0x4 (BYTES_64K): 64K bytes SDMA Buffer Boundary - * - 0x5 (BYTES_128K): 128K bytes SDMA Buffer Boundary - * - 0x6 (BYTES_256K): 256K bytes SDMA Buffer Boundary - * - 0x7 (BYTES_512K): 512K bytes SDMA Buffer Boundary - */ -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK (0x7000U) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT (12U) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) -#define SDXC_BLK_ATTR_SDMA_BUF_BDARY_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_SDMA_BUF_BDARY_MASK) >> SDXC_BLK_ATTR_SDMA_BUF_BDARY_SHIFT) - -/* - * XFER_BLOCK_SIZE (RW) - * - * Transfer Block Size - * These bits specify the block size of data transfers. In case of memory, it is set to 512 bytes. It can be accessed only if no transaction is executing. - * Read operations during transfers may return an invalid value, and write operations are ignored. Following are the values for XFER_BLOCK_SIZE: - * - 0x1: 1 byte - * - 0x2: 2 bytes - * - 0x3: 3 bytes - * - . - * - 0x1FF: 511 byte - * - 0x200: 512 byt es - * - . - * - 0x800: 2048 bytes - * Note: This register must be programmed with a non-zero value for data transfer. - */ -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK (0xFFFU) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT (0U) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SET(x) (((uint32_t)(x) << SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) -#define SDXC_BLK_ATTR_XFER_BLOCK_SIZE_GET(x) (((uint32_t)(x) & SDXC_BLK_ATTR_XFER_BLOCK_SIZE_MASK) >> SDXC_BLK_ATTR_XFER_BLOCK_SIZE_SHIFT) - -/* Bitfield definition for register: CMD_ARG */ -/* - * ARGUMNET (RW) - * - * Command Argument - * These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format. - */ -#define SDXC_CMD_ARG_ARGUMNET_MASK (0xFFFFFFFFUL) -#define SDXC_CMD_ARG_ARGUMNET_SHIFT (0U) -#define SDXC_CMD_ARG_ARGUMNET_SET(x) (((uint32_t)(x) << SDXC_CMD_ARG_ARGUMNET_SHIFT) & SDXC_CMD_ARG_ARGUMNET_MASK) -#define SDXC_CMD_ARG_ARGUMNET_GET(x) (((uint32_t)(x) & SDXC_CMD_ARG_ARGUMNET_MASK) >> SDXC_CMD_ARG_ARGUMNET_SHIFT) - -/* Bitfield definition for register: CMD_XFER */ -/* - * CMD_INDEX (RW) - * - * Command Index - * These bits are set to the command number that is specified in bits 45-40 of the Command Format. - */ -#define SDXC_CMD_XFER_CMD_INDEX_MASK (0x3F000000UL) -#define SDXC_CMD_XFER_CMD_INDEX_SHIFT (24U) -#define SDXC_CMD_XFER_CMD_INDEX_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_INDEX_SHIFT) & SDXC_CMD_XFER_CMD_INDEX_MASK) -#define SDXC_CMD_XFER_CMD_INDEX_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_INDEX_MASK) >> SDXC_CMD_XFER_CMD_INDEX_SHIFT) - -/* - * CMD_TYPE (RW) - * - * Command Type - * These bits indicate the command type. - * Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52, CMD_TYPE field shall be set to 0x3. - * Values: - * 0x3 (ABORT_CMD): Abort - * 0x2 (RESUME_CMD): Resume - * 0x1 (SUSPEND_CMD): Suspend - * 0x0 (NORMAL_CMD): Normal - */ -#define SDXC_CMD_XFER_CMD_TYPE_MASK (0xC00000UL) -#define SDXC_CMD_XFER_CMD_TYPE_SHIFT (22U) -#define SDXC_CMD_XFER_CMD_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_TYPE_SHIFT) & SDXC_CMD_XFER_CMD_TYPE_MASK) -#define SDXC_CMD_XFER_CMD_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_TYPE_MASK) >> SDXC_CMD_XFER_CMD_TYPE_SHIFT) - -/* - * DATA_PRESENT_SEL (RW) - * - * Data Present Select - * This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: - * Command using the CMD line - * Command with no data transfer but using busy signal on the DAT[0] line - * Resume Command - * Values: - * 0x0 (NO_DATA): No Data Present - * 0x1 (DATA): Data Present - */ -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK (0x200000UL) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT (21U) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) -#define SDXC_CMD_XFER_DATA_PRESENT_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_PRESENT_SEL_MASK) >> SDXC_CMD_XFER_DATA_PRESENT_SEL_SHIFT) - -/* - * CMD_IDX_CHK_ENABLE (RW) - * - * Command Index Check Enable - * This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. - * If the value is not the same, it is reported as a Command Index error. - * Note: - * Index Check enable must be set to 0 for the command with no response, R2 response, R3 response and R4 response. - * For the tuning command, this bit must always be set to enable the index check. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK (0x100000UL) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT (20U) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_IDX_CHK_ENABLE_SHIFT) - -/* - * CMD_CRC_CHK_ENABLE (RW) - * - * Command CRC Check Enable - * This bit enables the Host Controller to check the CRC field in the response. If an error is detected, it is reported as a Command CRC error. - * Note: - * CRC Check enable must be set to 0 for the command with no response, R3 response, and R4 response. - * For the tuning command, this bit must always be set to 1 to enable the CRC check. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK (0x80000UL) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT (19U) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_CMD_CRC_CHK_ENABLE_SHIFT) - -/* - * SUB_CMD_FLAG (RW) - * - * Sub Command Flag - * This bit distinguishes between a main command and a sub command. - * Values: - * 0x0 (MAIN): Main Command - * 0x1 (SUB): Sub Command - */ -#define SDXC_CMD_XFER_SUB_CMD_FLAG_MASK (0x40000UL) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT (18U) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) -#define SDXC_CMD_XFER_SUB_CMD_FLAG_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_SUB_CMD_FLAG_MASK) >> SDXC_CMD_XFER_SUB_CMD_FLAG_SHIFT) - -/* - * RESP_TYPE_SELECT (RW) - * - * Response Type Select - * This bit indicates the type of response expected from the card. - * Values: - * 0x0 (NO_RESP): No Response - * 0x1 (RESP_LEN_136): Response Length 136 - * 0x2 (RESP_LEN_48): Response Length 48 - * 0x3 (RESP_LEN_48B): Response Length 48; Check Busy after response - */ -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK (0x30000UL) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT (16U) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) -#define SDXC_CMD_XFER_RESP_TYPE_SELECT_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_SELECT_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SELECT_SHIFT) - -/* - * RESP_INT_DISABLE (RW) - * - * Response Interrupt Disable - * The Host Controller supports response check function to avoid overhead of response error check by the Host driver. - * Response types of only R1 and R5 can be checked by the Controller. - * If Host Driver checks the response error, set this bit to 0 and wait for Command Complete Interrupt and then check the response register. - * If the Host Controller checks the response error, set this bit to 1 and set the Response Error Check Enable bit to 1. - * The Command Complete Interrupt is disabled by this bit regardless of the Command Complete Signal Enable. - * Note: During tuning (when the Execute Tuning bit in the Host Control2 register is set), the Command Complete Interrupt is not generated irrespective of the Response Interrupt Disable setting. - * Values: - * - 0x0 (ENABLED): Response Interrupt is enabled - * - 0x1 (DISABLED): Response Interrupt is disabled - */ -#define SDXC_CMD_XFER_RESP_INT_DISABLE_MASK (0x100U) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT (8U) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) -#define SDXC_CMD_XFER_RESP_INT_DISABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_INT_DISABLE_MASK) >> SDXC_CMD_XFER_RESP_INT_DISABLE_SHIFT) - -/* - * RESP_ERR_CHK_ENABLE (RW) - * - * Response Error Check Enable - * The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. - * If the Host Controller checks the response error, set this bit to 1 and set Response Interrupt Disable to 1. If an error is detected, the Response Error interrupt is generated in the Error Interrupt Status register. - * Note: - * - Response error check must not be enabled for any response type other than R1 and R5. - * - Response check must not be enabled for the tuning command. - * Values: - * - 0x0 (DISABLED): Response Error Check is disabled - * - 0x1 (ENABLED): Response Error Check is enabled - */ -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK (0x80U) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT (7U) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) -#define SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_MASK) >> SDXC_CMD_XFER_RESP_ERR_CHK_ENABLE_SHIFT) - -/* - * RESP_TYPE (RW) - * - * Response Type R1/R5 - * This bit selects either R1 or R5 as a response type when the Response Error Check is selected. - * Error statuses checked in R1: - * OUT_OF_RANGE - * ADDRESS_ERROR - * BLOCK_LEN_ERROR - * WP_VIOLATION - * CARD_IS_LOCKED - * COM_CRC_ERROR - * CARD_ECC_FAILED - * CC_ERROR - * ERROR - * Response Flags checked in R5: - * COM_CRC_ERROR - * ERROR - * FUNCTION_NUMBER - * OUT_OF_RANGE - * Values: - * 0x0 (RESP_R1): R1 (Memory) - * 0x1 (RESP_R5): R5 (SDIO) - */ -#define SDXC_CMD_XFER_RESP_TYPE_MASK (0x40U) -#define SDXC_CMD_XFER_RESP_TYPE_SHIFT (6U) -#define SDXC_CMD_XFER_RESP_TYPE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_RESP_TYPE_SHIFT) & SDXC_CMD_XFER_RESP_TYPE_MASK) -#define SDXC_CMD_XFER_RESP_TYPE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_RESP_TYPE_MASK) >> SDXC_CMD_XFER_RESP_TYPE_SHIFT) - -/* - * MULTI_BLK_SEL (RW) - * - * Multi/Single Block Select - * This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0, it is not necessary to set the Block Count register. - * Values: - * 0x0 (SINGLE): Single Block - * 0x1 (MULTI): Multiple Block - */ -#define SDXC_CMD_XFER_MULTI_BLK_SEL_MASK (0x20U) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT (5U) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) -#define SDXC_CMD_XFER_MULTI_BLK_SEL_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_MULTI_BLK_SEL_MASK) >> SDXC_CMD_XFER_MULTI_BLK_SEL_SHIFT) - -/* - * DATA_XFER_DIR (RW) - * - * Data Transfer Direction Select - * This bit defines the direction of DAT line data transfers. - * This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. - * Values: - * 0x1 (READ): Read (Card to Host) - * 0x0 (WRITE): Write (Host to Card) - */ -#define SDXC_CMD_XFER_DATA_XFER_DIR_MASK (0x10U) -#define SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT (4U) -#define SDXC_CMD_XFER_DATA_XFER_DIR_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) -#define SDXC_CMD_XFER_DATA_XFER_DIR_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DATA_XFER_DIR_MASK) >> SDXC_CMD_XFER_DATA_XFER_DIR_SHIFT) - -/* - * AUTO_CMD_ENABLE (RW) - * - * Auto Command Enable - * This field determines use of Auto Command functions. - * Note: In SDIO, this field must be set as 00b (Auto Command Disabled). - * Values: - * 0x0 (AUTO_CMD_DISABLED): Auto Command Disabled - * 0x1 (AUTO_CMD12_ENABLED): Auto CMD12 Enable - * 0x2 (AUTO_CMD23_ENABLED): Auto CMD23 Enable - * 0x3 (AUTO_CMD_AUTO_SEL): Auto CMD Auto Sel - */ -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK (0xCU) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT (2U) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) -#define SDXC_CMD_XFER_AUTO_CMD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_AUTO_CMD_ENABLE_MASK) >> SDXC_CMD_XFER_AUTO_CMD_ENABLE_SHIFT) - -/* - * BLOCK_COUNT_ENABLE (RW) - * - * Block Count Enable - * This bit is used to enable the Block Count register, which is relevant for multiple block transfers. - * If this bit is set to 0, the Block Count register is disabled, which is useful in executing an infinite transfer. - * The Host Driver must set this bit to 0 when ADMA is used. - * Values: - * 0x1 (ENABLED): Enable - * 0x0 (DISABLED): Disable - */ -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK (0x2U) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT (1U) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) -#define SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_MASK) >> SDXC_CMD_XFER_BLOCK_COUNT_ENABLE_SHIFT) - -/* - * DMA_ENABLE (RW) - * - * DMA Enable - * This bit enables the DMA functionality. If this bit is set to 1, a DMA operation begins when the Host Driver writes to the Command register. - * You can select one of the DMA modes by using DMA Select in the Host Control 1 register. - * Values: - * 0x1 (ENABLED): DMA Data transfer - * 0x0 (DISABLED): No data transfer or Non-DMA data transfer - */ -#define SDXC_CMD_XFER_DMA_ENABLE_MASK (0x1U) -#define SDXC_CMD_XFER_DMA_ENABLE_SHIFT (0U) -#define SDXC_CMD_XFER_DMA_ENABLE_SET(x) (((uint32_t)(x) << SDXC_CMD_XFER_DMA_ENABLE_SHIFT) & SDXC_CMD_XFER_DMA_ENABLE_MASK) -#define SDXC_CMD_XFER_DMA_ENABLE_GET(x) (((uint32_t)(x) & SDXC_CMD_XFER_DMA_ENABLE_MASK) >> SDXC_CMD_XFER_DMA_ENABLE_SHIFT) - -/* Bitfield definition for register array: RESP */ -/* - * RESP01 (RO) - * - * Command Response - * These bits reflect 39-8 bits of SD/eMMC Response Field. - * Note: For Auto CMD, the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP[RESP67] register. - */ -#define SDXC_RESP_RESP01_MASK (0xFFFFFFFFUL) -#define SDXC_RESP_RESP01_SHIFT (0U) -#define SDXC_RESP_RESP01_GET(x) (((uint32_t)(x) & SDXC_RESP_RESP01_MASK) >> SDXC_RESP_RESP01_SHIFT) - -/* Bitfield definition for register: BUF_DATA */ -/* - * BUF_DATA (RW) - * - * Buffer Data - * These bits enable access to the Host Controller packet buffer. - */ -#define SDXC_BUF_DATA_BUF_DATA_MASK (0xFFFFFFFFUL) -#define SDXC_BUF_DATA_BUF_DATA_SHIFT (0U) -#define SDXC_BUF_DATA_BUF_DATA_SET(x) (((uint32_t)(x) << SDXC_BUF_DATA_BUF_DATA_SHIFT) & SDXC_BUF_DATA_BUF_DATA_MASK) -#define SDXC_BUF_DATA_BUF_DATA_GET(x) (((uint32_t)(x) & SDXC_BUF_DATA_BUF_DATA_MASK) >> SDXC_BUF_DATA_BUF_DATA_SHIFT) - -/* Bitfield definition for register: PSTATE */ -/* - * SUB_CMD_STAT (RO) - * - * Sub Command Status - * This bit is used to distinguish between a main command and a sub command status. - * Values: - * 0x0 (FALSE): Main Command Status - * 0x1 (TRUE): Sub Command Status - */ -#define SDXC_PSTATE_SUB_CMD_STAT_MASK (0x10000000UL) -#define SDXC_PSTATE_SUB_CMD_STAT_SHIFT (28U) -#define SDXC_PSTATE_SUB_CMD_STAT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_SUB_CMD_STAT_MASK) >> SDXC_PSTATE_SUB_CMD_STAT_SHIFT) - -/* - * CMD_ISSUE_ERR (RO) - * - * Command Not Issued by Error - * This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. - * Values: - * 0x0 (FALSE): No error for issuing a command - * 0x1 (TRUE): Command cannot be issued - */ -#define SDXC_PSTATE_CMD_ISSUE_ERR_MASK (0x8000000UL) -#define SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT (27U) -#define SDXC_PSTATE_CMD_ISSUE_ERR_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_ISSUE_ERR_MASK) >> SDXC_PSTATE_CMD_ISSUE_ERR_SHIFT) - -/* - * CMD_LINE_LVL (RO) - * - * Command-Line Signal Level - * This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal. - */ -#define SDXC_PSTATE_CMD_LINE_LVL_MASK (0x1000000UL) -#define SDXC_PSTATE_CMD_LINE_LVL_SHIFT (24U) -#define SDXC_PSTATE_CMD_LINE_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_LINE_LVL_MASK) >> SDXC_PSTATE_CMD_LINE_LVL_SHIFT) - -/* - * DAT_3_0 (RO) - * - * DAT[3:0] Line Signal Level - * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal. - */ -#define SDXC_PSTATE_DAT_3_0_MASK (0xF00000UL) -#define SDXC_PSTATE_DAT_3_0_SHIFT (20U) -#define SDXC_PSTATE_DAT_3_0_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_3_0_MASK) >> SDXC_PSTATE_DAT_3_0_SHIFT) - -/* - * WR_PROTECT_SW_LVL (RO) - * - * Write Protect Switch Pin Level - * This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. - * Values: - * 0x0 (FALSE): Write protected - * 0x1 (TRUE): Write enabled - */ -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK (0x80000UL) -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT (19U) -#define SDXC_PSTATE_WR_PROTECT_SW_LVL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_PROTECT_SW_LVL_MASK) >> SDXC_PSTATE_WR_PROTECT_SW_LVL_SHIFT) - -/* - * CARD_DETECT_PIN_LEVEL (RO) - * - * Card Detect Pin Level - * This bit reflects the inverse synchronized value of the card_detect_n signal. - * Values: - * 0x0 (FALSE): No card present - * 0x1 (TRUE): Card Present - */ -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK (0x40000UL) -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT (18U) -#define SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_MASK) >> SDXC_PSTATE_CARD_DETECT_PIN_LEVEL_SHIFT) - -/* - * CARD_STABLE (RO) - * - * Card Stable - * This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. - * Values: - * 0x0 (FALSE): Reset or Debouncing - * 0x1 (TRUE): No Card or Inserted - */ -#define SDXC_PSTATE_CARD_STABLE_MASK (0x20000UL) -#define SDXC_PSTATE_CARD_STABLE_SHIFT (17U) -#define SDXC_PSTATE_CARD_STABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_STABLE_MASK) >> SDXC_PSTATE_CARD_STABLE_SHIFT) - -/* - * CARD_INSERTED (RO) - * - * Card Inserted - * This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. - * Values: - * 0x0 (FALSE): Reset, Debouncing, or No card - * 0x1 (TRUE): Card Inserted - */ -#define SDXC_PSTATE_CARD_INSERTED_MASK (0x10000UL) -#define SDXC_PSTATE_CARD_INSERTED_SHIFT (16U) -#define SDXC_PSTATE_CARD_INSERTED_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CARD_INSERTED_MASK) >> SDXC_PSTATE_CARD_INSERTED_SHIFT) - -/* - * BUF_RD_ENABLE (RO) - * - * Buffer Read Enable - * This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. - * Values: - * 0x0 (DISABLED): Read disable - * 0x1 (ENABLED): Read enable - */ -#define SDXC_PSTATE_BUF_RD_ENABLE_MASK (0x800U) -#define SDXC_PSTATE_BUF_RD_ENABLE_SHIFT (11U) -#define SDXC_PSTATE_BUF_RD_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_RD_ENABLE_MASK) >> SDXC_PSTATE_BUF_RD_ENABLE_SHIFT) - -/* - * BUF_WR_ENABLE (RO) - * - * Buffer Write Enable - * This bit is used for non-DMA transfers. This bit is set if space is available for writing data. - * Values: - * 0x0 (DISABLED): Write disable - * 0x1 (ENABLED): Write enable - */ -#define SDXC_PSTATE_BUF_WR_ENABLE_MASK (0x400U) -#define SDXC_PSTATE_BUF_WR_ENABLE_SHIFT (10U) -#define SDXC_PSTATE_BUF_WR_ENABLE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_BUF_WR_ENABLE_MASK) >> SDXC_PSTATE_BUF_WR_ENABLE_SHIFT) - -/* - * RD_XFER_ACTIVE (RO) - * - * Read Transfer Active - * This bit indicates whether a read transfer is active for SD/eMMC mode. - * Values: - * 0x0 (INACTIVE): No valid data - * 0x1 (ACTIVE): Transferring data - */ -#define SDXC_PSTATE_RD_XFER_ACTIVE_MASK (0x200U) -#define SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT (9U) -#define SDXC_PSTATE_RD_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RD_XFER_ACTIVE_MASK) >> SDXC_PSTATE_RD_XFER_ACTIVE_SHIFT) - -/* - * WR_XFER_ACTIVE (RO) - * - * Write Transfer Active - * This status indicates whether a write transfer is active for SD/eMMC mode. - * Values: - * 0x0 (INACTIVE): No valid data - * 0x1 (ACTIVE): Transferring data - */ -#define SDXC_PSTATE_WR_XFER_ACTIVE_MASK (0x100U) -#define SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT (8U) -#define SDXC_PSTATE_WR_XFER_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_WR_XFER_ACTIVE_MASK) >> SDXC_PSTATE_WR_XFER_ACTIVE_SHIFT) - -/* - * DAT_7_4 (RO) - * - * DAT[7:4] Line Signal Level - * This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal. - */ -#define SDXC_PSTATE_DAT_7_4_MASK (0xF0U) -#define SDXC_PSTATE_DAT_7_4_SHIFT (4U) -#define SDXC_PSTATE_DAT_7_4_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_7_4_MASK) >> SDXC_PSTATE_DAT_7_4_SHIFT) - -/* - * RE_TUNE_REQ (RO) - * - * Re-Tuning Request - * SDXC does not generate retuning request. The software must maintain the Retuning timer. - */ -#define SDXC_PSTATE_RE_TUNE_REQ_MASK (0x8U) -#define SDXC_PSTATE_RE_TUNE_REQ_SHIFT (3U) -#define SDXC_PSTATE_RE_TUNE_REQ_GET(x) (((uint32_t)(x) & SDXC_PSTATE_RE_TUNE_REQ_MASK) >> SDXC_PSTATE_RE_TUNE_REQ_SHIFT) - -/* - * DAT_LINE_ACTIVE (RO) - * - * DAT Line Active ( - * This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. - * In the case of read transactions, this bit indicates whether a read transfer is executing on the SD/eMMC bus. - * In the case of write transactions, this bit indicates whether a write transfer is executing on the SD/eMMC bus. - * For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. - * Values: - * 0x0 (INACTIVE): DAT Line Inactive - * 0x1 (ACTIVE): DAT Line Active - */ -#define SDXC_PSTATE_DAT_LINE_ACTIVE_MASK (0x4U) -#define SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT (2U) -#define SDXC_PSTATE_DAT_LINE_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_LINE_ACTIVE_MASK) >> SDXC_PSTATE_DAT_LINE_ACTIVE_SHIFT) - -/* - * DAT_INHIBIT (RO) - * - * Command Inhibit (DAT) - * This bit is generated if either DAT line active or Read transfer active is set to 1. - * If this bit is set to 0, it indicates that the Host Controller can issue subsequent SD/eMMC commands. - * Values: - * 0x0 (READY): Can issue command which used DAT line - * 0x1 (NOT_READY): Cannot issue command which used DAT line - */ -#define SDXC_PSTATE_DAT_INHIBIT_MASK (0x2U) -#define SDXC_PSTATE_DAT_INHIBIT_SHIFT (1U) -#define SDXC_PSTATE_DAT_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_DAT_INHIBIT_MASK) >> SDXC_PSTATE_DAT_INHIBIT_SHIFT) - -/* - * CMD_INHIBIT (RO) - * - * Command Inhibit (CMD) - * This bit indicates the following : - * If this bit is set to 0, it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. - * This bit is set when the command register is written. This bit is cleared when the command response is received. - * This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. - * Values: - * 0x0 (READY): Host Controller is ready to issue a command - * 0x1 (NOT_READY): Host Controller is not ready to issue a command - */ -#define SDXC_PSTATE_CMD_INHIBIT_MASK (0x1U) -#define SDXC_PSTATE_CMD_INHIBIT_SHIFT (0U) -#define SDXC_PSTATE_CMD_INHIBIT_GET(x) (((uint32_t)(x) & SDXC_PSTATE_CMD_INHIBIT_MASK) >> SDXC_PSTATE_CMD_INHIBIT_SHIFT) - -/* Bitfield definition for register: PROT_CTRL */ -/* - * CARD_REMOVAL (RW) - * - * Wakeup Event Enable on SD Card Removal - * This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. - * For the SDIO card, Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does not affect this bit. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_REMOVAL_MASK (0x4000000UL) -#define SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT (26U) -#define SDXC_PROT_CTRL_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) -#define SDXC_PROT_CTRL_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_REMOVAL_MASK) >> SDXC_PROT_CTRL_CARD_REMOVAL_SHIFT) - -/* - * CARD_INSERT (RW) - * - * Wakeup Event Enable on SD Card Insertion - * This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. - * FN_WUS (Wake Up Support) in CIS does not affect this bit. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_INSERT_MASK (0x2000000UL) -#define SDXC_PROT_CTRL_CARD_INSERT_SHIFT (25U) -#define SDXC_PROT_CTRL_CARD_INSERT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INSERT_SHIFT) & SDXC_PROT_CTRL_CARD_INSERT_MASK) -#define SDXC_PROT_CTRL_CARD_INSERT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INSERT_MASK) >> SDXC_PROT_CTRL_CARD_INSERT_SHIFT) - -/* - * CARD_INT (RW) - * - * Wakeup Event Enable on Card Interrupt - * This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. - * This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. - * Values: - * 0x0 (DISABLED): Disable - * 0x1 (ENABLED): Enable - */ -#define SDXC_PROT_CTRL_CARD_INT_MASK (0x1000000UL) -#define SDXC_PROT_CTRL_CARD_INT_SHIFT (24U) -#define SDXC_PROT_CTRL_CARD_INT_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CARD_INT_SHIFT) & SDXC_PROT_CTRL_CARD_INT_MASK) -#define SDXC_PROT_CTRL_CARD_INT_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CARD_INT_MASK) >> SDXC_PROT_CTRL_CARD_INT_SHIFT) - -/* - * INT_AT_BGAP (RW) - * - * Interrupt At Block Gap - * This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. - * Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. - * Values: - * 0x0 (DISABLE): Disabled - * 0x1 (ENABLE): Enabled - */ -#define SDXC_PROT_CTRL_INT_AT_BGAP_MASK (0x80000UL) -#define SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT (19U) -#define SDXC_PROT_CTRL_INT_AT_BGAP_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) -#define SDXC_PROT_CTRL_INT_AT_BGAP_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_INT_AT_BGAP_MASK) >> SDXC_PROT_CTRL_INT_AT_BGAP_SHIFT) - -/* - * RD_WAIT_CTRL (RW) - * - * Read Wait Control - * This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. - * Otherwise, the Host Controller has to stop the card clock to hold the read data. In UHS-II mode, Read Wait is disabled. - * Values: - * 0x0 (DISABLE): Disable Read Wait Control - * 0x1 (ENABLE): Enable Read Wait Control - */ -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK (0x40000UL) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT (18U) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) -#define SDXC_PROT_CTRL_RD_WAIT_CTRL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_RD_WAIT_CTRL_MASK) >> SDXC_PROT_CTRL_RD_WAIT_CTRL_SHIFT) - -/* - * CONTINUE_REQ (RW) - * - * Continue Request - * This bit is used to restart the transaction, which was stopped using the Stop At Block Gap Request. - * The Host Controller automatically clears this bit when the transaction restarts. - * If stop at block gap request is set to 1, any write to this bit is ignored. - * Values: - * 0x0 (NO_AFFECT): No Affect - * 0x1 (RESTART): Restart - */ -#define SDXC_PROT_CTRL_CONTINUE_REQ_MASK (0x20000UL) -#define SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT (17U) -#define SDXC_PROT_CTRL_CONTINUE_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) -#define SDXC_PROT_CTRL_CONTINUE_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_CONTINUE_REQ_MASK) >> SDXC_PROT_CTRL_CONTINUE_REQ_SHIFT) - -/* - * STOP_BG_REQ (RW) - * - * Stop At Block Gap Request - * This bit is used to stop executing read and write transactions at the next block gap for non-DMA, SDMA, and ADMA transfers. - * Values: - * 0x0 (XFER): Transfer - * 0x1 (STOP): Stop - */ -#define SDXC_PROT_CTRL_STOP_BG_REQ_MASK (0x10000UL) -#define SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT (16U) -#define SDXC_PROT_CTRL_STOP_BG_REQ_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) -#define SDXC_PROT_CTRL_STOP_BG_REQ_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_STOP_BG_REQ_MASK) >> SDXC_PROT_CTRL_STOP_BG_REQ_SHIFT) - -/* - * SD_BUS_VOL_VDD1 (RW) - * - * SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD - * These bits enable the Host Driver to select the voltage level for an SD/eMMC card. - * Before setting this register, the Host Driver checks the Voltage Support bits in the Capabilities register. - * If an unsupported voltage is selected, the Host System does not supply the SD Bus voltage. - * The value set in this field is available on the SDXC output signal (sd_vdd1_sel), which is used by the voltage switching circuitry. - * SD Bus Voltage Select options: - * 0x7 : 3.3V(Typical) - * 0x6 : 3.0V(Typical) - * 0x5 : 1.8V(Typical) for Embedded - * 0x4 : 0x0 - Reserved - * eMMC Bus Voltage Select options: - * 0x7 : 3.3V(Typical) - * 0x6 : 1.8V(Typical) - * 0x5 : 1.2V(Typical) - * 0x4 : 0x0 - Reserved - * Values: - * 0x7 (V_3_3): 3.3V (Typ.) - * 0x6 (V_3_0): 3.0V (Typ.) - * 0x5 (V_1_8): 1.8V (Typ.) for Embedded - * 0x4 (RSVD4): Reserved - * 0x3 (RSVD3): Reserved - * 0x2 (RSVD2): Reserved - * 0x1 (RSVD1): Reserved - * 0x0 (RSVD0): Reserved - */ -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK (0xE00U) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT (9U) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) -#define SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_VOL_VDD1_SHIFT) - -/* - * SD_BUS_PWR_VDD1 (RW) - * - * SD Bus Power for VDD1 - * This bit enables VDD1 power of the card. - * This setting is available on the sd_vdd1_on output of SDXC so that it can be used to control the VDD1 power supply of the card. - * Before setting this bit, the SD Host Driver sets the SD Bus Voltage Select bit. If the Host Controller detects a No Card state, this bit is cleared. - * In SD mode, if this bit is cleared, the Host Controller stops the SD Clock by clearing the SD_CLK_EN bit in the SYS_CTRL register. - * Values: - * 0x0 (OFF): Power off - * 0x1 (ON): Power on - */ -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK (0x100U) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT (8U) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) -#define SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_MASK) >> SDXC_PROT_CTRL_SD_BUS_PWR_VDD1_SHIFT) - -/* - * EXT_DAT_XFER (RW) - * - * Extended Data Transfer Width - * This bit controls 8-bit bus width mode of embedded device. - * Values: - * 0x1 (EIGHT_BIT): 8-bit Bus Width - * 0x0 (DEFAULT): Bus Width is selected by the Data Transfer Width - */ -#define SDXC_PROT_CTRL_EXT_DAT_XFER_MASK (0x20U) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT (5U) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) -#define SDXC_PROT_CTRL_EXT_DAT_XFER_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_EXT_DAT_XFER_MASK) >> SDXC_PROT_CTRL_EXT_DAT_XFER_SHIFT) - -/* - * DMA_SEL (RW) - * - * DMA Select - * This field is used to select the DMA type. - * When Host Version 4 Enable is 1 in Host Control 2 register: - * 0x0 : SDMA is selected - * 0x1 : Reserved - * 0x2 : ADMA2 is selected - * 0x3 : ADMA2 or ADMA3 is selected - * When Host Version 4 Enable is 0 in Host Control 2 register: - * 0x0 : SDMA is selected - * 0x1 : Reserved - * 0x2 : 32-bit Address ADMA2 is selected - * 0x3 : 64-bit Address ADMA2 is selected - * Values: - * 0x0 (SDMA): SDMA is selected - * 0x1 (RSVD_BIT): Reserved - * 0x2 (ADMA2): ADMA2 is selected - * 0x3 (ADMA2_3): ADMA2 or ADMA3 is selected - */ -#define SDXC_PROT_CTRL_DMA_SEL_MASK (0x18U) -#define SDXC_PROT_CTRL_DMA_SEL_SHIFT (3U) -#define SDXC_PROT_CTRL_DMA_SEL_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DMA_SEL_SHIFT) & SDXC_PROT_CTRL_DMA_SEL_MASK) -#define SDXC_PROT_CTRL_DMA_SEL_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DMA_SEL_MASK) >> SDXC_PROT_CTRL_DMA_SEL_SHIFT) - -/* - * HIGH_SPEED_EN (RW) - * - * High Speed Enable - * this bit is used to determine the selection of preset value for High Speed mode. - * Before setting this bit, the Host Driver checks the High Speed Support in the Capabilities register. - * Note: SDXC always outputs the sd_cmd_out and sd_dat_out lines at the rising edge of cclk_tx clock irrespective of this bit. - * Values: - * 0x1 (HIGH_SPEED): High Speed mode - * 0x0 (NORMAL_SPEED): Normal Speed mode - */ -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK (0x4U) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT (2U) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) -#define SDXC_PROT_CTRL_HIGH_SPEED_EN_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_HIGH_SPEED_EN_MASK) >> SDXC_PROT_CTRL_HIGH_SPEED_EN_SHIFT) - -/* - * DAT_XFER_WIDTH (RW) - * - * Data Transfer Width - * For SD/eMMC mode,this bit selects the data transfer width of the Host Controller. - * The Host Driver sets it to match the data width of the SD/eMMC card. In UHS-II mode, this bit is irrelevant. - * Values: - * 0x1 (FOUR_BIT): 4-bit mode - * 0x0 (ONE_BIT): 1-bit mode - */ -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK (0x2U) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT (1U) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_SET(x) (((uint32_t)(x) << SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) -#define SDXC_PROT_CTRL_DAT_XFER_WIDTH_GET(x) (((uint32_t)(x) & SDXC_PROT_CTRL_DAT_XFER_WIDTH_MASK) >> SDXC_PROT_CTRL_DAT_XFER_WIDTH_SHIFT) - -/* Bitfield definition for register: SYS_CTRL */ -/* - * SW_RST_DAT (RW) - * - * Software Reset For DAT line - * This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. - * The following registers and bits are cleared by this bit: - * Buffer Data Port register - * -Buffer is cleared and initialized. - * Present state register - * -Buffer Read Enable - * -Buffer Write Enable - * -Read Transfer Active - * -Write Transfer Active - * -DAT Line Active - * -Command Inhibit (DAT) - * Block Gap Control register - * -Continue Request - * -Stop At Block Gap Request - * Normal Interrupt status register - * -Buffer Read Ready - * -Buffer Write Ready - * -DMA Interrupt - * -Block Gap Event - * -Transfer Complete - * In UHS-II mode, this bit shall be set to 0 - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_DAT_MASK (0x4000000UL) -#define SDXC_SYS_CTRL_SW_RST_DAT_SHIFT (26U) -#define SDXC_SYS_CTRL_SW_RST_DAT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) -#define SDXC_SYS_CTRL_SW_RST_DAT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_DAT_MASK) >> SDXC_SYS_CTRL_SW_RST_DAT_SHIFT) - -/* - * SW_RST_CMD (RW) - * - * Software Reset For CMD line - * This bit resets only a part of the command circuit to be able to issue a command. - * It bit is also used to initialize a UHS-II command circuit. - * This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD) control) and does not affect the data transfer circuit. - * Host Controller can continue data transfer even after this reset is executed while handling subcommand-response errors. - * The following registers and bits are cleared by this bit: - * Present State register : Command Inhibit (CMD) bit - * Normal Interrupt Status register : Command Complete bit - * Error Interrupt Status : Response error statuses related to Command Inhibit (CMD) bit - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_CMD_MASK (0x2000000UL) -#define SDXC_SYS_CTRL_SW_RST_CMD_SHIFT (25U) -#define SDXC_SYS_CTRL_SW_RST_CMD_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) -#define SDXC_SYS_CTRL_SW_RST_CMD_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_CMD_MASK) >> SDXC_SYS_CTRL_SW_RST_CMD_SHIFT) - -/* - * SW_RST_ALL (RW) - * - * Software Reset For All - * This reset affects the entire Host Controller except for the card detection circuit. - * During its initialization, the Host Driver sets this bit to 1 to reset the Host Controller. - * All registers are reset except the capabilities register. - * If this bit is set to 1, the Host Driver must issue reset command and reinitialize the card. - * Values: - * 0x0 (FALSE): Work - * 0x1 (TRUE): Reset - */ -#define SDXC_SYS_CTRL_SW_RST_ALL_MASK (0x1000000UL) -#define SDXC_SYS_CTRL_SW_RST_ALL_SHIFT (24U) -#define SDXC_SYS_CTRL_SW_RST_ALL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) -#define SDXC_SYS_CTRL_SW_RST_ALL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SW_RST_ALL_MASK) >> SDXC_SYS_CTRL_SW_RST_ALL_SHIFT) - -/* - * TOUT_CNT (RW) - * - * Data Timeout Counter Value. - * This value determines the interval by which DAT line timeouts are detected. - * The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. - * When setting this register, prevent inadvertent timeout events by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable register). - * The values for these bits are: - * 0xF : Reserved - * 0xE : TMCLK x 2^27 - * ......... - * 0x1 : TMCLK x 2^14 - * 0x0 : TMCLK x 2^13 - * Note: During a boot operating in an eMMC mode, an application must configure the boot data timeout value (approximately 1 sec) in this bit. - */ -#define SDXC_SYS_CTRL_TOUT_CNT_MASK (0xF0000UL) -#define SDXC_SYS_CTRL_TOUT_CNT_SHIFT (16U) -#define SDXC_SYS_CTRL_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_TOUT_CNT_SHIFT) & SDXC_SYS_CTRL_TOUT_CNT_MASK) -#define SDXC_SYS_CTRL_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_TOUT_CNT_MASK) >> SDXC_SYS_CTRL_TOUT_CNT_SHIFT) - -/* - * FREQ_SEL (RW) - * - * SDCLK/RCLK Frequency Select - * These bits are used to select the frequency of the SDCLK signal. - * These bits depend on setting of Preset Value Enable in the Host Control 2 register. - * If Preset Value Enable = 0, these bits are set by the Host Driver. - * If Preset Value Enable = 1, these bits are automatically set to a value specified in one of the Preset Value register. - * The value is reflected on the lower 8-bit of the card_clk_freq_selsignal. - * 10-bit Divided Clock Mode: - * 0x3FF : 1/2046 Divided clock - * .......... - * N : 1/2N Divided Clock - * .......... - * 0x002 : 1/4 Divided Clock - * 0x001 : 1/2 Divided Clock - * 0x000 : Base clock (10MHz - 255 MHz) - * Programmable Clock Mode : Enables the Host System to select a fine grain SD clock frequency: - * 0x3FF : Base clock * M /1024 - * .......... - * N-1 : Base clock * M /N - * .......... - * 0x002 : Base clock * M /3 - * 0x001 : Base clock * M /2 - * 0x000 : Base clock * M - */ -#define SDXC_SYS_CTRL_FREQ_SEL_MASK (0xFF00U) -#define SDXC_SYS_CTRL_FREQ_SEL_SHIFT (8U) -#define SDXC_SYS_CTRL_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_FREQ_SEL_MASK) -#define SDXC_SYS_CTRL_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_FREQ_SEL_SHIFT) - -/* - * UPPER_FREQ_SEL (RW) - * - * These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. - * The value is reflected on the upper 2 bits of the card_clk_freq_sel signal. - */ -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK (0xC0U) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT (6U) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) -#define SDXC_SYS_CTRL_UPPER_FREQ_SEL_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_UPPER_FREQ_SEL_MASK) >> SDXC_SYS_CTRL_UPPER_FREQ_SEL_SHIFT) - -/* - * CLK_GEN_SELECT (RW) - * - * Clock Generator Select - * This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. - * If Preset Value Enable = 0, this bit is set by the Host Driver. - * If Preset Value Enable = 1, this bit is automatically set to a value specified in one of the Preset Value registers. - * The value is reflected on the card_clk_gen_sel signal. - * Values: - * 0x0 (FALSE): Divided Clock Mode - * 0x1 (TRUE): Programmable Clock Mode - */ -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK (0x20U) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT (5U) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) -#define SDXC_SYS_CTRL_CLK_GEN_SELECT_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_CLK_GEN_SELECT_MASK) >> SDXC_SYS_CTRL_CLK_GEN_SELECT_SHIFT) - -/* - * PLL_ENABLE (RW) - * - * PLL Enable - * This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). - * When Host Version 4 Enable = 0, INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. - * Note: If this bit is not used to to active the PLL when Host Version 4 Enable = 1, it is recommended to set this bit to '1' . - * Values: - * 0x0 (FALSE): PLL is in low power mode - * 0x1 (TRUE): PLL is enabled - */ -#define SDXC_SYS_CTRL_PLL_ENABLE_MASK (0x8U) -#define SDXC_SYS_CTRL_PLL_ENABLE_SHIFT (3U) -#define SDXC_SYS_CTRL_PLL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) -#define SDXC_SYS_CTRL_PLL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_PLL_ENABLE_MASK) >> SDXC_SYS_CTRL_PLL_ENABLE_SHIFT) - -/* - * SD_CLK_EN (RW) - * - * SD/eMMC Clock Enable - * This bit stops the SDCLK or RCLK when set to 0. - * The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. - * The value is reflected on the clk2card_on pin. - * Values: - * 0x0 (FALSE): Disable providing SDCLK/RCLK - * 0x1 (TRUE): Enable providing SDCLK/RCLK - */ -#define SDXC_SYS_CTRL_SD_CLK_EN_MASK (0x4U) -#define SDXC_SYS_CTRL_SD_CLK_EN_SHIFT (2U) -#define SDXC_SYS_CTRL_SD_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) -#define SDXC_SYS_CTRL_SD_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_SD_CLK_EN_MASK) >> SDXC_SYS_CTRL_SD_CLK_EN_SHIFT) - -/* - * INTERNAL_CLK_STABLE (RW) - * - * Internal Clock Stable - * This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. - * This bit reflects the synchronized value of the intclk_stable signal after the Internal Clock Enable bit is set to 1, - * and also reflects the synchronized value of the card_clk_stable signal after the PLL Enable bit is set to 1. - * Values: - * 0x0 (FALSE): Not Ready - * 0x1 (TRUE): Ready - */ -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK (0x2U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT (1U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) -#define SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_STABLE_SHIFT) - -/* - * INTERNAL_CLK_EN (RW) - * - * Internal Clock Enable - * This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. - * The Host Controller must stop its internal clock to enter a very low power state. - * However, registers can still be read and written to. The value is reflected on the intclk_en signal. - * Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set this bit to '1' . - * Values: - * 0x0 (FALSE): Stop - * 0x1 (TRUE): Oscillate - */ -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK (0x1U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT (0U) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_SET(x) (((uint32_t)(x) << SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) -#define SDXC_SYS_CTRL_INTERNAL_CLK_EN_GET(x) (((uint32_t)(x) & SDXC_SYS_CTRL_INTERNAL_CLK_EN_MASK) >> SDXC_SYS_CTRL_INTERNAL_CLK_EN_SHIFT) - -/* Bitfield definition for register: INT_STAT */ -/* - * BOOT_ACK_ERR (R/W1C) - * - * Boot Acknowledgment Error - * This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. - * In SD/UHS-II mode, this bit is irrelevant. - */ -#define SDXC_INT_STAT_BOOT_ACK_ERR_MASK (0x10000000UL) -#define SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT (28U) -#define SDXC_INT_STAT_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) -#define SDXC_INT_STAT_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BOOT_ACK_ERR_MASK) >> SDXC_INT_STAT_BOOT_ACK_ERR_SHIFT) - -/* - * RESP_ERR (R/W1C) - * - * Response Error - * Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. - * If Response Error Check Enable is set to 1 in the Transfer Mode register, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1.This is applicable in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_RESP_ERR_MASK (0x8000000UL) -#define SDXC_INT_STAT_RESP_ERR_SHIFT (27U) -#define SDXC_INT_STAT_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_RESP_ERR_SHIFT) & SDXC_INT_STAT_RESP_ERR_MASK) -#define SDXC_INT_STAT_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RESP_ERR_MASK) >> SDXC_INT_STAT_RESP_ERR_SHIFT) - -/* - * TUNING_ERR (R/W1C) - * - * Tuning Error - * This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure - * (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register). - * By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. - * To reset tuning circuit, Sampling Clock Select is set to 0 before executing tuning procedure. - * The Tuning Error is higher priority than the other error interrupts generated during data transfer. - * By detecting Tuning Error, the Host Driver must discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from the tuning circuit error. - * This is applicable in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_TUNING_ERR_MASK (0x4000000UL) -#define SDXC_INT_STAT_TUNING_ERR_SHIFT (26U) -#define SDXC_INT_STAT_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_TUNING_ERR_SHIFT) & SDXC_INT_STAT_TUNING_ERR_MASK) -#define SDXC_INT_STAT_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_TUNING_ERR_MASK) >> SDXC_INT_STAT_TUNING_ERR_SHIFT) - -/* - * ADMA_ERR (R/W1C) - * - * ADMA Error - * This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: - * Error response received from System bus (Master I/F) - * ADMA3,ADMA2 Descriptors invalid - * CQE Task or Transfer descriptors invalid - * When the error occurs, the state of the ADMA is saved in the ADMA Error Status register. - * In eMMC CQE mode: - * The Host Controller generates this Interrupt when it detects an invalid descriptor data (Valid=0) at the ST_FDS state. - * ADMA Error State in the ADMA Error Status indicates that an error has occurred in ST_FDS state. - * The Host Driver may find that Valid bit is not set at the error descriptor. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_ADMA_ERR_MASK (0x2000000UL) -#define SDXC_INT_STAT_ADMA_ERR_SHIFT (25U) -#define SDXC_INT_STAT_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_ADMA_ERR_SHIFT) & SDXC_INT_STAT_ADMA_ERR_MASK) -#define SDXC_INT_STAT_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ADMA_ERR_MASK) >> SDXC_INT_STAT_ADMA_ERR_SHIFT) - -/* - * AUTO_CMD_ERR (R/W1C) - * - * Auto CMD Error - * This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. - * This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. - * D07 is effective in case of Auto CMD12. Auto CMD Error Status register is valid while this bit is set to 1 and may be cleared by clearing of this bit. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_AUTO_CMD_ERR_MASK (0x1000000UL) -#define SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT (24U) -#define SDXC_INT_STAT_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) -#define SDXC_INT_STAT_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_AUTO_CMD_ERR_MASK) >> SDXC_INT_STAT_AUTO_CMD_ERR_SHIFT) - -/* - * CUR_LMT_ERR (R/W1C) - * - * Current Limit Error - * By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested to supply power for the SD Bus. - * If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. - * A reading of 1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. - * A reading of 0 for this bit means that the Host Controller is supplying power and no error has occurred. - * The Host Controller may require some sampling time to detect the current limit. - * SDXC Host Controller does not support this function, this bit is always set to 0. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Power Fail - */ -#define SDXC_INT_STAT_CUR_LMT_ERR_MASK (0x800000UL) -#define SDXC_INT_STAT_CUR_LMT_ERR_SHIFT (23U) -#define SDXC_INT_STAT_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) -#define SDXC_INT_STAT_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CUR_LMT_ERR_MASK) >> SDXC_INT_STAT_CUR_LMT_ERR_SHIFT) - -/* - * DATA_END_BIT_ERR (R/W1C) - * - * Data End Bit Error - * This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_DATA_END_BIT_ERR_MASK (0x400000UL) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT (22U) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) -#define SDXC_INT_STAT_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_END_BIT_ERR_MASK) >> SDXC_INT_STAT_DATA_END_BIT_ERR_SHIFT) - -/* - * DATA_CRC_ERR (R/W1C) - * - * Data CRC Error - * This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line, - * when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_DATA_CRC_ERR_MASK (0x200000UL) -#define SDXC_INT_STAT_DATA_CRC_ERR_SHIFT (21U) -#define SDXC_INT_STAT_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) -#define SDXC_INT_STAT_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_CRC_ERR_MASK) >> SDXC_INT_STAT_DATA_CRC_ERR_SHIFT) - -/* - * DATA_TOUT_ERR (R/W1C) - * - * Data Timeout Error - * This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: - * Busy timeout for R1b, R5b type - * Busy timeout after Write CRC status - * Write CRC Status timeout - * Read Data timeout - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Time out - */ -#define SDXC_INT_STAT_DATA_TOUT_ERR_MASK (0x100000UL) -#define SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT (20U) -#define SDXC_INT_STAT_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) -#define SDXC_INT_STAT_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DATA_TOUT_ERR_MASK) >> SDXC_INT_STAT_DATA_TOUT_ERR_SHIFT) - -/* - * CMD_IDX_ERR (R/W1C) - * - * Command Index Error - * This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_CMD_IDX_ERR_MASK (0x80000UL) -#define SDXC_INT_STAT_CMD_IDX_ERR_SHIFT (19U) -#define SDXC_INT_STAT_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) -#define SDXC_INT_STAT_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_IDX_ERR_MASK) >> SDXC_INT_STAT_CMD_IDX_ERR_SHIFT) - -/* - * CMD_END_BIT_ERR (R/W1C) - * - * Command End Bit Error - * This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): End Bit error generated - */ -#define SDXC_INT_STAT_CMD_END_BIT_ERR_MASK (0x40000UL) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT (18U) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) -#define SDXC_INT_STAT_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_END_BIT_ERR_MASK) >> SDXC_INT_STAT_CMD_END_BIT_ERR_SHIFT) - -/* - * CMD_CRC_ERR (R/W1C) - * - * Command CRC Error - * Command CRC Error is generated in SD/eMMC mode for following two cases. - * If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout), this bit is set to 1 when detecting a CRC error in the command response. - * The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. - * If the Host Controller drives the CMD line to 1 level, - * but detects 0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 1. - * The Command Timeout Error is also set to 1 to distinguish a CMD line conflict. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): CRC error generated - */ -#define SDXC_INT_STAT_CMD_CRC_ERR_MASK (0x20000UL) -#define SDXC_INT_STAT_CMD_CRC_ERR_SHIFT (17U) -#define SDXC_INT_STAT_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) -#define SDXC_INT_STAT_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_CRC_ERR_MASK) >> SDXC_INT_STAT_CMD_CRC_ERR_SHIFT) - -/* - * CMD_TOUT_ERR (R/W1C) - * - * Command Timeout Error - * In SD/eMMC Mode,this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. - * If the Host Controller detects a CMD line conflict, along with Command CRC Error bit, this bit is set to 1, without waiting for 64 SD/eMMC card clock cycles. - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Time out - */ -#define SDXC_INT_STAT_CMD_TOUT_ERR_MASK (0x10000UL) -#define SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT (16U) -#define SDXC_INT_STAT_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) -#define SDXC_INT_STAT_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_TOUT_ERR_MASK) >> SDXC_INT_STAT_CMD_TOUT_ERR_SHIFT) - -/* - * ERR_INTERRUPT (RO) - * - * Error Interrupt - * If any of the bits in the Error Interrupt Status register are set, then this bit is set. - * Values: - * 0x0 (FALSE): No Error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_STAT_ERR_INTERRUPT_MASK (0x8000U) -#define SDXC_INT_STAT_ERR_INTERRUPT_SHIFT (15U) -#define SDXC_INT_STAT_ERR_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_ERR_INTERRUPT_MASK) >> SDXC_INT_STAT_ERR_INTERRUPT_SHIFT) - -/* - * CQE_EVENT (R/W1C) - * - * Command Queuing Event - * This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. - * Values: - * 0x0 (FALSE): No Event - * 0x1 (TRUE): Command Queuing Event is detected - */ -#define SDXC_INT_STAT_CQE_EVENT_MASK (0x4000U) -#define SDXC_INT_STAT_CQE_EVENT_SHIFT (14U) -#define SDXC_INT_STAT_CQE_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CQE_EVENT_SHIFT) & SDXC_INT_STAT_CQE_EVENT_MASK) -#define SDXC_INT_STAT_CQE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CQE_EVENT_MASK) >> SDXC_INT_STAT_CQE_EVENT_SHIFT) - -/* - * FX_EVENT (RO) - * - * FX Event - * This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. - * Values: - * 0x0 (FALSE): No Event - * 0x1 (TRUE): FX Event is detected - */ -#define SDXC_INT_STAT_FX_EVENT_MASK (0x2000U) -#define SDXC_INT_STAT_FX_EVENT_SHIFT (13U) -#define SDXC_INT_STAT_FX_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_FX_EVENT_MASK) >> SDXC_INT_STAT_FX_EVENT_SHIFT) - -/* - * RE_TUNE_EVENT (RO) - * - * Re-tuning Event - * This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported. - */ -#define SDXC_INT_STAT_RE_TUNE_EVENT_MASK (0x1000U) -#define SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT (12U) -#define SDXC_INT_STAT_RE_TUNE_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_RE_TUNE_EVENT_MASK) >> SDXC_INT_STAT_RE_TUNE_EVENT_SHIFT) - -/* - * CARD_INTERRUPT (RO) - * - * Card Interrupt - * This bit reflects the synchronized value of: - * DAT[1] Interrupt Input for SD Mode - * DAT[2] Interrupt Input for UHS-II Mode - * Values: - * 0x0 (FALSE): No Card Interrupt - * 0x1 (TRUE): Generate Card Interrupt - */ -#define SDXC_INT_STAT_CARD_INTERRUPT_MASK (0x100U) -#define SDXC_INT_STAT_CARD_INTERRUPT_SHIFT (8U) -#define SDXC_INT_STAT_CARD_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INTERRUPT_MASK) >> SDXC_INT_STAT_CARD_INTERRUPT_SHIFT) - -/* - * CARD_REMOVAL (R/W1C) - * - * Card Removal - * This bit is set if the Card Inserted in the Present State register changes from 1 to 0. - * Values: - * 0x0 (FALSE): Card state stable or Debouncing - * 0x1 (TRUE): Card Removed - */ -#define SDXC_INT_STAT_CARD_REMOVAL_MASK (0x80U) -#define SDXC_INT_STAT_CARD_REMOVAL_SHIFT (7U) -#define SDXC_INT_STAT_CARD_REMOVAL_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_REMOVAL_SHIFT) & SDXC_INT_STAT_CARD_REMOVAL_MASK) -#define SDXC_INT_STAT_CARD_REMOVAL_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_REMOVAL_MASK) >> SDXC_INT_STAT_CARD_REMOVAL_SHIFT) - -/* - * CARD_INSERTION (R/W1C) - * - * Card Insertion - * This bit is set if the Card Inserted in the Present State register changes from 0 to 1. - * Values: - * 0x0 (FALSE): Card state stable or Debouncing - * 0x1 (TRUE): Card Inserted - */ -#define SDXC_INT_STAT_CARD_INSERTION_MASK (0x40U) -#define SDXC_INT_STAT_CARD_INSERTION_SHIFT (6U) -#define SDXC_INT_STAT_CARD_INSERTION_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CARD_INSERTION_SHIFT) & SDXC_INT_STAT_CARD_INSERTION_MASK) -#define SDXC_INT_STAT_CARD_INSERTION_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CARD_INSERTION_MASK) >> SDXC_INT_STAT_CARD_INSERTION_SHIFT) - -/* - * BUF_RD_READY (R/W1C) - * - * Buffer Read Ready - * This bit is set if the Buffer Read Enable changes from 0 to 1. - * Values: - * 0x0 (FALSE): Not ready to read buffer - * 0x1 (TRUE): Ready to read buffer - */ -#define SDXC_INT_STAT_BUF_RD_READY_MASK (0x20U) -#define SDXC_INT_STAT_BUF_RD_READY_SHIFT (5U) -#define SDXC_INT_STAT_BUF_RD_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_RD_READY_SHIFT) & SDXC_INT_STAT_BUF_RD_READY_MASK) -#define SDXC_INT_STAT_BUF_RD_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_RD_READY_MASK) >> SDXC_INT_STAT_BUF_RD_READY_SHIFT) - -/* - * BUF_WR_READY (R/W1C) - * - * Buffer Write Ready - * This bit is set if the Buffer Write Enable changes from 0 to 1. - * Values: - * 0x0 (FALSE): Not ready to write buffer - * 0x1 (TRUE): Ready to write buffer - */ -#define SDXC_INT_STAT_BUF_WR_READY_MASK (0x10U) -#define SDXC_INT_STAT_BUF_WR_READY_SHIFT (4U) -#define SDXC_INT_STAT_BUF_WR_READY_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BUF_WR_READY_SHIFT) & SDXC_INT_STAT_BUF_WR_READY_MASK) -#define SDXC_INT_STAT_BUF_WR_READY_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BUF_WR_READY_MASK) >> SDXC_INT_STAT_BUF_WR_READY_SHIFT) - -/* - * DMA_INTERRUPT (R/W1C) - * - * DMA Interrupt - * This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. - * In case of ADMA, by setting the Int field in the descriptor table, the Host controller generates this interrupt. - * This interrupt is not generated after a Transfer Complete. - * Values: - * 0x0 (FALSE): No DMA Interrupt - * 0x1 (TRUE): DMA Interrupt is generated - */ -#define SDXC_INT_STAT_DMA_INTERRUPT_MASK (0x8U) -#define SDXC_INT_STAT_DMA_INTERRUPT_SHIFT (3U) -#define SDXC_INT_STAT_DMA_INTERRUPT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) -#define SDXC_INT_STAT_DMA_INTERRUPT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_DMA_INTERRUPT_MASK) >> SDXC_INT_STAT_DMA_INTERRUPT_SHIFT) - -/* - * BGAP_EVENT (R/W1C) - * - * Block Gap Event - * This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. - * Values: - * 0x0 (FALSE): No Block Gap Event - * 0x1 (TRUE): Transaction stopped at block gap - */ -#define SDXC_INT_STAT_BGAP_EVENT_MASK (0x4U) -#define SDXC_INT_STAT_BGAP_EVENT_SHIFT (2U) -#define SDXC_INT_STAT_BGAP_EVENT_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_BGAP_EVENT_SHIFT) & SDXC_INT_STAT_BGAP_EVENT_MASK) -#define SDXC_INT_STAT_BGAP_EVENT_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_BGAP_EVENT_MASK) >> SDXC_INT_STAT_BGAP_EVENT_SHIFT) - -/* - * XFER_COMPLETE (R/W1C) - * - * Transfer Complete - * This bit is set when a read/write transfer and a command with status busy is completed. - * Values: - * 0x0 (FALSE): Not complete - * 0x1 (TRUE): Command execution is completed - */ -#define SDXC_INT_STAT_XFER_COMPLETE_MASK (0x2U) -#define SDXC_INT_STAT_XFER_COMPLETE_SHIFT (1U) -#define SDXC_INT_STAT_XFER_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_XFER_COMPLETE_SHIFT) & SDXC_INT_STAT_XFER_COMPLETE_MASK) -#define SDXC_INT_STAT_XFER_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_XFER_COMPLETE_MASK) >> SDXC_INT_STAT_XFER_COMPLETE_SHIFT) - -/* - * CMD_COMPLETE (R/W1C) - * - * Command Complete - * In an SD/eMMC Mode, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. - * This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. - * Values: - * 0x0 (FALSE): No command complete - * 0x1 (TRUE): Command Complete - */ -#define SDXC_INT_STAT_CMD_COMPLETE_MASK (0x1U) -#define SDXC_INT_STAT_CMD_COMPLETE_SHIFT (0U) -#define SDXC_INT_STAT_CMD_COMPLETE_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_CMD_COMPLETE_SHIFT) & SDXC_INT_STAT_CMD_COMPLETE_MASK) -#define SDXC_INT_STAT_CMD_COMPLETE_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_CMD_COMPLETE_MASK) >> SDXC_INT_STAT_CMD_COMPLETE_SHIFT) - -/* Bitfield definition for register: INT_STAT_EN */ -/* - * BOOT_ACK_ERR_STAT_EN (RW) - * - * Boot Acknowledgment Error (eMMC Mode only) - * Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (INT_STAT). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK (0x10000000UL) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT (28U) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BOOT_ACK_ERR_STAT_EN_SHIFT) - -/* - * RESP_ERR_STAT_EN (RW) - * - * Response Error Status Enable (SD Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK (0x8000000UL) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT (27U) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RESP_ERR_STAT_EN_SHIFT) - -/* - * TUNING_ERR_STAT_EN (RW) - * - * Tuning Error Status Enable (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK (0x4000000UL) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT (26U) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_TUNING_ERR_STAT_EN_SHIFT) - -/* - * ADMA_ERR_STAT_EN (RW) - * - * ADMA Error Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK (0x2000000UL) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT (25U) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_ADMA_ERR_STAT_EN_SHIFT) - -/* - * AUTO_CMD_ERR_STAT_EN (RW) - * - * Auto CMD Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK (0x1000000UL) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT (24U) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_AUTO_CMD_ERR_STAT_EN_SHIFT) - -/* - * CUR_LMT_ERR_STAT_EN (RW) - * - * Current Limit Error Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK (0x800000UL) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT (23U) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CUR_LMT_ERR_STAT_EN_SHIFT) - -/* - * DATA_END_BIT_ERR_STAT_EN (RW) - * - * Data End Bit Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK (0x400000UL) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT (22U) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_END_BIT_ERR_STAT_EN_SHIFT) - -/* - * DATA_CRC_ERR_STAT_EN (RW) - * - * Data CRC Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK (0x200000UL) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT (21U) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_CRC_ERR_STAT_EN_SHIFT) - -/* - * DATA_TOUT_ERR_STAT_EN (RW) - * - * Data Timeout Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK (0x100000UL) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT (20U) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DATA_TOUT_ERR_STAT_EN_SHIFT) - -/* - * CMD_IDX_ERR_STAT_EN (RW) - * - * Command Index Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK (0x80000UL) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT (19U) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_IDX_ERR_STAT_EN_SHIFT) - -/* - * CMD_END_BIT_ERR_STAT_EN (RW) - * - * Command End Bit Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK (0x40000UL) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT (18U) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_END_BIT_ERR_STAT_EN_SHIFT) - -/* - * CMD_CRC_ERR_STAT_EN (RW) - * - * Command CRC Error Status Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK (0x20000UL) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT (17U) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_CRC_ERR_STAT_EN_SHIFT) - -/* - * CMD_TOUT_ERR_STAT_EN (RW) - * - * Command Timeout Error Status Enable (SD/eMMC Mode only). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK (0x10000UL) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT (16U) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_TOUT_ERR_STAT_EN_SHIFT) - -/* - * CQE_EVENT_STAT_EN (RW) - * - * CQE Event Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK (0x4000U) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT (14U) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CQE_EVENT_STAT_EN_SHIFT) - -/* - * FX_EVENT_STAT_EN (RW) - * - * FX Event Status Enable - * This bit is added from Version 4.10. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK (0x2000U) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT (13U) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_FX_EVENT_STAT_EN_SHIFT) - -/* - * RE_TUNE_EVENT_STAT_EN (RW) - * - * Re-Tuning Event (UHS-I only) Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK (0x1000U) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT (12U) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_RE_TUNE_EVENT_STAT_EN_SHIFT) - -/* - * CARD_INTERRUPT_STAT_EN (RW) - * - * Card Interrupt Status Enable - * If this bit is set to 0, the Host Controller clears the interrupt request to the System. - * The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. - * The Host Driver may clear the Card Interrupt Status Enable before servicing the Card Interrupt and may set this bit again after all interrupt requests from the card are cleared to prevent inadvertent interrupts. - * By setting this bit to 0, interrupt input must be masked by implementation so that the interrupt input is not affected by external signal in any state (for example, floating). - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK (0x100U) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT (8U) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INTERRUPT_STAT_EN_SHIFT) - -/* - * CARD_REMOVAL_STAT_EN (RW) - * - * Card Removal Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK (0x80U) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT (7U) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_REMOVAL_STAT_EN_SHIFT) - -/* - * CARD_INSERTION_STAT_EN (RW) - * - * Card Insertion Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK (0x40U) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT (6U) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CARD_INSERTION_STAT_EN_SHIFT) - -/* - * BUF_RD_READY_STAT_EN (RW) - * - * Buffer Read Ready Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK (0x20U) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT (5U) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_RD_READY_STAT_EN_SHIFT) - -/* - * BUF_WR_READY_STAT_EN (RW) - * - * Buffer Write Ready Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK (0x10U) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT (4U) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BUF_WR_READY_STAT_EN_SHIFT) - -/* - * DMA_INTERRUPT_STAT_EN (RW) - * - * DMA Interrupt Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK (0x8U) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT (3U) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_DMA_INTERRUPT_STAT_EN_SHIFT) - -/* - * BGAP_EVENT_STAT_EN (RW) - * - * Block Gap Event Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK (0x4U) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT (2U) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_MASK) >> SDXC_INT_STAT_EN_BGAP_EVENT_STAT_EN_SHIFT) - -/* - * XFER_COMPLETE_STAT_EN (RW) - * - * Transfer Complete Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK (0x2U) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT (1U) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_XFER_COMPLETE_STAT_EN_SHIFT) - -/* - * CMD_COMPLETE_STAT_EN (RW) - * - * Command Complete Status Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK (0x1U) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT (0U) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SET(x) (((uint32_t)(x) << SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) -#define SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_GET(x) (((uint32_t)(x) & SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_MASK) >> SDXC_INT_STAT_EN_CMD_COMPLETE_STAT_EN_SHIFT) - -/* Bitfield definition for register: INT_SIGNAL_EN */ -/* - * BOOT_ACK_ERR_SIGNAL_EN (RW) - * - * Boot Acknowledgment Error (eMMC Mode only). - * Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgment Error in Error Interrupt Status register is set. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK (0x10000000UL) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT (28U) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BOOT_ACK_ERR_SIGNAL_EN_SHIFT) - -/* - * RESP_ERR_SIGNAL_EN (RW) - * - * Response Error Signal Enable (SD Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK (0x8000000UL) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT (27U) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RESP_ERR_SIGNAL_EN_SHIFT) - -/* - * TUNING_ERR_SIGNAL_EN (RW) - * - * Tuning Error Signal Enable (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK (0x4000000UL) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT (26U) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_TUNING_ERR_SIGNAL_EN_SHIFT) - -/* - * ADMA_ERR_SIGNAL_EN (RW) - * - * ADMA Error Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK (0x2000000UL) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT (25U) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_ADMA_ERR_SIGNAL_EN_SHIFT) - -/* - * AUTO_CMD_ERR_SIGNAL_EN (RW) - * - * Auto CMD Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK (0x1000000UL) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT (24U) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_AUTO_CMD_ERR_SIGNAL_EN_SHIFT) - -/* - * CUR_LMT_ERR_SIGNAL_EN (RW) - * - * Current Limit Error Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK (0x800000UL) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT (23U) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CUR_LMT_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_END_BIT_ERR_SIGNAL_EN (RW) - * - * Data End Bit Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK (0x400000UL) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT (22U) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_END_BIT_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_CRC_ERR_SIGNAL_EN (RW) - * - * Data CRC Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK (0x200000UL) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT (21U) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_CRC_ERR_SIGNAL_EN_SHIFT) - -/* - * DATA_TOUT_ERR_SIGNAL_EN (RW) - * - * Data Timeout Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK (0x100000UL) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT (20U) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DATA_TOUT_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_IDX_ERR_SIGNAL_EN (RW) - * - * Command Index Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): No error - * 0x1 (TRUE): Error - */ -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK (0x80000UL) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT (19U) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_IDX_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_END_BIT_ERR_SIGNAL_EN (RW) - * - * Command End Bit Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK (0x40000UL) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT (18U) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_END_BIT_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_CRC_ERR_SIGNAL_EN (RW) - * - * Command CRC Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK (0x20000UL) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT (17U) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_CRC_ERR_SIGNAL_EN_SHIFT) - -/* - * CMD_TOUT_ERR_SIGNAL_EN (RW) - * - * Command Timeout Error Signal Enable (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK (0x10000UL) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT (16U) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_TOUT_ERR_SIGNAL_EN_SHIFT) - -/* - * CQE_EVENT_SIGNAL_EN (RW) - * - * Command Queuing Engine Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK (0x4000U) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT (14U) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CQE_EVENT_SIGNAL_EN_SHIFT) - -/* - * FX_EVENT_SIGNAL_EN (RW) - * - * FX Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK (0x2000U) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT (13U) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_FX_EVENT_SIGNAL_EN_SHIFT) - -/* - * RE_TUNE_EVENT_SIGNAL_EN (RW) - * - * Re-Tuning Event (UHS-I only) Signal Enable. - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK (0x1000U) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT (12U) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_RE_TUNE_EVENT_SIGNAL_EN_SHIFT) - -/* - * CARD_INTERRUPT_SIGNAL_EN (RW) - * - * Card Interrupt Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK (0x100U) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT (8U) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INTERRUPT_SIGNAL_EN_SHIFT) - -/* - * CARD_REMOVAL_SIGNAL_EN (RW) - * - * Card Removal Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK (0x80U) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT (7U) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_REMOVAL_SIGNAL_EN_SHIFT) - -/* - * CARD_INSERTION_SIGNAL_EN (RW) - * - * Card Insertion Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK (0x40U) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT (6U) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CARD_INSERTION_SIGNAL_EN_SHIFT) - -/* - * BUF_RD_READY_SIGNAL_EN (RW) - * - * Buffer Read Ready Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK (0x20U) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT (5U) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_RD_READY_SIGNAL_EN_SHIFT) - -/* - * BUF_WR_READY_SIGNAL_EN (RW) - * - * Buffer Write Ready Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK (0x10U) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT (4U) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BUF_WR_READY_SIGNAL_EN_SHIFT) - -/* - * DMA_INTERRUPT_SIGNAL_EN (RW) - * - * DMA Interrupt Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK (0x8U) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT (3U) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_DMA_INTERRUPT_SIGNAL_EN_SHIFT) - -/* - * BGAP_EVENT_SIGNAL_EN (RW) - * - * Block Gap Event Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK (0x4U) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT (2U) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_BGAP_EVENT_SIGNAL_EN_SHIFT) - -/* - * XFER_COMPLETE_SIGNAL_EN (RW) - * - * Transfer Complete Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK (0x2U) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT (1U) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_XFER_COMPLETE_SIGNAL_EN_SHIFT) - -/* - * CMD_COMPLETE_SIGNAL_EN (RW) - * - * Command Complete Signal Enable - * Values: - * 0x0 (FALSE): Masked - * 0x1 (TRUE): Enabled - */ -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK (0x1U) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT (0U) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SET(x) (((uint32_t)(x) << SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) -#define SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_GET(x) (((uint32_t)(x) & SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_MASK) >> SDXC_INT_SIGNAL_EN_CMD_COMPLETE_SIGNAL_EN_SHIFT) - -/* Bitfield definition for register: AC_HOST_CTRL */ -/* - * PRESET_VAL_ENABLE (RW) - * - * Preset Value Enable - * This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. - * When Preset Value Enable is set, SDCLK frequency generation (Frequency Select and Clock Generator Select) and the driver strength selection are performed by the controller. - * These values are selected from set of Preset Value registers based on selected speed mode. - * Values: - * 0x0 (FALSE): SDCLK and Driver Strength are controlled by Host Driver - * 0x1 (TRUE): Automatic Selection by Preset Value are Enabled - */ -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK (0x80000000UL) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT (31U) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_PRESET_VAL_ENABLE_SHIFT) - -/* - * ASYNC_INT_ENABLE (RW) - * - * Asynchronous Interrupt Enable - * This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. - * Values: - * 0x0 (FALSE): Disabled - * 0x1 (TRUE): Enabled - */ -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK (0x40000000UL) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT (30U) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_ASYNC_INT_ENABLE_SHIFT) - -/* - * HOST_VER4_ENABLE (RW) - * - * Host Version 4 Enable - * This bit selects either Version 3.00 compatible mode or Version 4 mode. - * Functions of following fields are modified for Host Version 4 mode: - * SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA System Address register (003h-000h) - * ADMA2/ADMA3 selection: ADMA3 is selected by DMA select in Host Control 1 register - * 64-bit ADMA Descriptor Size: 128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1 - * Selection of 32-bit/64-bit System Addressing: Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register - * 32-bit Block Count: SDMA System Address register (003h-000h) is modified to 32-bit Block Count register - * Note: It is recommended not to program ADMA3 Integrated Descriptor Address registers, - * UHS-II registers and Command Queuing registers (if applicable) while operating in Host version less than 4 mode (Host Version 4 Enable = 0). - * Values: - * 0x0 (FALSE): Version 3.00 compatible mode - * 0x1 (TRUE): Version 4 mode - */ -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK (0x10000000UL) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT (28U) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_HOST_VER4_ENABLE_SHIFT) - -/* - * CMD23_ENABLE (RW) - * - * CMD23 Enable - * If the card supports CMD23, this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. - * Values: - * 0x0 (FALSE): Auto CMD23 is disabled - * 0x1 (TRUE): Auto CMD23 is enabled - */ -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK (0x8000000UL) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT (27U) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) -#define SDXC_AC_HOST_CTRL_CMD23_ENABLE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD23_ENABLE_MASK) >> SDXC_AC_HOST_CTRL_CMD23_ENABLE_SHIFT) - -/* - * ADMA2_LEN_MODE (RW) - * - * ADMA2 Length Mode - * This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. - * Values: - * 0x0 (FALSE): 16-bit Data Length Mode - * 0x1 (TRUE): 26-bit Data Length Mode - */ -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK (0x4000000UL) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT (26U) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) -#define SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_MASK) >> SDXC_AC_HOST_CTRL_ADMA2_LEN_MODE_SHIFT) - -/* - * SAMPLE_CLK_SEL (RW) - * - * Sampling Clock Select - * This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. - * This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is cleared). - * Setting this bit to 1 means that tuning is completed successfully and setting this bit to 0 means that tuning has failed. - * The value is reflected on the sample_cclk_sel pin. - * Values: - * 0x0 (FALSE): Fixed clock is used to sample data - * 0x1 (TRUE): Tuned clock is used to sample data - */ -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK (0x800000UL) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT (23U) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) -#define SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_MASK) >> SDXC_AC_HOST_CTRL_SAMPLE_CLK_SEL_SHIFT) - -/* - * EXEC_TUNING (RW) - * - * Execute Tuning - * This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. - * Values: - * 0x0 (FALSE): Not Tuned or Tuning completed - * 0x1 (TRUE): Execute Tuning - */ -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK (0x400000UL) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT (22U) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) -#define SDXC_AC_HOST_CTRL_EXEC_TUNING_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_EXEC_TUNING_MASK) >> SDXC_AC_HOST_CTRL_EXEC_TUNING_SHIFT) - -/* - * SIGNALING_EN (RW) - * - * 1.8V Signaling Enable - * This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. - * Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. - * Host Controller clears this bit if switching to 1.8 signaling fails. The value is reflected on the uhs1_swvolt_en pin. - * Note: This bit must be set for all UHS-I speed modes (SDR12/SDR25/SDR50/SDR104/DDR50). - * Values: - * 0x0 (V_3_3): 3.3V Signalling - * 0x1 (V_1_8): 1.8V Signalling - */ -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK (0x80000UL) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT (19U) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) -#define SDXC_AC_HOST_CTRL_SIGNALING_EN_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_SIGNALING_EN_MASK) >> SDXC_AC_HOST_CTRL_SIGNALING_EN_SHIFT) - -/* - * UHS_MODE_SEL (RW) - * - * UHS Mode/eMMC Speed Mode Select - * These bits are used to select UHS mode in the SD mode of operation. In eMMC mode, these bits are used to select eMMC Speed mode. - * UHS Mode (SD/UHS-II mode only): - * 0x0 (SDR12): SDR12/Legacy - * 0x1 (SDR25): SDR25/High Speed SDR - * 0x2 (SDR50): SDR50 - * 0x3 (SDR104): SDR104/HS200 - * 0x4 (DDR50): DDR50/High Speed DDR - * 0x5 (RSVD5): Reserved - * 0x6 (RSVD6): Reserved - * 0x7 (UHS2): UHS-II/HS400 - * eMMC Speed Mode (eMMC mode only): - * 0x0: Legacy - * 0x1: High Speed SDR - * 0x2: Reserved - * 0x3: HS200 - * 0x4: High Speed DDR - * 0x5: Reserved - * 0x6: Reserved - * 0x7: HS400 - */ -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK (0x70000UL) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT (16U) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SET(x) (((uint32_t)(x) << SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) -#define SDXC_AC_HOST_CTRL_UHS_MODE_SEL_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_UHS_MODE_SEL_MASK) >> SDXC_AC_HOST_CTRL_UHS_MODE_SEL_SHIFT) - -/* - * CMD_NOT_ISSUED_AUTO_CMD12 (RO) - * - * Command Not Issued By Auto CMD12 Error - * If this bit is set to 1, CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. - * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. - * Values: - * 0x1 (TRUE): Not Issued - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) -#define SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_AC_HOST_CTRL_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) - -/* - * AUTO_CMD_RESP_ERR (RO) - * - * Auto CMD Response Error - * This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. - * This status is ignored if any bit between D00 to D04 is set to 1. - * Values: - * 0x1 (TRUE): Error - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK (0x20U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT (5U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_RESP_ERR_SHIFT) - -/* - * AUTO_CMD_IDX_ERR (RO) - * - * Auto CMD Index Error - * This bit is set if the command index error occurs in response to a command. - * Values: - * 0x1 (TRUE): Error - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK (0x10U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT (4U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_IDX_ERR_SHIFT) - -/* - * AUTO_CMD_EBIT_ERR (RO) - * - * Auto CMD End Bit Error - * This bit is set when detecting that the end bit of command response is 0. - * Values: - * 0x1 (TRUE): End Bit Error Generated - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK (0x8U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT (3U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_EBIT_ERR_SHIFT) - -/* - * AUTO_CMD_CRC_ERR (RO) - * - * Auto CMD CRC Error - * This bit is set when detecting a CRC error in the command response. - * Values: - * 0x1 (TRUE): CRC Error Generated - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK (0x4U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT (2U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_CRC_ERR_SHIFT) - -/* - * AUTO_CMD_TOUT_ERR (RO) - * - * Auto CMD Timeout Error - * This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. - * If this bit is set to 1, error status bits (D04-D01) are meaningless. - * Values: - * 0x1 (TRUE): Time out - * 0x0 (FALSE): No Error - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK (0x2U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT (1U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD_TOUT_ERR_SHIFT) - -/* - * AUTO_CMD12_NOT_EXEC (RO) - * - * Auto CMD12 Not Executed - * If multiple memory block data transfer is not started due to a command error, this bit is not set because it is not necessary to issue an Auto CMD12. - * Setting this bit to 1 means that the Host Controller cannot issue Auto CMD12 to stop multiple memory block data transfer, due to some error. - * If this bit is set to 1, error status bits (D04-D01) is meaningless. - * This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. - * Values: - * 0x1 (TRUE): Not Executed - * 0x0 (FALSE): Executed - */ -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK (0x1U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT (0U) -#define SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_AC_HOST_CTRL_AUTO_CMD12_NOT_EXEC_SHIFT) - -/* Bitfield definition for register: CAPABILITIES1 */ -/* - * SLOT_TYPE_R (RO) - * - * Slot Type - * These bits indicate usage of a slot by a specific Host System. - * Values: - * 0x0 (REMOVABLE_SLOT): Removable Card Slot - * 0x1 (EMBEDDED_SLOT): Embedded Slot for one Device - * 0x2 (SHARED_SLOT): Shared Bus Slot (SD mode) - * 0x3 (UHS2_EMBEDDED_SLOT): UHS-II Multiple Embedded Devices - */ -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK (0xC0000000UL) -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT (30U) -#define SDXC_CAPABILITIES1_SLOT_TYPE_R_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SLOT_TYPE_R_MASK) >> SDXC_CAPABILITIES1_SLOT_TYPE_R_SHIFT) - -/* - * ASYNC_INT_SUPPORT (RO) - * - * Asynchronous Interrupt Support (SD Mode only) - * Values: - * 0x0 (FALSE): Asynchronous Interrupt Not Supported - * 0x1 (TRUE): Asynchronous Interrupt Supported - */ -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK (0x20000000UL) -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT (29U) -#define SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ASYNC_INT_SUPPORT_SHIFT) - -/* - * VOLT_18 (RO) - * - * Voltage Support for 1.8V - * Values: - * 0x0 (FALSE): 1.8V Not Supported - * 0x1 (TRUE): 1.8V Supported - */ -#define SDXC_CAPABILITIES1_VOLT_18_MASK (0x4000000UL) -#define SDXC_CAPABILITIES1_VOLT_18_SHIFT (26U) -#define SDXC_CAPABILITIES1_VOLT_18_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_18_MASK) >> SDXC_CAPABILITIES1_VOLT_18_SHIFT) - -/* - * VOLT_30 (RO) - * - * Voltage Support for SD 3.0V or Embedded 1.2V - * Values: - * 0x0 (FALSE): SD 3.0V or Embedded 1.2V Not Supported - * 0x1 (TRUE): SD 3.0V or Embedded Supported - */ -#define SDXC_CAPABILITIES1_VOLT_30_MASK (0x2000000UL) -#define SDXC_CAPABILITIES1_VOLT_30_SHIFT (25U) -#define SDXC_CAPABILITIES1_VOLT_30_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_30_MASK) >> SDXC_CAPABILITIES1_VOLT_30_SHIFT) - -/* - * VOLT_33 (RO) - * - * Voltage Support for 3.3V - * Values: - * 0x0 (FALSE): 3.3V Not Supported - * 0x1 (TRUE): 3.3V Supported - */ -#define SDXC_CAPABILITIES1_VOLT_33_MASK (0x1000000UL) -#define SDXC_CAPABILITIES1_VOLT_33_SHIFT (24U) -#define SDXC_CAPABILITIES1_VOLT_33_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_VOLT_33_MASK) >> SDXC_CAPABILITIES1_VOLT_33_SHIFT) - -/* - * SUS_RES_SUPPORT (RO) - * - * Suspense/Resume Support - * This bit indicates whether the Host Controller supports Suspend/Resume functionality. - * If this bit is 0, the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is not supported. - * Values: - * 0x0 (FALSE): Not Supported - * 0x1 (TRUE): Supported - */ -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK (0x800000UL) -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT (23U) -#define SDXC_CAPABILITIES1_SUS_RES_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SUS_RES_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SUS_RES_SUPPORT_SHIFT) - -/* - * SDMA_SUPPORT (RO) - * - * SDMA Support - * This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. - * Values: - * 0x0 (FALSE): SDMA not Supported - * 0x1 (TRUE): SDMA Supported - */ -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK (0x400000UL) -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT (22U) -#define SDXC_CAPABILITIES1_SDMA_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_SDMA_SUPPORT_MASK) >> SDXC_CAPABILITIES1_SDMA_SUPPORT_SHIFT) - -/* - * HIGH_SPEED_SUPPORT (RO) - * - * High Speed Support - * This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. - * Values: - * 0x0 (FALSE): High Speed not Supported - * 0x1 (TRUE): High Speed Supported - */ -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK (0x200000UL) -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT (21U) -#define SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_MASK) >> SDXC_CAPABILITIES1_HIGH_SPEED_SUPPORT_SHIFT) - -/* - * ADMA2_SUPPORT (RO) - * - * ADMA2 Support - * This bit indicates whether the Host Controller is capable of using ADMA2. - * Values: - * 0x0 (FALSE): ADMA2 not Supported - * 0x1 (TRUE): ADMA2 Supported - */ -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK (0x80000UL) -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT (19U) -#define SDXC_CAPABILITIES1_ADMA2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_ADMA2_SUPPORT_MASK) >> SDXC_CAPABILITIES1_ADMA2_SUPPORT_SHIFT) - -/* - * EMBEDDED_8_BIT (RO) - * - * 8-bit Support for Embedded Device - * This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. - * Values: - * 0x0 (FALSE): 8-bit Bus Width not Supported - * 0x1 (TRUE): 8-bit Bus Width Supported - */ -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK (0x40000UL) -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT (18U) -#define SDXC_CAPABILITIES1_EMBEDDED_8_BIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_EMBEDDED_8_BIT_MASK) >> SDXC_CAPABILITIES1_EMBEDDED_8_BIT_SHIFT) - -/* - * MAX_BLK_LEN (RO) - * - * Maximum Block Length - * This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. - * The buffer transfers this block size without wait cycles. The transfer block length is always 512 bytes for the SD Memory irrespective of this bit - * Values: - * 0x0 (ZERO): 512 Byte - * 0x1 (ONE): 1024 Byte - * 0x2 (TWO): 2048 Byte - * 0x3 (THREE): Reserved - */ -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK (0x30000UL) -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT (16U) -#define SDXC_CAPABILITIES1_MAX_BLK_LEN_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_MAX_BLK_LEN_MASK) >> SDXC_CAPABILITIES1_MAX_BLK_LEN_SHIFT) - -/* - * BASE_CLK_FREQ (RO) - * - * Base Clock Frequency for SD clock - * These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. - * 6-Bit Base Clock Frequency: This mode is supported by the Host Controller version 1.00 and 2.00. - * The upper 2 bits are not effective and are always 0. The unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz. - * -0x00 : Get information through another method - * -0x01 : 1 MHz - * -0x02 : 2 MHz - * -............. - * -0x3F : 63 MHz - * -0x40-0xFF : Not Supported - * 8-Bit Base Clock Frequency: This mode is supported by the Host Controller version 3.00. The unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz. - * -0x00 : Get information through another method - * -0x01 : 1 MHz - * -0x02 : 2 MHz - * -............ - * -0xFF : 255 MHz - * If the frequency is 16.5 MHz, the larger value is set to 0001001b (17 MHz) because the Host Driver uses this value to calculate the clock divider value and it does not exceed the upper limit of the SD Clock frequency. - * If these bits are all 0, the Host system has to get information using a different method. - */ -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK (0xFF00U) -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT (8U) -#define SDXC_CAPABILITIES1_BASE_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_BASE_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_BASE_CLK_FREQ_SHIFT) - -/* - * TOUT_CLK_UNIT (RO) - * - * Timeout Clock Unit - * This bit shows the unit of base clock frequency used to detect Data TImeout Error. - * Values: - * 0x0 (KHZ): KHz - * 0x1 (MHZ): MHz - */ -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK (0x80U) -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT (7U) -#define SDXC_CAPABILITIES1_TOUT_CLK_UNIT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_UNIT_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_UNIT_SHIFT) - -/* - * TOUT_CLK_FREQ (RO) - * - * Timeout Clock Frequency - * This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. - * 0x00 : Get information through another method - * 0x01 : 1KHz / 1MHz - * 0x02 : 2KHz / 2MHz - * 0x03 : 3KHz / 3MHz - * ........... - * 0x3F : 63KHz / 63MHz - */ -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK (0x3FU) -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT (0U) -#define SDXC_CAPABILITIES1_TOUT_CLK_FREQ_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES1_TOUT_CLK_FREQ_MASK) >> SDXC_CAPABILITIES1_TOUT_CLK_FREQ_SHIFT) - -/* Bitfield definition for register: CAPABILITIES2 */ -/* - * VDD2_18V_SUPPORT (RO) - * - * 1.8V VDD2 Support - * This bit indicates support of VDD2 for the Host System. - * 0x0 (FALSE): 1.8V VDD2 is not Supported - * 0x1 (TRUE): 1.8V VDD2 is Supported - */ -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK (0x10000000UL) -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT (28U) -#define SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_MASK) >> SDXC_CAPABILITIES2_VDD2_18V_SUPPORT_SHIFT) - -/* - * ADMA3_SUPPORT (RO) - * - * ADMA3 Support - * This bit indicates whether the Host Controller is capable of using ADMA3. - * Values: - * 0x0 (FALSE): ADMA3 not Supported - * 0x1 (TRUE): ADMA3 Supported - */ -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK (0x8000000UL) -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT (27U) -#define SDXC_CAPABILITIES2_ADMA3_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_ADMA3_SUPPORT_MASK) >> SDXC_CAPABILITIES2_ADMA3_SUPPORT_SHIFT) - -/* - * CLK_MUL (RO) - * - * Clock Multiplier - * These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. - * 0x0: Clock Multiplier is not Supported - * 0x1: Clock Multiplier M = 2 - * 0x2: Clock Multiplier M = 3 - * ......... - * 0xFF: Clock Multiplier M = 256 - */ -#define SDXC_CAPABILITIES2_CLK_MUL_MASK (0xFF0000UL) -#define SDXC_CAPABILITIES2_CLK_MUL_SHIFT (16U) -#define SDXC_CAPABILITIES2_CLK_MUL_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_CLK_MUL_MASK) >> SDXC_CAPABILITIES2_CLK_MUL_SHIFT) - -/* - * RE_TUNING_MODES (RO) - * - * Re-Tuning Modes (UHS-I only) - * These bits select the re-tuning method and limit the maximum data length. - * Values: - * 0x0 (MODE1): Timer - * 0x1 (MODE2): Timer and Re-Tuning Request (Not supported) - * 0x2 (MODE3): Auto Re-Tuning (for transfer) - * 0x3 (RSVD_MODE): Reserved - */ -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK (0xC000U) -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT (14U) -#define SDXC_CAPABILITIES2_RE_TUNING_MODES_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RE_TUNING_MODES_MASK) >> SDXC_CAPABILITIES2_RE_TUNING_MODES_SHIFT) - -/* - * USE_TUNING_SDR50 (RO) - * - * Use Tuning for SDR50 (UHS-I only) - * Values: - * 0x0 (ZERO): SDR50 does not require tuning - * 0x1 (ONE): SDR50 requires tuning - */ -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK (0x2000U) -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT (13U) -#define SDXC_CAPABILITIES2_USE_TUNING_SDR50_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_USE_TUNING_SDR50_MASK) >> SDXC_CAPABILITIES2_USE_TUNING_SDR50_SHIFT) - -/* - * RETUNE_CNT (RO) - * - * Timer Count for Re-Tuning (UHS-I only) - * 0x0: Re-Tuning Timer disabled - * 0x1: 1 seconds - * 0x2: 2 seconds - * 0x3: 4 seconds - * ........ - * 0xB: 1024 seconds - * 0xC: Reserved - * 0xD: Reserved - * 0xE: Reserved - * 0xF: Get information from other source - */ -#define SDXC_CAPABILITIES2_RETUNE_CNT_MASK (0xF00U) -#define SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT (8U) -#define SDXC_CAPABILITIES2_RETUNE_CNT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_RETUNE_CNT_MASK) >> SDXC_CAPABILITIES2_RETUNE_CNT_SHIFT) - -/* - * DRV_TYPED (RO) - * - * Driver Type D Support (UHS-I only) - * This bit indicates support of Driver Type D for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type D is not supported - * 0x1 (TRUE): Driver Type D is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPED_MASK (0x40U) -#define SDXC_CAPABILITIES2_DRV_TYPED_SHIFT (6U) -#define SDXC_CAPABILITIES2_DRV_TYPED_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPED_MASK) >> SDXC_CAPABILITIES2_DRV_TYPED_SHIFT) - -/* - * DRV_TYPEC (RO) - * - * Driver Type C Support (UHS-I only) - * This bit indicates support of Driver Type C for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type C is not supported - * 0x1 (TRUE): Driver Type C is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPEC_MASK (0x20U) -#define SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT (5U) -#define SDXC_CAPABILITIES2_DRV_TYPEC_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEC_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEC_SHIFT) - -/* - * DRV_TYPEA (RO) - * - * Driver Type A Support (UHS-I only) - * This bit indicates support of Driver Type A for 1.8 Signaling. - * Values: - * 0x0 (FALSE): Driver Type A is not supported - * 0x1 (TRUE): Driver Type A is supported - */ -#define SDXC_CAPABILITIES2_DRV_TYPEA_MASK (0x10U) -#define SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT (4U) -#define SDXC_CAPABILITIES2_DRV_TYPEA_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DRV_TYPEA_MASK) >> SDXC_CAPABILITIES2_DRV_TYPEA_SHIFT) - -/* - * UHS2_SUPPORT (RO) - * - * UHS-II Support (UHS-II only) - * This bit indicates whether Host Controller supports UHS-II. - * Values: - * 0x0 (FALSE): UHS-II is not supported - * 0x1 (TRUE): UHS-II is supported - */ -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK (0x8U) -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT (3U) -#define SDXC_CAPABILITIES2_UHS2_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_UHS2_SUPPORT_MASK) >> SDXC_CAPABILITIES2_UHS2_SUPPORT_SHIFT) - -/* - * DDR50_SUPPORT (RO) - * - * DDR50 Support (UHS-I only) - * Values: - * 0x0 (FALSE): DDR50 is not supported - * 0x1 (TRUE): DDR50 is supported - */ -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK (0x4U) -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT (2U) -#define SDXC_CAPABILITIES2_DDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_DDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_DDR50_SUPPORT_SHIFT) - -/* - * SDR104_SUPPORT (RO) - * - * SDR104 Support (UHS-I only) - * This bit mentions that SDR104 requires tuning. - * Values: - * 0x0 (FALSE): SDR104 is not supported - * 0x1 (TRUE): SDR104 is supported - */ -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK (0x2U) -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT (1U) -#define SDXC_CAPABILITIES2_SDR104_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR104_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR104_SUPPORT_SHIFT) - -/* - * SDR50_SUPPORT (RO) - * - * SDR50 Support (UHS-I only) - * This bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. - * Values: - * 0x0 (FALSE): SDR50 is not supported - * 0x1 (TRUE): SDR50 is supported - */ -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK (0x1U) -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT (0U) -#define SDXC_CAPABILITIES2_SDR50_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CAPABILITIES2_SDR50_SUPPORT_MASK) >> SDXC_CAPABILITIES2_SDR50_SUPPORT_SHIFT) - -/* Bitfield definition for register: CURR_CAPABILITIES1 */ -/* - * MAX_CUR_18V (RO) - * - * Maximum Current for 1.8V - * This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK (0xFF0000UL) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT (16U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_18V_SHIFT) - -/* - * MAX_CUR_30V (RO) - * - * Maximum Current for 3.0V - * This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK (0xFF00U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT (8U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_30V_SHIFT) - -/* - * MAX_CUR_33V (RO) - * - * Maximum Current for 3.3V - * This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK (0xFFU) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT (0U) -#define SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_MASK) >> SDXC_CURR_CAPABILITIES1_MAX_CUR_33V_SHIFT) - -/* Bitfield definition for register: CURR_CAPABILITIES2 */ -/* - * MAX_CUR_VDD2_18V (RO) - * - * Maximum Current for 1.8V VDD2 - * This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. - * 0: Get information through another method - * 1: 4mA - * 2: 8mA - * 3: 13mA - * ....... - * 255: 1020mA - */ -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK (0xFFU) -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT (0U) -#define SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_GET(x) (((uint32_t)(x) & SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_MASK) >> SDXC_CURR_CAPABILITIES2_MAX_CUR_VDD2_18V_SHIFT) - -/* Bitfield definition for register: FORCE_EVENT */ -/* - * FORCE_BOOT_ACK_ERR (WO) - * - * Force Event for Boot Ack error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Boot ack Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK (0x10000000UL) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT (28U) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_BOOT_ACK_ERR_SHIFT) - -/* - * FORCE_RESP_ERR (WO) - * - * Force Event for Response Error (SD Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Response Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK (0x8000000UL) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT (27U) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_RESP_ERR_SHIFT) - -/* - * FORCE_TUNING_ERR (WO) - * - * Force Event for Tuning Error (UHS-I Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Tuning Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK (0x4000000UL) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT (26U) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_TUNING_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_TUNING_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_TUNING_ERR_SHIFT) - -/* - * FORCE_ADMA_ERR (WO) - * - * Force Event for ADMA Error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): ADMA Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK (0x2000000UL) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT (25U) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_ADMA_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_ADMA_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_ADMA_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_ERR (WO) - * - * Force Event for Auto CMD Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Auto CMD Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK (0x1000000UL) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT (24U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_ERR_SHIFT) - -/* - * FORCE_CUR_LMT_ERR (WO) - * - * Force Event for Current Limit Error - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Current Limit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK (0x800000UL) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT (23U) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CUR_LMT_ERR_SHIFT) - -/* - * FORCE_DATA_END_BIT_ERR (WO) - * - * Force Event for Data End Bit Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data End Bit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK (0x400000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT (22U) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_END_BIT_ERR_SHIFT) - -/* - * FORCE_DATA_CRC_ERR (WO) - * - * Force Event for Data CRC Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data CRC Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK (0x200000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT (21U) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_CRC_ERR_SHIFT) - -/* - * FORCE_DATA_TOUT_ERR (WO) - * - * Force Event for Data Timeout Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Data Timeout Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK (0x100000UL) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT (20U) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_DATA_TOUT_ERR_SHIFT) - -/* - * FORCE_CMD_IDX_ERR (WO) - * - * Force Event for Command Index Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command Index Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK (0x80000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT (19U) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_IDX_ERR_SHIFT) - -/* - * FORCE_CMD_END_BIT_ERR (WO) - * - * Force Event for Command End Bit Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command End Bit Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK (0x40000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT (18U) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_END_BIT_ERR_SHIFT) - -/* - * FORCE_CMD_CRC_ERR (WO) - * - * Force Event for Command CRC Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command CRC Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK (0x20000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT (17U) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_CRC_ERR_SHIFT) - -/* - * FORCE_CMD_TOUT_ERR (WO) - * - * Force Event for Command Timeout Error (SD/eMMC Mode only) - * Values: - * 0x0 (FALSE): Not Affected - * 0x1 (TRUE): Command Timeout Error Status is set - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK (0x10000UL) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT (16U) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_TOUT_ERR_SHIFT) - -/* - * FORCE_CMD_NOT_ISSUED_AUTO_CMD12 (WO) - * - * Force Event for Command Not Issued By Auto CMD12 Error - * Values: - * 0x1 (TRUE): Command Not Issued By Auto CMD12 Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK (0x80U) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT (7U) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) -#define SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_MASK) >> SDXC_FORCE_EVENT_FORCE_CMD_NOT_ISSUED_AUTO_CMD12_SHIFT) - -/* - * FORCE_AUTO_CMD_RESP_ERR (WO) - * - * Force Event for Auto CMD Response Error - * Values: - * 0x1 (TRUE): Auto CMD Response Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK (0x20U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT (5U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_RESP_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_IDX_ERR (WO) - * - * Force Event for Auto CMD Index Error - * Values: - * 0x1 (TRUE): Auto CMD Index Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK (0x10U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT (4U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_IDX_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_EBIT_ERR (WO) - * - * Force Event for Auto CMD End Bit Error - * Values: - * 0x1 (TRUE): Auto CMD End Bit Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK (0x8U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT (3U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_EBIT_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_CRC_ERR (WO) - * - * Force Event for Auto CMD CRC Error - * Values: - * 0x1 (TRUE): Auto CMD CRC Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK (0x4U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT (2U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_CRC_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD_TOUT_ERR (WO) - * - * Force Event for Auto CMD Timeout Error - * Values: - * 0x1 (TRUE): Auto CMD Timeout Error Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK (0x2U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT (1U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD_TOUT_ERR_SHIFT) - -/* - * FORCE_AUTO_CMD12_NOT_EXEC (WO) - * - * Force Event for Auto CMD12 Not Executed - * Values: - * 0x1 (TRUE): Auto CMD12 Not Executed Status is set - * 0x0 (FALSE): Not Affected - */ -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK (0x1U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT (0U) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SET(x) (((uint32_t)(x) << SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) -#define SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_GET(x) (((uint32_t)(x) & SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_MASK) >> SDXC_FORCE_EVENT_FORCE_AUTO_CMD12_NOT_EXEC_SHIFT) - -/* Bitfield definition for register: ADMA_ERR_STAT */ -/* - * ADMA_LEN_ERR (RO) - * - * ADMA Length Mismatch Error States - * This error occurs in the following instances: - * While the Block Count Enable is being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length - * When the total data length cannot be divided by the block length - * Values: - * 0x0 (NO_ERR): No Error - * 0x1 (ERROR): Error - */ -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK (0x4U) -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT (2U) -#define SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_LEN_ERR_SHIFT) - -/* - * ADMA_ERR_STATES (RO) - * - * ADMA Error States - * These bits indicate the state of ADMA when an error occurs during ADMA data transfer. - * Values: - * 0x0 (ST_STOP): Stop DMA - SYS_ADR register points to a location next to the error descriptor - * 0x1 (ST_FDS): Fetch Descriptor - SYS_ADR register points to the error descriptor - * 0x2 (UNUSED): Never set this state - * 0x3 (ST_TFR): Transfer Data - SYS_ADR register points to a location next to the error descriptor - */ -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK (0x3U) -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT (0U) -#define SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_GET(x) (((uint32_t)(x) & SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_MASK) >> SDXC_ADMA_ERR_STAT_ADMA_ERR_STATES_SHIFT) - -/* Bitfield definition for register: ADMA_SYS_ADDR */ -/* - * ADMA_SA (RW) - * - * ADMA System Address - * These bits indicate the lower 32 bits of the ADMA system address. - * SDMA: If Host Version 4 Enable is set to 1, this register stores the system address of the data location - * ADMA2: This register stores the byte address of the executing command of the descriptor table - * ADMA3: This register is set by ADMA3. ADMA2 increments the address of this register that points to the next line, every time a Descriptor line is fetched. - */ -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK (0xFFFFFFFFUL) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT (0U) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_SET(x) (((uint32_t)(x) << SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) -#define SDXC_ADMA_SYS_ADDR_ADMA_SA_GET(x) (((uint32_t)(x) & SDXC_ADMA_SYS_ADDR_ADMA_SA_MASK) >> SDXC_ADMA_SYS_ADDR_ADMA_SA_SHIFT) - -/* Bitfield definition for register array: PRESET */ -/* - * CLK_GEN_SEL_VAL (RO) - * - * Clock Generator Select Value - * This bit is effective when the Host Controller supports a programmable clock generator. - * Values: - * 0x0 (FALSE): Host Controller Ver2.0 Compatible Clock Generator - * 0x1 (PROG): Programmable Clock Generator - */ -#define SDXC_PRESET_CLK_GEN_SEL_VAL_MASK (0x400U) -#define SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT (10U) -#define SDXC_PRESET_CLK_GEN_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_CLK_GEN_SEL_VAL_MASK) >> SDXC_PRESET_CLK_GEN_SEL_VAL_SHIFT) - -/* - * FREQ_SEL_VAL (RO) - * - * SDCLK/RCLK Frequency Select Value - * 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System. - */ -#define SDXC_PRESET_FREQ_SEL_VAL_MASK (0x3FFU) -#define SDXC_PRESET_FREQ_SEL_VAL_SHIFT (0U) -#define SDXC_PRESET_FREQ_SEL_VAL_GET(x) (((uint16_t)(x) & SDXC_PRESET_FREQ_SEL_VAL_MASK) >> SDXC_PRESET_FREQ_SEL_VAL_SHIFT) - -/* Bitfield definition for register: ADMA_ID_ADDR */ -/* - * ADMA_ID_ADDR (RW) - * - * ADMA Integrated Descriptor Address - * These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. - * The start address of Integrated Descriptor is set to these register bits. - * The ADMA3 fetches one Descriptor Address and increments these bits to indicate the next Descriptor address. - */ -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK (0xFFFFFFFFUL) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT (0U) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SET(x) (((uint32_t)(x) << SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) -#define SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_GET(x) (((uint32_t)(x) & SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_MASK) >> SDXC_ADMA_ID_ADDR_ADMA_ID_ADDR_SHIFT) - -/* Bitfield definition for register: P_EMBEDDED_CNTRL */ -/* - * REG_OFFSET_ADDR (RO) - * - * Offset Address of Embedded Control register. - */ -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK (0xFFFU) -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_MASK) >> SDXC_P_EMBEDDED_CNTRL_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: P_VENDOR_SPECIFIC_AREA */ -/* - * REG_OFFSET_ADDR (RO) - * - * Base offset Address for Vendor-Specific registers. - */ -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFU) -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: P_VENDOR2_SPECIFIC_AREA */ -/* - * REG_OFFSET_ADDR (RO) - * - * Base offset Address for Command Queuing registers. - */ -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK (0xFFFFU) -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT (0U) -#define SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_GET(x) (((uint16_t)(x) & SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_MASK) >> SDXC_P_VENDOR2_SPECIFIC_AREA_REG_OFFSET_ADDR_SHIFT) - -/* Bitfield definition for register: SLOT_INTR_STATUS */ -/* - * INTR_SLOT (RO) - * - * Interrupt signal for each Slot - * These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. - * A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the Host Driver can identify the interrupt that is generated by reading these bits. - * By a power on reset or by setting Software Reset For All bit, the interrupt signals are de-asserted and this status reads 00h. - * Bit 00: Slot 1 - * Bit 01: Slot 2 - * Bit 02: Slot 3 - * .......... - * .......... - * Bit 07: Slot 8 - * Note: MSHC Host Controller support single card slot. This register shall always return 0. - */ -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK (0xFFU) -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT (0U) -#define SDXC_SLOT_INTR_STATUS_INTR_SLOT_GET(x) (((uint16_t)(x) & SDXC_SLOT_INTR_STATUS_INTR_SLOT_MASK) >> SDXC_SLOT_INTR_STATUS_INTR_SLOT_SHIFT) - -/* Bitfield definition for register: CQVER */ -/* - * EMMC_VER_MAHOR (RO) - * - * This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_MAHOR_MASK (0xF00U) -#define SDXC_CQVER_EMMC_VER_MAHOR_SHIFT (8U) -#define SDXC_CQVER_EMMC_VER_MAHOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MAHOR_MASK) >> SDXC_CQVER_EMMC_VER_MAHOR_SHIFT) - -/* - * EMMC_VER_MINOR (RO) - * - * This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_MINOR_MASK (0xF0U) -#define SDXC_CQVER_EMMC_VER_MINOR_SHIFT (4U) -#define SDXC_CQVER_EMMC_VER_MINOR_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_MINOR_MASK) >> SDXC_CQVER_EMMC_VER_MINOR_SHIFT) - -/* - * EMMC_VER_SUFFIX (RO) - * - * This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format. - */ -#define SDXC_CQVER_EMMC_VER_SUFFIX_MASK (0xFU) -#define SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT (0U) -#define SDXC_CQVER_EMMC_VER_SUFFIX_GET(x) (((uint32_t)(x) & SDXC_CQVER_EMMC_VER_SUFFIX_MASK) >> SDXC_CQVER_EMMC_VER_SUFFIX_SHIFT) - -/* Bitfield definition for register: CQCAP */ -/* - * CRYPTO_SUPPORT (RO) - * - * Crypto Support - * This bit indicates whether the Host Controller supports cryptographic operations. - * Values: - * 0x0 (FALSE): Crypto not Supported - * 0x1 (TRUE): Crypto Supported - */ -#define SDXC_CQCAP_CRYPTO_SUPPORT_MASK (0x10000000UL) -#define SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT (28U) -#define SDXC_CQCAP_CRYPTO_SUPPORT_GET(x) (((uint32_t)(x) & SDXC_CQCAP_CRYPTO_SUPPORT_MASK) >> SDXC_CQCAP_CRYPTO_SUPPORT_SHIFT) - -/* - * ITCFMUL (RO) - * - * Internal Timer Clock Frequency Multiplier (ITCFMUL) - * This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS - * polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are reserved. - * Values: - * 0x0 (CLK_1KHz): 1KHz clock - * 0x1 (CLK_10KHz): 10KHz clock - * 0x2 (CLK_100KHz): 100KHz clock - * 0x3 (CLK_1MHz): 1MHz clock - * 0x4 (CLK_10MHz): 10MHz clock - */ -#define SDXC_CQCAP_ITCFMUL_MASK (0xF000U) -#define SDXC_CQCAP_ITCFMUL_SHIFT (12U) -#define SDXC_CQCAP_ITCFMUL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFMUL_MASK) >> SDXC_CQCAP_ITCFMUL_SHIFT) - -/* - * ITCFVAL (RO) - * - * Internal Timer Clock Frequency Value (ITCFVAL) - * This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL. - */ -#define SDXC_CQCAP_ITCFVAL_MASK (0x3FFU) -#define SDXC_CQCAP_ITCFVAL_SHIFT (0U) -#define SDXC_CQCAP_ITCFVAL_GET(x) (((uint32_t)(x) & SDXC_CQCAP_ITCFVAL_MASK) >> SDXC_CQCAP_ITCFVAL_SHIFT) - -/* Bitfield definition for register: CQCFG */ -/* - * DCMD_EN (RW) - * - * This bit indicates to the hardware whether the Task - * Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor. - * Values: - * 0x1 (SLOT31_DCMD_ENABLE): Task descriptor in slot #31 is a DCMD Task Descriptor - * 0x0 (SLOT31_DCMD_DISABLE): Task descriptor in slot #31 is a data Transfer Task Descriptor - */ -#define SDXC_CQCFG_DCMD_EN_MASK (0x1000U) -#define SDXC_CQCFG_DCMD_EN_SHIFT (12U) -#define SDXC_CQCFG_DCMD_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_DCMD_EN_SHIFT) & SDXC_CQCFG_DCMD_EN_MASK) -#define SDXC_CQCFG_DCMD_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_DCMD_EN_MASK) >> SDXC_CQCFG_DCMD_EN_SHIFT) - -/* - * TASK_DESC_SIZE (RW) - * - * Bit Value Description - * This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). - * Values: - * 0x1 (TASK_DESC_128b): Task descriptor size is 128 bits - * 0x0 (TASK_DESC_64b): Task descriptor size is 64 bit - */ -#define SDXC_CQCFG_TASK_DESC_SIZE_MASK (0x100U) -#define SDXC_CQCFG_TASK_DESC_SIZE_SHIFT (8U) -#define SDXC_CQCFG_TASK_DESC_SIZE_SET(x) (((uint32_t)(x) << SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) -#define SDXC_CQCFG_TASK_DESC_SIZE_GET(x) (((uint32_t)(x) & SDXC_CQCFG_TASK_DESC_SIZE_MASK) >> SDXC_CQCFG_TASK_DESC_SIZE_SHIFT) - -/* - * CQ_EN (RW) - * - */ -#define SDXC_CQCFG_CQ_EN_MASK (0x1U) -#define SDXC_CQCFG_CQ_EN_SHIFT (0U) -#define SDXC_CQCFG_CQ_EN_SET(x) (((uint32_t)(x) << SDXC_CQCFG_CQ_EN_SHIFT) & SDXC_CQCFG_CQ_EN_MASK) -#define SDXC_CQCFG_CQ_EN_GET(x) (((uint32_t)(x) & SDXC_CQCFG_CQ_EN_MASK) >> SDXC_CQCFG_CQ_EN_SHIFT) - -/* Bitfield definition for register: CQCTL */ -/* - * CLR_ALL_TASKS (RW) - * - * Clear all tasks - * This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. - * Values: - * 0x1 (CLEAR_ALL_TASKS): Clears all the tasks in the controller - * 0x0 (NO_EFFECT): Programming 0 has no effect - */ -#define SDXC_CQCTL_CLR_ALL_TASKS_MASK (0x100U) -#define SDXC_CQCTL_CLR_ALL_TASKS_SHIFT (8U) -#define SDXC_CQCTL_CLR_ALL_TASKS_SET(x) (((uint32_t)(x) << SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) -#define SDXC_CQCTL_CLR_ALL_TASKS_GET(x) (((uint32_t)(x) & SDXC_CQCTL_CLR_ALL_TASKS_MASK) >> SDXC_CQCTL_CLR_ALL_TASKS_SHIFT) - -/* - * HALT (RW) - * - * Halt request and resume - * Values: - * 0x1 (HALT_CQE): Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. - * For example, issuing a Discard Task command (CMDQ_TASK_MGMT). - * When the software writes 1, CQE completes the ongoing task (if any in progress). - * After the task is completed and the CQE is in idle state, CQE does not issue new commands and indicates to the software by setting this bit to 1. - * The software can poll on this bit until it is set to 1 and only then send commands on the eMMC bus. - * 0x0 (RESUME_CQE): Software writes 0 to this bit to exit from the halt state and resume CQE activity - */ -#define SDXC_CQCTL_HALT_MASK (0x1U) -#define SDXC_CQCTL_HALT_SHIFT (0U) -#define SDXC_CQCTL_HALT_SET(x) (((uint32_t)(x) << SDXC_CQCTL_HALT_SHIFT) & SDXC_CQCTL_HALT_MASK) -#define SDXC_CQCTL_HALT_GET(x) (((uint32_t)(x) & SDXC_CQCTL_HALT_MASK) >> SDXC_CQCTL_HALT_SHIFT) - -/* Bitfield definition for register: CQIS */ -/* - * TCL (RW) - * - * Task cleared interrupt - * This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. - * The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing CQCTL). - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): TCL Interrupt is set - * 0x0 (NOTSET): TCL Interrupt is not set - */ -#define SDXC_CQIS_TCL_MASK (0x8U) -#define SDXC_CQIS_TCL_SHIFT (3U) -#define SDXC_CQIS_TCL_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCL_SHIFT) & SDXC_CQIS_TCL_MASK) -#define SDXC_CQIS_TCL_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCL_MASK) >> SDXC_CQIS_TCL_SHIFT) - -/* - * RED (RW) - * - * Response error detected interrupt - * This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status - * field. Configure the CQRMEM register to identify device status bit fields that may trigger an interrupt and that are masked. - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): RED Interrupt is set - * 0x0 (NOTSET): RED Interrupt is not set - */ -#define SDXC_CQIS_RED_MASK (0x4U) -#define SDXC_CQIS_RED_SHIFT (2U) -#define SDXC_CQIS_RED_SET(x) (((uint32_t)(x) << SDXC_CQIS_RED_SHIFT) & SDXC_CQIS_RED_MASK) -#define SDXC_CQIS_RED_GET(x) (((uint32_t)(x) & SDXC_CQIS_RED_MASK) >> SDXC_CQIS_RED_SHIFT) - -/* - * TCC (RW) - * - * Task complete interrupt - * This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: - * A task is completed and the INT bit is set in its Task Descriptor - * Interrupt caused by Interrupt Coalescing logic due to timeout - * Interrupt Coalescing logic reached the configured threshold - * A value of 1 clears this status bit - */ -#define SDXC_CQIS_TCC_MASK (0x2U) -#define SDXC_CQIS_TCC_SHIFT (1U) -#define SDXC_CQIS_TCC_SET(x) (((uint32_t)(x) << SDXC_CQIS_TCC_SHIFT) & SDXC_CQIS_TCC_MASK) -#define SDXC_CQIS_TCC_GET(x) (((uint32_t)(x) & SDXC_CQIS_TCC_MASK) >> SDXC_CQIS_TCC_SHIFT) - -/* - * HAC (RW) - * - * Halt complete interrupt - * This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. - * A value of 1 clears this status bit. - * Values: - * 0x1 (SET): HAC Interrupt is set - * 0x0 (NOTSET): HAC Interrupt is not set - */ -#define SDXC_CQIS_HAC_MASK (0x1U) -#define SDXC_CQIS_HAC_SHIFT (0U) -#define SDXC_CQIS_HAC_SET(x) (((uint32_t)(x) << SDXC_CQIS_HAC_SHIFT) & SDXC_CQIS_HAC_MASK) -#define SDXC_CQIS_HAC_GET(x) (((uint32_t)(x) & SDXC_CQIS_HAC_MASK) >> SDXC_CQIS_HAC_SHIFT) - -/* Bitfield definition for register: CQISE */ -/* - * TCL_STE (RW) - * - * Task cleared interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.TCL is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.TCL is disabled - */ -#define SDXC_CQISE_TCL_STE_MASK (0x8U) -#define SDXC_CQISE_TCL_STE_SHIFT (3U) -#define SDXC_CQISE_TCL_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCL_STE_SHIFT) & SDXC_CQISE_TCL_STE_MASK) -#define SDXC_CQISE_TCL_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCL_STE_MASK) >> SDXC_CQISE_TCL_STE_SHIFT) - -/* - * RED_STE (RW) - * - * Response error detected interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.RED is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.RED is disabled - */ -#define SDXC_CQISE_RED_STE_MASK (0x4U) -#define SDXC_CQISE_RED_STE_SHIFT (2U) -#define SDXC_CQISE_RED_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_RED_STE_SHIFT) & SDXC_CQISE_RED_STE_MASK) -#define SDXC_CQISE_RED_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_RED_STE_MASK) >> SDXC_CQISE_RED_STE_SHIFT) - -/* - * TCC_STE (RW) - * - * Task complete interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.TCC is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.TCC is disabled - */ -#define SDXC_CQISE_TCC_STE_MASK (0x2U) -#define SDXC_CQISE_TCC_STE_SHIFT (1U) -#define SDXC_CQISE_TCC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_TCC_STE_SHIFT) & SDXC_CQISE_TCC_STE_MASK) -#define SDXC_CQISE_TCC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_TCC_STE_MASK) >> SDXC_CQISE_TCC_STE_SHIFT) - -/* - * HAC_STE (RW) - * - * Halt complete interrupt status enable - * Values: - * 0x1 (INT_STS_ENABLE): CQIS.HAC is set when its interrupt condition is active - * 0x0 (INT_STS_DISABLE): CQIS.HAC is disabled - */ -#define SDXC_CQISE_HAC_STE_MASK (0x1U) -#define SDXC_CQISE_HAC_STE_SHIFT (0U) -#define SDXC_CQISE_HAC_STE_SET(x) (((uint32_t)(x) << SDXC_CQISE_HAC_STE_SHIFT) & SDXC_CQISE_HAC_STE_MASK) -#define SDXC_CQISE_HAC_STE_GET(x) (((uint32_t)(x) & SDXC_CQISE_HAC_STE_MASK) >> SDXC_CQISE_HAC_STE_SHIFT) - -/* Bitfield definition for register: CQISGE */ -/* - * TCL_SGE (RW) - * - * Task cleared interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.TCL interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.TCL interrupt signal generation is disabled - */ -#define SDXC_CQISGE_TCL_SGE_MASK (0x8U) -#define SDXC_CQISGE_TCL_SGE_SHIFT (3U) -#define SDXC_CQISGE_TCL_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCL_SGE_SHIFT) & SDXC_CQISGE_TCL_SGE_MASK) -#define SDXC_CQISGE_TCL_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCL_SGE_MASK) >> SDXC_CQISGE_TCL_SGE_SHIFT) - -/* - * RED_SGE (RW) - * - * Response error detected interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.RED interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.RED interrupt signal generation is disabled - */ -#define SDXC_CQISGE_RED_SGE_MASK (0x4U) -#define SDXC_CQISGE_RED_SGE_SHIFT (2U) -#define SDXC_CQISGE_RED_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_RED_SGE_SHIFT) & SDXC_CQISGE_RED_SGE_MASK) -#define SDXC_CQISGE_RED_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_RED_SGE_MASK) >> SDXC_CQISGE_RED_SGE_SHIFT) - -/* - * TCC_SGE (RW) - * - * Task complete interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.TCC interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.TCC interrupt signal generation is disabled - */ -#define SDXC_CQISGE_TCC_SGE_MASK (0x2U) -#define SDXC_CQISGE_TCC_SGE_SHIFT (1U) -#define SDXC_CQISGE_TCC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_TCC_SGE_SHIFT) & SDXC_CQISGE_TCC_SGE_MASK) -#define SDXC_CQISGE_TCC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_TCC_SGE_MASK) >> SDXC_CQISGE_TCC_SGE_SHIFT) - -/* - * HAC_SGE (RW) - * - * Halt complete interrupt signal enable - * Values: - * 0x1 (INT_SIG_ENABLE): CQIS.HAC interrupt signal generation is active - * 0x0 (INT_SIG_DISABLE): CQIS.HAC interrupt signal generation is disabled - */ -#define SDXC_CQISGE_HAC_SGE_MASK (0x1U) -#define SDXC_CQISGE_HAC_SGE_SHIFT (0U) -#define SDXC_CQISGE_HAC_SGE_SET(x) (((uint32_t)(x) << SDXC_CQISGE_HAC_SGE_SHIFT) & SDXC_CQISGE_HAC_SGE_MASK) -#define SDXC_CQISGE_HAC_SGE_GET(x) (((uint32_t)(x) & SDXC_CQISGE_HAC_SGE_MASK) >> SDXC_CQISGE_HAC_SGE_SHIFT) - -/* Bitfield definition for register: CQIC */ -/* - * INTC_EN (RW) - * - * Interrupt Coalescing Enable Bit - * Values: - * 0x1 (ENABLE_INT_COALESCING): Interrupt coalescing mechanism is active. Interrupts are counted and timed, and coalesced interrupts are generated - * 0x0 (DISABLE_INT_COALESCING): Interrupt coalescing mechanism is disabled (Default) - */ -#define SDXC_CQIC_INTC_EN_MASK (0x80000000UL) -#define SDXC_CQIC_INTC_EN_SHIFT (31U) -#define SDXC_CQIC_INTC_EN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_EN_SHIFT) & SDXC_CQIC_INTC_EN_MASK) -#define SDXC_CQIC_INTC_EN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_EN_MASK) >> SDXC_CQIC_INTC_EN_SHIFT) - -/* - * INTC_STAT (RO) - * - * Interrupt Coalescing Status Bit - * This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt - * coalescing (that is, this is set if and only if INTC counter > 0). - * Values: - * 0x1 (INTC_ATLEAST1_COMP): At least one INT0 task completion has been counted (INTC counter > 0) - * 0x0 (INTC_NO_TASK_COMP): INT0 Task completions have not occurred since last counter reset (INTC counter == 0) - */ -#define SDXC_CQIC_INTC_STAT_MASK (0x100000UL) -#define SDXC_CQIC_INTC_STAT_SHIFT (20U) -#define SDXC_CQIC_INTC_STAT_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_STAT_MASK) >> SDXC_CQIC_INTC_STAT_SHIFT) - -/* - * INTC_RST (WO) - * - * Counter and Timer Reset - * When host driver writes 1, the interrupt coalescing timer and counter are reset. - * Values: - * 0x1 (ASSERT_INTC_RESET): Interrupt coalescing timer and counter are reset - * 0x0 (NO_EFFECT): No Effect - */ -#define SDXC_CQIC_INTC_RST_MASK (0x10000UL) -#define SDXC_CQIC_INTC_RST_SHIFT (16U) -#define SDXC_CQIC_INTC_RST_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_RST_SHIFT) & SDXC_CQIC_INTC_RST_MASK) -#define SDXC_CQIC_INTC_RST_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_RST_MASK) >> SDXC_CQIC_INTC_RST_SHIFT) - -/* - * INTC_TH_WEN (WO) - * - * Interrupt Coalescing Counter Threshold Write Enable - * When software writes 1 to this bit, the value INTC_TH is updated with the contents written on the same cycle. - * Values: - * 0x1 (WEN_SET): Sets INTC_TH_WEN - * 0x0 (WEN_CLR): Clears INTC_TH_WEN - */ -#define SDXC_CQIC_INTC_TH_WEN_MASK (0x8000U) -#define SDXC_CQIC_INTC_TH_WEN_SHIFT (15U) -#define SDXC_CQIC_INTC_TH_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_WEN_SHIFT) & SDXC_CQIC_INTC_TH_WEN_MASK) -#define SDXC_CQIC_INTC_TH_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_WEN_MASK) >> SDXC_CQIC_INTC_TH_WEN_SHIFT) - -/* - * INTC_TH (WO) - * - * Interrupt Coalescing Counter Threshold filed - * Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor), which are required in order to generate an interrupt. - * Counter Operation: As data transfer tasks with INT=0 complete, they are counted by CQE. - * The counter is reset by software during the interrupt service routine. - * The counter stops counting when it reaches the value configured in INTC_TH, and generates interrupt. - * 0x0: Interrupt coalescing feature disabled - * 0x1: Interrupt coalescing interrupt generated after 1 task when INT=0 completes - * 0x2: Interrupt coalescing interrupt generated after 2 tasks when INT=0 completes - * ........ - * 0x1f: Interrupt coalescing interrupt generated after 31 tasks when INT=0 completes - * To write to this field, the INTC_TH_WEN bit must be set during the same write operation. - */ -#define SDXC_CQIC_INTC_TH_MASK (0x1F00U) -#define SDXC_CQIC_INTC_TH_SHIFT (8U) -#define SDXC_CQIC_INTC_TH_SET(x) (((uint32_t)(x) << SDXC_CQIC_INTC_TH_SHIFT) & SDXC_CQIC_INTC_TH_MASK) -#define SDXC_CQIC_INTC_TH_GET(x) (((uint32_t)(x) & SDXC_CQIC_INTC_TH_MASK) >> SDXC_CQIC_INTC_TH_SHIFT) - -/* - * TOUT_VAL_WEN (WO) - * - * When software writes 1 to this bit, the value TOUT_VAL is updated with the contents written on the same cycle. - * Values: - * 0x1 (WEN_SET): Sets TOUT_VAL_WEN - * 0x0 (WEN_CLR): clears TOUT_VAL_WEN - */ -#define SDXC_CQIC_TOUT_VAL_WEN_MASK (0x80U) -#define SDXC_CQIC_TOUT_VAL_WEN_SHIFT (7U) -#define SDXC_CQIC_TOUT_VAL_WEN_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_WEN_SHIFT) & SDXC_CQIC_TOUT_VAL_WEN_MASK) -#define SDXC_CQIC_TOUT_VAL_WEN_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_WEN_MASK) >> SDXC_CQIC_TOUT_VAL_WEN_SHIFT) - -/* - * TOUT_VAL (RW) - * - * Interrupt Coalescing Timeout Value - * Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. - * Timer Operation: The timer is reset by software during the interrupt service routine. - * It starts running when the first data transfer task with INT=0 is completed, after the timer was reset. - * When the timer reaches the value configured in ICTOVAL field, it generates an interrupt and stops. - * The timer's unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. - * 0x0: Timer is disabled. Timeout-based interrupt is not generated - * 0x1: Timeout on 01x1024 cycles of timer clock frequency - * 0x2: Timeout on 02x1024 cycles of timer clock frequency - * ........ - * 0x7f: Timeout on 127x1024 cycles of timer clock frequency - * In order to write to this field, the TOUT_VAL_WEN bit must - * be set at the same write operation. - */ -#define SDXC_CQIC_TOUT_VAL_MASK (0x7FU) -#define SDXC_CQIC_TOUT_VAL_SHIFT (0U) -#define SDXC_CQIC_TOUT_VAL_SET(x) (((uint32_t)(x) << SDXC_CQIC_TOUT_VAL_SHIFT) & SDXC_CQIC_TOUT_VAL_MASK) -#define SDXC_CQIC_TOUT_VAL_GET(x) (((uint32_t)(x) & SDXC_CQIC_TOUT_VAL_MASK) >> SDXC_CQIC_TOUT_VAL_SHIFT) - -/* Bitfield definition for register: CQTDLBA */ -/* - * TDLBA (RW) - * - * This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. - * The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver. - * This address is set on 1 KB boundary. The lower 10 bits of this register are set to 0 by the software and are ignored by CQE - */ -#define SDXC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFUL) -#define SDXC_CQTDLBA_TDLBA_SHIFT (0U) -#define SDXC_CQTDLBA_TDLBA_SET(x) (((uint32_t)(x) << SDXC_CQTDLBA_TDLBA_SHIFT) & SDXC_CQTDLBA_TDLBA_MASK) -#define SDXC_CQTDLBA_TDLBA_GET(x) (((uint32_t)(x) & SDXC_CQTDLBA_TDLBA_MASK) >> SDXC_CQTDLBA_TDLBA_SHIFT) - -/* Bitfield definition for register: CQTDBR */ -/* - * DBR (RW) - * - * The software configures TDLBA and TDLBAU, and enable - * CQE in CQCFG before using this register. - * Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. - * Writing 0 by the software does not have any impact on the hardware, and does not change the value of the register bit. - * CQE always processes tasks according to the order submitted to the list by CQTDBR write transactions. - * CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to - * the device. CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument. - * The corresponding bit is cleared to 0 by CQE in one of the following events: - * A task execution is completed (with success or error). - * The task is cleared using CQTCLR register. - * All tasks are cleared using CQCTL register. - * CQE is disabled using CQCFG register. - * Software may initiate multiple tasks at the same time (batch submission) by writing 1 to multiple bits of this register in the same transaction. - * In the case of batch submission, CQE processes the tasks in order of the task index, starting with the lowest index. - * If one or more tasks in the batch are marked with QBR, the ordering of execution is based on said processing order. - */ -#define SDXC_CQTDBR_DBR_MASK (0xFFFFFFFFUL) -#define SDXC_CQTDBR_DBR_SHIFT (0U) -#define SDXC_CQTDBR_DBR_SET(x) (((uint32_t)(x) << SDXC_CQTDBR_DBR_SHIFT) & SDXC_CQTDBR_DBR_MASK) -#define SDXC_CQTDBR_DBR_GET(x) (((uint32_t)(x) & SDXC_CQTDBR_DBR_MASK) >> SDXC_CQTDBR_DBR_SHIFT) - -/* Bitfield definition for register: CQTCN */ -/* - * TCN (RW) - * - * Task Completion Notification - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Task-N has completed execution (with success or errors) - * Bit-N(0): Task-N has not completed, could be pending or not submitted. - * On task completion, software may read this register to know tasks that have completed. After reading this register, - * software may clear the relevant bit fields by writing 1 to the corresponding bits. - */ -#define SDXC_CQTCN_TCN_MASK (0xFFFFFFFFUL) -#define SDXC_CQTCN_TCN_SHIFT (0U) -#define SDXC_CQTCN_TCN_SET(x) (((uint32_t)(x) << SDXC_CQTCN_TCN_SHIFT) & SDXC_CQTCN_TCN_MASK) -#define SDXC_CQTCN_TCN_GET(x) (((uint32_t)(x) & SDXC_CQTCN_TCN_MASK) >> SDXC_CQTCN_TCN_SHIFT) - -/* Bitfield definition for register: CQDQS */ -/* - * DQS (RW) - * - * Device Queue Status - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Device has marked task N as ready for execution - * Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. - * Host controller updates this register with response of the Device Queue Status command. - */ -#define SDXC_CQDQS_DQS_MASK (0xFFFFFFFFUL) -#define SDXC_CQDQS_DQS_SHIFT (0U) -#define SDXC_CQDQS_DQS_SET(x) (((uint32_t)(x) << SDXC_CQDQS_DQS_SHIFT) & SDXC_CQDQS_DQS_MASK) -#define SDXC_CQDQS_DQS_GET(x) (((uint32_t)(x) & SDXC_CQDQS_DQS_MASK) >> SDXC_CQDQS_DQS_SHIFT) - -/* Bitfield definition for register: CQDPT */ -/* - * DPT (RW) - * - * Device-Pending Tasks - * Each of the 32 bits are bit mapped to the 32 tasks. - * Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution - * Bit-N(0): Task-N is not yet queued. - * Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task has not been executed. - * The controller sets this bit after receiving a successful response for CMD45. CQE clears this bit after the task has completed execution. - * Software reads this register in the task-discard procedure to determine if the task is queued in the device - */ -#define SDXC_CQDPT_DPT_MASK (0xFFFFFFFFUL) -#define SDXC_CQDPT_DPT_SHIFT (0U) -#define SDXC_CQDPT_DPT_SET(x) (((uint32_t)(x) << SDXC_CQDPT_DPT_SHIFT) & SDXC_CQDPT_DPT_MASK) -#define SDXC_CQDPT_DPT_GET(x) (((uint32_t)(x) & SDXC_CQDPT_DPT_MASK) >> SDXC_CQDPT_DPT_SHIFT) - -/* Bitfield definition for register: CQTCLR */ -/* - * TCLR (RW) - * - * Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. - * This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. - * When software writes 1 to a bit in this register, CQE updates the value to 1, and starts clearing the data structures related to the task. - * CQE clears the bit fields (sets a value of 0) in CQTCLR and in CQTDBR once the clear operation is complete. - * Software must poll on the CQTCLR until it is leared to verify that a clear operation was done. - */ -#define SDXC_CQTCLR_TCLR_MASK (0xFFFFFFFFUL) -#define SDXC_CQTCLR_TCLR_SHIFT (0U) -#define SDXC_CQTCLR_TCLR_SET(x) (((uint32_t)(x) << SDXC_CQTCLR_TCLR_SHIFT) & SDXC_CQTCLR_TCLR_MASK) -#define SDXC_CQTCLR_TCLR_GET(x) (((uint32_t)(x) & SDXC_CQTCLR_TCLR_MASK) >> SDXC_CQTCLR_TCLR_SHIFT) - -/* Bitfield definition for register: CQSSC1 */ -/* - * SQSCMD_BLK_CNT (RW) - * - * This field indicates when SQS CMD is sent while data transfer is in progress. - * A value of 'n' indicates that CQE sends status command on the CMD line, during the transfer of data block BLOCK_CNTn, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction. - * 0x0: SEND_QUEUE_STATUS (CMD13) command is not sent during the transaction. Instead, it is sent only when the data lines are idle. - * 0x1: SEND_QUEUE_STATUS command is to be sent during the last block of the transaction. - * 0x2: SEND_QUEUE_STATUS command when last 2 blocks are pending. - * 0x3: SEND_QUEUE_STATUS command when last 3 blocks are pending. - * ........ - * 0xf: SEND_QUEUE_STATUS command when last 15 blocks are pending. - * Should be programmed only when CQCFG.CQ_EN is 0 - */ -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK (0xF0000UL) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT (16U) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) -#define SDXC_CQSSC1_SQSCMD_BLK_CNT_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_BLK_CNT_MASK) >> SDXC_CQSSC1_SQSCMD_BLK_CNT_SHIFT) - -/* - * SQSCMD_IDLE_TMR (RW) - * - * This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. - * Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. - * When a SEND_QUEUE_STATUS response indicates that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS. - * Timer units are clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field CQCAP register. - * The minimum value is 0001h (1 clock period) and the maximum value is FFFFh (65535 clock periods). - * For example, a CQCAP field value of 0 indicates a 19.2 MHz clock frequency (period = 52.08 ns). - * If the setting in CQSSC1.CIT is 1000h, the calculated polling period is 4096*52.08 ns= 213.33 us. - * Should be programmed only when CQCFG.CQ_EN is '0' - */ -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK (0xFFFFU) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT (0U) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_SET(x) (((uint32_t)(x) << SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) -#define SDXC_CQSSC1_SQSCMD_IDLE_TMR_GET(x) (((uint32_t)(x) & SDXC_CQSSC1_SQSCMD_IDLE_TMR_MASK) >> SDXC_CQSSC1_SQSCMD_IDLE_TMR_SHIFT) - -/* Bitfield definition for register: CQSSC2 */ -/* - * SQSCMD_RCA (RW) - * - * This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. - * CQE copies this field to bits 31:16 of the argument when transmitting SEND_ QUEUE_STATUS (CMD13) command. - */ -#define SDXC_CQSSC2_SQSCMD_RCA_MASK (0xFFFFU) -#define SDXC_CQSSC2_SQSCMD_RCA_SHIFT (0U) -#define SDXC_CQSSC2_SQSCMD_RCA_SET(x) (((uint32_t)(x) << SDXC_CQSSC2_SQSCMD_RCA_SHIFT) & SDXC_CQSSC2_SQSCMD_RCA_MASK) -#define SDXC_CQSSC2_SQSCMD_RCA_GET(x) (((uint32_t)(x) & SDXC_CQSSC2_SQSCMD_RCA_MASK) >> SDXC_CQSSC2_SQSCMD_RCA_SHIFT) - -/* Bitfield definition for register: CQCRDCT */ -/* - * DCMD_RESP (RO) - * - * This register contains the response of the command generated by the last direct command (DCMD) task that was sent. - * Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller. - */ -#define SDXC_CQCRDCT_DCMD_RESP_MASK (0xFFFFFFFFUL) -#define SDXC_CQCRDCT_DCMD_RESP_SHIFT (0U) -#define SDXC_CQCRDCT_DCMD_RESP_GET(x) (((uint32_t)(x) & SDXC_CQCRDCT_DCMD_RESP_MASK) >> SDXC_CQCRDCT_DCMD_RESP_SHIFT) - -/* Bitfield definition for register: CQRMEM */ -/* - * RESP_ERR_MASK (RW) - * - * The bits of this field are bit mapped to the device response. - * This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. - * 1: When a R1/R1b response is received, with a bit i in the device status set, a RED interrupt is generated. - * 0: When a R1/R1b response is received, bit i in the device status is ignored. - * The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status. - * Note: Responses to CMD13 (SQS) encode the QSR so that they are ignored by this logic. - */ -#define SDXC_CQRMEM_RESP_ERR_MASK_MASK (0xFFFFFFFFUL) -#define SDXC_CQRMEM_RESP_ERR_MASK_SHIFT (0U) -#define SDXC_CQRMEM_RESP_ERR_MASK_SET(x) (((uint32_t)(x) << SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) -#define SDXC_CQRMEM_RESP_ERR_MASK_GET(x) (((uint32_t)(x) & SDXC_CQRMEM_RESP_ERR_MASK_MASK) >> SDXC_CQRMEM_RESP_ERR_MASK_SHIFT) - -/* Bitfield definition for register: CQTERRI */ -/* - * TRANS_ERR_TASKID (RO) - * - * This field captures the ID of the task that was executed and whose data transfer has errors. - */ -#define SDXC_CQTERRI_TRANS_ERR_TASKID_MASK (0x1F000000UL) -#define SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT (24U) -#define SDXC_CQTERRI_TRANS_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_TASKID_MASK) >> SDXC_CQTERRI_TRANS_ERR_TASKID_SHIFT) - -/* - * TRANS_ERR_CMD_INDX (RO) - * - * This field captures the index of the command that was executed and whose data transfer has errors. - */ -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK (0x3F0000UL) -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT (16U) -#define SDXC_CQTERRI_TRANS_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_TRANS_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_TRANS_ERR_CMD_INDX_SHIFT) - -/* - * RESP_ERR_FIELDS_VALID (RO) - * - * This bit is updated when an error is detected while a command transaction was in progress. - * Values: - * 0x1 (SET): Response-related error is detected. Check contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX fields - * 0x0 (NOT_SET): Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX - */ -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK (0x8000U) -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT (15U) -#define SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_MASK) >> SDXC_CQTERRI_RESP_ERR_FIELDS_VALID_SHIFT) - -/* - * RESP_ERR_TASKID (RO) - * - * This field captures the ID of the task which was executed on the command line when the error occurred. - */ -#define SDXC_CQTERRI_RESP_ERR_TASKID_MASK (0x1F00U) -#define SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT (8U) -#define SDXC_CQTERRI_RESP_ERR_TASKID_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_TASKID_MASK) >> SDXC_CQTERRI_RESP_ERR_TASKID_SHIFT) - -/* - * RESP_ERR_CMD_INDX (RO) - * - * This field captures the index of the command that was executed on the command line when the error occurred - */ -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK (0x3FU) -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT (0U) -#define SDXC_CQTERRI_RESP_ERR_CMD_INDX_GET(x) (((uint32_t)(x) & SDXC_CQTERRI_RESP_ERR_CMD_INDX_MASK) >> SDXC_CQTERRI_RESP_ERR_CMD_INDX_SHIFT) - -/* Bitfield definition for register: CQCRI */ -/* - * CMD_RESP_INDX (RO) - * - * Last Command Response index - * This field stores the index of the last received command response. Controller updates the value every time a command response is received - */ -#define SDXC_CQCRI_CMD_RESP_INDX_MASK (0x3FU) -#define SDXC_CQCRI_CMD_RESP_INDX_SHIFT (0U) -#define SDXC_CQCRI_CMD_RESP_INDX_GET(x) (((uint32_t)(x) & SDXC_CQCRI_CMD_RESP_INDX_MASK) >> SDXC_CQCRI_CMD_RESP_INDX_SHIFT) - -/* Bitfield definition for register: CQCRA */ -/* - * CMD_RESP_ARG (RO) - * - * Last Command Response argument - * This field stores the argument of the last received command response. Controller updates the value every time a command response is received. - */ -#define SDXC_CQCRA_CMD_RESP_ARG_MASK (0xFFFFFFFFUL) -#define SDXC_CQCRA_CMD_RESP_ARG_SHIFT (0U) -#define SDXC_CQCRA_CMD_RESP_ARG_GET(x) (((uint32_t)(x) & SDXC_CQCRA_CMD_RESP_ARG_MASK) >> SDXC_CQCRA_CMD_RESP_ARG_SHIFT) - -/* Bitfield definition for register: MSHC_VER_ID */ -/* - * VER_ID (RO) - * - */ -#define SDXC_MSHC_VER_ID_VER_ID_MASK (0xFFFFFFFFUL) -#define SDXC_MSHC_VER_ID_VER_ID_SHIFT (0U) -#define SDXC_MSHC_VER_ID_VER_ID_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_ID_VER_ID_MASK) >> SDXC_MSHC_VER_ID_VER_ID_SHIFT) - -/* Bitfield definition for register: MSHC_VER_TYPE */ -/* - * VER_TYPE (RO) - * - */ -#define SDXC_MSHC_VER_TYPE_VER_TYPE_MASK (0xFFFFFFFFUL) -#define SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT (0U) -#define SDXC_MSHC_VER_TYPE_VER_TYPE_GET(x) (((uint32_t)(x) & SDXC_MSHC_VER_TYPE_VER_TYPE_MASK) >> SDXC_MSHC_VER_TYPE_VER_TYPE_SHIFT) - -/* Bitfield definition for register: EMMC_BOOT_CTRL */ -/* - * BOOT_TOUT_CNT (RW) - * - * Boot Ack Timeout Counter Value. - * This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. - * 0xF : Reserved - * 0xE : TMCLK x 2^27 - * ............ - * 0x1 : TMCLK x 2^14 - * 0x0 : TMCLK x 2^13 - */ -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK (0xF0000000UL) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT (28U) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) -#define SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT) - -/* - * BOOT_ACK_ENABLE (RW) - * - * Boot Acknowledge Enable - * When this bit set, SDXC checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. - * Values: - * 0x1 (TRUE): Boot Ack enable - * 0x0 (FALSE): Boot Ack disable - */ -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK (0x1000000UL) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT (24U) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_BOOT_ACK_ENABLE_SHIFT) - -/* - * VALIDATE_BOOT (WO) - * - * Validate Mandatory Boot Enable bit - * This bit is used to validate the MAN_BOOT_EN bit. - * Values: - * 0x1 (TRUE): Validate Mandatory boot enable bit - * 0x0 (FALSE): Ignore Mandatory boot Enable bit - */ -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK (0x800000UL) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT (23U) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) -#define SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_MASK) >> SDXC_EMMC_BOOT_CTRL_VALIDATE_BOOT_SHIFT) - -/* - * MAN_BOOT_EN (RW) - * - * Mandatory Boot Enable - * This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. - * Writing 0 is ignored. The SDXC clears this bit after the boot transfer is completed or terminated. - * Values: - * 0x1 (MAN_BOOT_EN): Mandatory boot enable - * 0x0 (MAN_BOOT_DIS): Mandatory boot disable - */ -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK (0x10000UL) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT (16U) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) -#define SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_MASK) >> SDXC_EMMC_BOOT_CTRL_MAN_BOOT_EN_SHIFT) - -/* - * CQE_PREFETCH_DISABLE (RW) - * - * Enable or Disable CQE's PREFETCH feature - * This field allows Software to disable CQE's data prefetch feature when set to 1. - * Values: - * 0x0 (PREFETCH_ENABLE): CQE can Prefetch data for sucessive WRITE transfers and pipeline sucessive READ transfers - * 0x1 (PREFETCH_DISABLE): Prefetch for WRITE and Pipeline for READ are disabled - */ -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK (0x400U) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT (10U) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_PREFETCH_DISABLE_SHIFT) - -/* - * CQE_ALGO_SEL (RW) - * - * Scheduler algorithm selected for execution - * This bit selects the Algorithm used for selecting one of the many ready tasks for execution. - * Values: - * 0x0 (PRI_REORDER_PLUS_FCFS): Priority based reordering with FCFS to resolve equal priority tasks - * 0x1 (FCFS_ONLY): First come First serve, in the order of DBR rings - */ -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK (0x200U) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT (9U) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) -#define SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_MASK) >> SDXC_EMMC_BOOT_CTRL_CQE_ALGO_SEL_SHIFT) - -/* - * ENH_STROBE_ENABLE (RW) - * - * Enhanced Strobe Enable - * This bit instructs SDXC to sample the CMD line using data strobe for HS400 mode. - * Values: - * 0x1 (ENH_STB_FOR_CMD): CMD line is sampled using data strobe for HS400 mode - * 0x0 (NO_STB_FOR_CMD): CMD line is sampled using cclk_rx for HS400 mode - */ -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK (0x100U) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT (8U) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) -#define SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_MASK) >> SDXC_EMMC_BOOT_CTRL_ENH_STROBE_ENABLE_SHIFT) - -/* - * EMMC_RST_N_OE (RW) - * - * Output Enable control for EMMC Device Reset signal PAD - * control. - * This field drived sd_rst_n_oe output of SDXC - * Values: - * 0x1 (ENABLE): sd_rst_n_oe is 1 - * 0x0 (DISABLE): sd_rst_n_oe is 0 - */ -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK (0x8U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT (3U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_OE_SHIFT) - -/* - * EMMC_RST_N (RW) - * - * EMMC Device Reset signal control. - * This register field controls the sd_rst_n output of SDXC - * Values: - * 0x1 (RST_DEASSERT): Reset to eMMC device is deasserted - * 0x0 (RST_ASSERT): Reset to eMMC device asserted (active low) - */ -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK (0x4U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT (2U) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) -#define SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_MASK) >> SDXC_EMMC_BOOT_CTRL_EMMC_RST_N_SHIFT) - -/* - * DISABLE_DATA_CRC_CHK (RW) - * - * Disable Data CRC Check - * This bit controls masking of CRC16 error for Card Write in eMMC mode. - * This is useful in bus testing (CMD19) for an eMMC device. In bus testing, an eMMC card does not send CRC status for a block, - * which may generate CRC error. This CRC error can be masked using this bit during bus testing. - * Values: - * 0x1 (DISABLE): DATA CRC check is disabled - * 0x0 (ENABLE): DATA CRC check is enabled - */ -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK (0x2U) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT (1U) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) -#define SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_MASK) >> SDXC_EMMC_BOOT_CTRL_DISABLE_DATA_CRC_CHK_SHIFT) - -/* - * CARD_IS_EMMC (RW) - * - * eMMC Card present - * This bit indicates the type of card connected. An application program this bit based on the card connected to SDXC. - * Values: - * 0x1 (EMMC_CARD): Card connected to SDXC is an eMMC card - * 0x0 (NON_EMMC_CARD): Card connected to SDXCis a non-eMMC card - */ -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK (0x1U) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT (0U) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SET(x) (((uint32_t)(x) << SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) -#define SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_GET(x) (((uint32_t)(x) & SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_MASK) >> SDXC_EMMC_BOOT_CTRL_CARD_IS_EMMC_SHIFT) - -/* Bitfield definition for register: AUTO_TUNING_CTRL */ -/* - * SWIN_TH_VAL (RW) - * - * Sampling window threshold value setting - * The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 32 taps - * can use values from 0x0 to 0x1F. - * This field is valid only when SWIN_TH_EN is '1'. Should be programmed only when SAMPLE_CLK_SEL is '0' - * 0x0 : Threshold values is 0x1, windows of length 1 tap and above can be selected as sampling window. - * 0x1 : Threshold values is 0x2, windows of length 2 taps and above can be selected as sampling window. - * 0x2 : Threshold values is 0x1, windows of length 3 taps and above can be selected as sampling window. - * ........ - * 0x1F : Threshold values is 0x1, windows of length 32 taps and above can be selected as sampling window. - */ -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK (0x7F000000UL) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT (24U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_VAL_SHIFT) - -/* - * POST_CHANGE_DLY (RW) - * - * Time taken for phase switching and stable clock output. - * Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. - * Values: - * 0x0 (LATENCY_LT_1): Less than 1-cycle latency - * 0x1 (LATENCY_LT_2): Less than 2-cycle latency - * 0x2 (LATENCY_LT_3): Less than 3-cycle latency - * 0x3 (LATENCY_LT_4): Less than 4-cycle latency - */ -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK (0x180000UL) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT (19U) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) -#define SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_POST_CHANGE_DLY_SHIFT) - -/* - * PRE_CHANGE_DLY (RW) - * - * Maximum Latency specification between cclk_tx and cclk_rx. - * Values: - * 0x0 (LATENCY_LT_1): Less than 1-cycle latency - * 0x1 (LATENCY_LT_2): Less than 2-cycle latency - * 0x2 (LATENCY_LT_3): Less than 3-cycle latency - * 0x3 (LATENCY_LT_4): Less than 4-cycle latency - */ -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK (0x60000UL) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT (17U) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) -#define SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_MASK) >> SDXC_AUTO_TUNING_CTRL_PRE_CHANGE_DLY_SHIFT) - -/* - * TUNE_CLK_STOP_EN (RW) - * - * Clock stopping control for Tuning and auto-tuning circuit. - * When enabled, clock gate control output of SDXC (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. - * This effectively stops the Device/Card clock, cclk_rx and also drift_cclk_rx. Changing phase code when clocks are stopped ensures glitch free phase switching. - * Set this bit to 0 if the PHY or delayline can guarantee glitch free switching. - * Values: - * 0x1 (ENABLE_CLK_STOPPING): Clocks stopped during phase code change - * 0x0 (DISABLE_CLK_STOPPING): Clocks not stopped. PHY ensures glitch free phase switching - */ -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK (0x10000UL) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT (16U) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_TUNE_CLK_STOP_EN_SHIFT) - -/* - * WIN_EDGE_SEL (RW) - * - * This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. - * 0x0: User selection disabled. Tuning calculated edges are used. - * 0x1: Right edge Phase is center + 2 stages, Left edge Phase is center - 2 stages. - * 0x2: Right edge Phase is center + 3 stages, Left edge Phase is center - 3 stagess - * ... - * 0xF: Right edge Phase is center + 16 stages, Left edge Phase is center - 16 stages. - */ -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK (0xF00U) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT (8U) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) -#define SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_WIN_EDGE_SEL_SHIFT) - -/* - * SW_TUNE_EN (RW) - * - * This fields enables software-managed tuning flow. - * Values: - * 0x1 (SW_TUNING_ENABLE): Software-managed tuning enabled. AUTO_TUNING_STAT.CENTER_PH_CODE Field is now writable. - * 0x0 (SW_TUNING_DISABLE): Software-managed tuning disabled - */ -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK (0x10U) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT (4U) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SW_TUNE_EN_SHIFT) - -/* - * RPT_TUNE_ERR (RW) - * - * Framing errors are not generated when executing tuning. - * This debug bit allows users to report these errors. - * Values: - * 0x1 (DEBUG_ERRORS): Debug mode for reporting framing errors - * 0x0 (ERRORS_DISABLED): Default mode where as per SDXC no errors are reported. - */ -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK (0x8U) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT (3U) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) -#define SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_MASK) >> SDXC_AUTO_TUNING_CTRL_RPT_TUNE_ERR_SHIFT) - -/* - * SWIN_TH_EN (RW) - * - * Sampling window Threshold enable - * Selects the tuning mode - * Field should be programmed only when SAMPLE_CLK_SEL is '0' - * Values: - * 0x1 (THRESHOLD_MODE): Tuning engine selects the first complete sampling window that meets the threshold - * set by SWIN_TH_VAL field - * 0x0 (LARGEST_WIN_MODE): Tuning engine sweeps all taps and settles at the largest window - */ -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK (0x4U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT (2U) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_SWIN_TH_EN_SHIFT) - -/* - * CI_SEL (RW) - * - * Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. - * Values: - * 0x0 (WHEN_IN_BLK_GAP): Driven in block gap interval - * 0x1 (WHEN_IN_IDLE): Driven at the end of the transfer - */ -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK (0x2U) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT (1U) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) -#define SDXC_AUTO_TUNING_CTRL_CI_SEL_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_CI_SEL_MASK) >> SDXC_AUTO_TUNING_CTRL_CI_SEL_SHIFT) - -/* - * AT_EN (RW) - * - * Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. - * Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 retuning. - * This field should be programmed only when SYS_CTRL.SD_CLK_EN is 0. - * Values: - * 0x1 (AT_ENABLE): AutoTuning is enabled - * 0x0 (AT_DISABLE): AutoTuning is disabled - */ -#define SDXC_AUTO_TUNING_CTRL_AT_EN_MASK (0x1U) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT (0U) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) -#define SDXC_AUTO_TUNING_CTRL_AT_EN_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_CTRL_AT_EN_MASK) >> SDXC_AUTO_TUNING_CTRL_AT_EN_SHIFT) - -/* Bitfield definition for register: AUTO_TUNING_STAT */ -/* - * L_EDGE_PH_CODE (RO) - * - * Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window. - */ -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK (0xFF0000UL) -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT (16U) -#define SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_L_EDGE_PH_CODE_SHIFT) - -/* - * R_EDGE_PH_CODE (RO) - * - * Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window. - */ -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK (0xFF00U) -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT (8U) -#define SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_R_EDGE_PH_CODE_SHIFT) - -/* - * CENTER_PH_CODE (RW) - * - * Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AUTO_TUNING_CTRL.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel - */ -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK (0xFFU) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT (0U) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SET(x) (((uint32_t)(x) << SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) -#define SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_GET(x) (((uint32_t)(x) & SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_MASK) >> SDXC_AUTO_TUNING_STAT_CENTER_PH_CODE_SHIFT) - -/* Bitfield definition for register: MISC_CTRL0 */ -/* - * CARDCLK_INV_EN (RW) - * - * set to invert card_clk, for slow speed card to meet 5ns setup timing. - * May cause glitch on clock, should be set before enable clk(in core cfg) - */ -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK (0x10000000UL) -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT (28U) -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) -#define SDXC_MISC_CTRL0_CARDCLK_INV_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_CARDCLK_INV_EN_MASK) >> SDXC_MISC_CTRL0_CARDCLK_INV_EN_SHIFT) - -/* - * PAD_CLK_SEL_B (RW) - * - * set to use internal clock directly, may have timing issue; - * clr to use clock loopback from pad. - */ -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK (0x20000UL) -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT (17U) -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) -#define SDXC_MISC_CTRL0_PAD_CLK_SEL_B_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_PAD_CLK_SEL_B_MASK) >> SDXC_MISC_CTRL0_PAD_CLK_SEL_B_SHIFT) - -/* - * FREQ_SEL_SW_EN (RW) - * - * set to use FREQ_SEL_SW as card clock divider; - * clear to use core logic as clock divider. - */ -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK (0x800U) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT (11U) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_EN_SHIFT) - -/* - * TMCLK_EN (RW) - * - * set to force enable tmclk; - * clear to use core signal intclk_en to control it - */ -#define SDXC_MISC_CTRL0_TMCLK_EN_MASK (0x400U) -#define SDXC_MISC_CTRL0_TMCLK_EN_SHIFT (10U) -#define SDXC_MISC_CTRL0_TMCLK_EN_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) -#define SDXC_MISC_CTRL0_TMCLK_EN_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_TMCLK_EN_MASK) >> SDXC_MISC_CTRL0_TMCLK_EN_SHIFT) - -/* - * FREQ_SEL_SW (RW) - * - * software card clock divider, it will be used only when FREQ_SEL_SW_EN is set - */ -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK (0x3FFU) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT (0U) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) -#define SDXC_MISC_CTRL0_FREQ_SEL_SW_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL0_FREQ_SEL_SW_MASK) >> SDXC_MISC_CTRL0_FREQ_SEL_SW_SHIFT) - -/* Bitfield definition for register: MISC_CTRL1 */ -/* - * CARD_ACTIVE (RW) - * - * SW write 1 to start card clock delay counter(delay time is configed by CARD_ACTIVE_PERIOD_SEL). - * When counter finished, this bit will be cleared by hardware. - * Write 1 when this bit is 1 will cause unknown result(actually no use except write at exact finish time) - */ -#define SDXC_MISC_CTRL1_CARD_ACTIVE_MASK (0x80000000UL) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT (31U) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_SHIFT) - -/* - * CARD_ACTIVE_PERIOD_SEL (RW) - * - * card clock delay config. - * 00 for 100 cycle; 01 for 74 cycle; 10 for 128 cycle; 11 for 256 cycle - */ -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK (0x30000000UL) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT (28U) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) -#define SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_MASK) >> SDXC_MISC_CTRL1_CARD_ACTIVE_PERIOD_SEL_SHIFT) - -/* - * CARDCLK_DLYSEL (RW) - * - * for card clock DLL, default 0 - */ -#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK (0x3F00000UL) -#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT (20U) -#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) -#define SDXC_MISC_CTRL1_CARDCLK_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_CARDCLK_DLYSEL_MASK) >> SDXC_MISC_CTRL1_CARDCLK_DLYSEL_SHIFT) - -/* - * STROBE_DLYSEL (RW) - * - * for strobe DLL, default 7taps(1ns) - */ -#define SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK (0x3F000UL) -#define SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT (12U) -#define SDXC_MISC_CTRL1_STROBE_DLYSEL_SET(x) (((uint32_t)(x) << SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) -#define SDXC_MISC_CTRL1_STROBE_DLYSEL_GET(x) (((uint32_t)(x) & SDXC_MISC_CTRL1_STROBE_DLYSEL_MASK) >> SDXC_MISC_CTRL1_STROBE_DLYSEL_SHIFT) - - - -/* RESP register group index macro definition */ -#define SDXC_RESP_RESP01 (0UL) -#define SDXC_RESP_RESP23 (1UL) -#define SDXC_RESP_RESP45 (2UL) -#define SDXC_RESP_RESP67 (3UL) - -/* PRESET register group index macro definition */ -#define SDXC_PRESET_INIT (0UL) -#define SDXC_PRESET_DS (1UL) -#define SDXC_PRESET_HS (2UL) -#define SDXC_PRESET_SDR12 (3UL) -#define SDXC_PRESET_SDR25 (4UL) -#define SDXC_PRESET_SDR50 (5UL) -#define SDXC_PRESET_SDR104 (6UL) -#define SDXC_PRESET_DDR50 (7UL) -#define SDXC_PRESET_UHS2 (10UL) - - -#endif /* HPM_SDXC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sec_regs.h deleted file mode 100644 index 19362a87502..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sec_regs.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SEC_H -#define HPM_SEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ - __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ -} SEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define SEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define SEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define SEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_NSC_MASK) >> SEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define SEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define SEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define SEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_SEC_MASK) >> SEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * PMIC_FAIL (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define SEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) -#define SEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) -#define SEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_FAIL_SHIFT) & SEC_SECURE_STATE_PMIC_FAIL_MASK) -#define SEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_FAIL_MASK) >> SEC_SECURE_STATE_PMIC_FAIL_SHIFT) - -/* - * PMIC_NSC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define SEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) -#define SEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) -#define SEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_NSC_SHIFT) & SEC_SECURE_STATE_PMIC_NSC_MASK) -#define SEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_NSC_MASK) >> SEC_SECURE_STATE_PMIC_NSC_SHIFT) - -/* - * PMIC_SEC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define SEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) -#define SEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) -#define SEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_SEC_SHIFT) & SEC_SECURE_STATE_PMIC_SEC_MASK) -#define SEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_SEC_MASK) >> SEC_SECURE_STATE_PMIC_SEC_SHIFT) - -/* - * PMIC_INS (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define SEC_SECURE_STATE_PMIC_INS_MASK (0x10U) -#define SEC_SECURE_STATE_PMIC_INS_SHIFT (4U) -#define SEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_INS_SHIFT) & SEC_SECURE_STATE_PMIC_INS_MASK) -#define SEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_INS_MASK) >> SEC_SECURE_STATE_PMIC_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define SEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define SEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define SEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define SEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) >> SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define SEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define SEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define SEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define SEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define SEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define SEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define SEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define SEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define SEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define SEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define SEC_EVENT_EVENT_SHIFT (16U) -#define SEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & SEC_EVENT_EVENT_MASK) >> SEC_EVENT_EVENT_SHIFT) - -/* - * PMIC_ESC_NSC (RO) - * - * PMIC is escalating non-secure event - */ -#define SEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) -#define SEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) -#define SEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_NSC_MASK) >> SEC_EVENT_PMIC_ESC_NSC_SHIFT) - -/* - * PMIC_ESC_SEC (RO) - * - * PMIC is escalting secure event - */ -#define SEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) -#define SEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) -#define SEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_SEC_MASK) >> SEC_EVENT_PMIC_ESC_SEC_SHIFT) - -/* Bitfield definition for register: LIFECYCLE */ -/* - * LIFECYCLE (RO) - * - * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, - * bit0: lifecycle_unknow - */ -#define SEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) -#define SEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) -#define SEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & SEC_LIFECYCLE_LIFECYCLE_MASK) >> SEC_LIFECYCLE_LIFECYCLE_SHIFT) - - - - -#endif /* HPM_SEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_smix_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_smix_regs.h deleted file mode 100644 index a4a106b17c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_smix_regs.h +++ /dev/null @@ -1,1018 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SMIX_H -#define HPM_SMIX_H - -typedef struct { - __R uint32_t DMAC_ID; /* 0x0: DMAC_ID Register */ - __RW uint32_t DMAC_TC_ST; /* 0x4: Transfer Complete Status */ - __RW uint32_t DMAC_ABRT_ST; /* 0x8: Transfer Abort Status */ - __RW uint32_t DMAC_ERR_ST; /* 0xC: Transfer Error Status */ - __R uint8_t RESERVED0[16]; /* 0x10 - 0x1F: Reserved */ - __RW uint32_t DMAC_CTRL; /* 0x20: Control Register */ - __W uint32_t DMAC_ABRT_CMD; /* 0x24: Abort Command Register */ - __R uint8_t RESERVED1[12]; /* 0x28 - 0x33: Reserved */ - __RW uint32_t DMAC_CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED2[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTL; /* 0x40: Channel N Control Register */ - __RW uint32_t BURST_COUNT; /* 0x44: Channel N Source Total Beats Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel N Source Register */ - __R uint8_t RESERVED0[4]; /* 0x4C - 0x4F: Reserved */ - __RW uint32_t DSTADDR; /* 0x50: Channel N Destination Register */ - __R uint8_t RESERVED1[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t LLP; /* 0x58: Channel N Linked List Pointer Register */ - __R uint8_t RESERVED2[4]; /* 0x5C - 0x5F: Reserved */ - } DMA_CH[26]; - __R uint8_t RESERVED3[1152]; /* 0x380 - 0x7FF: Reserved */ - __RW uint32_t CALSAT_ST; /* 0x800: SMIX Cal Saturation Status Register */ - __RW uint32_t FDOT_DONE_ST; /* 0x804: SMIX Fade-Out Done Status Register */ - __R uint32_t DATA_ST; /* 0x808: SMIX Data Status Register */ - __R uint8_t RESERVED4[52]; /* 0x80C - 0x83F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x840: SMIX Dstination N Control Register */ - __RW uint32_t GAIN; /* 0x844: SMIX Dstination N Gain Register */ - __RW uint32_t BUFSIZE; /* 0x848: SMIX Dstination N Max Index Register */ - __RW uint32_t FADEIN; /* 0x84C: SMIX Dstination N Fade-In Configuration Register */ - __RW uint32_t FADEOUT; /* 0x850: SMIX Dstination N Fade-Out Configuration Register */ - __R uint32_t ST; /* 0x854: SMIX Dstination N Status Register */ - __R uint32_t DATA; /* 0x858: SMIX Dstination N Data Out Register */ - __R uint8_t RESERVED0[4]; /* 0x85C - 0x85F: Reserved */ - __RW uint32_t SOURCE_EN; /* 0x860: SMIX Dstination N Source Enable Register */ - __RW uint32_t SOURCE_ACT; /* 0x864: SMIX Dstination N Source Activation Register */ - __RW uint32_t SOURCE_DEACT; /* 0x868: SMIX Dstination N Source De-Activation Register */ - __RW uint32_t SOURCE_FADEIN_CTRL; /* 0x86C: SMIX Dstination N Source Fade-in Control Register */ - __R uint32_t DEACT_ST; /* 0x870: SMIX Dstination N Source Deactivation Status Register */ - __RW uint32_t SOURCE_MFADEOUT_CTRL; /* 0x874: SMIX Dstination N Source Manual Fade-out Control Register */ - __R uint8_t RESERVED1[8]; /* 0x878 - 0x87F: Reserved */ - } DST_CH[2]; - __R uint8_t RESERVED5[64]; /* 0x8C0 - 0x8FF: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x900: SMIX Source N Control Register */ - __RW uint32_t GAIN; /* 0x904: SMIX Source N Gain Register */ - __RW uint32_t FADEIN; /* 0x908: SMIX Source N Fade-in Control Register */ - __RW uint32_t FADEOUT; /* 0x90C: SMIX Source N Fade-out Control Register */ - __RW uint32_t BUFSIZE; /* 0x910: SMIX Source N Buffer Size Register */ - __RW uint32_t ST; /* 0x914: SMIX Source N Status Register */ - __W uint32_t DATA; /* 0x918: SMIX Source N Data Input Register */ - __R uint8_t RESERVED0[4]; /* 0x91C - 0x91F: Reserved */ - } SOURCE_CH[14]; -} SMIX_Type; - - -/* Bitfield definition for register: DMAC_ID */ -/* - * REV (RO) - * - * Revision - */ -#define SMIX_DMAC_ID_REV_MASK (0x7FFFFUL) -#define SMIX_DMAC_ID_REV_SHIFT (0U) -#define SMIX_DMAC_ID_REV_GET(x) (((uint32_t)(x) & SMIX_DMAC_ID_REV_MASK) >> SMIX_DMAC_ID_REV_SHIFT) - -/* Bitfield definition for register: DMAC_TC_ST */ -/* - * CH (W1C) - * - * The terminal count status is set when a channel transfer finishes without abort or error events - */ -#define SMIX_DMAC_TC_ST_CH_MASK (0x3FFFFFFUL) -#define SMIX_DMAC_TC_ST_CH_SHIFT (0U) -#define SMIX_DMAC_TC_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_TC_ST_CH_SHIFT) & SMIX_DMAC_TC_ST_CH_MASK) -#define SMIX_DMAC_TC_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_TC_ST_CH_MASK) >> SMIX_DMAC_TC_ST_CH_SHIFT) - -/* Bitfield definition for register: DMAC_ABRT_ST */ -/* - * CH (W1C) - * - * The abort status is set when a channel transfer is aborted - */ -#define SMIX_DMAC_ABRT_ST_CH_MASK (0x3FFFFFFUL) -#define SMIX_DMAC_ABRT_ST_CH_SHIFT (0U) -#define SMIX_DMAC_ABRT_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_ST_CH_SHIFT) & SMIX_DMAC_ABRT_ST_CH_MASK) -#define SMIX_DMAC_ABRT_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_ST_CH_MASK) >> SMIX_DMAC_ABRT_ST_CH_SHIFT) - -/* Bitfield definition for register: DMAC_ERR_ST */ -/* - * CH (W1C) - * - * The error status is set when a channel transfer encounters the following error events: - * . Bus error - * . Unaligned address - * . Unaligned transfer width - * . Reserved configuration - */ -#define SMIX_DMAC_ERR_ST_CH_MASK (0x3FFFFFFUL) -#define SMIX_DMAC_ERR_ST_CH_SHIFT (0U) -#define SMIX_DMAC_ERR_ST_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ERR_ST_CH_SHIFT) & SMIX_DMAC_ERR_ST_CH_MASK) -#define SMIX_DMAC_ERR_ST_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ERR_ST_CH_MASK) >> SMIX_DMAC_ERR_ST_CH_SHIFT) - -/* Bitfield definition for register: DMAC_CTRL */ -/* - * SRST (RW) - * - * Software Reset - */ -#define SMIX_DMAC_CTRL_SRST_MASK (0x1U) -#define SMIX_DMAC_CTRL_SRST_SHIFT (0U) -#define SMIX_DMAC_CTRL_SRST_SET(x) (((uint32_t)(x) << SMIX_DMAC_CTRL_SRST_SHIFT) & SMIX_DMAC_CTRL_SRST_MASK) -#define SMIX_DMAC_CTRL_SRST_GET(x) (((uint32_t)(x) & SMIX_DMAC_CTRL_SRST_MASK) >> SMIX_DMAC_CTRL_SRST_SHIFT) - -/* Bitfield definition for register: DMAC_ABRT_CMD */ -/* - * CH (WO) - * - * Write 1 to force the corresponding channel into abort status - */ -#define SMIX_DMAC_ABRT_CMD_CH_MASK (0x3FFFFFFUL) -#define SMIX_DMAC_ABRT_CMD_CH_SHIFT (0U) -#define SMIX_DMAC_ABRT_CMD_CH_SET(x) (((uint32_t)(x) << SMIX_DMAC_ABRT_CMD_CH_SHIFT) & SMIX_DMAC_ABRT_CMD_CH_MASK) -#define SMIX_DMAC_ABRT_CMD_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_ABRT_CMD_CH_MASK) >> SMIX_DMAC_ABRT_CMD_CH_SHIFT) - -/* Bitfield definition for register: DMAC_CHEN */ -/* - * CH (RO) - * - * Write 1 to enable the corresponding channel - */ -#define SMIX_DMAC_CHEN_CH_MASK (0x3FFFFFFUL) -#define SMIX_DMAC_CHEN_CH_SHIFT (0U) -#define SMIX_DMAC_CHEN_CH_GET(x) (((uint32_t)(x) & SMIX_DMAC_CHEN_CH_MASK) >> SMIX_DMAC_CHEN_CH_SHIFT) - -/* Bitfield definition for register of struct array DMA_CH: CTL */ -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define SMIX_DMA_CH_CTL_SRCREQSEL_MASK (0x7C000000UL) -#define SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT (26U) -#define SMIX_DMA_CH_CTL_SRCREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) -#define SMIX_DMA_CH_CTL_SRCREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCREQSEL_MASK) >> SMIX_DMA_CH_CTL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define SMIX_DMA_CH_CTL_DSTREQSEL_MASK (0x3E00000UL) -#define SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT (21U) -#define SMIX_DMA_CH_CTL_DSTREQSEL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) -#define SMIX_DMA_CH_CTL_DSTREQSEL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTREQSEL_MASK) >> SMIX_DMA_CH_CTL_DSTREQSEL_SHIFT) - -/* - * PRIORITY (RW) - * - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define SMIX_DMA_CH_CTL_PRIORITY_MASK (0x80000UL) -#define SMIX_DMA_CH_CTL_PRIORITY_SHIFT (19U) -#define SMIX_DMA_CH_CTL_PRIORITY_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_PRIORITY_SHIFT) & SMIX_DMA_CH_CTL_PRIORITY_MASK) -#define SMIX_DMA_CH_CTL_PRIORITY_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_PRIORITY_MASK) >> SMIX_DMA_CH_CTL_PRIORITY_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * 0x0: 1 beat per transfer - * 0x1: 2 beats per transfer - * 0x2: 4 beats per transfer - * 0x3: 8 beats per transfer - * 0x4: 16 beats per transfer - * 0x5: 32 beats per transfer - * 0x6: 64 beats per transfer - * 0x7: 128 beats per transfer - */ -#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK (0x78000UL) -#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT (15U) -#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) -#define SMIX_DMA_CH_CTL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCBURSTSIZE_MASK) >> SMIX_DMA_CH_CTL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source Transfer Beat Size: - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - */ -#define SMIX_DMA_CH_CTL_SRCWIDTH_MASK (0x6000U) -#define SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT (13U) -#define SMIX_DMA_CH_CTL_SRCWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) -#define SMIX_DMA_CH_CTL_SRCWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCWIDTH_MASK) >> SMIX_DMA_CH_CTL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination Transfer Beat Size: - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - */ -#define SMIX_DMA_CH_CTL_DSTWIDTH_MASK (0x1800U) -#define SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT (11U) -#define SMIX_DMA_CH_CTL_DSTWIDTH_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) -#define SMIX_DMA_CH_CTL_DSTWIDTH_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTWIDTH_MASK) >> SMIX_DMA_CH_CTL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * DMA Source handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define SMIX_DMA_CH_CTL_SRCMODE_MASK (0x400U) -#define SMIX_DMA_CH_CTL_SRCMODE_SHIFT (10U) -#define SMIX_DMA_CH_CTL_SRCMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCMODE_SHIFT) & SMIX_DMA_CH_CTL_SRCMODE_MASK) -#define SMIX_DMA_CH_CTL_SRCMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCMODE_MASK) >> SMIX_DMA_CH_CTL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * DMA Destination handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - */ -#define SMIX_DMA_CH_CTL_DSTMODE_MASK (0x200U) -#define SMIX_DMA_CH_CTL_DSTMODE_SHIFT (9U) -#define SMIX_DMA_CH_CTL_DSTMODE_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTMODE_SHIFT) & SMIX_DMA_CH_CTL_DSTMODE_MASK) -#define SMIX_DMA_CH_CTL_DSTMODE_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTMODE_MASK) >> SMIX_DMA_CH_CTL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers an error exception - */ -#define SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK (0x180U) -#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT (7U) -#define SMIX_DMA_CH_CTL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) -#define SMIX_DMA_CH_CTL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_SRCADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers an error exception - */ -#define SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK (0x60U) -#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT (5U) -#define SMIX_DMA_CH_CTL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) -#define SMIX_DMA_CH_CTL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_DSTADDRCTRL_MASK) >> SMIX_DMA_CH_CTL_DSTADDRCTRL_SHIFT) - -/* - * ABRT_INT_EN (RW) - * - * Abort interrupt enable - */ -#define SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK (0x8U) -#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT (3U) -#define SMIX_DMA_CH_CTL_ABRT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) -#define SMIX_DMA_CH_CTL_ABRT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ABRT_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ABRT_INT_EN_SHIFT) - -/* - * ERR_INT_EN (RW) - * - * Err interrupt enable - */ -#define SMIX_DMA_CH_CTL_ERR_INT_EN_MASK (0x4U) -#define SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT (2U) -#define SMIX_DMA_CH_CTL_ERR_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) -#define SMIX_DMA_CH_CTL_ERR_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_ERR_INT_EN_MASK) >> SMIX_DMA_CH_CTL_ERR_INT_EN_SHIFT) - -/* - * TC_INT_EN (RW) - * - * TC interrupt enable - */ -#define SMIX_DMA_CH_CTL_TC_INT_EN_MASK (0x2U) -#define SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT (1U) -#define SMIX_DMA_CH_CTL_TC_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) -#define SMIX_DMA_CH_CTL_TC_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_TC_INT_EN_MASK) >> SMIX_DMA_CH_CTL_TC_INT_EN_SHIFT) - -/* - * EN (RW) - * - * channel enable bit - */ -#define SMIX_DMA_CH_CTL_EN_MASK (0x1U) -#define SMIX_DMA_CH_CTL_EN_SHIFT (0U) -#define SMIX_DMA_CH_CTL_EN_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_CTL_EN_SHIFT) & SMIX_DMA_CH_CTL_EN_MASK) -#define SMIX_DMA_CH_CTL_EN_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_CTL_EN_MASK) >> SMIX_DMA_CH_CTL_EN_SHIFT) - -/* Bitfield definition for register of struct array DMA_CH: BURST_COUNT */ -/* - * NUM (RW) - * - * the total number of source beats - */ -#define SMIX_DMA_CH_BURST_COUNT_NUM_MASK (0xFFFFFFFFUL) -#define SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT (0U) -#define SMIX_DMA_CH_BURST_COUNT_NUM_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) -#define SMIX_DMA_CH_BURST_COUNT_NUM_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_BURST_COUNT_NUM_MASK) >> SMIX_DMA_CH_BURST_COUNT_NUM_SHIFT) - -/* Bitfield definition for register of struct array DMA_CH: SRCADDR */ -/* - * PTR (RW) - * - * source address - */ -#define SMIX_DMA_CH_SRCADDR_PTR_MASK (0xFFFFFFFFUL) -#define SMIX_DMA_CH_SRCADDR_PTR_SHIFT (0U) -#define SMIX_DMA_CH_SRCADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_SRCADDR_PTR_SHIFT) & SMIX_DMA_CH_SRCADDR_PTR_MASK) -#define SMIX_DMA_CH_SRCADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_SRCADDR_PTR_MASK) >> SMIX_DMA_CH_SRCADDR_PTR_SHIFT) - -/* Bitfield definition for register of struct array DMA_CH: DSTADDR */ -/* - * PTR (RW) - * - * destination address - */ -#define SMIX_DMA_CH_DSTADDR_PTR_MASK (0xFFFFFFFFUL) -#define SMIX_DMA_CH_DSTADDR_PTR_SHIFT (0U) -#define SMIX_DMA_CH_DSTADDR_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_DSTADDR_PTR_SHIFT) & SMIX_DMA_CH_DSTADDR_PTR_MASK) -#define SMIX_DMA_CH_DSTADDR_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_DSTADDR_PTR_MASK) >> SMIX_DMA_CH_DSTADDR_PTR_SHIFT) - -/* Bitfield definition for register of struct array DMA_CH: LLP */ -/* - * PTR (RW) - * - * the address pointer for the linked list descriptor - */ -#define SMIX_DMA_CH_LLP_PTR_MASK (0xFFFFFFFFUL) -#define SMIX_DMA_CH_LLP_PTR_SHIFT (0U) -#define SMIX_DMA_CH_LLP_PTR_SET(x) (((uint32_t)(x) << SMIX_DMA_CH_LLP_PTR_SHIFT) & SMIX_DMA_CH_LLP_PTR_MASK) -#define SMIX_DMA_CH_LLP_PTR_GET(x) (((uint32_t)(x) & SMIX_DMA_CH_LLP_PTR_MASK) >> SMIX_DMA_CH_LLP_PTR_SHIFT) - -/* Bitfield definition for register: CALSAT_ST */ -/* - * DST (W1C) - * - * DST CAL_SAT_ERR. W1C - */ -#define SMIX_CALSAT_ST_DST_MASK (0xC0000000UL) -#define SMIX_CALSAT_ST_DST_SHIFT (30U) -#define SMIX_CALSAT_ST_DST_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_DST_SHIFT) & SMIX_CALSAT_ST_DST_MASK) -#define SMIX_CALSAT_ST_DST_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_DST_MASK) >> SMIX_CALSAT_ST_DST_SHIFT) - -/* - * SRC (W1C) - * - * SRC CAL_SAT_ERR. W1C - */ -#define SMIX_CALSAT_ST_SRC_MASK (0x3FFFU) -#define SMIX_CALSAT_ST_SRC_SHIFT (0U) -#define SMIX_CALSAT_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_CALSAT_ST_SRC_SHIFT) & SMIX_CALSAT_ST_SRC_MASK) -#define SMIX_CALSAT_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_CALSAT_ST_SRC_MASK) >> SMIX_CALSAT_ST_SRC_SHIFT) - -/* Bitfield definition for register: FDOT_DONE_ST */ -/* - * DST (W1C) - * - * DST fadeout done. W1C - */ -#define SMIX_FDOT_DONE_ST_DST_MASK (0xC0000000UL) -#define SMIX_FDOT_DONE_ST_DST_SHIFT (30U) -#define SMIX_FDOT_DONE_ST_DST_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_DST_SHIFT) & SMIX_FDOT_DONE_ST_DST_MASK) -#define SMIX_FDOT_DONE_ST_DST_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_DST_MASK) >> SMIX_FDOT_DONE_ST_DST_SHIFT) - -/* - * SRC (W1C) - * - * SRC fadeout done. W1C - */ -#define SMIX_FDOT_DONE_ST_SRC_MASK (0x3FFFU) -#define SMIX_FDOT_DONE_ST_SRC_SHIFT (0U) -#define SMIX_FDOT_DONE_ST_SRC_SET(x) (((uint32_t)(x) << SMIX_FDOT_DONE_ST_SRC_SHIFT) & SMIX_FDOT_DONE_ST_SRC_MASK) -#define SMIX_FDOT_DONE_ST_SRC_GET(x) (((uint32_t)(x) & SMIX_FDOT_DONE_ST_SRC_MASK) >> SMIX_FDOT_DONE_ST_SRC_SHIFT) - -/* Bitfield definition for register: DATA_ST */ -/* - * DST_DA (RO) - * - * DST data available - */ -#define SMIX_DATA_ST_DST_DA_MASK (0xC0000000UL) -#define SMIX_DATA_ST_DST_DA_SHIFT (30U) -#define SMIX_DATA_ST_DST_DA_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_DA_MASK) >> SMIX_DATA_ST_DST_DA_SHIFT) - -/* - * DST_UNDL (RO) - * - * DST data underflow - */ -#define SMIX_DATA_ST_DST_UNDL_MASK (0x30000000UL) -#define SMIX_DATA_ST_DST_UNDL_SHIFT (28U) -#define SMIX_DATA_ST_DST_UNDL_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_DST_UNDL_MASK) >> SMIX_DATA_ST_DST_UNDL_SHIFT) - -/* - * SRC_DN (RO) - * - * SRC data needed - */ -#define SMIX_DATA_ST_SRC_DN_MASK (0x3FFFU) -#define SMIX_DATA_ST_SRC_DN_SHIFT (0U) -#define SMIX_DATA_ST_SRC_DN_GET(x) (((uint32_t)(x) & SMIX_DATA_ST_SRC_DN_MASK) >> SMIX_DATA_ST_SRC_DN_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: CTRL */ -/* - * DATA_UNFL_IE (RW) - * - * Data Underflow Error IntEn - */ -#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK (0x100000UL) -#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT (20U) -#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) -#define SMIX_DST_CH_CTRL_DATA_UNFL_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DATA_UNFL_IE_MASK) >> SMIX_DST_CH_CTRL_DATA_UNFL_IE_SHIFT) - -/* - * THRSH (RW) - * - * FIFO threshold for DMA or Int. >= will generate req. Must be greater or equal than 8. The read burst of DMA should make the fillings in the buffer be greater than 4. - */ -#define SMIX_DST_CH_CTRL_THRSH_MASK (0xFF000UL) -#define SMIX_DST_CH_CTRL_THRSH_SHIFT (12U) -#define SMIX_DST_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_THRSH_SHIFT) & SMIX_DST_CH_CTRL_THRSH_MASK) -#define SMIX_DST_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_THRSH_MASK) >> SMIX_DST_CH_CTRL_THRSH_SHIFT) - -/* - * CALSAT_INT_EN (RW) - * - * Cal Saturation IntEn - */ -#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK (0x800U) -#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT (11U) -#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) -#define SMIX_DST_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_DST_CH_CTRL_CALSAT_INT_EN_SHIFT) - -/* - * DA_INT_EN (RW) - * - * Data Available IntEn - */ -#define SMIX_DST_CH_CTRL_DA_INT_EN_MASK (0x400U) -#define SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT (10U) -#define SMIX_DST_CH_CTRL_DA_INT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) -#define SMIX_DST_CH_CTRL_DA_INT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DA_INT_EN_MASK) >> SMIX_DST_CH_CTRL_DA_INT_EN_SHIFT) - -/* - * ADEACTFADEOUT_EN (RW) - * - * AutoDeactAfterFadeOut_En: - * Asserted to enter de-activated mode after fade-out done - */ -#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK (0x200U) -#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT (9U) -#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) -#define SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_MASK) >> SMIX_DST_CH_CTRL_ADEACTFADEOUT_EN_SHIFT) - -/* - * FADEOUT_DONE_IE (RW) - * - * Fade-Out interrupt enable - */ -#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK (0x100U) -#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT (8U) -#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) -#define SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_DST_CH_CTRL_FADEOUT_DONE_IE_SHIFT) - -/* - * DST_DEACT (RW) - * - * de-activate the destination channel - */ -#define SMIX_DST_CH_CTRL_DST_DEACT_MASK (0x80U) -#define SMIX_DST_CH_CTRL_DST_DEACT_SHIFT (7U) -#define SMIX_DST_CH_CTRL_DST_DEACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) -#define SMIX_DST_CH_CTRL_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_DEACT_MASK) >> SMIX_DST_CH_CTRL_DST_DEACT_SHIFT) - -/* - * DST_ACT (RW) - * - * activate the destination channel - */ -#define SMIX_DST_CH_CTRL_DST_ACT_MASK (0x40U) -#define SMIX_DST_CH_CTRL_DST_ACT_SHIFT (6U) -#define SMIX_DST_CH_CTRL_DST_ACT_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_ACT_SHIFT) & SMIX_DST_CH_CTRL_DST_ACT_MASK) -#define SMIX_DST_CH_CTRL_DST_ACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_ACT_MASK) >> SMIX_DST_CH_CTRL_DST_ACT_SHIFT) - -/* - * DSTFADOUT_MEN (RW) - * - * Manual FadeOut_Ctrl for destionation. Auto clear. - */ -#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK (0x20U) -#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT (5U) -#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) -#define SMIX_DST_CH_CTRL_DSTFADOUT_MEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_MEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_MEN_SHIFT) - -/* - * DSTFADOUT_AEN (RW) - * - * Automatically FadeOut_Ctrl for destionation. Only effective after DST_AFADEOUT is assigned a non-zero value - */ -#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK (0x10U) -#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT (4U) -#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) -#define SMIX_DST_CH_CTRL_DSTFADOUT_AEN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADOUT_AEN_MASK) >> SMIX_DST_CH_CTRL_DSTFADOUT_AEN_SHIFT) - -/* - * DSTFADIN_EN (RW) - * - * FadeIn_Ctrl for destionation. Auto clear. - */ -#define SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK (0x8U) -#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT (3U) -#define SMIX_DST_CH_CTRL_DSTFADIN_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) -#define SMIX_DST_CH_CTRL_DSTFADIN_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DSTFADIN_EN_MASK) >> SMIX_DST_CH_CTRL_DSTFADIN_EN_SHIFT) - -/* - * DST_EN (RW) - * - * Dst enabled. When disabled, clear the FIFO pointers. - */ -#define SMIX_DST_CH_CTRL_DST_EN_MASK (0x4U) -#define SMIX_DST_CH_CTRL_DST_EN_SHIFT (2U) -#define SMIX_DST_CH_CTRL_DST_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_DST_EN_SHIFT) & SMIX_DST_CH_CTRL_DST_EN_MASK) -#define SMIX_DST_CH_CTRL_DST_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_DST_EN_MASK) >> SMIX_DST_CH_CTRL_DST_EN_SHIFT) - -/* - * SOFTRST (RW) - * - * Soft reset - */ -#define SMIX_DST_CH_CTRL_SOFTRST_MASK (0x2U) -#define SMIX_DST_CH_CTRL_SOFTRST_SHIFT (1U) -#define SMIX_DST_CH_CTRL_SOFTRST_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_SOFTRST_SHIFT) & SMIX_DST_CH_CTRL_SOFTRST_MASK) -#define SMIX_DST_CH_CTRL_SOFTRST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_SOFTRST_MASK) >> SMIX_DST_CH_CTRL_SOFTRST_SHIFT) - -/* - * MIXER_EN (RW) - * - * mixer function enable. - */ -#define SMIX_DST_CH_CTRL_MIXER_EN_MASK (0x1U) -#define SMIX_DST_CH_CTRL_MIXER_EN_SHIFT (0U) -#define SMIX_DST_CH_CTRL_MIXER_EN_SET(x) (((uint32_t)(x) << SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) -#define SMIX_DST_CH_CTRL_MIXER_EN_GET(x) (((uint32_t)(x) & SMIX_DST_CH_CTRL_MIXER_EN_MASK) >> SMIX_DST_CH_CTRL_MIXER_EN_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: GAIN */ -/* - * VAL (RW) - * - * Unsigned Int, with 12 fractional bits. . The top 3 bits are for shift. Same as SHFT_CTR[2:0] - */ -#define SMIX_DST_CH_GAIN_VAL_MASK (0x7FFFU) -#define SMIX_DST_CH_GAIN_VAL_SHIFT (0U) -#define SMIX_DST_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_GAIN_VAL_SHIFT) & SMIX_DST_CH_GAIN_VAL_MASK) -#define SMIX_DST_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_GAIN_VAL_MASK) >> SMIX_DST_CH_GAIN_VAL_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: BUFSIZE */ -/* - * MAX_IDX (RW) - * - * The total length of the dst stream -1. If zero, means there is no end of the stream. - */ -#define SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK (0xFFFFFFFFUL) -#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT (0U) -#define SMIX_DST_CH_BUFSIZE_MAX_IDX_SET(x) (((uint32_t)(x) << SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) -#define SMIX_DST_CH_BUFSIZE_MAX_IDX_GET(x) (((uint32_t)(x) & SMIX_DST_CH_BUFSIZE_MAX_IDX_MASK) >> SMIX_DST_CH_BUFSIZE_MAX_IDX_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: FADEIN */ -/* - * DELTA (RW) - * - * Fade-in delta for linear fading in from 0 to 1 (about at most 20s for 48kHz sampled sound) - * (Using only top 14 bits for mul) - */ -#define SMIX_DST_CH_FADEIN_DELTA_MASK (0xFFFFFUL) -#define SMIX_DST_CH_FADEIN_DELTA_SHIFT (0U) -#define SMIX_DST_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEIN_DELTA_SHIFT) & SMIX_DST_CH_FADEIN_DELTA_MASK) -#define SMIX_DST_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEIN_DELTA_MASK) >> SMIX_DST_CH_FADEIN_DELTA_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: FADEOUT */ -/* - * DELTA (RW) - * - * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 - */ -#define SMIX_DST_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) -#define SMIX_DST_CH_FADEOUT_DELTA_SHIFT (0U) -#define SMIX_DST_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_DST_CH_FADEOUT_DELTA_SHIFT) & SMIX_DST_CH_FADEOUT_DELTA_MASK) -#define SMIX_DST_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_FADEOUT_DELTA_MASK) >> SMIX_DST_CH_FADEOUT_DELTA_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: ST */ -/* - * FIFO_FILLINGS (RO) - * - * destination channel output FIFO fillings - */ -#define SMIX_DST_CH_ST_FIFO_FILLINGS_MASK (0x7FC0U) -#define SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT (6U) -#define SMIX_DST_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_DST_CH_ST_FIFO_FILLINGS_SHIFT) - -/* - * FDOUT_DONE (RO) - * - * Fade-Out Done. W1C - */ -#define SMIX_DST_CH_ST_FDOUT_DONE_MASK (0x20U) -#define SMIX_DST_CH_ST_FDOUT_DONE_SHIFT (5U) -#define SMIX_DST_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_FDOUT_DONE_MASK) >> SMIX_DST_CH_ST_FDOUT_DONE_SHIFT) - -/* - * CALSAT (RO) - * - * Saturate Error Found. W1C - */ -#define SMIX_DST_CH_ST_CALSAT_MASK (0x10U) -#define SMIX_DST_CH_ST_CALSAT_SHIFT (4U) -#define SMIX_DST_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_CALSAT_MASK) >> SMIX_DST_CH_ST_CALSAT_SHIFT) - -/* - * DA (RO) - * - * Data Available - */ -#define SMIX_DST_CH_ST_DA_MASK (0x8U) -#define SMIX_DST_CH_ST_DA_SHIFT (3U) -#define SMIX_DST_CH_ST_DA_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_DA_MASK) >> SMIX_DST_CH_ST_DA_SHIFT) - -/* - * MODE (RO) - * - * The modes are: - * Mode 0: Disabled: after reset. Program the registers, and DSTn_CTRL [DST_EN] to enter Mode 1. - * Mode 1: Enabled and not-activated. wait for DSTn_CTRL [DSTFADIN_EN] or DSTn_CTRL [DST_ACT], jump to Mode 3 or Mode 4 based on whether Fade-in enabled. - * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will send data to DMA. Jump to Mode 4 after fadin op done. - * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will send data to DMA. - * Mode 5: Enabled and activated and fade-out in progress: After faded out OP. Will send data to DMA. Will transfer to mode 6 or mode 7 depending on the DSTn_CTRL [ADeactFadeOut_En] cfg - * Mode 6: Enabled and activated and faded-out: faded out is done. Will send data to DMA. Will transfer to mode 7 if manual deactivated. - * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't send data to DMA. Won't gen data avail signals. Intf register can be programmed. Will change to Mode 3 or Mode 4 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTn_CTRL [DST_EN] is assigned 0. To support a new stream or, to continue the old stream after a pause. - */ -#define SMIX_DST_CH_ST_MODE_MASK (0x7U) -#define SMIX_DST_CH_ST_MODE_SHIFT (0U) -#define SMIX_DST_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_DST_CH_ST_MODE_MASK) >> SMIX_DST_CH_ST_MODE_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: DATA */ -/* - * VAL (RO) - * - * Output data buffer - */ -#define SMIX_DST_CH_DATA_VAL_MASK (0xFFFFFFFFUL) -#define SMIX_DST_CH_DATA_VAL_SHIFT (0U) -#define SMIX_DST_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DATA_VAL_MASK) >> SMIX_DST_CH_DATA_VAL_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: SOURCE_EN */ -/* - * VAL (RW) - * - * After enabled, Data needed req will be asserted. DMA can feed in data. The channel will join in the sum operation of mixer operation. - */ -#define SMIX_DST_CH_SOURCE_EN_VAL_MASK (0xFFU) -#define SMIX_DST_CH_SOURCE_EN_VAL_SHIFT (0U) -#define SMIX_DST_CH_SOURCE_EN_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) -#define SMIX_DST_CH_SOURCE_EN_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_EN_VAL_MASK) >> SMIX_DST_CH_SOURCE_EN_VAL_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: SOURCE_ACT */ -/* - * VAL (WO) - * - * Manually Activate the channel - */ -#define SMIX_DST_CH_SOURCE_ACT_VAL_MASK (0xFFU) -#define SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT (0U) -#define SMIX_DST_CH_SOURCE_ACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) -#define SMIX_DST_CH_SOURCE_ACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_ACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_ACT_VAL_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: SOURCE_DEACT */ -/* - * VAL (WO) - * - * Manually DeActivate the channel - */ -#define SMIX_DST_CH_SOURCE_DEACT_VAL_MASK (0xFFU) -#define SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT (0U) -#define SMIX_DST_CH_SOURCE_DEACT_VAL_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) -#define SMIX_DST_CH_SOURCE_DEACT_VAL_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_DEACT_VAL_MASK) >> SMIX_DST_CH_SOURCE_DEACT_VAL_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: SOURCE_FADEIN_CTRL */ -/* - * AOP (RW) - * - * Asserted to start fade-in operation. When the amplification factors are stable, auto clear. - */ -#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK (0xFFU) -#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT (0U) -#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) -#define SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_MASK) >> SMIX_DST_CH_SOURCE_FADEIN_CTRL_AOP_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: DEACT_ST */ -/* - * DST_DEACT (RO) - * - * Asserted when in de-active mode - */ -#define SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK (0x80000000UL) -#define SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT (31U) -#define SMIX_DST_CH_DEACT_ST_DST_DEACT_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_DST_DEACT_MASK) >> SMIX_DST_CH_DEACT_ST_DST_DEACT_SHIFT) - -/* - * SRC_DEACT_ST (RO) - * - * Asserted when in de-active mode - */ -#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK (0xFFU) -#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT (0U) -#define SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_GET(x) (((uint32_t)(x) & SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_MASK) >> SMIX_DST_CH_DEACT_ST_SRC_DEACT_ST_SHIFT) - -/* Bitfield definition for register of struct array DST_CH: SOURCE_MFADEOUT_CTRL */ -/* - * OP (RW) - * - * Asserted to start fade-out operation. When the amplification factors are stable, auto clear. - */ -#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK (0xFFU) -#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT (0U) -#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SET(x) (((uint32_t)(x) << SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) -#define SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_GET(x) (((uint32_t)(x) & SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_MASK) >> SMIX_DST_CH_SOURCE_MFADEOUT_CTRL_OP_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: CTRL */ -/* - * FIFO_RESET (RW) - * - * Asserted to reset FIFO pointer. Cleared to exit reset state. - */ -#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK (0x200000UL) -#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT (21U) -#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) -#define SMIX_SOURCE_CH_CTRL_FIFO_RESET_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FIFO_RESET_MASK) >> SMIX_SOURCE_CH_CTRL_FIFO_RESET_SHIFT) - -/* - * THRSH (RW) - * - * FIFO threshold for DMA or Int. <= will generate req. Must be greater or equal than 8. This threshold is also used to trgger the internal FIR operation. To avoid the reading and writing to the same address in the memory block, the threshold should greater than 4. - */ -#define SMIX_SOURCE_CH_CTRL_THRSH_MASK (0x1FE000UL) -#define SMIX_SOURCE_CH_CTRL_THRSH_SHIFT (13U) -#define SMIX_SOURCE_CH_CTRL_THRSH_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) -#define SMIX_SOURCE_CH_CTRL_THRSH_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_THRSH_MASK) >> SMIX_SOURCE_CH_CTRL_THRSH_SHIFT) - -/* - * CALSAT_INT_EN (RW) - * - * Cal Saturation IntEn - */ -#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK (0x1000U) -#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT (12U) -#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) -#define SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_CALSAT_INT_EN_SHIFT) - -/* - * DN_INT_EN (RW) - * - * Data Needed IntEn - */ -#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK (0x800U) -#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT (11U) -#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) -#define SMIX_SOURCE_CH_CTRL_DN_INT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_DN_INT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_DN_INT_EN_SHIFT) - -/* - * SHFT_CTRL (RW) - * - * Shift operation after FIR - * 0: no shift (when no upsampling or up-sampling-by-2 or up-sampling-by-3) - * 1: left-shift-by-1 (when up-sampling-by-4 or up-sampling-by-6) - * 2: left-shift-by-1 (when up-sampling-by-8 or up-sampling-by-12) - * 7: /2 (when rate /2) - * Other n: shift-left-by-n, but not suggested to be used. - */ -#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK (0x700U) -#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT (8U) -#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) -#define SMIX_SOURCE_CH_CTRL_SHFT_CTRL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_SHFT_CTRL_MASK) >> SMIX_SOURCE_CH_CTRL_SHFT_CTRL_SHIFT) - -/* - * AUTODEACTAFTERFADEOUT_EN (RW) - * - * Asserted to enter de-activated mode after fade-out done - */ -#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK (0x80U) -#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT (7U) -#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) -#define SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_MASK) >> SMIX_SOURCE_CH_CTRL_AUTODEACTAFTERFADEOUT_EN_SHIFT) - -/* - * FADEOUT_DONE_IE (RW) - * - * Fade-Out interrupt enable - */ -#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK (0x40U) -#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT (6U) -#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) -#define SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_MASK) >> SMIX_SOURCE_CH_CTRL_FADEOUT_DONE_IE_SHIFT) - -/* - * RATECONV (RW) - * - * 0: no rate conversion - * 1: up-conversion x2 - * 2: up-conversion x3 - * 3: up-conversion x4 - * 4: up-conversion x6 - * 5: up-conversion x8 - * 6: up-conversion x12 - * 7: down-conversion /2 - */ -#define SMIX_SOURCE_CH_CTRL_RATECONV_MASK (0x7U) -#define SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT (0U) -#define SMIX_SOURCE_CH_CTRL_RATECONV_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) -#define SMIX_SOURCE_CH_CTRL_RATECONV_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_CTRL_RATECONV_MASK) >> SMIX_SOURCE_CH_CTRL_RATECONV_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: GAIN */ -/* - * VAL (RW) - * - * Unsigned Int, with 12 fractional bits. The top 3 bits are for shift. Same as SHFT_CTR[2:0]. - */ -#define SMIX_SOURCE_CH_GAIN_VAL_MASK (0x7FFFU) -#define SMIX_SOURCE_CH_GAIN_VAL_SHIFT (0U) -#define SMIX_SOURCE_CH_GAIN_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_GAIN_VAL_SHIFT) & SMIX_SOURCE_CH_GAIN_VAL_MASK) -#define SMIX_SOURCE_CH_GAIN_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_GAIN_VAL_MASK) >> SMIX_SOURCE_CH_GAIN_VAL_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: FADEIN */ -/* - * DELTA (RW) - * - * Fade -in confg. - */ -#define SMIX_SOURCE_CH_FADEIN_DELTA_MASK (0xFFFFFUL) -#define SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT (0U) -#define SMIX_SOURCE_CH_FADEIN_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) -#define SMIX_SOURCE_CH_FADEIN_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEIN_DELTA_MASK) >> SMIX_SOURCE_CH_FADEIN_DELTA_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: FADEOUT */ -/* - * DELTA (RW) - * - * Fade out in 2^DELTA samples. Now DELTA can be at most 14。 - */ -#define SMIX_SOURCE_CH_FADEOUT_DELTA_MASK (0xFFFFFUL) -#define SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT (0U) -#define SMIX_SOURCE_CH_FADEOUT_DELTA_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) -#define SMIX_SOURCE_CH_FADEOUT_DELTA_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_FADEOUT_DELTA_MASK) >> SMIX_SOURCE_CH_FADEOUT_DELTA_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: BUFSIZE */ -/* - * MAXIDX (RW) - * - * unit as 16-bits per sample. Zero means no length limit. = Act Len-1. - * The actual length is the up_rate*(input_data_length-4). - * If the filter processing is down-sampling, the value of up_rate above is 1. - * If the filter processing is up-sampling, the value of up_rate above is the up-sampling rate. - */ -#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK (0xFFFFFFFFUL) -#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT (0U) -#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) -#define SMIX_SOURCE_CH_BUFSIZE_MAXIDX_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_BUFSIZE_MAXIDX_MASK) >> SMIX_SOURCE_CH_BUFSIZE_MAXIDX_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: ST */ -/* - * FIFO_FILLINGS (RO) - * - * The fillings of input FIFO. - */ -#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK (0x7FC00UL) -#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT (10U) -#define SMIX_SOURCE_CH_ST_FIFO_FILLINGS_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIFO_FILLINGS_MASK) >> SMIX_SOURCE_CH_ST_FIFO_FILLINGS_SHIFT) - -/* - * FDOUT_DONE (W1C) - * - * Fade-Out Done. W1C - */ -#define SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK (0x200U) -#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT (9U) -#define SMIX_SOURCE_CH_ST_FDOUT_DONE_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) -#define SMIX_SOURCE_CH_ST_FDOUT_DONE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FDOUT_DONE_MASK) >> SMIX_SOURCE_CH_ST_FDOUT_DONE_SHIFT) - -/* - * CALSAT (W1C) - * - * Calculation saturation status. W1C - */ -#define SMIX_SOURCE_CH_ST_CALSAT_MASK (0x100U) -#define SMIX_SOURCE_CH_ST_CALSAT_SHIFT (8U) -#define SMIX_SOURCE_CH_ST_CALSAT_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_ST_CALSAT_SHIFT) & SMIX_SOURCE_CH_ST_CALSAT_MASK) -#define SMIX_SOURCE_CH_ST_CALSAT_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_CALSAT_MASK) >> SMIX_SOURCE_CH_ST_CALSAT_SHIFT) - -/* - * DN (RO) - * - * Data needed flag - */ -#define SMIX_SOURCE_CH_ST_DN_MASK (0x80U) -#define SMIX_SOURCE_CH_ST_DN_SHIFT (7U) -#define SMIX_SOURCE_CH_ST_DN_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_DN_MASK) >> SMIX_SOURCE_CH_ST_DN_SHIFT) - -/* - * FIRPHASE (RO) - * - * the poly phase counter - */ -#define SMIX_SOURCE_CH_ST_FIRPHASE_MASK (0x78U) -#define SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT (3U) -#define SMIX_SOURCE_CH_ST_FIRPHASE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_FIRPHASE_MASK) >> SMIX_SOURCE_CH_ST_FIRPHASE_SHIFT) - -/* - * MODE (RO) - * - * The modes are: - * Mode 0: Disabled: after reset. Program the registers, and DSTx_SRC_EN[n] to enter Mode 1. - * Mode 1: Enabled but not activated: After Enabled. Data needed signal can send out, can receive DMA data. Will enter Mode 2 after manual ACT or Fade-in CMD - * Mode 2: Enabled and activated and buffer feed-in in progress: Can not be fade out. Will consume data from DMA. If not enter due to Fade-in CMD, will enter Mode 4, else enter Mode 3. This mode is used to make the channel in MIX only after initial data are ready, thus will not stall mix operation due to the lackness of data of this channel omly. - * Mode 3: Enabled and activated and fade-in in progress: Can not be fade out. Will consume data from DMA. - * Mode 4: Enabled and activated and done fade-in, no fade-out yet: Can be fade out. Will consume data from DMA. - * Mode 5: Enabled and activated and fade-out in progress: After faded out done. Will consume data from DMA. Will transfer to mode 6 or mode 7 depending on the SRCn_CTRL[AutoDeactAfterFadeOut_En] cfg - * Mode 6: Enabled and activated and faded-out: faded out is done. Will consume data from DMA. Will transfer to mode 7 if manual deactivated. - * Mode 7: Enabled and De-activated: If configured to enter this mode, after auto or manuallly fade-out, or after manual de-activated. Won't consume data from DMA. Won't gen data needed signals. Intf register can be programmed. Will change to Mode 2 after manual ACT or Fade-in CMD. Will transfer to Mode 0 if DSTx_SRC_EN[n] is assigned 0. To support a new stream or, to continue the old stream after a pause. - */ -#define SMIX_SOURCE_CH_ST_MODE_MASK (0x7U) -#define SMIX_SOURCE_CH_ST_MODE_SHIFT (0U) -#define SMIX_SOURCE_CH_ST_MODE_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_ST_MODE_MASK) >> SMIX_SOURCE_CH_ST_MODE_SHIFT) - -/* Bitfield definition for register of struct array SOURCE_CH: DATA */ -/* - * VAL (WO) - * - * Data input register - */ -#define SMIX_SOURCE_CH_DATA_VAL_MASK (0xFFFFFFFFUL) -#define SMIX_SOURCE_CH_DATA_VAL_SHIFT (0U) -#define SMIX_SOURCE_CH_DATA_VAL_SET(x) (((uint32_t)(x) << SMIX_SOURCE_CH_DATA_VAL_SHIFT) & SMIX_SOURCE_CH_DATA_VAL_MASK) -#define SMIX_SOURCE_CH_DATA_VAL_GET(x) (((uint32_t)(x) & SMIX_SOURCE_CH_DATA_VAL_MASK) >> SMIX_SOURCE_CH_DATA_VAL_SHIFT) - - - -/* DMA_CH register group index macro definition */ -#define SMIX_DMA_CH_0 (0UL) -#define SMIX_DMA_CH_1 (1UL) -#define SMIX_DMA_CH_2 (2UL) -#define SMIX_DMA_CH_3 (3UL) -#define SMIX_DMA_CH_4 (4UL) -#define SMIX_DMA_CH_5 (5UL) -#define SMIX_DMA_CH_6 (6UL) -#define SMIX_DMA_CH_7 (7UL) -#define SMIX_DMA_CH_8 (8UL) -#define SMIX_DMA_CH_9 (9UL) -#define SMIX_DMA_CH_10 (10UL) -#define SMIX_DMA_CH_11 (11UL) -#define SMIX_DMA_CH_12 (12UL) -#define SMIX_DMA_CH_13 (13UL) -#define SMIX_DMA_CH_14 (14UL) -#define SMIX_DMA_CH_15 (15UL) -#define SMIX_DMA_CH_16 (16UL) -#define SMIX_DMA_CH_17 (17UL) -#define SMIX_DMA_CH_18 (18UL) -#define SMIX_DMA_CH_19 (19UL) -#define SMIX_DMA_CH_20 (20UL) -#define SMIX_DMA_CH_21 (21UL) -#define SMIX_DMA_CH_22 (22UL) -#define SMIX_DMA_CH_23 (23UL) -#define SMIX_DMA_CH_24 (24UL) -#define SMIX_DMA_CH_25 (25UL) - -/* DST_CH register group index macro definition */ -#define SMIX_DST_CH_0 (0UL) -#define SMIX_DST_CH_1 (1UL) - -/* SOURCE_CH register group index macro definition */ -#define SMIX_SOURCE_CH_0 (0UL) -#define SMIX_SOURCE_CH_1 (1UL) -#define SMIX_SOURCE_CH_2 (2UL) -#define SMIX_SOURCE_CH_3 (3UL) -#define SMIX_SOURCE_CH_4 (4UL) -#define SMIX_SOURCE_CH_5 (5UL) -#define SMIX_SOURCE_CH_6 (6UL) -#define SMIX_SOURCE_CH_7 (7UL) -#define SMIX_SOURCE_CH_8 (8UL) -#define SMIX_SOURCE_CH_9 (9UL) -#define SMIX_SOURCE_CH_10 (10UL) -#define SMIX_SOURCE_CH_11 (11UL) -#define SMIX_SOURCE_CH_12 (12UL) -#define SMIX_SOURCE_CH_13 (13UL) - - -#endif /* HPM_SMIX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_spi_regs.h deleted file mode 100644 index 204a3dc9961..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_spi_regs.h +++ /dev/null @@ -1,1034 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SPI_H -#define HPM_SPI_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t WR_TRANS_CNT; /* 0x4: Transfer count for write data */ - __RW uint32_t RD_TRANS_CNT; /* 0x8: Transfer count for read data */ - __R uint8_t RESERVED1[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ - __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ - __RW uint32_t CMD; /* 0x24: Command Register */ - __RW uint32_t ADDR; /* 0x28: Address Register */ - __RW uint32_t DATA; /* 0x2C: Data Register */ - __RW uint32_t CTRL; /* 0x30: Control Register */ - __R uint32_t STATUS; /* 0x34: Status Register */ - __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ - __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED3[28]; /* 0x44 - 0x5F: Reserved */ - __RW uint32_t SLVST; /* 0x60: Slave Status Register */ - __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint32_t SLVDATAWCNT; /* 0x68: WCnt */ - __R uint32_t SLVDATARCNT; /* 0x6C: RCnt */ - __R uint8_t RESERVED4[12]; /* 0x70 - 0x7B: Reserved */ - __R uint32_t CONFIG; /* 0x7C: Configuration Register */ -} SPI_Type; - - -/* Bitfield definition for register: WR_TRANS_CNT */ -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_WR_TRANS_CNT_WRTRANCNT_MASK (0xFFFFFFFFUL) -#define SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT (0U) -#define SPI_WR_TRANS_CNT_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) -#define SPI_WR_TRANS_CNT_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) >> SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) - -/* Bitfield definition for register: RD_TRANS_CNT */ -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_RD_TRANS_CNT_RDTRANCNT_MASK (0xFFFFFFFFUL) -#define SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT (0U) -#define SPI_RD_TRANS_CNT_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) -#define SPI_RD_TRANS_CNT_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) >> SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: TRANSFMT */ -/* - * ADDRLEN (RW) - * - * Address length in bytes - * 0x0: 1 byte - * 0x1: 2 bytes - * 0x2: 3 bytes - * 0x3: 4 bytes - */ -#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) -#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) -#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) -#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) - -/* - * DATALEN (RW) - * - * The length of each data unit in bits - * The actual bit number of a data unit is (DataLen + 1) - */ -#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) -#define SPI_TRANSFMT_DATALEN_SHIFT (8U) -#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) -#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) - -/* - * DATAMERGE (RW) - * - * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. - * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. - * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - */ -#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) -#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) -#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) -#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) - -/* - * MOSIBIDIR (RW) - * - * Bi-directional MOSI in regular (single) mode - * 0x0: MOSI is uni-directional signal in regular mode. - * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - */ -#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) -#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) -#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) -#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) - -/* - * LSB (RW) - * - * Transfer data with the least significant bit first - * 0x0: Most significant bit first - * 0x1: Least significant bit first - */ -#define SPI_TRANSFMT_LSB_MASK (0x8U) -#define SPI_TRANSFMT_LSB_SHIFT (3U) -#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) -#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) - -/* - * SLVMODE (RW) - * - * SPI Master/Slave mode selection - * 0x0: Master mode - * 0x1: Slave mode - */ -#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) -#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) -#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) -#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) - -/* - * CPOL (RW) - * - * SPI Clock Polarity - * 0x0: SCLK is LOW in the idle states - * 0x1: SCLK is HIGH in the idle states - */ -#define SPI_TRANSFMT_CPOL_MASK (0x2U) -#define SPI_TRANSFMT_CPOL_SHIFT (1U) -#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) -#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) - -/* - * CPHA (RW) - * - * SPI Clock Phase - * 0x0: Sampling data at odd SCLK edges - * 0x1: Sampling data at even SCLK edges - */ -#define SPI_TRANSFMT_CPHA_MASK (0x1U) -#define SPI_TRANSFMT_CPHA_SHIFT (0U) -#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) -#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) - -/* Bitfield definition for register: DIRECTIO */ -/* - * DIRECTIOEN (RW) - * - * Enable Direct IO - * 0x0: Disable - * 0x1: Enable - */ -#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) -#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) -#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) -#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) - -/* - * HOLD_OE (RW) - * - * Output enable for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) -#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) -#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) -#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) - -/* - * WP_OE (RW) - * - * Output enable for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) -#define SPI_DIRECTIO_WP_OE_SHIFT (20U) -#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) -#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) - -/* - * MISO_OE (RW) - * - * Output enable fo the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) -#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) -#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) -#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) - -/* - * MOSI_OE (RW) - * - * Output enable for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) -#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) -#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) -#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) - -/* - * SCLK_OE (RW) - * - * Output enable for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) -#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) -#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) -#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) - -/* - * CS_OE (RW) - * - * Output enable for SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) -#define SPI_DIRECTIO_CS_OE_SHIFT (16U) -#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) -#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) - -/* - * HOLD_O (RW) - * - * Output value for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) -#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) -#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) -#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) - -/* - * WP_O (RW) - * - * Output value for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_O_MASK (0x1000U) -#define SPI_DIRECTIO_WP_O_SHIFT (12U) -#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) -#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) - -/* - * MISO_O (RW) - * - * Output value for the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_O_MASK (0x800U) -#define SPI_DIRECTIO_MISO_O_SHIFT (11U) -#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) -#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) - -/* - * MOSI_O (RW) - * - * Output value for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) -#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) -#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) -#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) - -/* - * SCLK_O (RW) - * - * Output value for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) -#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) -#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) -#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) - -/* - * CS_O (RW) - * - * Output value for the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_O_MASK (0x100U) -#define SPI_DIRECTIO_CS_O_SHIFT (8U) -#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) -#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) - -/* - * HOLD_I (RO) - * - * Status of the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) -#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) -#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) - -/* - * WP_I (RO) - * - * Status of the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_I_MASK (0x10U) -#define SPI_DIRECTIO_WP_I_SHIFT (4U) -#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) - -/* - * MISO_I (RO) - * - * Status of the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_I_MASK (0x8U) -#define SPI_DIRECTIO_MISO_I_SHIFT (3U) -#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) - -/* - * MOSI_I (RO) - * - * Status of the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) -#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) -#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) - -/* - * SCLK_I (RO) - * - * Status of the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) -#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) -#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) - -/* - * CS_I (RO) - * - * Status of the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_I_MASK (0x1U) -#define SPI_DIRECTIO_CS_I_SHIFT (0U) -#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) - -/* Bitfield definition for register: TRANSCTRL */ -/* - * SLVDATAONLY (RW) - * - * Data-only mode (slave mode only) - * 0x0: Disable the data-only mode - * 0x1: Enable the data-only mode - * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - */ -#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) -#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) -#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) -#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) - -/* - * CMDEN (RW) - * - * SPI command phase enable (Master mode only) - * 0x0: Disable the command phase - * 0x1: Enable the command phase - */ -#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) -#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) -#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) -#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) - -/* - * ADDREN (RW) - * - * SPI address phase enable (Master mode only) - * 0x0: Disable the address phase - * 0x1: Enable the address phase - */ -#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) -#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) -#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) -#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) - -/* - * ADDRFMT (RW) - * - * SPI address phase format (Master mode only) - * 0x0: Address phase is the regular (single) mode - * 0x1: The format of the address phase is the same as the data phase (DualQuad). - */ -#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) -#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) -#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) -#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) - -/* - * TRANSMODE (RW) - * - * Transfer mode - * The transfer sequence could be - * 0x0: Write and read at the same time - * 0x1: Write only - * 0x2: Read only - * 0x3: Write, Read - * 0x4: Read, Write - * 0x5: Write, Dummy, Read - * 0x6: Read, Dummy, Write - * 0x7: None Data (must enable CmdEn or AddrEn in master mode) - * 0x8: Dummy, Write - * 0x9: Dummy, Read - * 0xa~0xf: Reserved - */ -#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) -#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) -#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) -#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) - -/* - * DUALQUAD (RW) - * - * SPI data phase format - * 0x0: Regular (Single) mode - * 0x1: Dual I/O mode - * 0x2: Quad I/O mode - * 0x3: Reserved - */ -#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) -#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) -#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) -#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) - -/* - * TOKENEN (RW) - * - * Token transfer enable (Master mode only) - * Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. - * 0x0: Disable the one-byte special token - * 0x1: Enable the one-byte special token - */ -#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) -#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) -#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) -#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) - -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) -#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) -#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) -#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) - -/* - * TOKENVALUE (RW) - * - * Token value (Master mode only) - * The value of the one-byte special token following the address phase for SPI read transfers. - * 0x0: token value = 0x00 - * 0x1: token value = 0x69 - */ -#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) -#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) -#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) -#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) - -/* - * DUMMYCNT (RW) - * - * Dummy data count. The actual dummy count is (DummyCnt +1). - * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) - * The Data pins are put into the high impedance during the dummy data phase. - * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - */ -#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) -#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) -#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) -#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) - -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) -#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) -#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) -#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * SPI Command - */ -#define SPI_CMD_CMD_MASK (0xFFU) -#define SPI_CMD_CMD_SHIFT (0U) -#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) -#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * SPI Address - * (Master mode only) - */ -#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define SPI_ADDR_ADDR_SHIFT (0U) -#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) -#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Data to transmit or the received data - * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. - * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - */ -#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SPI_DATA_DATA_SHIFT (0U) -#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) -#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * CS_EN (RW) - * - */ -#define SPI_CTRL_CS_EN_MASK (0xF000000UL) -#define SPI_CTRL_CS_EN_SHIFT (24U) -#define SPI_CTRL_CS_EN_SET(x) (((uint32_t)(x) << SPI_CTRL_CS_EN_SHIFT) & SPI_CTRL_CS_EN_MASK) -#define SPI_CTRL_CS_EN_GET(x) (((uint32_t)(x) & SPI_CTRL_CS_EN_MASK) >> SPI_CTRL_CS_EN_SHIFT) - -/* - * TXTHRES (RW) - * - * Transmit (TX) FIFO Threshold - * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - */ -#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) -#define SPI_CTRL_TXTHRES_SHIFT (16U) -#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) -#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) - -/* - * RXTHRES (RW) - * - * Receive (RX) FIFO Threshold - * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - */ -#define SPI_CTRL_RXTHRES_MASK (0xFF00U) -#define SPI_CTRL_RXTHRES_SHIFT (8U) -#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) -#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) - -/* - * TXDMAEN (RW) - * - * TX DMA enable - */ -#define SPI_CTRL_TXDMAEN_MASK (0x10U) -#define SPI_CTRL_TXDMAEN_SHIFT (4U) -#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) -#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) - -/* - * RXDMAEN (RW) - * - * RX DMA enable - */ -#define SPI_CTRL_RXDMAEN_MASK (0x8U) -#define SPI_CTRL_RXDMAEN_SHIFT (3U) -#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) -#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) - -/* - * TXFIFORST (RW) - * - * Transmit FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_TXFIFORST_MASK (0x4U) -#define SPI_CTRL_TXFIFORST_SHIFT (2U) -#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) -#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) - -/* - * RXFIFORST (RW) - * - * Receive FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_RXFIFORST_MASK (0x2U) -#define SPI_CTRL_RXFIFORST_SHIFT (1U) -#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) -#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) - -/* - * SPIRST (RW) - * - * SPI reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_SPIRST_MASK (0x1U) -#define SPI_CTRL_SPIRST_SHIFT (0U) -#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) -#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TXNUM_7_6 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) -#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) -#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) - -/* - * RXNUM_7_6 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) -#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) -#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) - -/* - * TXFULL (RO) - * - * Transmit FIFO Full flag - */ -#define SPI_STATUS_TXFULL_MASK (0x800000UL) -#define SPI_STATUS_TXFULL_SHIFT (23U) -#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) - -/* - * TXEMPTY (RO) - * - * Transmit FIFO Empty flag - */ -#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) -#define SPI_STATUS_TXEMPTY_SHIFT (22U) -#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) - -/* - * TXNUM_5_0 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) -#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) -#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) - -/* - * RXFULL (RO) - * - * Receive FIFO Full flag - */ -#define SPI_STATUS_RXFULL_MASK (0x8000U) -#define SPI_STATUS_RXFULL_SHIFT (15U) -#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) - -/* - * RXEMPTY (RO) - * - * Receive FIFO Empty flag - */ -#define SPI_STATUS_RXEMPTY_MASK (0x4000U) -#define SPI_STATUS_RXEMPTY_SHIFT (14U) -#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) - -/* - * RXNUM_5_0 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) -#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) -#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) - -/* - * SPIACTIVE (RO) - * - * SPI register programming is in progress. - * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. - * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. - * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. - * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - */ -#define SPI_STATUS_SPIACTIVE_MASK (0x1U) -#define SPI_STATUS_SPIACTIVE_SHIFT (0U) -#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) - -/* Bitfield definition for register: INTREN */ -/* - * SLVCMDEN (RW) - * - * Enable the Slave Command Interrupt. - * Control whether interrupts are triggered whenever slave commands are received. - * (Slave mode only) - */ -#define SPI_INTREN_SLVCMDEN_MASK (0x20U) -#define SPI_INTREN_SLVCMDEN_SHIFT (5U) -#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) -#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) - -/* - * ENDINTEN (RW) - * - * Enable the End of SPI Transfer interrupt. - * Control whether interrupts are triggered when SPI transfers end. - * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - */ -#define SPI_INTREN_ENDINTEN_MASK (0x10U) -#define SPI_INTREN_ENDINTEN_SHIFT (4U) -#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) -#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) - -/* - * TXFIFOINTEN (RW) - * - * Enable the SPI Transmit FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - */ -#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) -#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) -#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) -#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) - -/* - * RXFIFOINTEN (RW) - * - * Enable the SPI Receive FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - */ -#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) -#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) -#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) -#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) - -/* - * TXFIFOURINTEN (RW) - * - * Enable the SPI Transmit FIFO Underrun interrupt. - * Control whether interrupts are triggered when the Transmit FIFO run out of data. - * (Slave mode only) - */ -#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) -#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) -#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) -#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) - -/* - * RXFIFOORINTEN (RW) - * - * Enable the SPI Receive FIFO Overrun interrupt. - * Control whether interrupts are triggered when the Receive FIFO overflows. - * (Slave mode only) - */ -#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) -#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) -#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) -#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) - -/* Bitfield definition for register: INTRST */ -/* - * SLVCMDINT (W1C) - * - * Slave Command Interrupt. - * This bit is set when Slave Command interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_SLVCMDINT_MASK (0x20U) -#define SPI_INTRST_SLVCMDINT_SHIFT (5U) -#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) -#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) - -/* - * ENDINT (W1C) - * - * End of SPI Transfer interrupt. - * This bit is set when End of SPI Transfer interrupts occur. - */ -#define SPI_INTRST_ENDINT_MASK (0x10U) -#define SPI_INTRST_ENDINT_SHIFT (4U) -#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) -#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) - -/* - * TXFIFOINT (W1C) - * - * TX FIFO Threshold interrupt. - * This bit is set when TX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_TXFIFOINT_MASK (0x8U) -#define SPI_INTRST_TXFIFOINT_SHIFT (3U) -#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) -#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) - -/* - * RXFIFOINT (W1C) - * - * RX FIFO Threshold interrupt. - * This bit is set when RX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_RXFIFOINT_MASK (0x4U) -#define SPI_INTRST_RXFIFOINT_SHIFT (2U) -#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) -#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) - -/* - * TXFIFOURINT (W1C) - * - * TX FIFO Underrun interrupt. - * This bit is set when TX FIFO Underrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) -#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) -#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) -#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) - -/* - * RXFIFOORINT (W1C) - * - * RX FIFO Overrun interrupt. - * This bit is set when RX FIFO Overrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) -#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) -#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) -#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) - -/* Bitfield definition for register: TIMING */ -/* - * CS2SCLK (RW) - * - * The minimum time between the edges of SPI CS and the edges of SCLK. - * SCLK_period * (CS2SCLK + 1) / 2 - */ -#define SPI_TIMING_CS2SCLK_MASK (0x3000U) -#define SPI_TIMING_CS2SCLK_SHIFT (12U) -#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) -#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) - -/* - * CSHT (RW) - * - * The minimum time that SPI CS should stay HIGH. - * SCLK_period * (CSHT + 1) / 2 - */ -#define SPI_TIMING_CSHT_MASK (0xF00U) -#define SPI_TIMING_CSHT_SHIFT (8U) -#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) -#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) - -/* - * SCLK_DIV (RW) - * - * The clock frequency ratio between the clock source and SPI interface SCLK. - * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) - * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - */ -#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) -#define SPI_TIMING_SCLK_DIV_SHIFT (0U) -#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) -#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) - -/* Bitfield definition for register: SLVST */ -/* - * UNDERRUN (W1C) - * - * Data underrun occurs in the last transaction - */ -#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) -#define SPI_SLVST_UNDERRUN_SHIFT (18U) -#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) -#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) - -/* - * OVERRUN (RW) - * - * Data overrun occurs in the last transaction - */ -#define SPI_SLVST_OVERRUN_MASK (0x20000UL) -#define SPI_SLVST_OVERRUN_SHIFT (17U) -#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) -#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) - -/* - * READY (RW) - * - * Set this bit to indicate that the ATCSPI200 is ready for data transaction. - * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - */ -#define SPI_SLVST_READY_MASK (0x10000UL) -#define SPI_SLVST_READY_SHIFT (16U) -#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) -#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) - -/* - * USR_STATUS (RW) - * - * User defined status flags - */ -#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) -#define SPI_SLVST_USR_STATUS_SHIFT (0U) -#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) -#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) - -/* Bitfield definition for register: SLVDATACNT */ -/* - * WCNT (RO) - * - * Slave transmitted data count - */ -#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) -#define SPI_SLVDATACNT_WCNT_SHIFT (16U) -#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) - -/* - * RCNT (RO) - * - * Slave received data count - */ -#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) -#define SPI_SLVDATACNT_RCNT_SHIFT (0U) -#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) - -/* Bitfield definition for register: SLVDATAWCNT */ -/* - * VAL (RO) - * - */ -#define SPI_SLVDATAWCNT_VAL_MASK (0xFFFFFFFFUL) -#define SPI_SLVDATAWCNT_VAL_SHIFT (0U) -#define SPI_SLVDATAWCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATAWCNT_VAL_MASK) >> SPI_SLVDATAWCNT_VAL_SHIFT) - -/* Bitfield definition for register: SLVDATARCNT */ -/* - * VAL (RO) - * - */ -#define SPI_SLVDATARCNT_VAL_MASK (0xFFFFFFFFUL) -#define SPI_SLVDATARCNT_VAL_SHIFT (0U) -#define SPI_SLVDATARCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATARCNT_VAL_MASK) >> SPI_SLVDATARCNT_VAL_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * SLAVE (RO) - * - * Support for SPI Slave mode - */ -#define SPI_CONFIG_SLAVE_MASK (0x4000U) -#define SPI_CONFIG_SLAVE_SHIFT (14U) -#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) - -/* - * QUADSPI (RO) - * - * Support for Quad I/O SPI - */ -#define SPI_CONFIG_QUADSPI_MASK (0x200U) -#define SPI_CONFIG_QUADSPI_SHIFT (9U) -#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) - -/* - * DUALSPI (RO) - * - * Support for Dual I/O SPI - */ -#define SPI_CONFIG_DUALSPI_MASK (0x100U) -#define SPI_CONFIG_DUALSPI_SHIFT (8U) -#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) - -/* - * TXFIFOSIZE (RO) - * - * Depth of TX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) -#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) -#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) - -/* - * RXFIFOSIZE (RO) - * - * Depth of RX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) -#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) -#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) - - - - -#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sysctl_regs.h deleted file mode 100644 index c751bdf0a1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_sysctl_regs.h +++ /dev/null @@ -1,1297 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYSCTL_H -#define HPM_SYSCTL_H - -typedef struct { - __RW uint32_t RESOURCE[353]; /* 0x0 - 0x580: Resource control register for cpu0_core */ - __R uint8_t RESERVED0[636]; /* 0x584 - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: Group setting */ - __RW uint32_t SET; /* 0x804: Group setting */ - __RW uint32_t CLEAR; /* 0x808: Group setting */ - __RW uint32_t TOGGLE; /* 0x80C: Group setting */ - } GROUP0[4]; - __R uint8_t RESERVED1[192]; /* 0x840 - 0x8FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ - __RW uint32_t SET; /* 0x904: Affiliate of Group */ - __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ - __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ - } AFFILIATE[1]; - __R uint8_t RESERVED2[16]; /* 0x910 - 0x91F: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x920: Retention Control */ - __RW uint32_t SET; /* 0x924: Retention Control */ - __RW uint32_t CLEAR; /* 0x928: Retention Control */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Control */ - } RETENTION[1]; - __R uint8_t RESERVED3[1744]; /* 0x930 - 0xFFF: Reserved */ - struct { - __RW uint32_t STATUS; /* 0x1000: Power Setting */ - __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ - __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ - __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ - } POWER[3]; - __R uint8_t RESERVED4[976]; /* 0x1030 - 0x13FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ - __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ - __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ - __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ - } RESET[5]; - __R uint8_t RESERVED5[944]; /* 0x1450 - 0x17FF: Reserved */ - __RW uint32_t CLOCK[69]; /* 0x1800 - 0x1910: Clock setting */ - __R uint8_t RESERVED6[748]; /* 0x1914 - 0x1BFF: Reserved */ - __RW uint32_t ADCCLK[2]; /* 0x1C00 - 0x1C04: Clock setting */ - __RW uint32_t I2SCLK[4]; /* 0x1C08 - 0x1C14: Clock setting */ - __R uint8_t RESERVED7[1000]; /* 0x1C18 - 0x1FFF: Reserved */ - __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ - __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ - __R uint32_t CURRENT; /* 0x2404: Clock measure result */ - __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ - __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ - __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ - } MONITOR[4]; - __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */ - struct { - __RW uint32_t LP; /* 0x2800: CPU0 LP control */ - __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ - __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ - __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */ - __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */ - __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */ - __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */ - } CPU[1]; -} SYSCTL_Type; - - -/* Bitfield definition for register array: RESOURCE */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any nodes - * 1: any of nodes is changing status - */ -#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) -#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: no change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) -#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) - -/* - * MODE (RW) - * - * resource work mode - * 0:auto turn on and off as system required(recommended) - * 1:always on - * 2:always off - * 3:reserved - */ -#define SYSCTL_RESOURCE_MODE_MASK (0x3U) -#define SYSCTL_RESOURCE_MODE_SHIFT (0U) -#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) -#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) -#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) -#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) -#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: VALUE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * bit0: cpu0 depends on group0 - * bit1: cpu0 depends on group1 - * bit2: cpu0 depends on group2 - * bit3: cpu0 depends on group3 - */ -#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) -#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: SET */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0，each bit represents a group - * 0: no effect - * 1: the group is assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) -#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: the group is not assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) -#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: toggle the result that whether the group is assigned to CPU0 before - */ -#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: VALUE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * bit00: soc_mem is kept on while cpu0 stop - * bit01: soc_ctx is kept on while cpu0 stop - * bit02: cpu0_mem is kept on while cpu0 stop - * bit03: cpu0_ctx is kept on while cpu0 stop - * bit04: con_ctx is kept on while cpu0 stop - * bit05: vis_mem is kept on while cpu0 stop - * bit06: vis_ctx is kept on while cpu0 stop - * bit07: gpu_mem is kept on while cpu0 stop - * bit08: gpu_ctx is kept on while cpu0 stop - * bit09: xtal_hold is kept on while cpu0 stop - * bit10: pll0_hold is kept on while cpu0 stop - * bit11: pll1_hold is kept on while cpu0 stop - * bit12: pll2_hold is kept on while cpu0 stop - * bit13: pll3 is kept on while cpu0 stop - * bit14: pll4 is kept on while cpu0 stop - */ -#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) -#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: SET */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: keep - */ -#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) -#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: CLEAR */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: no keep - */ -#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) -#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: TOGGLE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: toggle the result that whether the resource is kept on while CPU0 stop before - */ -#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) -#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array POWER: STATUS */ -/* - * FLAG (RW) - * - * flag represents power cycle happened from last clear of this bit - * 0: power domain did not edurance power cycle since last clear of this bit - * 1: power domain enduranced power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) -#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) -#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) -#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup power cycle happened from last clear of this bit - * 0: power domain did not edurance wakeup power cycle since last clear of this bit - * 1: power domain enduranced wakeup power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) - -/* - * LF_DISABLE (RO) - * - * low fanout power switch disable - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) - -/* - * LF_ACK (RO) - * - * low fanout power switch feedback - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) -#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) -#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) - -/* Bitfield definition for register of struct array POWER: LF_WAIT */ -/* - * WAIT (RW) - * - * wait time for low fan out power switch turn on, default value is 255 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: OFF_WAIT */ -/* - * WAIT (RW) - * - * wait time for power switch turn off, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONTROL */ -/* - * FLAG (RW) - * - * flag represents reset happened from last clear of this bit - * 0: domain did not edurance reset cycle since last clear of this bit - * 1: domain enduranced reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) -#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup reset happened from last clear of this bit - * 0: domain did not edurance wakeup reset cycle since last clear of this bit - * 1: domain enduranced wakeup reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) - -/* - * HOLD (RW) - * - * perform reset and hold in reset, until ths bit cleared by software - * 0: reset is released for function - * 1: reset is assert and hold - */ -#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) -#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) -#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) -#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) - -/* - * RESET (RW) - * - * perform reset and release imediately - * 0: reset is released - * 1 reset is asserted and will release automatically - */ -#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) -#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) -#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) -#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONFIG */ -/* - * PRE_WAIT (RW) - * - * wait cycle numbers before assert reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) - -/* - * RSTCLK_NUM (RW) - * - * reset clock number(must be even number) - * 0: 0 cycle - * 1: 0 cycles - * 2: 2 cycles - * 3: 2 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) - -/* - * POST_WAIT (RW) - * - * time guard band for reset release - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: COUNTER */ -/* - * COUNTER (RW) - * - * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) -#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) -#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) -#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) - -/* Bitfield definition for register array: CLOCK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) -#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll1_clk0 - * 3:pll1_clk1 - * 4:pll2_clk0 - * 5:pll2_clk1 - * 6:pll3_clk0 - * 7:pll4_clk0 - */ -#define SYSCTL_CLOCK_MUX_MASK (0x700U) -#define SYSCTL_CLOCK_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) -#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) -#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) - -/* Bitfield definition for register array: ADCCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) -#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ana clock N - * 1: axis clock - */ -#define SYSCTL_ADCCLK_MUX_MASK (0x100U) -#define SYSCTL_ADCCLK_MUX_SHIFT (8U) -#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) -#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) - -/* Bitfield definition for register array: I2SCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK) -#define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: aud clock N - * 1: aud clock 0 for others , aud clock 1 for i2s0 - */ -#define SYSCTL_I2SCLK_MUX_MASK (0x100U) -#define SYSCTL_I2SCLK_MUX_SHIFT (8U) -#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) -#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) - -/* Bitfield definition for register: GLOBAL00 */ -/* - * MUX (RW) - * - * global clock override request - * bit0: override to preset0 - * bit1: override to preset1 - * bit2: override to preset2 - * bit3: override to preset3 - * bit4: override to preset4 - * bit5: override to preset5 - * bit6: override to preset6 - * bit7: override to preset7 - */ -#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) -#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) -#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) -#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * VALID (RW) - * - * result is ready for read - * 0: not ready - * 1: result is ready - */ -#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) -#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) -#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) -#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) - -/* - * DIV_BUSY (RO) - * - * divider is applying new setting - */ -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) - -/* - * OUTEN (RW) - * - * enable clock output - */ -#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) -#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) - -/* - * DIV (RW) - * - * output divider - */ -#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) -#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) -#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) - -/* - * HIGH (RW) - * - * clock frequency higher than upper limit - */ -#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) -#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock frequency lower than lower limit - */ -#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) -#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) -#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) -#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) - -/* - * START (RW) - * - * start measurement - */ -#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) -#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) -#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) -#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) - -/* - * MODE (RW) - * - * work mode, - * 0: register value will be compared to measurement - * 1: upper and lower value will be recordered in register - */ -#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) -#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) -#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) -#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) - -/* - * ACCURACY (RW) - * - * measurement accuracy, - * 0: resolution is 1kHz - * 1: resolution is 1Hz - */ -#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) - -/* - * REFERENCE (RW) - * - * reference clock selection, - * 0: 32k - * 1: 24M - */ -#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) - -/* - * SELECTION (RW) - * - * clock measurement selection - */ -#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) -#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CURRENT */ -/* - * FREQUENCY (RO) - * - * self updating measure result - */ -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ -/* - * FREQUENCY (RW) - * - * lower frequency - */ -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ -/* - * FREQUENCY (RW) - * - * upper frequency - */ -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array CPU: LP */ -/* - * WAKE_CNT (RW) - * - * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - */ -#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) -#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) -#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) -#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) - -/* - * HALT (RW) - * - * halt request for CPU0, - * 0: CPU0 will start to execute after reset or receive wakeup request - * 1: CPU0 will not start after reset, or wakeup after WFI - */ -#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) -#define SYSCTL_CPU_LP_HALT_SHIFT (16U) -#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) -#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) - -/* - * WAKE (RO) - * - * CPU0 is waking up - * 0: CPU0 wake up not asserted - * 1: CPU0 wake up asserted - */ -#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) -#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) -#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) - -/* - * EXEC (RO) - * - * CPU0 is executing - * 0: CPU0 is not executing - * 1: CPU0 is executing - */ -#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) -#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) -#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) - -/* - * WAKE_FLAG (RW) - * - * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit - * 0: CPU0 wakeup not happened - * 1: CPU0 wake up happened - */ -#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) -#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) - -/* - * SLEEP_FLAG (RW) - * - * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) -#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) - -/* - * RESET_FLAG (RW) - * - * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit - * 0: CPU0 reset not happened - * 1: CPU0 reset happened - */ -#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) -#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) -#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) -#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) - -/* - * MODE (RW) - * - * Low power mode, system behavior after WFI - * 00: CPU clock stop after WFI - * 01: System enter low power mode after WFI - * 10: Keep running after WFI - * 11: reserved - */ -#define SYSCTL_CPU_LP_MODE_MASK (0x3U) -#define SYSCTL_CPU_LP_MODE_SHIFT (0U) -#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) -#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) - -/* Bitfield definition for register of struct array CPU: LOCK */ -/* - * GPR (RW) - * - * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - */ -#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) -#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) -#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) -#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) - -/* - * LOCK (RW) - * - * Lock bit for CPU_LOCK - */ -#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) -#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) -#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) -#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register of struct array CPU: GPR0 */ -/* - * GPR (RW) - * - * register for software to handle resume, can save resume address or status - */ -#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) -#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) -#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) - -/* Bitfield definition for register of struct array CPU: STATUS0 */ -/* - * STATUS (RO) - * - * IRQ values - */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register of struct array CPU: ENABLE0 */ -/* - * ENABLE (RW) - * - * IRQ wakeup enable - */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) - - - -/* RESOURCE register group index macro definition */ -#define SYSCTL_RESOURCE_CPU0 (0UL) -#define SYSCTL_RESOURCE_CPX0 (1UL) -#define SYSCTL_RESOURCE_POW_VIS (21UL) -#define SYSCTL_RESOURCE_POW_CPU0 (22UL) -#define SYSCTL_RESOURCE_POW_GPU (23UL) -#define SYSCTL_RESOURCE_RST_SOC (25UL) -#define SYSCTL_RESOURCE_RST_CON (26UL) -#define SYSCTL_RESOURCE_RST_VIS (27UL) -#define SYSCTL_RESOURCE_RST_CPU0 (28UL) -#define SYSCTL_RESOURCE_RST_GPU (29UL) -#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (35UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (36UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (37UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (38UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (39UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (40UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL3 (41UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL3 (42UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL4 (43UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL4 (44UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (45UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (46UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (47UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL3_REF (48UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL4_REF (49UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_GPU0 (66UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIF (67UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIS (68UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIC (69UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIV (70UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXID (71UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (72UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (73UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (74UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (75UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN4 (76UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN5 (77UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN6 (78UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN7 (79UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN0 (80UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN1 (81UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN2 (82UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN3 (83UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN4 (84UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN5 (85UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN6 (86UL) -#define SYSCTL_RESOURCE_CLK_TOP_LIN7 (87UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (88UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (89UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (90UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (91UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (92UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (93UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (94UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (95UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT0 (96UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT1 (97UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT2 (98UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT3 (99UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT4 (100UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT5 (101UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT6 (102UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT7 (103UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (104UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (105UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (106UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (107UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR4 (108UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR5 (109UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR6 (110UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR7 (111UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (112UL) -#define SYSCTL_RESOURCE_CLK_TOP_XRAM (113UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (114UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (115UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (116UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (117UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD2 (118UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD3 (119UL) -#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (120UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (121UL) -#define SYSCTL_RESOURCE_CLK_TOP_SDC0 (122UL) -#define SYSCTL_RESOURCE_CLK_TOP_SDC1 (123UL) -#define SYSCTL_RESOURCE_CLK_TOP_NTM0 (124UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF0 (125UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF1 (126UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAM0 (127UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAM1 (128UL) -#define SYSCTL_RESOURCE_CLK_TOP_LCD0 (129UL) -#define SYSCTL_RESOURCE_CLK_TOP_LCD1 (130UL) -#define SYSCTL_RESOURCE_CLK_TOP_CSI0 (131UL) -#define SYSCTL_RESOURCE_CLK_TOP_CSI1 (132UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (133UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (134UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (135UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (136UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S2 (137UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S3 (138UL) -#define SYSCTL_RESOURCE_AXIS (256UL) -#define SYSCTL_RESOURCE_AXIC (257UL) -#define SYSCTL_RESOURCE_AXIV (258UL) -#define SYSCTL_RESOURCE_AXIG (259UL) -#define SYSCTL_RESOURCE_LMM0 (260UL) -#define SYSCTL_RESOURCE_MCT0 (261UL) -#define SYSCTL_RESOURCE_ROM0 (262UL) -#define SYSCTL_RESOURCE_DDR0 (263UL) -#define SYSCTL_RESOURCE_XRAM (264UL) -#define SYSCTL_RESOURCE_CAN0 (265UL) -#define SYSCTL_RESOURCE_CAN1 (266UL) -#define SYSCTL_RESOURCE_CAN2 (267UL) -#define SYSCTL_RESOURCE_CAN3 (268UL) -#define SYSCTL_RESOURCE_CAN4 (269UL) -#define SYSCTL_RESOURCE_CAN5 (270UL) -#define SYSCTL_RESOURCE_CAN6 (271UL) -#define SYSCTL_RESOURCE_CAN7 (272UL) -#define SYSCTL_RESOURCE_PTPC (273UL) -#define SYSCTL_RESOURCE_CRC0 (274UL) -#define SYSCTL_RESOURCE_OAMP (275UL) -#define SYSCTL_RESOURCE_LIN0 (276UL) -#define SYSCTL_RESOURCE_LIN1 (277UL) -#define SYSCTL_RESOURCE_LIN2 (278UL) -#define SYSCTL_RESOURCE_LIN3 (279UL) -#define SYSCTL_RESOURCE_LIN4 (280UL) -#define SYSCTL_RESOURCE_LIN5 (281UL) -#define SYSCTL_RESOURCE_LIN6 (282UL) -#define SYSCTL_RESOURCE_LIN7 (283UL) -#define SYSCTL_RESOURCE_I2C0 (284UL) -#define SYSCTL_RESOURCE_I2C1 (285UL) -#define SYSCTL_RESOURCE_I2C2 (286UL) -#define SYSCTL_RESOURCE_I2C3 (287UL) -#define SYSCTL_RESOURCE_SPI0 (288UL) -#define SYSCTL_RESOURCE_SPI1 (289UL) -#define SYSCTL_RESOURCE_SPI2 (290UL) -#define SYSCTL_RESOURCE_SPI3 (291UL) -#define SYSCTL_RESOURCE_URT0 (292UL) -#define SYSCTL_RESOURCE_URT1 (293UL) -#define SYSCTL_RESOURCE_URT2 (294UL) -#define SYSCTL_RESOURCE_URT3 (295UL) -#define SYSCTL_RESOURCE_URT4 (296UL) -#define SYSCTL_RESOURCE_URT5 (297UL) -#define SYSCTL_RESOURCE_URT6 (298UL) -#define SYSCTL_RESOURCE_URT7 (299UL) -#define SYSCTL_RESOURCE_WDG0 (300UL) -#define SYSCTL_RESOURCE_WDG1 (301UL) -#define SYSCTL_RESOURCE_MBX0 (302UL) -#define SYSCTL_RESOURCE_MBX1 (303UL) -#define SYSCTL_RESOURCE_TMR0 (304UL) -#define SYSCTL_RESOURCE_TMR1 (305UL) -#define SYSCTL_RESOURCE_TMR2 (306UL) -#define SYSCTL_RESOURCE_TMR3 (307UL) -#define SYSCTL_RESOURCE_TMR4 (308UL) -#define SYSCTL_RESOURCE_TMR5 (309UL) -#define SYSCTL_RESOURCE_TMR6 (310UL) -#define SYSCTL_RESOURCE_TMR7 (311UL) -#define SYSCTL_RESOURCE_I2S0 (312UL) -#define SYSCTL_RESOURCE_I2S1 (313UL) -#define SYSCTL_RESOURCE_I2S2 (314UL) -#define SYSCTL_RESOURCE_I2S3 (315UL) -#define SYSCTL_RESOURCE_PDM0 (316UL) -#define SYSCTL_RESOURCE_DAO0 (317UL) -#define SYSCTL_RESOURCE_SMIX (318UL) -#define SYSCTL_RESOURCE_RNG0 (319UL) -#define SYSCTL_RESOURCE_SDP0 (320UL) -#define SYSCTL_RESOURCE_KMAN (321UL) -#define SYSCTL_RESOURCE_GPIO (322UL) -#define SYSCTL_RESOURCE_ADC0 (323UL) -#define SYSCTL_RESOURCE_ADC1 (324UL) -#define SYSCTL_RESOURCE_SDM0 (325UL) -#define SYSCTL_RESOURCE_HDMA (326UL) -#define SYSCTL_RESOURCE_XDMA (327UL) -#define SYSCTL_RESOURCE_XPI0 (328UL) -#define SYSCTL_RESOURCE_FFA0 (329UL) -#define SYSCTL_RESOURCE_TSNS (330UL) -#define SYSCTL_RESOURCE_ETH0 (331UL) -#define SYSCTL_RESOURCE_USB0 (332UL) -#define SYSCTL_RESOURCE_SDC0 (333UL) -#define SYSCTL_RESOURCE_SDC1 (334UL) -#define SYSCTL_RESOURCE_NTM0 (335UL) -#define SYSCTL_RESOURCE_REF0 (336UL) -#define SYSCTL_RESOURCE_REF1 (337UL) -#define SYSCTL_RESOURCE_CAM0 (338UL) -#define SYSCTL_RESOURCE_CAM1 (339UL) -#define SYSCTL_RESOURCE_PDMA (340UL) -#define SYSCTL_RESOURCE_JPEG (341UL) -#define SYSCTL_RESOURCE_LCD0 (342UL) -#define SYSCTL_RESOURCE_LCD1 (343UL) -#define SYSCTL_RESOURCE_GWC0 (344UL) -#define SYSCTL_RESOURCE_GWC1 (345UL) -#define SYSCTL_RESOURCE_CSI0 (346UL) -#define SYSCTL_RESOURCE_CSI1 (347UL) -#define SYSCTL_RESOURCE_DSI0 (348UL) -#define SYSCTL_RESOURCE_DSI1 (349UL) -#define SYSCTL_RESOURCE_LVB0 (350UL) -#define SYSCTL_RESOURCE_LCB0 (351UL) -#define SYSCTL_RESOURCE_GPU0 (352UL) - -/* GROUP0 register group index macro definition */ -#define SYSCTL_GROUP0_LINK0 (0UL) -#define SYSCTL_GROUP0_LINK1 (1UL) -#define SYSCTL_GROUP0_LINK2 (2UL) -#define SYSCTL_GROUP0_LINK3 (3UL) - -/* AFFILIATE register group index macro definition */ -#define SYSCTL_AFFILIATE_CPU0 (0UL) - -/* RETENTION register group index macro definition */ -#define SYSCTL_RETENTION_CPU0 (0UL) - -/* POWER register group index macro definition */ -#define SYSCTL_POWER_VIS (0UL) -#define SYSCTL_POWER_CPU0 (1UL) -#define SYSCTL_POWER_GPU (2UL) - -/* RESET register group index macro definition */ -#define SYSCTL_RESET_SOC (0UL) -#define SYSCTL_RESET_CON (1UL) -#define SYSCTL_RESET_VIS (2UL) -#define SYSCTL_RESET_CPU0 (3UL) -#define SYSCTL_RESET_GPU (4UL) - -/* CLOCK register group index macro definition */ -#define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL) -#define SYSCTL_CLOCK_CLK_TOP_GPU0 (2UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIF (3UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIS (4UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIC (5UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIV (6UL) -#define SYSCTL_CLOCK_CLK_TOP_AXID (7UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN0 (8UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN1 (9UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN2 (10UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN3 (11UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN4 (12UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN5 (13UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN6 (14UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN7 (15UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN0 (16UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN1 (17UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN2 (18UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN3 (19UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN4 (20UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN5 (21UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN6 (22UL) -#define SYSCTL_CLOCK_CLK_TOP_LIN7 (23UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C0 (24UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C1 (25UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C2 (26UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C3 (27UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI0 (28UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI1 (29UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI2 (30UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI3 (31UL) -#define SYSCTL_CLOCK_CLK_TOP_URT0 (32UL) -#define SYSCTL_CLOCK_CLK_TOP_URT1 (33UL) -#define SYSCTL_CLOCK_CLK_TOP_URT2 (34UL) -#define SYSCTL_CLOCK_CLK_TOP_URT3 (35UL) -#define SYSCTL_CLOCK_CLK_TOP_URT4 (36UL) -#define SYSCTL_CLOCK_CLK_TOP_URT5 (37UL) -#define SYSCTL_CLOCK_CLK_TOP_URT6 (38UL) -#define SYSCTL_CLOCK_CLK_TOP_URT7 (39UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR0 (40UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR1 (41UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR2 (42UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR3 (43UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR4 (44UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR5 (45UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR6 (46UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR7 (47UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI0 (48UL) -#define SYSCTL_CLOCK_CLK_TOP_XRAM (49UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA0 (50UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA1 (51UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD0 (52UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD1 (53UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD2 (54UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD3 (55UL) -#define SYSCTL_CLOCK_CLK_TOP_ETH0 (56UL) -#define SYSCTL_CLOCK_CLK_TOP_PTP0 (57UL) -#define SYSCTL_CLOCK_CLK_TOP_SDC0 (58UL) -#define SYSCTL_CLOCK_CLK_TOP_SDC1 (59UL) -#define SYSCTL_CLOCK_CLK_TOP_NTM0 (60UL) -#define SYSCTL_CLOCK_CLK_TOP_REF0 (61UL) -#define SYSCTL_CLOCK_CLK_TOP_REF1 (62UL) -#define SYSCTL_CLOCK_CLK_TOP_CAM0 (63UL) -#define SYSCTL_CLOCK_CLK_TOP_CAM1 (64UL) -#define SYSCTL_CLOCK_CLK_TOP_LCD0 (65UL) -#define SYSCTL_CLOCK_CLK_TOP_LCD1 (66UL) -#define SYSCTL_CLOCK_CLK_TOP_CSI0 (67UL) -#define SYSCTL_CLOCK_CLK_TOP_CSI1 (68UL) - -/* ADCCLK register group index macro definition */ -#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) - -/* I2SCLK register group index macro definition */ -#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S2 (2UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S3 (3UL) - -/* MONITOR register group index macro definition */ -#define SYSCTL_MONITOR_SLICE0 (0UL) -#define SYSCTL_MONITOR_SLICE1 (1UL) -#define SYSCTL_MONITOR_SLICE2 (2UL) -#define SYSCTL_MONITOR_SLICE3 (3UL) - -/* GPR register group index macro definition */ -#define SYSCTL_CPU_GPR_GPR0 (0UL) -#define SYSCTL_CPU_GPR_GPR1 (1UL) -#define SYSCTL_CPU_GPR_GPR2 (2UL) -#define SYSCTL_CPU_GPR_GPR3 (3UL) -#define SYSCTL_CPU_GPR_GPR4 (4UL) -#define SYSCTL_CPU_GPR_GPR5 (5UL) -#define SYSCTL_CPU_GPR_GPR6 (6UL) -#define SYSCTL_CPU_GPR_GPR7 (7UL) -#define SYSCTL_CPU_GPR_GPR8 (8UL) -#define SYSCTL_CPU_GPR_GPR9 (9UL) -#define SYSCTL_CPU_GPR_GPR10 (10UL) -#define SYSCTL_CPU_GPR_GPR11 (11UL) -#define SYSCTL_CPU_GPR_GPR12 (12UL) -#define SYSCTL_CPU_GPR_GPR13 (13UL) - -/* WAKEUP_STATUS register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) - -/* WAKEUP_ENABLE register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) - -/* CPU register group index macro definition */ -#define SYSCTL_CPU_CPU0 (0UL) - - -#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_tamp_regs.h deleted file mode 100644 index 77a04f69e05..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_tamp_regs.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TAMP_H -#define HPM_TAMP_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Tamper n control */ - __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */ - __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - } TAMP[4]; - __R uint8_t RESERVED0[64]; /* 0x40 - 0x7F: Reserved */ - __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */ - __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */ -} TAMP_Type; - - -/* Bitfield definition for register of struct array TAMP: CONTROL */ -/* - * LOCK (RW) - * - * lock tamper setting - * 0: tamper setting can be changed - * 1: tamper setting will last to next battery domain power cycle - */ -#define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL) -#define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U) -#define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK) -#define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT) - -/* - * BYPASS (RW) - * - * bypass tamper violation filter - * 0: filter applied - * 1: filter not used - */ -#define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL) -#define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U) -#define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK) -#define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT) - -/* - * FILTER (RW) - * - * filter length - * 0: 1 cycle - * 1: 2 cycle - * 15: 65526 cycle - */ -#define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL) -#define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U) -#define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK) -#define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT) - -/* - * VALUE (RW) - * - * pin value for passive tamper - */ -#define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U) -#define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U) -#define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK) -#define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT) - -/* - * SPEED (RW) - * - * tamper speed selection, (2^SPEED) changes per second - * 0: 1 shift per second - * 1: 2 shifts per second - * . . . - * 15: 32768 shifts per second - */ -#define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U) -#define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U) -#define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK) -#define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT) - -/* - * RECOVER (RW) - * - * tamper will recover itself if tamper LFSR goes wrong - * 0: tamper will not recover - * 1: tamper will recover - */ -#define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U) -#define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U) -#define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK) -#define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT) - -/* - * ACTIVE (RW) - * - * select active or passive tamper - * 0: passive tamper - * 1: active tamper - */ -#define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U) -#define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U) -#define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK) -#define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable tamper - * 0: tamper disableed - * 1: tamper enabled - */ -#define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U) -#define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U) -#define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK) -#define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array TAMP: POLY */ -/* - * POLY (RW) - * - * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - */ -#define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_POLY_POLY_SHIFT (0U) -#define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK) -#define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array TAMP: LFSR */ -/* - * LFSR (WO) - * - * LFSR for active tamper, write only register, always read 0 - */ -#define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_LFSR_LFSR_SHIFT (0U) -#define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK) -#define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT) - -/* Bitfield definition for register: TAMP_FLAG */ -/* - * FLAG (RW) - * - * tamper flag, each bit represents one tamper pin, write 1 to clear the flag - * Note, clear can only be cleared when tamper disappeared - */ -#define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU) -#define TAMP_TAMP_FLAG_FLAG_SHIFT (0U) -#define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK) -#define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * LOCK (RW) - * - * lock bit for IRQ enable - * 0: enable bits can be changed - * 1: enable bits hold until next battery domain power cycle - */ -#define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL) -#define TAMP_IRQ_EN_LOCK_SHIFT (31U) -#define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK) -#define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable, each bit represents one tamper pin - * 0: interrupt disabled - * 1: interrupt enabled - */ -#define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU) -#define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U) -#define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK) -#define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT) - - - -/* TAMP register group index macro definition */ -#define TAMP_TAMP_TAMP0 (0UL) -#define TAMP_TAMP_TAMP1 (1UL) -#define TAMP_TAMP_TAMP2 (2UL) -#define TAMP_TAMP_TAMP3 (3UL) - - -#endif /* HPM_TAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_tsns_regs.h deleted file mode 100644 index fcaf224c309..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_tsns_regs.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSNS_H -#define HPM_TSNS_H - -typedef struct { - __R uint32_t T; /* 0x0: Temperature */ - __R uint32_t TMAX; /* 0x4: Maximum Temperature */ - __R uint32_t TMIN; /* 0x8: Minimum Temperature */ - __R uint32_t AGE; /* 0xC: Sample age */ - __RW uint32_t STATUS; /* 0x10: Status */ - __RW uint32_t CONFIG; /* 0x14: Configuration */ - __RW uint32_t VALIDITY; /* 0x18: Sample validity */ - __RW uint32_t FLAG; /* 0x1C: Temperature flag */ - __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ - __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ - __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ - __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ - __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __RW uint32_t ADVAN; /* 0x38: Advance configuration */ -} TSNS_Type; - - -/* Bitfield definition for register: T */ -/* - * T (RO) - * - * Signed number of temperature in 256 x celsius degree - */ -#define TSNS_T_T_MASK (0xFFFFFFFFUL) -#define TSNS_T_T_SHIFT (0U) -#define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) - -/* Bitfield definition for register: TMAX */ -/* - * T (RO) - * - * maximum temperature ever found - */ -#define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMAX_T_SHIFT (0U) -#define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) - -/* Bitfield definition for register: TMIN */ -/* - * T (RO) - * - * minimum temperature ever found - */ -#define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMIN_T_SHIFT (0U) -#define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) - -/* Bitfield definition for register: AGE */ -/* - * AGE (RO) - * - * age of T register in 24MHz clock cycles - */ -#define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) -#define TSNS_AGE_AGE_SHIFT (0U) -#define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * VALID (RO) - * - * indicate value in T is valid or not - * 0: not valid - * 1:valid - */ -#define TSNS_STATUS_VALID_MASK (0x80000000UL) -#define TSNS_STATUS_VALID_SHIFT (31U) -#define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) - -/* - * TRIGGER (W1C) - * - * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - */ -#define TSNS_STATUS_TRIGGER_MASK (0x1U) -#define TSNS_STATUS_TRIGGER_SHIFT (0U) -#define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) -#define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * IRQ_EN (RW) - * - * Enable interrupt - */ -#define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) -#define TSNS_CONFIG_IRQ_EN_SHIFT (31U) -#define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) -#define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) - -/* - * RST_EN (RW) - * - * Enable reset - */ -#define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) -#define TSNS_CONFIG_RST_EN_SHIFT (30U) -#define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) -#define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) - -/* - * COMPARE_MIN_EN (RW) - * - * Enable compare for minimum temperature - */ -#define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) -#define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) -#define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) -#define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) - -/* - * COMPARE_MAX_EN (RW) - * - * Enable compare for maximum temperature - */ -#define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) -#define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) -#define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) -#define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) - -/* - * SPEED (RW) - * - * cycles of a progressive step in 24M clock, valid from 24-255, default 96 - * 24: 24 cycle for a step - * 25: 25 cycle for a step - * 26: 26 cycle for a step - * ... - * 255: 255 cycle for a step - */ -#define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) -#define TSNS_CONFIG_SPEED_SHIFT (16U) -#define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) -#define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) - -/* - * AVERAGE (RW) - * - * Average time, default in 3 - * 0: measure and return - * 1: twice and average - * 2: 4 times and average - * . . . - * 7: 128 times and average - */ -#define TSNS_CONFIG_AVERAGE_MASK (0x700U) -#define TSNS_CONFIG_AVERAGE_SHIFT (8U) -#define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) -#define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) - -/* - * CONTINUOUS (RW) - * - * continuous mode that keep sampling temperature peridically - * 0: trigger mode - * 1: continuous mode - */ -#define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) -#define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) -#define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) -#define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) - -/* - * ASYNC (RW) - * - * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value - * 0: active mode - * 1: Async mode - */ -#define TSNS_CONFIG_ASYNC_MASK (0x2U) -#define TSNS_CONFIG_ASYNC_SHIFT (1U) -#define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) -#define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) - -/* - * ENABLE (RW) - * - * Enable temperature - * 0: disable, temperature sensor is shut down - * 1: enable. Temperature sensor enabled - */ -#define TSNS_CONFIG_ENABLE_MASK (0x1U) -#define TSNS_CONFIG_ENABLE_SHIFT (0U) -#define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) -#define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) - -/* Bitfield definition for register: VALIDITY */ -/* - * VALIDITY (RW) - * - * time for temperature values to expire in 24M clock cycles - */ -#define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) -#define TSNS_VALIDITY_VALIDITY_SHIFT (0U) -#define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) -#define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) - -/* Bitfield definition for register: FLAG */ -/* - * RECORD_MIN_CLR (RW) - * - * Clear minimum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) -#define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) -#define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) -#define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) - -/* - * RECORD_MAX_CLR (RW) - * - * Clear maximum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) -#define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) -#define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) -#define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) - -/* - * UNDER_TEMP (RW) - * - * Clear under temperature status, write 1 to clear - */ -#define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) -#define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) -#define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) -#define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) - -/* - * OVER_TEMP (RW) - * - * Clear over temperature status, write 1 to clear - */ -#define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) -#define TSNS_FLAG_OVER_TEMP_SHIFT (16U) -#define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) -#define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) - -/* - * IRQ (RW) - * - * IRQ flag, write 1 to clear - */ -#define TSNS_FLAG_IRQ_MASK (0x1U) -#define TSNS_FLAG_IRQ_SHIFT (0U) -#define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) -#define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_IRQ */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) -#define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_IRQ */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) -#define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_RST */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_RST_T_SHIFT (0U) -#define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) -#define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_RST */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_RST_T_SHIFT (0U) -#define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) -#define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: ASYNC */ -/* - * ASYNC_TYPE (RW) - * - * Compare hotter than or colder than in asynchoronous mode - * 0: hotter than - * 1: colder than - */ -#define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) -#define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) -#define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) -#define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) - -/* - * POLARITY (RW) - * - * Polarity of internal comparator - */ -#define TSNS_ASYNC_POLARITY_MASK (0x10000UL) -#define TSNS_ASYNC_POLARITY_SHIFT (16U) -#define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) -#define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) - -/* - * VALUE (RW) - * - * Value of async mode to compare - */ -#define TSNS_ASYNC_VALUE_MASK (0x7FFU) -#define TSNS_ASYNC_VALUE_SHIFT (0U) -#define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) -#define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) - -/* Bitfield definition for register: ADVAN */ -/* - * ASYNC_IRQ (RO) - * - * interrupt status of asynchronous mode - */ -#define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) -#define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) -#define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) - -/* - * ACTIVE_IRQ (RO) - * - * interrupt status of active mode - */ -#define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) -#define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) -#define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) - -/* - * SAMPLING (RO) - * - * temperature sampling is working - */ -#define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) -#define TSNS_ADVAN_SAMPLING_SHIFT (16U) -#define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) - -/* - * NEG_ONLY (RW) - * - * use negative compare polarity only - */ -#define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) -#define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) -#define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) -#define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) - -/* - * POS_ONLY (RW) - * - * use positive compare polarity only - */ -#define TSNS_ADVAN_POS_ONLY_MASK (0x1U) -#define TSNS_ADVAN_POS_ONLY_SHIFT (0U) -#define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) -#define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) - - - - -#endif /* HPM_TSNS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_uart_regs.h deleted file mode 100644 index 1c294c0485a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_uart_regs.h +++ /dev/null @@ -1,676 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_UART_H -#define HPM_UART_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t IDLE_CFG; /* 0x4: Idle Configuration Register */ - __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __RW uint32_t FCRR; /* 0x18: FIFO Control Register config */ - __R uint8_t RESERVED2[4]; /* 0x1C - 0x1F: Reserved */ - union { - __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ - __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ - __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ - __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ - __W uint32_t FCR; /* 0x28: FIFO Control Register */ - }; - __RW uint32_t LCR; /* 0x2C: Line Control Register */ - __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ - __R uint32_t LSR; /* 0x34: Line Status Register */ - __R uint32_t MSR; /* 0x38: Modem Status Register */ - __RW uint32_t GPR; /* 0x3C: GPR Register */ -} UART_Type; - - -/* Bitfield definition for register: IDLE_CFG */ -/* - * RXEN (RW) - * - * UART receive enable. - * 0 - hold RX input to high, avoide wrong data input when config pinmux - * 1 - bypass RX input from PIN - * software should set it after config pinmux - */ -#define UART_IDLE_CFG_RXEN_MASK (0x800U) -#define UART_IDLE_CFG_RXEN_SHIFT (11U) -#define UART_IDLE_CFG_RXEN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RXEN_SHIFT) & UART_IDLE_CFG_RXEN_MASK) -#define UART_IDLE_CFG_RXEN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RXEN_MASK) >> UART_IDLE_CFG_RXEN_SHIFT) - -/* - * RX_IDLE_COND (RW) - * - * IDLE Detection Condition - * 0 - Treat as idle if RX pin is logic one - * 1 - Treat as idle if UART state machine state is idle - */ -#define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x200U) -#define UART_IDLE_CFG_RX_IDLE_COND_SHIFT (9U) -#define UART_IDLE_CFG_RX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_COND_SHIFT) & UART_IDLE_CFG_RX_IDLE_COND_MASK) -#define UART_IDLE_CFG_RX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_COND_MASK) >> UART_IDLE_CFG_RX_IDLE_COND_SHIFT) - -/* - * RX_IDLE_EN (RW) - * - * UART Idle Detect Enable - * 0 - Disable - * 1 - Enable - * it should be enabled if enable address match feature - */ -#define UART_IDLE_CFG_RX_IDLE_EN_MASK (0x100U) -#define UART_IDLE_CFG_RX_IDLE_EN_SHIFT (8U) -#define UART_IDLE_CFG_RX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_EN_SHIFT) & UART_IDLE_CFG_RX_IDLE_EN_MASK) -#define UART_IDLE_CFG_RX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_EN_MASK) >> UART_IDLE_CFG_RX_IDLE_EN_SHIFT) - -/* - * RX_IDLE_THR (RW) - * - * Threshold for UART Receive Idle detection (in terms of bits) - */ -#define UART_IDLE_CFG_RX_IDLE_THR_MASK (0xFFU) -#define UART_IDLE_CFG_RX_IDLE_THR_SHIFT (0U) -#define UART_IDLE_CFG_RX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_THR_SHIFT) & UART_IDLE_CFG_RX_IDLE_THR_MASK) -#define UART_IDLE_CFG_RX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_THR_MASK) >> UART_IDLE_CFG_RX_IDLE_THR_SHIFT) - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * The depth of RXFIFO and TXFIFO - * 0: 16-byte FIFO - * 1: 32-byte FIFO - * 2: 64-byte FIFO - * 3: 128-byte FIFO - */ -#define UART_CFG_FIFOSIZE_MASK (0x3U) -#define UART_CFG_FIFOSIZE_SHIFT (0U) -#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: OSCR */ -/* - * OSC (RW) - * - * Over-sample control - * The value must be an even number; any odd value - * writes to this field will be converted to an even value. - * OSC=0: reserved - * OSC<=8: The over-sample ratio is 8 - * 8 < OSC< 32: The over sample ratio is OSC - */ -#define UART_OSCR_OSC_MASK (0x1FU) -#define UART_OSCR_OSC_SHIFT (0U) -#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) -#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) - -/* Bitfield definition for register: FCRR */ -/* - * RFIFOT (RW) - * - * Receiver FIFO trigger level - */ -#define UART_FCRR_RFIFOT_MASK (0xC0U) -#define UART_FCRR_RFIFOT_SHIFT (6U) -#define UART_FCRR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT_SHIFT) & UART_FCRR_RFIFOT_MASK) -#define UART_FCRR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT_MASK) >> UART_FCRR_RFIFOT_SHIFT) - -/* - * TFIFOT (RW) - * - * Transmitter FIFO trigger level - */ -#define UART_FCRR_TFIFOT_MASK (0x30U) -#define UART_FCRR_TFIFOT_SHIFT (4U) -#define UART_FCRR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT_SHIFT) & UART_FCRR_TFIFOT_MASK) -#define UART_FCRR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT_MASK) >> UART_FCRR_TFIFOT_SHIFT) - -/* - * DMAE (RW) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCRR_DMAE_MASK (0x8U) -#define UART_FCRR_DMAE_SHIFT (3U) -#define UART_FCRR_DMAE_SET(x) (((uint32_t)(x) << UART_FCRR_DMAE_SHIFT) & UART_FCRR_DMAE_MASK) -#define UART_FCRR_DMAE_GET(x) (((uint32_t)(x) & UART_FCRR_DMAE_MASK) >> UART_FCRR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCRR_TFIFORST_MASK (0x4U) -#define UART_FCRR_TFIFORST_SHIFT (2U) -#define UART_FCRR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFORST_SHIFT) & UART_FCRR_TFIFORST_MASK) -#define UART_FCRR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFORST_MASK) >> UART_FCRR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCRR_RFIFORST_MASK (0x2U) -#define UART_FCRR_RFIFORST_SHIFT (1U) -#define UART_FCRR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFORST_SHIFT) & UART_FCRR_RFIFORST_MASK) -#define UART_FCRR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFORST_MASK) >> UART_FCRR_RFIFORST_SHIFT) - -/* - * FIFOE (RW) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCRR_FIFOE_MASK (0x1U) -#define UART_FCRR_FIFOE_SHIFT (0U) -#define UART_FCRR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOE_SHIFT) & UART_FCRR_FIFOE_MASK) -#define UART_FCRR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOE_MASK) >> UART_FCRR_FIFOE_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RBR (RO) - * - * Receive data read port - */ -#define UART_RBR_RBR_MASK (0xFFU) -#define UART_RBR_RBR_SHIFT (0U) -#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) - -/* Bitfield definition for register: THR */ -/* - * THR (WO) - * - * Transmit data write port - */ -#define UART_THR_THR_MASK (0xFFU) -#define UART_THR_THR_SHIFT (0U) -#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) -#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) - -/* Bitfield definition for register: DLL */ -/* - * DLL (RW) - * - * Least significant byte of the Divisor Latch - */ -#define UART_DLL_DLL_MASK (0xFFU) -#define UART_DLL_DLL_SHIFT (0U) -#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) -#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) - -/* Bitfield definition for register: IER */ -/* - * ERXIDLE (RW) - * - * Enable Receive Idle interrupt - * 0 - Disable Idle interrupt - * 1 - Enable Idle interrupt - */ -#define UART_IER_ERXIDLE_MASK (0x80000000UL) -#define UART_IER_ERXIDLE_SHIFT (31U) -#define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) -#define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) - -/* - * EMSI (RW) - * - * Enable modem status interrupt - * The interrupt asserts when the status of one of the - * following occurs: - * The status of modem_rin, modem_dcdn, - * modem_dsrn or modem_ctsn (If the auto-cts mode is - * disabled) has been changed. - * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), - * modem_ctsn would be used to control the transmitter. - */ -#define UART_IER_EMSI_MASK (0x8U) -#define UART_IER_EMSI_SHIFT (3U) -#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) -#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) - -/* - * ELSI (RW) - * - * Enable receiver line status interrupt - */ -#define UART_IER_ELSI_MASK (0x4U) -#define UART_IER_ELSI_SHIFT (2U) -#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) -#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) - -/* - * ETHEI (RW) - * - * Enable transmitter holding register interrupt - */ -#define UART_IER_ETHEI_MASK (0x2U) -#define UART_IER_ETHEI_SHIFT (1U) -#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) -#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) - -/* - * ERBI (RW) - * - * Enable received data available interrupt and the - * character timeout interrupt - * 0: Disable - * 1: Enable - */ -#define UART_IER_ERBI_MASK (0x1U) -#define UART_IER_ERBI_SHIFT (0U) -#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) -#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) - -/* Bitfield definition for register: DLM */ -/* - * DLM (RW) - * - * Most significant byte of the Divisor Latch - */ -#define UART_DLM_DLM_MASK (0xFFU) -#define UART_DLM_DLM_SHIFT (0U) -#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) -#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) - -/* Bitfield definition for register: IIR */ -/* - * RXIDLE_FLAG (W1C) - * - * UART IDLE Flag - * 0 - UART is busy - * 1 - UART is idle - * NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - */ -#define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) -#define UART_IIR_RXIDLE_FLAG_SHIFT (31U) -#define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) -#define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) - -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR_FIFOED_MASK (0xC0U) -#define UART_IIR_FIFOED_SHIFT (6U) -#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR_INTRID_MASK (0xFU) -#define UART_IIR_INTRID_SHIFT (0U) -#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) - -/* Bitfield definition for register: FCR */ -/* - * RFIFOT (WO) - * - * Receiver FIFO trigger level - */ -#define UART_FCR_RFIFOT_MASK (0xC0U) -#define UART_FCR_RFIFOT_SHIFT (6U) -#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) -#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) - -/* - * TFIFOT (WO) - * - * Transmitter FIFO trigger level - */ -#define UART_FCR_TFIFOT_MASK (0x30U) -#define UART_FCR_TFIFOT_SHIFT (4U) -#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) -#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) - -/* - * DMAE (WO) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCR_DMAE_MASK (0x8U) -#define UART_FCR_DMAE_SHIFT (3U) -#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) -#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_TFIFORST_MASK (0x4U) -#define UART_FCR_TFIFORST_SHIFT (2U) -#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) -#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_RFIFORST_MASK (0x2U) -#define UART_FCR_RFIFORST_SHIFT (1U) -#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) -#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) - -/* - * FIFOE (WO) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCR_FIFOE_MASK (0x1U) -#define UART_FCR_FIFOE_SHIFT (0U) -#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) -#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) - -/* Bitfield definition for register: LCR */ -/* - * DLAB (RW) - * - * Divisor latch access bit - */ -#define UART_LCR_DLAB_MASK (0x80U) -#define UART_LCR_DLAB_SHIFT (7U) -#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) -#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) - -/* - * BC (RW) - * - * Break control - */ -#define UART_LCR_BC_MASK (0x40U) -#define UART_LCR_BC_SHIFT (6U) -#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) -#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) - -/* - * SPS (RW) - * - * Stick parity - * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). - * 0: Disable the sticky bit parity. - */ -#define UART_LCR_SPS_MASK (0x20U) -#define UART_LCR_SPS_SHIFT (5U) -#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) -#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) - -/* - * EPS (RW) - * - * Even parity select - * 1: Even parity (an even number of logic-1 is in the data - * and parity bits) - * 0: Old parity. - */ -#define UART_LCR_EPS_MASK (0x10U) -#define UART_LCR_EPS_SHIFT (4U) -#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) -#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) - -/* - * PEN (RW) - * - * Parity enable - * When this bit is set, a parity bit is generated in - * transmitted data before the first STOP bit and the parity - * bit would be checked for the received data. - */ -#define UART_LCR_PEN_MASK (0x8U) -#define UART_LCR_PEN_SHIFT (3U) -#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) -#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) - -/* - * STB (RW) - * - * Number of STOP bits - * 0: 1 bits - * 1: The number of STOP bit is based on the WLS setting - * When WLS = 0, STOP bit is 1.5 bits - * When WLS = 1, 2, 3, STOP bit is 2 bits - */ -#define UART_LCR_STB_MASK (0x4U) -#define UART_LCR_STB_SHIFT (2U) -#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) -#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) - -/* - * WLS (RW) - * - * Word length setting - * 0: 5 bits - * 1: 6 bits - * 2: 7 bits - * 3: 8 bits - */ -#define UART_LCR_WLS_MASK (0x3U) -#define UART_LCR_WLS_SHIFT (0U) -#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) -#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) - -/* Bitfield definition for register: MCR */ -/* - * AFE (RW) - * - * Auto flow control enable - * 0: Disable - * 1: The auto-CTS and auto-RTS setting is based on the - * RTS bit setting: - * When RTS = 0, auto-CTS only - * When RTS = 1, auto-CTS and auto-RTS - */ -#define UART_MCR_AFE_MASK (0x20U) -#define UART_MCR_AFE_SHIFT (5U) -#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) -#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) - -/* - * LOOP (RW) - * - * Enable loopback mode - * 0: Disable - * 1: Enable - */ -#define UART_MCR_LOOP_MASK (0x10U) -#define UART_MCR_LOOP_SHIFT (4U) -#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) -#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) - -/* - * RTS (RW) - * - * Request to send - * This bit controls the modem_rtsn output. - * 0: The modem_rtsn output signal will be driven HIGH - * 1: The modem_rtsn output signal will be driven LOW - */ -#define UART_MCR_RTS_MASK (0x2U) -#define UART_MCR_RTS_SHIFT (1U) -#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) -#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) - -/* Bitfield definition for register: LSR */ -/* - * ERRF (RO) - * - * Error in RXFIFO - * In the FIFO mode, this bit is set when there is at least - * one parity error, framing error, or line break - * associated with data in the RXFIFO. It is cleared when - * this register is read and there is no more error for the - * rest of data in the RXFIFO. - */ -#define UART_LSR_ERRF_MASK (0x80U) -#define UART_LSR_ERRF_SHIFT (7U) -#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) - -/* - * TEMT (RO) - * - * Transmitter empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) and the Transmitter Shift Register (TSR) are - * both empty. Otherwise, it is zero. - */ -#define UART_LSR_TEMT_MASK (0x40U) -#define UART_LSR_TEMT_SHIFT (6U) -#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) - -/* - * THRE (RO) - * - * Transmitter Holding Register empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) is empty. Otherwise, it is zero. - * If the THRE interrupt is enabled, an interrupt is - * triggered when THRE becomes 1. - */ -#define UART_LSR_THRE_MASK (0x20U) -#define UART_LSR_THRE_SHIFT (5U) -#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) - -/* - * LBREAK (RO) - * - * Line break - * This bit is set when the uart_sin input signal was held - * LOWfor longer than the time for a full-word - * transmission. A full-word transmission is the - * transmission of the START, data, parity, and STOP - * bits. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the line break for - * the received data at the top of the RXFIFO. - */ -#define UART_LSR_LBREAK_MASK (0x10U) -#define UART_LSR_LBREAK_SHIFT (4U) -#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) - -/* - * FE (RO) - * - * Framing error - * This bit is set when the received STOP bit is not - * HIGH. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the framing error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_FE_MASK (0x8U) -#define UART_LSR_FE_SHIFT (3U) -#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) - -/* - * PE (RO) - * - * Parity error - * This bit is set when the received parity does not match - * with the parity selected in the LCR[5:4]. It is cleared - * when this register is read. - * In the FIFO mode, this bit indicates the parity error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_PE_MASK (0x4U) -#define UART_LSR_PE_SHIFT (2U) -#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) - -/* - * OE (RO) - * - * Overrun error - * This bit indicates that data in the Receiver Buffer - * Register (RBR) is overrun. - */ -#define UART_LSR_OE_MASK (0x2U) -#define UART_LSR_OE_SHIFT (1U) -#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) - -/* - * DR (RO) - * - * Data ready. - * This bit is set when there are incoming received data - * in the Receiver Buffer Register (RBR). It is cleared - * when all of the received data are read. - */ -#define UART_LSR_DR_MASK (0x1U) -#define UART_LSR_DR_SHIFT (0U) -#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) - -/* Bitfield definition for register: MSR */ -/* - * CTS (RO) - * - * Clear to send - * 0: The modem_ctsn input signal is HIGH. - * 1: The modem_ctsn input signal is LOW. - */ -#define UART_MSR_CTS_MASK (0x10U) -#define UART_MSR_CTS_SHIFT (4U) -#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) - -/* - * DCTS (RC) - * - * Delta clear to send - * This bit is set when the state of the modem_ctsn input - * signal has been changed since the last time this - * register is read. - */ -#define UART_MSR_DCTS_MASK (0x1U) -#define UART_MSR_DCTS_SHIFT (0U) -#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) - -/* Bitfield definition for register: GPR */ -/* - * DATA (RW) - * - * A one-byte storage register - */ -#define UART_GPR_DATA_MASK (0xFFU) -#define UART_GPR_DATA_SHIFT (0U) -#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) -#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) - - - - -#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_usb_regs.h deleted file mode 100644 index ffaaefb4024..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_usb_regs.h +++ /dev/null @@ -1,2271 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_USB_H -#define HPM_USB_H - -typedef struct { - __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ - __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ - __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ - __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ - __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ - __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ - __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ - __RW uint32_t USBCMD; /* 0x140: USB Command Register */ - __RW uint32_t USBSTS; /* 0x144: USB Status Register */ - __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ - __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ - __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ - union { - __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ - __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ - }; - union { - __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ - __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ - }; - __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ - __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ - __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ - __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ - __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ - __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ - __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ - __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ - __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ - __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ - __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ - __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ - __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ - __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ - __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ - __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[16]; /* 0x1C0 - 0x1FC: Endpoint Control0 Register... Endpoint Control7 Register */ - __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */ - __RW uint32_t PHY_CTRL0; /* 0x210: */ - __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED8[8]; /* 0x218 - 0x21F: Reserved */ - __RW uint32_t TOP_STATUS; /* 0x220: */ - __RW uint32_t PHY_STATUS; /* 0x224: */ -} USB_Type; - - -/* Bitfield definition for register: GPTIMER0LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) -#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER0CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD - */ -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software; - * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the - * counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: GPTIMER1LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) -#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER1CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - */ -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and - * automatically reload the counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: SBUSCFG */ -/* - * AHBBRST (RW) - * - * AHBBRST - * AHB master interface Burst configuration - * These bits control AHB master transfer type sequence (or priority). - * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. - * 000 - Incremental burst of unspecified length only - * 001 - INCR4 burst, then single transfer - * 010 - INCR8 burst, INCR4 burst, then single transfer - * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer - * 100 - Reserved, don't use - * 101 - INCR4 burst, then incremental burst of unspecified length - * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length - * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) -#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) - -/* Bitfield definition for register: USBCMD */ -/* - * ITC (RW) - * - * ITC - * Interrupt Threshold Control -Read/Write. - * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. - * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are - * shown below. - * Value Maximum Interrupt Interval - * 00000000 - Immediate (no threshold) - * 00000001 - 1 micro-frame - * 00000010 - 2 micro-frames - * 00000100 - 4 micro-frames - * 00001000 - 8 micro-frames - * 00010000 - 16 micro-frames - * 00100000 - 32 micro-frames - * 01000000 - 64 micro-frames - */ -#define USB_USBCMD_ITC_MASK (0xFF0000UL) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) -#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) - -/* - * FS_2 (RW) - * - * FS_2 - * Frame List Size - (Read/Write or Read Only). [host mode only] - * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. - * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. - * NOTE: This field is made up from USBCMD bits 15, 3 and 2. - * Value Meaning - * 0b000 - 1024 elements (4096 bytes) Default value - * 0b001 - 512 elements (2048 bytes) - * 0b010 - 256 elements (1024 bytes) - * 0b011 - 128 elements (512 bytes) - * 0b100 - 64 elements (256 bytes) - * 0b101 - 32 elements (128 bytes) - * 0b110 - 16 elements (64 bytes) - * 0b111 - 8 elements (32 bytes) - */ -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) - -/* - * ATDTW (RW) - * - * ATDTW - * Add dTD TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's - * linked list. This bit is set and cleared by software. - * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD - * to a primed endpoint may go unrecognized. - */ -#define USB_USBCMD_ATDTW_MASK (0x4000U) -#define USB_USBCMD_ATDTW_SHIFT (14U) -#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) - -/* - * SUTW (RW) - * - * SUTW - * Setup TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. - * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then - * there is a hazard when new setup data arrives while the DCD is copying the setup data payload - * from the QH for a previous setup packet. This bit is set and cleared by software. - * This bit would also be cleared by hardware when a hazard detected. - */ -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) - -/* - * PRM (WO) - * - * Asynchronous Schedule start- Write only， host mode only。 - * this bit is used to notify hostcontroller to start async schedule immediately. - */ -#define USB_USBCMD_PRM_MASK (0x1000U) -#define USB_USBCMD_PRM_SHIFT (12U) -#define USB_USBCMD_PRM_SET(x) (((uint32_t)(x) << USB_USBCMD_PRM_SHIFT) & USB_USBCMD_PRM_MASK) -#define USB_USBCMD_PRM_GET(x) (((uint32_t)(x) & USB_USBCMD_PRM_MASK) >> USB_USBCMD_PRM_SHIFT) - -/* - * ASPE (RW) - * - * ASPE - * Asynchronous Schedule Park Mode Enable - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. - * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. - * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - * NOTE: ASPE bit reset value: '0b' for OTG controller . - */ -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) - -/* - * ASP (RW) - * - * ASP - * Asynchronous Schedule Park Mode Count - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. - * It contains a count of the number of successive transactions the host controller is allowed to - * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. - * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. - * This field is set to 3h in all controller core. - */ -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) - -/* - * IAA (RW) - * - * IAA - * Interrupt on Async Advance Doorbell - Read/Write. - * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. - * When the host controller has evicted all appropriate cached schedule states, - * it sets the Interrupt on Async Advance status bit in the USBSTS register. - * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. - * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. - * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. - * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - */ -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) - -/* - * ASE (RW) - * - * ASE - * Asynchronous Schedule Enable - Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Asynchronous Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Asynchronous Schedule. - * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - */ -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) - -/* - * PSE (RW) - * - * PSE - * Periodic Schedule Enable- Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Periodic Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Periodic Schedule - * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - */ -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) - -/* - * FS_1 (RW) - * - * FS_1 - * See description at bit 15 - */ -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) - -/* - * RST (RW) - * - * RST - * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. - * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. - * Host operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. - * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. - * Attempting to reset an actively running host controller will result in undefined behavior. - * Device operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. - * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - */ -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) - -/* - * RS (RW) - * - * RS - * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. - * Host operation mode: - * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. - * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. - * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. - * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). - * Device operation mode: - * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. - * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. - * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) - -/* Bitfield definition for register: USBSTS */ -/* - * TI1 (RWC) - * - * TI1 - * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. - * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this - * bit will clear it. - */ -#define USB_USBSTS_TI1_MASK (0x2000000UL) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) -#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) - -/* - * TI0 (RWC) - * - * TI0 - * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. - * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this - * bit clears it. - */ -#define USB_USBSTS_TI0_MASK (0x1000000UL) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) - -/* - * UPI (RWC) - * - * USB Host Periodic Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. - * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero. - */ -#define USB_USBSTS_UPI_MASK (0x80000UL) -#define USB_USBSTS_UPI_SHIFT (19U) -#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) -#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) - -/* - * UAI (RWC) - * - * USB Host Asynchronous Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. - * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero - */ -#define USB_USBSTS_UAI_MASK (0x40000UL) -#define USB_USBSTS_UAI_SHIFT (18U) -#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) -#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) - -/* - * NAKI (RO) - * - * NAKI - * NAK Interrupt Bit--RO. - * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and - * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware - * when all Enabled TX/RX Endpoint NAK bits are cleared. - */ -#define USB_USBSTS_NAKI_MASK (0x10000UL) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) - -/* - * AS (RO) - * - * AS - * Asynchronous Schedule Status - Read Only. - * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. - * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) - -/* - * PS (RO) - * - * PS - * Periodic Schedule Status - Read Only. - * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. - * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) - -/* - * RCL (RO) - * - * RCL - * Reclamation - Read Only. - * This is a read-only status bit used to detect an empty asynchronous schedule. - * Only used in the host operation mode. - */ -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) - -/* - * HCH (RO) - * - * HCH - * HCHaIted - Read Only. - * This bit is a zero whenever the Run/Stop bit is a one. - * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - * either by software or by the Controller hardware (for example, an internal error). - * Only used in the host operation mode. - * Default value is '0b' for OTG core . - * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE - * register. - * NOTE: HCH bit reset value: '0b' for OTG controller core . - */ -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) - -/* - * SLI (RWC) - * - * SLI - * DCSuspend - R/WC. - * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. - * Only used in device operation mode. - */ -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) - -/* - * SRI (RWC) - * - * SRI - * SOF Received - R/WC. - * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. - * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. - * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. - * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. - * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. - * Software writes a 1 to this bit to clear it. - */ -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) - -/* - * URI (RWC) - * - * URI - * USB Reset Received - R/WC. - * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. - * Software can write a 1 to this bit to clear the USB Reset Received status bit. - * Only used in device operation mode. - */ -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) - -/* - * AAI (RWC) - * - * AAI - * Interrupt on Async Advance - R/WC. - * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule - * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. - * Only used in host operation mode. - */ -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) - -/* - * SEI (RWC) - * - * System Error – RWC. Default = 0b. - * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. - * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - */ -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) - -/* - * FRI (RWC) - * - * FRI - * Frame List Rollover - R/WC. - * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to - * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the - * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the - * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host - * Controller sets this bit to a one every time FHINDEX [12] toggles. - * Only used in host operation mode. - */ -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) - -/* - * PCI (RWC) - * - * PCI - * Port Change Detect - R/WC. - * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, - * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. - * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. - * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, - * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - */ -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) - -/* - * UEI (RWC) - * - * UEI - * USB Error Interrupt (USBERRINT) - R/WC. - * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. - * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - */ -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) - -/* - * UI (RWC) - * - * UI - * USB Interrupt (USBINT) - R/WC. - * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB - * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. - * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when - * the actual number of bytes received was less than the expected number of bytes. - */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) - -/* Bitfield definition for register: USBINTR */ -/* - * TIE1 (RW) - * - * TIE1 - * General Purpose Timer #1 Interrupt Enable - * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE1_MASK (0x2000000UL) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) -#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) - -/* - * TIE0 (RW) - * - * TIE0 - * General Purpose Timer #0 Interrupt Enable - * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE0_MASK (0x1000000UL) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) - -/* - * UPIE (RW) - * - * UPIE - * USB Host Periodic Interrupt Enable - * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UPIE_MASK (0x80000UL) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) - -/* - * UAIE (RW) - * - * UAIE - * USB Host Asynchronous Interrupt Enable - * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UAIE_MASK (0x40000UL) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) - -/* - * NAKE (RO) - * - * NAKE - * NAK Interrupt Enable - * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_NAKE_MASK (0x10000UL) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) - -/* - * SLE (RW) - * - * SLE - * Sleep Interrupt Enable - * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) - -/* - * SRE (RW) - * - * SRE - * SOF Received Interrupt Enable - * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) - -/* - * URE (RW) - * - * URE - * USB Reset Interrupt Enable - * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) - -/* - * AAE (RW) - * - * AAE - * Async Advance Interrupt Enable - * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) - -/* - * SEE (RW) - * - * SEE - * System Error Interrupt Enable - * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) - -/* - * FRE (RW) - * - * FRE - * Frame List Rollover Interrupt Enable - * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) - -/* - * PCE (RW) - * - * PCE - * Port Change Detect Interrupt Enable - * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) - -/* - * UEE (RWC) - * - * UEE - * USB Error Interrupt Enable - * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) - -/* - * UE (RW) - * - * UE - * USB Interrupt Enable - * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) - -/* Bitfield definition for register: FRINDEX */ -/* - * FRINDEX (RW) - * - * FRINDEX - * Frame Index. - * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. - * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. - * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. - * USBCMD [Frame List Size] Number Elements N - * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. - * In either mode bits 2:0 indicate the current microframe. - * The bit field values description below is represented as (Frame List Size) Number Elements N. - * 00000000000000 - (1024) 12 - * 00000000000001 - (512) 11 - * 00000000000010 - (256) 10 - * 00000000000011 - (128) 9 - * 00000000000100 - (64) 8 - * 00000000000101 - (32) 7 - * 00000000000110 - (16) 6 - * 00000000000111 - (8) 5 - */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) -#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) - -/* Bitfield definition for register: DEVICEADDR */ -/* - * USBADR (RW) - * - * USBADR - * Device Address. - * These bits correspond to the USB device address - */ -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) -#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) - -/* - * USBADRA (RW) - * - * USBADRA - * Device Address Advance. Default=0. - * When this bit is '0', any writes to USBADR are instantaneous. - * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. - * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. - * Hardware will automatically clear this bit on the following conditions: - * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). - * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). - * 3) Device Reset occurs (USBADR is reset to 0). - * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. - * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. - * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), - * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) - -/* Bitfield definition for register: PERIODICLISTBASE */ -/* - * BASEADR (RW) - * - * BASEADR - * Base Address (Low). - * These bits correspond to memory address signals [31:12], respectively. - * Only used by the host controller. - */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) -#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) - -/* Bitfield definition for register: ASYNCLISTADDR */ -/* - * ASYBASE (RW) - * - * ASYBASE - * Link Pointer Low (LPL). - * These bits correspond to memory address signals [31:5], respectively. This field may only reference a - * Queue Head (QH). - * Only used by the host controller. - */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) -#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) - -/* Bitfield definition for register: ENDPTLISTADDR */ -/* - * EPBASE (RW) - * - * EPBASE - * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. - * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) -#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) - -/* Bitfield definition for register: BURSTSIZE */ -/* - * TXPBURST (RW) - * - * TXPBURST - * Programmable TX Burst Size. - * Default value is determined by TXBURST bits in n_HWTXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from system - * memory to the USB bus. - */ -#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) - -/* - * RXPBURST (RW) - * - * RXPBURST - * Programmable RX Burst Size. - * Default value is determined by TXBURST bits in n_HWRXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from the - * USB bus to system memory. - */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) - -/* Bitfield definition for register: TXFILLTUNING */ -/* - * TXFIFOTHRES (RW) - * - * TXFIFOTHRES - * FIFO Burst Threshold. (Read/Write) - * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. - * The minimum value is 2 and this value should be a low as possible to maximize USB performance. - * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth - * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. - * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - */ -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* - * TXSCHHEALTH (RWC) - * - * TXSCHHEALTH - * Scheduler Health Counter. (Read/Write To Clear) - * Table continues on the next page - * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES - * before running out of time to send the packet before the next Start-Of-Frame. - * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. - * Writing to this register will clear the counter and this counter will max. at 31. - */ -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) - -/* - * TXSCHOH (RW) - * - * TXSCHOH - * Scheduler Overhead. (Read/Write) [Default = 0] - * This register adds an additional fixed offset to the schedule time estimator described above as Tff. - * As an approximation, the value chosen for this register should limit the number of back-off events captured - * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. - * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. - * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. - * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. - * Default value is '08h' for OTG controller core . - */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) - -/* Bitfield definition for register: ENDPTNAK */ -/* - * EPTN (RWC) - * - * EPTN - * TX Endpoint NAK - R/WC. - * Each TX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received IN token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) -#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) - -/* - * EPRN (RWC) - * - * EPRN - * RX Endpoint NAK - R/WC. - * Each RX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) - -/* Bitfield definition for register: ENDPTNAKEN */ -/* - * EPTNE (RW) - * - * EPTNE - * TX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the - * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) - -/* - * EPRNE (RW) - * - * EPRNE - * RX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the - * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) - -/* Bitfield definition for register: PORTSC1 */ -/* - * STS (RW) - * - * STS - * Serial Transceiver Select - * 1 Serial Interface Engine is selected - * 0 Parallel Interface signals is selected - * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. - * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - */ -#define USB_PORTSC1_STS_MASK (0x20000000UL) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) - -/* - * PTW (RW) - * - * PTW - * Parallel Transceiver Width - * This bit has no effect if serial interface engine is used. - * 0 - Select the 8-bit UTMI interface [60MHz] - * 1 - Select the 16-bit UTMI interface [30MHz] - */ -#define USB_PORTSC1_PTW_MASK (0x10000000UL) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) - -/* - * PSPD (RO) - * - * PSPD - * Port Speed - Read Only. - * This register field indicates the speed at which the port is operating. - * 00 - Full Speed - * 01 - Low Speed - * 10 - High Speed - * 11 - Undefined - */ -#define USB_PORTSC1_PSPD_MASK (0xC000000UL) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) - -/* - * PFSC (RW) - * - * PFSC - * Port Force Full Speed Connect - Read/Write. Default = 0b. - * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp - * sequence that allows the port to identify itself as High Speed. - * 0 - Normal operation - * 1 - Forced to full speed - */ -#define USB_PORTSC1_PFSC_MASK (0x1000000UL) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) - -/* - * PHCD (RW) - * - * PHCD - * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. - * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY - * clock. - * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. - * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD - * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend - * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the - * device controller driver must clear this bit. - * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put - * into suspend mode or when no downstream device is connected. Low power suspend is completely - * under the control of software. - * 0 - Enable PHY clock - * 1 - Disable PHY clock - */ -#define USB_PORTSC1_PHCD_MASK (0x800000UL) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) - -/* - * WKOC (RW) - * - * WKOC - * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. - * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero. - */ -#define USB_PORTSC1_WKOC_MASK (0x400000UL) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) - -/* - * WKDC (RW) - * - * WKDC - * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables - * the port to be sensitive to device disconnects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKDC_MASK (0x200000UL) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) - -/* - * WKCN (RW) - * - * WKCN - * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. - * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKCN_MASK (0x100000UL) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) - -/* - * PTC (RW) - * - * PTC - * Port Test Control - Read/Write. Default = 0000b. - * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. - * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. - * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. - * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. - * NOTE: Low speed operations are not supported as a peripheral device. - * Any other value than zero indicates that the port is operating in test mode. - * Value Specific Test - * 0000 - TEST_MODE_DISABLE - * 0001 - J_STATE - * 0010 - K_STATE - * 0011 - SE0 (host) / NAK (device) - * 0100 - Packet - * 0101 - FORCE_ENABLE_HS - * 0110 - FORCE_ENABLE_FS - * 0111 - FORCE_ENABLE_LS - * 1000-1111 - Reserved - */ -#define USB_PORTSC1_PTC_MASK (0xF0000UL) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) - -/* - * PP (RW) - * - * PP - * Port Power (PP)-Read/Write or Read Only. - * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: - * PPC - * PP Operation - * 0 - * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. - * 1 - * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). - * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. - * When an over-current condition is detected on a powered port and PPC is a one, - * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). - * This feature is implemented in all controller cores (PPC = 1). - */ -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) - -/* - * LS (RO) - * - * LS - * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal - * lines. - * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because - * the port controller state machine and the port routing manage the connection of LS and FS. - * In device mode, the use of linestate by the device controller driver is not necessary. - * The encoding of the bits are: - * Bits [11:10] Meaning - * 00 - SE0 - * 01 - K-state - * 10 - J-state - * 11 - Undefined - */ -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) - -/* - * HSP (RO) - * - * HSP - * High-Speed Port - Read Only. Default = 0b. - * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the - * host/device connected to the port is not in a high-speed mode. - * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - */ -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) - -/* - * PR (RW) - * - * PR - * Port Reset - Read/Write or Read Only. Default = 0b. - * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. - * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. - * This bit will automatically change to zero after the reset sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. - * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - */ -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) - -/* - * SUSP (RW) - * - * SUSP - * Suspend - Read/Write or Read Only. Default = 0b. - * 1=Port in suspend state. 0=Port not in suspend state. - * In Host Mode: Read/Write. - * Port Enabled Bit and Suspend bit of this register define the port states as follows: - * Bits [Port Enabled, Suspend] Port State - * 0x Disable - * 10 Enable - * 11 Suspend - * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. - * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. - * In the suspend state, the port is sensitive to resume detection. - * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. - * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. - * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: Read Only. - * In device mode this bit is a read only status bit. - */ -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) - -/* - * FPR (RW) - * - * FPR - * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. - * In Host Mode: - * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. - * This bit will automatically change to zero after the resume sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. - * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. - * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. - * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * This bit is not-EHCI compatible. - * In Device mode: - * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. - * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * The bit will be cleared when the device returns to normal operation. - * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - */ -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) - -/* - * OCC (RW) - * - * OCC - * Over-current Change-R/WC. Default=0. - * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - */ -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) - -/* - * OCA (RO) - * - * OCA - * Over-current Active-Read Only. Default 0. - * This bit will automatically transition from one to zero when the over current condition is removed. - * 0 - This port does not have an over-current condition. - * 1 - This port currently has an over-current condition - */ -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) - -/* - * PEC (RWC) - * - * PEC - * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. - * In Host Mode: - * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or - * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). - * Software clears this by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero. - * In Device mode: - * The device port is always enabled, so this bit is always '0b'. - */ -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) - -/* - * PE (RWC) - * - * PE - * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. - * In Host Mode: - * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. - * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. - * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. - * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * The device port is always enabled, so this bit is always '1b'. - */ -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) - -/* - * CSC (RWC) - * - * CSC - * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. - * In Host Mode: - * Indicates a change has occurred in the port's Current Connect Status. - * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. - * For example, the insertion status changes twice before system software has cleared the changed condition, - * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * This bit is undefined in device controller mode. - */ -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) - -/* - * CCS (RWC) - * - * CCS - * Current Connect Status-Read Only. - * In Host Mode: - * 1=Device is present on port. 0=No device is present. Default = 0. - * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * 1=Attached. 0=Not Attached. Default=0. - * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. - * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. - * It does not state the device being disconnected or Suspended. - */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) - -/* Bitfield definition for register: OTGSC */ -/* - * ASVIE (RW) - * - * ASVIE - * A Session Valid Interrupt Enable - Read/Write. - */ -#define USB_OTGSC_ASVIE_MASK (0x4000000UL) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) - -/* - * AVVIE (RW) - * - * AVVIE - * A VBus Valid Interrupt Enable - Read/Write. - * Setting this bit enables the A VBus valid interrupt. - */ -#define USB_OTGSC_AVVIE_MASK (0x2000000UL) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) - -/* - * IDIE (RW) - * - * IDIE - * USB ID Interrupt Enable - Read/Write. - * Setting this bit enables the USB ID interrupt. - */ -#define USB_OTGSC_IDIE_MASK (0x1000000UL) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) - -/* - * ASVIS (RWC) - * - * ASVIS - * A Session Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the A session valid threshold. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_ASVIS_MASK (0x40000UL) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) - -/* - * AVVIS (RWC) - * - * AVVIS - * A VBus Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_AVVIS_MASK (0x20000UL) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) - -/* - * IDIS (RWC) - * - * IDIS - * USB ID Interrupt Status - Read/Write. - * This bit is set when a change on the ID input has been detected. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_IDIS_MASK (0x10000UL) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) - -/* - * ASV (RO) - * - * ASV - * A Session Valid - Read Only. - * Indicates VBus is above the A session valid threshold. - */ -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) - -/* - * AVV (RO) - * - * AVV - * A VBus Valid - Read Only. - * Indicates VBus is above the A VBus valid threshold. - */ -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) - -/* - * ID (RO) - * - * ID - * USB ID - Read Only. - * 0 = A device, 1 = B device - */ -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) - -/* - * IDPU (RW) - * - * IDPU - * ID Pullup - Read/Write - * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input - * will not be sampled. - */ -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) - -/* - * VC (RW) - * - * VC - * VBUS Charge - Read/Write. - * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - */ -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) - -/* - * VD (RW) - * - * VD - * VBUS_Discharge - Read/Write. - * Setting this bit causes VBus to discharge through a resistor. - */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) - -/* Bitfield definition for register: USBMODE */ -/* - * SDIS (RW) - * - * SDIS - * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) - * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. - * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. - * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. - * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems - * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. - * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for - * the scheduler when using this feature. - * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - */ -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) -#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) - -/* - * SLOM (RW) - * - * SLOM - * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . - * 0 - Setup Lockouts On (default); - * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - */ -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) - -/* - * ES (RW) - * - * ES - * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the - * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected - * by the value of this bit because they are based upon the 32-bit word. - * Bit Meaning - * 0 - Little Endian [Default] - * 1 - Big Endian - */ -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) - -/* - * CM (RW) - * - * CM - * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only - * implementations. For those designs that contain both host & device capability, the controller defaults to - * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ - * device controllers, this register can only be written once after reset. If it is necessary to switch modes, - * software must reset the controller by writing to the RESET bit in the USBCMD register before - * reprogramming this register. - * For OTG controller core, reset value is '00b'. - * 00 - Idle [Default for combination host/device] - * 01 - Reserved - * 10 - Device Controller [Default for device only controller] - * 11 - Host Controller [Default for host only controller] - */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) - -/* Bitfield definition for register: ENDPTSETUPSTAT */ -/* - * ENDPTSETUPSTAT (RWC) - * - * ENDPTSETUPSTAT - * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. - * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. - * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. - * This register is only used in device mode. - */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* Bitfield definition for register: ENDPTPRIME */ -/* - * PETB (RWS) - * - * PETB - * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a - * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. - * Software should write a one to the corresponding bit when posting a new transfer descriptor to an - * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor - * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated - * endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) -#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) - -/* - * PERB (RWS) - * - * PERB - * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. - * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. - * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. - * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) - -/* Bitfield definition for register: ENDPTFLUSH */ -/* - * FETB (RWS) - * - * FETB - * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) -#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) - -/* - * FERB (RWS) - * - * FERB - * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) - -/* Bitfield definition for register: ENDPTSTAT */ -/* - * ETBR (RO) - * - * ETBR - * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. - * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. - * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. - * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. - * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. - * ETBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) - -/* - * ERBR (RO) - * - * ERBR - * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective - * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a - * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the - * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB - * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the - * USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations - * when a dTD is retired, and the dQH is updated. - * ERBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) - -/* Bitfield definition for register: ENDPTCOMPLETE */ -/* - * ETCE (RWC) - * - * ETCE - * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. - * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. - * ETCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) - -/* - * ERCE (RWC) - * - * ERCE - * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred - * and software should read the corresponding endpoint queue to determine the transfer status. If the - * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the - * USBINT . Writing one clears the corresponding bit in this register. - * ERCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) - -/* Bitfield definition for register array: ENDPTCTRL */ -/* - * TXE (RW) - * - * TXE - * TX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) -#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) - -/* - * TXR (WS) - * - * TXR - * TX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the Host and device. - */ -#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) - -/* - * TXT (RW) - * - * TXT - * TX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) - -/* - * TXS (RW) - * - * TXS - * TX Endpoint Stall - Read/Write - * 0 End Point OK - * 1 End Point Stalled - * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured - * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. - * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. - * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: - * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - */ -#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) - -/* - * RXE (RW) - * - * RXE - * RX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) - -/* - * RXR (WS) - * - * RXR - * RX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the host and device. - */ -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) - -/* - * RXT (RW) - * - * RXT - * RX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) - -/* - * RXS (RW) - * - * RXS - * RX Endpoint Stall - Read/Write - * 0 End Point OK. [Default] - * 1 End Point Stalled - * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control - * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit - * is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This - * control will continue to STALL until this bit is either cleared by software or automatically cleared as above - * for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the - * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it - * is unlikely the DCD software will observe this delay. However, should the DCD observe that the - * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit - * until it is set or until a new setup has been received by checking the associated endptsetupstat - * Bit. - */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) - -/* Bitfield definition for register: OTG_CTRL0 */ -/* - * OTG_WKDPDMCHG_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) - -/* - * AUTORESUME_EN (RW) - * - */ -#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) -#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) -#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) -#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) - -/* - * OTG_VBUS_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) - -/* - * OTG_ID_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) - -/* - * OTG_VBUS_SOURCE_SEL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) - -/* - * OTG_UTMI_SUSPENDM_SW (RW) - * - * default 0 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) - -/* - * OTG_UTMI_RESET_SW (RW) - * - * default 1 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) - -/* - * OTG_WAKEUP_INT_ENABLE (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) - -/* - * OTG_POWER_MASK (RW) - * - */ -#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) -#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) - -/* - * OTG_OVER_CUR_POL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) - -/* - * OTG_OVER_CUR_DIS (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) - -/* - * SER_MODE_SUSPEND_EN (RW) - * - * for naneng usbphy, only switch to serial mode when suspend - */ -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL0 */ -/* - * GPIO_ID_SEL_N (RW) - * - */ -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) - -/* - * ID_DIG_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) - -/* - * SESS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) - -/* - * VBUS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) - -/* - * ID_DIG_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) - -/* - * SESS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) - -/* - * VBUS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL1 */ -/* - * UTMI_CFG_RST_N (RW) - * - */ -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) - -/* - * UTMI_OTG_SUSPENDM (RW) - * - * OTG suspend, not utmi_suspendm - */ -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) - -/* Bitfield definition for register: TOP_STATUS */ -/* - * WAKEUP_INT_STATUS (RW) - * - */ -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * UTMI_CLK_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) -#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) - -/* - * LINE_STATE (RW) - * - */ -#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) -#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) -#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) -#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) - -/* - * HOST_DISCONNECT (RW) - * - */ -#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) -#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) - -/* - * ID_DIG (RW) - * - */ -#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) -#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) -#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) -#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) - -/* - * UTMI_SESS_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) -#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) - -/* - * VBUS_VALID (RW) - * - */ -#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) -#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) -#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) -#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) - - - -/* ENDPTCTRL register group index macro definition */ -#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) -#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) -#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) -#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) -#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) -#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) -#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) -#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) -#define USB_ENDPTCTRL_ENDPTCTRL8 (8UL) -#define USB_ENDPTCTRL_ENDPTCTRL9 (9UL) -#define USB_ENDPTCTRL_ENDPTCTRL10 (10UL) -#define USB_ENDPTCTRL_ENDPTCTRL11 (11UL) -#define USB_ENDPTCTRL_ENDPTCTRL12 (12UL) -#define USB_ENDPTCTRL_ENDPTCTRL13 (13UL) -#define USB_ENDPTCTRL_ENDPTCTRL14 (14UL) -#define USB_ENDPTCTRL_ENDPTCTRL15 (15UL) - - -#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_vad_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_vad_regs.h deleted file mode 100644 index 8aad52aa969..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6800/ip/hpm_vad_regs.h +++ /dev/null @@ -1,441 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_VAD_H -#define HPM_VAD_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t FILTCTRL; /* 0x4: Filter Control Register */ - __RW uint32_t DEC_CTRL0; /* 0x8: Decision Control Register 0 */ - __RW uint32_t DEC_CTRL1; /* 0xC: Decision Control Register 1 */ - __RW uint32_t DEC_CTRL2; /* 0x10: Decision Control Register 2 */ - __R uint8_t RESERVED0[4]; /* 0x14 - 0x17: Reserved */ - __RW uint32_t ST; /* 0x18: Status */ - __RW uint32_t OFIFO; /* 0x1C: Out FIFO */ - __RW uint32_t RUN; /* 0x20: Run Command Register */ - __RW uint32_t OFIFO_CTRL; /* 0x24: Out FIFO Control Register */ - __RW uint32_t CIC_CFG; /* 0x28: CIC Configuration Register */ - __R uint8_t RESERVED1[116]; /* 0x2C - 0x9F: Reserved */ - __R uint32_t COEF[1]; /* 0xA0: Short Time Energy Register */ -} VAD_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * CAPT_DLY (RW) - * - * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - */ -#define VAD_CTRL_CAPT_DLY_MASK (0xF000000UL) -#define VAD_CTRL_CAPT_DLY_SHIFT (24U) -#define VAD_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << VAD_CTRL_CAPT_DLY_SHIFT) & VAD_CTRL_CAPT_DLY_MASK) -#define VAD_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & VAD_CTRL_CAPT_DLY_MASK) >> VAD_CTRL_CAPT_DLY_SHIFT) - -/* - * PDM_CLK_HFDIV (RW) - * - * The clock divider will work at least 4. - * 0: div-by-2, - * 1: div-by-4 - * . . . - * n: div-by-2*(n+1) - */ -#define VAD_CTRL_PDM_CLK_HFDIV_MASK (0xF00000UL) -#define VAD_CTRL_PDM_CLK_HFDIV_SHIFT (20U) -#define VAD_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_HFDIV_SHIFT) & VAD_CTRL_PDM_CLK_HFDIV_MASK) -#define VAD_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_HFDIV_MASK) >> VAD_CTRL_PDM_CLK_HFDIV_SHIFT) - -/* - * VAD_IE (RW) - * - * VAD event interrupt enable - */ -#define VAD_CTRL_VAD_IE_MASK (0x40000UL) -#define VAD_CTRL_VAD_IE_SHIFT (18U) -#define VAD_CTRL_VAD_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_VAD_IE_SHIFT) & VAD_CTRL_VAD_IE_MASK) -#define VAD_CTRL_VAD_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_VAD_IE_MASK) >> VAD_CTRL_VAD_IE_SHIFT) - -/* - * OFIFO_AV_IE (RW) - * - * OFIFO data available interrupt enable - */ -#define VAD_CTRL_OFIFO_AV_IE_MASK (0x20000UL) -#define VAD_CTRL_OFIFO_AV_IE_SHIFT (17U) -#define VAD_CTRL_OFIFO_AV_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_AV_IE_SHIFT) & VAD_CTRL_OFIFO_AV_IE_MASK) -#define VAD_CTRL_OFIFO_AV_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_AV_IE_MASK) >> VAD_CTRL_OFIFO_AV_IE_SHIFT) - -/* - * MEMBUF_EMPTY_IE (RW) - * - * Buf empty interrupt enable - */ -#define VAD_CTRL_MEMBUF_EMPTY_IE_MASK (0x10000UL) -#define VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT (16U) -#define VAD_CTRL_MEMBUF_EMPTY_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) -#define VAD_CTRL_MEMBUF_EMPTY_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_EMPTY_IE_MASK) >> VAD_CTRL_MEMBUF_EMPTY_IE_SHIFT) - -/* - * OFIFO_OVFL_ERR_IE (RW) - * - * OFIFO overflow error interrupt enable - */ -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x8000U) -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (15U) -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) -#define VAD_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> VAD_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) - -/* - * IIR_OVLD_ERR_IE (RW) - * - * IIR overload error interrupt enable - */ -#define VAD_CTRL_IIR_OVLD_ERR_IE_MASK (0x4000U) -#define VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT (14U) -#define VAD_CTRL_IIR_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) -#define VAD_CTRL_IIR_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVLD_ERR_IE_MASK) >> VAD_CTRL_IIR_OVLD_ERR_IE_SHIFT) - -/* - * IIR_OVFL_ERR_IE (RW) - * - * IIR overflow error interrupt enable - */ -#define VAD_CTRL_IIR_OVFL_ERR_IE_MASK (0x2000U) -#define VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT (13U) -#define VAD_CTRL_IIR_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) -#define VAD_CTRL_IIR_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_IIR_OVFL_ERR_IE_MASK) >> VAD_CTRL_IIR_OVFL_ERR_IE_SHIFT) - -/* - * CIC_OVLD_ERR_IE (RW) - * - * CIC overload Interrupt Enable - */ -#define VAD_CTRL_CIC_OVLD_ERR_IE_MASK (0x1000U) -#define VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT (12U) -#define VAD_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) -#define VAD_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_OVLD_ERR_IE_MASK) >> VAD_CTRL_CIC_OVLD_ERR_IE_SHIFT) - -/* - * CIC_SAT_ERR_IE (RW) - * - * CIC saturation Interrupt Enable - */ -#define VAD_CTRL_CIC_SAT_ERR_IE_MASK (0x800U) -#define VAD_CTRL_CIC_SAT_ERR_IE_SHIFT (11U) -#define VAD_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) -#define VAD_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & VAD_CTRL_CIC_SAT_ERR_IE_MASK) >> VAD_CTRL_CIC_SAT_ERR_IE_SHIFT) - -/* - * MEMBUF_DISABLE (RW) - * - * asserted to disable membuf - */ -#define VAD_CTRL_MEMBUF_DISABLE_MASK (0x200U) -#define VAD_CTRL_MEMBUF_DISABLE_SHIFT (9U) -#define VAD_CTRL_MEMBUF_DISABLE_SET(x) (((uint32_t)(x) << VAD_CTRL_MEMBUF_DISABLE_SHIFT) & VAD_CTRL_MEMBUF_DISABLE_MASK) -#define VAD_CTRL_MEMBUF_DISABLE_GET(x) (((uint32_t)(x) & VAD_CTRL_MEMBUF_DISABLE_MASK) >> VAD_CTRL_MEMBUF_DISABLE_SHIFT) - -/* - * FIFO_THRSH (RW) - * - * OFIFO threshold to generate ofifo_av (when fillings >= threshold) (fifo size: max 16 items, 16*32bits) - */ -#define VAD_CTRL_FIFO_THRSH_MASK (0x1E0U) -#define VAD_CTRL_FIFO_THRSH_SHIFT (5U) -#define VAD_CTRL_FIFO_THRSH_SET(x) (((uint32_t)(x) << VAD_CTRL_FIFO_THRSH_SHIFT) & VAD_CTRL_FIFO_THRSH_MASK) -#define VAD_CTRL_FIFO_THRSH_GET(x) (((uint32_t)(x) & VAD_CTRL_FIFO_THRSH_MASK) >> VAD_CTRL_FIFO_THRSH_SHIFT) - -/* - * PDM_CLK_DIV_BYPASS (RW) - * - * asserted to bypass the pdm clock divider - */ -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x10U) -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (4U) -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) -#define VAD_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> VAD_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) - -/* - * PDM_CLK_OE (RW) - * - * pdm_clk_output_en - */ -#define VAD_CTRL_PDM_CLK_OE_MASK (0x8U) -#define VAD_CTRL_PDM_CLK_OE_SHIFT (3U) -#define VAD_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << VAD_CTRL_PDM_CLK_OE_SHIFT) & VAD_CTRL_PDM_CLK_OE_MASK) -#define VAD_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & VAD_CTRL_PDM_CLK_OE_MASK) >> VAD_CTRL_PDM_CLK_OE_SHIFT) - -/* - * CH_POL (RW) - * - * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - */ -#define VAD_CTRL_CH_POL_MASK (0x6U) -#define VAD_CTRL_CH_POL_SHIFT (1U) -#define VAD_CTRL_CH_POL_SET(x) (((uint32_t)(x) << VAD_CTRL_CH_POL_SHIFT) & VAD_CTRL_CH_POL_MASK) -#define VAD_CTRL_CH_POL_GET(x) (((uint32_t)(x) & VAD_CTRL_CH_POL_MASK) >> VAD_CTRL_CH_POL_SHIFT) - -/* - * CHNUM (RW) - * - * the number of channels to be stored in buffer. Asserted to enable 2 channels. - */ -#define VAD_CTRL_CHNUM_MASK (0x1U) -#define VAD_CTRL_CHNUM_SHIFT (0U) -#define VAD_CTRL_CHNUM_SET(x) (((uint32_t)(x) << VAD_CTRL_CHNUM_SHIFT) & VAD_CTRL_CHNUM_MASK) -#define VAD_CTRL_CHNUM_GET(x) (((uint32_t)(x) & VAD_CTRL_CHNUM_MASK) >> VAD_CTRL_CHNUM_SHIFT) - -/* Bitfield definition for register: FILTCTRL */ -/* - * DECRATIO (RW) - * - * the decimation ratio of iir after CIC -1 - * 2: means dec-by-3 - */ -#define VAD_FILTCTRL_DECRATIO_MASK (0x700U) -#define VAD_FILTCTRL_DECRATIO_SHIFT (8U) -#define VAD_FILTCTRL_DECRATIO_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_DECRATIO_SHIFT) & VAD_FILTCTRL_DECRATIO_MASK) -#define VAD_FILTCTRL_DECRATIO_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_DECRATIO_MASK) >> VAD_FILTCTRL_DECRATIO_SHIFT) - -/* - * IIR_SLOT_EN (RW) - * - * IIR slot enable - */ -#define VAD_FILTCTRL_IIR_SLOT_EN_MASK (0xFFU) -#define VAD_FILTCTRL_IIR_SLOT_EN_SHIFT (0U) -#define VAD_FILTCTRL_IIR_SLOT_EN_SET(x) (((uint32_t)(x) << VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) -#define VAD_FILTCTRL_IIR_SLOT_EN_GET(x) (((uint32_t)(x) & VAD_FILTCTRL_IIR_SLOT_EN_MASK) >> VAD_FILTCTRL_IIR_SLOT_EN_SHIFT) - -/* Bitfield definition for register: DEC_CTRL0 */ -/* - * NOISE_TOL (RW) - * - * the value of amplitude for noise determination when calculationg ZCR - */ -#define VAD_DEC_CTRL0_NOISE_TOL_MASK (0xFFFF0000UL) -#define VAD_DEC_CTRL0_NOISE_TOL_SHIFT (16U) -#define VAD_DEC_CTRL0_NOISE_TOL_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_NOISE_TOL_SHIFT) & VAD_DEC_CTRL0_NOISE_TOL_MASK) -#define VAD_DEC_CTRL0_NOISE_TOL_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_NOISE_TOL_MASK) >> VAD_DEC_CTRL0_NOISE_TOL_SHIFT) - -/* - * BLK_CFG (RW) - * - * asserted to have 3 sub-blocks, otherwise to have 2 sub-blocks - */ -#define VAD_DEC_CTRL0_BLK_CFG_MASK (0x200U) -#define VAD_DEC_CTRL0_BLK_CFG_SHIFT (9U) -#define VAD_DEC_CTRL0_BLK_CFG_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_BLK_CFG_SHIFT) & VAD_DEC_CTRL0_BLK_CFG_MASK) -#define VAD_DEC_CTRL0_BLK_CFG_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_BLK_CFG_MASK) >> VAD_DEC_CTRL0_BLK_CFG_SHIFT) - -/* - * SUBBLK_LEN (RW) - * - * length of sub-block - */ -#define VAD_DEC_CTRL0_SUBBLK_LEN_MASK (0x1FFU) -#define VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT (0U) -#define VAD_DEC_CTRL0_SUBBLK_LEN_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) -#define VAD_DEC_CTRL0_SUBBLK_LEN_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL0_SUBBLK_LEN_MASK) >> VAD_DEC_CTRL0_SUBBLK_LEN_SHIFT) - -/* Bitfield definition for register: DEC_CTRL1 */ -/* - * ZCR_HIGH (RW) - * - * ZCR high limit - */ -#define VAD_DEC_CTRL1_ZCR_HIGH_MASK (0x3FF800UL) -#define VAD_DEC_CTRL1_ZCR_HIGH_SHIFT (11U) -#define VAD_DEC_CTRL1_ZCR_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) -#define VAD_DEC_CTRL1_ZCR_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_HIGH_MASK) >> VAD_DEC_CTRL1_ZCR_HIGH_SHIFT) - -/* - * ZCR_LOW (RW) - * - * ZCR low limit - */ -#define VAD_DEC_CTRL1_ZCR_LOW_MASK (0x7FFU) -#define VAD_DEC_CTRL1_ZCR_LOW_SHIFT (0U) -#define VAD_DEC_CTRL1_ZCR_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL1_ZCR_LOW_SHIFT) & VAD_DEC_CTRL1_ZCR_LOW_MASK) -#define VAD_DEC_CTRL1_ZCR_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL1_ZCR_LOW_MASK) >> VAD_DEC_CTRL1_ZCR_LOW_SHIFT) - -/* Bitfield definition for register: DEC_CTRL2 */ -/* - * AMP_HIGH (RW) - * - * amplitude high limit - */ -#define VAD_DEC_CTRL2_AMP_HIGH_MASK (0xFFFF0000UL) -#define VAD_DEC_CTRL2_AMP_HIGH_SHIFT (16U) -#define VAD_DEC_CTRL2_AMP_HIGH_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_HIGH_SHIFT) & VAD_DEC_CTRL2_AMP_HIGH_MASK) -#define VAD_DEC_CTRL2_AMP_HIGH_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_HIGH_MASK) >> VAD_DEC_CTRL2_AMP_HIGH_SHIFT) - -/* - * AMP_LOW (RW) - * - * amplitude low limit - */ -#define VAD_DEC_CTRL2_AMP_LOW_MASK (0xFFFFU) -#define VAD_DEC_CTRL2_AMP_LOW_SHIFT (0U) -#define VAD_DEC_CTRL2_AMP_LOW_SET(x) (((uint32_t)(x) << VAD_DEC_CTRL2_AMP_LOW_SHIFT) & VAD_DEC_CTRL2_AMP_LOW_MASK) -#define VAD_DEC_CTRL2_AMP_LOW_GET(x) (((uint32_t)(x) & VAD_DEC_CTRL2_AMP_LOW_MASK) >> VAD_DEC_CTRL2_AMP_LOW_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * VAD (W1C) - * - * VAD event found - */ -#define VAD_ST_VAD_MASK (0x80U) -#define VAD_ST_VAD_SHIFT (7U) -#define VAD_ST_VAD_SET(x) (((uint32_t)(x) << VAD_ST_VAD_SHIFT) & VAD_ST_VAD_MASK) -#define VAD_ST_VAD_GET(x) (((uint32_t)(x) & VAD_ST_VAD_MASK) >> VAD_ST_VAD_SHIFT) - -/* - * OFIFO_AV (RO) - * - * OFIFO data available - */ -#define VAD_ST_OFIFO_AV_MASK (0x40U) -#define VAD_ST_OFIFO_AV_SHIFT (6U) -#define VAD_ST_OFIFO_AV_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_AV_MASK) >> VAD_ST_OFIFO_AV_SHIFT) - -/* - * MEMBUF_EMPTY (W1C) - * - * Buf empty - */ -#define VAD_ST_MEMBUF_EMPTY_MASK (0x20U) -#define VAD_ST_MEMBUF_EMPTY_SHIFT (5U) -#define VAD_ST_MEMBUF_EMPTY_SET(x) (((uint32_t)(x) << VAD_ST_MEMBUF_EMPTY_SHIFT) & VAD_ST_MEMBUF_EMPTY_MASK) -#define VAD_ST_MEMBUF_EMPTY_GET(x) (((uint32_t)(x) & VAD_ST_MEMBUF_EMPTY_MASK) >> VAD_ST_MEMBUF_EMPTY_SHIFT) - -/* - * OFIFO_OVFL (W1C) - * - * OFIFO overflow - */ -#define VAD_ST_OFIFO_OVFL_MASK (0x10U) -#define VAD_ST_OFIFO_OVFL_SHIFT (4U) -#define VAD_ST_OFIFO_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_OFIFO_OVFL_SHIFT) & VAD_ST_OFIFO_OVFL_MASK) -#define VAD_ST_OFIFO_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_OFIFO_OVFL_MASK) >> VAD_ST_OFIFO_OVFL_SHIFT) - -/* - * IIR_OVLD (W1C) - * - * IIR overloading - */ -#define VAD_ST_IIR_OVLD_MASK (0x8U) -#define VAD_ST_IIR_OVLD_SHIFT (3U) -#define VAD_ST_IIR_OVLD_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVLD_SHIFT) & VAD_ST_IIR_OVLD_MASK) -#define VAD_ST_IIR_OVLD_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVLD_MASK) >> VAD_ST_IIR_OVLD_SHIFT) - -/* - * IIR_OVFL (W1C) - * - * IIR oberflow - */ -#define VAD_ST_IIR_OVFL_MASK (0x4U) -#define VAD_ST_IIR_OVFL_SHIFT (2U) -#define VAD_ST_IIR_OVFL_SET(x) (((uint32_t)(x) << VAD_ST_IIR_OVFL_SHIFT) & VAD_ST_IIR_OVFL_MASK) -#define VAD_ST_IIR_OVFL_GET(x) (((uint32_t)(x) & VAD_ST_IIR_OVFL_MASK) >> VAD_ST_IIR_OVFL_SHIFT) - -/* - * CIC_OVLD_ERR (W1C) - * - * CIC overload - */ -#define VAD_ST_CIC_OVLD_ERR_MASK (0x2U) -#define VAD_ST_CIC_OVLD_ERR_SHIFT (1U) -#define VAD_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_OVLD_ERR_SHIFT) & VAD_ST_CIC_OVLD_ERR_MASK) -#define VAD_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_OVLD_ERR_MASK) >> VAD_ST_CIC_OVLD_ERR_SHIFT) - -/* - * CIC_SAT_ERR (W1C) - * - * CIC saturation - */ -#define VAD_ST_CIC_SAT_ERR_MASK (0x1U) -#define VAD_ST_CIC_SAT_ERR_SHIFT (0U) -#define VAD_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << VAD_ST_CIC_SAT_ERR_SHIFT) & VAD_ST_CIC_SAT_ERR_MASK) -#define VAD_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & VAD_ST_CIC_SAT_ERR_MASK) >> VAD_ST_CIC_SAT_ERR_SHIFT) - -/* Bitfield definition for register: OFIFO */ -/* - * D (RW) - * - * The PCM data. - * When there is only one channel, the samples are from Ch0, and the 2 samples in the 32-bits are: bit [31:16]: the samples earlier in time ([T-1]). Bit [15:0]: the samples later in time ([T]). - * When there is two channels, the samples in the 32-bits are: bit [31:16]: the samples belong to Ch 1 (when ch_pol[1:0]==2, the data is captured at the positive part of the pdm clk). bit [15:0]: the samples belong to Ch 0 (when ch_pol[1:0]==2, the data is captured at the negtive part of the pdm clk). - */ -#define VAD_OFIFO_D_MASK (0xFFFFFFFFUL) -#define VAD_OFIFO_D_SHIFT (0U) -#define VAD_OFIFO_D_SET(x) (((uint32_t)(x) << VAD_OFIFO_D_SHIFT) & VAD_OFIFO_D_MASK) -#define VAD_OFIFO_D_GET(x) (((uint32_t)(x) & VAD_OFIFO_D_MASK) >> VAD_OFIFO_D_SHIFT) - -/* Bitfield definition for register: RUN */ -/* - * SFTRST (RW) - * - * software reset. Self-clear - */ -#define VAD_RUN_SFTRST_MASK (0x2U) -#define VAD_RUN_SFTRST_SHIFT (1U) -#define VAD_RUN_SFTRST_SET(x) (((uint32_t)(x) << VAD_RUN_SFTRST_SHIFT) & VAD_RUN_SFTRST_MASK) -#define VAD_RUN_SFTRST_GET(x) (((uint32_t)(x) & VAD_RUN_SFTRST_MASK) >> VAD_RUN_SFTRST_SHIFT) - -/* - * VAD_EN (RW) - * - * module enable - */ -#define VAD_RUN_VAD_EN_MASK (0x1U) -#define VAD_RUN_VAD_EN_SHIFT (0U) -#define VAD_RUN_VAD_EN_SET(x) (((uint32_t)(x) << VAD_RUN_VAD_EN_SHIFT) & VAD_RUN_VAD_EN_MASK) -#define VAD_RUN_VAD_EN_GET(x) (((uint32_t)(x) & VAD_RUN_VAD_EN_MASK) >> VAD_RUN_VAD_EN_SHIFT) - -/* Bitfield definition for register: OFIFO_CTRL */ -/* - * EN (RW) - * - * Asserted to enable OFIFO - */ -#define VAD_OFIFO_CTRL_EN_MASK (0x1U) -#define VAD_OFIFO_CTRL_EN_SHIFT (0U) -#define VAD_OFIFO_CTRL_EN_SET(x) (((uint32_t)(x) << VAD_OFIFO_CTRL_EN_SHIFT) & VAD_OFIFO_CTRL_EN_MASK) -#define VAD_OFIFO_CTRL_EN_GET(x) (((uint32_t)(x) & VAD_OFIFO_CTRL_EN_MASK) >> VAD_OFIFO_CTRL_EN_SHIFT) - -/* Bitfield definition for register: CIC_CFG */ -/* - * POST_SCALE (RW) - * - * the shift value after CIC results. - */ -#define VAD_CIC_CFG_POST_SCALE_MASK (0xFC00U) -#define VAD_CIC_CFG_POST_SCALE_SHIFT (10U) -#define VAD_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << VAD_CIC_CFG_POST_SCALE_SHIFT) & VAD_CIC_CFG_POST_SCALE_MASK) -#define VAD_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & VAD_CIC_CFG_POST_SCALE_MASK) >> VAD_CIC_CFG_POST_SCALE_SHIFT) - -/* Bitfield definition for register array: COEF */ -/* - * VAL (RO) - * - * The current detected short time energy - */ -#define VAD_COEF_VAL_MASK (0xFFFFFFFFUL) -#define VAD_COEF_VAL_SHIFT (0U) -#define VAD_COEF_VAL_GET(x) (((uint32_t)(x) & VAD_COEF_VAL_MASK) >> VAD_COEF_VAL_SHIFT) - - - -/* COEF register group index macro definition */ -#define VAD_COEF_STE_ACT (0UL) - - -#endif /* HPM_VAD_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/HPM6E80_svd.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/HPM6E80_svd.xml deleted file mode 100644 index de3116fb022..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/HPM6E80_svd.xml +++ /dev/null @@ -1,56191 +0,0 @@ - - - HPMICRO - HPM6E80 - HPM6E00 - 1.0 - HPM6E00 device - - /* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - - - other - r0p0 - little - false - true - true - 7 - false - - - - 8 - 32 - 32 - read-write - 0x0 - 0xFFFFFFFF - - - - - FGPIO - FGPIO - GPIO - 0x300000 - - 0x0 - 0x900 - registers - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - DI[%s] - no description available - 0x0 - - VALUE - GPIO input value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INPUT - GPIO input bus value, each bit represents a bus bit -0: low level presents on chip pin -1: high level presents on chip pin - 0 - 32 - read-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - DO[%s] - no description available - 0x100 - - VALUE - GPIO output value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - SET - GPIO output set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - CLEAR - GPIO output clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - TOGGLE - GPIO output toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT - GPIO output register value, each bit represents a bus bit -0: chip pin output low level when direction is output -1: chip pin output high level when direction is output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - OE[%s] - no description available - 0x200 - - VALUE - GPIO direction value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - SET - GPIO direction set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - CLEAR - GPIO direction clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - TOGGLE - GPIO direction toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - DIRECTION - GPIO direction, each bit represents a bus bit -0: input -1: output - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - IF[%s] - no description available - 0x300 - - VALUE - GPIO interrupt flag value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_FLAG - GPIO interrupt flag, write 1 to clear this flag -0: no irq -1: irq pending - 0 - 32 - write-only - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - IE[%s] - no description available - 0x400 - - VALUE - GPIO interrupt enable value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - SET - GPIO interrupt enable set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt enable clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt enable toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_EN - GPIO interrupt enable, each bit represents a bus bit -0: irq is disabled -1: irq is enable - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - PL[%s] - no description available - 0x500 - - VALUE - GPIO interrupt polarity value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt polarity set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt polarity clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt polarity toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_POL - GPIO interrupt polarity, each bit represents a bus bit -0: irq is high level or rising edge -1: irq is low level or falling edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - TP[%s] - no description available - 0x600 - - VALUE - GPIO interrupt type value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - SET - GPIO interrupt type set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt type clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt type toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_TYPE - GPIO interrupt type, each bit represents a bus bit -0: irq is triggered by level -1: irq is triggered by edge - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - AS[%s] - no description available - 0x700 - - VALUE - GPIO interrupt asynchronous value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - SET - GPIO interrupt asynchronous set - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - CLEAR - GPIO interrupt asynchronous clear - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - TOGGLE - GPIO interrupt asynchronous toggle - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ASYNC - GPIO interrupt asynchronous, each bit represents a bus bit -0: irq is triggered base on system clock -1: irq is triggered combinational -Note: combinational interrupt is sensitive to environment noise - 0 - 32 - read-write - - - - - - 16 - 0x10 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,gpiov,gpiow,gpiox,gpioy,gpioz - PD[%s] - no description available - 0x800 - - VALUE - GPIO dual edge interrupt enable value - 0x0 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable -0: single edge interrupt -1: dual edge interrupt enable - 0 - 1 - read-write - - - - - SET - GPIO dual edge interrupt enable set - 0x4 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable set -0: keep original edge interrupt type -1: dual edge interrupt enable - 0 - 1 - read-write - - - - - CLEAR - GPIO dual edge interrupt enable clear - 0x8 - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable clear -0: keep original edge interrupt type -1: single edge interrupt enable - 0 - 1 - read-write - - - - - TOGGLE - GPIO dual edge interrupt enable toggle - 0xc - 32 - 0x00000000 - 0x00000001 - - - IRQ_DUAL - GPIO dual edge interrupt enable toggle -0: keep original edge interrupt type -1: change original edge interrupt type to another one. - 0 - 1 - read-write - - - - - - - - GPIO0 - GPIO0 - GPIO - 0xf00d0000 - - - GPIO1 - GPIO1 - GPIO - 0xf00d4000 - - - PGPIO - PGPIO - GPIO - 0xf411c000 - - - BGPIO - BGPIO - GPIO - 0xf4214000 - - - PLIC - PLIC - PLIC - 0xe4000000 - - 0x0 - 0x202000 - registers - - - - feature - Feature enable register - 0x0 - 32 - 0x00000000 - 0x00000003 - - - VECTORED - Vector mode enable -0: Disabled -1: Enabled - 1 - 1 - read-write - - - PREEMPT - Preemptive priority interrupt enable -0: Disabled -1: Enabled - 0 - 1 - read-write - - - - - 127 - 0x4 - PRIORITY1,PRIORITY2,PRIORITY3,PRIORITY4,PRIORITY5,PRIORITY6,PRIORITY7,PRIORITY8,PRIORITY9,PRIORITY10,PRIORITY11,PRIORITY12,PRIORITY13,PRIORITY14,PRIORITY15,PRIORITY16,PRIORITY17,PRIORITY18,PRIORITY19,PRIORITY20,PRIORITY21,PRIORITY22,PRIORITY23,PRIORITY24,PRIORITY25,PRIORITY26,PRIORITY27,PRIORITY28,PRIORITY29,PRIORITY30,PRIORITY31,PRIORITY32,PRIORITY33,PRIORITY34,PRIORITY35,PRIORITY36,PRIORITY37,PRIORITY38,PRIORITY39,PRIORITY40,PRIORITY41,PRIORITY42,PRIORITY43,PRIORITY44,PRIORITY45,PRIORITY46,PRIORITY47,PRIORITY48,PRIORITY49,PRIORITY50,PRIORITY51,PRIORITY52,PRIORITY53,PRIORITY54,PRIORITY55,PRIORITY56,PRIORITY57,PRIORITY58,PRIORITY59,PRIORITY60,PRIORITY61,PRIORITY62,PRIORITY63,PRIORITY64,PRIORITY65,PRIORITY66,PRIORITY67,PRIORITY68,PRIORITY69,PRIORITY70,PRIORITY71,PRIORITY72,PRIORITY73,PRIORITY74,PRIORITY75,PRIORITY76,PRIORITY77,PRIORITY78,PRIORITY79,PRIORITY80,PRIORITY81,PRIORITY82,PRIORITY83,PRIORITY84,PRIORITY85,PRIORITY86,PRIORITY87,PRIORITY88,PRIORITY89,PRIORITY90,PRIORITY91,PRIORITY92,PRIORITY93,PRIORITY94,PRIORITY95,PRIORITY96,PRIORITY97,PRIORITY98,PRIORITY99,PRIORITY100,PRIORITY101,PRIORITY102,PRIORITY103,PRIORITY104,PRIORITY105,PRIORITY106,PRIORITY107,PRIORITY108,PRIORITY109,PRIORITY110,PRIORITY111,PRIORITY112,PRIORITY113,PRIORITY114,PRIORITY115,PRIORITY116,PRIORITY117,PRIORITY118,PRIORITY119,PRIORITY120,PRIORITY121,PRIORITY122,PRIORITY123,PRIORITY124,PRIORITY125,PRIORITY126,PRIORITY127 - PRIORITY[%s] - no description available - 0x4 - 32 - 0x00000001 - 0xFFFFFFFF - - - PRIORITY - Interrupt source priority. The valid range of this field is 0-7. -0: Never interrupt -1-7: Interrupt source priority. The larger the value, the higher the priority. - 0 - 32 - read-write - - - - - 4 - 0x4 - PENDING0,PENDING1,PENDING2,PENDING3 - PENDING[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - 4 - 0x4 - TRIGGER0,TRIGGER1,TRIGGER2,TRIGGER3 - TRIGGER[%s] - no description available - 0x1080 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. -0: Level-triggered interrupt -1: Edge-triggered interrupt - 0 - 32 - read-only - - - - - NUMBER - Number of supported interrupt sources and targets - 0x1100 - 32 - 0xFFFFFFFF - - - NUM_TARGET - The number of supported targets - 16 - 16 - read-only - - - NUM_INTERRUPT - The number of supported interrupt sources - 0 - 16 - read-only - - - - - INFO - Version and the maximum priority - 0x1104 - 32 - 0xFFFFFFFF - - - MAX_PRIORITY - The maximum priority supported - 16 - 16 - read-only - - - VERSION - The version of the PLIC design - 0 - 16 - read-only - - - - - 2 - 0x80 - target0,target1 - TARGETINT[%s] - no description available - 0x2000 - - 4 - 0x4 - INTEN0,INTEN1,INTEN2,INTEN3 - INTEN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - INTERRUPT - The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - 0 - 32 - read-write - - - - - - 2 - 0x1000 - target0,target1 - TARGETCONFIG[%s] - no description available - 0x200000 - - THRESHOLD - Target0 priority threshold - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - THRESHOLD - Interrupt priority threshold. - 0 - 32 - read-write - - - - - CLAIM - Target claim and complete - 0x4 - 32 - 0x00000000 - 0x000003FF - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 10 - read-write - - - - - PPS - Preempted priority stack - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRIORITY_PREEMPTED - Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - 0 - 32 - read-write - - - - - - - - MCHTMR - MCHTMR - MCHTMR - 0xe6000000 - - 0x0 - 0x10 - registers - - - - MTIME - Machine Time - 0x0 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIME - Machine time - 0 - 64 - read-write - - - - - MTIMECMP - Machine Time Compare - 0x8 - 64 - 0x0000000000020210 - 0xFFFFFFFFFFFFFFFF - - - MTIMECMP - Machine time compare - 0 - 64 - read-write - - - - - - - PLICSW - PLICSW - PLICSW - 0xe6400000 - - 0x1000 - 0x1ff008 - registers - - - - PENDING - Pending status - 0x1000 - 32 - 0x00000000 - 0x00000002 - - - INTERRUPT - writing 1 to trigger software interrupt - 1 - 1 - read-write - - - - - INTEN - Interrupt enable - 0x2000 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT - enable software interrupt - 0 - 1 - read-write - - - - - CLAIM - Claim and complete. - 0x200004 - 32 - 0x00000000 - 0x00000001 - - - INTERRUPT_ID - On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - 0 - 1 - read-write - - - - - - - GPTMR0 - GPTMR0 - GPTMR - 0xf0000000 - - 0x0 - 0x20c - registers - - - - 4 - 0x40 - ch0,ch1,ch2,ch3 - CHANNEL[%s] - no description available - 0x0 - - CR - Control Register - 0x0 - 32 - 0x00000000 - 0x8007FFFF - - - CNTUPT - 1- update counter to new value as CNTUPTVAL -This bit will be auto cleared after 1 cycle - 31 - 1 - write-only - - - CNT_MODE - 0: internal counting mode, timer increase each gptmr clock cycle. -1: external counting mode, timer increase at each input signal posedge, reload/compare feature can still work but change at input signal posedge. - 18 - 1 - read-write - - - OPMODE - 0: round mode -1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. -NOTE: reload irq will be always set at one-shot mode at end - 17 - 1 - read-write - - - MONITOR_SEL - set to monitor input signal high level time(chan_meas_high) -clr to monitor input signal period(chan_meas_prd) - 16 - 1 - read-write - - - MONITOR_EN - set to monitor input signal period or high level time. -When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts -* only can be used when trig_mode is selected as measure mode(100) -* the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. -if no posedge after reload for more than val_1, will also assert irq_capt - 15 - 1 - read-write - - - CNTRST - 1- reset counter - 14 - 1 - read-write - - - SYNCFLW - 1- enable this channel to reset counter to reload(RLD) together with its previous channel. -This bit is not valid for channel 0. - 13 - 1 - read-write - - - SYNCIFEN - 1- SYNCI is valid on its falling edge - 12 - 1 - read-write - - - SYNCIREN - 1- SYNCI is valid on its rising edge - 11 - 1 - read-write - - - CEN - 1- counter enable - 10 - 1 - read-write - - - CMPINIT - Output compare initial poliarity -1- The channel output initial level is high -0- The channel output initial level is low -User should set this bit before set CMPEN to 1. - 9 - 1 - read-write - - - CMPEN - 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - 8 - 1 - read-write - - - DMASEL - select one of DMA request: -00- CMP0 flag -01- CMP1 flag -10- Input signal toggle captured -11- RLD flag, counter reload; - 6 - 2 - read-write - - - DMAEN - 1- enable dma - 5 - 1 - read-write - - - SWSYNCIEN - 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - 4 - 1 - read-write - - - DBGPAUSE - 1- counter will pause if chip is in debug mode - 3 - 1 - read-write - - - CAPMODE - This bitfield define the input capture mode -100: width measure mode, timer will calculate the input signal period and duty cycle -011: capture at both rising edge and falling edge -010: capture at falling edge -001: capture at rising edge -000: No capture - 0 - 3 - read-write - - - - - 2 - 0x4 - CMP0,CMP1 - CMP[%s] - no description available - 0x4 - 32 - 0xFFFFFFF0 - 0xFFFFFFFF - - - CMP - compare value 0 - 0 - 32 - read-write - - - - - RLD - Reload register - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - RLD - reload value - 0 - 32 - read-write - - - - - CNTUPTVAL - Counter update value register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTUPTVAL - counter will be set to this value when software write cntupt bit in CR - 0 - 32 - read-write - - - - - CAPPOS - Capture rising edge register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPOS - This register contains the counter value captured at input signal rising edge - 0 - 32 - read-only - - - - - CAPNEG - Capture falling edge register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPNEG - This register contains the counter value captured at input signal falling edge - 0 - 32 - read-only - - - - - CAPPRD - PWM period measure register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPPRD - This register contains the input signal period when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CAPDTY - PWM duty cycle measure register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - MEAS_HIGH - This register contains the input signal duty cycle when channel is configured to input capture measure mode. - 0 - 32 - read-only - - - - - CNT - Counter - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - 32 bit counter value - 0 - 32 - read-only - - - - - - SR - Status register - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1F - channel 3 compare value 1 match flag - 15 - 1 - write-only - - - CH3CMP0F - channel 3 compare value 1 match flag - 14 - 1 - write-only - - - CH3CAPF - channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 13 - 1 - write-only - - - CH3RLDF - channel 3 counter reload flag - 12 - 1 - write-only - - - CH2CMP1F - channel 2 compare value 1 match flag - 11 - 1 - write-only - - - CH2CMP0F - channel 2 compare value 1 match flag - 10 - 1 - write-only - - - CH2CAPF - channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 9 - 1 - write-only - - - CH2RLDF - channel 2 counter reload flag - 8 - 1 - write-only - - - CH1CMP1F - channel 1 compare value 1 match flag - 7 - 1 - write-only - - - CH1CMP0F - channel 1 compare value 1 match flag - 6 - 1 - write-only - - - CH1CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 5 - 1 - write-only - - - CH1RLDF - channel 1 counter reload flag - 4 - 1 - write-only - - - CH0CMP1F - channel 1 compare value 1 match flag - 3 - 1 - write-only - - - CH0CMP0F - channel 1 compare value 1 match flag - 2 - 1 - write-only - - - CH0CAPF - channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - 1 - 1 - write-only - - - CH0RLDF - channel 1 counter reload flag - 0 - 1 - write-only - - - - - IRQEN - Interrupt request enable register - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3CMP1EN - 1- generate interrupt request when ch3cmp1f flag is set - 15 - 1 - read-write - - - CH3CMP0EN - 1- generate interrupt request when ch3cmp0f flag is set - 14 - 1 - read-write - - - CH3CAPEN - 1- generate interrupt request when ch3capf flag is set - 13 - 1 - read-write - - - CH3RLDEN - 1- generate interrupt request when ch3rldf flag is set - 12 - 1 - read-write - - - CH2CMP1EN - 1- generate interrupt request when ch2cmp1f flag is set - 11 - 1 - read-write - - - CH2CMP0EN - 1- generate interrupt request when ch2cmp0f flag is set - 10 - 1 - read-write - - - CH2CAPEN - 1- generate interrupt request when ch2capf flag is set - 9 - 1 - read-write - - - CH2RLDEN - 1- generate interrupt request when ch2rldf flag is set - 8 - 1 - read-write - - - CH1CMP1EN - 1- generate interrupt request when ch1cmp1f flag is set - 7 - 1 - read-write - - - CH1CMP0EN - 1- generate interrupt request when ch1cmp0f flag is set - 6 - 1 - read-write - - - CH1CAPEN - 1- generate interrupt request when ch1capf flag is set - 5 - 1 - read-write - - - CH1RLDEN - 1- generate interrupt request when ch1rldf flag is set - 4 - 1 - read-write - - - CH0CMP1EN - 1- generate interrupt request when ch0cmp1f flag is set - 3 - 1 - read-write - - - CH0CMP0EN - 1- generate interrupt request when ch0cmp0f flag is set - 2 - 1 - read-write - - - CH0CAPEN - 1- generate interrupt request when ch0capf flag is set - 1 - 1 - read-write - - - CH0RLDEN - 1- generate interrupt request when ch0rldf flag is set - 0 - 1 - read-write - - - - - GCR - Global control register - 0x208 - 32 - 0x00000000 - 0x0000000F - - - SWSYNCT - set this bitfield to trigger software counter sync event - 0 - 4 - read-write - - - - - - - GPTMR1 - GPTMR1 - GPTMR - 0xf0004000 - - - GPTMR2 - GPTMR2 - GPTMR - 0xf0008000 - - - GPTMR3 - GPTMR3 - GPTMR - 0xf000c000 - - - GPTMR4 - GPTMR4 - GPTMR - 0xf0010000 - - - GPTMR5 - GPTMR5 - GPTMR - 0xf0014000 - - - GPTMR6 - GPTMR6 - GPTMR - 0xf0018000 - - - GPTMR7 - GPTMR7 - GPTMR - 0xf001c000 - - - NTMR0 - NTMR0 - GPTMR - 0xf1410000 - - - NTMR1 - NTMR1 - GPTMR - 0xf1414000 - - - PTMR - PTMR - GPTMR - 0xf4120000 - - - UART0 - UART0 - UART - 0xf0040000 - - 0x4 - 0x3c - registers - - - - IDLE_CFG - Idle Configuration Register - 0x4 - 32 - 0x00000000 - 0x03FF0BFF - - - TX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if TX pin is logic one -1 - Treat as idle if UART state machine state is idle - 25 - 1 - read-write - - - TX_IDLE_EN - UART TX Idle Detect Enable -0 - Disable -1 - Enable - 24 - 1 - read-write - - - TX_IDLE_THR - Threshold for UART transmit Idle detection (in terms of bits) - 16 - 8 - read-write - - - RXEN - UART receive enable. -0 - hold RX input to high, avoide wrong data input when config pinmux -1 - bypass RX input from PIN -software should set it after config pinmux - 11 - 1 - read-write - - - RX_IDLE_COND - IDLE Detection Condition -0 - Treat as idle if RX pin is logic one -1 - Treat as idle if UART state machine state is idle - 9 - 1 - read-write - - - RX_IDLE_EN - UART Idle Detect Enable -0 - Disable -1 - Enable -it should be enabled if enable address match feature - 8 - 1 - read-write - - - RX_IDLE_THR - Threshold for UART Receive Idle detection (in terms of bits) - 0 - 8 - read-write - - - - - ADDR_CFG - address match config register - 0x8 - 32 - 0x00000000 - 0x001FFFFF - - - TXEN_9BIT - set to use 9bit mode for transmitter, -will set the MSB for the first character as address flag, keep 0 for others. - 20 - 1 - read-write - - - RXEN_ADDR_MSB - set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). -Clr to use first character as address. -Only needed if enable address match feature - 19 - 1 - read-write - - - RXEN_9BIT - set to use 9bit mode for receiver, only valid if rxen_addr_msb is set - 18 - 1 - read-write - - - A1_EN - enable addr1 compare for the first character. -If a1_en OR a0_en, then do not receive data if address not match. -If ~a1_en AND ~a0_en, the receive all data like before. -NOTE: should set idle_tmout_en if enable address match feature - 17 - 1 - read-write - - - A0_EN - enable addr0 compare for the first character - 16 - 1 - read-write - - - ADDR1 - address 1 fileld. -in 9bit mode, this is the full address byte. -For other mode(8/7/6/5bit), MSB should be set for address flag. -If want address==0 to be matched at 8bit mode, should set addr1=0x80 - 8 - 8 - read-write - - - ADDR0 - address 0 field. - 0 - 8 - read-write - - - - - IIR2 - Interrupt Identification Register2 - 0xc - 32 - 0x00000001 - 0xF80000CF - - - RXIDLE_FLAG - UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear -0 - UART RX is busy -1 - UART RX is idle - 31 - 1 - write-only - - - TXIDLE_FLAG - UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear -0 - UART TX is busy -1 - UART TX is idle - 30 - 1 - write-only - - - ADDR_MATCH - address match irq status, assert if either address match(and enabled). Write one clear -NOTE: the address byte may not moved by DMA at this point. -User can wait next addr_match_idle irq for the whole data include address - 29 - 1 - write-only - - - ADDR_MATCH_IDLE - address match and idle irq status, assert at rx bus idle if address match event triggered. -Write one clear; - 28 - 1 - write-only - - - DATA_LOST - assert if data lost before address match status, write one clear; -It will not assert if no address match occurs - 27 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FIFOSIZE - The depth of RXFIFO and TXFIFO -0: 16-byte FIFO -1: 32-byte FIFO -2: 64-byte FIFO -3: 128-byte FIFO - 0 - 2 - read-only - - - - - OSCR - Over Sample Control Register - 0x14 - 32 - 0x00000010 - 0x0000001F - - - OSC - Over-sample control -The value must be an even number; any odd value -writes to this field will be converted to an even value. -OSC=0: reserved -OSC<=8: The over-sample ratio is 8 -8 < OSC< 32: The over sample ratio is OSC - 0 - 5 - read-write - - - - - FCRR - FIFO Control Register config - 0x18 - 32 - 0x00000000 - 0x008F0FFF - - - FIFOT4EN - set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) -clr to use 2bit(TFIFOT and RFIFOT) - 23 - 1 - read-write - - - TFIFOT4 - txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. - 16 - 4 - read-write - - - RFIFOT4 - rxfifo threshold(0 for 1byte, 0xF for 16bytes). -Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled - 8 - 4 - read-write - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - read-write - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - read-write - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - read-write - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - read-write - - - - - MOTO_CFG - moto system control register - 0x1c - 32 - 0x00000000 - 0x8000FFF0 - - - SWTRG - software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. -Hardware auto reset. - 31 - 1 - write-only - - - TXSTP_BITS - if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits - 8 - 8 - read-write - - - HWTRG_EN - set to enable hardware trigger(trigger from moto is shared by other UART) - 7 - 1 - read-write - - - TRG_MODE - set to enable trigger mode. -software should push needed data into txbuffer frist, uart will not start transmission at this time. -User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty -NOTE: the hw_trigger should be pulse signal from trig mux. - 6 - 1 - read-write - - - TRG_CLR_RFIFO - set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. - 5 - 1 - read-write - - - TXSTOP_INSERT - set to insert STOP bits between each tx byte till tx fifo empty. -NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set - 4 - 1 - read-write - - - - - RBR - Receiver Buffer Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - RBR - Receive data read port - 0 - 8 - read-only - - - - - THR - Transmitter Holding Register (when DLAB = 0) - UNION_20 - 0x20 - 32 - 0x00000000 - 0x000000FF - - - THR - Transmit data write port - 0 - 8 - write-only - - - - - DLL - Divisor Latch LSB (when DLAB = 1) - UNION_20 - 0x20 - 32 - 0x00000001 - 0x000000FF - - - DLL - Least significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IER - Interrupt Enable Register (when DLAB = 0) - UNION_24 - 0x24 - 32 - 0x00000000 - 0xF800000F - - - ERXIDLE - Enable Receive Idle interrupt -0 - Disable Idle interrupt -1 - Enable Idle interrupt - 31 - 1 - read-write - - - ETXIDLE - enable transmit idle interrupt - 30 - 1 - read-write - - - EADDRM - enable ADDR_MATCH interrupt - 29 - 1 - read-write - - - EADDRM_IDLE - enable ADDR_MATCH_IDLE interrupt - 28 - 1 - read-write - - - EDATLOST - enable DATA_LOST interrupt - 27 - 1 - read-write - - - EMSI - Enable modem status interrupt -The interrupt asserts when the status of one of the -following occurs: -The status of modem_rin, modem_dcdn, -modem_dsrn or modem_ctsn (If the auto-cts mode is -disabled) has been changed. -If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), -modem_ctsn would be used to control the transmitter. - 3 - 1 - read-write - - - ELSI - Enable receiver line status interrupt - 2 - 1 - read-write - - - ETHEI - Enable transmitter holding register interrupt - 1 - 1 - read-write - - - ERBI - Enable received data available interrupt and the -character timeout interrupt -0: Disable -1: Enable - 0 - 1 - read-write - - - - - DLM - Divisor Latch MSB (when DLAB = 1) - UNION_24 - 0x24 - 32 - 0x00000000 - 0x000000FF - - - DLM - Most significant byte of the Divisor Latch - 0 - 8 - read-write - - - - - IIR - Interrupt Identification Register - UNION_28 - 0x28 - 32 - 0x00000001 - 0x800000CF - - - RXIDLE_FLAG - UART IDLE Flag -0 - UART is busy -1 - UART is idle -NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - 31 - 1 - write-only - - - FIFOED - FIFOs enabled -These two bits are 1 when bit 0 of the FIFO Control -Register (FIFOE) is set to 1. - 6 - 2 - read-only - - - INTRID - Interrupt ID, see IIR2 for detail decoding - 0 - 4 - read-only - - - - - FCR - FIFO Control Register - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000000FF - - - RFIFOT - Receiver FIFO trigger level - 6 - 2 - write-only - - - TFIFOT - Transmitter FIFO trigger level - 4 - 2 - write-only - - - DMAE - DMA enable -0: Disable -1: Enable - 3 - 1 - write-only - - - TFIFORST - Transmitter FIFO reset -Write 1 to clear all bytes in the TXFIFO and resets its -counter. The Transmitter Shift Register is not cleared. -This bit will automatically be cleared. - 2 - 1 - write-only - - - RFIFORST - Receiver FIFO reset -Write 1 to clear all bytes in the RXFIFO and resets its -counter. The Receiver Shift Register is not cleared. -This bit will automatically be cleared. - 1 - 1 - write-only - - - FIFOE - FIFO enable -Write 1 to enable both the transmitter and receiver -FIFOs. -The FIFOs are reset when the value of this bit toggles. - 0 - 1 - write-only - - - - - LCR - Line Control Register - 0x2c - 32 - 0x00000000 - 0x000000FF - - - DLAB - Divisor latch access bit - 7 - 1 - read-write - - - BC - Break control - 6 - 1 - read-write - - - SPS - Stick parity -1: Parity bit is constant 0 or 1, depending on bit4 (EPS). -0: Disable the sticky bit parity. - 5 - 1 - read-write - - - EPS - Even parity select -1: Even parity (an even number of logic-1 is in the data -and parity bits) -0: Old parity. - 4 - 1 - read-write - - - PEN - Parity enable -When this bit is set, a parity bit is generated in -transmitted data before the first STOP bit and the parity -bit would be checked for the received data. - 3 - 1 - read-write - - - STB - Number of STOP bits -0: 1 bits -1: The number of STOP bit is based on the WLS setting -When WLS = 0, STOP bit is 1.5 bits -When WLS = 1, 2, 3, STOP bit is 2 bits - 2 - 1 - read-write - - - WLS - Word length setting -0: 5 bits -1: 6 bits -2: 7 bits -3: 8 bits - 0 - 2 - read-write - - - - - MCR - Modem Control Register ( - 0x30 - 32 - 0x00000000 - 0x00000032 - - - AFE - Auto flow control enable -0: Disable -1: The auto-CTS and auto-RTS setting is based on the -RTS bit setting: -When RTS = 0, auto-CTS only -When RTS = 1, auto-CTS and auto-RTS - 5 - 1 - read-write - - - LOOP - Enable loopback mode -0: Disable -1: Enable - 4 - 1 - read-write - - - RTS - Request to send -This bit controls the modem_rtsn output. -0: The modem_rtsn output signal will be driven HIGH -1: The modem_rtsn output signal will be driven LOW - 1 - 1 - read-write - - - - - LSR - Line Status Register - 0x34 - 32 - 0x00000000 - 0xC01F1FFF - - - RXIDLE - rxidle after timeout, clear after rx idle condition not match - 31 - 1 - read-only - - - TXIDLE - txidle after timeout, clear after tx idle condition not match - 30 - 1 - read-only - - - RFIFO_NUM - data bytes in rxfifo not read - 16 - 5 - read-only - - - TFIFO_NUM - data bytes in txfifo not sent - 8 - 5 - read-only - - - ERRF - Error in RXFIFO -In the FIFO mode, this bit is set when there is at least -one parity error, framing error, or line break -associated with data in the RXFIFO. It is cleared when -this register is read and there is no more error for the -rest of data in the RXFIFO. - 7 - 1 - read-only - - - TEMT - Transmitter empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) and the Transmitter Shift Register (TSR) are -both empty. Otherwise, it is zero. - 6 - 1 - read-only - - - THRE - Transmitter Holding Register empty -This bit is 1 when the THR (TXFIFO in the FIFO -mode) is empty. Otherwise, it is zero. -If the THRE interrupt is enabled, an interrupt is -triggered when THRE becomes 1. - 5 - 1 - read-only - - - LBREAK - Line break -This bit is set when the uart_sin input signal was held -LOWfor longer than the time for a full-word -transmission. A full-word transmission is the -transmission of the START, data, parity, and STOP -bits. It is cleared when this register is read. -In the FIFO mode, this bit indicates the line break for -the received data at the top of the RXFIFO. - 4 - 1 - read-only - - - FE - Framing error -This bit is set when the received STOP bit is not -HIGH. It is cleared when this register is read. -In the FIFO mode, this bit indicates the framing error -for the received data at the top of the RXFIFO. - 3 - 1 - read-only - - - PE - Parity error -This bit is set when the received parity does not match -with the parity selected in the LCR[5:4]. It is cleared -when this register is read. -In the FIFO mode, this bit indicates the parity error -for the received data at the top of the RXFIFO. - 2 - 1 - read-only - - - OE - Overrun error -This bit indicates that data in the Receiver Buffer -Register (RBR) is overrun. - 1 - 1 - read-only - - - DR - Data ready. -This bit is set when there are incoming received data -in the Receiver Buffer Register (RBR). It is cleared -when all of the received data are read. - 0 - 1 - read-only - - - - - MSR - Modem Status Register - 0x38 - 32 - 0x00000000 - 0x00000011 - - - CTS - Clear to send -0: The modem_ctsn input signal is HIGH. -1: The modem_ctsn input signal is LOW. - 4 - 1 - read-only - - - DCTS - Delta clear to send -This bit is set when the state of the modem_ctsn input -signal has been changed since the last time this -register is read. - 0 - 1 - read-only - - - - - GPR - GPR Register - 0x3c - 32 - 0x00000000 - 0x000000FF - - - DATA - A one-byte storage register - 0 - 8 - read-write - - - - - - - UART1 - UART1 - UART - 0xf0044000 - - - UART2 - UART2 - UART - 0xf0048000 - - - UART3 - UART3 - UART - 0xf004c000 - - - UART4 - UART4 - UART - 0xf0050000 - - - UART5 - UART5 - UART - 0xf0054000 - - - UART6 - UART6 - UART - 0xf0058000 - - - UART7 - UART7 - UART - 0xf005c000 - - - UART8 - UART8 - UART - 0xf0180000 - - - UART9 - UART9 - UART - 0xf0184000 - - - UART10 - UART10 - UART - 0xf0188000 - - - UART11 - UART11 - UART - 0xf018c000 - - - UART12 - UART12 - UART - 0xf0190000 - - - UART13 - UART13 - UART - 0xf0194000 - - - UART14 - UART14 - UART - 0xf0198000 - - - UART15 - UART15 - UART - 0xf019c000 - - - PUART - PUART - UART - 0xf4124000 - - - I2C0 - I2C0 - I2C - 0xf0060000 - - 0x4 - 0x30 - registers - - - - Cfg - Configuration Register - 0x10 - 32 - 0x00000001 - 0xFFFFFFFF - - - FIFOSIZE - FIFO Size: -0: 2 bytes -1: 4 bytes -2: 8 bytes -3: 16 bytes - 0 - 2 - read-only - - - - - IntEn - Interrupt Enable Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMPL - Set to enable the Completion Interrupt. -Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. -Slave: interrupts when a transaction addressing the controller is completed. - 9 - 1 - read-write - - - BYTERECV - Set to enable the Byte Receive Interrupt. -Interrupts when a byte of data is received -Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - 8 - 1 - read-write - - - BYTETRANS - Set to enable the Byte Transmit Interrupt. -Interrupts when a byte of data is transmitted. - 7 - 1 - read-write - - - START - Set to enable the START Condition Interrupt. -Interrupts when a START condition/repeated START condition is detected. - 6 - 1 - read-write - - - STOP - Set to enable the STOP Condition Interrupt -Interrupts when a STOP condition is detected. - 5 - 1 - read-write - - - ARBLOSE - Set to enable the Arbitration Lose Interrupt. -Master: interrupts when the controller loses the bus arbitration -Slave: not available in this mode. - 4 - 1 - read-write - - - ADDRHIT - Set to enable the Address Hit Interrupt. -Master: interrupts when the addressed slave returned an ACK. -Slave: interrupts when the controller is addressed. - 3 - 1 - read-write - - - FIFOHALF - Set to enable the FIFO Half Interrupt. -Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. -Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. -This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - 2 - 1 - read-write - - - FIFOFULL - Set to enable the FIFO Full Interrupt. -Interrupts when the FIFO is full. - 1 - 1 - read-write - - - FIFOEMPTY - Set to enabled the FIFO Empty Interrupt -Interrupts when the FIFO is empty. - 0 - 1 - read-write - - - - - Status - Status Register - 0x18 - 32 - 0x00000001 - 0xFFFFFFFF - - - LINESDA - Indicates the current status of the SDA line on the bus -1: high -0: low - 14 - 1 - read-only - - - LINESCL - Indicates the current status of the SCL line on the bus -1: high -0: low - 13 - 1 - read-only - - - GENCALL - Indicates that the address of the current transaction is a general call address: -1: General call -0: Not general call - 12 - 1 - read-only - - - BUSBUSY - Indicates that the bus is busy -The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus -1: Busy -0: Not busy - 11 - 1 - read-only - - - ACK - Indicates the type of the last received/transmitted acknowledgement bit: -1: ACK -0: NACK - 10 - 1 - read-only - - - CMPL - Transaction Completion -Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration -Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - 9 - 1 - write-only - - - BYTERECV - Indicates that a byte of data has been received. - 8 - 1 - write-only - - - BYTETRANS - Indicates that a byte of data has been transmitted. - 7 - 1 - write-only - - - START - Indicates that a START Condition or a repeated START condition has been transmitted/received. - 6 - 1 - write-only - - - STOP - Indicates that a STOP Condition has been transmitted/received. - 5 - 1 - write-only - - - ARBLOSE - Indicates that the controller has lost the bus arbitration. - 4 - 1 - write-only - - - ADDRHIT - Master: indicates that a slave has responded to the transaction. -Slave: indicates that a transaction is targeting the controller (including the General Call). - 3 - 1 - write-only - - - FIFOHALF - Transmitter: Indicates that the FIFO is half-empty. - 2 - 1 - read-only - - - FIFOFULL - Indicates that the FIFO is full. - 1 - 1 - read-only - - - FIFOEMPTY - Indicates that the FIFO is empty. - 0 - 1 - read-only - - - - - Addr - Address Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - The slave address. -For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - 0 - 10 - read-write - - - - - Data - Data Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Write this register to put one byte of data to the FIFO. -Read this register to get one byte of data from the FIFO. - 0 - 8 - read-write - - - - - Ctrl - Control Register - 0x24 - 32 - 0x00905E00 - 0xFFFFFFFF - - - DATACNT_HIGH - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 24 - 8 - read-write - - - RESET_LEN - reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - 20 - 4 - read-write - - - RESET_HOLD_SCKIN - set to hold input clock to high when reset is active - 14 - 1 - read-write - - - RESET_ON - set to send reset signals(just toggle clock bus defined by reset_len). -this register is clered when reset is end, can't be cleared by software - 13 - 1 - read-write - - - PHASE_START - Enable this bit to send a START condition at the beginning of transaction. -Master mode only. - 12 - 1 - read-write - - - PHASE_ADDR - Enable this bit to send the address after START condition. -Master mode only. - 11 - 1 - read-write - - - PHASE_DATA - Enable this bit to send the data after Address phase. -Master mode only. - 10 - 1 - read-write - - - PHASE_STOP - Enable this bit to send a STOP condition at the end of a transaction. -Master mode only. - 9 - 1 - read-write - - - DIR - Transaction direction -Master: Set this bit to determine the direction for the next transaction. -0: Transmitter -1: Receiver -Slave: The direction of the last received transaction. -0: Receiver -1: Transmitter - 8 - 1 - read-write - - - DATACNT - Data counts in bytes. -Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. -Slave: the meaning of DataCnt depends on the DMA mode: -If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. -If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - 0 - 8 - read-write - - - - - Cmd - Command Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - Write this register with the following values to perform the corresponding actions: -0x0: no action -0x1: issue a data transaction (Master only) -0x2: respond with an ACK to the received byte -0x3: respond with a NACK to the received byte -0x4: clear the FIFO -0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) -When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. -Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - 0 - 3 - read-write - - - - - Setup - Setup Register - 0x2c - 32 - 0x05252100 - 0xFFFFFFFF - - - T_SUDAT - T_SUDAT defines the data setup time before releasing the SCL. -Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) -tpclk = PCLK period -TPM = The multiplier value in Timing Parameter Multiplier Register - 24 - 5 - read-write - - - T_SP - T_SP defines the pulse width of spikes that must be suppressed by the input filter. -Pulse width = T_SP * tpclk* (TPM+1) - 21 - 3 - read-write - - - T_HDDAT - T_HDDAT defines the data hold time after SCL goes LOW -Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - 16 - 5 - read-write - - - T_SCLRADIO - The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. -SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) -1: ratio = 2 -0: ratio = 1 -This field is only valid when the controller is in the master mode. - 13 - 1 - read-write - - - T_SCLHI - The HIGH period of generated SCL clock is defined by T_SCLHi. -SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) -The T_SCLHi value must be greater than T_SP and T_HDDAT values. -This field is only valid when the controller is in the master mode. - 4 - 9 - read-write - - - DMAEN - Enable the direct memory access mode data transfer. -1: Enable -0: Disable - 3 - 1 - read-write - - - MASTER - Configure this device as a master or a slave. -1: Master mode -0: Slave mode - 2 - 1 - read-write - - - ADDRESSING - I2C addressing mode: -1: 10-bit addressing mode -0: 7-bit addressing mode - 1 - 1 - read-write - - - IICEN - Enable the I2C controller. -1: Enable -0: Disable - 0 - 1 - read-write - - - - - TPM - I2C Timing Paramater Multiplier - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPM - A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - 0 - 5 - read-write - - - - - - - I2C1 - I2C1 - I2C - 0xf0064000 - - - I2C2 - I2C2 - I2C - 0xf0068000 - - - I2C3 - I2C3 - I2C - 0xf006c000 - - - I2C4 - I2C4 - I2C - 0xf01a0000 - - - I2C5 - I2C5 - I2C - 0xf01a4000 - - - I2C6 - I2C6 - I2C - 0xf01a8000 - - - I2C7 - I2C7 - I2C - 0xf01ac000 - - - SPI0 - SPI0 - SPI - 0xf0070000 - - 0x4 - 0x7c - registers - - - - wr_trans_cnt - Transfer count for write data - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 0 - 32 - read-write - - - - - rd_trans_cnt - Transfer count for read data - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 32 - read-write - - - - - TransFmt - Transfer Format Register - 0x10 - 32 - 0x00020780 - 0xFFFF1F9F - - - ADDRLEN - Address length in bytes -0x0: 1 byte -0x1: 2 bytes -0x2: 3 bytes -0x3: 4 bytes - 16 - 2 - read-write - - - DATALEN - The length of each data unit in bits -The actual bit number of a data unit is (DataLen + 1) - 8 - 5 - read-write - - - DATAMERGE - Enable Data Merge mode, which does automatic data split on write and data coalescing on read. -This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. -When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - 7 - 1 - read-write - - - MOSIBIDIR - Bi-directional MOSI in regular (single) mode -0x0: MOSI is uni-directional signal in regular mode. -0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - 4 - 1 - read-write - - - LSB - Transfer data with the least significant bit first -0x0: Most significant bit first -0x1: Least significant bit first - 3 - 1 - read-write - - - SLVMODE - SPI Master/Slave mode selection -0x0: Master mode -0x1: Slave mode - 2 - 1 - read-write - - - CPOL - SPI Clock Polarity -0x0: SCLK is LOW in the idle states -0x1: SCLK is HIGH in the idle states - 1 - 1 - read-write - - - CPHA - SPI Clock Phase -0x0: Sampling data at odd SCLK edges -0x1: Sampling data at even SCLK edges - 0 - 1 - read-write - - - - - DirectIO - Direct IO Control Register - 0x14 - 32 - 0x00003100 - 0x013F3F3F - - - DIRECTIOEN - Enable Direct IO -0x0: Disable -0x1: Enable - 24 - 1 - read-write - - - HOLD_OE - Output enable for the SPI Flash hold signal - 21 - 1 - read-write - - - WP_OE - Output enable for the SPI Flash write protect signal - 20 - 1 - read-write - - - MISO_OE - Output enable fo the SPI MISO signal - 19 - 1 - read-write - - - MOSI_OE - Output enable for the SPI MOSI signal - 18 - 1 - read-write - - - SCLK_OE - Output enable for the SPI SCLK signal - 17 - 1 - read-write - - - CS_OE - Output enable for SPI CS (chip select) signal - 16 - 1 - read-write - - - HOLD_O - Output value for the SPI Flash hold signal - 13 - 1 - read-write - - - WP_O - Output value for the SPI Flash write protect signal - 12 - 1 - read-write - - - MISO_O - Output value for the SPI MISO signal - 11 - 1 - read-write - - - MOSI_O - Output value for the SPI MOSI signal - 10 - 1 - read-write - - - SCLK_O - Output value for the SPI SCLK signal - 9 - 1 - read-write - - - CS_O - Output value for the SPI CS (chip select) signal - 8 - 1 - read-write - - - HOLD_I - Status of the SPI Flash hold signal - 5 - 1 - read-only - - - WP_I - Status of the SPI Flash write protect signal - 4 - 1 - read-only - - - MISO_I - Status of the SPI MISO signal - 3 - 1 - read-only - - - MOSI_I - Status of the SPI MOSI signal - 2 - 1 - read-only - - - SCLK_I - Status of the SPI SCLK signal - 1 - 1 - read-only - - - CS_I - Status of the SPI CS (chip select) signal - 0 - 1 - read-only - - - - - TransCtrl - Transfer Control Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - SLVDATAONLY - Data-only mode (slave mode only) -0x0: Disable the data-only mode -0x1: Enable the data-only mode -Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - 31 - 1 - read-write - - - CMDEN - SPI command phase enable (Master mode only) -0x0: Disable the command phase -0x1: Enable the command phase - 30 - 1 - read-write - - - ADDREN - SPI address phase enable (Master mode only) -0x0: Disable the address phase -0x1: Enable the address phase - 29 - 1 - read-write - - - ADDRFMT - SPI address phase format (Master mode only) -0x0: Address phase is the regular (single) mode -0x1: The format of the address phase is the same as the data phase (DualQuad). - 28 - 1 - read-write - - - TRANSMODE - Transfer mode -The transfer sequence could be -0x0: Write and read at the same time -0x1: Write only -0x2: Read only -0x3: Write, Read -0x4: Read, Write -0x5: Write, Dummy, Read -0x6: Read, Dummy, Write -0x7: None Data (must enable CmdEn or AddrEn in master mode) -0x8: Dummy, Write -0x9: Dummy, Read -0xa~0xf: Reserved - 24 - 4 - read-write - - - DUALQUAD - SPI data phase format -0x0: Regular (Single) mode -0x1: Dual I/O mode -0x2: Quad I/O mode -0x3: Reserved - 22 - 2 - read-write - - - TOKENEN - Token transfer enable (Master mode only) -Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. -0x0: Disable the one-byte special token -0x1: Enable the one-byte special token - 21 - 1 - read-write - - - WRTRANCNT - Transfer count for write data -WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). -WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must be equal to RdTranCnt. - 12 - 9 - read-write - - - TOKENVALUE - Token value (Master mode only) -The value of the one-byte special token following the address phase for SPI read transfers. -0x0: token value = 0x00 -0x1: token value = 0x69 - 11 - 1 - read-write - - - DUMMYCNT - Dummy data count. The actual dummy count is (DummyCnt +1). -The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) -The Data pins are put into the high impedance during the dummy data phase. -DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - 9 - 2 - read-write - - - RDTRANCNT - Transfer count for read data -RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). -RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. -The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. -For TransMode 0, WrTranCnt must equal RdTranCnt. - 0 - 9 - read-write - - - - - Cmd - Command Register - 0x24 - 32 - 0x00000000 - 0x000000FF - - - CMD - SPI Command - 0 - 8 - read-write - - - - - Addr - Address Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - SPI Address -(Master mode only) - 0 - 32 - read-write - - - - - Data - Data Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Data to transmit or the received data -For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. -The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. -If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - 0 - 32 - read-write - - - - - Ctrl - Control Register - 0x30 - 32 - 0x00000000 - 0x0FFFFF1F - - - CS_EN - No description available - 24 - 4 - read-write - - - TXTHRES - Transmit (TX) FIFO Threshold -The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - 16 - 8 - read-write - - - RXTHRES - Receive (RX) FIFO Threshold -The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - 8 - 8 - read-write - - - TXDMAEN - TX DMA enable - 4 - 1 - read-write - - - RXDMAEN - RX DMA enable - 3 - 1 - read-write - - - TXFIFORST - Transmit FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 2 - 1 - read-write - - - RXFIFORST - Receive FIFO reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 1 - 1 - read-write - - - SPIRST - SPI reset -Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - 0 - 1 - read-write - - - - - Status - Status Register - 0x34 - 32 - 0x00000000 - 0x33FFFF01 - - - TXNUM_7_6 - Number of valid entries in the Transmit FIFO - 28 - 2 - read-only - - - RXNUM_7_6 - Number of valid entries in the Receive FIFO - 24 - 2 - read-only - - - TXFULL - Transmit FIFO Full flag - 23 - 1 - read-only - - - TXEMPTY - Transmit FIFO Empty flag - 22 - 1 - read-only - - - TXNUM_5_0 - Number of valid entries in the Transmit FIFO - 16 - 6 - read-only - - - RXFULL - Receive FIFO Full flag - 15 - 1 - read-only - - - RXEMPTY - Receive FIFO Empty flag - 14 - 1 - read-only - - - RXNUM_5_0 - Number of valid entries in the Receive FIFO - 8 - 6 - read-only - - - SPIACTIVE - SPI register programming is in progress. -In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. -In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. -Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. -Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - 0 - 1 - read-only - - - - - IntrEn - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000003F - - - SLVCMDEN - Enable the Slave Command Interrupt. -Control whether interrupts are triggered whenever slave commands are received. -(Slave mode only) - 5 - 1 - read-write - - - ENDINTEN - Enable the End of SPI Transfer interrupt. -Control whether interrupts are triggered when SPI transfers end. -(In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - 4 - 1 - read-write - - - TXFIFOINTEN - Enable the SPI Transmit FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - 3 - 1 - read-write - - - RXFIFOINTEN - Enable the SPI Receive FIFO Threshold interrupt. -Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - 2 - 1 - read-write - - - TXFIFOURINTEN - Enable the SPI Transmit FIFO Underrun interrupt. -Control whether interrupts are triggered when the Transmit FIFO run out of data. -(Slave mode only) - 1 - 1 - read-write - - - RXFIFOORINTEN - Enable the SPI Receive FIFO Overrun interrupt. -Control whether interrupts are triggered when the Receive FIFO overflows. -(Slave mode only) - 0 - 1 - read-write - - - - - IntrSt - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000003F - - - SLVCMDINT - Slave Command Interrupt. -This bit is set when Slave Command interrupts occur. -(Slave mode only) - 5 - 1 - write-only - - - ENDINT - End of SPI Transfer interrupt. -This bit is set when End of SPI Transfer interrupts occur. - 4 - 1 - write-only - - - TXFIFOINT - TX FIFO Threshold interrupt. -This bit is set when TX FIFO Threshold interrupts occur. - 3 - 1 - write-only - - - RXFIFOINT - RX FIFO Threshold interrupt. -This bit is set when RX FIFO Threshold interrupts occur. - 2 - 1 - write-only - - - TXFIFOURINT - TX FIFO Underrun interrupt. -This bit is set when TX FIFO Underrun interrupts occur. -(Slave mode only) - 1 - 1 - write-only - - - RXFIFOORINT - RX FIFO Overrun interrupt. -This bit is set when RX FIFO Overrun interrupts occur. -(Slave mode only) - 0 - 1 - write-only - - - - - Timing - Interface Timing Register - 0x40 - 32 - 0x00000000 - 0x00003FFF - - - CS2SCLK - The minimum time between the edges of SPI CS and the edges of SCLK. -SCLK_period * (CS2SCLK + 1) / 2 - 12 - 2 - read-write - - - CSHT - The minimum time that SPI CS should stay HIGH. -SCLK_period * (CSHT + 1) / 2 - 8 - 4 - read-write - - - SCLK_DIV - The clock frequency ratio between the clock source and SPI interface SCLK. -SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) -The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - 0 - 8 - read-write - - - - - SlvSt - Slave Status Register - 0x60 - 32 - 0x00000000 - 0x0007FFFF - - - UNDERRUN - Data underrun occurs in the last transaction - 18 - 1 - write-only - - - OVERRUN - Data overrun occurs in the last transaction - 17 - 1 - read-write - - - READY - Set this bit to indicate that the ATCSPI200 is ready for data transaction. -When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - 16 - 1 - read-write - - - USR_STATUS - User defined status flags - 0 - 16 - read-write - - - - - SlvDataCnt - Slave Data Count Register - 0x64 - 32 - 0x00000000 - 0x03FF03FF - - - WCNT - Slave transmitted data count - 16 - 10 - read-only - - - RCNT - Slave received data count - 0 - 10 - read-only - - - - - SlvDataWCnt - WCnt - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - SlvDataRCnt - RCnt - 0x6c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - No description available - 0 - 32 - read-only - - - - - Config - Configuration Register - 0x7c - 32 - 0x00004311 - 0x000043FF - - - SLAVE - Support for SPI Slave mode - 14 - 1 - read-only - - - QUADSPI - Support for Quad I/O SPI - 9 - 1 - read-only - - - DUALSPI - Support for Dual I/O SPI - 8 - 1 - read-only - - - TXFIFOSIZE - Depth of TX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 4 - 4 - read-only - - - RXFIFOSIZE - Depth of RX FIFO -0x0: 2 words -0x1: 4 words -0x2: 8 words -0x3: 16 words -0x4: 32 words -0x5: 64 words -0x6: 128 words - 0 - 4 - read-only - - - - - - - SPI1 - SPI1 - SPI - 0xf0074000 - - - SPI2 - SPI2 - SPI - 0xf0078000 - - - SPI3 - SPI3 - SPI - 0xf007c000 - - - SPI4 - SPI4 - SPI - 0xf01b0000 - - - SPI5 - SPI5 - SPI - 0xf01b4000 - - - SPI6 - SPI6 - SPI - 0xf01b8000 - - - SPI7 - SPI7 - SPI - 0xf01bc000 - - - CRC - CRC - CRC - 0xf0080000 - - 0x0 - 0x200 - registers - - - - 8 - 0x40 - 0,1,2,3,4,5,6,7 - CHN[%s] - no description available - 0x0 - - pre_set - &index0 pre set for crc setting - 0x0 - 32 - 0x00000000 - 0x000000FF - - - PRE_SET - 0: no pre set -1: CRC32 -2: CRC32-AUTOSAR -3: CRC16-CCITT -4: CRC16-XMODEM -5: CRC16-MODBUS -1: CRC32 -2: CRC32-autosar -3: CRC16-ccitt -4: CRC16-xmodem -5: CRC16-modbus -6: crc16_dnp -7: crc16_x25 -8: crc16_usb -9: crc16_maxim -10: crc16_ibm -11: crc8_maxim -12: crc8_rohc -13: crc8_itu -14: crc8 -15: crc5_usb - 0 - 8 - read-write - - - - - clr - chn&index0 clear crc result and setting - 0x4 - 32 - 0x00000000 - 0x00000001 - - - CLR - write 1 to clr crc setting and result for its channel. -always read 0. - 0 - 1 - read-write - - - - - poly - chn&index0 poly - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - poly setting - 0 - 32 - read-write - - - - - init_data - chn&index0 init_data - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - INIT_DATA - initial data of CRC - 0 - 32 - read-write - - - - - xorout - chn&index0 xorout - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - XOROUT - XOR for CRC result - 0 - 32 - read-write - - - - - misc_setting - chn&index0 misc_setting - 0x14 - 32 - 0x00000000 - 0x0101013F - - - BYTE_REV - 0: no wrap input byte order -1: wrap input byte order - 24 - 1 - read-write - - - REV_OUT - 0: no wrap output bit order -1: wrap output bit order - 16 - 1 - read-write - - - REV_IN - 0: no wrap input bit order -1: wrap input bit order - 8 - 1 - read-write - - - POLY_WIDTH - crc data length - 0 - 6 - read-write - - - - - data - chn&index0 data - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data for crc - 0 - 32 - read-write - - - - - result - chn&index0 result - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RESULT - crc result - 0 - 32 - read-write - - - - - - - - TSNS - TSNS - TSNS - 0xf0090000 - - 0x0 - 0x3c - registers - - - - T - Temperature - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Signed number of temperature in 256 x celsius degree - 0 - 32 - read-only - - - - - TMAX - Maximum Temperature - 0x4 - 32 - 0xFF800000 - 0xFFFFFFFF - - - T - maximum temperature ever found - 0 - 32 - read-only - - - - - TMIN - Minimum Temperature - 0x8 - 32 - 0x007FFFFF - 0xFFFFFFFF - - - T - minimum temperature ever found - 0 - 32 - read-only - - - - - AGE - Sample age - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - AGE - age of T register in 24MHz clock cycles - 0 - 32 - read-only - - - - - STATUS - Status - 0x10 - 32 - 0x00000000 - 0x80000001 - - - VALID - indicate value in T is valid or not -0: not valid -1:valid - 31 - 1 - read-only - - - TRIGGER - Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - 0 - 1 - write-only - - - - - CONFIG - Configuration - 0x14 - 32 - 0x00600300 - 0xC3FF0713 - - - IRQ_EN - Enable interrupt - 31 - 1 - read-write - - - RST_EN - Enable reset - 30 - 1 - read-write - - - COMPARE_MIN_EN - Enable compare for minimum temperature - 25 - 1 - read-write - - - COMPARE_MAX_EN - Enable compare for maximum temperature - 24 - 1 - read-write - - - SPEED - cycles of a progressive step in 24M clock, valid from 24-255, default 96 -24: 24 cycle for a step -25: 25 cycle for a step -26: 26 cycle for a step -... -255: 255 cycle for a step - 16 - 8 - read-write - - - AVERAGE - Average time, default in 3 -0: measure and return -1: twice and average -2: 4 times and average -. . . -7: 128 times and average - 8 - 3 - read-write - - - CONTINUOUS - continuous mode that keep sampling temperature peridically -0: trigger mode -1: continuous mode - 4 - 1 - read-write - - - ASYNC - Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value -0: active mode -1: Async mode - 1 - 1 - read-write - - - ENABLE - Enable temperature -0: disable, temperature sensor is shut down -1: enable. Temperature sensor enabled - 0 - 1 - read-write - - - - - VALIDITY - Sample validity - 0x18 - 32 - 0x016E3600 - 0xFFFFFFFF - - - VALIDITY - time for temperature values to expire in 24M clock cycles - 0 - 32 - read-write - - - - - FLAG - Temperature flag - 0x1c - 32 - 0x00000000 - 0x00330001 - - - RECORD_MIN_CLR - Clear minimum recorder of temerature, write 1 to clear - 21 - 1 - read-write - - - RECORD_MAX_CLR - Clear maximum recorder of temerature, write 1 to clear - 20 - 1 - read-write - - - UNDER_TEMP - Clear under temperature status, write 1 to clear - 17 - 1 - read-write - - - OVER_TEMP - Clear over temperature status, write 1 to clear - 16 - 1 - read-write - - - IRQ - IRQ flag, write 1 to clear - 0 - 1 - read-write - - - - - UPPER_LIM_IRQ - Maximum temperature to interrupt - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_IRQ - Minimum temperature to interrupt - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - UPPER_LIM_RST - Maximum temperature to reset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Maximum temperature for compare - 0 - 32 - read-write - - - - - LOWER_LIM_RST - Minimum temperature to reset - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - T - Minimum temperature for compare - 0 - 32 - read-write - - - - - ASYNC - Configuration in asynchronous mode - 0x30 - 32 - 0x00000000 - 0x010107FF - - - ASYNC_TYPE - Compare hotter than or colder than in asynchoronous mode -0: hotter than -1: colder than - 24 - 1 - read-write - - - POLARITY - Polarity of internal comparator - 16 - 1 - read-write - - - VALUE - Value of async mode to compare - 0 - 11 - read-write - - - - - ADVAN - Advance configuration - 0x38 - 32 - 0x00000000 - 0x03010003 - - - ASYNC_IRQ - interrupt status of asynchronous mode - 25 - 1 - read-only - - - ACTIVE_IRQ - interrupt status of active mode - 24 - 1 - read-only - - - SAMPLING - temperature sampling is working - 16 - 1 - read-only - - - NEG_ONLY - use negative compare polarity only - 1 - 1 - read-write - - - POS_ONLY - use positive compare polarity only - 0 - 1 - read-write - - - - - - - MBX0A - MBX0A - MBX - 0xf00a0000 - - 0x0 - 0x24 - registers - - - - CR - Command Registers - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXRESET - Reset TX Fifo and word. - 31 - 1 - read-write - - - BARCTL - Bus Access Response Control, when bit 15:14= -00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. -10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. -11: reserved. - 14 - 2 - read-write - - - BEIE - Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. -1, enable the bus access error interrupt. -0, disable the bus access error interrupt. - 8 - 1 - read-write - - - TFMAIE - TX FIFO message available interrupt enable. -1, enable the TX FIFO massage available interrupt. -0, disable the TX FIFO message available interrupt. - 7 - 1 - read-write - - - TFMEIE - TX FIFO message empty interrupt enable. -1, enable the TX FIFO massage empty interrupt. -0, disable the TX FIFO message empty interrupt. - 6 - 1 - read-write - - - RFMAIE - RX FIFO message available interrupt enable. -1, enable the RX FIFO massage available interrupt. -0, disable the RX FIFO message available interrupt. - 5 - 1 - read-write - - - RFMFIE - RX fifo message full interrupt enable. -1, enable the RX fifo message full interrupt. -0, disable the RX fifo message full interrupt. - 4 - 1 - read-write - - - TWMEIE - TX word message empty interrupt enable. -1, enable the TX word massage empty interrupt. -0, disable the TX word message empty interrupt. - 1 - 1 - read-write - - - RWMVIE - RX word message valid interrupt enable. -1, enable the RX word massage valid interrupt. -0, disable the RX word message valid interrupt. - 0 - 1 - read-write - - - - - SR - Status Registers - 0x4 - 32 - 0x000000E2 - 0xFFFF3FFF - - - RFVC - RX FIFO valid message count - 20 - 4 - read-only - - - TFEC - TX FIFO empty message word count - 16 - 4 - read-only - - - ERRRE - bus Error for read when rx word message are still invalid, this bit is W1C bit. -1, read from word message when the word message are still invalid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 13 - 1 - write-only - - - EWTRF - bus Error for write when tx word message are still valid, this bit is W1C bit. -1, write to word message when the word message are still valid will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 12 - 1 - write-only - - - ERRFE - bus Error for read when rx fifo empty, this bit is W1C bit. -1, read from a empty rx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 11 - 1 - write-only - - - EWTFF - bus Error for write when tx fifo full, this bit is W1C bit. -1, write to a fulled tx fifo will cause this error bit set. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 10 - 1 - write-only - - - EAIVA - bus Error for Accessing Invalid Address; this bit is W1C bit. -1, read and write to invalid address in the bus of this block, will set this bit. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 9 - 1 - write-only - - - EW2RO - bus Error for Write to Read Only address; this bit is W1C bit. -1, write to read only address happened in the bus of this block. -0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - 8 - 1 - write-only - - - TFMA - TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. -1, TXFIFO message buffer has slot available -0, no slot available (fifo full) - 7 - 1 - read-write - - - TFME - TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. -1, no any message data in TXFIFO from other core. -0, there are some data in the 4x32 TX FIFO from other core yet. - 6 - 1 - read-write - - - RFMA - RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, no any data in the 4x32 TXFIFO message buffer. -0, there are some data in the the 4x32 TXFIFO message buffer already. - 5 - 1 - read-only - - - RFMF - RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written 4x32 message in the RXFIFO. -0, no 4x32 RX FIFO message from other core yet. - 4 - 1 - read-only - - - TWME - TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, means this core had write word message to TXREG. -0, means no valid word message in the TXREG yet. - 1 - 1 - read-only - - - RWMV - RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. -1, the other core had written word message in the RXREG. -0, no valid word message yet in the RXREG. - 0 - 1 - read-only - - - - - TXREG - Transmit word message to other core. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXREG - Transmit word message to other core. - 0 - 32 - write-only - - - - - RXREG - Receive word message from other core. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - RXREG - Receive word message from other core. - 0 - 32 - read-only - - - - - 1 - 0x4 - TXFIFO0 - TXWRD[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXFIFO - TXFIFO for sending message to other core, FIFO size, 4x32 -can write one of the word address to push data to the FIFO; -can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - 0 - 32 - write-only - - - - - 1 - 0x4 - RXFIFO0 - RXWRD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXFIFO - RXFIFO for receiving message from other core, FIFO size, 4x32 -can read one of the word address to pop data to the FIFO; -can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - 0 - 32 - read-only - - - - - - - MBX0B - MBX0B - MBX - 0xf00a4000 - - - MBX1A - MBX1A - MBX - 0xf00a8000 - - - MBX1B - MBX1B - MBX - 0xf00ac000 - - - EWDG0 - EWDG0 - EWDG - 0xf00b0000 - - 0x0 - 0x28 - registers - - - - CTRL0 - wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x0 - 32 - 0x00000000 - 0x2FE2F03F - - - CLK_SEL - clock select -0：bus clock -1：ext clock - 29 - 1 - read-write - - - DIV_VALUE - clock divider, the clock divider works as 2 ^ div_value for wdt counter - 25 - 3 - read-write - - - WIN_EN - window mode enable - 24 - 1 - read-write - - - WIN_LOWER - Once window mode is opened, the lower counter value to refresh wdt -00: 4/8 overtime value -01: 5/8 of overtime value -10: 6/8 of overtime value -11: 7/8 of overtime value - 22 - 2 - read-write - - - CFG_LOCK - The register is locked and unlock is needed before re-config registers -Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. -The register update needs to be finished in the required period defined by UPD_OT_TIME register - 21 - 1 - read-write - - - OT_SELF_CLEAR - overtime reset can be self released after 32 function cycles - 17 - 1 - read-write - - - REF_OT_REQ - If refresh event has to be limited into a period after refresh unlocked. -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 15 - 1 - read-write - - - WIN_UPPER - The upper threshold of window value -The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value -If this register value is zero, then no upper level limitation - 12 - 3 - read-write - - - REF_LOCK - WDT refresh has to be unlocked firstly once refresh lock is enable. - 5 - 1 - read-write - - - REF_UNLOCK_MEC - Unlock refresh mechanism -00: the required unlock password is the same with refresh_psd_register -01: the required unlock password is a ring shift left value of refresh_psd_register -10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is -11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - 3 - 2 - read-write - - - EN_DBG - WTD enable or not in debug mode - 2 - 1 - read-write - - - EN_LP - WDT enable or not in low power mode -2'b00: wdt is halted once in low power mode -2'b01: wdt will work with 1/4 normal clock freq in low power mode -2'b10: wdt will work with 1/2 normal clock freq in low power mode -2'b11: wdt will work with normal clock freq in low power mode - 0 - 2 - read-write - - - - - CTRL1 - wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits - 0x4 - 32 - 0x00000000 - 0x00F300FC - - - REF_FAIL_RST_EN - Refresh violation will trigger an reset. -These event will be taken as a refresh violation: -1) Not refresh in the window once window mode is enabled -2) Not unlock refresh firstly if unlock is required -3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. -4) Not write the required word to refresh wdt. - 23 - 1 - read-write - - - REF_FAIL_INT_EN - Refresh violation will trigger an interrupt - 22 - 1 - read-write - - - UNL_REF_FAIL_RST_EN - Refresh unlock fail will trigger a reset - 21 - 1 - read-write - - - UNL_REF_FAIL_INT_EN - Refresh unlock fail will trigger a interrupt - 20 - 1 - read-write - - - OT_RST_EN - WDT overtime will generate a reset - 17 - 1 - read-write - - - OT_INT_EN - WDT can generate an interrupt warning before timeout - 16 - 1 - read-write - - - CTL_VIO_RST_EN - Ctrl update violation will trigger a reset -The violation event is to try updating the locked register before unlock them - 7 - 1 - read-write - - - CTL_VIO_INT_EN - Ctrl update violation will trigger a interrupt - 6 - 1 - read-write - - - UNL_CTL_FAIL_RST_EN - Unlock register update failure will trigger a reset - 5 - 1 - read-write - - - UNL_CTL_FAIL_INT_EN - Unlock register update failure will trigger a interrupt - 4 - 1 - read-write - - - PARITY_FAIL_RST_EN - Parity error will trigger a reset -A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - 3 - 1 - read-write - - - PARITY_FAIL_INT_EN - Parity error will trigger a interrupt - 2 - 1 - read-write - - - - - OT_INT_VAL - wdog timeout interrupt counter value - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - OT_INT_VAL - WDT timeout interrupt value - 0 - 16 - read-write - - - - - OT_RST_VAL - wdog timeout reset counter value - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - OT_RST_VAL - WDT timeout reset value - 0 - 16 - read-write - - - - - WDT_REFRESH_REG - wdog refresh register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDT_REFRESH_REG - Write this register by 32'h5A45_524F to refresh wdog -Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - 0 - 32 - write-only - - - - - WDT_STATUS - wdog status register - 0x14 - 32 - 0x00000000 - 0x0000007F - - - PARITY_ERROR - parity error -Write one to clear the bit - 6 - 1 - write-only - - - OT_RST - Timeout happens, a reset will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 5 - 1 - write-only - - - OT_INT - Timeout happens, a interrupt will happen once enable bit set -This bit can be cleared only by refreshing wdt or reset - 4 - 1 - write-only - - - CTL_UNL_FAIL - Unlock ctrl reg update protection fail -Write one to clear the bit - 3 - 1 - write-only - - - CTL_VIO - Violate register update protection mechanism -Write one to clear the bit - 2 - 1 - write-only - - - REF_UNL_FAIL - Refresh unlock fail -Write one to clear the bit - 1 - 1 - write-only - - - REF_VIO - Refresh fail -Write one to clear the bit - 0 - 1 - write-only - - - - - CFG_PROT - ctrl register protection register - 0x18 - 32 - 0x00000000 - 0x000FFFFF - - - UPD_OT_TIME - The period in which register update has to be in after unlock -The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - 16 - 4 - read-write - - - UPD_PSD - The password of unlocking register update - 0 - 16 - read-write - - - - - REF_PROT - refresh protection register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - REF_UNL_PSD - The password to unlock refreshing - 0 - 16 - read-write - - - - - WDT_EN - Wdog enable - 0x20 - 32 - 0x00000000 - 0x00000001 - - - WDOG_EN - Wdog is enabled, the re-written of this register is impacted by enable lock function - 0 - 1 - read-write - - - - - REF_TIME - Refresh period value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - REFRESH_PERIOD - The refresh period after refresh unlocked -Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - 0 - 16 - read-write - - - - - - - EWDG1 - EWDG1 - EWDG - 0xf00b4000 - - - EWDG2 - EWDG2 - EWDG - 0xf00b8000 - - - EWDG3 - EWDG3 - EWDG - 0xf00bc000 - - - PEWDG - PEWDG - EWDG - 0xf4128000 - - - DMAMUX - DMAMUX - DMAMUX - 0xf00c4000 - - 0x0 - 0x100 - registers - - - - 64 - 0x4 - HDMA_MUX0,HDMA_MUX1,HDMA_MUX2,HDMA_MUX3,HDMA_MUX4,HDMA_MUX5,HDMA_MUX6,HDMA_MUX7,HDMA_MUX8,HDMA_MUX9,HDMA_MUX10,HDMA_MUX11,HDMA_MUX12,HDMA_MUX13,HDMA_MUX14,HDMA_MUX15,HDMA_MUX16,HDMA_MUX17,HDMA_MUX18,HDMA_MUX19,HDMA_MUX20,HDMA_MUX21,HDMA_MUX22,HDMA_MUX23,HDMA_MUX24,HDMA_MUX25,HDMA_MUX26,HDMA_MUX27,HDMA_MUX28,HDMA_MUX29,HDMA_MUX30,HDMA_MUX31,XDMA_MUX0,XDMA_MUX1,XDMA_MUX2,XDMA_MUX3,XDMA_MUX4,XDMA_MUX5,XDMA_MUX6,XDMA_MUX7,XDMA_MUX8,XDMA_MUX9,XDMA_MUX10,XDMA_MUX11,XDMA_MUX12,XDMA_MUX13,XDMA_MUX14,XDMA_MUX15,XDMA_MUX16,XDMA_MUX17,XDMA_MUX18,XDMA_MUX19,XDMA_MUX20,XDMA_MUX21,XDMA_MUX22,XDMA_MUX23,XDMA_MUX24,XDMA_MUX25,XDMA_MUX26,XDMA_MUX27,XDMA_MUX28,XDMA_MUX29,XDMA_MUX30,XDMA_MUX31 - MUXCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x8000007F - - - ENABLE - DMA Mux Channel Enable -Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be -used to disable or reconfigure a DMA channel. -0b - DMA Mux channel is disabled -1b - DMA Mux channel is enabled - 31 - 1 - write-only - - - SOURCE - DMA Channel Source -Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - 0 - 7 - write-only - - - - - - - HDMA - HDMA - DMAV2 - 0xf00c8000 - - 0x4 - 0x43c - registers - - - - IDMisc - ID Misc - 0x4 - 32 - 0x00000000 - 0x0000FF00 - - - DMASTATE - DMA state machine -localparam ST_IDLE = 3'b000; -localparam ST_READ = 3'b001; -localparam ST_READ_ACK = 3'b010; -localparam ST_WRITE = 3'b011; -localparam ST_WRITE_ACK = 3'b100; -localparam ST_LL = 3'b101; -localparam ST_END = 3'b110; -localparam ST_END_WAIT = 3'b111; - 13 - 3 - read-only - - - CURCHAN - current channel in used - 8 - 5 - read-only - - - - - DMACfg - DMAC Configuration Register - 0x10 - 32 - 0x00000000 - 0xC3FFFFFF - - - CHAINXFR - Chain transfer -0x0: Chain transfer is not configured -0x1: Chain transfer is configured - 31 - 1 - read-only - - - REQSYNC - DMA request synchronization. -The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, -which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. -0x0: Request synchronization is not configured -0x1: Request synchronization is configured - 30 - 1 - read-only - - - DATAWIDTH - AXI bus data width -0x0: 32 bits -0x1: 64 bits -0x2: 128 bits -0x3: 256 bits - 24 - 2 - read-only - - - ADDRWIDTH - AXI bus address width -0x18: 24 bits -0x19: 25 bits -... -0x40: 64 bits -Others: Invalid - 17 - 7 - read-only - - - CORENUM - DMA core number -0x0: 1 core -0x1: 2 cores - 16 - 1 - read-only - - - BUSNUM - AXI bus interface number -0x0: 1 AXI bus -0x1: 2 AXI busses - 15 - 1 - read-only - - - REQNUM - Request/acknowledge pair number -0x0: 0 pair -0x1: 1 pair -0x2: 2 pairs -... -0x10: 16 pairs - 10 - 5 - read-only - - - FIFODEPTH - FIFO depth -0x4: 4 entries -0x8: 8 entries -0x10: 16 entries -0x20: 32 entries -Others: Invalid - 4 - 6 - read-only - - - CHANNELNUM - Channel number -0x1: 1 channel -0x2: 2 channels -... -0x8: 8 channels -Others: Invalid - 0 - 4 - read-only - - - - - DMACtrl - DMAC Control Register - 0x14 - 32 - 0x00000000 - 0x00000001 - - - RESET - Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. -Note: The software reset may cause the in-completion of AXI transaction. - 0 - 1 - write-only - - - - - ChAbort - Channel Abort Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHABORT - Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. -Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - 0 - 32 - write-only - - - - - INTHALFSTS - Harlf Complete Interrupt Status - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - half transfer done irq status - 0 - 32 - read-write - - - - - INTTCSTS - Trans Complete Interrupt Status Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. -0x0: Channel n has no terminal count status -0x1: Channel n has terminal count status - 0 - 32 - write-only - - - - - INTABORTSTS - Abort Interrupt Status Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. -0x0: Channel n has no abort status -0x1: Channel n has abort status - 0 - 32 - write-only - - - - - INTERRSTS - Error Interrupt Status Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - STS - The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: -- Bus error -- Unaligned address -- Unaligned transfer width -- Reserved configuration -0x0: Channel n has no error status -0x1: Channel n has error status - 0 - 32 - write-only - - - - - ChEN - Channel Enable Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CHEN - Alias of the Enable field of all ChnCtrl registers - 0 - 32 - read-only - - - - - 32 - 0x20 - ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,ch8,ch9,ch10,ch11,ch12,ch13,ch14,ch15,ch16,ch17,ch18,ch19,ch20,ch21,ch22,ch23,ch24,ch25,ch26,ch27,ch28,ch29,ch30,ch31 - CHCTRL[%s] - no description available - 0x40 - - Ctrl - Channel &index0 Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFF5DF - - - INFINITELOOP - set to loop current config infinitely - 31 - 1 - read-write - - - HANDSHAKEOPT - 0: one request to transfer one burst -1: one request to transfer all the data defined in ch_tts - 30 - 1 - read-write - - - PRIORITY - Channel priority level -0x0: Lower priority -0x1: Higher priority - 29 - 1 - read-write - - - BURSTOPT - set to change burst_size definition - 28 - 1 - read-write - - - SRCBURSTSIZE - Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. -The burst transfer byte number is (SrcBurstSize * SrcWidth). -0x0: 1 transfer -0x1: 2 transfers -0x2: 4 transfers -0x3: 8 transfers -0x4: 16 transfers -0x5: 32 transfers -0x6: 64 transfers -0x7: 128 transfers -0x8: 256 transfers -0x9:512 transfers -0xa: 1024 transfers -0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - 24 - 4 - read-write - - - SRCWIDTH - Source transfer width -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 21 - 3 - read-write - - - DSTWIDTH - Destination transfer width. -Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; -otherwise the error event will be triggered. -For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. -See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. -0x0: Byte transfer -0x1: Half-word transfer -0x2: Word transfer -0x3: Double word transfer -0x4: Quad word transfer -0x5: Eight word transfer -0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - 18 - 3 - read-write - - - SRCMODE - Source DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -Normal mode is enabled and started by software set Enable bit; -Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - 17 - 1 - read-write - - - DSTMODE - Destination DMA handshake mode -0x0: Normal mode -0x1: Handshake mode -the difference bewteen Source/Destination handshake mode is: -the dma block will response hardware request after read in Source handshake mode; -the dma block will response hardware request after write in Destination handshake mode; -NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - 16 - 1 - read-write - - - SRCADDRCTRL - Source address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 14 - 2 - read-write - - - DSTADDRCTRL - Destination address control -0x0: Increment address -0x1: Decrement address -0x2: Fixed address -0x3: Reserved, setting the field with this value triggers the error exception - 12 - 2 - read-write - - - SRC_FIXBURST - set to loop current burst, omit setting in src_addr_ctrl - 10 - 1 - read-write - - - DST_FIXBURST - set to loop current burst, omit setting in dst_addr_ctrl - 8 - 1 - read-write - - - SWAP_CTL - 00 ：use swap table(if swap table all 0, then act nothing) -01 : byte swap -10 : 16bit swap -11 : 32bit swap - 6 - 2 - read-write - - - INTHALFCNTMASK - Channel half interrupt mask -0x0: Allow the half interrupt to be triggered -0x1: Disable the half interrupt - 4 - 1 - read-write - - - INTABTMASK - Channel abort interrupt mask -0x0: Allow the abort interrupt to be triggered -0x1: Disable the abort interrupt - 3 - 1 - read-write - - - INTERRMASK - Channel error interrupt mask -0x0: Allow the error interrupt to be triggered -0x1: Disable the error interrupt - 2 - 1 - read-write - - - INTTCMASK - Channel terminal count interrupt mask -0x0: Allow the terminal count interrupt to be triggered -0x1: Disable the terminal count interrupt - 1 - 1 - read-write - - - ENABLE - Channel enable bit -0x0: Disable -0x1: Enable - 0 - 1 - read-write - - - - - TranSize - Channel &index0Transfer Size Register - 0x4 - 32 - 0x00000000 - 0x0FFFFFFF - - - TRANSIZE - Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. -If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - 0 - 28 - read-write - - - - - SrcAddr - Channel &index0 Source Address Low Part Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SRCADDRL - Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. -This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - 0 - 32 - read-write - - - - - ChanReqCtrl - Channel &index0 DMA Request Control Register - 0xc - 32 - 0x00000000 - 0x1F1F0000 - - - SRCREQSEL - Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - 24 - 5 - read-write - - - DSTREQSEL - Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - 16 - 5 - read-write - - - - - DstAddr - Channel &index0 Destination Address Low Part Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - DSTADDRL - Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. -This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - 0 - 32 - read-write - - - - - SwapTable - swap table register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - TABLE - "4bit for one byte, define how to swap, default is no swap. -For HDMA, support up to 4-byte, the register default value is 0x3210" - 0 - 32 - read-write - - - - - LLPointer - Channel &index0 Linked List Pointer Low Part Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFF8 - - - LLPOINTERL - Low part of the pointer to the next descriptor. The pointer must be double word aligned. - 3 - 29 - read-write - - - - - - - - XDMA - XDMA - DMAV2 - 0xf3100000 - - - PPI - PPI - PPI - 0xf00cc000 - - 0x0 - 0x800 - registers - - - - glb_cfg - glb_cfg - 0x0 - 32 - 0x00000000 - 0x00000003 - - - PAD_OUT_REG_ENJ - 0: register output, one cycle delay; -1: direct output， no delay but may have timing issue - 1 - 1 - read-write - - - SOFT_RESET - software reset - 0 - 1 - read-write - - - - - pad_cfg - pad_cfg - 0x4 - 32 - 0x0F000000 - 0x0F0FFFFF - - - CS_IDLE_ST - cs pin idle state, default high for active low - 24 - 4 - read-write - - - DM_PAD_POL - dm pin polarity - 16 - 4 - read-write - - - CTRL_PAD_OE - the pad output enable signal. 0 for IN; 1 for OUT. -NOTE: for unused pads, set both ctrl_pad_oe and ctrl_pad_pol to 0 - 8 - 8 - read-write - - - CTRL_PAD_POL - for OUT pad: -0: output the value in cmd -1: output reversed value in cmd -for IN pad, defines the signal active value, when ctrl_cfg.io_cfg is set, -will wait the active value for ready(generally read or write ready) - 0 - 8 - read-write - - - - - clkpin_cfg - clkpin_cfg - 0x14 - 32 - 0x00000000 - 0x0F0F0F23 - - - CYCLE - there will be a system counter run from 0 to cycle, -clk output will be set to high when counter is clk_high, and low when counter is clk_low. -The output will be system clock if cycle is 0. -All 4 CS share same clock configuration(one clock pin with configured frequency). -different CS can be assert at different counter value. - 24 - 4 - read-write - - - HIGH - clock high numer - 16 - 4 - read-write - - - LOW - clock low number - 8 - 4 - read-write - - - INVERT - set to invert clock output - 5 - 1 - read-write - - - AON - 0: use clk_gate in cmd sequence for whether output clock -1: always enable clock output; - 1 - 1 - read-write - - - EN - set to enable clock logic - 0 - 1 - read-write - - - - - tm_cfg - tm_cfg - 0x18 - 32 - 0x00000000 - 0x00010FFF - - - TM_EN - timeout enable. -if enabled, then if each AHB transfer time exceed tm_cfg clock cycles, will assert irq - 16 - 1 - read-write - - - TM_CFG - timeout value, max 20us at 200MHz clock - 0 - 12 - read-write - - - - - irq_sts - irq_sts - 0x20 - 32 - 0x00000000 - 0x00000001 - - - IRQ_TMOUT_STS - tiemout interrupt status, write 1 to clear - 0 - 1 - read-write - - - - - irq_en - irq_en - 0x24 - 32 - 0x00000000 - 0x00000001 - - - IRQ_TMOUT_EN - timeout interrupt enable - 0 - 1 - read-write - - - - - 4 - 0x20 - 0,1,2,3 - CS[%s] - no description available - 0x40 - - cfg0 - cfg0 - 0x0 - 32 - 0x00000000 - 0x0FFF0FFF - - - ADDR_END - No description available - 16 - 12 - read-write - - - ADDR_START - addr_start and addr_end config the address slot for CS0, use high 12bit, -the minimun slot is 1Mbyte(addr_start==addr_end) - 0 - 12 - read-write - - - - - cfg1 - cfg1 - 0x4 - 32 - 0xFFFF0000 - 0xFFFF000F - - - ADDR_MASK - the high AHB address will AND with {cs0_mask[15:0], 16'hFFFF}, -shift right with addr_shift, then output as real address. - 16 - 16 - read-write - - - ADDR_SHIFT - gennerally should be configured according to port size, -0 for 8bit; 1 for 16bit; 2 for 32bit; - 0 - 4 - read-write - - - - - cfg2 - cfg2 - 0x8 - 32 - 0x00000000 - 0x10F010F7 - - - CS_SYNC_EN - set to enable CS pin sync with clock counter. -Clr if use async mode(no clk pin), or not care the CS start time with clk pin - 28 - 1 - read-write - - - SYNC_CLK_SEL - CS assert at when clk_div_cnt equal to sync_clk_sel - 20 - 4 - read-write - - - READY_IN_SEL - 0: use two stage sync; -1: use one stage sync - 12 - 1 - read-write - - - INTER_CMD_DLY - set to none-zero value, will add delay between each command sequence for burst cmd, -or splited transfer cmd sequence(such as transfer 32bit on 16bit port), -CS will be de-assert during the delay. - 4 - 4 - read-write - - - PORT_SIZE - 00-8bit; 01-16bit; 10-32bit; 11-reserved - 1 - 2 - read-write - - - ENABLE - CS enable - 0 - 1 - read-write - - - - - cfg3 - cfg3 - 0xc - 32 - 0x00000000 - 0x3F3F3F3F - - - RCMD_END1 - sequential read cmd end index - 24 - 6 - read-write - - - RCMD_START1 - sequential read cmd start index - 16 - 6 - read-write - - - RCMD_END0 - first read cmd end index - 8 - 6 - read-write - - - RCMD_START0 - first read cmd start index - 0 - 6 - read-write - - - - - cfg4 - cfg4 - 0x10 - 32 - 0x3F3F3F3F - 0x3F3F3F3F - - - WCMD_END1 - sequential write cmd end index - 24 - 6 - read-write - - - WCMD_START1 - sequential write cmd start index - 16 - 6 - read-write - - - WCMD_END0 - first write cmd end index - 8 - 6 - read-write - - - WCMD_START0 - first write cmd start index - 0 - 6 - read-write - - - - - - 64 - 0x10 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,rsv60,61,62,63 - CMD[%s] - no description available - 0x400 - - cmd_cfg - cmd_cfg - 0x0 - 32 - 0x00000000 - 0x000300FF - - - CS_VAL - cs value in current cmd - 17 - 1 - read-write - - - CLK_GATE - the clock gate enable signal, set to output clock signal - 16 - 1 - read-write - - - CYCLE_NUM - cmd clock cycles - 0 - 8 - read-write - - - - - ad_cfg - ad_cfg - 0x4 - 32 - 0x00000000 - 0x0000FFFF - - - DIR3 - No description available - 15 - 1 - read-write - - - AD_SEL3 - No description available - 14 - 1 - read-write - - - BYTE_SEL3 - No description available - 12 - 2 - read-write - - - DIR2 - No description available - 11 - 1 - read-write - - - AD_SEL2 - No description available - 10 - 1 - read-write - - - BYTE_SEL2 - No description available - 8 - 2 - read-write - - - DIR1 - No description available - 7 - 1 - read-write - - - AD_SEL1 - No description available - 6 - 1 - read-write - - - BYTE_SEL1 - No description available - 4 - 2 - read-write - - - DIR0 - 0 for OUT; 1 for IN - 3 - 1 - read-write - - - AD_SEL0 - 0 for data; 1 for address. - 2 - 1 - read-write - - - BYTE_SEL0 - select one of the 4 bytes(11 for 31:24, 10 for 23:16, 01 for 15:8, 00 for 7:0) - 0 - 2 - read-write - - - - - ctrl_cfg - ctrl_cfg - 0x8 - 32 - 0x00000000 - 0x11111111 - - - IO_CFG7 - No description available - 28 - 1 - read-write - - - IO_CFG6 - No description available - 24 - 1 - read-write - - - IO_CFG5 - No description available - 20 - 1 - read-write - - - IO_CFG4 - No description available - 16 - 1 - read-write - - - IO_CFG3 - No description available - 12 - 1 - read-write - - - IO_CFG2 - No description available - 8 - 1 - read-write - - - IO_CFG1 - No description available - 4 - 1 - read-write - - - IO_CFG0 - for OUT, it defines the output value(0 or 1); -for IN, it defines whether to wait for ready(ready polarity is defined in ctrl_pad_pol) - 0 - 1 - read-write - - - - - - - - GPIOM - GPIOM - GPIOM - 0xf00d8000 - - 0x0 - 0x800 - registers - - - - 16 - 0x80 - gpioa,gpiob,gpioc,gpiod,gpioe,gpiof,rsv6,rsv7,rsv8,rsv9,rsv10,rsv11,rsv12,rsv13,gpioy,gpioz - ASSIGN[%s] - no description available - 0x0 - - 32 - 0x4 - PIN00,PIN01,PIN02,PIN03,PIN04,PIN05,PIN06,PIN07,PIN08,PIN09,PIN10,PIN11,PIN12,PIN13,PIN14,PIN15,PIN16,PIN17,PIN18,PIN19,PIN20,PIN21,PIN22,PIN23,PIN24,PIN25,PIN26,PIN27,PIN28,PIN29,PIN30,PIN31 - PIN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x80000F03 - - - LOCK - lock fields in this register, lock can only be cleared by soc reset -0: fields can be changed -1: fields locked to current value, not changeable - 31 - 1 - read-write - - - HIDE - pin value visibility to gpios, -bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 -bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 -bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio -bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - 8 - 4 - read-write - - - SELECT - select which gpio controls chip pin, -0: soc gpio0; -1: soc gpio1; -2: cpu0 fastgpio -3: cpu1 fast gpio - 0 - 2 - read-write - - - - - - - - LOBS - LOBS - LOBS - 0xf00dc000 - - 0x0 - 0xfb4 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xC0000001 - - - RUN - Run control. -0 LOBS disabled. Register programming permitted. -1 LOBS enabled - 0 - 1 - read-write - - - - - STREAMCTRL - Stream Control Register - 0xc - 32 - 0x00000027 - 0xFFFF81FF - - - SEL - Signal Group Select -0 128bit from one group -1 from 2 groups, 4bit in each group - 8 - 1 - read-write - - - FULL_CLEAR - FIFO Overflow Clear - 7 - 1 - read-write - - - SAMPLE - Sample Rate -4 take one every 5 -5 take one every 6 -6 take one every 7 - 3 - 4 - read-write - - - BURST - Burst Cfg -3b011 Incr4 -3b101 Incr8 -3b111 Incr16 - 0 - 3 - read-write - - - - - PTACTION - Pre-trigger Action Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRACE - Enables trace - 3 - 1 - read-write - - - - - STARTADDR - Start Address Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Start address - 0 - 32 - read-write - - - - - ENDADDR - End Address Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - End address - 0 - 32 - read-write - - - - - CTSR - Current Trigger State Register - 0x20 - 32 - 0x00000001 - 0xFFFFFFFF - - - FINALSTATE - 0 LOBS is still tracing. -1 Indicates that the LOBS has stopped advancing Trigger States and stopped trace. -FINALSTATE can be set by TRIGCTRL.COUNTBRK reaching the final loop count, or by programming NEXTSTATEto zero - 31 - 1 - read-only - - - CTSR - Reads current Trigger State. This is a one-hot encoded field. -When CTRL.RUN: -0 RAZ. -1 Returns current Trigger State. -If FINALSTATE is 1, then the CTSR field gives the Trigger State when FINALSTATE became 1 - 0 - 5 - read-only - - - - - CCVR - Current Counter Value Register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - CCVR - Returns the counter value when the CTSR was last read. If the CTSR has never been read, then the value in the CCVR is undefined - 0 - 32 - read-only - - - - - CAVR - Current Action Value Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRACE - Trace active. -0b0 Trace is not active. -0b1 Trace is active. - 3 - 1 - read-only - - - - - FIFOSTATE - Fifo State Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - FULL - FIFO full - 1 - 1 - read-only - - - EMPTY - FIFO empty - 0 - 1 - read-only - - - - - FINALADDR - Final Address Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Final address - 0 - 32 - read-write - - - - - GRPSELA - Group Select Register - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - NUM2 - Select sample group number2 - 4 - 4 - read-write - - - NUM1 - Select sample group number1 - 0 - 4 - read-write - - - - - GRPENA - Group Enable Register - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN2 - Enable sample group number2 - 1 - 1 - read-write - - - EN1 - Enable sample group number1 - 0 - 1 - read-write - - - - - SIGSELA1 - Signal Select1 Register - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - NUM4 - Select sample signal bit number4 in first group - 24 - 8 - read-write - - - NUM3 - Select sample signal bit number3 in first group - 16 - 8 - read-write - - - NUM2 - Select sample signal bit number2 in first group - 8 - 8 - read-write - - - NUM1 - Select sample signal bit number1 in first group - 0 - 8 - read-write - - - - - SIGSELA2 - Signal Select2 Register - 0x60 - 32 - 0x00000000 - 0xFFFFFFFF - - - NUM4 - Select sample signal bit number4 in second group - 24 - 8 - read-write - - - NUM3 - Select sample signal bit number3 in second group - 16 - 8 - read-write - - - NUM2 - Select sample signal bit number2 in second group - 8 - 8 - read-write - - - NUM1 - Select sample signal bit number1 in second group - 0 - 8 - read-write - - - - - SIGENA - Signal Enable Register - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN2 - Enable sample signal number2 - 4 - 4 - read-write - - - EN1 - Enable sample signal number1 - 0 - 4 - read-write - - - - - 5 - 0x100 - 0,1,2,3,4 - STATE[%s] - no description available - 0x100 - - SIGSEL - Signal Select Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Selects Signal Group. -0x1 Selects Signal Group 0. -0x2 Selects Signal Group 1. -0x4 Selects Signal Group 2. -0x8 Selects Signal Group 3. -0x10 Selects Signal Group 4. -0x20 Selects Signal Group 5. -0x40 Selects Signal Group 6. -0x80 Selects Signal Group 7. -0x100 Selects Signal Group 8. -0x200 Selects Signal Group 9. -0x400 Selects Signal Group 10. -0x800 Selects Signal Group 11. - 0 - 12 - read-write - - - - - TRIGCTRL - Trigger Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFCCF - - - TRACE - Trace capture control. -0b10 Trace is captured every ELACLK cycle. -others Reserved. - 6 - 2 - read-write - - - COMPSEL - Comparison mode. Acts as both a counter enable and a select for the comparison mode. -0b0 Disable counters and select Trigger Signal Comparison mode. -0b1 Enable counters and select Trigger Counter Comparison mode. - 3 - 1 - read-write - - - COMP - Trigger Signal Comparison type select. -0b000 Trigger Signal Comparisons disabled. The enabled counters count clocks immediately after the Trigger State has been entered and generate a programmable Output Action and transition to the next Trigger State when the Counter Compare Register count is reached, that is when a Trigger Counter Comparison match occurs. -0b001 Compare type is equal (==). -0b010 Compare type is greater than (>). -0b011 Compare type is greater than or equal (>=). -0b101 Compare type is not equal (!=). -0b110 Compare type is less than (<). -0b111 Compare type is less than or equal (<=). - 0 - 3 - read-write - - - - - NEXTSTATE - Next State Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - NEXTSTATE - Selects the next state to move to after the Trigger Condition has been met in the current state. -0x0 Do not change state. This is the final Trigger State. -0x1 Selects Trigger State 0. -0x2 Selects Trigger State 1. -0x4 Selects Trigger State 2. -0x8 Selects Trigger State 3. -0x10 Selects Trigger State 4. - 0 - 5 - read-write - - - - - ACTION - Action Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TRACE - Trace active. -0b0 Trace disable. -0b1 Trace enable. - 3 - 1 - read-write - - - - - COUNTCOMP - Counter Compare Register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - A value that, when reached in the associated up-counter for this Trigger State, causes a Trigger Counter Comparison match to occur. - 0 - 32 - read-write - - - - - EXTMASK - External Mask Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - External Mask - 0 - 32 - read-write - - - - - EXTCOMP - External Compare Register - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - External Compare - 0 - 32 - read-write - - - - - SIGMASK - Signal Mask Register - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - NUM3 - Select compare signal number3 - 24 - 8 - read-write - - - NUM2 - Select compare signal number2 - 16 - 8 - read-write - - - NUM1 - Select compare signal number1 - 8 - 8 - read-write - - - NUM0 - Select compare signal number0 - 0 - 8 - read-write - - - - - COMPEN - Compare Enable register - 0x44 - 32 - 0x00000000 - 0x0000000F - - - EN - Select compare signal number0-3 - 0 - 4 - read-write - - - - - SIGCOMP0 - Signal Compare Register0 - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE0 - Compare golden value for Signal Group signals[31:0]. - 0 - 32 - read-write - - - - - SIGCOMP1 - Signal Compare Register1 - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE1 - Compare golden value for Signal Group signals[63:32]. - 0 - 32 - read-write - - - - - SIGCOMP2 - Signal Compare Register2 - 0x88 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE2 - Compare golden value for Signal Group signals[95:64]. - 0 - 32 - read-write - - - - - SIGCOMP3 - Signal Compare Register3 - 0x8c - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE3 - Compare golden value for Signal Group signals[127:96]. - 0 - 32 - read-write - - - - - - LAR - Lock Access Register - 0xfb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Lock Access Value - 0 - 32 - read-write - - - - - - - ADC0 - ADC0 - ADC16 - 0xf0100000 - - 0x0 - 0x1464 - registers - - - - 12 - 0x4 - trg0a,trg0b,trg0c,trg1a,trg1b,trg1c,trg2a,trg2b,trg2c,trg3a,trg3b,trg3c - CONFIG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF3F3F7F - - - TRIG_LEN - length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - 30 - 2 - write-only - - - INTEN3 - interrupt enable for 4th conversion - 29 - 1 - read-write - - - CHAN3 - channel number for 4th conversion - 24 - 5 - read-write - - - INTEN2 - interrupt enable for 3rd conversion - 21 - 1 - read-write - - - CHAN2 - channel number for 3rd conversion - 16 - 5 - read-write - - - INTEN1 - interrupt enable for 2nd conversion - 13 - 1 - read-write - - - CHAN1 - channel number for 2nd conversion - 8 - 5 - read-write - - - QUEUE_EN - preemption queue enable control - 6 - 1 - read-write - - - INTEN0 - interrupt enable for 1st conversion - 5 - 1 - read-write - - - CHAN0 - channel number for 1st conversion - 0 - 5 - read-write - - - - - trg_dma_addr - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFC - - - TRG_DMA_ADDR - buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - 2 - 30 - read-write - - - - - trg_sw_sta - No description available - 0x34 - 32 - 0x00000000 - 0x0000001F - - - TRG_SW_STA - SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - 4 - 1 - read-write - - - TRIG_SW_INDEX - which trigger for the SW trigger -0 for trig0a, 1 for trig0b… -3 for trig1a, …11 for trig3c - 0 - 4 - read-write - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - BUS_RESULT[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x0001FFFF - - - VALID - set after conversion finished if wait_dis is set, cleared after software read. -The first time read with 0 will trigger one new conversion. -If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. -the result may not realtime if software read once and wait long time to read again - 16 - 1 - read-only - - - CHAN_RESULT - read this register will trigger one adc conversion. -If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result -If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - 0 - 16 - read-only - - - - - buf_cfg0 - No description available - 0x500 - 32 - 0x00000000 - 0x00000003 - - - BUS_MODE_EN - bus mode enable - 1 - 1 - read-write - - - WAIT_DIS - set to disable read waiting, get result immediately but maybe not current conversion result. - 0 - 1 - read-write - - - - - seq_cfg0 - No description available - 0x800 - 32 - 0x00000000 - 0x80000F1F - - - CYCLE - current dma write cycle bit - 31 - 1 - read-only - - - SEQ_LEN - sequence queue length, 0 for one, 0xF for 16 - 8 - 4 - read-write - - - RESTART_EN - if set together with cont_en, HW will continue process the whole queue after trigger once. -If cont_en is 0, this bit is not used - 4 - 1 - read-write - - - CONT_EN - if set, HW will continue process the queue till end(seq_len) after trigger once - 3 - 1 - read-write - - - SW_TRIG - SW trigger, pulse signal, cleared by HW one cycle later - 2 - 1 - write-only - - - SW_TRIG_EN - set to enable SW trigger - 1 - 1 - read-write - - - HW_TRIG_EN - set to enable external HW trigger, only trigger on posedge - 0 - 1 - read-write - - - - - seq_dma_addr - No description available - 0x804 - 32 - 0x00000000 - 0xFFFFFFFC - - - TAR_ADDR - dma target address, should be 4-byte aligned - 2 - 30 - read-write - - - - - seq_wr_addr - No description available - 0x808 - 32 - 0x00000000 - 0x00FFFFFF - - - SEQ_WR_POINTER - HW update this field after each dma write, it indicate the next dma write pointer. -dma write address is (tar_addr+seq_wr_pointer)*4 - 0 - 24 - read-only - - - - - seq_dma_cfg - No description available - 0x80c - 32 - 0x00000000 - 0x0FFF3FFF - - - STOP_POS - if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - 16 - 12 - read-write - - - DMA_RST - set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. -SW should clear all cycle bit in buffer to 0 before clear dma_rst - 13 - 1 - read-write - - - STOP_EN - set to stop dma if reach the stop_pos - 12 - 1 - read-write - - - BUF_LEN - dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 -0 for 4byte; -0xFFF for 16kbyte. - 0 - 12 - read-write - - - - - 16 - 0x4 - cfg0,cfg1,cfg2,cfg3,cfg4,cfg5,cfg6,cfg7,cfg8,cfg9,cfg10,cfg11,cfg12,cfg13,cfg14,cfg15 - SEQ_QUE[%s] - no description available - 0x810 - 32 - 0x00000000 - 0x0000003F - - - SEQ_INT_EN - interrupt enable for current conversion - 5 - 1 - read-write - - - CHAN_NUM_4_0 - channel number for current conversion - 0 - 5 - read-write - - - - - seq_high_cfg - No description available - 0x850 - 32 - 0x00000000 - 0x00FFFFFF - - - STOP_POS_HIGH - No description available - 12 - 12 - read-write - - - BUF_LEN_HIGH - No description available - 0 - 12 - read-write - - - - - 16 - 0x10 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - PRD_CFG[%s] - no description available - 0xc00 - - prd_cfg - No description available - 0x0 - 32 - 0x00000000 - 0x00001FFF - - - PRESCALE - 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - 8 - 5 - read-write - - - PRD - conver period, with prescale. -Set to 0 means disable current channel - 0 - 8 - read-write - - - - - prd_thshd_cfg - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - THSHDH - threshold high, assert interrupt(if enabled) if result exceed high or low. - 16 - 16 - read-write - - - THSHDL - threshold low - 0 - 16 - read-write - - - - - prd_result - No description available - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - CHAN_RESULT - adc convert result, update after each valid conversion. -it may be updated period according to config, also may be updated due to other queue convert the same channel - 0 - 16 - read-only - - - - - - 16 - 0x4 - chn0,chn1,chn2,chn3,chn4,chn5,chn6,chn7,chn8,chn9,chn10,chn11,chn12,chn13,chn14,chn15 - SAMPLE_CFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x00000FFF - - - SAMPLE_CLOCK_NUMBER_SHIFT - shift for sample clock number - 9 - 3 - read-write - - - SAMPLE_CLOCK_NUMBER - sample clock number, base on clock_period, default one period - 0 - 9 - read-write - - - - - conv_cfg1 - No description available - 0x1104 - 32 - 0x00000000 - 0x000001FF - - - CONVERT_CLOCK_NUMBER - convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); -user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. -Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - 4 - 5 - read-write - - - CLOCK_DIVIDER - clock_period, N half clock cycle per half adc cycle -0 for same adc_clk and bus_clk, -1 for 1:2, -2 for 1:3, -... -15 for 1:16 -Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - 0 - 4 - read-write - - - - - adc_cfg0 - No description available - 0x1108 - 32 - 0x00000000 - 0xA0000001 - - - SEL_SYNC_AHB - set to 1 will enable sync AHB bus, to get better bus performance. -Adc_clk must to be set to same as bus clock at this mode - 31 - 1 - read-write - - - ADC_AHB_EN - set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - 29 - 1 - read-write - - - PORT3_REALTIME - set to enable trg queue stop other queues - 0 - 1 - read-write - - - - - int_sts - No description available - 0x1110 - 32 - 0x00000000 - 0xFFF0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - STOP_POS - No description available - 20 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - int_en - No description available - 0x1114 - 32 - 0x00000000 - 0xFFF0FFFF - - - TRIG_CMPT - interrupt for one trigger conversion complete if enabled - 31 - 1 - read-write - - - TRIG_SW_CFLCT - No description available - 30 - 1 - read-write - - - TRIG_HW_CFLCT - No description available - 29 - 1 - read-write - - - READ_CFLCT - read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - 28 - 1 - read-write - - - SEQ_SW_CFLCT - sequence queue conflict interrupt, set if HW or SW trigger received during conversion - 27 - 1 - read-write - - - SEQ_HW_CFLCT - No description available - 26 - 1 - read-write - - - SEQ_DMAABT - dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - 25 - 1 - read-write - - - SEQ_CMPT - the whole sequence complete interrupt - 24 - 1 - read-write - - - SEQ_CVC - one conversion complete in seq_queue if related seq_int_en is set - 23 - 1 - read-write - - - DMA_FIFO_FULL - DMA fifo full interrupt, user need to check clock frequency if it's set. - 22 - 1 - read-write - - - AHB_ERR - set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - 21 - 1 - read-write - - - STOP_POS - No description available - 20 - 1 - read-write - - - WDOG - set if one chanel watch dog event triggered - 0 - 16 - read-write - - - - - trigmux_en - No description available - 0x1118 - 32 - 0x00000000 - 0x0190FFFF - - - SEQ_CMPT - No description available - 24 - 1 - read-write - - - SEQ_CVC - No description available - 23 - 1 - read-write - - - STOP_POS - No description available - 20 - 1 - read-write - - - WDOG - No description available - 0 - 16 - read-write - - - - - trg_cmpt_flag - No description available - 0x111c - 32 - 0x00000000 - 0x00000FFF - - - TRG_CMPT_FLAG - No description available - 0 - 12 - read-write - - - - - ana_ctrl0 - No description available - 0x1200 - 32 - 0x00000000 - 0x80001004 - - - MOTO_EN - "set to enable moto_soc and moto_valid. -Should use AHB clock for adc, this bit can be used avoid async output" - 31 - 1 - read-write - - - ADC_CLK_ON - set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. -MUST set clock_period to 0 or 1 for adc16 reg access - 12 - 1 - read-write - - - STARTCAL - set to start the offset calibration cycle (Active H). user need to clear it after setting it. - 2 - 1 - read-write - - - - - ana_status - No description available - 0x1210 - 32 - 0x00000000 - 0x00000080 - - - CALON - Indicates if the ADC is in calibration mode (Active H). - 7 - 1 - read-write - - - - - 34 - 0x2 - adc16_para00,adc16_para01,adc16_para02,adc16_para03,adc16_para04,adc16_para05,adc16_para06,adc16_para07,adc16_para08,adc16_para09,adc16_para10,adc16_para11,adc16_para12,adc16_para13,adc16_para14,adc16_para15,adc16_para16,adc16_para17,adc16_para18,adc16_para19,adc16_para20,adc16_para21,adc16_para22,adc16_para23,adc16_para24,adc16_para25,adc16_para26,adc16_para27,adc16_para28,adc16_para29,adc16_para30,adc16_para31,adc16_para32,adc16_para33 - ADC16_PARAMS[%s] - no description available - 0x1400 - 16 - 0x0000 - 0xFFFF - - - PARAM_VAL - No description available - 0 - 16 - read-write - - - - - adc16_config0 - No description available - 0x1444 - 32 - 0x00000000 - 0x01F07FFF - - - REG_EN - set to enable regulator - 24 - 1 - read-write - - - BANDGAP_EN - set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - 23 - 1 - read-write - - - CAL_AVG_CFG - for average the calibration result. -0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; -4- 16 loops; 5-32 loops; others reserved - 20 - 3 - read-write - - - PREEMPT_EN - set to enable preemption feature - 14 - 1 - read-write - - - CONV_PARAM - conversion parameter - 0 - 14 - read-write - - - - - adc16_config1 - No description available - 0x1460 - 32 - 0x00000000 - 0x00001F00 - - - COV_END_CNT - used for faster conversion, user can change it to get higher convert speed(but less accuracy). -should set to (21-convert_clock_number+1). - 8 - 5 - read-write - - - - - - - ADC1 - ADC1 - ADC16 - 0xf0104000 - - - ADC2 - ADC2 - ADC16 - 0xf0108000 - - - ADC3 - ADC3 - ADC16 - 0xf010c000 - - - ACMP0 - ACMP0 - ACMP - 0xf0130000 - - 0x0 - 0x40 - registers - - - - 2 - 0x20 - chn0,chn1 - CHANNEL[%s] - no description available - 0x0 - - cfg - Configure Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - HYST - This bitfield configure the comparator hysteresis. -00: Hysteresis level 0 -01: Hysteresis level 1 -10: Hysteresis level 2 -11: Hysteresis level 3 - 30 - 2 - read-write - - - DACEN - This bit enable the comparator internal DAC -0: DAC disabled -1: DAC enabled - 29 - 1 - read-write - - - HPMODE - This bit enable the comparator high performance mode. -0: HP mode disabled -1: HP mode enabled - 28 - 1 - read-write - - - CMPEN - This bit enable the comparator. -0: ACMP disabled -1: ACMP enabled - 27 - 1 - read-write - - - MINSEL - PIN select, from pad_ai_acmp[7:1] and dac_out - 24 - 3 - read-write - - - DAC_TRIG_EN - if set, the dac value is from moto system when valid -if clr, use dac_cfg value - 23 - 1 - read-write - - - PINSEL - MIN select, from pad_ai_acmp[7:1] and dac_out - 20 - 3 - read-write - - - CMPOEN - This bit enable the comparator output on pad. -0: ACMP output disabled -1: ACMP output enabled - 19 - 1 - read-write - - - FLTBYPS - This bit bypass the comparator output digital filter. -0: The ACMP output need pass digital filter -1: The ACMP output digital filter is bypassed. - 18 - 1 - read-write - - - WINEN - This bit enable the comparator window mode. -0: Window mode is disabled -1: Window mode is enabled - 17 - 1 - read-write - - - OPOL - The output polarity control bit. -0: The ACMP output remain un-changed. -1: The ACMP output is inverted. - 16 - 1 - read-write - - - FLTMODE - This bitfield define the ACMP output digital filter mode: -000-bypass -100-change immediately; -101-change after filter; -110-stalbe low; -111-stable high - 13 - 3 - read-write - - - SYNCEN - This bit enable the comparator output synchronization. -0: ACMP output not synchronized with ACMP clock. -1: ACMP output synchronized with ACMP clock. - 12 - 1 - read-write - - - FLTLEN - This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - 0 - 12 - read-write - - - - - daccfg - DAC configure register - 0x4 - 32 - 0x00000000 - 0x000000FF - - - DACCFG - 8bit DAC digital value output to analog block - 0 - 8 - read-write - - - - - sr - Status register - 0x10 - 32 - 0x00000000 - 0x00000003 - - - FEDGF - Output falling edge flag. Write 1 to clear this flag. - 1 - 1 - read-write - - - REDGF - Output rising edge flag. Write 1 to clear this flag. - 0 - 1 - read-write - - - - - irqen - Interrupt request enable register - 0x14 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag interrupt enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag interrupt enable bit. - 0 - 1 - read-write - - - - - dmaen - DMA request enable register - 0x18 - 32 - 0x00000000 - 0x00000003 - - - FEDGEN - Output falling edge flag DMA request enable bit. - 1 - 1 - read-write - - - REDGEN - Output rising edge flag DMA request enable bit. - 0 - 1 - read-write - - - - - - - - ACMP1 - ACMP1 - ACMP - 0xf0134000 - - - ACMP2 - ACMP2 - ACMP - 0xf0138000 - - - ACMP3 - ACMP3 - ACMP - 0xf013c000 - - - I2S0 - I2S0 - I2S - 0xf0140000 - - 0x0 - 0x80 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST_RX - software reset the RX module if asserted to be 1'b1. Self-clear. - 18 - 1 - read-write - - - SFTRST_TX - software reset the TX module if asserted to be 1'b1. Self-clear. - 17 - 1 - read-write - - - SFTRST_CLKGEN - software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - 16 - 1 - read-write - - - TXDNIE - TX buffer data needed interrupt enable -0: TXE interrupt masked -1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - 15 - 1 - read-write - - - RXDAIE - RX buffer data available interrupt enable -0: RXNE interrupt masked -1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - 14 - 1 - read-write - - - ERRIE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 13 - 1 - read-write - - - TX_DMA_EN - Asserted to use DMA, else to use interrupt - 12 - 1 - read-write - - - RX_DMA_EN - Asserted to use DMA, else to use interrupt - 11 - 1 - read-write - - - TXFIFOCLR - Self-clear - 10 - 1 - read-write - - - RXFIFOCLR - Self-clear - 9 - 1 - read-write - - - TX_EN - enable for each TX data pad - 5 - 4 - read-write - - - RX_EN - enable for each RX data pad - 1 - 4 - read-write - - - I2S_EN - enable for the module - 0 - 1 - read-write - - - - - RFIFO_FILLINGS - Rx FIFO Filling Level - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX3 - RX3 fifo fillings - 24 - 8 - read-only - - - RX2 - RX2 fifo fillings - 16 - 8 - read-only - - - RX1 - RX1 fifo fillings - 8 - 8 - read-only - - - RX0 - RX0 fifo fillings - 0 - 8 - read-only - - - - - TFIFO_FILLINGS - Tx FIFO Filling Level - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX3 - TX3 fifo fillings - 24 - 8 - read-only - - - TX2 - TX2 fifo fillings - 16 - 8 - read-only - - - TX1 - TX1 fifo fillings - 8 - 8 - read-only - - - TX0 - TX0 fifo fillings - 0 - 8 - read-only - - - - - FIFO_THRESH - TX/RX FIFO Threshold setting. - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TX - TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - 8 - 8 - read-write - - - RX - RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - 0 - 8 - read-write - - - - - STA - Status Registers - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_UD - Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - 13 - 4 - write-only - - - RX_OV - Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - 9 - 4 - write-only - - - TX_DN - Asserted when tx fifo data are needed. - 5 - 4 - read-only - - - RX_DA - Asserted when rx fifo data are available. - 1 - 4 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXD[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - read-only - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXD[%s] - no description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - D - No description available - 0 - 32 - write-only - - - - - CFGR - Configruation Regsiters - 0x50 - 32 - 0x40000000 - 0xFFFFFFFF - - - BCLK_GATEOFF - Gate off the bclk. Asserted to gate-off the BCLK. - 30 - 1 - read-write - - - BCLK_DIV - Linear prescaler to generate BCLK from MCLK. -BCLK_DIV [8:0] = 0: BCLK=No CLK. -BCLK_DIV [8:0] = 1: BCLK=MCLK/1 -BCLK_DIV [8:0] = n: BCLK=MCLK/(n). -Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 21 - 9 - read-write - - - INV_BCLK_OUT - Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - 20 - 1 - read-write - - - INV_BCLK_IN - Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - 19 - 1 - read-write - - - INV_FCLK_OUT - Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - 18 - 1 - read-write - - - INV_FCLK_IN - Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - 17 - 1 - read-write - - - INV_MCLK_OUT - Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - 16 - 1 - read-write - - - INV_MCLK_IN - Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - 15 - 1 - read-write - - - BCLK_SEL_OP - asserted to use external clk source - 14 - 1 - read-write - - - FCLK_SEL_OP - asserted to use external clk source - 13 - 1 - read-write - - - MCK_SEL_OP - asserted to use external clk source - 12 - 1 - read-write - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -5'h2: 2 channels -5'h4: 4 channels -... -5‘h10: 16 channels (max) - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - MISC_CFGR - Misc configuration Registers - 0x58 - 32 - 0x00042000 - 0xFFFFEC01 - - - MCLK_GATEOFF - Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - 13 - 1 - read-write - - - MCLKOE - Master clock output to pad enable -0: Master clock output is disabled -1: Master clock output is enabled -Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - 0 - 1 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - RXDSLOT[%s] - no description available - 0x60 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - 4 - 0x4 - DATA0,DATA1,DATA2,DATA3 - TXDSLOT[%s] - no description available - 0x70 - 32 - 0x0000FFFF - 0x0000FFFF - - - EN - No description available - 0 - 16 - read-write - - - - - - - I2S1 - I2S1 - I2S - 0xf0144000 - - - DAO - DAO - DAO - 0xf0150000 - - 0x0 - 0x1c - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x000200FF - - - HPF_EN - Whether HPF is enabled. This HPF is used to filter out the DC part. - 17 - 1 - read-write - - - MONO - Asserted to let the left and right channel output the same value. - 7 - 1 - read-write - - - RIGHT_EN - Asserted to enable the right channel - 6 - 1 - read-write - - - LEFT_EN - Asserted to enable the left channel - 5 - 1 - read-write - - - REMAP - 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative -0: Don't use remap pwm version - 4 - 1 - read-write - - - INVERT - all the outputs are inverted before sending to pad - 3 - 1 - read-write - - - FALSE_LEVEL - the pad output in False run mode, or when the module is disabled -0: all low -1: all high -2: P-high, N-low -3. output is not enabled - 1 - 2 - read-write - - - FALSE_RUN - the module continues to consume data, but all the pads are constant, thus no audio out - 0 - 1 - read-write - - - - - CMD - Command Register - 0x8 - 32 - 0x00000000 - 0x00000003 - - - SFTRST - Self-clear - 1 - 1 - read-write - - - RUN - Enable this module to run. - 0 - 1 - read-write - - - - - RX_CFGR - Configuration Register - 0xc - 32 - 0x00000000 - 0x00000FFF - - - FRAME_EDGE - The start edge of a frame -0: Falling edge indicates a new frame (Just like standard I2S Philips standard) -1: Rising edge indicates a new frame - 11 - 1 - read-write - - - CH_MAX - CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. -It must be an even number, so CH_MAX[0] is always 0. -4'h2: 2 channels -4'h4: 4 channels -etc - 6 - 5 - read-write - - - TDM_EN - TDM mode -0: not TDM mode -1: TDM mode - 5 - 1 - read-write - - - STD - I2S standard selection -00: I2S Philips standard. -01: MSB justified standard (left justified) -10: LSB justified standard (right justified) -11: PCM standard -For more details on I2S standards. -Note: For correct operation, these bits should be configured when the I2S is disabled. - 3 - 2 - read-write - - - DATSIZ - Data length to be transferred -00: 16-bit data length -01: 24-bit data length -10: 32-bit data length -11: Not allowed -Note: For correct operation, these bits should be configured when the I2S is disabled. - 1 - 2 - read-write - - - CHSIZ - Channel length (number of bits per audio channel) -0: 16-bit wide -1: 32-bit wide -The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. -Note: For correct operation, this bit should be configured when the I2S is disabled. - 0 - 1 - read-write - - - - - RXSLT - RX Slot Control Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EN - Slot enable for the channels. - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - PDM - PDM - PDM - 0xf0154000 - - 0x0 - 0x34 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x809FF7FF - - - SFTRST - software reset the module. Self-clear. - 31 - 1 - read-write - - - SOF_FEDGE - asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - 23 - 1 - read-write - - - USE_COEF_RAM - Asserted to use Coef RAM instead of Coef ROM - 20 - 1 - read-write - - - FILT_CRX_ERR_IE - data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - 19 - 1 - read-write - - - OFIFO_OVFL_ERR_IE - output fifo overflow error interrupt enable - 18 - 1 - read-write - - - CIC_OVLD_ERR_IE - CIC overload error interrupt enable - 17 - 1 - read-write - - - CIC_SAT_ERR_IE - Error interrupt enable -This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. -0: Error interrupt is masked -1: Error interrupt is enabled - 16 - 1 - read-write - - - DEC_AFT_CIC - decimation rate after CIC. Now it is forced to be 3. - 12 - 4 - read-write - - - CAPT_DLY - Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - 7 - 4 - read-write - - - PDM_CLK_HFDIV - The clock divider will work at least 4. -0: div-by-2, -1: div-by-4 -. . . -n: div-by-2*(n+1) - 3 - 4 - read-write - - - PDM_CLK_DIV_BYPASS - asserted to bypass the pdm clock divider - 2 - 1 - read-write - - - PDM_CLK_OE - pdm_clk_output_en - 1 - 1 - read-write - - - HPF_EN - pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - 0 - 1 - read-write - - - - - CH_CTRL - Channel Control Register - 0x4 - 32 - 0x00000000 - 0x00FF03FF - - - CH_POL - Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - 16 - 8 - read-write - - - CH_EN - Asserted to enable the channel. -Ch8 & 9 are refs. -Ch0-7 are pdm mics. - 0 - 10 - read-write - - - - - ST - Status Register - 0x8 - 32 - 0x00000000 - 0x0000000F - - - FILT_CRX_ERR - data accessed out of boundary error - 3 - 1 - write-only - - - OFIFO_OVFL_ERR - output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - 2 - 1 - write-only - - - CIC_OVLD_ERR - CIC overload error. write 1 clear - 1 - 1 - write-only - - - CIC_SAT_ERR - CIC saturation. Write 1 clear - 0 - 1 - write-only - - - - - CH_CFG - Channel Configuration Register - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - CH9_TYPE - No description available - 18 - 2 - read-write - - - CH8_TYPE - No description available - 16 - 2 - read-write - - - CH7_TYPE - No description available - 14 - 2 - read-write - - - CH6_TYPE - No description available - 12 - 2 - read-write - - - CH5_TYPE - No description available - 10 - 2 - read-write - - - CH4_TYPE - No description available - 8 - 2 - read-write - - - CH3_TYPE - No description available - 6 - 2 - read-write - - - CH2_TYPE - No description available - 4 - 2 - read-write - - - CH1_TYPE - No description available - 2 - 2 - read-write - - - CH0_TYPE - Type of Channel 0 -2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) -2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - 0 - 2 - read-write - - - - - CIC_CFG - CIC configuration register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - POST_SCALE - the shift value after CIC results. - 10 - 6 - read-write - - - SGD - Sigma_delta_order[1:0] -2'b00: 7 -2'b01: 6 -2'b10: 5 -Others: unused - 8 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation factor - 0 - 8 - read-write - - - - - CTRL_INBUF - In Buf Control Register - 0x14 - 32 - 0x00000000 - 0x3FFFFFFF - - - MAX_PTR - The buf size-1 for each channel - 22 - 8 - read-write - - - PITCH - The spacing between starting address of adjacent channels - 11 - 11 - read-write - - - START_ADDR - The starting address of channel 0 in filter data buffer - 0 - 11 - read-write - - - - - CTRL_FILT0 - Filter 0 Control Register - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M0 - Coef length of filter type 2'b00 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b00 in coef memory - 0 - 8 - read-write - - - - - CTRL_FILT1 - Filter 1 Control Register - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - COEF_LEN_M1 - Coef length of filter type 2'b01 in coef memory - 8 - 8 - read-write - - - COEF_START_ADDR - Starting address of Coef of filter type 2'b01 in coef memory - 0 - 8 - read-write - - - - - RUN - Run Register - 0x20 - 32 - 0x00000000 - 0x00000001 - - - PDM_EN - Asserted to enable the module - 0 - 1 - read-write - - - - - MEMAddr - Memory Access Address - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - 0--0x0FFFFFFF: COEF_RAM -0x10000000--0x1FFFFFFF: DATA_RAM - 0 - 32 - read-write - - - - - MEMData - Memory Access Data - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - The data write-to/read-from buffer - 0 - 32 - read-write - - - - - HPF_MA - HPF A Coef Register - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - Composite value of coef A of the Order-1 HPF - 0 - 32 - read-write - - - - - HPF_B - HPF B Coef Register - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEF - coef B of the Order-1 HPF - 0 - 32 - read-write - - - - - - - MCAN0 - MCAN0 - MCAN - 0xf0300000 - - 0x4 - 0x408 - registers - - - - ENDN - endian register - 0x4 - 32 - 0x87654321 - 0xFFFFFFFF - - - EVT - Endianness Test Value -The endianness test value is 0x87654321. - 0 - 32 - read-only - - - - - DBTP - data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set - 0xc - 32 - 0x00000A33 - 0x009F1FFF - - - TDC - transmitter delay compensation enable -0= Transmitter Delay Compensation disabled -1= Transmitter Delay Compensation enabled - 23 - 1 - read-write - - - DBRP - Data Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. -When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 5 - read-write - - - DTSEG1 - Data time segment before sample point -Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 5 - read-write - - - DTSEG2 - Data time segment after sample point -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 4 - 4 - read-write - - - DSJW - Data (Re)Synchronization Jump Width -Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 0 - 4 - read-write - - - - - TEST - test register - 0x10 - 32 - 0x00000000 - 0x003F3FF0 - - - SVAL - Started Valid -0= Value of TXBNS not valid -1= Value of TXBNS valid - 21 - 1 - read-only - - - TXBNS - Tx Buffer Number Started -Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - 16 - 5 - read-only - - - PVAL - Prepared Valid -0= Value of TXBNP not valid -1= Value of TXBNP valid - 13 - 1 - read-only - - - TXBNP - Tx Buffer Number Prepared -Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - 8 - 5 - read-only - - - RX - Receive Pin -Monitors the actual value of pin m_can_rx -0= The CAN bus is dominant (m_can_rx = ‘0’) -1= The CAN bus is recessive (m_can_rx = ‘1’) - 7 - 1 - read-only - - - TX - Control of Transmit Pin -00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time -01 Sample Point can be monitored at pin m_can_tx -10 Dominant (‘0’) level at pin m_can_tx -11 Recessive (‘1’) at pin m_can_tx - 5 - 2 - read-write - - - LBCK - Loop Back Mode -0= Reset value, Loop Back Mode is disabled -1= Loop Back Mode is enabled - 4 - 1 - read-write - - - - - RWD - ram watchdog - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - WDV - Watchdog Value -Actual Message RAM Watchdog Counter Value. - 8 - 8 - read-only - - - WDC - Watchdog Configuration -Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - 0 - 8 - read-write - - - - - CCCR - CC control register - 0x18 - 32 - 0x00000001 - 0x0000FFFF - - - NISO - Non ISO Operation -If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD -Specification V1.0. -0= CAN FD frame format according to ISO 11898-1:2015 -1= CAN FD frame format according to Bosch CAN FD Specification V1.0 -Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - 15 - 1 - read-write - - - TXP - Transmit Pause -If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after -itself has successfully transmitted a frame (see Section 3.5). -0= Transmit pause disabled -1= Transmit pause enabled - 14 - 1 - read-write - - - EFBI - Edge Filtering during Bus Integration -0= Edge filtering disabled -1= Two consecutive dominant tq required to detect an edge for hard synchronization - 13 - 1 - read-write - - - PXHD - Protocol Exception Handling Disable -0= Protocol exception handling enabled -1= Protocol exception handling disabled -Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - 12 - 1 - read-write - - - WMM - Wide Message Marker -Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. -0= 8-bit Message Marker used -1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - 11 - 1 - read-write - - - UTSU - Use Timestamping Unit -When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. -0= Internal time stamping -1= External time stamping by TSU -Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. -In this case bit UTSU is fixed to zero by synthesis. - 10 - 1 - read-write - - - BRSE - Bit Rate Switch Enable -0= Bit rate switching for transmissions disabled -1= Bit rate switching for transmissions enabled -Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - 9 - 1 - read-write - - - FDOE - FD Operation Enable -0= FD operation disabled -1= FD operation enabled - 8 - 1 - read-write - - - TEST - Test Mode Enable -0= Normal operation, register TEST holds reset values -1= Test Mode, write access to register TEST enabled - 7 - 1 - read-write - - - DAR - Disable Automatic Retransmission -0= Automatic retransmission of messages not transmitted successfully enabled -1= Automatic retransmission disabled - 6 - 1 - read-write - - - MON - Bus Monitoring Mode -Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. -0= Bus Monitoring Mode is disabled -1= Bus Monitoring Mode is enabled - 5 - 1 - read-write - - - CSR - Clock Stop Request -0= No clock stop is requested -1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - 4 - 1 - read-write - - - CSA - Clock Stop Acknowledge -0= No clock stop acknowledged -1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - 3 - 1 - read-only - - - ASM - Restricted Operation Mode -Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. -0= Normal CAN operation -1= Restricted Operation Mode active - 2 - 1 - read-write - - - CCE - Configuration Change Enable -0= The CPU has no write access to the protected configuration registers -1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - 1 - 1 - read-write - - - INIT - Initialization -0= Normal Operation -1= Initialization is started - 0 - 1 - read-write - - - - - NBTP - nominal bit timing and prescaler register - 0x1c - 32 - 0x06000A03 - 0xFFFFFF7F - - - NSJW - Nominal (Re)Synchronization Jump Width -Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 25 - 7 - read-write - - - NBRP - Nominal Bit Rate Prescaler -The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is -such that one more than the value programmed here is used. - 16 - 9 - read-write - - - NTSEG1 - Nominal Time segment before sample point -Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 8 - 8 - read-write - - - NTSEG2 - Nominal Time segment after sample point -Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - 0 - 7 - read-write - - - - - TSCC - timestamp counter configuration - 0x20 - 32 - 0x00000000 - 0x000F0003 - - - TCP - Timestamp Counter Prescaler -Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - 16 - 4 - read-write - - - TSS - timestamp Select -00= Timestamp counter value always 0x0000 -01= Timestamp counter value incremented according to TCP -10= External timestamp counter value used -11= Same as “00” - 0 - 2 - read-write - - - - - TSCV - timestamp counter value - 0x24 - 32 - 0x00000000 - 0x0000FFFF - - - TSC - Timestamp Counter -The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - 0 - 16 - read-only - - - - - TOCC - timeout counter configuration - 0x28 - 32 - 0xFFFF0000 - 0xFFFF0007 - - - TOP - Timeout Period -Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - 16 - 16 - read-write - - - TOS - Timeout Select -When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. -When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. -00= Continuous operation -01= Timeout controlled by Tx Event FIFO -10= Timeout controlled by Rx FIFO 0 -11= Timeout controlled by Rx FIFO 1 - 1 - 2 - read-write - - - RP - Enable Timeout Counter -0= Timeout Counter disabled -1= Timeout Counter enabled - 0 - 1 - read-write - - - - - TOCV - timeout counter value - 0x2c - 32 - 0x0000FFFF - 0x0000FFFF - - - TOC - Timeout Counter -The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. -When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. -Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - 0 - 16 - read-only - - - - - ECR - error counter register - 0x40 - 32 - 0x00000000 - 0x00FFFFFF - - - CEL - CAN Error Logging -The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. -The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. -The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. -Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - 16 - 8 - read-only - - - RP - Receive Error Passive -0= The Receive Error Counter is below the error passive level of 128 -1= The Receive Error Counter has reached the error passive level of 128 - 15 - 1 - read-only - - - REC - Receive Error Counter -Actual state of the Receive Error Counter, values between 0 and 127 - 8 - 7 - read-only - - - TEC - Transmit Error Counter -Actual state of the Transmit Error Counter, values between 0 and 255 -Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - 0 - 8 - read-only - - - - - PSR - protocol status register - 0x44 - 32 - 0x00000707 - 0x007F7FFF - - - TDCV - Transmitter Delay Compensation Value -Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. -The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - 16 - 7 - read-only - - - PXE - Protocol Exception Event -0= No protocol exception event occurred since last read access -1= Protocol exception event occurred -Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - 14 - 1 - read-only - - - RFDF - Received a CAN FD Message -This bit is set independent of acceptance filtering. -0= Since this bit was reset by the CPU, no CAN FD message has been received -1= Message in CAN FD format with FDF flag set has been received -Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - 13 - 1 - read-only - - - RBRS - BRS flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its BRS flag set -1= Last received CAN FD message had its BRS flag set -Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - 12 - 1 - read-only - - - RESI - ESI flag of last received CAN FD Message -This bit is set together with RFDF, independent of acceptance filtering. -0= Last received CAN FD message did not have its ESI flag set -1= Last received CAN FD message had its ESI flag set -Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - 11 - 1 - read-only - - - DLEC - Data Phase Last Error Code -Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with -its BRS flag set has been transferred (reception or transmission) without error. -Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - 8 - 3 - read-only - - - BO - Bus_Off Status -0= The M_CAN is not Bus_Off -1= The M_CAN is in Bus_Off state - 7 - 1 - read-only - - - EW - Warning Status -0= Both error counters are below the Error_Warning limit of 96 -1= At least one of error counter has reached the Error_Warning limit of 96 - 6 - 1 - read-only - - - EP - Error Passive -0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected -1= The M_CAN is in the Error_Passive state - 5 - 1 - read-only - - - ACT - Activity -Monitors the module’s CAN communication state. -00= Synchronizing - node is synchronizing on CAN communication -01= Idle - node is neither receiver nor transmitter -10= Receiver - node is operating as receiver -11= Transmitter - node is operating as transmitter -Note: ACT is set to “00” by a Protocol Exception Event. - 3 - 2 - read-only - - - LEC - Last Error Code -The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. -0= No Error: No error occurred since LEC has been reset by successful reception or transmission. -1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. -2= Form Error: A fixed format part of a received frame has the wrong format. -3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. -4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), -the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus -value was dominant. -5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at -dominant or continuously disturbed). -6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. -7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. -Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. -Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. -At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, -enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. -Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - 0 - 3 - read-only - - - - - TDCR - transmitter delay compensation - 0x48 - 32 - 0x00000000 - 0x00007F7F - - - TDCO - Transmitter Delay Compensation SSP Offset -Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - 8 - 7 - read-write - - - TDCF - Transmitter Delay Compensation Filter Window Length -Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. -The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - 0 - 7 - read-write - - - - - IR - interrupt register - 0x50 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARA - Access to Reserved Address -0= No access to reserved address occurred -1= Access to reserved address occurred - 29 - 1 - read-write - - - PED - Protocol Error in Data Phase (Data Bit Time is used) -0= No protocol error in data phase -1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - 28 - 1 - read-write - - - PEA - Protocol Error in Arbitration Phase (Nominal Bit Time is used) -0= No protocol error in arbitration phase -1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - 27 - 1 - read-write - - - WDI - Watchdog Interrupt -0= No Message RAM Watchdog event occurred -1= Message RAM Watchdog event due to missing READY - 26 - 1 - read-write - - - BO - Bus_Off Status -0= Bus_Off status unchanged -1= Bus_Off status changed - 25 - 1 - read-write - - - EW - Warning Status -0= Error_Warning status unchanged -1= Error_Warning status changed - 24 - 1 - read-write - - - EP - Error Passive -0= Error_Passive status unchanged -1= Error_Passive status changed - 23 - 1 - read-write - - - ELO - Error Logging Overflow -0= CAN Error Logging Counter did not overflow -1= Overflow of CAN Error Logging Counter occurred - 22 - 1 - read-write - - - BEU - Bit Error Uncorrected -Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. -An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. -0= No bit error detected when reading from Message RAM -1= Bit error detected, uncorrected (e.g. parity logic) - 21 - 1 - read-write - - - BEC - Bit Error Corrected -Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. -0= No bit error detected when reading from Message RAM -1= Bit error detected and corrected (e.g. ECC) - 20 - 1 - read-write - - - DRX - Message stored to Dedicated Rx Buffer -The flag is set whenever a received message has been stored into a dedicated Rx Buffer. -0= No Rx Buffer updated -1= At least one received message stored into an Rx Buffer - 19 - 1 - read-write - - - TOO - Timeout Occurred -0= No timeout -1= Timeout reached - 18 - 1 - read-write - - - MRAF - Message RAM Access Failure -The flag is set, when the Rx Handler -.has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message -storage is aborted and the Rx Handler starts processing of the following message. -.was not able to write a message to the Message RAM. In this case message storage is aborted. -In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. -The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the -M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. -0= No Message RAM access failure occurred -1= Message RAM access failure occurred - 17 - 1 - read-write - - - TSW - Timestamp Wraparound -0= No timestamp counter wrap-around -1= Timestamp counter wrapped around - 16 - 1 - read-write - - - TEFL - Tx Event FIFO Element Lost -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - 15 - 1 - read-write - - - TEFF - Tx Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 14 - 1 - read-write - - - TEFW - Tx Event FIFO Watermark Reached -0= Tx Event FIFO fill level below watermark -1= Tx Event FIFO fill level reached watermark - 13 - 1 - read-write - - - TEFN - Tx Event FIFO New Entry -0= Tx Event FIFO unchanged -1= Tx Handler wrote Tx Event FIFO element - 12 - 1 - read-write - - - TFE - Tx FIFO Empty -0= Tx FIFO non-empty -1= Tx FIFO empty - 11 - 1 - read-write - - - TCF - Transmission Cancellation Finished -0= No transmission cancellation finished -1= Transmission cancellation finished - 10 - 1 - read-write - - - TC - Transmission Completed -0= No transmission completed -1= Transmission completed - 9 - 1 - read-write - - - HPM - High Priority Message -0= No high priority message received -1= High priority message received - 8 - 1 - read-write - - - RF1L - Rx FIFO 1 Message Lost -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - 7 - 1 - read-write - - - RF1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 6 - 1 - read-write - - - RF1W - Rx FIFO 1 Watermark Reached -0= Rx FIFO 1 fill level below watermark -1= Rx FIFO 1 fill level reached watermark - 5 - 1 - read-write - - - RF1N - Rx FIFO 1 New Message -0= No new message written to Rx FIFO 1 -1= New message written to Rx FIFO 1 - 4 - 1 - read-write - - - RF0L - Rx FIFO 0 Message Lost -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - 3 - 1 - read-write - - - RF0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 2 - 1 - read-write - - - RF0W - Rx FIFO 0 Watermark Reached -0= Rx FIFO 0 fill level below watermark -1= Rx FIFO 0 fill level reached watermark - 1 - 1 - read-write - - - RF0N - Rx FIFO 0 New Message -0= No new message written to Rx FIFO 0 -1= New message written to Rx FIFO 0 - 0 - 1 - read-write - - - - - IE - interrupt enable - 0x54 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAE - Access to Reserved Address Enable - 29 - 1 - read-write - - - PEDE - Protocol Error in Data Phase Enable - 28 - 1 - read-write - - - PEAE - Protocol Error in Arbitration Phase Enable - 27 - 1 - read-write - - - WDIE - Watchdog Interrupt Enable - 26 - 1 - read-write - - - BOE - Bus_Off Status Interrupt Enable - 25 - 1 - read-write - - - EWE - Warning Status Interrupt Enable - 24 - 1 - read-write - - - EPE - Error Passive Interrupt Enable - 23 - 1 - read-write - - - ELOE - Error Logging Overflow Interrupt Enable - 22 - 1 - read-write - - - BEUE - Bit Error Uncorrected Interrupt Enable - 21 - 1 - read-write - - - BECE - Bit Error Corrected Interrupt Enable - 20 - 1 - read-write - - - DRXE - Message stored to Dedicated Rx Buffer Interrupt Enable - 19 - 1 - read-write - - - TOOE - Timeout Occurred Interrupt Enable - 18 - 1 - read-write - - - MRAFE - Message RAM Access Failure Interrupt Enable - 17 - 1 - read-write - - - TSWE - Timestamp Wraparound Interrupt Enable - 16 - 1 - read-write - - - TEFLE - Tx Event FIFO Event Lost Interrupt Enable - 15 - 1 - read-write - - - TEFFE - Tx Event FIFO Full Interrupt Enable - 14 - 1 - read-write - - - TEFWE - Tx Event FIFO Watermark Reached Interrupt Enable - 13 - 1 - read-write - - - TEFNE - Tx Event FIFO New Entry Interrupt Enable - 12 - 1 - read-write - - - TFEE - Tx FIFO Empty Interrupt Enable - 11 - 1 - read-write - - - TCFE - Transmission Cancellation Finished Interrupt Enable - 10 - 1 - read-write - - - TCE - Transmission Completed Interrupt Enable - 9 - 1 - read-write - - - HPME - High Priority Message Interrupt Enable - 8 - 1 - read-write - - - RF1LE - Rx FIFO 1 Message Lost Interrupt Enable - 7 - 1 - read-write - - - RF1FE - Rx FIFO 1 Full Interrupt Enable - 6 - 1 - read-write - - - RF1WE - Rx FIFO 1 Watermark Reached Interrupt Enable - 5 - 1 - read-write - - - RF1NE - Rx FIFO 1 New Message Interrupt Enable - 4 - 1 - read-write - - - RF0LE - Rx FIFO 0 Message Lost Interrupt Enable - 3 - 1 - read-write - - - RF0FE - Rx FIFO 0 Full Interrupt Enable - 2 - 1 - read-write - - - RF0WE - Rx FIFO 0 Watermark Reached Interrupt Enable - 1 - 1 - read-write - - - RF0NE - Rx FIFO 0 New Message Interrupt Enable - 0 - 1 - read-write - - - - - ILS - interrupt line select - 0x58 - 32 - 0x00000000 - 0x3FFFFFFF - - - ARAL - Access to Reserved Address Line - 29 - 1 - read-write - - - PEDL - Protocol Error in Data Phase Line - 28 - 1 - read-write - - - PEAL - Protocol Error in Arbitration Phase Line - 27 - 1 - read-write - - - WDIL - Watchdog Interrupt Line - 26 - 1 - read-write - - - BOL - Bus_Off Status Interrupt Line - 25 - 1 - read-write - - - EWL - Warning Status Interrupt Line - 24 - 1 - read-write - - - EPL - Error Passive Interrupt Line - 23 - 1 - read-write - - - ELOL - Error Logging Overflow Interrupt Line - 22 - 1 - read-write - - - BEUL - Bit Error Uncorrected Interrupt Line - 21 - 1 - read-write - - - BECL - Bit Error Corrected Interrupt Line - 20 - 1 - read-write - - - DRXL - Message stored to Dedicated Rx Buffer Interrupt Line - 19 - 1 - read-write - - - TOOL - Timeout Occurred Interrupt Line - 18 - 1 - read-write - - - MRAFL - Message RAM Access Failure Interrupt Line - 17 - 1 - read-write - - - TSWL - Timestamp Wraparound Interrupt Line - 16 - 1 - read-write - - - TEFLL - Tx Event FIFO Event Lost Interrupt Line - 15 - 1 - read-write - - - TEFFL - Tx Event FIFO Full Interrupt Line - 14 - 1 - read-write - - - TEFWL - Tx Event FIFO Watermark Reached Interrupt Line - 13 - 1 - read-write - - - TEFNL - Tx Event FIFO New Entry Interrupt Line - 12 - 1 - read-write - - - TFEL - Tx FIFO Empty Interrupt Line - 11 - 1 - read-write - - - TCFL - Transmission Cancellation Finished Interrupt Line - 10 - 1 - read-write - - - TCL - Transmission Completed Interrupt Line - 9 - 1 - read-write - - - HPML - High Priority Message Interrupt Line - 8 - 1 - read-write - - - RF1LL - Rx FIFO 1 Message Lost Interrupt Line - 7 - 1 - read-write - - - RF1FL - Rx FIFO 1 Full Interrupt Line - 6 - 1 - read-write - - - RF1WL - Rx FIFO 1 Watermark Reached Interrupt Line - 5 - 1 - read-write - - - RF1NL - Rx FIFO 1 New Message Interrupt Line - 4 - 1 - read-write - - - RF0LL - Rx FIFO 0 Message Lost Interrupt Line - 3 - 1 - read-write - - - RF0FL - Rx FIFO 0 Full Interrupt Line - 2 - 1 - read-write - - - RF0WL - Rx FIFO 0 Watermark Reached Interrupt Line - 1 - 1 - read-write - - - RF0NL - Rx FIFO 0 New Message Interrupt Line - 0 - 1 - read-write - - - - - ILE - interrupt line enable - 0x5c - 32 - 0x00000000 - 0x00000003 - - - EINT1 - Enable Interrupt Line 1 -0= Interrupt line m_can_int1 disabled -1= Interrupt line m_can_int1 enabled - 1 - 1 - read-write - - - EINT0 - Enable Interrupt Line 0 -0= Interrupt line m_can_int0 disabled -1= Interrupt line m_can_int0 enabled - 0 - 1 - read-write - - - - - GFC - global filter configuration - 0x80 - 32 - 0x00000000 - 0x0000003F - - - ANFS - Accept Non-matching Frames Standard -Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 4 - 2 - read-write - - - ANFE - Accept Non-matching Frames Extended -Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. -00= Accept in Rx FIFO 0 -01= Accept in Rx FIFO 1 -10= Reject -11= Reject - 2 - 2 - read-write - - - RRFS - Reject Remote Frames Standard -0= Filter remote frames with 11-bit standard IDs -1= Reject all remote frames with 11-bit standard IDs - 1 - 1 - read-write - - - RRFE - Reject Remote Frames Extended -0= Filter remote frames with 29-bit extended IDs -1= Reject all remote frames with 29-bit extended IDs - 0 - 1 - read-write - - - - - SIDFC - standard ID filter configuration - 0x84 - 32 - 0x00000000 - 0x00FFFFFC - - - LSS - List Size Standard -0= No standard Message ID filter -1-128= Number of standard Message ID filter elements ->128= Values greater than 128 are interpreted as 128 - 16 - 8 - read-write - - - FLSSA - Filter List Standard Start Address -Start address of standard Message ID filter list (32-bit word address) - 2 - 14 - read-write - - - - - XIDFC - extended ID filter configuration - 0x88 - 32 - 0x00000000 - 0x007FFFFC - - - LSE - List Size Extended -0= No extended Message ID filter -1-64= Number of extended Message ID filter elements ->64= Values greater than 64 are interpreted as 64 - 16 - 7 - read-write - - - FLESA - Filter List Extended Start Address -Start address of extended Message ID filter list (32-bit word address). - 2 - 14 - read-write - - - - - XIDAM - extended id and mask - 0x90 - 32 - 0x1FFFFFFF - 0x1FFFFFFF - - - EIDM - Extended ID Mask -For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - 0 - 29 - read-write - - - - - HPMS - high priority message status - 0x94 - 32 - 0x00000000 - 0x0000FFFF - - - FLST - Filter List -Indicates the filter list of the matching filter element. -0= Standard Filter List -1= Extended Filter List - 15 - 1 - read-only - - - FIDX - Filter Index -Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - 8 - 7 - read-only - - - MSI - Message Storage Indicator -00= No FIFO selected -01= FIFO message lost -10= Message stored in FIFO 0 -11= Message stored in FIFO 1 - 6 - 2 - read-only - - - BIDX - Buffer Index -Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - 0 - 6 - read-only - - - - - NDAT1 - new data1 - 0x98 - 32 - 0x00000000 - 0xFFFFFFFF - - - ND1 - New Data[31:0] -The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - NDAT2 - new data2 - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - ND2 - New Data[63:32] -The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. -The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. -0= Rx Buffer not updated -1= Rx Buffer updated from new message - 0 - 32 - read-write - - - - - RXF0C - rx fifo 0 configuration - 0xa0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F0OM - FIFO 0 Operation Mode -FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 0 blocking mode -1= FIFO 0 overwrite mode - 31 - 1 - read-write - - - F0WM - Rx FIFO 0 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F0S - Rx FIFO 0 Size -0= No Rx FIFO 0 -1-64= Number of Rx FIFO 0 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 0 elements are indexed from 0 to F0S-1 - 16 - 7 - read-write - - - F0SA - Rx FIFO 0 Start Address -Start address of Rx FIFO 0 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF0S - rx fifo 0 status - 0xa4 - 32 - 0x00000000 - 0x033F3F7F - - - RF0L - Rx FIFO 0 Message Lost -This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. -0= No Rx FIFO 0 message lost -1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero -Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F0F - Rx FIFO 0 Full -0= Rx FIFO 0 not full -1= Rx FIFO 0 full - 24 - 1 - read-only - - - F0PI - Rx FIFO 0 Put Index -Rx FIFO 0 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F0GI - Rx FIFO 0 Get Index -Rx FIFO 0 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F0FL - Rx FIFO 0 Fill Level -Number of elements stored in Rx FIFO 0, range 0 to 64. - 0 - 7 - read-only - - - - - RXF0A - rx fifo0 acknowledge - 0xa8 - 32 - 0x00000000 - 0x0000003F - - - F0AI - Rx FIFO 0 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. -This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - 0 - 6 - read-write - - - - - RXBC - rx buffer configuration - 0xac - 32 - 0x00000000 - 0x0000FFFC - - - RBSA - Rx Buffer Start Address -Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - 2 - 14 - read-write - - - - - RXF1C - rx fifo1 configuration - 0xb0 - 32 - 0x00000000 - 0xFF7FFFFC - - - F1OM - FIFO 1 Operation Mode -FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). -0= FIFO 1 blocking mode -1= FIFO 1 overwrite mode - 31 - 1 - read-write - - - F1WM - Rx FIFO 1 Watermark -0= Watermark interrupt disabled -1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) ->64= Watermark interrupt disabled - 24 - 7 - read-write - - - F1S - Rx FIFO 1 Size -0= No Rx FIFO 1 -1-64= Number of Rx FIFO 1 elements ->64= Values greater than 64 are interpreted as 64 -The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - 16 - 7 - read-write - - - F1SA - Rx FIFO 1 Start Address -Start address of Rx FIFO 1 in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - RXF1S - rx fifo1 status - 0xb4 - 32 - 0x00000000 - 0xC33F3F7F - - - DMS - Debug Message Status -00= Idle state, wait for reception of debug messages, DMA request is cleared -01= Debug message A received -10= Debug messages A, B received -11= Debug messages A, B, C received, DMA request is set - 30 - 2 - read-only - - - RF1L - Rx FIFO 1 Message Lost -This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. -0= No Rx FIFO 1 message lost -1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero -Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - 25 - 1 - read-only - - - F1F - Rx FIFO 1 Full -0= Rx FIFO 1 not full -1= Rx FIFO 1 full - 24 - 1 - read-only - - - F1PI - Rx FIFO 1 Put Index -Rx FIFO 1 write index pointer, range 0 to 63. - 16 - 6 - read-only - - - F1GI - Rx FIFO 1 Get Index -Rx FIFO 1 read index pointer, range 0 to 63. - 8 - 6 - read-only - - - F1FL - Rx FIFO 1 Fill Level -Number of elements stored in Rx FIFO 1, range 0 to 64. - 0 - 7 - read-only - - - - - RXF1A - rx fifo 1 acknowledge - 0xb8 - 32 - 0x00000000 - 0x0000003F - - - F1AI - Rx FIFO 1 Acknowledge Index -After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. -This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - 0 - 6 - read-write - - - - - RXESC - rx buffer/fifo element size configuration - 0xbc - 32 - 0x00000000 - 0x00000777 - - - RBDS - Rx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 8 - 3 - read-write - - - F1DS - Rx FIFO 1 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field - 4 - 3 - read-write - - - F0DS - Rx FIFO 0 Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, -only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - 0 - 3 - read-write - - - - - TXBC - tx buffer configuration - 0xc0 - 32 - 0x00000000 - 0x7F3FFFFC - - - TFQM - Tx FIFO/Queue Mode -0= Tx FIFO operation -1= Tx Queue operation - 30 - 1 - read-write - - - TFQS - Transmit FIFO/Queue Size -0= No Tx FIFO/Queue -1-32= Number of Tx Buffers used for Tx FIFO/Queue ->32= Values greater than 32 are interpreted as 32 - 24 - 6 - read-write - - - NDTB - Number of Dedicated Transmit Buffers -0= No Dedicated Tx Buffers -1-32= Number of Dedicated Tx Buffers ->32= Values greater than 32 are interpreted as 32 - 16 - 6 - read-write - - - TBSA - Tx Buffers Start Address -Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). -Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - 2 - 14 - read-write - - - - - TXFQS - tx fifo/queue status - 0xc4 - 32 - 0x00000000 - 0x003F1F3F - - - TFQF - Tx FIFO/Queue Full -0= Tx FIFO/Queue not full -1= Tx FIFO/Queue full - 21 - 1 - read-only - - - TFQPI - Tx FIFO/Queue Put Index -Tx FIFO/Queue write index pointer, range 0 to 31. - 16 - 5 - read-only - - - TFGI - Tx FIFO Get Index -Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured -(TXBC.TFQM = ‘1’). - 8 - 5 - read-only - - - TFFL - Tx FIFO Free Level -Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) -Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with -the first dedicated Tx Buffers. -Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - 0 - 6 - read-only - - - - - TXESC - tx buffer element size configuration - 0xc8 - 32 - 0x00000000 - 0x00000007 - - - TBDS - Tx Buffer Data Field Size -000= 8 byte data field -001= 12 byte data field -010= 16 byte data field -011= 20 byte data field -100= 24 byte data field -101= 32 byte data field -110= 48 byte data field -111= 64 byte data field -Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - 0 - 3 - read-write - - - - - TXBRP - tx buffer request pending - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - TRP - Transmission Request Pending -Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register -TXBCR. -TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the -highest priority (Tx Buffer with lowest Message ID). -A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, -this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. -After a cancellation has been requested, a finished cancellation is signalled via TXBCF -? after successful transmission together with the corresponding TXBTO bit -? when the transmission has not yet been started at the point of cancellation -? when the transmission has been aborted due to lost arbitration -? when an error occurred during frame transmission -In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. -0= No transmission request pending -1= Transmission request pending -Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - 0 - 32 - read-only - - - - - TXBAR - tx buffer add request - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - AR - Add Request -Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx -Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. -When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. -0= No transmission request added -1= Transmission requested added -Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - 0 - 32 - read-write - - - - - TXBCR - tx buffer cancellation request - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CR - Cancellation Request -Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. -This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. -0= No cancellation pending -1= Cancellation pending - 0 - 32 - read-write - - - - - TXBTO - tx buffer transmission occurred - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TO - Transmission Occurred -Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmission occurred -1= Transmission occurred - 0 - 32 - read-only - - - - - TXBCF - tx buffer cancellation finished - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - CF - Cancellation Finished -Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. -In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. -0= No transmit buffer cancellation -1= Transmit buffer cancellation finished - 0 - 32 - read-only - - - - - TXBTIE - tx buffer transmission interrupt enable - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIE - Transmission Interrupt Enable -Each Tx Buffer has its own Transmission Interrupt Enable bit. -0= Transmission interrupt disabled -1= Transmission interrupt enable - 0 - 32 - read-write - - - - - TXBCIE - tx buffer cancellation finished interrupt enable - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CFIE - Cancellation Finished Interrupt Enable -Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. -0= Cancellation finished interrupt disabled -1= Cancellation finished interrupt enabled - 0 - 32 - read-write - - - - - TXEFC - tx event fifo configuration - 0xf0 - 32 - 0x00000000 - 0x3F3FFFFC - - - EFWM - Event FIFO Watermark -0= Watermark interrupt disabled -1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) ->32= Watermark interrupt disabled - 24 - 6 - read-write - - - EFS - Event FIFO Size -0= Tx Event FIFO disabled -1-32= Number of Tx Event FIFO elements ->32= Values greater than 32 are interpreted as 32 -The Tx Event FIFO elements are indexed from 0 to EFS - 1 - 16 - 6 - read-write - - - EFSA - Event FIFO Start Address -Start address of Tx Event FIFO in Message RAM (32-bit word address) - 2 - 14 - read-write - - - - - TXEFS - tx event fifo status - 0xf4 - 32 - 0x00000000 - 0x031F1F3F - - - TEFL - Tx Event FIFO Element Lost -This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. -0= No Tx Event FIFO element lost -1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - 25 - 1 - read-only - - - EFF - Event FIFO Full -0= Tx Event FIFO not full -1= Tx Event FIFO full - 24 - 1 - read-only - - - EFPI - Event FIFO Put Index -Tx Event FIFO write index pointer, range 0 to 31. - 16 - 5 - read-only - - - EFGI - Event FIFO Get Index -Tx Event FIFO read index pointer, range 0 to 31. - 8 - 5 - read-only - - - EFFL - Event FIFO Fill Level -Number of elements stored in Tx Event FIFO, range 0 to 32. - 0 - 6 - read-only - - - - - TXEFA - tx event fifo acknowledge - 0xf8 - 32 - 0x00000000 - 0x0000001F - - - EFAI - Event FIFO Acknowledge Index -After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get -Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - 0 - 5 - read-write - - - - - 16 - 0x4 - TS_SEL0,TS_SEL1,TS_SEL2,TS_SEL3,TS_SEL4,TS_SEL5,TS_SEL6,TS_SEL7,TS_SEL8,TS_SEL9,TS_SEL10,TS_SEL11,TS_SEL12,TS_SEL13,TS_SEL14,TS_SEL15 - TS_SEL[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - TS - Timestamp Word TS -default can save 16 timestamps with 32bit; -if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - 0 - 32 - read-only - - - - - CREL - core release register - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - REL - Core Release -One digit, BCD-coded - 28 - 4 - read-only - - - STEP - Step of Core Release -One digit, BCD-coded. - 24 - 4 - read-only - - - SUBSTEP - Sub-step of Core Release -One digit, BCD-coded - 20 - 4 - read-only - - - YEAR - Timestamp Year -One digit, BCD-coded. This field is set by generic parameter on -synthesis. - 16 - 4 - read-only - - - MON - Timestamp Month -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 8 - 8 - read-only - - - DAY - Timestamp Day -Two digits, BCD-coded. This field is set by generic parameter -on synthesis. - 0 - 8 - read-only - - - - - TSCFG - timestamp configuration - 0x244 - 32 - 0x00000000 - 0x0000FF0F - - - TBPRE - Timebase Prescaler -0x00 to 0xFF -The value by which the oscillator frequency is divided for -generating the timebase counter clock. Valid values for the -Timebase Prescaler are 0 to 255. The actual interpretation by -the hardware of this value is such that one more than the value -programmed here is used. Affects only the TSU internal -timebase. When the internal timebase is excluded by synthesis, -TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not -used. - 8 - 8 - read-write - - - EN64 - set to use 64bit timestamp. -when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. -TSP can be used to select different one - 3 - 1 - read-write - - - SCP - Select Capturing Position -0: Capture Timestamp at EOF -1: Capture Timestamp at SOF - 2 - 1 - read-write - - - TBCS - Timebase Counter Select -When the internal timebase is excluded by synthesis, TBCS is -fixed to ‘1’. -0: Timestamp value captured from internal timebase counter, - ATB.TB[31:0] is the internal timbase counter -1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - 1 - 1 - read-write - - - TSUE - Timestamp Unit Enable -0: TSU disabled -1: TSU enabled - 0 - 1 - read-write - - - - - TSS1 - timestamp status1 - 0x248 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSL - Timestamp Lost -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. -Reading a Timestamp register resets the related bit. - 16 - 16 - read-only - - - TSN - Timestamp New -Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related -Timestamp register. Reading a Timestamp register resets the related bit. - 0 - 16 - read-only - - - - - TSS2 - timestamp status2 - 0x24c - 32 - 0x00000000 - 0x0000000F - - - TSP - Timestamp Pointer -The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 -depending on number_ts_g), it is incremented to 0. -Value also signalled on output m_can_tsp[3:0]. - 0 - 4 - read-only - - - - - ATB - actual timebase - 0x250 - 32 - 0x00000000 - 0xFFFFFFFF - - - TB - timebase for timestamp generation 31-0 - 0 - 32 - read-only - - - - - ATBH - actual timebase high - 0x254 - 32 - 0x00000000 - 0xFFFFFFFF - - - TBH - timebase for timestamp generation 63-32 - 0 - 32 - read-only - - - - - GLB_CTL - global control - 0x400 - 32 - 0x00000000 - 0xE0000003 - - - M_CAN_STBY - m_can standby control - 31 - 1 - read-write - - - STBY_CLR_EN - m_can standby clear control -0:controlled by software by standby bit[bit31] -1:auto clear standby by hardware when rx data is 0 - 30 - 1 - read-write - - - STBY_POL - standby polarity selection - 29 - 1 - read-write - - - TSU_TBIN_SEL - external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - 0 - 2 - read-write - - - - - GLB_STATUS - global status - 0x404 - 32 - 0x00000000 - 0x0000000C - - - M_CAN_INT1 - m_can interrupt status1 - 3 - 1 - read-only - - - M_CAN_INT0 - m_can interrupt status0 - 2 - 1 - read-only - - - - - - - MCAN1 - MCAN1 - MCAN - 0xf0304000 - - - MCAN2 - MCAN2 - MCAN - 0xf0308000 - - - MCAN3 - MCAN3 - MCAN - 0xf030c000 - - - MCAN4 - MCAN4 - MCAN - 0xf0310000 - - - MCAN5 - MCAN5 - MCAN - 0xf0314000 - - - MCAN6 - MCAN6 - MCAN - 0xf0318000 - - - MCAN7 - MCAN7 - MCAN - 0xf031c000 - - - PTPC - PTPC - PTPC - 0xf037c000 - - 0x0 - 0x3004 - registers - - - - 2 - 0x1000 - 0,1 - PTPC[%s] - no description available - 0x0 - - Ctrl0 - Control Register 0 - 0x0 - 32 - 0x00000000 - 0x000003FF - - - SUBSEC_DIGITAL_ROLLOVER - Format for ns counter rollover, -1-digital, overflow time 1000000000/0x3B9ACA00 -0-binary, overflow time 0x7FFFFFFF - 9 - 1 - read-write - - - CAPT_SNAP_KEEP - set will keep capture snap till software read capt_snapl. -If this bit is set, software should read capt_snaph first to avoid wrong result. -If this bit is cleared, capture result will be updated at each capture event - 8 - 1 - read-write - - - CAPT_SNAP_POS_EN - set will use posege of input capture signal to latch timestamp value - 7 - 1 - read-write - - - CAPT_SNAP_NEG_EN - No description available - 6 - 1 - read-write - - - COMP_EN - set to enable compare, will be cleared by HW when compare event triggered - 4 - 1 - read-write - - - UPDATE_TIMER - update timer with +/- ts_updt, pulse, clear after set - 3 - 1 - write-only - - - INIT_TIMER - initial timer with ts_updt, pulse, clear after set - 2 - 1 - write-only - - - FINE_COARSE_SEL - 0: coarse update, ns counter add ss_incr[7:0] each clk -1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - 1 - 1 - read-write - - - TIMER_ENABLE - No description available - 0 - 1 - read-write - - - - - ctrl1 - Control Register 1 - 0x4 - 32 - 0x00000000 - 0x000000FF - - - SS_INCR - constant value used to add ns counter; -such as for 50MHz timer clock, set it to 8'd20 - 0 - 8 - read-write - - - - - timeh - timestamp high - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_HIGH - No description available - 0 - 32 - read-only - - - - - timel - timestamp low - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOW - No description available - 0 - 32 - read-only - - - - - ts_updth - timestamp update high - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_UPDATE - together with ts_updtl, used to initial or update timestamp - 0 - 32 - read-write - - - - - ts_updtl - timestamp update low - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADD_SUB - 1 for sub; 0 for add, used only at update - 31 - 1 - read-write - - - NS_UPDATE - No description available - 0 - 31 - read-write - - - - - addend - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDEND - used in fine update mode only - 0 - 32 - read-write - - - - - tarh - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_HIGH - used for generate compare signal if enabled - 0 - 32 - read-write - - - - - tarl - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TARGET_TIME_LOW - No description available - 0 - 32 - read-write - - - - - pps_ctrl - No description available - 0x2c - 32 - 0x00000000 - 0x0000000F - - - PPS_CTRL - No description available - 0 - 4 - read-write - - - - - capt_snaph - No description available - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_HIGH - take snapshot for input capture signal, at pos or neg or both; -the result can be kept or updated at each event according to cfg0.bit8 - 0 - 32 - read-only - - - - - capt_snapl - No description available - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAPT_SNAP_LOW - No description available - 0 - 32 - read-write - - - - - - time_sel - No description available - 0x2000 - 32 - 0x00000000 - 0x0000000F - - - CAN3_TIME_SEL - No description available - 3 - 1 - read-write - - - CAN2_TIME_SEL - No description available - 2 - 1 - read-write - - - CAN1_TIME_SEL - No description available - 1 - 1 - read-write - - - CAN0_TIME_SEL - set to use ptpc1 for canx -clr to use ptpc0 for canx - 0 - 1 - read-write - - - - - int_sts - No description available - 0x2004 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - write-only - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - write-only - - - PPS_INT_STS1 - No description available - 16 - 1 - write-only - - - COMP_INT_STS0 - No description available - 2 - 1 - write-only - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - write-only - - - PPS_INT_STS0 - No description available - 0 - 1 - write-only - - - - - int_en - No description available - 0x2008 - 32 - 0x00000000 - 0x00070007 - - - COMP_INT_STS1 - No description available - 18 - 1 - read-write - - - CAPTURE_INT_STS1 - No description available - 17 - 1 - read-write - - - PPS_INT_STS1 - No description available - 16 - 1 - read-write - - - COMP_INT_STS0 - No description available - 2 - 1 - read-write - - - CAPTURE_INT_STS0 - No description available - 1 - 1 - read-write - - - PPS_INT_STS0 - No description available - 0 - 1 - read-write - - - - - ptpc_can_ts_sel - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF00 - - - TSU_TBIN3_SEL - No description available - 26 - 6 - read-write - - - TSU_TBIN2_SEL - No description available - 20 - 6 - read-write - - - TSU_TBIN1_SEL - No description available - 14 - 6 - read-write - - - TSU_TBIN0_SEL - No description available - 8 - 6 - read-write - - - - - - - QEI0 - QEI0 - QEIV2 - 0xf0400000 - - 0x0 - 0x298 - registers - - - - cr - Control register - 0x0 - 32 - 0x00000000 - 0x807FFF7F - - - READ - 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - 31 - 1 - write-only - - - ZCNTCFG - 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 -0- zcnt will increment or decrement when Z input assert - 22 - 1 - read-write - - - PHCALIZ - 1- phcnt will set to phidx when Z input assert(for abz digital signsl) - 21 - 1 - read-write - - - Z_ONLY_EN - 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) - 20 - 1 - read-write - - - H2FDIR0 - No description available - 19 - 1 - read-write - - - H2FDIR1 - No description available - 18 - 1 - read-write - - - H2RDIR0 - No description available - 17 - 1 - read-write - - - H2RDIR1 - No description available - 16 - 1 - read-write - - - PAUSEPOS - 1- pause position output valid when PAUSE assert - 15 - 1 - read-write - - - PAUSESPD - 1- pause spdcnt when PAUSE assert - 14 - 1 - read-write - - - PAUSEPH - 1- pause phcnt when PAUSE assert - 13 - 1 - read-write - - - PAUSEZ - 1- pause zcnt when PAUSE assert - 12 - 1 - read-write - - - HFDIR0 - 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - 11 - 1 - read-write - - - HFDIR1 - 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - 10 - 1 - read-write - - - HRDIR0 - 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - 9 - 1 - read-write - - - HRDIR1 - 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - 8 - 1 - read-write - - - FAULTPOS - No description available - 6 - 1 - read-write - - - SNAPEN - 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - 5 - 1 - read-write - - - RSTCNT - 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - 4 - 1 - read-write - - - RD_SEL - define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, -width_snap0,width_snap1, timer_snap0, timer_snap1) -0 : same as hpm1000/500/500s; -1: use width for position; use timer for angle - 3 - 1 - read-write - - - ENCTYP - 000-abz; 001-pd; 010-ud; 011-UVW(hal) -100-single A; 101-single sin; 110: sin&cos - 0 - 3 - read-write - - - - - phcfg - Phase configure register - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - PHMAX - maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - 0 - 32 - read-write - - - - - wdgcfg - Watchdog configure register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WDGEN - 1- enable wdog counter - 31 - 1 - read-write - - - WDOG_CFG - define as stop if phase_cnt change is less than it -if 0, then each change of phase_cnt will clear wdog counter; -if 2, then phase_cnt change larger than 2 will clear wdog counter - 28 - 3 - read-write - - - WDGTO - watch dog timeout value - 0 - 28 - read-write - - - - - phidx - Phase index register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PHIDX - phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - 0 - 32 - read-write - - - - - trgoen - Tigger output enable register - 0x10 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGFEN - 1- enable trigger output when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- enable trigger output when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- enable trigger output when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- enable trigger output when zphf flag set - 28 - 1 - read-write - - - ZMISSFEN - No description available - 27 - 1 - read-write - - - WIDTHTMFEN - No description available - 26 - 1 - read-write - - - POS2CMPFEN - No description available - 25 - 1 - read-write - - - DIRCHGFEN - No description available - 24 - 1 - read-write - - - CYCLE0FEN - No description available - 23 - 1 - read-write - - - CYCLE1FEN - No description available - 22 - 1 - read-write - - - PULSE0FEN - No description available - 21 - 1 - read-write - - - PULSE1FEN - No description available - 20 - 1 - read-write - - - HOME2FEN - No description available - 19 - 1 - read-write - - - FAULTFEN - No description available - 18 - 1 - read-write - - - - - readen - Read event enable register - 0x14 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGFEN - 1- load counters to their read registers when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- load counters to their read registers when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- load counters to their read registers when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- load counters to their read registers when zphf flag set - 28 - 1 - read-write - - - ZMISSFEN - No description available - 27 - 1 - read-write - - - WIDTHTMFEN - No description available - 26 - 1 - read-write - - - POS2CMPFEN - No description available - 25 - 1 - read-write - - - DIRCHGFEN - No description available - 24 - 1 - read-write - - - CYCLE0FEN - No description available - 23 - 1 - read-write - - - CYCLE1FEN - No description available - 22 - 1 - read-write - - - PULSE0FEN - No description available - 21 - 1 - read-write - - - PULSE1FEN - No description available - 20 - 1 - read-write - - - HOME2FEN - No description available - 19 - 1 - read-write - - - FAULTFEN - No description available - 18 - 1 - read-write - - - - - zcmp - Z comparator - 0x18 - 32 - 0x80000000 - 0xFFFFFFFF - - - ZCMP - zcnt postion compare value - 0 - 32 - read-write - - - - - phcmp - Phase comparator - 0x1c - 32 - 0x80000000 - 0xFFFFFFFF - - - PHCMP - phcnt position compare value - 0 - 32 - read-write - - - - - spdcmp - Speed comparator - 0x20 - 32 - 0x80000000 - 0xFFFFFFFF - - - SPDCMP - spdcnt position compare value - 0 - 32 - read-write - - - - - dmaen - DMA request enable register - 0x24 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGFEN - 1- generate dma request when wdg flag set - 31 - 1 - read-write - - - HOMEFEN - 1- generate dma request when homef flag set - 30 - 1 - read-write - - - POSCMPFEN - 1- generate dma request when poscmpf flag set - 29 - 1 - read-write - - - ZPHFEN - 1- generate dma request when zphf flag set - 28 - 1 - read-write - - - ZMISSFEN - No description available - 27 - 1 - read-write - - - WIDTHTMFEN - No description available - 26 - 1 - read-write - - - POS2CMPFEN - No description available - 25 - 1 - read-write - - - DIRCHGFEN - No description available - 24 - 1 - read-write - - - CYCLE0FEN - No description available - 23 - 1 - read-write - - - CYCLE1FEN - No description available - 22 - 1 - read-write - - - PULSE0FEN - No description available - 21 - 1 - read-write - - - PULSE1FEN - No description available - 20 - 1 - read-write - - - HOME2FEN - No description available - 19 - 1 - read-write - - - FAULTFEN - No description available - 18 - 1 - read-write - - - - - sr - Status register - 0x28 - 32 - 0x00000000 - 0xFFFC0000 - - - WDGF - watchdog flag - 31 - 1 - read-write - - - HOMEF - home flag - 30 - 1 - read-write - - - POSCMPF - postion compare match flag - 29 - 1 - read-write - - - ZPHF - z input flag - 28 - 1 - read-write - - - ZMISSF - No description available - 27 - 1 - read-write - - - WIDTHTMF - No description available - 26 - 1 - read-write - - - POS2CMPF - No description available - 25 - 1 - read-write - - - DIRCHGF - No description available - 24 - 1 - read-write - - - CYCLE0F - No description available - 23 - 1 - read-write - - - CYCLE1F - No description available - 22 - 1 - read-write - - - PULSE0F - No description available - 21 - 1 - read-write - - - PULSE1F - No description available - 20 - 1 - read-write - - - HOME2F - No description available - 19 - 1 - read-write - - - FAULTF - No description available - 18 - 1 - read-write - - - - - irqen - Interrupt request register - 0x2c - 32 - 0x00000000 - 0xFFFC0000 - - - WDGIE - 1- generate interrupt when wdg flag set - 31 - 1 - read-write - - - HOMEIE - 1- generate interrupt when homef flag set - 30 - 1 - read-write - - - POSCMPIE - 1- generate interrupt when poscmpf flag set - 29 - 1 - read-write - - - ZPHIE - 1- generate interrupt when zphf flag set - 28 - 1 - read-write - - - ZMISSE - No description available - 27 - 1 - read-write - - - WIDTHTME - No description available - 26 - 1 - read-write - - - POS2CMPE - No description available - 25 - 1 - read-write - - - DIRCHGE - No description available - 24 - 1 - read-write - - - CYCLE0E - No description available - 23 - 1 - read-write - - - CYCLE1E - No description available - 22 - 1 - read-write - - - PULSE0E - No description available - 21 - 1 - read-write - - - PULSE1E - No description available - 20 - 1 - read-write - - - HOME2E - No description available - 19 - 1 - read-write - - - FAULTE - No description available - 18 - 1 - read-write - - - - - 4 - 0x10 - current,read,snap0,snap1 - COUNT[%s] - no description available - 0x30 - - z - Z counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ZCNT - zcnt value - 0 - 32 - read-write - - - - - ph - Phase counter - 0x4 - 32 - 0x00000000 - 0x461FFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 30 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 26 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 25 - 1 - read-only - - - PHCNT - phcnt value - 0 - 21 - read-only - - - - - spd - Speed counter - 0x8 - 32 - 0x00000000 - 0xEFFFFFFF - - - DIR - 1- reverse rotation -0- forward rotation - 31 - 1 - read-only - - - ASTAT - 1- a input is high -0- a input is low - 30 - 1 - read-only - - - BSTAT - 1- b input is high -0- b input is low - 29 - 1 - read-write - - - SPDCNT - spdcnt value - 0 - 28 - read-only - - - - - tmr - Timer counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TMRCNT - 32 bit free run timer - 0 - 32 - read-only - - - - - - zcmp2 - Z comparator - 0x80 - 32 - 0x80000000 - 0xFFFFFFFF - - - ZCMP2 - No description available - 0 - 32 - read-write - - - - - phcmp2 - Phase comparator - 0x84 - 32 - 0x80000000 - 0xFFFFFFFF - - - PHCMP2 - No description available - 0 - 32 - read-write - - - - - spdcmp2 - Speed comparator - 0x88 - 32 - 0x80000000 - 0xFFFFFFFF - - - SPDCMP2 - No description available - 0 - 32 - read-write - - - - - match_cfg - No description available - 0x8c - 32 - 0x00000000 - 0xFE00FE00 - - - ZCMPDIS - 1- postion compare not include zcnt - 31 - 1 - read-write - - - DIRCMPDIS - 1- postion compare not include rotation direction - 30 - 1 - read-write - - - DIRCMP - 0- position compare need positive rotation -1- position compare need negative rotation - 29 - 1 - read-write - - - SPDCMPDIS - No description available - 28 - 1 - read-write - - - PHASE_MATCH_DIS - No description available - 27 - 1 - read-write - - - POS_MATCH_DIR - No description available - 26 - 1 - read-write - - - POS_MATCH_OPT - No description available - 25 - 1 - read-write - - - ZCMP2DIS - No description available - 15 - 1 - read-write - - - DIRCMP2DIS - No description available - 14 - 1 - read-write - - - DIRCMP2 - No description available - 13 - 1 - read-write - - - SPDCMP2DIS - No description available - 12 - 1 - read-write - - - PHASE_MATCH_DIS2 - No description available - 11 - 1 - read-write - - - POS_MATCH2_DIR - No description available - 10 - 1 - read-write - - - POS_MATCH2_OPT - No description available - 9 - 1 - read-write - - - - - 6 - 0x4 - filt_cfg_a,filt_cfg_b,filt_cfg_z,filt_cfg_h,filt_cfg_h2,filt_cfg_f - FILT_CFG[%s] - no description available - 0x90 - 32 - 0x00001000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stable low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN - This bitfields defines the filter counter length. - 0 - 12 - read-write - - - - - qei_cfg - qei config register - 0x100 - 32 - 0x00000000 - 0xF00F1F3F - - - SW_PULSE0_RESTART - set to restart cycle counter for configed pulse_num. HW auto clear - 31 - 1 - read-write - - - SW_PULSE1_RESTART - No description available - 30 - 1 - read-write - - - SW_CYCLE0_RESTART - set to restart pulse counter for configed cycle_num. HW auto clear - 29 - 1 - read-write - - - SW_CYCLE1_RESTART - No description available - 28 - 1 - read-write - - - PULSE0_ONESHOT - set to use oneshot mode for configed pulse_num - 19 - 1 - read-write - - - PULSE1_ONESHOT - No description available - 18 - 1 - read-write - - - CYCLE0_ONESHOT - set to use oneshot mode for configed cycle_num - 17 - 1 - read-write - - - CYCLE1_ONESHOT - No description available - 16 - 1 - read-write - - - SPEED_DIR_CHG_EN - clear counter if detect direction change - 12 - 1 - read-write - - - TRIG_PULSE0_EN - set to enable trigger start cycle counter for configed pulse_num(from the selected edge) - 11 - 1 - read-write - - - TRIG_PULSE1_EN - No description available - 10 - 1 - read-write - - - TRIG_CYCLE0_EN - set to enable trigger start pulse counter for configed cycle_num - 9 - 1 - read-write - - - TRIG_CYCLE1_EN - No description available - 8 - 1 - read-write - - - UVW_POS_OPT0 - set to output next area position for QEO use; -clr to output exact point position for MMC use - 5 - 1 - read-write - - - NEGEDGE_EN - bit4: negedge enable -bit3: posedge enable -bit2: W in hal enable -bit1: signal b(or V in hal) enable -bit0: signal a(or U in hal) enable -such as: -01001: use posedge A -11010: use both edge of signal B -11111: use both edge of all HAL siganls - 4 - 1 - read-write - - - POSIDGE_EN - No description available - 3 - 1 - read-write - - - SIGZ_EN - No description available - 2 - 1 - read-write - - - SIGB_EN - No description available - 1 - 1 - read-write - - - SIGA_EN - No description available - 0 - 1 - read-write - - - - - pulse0_num - pulse0_num - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_NUM - for speed detection, will count the cycle number for configed pulse_num - 0 - 32 - read-write - - - - - pulse1_num - pulse1_num - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_NUM - No description available - 0 - 32 - read-write - - - - - cycle0_cnt - cycle0_cnt - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_CNT - No description available - 0 - 32 - read-only - - - - - cycle0pulse_cnt - cycle0pulse_cnt - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0PULSE_CNT - No description available - 0 - 32 - read-only - - - - - cycle1_cnt - cycle1_cnt - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_CNT - No description available - 0 - 32 - read-only - - - - - cycle1pulse_cnt - cycle1pulse_cnt - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1PULSE_CNT - No description available - 0 - 32 - read-only - - - - - cycle0_snap0 - cycle0_snap0 - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_SNAP0 - No description available - 0 - 32 - read-only - - - - - cycle0_snap1 - cycle0_snap1 - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_SNAP1 - No description available - 0 - 32 - read-only - - - - - cycle1_snap0 - cycle1_snap0 - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_SNAP0 - No description available - 0 - 32 - read-only - - - - - cycle1_snap1 - cycle1_snap1 - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_SNAP1 - No description available - 0 - 32 - read-only - - - - - cycle0_num - cycle0_num - 0x140 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE0_NUM - No description available - 0 - 32 - read-write - - - - - cycle1_num - cycle1_num - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYCLE1_NUM - No description available - 0 - 32 - read-write - - - - - pulse0_cnt - pulse0_cnt - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_CNT - No description available - 0 - 32 - read-only - - - - - pulse0cycle_cnt - pulse0cycle_cnt - 0x14c - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0CYCLE_CNT - No description available - 0 - 32 - read-only - - - - - pulse1_cnt - pulse1_cnt - 0x150 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_CNT - No description available - 0 - 32 - read-only - - - - - pulse1cycle_cnt - pulse1cycle_cnt - 0x154 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1CYCLE_CNT - No description available - 0 - 32 - read-only - - - - - pulse0_snap0 - pulse0_snap0 - 0x158 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse0cycle_snap0 - pulse0cycle_snap0 - 0x15c - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0CYCLE_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse0_snap1 - pulse0_snap1 - 0x160 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0_SNAP1 - No description available - 0 - 32 - read-only - - - - - pulse0cycle_snap1 - pulse0cycle_snap1 - 0x164 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE0CYCLE_SNAP1 - No description available - 0 - 32 - read-only - - - - - pulse1_snap0 - pulse1_snap0 - 0x168 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse1cycle_snap0 - pulse1cycle_snap0 - 0x16c - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1CYCLE_SNAP0 - No description available - 0 - 32 - read-only - - - - - pulse1_snap1 - pulse1_snap1 - 0x170 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1_SNAP1 - No description available - 0 - 32 - read-only - - - - - pulse1cycle_snap1 - pulse1cycle_snap1 - 0x174 - 32 - 0x00000000 - 0xFFFFFFFF - - - PULSE1CYCLE_SNAP1 - No description available - 0 - 32 - read-only - - - - - timestamp - timestamp - 0x1e0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP - for SIN/COS mode, it saves the timestampe of the begining of first ADC sample time; -for ABZ mode, it saves the timestampe of edge of input signals - 0 - 32 - read-only - - - - - adc_threshold - adc_threshold - 0x1f0 - 32 - 0x0000FFFF - 0xFFFFFFFF - - - LOW_LIMIT - for SINCOS mode, if (max+min/2) of the two adc result, is small than limit, -then this value is treated as unvalid, no position output. -this is uesd to avoid wrong adc resule(such as 0 or same sin cos value) - 16 - 16 - read-write - - - HIGH_LIMIT - high limit for SINCOS mode adc result - 0 - 16 - read-write - - - - - adcx_cfg0 - adcx_cfg0 - 0x200 - 32 - 0x00000000 - 0x0000019F - - - X_ADCSEL - No description available - 8 - 1 - read-write - - - X_ADC_ENABLE - No description available - 7 - 1 - read-write - - - X_CHAN - No description available - 0 - 5 - read-write - - - - - adcx_cfg1 - adcx_cfg1 - 0x204 - 32 - 0x00004000 - 0xFFFFFFFF - - - X_PARAM1 - No description available - 16 - 16 - read-write - - - X_PARAM0 - No description available - 0 - 16 - read-write - - - - - adcx_cfg2 - adcx_cfg2 - 0x208 - 32 - 0x80000000 - 0xFFFFFFFF - - - X_OFFSET - No description available - 0 - 32 - read-write - - - - - adcy_cfg0 - adcy_cfg0 - 0x210 - 32 - 0x00000000 - 0x0000019F - - - Y_ADCSEL - No description available - 8 - 1 - read-write - - - Y_ADC_ENABLE - No description available - 7 - 1 - read-write - - - Y_CHAN - No description available - 0 - 5 - read-write - - - - - adcy_cfg1 - adcy_cfg1 - 0x214 - 32 - 0x40000000 - 0xFFFFFFFF - - - Y_PARAM1 - No description available - 16 - 16 - read-write - - - Y_PARAM0 - No description available - 0 - 16 - read-write - - - - - adcy_cfg2 - adcy_cfg2 - 0x218 - 32 - 0x80000000 - 0xFFFFFFFF - - - Y_OFFSET - No description available - 0 - 32 - read-write - - - - - cal_cfg - cal_cfg - 0x220 - 32 - 0x00000100 - 0x00FFFFFF - - - XY_DELAY - valid x/y delay, larger than this delay will be treated as invalid data. -Default 1.25us@200MHz; max 80ms; - 0 - 24 - read-write - - - - - phase_param - phase_param - 0x230 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - PHASE_PARAM - No description available - 0 - 32 - read-write - - - - - pos_threshold - pos_threshold - 0x238 - 32 - 0x80000000 - 0xFFFFFFFF - - - POS_THRESHOLD - No description available - 0 - 32 - read-write - - - - - 6 - 0x4 - uvw_pos0,uvw_pos1,uvw_pos2,uvw_pos3,uvw_pos4,uvw_pos5 - UVW_POS[%s] - no description available - 0x240 - 32 - 0x00000000 - 0xFFFFFFFF - - - UVW_POS0 - No description available - 0 - 32 - read-write - - - - - 6 - 0x4 - uvw_pos0_cfg,uvw_pos1_cfg,uvw_pos2_cfg,uvw_pos3_cfg,uvw_pos4_cfg,uvw_pos5_cfg - UVW_POS_CFG[%s] - no description available - 0x258 - 32 - 0x00000000 - 0x0000007F - - - POS_EN - No description available - 6 - 1 - read-write - - - U_POS_SEL - No description available - 4 - 2 - read-write - - - V_POS_SEL - No description available - 2 - 2 - read-write - - - W_POS_SEL - No description available - 0 - 2 - read-write - - - - - phase_cnt - phase_cnt - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - PHASE_CNT - No description available - 0 - 32 - read-write - - - - - phase_update - phase_update - 0x284 - 32 - 0x00000000 - 0xFFFFFFFF - - - INC - set to add value to phase_cnt - 31 - 1 - write-only - - - DEC - set to minus value from phase_cnt(set inc and dec same time willl act inc) - 30 - 1 - write-only - - - VALUE - value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation - 0 - 30 - write-only - - - - - position - position - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSITION - No description available - 0 - 32 - read-write - - - - - position_update - position_update - 0x28c - 32 - 0x00000000 - 0xFFFFFFFF - - - INC - set to add value to position - 31 - 1 - write-only - - - DEC - set to minus value from position(set inc and dec same time willl act inc) - 30 - 1 - write-only - - - VALUE - value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation - 0 - 30 - write-only - - - - - angle - No description available - 0x290 - 32 - 0x00000000 - 0xFFFFFFFF - - - ANGLE - No description available - 0 - 32 - read-only - - - - - pos_timeout - pos_timeout - 0x294 - 32 - 0x7FFFFFFF - 0xFFFFFFFF - - - ENABLE - enable position timeout feature, if timeout, send valid again - 31 - 1 - read-write - - - TIMEOUT - postion timeout value - 0 - 31 - read-write - - - - - - - QEI1 - QEI1 - QEIV2 - 0xf0404000 - - - QEI2 - QEI2 - QEIV2 - 0xf0408000 - - - QEI3 - QEI3 - QEIV2 - 0xf040c000 - - - QEO0 - QEO0 - QEOV2 - 0xf0410000 - - 0x0 - 0x21c - registers - - - - WAVE_mode - analog waves mode - 0x0 - 32 - 0x00000000 - 0xFFFFFFF7 - - - WAVE2_ABOVE_MAX_LIMIT - wave2 above max limit mode. -0: output all bits are 1. -1: output 0x0. -2: output as level_max_limit2.level0_max_limit - 30 - 2 - read-write - - - WAVE2_HIGH_AREA1_LIMIT - wave2 high area1 limit mode. -0: output all bits are 1. -1: output as level_max_limit2.level0_max_limit - 29 - 1 - read-write - - - WAVE2_HIGH_AREA0_LIMIT - wave2 high area0 limit mode. -0: output all bits are 1. -1: output as level_max_limit2.level0_max_limit - 28 - 1 - read-write - - - WAVE2_LOW_AREA1_LIMIT - wave2 low area1 limit mode. -0: output 0. -1: output as level_min_limit2.level1_min_limit - 27 - 1 - read-write - - - WAVE2_LOW_AREA0_LIMIT - wave2 low area0 limit mode. -0: output 0. -1: output as level_min_limit2.level1_min_limit - 26 - 1 - read-write - - - WAVE2_BELOW_MIN_LIMIT - wave2 below min limit mode. -0: output 0. -1: output all bits are 1. -2: output as level_min_limit2.level1_min_limit - 24 - 2 - read-write - - - WAVE1_ABOVE_MAX_LIMIT - wave1 above max limit mode. -0: output all bits are 1. -1: output 0x0. -2: output as level_max_limit1.level0_max_limit - 22 - 2 - read-write - - - WAVE1_HIGH_AREA1_LIMIT - wave1 high area1 limit mode. -0: output all bits are 1. -1: output as level_max_limit1.level0_max_limit - 21 - 1 - read-write - - - WAVE1_HIGH_AREA0_LIMIT - wave1 high area0 limit mode. -0: output all bits are 1. -1: output as level_max_limit1.level0_max_limit - 20 - 1 - read-write - - - WAVE1_LOW_AREA1_LIMIT - wave1 low area1 limit mode. -0: output 0. -1: output as level_min_limit1.level1_min_limit - 19 - 1 - read-write - - - WAVE1_LOW_AREA0_LIMIT - wave1 low area0 limit mode. -0: output 0. -1: output as level_min_limit1.level1_min_limit - 18 - 1 - read-write - - - WAVE1_BELOW_MIN_LIMIT - wave1 below min limit mode. -0: output 0. -1: output all bits are 1. -2: output as level_min_limit1.level1_min_limit - 16 - 2 - read-write - - - WAVE0_ABOVE_MAX_LIMIT - wave0 above max limit mode. -0: output all bits are 1. -1: output 0x0. -2: output as level_max_limit0.level0_max_limit - 14 - 2 - read-write - - - WAVE0_HIGH_AREA1_LIMIT - wave0 high area1 limit mode. -0: output all bits are 1. -1: output as level_max_limit0.level0_max_limit - 13 - 1 - read-write - - - WAVE0_HIGH_AREA0_LIMIT - wave0 high area0 limit mode. -0: output all bits are 1. -1: output as level_max_limit0.level0_max_limit - 12 - 1 - read-write - - - WAVE0_LOW_AREA1_LIMIT - wave0 low area1 limit mode. -0: output 0. -1: output as level_min_limit0.level1_min_limit - 11 - 1 - read-write - - - WAVE0_LOW_AREA0_LIMIT - wave0 low area0 limit mode. -0: output 0. -1: output as level_min_limit0.level1_min_limit - 10 - 1 - read-write - - - WAVE0_BELOW_MIN_LIMIT - wave0 below min limit mode. -0: output 0. -1: output all bits are 1. -2: output as level_min_limit0.level1_min_limit - 8 - 2 - read-write - - - SADDLE_TYPE - saddle type seclect; -0:standard saddle. -1: triple-cos saddle. - 7 - 1 - read-write - - - ENABLE_DQ_VALID - enable vd or vq valid to trigger analog wave calcuation -0: disable. -1: enable. - 6 - 1 - read-write - - - ENABLE_POS_VALID - enable position valid to trigger analog wave calcuation -0: disable. -1: enable. - 5 - 1 - read-write - - - EN_WAVE_VD_VQ_INJECT - wave VdVq inject enable. -0: disable VdVq inject. -1: enable VdVq inject. - 4 - 1 - read-write - - - VD_VQ_SEL - vd_vq sel ctrl: -0: from CLC. -1: from software. - 2 - 1 - read-write - - - WAVES_OUTPUT_TYPE - wave0/1/2 output mode. -0: cosine wave. -1: saddle wave. -2. abs cosine wave. -3. saw wave - 0 - 2 - read-write - - - - - WAVE_resolution - resolution of wave0/1/2 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINES - wave0/1/2 resolution - 0 - 32 - read-write - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_PHASE_SHIFT[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period - 0 - 32 - read-write - - - - - WAVE_vd_inject - wave vd inject value - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VD_VAL - Vd inject value - 0 - 32 - read-write - - - - - WAVE_vq_inject - wave vq inject value - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - VQ_VAL - Vq inject value - 0 - 32 - read-write - - - - - WAVE_vd_vq_load - load wave0/1/2 vd vq value - 0x2c - 32 - 0x00000000 - 0x00000001 - - - LOAD - load wave0/1/2 vd vq value. always read 0 -0: vd vq keep previous value. -1: load wave0/1/2 vd vq value at sametime. - 0 - 1 - write-only - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_AMPLITUDE[%s] - no description available - 0x30 - 32 - 0x00000000 - 0x0001FFFF - - - EN_SCAL - enable wave amplitude scaling. 0: disable; 1: enable - 16 - 1 - read-write - - - AMP_VAL - amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. - 0 - 16 - read-write - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_MID_POINT[%s] - no description available - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. - 0 - 32 - read-write - - - - - 3 - 0x8 - wave0,wave1,wave2 - WAVE_LIMIT0[%s] - no description available - 0x48 - - min_level0 - wave0 low area limit value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT_LEVEL0 - low area limit level0 - 0 - 32 - read-write - - - - - max_level0 - wave0 high area limit value - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - LIMIT_LEVEL0 - high area limit level0 - 0 - 32 - read-write - - - - - - 3 - 0x8 - wave0,wave1,wave2 - WAVE_LIMIT1[%s] - no description available - 0x60 - - min_level1 - wave0 low area limit value level1 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LIMIT_LEVEL1 - low area limit level1 - 0 - 32 - read-write - - - - - max_level1 - wave0 high area limit value level1 - 0x4 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - LIMIT_LEVEL1 - high area limit level1 - 0 - 32 - read-write - - - - - - 3 - 0x4 - wave0,wave1,wave2 - WAVE_DEADZONE_SHIFT[%s] - no description available - 0x78 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - wave0 deadzone shifter value - 0 - 32 - read-write - - - - - WAVE_pwm_cycle - pwm_cycle - 0x84 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - pwm_cycle - 0 - 32 - read-write - - - - - ABZ_mode - wave_a/b/z output mode - 0x100 - 32 - 0x00000000 - 0x99111333 - - - ABZ_OUTPUT_ENABLE - abz output enable： -0：abz output disable, all keep 0 -1：abz output enable. - 31 - 1 - read-write - - - REVERSE_EDGE_TYPE - pulse reverse wave，reverse edge point: -0: between pulse's posedge and negedge, min period dedicated by the num line_width -1: edge change point flow pulse's negedge. - 28 - 1 - read-write - - - POSITION_SYNC_MODE - position sync mode: -0: only sync integer line part into qeo own position. -1: sync integer and fraction part into qeo own position. - 27 - 1 - read-write - - - EN_WDOG - enable abz wdog: -0: disable abz wdog. -1: enable abz wdog. - 24 - 1 - read-write - - - Z_POLARITY - wave_z polarity. -0: normal output. -1: invert normal output - 20 - 1 - read-write - - - B_POLARITY - wave_b polarity. -0: normal output. -1: invert normal output - 16 - 1 - read-write - - - A_POLARITY - wave_a polarity. -0: normal output. -1: invert normal output - 12 - 1 - read-write - - - Z_TYPE - wave_z type: -0: zero pulse type, start and end line number decided by z_start、z_end and z_offset. -1: zero pulse type, z output start to high when position= z_start, and mantain numbers of 1/4 line cfg in z_pulse_width register -2: reserved -3: wave_z output as tree-phase wave same as wave_a/wave_b - 8 - 2 - read-write - - - B_TYPE - wave_b type: -0: Two-phase orthogonality wave_b. -1: reverse wave of pulse/reverse type. -2: down wave of up/down type. -3: Three-phase orthogonality wave_b. - 4 - 2 - read-write - - - A_TYPE - wave_a type: -0: Two-phase orthogonality wave_a. -1: pulse wave of pulse/reverse type. -2: up wave of up/down type. -3: Three-phase orthogonality wave_a. - 0 - 2 - read-write - - - - - ABZ_resolution - resolution of wave_a/b/z - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINES - wave_a/b/z resolution - 0 - 32 - read-write - - - - - 3 - 0x4 - a,b,z - ABZ_PHASE_SHIFT[%s] - no description available - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period. - 0 - 32 - read-write - - - - - ABZ_line_width - Two-phase orthogonality wave 1/4 period - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINE - the num of system clk by 1/4 period when using as Two-phase orthogonality. - 0 - 32 - read-write - - - - - ABZ_wdog_width - wdog width of qeo - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - WIDTH - wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. - 0 - 32 - read-write - - - - - ABZ_postion_sync - sync abz owned postion - 0x11c - 32 - 0x00000000 - 0x00000001 - - - POSTION - load next valid postion into abz owned postion. always read 0 -0: sync abz owned postion with next valid postion. -1: not sync. - 0 - 1 - write-only - - - - - ABZ_overall_offset - abz overall position offset - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - abz position overall offset, it affects abz position before resolution convert - 0 - 32 - read-write - - - - - ABZ_z_start - zero phase start line num - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - Z_START - number of Z start line - 0 - 32 - read-write - - - - - ABZ_z_end - zero phase end line num - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - Z_END - number of Z end line - 0 - 32 - read-write - - - - - ABZ_z_offset - zero phase start and end 1/4 line num - 0x12c - 32 - 0x00000000 - 0x00000330 - - - Z_END_OFFSET - number of Z end 1/4 line - 8 - 2 - read-write - - - Z_START_OFFSET - number of Z start 1/4 line - 4 - 2 - read-write - - - - - ABZ_z_pulse_width - zero pulse witdth - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - number of z_pulse_width - 0 - 32 - read-write - - - - - PWM_mode - pwm mode - 0x140 - 32 - 0x00000000 - 0xFFFF831F - - - PWM7_SAFETY - PWM safety mode phase table - 30 - 2 - read-write - - - PWM6_SAFETY - PWM safety mode phase table - 28 - 2 - read-write - - - PWM5_SAFETY - PWM safety mode phase table - 26 - 2 - read-write - - - PWM4_SAFETY - PWM safety mode phase table - 24 - 2 - read-write - - - PWM3_SAFETY - PWM safety mode phase table - 22 - 2 - read-write - - - PWM2_SAFETY - PWM safety mode phase table - 20 - 2 - read-write - - - PWM1_SAFETY - PWM safety mode phase table - 18 - 2 - read-write - - - PWM0_SAFETY - PWM safety mode phase table - 16 - 2 - read-write - - - ENABLE_PWM - enable PWM force output -0: disable -1: enable - 15 - 1 - read-write - - - PWM_ENTER_SAFETY_MODE - PWM enter safety mode -0: not enter -1: enter - 9 - 1 - read-write - - - PWM_SAFETY_BYPASS - PWM safety mode bypass -0: not bypass -1: bypass - 8 - 1 - read-write - - - REVISE_UP_DN - exchange PWM pairs’ output -0: not exchange. -1: exchange. - 4 - 1 - read-write - - - PHASE_NUM - pwm force phase number. - 0 - 4 - read-write - - - - - PWM_resolution - resolution of pwm - 0x144 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINES - pwm resolution - 0 - 32 - read-write - - - - - 4 - 0x4 - a,b,c,d - PWM_PHASE_SHIFT[%s] - no description available - 0x148 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period - 0 - 32 - read-write - - - - - 24 - 0x4 - posedge0,posedge1,posedge2,posedge3,posedge4,posedge5,posedge6,posedge7,posedge8,posedge9,posedge10,posedge11,negedge0,negedge1,negedge2,negedge3,negedge4,negedge5,negedge6,negedge7,negedge8,negedge9,negedge10,negedge11 - PWM_PHASE_TABLE[%s] - no description available - 0x158 - 32 - 0x00000000 - 0x0000FFFF - - - PWM7 - pwm phase table value - 14 - 2 - read-write - - - PWM6 - pwm phase table value - 12 - 2 - read-write - - - PWM5 - pwm phase table value - 10 - 2 - read-write - - - PWM4 - pwm phase table value - 8 - 2 - read-write - - - PWM3 - pwm phase table value - 6 - 2 - read-write - - - PWM2 - pwm phase table value - 4 - 2 - read-write - - - PWM1 - pwm phase table value - 2 - 2 - read-write - - - PWM0 - pwm phase table value - 0 - 2 - read-write - - - - - PWM_postion_software - softwave inject postion - 0x1f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSTION_SOFTWAVE - softwave inject postion - 0 - 32 - read-write - - - - - PWM_postion_sel - select softwave inject postion - 0x1fc - 32 - 0x00000000 - 0x00000001 - - - POSTION_SEL - enable softwave inject postion. -0: disable. -1: enable. - 0 - 1 - read-write - - - - - PWM_status - qeo status - 0x200 - 32 - 0x00000000 - 0xFFFF0001 - - - PWM_FOURCE - qeo_pwm_force observe - 16 - 16 - read-only - - - PWM_SAFETY - pwm_fault status - 0 - 1 - read-only - - - - - PWM_debug0 - qeo debug 0 - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_DAC0 - wave0 - 0 - 32 - read-only - - - - - PWM_debug1 - qeo debug 1 - 0x208 - 32 - 0x00000000 - 0x11110000 - - - QEO_FINISH - qeo finish observe - 28 - 1 - read-only - - - PAD_Z - pad_z observe - 24 - 1 - read-only - - - PAD_B - pad_b observe - 20 - 1 - read-only - - - PAD_A - pad_a observe - 16 - 1 - read-only - - - - - PWM_debug2 - qeo debug 2 - 0x20c - 32 - 0x00000000 - 0xFFFFFFFF - - - ABZ_OWN_POSTION - abz_own_postion observe - 0 - 32 - read-only - - - - - PWM_debug3 - qeo debug 3 - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - ABZ_OWN_POSTION - abz_own_postion observe - 0 - 32 - read-only - - - - - PWM_debug4 - qeo debug 4 - 0x214 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_DAC1 - wave1 - 0 - 32 - read-only - - - - - PWM_debug5 - qeo debug 5 - 0x218 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_DAC2 - wave2 - 0 - 32 - read-only - - - - - - - QEO1 - QEO1 - QEOV2 - 0xf0414000 - - - QEO2 - QEO2 - QEOV2 - 0xf0418000 - - - QEO3 - QEO3 - QEOV2 - 0xf041c000 - - - PWM0 - PWM0 - PWMV2 - 0xf0420000 - - 0x0 - 0x980 - registers - - - - work_ctrl0 - No description available - 0x0 - 32 - 0x00000000 - 0x80000000 - - - SHADOW_UNLOCK - write 0x… first to unlock, then set related bits in unlock_sel to unlock following shadow registers(from 0x04 to 0x78), -otherwise the shadow registers can not be written. -The shadow registers will be loaded to work registers only when shadow_lock is 1 or lock is not enabled -This bit can be cleared by set shadow_lock bit in work_ctrl1 - 31 - 1 - read-write - - - - - unlock - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK_BIT - bit2 to bit 29 for value_shadow, bit30 for force_mode -the shadow registers can be updated only when related unlock_bit is set; -this register can only be updated after unlock - 0 - 32 - read-write - - - - - 28 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27 - SHADOW_VAL[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - shadow registers, if used as reload or compare point, shall be 24bit clock cycles plus 1bit half cycle and 7bit high-resolution delay - 0 - 32 - read-write - - - - - force_mode - No description available - 0x78 - 32 - 0x00000000 - 0x00FFFFFF - - - POLARITY - one bit for one pwm channel, it's used as shadow register when pwm_cfg0.polarity_opt0 is set. -output polarity, set to 1 will invert the output(after pwm selection, pair mode, dead area insertion, before force/fault) - 16 - 8 - read-write - - - FORCE_MODE - 2bit for each PWM channel(0~7); -00: force output 0 -01: force output 1 -10: output highz(pad_oe_*=0) -11: no force -this field may be changed by software as shadow register , the update time should be defined by chan_cfg.load, only for PWM channels. - 0 - 16 - read-write - - - - - work_ctrl1 - No description available - 0x7c - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW_LOCK - one to lock, sofware can't write any shadow registers -Software have to write 0x…. to work_ctrl0 to clear this bit. - 31 - 1 - read-write - - - - - 8 - 0x10 - 0,1,2,3,4,5,6,7 - PWM[%s] - no description available - 0x100 - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x01000F77 - - - TRIG_SEL4 - for N=0/2/4/6, clear to select 2 compare point(N*2~N*2+1); -set to select 4 compare point(N*2~N*2+3); -or use 2 compare point(N*2+2~N*2+3); -for N=1/3/5/7, this bit is no means, it can work on pair mode, or use 2 compare point (N*2+2~N*2+3); -assume select ab or abcd, abcd can between 0 and 2T. -output will be 1 when counter value between a and b; -if b<=a then output all 0; if b>=(T+a), then output all 1; - 24 - 1 - read-write - - - FAULT_SEL_ASYNC - select from 16bit async fault from pad - 8 - 4 - read-write - - - FAULT_POL_ASYNC - fault polarity for input fault from pad, 1-active low; 0-active high; - 6 - 1 - read-write - - - FAULT_EN_ASYNC - set to enable the input async faults from pad directly - 5 - 1 - read-write - - - FAULT_EN_SYNC - set to enable the input faults from trig_mux(trigger_in[0] for channel0/1, 1 for 23, 2 for 45, 3 for 67) - 4 - 1 - read-write - - - POL_UPDATE_SEL - used when polarity_opt0 is set, define when to update polarity working register. -0: software set work_ctrl1.shadow_lock bit -1: update at reload point; - 2 - 1 - read-write - - - OUT_POLARITY - output polarity, set to 1 will invert the output(after pwm selection, pair mode, dead area insertion, before force/fault) -when polarity_opt0 is set, this bit is controlled by shadow register, can't be writable; read as working register -use compare channel settings(in cmp_cfg) as shadow register update - 1 - 1 - read-write - - - POLARITY_OPT0 - set to use shadow polarity - 0 - 1 - read-write - - - - - cfg1 - No description available - 0x4 - 32 - 0x00000000 - 0x1FFF7777 - - - HIGHZ_EN_N - 0 to highz pwm outputs(pad_oe*=0), software need set this bit to 1 to enable pwm output - 28 - 1 - read-write - - - FORCE_UPDATE_TIME - define when to use the shadow register value for working register(force_mode) -00: software set work_ctrl1.shadow_lock bit -01: use the related counter rld_cmp_sel0 and rld_cmp_sel1, to select one compare point -10: related counter reload time(selected by pwm_cnt) -11: use force_trig_sel to select one of the input trigger -NOTE: 00/01 are not recommended since the update time is not controllable, may cause error in complex application. -00 is used for initialization or debug, not suggest for real time update - 26 - 2 - read-write - - - FAULT_MODE - 00: force output 0 -01: force output 1 -1x: output highz(pad_oe_*=0) - 24 - 2 - read-write - - - FAULT_REC_TIME - 00: immediately -01: after main counter reload time -10: use fault_rec_sel to select one of the input trigger -11: software write fault_clear in glb_ctrl2, no effort if pwm_fault is still assert - 22 - 2 - read-write - - - SW_FORCE_EN - 0 for hardware force, from trig_mux selected by pwm_force_sel -1 for software force, from glb_ctrl.sw_force - 21 - 1 - read-write - - - PAIR_MODE - if set to 1, PWM work at pair mode, -pwm_cfg for channel 2m is used for channel 2m+1(m=0,1,2,3), -except the dead area, which is separate for each channel even in pair mode -software need set this bit for both channel of one pair, otherwise result unknown. - 20 - 1 - read-write - - - PWM_LOGIC - valid only for pwm0/2/4/6 when trig_sel4 is set -00: ab OR cd; -01: ab AND cd; -10: ab XOR cd; -11: cd - 18 - 2 - read-write - - - FORCE_TIME - 00: force immediately -01: force at main counter reload time -10: force at trig signal selected by force_act_sel -11: no force -the force assert/deassert will happen at the force_time; -qeo force and value also latched at this time - 16 - 2 - read-write - - - FORCE_TRIG_SEL - select one trigger from 8, should set to pulse in trig_mux, will load shadow register(force)mode) to force_mode_work at this time - 12 - 3 - read-write - - - FORCE_ACT_SEL - select one trigger from 8, should set to pulse in trig_mux, will load hw/sw force at this time - 8 - 3 - read-write - - - PWM_FORCE_SEL - select one trigger from 8 as force signal, should be level signal, 1 for force active, 0 for no force - 4 - 3 - read-write - - - FAULT_REC_SEL - select one trigger from 8, should set to pulse in trig_mux, used for fault recovery if fault_rec_time is set to 2'b10 - 0 - 3 - read-write - - - - - dead_area - No description available - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - DEAD_AREA - 16bit cycle delay plus 8bit hr_delay -min value is 2 cycles, less than 0x200 will be treated as no dead area; -NOTE: dead insertion must be configured with pair, that is, for pwm 01/23/45/67. -otherwise the result maybe UNKNOWN!!! - 0 - 24 - read-write - - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - TRIGGER_CFG[%s] - no description available - 0x180 - 32 - 0x00000000 - 0x0000001F - - - TRIGGER_OUT_SEL - select one from 24 compare result as trigger out, set at compare point, clear at reload point. - 0 - 5 - read-write - - - - - glb_ctrl - No description available - 0x1f0 - 32 - 0x00000000 - 0x00FF0318 - - - SW_FORCE - software write 1 to start software force, if the pwm_cfg<n>.sw_force_en is set, force will take effort - 16 - 8 - read-write - - - OUTPUT_DELAY - add delay after dead_area insertiong logic, for hr_pwm - 8 - 2 - read-write - - - HR_PWM_EN - set to enable hr pwm, clear to bypass delay chain. - 4 - 1 - read-write - - - FRAC_DISABLE - set to disable bit[7:0] in DAC value when Calculation Unit use it. - 3 - 1 - read-write - - - - - glb_ctrl2 - No description available - 0x1f4 - 32 - 0x00000000 - 0x0F20FF01 - - - DAC_SW_MODE - set for software DAC mode, software can write dac_value*_sv directly, and dac_valid from moto system is ignored - 24 - 4 - read-write - - - DEBUG_IN_EN - set to enable debug_in signal as fault signal, generally disable pwm output - 21 - 1 - read-write - - - FAULT_CLEAR - software write 1 to clear fault event if pwm_cfg.fault_rec_time is 2'b11. -software need to clear it after the fault signal is de-assert and before next fault -one bit for one pwm channel - 8 - 8 - read-write - - - SHADOW_LOCK_EN - enable shadow_lock feature, if cleared, shadow_lock will be always 0 - 0 - 1 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - CNT_RELOAD_WORK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - counter0 reload working register - 0 - 32 - read-only - - - - - 24 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP_VAL_WORK[%s] - no description available - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - compare point working register - 0 - 32 - read-only - - - - - force_work - No description available - 0x27c - 32 - 0x00000000 - 0x00FFFFFF - - - OUT_POLARITY - force working register - 16 - 8 - read-only - - - FORCE_MODE - force_mode work register - 0 - 16 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - CNT_VAL[%s] - no description available - 0x2a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - main counter value - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - DAC_VALUE_SV[%s] - no description available - 0x2b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - save dac0_value when dac0_valid if dac_sw_mode is 0; -software write dac_value directly if dac_sw_mode is 1 - 0 - 32 - read-write - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - CAPTURE_POS[%s] - no description available - 0x300 - 32 - 0x00000000 - 0xFFFFFF13 - - - CAPTURE_POS - related counter value captured at input negedge - 8 - 24 - read-only - - - CAPTURE_SELGPIO - 0: result from CAP[ 7:0], from trgm -1: result from CAP[15:8], from gpio - 4 - 1 - read-write - - - CNT_INDEX - related counter - 0 - 2 - read-write - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - CAPTURE_NEG[%s] - no description available - 0x380 - 32 - 0x00000000 - 0xFFFFFF00 - - - CAPTURE_NEG - counter value captured at input negedge - 8 - 24 - read-only - - - - - irq_sts - No description available - 0x400 - 32 - 0x00000000 - 0x8000003F - - - IRQ_CAL_OVERFLOW - end of output burst - 31 - 1 - write-only - - - IRQ_BURSTEND - end of output burst - 5 - 1 - read-only - - - IRQ_FAULT - for external fault event - 4 - 1 - read-only - - - IRQ_CAPTURE_NEG - capture negedge status - 3 - 1 - read-only - - - IRQ_CAPTURE_POS - capture posedge status - 2 - 1 - read-only - - - IRQ_RELOAD - when clock counter reach the reload time - 1 - 1 - read-only - - - IRQ_CMP - for 24 channel, compare event - 0 - 1 - read-only - - - - - irq_en - No description available - 0x404 - 32 - 0x00000000 - 0x80000000 - - - IRQ_EN_OVERFLOW - enable interrupt when calculation unit overflow - 31 - 1 - read-write - - - - - irq_sts_cmp - No description available - 0x410 - 32 - 0x00000000 - 0x00FFFFFF - - - IRQ_STS_CMP - interrupt flag for compare point match event, and each bit means one compare point. - 0 - 24 - write-only - - - - - irq_sts_reload - No description available - 0x414 - 32 - 0x00000000 - 0x0000000F - - - IRQ_STS_RELOAD - interrupt flag for reload event , and each bit means one main counter. - 0 - 4 - write-only - - - - - irq_sts_cap_pos - No description available - 0x418 - 32 - 0x00000000 - 0x000000FF - - - IRQ_STS_CAP_POS - interrupt flag for posedge capture event , and each bit means one capture channel. - 0 - 8 - write-only - - - - - irq_sts_cap_neg - No description available - 0x41c - 32 - 0x00000000 - 0x000000FF - - - IRQ_STS_CAP_NEG - interrupt flag for negedge capture event , and each bit means one capture channel. - 0 - 8 - write-only - - - - - irq_sts_fault - No description available - 0x420 - 32 - 0x00000000 - 0x000000FF - - - IRQ_STS_FAULT - interrupt flag for external fault event , and each bit means one external fault channel. - 0 - 8 - write-only - - - - - irq_sts_burstend - No description available - 0x424 - 32 - 0x00000000 - 0x0000000F - - - IRQ_STS_BURSTEND - interrupt flag for output burst done event , and each bit means one main counter. - 0 - 4 - write-only - - - - - irq_en_cmp - No description available - 0x430 - 32 - 0x00000000 - 0x00FFFFFF - - - IRQ_EN_CMP - interrupt enable field for compare point match event, and each bit means one compare point. - 0 - 24 - read-write - - - - - irq_en_reload - No description available - 0x434 - 32 - 0x00000000 - 0x0000000F - - - IRQ_EN_RELOAD - interrupt enable field for reload event , and each bit means one main counter. - 0 - 4 - read-write - - - - - irq_en_cap_pos - No description available - 0x438 - 32 - 0x00000000 - 0x000000FF - - - IRQ_EN_CAP_POS - interrupt enable field for posedge capture event , and each bit means one capture channel. - 0 - 8 - read-write - - - - - irq_en_cap_neg - No description available - 0x43c - 32 - 0x00000000 - 0x000000FF - - - IRQ_EN_CAP_NEG - interrupt enable field for negedge capture event , and each bit means one capture channel. - 0 - 8 - read-write - - - - - irq_en_fault - No description available - 0x440 - 32 - 0x00000000 - 0x000000FF - - - IRQ_EN_FAULT - interrupt enable field for external fault event , and each bit means one external fault channel. - 0 - 8 - read-write - - - - - irq_en_burstend - No description available - 0x444 - 32 - 0x00000000 - 0x0000000F - - - IRQ_EN_BURSTEND - interrupt enable field for output burst done event , and each bit means one main counter. - 0 - 4 - read-write - - - - - dma_en - No description available - 0x480 - 32 - 0x00000000 - 0x9F9F9F9F - - - DMA3_EN - enable dma3 - 31 - 1 - read-write - - - DMA3_SEL - selelct one of compare point(0~23) or one reload point(24~27) as dma0 - 24 - 5 - read-write - - - DMA2_EN - enable dma2 - 23 - 1 - read-write - - - DMA2_SEL - selelct one of compare point(0~23) or one reload point(24~27) as dma0 - 16 - 5 - read-write - - - DMA1_EN - enable dma1 - 15 - 1 - read-write - - - DMA1_SEL - selelct one of compare point(0~23) or one reload point(24~27) as dma0 - 8 - 5 - read-write - - - DMA0_EN - enable dma0 - 7 - 1 - read-write - - - DMA0_SEL - selelct one of compare point(0~23) or one reload point(24~27) as dma0 - 0 - 5 - read-write - - - - - 4 - 0x10 - 0,1,2,3 - CNT[%s] - no description available - 0x500 - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x1F1F731F - - - RLD_CMP_SEL1 - select one compare point from 24, set to 0x1F to disable current selection, used for reload value, compare value, force value update - 24 - 5 - read-write - - - RLD_CMP_SEL0 - select one compare point from 24, set to 0x1F to disable current selection - 16 - 5 - read-write - - - RLD_TRIG_SEL - select one trigger from 8, should set to pulse in trig_mux - 12 - 3 - read-write - - - RLD_UPDATE_TIME - define when to use the calculation output value as reload time -00: software set work_ctrl1.shadow_lock bit -01: use compare point selected by rld_cmp_sel0 or rld_cmp_sel1 -10: counter reload time -11: use rld_trig_sel to select one of the input trigger -NOTE: 00 is not recommended since the update time is not controllable, may cause error in complex application. - 8 - 2 - read-write - - - CNT_D_PARAM - input dac data parameter - 0 - 5 - read-write - - - - - cfg1 - No description available - 0x4 - 32 - 0x00000000 - 0x039F9F1F - - - CNT_DAC_INDEX - select one of the dac value - 24 - 2 - read-write - - - CNT_LU_EN - set to enable up limit, use cnt_lu_off to select one of the shadow register value as limitation - 23 - 1 - read-write - - - CNT_LIM_UP - up limit offset selection, from one of the shadow_val - 16 - 5 - read-write - - - CNT_LL_EN - set to enable low limit - 15 - 1 - read-write - - - CNT_LIM_LO - low limit offset selection, from one of the shadow_val - 8 - 5 - read-write - - - CNT_IN_OFF - input data offset selection, from one of the shadow_val, default just shadow reload time - 0 - 5 - read-write - - - - - cfg2 - No description available - 0x8 - 32 - 0x00000000 - 0x8778F78F - - - CNT_RELOAD_EN - set to use input signal(selected by cnt_reload_trig) to reload timer - 31 - 1 - read-write - - - CNT_RELOAD_TRIG - select one trigger from 8, should set to pulse in trig_mux - 24 - 3 - read-write - - - CNT_UPDATE_TRIG1 - select one trigger from 8, should set to pulse in trig_mux - 20 - 3 - read-write - - - CNT_UPDATE_EN1 - set to enable using trig1 to load calculation cell output to counter - 19 - 1 - read-write - - - CNT_TRIG1 - change counter value to one of the calculation cell output when cnt_update_triger1 issued - 12 - 4 - read-write - - - CNT_UPDATE_TRIG0 - select one trigger from 8, should set to pulse in trig_mux - 8 - 3 - read-write - - - CNT_UPDATE_EN0 - set to enable using trig0 to load calculation cell output to counter - 7 - 1 - read-write - - - CNT_TRIG0 - change counter value to one of the calculation cell output when cnt_update_triger0 issued - 0 - 4 - read-write - - - - - cfg3 - No description available - 0xc - 32 - 0x00000000 - 0x0072FFFF - - - CNT_START_SEL - select one trigger from 8, should set to pulse in trig_mux - 20 - 3 - read-write - - - CNT_HW_START_EN - enable use trigger to start pwm output(at next reload point), by cnt_start_sel - 17 - 1 - read-write - - - CNT_BURST - output pwm wave for configured burst(timer period), -0 for one burst; 1 for two burst. -set to 0xFFFF for always output pwm wave -bit's only used when setting cnt_sw_start or trigger selected by cnt_start_sel - 0 - 16 - read-write - - - - - - cnt_glbcfg - No description available - 0x540 - 32 - 0x00000000 - 0x000F0F0F - - - CNT_SW_START - set to start pwm output(at next reload point), write only, Auto clear. -User can disable pwm output before burst end by start again with cnt_burst=0 - 16 - 4 - write-only - - - TIMER_RESET - set to clear current timer. Auto clear - 8 - 4 - write-only - - - TIMER_ENABLE - 1 to enable the main cycle counter; 0 to stop the counter; -NOTE: when counter stopped, the related trigger_out will be cleared to 0, the related pwm output will keep value not changed. - 0 - 4 - read-write - - - - - 16 - 0x10 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CAL[%s] - no description available - 0x600 - - cfg0 - No description available - 0x0 - 32 - 0x00000000 - 0x1F1F1F1F - - - CAL_LU_PARAM - up limit parameter - 24 - 5 - read-write - - - CAL_LL_PARAM - low limit parameter - 16 - 5 - read-write - - - CAL_T_PARAM - period parameter - 8 - 5 - read-write - - - CAL_D_PARAM - dac/counter value parameter - 0 - 5 - read-write - - - - - cfg1 - No description available - 0x4 - 32 - 0x00000000 - 0x379F9F1F - - - CAL_T_INDEX - select one of 4 counter reload time - 28 - 2 - read-write - - - CAL_IN_INDEX - 0~3 to select one of the dac input value; 4~7 to select one of the current counter value - 24 - 3 - read-write - - - CAL_LU_EN - set to enable up limit - 23 - 1 - read-write - - - CAL_LIM_UP - up limit offset selection, select from one of the shadow_val - 16 - 5 - read-write - - - CAL_LL_EN - set to enable low limit - 15 - 1 - read-write - - - CAL_LIM_LO - low limit offset selection, select from one of the shadow_val - 8 - 5 - read-write - - - CAL_IN_OFF - offset for calculation unit, select from one of the shadow_val. - 0 - 5 - read-write - - - - - - 24 - 0x10 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23 - CMP[%s] - no description available - 0x800 - - cfg - No description available - 0x0 - 32 - 0x00000000 - 0x773FC000 - - - CMP_TRIG_SEL - select one trigger from 8, should set to pulse in trig_mux - 28 - 3 - read-write - - - CMP_UPDATE_TIME - define when to use the shadow register value for working register(trig_cmp) -000: software set work_ctrl1.shadow_lock bit -001: update immediately(at next cycle) -010: related counter reload time -011: use cmp_update_trigger(from trig_mux, selected by cmp_trig_sel) -100: use the related counter rld_cmp_sel0 to select one compare point -101: use the related counter rld_cmp_sel1, to select one compare point -11x: reserved, no update. - 24 - 3 - read-write - - - CMP_IN_SEL - 0x00~0x1B select one of the shadow_val directly -0x20~0x2F select one of the calculation cell output -0x30~0x37 select one of capture_pos value(low 8bit are 0) -0x38+k select T/4 -0x3E select 0xFFFFF000 -0x3F select 0xFFFFFF00 -others select 0 - 16 - 6 - read-write - - - CMP_CNT - select one from 4 counters, only for N>=16. -for N<16, this field is0, every 4 compare point related to one counter(0123 for counter0, 4567 for counter1….) - 14 - 2 - read-write - - - - - - - - PWM1 - PWM1 - PWMV2 - 0xf0424000 - - - PWM2 - PWM2 - PWMV2 - 0xf0428000 - - - PWM3 - PWM3 - PWMV2 - 0xf042c000 - - - RDC0 - RDC0 - RDC - 0xf0440000 - - 0x0 - 0xf0 - registers - - - - rdc_ctl - rdc control - 0x0 - 32 - 0x00000000 - 0x003FF37F - - - TS_SEL - Time stamp selection for accumulation -0: end of accumulation -1: start of accumulation -2: center of accumulation - 20 - 2 - read-write - - - ACC_LEN - Accumulate time, support on the fly change -0：1 cycle -1：2 cycles -… -255: 256 cycles - 12 - 8 - read-write - - - ACC_OUT_MASK - rdc output mask - 9 - 1 - read-write - - - IIR_EN - IIR enable for adc input - 8 - 1 - read-write - - - RECTIFY_SEL - Select reference point of rectify signal -0: 0 phase of internal exciting signal -1: 90 phase of internal exciting signal -2: 180 phase of internal exciting signal -3: 270 phase of internal exciting signal -4: use value on external pin -5: use invert value on external pin - 4 - 3 - read-write - - - ACC_FAST - every adc value can be as one accumulate value - 3 - 1 - read-write - - - ACC_EN - Enable rdc accumulate -0: rdc disable -1: rdc enable - 2 - 1 - read-write - - - EXC_START - Write 1 start excite signal, always read 0 -0: no effect -1: start excite signal - 1 - 1 - read-write - - - EXC_EN - Enable rdc excite signal -0: rdc disable -1: rdc enable - 0 - 1 - read-write - - - - - acc_i - accumulate result of i_channel - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - accumulate result of i_channel, this is a signed number - 0 - 32 - read-only - - - - - acc_q - accumulate result of q_channel - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - accumulate result of q_channel, this is a signed number - 0 - 32 - read-only - - - - - in_ctl - input channel selection - 0xc - 32 - 0x00000000 - 0x0011F11F - - - PORT_Q_SEL - Input port selection for q_channel, -0:sel port0 -1:sel port1 - 20 - 1 - read-write - - - CH_Q_SEL - Input channel selection for q_channel -0: channel 0 selected -1: channel 1 selected -… -31: channel 31 selected - 12 - 5 - read-write - - - PORT_I_SEL - Input port selection for i_channel, -0:sel port0 -1:sel port1 - 8 - 1 - read-write - - - CH_I_SEL - Input channel selection for i_channel -0: channel 0 selected -1: channel 1 selected -… -31: channel 31 selected - 0 - 5 - read-write - - - - - out_ctl - output channel selection - 0x10 - 32 - 0x00000000 - 0x00001F1F - - - CH_Q_SEL - Output channel selection for q_channel - 8 - 5 - read-write - - - CH_I_SEL - Output channel selection for i_channel - 0 - 5 - read-write - - - - - iir_b - IIR parameter for b branch - 0x14 - 32 - 0x00000001 - 0x01000007 - - - LOWPASS - IIR in lowpass mode - 24 - 1 - read-write - - - IIR_B - IIR parameter for b branch - 0 - 3 - read-write - - - - - iir_a - IIR parameter for a branch - 0x18 - 32 - 0x00F601F4 - 0x00FF01FF - - - IIR_A2 - IIR parameter a2 for a branch - 16 - 8 - read-write - - - IIR_A1 - IIR parameter a1 for a branch - 0 - 9 - read-write - - - - - exc_timming - excitation signal timming setting - 0x34 - 32 - 0x000400C8 - 0x01FFFFFF - - - SWAP - Swap output of PWM and DAC -0: disable swap -1: swap output - 24 - 1 - read-write - - - PWM_PRD - Pwm period in samples， -0：1 sample period -1: 2 sample period -... -15: 16 sample period - 20 - 4 - read-write - - - SMP_NUM - Number of sample every excitation period -0: 4 point -1: 8 point -… -8: 1024 point - 16 - 4 - read-write - - - SMP_RATE - The period for excitation sample in clock cycle， -0: not allowed -1: 1 cycle -2: 2 cycles -… -65535 : 65535 cycles - 0 - 16 - read-write - - - - - exc_scaling - amplitude scaling for excitation - 0x38 - 32 - 0x00000011 - 0x000000FF - - - AMP_EXP - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 4 - 4 - read-write - - - AMP_MAN - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 0 - 4 - read-write - - - - - exc_offset - amplitude offset setting - 0x3c - 32 - 0x00800000 - 0x00FFFFFF - - - AMP_OFFSET - Offset for excitation - 0 - 24 - read-write - - - - - pwm_scaling - amplitude scaling for excitation - 0x40 - 32 - 0x00000111 - 0x000031FF - - - N_POL - Polarity of exc_n signal -0: high active -1: low active - 13 - 1 - read-write - - - P_POL - Polarity of exc_p signal -0: high active -1: low active - 12 - 1 - read-write - - - DITHER - Enable dither of pwm -0: disable -1: enable - 8 - 1 - read-write - - - AMP_EXP - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 4 - 4 - read-write - - - AMP_MAN - Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - 0 - 4 - read-write - - - - - pwm_offset - amplitude offset setting - 0x44 - 32 - 0x00000064 - 0x00FFFFFF - - - AMP_OFFSET - Offset for excitation - 0 - 24 - read-write - - - - - trig_out0_cfg - Configuration for trigger out 0 in clock cycle - 0x48 - 32 - 0x00100019 - 0x001FFFFF - - - ENABLE - Enable trigger out0 -0: disable -1: enable - 20 - 1 - read-write - - - LEAD_TIM - Lead time for trigger out0 from center of low level , this is a signed value -… -2: 2 cycle befor center of low level -1: 1 cycle before center of low level -0: center of low level --1: 1cycle after center of low level --2: 2cycle after center of low level - 0 - 20 - read-write - - - - - trig_out1_cfg - Configuration for trigger out 1 in clock cycle - 0x4c - 32 - 0x0010004B - 0x001FFFFF - - - ENABLE - Enable trigger out1 -0: disable -1: enable - 20 - 1 - read-write - - - LEAD_TIM - Lead time for trigger out0 from center of hight level , this is a signed value -… -2: 2 cycle befor center of hight level -1: 1 cycle before center of hight level -0: center of hight level --1: 1cycle after center of hight level --2: 2cycle after center of hight level - 0 - 20 - read-write - - - - - pwm_dz - pwm dead zone control in clock cycle - 0x50 - 32 - 0x00000000 - 0x0000FFFF - - - DZ_N - Exc_n dead zone in clock cycle before swap -0: no dead zone -1: 1 cycle dead zone -2: 2 cycle dead zone -… - 8 - 8 - read-write - - - DZ_P - Exc_p dead zone in clock cycle before swap -0: no dead zone -1: 1 cycle dead zone -2: 2 cycle dead zone -… - 0 - 8 - read-write - - - - - sync_out_ctrl - synchronize output signal control - 0x54 - 32 - 0x00000000 - 0xFFFF0033 - - - PWM_OUT_DLY - Delay bettween the delyed trigger and the first pwm pulse in clock cycle -1: 1 cycle -2: 2 cycle -… - 16 - 16 - read-only - - - MIN2TRIG_EN - Enable trigger out from the min point of exciting signal -1: enable -0: disable - 5 - 1 - read-write - - - MAX2TRIG_EN - Enable trigger out from the max point of exciting signal -1: enable -0: disable - 4 - 1 - read-write - - - SYNC_OUT_SEL - Select output synchornize signal -0: 0 phase of internal exciting signal -1: 90 phase of internal exciting signal -2: 180 phase of internal exciting signal -3: 270 phase of internal exciting signal - 0 - 2 - read-write - - - - - exc_sync_dly - trigger in delay timming in soc bus cycle - 0x58 - 32 - 0x01000001 - 0x01FFFFFF - - - DISABLE - Disable hardware trigger input -0: enable -1: disable - 24 - 1 - read-write - - - DELAY - Trigger in delay timming in bus cycle from rising edge of trigger signal -0: 1 cycle -1: 2 cycle -… -0xffffff: 2^24 cycle - 0 - 24 - read-write - - - - - max_min_pos - max min data position of channel - 0x6c - 32 - 0x00000000 - 0x00000001 - - - MAX_MIN_POS - max min value position -0: max min value at adc input -1: max min value at IIR output - 0 - 1 - read-write - - - - - max_i - max value of i_channel - 0x70 - 32 - 0x00000000 - 0xFFFFFF01 - - - MAX - Max value of i_channel, write clear - 8 - 24 - read-write - - - VALID - Max value valid, write clear -0: max value is not valid -1: max value is valid - 0 - 1 - read-write - - - - - min_i - min value of i_channel - 0x74 - 32 - 0x00000000 - 0xFFFFFF01 - - - MIN - Min value of i_channel, write clear - 8 - 24 - read-write - - - VALID - Min value valid, write clear -0: min value is not valid -1: min value is valid - 0 - 1 - read-write - - - - - max_q - max value of q_channel - 0x78 - 32 - 0x00000000 - 0xFFFFFF01 - - - MAX - Max value of q_channel, write clear - 8 - 24 - read-write - - - VALID - Max value valid, write clear -0: max value is not valid -1: max value is valid - 0 - 1 - read-write - - - - - min_q - min value of q_channel - 0x7c - 32 - 0x00000000 - 0xFFFFFF01 - - - MIN - Min value of q_channel, write clear - 8 - 24 - read-write - - - VALID - Min value valid, write clear -0: min value is not valid -1: min value is valid - 0 - 1 - read-write - - - - - thrs_i - the offset setting for edge detection of the i_channel - 0x80 - 32 - 0x00000000 - 0xFFFFFF01 - - - THRS - The offset setting for edge detection of the i_channel, signed number -… -2: the offset is 0x800000+2 -1: the offset is 0x800000+1 -0: the offset is 0x800000 --1: the offset is 0x800000-1 --2: the offset is 0x800000-2 -… - 8 - 24 - read-write - - - THRS4ACC - enable thrs data for accumulate - 0 - 1 - read-write - - - - - thrs_q - the offset setting for edge detection of the q_channel - 0x84 - 32 - 0x00000000 - 0xFFFFFF01 - - - THRS - The offset setting for edge detection of the q_channel, signed number -… -2: the offset is 0x800000+2 -1: the offset is 0x800000+1 -0: the offset is 0x800000 --1: the offset is 0x800000-1 --2: the offset is 0x800000-2 -… - 8 - 24 - read-write - - - THRS4ACC - enable thrs data for accumulate - 0 - 1 - read-write - - - - - edg_det_ctl - the control for edge detection - 0x88 - 32 - 0x00000080 - 0x000003F7 - - - HOLD - The minimum edge distance in sample -0:1 sample -1:2 sample -2:3 samples -… -63:64 samples - 4 - 6 - read-write - - - FILTER - The continuous positive or negative number for edge detection -0: 1 -1: 2 -… -7: 8 - 0 - 3 - read-write - - - - - acc_scaling - scaling for accumulation result - 0x8c - 32 - 0x00000000 - 0x0000010F - - - TOXIC_LK - Toxic accumulation data be removed control -1: enable -0: disable - 8 - 1 - read-write - - - ACC_SHIFT - Accumulation value shift control, this is a sign number. -0: {acc[39],acc[38:8]} -1: {acc[39],acc[37:7]} -2: {acc[39],acc[36:6]} -… -7: {acc[39],acc[31:1]} -8: {acc[39],acc[30:0]} -9: acc/2^9 -10: acc/2^10 -… -15:acc/2^15 - 0 - 4 - read-write - - - - - exc_period - period of excitation - 0x90 - 32 - 0x00001770 - 0xFFFFFFFF - - - EXC_PERIOD - The num in clock cycle for period of excitation -0: invalid value -1:1 cycle -2:2 cycles -… - 0 - 32 - read-write - - - - - sync_delay_i - delay setting in clock cycle for synchronous signal - 0xa0 - 32 - 0x00000008 - 0xFFFFFFFF - - - DELAY - Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. -0: invalid value -1: 1 cycles -2: 2 cycles -... - 0 - 32 - read-write - - - - - rise_delay_i - delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RISE_DELAY - Delay value on rising edge of i_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - fall_delay_i - delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - FALL_DELAY - Delay value on falling edge of i_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - sample_rise_i - sample value on rising edge of rectify signal - 0xb0 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on rising edge of rectify signal - 8 - 24 - read-only - - - - - sample_fall_i - sample value on falling edge of rectify signal - 0xb4 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on falling edge of rectify signal - 8 - 24 - read-only - - - - - acc_cnt_i - number of accumulation - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - sample number during the negtive of rectify signal -1: 1 -2: 2 -… - 16 - 16 - read-only - - - CNT_POS - sample number during the positive of rectify signal -1: 1 -2: 2 -… - 0 - 16 - read-only - - - - - sign_cnt_i - sample counter of opposite sign with rectify signal - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - Positive sample counter during negative rectify signal - 16 - 16 - read-only - - - CNT_POS - Negative sample counter during positive rectify signal - 0 - 16 - read-only - - - - - sync_delay_q - delay setting in clock cycle for synchronous signal - 0xc0 - 32 - 0x00000008 - 0xFFFFFFFF - - - DELAY - Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. -0: invalid value -1: 1 cycles -2: 2 cycles -... - 0 - 32 - read-write - - - - - rise_delay_q - delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RISE_DELAY - Delay value on rising edge of q_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - fall_delay_q - delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - FALL_DELAY - Delay value on falling edge of q_channel data -0: 1 cycle -1: 2 cycles -… - 0 - 32 - read-only - - - - - sample_rise_q - sample value on rising edge of rectify signal - 0xd0 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on rising edge of rectify signal - 8 - 24 - read-only - - - - - sample_fall_q - sample value on falling edge of rectify signal - 0xd4 - 32 - 0x00000000 - 0xFFFFFF00 - - - VALUE - sample value on falling edge of rectify signal - 8 - 24 - read-only - - - - - acc_cnt_q - number of accumulation - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - sample number during the negtive of rectify signal -1: 1 -2: 2 -… - 16 - 16 - read-only - - - CNT_POS - sample number during the positive of rectify signal -1: 1 -2: 2 -… - 0 - 16 - read-only - - - - - sign_cnt_q - sample counter of opposite sign with rectify signal - 0xdc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT_NEG - Positive sample counter during negative rectify signal - 16 - 16 - read-only - - - CNT_POS - Negative sample counter during positive rectify signal - 0 - 16 - read-only - - - - - amp_max - the maximum of acc amplitude - 0xe0 - 32 - 0x01000000 - 0xFFFFFFFF - - - MAX - the maximum of acc amplitude - 0 - 32 - read-write - - - - - amp_min - the minimum of acc amplitude - 0xe4 - 32 - 0x00400000 - 0xFFFFFFFF - - - MIN - the minimum of acc amplitude - 0 - 32 - read-write - - - - - int_en - the interrupt mask control - 0xe8 - 32 - 0x00000000 - 0x8000FFFF - - - INT_EN - enable interrupt output - 31 - 1 - read-write - - - ACC_VLD_I_EN - i_channel accumulate valid interrupt enable for i_channel - 15 - 1 - read-write - - - ACC_VLD_Q_EN - q_channel accumulate valid interrupt enable for i_channel - 14 - 1 - read-write - - - RISING_DELAY_I_EN - i_channel delayed rectify signal rising edge interrupt enable - 13 - 1 - read-write - - - FALLING_DELAY_I_EN - i_channel delayed rectify signal falling edge interrupt enable - 12 - 1 - read-write - - - RISING_DELAY_Q_EN - q_channel delayed rectify signal rising edge interrupt enable - 11 - 1 - read-write - - - FALLING_DELAY_Q_EN - q_channel delayed rectify signal falling edge interrupt enable - 10 - 1 - read-write - - - SAMPLE_RISING_I_EN - i_channel rising edge interrupt enable - 9 - 1 - read-write - - - SAMPLE_FALLING_I_EN - i_channel falling edge interrupt enable - 8 - 1 - read-write - - - SAMPLE_RISING_Q_EN - q_channel rising edge interrupt enable - 7 - 1 - read-write - - - SAMPLE_FALLING_Q_EN - q_channel falling edge interrupt enable - 6 - 1 - read-write - - - ACC_VLD_I_OVH_EN - i_channel accumulate overflow interrupt enable - 5 - 1 - read-write - - - ACC_VLD_Q_OVH_EN - q_channel accumulate overflow interrupt enable - 4 - 1 - read-write - - - ACC_VLD_I_OVL_EN - i_channel accumulate underflow interrupt enable - 3 - 1 - read-write - - - ACC_VLD_Q_OVL_EN - q_channel accumulate underflow interrupt enable - 2 - 1 - read-write - - - ACC_AMP_OVH_EN - accumulate ample overflow interrupt enable - 1 - 1 - read-write - - - ACC_AMP_OVL_EN - accumulate ample underflow interrupt enable - 0 - 1 - read-write - - - - - adc_int_state - the interrupt state - 0xec - 32 - 0x00000000 - 0x0000FFFF - - - ACC_VLD_I_STA - i_channel accumulate valid interrupt status for i_channel - 15 - 1 - write-only - - - ACC_VLD_Q_STA - q_channel accumulate valid interrupt status for i_channel - 14 - 1 - write-only - - - RISING_DELAY_I_STA - i_channel delayed rectify signal rising edge interrupt status - 13 - 1 - write-only - - - FALLING_DELAY_I_STA - i_channel delayed rectify signal falling edge interrupt status - 12 - 1 - write-only - - - RISING_DELAY_Q_STA - q_channel delayed rectify signal rising edge interrupt status - 11 - 1 - write-only - - - FALLING_DELAY_Q_STA - q_channel delayed rectify signal falling edge interrupt status - 10 - 1 - write-only - - - SAMPLE_RISING_I_STA - i_channel rising edge interrupt status - 9 - 1 - write-only - - - SAMPLE_FALLING_I_STA - i_channel falling edge interrupt status - 8 - 1 - write-only - - - SAMPLE_RISING_Q_STA - q_channel rising edge interrupt status - 7 - 1 - write-only - - - SAMPLE_FALLING_Q_STA - q_channel falling edge interrupt status - 6 - 1 - write-only - - - ACC_VLD_I_OVH_STA - i_channel accumulate overflow interrupt status - 5 - 1 - write-only - - - ACC_VLD_Q_OVH_STA - q_channel accumulate overflow interrupt status - 4 - 1 - write-only - - - ACC_VLD_I_OVL_STA - i_channel accumulate underflow interrupt status - 3 - 1 - write-only - - - ACC_VLD_Q_OVL_STA - q_channel accumulate underflow interrupt status - 2 - 1 - write-only - - - ACC_AMP_OVH_STA - accumulate ample overflow interrupt status - 1 - 1 - write-only - - - ACC_AMP_OVL_STA - accumulate ample underflow interrupt status - 0 - 1 - write-only - - - - - - - RDC1 - RDC1 - RDC - 0xf0444000 - - - SDM0 - SDM0 - SDM - 0xf0450000 - - 0x0 - 0x110 - registers - - - - CTRL - SDM control register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFE - - - SFTRST - software reset the module if asserted to be1’b1. - 31 - 1 - read-write - - - CHMD - Channel Rcv mode -Bits[2:0] for Ch0. -Bits[5:3] for Ch1 -Bits[8:6] for Ch2 -Bits[11:9] for Ch3 -3'b000: Capture at posedge of MCLK -3'b001: Capture at both posedge and negedge of MCLK -3'b010: Manchestor Mode -3'b011: Capture at negedge of MCLK -3'b100: Capture at every other posedge of MCLK -3'b101: Capture at every other negedge of MCLK -Others: Undefined - 14 - 12 - read-write - - - SYNC_MCLK - Asserted to double sync the mclk input pin before its usage inside the module - 10 - 4 - read-write - - - SYNC_MDAT - Asserted to double sync the mdat input pin before its usage inside the module - 6 - 4 - read-write - - - CH_EN - Channel Enable - 2 - 4 - read-write - - - IE - Interrupt Enable - 1 - 1 - read-write - - - - - INT_EN - Interrupt enable register. - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3DRY - Ch3 Data Ready interrupt enable. - 7 - 1 - read-write - - - CH2DRY - Ch2 Data Ready interrupt enable - 6 - 1 - read-write - - - CH1DRY - Ch1 Data Ready interrupt enable - 5 - 1 - read-write - - - CH0DRY - Ch0 Data Ready interrupt enable - 4 - 1 - read-write - - - CH3ERR - Ch3 Error interrupt enable. - 3 - 1 - read-write - - - CH2ERR - Ch2 Error interrupt enable - 2 - 1 - read-write - - - CH1ERR - Ch1 Error interrupt enable - 1 - 1 - read-write - - - CH0ERR - Ch0 Error interrupt enable - 0 - 1 - read-write - - - - - STATUS - Status Registers - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CH3DRY - Ch3 Data Ready. -De-assert this bit by reading the data (or data fifo) registers. - 7 - 1 - read-only - - - CH2DRY - Ch2 Data Ready - 6 - 1 - read-only - - - CH1DRY - Ch1 Data Ready - 5 - 1 - read-only - - - CH0DRY - Ch0 Data Ready - 4 - 1 - read-only - - - CH3ERR - Ch3 Error. -ORed together by channel related error signals and corresponding error interrupt enable signals. -De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. - 3 - 1 - read-only - - - CH2ERR - Ch2 Error - 2 - 1 - read-only - - - CH1ERR - Ch1 Error - 1 - 1 - read-only - - - CH0ERR - Ch0 Error - 0 - 1 - read-only - - - - - 4 - 0x40 - 0,1,2,3 - CH[%s] - no description available - 0x10 - - SDFIFOCTRL - Data FIFO Path Control Register - 0x0 - 32 - 0x00000000 - 0xFFFF01F4 - - - GATE_SAMPLES - The number-1-3 of input PDM bit samples to be gated when CIC_GATE_EN=1. Max 255. So the minimum gated samples is 4 samples when GATE_SAMPLES=0. - 16 - 8 - read-write - - - THRSH - FIFO threshold (0,..,16) (fillings > threshold, then gen int) - 4 - 5 - read-write - - - D_RDY_INT_EN - FIFO data ready interrupt enable - 2 - 1 - read-write - - - - - SDCTRLP - Data Path Control Primary Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MANCH_THR - Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] - 25 - 7 - read-write - - - WDOG_THR - Watch dog threshold for channel failure of CLK halting - 17 - 8 - read-write - - - AF_IE - Acknowledge feedback interrupt enable - 16 - 1 - read-write - - - DFFOVIE - Ch Data FIFO overflow interrupt enable - 15 - 1 - read-write - - - DSATIE - Ch CIC Data Saturation Interrupt Enable - 14 - 1 - read-write - - - DRIE - Ch Data Ready Interrupt Enable - 13 - 1 - read-write - - - SYNCSEL - Select the PWM SYNC Source - 7 - 6 - read-write - - - FFSYNCCLREN - Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 - 6 - 1 - read-write - - - WTSYNACLR - 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen -0: WTSYNFLG should be cleared manually by WTSYNMCLR - 5 - 1 - read-write - - - WTSYNMCLR - 1: Manually clear WTSYNFLG. Auto-clear. - 4 - 1 - read-write - - - WTSYNCEN - 1: Start to store data only after PWM SYNC event -0: Start to store data whenever enabled - 3 - 1 - read-write - - - D32 - 1:32 bit data -0:16 bit data - 2 - 1 - read-write - - - DR_OPT - 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold -0: Use Data Reg Ready as data ready - 1 - 1 - read-write - - - EN - Data Path Enable - 0 - 1 - read-write - - - - - SDCTRLE - Data Path Control Extra Register - 0x8 - 32 - 0x00000000 - 0xFE77FFFF - - - CIC_GATE_TYPE - 1: the gate cycle is determined by SDFIFOCTRLn[GATE_SAMPLES]. -0: the gate cycle is determined by the CIC decimation counter, and the minimal gated off PDM bits are determined by SDFIFOCTRLn[GATE_SAMPLES], and at the same time, to keep alignment with normal PCM sampling time. - 31 - 1 - read-write - - - CIC_GATE_POL - 1: When mask signal is 1, pause the CIC stage at he rising edge of mask signal. -0: When mask signal is 0, pause the CIC stage at he falling edge of mask signal. - 30 - 1 - read-write - - - CIC_GATE_SEL - Select the mask signal for CIC gate signal. - 26 - 4 - read-write - - - CIC_GATE_EN - 1: the CIC stage can be paused by the mask input. -0: the CIC stage won't be paused by the mask input. - 25 - 1 - read-write - - - TIMESTAMP_TYPE - 1. Use the time (when the data is calculated out) - delta_time_of_filter_span as the timestamp. -0: Use the time when the data is calculated out. - 22 - 1 - read-write - - - DFIFO_S_T - 1: the output of SDFIFO is data and timestamp interleaved. First is data. -0: the output of SDFIFO is data only - 21 - 1 - read-write - - - DATA_S_T - "1: the read output of SData is data and timestamp interleaved. First is data. -0: the read output of SData is data only" - 20 - 1 - read-write - - - SGD_ORDR - CIC order -0: SYNC1 -1: SYNC2 -2: SYNC3 -3: FAST_SYNC - 17 - 2 - read-write - - - PWMSYNC - Asserted to double sync the PWM trigger signal - 16 - 1 - read-write - - - CIC_SCL - CIC shift control - 11 - 4 - read-write - - - CIC_DEC_RATIO - CIC decimation ratio. 0 means div-by-256 - 3 - 8 - read-write - - - IGN_INI_SAMPLES - NotZero: Don't store the first samples that are not accurate -Zero: Store all samples - 0 - 3 - read-write - - - - - SDST - Data Path Status - 0xc - 32 - 0x00000000 - 0xFF8033FF - - - PERIOD_MCLK - maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. - 23 - 8 - read-only - - - SDATA_D0_T1 - 1: next readout is timestamp -0: next readout is data - 13 - 1 - read-only - - - SDFIFO_D0_T1 - 1: next readout is timestamp -0: next readout is data - 12 - 1 - read-only - - - FIFO_DR - FIFO data ready - 9 - 1 - write-only - - - AF - Achnowledge flag - 8 - 1 - write-only - - - DOV_ERR - Data FIFO Overflow Error. Error flag. - 7 - 1 - write-only - - - DSAT_ERR - CIC out Data saturation err. Error flag. - 6 - 1 - write-only - - - WTSYNFLG - Wait-for-sync event found - 5 - 1 - read-only - - - FILL - Data FIFO Fillings - 0 - 5 - read-only - - - - - SDATA - Data - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Data - 0 - 32 - read-only - - - - - SDFIFO - FIFO Data - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - FIFO Data - 0 - 32 - read-only - - - - - SCAMP - instant Amplitude Results - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - instant Amplitude Results - 0 - 16 - read-only - - - - - SCHTL - Amplitude Threshold for High Limit - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Amplitude Threshold for High Limit - 0 - 16 - read-write - - - - - SCHTLZ - Amplitude Threshold for zero crossing - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Amplitude Threshold for zero crossing - 0 - 16 - read-write - - - - - SCLLT - Amplitude Threshold for low limit - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - VAL - Amplitude Threshold for low limit - 0 - 16 - read-write - - - - - SCCTRL - Amplitude Path Control - 0x28 - 32 - 0x00000000 - 0xFFFC01FF - - - HZ_EN - Zero Crossing Enable - 23 - 1 - read-write - - - MF_IE - Module failure Interrupt enable - 22 - 1 - read-write - - - HL_IE - HLT Interrupt Enable - 21 - 1 - read-write - - - LL_IE - LLT interrupt Enable - 20 - 1 - read-write - - - SGD_ORDR - CIC order -0: SYNC1 -1: SYNC2 -2: SYNC3 -3: FAST_SYNC - 18 - 2 - read-write - - - CIC_DEC_RATIO - CIC decimation ratio. 0 means div-by-32 - 4 - 5 - read-write - - - IGN_INI_SAMPLES - NotZero: Ignore the first samples that are not accurate -Zero: Use all samples - 1 - 3 - read-write - - - EN - Amplitude Path Enable - 0 - 1 - read-write - - - - - SCST - Amplitude Path Status - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - HZ - Amplitude rising above HZ event found. - 3 - 1 - write-only - - - MF - power modulator Failure found. MCLK not found. Error flag. - 2 - 1 - write-only - - - CMPH - HLT out of range. Error flag. - 1 - 1 - write-only - - - CMPL - LLT out of range. Error flag. - 0 - 1 - write-only - - - - - - - - SDM1 - SDM1 - SDM - 0xf0454000 - - - PLB - PLB - PLB - 0xf0460000 - - 0x0 - 0x500 - registers - - - - 8 - 0x20 - 0,1,2,3,4,5,6,7 - TYPE_A[%s] - no description available - 0x0 - - 4 - 0x4 - 0,1,2,3 - LOOKUP_TABLE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0000FFFF - - - LOOKUP_TABLE - using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. - 0 - 16 - read-write - - - - - sw_inject - TYPE A CHN&index0 software inject - 0x10 - 32 - 0x00000000 - 0x0000000F - - - SW_INJECT - software can inject value to TYPEA's output - 0 - 4 - read-write - - - - - - 8 - 0x20 - 0,1,2,3,4,5,6,7 - TYPE_B[%s] - no description available - 0x400 - - 2 - 0x4 - 0,1 - LUT[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOOKUP_TABLE - lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in - 0 - 32 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - CMP[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP_VALUE - cmp value, using as data unit operation - 0 - 32 - read-write - - - - - mode - TYPE B CHN&index0 mode ctrl - 0x18 - 32 - 0x00000000 - 0x0001FFFF - - - OPT_SEL - operation selection in data unit. - 16 - 1 - read-write - - - OUT3_SEL - trig out 3 output type in current channel - 12 - 4 - read-write - - - OUT2_SEL - trig out 2 output type in current channel - 8 - 4 - read-write - - - OUT1_SEL - trig out 1 output type in current channel - 4 - 4 - read-write - - - OUT0_SEL - trig out 0 output type in current channel - 0 - 4 - read-write - - - - - sw_inject - TYPE B CHN&index0 software inject - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - SOFTWARE_INJECT - data unit value can be changed if program this register - 0 - 32 - read-write - - - - - - - - SYNT - SYNT - SYNT - 0xf0464000 - - 0x0 - 0x60 - registers - - - - gcr - Global control register - 0x0 - 32 - 0x00000000 - 0xF000003F - - - TIMESTAMP_INC_NEW - set to increase the timesamp with new value, auto clr - 31 - 1 - write-only - - - TIMESTAMP_DEC_NEW - set to decrease the timesamp with new value, auto clr - 30 - 1 - write-only - - - TIMESTAMP_SET_NEW - set the timesamp to new value, auto clr - 29 - 1 - write-only - - - TIMESTAMP_RESET - reset timesamp to 0, auto clr - 28 - 1 - write-only - - - TIMESTAMP_DEBUG_EN - set to enable cpu_debug_mode to stop the timesamp - 5 - 1 - read-write - - - TIMESTAMP_ENABLE - set to enable the timesamp , clr to stop - 4 - 1 - read-write - - - TIMER_ONESHOT - set for one shot mode, timer will run only once. -Software need reset timer first to start another one shot - 3 - 1 - read-write - - - COUNTER_DEBUG_EN - set to enable cpu_debug_mode to stop the counter - 2 - 1 - read-write - - - CRST - 1- Reset counter - 1 - 1 - read-write - - - CEN - 1- Enable counter - 0 - 1 - read-write - - - - - rld - Counter reload register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - RLD - counter reload value - 0 - 32 - read-write - - - - - timestamp_new - timestamp new value register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - new value for timesamp , can be used as set/inc/dec - 0 - 32 - read-write - - - - - cnt - Counter - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CNT - counter - 0 - 32 - read-only - - - - - timestamp_sav - timestamp trig save value - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - use the trigger to save timesamp here - 0 - 32 - read-only - - - - - timestamp_cur - timestamp read value - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - current timesamp value - 0 - 32 - read-only - - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - CMP[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMP - comparator value, the output will assert when counter count to this value - 0 - 32 - read-write - - - - - - - SEI - SEI - SEI - 0xf0470000 - - 0x0 - 0x4000 - registers - - - - 13 - 0x400 - 0,1,2,3,4,5,6,7,8,9,10,11,12 - CTRL[%s] - no description available - 0x0 - - ENGINE_CTRL - Engine control register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - WATCH - Enable watch dog -0: Watch dog disabled -1: Watch dog enabled - 24 - 1 - read-write - - - ARMING - Wait for trigger before excuting -0: Execute on enable -1: Wait trigger before exection after enabled - 16 - 1 - read-write - - - EXCEPT - Explain timout as exception -0: when timeout, pointer move to next instruction -1: when timeout, pointer jump to timeout vector - 8 - 1 - read-write - - - REWIND - Rewind execution pointer -0: run -1: clean status and rewind - 4 - 1 - read-write - - - ENABLE - Enable -0: disable -1: enable - 0 - 1 - read-write - - - - - ENGINE_PTR_CFG - Pointer configuration register - 0x4 - 32 - 0x00000000 - 0xFF1FFFFF - - - DAT_CDM - Select DATA register to receive CDM bit in BiSSC slave mode -0: ignore -1: command -2: data register 2 -3: data register 3 -... -29:data register 29 -30: value 0 when send, ignore in receive -31: value1 when send, ignore in receive - 24 - 5 - read-write - - - DAT_BASE - Bias for data register access, if calculated index bigger than 32, index will wrap around -0: real data index -1: access index is 1 greater than instruction address -2: access index is 2 greater than instruction address -... -31: access index is 31 greater than instruction address - 16 - 5 - read-write - - - POINTER_WDOG - Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME - 8 - 8 - read-write - - - POINTER_INIT - Initial execute pointer - 0 - 8 - read-write - - - - - ENGINE_WDG_CFG - Watch dog configuration register - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - WDOG_TIME - Time out count for each instruction, counter in bit time. - 0 - 16 - read-write - - - - - ENGINE_EXE_STA - Execution status - 0x10 - 32 - 0x00000000 - 0x00110101 - - - TRIGERED - Execution has been triggered -0: Execution not triggered -1: Execution triggered - 20 - 1 - read-only - - - ARMED - Waiting for trigger for execution -0: Not in waiting status -1: In waiting status - 16 - 1 - read-only - - - EXPIRE - Watchdog timer expired -0: Not expired -1: Expired - 8 - 1 - read-only - - - STALL - Program finished -0: Program is executing -1: Program finished - 0 - 1 - read-only - - - - - ENGINE_EXE_PTR - Execution pointer - 0x14 - 32 - 0x00000000 - 0x1F1F00FF - - - HALT_CNT - Halt count in halt instrution - 24 - 5 - read-only - - - BIT_CNT - Bit count in send and receive instruction execution - 16 - 5 - read-only - - - POINTER - Current program pointer - 0 - 8 - read-only - - - - - ENGINE_EXE_INST - Execution instruction - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - INST - Current instruction - 0 - 32 - read-only - - - - - ENGINE_WDG_STA - Watch dog status - 0x1c - 32 - 0x00000000 - 0x0000FFFF - - - WDOG_CNT - Current watch dog counter value - 0 - 16 - read-only - - - - - XCVR_CTRL - Transceiver control register - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRISMP - Tipple sampe -0: sample 1 time for data transition -1: sample 3 times in receive and result in 2oo3 - 12 - 1 - read-write - - - PAR_CLR - Clear parity error, this is a self clear bit -0: no effect -1: clear parity error - 8 - 1 - write-only - - - RESTART - Restart tranceiver, this is a self clear bit -0: no effect -1: reset tranceiver - 4 - 1 - write-only - - - MODE - Tranceiver mode -0: synchronous maaster -1: synchronous slave -2: asynchronous mode -3: asynchronous mode - 0 - 2 - read-write - - - - - XCVR_TYPE_CFG - Transceiver configuration register - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - WAIT_LEN - Number of extra stop bit for asynchronous mode -0: 1 bit -1: 2 bit -... -255: 256 bit - 24 - 8 - read-write - - - DATA_LEN - Number of data bit for asynchronous mode -0: 1 bit -1: 2 bit -... -31: 32 bit - 16 - 5 - read-write - - - PAR_POL - Polarity of parity for asynchronous mode -0: even -1: odd - 9 - 1 - read-write - - - PAR_EN - enable parity check for asynchronous mode -0: disable -1: enable - 8 - 1 - read-write - - - DA_IDLEZ - Idle state driver of data line -0: output -1: high-Z - 3 - 1 - read-write - - - CK_IDLEZ - Idle state driver of clock line -0: output -1: high-Z - 2 - 1 - read-write - - - DA_IDLEV - Idle state value of data line -0: data'0' -1: data'1' - 1 - 1 - read-write - - - CK_IDLEV - Idle state value of clock line -0: data'0' -1: data'1' - 0 - 1 - read-write - - - - - XCVR_BAUD_CFG - Transceiver baud rate register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - SYNC_POINT - Baud synchronous time, minmum bit time - 16 - 16 - read-write - - - BAUD_DIV - Baud rate, bit time in system clock cycle - 0 - 16 - read-write - - - - - XCVR_DATA_CFG - Transceiver data timing configuration - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - TXD_POINT - data transmit point in system clcok cycle - 16 - 16 - read-write - - - RXD_POINT - data receive point in system clcok cycle - 0 - 16 - read-write - - - - - XCVR_CLK_CFG - Transceiver clock timing configuration - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CK1_POINT - clock point 1 in system clcok cycle - 16 - 16 - read-write - - - CK0_POINT - clock point 0 in system clcok cycle - 0 - 16 - read-write - - - - - XCVR_PIN - Transceiver pin status - 0x38 - 32 - 0x00000000 - 0x07070707 - - - OE_CK - CK drive state -0: input -1: output - 26 - 1 - read-only - - - DI_CK - CK state -0: data 0 -1: data 1 - 25 - 1 - read-only - - - DO_CK - CK output -0: data 0 -1: data 1 - 24 - 1 - read-only - - - OE_RX - RX drive state -0: input -1: output - 18 - 1 - read-only - - - DI_RX - RX state -0: data 0 -1: data 1 - 17 - 1 - read-only - - - DO_RX - RX output -0: data 0 -1: data 1 - 16 - 1 - read-only - - - OE_DE - DE drive state -0: input -1: output - 10 - 1 - read-only - - - DI_DE - DE state -0: data 0 -1: data 1 - 9 - 1 - read-only - - - DO_DE - DE output -0: data 0 -1: data 1 - 8 - 1 - read-only - - - OE_TX - TX drive state -0: input -1: output - 2 - 1 - read-only - - - DI_TX - TX state -0: data 0 -1: data 1 - 1 - 1 - read-only - - - DO_TX - TX output -0: data 0 -1: data 1 - 0 - 1 - read-only - - - - - XCVR_STATE - FSM of asynchronous - 0x3c - 32 - 0x00000000 - 0x07070000 - - - RECV_STATE - FSM of asynchronous receive - 24 - 3 - read-only - - - SEND_STATE - FSM of asynchronous transmit - 16 - 3 - read-only - - - - - TRG_IN_CFG - Trigger input configuration - 0x40 - 32 - 0x00000000 - 0x83878787 - - - REWIND_EN - enable rewind cmd register by LATCH - 31 - 1 - read-write - - - REWIND_SEL - select one LATCH to rewind CMD register -0:LATCH[0] -1:LATCH[1] -2:LATCH[2] -3:LATCH[3] - 24 - 2 - read-write - - - PRD_EN - Enable period trigger (tigger 2) -0: periodical trigger disabled -1: periodical trigger enabled - 23 - 1 - read-write - - - SYNC_SEL - Synchronize sigal selection (tigger 2) -0: trigger in 0 -1: trigger in 1 -... -7: trigger in 7 - 16 - 3 - read-write - - - IN1_EN - Enable trigger 1 -0: disable trigger 1 -1: enable trigger 1 - 15 - 1 - read-write - - - IN1_SEL - Trigger 1 sigal selection -0: trigger in 0 -1: trigger in 1 -... -7: trigger in 7 - 8 - 3 - read-write - - - IN0_EN - Enable trigger 0 -0: disable trigger 1 -1: enable trigger 1 - 7 - 1 - read-write - - - IN0_SEL - Trigger 0 sigal selection -0: trigger in 0 -1: trigger in 1 -... -7: trigger in 7 - 0 - 3 - read-write - - - - - TRG_SW - Software trigger - 0x44 - 32 - 0x00000000 - 0x00000001 - - - SOFT - Software trigger (tigger 3). this bit is self-clear -0: trigger source disabled -1: trigger source enabled - 0 - 1 - write-only - - - - - TRG_PRD_CFG - Period trigger configuration - 0x48 - 32 - 0x00000000 - 0xFFFF0001 - - - ARMING - Wait for trigger synchronous before trigger -0: Trigger directly -1: Wait trigger source before period trigger - 16 - 1 - read-write - - - SYNC - Synchronous -0: Not synchronous -1: Synchronous every trigger source - 0 - 1 - read-write - - - - - TRG_PRD - Trigger period - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - PERIOD - Trigger period - 0 - 32 - read-write - - - - - TRG_OUT_CFG - Trigger output configuration - 0x50 - 32 - 0x00000000 - 0x87878787 - - - OUT3_EN - Enable trigger 3 -0: disable trigger 3 -1: enable trigger 3 - 31 - 1 - read-write - - - OUT3_SEL - Trigger 3 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 24 - 3 - read-write - - - OUT2_EN - Enable trigger 2 -0: disable trigger 2 -1: enable trigger 2 - 23 - 1 - read-write - - - OUT2_SEL - Trigger 2 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 16 - 3 - read-write - - - OUT1_EN - Enable trigger 1 -0: disable trigger 1 -1: enable trigger 1 - 15 - 1 - read-write - - - OUT1_SEL - Trigger 1 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 8 - 3 - read-write - - - OUT0_EN - Enable trigger 0 -0: disable trigger 1 -1: enable trigger 1 - 7 - 1 - read-write - - - OUT0_SEL - Trigger 0 sigal selection -0: trigger out 0 -1: trigger out 1 -... -7: trigger out 7 - 0 - 3 - read-write - - - - - TRG_PRD_STS - Period trigger status - 0x60 - 32 - 0x00000000 - 0x00110000 - - - TRIGERED - Period has been triggered -0: Not triggered -1: Triggered - 20 - 1 - read-only - - - ARMED - Waiting for trigger -0: Not in waiting status -1: In waiting status - 16 - 1 - read-only - - - - - TRG_PRD_CNT - Period trigger counter - 0x64 - 32 - 0x00000000 - 0xFFFFFFFF - - - PERIOD_CNT - Trigger period counter - 0 - 32 - read-only - - - - - 4 - 0x4 - 0,1,2,3 - TRG_TABLE_CMD[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_TRIGGER0 - Trigger command - 0 - 32 - read-write - - - - - 4 - 0x4 - 0,1,2,3 - TRG_TABLE_TIME[%s] - no description available - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRIGGER0_TIME - Trigger time - 0 - 32 - read-only - - - - - CMD_MODE - command register mode - 0xc0 - 32 - 0x00000000 - 0xE0FFCFFF - - - WLEN - word length -0: 1 bit -1: 2 bit -... -31: 32 bit - 16 - 5 - read-write - - - WORDER - word order -0: sample as bit order -1: different from bit order - 11 - 1 - read-write - - - BORDER - bit order -0: LSB first -1: MSB first - 10 - 1 - read-write - - - SIGNED - Signed -0: unsigned value -1: signed value - 9 - 1 - read-write - - - REWIND - Write 1 to rewind read/write pointer, this is a self clear bit - 8 - 1 - write-only - - - MODE - Data mode(CMD register only support data mode) -0: data mode -1: check mode -2: CRC mode - 0 - 2 - read-write - - - - - CMD_IDX - command register configuration - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LAST_BIT - Last bit index for tranceive - 24 - 5 - read-write - - - FIRST_BIT - First bit index for tranceive - 16 - 5 - read-write - - - MAX_BIT - Highest bit index - 8 - 5 - read-write - - - MIN_BIT - Lowest bit index - 0 - 5 - read-write - - - - - CMD_CMD - command - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - DATA - 0 - 32 - read-write - - - - - CMD_SET - command bit set register - 0xe4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_SET - DATA bit set - 0 - 32 - read-write - - - - - CMD_CLR - command bit clear register - 0xe8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_CLR - DATA bit clear - 0 - 32 - read-write - - - - - CMD_INV - command bit invert register - 0xec - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_TGL - DATA bit toggle - 0 - 32 - read-write - - - - - CMD_IN - Commad input - 0xf0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_IN - Commad input - 0 - 32 - read-only - - - - - CMD_OUT - Command output - 0xf4 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_OUT - Command output - 0 - 32 - read-only - - - - - CMD_STS - Command status - 0xf8 - 32 - 0x00000000 - 0xE0FFFFFF - - - WORD_IDX - Word index - 16 - 5 - read-only - - - WORD_CNT - Word counter - 8 - 5 - read-only - - - BIT_IDX - Bit index - 0 - 5 - read-only - - - - - 8 - 0x20 - 0,1,2,3,4,5,6,7 - CMD_CMD_TABLE[%s] - no description available - 0x100 - - MIN - command start value - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_MIN - minimum command value - 0 - 32 - read-write - - - - - MAX - command end value - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_MAX - maximum command value - 0 - 32 - read-write - - - - - MSK - command compare bit enable - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD_MASK - compare mask - 0 - 32 - read-write - - - - - PTA - command pointer 0 - 3 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR3 - pointer3 - 24 - 8 - read-write - - - PTR2 - pointer2 - 16 - 8 - read-write - - - PTR1 - pointer1 - 8 - 8 - read-write - - - PTR0 - pointer0 - 0 - 8 - read-write - - - - - PTB - command pointer 4 - 7 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR7 - pointer7 - 24 - 8 - read-write - - - PTR6 - pointer6 - 16 - 8 - read-write - - - PTR5 - pointer5 - 8 - 8 - read-write - - - PTR4 - pointer4 - 0 - 8 - read-write - - - - - PTC - command pointer 8 - 11 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR11 - pointer11 - 24 - 8 - read-write - - - PTR10 - pointer10 - 16 - 8 - read-write - - - PTR9 - pointer9 - 8 - 8 - read-write - - - PTR8 - pointer8 - 0 - 8 - read-write - - - - - PTD - command pointer 12 - 15 - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - PTR15 - pointer15 - 24 - 8 - read-write - - - PTR14 - pointer14 - 16 - 8 - read-write - - - PTR13 - pointer13 - 8 - 8 - read-write - - - PTR12 - pointer12 - 0 - 8 - read-write - - - - - - 4 - 0x20 - 0,1,2,3 - CMD_LATCH[%s] - no description available - 0x200 - - 4 - 0x4 - 0_1,1_2,2_3,3_0 - TRAN[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFF0FFFFF - - - POINTER - pointer - 24 - 8 - read-write - - - CFG_TM - timeout -0: high -1: low -2: rise -3: fall - 16 - 2 - read-write - - - CFG_RXD - data received -0: high -1: low -2: rise -3: fall - 14 - 2 - read-write - - - CFG_TXD - data send -0: high -1: low -2: rise -3: fall - 12 - 2 - read-write - - - CFG_CLK - clock -0: high -1: low -2: rise -3: fall - 10 - 2 - read-write - - - CFG_PTR - pointer -0: match -1: not match -2:entry -3:leave - 8 - 2 - read-write - - - OV_TM - override timeout check - 4 - 1 - read-write - - - OV_RXD - override RX data check - 3 - 1 - read-write - - - OV_TXD - override TX data check - 2 - 1 - read-write - - - OV_CLK - override clock check - 1 - 1 - read-write - - - OV_PTR - override pointer check - 0 - 1 - read-write - - - - - CFG - Latch configuration - 0x10 - 32 - 0x00000000 - 0x8700FFFF - - - EN - Enable latch -0: disable -1: enable - 31 - 1 - read-write - - - SELECT - Output select -0: state0-state1 -1: state1-state2 -2: state2-state3 -3: state3-state0 - 24 - 3 - read-write - - - DELAY - Delay in system clock cycle, for state transition - 0 - 16 - read-write - - - - - TIME - Latch time - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - LAT_TIME - Latch time - 0 - 32 - read-only - - - - - STS - Latch status - 0x1c - 32 - 0x00000000 - 0x0700FFFF - - - STATE - State - 24 - 3 - read-only - - - LAT_CNT - Latch counter - 0 - 16 - read-only - - - - - - POS_SMP_EN - Sample selection register - 0x280 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_EN - Position include acceleration -0: use acceleration from sample override acceleration register -1: use acceleration from motor group - 31 - 1 - read-write - - - ACC_SEL - Data register for acceleration transfer - 24 - 5 - read-write - - - SPD_EN - Position include speed -0: use speed from sample override speed register -1: use speed from motor group - 23 - 1 - read-write - - - SPD_SEL - Data register for speed transfer - 16 - 5 - read-write - - - REV_EN - Position include revolution -0: use revolution from sample override revolution register -1: use revolution from motor group - 15 - 1 - read-write - - - REV_SEL - Data register for revolution transfer - 8 - 5 - read-write - - - POS_EN - Position include position -0: use position from sample override position register -1: use position from motor group - 7 - 1 - read-write - - - POS_SEL - Data register for position transfer - 0 - 5 - read-write - - - - - POS_SMP_CFG - Sample configuration - 0x284 - 32 - 0x00000000 - 0x0103FFFF - - - ONCE - Sample one time -0: Sample during windows time -1: Close sample window after first sample - 24 - 1 - read-write - - - LAT_SEL - Latch selection -0: latch 0 -1: latch 1 -2: latch 2 -3: latch 3 - 16 - 2 - read-write - - - WINDOW - Sample window, in clock cycle - 0 - 16 - read-write - - - - - POS_SMP_DAT - Sample data - 0x288 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT_SEL - Data register sampled, each bit represent a data register - 0 - 32 - read-write - - - - - POS_SMP_POS - Sample override position - 0x290 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS - Sample override position - 0 - 32 - read-write - - - - - POS_SMP_REV - Sample override revolution - 0x294 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - Sample override revolution - 0 - 32 - read-write - - - - - POS_SMP_SPD - Sample override speed - 0x298 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPD - Sample override speed - 0 - 32 - read-write - - - - - POS_SMP_ACC - Sample override accelerate - 0x29c - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - Sample override accelerate - 0 - 32 - read-write - - - - - POS_UPD_EN - Update configuration - 0x2a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_EN - Position include acceleration -0: use acceleration from update override acceleration register -1: use acceleration from data register - 31 - 1 - read-write - - - ACC_SEL - Data register for acceleration transfer - 24 - 5 - read-write - - - SPD_EN - Position include speed -0: use speed from update override speed register -1: use speed from data register - 23 - 1 - read-write - - - SPD_SEL - Data register for speed transfer - 16 - 5 - read-write - - - REV_EN - Position include revolution -0: use revolution from update override revolution register -1: use revolution from data register - 15 - 1 - read-write - - - REV_SEL - Data register for revolution transfer - 8 - 5 - read-write - - - POS_EN - Position include position -0: use position from update override position register -1: use position from data register - 7 - 1 - read-write - - - POS_SEL - Data register for position transfer - 0 - 5 - read-write - - - - - POS_UPD_CFG - Update configuration - 0x2a4 - 32 - 0x00000000 - 0x81030000 - - - TIME_OVRD - Use override time -0: use time sample from motor group -1: use override time - 31 - 1 - read-write - - - ONERR - Sample one time -0: Sample during windows time -1: Close sample window after first sample - 24 - 1 - read-write - - - LAT_SEL - Latch selection -0: latch 0 -1: latch 1 -2: latch 2 -3: latch 3 - 16 - 2 - read-write - - - - - POS_UPD_DAT - Update data - 0x2a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT_SEL - Data register sampled, each bit represent a data register - 0 - 32 - read-write - - - - - POS_UPD_TIME - Update overide time - 0x2ac - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - Update override time - 0 - 32 - read-write - - - - - POS_UPD_POS - Update override position - 0x2b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS - Update override position - 0 - 32 - read-write - - - - - POS_UPD_REV - Update override revolution - 0x2b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - Update override revolution - 0 - 32 - read-write - - - - - POS_UPD_SPD - Update override speed - 0x2b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPD - Update override speed - 0 - 32 - read-write - - - - - POS_UPD_ACC - Update override accelerate - 0x2bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - Update override accelerate - 0 - 32 - read-write - - - - - POS_SMP_VAL - Sample valid - 0x2c0 - 32 - 0x00000000 - 0x80808080 - - - ACC - Position include acceleration - 31 - 1 - read-only - - - SPD - Position include speed - 23 - 1 - read-only - - - REV - Position include revolution - 15 - 1 - read-only - - - POS - Position include position - 7 - 1 - read-only - - - - - POS_SMP_STS - Sample status - 0x2c4 - 32 - 0x00000000 - 0x0100FFFF - - - OCCUR - Sample occured -0: Sample not happened -1: Sample occured - 24 - 1 - read-only - - - WIN_CNT - Sample window counter - 0 - 16 - read-only - - - - - POS_TIME_IN - input time - 0x2cc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - input time - 0 - 32 - read-only - - - - - POS_POS_IN - Input position - 0x2d0 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS - Input position - 0 - 32 - read-only - - - - - POS_REV_IN - Input revolution - 0x2d4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV - Input revolution - 0 - 32 - read-only - - - - - POS_SPD_IN - Input speed - 0x2d8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SPD - Input speed - 0 - 32 - read-only - - - - - POS_ACC_IN - Input accelerate - 0x2dc - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC - Input accelerate - 0 - 32 - read-only - - - - - POS_UPD_STS - Update status - 0x2e4 - 32 - 0x00000000 - 0x01000000 - - - UPD_ERR - Update error -0: data receive normally -1: data receive error - 24 - 1 - read-only - - - - - IRQ_INT_EN - Interrupt Enable - 0x300 - 32 - 0x00000000 - 0xFF1F3FF7 - - - TRG_ERR3 - Trigger3 failed - 31 - 1 - read-write - - - TRG_ERR2 - Trigger2 failed - 30 - 1 - read-write - - - TRG_ERR1 - Trigger1 failed - 29 - 1 - read-write - - - TRG_ERR0 - Trigger0 failed - 28 - 1 - read-write - - - TRIGER3 - Trigger3 - 27 - 1 - read-write - - - TRIGER2 - Trigger2 - 26 - 1 - read-write - - - TRIGER1 - Trigger1 - 25 - 1 - read-write - - - TRIGER0 - Trigger0 - 24 - 1 - read-write - - - SMP_ERR - Sample error - 20 - 1 - read-write - - - LATCH3 - Latch3 - 19 - 1 - read-write - - - LATCH2 - Latch2 - 18 - 1 - read-write - - - LATCH1 - Latch1 - 17 - 1 - read-write - - - LATCH0 - Latch0 - 16 - 1 - read-write - - - TIMEOUT - Timeout - 13 - 1 - read-write - - - TRX_ERR - Transfer error - 12 - 1 - read-write - - - INSTR1_END - Instruction 1 end - 11 - 1 - read-write - - - INSTR0_END - Instruction 0 end - 10 - 1 - read-write - - - PTR1_END - Pointer 1 end - 9 - 1 - read-write - - - PTR0_END - Pointer 0 end - 8 - 1 - read-write - - - INSTR1_ST - Instruction 1 start - 7 - 1 - read-write - - - INSTR0_ST - Instruction 0 start - 6 - 1 - read-write - - - PTR1_ST - Pointer 1 start - 5 - 1 - read-write - - - PTR0_ST - Pointer 0 start - 4 - 1 - read-write - - - WDOG - Watch dog - 2 - 1 - read-write - - - EXCEPT - Exception - 1 - 1 - read-write - - - STALL - Stall - 0 - 1 - read-write - - - - - IRQ_INT_FLAG - Interrupt flag - 0x304 - 32 - 0x00000000 - 0xFF1F3FF7 - - - TRG_ERR3 - Trigger3 failed - 31 - 1 - write-only - - - TRG_ERR2 - Trigger2 failed - 30 - 1 - write-only - - - TRG_ERR1 - Trigger1 failed - 29 - 1 - write-only - - - TRG_ERR0 - Trigger0 failed - 28 - 1 - write-only - - - TRIGER3 - Trigger3 - 27 - 1 - write-only - - - TRIGER2 - Trigger2 - 26 - 1 - write-only - - - TRIGER1 - Trigger1 - 25 - 1 - write-only - - - TRIGER0 - Trigger0 - 24 - 1 - write-only - - - SMP_ERR - Sample error - 20 - 1 - write-only - - - LATCH3 - Latch3 - 19 - 1 - write-only - - - LATCH2 - Latch2 - 18 - 1 - write-only - - - LATCH1 - Latch1 - 17 - 1 - write-only - - - LATCH0 - Latch0 - 16 - 1 - write-only - - - TIMEOUT - Timeout - 13 - 1 - write-only - - - TRX_ERR - Transfer error - 12 - 1 - write-only - - - INSTR1_END - Instruction 1 end - 11 - 1 - write-only - - - INSTR0_END - Instruction 0 end - 10 - 1 - write-only - - - PTR1_END - Pointer 1 end - 9 - 1 - write-only - - - PTR0_END - Pointer 0 end - 8 - 1 - write-only - - - INSTR1_ST - Instruction 1 start - 7 - 1 - write-only - - - INSTR0_ST - Instruction 0 start - 6 - 1 - write-only - - - PTR1_ST - Pointer 1 start - 5 - 1 - write-only - - - PTR0_ST - Pointer 0 start - 4 - 1 - write-only - - - WDOG - Watch dog - 2 - 1 - write-only - - - EXCEPT - Exception - 1 - 1 - write-only - - - STALL - Stall - 0 - 1 - write-only - - - - - IRQ_INT_STS - Interrupt status - 0x308 - 32 - 0x00000000 - 0xFF1F3FF7 - - - TRG_ERR3 - Trigger3 failed - 31 - 1 - read-only - - - TRG_ERR2 - Trigger2 failed - 30 - 1 - read-only - - - TRG_ERR1 - Trigger1 failed - 29 - 1 - read-only - - - TRG_ERR0 - Trigger0 failed - 28 - 1 - read-only - - - TRIGER3 - Trigger3 - 27 - 1 - read-only - - - TRIGER2 - Trigger2 - 26 - 1 - read-only - - - TRIGER1 - Trigger1 - 25 - 1 - read-only - - - TRIGER0 - Trigger0 - 24 - 1 - read-only - - - SMP_ERR - Sample error - 20 - 1 - read-only - - - LATCH3 - Latch3 - 19 - 1 - read-only - - - LATCH2 - Latch2 - 18 - 1 - read-only - - - LATCH1 - Latch1 - 17 - 1 - read-only - - - LATCH0 - Latch0 - 16 - 1 - read-only - - - TIMEOUT - Timeout - 13 - 1 - read-only - - - TRX_ERR - Transfer error - 12 - 1 - read-only - - - INSTR1_END - Instruction 1 end - 11 - 1 - read-only - - - INSTR0_END - Instruction 0 end - 10 - 1 - read-only - - - PTR1_END - Pointer 1 end - 9 - 1 - read-only - - - PTR0_END - Pointer 0 end - 8 - 1 - read-only - - - INSTR1_ST - Instruction 1 start - 7 - 1 - read-only - - - INSTR0_ST - Instruction 0 start - 6 - 1 - read-only - - - PTR1_ST - Pointer 1 start - 5 - 1 - read-only - - - PTR0_ST - Pointer 0 start - 4 - 1 - read-only - - - WDOG - Watch dog - 2 - 1 - read-only - - - EXCEPT - Exception - 1 - 1 - read-only - - - STALL - Stall - 0 - 1 - read-only - - - - - IRQ_POINTER0 - Match pointer 0 - 0x310 - 32 - 0x00000000 - 0x000000FF - - - POINTER - Match pointer 0 - 0 - 8 - read-write - - - - - IRQ_POINTER1 - Match pointer 1 - 0x314 - 32 - 0x00000000 - 0x000000FF - - - POINTER - Match pointer 1 - 0 - 8 - read-write - - - - - IRQ_INSTR0 - Match instruction 0 - 0x318 - 32 - 0x00000000 - 0xFFFFFFFF - - - INSTR - Match instruction 0 - 0 - 32 - read-write - - - - - IRQ_INSTR1 - Match instruction 1 - 0x31c - 32 - 0x00000000 - 0xFFFFFFFF - - - INSTR - Match instruction 1 - 0 - 32 - read-write - - - - - - 256 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255 - INSTR[%s] - no description available - 0x3400 - 32 - 0x00000000 - 0xFFFFFFFF - - - OP - operation -0: halt -1: jump -2: send with timeout check -3: send without timout check -4: wait with timeout check -5: wait without timout check -6: receive with timeout check -7: receive without timout check - 26 - 3 - read-write - - - CK - clock -0: low -1: rise-fall -2: fall-rise -3: high - 24 - 2 - read-write - - - CRC - CRC register -0: don't calculate CRC -1: do not set this value -2: data register 2 -3: data register 3 -... -29: data register 29 -30: value 0 when send, wait 0 in receive -31: value1 when send, wait 1 in receive - 16 - 5 - read-write - - - DAT - DATA register -0: ignore data -1: command -2: data register 2 -3: data register 3 -... -29: data register 29 -30: value 0 when send, wait 0 in receive -31: value1 when send, wait 1 in receive - 8 - 5 - read-write - - - OPR - [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. -[2] When OP is 1, this area is the the pointer to the command table. -OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; -OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; -OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. -[3] When OP is 2-7, this area is the data length as fellow: -0: 1 bit -1: 2 bit - ... -31: 32 bit - 0 - 5 - read-write - - - - - 32 - 0x40 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - DAT[%s] - no description available - 0x3800 - - MODE - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_LEN - CRC length -0: 1 bit -1: 2 bit -... -31: 32 bit - 24 - 5 - read-write - - - WLEN - word length -0: 1 bit -1: 2 bit -... -31: 32 bit - 16 - 5 - read-write - - - CRC_SHIFT - CRC shift mode, this mode is used to perform repeat code check -0: CRC -1: shift mode - 13 - 1 - read-write - - - CRC_INV - CRC invert -0: use CRC -1: use inverted CRC - 12 - 1 - read-write - - - WORDER - word order -0: sample as bit order -1: different from bit order - 11 - 1 - read-write - - - BORDER - bit order -0: LSB first -1: MSB first - 10 - 1 - read-write - - - SIGNED - Signed -0: unsigned value -1: signed value - 9 - 1 - read-write - - - REWIND - Write 1 to rewind read/write pointer, this is a self clear bit - 8 - 1 - read-write - - - MODE - Data mode -0: data mode -1: check mode -2: CRC mode - 0 - 2 - read-write - - - - - IDX - Data register bit index - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LAST_BIT - Last bit index for tranceive - 24 - 5 - read-write - - - FIRST_BIT - First bit index for tranceive - 16 - 5 - read-write - - - MAX_BIT - Highest bit index - 8 - 5 - read-write - - - MIN_BIT - Lowest bit index - 0 - 5 - read-write - - - - - GOLD - Gold data for data check - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GOLD_VALUE - Gold value for check mode - 0 - 32 - read-write - - - - - CRCINIT - CRC calculation initial vector - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_INIT - CRC initial value - 0 - 32 - read-write - - - - - CRCPOLY - CRC calculation polynomial - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_POLY - CRC polymonial - 0 - 32 - read-write - - - - - DATA - Data value - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - DATA - 0 - 32 - read-write - - - - - SET - Data bit set - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_SET - DATA bit set - 0 - 32 - read-write - - - - - CLR - Data bit clear - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_CLR - DATA bit clear - 0 - 32 - read-write - - - - - INV - Data bit invert - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_INV - DATA bit toggle - 0 - 32 - read-write - - - - - IN - Data input - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_IN - Data input - 0 - 32 - read-only - - - - - OUT - Data output - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA_OUT - Data output - 0 - 32 - read-only - - - - - STS - Data status - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - CRC_IDX - CRC index - 24 - 5 - read-only - - - WORD_IDX - Word index - 16 - 5 - read-only - - - WORD_CNT - Word counter - 8 - 5 - read-only - - - BIT_IDX - Bit index - 0 - 5 - read-only - - - - - - - - TRGM0 - TRGM0 - TRGM - 0xf047c000 - - 0x0 - 0x13c8 - registers - - - - 64 - 0x4 - PWM0_IN0,PWM0_IN1,PWM0_IN2,PWM0_IN3,PWM0_IN4,PWM0_IN5,PWM0_IN6,PWM0_IN7,PWM1_IN0,PWM1_IN1,PWM1_IN2,PWM1_IN3,PWM1_IN4,PWM1_IN5,PWM1_IN6,PWM1_IN7,PWM2_IN0,PWM2_IN1,PWM2_IN2,PWM2_IN3,PWM2_IN4,PWM2_IN5,PWM2_IN6,PWM2_IN7,PWM3_IN0,PWM3_IN1,PWM3_IN2,PWM3_IN3,PWM3_IN4,PWM3_IN5,PWM3_IN6,PWM3_IN7,MOTO_GPIO_IN0,MOTO_GPIO_IN1,MOTO_GPIO_IN2,MOTO_GPIO_IN3,MOTO_GPIO_IN4,MOTO_GPIO_IN5,MOTO_GPIO_IN6,MOTO_GPIO_IN7,MOTO_GPIO_IN8,MOTO_GPIO_IN9,MOTO_GPIO_IN10,MOTO_GPIO_IN11,MOTO_GPIO_IN12,MOTO_GPIO_IN13,MOTO_GPIO_IN14,MOTO_GPIO_IN15,MOTO_GPIO_IN16,MOTO_GPIO_IN17,MOTO_GPIO_IN18,MOTO_GPIO_IN19,MOTO_GPIO_IN20,MOTO_GPIO_IN21,MOTO_GPIO_IN22,MOTO_GPIO_IN23,MOTO_GPIO_IN24,MOTO_GPIO_IN25,MOTO_GPIO_IN26,MOTO_GPIO_IN27,MOTO_GPIO_IN28,MOTO_GPIO_IN29,MOTO_GPIO_IN30,MOTO_GPIO_IN31 - FILTCFG[%s] - no description available - 0x0 - 32 - 0x00000000 - 0x0001FFFF - - - OUTINV - 1- Filter will invert the output -0- Filter will not invert the output - 16 - 1 - read-write - - - MODE - This bitfields defines the filter mode -000-bypass; -100-rapid change mode; -101-delay filter mode; -110-stalbe low mode; -111-stable high mode - 13 - 3 - read-write - - - SYNCEN - set to enable sychronization input signal with TRGM clock - 12 - 1 - read-write - - - FILTLEN_SHIFT - No description available - 9 - 3 - read-write - - - FILTLEN_BASE - This bitfields defines the filter counter length. - 0 - 9 - read-write - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DMACFG[%s] - no description available - 0x400 - 32 - 0x00000000 - 0x8000003F - - - DMAMUX_EN - No description available - 31 - 1 - read-write - - - DMASRCSEL - No description available - 0 - 6 - read-write - - - - - GCR - No description available - 0x500 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGOPEN - No description available - 0 - 32 - read-write - - - - - ADC_MATRIX_SEL0 - adc matrix select register0 - 0x540 - 32 - 0x00000000 - 0xFFFFFFFF - - - RDC1_ADC1_SEL - No description available - 24 - 8 - read-write - - - RDC1_ADC0_SEL - No description available - 16 - 8 - read-write - - - RDC0_ADC1_SEL - No description available - 8 - 8 - read-write - - - RDC0_ADC0_SEL - No description available - 0 - 8 - read-write - - - - - ADC_MATRIX_SEL1 - adc matrix select register1 - 0x544 - 32 - 0x00000000 - 0xFFFFFFFF - - - QEI3_ADC1_SEL - No description available - 24 - 8 - read-write - - - QEI3_ADC0_SEL - No description available - 16 - 8 - read-write - - - QEI2_ADC1_SEL - No description available - 8 - 8 - read-write - - - QEI2_ADC0_SEL - No description available - 0 - 8 - read-write - - - - - ADC_MATRIX_SEL2 - adc matrix select register2 - 0x548 - 32 - 0x00000000 - 0xFFFFFFFF - - - VSC1_ADC0_SEL - No description available - 24 - 8 - read-write - - - VSC0_ADC2_SEL - No description available - 16 - 8 - read-write - - - VSC0_ADC1_SEL - No description available - 8 - 8 - read-write - - - VSC0_ADC0_SEL - No description available - 0 - 8 - read-write - - - - - ADC_MATRIX_SEL3 - adc matrix select register3 - 0x54c - 32 - 0x00000000 - 0xFFFFFFFF - - - CLC0_IQ_ADC_SEL - No description available - 24 - 8 - read-write - - - CLC0_ID_ADC_SEL - No description available - 16 - 8 - read-write - - - VSC1_ADC2_SEL - No description available - 8 - 8 - read-write - - - VSC1_ADC1_SEL - No description available - 0 - 8 - read-write - - - - - ADC_MATRIX_SEL4 - adc matrix select register2 - 0x550 - 32 - 0x00000000 - 0xFFFFFFFF - - - CLC1_VB_ADC_SEL - No description available - 24 - 8 - read-write - - - CLC1_IQ_ADC_SEL - No description available - 16 - 8 - read-write - - - CLC1_ID_ADC_SEL - No description available - 8 - 8 - read-write - - - CLC0_VB_ADC_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL0 - dac matrix select register0 - 0x580 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACMP3_DAC_SEL - No description available - 24 - 8 - read-write - - - ACMP2_DAC_SEL - No description available - 16 - 8 - read-write - - - ACMP1_DAC_SEL - No description available - 8 - 8 - read-write - - - ACMP0_DAC_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL1 - dac matrix select register1 - 0x584 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACMP7_DAC_SEL - No description available - 24 - 8 - read-write - - - ACMP6_DAC_SEL - No description available - 16 - 8 - read-write - - - ACMP5_DAC_SEL - No description available - 8 - 8 - read-write - - - ACMP4_DAC_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL2 - dac matrix select register2 - 0x588 - 32 - 0x00000000 - 0xFFFFFFFF - - - PWM0_DAC3_SEL - No description available - 24 - 8 - read-write - - - PWM0_DAC2_SEL - No description available - 16 - 8 - read-write - - - PWM0_DAC1_SEL - No description available - 8 - 8 - read-write - - - PWM0_DAC0_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL3 - dac matrix select register3 - 0x58c - 32 - 0x00000000 - 0xFFFFFFFF - - - PWM1_DAC3_SEL - No description available - 24 - 8 - read-write - - - PWM1_DAC2_SEL - No description available - 16 - 8 - read-write - - - PWM1_DAC1_SEL - No description available - 8 - 8 - read-write - - - PWM1_DAC0_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL4 - dac matrix select register4 - 0x590 - 32 - 0x00000000 - 0xFFFFFFFF - - - PWM2_DAC3_SEL - No description available - 24 - 8 - read-write - - - PWM2_DAC2_SEL - No description available - 16 - 8 - read-write - - - PWM2_DAC1_SEL - No description available - 8 - 8 - read-write - - - PWM2_DAC0_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL5 - dac matrix select register5 - 0x594 - 32 - 0x00000000 - 0xFFFFFFFF - - - PWM3_DAC3_SEL - No description available - 24 - 8 - read-write - - - PWM3_DAC2_SEL - No description available - 16 - 8 - read-write - - - PWM3_DAC1_SEL - No description available - 8 - 8 - read-write - - - PWM3_DAC0_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL6 - dac matrix select register6 - 0x598 - 32 - 0x00000000 - 0xFFFFFFFF - - - QEO1_VQ_DAC_SEL - No description available - 24 - 8 - read-write - - - QEO1_VD_DAC_SEL - No description available - 16 - 8 - read-write - - - QEO0_VQ_DAC_SEL - No description available - 8 - 8 - read-write - - - QEO0_VD_DAC_SEL - No description available - 0 - 8 - read-write - - - - - DAC_MATRIX_SEL7 - dac matrix select register7 - 0x59c - 32 - 0x00000000 - 0xFFFFFFFF - - - QEO3_VQ_DAC_SEL - No description available - 24 - 8 - read-write - - - QEO3_VD_DAC_SEL - No description available - 16 - 8 - read-write - - - QEO2_VQ_DAC_SEL - No description available - 8 - 8 - read-write - - - QEO2_VD_DAC_SEL - No description available - 0 - 8 - read-write - - - - - POS_MATRIX_SEL0 - position matrix select register0 - 0x5c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEI_POSIN3_SEL - No description available - 24 - 8 - read-write - - - SEI_POSIN2_SEL - No description available - 16 - 8 - read-write - - - SEI_POSIN1_SEL - No description available - 8 - 8 - read-write - - - SEI_POSIN0_SEL - No description available - 0 - 8 - read-write - - - - - POS_MATRIX_SEL1 - position matrix select register0 - 0x5c4 - 32 - 0x00000000 - 0xFFFFFFFF - - - QEO1_POS_SEL - No description available - 24 - 8 - read-write - - - QEO0_POS_SEL - No description available - 16 - 8 - read-write - - - MTG1_POS_SEL - No description available - 8 - 8 - read-write - - - MTG0_POS_SEL - No description available - 0 - 8 - read-write - - - - - POS_MATRIX_SEL2 - position matrix select register2 - 0x5c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VSC1_POS_SEL - No description available - 24 - 8 - read-write - - - VSC0_POS_SEL - No description available - 16 - 8 - read-write - - - QEO3_POS_SEL - No description available - 8 - 8 - read-write - - - QEO2_POS_SEL - No description available - 0 - 8 - read-write - - - - - 8 - 0x4 - 0,4,1,5,2,6,3,7 - TRGM_IN[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGM_IN - No description available - 0 - 32 - read-only - - - - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - TRGM_OUT[%s] - no description available - 0x680 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGM_OUT - No description available - 0 - 32 - read-only - - - - - pwm_delay_cfg - pwm delay chain config register - 0x800 - 32 - 0x00000000 - 0x0000003F - - - DELAY_CHAN_CALIB_SW - No description available - 0 - 6 - read-write - - - - - pwm_calib_cfg - pwm delay chain calibration control register - 0x804 - 32 - 0x00000000 - 0x0000801F - - - CALIB_SW_START - No description available - 15 - 1 - read-write - - - CALIB_PERIOD - No description available - 0 - 5 - read-write - - - - - 242 - 0x4 - MOT_GPIO0,MOT_GPIO1,MOT_GPIO2,MOT_GPIO3,MOT_GPIO4,MOT_GPIO5,MOT_GPIO6,MOT_GPIO7,MOT_GPIO8,MOT_GPIO9,MOT_GPIO10,MOT_GPIO11,MOT_GPIO12,MOT_GPIO13,MOT_GPIO14,MOT_GPIO15,MOT_GPIO16,MOT_GPIO17,MOT_GPIO18,MOT_GPIO19,MOT_GPIO20,MOT_GPIO21,MOT_GPIO22,MOT_GPIO23,MOT_GPIO24,MOT_GPIO25,MOT_GPIO26,MOT_GPIO27,MOT_GPIO28,MOT_GPIO29,MOT_GPIO30,MOT_GPIO31,SDM_PWM_SOC0,SDM_PWM_SOC1,SDM_PWM_SOC2,SDM_PWM_SOC3,SDM_PWM_SOC4,SDM_PWM_SOC5,SDM_PWM_SOC6,SDM_PWM_SOC7,SDM_PWM_SOC8,SDM_PWM_SOC9,SDM_PWM_SOC10,SDM_PWM_SOC11,SDM_PWM_SOC12,SDM_PWM_SOC13,SDM_PWM_SOC14,SDM_PWM_SOC15,ADC0_STRGI,ADC1_STRGI,ADC2_STRGI,ADC3_STRGI,ADCx_PTRGI0A,ADCx_PTRGI0B,ADCx_PTRGI0C,ADCx_PTRGI1A,ADCx_PTRGI1B,ADCx_PTRGI1C,ADCx_PTRGI2A,ADCx_PTRGI2B,ADCx_PTRGI2C,ADCx_PTRGI3A,ADCx_PTRGI3B,ADCx_PTRGI3C,VSC0_TRIG_IN0,VSC0_TRIG_IN1,VSC1_TRIG_IN0,VSC1_TRIG_IN1,RDC0_TRIG_IN0,RDC0_TRIG_IN1,RDC1_TRIG_IN0,RDC1_TRIG_IN1,QEI0_TRIG_IN,QEI1_TRIG_IN,QEI2_TRIG_IN,QEI3_TRIG_IN,QEI0_PAUSE,QEI1_PAUSE,QEI2_PAUSE,QEI3_PAUSE,QEO0_TRIG_IN0,QEO0_TRIG_IN1,QEO1_TRIG_IN0,QEO1_TRIG_IN1,QEO2_TRIG_IN0,QEO2_TRIG_IN1,QEO3_TRIG_IN0,QEO3_TRIG_IN1,SEI_TRIG_IN0,SEI_TRIG_IN1,SEI_TRIG_IN2,SEI_TRIG_IN3,SEI_TRIG_IN4,SEI_TRIG_IN5,SEI_TRIG_IN6,SEI_TRIG_IN7,CMP0_WIN,CMP1_WIN,CMP2_WIN,CMP3_WIN,CMP4_WIN,CMP5_WIN,CMP6_WIN,CMP7_WIN,GPTMR0_IN2,GPTMR0_IN3,GPTMR0_SYNCI,GPTMR1_IN2,GPTMR1_IN3,GPTMR1_SYNCI,GPTMR2_IN2,GPTMR2_IN3,GPTMR2_SYNCI,GPTMR3_IN2,GPTMR3_IN3,GPTMR3_SYNCI,GPTMR4_IN2,GPTMR4_IN3,GPTMR4_SYNCI,GPTMR5_IN2,GPTMR5_IN3,GPTMR5_SYNCI,GPTMR6_IN2,GPTMR6_IN3,GPTMR6_SYNCI,GPTMR7_IN2,GPTMR7_IN3,GPTMR7_SYNCI,PLB_IN_00,PLB_IN_01,PLB_IN_02,PLB_IN_03,PLB_IN_04,PLB_IN_05,PLB_IN_06,PLB_IN_07,PLB_IN_08,PLB_IN_09,PLB_IN_10,PLB_IN_11,PLB_IN_12,PLB_IN_13,PLB_IN_14,PLB_IN_15,PLB_IN_16,PLB_IN_17,PLB_IN_18,PLB_IN_19,PLB_IN_20,PLB_IN_21,PLB_IN_22,PLB_IN_23,PLB_IN_24,PLB_IN_25,PLB_IN_26,PLB_IN_27,PLB_IN_28,PLB_IN_29,PLB_IN_30,PLB_IN_31,PLB_IN_32,PLB_IN_33,PLB_IN_34,PLB_IN_35,PLB_IN_36,PLB_IN_37,PLB_IN_38,PLB_IN_39,PLB_IN_40,PLB_IN_41,PLB_IN_42,PLB_IN_43,PLB_IN_44,PLB_IN_45,PLB_IN_46,PLB_IN_47,PLB_IN_48,PLB_IN_49,PLB_IN_50,PLB_IN_51,PLB_IN_52,PLB_IN_53,PLB_IN_54,PLB_IN_55,PLB_IN_56,PLB_IN_57,PLB_IN_58,PLB_IN_59,PLB_IN_60,PLB_IN_61,PLB_IN_62,PLB_IN_63,PWM0_TRIG_IN0,PWM0_TRIG_IN1,PWM0_TRIG_IN2,PWM0_TRIG_IN3,PWM0_TRIG_IN4,PWM0_TRIG_IN5,PWM0_TRIG_IN6,PWM0_TRIG_IN7,PWM1_TRIG_IN0,PWM1_TRIG_IN1,PWM1_TRIG_IN2,PWM1_TRIG_IN3,PWM1_TRIG_IN4,PWM1_TRIG_IN5,PWM1_TRIG_IN6,PWM1_TRIG_IN7,PWM2_TRIG_IN0,PWM2_TRIG_IN1,PWM2_TRIG_IN2,PWM2_TRIG_IN3,PWM2_TRIG_IN4,PWM2_TRIG_IN5,PWM2_TRIG_IN6,PWM2_TRIG_IN7,PWM3_TRIG_IN0,PWM3_TRIG_IN1,PWM3_TRIG_IN2,PWM3_TRIG_IN3,PWM3_TRIG_IN4,PWM3_TRIG_IN5,PWM3_TRIG_IN6,PWM3_TRIG_IN7,CAN_PTPC0_CAP,CAN_PTPC1_CAP,UART_TRIG0,UART_TRIG1,SYNCTIMER_TRIG,TRGM_IRQ0,TRGM_IRQ1,TRGM_DMA0,TRGM_DMA1,MTG0_TRIG_IN0,MTG0_TRIG_IN1,MTG0_TRIG_IN2,MTG0_TRIG_IN3,MTG1_TRIG_IN0,MTG1_TRIG_IN1,MTG1_TRIG_IN2,MTG1_TRIG_IN3,ESC_TRIG_IN - TRGOCFG[%s] - no description available - 0x1000 - 32 - 0x00000000 - 0x000700FF - - - OUTINV - 1- Invert the output - 18 - 1 - read-write - - - FEDG2PEN - 1- The selected input signal falling edge will be convert to an pulse on output. - 17 - 1 - read-write - - - REDG2PEN - 1- The selected input signal rising edge will be convert to an pulse on output. - 16 - 1 - read-write - - - TRIGOSEL - This bitfield selects one of the TRGM inputs as output. - 0 - 8 - read-write - - - - - - - MTG0 - MTG0 - MTG - 0xf0490000 - - 0x0 - 0x3080 - registers - - - - 2 - 0x1000 - 0,1 - TRA[%s] - no description available - 0x0 - - control - tra&index0_control - 0x0 - 32 - 0x00000000 - 0x0000003F - - - CMD_FAIL_IRQ_EN - No description available - 5 - 1 - read-write - - - LOCK_IRQ_EN - No description available - 4 - 1 - read-write - - - CMD_FAIL_IRQ - No description available - 3 - 1 - write-only - - - LOCK_IRQ - No description available - 2 - 1 - write-only - - - SW_LOCK - No description available - 1 - 1 - read-write - - - OVALID_CLEAR - No description available - 0 - 1 - read-write - - - - - shift - tra&index0_shift - 0x4 - 32 - 0x00000000 - 0xE000077F - - - ACC_SHIFT_FAIL_IRQ - No description available - 31 - 1 - write-only - - - VEL_SHIFT_FAIL_IRQ - No description available - 30 - 1 - write-only - - - SHIFT_FAIL_EN - No description available - 29 - 1 - read-write - - - JER_SHIFT - No description available - 8 - 3 - read-write - - - ACC_SHIFT - No description available - 4 - 3 - read-write - - - VEL_SHIFT - No description available - 0 - 4 - read-write - - - - - link - tra&index0_link - 0x8 - 32 - 0x00000000 - 0x00007777 - - - LINK_CFG_3 - No description available - 12 - 3 - read-write - - - LINK_CFG_2 - No description available - 8 - 3 - read-write - - - LINK_CFG_1 - No description available - 4 - 3 - read-write - - - LINK_CFG_0 - No description available - 0 - 3 - read-write - - - - - 4 - 0x20 - 0,1,2,3 - CMD[%s] - no description available - 0x20 - - control - tra&index0_cmd&index1_control - 0x0 - 32 - 0x00000000 - 0xE000001F - - - PASS_IRQ - No description available - 31 - 1 - write-only - - - PASS_IRQ_EN - No description available - 30 - 1 - read-write - - - MODE - No description available - 29 - 1 - read-write - - - OBJECT - No description available - 0 - 5 - read-write - - - - - rev_preset - tra&index0_cmd&index1_rev_preset - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV_PRESET - No description available - 0 - 32 - read-write - - - - - pos_preset - tra&index0_cmd&index1_pos_preset - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS_PRESET - No description available - 0 - 32 - read-write - - - - - vel_preset - tra&index0_cmd&index1_vel_preset - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - VEL_PRESET - No description available - 0 - 32 - read-write - - - - - acc_preset - tra&index0_cmd&index1_acc_preset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_PRESET - No description available - 0 - 32 - read-write - - - - - jer_preset - tra&index0_cmd&index1_jer_preset - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - JER_PRESET - No description available - 0 - 32 - read-write - - - - - timestamp - tra&index0_cmd&index1_timestamp - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP - No description available - 0 - 32 - read-only - - - - - - lock_rev - tra&index0_lock_rev - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_REV - No description available - 0 - 32 - read-only - - - - - lock_pos - tra&index0_lock_pos - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_POS - No description available - 0 - 32 - read-only - - - - - lock_vel - tra&index0_lock_vel - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_VEL - No description available - 0 - 32 - read-only - - - - - lock_acc - tra&index0_lock_acc - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_ACC - No description available - 0 - 32 - read-only - - - - - lock_time - tra&index0_lock_time - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_TIME - No description available - 0 - 32 - read-only - - - - - step_limit_ctrl - tra&index0_step_limit_ctrl - 0xc0 - 32 - 0x00000000 - 0x00001F07 - - - POS_ONE_WAY_FORCE_MODE - No description available - 12 - 1 - read-write - - - POS_ONE_WAY_MODE - No description available - 11 - 1 - read-write - - - POS_ONE_WAY_EN - No description available - 10 - 1 - read-write - - - POS_STEP_MODE - No description available - 9 - 1 - read-write - - - POS_STEP_EN - No description available - 8 - 1 - read-write - - - VEL_ONE_WAY_MODE - No description available - 2 - 1 - read-write - - - VEL_ONE_WAY_EN - No description available - 1 - 1 - read-write - - - VEL_STEP_EN - No description available - 0 - 1 - read-write - - - - - vel_step_max - tra&index0_vel_step_max - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VEL_STEP_MAX - No description available - 0 - 32 - read-write - - - - - vel_step_min - tra&index0_vel_step_min - 0xc8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VEL_STEP_MIN - No description available - 0 - 32 - read-write - - - - - pos_step_max - tra&index0_pos_step_max - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - POS_STEP_MAX - No description available - 0 - 32 - read-write - - - - - pos_step_min - tra&index0_pos_step_min - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS_STEP_MIN - No description available - 0 - 32 - read-write - - - - - vel_limit_p - tra&index0_vel_limit_p - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - VEL_LIMIT_P - No description available - 0 - 32 - read-write - - - - - vel_limit_n - tra&index0_vel_limit_n - 0xd8 - 32 - 0x00000000 - 0xFFFFFFFF - - - VEL_LIMIT_N - No description available - 0 - 32 - read-write - - - - - - 4 - 0x20 - 0,1,2,3 - EVENT[%s] - no description available - 0x2000 - - control - event&index0_control - 0x0 - 32 - 0x00000000 - 0xFFFFC00F - - - ENABLE - No description available - 31 - 1 - read-write - - - SOURCE_MUX - No description available - 27 - 4 - read-write - - - OBJECT - No description available - 23 - 4 - read-write - - - MODE - No description available - 19 - 4 - read-write - - - DIR - No description available - 17 - 2 - read-write - - - DIR_MODE - No description available - 16 - 1 - read-write - - - OVER_MODE_CMP - No description available - 15 - 1 - read-write - - - TRIG_NUM - No description available - 14 - 1 - read-write - - - EVENT_OVER_IRQ_EN - No description available - 3 - 1 - read-write - - - EVENT_IRQ_EN - No description available - 2 - 1 - read-write - - - EVENT_OVER_IRQ - No description available - 1 - 1 - write-only - - - EVENT_IRQ - No description available - 0 - 1 - write-only - - - - - preset_0 - event&index0_preset_0 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRESET - No description available - 0 - 32 - read-write - - - - - preset_1 - event&index0_preset_1 - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRESET - No description available - 0 - 32 - read-write - - - - - preset_2 - event&index0_preset_2 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PRESET - No description available - 0 - 32 - read-write - - - - - preset_3 - event&index0_preset_3 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRESET - No description available - 0 - 32 - read-write - - - - - timestamp - event&index0_timestamp - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP - No description available - 0 - 32 - read-only - - - - - - sw_event - sw_event - 0x2080 - 32 - 0x00000000 - 0x00000001 - - - SW_EVENT_TRIG - No description available - 0 - 1 - read-write - - - - - sw_glb_reset - sw_glb_reset - 0x2084 - 32 - 0x00000000 - 0x00000001 - - - SW_GLB_RESET - No description available - 0 - 1 - write-only - - - - - filter_control - filter_control - 0x3000 - 32 - 0x00000000 - 0xE0FA3F7F - - - MUL_ERR_IRQ_0 - No description available - 31 - 1 - write-only - - - MUL_ERR_IRQ_1 - No description available - 30 - 1 - write-only - - - MUL_ERR_IRQ_EN - No description available - 29 - 1 - read-write - - - ERR_BYPASS_STATUS - No description available - 23 - 1 - read-only - - - ERR_BYPASS_F_I_EN - No description available - 22 - 1 - read-write - - - ERR_BYPASS_I_F_EN - No description available - 21 - 1 - read-write - - - SW_LOCK - No description available - 20 - 1 - read-write - - - TIMEOUT_EN - No description available - 19 - 1 - read-write - - - REV_INI_MODE - No description available - 17 - 1 - read-write - - - SEL_TIME1 - No description available - 12 - 2 - read-write - - - SEL_TIME0 - No description available - 10 - 2 - read-write - - - EN_TIME1 - No description available - 9 - 1 - read-write - - - EN_TIME0 - No description available - 8 - 1 - read-write - - - A_EN - No description available - 6 - 1 - read-write - - - ERR_INI - No description available - 5 - 1 - read-write - - - ERR_BYPASS_EN - No description available - 4 - 1 - read-write - - - FF_MODE - No description available - 3 - 1 - read-write - - - FF_EN - No description available - 2 - 1 - read-write - - - INIT_EN - No description available - 1 - 1 - read-write - - - ENABLE - No description available - 0 - 1 - read-write - - - - - filter_rev_value - filter_rev_value - 0x3010 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-write - - - - - filter_pos_value - filter_pos_value - 0x3014 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-write - - - - - filter_vel_value - filter_vel_value - 0x3018 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-write - - - - - filter_acc_value - filter_acc_value - 0x301c - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-write - - - - - filter_mot_sel - filter_mot_sel - 0x3020 - 32 - 0x00000000 - 0x3F3F3F3F - - - OUTPUT_VEL_SEL - No description available - 24 - 6 - read-write - - - OUTPUT_ACC_SEL - No description available - 16 - 6 - read-write - - - FILTER_VEL_SEL - No description available - 8 - 6 - read-write - - - FILTER_ACC_SEL - No description available - 0 - 6 - read-write - - - - - filter_stage_sel - filter_stage_sel - 0x3024 - 32 - 0x00000000 - 0x3FFFFFFF - - - STAGE5_SEL - No description available - 25 - 5 - read-write - - - STAGE4_SEL - No description available - 20 - 5 - read-write - - - STAGE3_SEL - No description available - 15 - 5 - read-write - - - STAGE2_SEL - No description available - 10 - 5 - read-write - - - STAGE1_SEL - No description available - 5 - 5 - read-write - - - STAGE0_SEL - No description available - 0 - 5 - read-write - - - - - filter_time_constant_tp - filter_time_constant_tp - 0x3028 - 32 - 0x00000000 - 0x00FFFFFF - - - TP - No description available - 0 - 24 - read-write - - - - - filter_time_constant_tz - filter_time_constant_tz - 0x302c - 32 - 0x00000000 - 0x00FFFFFF - - - TZ - No description available - 0 - 24 - read-write - - - - - filter_time_constant_tz_1 - filter_time_constant_tz_1 - 0x3030 - 32 - 0x00000000 - 0x00FFFFFF - - - TZ_1 - No description available - 0 - 24 - read-write - - - - - filter_zero_tz_sel - filter_zero_tz_sel - 0x3034 - 32 - 0x00000000 - 0x0000003F - - - STAGE5 - No description available - 5 - 1 - read-write - - - STAGE4 - No description available - 4 - 1 - read-write - - - STAGE3 - No description available - 3 - 1 - read-write - - - STAGE2 - No description available - 2 - 1 - read-write - - - STAGE1 - No description available - 1 - 1 - read-write - - - STAGE0 - No description available - 0 - 1 - read-write - - - - - filter_gain - filter_gain - 0x3038 - 32 - 0x00000000 - 0xC0FFFFFF - - - GAIN_T0_EN - No description available - 31 - 1 - read-write - - - GAIN_T1_EN - No description available - 30 - 1 - read-write - - - K - No description available - 0 - 24 - read-write - - - - - filter_stage_shift0 - filter_stage_shift0 - 0x303c - 32 - 0x00000000 - 0xFFFFFFFF - - - STAGE3_SHIFT1 - No description available - 28 - 4 - read-write - - - STAGE3_SHIFT0 - No description available - 24 - 4 - read-write - - - STAGE2_SHIFT1 - No description available - 20 - 4 - read-write - - - STAGE2_SHIFT0 - No description available - 16 - 4 - read-write - - - STAGE1_SHIFT1 - No description available - 12 - 4 - read-write - - - STAGE1_SHIFT0 - No description available - 8 - 4 - read-write - - - STAGE0_SHIFT1 - No description available - 4 - 4 - read-write - - - STAGE0_SHIFT0 - No description available - 0 - 4 - read-write - - - - - filter_stage_shift1 - filter_stage_shift1 - 0x3040 - 32 - 0x00000000 - 0x0000FFFF - - - STAGE5_SHIFT1 - No description available - 12 - 4 - read-write - - - STAGE5_SHIFT0 - No description available - 8 - 4 - read-write - - - STAGE4_SHIFT1 - No description available - 4 - 4 - read-write - - - STAGE4_SHIFT0 - No description available - 0 - 4 - read-write - - - - - filter_param_shift - filter_param_shift - 0x3044 - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_SHIFT_PARAM - No description available - 28 - 4 - read-write - - - VEL_SHIFT_PARAM - No description available - 24 - 4 - read-write - - - GAIN_K_SHIFT - No description available - 20 - 4 - read-write - - - GAIN_T0_SHIFT - No description available - 16 - 4 - read-write - - - GAIN_T1_SHIFT - No description available - 12 - 4 - read-write - - - TP_SHIFT - No description available - 8 - 4 - read-write - - - TZ_1_SHIFT - No description available - 4 - 4 - read-write - - - TZ_SHIFT - No description available - 0 - 4 - read-write - - - - - filter_time_shift - filter_time_shift - 0x3048 - 32 - 0x00000000 - 0x0000FFFF - - - ACC_SHIFT_TIME1 - No description available - 12 - 4 - read-write - - - VEL_SHIFT_TIME1 - No description available - 8 - 4 - read-write - - - ACC_SHIFT_TIME0 - No description available - 4 - 4 - read-write - - - VEL_SHIFT_TIME0 - No description available - 0 - 4 - read-write - - - - - filter_ff_shift - filter_ff_shift - 0x304c - 32 - 0x00000000 - 0x0000FFFF - - - OUTPUT_ACC_SHIFT - No description available - 12 - 4 - read-write - - - FILTER_ACC_SHIFT - No description available - 8 - 4 - read-write - - - OUTPUT_VEL_SHIFT - No description available - 4 - 4 - read-write - - - FILTER_VEL_SHIFT - No description available - 0 - 4 - read-write - - - - - filter_time1_sw_adjust - filter_time1_sw_adjust - 0x3050 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - No description available - 0 - 32 - read-write - - - - - filter_time0_sw_adjust - filter_time0_sw_adjust - 0x3054 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - No description available - 0 - 32 - read-write - - - - - filter_error_limit_l - filter_error_limit - 0x3060 - 32 - 0x00000000 - 0xFFFFFFFF - - - ERROR_LIMIT_L - No description available - 0 - 32 - read-write - - - - - filter_error_limit_h - filter_error_limit - 0x3064 - 32 - 0x00000000 - 0xFFFFFFFF - - - ERROR_LIMIT_H - No description available - 0 - 32 - read-write - - - - - filter_timeout_cnt - filter_timeout_cnt - 0x306c - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMEOUT_CNT - No description available - 0 - 32 - read-write - - - - - filter_rev_lock - filter_rev_lock - 0x3070 - 32 - 0x00000000 - 0xFFFFFFFF - - - REV_STATUS - No description available - 0 - 32 - read-only - - - - - filter_pos_lock - filter_pos_lock - 0x3074 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS_STATUS - No description available - 0 - 32 - read-only - - - - - filter_vel_lock - filter_vel_lock - 0x3078 - 32 - 0x00000000 - 0xFFFFFFFF - - - VEL_STATUS - No description available - 0 - 32 - read-only - - - - - filter_acc_lock - filter_acc_lock - 0x307c - 32 - 0x00000000 - 0xFFFFFFFF - - - ACC_STATUS - No description available - 0 - 32 - read-only - - - - - - - MTG1 - MTG1 - MTG - 0xf0494000 - - - VSC0 - VSC0 - VSC - 0xf04a0000 - - 0x0 - 0x128 - registers - - - - abc_mode - abc mode - 0x0 - 32 - 0x00000000 - 0x8FFF3338 - - - PHASE_ABSENT_MODE - whether using value_a and value_b instead of three phase - 31 - 1 - read-write - - - VALUE_C_WIDTH - numbers of value_c for each convert - 24 - 4 - read-write - - - VALUE_B_WIDTH - numbers of value_b for each convert - 20 - 4 - read-write - - - VALUE_A_WIDTH - numbers of value_a for each convert - 16 - 4 - read-write - - - VALUE_C_LOC - the adc index of value_c: -2'b:00: resevered; -2'b:01: from adc0; -2'b:10: from adc1; -2'b:11: from adc2; - 12 - 2 - read-write - - - VALUE_B_LOC - the adc index of value_b: -2'b:00: resevered; -2'b:01: from adc0; -2'b:10: from adc1; -2'b:11: from adc2; - 8 - 2 - read-write - - - VALUE_A_LOC - the adc index of value_a: -2'b:00: resevered; -2'b:01: from adc0; -2'b:10: from adc1; -2'b:11: from adc2; - 4 - 2 - read-write - - - ENABLE_VSC - enable vsc convert: -0: disable vsc convert -1: enable vsc convert - 3 - 1 - read-write - - - - - adc_chan_assign - assign adc_chan for value_a/b/c - 0x4 - 32 - 0x00000000 - 0x001F1F1F - - - VALUE_C_CHAN - value_c's adc chan - 16 - 5 - read-write - - - VALUE_B_CHAN - value_b's adc chan - 8 - 5 - read-write - - - VALUE_A_CHAN - value_a's adc chan - 0 - 5 - read-write - - - - - value_a_data_opt - value_a data operation mode - 0x8 - 32 - 0x00000000 - 0x0000FFFF - - - OPT_3 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 12 - 4 - read-write - - - OPT_2 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 8 - 4 - read-write - - - OPT_1 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 4 - 4 - read-write - - - OPT_0 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 0 - 4 - read-write - - - - - value_b_data_opt - value_b data operation mode - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - OPT_3 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 12 - 4 - read-write - - - OPT_2 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 8 - 4 - read-write - - - OPT_1 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 4 - 4 - read-write - - - OPT_0 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 0 - 4 - read-write - - - - - value_c_data_opt - value_c data operation mode - 0x18 - 32 - 0x00000000 - 0x0000FFFF - - - OPT_3 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 12 - 4 - read-write - - - OPT_2 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 8 - 4 - read-write - - - OPT_1 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 4 - 4 - read-write - - - OPT_0 - 0: PLUS_MUL_1 -1: PLUS_MUL_2 -5: PLUS_DIV_2 -6: PLUS_DIV_3 -7: PLUS_DIV_4 -8: MINUS MUL 1 -9: MINUS MUL 2 -13: MINUS DIV 2 -14: MINUS DIV 3 -15: MINUS DIV 4 - 0 - 4 - read-write - - - - - value_a_offset - value_a offset - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_A_OFFSET - value_a offset - 0 - 32 - read-write - - - - - value_b_offset - value_b_offset - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_B_OFFSET - value_b_offset - 0 - 32 - read-write - - - - - value_c_offset - value_c offset - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_C_OFFSET - value_c offset - 0 - 32 - read-write - - - - - irq_status - irq status - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_STATUS - irq status bit: -bit0: vsc convert done irq. -bit1: in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq. -bit2: value_c overflow during capture process. -bit3: value_b_overflow during capture process. -bit4: value_a_overflow during capture process. -bit5: adc2 chan not capture enough adc value. -bit6: adc1 chan not capture enough adc value. -bit7: adc0 chan not capture enough adc value. -bit8: position not got valid before pos_wait_cycle timeout. -bit9: adc2 wait cycle timeout. -bit10: adc1 wait cycle timeout. -bit11: adc0 wait cycle timeout. -bit12: trigger_in break vsc convert even if adc or position is ready. - 0 - 32 - read-write - - - - - value_a_sw - value_a software inject value - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_A_SW - value_a_sw - 0 - 32 - read-write - - - - - value_b_sw - value_b software inject value - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_B_SW - value_b_sw - 0 - 32 - read-write - - - - - value_c_sw - value_c software inject value - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE_C_SW - value_c_sw - 0 - 32 - read-write - - - - - value_sw_ready - software inject value_a/value_b/value_c ready - 0x3c - 32 - 0x00000000 - 0x00000001 - - - VALUE_SW_READY - software inject value_a/value_b/value_c ready - 0 - 1 - write-only - - - - - trigger_sw - software trigger event - 0x40 - 32 - 0x00000000 - 0x00000001 - - - TRIGGER_SW - software trigger to start waiting adc capture value, same as hardwire trigger_in - 0 - 1 - write-only - - - - - timelock - timestamp mode and postion capture ctrl - 0x44 - 32 - 0x00000000 - 0x0000303F - - - POSITION_CAPTURE_MODE - postion capture mode: -00: position use last valid data when adc value capture finish -01: position use frist valid data after adc value capture -10: position use last valid data before adc value capture -other: reserved - 12 - 2 - read-write - - - ADC_TIMESTAMP_SEL - adc timestamp select： -0：reserved; -1: from value_a; -2: from value_b; -3: from value_c; - 4 - 2 - read-write - - - VALUE_COUNTER_SEL - adc timestamp use which number index of adc_timestamp_sel used. - 0 - 4 - read-write - - - - - position_sw - position software inject value - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - POSITION_SW - position_sw - 0 - 32 - read-write - - - - - adc_wait_cycle - adc wait cycle after trigger adc capture event - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - ADC_WAIT_CYCLE - adc wait cycle after trigger adc capture event - 0 - 32 - read-write - - - - - pos_wait_cycle - pos wait cycle after trigger adc capture event - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - POS_WAIT_CYCLE - position wait cycle after trigger adc capture event - 0 - 32 - read-write - - - - - irq_enable - irq bit enable - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - IRQ_ENABLE - irq enable bit: -bit0: vsc convert done irq. -bit1: in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq. -bit2: value_c overflow during capture process. -bit3: value_b_overflow during capture process. -bit4: value_a_overflow during capture process. -bit5: adc2 chan not capture enough adc value. -bit6: adc1 chan not capture enough adc value. -bit7: adc0 chan not capture enough adc value. -bit8: position not got valid before pos_wait_cycle timeout. -bit9: adc2 wait cycle timeout. -bit10: adc1 wait cycle timeout. -bit11: adc0 wait cycle timeout. -bit12: trigger_in break vsc convert even if adc or position is ready. - 0 - 32 - read-write - - - - - adc_phase_tolerate - adc phase tolerate - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADC_PHASE_TOLERATE - in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq. - 0 - 32 - read-write - - - - - pos_pole - position pole num - 0x5c - 32 - 0x00000000 - 0x0000FFFF - - - POS_POLE - pole number - 0 - 16 - read-write - - - - - id_posedge - posedge order Id value - 0x100 - 32 - 0x00000000 - 0xFFFFFFFF - - - ID_POSEDGE - posedge order Id value - 0 - 32 - read-only - - - - - iq_posedge - posedge order Iq value - 0x104 - 32 - 0x00000000 - 0xFFFFFFFF - - - IQ_POSEDGE - posedge order Iq value - 0 - 32 - read-only - - - - - id_negedge - negedge order Id value - 0x108 - 32 - 0x00000000 - 0xFFFFFFFF - - - ID_NEGEDGE - negedge order Id value - 0 - 32 - read-only - - - - - iq_negedge - negedge order Iq value - 0x10c - 32 - 0x00000000 - 0xFFFFFFFF - - - IQ_NEGEDGE - negedge order Iq value - 0 - 32 - read-only - - - - - alpha_posedge - posedge order alpha value - 0x110 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALPHA_POSEDGE - posedge order alpha value - 0 - 32 - read-only - - - - - beta_posedge - posedge order beta value - 0x114 - 32 - 0x00000000 - 0xFFFFFFFF - - - BETA_POSEDGE - posedge order beta value - 0 - 32 - read-only - - - - - alpha_negedge - negedge order alpha value - 0x118 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALPHA_NEGEDGE - negedge order alpha value - 0 - 32 - read-only - - - - - beta_negedge - negedge order beta value - 0x11c - 32 - 0x00000000 - 0xFFFFFFFF - - - BETA_NEGEDGE - negedge order beta value - 0 - 32 - read-only - - - - - timestamp_locked - timestamp_locked - 0x120 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP_LOCKED - timestamp_locked - 0 - 32 - read-only - - - - - debug_status0 - debug_status0 - 0x124 - 32 - 0x00000000 - 0x00000FFF - - - VALUE_A_COUNTER - value_a_counter - 8 - 4 - read-only - - - VALUE_B_COUNTER - value_b_counter - 4 - 4 - read-only - - - VALUE_C_COUNTER - value_c_counter - 0 - 4 - read-only - - - - - - - VSC1 - VSC1 - VSC - 0xf04a4000 - - - CLC0 - CLC0 - CLC - 0xf04b0000 - - 0x0 - 0x204 - registers - - - - 2 - 0x100 - vd,vq - VDVQ_CHAN[%s] - no description available - 0x0 - - mode - &index0 mode ctrl - 0x0 - 32 - 0x00000000 - 0x810107FF - - - ENABLE_CLC - enable CLC - 31 - 1 - read-write - - - MASK_MODE - open mode: CLC keep working even if bad irq status ocurred - 24 - 1 - read-write - - - DQ_MODE - dq mode - 16 - 1 - read-write - - - ENABLE_IRQ - enable irq: -irq_data_in_forbid , // 10 -irq_forb_err_boundary , // 9 -irq_p3z3_over_lo , // 8 -irq_p3z3_over_hi , // 7 -irq_p3z3_err_boundary , // 6 -irq_z2_over_sf , // 5 -irq_z2_over_lo , // 4 -irq_z2_over_hi , // 3 -irq_z2_err_boundary , // 2 -irq_coef_err_boundary , // 1 -irq_valid_clc // 0 - 0 - 11 - read-write - - - - - adc_expect - &index0 adc expect - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADC_EXPECT - adc expect value - 0 - 32 - read-write - - - - - adc_chan - &index0 adc used channel - 0x8 - 32 - 0x00000000 - 0x0000001F - - - ADC_CHAN - adc used chan ID - 0 - 5 - read-write - - - - - adc_offset - &index0 adc used offset - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - ADC_OFFSET - adc used offset - 0 - 32 - read-write - - - - - eadc_lowth - &index0 eadc_lowth value used in error adc cofficient selection - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_LOWTH - if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - 0 - 32 - read-write - - - - - eadc_highth - &index0 eadc_highth value used in error adc cofficient selection - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_HIGHTH - if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - 0 - 32 - read-write - - - - - eadc_midlowth - &index0 eadc_midlowth value used in error adc cofficient selection - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_MIDLOWTH - if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - 0 - 32 - read-write - - - - - eadc_midhighth - &index0 eadc_midhighth value used in error adc cofficient selection - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_MIDHIGHTH - if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - 0 - 32 - read-write - - - - - p2z2_clamp_lo - &index0 2p2z output clamp low threshold - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - 2P2Z_CLAMP_LO - 2p2z output clamp low threshold - 0 - 32 - read-write - - - - - p2z2_clamp_hi - &index0 2p2z output clamp high threshold - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - 2P2Z_CLAMP_HI - 2p2z output clamp high threshold - 0 - 32 - read-write - - - - - p3z3_clamp_lo - &index0 3p3z output clamp low threshold - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - 3P3Z_CLAMP_LO - 3p3z output clamp low threshold - 0 - 32 - read-write - - - - - p3z3_clamp_hi - &index0 3p3z output clamp high threshold - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - 3P3Z_CLAMP_HI - 3p3z output clamp high threshold - 0 - 32 - read-write - - - - - 3 - 0x20 - 0,1,2 - COEFF[%s] - no description available - 0x40 - - coeff_b0 - &index0 zone &index1 b0 - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_B0 - coefficient b0 - 0 - 32 - read-write - - - - - coeff_b1 - &index0 zone &index1 b1 - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_B1 - coefficient b1 - 0 - 32 - read-write - - - - - coeff_b2 - &index0 zone &index1 b2 - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_B2 - coefficient b2 - 0 - 32 - read-write - - - - - coeff_b3 - &index0 zone &index1 b3 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_B3 - coefficient b3 - 0 - 32 - read-write - - - - - coeff_a0 - &index0 zone &index1 a0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_A0 - coefficient a0 - 0 - 32 - read-write - - - - - coeff_a1 - &index0 zone &index1 a1 - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_A1 - coefficient a1 - 0 - 32 - read-write - - - - - coeff_a2 - &index0 zone &index1 a2 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - COEFF_A2 - coefficient a2 - 0 - 32 - read-write - - - - - coeff_ks - &index0 zone &index1 kscaling - 0x1c - 32 - 0x00000000 - 0x0000001F - - - COEFF_KSCALING - coefficient kscaling - 0 - 5 - read-write - - - - - - pwm_period - &index0 pwm_period - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PWM_PERIOD - pwm_period - 0 - 32 - read-write - - - - - output_value - &index0 output value - 0xa4 - 32 - 0x00000000 - 0xFFFFFFFF - - - OUTPUT_VALUE - output_value - 0 - 32 - read-only - - - - - timestamp - &index0 adc timestamp used - 0xa8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIMESTAMP - timestamp - 0 - 32 - read-only - - - - - eadc_curr - &index0 error adc latest value - 0xac - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_CURR - error adc latest value - 0 - 32 - read-write - - - - - eadc_pre0 - &index0 error adc previous0 value - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_PRE0 - error adc previous 0 value - 0 - 32 - read-write - - - - - eadc_pre1 - &index0 error adc previous1 value - 0xb4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EADC_PRE1 - error adc previous 1 value - 0 - 32 - read-write - - - - - p2z2_curr - &index0 2p2z latest value - 0xb8 - 32 - 0x00000000 - 0xFFFFFFFF - - - 2P2Z_CURR - 2p2z latest value - 0 - 32 - read-write - - - - - p2z2_pre0 - &index0 2p2z previous0 value - 0xbc - 32 - 0x00000000 - 0xFFFFFFFF - - - 2P2Z_PRE0 - 2p2z previous 0 value - 0 - 32 - read-write - - - - - p3z3_curr - &index0 3p3z latest value - 0xc4 - 32 - 0x00000000 - 0xFFFFFFFF - - - 3P3Z_CURR - 3p3z latest value - 0 - 32 - read-write - - - - - p3z3_forbid_lo - &index0 3p3z output forbid low threshold - 0xcc - 32 - 0x00000000 - 0xFFFFFFFF - - - 3P3Z_FORBID_LO - 3p3z output forbid low threshold - 0 - 32 - read-write - - - - - p3z3_forbid_md - &index0 3p3z output forbid middle threshold - 0xd0 - 32 - 0x00000000 - 0xFFFFFFFF - - - 3P3Z_FORBID_MD - 3p3z output forbid middle threshold - 0 - 32 - read-write - - - - - p3z3_forbid_hi - &index0 3p3z output forbid high threshold - 0xd4 - 32 - 0x00000000 - 0xFFFFFFFF - - - 3P3Z_FORBID_HI - 3p3z output forbid high threshold - 0 - 32 - read-write - - - - - adc_sw - &index0 adc software inject value - 0xe0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADC_SW - adc software inject value - 0 - 32 - read-write - - - - - status - &index0 irq_status - 0xfc - 32 - 0x00000000 - 0x000007FF - - - STATUS - status, write 1 to clear it. : -irq_data_in_forbid , // 10 -irq_forb_err_boundary , // 9 -irq_p3z3_over_lo , // 8 -irq_p3z3_over_hi , // 7 -irq_p3z3_err_boundary , // 6 -irq_z2_over_sf , // 5 -irq_z2_over_lo , // 4 -irq_z2_over_hi , // 3 -irq_z2_err_boundary , // 2 -irq_coef_err_boundary , // 1 -irq_valid_clc // 0 - 0 - 11 - write-only - - - - - - dq_adc_sw_ready - enable d/q chan software inject adc value - 0x200 - 32 - 0x00000000 - 0x00000001 - - - DQ_ADC_SW_READY - enable d/q chan software inject adc value - 0 - 1 - write-only - - - - - - - CLC1 - CLC1 - CLC - 0xf04b4000 - - - ENET0 - ENET0 - ENET - 0xf1400000 - - 0x0 - 0x3028 - registers - - - - MACCFG - MAC Configuration Register - 0x0 - 32 - 0x00000000 - 0x7FFFFFFF - - - SARC - Source Address Insertion or Replacement Control - This field controls the source address insertion or replacement for all transmitted frames. -Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: -- 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. -- 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -- 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. -Note: - Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, -that is, the current frame does not use the updated value. -- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - 28 - 3 - read-write - - - TWOKPE - IEEE 802.3as Support for 2K Packets - When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. -When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. -When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. -When Bit 20 is set, setting this bit has no effect on Giant Frame status. - 27 - 1 - read-write - - - SFTERR - SMII Force Transmit Error - When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - 26 - 1 - read-write - - - CST - CRC Stripping for Type Frames - When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. -This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - 25 - 1 - read-write - - - TC - Transmit Configuration in RGMII, SGMII, or SMII - When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - or SGMII port. When this bit is reset, no such information is driven to the PHY. -This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - 24 - 1 - read-write - - - WD - Watchdog Disable - When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - 23 - 1 - read-write - - - JD - Jabber Disable - When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. -When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - 22 - 1 - read-write - - - BE - Frame Burst Enable - When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - 21 - 1 - read-write - - - JE - Jumbo Frame Enable - When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - 20 - 1 - read-write - - - IFG - Inter-Frame Gap - These bits control the minimum IFG between frames during transmission. -- 000: 96 bit times -- 001: 88 bit times -- 010: 80 bit times - ... -- 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). -Lower values are not considered. -In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - 17 - 3 - read-write - - - DCRS - Disable Carrier Sense During Transmission - When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. -When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - 16 - 1 - read-write - - - PS - Port Select - This bit selects the Ethernet line speed. -- 0: For 1000 Mbps operations -- 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. -In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, -this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - 15 - 1 - read-write - - - FES - Speed - This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: -- 0: 10 Mbps -- 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. -This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. -This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. -In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. -In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - 14 - 1 - read-write - - - DO - Disable Receive Own - When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. -When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. -This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - 13 - 1 - read-write - - - LM - Loopback Mode - When this bit is set, the MAC operates in the loopback mode at GMII or MII. -The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - 12 - 1 - read-write - - - DM - Duplex Mode - When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - 11 - 1 - read-write - - - IPC - Checksum Offload -When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. -It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) -of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. -The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) -and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). -When this bit is reset, this function is disabled. -When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - 10 - 1 - read-write - - - DR - Disable Retry -When this bit is set, the MAC attempts only one transmission. -When a collision occurs on the GMII or MII interface, -the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. -When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - 9 - 1 - read-write - - - LUD - Link Up or Down - This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: -- 0: Link Down -- 1: Link Up - 8 - 1 - read-write - - - ACS - Automatic Pad or CRC Stripping - When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. -All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. -When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - 7 - 1 - read-write - - - BL - Back-Off Limit - The Back-Off limit determines the random integer number (r) of slot time delays - (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. -This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. -- 00: k= min (n, 10) -- 01: k = min (n, 8) -- 10: k = min (n, 4) -- 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - 5 - 2 - read-write - - - DC - Deferral Check - When this bit is set, the deferral check function is enabled in the MAC. -The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, -when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, -but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. -For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, -the transmitter transmits and collision happens. -Because of collision, the transmitter needs to back off and then defer again after back off completion. -In such a scenario, the deferral timer is reset to 0 and it is restarted. - 4 - 1 - read-write - - - TE - Transmitter Enable - When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - 3 - 1 - read-write - - - RE - Receiver Enable - When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, -the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - 2 - 1 - read-write - - - PRELEN - Preamble Length for Transmit frames - These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - The preamble reduction occurs only when the MAC is operating in the full-duplex mode. -- 2'b00: 7 bytes of preamble -- 2'b01: 5 bytes of preamble -- 2'b10: 3 bytes of preamble -- 2'b11: Reserved - 0 - 2 - read-write - - - - - MACFF - MAC Frame Filter - 0x4 - 32 - 0x00000000 - 0x803087FF - - - RA - Receive All - When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. -The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, -the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - 31 - 1 - read-write - - - DNTU - Drop non-TCP/UDP over IP Frames - When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. -When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - 21 - 1 - read-write - - - IPFE - Layer 3 and Layer 4 Filter Enable - When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, -this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - 20 - 1 - read-write - - - VTFE - VLAN Tag Filter Enable - When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. -When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - 15 - 1 - read-write - - - HPF - Hash or Perfect Filter - When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. -When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - 10 - 1 - read-write - - - SAF - Source Address Filter Enable - When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - 9 - 1 - read-write - - - SAIF - SA Inverse Filtering -When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. -When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - 8 - 1 - read-write - - - PCF - Pass Control Frames - These bits control the forwarding of all control frames (including unicast and multicast Pause frames). -- 00: MAC filters all control frames from reaching the application. -- 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. -- 10: MAC forwards all control frames to application even if they fail the Address Filter. -- 11: MAC forwards control frames that pass the Address Filter. -The following conditions should be true for the Pause frames processing: -- Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. -- Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. -- Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. -Note: This field should be set to 01 only when the Condition 1 is true, -that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. -Otherwise, the Pause frame filtering may be inconsistent. -When Condition 1 is false, the Pause frames are considered as generic control frames. -Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, -you should set the PCF field to 10 or 11 (as required by the application). - 6 - 2 - read-write - - - DBF - Disable Broadcast Frames - When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. -When this bit is reset, the AFM module passes all received broadcast frames. - 5 - 1 - read-write - - - PM - Pass All Multicast -When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. -When reset, filtering of multicast frame depends on HMC bit. - 4 - 1 - read-write - - - DAIF - DA Inverse Filtering - When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. -When reset, normal filtering of frames is performed. - 3 - 1 - read-write - - - HMC - Hash Multicast -When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, -the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - 2 - 1 - read-write - - - HUC - Hash Unicast - When set, the MAC performs destination address filtering of unicast frames according to the hash table. -When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - 1 - 1 - read-write - - - PR - Promiscuous Mode -When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - 0 - 1 - read-write - - - - - HASH_H - Hash Table High Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HTH - Hash Table High - This field contains the upper 32 bits of the Hash table. - 0 - 32 - read-write - - - - - HASH_L - Hash Table Low Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - HTL - Hash Table Low - This field contains the lower 32 bits of the Hash table. - 0 - 32 - read-write - - - - - GMII_ADDR - GMII Address Register - 0x10 - 32 - 0x00000000 - 0x0000FFFF - - - PA - Physical Layer Address - This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - 11 - 5 - read-write - - - GR - GMII Register - These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - 6 - 5 - read-write - - - CR - CSR Clock Range - The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. -The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. -The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) -ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. -- 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. -- 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. -- 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. -- 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. -- 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. -- 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. -- 0110, 0111: Reserved -When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. -For example, -when CSR clock is of 100 MHz frequency and you program these bits as 1010, -then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. -Program the following values only if the interfacing chips support faster MDC clocks. -- 1000: CSR clock/4 -- 1001: CSR clock/6 -- 1010: CSR clock/8 -- 1011: CSR clock/10 -- 1100: CSR clock/12 -- 1101: CSR clock/14 -- 1110: CSR clock/16 -- 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - 2 - 4 - read-write - - - GW - GMII Write - When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, -it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - 1 - 1 - read-write - - - GB - GMII Busy - This bit should read logic 0 before writing to Register 4 and Register 5. -During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - Register 5 is invalid until this bit is cleared by the MAC. -Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. -Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. -The subsequent read or write operation should happen only after the previous operation is complete. -Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, -there is no change in the functionality of this bit even when the PHY is not present. - 0 - 1 - read-write - - - - - GMII_DATA - GMII Data Register - 0x14 - 32 - 0x00000000 - 0x0000FFFF - - - GD - GMII Data - This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation -or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - 0 - 16 - read-write - - - - - FLOWCTRL - Flow Control Register - 0x18 - 32 - 0x00000000 - 0xFFFF00BF - - - PT - Pause Time - This field holds the value to be used in the Pause Time field in the transmit control frame. -If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - 16 - 16 - read-write - - - DZPQ - Disable Zero-Quanta Pause - When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of -the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). -When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - 7 - 1 - read-write - - - PLT - Pause Low Threshold - This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. -The threshold values should be always less than the Pause Time configured in Bits[31:16]. - For example, if PT = 100H (256 slot-times), and PLT = 01, -then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. -The following list provides the threshold values for different values: -- 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). -- 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). -- 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). -- 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - 4 - 2 - read-write - - - UP - Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. -When this bit is set, the MAC can also detect Pause frames with unicast address of the station. -This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. -When this bit is reset, the MAC only detects Pause frames with unique multicast address. - 3 - 1 - read-write - - - RFE - Receive Flow Control Enable - When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - 2 - 1 - read-write - - - TFE - Transmit Flow Control Enable -In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. -When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. -In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - 1 - 1 - read-write - - - FCB_BPA - Flow Control Busy or Backpressure Activate - This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. -In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - To initiate a Pause frame, the Application must set this bit to 1'b1. -During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. -After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. -The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, -when this bit is set (and TFE is set), then backpressure is asserted by the MAC. -During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. -This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. -When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - 0 - 1 - read-write - - - - - VLAN_TAG - VLAN Tag Register - 0x1c - 32 - 0x00000000 - 0x000FFFFF - - - VTHM - VLAN Tag Hash Table Match Enable - When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). -A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. -When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, -the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - 19 - 1 - read-write - - - ESVL - Enable S-VLAN - When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - 18 - 1 - read-write - - - VTIM - VLAN Tag Inverse Match Enable -When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - The frames with matched VLAN Tag are marked as matched. - 17 - 1 - read-write - - - ETV - Enable 12-Bit VLAN Tag Comparison - When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, -only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. -When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - 16 - 1 - read-write - - - VL - VLAN Tag Identifier for Receive Frames - This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. -The following list describes the bits of this field: - - Bits [15:13]: User Priority -- Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) -- Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - 0 - 16 - read-write - - - - - RWKFRMFILT - Remote Wake-Up Frame Filter Register - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - WKUPFRMFILT - This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). -The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. -The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. -Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - 0 - 32 - read-write - - - - - PMT_CSR - PMT Control and Status Register - 0x2c - 32 - 0x00000000 - 0x9F000267 - - - RWKFILTRST - Remote Wake-Up Frame Filter Register Pointer Reset -When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - 31 - 1 - read-write - - - RWKPTR - Remote Wake-up FIFO Pointer -This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, -the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - 24 - 5 - read-write - - - GLBLUCAST - Global Unicast -When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - 9 - 1 - read-write - - - RWKPRCVD - Remote Wake-Up Frame Received -When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - 6 - 1 - read-write - - - MGKPRCVD - Magic Packet Received -When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - 5 - 1 - read-write - - - RWKPKTEN - Remote Wake-Up Frame Enable -When set, enables generation of a power management event because of remote wake-up frame reception. - 2 - 1 - read-write - - - MGKPKTEN - Magic Packet Enable -When set, enables generation of a power management event because of magic packet reception. - 1 - 1 - read-write - - - PWRDWN - Power Down -When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. -This bit is then self-cleared and the power-down mode is disabled. -The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. -The frames, received by the MAC after this bit is cleared, are forwarded to the application. -This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. -Note: You can gate-off the CSR clock during the power-down mode. -However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - 0 - 1 - read-write - - - - - LPI_CSR - LPI Control and Status Register - 0x30 - 32 - 0x00000000 - 0x000F030F - - - LPITXA - LPI TX Automate -This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. -This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, -the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. -The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. -If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), -when the MAC is in the LPI mode, the MAC exits the LPI mode. -When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - 19 - 1 - read-write - - - PLSEN - PHY Link Status Enable -This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. -When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - 18 - 1 - read-write - - - PLS - PHY Link Status -This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. -When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - 17 - 1 - read-write - - - LPIEN - LPI Enable -When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. -This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - 16 - 1 - read-write - - - RLPIST - Receive LPI State -When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - 9 - 1 - read-write - - - TLPIST - Transmit LPI State -When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - 8 - 1 - read-write - - - RLPIEX - Receive LPI Exit -When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. -This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 3 - 1 - read-write - - - RLPIEN - Receive LPI Entry -When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. -Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - 2 - 1 - read-write - - - TLPIEX - Transmit LPI Exit -When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - 1 - 1 - read-write - - - TLPIEN - Transmit LPI Entry - When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - 0 - 1 - read-write - - - - - LPI_TCR - LPI Timers Control Register - 0x34 - 32 - 0x00000000 - 0x03FFFFFF - - - LST - LPI LS TIMER -This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. -The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - 16 - 10 - read-write - - - TWT - LPI TW TIMER -This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - the LPI pattern to the PHY and before it resumes the normal transmission. -The TLPIEX status bit is set after the expiry of this timer. - 0 - 16 - read-write - - - - - INTR_STATUS - Interrupt Status Register - 0x38 - 32 - 0x00000000 - 0x00000EFF - - - GPIIS - GPI Interrupt Status -When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. -This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - When the GPIO feature is not enabled, this bit is reserved. - 11 - 1 - read-only - - - LPIIS - LPI Interrupt Status -When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. -This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - 10 - 1 - read-only - - - TSIS - Timestamp Interrupt Status -When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: -- The system time value equals or exceeds the value specified in the Target Time High and Low registers. -- There is an overflow in the seconds register. - - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - 9 - 1 - read-only - - - MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 7 - 1 - read-only - - - MMCTXIS - MMC Transmit Interrupt Status -This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 6 - 1 - read-only - - - MMCRXIS - MMC Receive Interrupt Status -This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - 5 - 1 - read-only - - - MMCIS - MMC Interrupt Status -This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - 4 - 1 - read-only - - - PMTIS - PMT Interrupt Status -This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). -This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - 3 - 1 - read-only - - - PCSANCIS - PCS Auto-Negotiation Complete -This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation to the AN Status register. - 2 - 1 - read-only - - - PCSLCHGIS - PCS Link Status Changed -This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). -This bit is cleared when you perform a read operation on the AN Status register. - 1 - 1 - read-only - - - RGSMIIIS - RGMII or SMII Interrupt Status -This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). -This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - 0 - 1 - read-only - - - - - INTR_MASK - Interrupt Mask Register - 0x3c - 32 - 0x00000000 - 0x0000060F - - - LPIIM - LPI Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - 10 - 1 - read-write - - - TSIM - Timestamp Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - 9 - 1 - read-write - - - PMTIM - PMT Interrupt Mask - When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - 3 - 1 - read-write - - - PCSANCIM - PCS AN Completion Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - 2 - 1 - read-write - - - PCSLCHGIM - PCS Link Status Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - 1 - 1 - read-write - - - RGSMIIIM - RGMII or SMII Interrupt Mask -When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - 0 - 1 - read-write - - - - - MAC_ADDR_0_HIGH - MAC Address 0 High Register - 0x40 - 32 - 0x00000000 - 0x8000FFFF - - - AE - Address Enable - This bit is RO. The bit value is fixed at 1. - 31 - 1 - read-only - - - ADDRHI - MAC Address0 [47:32] - This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 16 - read-write - - - - - MAC_ADDR_0_LOW - MAC Address 0 Low Register - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address0 [31:0] - This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - 0 - 32 - read-write - - - - - 4 - 0x8 - 1,2,3,4 - MAC_ADDR[%s] - no description available - 0x48 - - HIGH - MAC Address High Register - 0x0 - 32 - 0x00000000 - 0xFF00FFFF - - - AE - Address Enable -When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - 31 - 1 - read-write - - - SA - Source Address -When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - 30 - 1 - read-write - - - MBC - Mask Byte Control -These bits are mask control bits for comparison of each of the MAC Address bytes. -When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. -Each bit controls the masking of the bytes as follows: -- Bit 29: Register 18[15:8] -- Bit 28: Register 18[7:0] -- Bit 27: Register 19[31:24] - -... -- Bit 24: Register 19[7:0] -You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - 24 - 6 - read-write - - - ADDRHI - MAC Address1 [47:32] -This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - 0 - 16 - read-write - - - - - LOW - MAC Address Low Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - MAC Address1 [31:0] -This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - 0 - 32 - read-write - - - - - - XMII_CSR - SGMII/RGMII/SMII Control and Status Register - 0xd8 - 32 - 0x00000000 - 0x0000003F - - - FALSCARDET - False Carrier Detected - This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 5 - 1 - read-write - - - JABTO - Jabber Timeout - This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - 4 - 1 - read-write - - - LNKSTS - Link Status - This bit indicates whether the link between the local PHY and the remote PHY is up or down. -It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. -The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - 3 - 1 - read-write - - - LNKSPEED - Link Speed - This bit indicates the current speed of the link: -- 00: 2.5 MHz -- 01: 25 MHz -- 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - 1 - 2 - read-write - - - LNKMOD - Link Mode - This bit indicates the current mode of operation of the link: -- 1’b0: Half-duplex mode -- 1’b1: Full-duplex mode - 0 - 1 - read-write - - - - - WDOG_WTO - Watchdog Timeout Register - 0xdc - 32 - 0x00000000 - 0x00013FFF - - - PWE - Programmable Watchdog Enable - When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. -When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - 16 - 1 - read-write - - - WTO - Watchdog Timeout -When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, -this field is used as watchdog timeout for a received frame. - If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. -Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). -Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - 0 - 14 - read-write - - - - - mmc_cntrl - MMC Control establishes the operating mode of MMC. - 0x100 - 32 - 0x00000000 - 0x0000013F - - - UCDBC - Update MMC Counters for Dropped Broadcast Frames -When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - When reset, the MMC Counters are not updated for dropped Broadcast frames. - 8 - 1 - read-write - - - CNTPRSTLVL - Full-Half Preset -When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half -- 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half -- 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full -- 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full -- 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - 5 - 1 - read-write - - - CNTPRST - Counters Preset -When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. -This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - 4 - 1 - read-write - - - CNTFREEZ - MMC Counter Freeze -When this bit is set, it freezes all MMC counters to their current value. -Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - 3 - 1 - read-write - - - RSTONRD - Reset on Read -When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - 2 - 1 - read-write - - - CNTSTOPRO - Counter Stop Rollover -When this bit is set, the counter does not roll over to zero after reaching the maximum value. - 1 - 1 - read-write - - - CNTRST - Counters Reset -When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - 0 - 1 - read-write - - - - - mmc_intr_rx - MMC Receive Interrupt - 0x104 - 32 - 0x00000000 - 0x03FFFFFF - - - RXCTRLFIS - MMC Receive Control Frame Counter Interrupt Status -This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIS - MMC Receive Error Frame Counter Interrupt Status -This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIS - MMC Receive Watchdog Error Frame Counter Interrupt Status -This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIS - MMC Receive VLAN Good Bad Frame Counter Interrupt Status -This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIS - MMC Receive FIFO Overflow Frame Counter Interrupt Status -This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIS - MMC Receive Pause Frame Counter Interrupt Status -This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIS - MMC Receive Out Of Range Error Frame Counter Interrupt Status. -This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIS - MMC Receive Length Error Frame Counter Interrupt Status -This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIS - MMC Receive Unicast Good Frame Counter Interrupt Status -This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIS - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. -This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIS - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIS - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIS - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIS - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIS - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIS - MMC Receive Oversize Good Frame Counter Interrupt Status -This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIS - MMC Receive Undersize Good Frame Counter Interrupt Status -This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIS - MMC Receive Jabber Error Frame Counter Interrupt Status -This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIS - MMC Receive Runt Frame Counter Interrupt Status -This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIS - MMC Receive Alignment Error Frame Counter Interrupt Status -This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIS - MMC Receive CRC Error Frame Counter Interrupt Status -This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIS - MMC Receive Multicast Good Frame Counter Interrupt Status -This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIS - MMC Receive Broadcast Good Frame Counter Interrupt Status -This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status -This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status -This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXGBFRMIS - MMC Receive Good Bad Frame Counter Interrupt Status -This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_tx - MMC Transmit Interrupt - 0x108 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIS - MMC Transmit Oversize Good Frame Counter Interrupt Status -This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIS - MMC Transmit VLAN Good Frame Counter Interrupt Status -This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIS - MMC Transmit Pause Frame Counter Interrupt Status -This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIS - MMC Transmit Excessive Deferral Frame Counter Interrupt Status -This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIS - MMC Transmit Good Frame Counter Interrupt Status -This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status -This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIS - MMC Transmit Carrier Error Frame Counter Interrupt Status -This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIS - MMC Transmit Excessive Collision Frame Counter Interrupt Status -This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIS - MMC Transmit Late Collision Frame Counter Interrupt Status -This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIS - MMC Transmit Deferred Frame Counter Interrupt Status -This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIS - MMC Transmit Multiple Collision Good Frame Counter Interrupt Status -This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIS - MMC Transmit Single Collision Good Frame Counter Interrupt Status -This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIS - MMC Transmit Underflow Error Frame Counter Interrupt Status -This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIS - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIS - MMC Transmit Multicast Good Bad Frame Counter Interrupt Status -The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIS - MMC Transmit Unicast Good Bad Frame Counter Interrupt Status -This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIS - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIS - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIS - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIS - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIS - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIS - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status -This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIS - MMC Transmit Multicast Good Frame Counter Interrupt Status -This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIS - MMC Transmit Broadcast Good Frame Counter Interrupt Status -This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIS - MMC Transmit Good Bad Frame Counter Interrupt Status -This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status -This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_intr_mask_rx - MMC Receive Interrupt mask - 0x10c - 32 - 0x00000000 - 0x03FFFFFE - - - RXCTRLFIM - MMC Receive Control Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXRCVERRFIM - MMC Receive Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXWDOGFIM - MMC Receive Watchdog Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXVLANGBFIM - MMC Receive VLAN Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXFOVFIM - MMC Receive FIFO Overflow Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXPAUSFIM - MMC Receive Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXORANGEFIM - MMC Receive Out Of Range Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXLENERFIM - MMC Receive Length Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXUCGFIM - MMC Receive Unicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RX1024TMAXOCTGBFIM - MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. -Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RX512T1023OCTGBFIM - MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - RX256T511OCTGBFIM - MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - RX128T255OCTGBFIM - MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RX65T127OCTGBFIM - MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RX64OCTGBFIM - MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXOSIZEGFIM - MMC Receive Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUSIZEGFIM - MMC Receive Undersize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXJABERFIM - MMC Receive Jabber Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXRUNTFIM - MMC Receive Runt Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXALGNERFIM - MMC Receive Alignment Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXCRCERFIM - MMC Receive CRC Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXMCGFIM - MMC Receive Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXBCGFIM - MMC Receive Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask. -Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - - - mmc_intr_mask_tx - MMC Transmit Interrupt Mask - 0x110 - 32 - 0x00000000 - 0x03FFFFFF - - - TXOSIZEGFIM - MMC Transmit Oversize Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - TXVLANGFIM - MMC Transmit VLAN Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - TXPAUSFIM - MMC Transmit Pause Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - TXEXDEFFIM - MMC Transmit Excessive Deferral Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - TXGFRMIM - MMC Transmit Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - TXCARERFIM - MMC Transmit Carrier Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - TXEXCOLFIM - MMC Transmit Excessive Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - TXLATCOLFIM - MMC Transmit Late Collision Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - TXDEFFIM - MMC Transmit Deferred Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - TXMCOLGFIM - MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - 15 - 1 - read-write - - - TXSCOLGFIM - MMC Transmit Single Collision Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - 14 - 1 - read-write - - - TXUFLOWERFIM - MMC Transmit Underflow Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - TXBCGBFIM - MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - TXMCGBFIM - MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - TXUCGBFIM - MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - TX1024TMAXOCTGBFIM - MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - TX512T1023OCTGBFIM - MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - TX256T511OCTGBFIM - MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - TX128T255OCTGBFIM - MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - TX65T127OCTGBFIM - MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - TX64OCTGBFIM - MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - TXMCGFIM - MMC Transmit Multicast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - TXBCGFIM - MMC Transmit Broadcast Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - TXGBFRMIM - MMC Transmit Good Bad Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - tx64octets_gb - Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx65to127octets_gb - Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x128 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx128to255octets_gb - Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x12c - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx256to511octets_gb - Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x130 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx512to1023octets_gb - Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. - 0x134 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - tx1024tomaxoctets_gb - Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. - 0x138 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - 0 - 32 - read-write - - - - - rxframecount_gb - Number of good and bad frames received - 0x180 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good and bad frames received. - 0 - 32 - read-write - - - - - mmc_ipc_intr_mask_rx - MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. - 0x200 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - 26 - 1 - read-write - - - RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIM - MMC Receive ICMP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIM - MMC Receive ICMP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIM - MMC Receive TCP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIM - MMC Receive TCP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIM - MMC Receive UDP Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIM - MMC Receive UDP Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIM - MMC Receive IPV6 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIM - MMC Receive IPV6 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIM - MMC Receive IPV6 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIM - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIM - MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIM - MMC Receive IPV4 No Payload Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIM - MMC Receive IPV4 Header Error Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIM - MMC Receive IPV4 Good Frame Counter Interrupt Mask -Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - mmc_ipc_intr_rx - MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. - 0x208 - 32 - 0x00000000 - 0x3FFF3FFF - - - RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status -This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - 29 - 1 - read-write - - - RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status -This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - 28 - 1 - read-write - - - RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status -This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - 27 - 1 - read-write - - - RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status -This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - 26 - 1 - read-write - - - RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status -This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - 25 - 1 - read-write - - - RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status -This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - 24 - 1 - read-write - - - RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - 23 - 1 - read-write - - - RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 22 - 1 - read-write - - - RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status -This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - 21 - 1 - read-write - - - RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status -This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - 20 - 1 - read-write - - - RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status -This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - 19 - 1 - read-write - - - RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status -This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - 18 - 1 - read-write - - - RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - 17 - 1 - read-write - - - RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status -This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - 16 - 1 - read-write - - - RXICMPERFIS - MMC Receive ICMP Error Frame Counter Interrupt Status -This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - 13 - 1 - read-write - - - RXICMPGFIS - MMC Receive ICMP Good Frame Counter Interrupt Status -This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - 12 - 1 - read-write - - - RXTCPERFIS - MMC Receive TCP Error Frame Counter Interrupt Status -This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - 11 - 1 - read-write - - - RXTCPGFIS - MMC Receive TCP Good Frame Counter Interrupt Status -This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - 10 - 1 - read-write - - - RXUDPERFIS - MMC Receive UDP Error Frame Counter Interrupt Status -This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - 9 - 1 - read-write - - - RXUDPGFIS - MMC Receive UDP Good Frame Counter Interrupt Status -This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - 8 - 1 - read-write - - - RXIPV6NOPAYFIS - MMC Receive IPV6 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - 7 - 1 - read-write - - - RXIPV6HERFIS - MMC Receive IPV6 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 6 - 1 - read-write - - - RXIPV6GFIS - MMC Receive IPV6 Good Frame Counter Interrupt Status -This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - 5 - 1 - read-write - - - RXIPV4UDSBLFIS - MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status -This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - 4 - 1 - read-write - - - RXIPV4FRAGFIS - MMC Receive IPV4 Fragmented Frame Counter Interrupt Status -This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - 3 - 1 - read-write - - - RXIPV4NOPAYFIS - MMC Receive IPV4 No Payload Frame Counter Interrupt Status -This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - 2 - 1 - read-write - - - RXIPV4HERFIS - MMC Receive IPV4 Header Error Frame Counter Interrupt Status -This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - 1 - 1 - read-write - - - RXIPV4GFIS - MMC Receive IPV4 Good Frame Counter Interrupt Status -This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - 0 - 1 - read-write - - - - - rxipv4_gd_fms - Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload - 0x210 - 32 - 0x00000000 - 0xFFFFFFFF - - - FRMCNT - Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - 0 - 32 - read-write - - - - - 1 - 0x20 - 0 - L3_L4_CFG[%s] - no description available - 0x400 - - L3_L4_CTRL - Layer 3 and Layer 4 Control Register - 0x0 - 32 - 0x00000000 - 0x003DFFFD - - - L4DPIM0 - Layer 4 Destination Port Inverse Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - 21 - 1 - read-write - - - L4DPM0 - Layer 4 Destination Port Match Enable - When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. -When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - 20 - 1 - read-write - - - L4SPIM0 - Layer 4 Source Port Inverse Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. -When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. -This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - 19 - 1 - read-write - - - L4SPM0 - Layer 4 Source Port Match Enable -When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - 18 - 1 - read-write - - - L4PEN0 - Layer 4 Protocol Enable -When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. -When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. -The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - 16 - 1 - read-write - - - L3HDBM0 - Layer 3 IP DA Higher Bits Match - IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, -which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. -The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - … -- 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 11 - 5 - read-write - - - L3HSBM0 - Layer 3 IP SA Higher Bits Match - IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: -- 0: No bits are masked. -- 1: LSb[0] is masked. -- 2: Two LSbs [1:0] are masked. - ... -- 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. -This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - 6 - 5 - read-write - - - L3DAIM0 - Layer 3 IP DA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. -When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - 5 - 1 - read-write - - - L3DAM0 - Layer 3 IP DA Match Enable -When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. -Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - 4 - 1 - read-write - - - L3SAIM0 - Layer 3 IP SA Inverse Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. -This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - 3 - 1 - read-write - - - L3SAM0 - Layer 3 IP SA Match Enable -When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - 2 - 1 - read-write - - - L3PEN0 - Layer 3 Protocol Enable - When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. -When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. -The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - 0 - 1 - read-write - - - - - L4_Addr - Layer 4 Address Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - L4DP0 - Layer 4 Destination Port Number Field -When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - 16 - 16 - read-write - - - L4SP0 - Layer 4 Source Port Number Field - When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. -When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - 0 - 16 - read-write - - - - - L3_Addr_0 - Layer 3 Address 0 Register - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A00 - Layer 3 Address 0 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_1 - Layer 3 Address 1 Register - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A10 - Layer 3 Address 1 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - 0 - 32 - read-write - - - - - L3_Addr_2 - Layer 3 Address 2 Register - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A20 - Layer 3 Address 2 Field - When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. -When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - L3_Addr_3 - Layer 3 Address 3 Register - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - L3A30 - Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), -this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. -When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - 0 - 32 - read-write - - - - - - VLAN_TAG_INC_RPL - VLAN Tag Inclusion or Replacement Register - 0x584 - 32 - 0x00000000 - 0x000FFFFF - - - CSVL - C-VLAN or S-VLAN - When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - 19 - 1 - read-write - - - VLP - VLAN Priority Control -When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - 18 - 1 - read-write - - - VLC - VLAN Tag Control in Transmit Frames -- 2’b00: No VLAN tag deletion, insertion, or replacement -- 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. -- 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. -This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. -- 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). -Note: Changes to this field take effect only on the start of a frame. -If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - 16 - 2 - read-write - - - VLT - VLAN Tag for Transmit Frames - This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - 0 - 16 - read-write - - - - - VLAN_HASH - VLAN Hash Table Register - 0x588 - 32 - 0x00000000 - 0x0000FFFF - - - VLHT - VLAN Hash Table - This field contains the 16-bit VLAN Hash Table. - 0 - 16 - read-write - - - - - TS_CTRL - Timestamp Control Register - 0x700 - 32 - 0x00000000 - 0x1F07FF3F - - - ATSEN3 - Auxiliary Snapshot 3 Enable -This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - 28 - 1 - read-write - - - ATSEN2 - Auxiliary Snapshot 2 Enable -This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - 27 - 1 - read-write - - - ATSEN1 - Auxiliary Snapshot 1 Enable -This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - 26 - 1 - read-write - - - ATSEN0 - Auxiliary Snapshot 0 Enable -This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - 25 - 1 - read-write - - - ATSFC - Auxiliary Snapshot FIFO Clear -When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. -This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - 24 - 1 - read-write - - - TSENMACADDR - Enable MAC address for PTP Frame Filtering -When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - 18 - 1 - read-write - - - SNAPTYPSEL - Select PTP packets for Taking Snapshots - These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - 16 - 2 - read-write - - - TSMSTRENA - Enable Snapshot for Messages Relevant to Master -When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - 15 - 1 - read-write - - - TSEVNTENA - Enable Timestamp Snapshot for Event Messages -When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - 14 - 1 - read-write - - - TSIPV4ENA - Enable Processing of PTP Frames Sent over IPv4-UDP - When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - 13 - 1 - read-write - - - TSIPV6ENA - Enable Processing of PTP Frames Sent over IPv6-UDP -When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - 12 - 1 - read-write - - - TSIPENA - Enable Processing of PTP over Ethernet Frames -When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - 11 - 1 - read-write - - - TSVER2ENA - Enable PTP packet Processing for Version 2 Format -When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - 10 - 1 - read-write - - - TSCTRLSSR - Timestamp Digital or Binary Rollover Control -When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - When reset, the rollover value of sub-second register is 0x7FFF_FFFF. -The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - 9 - 1 - read-write - - - TSENALL - Enable Timestamp for All Frames -When set, the timestamp snapshot is enabled for all frames received by the MAC. - 8 - 1 - read-write - - - TSADDREG - Addend Reg Update -When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. -This register bit should be zero before setting it. - 5 - 1 - read-write - - - TSTRIG - Timestamp Interrupt Trigger Enable -When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. -This bit is reset after the generation of the Timestamp Trigger Interrupt. - 4 - 1 - read-write - - - TSUPDT - Timestamp Update -When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - 3 - 1 - read-write - - - TSINIT - Timestamp Initialize -When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) -and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. -This bit is reset when the initialization is complete. -The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - 2 - 1 - read-write - - - TSCFUPDT - Timestamp Fine or Coarse Update -When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - 1 - 1 - read-write - - - TSENA - Timestamp Enable -When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. -You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - 0 - 1 - read-write - - - - - SUB_SEC_INCR - Sub-Second Increment Register - 0x704 - 32 - 0x00000000 - 0x000000FF - - - SSINC - Sub-second Increment Value -The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. -For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) -when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. -When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. -In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - 0 - 8 - read-write - - - - - SYST_SEC - System Time - Seconds Register - 0x708 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - 0 - 32 - read-only - - - - - SYST_NSEC - System Time - Nanoseconds Register - 0x70c - 32 - 0x00000000 - 0x7FFFFFFF - - - TSSS - Timestamp Sub Seconds - The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - 0 - 31 - read-only - - - - - SYST_SEC_UPD - System Time - Seconds Update Register - 0x710 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSS - Timestamp Second - The value in this field indicates the time in seconds to be initialized or added to the system time. - 0 - 32 - read-write - - - - - SYST_NSEC_UPD - System Time - Nanoseconds Update Register - 0x714 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDSUB - Add or Subtract Time - When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - 31 - 1 - read-write - - - TSSS - Timestamp Sub Seconds -The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. -When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - 0 - 31 - read-write - - - - - TS_ADDEND - Timestamp Addend Register - 0x718 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSAR - Timestamp Addend Register -This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - 0 - 32 - read-write - - - - - TGTTM_SEC - Target Time Seconds Register - 0x71c - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTR - Target Time Seconds Register - This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - Target Time Nanoseconds Register - 0x720 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY - Target Time Register Busy - The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Target Time Registers when this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - 31 - 1 - read-write - - - TTSLO - Target Timestamp Low Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). -This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - SYSTM_H_SEC - System Time - Higher Word Seconds Register - 0x724 - 32 - 0x00000000 - 0x0000FFFF - - - TSHWR - Timestamp Higher Word Register -This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. -The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - 0 - 16 - read-write - - - - - TS_STATUS - Timestamp Status Register - 0x728 - 32 - 0x00000000 - 0x3F0F03FF - - - ATSNS - Number of Auxiliary Timestamp Snapshots -This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. -These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. -This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 25 - 5 - read-only - - - ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed - This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. -This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - 24 - 1 - read-only - - - ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier -These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. -When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. -These bits are applicable only if the number of Auxiliary snapshots is more than one. -One bit is assigned for each trigger as shown in the following list: -- Bit 16: Auxiliary trigger 0 -- Bit 17: Auxiliary trigger 1 -- Bit 18: Auxiliary trigger 2 -- Bit 19: Auxiliary trigger 3 - The software can read this register to find the triggers that are set when the timestamp is taken. - 16 - 4 - read-only - - - TSTRGTERR3 - Timestamp Target Time Error -This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - 9 - 1 - read-only - - - TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 -When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - 8 - 1 - read-only - - - TSTRGTERR2 - No description available - 7 - 1 - read-only - - - TSTARGT2 - No description available - 6 - 1 - read-only - - - TSTRGTERR1 - No description available - 5 - 1 - read-only - - - TSTARGT1 - No description available - 4 - 1 - read-only - - - TSTRGTERR - No description available - 3 - 1 - read-only - - - AUXTSTRIG - No description available - 2 - 1 - read-only - - - TSTARGT - No description available - 1 - 1 - read-only - - - TSSOVF - No description available - 0 - 1 - read-only - - - - - PPS_CTRL - PPS Control Register - 0x72c - 32 - 0x00000000 - 0x6767677F - - - TRGTMODSEL3 - Target Time Register Mode for PPS3 Output -This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - 29 - 2 - read-write - - - PPSCMD3 - Flexible PPS3 Output Control -This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 24 - 3 - write-only - - - TRGTMODSEL2 - Target Time Register Mode for PPS2 Output -This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - 21 - 2 - read-write - - - PPSCMD2 - Flexible PPS2 Output Control -This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 16 - 3 - write-only - - - TRGTMODSEL1 - Target Time Register Mode for PPS1 Output -This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - 13 - 2 - read-write - - - PPSCMD1 - Flexible PPS1 Output Control -This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - 8 - 3 - write-only - - - TRGTMODSEL0 - Target Time Register Mode for PPS0 Output - This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: -- 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. -- 01: Reserved -- 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. -- 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - 5 - 2 - read-write - - - PPSEN0 - Flexible PPS Output Mode Enable -When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - 4 - 1 - read-write - - - PPSCTRLCMD0 - PPSCTRL0: PPS0 Output Frequency Control -This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. -The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. -For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: -- 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. -- 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. -- 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. -- 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... -- 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. -Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. -In the digital rollover mode, the PPS output frequency is an average number. -The actual clock is of different frequency that gets synchronized every second. For example: -- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms -- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - - One clock of 50 percent duty cycle and 537 ms period - - Second clock of 463 ms period (268 ms low and 195 ms high) -- When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - - Three clocks of 50 percent duty cycle and 268 ms period - - Fourth clock of 195 ms period (134 ms low and 61 ms high) -PPSCMD0: Flexible PPS0 Output Control -0000: No Command -0001: START Single Pulse -This command generates single pulse rising at the start point defined in -Target Time Registers and of a duration defined -in the PPS0 Width Register. -0010: START Pulse Train -This command generates the train of pulses rising at the start point -defined in the Target Time Registers and of a duration defined in the -PPS0 Width Register and repeated at interval defined in the PPS -Interval Register. By default, the PPS pulse train is free-running unless -stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train -immediately’ commands. -0011: Cancel START -This command cancels the START Single Pulse and START Pulse Train -commands if the system time has not crossed the programmed start -time. -0100: STOP Pulse train at time -This command stops the train of pulses initiated by the START Pulse -Train command (PPSCMD = 0010) after the time programmed in the -Target Time registers elapses. -0101: STOP Pulse Train immediately -This command immediately stops the train of pulses initiated by the -START Pulse Train command (PPSCMD = 0010). -0110: Cancel STOP Pulse train -This command cancels the STOP pulse train at time command if the -programmed stop time has not elapsed. The PPS pulse train becomes -free-running on the successful execution of this command. -0111-1111: Reserved -Note: These bits get cleared automatically - 0 - 4 - read-write - - - - - AUX_TS_NSEC - Auxiliary Timestamp - Nanoseconds Register - 0x730 - 32 - 0x00000000 - 0x7FFFFFFF - - - AUXTSLO - Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - 0 - 31 - read-only - - - - - AUX_TS_SEC - Auxiliary Timestamp - Seconds Register - 0x734 - 32 - 0x00000000 - 0xFFFFFFFF - - - AUXTSHI - Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - 0 - 32 - read-only - - - - - PPS0_INTERVAL - PPS Interval Register - 0x760 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 Output Signal Interval -These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if the PTP reference clock is 50 MHz (period of 20ns), -and desired interval between rising edges of PPS0 signal output is 100ns - (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - PPS0_WIDTH - PPS Width Register - 0x764 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS0 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. -For example, if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - 3 - 0x20 - 1,2,3 - PPS[%s] - no description available - 0x780 - - TGTTM_SEC - PPS Target Time Seconds Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSTRH1 - PPS1 Target Time Seconds Register -This register stores the time in seconds. -When the timestamp value matches or exceeds both Target Timestamp registers, -then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), -the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - 0 - 32 - read-write - - - - - TGTTM_NSEC - PPS Target Time Nanoseconds Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TRGTBUSY1 - PPS1 Target Time Register Busy -The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. -Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. -The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain -The application must not update the Targeers wht Time Registen this bit is read as 1. -Otherwise, the synchronization of the previous programmed time gets corrupted. - 31 - 1 - read-write - - - TTSL1 - Target Time Low for PPS1 Register -This register stores the time in (signed) nanoseconds. -When the value of the timestamp matches the both Target Timestamp registers, -then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). -The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - 0 - 31 - read-write - - - - - INTERVAL - PPS Interval Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 Output Signal Interval -These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), -then you should program value 4 (5 – 1) in this register. - 0 - 32 - read-write - - - - - WIDTH - PPS Width Register - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSWIDTH - PPS1 Output Signal Width -These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. -You need to program one value less than the required interval. For example, - if PTP reference clock is 50 MHz (period of 20ns), -and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), -then you should program value 3 (4 – 1) in this register. - 0 - 32 - read-write - - - - - - DMA_BUS_MODE - Bus Mode Register - 0x1000 - 32 - 0x00000000 - 0xBFFFFFFF - - - RIB - Rebuild INCRx Burst -When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. -The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. -By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - 31 - 1 - read-write - - - PRWG - Channel Priority -Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. -- 00: The priority weight is 1. -- 01: The priority weight is 2. -- 10: The priority weight is 3. -- 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - 28 - 2 - read-write - - - TXPR - Transmit Priority -When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - 27 - 1 - read-write - - - MB - Mixed Burst -When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), -whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - 26 - 1 - read-write - - - AAL - Address-Aligned Beats -When this bit is set high and the FB bit is equal to 1, -the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - 25 - 1 - read-write - - - PBLX8 - PBLx8 Mode -When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. -Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - 24 - 1 - read-write - - - USP - Use Separate PBL -When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. -The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. -When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - 23 - 1 - read-write - - - RPBL - Rx DMA PBL -This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. -This field is valid and applicable only when USP is set high. - 17 - 6 - read-write - - - FB - Fixed Burst - This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. -When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. -When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - 16 - 1 - read-write - - - PR - Priority Ratio - These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. -- 00: The Priority Ratio is 1:1. -- 01: The Priority Ratio is 2:1. -- 10: The Priority Ratio is 3:1. -- 11: The Priority Ratio is 4:1. - 14 - 2 - read-write - - - PBL - Programmable Burst Length -These bits indicate the maximum number of beats to be transferred in one DMA transaction. -This is the maximum value that is used in a single block Read or Write. -The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. -PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. -Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. -If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - 8 - 6 - read-write - - - ATDS - Alternate Descriptor Size -When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). -This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. -The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. -This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: -- Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. -When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - 7 - 1 - read-write - - - DSL - Descriptor Skip Length -This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. -The address skipping starts from the end of current descriptor to the start of next descriptor. -When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - 2 - 5 - read-write - - - DA - DMA Arbitration Scheme -This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. -- 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). -- 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - 1 - 1 - read-write - - - SWR - Software Reset - When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. -It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. -Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. -Note: - The Software reset function is driven only by this bit. -Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. -- The reset operation is completed only when all resets in all active clock domains are de-asserted. -Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. -The time to complete the software reset operation depends on the frequency of the slowest active clock. - 0 - 1 - read-write - - - - - DMA_TX_POLL_DEMAND - Transmit Poll Demand Register - 0x1004 - 32 - 0x00000000 - 0xFFFFFFFF - - - TPD - Transmit Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the transmission resumes. - 0 - 32 - read-write - - - - - DMA_RX_POLL_DEMAND - Receive Poll Demand Register - 0x1008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RPD - Receive Poll Demand -When these bits are written with any value, -the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - If that descriptor is not available (owned by the Host), -the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. -If the descriptor is available, the Rx DMA returns to the active state. - 0 - 32 - read-write - - - - - DMA_RX_DESC_LIST_ADDR - Receive Descriptor List Address Register - 0x100c - 32 - 0x00000000 - 0xFFFFFFFF - - - RDESLA - Start of Receive List -This field contains the base address of the first descriptor in the Receive Descriptor list. -The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_TX_DESC_LIST_ADDR - Transmit Descriptor List Address Register - 0x1010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TDESLA - Start of Transmit List -This field contains the base address of the first descriptor in the Transmit Descriptor list. -The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - 0 - 32 - read-write - - - - - DMA_STATUS - Status Register - 0x1014 - 32 - 0x00000000 - 0x7FFFE7FF - - - GLPII - GLPII: GMAC LPI Interrupt (for Channel 0) -This bit indicates an interrupt event in the LPI logic of the MAC. -To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. -Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. -When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. --or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. -To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. -Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. -Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - 30 - 1 - read-write - - - TTI - Timestamp Trigger Interrupt -This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. -This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - 29 - 1 - read-write - - - GPI - GMAC PMT Interrupt -This bit indicates an interrupt event in the PMT module of the DWC_gmac. - The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the Power Management feature is enabled. -Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - 28 - 1 - read-write - - - GMI - GMAC MMC Interrupt - This bit reflects an interrupt event in the MMC module of the DWC_gmac. -The software must read the corresponding registers in the DWC_gmac -to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. -The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. -This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - 27 - 1 - read-write - - - GLI - GMAC Line Interface Interrupt -When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): -- PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event -- SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - read any of the following corresponding registers: -- PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) -- SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) -- General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - 26 - 1 - read-write - - - EB - Error Bits -This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. -- 0 0 0: Error during Rx DMA Write Data Transfer -- 0 1 1: Error during Tx DMA Read Data Transfer -- 1 0 0: Error during Rx DMA Descriptor Write Access -- 1 0 1: Error during Tx DMA Descriptor Write Access -- 1 1 0: Error during Rx DMA Descriptor Read Access -- 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - 23 - 3 - read-write - - - TS - Transmit Process State -This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped; Reset or Stop Transmit Command issued -- 3’b001: Running; Fetching Transmit Transfer Descriptor -- 3’b010: Running; Waiting for status -- 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) -- 3’b100: TIME_STAMP write state -- 3’b101: Reserved for future use -- 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow -- 3’b111: Running; Closing Transmit Descriptor - 20 - 3 - read-write - - - RS - Receive Process State -This field indicates the Receive DMA FSM state. This field does not generate an interrupt. -- 3’b000: Stopped: Reset or Stop Receive Command issued -- 3’b001: Running: Fetching Receive Transfer Descriptor -- 3’b010: Reserved for future use -- 3’b011: Running: Waiting for receive packet -- 3’b100: Suspended: Receive Descriptor Unavailable -- 3’b101: Running: Closing Receive Descriptor -- 3’b110: TIME_STAMP write state -- 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - 17 - 3 - read-write - - - NIS - Normal Interrupt Summary -Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in -Register 7 (Interrupt Enable Register): -- Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt -- Register 5[14]: Early Receive Interrupt Only unmasked bits - (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - 16 - 1 - read-write - - - AIS - Abnormal Interrupt Summary -Abnormal Interrupt Summary bit value is the logical OR of the following -when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive FIFO Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt -- Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. -This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - 15 - 1 - read-write - - - ERI - Early Receive Interrupt -This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - 14 - 1 - read-write - - - FBI - Fatal Bus Error Interrupt -This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - 13 - 1 - read-write - - - ETI - Early Transmit Interrupt -This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - 10 - 1 - read-write - - - RWT - Receive Watchdog Timeout -When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - 9 - 1 - read-write - - - RPS - Receive Process Stopped -This bit is asserted when the Receive Process enters the Stopped state. - 8 - 1 - read-write - - - RU - Receive Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. -The Receive Process is suspended. To resume processing Receive descriptors, - the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. -This bit is set only when the previous Receive Descriptor is owned by the DMA. - 7 - 1 - read-write - - - RI - Receive Interrupt -This bit indicates that the frame reception is complete. -When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, -and the specific frame status information is updated in the descriptor. -The reception remains in the Running state. - 6 - 1 - read-write - - - UNF - Transmit Underflow -This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - 5 - 1 - read-write - - - OVF - Receive Overflow -This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - 4 - 1 - read-write - - - TJT - Transmit Jabber Timeout -This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). -When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - 3 - 1 - read-write - - - TU - Transmit Buffer Unavailable -This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. -To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - 2 - 1 - read-write - - - TPS - Transmit Process Stopped -This bit is set when the transmission is stopped. - 1 - 1 - read-write - - - TI - Transmit Interrupt -This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - 0 - 1 - read-write - - - - - DMA_OP_MODE - Operation Mode Register - 0x1018 - 32 - 0x00000000 - 0x13F1FFFE - - - DT - Disable Dropping of TCP/IP Checksum Error Frames -When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. -When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - 28 - 1 - read-write - - - RSF - Receive Store and Forward -When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - 25 - 1 - read-write - - - DFF - Disable Flushing of Received Frames -When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - 24 - 1 - read-write - - - RFA_2 - MSB of Threshold for Activating Flow Control -If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, -this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. -This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 23 - 1 - read-write - - - RFD_2 - MSB of Threshold for Deactivating Flow Control -If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: -- 100: Full minus 5 KB, that is, FULL — 5 KB -- 101: Full minus 6 KB, that is, FULL — 6 KB -- 110: Full minus 7 KB, that is, FULL — 7 KB -- 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - 22 - 1 - read-write - - - TSF - Transmit Store and Forward -When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. -When this bit is set, the TTC values specified in Bits [16:14] are ignored. -This bit should be changed only when the transmission is stopped. - 21 - 1 - read-write - - - FTF - Flush Transmit FIFO -When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. -This bit is cleared internally when the flushing operation is complete. -The Operation Mode register should not be written to until this bit is cleared. -The data which is already accepted by the MAC transmitter is not flushed. -It is scheduled for transmission and results in underflow and runt frame transmission. - 20 - 1 - read-write - - - TTC - Transmit Threshold Control -These bits control the threshold level of the MTL Transmit FIFO. - Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. -In addition, full frames with a length less than the threshold are also transmitted. - These bits are used only when Bit 21 (TSF) is reset. -- 000: 64 -- 001: 128 -- 010: 192 -- 011: 256 -- 100: 40 -- 101: 32 -- 110: 24 -- 111: 16 - 14 - 3 - read-write - - - ST - Start or Stop Transmission Command -When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. -Descriptor acquisition is attempted either from the current position in the list, -which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), -or from the position retained when transmission was stopped previously. - If the DMA does not own the current descriptor, -transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Transmission command is effective only when transmission is stopped. -If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - then the DMA behavior is unpredictable. When this bit is reset, -the transmission process is placed in the Stopped state after completing the transmission of the current frame. -The Next Descriptor position in the Transmit List is saved, -and it becomes the current position when transmission is restarted. -To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. -The new value is considered when this bit is set again. -The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - 13 - 1 - read-write - - - RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. -- 00: Full minus 1 KB, that is, FULL — 1 KB -- 01: Full minus 2 KB, that is, FULL — 2 KB -- 10: Full minus 3 KB, that is, FULL — 3 KB -- 11: Full minus 4 KB, that is, FULL — 4 KB -The de-assertion is effective only after flow control is asserted. - If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. -These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - 11 - 2 - read-write - - - RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex modes) -These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. -- 00: Full minus 1 KB, that is, FULL—1KB. -- 01: Full minus 2 KB, that is, FULL—2KB. -- 10: Full minus 3 KB, that is, FULL—3KB. -- 11: Full minus 4 KB, that is, FULL—4KB. -These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, -an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. -These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. -Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, -the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - 9 - 2 - read-write - - - EFC - Enable HW Flow Control -When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. -When reset, the flow control operation is disabled. - This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - 8 - 1 - read-write - - - FEF - Forward Error Frames -When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). -However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), -then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, -the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. -When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. -If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, -then the frame is dropped irrespective of the FEF bit setting. -However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. -Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: -- The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - - The advanced timestamp feature is not selected but the extended status is selected. -The extended status is available with the following features: -- L3-L4 filter in GMAC-CORE or GMAC-MTL configurations -- Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - 7 - 1 - read-write - - - FUF - Forward Undersized Good Frames -When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC -When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - 6 - 1 - read-write - - - DGF - Drop Giant Frames -When set, the MAC drops the received giant frames in the Rx FIFO, -that is, frames that are larger than the computed giant frame limit. -When reset, the MAC does not drop the giant frames in the Rx FIFO. -Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: -- Configurations in which IP Checksum Offload (Type 1) is selected in Rx -- Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format -- Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - 5 - 1 - read-write - - - RTC - Receive Threshold Control -These two bits control the threshold level of the MTL Receive FIFO. -Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. -In addition, full frames with length less than the threshold are automatically transferred. -The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. -These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. -- 00: 64 -- 01: 32 -- 10: 96 -- 11: 128 - 3 - 2 - read-write - - - OSF - Operate on Second Frame -When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - 2 - 1 - read-write - - - SR - Start or Stop Receive -When this bit is set, the Receive process is placed in the Running state. -The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. -The descriptor acquisition is attempted from the current position in the list, -which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. -If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. -The Start Receive command is effective only when the reception has stopped. - If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. -When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. -The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. -The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - 1 - 1 - read-write - - - - - DMA_INTR_EN - Interrupt Enable Register - 0x101c - 32 - 0x00000000 - 0x0001E7FF - - - NIE - Normal Interrupt Summary Enable -When this bit is set, normal interrupt summary is enabled. -When this bit is reset, normal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): - - Register 5[0]: Transmit Interrupt -- Register 5[2]: Transmit Buffer Unavailable -- Register 5[6]: Receive Interrupt - - Register 5[14]: Early Receive Interrupt - 16 - 1 - read-write - - - AIE - Abnormal Interrupt Summary Enable -When this bit is set, abnormal interrupt summary is enabled. -When this bit is reset, the abnormal interrupt summary is disabled. -This bit enables the following interrupts in Register 5 (Status Register): -- Register 5[1]: Transmit Process Stopped -- Register 5[3]: Transmit Jabber Timeout -- Register 5[4]: Receive Overflow -- Register 5[5]: Transmit Underflow -- Register 5[7]: Receive Buffer Unavailable -- Register 5[8]: Receive Process Stopped -- Register 5[9]: Receive Watchdog Timeout -- Register 5[10]: Early Transmit Interrupt - - Register 5[13]: Fatal Bus Error - 15 - 1 - read-write - - - ERE - Early Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - 14 - 1 - read-write - - - FBE - Fatal Bus Error Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - 13 - 1 - read-write - - - ETE - Early Transmit Interrupt Enable -When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - 10 - 1 - read-write - - - RWE - Receive Watchdog Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - 9 - 1 - read-write - - - RSE - Receive Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - 8 - 1 - read-write - - - RUE - Receive Buffer Unavailable Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - 7 - 1 - read-write - - - RIE - Receive Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - 6 - 1 - read-write - - - UNE - Underflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - 5 - 1 - read-write - - - OVE - Overflow Interrupt Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - 4 - 1 - read-write - - - TJE - Transmit Jabber Timeout Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - 3 - 1 - read-write - - - TUE - Transmit Buffer Unavailable Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - 2 - 1 - read-write - - - TSE - Transmit Stopped Enable -When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - 1 - 1 - read-write - - - TIE - Transmit Interrupt Enable -When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - 0 - 1 - read-write - - - - - DMA_MISS_OVF_CNT - Missed Frame And Buffer Overflow Counter Register - 0x1020 - 32 - 0x00000000 - 0x1FFFFFFF - - - ONFCNTOVF - Overflow Bit for FIFO Overflow Counter -This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, -that is, the Rx FIFO overflows with the overflow frame counter at maximum value. -In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 28 - 1 - read-write - - - OVFFRMCNT - Overflow Frame Counter -This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - 17 - 11 - read-write - - - MISCNTOVF - Overflow Bit for Missed Frame Counter -This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, -that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - 16 - 1 - read-write - - - MISFRMCNT - Missed Frame Counter -This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. -This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - 0 - 16 - read-write - - - - - DMA_RX_INTR_WDOG - Receive Interrupt Watchdog Timer Register - 0x1024 - 32 - 0x00000000 - 0x000000FF - - - RIWT - RI Watchdog Timer Count -This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. -The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer -of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. -When the watchdog timer runs out, the RI bit is set and the timer is stopped. -The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - 0 - 8 - read-write - - - - - DMA_AXI_MODE - AXI Bus Mode Register - 0x1028 - 32 - 0x00000000 - 0xC0FF30FF - - - EN_LPI - Enable Low Power Interface (LPI) -When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. -When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - 31 - 1 - read-write - - - LPI_XIT_FRM - Unlock on Magic Packet or Remote Wake-Up Frame -When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. -When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - 30 - 1 - read-write - - - WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit -This value limits the maximum outstanding request on the AXI write interface. -Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - 20 - 4 - read-write - - - RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit -This value limits the maximum outstanding request on the AXI read interface. -Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - 16 - 4 - read-write - - - ONEKBBE - 1 KB Boundary Crossing Enable for the GMAC-AXI Master -When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. -When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - 13 - 1 - read-write - - - AXI_AAL - Address-Aligned Beats -This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). -When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - 12 - 1 - read-write - - - BLEN256 - AXI Burst Length 256 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - 7 - 1 - read-write - - - BLEN128 - AXI Burst Length 128 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - 6 - 1 - read-write - - - BLEN64 - AXI Burst Length 64 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - 5 - 1 - read-write - - - BLEN32 - AXI Burst Length 32 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. -This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - 4 - 1 - read-write - - - BLEN16 - AXI Burst Length 16 -When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - 3 - 1 - read-write - - - BLEN8 - AXI Burst Length 8 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 2 - 1 - read-write - - - BLEN4 - AXI Burst Length 4 -When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. -Setting this bit has no effect when UNDEF is set to 1. - 1 - 1 - read-write - - - UNDEF - AXI Undefined Burst Length -This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). -- When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. -- When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. -If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - 0 - 1 - read-write - - - - - DMA_BUS_STATUS - AHB or AXI Status Register - 0x102c - 32 - 0x00000000 - 0x00000003 - - - AXIRDSTS - AXI Master Read Channel Status -When high, it indicates that AXI master's read channel is active and transferring data. - 1 - 1 - read-write - - - AXWHSTS - AXI Master Write Channel or AHB Master Status -When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - it indicates that the AHB master interface FSMs are in the non-idle state. - 0 - 1 - read-write - - - - - DMA_CURR_HOST_TX_DESC - Current Host Transmit Descriptor Register - 0x1048 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTDESAPTR - Host Transmit Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_DESC - Current Host Receive Descriptor Register - 0x104c - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRDESAPTR - Host Receive Descriptor Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_TX_BUF - Current Host Transmit Buffer Address Register - 0x1050 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURTBUFAPTR - Host Transmit Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - DMA_CURR_HOST_RX_BUF - Current Host Receive Buffer Address Register - 0x1054 - 32 - 0x00000000 - 0xFFFFFFFF - - - CURRBUFAPTR - Host Receive Buffer Address Pointer -Cleared on Reset. Pointer updated by the DMA during operation. - 0 - 32 - read-write - - - - - CTRL0 - Control Register 0 - 0x3000 - 32 - 0x00000000 - 0x00003F3F - - - ENET0_RXCLK_DLY_SEL - No description available - 8 - 6 - read-write - - - ENET0_TXCLK_DLY_SEL - No description available - 0 - 6 - read-write - - - - - CTRL2 - Control Register 1 - 0x3008 - 32 - 0x00000000 - 0x2008F400 - - - ENET0_LPI_IRQ_EN - lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt - 29 - 1 - read-write - - - ENET0_REFCLK_OE - set to enable output 50MHz clock to rmii phy. -User should set it if use soc internal clock as refclk - 19 - 1 - read-write - - - ENET0_PHY_INF_SEL - PHY mode select -000MII; 001RGMII; 100RMII; -should be set before config IOMUX, otherwise may cause glitch for RGMII - 13 - 3 - read-write - - - ENET0_FLOWCTRL - flow control request - 12 - 1 - read-write - - - ENET0_RMII_TXCLK_SEL - RMII mode output clock pad select -set to use txck as RMII refclk; -clr to use rxck as RMII refclk; default 0(rxck) -refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. - 10 - 1 - read-write - - - - - - - ENET1 - ENET1 - ENET - 0xf1404000 - - - USB0 - USB0 - USB - 0xf1420000 - - 0x80 - 0x1a8 - registers - - - - GPTIMER0LD - General Purpose Timer #0 Load Register - 0x80 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER0CTRL - General Purpose Timer #0 Controller Register - 0x84 - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in n_GPTIMER0LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software; -In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the -counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - GPTIMER1LD - General Purpose Timer #1 Load Register - 0x88 - 32 - 0x00000000 - 0x00FFFFFF - - - GPTLD - GPTLD -General Purpose Timer Load Value -These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. -This value represents the time in microseconds minus 1 for the timer duration. -Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. -NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - 0 - 24 - read-write - - - - - GPTIMER1CTRL - General Purpose Timer #1 Controller Register - 0x8c - 32 - 0x00000000 - 0xC1FFFFFF - - - GPTRUN - GPTRUN -General Purpose Timer Run -GPTCNT bits are not effected when setting or clearing this bit. -0 - Stop counting -1 - Run - 31 - 1 - read-write - - - GPTRST - GPTRST -General Purpose Timer Reset -0 - No action -1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - 30 - 1 - write-only - - - GPTMODE - GPTMODE -General Purpose Timer Mode -In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is -reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and -automatically reload the counter value from GPTLD bits to start again. -0 - One Shot Mode -1 - Repeat Mode - 24 - 1 - read-write - - - GPTCNT - GPTCNT -General Purpose Timer Counter. -This field is the count value of the countdown timer. - 0 - 24 - read-only - - - - - SBUSCFG - System Bus Config Register - 0x90 - 32 - 0x00000000 - 0x00000007 - - - AHBBRST - AHBBRST -AHB master interface Burst configuration -These bits control AHB master transfer type sequence (or priority). -NOTE: This register overrides n_BURSTSIZE register when its value is not zero. -000 - Incremental burst of unspecified length only -001 - INCR4 burst, then single transfer -010 - INCR8 burst, INCR4 burst, then single transfer -011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer -100 - Reserved, don't use -101 - INCR4 burst, then incremental burst of unspecified length -110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length -111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - 0 - 3 - read-write - - - - - USBCMD - USB Command Register - 0x140 - 32 - 0x00080000 - 0x00FFFB7F - - - ITC - ITC -Interrupt Threshold Control -Read/Write. -The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. -ITC contains the maximum interrupt interval measured in micro-frames. Valid values are -shown below. -Value Maximum Interrupt Interval -00000000 - Immediate (no threshold) -00000001 - 1 micro-frame -00000010 - 2 micro-frames -00000100 - 4 micro-frames -00001000 - 8 micro-frames -00010000 - 16 micro-frames -00100000 - 32 micro-frames -01000000 - 64 micro-frames - 16 - 8 - read-write - - - FS_2 - FS_2 -Frame List Size - (Read/Write or Read Only). [host mode only] -This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. -This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. -NOTE: This field is made up from USBCMD bits 15, 3 and 2. -Value Meaning -0b000 - 1024 elements (4096 bytes) Default value -0b001 - 512 elements (2048 bytes) -0b010 - 256 elements (1024 bytes) -0b011 - 128 elements (512 bytes) -0b100 - 64 elements (256 bytes) -0b101 - 32 elements (128 bytes) -0b110 - 16 elements (64 bytes) -0b111 - 8 elements (32 bytes) - 15 - 1 - read-write - - - ATDTW - ATDTW -Add dTD TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's -linked list. This bit is set and cleared by software. -This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD -to a primed endpoint may go unrecognized. - 14 - 1 - read-write - - - SUTW - SUTW -Setup TripWire - Read/Write. [device mode only] -This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. -If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then -there is a hazard when new setup data arrives while the DCD is copying the setup data payload -from the QH for a previous setup packet. This bit is set and cleared by software. -This bit would also be cleared by hardware when a hazard detected. - 13 - 1 - read-write - - - PRM - Asynchronous Schedule start- Write only， host mode only。 -this bit is used to notify hostcontroller to start async schedule immediately. - 12 - 1 - write-only - - - ASPE - ASPE -Asynchronous Schedule Park Mode Enable - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. -Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. -When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. -NOTE: ASPE bit reset value: '0b' for OTG controller . - 11 - 1 - read-write - - - ASP - ASP -Asynchronous Schedule Park Mode Count - Read/Write. -If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. -It contains a count of the number of successive transactions the host controller is allowed to -execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. -Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. -This field is set to 3h in all controller core. - 8 - 2 - read-write - - - IAA - IAA -Interrupt on Async Advance Doorbell - Read/Write. -This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. -When the host controller has evicted all appropriate cached schedule states, -it sets the Interrupt on Async Advance status bit in the USBSTS register. -If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. -The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. -Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. -This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - 6 - 1 - read-write - - - ASE - ASE -Asynchronous Schedule Enable - Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Asynchronous Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Asynchronous Schedule. -1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - 5 - 1 - read-write - - - PSE - PSE -Periodic Schedule Enable- Read/Write. Default 0b. -This bit controls whether the host controller skips processing the Periodic Schedule. -Only the host controller uses this bit. -Values Meaning -0 - Do not process the Periodic Schedule -1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - 4 - 1 - read-write - - - FS_1 - FS_1 -See description at bit 15 - 2 - 2 - read-write - - - RST - RST -Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. -This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. -Host operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. -Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. -Attempting to reset an actively running host controller will result in undefined behavior. -Device operation mode: -When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. -Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. -In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - 1 - 1 - read-write - - - RS - RS -Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. -Host operation mode: -When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. -When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. -The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. -Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). -Device operation mode: -Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. -This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. -Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - 0 - 1 - read-write - - - - - USBSTS - USB Status Register - 0x144 - 32 - 0x00000000 - 0x030DF1FF - - - TI1 - TI1 -General Purpose Timer Interrupt 1(GPTINT1)--R/WC. -This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this -bit will clear it. - 25 - 1 - read-write - - - TI0 - TI0 -General Purpose Timer Interrupt 0(GPTINT0)--R/WC. -This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this -bit clears it. - 24 - 1 - read-write - - - UPI - USB Host Periodic Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. -This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero. - 19 - 1 - read-write - - - UAI - USB Host Asynchronous Interrupt – RWC. Default = 0b. -This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction -where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. -This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. -A short packet is when the actual number of bytes received was less than expected. -This bit is not used by the device controller and will always be zero - 18 - 1 - read-write - - - NAKI - NAKI -NAK Interrupt Bit--RO. -This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and -corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware -when all Enabled TX/RX Endpoint NAK bits are cleared. - 16 - 1 - read-only - - - AS - AS -Asynchronous Schedule Status - Read Only. -This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. -When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 15 - 1 - read-only - - - PS - PS -Periodic Schedule Status - Read Only. -This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. -The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. -When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). -Only used in the host operation mode. - 14 - 1 - read-only - - - RCL - RCL -Reclamation - Read Only. -This is a read-only status bit used to detect an empty asynchronous schedule. -Only used in the host operation mode. - 13 - 1 - read-only - - - HCH - HCH -HCHaIted - Read Only. -This bit is a zero whenever the Run/Stop bit is a one. - The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - either by software or by the Controller hardware (for example, an internal error). -Only used in the host operation mode. -Default value is '0b' for OTG core . -This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE -register. -NOTE: HCH bit reset value: '0b' for OTG controller core . - 12 - 1 - read-only - - - SLI - SLI -DCSuspend - R/WC. -When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. -Only used in device operation mode. - 8 - 1 - read-write - - - SRI - SRI -SOF Received - R/WC. -When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. -When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. -Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. -Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. -In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. -Software writes a 1 to this bit to clear it. - 7 - 1 - read-write - - - URI - URI -USB Reset Received - R/WC. -When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. -Software can write a 1 to this bit to clear the USB Reset Received status bit. -Only used in device operation mode. - 6 - 1 - read-write - - - AAI - AAI -Interrupt on Async Advance - R/WC. -System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule -by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. -Only used in host operation mode. - 5 - 1 - read-write - - - SEI - System Error – RWC. Default = 0b. -In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. -In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - 4 - 1 - read-write - - - FRI - FRI -Frame List Rollover - R/WC. -The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to -zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the -frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the -Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host -Controller sets this bit to a one every time FHINDEX [12] toggles. -Only used in host operation mode. - 3 - 1 - read-write - - - PCI - PCI -Port Change Detect - R/WC. -The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, -or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. -The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. -When the port controller exits the full or high-speed operation states due to Reset or Suspend events, -the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - 2 - 1 - read-write - - - UEI - UEI -USB Error Interrupt (USBERRINT) - R/WC. -When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. -This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - 1 - 1 - read-write - - - UI - UI -USB Interrupt (USBINT) - R/WC. -This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB -transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. -This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when -the actual number of bytes received was less than the expected number of bytes. - 0 - 1 - read-write - - - - - USBINTR - Interrupt Enable Register - 0x148 - 32 - 0x00000000 - 0x030D01FF - - - TIE1 - TIE1 -General Purpose Timer #1 Interrupt Enable -When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - 25 - 1 - read-write - - - TIE0 - TIE0 -General Purpose Timer #0 Interrupt Enable -When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - 24 - 1 - read-write - - - UPIE - UPIE -USB Host Periodic Interrupt Enable -When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 19 - 1 - read-write - - - UAIE - UAIE -USB Host Asynchronous Interrupt Enable -When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an -interrupt at the next interrupt threshold. - 18 - 1 - read-write - - - NAKE - NAKE -NAK Interrupt Enable -When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - 16 - 1 - read-only - - - SLE - SLE -Sleep Interrupt Enable -When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 8 - 1 - read-write - - - SRE - SRE -SOF Received Interrupt Enable -When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - 7 - 1 - read-write - - - URE - URE -USB Reset Interrupt Enable -When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in device operation mode. - 6 - 1 - read-write - - - AAE - AAE -Async Advance Interrupt Enable -When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 5 - 1 - read-write - - - SEE - SEE -System Error Interrupt Enable -When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 4 - 1 - read-write - - - FRE - FRE -Frame List Rollover Interrupt Enable -When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. -Only used in host operation mode. - 3 - 1 - read-write - - - PCE - PCE -Port Change Detect Interrupt Enable -When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - 2 - 1 - read-write - - - UEE - UEE -USB Error Interrupt Enable -When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - 1 - 1 - read-write - - - UE - UE -USB Interrupt Enable -When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - 0 - 1 - read-write - - - - - FRINDEX - USB Frame Index Register - 0x14c - 32 - 0x00000000 - 0x00003FFF - - - FRINDEX - FRINDEX -Frame Index. -The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. -This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. -The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. -USBCMD [Frame List Size] Number Elements N -In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. -In either mode bits 2:0 indicate the current microframe. -The bit field values description below is represented as (Frame List Size) Number Elements N. -00000000000000 - (1024) 12 -00000000000001 - (512) 11 -00000000000010 - (256) 10 -00000000000011 - (128) 9 -00000000000100 - (64) 8 -00000000000101 - (32) 7 -00000000000110 - (16) 6 -00000000000111 - (8) 5 - 0 - 14 - read-write - - - - - DEVICEADDR - Device Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFF000000 - - - USBADR - USBADR -Device Address. -These bits correspond to the USB device address - 25 - 7 - read-write - - - USBADRA - USBADRA -Device Address Advance. Default=0. -When this bit is '0', any writes to USBADR are instantaneous. - When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. -After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. -Hardware will automatically clear this bit on the following conditions: -1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). -2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). -3) Device Reset occurs (USBADR is reset to 0). -NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. -This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. -If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), -the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - 24 - 1 - read-write - - - - - PERIODICLISTBASE - Frame List Base Address Register - UNION_154 - 0x154 - 32 - 0x00000000 - 0xFFFFF000 - - - BASEADR - BASEADR -Base Address (Low). -These bits correspond to memory address signals [31:12], respectively. -Only used by the host controller. - 12 - 20 - read-write - - - - - ASYNCLISTADDR - Next Asynch. Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFFFE0 - - - ASYBASE - ASYBASE -Link Pointer Low (LPL). -These bits correspond to memory address signals [31:5], respectively. This field may only reference a -Queue Head (QH). -Only used by the host controller. - 5 - 27 - read-write - - - - - ENDPTLISTADDR - Endpoint List Address Register - UNION_158 - 0x158 - 32 - 0x00000000 - 0xFFFFF800 - - - EPBASE - EPBASE -Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. -This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - 11 - 21 - read-write - - - - - BURSTSIZE - Programmable Burst Size Register - 0x160 - 32 - 0x00000000 - 0x0000FFFF - - - TXPBURST - TXPBURST -Programmable TX Burst Size. -Default value is determined by TXBURST bits in n_HWTXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from system -memory to the USB bus. - 8 - 8 - read-write - - - RXPBURST - RXPBURST -Programmable RX Burst Size. -Default value is determined by TXBURST bits in n_HWRXBUF. -This register represents the maximum length of a the burst in 32-bit words while moving data from the -USB bus to system memory. - 0 - 8 - read-write - - - - - TXFILLTUNING - TX FIFO Fill Tuning Register - 0x164 - 32 - 0x00000000 - 0x003F1F7F - - - TXFIFOTHRES - TXFIFOTHRES -FIFO Burst Threshold. (Read/Write) -This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. -The minimum value is 2 and this value should be a low as possible to maximize USB performance. -A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth -where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. -This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - 16 - 6 - read-write - - - TXSCHHEALTH - TXSCHHEALTH -Scheduler Health Counter. (Read/Write To Clear) -Table continues on the next page -This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES -before running out of time to send the packet before the next Start-Of-Frame. -This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. -Writing to this register will clear the counter and this counter will max. at 31. - 8 - 5 - read-write - - - TXSCHOH - TXSCHOH -Scheduler Overhead. (Read/Write) [Default = 0] -This register adds an additional fixed offset to the schedule time estimator described above as Tff. -As an approximation, the value chosen for this register should limit the number of back-off events captured -in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. -Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. -The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. -The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. -Default value is '08h' for OTG controller core . - 0 - 7 - read-write - - - - - ENDPTNAK - Endpoint NAK Register - 0x178 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTN - EPTN -TX Endpoint NAK - R/WC. -Each TX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received IN token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRN - EPRN -RX Endpoint NAK - R/WC. -Each RX endpoint has 1 bit in this field. The bit is set when the -device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - ENDPTNAKEN - Endpoint NAK Enable Register - 0x17c - 32 - 0x00000000 - 0xFFFFFFFF - - - EPTNE - EPTNE -TX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the -corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 16 - 16 - read-write - - - EPRNE - EPRNE -RX Endpoint NAK Enable - R/W. -Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the -corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. -Bit [N] - Endpoint #[N], N is 0-7 - 0 - 16 - read-write - - - - - PORTSC1 - Port Status & Control - 0x184 - 32 - 0x00000000 - 0x3DFF1FFF - - - STS - STS -Serial Transceiver Select -1 Serial Interface Engine is selected -0 Parallel Interface signals is selected -Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. -When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - 29 - 1 - read-write - - - PTW - PTW -Parallel Transceiver Width -This bit has no effect if serial interface engine is used. -0 - Select the 8-bit UTMI interface [60MHz] -1 - Select the 16-bit UTMI interface [30MHz] - 28 - 1 - read-write - - - PSPD - PSPD -Port Speed - Read Only. -This register field indicates the speed at which the port is operating. -00 - Full Speed -01 - Low Speed -10 - High Speed -11 - Undefined - 26 - 2 - read-only - - - PFSC - PFSC -Port Force Full Speed Connect - Read/Write. Default = 0b. -When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp -sequence that allows the port to identify itself as High Speed. -0 - Normal operation -1 - Forced to full speed - 24 - 1 - read-write - - - PHCD - PHCD -PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. -When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY -clock. -NOTE: The PHY clock cannot be disabled if it is being used as the system clock. -In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD -Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend -will be cleared automatically when the host initials resume. Before forcing a resume from the device, the -device controller driver must clear this bit. -In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put -into suspend mode or when no downstream device is connected. Low power suspend is completely -under the control of software. -0 - Enable PHY clock -1 - Disable PHY clock - 23 - 1 - read-write - - - WKOC - WKOC -Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. -Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. -This field is zero if Port Power(PORTSC1) is zero. - 22 - 1 - read-write - - - WKDC - WKDC -Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables -the port to be sensitive to device disconnects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 21 - 1 - read-write - - - WKCN - WKCN -Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. -Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. -This field is zero if Port Power(PORTSC1) is zero or in device mode. - 20 - 1 - read-write - - - PTC - PTC -Port Test Control - Read/Write. Default = 0000b. -Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. -The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. -Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. -Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. -NOTE: Low speed operations are not supported as a peripheral device. -Any other value than zero indicates that the port is operating in test mode. -Value Specific Test -0000 - TEST_MODE_DISABLE -0001 - J_STATE -0010 - K_STATE -0011 - SE0 (host) / NAK (device) -0100 - Packet -0101 - FORCE_ENABLE_HS -0110 - FORCE_ENABLE_FS -0111 - FORCE_ENABLE_LS -1000-1111 - Reserved - 16 - 4 - read-write - - - PP - PP -Port Power (PP)-Read/Write or Read Only. -The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: -PPC -PP Operation -0 -1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. -1 -1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). -When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. -When an over-current condition is detected on a powered port and PPC is a one, -the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). -This feature is implemented in all controller cores (PPC = 1). - 12 - 1 - read-write - - - LS - LS -Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal -lines. -In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because -the port controller state machine and the port routing manage the connection of LS and FS. -In device mode, the use of linestate by the device controller driver is not necessary. -The encoding of the bits are: -Bits [11:10] Meaning -00 - SE0 -01 - K-state -10 - J-state -11 - Undefined - 10 - 2 - read-only - - - HSP - HSP -High-Speed Port - Read Only. Default = 0b. -When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the -host/device connected to the port is not in a high-speed mode. -NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - 9 - 1 - read-only - - - PR - PR -Port Reset - Read/Write or Read Only. Default = 0b. -In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. -When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. -This bit will automatically change to zero after the reset sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. -In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - 8 - 1 - read-write - - - SUSP - SUSP -Suspend - Read/Write or Read Only. Default = 0b. -1=Port in suspend state. 0=Port not in suspend state. -In Host Mode: Read/Write. -Port Enabled Bit and Suspend bit of this register define the port states as follows: -Bits [Port Enabled, Suspend] Port State -0x Disable -10 Enable -11 Suspend -When in suspend state, downstream propagation of data is blocked on this port, except for port reset. -The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. -In the suspend state, the port is sensitive to resume detection. -Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. -The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. -If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: Read Only. -In device mode this bit is a read only status bit. - 7 - 1 - read-write - - - FPR - FPR -Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. -In Host Mode: -Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. -This bit will automatically change to zero after the resume sequence is complete. -This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. -Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. -The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. -Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. -This field is zero if Port Power(PORTSC1) is zero in host mode. -This bit is not-EHCI compatible. -In Device mode: -After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. -The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. -The bit will be cleared when the device returns to normal operation. - Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - 6 - 1 - read-write - - - OCC - OCC -Over-current Change-R/WC. Default=0. -This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - 5 - 1 - read-write - - - OCA - OCA -Over-current Active-Read Only. Default 0. -This bit will automatically transition from one to zero when the over current condition is removed. -0 - This port does not have an over-current condition. -1 - This port currently has an over-current condition - 4 - 1 - read-only - - - PEC - PEC -Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. -In Host Mode: -For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or -due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). -Software clears this by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero. -In Device mode: -The device port is always enabled, so this bit is always '0b'. - 3 - 1 - read-write - - - PE - PE -Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. -In Host Mode: -Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. -Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. -Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. -When the port is disabled, (0b) downstream propagation of data is blocked except for reset. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -The device port is always enabled, so this bit is always '1b'. - 2 - 1 - read-write - - - CSC - CSC -Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. -In Host Mode: -Indicates a change has occurred in the port's Current Connect Status. -The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. -For example, the insertion status changes twice before system software has cleared the changed condition, -hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -This bit is undefined in device controller mode. - 1 - 1 - read-write - - - CCS - CCS -Current Connect Status-Read Only. -In Host Mode: -1=Device is present on port. 0=No device is present. Default = 0. -This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. -This field is zero if Port Power(PORTSC1) is zero in host mode. -In Device Mode: -1=Attached. 0=Not Attached. Default=0. -A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. -A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. -It does not state the device being disconnected or Suspended. - 0 - 1 - read-write - - - - - OTGSC - On-The-Go Status & control Register - 0x1a4 - 32 - 0x00000000 - 0x07070723 - - - ASVIE - ASVIE -A Session Valid Interrupt Enable - Read/Write. - 26 - 1 - read-write - - - AVVIE - AVVIE -A VBus Valid Interrupt Enable - Read/Write. -Setting this bit enables the A VBus valid interrupt. - 25 - 1 - read-write - - - IDIE - IDIE -USB ID Interrupt Enable - Read/Write. -Setting this bit enables the USB ID interrupt. - 24 - 1 - read-write - - - ASVIS - ASVIS -A Session Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the A session valid threshold. -Software must write a one to clear this bit. - 18 - 1 - read-write - - - AVVIS - AVVIS -A VBus Valid Interrupt Status - Read/Write to Clear. -This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. -Software must write a one to clear this bit. - 17 - 1 - read-write - - - IDIS - IDIS -USB ID Interrupt Status - Read/Write. -This bit is set when a change on the ID input has been detected. -Software must write a one to clear this bit. - 16 - 1 - read-write - - - ASV - ASV -A Session Valid - Read Only. -Indicates VBus is above the A session valid threshold. - 10 - 1 - read-only - - - AVV - AVV -A VBus Valid - Read Only. -Indicates VBus is above the A VBus valid threshold. - 9 - 1 - read-only - - - ID - ID -USB ID - Read Only. -0 = A device, 1 = B device - 8 - 1 - read-only - - - IDPU - IDPU -ID Pullup - Read/Write -This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input -will not be sampled. - 5 - 1 - read-write - - - VC - VC -VBUS Charge - Read/Write. -Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - 1 - 1 - read-write - - - VD - VD -VBUS_Discharge - Read/Write. -Setting this bit causes VBus to discharge through a resistor. - 0 - 1 - read-write - - - - - USBMODE - USB Device Mode Register - 0x1a8 - 32 - 0x00000000 - 0x0000001F - - - SDIS - SDIS -Stream Disable Mode. (0 - Inactive [default]; 1 - Active) -Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. -This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. -Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. -Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems -where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. -NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for -the scheduler when using this feature. -NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - 4 - 1 - read-write - - - SLOM - SLOM -Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . -0 - Setup Lockouts On (default); -1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - 3 - 1 - read-write - - - ES - ES -Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the -host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected -by the value of this bit because they are based upon the 32-bit word. -Bit Meaning -0 - Little Endian [Default] -1 - Big Endian - 2 - 1 - read-write - - - CM - CM -Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only -implementations. For those designs that contain both host & device capability, the controller defaults to -an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ -device controllers, this register can only be written once after reset. If it is necessary to switch modes, -software must reset the controller by writing to the RESET bit in the USBCMD register before -reprogramming this register. -For OTG controller core, reset value is '00b'. -00 - Idle [Default for combination host/device] -01 - Reserved -10 - Device Controller [Default for device only controller] -11 - Host Controller [Default for host only controller] - 0 - 2 - read-write - - - - - ENDPTSETUPSTAT - Endpoint Setup Status Register - 0x1ac - 32 - 0x00000000 - 0x0000FFFF - - - ENDPTSETUPSTAT - ENDPTSETUPSTAT -Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. -Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. -The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. -This register is only used in device mode. - 0 - 16 - read-write - - - - - ENDPTPRIME - Endpoint Prime Register - 0x1b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - PETB - PETB -Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a -buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. -Software should write a one to the corresponding bit when posting a new transfer descriptor to an -endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor -from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated -endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - PERB - PERB -Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. -Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. -Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. -Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. -NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD -is retired, and the dQH is updated. -PERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTFLUSH - Endpoint Flush Register - 0x1b4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FETB - FETB -Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. -If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FETB[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - FERB - FERB -Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. -Hardware clears this register after the endpoint flush operation is successful. -FERB[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - ENDPTSTAT - Endpoint Status Register - 0x1b8 - 32 - 0x00000000 - 0xFFFFFFFF - - - ETBR - ETBR -Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. -This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. -There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. -This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. -Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. -ETBR[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-only - - - ERBR - ERBR -Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective -endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a -corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the -ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB -traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the -USB DMA system, or through the ENDPTFLUSH register. -NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations -when a dTD is retired, and the dQH is updated. -ERBR[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-only - - - - - ENDPTCOMPLETE - Endpoint Complete Register - 0x1bc - 32 - 0x00000000 - 0xFFFFFFFF - - - ETCE - ETCE -Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. -If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. -ETCE[N] - Endpoint #N, N is in 0..7 - 16 - 16 - read-write - - - ERCE - ERCE -Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred -and software should read the corresponding endpoint queue to determine the transfer status. If the -corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the -USBINT . Writing one clears the corresponding bit in this register. -ERCE[N] - Endpoint #N, N is in 0..7 - 0 - 16 - read-write - - - - - 16 - 0x4 - ENDPTCTRL0,ENDPTCTRL1,ENDPTCTRL2,ENDPTCTRL3,ENDPTCTRL4,ENDPTCTRL5,ENDPTCTRL6,ENDPTCTRL7,ENDPTCTRL8,ENDPTCTRL9,ENDPTCTRL10,ENDPTCTRL11,ENDPTCTRL12,ENDPTCTRL13,ENDPTCTRL14,ENDPTCTRL15 - ENDPTCTRL[%s] - no description available - 0x1c0 - 32 - 0x00000000 - 0x00CD00CD - - - TXE - TXE -TX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 23 - 1 - read-write - - - TXR - TXR -TX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the Host and device. - 22 - 1 - write-only - - - TXT - TXT -TX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 18 - 2 - read-write - - - TXS - TXS -TX Endpoint Stall - Read/Write -0 End Point OK -1 End Point Stalled -This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured -as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. -This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. -In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: -continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - 16 - 1 - read-write - - - RXE - RXE -RX Endpoint Enable -0 Disabled [Default] -1 Enabled -An Endpoint should be enabled only after it has been configured. - 7 - 1 - read-write - - - RXR - RXR -RX Data Toggle Reset (WS) -Write 1 - Reset PID Sequence -Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order -to synchronize the data PID's between the host and device. - 6 - 1 - write-only - - - RXT - RXT -RX Endpoint Type - Read/Write -00 Control -01 Isochronous -10 Bulk -11 Interrupt - 2 - 2 - read-write - - - RXS - RXS -RX Endpoint Stall - Read/Write -0 End Point OK. [Default] -1 End Point Stalled -This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control -Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit -is cleared. -Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This -control will continue to STALL until this bit is either cleared by software or automatically cleared as above -for control endpoints. -NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the -ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it -is unlikely the DCD software will observe this delay. However, should the DCD observe that the -stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit -until it is set or until a new setup has been received by checking the associated endptsetupstat -Bit. - 0 - 1 - read-write - - - - - OTG_CTRL0 - No description available - 0x200 - 32 - 0x00000000 - 0x020B3F90 - - - OTG_WKDPDMCHG_EN - No description available - 25 - 1 - read-write - - - AUTORESUME_EN - No description available - 19 - 1 - read-write - - - OTG_VBUS_WAKEUP_EN - No description available - 17 - 1 - read-write - - - OTG_ID_WAKEUP_EN - No description available - 16 - 1 - read-write - - - OTG_VBUS_SOURCE_SEL - No description available - 13 - 1 - read-write - - - OTG_UTMI_SUSPENDM_SW - default 0 for naneng usbphy - 12 - 1 - read-write - - - OTG_UTMI_RESET_SW - default 1 for naneng usbphy - 11 - 1 - read-write - - - OTG_WAKEUP_INT_ENABLE - No description available - 10 - 1 - read-write - - - OTG_POWER_MASK - No description available - 9 - 1 - read-write - - - OTG_OVER_CUR_POL - No description available - 8 - 1 - read-write - - - OTG_OVER_CUR_DIS - No description available - 7 - 1 - read-write - - - SER_MODE_SUSPEND_EN - for naneng usbphy, only switch to serial mode when suspend - 4 - 1 - read-write - - - - - PHY_CTRL0 - No description available - 0x210 - 32 - 0x00000000 - 0x02007007 - - - GPIO_ID_SEL_N - No description available - 25 - 1 - read-write - - - ID_DIG_OVERRIDE - No description available - 14 - 1 - read-write - - - SESS_VALID_OVERRIDE - No description available - 13 - 1 - read-write - - - VBUS_VALID_OVERRIDE - No description available - 12 - 1 - read-write - - - ID_DIG_OVERRIDE_EN - No description available - 2 - 1 - read-write - - - SESS_VALID_OVERRIDE_EN - No description available - 1 - 1 - read-write - - - VBUS_VALID_OVERRIDE_EN - No description available - 0 - 1 - read-write - - - - - PHY_CTRL1 - No description available - 0x214 - 32 - 0x00000000 - 0x00100002 - - - UTMI_CFG_RST_N - No description available - 20 - 1 - read-write - - - UTMI_OTG_SUSPENDM - OTG suspend, not utmi_suspendm - 1 - 1 - read-write - - - - - TOP_STATUS - No description available - 0x220 - 32 - 0x00000000 - 0x80000000 - - - WAKEUP_INT_STATUS - No description available - 31 - 1 - read-write - - - - - PHY_STATUS - No description available - 0x224 - 32 - 0x00000000 - 0x800000F5 - - - UTMI_CLK_VALID - No description available - 31 - 1 - read-write - - - LINE_STATE - No description available - 6 - 2 - read-write - - - HOST_DISCONNECT - No description available - 5 - 1 - read-write - - - ID_DIG - No description available - 4 - 1 - read-write - - - UTMI_SESS_VALID - No description available - 2 - 1 - read-write - - - VBUS_VALID - No description available - 0 - 1 - read-write - - - - - - - TSW - TSW - TSW - 0xf1600000 - - 0x4 - 0x7fffc - registers - - - - LU_MAIN_CTRL - LU_MAIN control - 0x4 - 32 - 0x00000000 - 0x00000001 - - - BYP_EN - MAC lookup bypass - 0 - 1 - read-write - - - - - LU_MAIN_HITMEM - LU_MAIN hit - 0x8 - 32 - 0x00000000 - 0x00000003 - - - CAMMEMCLR - clear the cam memory - 1 - 1 - read-write - - - HITMEMCLR - clears the hit memory - 0 - 1 - read-write - - - - - LU_MAIN_PARAM - LU_MAIN parameter - 0xc - 32 - 0x00000000 - 0x0000FFFF - - - NSTR - number of supported streams - 8 - 8 - read-only - - - ADDRW_ENTRY - bit width of entry address vector - 0 - 8 - read-only - - - - - LU_MAIN_BYPASS - LU_MAIN bypass - 0x10 - 32 - 0x00000000 - 0x01FFFFFF - - - HIT - set hit bit to frame, only for debugging - 24 - 1 - read-write - - - UTAG - set internal user tag field - 21 - 3 - read-write - - - HIT_VLAN - mark frame to be vlan-tagged - 20 - 1 - read-write - - - DROP - mark frame to be dropped - 19 - 1 - read-write - - - QUEUE - number of configured buffer depth - 16 - 3 - read-write - - - DEST - target destination ports of frame - 0 - 16 - read-write - - - - - LU_MAIN_PCP_REMAP - LU_MAIN PCP remap - 0x14 - 32 - 0x00000000 - 0x00FFFFFF - - - PCP7 - queue value for PCP=7 - 21 - 3 - read-write - - - PCP6 - queue value for PCP=6 - 18 - 3 - read-write - - - PCP5 - queue value for PCP=5 - 15 - 3 - read-write - - - PCP4 - queue value for PCP=4 - 12 - 3 - read-write - - - PCP3 - queue value for PCP=3 - 9 - 3 - read-write - - - PCP2 - queue value for PCP=2 - 6 - 3 - read-write - - - PCP1 - queue value for PCP=1 - 3 - 3 - read-write - - - PCP0 - queue value for PCP=0 - 0 - 3 - read-write - - - - - LU_MAIN_VERSION - LU_MAIN version - 0x18 - 32 - 0x00000000 - 0xFFFF00FF - - - VER_HI - major version - 24 - 8 - read-only - - - VER_LO - minor version - 16 - 8 - read-only - - - VER_REV - revision number - 0 - 8 - read-only - - - - - LU_MAIN_INTF_ACTION - LU_MAIN low word of action data for internal frames - 0x20 - 32 - 0x00000000 - 0x01FFFFFF - - - UTAG - TSN user sideband information from ALMEM - 22 - 3 - read-write - - - QSEL - Define the traffic queue selection: -00 – use PCP field of VLAN, untagged frames use PCP of PVID -01 – use PCP field with global remapping list -10 – reserved -11 – use value QUEUE of Action List - 20 - 2 - read-write - - - DROP - 1 if frame should be dropped. - 19 - 1 - read-write - - - QUEUE - Select the Priority Queue for TSN TX, only used if QSEL=11 - 16 - 3 - read-write - - - DEST - Select the destination ports of forwarded frame. It is coded in onehot/select way, -where 0 is always route to null. Every bit is mapped to a port. -00000 – to null (frame to clear) -00001 – to port 0 (CPU Port) -00010 – to port 1 -00100 – to port 2 -01000 – to port 3 - 0 - 16 - read-write - - - - - LU_MAIN_BC_ACTION - LU_MAIN low word of action data for broadcast frames - 0x28 - 32 - 0x00000000 - 0x01FFFFFF - - - UTAG - TSN user sideband information from ALMEM - 22 - 3 - read-write - - - QSEL - Define the traffic queue selection: -00 – use PCP field of VLAN, untagged frames use PCP of PVID -01 – use PCP field with global remapping list -10 – reserved -11 – use value QUEUE of Action List - 20 - 2 - read-write - - - DROP - 1 if frame should be dropped. - 19 - 1 - read-write - - - QUEUE - Select the Priority Queue for TSN TX, only used if QSEL=11 - 16 - 3 - read-write - - - DEST - Select the destination ports of forwarded frame. It is coded in onehot/select way, -where 0 is always route to null. Every bit is mapped to a port. -00000 – to null (frame to clear) -00001 – to port 0 (CPU Port) -00010 – to port 1 -00100 – to port 2 -01000 – to port 3 - 0 - 16 - read-write - - - - - LU_MAIN_NN_ACTION - LU_MAIN low word of action data for unknown frames - 0x30 - 32 - 0x00000000 - 0x01FFFFFF - - - UTAG - TSN user sideband information from ALMEM - 22 - 3 - read-write - - - QSEL - Define the traffic queue selection: -00 – use PCP field of VLAN, untagged frames use PCP of PVID -01 – use PCP field with global remapping list -10 – reserved -11 – use value QUEUE of Action List - 20 - 2 - read-write - - - DROP - 1 if frame should be dropped. - 19 - 1 - read-write - - - QUEUE - Select the Priority Queue for TSN TX, only used if QSEL=11 - 16 - 3 - read-write - - - DEST - Select the destination ports of forwarded frame. It is coded in onehot/select way, -where 0 is always route to null. Every bit is mapped to a port. -00000 – to null (frame to clear) -00001 – to port 0 (CPU Port) -00010 – to port 1 -00100 – to port 2 -01000 – to port 3 - 0 - 16 - read-write - - - - - APB2AXIS_CAM_STS - status register - 0x100 - 32 - 0x00000000 - 0x00000003 - - - BUSY - the controller is writing data and/or data is pending - 1 - 1 - read-only - - - RDY - the new data is written to data register - 0 - 1 - read-only - - - - - APB2AXIS_CAM_REQ_CNT - request count - 0x110 - 32 - 0x00000000 - 0x000000FF - - - WRCNT - number of streams in queue - 0 - 8 - read-only - - - - - APB2AXIS_CAM_FILLSTS - fill status - 0x114 - 32 - 0x00000000 - 0x00000011 - - - FULL - frame was dropped because the internal descriptor FIFO is full - 4 - 1 - read-only - - - EMPTY - FD FIFO failure, internal controller lost synchronization - 0 - 1 - read-only - - - - - APB2AXIS_CAM_RESET - reset - 0x118 - 32 - 0x00000000 - 0x00000001 - - - RESET - resets controller and clears all pending stream data - 0 - 1 - write-only - - - - - APB2AXIS_CAM_PARAM - parameter - 0x11c - 32 - 0x00000000 - 0x0000FFFF - - - DEPTH - number of configured buffer depth - 8 - 8 - read-only - - - WORDLEN_BYTE - number of configured 32bit words for this controller - 0 - 8 - read-only - - - - - APB2AXI_CAM_REQDATA_0 - data0 - 0x120 - 32 - 0x00000000 - 0xFFFF0301 - - - ENTRY_NUM - entry number - 16 - 16 - read-write - - - TYPE - select between set, clear or clear all - 8 - 2 - read-write - - - CH - CAM APB2AXIS channel selection - 0 - 1 - read-write - - - - - APB2AXI_CAM_REQDATA_1 - data1 - 0x124 - 32 - 0x00000000 - 0xFFFFFFFF - - - DESTMAC_LO_PORT_VEC - dest-mac[31:0] when CH=0；PORT_VEC when CH=1 - 0 - 32 - read-write - - - - - APB2AXI_CAM_REQDATA_2 - data2 - 0x128 - 32 - 0x00000000 - 0x0FFFFFFF - - - VID - VLAN-ID value (12 bit) for the VLAN_ID table. Use the fefault VLAN-ID(VID=1), if setup an entry for non-VLAN traffic. - 16 - 12 - read-write - - - DESTMAC_HI - dest-mac[47:32] when CH=0 - 0 - 16 - read-write - - - - - APB2AXIS_ALMEM_STS - status register - 0x200 - 32 - 0x00000000 - 0x00000003 - - - BUSY - the controller is writing data and/or data is pending - 1 - 1 - read-only - - - RDY - the new data is written to data register - 0 - 1 - read-only - - - - - APB2AXIS_ALMEM_REQ_CNT - request count - 0x210 - 32 - 0x00000000 - 0x000000FF - - - WRCNT - number of streams in queue - 0 - 8 - read-only - - - - - APB2AXIS_ALMEM_FILLSTS - fill status - 0x214 - 32 - 0x00000000 - 0x00000011 - - - FULL - frame was dropped because the internal descriptor FIFO is full - 4 - 1 - read-only - - - EMPTY - FD FIFO failure, internal controller lost synchronization - 0 - 1 - read-only - - - - - APB2AXIS_ALMEM_RESET - reset - 0x218 - 32 - 0x00000000 - 0x00000001 - - - RESET - resets controller and clears all pending stream data - 0 - 1 - write-only - - - - - APB2AXIS_ALMEM_PARAM - parameter - 0x21c - 32 - 0x00000000 - 0x0000FFFF - - - DEPTH - number of configured buffer depth - 8 - 8 - read-only - - - WORDLEN_BYTE - number of configured 32bit words for this controller - 0 - 8 - read-only - - - - - APB2AXIS_ALMEM_REQDATA_0 - data0 - 0x220 - 32 - 0x00000000 - 0x01FFFFFF - - - UTAG - user sideband information - 22 - 3 - read-write - - - QSEL - define the traffic queue selection - 20 - 2 - read-write - - - DROP - frame should dropped - 19 - 1 - read-write - - - QUEUE - select the priority queue if qsel=11 - 16 - 3 - read-write - - - DEST - destination ports - 0 - 16 - read-write - - - - - APB2AXIS_ALMEM_REQDATA_1 - data1 - 0x224 - 32 - 0x00000000 - 0xC000FFFF - - - WR_NRD - 1 for write and 0 for read - 31 - 1 - read-write - - - RESP - write response enable - 30 - 1 - read-write - - - ENTRY_NUM - define the entry number for reading and writing - 0 - 16 - read-write - - - - - AXIS2APB_ALMEM_STS - status register - 0x280 - 32 - 0x00000000 - 0x00000003 - - - BUSY - the controller is writing data and/or data is pending - 1 - 1 - read-only - - - RDY - the new data is written to data register - 0 - 1 - read-only - - - - - AXIS2APB_ALMEM_RESP_CNT - response count - 0x290 - 32 - 0x00000000 - 0x000000FF - - - RDCNT - number of streams in queue - 0 - 8 - read-only - - - - - AXIS2APB_ALMEM_FILLSTS - fill status - 0x294 - 32 - 0x00000000 - 0x00000011 - - - FULL - FD FIFO full - 4 - 1 - read-only - - - EMPTY - FD FIFO failure - 0 - 1 - read-only - - - - - AXIS2APB_ALMEM_RESET - reset - 0x298 - 32 - 0x00000000 - 0x00000001 - - - RESET - Resets controller and clears all pending stream data - 0 - 1 - read-write - - - - - AXIS2APB_ALMEM_PARAM - parameter - 0x29c - 32 - 0x00000000 - 0x0000FFFF - - - DEPTH - number of configured buffer depth - 8 - 8 - read-only - - - WORDLEN_BYTE - number of configured 32bit for this controller - 0 - 8 - read-only - - - - - AXIS2APB_ALMEM_RESPDATA_0 - data0 - 0x2a0 - 32 - 0x00000000 - 0x01FFFFFF - - - UTAG - user sideband information - 22 - 3 - read-write - - - QSEL - define the traffic queue selection - 20 - 2 - read-write - - - DROP - frame should dropped - 19 - 1 - read-write - - - QUEUE - select the priority queue if qsel=11 - 16 - 3 - read-write - - - DEST - destination ports - 0 - 16 - read-write - - - - - AXIS2APB_ALMEM_RESPDATA_1 - data1 - 0x2a4 - 32 - 0x00000000 - 0xC000FFFF - - - WR_NRD - 1 for write and 0 for read - 31 - 1 - read-write - - - RESP - write response enable - 30 - 1 - read-write - - - ENTRY_NUM - define the entry number for reading and writing - 0 - 16 - read-write - - - - - 4 - 0x4 - HITMEM_REG_1,HITMEM_REG_2,HITMEM_REG_3,HITMEM_REG_4 - HITMEM[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - HITMEM_REG - Every bit represents a lookup entry starting with bit 0 -as entry 0. The memory can be written and cleared by the host system via common memory-mapped -bus access. - 0 - 32 - read-write - - - - - APB2AXIS_LOOKUP_STS - status register - 0x1000 - 32 - 0x00000000 - 0x00000003 - - - BUSY - the controller is writing data and/or data is pending - 1 - 1 - read-only - - - RDY - the new data is written to data register - 0 - 1 - read-only - - - - - APB2AXIS_LOOKUP_REQ_CNT - response count - 0x1010 - 32 - 0x00000000 - 0x000000FF - - - WRCNT - number of streams in queue - 0 - 8 - read-only - - - - - APB2AXIS_LOOKUP_FILLSTS - fill status - 0x1014 - 32 - 0x00000000 - 0x00000011 - - - FULL - FD FIFO full - 4 - 1 - read-only - - - EMPTY - FD FIFO failure - 0 - 1 - read-only - - - - - APB2AXIS_LOOKUP_RESET - reset - 0x1018 - 32 - 0x00000000 - 0x00000001 - - - RESET - Resets controller and clears all pending stream data - 0 - 1 - read-write - - - - - APB2AXIS_LOOKUP_PARAM - parameter - 0x101c - 32 - 0x00000000 - 0x0000FFFF - - - DEPTH - number of configured buffer depth - 8 - 8 - read-only - - - WORDLEN_BYTE - number of configured 32bit for this controller - 0 - 8 - read-only - - - - - APB2AXIS_LOOKUP_REQDATA_0 - LOOKUP REQUEST Register REQ_DATA_0 - 0x1020 - 32 - 0x00000000 - 0xFFFFFFFF - - - DESTMAC - Holding the first four bytes of requested MAC address. - 0 - 32 - read-write - - - - - APB2AXIS_LOOKUP_REQDATA_1 - LOOKUP REQUEST Register REQ_DATA_1 - 0x1024 - 32 - 0x00000000 - 0x0000FFFF - - - DESTMAC - Holding the last two bytes of requested MAC address. - 0 - 16 - read-write - - - - - APB2AXIS_LOOKUP_REQDATA_3 - LOOKUP REQUEST Register REQ_DATA_2 - 0x102c - 32 - 0x00000000 - 0x0001FFFF - - - IS_VLAN - Tell the LOOKUP module the requested traffic is VLAN tagged. - 16 - 1 - read-write - - - VLAN_TCI - Set the requested traffic VLAN_TCI, if IS_VLAN=1. - 0 - 16 - read-write - - - - - AXIS2APB_LOOKUP_STS - status register - 0x1080 - 32 - 0x00000000 - 0x00000003 - - - BUSY - the controller is writing data and/or data is pending - 1 - 1 - read-only - - - RDY - the new data is written to data register - 0 - 1 - read-only - - - - - AXIS2APB_LOOKUP_RESP_CNT - response count - 0x1090 - 32 - 0x00000000 - 0x000000FF - - - RDCNT - number of streams in queue - 0 - 8 - read-only - - - - - AXIS2APB_LOOKUP_FILLSTS - fill status - 0x1094 - 32 - 0x00000000 - 0x00000011 - - - FULL - FD FIFO full - 4 - 1 - read-only - - - EMPTY - FD FIFO failure - 0 - 1 - read-only - - - - - AXIS2APB_LOOKUP_RESET - reset - 0x1098 - 32 - 0x00000000 - 0x00000001 - - - RESET - Resets controller and clears all pending stream data - 0 - 1 - read-write - - - - - AXIS2APB_LOOKUP_PARAM - parameter - 0x109c - 32 - 0x00000000 - 0x0000FFFF - - - DEPTH - number of configured buffer depth - 8 - 8 - read-only - - - WORDLEN_BYTE - number of configured 32bit for this controller - 0 - 8 - read-only - - - - - AXIS2APB_LOOKUP_RESPDATA_0 - LOOKUP RESPONSE Data Register - 0x10a0 - 32 - 0x00000000 - 0x03FFFFFF - - - DROP_VLAN - Used for statistics. Shows that drop occurs by VLAN-ID - 25 - 1 - read-write - - - HIT - Is 1, if DESTMAC and VID hit an entry. - 24 - 1 - read-write - - - UTAG - TSN user sideband information from ALMEM. - 21 - 3 - read-write - - - HIT_VLAN - Is 1, if VID hit entry in VLAN_PORT table. - 20 - 1 - read-write - - - DROP - Indicate that the frame should be dropped. - 19 - 1 - read-write - - - QUEUE - TX traffic queue selection. - 16 - 3 - read-write - - - DEST - Forwarding ports from 0 to 15, Bit 0 is CPU port. - 0 - 16 - read-write - - - - - AXIS2APB_LOOKUP_RESPDATA_1 - LOOKUP RESPONSE Data Register - 0x10a8 - 32 - 0x00000000 - 0x0000FFFF - - - ENTRY_NUM - Entry number of ALMEM. - 0 - 16 - read-write - - - - - CENTRAL_CSR_VERSION - version register - 0x2000 - 32 - 0x00000000 - 0xFFFF00FF - - - VER_HI - Major Version number of TSN-SW core. - 24 - 8 - read-only - - - VER_LO - Minor Version number of TSN-SW core. - 16 - 8 - read-only - - - VER_REV - Reversion number of TSN-SW core. - 0 - 8 - read-only - - - - - CENTRAL_CSR_PARAM - Parameter Register - 0x2004 - 32 - 0x00000000 - 0x0007FFFF - - - INCL_QCI - Shows if QCI module is present. - 18 - 1 - read-only - - - INCL_CB0 - Shows if IP is configured with “lightweight” 802.1CB at CPU-Port. - 17 - 1 - read-only - - - TESTMODE - Shows if IP is configured in TESTMODE. - 16 - 1 - read-only - - - TYPE - Specify type of switch core - 8 - 8 - read-only - - - NPORTS - Number of TSN ports without counting internal CPU port. For TSN-SE, it returns always 2 - 0 - 8 - read-only - - - - - CENTRAL_CSR_CONFIG - Configuration Register - 0x2008 - 32 - 0x00100000 - 0x00FFFFFF - - - MSEC_CYCLES - Number of SYS_CLK cycles during 1 ms. It is required to calculate a correct time - 0 - 24 - read-write - - - - - CENTRAL_CSR_CB_PARAM - CB Parameter Register - 0x200c - 32 - 0x00000000 - 0x0000FFFF - - - SID_D - Number of 802.1CB Stream Identification entries. 2^SID_D entries - 8 - 8 - read-only - - - FRER_D - Number of 802.1CB Recovery Function entries. 2^FRER_D entries. - 0 - 8 - read-only - - - - - CENTRAL_CSR_QCI_CTRL_PARAM - QCI Control Parameter Register - 0x2010 - 32 - 0x00000000 - 0x00FFFFFF - - - QCI_GTD - (Log) gate table depth. 2**GTD entries. - 16 - 8 - read-only - - - QCI_FMD - (Log) flow meter depth. 2**FMD entries. - 8 - 8 - read-only - - - QCI_FTD - (Log) filter table depth. 2**FTD entries. - 0 - 8 - read-only - - - - - CENTRAL_QCI_HWCFG - PSPF General CTRAL - 0x2104 - 32 - 0x00000000 - 0x00FFFFFF - - - FMD - FMD – parameter - 16 - 8 - read-only - - - GTD - GTD – parameter - 8 - 8 - read-only - - - FTD - FTD – parameter - 0 - 8 - read-only - - - - - CENTRAL_QCI_FILTERSEL - Filter select index - 0x2110 - 32 - 0x00000000 - 0x000000FF - - - INDEX - Filter select index -Any written value larger than the maximum index -(2**FTD-1) will result in a read-back value of <0>. - 0 - 8 - read-write - - - - - CENTRAL_QCI_METERSEL - Flowmeter select index - 0x2114 - 32 - 0x00000000 - 0x000000FF - - - INDEX - Flowmeter select index -Any written value larger than the maximum index -(2**FMD-1) will result in a read-back value of <0>. - 0 - 8 - read-write - - - - - CENTRAL_QCI_GATESEL - Gate select index - 0x2118 - 32 - 0x00000000 - 0x000000FF - - - INDEX - Gate select index -Any written value larger than the maximum index -(2**GTD-1) will result in a read-back value of <0>. - 0 - 8 - read-write - - - - - CENTRAL_QCI_FCTRL - FILTER SETTING - 0x2120 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENBLK - Enable blocking of oversized frames -(802.1Qci – 8.6.5.1.1 (g)) - 31 - 1 - read-write - - - ENFSZ - 0: No frame size check -1: Frame size checking, size defined by FSIZE.MXSZ -(802.1Qci – 8.6.5.1.1 (e.1)) - 30 - 1 - read-write - - - ENFID - 0: No Flow Meter -1: Enable Flow Metering -(802.1Qci – 8.6.5.1.1 (e.2)) - 29 - 1 - read-write - - - ENSID - 0: Filter match any SID value -1: Filter match SID value -(802.1Qci – 8.6.5.1.1 (b)) - 28 - 1 - read-write - - - ENPCP - 0: Filter match any PCP value -1: Filter match PCP value -(802.1Qci – 8.6.5.1.1 (c)) - 27 - 1 - read-write - - - PCP - Filter priority code point, if enabled by ENPCP - 24 - 3 - read-write - - - FMD - Associated Flow Meter – if enabled by ENFID - 16 - 8 - read-write - - - GID - Associated Gate - 8 - 8 - read-write - - - SID - Filter Stream ID – if enabled by ENSID - 0 - 8 - read-write - - - - - CENTRAL_QCI_FSIZE - No description available - 0x2124 - 32 - 0x00000000 - 0x8000FFFF - - - BLK - Stream blocked due to oversize frame. -Write <1> to clear. -(802.1Qci – 8.6.5.1.1 (h)) - 31 - 1 - read-write - - - MXSZ - Maximum-SDU size in octets - 0 - 16 - read-write - - - - - 6 - 0x4 - CENTRAL_QCI_CNT0,CENTRAL_QCI_CNT1,CENTRAL_QCI_CNT2,CENTRAL_QCI_CNT3,CENTRAL_QCI_CNT4,CENTRAL_QCI_CNT5 - QCI_CNT[%s] - no description available - 0x2140 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Filter counter (see 802.1Qci 8.6.5.1.1 f) -CNT0: Frames that matched filter -CNT1: Frames that passed gate -CNT2: Frames that did not pass gate -CNT3: Frames that passed Maximum-SDU size check -CNT4: Frames that did not pass size check -CNT5: Frames discarded by Flow Meter operation -Counters starting at value <0> after reset. - 0 - 32 - read-only - - - - - CENTRAL_QCI_MCTRL - Flow meter settings - 0x2160 - 32 - 0x80000000 - 0x8000001F - - - RESET - Flow Meter reset – self-resetting to <0> - 31 - 1 - write-only - - - MAFR - MarkAllFramesRed – cleared by RESET -(802.1Qci – 8.6.5.1.3 (j)) - 4 - 1 - read-only - - - MAFREN - MarkAllFramesRedEnable -(802.1Qci – 8.6.5.1.3 (i)) - 3 - 1 - read-write - - - DOY - DropOnYellow -(802.1Qci – 8.6.5.1.3 (h)) - 2 - 1 - read-write - - - CM - Color mode – functionally unused -(802.1Qci – 8.6.5.1.3 (g)) - 1 - 1 - read-write - - - CF - Coupling flag -(802.1Qci – 8.6.5.1.3 (f)) - 0 - 1 - read-write - - - - - CENTRAL_QCI_CIR - No description available - 0x2170 - 32 - 0x00000000 - 0x00FFFFFF - - - CIR - Committed information rate – see Chapter 7.5.2.4. -(802.1Qci – 8.6.5.1.3 (b)) - 0 - 24 - read-write - - - - - CENTRAL_QCI_CBS - No description available - 0x2174 - 32 - 0x00000000 - 0xFFFFFFFF - - - CBS - Committed burst size, in bits (not octets!) -(802.1Qci – 8.6.5.1.3 (c)) - 0 - 32 - read-write - - - - - CENTRAL_QCI_EIR - No description available - 0x2178 - 32 - 0x00000000 - 0x00FFFFFF - - - EIR - Excess information rate – see Chapter 7.5.2.4. -(802.1Qci – 8.6.5.1.3 (d)) - 0 - 24 - read-write - - - - - CENTRAL_QCI_EBS - No description available - 0x217c - 32 - 0x00000000 - 0xFFFFFFFF - - - EBS - Excess burst size, in bits (not octets) -(802.1Qci – 8.6.5.1.3 (e)) - 0 - 32 - read-write - - - - - CENTRAL_QCI_GCTRL - Gate settings - 0x2180 - 32 - 0x00000000 - 0x000000FF - - - IPV - Administrative internal priority value specification -(802.1Qci – 8.6.5.1.2 (c)) - 5 - 3 - read-write - - - STATE - Administrative stream gate state -(802.1Qci – 8.6.5.1.2 (b)) - 4 - 1 - read-write - - - CDOEE - Gate – ClosedDueToOctetsExceededEnable -(802.1Qci – 8.6.5.1.2 (f)) - 3 - 1 - read-write - - - CDIRE - Gate – ClosedDueToInvalidRxEnable -(802.1Qci – 8.6.5.1.2 (d)) - 2 - 1 - read-write - - - CFGCH - Gate – change config (self-resetting to <0>) - 1 - 1 - read-write - - - EN - Gate control – enable - 0 - 1 - read-write - - - - - CENTRAL_QCI_GSTATUS - No description available - 0x2184 - 32 - 0x00000000 - 0x000000FF - - - IPV - Operational internal priority value specification -(802.1Qci – 8.6.5.1.2 (c)) - 5 - 3 - read-only - - - STATE - Operational stream gate state -(802.1Qci – 8.6.5.1.2 (b)) - 4 - 1 - read-only - - - CDOE - Gate – ClosedDueToOctetsExceeded. Write <1> to -clear. -(802.1Qci – 8.6.5.1.2 (g)) - 3 - 1 - write-only - - - CDIR - Gate – ClosedDueToInvalidRx. Write <1> to clear. -(802.1Qci – 8.6.5.1.2 (e)) - 2 - 1 - write-only - - - CFGP - Configuration change pending - 1 - 1 - read-only - - - CFGERR - Configuration change error. Write <1> to clear. - 0 - 1 - write-only - - - - - CENTRAL_QCI_GLISTINDEX - No description available - 0x2188 - 32 - 0x00000000 - 0x0000000F - - - IDX - Admin list pointer, select entry 0 – 15. - 0 - 4 - read-write - - - - - CENTRAL_QCI_LISTLEN - No description available - 0x218c - 32 - 0x00000000 - 0x000F000F - - - OLEN - Operational list length - 16 - 4 - read-only - - - ALEN - Administrative list length - 0 - 4 - read-write - - - - - CENTRAL_QCI_ACYCLETM - No description available - 0x2190 - 32 - 0x00000000 - 0x3FFFFFFF - - - ACT - Administrative cycle time length, nanoseconds. - 0 - 30 - read-write - - - - - CENTRAL_QCI_ABASETM_L - No description available - 0x2194 - 32 - 0x00000000 - 0x3FFFFFFF - - - ABTL - Administrative base time. Nanoseconds and seconds part. Cycle starts after becoming operational when time is reached by inputs <rtc_sec> and <rtc_ns>. - 0 - 30 - read-write - - - - - CENTRAL_QCI_ABASETM_H - No description available - 0x2198 - 32 - 0x00000000 - 0xFFFFFFFF - - - ABTH - No description available - 0 - 32 - read-write - - - - - CENTRAL_QCI_AENTRY_CTRL - No description available - 0x21a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATE - AdminList – gate state (1: open) - 31 - 1 - read-write - - - IPV - AdminList – IPV - 28 - 3 - read-write - - - OCT - AdminList – maximum octets (0 – disabled) - 0 - 28 - read-write - - - - - CENTRAL_QCI_AENTRY_AENTRY_IVAL - No description available - 0x21a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - IVAL - AdminList – time interval in clock ticks - 0 - 32 - read-write - - - - - CENTRAL_QCI_AENTRY_OCYCLETM - No description available - 0x21a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - OCT - OperCycleTime in nanoseconds - 0 - 32 - read-only - - - - - CENTRAL_QCI_AENTRY_OBASETM_L - No description available - 0x21ac - 32 - 0x00000000 - 0xFFFFFFFF - - - OBTL - OperBaseTime – nanoseconds and seconds. Constantly -updated – OperBaseTime + N * OperCycleTimt. Might -be non-normalized. - 0 - 32 - read-only - - - - - CENTRAL_QCI_AENTRY_OBASETM_H - No description available - 0x21b0 - 32 - 0x00000000 - 0xFFFFFFFF - - - OBTH - No description available - 0 - 32 - read-only - - - - - MM2S_DMA_CR - mm2s control register - 0x4000 - 32 - 0x0F000000 - 0xFF00000F - - - MXLEN - max axi burst size - 24 - 8 - read-write - - - IRQEN - interrupt request enable - 3 - 1 - read-write - - - RESET - do reset when active - 2 - 1 - write-only - - - SOE - stop on error flag - 1 - 1 - read-write - - - RUN - run command from queue to data mover - 0 - 1 - read-write - - - - - MM2S_DMA_SR - mm2s status - 0x4004 - 32 - 0x00000050 - 0x000000FF - - - RBUFF - response buffer full - 7 - 1 - read-only - - - RBUFE - response buffer empty - 6 - 1 - read-only - - - CBUFF - command buffer full - 5 - 1 - read-only - - - CBUFE - command buffer empty - 4 - 1 - read-only - - - IRQ - interrupt request pending - 3 - 1 - read-write - - - RSET - resetting status - 2 - 1 - read-only - - - BUSY - busy - 1 - 1 - read-only - - - STOP - mm2s is stopped - 0 - 1 - read-only - - - - - MM2S_DMA_FILL - mm2s dma fill status - 0x4008 - 32 - 0x00000000 - 0xFFFFFFFF - - - RFILL - response buffer fill level - 16 - 16 - read-only - - - CFILL - command buffer fill level - 0 - 16 - read-only - - - - - MM2S_DMA_CFG - mm2s dma configure - 0x401c - 32 - 0x00000000 - 0x0FFFFFFF - - - DBUFD - data buffer depth - 24 - 4 - read-only - - - CBUFD - command buffer depth - 20 - 4 - read-only - - - ENA64 - enable support for 64 bit addressing - 19 - 1 - read-only - - - ASIZE - axi data bus width - 16 - 3 - read-only - - - VER - ip version - 0 - 16 - read-only - - - - - MM2S_ADDRLO - mm2s axi address - 0x4020 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - axi address - 0 - 32 - read-write - - - - - MM2S_LENGTH - mm2s axi length - 0x4028 - 32 - 0x00000000 - 0x0000FFFF - - - LENGTH - transfer request length in bytes - 0 - 16 - read-write - - - - - MM2S_CTRL - mm2s command control - 0x402c - 32 - 0x00000000 - 0x8000001F - - - GO - commit buffered descriptor to command queue - 31 - 1 - write-only - - - NGENLAST - no generation of TLAST - 4 - 1 - read-write - - - ID - command id - 0 - 4 - read-write - - - - - MM2S_RESP - mm2s response buffer - 0x4030 - 32 - 0x00000000 - 0x7F00FFFF - - - LAST - axi-stream with TLAST - 30 - 1 - read-only - - - DECERR - decode error - 29 - 1 - read-only - - - SLVERR - slave error - 28 - 1 - read-only - - - ID - command ID feedback - 24 - 4 - read-only - - - LENGTH - requested length of tansfer in bytes from command - 0 - 16 - read-only - - - - - S2MM_DMA_CR - s2mm dma control - 0x4080 - 32 - 0x0F000000 - 0xFF00000F - - - MXLEN - max axi burst size - 24 - 8 - read-write - - - IRQEN - interrupt request enable - 3 - 1 - read-write - - - RESET - do reset when writing 1 - 2 - 1 - write-only - - - SOE - stop on error flag - 1 - 1 - read-write - - - RUN - run commands from queue to data mover - 0 - 1 - read-write - - - - - S2MM_DMA_SR - s2mm state - 0x4084 - 32 - 0x00000050 - 0x000000FF - - - RBUFF - response buffer full - 7 - 1 - read-only - - - RBUFE - response buffer empty - 6 - 1 - read-only - - - CBUFF - command buffer full - 5 - 1 - read-only - - - CBUFE - command buffer empty - 4 - 1 - read-only - - - IRQ - interrupt request pending - 3 - 1 - read-write - - - RSET - resetting status - 2 - 1 - read-only - - - BUSY - busy, issued command and outstanding response - 1 - 1 - read-only - - - STOP - s2mm is stopped - 0 - 1 - read-only - - - - - S2MM_DMA_FILL - s2mm buffer fill status - 0x4088 - 32 - 0x00000000 - 0xFFFFFFFF - - - RFILL - response buffer fill level - 16 - 16 - read-only - - - CFILL - command buffer fill level - 0 - 16 - read-only - - - - - S2MM_DMA_CFG - s2mm dma config status - 0x409c - 32 - 0x00000000 - 0x0FFFFFFF - - - DBUFD - data buffer depth - 24 - 4 - read-only - - - CBUFD - command buffer depth - 20 - 4 - read-only - - - ENA64 - enabled support for 64 bit - 19 - 1 - read-only - - - ASIZE - axi data bus width - 16 - 3 - read-only - - - VER - IP version - 0 - 16 - read-only - - - - - S2MM_ADDRLO - s2mm axi address - 0x40a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDRLO - axi address - 0 - 32 - read-write - - - - - S2MM_LENGTH - s2mm axi length - 0x40a8 - 32 - 0x00000000 - 0x0000FFFF - - - LENGTH - transfer request length in bytes - 0 - 16 - read-write - - - - - S2MM_CTRL - s2mm command control - 0x40ac - 32 - 0x00000000 - 0x8000000F - - - GO - commit buffered descriptor to command queue - 31 - 1 - write-only - - - ID - command id - 0 - 4 - read-write - - - - - S2MM_RESP - s2mm response buffer - 0x40b0 - 32 - 0x00000000 - 0x7F00FFFF - - - LAST - axi-stream with last - 30 - 1 - read-only - - - DECERR - decode error - 29 - 1 - read-only - - - SLVERR - slave error - 28 - 1 - read-only - - - ID - command ID feedback - 24 - 4 - read-only - - - LENGTH - received packet size when terminated by TLAST - 0 - 16 - read-only - - - - - PTP_EVT_TS_CTL - timestamp control - 0x6000 - 32 - 0x00000000 - 0x1F000010 - - - ATSEN - auxiliay snapshot enable - 25 - 4 - read-write - - - ATSFC - auxiliary snapshot fifo clear - 24 - 1 - write-only - - - TSTIG - timestamp interrupt trigger enable - 4 - 1 - read-write - - - - - PTP_EVT_PPS_TOD_SEC - pps tod seconds - 0x6008 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS_TOD_SEC - pps tod seconds - 0 - 32 - read-only - - - - - PTP_EVT_PPS_TOD_NS - pps tod sun seconds - 0x600c - 32 - 0x00000000 - 0x3FFFFFFF - - - PPS_TOD_NS - pps tod sub seconds - 0 - 30 - read-only - - - - - PTP_EVT_SCP_SEC0 - target time seconds - 0x601c - 32 - 0x00000000 - 0xFFFFFFFF - - - SCP_SEC - target time seconds - 0 - 32 - read-write - - - - - PTP_EVT_SCP_NS0 - target time sub seconds - 0x6020 - 32 - 0x00000000 - 0x3FFFFFFF - - - SCP_NS - target time sub seconds - 0 - 30 - read-write - - - - - PTP_EVT_TMR_STS - timer status - 0x6028 - 32 - 0x00000000 - 0x3F0F07FE - - - RD_CNT - fifo valid count - 25 - 5 - read-only - - - ATSSTM - auxiliary fifo full error - 24 - 1 - read-only - - - ATPORT - auxiliary port - 16 - 4 - read-only - - - PPS_TOD_INTR - pps tod intrrupt - 10 - 1 - read-only - - - TARGET_TIME3_CFG_ERR - target time3 configure error - 9 - 1 - read-only - - - TARGET_TIME3_REACH_INTR - target time3 reached - 8 - 1 - read-only - - - TARGET_TIME2_CFG_ERR - target time2 configure error - 7 - 1 - read-only - - - TARGET_TIME2_REACH_INTR - target time2 reached - 6 - 1 - read-only - - - TARGET_TIME1_CFG_ERR - target time1 configure error - 5 - 1 - read-only - - - TARGET_TIME1_REACH_INTR - target time1 reached - 4 - 1 - read-only - - - TARGET_TIME0_CFG_ERR - target time0 configure error - 3 - 1 - read-only - - - PTP_FIFO_WR_INTR - auxiliary timestamp trigger snapshot - 2 - 1 - read-only - - - TARGET_TIME0_REACH_INTR - target time0 reached - 1 - 1 - read-only - - - - - PTP_EVT_PPS_CMD - pps command control - 0x602c - 32 - 0x00000000 - 0x6767677F - - - PPS_MODE3 - Target Time Register Mode for PPS3 Output - 29 - 2 - read-write - - - PPS_CMD3 - pps3 command - 24 - 3 - read-write - - - PPS_MODE2 - Target Time Register Mode for PPS2 Output - 21 - 2 - read-write - - - PPS_CMD2 - pps2 command - 16 - 3 - read-write - - - PPS_MODE1 - Target Time Register Mode for PPS1 Output - 13 - 2 - read-write - - - PPS_CMD1 - pps1 command - 8 - 3 - read-write - - - PPS_MODE0 - Target Time Register Mode for PPS0 Output - 5 - 2 - read-write - - - PPS_EN0 - flexible PPS0 output mode enable - 4 - 1 - read-write - - - PPS_CMD0 - pps0 command - 0 - 4 - read-write - - - - - PTP_EVT_ATSLO - auxiliray read data sub seconds - 0x6030 - 32 - 0x00000000 - 0x7FFFFFFF - - - STSLO - auxiliary fifo read sub seconds info - 0 - 31 - read-only - - - - - PTP_EVT_ATSHI - auxiliray read data seconds - 0x6034 - 32 - 0x00000000 - 0xFFFFFFFF - - - STSHI - auxiliary fifo read seconds info - 0 - 32 - read-only - - - - - PTP_EVT_PPS0_INTERVAL - pps0 interval configure - 0x6060 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS0 output signal interval - 0 - 32 - read-write - - - - - PTP_EVT_PPS0_WIDTH - pps0 width configure - 0x6064 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS_WIDTH - pps0 output signal width - 0 - 32 - read-write - - - - - PTP_EVT_SCP_SEC1 - target time seconds - 0x6080 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCP_SEC - target time seconds - 0 - 32 - read-write - - - - - PTP_EVT_SCP_NS1 - target time sub seconds - 0x6084 - 32 - 0x00000000 - 0x3FFFFFFF - - - SCP_NS - target time sub seconds - 0 - 30 - read-write - - - - - PTP_EVT_PPS1_INTERVAL - pps1 interval configure - 0x6088 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS1 output signal interval - 0 - 32 - read-write - - - - - PTP_EVT_PPS1_WIDTH - pps1 width configure - 0x608c - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS_WIDTH - pps1 output signal width - 0 - 32 - read-write - - - - - PTP_EVT_SCP_SEC2 - target time seconds - 0x60a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCP_SEC - target time seconds - 0 - 32 - read-write - - - - - PTP_EVT_SCP_NS2 - target time sub seconds - 0x60a4 - 32 - 0x00000000 - 0x3FFFFFFF - - - SCP_NS - target time sub seconds - 0 - 30 - read-write - - - - - PTP_EVT_PPS2_INTERVAL - pps2 interval configure - 0x60a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS2 output signal interval - 0 - 32 - read-write - - - - - PTP_EVT_PPS2_WIDTH - pps2 width configure - 0x60ac - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS_WIDTH - pps2 output signal width - 0 - 32 - read-write - - - - - PTP_EVT_SCP_SEC3 - target time seconds - 0x60c0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCP_SEC - target time seconds - 0 - 32 - read-write - - - - - PTP_EVT_SCP_NS3 - target time sub seconds - 0x60c4 - 32 - 0x00000000 - 0x3FFFFFFF - - - SCP_NS - target time sub seconds - 0 - 30 - read-write - - - - - PTP_EVT_PPS3_INTERVAL - pps3 interval configure - 0x60c8 - 32 - 0x00000000 - 0xFFFFFFFF - - - PPSINT - PPS3 output signal interval - 0 - 32 - read-write - - - - - PTP_EVT_PPS3_WIDTH - pps3 width configure - 0x60cc - 32 - 0x00000000 - 0xFFFFFFFF - - - PPS_WIDTH - pps3 output signal width - 0 - 32 - read-write - - - - - PTP_EVT_PPS_CTRL0 - pps control 0 register - 0x60e0 - 32 - 0x0000000A - 0x0000000F - - - PPS_TOD_INTR_MSK - pps tod interrupt enable - 3 - 1 - read-write - - - TARGET_RAC_INTR_MSK - target timmer interrupt mask - 2 - 1 - read-write - - - FIFO_WR_INTR_MSK - auxiliary snapshot fifo write interrupt enable - 1 - 1 - read-write - - - TIME_SEL - timer selection - 0 - 1 - read-write - - - - - PTP_EVT_PPS_SEL - No description available - 0x60e4 - 32 - 0x00000000 - 0x1F1F1F1F - - - PPS3_SEL - pps selection for pps3 - 24 - 5 - read-write - - - PPS2_SEL - pps selection for pps2 - 16 - 5 - read-write - - - PPS1_SEL - pps selection for pps1 - 8 - 5 - read-write - - - PPS0_SEL - pps selection for pps0 - 0 - 5 - read-write - - - - - SOFT_RST_CTRL - softer reset control - 0x60f0 - 32 - 0x00000000 - 0x00000D3F - - - TSN_CORE_RST - tsn core reset control - 11 - 1 - read-write - - - PTP_EVT_RST - ptp event module reset control - 10 - 1 - read-write - - - DMA0_RST - dma0 reset control - 8 - 1 - read-write - - - PORT3_RX_RST - port3 rx reset control - 5 - 1 - read-write - - - PORT3_TX_RST - port3 tx reset control - 4 - 1 - read-write - - - PORT2_RX_RST - port2 rx reset control - 3 - 1 - read-write - - - PORT2_TX_RST - port2 tx reset control - 2 - 1 - read-write - - - PORT1_RX_RST - port1 rx reset control - 1 - 1 - read-write - - - PORT1_TX_RST - port1 tx reset control - 0 - 1 - read-write - - - - - CPU_PORT_PORT_MAIN_TAGGING - PVID Tagging Register - 0x10000 - 32 - 0x00000001 - 0x0003FFFF - - - FORCE - The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports - 17 - 1 - read-write - - - ACCESS - Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged - 16 - 1 - read-write - - - PCP - VLAN-TCI: Priority Code Point, used when tagged. - 13 - 3 - read-write - - - DEI - VLAN-TCI: Drop Eligible Indicator, used when tagged. - 12 - 1 - read-write - - - PVID - Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1. - 0 - 12 - read-write - - - - - CPU_PORT_PORT_MAIN_ENNABLE - Port Module Enable Register - 0x10004 - 32 - 0x00000003 - 0x00000003 - - - EN_SF - only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption - 1 - 1 - read-write - - - EN_QCI - if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption. - 0 - 1 - read-write - - - - - CPU_PORT_EGRESS_STMID_ESELECT - Stream Identification - 0x12800 - 32 - 0x00000000 - 0x000000FF - - - ESEL - Select entry. Selected entry mapped to 0x40 – 0x5C. - 0 - 8 - read-only - - - - - CPU_PORT_EGRESS_STMID_CONTROL - No description available - 0x12840 - 32 - 0x00000000 - 0x0000FFFF - - - SID - Stream ID – inserted to header on match - 8 - 8 - read-write - - - SEQGEN - Sequence number generation enable - 7 - 1 - read-write - - - ACTCTL - Active Destination MAC – control. See Table 6-6. - 4 - 2 - read-write - - - SMAC - 0: Lookup by Destination MAC 1: Lookup by Source MAC - 3 - 1 - read-write - - - MODE - Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged - 1 - 2 - read-write - - - EN - Enable entry - 0 - 1 - read-write - - - - - CPU_PORT_EGRESS_STMID_SEQNO - No description available - 0x12844 - 32 - 0x00000000 - 0x0000FFFF - - - SEQNO - Sequence number – next number when generating,any write access to clear. - 0 - 16 - read-write - - - - - CPU_PORT_EGRESS_STMID_MATCHCNT - No description available - 0x12848 - 32 - 0x00000000 - 0xFFFFFFFF - - - MATCH - Entry match counter – any write access to clear. - 0 - 32 - read-write - - - - - CPU_PORT_EGRESS_STMID_MACLO - No description available - 0x12850 - 32 - 0x00000000 - 0xFFFFFFFF - - - MACL - MAC-Address [31:0] used by lookup. - 0 - 32 - read-write - - - - - CPU_PORT_EGRESS_STMID_MACHI - No description available - 0x12854 - 32 - 0x00000000 - 0x0FFFFFFF - - - VID - VLAN ID used by lookup. - 16 - 12 - read-write - - - MATCH - MAC-Address [47:31] used by lookup. - 0 - 16 - read-write - - - - - CPU_PORT_EGRESS_STMID_AMACHI - No description available - 0x1285c - 32 - 0x00000000 - 0xFFFFFFFF - - - APCP - Active Destination MAC, PCP - 28 - 4 - read-write - - - AVID - Active Destination MAC, VLAN ID - 16 - 12 - read-write - - - AMACH - Active Destination MAC, MAC-Address [47:32] - 0 - 16 - read-write - - - - - CPU_PORT_EGRESS_FRER_CONTROL - Frame Replication and Elimination - 0x12a00 - 32 - 0x00000000 - 0x00000003 - - - LATER - Latent error flag – write 1 to clear - 1 - 1 - read-write - - - RTENC - R-TAG encoding enable. - 0 - 1 - read-write - - - - - CPU_PORT_EGRESS_FRER_SIDSEL - No description available - 0x12a04 - 32 - 0x00000000 - 0x000000FF - - - SID - Stream ID selection for host access to IRFUNC and SRFUNC. - 0 - 8 - read-write - - - - - CPU_PORT_EGRESS_FRER_IRFUNC - No description available - 0x12a08 - 32 - 0x00000000 - 0x800000FF - - - FEN - Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - 31 - 1 - read-write - - - FIDX - No description available - 0 - 8 - read-write - - - - - CPU_PORT_EGRESS_FRER_SRFUNC - No description available - 0x12a0c - 32 - 0x00000000 - 0x800000FF - - - FEN - Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - 31 - 1 - read-write - - - FIDX - No description available - 0 - 8 - read-write - - - - - CPU_PORT_EGRESS_FRER_FSELECT - No description available - 0x12a10 - 32 - 0x00000000 - 0x000000FF - - - FIDX - Recovery function selection for host access at offset 0x140+ - 0 - 8 - read-write - - - - - CPU_PORT_EGRESS_FRER_FCTRL - No description available - 0x12a40 - 32 - 0x00000000 - 0x80FFFFFF - - - FRSET - Reset recovery function – self-resetting to 0 - 31 - 1 - write-only - - - PATHS - Number of paths (used by latent error detection) - 16 - 8 - read-write - - - HLEN - History length (used by Vector recovery algorithm) - 8 - 5 - read-write - - - ALGO - Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm - 4 - 1 - read-write - - - LATEN - Latent error detection enable - 3 - 1 - read-write - - - IND - Individual function (802.1CB 10.4.1.10) - 2 - 1 - read-write - - - TNS - TakeNoSequence (802.1CB 10.4.1.9) - 1 - 1 - read-write - - - - - CPU_PORT_EGRESS_FRER_RESETMSEC - No description available - 0x12a44 - 32 - 0x00000000 - 0x00FFFFFF - - - FSRMS - frerSeqRcvyResetMSec (802.1CB 10.4.1.7) - 0 - 24 - read-write - - - - - CPU_PORT_EGRESS_FRER_LatRsPeriod - No description available - 0x12a48 - 32 - 0x00000000 - 0x00FFFFFF - - - FLATR - frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4) - 0 - 24 - read-write - - - - - CPU_PORT_EGRESS_FRER_LatTestPeriod - No description available - 0x12a4c - 32 - 0x00000000 - 0x00FFFFFF - - - FLATT - frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2) - 0 - 24 - read-write - - - - - CPU_PORT_EGRESS_FRER_LatErrDiffAlw - No description available - 0x12a50 - 32 - 0x00000000 - 0xFFFFFFFF - - - FDIFF - frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1) - 0 - 32 - read-write - - - - - CPU_PORT_EGRESS_FRER_LatErrCnt - No description available - 0x12a54 - 32 - 0x00000000 - 0xFFFFFFFF - - - LATERR - Counter – latent error detect. Write any value to clear - 0 - 32 - read-write - - - - - 8 - 0x4 - CPU_PORT_EGRESS_FRER_CNT0,CPU_PORT_EGRESS_FRER_CNT1,CPU_PORT_EGRESS_FRER_CNT2,CPU_PORT_EGRESS_FRER_CNT3,CPU_PORT_EGRESS_FRER_CNT4,CPU_PORT_EGRESS_FRER_CNT5,CPU_PORT_EGRESS_FRER_CNT6,CPU_PORT_EGRESS_FRER_CNT7 - EGFRCNT[%s] - no description available - 0x12a60 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Frame counters - 0 - 32 - read-only - - - - - CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE - No description available - 0x14000 - 32 - 0x00000000 - 0xFFFFFFFF - - - FDMEM_CNT_BYTE - Number of bytes stored in frame drop FIFO - 0 - 32 - read-only - - - - - CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS - No description available - 0x14004 - 32 - 0x00000000 - 0x00000F0F - - - WAIT_FOR_LU - FD FIFO waits for LookUp information. - 11 - 1 - read-only - - - WAIT_FOR_FRAME - FD FIFO waits for more frame data. - 10 - 1 - read-only - - - BUSY - FD FIFO processes data. - 9 - 1 - read-only - - - READY - FD FIFO ready to work or working. - 8 - 1 - read-only - - - FULL - FD FIFO full - 3 - 1 - read-only - - - AMST_FULL - FD FIFO almost full. Less than 1600 Byte left. - 2 - 1 - read-only - - - AMST_EMPTY - FD FIFO almost empty. Few bytes in FIFO. - 1 - 1 - read-only - - - EMPTY - FD FIFO empty - 0 - 1 - read-only - - - - - CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG - No description available - 0x14008 - 32 - 0x00000000 - 0x0000007F - - - LU_DESC_ERR - LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset. - 6 - 1 - read-write - - - WRFAIL_FULL - Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set. - 5 - 1 - read-write - - - DROP_NRDY - Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO - 4 - 1 - read-write - - - DROP_FULL_DESC - Frame was dropped because the internal descriptor FIFO is full. Full by too many frames. - 3 - 1 - read-write - - - DROP_FULL_MEM - Frame was dropped because the FIFO is full. Full by too much data. - 2 - 1 - read-write - - - DESC_NRDY_ERR - FD FIFO failure. Descriptor not received correctly. - 1 - 1 - read-write - - - DESC_SEQ_ERR - FD FIFO failure. Internal controller lost synchronization. - 0 - 1 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG - No description available - 0x1400c - 32 - 0x00000000 - 0x0000007F - - - IE - Interrupt enable of ERROR_FLAG. - 0 - 7 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG - No description available - 0x14010 - 32 - 0x00000000 - 0x00000001 - - - NOCUT_ERROR - FD_FIFO does not shorten frames which contain an error. - 0 - 1 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG - No description available - 0x14014 - 32 - 0x00000000 - 0xFFFF037F - - - DROP_DEST - Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0]. - 16 - 16 - read-write - - - MIRROR_TX_EN - Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX. - 9 - 1 - read-write - - - MIRROR_RX_EN - Incoming frames of this port will be mirrored to the given destination in MIRROR_RX. - 8 - 1 - read-write - - - CT_FPE_OVRD - If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F. - 6 - 1 - read-write - - - DISABLE - Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL. - 5 - 1 - read-write - - - DROP_ALL - Route all frames to DROP_DEST. - 4 - 1 - read-write - - - ERROR_TO_CPU - Send error frames to CPU. - 3 - 1 - read-write - - - MIRROR_TO_CPU - Duplicate frames to CPU. - 2 - 1 - read-write - - - NODROP_ERROR - Do not drop frame errors. - 1 - 1 - read-write - - - MODE_STORE_FW - Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward - 0 - 1 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_RESET - No description available - 0x14018 - 32 - 0x00000000 - 0x00000001 - - - SOFTRS - Write 1 to reset FD controller and memory pointers. Register Map content remains untouched - 0 - 1 - write-only - - - - - CPU_PORT_IGRESS_RX_FDFIFO_PARAM - No description available - 0x1401c - 32 - 0x00000000 - 0xFFFFFFFF - - - LU_FIFO_DEPTH - Number of MAC lookup descriptors the FIFO can store. - 24 - 8 - read-only - - - FD_DESC_FIFO_DESC - Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame. - 16 - 8 - read-only - - - FD_FIFO_DESC - Number of words (4byte) the Frame Drop FIFO can store. - 0 - 16 - read-only - - - - - CPU_PORT_IGRESS_RX_FDFIFO_STRFWD - No description available - 0x14020 - 32 - 0x00000000 - 0x01FFFFFF - - - PORT - If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK - No description available - 0x14024 - 32 - 0x001FFFFF - 0x01FFFFFF - - - PORT - Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports). -bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_MIRROR - No description available - 0x14028 - 32 - 0x00000000 - 0x01FFFFFF - - - PORT - Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port. -bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX - No description available - 0x1402c - 32 - 0x00000000 - 0x01FFFFFF - - - PORT - Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic. -bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - CPU_PORT_IGRESS_STMID_ESELECT - Stream Identification - 0x14800 - 32 - 0x00000000 - 0x000000FF - - - ESEL - Select entry. Selected entry mapped to 0x40 – 0x5C. - 0 - 8 - read-only - - - - - CPU_PORT_IGRESS_STMID_CONTROL - No description available - 0x14840 - 32 - 0x00000000 - 0x0000FFFF - - - SID - Stream ID – inserted to header on match - 8 - 8 - read-write - - - SEQGEN - Sequence number generation enable - 7 - 1 - read-write - - - ACTCTL - Active Destination MAC – control. See Table 6-6. - 4 - 2 - read-write - - - SMAC - 0: Lookup by Destination MAC 1: Lookup by Source MAC - 3 - 1 - read-write - - - MODE - Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged - 1 - 2 - read-write - - - EN - Enable entry - 0 - 1 - read-write - - - - - CPU_PORT_IGRESS_STMID_SEQNO - No description available - 0x14844 - 32 - 0x00000000 - 0x0000FFFF - - - SEQNO - Sequence number – next number when generating,any write access to clear. - 0 - 16 - read-write - - - - - CPU_PORT_IGRESS_STMID_MATCHCNT - No description available - 0x14848 - 32 - 0x00000000 - 0xFFFFFFFF - - - MATCH - Entry match counter – any write access to clear. - 0 - 32 - read-write - - - - - CPU_PORT_IGRESS_STMID_MACLO - No description available - 0x14850 - 32 - 0x00000000 - 0xFFFFFFFF - - - MACL - MAC-Address [31:0] used by lookup. - 0 - 32 - read-write - - - - - CPU_PORT_IGRESS_STMID_MACHI - No description available - 0x14854 - 32 - 0x00000000 - 0x0FFFFFFF - - - VID - VLAN ID used by lookup. - 16 - 12 - read-write - - - MATCH - MAC-Address [47:31] used by lookup. - 0 - 16 - read-write - - - - - CPU_PORT_IGRESS_STMID_AMACHI - No description available - 0x1485c - 32 - 0x00000000 - 0xFFFFFFFF - - - APCP - Active Destination MAC, PCP - 28 - 4 - read-write - - - AVID - Active Destination MAC, VLAN ID - 16 - 12 - read-write - - - AMACH - Active Destination MAC, MAC-Address [47:32] - 0 - 16 - read-write - - - - - CPU_PORT_IGRESS_FRER_CONTROL - Frame Replication and Elimination - 0x14a00 - 32 - 0x00000000 - 0x00000003 - - - LATER - Latent error flag – write 1 to clear - 1 - 1 - read-write - - - RTENC - R-TAG encoding enable. - 0 - 1 - read-write - - - - - CPU_PORT_IGRESS_FRER_SIDSEL - No description available - 0x14a04 - 32 - 0x00000000 - 0x000000FF - - - SID - Stream ID selection for host access to IRFUNC and SRFUNC. - 0 - 8 - read-write - - - - - CPU_PORT_IGRESS_FRER_IRFUNC - No description available - 0x14a08 - 32 - 0x00000000 - 0x800000FF - - - FEN - Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - 31 - 1 - read-write - - - FIDX - No description available - 0 - 8 - read-write - - - - - CPU_PORT_IGRESS_FRER_SRFUNC - No description available - 0x14a0c - 32 - 0x00000000 - 0x800000FF - - - FEN - Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - 31 - 1 - read-write - - - FIDX - No description available - 0 - 8 - read-write - - - - - CPU_PORT_IGRESS_FRER_FSELECT - No description available - 0x14a10 - 32 - 0x00000000 - 0x000000FF - - - FIDX - Recovery function selection for host access at offset 0x140+ - 0 - 8 - read-write - - - - - CPU_PORT_IGRESS_FRER_FCTRL - No description available - 0x14a40 - 32 - 0x00000000 - 0x80FFFFFF - - - FRSET - Reset recovery function – self-resetting to 0 - 31 - 1 - write-only - - - PATHS - Number of paths (used by latent error detection) - 16 - 8 - read-write - - - HLEN - History length (used by Vector recovery algorithm) - 8 - 5 - read-write - - - ALGO - Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm - 4 - 1 - read-write - - - LATEN - Latent error detection enable - 3 - 1 - read-write - - - IND - Individual function (802.1CB 10.4.1.10) - 2 - 1 - read-write - - - TNS - TakeNoSequence (802.1CB 10.4.1.9) - 1 - 1 - read-write - - - - - CPU_PORT_IGRESS_FRER_RESETMSEC - No description available - 0x14a44 - 32 - 0x00000000 - 0x00FFFFFF - - - FSRMS - frerSeqRcvyResetMSec (802.1CB 10.4.1.7) - 0 - 24 - read-write - - - - - CPU_PORT_IGRESS_FRER_LatRsPeriod - No description available - 0x14a48 - 32 - 0x00000000 - 0x00FFFFFF - - - FLATR - frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4) - 0 - 24 - read-write - - - - - CPU_PORT_IGRESS_FRER_LatTestPeriod - No description available - 0x14a4c - 32 - 0x00000000 - 0x00FFFFFF - - - FLATT - frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2) - 0 - 24 - read-write - - - - - CPU_PORT_IGRESS_FRER_LatErrDiffAlw - No description available - 0x14a50 - 32 - 0x00000000 - 0xFFFFFFFF - - - FDIFF - frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1) - 0 - 32 - read-write - - - - - CPU_PORT_IGRESS_FRER_LatErrCnt - No description available - 0x14a54 - 32 - 0x00000000 - 0xFFFFFFFF - - - LATERR - Counter – latent error detect. Write any value to clear - 0 - 32 - read-write - - - - - 8 - 0x4 - CPU_PORT_IGRESS_FRER_CNT0,CPU_PORT_IGRESS_FRER_CNT1,CPU_PORT_IGRESS_FRER_CNT2,CPU_PORT_IGRESS_FRER_CNT3,CPU_PORT_IGRESS_FRER_CNT4,CPU_PORT_IGRESS_FRER_CNT5,CPU_PORT_IGRESS_FRER_CNT6,CPU_PORT_IGRESS_FRER_CNT7 - IGFRCNT[%s] - no description available - 0x14a60 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Frame counters - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_CTRL - No description available - 0x18004 - 32 - 0x00000000 - 0x00000001 - - - EN - Enables counter. If deasserted the counter process stops and the counters hold their value. - 0 - 1 - read-write - - - - - CPU_PORT_MONITOR_RESET - No description available - 0x18008 - 32 - 0x00000000 - 0x00000007 - - - RSRX - Write '1' to reset all RX counters. - 2 - 1 - write-only - - - RSTX - Write '1' to reset all TX counters - 1 - 1 - write-only - - - RSALL - Write '1' to reset all TX&RX counters. - 0 - 1 - write-only - - - - - CPU_PORT_MONITOR_PARAM - No description available - 0x1800c - 32 - 0x00000000 - 0xFFFFFF7F - - - RX_CNT_EN_VEC - Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - 16 - 16 - read-only - - - TX_CNT_EN_VEC - Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - 8 - 8 - read-only - - - CNTW - Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter -are available. - 0 - 7 - read-only - - - - - CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD - No description available - 0x18010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_FGOOD - Good transmitted Frames to TX TSN-EP. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR - No description available - 0x18018 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_FERROR - Transmitted Frames with Error to TX TSN-EP. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL - No description available - 0x18020 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_DROP_OVFL - Dropped frames by full queue of TSN-EP. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD - No description available - 0x18040 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FGOOD - Good received frame by ingress buffer. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR - No description available - 0x18048 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FERROR - Bad received frame by ingress buffer. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN - No description available - 0x18050 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_KNOWN - Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN - No description available - 0x18058 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_UNKNOWN - Number of frames passed ingress without hit by MAC table. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_UC - No description available - 0x18060 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_UC - Number of unicast frames - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN - No description available - 0x18068 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_INTERN - Number of non-relay frames - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_BC - No description available - 0x18070 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_BC - Number of Broadcast frames - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI - No description available - 0x18078 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_MULTI - Number of Multicast frames - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN - No description available - 0x18080 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_VLAN - Number of VLAN tagged frames - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL - No description available - 0x18088 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_OVFL - Dropped frames by ingress overflow. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU - No description available - 0x18090 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_LU - Dropped frames by LookUp decision. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR - No description available - 0x18098 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_ERR - Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN - No description available - 0x180a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_VLAN - Dropped frames by incompatible VLAN. - 0 - 32 - read-only - - - - - CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD - No description available - 0x180a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FPE_FGOOD - Number of preemptable frames. Subset of RX_FGOOD - 0 - 32 - read-only - - - - - 3 - 0x20000 - port1,port2,port3 - TSNPORT[%s] - no description available - 0x20000 - - 2 - 0x200 - em1,pm1 - MAC[%s] - no description available - 0x0 - - MAC_VER - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - VER_H - Major version number (higher part of the version) - 16 - 16 - read-only - - - VER_L - Minor version number (lower part of the version) - 0 - 16 - read-only - - - - - MAC_MACADDR_L - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MACADDR - MAC address -Lower bits of MAC address (31:0). -MACADDR only be modified if TX_EN=0 and RX_EN=0. - 0 - 32 - read-write - - - - - MAC_MACADDR_H - No description available - 0x8 - 32 - 0x00000000 - 0x0001FFFF - - - PROMISC - 0 – disabled -1 – enabled -If promiscuous mode is enabled, then reception of all frames independent from the -Ethernet destination address is enabled. -PROMISC can be changed at any time. - 16 - 1 - read-write - - - MACADDR - MAC address (see Chapter 4.1) -Upper bits of MAC address (47:32). -MACADDR can only be modified if TX_EN=0 and RX_EN=0. - 0 - 16 - read-write - - - - - MAC_MAC_CTRL - No description available - 0xc - 32 - 0x00191930 - 0x1F193F7F - - - FSTIM - Fault Stimulation -See Chapter 11.3, Table 11-1 for details. -FSTIM is write-locked if CSA=1. - 24 - 5 - read-write - - - RCA - <ref_clk> active -0 – not active -1 – active -See chapter 11.2.3 for details. - 20 - 1 - read-only - - - MCA - <mii_clk> active -0 – not active -1 – active -See chapter 11.2.3 for details. - 19 - 1 - read-only - - - SEN - Safety Enable -0 – disabled -1 – enabled -If enabled, then two instances of the logic core of LLEMAC-1G are compared at -runtime to each other. -SEN can only be changed if RX_EN and TX_EN can be read as 0. Deactivation delays -of RX_EN and TX_EN have to be considered. It is possible to change SEN together -with the activation of RX_EN and TX_EN. - 16 - 1 - read-write - - - CSA - Clock switching active (<tx_clk>) -0 – not active -1 – active -Switching of <tx_clk> is commanded if CLKSEL or FSTIM (see Table 11-1) are -written. Clock switching takes a few clock cycles and this is signaled with CSA=1. -When CSA=1 then CLKSEL and FSTIM are write-locked and cannot be changed. - 13 - 1 - read-only - - - RCE - <ref_clk> enable -0 – disabled -1 – enabled -RCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details. - 12 - 1 - read-write - - - MCE - <mii_clk> enable -0 – disabled -1 – enabled -MCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details. - 11 - 1 - read-write - - - CLKSEL - TX path clock selector -000 – <mii_clk> -001 – <ref_clk> (recommended setting for this selection) -010 – <ref_clk> divided by 5 -011 – <ref_clk> divided by 10 -100 – <ref_clk> divided by 50 -111 – <ref_clk> and enables modification of RCE and MCE -others – <ref_clk> -See Chapter 7 for further details. -CLKSEL is write-locked if CSA=1. - 8 - 3 - read-write - - - PHYSEL - Selection of the PHY (See Chapter 4.6.) -00 – MII -01 – GMII -10 – RGMII -11 – reserved -PHYSEL can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of -RX_EN and TX_EN have to be considered. PHYSEL can only be changed, if these -register bits can be read as 0. It is possible to change PHYSEL together with the -activation of RX_EN and TX_EN. -PHYSEL drives the output <rx_physel>. - 5 - 2 - read-write - - - GMIIMODE - GMII mode / Ethernet speed selection (See Chapter 4.5.) -0 – MII: 10Mbit/s or 100Mbit/s -1 – GMII: 1GBit/s -GMIIMODE can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of -RX_EN and TX_EN have to be considered. GMIIMODE can only be changed, if these -register bits can be read as 0. It is possible to change GMIIMODE together with the -activation of RX_EN and TX_EN. -GMIIMODE drives the outputs <tx_gmiimode> and <rx_gmiimode>. - 4 - 1 - read-write - - - JUMBO - Jumbo frame support -0 – jumbo frames not supported -1 – jumbo frame supported (not recommended) -Jumbo frames are non-standard Ethernet frames with a size bigger than envelope -frames (which contain 1982 payload bytes). If jumbo frames are not supported, then -LLEMAC-1G generates the appropriate error signals (<tx_gmii_er> for the TX path -and <rx_avst_err> for the RX path). -Although jumbo frames typically contain up to 9000 bytes, the LLEMAC-1G can handle -an infinite frame size. The problem of jumbo frames is the necessary storage space in -transmission and reception buffers. LLEMAC-1G does not include storage buffers. -JUMBO can be activated or deactivated at any time. The new setting becomes valid -immediately after clock domain crossing. - 3 - 1 - read-write - - - TX_EN - TX path enable -0 – transmission disabled - Avalon-ST READY for the TX path will be set to 0. -1 – transmission enabled -TX_EN can be activated or deactivated at any time. Deactivation may take some time. -If during deactivation there is a frame in transmission, then this frame will be -completed fist. Afterwards bit TX_EN can be read as 0. -After the transmission is disabled there may be pending frames left, waiting at the TX -stream interface. - 2 - 1 - read-write - - - RX_EN - RX path enable -0 – reception disabled – no frames fed to Avalon-ST RX path -1 – reception enabled -RX_EN can be activated or deactivated at any time. Deactivation may take some time. -If during deactivation there is a frame in reception, then this frame will be completed -first. Afterwards bit RX_EN can be read as 0. - 1 - 1 - read-write - - - RESSTAT - Software reset of the statistic counters (see Table 3-8) -0 – no reset -1 – reset active -RESSTAT will be automatically set to 0 after the counters have been reset - 0 - 1 - read-write - - - - - MAC_TX_FRAMES - No description available - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_FRAMES - Number of successfully transmitted frames. - 0 - 32 - read-only - - - - - MAC_RX_FRAMES - No description available - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FRAMES - Number of successfully received frames. - 0 - 32 - read-only - - - - - MAC_TX_OCTETS - No description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_OCTETS - Number of successfully transmitted payload and padding octets. - 0 - 32 - read-only - - - - - MAC_RX_OCTETS - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_OCTETS - Number of successfully received payload and padding octets. - 0 - 32 - read-only - - - - - MAC_MDIO_CFG - No description available - 0x20 - 32 - 0x00000000 - 0x000081FF - - - NPRE - No Preamble -With NPRE=1 the preamble generation is suppressed and frames are initiated with -Start of Frame pattern directly. Suitable in case that all connected PHYs accept -management frames without a preamble pattern. Recommended to be used if only -one PHY is connected. - 15 - 1 - read-write - - - ENABLE - Enable the MDIO controller. If the controller is enabled then MDC will be toggled. -ENABLE can only be read as 1 if a valid MDC_CLKDIV value is set. - 8 - 1 - read-write - - - MDC_CLKDIV - Clock Divider to configure MDC clock frequency. Refer to 10.1 Clock Divider for more -details. - 0 - 8 - read-write - - - - - MAC_MDIO_CTRL - No description available - 0x24 - 32 - 0x00000000 - 0xDF1F0101 - - - OP - Opcode to determine transfer type -01 – Write Access -10 – Read Access - 30 - 2 - read-write - - - PHYAD - Management Frame PHY Address. - 24 - 5 - read-write - - - REGAD - Management Frame Register Address. - 16 - 5 - read-write - - - INIT - INIT=1 results in a MDIO write/read transfer if READY=1. If READY=0 while a -transfer is already pending or if ENABLE=0 then settings INIT=1 has no effect and -the current transaction is withdrawn. - 8 - 1 - read-write - - - READY - READY=1 indicates a finished transfer and also shows that the controller is ready for a -new transfer. READY=1 is only possible if ENABLE=1. -If READY=1 is signaled after a read transfer, then RD_DATA is valid until a new -transfer is started. - 0 - 1 - read-only - - - - - MAC_MDIO_RD_DATA - No description available - 0x28 - 32 - 0x00000000 - 0x0000FFFF - - - RD_DATA - Read Data is available if READY=1 after a transfer has been started. RD_DATA represents the content of the management data field of the read transfer. - 0 - 16 - read-only - - - - - MAC_MDIO_WR_DATA - No description available - 0x2c - 32 - 0x00000000 - 0x0000FFFF - - - WR_DATA - Data is used for the management data field after a write transfer has been started - 0 - 16 - read-write - - - - - MAC_IRQ_CTRL - No description available - 0x30 - 32 - 0x0000000C - 0x00000F0D - - - CAIF - Clock activity interrupt flag -0 – no interrupt -1 – interrupt pending -See Chapter 11.2.3 for details. - 11 - 1 - read-write - - - SWIF - Safety warning interrupt flag -0 – no interrupt -1 – interrupt pending -See Chapter 11.2.2 for details - 10 - 1 - read-write - - - SEIF - Safety Error Interrupt Flag -0 – no interrupt -1 – interrupt pending -If SEN=1 and if there is a mismatch between both instances of the logic core of -LLEMAC-1G then this results in SEIF=1, TX_EN=0 and RX_EN=0. - 9 - 1 - read-write - - - MDIF - MDIO Interrupt Flag -1 – A transfer has been finished -0 – No transfer done - 8 - 1 - read-write - - - CAIE - Clock activity interrupt enable -0 – CAIF disabled -1 – CAIF enabled - 3 - 1 - read-write - - - SWIE - Safety warning interrupt enable -0 – SWIF disabled -1 – SWIF enabled - 2 - 1 - read-write - - - MDIE - MDIO Interrupt Enable -0 – Disabled -1 – Enabled - 0 - 1 - read-write - - - - - - RTC_CR - ONLY IN PORT1 - 0x800 - 32 - 0x00000000 - 0x0000000E - - - TAIE - Timer A interrupt enable: interrupt enabled when 1 - 3 - 1 - read-write - - - TAEN - Timer A enable: timer enabled when 1 - 2 - 1 - read-write - - - ALIE - Alarm interrupt enable: alarm interrupt enabled when 1 - 1 - 1 - read-write - - - - - RTC_SR - ONLY IN PORT1 - 0x804 - 32 - 0x00000000 - 0x0000000A - - - TAIS - Timer A Interrupt Status: set at rising edge of “timer_clk_a”, write 1 to clear - 3 - 1 - read-write - - - ALIS - ALIS ro Alarm Interrupt Status: Always set while RTC-Time >= Alarm-Time - 1 - 1 - read-only - - - - - RTC_CT_CURTIME_NS - ONLY IN PORT1 - 0x810 - 32 - 0x00000000 - 0x3FFFFFFF - - - CT_NS - Local Time (nanosecond part): Update can be triggered by write access to this register. Value range from 0 – 999999999. - 0 - 30 - read-write - - - - - RTC_CT_CURTIME_SEC - ONLY IN PORT1 - 0x814 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT_SEC - Current Time (second part): Update can be triggered by write access to register CURTIME_NS. - 0 - 32 - read-only - - - - - RTC_CT_TIMER_INCR - ONLY IN PORT1 - 0x81c - 32 - 0x00000000 - 0xFFFFFFFF - - - NS - Local time increment – nanoseconds (integer) - 24 - 8 - read-write - - - FNS - Local time increment – fractional ns, unsigned, in (1 / 2^24) n - 0 - 24 - read-write - - - - - RTC_OFS_NS - ONLY IN PORT1 - 0x820 - 32 - 0x00000000 - 0x3FFFFFFF - - - OFS_NS - Real Time Offset (nanoseconds part). Valid value range from 0 – 999999999. - 0 - 30 - read-write - - - - - RTC_OFS_SL - ONLY IN PORT1 - 0x824 - 32 - 0x00000000 - 0xFFFFFFFF - - - OFS_SL - 48 Bit Real Time Offset (seconds lo part) - 0 - 32 - read-write - - - - - RTC_OFS_SH - ONLY IN PORT1 - 0x828 - 32 - 0x00000000 - 0x0000FFFF - - - OFS_SH - 48 Bit Real Time Offset (seconds hi part) - 0 - 16 - read-write - - - - - RTC_OFS_CH - ONLY IN PORT1 - 0x82c - 32 - 0x00000000 - 0xFFFFFFFF - - - SEXT - Real Time Offset Change – sign extension of SFNS (Bit 23) - 24 - 8 - read-only - - - SFNS - Real Time Offset Change in fractional nanoseconds, signed value; value range from -2^23 / 2^24 to (2^23-1) / 2^24 nanoseconds. - 0 - 24 - read-write - - - - - RTC_ALARM_NS - ONLY IN PORT1 - 0x830 - 32 - 0x00000000 - 0x3FFFFFFF - - - AL_NS - Alarm Time (nanoseconds part). Valid value range from 0 – 999999999. - 0 - 30 - read-write - - - - - RTC_ALARM_SL - ONLY IN PORT1 - 0x834 - 32 - 0x00000000 - 0xFFFFFFFF - - - AL_SL - Alarm Time (seconds lo part) - 0 - 32 - read-write - - - - - RTC_ALARM_SH - ONLY IN PORT1 - 0x838 - 32 - 0x00000000 - 0x0000FFFF - - - AL_SH - Alarm Time (seconds hi part) - 0 - 16 - read-write - - - - - RTC_TIMER_A_PERIOD - ONLY IN PORT1 - 0x840 - 32 - 0x00000000 - 0x1FFFFFFF - - - PERIOD_NS - Timer A Period in ns. This is the period of the timer until the next event, but the half-period of the signal “timer_a_clk”. - 0 - 29 - read-write - - - - - TSYN_CR - No description available - 0x1004 - 32 - 0x00000000 - 0x001F1F07 - - - TMR_ALD - Timer Auto Load: automatic reloading of timer when reaching 0. Done flag stays set after countdown. Used for periodic events, when following event shall not be delayed by host interaction. - 16 - 5 - read-write - - - TMR_EN - Timer Enable: every bit corresponds to Timer 0 – 4 - 8 - 5 - read-write - - - TMRIE - Timer Interrupt Enable - 2 - 1 - read-write - - - RXIE - Rx Interrupt Enable - 1 - 1 - read-write - - - TXIE - Tx Interrupt Enable - 0 - 1 - read-write - - - - - TSYN_SR - No description available - 0x1008 - 32 - 0x00000000 - 0x00001F07 - - - TMR_DN - Timer Done: 1 when timer reached 0 - 8 - 5 - read-write - - - TMRIS - Timer Interrupt Status: OR’ed (TMR_DN AND TMR_EN) flags. 1 when timer is enabled and countdown is done - 2 - 1 - read-only - - - RXIS - Rx Interrupt Status, RX buffer data available equal to PTP_RX_STS.AV) - 1 - 1 - read-only - - - TXIS - Tx Done Interrupt Status: OR’ed PTP_TX_DONE - 0 - 1 - read-only - - - - - TSYN_PTP_TX_STS - No description available - 0x1010 - 32 - 0x00000000 - 0x000000FF - - - STS - Transmission status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission pending - 0 - 8 - read-only - - - - - TSYN_PTP_TX_DONE - No description available - 0x1014 - 32 - 0x00000000 - 0x000000FF - - - DONE - Transmission done status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission done. -Writing a ‘1’ clears corresponding bit.. - 0 - 8 - read-write - - - - - TSYN_PTP_TX_TRIG - No description available - 0x1018 - 32 - 0x00000000 - 0x000000FF - - - TRIG - Trigger PTP TX bin n (bit 0 – 7 correspond to tx bin 0 –7). Writing ‘1’ will trigger transmission. Corresponding bit PTP_TX_STS.STS(n) will be set immediately. - 0 - 8 - write-only - - - - - TSYN_PTP_RX_STS - No description available - 0x101c - 32 - 0x00000000 - 0xC0000007 - - - OV - FIFO overflow flag. PTP frame has been received and there was no free buffer available. Data has been lost. - 31 - 1 - read-write - - - AV_NXT - Read access: buffer data available – reading data from RX_BUF is valid. -Write access: switch to next RX buffer – shall only be done when buffer not empty (AV=1). Use field RX_SEL as indication when rx buffer switch has been done. - 30 - 1 - read-write - - - RX_SEL - Current selected RX buffer for reading (0-7). Can be used to determine when RX buffer has been switched after setting PTP_RX_STS.NXT - 0 - 3 - read-only - - - - - 5 - 0x4 - TSYN_TMR0,TSYN_TMR1,TSYN_TMR2,TSYN_TMR3,TSYN_TMR4 - TSYNTMR[%s] - no description available - 0x1020 - 32 - 0x00000000 - 0x000FFFFF - - - PERIOD - Period in ticks, ticks based on register HCLKDIV and host clock <sys_clk>. - 0 - 20 - read-write - - - - - TSYN_HCLKDIV - No description available - 0x103c - 32 - 0x00000000 - 0x000FFFFF - - - PERIOD - Period in host clocks <sys_clk>. Host clock shall be scaled to ticks of 1/1024th second. Ticks are used by timer TMR0 – TMR4. - 0 - 20 - read-write - - - - - TSYN_RXBUF_RX_FRAME_LENGTH_BYTES - No description available - 0x1600 - 32 - 0x00000000 - 0x00000FFF - - - RX_FRAME_LENGTH_BYTES - RX frame length bytes [11:0] - 0 - 12 - read-only - - - - - TSYN_RXBUF_RX_TIME_STAMP_L - No description available - 0x1608 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_TIMESTAMP_LOW - RX Timestamp [31:0] - 0 - 32 - read-only - - - - - TSYN_RXBUF_RX_TIME_STAMP_H - No description available - 0x160c - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_TIMESTAMP_HIGH - RX Timestamp [63:32] - 0 - 32 - read-only - - - - - 60 - 0x4 - TSYN_RXBUF_DATA_WORD0,TSYN_RXBUF_DATA_WORD1,TSYN_RXBUF_DATA_WORD2,TSYN_RXBUF_DATA_WORD3,TSYN_RXBUF_DATA_WORD4,TSYN_RXBUF_DATA_WORD5,TSYN_RXBUF_DATA_WORD6,TSYN_RXBUF_DATA_WORD7,TSYN_RXBUF_DATA_WORD8,TSYN_RXBUF_DATA_WORD9,TSYN_RXBUF_DATA_WORD10,TSYN_RXBUF_DATA_WORD11,TSYN_RXBUF_DATA_WORD12,TSYN_RXBUF_DATA_WORD13,TSYN_RXBUF_DATA_WORD14,TSYN_RXBUF_DATA_WORD15,TSYN_RXBUF_DATA_WORD16,TSYN_RXBUF_DATA_WORD17,TSYN_RXBUF_DATA_WORD18,TSYN_RXBUF_DATA_WORD19,TSYN_RXBUF_DATA_WORD20,TSYN_RXBUF_DATA_WORD21,TSYN_RXBUF_DATA_WORD22,TSYN_RXBUF_DATA_WORD23,TSYN_RXBUF_DATA_WORD24,TSYN_RXBUF_DATA_WORD25,TSYN_RXBUF_DATA_WORD26,TSYN_RXBUF_DATA_WORD27,TSYN_RXBUF_DATA_WORD28,TSYN_RXBUF_DATA_WORD29,TSYN_RXBUF_DATA_WORD30,TSYN_RXBUF_DATA_WORD31,TSYN_RXBUF_DATA_WORD32,TSYN_RXBUF_DATA_WORD33,TSYN_RXBUF_DATA_WORD34,TSYN_RXBUF_DATA_WORD35,TSYN_RXBUF_DATA_WORD36,TSYN_RXBUF_DATA_WORD37,TSYN_RXBUF_DATA_WORD38,TSYN_RXBUF_DATA_WORD39,TSYN_RXBUF_DATA_WORD40,TSYN_RXBUF_DATA_WORD41,TSYN_RXBUF_DATA_WORD42,TSYN_RXBUF_DATA_WORD43,TSYN_RXBUF_DATA_WORD44,TSYN_RXBUF_DATA_WORD45,TSYN_RXBUF_DATA_WORD46,TSYN_RXBUF_DATA_WORD47,TSYN_RXBUF_DATA_WORD48,TSYN_RXBUF_DATA_WORD49,TSYN_RXBUF_DATA_WORD50,TSYN_RXBUF_DATA_WORD51,TSYN_RXBUF_DATA_WORD52,TSYN_RXBUF_DATA_WORD53,TSYN_RXBUF_DATA_WORD54,TSYN_RXBUF_DATA_WORD55,TSYN_RXBUF_DATA_WORD56,TSYN_RXBUF_DATA_WORD57,TSYN_RXBUF_DATA_WORD58,TSYN_RXBUF_DATA_WORD59 - RXDATA[%s] - no description available - 0x1610 - 32 - 0x00000000 - 0xFFFFFFFF - - - RXBUF_DATA_WORD - RXBUF_DATA_WORD - 0 - 32 - read-only - - - - - 8 - 0x100 - tx0,tx1,tx2,tx3,tx4,tx5,tx6,tx7 - BIN[%s] - no description available - 0x1800 - - 60 - 0x4 - TSYN_TXBUF_BIN0_DATA_WORD0,TSYN_TXBUF_BIN0_DATA_WORD1,TSYN_TXBUF_BIN0_DATA_WORD2,TSYN_TXBUF_BIN0_DATA_WORD3,TSYN_TXBUF_BIN0_DATA_WORD4,TSYN_TXBUF_BIN0_DATA_WORD5,TSYN_TXBUF_BIN0_DATA_WORD6,TSYN_TXBUF_BIN0_DATA_WORD7,TSYN_TXBUF_BIN0_DATA_WORD8,TSYN_TXBUF_BIN0_DATA_WORD9,TSYN_TXBUF_BIN0_DATA_WORD10,TSYN_TXBUF_BIN0_DATA_WORD11,TSYN_TXBUF_BIN0_DATA_WORD12,TSYN_TXBUF_BIN0_DATA_WORD13,TSYN_TXBUF_BIN0_DATA_WORD14,TSYN_TXBUF_BIN0_DATA_WORD15,TSYN_TXBUF_BIN0_DATA_WORD16,TSYN_TXBUF_BIN0_DATA_WORD17,TSYN_TXBUF_BIN0_DATA_WORD18,TSYN_TXBUF_BIN0_DATA_WORD19,TSYN_TXBUF_BIN0_DATA_WORD20,TSYN_TXBUF_BIN0_DATA_WORD21,TSYN_TXBUF_BIN0_DATA_WORD22,TSYN_TXBUF_BIN0_DATA_WORD23,TSYN_TXBUF_BIN0_DATA_WORD24,TSYN_TXBUF_BIN0_DATA_WORD25,TSYN_TXBUF_BIN0_DATA_WORD26,TSYN_TXBUF_BIN0_DATA_WORD27,TSYN_TXBUF_BIN0_DATA_WORD28,TSYN_TXBUF_BIN0_DATA_WORD29,TSYN_TXBUF_BIN0_DATA_WORD30,TSYN_TXBUF_BIN0_DATA_WORD31,TSYN_TXBUF_BIN0_DATA_WORD32,TSYN_TXBUF_BIN0_DATA_WORD33,TSYN_TXBUF_BIN0_DATA_WORD34,TSYN_TXBUF_BIN0_DATA_WORD35,TSYN_TXBUF_BIN0_DATA_WORD36,TSYN_TXBUF_BIN0_DATA_WORD37,TSYN_TXBUF_BIN0_DATA_WORD38,TSYN_TXBUF_BIN0_DATA_WORD39,TSYN_TXBUF_BIN0_DATA_WORD40,TSYN_TXBUF_BIN0_DATA_WORD41,TSYN_TXBUF_BIN0_DATA_WORD42,TSYN_TXBUF_BIN0_DATA_WORD43,TSYN_TXBUF_BIN0_DATA_WORD44,TSYN_TXBUF_BIN0_DATA_WORD45,TSYN_TXBUF_BIN0_DATA_WORD46,TSYN_TXBUF_BIN0_DATA_WORD47,TSYN_TXBUF_BIN0_DATA_WORD48,TSYN_TXBUF_BIN0_DATA_WORD49,TSYN_TXBUF_BIN0_DATA_WORD50,TSYN_TXBUF_BIN0_DATA_WORD51,TSYN_TXBUF_BIN0_DATA_WORD52,TSYN_TXBUF_BIN0_DATA_WORD53,TSYN_TXBUF_BIN0_DATA_WORD54,TSYN_TXBUF_BIN0_DATA_WORD55,TSYN_TXBUF_BIN0_DATA_WORD56,TSYN_TXBUF_BIN0_DATA_WORD57,TSYN_TXBUF_BIN0_DATA_WORD58,TSYN_TXBUF_BIN0_DATA_WORD59 - TXDATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBUF_BIN0_DATA_WORD0 - TXBUF_BIN0_DATA_WORD0 - 0 - 32 - read-write - - - - - TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN - No description available - 0xf0 - 32 - 0x00000000 - 0x070000FF - - - TXBUF_BIN0_TQUE - TXBUF_BIN0_TQUE - 24 - 3 - read-write - - - TXBUF_BIN0_TX_LEN - TXBUF_BIN0_TX_LEN - 0 - 8 - read-write - - - - - TSYN_TXBUF_BIN0_TX_TIMESTAMP_L - No description available - 0xf8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBUF_BIN0_TX_TIMESTAMP_L - TXBUF_BIN0_TX_TIMESTAMP_L - 0 - 32 - read-write - - - - - TSYN_TXBUF_BIN0_TX_TIMESTAMP_H - No description available - 0xfc - 32 - 0x00000000 - 0xFFFFFFFF - - - TXBUF_BIN0_TX_TIMESTAMP_H - TXBUF_BIN0TX_TIMESTAMP_H - 0 - 32 - read-write - - - - - - TSN_SHAPER_HWCFG1 - No description available - 0x2004 - 32 - 0x00000000 - 0xFFFFFFFF - - - LWIDTH - Scheduler list address width (IP core parameter LWIDTH) - 24 - 8 - read-only - - - TQC - Traffic queue count (IP core parameter TQC) - 16 - 8 - read-only - - - TQD - Traffic queue depth (IP core parameter TQD) - 8 - 8 - read-only - - - DW - Traffic queue data width (Bytes); fixed to value 4 within -IP core - 0 - 8 - read-only - - - - - TSN_SHAPER_TQAV - No description available - 0x200c - 32 - 0x00000000 - 0x0000FFFF - - - AVIE - Traffic queue interrupt enable on buffer space available, -one bit per traffic queue -Bit[i] = 0: no interrupt -Bit[i] = 1: interrupt, when AVAIL[i]=1 - 8 - 8 - read-write - - - AVAIL - Traffic queue buffer space available for complete packet of size MaxSDU (register MXSDUi) -Bit[i] = 1: space available -Bit[i] = 0: no space available or TQ not implemented (I >= TQC) - 0 - 8 - read-only - - - - - TSN_SHAPER_TQEM - No description available - 0x2010 - 32 - 0x00000000 - 0x000000FF - - - EMPTY - Traffic queue empty -Bit[i] = 1: traffic queue i is empty - 0 - 8 - read-only - - - - - TSN_SHAPER_FPST - No description available - 0x2014 - 32 - 0x00000000 - 0x000000FF - - - TABLE - Frame Preemption Status Table, -Bit[i] = 1: Preemptable traffic in TQ[i], otherwise -Express traffic (default) - 0 - 8 - read-write - - - - - TSN_SHAPER_MMCT - No description available - 0x2018 - 32 - 0x00000000 - 0x00000003 - - - RQREL - Request HOLD-Signal release operation. Will be automatically set to <0> - 1 - 1 - read-write - - - RQHLD - Request HOLD-Signal hold operation. Will be automatically set to <0>. - 0 - 1 - read-write - - - - - TSN_SHAPER_HOLDADV - No description available - 0x201c - 32 - 0x00000000 - 0x0000FFFF - - - VALUE - holdAdvance time for TAS operation Set-And-Hold-MAC in <sys_clk> cycles - 0 - 16 - read-write - - - - - 8 - 0x4 - TSN_SHAPER_MXSDU0,TSN_SHAPER_MXSDU1,TSN_SHAPER_MXSDU2,TSN_SHAPER_MXSDU3,TSN_SHAPER_MXSDU4,TSN_SHAPER_MXSDU5,TSN_SHAPER_MXSDU6,TSN_SHAPER_MXSDU7 - MXSDU[%s] - no description available - 0x2100 - 32 - 0x00000000 - 0x0000FFFF - - - SDU - Maximum SDU size for traffic queue n (n = 0 – 7)Returns 0 when n > TQC. Value is size in words (32 bit word size). - 0 - 16 - read-write - - - - - 8 - 0x4 - TSN_SHAPER_TXSEL0,TSN_SHAPER_TXSEL1,TSN_SHAPER_TXSEL2,TSN_SHAPER_TXSEL3,TSN_SHAPER_TXSEL4,TSN_SHAPER_TXSEL5,TSN_SHAPER_TXSEL6,TSN_SHAPER_TXSEL7 - TXSEL[%s] - no description available - 0x2120 - 32 - 0x00000000 - 0x0000FFFF - - - CBS_EN - CBS enable traffic queue n (n = 0 – 7). Returns 0 when n > TQC. Must be 0 when changing register IDSLPi. - 0 - 16 - read-write - - - - - 8 - 0x4 - TSN_SHAPER_IDSEL0,TSN_SHAPER_IDSEL1,TSN_SHAPER_IDSEL2,TSN_SHAPER_IDSEL3,TSN_SHAPER_IDSEL04,TSN_SHAPER_IDSEL5,TSN_SHAPER_IDSEL6,TSN_SHAPER_IDSEL7 - IDSEL[%s] - no description available - 0x2140 - 32 - 0x00000000 - 0x000FFFFF - - - INT - CBS idle slope for traffic queue n (n = 0 – 7). Returns -0 when n > TQC. The register must only be written -when TXSELi.CBE_EN=0. -The idle slope value is defined as (INT + FRACT / -65536). The idle slope is set in bits per tick related to -<tx_clk>. - 16 - 4 - read-write - - - FRACT - No description available - 0 - 16 - read-write - - - - - PORT1_QCH0_CFG - qch channel0 control - 0x2800 - 32 - 0x00000000 - 0x00177FF1 - - - CQF_IN_ERR - qch queue in error - 20 - 1 - write-only - - - CQF_NUM - qch queue destination buffer select - 16 - 3 - read-write - - - TAS_GPIO_SEL - tas_gpio select - 12 - 3 - read-write - - - AXIS_QCH_EN - qch queue in select - 4 - 8 - read-write - - - CQF_EN - qch enable - 0 - 1 - read-write - - - - - PORT1_QCH1_CFG - qch channel1 control - 0x2804 - 32 - 0x00000000 - 0x00177FF1 - - - CQF_IN_ERR - qch queue in error - 20 - 1 - write-only - - - CQF_NUM - qch queue destination buffer select - 16 - 3 - read-write - - - TAS_GPIO_SEL - tas_gpio select - 12 - 3 - read-write - - - AXIS_QCH_EN - qch queue in select - 4 - 8 - read-write - - - CQF_EN - qch enable - 0 - 1 - read-write - - - - - PORT1_QCH2_CFG - qch channel2 control - 0x2808 - 32 - 0x00000000 - 0x00177FF1 - - - CQF_IN_ERR - qch queue in error - 20 - 1 - write-only - - - CQF_NUM - qch queue destination buffer select - 16 - 3 - read-write - - - TAS_GPIO_SEL - tas_gpio select - 12 - 3 - read-write - - - AXIS_QCH_EN - qch queue in select - 4 - 8 - read-write - - - CQF_EN - qch enable - 0 - 1 - read-write - - - - - PORT1_QCH3_CFG - qch channel3 control - 0x280c - 32 - 0x00000000 - 0x00177FF1 - - - CQF_IN_ERR - qch queue in error - 20 - 1 - write-only - - - CQF_NUM - qch queue destination buffer select - 16 - 3 - read-write - - - TAS_GPIO_SEL - tas_gpio select - 12 - 3 - read-write - - - AXIS_QCH_EN - qch queue in select - 4 - 8 - read-write - - - CQF_EN - qch enable - 0 - 1 - read-write - - - - - PORT1_QCH_ERR_CFG - qch clear - 0x2810 - 32 - 0x00000000 - 0x0000FF07 - - - CQF_QUE_ERR - que gate error for each cqf - 8 - 8 - write-only - - - CQF_NUM_CFG_ERR - cqf_num config error - 2 - 1 - read-only - - - AXIS_QCH_CFG_ERR - axis_qch_en config error - 1 - 1 - read-only - - - CQF_CLR_CTRL - enable cqf buffer auto clear when error - 0 - 1 - read-write - - - - - TSN_SHAPER_TAS_CRSR - No description available - 0x3000 - 32 - 0x00000000 - 0xFFFFFF0F - - - ADMINGS - Admin gate states, fixed 0xFF. Gate states when TAS is disabled. - 24 - 8 - read-only - - - OPERGS - Operational gate states of TQ[i] (i = 0 – TQC-1) -Bit[i]=0 – Gate is closed; no start of frame TX possible -Bit[i]=1 – Gate is open - 16 - 8 - read-only - - - TAS_GPIO_STA - operational tas gpio gate status of TQ[i] - 8 - 8 - read-only - - - CFGPEND - Configuration change is pending – Admin basetime not yet reached. - 3 - 1 - read-only - - - CFGERR - Configuration error. - 2 - 1 - read-write - - - CFGCHG - Switch configuration; Bit is automatically reset to 0; -Setting Bit=1 triggers configuration change event. - 1 - 1 - read-write - - - EN - Enable time aware scheduling. - 0 - 1 - read-write - - - - - TSN_SHAPER_TAS_ACYCLETM - No description available - 0x3004 - 32 - 0x00000000 - 0x3FFFFFFF - - - CTIME - Admin cycletime in nanoseconds. - 0 - 30 - read-write - - - - - TSN_SHAPER_TAS_ABASETM_L - No description available - 0x3008 - 32 - 0x00000000 - 0x3FFFFFFF - - - BASETM_L - Admin basetime – nanoseconds and seconds part. - 0 - 30 - read-write - - - - - TSN_SHAPER_TAS_ABASETM_H - No description available - 0x300c - 32 - 0x00000000 - 0xFFFFFFFF - - - BASETM_H - No description available - 0 - 32 - read-write - - - - - TSN_SHAPER_TAS_LISTLEN - No description available - 0x3010 - 32 - 0x00000000 - 0x00FF00FF - - - OLISTLEN - Oper list length. - 16 - 8 - read-only - - - ALISTLEN - Admin list length. - 0 - 8 - read-write - - - - - TSN_SHAPER_TAS_OCYCLETM - No description available - 0x3014 - 32 - 0x00000000 - 0x3FFFFFFF - - - CTIME - Operational cycletime in nanoseconds - 0 - 30 - read-only - - - - - TSN_SHAPER_TAS_OBASETM_L - No description available - 0x3018 - 32 - 0x00000000 - 0xFFFFFFFF - - - BASETM_L - Operational basetime – nanoseconds and seconds part. The operational basetime might occasionally have a non-normalized value (ns >= 10^9) for one clock cycle. - 0 - 32 - read-only - - - - - TSN_SHAPER_TAS_OBASETM_H - No description available - 0x301c - 32 - 0x00000000 - 0xFFFFFFFF - - - BASETM_H - No description available - 0 - 32 - read-only - - - - - 8 - 0x4 - TSN_SHAPER_MXTK0,TSN_SHAPER_MXTK1,TSN_SHAPER_MXTK2,TSN_SHAPER_MXTK3,TSN_SHAPER_MXTK4,TSN_SHAPER_MXTK5,TSN_SHAPER_MXTK6,TSN_SHAPER_MXTK7 - MXTK[%s] - no description available - 0x3020 - 32 - 0x00000000 - 0x00FFFFFF - - - TICK - Maximum SDU size in clock ticks. MXTKi is only supported when TQC > i, otherwise read-only with value 0 - 0 - 24 - read-write - - - - - 8 - 0x4 - TSN_SHAPER_TXOV0,TSN_SHAPER_TXOV1,TSN_SHAPER_TXOV2,TSN_SHAPER_TXOV3,TSN_SHAPER_TXOV4,TSN_SHAPER_TXOV5,TSN_SHAPER_TXOV6,TSN_SHAPER_TXOV7 - TXOV[%s] - no description available - 0x3040 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - Transmission overrun counter; increments on transmission when gate is closed; any write access will clear register to 0. TXOVi is only supported when TQC > i. - 0 - 32 - read-write - - - - - 256 - 0x8 - ent0,ent1,ent2,ent3,ent4,ent5,ent6,ent7,ent8,ent9,ent10,ent11,ent12,ent13,ent14,ent15,ent16,ent17,ent18,ent19,ent20,ent21,ent22,ent23,ent24,ent25,ent26,ent27,ent28,ent29,ent30,ent31,ent32,ent33,ent34,ent35,ent36,ent37,ent38,ent39,ent40,ent41,ent42,ent43,ent44,ent45,ent46,ent47,ent48,ent49,ent50,ent51,ent52,ent53,ent54,ent55,ent56,ent57,ent58,ent59,ent60,ent61,ent62,ent63,ent64,ent65,ent66,ent67,ent68,ent69,ent70,ent71,ent72,ent73,ent74,ent75,ent76,ent77,ent78,ent79,ent80,ent81,ent82,ent83,ent84,ent85,ent86,ent87,ent88,ent89,ent90,ent91,ent92,ent93,ent94,ent95,ent96,ent97,ent98,ent99,ent100,ent101,ent102,ent103,ent104,ent105,ent106,ent107,ent108,ent109,ent110,ent111,ent112,ent113,ent114,ent115,ent116,ent117,ent118,ent119,ent120,ent121,ent122,ent123,ent124,ent125,ent126,ent127,ent128,ent129,ent130,ent131,ent132,ent133,ent134,ent135,ent136,ent137,ent138,ent139,ent140,ent141,ent142,ent143,ent144,ent145,ent146,ent147,ent148,ent149,ent150,ent151,ent152,ent153,ent154,ent155,ent156,ent157,ent158,ent159,ent160,ent161,ent162,ent163,ent164,ent165,ent166,ent167,ent168,ent169,ent170,ent171,ent172,ent173,ent174,ent175,ent176,ent177,ent178,ent179,ent180,ent181,ent182,ent183,ent184,ent185,ent186,ent187,ent188,ent189,ent190,ent191,ent192,ent193,ent194,ent195,ent196,ent197,ent198,ent199,ent200,ent201,ent202,ent203,ent204,ent205,ent206,ent207,ent208,ent209,ent210,ent211,ent212,ent213,ent214,ent215,ent216,ent217,ent218,ent219,ent220,ent221,ent222,ent223,ent224,ent225,ent226,ent227,ent228,ent229,ent230,ent231,ent232,ent233,ent234,ent235,ent236,ent237,ent238,ent239,ent240,ent241,ent242,ent243,ent244,ent245,ent246,ent247,ent248,ent249,ent250,ent251,ent252,ent253,ent254,ent255 - SHACL[%s] - no description available - 0x3800 - - TSN_SHAPER_ACLIST_ENTRY0_L - No description available - 0x0 - 32 - 0x00000000 - 0x0003FFFF - - - TAS_GPIO - gate states for qch and ptp event source - 10 - 8 - read-write - - - OP - gate operation: -0 – SetGateStates -1 – Set-And-Hold-MAC -2 – Set-And-Release-MAC -3 – undefined - 8 - 2 - read-write - - - STATE - gate state vector; -1 – Gate is open - 0 - 8 - read-write - - - - - TSN_SHAPER_ACLIST_ENTRY0_H - No description available - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - Time interval, entry execution in in host clock ticks (<sys_clk>) - 0 - 32 - read-write - - - - - - TSN_EP_VER - No description available - 0xf000 - 32 - 0x00000000 - 0xFFFF00FF - - - VER_HI - major version number - 24 - 8 - read-only - - - VER_LO - minor version number - 16 - 8 - read-only - - - VER_REV - revision number - 0 - 8 - read-only - - - - - TSN_EP_CTRL - No description available - 0xf004 - 32 - 0x00000000 - 0xC0000001 - - - FILTDIS - Disable filtering of PTP frames (Ethertype = 0x88F7) - 31 - 1 - read-write - - - PTP_1S_EN - Enable PTPv2 1-step synchronization suppor - 30 - 1 - read-write - - - IE_TSF - TxTimestampFifo interrupt enable; interrupt will be set when IE_TSF=<1> and TSF_SR.USED>0 - 0 - 1 - read-write - - - - - TSN_EP_TXUF - No description available - 0xf010 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - TX buffer underflow counter; incremented when any MAC runs out of data during transmission. The counter is cleared at any write access. The counter is shared by pMAC and eMAC. If underflow event occurs at the same time for pMAC and eMAC, it will be counted as one event. - 0 - 32 - read-write - - - - - TSN_EP_IPCFG - No description available - 0xf014 - 32 - 0x00000000 - 0xFC000000 - - - INCL_RTC - IP core parameter “INCL_RTC” - 31 - 1 - read-only - - - INCL_SHAP - IP core parameter “INCL_SHAPER” - 30 - 1 - read-only - - - INCL_FPE - IP core parameter “INCL_FPE” - 29 - 1 - read-only - - - INCL_TSF - IP core parameter “INCL_TSF” - 28 - 1 - read-only - - - INCL_TSYNC - IP core parameter “INCL_TSYNC” - 27 - 1 - read-only - - - INCL_1STEP - IP core parameter “INCL_1STEP” - 26 - 1 - read-only - - - - - TSN_EP_TSF_D0 - No description available - 0xf020 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSF_NS - Tx-Timestamp-Fifo, lower 32 bit part of local time (<curtime>) at the start of transmission of the packet. Usually nanoseconds part when used with included RTC. - 0 - 32 - read-only - - - - - TSN_EP_TSF_D1 - No description available - 0xf024 - 32 - 0x00000000 - 0xFFFFFFFF - - - TSF_SEC - Tx-Timestamp-Fifo, upper 32 bit part of the local time (<curtime>) at the start of the transmission of the packet. Usually seconds part when used with included RTC. - 0 - 32 - read-only - - - - - TSN_EP_TSF_D2 - No description available - 0xf028 - 32 - 0x00000000 - 0xE0000007 - - - TSF_TQ - Tx-Timestamp-Fifo, traffic queue <tx_tqueue> of sent packet - 29 - 3 - read-only - - - TSF_USR - Tx-Timestamp-Fifo, user sideband <tx_tuser> of sent packet; Note: any read to register will remove actual value from FIFO - 0 - 3 - read-only - - - - - TSN_EP_TSF_SR - No description available - 0xf02c - 32 - 0x00000000 - 0x800000FF - - - TSF_OV - Overflow of Tx-Timestamp-Fifo. At least one transmitted packet has been sent and timestamp was not stored; write bit to clear flag - 31 - 1 - read-write - - - TSF_USED - Tx-Timestamp-Fifo currently used entries counter; reading of TSF_Dx is only valid if field value > 0. Any read from TSF_D2 will decrement counter (unless already 0). - 0 - 8 - read-only - - - - - TSN_EP_MMS_CTRL - No description available - 0xf030 - 32 - 0x00000000 - 0x000000FF - - - STATSEL - MMS statistic counter selection, value can be read in register -MMS_STAT -<000>: Frame reassembly error counter (802.3br, 30.14.1.8) -<001>: Frames rejected due to wrong SMD (802.3br, 30.14.1.9) -<010>: Frame assembly ok counter (802.3br, 30.14.1.10) -<011>: Fragment rx counter (802.3br, 30.14.1.11) -<100>: Fragment tx counter (802.3br, 30.14.1.12) -<101>: Hold request counter (802.3br, 30.14.1.13) -otherwise: <0> - 5 - 3 - read-write - - - FRAGSZ - Minimum non-final fragment size: 64 x (1 + FRAGSZ) – 4 octets - 3 - 2 - read-write - - - DISV - Disable verification - 2 - 1 - read-write - - - LINK - Link error - 1 - 1 - read-write - - - EN - Enable preemption - 0 - 1 - read-write - - - - - TSN_EP_MMS_STS - No description available - 0xf034 - 32 - 0x00000000 - 0x00000007 - - - VFAIL - 802.3br verification state failure; verification is done when any bit VFAIL or VOK is <1> - 2 - 1 - read-only - - - VOK - 802.3br verification state ok; verification is done when any bit VFAIL or VOK is <1> - 1 - 1 - read-only - - - HLD - HOLD-Signal - 0 - 1 - read-only - - - - - TSN_EP_MMS_VTIME - No description available - 0xf038 - 32 - 0x00000000 - 0xFFFFFFFF - - - VTIME - 802.3br verification timeout counter in <sys_clk> cycles. Must be set by software in range of 1ms to 128ms. - 0 - 32 - read-write - - - - - TSN_EP_MMS_STAT - No description available - 0xf03c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - Statistic counter of MMS, selected by MMS_CTRL.STATSEL,any write access will clear selected counter - 0 - 32 - read-write - - - - - TSN_EP_PTP_UPTM_NS - No description available - 0xf040 - 32 - 0x00000000 - 0xFFFFFFFF - - - UPTM_NS - PTP SYNC frame “upstreamTxTime” in format “seconds.nanoseconds” as potentially received by another TSN-EP port. The correction field of a transmitted PTP SYNC frame is modified by (egressTimestamp –upstreamTxTime), relative to the LocalClock. The “rateRatio” to the Grandmaster Clock is not taken into account. - 0 - 32 - write-only - - - - - TSN_EP_PTP_UPTM_S - No description available - 0xf044 - 32 - 0x00000000 - 0xFFFFFFFF - - - UPTM_NS - No description available - 0 - 32 - write-only - - - - - TSN_EP_PTP_SR - No description available - 0xf048 - 32 - 0x00000000 - 0x0000FFFF - - - MEAS_NS - Measured value of the deviation of the early timestamping for PTP frames. This value is informational only. The deviation is already included to the corrected “correctionField”. - 0 - 16 - read-only - - - - - SW_CTRL_PORT_MAIN_TAGGING - PVID Tagging Register - 0x10000 - 32 - 0x00000001 - 0x0003FFFF - - - FORCE - The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports - 17 - 1 - read-write - - - ACCESS - Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged - 16 - 1 - read-write - - - PCP - VLAN-TCI: Priority Code Point, used when tagged. - 13 - 3 - read-write - - - DEI - VLAN-TCI: Drop Eligible Indicator, used when tagged. - 12 - 1 - read-write - - - PVID - Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1. - 0 - 12 - read-write - - - - - SW_CTRL_PORT_MAIN_ENNABLE - Port Module Enable Register - 0x10004 - 32 - 0x00000003 - 0x00000003 - - - EN_SF - only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption - 1 - 1 - read-write - - - EN_QCI - if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption. - 0 - 1 - read-write - - - - - SW_CTRL_EGRESS_ECSR_QDROP - No description available - 0x12000 - 32 - 0x0001FFFF - 0xFFFFFFFF - - - DIS_VEC - disable drop for each queue when queue not free - 24 - 8 - read-write - - - EN_VEC - Enable/Disable drop in egress when TSN queue not free. -1 - drop enabled -0 - drop disabled -TSN-SW: -bit[i] - from Port[i] - 0 - 24 - read-write - - - - - 2 - 0x100 - e1,p1 - RXFIFO[%s] - no description available - 0x14000 - - SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE - No description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FDMEM_CNT_BYTE - Number of bytes stored in frame drop FIFO - 0 - 32 - read-only - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS - No description available - 0x4 - 32 - 0x00000000 - 0x00000F0F - - - WAIT_FOR_LU - FD FIFO waits for LookUp information. - 11 - 1 - read-only - - - WAIT_FOR_FRAME - FD FIFO waits for more frame data. - 10 - 1 - read-only - - - BUSY - FD FIFO processes data. - 9 - 1 - read-only - - - READY - FD FIFO ready to work or working. - 8 - 1 - read-only - - - FULL - FD FIFO full - 3 - 1 - read-only - - - AMST_FULL - FD FIFO almost full. Less than 1600 Byte left. - 2 - 1 - read-only - - - AMST_EMPTY - FD FIFO almost empty. Few bytes in FIFO. - 1 - 1 - read-only - - - EMPTY - FD FIFO empty - 0 - 1 - read-only - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG - No description available - 0x8 - 32 - 0x00000000 - 0x0000007F - - - LU_DESC_ERR - LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset. - 6 - 1 - read-write - - - WRFAIL_FULL - Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set. - 5 - 1 - read-write - - - DROP_NRDY - Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO - 4 - 1 - read-write - - - DROP_FULL_DESC - Frame was dropped because the internal descriptor FIFO is full. Full by too many frames. - 3 - 1 - read-write - - - DROP_FULL_MEM - Frame was dropped because the FIFO is full. Full by too much data. - 2 - 1 - read-write - - - DESC_NRDY_ERR - FD FIFO failure. Descriptor not received correctly. - 1 - 1 - read-write - - - DESC_SEQ_ERR - FD FIFO failure. Internal controller lost synchronization. - 0 - 1 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG - No description available - 0xc - 32 - 0x00000000 - 0x0000007F - - - IE - Interrupt enable of ERROR_FLAG. - 0 - 7 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG - No description available - 0x10 - 32 - 0x00000000 - 0x00000001 - - - NOCUT_ERROR - FD_FIFO does not shorten frames which contain an error. - 0 - 1 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG - No description available - 0x14 - 32 - 0x00000000 - 0xFFFF037F - - - DROP_DEST - Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0]. - 16 - 16 - read-write - - - MIRROR_TX_EN - Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX. - 9 - 1 - read-write - - - MIRROR_RX_EN - Incoming frames of this port will be mirrored to the given destination in MIRROR_RX. - 8 - 1 - read-write - - - CT_FPE_OVRD - If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F. - 6 - 1 - read-write - - - DISABLE - Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL. - 5 - 1 - read-write - - - DROP_ALL - Route all frames to DROP_DEST. - 4 - 1 - read-write - - - ERROR_TO_CPU - Send error frames to CPU. - 3 - 1 - read-write - - - MIRROR_TO_CPU - Duplicate frames to CPU. - 2 - 1 - read-write - - - NODROP_ERROR - Do not drop frame errors. - 1 - 1 - read-write - - - MODE_STORE_FW - Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward - 0 - 1 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_RESET - No description available - 0x18 - 32 - 0x00000000 - 0x00000001 - - - SOFTRS - Write 1 to reset FD controller and memory pointers. Register Map content remains untouched - 0 - 1 - write-only - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM - No description available - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - LU_FIFO_DEPTH - Number of MAC lookup descriptors the FIFO can store. - 24 - 8 - read-only - - - FD_DESC_FIFO_DESC - Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame. - 16 - 8 - read-only - - - FD_FIFO_DESC - Number of words (4byte) the Frame Drop FIFO can store. - 0 - 16 - read-only - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD - No description available - 0x20 - 32 - 0x00000000 - 0x01FFFFFF - - - PORT - If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK - No description available - 0x24 - 32 - 0x001FFFFF - 0x01FFFFFF - - - PORT - Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports). -bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR - No description available - 0x28 - 32 - 0x00000000 - 0x01FFFFFF - - - PORT - Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port. -bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX - No description available - 0x2c - 32 - 0x00000000 - 0x01FFFFFF - - - PORT - Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic. -bit 0 - CPU-Port, -bit 1 - Port 1, … - 0 - 25 - read-write - - - - - - SW_CTRL_MONITOR_CTRL - No description available - 0x18004 - 32 - 0x00000000 - 0x00000001 - - - EN - Enables counter. If deasserted the counter process stops and the counters hold their value. - 0 - 1 - read-write - - - - - SW_CTRL_MONITOR_RESET - No description available - 0x18008 - 32 - 0x00000000 - 0x00000007 - - - RSRX - Write '1' to reset all RX counters. - 2 - 1 - write-only - - - RSTX - Write '1' to reset all TX counters - 1 - 1 - write-only - - - RSALL - Write '1' to reset all TX&RX counters. - 0 - 1 - write-only - - - - - SW_CTRL_MONITOR_PARAM - No description available - 0x1800c - 32 - 0x00000000 - 0xFFFFFF7F - - - RX_CNT_EN_VEC - Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - 16 - 16 - read-only - - - TX_CNT_EN_VEC - Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - 8 - 8 - read-only - - - CNTW - Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter -are available. - 0 - 7 - read-only - - - - - MONITOR_TX_COUNTER_TX_FGOOD - No description available - 0x18010 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_FGOOD - Good transmitted Frames to TX TSN-EP. - 0 - 32 - read-only - - - - - MONITOR_TX_COUNTER_TX_FERROR - No description available - 0x18018 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_FERROR - Transmitted Frames with Error to TX TSN-EP. - 0 - 32 - read-only - - - - - MONITOR_TX_COUNTER_TX_DROP_OVFL - No description available - 0x18020 - 32 - 0x00000000 - 0xFFFFFFFF - - - TX_DROP_OVFL - Dropped frames by full queue of TSN-EP. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_FGOOD - No description available - 0x18040 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FGOOD - Good received frame by ingress buffer. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_FERROR - No description available - 0x18048 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FERROR - Bad received frame by ingress buffer. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_KNOWN - No description available - 0x18050 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_KNOWN - Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_UNKNOWN - No description available - 0x18058 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_UNKNOWN - Number of frames passed ingress without hit by MAC table. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_UC - No description available - 0x18060 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_UC - Number of unicast frames - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_INTERN - No description available - 0x18068 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_INTERN - Number of non-relay frames - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_BC - No description available - 0x18070 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_BC - Number of Broadcast frames - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_MULTI - No description available - 0x18078 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_MULTI - Number of Multicast frames - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_VLAN - No description available - 0x18080 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_VLAN - Number of VLAN tagged frames - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_DROP_OVFL - No description available - 0x18088 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_OVFL - Dropped frames by ingress overflow. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_DROP_LU - No description available - 0x18090 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_LU - Dropped frames by LookUp decision. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_DROP_ERR - No description available - 0x18098 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_ERR - Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_DROP_VLAN - No description available - 0x180a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_DROP_VLAN - Dropped frames by incompatible VLAN. - 0 - 32 - read-only - - - - - MONITOR_RX_COUNTER_RX_FPE_FGOOD - No description available - 0x180a8 - 32 - 0x00000000 - 0xFFFFFFFF - - - RX_FPE_FGOOD - Number of preemptable frames. Subset of RX_FGOOD - 0 - 32 - read-only - - - - - GPR_CTRL0 - control register0 - 0x1c000 - 32 - 0x00000000 - 0x00003F3F - - - RXCLK_DLY_SEL - delay value of rxclk_delay_chain - 8 - 6 - read-write - - - TXCLK_DLY_SEL - delay value of txclk_delay_chain - 0 - 6 - read-write - - - - - GPR_CTRL2 - control register2 - 0x1c008 - 32 - 0x00010000 - 0x0038E400 - - - MAC_SPEED - mac speed - 20 - 2 - read-write - - - PAD_OE_ETH_REFCLK - refclock output enable when rmii - 19 - 1 - read-write - - - PHY_INTF_SEL - phy interface select - 13 - 3 - read-write - - - RMII_TXCLK_SEL - txclk select control for RMII - 10 - 1 - read-write - - - - - - - - ESC - ESC - ESC - 0xf1700000 - - 0x0 - 0x1f0a4 - registers - - - - TYPE - Type of EtherCAT controller - 0x0 - 8 - 0xA2 - 0xFF - - - TYPE - Controller type - 0 - 8 - read-only - - - - - REVISION - Revision of EtherCAT controller - 0x1 - 8 - 0x00 - 0xFF - - - X - major version X - 0 - 8 - read-only - - - - - BUILD - Build of EtherCAT controller - 0x2 - 16 - 0x0000 - 0xFFFF - - - BUILD - No description available - 8 - 8 - read-only - - - Y - minor version Y - 4 - 4 - read-only - - - Z - maintenance version Z - 0 - 4 - read-only - - - - - FMMU_NUM - FMMU supported - 0x4 - 8 - 0x08 - 0xFF - - - NUM - Number of supported FMMU channels (or entities) - 0 - 8 - read-only - - - - - SYNCM_NUM - SyncManagers supported - 0x5 - 8 - 0x08 - 0xFF - - - NUM - Number of supported SyncManager channels (or entities) - 0 - 8 - read-only - - - - - RAM_SIZE - RAM Size - 0x6 - 8 - 0x3C - 0xFF - - - SIZE - Process Data RAM size supported in KByte - 0 - 8 - read-only - - - - - PORT_DESC - Port Descriptor - 0x7 - 8 - 0x3F - 0xFF - - - PORT3 - Port configuration: -00:Not implemented -01:Not configured (SII EEPROM) -10:EBUS -11:MII/RMII/RGMII - 6 - 2 - read-only - - - PORT2 - Port configuration: -00:Not implemented -01:Not configured (SII EEPROM) -10:EBUS -11:MII/RMII/RGMII - 4 - 2 - read-only - - - PORT1 - Port configuration: -00:Not implemented -01:Not configured (SII EEPROM) -10:EBUS -11:MII/RMII/RGMII - 2 - 2 - read-only - - - PORT0 - Port configuration: -00:Not implemented -01:Not configured (SII EEPROM) -10:EBUS -11:MII/RMII/RGMII - 0 - 2 - read-only - - - - - FEATURE - ESC Feature supported - 0x8 - 16 - 0x008C - 0x0FCD - - - FFSC - Fixed FMMU/SyncManager configuration: -0:Variable configuration -1:Fixed configuration (refer to documentation of supporting ESCs) - 11 - 1 - read-only - - - RWC - EtherCAT read/write command support(BRW,APRW,FPRW): -0:Supported -1:Not supported - 10 - 1 - read-only - - - LRW - EtherCAT LRW command support: -0:Supported -1:Not supported - 9 - 1 - read-only - - - EDSA - Enhanced DC SYNC Activation: -0:Not available -1:Available -Note:This feature refers to registers 0x981[7:3] and 0x0984 - 8 - 1 - read-only - - - SHFE - Seperate Handling of FCS Errors: -0:Not supported -1:Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter - 7 - 1 - read-only - - - ELDM - Enhanced Link Detection MII: -0:Not available -1:Available - 6 - 1 - read-only - - - DCW - Distributed Clocks width: -0:32 bit -1:64 bit - 3 - 1 - read-only - - - DC - Distributed Clocks: -0:Not available -1:Available - 2 - 1 - read-only - - - FMMU - FMMU Operation: -0:Bit oriented -1:Byte oriented - 0 - 1 - read-only - - - - - STATION_ADDR - Configured Station Address - 0x10 - 16 - 0x0000 - 0xFFFF - - - ADDR - Address used for node addressing -(FPRD/FPWR/FPRW/FRMW commands) - 0 - 16 - read-only - - - - - STATION_ALS - Configured Station Alias - 0x12 - 16 - 0x0000 - 0xFFFF - - - ADDR - Alias Address used for node addressing -(FPRD/FPWR/FPRW/FRMW commands). -The use of this alias is activated by Register -DL Control Bit 0x0100[24]. -NOTE:EEPROM value is only transferred into this -register at first EEPROM load after power-on or -reset. -ESC20 exception:EEPROM value is transferred -into this register after each EEPROM reload -command. - 0 - 16 - read-write - - - - - REG_WEN - Register Write Enable - 0x20 - 8 - 0x00 - 0x01 - - - EN - If register write protection is enabled, this -register has to be written in the same -Ethernet frame (value does not matter) -before other writes to this station are allowed. -This bit is self-clearing at the beginning of the -next frame (SOF), or if Register Write -Protection is disabled. - 0 - 1 - read-only - - - - - REG_WP - Register Write Protection - 0x21 - 8 - 0x00 - 0x01 - - - WP - Register write protection: -0:Protection disabled -1:Protection enabled -Registers 0x0000:0x0F7F are write-protected, -except for 0x0020 and 0x0030 - 0 - 1 - read-only - - - - - ESC_WEN - ESC Write Enable - 0x30 - 8 - 0x00 - 0x01 - - - EN - If ESC write protection is enabled, this -register has to be written in the same -Ethernet frame (value does not matter) -before other writes to this station are allowed. -This bit is self-clearing at the beginning of the -next frame (SOF), or if ESC Write Protection -is disabled. - 0 - 1 - read-only - - - - - ESC_WP - ESC Write Protection - 0x31 - 8 - 0x00 - 0x01 - - - WP - Write protect: -0:Protection disabled -1:Protection enabled -All areas are write-protected, except for 0x0030. - 0 - 1 - read-only - - - - - ESC_RST_ECAT - ESC Reset ECAT - 0x40 - 8 - 0x00 - 0x03 - - - PR - Progress of the reset procedure: -00:initial/reset state -01:after writing 0x52 ('R'), when previous -state was 00 -10:after writing 0x45 ('E'), when previous -state was 01 -11:after writing 0x53 ('S'), when previous -state was 10. -This value must not be observed -because the ESC enters reset when this -state is reached, resulting in state 00 - 0 - 2 - read-only - - - - - ESC_RST_PDI - ESC Reset PDI - 0x41 - 8 - 0x00 - 0xFF - - - RST - A reset is asserted after writing the reset -sequence 0x52 ('R'), 0x45 ('E') and 0x53 ('S') -in this register with 3 consecutive commands. -Any other command which does not continue -the sequence by writing the next expected -value will cancel the reset procedure - 0 - 8 - read-write - - - - - ESC_DL_CTRL - ESC DL Control - 0x100 - 32 - 0x00000000 - 0x0107FF03 - - - SA - Station alias: -0:Ignore Station Alias -1:Alias can be used for all configured -address comm - 24 - 1 - read-only - - - RFS - RX FIFO Size (ESC delays start of -forwarding until FIFO is at least half full). -RX FIFO Size/RX delay reduction** : -Value:EBUS:MII: -0:-50 ns -40 ns (-80 ns***) -1:-40 ns -40 ns (-80 ns***) -2:-30 ns -40 ns -3:-20 ns -40 ns -4:-10 ns no change -5:no change no change -6:no change no change -7:default default -NOTE:EEPROM value is only taken over at first -EEPROM load after power-on or reset - 16 - 3 - read-only - - - LP3 - Loop Port 3: -00:Auto -01:Auto Close -10:Open -11:Closed - 14 - 2 - read-only - - - LP2 - Loop Port 2: -00:Auto -01:Auto Close -10:Open -11:Closed - 12 - 2 - read-only - - - LP1 - Loop Port 1: -00:Auto -01:Auto Close -10:Open -11:Closed - 10 - 2 - read-only - - - LP0 - Loop Port 0: -00:Auto -01:Auto Close -10:Open -11:Closed -NOTE: -Loop open means sending/receiving over this port -is enabled, loop closed means sending/receiving -is disabled and frames are forwarded to the next -open port internally. -Auto:loop closed at link down, opened at link up -Auto Close:loop closed at link down, opened with -writing 01 again after link up (or receiving a valid -Ethernet frame at the closed port) -Open:loop open regardless of link state -Closed:loop closed regardless of link state - 8 - 2 - read-only - - - TU - Temporary use of settings in -0x0100:0x0103[8:15]: -0:permanent use -1:use for about 1 second, then revert to -previous settings - 1 - 1 - read-only - - - FR - Forwarding rule: -0:Forward non-EtherCAT frames: -EtherCAT frames are processed, -non-EtherCAT frames are forwarded -without processing or modification. -The source MAC address is not -changed for any frame. -1:Destroy non-EtherCAT frames: -EtherCAT frames are processed, non-EtherCAT frames are destroyed. -The source MAC address is changed by -the Processing Unit for every frame -(SOURCE_MAC[1] is set - 0 - 1 - read-only - - - - - PHYSICAL_RW_OFFSET - Physical Read/Write Offset - 0x108 - 16 - 0x0000 - 0xFFFF - - - OFFSET - This register is used for ReadWrite -commands in Device Addressing mode -(FPRW, APRW, BRW). -The internal read address is directly taken -from the offset address field of the EtherCAT -datagram header, while the internal write -address is calculated by adding the Physical -Read/Write Offset value to the offset address -field. -Internal read address = ADR, -internal write address = ADR + R/W-Offset - 0 - 16 - read-only - - - - - ESC_DL_STAT - ESC DL Status - 0x110 - 16 - 0x0000 - 0xFFF7 - - - CP3 - Communication on Port 3: -0:No stable communication -1:Communication established - 15 - 1 - read-only - - - LP3 - Loop Port 3: -0:Open -1:Closed - 14 - 1 - read-only - - - CP2 - Communication on Port 2: -0:No stable communication -1:Communication established - 13 - 1 - read-only - - - LP2 - Loop Port 2: -0:Open -1:Closed - 12 - 1 - read-only - - - CP1 - Communication on Port 1: -0:No stable communication -1:Communication established - 11 - 1 - read-only - - - LP1 - Loop Port 1: -0:Open -1:Closed - 10 - 1 - read-only - - - CP0 - Communication on Port 0: -0:No stable communication -1:Communication established - 9 - 1 - read-only - - - LP0 - Loop Port 0: -0:Open -1:Closed - 8 - 1 - read-only - - - PLP3 - Physical link on Port 3: -0:No link -1:Link detected - 7 - 1 - read-only - - - PLP2 - Physical link on Port 2: -0:No link -1:Link detected - 6 - 1 - read-only - - - PLP1 - Physical link on Port 1: -0:No link -1:Link detected - 5 - 1 - read-only - - - PLP0 - Physical link on Port 0: -0:No link -1:Link detected - 4 - 1 - read-only - - - ELD - Enhanced Link detection: -0:Deactivated for all ports -1:Activated for at least one port -NOTE:EEPROM value is only transferred into this -register at first EEPROM load after power-on or -reset - 2 - 1 - read-only - - - WDS - PDI Watchdog Status: -0:Watchdog expired -1:Watchdog reloaded - 1 - 1 - read-only - - - EPLC - PDI operational/EEPROM loaded correctly: -0:EEPROM not loaded, PDI not -operational (no access to Process Data -RAM) -1:EEPROM loaded correctly, PDI -operational (access to Process Data -RAM) - 0 - 1 - read-only - - - - - AL_CTRL - AL Control - 0x120 - 16 - 0x0001 - 0x003F - - - DI - Device Identification: -0:No request -1:Device Identification request - 5 - 1 - read-write - - - EIA - Error Ind Ack: -0:No Ack of Error Ind in AL status register -1:Ack of Error Ind in AL status register - 4 - 1 - read-write - - - IST - Initiate State Transition of the Device State -Machine: -1:Request Init State -3:Request Bootstrap State -2:Request Pre-Operational State -4:Request Safe-Operational State -8:Request Operational State - 0 - 4 - read-write - - - - - AL_STAT - AL Status - 0x130 - 16 - 0x0001 - 0x003F - - - DI - Device Identification: -0:Device Identification not valid -1:Device Identification loaded - 5 - 1 - read-write - - - EI - Error Ind: -0:Device is in State as requested or Flag -cleared by command -1:Device has not entered requested State -or changed State as result of a local -action - 4 - 1 - read-write - - - AS - Actual State of the Device State Machine: -1:Init State -3:Bootstrap State -2:Pre-Operational State -4:Safe-Operational State -8:Operational State - 0 - 4 - read-write - - - - - AL_STAT_CODE - AL Status Code - 0x134 - 16 - 0x0000 - 0xFFFF - - - CODE - AL Status Code - 0 - 16 - read-write - - - - - RUN_LED_OVRD - RUN LED Override - 0x138 - 8 - 0x00 - 0x1F - - - EN_OVRD - Enable Override: -0:Override disabled -1:Override enabled - 4 - 1 - read-write - - - LED_CODE - LED code: -0x0:Off -0x1:Flash 1x -0x2-0xC:Flash 2x – 12x -0xD:Blinking -0xE:Flickering -0xF:On - 0 - 4 - read-write - - - - - ERR_LED_OVRD - ERR LED Override - 0x139 - 8 - 0x00 - 0x1F - - - EN_OVRD - Enable Override: -0:Override disabled -1:Override enabled - 4 - 1 - read-write - - - LED_CODE - LED code: -0x0:Off -0x1-0xC:Flash 1x – 12x -0xD:Blinking -0xE:Flickering -0xF:On - 0 - 4 - read-write - - - - - PDI_CTRL - PDI Control - 0x140 - 8 - 0x00 - 0xFF - - - PDI - Process data interface: -0x00:Interface deactivated (no PDI) -0x01:4 Digital Input -0x02:4 Digital Output -0x03:2 Digital Input and 2 Digital Output -0x04:Digital I/O -0x05:SPI Slave -0x06:Oversampling I/O -0x07:EtherCAT Bridge (port 3) -0x08:16 Bit asynchronous Microcontroller -interface -0x09:8 Bit asynchronous Microcontroller -interface -0x0A:16 Bit synchronous Microcontroller -interface -0x0B:8 Bit synchronous Microcontroller -interface -0x10:32 Digital Input and 0 Digital Output -0x11:24 Digital Input and 8 Digital Output -0x12:16 Digital Input and 16 Digital Output -0x13:8 Digital Input and 24 Digital Output -0x14:0 Digital Input and 32 Digital Output -0x80:On-chip bus -Others:Reserved - 0 - 8 - read-only - - - - - ESC_CFG - ESC Configuration - 0x141 - 8 - 0x01 - 0xFF - - - ELP3 - Enhanced Link port 3: -0:disabled (if bit 1=0) -1:enabled - 7 - 1 - read-only - - - ELP2 - Enhanced Link port 2: -0:disabled (if bit 1=0) -1:enabled - 6 - 1 - read-only - - - ELP1 - Enhanced Link port 1: -0:disabled (if bit 1=0) -1:enabled - 5 - 1 - read-only - - - ELP0 - Enhanced Link port 0: -0:disabled (if bit 1=0) -1:enabled - 4 - 1 - read-only - - - CDLIU - Distributed Clocks Latch In Unit: -0:disabled (power saving) -1:enabled - 3 - 1 - read-only - - - DCSOU - Distributed Clocks SYNC Out Unit: -0:disabled (power saving) -1:enabled - 2 - 1 - read-only - - - ELDAP - Enhanced Link detection all ports: -0:disabled (if bits [7:4]=0) -1:enabled at all ports (overrides bits [7:4]) - 1 - 1 - read-only - - - DEV_EMU - Device emulation (control of AL status): -0:AL status register has to be set by PDI -1:AL status register will be set to value -written to AL control register - 0 - 1 - read-only - - - - - PDI_INFO - PDI Information - 0x14e - 16 - 0x0000 - 0x000F - - - PDICN - PDI configuration invalid: -0:PDI configuration ok -1:PDI configuration invalid - 3 - 1 - read-only - - - PDIA - PDI active: -0:PDI not active -1:PDI active - 2 - 1 - read-only - - - ECLFE - ESC configuration area loaded from -EEPROM: -0:not loaded -1:loaded - 1 - 1 - read-only - - - PFABW - DI function acknowledge by write: -0:Disabled -1:Enabled - 0 - 1 - read-only - - - - - PDI_CFG - PDI Configuration - 0x150 - 8 - 0x84 - 0xFF - - - BUS - On-chip bus: -000:Intel® Avalon® -001:AXI® -010:Xilinx® PLB v4.6 -100:Xilinx OPB -others:reserved - 5 - 3 - read-only - - - CLK - On-chip bus clock: -0:asynchronous -1-31:synchronous multiplication factor -(N * 25 MHz) - 0 - 5 - read-only - - - - - PDI_SL_CFG - PDI Sync/Latch[1:0] Configuration - 0x151 - 8 - 0x00 - 0xFF - - - SYNC1_MAER - SYNC1 mapped to AL Event Request -register 0x0220[3]: -0:Disabled -1:Enabled - 7 - 1 - read-only - - - SYNC1_CFG - SYNC1/LATCH1 configuration*: -0:LATCH1 input -1:SYNC1 output - 6 - 1 - read-only - - - SYNC1_ODP - SYNC1 output driver/polarity: -00:Push-Pull active low -01:Open Drain (active low) -10:Push-Pull active high -11:Open Source (active high) - 4 - 2 - read-only - - - SYNC0_MAER - SYNC0 mapped to AL Event Request -register 0x0220[2]: -0:Disabled -1:Enabled - 3 - 1 - read-only - - - SYNC0_CFG - SYNC0/LATCH0 configuration*: -0:LATCH0 Input -1:SYNC0 Output - 2 - 1 - read-only - - - SYNC0_ODP - SYNC0 output driver/polarity: -00:Push-Pull active low -01:Open Drain (active low) -10:Push-Pull active high -11:Open Source (active high) - 0 - 2 - read-only - - - - - PDI_EXT_CFG - PDI Extended Configuration - 0x152 - 16 - 0x0000 - 0x0703 - - - OCBST - On-chip bus sub-type for AXI: -000:AXI3 -001:AXI4 -010:AXI4 LITE -others:reserved - 8 - 3 - read-write - - - RPS - Read prefetch size (in cycles of PDI width): -0:4 cycles -1:1 cycle (typical) -2:2 cycles -3:Reserved - 0 - 2 - read-only - - - - - ECAT_EVT_MSK - ECAT Event Mask - 0x200 - 16 - 0x0000 - 0xFFFF - - - MASK - ECAT Event masking of the ECAT Event -Request Events for mapping into ECAT event -field of EtherCAT frames: -0:Corresponding ECAT Event Request -register bit is not mapped -1:Corresponding ECAT Event Request -register bit is mapped - 0 - 16 - read-only - - - - - PDI_AL_EVT_MSK - PDI AL Event Mask - 0x204 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - AL Event masking of the AL Event Request -register Events for mapping to PDI IRQ -signal: -0:Corresponding AL Event Request -register bit is not mapped -1:Corresponding AL Event Request -register bit is mapped - 0 - 32 - read-write - - - - - ECAT_EVT_REQ - ECAT Event Request - 0x210 - 16 - 0x0000 - 0x0FFD - - - MV - Mirrors values of each SyncManager Status: -0:No Sync Channel 0 event -1:Sync Channel 0 event pending -0:No Sync Channel 1 event -1:Sync Channel 1 event pending -… -0:No Sync Channel 7 event -1:Sync Channel 7 event pending - 4 - 8 - read-only - - - ALS_EVT - AL Status event: -0:No change in AL Status -1:AL Status change -(Bit is cleared by reading out AL Status -0x0130:0x0131 from ECAT) - 3 - 1 - read-only - - - DLS_EVT - DL Status event: -0:No change in DL Status -1:DL Status change -(Bit is cleared by reading out DL Status -0x0110:0x0111 from ECAT) - 2 - 1 - read-only - - - DCL_EVT - DC Latch event: -0:No change on DC Latch Inputs -1:At least one change on DC Latch Inputs -(Bit is cleared by reading DC Latch event -times from ECAT for ECAT-controlled Latch -Units, so that Latch 0/1 Status -0x09AE:0x09AF indicates no event) - 0 - 1 - read-only - - - - - AL_EVT_REQ - AL Event Request - 0x220 - 32 - 0x00000000 - 0x00FFFF7F - - - SM_INT - SyncManager interrupts (SyncManager -register offset 0x5, bit [0] or [1]): -0:No SyncManager 0 interrupt -1:SyncManager 0 interrupt pending -0:No SyncManager 1 interrupt -1:SyncManager 1 interrupt pending -… -0:No SyncManager 15 interrupt -1:SyncManager 15 interrupt pending - 8 - 16 - read-only - - - WDG_PD - Watchdog Process Data: -0:Has not expired -1:Has expired -(Bit is cleared by reading Watchdog Status -Process Data 0x0440 from PDI) - 6 - 1 - read-only - - - EE_EMU - EEPROM Emulation: -0:No command pending -1:EEPROM command pending -(Bit is cleared by acknowledging the -command in EEPROM Control/Status -register 0x0502:0x0503[10:8] from PDI) - 5 - 1 - read-only - - - SM_ACT - SyncManager activation register -(SyncManager register offset 0x6) changed: -0:No change in any SyncManager -1:At least one SyncManager changed -(Bit is cleared by reading SyncManager -Activation registers 0x0806 etc. from PDI) - 4 - 1 - read-only - - - ST_DC_SYNC1 - State of DC SYNC1 (if register -0x0151[7]=1): -(Bit is cleared by reading of SYNC1 status -0x098F from PDI, use only in Acknowledge -mode) - 3 - 1 - read-only - - - ST_DC_SYNC0 - State of DC SYNC0 (if register -0x0151[3]=1): -(Bit is cleared by reading SYNC0 status -0x098E from PDI, use only in Acknowledge -mode) - 2 - 1 - read-only - - - DCL_EVT - DC Latch event: -0:No change on DC Latch Inputs -1:At least one change on DC Latch Inputs -(Bit is cleared by reading DC Latch event -times from PDI, so that Latch 0/1 Status -0x09AE:0x09AF indicates no event. Available -if Latch Unit is PDI-controlled) - 1 - 1 - read-only - - - ALC_EVT - AL Control event: -0:No AL Control Register change -1:AL Control Register has been written3 -(Bit is cleared by reading AL Control register -0x0120:0x0121 from PDI) - 0 - 1 - read-only - - - - - 4 - 0x2 - PORT0,PORT1,PORT2,PORT3 - RX_ERR_CNT[%s] - no description available - 0x300 - 16 - 0x0000 - 0xFFFF - - - RX_ERR - RX Error counter of Port y (counting is -stopped when 0xFF is reached). - 8 - 8 - read-only - - - IVD_FRM - Invalid frame counter of Port y (counting is -stopped when 0xFF is reached). - 0 - 8 - read-only - - - - - 4 - 0x1 - PORT0,PORT1,PORT2,PORT3 - FWD_RX_ERR_CNT[%s] - no description available - 0x308 - 8 - 0x00 - 0xFF - - - ERR_CNT - Forwarded error counter of Port y (counting is -stopped when 0xFF is reached). - 0 - 8 - read-only - - - - - ECAT_PU_ERR_CNT - ECAT Processing Unit Error Counter - 0x30c - 8 - 0x00 - 0xFF - - - CNT - ECAT Processing Unit error counter -(counting is stopped when 0xFF is reached). -Counts errors of frames passing the -Processing Unit. - 0 - 8 - read-only - - - - - PDI_ERR_CNT - PDI Error Counter - 0x30d - 8 - 0x00 - 0xFF - - - CNT - PDI Error counter (counting is stopped when -0xFF is reached). Counts if a PDI access has -an interface error. - 0 - 8 - read-only - - - - - 4 - 0x1 - PORT0,PORT1,PORT2,PORT3 - LOST_LINK_CNT[%s] - no description available - 0x310 - 8 - 0x00 - 0xFF - - - CNT - Lost Link counter of Port y (counting is -stopped when 0xff is reached). Counts only if -port is open and loop is Auto. - 0 - 8 - read-only - - - - - WDG_DIV - Watchdog Divider - 0x400 - 16 - 0x09C2 - 0xFFFF - - - DIV - Watchdog divider:Number of 25 MHz tics -(minus 2) that represent the basic watchdog -increment. (Default value is 100µs = 2498) - 0 - 16 - read-only - - - - - WDG_TIME_PDI - Watchdog Time PDI - 0x410 - 16 - 0x03E8 - 0xFFFF - - - TIME - Watchdog Time PDI:number of basic -watchdog increments -(Default value with Watchdog divider 100µs -means 100ms Watchdog) - 0 - 16 - read-only - - - - - WDG_TIME_PDAT - Watchdog Time Process Data - 0x420 - 16 - 0x0000 - 0xFFFF - - - TIME - Watchdog Time Process Data:number of -basic watchdog increments -(Default value with Watchdog divider 100µs -means 100ms Watchdog) - 0 - 16 - read-only - - - - - WDG_STAT_PDAT - Watchdog Status Process Data - 0x440 - 16 - 0x0000 - 0x0001 - - - ST - Watchdog Status of Process Data (triggered -by SyncManagers) -0:Watchdog Process Data expired -1:Watchdog Process Data is active or -disabled - 0 - 1 - read-write - - - - - WDG_CNT_PDAT - Watchdog Counter Process Data - 0x442 - 8 - 0x00 - 0xFF - - - CNT - Watchdog Counter Process Data (counting is -stopped when 0xFF is reached). Counts if -Process Data Watchdog expires. - 0 - 8 - read-only - - - - - WDG_CNT_PDI - Watchdog Counter PDI - 0x443 - 8 - 0x00 - 0xFF - - - CNT - Watchdog PDI counter (counting is stopped -when 0xFF is reached). Counts if PDI -Watchdog expires. - 0 - 8 - read-only - - - - - EEPROM_CFG - EEPROM Configuration - 0x500 - 8 - 0x00 - 0x03 - - - FORCE_ECAT - Force ECAT access: -0:Do not change Bit 0x0501[0] -1:Reset Bit 0x0501[0] to 0 - 1 - 1 - read-only - - - PDI - EEPROM control is offered to PDI: -0:no -1:yes (PDI has EEPROM control) - 0 - 1 - read-only - - - - - EEPROM_PDI_ACC_STAT - EEPROM PDI Access State - 0x501 - 8 - 0x00 - 0x01 - - - ACCESS - Access to EEPROM: -0:PDI releases EEPROM access -1:PDI takes EEPROM access (PDI has -EEPROM control) - 0 - 1 - read-write - - - - - EEPROM_CTRL_STAT - EEPROM Control/Status - 0x502 - 16 - 0x0000 - 0xFFE1 - - - BUSY - Busy: -0:EEPROM Interface is idle -1:EEPROM Interface is busy - 15 - 1 - read-only - - - ERR_WEN - Error Write Enable*3 -: -0:No error -1:Write Command without Write enable - 14 - 1 - read-only - - - ERR_ACK_CMD - Error Acknowledge/Command*3 -: -0:No error -1:Missing EEPROM acknowledge or invalid -command -EEPROM emulation only:PDI writes 1 if a temporary -failure has occurred. - 13 - 1 - read-write - - - EE_LDS - EEPROM loading status: -0:EEPROM loaded, device information ok -1:EEPROM not loaded, device information not -available (EEPROM loading in progress or -finished with a failure) - 12 - 1 - read-only - - - CKSM_ERR - Checksum Error in ESC Configuration Area: -0:Checksum ok -1:Checksum error -EEPROM emulation for IP Core only:PDI writes 1 if a -CRC failure has occurred for a reload command. - 11 - 1 - read-write - - - CMD - Command register*2: -Write:Initiate command. -Read:Currently executed command -Commands: -000:No command/EEPROM idle (clear error bits) -001:Read -010:Write -100:Reload -Others:Reserved/invalid commands (do not issue) -EEPROM emulation only:after execution, PDI writes -command value to indicate operation is ready. - 8 - 3 - read-write - - - EE_ALGM - Selected EEPROM Algorithm: -0:1 address byte (1Kbit – 16Kbit EEPROMs) -1:2 address bytes (32Kbit – 4 Mbit EEPROMs) - 7 - 1 - read-only - - - NUM_RD_BYTE - Supported number of EEPROM read bytes: -0:4 Bytes -1:8 Bytes - 6 - 1 - read-only - - - EE_EMU - EPROM emulation: -0:Normal operation (I²C interface used) -1:PDI emulates EEPROM (I²C not used) - 5 - 1 - read-only - - - ECAT_WEN - ECAT write enable*2 -: -0:Write requests are disabled -1:Write requests are enabled -This bit is always 1 if PDI has EEPROM control. - 0 - 1 - read-only - - - - - EEPROM_ADDR - EEPROM Address - 0x504 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - EEPROM Address -0:First word (= 16 bit) -1:Second word -… -Actually used EEPROM Address bits: -[9-0] : EEPROM size up to 16 Kbit -[17-0] : EEPROM size 32 Kbit – 4 Mbit -[31-0] : EEPROM Emulation - 0 - 32 - read-write - - - - - EEPROM_DATA - EEPROM Data - 0x508 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - HI - EEPROM Read data (data read from -EEPROM, higher bytes) - 16 - 48 - read-write - - - LO - EEPROM Write data (data to be written to -EEPROM) or -EEPROM Read data (data read from -EEPROM, lower bytes) - 0 - 16 - read-write - - - - - MII_MNG_CS - MII Management Control/Status - 0x510 - 16 - 0x0000 - 0xE3FF - - - BUSY - Busy: -0:MII Management Interface is idle -1:MII Management Interface is busy - 15 - 1 - read-only - - - CMD_ERR - Command error: -0:Last Command was successful -1:Invalid command or write command -without Write Enable -Cleared by executing a valid command or by -writing “00” to Command register bits [9:8]. - 14 - 1 - read-only - - - RD_ERR - Read error: -0:No read error -1:Read error occurred (PHY or register -not available) -Cleared by writing to register 0x0511 - 13 - 1 - read-only - - - CMD - Command register*: -Write:Initiate command. -Read:Currently executed command -00:No command/MI idle (clear error bits) -01:Read -10:Write -Others:Reserved/invalid command (do not -issue) - 8 - 2 - read-write - - - PHY_ADDR - PHY address of port 0 -(this is equal to the PHY address offset, if the -PHY addresses are consecutive) -IP Core since V3.0.0/3.00c: -Translation 0x0512[7]=0: -Register 0x0510[7:3] shows PHY address of -port 0 -Translation 0x0512[7]=1: -Register 0x0510[7:3] shows the PHY address -which will be used for port 0-3 as requested -by 0x0512[4:0] (valid values 0-3) - 3 - 5 - read-only - - - LINK_DC - MI link detection and configuration: -0:Disabled for all ports -1:Enabled for at least one MII port, refer -to PHY Port Status (0x0518 ff.) for -details - 2 - 1 - read-only - - - PDI - Management Interface can be controlled by -PDI (registers 0x0516-0x0517): -0:Only ECAT control -1:PDI control possible - 1 - 1 - read-only - - - WEN - Write enable*: -0:Write disabled -1:Write enabled -This bit is always 1 if PDI has MI control. -ET1100-0000/-0001 exception: -Bit is not always 1 if PDI has MI control, and -bit is writable by PDI. - 0 - 1 - read-only - - - - - PHY_ADDR - PHY Address - 0x512 - 8 - 0x00 - 0x9F - - - SHOW - Target PHY Address translation: -0:Enabled -1:Disabled -Refer to 0x0512[4:0] and 0x0510[7:3] for -details. - 7 - 1 - read-write - - - ADDR - Target PHY Address -Translation 0x0512[7]=0: -0-3:Target PHY Addresses 0-3 are used -to access the PHYs at port 0-3, when -the PHY addresses are properly -configured -4-31:The configured PHY address of port 0 -(PHY address offset) is added to the -Target PHY Address values 4-31 -when accessing a PHY -Translation 0x0512[7]=1: -0-31:Target PHY Addresses is used when -accessing a PHY without translation - 0 - 5 - read-write - - - - - PHY_REG_ADDR - PHY Register Address - 0x513 - 8 - 0x00 - 0x1F - - - ADDR - Address of PHY Register that shall be -read/written - 0 - 5 - read-write - - - - - PHY_DATA - PHY Data - 0x514 - 16 - 0x0000 - 0xFFFF - - - DATA - PHY Read/Write Data - 0 - 16 - read-write - - - - - MIIM_ECAT_ACC_STAT - MII Management ECAT Access State - 0x516 - 8 - 0x00 - 0x01 - - - ACC - Access to MII management: -0:ECAT enables PDI takeover of MII -management interface -1:ECAT claims exclusive access to MII -management interface - 0 - 1 - read-only - - - - - MIIM_PDI_ACC_STAT - MII Management PDI Access State - 0x517 - 8 - 0x00 - 0x03 - - - FORCE - Force PDI Access State: -0:Do not change Bit 0x0517[0] -1:Reset Bit 0x0517[0] to 0 - 1 - 1 - read-only - - - ACC - Access to MII management: -0:ECAT has access to MII management -1:PDI has access to MII management - 0 - 1 - read-write - - - - - 4 - 0x1 - PORT0,PORT1,PORT2,PORT3 - PHY_STAT[%s] - no description available - 0x518 - 8 - 0x00 - 0x3F - - - PCU - PHY configuration updated: -0:No update -1:PHY configuration was updated -Cleared by writing any value to at least one -of the PHY Port y Status registers. - 5 - 1 - read-write - - - LPE - Link partner error: -0:No error detected -1:Link partner error - 4 - 1 - read-only - - - RE - Read error: -0:No read error occurred -1:A read error has occurred -Cleared by writing any value to at least one -of the PHY Port y Status registers. - 3 - 1 - read-write - - - LSE - Link status error: -0:No error -1:Link error, link inhibited - 2 - 1 - read-only - - - LS - Link status (100 Mbit/s, Full Duplex, Auto -negotiation): -0:No link -1:Link detected - 1 - 1 - read-only - - - PLS - Physical link status (PHY status register 1.2): -0:No physical link -1:Physical link detected - 0 - 1 - read-only - - - - - 8 - 0x10 - 0,1,2,3,4,5,6,7 - FMMU[%s] - no description available - 0x600 - - LOGIC_START_ADDR - Logical Start Address - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - ADDR - Logical start address within the EtherCAT -Address Space. - 0 - 32 - read-only - - - - - LENGTH - Length - 0x4 - 16 - 0x0000 - 0xFFFF - - - OFFSET - Offset from the first logical FMMU byte to the -last FMMU byte + 1 (e.g., if two bytes are -used, then this parameter shall contain 2) - 0 - 16 - read-only - - - - - LOGIC_START_BIT - Logical Start Bit - 0x6 - 8 - 0x00 - 0x07 - - - START - Logical starting bit that shall be mapped (bits -are counted from least significant bit 0 to -most significant bit 7) - 0 - 3 - read-only - - - - - LOGIC_STOP_BIT - Logical Stop Bit - 0x7 - 8 - 0x00 - 0x07 - - - STOP - Last logical bit that shall be mapped (bits are -counted from least significant bit 0 to most -significant bit 7) - 0 - 3 - read-only - - - - - PHYSICAL_START_ADDR - Physical Start Address - 0x8 - 16 - 0x0000 - 0xFFFF - - - ADDR - Physical Start Address (mapped to logical -Start address) - 0 - 16 - read-only - - - - - PHYSICAL_START_BIT - Physical Start Bit - 0xa - 8 - 0x00 - 0x07 - - - START - Physical starting bit as target of logical start -bit mapping (bits are counted from least -significant bit 0 to most significant bit 7) - 0 - 3 - read-only - - - - - TYPE - Type - 0xb - 8 - 0x00 - 0x03 - - - MAP_WR - 0:Ignore mapping for write accesses -1:Use mapping for write accesses - 1 - 1 - read-only - - - MAP_RD - 0:Ignore mapping for read accesses -1:Use mapping for read accesses - 0 - 1 - read-only - - - - - ACTIVATE - Activate - 0xc - 8 - 0x00 - 0x01 - - - ACT - 0:FMMU deactivated -1:FMMU activated. FMMU checks -logically addressed blocks to be -mapped according to configured -mapping - 0 - 1 - read-only - - - - - - 8 - 0x8 - 0,1,2,3,4,5,6,7 - SYNCM[%s] - no description available - 0x800 - - PHYSICAL_START_ADDR - Physical Start Address - 0x0 - 16 - 0x0000 - 0xFFFF - - - ADDR - First byte that will be handled by -SyncManager - 0 - 16 - read-only - - - - - LENGTH - Length - 0x2 - 16 - 0x0000 - 0xFFFF - - - LEN - Number of bytes assigned to SyncManager -(shall be greater than 1, otherwise -SyncManager is not activated. If set to 1, only -Watchdog Trigger is generated if configured) - 0 - 16 - read-only - - - - - CONTROL - Control - 0x4 - 8 - 0x00 - 0x7F - - - WDG_TRG_EN - Watchdog Trigger Enable: -0:Disabled -1:Enabled - 6 - 1 - read-only - - - INT_AL - Interrupt in AL Event Request Register: -0:Disabled -1:Enabled - 5 - 1 - read-only - - - INT_ECAT - Interrupt in ECAT Event Request Register: -0:Disabled -1:Enabled - 4 - 1 - read-only - - - DIR - Direction: -00:Read:ECAT read access, PDI write -access. -01:Write:ECAT write access, PDI read -access. -10:Reserved -11:Reserved - 2 - 2 - read-only - - - OP_MODE - Operation Mode: -00:Buffered (3 buffer mode) -01:Reserved -10:Mailbox (Single buffer mode) -11:Reserved - 0 - 2 - read-only - - - - - STATUS - Status - 0x5 - 8 - 0x00 - 0xFB - - - WB_INUSE - Write buffer in use (opened) - 7 - 1 - read-only - - - RB_INUSE - Read buffer in use (opened) - 6 - 1 - read-only - - - BUF_MODE - Buffered mode:buffer status (last written -buffer): -00:1 -st buffer -01:2 -nd buffer -10:3 -rd buffer -11:(no buffer written) -Mailbox mode:reserved - 4 - 2 - read-only - - - MBX_MODE - Mailbox mode:mailbox status: -0:Mailbox empty -1:Mailbox full -Buffered mode:reserved - 3 - 1 - read-only - - - INT_RD - Interrupt Read: -1:Interrupt after buffer was completely and -successfully read -0:Interrupt cleared after first byte of buffer -was written -NOTE:This interrupt is signalled to the writing -side if enabled in the SM Control register - 1 - 1 - read-only - - - INT_WR - Interrupt Write: -1:Interrupt after buffer was completely and -successfully written -0:Interrupt cleared after first byte of buffer -was read -NOTE:This interrupt is signalled to the reading -side if enabled in the SM Control register - 0 - 1 - read-only - - - - - ACTIVATE - Activate - 0x6 - 8 - 0x00 - 0xC3 - - - LATCH_PDI - Latch Event PDI: -0:No -1:Generate Latch events when PDI issues -a buffer exchange or when PDI -accesses buffer start address - 7 - 1 - read-only - - - LATCH_ECAT - Latch Event ECAT: -0:No -1:Generate Latch event when EtherCAT -master issues a buffer exchange - 6 - 1 - read-only - - - REPEAT - Repeat Request: -A toggle of Repeat Request means that a -mailbox retry is needed (primarily used in -conjunction with ECAT Read Mailbox) - 1 - 1 - read-only - - - EN - SyncManager Enable/Disable: -0:Disable:Access to Memory without -SyncManager control -1:Enable:SyncManager is active and -controls Memory area set in -configuration - 0 - 1 - read-write - - - - - PDI_CTRL - PDI Control - 0x7 - 8 - 0x00 - 0x03 - - - REPEAT_ACK - Repeat Ack: -If this is set to the same value as that set by -Repeat Request, the PDI acknowledges the -execution of a previous set Repeat request. - 1 - 1 - read-write - - - DEACT - Deactivate SyncManager: -Read: -0:Normal operation, SyncManager -activated. -1:SyncManager deactivated and reset. -SyncManager locks access to Memory -area. -Write: -0:Activate SyncManager -1:Request SyncManager deactivation -NOTE:Writing 1 is delayed until the end of the -frame, which is currently processed. - 0 - 1 - read-write - - - - - - 4 - 0x4 - PORT0,PORT1,PORT2,PORT3 - RCV_TIME[%s] - no description available - 0x900 - 32 - 0x00000000 - 0xFFFFFFFF - - - LT - Local time at the beginning of the last receive -frame containing a write access to register -0x0900. - 8 - 24 - read-only - - - REQ - Write: -A write access to register 0x0900 with -BWR or FPWR latches the local time at -the beginning of the receive frame (start -first bit of preamble) at each port. -Write (ESC20, ET1200 exception): -A write access latches the local time at -the beginning of the receive frame at -port 0. It enables the time stamping at -the other ports. -Read: -Local time at the beginning of the last -receive frame containing a write access -to this register. -NOTE:FPWR requires an address match for -accessing this register like any FPWR command. -All write commands with address match will -increment the working counter (e.g., APWR), but -they will not trigger receive time latching. - 0 - 8 - read-only - - - - - SYS_TIME - System Time - 0x910 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - ST - No description available - 0 - 64 - read-write - - - - - RCVT_ECAT_PU - Receive Time ECAT Processing Unit - 0x918 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - LT - Local time at the beginning of a frame (start -first bit of preamble) received at the ECAT -Processing Unit containing a write access to -register 0x0900 -NOTE:E.g., if port 0 is open, this register reflects -the Receive Time Port 0 as a 64 Bit value. -Any valid EtherCAT write access to register -0x0900 triggers latching, not only BWR/FPWR -commands as with register 0x0900. - 0 - 64 - read-only - - - - - SYS_TIME_OFFSET - System Time Offset - 0x920 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - OFFSET - Difference between local time and System -Time. Offset is added to the local time. - 0 - 64 - read-write - - - - - SYS_TIME_DELAY - System Time Delay - 0x928 - 32 - 0x00000000 - 0xFFFFFFFF - - - DLY - Delay between Reference Clock and the -ESC - 0 - 32 - read-write - - - - - SYS_TIME_DIFF - System Time Difference - 0x92c - 32 - 0x00000000 - 0xFFFFFFFF - - - DIFF - 0:Local copy of System Time less than -received System Time -1:Local copy of System Time greater than -or equal to received System Time - 31 - 1 - read-only - - - NUM - Mean difference between local copy of -System Time and received System Time -values -Difference = Received System Time – -local copy of System Time - 0 - 31 - read-only - - - - - SPD_CNT_START - Speed Counter Start - 0x930 - 16 - 0x0000 - 0x7FFF - - - BW - Bandwidth for adjustment of local copy of -System Time (larger values → smaller -bandwidth and smoother adjustment) -A write access resets System Time -Difference (0x092C:0x092F) and Speed -Counter Diff (0x0932:0x0933). -Valid values:0x0080 to 0x3FFF - 0 - 15 - read-write - - - - - SPD_CNT_DIFF - Speed Counter Diff - 0x932 - 16 - 0x0000 - 0xFFFF - - - DIFF - Representation of the deviation between -local clock period and Reference Clock's -clock period (representation:two's -complement) -Range:±(Speed Counter Start – 0x7F) - 0 - 16 - read-only - - - - - SYS_TIME_DIFF_FD - System Time Difference Filter Depth - 0x934 - 8 - 0x00 - 0x0F - - - DEPTH - Filter depth for averaging the received -System Time deviation -IP Core since V2.2.0/V2.02a: -A write access resets System Time -Difference (0x092C:0x092F) - 0 - 4 - read-write - - - - - SPD_CNT_FD - Speed Counter Filter Depth - 0x935 - 8 - 0x00 - 0x0F - - - DEPTH - Filter depth for averaging the clock period -deviation -IP Core since V2.2.0/V2.02a: -A write access resets the internal speed -counter filter - 0 - 4 - read-write - - - - - RCV_TIME_LM - Receive Time Latch Mode - 0x936 - 8 - 0x00 - 0x01 - - - LATCH_MODE - Receive Time Latch Mode: -0:Forwarding mode (used if frames are -entering the ESC at port 0 first): -Receive time stamps of ports 1-3 are -enabled after the write access to -0x0900, so the following frame at ports -1-3 will be time stamped (this is typically -the write frame to 0x0900 coming back -from the network behind the ESC). -1:Reverse mode (used if frames are -entering ESC at port 1-3 first): -Receive time stamps of ports 1-3 are -immediately taken over from the internal -hidden time stamp registers, so the -previous frame entering the ESC at -ports 1-3 will be time stamped when the -write frame to 0x0900 enters port 0 (the -previous frame at ports 1-3 is typically -the write frame to 0x0900 coming from -the master, which will enable time -stamp - 0 - 1 - read-only - - - - - CYC_UNIT_CTRL - Cyclic Unit Control - 0x980 - 8 - 0x00 - 0x31 - - - LATCHI1 - Latch In unit 1: -0:ECAT-controlled -1:PDI-controlled -NOTE:Latch interrupt is routed to ECAT/PDI -depending on this setting - 5 - 1 - read-only - - - LATCHI0 - Latch In unit 0: -0:ECAT-controlled -1:PDI-controlled -NOTE:Latch interrupt is routed to ECAT/PDI -depending on this setting. -Always 1 (PDI-controlled) if System Time is PDIcontrolled. - 4 - 1 - read-only - - - SYNCO - Cyclic Unit and SYNC0 out unit control: -0:ECAT-controlled -1:PDI-controlled - 0 - 1 - read-only - - - - - SYNCO_ACT - SYNC Out Unit Activation - 0x981 - 8 - 0x00 - 0xFF - - - SSDP - SyncSignal debug pulse (Vasily bit): -0:Deactivated -1:Immediately generate one ping only on -SYNC0-1 according to 0x0981[2:1 for -debugging -This bit is self-clearing, always read 0. -All pulses are generated at the same time, -the cycle time is ignored. The configured -pulse length is used. - 7 - 1 - read-write - - - NFC - Near future configuration (approx.): -0:½ DC width future (231 ns or 263 ns) -1:~2.1 sec. future (231 ns) - 6 - 1 - read-write - - - STPC - Start Time plausibility check: -0:Disabled. SyncSignal generation if Start -Time is reached. -1:Immediate SyncSignal generation if -Start Time is outside near future (see -0x0981[6]) - 5 - 1 - read-write - - - EXT - Extension of Start Time Cyclic Operation -(0x0990:0x0993): -0:No extension -1:Extend 32 bit written Start Time to 64 bit - 4 - 1 - read-write - - - AC - Auto-activation by writing Start Time Cyclic -Operation (0x0990:0x0997): -0:Disabled -1:Auto-activation enabled. 0x0981[0] is -set automatically after Start Time is -written. - 3 - 1 - read-write - - - SYNC1_GEN - SYNC1 generation: -0:Deactivated -1:SYNC1 pulse is generated - 2 - 1 - read-write - - - SYNC0_GEN - SYNC0 generation: -0:Deactivated -1:SYNC0 pulse is generated - 1 - 1 - read-write - - - SOUA - Sync Out Unit activation: -0:Deactivated -1:Activated - 0 - 1 - read-write - - - - - PULSE_LEN - Pulse Length of SyncSignals - 0x982 - 16 - 0x0000 - 0xFFFF - - - LEN - Pulse length of SyncSignals (in Units of -10ns) -0:Acknowledge mode:SyncSignal will be -cleared by reading SYNC[1:0] Status -register - 0 - 16 - read-only - - - - - ACT_STAT - Activation Status - 0x984 - 8 - 0x00 - 0x07 - - - CHK_RSLT - Start Time Cyclic Operation (0x0990:0x0997) -plausibility check result when Sync Out Unit -was activated: -0:Start Time was within near future -1:Start Time was out of near future -(0x0981[6]) - 2 - 1 - read-only - - - SYNC1 - SYNC1 activation state: -0:First SYNC1 pulse is not pending -1:First SYNC1 pulse is pending - 1 - 1 - read-only - - - SYNC0 - SYNC0 activation state: -0:First SYNC0 pulse is not pending -1:First SYNC0 pulse is pending - 0 - 1 - read-only - - - - - SYNC0_STAT - SYNC0 Status - 0x98e - 8 - 0x00 - 0x01 - - - ACK - SYNC0 state for Acknowledge mode. -SYNC0 in Acknowledge mode is cleared by -reading this register from PDI, use only in -Acknowledge mode - 0 - 1 - read-write - - - - - SYNC1_STAT - SYNC1 Status - 0x98f - 8 - 0x00 - 0x01 - - - ACK - SYNC1 state for Acknowledge mode. -SYNC1 in Acknowledge mode is cleared by -reading this register from PDI, use only in -Acknowledge mode - 0 - 1 - read-write - - - - - START_TIME_CO - Start Time Cyclic Operation - 0x990 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - ST - Write:Start time (System time) of cyclic -operation in ns -Read:System time of next SYNC0 pulse in -ns - 0 - 64 - read-write - - - - - NXT_SYNC1_PULSE - Next SYNC1 Pulse - 0x998 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - TIME - System time of next SYNC1 pulse in ns - 0 - 64 - read-only - - - - - SYNC0_CYC_TIME - SYNC0 Cycle Time - 0x9a0 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYC - Time between two consecutive SYNC0 -pulses in ns. -0:Single shot mode, generate only one -SYNC0 pulse. - 0 - 32 - read-write - - - - - SYNC1_CYC_TIME - SYNC1 Cycle Time - 0x9a4 - 32 - 0x00000000 - 0xFFFFFFFF - - - CYC - Time between SYNC0 pulse and SYNC1 -pulse in ns - 0 - 32 - read-write - - - - - LATCH0_CTRL - Latch0 Control - 0x9a8 - 8 - 0x00 - 0x03 - - - NEG_EDGE - Latch0 negative edge: -0:Continuous Latch active -1:Single event (only first event active) - 1 - 1 - read-write - - - POS_EDGE - Latch0 positive edge: -0:Continuous Latch active -1:Single event (only first event active) - 0 - 1 - read-write - - - - - LATCH1_CTRL - Latch1 Control - 0x9a9 - 8 - 0x00 - 0x03 - - - NEG_EDGE - Latch1 negative edge: -0:Continuous Latch active -1:Single event (only first event active) - 1 - 1 - read-write - - - POS_EDGE - Latch1 positive edge: -0:Continuous Latch active -1:Single event (only first event active) - 0 - 1 - read-write - - - - - LATCH0_STAT - Latch0 Status - 0x9ae - 8 - 0x00 - 0x07 - - - PIN_STAT - Latch0 pin state - 2 - 1 - read-only - - - NEG_EDGE - Event Latch0 negative edge. -0:Negative edge not detected or -continuous mode -1:Negative edge detected in single event -mode only. -Flag cleared by reading out Latch0 Time -Negative Edge. - 1 - 1 - read-only - - - POS_EDGE - Event Latch0 positive edge. -0:Positive edge not detected or -continuous mode -1:Positive edge detected in single event -mode only. -Flag cleared by reading out Latch0 Time -Positive Edge. - 0 - 1 - read-only - - - - - LATCH1_STAT - Latch1 Status - 0x9af - 8 - 0x00 - 0x07 - - - PIN_STAT - Latch1 pin state - 2 - 1 - read-only - - - NEG_EDGE - Event Latch1 negative edge. -0:Negative edge not detected or -continuous mode -1:Negative edge detected in single event -mode only. -Flag cleared by reading out Latch1 Time -Negative Edge. - 1 - 1 - read-only - - - POS_EDGE - Event Latch1 positive edge. -0:Positive edge not detected or -continuous mode -1:Positive edge detected in single event -mode only. -Flag cleared by reading out Latch1 Time -Positive Edge. - 0 - 1 - read-only - - - - - LATCH0_TIME_PE - Latch0 Time Positive Edge - 0x9b0 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - TIME - System time at the positive edge of the -Latch0 signal. - 0 - 64 - read-write - - - - - LATCH0_TIME_NE - Latch0 Time Negative Edge - 0x9b8 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - TIME - System time at the negative edge of the -Latch0 signal. - 0 - 64 - read-write - - - - - LATCH1_TIME_PE - Latch1 Time Positive Edge - 0x9c0 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - TIME - System time at the positive edge of the -Latch1 signal. - 0 - 64 - read-write - - - - - LATCH1_TIME_NE - Latch1 Time Negative Edge - 0x9c8 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - TIME - System time at the negative edge of the -Latch1 signal. - 0 - 64 - read-write - - - - - ECAT_BUF_CET - EtherCAT Buffer Change Event Time - 0x9f0 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - Local time at the beginning of the frame -which causes at least one SyncManager to -assert an ECAT event - 0 - 32 - read-only - - - - - PDI_BUF_SET - PDI Buffer Start Event Time - 0x9f8 - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - Local time when at least one SyncManager -asserts a PDI buffer start event - 0 - 32 - read-only - - - - - PDI_BUF_CET - PDI Buffer Change Event Time - 0x9fc - 32 - 0x00000000 - 0xFFFFFFFF - - - TIME - Local time when at least one SyncManager -asserts a PDI buffer change event - 0 - 32 - read-only - - - - - PID - Product ID - 0xe00 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - PID - Product ID - 0 - 64 - read-only - - - - - VID - Vendor ID - 0xe08 - 64 - 0x0000000000000000 - 0x00000000FFFFFFFF - - - VID - Vendor ID: -[23-0] Company -[31-24] Department -NOTE:Test Vendor IDs have [31:28]=0xE - 0 - 32 - read-only - - - - - DIO_OUT_DATA - Digital I/O Output Data - 0xf00 - 32 - 0x00000000 - 0xFFFFFFFF - - - OD - Output Data - 0 - 32 - read-only - - - - - GPO - General Purpose Outputs - 0xf10 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - GPOD - General Purpose Output Data - 0 - 64 - read-write - - - - - GPI - General Purpose Inputs - 0xf18 - 64 - 0x0000000000000000 - 0xFFFFFFFFFFFFFFFF - - - GPID - General Purpose Input Data - 0 - 64 - read-only - - - - - USER_RAM_BYTE0 - User Ram Byte 0 - 0xf80 - 8 - 0x00 - 0xFF - - - EXTF - Number of extended feature bits - 0 - 8 - read-write - - - - - USER_RAM_BYTE1 - User Ram Byte 1 - 0xf81 - 8 - 0x00 - 0xFF - - - PRWO - Physical Read/Write Offset (0x0108:0x0109) - 7 - 1 - read-write - - - AEMW - AL Event Mask writable (0x0204:0x0207) - 6 - 1 - read-write - - - GPO - General Purpose Outputs (0x0F10:0x0F17) - 5 - 1 - read-write - - - GPI - General Purpose Inputs (0x0F18:0x0F1F) - 4 - 1 - read-write - - - CSA - Configured Station Alias (0x0012:0x0013) - 3 - 1 - read-write - - - EIM - ECAT Interrupt Mask (0x0200:0x0201) - 2 - 1 - read-write - - - ALSCR - AL Status Code Register (0x0134:0x0135) - 1 - 1 - read-write - - - EDLCR - Extended DL Control Register (0x0102:0x0103) - 0 - 1 - read-write - - - - - USER_RAM_BYTE2 - User Ram Byte 2 - 0xf82 - 8 - 0x00 - 0xEF - - - ESCFG - EEPROM Size configurable (0x0502[7]): -0:EEPROM Size fixed to sizes up to 16 Kbit -1:EEPROM Size configurable - 7 - 1 - read-write - - - EPUPEC - ECAT Processing Unit/PDI Error Counter -(0x030C:0x030D) - 6 - 1 - read-write - - - DCSMET - DC SyncManager Event Times (0x09F0:0x09FF) - 5 - 1 - read-write - - - RESET - Reset (0x0040:0x0041) - 3 - 1 - read-write - - - WP - Write Protection (0x0020:0x0031) - 2 - 1 - read-write - - - WDGCNT - Watchdog counters (0x0442:0x0443) - 1 - 1 - read-write - - - WDW - Watchdog divider writable (0x0400:0x0401) and -Watchdog PDI (0x0410:0x0411) - 0 - 1 - read-write - - - - - USER_RAM_BYTE3 - User Ram Byte 3 - 0xf83 - 8 - 0x00 - 0xF8 - - - RLED - Run LED (DEV_STATE LED) - 7 - 1 - read-write - - - ELDE - Enhanced Link Detection EBUS - 6 - 1 - read-write - - - ELDM - Enhanced Link Detection MII - 5 - 1 - read-write - - - MMI - MII Management Interface (0x0510:0x0515) - 4 - 1 - read-write - - - LLC - Lost Link Counter (0x0310:0x0313) - 3 - 1 - read-write - - - - - USER_RAM_BYTE4 - User Ram Byte 4 - 0xf84 - 8 - 0x00 - 0xE9 - - - LDCM - Link detection and configuration by MI - 7 - 1 - read-write - - - DTLC - DC Time loop control assigned to PDI - 6 - 1 - read-write - - - DSOU - DC Sync Out Unit - 5 - 1 - read-write - - - DLIU - DC Latch In Unit - 3 - 1 - read-write - - - LALED - Link/Activity LED - 0 - 1 - read-write - - - - - USER_RAM_BYTE5 - User Ram Byte 5 - 0xf85 - 8 - 0x00 - 0x27 - - - DDIOR - Disable Digital I/O register (0x0F00:0x0F03) - 5 - 1 - read-write - - - EEU - EEPROM emulation by µController - 2 - 1 - read-write - - - ATS - Automatic TX shift - 1 - 1 - read-write - - - MCPP - MI control by PDI possible - 0 - 1 - read-write - - - - - USER_RAM_BYTE6 - User Ram Byte 6 - 0xf86 - 8 - 0x00 - 0x04 - - - RELEDOR - RUN/ERR LED Override (0x0138:0x0139) - 2 - 1 - read-write - - - - - USER_RAM_BYTE7 - User Ram Byte 7 - 0xf87 - 8 - 0x00 - 0xC8 - - - DCST - DC System Time (0x0910:0x0936) - 7 - 1 - read-write - - - DCRT - DC Receive Times (0x0900:0x090F) - 6 - 1 - read-write - - - DCS1D - DC Sync1 disable - 3 - 1 - read-write - - - - - USER_RAM_BYTE8 - User Ram Byte 8 - 0xf88 - 8 - 0x00 - 0x3D - - - PPDI - PLB PDI - 5 - 1 - read-write - - - OPDI - OPB PDI - 4 - 1 - read-write - - - APDI - Avalon PDI - 3 - 1 - read-write - - - PDICEC - PDI clears error counter - 2 - 1 - read-write - - - DC64 - DC 64 bit - 0 - 1 - read-write - - - - - USER_RAM_BYTE9 - User Ram Byte 9 - 0xf89 - 8 - 0x00 - 0x80 - - - DR - Direct RESET - 7 - 1 - read-write - - - - - USER_RAM_BYTE10 - User Ram Byte 10 - 0xf8a - 8 - 0x00 - 0xCC - - - PDIIR - PDI Information register (0x014E:0x014F) - 7 - 1 - read-write - - - PDIFA - PDI function acknowledge by PDI write - 6 - 1 - read-write - - - APDI - AXI PDI - 3 - 1 - read-write - - - DCL1D - DC Latch1 disable - 2 - 1 - read-write - - - - - USER_RAM_BYTE11 - User Ram Byte 11 - 0xf8b - 8 - 0x00 - 0x08 - - - LEDTST - LED test - 3 - 1 - read-write - - - - - USER_RAM_BYTE14 - User Ram Byte 14 - 0xf8e - 8 - 0x00 - 0xC0 - - - DIOBS - Digital I/O PDI byte size - 6 - 2 - read-write - - - - - USER_RAM_BYTE15 - User Ram Byte 15 - 0xf8f - 8 - 0x00 - 0x1C - - - AUCPDI - Asynchronous µC PDI - 4 - 1 - read-write - - - SSPDI - SPI Slave PDI - 3 - 1 - read-write - - - DIOPDI - Digital I/O PDI - 2 - 1 - read-write - - - - - USER_RAM_BYTE19 - User Ram Byte 19 - 0xf93 - 8 - 0x00 - 0x77 - - - SCP - Security CPLD protection - 6 - 1 - read-write - - - RMII - RMII - 5 - 1 - read-write - - - URGP - Use RGMII GTX_CLK phase shifted clock input - 4 - 1 - read-write - - - CIA - CLK_PDI_EXT is asynchronous - 2 - 1 - read-write - - - IPARO - Individual PHY address read out (0x0510[7:3]) - 1 - 1 - read-write - - - RGMII - RGMII - 0 - 1 - read-write - - - - - PDRAM - Process Data Ram - 0x1000 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Input Data - 0 - 32 - read-write - - - - - PDRAM_ALS - Process Data Ram Alias - 0x10000 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - No description available - 0 - 32 - read-write - - - - - GPR_CFG0 - General Purpose Configure 0 - 0x1f000 - 32 - 0x00001000 - 0x00003009 - - - CLK100_EN - No description available - 13 - 1 - read-write - - - EEPROM_EMU - 1 is EEPROM emulation mode (default) - 12 - 1 - read-write - - - I2C_SCLK_EN - No description available - 3 - 1 - read-write - - - PROM_SIZE - Sets EEPROM size: -0:up to 16 kbit EEPROM -1:32 kbit-4Mbit EEPROM - 0 - 1 - read-write - - - - - GPR_CFG1 - General Purpose Configure 1 - 0x1f004 - 32 - 0x00000000 - 0xE00033C0 - - - SYNC1_IRQ_EN - No description available - 31 - 1 - read-write - - - SYNC0_IRQ_EN - No description available - 30 - 1 - read-write - - - RSTO_IRQ_EN - No description available - 29 - 1 - read-write - - - SYNC1_DMA_EN - No description available - 13 - 1 - read-write - - - SYNC0_DMA_EN - No description available - 12 - 1 - read-write - - - LATCH1_FROM_IO - 0:from NTM - 9 - 1 - read-write - - - LATCH0_FROM_IO - 0:from TRIGGER_MUX - 8 - 1 - read-write - - - RSTO_OVRD - No description available - 7 - 1 - read-write - - - RSTO_OVRD_ENJ - No description available - 6 - 1 - read-write - - - - - GPR_CFG2 - General Purpose Configure 2 - 0x1f008 - 32 - 0x00000000 - 0x33300000 - - - NMII_LINK2_FROM_IO - No description available - 29 - 1 - read-write - - - NMII_LINK2_GPR - No description available - 28 - 1 - read-write - - - NMII_LINK1_FROM_IO - No description available - 25 - 1 - read-write - - - NMII_LINK1_GPR - No description available - 24 - 1 - read-write - - - NMII_LINK0_FROM_IO - No description available - 21 - 1 - read-write - - - NMII_LINK0_GPR - No description available - 20 - 1 - read-write - - - - - PHY_CFG0 - PHY Configure 0 - 0x1f010 - 32 - 0x00000000 - 0x40808080 - - - MAC_SPEED - 1:100M - 30 - 1 - read-write - - - PORT2_RMII_EN - No description available - 23 - 1 - read-write - - - PORT1_RMII_EN - No description available - 15 - 1 - read-write - - - PORT0_RMII_EN - No description available - 7 - 1 - read-write - - - - - PHY_CFG1 - PHY Configure 1 - 0x1f014 - 32 - 0x00000001 - 0x000007FF - - - RMII_REFCLK_SEL - 0:use RXCK as 50M refclk. 1:use TXCK as 50M refclk - 8 - 3 - read-write - - - REFCK_25M_INV - No description available - 7 - 1 - read-write - - - RMII_P2_RXCK_REFCLK_OE - No description available - 6 - 1 - read-write - - - RMII_P1_RXCK_REFCLK_OE - No description available - 5 - 1 - read-write - - - RMII_P0_RXCK_REFCLK_OE - No description available - 4 - 1 - read-write - - - REFCK_25M_OE - No description available - 3 - 1 - read-write - - - RMII_P2_TXCK_REFCLK_OE - No description available - 2 - 1 - read-write - - - RMII_P1_TXCK_REFCLK_OE - No description available - 1 - 1 - read-write - - - RMII_P0_TXCK_REFCLK_OE - No description available - 0 - 1 - read-write - - - - - GPIO_CTRL - GPIO Output Enable - 0x1f020 - 32 - 0x00000000 - 0xC0003F1F - - - SW_LATCH_GPI - if gpi_trig_sel is set to 4'b1001, setting this bit will latch GPI to gpi_reg0/1 - 31 - 1 - write-only - - - SW_LATCH_GPO - if gpo_trig_sel is set to 4'b1001, setting this bit will latch GPO to gpo_reg0/1 - 30 - 1 - write-only - - - GPI_OVERRIDE_EN - set this bit will use GPI from the software register gpi_override0/1 -clr to use GPI from pad directly - 13 - 1 - read-write - - - GPI_TRIG_EN - use gpi_trig_sel can select the trigger event to latch GPI signal(from reg or pad) -set to use triggered signal; -clr to use signals direclty(from reg or pad) -assign pdi_gpi = gpi_trig_en ? gpi_reg : - (gpi_override_en ? gpi_override :pad_di_ecat_gpi); - 12 - 1 - read-write - - - GPI_TRIG_SEL - select the trigger signal to latch GPI. -0000: SOF; 0001: EOF; 0010: pos of SYNC0; 0011: pos of SYNC1; -0100: pos of LATCH0; 0101: pos of LATCH1; 0110: neg of LATCH0; 0111: neg of LATCH1 -1000: wdog trigger; 1001: sw set gpio_ctrl[31]; others no trigger - 8 - 4 - read-write - - - GPO_TRIG_EN - use gpo_trig_sel can select the trigger event to latch GPO signal(from core) -set to use triggered signal; -clr to use GPO signals direclty(from reg or pad) - 4 - 1 - read-write - - - GPO_TRIG_SEL - select the trigger signal to latch GPO. -0000: SOF; 0001: EOF; 0010: pos of SYNC0; 0011: pos of SYNC1; -0100: pos of LATCH0; 0101: pos of LATCH1; 0110: neg of LATCH0; 0111: neg of LATCH1 -1000: wdog trigger; 1001: sw set gpio_ctrl[30]; others no trigger - 0 - 4 - read-write - - - - - GPI_OVERRIDE0 - GPI low word Override value - 0x1f030 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR_OVERRIDE_LOW - No description available - 0 - 32 - read-write - - - - - GPI_OVERRIDE1 - GPI high word Override value - 0x1f034 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR_OVERRIDE_HIGH - No description available - 0 - 32 - read-write - - - - - GPO_REG0 - GPO low word read value - 0x1f038 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-only - - - - - GPO_REG1 - GPO high word read value - 0x1f03c - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-only - - - - - GPI_REG0 - GPI low word read value - 0x1f040 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-only - - - - - GPI_REG1 - GPI high word read value - 0x1f044 - 32 - 0x00000000 - 0xFFFFFFFF - - - VALUE - No description available - 0 - 32 - read-only - - - - - GPR_STATUS - global status register - 0x1f060 - 32 - 0x00000000 - 0xFFFF037F - - - NLINK2_PADSEL - No description available - 28 - 4 - read-only - - - NLINK1_PADSEL - No description available - 24 - 4 - read-only - - - NLINK0_PADSEL - No description available - 20 - 4 - read-only - - - PDI_SOF - No description available - 19 - 1 - read-only - - - PDI_EOF - No description available - 18 - 1 - read-only - - - PDI_WD_TRIGGER - No description available - 17 - 1 - read-only - - - PDI_WD_STATE - No description available - 16 - 1 - read-only - - - SYNC_OUT1 - No description available - 9 - 1 - read-only - - - SYNC_OUT0 - No description available - 8 - 1 - read-only - - - LED_STATE_RUN - No description available - 6 - 1 - read-only - - - LED_ERR - No description available - 5 - 1 - read-only - - - LED_RUN - No description available - 4 - 1 - read-only - - - DEV_STATE - No description available - 3 - 1 - read-only - - - LINK_ACT - No description available - 0 - 3 - read-only - - - - - 9 - 0x4 - CTR0,CTR1,CTR2,CTR3,CTR4,CTR5,CTR6,CTR7,CTR8 - IO_CFG[%s] - no description available - 0x1f080 - 32 - 0x00000000 - 0x0000001F - - - INVERT - 1:invert the IO - 4 - 1 - read-write - - - FUNC_ALT - IO usage: -0:NMII_LINK0 -1:NMII_LINK1 -2:NMII_LINK2 -3:LINK_ACT0 -4:LINK_ACT1 -5:LINK_ACT2 -6:LED_RUN -7:LED_ERR -8:RESET_OUT - 0 - 4 - read-write - - - - - - - FEMC - FEMC - FEMC - 0xf300c000 - - 0x0 - 0x154 - registers - - - - CTRL - Control Register - 0x0 - 32 - 0x00000000 - 0x1FFF0007 - - - BTO - Bus timeout cycles -AXI Bus timeout cycle is as following (255*(2^BTO)): -00000b - 255*1 -00001-11110b - 255*2 - 255*2^30 -11111b - 255*2^31 - 24 - 5 - read-write - - - CTO - Command Execution timeout cycles -When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is -generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is -CTO*1024 cycle. - 16 - 8 - read-write - - - DQS - DQS (read strobe) mode -0b - Dummy read strobe loopbacked internally -1b - Dummy read strobe loopbacked from DQS pad - 2 - 1 - read-write - - - DIS - Module Disable -0b - Module enabled -1b - Module disabled - 1 - 1 - read-write - - - RST - Software Reset -Reset all internal logic in SEMC except configuration register - 0 - 1 - read-write - - - - - IOCTRL - IO Mux Control Register - 0x4 - 32 - 0x00000000 - 0x000000F0 - - - IO_CSX - IO_CSX output selection -0001b - SDRAM CS1 -0110b - SRAM CE# - 4 - 4 - read-write - - - - - BMW0 - Bus (AXI) Weight Control Register 0 - 0x8 - 32 - 0x00000000 - 0x00FFFFFF - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - SH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - BMW1 - Bus (AXI) Weight Control Register 1 - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - BR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current -executing command. - 24 - 8 - read-write - - - RWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is -same as current executing command with read/write operation switch. - 16 - 8 - read-write - - - PH - Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is -same as current executing command without read/write operation switch. - 8 - 8 - read-write - - - AGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is -multiplied by WAGE to get weight score. - 4 - 4 - read-write - - - QOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator -for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS -is multiplied by WQOS to get weight score. - 0 - 4 - read-write - - - - - 3 - 0x4 - BASE0,BASE1,rsv2,rsv3,rsv4,rsv5,BASE6 - BR[%s] - no description available - 0x10 - 32 - 0x00000000 - 0xFFFFF03F - - - BASE - Base Address -This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low -position 12 bits are all zero. - 12 - 20 - read-write - - - SIZE - Memory size -00000b - 4KB -00001b - 8KB -00010b - 16KB -00011b - 32KB -00100b - 64KB -00101b - 128KB -00110b - 256KB -00111b - 512KB -01000b - 1MB -01001b - 2MB -01010b - 4MB -01011b - 8MB -01100b - 16MB -01101b - 32MB -01110b - 64MB -01111b - 128MB -10000b - 256MB -10001b - 512MB -10010b - 1GB -10011b - 2GB -10100-11111b - 4GB - 1 - 5 - read-write - - - VLD - Valid - 0 - 1 - read-write - - - - - INTEN - Interrupt Enable Register - 0x38 - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI BUS error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 3 - 1 - read-write - - - AXICMDERR - AXI command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 2 - 1 - read-write - - - IPCMDERR - IP command error interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 1 - 1 - read-write - - - IPCMDDONE - IP command done interrupt enable -0b - Interrupt is disabled -1b - Interrupt is enabled - 0 - 1 - read-write - - - - - INTR - Interrupt Status Register - 0x3c - 32 - 0x00000000 - 0x0000000F - - - AXIBUSERR - AXI bus error interrupt -AXI Bus error interrupt is generated in following cases: -• AXI address is invalid -• AXI 8-bit or 16-bit WRAP write/read - 3 - 1 - write-only - - - AXICMDERR - AXI command error interrupt -AXI command error interrupt is generated when AXI command execution timeout. - 2 - 1 - write-only - - - IPCMDERR - IP command error done interrupt -IP command error interrupt is generated in following case: -• IP Command Address target invalid device space -• IP Command Code unsupported -• IP Command triggered when previous command - 1 - 1 - write-only - - - IPCMDDONE - IP command normal done interrupt - 0 - 1 - write-only - - - - - SDRCTRL0 - SDRAM Control Register 0 - 0x40 - 32 - 0x00000000 - 0x00004FFB - - - BANK2 - 2 Bank selection bit -0b - SDRAM device has 4 banks. -1b - SDRAM device has 2 banks. - 14 - 1 - read-write - - - CAS - CAS Latency -00b - 1 -01b - 1 -10b - 2 -11b - 3 - 10 - 2 - read-write - - - COL - Column address bit number -00b - 12 bit -01b - 11 bit -10b - 10 bit -11b - 9 bit - 8 - 2 - read-write - - - COL8 - Column 8 selection bit -0b - Column address bit number is decided by COL field. -1b - Column address bit number is 8. COL field is ignored. - 7 - 1 - read-write - - - BURSTLEN - Burst Length -000b - 1 -001b - 2 -010b - 4 -011b - 8 -100b - 8 -101b - 8 -110b - 8 -111b - 8 - 4 - 3 - read-write - - - HIGHBAND - high band select -0: use data[15:0] for 16bit SDRAM; -1: use data[31:16] for 16bit SDRAM; -only used when Port Size is 16bit(PORTSZ=01b) - 3 - 1 - read-write - - - PORTSZ - Port Size -00b - 8bit -01b - 16bit -10b - 32bit - 0 - 2 - read-write - - - - - SDRCTRL1 - SDRAM Control Register 1 - 0x44 - 32 - 0x00000000 - 0x00FFFFFF - - - ACT2PRE - ACT to Precharge minimum time -It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - 20 - 4 - read-write - - - CKEOFF - CKE OFF minimum time -It is promised clock suspend last at leat CKEOFF+1 clock cycles. - 16 - 4 - read-write - - - WRC - Write recovery time -It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - 13 - 3 - read-write - - - RFRC - Refresh recovery time -It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - 8 - 5 - read-write - - - ACT2RW - ACT to Read/Write wait time -It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - 4 - 4 - read-write - - - PRE2ACT - PRECHARGE to ACT/Refresh wait time -It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - 0 - 4 - read-write - - - - - SDRCTRL2 - SDRAM Control Register 2 - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - ITO - SDRAM Idle timeout -It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is -considered idle when there is no AXI Bus transfer and no SDRAM command pending. -00000000b - IDLE timeout period is 256*Prescale period. -00000001-11111111b - IDLE timeout period is ITO*Prescale period. - 24 - 8 - read-write - - - ACT2ACT - ACT to ACT wait time -It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This -could help to meet tRRD timing requirement by SDRAM device. - 16 - 8 - read-write - - - REF2REF - Refresh to Refresh wait time -It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. -This could help to meet tRFC timing requirement by SDRAM device. - 8 - 8 - read-write - - - SRRC - Self Refresh Recovery time -It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - 0 - 8 - read-write - - - - - SDRCTRL3 - SDRAM Control Register 3 - 0x4c - 32 - 0x00000000 - 0xFFFFFF0F - - - UT - Refresh urgent threshold -Internal refresh request is generated on every Refresh period. Before internal request timer count up to -urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh -request is handled in lower priority than any pending AXI command or IP command to SDRAM device. -When internal request timer count up to this urgent threshold, refresh request is considered as urgent -refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP -command to SDRAM device. -NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as -urgent refresh request. -Refresh urgent threshold is as follwoing: -00000000b - 256*Prescaler period -00000001-11111111b - UT*Prescaler period - 24 - 8 - read-write - - - RT - Refresh timer period -Refresh timer period is as following: -00000000b - 256*Prescaler period -00000001-11111111b - RT*Prescaler period - 16 - 8 - read-write - - - PRESCALE - Prescaler timer period -Prescaler timer period is as following: -00000000b - 256*16 clock cycles -00000001-11111111b - PRESCALE*16 clock cycles - 8 - 8 - read-write - - - REBL - Refresh burst length -It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The -number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. -000b - 1 -001b - 2 -010b - 3 -011b - 4 -100b - 5 -101b - 6 -110b - 7 -111b - 8 - 1 - 3 - read-write - - - REN - Refresh enable - 0 - 1 - read-write - - - - - SRCTRL0 - SRAM control register 0 - 0x70 - 32 - 0x00000000 - 0x00000F01 - - - ADVH - ADV hold state -0b - ADV is high during address hold state -1b - ADV is low during address hold state - 11 - 1 - read-write - - - ADVP - ADV polarity -0b - ADV is active low -1b - ADV is active high - 10 - 1 - read-write - - - ADM - address data mode -00b - address and data MUX mode -11b - address and data non-MUX mode - 8 - 2 - read-write - - - PORTSZ - port size -0b - 8bit -1b - 16bit - 0 - 1 - read-write - - - - - SRCTRL1 - SRAM control register 1 - 0x74 - 32 - 0x00000000 - 0xFFFFFFFF - - - OEH - OE high time, is OEH+1 clock cycles - 28 - 4 - read-write - - - OEL - OE low time, is OEL+1 clock cycles - 24 - 4 - read-write - - - WEH - WE high time, is WEH+1 clock cycles - 20 - 4 - read-write - - - WEL - WE low time, is WEL+1 clock cycles - 16 - 4 - read-write - - - AH - Address hold time, is AH+1 clock cycles - 12 - 4 - read-write - - - AS - Address setup time, is AS+1 clock cycles - 8 - 4 - read-write - - - CEH - Chip enable hold time, is CEH+1 clock cycles - 4 - 4 - read-write - - - CES - Chip enable setup time, is CES+1 clock cycles - 0 - 4 - read-write - - - - - SADDR - IP Command Control Register 0 - 0x90 - 32 - 0x00000000 - 0xFFFFFFFF - - - SA - Slave address - 0 - 32 - read-write - - - - - DATSZ - IP Command Control Register 1 - 0x94 - 32 - 0x00000000 - 0x00000007 - - - DATSZ - Data Size in Byte -When IP command is not a write/read operation, DATSZ field would be ignored. -000b - 4 -001b - 1 -010b - 2 -011b - 3 -100b - 4 -101b - 4 -110b - 4 -111b - 4 - 0 - 3 - read-write - - - - - BYTEMSK - IP Command Control Register 2 - 0x98 - 32 - 0x00000000 - 0x0000000F - - - BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) -0b - Byte Unmasked -1b - Byte Masked - 3 - 1 - read-write - - - BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) -0b - Byte Unmasked -1b - Byte Masked - 2 - 1 - read-write - - - BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) -0b - Byte Unmasked -1b - Byte Masked - 1 - 1 - read-write - - - BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) -0b - Byte Unmasked -1b - Byte Masked - 0 - 1 - read-write - - - - - IPCMD - IP Command Register - 0x9c - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory -device is selected by BRx settings and IPCR0 registers. - 16 - 16 - write-only - - - CMD - SDRAM Commands: -• 0x8: READ -• 0x9: WRITE -• 0xA: MODESET -• 0xB: ACTIVE -• 0xC: AUTO REFRESH -• 0xD: SELF REFRESH -• 0xE: PRECHARGE -• 0xF: PRECHARGE ALL -• Others: RSVD -NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - 0 - 16 - read-write - - - - - IPTX - TX DATA Register - 0xa0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - IPRX - RX DATA Register - 0xb0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DAT - Data - 0 - 32 - read-write - - - - - STAT0 - Status Register 0 - 0xc0 - 32 - 0x00000000 - 0x00000001 - - - IDLE - Indicating whether it is in IDLE state. -When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no -pending device access. - 0 - 1 - read-only - - - - - DLYCFG - Delay Line Config Register - 0x150 - 32 - 0x00000000 - 0x0000203F - - - OE - delay clock output enable, should be set after setting DLYEN and DLYSEL - 13 - 1 - read-write - - - DLYSEL - delay line select, 0 for 1 cell, 31 for all 32 cells - 1 - 5 - read-write - - - DLYEN - delay line enable - 0 - 1 - read-write - - - - - - - FFA - FFA - FFA - 0xf3108000 - - 0x0 - 0x48 - registers - - - - CTRL - No description available - 0x0 - 32 - 0x00000000 - 0x80000001 - - - SFTRST - software reset the module if asserted to be 1. -EN is only active after this bit is zero. - 31 - 1 - read-write - - - EN - Asserted to enable the module - 0 - 1 - read-write - - - - - STATUS - No description available - 0x4 - 32 - 0x00000000 - 0x000003FF - - - FP_NAN - Ored together by ( FP_ST[IN_NAN] & FP_CTRL[IN_NAN_IE] ) | ( FP_ST[COEF_NAN] & FP_CTRL[COEF_NAN_IE] ) - 9 - 1 - read-only - - - FP_SAT - Ored together by ( FP_ST[IN_SAT] & FP_CTRL[IN_SAT_IE] ) | ( FP_ST[COEF_SAT] & FP_CTRL[COEF_SAT_IE] ) - 8 - 1 - read-only - - - FIR_OV - FIR Overflow err - 7 - 1 - write-only - - - FFT_OV - FFT Overflow Err - 6 - 1 - write-only - - - WR_ERR - AXI Data Write Error - 5 - 1 - write-only - - - RD_NXT_ERR - AXI Read Bus Error for NXT DATA - 4 - 1 - write-only - - - RD_ERR - AXI Data Read Error - 3 - 1 - write-only - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - write-only - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - write-only - - - - - INT_EN - No description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - WRSV1 - Reserved - 8 - 24 - read-write - - - FIR_OV - FIR Overflow err - 7 - 1 - read-write - - - FFT_OV - FFT Overflow Err - 6 - 1 - read-write - - - WR_ERR - Enable Data Write Error interrupt - 5 - 1 - read-write - - - RD_NXT_ERR - Enable Read Bus Error for NXT DATA interrupt - 4 - 1 - read-write - - - RD_ERR - Enable Data Read Error interrupt - 3 - 1 - read-write - - - NXT_CMD_RD_DONE - Indicate that next command sequence is already read into the module. - 1 - 1 - read-write - - - OP_CMD_DONE - Indicate that operation cmd is done, and data are available in system memory. - 0 - 1 - read-write - - - - - FP_CTRL - No description available - 0x10 - 32 - 0x00000000 - 0xBFFFFFFF - - - IN_SAT_IE - IN_SAT interrupt enable - 31 - 1 - read-write - - - COEF_SAT_IE - COEF_SAT interrupt enable - 29 - 1 - read-write - - - IN_NAN_IE - IN_NAN interrupt enable - 28 - 1 - read-write - - - COEF_NAN_IE - COEF_NAN interrupt enable - 27 - 1 - read-write - - - EXP_ST_SEL - 2'b00: exp for input data -2'b01: exp for output data -2'b10: exp for coef data - 25 - 2 - read-write - - - OPT_BIAS_EXP - Asserted to use biased exp as exp input and exp output - 24 - 1 - read-write - - - COEF_MAX - The coef max exp for float. When used as float input, this field must be configured. The absolute value of coefficients should be smalller than pow(2, (COEF_MAX+1)). So this suggested value is (ceil(log2(fabs(coef[])))-1). - 16 - 8 - read-write - - - OUT_MAX - The output max exp for float. When used as float output, this field must be configured. The absolute value of output data should be smalller than pow(2, (OUT_MAX+1)). So this suggested value is (ceil(log2(fabs(out[])))-1). - 8 - 8 - read-write - - - IN_MAX - The input max exp for float. When used as float input, this field must be configured. The absolute value of input data should be smalller than pow(2, (IN_MAX+1)). So this suggested value is (ceil(log2(fabs(in[])))-1). - 0 - 8 - read-write - - - - - FP_ST - No description available - 0x14 - 32 - 0x00000000 - 0xB800FFFF - - - IN_SAT - the float input is saturated when converted from float to fix due to small FLT_CTRL[IN_MAX]. - 31 - 1 - write-only - - - COEF_SAT - the float coef is saturated when converted from float to fix due to small FLT_CTRL[COEF_MAX]. - 29 - 1 - write-only - - - IN_NAN - IN_NAN found - 28 - 1 - write-only - - - COEF_NAN - COEF_NAN found - 27 - 1 - write-only - - - EXP_MAX - The max exp for float - 8 - 8 - read-only - - - EXP_MIN - The min exp for float - 0 - 8 - read-only - - - - - OP_CTRL - No description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - NXT_ADDR - The address for the next command. -It will be processed after CUR_CMD is executed and done.. - 2 - 30 - read-write - - - NXT_EN - Whether NXT_CMD is enabled. -Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - 1 - 1 - read-write - - - EN - Whether CUR_CMD is enabled. -Asserted to enable the CUR_CMD - 0 - 1 - read-write - - - - - OP_CMD - No description available - 0x24 - 32 - 0x00000000 - 0x01FFFEFF - - - CONJ_C - asserted to have conjuate value for coefs in computation - 24 - 1 - read-write - - - CMD - The Command Used: -0: FIR -2: FFT -Others: Reserved - 18 - 6 - read-write - - - OUTD_TYPE - Output data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 15 - 3 - read-write - - - COEF_TYPE - Coef data type (used for FIR): -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 12 - 3 - read-write - - - IND_TYPE - Input data type: -0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 -4:complex sp float 5: real sp float - 9 - 3 - read-write - - - NXT_CMD_LEN - The length of nxt commands in 32-bit words - 0 - 8 - read-write - - - - - OP_REG0 - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0x00003FFF - - - FIR_COEF_TAPS - Length of FIR coefs （max 256） - 0 - 14 - read-write - - - - - OP_FFT_MISC - No description available - UNION_28 - 0x28 - 32 - 0x00000000 - 0x000007FF - - - FFT_LEN - FFT length -0:8, -..., -n:2^(3+n) - 7 - 4 - read-write - - - IFFT - Asserted to indicate IFFT - 6 - 1 - read-write - - - TMP_BLK - Memory block for indata. Should be assigned as 1 - 2 - 2 - read-write - - - IND_BLK - Memory block for indata. Should be assigned as 0 - 0 - 2 - read-write - - - - - OP_REG1 - No description available - UNION_2C - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_MISC1 - No description available - UNION_2C - 0x2c - 32 - 0x00000000 - 0x003FFFFF - - - OUTD_MEM_BLK - Should be assigned as 0 - 20 - 2 - read-write - - - COEF_MEM_BLK - Should be assigned as 1 - 18 - 2 - read-write - - - IND_MEM_BLK - Should be assigned as 2 - 16 - 2 - read-write - - - FIR_DATA_TAPS - The input data data length - 0 - 16 - read-write - - - - - OP_REG2 - No description available - UNION_30 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FFT_INRBUF - No description available - UNION_30 - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG3 - No description available - UNION_34 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_INBUF - No description available - UNION_34 - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The input data buffer pointer - 0 - 32 - read-write - - - - - OP_REG4 - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_COEFBUF - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The coef buf pointer - 0 - 32 - read-write - - - - - OP_FFT_OUTRBUF - No description available - UNION_38 - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output (real) data buffer pointer - 0 - 32 - read-write - - - - - OP_REG5 - No description available - UNION_3C - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_FIR_OUTBUF - No description available - UNION_3C - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - LOC - The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - 0 - 32 - read-write - - - - - OP_REG6 - No description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - OP_REG7 - No description available - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CT - Contents - 0 - 32 - read-write - - - - - - - SDP - SDP - SDP - 0xf3140000 - - 0x0 - 0x60 - registers - - - - SDPCR - SDP control register - 0x0 - 32 - 0x30000000 - 0xFFFE0101 - - - SFTRST - soft reset. -Write 1 then 0, to reset the SDP block. - 31 - 1 - read-write - - - CLKGAT - Clock Gate for the SDP main logic. -Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - 30 - 1 - read-write - - - CIPDIS - Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. -1, Cipher is disabled in this chip. -0, Cipher is enabled in this chip. - 29 - 1 - read-only - - - HASDIS - HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. -1, HASH is disabled in this chip. -0, HASH is enabled in this chip. - 28 - 1 - read-only - - - CIPHEN - Cipher Enablement, controlled by SW. -1, Cipher is Enabled. -0, Cipher is Disabled. - 23 - 1 - read-write - - - HASHEN - HASH Enablement, controlled by SW. -1, HASH is Enabled. -0, HASH is Disabled. - 22 - 1 - read-write - - - MCPEN - Memory Copy Enablement, controlled by SW. -1, Memory copy is Enabled. -0, Memory copy is Disabled. - 21 - 1 - read-write - - - CONFEN - Constant Fill to memory, controlled by SW. -1, Constant fill is Enabled. -0, Constant fill is Disabled. - 20 - 1 - read-write - - - DCRPDI - Decryption Disable bit, Write to 1 to disable the decryption. - 19 - 1 - read-write - - - TSTPKT0IRQ - Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - 17 - 1 - read-write - - - RDSCEN - when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) -when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - 8 - 1 - read-write - - - INTEN - Interrupt Enablement, controlled by SW. -1, SDP interrupt is enabled. -0, SDP interrupt is disabled. - 0 - 1 - read-write - - - - - MODCTRL - Mod control register. - 0x4 - 32 - 0x00000000 - 0xFFFFF7FF - - - AESALG - AES algorithem selection. -0x0 = AES 128; -0x1 = AES 256; -0x8 = SM4； -Others, reserved. - 28 - 4 - read-write - - - AESMOD - AES mode selection. -0x0 = ECB; -0x1 = CBC; -Others, reserved. - 24 - 4 - read-write - - - AESKS - AES Key Selection. -These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: -0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. -0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -.... -0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. -0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. -0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. -0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. -0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. -0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. -0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. -0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. -0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. -0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. -0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. -0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. -0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. -0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. -Other values, reserved. - 18 - 6 - read-write - - - AESDIR - AES direction -1x1, AES Decryption -1x0, AES Encryption. - 16 - 1 - read-write - - - HASALG - HASH Algorithem selection. -0x0 SHA1 — -0x1 CRC32 — -0x2 SHA256 — - 12 - 4 - read-write - - - HASCHK - HASH Check Enable Bit. -1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; -1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. -For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - 10 - 1 - read-write - - - HASOUT - When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. -0 INPUT HASH -1 OUTPUT HASH - 9 - 1 - read-write - - - DINSWP - Decide whether the SDP byteswaps the input data (big-endian data); -When all bits are set, the data is assumed to be in the big-endian format - 4 - 2 - read-write - - - DOUTSWP - Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - 2 - 2 - read-write - - - KEYSWP - Decide whether the SDP byteswaps the Key (big-endian data). -When all bits are set, the data is assumed to be in the big-endian format - 0 - 2 - read-write - - - - - PKTCNT - packet counter registers. - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - CNTVAL - This read-only field shows the current (instantaneous) value of the packet counter - 16 - 8 - read-only - - - CNTINCR - The value written to this field is added to the spacket count. - 0 - 8 - read-write - - - - - STA - Status Registers - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - TAG - packet tag. - 24 - 8 - read-only - - - IRQ - interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - 23 - 1 - write-only - - - CHN1PKT0 - the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - 20 - 1 - write-only - - - AESBSY - AES Busy - 19 - 1 - read-only - - - HASBSY - Hashing Busy - 18 - 1 - read-only - - - PKTCNT0 - Packet Counter registers reachs to ZERO now. - 17 - 1 - write-only - - - PKTDON - Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - 16 - 1 - write-only - - - ERRSET - Working mode setup error. - 5 - 1 - write-only - - - ERRPKT - Packet head access error, or status update error. - 4 - 1 - write-only - - - ERRSRC - Source Buffer Access Error - 3 - 1 - write-only - - - ERRDST - Destination Buffer Error - 2 - 1 - write-only - - - ERRHAS - Hashing Check Error - 1 - 1 - write-only - - - ERRCHAIN - buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - 0 - 1 - write-only - - - - - KEYADDR - Key Address - 0x10 - 32 - 0x00000040 - 0xFFFFFFFF - - - INDEX - To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. -Key index pointer. The valid indices are 0-[number_keys]. -In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - 16 - 8 - read-write - - - SUBWRD - Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field -increments; To write a key, the software must first write the desired key index/subword to this register. - 0 - 2 - read-write - - - - - KEYDAT - Key Data - 0x14 - 32 - 0x00000030 - 0xFFFFFFFF - - - KEYDAT - This register provides the write access to the key/key subword specified by the key index register. -Writing this location updates the selected subword for the key located at the index -specified by the key index register. The write also triggers the SUBWORD field of the -KEY register to increment to the next higher word in the key - 0 - 32 - read-write - - - - - 4 - 0x4 - CIPHIV0,CIPHIV1,CIPHIV2,CIPHIV3 - CIPHIV[%s] - no description available - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - CIPHIV - cipher initialization vector. - 0 - 32 - read-write - - - - - 8 - 0x4 - HASWRD0,HASWRD1,HASWRD2,HASWRD3,HASWRD4,HASWRD5,HASWRD6,HASWRD7 - HASWRD[%s] - no description available - 0x28 - 32 - 0x00000030 - 0xFFFFFFFF - - - HASWRD - Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. -If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - 0 - 32 - read-write - - - - - CMDPTR - Command Pointer - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - CMDPTR - current command addresses the register points to the multiword -descriptor that is to be executed (or is currently being executed) - 0 - 32 - read-write - - - - - NPKTPTR - Next Packet Address Pointer - 0x4c - 32 - 0x00000000 - 0xFFFFFFFF - - - NPKTPTR - Next Packet Address Pointer - 0 - 32 - read-write - - - - - PKTCTL - Packet Control Registers - 0x50 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTTAG - packet tag - 24 - 8 - read-write - - - CIPHIV - Load Initial Vector for the AES in this packet. - 6 - 1 - read-write - - - HASFNL - Hash Termination packet - 5 - 1 - read-write - - - HASINI - Hash Initialization packat - 4 - 1 - read-write - - - CHAIN - whether the next command pointer register must be loaded into the channel's current descriptor -pointer. - 3 - 1 - read-write - - - DCRSEMA - whether the channel's semaphore must be decremented at the end of the current operation. -When the semaphore reaches a value of zero, no more operations are issued from the channel. - 2 - 1 - read-write - - - PKTINT - Reflects whether the channel must issue an interrupt upon the completion of the packet - 1 - 1 - read-write - - - - - PKTSRC - Packet Memory Source Address - 0x54 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTSRC - Packet Memory Source Address - 0 - 32 - read-write - - - - - PKTDST - Packet Memory Destination Address - 0x58 - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTDST - Packet Memory Destination Address - 0 - 32 - read-write - - - - - PKTBUF - Packet buffer size. - 0x5c - 32 - 0x00000000 - 0xFFFFFFFF - - - PKTBUF - No description available - 0 - 32 - read-write - - - - - - - PSEC - PSEC - PSEC - 0xf3144000 - - 0x0 - 0x18 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x000300F0 - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - PMIC_FAIL - PMIC secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 7 - 1 - read-write - - - PMIC_NSC - PMIC secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 6 - 1 - read-write - - - PMIC_SEC - PMIC secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 5 - 1 - read-write - - - PMIC_INS - PMIC secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 4 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF000C - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - PMIC_ESC_NSC - PMIC is escalating non-secure event - 3 - 1 - read-only - - - PMIC_ESC_SEC - PMIC is escalting secure event - 2 - 1 - read-only - - - - - LIFECYCLE - Lifecycle - 0x14 - 32 - 0x00000000 - 0x000000FF - - - LIFECYCLE - lifecycle status, -bit7: lifecycle_debate, -bit6: lifecycle_scribe, -bit5: lifecycle_no_ret, -bit4: lifecycle_return, -bit3: lifecycle_secure, -bit2: lifecycle_nonsec, -bit1: lifecycle_create, -bit0: lifecycle_unknow - 0 - 8 - read-only - - - - - - - PMON - PMON - PMON - 0xf3148000 - - 0x0 - 0x48 - registers - - - - 4 - 0x8 - glitch0,glitch1,clock0,clock1 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - IRQ_FLAG - No description available - 0x40 - 32 - 0x00000000 - 0x0000000F - - - FLAG - interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag -0: no monitor interrupt -1: monitor interrupt happened - 0 - 4 - read-write - - - - - IRQ_ENABLE - No description available - 0x44 - 32 - 0x00000000 - 0x0000000F - - - ENABLE - interrupt enable, each bit represents for one monitor -0: monitor interrupt disabled -1: monitor interrupt enabled - 0 - 4 - read-write - - - - - - - RNG - RNG - RNG - 0xf314c000 - - 0x0 - 0x40 - registers - - - - CMD - Command Register - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SFTRST - Soft Reset, Perform a software reset of the RNG This bit is self-clearing. -0 Do not perform a software reset. -1 Software reset - 6 - 1 - read-write - - - CLRERR - Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. -0 Do not clear the errors and the interrupt. -1 Clear the errors and the interrupt. - 5 - 1 - read-write - - - CLRINT - Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. -0 Do not clear the interrupt. -1 Clear the interrupt - 4 - 1 - read-write - - - GENSD - Generate Seed, when both ST and GS triggered, ST first and GS next. - 1 - 1 - read-write - - - SLFCHK - Self Test, when both ST and GS triggered, ST first and GS next. - 0 - 1 - read-write - - - - - CTRL - Control Register - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - MIRQERR - Mask Interrupt Request for Error - 6 - 1 - read-write - - - MIRQDN - Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: -• Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). -• Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - 5 - 1 - read-write - - - AUTRSD - Auto Reseed - 4 - 1 - read-write - - - FUFMOD - FIFO underflow response mode -00 Return all zeros and set the ESR[FUFE]. -01 Return all zeros and set the ESR[FUFE]. -10 Generate the bus transfer error -11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - 0 - 2 - read-write - - - - - STA - Status Register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SCPF - Self Check Pass Fail - 21 - 3 - read-only - - - FUNCERR - Error was detected, check ESR register for details - 16 - 1 - read-only - - - FSIZE - Fifo Size, it is 5 in this design. - 12 - 4 - read-only - - - FRNNU - Fifo Level, Indicates the number of random words currently in the output FIFO - 8 - 4 - read-only - - - NSDDN - New seed done. - 6 - 1 - read-only - - - FSDDN - 1st Seed done -When "1", Indicates that the RNG generated the first seed. - 5 - 1 - read-only - - - SCDN - Self Check Done -Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is -initiated by setting the CMD[ST]. -0 Self test not completed -1 Completed a self test since the last reset. - 4 - 1 - read-only - - - RSDREQ - Reseed needed -Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or -automatically if the CTRL[ARS] is set. - 3 - 1 - read-only - - - IDLE - Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - 2 - 1 - read-only - - - BUSY - when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - 1 - 1 - read-only - - - - - ERR - Error Registers - 0xc - 32 - 0x00000000 - 0xFFFFFF3F - - - FUFE - FIFO access error(underflow) - 5 - 1 - read-only - - - SCKERR - Self-test error -Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a -hardware reset or by writing 1 to the CMD[CE] - 3 - 1 - read-only - - - - - FO2B - FIFO out to bus/cpu - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2B - SW read the FIFO output. - 0 - 32 - read-only - - - - - 8 - 0x4 - FO2S0,FO2S1,FO2S2,FO2S3,FO2S4,FO2S5,FO2S6,FO2S7 - R2SK[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - FO2S0 - FIFO out to KMAN, will be SDP engine key. - 0 - 32 - read-only - - - - - - - KEYM - KEYM - KEYM - 0xf3154000 - - 0x0 - 0x50 - registers - - - - 8 - 0x4 - SFK0,SFK1,SFK2,SFK3,SFK4,SFK5,SFK6,SFK7 - SOFTMKEY[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software symmetric key -key will be scambled to 4 variants for software to use, and replicable on same chip. -scramble keys are chip different, and not replicable on different chip -must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - 0 - 32 - read-write - - - - - 8 - 0x4 - SPK0,SPK1,SPK2,SPK3,SPK4,SPK5,SPK6,SPK7 - SOFTPKEY[%s] - no description available - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - KEY - software asymmetric key -key is derived from scrambles of fuse private key, software input key, SRK, and system security status. -This key os read once, sencondary read will read out 0 - 0 - 32 - read-write - - - - - SEC_KEY_CTL - secure key generation - 0x40 - 32 - 0x00000000 - 0x80011117 - - - LOCK_SEC_CTL - block secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use origin value in software symmetric key -1: use scramble version of software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use alnertave scramble of fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - NSC_KEY_CTL - non-secure key generation - 0x44 - 32 - 0x00000000 - 0x80011117 - - - LOCK_NSC_CTL - block non-secure state key setting being changed - 31 - 1 - read-write - - - SK_VAL - session key valid -0: session key is all 0's and not usable -1: session key is valid - 16 - 1 - read-only - - - SMK_SEL - software symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 12 - 1 - read-write - - - ZMK_SEL - batt symmetric key selection -0: use scramble version of software symmetric key -1: use origin value in software symmetric key - 8 - 1 - read-write - - - FMK_SEL - fuse symmetric key selection -0: use scramble version of fuse symmetric key -1: use origin value in fuse symmetric key - 4 - 1 - read-write - - - KEY_SEL - non-secure symmtric key synthesize setting, key is a XOR of following -bit0: fuse mk, 0: not selected, 1:selected -bit1: zmk from batt, 0: not selected, 1:selected -bit2: software key 0: not selected, 1:selected - 0 - 3 - read-write - - - - - RNG - Random number interface behavior - 0x48 - 32 - 0x00000000 - 0x00010001 - - - BLOCK_RNG_XOR - block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset -0: RNG_XOR can be changed by software -1: RNG_XOR ignore software change from software - 16 - 1 - read-write - - - RNG_XOR - control how SFK is accepted from random number generator -0: SFK value replaced by random number input -1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - 0 - 1 - read-write - - - - - READ_CONTROL - key read out control - 0x4c - 32 - 0x00000000 - 0x00010001 - - - BLOCK_PK_READ - asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 16 - 1 - read-write - - - BLOCK_SMK_READ - symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset -0: key can be read out -1: key cannot be read out - 0 - 1 - read-write - - - - - - - OTP - OTP - OTP - 0xf3158000 - - 0x0 - 0xc08 - registers - - - - 128 - 0x4 - SHADOW000,SHADOW001,SHADOW002,SHADOW003,SHADOW004,SHADOW005,SHADOW006,SHADOW007,SHADOW008,SHADOW009,SHADOW010,SHADOW011,SHADOW012,SHADOW013,SHADOW014,SHADOW015,SHADOW016,SHADOW017,SHADOW018,SHADOW019,SHADOW020,SHADOW021,SHADOW022,SHADOW023,SHADOW024,SHADOW025,SHADOW026,SHADOW027,SHADOW028,SHADOW029,SHADOW030,SHADOW031,SHADOW032,SHADOW033,SHADOW034,SHADOW035,SHADOW036,SHADOW037,SHADOW038,SHADOW039,SHADOW040,SHADOW041,SHADOW042,SHADOW043,SHADOW044,SHADOW045,SHADOW046,SHADOW047,SHADOW048,SHADOW049,SHADOW050,SHADOW051,SHADOW052,SHADOW053,SHADOW054,SHADOW055,SHADOW056,SHADOW057,SHADOW058,SHADOW059,SHADOW060,SHADOW061,SHADOW062,SHADOW063,SHADOW064,SHADOW065,SHADOW066,SHADOW067,SHADOW068,SHADOW069,SHADOW070,SHADOW071,SHADOW072,SHADOW073,SHADOW074,SHADOW075,SHADOW076,SHADOW077,SHADOW078,SHADOW079,SHADOW080,SHADOW081,SHADOW082,SHADOW083,SHADOW084,SHADOW085,SHADOW086,SHADOW087,SHADOW088,SHADOW089,SHADOW090,SHADOW091,SHADOW092,SHADOW093,SHADOW094,SHADOW095,SHADOW096,SHADOW097,SHADOW098,SHADOW099,SHADOW100,SHADOW101,SHADOW102,SHADOW103,SHADOW104,SHADOW105,SHADOW106,SHADOW107,SHADOW108,SHADOW109,SHADOW110,SHADOW111,SHADOW112,SHADOW113,SHADOW114,SHADOW115,SHADOW116,SHADOW117,SHADOW118,SHADOW119,SHADOW120,SHADOW121,SHADOW122,SHADOW123,SHADOW124,SHADOW125,SHADOW126,SHADOW127 - SHADOW[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SHADOW - shadow register of fuse for pmic area -for PMIC, index valid for 0-15, for SOC index valid for 16-128 - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - SHADOW_LOCK[%s] - no description available - 0x200 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - 128 - 0x4 - FUSE000,FUSE001,FUSE002,FUSE003,FUSE004,FUSE005,FUSE006,FUSE007,FUSE008,FUSE009,FUSE010,FUSE011,FUSE012,FUSE013,FUSE014,FUSE015,FUSE016,FUSE017,FUSE018,FUSE019,FUSE020,FUSE021,FUSE022,FUSE023,FUSE024,FUSE025,FUSE026,FUSE027,FUSE028,FUSE029,FUSE030,FUSE031,FUSE032,FUSE033,FUSE034,FUSE035,FUSE036,FUSE037,FUSE038,FUSE039,FUSE040,FUSE041,FUSE042,FUSE043,FUSE044,FUSE045,FUSE046,FUSE047,FUSE048,FUSE049,FUSE050,FUSE051,FUSE052,FUSE053,FUSE054,FUSE055,FUSE056,FUSE057,FUSE058,FUSE059,FUSE060,FUSE061,FUSE062,FUSE063,FUSE064,FUSE065,FUSE066,FUSE067,FUSE068,FUSE069,FUSE070,FUSE071,FUSE072,FUSE073,FUSE074,FUSE075,FUSE076,FUSE077,FUSE078,FUSE079,FUSE080,FUSE081,FUSE082,FUSE083,FUSE084,FUSE085,FUSE086,FUSE087,FUSE088,FUSE089,FUSE090,FUSE091,FUSE092,FUSE093,FUSE094,FUSE095,FUSE096,FUSE097,FUSE098,FUSE099,FUSE100,FUSE101,FUSE102,FUSE103,FUSE104,FUSE105,FUSE106,FUSE107,FUSE108,FUSE109,FUSE110,FUSE111,FUSE112,FUSE113,FUSE114,FUSE115,FUSE116,FUSE117,FUSE118,FUSE119,FUSE120,FUSE121,FUSE122,FUSE123,FUSE124,FUSE125,FUSE126,FUSE127 - FUSE[%s] - no description available - 0x400 - 32 - 0x00000000 - 0xFFFFFFFF - - - FUSE - fuse array, valid in PMIC part only -read operation will read out value in fuse array -write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - 0 - 32 - read-write - - - - - 8 - 0x4 - LOCK00,LOCK01,LOCK02,LOCK03,LOCK04,LOCK05,LOCK06,LOCK07 - FUSE_LOCK[%s] - no description available - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK - lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types -00: not locked -01: soft locked -10: not locked, and cannot lock in furture -11: double locked - 0 - 32 - read-write - - - - - UNLOCK - UNLOCK - 0x800 - 32 - 0x00000000 - 0xFFFFFFFF - - - UNLOCK - unlock word for fuse array operation -write "OPEN" to unlock fuse array, write any other value will lock write to fuse. -Please make sure 24M crystal is running and 2.5V LDO working properly - 0 - 32 - read-write - - - - - DATA - DATA - 0x804 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - data register for non-blocking access -this register hold dat read from fuse array or data to by programmed to fuse array - 0 - 32 - read-write - - - - - ADDR - ADDR - 0x808 - 32 - 0x00000000 - 0x0000007F - - - ADDR - word address to be read or write - 0 - 7 - read-write - - - - - CMD - CMD - 0x80c - 32 - 0x00000000 - 0xFFFFFFFF - - - CMD - command to access fure array -"BLOW" will update fuse word at ADDR to value hold in DATA -"READ" will fetch fuse value in at ADDR to DATA register - 0 - 32 - read-write - - - - - LOAD_REQ - LOAD Request - 0xa00 - 32 - 0x00000007 - 0x0000000F - - - REQUEST - reload request for 4 regions -bit0: region0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - LOAD_COMP - LOAD complete - 0xa04 - 32 - 0x00000007 - 0x0000000F - - - COMPLETE - reload complete sign for 4 regions -bit0: region 0 -bit1: region1 -bit2: region2 -bit3: region3 - 0 - 4 - read-write - - - - - 4 - 0x4 - LOAD_REGION0,LOAD_REGION1,LOAD_REGION2,LOAD_REGION3 - REGION[%s] - no description available - 0xa20 - 32 - 0x00000800 - 0x00007F7F - - - STOP - stop address of load region, fuse word at end address will NOT be reloaded -region0: fixed at 8 -region1: fixed at 16 -region2: fixed at 0, -region3: usrer configurable - 8 - 7 - read-write - - - START - start address of load region, fuse word at start address will be reloaded -region0: fixed at 0 -region1: fixed at 8 -region2: fixed at 16, -region3: usrer configurable - 0 - 7 - read-write - - - - - INT_FLAG - interrupt flag - 0xc00 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write flag, write 1 to clear -0: fuse is not written or writing -1: value in DATA register is programmed into fuse - 2 - 1 - read-write - - - READ - fuse read flag, write 1 to clear -0: fuse is not read or reading -1: fuse value is put in DATA register - 1 - 1 - read-write - - - LOAD - fuse load flag, write 1 to clear -0: fuse is not loaded or loading -1: fuse loaded - 0 - 1 - read-write - - - - - INT_EN - interrupt enable - 0xc04 - 32 - 0x00000000 - 0x00000007 - - - WRITE - fuse write interrupt enable -0: fuse write interrupt is not enable -1: fuse write interrupt is enable - 2 - 1 - read-write - - - READ - fuse read interrupt enable -0: fuse read interrupt is not enable -1: fuse read interrupt is enable - 1 - 1 - read-write - - - LOAD - fuse load interrupt enable -0: fuse load interrupt is not enable -1: fuse load interrupt is enable - 0 - 1 - read-write - - - - - - - SYSCTL - SYSCTL - SYSCTL - 0xf4000000 - - 0x0 - 0x3000 - registers - - - - 228 - 0x4 - cpu0,cpx0,rsv2,rsv3,rsv4,rsv5,rsv6,rsv7,cpu1,cpx1,rsv10,rsv11,rsv12,rsv13,rsv14,rsv15,rsv16,rsv17,rsv18,rsv19,rsv20,pow_cpu0,pow_cpu1,pow_otn,rst_soc,rst_cpu0,rst_cpu1,rst_otn,rsv28,rsv29,rsv30,rsv31,clk_src_xtal,clk_src_pll0,clk_src_clk0_pll0,clk_src_clk1_pll0,clk_src_pll1,clk_src_clk0_pll1,clk_src_clk1_pll1,clk_src_clk2_pll1,clk_src_pll2,clk_src_clk0_pll2,clk_src_clk1_pll2,clk_src_pll0_ref,clk_src_pll1_ref,clk_src_pll2_ref,rsv46,rsv47,rsv48,rsv49,rsv50,rsv51,rsv52,rsv53,rsv54,rsv55,rsv56,rsv57,rsv58,rsv59,rsv60,rsv61,rsv62,rsv63,clk_top_cpu0,clk_top_mct0,clk_top_cpu1,clk_top_mct1,clk_top_ahb0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axin,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_i2c4,clk_top_i2c5,clk_top_i2c6,clk_top_i2c7,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_spi4,clk_top_spi5,clk_top_spi6,clk_top_spi7,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_urt8,clk_top_urt9,clk_top_urt10,clk_top_urt11,clk_top_urt12,clk_top_urt13,clk_top_urt14,clk_top_urt15,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_xpi0,clk_top_femc,clk_top_eth0,clk_top_ptp0,clk_top_ref0,clk_top_ref1,clk_top_ntm0,clk_top_tsw1,clk_top_tsw2,clk_top_tsw3,clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3,clk_top_i2s0,clk_top_i2s1,rsv143,rsv144,rsv145,rsv146,rsv147,rsv148,rsv149,rsv150,rsv151,rsv152,rsv153,rsv154,rsv155,rsv156,rsv157,rsv158,rsv159,rsv160,rsv161,rsv162,rsv163,rsv164,rsv165,rsv166,rsv167,rsv168,rsv169,rsv170,rsv171,rsv172,rsv173,rsv174,rsv175,rsv176,rsv177,rsv178,rsv179,rsv180,rsv181,rsv182,rsv183,rsv184,rsv185,rsv186,rsv187,rsv188,rsv189,rsv190,rsv191,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,ahbp,axis,axic,axin,rom0,lmm0,mct0,lmm1,mct1,tmr0,tmr1,tmr2,tmr3,tmr4,tmr5,tmr6,tmr7,i2c0,i2c1,i2c2,i2c3,i2c4,i2c5,i2c6,i2c7,spi0,spi1,spi2,spi3,spi4,spi5,spi6,spi7,urt0,urt1,urt2,urt3,urt4,urt5,urt6,urt7,urt8,urt9,urt10,urt11,urt12,urt13,urt14,urt15,crc0,tsns,wdg0,wdg1,wdg2,wdg3,mbx0,mbx1,gpio,ppi0,hdma,lobs,adc0,adc1,adc2,adc3,cmp0,cmp1,cmp2,cmp3,i2s0,i2s1,pdm0,clsd,can0,can1,can2,can3,can4,can5,can6,can7,ptpc,qei0,qei1,qei2,qei3,qeo0,qeo1,qeo2,qeo3,pwm0,pwm1,pwm2,pwm3,rdc0,rdc1,sdm0,sdm1,plb0,sei0,mtg0,mtg1,vsc0,vsc1,clc0,clc1,emds,rng0,sdp0,pka0,kman,xpi0,femc,ram0,ram1,xdma,ffa0,eth0,usb0,ntm0,ref0,ref1,tsw0,esc0 - RESOURCE[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xC0000003 - - - GLB_BUSY - global busy -0: no changes pending to any nodes -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: no change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - MODE - resource work mode -0:auto turn on and off as system required(recommended) -1:always on -2:always off -3:reserved - 0 - 2 - read-write - - - - - 4 - 0x10 - link0,link1,link2,link3 - GROUP0[%s] - no description available - 0x800 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 4 - 0x10 - link0,link1,link2,link3 - GROUP1[%s] - no description available - 0x840 - - VALUE - Group setting - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: peripheral is not needed -1: periphera is needed - 0 - 32 - read-write - - - - - SET - Group setting - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: add periphera into this group，periphera is needed - 0 - 32 - read-write - - - - - CLEAR - Group setting - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: delete periphera in this group，periphera is not needed - 0 - 32 - read-write - - - - - TOGGLE - Group setting - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LINK - denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral -0: no effect -1: toggle the result that whether periphera is needed before - 0 - 32 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - AFFILIATE[%s] - no description available - 0x900 - - VALUE - Affiliate of Group - 0x0 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -bit0: cpu0 depends on group0 -bit1: cpu0 depends on group1 -bit2: cpu0 depends on group2 -bit3: cpu0 depends on group3 - 0 - 4 - read-write - - - - - SET - Affiliate of Group - 0x4 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0，each bit represents a group -0: no effect -1: the group is assigned to CPU0 - 0 - 4 - read-write - - - - - CLEAR - Affiliate of Group - 0x8 - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: the group is not assigned to CPU0 - 0 - 4 - read-write - - - - - TOGGLE - Affiliate of Group - 0xc - 32 - 0x00000000 - 0x0000000F - - - LINK - Affiliate groups of cpu0, each bit represents a group -0: no effect -1: toggle the result that whether the group is assigned to CPU0 before - 0 - 4 - read-write - - - - - - 2 - 0x10 - cpu0,cpu1 - RETENTION[%s] - no description available - 0x920 - - VALUE - Retention Contol - 0x0 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -bit00: soc_mem is kept on while cpu0 stop -bit01: soc_ctx is kept on while cpu0 stop -bit02: cpu0_mem is kept on while cpu0 stop -bit03: cpu0_ctx is kept on while cpu0 stop -bit04: cpu1_mem is kept on while cpu0 stop -bit05: cpu1_ctx is kept on while cpu0 stop -bit06: otn_mem is kept on while cpu0 stop -bit07: otn_ctx is kept on while cpu0 stop -bit08: xtal_hold is kept on while cpu0 stop -bit09: pll0_hold is kept on while cpu0 stop -bit10: pll1_hold is kept on while cpu0 stop -bit11: pll2_hold is kept on while cpu0 stop - 0 - 15 - read-write - - - - - SET - Retention Contol - 0x4 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: keep - 0 - 15 - read-write - - - - - CLEAR - Retention Contol - 0x8 - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: no keep - 0 - 15 - read-write - - - - - TOGGLE - Retention Contol - 0xc - 32 - 0x00000000 - 0x00007FFF - - - LINK - retention setting while CPU0 enter stop mode, each bit represents a resource -0: no effect -1: toggle the result that whether the resource is kept on while CPU0 stop before - 0 - 15 - read-write - - - - - - 3 - 0x10 - cpu0,cpu1,otn - POWER[%s] - no description available - 0x1000 - - status - Power Setting - 0x0 - 32 - 0x80000000 - 0xC0001100 - - - FLAG - flag represents power cycle happened from last clear of this bit -0: power domain did not edurance power cycle since last clear of this bit -1: power domain enduranced power cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup power cycle happened from last clear of this bit -0: power domain did not edurance wakeup power cycle since last clear of this bit -1: power domain enduranced wakeup power cycle since last clear of this bit - 30 - 1 - read-write - - - LF_DISABLE - low fanout power switch disable -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 12 - 1 - read-only - - - LF_ACK - low fanout power switch feedback -0: low fanout power switches are turned on -1: low fanout power switches are truned off - 8 - 1 - read-only - - - - - lf_wait - Power Setting - 0x4 - 32 - 0x000000FF - 0x000FFFFF - - - WAIT - wait time for low fan out power switch turn on, default value is 255 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - off_wait - Power Setting - 0xc - 32 - 0x0000000F - 0x000FFFFF - - - WAIT - wait time for power switch turn off, default value is 15 -0: 0 clock cycle -1: 1 clock cycles -. . . -clock cycles count on 24MHz - 0 - 20 - read-write - - - - - - 4 - 0x10 - soc,cpu0,cpu1,otn - RESET[%s] - no description available - 0x1400 - - control - Reset Setting - 0x0 - 32 - 0x80000000 - 0xC0000011 - - - FLAG - flag represents reset happened from last clear of this bit -0: domain did not edurance reset cycle since last clear of this bit -1: domain enduranced reset cycle since last clear of this bit - 31 - 1 - read-write - - - FLAG_WAKE - flag represents wakeup reset happened from last clear of this bit -0: domain did not edurance wakeup reset cycle since last clear of this bit -1: domain enduranced wakeup reset cycle since last clear of this bit - 30 - 1 - read-write - - - HOLD - perform reset and hold in reset, until ths bit cleared by software -0: reset is released for function -1: reset is assert and hold - 4 - 1 - read-write - - - RESET - perform reset and release imediately -0: reset is released -1 reset is asserted and will release automaticly - 0 - 1 - read-write - - - - - config - Reset Setting - 0x4 - 32 - 0x00402003 - 0x00FFFFFF - - - PRE_WAIT - wait cycle numbers before assert reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 16 - 8 - read-write - - - RSTCLK_NUM - reset clock number(must be even number) -0: 0 cycle -1: 0 cycles -2: 2 cycles -3: 2 cycles -. . . -Note, clock cycle is base on 24M - 8 - 8 - read-write - - - POST_WAIT - time guard band for reset release -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 8 - read-write - - - - - counter - Reset Setting - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - COUNTER - self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset -0: wait 0 cycle -1: wait 1 cycles -. . . -Note, clock cycle is base on 24M - 0 - 20 - read-write - - - - - - 73 - 0x4 - clk_top_cpu0,clk_top_mct0,clk_top_cpu1,clk_top_mct1,clk_top_ahb0,clk_top_axif,clk_top_axis,clk_top_axic,clk_top_axin,clk_top_tmr0,clk_top_tmr1,clk_top_tmr2,clk_top_tmr3,clk_top_tmr4,clk_top_tmr5,clk_top_tmr6,clk_top_tmr7,clk_top_i2c0,clk_top_i2c1,clk_top_i2c2,clk_top_i2c3,clk_top_i2c4,clk_top_i2c5,clk_top_i2c6,clk_top_i2c7,clk_top_spi0,clk_top_spi1,clk_top_spi2,clk_top_spi3,clk_top_spi4,clk_top_spi5,clk_top_spi6,clk_top_spi7,clk_top_urt0,clk_top_urt1,clk_top_urt2,clk_top_urt3,clk_top_urt4,clk_top_urt5,clk_top_urt6,clk_top_urt7,clk_top_urt8,clk_top_urt9,clk_top_urt10,clk_top_urt11,clk_top_urt12,clk_top_urt13,clk_top_urt14,clk_top_urt15,clk_top_ana0,clk_top_ana1,clk_top_ana2,clk_top_ana3,clk_top_aud0,clk_top_aud1,clk_top_can0,clk_top_can1,clk_top_can2,clk_top_can3,clk_top_can4,clk_top_can5,clk_top_can6,clk_top_can7,clk_top_xpi0,clk_top_femc,clk_top_eth0,clk_top_ptp0,clk_top_ntm0,clk_top_ref0,clk_top_ref1,clk_top_tsw1,clk_top_tsw2,clk_top_tsw3 - CLOCK[%s] - no description available - 0x1800 - 32 - 0x00000000 - 0xD00007FF - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux in clock component -0:osc0_clk0 -1:pll0_clk0 -2:pll0_clk1 -3:pll1_clk0 -4:pll1_clk1 -5:pll1_clk2 -6:pll2_clk0 -7:pll2_clk1 - 8 - 3 - read-write - - - DIV - clock divider -0: divider by 1 -1: divider by 2 -2: divider by 3 -. . . -255: divider by 256 - 0 - 8 - read-write - - - - - 4 - 0x4 - clk_top_adc0,clk_top_adc1,clk_top_adc2,clk_top_adc3 - ADCCLK[%s] - no description available - 0x1c00 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: ana clock N -1: ahb0 clock - 8 - 1 - read-write - - - - - 2 - 0x4 - clk_top_i2s0,clk_top_i2s1 - I2SCLK[%s] - no description available - 0x1c10 - 32 - 0x00000000 - 0xD0000100 - - - GLB_BUSY - global busy -0: no changes pending to any clock -1: any of nodes is changing status - 31 - 1 - read-only - - - LOC_BUSY - local busy -0: a change is pending for current node -1: current node is changing status - 30 - 1 - read-only - - - PRESERVE - preserve function against global select -0: select global clock setting -1: not select global clock setting - 28 - 1 - read-write - - - MUX - current mux -0: aud clock N -1: aud clock 0 for others , aud clock 1 for i2s0 - 8 - 1 - read-write - - - - - global00 - Clock senario - 0x2000 - 32 - 0x00000000 - 0x000000FF - - - MUX - global clock override request -bit0: override to preset0 -bit1: override to preset1 -bit2: override to preset2 -bit3: override to preset3 -bit4: override to preset4 -bit5: override to preset5 -bit6: override to preset6 -bit7: override to preset7 - 0 - 8 - read-write - - - - - 4 - 0x20 - slice0,slice1,slice2,slice3 - MONITOR[%s] - no description available - 0x2400 - - control - Clock measure and monitor control - 0x0 - 32 - 0x00000000 - 0x89FFD7FF - - - VALID - result is ready for read -0: not ready -1: result is ready - 31 - 1 - read-write - - - DIV_BUSY - divider is applying new setting - 27 - 1 - read-only - - - OUTEN - enable clock output - 24 - 1 - read-write - - - DIV - output divider - 16 - 8 - read-write - - - HIGH - clock frequency higher than upper limit - 15 - 1 - read-write - - - LOW - clock frequency lower than lower limit - 14 - 1 - read-write - - - START - start measurement - 12 - 1 - read-write - - - MODE - work mode, -0: register value will be compared to measurement -1: upper and lower value will be recordered in register - 10 - 1 - read-write - - - ACCURACY - measurement accuracy, -0: resolution is 1kHz -1: resolution is 1Hz - 9 - 1 - read-write - - - REFERENCE - refrence clock selection, -0: 32k -1: 24M - 8 - 1 - read-write - - - SELECTION - clock measurement selection - 0 - 8 - read-write - - - - - current - Clock measure result - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - self updating measure result - 0 - 32 - read-only - - - - - low_limit - Clock lower limit - 0x8 - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - FREQUENCY - lower frequency - 0 - 32 - read-write - - - - - high_limit - Clock upper limit - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - FREQUENCY - upper frequency - 0 - 32 - read-write - - - - - - 2 - 0x400 - cpu0,cpu1 - CPU[%s] - no description available - 0x2800 - - LP - CPU0 LP control - 0x0 - 32 - 0x00001000 - 0xFF013703 - - - WAKE_CNT - CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - 24 - 8 - read-write - - - HALT - halt request for CPU0, -0: CPU0 will start to execute after reset or receive wakeup request -1: CPU0 will not start after reset, or wakeup after WFI - 16 - 1 - read-write - - - WAKE - CPU0 is waking up -0: CPU0 wake up not asserted -1: CPU0 wake up asserted - 13 - 1 - read-only - - - EXEC - CPU0 is executing -0: CPU0 is not executing -1: CPU0 is executing - 12 - 1 - read-only - - - WAKE_FLAG - CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit -0: CPU0 wakeup not happened -1: CPU0 wake up happened - 10 - 1 - read-write - - - SLEEP_FLAG - CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit -0: CPU0 sleep not happened -1: CPU0 sleep happened - 9 - 1 - read-write - - - RESET_FLAG - CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit -0: CPU0 reset not happened -1: CPU0 reset happened - 8 - 1 - read-write - - - MODE - Low power mode, system behavior after WFI -00: CPU clock stop after WFI -01: System enter low power mode after WFI -10: Keep running after WFI -11: reserved - 0 - 2 - read-write - - - - - LOCK - CPU0 Lock GPR - 0x4 - 32 - 0x00000000 - 0x0000FFFE - - - GPR - Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - 2 - 14 - read-write - - - LOCK - Lock bit for CPU_LOCK - 1 - 1 - read-write - - - - - 14 - 0x4 - GPR0,GPR1,GPR2,GPR3,GPR4,GPR5,GPR6,GPR7,GPR8,GPR9,GPR10,GPR11,GPR12,GPR13 - GPR[%s] - no description available - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - register for software to handle resume, can save resume address or status - 0 - 32 - read-write - - - - - 6 - 0x4 - STATUS0,STATUS1,STATUS2,STATUS3,STATUS4,STATUS5 - WAKEUP_STATUS[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - IRQ values - 0 - 32 - read-only - - - - - 6 - 0x4 - ENABLE0,ENABLE1,ENABLE2,ENABLE3,ENABLE4,ENABLE5 - WAKEUP_ENABLE[%s] - no description available - 0x80 - 32 - 0x00000000 - 0xFFFFFFFF - - - ENABLE - IRQ wakeup enable - 0 - 32 - read-write - - - - - - - - IOC - IOC - IOC - 0xf4040000 - - 0x0 - 0xf40 - registers - - - - 488 - 0x8 - pa00,pa01,pa02,pa03,pa04,pa05,pa06,pa07,pa08,pa09,pa10,pa11,pa12,pa13,pa14,pa15,pa16,pa17,pa18,pa19,pa20,pa21,pa22,pa23,pa24,pa25,pa26,pa27,pa28,pa29,pa30,pa31,pb00,pb01,pb02,pb03,pb04,pb05,pb06,pb07,pb08,pb09,pb10,pb11,pb12,pb13,pb14,pb15,pb16,pb17,pb18,pb19,pb20,pb21,pb22,pb23,pb24,pb25,pb26,pb27,pb28,pb29,pb30,pb31,pc00,pc01,pc02,pc03,pc04,pc05,pc06,pc07,pc08,pc09,pc10,pc11,pc12,pc13,pc14,pc15,pc16,pc17,pc18,pc19,pc20,pc21,pc22,pc23,pc24,pc25,pc26,pc27,pc28,pc29,pc30,pc31,pd00,pd01,pd02,pd03,pd04,pd05,pd06,pd07,pd08,pd09,pd10,pd11,pd12,pd13,pd14,pd15,pd16,pd17,pd18,pd19,pd20,pd21,pd22,pd23,pd24,pd25,pd26,pd27,pd28,pd29,pd30,pd31,pe00,pe01,pe02,pe03,pe04,pe05,pe06,pe07,pe08,pe09,pe10,pe11,pe12,pe13,pe14,pe15,pe16,pe17,pe18,pe19,pe20,pe21,pe22,pe23,pe24,pe25,pe26,pe27,pe28,pe29,pe30,pe31,pf00,pf01,pf02,pf03,pf04,pf05,pf06,pf07,pf08,pf09,pf10,pf11,pf12,pf13,pf14,pf15,pf16,pf17,pf18,pf19,pf20,pf21,pf22,pf23,pf24,pf25,pf26,pf27,pf28,pf29,pf30,pf31,rsv192,rsv193,rsv194,rsv195,rsv196,rsv197,rsv198,rsv199,rsv200,rsv201,rsv202,rsv203,rsv204,rsv205,rsv206,rsv207,rsv208,rsv209,rsv210,rsv211,rsv212,rsv213,rsv214,rsv215,rsv216,rsv217,rsv218,rsv219,rsv220,rsv221,rsv222,rsv223,rsv224,rsv225,rsv226,rsv227,rsv228,rsv229,rsv230,rsv231,rsv232,rsv233,rsv234,rsv235,rsv236,rsv237,rsv238,rsv239,rsv240,rsv241,rsv242,rsv243,rsv244,rsv245,rsv246,rsv247,rsv248,rsv249,rsv250,rsv251,rsv252,rsv253,rsv254,rsv255,rsv256,rsv257,rsv258,rsv259,rsv260,rsv261,rsv262,rsv263,rsv264,rsv265,rsv266,rsv267,rsv268,rsv269,rsv270,rsv271,rsv272,rsv273,rsv274,rsv275,rsv276,rsv277,rsv278,rsv279,rsv280,rsv281,rsv282,rsv283,rsv284,rsv285,rsv286,rsv287,rsv288,rsv289,rsv290,rsv291,rsv292,rsv293,rsv294,rsv295,rsv296,rsv297,rsv298,rsv299,rsv300,rsv301,rsv302,rsv303,rsv304,rsv305,rsv306,rsv307,rsv308,rsv309,rsv310,rsv311,rsv312,rsv313,rsv314,rsv315,rsv316,rsv317,rsv318,rsv319,rsv320,rsv321,rsv322,rsv323,rsv324,rsv325,rsv326,rsv327,rsv328,rsv329,rsv330,rsv331,rsv332,rsv333,rsv334,rsv335,rsv336,rsv337,rsv338,rsv339,rsv340,rsv341,rsv342,rsv343,rsv344,rsv345,rsv346,rsv347,rsv348,rsv349,rsv350,rsv351,pv00,pv01,pv02,pv03,pv04,pv05,pv06,pv07,pv08,pv09,pv10,pv11,pv12,pv13,pv14,pv15,rsv368,rsv369,rsv370,rsv371,rsv372,rsv373,rsv374,rsv375,rsv376,rsv377,rsv378,rsv379,rsv380,rsv381,rsv382,rsv383,pw00,pw01,pw02,pw03,pw04,pw05,pw06,pw07,pw08,pw09,pw10,pw11,pw12,pw13,pw14,pw15,pw16,pw17,pw18,pw19,pw20,pw21,pw22,pw23,rsv408,rsv409,rsv410,rsv411,rsv412,rsv413,rsv414,rsv415,px00,px01,px02,px03,px04,px05,px06,px07,rsv424,rsv425,rsv426,rsv427,rsv428,rsv429,rsv430,rsv431,rsv432,rsv433,rsv434,rsv435,rsv436,rsv437,rsv438,rsv439,rsv440,rsv441,rsv442,rsv443,rsv444,rsv445,rsv446,rsv447,py00,py01,py02,py03,py04,py05,py06,py07,rsv456,rsv457,rsv458,rsv459,rsv460,rsv461,rsv462,rsv463,rsv464,rsv465,rsv466,rsv467,rsv468,rsv469,rsv470,rsv471,rsv472,rsv473,rsv474,rsv475,rsv476,rsv477,rsv478,rsv479,pz00,pz01,pz02,pz03,pz04,pz05,pz06,pz07 - PAD[%s] - no description available - 0x0 - - FUNC_CTL - ALT SELECT - 0x0 - 32 - 0x00000000 - 0x0001011F - - - LOOP_BACK - force input on -0: disable -1: enable - 16 - 1 - read-write - - - ANALOG - select analog pin in pad -0: disable -1: enable - 8 - 1 - read-write - - - ALT_SELECT - alt select -0: ALT0 -1: ALT1 -... -31:ALT31 - 0 - 5 - read-write - - - - - PAD_CTL - PAD SETTINGS - 0x4 - 32 - 0x01010056 - 0x01370177 - - - HYS - schmitt trigger enable -0: disable -1: enable - 24 - 1 - read-write - - - PRS - select pull up/down internal resistance strength: -For pull down, only have 100 Kohm resistance -For pull up: -00: 100 KOhm -01: 47 KOhm -10: 22 KOhm -11: 22 KOhm - 20 - 2 - read-write - - - PS - pull select -0: pull down -1: pull up - 18 - 1 - read-write - - - PE - pull enable -0: pull disable -1: pull enable - 17 - 1 - read-write - - - KE - keeper capability enable -0: keeper disable -1: keeper enable - 16 - 1 - read-write - - - OD - open drain -0: open drain disable -1: open drain enable - 8 - 1 - read-write - - - SR - slew rate -0: Slow slew rate -1: Fast slew rate - 6 - 1 - read-write - - - SPD - additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise -00: Slow frequency slew rate(50Mhz) -01: Medium frequency slew rate(100 Mhz) -10: Fast frequency slew rate(150 Mhz) -11: Max frequency slew rate(200Mhz) - 4 - 2 - read-write - - - DS - drive strength -1.8V Mode: -000: 260 Ohm -001: 260 Ohm -010: 130 Ohm -011: 88 Ohm -100: 65 Ohm -101: 52 Ohm -110: 43 Ohm -111: 37 Ohm -3.3V Mode: -000: 157 Ohm -001: 157 Ohm -010: 78 Ohm -011: 53 Ohm -100: 39 Ohm -101: 32 Ohm -110: 26 Ohm -111: 23 Ohm - 0 - 3 - read-write - - - - - - - - PIOC - PIOC - IOC - 0xf4118000 - - - BIOC - BIOC - IOC - 0xf4210000 - - - PLLCTLV2 - PLLCTLV2 - PLLCTLV2 - 0xf40c0000 - - 0x0 - 0x200 - registers - - - - XTAL - OSC configuration - 0x0 - 32 - 0x0001FFFF - 0xB00FFFFF - - - BUSY - Busy flag -0: Oscillator is working or shutdown -1: Oscillator is changing status - 31 - 1 - read-only - - - RESPONSE - Crystal oscillator status -0: Oscillator is not stable -1: Oscillator is stable for use - 29 - 1 - read-only - - - ENABLE - Crystal oscillator enable status -0: Oscillator is off -1: Oscillator is on - 28 - 1 - read-only - - - RAMP_TIME - Rampup time of XTAL oscillator in cycles of RC24M clock -0: 0 cycle -1: 1 cycle -2: 2 cycle -1048575: 1048575 cycles - 0 - 20 - read-write - - - - - 3 - 0x80 - pll0,pll1,pll2 - PLL[%s] - no description available - 0x80 - - MFI - PLL0 multiple register - 0x0 - 32 - 0x00000010 - 0xB000007F - - - BUSY - Busy flag -0: PLL is stable or shutdown -1: PLL is changing status - 31 - 1 - read-only - - - RESPONSE - PLL status -0: PLL is not stable -1: PLL is stable for use - 29 - 1 - read-only - - - ENABLE - PLL enable status -0: PLL is off -1: PLL is on - 28 - 1 - read-only - - - MFI - loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) -0-15: invalid -16: divide by 16 -17: divide by17 -. . . -42: divide by 42 -43~:invalid - 0 - 7 - read-write - - - - - MFN - PLL0 fraction numerator register - 0x4 - 32 - 0x09896800 - 0x3FFFFFFF - - - MFN - Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - 0 - 30 - read-write - - - - - MFD - PLL0 fraction demoninator register - 0x8 - 32 - 0x0E4E1C00 - 0x3FFFFFFF - - - MFD - Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - 0 - 30 - read-write - - - - - SS_STEP - PLL0 spread spectrum step register - 0xc - 32 - 0x00000000 - 0x3FFFFFFF - - - STEP - Step of spread spectrum modulator. -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - SS_STOP - PLL0 spread spectrum stop register - 0x10 - 32 - 0x00000000 - 0x3FFFFFFF - - - STOP - Stop point of spread spectrum modulator -This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - 0 - 30 - read-write - - - - - CONFIG - PLL0 confguration register - 0x14 - 32 - 0x00000000 - 0x00000101 - - - SPREAD - Enable spread spectrum function. This field supports changing during PLL running. - 8 - 1 - read-write - - - REFSEL - Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. -0: XTAL24M -1: IRC24M - 0 - 1 - read-write - - - - - LOCKTIME - PLL0 lock time register - 0x18 - 32 - 0x000009C4 - 0x0000FFFF - - - LOCKTIME - Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - 0 - 16 - read-write - - - - - STEPTIME - PLL0 step time register - 0x1c - 32 - 0x000009C4 - 0x0000FFFF - - - STEPTIME - Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - 0 - 16 - read-write - - - - - ADVANCED - PLL0 advance configuration register - 0x20 - 32 - 0x00000000 - 0x11000000 - - - SLOW - Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. -0: fast lock enabled, lock time is 100us -1: fast lock disabled, lock time is 400us - 28 - 1 - read-write - - - DITHER - Enable dither function - 24 - 1 - read-write - - - - - 3 - 0x4 - DIV0,DIV1,DIV2 - DIV[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xB000003F - - - BUSY - Busy flag -0: divider is working -1: divider is changing status - 31 - 1 - read-only - - - RESPONSE - Divider response status -0: Divider is not stable -1: Divider is stable for use - 29 - 1 - read-only - - - ENABLE - Divider enable status -0: Divider is off -1: Divider is on - 28 - 1 - read-only - - - DIV - Divider factor, divider factor is DIV/5 + 1 -0: divide by 1 -1: divide by 1.2 -2: divide by 1.4 -. . . -63: divide by 13.6 - 0 - 6 - read-write - - - - - - - - PPOR - PPOR - PPOR - 0xf4100000 - - 0x0 - 0x20 - registers - - - - RESET_FLAG - flag indicate reset source - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - FLAG - reset reason of last hard reset, write 1 to clear each bit -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - write-only - - - - - RESET_STATUS - reset source status - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - STATUS - current status of reset sources -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-only - - - - - RESET_HOLD - reset hold attribute - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - HOLD - hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_ENABLE - reset source enable - 0xc - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - ENABLE - enable of reset sources -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - RESET_TYPE - reset type triggered by reset - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - TYPE - reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem -0: brownout -1: temperature -4: debug reset -5: jtag soft reset -8: cpu0 lockup(not available) -9: cpu1 lockup(not available) -10: cpu0 request(not available) -11: cpu1 request(not available) -16: watch dog 0 -17: watch dog 1 -18: watch dog 2(not available) -19: watch dog 3(not available) -24: pmic watch dog -30: jtag ieee reset -31: software - 0 - 32 - read-write - - - - - SOFTWARE_RESET - Software reset counter - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - 0 - 32 - read-write - - - - - - - PCFG - PCFG - PCFG - 0xf4104000 - - 0x0 - 0x70 - registers - - - - BANDGAP - BANGGAP control - 0x0 - 32 - 0x00101010 - 0x801F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - VBG_1P0_TRIM - Banggap 1.0V output trim value - 16 - 5 - read-write - - - VBG_P65_TRIM - Banggap 1.0V output trim value - 8 - 5 - read-write - - - VBG_P50_TRIM - Banggap 1.0V output trim value - 0 - 5 - read-write - - - - - LDO1P1 - 1V LDO config - 0x4 - 32 - 0x0000044C - 0x00000FFF - - - VOLT - LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. -700: 700mV -720: 720mV -. . . -1320:1320mV - 0 - 12 - read-write - - - - - LDO2P5 - 2.5V LDO config - 0x8 - 32 - 0x000009C4 - 0x10010FFF - - - READY - Ready flag, will set 1ms after enabled or voltage change -0: LDO is not ready for use -1: LDO is ready - 28 - 1 - read-only - - - ENABLE - LDO enable -0: turn off LDO -1: turn on LDO - 16 - 1 - read-write - - - VOLT - LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. -2125: 2125mV -2150: 2150mV -. . . -2900:2900mV - 0 - 12 - read-write - - - - - DCDC_MODE - DCDC mode select - 0x10 - 32 - 0x0001047E - 0x10070FFF - - - READY - Ready flag -0: DCDC is applying new change -1: DCDC is ready - 28 - 1 - read-only - - - MODE - DCDC work mode -XX0: trun off -001: basic mode -011: generic mode -101: automatic mode -111: expert mode - 16 - 3 - read-write - - - VOLT - DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_LPMODE - DCDC low power mode - 0x14 - 32 - 0x00000384 - 0x00000FFF - - - STBY_VOLT - DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. -600: 600mV -625: 625mV -. . . -1375:1375mV - 0 - 12 - read-write - - - - - DCDC_PROT - DCDC protection - 0x18 - 32 - 0x00000010 - 0x11018191 - - - ILIMIT_LP - over current setting for low power mode -0:250mA -1:200mA - 28 - 1 - read-write - - - OVERLOAD_LP - over current in low power mode -0: current is below setting -1: overcurrent happened in low power mode - 24 - 1 - read-only - - - POWER_LOSS_FLAG - power loss -0: input power is good -1: input power is too low - 16 - 1 - read-only - - - DISABLE_OVERVOLTAGE - ouput over voltage protection -0: protection enabled, DCDC will shut down is output voltage is unexpected high -1: protection disabled, DCDC continue to adjust output voltage - 15 - 1 - read-write - - - OVERVOLT_FLAG - output over voltage flag -0: output is normal -1: output is unexpected high - 8 - 1 - read-only - - - DISABLE_SHORT - disable output short circuit protection -0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected -1: short circuit protection disabled - 7 - 1 - read-write - - - SHORT_CURRENT - short circuit current setting -0: 2.0A, -1: 1.3A - 4 - 1 - read-write - - - SHORT_FLAG - short circuit flag -0: current is within limit -1: short circuits detected - 0 - 1 - read-only - - - - - DCDC_CURRENT - DCDC current estimation - 0x1c - 32 - 0x00000000 - 0x0000811F - - - ESTI_EN - enable current measure - 15 - 1 - read-write - - - VALID - Current level valid -0: data is invalid -1: data is valid - 8 - 1 - read-only - - - LEVEL - DCDC current level, current level is num * 50mA - 0 - 5 - read-only - - - - - DCDC_ADVMODE - DCDC advance setting - 0x20 - 32 - 0x03120040 - 0x073F007F - - - EN_RCSCALE - Enable RC scale - 24 - 3 - read-write - - - DC_C - Loop C number - 20 - 2 - read-write - - - DC_R - Loop R number - 16 - 4 - read-write - - - EN_FF_DET - enable feed forward detect -0: feed forward detect is disabled -1: feed forward detect is enabled - 6 - 1 - read-write - - - EN_FF_LOOP - enable feed forward loop -0: feed forward loop is disabled -1: feed forward loop is enabled - 5 - 1 - read-write - - - EN_AUTOLP - enable auto enter low power mode -0: do not enter low power mode -1: enter low power mode if current is detected low - 4 - 1 - read-write - - - EN_DCM_EXIT - avoid over voltage -0: stay in DCM mode when voltage excess -1: change to CCM mode when voltage excess - 3 - 1 - read-write - - - EN_SKIP - enable skip on narrow pulse -0: do not skip narrow pulse -1: skip narrow pulse - 2 - 1 - read-write - - - EN_IDLE - enable skip when voltage is higher than threshold -0: do not skip -1: skip if voltage is excess - 1 - 1 - read-write - - - EN_DCM - DCM mode -0: CCM mode -1: DCM mode - 0 - 1 - read-write - - - - - DCDC_ADVPARAM - DCDC advance parameter - 0x24 - 32 - 0x00006E1C - 0x00007F7F - - - MIN_DUT - minimum duty cycle - 8 - 7 - read-write - - - MAX_DUT - maximum duty cycle - 0 - 7 - read-write - - - - - DCDC_MISC - DCDC misc parameter - 0x28 - 32 - 0x00070100 - 0x13170317 - - - EN_HYST - hysteres enable - 28 - 1 - read-write - - - HYST_SIGN - hysteres sign - 25 - 1 - read-write - - - HYST_THRS - hysteres threshold - 24 - 1 - read-write - - - RC_SCALE - Loop RC scale threshold - 20 - 1 - read-write - - - DC_FF - Loop feed forward number - 16 - 3 - read-write - - - OL_THRE - overload for threshold for lod power mode - 8 - 2 - read-write - - - OL_HYST - current hysteres range -0: 12.5mV -1: 25mV - 4 - 1 - read-write - - - DELAY - enable delay -0: delay disabled, -1: delay enabled - 2 - 1 - read-write - - - CLK_SEL - clock selection -0: select DCDC internal oscillator -1: select RC24M oscillator - 1 - 1 - read-write - - - EN_STEP - enable stepping in voltage change -0: stepping disabled, -1: steping enabled - 0 - 1 - read-write - - - - - DCDC_DEBUG - DCDC Debug - 0x2c - 32 - 0x00005DBF - 0x000FFFFF - - - UPDATE_TIME - DCDC voltage change time in 24M clock cycles, default value is 1mS - 0 - 20 - read-write - - - - - DCDC_START_TIME - DCDC ramp time - 0x30 - 32 - 0x0001193F - 0x000FFFFF - - - START_TIME - Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - 0 - 20 - read-write - - - - - DCDC_RESUME_TIME - DCDC resume time - 0x34 - 32 - 0x00008C9F - 0x000FFFFF - - - RESUME_TIME - Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - 0 - 20 - read-write - - - - - POWER_TRAP - SOC power trap - 0x40 - 32 - 0x00000000 - 0x80010001 - - - TRIGGERED - Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. -0: low power trap is not triggered -1: low power trap triggered - 31 - 1 - read-write - - - RETENTION - DCDC enter standby mode, which will reduce voltage for memory content retention -0: Shutdown DCDC -1: reduce DCDC voltage - 16 - 1 - read-write - - - TRAP - Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered -0: trap not enabled, pmic side low power function disabled -1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - 0 - 1 - read-write - - - - - WAKE_CAUSE - Wake up source - 0x44 - 32 - 0x00000000 - 0xFFFFFFFF - - - CAUSE - wake up cause, each bit represents one wake up source, write 1 to clear the register bit -0: wake up source is not active during last wakeup -1: wake up source is active furing last wakeup -bit 0: pmic_enable -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit16: batt security interrupt -bit17:batt gpio interrupt -bit19:rtc interrupt -bit31: pin wakeup - 0 - 32 - read-write - - - - - WAKE_MASK - Wake up mask - 0x48 - 32 - 0x00000000 - 0xFFFFFFFF - - - MASK - mask for wake up sources, each bit represents one wakeup source -0: allow source to wake up system -1: disallow source to wakeup system -bit 0: pmic_enable -bit 7: UART interrupt -bit 8: TMR interrupt -bit 9: WDG interrupt -bit10: GPIO in PMIC interrupt -bit16: batt security interrupt -bit17:batt gpio interrupt -bit19:rtc interrupt -bit31: pin wakeup - 0 - 32 - read-write - - - - - SCG_CTRL - Clock gate control in PMIC - 0x4c - 32 - 0xFFFFFFFF - 0xFFFFFFFF - - - SCG - control whether clock being gated during PMIC low power flow, 2 bits for each peripheral -00,01: reserved -10: clock is always off -11: clock is always on -bit6-7:gpio -bit8-9:ioc -bit10-11: timer -bit12-13:wdog -bit14-15:uart - 0 - 32 - read-write - - - - - RC24M - RC 24M config - 0x60 - 32 - 0x00000310 - 0x8000071F - - - RC_TRIMMED - RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: RC is not trimmed -1: RC is trimmed - 31 - 1 - read-write - - - TRIM_C - Coarse trim for RC24M, bigger value means faster - 8 - 3 - read-write - - - TRIM_F - Fine trim for RC24M, bigger value means faster - 0 - 5 - read-write - - - - - RC24M_TRACK - RC 24M track mode - 0x64 - 32 - 0x00000000 - 0x00010011 - - - SEL24M - Select track reference -0: select 32K as reference -1: select 24M XTAL as reference - 16 - 1 - read-write - - - RETURN - Retrun default value when XTAL loss -0: remain last tracking value -1: switch to default value - 4 - 1 - read-write - - - TRACK - track mode -0: RC24M free running -1: track RC24M to external XTAL - 0 - 1 - read-write - - - - - TRACK_TARGET - RC 24M track target - 0x68 - 32 - 0x00000000 - 0xFFFFFFFF - - - PRE_DIV - Divider for reference source - 16 - 16 - read-write - - - TARGET - Target frequency multiplier of divided source - 0 - 16 - read-write - - - - - STATUS - RC 24M track status - 0x6c - 32 - 0x00000000 - 0x0011871F - - - SEL32K - track is using XTAL32K -0: track is not using XTAL32K -1: track is using XTAL32K - 20 - 1 - read-only - - - SEL24M - track is using XTAL24M -0: track is not using XTAL24M -1: track is using XTAL24M - 16 - 1 - read-only - - - EN_TRIM - default value takes effect -0: default value is invalid -1: default value is valid - 15 - 1 - read-only - - - TRIM_C - default coarse trim value - 8 - 3 - read-only - - - TRIM_F - default fine trim value - 0 - 5 - read-only - - - - - - - PDGO - PDGO - PDGO - 0xf4134000 - - 0x0 - 0x714 - registers - - - - DGO_TURNOFF - trunoff control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. - 0 - 32 - write-only - - - - - DGO_RC32K_CFG - RC32K CLOCK - 0x4 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - DGO_GPR00 - Generic control 0 - 0x600 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR01 - Generic control 1 - 0x604 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR02 - Generic control 2 - 0x608 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_GPR03 - Generic control 3 - 0x60c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - DGO_CTR0 - control register 0 - 0x700 - 32 - 0x00000000 - 0x00010000 - - - RETENTION - dgo register status retenion - 16 - 1 - read-write - - - - - DGO_CTR1 - control register 1 - 0x704 - 32 - 0x00000000 - 0x80010001 - - - AOTO_SYS_WAKEUP - software wakeup： 0 : wakeup once； 1：auto wakeup Continuously - 31 - 1 - read-write - - - WAKEUP_EN - permit wakeup pin or software wakeup - 16 - 1 - read-write - - - PIN_WAKEUP_STATUS - wakeup pin status - 0 - 1 - read-only - - - - - DGO_CTR2 - control register 2 - 0x708 - 32 - 0x00000000 - 0x01010000 - - - RESETN_PULLUP_DISABLE - resetn pin pull up disable - 24 - 1 - read-write - - - WAKEUP_PULLDN_DISABLE - wakeup pin pull down disable - 16 - 1 - read-write - - - - - DGO_CTR3 - control register 3 - 0x70c - 32 - 0x00000000 - 0xFFFFFFFF - - - WAKEUP_COUNTER - software wakeup counter - 0 - 32 - read-write - - - - - DGO_CTR4 - control register 4 - 0x710 - 32 - 0x00000000 - 0x00000003 - - - BANDGAP_LESS_POWER - Banggap work in power save mode, banggap function normally -0: banggap works in high performance mode -1: banggap works in power saving mode - 1 - 1 - read-write - - - BANDGAP_LP_MODE - Banggap work in low power mode, banggap function limited -0: banggap works in normal mode -1: banggap works in low power mode - 0 - 1 - read-write - - - - - - - PGPR0 - PGPR0 - PGPR - 0xf4138000 - - 0x0 - 0x40 - registers - - - - PMIC_GPR00 - Generic control - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR01 - Generic control - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR02 - Generic control - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR03 - Generic control - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR04 - Generic control - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR05 - Generic control - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR06 - Generic control - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR07 - Generic control - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR08 - Generic control - 0x20 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR09 - Generic control - 0x24 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR10 - Generic control - 0x28 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR11 - Generic control - 0x2c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR12 - Generic control - 0x30 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR13 - Generic control - 0x34 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR14 - Generic control - 0x38 - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - PMIC_GPR15 - Generic control - 0x3c - 32 - 0x00000000 - 0xFFFFFFFF - - - GPR - Generic control - 0 - 32 - read-write - - - - - - - PGPR1 - PGPR1 - PGPR - 0xf413c000 - - - BACC - BACC - BACC - 0xf4200000 - - 0x0 - 0x10 - registers - - - - CONFIG - Access timing for access - 0x0 - 32 - 0x00000000 - 0x3000FFFF - - - FAST_WRITE - Use fast write -0: Write normally -1: boost write - 29 - 1 - read-write - - - FAST_READ - Use fast read -0: Read normally -1: boost read - 28 - 1 - read-write - - - TIMING - Time in APB clock cycles, for battery timing penerate - 0 - 16 - read-write - - - - - PRE_TIME - Timing gap before rising edge - 0x8 - 32 - 0x00000000 - 0x000FFFFF - - - PRE_RATIO - Ratio of guard band before rising edge -0: 0 -1: 1/32768 of low level width -2: 1/16384 of low level width -14: 1/4 of low level width -15: 1/2 of low level width - 16 - 4 - read-write - - - PRE_OFFSET - guard band before rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - POST_TIME - Timing gap after rising edge - 0xc - 32 - 0x00000000 - 0x000FFFFF - - - POST_RATIO - Ratio of guard band after rising edge -0: 0 -1: 1/32768 of high level width -2: 1/16384 of high level width -14: 1/4 of high level width -15: 1/2 of high level width - 16 - 4 - read-write - - - POST_OFFSET - guard band after rising edge -this value will be added to ratio number - 0 - 16 - read-write - - - - - - - BPOR - BPOR - BPOR - 0xf4204000 - - 0x0 - 0x4 - registers - - - - POR_CONFIG - Power on reset config - 0x0 - 32 - 0x00000000 - 0x00000001 - - - RETENTION - retention battery domain setting -0: battery reset on reset pin reset happen -1: battery domain retention when reset pin reset happen - 0 - 1 - read-write - - - - - - - BCFG - BCFG - BCFG - 0xf4208000 - - 0x0 - 0x14 - registers - - - - VBG_CFG - Bandgap config - 0x0 - 32 - 0x00000000 - 0x811F1F1F - - - VBG_TRIMMED - Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: bandgap is not trimmed -1: bandgap is trimmed - 31 - 1 - read-write - - - POWER_SAVE - Bandgap works in power save mode -0: not in power save mode -1: bandgap work in power save mode - 24 - 1 - read-write - - - VBG_1P0 - Bandgap 1.0V output trim - 16 - 5 - read-write - - - VBG_P65 - Bandgap 0.65V output trim - 8 - 5 - read-write - - - VBG_P50 - Bandgap 0.50V output trim - 0 - 5 - read-write - - - - - IRC32K_CFG - On-chip 32k oscillator config - 0x8 - 32 - 0x00000000 - 0x80C001FF - - - IRC_TRIMMED - IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value -0: irc is not trimmed -1: irc is trimmed - 31 - 1 - read-write - - - CAPEX7_TRIM - IRC32K bit 7 - 23 - 1 - read-write - - - CAPEX6_TRIM - IRC32K bit 6 - 22 - 1 - read-write - - - CAP_TRIM - capacitor trim bits - 0 - 9 - read-write - - - - - XTAL32K_CFG - XTAL 32K config - 0xc - 32 - 0x00000000 - 0x00001313 - - - HYST_EN - crystal 32k hysteres enable - 12 - 1 - read-write - - - GMSEL - crystal 32k gm selection - 8 - 2 - read-write - - - CFG - crystal 32k config - 4 - 1 - read-write - - - AMP - crystal 32k amplifier - 0 - 2 - read-write - - - - - CLK_CFG - Clock config - 0x10 - 32 - 0x00000000 - 0x10010010 - - - XTAL_SEL - crystal selected - 28 - 1 - read-only - - - KEEP_IRC - force irc32k run - 16 - 1 - read-write - - - FORCE_XTAL - force switch to crystal - 4 - 1 - read-write - - - - - - - BGPR0 - BGPR0 - BGPR - 0xf4218000 - - 0x0 - 0x40 - registers - - - - 16 - 0x4 - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 - GPR[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - Generic control - 0 - 32 - read-write - - - - - - - BGPR1 - BGPR1 - BGPR - 0xf4220000 - - - BSEC - BSEC - BSEC - 0xf4240000 - - 0x0 - 0x14 - registers - - - - SECURE_STATE - Secure state - 0x0 - 32 - 0x00000000 - 0x0003000F - - - ALLOW_NSC - Non-secure state allow -0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter non-secure state - 17 - 1 - read-only - - - ALLOW_SEC - Secure state allow -0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state -1: system is healthy to enter secure state - 16 - 1 - read-only - - - BATT_FAIL - BATT secure state one hot indicator -0: secure state is not in fail state -1: secure state is in fail state - 3 - 1 - read-write - - - BATT_NSC - BATT secure state one hot indicator -0: secure state is not in non-secure state -1: secure state is in non-secure state - 2 - 1 - read-write - - - BATT_SEC - BATT secure state one hot indicator -0: secure state is not in secure state -1: secure state is in secure state - 1 - 1 - read-write - - - BATT_INS - BATT secure state one hot indicator -0: secure state is not in inspect state -1: secure state is in inspect state - 0 - 1 - read-write - - - - - SECURE_STATE_CONFIG - secure state configuration - 0x4 - 32 - 0x00000000 - 0x00000009 - - - LOCK - Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset -0: not locked, register can be modified -1: register locked, write access to the register is ignored - 3 - 1 - read-write - - - ALLOW_RESTART - allow secure state restart from fail state -0: restart is not allowed, only hardware reset can recover secure state -1: software is allowed to switch to inspect state from fail state - 0 - 1 - read-write - - - - - VIOLATION_CONFIG - Security violation config - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state violations, each bit represents one security event -0: event is not a security violation -1: event is a security violation - 0 - 15 - read-write - - - - - ESCALATE_CONFIG - Escalate behavior on security event - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - LOCK_NSC - Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified -1: register locked, write access to the configuration is ignored - 31 - 1 - read-write - - - NSC_VIO_CFG - configuration of non-secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 16 - 15 - read-write - - - LOCK_SEC - Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset -0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - 15 - 1 - read-write - - - SEC_VIO_CFG - configuration of secure state escalates, each bit represents one security event -0: event is not a security escalate -1: event is a security escalate - 0 - 15 - read-write - - - - - EVENT - Event and escalate status - 0x10 - 32 - 0x00000000 - 0xFFFF0003 - - - EVENT - local event statue, each bit represents one security event - 16 - 16 - read-only - - - BATT_ESC_NSC - BATT is escalating non-secure event - 1 - 1 - read-only - - - BATT_ESC_SEC - BATT is escalting ssecure event - 0 - 1 - read-only - - - - - - - RTC - RTC - RTC - 0xf4244000 - - 0x0 - 0x28 - registers - - - - SECOND - Second counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - SECOND - second counter - 0 - 32 - read-write - - - - - SUBSEC - Sub-second counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - SUBSEC - sub second counter - 0 - 32 - read-only - - - - - SEC_SNAP - Second counter snap shot - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - SEC_SNAP - second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - SUB_SNAP - Sub-second counter snap shot - 0xc - 32 - 0x00000000 - 0xFFFFFFFF - - - SUB_SNAP - sub second snap shot, write to take snap shot - 0 - 32 - read-write - - - - - ALARM0 - RTC alarm0 - 0x10 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM0_INC - Alarm0 incremental - 0x14 - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM1 - RTC alarm1 - 0x18 - 32 - 0x00000000 - 0xFFFFFFFF - - - ALARM - Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - 0 - 32 - read-write - - - - - ALARM1_INC - Alarm1 incremental - 0x1c - 32 - 0x00000000 - 0xFFFFFFFF - - - INCREASE - adder when ARLAM0 happen, helps to create periodical alarm - 0 - 32 - read-write - - - - - ALARM_FLAG - RTC alarm flag - 0x20 - 32 - 0x00000000 - 0x00000003 - - - ALARM1 - alarm1 happen - 1 - 1 - read-write - - - ALARM0 - alarm0 happen - 0 - 1 - read-write - - - - - ALARM_EN - RTC alarm enable - 0x24 - 32 - 0x00000000 - 0x00000003 - - - ENABLE1 - alarm1 mask -0: alarm1 disabled -1: alarm1 enabled - 1 - 1 - read-write - - - ENABLE0 - alarm0 mask -0: alarm0 disabled -1: alarm0 enabled - 0 - 1 - read-write - - - - - - - BKEY - BKEY - BKEY - 0xf4248000 - - 0x0 - 0x4c - registers - - - - 2 - 0x20 - 0,1 - KEY[%s] - no description available - 0x0 - - 8 - 0x4 - 0,1,2,3,4,5,6,7 - DATA[%s] - no description available - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - DATA - security key data - 0 - 32 - read-write - - - - - - 2 - 0x4 - KEY0,KEY1 - ECC[%s] - no description available - 0x40 - 32 - 0x00000000 - 0xC000FFFF - - - WLOCK - write lock to key0 -0: write enable -1: write ignored - 31 - 1 - read-write - - - RLOCK - read lock to key0 -0: key read enable -1: key always read as 0 - 30 - 1 - read-write - - - ECC - Parity check bits for key0 - 0 - 16 - read-write - - - - - SELECT - Key selection - 0x48 - 32 - 0x00000000 - 0x00000001 - - - SELECT - select key, key0 treated as secure key, in non-scure mode, only key1 can be selected -0: select key0 in secure mode, key1 in non-secure mode -1: select key1 in secure or nonsecure mode - 0 - 1 - read-write - - - - - - - BMON - BMON - BMON - 0xf424c000 - - 0x0 - 0x20 - registers - - - - 2 - 0x10 - glitch0,clock0 - MONITOR[%s] - no description available - 0x0 - - CONTROL - Glitch and clock monitor control - 0x0 - 32 - 0x00000000 - 0x00000011 - - - ACTIVE - select glitch works in active mode or passve mode. -0: passive mode, depends on power glitch destroy DFF value -1: active mode, check glitch by DFF chain - 4 - 1 - read-write - - - ENABLE - enable glitch detector -0: detector disabled -1: detector enabled - 0 - 1 - read-write - - - - - STATUS - Glitch and clock monitor status - 0x4 - 32 - 0x00000000 - 0x00000001 - - - FLAG - flag for glitch detected, write 1 to clear this flag -0: glitch not detected -1: glitch detected - 0 - 1 - read-write - - - - - - - - TAMP - TAMP - TAMP - 0xf4250000 - - 0x0 - 0x88 - registers - - - - 4 - 0x10 - tamp0,tamp1,tamp2,tamp3 - TAMP[%s] - no description available - 0x0 - - CONTROL - Tamper n control - 0x0 - 32 - 0x00000000 - 0x801F03F7 - - - LOCK - lock tamper setting -0: tamper setting can be changed -1: tamper setting will last to next battery domain power cycle - 31 - 1 - read-write - - - BYPASS - bypass tamper violation filter -0: filter applied -1: filter not used - 20 - 1 - read-write - - - FILTER - filter length -0: 1 cycle -1: 2 cycle -15: 65526 cycle - 16 - 4 - read-write - - - VALUE - pin value for passive tamper - 8 - 2 - read-write - - - SPEED - tamper speed selection, (2^SPEED) changes per second -0: 1 shift per second -1: 2 shifts per second -. . . -15: 32768 shifts per second - 4 - 4 - read-write - - - RECOVER - tamper will recover itself if tamper LFSR goes wrong -0: tamper will not recover -1: tamper will recover - 2 - 1 - read-write - - - ACTIVE - select active or passive tamper -0: passive tamper -1: active tamper - 1 - 1 - read-write - - - ENABLE - enable tamper -0: tamper disableed -1: tamper enabled - 0 - 1 - read-write - - - - - POLY - Tamper n Polynomial of LFSR - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - POLY - tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - 0 - 32 - read-write - - - - - LFSR - Tamper n LFSR shift register - 0x8 - 32 - 0x00000000 - 0xFFFFFFFF - - - LFSR - LFSR for active tamper, write only register, always read 0 - 0 - 32 - write-only - - - - - - TAMP_FLAG - Tamper flag - 0x80 - 32 - 0x00000000 - 0x00000FFF - - - FLAG - tamper flag, each bit represents one tamper pin, write 1 to clear the flag -Note, clear can only be cleared when tamper disappeared - 0 - 12 - read-write - - - - - IRQ_EN - Tamper interrupt enable - 0x84 - 32 - 0x00000000 - 0x80000FFF - - - LOCK - lock bit for IRQ enable -0: enable bits can be changed -1: enable bits hold until next battery domain power cycle - 31 - 1 - read-write - - - IRQ_EN - interrupt enable, each bit represents one tamper pin -0: interrupt disabled -1: interrupt enabled - 0 - 12 - read-write - - - - - - - MONO - MONO - MONO - 0xf4254000 - - 0x0 - 0x8 - registers - - - - MONOL - Low part of monotonic counter - 0x0 - 32 - 0x00000000 - 0xFFFFFFFF - - - COUNTER - low part of monotonica counter, write to this counter will cause counter increase by 1 - 0 - 32 - read-write - - - - - MONOH - High part of monotonic counter - 0x4 - 32 - 0x00000000 - 0xFFFFFFFF - - - EPOCH - Fuse value for high part of monotonica - 16 - 16 - read-write - - - COUNTER - high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - 0 - 16 - read-write - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/SConscript b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/SConscript deleted file mode 100644 index 5717c3e6317..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/SConscript +++ /dev/null @@ -1,25 +0,0 @@ -import os -import sys -Import('rtconfig') -from building import * - -#get current directory -cwd = GetCurrentDir() - -# Update include path -path = [ cwd, cwd + '/boot' ] - -# The set of source files associated with this SConscript file. -src = Split(''' - system.c - hpm_l1c_drv.c - hpm_sysctl_drv.c - hpm_clock_drv.c - hpm_otp_drv.c - boot/hpm_bootheader.c -''') - - -group = DefineGroup('SoC', src, depend = [''], CPPPATH = path) - -Return ('group') diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot/hpm_bootheader.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot/hpm_bootheader.c deleted file mode 100644 index 57cdf5aa2e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot/hpm_bootheader.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_bootheader.h" - -/* symbol exported from startup.S */ -extern uint32_t _start[]; - -/* following symbols exported from linker script */ -extern uint32_t __app_load_addr__[]; -extern uint32_t __app_offset__[]; -extern uint32_t __fw_size__[]; - -#define FW_SIZE (32768) -__attribute__ ((section(".fw_info_table"))) const fw_info_table_t fw_info = { - (uint32_t)__app_offset__, /* offset */ - (uint32_t)__fw_size__, /* size */ - 0, /* flags */ - 0, /* reserved0 */ - (uint32_t) &__app_load_addr__, /* load_addr */ - 0, /* reserved1 */ - (uint32_t) _start, /* entry_point */ - 0, /* reserved2 */ - {0}, /* hash */ - {0}, /* iv */ -}; - -__attribute__ ((section(".boot_header"))) const boot_header_t header = { - HPM_BOOTHEADER_TAG, /* tag */ - 0x10, /* version*/ - sizeof(header) + sizeof(fw_info), - 0, /* flags */ - 0, /* sw_version */ - 0, /* fuse_version */ - 1, /* fw_count */ - 0, - 0, /* sig_block_offset */ -}; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot/hpm_bootheader.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot/hpm_bootheader.h deleted file mode 100644 index d7f22fd8240..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/boot/hpm_bootheader.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BOOT_HEADER_H -#define HPM_BOOT_HEADER_H - -#include "hpm_common.h" - -#define HPM_BOOTHEADER_TAG (0xBFU) -#define HPM_BOOTHEADER_MAX_FW_COUNT (2U) - -#ifndef HPM_BOOT_FW_COUNT -#define HPM_BOOT_FW_COUNT 1 -#endif - -#if HPM_BOOT_FW_COUNT < 1 -#error "HPM_BOOT_FW_COUNT can't be less than 1" -#endif - -typedef struct { - uint32_t offset; /* 0x0: offset to boot_header start */ - uint32_t size; /* 0x4: size in bytes */ - uint32_t flags; /* 0x8: [3:0] fw type: */ - /* 0 - executable */ - /* 1 - cmd container */ - /* [11:8] - hash type */ - /* 0 - none */ - /* 1 - sha256 */ - /* 2 - sm3 */ - uint32_t reserved0; /* 0xC */ - uint32_t load_addr; /* 0x10: load address */ - uint32_t reserved1; /* 0x14 */ - uint32_t entry_point; /* 0x18: application entry */ - uint32_t reserved2; /* 0x1C */ - uint8_t hash[64]; /* 0x20: hash value */ - uint8_t iv[32]; /* 0x60: initial vector */ -} fw_info_table_t; - -typedef struct { - uint8_t tag; /* 0x0: must be '0xbf' */ - uint8_t version; /* 0x1: header version */ - uint16_t length; /* 0x2: header length, max 8KB */ - uint32_t flags; /* 0x4: [3:0] SRK set */ - /* [7:4] SRK index */ - /* [15:8] SRK_REVOKE_MASK */ - /* [19:16] Signature Type */ - /* 1: ECDSA */ - /* 2: SM2 */ - uint16_t sw_version; /* 0x8: software version */ - uint8_t fuse_version; /* 0xA: fuse version */ - uint8_t fw_count; /* 0xB: number of fw */ - uint16_t dc_block_offset; /* 0xC: device config block offset*/ - uint16_t sig_block_offset; /* 0xE: signature block offset */ - /* - * fw_info_table_t fw_info[HPM_BOOT_FW_COUNT]; [> 0x10: fw table <] - * uint32_t dc_info[]; [> <] - */ -} boot_header_t; - -#endif /* HPM_BOOT_HEADER_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_batt_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_batt_iomux.h deleted file mode 100644 index 063788254d5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_batt_iomux.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BATT_IOMUX_H -#define HPM_BATT_IOMUX_H - -/* BIOC_PZ00_FUNC_CTL function mux definitions */ -#define BIOC_PZ00_FUNC_CTL_BGPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ00_FUNC_CTL_TAMP_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ00_FUNC_CTL_SOC_PZ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ01_FUNC_CTL function mux definitions */ -#define BIOC_PZ01_FUNC_CTL_BGPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ01_FUNC_CTL_TAMP_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ01_FUNC_CTL_SOC_PZ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ02_FUNC_CTL function mux definitions */ -#define BIOC_PZ02_FUNC_CTL_BGPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ02_FUNC_CTL_TAMP_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ02_FUNC_CTL_SOC_PZ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ03_FUNC_CTL function mux definitions */ -#define BIOC_PZ03_FUNC_CTL_BGPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ03_FUNC_CTL_TAMP_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ03_FUNC_CTL_SOC_PZ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ04_FUNC_CTL function mux definitions */ -#define BIOC_PZ04_FUNC_CTL_BGPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ04_FUNC_CTL_TAMP_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ04_FUNC_CTL_SOC_PZ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ05_FUNC_CTL function mux definitions */ -#define BIOC_PZ05_FUNC_CTL_BGPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ05_FUNC_CTL_TAMP_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ05_FUNC_CTL_SOC_PZ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ06_FUNC_CTL function mux definitions */ -#define BIOC_PZ06_FUNC_CTL_BGPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ06_FUNC_CTL_TAMP_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ06_FUNC_CTL_SOC_PZ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* BIOC_PZ07_FUNC_CTL function mux definitions */ -#define BIOC_PZ07_FUNC_CTL_BGPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define BIOC_PZ07_FUNC_CTL_TAMP_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define BIOC_PZ07_FUNC_CTL_SOC_PZ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_BATT_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_bcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_bcfg_drv.h deleted file mode 100644 index 2a6b23c8a52..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_bcfg_drv.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BCFG_DRV_H -#define HPM_BCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_bcfg_regs.h" - -/** - * - * @brief BCFG driver APIs - * @defgroup bcfg_interface BCFG driver APIs - * @ingroup io_interfaces - * @{ - */ - - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief enable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_enable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG |= BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -/** - * @brief disable power save mode - * - * @param[in] ptr base address - */ -static inline void bcfg_vbg_disable_power_save_mode(BCFG_Type *ptr) -{ - ptr->VBG_CFG &= ~BCFG_VBG_CFG_POWER_SAVE_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BCFG_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_bpor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_bpor_drv.h deleted file mode 100644 index 76f3c0481a3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_bpor_drv.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_BPOR_DRV_H -#define HPM_BPOR_DRV_H - -#include "hpm_common.h" -#include "hpm_bpor_regs.h" - -/** - * - * @brief BPOR driver APIs - * @defgroup bpor_interface BPOR driver APIs - * @ingroup io_interfaces - * @{ - * - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Enable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_enable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG |= BPOR_POR_CONFIG_RETENTION_MASK; -} - -/** - * @brief Disable register value retention when power down occurs - * - * @param[in] ptr BPOR base address - */ -static inline void bpor_disable_reg_value_retention(BPOR_Type *ptr) -{ - ptr->POR_CONFIG &= ~BPOR_POR_CONFIG_RETENTION_MASK; -} - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_BPOR_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_clock_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_clock_drv.c deleted file mode 100644 index 84cfe098226..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_clock_drv.c +++ /dev/null @@ -1,522 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_clock_drv.h" -#include "hpm_sysctl_drv.h" -#include "hpm_soc.h" -#include "hpm_common.h" -#include "hpm_pllctlv2_drv.h" -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -/* Clock preset values */ -#define FREQ_PRESET1_OSC0_CLK0 (24000000UL) -#define FREQ_PRESET1_PLL0_CLK0 (600000000UL) -#define FREQ_PRESET1_PLL0_CLK1 (500000000UL) -#define FREQ_PRESET1_PLL1_CLK0 (800000000UL) -#define FREQ_PRESET1_PLL1_CLK1 (333333333UL) -#define FREQ_PRESET1_PLL1_CLK2 (250000000UL) -#define FREQ_PRESET1_PLL2_CLK0 (516096000UL) -#define FREQ_PRESET1_PLL2_CLK1 (451584000UL) -#define FREQ_32KHz (32768UL) -#define ADC_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->ADCCLK) -#define I2S_INSTANCE_NUM ARRAY_SIZE(HPM_SYSCTL->I2SCLK) -#define EWDG_INSTANCE_NUM (4U) -#define BUS_FREQ_MAX (200000000UL) -#define FREQ_1MHz (1000000UL) - - -/* Clock On/Off definitions */ -#define CLOCK_ON (true) -#define CLOCK_OFF (false) - - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -/** - * @brief Get Clock frequency for IP in common group - */ -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node); - -/** - * @brief Get Clock frequency for ADC - */ -static uint32_t get_frequency_for_adc(uint32_t instance); - -/** - * @brief Get Clock frequency for I2S - */ -static uint32_t get_frequency_for_i2s(uint32_t instance); - -/** - * @brief Get Clock frequency for EWDG - */ -static uint32_t get_frequency_for_ewdg(uint32_t instance); - -/** - * @brief Get Clock frequency for PEWDG - */ -static uint32_t get_frequency_for_pewdg(void); - -/** - * @brief Turn on/off the IP clock - */ -static void switch_ip_clock(clock_name_t clock_name, bool on); - -/*********************************************************************************************************************** - * Variables - **********************************************************************************************************************/ -static const clock_node_t s_adc_clk_mux_node[] = { - clock_node_ana0, - clock_node_ahb0, -}; - -static EWDG_Type *const s_wdgs[] = { - HPM_EWDG0, - HPM_EWDG1, - HPM_EWDG2, - HPM_EWDG3, -}; - -uint32_t hpm_core_clock; - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -uint32_t clock_get_frequency(clock_name_t clock_name) -{ - uint32_t clk_freq = 0UL; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_freq = get_frequency_for_ip_in_common_group((clock_node_t) node_or_instance); - break; - case CLK_SRC_GROUP_ADC: - clk_freq = get_frequency_for_adc(node_or_instance); - break; - case CLK_SRC_GROUP_I2S: - clk_freq = get_frequency_for_i2s(node_or_instance); - break; - case CLK_SRC_GROUP_EWDG: - clk_freq = get_frequency_for_ewdg(node_or_instance); - break; - case CLK_SRC_GROUP_PEWDG: - clk_freq = get_frequency_for_pewdg(); - break; - case CLK_SRC_GROUP_PMIC: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case CLK_SRC_GROUP_AHB: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); - break; - case CLK_SRC_GROUP_AXIF: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axif); - break; - case CLK_SRC_GROUP_AXIS: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axis); - break; - case CLK_SRC_GROUP_AXIC: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axic); - break; - case CLK_SRC_GROUP_AXIN: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_axin); - break; - case CLK_SRC_GROUP_CPU0: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_cpu0); - break; - case CLK_SRC_GROUP_CPU1: - clk_freq = get_frequency_for_ip_in_common_group(clock_node_cpu1); - break; - case CLK_SRC_GROUP_SRC: - clk_freq = get_frequency_for_source((clock_source_t) node_or_instance); - break; - default: - clk_freq = 0UL; - break; - } - return clk_freq; -} - -uint32_t get_frequency_for_source(clock_source_t source) -{ - uint32_t clk_freq = 0UL; - switch (source) { - case clock_source_osc0_clk0: - clk_freq = FREQ_PRESET1_OSC0_CLK0; - break; - case clock_source_pll0_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 0U); - break; - case clock_source_pll0_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 0U, 1U); - break; - case clock_source_pll1_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 0U); - break; - case clock_source_pll1_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 1U); - break; - case clock_source_pll1_clk2: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 1U, 2U); - break; - case clock_source_pll2_clk0: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 0U); - break; - case clock_source_pll2_clk1: - clk_freq = pllctlv2_get_pll_postdiv_freq_in_hz(HPM_PLLCTLV2, 2U, 1U); - break; - default: - clk_freq = 0UL; - break; - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ip_in_common_group(clock_node_t node) -{ - uint32_t clk_freq = 0UL; - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(node); - - if (node_or_instance < clock_node_end) { - uint32_t clk_node = (uint32_t) node_or_instance; - - uint32_t clk_div = 1UL + SYSCTL_CLOCK_DIV_GET(HPM_SYSCTL->CLOCK[clk_node]); - clock_source_t clk_mux = (clock_source_t) SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[clk_node]); - clk_freq = get_frequency_for_source(clk_mux) / clk_div; - } - return clk_freq; -} - -static uint32_t get_frequency_for_adc(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - bool is_mux_valid = false; - clock_node_t node = clock_node_end; - if (instance < ADC_INSTANCE_NUM) { - uint32_t mux_in_reg = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[instance]); - if (mux_in_reg < ARRAY_SIZE(s_adc_clk_mux_node)) { - node = s_adc_clk_mux_node[mux_in_reg]; - is_mux_valid = true; - } - } - - if (is_mux_valid) { - if (node == clock_node_ahb0) { - clk_freq = get_frequency_for_ip_in_common_group(clock_node_ahb0); - } else { - node += instance; - clk_freq = get_frequency_for_ip_in_common_group(node); - } - } - return clk_freq; -} - -static uint32_t get_frequency_for_i2s(uint32_t instance) -{ - uint32_t clk_freq = 0UL; - clock_node_t node; - uint32_t mux_in_reg; - - if (instance < I2S_INSTANCE_NUM) { - mux_in_reg = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[instance]); - if (mux_in_reg == 0) { - node = clock_node_aud0 + instance; - } else if (instance == 0) { - node = clock_node_aud1; - } else { - node = clock_node_aud0; - } - clk_freq = get_frequency_for_ip_in_common_group(node); - } - - return clk_freq; -} - -static uint32_t get_frequency_for_ewdg(uint32_t instance) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(s_wdgs[instance]->CTRL0) == 0) { - freq_in_hz = get_frequency_for_ip_in_common_group(clock_node_ahb0); - } else { - freq_in_hz = FREQ_32KHz; - } - return freq_in_hz; -} - -static uint32_t get_frequency_for_pewdg(void) -{ - uint32_t freq_in_hz; - if (EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0) == 0) { - freq_in_hz = FREQ_PRESET1_OSC0_CLK0; - } else { - freq_in_hz = FREQ_32KHz; - } - - return freq_in_hz; -} - -clk_src_t clock_get_source(clock_name_t clock_name) -{ - uint8_t clk_src_group = CLK_SRC_GROUP_INVALID; - uint8_t clk_src_index = 0xFU; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = SYSCTL_CLOCK_MUX_GET(HPM_SYSCTL->CLOCK[node_or_instance]); - break; - case CLK_SRC_GROUP_ADC: - if (node_or_instance < ADC_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_ADC; - clk_src_index = SYSCTL_ADCCLK_MUX_GET(HPM_SYSCTL->ADCCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_I2S: - if (node_or_instance < I2S_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_I2S; - clk_src_index = SYSCTL_I2SCLK_MUX_GET(HPM_SYSCTL->I2SCLK[node_or_instance]); - } - break; - case CLK_SRC_GROUP_EWDG: - if (node_or_instance < EWDG_INSTANCE_NUM) { - clk_src_group = CLK_SRC_GROUP_EWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(s_wdgs[node_or_instance]->CTRL0); - } - break; - case CLK_SRC_GROUP_PEWDG: - clk_src_group = CLK_SRC_GROUP_PEWDG; - clk_src_index = EWDG_CTRL0_CLK_SEL_GET(HPM_PEWDG->CTRL0); - break; - case CLK_SRC_GROUP_PMIC: - clk_src_group = CLK_SRC_GROUP_COMMON; - clk_src_index = clock_source_osc0_clk0; - break; - case CLK_SRC_GROUP_SRC: - clk_src_index = (clk_src_t) node_or_instance; - break; - default: - clk_src_group = CLK_SRC_GROUP_INVALID; - break; - } - - clk_src_t clk_src; - if (clk_src_group != CLK_SRC_GROUP_INVALID) { - clk_src = MAKE_CLK_SRC(clk_src_group, clk_src_index); - } else { - clk_src = clk_src_invalid; - } - - return clk_src; -} - -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_ADC) || (node_or_instance >= ADC_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_adc_src_ana0) || (src > clk_adc_src_ahb0)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->ADCCLK[node_or_instance] = - (HPM_SYSCTL->ADCCLK[node_or_instance] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - - if ((clk_src_type != CLK_SRC_GROUP_I2S) || (node_or_instance >= I2S_INSTANCE_NUM)) { - return status_clk_invalid; - } - - if ((src < clk_i2s_src_aud0) || (src > clk_i2s_src_audx)) { - return status_clk_src_invalid; - } - - uint32_t clk_src_index = GET_CLK_SRC_INDEX(src); - HPM_SYSCTL->I2SCLK[node_or_instance] = - (HPM_SYSCTL->I2SCLK[node_or_instance] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(clk_src_index); - - return status_success; -} - -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src) -{ - uint32_t clk_src_grp = GET_CLK_SRC_GROUP(clock_name); - if ((clk_src_grp != CLK_SRC_GROUP_EWDG) && (clk_src_grp != CLK_SRC_GROUP_PEWDG)) { - return status_invalid_argument; - } - if (clock_name == clock_pwdg) { - if ((src == clk_pwdg_src_osc24m) || (src == clk_pwdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_pwdg_src_osc24m); - HPM_PEWDG->CTRL0 = (HPM_PEWDG->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } else { - uint32_t instance = GET_CLK_SRC_INDEX(clock_name); - if ((src == clk_wdg_src_ahb0) || (src == clk_wdg_src_osc32k)) { - uint32_t wdg_clk_src_in_ip = (uint32_t)(src - clk_wdg_src_ahb0); - s_wdgs[instance]->CTRL0 = (s_wdgs[instance]->CTRL0 & ~EWDG_CTRL0_CLK_SEL_MASK) | EWDG_CTRL0_CLK_SEL_SET(wdg_clk_src_in_ip); - } else { - return status_invalid_argument; - } - } - return status_success; -} - -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div) -{ - hpm_stat_t status = status_success; - uint32_t clk_src_type = GET_CLK_SRC_GROUP_FROM_NAME(clock_name); - uint32_t node_or_instance = GET_CLK_NODE_FROM_NAME(clock_name); - switch (clk_src_type) { - case CLK_SRC_GROUP_COMMON: - if ((div < 1U) || (div > 256U)) { - status = status_clk_div_invalid; - } else { - clock_source_t source = GET_CLOCK_SOURCE_FROM_CLK_SRC(src); - sysctl_config_clock(HPM_SYSCTL, (clock_node_t) node_or_instance, source, div); - } - break; - case CLK_SRC_GROUP_ADC: - case CLK_SRC_GROUP_I2S: - case CLK_SRC_GROUP_EWDG: - case CLK_SRC_GROUP_PEWDG: - case CLK_SRC_GROUP_SRC: - status = status_clk_operation_unsupported; - break; - case CLK_SRC_GROUP_PMIC: - status = status_clk_fixed; - break; - case CLK_SRC_GROUP_AHB: - status = status_clk_shared_ahb; - break; - case CLK_SRC_GROUP_AXIF: - status = status_clk_shared_axif; - break; - case CLK_SRC_GROUP_AXIS: - status = status_clk_shared_axis; - break; - case CLK_SRC_GROUP_AXIC: - status = status_clk_shared_axic; - break; - case CLK_SRC_GROUP_AXIN: - status = status_clk_shared_axin; - break; - case CLK_SRC_GROUP_CPU0: - status = status_clk_shared_cpu0; - break; - case CLK_SRC_GROUP_CPU1: - status = status_clk_shared_cpu1; - break; - default: - status = status_clk_src_invalid; - break; - } - - return status; -} - -static void switch_ip_clock(clock_name_t clock_name, bool on) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - uint32_t mode = on ? 1UL : 2UL; - HPM_SYSCTL->RESOURCE[resource] = - (HPM_SYSCTL->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | SYSCTL_RESOURCE_MODE_SET(mode); - } -} - -void clock_enable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_ON); -} - -void clock_disable(clock_name_t clock_name) -{ - switch_ip_clock(clock_name, CLOCK_OFF); -} - -void clock_add_to_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, true); - } -} - -void clock_remove_from_group(clock_name_t clock_name, uint32_t group) -{ - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - sysctl_enable_group_resource(HPM_SYSCTL, group, resource, false); - } -} - -bool clock_check_in_group(clock_name_t clock_name, uint32_t group) -{ - bool added = false; - uint32_t resource = GET_CLK_RESOURCE_FROM_NAME(clock_name); - - if (resource < sysctl_resource_end) { - added = sysctl_check_group_resource_enable(HPM_SYSCTL, group, resource); - } - return added; -} - -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].SET = (1UL << group); - } -} - -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu) -{ - if (cpu < 2U) { - HPM_SYSCTL->AFFILIATE[cpu].CLEAR = (1UL << group); - } -} - -void clock_cpu_delay_us(uint32_t us) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + ticks_per_us * us; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_cpu_delay_ms(uint32_t ms) -{ - uint32_t ticks_per_us = (hpm_core_clock + FREQ_1MHz - 1U) / FREQ_1MHz; - uint64_t expected_ticks = hpm_csr_get_core_cycle() + (uint64_t)ticks_per_us * 1000UL * ms; - while (hpm_csr_get_core_cycle() < expected_ticks) { - } -} - -void clock_update_core_clock(void) -{ - hpm_core_clock = clock_get_frequency(clock_cpu0); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_clock_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_clock_drv.h deleted file mode 100644 index 06da356fab7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_clock_drv.h +++ /dev/null @@ -1,433 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_CLOCK_DRV_H -#define HPM_CLOCK_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_drv.h" - - -/** - * @brief Error codes for clock driver - */ -enum { - status_clk_div_invalid = MAKE_STATUS(status_group_clk, 0), - status_clk_src_invalid = MAKE_STATUS(status_group_clk, 1), - status_clk_invalid = MAKE_STATUS(status_group_clk, 2), - status_clk_operation_unsupported = MAKE_STATUS(status_group_clk, 3), - status_clk_shared_ahb = MAKE_STATUS(status_group_clk, 4), - status_clk_shared_axif = MAKE_STATUS(status_group_clk, 5), - status_clk_shared_axis = MAKE_STATUS(status_group_clk, 6), - status_clk_shared_axic = MAKE_STATUS(status_group_clk, 7), - status_clk_shared_axin = MAKE_STATUS(status_group_clk, 8), - status_clk_shared_cpu0 = MAKE_STATUS(status_group_clk, 9), - status_clk_shared_cpu1 = MAKE_STATUS(status_group_clk, 10), - status_clk_fixed = MAKE_STATUS(status_group_clk, 11), -}; - -/** - * @brief Clock source group definitions - */ -#define CLK_SRC_GROUP_COMMON (0U) -#define CLK_SRC_GROUP_ADC (1U) -#define CLK_SRC_GROUP_I2S (2U) -#define CLK_SRC_GROUP_EWDG (3U) -#define CLK_SRC_GROUP_AHB (4U) -#define CLK_SRC_GROUP_AXIF (5U) -#define CLK_SRC_GROUP_AXIS (6U) -#define CLK_SRC_GROUP_AXIC (7U) -#define CLK_SRC_GROUP_AXIN (8U) -#define CLK_SRC_GROUP_PMIC (9U) -#define CLK_SRC_GROUP_PEWDG (10U) -#define CLK_SRC_GROUP_CPU0 (11U) -#define CLK_SRC_GROUP_CPU1 (12U) -#define CLK_SRC_GROUP_SRC (13U) -#define CLK_SRC_GROUP_INVALID (14U) - -#define MAKE_CLK_SRC(src_grp, index) (((uint8_t)(src_grp)<<4) | (index)) -#define GET_CLK_SRC_GROUP(src) (((uint8_t)(src)>>4) & 0x0FU) -#define GET_CLK_SRC_INDEX(src) ((uint8_t)(src) & 0x0FU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/** - * @brief Clock source definitions - */ -typedef enum _clock_sources { - clk_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 0), - clk_src_pll0_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 1), - clk_src_pll0_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 2), - clk_src_pll1_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 3), - clk_src_pll1_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 4), - clk_src_pll1_clk2 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 5), - clk_src_pll2_clk0 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 6), - clk_src_pll2_clk1 = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 7), - clk_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_COMMON, 8), - - clk_adc_src_ana0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana1 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana2 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ana3 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 0), - clk_adc_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_ADC, 1), - - clk_i2s_src_aud0 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_aud1 = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 0), - clk_i2s_src_audx = MAKE_CLK_SRC(CLK_SRC_GROUP_I2S, 1), - - clk_wdg_src_ahb0 = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 0), - clk_wdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_EWDG, 1), - - clk_pwdg_src_osc24m = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 0), - clk_pwdg_src_osc32k = MAKE_CLK_SRC(CLK_SRC_GROUP_PEWDG, 1), - - clk_src_invalid = MAKE_CLK_SRC(CLK_SRC_GROUP_INVALID, 15), -} clk_src_t; - -#define RESOURCE_INVALID (0xFFFFU) - -#define GET_CLOCK_SOURCE_FROM_CLK_SRC(clk_src) (clock_source_t)((uint32_t)(clk_src) & 0xFU) - -/* Clock NAME related Macros */ -#define MAKE_CLOCK_NAME(resource, src_type, node) (((uint32_t)(resource) << 16) | ((uint32_t)(src_type) << 8) | ((uint32_t)node)) -#define GET_CLK_SRC_GROUP_FROM_NAME(name) (((uint32_t)(name) >> 8) & 0xFFUL) -#define GET_CLK_NODE_FROM_NAME(name) ((uint32_t)(name) & 0xFFUL) -#define GET_CLK_RESOURCE_FROM_NAME(name) ((uint32_t)(name) >> 16) - -/** - * @brief Peripheral Clock Type Description - */ -typedef enum _clock_name { - clock_cpu0 = MAKE_CLOCK_NAME(sysctl_resource_cpu0, CLK_SRC_GROUP_COMMON, clock_node_cpu0), - clock_mchtmr0 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr0, CLK_SRC_GROUP_COMMON, clock_node_mchtmr0), - clock_cpu1 = MAKE_CLOCK_NAME(sysctl_resource_cpu1, CLK_SRC_GROUP_COMMON, clock_node_cpu1), - clock_mchtmr1 = MAKE_CLOCK_NAME(sysctl_resource_mchtmr1, CLK_SRC_GROUP_COMMON, clock_node_mchtmr1), - clock_ahb0 = MAKE_CLOCK_NAME(sysctl_resource_ahbp, CLK_SRC_GROUP_COMMON, clock_node_ahb0), - clock_axif = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_axif), - clock_axis = MAKE_CLOCK_NAME(sysctl_resource_axis, CLK_SRC_GROUP_COMMON, clock_node_axis), - clock_axic = MAKE_CLOCK_NAME(sysctl_resource_axic, CLK_SRC_GROUP_COMMON, clock_node_axic), - clock_axin = MAKE_CLOCK_NAME(sysctl_resource_axin, CLK_SRC_GROUP_COMMON, clock_node_axin), - clock_gptmr0 = MAKE_CLOCK_NAME(sysctl_resource_gptmr0, CLK_SRC_GROUP_COMMON, clock_node_gptmr0), - clock_gptmr1 = MAKE_CLOCK_NAME(sysctl_resource_gptmr1, CLK_SRC_GROUP_COMMON, clock_node_gptmr1), - clock_gptmr2 = MAKE_CLOCK_NAME(sysctl_resource_gptmr2, CLK_SRC_GROUP_COMMON, clock_node_gptmr2), - clock_gptmr3 = MAKE_CLOCK_NAME(sysctl_resource_gptmr3, CLK_SRC_GROUP_COMMON, clock_node_gptmr3), - clock_gptmr4 = MAKE_CLOCK_NAME(sysctl_resource_gptmr4, CLK_SRC_GROUP_COMMON, clock_node_gptmr4), - clock_gptmr5 = MAKE_CLOCK_NAME(sysctl_resource_gptmr5, CLK_SRC_GROUP_COMMON, clock_node_gptmr5), - clock_gptmr6 = MAKE_CLOCK_NAME(sysctl_resource_gptmr6, CLK_SRC_GROUP_COMMON, clock_node_gptmr6), - clock_gptmr7 = MAKE_CLOCK_NAME(sysctl_resource_gptmr7, CLK_SRC_GROUP_COMMON, clock_node_gptmr7), - clock_i2c0 = MAKE_CLOCK_NAME(sysctl_resource_i2c0, CLK_SRC_GROUP_COMMON, clock_node_i2c0), - clock_i2c1 = MAKE_CLOCK_NAME(sysctl_resource_i2c1, CLK_SRC_GROUP_COMMON, clock_node_i2c1), - clock_i2c2 = MAKE_CLOCK_NAME(sysctl_resource_i2c2, CLK_SRC_GROUP_COMMON, clock_node_i2c2), - clock_i2c3 = MAKE_CLOCK_NAME(sysctl_resource_i2c3, CLK_SRC_GROUP_COMMON, clock_node_i2c3), - clock_i2c4 = MAKE_CLOCK_NAME(sysctl_resource_i2c4, CLK_SRC_GROUP_COMMON, clock_node_i2c4), - clock_i2c5 = MAKE_CLOCK_NAME(sysctl_resource_i2c5, CLK_SRC_GROUP_COMMON, clock_node_i2c5), - clock_i2c6 = MAKE_CLOCK_NAME(sysctl_resource_i2c6, CLK_SRC_GROUP_COMMON, clock_node_i2c6), - clock_i2c7 = MAKE_CLOCK_NAME(sysctl_resource_i2c7, CLK_SRC_GROUP_COMMON, clock_node_i2c7), - clock_spi0 = MAKE_CLOCK_NAME(sysctl_resource_spi0, CLK_SRC_GROUP_COMMON, clock_node_spi0), - clock_spi1 = MAKE_CLOCK_NAME(sysctl_resource_spi1, CLK_SRC_GROUP_COMMON, clock_node_spi1), - clock_spi2 = MAKE_CLOCK_NAME(sysctl_resource_spi2, CLK_SRC_GROUP_COMMON, clock_node_spi2), - clock_spi3 = MAKE_CLOCK_NAME(sysctl_resource_spi3, CLK_SRC_GROUP_COMMON, clock_node_spi3), - clock_spi4 = MAKE_CLOCK_NAME(sysctl_resource_spi4, CLK_SRC_GROUP_COMMON, clock_node_spi4), - clock_spi5 = MAKE_CLOCK_NAME(sysctl_resource_spi5, CLK_SRC_GROUP_COMMON, clock_node_spi5), - clock_spi6 = MAKE_CLOCK_NAME(sysctl_resource_spi6, CLK_SRC_GROUP_COMMON, clock_node_spi6), - clock_spi7 = MAKE_CLOCK_NAME(sysctl_resource_spi7, CLK_SRC_GROUP_COMMON, clock_node_spi7), - clock_uart0 = MAKE_CLOCK_NAME(sysctl_resource_uart0, CLK_SRC_GROUP_COMMON, clock_node_uart0), - clock_uart1 = MAKE_CLOCK_NAME(sysctl_resource_uart1, CLK_SRC_GROUP_COMMON, clock_node_uart1), - clock_uart2 = MAKE_CLOCK_NAME(sysctl_resource_uart2, CLK_SRC_GROUP_COMMON, clock_node_uart2), - clock_uart3 = MAKE_CLOCK_NAME(sysctl_resource_uart3, CLK_SRC_GROUP_COMMON, clock_node_uart3), - clock_uart4 = MAKE_CLOCK_NAME(sysctl_resource_uart4, CLK_SRC_GROUP_COMMON, clock_node_uart4), - clock_uart5 = MAKE_CLOCK_NAME(sysctl_resource_uart5, CLK_SRC_GROUP_COMMON, clock_node_uart5), - clock_uart6 = MAKE_CLOCK_NAME(sysctl_resource_uart6, CLK_SRC_GROUP_COMMON, clock_node_uart6), - clock_uart7 = MAKE_CLOCK_NAME(sysctl_resource_uart7, CLK_SRC_GROUP_COMMON, clock_node_uart7), - clock_uart8 = MAKE_CLOCK_NAME(sysctl_resource_uart8, CLK_SRC_GROUP_COMMON, clock_node_uart8), - clock_uart9 = MAKE_CLOCK_NAME(sysctl_resource_uart9, CLK_SRC_GROUP_COMMON, clock_node_uart9), - clock_uart10 = MAKE_CLOCK_NAME(sysctl_resource_uart10, CLK_SRC_GROUP_COMMON, clock_node_uart10), - clock_uart11 = MAKE_CLOCK_NAME(sysctl_resource_uart11, CLK_SRC_GROUP_COMMON, clock_node_uart11), - clock_uart12 = MAKE_CLOCK_NAME(sysctl_resource_uart12, CLK_SRC_GROUP_COMMON, clock_node_uart12), - clock_uart13 = MAKE_CLOCK_NAME(sysctl_resource_uart13, CLK_SRC_GROUP_COMMON, clock_node_uart13), - clock_uart14 = MAKE_CLOCK_NAME(sysctl_resource_uart14, CLK_SRC_GROUP_COMMON, clock_node_uart14), - clock_uart15 = MAKE_CLOCK_NAME(sysctl_resource_uart15, CLK_SRC_GROUP_COMMON, clock_node_uart15), - clock_can0 = MAKE_CLOCK_NAME(sysctl_resource_can0, CLK_SRC_GROUP_COMMON, clock_node_can0), - clock_can1 = MAKE_CLOCK_NAME(sysctl_resource_can1, CLK_SRC_GROUP_COMMON, clock_node_can1), - clock_can2 = MAKE_CLOCK_NAME(sysctl_resource_can2, CLK_SRC_GROUP_COMMON, clock_node_can2), - clock_can3 = MAKE_CLOCK_NAME(sysctl_resource_can3, CLK_SRC_GROUP_COMMON, clock_node_can3), - clock_can4 = MAKE_CLOCK_NAME(sysctl_resource_can4, CLK_SRC_GROUP_COMMON, clock_node_can4), - clock_can5 = MAKE_CLOCK_NAME(sysctl_resource_can5, CLK_SRC_GROUP_COMMON, clock_node_can5), - clock_can6 = MAKE_CLOCK_NAME(sysctl_resource_can6, CLK_SRC_GROUP_COMMON, clock_node_can6), - clock_can7 = MAKE_CLOCK_NAME(sysctl_resource_can7, CLK_SRC_GROUP_COMMON, clock_node_can7), - clock_xpi0 = MAKE_CLOCK_NAME(sysctl_resource_xpi0, CLK_SRC_GROUP_COMMON, clock_node_xpi0), - clock_femc = MAKE_CLOCK_NAME(sysctl_resource_femc, CLK_SRC_GROUP_COMMON, clock_node_femc), - clock_eth0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_eth0), - clock_ptp0 = MAKE_CLOCK_NAME(sysctl_resource_eth0, CLK_SRC_GROUP_COMMON, clock_node_ptp0), - clock_ntmr0 = MAKE_CLOCK_NAME(sysctl_resource_ntmr0, CLK_SRC_GROUP_COMMON, clock_node_ntmr0), - clock_ref0 = MAKE_CLOCK_NAME(sysctl_resource_ref0, CLK_SRC_GROUP_COMMON, clock_node_ref0), - clock_ref1 = MAKE_CLOCK_NAME(sysctl_resource_ref1, CLK_SRC_GROUP_COMMON, clock_node_ref1), - clock_tsn1 = MAKE_CLOCK_NAME(sysctl_resource_tsn0, CLK_SRC_GROUP_COMMON, clock_node_tsn1), - clock_tsn2 = MAKE_CLOCK_NAME(sysctl_resource_tsn0, CLK_SRC_GROUP_COMMON, clock_node_tsn2), - clock_tsn3 = MAKE_CLOCK_NAME(sysctl_resource_tsn0, CLK_SRC_GROUP_COMMON, clock_node_tsn3), - - clock_crc0 = MAKE_CLOCK_NAME(sysctl_resource_crc0, CLK_SRC_GROUP_AHB, 0), - clock_tsns = MAKE_CLOCK_NAME(sysctl_resource_tsns, CLK_SRC_GROUP_AHB, 0), - clock_mbx0 = MAKE_CLOCK_NAME(sysctl_resource_mbx0, CLK_SRC_GROUP_AHB, 0), - clock_mbx1 = MAKE_CLOCK_NAME(sysctl_resource_mbx1, CLK_SRC_GROUP_AHB, 0), - clock_gpio = MAKE_CLOCK_NAME(sysctl_resource_gpio, CLK_SRC_GROUP_AHB, 0), - clock_ppi0 = MAKE_CLOCK_NAME(sysctl_resource_ppi0, CLK_SRC_GROUP_AHB, 0), - clock_hdma = MAKE_CLOCK_NAME(sysctl_resource_hdma, CLK_SRC_GROUP_AHB, 0), - clock_lobs = MAKE_CLOCK_NAME(sysctl_resource_lobs, CLK_SRC_GROUP_AHB, 0), - clock_cmp0 = MAKE_CLOCK_NAME(sysctl_resource_cmp0, CLK_SRC_GROUP_AHB, 0), - clock_cmp1 = MAKE_CLOCK_NAME(sysctl_resource_cmp1, CLK_SRC_GROUP_AHB, 0), - clock_cmp2 = MAKE_CLOCK_NAME(sysctl_resource_cmp2, CLK_SRC_GROUP_AHB, 0), - clock_cmp3 = MAKE_CLOCK_NAME(sysctl_resource_cmp3, CLK_SRC_GROUP_AHB, 0), - clock_ptpc = MAKE_CLOCK_NAME(sysctl_resource_ptpc, CLK_SRC_GROUP_AHB, 0), - clock_mot0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_AHB, 0), - clock_qei0 = MAKE_CLOCK_NAME(sysctl_resource_qei0, CLK_SRC_GROUP_AHB, 0), - clock_qei1 = MAKE_CLOCK_NAME(sysctl_resource_qei1, CLK_SRC_GROUP_AHB, 0), - clock_qei2 = MAKE_CLOCK_NAME(sysctl_resource_qei2, CLK_SRC_GROUP_AHB, 0), - clock_qei3 = MAKE_CLOCK_NAME(sysctl_resource_qei3, CLK_SRC_GROUP_AHB, 0), - clock_qeo0 = MAKE_CLOCK_NAME(sysctl_resource_qeo0, CLK_SRC_GROUP_AHB, 0), - clock_qeo1 = MAKE_CLOCK_NAME(sysctl_resource_qeo1, CLK_SRC_GROUP_AHB, 0), - clock_qeo2 = MAKE_CLOCK_NAME(sysctl_resource_qeo2, CLK_SRC_GROUP_AHB, 0), - clock_qeo3 = MAKE_CLOCK_NAME(sysctl_resource_qeo3, CLK_SRC_GROUP_AHB, 0), - clock_pwm0 = MAKE_CLOCK_NAME(sysctl_resource_pwm0, CLK_SRC_GROUP_AHB, 0), - clock_pwm1 = MAKE_CLOCK_NAME(sysctl_resource_pwm1, CLK_SRC_GROUP_AHB, 0), - clock_pwm2 = MAKE_CLOCK_NAME(sysctl_resource_pwm2, CLK_SRC_GROUP_AHB, 0), - clock_pwm3 = MAKE_CLOCK_NAME(sysctl_resource_pwm3, CLK_SRC_GROUP_AHB, 0), - clock_rdc0 = MAKE_CLOCK_NAME(sysctl_resource_rdc0, CLK_SRC_GROUP_AHB, 0), - clock_rdc1 = MAKE_CLOCK_NAME(sysctl_resource_rdc1, CLK_SRC_GROUP_AHB, 0), - clock_sdm0 = MAKE_CLOCK_NAME(sysctl_resource_sdm0, CLK_SRC_GROUP_AHB, 0), - clock_sdm1 = MAKE_CLOCK_NAME(sysctl_resource_sdm1, CLK_SRC_GROUP_AHB, 0), - clock_plb0 = MAKE_CLOCK_NAME(sysctl_resource_plb0, CLK_SRC_GROUP_AHB, 0), - clock_sei0 = MAKE_CLOCK_NAME(sysctl_resource_sei0, CLK_SRC_GROUP_AHB, 0), - clock_mtg0 = MAKE_CLOCK_NAME(sysctl_resource_mtg0, CLK_SRC_GROUP_AHB, 0), - clock_mtg1 = MAKE_CLOCK_NAME(sysctl_resource_mtg1, CLK_SRC_GROUP_AHB, 0), - clock_vsc0 = MAKE_CLOCK_NAME(sysctl_resource_vsc0, CLK_SRC_GROUP_AHB, 0), - clock_vsc1 = MAKE_CLOCK_NAME(sysctl_resource_vsc1, CLK_SRC_GROUP_AHB, 0), - clock_clc0 = MAKE_CLOCK_NAME(sysctl_resource_clc0, CLK_SRC_GROUP_AHB, 0), - clock_clc1 = MAKE_CLOCK_NAME(sysctl_resource_clc1, CLK_SRC_GROUP_AHB, 0), - clock_emds = MAKE_CLOCK_NAME(sysctl_resource_emds, CLK_SRC_GROUP_AHB, 0), - - clock_watchdog0 = MAKE_CLOCK_NAME(sysctl_resource_wdg0, CLK_SRC_GROUP_EWDG, 0), - clock_watchdog1 = MAKE_CLOCK_NAME(sysctl_resource_wdg1, CLK_SRC_GROUP_EWDG, 1), - clock_watchdog2 = MAKE_CLOCK_NAME(sysctl_resource_wdg2, CLK_SRC_GROUP_EWDG, 2), - clock_watchdog3 = MAKE_CLOCK_NAME(sysctl_resource_wdg3, CLK_SRC_GROUP_EWDG, 3), - - clock_rng = MAKE_CLOCK_NAME(sysctl_resource_rng0, CLK_SRC_GROUP_AXIS, 0), - clock_sdp = MAKE_CLOCK_NAME(sysctl_resource_sdp0, CLK_SRC_GROUP_AXIS, 1), - clock_pka = MAKE_CLOCK_NAME(sysctl_resource_pka0, CLK_SRC_GROUP_AXIS, 2), - clock_kman = MAKE_CLOCK_NAME(sysctl_resource_kman, CLK_SRC_GROUP_AXIS, 3), - clock_xdma = MAKE_CLOCK_NAME(sysctl_resource_xdma, CLK_SRC_GROUP_AXIS, 4), - clock_ffa0 = MAKE_CLOCK_NAME(sysctl_resource_ffa0, CLK_SRC_GROUP_AXIS, 5), - clock_rom0 = MAKE_CLOCK_NAME(sysctl_resource_rom0, CLK_SRC_GROUP_AXIS, 6), - - clock_ram0 = MAKE_CLOCK_NAME(sysctl_resource_ram0, CLK_SRC_GROUP_AXIF, 0), - clock_ram1 = MAKE_CLOCK_NAME(sysctl_resource_ram1, CLK_SRC_GROUP_AXIF, 1), - - clock_usb0 = MAKE_CLOCK_NAME(sysctl_resource_usb0, CLK_SRC_GROUP_AXIC, 0), - - clock_esc0 = MAKE_CLOCK_NAME(sysctl_resource_esc0, CLK_SRC_GROUP_AXIN, 0), - - clock_lmm0 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU0, 0), - clock_lmm1 = MAKE_CLOCK_NAME(sysctl_resource_lmm0, CLK_SRC_GROUP_CPU1, 0), - - clock_puart = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 0), - clock_ptmr = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PMIC, 1), - - clock_pwdg = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_PEWDG, 0), - - /* For ADC, there are 2-stage clock source and divider configurations */ - clock_ana0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana0), - clock_ana1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana1), - clock_ana2 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana2), - clock_ana3 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_ana3), - clock_adc0 = MAKE_CLOCK_NAME(sysctl_resource_adc0, CLK_SRC_GROUP_ADC, 0), - clock_adc1 = MAKE_CLOCK_NAME(sysctl_resource_adc1, CLK_SRC_GROUP_ADC, 1), - clock_adc2 = MAKE_CLOCK_NAME(sysctl_resource_adc2, CLK_SRC_GROUP_ADC, 2), - clock_adc3 = MAKE_CLOCK_NAME(sysctl_resource_adc3, CLK_SRC_GROUP_ADC, 3), - - /* For I2S, there are 2-stage clock source and divider configurations */ - clock_aud0 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud0), - clock_aud1 = MAKE_CLOCK_NAME(RESOURCE_INVALID, CLK_SRC_GROUP_COMMON, clock_node_aud1), - clock_i2s0 = MAKE_CLOCK_NAME(sysctl_resource_i2s0, CLK_SRC_GROUP_I2S, 0), - clock_i2s1 = MAKE_CLOCK_NAME(sysctl_resource_i2s1, CLK_SRC_GROUP_I2S, 1), - clock_pdm = MAKE_CLOCK_NAME(sysctl_resource_i2spdm0, CLK_SRC_GROUP_I2S, 0), - clock_dao = MAKE_CLOCK_NAME(sysctl_resource_i2sdao, CLK_SRC_GROUP_I2S, 1), - - /* Clock sources */ - clk_osc0clk0 = MAKE_CLOCK_NAME(sysctl_resource_xtal, CLK_SRC_GROUP_SRC, 0), - clk_pll0clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll0, CLK_SRC_GROUP_SRC, 1), - clk_pll0clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll0, CLK_SRC_GROUP_SRC, 2), - clk_pll1clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll1, CLK_SRC_GROUP_SRC, 3), - clk_pll1clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll1, CLK_SRC_GROUP_SRC, 4), - clk_pll1clk2 = MAKE_CLOCK_NAME(sysctl_resource_clk2_pll1, CLK_SRC_GROUP_SRC, 5), - clk_pll2clk0 = MAKE_CLOCK_NAME(sysctl_resource_clk0_pll2, CLK_SRC_GROUP_SRC, 6), - clk_pll2clk1 = MAKE_CLOCK_NAME(sysctl_resource_clk1_pll2, CLK_SRC_GROUP_SRC, 7), -} clock_name_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Get specified IP frequency - * @param[in] clock_name IP clock name - * - * @return IP clock frequency in Hz - */ -uint32_t clock_get_frequency(clock_name_t clock_name); - - -/** - * @brief Get Clock frequency for selected clock source - * @param [in] source clock source - * @return clock frequency for selected clock source - */ -uint32_t get_frequency_for_source(clock_source_t source); - -/** - * @brief Get the IP clock source - * Note: This API return the direct clock source - * @param [in] clock_name clock name - * @return IP clock source - */ -clk_src_t clock_get_source(clock_name_t clock_name); - -/** - * @brief Set ADC clock source - * @param[in] clock_name ADC clock name - * @param[in] src ADC clock source - * - * @return #status_success Setting ADC clock source is successful - * #status_clk_invalid Invalid ADC clock - * #status_clk_src_invalid Invalid ADC clock source - */ -hpm_stat_t clock_set_adc_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set DAC clock source - * @param[in] clock_name DAC clock name - * @param[in] src DAC clock source - * - * @return #status_success Setting DAC clock source is successful - * #status_clk_invalid Invalid DAC clock - * #status_clk_src_invalid Invalid DAC clock source - */ -hpm_stat_t clock_set_dac_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set I2S clock source - * @param[in] clock_name I2S clock name - * @param[in] src I2S clock source - * - * @return #status_success Setting I2S clock source is successful - * #status_clk_invalid Invalid I2S clock - * #status_clk_src_invalid Invalid I2S clock source - */ -hpm_stat_t clock_set_i2s_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the WDG clock source - * @param [in] clock_name WDG clock name - * @param [in] src WDG clock source - * - * @retval status_success Setting WDG clock source is successful - * @retval status_invalid_argument Invalid WDG or invalid clock source - */ -hpm_stat_t clock_set_wdg_source(clock_name_t clock_name, clk_src_t src); - -/** - * @brief Set the IP clock source and divider - * @param[in] clock_name clock name - * @param[in] src clock source - * @param[in] div clock divider, valid range (1 - 256) - * - * @return #status_success Setting Clock source and divider is successful. - * #status_clk_src_invalid clock source is invalid. - * #status_clk_fixed clock source and divider is a fixed value - * #status_clk_shared_ahb Clock is shared with the AHB clock - * #status_clk_shared_axi0 Clock is shared with the AXI0 clock - * #status_clk_shared_axi1 CLock is shared with the AXI1 clock - * #status_clk_shared_axi2 Clock is shared with the AXI2 clock - * #status_clk_shared_cpu0 Clock is shared with the CPU0 clock - * #status_clk_shared_cpu1 Clock is shared with the CPU1 clock - */ -hpm_stat_t clock_set_source_divider(clock_name_t clock_name, clk_src_t src, uint32_t div); - -/** - * @brief Enable IP clock - * @param[in] clock_name IP clock name - */ -void clock_enable(clock_name_t clock_name); - -/** - * @brief Disable IP clock - * @param[in] clock_name IP clock name - */ -void clock_disable(clock_name_t clock_name); - -/** - * @brief Add IP to specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_add_to_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Remove IP from specified group - * @param[in] clock_name IP clock name - * @param[in] group resource group index, valid value: 0/1/2/3 - */ -void clock_remove_from_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Check IP in specified group - * @param[in] clock_name IP clock name - * @return true if in group, false if not in group - */ -bool clock_check_in_group(clock_name_t clock_name, uint32_t group); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_connect_group_to_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Disconnect the clock group from specified CPU - * @param[in] group clock group index, value value is 0/1/2/3 - * @param[in] cpu CPU index, valid value is 0/1 - */ -void clock_disconnect_group_from_cpu(uint32_t group, uint32_t cpu); - -/** - * @brief Delay specified microseconds - * - * @param [in] us expected delay interval in microseconds - */ -void clock_cpu_delay_us(uint32_t us); - -/** - * @brief Delay specified milliseconds - * - * @param [in] ms expected delay interval in milliseconds - */ -void clock_cpu_delay_ms(uint32_t ms); - -/** - * @brief Update the Core clock frequency - */ -void clock_update_core_clock(void); - -/** - * @brief HPM Core clock variable - */ -extern uint32_t hpm_core_clock; - -#ifdef __cplusplus -} -#endif - -#endif /* HPM_CLOCK_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_csr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_csr_regs.h deleted file mode 100644 index 5f43b12bd1a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_csr_regs.h +++ /dev/null @@ -1,6512 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CSR_H -#define HPM_CSR_H - -/* STANDARD CRS address definition */ -#define CSR_USTATUS (0x0) -#define CSR_UIE (0x4) -#define CSR_UTVEC (0x5) -#define CSR_USCRATCH (0x40) -#define CSR_UEPC (0x41) -#define CSR_UCAUSE (0x42) -#define CSR_UTVAL (0x43) -#define CSR_UIP (0x44) -#define CSR_SSTATUS (0x100) -#define CSR_SEDELEG (0x102) -#define CSR_SIDELEG (0x103) -#define CSR_SIE (0x104) -#define CSR_STVEC (0x105) -#define CSR_SSCRATCH (0x140) -#define CSR_SEPC (0x141) -#define CSR_SCAUSE (0x142) -#define CSR_STVAL (0x143) -#define CSR_SIP (0x144) -#define CSR_SATP (0x180) -#define CSR_MSTATUS (0x300) -#define CSR_MISA (0x301) -#define CSR_MEDELEG (0x302) -#define CSR_MIDELEG (0x303) -#define CSR_MIE (0x304) -#define CSR_MTVEC (0x305) -#define CSR_MCOUNTEREN (0x306) -#define CSR_MHPMEVENT3 (0x323) -#define CSR_MHPMEVENT4 (0x324) -#define CSR_MHPMEVENT5 (0x325) -#define CSR_MHPMEVENT6 (0x326) -#define CSR_MSCRATCH (0x340) -#define CSR_MEPC (0x341) -#define CSR_MCAUSE (0x342) -#define CSR_MTVAL (0x343) -#define CSR_MIP (0x344) -#define CSR_PMPCFG0 (0x3A0) -#define CSR_PMPCFG1 (0x3A1) -#define CSR_PMPCFG2 (0x3A2) -#define CSR_PMPCFG3 (0x3A3) -#define CSR_PMPADDR0 (0x3B0) -#define CSR_PMPADDR1 (0x3B1) -#define CSR_PMPADDR2 (0x3B2) -#define CSR_PMPADDR3 (0x3B3) -#define CSR_PMPADDR4 (0x3B4) -#define CSR_PMPADDR5 (0x3B5) -#define CSR_PMPADDR6 (0x3B6) -#define CSR_PMPADDR7 (0x3B7) -#define CSR_PMPADDR8 (0x3B8) -#define CSR_PMPADDR9 (0x3B9) -#define CSR_PMPADDR10 (0x3BA) -#define CSR_PMPADDR11 (0x3BB) -#define CSR_PMPADDR12 (0x3BC) -#define CSR_PMPADDR13 (0x3BD) -#define CSR_PMPADDR14 (0x3BE) -#define CSR_PMPADDR15 (0x3BF) -#define CSR_TSELECT (0x7A0) -#define CSR_TDATA1 (0x7A1) -#define CSR_MCONTROL (0x7A1) -#define CSR_ICOUNT (0x7A1) -#define CSR_ITRIGGER (0x7A1) -#define CSR_ETRIGGER (0x7A1) -#define CSR_TDATA2 (0x7A2) -#define CSR_TDATA3 (0x7A3) -#define CSR_TEXTRA (0x7A3) -#define CSR_TINFO (0x7A4) -#define CSR_TCONTROL (0x7A5) -#define CSR_MCONTEXT (0x7A8) -#define CSR_SCONTEXT (0x7AA) -#define CSR_DCSR (0x7B0) -#define CSR_DPC (0x7B1) -#define CSR_DSCRATCH0 (0x7B2) -#define CSR_DSCRATCH1 (0x7B3) -#define CSR_MCYCLE (0xB00) -#define CSR_MINSTRET (0xB02) -#define CSR_MHPMCOUNTER3 (0xB03) -#define CSR_MHPMCOUNTER4 (0xB04) -#define CSR_MHPMCOUNTER5 (0xB05) -#define CSR_MHPMCOUNTER6 (0xB06) -#define CSR_MCYCLEH (0xB80) -#define CSR_MINSTRETH (0xB82) -#define CSR_MHPMCOUNTER3H (0xB83) -#define CSR_MHPMCOUNTER4H (0xB84) -#define CSR_MHPMCOUNTER5H (0xB85) -#define CSR_MHPMCOUNTER6H (0xB86) -#define CSR_PMACFG0 (0xBC0) -#define CSR_PMACFG1 (0xBC1) -#define CSR_PMACFG2 (0xBC2) -#define CSR_PMACFG3 (0xBC3) -#define CSR_PMAADDR0 (0xBD0) -#define CSR_PMAADDR1 (0xBD1) -#define CSR_PMAADDR2 (0xBD2) -#define CSR_PMAADDR3 (0xBD3) -#define CSR_PMAADDR4 (0xBD4) -#define CSR_PMAADDR5 (0xBD5) -#define CSR_PMAADDR6 (0xBD6) -#define CSR_PMAADDR7 (0xBD7) -#define CSR_PMAADDR8 (0xBD8) -#define CSR_PMAADDR9 (0xBD9) -#define CSR_PMAADDR10 (0xBDA) -#define CSR_PMAADDR11 (0xBDB) -#define CSR_PMAADDR12 (0xBDC) -#define CSR_PMAADDR13 (0xBDD) -#define CSR_PMAADDR14 (0xBDE) -#define CSR_PMAADDR15 (0xBDF) -#define CSR_CYCLE (0xC00) -#define CSR_CYCLEH (0xC80) -#define CSR_MVENDORID (0xF11) -#define CSR_MARCHID (0xF12) -#define CSR_MIMPID (0xF13) -#define CSR_MHARTID (0xF14) - -/* NON-STANDARD CRS address definition */ -#define CSR_SCOUNTEREN (0x106) -#define CSR_MCOUNTINHIBIT (0x320) -#define CSR_MILMB (0x7C0) -#define CSR_MDLMB (0x7C1) -#define CSR_MECC_CODE (0x7C2) -#define CSR_MNVEC (0x7C3) -#define CSR_MXSTATUS (0x7C4) -#define CSR_MPFT_CTL (0x7C5) -#define CSR_MHSP_CTL (0x7C6) -#define CSR_MSP_BOUND (0x7C7) -#define CSR_MSP_BASE (0x7C8) -#define CSR_MDCAUSE (0x7C9) -#define CSR_MCACHE_CTL (0x7CA) -#define CSR_MCCTLBEGINADDR (0x7CB) -#define CSR_MCCTLCOMMAND (0x7CC) -#define CSR_MCCTLDATA (0x7CD) -#define CSR_MCOUNTERWEN (0x7CE) -#define CSR_MCOUNTERINTEN (0x7CF) -#define CSR_MMISC_CTL (0x7D0) -#define CSR_MCOUNTERMASK_M (0x7D1) -#define CSR_MCOUNTERMASK_S (0x7D2) -#define CSR_MCOUNTERMASK_U (0x7D3) -#define CSR_MCOUNTEROVF (0x7D4) -#define CSR_MSLIDELEG (0x7D5) -#define CSR_MCLK_CTL (0x7DF) -#define CSR_DEXC2DBG (0x7E0) -#define CSR_DDCAUSE (0x7E1) -#define CSR_UITB (0x800) -#define CSR_UCODE (0x801) -#define CSR_UDCAUSE (0x809) -#define CSR_UCCTLBEGINADDR (0x80B) -#define CSR_UCCTLCOMMAND (0x80C) -#define CSR_SLIE (0x9C4) -#define CSR_SLIP (0x9C5) -#define CSR_SDCAUSE (0x9C9) -#define CSR_SCCTLDATA (0x9CD) -#define CSR_SCOUNTERINTEN (0x9CF) -#define CSR_SCOUNTERMASK_M (0x9D1) -#define CSR_SCOUNTERMASK_S (0x9D2) -#define CSR_SCOUNTERMASK_U (0x9D3) -#define CSR_SCOUNTEROVF (0x9D4) -#define CSR_SCOUNTINHIBIT (0x9E0) -#define CSR_SHPMEVENT3 (0x9E3) -#define CSR_SHPMEVENT4 (0x9E4) -#define CSR_SHPMEVENT5 (0x9E5) -#define CSR_SHPMEVENT6 (0x9E6) -#define CSR_MICM_CFG (0xFC0) -#define CSR_MDCM_CFG (0xFC1) -#define CSR_MMSC_CFG (0xFC2) -#define CSR_MMSC_CFG2 (0xFC3) - -/* STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: USTATUS */ -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_USTATUS_UPIE_MASK (0x10U) -#define CSR_USTATUS_UPIE_SHIFT (4U) -#define CSR_USTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UPIE_SHIFT) & CSR_USTATUS_UPIE_MASK) -#define CSR_USTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UPIE_MASK) >> CSR_USTATUS_UPIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_USTATUS_UIE_MASK (0x1U) -#define CSR_USTATUS_UIE_SHIFT (0U) -#define CSR_USTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_USTATUS_UIE_SHIFT) & CSR_USTATUS_UIE_MASK) -#define CSR_USTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_USTATUS_UIE_MASK) >> CSR_USTATUS_UIE_SHIFT) - -/* Bitfield definition for register: UIE */ -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UEIE_MASK (0x100U) -#define CSR_UIE_UEIE_SHIFT (8U) -#define CSR_UIE_UEIE_SET(x) (((uint32_t)(x) << CSR_UIE_UEIE_SHIFT) & CSR_UIE_UEIE_MASK) -#define CSR_UIE_UEIE_GET(x) (((uint32_t)(x) & CSR_UIE_UEIE_MASK) >> CSR_UIE_UEIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_UTIE_MASK (0x10U) -#define CSR_UIE_UTIE_SHIFT (4U) -#define CSR_UIE_UTIE_SET(x) (((uint32_t)(x) << CSR_UIE_UTIE_SHIFT) & CSR_UIE_UTIE_MASK) -#define CSR_UIE_UTIE_GET(x) (((uint32_t)(x) & CSR_UIE_UTIE_MASK) >> CSR_UIE_UTIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_UIE_USIE_MASK (0x1U) -#define CSR_UIE_USIE_SHIFT (0U) -#define CSR_UIE_USIE_SET(x) (((uint32_t)(x) << CSR_UIE_USIE_SHIFT) & CSR_UIE_USIE_MASK) -#define CSR_UIE_USIE_GET(x) (((uint32_t)(x) & CSR_UIE_USIE_MASK) >> CSR_UIE_USIE_SHIFT) - -/* Bitfield definition for register: UTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_UTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_UTVEC_BASE_31_2_SHIFT (2U) -#define CSR_UTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_UTVEC_BASE_31_2_SHIFT) & CSR_UTVEC_BASE_31_2_MASK) -#define CSR_UTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_UTVEC_BASE_31_2_MASK) >> CSR_UTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: USCRATCH */ -/* - * USCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_USCRATCH_USCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_USCRATCH_USCRATCH_SHIFT (0U) -#define CSR_USCRATCH_USCRATCH_SET(x) (((uint32_t)(x) << CSR_USCRATCH_USCRATCH_SHIFT) & CSR_USCRATCH_USCRATCH_MASK) -#define CSR_USCRATCH_USCRATCH_GET(x) (((uint32_t)(x) & CSR_USCRATCH_USCRATCH_MASK) >> CSR_USCRATCH_USCRATCH_SHIFT) - -/* Bitfield definition for register: UEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_UEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_UEPC_EPC_SHIFT (1U) -#define CSR_UEPC_EPC_SET(x) (((uint32_t)(x) << CSR_UEPC_EPC_SHIFT) & CSR_UEPC_EPC_MASK) -#define CSR_UEPC_EPC_GET(x) (((uint32_t)(x) & CSR_UEPC_EPC_MASK) >> CSR_UEPC_EPC_SHIFT) - -/* Bitfield definition for register: UCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_UCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_UCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_UCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_UCAUSE_INTERRUPT_SHIFT) & CSR_UCAUSE_INTERRUPT_MASK) -#define CSR_UCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_UCAUSE_INTERRUPT_MASK) >> CSR_UCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 4:User timer interrupt - * 8:User external interrupt - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9-11:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32：Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_UCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_UCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_UCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_UCAUSE_EXCEPTION_CODE_SHIFT) & CSR_UCAUSE_EXCEPTION_CODE_MASK) -#define CSR_UCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_UCAUSE_EXCEPTION_CODE_MASK) >> CSR_UCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: UTVAL */ -/* - * UTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_UTVAL_UTVAL_MASK (0xFFFFFFFFUL) -#define CSR_UTVAL_UTVAL_SHIFT (0U) -#define CSR_UTVAL_UTVAL_SET(x) (((uint32_t)(x) << CSR_UTVAL_UTVAL_SHIFT) & CSR_UTVAL_UTVAL_MASK) -#define CSR_UTVAL_UTVAL_GET(x) (((uint32_t)(x) & CSR_UTVAL_UTVAL_MASK) >> CSR_UTVAL_UTVAL_SHIFT) - -/* Bitfield definition for register: UIP */ -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UEIP_MASK (0x100U) -#define CSR_UIP_UEIP_SHIFT (8U) -#define CSR_UIP_UEIP_SET(x) (((uint32_t)(x) << CSR_UIP_UEIP_SHIFT) & CSR_UIP_UEIP_MASK) -#define CSR_UIP_UEIP_GET(x) (((uint32_t)(x) & CSR_UIP_UEIP_MASK) >> CSR_UIP_UEIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_UTIP_MASK (0x10U) -#define CSR_UIP_UTIP_SHIFT (4U) -#define CSR_UIP_UTIP_SET(x) (((uint32_t)(x) << CSR_UIP_UTIP_SHIFT) & CSR_UIP_UTIP_MASK) -#define CSR_UIP_UTIP_GET(x) (((uint32_t)(x) & CSR_UIP_UTIP_MASK) >> CSR_UIP_UTIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_UIP_USIP_MASK (0x1U) -#define CSR_UIP_USIP_SHIFT (0U) -#define CSR_UIP_USIP_SET(x) (((uint32_t)(x) << CSR_UIP_USIP_SHIFT) & CSR_UIP_USIP_MASK) -#define CSR_UIP_USIP_GET(x) (((uint32_t)(x) & CSR_UIP_USIP_MASK) >> CSR_UIP_USIP_SHIFT) - -/* Bitfield definition for register: SSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_SSTATUS_SD_MASK (0x80000000UL) -#define CSR_SSTATUS_SD_SHIFT (31U) -#define CSR_SSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SD_MASK) >> CSR_SSTATUS_SD_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect. - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_SSTATUS_MXR_MASK (0x80000UL) -#define CSR_SSTATUS_MXR_SHIFT (19U) -#define CSR_SSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_SSTATUS_MXR_SHIFT) & CSR_SSTATUS_MXR_MASK) -#define CSR_SSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_SSTATUS_MXR_MASK) >> CSR_SSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_SSTATUS_SUM_MASK (0x40000UL) -#define CSR_SSTATUS_SUM_SHIFT (18U) -#define CSR_SSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SUM_SHIFT) & CSR_SSTATUS_SUM_MASK) -#define CSR_SSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SUM_MASK) >> CSR_SSTATUS_SUM_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggeredwhen XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. - * Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * The same copy of XS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the XS bits to manage deferred context switches of ACE states. Machine mode software should be more conservative in managing context switches using XS bits - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_XS_MASK (0x18000UL) -#define CSR_SSTATUS_XS_SHIFT (15U) -#define CSR_SSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_XS_MASK) >> CSR_SSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. - * This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * Otherwise, FS is updated to the Dirty state by any instruction that updates fcsr or any f register. - * Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * The same copy of FS bits are shared by both mstatus and sstatus. Normally the supervisor mode privileged software would use the FS bits to manage deferred context switches of FPU states. Machine mode software should be more conservative in managing context switches using FS bits. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_SSTATUS_FS_MASK (0x6000U) -#define CSR_SSTATUS_FS_SHIFT (13U) -#define CSR_SSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_SSTATUS_FS_SHIFT) & CSR_SSTATUS_FS_MASK) -#define CSR_SSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_SSTATUS_FS_MASK) >> CSR_SSTATUS_FS_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_SSTATUS_SPP_MASK (0x100U) -#define CSR_SSTATUS_SPP_SHIFT (8U) -#define CSR_SSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPP_SHIFT) & CSR_SSTATUS_SPP_MASK) -#define CSR_SSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPP_MASK) >> CSR_SSTATUS_SPP_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_SSTATUS_SPIE_MASK (0x20U) -#define CSR_SSTATUS_SPIE_SHIFT (5U) -#define CSR_SSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SPIE_SHIFT) & CSR_SSTATUS_SPIE_MASK) -#define CSR_SSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SPIE_MASK) >> CSR_SSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_SSTATUS_UPIE_MASK (0x10U) -#define CSR_SSTATUS_UPIE_SHIFT (4U) -#define CSR_SSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UPIE_SHIFT) & CSR_SSTATUS_UPIE_MASK) -#define CSR_SSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UPIE_MASK) >> CSR_SSTATUS_UPIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_SIE_MASK (0x2U) -#define CSR_SSTATUS_SIE_SHIFT (1U) -#define CSR_SSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_SIE_SHIFT) & CSR_SSTATUS_SIE_MASK) -#define CSR_SSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_SIE_MASK) >> CSR_SSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0 Disabled - * 1 Enabled - */ -#define CSR_SSTATUS_UIE_MASK (0x1U) -#define CSR_SSTATUS_UIE_SHIFT (0U) -#define CSR_SSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_SSTATUS_UIE_SHIFT) & CSR_SSTATUS_UIE_MASK) -#define CSR_SSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_SSTATUS_UIE_MASK) >> CSR_SSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: SEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SPF_MASK (0x8000U) -#define CSR_SEDELEG_SPF_SHIFT (15U) -#define CSR_SEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SPF_SHIFT) & CSR_SEDELEG_SPF_MASK) -#define CSR_SEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SPF_MASK) >> CSR_SEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LPF_MASK (0x2000U) -#define CSR_SEDELEG_LPF_SHIFT (13U) -#define CSR_SEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LPF_SHIFT) & CSR_SEDELEG_LPF_MASK) -#define CSR_SEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LPF_MASK) >> CSR_SEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IPF_MASK (0x1000U) -#define CSR_SEDELEG_IPF_SHIFT (12U) -#define CSR_SEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IPF_SHIFT) & CSR_SEDELEG_IPF_MASK) -#define CSR_SEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IPF_MASK) >> CSR_SEDELEG_IPF_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_UEC_MASK (0x100U) -#define CSR_SEDELEG_UEC_SHIFT (8U) -#define CSR_SEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_SEDELEG_UEC_SHIFT) & CSR_SEDELEG_UEC_MASK) -#define CSR_SEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_SEDELEG_UEC_MASK) >> CSR_SEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAF_MASK (0x80U) -#define CSR_SEDELEG_SAF_SHIFT (7U) -#define CSR_SEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAF_SHIFT) & CSR_SEDELEG_SAF_MASK) -#define CSR_SEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAF_MASK) >> CSR_SEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_SAM_MASK (0x40U) -#define CSR_SEDELEG_SAM_SHIFT (6U) -#define CSR_SEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_SAM_SHIFT) & CSR_SEDELEG_SAM_MASK) -#define CSR_SEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_SAM_MASK) >> CSR_SEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAF_MASK (0x20U) -#define CSR_SEDELEG_LAF_SHIFT (5U) -#define CSR_SEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAF_SHIFT) & CSR_SEDELEG_LAF_MASK) -#define CSR_SEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAF_MASK) >> CSR_SEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_LAM_MASK (0x10U) -#define CSR_SEDELEG_LAM_SHIFT (4U) -#define CSR_SEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_LAM_SHIFT) & CSR_SEDELEG_LAM_MASK) -#define CSR_SEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_LAM_MASK) >> CSR_SEDELEG_LAM_SHIFT) - -/* - * B (RW) - * - * B indicates whether an exception triggered by breakpoint will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_B_MASK (0x8U) -#define CSR_SEDELEG_B_SHIFT (3U) -#define CSR_SEDELEG_B_SET(x) (((uint32_t)(x) << CSR_SEDELEG_B_SHIFT) & CSR_SEDELEG_B_MASK) -#define CSR_SEDELEG_B_GET(x) (((uint32_t)(x) & CSR_SEDELEG_B_MASK) >> CSR_SEDELEG_B_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_II_MASK (0x4U) -#define CSR_SEDELEG_II_SHIFT (2U) -#define CSR_SEDELEG_II_SET(x) (((uint32_t)(x) << CSR_SEDELEG_II_SHIFT) & CSR_SEDELEG_II_MASK) -#define CSR_SEDELEG_II_GET(x) (((uint32_t)(x) & CSR_SEDELEG_II_MASK) >> CSR_SEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to U-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAF_MASK (0x2U) -#define CSR_SEDELEG_IAF_SHIFT (1U) -#define CSR_SEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAF_SHIFT) & CSR_SEDELEG_IAF_MASK) -#define CSR_SEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAF_MASK) >> CSR_SEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to U-mode.. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SEDELEG_IAM_MASK (0x1U) -#define CSR_SEDELEG_IAM_SHIFT (0U) -#define CSR_SEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_SEDELEG_IAM_SHIFT) & CSR_SEDELEG_IAM_MASK) -#define CSR_SEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_SEDELEG_IAM_MASK) >> CSR_SEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: SIDELEG */ -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UEI_MASK (0x100U) -#define CSR_SIDELEG_UEI_SHIFT (8U) -#define CSR_SIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UEI_SHIFT) & CSR_SIDELEG_UEI_MASK) -#define CSR_SIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UEI_MASK) >> CSR_SIDELEG_UEI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_UTI_MASK (0x10U) -#define CSR_SIDELEG_UTI_SHIFT (4U) -#define CSR_SIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_UTI_SHIFT) & CSR_SIDELEG_UTI_MASK) -#define CSR_SIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_UTI_MASK) >> CSR_SIDELEG_UTI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_SIDELEG_USI_MASK (0x1U) -#define CSR_SIDELEG_USI_SHIFT (0U) -#define CSR_SIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_SIDELEG_USI_SHIFT) & CSR_SIDELEG_USI_MASK) -#define CSR_SIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_SIDELEG_USI_MASK) >> CSR_SIDELEG_USI_SHIFT) - -/* Bitfield definition for register: SIE */ -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SEIE_MASK (0x200U) -#define CSR_SIE_SEIE_SHIFT (9U) -#define CSR_SIE_SEIE_SET(x) (((uint32_t)(x) << CSR_SIE_SEIE_SHIFT) & CSR_SIE_SEIE_MASK) -#define CSR_SIE_SEIE_GET(x) (((uint32_t)(x) & CSR_SIE_SEIE_MASK) >> CSR_SIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UEIE_MASK (0x100U) -#define CSR_SIE_UEIE_SHIFT (8U) -#define CSR_SIE_UEIE_SET(x) (((uint32_t)(x) << CSR_SIE_UEIE_SHIFT) & CSR_SIE_UEIE_MASK) -#define CSR_SIE_UEIE_GET(x) (((uint32_t)(x) & CSR_SIE_UEIE_MASK) >> CSR_SIE_UEIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_STIE_MASK (0x20U) -#define CSR_SIE_STIE_SHIFT (5U) -#define CSR_SIE_STIE_SET(x) (((uint32_t)(x) << CSR_SIE_STIE_SHIFT) & CSR_SIE_STIE_MASK) -#define CSR_SIE_STIE_GET(x) (((uint32_t)(x) & CSR_SIE_STIE_MASK) >> CSR_SIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_UTIE_MASK (0x10U) -#define CSR_SIE_UTIE_SHIFT (4U) -#define CSR_SIE_UTIE_SET(x) (((uint32_t)(x) << CSR_SIE_UTIE_SHIFT) & CSR_SIE_UTIE_MASK) -#define CSR_SIE_UTIE_GET(x) (((uint32_t)(x) & CSR_SIE_UTIE_MASK) >> CSR_SIE_UTIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_SSIE_MASK (0x2U) -#define CSR_SIE_SSIE_SHIFT (1U) -#define CSR_SIE_SSIE_SET(x) (((uint32_t)(x) << CSR_SIE_SSIE_SHIFT) & CSR_SIE_SSIE_MASK) -#define CSR_SIE_SSIE_GET(x) (((uint32_t)(x) & CSR_SIE_SSIE_MASK) >> CSR_SIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_SIE_USIE_MASK (0x1U) -#define CSR_SIE_USIE_SHIFT (0U) -#define CSR_SIE_USIE_SET(x) (((uint32_t)(x) << CSR_SIE_USIE_SHIFT) & CSR_SIE_USIE_MASK) -#define CSR_SIE_USIE_GET(x) (((uint32_t)(x) & CSR_SIE_USIE_MASK) >> CSR_SIE_USIE_SHIFT) - -/* Bitfield definition for register: STVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode. - */ -#define CSR_STVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_STVEC_BASE_31_2_SHIFT (2U) -#define CSR_STVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_STVEC_BASE_31_2_SHIFT) & CSR_STVEC_BASE_31_2_MASK) -#define CSR_STVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_STVEC_BASE_31_2_MASK) >> CSR_STVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: SSCRATCH */ -/* - * SSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_SSCRATCH_SSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_SSCRATCH_SSCRATCH_SHIFT (0U) -#define CSR_SSCRATCH_SSCRATCH_SET(x) (((uint32_t)(x) << CSR_SSCRATCH_SSCRATCH_SHIFT) & CSR_SSCRATCH_SSCRATCH_MASK) -#define CSR_SSCRATCH_SSCRATCH_GET(x) (((uint32_t)(x) & CSR_SSCRATCH_SSCRATCH_MASK) >> CSR_SSCRATCH_SSCRATCH_SHIFT) - -/* Bitfield definition for register: SEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_SEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_SEPC_EPC_SHIFT (1U) -#define CSR_SEPC_EPC_SET(x) (((uint32_t)(x) << CSR_SEPC_EPC_SHIFT) & CSR_SEPC_EPC_MASK) -#define CSR_SEPC_EPC_GET(x) (((uint32_t)(x) & CSR_SEPC_EPC_MASK) >> CSR_SEPC_EPC_SHIFT) - -/* Bitfield definition for register: SCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt. - */ -#define CSR_SCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_SCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_SCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_SCAUSE_INTERRUPT_SHIFT) & CSR_SCAUSE_INTERRUPT_MASK) -#define CSR_SCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_SCAUSE_INTERRUPT_MASK) >> CSR_SCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception Code. - * When interrupt is 1: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 256+16:Slave port ECC error interrupt (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt(S-mode) - * When interrupt is 0: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:10:Reserved - * 12:Instruction page fault - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_SCAUSE_EXCEPTION_CODE_MASK (0x3FFU) -#define CSR_SCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_SCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_SCAUSE_EXCEPTION_CODE_SHIFT) & CSR_SCAUSE_EXCEPTION_CODE_MASK) -#define CSR_SCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_SCAUSE_EXCEPTION_CODE_MASK) >> CSR_SCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: STVAL */ -/* - * STVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_STVAL_STVAL_MASK (0xFFFFFFFFUL) -#define CSR_STVAL_STVAL_SHIFT (0U) -#define CSR_STVAL_STVAL_SET(x) (((uint32_t)(x) << CSR_STVAL_STVAL_SHIFT) & CSR_STVAL_STVAL_MASK) -#define CSR_STVAL_STVAL_GET(x) (((uint32_t)(x) & CSR_STVAL_STVAL_MASK) >> CSR_STVAL_STVAL_SHIFT) - -/* Bitfield definition for register: SIP */ -/* - * SEIP (RO) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SEIP_MASK (0x200U) -#define CSR_SIP_SEIP_SHIFT (9U) -#define CSR_SIP_SEIP_GET(x) (((uint32_t)(x) & CSR_SIP_SEIP_MASK) >> CSR_SIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UEIP_MASK (0x100U) -#define CSR_SIP_UEIP_SHIFT (8U) -#define CSR_SIP_UEIP_SET(x) (((uint32_t)(x) << CSR_SIP_UEIP_SHIFT) & CSR_SIP_UEIP_MASK) -#define CSR_SIP_UEIP_GET(x) (((uint32_t)(x) & CSR_SIP_UEIP_MASK) >> CSR_SIP_UEIP_SHIFT) - -/* - * STIP (RO) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_STIP_MASK (0x20U) -#define CSR_SIP_STIP_SHIFT (5U) -#define CSR_SIP_STIP_GET(x) (((uint32_t)(x) & CSR_SIP_STIP_MASK) >> CSR_SIP_STIP_SHIFT) - -/* - * UTIP (RO) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_UTIP_MASK (0x10U) -#define CSR_SIP_UTIP_SHIFT (4U) -#define CSR_SIP_UTIP_GET(x) (((uint32_t)(x) & CSR_SIP_UTIP_MASK) >> CSR_SIP_UTIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_SSIP_MASK (0x2U) -#define CSR_SIP_SSIP_SHIFT (1U) -#define CSR_SIP_SSIP_SET(x) (((uint32_t)(x) << CSR_SIP_SSIP_SHIFT) & CSR_SIP_SSIP_MASK) -#define CSR_SIP_SSIP_GET(x) (((uint32_t)(x) & CSR_SIP_SSIP_MASK) >> CSR_SIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_SIP_USIP_MASK (0x1U) -#define CSR_SIP_USIP_SHIFT (0U) -#define CSR_SIP_USIP_SET(x) (((uint32_t)(x) << CSR_SIP_USIP_SHIFT) & CSR_SIP_USIP_MASK) -#define CSR_SIP_USIP_GET(x) (((uint32_t)(x) & CSR_SIP_USIP_MASK) >> CSR_SIP_USIP_SHIFT) - -/* Bitfield definition for register: SATP */ -/* - * MODE (RW) - * - * MODE holds the page translation mode. When MODE is Bare, virtual addresses are equal to physical addresses in S-mode. When MMU is - * not supported in the product, this CSR will be - * hardwired to 0. - * 0:No page translation - * 1:Page-based 32-bit virtual addressing - */ -#define CSR_SATP_MODE_MASK (0x80000000UL) -#define CSR_SATP_MODE_SHIFT (31U) -#define CSR_SATP_MODE_SET(x) (((uint32_t)(x) << CSR_SATP_MODE_SHIFT) & CSR_SATP_MODE_MASK) -#define CSR_SATP_MODE_GET(x) (((uint32_t)(x) & CSR_SATP_MODE_MASK) >> CSR_SATP_MODE_SHIFT) - -/* - * ASID (RW) - * - * ASID holds the address space identifier. - */ -#define CSR_SATP_ASID_MASK (0x7FC00000UL) -#define CSR_SATP_ASID_SHIFT (22U) -#define CSR_SATP_ASID_SET(x) (((uint32_t)(x) << CSR_SATP_ASID_SHIFT) & CSR_SATP_ASID_MASK) -#define CSR_SATP_ASID_GET(x) (((uint32_t)(x) & CSR_SATP_ASID_MASK) >> CSR_SATP_ASID_SHIFT) - -/* - * PPN (RW) - * - * PPN holds the physical page number of the root page table. - */ -#define CSR_SATP_PPN_MASK (0x3FFFFFUL) -#define CSR_SATP_PPN_SHIFT (0U) -#define CSR_SATP_PPN_SET(x) (((uint32_t)(x) << CSR_SATP_PPN_SHIFT) & CSR_SATP_PPN_MASK) -#define CSR_SATP_PPN_GET(x) (((uint32_t)(x) & CSR_SATP_PPN_MASK) >> CSR_SATP_PPN_SHIFT) - -/* Bitfield definition for register: MSTATUS */ -/* - * SD (RO) - * - * SD summarizes whether either the FS field or XS field is dirty. - */ -#define CSR_MSTATUS_SD_MASK (0x80000000UL) -#define CSR_MSTATUS_SD_SHIFT (31U) -#define CSR_MSTATUS_SD_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SD_MASK) >> CSR_MSTATUS_SD_SHIFT) - -/* - * TSR (RW) - * - * TSR controls whether executing SRET instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TSR_MASK (0x400000UL) -#define CSR_MSTATUS_TSR_SHIFT (22U) -#define CSR_MSTATUS_TSR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TSR_SHIFT) & CSR_MSTATUS_TSR_MASK) -#define CSR_MSTATUS_TSR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TSR_MASK) >> CSR_MSTATUS_TSR_SHIFT) - -/* - * TW (RW) - * - * TW controls whether executing WFI instructions in S-mode will raise illegal instruction exceptions. It is hardwired to 0 when S-mode is not supported. - * 0: Normal execution - * 1: Raising exceptions - */ -#define CSR_MSTATUS_TW_MASK (0x200000UL) -#define CSR_MSTATUS_TW_SHIFT (21U) -#define CSR_MSTATUS_TW_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TW_SHIFT) & CSR_MSTATUS_TW_MASK) -#define CSR_MSTATUS_TW_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TW_MASK) >> CSR_MSTATUS_TW_SHIFT) - -/* - * TVM (RW) - * - * TVM controls whether performing certain virtual memory operations in S-mode will raise illegal instruction exceptions. The operations include accessing the satp register and executing the SFENCE.VMA instruction. It is hardwired to 0 when S-mode is not supported. - * 0:Normal execution - * 1:Raising exceptions - */ -#define CSR_MSTATUS_TVM_MASK (0x100000UL) -#define CSR_MSTATUS_TVM_SHIFT (20U) -#define CSR_MSTATUS_TVM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_TVM_SHIFT) & CSR_MSTATUS_TVM_MASK) -#define CSR_MSTATUS_TVM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_TVM_MASK) >> CSR_MSTATUS_TVM_SHIFT) - -/* - * MXR (RW) - * - * MXR controls whether execute-only pages are readable. It has no effect when page-based virtual memory is not in effect - * 0:Execute-only pages are not readable - * 1:Execute-only pages are readable - */ -#define CSR_MSTATUS_MXR_MASK (0x80000UL) -#define CSR_MSTATUS_MXR_SHIFT (19U) -#define CSR_MSTATUS_MXR_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MXR_SHIFT) & CSR_MSTATUS_MXR_MASK) -#define CSR_MSTATUS_MXR_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MXR_MASK) >> CSR_MSTATUS_MXR_SHIFT) - -/* - * SUM (RW) - * - * SUM controls whether a S-mode load/store instruction to a user accessible page is allowed or not when page translation is enabled. It is in effect in two scenarios: (a) M-mode with MPRV=1 and MPP=S, and (b) in S-mode. It has no effect when page-based virtual memory is not in effect. A page is user accessible when the U bit of the corresponding PTE entry is 1. It is hardwired to 0 when S-mode is not supported. - * 0:Not Allowed - * 1:Allowed - */ -#define CSR_MSTATUS_SUM_MASK (0x40000UL) -#define CSR_MSTATUS_SUM_SHIFT (18U) -#define CSR_MSTATUS_SUM_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SUM_SHIFT) & CSR_MSTATUS_SUM_MASK) -#define CSR_MSTATUS_SUM_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SUM_MASK) >> CSR_MSTATUS_SUM_SHIFT) - -/* - * MPRV (RW) - * - * When the MPRV bit is set, the memory access privilege for load and store are specified by the MPP field. When U-mode is not available, this field is hardwired to 0. - */ -#define CSR_MSTATUS_MPRV_MASK (0x20000UL) -#define CSR_MSTATUS_MPRV_SHIFT (17U) -#define CSR_MSTATUS_MPRV_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPRV_SHIFT) & CSR_MSTATUS_MPRV_MASK) -#define CSR_MSTATUS_MPRV_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPRV_MASK) >> CSR_MSTATUS_MPRV_SHIFT) - -/* - * XS (RO) - * - * XS holds the status of the architectural states (ACE registers) of ACE instructions. The value of this field is zero if ACE extension is not configured. This field is primarily managed by software. The processor hardware assists the state managements in two regards: - * Illegal instruction exceptions are triggered when XS is Off. - * XS is updated to the Dirty state with the execution of ACE instructions when XS is not Off. Changing the setting of this field has no effect on the contents of ACE states. In particular, setting XS to Off does not destroy the states, nor does setting XS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_XS_MASK (0x18000UL) -#define CSR_MSTATUS_XS_SHIFT (15U) -#define CSR_MSTATUS_XS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_XS_MASK) >> CSR_MSTATUS_XS_SHIFT) - -/* - * FS (RW) - * - * FS holds the status of the architectural states of the floating-point unit, including the fcsr CSR and f0 – f31 floating-point data registers. The value of this field is zero and read-only if the processor does not have FPU. This field is primarily managed by software. The processor hardware assists the state - * managements in two regards: - * Attempts to access fcsr or any f register raise an illegal-instruction exception when FS is Off. - * FS is updated to the Dirty state with the execution of any instruction that updates fcsr or any f register when FS is Initial or Clean. Changing the setting of this field has no effect on the contents of the floating-point register states. In particular, setting FS to Off does not destroy the states, nor does setting FS to Initial clear the contents. - * 0:Off - * 1:Initial - * 2:Clean - * 3:Dirty - */ -#define CSR_MSTATUS_FS_MASK (0x6000U) -#define CSR_MSTATUS_FS_SHIFT (13U) -#define CSR_MSTATUS_FS_SET(x) (((uint32_t)(x) << CSR_MSTATUS_FS_SHIFT) & CSR_MSTATUS_FS_MASK) -#define CSR_MSTATUS_FS_GET(x) (((uint32_t)(x) & CSR_MSTATUS_FS_MASK) >> CSR_MSTATUS_FS_SHIFT) - -/* - * MPP (RW) - * - * MPP holds the privilege mode prior to a trap. Encoding for privilege mode is described in Table5. When U-mode is not available, this field is hardwired to 3. - */ -#define CSR_MSTATUS_MPP_MASK (0x1800U) -#define CSR_MSTATUS_MPP_SHIFT (11U) -#define CSR_MSTATUS_MPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPP_SHIFT) & CSR_MSTATUS_MPP_MASK) -#define CSR_MSTATUS_MPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPP_MASK) >> CSR_MSTATUS_MPP_SHIFT) - -/* - * SPP (RW) - * - * SPP holds the privilege mode prior to a trap. Encoding is 1 for S-mode and 0 for U-mode. - */ -#define CSR_MSTATUS_SPP_MASK (0x100U) -#define CSR_MSTATUS_SPP_SHIFT (8U) -#define CSR_MSTATUS_SPP_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPP_SHIFT) & CSR_MSTATUS_SPP_MASK) -#define CSR_MSTATUS_SPP_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPP_MASK) >> CSR_MSTATUS_SPP_SHIFT) - -/* - * MPIE (RW) - * - * MPIE holds the value of the MIE bit prior to a trap. - */ -#define CSR_MSTATUS_MPIE_MASK (0x80U) -#define CSR_MSTATUS_MPIE_SHIFT (7U) -#define CSR_MSTATUS_MPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MPIE_SHIFT) & CSR_MSTATUS_MPIE_MASK) -#define CSR_MSTATUS_MPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MPIE_MASK) >> CSR_MSTATUS_MPIE_SHIFT) - -/* - * SPIE (RW) - * - * SPIE holds the value of the SIE bit prior to a trap. - */ -#define CSR_MSTATUS_SPIE_MASK (0x20U) -#define CSR_MSTATUS_SPIE_SHIFT (5U) -#define CSR_MSTATUS_SPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SPIE_SHIFT) & CSR_MSTATUS_SPIE_MASK) -#define CSR_MSTATUS_SPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SPIE_MASK) >> CSR_MSTATUS_SPIE_SHIFT) - -/* - * UPIE (RW) - * - * UPIE holds the value of the UIE bit prior to a trap. - */ -#define CSR_MSTATUS_UPIE_MASK (0x10U) -#define CSR_MSTATUS_UPIE_SHIFT (4U) -#define CSR_MSTATUS_UPIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UPIE_SHIFT) & CSR_MSTATUS_UPIE_MASK) -#define CSR_MSTATUS_UPIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UPIE_MASK) >> CSR_MSTATUS_UPIE_SHIFT) - -/* - * MIE (RW) - * - * M mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_MIE_MASK (0x8U) -#define CSR_MSTATUS_MIE_SHIFT (3U) -#define CSR_MSTATUS_MIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_MIE_SHIFT) & CSR_MSTATUS_MIE_MASK) -#define CSR_MSTATUS_MIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_MIE_MASK) >> CSR_MSTATUS_MIE_SHIFT) - -/* - * SIE (RW) - * - * S mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_SIE_MASK (0x2U) -#define CSR_MSTATUS_SIE_SHIFT (1U) -#define CSR_MSTATUS_SIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_SIE_SHIFT) & CSR_MSTATUS_SIE_MASK) -#define CSR_MSTATUS_SIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_SIE_MASK) >> CSR_MSTATUS_SIE_SHIFT) - -/* - * UIE (RW) - * - * U mode interrupt enable bit. - * 0: Disabled - * 1: Enabled - */ -#define CSR_MSTATUS_UIE_MASK (0x1U) -#define CSR_MSTATUS_UIE_SHIFT (0U) -#define CSR_MSTATUS_UIE_SET(x) (((uint32_t)(x) << CSR_MSTATUS_UIE_SHIFT) & CSR_MSTATUS_UIE_MASK) -#define CSR_MSTATUS_UIE_GET(x) (((uint32_t)(x) & CSR_MSTATUS_UIE_MASK) >> CSR_MSTATUS_UIE_SHIFT) - -/* Bitfield definition for register: MISA */ -/* - * BASE (RO) - * - * The general-purpose register width of the native base integer ISA. - * 0:Reserved - * 1:32 - * 2:64 - * 3:128 - */ -#define CSR_MISA_BASE_MASK (0xC0000000UL) -#define CSR_MISA_BASE_SHIFT (30U) -#define CSR_MISA_BASE_GET(x) (((uint32_t)(x) & CSR_MISA_BASE_MASK) >> CSR_MISA_BASE_SHIFT) - -/* - * Z (RO) - * - * Reserved - */ -#define CSR_MISA_Z_MASK (0x2000000UL) -#define CSR_MISA_Z_SHIFT (25U) -#define CSR_MISA_Z_GET(x) (((uint32_t)(x) & CSR_MISA_Z_MASK) >> CSR_MISA_Z_SHIFT) - -/* - * Y (RO) - * - * Reserved - */ -#define CSR_MISA_Y_MASK (0x1000000UL) -#define CSR_MISA_Y_SHIFT (24U) -#define CSR_MISA_Y_GET(x) (((uint32_t)(x) & CSR_MISA_Y_MASK) >> CSR_MISA_Y_SHIFT) - -/* - * X (RO) - * - * Non-standard extensions present - */ -#define CSR_MISA_X_MASK (0x800000UL) -#define CSR_MISA_X_SHIFT (23U) -#define CSR_MISA_X_GET(x) (((uint32_t)(x) & CSR_MISA_X_MASK) >> CSR_MISA_X_SHIFT) - -/* - * W (RO) - * - * Reserved - */ -#define CSR_MISA_W_MASK (0x400000UL) -#define CSR_MISA_W_SHIFT (22U) -#define CSR_MISA_W_GET(x) (((uint32_t)(x) & CSR_MISA_W_MASK) >> CSR_MISA_W_SHIFT) - -/* - * V (RO) - * - * Tentatively reserved for Vector extension - */ -#define CSR_MISA_V_MASK (0x200000UL) -#define CSR_MISA_V_SHIFT (21U) -#define CSR_MISA_V_GET(x) (((uint32_t)(x) & CSR_MISA_V_MASK) >> CSR_MISA_V_SHIFT) - -/* - * U (RO) - * - * User mode implemented - * 0:Machine - * 1:Machine + User / Machine + Supervisor + User - */ -#define CSR_MISA_U_MASK (0x100000UL) -#define CSR_MISA_U_SHIFT (20U) -#define CSR_MISA_U_GET(x) (((uint32_t)(x) & CSR_MISA_U_MASK) >> CSR_MISA_U_SHIFT) - -/* - * T (RO) - * - * Tentatively reserved for Transactional Memory extension - */ -#define CSR_MISA_T_MASK (0x80000UL) -#define CSR_MISA_T_SHIFT (19U) -#define CSR_MISA_T_GET(x) (((uint32_t)(x) & CSR_MISA_T_MASK) >> CSR_MISA_T_SHIFT) - -/* - * S (RO) - * - * Supervisor mode implemented - * 0:Machine / Machine + User - * 1:Machine + Supervisor + User - */ -#define CSR_MISA_S_MASK (0x40000UL) -#define CSR_MISA_S_SHIFT (18U) -#define CSR_MISA_S_GET(x) (((uint32_t)(x) & CSR_MISA_S_MASK) >> CSR_MISA_S_SHIFT) - -/* - * R (RO) - * - * Reserved - */ -#define CSR_MISA_R_MASK (0x20000UL) -#define CSR_MISA_R_SHIFT (17U) -#define CSR_MISA_R_GET(x) (((uint32_t)(x) & CSR_MISA_R_MASK) >> CSR_MISA_R_SHIFT) - -/* - * Q (RO) - * - * Quad-precision floating-point extension - */ -#define CSR_MISA_Q_MASK (0x10000UL) -#define CSR_MISA_Q_SHIFT (16U) -#define CSR_MISA_Q_GET(x) (((uint32_t)(x) & CSR_MISA_Q_MASK) >> CSR_MISA_Q_SHIFT) - -/* - * P (RO) - * - * Tentatively reserved for Packed-SIMD extension - */ -#define CSR_MISA_P_MASK (0x8000U) -#define CSR_MISA_P_SHIFT (15U) -#define CSR_MISA_P_GET(x) (((uint32_t)(x) & CSR_MISA_P_MASK) >> CSR_MISA_P_SHIFT) - -/* - * O (RO) - * - * Reserved - */ -#define CSR_MISA_O_MASK (0x4000U) -#define CSR_MISA_O_SHIFT (14U) -#define CSR_MISA_O_GET(x) (((uint32_t)(x) & CSR_MISA_O_MASK) >> CSR_MISA_O_SHIFT) - -/* - * N (RO) - * - * User-level interrupts supported - * 0:no - * 1:yes - */ -#define CSR_MISA_N_MASK (0x2000U) -#define CSR_MISA_N_SHIFT (13U) -#define CSR_MISA_N_GET(x) (((uint32_t)(x) & CSR_MISA_N_MASK) >> CSR_MISA_N_SHIFT) - -/* - * M (RO) - * - * Integer Multiply/Divide extension - */ -#define CSR_MISA_M_MASK (0x1000U) -#define CSR_MISA_M_SHIFT (12U) -#define CSR_MISA_M_GET(x) (((uint32_t)(x) & CSR_MISA_M_MASK) >> CSR_MISA_M_SHIFT) - -/* - * L (RO) - * - * Tentatively reserved for Decimal Floating-Point extension - */ -#define CSR_MISA_L_MASK (0x800U) -#define CSR_MISA_L_SHIFT (11U) -#define CSR_MISA_L_GET(x) (((uint32_t)(x) & CSR_MISA_L_MASK) >> CSR_MISA_L_SHIFT) - -/* - * K (RO) - * - * Reserved - */ -#define CSR_MISA_K_MASK (0x400U) -#define CSR_MISA_K_SHIFT (10U) -#define CSR_MISA_K_GET(x) (((uint32_t)(x) & CSR_MISA_K_MASK) >> CSR_MISA_K_SHIFT) - -/* - * J (RO) - * - * Tentatively reserved for Dynamically Translated Languages extension - */ -#define CSR_MISA_J_MASK (0x200U) -#define CSR_MISA_J_SHIFT (9U) -#define CSR_MISA_J_GET(x) (((uint32_t)(x) & CSR_MISA_J_MASK) >> CSR_MISA_J_SHIFT) - -/* - * I (RO) - * - * RV32I/64I/128I base ISA - */ -#define CSR_MISA_I_MASK (0x100U) -#define CSR_MISA_I_SHIFT (8U) -#define CSR_MISA_I_GET(x) (((uint32_t)(x) & CSR_MISA_I_MASK) >> CSR_MISA_I_SHIFT) - -/* - * H (RO) - * - * Reserved - */ -#define CSR_MISA_H_MASK (0x80U) -#define CSR_MISA_H_SHIFT (7U) -#define CSR_MISA_H_GET(x) (((uint32_t)(x) & CSR_MISA_H_MASK) >> CSR_MISA_H_SHIFT) - -/* - * G (RO) - * - * Additional standard extensions present - */ -#define CSR_MISA_G_MASK (0x40U) -#define CSR_MISA_G_SHIFT (6U) -#define CSR_MISA_G_GET(x) (((uint32_t)(x) & CSR_MISA_G_MASK) >> CSR_MISA_G_SHIFT) - -/* - * F (RO) - * - * Single-precision floating-point extension - * 0:none - * 1:double+single precision / single precision - */ -#define CSR_MISA_F_MASK (0x20U) -#define CSR_MISA_F_SHIFT (5U) -#define CSR_MISA_F_GET(x) (((uint32_t)(x) & CSR_MISA_F_MASK) >> CSR_MISA_F_SHIFT) - -/* - * E (RO) - * - * RV32E base ISA - */ -#define CSR_MISA_E_MASK (0x10U) -#define CSR_MISA_E_SHIFT (4U) -#define CSR_MISA_E_GET(x) (((uint32_t)(x) & CSR_MISA_E_MASK) >> CSR_MISA_E_SHIFT) - -/* - * D (RO) - * - * Double-precision floating-point extension - * 0:single precision / none - * 1:double+single precision - */ -#define CSR_MISA_D_MASK (0x8U) -#define CSR_MISA_D_SHIFT (3U) -#define CSR_MISA_D_GET(x) (((uint32_t)(x) & CSR_MISA_D_MASK) >> CSR_MISA_D_SHIFT) - -/* - * C (RO) - * - * Compressed extension - */ -#define CSR_MISA_C_MASK (0x4U) -#define CSR_MISA_C_SHIFT (2U) -#define CSR_MISA_C_GET(x) (((uint32_t)(x) & CSR_MISA_C_MASK) >> CSR_MISA_C_SHIFT) - -/* - * B (RO) - * - * Tentatively reserved for Bit operations extension - */ -#define CSR_MISA_B_MASK (0x2U) -#define CSR_MISA_B_SHIFT (1U) -#define CSR_MISA_B_GET(x) (((uint32_t)(x) & CSR_MISA_B_MASK) >> CSR_MISA_B_SHIFT) - -/* - * A (RO) - * - * Atomic extension - * 0:no - * 1:yes - */ -#define CSR_MISA_A_MASK (0x1U) -#define CSR_MISA_A_SHIFT (0U) -#define CSR_MISA_A_GET(x) (((uint32_t)(x) & CSR_MISA_A_MASK) >> CSR_MISA_A_SHIFT) - -/* Bitfield definition for register: MEDELEG */ -/* - * SPF (RW) - * - * SPF indicates whether a Store/AMO Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SPF_MASK (0x8000U) -#define CSR_MEDELEG_SPF_SHIFT (15U) -#define CSR_MEDELEG_SPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SPF_SHIFT) & CSR_MEDELEG_SPF_MASK) -#define CSR_MEDELEG_SPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SPF_MASK) >> CSR_MEDELEG_SPF_SHIFT) - -/* - * LPF (RW) - * - * LPF indicates whether a Load Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LPF_MASK (0x2000U) -#define CSR_MEDELEG_LPF_SHIFT (13U) -#define CSR_MEDELEG_LPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LPF_SHIFT) & CSR_MEDELEG_LPF_MASK) -#define CSR_MEDELEG_LPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LPF_MASK) >> CSR_MEDELEG_LPF_SHIFT) - -/* - * IPF (RW) - * - * IPF indicates whether an Instruction Page Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IPF_MASK (0x1000U) -#define CSR_MEDELEG_IPF_SHIFT (12U) -#define CSR_MEDELEG_IPF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IPF_SHIFT) & CSR_MEDELEG_IPF_MASK) -#define CSR_MEDELEG_IPF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IPF_MASK) >> CSR_MEDELEG_IPF_SHIFT) - -/* - * SEC (RW) - * - * SEC indicates whether an exception triggered by environment call from S-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SEC_MASK (0x200U) -#define CSR_MEDELEG_SEC_SHIFT (9U) -#define CSR_MEDELEG_SEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SEC_SHIFT) & CSR_MEDELEG_SEC_MASK) -#define CSR_MEDELEG_SEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SEC_MASK) >> CSR_MEDELEG_SEC_SHIFT) - -/* - * UEC (RW) - * - * UEC indicates whether an exception triggered by environment call from U-mode will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_UEC_MASK (0x100U) -#define CSR_MEDELEG_UEC_SHIFT (8U) -#define CSR_MEDELEG_UEC_SET(x) (((uint32_t)(x) << CSR_MEDELEG_UEC_SHIFT) & CSR_MEDELEG_UEC_MASK) -#define CSR_MEDELEG_UEC_GET(x) (((uint32_t)(x) & CSR_MEDELEG_UEC_MASK) >> CSR_MEDELEG_UEC_SHIFT) - -/* - * SAF (RW) - * - * SAF indicates whether a Store/AMO Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAF_MASK (0x80U) -#define CSR_MEDELEG_SAF_SHIFT (7U) -#define CSR_MEDELEG_SAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAF_SHIFT) & CSR_MEDELEG_SAF_MASK) -#define CSR_MEDELEG_SAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAF_MASK) >> CSR_MEDELEG_SAF_SHIFT) - -/* - * SAM (RW) - * - * SAM indicates whether a Store/AMO Address Misaligned exception will be delegated to S-mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_SAM_MASK (0x40U) -#define CSR_MEDELEG_SAM_SHIFT (6U) -#define CSR_MEDELEG_SAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_SAM_SHIFT) & CSR_MEDELEG_SAM_MASK) -#define CSR_MEDELEG_SAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_SAM_MASK) >> CSR_MEDELEG_SAM_SHIFT) - -/* - * LAF (RW) - * - * LAF indicates whether a Load Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAF_MASK (0x20U) -#define CSR_MEDELEG_LAF_SHIFT (5U) -#define CSR_MEDELEG_LAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAF_SHIFT) & CSR_MEDELEG_LAF_MASK) -#define CSR_MEDELEG_LAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAF_MASK) >> CSR_MEDELEG_LAF_SHIFT) - -/* - * LAM (RW) - * - * LAM indicates whether a Load Address Misaligned exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_LAM_MASK (0x10U) -#define CSR_MEDELEG_LAM_SHIFT (4U) -#define CSR_MEDELEG_LAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_LAM_SHIFT) & CSR_MEDELEG_LAM_MASK) -#define CSR_MEDELEG_LAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_LAM_MASK) >> CSR_MEDELEG_LAM_SHIFT) - -/* - * II (RW) - * - * II indicates whether an Illegal Instruction exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_II_MASK (0x4U) -#define CSR_MEDELEG_II_SHIFT (2U) -#define CSR_MEDELEG_II_SET(x) (((uint32_t)(x) << CSR_MEDELEG_II_SHIFT) & CSR_MEDELEG_II_MASK) -#define CSR_MEDELEG_II_GET(x) (((uint32_t)(x) & CSR_MEDELEG_II_MASK) >> CSR_MEDELEG_II_SHIFT) - -/* - * IAF (RW) - * - * IAF indicates whether an Instruction Access Fault exception will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAF_MASK (0x2U) -#define CSR_MEDELEG_IAF_SHIFT (1U) -#define CSR_MEDELEG_IAF_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAF_SHIFT) & CSR_MEDELEG_IAF_MASK) -#define CSR_MEDELEG_IAF_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAF_MASK) >> CSR_MEDELEG_IAF_SHIFT) - -/* - * IAM (RW) - * - * IAM indicates whether an Instruction Address Misaligned exception will be delegated to S-Mode - * 0:Not delegate - * 1:delegate - */ -#define CSR_MEDELEG_IAM_MASK (0x1U) -#define CSR_MEDELEG_IAM_SHIFT (0U) -#define CSR_MEDELEG_IAM_SET(x) (((uint32_t)(x) << CSR_MEDELEG_IAM_SHIFT) & CSR_MEDELEG_IAM_MASK) -#define CSR_MEDELEG_IAM_GET(x) (((uint32_t)(x) & CSR_MEDELEG_IAM_MASK) >> CSR_MEDELEG_IAM_SHIFT) - -/* Bitfield definition for register: MIDELEG */ -/* - * SEI (RW) - * - * SEI indicates whether an S-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SEI_MASK (0x200U) -#define CSR_MIDELEG_SEI_SHIFT (9U) -#define CSR_MIDELEG_SEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SEI_SHIFT) & CSR_MIDELEG_SEI_MASK) -#define CSR_MIDELEG_SEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SEI_MASK) >> CSR_MIDELEG_SEI_SHIFT) - -/* - * UEI (RW) - * - * UEI indicates whether an U-mode external interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UEI_MASK (0x100U) -#define CSR_MIDELEG_UEI_SHIFT (8U) -#define CSR_MIDELEG_UEI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UEI_SHIFT) & CSR_MIDELEG_UEI_MASK) -#define CSR_MIDELEG_UEI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UEI_MASK) >> CSR_MIDELEG_UEI_SHIFT) - -/* - * STI (RW) - * - * STI indicates whether an S-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_STI_MASK (0x20U) -#define CSR_MIDELEG_STI_SHIFT (5U) -#define CSR_MIDELEG_STI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_STI_SHIFT) & CSR_MIDELEG_STI_MASK) -#define CSR_MIDELEG_STI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_STI_MASK) >> CSR_MIDELEG_STI_SHIFT) - -/* - * UTI (RW) - * - * UTI indicates whether an U-mode timer interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_UTI_MASK (0x10U) -#define CSR_MIDELEG_UTI_SHIFT (4U) -#define CSR_MIDELEG_UTI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_UTI_SHIFT) & CSR_MIDELEG_UTI_MASK) -#define CSR_MIDELEG_UTI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_UTI_MASK) >> CSR_MIDELEG_UTI_SHIFT) - -/* - * SSI (RW) - * - * SSI indicates whether an S-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_SSI_MASK (0x2U) -#define CSR_MIDELEG_SSI_SHIFT (1U) -#define CSR_MIDELEG_SSI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_SSI_SHIFT) & CSR_MIDELEG_SSI_MASK) -#define CSR_MIDELEG_SSI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_SSI_MASK) >> CSR_MIDELEG_SSI_SHIFT) - -/* - * USI (RW) - * - * USI indicates whether an U-mode software interrupt will be delegated to S-mode. - * 0:Not delegate - * 1:delegate - */ -#define CSR_MIDELEG_USI_MASK (0x1U) -#define CSR_MIDELEG_USI_SHIFT (0U) -#define CSR_MIDELEG_USI_SET(x) (((uint32_t)(x) << CSR_MIDELEG_USI_SHIFT) & CSR_MIDELEG_USI_MASK) -#define CSR_MIDELEG_USI_GET(x) (((uint32_t)(x) & CSR_MIDELEG_USI_MASK) >> CSR_MIDELEG_USI_SHIFT) - -/* Bitfield definition for register: MIE */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_PMOVI_MASK (0x40000UL) -#define CSR_MIE_PMOVI_SHIFT (18U) -#define CSR_MIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIE_PMOVI_SHIFT) & CSR_MIE_PMOVI_MASK) -#define CSR_MIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIE_PMOVI_MASK) >> CSR_MIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt enable bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_BWEI_MASK (0x20000UL) -#define CSR_MIE_BWEI_SHIFT (17U) -#define CSR_MIE_BWEI_SET(x) (((uint32_t)(x) << CSR_MIE_BWEI_SHIFT) & CSR_MIE_BWEI_MASK) -#define CSR_MIE_BWEI_GET(x) (((uint32_t)(x) & CSR_MIE_BWEI_MASK) >> CSR_MIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_IMECCI_MASK (0x10000UL) -#define CSR_MIE_IMECCI_SHIFT (16U) -#define CSR_MIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIE_IMECCI_SHIFT) & CSR_MIE_IMECCI_MASK) -#define CSR_MIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIE_IMECCI_MASK) >> CSR_MIE_IMECCI_SHIFT) - -/* - * MEIE (RW) - * - * M mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MEIE_MASK (0x800U) -#define CSR_MIE_MEIE_SHIFT (11U) -#define CSR_MIE_MEIE_SET(x) (((uint32_t)(x) << CSR_MIE_MEIE_SHIFT) & CSR_MIE_MEIE_MASK) -#define CSR_MIE_MEIE_GET(x) (((uint32_t)(x) & CSR_MIE_MEIE_MASK) >> CSR_MIE_MEIE_SHIFT) - -/* - * SEIE (RW) - * - * S mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SEIE_MASK (0x200U) -#define CSR_MIE_SEIE_SHIFT (9U) -#define CSR_MIE_SEIE_SET(x) (((uint32_t)(x) << CSR_MIE_SEIE_SHIFT) & CSR_MIE_SEIE_MASK) -#define CSR_MIE_SEIE_GET(x) (((uint32_t)(x) & CSR_MIE_SEIE_MASK) >> CSR_MIE_SEIE_SHIFT) - -/* - * UEIE (RW) - * - * U mode external interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UEIE_MASK (0x100U) -#define CSR_MIE_UEIE_SHIFT (8U) -#define CSR_MIE_UEIE_SET(x) (((uint32_t)(x) << CSR_MIE_UEIE_SHIFT) & CSR_MIE_UEIE_MASK) -#define CSR_MIE_UEIE_GET(x) (((uint32_t)(x) & CSR_MIE_UEIE_MASK) >> CSR_MIE_UEIE_SHIFT) - -/* - * MTIE (RW) - * - * M mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MTIE_MASK (0x80U) -#define CSR_MIE_MTIE_SHIFT (7U) -#define CSR_MIE_MTIE_SET(x) (((uint32_t)(x) << CSR_MIE_MTIE_SHIFT) & CSR_MIE_MTIE_MASK) -#define CSR_MIE_MTIE_GET(x) (((uint32_t)(x) & CSR_MIE_MTIE_MASK) >> CSR_MIE_MTIE_SHIFT) - -/* - * STIE (RW) - * - * S mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_STIE_MASK (0x20U) -#define CSR_MIE_STIE_SHIFT (5U) -#define CSR_MIE_STIE_SET(x) (((uint32_t)(x) << CSR_MIE_STIE_SHIFT) & CSR_MIE_STIE_MASK) -#define CSR_MIE_STIE_GET(x) (((uint32_t)(x) & CSR_MIE_STIE_MASK) >> CSR_MIE_STIE_SHIFT) - -/* - * UTIE (RW) - * - * U mode timer interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_UTIE_MASK (0x10U) -#define CSR_MIE_UTIE_SHIFT (4U) -#define CSR_MIE_UTIE_SET(x) (((uint32_t)(x) << CSR_MIE_UTIE_SHIFT) & CSR_MIE_UTIE_MASK) -#define CSR_MIE_UTIE_GET(x) (((uint32_t)(x) & CSR_MIE_UTIE_MASK) >> CSR_MIE_UTIE_SHIFT) - -/* - * MSIE (RW) - * - * M mode software interrupt enable bit - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_MSIE_MASK (0x8U) -#define CSR_MIE_MSIE_SHIFT (3U) -#define CSR_MIE_MSIE_SET(x) (((uint32_t)(x) << CSR_MIE_MSIE_SHIFT) & CSR_MIE_MSIE_MASK) -#define CSR_MIE_MSIE_GET(x) (((uint32_t)(x) & CSR_MIE_MSIE_MASK) >> CSR_MIE_MSIE_SHIFT) - -/* - * SSIE (RW) - * - * S mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_SSIE_MASK (0x2U) -#define CSR_MIE_SSIE_SHIFT (1U) -#define CSR_MIE_SSIE_SET(x) (((uint32_t)(x) << CSR_MIE_SSIE_SHIFT) & CSR_MIE_SSIE_MASK) -#define CSR_MIE_SSIE_GET(x) (((uint32_t)(x) & CSR_MIE_SSIE_MASK) >> CSR_MIE_SSIE_SHIFT) - -/* - * USIE (RW) - * - * U mode software interrupt enable bit. - * 0:Disabled - * 1:Enabled - */ -#define CSR_MIE_USIE_MASK (0x1U) -#define CSR_MIE_USIE_SHIFT (0U) -#define CSR_MIE_USIE_SET(x) (((uint32_t)(x) << CSR_MIE_USIE_SHIFT) & CSR_MIE_USIE_MASK) -#define CSR_MIE_USIE_GET(x) (((uint32_t)(x) & CSR_MIE_USIE_MASK) >> CSR_MIE_USIE_SHIFT) - -/* Bitfield definition for register: MTVEC */ -/* - * BASE_31_2 (RW) - * - * Base address for interrupt and exception handlers. See description above for alignment requirements when PLIC is in the vector mode - */ -#define CSR_MTVEC_BASE_31_2_MASK (0xFFFFFFFCUL) -#define CSR_MTVEC_BASE_31_2_SHIFT (2U) -#define CSR_MTVEC_BASE_31_2_SET(x) (((uint32_t)(x) << CSR_MTVEC_BASE_31_2_SHIFT) & CSR_MTVEC_BASE_31_2_MASK) -#define CSR_MTVEC_BASE_31_2_GET(x) (((uint32_t)(x) & CSR_MTVEC_BASE_31_2_MASK) >> CSR_MTVEC_BASE_31_2_SHIFT) - -/* Bitfield definition for register: MCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_MCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_MCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM6_SHIFT) & CSR_MCOUNTEREN_HPM6_MASK) -#define CSR_MCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM6_MASK) >> CSR_MCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_MCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_MCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM5_SHIFT) & CSR_MCOUNTEREN_HPM5_MASK) -#define CSR_MCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM5_MASK) >> CSR_MCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_MCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_MCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM4_SHIFT) & CSR_MCOUNTEREN_HPM4_MASK) -#define CSR_MCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM4_MASK) >> CSR_MCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_MCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_MCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_HPM3_SHIFT) & CSR_MCOUNTEREN_HPM3_MASK) -#define CSR_MCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_HPM3_MASK) >> CSR_MCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_IR_MASK (0x4U) -#define CSR_MCOUNTEREN_IR_SHIFT (2U) -#define CSR_MCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_IR_SHIFT) & CSR_MCOUNTEREN_IR_MASK) -#define CSR_MCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_IR_MASK) >> CSR_MCOUNTEREN_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_TM_MASK (0x2U) -#define CSR_MCOUNTEREN_TM_SHIFT (1U) -#define CSR_MCOUNTEREN_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_TM_SHIFT) & CSR_MCOUNTEREN_TM_MASK) -#define CSR_MCOUNTEREN_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_TM_MASK) >> CSR_MCOUNTEREN_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEREN_CY_MASK (0x1U) -#define CSR_MCOUNTEREN_CY_SHIFT (0U) -#define CSR_MCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEREN_CY_SHIFT) & CSR_MCOUNTEREN_CY_MASK) -#define CSR_MCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEREN_CY_MASK) >> CSR_MCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT3_SEL_SHIFT (4U) -#define CSR_MHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_SEL_SHIFT) & CSR_MHPMEVENT3_SEL_MASK) -#define CSR_MHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_SEL_MASK) >> CSR_MHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT3_TYPE_SHIFT) & CSR_MHPMEVENT3_TYPE_MASK) -#define CSR_MHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT3_TYPE_MASK) >> CSR_MHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT4_SEL_SHIFT (4U) -#define CSR_MHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_SEL_SHIFT) & CSR_MHPMEVENT4_SEL_MASK) -#define CSR_MHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_SEL_MASK) >> CSR_MHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT4_TYPE_SHIFT) & CSR_MHPMEVENT4_TYPE_MASK) -#define CSR_MHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT4_TYPE_MASK) >> CSR_MHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT5_SEL_SHIFT (4U) -#define CSR_MHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_SEL_SHIFT) & CSR_MHPMEVENT5_SEL_MASK) -#define CSR_MHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_SEL_MASK) >> CSR_MHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT5_TYPE_SHIFT) & CSR_MHPMEVENT5_TYPE_MASK) -#define CSR_MHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT5_TYPE_MASK) >> CSR_MHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: MHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_MHPMEVENT6_SEL_SHIFT (4U) -#define CSR_MHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_SEL_SHIFT) & CSR_MHPMEVENT6_SEL_MASK) -#define CSR_MHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_SEL_MASK) >> CSR_MHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_MHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_MHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_MHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_MHPMEVENT6_TYPE_SHIFT) & CSR_MHPMEVENT6_TYPE_MASK) -#define CSR_MHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_MHPMEVENT6_TYPE_MASK) >> CSR_MHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MSCRATCH */ -/* - * MSCRATCH (RW) - * - * Scratch register storage. - */ -#define CSR_MSCRATCH_MSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_MSCRATCH_MSCRATCH_SHIFT (0U) -#define CSR_MSCRATCH_MSCRATCH_SET(x) (((uint32_t)(x) << CSR_MSCRATCH_MSCRATCH_SHIFT) & CSR_MSCRATCH_MSCRATCH_MASK) -#define CSR_MSCRATCH_MSCRATCH_GET(x) (((uint32_t)(x) & CSR_MSCRATCH_MSCRATCH_MASK) >> CSR_MSCRATCH_MSCRATCH_SHIFT) - -/* Bitfield definition for register: MEPC */ -/* - * EPC (RW) - * - * Exception program counter. - */ -#define CSR_MEPC_EPC_MASK (0xFFFFFFFEUL) -#define CSR_MEPC_EPC_SHIFT (1U) -#define CSR_MEPC_EPC_SET(x) (((uint32_t)(x) << CSR_MEPC_EPC_SHIFT) & CSR_MEPC_EPC_MASK) -#define CSR_MEPC_EPC_GET(x) (((uint32_t)(x) & CSR_MEPC_EPC_MASK) >> CSR_MEPC_EPC_SHIFT) - -/* Bitfield definition for register: MCAUSE */ -/* - * INTERRUPT (RW) - * - * Interrupt - */ -#define CSR_MCAUSE_INTERRUPT_MASK (0x80000000UL) -#define CSR_MCAUSE_INTERRUPT_SHIFT (31U) -#define CSR_MCAUSE_INTERRUPT_SET(x) (((uint32_t)(x) << CSR_MCAUSE_INTERRUPT_SHIFT) & CSR_MCAUSE_INTERRUPT_MASK) -#define CSR_MCAUSE_INTERRUPT_GET(x) (((uint32_t)(x) & CSR_MCAUSE_INTERRUPT_MASK) >> CSR_MCAUSE_INTERRUPT_SHIFT) - -/* - * EXCEPTION_CODE (RW) - * - * Exception code - * When interrupt is 1, the value means: - * 0:User software interrupt - * 1:Supervisor software interrupt - * 3:Machine software interrupt - * 4:User timer interrupt - * 5:Supervisor timer interrupt - * 7:Machine timer interrupt - * 8:User external interrupt - * 9:Supervisor external interrupt - * 11:Machine external interrupt - * 16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (M-mode) - * 17:Bus read/write transaction error interrupt (M-mode) - * 18:Performance monitor overflow interrupt (M-mode) - * 256+16:Imprecise ECC error interrupt (slave port accesses, D-Cache evictions, and nonblocking load/stores) (S-mode) - * 256+17:Bus write transaction error interrupt (S-mode) - * 256+18:Performance monitor overflow interrupt (S-mode) - * When interrupt bit is 0, the value means: - * 0:Instruction address misaligned - * 1:Instruction access fault - * 2:Illegal instruction - * 3:Breakpoint - * 4:Load address misaligned - * 5:Load access fault - * 6:Store/AMO address misaligned - * 7:Store/AMO access fault - * 8:Environment call from U-mode - * 9:Environment call from S-mode - * 11:Environment call from M-mode - * 32:Stack overflow exception - * 33:Stack underflow exception - * 40-47:Reserved - */ -#define CSR_MCAUSE_EXCEPTION_CODE_MASK (0xFFFU) -#define CSR_MCAUSE_EXCEPTION_CODE_SHIFT (0U) -#define CSR_MCAUSE_EXCEPTION_CODE_SET(x) (((uint32_t)(x) << CSR_MCAUSE_EXCEPTION_CODE_SHIFT) & CSR_MCAUSE_EXCEPTION_CODE_MASK) -#define CSR_MCAUSE_EXCEPTION_CODE_GET(x) (((uint32_t)(x) & CSR_MCAUSE_EXCEPTION_CODE_MASK) >> CSR_MCAUSE_EXCEPTION_CODE_SHIFT) - -/* Bitfield definition for register: MTVAL */ -/* - * MTVAL (RW) - * - * Exception-specific information for software trap handling. - */ -#define CSR_MTVAL_MTVAL_MASK (0xFFFFFFFFUL) -#define CSR_MTVAL_MTVAL_SHIFT (0U) -#define CSR_MTVAL_MTVAL_SET(x) (((uint32_t)(x) << CSR_MTVAL_MTVAL_SHIFT) & CSR_MTVAL_MTVAL_MASK) -#define CSR_MTVAL_MTVAL_GET(x) (((uint32_t)(x) & CSR_MTVAL_MTVAL_MASK) >> CSR_MTVAL_MTVAL_SHIFT) - -/* Bitfield definition for register: MIP */ -/* - * PMOVI (RW) - * - * Performance monitor overflow local interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_PMOVI_MASK (0x40000UL) -#define CSR_MIP_PMOVI_SHIFT (18U) -#define CSR_MIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_MIP_PMOVI_SHIFT) & CSR_MIP_PMOVI_MASK) -#define CSR_MIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_MIP_PMOVI_MASK) >> CSR_MIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Bus read/write transaction error local interrupt pending bit. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_BWEI_MASK (0x20000UL) -#define CSR_MIP_BWEI_SHIFT (17U) -#define CSR_MIP_BWEI_SET(x) (((uint32_t)(x) << CSR_MIP_BWEI_SHIFT) & CSR_MIP_BWEI_MASK) -#define CSR_MIP_BWEI_GET(x) (((uint32_t)(x) & CSR_MIP_BWEI_MASK) >> CSR_MIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Imprecise ECC error local interrupt enable bit. The processor may receive imprecise ECC errors on slave port accesses or cache writebacks. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_IMECCI_MASK (0x10000UL) -#define CSR_MIP_IMECCI_SHIFT (16U) -#define CSR_MIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_MIP_IMECCI_SHIFT) & CSR_MIP_IMECCI_MASK) -#define CSR_MIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_MIP_IMECCI_MASK) >> CSR_MIP_IMECCI_SHIFT) - -/* - * MEIP (RW) - * - * M mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MEIP_MASK (0x800U) -#define CSR_MIP_MEIP_SHIFT (11U) -#define CSR_MIP_MEIP_SET(x) (((uint32_t)(x) << CSR_MIP_MEIP_SHIFT) & CSR_MIP_MEIP_MASK) -#define CSR_MIP_MEIP_GET(x) (((uint32_t)(x) & CSR_MIP_MEIP_MASK) >> CSR_MIP_MEIP_SHIFT) - -/* - * SEIP (RW) - * - * S mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SEIP_MASK (0x200U) -#define CSR_MIP_SEIP_SHIFT (9U) -#define CSR_MIP_SEIP_SET(x) (((uint32_t)(x) << CSR_MIP_SEIP_SHIFT) & CSR_MIP_SEIP_MASK) -#define CSR_MIP_SEIP_GET(x) (((uint32_t)(x) & CSR_MIP_SEIP_MASK) >> CSR_MIP_SEIP_SHIFT) - -/* - * UEIP (RW) - * - * U mode external interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UEIP_MASK (0x100U) -#define CSR_MIP_UEIP_SHIFT (8U) -#define CSR_MIP_UEIP_SET(x) (((uint32_t)(x) << CSR_MIP_UEIP_SHIFT) & CSR_MIP_UEIP_MASK) -#define CSR_MIP_UEIP_GET(x) (((uint32_t)(x) & CSR_MIP_UEIP_MASK) >> CSR_MIP_UEIP_SHIFT) - -/* - * MTIP (RW) - * - * M mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MTIP_MASK (0x80U) -#define CSR_MIP_MTIP_SHIFT (7U) -#define CSR_MIP_MTIP_SET(x) (((uint32_t)(x) << CSR_MIP_MTIP_SHIFT) & CSR_MIP_MTIP_MASK) -#define CSR_MIP_MTIP_GET(x) (((uint32_t)(x) & CSR_MIP_MTIP_MASK) >> CSR_MIP_MTIP_SHIFT) - -/* - * STIP (RW) - * - * S mode timer interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_STIP_MASK (0x20U) -#define CSR_MIP_STIP_SHIFT (5U) -#define CSR_MIP_STIP_SET(x) (((uint32_t)(x) << CSR_MIP_STIP_SHIFT) & CSR_MIP_STIP_MASK) -#define CSR_MIP_STIP_GET(x) (((uint32_t)(x) & CSR_MIP_STIP_MASK) >> CSR_MIP_STIP_SHIFT) - -/* - * UTIP (RW) - * - * U mode timer interrupt pending bit - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_UTIP_MASK (0x10U) -#define CSR_MIP_UTIP_SHIFT (4U) -#define CSR_MIP_UTIP_SET(x) (((uint32_t)(x) << CSR_MIP_UTIP_SHIFT) & CSR_MIP_UTIP_MASK) -#define CSR_MIP_UTIP_GET(x) (((uint32_t)(x) & CSR_MIP_UTIP_MASK) >> CSR_MIP_UTIP_SHIFT) - -/* - * MSIP (RW) - * - * M mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_MSIP_MASK (0x8U) -#define CSR_MIP_MSIP_SHIFT (3U) -#define CSR_MIP_MSIP_SET(x) (((uint32_t)(x) << CSR_MIP_MSIP_SHIFT) & CSR_MIP_MSIP_MASK) -#define CSR_MIP_MSIP_GET(x) (((uint32_t)(x) & CSR_MIP_MSIP_MASK) >> CSR_MIP_MSIP_SHIFT) - -/* - * SSIP (RW) - * - * S mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_SSIP_MASK (0x2U) -#define CSR_MIP_SSIP_SHIFT (1U) -#define CSR_MIP_SSIP_SET(x) (((uint32_t)(x) << CSR_MIP_SSIP_SHIFT) & CSR_MIP_SSIP_MASK) -#define CSR_MIP_SSIP_GET(x) (((uint32_t)(x) & CSR_MIP_SSIP_MASK) >> CSR_MIP_SSIP_SHIFT) - -/* - * USIP (RW) - * - * U mode software interrupt pending bit. - * 0:Not pending - * 1:Pending - */ -#define CSR_MIP_USIP_MASK (0x1U) -#define CSR_MIP_USIP_SHIFT (0U) -#define CSR_MIP_USIP_SET(x) (((uint32_t)(x) << CSR_MIP_USIP_SHIFT) & CSR_MIP_USIP_MASK) -#define CSR_MIP_USIP_GET(x) (((uint32_t)(x) & CSR_MIP_USIP_MASK) >> CSR_MIP_USIP_SHIFT) - -/* Bitfield definition for register: PMPCFG0 */ -/* - * PMP3CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP3CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG0_PMP3CFG_SHIFT (24U) -#define CSR_PMPCFG0_PMP3CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP3CFG_SHIFT) & CSR_PMPCFG0_PMP3CFG_MASK) -#define CSR_PMPCFG0_PMP3CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP3CFG_MASK) >> CSR_PMPCFG0_PMP3CFG_SHIFT) - -/* - * PMP2CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP2CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG0_PMP2CFG_SHIFT (16U) -#define CSR_PMPCFG0_PMP2CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP2CFG_SHIFT) & CSR_PMPCFG0_PMP2CFG_MASK) -#define CSR_PMPCFG0_PMP2CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP2CFG_MASK) >> CSR_PMPCFG0_PMP2CFG_SHIFT) - -/* - * PMP1CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP1CFG_MASK (0xFF00U) -#define CSR_PMPCFG0_PMP1CFG_SHIFT (8U) -#define CSR_PMPCFG0_PMP1CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP1CFG_SHIFT) & CSR_PMPCFG0_PMP1CFG_MASK) -#define CSR_PMPCFG0_PMP1CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP1CFG_MASK) >> CSR_PMPCFG0_PMP1CFG_SHIFT) - -/* - * PMP0CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG0_PMP0CFG_MASK (0xFFU) -#define CSR_PMPCFG0_PMP0CFG_SHIFT (0U) -#define CSR_PMPCFG0_PMP0CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG0_PMP0CFG_SHIFT) & CSR_PMPCFG0_PMP0CFG_MASK) -#define CSR_PMPCFG0_PMP0CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG0_PMP0CFG_MASK) >> CSR_PMPCFG0_PMP0CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG1 */ -/* - * PMP7CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP7CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG1_PMP7CFG_SHIFT (24U) -#define CSR_PMPCFG1_PMP7CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP7CFG_SHIFT) & CSR_PMPCFG1_PMP7CFG_MASK) -#define CSR_PMPCFG1_PMP7CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP7CFG_MASK) >> CSR_PMPCFG1_PMP7CFG_SHIFT) - -/* - * PMP6CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP6CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG1_PMP6CFG_SHIFT (16U) -#define CSR_PMPCFG1_PMP6CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP6CFG_SHIFT) & CSR_PMPCFG1_PMP6CFG_MASK) -#define CSR_PMPCFG1_PMP6CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP6CFG_MASK) >> CSR_PMPCFG1_PMP6CFG_SHIFT) - -/* - * PMP5CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP5CFG_MASK (0xFF00U) -#define CSR_PMPCFG1_PMP5CFG_SHIFT (8U) -#define CSR_PMPCFG1_PMP5CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP5CFG_SHIFT) & CSR_PMPCFG1_PMP5CFG_MASK) -#define CSR_PMPCFG1_PMP5CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP5CFG_MASK) >> CSR_PMPCFG1_PMP5CFG_SHIFT) - -/* - * PMP4CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG1_PMP4CFG_MASK (0xFFU) -#define CSR_PMPCFG1_PMP4CFG_SHIFT (0U) -#define CSR_PMPCFG1_PMP4CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG1_PMP4CFG_SHIFT) & CSR_PMPCFG1_PMP4CFG_MASK) -#define CSR_PMPCFG1_PMP4CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG1_PMP4CFG_MASK) >> CSR_PMPCFG1_PMP4CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG2 */ -/* - * PMP11CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP11CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG2_PMP11CFG_SHIFT (24U) -#define CSR_PMPCFG2_PMP11CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP11CFG_SHIFT) & CSR_PMPCFG2_PMP11CFG_MASK) -#define CSR_PMPCFG2_PMP11CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP11CFG_MASK) >> CSR_PMPCFG2_PMP11CFG_SHIFT) - -/* - * PMP10CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP10CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG2_PMP10CFG_SHIFT (16U) -#define CSR_PMPCFG2_PMP10CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP10CFG_SHIFT) & CSR_PMPCFG2_PMP10CFG_MASK) -#define CSR_PMPCFG2_PMP10CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP10CFG_MASK) >> CSR_PMPCFG2_PMP10CFG_SHIFT) - -/* - * PMP9CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP9CFG_MASK (0xFF00U) -#define CSR_PMPCFG2_PMP9CFG_SHIFT (8U) -#define CSR_PMPCFG2_PMP9CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP9CFG_SHIFT) & CSR_PMPCFG2_PMP9CFG_MASK) -#define CSR_PMPCFG2_PMP9CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP9CFG_MASK) >> CSR_PMPCFG2_PMP9CFG_SHIFT) - -/* - * PMP8CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG2_PMP8CFG_MASK (0xFFU) -#define CSR_PMPCFG2_PMP8CFG_SHIFT (0U) -#define CSR_PMPCFG2_PMP8CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG2_PMP8CFG_SHIFT) & CSR_PMPCFG2_PMP8CFG_MASK) -#define CSR_PMPCFG2_PMP8CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG2_PMP8CFG_MASK) >> CSR_PMPCFG2_PMP8CFG_SHIFT) - -/* Bitfield definition for register: PMPCFG3 */ -/* - * PMP15CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP15CFG_MASK (0xFF000000UL) -#define CSR_PMPCFG3_PMP15CFG_SHIFT (24U) -#define CSR_PMPCFG3_PMP15CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP15CFG_SHIFT) & CSR_PMPCFG3_PMP15CFG_MASK) -#define CSR_PMPCFG3_PMP15CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP15CFG_MASK) >> CSR_PMPCFG3_PMP15CFG_SHIFT) - -/* - * PMP14CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP14CFG_MASK (0xFF0000UL) -#define CSR_PMPCFG3_PMP14CFG_SHIFT (16U) -#define CSR_PMPCFG3_PMP14CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP14CFG_SHIFT) & CSR_PMPCFG3_PMP14CFG_MASK) -#define CSR_PMPCFG3_PMP14CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP14CFG_MASK) >> CSR_PMPCFG3_PMP14CFG_SHIFT) - -/* - * PMP13CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP13CFG_MASK (0xFF00U) -#define CSR_PMPCFG3_PMP13CFG_SHIFT (8U) -#define CSR_PMPCFG3_PMP13CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP13CFG_SHIFT) & CSR_PMPCFG3_PMP13CFG_MASK) -#define CSR_PMPCFG3_PMP13CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP13CFG_MASK) >> CSR_PMPCFG3_PMP13CFG_SHIFT) - -/* - * PMP12CFG (RW) - * - * See PMPCFG Table - */ -#define CSR_PMPCFG3_PMP12CFG_MASK (0xFFU) -#define CSR_PMPCFG3_PMP12CFG_SHIFT (0U) -#define CSR_PMPCFG3_PMP12CFG_SET(x) (((uint32_t)(x) << CSR_PMPCFG3_PMP12CFG_SHIFT) & CSR_PMPCFG3_PMP12CFG_MASK) -#define CSR_PMPCFG3_PMP12CFG_GET(x) (((uint32_t)(x) & CSR_PMPCFG3_PMP12CFG_MASK) >> CSR_PMPCFG3_PMP12CFG_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaa0 8 - * aaaa. . . aa01 16 - * aaaa. . . a011 32 - * . . . . . . - * aa01. . . 1111 2^{XLEN} - * a011. . . 1111 2^{XLEN+1} - * 0111. . . 1111 2^{XLEN+2} - * 1111. . . 1111 2^{XLEN+3*1} - */ -#define CSR_PMPADDR0_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR0_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR0_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR0_PMPADDR_31_2_SHIFT) & CSR_PMPADDR0_PMPADDR_31_2_MASK) -#define CSR_PMPADDR0_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR0_PMPADDR_31_2_MASK) >> CSR_PMPADDR0_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR1_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR1_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR1_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR1_PMPADDR_31_2_SHIFT) & CSR_PMPADDR1_PMPADDR_31_2_MASK) -#define CSR_PMPADDR1_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR1_PMPADDR_31_2_MASK) >> CSR_PMPADDR1_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR2_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR2_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR2_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR2_PMPADDR_31_2_SHIFT) & CSR_PMPADDR2_PMPADDR_31_2_MASK) -#define CSR_PMPADDR2_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR2_PMPADDR_31_2_MASK) >> CSR_PMPADDR2_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR3_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR3_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR3_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR3_PMPADDR_31_2_SHIFT) & CSR_PMPADDR3_PMPADDR_31_2_MASK) -#define CSR_PMPADDR3_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR3_PMPADDR_31_2_MASK) >> CSR_PMPADDR3_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR4_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR4_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR4_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR4_PMPADDR_31_2_SHIFT) & CSR_PMPADDR4_PMPADDR_31_2_MASK) -#define CSR_PMPADDR4_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR4_PMPADDR_31_2_MASK) >> CSR_PMPADDR4_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR5_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR5_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR5_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR5_PMPADDR_31_2_SHIFT) & CSR_PMPADDR5_PMPADDR_31_2_MASK) -#define CSR_PMPADDR5_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR5_PMPADDR_31_2_MASK) >> CSR_PMPADDR5_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR6_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR6_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR6_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR6_PMPADDR_31_2_SHIFT) & CSR_PMPADDR6_PMPADDR_31_2_MASK) -#define CSR_PMPADDR6_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR6_PMPADDR_31_2_MASK) >> CSR_PMPADDR6_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR7_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR7_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR7_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR7_PMPADDR_31_2_SHIFT) & CSR_PMPADDR7_PMPADDR_31_2_MASK) -#define CSR_PMPADDR7_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR7_PMPADDR_31_2_MASK) >> CSR_PMPADDR7_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR8_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR8_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR8_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR8_PMPADDR_31_2_SHIFT) & CSR_PMPADDR8_PMPADDR_31_2_MASK) -#define CSR_PMPADDR8_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR8_PMPADDR_31_2_MASK) >> CSR_PMPADDR8_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR9_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR9_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR9_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR9_PMPADDR_31_2_SHIFT) & CSR_PMPADDR9_PMPADDR_31_2_MASK) -#define CSR_PMPADDR9_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR9_PMPADDR_31_2_MASK) >> CSR_PMPADDR9_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR10_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR10_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR10_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR10_PMPADDR_31_2_SHIFT) & CSR_PMPADDR10_PMPADDR_31_2_MASK) -#define CSR_PMPADDR10_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR10_PMPADDR_31_2_MASK) >> CSR_PMPADDR10_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR11_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR11_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR11_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR11_PMPADDR_31_2_SHIFT) & CSR_PMPADDR11_PMPADDR_31_2_MASK) -#define CSR_PMPADDR11_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR11_PMPADDR_31_2_MASK) >> CSR_PMPADDR11_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR12_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR12_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR12_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR12_PMPADDR_31_2_SHIFT) & CSR_PMPADDR12_PMPADDR_31_2_MASK) -#define CSR_PMPADDR12_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR12_PMPADDR_31_2_MASK) >> CSR_PMPADDR12_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR13_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR13_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR13_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR13_PMPADDR_31_2_SHIFT) & CSR_PMPADDR13_PMPADDR_31_2_MASK) -#define CSR_PMPADDR13_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR13_PMPADDR_31_2_MASK) >> CSR_PMPADDR13_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR14_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR14_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR14_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR14_PMPADDR_31_2_SHIFT) & CSR_PMPADDR14_PMPADDR_31_2_MASK) -#define CSR_PMPADDR14_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR14_PMPADDR_31_2_MASK) >> CSR_PMPADDR14_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMPADDR */ -/* - * PMPADDR_31_2 (RW) - * - * same as pmpaddr0 - */ -#define CSR_PMPADDR15_PMPADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMPADDR15_PMPADDR_31_2_SHIFT (2U) -#define CSR_PMPADDR15_PMPADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMPADDR15_PMPADDR_31_2_SHIFT) & CSR_PMPADDR15_PMPADDR_31_2_MASK) -#define CSR_PMPADDR15_PMPADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMPADDR15_PMPADDR_31_2_MASK) >> CSR_PMPADDR15_PMPADDR_31_2_SHIFT) - -/* Bitfield definition for register: TSELECT */ -/* - * TRIGGER_INDEX (RW) - * - * This register determines which trigger is accessible through other trigger registers. - */ -#define CSR_TSELECT_TRIGGER_INDEX_MASK (0xFFFFFFFFUL) -#define CSR_TSELECT_TRIGGER_INDEX_SHIFT (0U) -#define CSR_TSELECT_TRIGGER_INDEX_SET(x) (((uint32_t)(x) << CSR_TSELECT_TRIGGER_INDEX_SHIFT) & CSR_TSELECT_TRIGGER_INDEX_MASK) -#define CSR_TSELECT_TRIGGER_INDEX_GET(x) (((uint32_t)(x) & CSR_TSELECT_TRIGGER_INDEX_MASK) >> CSR_TSELECT_TRIGGER_INDEX_SHIFT) - -/* Bitfield definition for register: TDATA1 */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - * 3:The selected trigger is an instruction count trigger - * 4:The selected trigger is an interrupt trigger. - * 5:The selected trigger is an exception trigger. - */ -#define CSR_TDATA1_TYPE_MASK (0xF0000000UL) -#define CSR_TDATA1_TYPE_SHIFT (28U) -#define CSR_TDATA1_TYPE_SET(x) (((uint32_t)(x) << CSR_TDATA1_TYPE_SHIFT) & CSR_TDATA1_TYPE_MASK) -#define CSR_TDATA1_TYPE_GET(x) (((uint32_t)(x) & CSR_TDATA1_TYPE_MASK) >> CSR_TDATA1_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_TDATA1_DMODE_MASK (0x8000000UL) -#define CSR_TDATA1_DMODE_SHIFT (27U) -#define CSR_TDATA1_DMODE_SET(x) (((uint32_t)(x) << CSR_TDATA1_DMODE_SHIFT) & CSR_TDATA1_DMODE_MASK) -#define CSR_TDATA1_DMODE_GET(x) (((uint32_t)(x) & CSR_TDATA1_DMODE_MASK) >> CSR_TDATA1_DMODE_SHIFT) - -/* - * DATA (RW) - * - * Trigger-specific data - */ -#define CSR_TDATA1_DATA_MASK (0x7FFFFFFUL) -#define CSR_TDATA1_DATA_SHIFT (0U) -#define CSR_TDATA1_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA1_DATA_SHIFT) & CSR_TDATA1_DATA_MASK) -#define CSR_TDATA1_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA1_DATA_MASK) >> CSR_TDATA1_DATA_SHIFT) - -/* Bitfield definition for register: MCONTROL */ -/* - * TYPE (RW) - * - * Indicates the trigger type. - * 0:The selected trigger is invalid. - * 2:The selected trigger is an address/data match trigger. - */ -#define CSR_MCONTROL_TYPE_MASK (0xF0000000UL) -#define CSR_MCONTROL_TYPE_SHIFT (28U) -#define CSR_MCONTROL_TYPE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_TYPE_SHIFT) & CSR_MCONTROL_TYPE_MASK) -#define CSR_MCONTROL_TYPE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_TYPE_MASK) >> CSR_MCONTROL_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_MCONTROL_DMODE_MASK (0x8000000UL) -#define CSR_MCONTROL_DMODE_SHIFT (27U) -#define CSR_MCONTROL_DMODE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_DMODE_SHIFT) & CSR_MCONTROL_DMODE_MASK) -#define CSR_MCONTROL_DMODE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_DMODE_MASK) >> CSR_MCONTROL_DMODE_SHIFT) - -/* - * MASKMAX (RO) - * - * Indicates the largest naturally aligned range supported by the hardware is 2ˆ12 bytes. - */ -#define CSR_MCONTROL_MASKMAX_MASK (0x7E00000UL) -#define CSR_MCONTROL_MASKMAX_SHIFT (21U) -#define CSR_MCONTROL_MASKMAX_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MASKMAX_MASK) >> CSR_MCONTROL_MASKMAX_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_MCONTROL_ACTION_MASK (0xF000U) -#define CSR_MCONTROL_ACTION_SHIFT (12U) -#define CSR_MCONTROL_ACTION_SET(x) (((uint32_t)(x) << CSR_MCONTROL_ACTION_SHIFT) & CSR_MCONTROL_ACTION_MASK) -#define CSR_MCONTROL_ACTION_GET(x) (((uint32_t)(x) & CSR_MCONTROL_ACTION_MASK) >> CSR_MCONTROL_ACTION_SHIFT) - -/* - * CHAIN (RW) - * - * Setting this field to enable trigger chain. - * 0:When this trigger matches, the configured action is taken. - * 1:While this trigger does not match, it prevents the trigger with the next index from matching. - * If Number of Triggers is 2, this field is hardwired to 0 on trigger 1 (tselect = 1). - * If Number of Triggers is 4, this field is hardwired - * to 0 on trigger 3 (tselect = 3). - * If Number of Triggers is 8, this field is hardwired to 0 on trigger 3 and trigger 7 (tselect = 3 or 7). - */ -#define CSR_MCONTROL_CHAIN_MASK (0x800U) -#define CSR_MCONTROL_CHAIN_SHIFT (11U) -#define CSR_MCONTROL_CHAIN_SET(x) (((uint32_t)(x) << CSR_MCONTROL_CHAIN_SHIFT) & CSR_MCONTROL_CHAIN_MASK) -#define CSR_MCONTROL_CHAIN_GET(x) (((uint32_t)(x) & CSR_MCONTROL_CHAIN_MASK) >> CSR_MCONTROL_CHAIN_SHIFT) - -/* - * MATCH (RW) - * - * Setting this field to select the matching scheme. 0:Matches when the value equals tdata2. 1:Matches when the top M bits of the value match the top M bits of tdata2. M is 31 minus the index of the least-significant bit containing 0 in tdata2. - * 2:Matches when the value is greater than (unsigned) or equal to tdata2. - * 3:Matches when the value is less than (unsigned) tdata2 - */ -#define CSR_MCONTROL_MATCH_MASK (0x780U) -#define CSR_MCONTROL_MATCH_SHIFT (7U) -#define CSR_MCONTROL_MATCH_SET(x) (((uint32_t)(x) << CSR_MCONTROL_MATCH_SHIFT) & CSR_MCONTROL_MATCH_MASK) -#define CSR_MCONTROL_MATCH_GET(x) (((uint32_t)(x) & CSR_MCONTROL_MATCH_MASK) >> CSR_MCONTROL_MATCH_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_MCONTROL_M_MASK (0x40U) -#define CSR_MCONTROL_M_SHIFT (6U) -#define CSR_MCONTROL_M_SET(x) (((uint32_t)(x) << CSR_MCONTROL_M_SHIFT) & CSR_MCONTROL_M_MASK) -#define CSR_MCONTROL_M_GET(x) (((uint32_t)(x) & CSR_MCONTROL_M_MASK) >> CSR_MCONTROL_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_MCONTROL_S_MASK (0x10U) -#define CSR_MCONTROL_S_SHIFT (4U) -#define CSR_MCONTROL_S_SET(x) (((uint32_t)(x) << CSR_MCONTROL_S_SHIFT) & CSR_MCONTROL_S_MASK) -#define CSR_MCONTROL_S_GET(x) (((uint32_t)(x) & CSR_MCONTROL_S_MASK) >> CSR_MCONTROL_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_MCONTROL_U_MASK (0x8U) -#define CSR_MCONTROL_U_SHIFT (3U) -#define CSR_MCONTROL_U_SET(x) (((uint32_t)(x) << CSR_MCONTROL_U_SHIFT) & CSR_MCONTROL_U_MASK) -#define CSR_MCONTROL_U_GET(x) (((uint32_t)(x) & CSR_MCONTROL_U_MASK) >> CSR_MCONTROL_U_SHIFT) - -/* - * EXECUTE (RW) - * - * Setting this field to enable this trigger to compare virtual address of an instruction. - */ -#define CSR_MCONTROL_EXECUTE_MASK (0x4U) -#define CSR_MCONTROL_EXECUTE_SHIFT (2U) -#define CSR_MCONTROL_EXECUTE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_EXECUTE_SHIFT) & CSR_MCONTROL_EXECUTE_MASK) -#define CSR_MCONTROL_EXECUTE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_EXECUTE_MASK) >> CSR_MCONTROL_EXECUTE_SHIFT) - -/* - * STORE (RW) - * - * Setting this field to enable this trigger to compare virtual address of a store. - */ -#define CSR_MCONTROL_STORE_MASK (0x2U) -#define CSR_MCONTROL_STORE_SHIFT (1U) -#define CSR_MCONTROL_STORE_SET(x) (((uint32_t)(x) << CSR_MCONTROL_STORE_SHIFT) & CSR_MCONTROL_STORE_MASK) -#define CSR_MCONTROL_STORE_GET(x) (((uint32_t)(x) & CSR_MCONTROL_STORE_MASK) >> CSR_MCONTROL_STORE_SHIFT) - -/* - * LOAD (RW) - * - * Setting this field to enable this trigger to compare virtual address of a load. - */ -#define CSR_MCONTROL_LOAD_MASK (0x1U) -#define CSR_MCONTROL_LOAD_SHIFT (0U) -#define CSR_MCONTROL_LOAD_SET(x) (((uint32_t)(x) << CSR_MCONTROL_LOAD_SHIFT) & CSR_MCONTROL_LOAD_MASK) -#define CSR_MCONTROL_LOAD_GET(x) (((uint32_t)(x) & CSR_MCONTROL_LOAD_MASK) >> CSR_MCONTROL_LOAD_SHIFT) - -/* Bitfield definition for register: ICOUNT */ -/* - * TYPE (RW) - * - * The selected trigger is an instruction count trigger. - */ -#define CSR_ICOUNT_TYPE_MASK (0xF0000000UL) -#define CSR_ICOUNT_TYPE_SHIFT (28U) -#define CSR_ICOUNT_TYPE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_TYPE_SHIFT) & CSR_ICOUNT_TYPE_MASK) -#define CSR_ICOUNT_TYPE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_TYPE_MASK) >> CSR_ICOUNT_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ICOUNT_DMODE_MASK (0x8000000UL) -#define CSR_ICOUNT_DMODE_SHIFT (27U) -#define CSR_ICOUNT_DMODE_SET(x) (((uint32_t)(x) << CSR_ICOUNT_DMODE_SHIFT) & CSR_ICOUNT_DMODE_MASK) -#define CSR_ICOUNT_DMODE_GET(x) (((uint32_t)(x) & CSR_ICOUNT_DMODE_MASK) >> CSR_ICOUNT_DMODE_SHIFT) - -/* - * COUNT (RO) - * - * This field is hardwired to 1 for single-stepping support - */ -#define CSR_ICOUNT_COUNT_MASK (0x400U) -#define CSR_ICOUNT_COUNT_SHIFT (10U) -#define CSR_ICOUNT_COUNT_GET(x) (((uint32_t)(x) & CSR_ICOUNT_COUNT_MASK) >> CSR_ICOUNT_COUNT_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ICOUNT_M_MASK (0x200U) -#define CSR_ICOUNT_M_SHIFT (9U) -#define CSR_ICOUNT_M_SET(x) (((uint32_t)(x) << CSR_ICOUNT_M_SHIFT) & CSR_ICOUNT_M_MASK) -#define CSR_ICOUNT_M_GET(x) (((uint32_t)(x) & CSR_ICOUNT_M_MASK) >> CSR_ICOUNT_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ICOUNT_S_MASK (0x80U) -#define CSR_ICOUNT_S_SHIFT (7U) -#define CSR_ICOUNT_S_SET(x) (((uint32_t)(x) << CSR_ICOUNT_S_SHIFT) & CSR_ICOUNT_S_MASK) -#define CSR_ICOUNT_S_GET(x) (((uint32_t)(x) & CSR_ICOUNT_S_MASK) >> CSR_ICOUNT_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ICOUNT_U_MASK (0x40U) -#define CSR_ICOUNT_U_SHIFT (6U) -#define CSR_ICOUNT_U_SET(x) (((uint32_t)(x) << CSR_ICOUNT_U_SHIFT) & CSR_ICOUNT_U_MASK) -#define CSR_ICOUNT_U_GET(x) (((uint32_t)(x) & CSR_ICOUNT_U_MASK) >> CSR_ICOUNT_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ICOUNT_ACTION_MASK (0x3FU) -#define CSR_ICOUNT_ACTION_SHIFT (0U) -#define CSR_ICOUNT_ACTION_SET(x) (((uint32_t)(x) << CSR_ICOUNT_ACTION_SHIFT) & CSR_ICOUNT_ACTION_MASK) -#define CSR_ICOUNT_ACTION_GET(x) (((uint32_t)(x) & CSR_ICOUNT_ACTION_MASK) >> CSR_ICOUNT_ACTION_SHIFT) - -/* Bitfield definition for register: ITRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an interrupt trigger. - */ -#define CSR_ITRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ITRIGGER_TYPE_SHIFT (28U) -#define CSR_ITRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_TYPE_SHIFT) & CSR_ITRIGGER_TYPE_MASK) -#define CSR_ITRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_TYPE_MASK) >> CSR_ITRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ITRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ITRIGGER_DMODE_SHIFT (27U) -#define CSR_ITRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_DMODE_SHIFT) & CSR_ITRIGGER_DMODE_MASK) -#define CSR_ITRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_DMODE_MASK) >> CSR_ITRIGGER_DMODE_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ITRIGGER_M_MASK (0x200U) -#define CSR_ITRIGGER_M_SHIFT (9U) -#define CSR_ITRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_M_SHIFT) & CSR_ITRIGGER_M_MASK) -#define CSR_ITRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_M_MASK) >> CSR_ITRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ITRIGGER_S_MASK (0x80U) -#define CSR_ITRIGGER_S_SHIFT (7U) -#define CSR_ITRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_S_SHIFT) & CSR_ITRIGGER_S_MASK) -#define CSR_ITRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_S_MASK) >> CSR_ITRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ITRIGGER_U_MASK (0x40U) -#define CSR_ITRIGGER_U_SHIFT (6U) -#define CSR_ITRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_U_SHIFT) & CSR_ITRIGGER_U_MASK) -#define CSR_ITRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_U_MASK) >> CSR_ITRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception. - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ITRIGGER_ACTION_MASK (0x3FU) -#define CSR_ITRIGGER_ACTION_SHIFT (0U) -#define CSR_ITRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ITRIGGER_ACTION_SHIFT) & CSR_ITRIGGER_ACTION_MASK) -#define CSR_ITRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ITRIGGER_ACTION_MASK) >> CSR_ITRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: ETRIGGER */ -/* - * TYPE (RW) - * - * The selected trigger is an exception trigger. - */ -#define CSR_ETRIGGER_TYPE_MASK (0xF0000000UL) -#define CSR_ETRIGGER_TYPE_SHIFT (28U) -#define CSR_ETRIGGER_TYPE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_TYPE_SHIFT) & CSR_ETRIGGER_TYPE_MASK) -#define CSR_ETRIGGER_TYPE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_TYPE_MASK) >> CSR_ETRIGGER_TYPE_SHIFT) - -/* - * DMODE (RW) - * - * Setting this field to indicate the trigger is used by Debug Mode. - * 0:Both Debug-mode and M-mode can write the currently selected trigger registers. - * 1:Only Debug Mode can write the currently selected trigger registers. Writes from M-mode is ignored. - */ -#define CSR_ETRIGGER_DMODE_MASK (0x8000000UL) -#define CSR_ETRIGGER_DMODE_SHIFT (27U) -#define CSR_ETRIGGER_DMODE_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_DMODE_SHIFT) & CSR_ETRIGGER_DMODE_MASK) -#define CSR_ETRIGGER_DMODE_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_DMODE_MASK) >> CSR_ETRIGGER_DMODE_SHIFT) - -/* - * NMI (RW) - * - * Setting this field to enable this trigger in non-maskable interrupts, regardless of the values of s, u, and m. - */ -#define CSR_ETRIGGER_NMI_MASK (0x400U) -#define CSR_ETRIGGER_NMI_SHIFT (10U) -#define CSR_ETRIGGER_NMI_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_NMI_SHIFT) & CSR_ETRIGGER_NMI_MASK) -#define CSR_ETRIGGER_NMI_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_NMI_MASK) >> CSR_ETRIGGER_NMI_SHIFT) - -/* - * M (RW) - * - * Setting this field to enable this trigger in M-mode. - */ -#define CSR_ETRIGGER_M_MASK (0x200U) -#define CSR_ETRIGGER_M_SHIFT (9U) -#define CSR_ETRIGGER_M_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_M_SHIFT) & CSR_ETRIGGER_M_MASK) -#define CSR_ETRIGGER_M_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_M_MASK) >> CSR_ETRIGGER_M_SHIFT) - -/* - * S (RW) - * - * Setting this field to enable this trigger in S-mode. - */ -#define CSR_ETRIGGER_S_MASK (0x80U) -#define CSR_ETRIGGER_S_SHIFT (7U) -#define CSR_ETRIGGER_S_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_S_SHIFT) & CSR_ETRIGGER_S_MASK) -#define CSR_ETRIGGER_S_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_S_MASK) >> CSR_ETRIGGER_S_SHIFT) - -/* - * U (RW) - * - * Setting this field to enable this trigger in U-mode. - */ -#define CSR_ETRIGGER_U_MASK (0x40U) -#define CSR_ETRIGGER_U_SHIFT (6U) -#define CSR_ETRIGGER_U_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_U_SHIFT) & CSR_ETRIGGER_U_MASK) -#define CSR_ETRIGGER_U_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_U_MASK) >> CSR_ETRIGGER_U_SHIFT) - -/* - * ACTION (RW) - * - * Setting this field to select what happens when this trigger matches. - * 0:Raise a breakpoint exception - * 1:Enter Debug Mode. (Only supported when DMODE is 1.) - */ -#define CSR_ETRIGGER_ACTION_MASK (0x3FU) -#define CSR_ETRIGGER_ACTION_SHIFT (0U) -#define CSR_ETRIGGER_ACTION_SET(x) (((uint32_t)(x) << CSR_ETRIGGER_ACTION_SHIFT) & CSR_ETRIGGER_ACTION_MASK) -#define CSR_ETRIGGER_ACTION_GET(x) (((uint32_t)(x) & CSR_ETRIGGER_ACTION_MASK) >> CSR_ETRIGGER_ACTION_SHIFT) - -/* Bitfield definition for register: TDATA2 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata2 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA2_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA2_DATA_SHIFT (0U) -#define CSR_TDATA2_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA2_DATA_SHIFT) & CSR_TDATA2_DATA_MASK) -#define CSR_TDATA2_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA2_DATA_MASK) >> CSR_TDATA2_DATA_SHIFT) - -/* Bitfield definition for register: TDATA3 */ -/* - * DATA (RW) - * - * This register provides accesses to the tdata3 register of the currently selected trigger registers selected by the tselect register, and it holds trigger-specific data.. - */ -#define CSR_TDATA3_DATA_MASK (0xFFFFFFFFUL) -#define CSR_TDATA3_DATA_SHIFT (0U) -#define CSR_TDATA3_DATA_SET(x) (((uint32_t)(x) << CSR_TDATA3_DATA_SHIFT) & CSR_TDATA3_DATA_MASK) -#define CSR_TDATA3_DATA_GET(x) (((uint32_t)(x) & CSR_TDATA3_DATA_MASK) >> CSR_TDATA3_DATA_SHIFT) - -/* Bitfield definition for register: TEXTRA */ -/* - * MVALUE (RW) - * - * Data used together with MSELECT. - */ -#define CSR_TEXTRA_MVALUE_MASK (0xFC000000UL) -#define CSR_TEXTRA_MVALUE_SHIFT (26U) -#define CSR_TEXTRA_MVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MVALUE_SHIFT) & CSR_TEXTRA_MVALUE_MASK) -#define CSR_TEXTRA_MVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MVALUE_MASK) >> CSR_TEXTRA_MVALUE_SHIFT) - -/* - * MSELECT (RW) - * - * 0:Ignore MVALUE. - * 1:This trigger will only match if the lower bits of mcontext equal MVALUE. - */ -#define CSR_TEXTRA_MSELECT_MASK (0x2000000UL) -#define CSR_TEXTRA_MSELECT_SHIFT (25U) -#define CSR_TEXTRA_MSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_MSELECT_SHIFT) & CSR_TEXTRA_MSELECT_MASK) -#define CSR_TEXTRA_MSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_MSELECT_MASK) >> CSR_TEXTRA_MSELECT_SHIFT) - -/* - * SVALUE (RW) - * - * Data used together with SSELECT. - */ -#define CSR_TEXTRA_SVALUE_MASK (0x7FCU) -#define CSR_TEXTRA_SVALUE_SHIFT (2U) -#define CSR_TEXTRA_SVALUE_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SVALUE_SHIFT) & CSR_TEXTRA_SVALUE_MASK) -#define CSR_TEXTRA_SVALUE_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SVALUE_MASK) >> CSR_TEXTRA_SVALUE_SHIFT) - -/* - * SSELECT (RW) - * - * 0:Ignore MVALUE - * 1:This trigger will only match if the lower bits of scontext equal SVALUE - * 2This trigger will only match if satp.ASID equals SVALUE. - */ -#define CSR_TEXTRA_SSELECT_MASK (0x3U) -#define CSR_TEXTRA_SSELECT_SHIFT (0U) -#define CSR_TEXTRA_SSELECT_SET(x) (((uint32_t)(x) << CSR_TEXTRA_SSELECT_SHIFT) & CSR_TEXTRA_SSELECT_MASK) -#define CSR_TEXTRA_SSELECT_GET(x) (((uint32_t)(x) & CSR_TEXTRA_SSELECT_MASK) >> CSR_TEXTRA_SSELECT_SHIFT) - -/* Bitfield definition for register: TINFO */ -/* - * INFO (RO) - * - * One bit for each possible type in tdata1. Bit N corresponds to type N. If the bit is set, then that - * type is supported by the currently selected trigger. If the currently selected trigger does not exist, this field contains 1. - * 0:When this bit is set, there is no trigger at this tselect - * 1:Reserved and hardwired to 0. - * 2：When this bit is set, the selected trigger supports type of address/data match trigger - * 3:When this bit is set, the selected trigger supports type of instruction count trigger. - * 4:When this bit is set, the selected trigger supports type of interrupt trigger - * 5:When this bit is set, the selected trigger supports type of exception trigger - * 15:When this bit is set, the selected trigger exists (so enumeration shouldn’t terminate), but is not currently available. - * Others:Reserved for future use. - */ -#define CSR_TINFO_INFO_MASK (0xFFFFU) -#define CSR_TINFO_INFO_SHIFT (0U) -#define CSR_TINFO_INFO_GET(x) (((uint32_t)(x) & CSR_TINFO_INFO_MASK) >> CSR_TINFO_INFO_SHIFT) - -/* Bitfield definition for register: TCONTROL */ -/* - * MPTE (RW) - * - * M-mode previous trigger enable field. When a trap into M-mode is taken, MPTE is set to the value of MTE. - */ -#define CSR_TCONTROL_MPTE_MASK (0x80U) -#define CSR_TCONTROL_MPTE_SHIFT (7U) -#define CSR_TCONTROL_MPTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MPTE_SHIFT) & CSR_TCONTROL_MPTE_MASK) -#define CSR_TCONTROL_MPTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MPTE_MASK) >> CSR_TCONTROL_MPTE_SHIFT) - -/* - * MTE (RW) - * - * M-mode trigger enable field. When a trap into M-mode is taken, MTE is set to 0. When the MRET instruction is executed, MTE is set to the value of MPTE. - * 0:Triggers do not match/fire while the hart is in M-mode. - * 1:Triggers do match/fire while the hart is in M-mode. - */ -#define CSR_TCONTROL_MTE_MASK (0x8U) -#define CSR_TCONTROL_MTE_SHIFT (3U) -#define CSR_TCONTROL_MTE_SET(x) (((uint32_t)(x) << CSR_TCONTROL_MTE_SHIFT) & CSR_TCONTROL_MTE_MASK) -#define CSR_TCONTROL_MTE_GET(x) (((uint32_t)(x) & CSR_TCONTROL_MTE_MASK) >> CSR_TCONTROL_MTE_SHIFT) - -/* Bitfield definition for register: MCONTEXT */ -/* - * MCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_MCONTEXT_MCONTEXT_MASK (0x3FU) -#define CSR_MCONTEXT_MCONTEXT_SHIFT (0U) -#define CSR_MCONTEXT_MCONTEXT_SET(x) (((uint32_t)(x) << CSR_MCONTEXT_MCONTEXT_SHIFT) & CSR_MCONTEXT_MCONTEXT_MASK) -#define CSR_MCONTEXT_MCONTEXT_GET(x) (((uint32_t)(x) & CSR_MCONTEXT_MCONTEXT_MASK) >> CSR_MCONTEXT_MCONTEXT_SHIFT) - -/* Bitfield definition for register: SCONTEXT */ -/* - * SCONTEXT (RW) - * - * Machine mode software can write a context number to this register, which can be used to set triggers that only fire in that specific context. - */ -#define CSR_SCONTEXT_SCONTEXT_MASK (0x1FFU) -#define CSR_SCONTEXT_SCONTEXT_SHIFT (0U) -#define CSR_SCONTEXT_SCONTEXT_SET(x) (((uint32_t)(x) << CSR_SCONTEXT_SCONTEXT_SHIFT) & CSR_SCONTEXT_SCONTEXT_MASK) -#define CSR_SCONTEXT_SCONTEXT_GET(x) (((uint32_t)(x) & CSR_SCONTEXT_SCONTEXT_MASK) >> CSR_SCONTEXT_SCONTEXT_SHIFT) - -/* Bitfield definition for register: DCSR */ -/* - * XDEBUGVER (RO) - * - * Version of the external debugger. 0 indicates that no external debugger exists and 4 indicates that the external debugger conforms to the RISC-V External Debug Support (TD003) V0.13 - */ -#define CSR_DCSR_XDEBUGVER_MASK (0xF0000000UL) -#define CSR_DCSR_XDEBUGVER_SHIFT (28U) -#define CSR_DCSR_XDEBUGVER_GET(x) (((uint32_t)(x) & CSR_DCSR_XDEBUGVER_MASK) >> CSR_DCSR_XDEBUGVER_SHIFT) - -/* - * EBREAKM (RW) - * - * This bit controls the behavior of EBREAK instructions in Machine Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKM_MASK (0x8000U) -#define CSR_DCSR_EBREAKM_SHIFT (15U) -#define CSR_DCSR_EBREAKM_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKM_SHIFT) & CSR_DCSR_EBREAKM_MASK) -#define CSR_DCSR_EBREAKM_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKM_MASK) >> CSR_DCSR_EBREAKM_SHIFT) - -/* - * EBREAKS (RW) - * - * This bit controls the behavior of EBREAK instructions in Supervisor Mode. - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKS_MASK (0x2000U) -#define CSR_DCSR_EBREAKS_SHIFT (13U) -#define CSR_DCSR_EBREAKS_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKS_SHIFT) & CSR_DCSR_EBREAKS_MASK) -#define CSR_DCSR_EBREAKS_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKS_MASK) >> CSR_DCSR_EBREAKS_SHIFT) - -/* - * EBREAKU (RW) - * - * This bit controls the behavior of EBREAK instructions in User/Application Mode - * 0:Generate a regular breakpoint exception - * 1:Enter Debug Mode - */ -#define CSR_DCSR_EBREAKU_MASK (0x1000U) -#define CSR_DCSR_EBREAKU_SHIFT (12U) -#define CSR_DCSR_EBREAKU_SET(x) (((uint32_t)(x) << CSR_DCSR_EBREAKU_SHIFT) & CSR_DCSR_EBREAKU_MASK) -#define CSR_DCSR_EBREAKU_GET(x) (((uint32_t)(x) & CSR_DCSR_EBREAKU_MASK) >> CSR_DCSR_EBREAKU_SHIFT) - -/* - * STEPIE (RW) - * - * This bit controls whether interrupts are enabled during single stepping - * 0:Disable interrupts during single stepping - * 1:Allow interrupts in single stepping - */ -#define CSR_DCSR_STEPIE_MASK (0x800U) -#define CSR_DCSR_STEPIE_SHIFT (11U) -#define CSR_DCSR_STEPIE_SET(x) (((uint32_t)(x) << CSR_DCSR_STEPIE_SHIFT) & CSR_DCSR_STEPIE_MASK) -#define CSR_DCSR_STEPIE_GET(x) (((uint32_t)(x) & CSR_DCSR_STEPIE_MASK) >> CSR_DCSR_STEPIE_SHIFT) - -/* - * STOPCOUNT (RW) - * - * This bit controls whether performance counters are stopped in Debug Mode. - * 0:Do not stop counters in Debug Mode - * 1:Stop counters in Debug Mode - */ -#define CSR_DCSR_STOPCOUNT_MASK (0x400U) -#define CSR_DCSR_STOPCOUNT_SHIFT (10U) -#define CSR_DCSR_STOPCOUNT_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPCOUNT_SHIFT) & CSR_DCSR_STOPCOUNT_MASK) -#define CSR_DCSR_STOPCOUNT_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPCOUNT_MASK) >> CSR_DCSR_STOPCOUNT_SHIFT) - -/* - * STOPTIME (RW) - * - * This bit controls whether timers are stopped in Debug Mode. The processor only drives its stoptime output pin to 1 if it is in Debug Mode and this bit is set. Integration effort is required to make timers in the platform observe this pin to really stop them. - * 0:Do not stop timers in Debug Mode - * 1:Stop timers in Debug Mode - */ -#define CSR_DCSR_STOPTIME_MASK (0x200U) -#define CSR_DCSR_STOPTIME_SHIFT (9U) -#define CSR_DCSR_STOPTIME_SET(x) (((uint32_t)(x) << CSR_DCSR_STOPTIME_SHIFT) & CSR_DCSR_STOPTIME_MASK) -#define CSR_DCSR_STOPTIME_GET(x) (((uint32_t)(x) & CSR_DCSR_STOPTIME_MASK) >> CSR_DCSR_STOPTIME_SHIFT) - -/* - * CAUSE (RO) - * - * Reason why Debug Mode was entered. When there are multiple reasons to enter Debug Mode, the priority to determine the CAUSE value will be: trigger module > EBREAK > halt-on-reset > halt request > single step. Halt requests are requests issued by the external debugger - * 0:Reserved - * 1:EBREAK - * 2:Trigger module - * 3:Halt request - * 4:Single step - * 5:Halt-on-reset - * 6-7:Reserved - */ -#define CSR_DCSR_CAUSE_MASK (0x1C0U) -#define CSR_DCSR_CAUSE_SHIFT (6U) -#define CSR_DCSR_CAUSE_GET(x) (((uint32_t)(x) & CSR_DCSR_CAUSE_MASK) >> CSR_DCSR_CAUSE_SHIFT) - -/* - * MPRVEN (RW) - * - * This bit controls whether mstatus.MPRV takes effect in Debug Mode. - * 0:MPRV in mstatus is ignored in Debug Mode. - * 1:MPRV in mstatus takes effect in Debug Mode. - */ -#define CSR_DCSR_MPRVEN_MASK (0x10U) -#define CSR_DCSR_MPRVEN_SHIFT (4U) -#define CSR_DCSR_MPRVEN_SET(x) (((uint32_t)(x) << CSR_DCSR_MPRVEN_SHIFT) & CSR_DCSR_MPRVEN_MASK) -#define CSR_DCSR_MPRVEN_GET(x) (((uint32_t)(x) & CSR_DCSR_MPRVEN_MASK) >> CSR_DCSR_MPRVEN_SHIFT) - -/* - * NMIP (RO) - * - * When this bit is set, there is a Non-Maskable-Interrupt (NMI) pending for the hart. Since an NMI can indicate a hardware error condition, reliable debugging may no longer be possible once this bit becomes set. - */ -#define CSR_DCSR_NMIP_MASK (0x8U) -#define CSR_DCSR_NMIP_SHIFT (3U) -#define CSR_DCSR_NMIP_GET(x) (((uint32_t)(x) & CSR_DCSR_NMIP_MASK) >> CSR_DCSR_NMIP_SHIFT) - -/* - * STEP (RW) - * - * This bit controls whether non-Debug Mode instruction execution is in the single step mode. When set, the hart returns to Debug Mode after a single instruction execution. If the instruction does not complete due to an exception, the hart will immediately enter Debug Mode before executing the trap handler, with appropriate exception registers set. - * 0:Single Step Mode is off - * 1:Single Step Mode is on - */ -#define CSR_DCSR_STEP_MASK (0x4U) -#define CSR_DCSR_STEP_SHIFT (2U) -#define CSR_DCSR_STEP_SET(x) (((uint32_t)(x) << CSR_DCSR_STEP_SHIFT) & CSR_DCSR_STEP_MASK) -#define CSR_DCSR_STEP_GET(x) (((uint32_t)(x) & CSR_DCSR_STEP_MASK) >> CSR_DCSR_STEP_SHIFT) - -/* - * PRV (RW) - * - * The privilege level that the hart was operating in when Debug Mode was entered. The external debugger can modify this value to change the hart’s privilege level when exiting Debug Mode. - * 0:User/Application - * 1:Supervisor - * 2:Reserved - * 3:Machine - */ -#define CSR_DCSR_PRV_MASK (0x3U) -#define CSR_DCSR_PRV_SHIFT (0U) -#define CSR_DCSR_PRV_SET(x) (((uint32_t)(x) << CSR_DCSR_PRV_SHIFT) & CSR_DCSR_PRV_MASK) -#define CSR_DCSR_PRV_GET(x) (((uint32_t)(x) & CSR_DCSR_PRV_MASK) >> CSR_DCSR_PRV_SHIFT) - -/* Bitfield definition for register: DPC */ -/* - * DPC (RW) - * - * Debug Program Counter. Bit 0 is hardwired to 0. - */ -#define CSR_DPC_DPC_MASK (0xFFFFFFFFUL) -#define CSR_DPC_DPC_SHIFT (0U) -#define CSR_DPC_DPC_SET(x) (((uint32_t)(x) << CSR_DPC_DPC_SHIFT) & CSR_DPC_DPC_MASK) -#define CSR_DPC_DPC_GET(x) (((uint32_t)(x) & CSR_DPC_DPC_MASK) >> CSR_DPC_DPC_SHIFT) - -/* Bitfield definition for register: DSCRATCH0 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH0_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH0_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH0_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH0_DSCRATCH_MASK) >> CSR_DSCRATCH0_DSCRATCH_SHIFT) - -/* Bitfield definition for register: DSCRATCH1 */ -/* - * DSCRATCH (RO) - * - * A scratch register that is reserved for use by Debug Module. - */ -#define CSR_DSCRATCH1_DSCRATCH_MASK (0xFFFFFFFFUL) -#define CSR_DSCRATCH1_DSCRATCH_SHIFT (0U) -#define CSR_DSCRATCH1_DSCRATCH_GET(x) (((uint32_t)(x) & CSR_DSCRATCH1_DSCRATCH_MASK) >> CSR_DSCRATCH1_DSCRATCH_SHIFT) - -/* Bitfield definition for register: MCYCLE */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLE_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLE_COUNTER_SHIFT (0U) -#define CSR_MCYCLE_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLE_COUNTER_SHIFT) & CSR_MCYCLE_COUNTER_MASK) -#define CSR_MCYCLE_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLE_COUNTER_MASK) >> CSR_MCYCLE_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRET */ -/* - * COUNTER (RW) - * - * the lower 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRET_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRET_COUNTER_SHIFT (0U) -#define CSR_MINSTRET_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRET_COUNTER_SHIFT) & CSR_MINSTRET_COUNTER_MASK) -#define CSR_MINSTRET_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRET_COUNTER_MASK) >> CSR_MINSTRET_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3_COUNTER_SHIFT) & CSR_MHPMCOUNTER3_COUNTER_MASK) -#define CSR_MHPMCOUNTER3_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3_COUNTER_MASK) >> CSR_MHPMCOUNTER3_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4_COUNTER_SHIFT) & CSR_MHPMCOUNTER4_COUNTER_MASK) -#define CSR_MHPMCOUNTER4_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4_COUNTER_MASK) >> CSR_MHPMCOUNTER4_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5_COUNTER_SHIFT) & CSR_MHPMCOUNTER5_COUNTER_MASK) -#define CSR_MHPMCOUNTER5_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5_COUNTER_MASK) >> CSR_MHPMCOUNTER5_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6 */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6_COUNTER_SHIFT) & CSR_MHPMCOUNTER6_COUNTER_MASK) -#define CSR_MHPMCOUNTER6_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6_COUNTER_MASK) >> CSR_MHPMCOUNTER6_COUNTER_SHIFT) - -/* Bitfield definition for register: MCYCLEH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Cycle Counter - */ -#define CSR_MCYCLEH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MCYCLEH_COUNTER_SHIFT (0U) -#define CSR_MCYCLEH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MCYCLEH_COUNTER_SHIFT) & CSR_MCYCLEH_COUNTER_MASK) -#define CSR_MCYCLEH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MCYCLEH_COUNTER_MASK) >> CSR_MCYCLEH_COUNTER_SHIFT) - -/* Bitfield definition for register: MINSTRETH */ -/* - * COUNTER (RW) - * - * the higher 32 bits of Machine Instruction-Retired Counter - */ -#define CSR_MINSTRETH_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MINSTRETH_COUNTER_SHIFT (0U) -#define CSR_MINSTRETH_COUNTER_SET(x) (((uint32_t)(x) << CSR_MINSTRETH_COUNTER_SHIFT) & CSR_MINSTRETH_COUNTER_MASK) -#define CSR_MINSTRETH_COUNTER_GET(x) (((uint32_t)(x) & CSR_MINSTRETH_COUNTER_MASK) >> CSR_MINSTRETH_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER3H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent3 - */ -#define CSR_MHPMCOUNTER3H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER3H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER3H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER3H_COUNTER_SHIFT) & CSR_MHPMCOUNTER3H_COUNTER_MASK) -#define CSR_MHPMCOUNTER3H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER3H_COUNTER_MASK) >> CSR_MHPMCOUNTER3H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER4H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent4 - */ -#define CSR_MHPMCOUNTER4H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER4H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER4H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER4H_COUNTER_SHIFT) & CSR_MHPMCOUNTER4H_COUNTER_MASK) -#define CSR_MHPMCOUNTER4H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER4H_COUNTER_MASK) >> CSR_MHPMCOUNTER4H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER5H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent5 - */ -#define CSR_MHPMCOUNTER5H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER5H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER5H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER5H_COUNTER_SHIFT) & CSR_MHPMCOUNTER5H_COUNTER_MASK) -#define CSR_MHPMCOUNTER5H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER5H_COUNTER_MASK) >> CSR_MHPMCOUNTER5H_COUNTER_SHIFT) - -/* Bitfield definition for register: MHPMCOUNTER6H */ -/* - * COUNTER (RW) - * - * count the num- ber of events selected by mhpmevent6 - */ -#define CSR_MHPMCOUNTER6H_COUNTER_MASK (0xFFFFFFFFUL) -#define CSR_MHPMCOUNTER6H_COUNTER_SHIFT (0U) -#define CSR_MHPMCOUNTER6H_COUNTER_SET(x) (((uint32_t)(x) << CSR_MHPMCOUNTER6H_COUNTER_SHIFT) & CSR_MHPMCOUNTER6H_COUNTER_MASK) -#define CSR_MHPMCOUNTER6H_COUNTER_GET(x) (((uint32_t)(x) & CSR_MHPMCOUNTER6H_COUNTER_MASK) >> CSR_MHPMCOUNTER6H_COUNTER_SHIFT) - -/* Bitfield definition for register: PMACFG0 */ -/* - * PMA3CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA3CFG_MASK (0xFF000000UL) -#define CSR_PMACFG0_PMA3CFG_SHIFT (24U) -#define CSR_PMACFG0_PMA3CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA3CFG_SHIFT) & CSR_PMACFG0_PMA3CFG_MASK) -#define CSR_PMACFG0_PMA3CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA3CFG_MASK) >> CSR_PMACFG0_PMA3CFG_SHIFT) - -/* - * PMA2CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA2CFG_MASK (0xFF0000UL) -#define CSR_PMACFG0_PMA2CFG_SHIFT (16U) -#define CSR_PMACFG0_PMA2CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA2CFG_SHIFT) & CSR_PMACFG0_PMA2CFG_MASK) -#define CSR_PMACFG0_PMA2CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA2CFG_MASK) >> CSR_PMACFG0_PMA2CFG_SHIFT) - -/* - * PMA1CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA1CFG_MASK (0xFF00U) -#define CSR_PMACFG0_PMA1CFG_SHIFT (8U) -#define CSR_PMACFG0_PMA1CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA1CFG_SHIFT) & CSR_PMACFG0_PMA1CFG_MASK) -#define CSR_PMACFG0_PMA1CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA1CFG_MASK) >> CSR_PMACFG0_PMA1CFG_SHIFT) - -/* - * PMA0CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG0_PMA0CFG_MASK (0xFFU) -#define CSR_PMACFG0_PMA0CFG_SHIFT (0U) -#define CSR_PMACFG0_PMA0CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG0_PMA0CFG_SHIFT) & CSR_PMACFG0_PMA0CFG_MASK) -#define CSR_PMACFG0_PMA0CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG0_PMA0CFG_MASK) >> CSR_PMACFG0_PMA0CFG_SHIFT) - -/* Bitfield definition for register: PMACFG1 */ -/* - * PMA7CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA7CFG_MASK (0xFF000000UL) -#define CSR_PMACFG1_PMA7CFG_SHIFT (24U) -#define CSR_PMACFG1_PMA7CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA7CFG_SHIFT) & CSR_PMACFG1_PMA7CFG_MASK) -#define CSR_PMACFG1_PMA7CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA7CFG_MASK) >> CSR_PMACFG1_PMA7CFG_SHIFT) - -/* - * PMA6CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA6CFG_MASK (0xFF0000UL) -#define CSR_PMACFG1_PMA6CFG_SHIFT (16U) -#define CSR_PMACFG1_PMA6CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA6CFG_SHIFT) & CSR_PMACFG1_PMA6CFG_MASK) -#define CSR_PMACFG1_PMA6CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA6CFG_MASK) >> CSR_PMACFG1_PMA6CFG_SHIFT) - -/* - * PMA5CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA5CFG_MASK (0xFF00U) -#define CSR_PMACFG1_PMA5CFG_SHIFT (8U) -#define CSR_PMACFG1_PMA5CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA5CFG_SHIFT) & CSR_PMACFG1_PMA5CFG_MASK) -#define CSR_PMACFG1_PMA5CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA5CFG_MASK) >> CSR_PMACFG1_PMA5CFG_SHIFT) - -/* - * PMA4CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG1_PMA4CFG_MASK (0xFFU) -#define CSR_PMACFG1_PMA4CFG_SHIFT (0U) -#define CSR_PMACFG1_PMA4CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG1_PMA4CFG_SHIFT) & CSR_PMACFG1_PMA4CFG_MASK) -#define CSR_PMACFG1_PMA4CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG1_PMA4CFG_MASK) >> CSR_PMACFG1_PMA4CFG_SHIFT) - -/* Bitfield definition for register: PMACFG2 */ -/* - * PMA11CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA11CFG_MASK (0xFF000000UL) -#define CSR_PMACFG2_PMA11CFG_SHIFT (24U) -#define CSR_PMACFG2_PMA11CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA11CFG_SHIFT) & CSR_PMACFG2_PMA11CFG_MASK) -#define CSR_PMACFG2_PMA11CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA11CFG_MASK) >> CSR_PMACFG2_PMA11CFG_SHIFT) - -/* - * PMA10CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA10CFG_MASK (0xFF0000UL) -#define CSR_PMACFG2_PMA10CFG_SHIFT (16U) -#define CSR_PMACFG2_PMA10CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA10CFG_SHIFT) & CSR_PMACFG2_PMA10CFG_MASK) -#define CSR_PMACFG2_PMA10CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA10CFG_MASK) >> CSR_PMACFG2_PMA10CFG_SHIFT) - -/* - * PMA9CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA9CFG_MASK (0xFF00U) -#define CSR_PMACFG2_PMA9CFG_SHIFT (8U) -#define CSR_PMACFG2_PMA9CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA9CFG_SHIFT) & CSR_PMACFG2_PMA9CFG_MASK) -#define CSR_PMACFG2_PMA9CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA9CFG_MASK) >> CSR_PMACFG2_PMA9CFG_SHIFT) - -/* - * PMA8CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG2_PMA8CFG_MASK (0xFFU) -#define CSR_PMACFG2_PMA8CFG_SHIFT (0U) -#define CSR_PMACFG2_PMA8CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG2_PMA8CFG_SHIFT) & CSR_PMACFG2_PMA8CFG_MASK) -#define CSR_PMACFG2_PMA8CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG2_PMA8CFG_MASK) >> CSR_PMACFG2_PMA8CFG_SHIFT) - -/* Bitfield definition for register: PMACFG3 */ -/* - * PMA15CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA15CFG_MASK (0xFF000000UL) -#define CSR_PMACFG3_PMA15CFG_SHIFT (24U) -#define CSR_PMACFG3_PMA15CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA15CFG_SHIFT) & CSR_PMACFG3_PMA15CFG_MASK) -#define CSR_PMACFG3_PMA15CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA15CFG_MASK) >> CSR_PMACFG3_PMA15CFG_SHIFT) - -/* - * PMA14CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA14CFG_MASK (0xFF0000UL) -#define CSR_PMACFG3_PMA14CFG_SHIFT (16U) -#define CSR_PMACFG3_PMA14CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA14CFG_SHIFT) & CSR_PMACFG3_PMA14CFG_MASK) -#define CSR_PMACFG3_PMA14CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA14CFG_MASK) >> CSR_PMACFG3_PMA14CFG_SHIFT) - -/* - * PMA13CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA13CFG_MASK (0xFF00U) -#define CSR_PMACFG3_PMA13CFG_SHIFT (8U) -#define CSR_PMACFG3_PMA13CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA13CFG_SHIFT) & CSR_PMACFG3_PMA13CFG_MASK) -#define CSR_PMACFG3_PMA13CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA13CFG_MASK) >> CSR_PMACFG3_PMA13CFG_SHIFT) - -/* - * PMA12CFG (RW) - * - * See PMACFG Table - */ -#define CSR_PMACFG3_PMA12CFG_MASK (0xFFU) -#define CSR_PMACFG3_PMA12CFG_SHIFT (0U) -#define CSR_PMACFG3_PMA12CFG_SET(x) (((uint32_t)(x) << CSR_PMACFG3_PMA12CFG_SHIFT) & CSR_PMACFG3_PMA12CFG_MASK) -#define CSR_PMACFG3_PMA12CFG_GET(x) (((uint32_t)(x) & CSR_PMACFG3_PMA12CFG_MASK) >> CSR_PMACFG3_PMA12CFG_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * Register Content : Match Size(Byte) - * aaaa. . . aaaaaaaaaaa Reserved - * . . . . . . - * aaaa. . . aa011111111 Reserved - * aaaa. . . a0111111111 2^{12} - * aaaa. . . 01111111111 2^{13} - * . . . . . . - * aa01. . . 11111111111 2^{XLEN} - * a011. . . 11111111111 2^{XLEN+1} - * 0111. . . 11111111111 2^{XLEN+2} - * 1111. . . 11111111111 Reserved - */ -#define CSR_PMAADDR0_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR0_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR0_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR0_PMAADDR_31_2_SHIFT) & CSR_PMAADDR0_PMAADDR_31_2_MASK) -#define CSR_PMAADDR0_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR0_PMAADDR_31_2_MASK) >> CSR_PMAADDR0_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR1_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR1_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR1_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR1_PMAADDR_31_2_SHIFT) & CSR_PMAADDR1_PMAADDR_31_2_MASK) -#define CSR_PMAADDR1_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR1_PMAADDR_31_2_MASK) >> CSR_PMAADDR1_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR2_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR2_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR2_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR2_PMAADDR_31_2_SHIFT) & CSR_PMAADDR2_PMAADDR_31_2_MASK) -#define CSR_PMAADDR2_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR2_PMAADDR_31_2_MASK) >> CSR_PMAADDR2_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR3_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR3_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR3_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR3_PMAADDR_31_2_SHIFT) & CSR_PMAADDR3_PMAADDR_31_2_MASK) -#define CSR_PMAADDR3_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR3_PMAADDR_31_2_MASK) >> CSR_PMAADDR3_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR4_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR4_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR4_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR4_PMAADDR_31_2_SHIFT) & CSR_PMAADDR4_PMAADDR_31_2_MASK) -#define CSR_PMAADDR4_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR4_PMAADDR_31_2_MASK) >> CSR_PMAADDR4_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR5_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR5_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR5_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR5_PMAADDR_31_2_SHIFT) & CSR_PMAADDR5_PMAADDR_31_2_MASK) -#define CSR_PMAADDR5_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR5_PMAADDR_31_2_MASK) >> CSR_PMAADDR5_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR6_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR6_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR6_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR6_PMAADDR_31_2_SHIFT) & CSR_PMAADDR6_PMAADDR_31_2_MASK) -#define CSR_PMAADDR6_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR6_PMAADDR_31_2_MASK) >> CSR_PMAADDR6_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR7_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR7_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR7_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR7_PMAADDR_31_2_SHIFT) & CSR_PMAADDR7_PMAADDR_31_2_MASK) -#define CSR_PMAADDR7_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR7_PMAADDR_31_2_MASK) >> CSR_PMAADDR7_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR8_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR8_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR8_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR8_PMAADDR_31_2_SHIFT) & CSR_PMAADDR8_PMAADDR_31_2_MASK) -#define CSR_PMAADDR8_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR8_PMAADDR_31_2_MASK) >> CSR_PMAADDR8_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR9_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR9_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR9_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR9_PMAADDR_31_2_SHIFT) & CSR_PMAADDR9_PMAADDR_31_2_MASK) -#define CSR_PMAADDR9_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR9_PMAADDR_31_2_MASK) >> CSR_PMAADDR9_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR10_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR10_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR10_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR10_PMAADDR_31_2_SHIFT) & CSR_PMAADDR10_PMAADDR_31_2_MASK) -#define CSR_PMAADDR10_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR10_PMAADDR_31_2_MASK) >> CSR_PMAADDR10_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR11_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR11_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR11_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR11_PMAADDR_31_2_SHIFT) & CSR_PMAADDR11_PMAADDR_31_2_MASK) -#define CSR_PMAADDR11_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR11_PMAADDR_31_2_MASK) >> CSR_PMAADDR11_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR12_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR12_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR12_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR12_PMAADDR_31_2_SHIFT) & CSR_PMAADDR12_PMAADDR_31_2_MASK) -#define CSR_PMAADDR12_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR12_PMAADDR_31_2_MASK) >> CSR_PMAADDR12_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR13_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR13_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR13_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR13_PMAADDR_31_2_SHIFT) & CSR_PMAADDR13_PMAADDR_31_2_MASK) -#define CSR_PMAADDR13_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR13_PMAADDR_31_2_MASK) >> CSR_PMAADDR13_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR14_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR14_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR14_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR14_PMAADDR_31_2_SHIFT) & CSR_PMAADDR14_PMAADDR_31_2_MASK) -#define CSR_PMAADDR14_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR14_PMAADDR_31_2_MASK) >> CSR_PMAADDR14_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register array: PMAADDR */ -/* - * PMAADDR_31_2 (RW) - * - * same as PMAADDR0 - */ -#define CSR_PMAADDR15_PMAADDR_31_2_MASK (0xFFFFFFFCUL) -#define CSR_PMAADDR15_PMAADDR_31_2_SHIFT (2U) -#define CSR_PMAADDR15_PMAADDR_31_2_SET(x) (((uint32_t)(x) << CSR_PMAADDR15_PMAADDR_31_2_SHIFT) & CSR_PMAADDR15_PMAADDR_31_2_MASK) -#define CSR_PMAADDR15_PMAADDR_31_2_GET(x) (((uint32_t)(x) & CSR_PMAADDR15_PMAADDR_31_2_MASK) >> CSR_PMAADDR15_PMAADDR_31_2_SHIFT) - -/* Bitfield definition for register: CYCLE */ -/* - * CYCLE (RW) - * - * Cycle Counter - */ -#define CSR_CYCLE_CYCLE_MASK (0xFFFFFFFFUL) -#define CSR_CYCLE_CYCLE_SHIFT (0U) -#define CSR_CYCLE_CYCLE_SET(x) (((uint32_t)(x) << CSR_CYCLE_CYCLE_SHIFT) & CSR_CYCLE_CYCLE_MASK) -#define CSR_CYCLE_CYCLE_GET(x) (((uint32_t)(x) & CSR_CYCLE_CYCLE_MASK) >> CSR_CYCLE_CYCLE_SHIFT) - -/* Bitfield definition for register: CYCLEH */ -/* - * CYCLEH (RW) - * - * Cycle Counter Higher 32-bit - */ -#define CSR_CYCLEH_CYCLEH_MASK (0xFFFFFFFFUL) -#define CSR_CYCLEH_CYCLEH_SHIFT (0U) -#define CSR_CYCLEH_CYCLEH_SET(x) (((uint32_t)(x) << CSR_CYCLEH_CYCLEH_SHIFT) & CSR_CYCLEH_CYCLEH_MASK) -#define CSR_CYCLEH_CYCLEH_GET(x) (((uint32_t)(x) & CSR_CYCLEH_CYCLEH_MASK) >> CSR_CYCLEH_CYCLEH_SHIFT) - -/* Bitfield definition for register: MVENDORID */ -/* - * MVENDORID (RO) - * - * The manufacturer ID - */ -#define CSR_MVENDORID_MVENDORID_MASK (0xFFFFFFFFUL) -#define CSR_MVENDORID_MVENDORID_SHIFT (0U) -#define CSR_MVENDORID_MVENDORID_GET(x) (((uint32_t)(x) & CSR_MVENDORID_MVENDORID_MASK) >> CSR_MVENDORID_MVENDORID_SHIFT) - -/* Bitfield definition for register: MARCHID */ -/* - * CPU_ID (RO) - * - * CPU ID - */ -#define CSR_MARCHID_CPU_ID_MASK (0x7FFFFFFFUL) -#define CSR_MARCHID_CPU_ID_SHIFT (0U) -#define CSR_MARCHID_CPU_ID_GET(x) (((uint32_t)(x) & CSR_MARCHID_CPU_ID_MASK) >> CSR_MARCHID_CPU_ID_SHIFT) - -/* Bitfield definition for register: MIMPID */ -/* - * MAJOR (RO) - * - * Revision major - */ -#define CSR_MIMPID_MAJOR_MASK (0xFFFFFF00UL) -#define CSR_MIMPID_MAJOR_SHIFT (8U) -#define CSR_MIMPID_MAJOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MAJOR_MASK) >> CSR_MIMPID_MAJOR_SHIFT) - -/* - * MINOR (RO) - * - * Revision minor - */ -#define CSR_MIMPID_MINOR_MASK (0xF0U) -#define CSR_MIMPID_MINOR_SHIFT (4U) -#define CSR_MIMPID_MINOR_GET(x) (((uint32_t)(x) & CSR_MIMPID_MINOR_MASK) >> CSR_MIMPID_MINOR_SHIFT) - -/* - * EXTENSION (RO) - * - * Revision extension - */ -#define CSR_MIMPID_EXTENSION_MASK (0xFU) -#define CSR_MIMPID_EXTENSION_SHIFT (0U) -#define CSR_MIMPID_EXTENSION_GET(x) (((uint32_t)(x) & CSR_MIMPID_EXTENSION_MASK) >> CSR_MIMPID_EXTENSION_SHIFT) - -/* Bitfield definition for register: MHARTID */ -/* - * MHARTID (RO) - * - * Hart ID - */ -#define CSR_MHARTID_MHARTID_MASK (0xFFFFFFFFUL) -#define CSR_MHARTID_MHARTID_SHIFT (0U) -#define CSR_MHARTID_MHARTID_GET(x) (((uint32_t)(x) & CSR_MHARTID_MHARTID_MASK) >> CSR_MHARTID_MHARTID_SHIFT) - -/* NON-STANDARD CRS register bitfiled definitions */ - -/* Bitfield definition for register: SCOUNTEREN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM6_MASK (0x40U) -#define CSR_SCOUNTEREN_HPM6_SHIFT (6U) -#define CSR_SCOUNTEREN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM6_SHIFT) & CSR_SCOUNTEREN_HPM6_MASK) -#define CSR_SCOUNTEREN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM6_MASK) >> CSR_SCOUNTEREN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM5_MASK (0x20U) -#define CSR_SCOUNTEREN_HPM5_SHIFT (5U) -#define CSR_SCOUNTEREN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM5_SHIFT) & CSR_SCOUNTEREN_HPM5_MASK) -#define CSR_SCOUNTEREN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM5_MASK) >> CSR_SCOUNTEREN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM4_MASK (0x10U) -#define CSR_SCOUNTEREN_HPM4_SHIFT (4U) -#define CSR_SCOUNTEREN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM4_SHIFT) & CSR_SCOUNTEREN_HPM4_MASK) -#define CSR_SCOUNTEREN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM4_MASK) >> CSR_SCOUNTEREN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_HPM3_MASK (0x8U) -#define CSR_SCOUNTEREN_HPM3_SHIFT (3U) -#define CSR_SCOUNTEREN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_HPM3_SHIFT) & CSR_SCOUNTEREN_HPM3_MASK) -#define CSR_SCOUNTEREN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_HPM3_MASK) >> CSR_SCOUNTEREN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_IR_MASK (0x4U) -#define CSR_SCOUNTEREN_IR_SHIFT (2U) -#define CSR_SCOUNTEREN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_IR_SHIFT) & CSR_SCOUNTEREN_IR_MASK) -#define CSR_SCOUNTEREN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_IR_MASK) >> CSR_SCOUNTEREN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEREN_CY_MASK (0x1U) -#define CSR_SCOUNTEREN_CY_SHIFT (0U) -#define CSR_SCOUNTEREN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEREN_CY_SHIFT) & CSR_SCOUNTEREN_CY_MASK) -#define CSR_SCOUNTEREN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEREN_CY_MASK) >> CSR_SCOUNTEREN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_MCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_MCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM6_SHIFT) & CSR_MCOUNTINHIBIT_HPM6_MASK) -#define CSR_MCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM6_MASK) >> CSR_MCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_MCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_MCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM5_SHIFT) & CSR_MCOUNTINHIBIT_HPM5_MASK) -#define CSR_MCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM5_MASK) >> CSR_MCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_MCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_MCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM4_SHIFT) & CSR_MCOUNTINHIBIT_HPM4_MASK) -#define CSR_MCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM4_MASK) >> CSR_MCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_MCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_MCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_HPM3_SHIFT) & CSR_MCOUNTINHIBIT_HPM3_MASK) -#define CSR_MCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_HPM3_MASK) >> CSR_MCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_MCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_MCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_IR_SHIFT) & CSR_MCOUNTINHIBIT_IR_MASK) -#define CSR_MCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_IR_MASK) >> CSR_MCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_MCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_MCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_TM_SHIFT) & CSR_MCOUNTINHIBIT_TM_MASK) -#define CSR_MCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_TM_MASK) >> CSR_MCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description. - */ -#define CSR_MCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_MCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_MCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTINHIBIT_CY_SHIFT) & CSR_MCOUNTINHIBIT_CY_MASK) -#define CSR_MCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTINHIBIT_CY_MASK) >> CSR_MCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: MILMB */ -/* - * IBPA (RO) - * - * The base physical address of ILM. It has to be an integer multiple of the ILM size - */ -#define CSR_MILMB_IBPA_MASK (0xFFFFFC00UL) -#define CSR_MILMB_IBPA_SHIFT (10U) -#define CSR_MILMB_IBPA_GET(x) (((uint32_t)(x) & CSR_MILMB_IBPA_MASK) >> CSR_MILMB_IBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the ILM RAMs. When set, load/store to ILM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MILMB_RWECC_MASK (0x8U) -#define CSR_MILMB_RWECC_SHIFT (3U) -#define CSR_MILMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MILMB_RWECC_SHIFT) & CSR_MILMB_RWECC_MASK) -#define CSR_MILMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MILMB_RWECC_MASK) >> CSR_MILMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MILMB_ECCEN_MASK (0x6U) -#define CSR_MILMB_ECCEN_SHIFT (1U) -#define CSR_MILMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MILMB_ECCEN_SHIFT) & CSR_MILMB_ECCEN_MASK) -#define CSR_MILMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MILMB_ECCEN_MASK) >> CSR_MILMB_ECCEN_SHIFT) - -/* - * IEN (RO) - * - * ILM enable control: - * 0:ILM is disabled - * 1:ILM is enabled - */ -#define CSR_MILMB_IEN_MASK (0x1U) -#define CSR_MILMB_IEN_SHIFT (0U) -#define CSR_MILMB_IEN_GET(x) (((uint32_t)(x) & CSR_MILMB_IEN_MASK) >> CSR_MILMB_IEN_SHIFT) - -/* Bitfield definition for register: MDLMB */ -/* - * DBPA (RO) - * - * The base physical address of DLM. It has to be an integer multiple of the DLM size - */ -#define CSR_MDLMB_DBPA_MASK (0xFFFFFC00UL) -#define CSR_MDLMB_DBPA_SHIFT (10U) -#define CSR_MDLMB_DBPA_GET(x) (((uint32_t)(x) & CSR_MDLMB_DBPA_MASK) >> CSR_MDLMB_DBPA_SHIFT) - -/* - * RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the DLM RAMs. When set, load/store to DLM reads/writes ECC codes to the mecc_code register. This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MDLMB_RWECC_MASK (0x8U) -#define CSR_MDLMB_RWECC_SHIFT (3U) -#define CSR_MDLMB_RWECC_SET(x) (((uint32_t)(x) << CSR_MDLMB_RWECC_SHIFT) & CSR_MDLMB_RWECC_MASK) -#define CSR_MDLMB_RWECC_GET(x) (((uint32_t)(x) & CSR_MDLMB_RWECC_MASK) >> CSR_MDLMB_RWECC_SHIFT) - -/* - * ECCEN (RW) - * - * Parity/ECC enable control: - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MDLMB_ECCEN_MASK (0x6U) -#define CSR_MDLMB_ECCEN_SHIFT (1U) -#define CSR_MDLMB_ECCEN_SET(x) (((uint32_t)(x) << CSR_MDLMB_ECCEN_SHIFT) & CSR_MDLMB_ECCEN_MASK) -#define CSR_MDLMB_ECCEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_ECCEN_MASK) >> CSR_MDLMB_ECCEN_SHIFT) - -/* - * DEN (RO) - * - * DLM enable control: - * 0:DLM is disabled - * 1:DLM is enabled - */ -#define CSR_MDLMB_DEN_MASK (0x1U) -#define CSR_MDLMB_DEN_SHIFT (0U) -#define CSR_MDLMB_DEN_GET(x) (((uint32_t)(x) & CSR_MDLMB_DEN_MASK) >> CSR_MDLMB_DEN_SHIFT) - -/* Bitfield definition for register: MECC_CODE */ -/* - * INSN (RO) - * - * Indicates if the parity/ECC error is caused by instruction fetch or data access. - * 0:Data access - * 1:Instruction fetch - */ -#define CSR_MECC_CODE_INSN_MASK (0x400000UL) -#define CSR_MECC_CODE_INSN_SHIFT (22U) -#define CSR_MECC_CODE_INSN_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_INSN_MASK) >> CSR_MECC_CODE_INSN_SHIFT) - -/* - * RAMID (RO) - * - * The ID of RAM that caused parity/ECC errors. - * This bit is updated on parity/ECC error exceptions. - * 0–1:Reserved - * 2:Tag RAM of I-Cache - * 3:Data RAM of I-Cache - * 4:Tag RAM of D-Cache - * 5:Data RAM of D-Cache - * 6:Tag RAM of TLB - * 7:Data RAM of TLB - * 8:ILM - * 9:DLM - * 10–15:Reserved - */ -#define CSR_MECC_CODE_RAMID_MASK (0x3C0000UL) -#define CSR_MECC_CODE_RAMID_SHIFT (18U) -#define CSR_MECC_CODE_RAMID_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_RAMID_MASK) >> CSR_MECC_CODE_RAMID_SHIFT) - -/* - * P (RO) - * - * Precise error. This bit is updated on parity/ECC error exceptions. - * 0:Imprecise error - * 1:Precise error - */ -#define CSR_MECC_CODE_P_MASK (0x20000UL) -#define CSR_MECC_CODE_P_SHIFT (17U) -#define CSR_MECC_CODE_P_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_P_MASK) >> CSR_MECC_CODE_P_SHIFT) - -/* - * C (RO) - * - * Correctable error. This bit is updated on parity/ECC error exceptions. - * 0:Uncorrectable error - * 1:Correctable error - */ -#define CSR_MECC_CODE_C_MASK (0x10000UL) -#define CSR_MECC_CODE_C_SHIFT (16U) -#define CSR_MECC_CODE_C_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_C_MASK) >> CSR_MECC_CODE_C_SHIFT) - -/* - * CODE (RW) - * - * This field records the ECC value on ECC error exceptions. This field is also used to read/write the ECC codes when diagnostic access of ECC codes are enabled (milmb.RWECC or mdlmb.RWECC is 1). - */ -#define CSR_MECC_CODE_CODE_MASK (0x7FU) -#define CSR_MECC_CODE_CODE_SHIFT (0U) -#define CSR_MECC_CODE_CODE_SET(x) (((uint32_t)(x) << CSR_MECC_CODE_CODE_SHIFT) & CSR_MECC_CODE_CODE_MASK) -#define CSR_MECC_CODE_CODE_GET(x) (((uint32_t)(x) & CSR_MECC_CODE_CODE_MASK) >> CSR_MECC_CODE_CODE_SHIFT) - -/* Bitfield definition for register: MNVEC */ -/* - * MNVEC (RO) - * - * Base address of the NMI handler. Its value is the zero-extended value of the reset_vector. - */ -#define CSR_MNVEC_MNVEC_MASK (0xFFFFFFFFUL) -#define CSR_MNVEC_MNVEC_SHIFT (0U) -#define CSR_MNVEC_MNVEC_GET(x) (((uint32_t)(x) & CSR_MNVEC_MNVEC_MASK) >> CSR_MNVEC_MNVEC_SHIFT) - -/* Bitfield definition for register: MXSTATUS */ -/* - * PDME (RW) - * - * For saving previous DME state on entering a trap. This field is hardwired to 0 if data cache and data local memory are not supported. - */ -#define CSR_MXSTATUS_PDME_MASK (0x20U) -#define CSR_MXSTATUS_PDME_SHIFT (5U) -#define CSR_MXSTATUS_PDME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PDME_SHIFT) & CSR_MXSTATUS_PDME_MASK) -#define CSR_MXSTATUS_PDME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PDME_MASK) >> CSR_MXSTATUS_PDME_SHIFT) - -/* - * DME (RW) - * - * Data Machine Error flag. It indicates an exception occurred at the data cache or data local memory (DLM). Load/store accesses will bypass D-Cache when this bit is set. The exception handler should clear this bit after the machine error has been dealt with. - */ -#define CSR_MXSTATUS_DME_MASK (0x10U) -#define CSR_MXSTATUS_DME_SHIFT (4U) -#define CSR_MXSTATUS_DME_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_DME_SHIFT) & CSR_MXSTATUS_DME_MASK) -#define CSR_MXSTATUS_DME_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_DME_MASK) >> CSR_MXSTATUS_DME_SHIFT) - -/* - * PPFT_EN (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding - * is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MXSTATUS_PPFT_EN_MASK (0x2U) -#define CSR_MXSTATUS_PPFT_EN_SHIFT (1U) -#define CSR_MXSTATUS_PPFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PPFT_EN_SHIFT) & CSR_MXSTATUS_PPFT_EN_MASK) -#define CSR_MXSTATUS_PPFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PPFT_EN_MASK) >> CSR_MXSTATUS_PPFT_EN_SHIFT) - -/* - * PFT_EN (RW) - * - * Enable performance throttling. When throttling is enabled, the processor executes instructions at the performance level specified in mpft_ctl.T_LEVEL. On entering a trap: - * PPFT_EN <= PFT_EN; - * PFT_EN <= mpft_ctl.FAST_INT ? 0 :PFT_EN; - * On executing an MRET instruction: - * PFT_EN <= PPFT_EN; - * This field is hardwired to 0 if the PowerBrake feature is not supported. - */ -#define CSR_MXSTATUS_PFT_EN_MASK (0x1U) -#define CSR_MXSTATUS_PFT_EN_SHIFT (0U) -#define CSR_MXSTATUS_PFT_EN_SET(x) (((uint32_t)(x) << CSR_MXSTATUS_PFT_EN_SHIFT) & CSR_MXSTATUS_PFT_EN_MASK) -#define CSR_MXSTATUS_PFT_EN_GET(x) (((uint32_t)(x) & CSR_MXSTATUS_PFT_EN_MASK) >> CSR_MXSTATUS_PFT_EN_SHIFT) - -/* Bitfield definition for register: MPFT_CTL */ -/* - * FAST_INT (RW) - * - * Fast interrupt response. If this field is set, mxstatus.PFT_EN will be automatically cleared when the processor enters an interrupt handler. - */ -#define CSR_MPFT_CTL_FAST_INT_MASK (0x100U) -#define CSR_MPFT_CTL_FAST_INT_SHIFT (8U) -#define CSR_MPFT_CTL_FAST_INT_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_FAST_INT_SHIFT) & CSR_MPFT_CTL_FAST_INT_MASK) -#define CSR_MPFT_CTL_FAST_INT_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_FAST_INT_MASK) >> CSR_MPFT_CTL_FAST_INT_SHIFT) - -/* - * T_LEVEL (RW) - * - * Throttling Level. The processor has the highest performance at throttling level 0 and the lowest - * performance at throttling level 15. - * 0:Level 0 (the highest performance) - * 1-14:Level 1-14 - * 15:Level 15 (the lowest performance) - */ -#define CSR_MPFT_CTL_T_LEVEL_MASK (0xF0U) -#define CSR_MPFT_CTL_T_LEVEL_SHIFT (4U) -#define CSR_MPFT_CTL_T_LEVEL_SET(x) (((uint32_t)(x) << CSR_MPFT_CTL_T_LEVEL_SHIFT) & CSR_MPFT_CTL_T_LEVEL_MASK) -#define CSR_MPFT_CTL_T_LEVEL_GET(x) (((uint32_t)(x) & CSR_MPFT_CTL_T_LEVEL_MASK) >> CSR_MPFT_CTL_T_LEVEL_SHIFT) - -/* Bitfield definition for register: MHSP_CTL */ -/* - * M (RW) - * - * Enables the SP protection and recording mechanism in Machine mode - * 0:The mechanism is disabled in Machine mode. - * 1: The mechanism is enabled in Machine mode. - */ -#define CSR_MHSP_CTL_M_MASK (0x20U) -#define CSR_MHSP_CTL_M_SHIFT (5U) -#define CSR_MHSP_CTL_M_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_M_SHIFT) & CSR_MHSP_CTL_M_MASK) -#define CSR_MHSP_CTL_M_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_M_MASK) >> CSR_MHSP_CTL_M_SHIFT) - -/* - * S (RW) - * - * Enables the SP protection and recording mechanism in Supervisor mode - * 0:The mechanism is disabled in Supervisor mode - * 1:The mechanism is enabled in Supervisor mode - */ -#define CSR_MHSP_CTL_S_MASK (0x10U) -#define CSR_MHSP_CTL_S_SHIFT (4U) -#define CSR_MHSP_CTL_S_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_S_SHIFT) & CSR_MHSP_CTL_S_MASK) -#define CSR_MHSP_CTL_S_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_S_MASK) >> CSR_MHSP_CTL_S_SHIFT) - -/* - * U (RW) - * - * Enables the SP protection and recording mechanism in User mode - * 0:The mechanism is disabled in User mode - * 1:The mechanism is enabled in User mode. - */ -#define CSR_MHSP_CTL_U_MASK (0x8U) -#define CSR_MHSP_CTL_U_SHIFT (3U) -#define CSR_MHSP_CTL_U_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_U_SHIFT) & CSR_MHSP_CTL_U_MASK) -#define CSR_MHSP_CTL_U_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_U_MASK) >> CSR_MHSP_CTL_U_SHIFT) - -/* - * SCHM (RW) - * - * Selects the operating scheme of the stack protection and recording mechanism - * 0:Stack overflow/underflow detection - * 1:Top-of-stack recording - */ -#define CSR_MHSP_CTL_SCHM_MASK (0x4U) -#define CSR_MHSP_CTL_SCHM_SHIFT (2U) -#define CSR_MHSP_CTL_SCHM_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_SCHM_SHIFT) & CSR_MHSP_CTL_SCHM_MASK) -#define CSR_MHSP_CTL_SCHM_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_SCHM_MASK) >> CSR_MHSP_CTL_SCHM_SHIFT) - -/* - * UDF_EN (RW) - * - * Enable bit for the stack underflow protection mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack underflow protection is disabled - * 1:The stack underflow protection is enabled. - */ -#define CSR_MHSP_CTL_UDF_EN_MASK (0x2U) -#define CSR_MHSP_CTL_UDF_EN_SHIFT (1U) -#define CSR_MHSP_CTL_UDF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_UDF_EN_SHIFT) & CSR_MHSP_CTL_UDF_EN_MASK) -#define CSR_MHSP_CTL_UDF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_UDF_EN_MASK) >> CSR_MHSP_CTL_UDF_EN_SHIFT) - -/* - * OVF_EN (RW) - * - * Enable bit for the stack overflow protection and recording mechanism. This bit will be cleared to 0 automatically by hardware when a stack protection (overflow or underflow) exception is taken. - * 0:The stack overflow protection and recording mechanism are disabled. - * 1:The stack overflow protection and recording mechanism are enabled. - */ -#define CSR_MHSP_CTL_OVF_EN_MASK (0x1U) -#define CSR_MHSP_CTL_OVF_EN_SHIFT (0U) -#define CSR_MHSP_CTL_OVF_EN_SET(x) (((uint32_t)(x) << CSR_MHSP_CTL_OVF_EN_SHIFT) & CSR_MHSP_CTL_OVF_EN_MASK) -#define CSR_MHSP_CTL_OVF_EN_GET(x) (((uint32_t)(x) & CSR_MHSP_CTL_OVF_EN_MASK) >> CSR_MHSP_CTL_OVF_EN_SHIFT) - -/* Bitfield definition for register: MSP_BOUND */ -/* - * MSP_BOUND (RW) - * - * Machine SP Bound - */ -#define CSR_MSP_BOUND_MSP_BOUND_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BOUND_MSP_BOUND_SHIFT (0U) -#define CSR_MSP_BOUND_MSP_BOUND_SET(x) (((uint32_t)(x) << CSR_MSP_BOUND_MSP_BOUND_SHIFT) & CSR_MSP_BOUND_MSP_BOUND_MASK) -#define CSR_MSP_BOUND_MSP_BOUND_GET(x) (((uint32_t)(x) & CSR_MSP_BOUND_MSP_BOUND_MASK) >> CSR_MSP_BOUND_MSP_BOUND_SHIFT) - -/* Bitfield definition for register: MSP_BASE */ -/* - * SP_BASE (RW) - * - * Machine SP base - */ -#define CSR_MSP_BASE_SP_BASE_MASK (0xFFFFFFFFUL) -#define CSR_MSP_BASE_SP_BASE_SHIFT (0U) -#define CSR_MSP_BASE_SP_BASE_SET(x) (((uint32_t)(x) << CSR_MSP_BASE_SP_BASE_SHIFT) & CSR_MSP_BASE_SP_BASE_MASK) -#define CSR_MSP_BASE_SP_BASE_GET(x) (((uint32_t)(x) & CSR_MSP_BASE_SP_BASE_MASK) >> CSR_MSP_BASE_SP_BASE_SHIFT) - -/* Bitfield definition for register: MDCAUSE */ -/* - * PM (RW) - * - * When mcause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0: User mode - * 1: Supervisor mode - * 2: Reserved - * 3: Machine mode - */ -#define CSR_MDCAUSE_PM_MASK (0x60U) -#define CSR_MDCAUSE_PM_SHIFT (5U) -#define CSR_MDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_PM_SHIFT) & CSR_MDCAUSE_PM_MASK) -#define CSR_MDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_PM_MASK) >> CSR_MDCAUSE_PM_SHIFT) - -/* - * MDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the mcause register. - * The value of MDCAUSE for precise exception: - * When mcause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When mcause == 2 (Illegal instruction): - * 0:Please parse the mtval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When mcause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When mcause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of MDCAUSE for imprecise exception: - * When mcause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When mcause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_MDCAUSE_MDCAUSE_MASK (0x7U) -#define CSR_MDCAUSE_MDCAUSE_SHIFT (0U) -#define CSR_MDCAUSE_MDCAUSE_SET(x) (((uint32_t)(x) << CSR_MDCAUSE_MDCAUSE_SHIFT) & CSR_MDCAUSE_MDCAUSE_MASK) -#define CSR_MDCAUSE_MDCAUSE_GET(x) (((uint32_t)(x) & CSR_MDCAUSE_MDCAUSE_MASK) >> CSR_MDCAUSE_MDCAUSE_SHIFT) - -/* Bitfield definition for register: MCACHE_CTL */ -/* - * DC_WAROUND (RW) - * - * Cache Write-Around threshold - * 0:Disables streaming. All cacheable write misses allocate a cache line according to PMA settings. - * 1:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 4 cache lines. - * 2:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 64 cache lines. - * 3:Stop allocating D-Cache entries regardless of PMA settings after consecutive stores to 128 cache lines. - */ -#define CSR_MCACHE_CTL_DC_WAROUND_MASK (0x6000U) -#define CSR_MCACHE_CTL_DC_WAROUND_SHIFT (13U) -#define CSR_MCACHE_CTL_DC_WAROUND_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_WAROUND_SHIFT) & CSR_MCACHE_CTL_DC_WAROUND_MASK) -#define CSR_MCACHE_CTL_DC_WAROUND_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_WAROUND_MASK) >> CSR_MCACHE_CTL_DC_WAROUND_SHIFT) - -/* - * DC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1000U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT (12U) -#define CSR_MCACHE_CTL_DC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_DC_FIRST_WORD_SHIFT) - -/* - * IC_FIRST_WORD (RO) - * - * Cache miss allocation filling policy - * 0:Cache line data is returned critical (double) word first - * 1:Cache line data is returned the lowest address (double) word first - */ -#define CSR_MCACHE_CTL_IC_FIRST_WORD_MASK (0x800U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT (11U) -#define CSR_MCACHE_CTL_IC_FIRST_WORD_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_FIRST_WORD_MASK) >> CSR_MCACHE_CTL_IC_FIRST_WORD_SHIFT) - -/* - * DPREF_EN (RW) - * - * This bit controls hardware prefetch for load/store accesses to cacheable memory regions when D-Cache size is not 0 - * 0:Disable hardware prefetch on load/store memory accesses - * 1:Enable hardware prefetch on load/store memory accesses - */ -#define CSR_MCACHE_CTL_DPREF_EN_MASK (0x400U) -#define CSR_MCACHE_CTL_DPREF_EN_SHIFT (10U) -#define CSR_MCACHE_CTL_DPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DPREF_EN_SHIFT) & CSR_MCACHE_CTL_DPREF_EN_MASK) -#define CSR_MCACHE_CTL_DPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DPREF_EN_MASK) >> CSR_MCACHE_CTL_DPREF_EN_SHIFT) - -/* - * IPREF_EN (RW) - * - * This bit controls hardware prefetch for instruction fetches to cacheable memory regions when Cache size is not 0 - * 0:Disable hardware prefetch on instruction fetches - * 1:Enable hardware prefetch on instruction fetches - */ -#define CSR_MCACHE_CTL_IPREF_EN_MASK (0x200U) -#define CSR_MCACHE_CTL_IPREF_EN_SHIFT (9U) -#define CSR_MCACHE_CTL_IPREF_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IPREF_EN_SHIFT) & CSR_MCACHE_CTL_IPREF_EN_MASK) -#define CSR_MCACHE_CTL_IPREF_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IPREF_EN_MASK) >> CSR_MCACHE_CTL_IPREF_EN_SHIFT) - -/* - * CCTL_SUEN (RW) - * - * Enable bit for Superuser-mode and User-mode software to access ucctlbeginaddr and ucctlcommand CSRs - * 0:Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1:Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define CSR_MCACHE_CTL_CCTL_SUEN_MASK (0x100U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SHIFT (8U) -#define CSR_MCACHE_CTL_CCTL_SUEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) -#define CSR_MCACHE_CTL_CCTL_SUEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_CCTL_SUEN_MASK) >> CSR_MCACHE_CTL_CCTL_SUEN_SHIFT) - -/* - * DC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is set to enable CCTL operations to access the ECC codes. This bit can be set for injecting ECC errors to test the ECC handler - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_DC_RWECC_MASK (0x80U) -#define CSR_MCACHE_CTL_DC_RWECC_SHIFT (7U) -#define CSR_MCACHE_CTL_DC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_RWECC_SHIFT) & CSR_MCACHE_CTL_DC_RWECC_MASK) -#define CSR_MCACHE_CTL_DC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_RWECC_MASK) >> CSR_MCACHE_CTL_DC_RWECC_SHIFT) - -/* - * IC_RWECC (RW) - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. It is set to enable CCTL operations to access the ECC codes . This bit can be set for injecting ECC errors to test the ECC handler. - * 0:Disable diagnostic accesses of ECC codes - * 1:Enable diagnostic accesses of ECC codes - */ -#define CSR_MCACHE_CTL_IC_RWECC_MASK (0x40U) -#define CSR_MCACHE_CTL_IC_RWECC_SHIFT (6U) -#define CSR_MCACHE_CTL_IC_RWECC_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_RWECC_SHIFT) & CSR_MCACHE_CTL_IC_RWECC_MASK) -#define CSR_MCACHE_CTL_IC_RWECC_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_RWECC_MASK) >> CSR_MCACHE_CTL_IC_RWECC_SHIFT) - -/* - * DC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * data cache. - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_DC_ECCEN_MASK (0x30U) -#define CSR_MCACHE_CTL_DC_ECCEN_SHIFT (4U) -#define CSR_MCACHE_CTL_DC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_ECCEN_SHIFT) & CSR_MCACHE_CTL_DC_ECCEN_MASK) -#define CSR_MCACHE_CTL_DC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_ECCEN_MASK) >> CSR_MCACHE_CTL_DC_ECCEN_SHIFT) - -/* - * IC_ECCEN (RW) - * - * Parity/ECC error checking enable control for the - * instruction cache - * 0:Disable parity/ECC - * 1:Reserved - * 2:Generate exceptions only on uncorrectable parity/ECC errors - * 3:Generate exceptions on any type of parity/ECC errors - */ -#define CSR_MCACHE_CTL_IC_ECCEN_MASK (0xCU) -#define CSR_MCACHE_CTL_IC_ECCEN_SHIFT (2U) -#define CSR_MCACHE_CTL_IC_ECCEN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_ECCEN_SHIFT) & CSR_MCACHE_CTL_IC_ECCEN_MASK) -#define CSR_MCACHE_CTL_IC_ECCEN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_ECCEN_MASK) >> CSR_MCACHE_CTL_IC_ECCEN_SHIFT) - -/* - * DC_EN (RW) - * - * Controls if the data cache is enabled or not. - * 0:D-Cache is disabled - * 1:D-Cache is enabled - */ -#define CSR_MCACHE_CTL_DC_EN_MASK (0x2U) -#define CSR_MCACHE_CTL_DC_EN_SHIFT (1U) -#define CSR_MCACHE_CTL_DC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_DC_EN_SHIFT) & CSR_MCACHE_CTL_DC_EN_MASK) -#define CSR_MCACHE_CTL_DC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_DC_EN_MASK) >> CSR_MCACHE_CTL_DC_EN_SHIFT) - -/* - * IC_EN (RW) - * - * Controls if the instruction cache is enabled or not. - * 0:I-Cache is disabled - * 1:I-Cache is enabled - */ -#define CSR_MCACHE_CTL_IC_EN_MASK (0x1U) -#define CSR_MCACHE_CTL_IC_EN_SHIFT (0U) -#define CSR_MCACHE_CTL_IC_EN_SET(x) (((uint32_t)(x) << CSR_MCACHE_CTL_IC_EN_SHIFT) & CSR_MCACHE_CTL_IC_EN_MASK) -#define CSR_MCACHE_CTL_IC_EN_GET(x) (((uint32_t)(x) & CSR_MCACHE_CTL_IC_EN_MASK) >> CSR_MCACHE_CTL_IC_EN_SHIFT) - -/* Bitfield definition for register: MCCTLBEGINADDR */ -/* - * VA (RW) - * - * This register holds the address information required by CCTL operations - */ -#define CSR_MCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_MCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_MCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLBEGINADDR_VA_SHIFT) & CSR_MCCTLBEGINADDR_VA_MASK) -#define CSR_MCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLBEGINADDR_VA_MASK) >> CSR_MCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: MCCTLCOMMAND */ -/* - * VA (RW) - * - * See CCTL Command Definition Table - */ -#define CSR_MCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_MCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_MCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLCOMMAND_VA_SHIFT) & CSR_MCCTLCOMMAND_VA_MASK) -#define CSR_MCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLCOMMAND_VA_MASK) >> CSR_MCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: MCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_MCCTLDATA_VA_MASK (0x1FU) -#define CSR_MCCTLDATA_VA_SHIFT (0U) -#define CSR_MCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_MCCTLDATA_VA_SHIFT) & CSR_MCCTLDATA_VA_MASK) -#define CSR_MCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_MCCTLDATA_VA_MASK) >> CSR_MCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: MCOUNTERWEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERWEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERWEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM6_SHIFT) & CSR_MCOUNTERWEN_HPM6_MASK) -#define CSR_MCOUNTERWEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM6_MASK) >> CSR_MCOUNTERWEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERWEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERWEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM5_SHIFT) & CSR_MCOUNTERWEN_HPM5_MASK) -#define CSR_MCOUNTERWEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM5_MASK) >> CSR_MCOUNTERWEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERWEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERWEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM4_SHIFT) & CSR_MCOUNTERWEN_HPM4_MASK) -#define CSR_MCOUNTERWEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM4_MASK) >> CSR_MCOUNTERWEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERWEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERWEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_HPM3_SHIFT) & CSR_MCOUNTERWEN_HPM3_MASK) -#define CSR_MCOUNTERWEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_HPM3_MASK) >> CSR_MCOUNTERWEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_IR_MASK (0x4U) -#define CSR_MCOUNTERWEN_IR_SHIFT (2U) -#define CSR_MCOUNTERWEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_IR_SHIFT) & CSR_MCOUNTERWEN_IR_MASK) -#define CSR_MCOUNTERWEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_IR_MASK) >> CSR_MCOUNTERWEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERWEN_CY_MASK (0x1U) -#define CSR_MCOUNTERWEN_CY_SHIFT (0U) -#define CSR_MCOUNTERWEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERWEN_CY_SHIFT) & CSR_MCOUNTERWEN_CY_MASK) -#define CSR_MCOUNTERWEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERWEN_CY_MASK) >> CSR_MCOUNTERWEN_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_MCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_MCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM6_SHIFT) & CSR_MCOUNTERINTEN_HPM6_MASK) -#define CSR_MCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM6_MASK) >> CSR_MCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_MCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_MCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM5_SHIFT) & CSR_MCOUNTERINTEN_HPM5_MASK) -#define CSR_MCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM5_MASK) >> CSR_MCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_MCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_MCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM4_SHIFT) & CSR_MCOUNTERINTEN_HPM4_MASK) -#define CSR_MCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM4_MASK) >> CSR_MCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_MCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_MCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_HPM3_SHIFT) & CSR_MCOUNTERINTEN_HPM3_MASK) -#define CSR_MCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_HPM3_MASK) >> CSR_MCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_MCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_MCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_IR_SHIFT) & CSR_MCOUNTERINTEN_IR_MASK) -#define CSR_MCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_IR_MASK) >> CSR_MCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_MCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_MCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERINTEN_CY_SHIFT) & CSR_MCOUNTERINTEN_CY_MASK) -#define CSR_MCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERINTEN_CY_MASK) >> CSR_MCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: MMISC_CTL */ -/* - * NBLD_EN (RW) - * - * This field controls the blocking behavior of load instructions. When this bit is clear, load instructions accessing non-device regions are blocking. When this bit is set, load instructions will not be blocking on such occasions and bus errors will no longer be reported synchronously. - * 0:Load to memory regions are blocking. - * 1:Load to memory regions are non-blocking. - */ -#define CSR_MMISC_CTL_NBLD_EN_MASK (0x100U) -#define CSR_MMISC_CTL_NBLD_EN_SHIFT (8U) -#define CSR_MMISC_CTL_NBLD_EN_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_NBLD_EN_SHIFT) & CSR_MMISC_CTL_NBLD_EN_MASK) -#define CSR_MMISC_CTL_NBLD_EN_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_NBLD_EN_MASK) >> CSR_MMISC_CTL_NBLD_EN_SHIFT) - -/* - * MSA_UNA (RW) - * - * This field controls whether the load/store instructions can access misaligned memory locations without generating Address Misaligned exceptions. - * Supported instructions: LW/LH/LHU/SW/SH - * 0:Misaligned accesses generate Address Misaligned exceptions. - * 1:Misaligned accesses generate Address Misaligned exceptions. - */ -#define CSR_MMISC_CTL_MSA_UNA_MASK (0x40U) -#define CSR_MMISC_CTL_MSA_UNA_SHIFT (6U) -#define CSR_MMISC_CTL_MSA_UNA_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_MSA_UNA_SHIFT) & CSR_MMISC_CTL_MSA_UNA_MASK) -#define CSR_MMISC_CTL_MSA_UNA_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_MSA_UNA_MASK) >> CSR_MMISC_CTL_MSA_UNA_SHIFT) - -/* - * BRPE (RW) - * - * Branch prediction enable bit. This bit controls all branch prediction structures. - * 0:Disabled - * 1:Enabled - * This bit is hardwired to 0 if branch prediction structure is not supported. - */ -#define CSR_MMISC_CTL_BRPE_MASK (0x8U) -#define CSR_MMISC_CTL_BRPE_SHIFT (3U) -#define CSR_MMISC_CTL_BRPE_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_BRPE_SHIFT) & CSR_MMISC_CTL_BRPE_MASK) -#define CSR_MMISC_CTL_BRPE_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_BRPE_MASK) >> CSR_MMISC_CTL_BRPE_SHIFT) - -/* - * RVCOMPM (RW) - * - * RISC-V compatibility mode enable bit. If the compatibility mode is turned on, all specific instructions become reserved instructions - * 0:Disabled - * 1:Enabled - */ -#define CSR_MMISC_CTL_RVCOMPM_MASK (0x4U) -#define CSR_MMISC_CTL_RVCOMPM_SHIFT (2U) -#define CSR_MMISC_CTL_RVCOMPM_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_RVCOMPM_SHIFT) & CSR_MMISC_CTL_RVCOMPM_MASK) -#define CSR_MMISC_CTL_RVCOMPM_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_RVCOMPM_MASK) >> CSR_MMISC_CTL_RVCOMPM_SHIFT) - -/* - * VEC_PLIC (RW) - * - * Selects the operation mode of PLIC: - * 0:Regular mode - * 1:Vector mode - * Please note that both this bit and the vector mode enable bit (VECTORED) of the Feature Enable Register in NCEPLIC100 should be turned on for the vectored interrupt support to work correctly. This bit is hardwired to 0 if the vectored PLIC feature is not supported. - */ -#define CSR_MMISC_CTL_VEC_PLIC_MASK (0x2U) -#define CSR_MMISC_CTL_VEC_PLIC_SHIFT (1U) -#define CSR_MMISC_CTL_VEC_PLIC_SET(x) (((uint32_t)(x) << CSR_MMISC_CTL_VEC_PLIC_SHIFT) & CSR_MMISC_CTL_VEC_PLIC_MASK) -#define CSR_MMISC_CTL_VEC_PLIC_GET(x) (((uint32_t)(x) & CSR_MMISC_CTL_VEC_PLIC_MASK) >> CSR_MMISC_CTL_VEC_PLIC_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM6_SHIFT) & CSR_MCOUNTERMASK_M_HPM6_MASK) -#define CSR_MCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM6_MASK) >> CSR_MCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM5_SHIFT) & CSR_MCOUNTERMASK_M_HPM5_MASK) -#define CSR_MCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM5_MASK) >> CSR_MCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM4_SHIFT) & CSR_MCOUNTERMASK_M_HPM4_MASK) -#define CSR_MCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM4_MASK) >> CSR_MCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_HPM3_SHIFT) & CSR_MCOUNTERMASK_M_HPM3_MASK) -#define CSR_MCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_HPM3_MASK) >> CSR_MCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_IR_SHIFT) & CSR_MCOUNTERMASK_M_IR_MASK) -#define CSR_MCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_IR_MASK) >> CSR_MCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_M_CY_SHIFT) & CSR_MCOUNTERMASK_M_CY_MASK) -#define CSR_MCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_M_CY_MASK) >> CSR_MCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM6_SHIFT) & CSR_MCOUNTERMASK_S_HPM6_MASK) -#define CSR_MCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM6_MASK) >> CSR_MCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM5_SHIFT) & CSR_MCOUNTERMASK_S_HPM5_MASK) -#define CSR_MCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM5_MASK) >> CSR_MCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM4_SHIFT) & CSR_MCOUNTERMASK_S_HPM4_MASK) -#define CSR_MCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM4_MASK) >> CSR_MCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_HPM3_SHIFT) & CSR_MCOUNTERMASK_S_HPM3_MASK) -#define CSR_MCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_HPM3_MASK) >> CSR_MCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_IR_SHIFT) & CSR_MCOUNTERMASK_S_IR_MASK) -#define CSR_MCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_IR_MASK) >> CSR_MCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_S_CY_SHIFT) & CSR_MCOUNTERMASK_S_CY_MASK) -#define CSR_MCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_S_CY_MASK) >> CSR_MCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_MCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_MCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM6_SHIFT) & CSR_MCOUNTERMASK_U_HPM6_MASK) -#define CSR_MCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM6_MASK) >> CSR_MCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_MCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_MCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM5_SHIFT) & CSR_MCOUNTERMASK_U_HPM5_MASK) -#define CSR_MCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM5_MASK) >> CSR_MCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_MCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_MCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM4_SHIFT) & CSR_MCOUNTERMASK_U_HPM4_MASK) -#define CSR_MCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM4_MASK) >> CSR_MCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_MCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_MCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_HPM3_SHIFT) & CSR_MCOUNTERMASK_U_HPM3_MASK) -#define CSR_MCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_HPM3_MASK) >> CSR_MCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_MCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_MCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_IR_SHIFT) & CSR_MCOUNTERMASK_U_IR_MASK) -#define CSR_MCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_IR_MASK) >> CSR_MCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_MCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_MCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTERMASK_U_CY_SHIFT) & CSR_MCOUNTERMASK_U_CY_MASK) -#define CSR_MCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTERMASK_U_CY_MASK) >> CSR_MCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: MCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_MCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_MCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM6_SHIFT) & CSR_MCOUNTEROVF_HPM6_MASK) -#define CSR_MCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM6_MASK) >> CSR_MCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_MCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_MCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM5_SHIFT) & CSR_MCOUNTEROVF_HPM5_MASK) -#define CSR_MCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM5_MASK) >> CSR_MCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_MCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_MCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM4_SHIFT) & CSR_MCOUNTEROVF_HPM4_MASK) -#define CSR_MCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM4_MASK) >> CSR_MCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_MCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_MCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_HPM3_SHIFT) & CSR_MCOUNTEROVF_HPM3_MASK) -#define CSR_MCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_HPM3_MASK) >> CSR_MCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_IR_MASK (0x4U) -#define CSR_MCOUNTEROVF_IR_SHIFT (2U) -#define CSR_MCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_IR_SHIFT) & CSR_MCOUNTEROVF_IR_MASK) -#define CSR_MCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_IR_MASK) >> CSR_MCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_MCOUNTEROVF_CY_MASK (0x1U) -#define CSR_MCOUNTEROVF_CY_SHIFT (0U) -#define CSR_MCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_MCOUNTEROVF_CY_SHIFT) & CSR_MCOUNTEROVF_CY_MASK) -#define CSR_MCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_MCOUNTEROVF_CY_MASK) >> CSR_MCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: MSLIDELEG */ -/* - * PMOVI (RW) - * - * Delegate S-mode performance monitor overflow local interrupt to S-mode. - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_PMOVI_MASK (0x40000UL) -#define CSR_MSLIDELEG_PMOVI_SHIFT (18U) -#define CSR_MSLIDELEG_PMOVI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_PMOVI_SHIFT) & CSR_MSLIDELEG_PMOVI_MASK) -#define CSR_MSLIDELEG_PMOVI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_PMOVI_MASK) >> CSR_MSLIDELEG_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Delegate S-mode bus read/write transaction error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_BWEI_MASK (0x20000UL) -#define CSR_MSLIDELEG_BWEI_SHIFT (17U) -#define CSR_MSLIDELEG_BWEI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_BWEI_SHIFT) & CSR_MSLIDELEG_BWEI_MASK) -#define CSR_MSLIDELEG_BWEI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_BWEI_MASK) >> CSR_MSLIDELEG_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Delegate S-mode slave-port ECC error local interrupt to S-mode - * 0:Do not delegate to S-mode. - * 1:Delegate to S-mode. - */ -#define CSR_MSLIDELEG_IMECCI_MASK (0x10000UL) -#define CSR_MSLIDELEG_IMECCI_SHIFT (16U) -#define CSR_MSLIDELEG_IMECCI_SET(x) (((uint32_t)(x) << CSR_MSLIDELEG_IMECCI_SHIFT) & CSR_MSLIDELEG_IMECCI_MASK) -#define CSR_MSLIDELEG_IMECCI_GET(x) (((uint32_t)(x) & CSR_MSLIDELEG_IMECCI_MASK) >> CSR_MSLIDELEG_IMECCI_SHIFT) - -/* Bitfield definition for register: MCLK_CTL */ -/* - * FUNIT (RW) - * - * Level 2 clock gating enable for function units listed in the following table. - * 16:integer arithmetic unit - * 17:integer permutation unit - * 18:integer mask unit - * 19:integer division unit - * 20:integer multiply and add unit - * 21:floating-point multiply and add - * unit - * 22:floating-point miscellaneous unit - * 23:floating-point division unit - * 24:load/store unit - * 31:25:Reserved - */ -#define CSR_MCLK_CTL_FUNIT_MASK (0xFFFF0000UL) -#define CSR_MCLK_CTL_FUNIT_SHIFT (16U) -#define CSR_MCLK_CTL_FUNIT_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FUNIT_SHIFT) & CSR_MCLK_CTL_FUNIT_MASK) -#define CSR_MCLK_CTL_FUNIT_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FUNIT_MASK) >> CSR_MCLK_CTL_FUNIT_SHIFT) - -/* - * VI (RW) - * - * Level 1 clock gating enable for the vector/floating-point issue queues. - */ -#define CSR_MCLK_CTL_VI_MASK (0x8000U) -#define CSR_MCLK_CTL_VI_SHIFT (15U) -#define CSR_MCLK_CTL_VI_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VI_SHIFT) & CSR_MCLK_CTL_VI_MASK) -#define CSR_MCLK_CTL_VI_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VI_MASK) >> CSR_MCLK_CTL_VI_SHIFT) - -/* - * VR (RW) - * - * Level 1 clock gating enable for the vector/floating-point register file. - */ -#define CSR_MCLK_CTL_VR_MASK (0x4000U) -#define CSR_MCLK_CTL_VR_SHIFT (14U) -#define CSR_MCLK_CTL_VR_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_VR_SHIFT) & CSR_MCLK_CTL_VR_MASK) -#define CSR_MCLK_CTL_VR_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_VR_MASK) >> CSR_MCLK_CTL_VR_SHIFT) - -/* - * AQ (RW) - * - * Level 1 clock gating enable for ACE load/store queues. - */ -#define CSR_MCLK_CTL_AQ_MASK (0x2000U) -#define CSR_MCLK_CTL_AQ_SHIFT (13U) -#define CSR_MCLK_CTL_AQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_AQ_SHIFT) & CSR_MCLK_CTL_AQ_MASK) -#define CSR_MCLK_CTL_AQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_AQ_MASK) >> CSR_MCLK_CTL_AQ_SHIFT) - -/* - * DQ (RW) - * - * Level 1 clock gating enable for data cache load/store queues. - */ -#define CSR_MCLK_CTL_DQ_MASK (0x1000U) -#define CSR_MCLK_CTL_DQ_SHIFT (12U) -#define CSR_MCLK_CTL_DQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_DQ_SHIFT) & CSR_MCLK_CTL_DQ_MASK) -#define CSR_MCLK_CTL_DQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_DQ_MASK) >> CSR_MCLK_CTL_DQ_SHIFT) - -/* - * UQ (RW) - * - * Level 1 clock gating enable for uncached queues - */ -#define CSR_MCLK_CTL_UQ_MASK (0x800U) -#define CSR_MCLK_CTL_UQ_SHIFT (11U) -#define CSR_MCLK_CTL_UQ_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_UQ_SHIFT) & CSR_MCLK_CTL_UQ_MASK) -#define CSR_MCLK_CTL_UQ_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_UQ_MASK) >> CSR_MCLK_CTL_UQ_SHIFT) - -/* - * FP (RW) - * - * Level 1 clock gating enable for scalar floating point issue unit and queues. - */ -#define CSR_MCLK_CTL_FP_MASK (0x400U) -#define CSR_MCLK_CTL_FP_SHIFT (10U) -#define CSR_MCLK_CTL_FP_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_FP_SHIFT) & CSR_MCLK_CTL_FP_MASK) -#define CSR_MCLK_CTL_FP_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_FP_MASK) >> CSR_MCLK_CTL_FP_SHIFT) - -/* - * CLKGATE (RW) - * - * One-hot clock gating levels. - * 0:Level 1 clock gating in module level - * 1:Level 2 clock gating in unit level - * 2:Level 3 clock gating in VPU level - * 7:3:Reserved - */ -#define CSR_MCLK_CTL_CLKGATE_MASK (0xFFU) -#define CSR_MCLK_CTL_CLKGATE_SHIFT (0U) -#define CSR_MCLK_CTL_CLKGATE_SET(x) (((uint32_t)(x) << CSR_MCLK_CTL_CLKGATE_SHIFT) & CSR_MCLK_CTL_CLKGATE_MASK) -#define CSR_MCLK_CTL_CLKGATE_GET(x) (((uint32_t)(x) & CSR_MCLK_CTL_CLKGATE_MASK) >> CSR_MCLK_CTL_CLKGATE_SHIFT) - -/* Bitfield definition for register: DEXC2DBG */ -/* - * PMOV (RW) - * - * Indicates whether performance counter overflow interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_PMOV_MASK (0x80000UL) -#define CSR_DEXC2DBG_PMOV_SHIFT (19U) -#define CSR_DEXC2DBG_PMOV_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_PMOV_SHIFT) & CSR_DEXC2DBG_PMOV_MASK) -#define CSR_DEXC2DBG_PMOV_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_PMOV_MASK) >> CSR_DEXC2DBG_PMOV_SHIFT) - -/* - * SPF (RW) - * - * Indicates whether store page fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SPF_MASK (0x40000UL) -#define CSR_DEXC2DBG_SPF_SHIFT (18U) -#define CSR_DEXC2DBG_SPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SPF_SHIFT) & CSR_DEXC2DBG_SPF_MASK) -#define CSR_DEXC2DBG_SPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SPF_MASK) >> CSR_DEXC2DBG_SPF_SHIFT) - -/* - * LPF (RW) - * - * Indicates whether load fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LPF_MASK (0x20000UL) -#define CSR_DEXC2DBG_LPF_SHIFT (17U) -#define CSR_DEXC2DBG_LPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LPF_SHIFT) & CSR_DEXC2DBG_LPF_MASK) -#define CSR_DEXC2DBG_LPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LPF_MASK) >> CSR_DEXC2DBG_LPF_SHIFT) - -/* - * IPF (RW) - * - * Indicates whether instruction page fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IPF_MASK (0x10000UL) -#define CSR_DEXC2DBG_IPF_SHIFT (16U) -#define CSR_DEXC2DBG_IPF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IPF_SHIFT) & CSR_DEXC2DBG_IPF_MASK) -#define CSR_DEXC2DBG_IPF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IPF_MASK) >> CSR_DEXC2DBG_IPF_SHIFT) - -/* - * BWE (RW) - * - * Indicates whether Bus-write Transaction Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_BWE_MASK (0x8000U) -#define CSR_DEXC2DBG_BWE_SHIFT (15U) -#define CSR_DEXC2DBG_BWE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_BWE_SHIFT) & CSR_DEXC2DBG_BWE_MASK) -#define CSR_DEXC2DBG_BWE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_BWE_MASK) >> CSR_DEXC2DBG_BWE_SHIFT) - -/* - * SLPECC (RW) - * - * Indicates whether local memory slave port ECC Error local interrupts are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SLPECC_MASK (0x4000U) -#define CSR_DEXC2DBG_SLPECC_SHIFT (14U) -#define CSR_DEXC2DBG_SLPECC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SLPECC_SHIFT) & CSR_DEXC2DBG_SLPECC_MASK) -#define CSR_DEXC2DBG_SLPECC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SLPECC_MASK) >> CSR_DEXC2DBG_SLPECC_SHIFT) - -/* - * ACE (RW) - * - * Indicates whether ACE-related exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.ACE is set - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_ACE_MASK (0x2000U) -#define CSR_DEXC2DBG_ACE_SHIFT (13U) -#define CSR_DEXC2DBG_ACE_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_ACE_SHIFT) & CSR_DEXC2DBG_ACE_MASK) -#define CSR_DEXC2DBG_ACE_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_ACE_MASK) >> CSR_DEXC2DBG_ACE_SHIFT) - -/* - * HSP (RW) - * - * Indicates whether Stack Protection exceptions are redirected to enter Debug Mode. This bit is present only when mmsc_cfg.HSP is set. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_HSP_MASK (0x1000U) -#define CSR_DEXC2DBG_HSP_SHIFT (12U) -#define CSR_DEXC2DBG_HSP_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_HSP_SHIFT) & CSR_DEXC2DBG_HSP_MASK) -#define CSR_DEXC2DBG_HSP_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_HSP_MASK) >> CSR_DEXC2DBG_HSP_SHIFT) - -/* - * MEC (RW) - * - * Indicates whether M-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_MEC_MASK (0x800U) -#define CSR_DEXC2DBG_MEC_SHIFT (11U) -#define CSR_DEXC2DBG_MEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_MEC_SHIFT) & CSR_DEXC2DBG_MEC_MASK) -#define CSR_DEXC2DBG_MEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_MEC_MASK) >> CSR_DEXC2DBG_MEC_SHIFT) - -/* - * SEC (RW) - * - * Indicates whether S-mode Environment Call exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SEC_MASK (0x200U) -#define CSR_DEXC2DBG_SEC_SHIFT (9U) -#define CSR_DEXC2DBG_SEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SEC_SHIFT) & CSR_DEXC2DBG_SEC_MASK) -#define CSR_DEXC2DBG_SEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SEC_MASK) >> CSR_DEXC2DBG_SEC_SHIFT) - -/* - * UEC (RW) - * - * Indicates whether U-mode Environment Call exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_UEC_MASK (0x100U) -#define CSR_DEXC2DBG_UEC_SHIFT (8U) -#define CSR_DEXC2DBG_UEC_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_UEC_SHIFT) & CSR_DEXC2DBG_UEC_MASK) -#define CSR_DEXC2DBG_UEC_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_UEC_MASK) >> CSR_DEXC2DBG_UEC_SHIFT) - -/* - * SAF (RW) - * - * Indicates whether Store Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAF_MASK (0x80U) -#define CSR_DEXC2DBG_SAF_SHIFT (7U) -#define CSR_DEXC2DBG_SAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAF_SHIFT) & CSR_DEXC2DBG_SAF_MASK) -#define CSR_DEXC2DBG_SAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAF_MASK) >> CSR_DEXC2DBG_SAF_SHIFT) - -/* - * SAM (RW) - * - * Indicates whether Store Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_SAM_MASK (0x40U) -#define CSR_DEXC2DBG_SAM_SHIFT (6U) -#define CSR_DEXC2DBG_SAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_SAM_SHIFT) & CSR_DEXC2DBG_SAM_MASK) -#define CSR_DEXC2DBG_SAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_SAM_MASK) >> CSR_DEXC2DBG_SAM_SHIFT) - -/* - * LAF (RW) - * - * Indicates whether Load Access Fault exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAF_MASK (0x20U) -#define CSR_DEXC2DBG_LAF_SHIFT (5U) -#define CSR_DEXC2DBG_LAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAF_SHIFT) & CSR_DEXC2DBG_LAF_MASK) -#define CSR_DEXC2DBG_LAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAF_MASK) >> CSR_DEXC2DBG_LAF_SHIFT) - -/* - * LAM (RW) - * - * Indicates whether Load Access Misaligned exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_LAM_MASK (0x10U) -#define CSR_DEXC2DBG_LAM_SHIFT (4U) -#define CSR_DEXC2DBG_LAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_LAM_SHIFT) & CSR_DEXC2DBG_LAM_MASK) -#define CSR_DEXC2DBG_LAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_LAM_MASK) >> CSR_DEXC2DBG_LAM_SHIFT) - -/* - * NMI (RW) - * - * Indicates whether Non-Maskable Interrupt - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_NMI_MASK (0x8U) -#define CSR_DEXC2DBG_NMI_SHIFT (3U) -#define CSR_DEXC2DBG_NMI_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_NMI_SHIFT) & CSR_DEXC2DBG_NMI_MASK) -#define CSR_DEXC2DBG_NMI_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_NMI_MASK) >> CSR_DEXC2DBG_NMI_SHIFT) - -/* - * II (RW) - * - * Indicates whether Illegal Instruction exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_II_MASK (0x4U) -#define CSR_DEXC2DBG_II_SHIFT (2U) -#define CSR_DEXC2DBG_II_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_II_SHIFT) & CSR_DEXC2DBG_II_MASK) -#define CSR_DEXC2DBG_II_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_II_MASK) >> CSR_DEXC2DBG_II_SHIFT) - -/* - * IAF (RW) - * - * Indicates whether Instruction Access Fault exceptions are redirected to enter Debug Mode - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAF_MASK (0x2U) -#define CSR_DEXC2DBG_IAF_SHIFT (1U) -#define CSR_DEXC2DBG_IAF_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAF_SHIFT) & CSR_DEXC2DBG_IAF_MASK) -#define CSR_DEXC2DBG_IAF_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAF_MASK) >> CSR_DEXC2DBG_IAF_SHIFT) - -/* - * IAM (RW) - * - * Indicates whether Instruction Access Misaligned exceptions are redirected to enter Debug Mode. - * 0:Do not redirect - * 1:Redirect - */ -#define CSR_DEXC2DBG_IAM_MASK (0x1U) -#define CSR_DEXC2DBG_IAM_SHIFT (0U) -#define CSR_DEXC2DBG_IAM_SET(x) (((uint32_t)(x) << CSR_DEXC2DBG_IAM_SHIFT) & CSR_DEXC2DBG_IAM_MASK) -#define CSR_DEXC2DBG_IAM_GET(x) (((uint32_t)(x) & CSR_DEXC2DBG_IAM_MASK) >> CSR_DEXC2DBG_IAM_SHIFT) - -/* Bitfield definition for register: DDCAUSE */ -/* - * SUBTYPE (RO) - * - * Subtypes for main type. - * The table below lists the subtypes for DCSR.CAUSE==1 and DDCAUSE.MAINTYPE==3. - * 0:Illegal instruction - * 1:Privileged instruction - * 2:Non-existent CSR - * 3:Privilege CSR access - * 4:Read-only CSR update - */ -#define CSR_DDCAUSE_SUBTYPE_MASK (0xFF00U) -#define CSR_DDCAUSE_SUBTYPE_SHIFT (8U) -#define CSR_DDCAUSE_SUBTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_SUBTYPE_MASK) >> CSR_DDCAUSE_SUBTYPE_SHIFT) - -/* - * MAINTYPE (RO) - * - * Cause for redirection to Debug Mode. - * 0:Software Breakpoint (EBREAK) - * 1:Instruction Access Misaligned (IAM) - * 2:Instruction Access Fault (IAF) - * 3:Illegal Instruction (II) - * 4:Non-Maskable Interrupt (NMI) - * 5:Load Access Misaligned (LAM) - * 6:Load Access Fault (LAF) - * 7:Store Access Misaligned (SAM) - * 8:Store Access Fault (SAF) - * 9:U-mode Environment Call (UEC) - * 10:S-mode Environment Call (SEC) - * 11:Instruction page fault - * 12:M-mode Environment Call (MEC) - * 13:Load page fault - * 14:Reserved - * 15:Store/AMO page fault - * 16:Imprecise ECC error - * 17;Bus write transaction error - * 18:Performance Counter overflow - * 19–31:Reserved - * 32:Stack overflow exception - * 33:Stack underflow exception - * 34:ACE disabled exception - * 35–39:Reserved - * 40–47:ACE exception - * ≥48:Reserved - */ -#define CSR_DDCAUSE_MAINTYPE_MASK (0xFFU) -#define CSR_DDCAUSE_MAINTYPE_SHIFT (0U) -#define CSR_DDCAUSE_MAINTYPE_GET(x) (((uint32_t)(x) & CSR_DDCAUSE_MAINTYPE_MASK) >> CSR_DDCAUSE_MAINTYPE_SHIFT) - -/* Bitfield definition for register: UITB */ -/* - * ADDR (RW) - * - * The base address of the CoDense instruction table. This field is reserved if uitb.HW == 1. - */ -#define CSR_UITB_ADDR_MASK (0xFFFFFFFCUL) -#define CSR_UITB_ADDR_SHIFT (2U) -#define CSR_UITB_ADDR_SET(x) (((uint32_t)(x) << CSR_UITB_ADDR_SHIFT) & CSR_UITB_ADDR_MASK) -#define CSR_UITB_ADDR_GET(x) (((uint32_t)(x) & CSR_UITB_ADDR_MASK) >> CSR_UITB_ADDR_SHIFT) - -/* - * HW (RO) - * - * This bit specifies if the CoDense instruction table is hardwired. - * 0:The instruction table is located in memory. uitb.ADDR should be initialized to point to the table before using the CoDense instructions. - * 1:The instruction table is hardwired. Initialization of uitb.ADDR is not needed before using the CoDense instructions. - */ -#define CSR_UITB_HW_MASK (0x1U) -#define CSR_UITB_HW_SHIFT (0U) -#define CSR_UITB_HW_GET(x) (((uint32_t)(x) & CSR_UITB_HW_MASK) >> CSR_UITB_HW_SHIFT) - -/* Bitfield definition for register: UCODE */ -/* - * OV (RW) - * - * Overflow flag. It will be set by DSP instructions with a saturated result. - * 0:A saturated result is not generated - * 1:A saturated result is generated - */ -#define CSR_UCODE_OV_MASK (0x1U) -#define CSR_UCODE_OV_SHIFT (0U) -#define CSR_UCODE_OV_SET(x) (((uint32_t)(x) << CSR_UCODE_OV_SHIFT) & CSR_UCODE_OV_MASK) -#define CSR_UCODE_OV_GET(x) (((uint32_t)(x) & CSR_UCODE_OV_MASK) >> CSR_UCODE_OV_SHIFT) - -/* Bitfield definition for register: UDCAUSE */ -/* - * UDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the ucause register. See the list below for details. - * The value of UDCAUSE for precise exception: - * When ucause == 1 (Instruction access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP instruction access violation - * 3:Bus error - * 4:PMA empty hole access - * When ucause == 2 (Illegal instruction) - * 0:Please parse the utval CSR - * 1:FP disabled exception - * 2:ACE disabled exception - * When ucause == 5 (Load access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP load access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - * When ucause == 7 (Store access fault) - * 0:Reserved - * 1:ECC/Parity error - * 2:PMP store access violation - * 3:Bus error - * 4:Misaligned address - * 5:PMA empty hole access - * 6:PMA attribute inconsistency - * 7:PMA NAMO exception - */ -#define CSR_UDCAUSE_UDCAUSE_MASK (0x7U) -#define CSR_UDCAUSE_UDCAUSE_SHIFT (0U) -#define CSR_UDCAUSE_UDCAUSE_SET(x) (((uint32_t)(x) << CSR_UDCAUSE_UDCAUSE_SHIFT) & CSR_UDCAUSE_UDCAUSE_MASK) -#define CSR_UDCAUSE_UDCAUSE_GET(x) (((uint32_t)(x) & CSR_UDCAUSE_UDCAUSE_MASK) >> CSR_UDCAUSE_UDCAUSE_SHIFT) - -/* Bitfield definition for register: UCCTLBEGINADDR */ -/* - * VA (RW) - * - * It is an alias to the mcctlbeginaddr register and it is only accessible to Supervisor-mode and User-mode software when mcache_ctl.CCTL_SUEN is 1. Otherwise illegal instruction exceptions will be triggered. - */ -#define CSR_UCCTLBEGINADDR_VA_MASK (0xFFFFFFFFUL) -#define CSR_UCCTLBEGINADDR_VA_SHIFT (0U) -#define CSR_UCCTLBEGINADDR_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLBEGINADDR_VA_SHIFT) & CSR_UCCTLBEGINADDR_VA_MASK) -#define CSR_UCCTLBEGINADDR_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLBEGINADDR_VA_MASK) >> CSR_UCCTLBEGINADDR_VA_SHIFT) - -/* Bitfield definition for register: UCCTLCOMMAND */ -/* - * VA (RW) - * - * See User CCTL Command Definition Table - */ -#define CSR_UCCTLCOMMAND_VA_MASK (0x1FU) -#define CSR_UCCTLCOMMAND_VA_SHIFT (0U) -#define CSR_UCCTLCOMMAND_VA_SET(x) (((uint32_t)(x) << CSR_UCCTLCOMMAND_VA_SHIFT) & CSR_UCCTLCOMMAND_VA_MASK) -#define CSR_UCCTLCOMMAND_VA_GET(x) (((uint32_t)(x) & CSR_UCCTLCOMMAND_VA_MASK) >> CSR_UCCTLCOMMAND_VA_SHIFT) - -/* Bitfield definition for register: SLIE */ -/* - * PMOVI (RW) - * - * Enable S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_PMOVI_MASK (0x40000UL) -#define CSR_SLIE_PMOVI_SHIFT (18U) -#define CSR_SLIE_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIE_PMOVI_SHIFT) & CSR_SLIE_PMOVI_MASK) -#define CSR_SLIE_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIE_PMOVI_MASK) >> CSR_SLIE_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Enable S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_BWEI_MASK (0x20000UL) -#define CSR_SLIE_BWEI_SHIFT (17U) -#define CSR_SLIE_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIE_BWEI_SHIFT) & CSR_SLIE_BWEI_MASK) -#define CSR_SLIE_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIE_BWEI_MASK) >> CSR_SLIE_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Enable S-mode slave-port ECC error local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIE_IMECCI_MASK (0x10000UL) -#define CSR_SLIE_IMECCI_SHIFT (16U) -#define CSR_SLIE_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIE_IMECCI_SHIFT) & CSR_SLIE_IMECCI_MASK) -#define CSR_SLIE_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIE_IMECCI_MASK) >> CSR_SLIE_IMECCI_SHIFT) - -/* Bitfield definition for register: SLIP */ -/* - * PMOVI (RW) - * - * Pending control and status of S-mode performance monitor overflow local interrupt. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_PMOVI_MASK (0x40000UL) -#define CSR_SLIP_PMOVI_SHIFT (18U) -#define CSR_SLIP_PMOVI_SET(x) (((uint32_t)(x) << CSR_SLIP_PMOVI_SHIFT) & CSR_SLIP_PMOVI_MASK) -#define CSR_SLIP_PMOVI_GET(x) (((uint32_t)(x) & CSR_SLIP_PMOVI_MASK) >> CSR_SLIP_PMOVI_SHIFT) - -/* - * BWEI (RW) - * - * Pending control and status of S-mode bus read/write transaction error local interrupt. The processor may receive bus errors on load/store instructions or cache writebacks. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_BWEI_MASK (0x20000UL) -#define CSR_SLIP_BWEI_SHIFT (17U) -#define CSR_SLIP_BWEI_SET(x) (((uint32_t)(x) << CSR_SLIP_BWEI_SHIFT) & CSR_SLIP_BWEI_MASK) -#define CSR_SLIP_BWEI_GET(x) (((uint32_t)(x) & CSR_SLIP_BWEI_MASK) >> CSR_SLIP_BWEI_SHIFT) - -/* - * IMECCI (RW) - * - * Pending control and status of S-mode slave-port ECC error local interrupt.. - * 0:Local interrupt is not enabled. - * 1:Local interrupt is enabled - */ -#define CSR_SLIP_IMECCI_MASK (0x10000UL) -#define CSR_SLIP_IMECCI_SHIFT (16U) -#define CSR_SLIP_IMECCI_SET(x) (((uint32_t)(x) << CSR_SLIP_IMECCI_SHIFT) & CSR_SLIP_IMECCI_MASK) -#define CSR_SLIP_IMECCI_GET(x) (((uint32_t)(x) & CSR_SLIP_IMECCI_MASK) >> CSR_SLIP_IMECCI_SHIFT) - -/* Bitfield definition for register: SDCAUSE */ -/* - * PM (RW) - * - * When scause is imprecise exception (in the form of an interrupt), the PM field records the privileged mode of the instruction that caused the imprecise exception. The PM field encoding is defined as follows: - * 0:User mode - * 1:Supervisor mode - * 2:Reserved - * 3:Machine mode - */ -#define CSR_SDCAUSE_PM_MASK (0x60U) -#define CSR_SDCAUSE_PM_SHIFT (5U) -#define CSR_SDCAUSE_PM_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_PM_SHIFT) & CSR_SDCAUSE_PM_MASK) -#define CSR_SDCAUSE_PM_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_PM_MASK) >> CSR_SDCAUSE_PM_SHIFT) - -/* - * SDCAUSE (RW) - * - * This register further disambiguates causes of traps recorded in the scause register. See the list below for details. - * The value of SDCAUSE for precise exception: - * When scause == 1 (Instruction access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP instruction access violation; 3:Bus error; 4:PMA empty hole access - * When scause == 2 (Illegal instruction): - * 0:Please parse the stval CSR; 1:FP disabled exception; 2:ACE disabled exception - * When scause == 5 (Load access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * When scause == 7 (Store access fault): - * 0:Reserved; 1:ECC/Parity error; 2:PMP load access violation; 3:Bus error; 4:Misaligned address; 5:PMA empty hole access; 6:PMA attribute inconsistency; 7:PMA NAMO exception - * The value of SDCAUSE for imprecise exception: - * When scause == Local Interrupt 16 or Local Interrupt 272 (16 + 256) (ECC error local interrupt) - * 0:Reserved; 1:LM slave port ECC/Parity error; 2:Imprecise store ECC/Parity error; 3:Imprecise load ECC/Parity error - * When scause == Local Interrupt 17 or Local Interrupt 273 (17 + 256) (Bus read/write transaction error local interrupt) - * 0:Reserved; 1:Bus read error; 2:Bus write error; 3:PMP error caused by load instructions; 4:PMP error caused by store instructions; 5:PMA error caused by load instructions; 6:PMA error caused by store instructions - */ -#define CSR_SDCAUSE_SDCAUSE_MASK (0x7U) -#define CSR_SDCAUSE_SDCAUSE_SHIFT (0U) -#define CSR_SDCAUSE_SDCAUSE_SET(x) (((uint32_t)(x) << CSR_SDCAUSE_SDCAUSE_SHIFT) & CSR_SDCAUSE_SDCAUSE_MASK) -#define CSR_SDCAUSE_SDCAUSE_GET(x) (((uint32_t)(x) & CSR_SDCAUSE_SDCAUSE_MASK) >> CSR_SDCAUSE_SDCAUSE_SHIFT) - -/* Bitfield definition for register: SCCTLDATA */ -/* - * VA (RW) - * - * See CCTL Commands Which Access mcctldata Table - */ -#define CSR_SCCTLDATA_VA_MASK (0x1FU) -#define CSR_SCCTLDATA_VA_SHIFT (0U) -#define CSR_SCCTLDATA_VA_SET(x) (((uint32_t)(x) << CSR_SCCTLDATA_VA_SHIFT) & CSR_SCCTLDATA_VA_MASK) -#define CSR_SCCTLDATA_VA_GET(x) (((uint32_t)(x) & CSR_SCCTLDATA_VA_MASK) >> CSR_SCCTLDATA_VA_SHIFT) - -/* Bitfield definition for register: SCOUNTERINTEN */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM6_MASK (0x40U) -#define CSR_SCOUNTERINTEN_HPM6_SHIFT (6U) -#define CSR_SCOUNTERINTEN_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM6_SHIFT) & CSR_SCOUNTERINTEN_HPM6_MASK) -#define CSR_SCOUNTERINTEN_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM6_MASK) >> CSR_SCOUNTERINTEN_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM5_MASK (0x20U) -#define CSR_SCOUNTERINTEN_HPM5_SHIFT (5U) -#define CSR_SCOUNTERINTEN_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM5_SHIFT) & CSR_SCOUNTERINTEN_HPM5_MASK) -#define CSR_SCOUNTERINTEN_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM5_MASK) >> CSR_SCOUNTERINTEN_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM4_MASK (0x10U) -#define CSR_SCOUNTERINTEN_HPM4_SHIFT (4U) -#define CSR_SCOUNTERINTEN_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM4_SHIFT) & CSR_SCOUNTERINTEN_HPM4_MASK) -#define CSR_SCOUNTERINTEN_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM4_MASK) >> CSR_SCOUNTERINTEN_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_HPM3_MASK (0x8U) -#define CSR_SCOUNTERINTEN_HPM3_SHIFT (3U) -#define CSR_SCOUNTERINTEN_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_HPM3_SHIFT) & CSR_SCOUNTERINTEN_HPM3_MASK) -#define CSR_SCOUNTERINTEN_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_HPM3_MASK) >> CSR_SCOUNTERINTEN_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_IR_MASK (0x4U) -#define CSR_SCOUNTERINTEN_IR_SHIFT (2U) -#define CSR_SCOUNTERINTEN_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_IR_SHIFT) & CSR_SCOUNTERINTEN_IR_MASK) -#define CSR_SCOUNTERINTEN_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_IR_MASK) >> CSR_SCOUNTERINTEN_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERINTEN_CY_MASK (0x1U) -#define CSR_SCOUNTERINTEN_CY_SHIFT (0U) -#define CSR_SCOUNTERINTEN_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERINTEN_CY_SHIFT) & CSR_SCOUNTERINTEN_CY_MASK) -#define CSR_SCOUNTERINTEN_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERINTEN_CY_MASK) >> CSR_SCOUNTERINTEN_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_M */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_M_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_M_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM6_SHIFT) & CSR_SCOUNTERMASK_M_HPM6_MASK) -#define CSR_SCOUNTERMASK_M_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM6_MASK) >> CSR_SCOUNTERMASK_M_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_M_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_M_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM5_SHIFT) & CSR_SCOUNTERMASK_M_HPM5_MASK) -#define CSR_SCOUNTERMASK_M_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM5_MASK) >> CSR_SCOUNTERMASK_M_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_M_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_M_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM4_SHIFT) & CSR_SCOUNTERMASK_M_HPM4_MASK) -#define CSR_SCOUNTERMASK_M_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM4_MASK) >> CSR_SCOUNTERMASK_M_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_M_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_M_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_HPM3_SHIFT) & CSR_SCOUNTERMASK_M_HPM3_MASK) -#define CSR_SCOUNTERMASK_M_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_HPM3_MASK) >> CSR_SCOUNTERMASK_M_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_M_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_M_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_IR_SHIFT) & CSR_SCOUNTERMASK_M_IR_MASK) -#define CSR_SCOUNTERMASK_M_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_IR_MASK) >> CSR_SCOUNTERMASK_M_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_M_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_M_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_M_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_M_CY_SHIFT) & CSR_SCOUNTERMASK_M_CY_MASK) -#define CSR_SCOUNTERMASK_M_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_M_CY_MASK) >> CSR_SCOUNTERMASK_M_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_S */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_S_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_S_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM6_SHIFT) & CSR_SCOUNTERMASK_S_HPM6_MASK) -#define CSR_SCOUNTERMASK_S_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM6_MASK) >> CSR_SCOUNTERMASK_S_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_S_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_S_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM5_SHIFT) & CSR_SCOUNTERMASK_S_HPM5_MASK) -#define CSR_SCOUNTERMASK_S_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM5_MASK) >> CSR_SCOUNTERMASK_S_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_S_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_S_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM4_SHIFT) & CSR_SCOUNTERMASK_S_HPM4_MASK) -#define CSR_SCOUNTERMASK_S_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM4_MASK) >> CSR_SCOUNTERMASK_S_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_S_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_S_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_HPM3_SHIFT) & CSR_SCOUNTERMASK_S_HPM3_MASK) -#define CSR_SCOUNTERMASK_S_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_HPM3_MASK) >> CSR_SCOUNTERMASK_S_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_S_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_S_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_IR_SHIFT) & CSR_SCOUNTERMASK_S_IR_MASK) -#define CSR_SCOUNTERMASK_S_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_IR_MASK) >> CSR_SCOUNTERMASK_S_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_S_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_S_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_S_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_S_CY_SHIFT) & CSR_SCOUNTERMASK_S_CY_MASK) -#define CSR_SCOUNTERMASK_S_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_S_CY_MASK) >> CSR_SCOUNTERMASK_S_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTERMASK_U */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM6_MASK (0x40U) -#define CSR_SCOUNTERMASK_U_HPM6_SHIFT (6U) -#define CSR_SCOUNTERMASK_U_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM6_SHIFT) & CSR_SCOUNTERMASK_U_HPM6_MASK) -#define CSR_SCOUNTERMASK_U_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM6_MASK) >> CSR_SCOUNTERMASK_U_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM5_MASK (0x20U) -#define CSR_SCOUNTERMASK_U_HPM5_SHIFT (5U) -#define CSR_SCOUNTERMASK_U_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM5_SHIFT) & CSR_SCOUNTERMASK_U_HPM5_MASK) -#define CSR_SCOUNTERMASK_U_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM5_MASK) >> CSR_SCOUNTERMASK_U_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM4_MASK (0x10U) -#define CSR_SCOUNTERMASK_U_HPM4_SHIFT (4U) -#define CSR_SCOUNTERMASK_U_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM4_SHIFT) & CSR_SCOUNTERMASK_U_HPM4_MASK) -#define CSR_SCOUNTERMASK_U_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM4_MASK) >> CSR_SCOUNTERMASK_U_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_HPM3_MASK (0x8U) -#define CSR_SCOUNTERMASK_U_HPM3_SHIFT (3U) -#define CSR_SCOUNTERMASK_U_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_HPM3_SHIFT) & CSR_SCOUNTERMASK_U_HPM3_MASK) -#define CSR_SCOUNTERMASK_U_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_HPM3_MASK) >> CSR_SCOUNTERMASK_U_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_IR_MASK (0x4U) -#define CSR_SCOUNTERMASK_U_IR_SHIFT (2U) -#define CSR_SCOUNTERMASK_U_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_IR_SHIFT) & CSR_SCOUNTERMASK_U_IR_MASK) -#define CSR_SCOUNTERMASK_U_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_IR_MASK) >> CSR_SCOUNTERMASK_U_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTERMASK_U_CY_MASK (0x1U) -#define CSR_SCOUNTERMASK_U_CY_SHIFT (0U) -#define CSR_SCOUNTERMASK_U_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTERMASK_U_CY_SHIFT) & CSR_SCOUNTERMASK_U_CY_MASK) -#define CSR_SCOUNTERMASK_U_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTERMASK_U_CY_MASK) >> CSR_SCOUNTERMASK_U_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTEROVF */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM6_MASK (0x40U) -#define CSR_SCOUNTEROVF_HPM6_SHIFT (6U) -#define CSR_SCOUNTEROVF_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM6_SHIFT) & CSR_SCOUNTEROVF_HPM6_MASK) -#define CSR_SCOUNTEROVF_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM6_MASK) >> CSR_SCOUNTEROVF_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM5_MASK (0x20U) -#define CSR_SCOUNTEROVF_HPM5_SHIFT (5U) -#define CSR_SCOUNTEROVF_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM5_SHIFT) & CSR_SCOUNTEROVF_HPM5_MASK) -#define CSR_SCOUNTEROVF_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM5_MASK) >> CSR_SCOUNTEROVF_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM4_MASK (0x10U) -#define CSR_SCOUNTEROVF_HPM4_SHIFT (4U) -#define CSR_SCOUNTEROVF_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM4_SHIFT) & CSR_SCOUNTEROVF_HPM4_MASK) -#define CSR_SCOUNTEROVF_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM4_MASK) >> CSR_SCOUNTEROVF_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_HPM3_MASK (0x8U) -#define CSR_SCOUNTEROVF_HPM3_SHIFT (3U) -#define CSR_SCOUNTEROVF_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_HPM3_SHIFT) & CSR_SCOUNTEROVF_HPM3_MASK) -#define CSR_SCOUNTEROVF_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_HPM3_MASK) >> CSR_SCOUNTEROVF_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_IR_MASK (0x4U) -#define CSR_SCOUNTEROVF_IR_SHIFT (2U) -#define CSR_SCOUNTEROVF_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_IR_SHIFT) & CSR_SCOUNTEROVF_IR_MASK) -#define CSR_SCOUNTEROVF_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_IR_MASK) >> CSR_SCOUNTEROVF_IR_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTEROVF_CY_MASK (0x1U) -#define CSR_SCOUNTEROVF_CY_SHIFT (0U) -#define CSR_SCOUNTEROVF_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTEROVF_CY_SHIFT) & CSR_SCOUNTEROVF_CY_MASK) -#define CSR_SCOUNTEROVF_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTEROVF_CY_MASK) >> CSR_SCOUNTEROVF_CY_SHIFT) - -/* Bitfield definition for register: SCOUNTINHIBIT */ -/* - * HPM6 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM6_MASK (0x40U) -#define CSR_SCOUNTINHIBIT_HPM6_SHIFT (6U) -#define CSR_SCOUNTINHIBIT_HPM6_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM6_SHIFT) & CSR_SCOUNTINHIBIT_HPM6_MASK) -#define CSR_SCOUNTINHIBIT_HPM6_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM6_MASK) >> CSR_SCOUNTINHIBIT_HPM6_SHIFT) - -/* - * HPM5 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM5_MASK (0x20U) -#define CSR_SCOUNTINHIBIT_HPM5_SHIFT (5U) -#define CSR_SCOUNTINHIBIT_HPM5_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM5_SHIFT) & CSR_SCOUNTINHIBIT_HPM5_MASK) -#define CSR_SCOUNTINHIBIT_HPM5_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM5_MASK) >> CSR_SCOUNTINHIBIT_HPM5_SHIFT) - -/* - * HPM4 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM4_MASK (0x10U) -#define CSR_SCOUNTINHIBIT_HPM4_SHIFT (4U) -#define CSR_SCOUNTINHIBIT_HPM4_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM4_SHIFT) & CSR_SCOUNTINHIBIT_HPM4_MASK) -#define CSR_SCOUNTINHIBIT_HPM4_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM4_MASK) >> CSR_SCOUNTINHIBIT_HPM4_SHIFT) - -/* - * HPM3 (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_HPM3_MASK (0x8U) -#define CSR_SCOUNTINHIBIT_HPM3_SHIFT (3U) -#define CSR_SCOUNTINHIBIT_HPM3_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_HPM3_SHIFT) & CSR_SCOUNTINHIBIT_HPM3_MASK) -#define CSR_SCOUNTINHIBIT_HPM3_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_HPM3_MASK) >> CSR_SCOUNTINHIBIT_HPM3_SHIFT) - -/* - * IR (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_IR_MASK (0x4U) -#define CSR_SCOUNTINHIBIT_IR_SHIFT (2U) -#define CSR_SCOUNTINHIBIT_IR_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_IR_SHIFT) & CSR_SCOUNTINHIBIT_IR_MASK) -#define CSR_SCOUNTINHIBIT_IR_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_IR_MASK) >> CSR_SCOUNTINHIBIT_IR_SHIFT) - -/* - * TM (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_TM_MASK (0x2U) -#define CSR_SCOUNTINHIBIT_TM_SHIFT (1U) -#define CSR_SCOUNTINHIBIT_TM_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_TM_SHIFT) & CSR_SCOUNTINHIBIT_TM_MASK) -#define CSR_SCOUNTINHIBIT_TM_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_TM_MASK) >> CSR_SCOUNTINHIBIT_TM_SHIFT) - -/* - * CY (RW) - * - * See register description - */ -#define CSR_SCOUNTINHIBIT_CY_MASK (0x1U) -#define CSR_SCOUNTINHIBIT_CY_SHIFT (0U) -#define CSR_SCOUNTINHIBIT_CY_SET(x) (((uint32_t)(x) << CSR_SCOUNTINHIBIT_CY_SHIFT) & CSR_SCOUNTINHIBIT_CY_MASK) -#define CSR_SCOUNTINHIBIT_CY_GET(x) (((uint32_t)(x) & CSR_SCOUNTINHIBIT_CY_MASK) >> CSR_SCOUNTINHIBIT_CY_SHIFT) - -/* Bitfield definition for register: SHPMEVENT3 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT3_SEL_SHIFT (4U) -#define CSR_SHPMEVENT3_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_SEL_SHIFT) & CSR_SHPMEVENT3_SEL_MASK) -#define CSR_SHPMEVENT3_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_SEL_MASK) >> CSR_SHPMEVENT3_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT3_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT3_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT3_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT3_TYPE_SHIFT) & CSR_SHPMEVENT3_TYPE_MASK) -#define CSR_SHPMEVENT3_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT3_TYPE_MASK) >> CSR_SHPMEVENT3_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT4 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT4_SEL_SHIFT (4U) -#define CSR_SHPMEVENT4_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_SEL_SHIFT) & CSR_SHPMEVENT4_SEL_MASK) -#define CSR_SHPMEVENT4_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_SEL_MASK) >> CSR_SHPMEVENT4_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT4_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT4_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT4_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT4_TYPE_SHIFT) & CSR_SHPMEVENT4_TYPE_MASK) -#define CSR_SHPMEVENT4_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT4_TYPE_MASK) >> CSR_SHPMEVENT4_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT5 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT5_SEL_SHIFT (4U) -#define CSR_SHPMEVENT5_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_SEL_SHIFT) & CSR_SHPMEVENT5_SEL_MASK) -#define CSR_SHPMEVENT5_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_SEL_MASK) >> CSR_SHPMEVENT5_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT5_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT5_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT5_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT5_TYPE_SHIFT) & CSR_SHPMEVENT5_TYPE_MASK) -#define CSR_SHPMEVENT5_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT5_TYPE_MASK) >> CSR_SHPMEVENT5_TYPE_SHIFT) - -/* Bitfield definition for register: SHPMEVENT6 */ -/* - * SEL (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_SEL_MASK (0x1F0U) -#define CSR_SHPMEVENT6_SEL_SHIFT (4U) -#define CSR_SHPMEVENT6_SEL_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_SEL_SHIFT) & CSR_SHPMEVENT6_SEL_MASK) -#define CSR_SHPMEVENT6_SEL_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_SEL_MASK) >> CSR_SHPMEVENT6_SEL_SHIFT) - -/* - * TYPE (RW) - * - * See Event Selectors table - */ -#define CSR_SHPMEVENT6_TYPE_MASK (0xFU) -#define CSR_SHPMEVENT6_TYPE_SHIFT (0U) -#define CSR_SHPMEVENT6_TYPE_SET(x) (((uint32_t)(x) << CSR_SHPMEVENT6_TYPE_SHIFT) & CSR_SHPMEVENT6_TYPE_MASK) -#define CSR_SHPMEVENT6_TYPE_GET(x) (((uint32_t)(x) & CSR_SHPMEVENT6_TYPE_MASK) >> CSR_SHPMEVENT6_TYPE_SHIFT) - -/* Bitfield definition for register: MICM_CFG */ -/* - * SETH (RO) - * - * This bit extends the ISET field. - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MICM_CFG_SETH_SHIFT (24U) -#define CSR_MICM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_SETH_MASK) >> CSR_MICM_CFG_SETH_SHIFT) - -/* - * ILM_ECC (RO) - * - * ILM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILM_ECC_MASK (0x600000UL) -#define CSR_MICM_CFG_ILM_ECC_SHIFT (21U) -#define CSR_MICM_CFG_ILM_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILM_ECC_MASK) >> CSR_MICM_CFG_ILM_ECC_SHIFT) - -/* - * ILMSZ (RO) - * - * ILM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMSZ_MASK (0xF8000UL) -#define CSR_MICM_CFG_ILMSZ_SHIFT (15U) -#define CSR_MICM_CFG_ILMSZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMSZ_MASK) >> CSR_MICM_CFG_ILMSZ_SHIFT) - -/* - * ILMB (RW) - * - * Number of ILM base registers present - * 0:No ILM base register present - * 1:One ILM base register present - * 2-7:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILMB_MASK (0x7000U) -#define CSR_MICM_CFG_ILMB_SHIFT (12U) -#define CSR_MICM_CFG_ILMB_SET(x) (((uint32_t)(x) << CSR_MICM_CFG_ILMB_SHIFT) & CSR_MICM_CFG_ILMB_MASK) -#define CSR_MICM_CFG_ILMB_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILMB_MASK) >> CSR_MICM_CFG_ILMB_SHIFT) - -/* - * IC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IC_ECC_MASK (0xC00U) -#define CSR_MICM_CFG_IC_ECC_SHIFT (10U) -#define CSR_MICM_CFG_IC_ECC_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IC_ECC_MASK) >> CSR_MICM_CFG_IC_ECC_SHIFT) - -/* - * ILCK (RO) - * - * I-Cache locking support - * 0:No locking support - * 1:With locking support - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ILCK_MASK (0x200U) -#define CSR_MICM_CFG_ILCK_SHIFT (9U) -#define CSR_MICM_CFG_ILCK_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ILCK_MASK) >> CSR_MICM_CFG_ILCK_SHIFT) - -/* - * ISZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_ISZ_MASK (0x1C0U) -#define CSR_MICM_CFG_ISZ_SHIFT (6U) -#define CSR_MICM_CFG_ISZ_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISZ_MASK) >> CSR_MICM_CFG_ISZ_SHIFT) - -/* - * IWAY (RO) - * - * Associativity of I-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MICM_CFG_IWAY_MASK (0x38U) -#define CSR_MICM_CFG_IWAY_SHIFT (3U) -#define CSR_MICM_CFG_IWAY_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_IWAY_MASK) >> CSR_MICM_CFG_IWAY_SHIFT) - -/* - * ISET (RO) - * - * I-Cache sets (# of cache lines per way): - * When micm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When micm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - */ -#define CSR_MICM_CFG_ISET_MASK (0x7U) -#define CSR_MICM_CFG_ISET_SHIFT (0U) -#define CSR_MICM_CFG_ISET_GET(x) (((uint32_t)(x) & CSR_MICM_CFG_ISET_MASK) >> CSR_MICM_CFG_ISET_SHIFT) - -/* Bitfield definition for register: MDCM_CFG */ -/* - * SETH (RO) - * - * This bit extends the DSET field. - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_SETH_MASK (0x1000000UL) -#define CSR_MDCM_CFG_SETH_SHIFT (24U) -#define CSR_MDCM_CFG_SETH_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_SETH_MASK) >> CSR_MDCM_CFG_SETH_SHIFT) - -/* - * DLM_ECC (RO) - * - * DLM soft-error protection scheme - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - * When DLM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLM_ECC_MASK (0x600000UL) -#define CSR_MDCM_CFG_DLM_ECC_SHIFT (21U) -#define CSR_MDCM_CFG_DLM_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLM_ECC_MASK) >> CSR_MDCM_CFG_DLM_ECC_SHIFT) - -/* - * DLMSZ (RO) - * - * DLM Size - * 0:0 Byte - * 1:1 KiB - * 2:2 KiB - * 3:4 KiB - * 4:8 KiB - * 5:16 KiB - * 6:32 KiB - * 7:64 KiB - * 8:128 KiB - * 9:256 KiB - * 10:512 KiB - * 11:1 MiB - * 12:2 MiB - * 13:4 MiB - * 14:8 MiB - * 15:16 MiB - * 16-31:Reserved - * When ILM is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLMSZ_MASK (0xF8000UL) -#define CSR_MDCM_CFG_DLMSZ_SHIFT (15U) -#define CSR_MDCM_CFG_DLMSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMSZ_MASK) >> CSR_MDCM_CFG_DLMSZ_SHIFT) - -/* - * DLMB (RO) - * - * Number of DLM base registers present - * 0:No DLM base register present - * 1:One DLM base register present - * 2-7:Reserved - * When DLM is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DLMB_MASK (0x7000U) -#define CSR_MDCM_CFG_DLMB_SHIFT (12U) -#define CSR_MDCM_CFG_DLMB_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLMB_MASK) >> CSR_MDCM_CFG_DLMB_SHIFT) - -/* - * DC_ECC (RO) - * - * Cache soft-error protection scheme - * 0:No parity/ECC support - * 1:Has parity support - * 2:Has ECC support - * 3:Reserved - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DC_ECC_MASK (0xC00U) -#define CSR_MDCM_CFG_DC_ECC_SHIFT (10U) -#define CSR_MDCM_CFG_DC_ECC_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DC_ECC_MASK) >> CSR_MDCM_CFG_DC_ECC_SHIFT) - -/* - * DLCK (RO) - * - * D-Cache locking support - * 0:No locking support - * 1:With locking support - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DLCK_MASK (0x200U) -#define CSR_MDCM_CFG_DLCK_SHIFT (9U) -#define CSR_MDCM_CFG_DLCK_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DLCK_MASK) >> CSR_MDCM_CFG_DLCK_SHIFT) - -/* - * DSZ (RO) - * - * Cache block (line) size - * 0:No I-Cache - * 1:8 bytes - * 2:16 bytes - * 3:32 bytes - * 4:64 bytes - * 5:128 bytes - * 6-7:Reserved - * When instruction cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DSZ_MASK (0x1C0U) -#define CSR_MDCM_CFG_DSZ_SHIFT (6U) -#define CSR_MDCM_CFG_DSZ_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSZ_MASK) >> CSR_MDCM_CFG_DSZ_SHIFT) - -/* - * DWAY (RO) - * - * Associativity of D-Cache - * 0:Direct-mapped - * 1:2-way - * 2:3-way - * 3:4-way - * 4:5-way - * 5:6-way - * 6:7-way - * 7:8-way - * When data cache is not configured, this field should be ignored. - */ -#define CSR_MDCM_CFG_DWAY_MASK (0x38U) -#define CSR_MDCM_CFG_DWAY_SHIFT (3U) -#define CSR_MDCM_CFG_DWAY_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DWAY_MASK) >> CSR_MDCM_CFG_DWAY_SHIFT) - -/* - * DSET (RO) - * - * D-Cache sets (# of cache lines per way): - * When mdcm_cfg.SETH==0: - * 0:64 - * 1:128 - * 2:256 - * 3:512 - * 4:1024 - * 5:2048 - * 6:4096 - * 7:Reserved - * When mdcm_cfg.SETH==1: - * 0:32 - * 1:16 - * 2:8 - * 3-7:Reserved - * When data cache is not configured, this field should be ignored - */ -#define CSR_MDCM_CFG_DSET_MASK (0x7U) -#define CSR_MDCM_CFG_DSET_SHIFT (0U) -#define CSR_MDCM_CFG_DSET_GET(x) (((uint32_t)(x) & CSR_MDCM_CFG_DSET_MASK) >> CSR_MDCM_CFG_DSET_SHIFT) - -/* Bitfield definition for register: MMSC_CFG */ -/* - * MSC_EXT (RO) - * - * Indicates if the mmsc_cfg2 CSR is present or not. - * 0:The mmsc_cfg2 CSR is not present. - * 1:The mmsc_cfg2 CSR is present - */ -#define CSR_MMSC_CFG_MSC_EXT_MASK (0x80000000UL) -#define CSR_MMSC_CFG_MSC_EXT_SHIFT (31U) -#define CSR_MMSC_CFG_MSC_EXT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_MSC_EXT_MASK) >> CSR_MMSC_CFG_MSC_EXT_SHIFT) - -/* - * PPMA (RO) - * - * Indicates if programmable PMA setup with PMA region CSRs is supported or not - * 0:Programmable PMA setup is not supported. - * 1:Programmable PMA setup is supported. - */ -#define CSR_MMSC_CFG_PPMA_MASK (0x40000000UL) -#define CSR_MMSC_CFG_PPMA_SHIFT (30U) -#define CSR_MMSC_CFG_PPMA_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PPMA_MASK) >> CSR_MMSC_CFG_PPMA_SHIFT) - -/* - * EDSP (RO) - * - * Indicates if the DSP extension is supported or not - * 0:The DSP extension is not supported. - * 1:The DSP extension is supported. - */ -#define CSR_MMSC_CFG_EDSP_MASK (0x20000000UL) -#define CSR_MMSC_CFG_EDSP_SHIFT (29U) -#define CSR_MMSC_CFG_EDSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EDSP_MASK) >> CSR_MMSC_CFG_EDSP_SHIFT) - -/* - * VCCTL (RO) - * - * Indicates the version number of CCTL command operation scheme supported by an implementation - * 0:instruction cache and data cache are not configured. - * 1:instruction cache or data cache is configured. - */ -#define CSR_MMSC_CFG_VCCTL_MASK (0xC0000UL) -#define CSR_MMSC_CFG_VCCTL_SHIFT (18U) -#define CSR_MMSC_CFG_VCCTL_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VCCTL_MASK) >> CSR_MMSC_CFG_VCCTL_SHIFT) - -/* - * EFHW (RO) - * - * Indicates the support of FLHW and FSHW instructions - * 0:FLHW and FSHW instructions are not supported - * 1:FLHW and FSHW instructions are supported. - */ -#define CSR_MMSC_CFG_EFHW_MASK (0x20000UL) -#define CSR_MMSC_CFG_EFHW_SHIFT (17U) -#define CSR_MMSC_CFG_EFHW_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EFHW_MASK) >> CSR_MMSC_CFG_EFHW_SHIFT) - -/* - * CCTLCSR (RO) - * - * Indicates the presence of CSRs for CCTL operations. - * 0:Feature of CSRs for CCTL operations is not supported. - * 1:Feature of CSRs for CCTL operations is supported. - */ -#define CSR_MMSC_CFG_CCTLCSR_MASK (0x10000UL) -#define CSR_MMSC_CFG_CCTLCSR_SHIFT (16U) -#define CSR_MMSC_CFG_CCTLCSR_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_CCTLCSR_MASK) >> CSR_MMSC_CFG_CCTLCSR_SHIFT) - -/* - * PMNDS (RO) - * - * Indicates if Andes-enhanced performance monitoring feature is present or no. - * 0:Andes-enhanced performance monitoring feature is not supported. - * 1:Andes-enhanced performance monitoring feature is supported. - */ -#define CSR_MMSC_CFG_PMNDS_MASK (0x8000U) -#define CSR_MMSC_CFG_PMNDS_SHIFT (15U) -#define CSR_MMSC_CFG_PMNDS_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PMNDS_MASK) >> CSR_MMSC_CFG_PMNDS_SHIFT) - -/* - * LMSLVP (RO) - * - * Indicates if local memory slave port is present or not. - * 0:Local memory slave port is not present. - * 1:Local memory slave port is implemented. - */ -#define CSR_MMSC_CFG_LMSLVP_MASK (0x4000U) -#define CSR_MMSC_CFG_LMSLVP_SHIFT (14U) -#define CSR_MMSC_CFG_LMSLVP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_LMSLVP_MASK) >> CSR_MMSC_CFG_LMSLVP_SHIFT) - -/* - * EV5PE (RO) - * - * Indicates whether AndeStar V5 Performance Extension is implemented or not. D45 always implements AndeStar V5 Performance Extension. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_EV5PE_MASK (0x2000U) -#define CSR_MMSC_CFG_EV5PE_SHIFT (13U) -#define CSR_MMSC_CFG_EV5PE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_EV5PE_MASK) >> CSR_MMSC_CFG_EV5PE_SHIFT) - -/* - * VPLIC (RO) - * - * Indicates whether the Andes Vectored PLIC Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_VPLIC_MASK (0x1000U) -#define CSR_MMSC_CFG_VPLIC_SHIFT (12U) -#define CSR_MMSC_CFG_VPLIC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_VPLIC_MASK) >> CSR_MMSC_CFG_VPLIC_SHIFT) - -/* - * ACE (RO) - * - * Indicates whether the Andes StackSafe hardware stack protection extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ACE_MASK (0x40U) -#define CSR_MMSC_CFG_ACE_SHIFT (6U) -#define CSR_MMSC_CFG_ACE_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ACE_MASK) >> CSR_MMSC_CFG_ACE_SHIFT) - -/* - * HSP (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_HSP_MASK (0x20U) -#define CSR_MMSC_CFG_HSP_SHIFT (5U) -#define CSR_MMSC_CFG_HSP_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_HSP_MASK) >> CSR_MMSC_CFG_HSP_SHIFT) - -/* - * PFT (RO) - * - * Indicates whether the Andes PowerBrake (Performance Throttling) power/performance scaling extension is implemented or not - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_PFT_MASK (0x10U) -#define CSR_MMSC_CFG_PFT_SHIFT (4U) -#define CSR_MMSC_CFG_PFT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_PFT_MASK) >> CSR_MMSC_CFG_PFT_SHIFT) - -/* - * ECD (RO) - * - * Indicates whether the Andes CoDense Extension is implemented or not. - * 0:Not implemented. - * 1:Implemented. - */ -#define CSR_MMSC_CFG_ECD_MASK (0x8U) -#define CSR_MMSC_CFG_ECD_SHIFT (3U) -#define CSR_MMSC_CFG_ECD_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECD_MASK) >> CSR_MMSC_CFG_ECD_SHIFT) - -/* - * TLB_ECC (RO) - * - * TLB parity/ECC support configuration. - * 0:No parity/ECC - * 1:Parity - * 2:ECC - * 3:Reserved - */ -#define CSR_MMSC_CFG_TLB_ECC_MASK (0x6U) -#define CSR_MMSC_CFG_TLB_ECC_SHIFT (1U) -#define CSR_MMSC_CFG_TLB_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_TLB_ECC_MASK) >> CSR_MMSC_CFG_TLB_ECC_SHIFT) - -/* - * ECC (RO) - * - * Indicates whether the parity/ECC soft-error protection is implemented or not. - * 0:Not implemented. - * 1:Implemented. - * The specific parity/ECC scheme used for each protected RAM is specified by the control bits in the following list. - * micm_cfg.IC_ECC - * micm_cfg.ILM_ECC - * mdcm_cfg.DC_ECC - * mdcm_cfg.DLM_ECC - * mmsc_cfg.TLB_ECC - */ -#define CSR_MMSC_CFG_ECC_MASK (0x1U) -#define CSR_MMSC_CFG_ECC_SHIFT (0U) -#define CSR_MMSC_CFG_ECC_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG_ECC_MASK) >> CSR_MMSC_CFG_ECC_SHIFT) - -/* Bitfield definition for register: MMSC_CFG2 */ -/* - * FINV (RO) - * - * Indicates if scalar FPU is implemented in VPU - * 0:Scalar FPU is not implemented in VPU - * 1:Scalar FPU is implemented in VPU - */ -#define CSR_MMSC_CFG2_FINV_MASK (0x20U) -#define CSR_MMSC_CFG2_FINV_SHIFT (5U) -#define CSR_MMSC_CFG2_FINV_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_FINV_MASK) >> CSR_MMSC_CFG2_FINV_SHIFT) - -/* - * ZFH (RO) - * - * Indicates if the FP16 half-precision floating-point extension (Zfh) is supported or not. - * 0:The FP16 extension is not supported. - * 1:The FP16 extension is supported - */ -#define CSR_MMSC_CFG2_ZFH_MASK (0x2U) -#define CSR_MMSC_CFG2_ZFH_SHIFT (1U) -#define CSR_MMSC_CFG2_ZFH_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_ZFH_MASK) >> CSR_MMSC_CFG2_ZFH_SHIFT) - -/* - * BF16CVT (RO) - * - * Indicates if the BFLOAT16 conversion extension - * is supported or not. - * 0:The BFLOAT16 conversion extension is not supported - * 1:The BFLOAT16 conversion extension is supported - */ -#define CSR_MMSC_CFG2_BF16CVT_MASK (0x1U) -#define CSR_MMSC_CFG2_BF16CVT_SHIFT (0U) -#define CSR_MMSC_CFG2_BF16CVT_GET(x) (((uint32_t)(x) & CSR_MMSC_CFG2_BF16CVT_MASK) >> CSR_MMSC_CFG2_BF16CVT_SHIFT) - - -#endif /* HPM_CSR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_dmamux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_dmamux_src.h deleted file mode 100644 index c3b9883aac0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_dmamux_src.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_SRC_H -#define HPM_DMAMUX_SRC_H - -/* dma mux definitions */ -#define HPM_DMA_SRC_SPI0_RX (0x0UL) -#define HPM_DMA_SRC_SPI0_TX (0x1UL) -#define HPM_DMA_SRC_SPI1_RX (0x2UL) -#define HPM_DMA_SRC_SPI1_TX (0x3UL) -#define HPM_DMA_SRC_SPI2_RX (0x4UL) -#define HPM_DMA_SRC_SPI2_TX (0x5UL) -#define HPM_DMA_SRC_SPI3_RX (0x6UL) -#define HPM_DMA_SRC_SPI3_TX (0x7UL) -#define HPM_DMA_SRC_UART0_RX (0x8UL) -#define HPM_DMA_SRC_UART0_TX (0x9UL) -#define HPM_DMA_SRC_UART1_RX (0xAUL) -#define HPM_DMA_SRC_UART1_TX (0xBUL) -#define HPM_DMA_SRC_UART2_RX (0xCUL) -#define HPM_DMA_SRC_UART2_TX (0xDUL) -#define HPM_DMA_SRC_UART3_RX (0xEUL) -#define HPM_DMA_SRC_UART3_TX (0xFUL) -#define HPM_DMA_SRC_UART4_RX (0x10UL) -#define HPM_DMA_SRC_UART4_TX (0x11UL) -#define HPM_DMA_SRC_UART5_RX (0x12UL) -#define HPM_DMA_SRC_UART5_TX (0x13UL) -#define HPM_DMA_SRC_UART6_RX (0x14UL) -#define HPM_DMA_SRC_UART6_TX (0x15UL) -#define HPM_DMA_SRC_UART7_RX (0x16UL) -#define HPM_DMA_SRC_UART7_TX (0x17UL) -#define HPM_DMA_SRC_I2C0 (0x18UL) -#define HPM_DMA_SRC_I2C1 (0x19UL) -#define HPM_DMA_SRC_I2C2 (0x1AUL) -#define HPM_DMA_SRC_I2C3 (0x1BUL) -#define HPM_DMA_SRC_SPI4_RX (0x1CUL) -#define HPM_DMA_SRC_SPI4_TX (0x1DUL) -#define HPM_DMA_SRC_SPI5_RX (0x1EUL) -#define HPM_DMA_SRC_SPI5_TX (0x1FUL) -#define HPM_DMA_SRC_SPI6_RX (0x20UL) -#define HPM_DMA_SRC_SPI6_TX (0x21UL) -#define HPM_DMA_SRC_SPI7_RX (0x22UL) -#define HPM_DMA_SRC_SPI7_TX (0x23UL) -#define HPM_DMA_SRC_UART8_RX (0x24UL) -#define HPM_DMA_SRC_UART8_TX (0x25UL) -#define HPM_DMA_SRC_UART9_RX (0x26UL) -#define HPM_DMA_SRC_UART9_TX (0x27UL) -#define HPM_DMA_SRC_UART10_RX (0x28UL) -#define HPM_DMA_SRC_UART10_TX (0x29UL) -#define HPM_DMA_SRC_UART11_RX (0x2AUL) -#define HPM_DMA_SRC_UART11_TX (0x2BUL) -#define HPM_DMA_SRC_UART12_RX (0x2CUL) -#define HPM_DMA_SRC_UART12_TX (0x2DUL) -#define HPM_DMA_SRC_UART13_RX (0x2EUL) -#define HPM_DMA_SRC_UART13_TX (0x2FUL) -#define HPM_DMA_SRC_UART14_RX (0x30UL) -#define HPM_DMA_SRC_UART14_TX (0x31UL) -#define HPM_DMA_SRC_UART15_RX (0x32UL) -#define HPM_DMA_SRC_UART15_TX (0x33UL) -#define HPM_DMA_SRC_I2C4 (0x34UL) -#define HPM_DMA_SRC_I2C5 (0x35UL) -#define HPM_DMA_SRC_I2C6 (0x36UL) -#define HPM_DMA_SRC_I2C7 (0x37UL) -#define HPM_DMA_SRC_MCAN0 (0x38UL) -#define HPM_DMA_SRC_MCAN1 (0x39UL) -#define HPM_DMA_SRC_MCAN2 (0x3AUL) -#define HPM_DMA_SRC_MCAN3 (0x3BUL) -#define HPM_DMA_SRC_MCAN4 (0x3CUL) -#define HPM_DMA_SRC_MCAN5 (0x3DUL) -#define HPM_DMA_SRC_MCAN6 (0x3EUL) -#define HPM_DMA_SRC_MCAN7 (0x3FUL) -#define HPM_DMA_SRC_I2S0_RX (0x40UL) -#define HPM_DMA_SRC_I2S0_TX (0x41UL) -#define HPM_DMA_SRC_I2S1_RX (0x42UL) -#define HPM_DMA_SRC_I2S1_TX (0x43UL) -#define HPM_DMA_SRC_GPTMR0_0 (0x44UL) -#define HPM_DMA_SRC_GPTMR0_1 (0x45UL) -#define HPM_DMA_SRC_GPTMR0_2 (0x46UL) -#define HPM_DMA_SRC_GPTMR0_3 (0x47UL) -#define HPM_DMA_SRC_GPTMR1_0 (0x48UL) -#define HPM_DMA_SRC_GPTMR1_1 (0x49UL) -#define HPM_DMA_SRC_GPTMR1_2 (0x4AUL) -#define HPM_DMA_SRC_GPTMR1_3 (0x4BUL) -#define HPM_DMA_SRC_GPTMR2_0 (0x4CUL) -#define HPM_DMA_SRC_GPTMR2_1 (0x4DUL) -#define HPM_DMA_SRC_GPTMR2_2 (0x4EUL) -#define HPM_DMA_SRC_GPTMR2_3 (0x4FUL) -#define HPM_DMA_SRC_GPTMR3_0 (0x50UL) -#define HPM_DMA_SRC_GPTMR3_1 (0x51UL) -#define HPM_DMA_SRC_GPTMR3_2 (0x52UL) -#define HPM_DMA_SRC_GPTMR3_3 (0x53UL) -#define HPM_DMA_SRC_GPTMR4_0 (0x54UL) -#define HPM_DMA_SRC_GPTMR4_1 (0x55UL) -#define HPM_DMA_SRC_GPTMR4_2 (0x56UL) -#define HPM_DMA_SRC_GPTMR4_3 (0x57UL) -#define HPM_DMA_SRC_GPTMR5_0 (0x58UL) -#define HPM_DMA_SRC_GPTMR5_1 (0x59UL) -#define HPM_DMA_SRC_GPTMR5_2 (0x5AUL) -#define HPM_DMA_SRC_GPTMR5_3 (0x5BUL) -#define HPM_DMA_SRC_GPTMR6_0 (0x5CUL) -#define HPM_DMA_SRC_GPTMR6_1 (0x5DUL) -#define HPM_DMA_SRC_GPTMR6_2 (0x5EUL) -#define HPM_DMA_SRC_GPTMR6_3 (0x5FUL) -#define HPM_DMA_SRC_GPTMR7_0 (0x60UL) -#define HPM_DMA_SRC_GPTMR7_1 (0x61UL) -#define HPM_DMA_SRC_GPTMR7_2 (0x62UL) -#define HPM_DMA_SRC_GPTMR7_3 (0x63UL) -#define HPM_DMA_SRC_MOT_0 (0x64UL) -#define HPM_DMA_SRC_MOT_1 (0x65UL) -#define HPM_DMA_SRC_MOT_2 (0x66UL) -#define HPM_DMA_SRC_MOT_3 (0x67UL) -#define HPM_DMA_SRC_MOT_4 (0x68UL) -#define HPM_DMA_SRC_MOT_5 (0x69UL) -#define HPM_DMA_SRC_MOT_6 (0x6AUL) -#define HPM_DMA_SRC_MOT_7 (0x6BUL) -#define HPM_DMA_SRC_ACMP0_0 (0x6CUL) -#define HPM_DMA_SRC_ACMP0_1 (0x6DUL) -#define HPM_DMA_SRC_ACMP1_0 (0x6EUL) -#define HPM_DMA_SRC_ACMP1_1 (0x6FUL) -#define HPM_DMA_SRC_ACMP2_0 (0x70UL) -#define HPM_DMA_SRC_ACMP2_1 (0x71UL) -#define HPM_DMA_SRC_ACMP3_0 (0x72UL) -#define HPM_DMA_SRC_ACMP3_1 (0x73UL) -#define HPM_DMA_SRC_XPI0_RX (0x74UL) -#define HPM_DMA_SRC_XPI0_TX (0x75UL) -#define HPM_DMA_SRC_ESC_SYNC0 (0x76UL) -#define HPM_DMA_SRC_ESC_SYNC1 (0x77UL) - - - -#endif /* HPM_DMAMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_enet_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_enet_soc_drv.h deleted file mode 100644 index fadee53a327..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_enet_soc_drv.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_ENET_SOC_DRV_H -#define HPM_ENET_SOC_DRV_H - -#include "hpm_soc.h" - -#if defined __cplusplus -extern "C" { -#endif - -static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_PHY_INF_SEL_MASK; - ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 |= ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - ptr->CTRL0 &= ~(ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK); - ptr->CTRL0 |= ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(tx_delay) | ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(rx_delay); - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal) -{ - hpm_stat_t stat = status_success; - - /* use an internal PLL clock as reference clock for rmii mode */ - if (ptr == HPM_ENET0) { - if (internal == true) { - /* use a pll clock */ - ptr->CTRL2 |= ENET_CTRL2_ENET0_REFCLK_OE_MASK | ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else { - /* use an external clock as reference clock for rmii mode */ - ptr->CTRL2 |= ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */ - } - } else { - return status_invalid_argument; - } - - return stat; -} - -static inline hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr) -{ - hpm_stat_t stat = status_success; - - if (ptr == HPM_ENET0) { - /* use an internal PLL clock for rgmii mode */ - ptr->CTRL2 &= ~ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; - } else { - return status_invalid_argument; - } - - return stat; -} - -#if defined __cplusplus -} /* __cplusplus */ -#endif - -#endif /* HPM_ENET_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_gpiom_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_gpiom_soc_drv.h deleted file mode 100644 index 59357c78aaa..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_gpiom_soc_drv.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_GPIOM_SOC_DRV_H -#define HPM_GPIOM_SOC_DRV_H - -/** - * @addtogroup gpiom_interface GPIOM driver APIs - * @{ - */ - -/* @brief gpiom control module */ -typedef enum gpiom_gpio { - gpiom_soc_gpio0 = 0, - gpiom_soc_gpio1 = 1, - gpiom_core0_fast = 2, - gpiom_core1_fast = 3, -} gpiom_gpio_t; - -/** - * @} - */ - -#endif /* HPM_GPIOM_SOC_DRV_H */ - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_interrupt.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_interrupt.h deleted file mode 100644 index 5a52f3a0fc6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_interrupt.h +++ /dev/null @@ -1,1205 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_INTERRUPT_H -#define HPM_INTERRUPT_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_plic_drv.h" - -/** - * @brief INTERRUPT driver APIs - * @defgroup irq_interface INTERRUPT driver APIs - * @{ - */ - -#define M_MODE 0 /*!< Machine mode */ -#define S_MODE 1 /*!< Supervisor mode */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Machine mode API: these APIs are supposed to be called at machine mode */ - -/** - * @brief Enable global IRQ with mask - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return mstatus - * - * @param[in] mask interrupt mask to be disabled - * @retval current mstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask) -{ - set_csr(CSR_MSTATUS, mask); -} - -/** - * @brief Enable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void) -{ - set_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Disable IRQ from interrupt controller - * - */ -ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ - */ -ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void) -{ - set_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK); -} - -/** - * @brief Delegate IRQ handling - * - * @param[in] mask interrupt mask to be delegated - */ -ATTR_ALWAYS_INLINE static inline void delegate_irq(uint32_t mask) -{ - set_csr(CSR_MIDELEG, mask); -} - -/** - * @brief Undelegate IRQ handling - * - * @param[in] mask interrupt mask to be undelegated - */ -ATTR_ALWAYS_INLINE static inline void undelegate_irq(uint32_t mask) -{ - clear_csr(CSR_MIDELEG, mask); -} - - -/* Supervisor mode API: these APIs are supposed to be called at supervisor mode */ - -/** - * @brief Enable global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be enabaled - */ -ATTR_ALWAYS_INLINE static inline void enable_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable global IRQ with mask and return sstatus for supervisor mode - * - * @param[in] mask interrupt mask to be disabled - * @retval current sstatus value before irq mask is disabled - */ -ATTR_ALWAYS_INLINE static inline uint32_t disable_s_global_irq(uint32_t mask) -{ - return read_clear_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Restore global IRQ with mask for supervisor mode - * - * @param[in] mask interrupt mask to be restored - */ -ATTR_ALWAYS_INLINE static inline void restore_s_global_irq(uint32_t mask) -{ - set_csr(CSR_SSTATUS, mask); -} - -/** - * @brief Disable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_irq_from_intc(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable IRQ from interrupt controller for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void enable_s_irq_from_intc(void) -{ - set_csr(CSR_SIE, CSR_SIE_SEIE_MASK); -} - -/** - * @brief Enable machine timer IRQ for supervisor mode - */ -ATTR_ALWAYS_INLINE static inline void enable_s_mchtmr_irq(void) -{ - set_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - -/** - * @brief Disable machine timer IRQ - * - */ -ATTR_ALWAYS_INLINE static inline void disable_s_mchtmr_irq(void) -{ - clear_csr(CSR_SIE, CSR_SIE_STIE_MASK); -} - - -/* - * CPU Machine SWI control - * - * Machine SWI (MSIP) is connected to PLICSW irq 1. - */ -#define PLICSWI 1 - -/** - * @brief Initialize software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void) -{ - __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - - -/** - * @brief Enable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void) -{ - set_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Disable software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void) -{ - clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK); -} - - -/** - * @brief Trigger software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void) -{ - __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI); -} - -/** - * @brief Claim software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void) -{ - __plic_claim_irq(HPM_PLICSW_BASE, 0); -} - -/** - * @brief Complete software interrupt - * - */ -ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void) -{ - __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI); -} - -/* - * @brief Enable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Disable IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq) - -#define intc_m_set_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold) - -/* - * @brief Complete IRQ for machine mode - * - * @param[in] irq Interrupt number - */ -#define intc_m_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq) - -/* - * @brief Claim IRQ for machine mode - * - */ -#define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE) - -/* - * @brief Enable IRQ for machine mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_m_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_m_enable_irq(irq); \ - } while (0) - - - -/* Supervisor mode */ - -/** - * @brief Enable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_enable_swi(void) -{ - set_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Disable software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_disable_swi(void) -{ - clear_csr(CSR_SIE, CSR_SIE_SSIE_MASK); -} - - -/** - * @brief Trigger software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_trigger_swi(void) -{ - set_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - - -/** - * @brief Complete software interrupt for supervisor mode - * - */ -ATTR_ALWAYS_INLINE static inline void intc_s_complete_swi(void) -{ - clear_csr(CSR_SIP, CSR_SIP_SSIP_MASK); -} - -/* - * @brief Enable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_enable_irq(irq) \ - intc_enable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Disable IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_disable_irq(irq) \ - intc_disable_irq(HPM_PLIC_TARGET_S_MODE, irq) - -#define intc_set_s_threshold(threshold) \ - intc_set_threshold(HPM_PLIC_TARGET_S_MODE, threshold) - -/* - * @brief Complete IRQ for supervisor mode - * - * @param[in] irq Interrupt number - */ -#define intc_s_complete_irq(irq) \ - intc_complete_irq(HPM_PLIC_TARGET_S_MODE, irq) - -/* - * @brief Claim IRQ for supervisor mode - * - */ -#define intc_s_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_S_MODE) - -/* - * @brief Enable IRQ for supervisor mode with priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -#define intc_s_enable_irq_with_priority(irq, priority) \ - do { \ - intc_set_irq_priority(irq, priority); \ - intc_s_enable_irq(irq); \ - } while (0) - - -/* - * @brief Enable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq) -{ - __plic_enable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt priority - * - * @param[in] irq Interrupt number - * @param[in] priority Priority of interrupt - */ -ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority) -{ - __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority); -} - -/** - * @brief Disable specific interrupt - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - */ -ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq) -{ - __plic_disable_irq(HPM_PLIC_BASE, target, irq); -} - -/** - * @brief Set interrupt threshold - * - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - */ -ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold) -{ - __plic_set_threshold(HPM_PLIC_BASE, target, threshold); -} - -/** - * @brief Claim IRQ - * - * @param[in] target Target to handle specific interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target) -{ - return __plic_claim_irq(HPM_PLIC_BASE, target); -} - -/** - * @brief Complete IRQ - * - * @param[in] target Target to handle specific interrupt - * @param[in] irq Specific IRQ to be completed - * - */ -ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq) -{ - __plic_complete_irq(HPM_PLIC_BASE, target, irq); -} - -/* - * Vectored based irq install and uninstall - */ -/* Machine mode */ -extern int __vector_table[]; -extern void default_irq_entry(void); - -/** - * @brief Install ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr) -{ - __vector_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq) -{ - __vector_table[irq] = (int) default_irq_entry; -} - -/* Supervisor mode */ -extern int __vector_s_table[]; -extern void default_s_irq_entry(void); -/** - * @brief Install ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * @param[in] isr Interrupt service routine - * - */ -ATTR_ALWAYS_INLINE static inline void install_s_isr(uint32_t irq, uint32_t isr) -{ - __vector_s_table[irq] = isr; -} - -/** - * @brief Uninstall ISR for certain IRQ for ram based vector table for supervisor mode - * - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void uninstall_s_isr(uint32_t irq) -{ - __vector_s_table[irq] = (int) default_s_irq_entry; -} - - -/* - * Inline nested irq entry/exit macros - */ -/* - * @brief Save CSR - * @param[in] r Target CSR to be saved - */ -#define SAVE_CSR(r) register long __##r = read_csr(r); - -/* - * @brief Restore macro - * - * @param[in] r Target CSR to be restored - */ -#define RESTORE_CSR(r) write_csr(r, __##r); - -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH -#define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS) -#define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS) -#else -#define SAVE_MXSTATUS() -#define RESTORE_MXSTATUS() -#endif - -#ifdef __riscv_flen -#define SAVE_FCSR() register int __fcsr = read_fcsr(); -#define RESTORE_FCSR() write_fcsr(__fcsr); -#else -#define SAVE_FCSR() -#define RESTORE_FCSR() -#endif - -#ifdef __riscv_dsp -#define SAVE_UCODE() SAVE_CSR(CSR_UCODE) -#define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE) -#else -#define SAVE_UCODE() -#define RESTORE_UCODE() -#endif - -#ifdef __riscv_flen -#if __riscv_flen == 32 -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 FPU caller registers +FCSR + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20)) -#else /* __riscv_flen = 64 */ -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + 20 DFPU caller + FCSR registers + UCODE (DSP) */ -#define CONTEXT_REG_NUM (4 * (16 + 4 + 20 * 2)) -#endif - -#else -/* RV32I caller registers + MCAUSE + MEPC + MSTATUS +MXSTATUS + UCODE (DSP)*/ -#define CONTEXT_REG_NUM (4 * (16 + 4)) -#endif - -#ifdef __riscv_flen -/* - * Save FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#if __riscv_flen == 32 -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4\n\ - c.fswsp ft1, 21*4 \n\ - c.fswsp ft2, 22*4 \n\ - c.fswsp ft3, 23*4 \n\ - c.fswsp ft4, 24*4 \n\ - c.fswsp ft5, 25*4 \n\ - c.fswsp ft6, 26*4 \n\ - c.fswsp ft7, 27*4 \n\ - c.fswsp fa0, 28*4 \n\ - c.fswsp fa1, 29*4 \n\ - c.fswsp fa2, 30*4 \n\ - c.fswsp fa3, 31*4 \n\ - c.fswsp fa4, 32*4 \n\ - c.fswsp fa5, 33*4 \n\ - c.fswsp fa6, 34*4 \n\ - c.fswsp fa7, 35*4 \n\ - c.fswsp ft8, 36*4 \n\ - c.fswsp ft9, 37*4 \n\ - c.fswsp ft10, 38*4 \n\ - c.fswsp ft11, 39*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4\n\ - c.flwsp ft1, 21*4 \n\ - c.flwsp ft2, 22*4 \n\ - c.flwsp ft3, 23*4 \n\ - c.flwsp ft4, 24*4 \n\ - c.flwsp ft5, 25*4 \n\ - c.flwsp ft6, 26*4 \n\ - c.flwsp ft7, 27*4 \n\ - c.flwsp fa0, 28*4 \n\ - c.flwsp fa1, 29*4 \n\ - c.flwsp fa2, 30*4 \n\ - c.flwsp fa3, 31*4 \n\ - c.flwsp fa4, 32*4 \n\ - c.flwsp fa5, 33*4 \n\ - c.flwsp fa6, 34*4 \n\ - c.flwsp fa7, 35*4 \n\ - c.flwsp ft8, 36*4 \n\ - c.flwsp ft9, 37*4 \n\ - c.flwsp ft10, 38*4 \n\ - c.flwsp ft11, 39*4 \n");\ -} -#else /* __ICCRISCV__ not defined */ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fswsp ft0, 20*4(sp)\n\ - c.fswsp ft1, 21*4(sp) \n\ - c.fswsp ft2, 22*4(sp) \n\ - c.fswsp ft3, 23*4(sp) \n\ - c.fswsp ft4, 24*4(sp) \n\ - c.fswsp ft5, 25*4(sp) \n\ - c.fswsp ft6, 26*4(sp) \n\ - c.fswsp ft7, 27*4(sp) \n\ - c.fswsp fa0, 28*4(sp) \n\ - c.fswsp fa1, 29*4(sp) \n\ - c.fswsp fa2, 30*4(sp) \n\ - c.fswsp fa3, 31*4(sp) \n\ - c.fswsp fa4, 32*4(sp) \n\ - c.fswsp fa5, 33*4(sp) \n\ - c.fswsp fa6, 34*4(sp) \n\ - c.fswsp fa7, 35*4(sp) \n\ - c.fswsp ft8, 36*4(sp) \n\ - c.fswsp ft9, 37*4(sp) \n\ - c.fswsp ft10, 38*4(sp) \n\ - c.fswsp ft11, 39*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.flwsp ft0, 20*4(sp)\n\ - c.flwsp ft1, 21*4(sp) \n\ - c.flwsp ft2, 22*4(sp) \n\ - c.flwsp ft3, 23*4(sp) \n\ - c.flwsp ft4, 24*4(sp) \n\ - c.flwsp ft5, 25*4(sp) \n\ - c.flwsp ft6, 26*4(sp) \n\ - c.flwsp ft7, 27*4(sp) \n\ - c.flwsp fa0, 28*4(sp) \n\ - c.flwsp fa1, 29*4(sp) \n\ - c.flwsp fa2, 30*4(sp) \n\ - c.flwsp fa3, 31*4(sp) \n\ - c.flwsp fa4, 32*4(sp) \n\ - c.flwsp fa5, 33*4(sp) \n\ - c.flwsp fa6, 34*4(sp) \n\ - c.flwsp fa7, 35*4(sp) \n\ - c.flwsp ft8, 36*4(sp) \n\ - c.flwsp ft9, 37*4(sp) \n\ - c.flwsp ft10, 38*4(sp) \n\ - c.flwsp ft11, 39*4(sp) \n");\ -} -#endif -#else /*__riscv_flen == 64*/ -#ifdef __ICCRISCV__ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4\n\ - c.fsdsp ft1, 22*4 \n\ - c.fsdsp ft2, 24*4 \n\ - c.fsdsp ft3, 26*4 \n\ - c.fsdsp ft4, 28*4 \n\ - c.fsdsp ft5, 30*4 \n\ - c.fsdsp ft6, 32*4 \n\ - c.fsdsp ft7, 34*4 \n\ - c.fsdsp fa0, 36*4 \n\ - c.fsdsp fa1, 38*4 \n\ - c.fsdsp fa2, 40*4 \n\ - c.fsdsp fa3, 42*4 \n\ - c.fsdsp fa4, 44*4 \n\ - c.fsdsp fa5, 46*4 \n\ - c.fsdsp fa6, 48*4 \n\ - c.fsdsp fa7, 50*4 \n\ - c.fsdsp ft8, 52*4 \n\ - c.fsdsp ft9, 54*4 \n\ - c.fsdsp ft10, 56*4 \n\ - c.fsdsp ft11, 58*4 \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4\n\ - c.fldsp ft1, 22*4 \n\ - c.fldsp ft2, 24*4 \n\ - c.fldsp ft3, 26*4 \n\ - c.fldsp ft4, 28*4 \n\ - c.fldsp ft5, 30*4 \n\ - c.fldsp ft6, 32*4 \n\ - c.fldsp ft7, 34*4 \n\ - c.fldsp fa0, 36*4 \n\ - c.fldsp fa1, 38*4 \n\ - c.fldsp fa2, 40*4 \n\ - c.fldsp fa3, 42*4 \n\ - c.fldsp fa4, 44*4 \n\ - c.fldsp fa5, 46*4 \n\ - c.fldsp fa6, 48*4 \n\ - c.fldsp fa7, 50*4 \n\ - c.fldsp ft8, 52*4 \n\ - c.fldsp ft9, 54*4 \n\ - c.fldsp ft10, 56*4 \n\ - c.fldsp ft11, 58*4 \n");\ -} -#else /*__riscv_flen == 64*/ -#define SAVE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fsdsp ft0, 20*4(sp)\n\ - c.fsdsp ft1, 22*4(sp) \n\ - c.fsdsp ft2, 24*4(sp) \n\ - c.fsdsp ft3, 26*4(sp) \n\ - c.fsdsp ft4, 28*4(sp) \n\ - c.fsdsp ft5, 30*4(sp) \n\ - c.fsdsp ft6, 32*4(sp) \n\ - c.fsdsp ft7, 34*4(sp) \n\ - c.fsdsp fa0, 36*4(sp) \n\ - c.fsdsp fa1, 38*4(sp) \n\ - c.fsdsp fa2, 40*4(sp) \n\ - c.fsdsp fa3, 42*4(sp) \n\ - c.fsdsp fa4, 44*4(sp) \n\ - c.fsdsp fa5, 46*4(sp) \n\ - c.fsdsp fa6, 48*4(sp) \n\ - c.fsdsp fa7, 50*4(sp) \n\ - c.fsdsp ft8, 52*4(sp) \n\ - c.fsdsp ft9, 54*4(sp) \n\ - c.fsdsp ft10, 56*4(sp) \n\ - c.fsdsp ft11, 58*4(sp) \n");\ -} - -/* - * Restore FPU caller registers: - * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack - */ -#define RESTORE_FPU_CONTEXT() { \ - __asm volatile("\n\ - c.fldsp ft0, 20*4(sp)\n\ - c.fldsp ft1, 22*4(sp) \n\ - c.fldsp ft2, 24*4(sp) \n\ - c.fldsp ft3, 26*4(sp) \n\ - c.fldsp ft4, 28*4(sp) \n\ - c.fldsp ft5, 30*4(sp) \n\ - c.fldsp ft6, 32*4(sp) \n\ - c.fldsp ft7, 34*4(sp) \n\ - c.fldsp fa0, 36*4(sp) \n\ - c.fldsp fa1, 38*4(sp) \n\ - c.fldsp fa2, 40*4(sp) \n\ - c.fldsp fa3, 42*4(sp) \n\ - c.fldsp fa4, 44*4(sp) \n\ - c.fldsp fa5, 46*4(sp) \n\ - c.fldsp fa6, 48*4(sp) \n\ - c.fldsp fa7, 50*4(sp) \n\ - c.fldsp ft8, 52*4(sp) \n\ - c.fldsp ft9, 54*4(sp) \n\ - c.fldsp ft10, 56*4(sp) \n\ - c.fldsp ft11, 58*4(sp) \n");\ -} -#endif -#endif -#else -#define SAVE_FPU_CONTEXT() -#define RESTORE_FPU_CONTEXT() -#endif - -#ifdef __ICCRISCV__ -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4 \n\ - c.swsp t0, 1*4 \n\ - c.swsp t1, 2*4 \n\ - c.swsp t2, 3*4 \n\ - c.swsp s0, 4*4 \n\ - c.swsp s1, 5*4 \n\ - c.swsp a0, 6*4 \n\ - c.swsp a1, 7*4 \n\ - c.swsp a2, 8*4 \n\ - c.swsp a3, 9*4 \n\ - c.swsp a4, 10*4 \n\ - c.swsp a5, 11*4 \n\ - c.swsp a6, 12*4 \n\ - c.swsp a7, 13*4 \n\ - c.swsp s2, 14*4 \n\ - c.swsp s3, 15*4 \n\ - c.swsp t3, 16*4 \n\ - c.swsp t4, 17*4 \n\ - c.swsp t5, 18*4 \n\ - c.swsp t6, 19*4"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4 \n\ - c.lwsp t0, 1*4 \n\ - c.lwsp t1, 2*4 \n\ - c.lwsp t2, 3*4 \n\ - c.lwsp s0, 4*4 \n\ - c.lwsp s1, 5*4 \n\ - c.lwsp a0, 6*4 \n\ - c.lwsp a1, 7*4 \n\ - c.lwsp a2, 8*4 \n\ - c.lwsp a3, 9*4 \n\ - c.lwsp a4, 10*4 \n\ - c.lwsp a5, 11*4 \n\ - c.lwsp a6, 12*4 \n\ - c.lwsp a7, 13*4 \n\ - c.lwsp s2, 14*4 \n\ - c.lwsp s3, 15*4 \n\ - c.lwsp t3, 16*4 \n\ - c.lwsp t4, 17*4 \n\ - c.lwsp t5, 18*4 \n\ - c.lwsp t6, 19*4 \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#else -/** - * @brief Save the caller registers based on the RISC-V ABI specification - */ -#define SAVE_CALLER_CONTEXT() { \ - __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\ - __asm volatile("\n\ - c.swsp ra, 0*4(sp) \n\ - c.swsp t0, 1*4(sp) \n\ - c.swsp t1, 2*4(sp) \n\ - c.swsp t2, 3*4(sp) \n\ - c.swsp s0, 4*4(sp) \n\ - c.swsp s1, 5*4(sp) \n\ - c.swsp a0, 6*4(sp) \n\ - c.swsp a1, 7*4(sp) \n\ - c.swsp a2, 8*4(sp) \n\ - c.swsp a3, 9*4(sp) \n\ - c.swsp a4, 10*4(sp) \n\ - c.swsp a5, 11*4(sp) \n\ - c.swsp a6, 12*4(sp) \n\ - c.swsp a7, 13*4(sp) \n\ - c.swsp s2, 14*4(sp) \n\ - c.swsp s3, 15*4(sp) \n\ - c.swsp t3, 16*4(sp) \n\ - c.swsp t4, 17*4(sp) \n\ - c.swsp t5, 18*4(sp) \n\ - c.swsp t6, 19*4(sp)"); \ - SAVE_FPU_CONTEXT(); \ -} - -/** - * @brief Restore the caller registers based on the RISC-V ABI specification - */ -#define RESTORE_CALLER_CONTEXT() { \ - __asm volatile("\n\ - c.lwsp ra, 0*4(sp) \n\ - c.lwsp t0, 1*4(sp) \n\ - c.lwsp t1, 2*4(sp) \n\ - c.lwsp t2, 3*4(sp) \n\ - c.lwsp s0, 4*4(sp) \n\ - c.lwsp s1, 5*4(sp) \n\ - c.lwsp a0, 6*4(sp) \n\ - c.lwsp a1, 7*4(sp) \n\ - c.lwsp a2, 8*4(sp) \n\ - c.lwsp a3, 9*4(sp) \n\ - c.lwsp a4, 10*4(sp) \n\ - c.lwsp a5, 11*4(sp) \n\ - c.lwsp a6, 12*4(sp) \n\ - c.lwsp a7, 13*4(sp) \n\ - c.lwsp s2, 14*4(sp) \n\ - c.lwsp s3, 15*4(sp) \n\ - c.lwsp t3, 16*4(sp) \n\ - c.lwsp t4, 17*4(sp) \n\ - c.lwsp t5, 18*4(sp) \n\ - c.lwsp t6, 19*4(sp) \n");\ - RESTORE_FPU_CONTEXT(); \ - __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\ -} -#endif - -#ifdef __riscv_flen -#define SAVE_FPU_STATE() { \ - __asm volatile("frcsr s1\n"); \ -} - -#define RESTORE_FPU_STATE() { \ - __asm volatile("fscsr s1\n"); \ -} -#else -#define SAVE_FPU_STATE() -#define RESTORE_FPU_STATE() -#endif - -#ifdef __riscv_dsp -/* - * Save DSP context - * NOTE: DSP context registers are stored at word offset 41 in the stack - */ -#define SAVE_DSP_CONTEXT() { \ - __asm volatile("csrrs s0, %0, x0\n" ::"i"(CSR_UCODE):); \ -} -/* - * @brief Restore DSP context - * @note DSP context registers are stored at word offset 41 in the stack - */ -#define RESTORE_DSP_CONTEXT() {\ - __asm volatile("csrw %0, s0\n" ::"i"(CSR_UCODE):); \ -} - -#else -#define SAVE_DSP_CONTEXT() -#define RESTORE_DSP_CONTEXT() -#endif - -/* - * @brief Enter Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define ENTER_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrr s2, mepc \n\ - csrr s3, mstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi mstatus, 8"); \ -} - -/* - * @brief Complete IRQ Handling - */ -#define COMPLETE_IRQ_HANDLING_M(irq_num) { \ - __asm volatile("csrci mstatus, 8"); \ - __asm volatile("lui a4, 0xe4200"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * MCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * MSTATUS = word offset 18 - * MXSTATUS = word offset 19 - */ -#define EXIT_NESTED_IRQ_HANDLING_M() { \ - __asm volatile("\n\ - csrw mstatus, s3 \n\ - csrw mepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - - -#define ENTER_NESTED_IRQ_HANDLING_S() {\ - __asm volatile("\n\ - csrr s2, sepc \n\ - csrr s3, sstatus \n");\ - SAVE_FPU_STATE(); \ - SAVE_DSP_CONTEXT(); \ - __asm volatile("csrsi sstatus, 2"); \ -} -#define COMPLETE_IRQ_HANDLING_S(irq_num) {\ - __asm volatile("csrci sstatus, 2"); \ - __asm volatile("lui a4, 0xe4201"); \ - __asm volatile("li a3, %0" : : "i" (irq_num) :); \ - __asm volatile("sw a3, 4(a4)"); \ -} - -/* - * @brief Exit Nested IRQ Handling at supervisor mode - * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below: - * SCAUSE - word offset 16 (not used in the vectored mode) - * EPC - word offset 17 - * SSTATUS = word offset 18 - */ -#define EXIT_NESTED_IRQ_HANDLING_S() { \ - __asm volatile("\n\ - csrw sstatus, s3 \n\ - csrw sepc, s2 \n");\ - RESTORE_FPU_STATE(); \ - RESTORE_DSP_CONTEXT(); \ -} - -/* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */ -#define NESTED_IRQ_ENTER() \ - SAVE_CSR(CSR_MEPC) \ - SAVE_CSR(CSR_MSTATUS) \ - SAVE_MXSTATUS() \ - SAVE_FCSR() \ - SAVE_UCODE() \ - set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -/* @brief Nested IRQ exit macro : Restore CSRs */ -#define NESTED_IRQ_EXIT() \ - RESTORE_CSR(CSR_MSTATUS) \ - RESTORE_CSR(CSR_MEPC) \ - RESTORE_MXSTATUS() \ - RESTORE_FCSR() \ - RESTORE_UCODE() - -#ifdef __cplusplus -#define EXTERN_C extern "C" -#else -#define EXTERN_C -#endif - -#define ISR_NAME_M(irq_num) default_isr_##irq_num -#define ISR_NAME_S(irq_num) default_isr_s_##irq_num -/** - * @brief Declare an external interrupt handler for machine mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS -#define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector"))); \ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \ -{ \ - isr();\ -} -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) \ -{ \ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_M();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_M(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_M();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("mret\n");\ -} - -/** - * @brief Declare an external interrupt handler for supervisor mode - * - * @param[in] irq_num - IRQ number index - * @param[in] isr - Application IRQ handler function pointer - */ -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_s_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_s_vector")));\ -void ISR_NAME_S(irq_num)(void) {\ - SAVE_CALLER_CONTEXT(); \ - ENTER_NESTED_IRQ_HANDLING_S();\ - __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\ - __asm volatile("jalr t1\n");\ - COMPLETE_IRQ_HANDLING_S(irq_num);\ - EXIT_NESTED_IRQ_HANDLING_S();\ - RESTORE_CALLER_CONTEXT();\ - __asm volatile("fence io, io");\ - __asm volatile("sret\n");\ -} -#endif -#else - -#define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_M(irq_num)(void) { \ - isr(); \ -} - -#define SDK_DECLARE_EXT_ISR_S(irq_num, isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void ISR_NAME_S(irq_num)(void) __attribute__((section(".isr_vector")));\ -void ISR_NAME_S(irq_num)(void) { \ - isr(); \ -} - -#endif - - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_isr(void) {\ - isr();\ -} - -/* Supervisor mode */ - -/** - * @brief Declare machine timer interrupt handler - * - * @param[in] isr - MCHTMR IRQ handler function pointer - */ -#define SDK_DECLARE_MCHTMR_ISR_S(isr) \ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void mchtmr_s_isr(void) __attribute__((section(".isr_vector"))); \ -void mchtmr_s_isr(void) {\ - isr();\ -} - -/** - * @brief Declare machine software interrupt handler - * - * @param[in] isr - SWI IRQ handler function pointer - */ -#define SDK_DECLARE_SWI_ISR_S(isr)\ -void isr(void) __attribute__((section(".isr_vector")));\ -EXTERN_C void swi_s_isr(void) __attribute__((section(".isr_vector"))); \ -void swi_s_isr(void) {\ - isr();\ -} - -#define CSR_MSTATUS_MPP_S_MODE (0x1) -#define MODE_SWITCH_FROM_M(mstatus, mepc, label, mode) \ -do { \ - if (label) { \ - write_csr(mepc, label); \ - } \ - clear_csr(mstatus, CSR_MSTATUS_MPP_MASK); \ - set_csr(mstatus, CSR_MSTATUS_MPP_SET(mode)); \ -} while(0) - -typedef void (*s_mode_entry)(void); - -/** - * @brief Switch mode to supervisor from machine - * - * @param[in] entry - entry point after mode is switched - */ -static inline void switch_to_s_mode(s_mode_entry entry) -{ - write_csr(CSR_SEPC, entry); - MODE_SWITCH_FROM_M(CSR_MSTATUS, CSR_MEPC, entry, CSR_MSTATUS_MPP_S_MODE); - if (entry) { - __asm("mret"); - } -} -#ifdef __cplusplus -} -#endif - -/** - * @} - */ -#endif /* HPM_INTERRUPT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_iomux.h deleted file mode 100644 index 5e6a258ac73..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_iomux.h +++ /dev/null @@ -1,3478 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOMUX_H -#define HPM_IOMUX_H - -/* IOC_PA00_FUNC_CTL function mux definitions */ -#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA00_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA01_FUNC_CTL function mux definitions */ -#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA01_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA02_FUNC_CTL function mux definitions */ -#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA02_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA03_FUNC_CTL function mux definitions */ -#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA03_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA03_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA04_FUNC_CTL function mux definitions */ -#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA04_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA05_FUNC_CTL function mux definitions */ -#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA05_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA05_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA06_FUNC_CTL function mux definitions */ -#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA06_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA07_FUNC_CTL function mux definitions */ -#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA07_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA07_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA08_FUNC_CTL function mux definitions */ -#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA08_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA08_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA08_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA08_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PA09_FUNC_CTL function mux definitions */ -#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA09_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA09_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA09_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA09_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA09_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PA09_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PA10_FUNC_CTL function mux definitions */ -#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA10_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA10_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA10_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA10_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA10_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PA10_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PA10_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PA11_FUNC_CTL function mux definitions */ -#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA11_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA11_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA11_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA11_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA11_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA11_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA11_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PA11_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PA11_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PA12_FUNC_CTL function mux definitions */ -#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA12_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA12_FUNC_CTL_ESC0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA12_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA12_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA12_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA12_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PA12_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PA12_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PA13_FUNC_CTL function mux definitions */ -#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA13_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA13_FUNC_CTL_ESC0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA13_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA13_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PA13_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PA13_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PA13_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PA14_FUNC_CTL function mux definitions */ -#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA14_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA14_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA14_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA14_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PA14_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PA14_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PA15_FUNC_CTL function mux definitions */ -#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA15_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA15_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PA15_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA15_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA16_FUNC_CTL function mux definitions */ -#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA16_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA16_FUNC_CTL_ESC0_P0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA16_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA16_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA16_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA17_FUNC_CTL function mux definitions */ -#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA17_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA17_FUNC_CTL_ESC0_P0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA17_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA17_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA17_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA18_FUNC_CTL function mux definitions */ -#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA18_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA18_FUNC_CTL_ESC0_P0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA18_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA18_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA18_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA19_FUNC_CTL function mux definitions */ -#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA19_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA19_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA19_FUNC_CTL_ESC0_P0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA19_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA19_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA20_FUNC_CTL function mux definitions */ -#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA20_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA20_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA20_FUNC_CTL_ESC0_P0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA20_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA20_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA21_FUNC_CTL function mux definitions */ -#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA21_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA21_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA21_FUNC_CTL_ESC0_P0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA21_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA21_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA21_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA22_FUNC_CTL function mux definitions */ -#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA22_FUNC_CTL_TSW0_P2_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA22_FUNC_CTL_ESC0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA22_FUNC_CTL_ETH0_TXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA22_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA22_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA22_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA23_FUNC_CTL function mux definitions */ -#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA23_FUNC_CTL_TSW0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA23_FUNC_CTL_ESC0_P0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA23_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA23_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA23_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PA23_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PA24_FUNC_CTL function mux definitions */ -#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA24_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA24_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA24_FUNC_CTL_ESC0_P0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA24_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA24_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA25_FUNC_CTL function mux definitions */ -#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA25_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA25_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA25_FUNC_CTL_ESC0_P0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA25_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA25_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA25_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA26_FUNC_CTL function mux definitions */ -#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA26_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA26_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA26_FUNC_CTL_ESC0_P0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA26_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA26_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA27_FUNC_CTL function mux definitions */ -#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA27_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA27_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA27_FUNC_CTL_ESC0_P0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA27_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA28_FUNC_CTL function mux definitions */ -#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA28_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA28_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA28_FUNC_CTL_ESC0_P0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA28_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA29_FUNC_CTL function mux definitions */ -#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PA29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PA29_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA29_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA29_FUNC_CTL_ESC0_P0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA30_FUNC_CTL function mux definitions */ -#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA30_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA30_FUNC_CTL_TSW0_P1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA30_FUNC_CTL_ESC0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA30_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PA31_FUNC_CTL function mux definitions */ -#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PA31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PA31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PA31_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PA31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PA31_FUNC_CTL_TSW0_P1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PA31_FUNC_CTL_ESC0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PA31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PA31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PA31_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PA31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PA31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PA31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB00_FUNC_CTL function mux definitions */ -#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB00_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB00_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB00_FUNC_CTL_ESC0_P0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB00_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB00_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB00_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB01_FUNC_CTL function mux definitions */ -#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB01_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB01_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB01_FUNC_CTL_ESC0_P0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB01_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB01_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB01_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB01_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB02_FUNC_CTL function mux definitions */ -#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB02_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB02_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB02_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB02_FUNC_CTL_ESC0_P0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB02_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB02_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB02_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB02_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB03_FUNC_CTL function mux definitions */ -#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB03_FUNC_CTL_SPI4_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB03_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB03_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB03_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB03_FUNC_CTL_ESC0_P0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB03_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB03_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB04_FUNC_CTL function mux definitions */ -#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB04_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB04_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB04_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB04_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB04_FUNC_CTL_ESC0_P0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB04_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB04_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB05_FUNC_CTL function mux definitions */ -#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB05_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB05_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB05_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB05_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB05_FUNC_CTL_ESC0_P0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB05_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB05_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB06_FUNC_CTL function mux definitions */ -#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB06_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB06_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB06_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB06_FUNC_CTL_ESC0_P0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB06_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB06_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB07_FUNC_CTL function mux definitions */ -#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB07_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB07_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB07_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB07_FUNC_CTL_ESC0_P0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB07_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB07_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB08_FUNC_CTL function mux definitions */ -#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB08_FUNC_CTL_SPI4_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB08_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB08_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB08_FUNC_CTL_ESC0_P0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB08_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB08_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB09_FUNC_CTL function mux definitions */ -#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB09_FUNC_CTL_SPI4_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB09_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB09_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB09_FUNC_CTL_ESC0_P0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB09_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB09_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB10_FUNC_CTL function mux definitions */ -#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB10_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB10_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB10_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB10_FUNC_CTL_ESC0_P0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB10_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB11_FUNC_CTL function mux definitions */ -#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB11_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB11_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PB11_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB11_FUNC_CTL_ESC0_P0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB11_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PB11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB12_FUNC_CTL function mux definitions */ -#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB12_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB12_FUNC_CTL_TSW0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB12_FUNC_CTL_ESC0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB12_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB13_FUNC_CTL function mux definitions */ -#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB13_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB13_FUNC_CTL_TSW0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB13_FUNC_CTL_ESC0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB13_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB14_FUNC_CTL function mux definitions */ -#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB14_FUNC_CTL_SPI4_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB14_FUNC_CTL_TSW0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB14_FUNC_CTL_ESC0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB14_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB15_FUNC_CTL function mux definitions */ -#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB15_FUNC_CTL_SPI4_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB15_FUNC_CTL_TSW0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB15_FUNC_CTL_ESC0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB15_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB16_FUNC_CTL function mux definitions */ -#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB16_FUNC_CTL_TSW0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB16_FUNC_CTL_ESC0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB16_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB16_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB16_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB17_FUNC_CTL function mux definitions */ -#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB17_FUNC_CTL_TSW0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB17_FUNC_CTL_ESC0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB17_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB17_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB17_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB17_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB18_FUNC_CTL function mux definitions */ -#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB18_FUNC_CTL_TSW0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB18_FUNC_CTL_ESC0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB18_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB18_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB18_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB19_FUNC_CTL function mux definitions */ -#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB19_FUNC_CTL_SPI7_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB19_FUNC_CTL_TSW0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB19_FUNC_CTL_ESC0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB19_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB19_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB19_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB20_FUNC_CTL function mux definitions */ -#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB20_FUNC_CTL_SPI6_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB20_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB20_FUNC_CTL_TSW0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB20_FUNC_CTL_ESC0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB20_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB20_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PB20_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB21_FUNC_CTL function mux definitions */ -#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB21_FUNC_CTL_SPI6_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB21_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB21_FUNC_CTL_TSW0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB21_FUNC_CTL_ESC0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB21_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB21_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB22_FUNC_CTL function mux definitions */ -#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB22_FUNC_CTL_SPI6_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB22_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB22_FUNC_CTL_TSW0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB22_FUNC_CTL_ESC0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB22_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB22_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB23_FUNC_CTL function mux definitions */ -#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB23_FUNC_CTL_SPI6_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB23_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PB23_FUNC_CTL_TSW0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PB23_FUNC_CTL_ESC0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB23_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB23_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PB24_FUNC_CTL function mux definitions */ -#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB24_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB24_FUNC_CTL_SPI7_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB24_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB24_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB24_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB24_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PB24_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PB24_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PB24_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PB25_FUNC_CTL function mux definitions */ -#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB25_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB25_FUNC_CTL_SPI7_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB25_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB25_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB25_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB25_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PB25_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PB25_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PB25_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PB26_FUNC_CTL function mux definitions */ -#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB26_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB26_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB26_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB26_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB26_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB26_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PB26_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PB26_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PB26_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PB27_FUNC_CTL function mux definitions */ -#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB27_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB27_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB27_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB27_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB27_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PB27_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PB27_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PB28_FUNC_CTL function mux definitions */ -#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB28_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB28_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB28_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB28_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB28_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB28_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB29_FUNC_CTL function mux definitions */ -#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB29_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB29_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PB29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PB29_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB29_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB29_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB29_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PB29_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PB29_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PB29_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PB30_FUNC_CTL function mux definitions */ -#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB30_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB30_FUNC_CTL_SPI7_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB30_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB30_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB30_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB30_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PB31_FUNC_CTL function mux definitions */ -#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PB31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PB31_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PB31_FUNC_CTL_SPI7_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PB31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PB31_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PB31_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PB31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PB31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PB31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PB31_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PB31_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PB31_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PB31_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PC00_FUNC_CTL function mux definitions */ -#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC00_FUNC_CTL_ESC0_GPI_63 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC00_FUNC_CTL_ESC0_GPO_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC00_FUNC_CTL_FEMC_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC00_FUNC_CTL_PPI0_DQ_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC00_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC00_FUNC_CTL_ESC0_GPI_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC01_FUNC_CTL function mux definitions */ -#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC01_FUNC_CTL_ESC0_GPI_62 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC01_FUNC_CTL_ESC0_GPO_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC01_FUNC_CTL_FEMC_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC01_FUNC_CTL_PPI0_DQ_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC01_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC01_FUNC_CTL_ESC0_GPI_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC02_FUNC_CTL function mux definitions */ -#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC02_FUNC_CTL_ESC0_GPI_61 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC02_FUNC_CTL_ESC0_GPO_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC02_FUNC_CTL_FEMC_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC02_FUNC_CTL_PPI0_DQ_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC02_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC02_FUNC_CTL_ESC0_GPI_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC02_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC03_FUNC_CTL function mux definitions */ -#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC03_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC03_FUNC_CTL_ESC0_GPI_60 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC03_FUNC_CTL_ESC0_GPO_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC03_FUNC_CTL_FEMC_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC03_FUNC_CTL_PPI0_DQ_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC03_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC03_FUNC_CTL_ESC0_GPI_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC04_FUNC_CTL function mux definitions */ -#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC04_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC04_FUNC_CTL_ESC0_GPI_59 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC04_FUNC_CTL_ESC0_GPO_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC04_FUNC_CTL_FEMC_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC04_FUNC_CTL_PPI0_DQ_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC04_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC04_FUNC_CTL_ESC0_GPI_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC05_FUNC_CTL function mux definitions */ -#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC05_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC05_FUNC_CTL_ESC0_GPI_58 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC05_FUNC_CTL_ESC0_GPO_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC05_FUNC_CTL_FEMC_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC05_FUNC_CTL_PPI0_DQ_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC05_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC05_FUNC_CTL_ESC0_GPI_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC06_FUNC_CTL function mux definitions */ -#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC06_FUNC_CTL_ESC0_GPI_57 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC06_FUNC_CTL_ESC0_GPO_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC06_FUNC_CTL_FEMC_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC06_FUNC_CTL_PPI0_DQ_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC06_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC06_FUNC_CTL_ESC0_GPI_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC07_FUNC_CTL function mux definitions */ -#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC07_FUNC_CTL_ESC0_GPI_56 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC07_FUNC_CTL_ESC0_GPO_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC07_FUNC_CTL_FEMC_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC07_FUNC_CTL_PPI0_DQ_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC07_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC07_FUNC_CTL_ESC0_GPI_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC08_FUNC_CTL function mux definitions */ -#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC08_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC08_FUNC_CTL_ESC0_GPI_55 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC08_FUNC_CTL_ESC0_GPO_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC08_FUNC_CTL_FEMC_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC08_FUNC_CTL_PPI0_DQ_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC08_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC08_FUNC_CTL_ESC0_GPI_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PC09_FUNC_CTL function mux definitions */ -#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC09_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC09_FUNC_CTL_ESC0_GPI_54 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC09_FUNC_CTL_ESC0_GPO_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC09_FUNC_CTL_FEMC_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC09_FUNC_CTL_PPI0_DQ_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC09_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC09_FUNC_CTL_ESC0_GPI_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC09_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC10_FUNC_CTL function mux definitions */ -#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC10_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC10_FUNC_CTL_ESC0_GPI_53 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC10_FUNC_CTL_ESC0_GPO_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC10_FUNC_CTL_FEMC_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC10_FUNC_CTL_PPI0_DQ_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC10_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC10_FUNC_CTL_ESC0_GPI_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC10_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC11_FUNC_CTL function mux definitions */ -#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC11_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC11_FUNC_CTL_ESC0_GPI_52 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC11_FUNC_CTL_ESC0_GPO_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC11_FUNC_CTL_FEMC_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC11_FUNC_CTL_PPI0_DQ_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC11_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC11_FUNC_CTL_ESC0_GPI_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC11_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC12_FUNC_CTL function mux definitions */ -#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC12_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC12_FUNC_CTL_ESC0_GPI_51 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC12_FUNC_CTL_ESC0_GPO_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC12_FUNC_CTL_FEMC_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC12_FUNC_CTL_PPI0_DM_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC12_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC12_FUNC_CTL_ESC0_GPI_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC12_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC13_FUNC_CTL function mux definitions */ -#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC13_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC13_FUNC_CTL_ESC0_GPI_50 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC13_FUNC_CTL_ESC0_GPO_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC13_FUNC_CTL_FEMC_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC13_FUNC_CTL_PPI0_DQ_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC13_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC13_FUNC_CTL_ESC0_GPI_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC13_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC13_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC13_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC14_FUNC_CTL function mux definitions */ -#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC14_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC14_FUNC_CTL_ESC0_GPI_49 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC14_FUNC_CTL_ESC0_GPO_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC14_FUNC_CTL_FEMC_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC14_FUNC_CTL_PPI0_DQ_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC14_FUNC_CTL_ESC0_GPI_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC14_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC14_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC14_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC15_FUNC_CTL function mux definitions */ -#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC15_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC15_FUNC_CTL_ESC0_GPI_48 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC15_FUNC_CTL_ESC0_GPO_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC15_FUNC_CTL_FEMC_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC15_FUNC_CTL_PPI0_DM_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC15_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC15_FUNC_CTL_ESC0_GPI_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC15_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC15_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC16_FUNC_CTL function mux definitions */ -#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC16_FUNC_CTL_ESC0_GPI_47 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC16_FUNC_CTL_ESC0_GPO_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC16_FUNC_CTL_FEMC_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC16_FUNC_CTL_PPI0_DQ_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC16_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) -#define IOC_PC16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC16_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC17_FUNC_CTL function mux definitions */ -#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC17_FUNC_CTL_ESC0_GPI_46 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC17_FUNC_CTL_ESC0_GPO_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC17_FUNC_CTL_FEMC_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC17_FUNC_CTL_PPI0_DQ_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC17_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PC18_FUNC_CTL function mux definitions */ -#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC18_FUNC_CTL_ESC0_GPI_45 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC18_FUNC_CTL_ESC0_GPO_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC18_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC18_FUNC_CTL_PPI0_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC18_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC18_FUNC_CTL_XPI_SLV_RDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC19_FUNC_CTL function mux definitions */ -#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC19_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC19_FUNC_CTL_ESC0_GPI_44 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC19_FUNC_CTL_ESC0_GPO_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC19_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC19_FUNC_CTL_PPI0_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC19_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC19_FUNC_CTL_XPI_SLV_ADQ_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC20_FUNC_CTL function mux definitions */ -#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC20_FUNC_CTL_ESC0_GPI_43 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC20_FUNC_CTL_ESC0_GPO_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC20_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC20_FUNC_CTL_PPI0_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC20_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC20_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC20_FUNC_CTL_XPI_SLV_ADQ_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC21_FUNC_CTL function mux definitions */ -#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC21_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC21_FUNC_CTL_ESC0_GPI_42 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC21_FUNC_CTL_ESC0_GPO_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC21_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC21_FUNC_CTL_PPI0_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC21_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC21_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC21_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC21_FUNC_CTL_XPI_SLV_ADQ_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC22_FUNC_CTL function mux definitions */ -#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC22_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC22_FUNC_CTL_ESC0_GPI_41 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC22_FUNC_CTL_ESC0_GPO_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC22_FUNC_CTL_FEMC_SRDY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC22_FUNC_CTL_PPI0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC22_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC22_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC22_FUNC_CTL_XPI_SLV_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PC23_FUNC_CTL function mux definitions */ -#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC23_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC23_FUNC_CTL_ESC0_GPI_40 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC23_FUNC_CTL_ESC0_GPO_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC23_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC23_FUNC_CTL_PPI0_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC23_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC23_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC24_FUNC_CTL function mux definitions */ -#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC24_FUNC_CTL_SPI2_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC24_FUNC_CTL_ESC0_GPI_39 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC24_FUNC_CTL_ESC0_GPO_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC24_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC24_FUNC_CTL_PPI0_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC25_FUNC_CTL function mux definitions */ -#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC25_FUNC_CTL_SPI2_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC25_FUNC_CTL_ESC0_GPI_38 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC25_FUNC_CTL_ESC0_GPO_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC25_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC25_FUNC_CTL_PPI0_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PC26_FUNC_CTL function mux definitions */ -#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC26_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC26_FUNC_CTL_ESC0_GPI_37 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC26_FUNC_CTL_ESC0_GPO_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC26_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC26_FUNC_CTL_PPI0_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC27_FUNC_CTL function mux definitions */ -#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC27_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC27_FUNC_CTL_ESC0_GPI_36 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC27_FUNC_CTL_ESC0_GPO_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC27_FUNC_CTL_FEMC_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC27_FUNC_CTL_PPI0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC27_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PC28_FUNC_CTL function mux definitions */ -#define IOC_PC28_FUNC_CTL_GPIO_C_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC28_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC28_FUNC_CTL_ESC0_GPI_35 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC28_FUNC_CTL_ESC0_GPO_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC28_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC28_FUNC_CTL_PPI0_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC28_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PC29_FUNC_CTL function mux definitions */ -#define IOC_PC29_FUNC_CTL_GPIO_C_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PC29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PC29_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC29_FUNC_CTL_ESC0_GPI_34 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC29_FUNC_CTL_ESC0_GPO_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC29_FUNC_CTL_FEMC_SCLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC29_FUNC_CTL_PPI0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC29_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC29_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC30_FUNC_CTL function mux definitions */ -#define IOC_PC30_FUNC_CTL_GPIO_C_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC30_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC30_FUNC_CTL_ESC0_GPI_33 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC30_FUNC_CTL_ESC0_GPO_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC30_FUNC_CTL_FEMC_SCS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC30_FUNC_CTL_PPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC30_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PC30_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PC31_FUNC_CTL function mux definitions */ -#define IOC_PC31_FUNC_CTL_GPIO_C_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PC31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PC31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PC31_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PC31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PC31_FUNC_CTL_ESC0_GPI_32 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PC31_FUNC_CTL_ESC0_GPO_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PC31_FUNC_CTL_FEMC_SCS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PC31_FUNC_CTL_PPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PC31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PC31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PC31_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PC31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PC31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PC31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD00_FUNC_CTL function mux definitions */ -#define IOC_PD00_FUNC_CTL_GPIO_D_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD00_FUNC_CTL_ESC0_GPI_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD00_FUNC_CTL_ESC0_GPO_32 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD00_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD00_FUNC_CTL_PPI0_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD00_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD00_FUNC_CTL_XPI_SLV_ADQ_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PD01_FUNC_CTL function mux definitions */ -#define IOC_PD01_FUNC_CTL_GPIO_D_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD01_FUNC_CTL_ESC0_GPI_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD01_FUNC_CTL_ESC0_GPO_33 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD01_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD01_FUNC_CTL_PPI0_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD01_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD01_FUNC_CTL_XPI_SLV_CSN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PD02_FUNC_CTL function mux definitions */ -#define IOC_PD02_FUNC_CTL_GPIO_D_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD02_FUNC_CTL_ESC0_GPI_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD02_FUNC_CTL_ESC0_GPO_34 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD02_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD02_FUNC_CTL_PPI0_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD02_FUNC_CTL_ESC0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD02_FUNC_CTL_XPI_SLV_ERR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PD03_FUNC_CTL function mux definitions */ -#define IOC_PD03_FUNC_CTL_GPIO_D_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD03_FUNC_CTL_SPI5_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD03_FUNC_CTL_ESC0_GPI_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD03_FUNC_CTL_ESC0_GPO_35 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD03_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD03_FUNC_CTL_PPI0_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD03_FUNC_CTL_ESC0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD03_FUNC_CTL_XPI_SLV_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(30) - -/* IOC_PD04_FUNC_CTL function mux definitions */ -#define IOC_PD04_FUNC_CTL_GPIO_D_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD04_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD04_FUNC_CTL_ESC0_GPI_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD04_FUNC_CTL_ESC0_GPO_36 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD04_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD04_FUNC_CTL_PPI0_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD05_FUNC_CTL function mux definitions */ -#define IOC_PD05_FUNC_CTL_GPIO_D_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD05_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD05_FUNC_CTL_ESC0_GPI_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD05_FUNC_CTL_ESC0_GPO_37 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD05_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD05_FUNC_CTL_PPI0_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD06_FUNC_CTL function mux definitions */ -#define IOC_PD06_FUNC_CTL_GPIO_D_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD06_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD06_FUNC_CTL_ESC0_GPI_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD06_FUNC_CTL_ESC0_GPO_38 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD06_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD06_FUNC_CTL_PPI0_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD07_FUNC_CTL function mux definitions */ -#define IOC_PD07_FUNC_CTL_GPIO_D_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD07_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD07_FUNC_CTL_ESC0_GPI_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD07_FUNC_CTL_ESC0_GPO_39 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD07_FUNC_CTL_FEMC_SCLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD07_FUNC_CTL_PPI0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD08_FUNC_CTL function mux definitions */ -#define IOC_PD08_FUNC_CTL_GPIO_D_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD08_FUNC_CTL_SPI5_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD08_FUNC_CTL_ESC0_GPI_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD08_FUNC_CTL_ESC0_GPO_40 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD08_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD08_FUNC_CTL_PPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD09_FUNC_CTL function mux definitions */ -#define IOC_PD09_FUNC_CTL_GPIO_D_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD09_FUNC_CTL_SPI5_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD09_FUNC_CTL_ESC0_GPI_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD09_FUNC_CTL_ESC0_GPO_41 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD09_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) - -/* IOC_PD10_FUNC_CTL function mux definitions */ -#define IOC_PD10_FUNC_CTL_GPIO_D_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD10_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD10_FUNC_CTL_ESC0_GPI_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD10_FUNC_CTL_ESC0_GPO_42 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD10_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD10_FUNC_CTL_PPI0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PD11_FUNC_CTL function mux definitions */ -#define IOC_PD11_FUNC_CTL_GPIO_D_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD11_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD11_FUNC_CTL_ESC0_GPI_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD11_FUNC_CTL_ESC0_GPO_43 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD11_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD11_FUNC_CTL_PPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PD12_FUNC_CTL function mux definitions */ -#define IOC_PD12_FUNC_CTL_GPIO_D_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD12_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD12_FUNC_CTL_ESC0_GPI_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD12_FUNC_CTL_ESC0_GPO_44 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD12_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD12_FUNC_CTL_PPI0_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD12_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD12_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD13_FUNC_CTL function mux definitions */ -#define IOC_PD13_FUNC_CTL_GPIO_D_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD13_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD13_FUNC_CTL_ESC0_GPI_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD13_FUNC_CTL_ESC0_GPO_45 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD13_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD13_FUNC_CTL_PPI0_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD13_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD13_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD14_FUNC_CTL function mux definitions */ -#define IOC_PD14_FUNC_CTL_GPIO_D_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD14_FUNC_CTL_SPI5_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD14_FUNC_CTL_ESC0_GPI_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD14_FUNC_CTL_ESC0_GPO_46 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD14_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD14_FUNC_CTL_PPI0_DQ_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD14_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD14_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD14_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD14_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD15_FUNC_CTL function mux definitions */ -#define IOC_PD15_FUNC_CTL_GPIO_D_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD15_FUNC_CTL_SPI5_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD15_FUNC_CTL_ESC0_GPI_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD15_FUNC_CTL_ESC0_GPO_47 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD15_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD15_FUNC_CTL_PPI0_DM_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD15_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD15_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD15_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD15_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD16_FUNC_CTL function mux definitions */ -#define IOC_PD16_FUNC_CTL_GPIO_D_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD16_FUNC_CTL_ESC0_GPI_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD16_FUNC_CTL_ESC0_GPO_48 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD16_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD16_FUNC_CTL_PPI0_DQ_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD16_FUNC_CTL_ESC0_GPO_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD16_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD17_FUNC_CTL function mux definitions */ -#define IOC_PD17_FUNC_CTL_GPIO_D_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD17_FUNC_CTL_ESC0_GPI_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD17_FUNC_CTL_ESC0_GPO_49 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD17_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD17_FUNC_CTL_PPI0_DQ_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD17_FUNC_CTL_ESC0_GPO_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD18_FUNC_CTL function mux definitions */ -#define IOC_PD18_FUNC_CTL_GPIO_D_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD18_FUNC_CTL_ESC0_GPI_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD18_FUNC_CTL_ESC0_GPO_50 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD18_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD18_FUNC_CTL_PPI0_DQ_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD18_FUNC_CTL_ESC0_GPO_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PD19_FUNC_CTL function mux definitions */ -#define IOC_PD19_FUNC_CTL_GPIO_D_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD19_FUNC_CTL_SPI6_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD19_FUNC_CTL_ESC0_GPI_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD19_FUNC_CTL_ESC0_GPO_51 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD19_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD19_FUNC_CTL_PPI0_DQ_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD19_FUNC_CTL_ESC0_GPO_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) - -/* IOC_PD20_FUNC_CTL function mux definitions */ -#define IOC_PD20_FUNC_CTL_GPIO_D_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD20_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD20_FUNC_CTL_ESC0_GPI_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD20_FUNC_CTL_ESC0_GPO_52 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD20_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD20_FUNC_CTL_PPI0_DQ_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD20_FUNC_CTL_ESC0_GPO_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD20_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD21_FUNC_CTL function mux definitions */ -#define IOC_PD21_FUNC_CTL_GPIO_D_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD21_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD21_FUNC_CTL_ESC0_GPI_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD21_FUNC_CTL_ESC0_GPO_53 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD21_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD21_FUNC_CTL_PPI0_DQ_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD21_FUNC_CTL_ESC0_GPO_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD21_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD21_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD22_FUNC_CTL function mux definitions */ -#define IOC_PD22_FUNC_CTL_GPIO_D_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD22_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD22_FUNC_CTL_ESC0_GPI_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD22_FUNC_CTL_ESC0_GPO_54 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD22_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD22_FUNC_CTL_PPI0_DQ_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD22_FUNC_CTL_ESC0_GPO_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD22_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD22_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD23_FUNC_CTL function mux definitions */ -#define IOC_PD23_FUNC_CTL_GPIO_D_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD23_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD23_FUNC_CTL_ESC0_GPI_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD23_FUNC_CTL_ESC0_GPO_55 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD23_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD23_FUNC_CTL_PPI0_DM_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD23_FUNC_CTL_ESC0_GPO_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD23_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD23_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PD24_FUNC_CTL function mux definitions */ -#define IOC_PD24_FUNC_CTL_GPIO_D_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD24_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD24_FUNC_CTL_SPI6_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD24_FUNC_CTL_ESC0_GPI_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD24_FUNC_CTL_ESC0_GPO_56 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD24_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD24_FUNC_CTL_PPI0_DQ_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD24_FUNC_CTL_ESC0_GPO_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD24_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PD24_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PD25_FUNC_CTL function mux definitions */ -#define IOC_PD25_FUNC_CTL_GPIO_D_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD25_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD25_FUNC_CTL_SPI6_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD25_FUNC_CTL_ESC0_GPI_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD25_FUNC_CTL_ESC0_GPO_57 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD25_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD25_FUNC_CTL_PPI0_DQ_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD25_FUNC_CTL_ESC0_GPO_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD25_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PD26_FUNC_CTL function mux definitions */ -#define IOC_PD26_FUNC_CTL_GPIO_D_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD26_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD26_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD26_FUNC_CTL_SPI6_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD26_FUNC_CTL_ESC0_GPI_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD26_FUNC_CTL_ESC0_GPO_58 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD26_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD26_FUNC_CTL_PPI0_DQ_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD26_FUNC_CTL_ESC0_GPO_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD26_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PD27_FUNC_CTL function mux definitions */ -#define IOC_PD27_FUNC_CTL_GPIO_D_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD27_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD27_FUNC_CTL_SPI6_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD27_FUNC_CTL_ESC0_GPI_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD27_FUNC_CTL_ESC0_GPO_59 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD27_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD27_FUNC_CTL_PPI0_DQ_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD27_FUNC_CTL_ESC0_GPO_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD27_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PD28_FUNC_CTL function mux definitions */ -#define IOC_PD28_FUNC_CTL_GPIO_D_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD28_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD28_FUNC_CTL_SPI6_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD28_FUNC_CTL_ESC0_GPI_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD28_FUNC_CTL_ESC0_GPO_60 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD28_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD28_FUNC_CTL_PPI0_DQ_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD28_FUNC_CTL_ESC0_GPO_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD28_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PD29_FUNC_CTL function mux definitions */ -#define IOC_PD29_FUNC_CTL_GPIO_D_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD29_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD29_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PD29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PD29_FUNC_CTL_SPI6_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD29_FUNC_CTL_ESC0_GPI_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD29_FUNC_CTL_ESC0_GPO_61 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD29_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD29_FUNC_CTL_PPI0_DQ_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD29_FUNC_CTL_ESC0_GPO_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD29_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PD30_FUNC_CTL function mux definitions */ -#define IOC_PD30_FUNC_CTL_GPIO_D_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD30_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD30_FUNC_CTL_SPI6_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD30_FUNC_CTL_ESC0_GPI_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD30_FUNC_CTL_ESC0_GPO_62 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD30_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD30_FUNC_CTL_PPI0_DQ_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD30_FUNC_CTL_ESC0_GPO_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD30_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PD31_FUNC_CTL function mux definitions */ -#define IOC_PD31_FUNC_CTL_GPIO_D_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PD31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PD31_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PD31_FUNC_CTL_SPI6_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PD31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PD31_FUNC_CTL_ESC0_GPI_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PD31_FUNC_CTL_ESC0_GPO_63 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PD31_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PD31_FUNC_CTL_PPI0_DQ_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PD31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PD31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PD31_FUNC_CTL_ESC0_GPO_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PD31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PD31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PD31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PD31_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PE00_FUNC_CTL function mux definitions */ -#define IOC_PE00_FUNC_CTL_GPIO_E_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE00_FUNC_CTL_TSW0_P1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE00_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE00_FUNC_CTL_PPI0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PE00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE00_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE00_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE00_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE00_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PE00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PE00_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PE00_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PE00_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PE01_FUNC_CTL function mux definitions */ -#define IOC_PE01_FUNC_CTL_GPIO_E_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE01_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PE01_FUNC_CTL_TSW0_P1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE01_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE01_FUNC_CTL_PPI0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PE01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE01_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE01_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE01_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE01_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PE02_FUNC_CTL function mux definitions */ -#define IOC_PE02_FUNC_CTL_GPIO_E_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE02_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PE02_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE02_FUNC_CTL_PPI0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PE02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE02_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE02_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE02_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PE03_FUNC_CTL function mux definitions */ -#define IOC_PE03_FUNC_CTL_GPIO_E_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE03_FUNC_CTL_SPI0_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE03_FUNC_CTL_TSW0_P2_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE03_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE03_FUNC_CTL_PPI0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(13) -#define IOC_PE03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE03_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE03_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE03_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PE03_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PE03_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PE03_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PE04_FUNC_CTL function mux definitions */ -#define IOC_PE04_FUNC_CTL_GPIO_E_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE04_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PE04_FUNC_CTL_TSW0_P2_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE04_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE04_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE04_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PE04_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PE04_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PE04_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PE05_FUNC_CTL function mux definitions */ -#define IOC_PE05_FUNC_CTL_GPIO_E_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE05_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE05_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PE05_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE05_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PE05_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PE05_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PE06_FUNC_CTL function mux definitions */ -#define IOC_PE06_FUNC_CTL_GPIO_E_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE06_FUNC_CTL_TSW0_P3_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE06_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE06_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE06_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PE06_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PE06_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PE06_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PE06_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PE07_FUNC_CTL function mux definitions */ -#define IOC_PE07_FUNC_CTL_GPIO_E_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE07_FUNC_CTL_TSW0_P3_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE07_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE07_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) -#define IOC_PE07_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PE07_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PE07_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PE07_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PE08_FUNC_CTL function mux definitions */ -#define IOC_PE08_FUNC_CTL_GPIO_E_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE08_FUNC_CTL_SPI0_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE08_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE08_FUNC_CTL_ESC0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE08_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE09_FUNC_CTL function mux definitions */ -#define IOC_PE09_FUNC_CTL_GPIO_E_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE09_FUNC_CTL_SPI0_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE09_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE09_FUNC_CTL_ESC0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE09_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE10_FUNC_CTL function mux definitions */ -#define IOC_PE10_FUNC_CTL_GPIO_E_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE10_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE10_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE10_FUNC_CTL_ESC0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE11_FUNC_CTL function mux definitions */ -#define IOC_PE11_FUNC_CTL_GPIO_E_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE11_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE11_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE11_FUNC_CTL_ESC0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE11_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE12_FUNC_CTL function mux definitions */ -#define IOC_PE12_FUNC_CTL_GPIO_E_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE12_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE12_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE12_FUNC_CTL_ESC0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE12_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE13_FUNC_CTL function mux definitions */ -#define IOC_PE13_FUNC_CTL_GPIO_E_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE13_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE13_FUNC_CTL_ESC0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE14_FUNC_CTL function mux definitions */ -#define IOC_PE14_FUNC_CTL_GPIO_E_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE14_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE14_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE14_FUNC_CTL_ESC0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE15_FUNC_CTL function mux definitions */ -#define IOC_PE15_FUNC_CTL_GPIO_E_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE15_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE15_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE15_FUNC_CTL_ESC0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE16_FUNC_CTL function mux definitions */ -#define IOC_PE16_FUNC_CTL_GPIO_E_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE16_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE16_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE16_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE16_FUNC_CTL_ESC0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE16_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE16_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE16_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE17_FUNC_CTL function mux definitions */ -#define IOC_PE17_FUNC_CTL_GPIO_E_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE17_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE17_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE17_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE17_FUNC_CTL_ESC0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE17_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE17_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE17_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE18_FUNC_CTL function mux definitions */ -#define IOC_PE18_FUNC_CTL_GPIO_E_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE18_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE18_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE18_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE18_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE18_FUNC_CTL_ESC0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE18_FUNC_CTL_QEI2_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE18_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE18_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE19_FUNC_CTL function mux definitions */ -#define IOC_PE19_FUNC_CTL_GPIO_E_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE19_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE19_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE19_FUNC_CTL_SPI3_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE19_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE19_FUNC_CTL_ESC0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE19_FUNC_CTL_QEI2_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE19_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE19_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE20_FUNC_CTL function mux definitions */ -#define IOC_PE20_FUNC_CTL_GPIO_E_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE20_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE20_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE20_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE20_FUNC_CTL_TSW0_P3_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE20_FUNC_CTL_ESC0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE20_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE20_FUNC_CTL_QEI2_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE20_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE20_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE21_FUNC_CTL function mux definitions */ -#define IOC_PE21_FUNC_CTL_GPIO_E_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE21_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE21_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE21_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE21_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE21_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE21_FUNC_CTL_TSW0_P3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE21_FUNC_CTL_ESC0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE21_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE21_FUNC_CTL_QEI2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE21_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE21_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE22_FUNC_CTL function mux definitions */ -#define IOC_PE22_FUNC_CTL_GPIO_E_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE22_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE22_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE22_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE22_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE22_FUNC_CTL_TSW0_P3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE22_FUNC_CTL_ESC0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE22_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE22_FUNC_CTL_QEI2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE22_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE22_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE23_FUNC_CTL function mux definitions */ -#define IOC_PE23_FUNC_CTL_GPIO_E_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE23_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE23_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE23_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE23_FUNC_CTL_TSW0_P3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE23_FUNC_CTL_ESC0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE23_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE23_FUNC_CTL_QEI2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE23_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE23_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE24_FUNC_CTL function mux definitions */ -#define IOC_PE24_FUNC_CTL_GPIO_E_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE24_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE24_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE24_FUNC_CTL_SPI3_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE24_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE24_FUNC_CTL_TSW0_P3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE24_FUNC_CTL_ESC0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE24_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE24_FUNC_CTL_RDC0_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE24_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE24_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE25_FUNC_CTL function mux definitions */ -#define IOC_PE25_FUNC_CTL_GPIO_E_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE25_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE25_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE25_FUNC_CTL_SPI3_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE25_FUNC_CTL_TSW0_P3_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE25_FUNC_CTL_ESC0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE25_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE25_FUNC_CTL_RDC0_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE25_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE25_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE26_FUNC_CTL function mux definitions */ -#define IOC_PE26_FUNC_CTL_GPIO_E_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE26_FUNC_CTL_GPTMR2_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE26_FUNC_CTL_UART6_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE26_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE26_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE26_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE26_FUNC_CTL_TSW0_P3_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE26_FUNC_CTL_ESC0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE26_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE26_FUNC_CTL_QEI1_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE26_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE26_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE27_FUNC_CTL function mux definitions */ -#define IOC_PE27_FUNC_CTL_GPIO_E_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE27_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE27_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE27_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE27_FUNC_CTL_TSW0_P3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE27_FUNC_CTL_ESC0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE27_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE27_FUNC_CTL_QEI1_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE27_FUNC_CTL_RDC1_PWM_N IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE27_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE28_FUNC_CTL function mux definitions */ -#define IOC_PE28_FUNC_CTL_GPIO_E_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE28_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE28_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE28_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE28_FUNC_CTL_TSW0_P3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE28_FUNC_CTL_ESC0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE28_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE28_FUNC_CTL_QEI1_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE28_FUNC_CTL_RDC1_PWM_P IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE28_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE29_FUNC_CTL function mux definitions */ -#define IOC_PE29_FUNC_CTL_GPIO_E_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE29_FUNC_CTL_GPTMR3_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE29_FUNC_CTL_UART7_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE29_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PE29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PE29_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE29_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE29_FUNC_CTL_TSW0_P3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE29_FUNC_CTL_ESC0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE29_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE29_FUNC_CTL_QEI1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE29_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE29_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE30_FUNC_CTL function mux definitions */ -#define IOC_PE30_FUNC_CTL_GPIO_E_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE30_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE30_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE30_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE30_FUNC_CTL_TSW0_P3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE30_FUNC_CTL_ESC0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE30_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE30_FUNC_CTL_QEI1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE30_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE30_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PE31_FUNC_CTL function mux definitions */ -#define IOC_PE31_FUNC_CTL_GPIO_E_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PE31_FUNC_CTL_GPTMR2_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PE31_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PE31_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PE31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PE31_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(8) -#define IOC_PE31_FUNC_CTL_TSW0_P3_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PE31_FUNC_CTL_ESC0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PE31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PE31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PE31_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PE31_FUNC_CTL_QEI1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PE31_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PE31_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF00_FUNC_CTL function mux definitions */ -#define IOC_PF00_FUNC_CTL_GPIO_F_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF00_FUNC_CTL_DAO_LN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF00_FUNC_CTL_TSW0_P3_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF00_FUNC_CTL_ESC0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF00_FUNC_CTL_TRGM_P_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF00_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF00_FUNC_CTL_QEO1_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF00_FUNC_CTL_SEI1_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF01_FUNC_CTL function mux definitions */ -#define IOC_PF01_FUNC_CTL_GPIO_F_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF01_FUNC_CTL_DAO_LP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF01_FUNC_CTL_TSW0_P3_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF01_FUNC_CTL_ESC0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF01_FUNC_CTL_TRGM_P_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF01_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF01_FUNC_CTL_QEO1_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF01_FUNC_CTL_SEI1_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF02_FUNC_CTL function mux definitions */ -#define IOC_PF02_FUNC_CTL_GPIO_F_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF02_FUNC_CTL_TSW0_P3_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF02_FUNC_CTL_ESC0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF02_FUNC_CTL_TRGM_P_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF02_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF02_FUNC_CTL_QEI0_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF02_FUNC_CTL_QEO1_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF02_FUNC_CTL_SEI1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF03_FUNC_CTL function mux definitions */ -#define IOC_PF03_FUNC_CTL_GPIO_F_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF03_FUNC_CTL_SPI4_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF03_FUNC_CTL_DAO_RN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF03_FUNC_CTL_TSW0_P3_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF03_FUNC_CTL_ESC0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF03_FUNC_CTL_TRGM_P_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF03_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF03_FUNC_CTL_QEI0_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF03_FUNC_CTL_SEI1_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF04_FUNC_CTL function mux definitions */ -#define IOC_PF04_FUNC_CTL_GPIO_F_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF04_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF04_FUNC_CTL_DAO_RP IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) -#define IOC_PF04_FUNC_CTL_TSW0_P3_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF04_FUNC_CTL_ESC0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF04_FUNC_CTL_TRGM_P_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF04_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF04_FUNC_CTL_QEI0_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF04_FUNC_CTL_SEI0_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF05_FUNC_CTL function mux definitions */ -#define IOC_PF05_FUNC_CTL_GPIO_F_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF05_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF05_FUNC_CTL_TSW0_P3_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF05_FUNC_CTL_ESC0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF05_FUNC_CTL_TRGM_P_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF05_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF05_FUNC_CTL_QEI0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF05_FUNC_CTL_QEO0_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF05_FUNC_CTL_SEI0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF06_FUNC_CTL function mux definitions */ -#define IOC_PF06_FUNC_CTL_GPIO_F_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF06_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF06_FUNC_CTL_TSW0_P3_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF06_FUNC_CTL_ESC0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF06_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF06_FUNC_CTL_TRGM_P_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF06_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF06_FUNC_CTL_QEI0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF06_FUNC_CTL_QEO0_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF06_FUNC_CTL_SEI0_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF07_FUNC_CTL function mux definitions */ -#define IOC_PF07_FUNC_CTL_GPIO_F_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF07_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF07_FUNC_CTL_TSW0_P3_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF07_FUNC_CTL_ESC0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF07_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF07_FUNC_CTL_TRGM_P_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF07_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF07_FUNC_CTL_QEI0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF07_FUNC_CTL_QEO0_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF07_FUNC_CTL_SEI0_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF08_FUNC_CTL function mux definitions */ -#define IOC_PF08_FUNC_CTL_GPIO_F_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF08_FUNC_CTL_SPI4_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF08_FUNC_CTL_TSW0_P3_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF08_FUNC_CTL_ESC0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF08_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF08_FUNC_CTL_TRGM_P_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF08_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF08_FUNC_CTL_QEO2_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF08_FUNC_CTL_SEI2_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF09_FUNC_CTL function mux definitions */ -#define IOC_PF09_FUNC_CTL_GPIO_F_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF09_FUNC_CTL_SPI4_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF09_FUNC_CTL_TSW0_P3_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF09_FUNC_CTL_ESC0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF09_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF09_FUNC_CTL_TRGM_P_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF09_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF09_FUNC_CTL_QEO2_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF09_FUNC_CTL_SEI2_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF10_FUNC_CTL function mux definitions */ -#define IOC_PF10_FUNC_CTL_GPIO_F_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF10_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF10_FUNC_CTL_TSW0_P3_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF10_FUNC_CTL_ESC0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF10_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF10_FUNC_CTL_TRGM_P_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF10_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF10_FUNC_CTL_QEI3_F IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF10_FUNC_CTL_QEO2_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF10_FUNC_CTL_SEI2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF11_FUNC_CTL function mux definitions */ -#define IOC_PF11_FUNC_CTL_GPIO_F_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF11_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF11_FUNC_CTL_TSW0_P3_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF11_FUNC_CTL_ESC0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF11_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF11_FUNC_CTL_TRGM_P_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF11_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF11_FUNC_CTL_QEI3_H1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF11_FUNC_CTL_SEI2_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF12_FUNC_CTL function mux definitions */ -#define IOC_PF12_FUNC_CTL_GPIO_F_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF12_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF12_FUNC_CTL_TSW0_P3_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF12_FUNC_CTL_ESC0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF12_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF12_FUNC_CTL_TRGM_P_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF12_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF12_FUNC_CTL_QEI3_H0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF12_FUNC_CTL_SEI3_CK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF13_FUNC_CTL function mux definitions */ -#define IOC_PF13_FUNC_CTL_GPIO_F_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF13_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF13_FUNC_CTL_TSW0_P3_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF13_FUNC_CTL_ESC0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF13_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF13_FUNC_CTL_TRGM_P_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF13_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF13_FUNC_CTL_QEI3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF13_FUNC_CTL_QEO3_Z IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF13_FUNC_CTL_SEI3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF14_FUNC_CTL function mux definitions */ -#define IOC_PF14_FUNC_CTL_GPIO_F_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF14_FUNC_CTL_SPI4_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF14_FUNC_CTL_TSW0_P3_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF14_FUNC_CTL_ESC0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF14_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF14_FUNC_CTL_TRGM_P_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF14_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF14_FUNC_CTL_QEI3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF14_FUNC_CTL_QEO3_B IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF14_FUNC_CTL_SEI3_RX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF15_FUNC_CTL function mux definitions */ -#define IOC_PF15_FUNC_CTL_GPIO_F_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF15_FUNC_CTL_SPI4_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF15_FUNC_CTL_TSW0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PF15_FUNC_CTL_ESC0_P2_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PF15_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF15_FUNC_CTL_TRGM_P_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF15_FUNC_CTL_ETH0_TXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) -#define IOC_PF15_FUNC_CTL_QEI3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(20) -#define IOC_PF15_FUNC_CTL_QEO3_A IOC_PAD_FUNC_CTL_ALT_SELECT_SET(21) -#define IOC_PF15_FUNC_CTL_SEI3_TX IOC_PAD_FUNC_CTL_ALT_SELECT_SET(22) - -/* IOC_PF16_FUNC_CTL function mux definitions */ -#define IOC_PF16_FUNC_CTL_GPIO_F_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF16_FUNC_CTL_PWM2_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF16_FUNC_CTL_TRGM_P_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF16_FUNC_CTL_SDM0_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF17_FUNC_CTL function mux definitions */ -#define IOC_PF17_FUNC_CTL_GPIO_F_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF17_FUNC_CTL_PWM2_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF17_FUNC_CTL_TRGM_P_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF17_FUNC_CTL_SDM0_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF18_FUNC_CTL function mux definitions */ -#define IOC_PF18_FUNC_CTL_GPIO_F_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF18_FUNC_CTL_I2C6_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF18_FUNC_CTL_PWM2_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF18_FUNC_CTL_TRGM_P_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF18_FUNC_CTL_SDM0_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF18_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PF18_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PF18_FUNC_CTL_TSW0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PF18_FUNC_CTL_ESC0_EVTO_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PF19_FUNC_CTL function mux definitions */ -#define IOC_PF19_FUNC_CTL_GPIO_F_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF19_FUNC_CTL_I2C6_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF19_FUNC_CTL_SPI7_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF19_FUNC_CTL_PWM2_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF19_FUNC_CTL_TRGM_P_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF19_FUNC_CTL_SDM0_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF19_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PF19_FUNC_CTL_ETH0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PF19_FUNC_CTL_TSW0_EVTO_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PF20_FUNC_CTL function mux definitions */ -#define IOC_PF20_FUNC_CTL_GPIO_F_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF20_FUNC_CTL_SPI6_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF20_FUNC_CTL_PWM2_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF20_FUNC_CTL_TRGM_P_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF20_FUNC_CTL_SDM0_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF20_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PF20_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PF20_FUNC_CTL_TSW0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PF20_FUNC_CTL_ESC0_EVTO_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PF21_FUNC_CTL function mux definitions */ -#define IOC_PF21_FUNC_CTL_GPIO_F_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF21_FUNC_CTL_SPI6_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF21_FUNC_CTL_PWM2_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF21_FUNC_CTL_TRGM_P_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF21_FUNC_CTL_SDM0_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF21_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PF21_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PF21_FUNC_CTL_TSW0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PF21_FUNC_CTL_ESC0_EVTI_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PF22_FUNC_CTL function mux definitions */ -#define IOC_PF22_FUNC_CTL_GPIO_F_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF22_FUNC_CTL_I2C7_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF22_FUNC_CTL_SPI6_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF22_FUNC_CTL_PWM2_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF22_FUNC_CTL_TRGM_P_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF22_FUNC_CTL_SDM0_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF22_FUNC_CTL_USB0_ID IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PF22_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PF22_FUNC_CTL_TSW0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) -#define IOC_PF22_FUNC_CTL_ESC0_EVTI_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(27) - -/* IOC_PF23_FUNC_CTL function mux definitions */ -#define IOC_PF23_FUNC_CTL_GPIO_F_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF23_FUNC_CTL_I2C7_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF23_FUNC_CTL_SPI6_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF23_FUNC_CTL_PWM2_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF23_FUNC_CTL_TRGM_P_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF23_FUNC_CTL_SDM0_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF23_FUNC_CTL_USB0_OC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF24_FUNC_CTL function mux definitions */ -#define IOC_PF24_FUNC_CTL_GPIO_F_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF24_FUNC_CTL_GPTMR6_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF24_FUNC_CTL_UART14_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF24_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF24_FUNC_CTL_SPI7_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF24_FUNC_CTL_MCAN6_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF24_FUNC_CTL_PWM3_P_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF24_FUNC_CTL_TRGM_P_24 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF24_FUNC_CTL_SDM1_DAT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF25_FUNC_CTL function mux definitions */ -#define IOC_PF25_FUNC_CTL_GPIO_F_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF25_FUNC_CTL_GPTMR6_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF25_FUNC_CTL_UART14_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF25_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF25_FUNC_CTL_SPI7_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF25_FUNC_CTL_MCAN6_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF25_FUNC_CTL_PWM3_P_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF25_FUNC_CTL_TRGM_P_25 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF25_FUNC_CTL_SDM1_CLK_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF26_FUNC_CTL function mux definitions */ -#define IOC_PF26_FUNC_CTL_GPIO_F_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF26_FUNC_CTL_GPTMR6_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF26_FUNC_CTL_UART14_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF26_FUNC_CTL_UART14_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF26_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF26_FUNC_CTL_MCAN6_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF26_FUNC_CTL_PWM3_P_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF26_FUNC_CTL_TRGM_P_26 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF26_FUNC_CTL_SDM1_DAT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF26_FUNC_CTL_CPU0_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) -#define IOC_PF26_FUNC_CTL_ETH0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(25) -#define IOC_PF26_FUNC_CTL_TSW0_EVTO_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(26) - -/* IOC_PF27_FUNC_CTL function mux definitions */ -#define IOC_PF27_FUNC_CTL_GPIO_F_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF27_FUNC_CTL_UART14_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF27_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF27_FUNC_CTL_PWM3_P_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF27_FUNC_CTL_TRGM_P_27 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF27_FUNC_CTL_SDM1_CLK_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF28_FUNC_CTL function mux definitions */ -#define IOC_PF28_FUNC_CTL_GPIO_F_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF28_FUNC_CTL_UART15_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF28_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF28_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF28_FUNC_CTL_PWM3_P_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF28_FUNC_CTL_TRGM_P_28 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF28_FUNC_CTL_SDM1_DAT_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) -#define IOC_PF28_FUNC_CTL_CPU1_NMI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PF29_FUNC_CTL function mux definitions */ -#define IOC_PF29_FUNC_CTL_GPIO_F_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF29_FUNC_CTL_GPTMR7_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF29_FUNC_CTL_UART15_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF29_FUNC_CTL_UART15_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PF29_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PF29_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF29_FUNC_CTL_MCAN7_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF29_FUNC_CTL_PWM3_P_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF29_FUNC_CTL_TRGM_P_29 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF29_FUNC_CTL_SDM1_CLK_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF30_FUNC_CTL function mux definitions */ -#define IOC_PF30_FUNC_CTL_GPIO_F_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF30_FUNC_CTL_UART15_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF30_FUNC_CTL_SPI7_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF30_FUNC_CTL_MCAN7_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF30_FUNC_CTL_PWM3_P_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF30_FUNC_CTL_TRGM_P_30 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF30_FUNC_CTL_SDM1_CLK_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PF31_FUNC_CTL function mux definitions */ -#define IOC_PF31_FUNC_CTL_GPIO_F_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PF31_FUNC_CTL_GPTMR6_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PF31_FUNC_CTL_UART15_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PF31_FUNC_CTL_SPI7_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PF31_FUNC_CTL_MCAN7_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PF31_FUNC_CTL_PWM3_P_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(16) -#define IOC_PF31_FUNC_CTL_TRGM_P_31 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) -#define IOC_PF31_FUNC_CTL_SDM1_DAT_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(23) - -/* IOC_PV00_FUNC_CTL function mux definitions */ -#define IOC_PV00_FUNC_CTL_GPIO_V_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV00_FUNC_CTL_TSW0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV00_FUNC_CTL_ESC0_P0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV01_FUNC_CTL function mux definitions */ -#define IOC_PV01_FUNC_CTL_GPIO_V_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV01_FUNC_CTL_TSW0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV01_FUNC_CTL_ESC0_P0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV02_FUNC_CTL function mux definitions */ -#define IOC_PV02_FUNC_CTL_GPIO_V_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV02_FUNC_CTL_TSW0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV02_FUNC_CTL_ESC0_P0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV03_FUNC_CTL function mux definitions */ -#define IOC_PV03_FUNC_CTL_GPIO_V_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV03_FUNC_CTL_SPI1_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV03_FUNC_CTL_TSW0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV03_FUNC_CTL_ESC0_P0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV04_FUNC_CTL function mux definitions */ -#define IOC_PV04_FUNC_CTL_GPIO_V_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV04_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV04_FUNC_CTL_TSW0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV04_FUNC_CTL_ESC0_P0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV05_FUNC_CTL function mux definitions */ -#define IOC_PV05_FUNC_CTL_GPIO_V_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV05_FUNC_CTL_SPI0_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV05_FUNC_CTL_TSW0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV05_FUNC_CTL_ESC0_P0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV06_FUNC_CTL function mux definitions */ -#define IOC_PV06_FUNC_CTL_GPIO_V_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV06_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV06_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV06_FUNC_CTL_TSW0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV06_FUNC_CTL_ESC0_P0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV07_FUNC_CTL function mux definitions */ -#define IOC_PV07_FUNC_CTL_GPIO_V_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV07_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV07_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV07_FUNC_CTL_TSW0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV07_FUNC_CTL_ESC0_P0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV08_FUNC_CTL function mux definitions */ -#define IOC_PV08_FUNC_CTL_GPIO_V_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV08_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV08_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV08_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV08_FUNC_CTL_SPI1_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV08_FUNC_CTL_TSW0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV08_FUNC_CTL_ESC0_P0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV09_FUNC_CTL function mux definitions */ -#define IOC_PV09_FUNC_CTL_GPIO_V_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV09_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV09_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV09_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV09_FUNC_CTL_SPI1_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV09_FUNC_CTL_TSW0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV09_FUNC_CTL_ESC0_P0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV10_FUNC_CTL function mux definitions */ -#define IOC_PV10_FUNC_CTL_GPIO_V_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV10_FUNC_CTL_GPTMR0_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV10_FUNC_CTL_UART2_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV10_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV10_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV10_FUNC_CTL_TSW0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV10_FUNC_CTL_ESC0_P0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV11_FUNC_CTL function mux definitions */ -#define IOC_PV11_FUNC_CTL_GPIO_V_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV11_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV11_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV11_FUNC_CTL_TSW0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV11_FUNC_CTL_ESC0_P0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV12_FUNC_CTL function mux definitions */ -#define IOC_PV12_FUNC_CTL_GPIO_V_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV12_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV12_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV12_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV12_FUNC_CTL_TSW0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PV12_FUNC_CTL_ESC0_CTR_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV13_FUNC_CTL function mux definitions */ -#define IOC_PV13_FUNC_CTL_GPIO_V_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV13_FUNC_CTL_GPTMR1_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV13_FUNC_CTL_UART3_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV13_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PV13_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PV13_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV13_FUNC_CTL_ESC0_CTR_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV14_FUNC_CTL function mux definitions */ -#define IOC_PV14_FUNC_CTL_GPIO_V_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV14_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV14_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV14_FUNC_CTL_ESC0_CTR_4 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PV15_FUNC_CTL function mux definitions */ -#define IOC_PV15_FUNC_CTL_GPIO_V_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PV15_FUNC_CTL_GPTMR0_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PV15_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PV15_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PV15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PV15_FUNC_CTL_ESC0_P0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PW00_FUNC_CTL function mux definitions */ -#define IOC_PW00_FUNC_CTL_GPIO_W_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW00_FUNC_CTL_GPTMR5_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW00_FUNC_CTL_UART8_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW00_FUNC_CTL_TSW0_P2_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW00_FUNC_CTL_ESC0_P1_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW00_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW01_FUNC_CTL function mux definitions */ -#define IOC_PW01_FUNC_CTL_GPIO_W_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW01_FUNC_CTL_GPTMR5_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW01_FUNC_CTL_UART8_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW01_FUNC_CTL_TSW0_P2_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW01_FUNC_CTL_ESC0_P1_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW01_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW02_FUNC_CTL function mux definitions */ -#define IOC_PW02_FUNC_CTL_GPIO_W_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW02_FUNC_CTL_GPTMR5_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW02_FUNC_CTL_UART8_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW02_FUNC_CTL_UART8_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW02_FUNC_CTL_TSW0_P2_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW02_FUNC_CTL_ESC0_P1_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW02_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW03_FUNC_CTL function mux definitions */ -#define IOC_PW03_FUNC_CTL_GPIO_W_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW03_FUNC_CTL_GPTMR5_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW03_FUNC_CTL_UART8_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW03_FUNC_CTL_SPI5_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW03_FUNC_CTL_TSW0_P2_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW03_FUNC_CTL_ESC0_P1_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW03_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW04_FUNC_CTL function mux definitions */ -#define IOC_PW04_FUNC_CTL_GPIO_W_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW04_FUNC_CTL_UART9_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW04_FUNC_CTL_SPI4_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW04_FUNC_CTL_TSW0_P2_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW04_FUNC_CTL_ESC0_P1_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW04_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW05_FUNC_CTL function mux definitions */ -#define IOC_PW05_FUNC_CTL_GPIO_W_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW05_FUNC_CTL_GPTMR5_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW05_FUNC_CTL_UART9_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW05_FUNC_CTL_UART9_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW05_FUNC_CTL_SPI4_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW05_FUNC_CTL_TSW0_P2_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW05_FUNC_CTL_ESC0_P1_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW05_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW06_FUNC_CTL function mux definitions */ -#define IOC_PW06_FUNC_CTL_GPIO_W_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW06_FUNC_CTL_GPTMR4_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW06_FUNC_CTL_UART9_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW06_FUNC_CTL_SPI4_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW06_FUNC_CTL_TSW0_P2_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW06_FUNC_CTL_ESC0_P1_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW06_FUNC_CTL_ETH0_TXCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW07_FUNC_CTL function mux definitions */ -#define IOC_PW07_FUNC_CTL_GPIO_W_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW07_FUNC_CTL_GPTMR4_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW07_FUNC_CTL_UART9_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW07_FUNC_CTL_SPI4_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW07_FUNC_CTL_TSW0_P2_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW07_FUNC_CTL_ESC0_P1_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW07_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW08_FUNC_CTL function mux definitions */ -#define IOC_PW08_FUNC_CTL_GPIO_W_08 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW08_FUNC_CTL_GPTMR4_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW08_FUNC_CTL_UART10_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW08_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PW08_FUNC_CTL_SPI5_CS_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW08_FUNC_CTL_MCAN2_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW08_FUNC_CTL_TSW0_P2_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW08_FUNC_CTL_ESC0_P1_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW08_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW09_FUNC_CTL function mux definitions */ -#define IOC_PW09_FUNC_CTL_GPIO_W_09 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW09_FUNC_CTL_GPTMR4_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW09_FUNC_CTL_UART10_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW09_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PW09_FUNC_CTL_SPI5_CS_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW09_FUNC_CTL_MCAN2_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW09_FUNC_CTL_TSW0_P2_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW09_FUNC_CTL_ESC0_P1_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW09_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW10_FUNC_CTL function mux definitions */ -#define IOC_PW10_FUNC_CTL_GPIO_W_10 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW10_FUNC_CTL_GPTMR4_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW10_FUNC_CTL_UART10_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW10_FUNC_CTL_UART10_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW10_FUNC_CTL_SPI5_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW10_FUNC_CTL_MCAN2_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW10_FUNC_CTL_TSW0_P2_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW10_FUNC_CTL_ESC0_P1_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW10_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW11_FUNC_CTL function mux definitions */ -#define IOC_PW11_FUNC_CTL_GPIO_W_11 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW11_FUNC_CTL_UART10_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW11_FUNC_CTL_SPI5_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW11_FUNC_CTL_TSW0_P2_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW11_FUNC_CTL_ESC0_P1_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW11_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW12_FUNC_CTL function mux definitions */ -#define IOC_PW12_FUNC_CTL_GPIO_W_12 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW12_FUNC_CTL_UART11_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW12_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PW12_FUNC_CTL_SPI5_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW12_FUNC_CTL_TSW0_P2_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW12_FUNC_CTL_ESC0_CTR_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW12_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW13_FUNC_CTL function mux definitions */ -#define IOC_PW13_FUNC_CTL_GPIO_W_13 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW13_FUNC_CTL_GPTMR5_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW13_FUNC_CTL_UART11_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW13_FUNC_CTL_UART11_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW13_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PW13_FUNC_CTL_SPI5_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW13_FUNC_CTL_MCAN3_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW13_FUNC_CTL_ESC0_CTR_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW13_FUNC_CTL_ETH0_TXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW14_FUNC_CTL function mux definitions */ -#define IOC_PW14_FUNC_CTL_GPIO_W_14 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW14_FUNC_CTL_UART11_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW14_FUNC_CTL_SPI5_DAT2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW14_FUNC_CTL_MCAN3_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW14_FUNC_CTL_ESC0_CTR_5 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW14_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW15_FUNC_CTL function mux definitions */ -#define IOC_PW15_FUNC_CTL_GPIO_W_15 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW15_FUNC_CTL_GPTMR4_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW15_FUNC_CTL_UART11_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW15_FUNC_CTL_SPI5_DAT3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW15_FUNC_CTL_MCAN3_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW15_FUNC_CTL_ESC0_P1_RXER IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW15_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW16_FUNC_CTL function mux definitions */ -#define IOC_PW16_FUNC_CTL_GPIO_W_16 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW16_FUNC_CTL_GPTMR7_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW16_FUNC_CTL_UART12_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW16_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW16_FUNC_CTL_TSW0_P1_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW16_FUNC_CTL_ESC0_CTR_6 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW16_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW17_FUNC_CTL function mux definitions */ -#define IOC_PW17_FUNC_CTL_GPIO_W_17 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW17_FUNC_CTL_GPTMR7_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW17_FUNC_CTL_UART12_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW17_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW17_FUNC_CTL_TSW0_P1_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW17_FUNC_CTL_ESC0_CTR_7 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW17_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(18) - -/* IOC_PW18_FUNC_CTL function mux definitions */ -#define IOC_PW18_FUNC_CTL_GPIO_W_18 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW18_FUNC_CTL_GPTMR7_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW18_FUNC_CTL_UART12_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW18_FUNC_CTL_UART12_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW18_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW18_FUNC_CTL_TSW0_P2_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW18_FUNC_CTL_ESC0_MDIO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PW19_FUNC_CTL function mux definitions */ -#define IOC_PW19_FUNC_CTL_GPIO_W_19 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW19_FUNC_CTL_GPTMR7_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW19_FUNC_CTL_UART12_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW19_FUNC_CTL_SPI6_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW19_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW19_FUNC_CTL_TSW0_P2_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(10) -#define IOC_PW19_FUNC_CTL_ESC0_MDC IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PW20_FUNC_CTL function mux definitions */ -#define IOC_PW20_FUNC_CTL_GPIO_W_20 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW20_FUNC_CTL_UART13_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW20_FUNC_CTL_SPI7_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW20_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW20_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW20_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PW21_FUNC_CTL function mux definitions */ -#define IOC_PW21_FUNC_CTL_GPIO_W_21 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW21_FUNC_CTL_GPTMR7_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW21_FUNC_CTL_UART13_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW21_FUNC_CTL_UART13_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PW21_FUNC_CTL_SPI7_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW21_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PW21_FUNC_CTL_ESC0_REFCK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) -#define IOC_PW21_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(24) - -/* IOC_PW22_FUNC_CTL function mux definitions */ -#define IOC_PW22_FUNC_CTL_GPIO_W_22 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW22_FUNC_CTL_GPTMR6_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW22_FUNC_CTL_UART13_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW22_FUNC_CTL_SPI7_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PW22_FUNC_CTL_ESC0_CTR_8 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(11) - -/* IOC_PW23_FUNC_CTL function mux definitions */ -#define IOC_PW23_FUNC_CTL_GPIO_W_23 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PW23_FUNC_CTL_GPTMR6_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PW23_FUNC_CTL_UART13_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PW23_FUNC_CTL_SPI7_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PX00_FUNC_CTL function mux definitions */ -#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX00_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX01_FUNC_CTL function mux definitions */ -#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX01_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX02_FUNC_CTL function mux definitions */ -#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX02_FUNC_CTL_I2C4_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX02_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX03_FUNC_CTL function mux definitions */ -#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX03_FUNC_CTL_I2C4_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX03_FUNC_CTL_SPI2_CS_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX03_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX04_FUNC_CTL function mux definitions */ -#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX04_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX04_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX05_FUNC_CTL function mux definitions */ -#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PX05_FUNC_CTL_SPI3_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PX05_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX06_FUNC_CTL function mux definitions */ -#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX06_FUNC_CTL_I2C5_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX06_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX06_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PX07_FUNC_CTL function mux definitions */ -#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PX07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PX07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PX07_FUNC_CTL_I2C5_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PX07_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PX07_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(12) -#define IOC_PX07_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(14) - -/* IOC_PY00_FUNC_CTL function mux definitions */ -#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY00_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY00_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY00_FUNC_CTL_MCAN0_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY01_FUNC_CTL function mux definitions */ -#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY01_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY01_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY01_FUNC_CTL_MCAN0_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PY02_FUNC_CTL function mux definitions */ -#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY02_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY02_FUNC_CTL_MCAN0_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY02_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PY03_FUNC_CTL function mux definitions */ -#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY03_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY03_FUNC_CTL_MCAN1_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY03_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PY04_FUNC_CTL function mux definitions */ -#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY04_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY04_FUNC_CTL_MCAN1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY04_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PY05_FUNC_CTL function mux definitions */ -#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY05_FUNC_CTL_GPTMR1_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY05_FUNC_CTL_UART1_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY05_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PY05_FUNC_CTL_SPI1_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY05_FUNC_CTL_MCAN1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) -#define IOC_PY05_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PY06_FUNC_CTL function mux definitions */ -#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY06_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY06_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PY07_FUNC_CTL function mux definitions */ -#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PY07_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PY07_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PY07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PY07_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PY07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(9) - -/* IOC_PZ00_FUNC_CTL function mux definitions */ -#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ00_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ00_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ00_FUNC_CTL_MCAN4_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ01_FUNC_CTL function mux definitions */ -#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ01_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ01_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ01_FUNC_CTL_MCAN4_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ02_FUNC_CTL function mux definitions */ -#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ02_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ02_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ02_FUNC_CTL_MCAN4_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ03_FUNC_CTL function mux definitions */ -#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ03_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ03_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ03_FUNC_CTL_MCAN5_STBY IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ04_FUNC_CTL function mux definitions */ -#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ04_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ04_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ04_FUNC_CTL_MCAN5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ05_FUNC_CTL function mux definitions */ -#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ05_FUNC_CTL_GPTMR3_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ05_FUNC_CTL_UART5_DE IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ05_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) -#define IOC_PZ05_FUNC_CTL_SPI2_CS_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) -#define IOC_PZ05_FUNC_CTL_MCAN5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(7) - -/* IOC_PZ06_FUNC_CTL function mux definitions */ -#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ06_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ06_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - -/* IOC_PZ07_FUNC_CTL function mux definitions */ -#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define IOC_PZ07_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define IOC_PZ07_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define IOC_PZ07_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_CTL_ALT_SELECT_SET(4) -#define IOC_PZ07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_CTL_ALT_SELECT_SET(5) - - -#endif /* HPM_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_l1c_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_l1c_drv.c deleted file mode 100644 index c55600dcdcc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_l1c_drv.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_l1c_drv.h" -#include - - -#define ASSERT_ADDR_SIZE(addr, size) do { \ - assert(address % HPM_L1C_CACHELINE_SIZE == 0); \ - assert(size % HPM_L1C_CACHELINE_SIZE == 0); \ - } while (0) - -static void l1c_op(uint8_t opcode, uint32_t address, uint32_t size) -{ - register uint32_t i; - register uint32_t next_address; - register uint32_t tmp; - register uint32_t csr; - - csr = read_clear_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK); - -#define CCTL_VERSION (3U << 18) - - if ((read_csr(CSR_MMSC_CFG) & CCTL_VERSION)) { - l1c_cctl_address(address); - next_address = address; - while ((next_address < (address + size)) && (next_address >= address)) { - l1c_cctl_cmd(opcode); - next_address = l1c_cctl_get_address(); - } - } else { - for (i = 0, tmp = 0; tmp < size; i++) { - l1c_cctl_address_cmd(opcode, address + i * HPM_L1C_CACHELINE_SIZE); - tmp += HPM_L1C_CACHELINE_SIZE; - } - } - - write_csr(CSR_MSTATUS, csr); -} - -void l1c_dc_enable(void) -{ - if (!l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_WAROUND_MASK); - set_csr(CSR_MCACHE_CTL, -#ifdef L1C_DC_WAROUND_VALUE - HPM_MCACHE_CTL_DC_WAROUND(L1C_DC_WAROUND_VALUE) | -#endif - HPM_MCACHE_CTL_DPREF_EN_MASK - | HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_dc_disable(void) -{ - if (l1c_dc_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_DC_EN_MASK); - } -} - -void l1c_ic_enable(void) -{ - if (!l1c_ic_is_enabled()) { - set_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IPREF_EN_MASK - | HPM_MCACHE_CTL_CCTL_SUEN_MASK - | HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_ic_disable(void) -{ - if (l1c_ic_is_enabled()) { - clear_csr(CSR_MCACHE_CTL, HPM_MCACHE_CTL_IC_EN_MASK); - } -} - -void l1c_fence_i(void) -{ - __asm("fence.i"); -} - -void l1c_dc_invalidate_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_INVAL_ALL); -} - -void l1c_dc_writeback_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WB_ALL); -} - -void l1c_dc_flush_all(void) -{ - l1c_cctl_cmd(HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL); -} - -void l1c_dc_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_LOCK, address, size); -} - -void l1c_dc_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_INVAL, address, size); -} - -void l1c_dc_writeback(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WB, address, size); -} - -void l1c_dc_flush(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL, address, size); -} - -void l1c_ic_invalidate(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_INVAL, address, size); -} - -void l1c_ic_fill_lock(uint32_t address, uint32_t size) -{ - ASSERT_ADDR_SIZE(address, size); - l1c_op(HPM_L1C_CCTL_CMD_L1I_VA_LOCK, address, size); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_l1c_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_l1c_drv.h deleted file mode 100644 index 1f1a21639a2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_l1c_drv.h +++ /dev/null @@ -1,485 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_L1_CACHE_H -#define _HPM_L1_CACHE_H -#include "hpm_common.h" -#include "hpm_csr_drv.h" -#include "hpm_soc.h" - -/** - * - * @brief L1CACHE driver APIs - * @defgroup l1cache_interface L1CACHE driver APIs - * @{ - */ - -/* cache size is 32KB */ -#define HPM_L1C_CACHE_SIZE (uint32_t)(32 * SIZE_1KB) -#define HPM_L1C_ICACHE_SIZE (HPM_L1C_CACHE_SIZE) -#define HPM_L1C_DCACHE_SIZE (HPM_L1C_CACHE_SIZE) -/* cache line size is 64B */ -#define HPM_L1C_CACHELINE_SIZE (64) -/* cache way is 128 */ -#define HPM_L1C_CACHELINES_PER_WAY (128) - -/* mcache_ctl register */ -/* - * Controls if the instruction cache is enabled or not. - * - * 0 I-Cache is disabled - * 1 I-Cache is enabled - */ -#define HPM_MCACHE_CTL_IC_EN_SHIFT (0UL) -#define HPM_MCACHE_CTL_IC_EN_MASK (1UL << HPM_MCACHE_CTL_IC_EN_SHIFT) -#define HPM_MCACHE_CTL_IC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_EN_SHIFT) & HPM_MCACHE_CTL_IC_EN_MASK) - -/* - * Controls if the data cache is enabled or not. - * - * 0 D-Cache is disabled - * 1 D-Cache is enabled - */ -#define HPM_MCACHE_CTL_DC_EN_SHIFT (1UL) -#define HPM_MCACHE_CTL_DC_EN_MASK (1UL << HPM_MCACHE_CTL_DC_EN_SHIFT) -#define HPM_MCACHE_CTL_DC_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_EN_SHIFT) & HPM_MCACHE_CTL_DC_EN_MASK) - -/* - * Parity/ECC error checking enable control for the instruction cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_IC_ECCEN_SHIFT (0x2UL) -#define HPM_MCACHE_CTL_IC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_IC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_ECCEN_SHIFT) & HPM_MCACHE_CTL_IC_ECCEN_MASK) - -/* - * - * Parity/ECC error checking enable control for the data cache. - * - * 0 Disable parity/ECC - * 1 Reserved - * 2 Generate exceptions only on uncorrectable parity/ECC errors - * 3 Generate exceptions on any type of parity/ECC errors - */ -#define HPM_MCACHE_CTL_DC_ECCEN_SHIFT (0x4UL) -#define HPM_MCACHE_CTL_DC_ECCEN_MASK (0x3UL << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) -#define HPM_MCACHE_CTL_DC_ECCEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_ECCEN_SHIFT) & HPM_MCACHE_CTL_DC_ECCEN_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the instruction cache RAMs. - * It is set to enable CCTL operations to access the ECC codes. This bit - * can be set for injecting ECC errors to test the ECC handler. - * - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_IC_RWECC_SHIFT (0x6UL) -#define HPM_MCACHE_CTL_IC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_IC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_IC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_RWECC_SHIFT) & HPM_MCACHE_CTL_IC_RWECC_MASK) - -/* - * - * Controls diagnostic accesses of ECC codes of the data cache RAMs. It is - * set to enable CCTL operations to access the ECC codes. This bit can be - * set for injecting - * - * ECC errors to test the ECC handler. - * 0 Disable diagnostic accesses of ECC codes - * 1 Enable diagnostic accesses of ECC codes - */ -#define HPM_MCACHE_CTL_DC_RWECC_SHIFT (0x7UL) -#define HPM_MCACHE_CTL_DC_RWECC_MASK (0x1UL << HPM_MCACHE_CTL_DC_RWECC_SHIFT) -#define HPM_MCACHE_CTL_DC_RWECC(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_RWECC_SHIFT) & HPM_MCACHE_CTL_DC_RWECC_MASK) - -/* - * Enable bit for Superuser-mode and User-mode software to access - * ucctlbeginaddr and ucctlcommand CSRs. - * - * 0 Disable ucctlbeginaddr and ucctlcommand accesses in S/U mode - * 1 Enable ucctlbeginaddr and ucctlcommand accesses in S/U mode - */ -#define HPM_MCACHE_CTL_CCTL_SUEN_SHIFT (0x8UL) -#define HPM_MCACHE_CTL_CCTL_SUEN_MASK (0x1UL << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) -#define HPM_MCACHE_CTL_CCTL_SUEN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_CCTL_SUEN_SHIFT) & HPM_MCACHE_CTL_CCTL_SUEN_MASK) - -/* - * This bit controls hardware prefetch for instruction fetches to cacheable - * memory regions when I-Cache size is not 0. - * - * 0 Disable hardware prefetch on instruction fetches - * 1 Enable hardware prefetch on instruction fetches - */ -#define HPM_MCACHE_CTL_IPREF_EN_SHIFT (0x9UL) -#define HPM_MCACHE_CTL_IPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_IPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_IPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IPREF_EN_SHIFT) & HPM_MCACHE_CTL_IPREF_EN_MASK) - -/* - * This bit controls hardware prefetch for load/store accesses to cacheable - * memory regions when D-Cache size is not 0. - * - * 0 Disable hardware prefetch on load/store memory accesses. - * 1 Enable hardware prefetch on load/store memory accesses. - */ -#define HPM_MCACHE_CTL_DPREF_EN_SHIFT (0x10UL) -#define HPM_MCACHE_CTL_DPREF_EN_MASK (0x1UL << HPM_MCACHE_CTL_DPREF_EN_SHIFT) -#define HPM_MCACHE_CTL_DPREF_EN(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DPREF_EN_SHIFT) & HPM_MCACHE_CTL_DPREF_EN_MASK) - -/* - * I-Cache miss allocation filling policy Value Meaning - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT (0x11UL) -#define HPM_MCACHE_CTL_IC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_IC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_IC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_IC_FIRST_WORD_MASK) - -/* - * D-Cache miss allocation filling policy - * - * 0 Cache line data is returned critical (double) word first - * 1 Cache line data is returned the lowest address (double) word first - */ -#define HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT (0x12UL) -#define HPM_MCACHE_CTL_DC_FIRST_WORD_MASK (0x1UL << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) -#define HPM_MCACHE_CTL_DC_FIRST_WORD(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_FIRST_WORD_SHIFT) & HPM_MCACHE_CTL_DC_FIRST_WORD_MASK) - -/* - * D-Cache Write-Around threshold - * - * 0 Disables streaming. All cacheable write misses allocate a cache line - * according to PMA settings. - * 1 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 4 cache lines. - * 2 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 64 cache lines. - * 3 Override PMA setting and do not allocate D-Cache entries after - * consecutive stores to 128 cache lines. - */ -#define HPM_MCACHE_CTL_DC_WAROUND_SHIFT (0x13UL) -#define HPM_MCACHE_CTL_DC_WAROUND_MASK (0x3UL << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) -#define HPM_MCACHE_CTL_DC_WAROUND(x) \ - (uint32_t)(((x) << HPM_MCACHE_CTL_DC_WAROUND_SHIFT) & HPM_MCACHE_CTL_DC_WAROUND_MASK) - -/* CCTL command list */ -#define HPM_L1C_CCTL_CMD_L1D_VA_INVAL (0UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WB (1UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_WBINVAL (2UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_LOCK (3UL) -#define HPM_L1C_CCTL_CMD_L1D_VA_UNLOCK (4UL) -#define HPM_L1C_CCTL_CMD_L1D_WBINVAL_ALL (6UL) -#define HPM_L1C_CCTL_CMD_L1D_WB_ALL (7UL) - -#define HPM_L1C_CCTL_CMD_L1I_VA_INVAL (8UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_LOCK (11UL) -#define HPM_L1C_CCTL_CMD_L1I_VA_UNLOCK (12UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_INVAL (16UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WB (17UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WBINVAL (18UL) - -#define HPM_L1C_CCTL_CMD_L1D_IX_RTAG (19UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_RDATA (20UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WTAG (21UL) -#define HPM_L1C_CCTL_CMD_L1D_IX_WDATA (22UL) - -#define HPM_L1C_CCTL_CMD_L1D_INVAL_ALL (23UL) - -#define HPM_L1C_CCTL_CMD_L1I_IX_INVAL (24UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RTAG (27UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_RDATA (28UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WTAG (29UL) -#define HPM_L1C_CCTL_CMD_L1I_IX_WDATA (30UL) - -#define HPM_L1C_CCTL_CMD_SUCCESS (1UL) -#define HPM_L1C_CCTL_CMD_FAIL (0UL) - -#ifdef __cplusplus -extern "C" { -#endif -/* get cache control register value */ -__attribute__((always_inline)) static inline uint32_t l1c_get_control(void) -{ - return read_csr(CSR_MCACHE_CTL); -} - -__attribute__((always_inline)) static inline bool l1c_dc_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_DC_EN_MASK; -} - -__attribute__((always_inline)) static inline bool l1c_ic_is_enabled(void) -{ - return l1c_get_control() & HPM_MCACHE_CTL_IC_EN_MASK; -} - -/* mcctlbeginaddress register bitfield layout for CCTL IX type command */ -#define HPM_MCCTLBEGINADDR_OFFSET_SHIFT (2UL) -#define HPM_MCCTLBEGINADDR_OFFSET_MASK ((uint32_t) 0xF << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) -#define HPM_MCCTLBEGINADDR_OFFSET(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_OFFSET_SHIFT) & HPM_MCCTLBEGINADDR_OFFSET_MASK) -#define HPM_MCCTLBEGINADDR_INDEX_SHIFT (6UL) -#define HPM_MCCTLBEGINADDR_INDEX_MASK ((uint32_t) 0x3F << HPM_MCCTLBEGINADDR_INDEX_SHIFT) -#define HPM_MCCTLBEGINADDR_INDEX(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_INDEX_SHIFT) & HPM_MCCTLBEGINADDR_INDEX_MASK) -#define HPM_MCCTLBEGINADDR_WAY_SHIFT (13UL) -#define HPM_MCCTLBEGINADDR_WAY_MASK ((uint32_t) 0x3 << HPM_MCCTLBEGINADDR_WAY_SHIFT) -#define HPM_MCCTLBEGINADDR_WAY(x) \ - (uint32_t)(((x) << HPM_MCCTLBEGINADDR_WAY_SHIFT) & HPM_MCCTLBEGINADDR_WAY_MASK) - -/* send IX command */ -__attribute__((always_inline)) static inline void l1c_cctl_address(uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); -} - -/* send command */ -__attribute__((always_inline)) static inline void l1c_cctl_cmd(uint8_t cmd) -{ - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -__attribute__((always_inline)) static inline uint32_t l1c_cctl_get_address(void) -{ - return read_csr(CSR_MCCTLBEGINADDR); -} - -/* send IX command */ -__attribute__((always_inline)) static inline - void l1c_cctl_address_cmd(uint8_t cmd, uint32_t address) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); -} - -#define HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT (2UL) -#define HPM_MCCTLDATA_I_TAG_ADDRESS_MASK (uint32_t)(0XFFFFF << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) -#define HPM_MCCTLDATA_I_TAG_ADDRESS(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_ADDRESS_SHIFT) & HPM_MCCTLDATA_I_TAG_ADDRESS_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT (29UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK_DUP(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_DUP_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_DUP_MASK) - -#define HPM_MCCTLDATA_I_TAG_LOCK_SHIFT (30UL) -#define HPM_MCCTLDATA_I_TAG_LOCK_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_I_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_I_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_I_TAG_VALID_SHIFT (31UL) -#define HPM_MCCTLDATA_I_TAG_VALID_MASK (uint32_t)(1 << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) -#define HPM_MCCTLDATA_I_TAG_VALID(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_I_TAG_VALID_SHIFT) & HPM_MCCTLDATA_I_TAG_VALID_MASK) - -#define HPM_MCCTLDATA_D_TAG_MESI_SHIFT (0UL) -#define HPM_MCCTLDATA_D_TAG_MESI_MASK (uint32_t)(0x3 << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) -#define HPM_MCCTLDATA_D_TAG_MESI(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_MESI_SHIFT) & HPM_MCCTLDATA_D_TAG_MESI_MASK) - -#define HPM_MCCTLDATA_D_TAG_LOCK_SHIFT (3UL) -#define HPM_MCCTLDATA_D_TAG_LOCK_MASK (uint32_t)(0x1 << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_LOCK(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) & HPM_MCCTLDATA_D_TAG_LOCK_MASK) - -#define HPM_MCCTLDATA_D_TAG_TAG_SHIFT (4UL) -#define HPM_MCCTLDATA_D_TAG_TAG_MASK (uint32_t)(0xFFFF << HPM_MCCTLDATA_D_TAG_LOCK_SHIFT) -#define HPM_MCCTLDATA_D_TAG_TAG(x) \ - (uint32_t)(((x) << HPM_MCCTLDATA_D_TAG_TAG_SHIFT) & HPM_MCCTLDATA_D_TAG_TAG_MASK) - -/* - * @brief Cache control command read address - * - * Send IX read tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] ecc_data ECC value - * @return data read - */ -ATTR_ALWAYS_INLINE static inline - uint32_t l1c_cctl_address_cmd_read(uint8_t cmd, uint32_t address, uint32_t *ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - *ecc_data = read_csr(CSR_MECC_CODE); - return read_csr(CSR_MCCTLDATA); -} - -/* - * @brief Cache control command write address - * - * Send IX write tag/data cmd - * @param[in] cmd Command code - * @param[in] address Target address - * @param[in] data Data to be written - * @param[in] ecc_data ECC of data - */ -ATTR_ALWAYS_INLINE static inline - void l1c_cctl_address_cmd_write(uint8_t cmd, uint32_t address, uint32_t data, uint32_t ecc_data) -{ - write_csr(CSR_MCCTLBEGINADDR, address); - write_csr(CSR_MCCTLCOMMAND, cmd); - write_csr(CSR_MCCTLDATA, data); - write_csr(CSR_MECC_CODE, ecc_data); -} - -#define HPM_L1C_CFG_SET_SHIFT (0UL) -#define HPM_L1C_CFG_SET_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SET_SHIFT) -#define HPM_L1C_CFG_WAY_SHIFT (3UL) -#define HPM_L1C_CFG_WAY_MASK (uint32_t)(0x7 << HPM_L1C_CFG_WAY_SHIFT) -#define HPM_L1C_CFG_SIZE_SHIFT (6UL) -#define HPM_L1C_CFG_SIZE_MASK (uint32_t)(0x7 << HPM_L1C_CFG_SIZE_SHIFT) -#define HPM_L1C_CFG_LOCK_SHIFT (9UL) -#define HPM_L1C_CFG_LOCK_MASK (uint32_t)(0x1 << HPM_L1C_CFG_LOCK_SHIFT) -#define HPM_L1C_CFG_ECC_SHIFT (10UL) -#define HPM_L1C_CFG_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_ECC_SHIFT) -#define HPM_L1C_CFG_LMB_SHIFT (12UL) -#define HPM_L1C_CFG_LMB_MASK (uint32_t)(0x7 << HPM_L1C_CFG_LMB_SHIFT) -#define HPM_L1C_CFG_LM_SIZE_SHIFT (15UL) -#define HPM_L1C_CFG_LM_SIZE_MASK (uint32_t)(0x1F << HPM_L1C_CFG_LM_SIZE_SHIFT) -#define HPM_L1C_CFG_LM_ECC_SHIFT (21UL) -#define HPM_L1C_CFG_LM_ECC_MASK (uint32_t)(0x3 << HPM_L1C_CFG_LM_ECC_SHIFT) -#define HPM_L1C_CFG_SETH_SHIFT (24UL) -#define HPM_L1C_CFG_SETH_MASK (uint32_t)(0x1 << HPM_L1C_CFG_SETH_SHIFT) - -/** - * @brief Align down based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_DOWN(n) ((uint32_t)(n) & ~(HPM_L1C_CACHELINE_SIZE - 1U)) - -/** - * @brief Align up based on cache line size - */ -#define HPM_L1C_CACHELINE_ALIGN_UP(n) HPM_L1C_CACHELINE_ALIGN_DOWN((uint32_t)(n) + HPM_L1C_CACHELINE_SIZE - 1U) - -/** - * @brief Get I-cache configuration - * - * @return I-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_ic_get_config(void) -{ - return read_csr(CSR_MICM_CFG); -} - -/** - * @brief Get D-cache configuration - * - * @return D-cache config register - */ -ATTR_ALWAYS_INLINE static inline uint32_t l1c_dc_get_config(void) -{ - return read_csr(CSR_MDCM_CFG); -} - -/* - * @brief D-cache disable - */ -void l1c_dc_disable(void); - -/* - * @brief D-cache enable - */ -void l1c_dc_enable(void); - -/* - * @brief D-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_dc_invalidate(uint32_t address, uint32_t size); - -/* - * @brief D-cache writeback by address - * @param[in] address Start address to be writtenback - * @param[in] size Size of memory to be writtenback - */ -void l1c_dc_writeback(uint32_t address, uint32_t size); - -/* - * @brief D-cache invalidate and writeback by address - * @param[in] address Start address to be invalidated and writtenback - * @param[in] size Size of memory to be invalidted and writtenback - */ -void l1c_dc_flush(uint32_t address, uint32_t size); - -/* - * @brief D-cache fill and lock by address - * @param[in] address Start address to be filled and locked - * @param[in] size Size of memory to be filled and locked - */ -void l1c_dc_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief I-cache disable - */ -void l1c_ic_disable(void); - -/* - * @brief I-cache enable - */ -void l1c_ic_enable(void); - -/* - * @brief I-cache invalidate by address - * @param[in] address Start address to be invalidated - * @param[in] size Size of memory to be invalidated - */ -void l1c_ic_invalidate(uint32_t address, uint32_t size); - -/* - * @brief I-cache fill and lock by address - * @param[in] address Start address to be locked - * @param[in] size Size of memory to be locked - */ -void l1c_ic_fill_lock(uint32_t address, uint32_t size); - -/* - * @brief Invalidate all icache and writeback all dcache - */ -void l1c_fence_i(void); - -/* - * @brief Invalidate all d-cache - */ -void l1c_dc_invalidate_all(void); - -/* - * @brief Writeback all d-cache - */ -void l1c_dc_writeback_all(void); - -/* - * @brief Flush all d-cache - */ -void l1c_dc_flush_all(void); - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* _HPM_L1_CACHE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_mcan_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_mcan_soc.h deleted file mode 100644 index 0d478dec0de..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_mcan_soc.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MCAN_SOC_H -#define HPM_MCAN_SOC_H - -#include -#include "hpm_mcan_regs.h" -#include "hpm_soc.h" - -#define MCAN_SOC_TSU_SRC_TWO_STAGES (1U) - -#define HPM_MCAN_EXT_TBSEL_NUM (4U) -#define HPM_MCAN_TBSEL_BASE (0xF02FF000UL) -#define HPM_MCAN_TBSEL (*(volatile uint32_t *)HPM_MCAN_TBSEL_BASE) -#define HPM_MCAN_TBSEL_BITWDITH (6U) -#define HPM_MCAN_TBSEL_MASK ((1UL << HPM_MCAN_TBSEL_BITWDITH) - 1UL) -#define HPM_MCAN_TBSEL0_SHIFT (8U) - -/** - * @brief MCAN MSG BUF base address (AHB_RAM) - */ -#define MCAN_MSG_BUF_BASE (0xF0200000UL) -#define MCAN_MSG_BUF_SIZE_IN_WORDS (640U) -#define MCAN_IP_SLOT_SIZE (0x4000U) - -/** - * @brief TSU External Timebase Sources - */ -#define MCAN_TSU_EXT_TIMEBASE_SRC_MIN (0U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_0 (MCAN_TSU_EXT_TIMEBASE_SRC_MIN) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_1 (1U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_2 (2U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3 (3U) -#define MCAN_TSU_EXT_TIMEBASE_SRC_MAX (MCAN_TSU_EXT_TIMEBASE_SRC_TBSEL_3) - -/** - * @brief MCAN TSU timebase option for each External Timebase - */ -#define MCAN_TSU_TBSEL_PTPC0 (0x20) -#define MCAN_TSU_TBSEL_MCAN0 (0x00) -#define MCAN_TSU_TBSEL_MCAN1 (0x01) -#define MCAN_TSU_TBSEL_MCAN2 (0x02) -#define MCAN_TSU_TBSEL_MCAN3 (0x03) -#define MCAN_TSU_TBSEL_MCAN4 (0x04) -#define MCAN_TSU_TBSEL_MCAN5 (0x05) -#define MCAN_TSU_TBSEL_MCAN6 (0x06) -#define MCAN_TSU_TBSEL_MCAN7 (0x07) - - -#ifdef __cpluspus -extern "C" { -#endif - -/** - * @brief Set External Timebase Source for MCAN TSU - * @param [in] ptr MCAN base - * @param [in] src External Timebase source - */ -static inline void mcan_set_tsu_ext_timebase_src(MCAN_Type *ptr, uint8_t src) -{ - if (src < HPM_MCAN_EXT_TBSEL_NUM) { - ptr->GLB_CTL = (ptr->GLB_CTL & ~MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) | MCAN_GLB_CTL_TSU_TBIN_SEL_SET(src); - } -} - -/** - * @brief Set the Source for specified external timebase - * - * @param [in] ptr MCAN base - * @param [in] ext_tbsel External TBSEL index - * @param [in] tbsel_src Timebase source selection - */ -static inline void mcan_set_tsu_tbsel_option(MCAN_Type *ptr, uint8_t ext_tbsel, uint8_t tbsel_option) -{ - (void) ptr; - if (ext_tbsel < HPM_MCAN_EXT_TBSEL_NUM) { - uint32_t tbsel_shift = (ext_tbsel * HPM_MCAN_TBSEL_BITWDITH) + HPM_MCAN_TBSEL0_SHIFT; - uint32_t tbsel_mask = HPM_MCAN_TBSEL_MASK << tbsel_shift; - HPM_MCAN_TBSEL = (HPM_MCAN_TBSEL & ~tbsel_mask) | (((uint32_t)tbsel_option << tbsel_shift) & tbsel_mask); - } -} - -/** - * @brief Enable Standby Pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_enable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL |= MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Disable Standby pin for MCAN - * @param [in] ptr MCAN base - */ -static inline void mcan_disable_standby_pin(MCAN_Type *ptr) -{ - ptr->GLB_CTL &= ~MCAN_GLB_CTL_M_CAN_STBY_MASK; -} - -/** - * @brief Get RAM base for MCAN - * @param [in] ptr MCAN base - * @return RAM base for MCAN - */ -static inline uint32_t mcan_get_ram_base(MCAN_Type *ptr) -{ - (void) ptr; - return MCAN_MSG_BUF_BASE; -} - -/** - * @brief Get the MCAN RAM offset in the dedicated/shared RAM for - * @param [in] ptr MCAN base - * @return RAM offset for MCAN - */ -static inline uint32_t mcan_get_ram_offset(MCAN_Type *ptr) -{ - uint32_t index = ((uint32_t) ptr - HPM_MCAN0_BASE) / MCAN_IP_SLOT_SIZE; - - return (index * MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); -} - -/** - * @brief Get MCAN RAM size - * @param [in] ptr MCAN base - * @return RAM size in bytes - */ -static inline uint32_t mcan_get_ram_size(MCAN_Type *ptr) -{ - (void) ptr; - return (MCAN_MSG_BUF_SIZE_IN_WORDS * sizeof(uint32_t)); -} - -#ifdef __cpluspus -} -#endif - -#endif /* HPM_MCAN_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_misc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_misc.h deleted file mode 100644 index 419d739bad8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_misc.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_MISC_H -#define HPM_MISC_H - -#define CORE0_ILM_LOCAL_BASE (0x00000000U) -#define CORE0_ILM_SIZE_IN_BYTE (0x00040000U) -#define CORE0_DLM_LOCAL_BASE (0x00200000U) -#define CORE0_DLM_SIZE_IN_BYTE (0x00040000U) -#define CORE1_ILM_LOCAL_BASE (0x00040000U) -#define CORE1_ILM_SIZE_IN_BYTE (0x00040000U) -#define CORE1_DLM_LOCAL_BASE (0x00240000U) -#define CORE1_DLM_SIZE_IN_BYTE (0x00040000U) - -#define CORE0_ILM_SYSTEM_BASE (0x00000000U) -#define CORE0_DLM_SYSTEM_BASE (0x00200000U) -#define CORE1_ILM_SYSTEM_BASE (0x00040000U) -#define CORE1_DLM_SYSTEM_BASE (0x00240000U) - -#define HPM_CORE0 (0U) -#define HPM_CORE1 (1U) - -/* map core local memory(DLM/ILM) to system address */ -static inline uint32_t core_local_mem_to_sys_address(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} - -/* map system address to core local memory(DLM/ILM) */ -static inline uint32_t sys_address_to_core_local_mem(uint8_t core_id, uint32_t addr) -{ - (void) core_id; - return addr; -} -#endif /* HPM_MISC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_otp_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_otp_drv.c deleted file mode 100644 index 2b941c74587..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_otp_drv.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_otp_drv.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -#define SHADOW_INDEX_IN_PMIC_OTP_END (15U) -#define OTP_UNLOCK_MAGIC_NUM (0x4E45504FUL) /*!< ASCII: OPEN */ -#define OTP_LOCK_MAGIC_NUM (~OTP_UNLOCK_MAGIC_NUM) -#define OTP_CMD_PROGRAM (0x574F4C42UL) /*!< ASCII: BLOW */ -#define OTP_CMD_READ (0x44414552UL) /*!< ASCII: READ */ - - -/*********************************************************************************************************************** - * Codes - **********************************************************************************************************************/ -void otp_init(void) -{ - -} - -void otp_deinit(void) -{ - -} - -uint32_t otp_read_from_shadow(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->SHADOW[addr]; - } - - return ret_val; -} - -uint32_t otp_read_from_ip(uint32_t addr) -{ - uint32_t ret_val = 0; - if (addr < ARRAY_SIZE(HPM_OTP->SHADOW)) { - ret_val = HPM_OTP->FUSE[addr]; - } - return ret_val; -} - -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - do { - uint32_t fuse_idx_max = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((addr >= fuse_idx_max) || (num_of_words > fuse_idx_max) || (addr + num_of_words > fuse_idx_max)); - - /* Enable 2.5V LDO for FUSE programming */ - uint32_t reg_val = (HPM_PCFG->LDO2P5 & ~PCFG_LDO2P5_VOLT_MASK) | PCFG_LDO2P5_ENABLE_MASK | PCFG_LDO2P5_VOLT_SET(2500); - HPM_PCFG->LDO2P5 = reg_val; - /* Wait until LDO is ready */ - while (!IS_HPM_BITMASK_SET(HPM_PCFG->LDO2P5, PCFG_DCDC_MODE_READY_MASK)) { - } - HPM_OTP->UNLOCK = OTP_UNLOCK_MAGIC_NUM; - for (uint32_t i = 0; i < num_of_words; i++) { - HPM_OTP->FUSE[addr++] = *src++; - } - HPM_OTP->UNLOCK = OTP_LOCK_MAGIC_NUM; - /* Disable 2.5V LDO after FUSE programming for saving power */ - HPM_PCFG->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_reload(otp_region_t region) -{ - hpm_stat_t status = status_invalid_argument; - if ((uint32_t)region < 0x10 && (region >= otp_region0_mask)) { - HPM_OTP->LOAD_REQ = (uint32_t)region; - HPM_OTP->LOAD_COMP = (uint32_t)region; - while (!IS_HPM_BITMASK_SET(HPM_OTP->LOAD_COMP, region)) { - - } - status = status_success; - } - - return status; -} - -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->FUSE_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option) -{ - hpm_stat_t status = status_invalid_argument; - - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW) || (lock_option > otp_lock_option_max)); - - OTP_Type *otp_base = HPM_OTP; - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - - uint32_t lock_mask = ((uint32_t)lock_option) << lock_reg_offset; - - otp_base->SHADOW_LOCK[lock_reg_idx] = lock_mask; - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words) -{ - hpm_stat_t status = status_invalid_argument; - - do { - uint32_t max_fuse_idx = ARRAY_SIZE(HPM_OTP->SHADOW); - HPM_BREAK_IF((start >= max_fuse_idx) || (num_of_words > max_fuse_idx) || ((start + num_of_words) > max_fuse_idx)); - - HPM_OTP->REGION[3] = OTP_REGION_START_SET(start) - | OTP_REGION_STOP_SET(start + num_of_words); - - status = status_success; - } while (false); - - return status; -} - -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val) -{ - hpm_stat_t status = status_invalid_argument; - do { - HPM_BREAK_IF(addr >= ARRAY_SIZE(HPM_OTP->SHADOW)); - - uint32_t lock_reg_idx = (addr << 1) / 32; - uint32_t lock_reg_offset = (addr << 1) % 32; - uint32_t lock_mask = 3U << lock_reg_offset; - - OTP_Type *otp_base = HPM_OTP; - otp_lock_option_t lock_opt = (otp_lock_option_t) ((otp_base->SHADOW_LOCK[lock_reg_idx] & lock_mask) - >> lock_reg_offset); - - if (lock_opt != otp_no_lock) { - status = otp_write_disallowed; - break; - } - - otp_base->SHADOW[addr] = val; - - status = status_success; - } while (false); - - return status; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_otp_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_otp_drv.h deleted file mode 100644 index 8c9559a9861..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_otp_drv.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_OTP_DRV_H -#define HPM_OTP_DRV_H - -/** - * @brief OTP APIs - * @defgroup otp_interface OTP driver APIs - * @{ - */ - -#include "hpm_common.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ -/** - * @brief OTP region definitions - */ -typedef enum { - otp_region0_mask = 1U, /*!< Address range: [0, 7] */ - otp_region1_mask = 2U, /*!< Address range: [8, 15] */ - otp_region2_mask = 4U, /*!< Address range: [16, 127] */ - otp_region3_mask = 8U, /*!< Address range: user defined */ -} otp_region_t; - -/** - * @brief OTP lock options - */ -typedef enum { - otp_no_lock = 0, - otp_read_only = 1, - otp_permanent_no_lock = 2, - otp_disable_access = 3, - otp_lock_option_max = otp_disable_access, -} otp_lock_option_t; - -enum { - otp_write_disallowed = MAKE_STATUS(status_group_otp, 0), -}; - -/*********************************************************************************************************************** - * Prototypes - **********************************************************************************************************************/ -#ifdef __cpluscplus -extern "C" { -#endif - -/** - * @brief Initialize OTP controller - */ -void otp_init(void); - -/** - * @brief De-initialize OTP controller - */ -void otp_deinit(void); - -/** - * @brief Read the OTP word from shadow register - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_shadow(uint32_t addr); - -/** - * @brief Read the specified OTP word from OTP IP bus - * @param [in] addr OTP word index - * @retval OTP word value - */ -uint32_t otp_read_from_ip(uint32_t addr); - -/** - * @brief Program a word to specified OTP field - * @param [in] addr OTP word index - * @param [in] src Pointer to the data to be programmed - * @param [in] num_of_words Number of words to be programmed, only 1 is allowed - * @return API execution status - */ -hpm_stat_t otp_program(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - -/** - * @brief Reload a OTP region - * @param [in] region OTP region option - * @return API execution status - */ -hpm_stat_t otp_reload(otp_region_t region); - -/** - * @brief Change the Software lock permission - * @param [in] addr OTP word index - * @param [in] lock_option OTP lcok option - * @return API execution status - */ -hpm_stat_t otp_lock_otp(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief OTP lock shadow - * @param [in] addr OTP word index - * @param [in] lock_option OTP lock option - * @return API execution status - */ -hpm_stat_t otp_lock_shadow(uint32_t addr, otp_lock_option_t lock_option); - -/** - * @brief Set the configurable region range - * @param [in] start OTP word start index - * @param [in] num_of_words Number of words in configuration region - * @retval status_out_of_range Invalid range - * @retval status_success Operation is successful - */ -hpm_stat_t otp_set_configurable_region(uint32_t start, uint32_t num_of_words); - -/** - * @return Write data to OTP shadow register - * @param [in] addr OTP word index - * @param [val] val Data to be written - * @return API execution status - */ -hpm_stat_t otp_write_shadow_register(uint32_t addr, uint32_t val); - - -#ifdef __cpluscplus -} -#endif -/** - * @} - */ - - - - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_pcfg_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_pcfg_drv.h deleted file mode 100644 index 1d18841f7ad..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_pcfg_drv.h +++ /dev/null @@ -1,497 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PCFG_DRV_H -#define HPM_PCFG_DRV_H - -#include "hpm_common.h" -#include "hpm_pcfg_regs.h" - -/** - * - * @brief PCFG driver APIs - * @defgroup pcfg_interface PCFG driver APIs - * @ingroup io_interfaces - * @{ - */ -#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON (0x3UL) -#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF (0x2UL) - -#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p)) -#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p)) - -/* @brief PCFG irc24m reference */ -typedef enum { - pcfg_irc24m_reference_32k = 0, - pcfg_irc24m_reference_24m_xtal = 1 -} pcfg_irc24m_reference_t; - -/* @brief PCFG dcdc current limit */ -typedef enum { - pcfg_dcdc_lp_current_limit_250ma = 0, - pcfg_dcdc_lp_current_limit_200ma = 1, -} pcfg_dcdc_lp_current_limit_t; - -/* @brief PCFG dcdc current hys */ -typedef enum { - pcfg_dcdc_current_hys_12_5mv = 0, - pcfg_dcdc_current_hys_25mv = 1, -} pcfg_dcdc_current_hys_t; - -/* @brief PCFG dcdc mode */ -typedef enum { - pcfg_dcdc_mode_off = 0, - pcfg_dcdc_mode_basic = 1, - pcfg_dcdc_mode_general = 3, - pcfg_dcdc_mode_expert = 7, -} pcfg_dcdc_mode_t; - -/* @brief PCFG pmc domain peripherals */ -typedef enum { - pcfg_pmc_periph_gpio = 6, - pcfg_pmc_periph_ioc = 8, - pcfg_pmc_periph_timer = 10, - pcfg_pmc_periph_wdog = 12, - pcfg_pmc_periph_uart = 14, -} pcfg_pmc_periph_t; - -/* @brief PCFG status */ -enum { - status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1), -}; - -/* @brief PCFG irc24m config */ -typedef struct { - uint32_t freq_in_hz; - pcfg_irc24m_reference_t reference; - bool return_to_default_on_xtal_loss; - bool free_run; -} pcfg_irc24m_config_t; - - -#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \ - ((uint32_t) (mode) << ((module) << 1)) - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief check if bandgap is trimmed or not - * - * @param[in] ptr base address - * - * @retval true if bandgap is trimmed - */ -static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr) -{ - return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief bandgap reload trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr) -{ - ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK; -} - -/** - * @brief turn off LDO2P5 - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr) -{ - ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief turn on LDO 2.5V - * - * @param[in] ptr base address - */ -static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr) -{ - ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK; -} - -/** - * @brief check if LDO 2.5V is stable - * - * @param[in] ptr base address - * - * @retval true if LDO2P5 is stable - */ -static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr) -{ - return PCFG_LDO2P5_READY_GET(ptr->LDO2P5); -} - -/* - * @brief check if DCDC is stable or not - * @param[in] ptr base address - * @retval true if DCDC is stable - */ -static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr) -{ - return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE); -} - -/* - * @brief set DCDC work mode - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode) -{ - ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode); -} - -/** - * @brief set low power current limit - * - * @param[in] ptr base address - * @param[in] limit current limit at low power mode - * @param[in] over_limit unused parameter, will be discarded - */ -static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit) -{ - (void) over_limit; - ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_ILIMIT_LP_MASK) | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit); -} - -/** - * @brief check if power loss flag is set - * - * @param[in] ptr base address - * - * @retval true if power loss is set - */ -static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT); -} - -/** - * @brief disable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief enable over voltage protection - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_ensable_over_voltage_prot(PCFG_Type *ptr) -{ - ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK; -} - -/** - * @brief checkover voltage flag - * - * @param[in] ptr base address - * @retval true if flag is set - */ -static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr) -{ - return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK; -} - -/** - * @brief disable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief enable current measurement - * - * @param[in] ptr base address - */ -static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr) -{ - ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK; -} - -/** - * @brief check if measured current is valid - * - * @param[in] ptr base address - * - * @retval true if measured current is valid - */ -static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr) -{ - return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK; -} - -/** - * @brief get DCDC start time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc start time in cycles - */ -static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME); -} - -/** - * @brief get DCDC resume time in number of 24MHz clock cycles - * - * @param[in] ptr base address - * - * @retval dcdc resuem time in cycles - */ -static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr) -{ - return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME); -} - -/** - * @brief set DCDC start time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles start time in cycles - */ -static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles); -} - -/** - * @brief set DCDC resuem time in 24MHz clock cycles - * - * @param[in] ptr base address - * @param[in] cycles resume time in cycles - */ -static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles) -{ - ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles); -} - -/** - * @brief set dcdc current hysteres range - * - * @param[in] ptr base address - * @param[in] range current hysteres range - */ -static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range) -{ - ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range); -} - -/** - * @brief disable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief enable power trap - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_power_trap(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK; -} - -/** - * @brief check if power trap is triggered - * - * @param[in] ptr base address - * - * @retval true if power trap is triggered - */ -static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr) -{ - return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief clear power trap trigger flag - * - * @param[in] ptr base address - */ -static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK; -} - -/** - * @brief disable dcdc retention - * - * @param[in] ptr base address - */ -static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief enable dcdc retention to retain soc sram data - * - * @param[in] ptr base address - */ -static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr) -{ - ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK; -} - -/** - * @brief clear wakeup cause flag - * - * @param[in] ptr base address - * @param[in] mask mask of flags to be cleared - */ -static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_CAUSE |= mask; -} - -/** - * @brief get wakeup cause - * - * @param[in] ptr base address - * - * @retval mask of wake cause - */ -static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr) -{ - return ptr->WAKE_CAUSE; -} - -/** - * @brief enable wakeup source - * - * @param[in] ptr base address - * @param[in] mask wakeup source mask - */ -static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK &= ~mask; -} - -/** - * @brief disable wakeup source - * - * @param[in] ptr base address - * @param[in] mask source to be disabled as wakeup source - */ -static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask) -{ - ptr->WAKE_MASK |= mask; -} - -/** - * @brief set clock gate mode in vpmc domain - * - * @param[in] ptr base address - * @param[in] mode clock gate mode mask - */ -static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode) -{ - ptr->SCG_CTRL = mode; -} - -/** - * @brief check if irc24m is trimmed - * - * @param[in] ptr base address - * - * @retval true if it is trimmed - */ -static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr) -{ - return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief reload irc24m trim value - * - * @param[in] ptr base address - */ -static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr) -{ - ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK; -} - -/** - * @brief config irc24m track - * - * @param[in] ptr base address - * @param[in] config config data - */ -void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config); - -/* - * @brief set DCDC voltage at standby mode - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 2.5V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set DCDC voltage - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief set output voltage of LDO 1V in mV - * @param[in] ptr base address - * @param[in] mv target voltage - * @retval status_success if successfully configured - */ -hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv); - -/* - * @brief get current DCDC current level in mA - * - * @param[in] ptr base address - * @retval Current level at mA - */ -uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr); - - -#ifdef __cplusplus -} -#endif -/** - * @} - */ - -#endif /* HPM_PCFG_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_plic_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_plic_drv.h deleted file mode 100644 index 8cb9d15f3da..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_plic_drv.h +++ /dev/null @@ -1,217 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PLIC_DRV_H -#define HPM_PLIC_DRV_H - -/** - * @brief PLIC driver APIs - * @defgroup plic_interface PLIC driver APIs - * @{ - */ - -#define HPM_PLIC_TARGET_M_MODE 0 -#define HPM_PLIC_TARGET_S_MODE 1 - -/* Feature Register */ -#define HPM_PLIC_FEATURE_OFFSET (0x00000000UL) -#define HPM_PLIC_FEATURE_VECTORED_MODE (0x2UL) -#define HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ (0x1UL) - -/* Priority Register - 32 bits per irq */ -#define HPM_PLIC_PRIORITY_OFFSET (0x00000004UL) -#define HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE 2 - -/* Pending Register - 1 bit per source */ -#define HPM_PLIC_PENDING_OFFSET (0x00001000UL) -#define HPM_PLIC_PENDING_SHIFT_PER_SOURCE 0 - -#define HPM_PLIC_TRIGGER_TYPE_OFFSET (0x00001080UL) -#define HPM_PLIC_TRIGGER_TYPE_SHIFT_PER_SORUCE 1 - -/* Enable Register - 0x80 per target */ -#define HPM_PLIC_ENABLE_OFFSET (0x00002000UL) -#define HPM_PLIC_ENABLE_SHIFT_PER_TARGET 7 - -/* Priority Threshold Register - 0x1000 per target */ -#define HPM_PLIC_THRESHOLD_OFFSET (0x00200000UL) -#define HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET 12 - -/* Claim Register - 0x1000 per target */ -#define HPM_PLIC_CLAIM_OFFSET (0x00200004UL) -#define HPM_PLIC_CLAIM_SHIFT_PER_TARGET 12 - -#if !defined(__ASSEMBLER__) - -/** - * @brief Set plic feature - * - * @param[in] base PLIC base address - * @param[in] feature Specific feature to be set - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_feature(uint32_t base, uint32_t feature) -{ - *(volatile uint32_t *)(base + HPM_PLIC_FEATURE_OFFSET) = feature; -} - -/** - * @brief Set plic threshold - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] threshold Threshold of IRQ can be serviced - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_threshold(uint32_t base, - uint32_t target, - uint32_t threshold) -{ - volatile uint32_t *threshold_ptr = (volatile uint32_t *)(base + - HPM_PLIC_THRESHOLD_OFFSET + - (target << HPM_PLIC_THRESHOLD_SHIFT_PER_TARGET)); - *threshold_ptr = threshold; -} - -/** - * @brief Set interrupt priority - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * @param[in] priority Priority to be assigned - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_priority(uint32_t base, - uint32_t irq, - uint32_t priority) -{ - volatile uint32_t *priority_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PRIORITY_OFFSET + ((irq-1) << HPM_PLIC_PRIORITY_SHIFT_PER_SOURCE)); - *priority_ptr = priority; -} - -/** - * @brief Set interrupt pending bit - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_set_irq_pending(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_PENDING_OFFSET + ((irq >> 5) << 2)); - *current_ptr = (1 << (irq & 0x1F)); -} - -/** - * @brief Set interrupt trigger type to edge-triggerred - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_edge_trigger(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); - *current_ptr |= (1UL << (irq & 0x1F)); -} - -/** - * @brief Set interrupt trigger type to level-triggerred - * - * @param[in] base PLIC base address - * @param[in] irq Target interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq_level_trigger(uint32_t base, uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *) (base + - HPM_PLIC_TRIGGER_TYPE_OFFSET + ((irq >> 5) << 2)); - *current_ptr &= ~(1UL << (irq & 0x1F)); -} - -/** - * @brief Enable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be enabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_enable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current | (1 << (irq & 0x1F)); - *current_ptr = current; -} - -/** - * @brief Disable interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number to be disabled - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_disable_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *current_ptr = (volatile uint32_t *)(base + - HPM_PLIC_ENABLE_OFFSET + - (target << HPM_PLIC_ENABLE_SHIFT_PER_TARGET) + - ((irq >> 5) << 2)); - uint32_t current = *current_ptr; - current = current & ~((1 << (irq & 0x1F))); - *current_ptr = current; -} - -/** - * @brief Claim interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to claim interrupt - * - */ -ATTR_ALWAYS_INLINE static inline uint32_t __plic_claim_irq(uint32_t base, uint32_t target) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - return *claim_addr; -} - -/** - * @brief Complete interrupt - * - * @param[in] base PLIC base address - * @param[in] target Target to handle specific interrupt - * @param[in] irq Interrupt number - * - */ -ATTR_ALWAYS_INLINE static inline void __plic_complete_irq(uint32_t base, - uint32_t target, - uint32_t irq) -{ - volatile uint32_t *claim_addr = (volatile uint32_t *)(base + - HPM_PLIC_CLAIM_OFFSET + - (target << HPM_PLIC_CLAIM_SHIFT_PER_TARGET)); - *claim_addr = irq; -} -#endif /* __ASSEMBLER__ */ -/** - * @} - */ -#endif /* HPM_PLIC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_pmic_iomux.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_pmic_iomux.h deleted file mode 100644 index ceefa620967..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_pmic_iomux.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMIC_IOMUX_H -#define HPM_PMIC_IOMUX_H - -/* PIOC_PY00_FUNC_CTL function mux definitions */ -#define PIOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY00_FUNC_CTL_PURT_TXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define PIOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY01_FUNC_CTL function mux definitions */ -#define PIOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY01_FUNC_CTL_PURT_RXD IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define PIOC_PY01_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY02_FUNC_CTL function mux definitions */ -#define PIOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY02_FUNC_CTL_PURT_RTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define PIOC_PY02_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY03_FUNC_CTL function mux definitions */ -#define PIOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY03_FUNC_CTL_PURT_CTS IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define PIOC_PY03_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY04_FUNC_CTL function mux definitions */ -#define PIOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY04_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY05_FUNC_CTL function mux definitions */ -#define PIOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY05_FUNC_CTL_PWDG_RSTN IOC_PAD_FUNC_CTL_ALT_SELECT_SET(1) -#define PIOC_PY05_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY06_FUNC_CTL function mux definitions */ -#define PIOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY06_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - -/* PIOC_PY07_FUNC_CTL function mux definitions */ -#define PIOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(0) -#define PIOC_PY07_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(2) -#define PIOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_CTL_ALT_SELECT_SET(3) - - -#endif /* HPM_PMIC_IOMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ppor_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ppor_drv.h deleted file mode 100644 index 01c07d1e6de..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ppor_drv.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_PPOR_DRV_H -#define HPM_PPOR_DRV_H -#include "hpm_ppor_regs.h" - -typedef enum { - ppor_reset_brownout = 1 << 0, - ppor_reset_debug = 1 << 4, - ppor_reset_wdog0 = 1 << 16, - ppor_reset_wdog1 = 1 << 17, - ppor_reset_wdog2 = 1 << 18, - ppor_reset_wdog3 = 1 << 19, - ppor_reset_pmic_wdog = 1 << 20, - ppor_reset_software = 1 << 31, -} ppor_reset_source_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * perform software reset in counter * (1/24Mhz) seconds - */ -static inline void ppor_sw_reset(PPOR_Type *ptr, uint32_t counter) -{ - ptr->SOFTWARE_RESET = PPOR_SOFTWARE_RESET_COUNTER_SET(counter); } - -/* - * clear enable reset source according to the given mask - */ -static inline void ppor_reset_mask_clear_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE &= ~mask; -} - -/* - * set enable reset source according to the given mask - */ -static inline void ppor_reset_mask_set_source_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_ENABLE |= mask; -} - -/* - * set enable reset source - */ -static inline void ppor_reset_set_source_enable(PPOR_Type *ptr, uint32_t reset_sources) -{ - ptr->RESET_ENABLE = reset_sources; -} - -/* - * get enabled reset source - */ -static inline uint32_t ppor_reset_get_enabled_source(PPOR_Type *ptr) -{ - return ptr->RESET_ENABLE; -} - -/* - * get reset status - */ -static inline uint32_t ppor_reset_get_status(PPOR_Type *ptr) -{ - return ptr->RESET_STATUS; -} - -/* - * get reset flags - */ -static inline uint32_t ppor_reset_get_flags(PPOR_Type *ptr) -{ - return ptr->RESET_FLAG; -} - -/* - * clear reset flags - */ -static inline void ppor_reset_clear_flags(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_FLAG = mask; -} - -/* - * get reset hold - */ -static inline uint32_t ppor_reset_get_hold(PPOR_Type *ptr) -{ - return ptr->RESET_HOLD; -} - -/* - * set reset hold - */ -static inline void ppor_reset_set_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD |= mask; -} - -/* - * clear reset hold - */ -static inline void ppor_reset_clear_hold_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_HOLD &= ~mask; -} - -/* - * set cold reset - */ -static inline void ppor_reset_set_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE &= ~mask; -} - -/* - * clear cold reset - */ -static inline void ppor_reset_clear_cold_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE |= mask; -} - -/* - * set hot reset - */ -static inline void ppor_reset_set_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE |= mask; -} - -/* - * clear hot reset - */ -static inline void ppor_reset_clear_hot_reset_enable(PPOR_Type *ptr, uint32_t mask) -{ - ptr->RESET_TYPE &= ~mask; -} - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_romapi.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_romapi.h deleted file mode 100644 index c889e7d8fc8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_romapi.h +++ /dev/null @@ -1,985 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_H -#define HPM_ROMAPI_H - -/** - * @brief ROM APIs - * @defgroup romapi_interface ROM APIs - * @{ - */ - -#include "hpm_common.h" -#include "hpm_otp_drv.h" -#include "hpm_romapi_xpi_def.h" -#include "hpm_romapi_xpi_soc_def.h" -#include "hpm_romapi_xpi_nor_def.h" -#include "hpm_romapi_xpi_ram_def.h" -#include "hpm_sdp_drv.h" - -/* XPI0 base address */ -#define HPM_XPI0_BASE (0xF3000000UL) /**< XPI0 Base address */ -/* XPI0 base pointer */ -#define HPM_XPI0 ((XPI_Type *) HPM_XPI0_BASE) /**< XPI0 Base pointer */ - - -/*********************************************************************************************************************** - * - * - * Definitions - * - * - **********************************************************************************************************************/ -/** - * @brief Enter Bootloader API argument - */ -typedef union { - uint32_t U; - struct { - uint32_t index: 8; /**< Image index */ - uint32_t peripheral: 8; /**< Boot peripheral */ - uint32_t src: 8; /**< Boot source */ - uint32_t tag: 8; /**< ROM API parameter tag, must be 0xEB */ - }; -} api_boot_arg_t; - -/*EXiP Region Parameter */ -typedef struct { - uint32_t start; /**< Start address, must be 4KB aligned */ - uint32_t len; /**< Must be 4KB aligned */ - uint8_t key[16]; /**< AES Key */ - uint8_t ctr[8]; /**< Initial Vector/Counter */ -} exip_region_param_t; - -typedef struct { - uint32_t region_start; - uint32_t region_end; - uint8_t aes_key[16]; - uint8_t nonce[8]; - uint8_t index; - bool enable; - bool valid; - bool lock; -} exip_region_context_t; - -#define API_BOOT_TAG (0xEBU) /**< ROM API parameter tag */ -#define API_BOOT_SRC_OTP (0U) /**< Boot source: OTP */ -#define API_BOOT_SRC_PRIMARY (1U) /**< Boot source: Primary */ -#define API_BOOT_SRC_SERIAL_BOOT (2U) /**< Boot source: Serial Boot */ -#define API_BOOT_SRC_ISP (3U) /**< Boot source: ISP */ -#define API_BOOT_PERIPH_AUTO (0U) /**< Boot peripheral: Auto detected */ -#define API_BOOT_PERIPH_UART (1U) /**< Boot peripheral: UART */ -#define API_BOOT_PERIPH_USBHID (2U) /**< Boot Peripheral: USB-HID */ - -/** - * @brief OTP driver interface - */ -typedef struct { - /**< OTP driver interface version */ - uint32_t version; - /**< OTP driver interface: init */ - void (*init)(void); - /**< OTP driver interface: deinit */ - void (*deinit)(void); - /**< OTP driver interface: read from shadow */ - uint32_t (*read_from_shadow)(uint32_t addr); - /**< OTP driver interface: read from ip */ - uint32_t (*read_from_ip)(uint32_t addr); - /**< OTP driver interface: program */ - hpm_stat_t (*program)(uint32_t addr, const uint32_t *src, uint32_t num_of_words); - /**< OTP driver interface: reload */ - hpm_stat_t (*reload)(otp_region_t region); - /**< OTP driver interface: lock */ - hpm_stat_t (*lock)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: lock_shadow */ - hpm_stat_t (*lock_shadow)(uint32_t addr, otp_lock_option_t lock_option); - /**< OTP driver interface: set_configurable_region */ - hpm_stat_t (*set_configurable_region)(uint32_t start, uint32_t num_of_words); - /**< OTP driver interface: write_shadow_register */ - hpm_stat_t (*write_shadow_register)(uint32_t addr, uint32_t data); -} otp_driver_interface_t; - -/** - * @brief XPI driver interface - */ -typedef struct { - /**< XPI driver interface: version */ - uint32_t version; - /**< XPI driver interface: get default configuration */ - hpm_stat_t (*get_default_config)(xpi_config_t *xpi_config); - /**< XPI driver interface: get default device configuration */ - hpm_stat_t (*get_default_device_config)(xpi_device_config_t *dev_config); - /**< XPI driver interface: initialize the XPI using xpi_config */ - hpm_stat_t (*init)(XPI_Type *base, xpi_config_t *xpi_config); - /**< XPI driver interface: configure the AHB buffer */ - hpm_stat_t (*config_ahb_buffer)(XPI_Type *base, xpi_ahb_buffer_cfg_t *ahb_buf_cfg); - /**< XPI driver interface: configure the device */ - hpm_stat_t (*config_device)(XPI_Type *base, xpi_device_config_t *dev_cfg, xpi_channel_t channel); - /**< XPI driver interface: update instruction talbe */ - hpm_stat_t (*update_instr_table)(XPI_Type *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num); - /**< XPI driver interface: transfer command/data using block interface */ - hpm_stat_t (*transfer_blocking)(XPI_Type *base, xpi_xfer_ctx_t *xfer); - /**< Software reset the XPI controller */ - void (*software_reset)(XPI_Type *base); - /**< XPI driver interface: Check whether IP is idle */ - bool (*is_idle)(XPI_Type *base); - /**< XPI driver interface: update delay line setting */ - void (*update_dllcr)(XPI_Type *base, - uint32_t serial_root_clk_freq, - uint32_t data_valid_time, - xpi_channel_t channel, - uint32_t dly_target); - /**< XPI driver interface: Get absolute address for APB transfer */ - hpm_stat_t - (*get_abs_apb_xfer_addr)(XPI_Type *base, xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr); -} xpi_driver_interface_t; - -/** - * @brief XPI RAM driver interface - */ -typedef struct { - /**< XPI RAM driver interface: API version */ - uint32_t version; - - /**< Get XPI RAM configuration based on cfg_option */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_ram_config_t *ram_cfg, xpi_ram_config_option_t *cfg_option); - - /**< XPI RAM driver interface: Initialize XPI RAM */ - hpm_stat_t (*init)(XPI_Type *base, xpi_ram_config_t *ram_cfg); -} xpi_ram_driver_interface_t; - - -/** - * @brief XPI NOR driver interface - */ -typedef struct { - /**< XPI NOR driver interface: API version */ - uint32_t version; - /**< XPI NOR driver interface: Get FLASH configuration */ - hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - /**< XPI NOR driver interface: initialize FLASH */ - hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Enable write access to FLASH */ - hpm_stat_t - (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Get FLASH status register */ - hpm_stat_t (*get_status)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status); - /**< XPI NOR driver interface: Wait when FLASH is still busy */ - hpm_stat_t - (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: erase a specified FLASH region */ - hpm_stat_t (*erase)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: Erase the whole FLASH */ - hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - /**< XPI NOR driver interface: Erase specified FLASH sector */ - hpm_stat_t - (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Erase specified FLASH block */ - hpm_stat_t - (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr); - /**< XPI NOR driver interface: Program data to specified FLASH address */ - hpm_stat_t (*program)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: read data from specified FLASH address */ - hpm_stat_t (*read)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length); - /**< XPI NOR driver interface: program FLASH page using nonblocking interface */ - hpm_stat_t (*page_program_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length); - /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */ - hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */ - hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr); - /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */ - hpm_stat_t - (*erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config); - - uint32_t reserved0[3]; - - /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */ - hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option); - - /**< XPI NOR driver interface: Get FLASH properties */ - hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value); - -} xpi_nor_driver_interface_t; - -/** - * @brief EXIP driver interface - */ -typedef struct { - uint32_t version; - hpm_stat_t (*enable)(XPI_Type *base); - hpm_stat_t (*disable)(XPI_Type *base); - hpm_stat_t (*lock_reg_access)(XPI_Type *base); - hpm_stat_t (*configure_region)(XPI_Type *base, const exip_region_context_t *ctx); - - bool (*remap_config)(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset); - bool (*remap_enabled)(XPI_Type *base); - void (*remap_disable)(XPI_Type *base); - bool (*exip_region_config)(XPI_Type *base, uint32_t index, exip_region_param_t *param); - void (*exip_region_disable)(XPI_Type *base, uint32_t index); -} exip_driver_interface_t; - -/** - * @brief SDP API interface - */ -typedef struct { - /**< SDP API interface: API version */ - uint32_t version; - /**< SDP API interface: Initialize IP */ - hpm_stat_t (*sdp_ip_init)(void); - /**< SDP API interface: Deinitialize IP */ - hpm_stat_t (*sdp_ip_deinit)(void); - /**< SDP API interface: Set AES key */ - hpm_stat_t (*aes_set_key)(sdp_aes_ctx_t *aes_ctx, const uint8_t *key, sdp_aes_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: AES ECB crypto operation */ - hpm_stat_t (*aes_crypt_ecb)(sdp_aes_ctx_t *aes_ctx, sdp_aes_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API interface: AES CBC crypto operation */ - hpm_stat_t (*aes_crypt_cbc)(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API interface: AES CTR crypto operation */ - hpm_stat_t - (*aes_crypt_ctr)(sdp_aes_ctx_t *aes_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API interface: AES CCM encryption */ - hpm_stat_t (*aes_ccm_gen_enc)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: AES CCM Decrypt and verify */ - hpm_stat_t (*aes_ccm_dec_verify)(sdp_aes_ctx_t *aes_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); - /**< SDP API interface: memcpy */ - hpm_stat_t (*memcpy)(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length); - /**< SDP API interface: memset */ - hpm_stat_t (*memset)(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length); - /**< SDP API interface: HASH initialization */ - hpm_stat_t (*hash_init)(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg); - /**< SDP API interface: HASH update */ - hpm_stat_t (*hash_update)(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length); - /**< SDP API interface: HASH finish */ - hpm_stat_t (*hash_finish)(sdp_hash_ctx_t *hash_ctx, uint8_t *digest); - /**< SDP API interface: Set SM4 Key */ - hpm_stat_t (*sm4_set_key)(sdp_sm4_ctx_t *sm4_ctx, const uint8_t *key, sdp_sm4_key_bits_t keybits, uint32_t key_idx); - /**< SDP API interface: SM4 Crypto ECB mode */ - hpm_stat_t (*sm4_crypt_ecb)(sdp_sm4_ctx_t *sm4_ctx, sdp_sm4_op_t op, uint32_t len, const uint8_t *in, uint8_t *out); - /**< SDP API Interface: SM4 Crypto CBC mode*/ - hpm_stat_t (*sm4_crypt_cbc)(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *input, - uint8_t *output); - /**< SDP API Interface: SM4 CTR mode */ - hpm_stat_t - (*sm4_crypt_ctr)(sdp_sm4_ctx_t *sm4_ctx, uint8_t *nonce_ctr, uint8_t *input, uint8_t *output, uint32_t length); - /**< SDP API Interface: SM4 CCM Encryption */ - hpm_stat_t (*sm4_ccm_gen_enc)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - uint8_t *tag, - uint32_t tag_len); - /**< SDP API Interface: SM4 CCM Decrypt and Verify */ - hpm_stat_t (*sm4_ccm_dec_verify)(sdp_sm4_ctx_t *sm4_ctx, - uint32_t input_len, - const uint8_t *nonce, - uint32_t nonce_len, - const uint8_t *aad, - uint32_t aad_len, - const uint8_t *input, - uint8_t *output, - const uint8_t *tag, - uint32_t tag_len); -} sdp_driver_interface_t; - -/** - * @brief Bootloader API table - */ -typedef struct { - /**< Bootloader API table: version */ - const uint32_t version; - /**< Bootloader API table: copyright string address */ - const char *copyright; - /**< Bootloader API table: run_bootloader API */ - hpm_stat_t (*run_bootloader)(void *arg); - /**< Bootloader API table: otp driver interface address */ - const otp_driver_interface_t *otp_driver_if; - /**< Bootloader API table: xpi driver interface address */ - const xpi_driver_interface_t *xpi_driver_if; - /**< Bootloader API table: xpi nor driver interface address */ - const xpi_nor_driver_interface_t *xpi_nor_driver_if; - /**< Bootloader API table: xpi ram driver interface address */ - const xpi_ram_driver_interface_t *xpi_ram_driver_if; - /**< Bootloader API table: sdp driver interface address */ - const sdp_driver_interface_t *sdp_driver_if; - const uint32_t reserved1[3]; - const exip_driver_interface_t *exip_api_if; - const uint32_t family_id; -} bootloader_api_table_t; - -/**< Bootloader API table Root */ -#define ROM_API_TABLE_ROOT ((const bootloader_api_table_t *)0x2001FF00U) - - -#ifdef __cplusplus -extern "C" { -#endif - -/*********************************************************************************************************************** - * - * - * Enter bootloader Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Eneter specified Boot mode - * @param [in] ctx Enter bootloader context - * @retval status_invalid Invalid parameters were deteced - */ -static inline hpm_stat_t rom_enter_bootloader(void *ctx) -{ - return ROM_API_TABLE_ROOT->run_bootloader(ctx); -} - -/*********************************************************************************************************************** - * - * - * XPI NOR Driver Wrapper - * - * - **********************************************************************************************************************/ - -/** - * @brief Get XPI NOR configuration via cfg_option - * @param [in] base XPI base address - * @param [out] nor_cfg XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_config(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_config(base, nor_cfg, cfg_option); -} - -/** - * @brief Initialize XPI NOR based on nor_config - * @param [in] base XPI base address - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_init(XPI_Type *base, xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->init(base, nor_config); -} - -/** - * @brief Erase specified FLASH region - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI nOR configuration - * @param[in] start Erase address start address - * @param[in] length Region size to be erased - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(base, channel, nor_config, start, length); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH sector in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Sector address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_sector_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_sector_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase specified FLASH blcok in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(base, channel, nor_config, start); - fencei(); - return status; -} - -/** - * @brief Erase specified FLASH blcok in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] start Block address - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_block_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t start) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block_nonblocking(base, channel, nor_config, start); -} - -/** - * @brief Erase the whole FLASH in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(base, channel, nor_config); -} - -/** - * @brief Erase the whole FLASH in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_erase_chip_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip_nonblocking(base, channel, nor_config); - fencei(); - return status; -} - -/** - * @brief Program data to specified FLASH address in blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_program(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - hpm_stat_t status = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(base, channel, nor_config, src, dst_addr, length); - fencei(); - return status; -} - -/** - * @brief Page-Program data to specified FLASH address in non-blocking way - * @param[in] base XPI base address - * @param[in] channel XPI transfer channel - * @param[in] nor_config XPI NOR configuration - * @param[in] src data source address - * @param[in] dst_addr Destination FLASH address - * @param[in] length length of data to be programmed - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_page_program_nonblocking(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - const uint32_t *src, - uint32_t dst_addr, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if - ->page_program_nonblocking(base, channel, nor_config, src, dst_addr, length); -} - -/** - * @brief Read data from specified FLASH address - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] dst Memory start address to store the data read out from FLASH - * @param [in] start FLASH address for data read - * @param [in] length length of data to be read out - * @return API execution address - */ -static inline hpm_stat_t rom_xpi_nor_read(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t *dst, - uint32_t start, - uint32_t length) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(base, channel, nor_config, dst, start, length); -} - -/** - * @brief Automatically configure XPI NOR based on cfg_option - * @param [in] base XPI base address - * @param [out] config XPI NOR configuration structure - * @param [in] cfg_option XPI NOR configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_auto_config(XPI_Type *base, - xpi_nor_config_t *config, - xpi_nor_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(base, config, cfg_option); -} - -/** - * @brief Get XPI NOR properties - * @param [in] base XPI base address - * @param [in] nor_cfg XPI NOR configuration structure - * @param [in] property_id - * @param [out] value property value retrieved by this API - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_property(XPI_Type *base, - xpi_nor_config_t *nor_cfg, - uint32_t property_id, - uint32_t *value) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_property(base, nor_cfg, property_id, value); -} - -/** - * @brief Return the status register value on XPI NOR FLASH - * - * @param [in] base XPI base address - * @param [in] channel XPI transfer channel - * @param [in] nor_config XPI NOR configuration - * @param [in] addr FLASH address offset - * @param [out] out_status FLASH status register value - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_nor_get_status(XPI_Type *base, - xpi_xfer_channel_t channel, - const xpi_nor_config_t *nor_config, - uint32_t addr, - uint16_t *out_status) -{ - return ROM_API_TABLE_ROOT->xpi_nor_driver_if->get_status(base, channel, nor_config, addr, out_status); -} - -/** - * @brief Configure the XPI Address Remapping Logic - * @param [in] base XPI base address - * @param [in] start Start Address (memory mapped address) - * @param [in] len Size for the remapping region - * @param [in] offset Relative address based on parameter "start" - * @retval true is all parameters are valid - * @retval false if any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_remap_config(XPI_Type *base, uint32_t start, uint32_t len, uint32_t offset) -{ - return ROM_API_TABLE_ROOT->exip_api_if->remap_config(base, start, len, offset); -} - -/** - * @brief Disable XPI Remapping logic - * @param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_remap_disable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->remap_disable(base); - fencei(); -} - -/** - * @brief Check whether XPI Remapping is enabled - * @param [in] base XPI base address - * - * @retval true Remapping logic is enabled - * @retval false Remapping logic is disabled - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_is_remap_enabled(XPI_Type *base) -{ - return ROM_API_TABLE_ROOT->exip_api_if->remap_enabled(base); -} - -/** - * @brief Configure Specified EXiP Region - * @param [in] base XPI base address - * @param [in] index EXiP Region index - * @param [in] param ExiP Region Parameter - * @retval true All parameters are valid - * @retval false Any parameter is invalid - */ -ATTR_RAMFUNC -static inline bool rom_xpi_nor_exip_region_config(XPI_Type *base, uint32_t index, exip_region_param_t *param) -{ - bool result = ROM_API_TABLE_ROOT->exip_api_if->exip_region_config(base, index, param); - ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(base); - fencei(); - return result; -} - -/** - * @brief Disable EXiP Feature on specified EXiP Region - * @@param [in] base XPI base address - * @param [in] index EXiP Region index - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_region_disable(XPI_Type *base, uint32_t index) -{ - ROM_API_TABLE_ROOT->exip_api_if->exip_region_disable(base, index); - fencei(); -} - -/** - * @brief Enable global EXiP logic - * @@param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_enable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->enable(base); - fencei(); -} - -/** - * @brief Disable global EXiP logic - * @@param [in] base XPI base address - */ -ATTR_RAMFUNC -static inline void rom_xpi_nor_exip_disable(XPI_Type *base) -{ - ROM_API_TABLE_ROOT->exip_api_if->disable(base); - fencei(); -} - -/*********************************************************************************************************************** - * - * - * XPI RAM Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Get XPI RAM configuration based on cfg_option - * @param [in] base XPI base address - * @param [out] ram_cfg XPI RAM configuration structure - * @param [in] cfg_option XPI RAM configuration option - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_get_config(XPI_Type *base, - xpi_ram_config_t *ram_cfg, - xpi_ram_config_option_t *cfg_option) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->get_config(base, ram_cfg, cfg_option); -} - -/** - * @brief Initialize XPI RAM - * @param [in] base XPI base address - * @param [in] ram_cfg XPI ram configuration - * @return API execution status - */ -static inline hpm_stat_t rom_xpi_ram_init(XPI_Type *base, xpi_ram_config_t *ram_cfg) -{ - return ROM_API_TABLE_ROOT->xpi_ram_driver_if->init(base, ram_cfg); -} - -/*********************************************************************************************************************** - * - * - * SDP Driver Wrapper - * - * - **********************************************************************************************************************/ -/** - * @brief Initialize SDP IP - */ -static inline void rom_sdp_init(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_init(); -} - -/** - * @brief De-initialize SDP IP - */ -static inline void rom_sdp_deinit(void) -{ - ROM_API_TABLE_ROOT->sdp_driver_if->sdp_ip_deinit(); -} - -/** - * @brief Set AES key to SDP - * @param [in] aes_ctx AES context - * @param [in] key AES key buffer - * @param [in] key_bits AES key-bit option - * @param[in] key_idx AES key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_set_key(sdp_aes_ctx_t *aes_ctx, - const uint8_t *key, - sdp_aes_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_set_key(aes_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP AES ECB crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] len Data length for AES encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_ecb(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_ecb(aes_ctx, op, len, in, out); -} - -/** - * @brief SDP AES CBC crypto operation(Encrypt or Decrypt) - * @param [in] aes_ctx AES context - * @param [in] op AES operation: encrypt or decrypt - * @param [in] length Data length for AES encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_aes_crypt_cbc(sdp_aes_ctx_t *aes_ctx, - sdp_aes_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->aes_crypt_cbc(aes_ctx, op, length, iv, in, out); -} - -/** - * @brief Set SM4 key to SDP - * @param [in] sm4_ctx SM4 context - * @param [in] key SM4 key buffer - * @param [in] key_bits SM4 key-bit option - * @param[in] key_idx SM4 key index - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_set_key(sdp_sm4_ctx_t *sm4_ctx, - const uint8_t *key, - sdp_sm4_key_bits_t key_bits, - uint32_t key_idx) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_set_key(sm4_ctx, key, key_bits, key_idx); -} - -/** - * @brief SDP SM4 ECB crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] len Data length for SM4 encryption/decryption - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_ecb(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t len, - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_ecb(sm4_ctx, op, len, in, out); -} - -/** - * @brief SDP SM4 CBC crypto operation(Encrypt or Decrypt) - * @param [in] sm4_ctx SM4 context - * @param [in] op SM4 operation: encrypt or decrypt - * @param [in] length Data length for SM4 encryption/decryption - * @param [in] iv Initial vector/nonce - * @param [in] in Input data - * @param [out] out Output data - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_sm4_crypt_cbc(sdp_sm4_ctx_t *sm4_ctx, - sdp_sm4_op_t op, - uint32_t length, - uint8_t iv[16], - const uint8_t *in, - uint8_t *out) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->sm4_crypt_cbc(sm4_ctx, op, length, iv, in, out); -} - -/** - * @brief HASH initialization - * @param [in] hash_ctx HASH context - * @param [in] alg HASH algorithm - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_init(sdp_hash_ctx_t *hash_ctx, sdp_hash_alg_t alg) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_init(hash_ctx, alg); -} - -/** - * @brief HASH Update - * @param [in] hash_ctx HASH context - * @param [in] data Data for HASH operation - * @param [in] length of the data for HASH operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_update(sdp_hash_ctx_t *hash_ctx, const uint8_t *data, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_update(hash_ctx, data, length); -} - -/** - * @brief HASH finialize - * @param [in] hash_ctx HASH context - * @param [out] digest the output digest - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_hash_finish(sdp_hash_ctx_t *hash_ctx, uint8_t *digest) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->hash_finish(hash_ctx, digest); -} - -/** - * @brief SDP memcpy operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memcpy - * @param [in] src Source address for memcpy - * @param [in] length Size of data for memcpy operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memcpy(sdp_dma_ctx_t *dma_ctx, void *dst, const void *src, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memcpy(dma_ctx, dst, src, length); -} - -/** - * @brief SDP memset operation - * @param [in] dma_ctx DMA context - * @param [out] dst Destination address for memset - * @param [in] pattern pattern for memset - * @param [in] length Size of data for memset operation - * @return API execution status - */ -static inline hpm_stat_t rom_sdp_memset(sdp_dma_ctx_t *dma_ctx, void *dst, uint8_t pattern, uint32_t length) -{ - return ROM_API_TABLE_ROOT->sdp_driver_if->memset(dma_ctx, dst, pattern, length); -} - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - - -#endif /* HPM_ROMAPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_romapi_xpi_soc_def.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_romapi_xpi_soc_def.h deleted file mode 100644 index ea3ba9e8f9b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_romapi_xpi_soc_def.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_ROMAPI_XPI_SOC_DEF_H -#define HPM_ROMAPI_XPI_SOC_DEF_H - -#include "hpm_common.h" -#include "hpm_romapi_xpi_def.h" - -/*********************************************************************************************************************** - * Definitions - **********************************************************************************************************************/ - -#define XPI_CLK_OUT_FREQ_OPTION_30MHz (1U) -#define XPI_CLK_OUT_FREQ_OPTION_50MHz (2U) -#define XPI_CLK_OUT_FREQ_OPTION_66MHz (3U) -#define XPI_CLK_OUT_FREQ_OPTION_80MHz (4U) -#define XPI_CLK_OUT_FREQ_OPTION_104MHz (5U) -#define XPI_CLK_OUT_FREQ_OPTION_120MHz (6U) -#define XPI_CLK_OUT_FREQ_OPTION_133MHz (7U) -#define XPI_CLK_OUT_FREQ_OPTION_166MHz (8U) -#define XPI_CLK_OUT_FREQ_OPTION_200MHz (9U) - -typedef struct { - struct { - uint8_t priority; /* Offset: 0x00 */ - uint8_t master_idx; /* Offset: 0x01 */ - uint8_t buf_size_in_dword; /* Offset: 0x02 */ - bool enable_prefetch; /* Offset: 0x03 */ - } entry[8]; -} xpi_ahb_buffer_cfg_t; - -typedef struct { - uint8_t data_pads; - xpi_channel_t channel; - xpi_io_group_t io_group; - uint8_t drive_strength; - bool enable_dqs; - bool enable_diff_clk; -} xpi_io_config_t; - -typedef enum { - xpi_freq_type_typical, - xpi_freq_type_mhz, -} clk_freq_type_t; - -typedef enum { - xpi_clk_src_auto, - xpi_clk_src_osc, - xpi_clk_src_pll0clk0, - xpi_clk_src_pll1clk0, - xpi_clk_src_pll1clk1, - xpi_clk_src_pll2clk0, - xpi_clk_src_pll2clk1, - xpi_clk_src_pll3clk0, - xpi_clk_src_pll4clk0, -} xpi_clk_src_t; - - -typedef union { - struct { - uint8_t freq; - bool enable_ddr; - xpi_clk_src_t clk_src; - clk_freq_type_t freq_type; - }; - uint32_t freq_opt; -} xpi_clk_config_t; - -typedef enum { - xpi_clock_bus, - xpi_clock_serial_root, - xpi_clock_serial, -} xpi_clock_t; - -#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ses_reg.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ses_reg.xml deleted file mode 100644 index a571b7b36a0..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ses_reg.xml +++ /dev/null @@ -1,88039 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ses_riscv_cpu_regs.xml b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ses_riscv_cpu_regs.xml deleted file mode 100644 index ec5ba6cb980..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_ses_riscv_cpu_regs.xml +++ /dev/null @@ -1,1098 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc.h deleted file mode 100644 index 1cec95c63b5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc.h +++ /dev/null @@ -1,991 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SOC_H -#define HPM_SOC_H - - -/* List of external IRQs */ -#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */ -#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */ -#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */ -#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */ -#define IRQn_GPIO0_E 5 /* GPIO0_E IRQ */ -#define IRQn_GPIO0_F 6 /* GPIO0_F IRQ */ -#define IRQn_GPIO0_V 7 /* GPIO0_V IRQ */ -#define IRQn_GPIO0_W 8 /* GPIO0_W IRQ */ -#define IRQn_GPIO0_X 9 /* GPIO0_X IRQ */ -#define IRQn_GPIO0_Y 10 /* GPIO0_Y IRQ */ -#define IRQn_GPIO0_Z 11 /* GPIO0_Z IRQ */ -#define IRQn_GPIO1_A 12 /* GPIO1_A IRQ */ -#define IRQn_GPIO1_B 13 /* GPIO1_B IRQ */ -#define IRQn_GPIO1_C 14 /* GPIO1_C IRQ */ -#define IRQn_GPIO1_D 15 /* GPIO1_D IRQ */ -#define IRQn_GPIO1_E 16 /* GPIO1_E IRQ */ -#define IRQn_GPIO1_F 17 /* GPIO1_F IRQ */ -#define IRQn_GPIO1_V 18 /* GPIO1_V IRQ */ -#define IRQn_GPIO1_W 19 /* GPIO1_W IRQ */ -#define IRQn_GPIO1_X 20 /* GPIO1_X IRQ */ -#define IRQn_GPIO1_Y 21 /* GPIO1_Y IRQ */ -#define IRQn_GPIO1_Z 22 /* GPIO1_Z IRQ */ -#define IRQn_GPTMR0 23 /* GPTMR0 IRQ */ -#define IRQn_GPTMR1 24 /* GPTMR1 IRQ */ -#define IRQn_GPTMR2 25 /* GPTMR2 IRQ */ -#define IRQn_GPTMR3 26 /* GPTMR3 IRQ */ -#define IRQn_GPTMR4 27 /* GPTMR4 IRQ */ -#define IRQn_GPTMR5 28 /* GPTMR5 IRQ */ -#define IRQn_GPTMR6 29 /* GPTMR6 IRQ */ -#define IRQn_GPTMR7 30 /* GPTMR7 IRQ */ -#define IRQn_UART0 31 /* UART0 IRQ */ -#define IRQn_UART1 32 /* UART1 IRQ */ -#define IRQn_UART2 33 /* UART2 IRQ */ -#define IRQn_UART3 34 /* UART3 IRQ */ -#define IRQn_UART4 35 /* UART4 IRQ */ -#define IRQn_UART5 36 /* UART5 IRQ */ -#define IRQn_UART6 37 /* UART6 IRQ */ -#define IRQn_UART7 38 /* UART7 IRQ */ -#define IRQn_I2C0 39 /* I2C0 IRQ */ -#define IRQn_I2C1 40 /* I2C1 IRQ */ -#define IRQn_I2C2 41 /* I2C2 IRQ */ -#define IRQn_I2C3 42 /* I2C3 IRQ */ -#define IRQn_SPI0 43 /* SPI0 IRQ */ -#define IRQn_SPI1 44 /* SPI1 IRQ */ -#define IRQn_SPI2 45 /* SPI2 IRQ */ -#define IRQn_SPI3 46 /* SPI3 IRQ */ -#define IRQn_TSNS 47 /* TSNS IRQ */ -#define IRQn_MBX0A 48 /* MBX0A IRQ */ -#define IRQn_MBX0B 49 /* MBX0B IRQ */ -#define IRQn_MBX1A 50 /* MBX1A IRQ */ -#define IRQn_MBX1B 51 /* MBX1B IRQ */ -#define IRQn_EWDG0 52 /* EWDG0 IRQ */ -#define IRQn_EWDG1 53 /* EWDG1 IRQ */ -#define IRQn_EWDG2 54 /* EWDG2 IRQ */ -#define IRQn_EWDG3 55 /* EWDG3 IRQ */ -#define IRQn_HDMA 56 /* HDMA IRQ */ -#define IRQn_LOBS 57 /* LOBS IRQ */ -#define IRQn_ADC0 58 /* ADC0 IRQ */ -#define IRQn_ADC1 59 /* ADC1 IRQ */ -#define IRQn_ADC2 60 /* ADC2 IRQ */ -#define IRQn_ADC3 61 /* ADC3 IRQ */ -#define IRQn_ACMP0_0 62 /* ACMP0[0] IRQ */ -#define IRQn_ACMP0_1 63 /* ACMP0[1] IRQ */ -#define IRQn_ACMP1_0 64 /* ACMP1[0] IRQ */ -#define IRQn_ACMP1_1 65 /* ACMP1[1] IRQ */ -#define IRQn_ACMP2_0 66 /* ACMP2[0] IRQ */ -#define IRQn_ACMP2_1 67 /* ACMP2[1] IRQ */ -#define IRQn_ACMP3_0 68 /* ACMP3[0] IRQ */ -#define IRQn_ACMP3_1 69 /* ACMP3[1] IRQ */ -#define IRQn_I2S0 70 /* I2S0 IRQ */ -#define IRQn_I2S1 71 /* I2S1 IRQ */ -#define IRQn_DAO 72 /* DAO IRQ */ -#define IRQn_PDM 73 /* PDM IRQ */ -#define IRQn_UART8 74 /* UART8 IRQ */ -#define IRQn_UART9 75 /* UART9 IRQ */ -#define IRQn_UART10 76 /* UART10 IRQ */ -#define IRQn_UART11 77 /* UART11 IRQ */ -#define IRQn_UART12 78 /* UART12 IRQ */ -#define IRQn_UART13 79 /* UART13 IRQ */ -#define IRQn_UART14 80 /* UART14 IRQ */ -#define IRQn_UART15 81 /* UART15 IRQ */ -#define IRQn_I2C4 82 /* I2C4 IRQ */ -#define IRQn_I2C5 83 /* I2C5 IRQ */ -#define IRQn_I2C6 84 /* I2C6 IRQ */ -#define IRQn_I2C7 85 /* I2C7 IRQ */ -#define IRQn_SPI4 86 /* SPI4 IRQ */ -#define IRQn_SPI5 87 /* SPI5 IRQ */ -#define IRQn_SPI6 88 /* SPI6 IRQ */ -#define IRQn_SPI7 89 /* SPI7 IRQ */ -#define IRQn_MCAN0 90 /* MCAN0 IRQ */ -#define IRQn_MCAN1 91 /* MCAN1 IRQ */ -#define IRQn_MCAN2 92 /* MCAN2 IRQ */ -#define IRQn_MCAN3 93 /* MCAN3 IRQ */ -#define IRQn_MCAN4 94 /* MCAN4 IRQ */ -#define IRQn_MCAN5 95 /* MCAN5 IRQ */ -#define IRQn_MCAN6 96 /* MCAN6 IRQ */ -#define IRQn_MCAN7 97 /* MCAN7 IRQ */ -#define IRQn_PTPC 98 /* PTPC IRQ */ -#define IRQn_QEI0 99 /* QEI0 IRQ */ -#define IRQn_QEI1 100 /* QEI1 IRQ */ -#define IRQn_QEI2 101 /* QEI2 IRQ */ -#define IRQn_QEI3 102 /* QEI3 IRQ */ -#define IRQn_PWM0 103 /* PWM0 IRQ */ -#define IRQn_PWM1 104 /* PWM1 IRQ */ -#define IRQn_PWM2 105 /* PWM2 IRQ */ -#define IRQn_PWM3 106 /* PWM3 IRQ */ -#define IRQn_RDC0 107 /* RDC0 IRQ */ -#define IRQn_RDC1 108 /* RDC1 IRQ */ -#define IRQn_SDM0 109 /* SDM0 IRQ */ -#define IRQn_SDM1 110 /* SDM1 IRQ */ -#define IRQn_SEI_0 111 /* SEI[0] IRQ */ -#define IRQn_SEI_1 112 /* SEI[1] IRQ */ -#define IRQn_SEI_2 113 /* SEI[2] IRQ */ -#define IRQn_SEI_3 114 /* SEI[3] IRQ */ -#define IRQn_MTG0 115 /* MTG0 IRQ */ -#define IRQn_MTG1 116 /* MTG1 IRQ */ -#define IRQn_VSC0 117 /* VSC0 IRQ */ -#define IRQn_VSC1 118 /* VSC1 IRQ */ -#define IRQn_CLC0_0 119 /* CLC0[0] IRQ */ -#define IRQn_CLC0_1 120 /* CLC0[1] IRQ */ -#define IRQn_CLC1_0 121 /* CLC1[0] IRQ */ -#define IRQn_CLC1_1 122 /* CLC1[1] IRQ */ -#define IRQn_TRGMUX0 123 /* TRGMUX0 IRQ */ -#define IRQn_TRGMUX1 124 /* TRGMUX1 IRQ */ -#define IRQn_ENET0 125 /* ENET0 IRQ */ -#define IRQn_NTMR0 126 /* NTMR0 IRQ */ -#define IRQn_USB0 127 /* USB0 IRQ */ -#define IRQn_TSW_0 128 /* TSW[0] IRQ */ -#define IRQn_TSW_1 129 /* TSW[1] IRQ */ -#define IRQn_TSW_2 130 /* TSW[2] IRQ */ -#define IRQn_TSW_3 131 /* TSW[3] IRQ */ -#define IRQn_TSW_PTP_EVT 132 /* TSW_PTP_EVT IRQ */ -#define IRQn_ESC 133 /* ESC IRQ */ -#define IRQn_ESC_SYNC0 134 /* ESC_SYNC0 IRQ */ -#define IRQn_ESC_SYNC1 135 /* ESC_SYNC1 IRQ */ -#define IRQn_ESC_RESET 136 /* ESC_RESET IRQ */ -#define IRQn_XPI0 137 /* XPI0 IRQ */ -#define IRQn_FEMC 138 /* FEMC IRQ */ -#define IRQn_PPI 139 /* PPI IRQ */ -#define IRQn_XDMA 140 /* XDMA IRQ */ -#define IRQn_FFA 141 /* FFA IRQ */ -#define IRQn_SDP 142 /* SDP IRQ */ -#define IRQn_RNG 143 /* RNG IRQ */ -#define IRQn_PKA 144 /* PKA IRQ */ -#define IRQn_PSEC 145 /* PSEC IRQ */ -#define IRQn_PGPIO 146 /* PGPIO IRQ */ -#define IRQn_PEWDG 147 /* PEWDG IRQ */ -#define IRQn_PTMR 148 /* PTMR IRQ */ -#define IRQn_PUART 149 /* PUART IRQ */ -#define IRQn_FUSE 150 /* FUSE IRQ */ -#define IRQn_SECMON 151 /* SECMON IRQ */ -#define IRQn_RTC 152 /* RTC IRQ */ -#define IRQn_PAD_WAKEUP 153 /* PAD_WAKEUP IRQ */ -#define IRQn_BGPIO 154 /* BGPIO IRQ */ -#define IRQn_BVIO 155 /* BVIO IRQ */ -#define IRQn_BROWNOUT 156 /* BROWNOUT IRQ */ -#define IRQn_SYSCTL 157 /* SYSCTL IRQ */ -#define IRQn_CPU0 158 /* CPU0 IRQ */ -#define IRQn_CPU1 159 /* CPU1 IRQ */ -#define IRQn_DEBUG0 160 /* DEBUG0 IRQ */ -#define IRQn_DEBUG1 161 /* DEBUG1 IRQ */ - -#include "hpm_common.h" - -#include "hpm_gpio_regs.h" -/* Address of GPIO instances */ -/* FGPIO base address */ -#define HPM_FGPIO_BASE (0x300000UL) -/* FGPIO base pointer */ -#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE) -/* GPIO0 base address */ -#define HPM_GPIO0_BASE (0xF00D0000UL) -/* GPIO0 base pointer */ -#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE) -/* GPIO1 base address */ -#define HPM_GPIO1_BASE (0xF00D4000UL) -/* GPIO1 base pointer */ -#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE) -/* PGPIO base address */ -#define HPM_PGPIO_BASE (0xF411C000UL) -/* PGPIO base pointer */ -#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE) -/* BGPIO base address */ -#define HPM_BGPIO_BASE (0xF4214000UL) -/* BGPIO base pointer */ -#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE) - -/* Address of DM instances */ -/* DM base address */ -#define HPM_DM_BASE (0x30000000UL) - -#include "hpm_plic_regs.h" -/* Address of PLIC instances */ -/* PLIC base address */ -#define HPM_PLIC_BASE (0xE4000000UL) -/* PLIC base pointer */ -#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE) - -#include "hpm_mchtmr_regs.h" -/* Address of MCHTMR instances */ -/* MCHTMR base address */ -#define HPM_MCHTMR_BASE (0xE6000000UL) -/* MCHTMR base pointer */ -#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE) - -#include "hpm_plic_sw_regs.h" -/* Address of PLICSW instances */ -/* PLICSW base address */ -#define HPM_PLICSW_BASE (0xE6400000UL) -/* PLICSW base pointer */ -#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE) - -#include "hpm_gptmr_regs.h" -/* Address of GPTMR instances */ -/* GPTMR0 base address */ -#define HPM_GPTMR0_BASE (0xF0000000UL) -/* GPTMR0 base pointer */ -#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE) -/* GPTMR1 base address */ -#define HPM_GPTMR1_BASE (0xF0004000UL) -/* GPTMR1 base pointer */ -#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE) -/* GPTMR2 base address */ -#define HPM_GPTMR2_BASE (0xF0008000UL) -/* GPTMR2 base pointer */ -#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE) -/* GPTMR3 base address */ -#define HPM_GPTMR3_BASE (0xF000C000UL) -/* GPTMR3 base pointer */ -#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE) -/* GPTMR4 base address */ -#define HPM_GPTMR4_BASE (0xF0010000UL) -/* GPTMR4 base pointer */ -#define HPM_GPTMR4 ((GPTMR_Type *) HPM_GPTMR4_BASE) -/* GPTMR5 base address */ -#define HPM_GPTMR5_BASE (0xF0014000UL) -/* GPTMR5 base pointer */ -#define HPM_GPTMR5 ((GPTMR_Type *) HPM_GPTMR5_BASE) -/* GPTMR6 base address */ -#define HPM_GPTMR6_BASE (0xF0018000UL) -/* GPTMR6 base pointer */ -#define HPM_GPTMR6 ((GPTMR_Type *) HPM_GPTMR6_BASE) -/* GPTMR7 base address */ -#define HPM_GPTMR7_BASE (0xF001C000UL) -/* GPTMR7 base pointer */ -#define HPM_GPTMR7 ((GPTMR_Type *) HPM_GPTMR7_BASE) -/* NTMR0 base address */ -#define HPM_NTMR0_BASE (0xF1410000UL) -/* NTMR0 base pointer */ -#define HPM_NTMR0 ((GPTMR_Type *) HPM_NTMR0_BASE) -/* NTMR1 base address */ -#define HPM_NTMR1_BASE (0xF1414000UL) -/* NTMR1 base pointer */ -#define HPM_NTMR1 ((GPTMR_Type *) HPM_NTMR1_BASE) -/* PTMR base address */ -#define HPM_PTMR_BASE (0xF4120000UL) -/* PTMR base pointer */ -#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE) - -#include "hpm_uart_regs.h" -/* Address of UART instances */ -/* UART0 base address */ -#define HPM_UART0_BASE (0xF0040000UL) -/* UART0 base pointer */ -#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE) -/* UART1 base address */ -#define HPM_UART1_BASE (0xF0044000UL) -/* UART1 base pointer */ -#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE) -/* UART2 base address */ -#define HPM_UART2_BASE (0xF0048000UL) -/* UART2 base pointer */ -#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE) -/* UART3 base address */ -#define HPM_UART3_BASE (0xF004C000UL) -/* UART3 base pointer */ -#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE) -/* UART4 base address */ -#define HPM_UART4_BASE (0xF0050000UL) -/* UART4 base pointer */ -#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE) -/* UART5 base address */ -#define HPM_UART5_BASE (0xF0054000UL) -/* UART5 base pointer */ -#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE) -/* UART6 base address */ -#define HPM_UART6_BASE (0xF0058000UL) -/* UART6 base pointer */ -#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE) -/* UART7 base address */ -#define HPM_UART7_BASE (0xF005C000UL) -/* UART7 base pointer */ -#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE) -/* UART8 base address */ -#define HPM_UART8_BASE (0xF0180000UL) -/* UART8 base pointer */ -#define HPM_UART8 ((UART_Type *) HPM_UART8_BASE) -/* UART9 base address */ -#define HPM_UART9_BASE (0xF0184000UL) -/* UART9 base pointer */ -#define HPM_UART9 ((UART_Type *) HPM_UART9_BASE) -/* UART10 base address */ -#define HPM_UART10_BASE (0xF0188000UL) -/* UART10 base pointer */ -#define HPM_UART10 ((UART_Type *) HPM_UART10_BASE) -/* UART11 base address */ -#define HPM_UART11_BASE (0xF018C000UL) -/* UART11 base pointer */ -#define HPM_UART11 ((UART_Type *) HPM_UART11_BASE) -/* UART12 base address */ -#define HPM_UART12_BASE (0xF0190000UL) -/* UART12 base pointer */ -#define HPM_UART12 ((UART_Type *) HPM_UART12_BASE) -/* UART13 base address */ -#define HPM_UART13_BASE (0xF0194000UL) -/* UART13 base pointer */ -#define HPM_UART13 ((UART_Type *) HPM_UART13_BASE) -/* UART14 base address */ -#define HPM_UART14_BASE (0xF0198000UL) -/* UART14 base pointer */ -#define HPM_UART14 ((UART_Type *) HPM_UART14_BASE) -/* UART15 base address */ -#define HPM_UART15_BASE (0xF019C000UL) -/* UART15 base pointer */ -#define HPM_UART15 ((UART_Type *) HPM_UART15_BASE) -/* PUART base address */ -#define HPM_PUART_BASE (0xF4124000UL) -/* PUART base pointer */ -#define HPM_PUART ((UART_Type *) HPM_PUART_BASE) - -#include "hpm_i2c_regs.h" -/* Address of I2C instances */ -/* I2C0 base address */ -#define HPM_I2C0_BASE (0xF0060000UL) -/* I2C0 base pointer */ -#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE) -/* I2C1 base address */ -#define HPM_I2C1_BASE (0xF0064000UL) -/* I2C1 base pointer */ -#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE) -/* I2C2 base address */ -#define HPM_I2C2_BASE (0xF0068000UL) -/* I2C2 base pointer */ -#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE) -/* I2C3 base address */ -#define HPM_I2C3_BASE (0xF006C000UL) -/* I2C3 base pointer */ -#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE) -/* I2C4 base address */ -#define HPM_I2C4_BASE (0xF01A0000UL) -/* I2C4 base pointer */ -#define HPM_I2C4 ((I2C_Type *) HPM_I2C4_BASE) -/* I2C5 base address */ -#define HPM_I2C5_BASE (0xF01A4000UL) -/* I2C5 base pointer */ -#define HPM_I2C5 ((I2C_Type *) HPM_I2C5_BASE) -/* I2C6 base address */ -#define HPM_I2C6_BASE (0xF01A8000UL) -/* I2C6 base pointer */ -#define HPM_I2C6 ((I2C_Type *) HPM_I2C6_BASE) -/* I2C7 base address */ -#define HPM_I2C7_BASE (0xF01AC000UL) -/* I2C7 base pointer */ -#define HPM_I2C7 ((I2C_Type *) HPM_I2C7_BASE) - -#include "hpm_spi_regs.h" -/* Address of SPI instances */ -/* SPI0 base address */ -#define HPM_SPI0_BASE (0xF0070000UL) -/* SPI0 base pointer */ -#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE) -/* SPI1 base address */ -#define HPM_SPI1_BASE (0xF0074000UL) -/* SPI1 base pointer */ -#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE) -/* SPI2 base address */ -#define HPM_SPI2_BASE (0xF0078000UL) -/* SPI2 base pointer */ -#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE) -/* SPI3 base address */ -#define HPM_SPI3_BASE (0xF007C000UL) -/* SPI3 base pointer */ -#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE) -/* SPI4 base address */ -#define HPM_SPI4_BASE (0xF01B0000UL) -/* SPI4 base pointer */ -#define HPM_SPI4 ((SPI_Type *) HPM_SPI4_BASE) -/* SPI5 base address */ -#define HPM_SPI5_BASE (0xF01B4000UL) -/* SPI5 base pointer */ -#define HPM_SPI5 ((SPI_Type *) HPM_SPI5_BASE) -/* SPI6 base address */ -#define HPM_SPI6_BASE (0xF01B8000UL) -/* SPI6 base pointer */ -#define HPM_SPI6 ((SPI_Type *) HPM_SPI6_BASE) -/* SPI7 base address */ -#define HPM_SPI7_BASE (0xF01BC000UL) -/* SPI7 base pointer */ -#define HPM_SPI7 ((SPI_Type *) HPM_SPI7_BASE) - -#include "hpm_crc_regs.h" -/* Address of CRC instances */ -/* CRC base address */ -#define HPM_CRC_BASE (0xF0080000UL) -/* CRC base pointer */ -#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE) - -#include "hpm_tsns_regs.h" -/* Address of TSNS instances */ -/* TSNS base address */ -#define HPM_TSNS_BASE (0xF0090000UL) -/* TSNS base pointer */ -#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE) - -#include "hpm_mbx_regs.h" -/* Address of MBX instances */ -/* MBX0A base address */ -#define HPM_MBX0A_BASE (0xF00A0000UL) -/* MBX0A base pointer */ -#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE) -/* MBX0B base address */ -#define HPM_MBX0B_BASE (0xF00A4000UL) -/* MBX0B base pointer */ -#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE) -/* MBX1A base address */ -#define HPM_MBX1A_BASE (0xF00A8000UL) -/* MBX1A base pointer */ -#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE) -/* MBX1B base address */ -#define HPM_MBX1B_BASE (0xF00AC000UL) -/* MBX1B base pointer */ -#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE) - -#include "hpm_ewdg_regs.h" -/* Address of EWDG instances */ -/* EWDG0 base address */ -#define HPM_EWDG0_BASE (0xF00B0000UL) -/* EWDG0 base pointer */ -#define HPM_EWDG0 ((EWDG_Type *) HPM_EWDG0_BASE) -/* EWDG1 base address */ -#define HPM_EWDG1_BASE (0xF00B4000UL) -/* EWDG1 base pointer */ -#define HPM_EWDG1 ((EWDG_Type *) HPM_EWDG1_BASE) -/* EWDG2 base address */ -#define HPM_EWDG2_BASE (0xF00B8000UL) -/* EWDG2 base pointer */ -#define HPM_EWDG2 ((EWDG_Type *) HPM_EWDG2_BASE) -/* EWDG3 base address */ -#define HPM_EWDG3_BASE (0xF00BC000UL) -/* EWDG3 base pointer */ -#define HPM_EWDG3 ((EWDG_Type *) HPM_EWDG3_BASE) -/* PEWDG base address */ -#define HPM_PEWDG_BASE (0xF4128000UL) -/* PEWDG base pointer */ -#define HPM_PEWDG ((EWDG_Type *) HPM_PEWDG_BASE) - -#include "hpm_dmamux_regs.h" -/* Address of DMAMUX instances */ -/* DMAMUX base address */ -#define HPM_DMAMUX_BASE (0xF00C4000UL) -/* DMAMUX base pointer */ -#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE) - -#include "hpm_dmav2_regs.h" -/* Address of DMAV2 instances */ -/* HDMA base address */ -#define HPM_HDMA_BASE (0xF00C8000UL) -/* HDMA base pointer */ -#define HPM_HDMA ((DMAV2_Type *) HPM_HDMA_BASE) -/* XDMA base address */ -#define HPM_XDMA_BASE (0xF3100000UL) -/* XDMA base pointer */ -#define HPM_XDMA ((DMAV2_Type *) HPM_XDMA_BASE) - -#include "hpm_ppi_regs.h" -/* Address of PPI instances */ -/* PPI base address */ -#define HPM_PPI_BASE (0xF00CC000UL) -/* PPI base pointer */ -#define HPM_PPI ((PPI_Type *) HPM_PPI_BASE) - -#include "hpm_gpiom_regs.h" -/* Address of GPIOM instances */ -/* GPIOM base address */ -#define HPM_GPIOM_BASE (0xF00D8000UL) -/* GPIOM base pointer */ -#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE) - -#include "hpm_lobs_regs.h" -/* Address of LOBS instances */ -/* LOBS base address */ -#define HPM_LOBS_BASE (0xF00DC000UL) -/* LOBS base pointer */ -#define HPM_LOBS ((LOBS_Type *) HPM_LOBS_BASE) - -#include "hpm_adc16_regs.h" -/* Address of ADC16 instances */ -/* ADC0 base address */ -#define HPM_ADC0_BASE (0xF0100000UL) -/* ADC0 base pointer */ -#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE) -/* ADC1 base address */ -#define HPM_ADC1_BASE (0xF0104000UL) -/* ADC1 base pointer */ -#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE) -/* ADC2 base address */ -#define HPM_ADC2_BASE (0xF0108000UL) -/* ADC2 base pointer */ -#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE) -/* ADC3 base address */ -#define HPM_ADC3_BASE (0xF010C000UL) -/* ADC3 base pointer */ -#define HPM_ADC3 ((ADC16_Type *) HPM_ADC3_BASE) - -#include "hpm_acmp_regs.h" -/* Address of ACMP instances */ -/* ACMP0 base address */ -#define HPM_ACMP0_BASE (0xF0130000UL) -/* ACMP0 base pointer */ -#define HPM_ACMP0 ((ACMP_Type *) HPM_ACMP0_BASE) -/* ACMP1 base address */ -#define HPM_ACMP1_BASE (0xF0134000UL) -/* ACMP1 base pointer */ -#define HPM_ACMP1 ((ACMP_Type *) HPM_ACMP1_BASE) -/* ACMP2 base address */ -#define HPM_ACMP2_BASE (0xF0138000UL) -/* ACMP2 base pointer */ -#define HPM_ACMP2 ((ACMP_Type *) HPM_ACMP2_BASE) -/* ACMP3 base address */ -#define HPM_ACMP3_BASE (0xF013C000UL) -/* ACMP3 base pointer */ -#define HPM_ACMP3 ((ACMP_Type *) HPM_ACMP3_BASE) - -#include "hpm_i2s_regs.h" -/* Address of I2S instances */ -/* I2S0 base address */ -#define HPM_I2S0_BASE (0xF0140000UL) -/* I2S0 base pointer */ -#define HPM_I2S0 ((I2S_Type *) HPM_I2S0_BASE) -/* I2S1 base address */ -#define HPM_I2S1_BASE (0xF0144000UL) -/* I2S1 base pointer */ -#define HPM_I2S1 ((I2S_Type *) HPM_I2S1_BASE) - -#include "hpm_dao_regs.h" -/* Address of DAO instances */ -/* DAO base address */ -#define HPM_DAO_BASE (0xF0150000UL) -/* DAO base pointer */ -#define HPM_DAO ((DAO_Type *) HPM_DAO_BASE) - -#include "hpm_pdm_regs.h" -/* Address of PDM instances */ -/* PDM base address */ -#define HPM_PDM_BASE (0xF0154000UL) -/* PDM base pointer */ -#define HPM_PDM ((PDM_Type *) HPM_PDM_BASE) - -#include "hpm_mcan_regs.h" -/* Address of MCAN instances */ -/* MCAN0 base address */ -#define HPM_MCAN0_BASE (0xF0300000UL) -/* MCAN0 base pointer */ -#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE) -/* MCAN1 base address */ -#define HPM_MCAN1_BASE (0xF0304000UL) -/* MCAN1 base pointer */ -#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE) -/* MCAN2 base address */ -#define HPM_MCAN2_BASE (0xF0308000UL) -/* MCAN2 base pointer */ -#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE) -/* MCAN3 base address */ -#define HPM_MCAN3_BASE (0xF030C000UL) -/* MCAN3 base pointer */ -#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE) -/* MCAN4 base address */ -#define HPM_MCAN4_BASE (0xF0310000UL) -/* MCAN4 base pointer */ -#define HPM_MCAN4 ((MCAN_Type *) HPM_MCAN4_BASE) -/* MCAN5 base address */ -#define HPM_MCAN5_BASE (0xF0314000UL) -/* MCAN5 base pointer */ -#define HPM_MCAN5 ((MCAN_Type *) HPM_MCAN5_BASE) -/* MCAN6 base address */ -#define HPM_MCAN6_BASE (0xF0318000UL) -/* MCAN6 base pointer */ -#define HPM_MCAN6 ((MCAN_Type *) HPM_MCAN6_BASE) -/* MCAN7 base address */ -#define HPM_MCAN7_BASE (0xF031C000UL) -/* MCAN7 base pointer */ -#define HPM_MCAN7 ((MCAN_Type *) HPM_MCAN7_BASE) - -#include "hpm_ptpc_regs.h" -/* Address of PTPC instances */ -/* PTPC base address */ -#define HPM_PTPC_BASE (0xF037C000UL) -/* PTPC base pointer */ -#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE) - -#include "hpm_qeiv2_regs.h" -/* Address of QEIV2 instances */ -/* QEI0 base address */ -#define HPM_QEI0_BASE (0xF0400000UL) -/* QEI0 base pointer */ -#define HPM_QEI0 ((QEIV2_Type *) HPM_QEI0_BASE) -/* QEI1 base address */ -#define HPM_QEI1_BASE (0xF0404000UL) -/* QEI1 base pointer */ -#define HPM_QEI1 ((QEIV2_Type *) HPM_QEI1_BASE) -/* QEI2 base address */ -#define HPM_QEI2_BASE (0xF0408000UL) -/* QEI2 base pointer */ -#define HPM_QEI2 ((QEIV2_Type *) HPM_QEI2_BASE) -/* QEI3 base address */ -#define HPM_QEI3_BASE (0xF040C000UL) -/* QEI3 base pointer */ -#define HPM_QEI3 ((QEIV2_Type *) HPM_QEI3_BASE) - -#include "hpm_qeov2_regs.h" -/* Address of QEOV2 instances */ -/* QEO0 base address */ -#define HPM_QEO0_BASE (0xF0410000UL) -/* QEO0 base pointer */ -#define HPM_QEO0 ((QEOV2_Type *) HPM_QEO0_BASE) -/* QEO1 base address */ -#define HPM_QEO1_BASE (0xF0414000UL) -/* QEO1 base pointer */ -#define HPM_QEO1 ((QEOV2_Type *) HPM_QEO1_BASE) -/* QEO2 base address */ -#define HPM_QEO2_BASE (0xF0418000UL) -/* QEO2 base pointer */ -#define HPM_QEO2 ((QEOV2_Type *) HPM_QEO2_BASE) -/* QEO3 base address */ -#define HPM_QEO3_BASE (0xF041C000UL) -/* QEO3 base pointer */ -#define HPM_QEO3 ((QEOV2_Type *) HPM_QEO3_BASE) - -#include "hpm_pwmv2_regs.h" -/* Address of PWMV2 instances */ -/* PWM0 base address */ -#define HPM_PWM0_BASE (0xF0420000UL) -/* PWM0 base pointer */ -#define HPM_PWM0 ((PWMV2_Type *) HPM_PWM0_BASE) -/* PWM1 base address */ -#define HPM_PWM1_BASE (0xF0424000UL) -/* PWM1 base pointer */ -#define HPM_PWM1 ((PWMV2_Type *) HPM_PWM1_BASE) -/* PWM2 base address */ -#define HPM_PWM2_BASE (0xF0428000UL) -/* PWM2 base pointer */ -#define HPM_PWM2 ((PWMV2_Type *) HPM_PWM2_BASE) -/* PWM3 base address */ -#define HPM_PWM3_BASE (0xF042C000UL) -/* PWM3 base pointer */ -#define HPM_PWM3 ((PWMV2_Type *) HPM_PWM3_BASE) - -#include "hpm_rdc_regs.h" -/* Address of RDC instances */ -/* RDC0 base address */ -#define HPM_RDC0_BASE (0xF0440000UL) -/* RDC0 base pointer */ -#define HPM_RDC0 ((RDC_Type *) HPM_RDC0_BASE) -/* RDC1 base address */ -#define HPM_RDC1_BASE (0xF0444000UL) -/* RDC1 base pointer */ -#define HPM_RDC1 ((RDC_Type *) HPM_RDC1_BASE) - -#include "hpm_sdm_regs.h" -/* Address of SDM instances */ -/* SDM0 base address */ -#define HPM_SDM0_BASE (0xF0450000UL) -/* SDM0 base pointer */ -#define HPM_SDM0 ((SDM_Type *) HPM_SDM0_BASE) -/* SDM1 base address */ -#define HPM_SDM1_BASE (0xF0454000UL) -/* SDM1 base pointer */ -#define HPM_SDM1 ((SDM_Type *) HPM_SDM1_BASE) - -#include "hpm_plb_regs.h" -/* Address of PLB instances */ -/* PLB base address */ -#define HPM_PLB_BASE (0xF0460000UL) -/* PLB base pointer */ -#define HPM_PLB ((PLB_Type *) HPM_PLB_BASE) - -#include "hpm_synt_regs.h" -/* Address of SYNT instances */ -/* SYNT base address */ -#define HPM_SYNT_BASE (0xF0464000UL) -/* SYNT base pointer */ -#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE) - -#include "hpm_sei_regs.h" -/* Address of SEI instances */ -/* SEI base address */ -#define HPM_SEI_BASE (0xF0470000UL) -/* SEI base pointer */ -#define HPM_SEI ((SEI_Type *) HPM_SEI_BASE) - -#include "hpm_trgm_regs.h" -/* Address of TRGM instances */ -/* TRGM0 base address */ -#define HPM_TRGM0_BASE (0xF047C000UL) -/* TRGM0 base pointer */ -#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE) - -#include "hpm_mtg_regs.h" -/* Address of MTG instances */ -/* MTG0 base address */ -#define HPM_MTG0_BASE (0xF0490000UL) -/* MTG0 base pointer */ -#define HPM_MTG0 ((MTG_Type *) HPM_MTG0_BASE) -/* MTG1 base address */ -#define HPM_MTG1_BASE (0xF0494000UL) -/* MTG1 base pointer */ -#define HPM_MTG1 ((MTG_Type *) HPM_MTG1_BASE) - -#include "hpm_vsc_regs.h" -/* Address of VSC instances */ -/* VSC0 base address */ -#define HPM_VSC0_BASE (0xF04A0000UL) -/* VSC0 base pointer */ -#define HPM_VSC0 ((VSC_Type *) HPM_VSC0_BASE) -/* VSC1 base address */ -#define HPM_VSC1_BASE (0xF04A4000UL) -/* VSC1 base pointer */ -#define HPM_VSC1 ((VSC_Type *) HPM_VSC1_BASE) - -#include "hpm_clc_regs.h" -/* Address of CLC instances */ -/* CLC0 base address */ -#define HPM_CLC0_BASE (0xF04B0000UL) -/* CLC0 base pointer */ -#define HPM_CLC0 ((CLC_Type *) HPM_CLC0_BASE) -/* CLC1 base address */ -#define HPM_CLC1_BASE (0xF04B4000UL) -/* CLC1 base pointer */ -#define HPM_CLC1 ((CLC_Type *) HPM_CLC1_BASE) - -#include "hpm_enet_regs.h" -/* Address of ENET instances */ -/* ENET0 base address */ -#define HPM_ENET0_BASE (0xF1400000UL) -/* ENET0 base pointer */ -#define HPM_ENET0 ((ENET_Type *) HPM_ENET0_BASE) -/* ENET1 base address */ -#define HPM_ENET1_BASE (0xF1404000UL) -/* ENET1 base pointer */ -#define HPM_ENET1 ((ENET_Type *) HPM_ENET1_BASE) - -#include "hpm_usb_regs.h" -/* Address of USB instances */ -/* USB0 base address */ -#define HPM_USB0_BASE (0xF1420000UL) -/* USB0 base pointer */ -#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE) - -#include "hpm_tsw_regs.h" -/* Address of TSW instances */ -/* TSW base address */ -#define HPM_TSW_BASE (0xF1600000UL) -/* TSW base pointer */ -#define HPM_TSW ((TSW_Type *) HPM_TSW_BASE) - -#include "hpm_esc_regs.h" -/* Address of ESC instances */ -/* ESC base address */ -#define HPM_ESC_BASE (0xF1700000UL) -/* ESC base pointer */ -#define HPM_ESC ((ESC_Type *) HPM_ESC_BASE) - -#include "hpm_femc_regs.h" -/* Address of FEMC instances */ -/* FEMC base address */ -#define HPM_FEMC_BASE (0xF300C000UL) -/* FEMC base pointer */ -#define HPM_FEMC ((FEMC_Type *) HPM_FEMC_BASE) - -/* Address of ROMC instances */ -/* ROMC base address */ -#define HPM_ROMC_BASE (0xF3104000UL) - -#include "hpm_ffa_regs.h" -/* Address of FFA instances */ -/* FFA base address */ -#define HPM_FFA_BASE (0xF3108000UL) -/* FFA base pointer */ -#define HPM_FFA ((FFA_Type *) HPM_FFA_BASE) - -#include "hpm_sdp_regs.h" -/* Address of SDP instances */ -/* SDP base address */ -#define HPM_SDP_BASE (0xF3140000UL) -/* SDP base pointer */ -#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE) - -#include "hpm_psec_regs.h" -/* Address of PSEC instances */ -/* PSEC base address */ -#define HPM_PSEC_BASE (0xF3144000UL) -/* PSEC base pointer */ -#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE) - -#include "hpm_pmon_regs.h" -/* Address of PMON instances */ -/* PMON base address */ -#define HPM_PMON_BASE (0xF3148000UL) -/* PMON base pointer */ -#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE) - -#include "hpm_rng_regs.h" -/* Address of RNG instances */ -/* RNG base address */ -#define HPM_RNG_BASE (0xF314C000UL) -/* RNG base pointer */ -#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE) - -#include "hpm_keym_regs.h" -/* Address of KEYM instances */ -/* KEYM base address */ -#define HPM_KEYM_BASE (0xF3154000UL) -/* KEYM base pointer */ -#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE) - -#include "hpm_otp_regs.h" -/* Address of OTP instances */ -/* OTP base address */ -#define HPM_OTP_BASE (0xF3158000UL) -/* OTP base pointer */ -#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE) - -#include "hpm_sysctl_regs.h" -/* Address of SYSCTL instances */ -/* SYSCTL base address */ -#define HPM_SYSCTL_BASE (0xF4000000UL) -/* SYSCTL base pointer */ -#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE) - -#include "hpm_ioc_regs.h" -/* Address of IOC instances */ -/* IOC base address */ -#define HPM_IOC_BASE (0xF4040000UL) -/* IOC base pointer */ -#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE) -/* PIOC base address */ -#define HPM_PIOC_BASE (0xF4118000UL) -/* PIOC base pointer */ -#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE) -/* BIOC base address */ -#define HPM_BIOC_BASE (0xF4210000UL) -/* BIOC base pointer */ -#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE) - -#include "hpm_pllctlv2_regs.h" -/* Address of PLLCTLV2 instances */ -/* PLLCTLV2 base address */ -#define HPM_PLLCTLV2_BASE (0xF40C0000UL) -/* PLLCTLV2 base pointer */ -#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE) - -#include "hpm_ppor_regs.h" -/* Address of PPOR instances */ -/* PPOR base address */ -#define HPM_PPOR_BASE (0xF4100000UL) -/* PPOR base pointer */ -#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE) - -#include "hpm_pcfg_regs.h" -/* Address of PCFG instances */ -/* PCFG base address */ -#define HPM_PCFG_BASE (0xF4104000UL) -/* PCFG base pointer */ -#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE) - -#include "hpm_pdgo_regs.h" -/* Address of PDGO instances */ -/* PDGO base address */ -#define HPM_PDGO_BASE (0xF4134000UL) -/* PDGO base pointer */ -#define HPM_PDGO ((PDGO_Type *) HPM_PDGO_BASE) - -#include "hpm_pgpr_regs.h" -/* Address of PGPR instances */ -/* PGPR0 base address */ -#define HPM_PGPR0_BASE (0xF4138000UL) -/* PGPR0 base pointer */ -#define HPM_PGPR0 ((PGPR_Type *) HPM_PGPR0_BASE) -/* PGPR1 base address */ -#define HPM_PGPR1_BASE (0xF413C000UL) -/* PGPR1 base pointer */ -#define HPM_PGPR1 ((PGPR_Type *) HPM_PGPR1_BASE) - -#include "hpm_bacc_regs.h" -/* Address of BACC instances */ -/* BACC base address */ -#define HPM_BACC_BASE (0xF4200000UL) -/* BACC base pointer */ -#define HPM_BACC ((BACC_Type *) HPM_BACC_BASE) - -#include "hpm_bpor_regs.h" -/* Address of BPOR instances */ -/* BPOR base address */ -#define HPM_BPOR_BASE (0xF4204000UL) -/* BPOR base pointer */ -#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE) - -#include "hpm_bcfg_regs.h" -/* Address of BCFG instances */ -/* BCFG base address */ -#define HPM_BCFG_BASE (0xF4208000UL) -/* BCFG base pointer */ -#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE) - -#include "hpm_bgpr_regs.h" -/* Address of BGPR instances */ -/* BGPR0 base address */ -#define HPM_BGPR0_BASE (0xF4218000UL) -/* BGPR0 base pointer */ -#define HPM_BGPR0 ((BGPR_Type *) HPM_BGPR0_BASE) -/* BGPR1 base address */ -#define HPM_BGPR1_BASE (0xF4220000UL) -/* BGPR1 base pointer */ -#define HPM_BGPR1 ((BGPR_Type *) HPM_BGPR1_BASE) - -#include "hpm_bsec_regs.h" -/* Address of BSEC instances */ -/* BSEC base address */ -#define HPM_BSEC_BASE (0xF4240000UL) -/* BSEC base pointer */ -#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE) - -#include "hpm_rtc_regs.h" -/* Address of RTC instances */ -/* RTC base address */ -#define HPM_RTC_BASE (0xF4244000UL) -/* RTC base pointer */ -#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE) - -#include "hpm_bkey_regs.h" -/* Address of BKEY instances */ -/* BKEY base address */ -#define HPM_BKEY_BASE (0xF4248000UL) -/* BKEY base pointer */ -#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE) - -#include "hpm_bmon_regs.h" -/* Address of BMON instances */ -/* BMON base address */ -#define HPM_BMON_BASE (0xF424C000UL) -/* BMON base pointer */ -#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE) - -#include "hpm_tamp_regs.h" -/* Address of TAMP instances */ -/* TAMP base address */ -#define HPM_TAMP_BASE (0xF4250000UL) -/* TAMP base pointer */ -#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE) - -#include "hpm_mono_regs.h" -/* Address of MONO instances */ -/* MONO base address */ -#define HPM_MONO_BASE (0xF4254000UL) -/* MONO base pointer */ -#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE) - - -#include "riscv/riscv_core.h" -#include "hpm_csr_regs.h" -#include "hpm_interrupt.h" -#include "hpm_misc.h" -#include "hpm_dmamux_src.h" -#include "hpm_trgmmux_src.h" -#include "hpm_iomux.h" -#include "hpm_pmic_iomux.h" -#include "hpm_batt_iomux.h" -#endif /* HPM_SOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc_feature.h deleted file mode 100644 index 38d55df323f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc_feature.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SOC_FEATURE_H -#define HPM_SOC_FEATURE_H - -#include "hpm_soc.h" -#include "hpm_soc_ip_feature.h" - -/* - * UART section - */ -#define UART_SOC_FIFO_SIZE (16U) - -/* - * I2C Section - */ -#define I2C_SOC_FIFO_SIZE (4U) -#define I2C_SOC_TRANSFER_COUNT_MAX (4096U) - -/* - * PMIC Section - */ -#define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U) -#define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U) -#define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125) -#define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U) -#define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U) -#define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U) - -/* - * I2S Section - */ -#define I2S_SOC_MAX_CHANNEL_NUM (16U) -#define I2S_SOC_MAX_TX_CHANNEL_NUM (8U) -#define I2S_SOC_MAX_TX_FIFO_DEPTH (8U) -#define PDM_I2S HPM_I2S0 -#define DAO_I2S HPM_I2S1 -#define PDM_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define VAD_SOC_SAMPLE_RATE_IN_HZ (16000U) -#define DAO_SOC_SAMPLE_RATE_IN_HZ (48000U) -#define DAO_SOC_PDM_SAMPLE_RATE_RATIO (3U) -#define DAO_SOC_VAD_SAMPLE_RATE_RATIO (3U) - -/* - * PLLCTL Section - */ -#define PLLCTL_SOC_PLL_MAX_COUNT (3U) -/* PLL reference clock in hz */ -#define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL) -/* only PLL1 and PLL2 have DIV0, DIV1 */ -#define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) -#define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0) - - -/* - * PWM Section - */ -#define PWM_SOC_PWM_MAX_COUNT (8U) -#define PWM_SOC_CMP_MAX_COUNT (24U) -#define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U) - -/* - * DMA Section - */ -#define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD) -#define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T) -#define DMA_SOC_CHANNEL_NUM (32U) -#define DMA_SOC_MAX_COUNT (2U) -#define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n)) -#define DMA_SOC_HAS_IDLE_FLAG (1U) - -/* - * PDMA Section - */ -#define PDMA_SOC_PS_MAX_COUNT (0U) - -/* - * LCDC Section - */ -#define LCDC_SOC_MAX_LAYER_COUNT (0U) -#define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U) -#define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2) -#define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2) - -/* -* USB Section -*/ -#define USB_SOC_MAX_COUNT (1U) - -#define USB_SOC_DCD_QTD_NEXT_INVALID (1U) -#define USB_SOC_DCD_QHD_BUFFER_COUNT (5U) -#define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U) -#ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT -#define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U) -#endif -#define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT) -#define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U) -#define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U) - -#define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U) - -/* -* ENET Section -*/ -#define ENET_SOC_RGMII_EN (0U) -#define ENET_SOC_DESC_ADDR_ALIGNMENT (32U) -#define ENET_SOC_BUFF_ADDR_ALIGNMENT (4U) -#define ENET_SOC_ADDR_MAX_COUNT (5U) -#define ENET_SOC_ALT_EHD_DES_MIN_LEN (4U) -#define ENET_SOC_ALT_EHD_DES_MAX_LEN (8U) -#define ENET_SOC_ALT_EHD_DES_LEN (8U) -#define ENET_SOC_PPS_MAX_COUNT (2L) -#define ENET_SOC_PPS1_EN (0U) - -/* -* ADC Section -*/ -#define ADC_SOC_IP_VERSION (3U) -#define ADC_SOC_SEQ_MAX_LEN (16U) -#define ADC_SOC_SEQ_HCFG_EN (1U) -#define ADC_SOC_MAX_TRIG_CH_LEN (4U) -#define ADC_SOC_MAX_TRIG_CH_NUM (11U) -#define ADC_SOC_DMA_ADDR_ALIGNMENT (4U) -#define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U) -#define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U) -#define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U) -#define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U) - -#define ADC16_SOC_PARAMS_LEN (34U) -#define ADC16_SOC_MAX_CH_NUM (15U) -#define ADC16_SOC_MAX_SAMPLE_VALUE (65535U) -#define ADC16_SOC_MAX_CONV_CLK_NUM (21U) - -/* - * SYSCTL Section - */ -#define SYSCTL_SOC_CPU_GPR_COUNT (14U) -#define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U) - -/* - * PTPC Section - */ -#define PTPC_SOC_TIMER_MAX_COUNT (2U) - -/* - * SDP Section - */ -#define SDP_REGISTER_DESCRIPTOR_COUNT (1U) -#define SDP_HAS_SM3_SUPPORT (1U) -#define SDP_HAS_SM4_SUPPORT (1U) - -/* - * SOC Privilege mode - */ -#define SOC_HAS_S_MODE (1U) - -/* - * DAC Section - */ -#define DAC_SOC_BUFF_ALIGNED_SIZE (32U) -#define DAC_SOC_MAX_DATA (4095U) -#define DAC_SOC_MAX_BUFF_COUNT (65536U) -#define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL) - -/* - * SPI Section - */ -#define SPI_SOC_TRANSFER_COUNT_MAX (512U) -#define SPI_SOC_FIFO_DEPTH (4U) - -/* - * ROM API section - */ -#define ROMAPI_HAS_SW_SM3 (1) -#define ROMAPI_HAS_SW_SM4 (1) - -/* - * OTP Section - */ -#define OTP_SOC_MAC0_IDX (65U) -#define OTP_SOC_MAC0_LEN (6U) /* in bytes */ - -#define OTP_SOC_UUID_IDX (88U) -#define OTP_SOC_UUID_LEN (16U) /* in bytes */ - -/** - * PWM Section - * - */ -#define PWM_SOC_HRPWM_SUPPORT (1U) -#define PWM_SOC_SHADOW_TRIG_SUPPORT (0U) -#define PWM_SOC_TIMER_RESET_SUPPORT (1U) - -/* - * TRGM section - */ -#define TRGM_SOC_HAS_FILTER_SHIFT (1U) -#define TRGM_SOC_HAS_DMAMUX_EN (1U) -#define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U) -#define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U) -#define TRGM_SOC_HAS_POS_MATRIX_SEL (1U) - -/* - * MCAN Section - */ -#define MCAN_SOC_MAX_COUNT (8U) -#define MCAN_SOC_MSG_BUF_IN_IP (0U) -#define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U) -#define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT - -/* - * EWDG Section - */ -#define EWDG_SOC_CLK_DIV_VAL_MAX (32U) -#define EWDG_SOC_OVERTIME_REG_WIDTH (32U) -#define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1) -#define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (0) - -/* - * Sync Timer Section - */ -#define SYNT_SOC_HAS_TIMESTAMP (1U) - -#endif /* HPM_SOC_FEATURE_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc_ip_feature.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc_ip_feature.h deleted file mode 100644 index b6420616fe6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_soc_ip_feature.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifndef HPM_SOC_IP_FEATURE_H -#define HPM_SOC_IP_FEATURE_H - -/* GPTMR related feature */ -#define HPM_IP_FEATURE_GPTMR_MONITOR 1 -#define HPM_IP_FEATURE_GPTMR_OP_MODE 1 -#define HPM_IP_FEATURE_GPTMR_CNT_MODE 1 - -/* UART related feature */ -#define HPM_IP_FEATURE_UART_RX_IDLE_DETECT 1 -#define HPM_IP_FEATURE_UART_FCRR 1 -#define HPM_IP_FEATURE_UART_RX_EN 1 -#define HPM_IP_FEATURE_UART_E00018_FIX 1 -#define HPM_IP_FEATURE_UART_9BIT_MODE 1 -#define HPM_IP_FEATURE_UART_ADDR_MATCH 1 -#define HPM_IP_FEATURE_UART_TRIG_MODE 1 -#define HPM_IP_FEATURE_UART_FINE_FIFO_THRLD 1 -#define HPM_IP_FEATURE_UART_IIR2 1 - -/* I2C related feature */ -#define HPM_IP_FEATURE_I2C_SUPPORT_RESET 1 - -/* SPI related feature */ -#define HPM_IP_FEATURE_SPI_NEW_TRANS_COUNT 1 -#define HPM_IP_FEATURE_SPI_CS_SELECT 1 -#define HPM_IP_FEATURE_SPI_SUPPORT_DIRECTIO 1 - -/* DMAV2 related feature */ -#define HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS 1 -#define HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP 1 - -/* ADC16 related feature */ -#define HPM_IP_FEATURE_ADC16_HAS_MOT_EN 1 - -/* DAO related feature */ -#define HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG 1 - -/* QEIV2 related feature */ -#define HPM_IP_FEATURE_QEIV2_ONESHOT_MODE 1 -#define HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG 1 -#define HPM_IP_FEATURE_QEIV2_TIMESTAMP 1 -#define HPM_IP_FEATURE_QEIV2_ADC_THRESHOLD 1 - -/* RDC related feature */ -#define HPM_IP_FEATURE_RDC_IIR 1 - -/* SEI related feature */ -#define HPM_IP_FEATURE_SEI_RX_LATCH_FEATURE 1 -#define HPM_IP_FEATURE_SEI_ASYNCHRONOUS_MODE_V2 1 -#define HPM_IP_FEATURE_SEI_TIMEOUT_REWIND_FEATURE 1 -#define HPM_IP_FEATURE_SEI_HAVE_DAT10_31 1 -#define HPM_IP_FEATURE_SEI_HAVE_INTR64_255 1 -#define HPM_IP_FEATURE_SEI_HAVE_CTRL2_12 1 -#define HPM_IP_FEATURE_SEI_HAVE_PTCD 1 - -/* ENET related feature */ -#define HPM_IP_FEATURE_ENET_HAS_MII_MODE 1 - -/* FFA related feature */ -#define HPM_IP_FEATURE_FFA_FP32 1 - -#endif /* HPM_SOC_IP_FEATURE_H */ \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_sysctl_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_sysctl_drv.c deleted file mode 100644 index e32dcece386..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_sysctl_drv.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_sysctl_drv.h" -#include "hpm_soc_feature.h" - -#define SYSCTL_RESOURCE_GROUP0 0 -#define SYSCTL_RESOURCE_GROUP1 1 - -#define SYSCTL_CPU_RELEASE_KEY(cpu) (0xC0BEF1A9UL | (((cpu) & 1) << 24)) - -static inline bool sysctl_valid_cpu_index(uint8_t cpu) -{ -#ifdef SYSCTL_CPU_CPU1 - return (cpu > SYSCTL_CPU_CPU1) ? false : true; -#else - return (cpu != SYSCTL_CPU_CPU0) ? false : true; -#endif -} - -hpm_stat_t sysctl_get_cpu_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint32_t *data, uint32_t size) -{ - uint32_t i; - if ((!sysctl_valid_cpu_index(cpu)) || (size > ARRAY_SIZE(ptr->CPU[cpu].GPR))) { - return status_invalid_argument; - } - for (i = 0; i < size; i++) { - *(data + i) = ptr->CPU[cpu].GPR[i]; - } - return status_success; -} - -static hpm_stat_t _sysctl_cpu_get_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - *(data + i) = ptr->CPU[cpu].GPR[start + i]; - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 0, start, count, data); -} - -hpm_stat_t sysctl_cpu1_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data) -{ - return _sysctl_cpu_get_gpr(ptr, 1, start, count, data); -} - -static hpm_stat_t _sysctl_cpu_set_gpr(SYSCTL_Type *ptr, uint8_t cpu, uint8_t start, uint8_t count, const uint32_t *data) -{ - uint8_t i, size = ARRAY_SIZE(ptr->CPU[cpu].GPR); - if (!sysctl_valid_cpu_index(cpu) || (data == NULL) || !count || start > size || count > size || - (start + count) > size) { - return status_invalid_argument; - } - for (i = 0; i < count; i++) { - ptr->CPU[cpu].GPR[start + i] = *(data + i); - } - return status_success; -} - -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 0, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu0_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock) -{ - hpm_stat_t stat = status_success; - uint16_t gpr_mask; - stat = _sysctl_cpu_set_gpr(ptr, 1, start, count, data); - if (stat != status_success) { - return stat; - } - if (lock) { - gpr_mask = ((1 << count) - 1) << start; - sysctl_cpu1_lock_gpr_with_mask(ptr, gpr_mask); - } - return stat; -} - -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config) -{ - (void) ptr; - config->mode = monitor_work_mode_record; - config->accuracy = monitor_accuracy_1khz; - config->reference = monitor_reference_24mhz; - config->divide_by = 1; - config->high_limit = 0; - config->low_limit = 0; - config->start_measure = true; - config->enable_output = false; - config->target = monitor_target_clk_top_cpu0; -} - -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t slice, monitor_config_t *config) -{ - ptr->MONITOR[slice].CONTROL &= ~(SYSCTL_MONITOR_CONTROL_START_MASK | SYSCTL_MONITOR_CONTROL_OUTEN_MASK); - - if (config->mode == monitor_work_mode_compare) { - ptr->MONITOR[slice].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(config->high_limit); - ptr->MONITOR[slice].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(config->low_limit); - } - - ptr->MONITOR[slice].CONTROL = (ptr->MONITOR[slice].CONTROL & - ~(SYSCTL_MONITOR_CONTROL_DIV_MASK | SYSCTL_MONITOR_CONTROL_MODE_MASK | SYSCTL_MONITOR_CONTROL_ACCURACY_MASK | - SYSCTL_MONITOR_CONTROL_REFERENCE_MASK | SYSCTL_MONITOR_CONTROL_SELECTION_MASK)) | - (SYSCTL_MONITOR_CONTROL_DIV_SET(config->divide_by - 1) | SYSCTL_MONITOR_CONTROL_MODE_SET(config->mode) | - SYSCTL_MONITOR_CONTROL_ACCURACY_SET(config->accuracy) | - SYSCTL_MONITOR_CONTROL_REFERENCE_SET(config->reference) | - SYSCTL_MONITOR_CONTROL_START_SET(config->start_measure) | - SYSCTL_MONITOR_CONTROL_OUTEN_SET(config->enable_output) | - SYSCTL_MONITOR_CONTROL_SELECTION_SET(config->target)); -} - -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output) -{ - uint32_t frequency = 0; - monitor_config_t monitor = { 0 }; - sysctl_monitor_get_default_config(ptr, &monitor); - monitor.target = target; - monitor.enable_output = enable_output; - sysctl_monitor_init(ptr, monitor_index, &monitor); - if (monitor_index < SYSCTL_SOC_MONITOR_SLICE_COUNT) { - frequency = sysctl_monitor_get_current_result(ptr, monitor_index); - } - return frequency; -} - -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry) -{ - if (!sysctl_valid_cpu_index(cpu)) { - return status_invalid_argument; - } - ptr->CPU[cpu].GPR[0] = entry; - ptr->CPU[cpu].GPR[1] = SYSCTL_CPU_RELEASE_KEY(cpu); - return status_success; -} - -hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 1, entry); -} - -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry) -{ - return sysctl_set_cpu_entry(ptr, 0, entry); -} - -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t linkable_resource, - bool enable) -{ - uint32_t index, offset; - if (linkable_resource < sysctl_resource_linkable_start) { - return status_invalid_argument; - } - - index = (linkable_resource - sysctl_resource_linkable_start) / 32; - offset = (linkable_resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - ptr->GROUP0[index].VALUE = (ptr->GROUP0[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, linkable_resource)) { - ; - } - } - break; - case SYSCTL_RESOURCE_GROUP1: - ptr->GROUP1[index].VALUE = (ptr->GROUP1[index].VALUE & ~(1UL << offset)) | (enable ? (1UL << offset) : 0); - if (enable) { - while (sysctl_resource_target_is_busy(ptr, linkable_resource)) { - ; - } - } - break; - default: - return status_invalid_argument; - } - - return status_success; -} - -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t linkable_resource) -{ - uint32_t index, offset; - bool enable; - - index = (linkable_resource - sysctl_resource_linkable_start) / 32; - offset = (linkable_resource - sysctl_resource_linkable_start) % 32; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - enable = ((ptr->GROUP0[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - case SYSCTL_RESOURCE_GROUP1: - enable = ((ptr->GROUP1[index].VALUE & (1UL << offset)) != 0) ? true : false; - break; - default: - enable = false; - break; - } - - return enable; -} - -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index) -{ - uint32_t value; - switch (group) { - case SYSCTL_RESOURCE_GROUP0: - value = ptr->GROUP0[index].VALUE; - break; - case SYSCTL_RESOURCE_GROUP1: - value = ptr->GROUP1[index].VALUE; - break; - default: - value = 0; - break; - } - return value; -} - -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP0, resource, false); -} - -hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, true); -} - -hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return sysctl_enable_group_resource(ptr, SYSCTL_RESOURCE_GROUP1, resource, false); -} - -hpm_stat_t sysctl_update_divider(SYSCTL_Type *ptr, clock_node_t node_index, uint32_t divide_by) -{ - uint32_t node = (uint32_t) node_index; - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_DIV_MASK)) | SYSCTL_CLOCK_DIV_SET(divide_by - 1); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node_index, clock_source_t source, uint32_t divide_by) -{ - uint32_t node = (uint32_t) node_index; - if (node >= clock_node_adc_start) { - return status_invalid_argument; - } - - if (source >= clock_source_general_source_end) { - return status_invalid_argument; - } - ptr->CLOCK[node] = (ptr->CLOCK[node] & ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | - (SYSCTL_CLOCK_MUX_SET(source) | SYSCTL_CLOCK_DIV_SET(divide_by - 1)); - while (sysctl_clock_target_is_busy(ptr, node)) { - } - return status_success; -} - -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source) -{ - if (source >= clock_source_adc_clk_end) { - return status_invalid_argument; - } - uint32_t adc_index = (uint32_t) (node - clock_node_adc_start); - if (adc_index >= ARRAY_SIZE(ptr->ADCCLK)) { - return status_invalid_argument; - } - - ptr->ADCCLK[adc_index] = (ptr->ADCCLK[adc_index] & ~SYSCTL_ADCCLK_MUX_MASK) | SYSCTL_ADCCLK_MUX_SET(source); - - return status_success; -} - -hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source) -{ - if (source >= clock_source_i2s_clk_end) { - return status_invalid_argument; - } - uint32_t i2s_index = (uint32_t) (node - clock_node_i2s_start); - if (i2s_index >= ARRAY_SIZE(ptr->I2SCLK)) { - return status_invalid_argument; - } - - ptr->I2SCLK[i2s_index] = (ptr->I2SCLK[i2s_index] & ~SYSCTL_I2SCLK_MUX_MASK) | SYSCTL_I2SCLK_MUX_SET(source); - - return status_success; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_sysctl_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_sysctl_drv.h deleted file mode 100644 index 71d53b31f5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_sysctl_drv.h +++ /dev/null @@ -1,1706 +0,0 @@ -/** - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_SYSCTL_DRV_H -#define HPM_SYSCTL_DRV_H - -#include "hpm_common.h" -#include "hpm_sysctl_regs.h" - -/** - * - * @brief SYSCTL driver APIs - * @defgroup sysctl_interface SYSCTL driver APIs - * @ingroup io_interfaces - * @{ - */ - -/** - * @brief Retention domains - */typedef enum { - sysctl_retention_domain_sys = 0, - sysctl_retention_domain_cpu0 = 2, - sysctl_retention_domain_cpu1 = 4, - sysctl_retention_domain_otn = 6, - sysctl_retention_domain_xtal24m = 8, - sysctl_retention_domain_pll0 = 9, - sysctl_retention_domain_pll1 = 10, - sysctl_retention_domain_pll2 = 11, -} sysctl_retention_domain_t; - -/** - * @brief Clock presets - */ -typedef enum { - sysctl_preset_0 = 1 << 0, - sysctl_preset_1 = 1 << 1, - sysctl_preset_2 = 1 << 2, - sysctl_preset_3 = 1 << 3, -} sysctl_preset_t; - -/** - * @brief Reset domains - */ -typedef enum { - sysctl_reset_domain_soc = 0, - sysctl_reset_domain_cpu0, - sysctl_reset_domain_cpu1, - sysctl_reset_domain_otn, -} sysctl_reset_domain_t; - -/** - * @brief Resource - */ -typedef enum { - sysctl_resource_cpu0 = SYSCTL_RESOURCE_CPU0, - sysctl_resource_cpx0 = SYSCTL_RESOURCE_CPX0, - sysctl_resource_cpu1 = SYSCTL_RESOURCE_CPU1, - sysctl_resource_cpx1 = SYSCTL_RESOURCE_CPX1, - sysctl_resource_pow_cpu0 = SYSCTL_RESOURCE_POW_CPU0, - sysctl_resource_pow_cpu1 = SYSCTL_RESOURCE_POW_CPU1, - sysctl_resource_pow_otn = SYSCTL_RESOURCE_POW_OTN, - sysctl_resource_rst_soc = SYSCTL_RESOURCE_RST_SOC, - sysctl_resource_rst_cpu0 = SYSCTL_RESOURCE_RST_CPU0, - sysctl_resource_rst_cpu1 = SYSCTL_RESOURCE_RST_CPU1, - sysctl_resource_rst_otn = SYSCTL_RESOURCE_RST_OTN, - sysctl_resource_xtal = SYSCTL_RESOURCE_CLK_SRC_XTAL, - sysctl_resource_pll0 = SYSCTL_RESOURCE_CLK_SRC_PLL0, - sysctl_resource_clk0_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0, - sysctl_resource_clk1_pll0 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0, - sysctl_resource_pll1 = SYSCTL_RESOURCE_CLK_SRC_PLL1, - sysctl_resource_clk0_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1, - sysctl_resource_clk1_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1, - sysctl_resource_clk2_pll1 = SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1, - sysctl_resource_pll2 = SYSCTL_RESOURCE_CLK_SRC_PLL2, - sysctl_resource_clk0_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2, - sysctl_resource_clk1_pll2 = SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2, - sysctl_resource_pll0_ref = SYSCTL_RESOURCE_CLK_SRC_PLL0_REF, - sysctl_resource_pll1_ref = SYSCTL_RESOURCE_CLK_SRC_PLL1_REF, - sysctl_resource_pll2_ref = SYSCTL_RESOURCE_CLK_SRC_PLL2_REF, - - sysctl_resource_clk_top_cpu0 = SYSCTL_RESOURCE_CLK_TOP_CPU0, - sysctl_resource_clk_top_mchtmr0 = SYSCTL_RESOURCE_CLK_TOP_MCT0, - sysctl_resource_clk_top_cpu1 = SYSCTL_RESOURCE_CLK_TOP_CPU1, - sysctl_resource_clk_top_mchtmr1 = SYSCTL_RESOURCE_CLK_TOP_MCT1, - sysctl_resource_clk_top_ahb0 = SYSCTL_RESOURCE_CLK_TOP_AHB0, - sysctl_resource_clk_top_axif = SYSCTL_RESOURCE_CLK_TOP_AXIF, - sysctl_resource_clk_top_axis = SYSCTL_RESOURCE_CLK_TOP_AXIS, - sysctl_resource_clk_top_axic = SYSCTL_RESOURCE_CLK_TOP_AXIC, - sysctl_resource_clk_top_axin = SYSCTL_RESOURCE_CLK_TOP_AXIN, - sysctl_resource_clk_top_gptmr0 = SYSCTL_RESOURCE_CLK_TOP_TMR0, - sysctl_resource_clk_top_gptmr1 = SYSCTL_RESOURCE_CLK_TOP_TMR1, - sysctl_resource_clk_top_gptmr2 = SYSCTL_RESOURCE_CLK_TOP_TMR2, - sysctl_resource_clk_top_gptmr3 = SYSCTL_RESOURCE_CLK_TOP_TMR3, - sysctl_resource_clk_top_gptmr4 = SYSCTL_RESOURCE_CLK_TOP_TMR4, - sysctl_resource_clk_top_gptmr5 = SYSCTL_RESOURCE_CLK_TOP_TMR5, - sysctl_resource_clk_top_gptmr6 = SYSCTL_RESOURCE_CLK_TOP_TMR6, - sysctl_resource_clk_top_gptmr7 = SYSCTL_RESOURCE_CLK_TOP_TMR7, - sysctl_resource_clk_top_i2c0 = SYSCTL_RESOURCE_CLK_TOP_I2C0, - sysctl_resource_clk_top_i2c1 = SYSCTL_RESOURCE_CLK_TOP_I2C1, - sysctl_resource_clk_top_i2c2 = SYSCTL_RESOURCE_CLK_TOP_I2C2, - sysctl_resource_clk_top_i2c3 = SYSCTL_RESOURCE_CLK_TOP_I2C3, - sysctl_resource_clk_top_i2c4 = SYSCTL_RESOURCE_CLK_TOP_I2C4, - sysctl_resource_clk_top_i2c5 = SYSCTL_RESOURCE_CLK_TOP_I2C5, - sysctl_resource_clk_top_i2c6 = SYSCTL_RESOURCE_CLK_TOP_I2C6, - sysctl_resource_clk_top_i2c7 = SYSCTL_RESOURCE_CLK_TOP_I2C7, - sysctl_resource_clk_top_spi0 = SYSCTL_RESOURCE_CLK_TOP_SPI0, - sysctl_resource_clk_top_spi1 = SYSCTL_RESOURCE_CLK_TOP_SPI1, - sysctl_resource_clk_top_spi2 = SYSCTL_RESOURCE_CLK_TOP_SPI2, - sysctl_resource_clk_top_spi3 = SYSCTL_RESOURCE_CLK_TOP_SPI3, - sysctl_resource_clk_top_spi4 = SYSCTL_RESOURCE_CLK_TOP_SPI4, - sysctl_resource_clk_top_spi5 = SYSCTL_RESOURCE_CLK_TOP_SPI5, - sysctl_resource_clk_top_spi6 = SYSCTL_RESOURCE_CLK_TOP_SPI6, - sysctl_resource_clk_top_spi7 = SYSCTL_RESOURCE_CLK_TOP_SPI7, - sysctl_resource_clk_top_uart0 = SYSCTL_RESOURCE_CLK_TOP_URT0, - sysctl_resource_clk_top_uart1 = SYSCTL_RESOURCE_CLK_TOP_URT1, - sysctl_resource_clk_top_uart2 = SYSCTL_RESOURCE_CLK_TOP_URT2, - sysctl_resource_clk_top_uart3 = SYSCTL_RESOURCE_CLK_TOP_URT3, - sysctl_resource_clk_top_uart4 = SYSCTL_RESOURCE_CLK_TOP_URT4, - sysctl_resource_clk_top_uart5 = SYSCTL_RESOURCE_CLK_TOP_URT5, - sysctl_resource_clk_top_uart6 = SYSCTL_RESOURCE_CLK_TOP_URT6, - sysctl_resource_clk_top_uart7 = SYSCTL_RESOURCE_CLK_TOP_URT7, - sysctl_resource_clk_top_uart8 = SYSCTL_RESOURCE_CLK_TOP_URT8, - sysctl_resource_clk_top_uart9 = SYSCTL_RESOURCE_CLK_TOP_URT9, - sysctl_resource_clk_top_uart10 = SYSCTL_RESOURCE_CLK_TOP_URT10, - sysctl_resource_clk_top_uart11 = SYSCTL_RESOURCE_CLK_TOP_URT11, - sysctl_resource_clk_top_uart12 = SYSCTL_RESOURCE_CLK_TOP_URT12, - sysctl_resource_clk_top_uart13 = SYSCTL_RESOURCE_CLK_TOP_URT13, - sysctl_resource_clk_top_uart14 = SYSCTL_RESOURCE_CLK_TOP_URT14, - sysctl_resource_clk_top_uart15 = SYSCTL_RESOURCE_CLK_TOP_URT15, - sysctl_resource_clk_top_ana0 = SYSCTL_RESOURCE_CLK_TOP_ANA0, - sysctl_resource_clk_top_ana1 = SYSCTL_RESOURCE_CLK_TOP_ANA1, - sysctl_resource_clk_top_ana2 = SYSCTL_RESOURCE_CLK_TOP_ANA2, - sysctl_resource_clk_top_ana3 = SYSCTL_RESOURCE_CLK_TOP_ANA3, - sysctl_resource_clk_top_aud0 = SYSCTL_RESOURCE_CLK_TOP_AUD0, - sysctl_resource_clk_top_aud1 = SYSCTL_RESOURCE_CLK_TOP_AUD1, - sysctl_resource_clk_top_can0 = SYSCTL_RESOURCE_CLK_TOP_CAN0, - sysctl_resource_clk_top_can1 = SYSCTL_RESOURCE_CLK_TOP_CAN1, - sysctl_resource_clk_top_can2 = SYSCTL_RESOURCE_CLK_TOP_CAN2, - sysctl_resource_clk_top_can3 = SYSCTL_RESOURCE_CLK_TOP_CAN3, - sysctl_resource_clk_top_can4 = SYSCTL_RESOURCE_CLK_TOP_CAN4, - sysctl_resource_clk_top_can5 = SYSCTL_RESOURCE_CLK_TOP_CAN5, - sysctl_resource_clk_top_can6 = SYSCTL_RESOURCE_CLK_TOP_CAN6, - sysctl_resource_clk_top_can7 = SYSCTL_RESOURCE_CLK_TOP_CAN7, - sysctl_resource_clk_top_xpi0 = SYSCTL_RESOURCE_CLK_TOP_XPI0, - sysctl_resource_clk_top_femc = SYSCTL_RESOURCE_CLK_TOP_FEMC, - sysctl_resource_clk_top_eth0 = SYSCTL_RESOURCE_CLK_TOP_ETH0, - sysctl_resource_clk_top_ptp0 = SYSCTL_RESOURCE_CLK_TOP_PTP0, - sysctl_resource_clk_top_ref0 = SYSCTL_RESOURCE_CLK_TOP_REF0, - sysctl_resource_clk_top_ref1 = SYSCTL_RESOURCE_CLK_TOP_REF1, - sysctl_resource_clk_top_ntm0 = SYSCTL_RESOURCE_CLK_TOP_NTM0, - sysctl_resource_clk_top_tsn1 = SYSCTL_RESOURCE_CLK_TOP_TSW1, - sysctl_resource_clk_top_tsn2 = SYSCTL_RESOURCE_CLK_TOP_TSW2, - sysctl_resource_clk_top_tsn3 = SYSCTL_RESOURCE_CLK_TOP_TSW3, - sysctl_resource_clk_top_adc0 = SYSCTL_RESOURCE_CLK_TOP_ADC0, - sysctl_resource_clk_top_adc1 = SYSCTL_RESOURCE_CLK_TOP_ADC1, - sysctl_resource_clk_top_adc2 = SYSCTL_RESOURCE_CLK_TOP_ADC2, - sysctl_resource_clk_top_adc3 = SYSCTL_RESOURCE_CLK_TOP_ADC3, - sysctl_resource_clk_top_i2s0 = SYSCTL_RESOURCE_CLK_TOP_I2S0, - sysctl_resource_clk_top_i2s1 = SYSCTL_RESOURCE_CLK_TOP_I2S1, - - sysctl_resource_linkable_start = 256, - sysctl_resource_ahbp = SYSCTL_RESOURCE_AHBP, - sysctl_resource_axis = SYSCTL_RESOURCE_AXIS, - sysctl_resource_axic = SYSCTL_RESOURCE_AXIC, - sysctl_resource_axin = SYSCTL_RESOURCE_AXIN, - sysctl_resource_rom0 = SYSCTL_RESOURCE_ROM0, - sysctl_resource_lmm0 = SYSCTL_RESOURCE_LMM0, - sysctl_resource_mchtmr0 = SYSCTL_RESOURCE_MCT0, - sysctl_resource_lmm1 = SYSCTL_RESOURCE_LMM1, - sysctl_resource_mchtmr1 = SYSCTL_RESOURCE_MCT1, - sysctl_resource_gptmr0 = SYSCTL_RESOURCE_TMR0, - sysctl_resource_gptmr1 = SYSCTL_RESOURCE_TMR1, - sysctl_resource_gptmr2 = SYSCTL_RESOURCE_TMR2, - sysctl_resource_gptmr3 = SYSCTL_RESOURCE_TMR3, - sysctl_resource_gptmr4 = SYSCTL_RESOURCE_TMR4, - sysctl_resource_gptmr5 = SYSCTL_RESOURCE_TMR5, - sysctl_resource_gptmr6 = SYSCTL_RESOURCE_TMR6, - sysctl_resource_gptmr7 = SYSCTL_RESOURCE_TMR7, - sysctl_resource_i2c0 = SYSCTL_RESOURCE_I2C0, - sysctl_resource_i2c1 = SYSCTL_RESOURCE_I2C1, - sysctl_resource_i2c2 = SYSCTL_RESOURCE_I2C2, - sysctl_resource_i2c3 = SYSCTL_RESOURCE_I2C3, - sysctl_resource_i2c4 = SYSCTL_RESOURCE_I2C4, - sysctl_resource_i2c5 = SYSCTL_RESOURCE_I2C5, - sysctl_resource_i2c6 = SYSCTL_RESOURCE_I2C6, - sysctl_resource_i2c7 = SYSCTL_RESOURCE_I2C7, - sysctl_resource_spi0 = SYSCTL_RESOURCE_SPI0, - sysctl_resource_spi1 = SYSCTL_RESOURCE_SPI1, - sysctl_resource_spi2 = SYSCTL_RESOURCE_SPI2, - sysctl_resource_spi3 = SYSCTL_RESOURCE_SPI3, - sysctl_resource_spi4 = SYSCTL_RESOURCE_SPI4, - sysctl_resource_spi5 = SYSCTL_RESOURCE_SPI5, - sysctl_resource_spi6 = SYSCTL_RESOURCE_SPI6, - sysctl_resource_spi7 = SYSCTL_RESOURCE_SPI7, - sysctl_resource_uart0 = SYSCTL_RESOURCE_URT0, - sysctl_resource_uart1 = SYSCTL_RESOURCE_URT1, - sysctl_resource_uart2 = SYSCTL_RESOURCE_URT2, - sysctl_resource_uart3 = SYSCTL_RESOURCE_URT3, - sysctl_resource_uart4 = SYSCTL_RESOURCE_URT4, - sysctl_resource_uart5 = SYSCTL_RESOURCE_URT5, - sysctl_resource_uart6 = SYSCTL_RESOURCE_URT6, - sysctl_resource_uart7 = SYSCTL_RESOURCE_URT7, - sysctl_resource_uart8 = SYSCTL_RESOURCE_URT8, - sysctl_resource_uart9 = SYSCTL_RESOURCE_URT9, - sysctl_resource_uart10 = SYSCTL_RESOURCE_URT10, - sysctl_resource_uart11 = SYSCTL_RESOURCE_URT11, - sysctl_resource_uart12 = SYSCTL_RESOURCE_URT12, - sysctl_resource_uart13 = SYSCTL_RESOURCE_URT13, - sysctl_resource_uart14 = SYSCTL_RESOURCE_URT14, - sysctl_resource_uart15 = SYSCTL_RESOURCE_URT15, - sysctl_resource_crc0 = SYSCTL_RESOURCE_CRC0, - sysctl_resource_tsns = SYSCTL_RESOURCE_TSNS, - sysctl_resource_wdg0 = SYSCTL_RESOURCE_WDG0, - sysctl_resource_wdg1 = SYSCTL_RESOURCE_WDG1, - sysctl_resource_wdg2 = SYSCTL_RESOURCE_WDG2, - sysctl_resource_wdg3 = SYSCTL_RESOURCE_WDG3, - sysctl_resource_mbx0 = SYSCTL_RESOURCE_MBX0, - sysctl_resource_mbx1 = SYSCTL_RESOURCE_MBX1, - sysctl_resource_gpio = SYSCTL_RESOURCE_GPIO, - sysctl_resource_ppi0 = SYSCTL_RESOURCE_PPI0, - sysctl_resource_hdma = SYSCTL_RESOURCE_HDMA, - sysctl_resource_lobs = SYSCTL_RESOURCE_LOBS, - sysctl_resource_adc0 = SYSCTL_RESOURCE_ADC0, - sysctl_resource_adc1 = SYSCTL_RESOURCE_ADC1, - sysctl_resource_adc2 = SYSCTL_RESOURCE_ADC2, - sysctl_resource_adc3 = SYSCTL_RESOURCE_ADC3, - sysctl_resource_cmp0 = SYSCTL_RESOURCE_CMP0, - sysctl_resource_cmp1 = SYSCTL_RESOURCE_CMP1, - sysctl_resource_cmp2 = SYSCTL_RESOURCE_CMP2, - sysctl_resource_cmp3 = SYSCTL_RESOURCE_CMP3, - sysctl_resource_i2s0 = SYSCTL_RESOURCE_I2S0, - sysctl_resource_i2s1 = SYSCTL_RESOURCE_I2S1, - sysctl_resource_i2spdm0 = SYSCTL_RESOURCE_PDM0, - sysctl_resource_i2sdao = SYSCTL_RESOURCE_CLSD, - sysctl_resource_can0 = SYSCTL_RESOURCE_CAN0, - sysctl_resource_can1 = SYSCTL_RESOURCE_CAN1, - sysctl_resource_can2 = SYSCTL_RESOURCE_CAN2, - sysctl_resource_can3 = SYSCTL_RESOURCE_CAN3, - sysctl_resource_can4 = SYSCTL_RESOURCE_CAN4, - sysctl_resource_can5 = SYSCTL_RESOURCE_CAN5, - sysctl_resource_can6 = SYSCTL_RESOURCE_CAN6, - sysctl_resource_can7 = SYSCTL_RESOURCE_CAN7, - sysctl_resource_ptpc = SYSCTL_RESOURCE_PTPC, - sysctl_resource_qei0 = SYSCTL_RESOURCE_QEI0, - sysctl_resource_qei1 = SYSCTL_RESOURCE_QEI1, - sysctl_resource_qei2 = SYSCTL_RESOURCE_QEI2, - sysctl_resource_qei3 = SYSCTL_RESOURCE_QEI3, - sysctl_resource_qeo0 = SYSCTL_RESOURCE_QEO0, - sysctl_resource_qeo1 = SYSCTL_RESOURCE_QEO1, - sysctl_resource_qeo2 = SYSCTL_RESOURCE_QEO2, - sysctl_resource_qeo3 = SYSCTL_RESOURCE_QEO3, - sysctl_resource_pwm0 = SYSCTL_RESOURCE_PWM0, - sysctl_resource_pwm1 = SYSCTL_RESOURCE_PWM1, - sysctl_resource_pwm2 = SYSCTL_RESOURCE_PWM2, - sysctl_resource_pwm3 = SYSCTL_RESOURCE_PWM3, - sysctl_resource_rdc0 = SYSCTL_RESOURCE_RDC0, - sysctl_resource_rdc1 = SYSCTL_RESOURCE_RDC1, - sysctl_resource_sdm0 = SYSCTL_RESOURCE_SDM0, - sysctl_resource_sdm1 = SYSCTL_RESOURCE_SDM1, - sysctl_resource_plb0 = SYSCTL_RESOURCE_PLB0, - sysctl_resource_sei0 = SYSCTL_RESOURCE_SEI0, - sysctl_resource_mtg0 = SYSCTL_RESOURCE_MTG0, - sysctl_resource_mtg1 = SYSCTL_RESOURCE_MTG1, - sysctl_resource_vsc0 = SYSCTL_RESOURCE_VSC0, - sysctl_resource_vsc1 = SYSCTL_RESOURCE_VSC1, - sysctl_resource_clc0 = SYSCTL_RESOURCE_CLC0, - sysctl_resource_clc1 = SYSCTL_RESOURCE_CLC1, - sysctl_resource_emds = SYSCTL_RESOURCE_EMDS, - sysctl_resource_rng0 = SYSCTL_RESOURCE_RNG0, - sysctl_resource_sdp0 = SYSCTL_RESOURCE_SDP0, - sysctl_resource_pka0 = SYSCTL_RESOURCE_PKA0, - sysctl_resource_kman = SYSCTL_RESOURCE_KMAN, - sysctl_resource_xpi0 = SYSCTL_RESOURCE_XPI0, - sysctl_resource_femc = SYSCTL_RESOURCE_FEMC, - sysctl_resource_ram0 = SYSCTL_RESOURCE_RAM0, - sysctl_resource_ram1 = SYSCTL_RESOURCE_RAM1, - sysctl_resource_xdma = SYSCTL_RESOURCE_XDMA, - sysctl_resource_ffa0 = SYSCTL_RESOURCE_FFA0, - sysctl_resource_eth0 = SYSCTL_RESOURCE_ETH0, - sysctl_resource_usb0 = SYSCTL_RESOURCE_USB0, - sysctl_resource_ntmr0 = SYSCTL_RESOURCE_NTM0, - sysctl_resource_ref0 = SYSCTL_RESOURCE_REF0, - sysctl_resource_ref1 = SYSCTL_RESOURCE_REF1, - sysctl_resource_tsn0 = SYSCTL_RESOURCE_TSW0, - sysctl_resource_esc0 = SYSCTL_RESOURCE_ESC0, - sysctl_resource_linkable_end, - sysctl_resource_end = sysctl_resource_linkable_end, -} sysctl_resource_t; - -/** - * @brief Resource modes - */ -typedef enum { - sysctl_resource_mode_auto = 0, /*!< Resource clock is automatically managed by system request */ - sysctl_resource_mode_force_on, /*!< Force the resource clock on */ - sysctl_resource_mode_force_off, /*!< Force the resource clock off */ -} sysctl_resource_mode_t; - -/** - * @brief Clock nodes - */ -typedef enum { - clock_node_cpu0 = SYSCTL_CLOCK_CLK_TOP_CPU0, - clock_node_mchtmr0 = SYSCTL_CLOCK_CLK_TOP_MCT0, - clock_node_cpu1 = SYSCTL_CLOCK_CLK_TOP_CPU1, - clock_node_mchtmr1 = SYSCTL_CLOCK_CLK_TOP_MCT1, - clock_node_ahb0 = SYSCTL_CLOCK_CLK_TOP_AHB0, - clock_node_axif = SYSCTL_CLOCK_CLK_TOP_AXIF, - clock_node_axis = SYSCTL_CLOCK_CLK_TOP_AXIS, - clock_node_axic = SYSCTL_CLOCK_CLK_TOP_AXIC, - clock_node_axin = SYSCTL_CLOCK_CLK_TOP_AXIN, - clock_node_gptmr0 = SYSCTL_CLOCK_CLK_TOP_TMR0, - clock_node_gptmr1 = SYSCTL_CLOCK_CLK_TOP_TMR1, - clock_node_gptmr2 = SYSCTL_CLOCK_CLK_TOP_TMR2, - clock_node_gptmr3 = SYSCTL_CLOCK_CLK_TOP_TMR3, - clock_node_gptmr4 = SYSCTL_CLOCK_CLK_TOP_TMR4, - clock_node_gptmr5 = SYSCTL_CLOCK_CLK_TOP_TMR5, - clock_node_gptmr6 = SYSCTL_CLOCK_CLK_TOP_TMR6, - clock_node_gptmr7 = SYSCTL_CLOCK_CLK_TOP_TMR7, - clock_node_i2c0 = SYSCTL_CLOCK_CLK_TOP_I2C0, - clock_node_i2c1 = SYSCTL_CLOCK_CLK_TOP_I2C1, - clock_node_i2c2 = SYSCTL_CLOCK_CLK_TOP_I2C2, - clock_node_i2c3 = SYSCTL_CLOCK_CLK_TOP_I2C3, - clock_node_i2c4 = SYSCTL_CLOCK_CLK_TOP_I2C4, - clock_node_i2c5 = SYSCTL_CLOCK_CLK_TOP_I2C5, - clock_node_i2c6 = SYSCTL_CLOCK_CLK_TOP_I2C6, - clock_node_i2c7 = SYSCTL_CLOCK_CLK_TOP_I2C7, - clock_node_spi0 = SYSCTL_CLOCK_CLK_TOP_SPI0, - clock_node_spi1 = SYSCTL_CLOCK_CLK_TOP_SPI1, - clock_node_spi2 = SYSCTL_CLOCK_CLK_TOP_SPI2, - clock_node_spi3 = SYSCTL_CLOCK_CLK_TOP_SPI3, - clock_node_spi4 = SYSCTL_CLOCK_CLK_TOP_SPI4, - clock_node_spi5 = SYSCTL_CLOCK_CLK_TOP_SPI5, - clock_node_spi6 = SYSCTL_CLOCK_CLK_TOP_SPI6, - clock_node_spi7 = SYSCTL_CLOCK_CLK_TOP_SPI7, - clock_node_uart0 = SYSCTL_CLOCK_CLK_TOP_URT0, - clock_node_uart1 = SYSCTL_CLOCK_CLK_TOP_URT1, - clock_node_uart2 = SYSCTL_CLOCK_CLK_TOP_URT2, - clock_node_uart3 = SYSCTL_CLOCK_CLK_TOP_URT3, - clock_node_uart4 = SYSCTL_CLOCK_CLK_TOP_URT4, - clock_node_uart5 = SYSCTL_CLOCK_CLK_TOP_URT5, - clock_node_uart6 = SYSCTL_CLOCK_CLK_TOP_URT6, - clock_node_uart7 = SYSCTL_CLOCK_CLK_TOP_URT7, - clock_node_uart8 = SYSCTL_CLOCK_CLK_TOP_URT8, - clock_node_uart9 = SYSCTL_CLOCK_CLK_TOP_URT9, - clock_node_uart10 = SYSCTL_CLOCK_CLK_TOP_URT10, - clock_node_uart11 = SYSCTL_CLOCK_CLK_TOP_URT11, - clock_node_uart12 = SYSCTL_CLOCK_CLK_TOP_URT12, - clock_node_uart13 = SYSCTL_CLOCK_CLK_TOP_URT13, - clock_node_uart14 = SYSCTL_CLOCK_CLK_TOP_URT14, - clock_node_uart15 = SYSCTL_CLOCK_CLK_TOP_URT15, - clock_node_ana0 = SYSCTL_CLOCK_CLK_TOP_ANA0, - clock_node_ana1 = SYSCTL_CLOCK_CLK_TOP_ANA1, - clock_node_ana2 = SYSCTL_CLOCK_CLK_TOP_ANA2, - clock_node_ana3 = SYSCTL_CLOCK_CLK_TOP_ANA3, - clock_node_aud0 = SYSCTL_CLOCK_CLK_TOP_AUD0, - clock_node_aud1 = SYSCTL_CLOCK_CLK_TOP_AUD1, - clock_node_can0 = SYSCTL_CLOCK_CLK_TOP_CAN0, - clock_node_can1 = SYSCTL_CLOCK_CLK_TOP_CAN1, - clock_node_can2 = SYSCTL_CLOCK_CLK_TOP_CAN2, - clock_node_can3 = SYSCTL_CLOCK_CLK_TOP_CAN3, - clock_node_can4 = SYSCTL_CLOCK_CLK_TOP_CAN4, - clock_node_can5 = SYSCTL_CLOCK_CLK_TOP_CAN5, - clock_node_can6 = SYSCTL_CLOCK_CLK_TOP_CAN6, - clock_node_can7 = SYSCTL_CLOCK_CLK_TOP_CAN7, - clock_node_xpi0 = SYSCTL_CLOCK_CLK_TOP_XPI0, - clock_node_femc = SYSCTL_CLOCK_CLK_TOP_FEMC, - clock_node_eth0 = SYSCTL_CLOCK_CLK_TOP_ETH0, - clock_node_ptp0 = SYSCTL_CLOCK_CLK_TOP_PTP0, - clock_node_ntmr0 = SYSCTL_CLOCK_CLK_TOP_NTM0, - clock_node_ref0 = SYSCTL_CLOCK_CLK_TOP_REF0, - clock_node_ref1 = SYSCTL_CLOCK_CLK_TOP_REF1, - clock_node_tsn1 = SYSCTL_CLOCK_CLK_TOP_TSW1, - clock_node_tsn2 = SYSCTL_CLOCK_CLK_TOP_TSW2, - clock_node_tsn3 = SYSCTL_CLOCK_CLK_TOP_TSW3, - - clock_node_adc_start, - clock_node_adc0 = clock_node_adc_start, - clock_node_adc1, - clock_node_adc2, - clock_node_adc3, - - clock_node_i2s_start, - clock_node_i2s0 = clock_node_i2s_start, - clock_node_i2s1, - clock_node_end, -} clock_node_t; - -/** - * @brief General clock sources - */ -typedef enum { - clock_source_osc0_clk0 = 0, - clock_source_pll0_clk0 = 1, - clock_source_pll0_clk1 = 2, - clock_source_pll1_clk0 = 3, - clock_source_pll1_clk1 = 4, - clock_source_pll1_clk2 = 5, - clock_source_pll2_clk0 = 6, - clock_source_pll2_clk1 = 7, - clock_source_general_source_end, -} clock_source_t; - -/** - * @brief ADC clock sources - */ -typedef enum { - clock_source_adc_ana_clock = 0, - clock_source_adc_ahb_clock = 1, - clock_source_adc_clk_end, -} clock_source_adc_t; - -/** - * @brief I2S clock sources - */ -typedef enum { - clock_source_i2s_audn_clock = 0, - clock_source_i2s_audx_clock = 1, - clock_source_i2s_clk_end, -} clock_source_i2s_t; - -/** - * @brief CPU low power mode - */ -typedef enum { - cpu_lp_mode_gate_cpu_clock = 0, - cpu_lp_mode_trigger_system_lp = 0x1, - cpu_lp_mode_ungate_cpu_clock = 0x2, -} cpu_lp_mode_t; - -/** - * @brief Monitor targets - */ -/* Monitor Target types */ -typedef enum { - monitor_target_clk_32k_batt = 0, - monitor_target_clk_32k_pmic = 1, - monitor_target_clk_irc24m = 2, - monitor_target_clk_xtal_24m = 3, - monitor_target_clk_usb0_phy = 4, - monitor_target_clk0_osc0 = 20, - monitor_target_clk0_pll0 = 21, - monitor_target_clk1_pll0 = 22, - monitor_target_clk0_pll1 = 23, - monitor_target_clk1_pll1 = 24, - monitor_target_clk2_pll1 = 25, - monitor_target_clk0_pll2 = 26, - monitor_target_clk1_pll2 = 27, - monitor_target_clk_top_cpu0 = 128, - monitor_target_clk_top_mchtmr0 = 129, - monitor_target_clk_top_cpu1 = 130, - monitor_target_clk_top_mchtmr1 = 131, - monitor_target_clk_top_axif = 132, - monitor_target_clk_top_axis = 133, - monitor_target_clk_top_axic = 134, - monitor_target_clk_top_axin = 135, - monitor_target_clk_top_ahb0 = 136, - monitor_target_clk_top_gptmr0 = 137, - monitor_target_clk_top_gptmr1 = 138, - monitor_target_clk_top_gptmr2 = 139, - monitor_target_clk_top_gptmr3 = 140, - monitor_target_clk_top_gptmr4 = 141, - monitor_target_clk_top_gptmr5 = 142, - monitor_target_clk_top_gptmr6 = 143, - monitor_target_clk_top_gptmr7 = 144, - monitor_target_clk_top_i2c0 = 145, - monitor_target_clk_top_i2c1 = 146, - monitor_target_clk_top_i2c2 = 147, - monitor_target_clk_top_i2c3 = 148, - monitor_target_clk_top_i2c4 = 149, - monitor_target_clk_top_i2c5 = 150, - monitor_target_clk_top_i2c6 = 151, - monitor_target_clk_top_i2c7 = 152, - monitor_target_clk_top_spi0 = 153, - monitor_target_clk_top_spi1 = 154, - monitor_target_clk_top_spi2 = 155, - monitor_target_clk_top_spi3 = 156, - monitor_target_clk_top_spi4 = 157, - monitor_target_clk_top_spi5 = 158, - monitor_target_clk_top_spi6 = 159, - monitor_target_clk_top_spi7 = 160, - monitor_target_clk_top_uart0 = 161, - monitor_target_clk_top_uart1 = 162, - monitor_target_clk_top_uart2 = 163, - monitor_target_clk_top_uart3 = 164, - monitor_target_clk_top_uart4 = 165, - monitor_target_clk_top_uart5 = 166, - monitor_target_clk_top_uart6 = 167, - monitor_target_clk_top_uart7 = 168, - monitor_target_clk_top_uart8 = 169, - monitor_target_clk_top_uart9 = 170, - monitor_target_clk_top_uart10 = 171, - monitor_target_clk_top_uart11 = 172, - monitor_target_clk_top_uart12 = 173, - monitor_target_clk_top_uart13 = 174, - monitor_target_clk_top_uart14 = 175, - monitor_target_clk_top_uart15 = 176, - monitor_target_clk_top_can0 = 177, - monitor_target_clk_top_can1 = 178, - monitor_target_clk_top_can2 = 179, - monitor_target_clk_top_can3 = 180, - monitor_target_clk_top_can4 = 181, - monitor_target_clk_top_can5 = 182, - monitor_target_clk_top_can6 = 183, - monitor_target_clk_top_can7 = 184, - monitor_target_clk_top_xpi0 = 185, - monitor_target_clk_top_femc = 186, - monitor_target_clk_top_ana0 = 187, - monitor_target_clk_top_ana1 = 188, - monitor_target_clk_top_ana2 = 189, - monitor_target_clk_top_ana3 = 190, - monitor_target_clk_top_aud0 = 191, - monitor_target_clk_top_aud1 = 192, - monitor_target_clk_top_eth0 = 193, - monitor_target_clk_top_ptp0 = 194, - monitor_target_clk_top_ref0 = 195, - monitor_target_clk_top_ref1 = 196, - monitor_target_clk_top_ntmr0 = 197, - monitor_target_clk_top_tsn1 = 198, - monitor_target_clk_top_tsn2 = 199, - monitor_target_clk_top_tsn3 = 200, -} monitor_target_t; - -/** - * @brief Monitor work mode - */ -typedef enum { - monitor_work_mode_compare = 0, - monitor_work_mode_record = 1, -} monitor_work_mode_t; - -/** - * @brief Monitor accuracy - */ -typedef enum { - monitor_accuracy_1khz = 0, - monitor_accuracy_1hz = 1, -} monitor_accuracy_t; - -/** - * @brief Monitor reference clock source - */ -typedef enum { - monitor_reference_32khz = 0, - monitor_reference_24mhz = 1, -} monitor_reference_t; - -typedef enum { - cpu_event_flag_mask_reset = SYSCTL_CPU_LP_RESET_FLAG_MASK, - cpu_event_flag_mask_sleep = SYSCTL_CPU_LP_SLEEP_FLAG_MASK, - cpu_event_flag_mask_wake = SYSCTL_CPU_LP_WAKE_FLAG_MASK, - cpu_event_flag_mask_all = SYSCTL_CPU_LP_RESET_FLAG_MASK | SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK, -} cpu_event_flag_mask_t; - -/** - * @brief Monitor config - */ -typedef struct monitor_config { - uint8_t divide_by; /**< Divider to be used for OBS output to pads */ - monitor_work_mode_t mode; /**< Monitor work mode */ - monitor_accuracy_t accuracy; /**< Monitor reference accuracy */ - monitor_reference_t reference; /**< Monitor reference clock source */ - monitor_target_t target; /**< Monitor target */ - bool start_measure; /**< Start flag */ - bool enable_output; /**< Enable output to pads if true */ - uint32_t high_limit; /**< Maximum frequency at compare mode */ - uint32_t low_limit; /**< Minimum frequency at compare mode */ -} monitor_config_t; - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Check if monitor result is valid - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * - * @return true if it is valid - */ -static inline bool sysctl_monitor_result_is_valid(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - return SYSCTL_MONITOR_CONTROL_VALID_GET(ptr->MONITOR[monitor_index].CONTROL); -} - -/** - * @brief Get target monitor instance result - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return value of monitor result measured - */ -static inline uint32_t sysctl_monitor_get_current_result(SYSCTL_Type *ptr, uint8_t monitor_index) -{ - while (!sysctl_monitor_result_is_valid(ptr, monitor_index)) { - } - return ptr->MONITOR[monitor_index].CURRENT; -} - -/** - * @brief Set work mode for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] mode monitor_work_mode_compare, monitor_work_mode_record - */ -static inline void sysctl_monitor_set_work_mode(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_work_mode_t mode) -{ - ptr->MONITOR[monitor_index].CONTROL = (ptr->MONITOR[monitor_index].CONTROL & ~SYSCTL_MONITOR_CONTROL_MODE_MASK) | - (SYSCTL_MONITOR_CONTROL_MODE_SET(mode)); -} - -/** - * @brief Set minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_low(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit measurement high limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit_high(SYSCTL_Type *ptr, uint8_t monitor_index, uint32_t limit) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit); - return status_success; -} - -/** - * @brief Set frequency limit for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] limit_high measurement high limit - * @param[in] limit_low measurement low limit - */ -static inline hpm_stat_t sysctl_monitor_set_limit(SYSCTL_Type *ptr, - uint8_t monitor_index, - uint32_t limit_high, - uint32_t limit_low) -{ - if (ptr->MONITOR[monitor_index].CONTROL & SYSCTL_MONITOR_CONTROL_MODE_MASK) { - return status_invalid_argument; - } - ptr->MONITOR[monitor_index].HIGH_LIMIT = SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(limit_high); - ptr->MONITOR[monitor_index].LOW_LIMIT = SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(limit_low); - return status_success; -} - -/** - * @brief Get maximum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current high limit value - */ -static inline uint32_t sysctl_monitor_get_limit_high(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(ptr->MONITOR[monitor_index].HIGH_LIMIT); -} - -/** - * @brief Get minimum frequency for target monitor instance - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @return current low limit value - */ -static inline uint32_t sysctl_monitor_get_limit_low(SYSCTL_Type *ptr, uint32_t monitor_index) -{ - return SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(ptr->MONITOR[monitor_index].LOW_LIMIT); -} - -/** - * @brief Measure specific target frequency - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index specific monitor instance to be used - * @param[in] target monitor target to be measured - * @param[in] enable_output enable clock obs output - * @return frequency of monitor target measured - */ -uint32_t sysctl_monitor_measure_frequency(SYSCTL_Type *ptr, - uint8_t monitor_index, - monitor_target_t target, - bool enable_output); - -/** - * @brief Link current CPU core its own group - * - * Once it is linked, peripherals state in that group will keep on as long as this core is not in low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_enable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].SET = 1 << cpu_index; -} - -/** - * @brief Unlink current CPU core with its own group - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index to enable its own affiliated group - */ -static inline void sysctl_set_disable_cpu_affiliate(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->AFFILIATE[cpu_index].CLEAR = 1 << cpu_index; -} - -/** - * @brief Check if any resource is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any resource is busy - */ -static inline bool sysctl_resource_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->RESOURCE[0] & SYSCTL_RESOURCE_GLB_BUSY_MASK; -} - -/** - * @brief Check if specific target is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return true if target resource is busy - */ -static inline bool sysctl_resource_target_is_busy(SYSCTL_Type *ptr, sysctl_resource_t resource) -{ - return ptr->RESOURCE[resource] & SYSCTL_RESOURCE_LOC_BUSY_MASK; -} - -/** - * @brief Set target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @param[in] mode target resource mode - */ -static inline void sysctl_resource_target_set_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource, - sysctl_resource_mode_t mode) -{ - ptr->RESOURCE[resource] = - (ptr->RESOURCE[resource] & ~SYSCTL_RESOURCE_MODE_MASK) | - SYSCTL_RESOURCE_MODE_SET(mode); -} - -/** - * @brief Get target mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource target resource index - * @return target resource mode - */ -static inline uint8_t sysctl_resource_target_get_mode(SYSCTL_Type *ptr, - sysctl_resource_t resource) -{ - return SYSCTL_RESOURCE_MODE_GET(ptr->RESOURCE[resource]); -} - -/** - * @brief Disable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].CLEAR = mask; -} - -/** - * @brief Disable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Disable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to clear - */ -static inline void sysctl_clear_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_clear_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu_lp_retention_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t mask) -{ - ptr->RETENTION[cpu_index].SET = mask; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu0_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 0, mask); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mask bit mask to set - */ -static inline void sysctl_set_cpu1_lp_retention_with_mask(SYSCTL_Type *ptr, uint32_t mask) -{ - sysctl_set_cpu_lp_retention_with_mask(ptr, 1, mask); -} - -/** - * @brief Enable resource retention when specific CPU enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index cpu index - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu_lp_retention(SYSCTL_Type *ptr, uint8_t cpu_index, uint32_t value) -{ - ptr->RETENTION[cpu_index].VALUE = value; -} - -/** - * @brief Enable resource retention when CPU0 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu0_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 0, value); -} - -/** - * @brief Enable resource retention when CPU1 enters stop mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] value value to be set - */ -static inline void sysctl_set_cpu1_lp_retention(SYSCTL_Type *ptr, uint32_t value) -{ - sysctl_set_cpu_lp_retention(ptr, 1, value); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu_lp_retain_domain(SYSCTL_Type *ptr, - uint8_t cpu_index, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - uint8_t set_mask = 0x1; - if (domain < sysctl_retention_domain_xtal24m) { - set_mask = retain_mem ? 0x3 : 0x1; - } - ptr->RETENTION[cpu_index].SET = (set_mask << domain); -} - -/** - * @brief Retain target domain for specific CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu0_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 0, domain, retain_mem); -} - -/** - * @brief Retain target domain for specific CPU - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain power to be retained - * @param[in] retain_mem set true to retain memory/register of target domain - */ -static inline void sysctl_set_cpu1_lp_retain_domain(SYSCTL_Type *ptr, - sysctl_retention_domain_t domain, - bool retain_mem) -{ - sysctl_set_cpu_lp_retain_domain(ptr, 1, domain, retain_mem); -} - -/** - * @brief Check if any clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @return true if any clock is busy - */ -static inline bool sysctl_clock_any_is_busy(SYSCTL_Type *ptr) -{ - return ptr->CLOCK[0] & SYSCTL_CLOCK_GLB_BUSY_MASK; -} - -/** - * @brief Check if target clock is busy - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - * @return true if target clock is busy - */ -static inline bool sysctl_clock_target_is_busy(SYSCTL_Type *ptr, uint32_t clock) -{ - return ptr->CLOCK[clock] & SYSCTL_CLOCK_LOC_BUSY_MASK; -} - -/** - * @brief Preserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_preserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] |= SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Unpreserve clock setting for certain node - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] clock target clock - */ -static inline void sysctl_clock_unpreserve_settings(SYSCTL_Type *ptr, clock_node_t clock) -{ - ptr->CLOCK[clock] &= ~SYSCTL_CLOCK_PRESERVE_MASK; -} - -/** - * @brief Set clock preset - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] preset preset - */ -static inline void sysctl_clock_set_preset(SYSCTL_Type *ptr, sysctl_preset_t preset) -{ - ptr->GLOBAL00 = (ptr->GLOBAL00 & ~SYSCTL_GLOBAL00_MUX_MASK) | SYSCTL_GLOBAL00_MUX_SET(preset); -} - -/** - * @brief Check if target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken wakeup reset - */ -static inline bool sysctl_reset_check_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain wakeup status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_wakeup_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - * @return true if target domain was taken reset - */ -static inline bool sysctl_reset_check_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - return ptr->RESET[domain].CONTROL & SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_flag(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK; -} - -/** - * @brief Clear target reset domain for all reset status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] domain target domain to be checked - */ -static inline void sysctl_reset_clear_target_domain_all_flags(SYSCTL_Type *ptr, sysctl_reset_domain_t domain) -{ - ptr->RESET[domain].CONTROL |= SYSCTL_RESET_CONTROL_FLAG_MASK | SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK; -} - -/** - * @brief Get target CPU wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_wakeup_source_status(SYSCTL_Type *ptr, uint8_t cpu_index, uint8_t status_index) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index]; -} - -/** - * @brief Get target CPU0 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu0_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 0, status_index); -} - -/** - * @brief Get target CPU1 wakeup source status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @return wakeup source status mask - */ -static inline uint32_t sysctl_get_cpu1_wakeup_source_status(SYSCTL_Type *ptr, uint8_t status_index) -{ - return sysctl_get_wakeup_source_status(ptr, 1, status_index); -} - -/** - * @brief Check wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t status_index, - uint32_t mask) -{ - return ptr->CPU[cpu_index].WAKEUP_STATUS[status_index] & mask; -} - -/** - * @brief Check CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_cpu0_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 0, status_index, mask); -} - -/** - * @brief Check CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] status_index wakeup status index 0 - 7 - * @param[in] mask expected status mask - * @return wakeup status according to given bit mask - */ -static inline uint32_t sysctl_check_cpu1_wakeup_source_status_with_mask(SYSCTL_Type *ptr, - uint8_t status_index, - uint32_t mask) -{ - return sysctl_check_wakeup_source_status_with_mask(ptr, 1, status_index, mask); -} - -/** - * @brief Enable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[0].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Enable CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_enable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[1].WAKEUP_ENABLE[enable_index] |= mask; -} - -/** - * @brief Disable wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint8_t enable_index, - uint32_t mask) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[enable_index] &= ~mask; -} - -/** - * @brief Disable CPU0 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 0, enable_index, mask); -} - - -/** - * @brief Disable CPU1 wakeup source status with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] enable_index wakeup enable index 0 - 7 - * @param[in] mask expected status mask - */ -static inline void sysctl_disable_cpu1_wakeup_source_with_mask(SYSCTL_Type *ptr, - uint8_t enable_index, - uint32_t mask) -{ - sysctl_disable_wakeup_source_with_mask(ptr, 1, enable_index, mask); -} - -/** - * @brief Disable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_wakeup_source_with_irq(SYSCTL_Type *ptr, - uint8_t cpu_index, - uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num >> 2] &= ~(1UL << (irq_num % 32)); -} - -/** - * @brief Disable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 0, irq_num); -} - - -/** - * @brief Disable CPU1 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be disabled as wakeup source - */ -static inline void sysctl_disable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_disable_wakeup_source_with_irq(ptr, 1, irq_num); -} - -/** - * @brief Enable wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_wakeup_source_with_irq(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t irq_num) -{ - ptr->CPU[cpu_index].WAKEUP_ENABLE[irq_num / 32] |= 1UL << (irq_num & 0x1F); -} - -/** - * @brief Enable CPU0 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu0_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 0, irq_num); -} - -/** - * @brief Enable CPU1 wakeup source status with irq - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] irq_num irq number to be set as wakeup source - */ -static inline void sysctl_enable_cpu1_wakeup_source_with_irq(SYSCTL_Type *ptr, uint16_t irq_num) -{ - sysctl_enable_wakeup_source_with_irq(ptr, 1, irq_num); -} - -/** - * @brief Lock CPU gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu_lock_gpr_with_mask(SYSCTL_Type *ptr, uint8_t cpu_index, uint16_t gpr_mask) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_GPR_SET(gpr_mask); -} - - -/** - * @brief Lock CPU0 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu0_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 0, gpr_mask); -} - -/** - * @brief Lock CPU1 gpr with mask - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] gpr_mask bit mask of gpr registers to be locked - */ -static inline void sysctl_cpu1_lock_gpr_with_mask(SYSCTL_Type *ptr, uint16_t gpr_mask) -{ - sysctl_cpu_lock_gpr_with_mask(ptr, 1, gpr_mask); -} - -/** - * @brief Lock CPU lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_cpu_lock(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LOCK |= SYSCTL_CPU_LOCK_LOCK_MASK; -} - -/** - * @brief Lock CPU0 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu0_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 0); -} - -/** - * @brief Lock CPU1 lock - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_cpu1_lock(SYSCTL_Type *ptr) -{ - sysctl_cpu_lock(ptr, 1); -} - -/** - * @brief Set CPU low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu_lp_mode(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_lp_mode_t mode) -{ - ptr->CPU[cpu_index].LP = (ptr->CPU[cpu_index].LP & ~(SYSCTL_CPU_LP_MODE_MASK)) | (mode); -} - -/** - * @brief Set CPU0 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu0_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 0, mode); -} - -/** - * @brief Set CPU1 low power mode - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] mode target mode to set - */ -static inline void sysctl_set_cpu1_lp_mode(SYSCTL_Type *ptr, cpu_lp_mode_t mode) -{ - sysctl_set_cpu_lp_mode(ptr, 1, mode); -} - -/** - * @brief Clear CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index, cpu_event_flag_mask_t flags) -{ - ptr->CPU[cpu_index].LP |= - ((SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK) & flags); -} - -/** - * @brief Clear CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu0_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 0, flags); -} - -/** - * @brief Clear CPU1 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] flags flag mask to be cleared - */ -static inline void sysctl_clear_cpu1_flags(SYSCTL_Type *ptr, cpu_event_flag_mask_t flags) -{ - sysctl_clear_cpu_flags(ptr, 1, flags); -} - -/** - * @brief Get CPU event flags - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu_flags(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ptr->CPU[cpu_index].LP & - (SYSCTL_CPU_LP_SLEEP_FLAG_MASK | SYSCTL_CPU_LP_WAKE_FLAG_MASK | SYSCTL_CPU_LP_RESET_FLAG_MASK); -} - -/** - * @brief Get CPU0 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu0_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 0); -} - -/** - * @brief Get CPU1 event flags - * - * @param[in] ptr SYSCTL_Type base address - * @retval event flag mask - */ -static inline uint32_t sysctl_get_cpu1_flags(SYSCTL_Type *ptr) -{ - return sysctl_get_cpu_flags(ptr, 1); -} - -/** - * @brief Release cpu - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - */ -static inline void sysctl_release_cpu(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - ptr->CPU[cpu_index].LP &= ~SYSCTL_CPU_LP_HALT_MASK; -} - -/** - * @brief Release cpu1 - * - * @param[in] ptr SYSCTL_Type base address - */ -static inline void sysctl_release_cpu1(SYSCTL_Type *ptr) -{ - sysctl_release_cpu(ptr, 1); -} - -/** - * @brief Check whether CPU is released or not - * - * @param [in] ptr SYSCTL_Type base address - * @param[in] cpu_index CPU index - * @retval true CPU is released - * @retval false CPU is on-hold - */ -static inline bool sysctl_is_cpu_released(SYSCTL_Type *ptr, uint8_t cpu_index) -{ - return ((ptr->CPU[cpu_index].LP & SYSCTL_CPU_LP_HALT_MASK) == 0U); -} - -/** - * @brief Check whether CPU1 is released or not - * - * @param [in] ptr SYSCTL_Type base address - * @retval true CPU1 is released - * @retval false CPU1 is on-hold - */ -static inline bool sysctl_is_cpu1_released(SYSCTL_Type *ptr) -{ - return sysctl_is_cpu_released(ptr, 1); -} - -/** - * @brief Config lock - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @param[in] divide_by clock frequency divider - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_config_clock(SYSCTL_Type *ptr, clock_node_t node, clock_source_t source, uint32_t divide_by); - -/** - * @brief Set ADC clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_adc_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_adc_t source); - -/** - * @brief Set I2S clock mux - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] node clock node to be configured - * @param[in] source clock source to be used - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_i2s_clock_mux(SYSCTL_Type *ptr, clock_node_t node, clock_source_i2s_t source); - -/** - * @brief Enable group resource - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be modified - * @param[in] resource target resource to be added/removed from group - * @param[in] enable set true to add resource, remove otherwise - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_enable_group_resource(SYSCTL_Type *ptr, - uint8_t group, - sysctl_resource_t resource, - bool enable); - -/** - * @brief Check group resource enable status - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be checked - * @param[in] resource target resource to be checked from group - * @return enable true if resource enable, false if resource disable - */ -bool sysctl_check_group_resource_enable(SYSCTL_Type *ptr, uint8_t group, sysctl_resource_t linkable_resource); - -/** - * @brief Get group resource value - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] group target group to be getted - * @param[in] index target group index - * @return group index value - */ -uint32_t sysctl_get_group_resource_value(SYSCTL_Type *ptr, uint8_t group, uint8_t index); - -/** - * @brief Add resource to CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource resource to be added to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU0 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU0 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu0(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Add resource to CPU1 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be added to CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_add_resource_to_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Remove resource from CPU1 - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] resource Resource to be removed to CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_remove_resource_from_cpu1(SYSCTL_Type *ptr, sysctl_resource_t resource); - -/** - * @brief Get default monitor config - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_get_default_config(SYSCTL_Type *ptr, monitor_config_t *config); - -/** - * @brief Initialize Monitor - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] monitor_index Monitor instance to be initialized - * @param[in] config Monitor config structure pointer - */ -void sysctl_monitor_init(SYSCTL_Type *ptr, uint8_t monitor_index, monitor_config_t *config); - -/** - * @brief Save data to CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved from CPU0 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu0_get_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set data to CPU1 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[in] data Pointer to data buffer - * @param[in] lock Set true to lock written GPR registers after setting - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_cpu1_set_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data, bool lock); - -/** - * @brief Get data saved in CPU1 GPR starting from given index - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] start Starting GPR index - * @param[in] count Number of GPR registers to set - * @param[out] data Pointer of buffer to save data - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_get_cpu1_gpr(SYSCTL_Type *ptr, uint8_t start, uint8_t count, uint32_t *data); - -/** - * @brief Set entry point on CPU boot or wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] cpu CPU index - * @param[in] entry Entry address for CPU - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu_entry(SYSCTL_Type *ptr, uint8_t cpu, uint32_t entry); - -/** - * @brief Set entry point on CPU0 wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU0 on its wakeup - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu0_wakeup_entry(SYSCTL_Type *ptr, uint32_t entry); - -/** - * @brief Set entry point on either CPU1 boot or wakeup - * - * @param[in] ptr SYSCTL_Type base address - * @param[in] entry Entry address for CPU1 - * @return status_success if everything is okay - */ -hpm_stat_t sysctl_set_cpu1_entry(SYSCTL_Type *ptr, uint32_t entry); - -#ifdef __cplusplus -} -#endif -/** - * @} - */ -#endif /* HPM_SYSCTL_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.c deleted file mode 100644 index 759a323b2bc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_trgm_soc_drv.h" - -void trgm_adc_matrix_config(TRGM_Type *ptr, trgm_adc_matrix_out_t consumer, trgm_adc_matrix_in_t src, bool inv_val) -{ - uint8_t sel; - - sel = (uint8_t)src; - if (inv_val) { - sel |= BIT7_MASK; - } - - switch (consumer) { - case trgm_adc_matrix_output_to_rdc0_adc0: - ptr->ADC_MATRIX_SEL0 = (ptr->ADC_MATRIX_SEL0 & ~TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK) - | TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_rdc0_adc1: - ptr->ADC_MATRIX_SEL0 = (ptr->ADC_MATRIX_SEL0 & ~TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK) - | TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_rdc1_adc0: - ptr->ADC_MATRIX_SEL0 = (ptr->ADC_MATRIX_SEL0 & ~TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK) - | TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_rdc1_adc1: - ptr->ADC_MATRIX_SEL0 = (ptr->ADC_MATRIX_SEL0 & ~TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK) - | TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_qei2_adc0: - ptr->ADC_MATRIX_SEL1 = (ptr->ADC_MATRIX_SEL1 & ~TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK) - | TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_qei2_adc1: - ptr->ADC_MATRIX_SEL1 = (ptr->ADC_MATRIX_SEL1 & ~TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK) - | TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_qei3_adc0: - ptr->ADC_MATRIX_SEL1 = (ptr->ADC_MATRIX_SEL1 & ~TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK) - | TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_qei3_adc1: - ptr->ADC_MATRIX_SEL1 = (ptr->ADC_MATRIX_SEL1 & ~TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK) - | TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_vsc0_adc0: - ptr->ADC_MATRIX_SEL2 = (ptr->ADC_MATRIX_SEL2 & ~TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK) - | TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_vsc0_adc1: - ptr->ADC_MATRIX_SEL2 = (ptr->ADC_MATRIX_SEL2 & ~TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK) - | TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_vsc0_adc2: - ptr->ADC_MATRIX_SEL2 = (ptr->ADC_MATRIX_SEL2 & ~TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK) - | TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_vsc1_adc0: - ptr->ADC_MATRIX_SEL2 = (ptr->ADC_MATRIX_SEL2 & ~TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK) - | TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_vsc1_adc1: - ptr->ADC_MATRIX_SEL3 = (ptr->ADC_MATRIX_SEL3 & ~TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK) - | TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_vsc1_adc2: - ptr->ADC_MATRIX_SEL3 = (ptr->ADC_MATRIX_SEL3 & ~TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK) - | TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_clc0_id_adc: - ptr->ADC_MATRIX_SEL3 = (ptr->ADC_MATRIX_SEL3 & ~TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK) - | TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_clc0_iq_adc: - ptr->ADC_MATRIX_SEL3 = (ptr->ADC_MATRIX_SEL3 & ~TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK) - | TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_clc0_vb_adc: - ptr->ADC_MATRIX_SEL4 = (ptr->ADC_MATRIX_SEL4 & ~TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK) - | TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_clc1_id_adc: - ptr->ADC_MATRIX_SEL4 = (ptr->ADC_MATRIX_SEL4 & ~TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK) - | TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_clc1_iq_adc: - ptr->ADC_MATRIX_SEL4 = (ptr->ADC_MATRIX_SEL4 & ~TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK) - | TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SET(sel); - break; - case trgm_adc_matrix_output_to_clc1_vb_adc: - ptr->ADC_MATRIX_SEL4 = (ptr->ADC_MATRIX_SEL4 & ~TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK) - | TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SET(sel); - break; - default: - break; - } -} - -void trgm_dac_matrix_config(TRGM_Type *ptr, trgm_dac_matrix_out_t consumer, trgm_dac_matrix_in_t src, bool inv_val) -{ - uint8_t sel; - - sel = (uint8_t)src; - if (inv_val) { - sel |= BIT7_MASK; - } - - switch (consumer) { - case trgm_dac_matrix_output_to_acmp0: - ptr->DAC_MATRIX_SEL0 = (ptr->DAC_MATRIX_SEL0 & ~TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp1: - ptr->DAC_MATRIX_SEL0 = (ptr->DAC_MATRIX_SEL0 & ~TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp2: - ptr->DAC_MATRIX_SEL0 = (ptr->DAC_MATRIX_SEL0 & ~TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp3: - ptr->DAC_MATRIX_SEL0 = (ptr->DAC_MATRIX_SEL0 & ~TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp4: - ptr->DAC_MATRIX_SEL1 = (ptr->DAC_MATRIX_SEL1 & ~TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp5: - ptr->DAC_MATRIX_SEL1 = (ptr->DAC_MATRIX_SEL1 & ~TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp6: - ptr->DAC_MATRIX_SEL1 = (ptr->DAC_MATRIX_SEL1 & ~TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_acmp7: - ptr->DAC_MATRIX_SEL1 = (ptr->DAC_MATRIX_SEL1 & ~TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm0_dac0: - ptr->DAC_MATRIX_SEL2 = (ptr->DAC_MATRIX_SEL2 & ~TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK) - | TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm0_dac1: - ptr->DAC_MATRIX_SEL2 = (ptr->DAC_MATRIX_SEL2 & ~TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK) - | TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm0_dac2: - ptr->DAC_MATRIX_SEL2 = (ptr->DAC_MATRIX_SEL2 & ~TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK) - | TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm0_dac3: - ptr->DAC_MATRIX_SEL2 = (ptr->DAC_MATRIX_SEL2 & ~TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK) - | TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm1_dac0: - ptr->DAC_MATRIX_SEL3 = (ptr->DAC_MATRIX_SEL3 & ~TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK) - | TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm1_dac1: - ptr->DAC_MATRIX_SEL3 = (ptr->DAC_MATRIX_SEL3 & ~TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK) - | TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm1_dac2: - ptr->DAC_MATRIX_SEL3 = (ptr->DAC_MATRIX_SEL3 & ~TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK) - | TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm1_dac3: - ptr->DAC_MATRIX_SEL3 = (ptr->DAC_MATRIX_SEL3 & ~TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK) - | TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm2_dac0: - ptr->DAC_MATRIX_SEL4 = (ptr->DAC_MATRIX_SEL4 & ~TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK) - | TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm2_dac1: - ptr->DAC_MATRIX_SEL4 = (ptr->DAC_MATRIX_SEL4 & ~TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK) - | TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm2_dac2: - ptr->DAC_MATRIX_SEL4 = (ptr->DAC_MATRIX_SEL4 & ~TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK) - | TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm2_dac3: - ptr->DAC_MATRIX_SEL4 = (ptr->DAC_MATRIX_SEL4 & ~TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK) - | TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm3_dac0: - ptr->DAC_MATRIX_SEL5 = (ptr->DAC_MATRIX_SEL5 & ~TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK) - | TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm3_dac1: - ptr->DAC_MATRIX_SEL5 = (ptr->DAC_MATRIX_SEL5 & ~TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK) - | TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm3_dac2: - ptr->DAC_MATRIX_SEL5 = (ptr->DAC_MATRIX_SEL5 & ~TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK) - | TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_pwm3_dac3: - ptr->DAC_MATRIX_SEL5 = (ptr->DAC_MATRIX_SEL5 & ~TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK) - | TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo0_vd_dac: - ptr->DAC_MATRIX_SEL6 = (ptr->DAC_MATRIX_SEL6 & ~TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo0_vq_dac: - ptr->DAC_MATRIX_SEL6 = (ptr->DAC_MATRIX_SEL6 & ~TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo1_vd_dac: - ptr->DAC_MATRIX_SEL6 = (ptr->DAC_MATRIX_SEL6 & ~TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo1_vq_dac: - ptr->DAC_MATRIX_SEL6 = (ptr->DAC_MATRIX_SEL6 & ~TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo2_vd_dac: - ptr->DAC_MATRIX_SEL7 = (ptr->DAC_MATRIX_SEL7 & ~TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo2_vq_dac: - ptr->DAC_MATRIX_SEL7 = (ptr->DAC_MATRIX_SEL7 & ~TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo3_vd_dac: - ptr->DAC_MATRIX_SEL7 = (ptr->DAC_MATRIX_SEL7 & ~TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SET(sel); - break; - case trgm_dac_matrix_output_to_qeo3_vq_dac: - ptr->DAC_MATRIX_SEL7 = (ptr->DAC_MATRIX_SEL7 & ~TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK) - | TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SET(sel); - break; - default: - break; - } -} - -void trgm_pos_matrix_config(TRGM_Type *ptr, trgm_pos_matrix_out_t consumer, trgm_pos_matrix_in_t src, bool inv_val) -{ - uint8_t sel; - - sel = (uint8_t)src; - if (inv_val) { - sel |= BIT7_MASK; - } - - switch (consumer) { - case trgm_pos_matrix_output_to_sei_pos0: - ptr->POS_MATRIX_SEL0 = (ptr->POS_MATRIX_SEL0 & ~TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) - | TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_sei_pos1: - ptr->POS_MATRIX_SEL0 = (ptr->POS_MATRIX_SEL0 & ~TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) - | TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_sei_pos2: - ptr->POS_MATRIX_SEL0 = (ptr->POS_MATRIX_SEL0 & ~TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK) - | TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_sei_pos3: - ptr->POS_MATRIX_SEL0 = (ptr->POS_MATRIX_SEL0 & ~TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK) - | TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_mtg0: - ptr->POS_MATRIX_SEL1 = (ptr->POS_MATRIX_SEL1 & ~TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_mtg1: - ptr->POS_MATRIX_SEL1 = (ptr->POS_MATRIX_SEL1 & ~TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_qeo0: - ptr->POS_MATRIX_SEL1 = (ptr->POS_MATRIX_SEL1 & ~TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_qeo1: - ptr->POS_MATRIX_SEL1 = (ptr->POS_MATRIX_SEL1 & ~TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_qeo2: - ptr->POS_MATRIX_SEL2 = (ptr->POS_MATRIX_SEL2 & ~TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_qeo3: - ptr->POS_MATRIX_SEL2 = (ptr->POS_MATRIX_SEL2 & ~TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_vsc0: - ptr->POS_MATRIX_SEL2 = (ptr->POS_MATRIX_SEL2 & ~TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SET(sel); - break; - case trgm_pos_matrix_output_to_vsc1: - ptr->POS_MATRIX_SEL2 = (ptr->POS_MATRIX_SEL2 & ~TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK) - | TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SET(sel); - break; - default: - break; - } -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.h deleted file mode 100644 index a230ec7a502..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgm_soc_drv.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef HPM_TRGM_SOC_DRV_H -#define HPM_TRGM_SOC_DRV_H - -#include "hpm_soc.h" -#include "hpm_trgm_regs.h" - -typedef enum { - trgm_adc_matrix_output_to_rdc0_adc0 = 0, - trgm_adc_matrix_output_to_rdc0_adc1, - trgm_adc_matrix_output_to_rdc1_adc0, - trgm_adc_matrix_output_to_rdc1_adc1, - trgm_adc_matrix_output_to_qei2_adc0, - trgm_adc_matrix_output_to_qei2_adc1, - trgm_adc_matrix_output_to_qei3_adc0, - trgm_adc_matrix_output_to_qei3_adc1, - trgm_adc_matrix_output_to_vsc0_adc0, - trgm_adc_matrix_output_to_vsc0_adc1, - trgm_adc_matrix_output_to_vsc0_adc2, - trgm_adc_matrix_output_to_vsc1_adc0, - trgm_adc_matrix_output_to_vsc1_adc1, - trgm_adc_matrix_output_to_vsc1_adc2, - trgm_adc_matrix_output_to_clc0_id_adc, - trgm_adc_matrix_output_to_clc0_iq_adc, - trgm_adc_matrix_output_to_clc0_vb_adc, - trgm_adc_matrix_output_to_clc1_id_adc, - trgm_adc_matrix_output_to_clc1_iq_adc, - trgm_adc_matrix_output_to_clc1_vb_adc, -} trgm_adc_matrix_out_t; - -typedef enum { - trgm_adc_matrix_in_from_adc0 = 0, - trgm_adc_matrix_in_from_adc1, - trgm_adc_matrix_in_from_adc2, - trgm_adc_matrix_in_from_adc3, - trgm_adc_matrix_in_from_sdm_adc0, - trgm_adc_matrix_in_from_sdm_adc1, - trgm_adc_matrix_in_from_sdm_adc2, - trgm_adc_matrix_in_from_sdm_adc3, - trgm_adc_matrix_in_from_sdm_adc4, - trgm_adc_matrix_in_from_sdm_adc5, - trgm_adc_matrix_in_from_sdm_adc6, - trgm_adc_matrix_in_from_sdm_adc7, - trgm_adc_matrix_in_from_vsc0_id_adc, - trgm_adc_matrix_in_from_vsc0_iq_adc, - trgm_adc_matrix_in_from_vsc1_id_adc, - trgm_adc_matrix_in_from_vsc1_iq_adc, -} trgm_adc_matrix_in_t; - -typedef enum { - trgm_dac_matrix_output_to_acmp0 = 0, - trgm_dac_matrix_output_to_acmp1, - trgm_dac_matrix_output_to_acmp2, - trgm_dac_matrix_output_to_acmp3, - trgm_dac_matrix_output_to_acmp4, - trgm_dac_matrix_output_to_acmp5, - trgm_dac_matrix_output_to_acmp6, - trgm_dac_matrix_output_to_acmp7, - trgm_dac_matrix_output_to_pwm0_dac0, - trgm_dac_matrix_output_to_pwm0_dac1, - trgm_dac_matrix_output_to_pwm0_dac2, - trgm_dac_matrix_output_to_pwm0_dac3, - trgm_dac_matrix_output_to_pwm1_dac0, - trgm_dac_matrix_output_to_pwm1_dac1, - trgm_dac_matrix_output_to_pwm1_dac2, - trgm_dac_matrix_output_to_pwm1_dac3, - trgm_dac_matrix_output_to_pwm2_dac0, - trgm_dac_matrix_output_to_pwm2_dac1, - trgm_dac_matrix_output_to_pwm2_dac2, - trgm_dac_matrix_output_to_pwm2_dac3, - trgm_dac_matrix_output_to_pwm3_dac0, - trgm_dac_matrix_output_to_pwm3_dac1, - trgm_dac_matrix_output_to_pwm3_dac2, - trgm_dac_matrix_output_to_pwm3_dac3, - trgm_dac_matrix_output_to_qeo0_vd_dac, - trgm_dac_matrix_output_to_qeo0_vq_dac, - trgm_dac_matrix_output_to_qeo1_vd_dac, - trgm_dac_matrix_output_to_qeo1_vq_dac, - trgm_dac_matrix_output_to_qeo2_vd_dac, - trgm_dac_matrix_output_to_qeo2_vq_dac, - trgm_dac_matrix_output_to_qeo3_vd_dac, - trgm_dac_matrix_output_to_qeo3_vq_dac, -} trgm_dac_matrix_out_t; - -typedef enum { - trgm_dac_matrix_in_from_qeo0_dac0 = 0, - trgm_dac_matrix_in_from_qeo0_dac1, - trgm_dac_matrix_in_from_qeo0_dac2, - trgm_dac_matrix_in_from_qeo1_dac0, - trgm_dac_matrix_in_from_qeo1_dac1, - trgm_dac_matrix_in_from_qeo1_dac2, - trgm_dac_matrix_in_from_qeo2_dac0, - trgm_dac_matrix_in_from_qeo2_dac1, - trgm_dac_matrix_in_from_qeo2_dac2, - trgm_dac_matrix_in_from_qeo3_dac0, - trgm_dac_matrix_in_from_qeo3_dac1, - trgm_dac_matrix_in_from_qeo3_dac2, - trgm_dac_matrix_in_from_clc0_vd_dac, - trgm_dac_matrix_in_from_clc0_vq_dac, - trgm_dac_matrix_in_from_clc1_vd_dac, - trgm_dac_matrix_in_from_clc1_vq_dac, -} trgm_dac_matrix_in_t; - -typedef enum { - trgm_pos_matrix_output_to_sei_pos0 = 0, - trgm_pos_matrix_output_to_sei_pos1, - trgm_pos_matrix_output_to_sei_pos2, - trgm_pos_matrix_output_to_sei_pos3, - trgm_pos_matrix_output_to_mtg0, - trgm_pos_matrix_output_to_mtg1, - trgm_pos_matrix_output_to_qeo0, - trgm_pos_matrix_output_to_qeo1, - trgm_pos_matrix_output_to_qeo2, - trgm_pos_matrix_output_to_qeo3, - trgm_pos_matrix_output_to_vsc0, - trgm_pos_matrix_output_to_vsc1, -} trgm_pos_matrix_out_t; - -typedef enum { - trgm_pos_matrix_in_from_sei_pos0 = 0, - trgm_pos_matrix_in_from_sei_pos1, - trgm_pos_matrix_in_from_sei_pos2, - trgm_pos_matrix_in_from_sei_pos3, - trgm_pos_matrix_in_from_qei0, - trgm_pos_matrix_in_from_qei1, - trgm_pos_matrix_in_from_qei2, - trgm_pos_matrix_in_from_qei3, - trgm_pos_matrix_in_from_mtg0_pos0, - trgm_pos_matrix_in_from_mtg0_pos1, - trgm_pos_matrix_in_from_mtg1_pos0, - trgm_pos_matrix_in_from_mtg1_pos1, -} trgm_pos_matrix_in_t; - -#if defined(__cplusplus) -extern "C" { -#endif - -void trgm_adc_matrix_config(TRGM_Type *ptr, trgm_adc_matrix_out_t consumer, trgm_adc_matrix_in_t src, bool inv_val); - -void trgm_dac_matrix_config(TRGM_Type *ptr, trgm_dac_matrix_out_t consumer, trgm_dac_matrix_in_t src, bool inv_val); - -void trgm_pos_matrix_config(TRGM_Type *ptr, trgm_pos_matrix_out_t consumer, trgm_pos_matrix_in_t src, bool inv_val); - -#if defined(__cplusplus) -} -#endif - -#endif /* HPM_TRGM_SOC_DRV_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgmmux_src.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgmmux_src.h deleted file mode 100644 index b1bcb869db6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/hpm_trgmmux_src.h +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGMMUX_SRC_H -#define HPM_TRGMMUX_SRC_H - -/* trgm0_input mux definitions */ -#define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) -#define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) -#define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x2UL) -#define HPM_TRGM0_INPUT_SRC_ENET0_PTP3 (0x3UL) -#define HPM_TRGM0_INPUT_SRC_ESC_SYNC0 (0x4UL) -#define HPM_TRGM0_INPUT_SRC_TSN_PTP3 (0x5UL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x6UL) -#define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x7UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x8UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x9UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0xAUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0xBUL) -#define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN0 (0xCUL) -#define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN1 (0xDUL) -#define HPM_TRGM0_INPUT_SRC_PWM3_CAPIN0 (0xEUL) -#define HPM_TRGM0_INPUT_SRC_ESC_SYNC1 (0xFUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH00 (0x10UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH01 (0x11UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH02 (0x12UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH03 (0x13UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH04 (0x14UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH05 (0x15UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH06 (0x16UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH07 (0x17UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH08 (0x18UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH09 (0x19UL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH10 (0x1AUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH11 (0x1BUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH12 (0x1CUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH13 (0x1DUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH14 (0x1EUL) -#define HPM_TRGM0_INPUT_SRC_SYNT_CH15 (0x1FUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x20UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x21UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x22UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x23UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0x24UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0x25UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0x26UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0x27UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT2 (0x28UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT3 (0x29UL) -#define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT2 (0x2AUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT3 (0x2BUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT2 (0x2CUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT3 (0x2DUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT2 (0x2EUL) -#define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT3 (0x2FUL) -#define HPM_TRGM0_INPUT_SRC_CMP0_OUT (0x30UL) -#define HPM_TRGM0_INPUT_SRC_CMP1_OUT (0x31UL) -#define HPM_TRGM0_INPUT_SRC_CMP2_OUT (0x32UL) -#define HPM_TRGM0_INPUT_SRC_CMP3_OUT (0x33UL) -#define HPM_TRGM0_INPUT_SRC_CMP4_OUT (0x34UL) -#define HPM_TRGM0_INPUT_SRC_CMP5_OUT (0x35UL) -#define HPM_TRGM0_INPUT_SRC_CMP6_OUT (0x36UL) -#define HPM_TRGM0_INPUT_SRC_CMP7_OUT (0x37UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x38UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x39UL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x3AUL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x3BUL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x3CUL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x3DUL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x3EUL) -#define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x3FUL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 (0x40UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_1 (0x41UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_2 (0x42UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_3 (0x43UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_4 (0x44UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_5 (0x45UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_6 (0x46UL) -#define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_7 (0x47UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 (0x48UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_1 (0x49UL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_2 (0x4AUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_3 (0x4BUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_4 (0x4CUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_5 (0x4DUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_6 (0x4EUL) -#define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_7 (0x46UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_0 (0x50UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_1 (0x51UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_2 (0x52UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_3 (0x53UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_4 (0x54UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_5 (0x55UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_6 (0x56UL) -#define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_7 (0x57UL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_0 (0x58UL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_1 (0x59UL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_2 (0x5AUL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_3 (0x5BUL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_4 (0x5CUL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_5 (0x5DUL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_6 (0x5EUL) -#define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_7 (0x5FUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P00 (0x60UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P01 (0x61UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P02 (0x62UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P03 (0x63UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P04 (0x64UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P05 (0x65UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P06 (0x66UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P07 (0x67UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P08 (0x68UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P09 (0x69UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0x6AUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0x6BUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P12 (0x6CUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P13 (0x6DUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P14 (0x6EUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P15 (0x6FUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P16 (0x70UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P17 (0x71UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P18 (0x72UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P19 (0x73UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P20 (0x74UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P21 (0x75UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P22 (0x76UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P23 (0x77UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P24 (0x78UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P25 (0x79UL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P26 (0x7AUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P27 (0x7BUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P28 (0x7CUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P29 (0x7DUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P30 (0x7EUL) -#define HPM_TRGM0_INPUT_SRC_TRGM0_P31 (0x7FUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x80UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x81UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x82UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x83UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x84UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x85UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x86UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x87UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x88UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x89UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x8AUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x8BUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x8CUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x8DUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x8EUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x8FUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x90UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x91UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x92UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x93UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x94UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x95UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x96UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x97UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x98UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x99UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x9AUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x9BUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x9CUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x9DUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x9EUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x9FUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT32 (0xA0UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT33 (0xA1UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT34 (0xA2UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT35 (0xA3UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT36 (0xA4UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT37 (0xA5UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT38 (0xA6UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT39 (0xA7UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT40 (0xA8UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT41 (0xA9UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT42 (0xAAUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT43 (0xABUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT44 (0xACUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT45 (0xADUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT46 (0xAEUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT47 (0xAFUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT48 (0xB0UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT49 (0xB1UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT50 (0xB2UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT51 (0xAAUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT52 (0xB4UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT53 (0xB5UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT54 (0xB6UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT55 (0xB7UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT56 (0xB8UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT57 (0xB9UL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT58 (0xBAUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT59 (0xBBUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT60 (0xBCUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT61 (0xBDUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT62 (0xBEUL) -#define HPM_TRGM0_INPUT_SRC_PLB_OUT63 (0xBFUL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ0 (0xC0UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ1 (0xC1UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ2 (0xC2UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ3 (0xC3UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA0 (0xC4UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA1 (0xC5UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA2 (0xC6UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA3 (0xC7UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL0 (0xC8UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL1 (0xC9UL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL2 (0xCAUL) -#define HPM_TRGM0_INPUT_SRC_SDM1_COMPL3 (0xCBUL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ0 (0xCCUL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ1 (0xCDUL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ2 (0xCEUL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ3 (0xCFUL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL0 (0xD0UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL1 (0xD1UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL2 (0xD2UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPL3 (0xD3UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA0 (0xD4UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA1 (0xD5UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA2 (0xD6UL) -#define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA3 (0xD7UL) -#define HPM_TRGM0_INPUT_SRC_ADC0_TRGO (0xD8UL) -#define HPM_TRGM0_INPUT_SRC_ADC1_TRGO (0xD9UL) -#define HPM_TRGM0_INPUT_SRC_ADC2_TRGO (0xDAUL) -#define HPM_TRGM0_INPUT_SRC_ADC3_TRGO (0xDBUL) -#define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0 (0xDCUL) -#define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_1 (0xDDUL) -#define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_0 (0xDEUL) -#define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_1 (0xDFUL) -#define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0xE0UL) -#define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0xE1UL) -#define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0xE2UL) -#define HPM_TRGM0_INPUT_SRC_QEI2_TRGO (0xE3UL) -#define HPM_TRGM0_INPUT_SRC_QEI3_TRGO (0xE4UL) - -/* trgm0_output mux definitions */ -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x0UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x1UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x2UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x3UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x4UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x5UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x6UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x7UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO8 (0x8UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO9 (0x9UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO10 (0xAUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO11 (0xBUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO12 (0xCUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO13 (0xDUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO14 (0xEUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO15 (0xFUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO16 (0x10UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO17 (0x11UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO18 (0x12UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO19 (0x13UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO20 (0x14UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO21 (0x15UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO22 (0x16UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO23 (0x17UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO24 (0x18UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO25 (0x19UL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO26 (0x1AUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO27 (0x1BUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO28 (0x1CUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO29 (0x1DUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO30 (0x1EUL) -#define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO31 (0x1FUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC0 (0x20UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC1 (0x21UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC2 (0x22UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC3 (0x23UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC4 (0x24UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC5 (0x25UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC6 (0x26UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC7 (0x27UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC8 (0x28UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC9 (0x29UL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC10 (0x2AUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC11 (0x2BUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC12 (0x2CUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC13 (0x2DUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC14 (0x2EUL) -#define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15 (0x2FUL) -#define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) -#define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI (0x33UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x37UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x38UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x39UL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x3AUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x3BUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x3CUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x3DUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x3EUL) -#define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x3FUL) -#define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0 (0x40UL) -#define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN1 (0x41UL) -#define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN0 (0x42UL) -#define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN1 (0x43UL) -#define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN0 (0x44UL) -#define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN1 (0x45UL) -#define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN0 (0x46UL) -#define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN1 (0x47UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x48UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x49UL) -#define HPM_TRGM0_OUTPUT_SRC_QEI2_TRIG_IN (0x4AUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI3_TRIG_IN (0x4BUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x4CUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x4DUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI2_PAUSE (0x4EUL) -#define HPM_TRGM0_OUTPUT_SRC_QEI3_PAUSE (0x4FUL) -#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x50UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x51UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x52UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x53UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN0 (0x54UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN1 (0x55UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN0 (0x56UL) -#define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN1 (0x57UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x58UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x59UL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x5AUL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x5BUL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x5CUL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x5DUL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x5EUL) -#define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x5FUL) -#define HPM_TRGM0_OUTPUT_SRC_CMP0_WIN (0x60UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP1_WIN (0x61UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP2_WIN (0x62UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP3_WIN (0x63UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP4_WIN (0x64UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP5_WIN (0x65UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP6_WIN (0x66UL) -#define HPM_TRGM0_OUTPUT_SRC_CMP7_WIN (0x67UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x68UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x69UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x6AUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x6BUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x6CUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x6DUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x6EUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x6FUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x70UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x71UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x72UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x73UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN2 (0x74UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN3 (0x75UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR4_SYNCI (0x76UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN2 (0x77UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN3 (0x78UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR5_SYNCI (0x79UL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN2 (0x7AUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN3 (0x7BUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR6_SYNCI (0x7CUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN2 (0x7DUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN3 (0x7EUL) -#define HPM_TRGM0_OUTPUT_SRC_GPTMR7_SYNCI (0x7FUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x80UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x81UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x82UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x83UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x84UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x85UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x86UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x87UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x88UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x89UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x8AUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x8BUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x8CUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x8DUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x8EUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x8FUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x90UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x91UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x92UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x93UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x94UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x95UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x96UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x97UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x98UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x99UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x9AUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x9BUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x9CUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x9DUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x9EUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x9FUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_32 (0xA0UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_33 (0xA1UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_34 (0xA2UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_35 (0xA3UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_36 (0xA4UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_37 (0xA5UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_38 (0xA6UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_39 (0xA7UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_40 (0xA8UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_41 (0xA9UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_42 (0xAAUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_43 (0xABUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_44 (0xACUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_45 (0xADUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_46 (0xAEUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_47 (0xAFUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_48 (0xB0UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_49 (0xB1UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_50 (0xB2UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_51 (0xB3UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_52 (0xB4UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_53 (0xB5UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_54 (0xB6UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_55 (0xB7UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_56 (0xB8UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_57 (0xB9UL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_58 (0xBAUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_59 (0xBBUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_60 (0xBCUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_61 (0xBDUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_62 (0xBEUL) -#define HPM_TRGM0_OUTPUT_SRC_PLB_IN_63 (0xBFUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN0 (0xC0UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN1 (0xC1UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN2 (0xC2UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN3 (0xC3UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN4 (0xC4UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN5 (0xC5UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN6 (0xC6UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN7 (0xC7UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0 (0xC8UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1 (0xC9UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2 (0xCAUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN3 (0xCBUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN4 (0xCCUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN5 (0xCDUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN6 (0xCEUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN7 (0xCFUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN0 (0xD0UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN1 (0xD1UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN2 (0xD2UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN3 (0xD3UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN4 (0xD4UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN5 (0xD5UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN6 (0xD6UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN7 (0xD7UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN0 (0xD8UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN1 (0xD9UL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN2 (0xDAUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN3 (0xDBUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN4 (0xDCUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN5 (0xDDUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN6 (0xDEUL) -#define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN7 (0xDFUL) -#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP (0xE0UL) -#define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP (0xE1UL) -#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0xE2UL) -#define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0xE3UL) -#define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0xE4UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0xE5UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0xE6UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0xE7UL) -#define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0xE8UL) -#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN0 (0xE9UL) -#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN1 (0xEAUL) -#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN2 (0xEBUL) -#define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN3 (0xECUL) -#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN0 (0xEDUL) -#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN1 (0xEEUL) -#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN2 (0xEFUL) -#define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN3 (0xF0UL) -#define HPM_TRGM0_OUTPUT_SRC_ESC_TRIG_IN (0xF1UL) - -/* trgm0_filter mux definitions */ -#define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) -#define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) -#define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN0 (0x10UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN1 (0x11UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN2 (0x12UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN3 (0x13UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN4 (0x14UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN5 (0x15UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN6 (0x16UL) -#define HPM_TRGM0_FILTER_SRC_PWM2_IN7 (0x17UL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN0 (0x18UL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN1 (0x19UL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN2 (0x1AUL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN3 (0x1BUL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN4 (0x1CUL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN5 (0x1DUL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN6 (0x1EUL) -#define HPM_TRGM0_FILTER_SRC_PWM3_IN7 (0x1FUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN0 (0x20UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN1 (0x21UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN2 (0x22UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN3 (0x23UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN4 (0x24UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN5 (0x25UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN6 (0x26UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN7 (0x27UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN8 (0x28UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN9 (0x29UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN10 (0x2AUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN11 (0x2BUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN12 (0x2CUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN13 (0x2DUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN14 (0x2EUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN15 (0x2FUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN16 (0x30UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN17 (0x31UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN18 (0x32UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN19 (0x33UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN20 (0x34UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN21 (0x35UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN22 (0x36UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN23 (0x37UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN24 (0x38UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN25 (0x39UL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN26 (0x3AUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN27 (0x3BUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN28 (0x3CUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN29 (0x3DUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN30 (0x3EUL) -#define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN31 (0x3FUL) - -/* trgm0_dma mux definitions */ -#define HPM_TRGM0_DMA_SRC_PWM0_REQ0 (0x0UL) -#define HPM_TRGM0_DMA_SRC_PWM0_REQ1 (0x1UL) -#define HPM_TRGM0_DMA_SRC_PWM0_REQ2 (0x2UL) -#define HPM_TRGM0_DMA_SRC_PWM0_REQ3 (0x3UL) -#define HPM_TRGM0_DMA_SRC_PWM1_REQ0 (0x4UL) -#define HPM_TRGM0_DMA_SRC_PWM1_REQ1 (0x5UL) -#define HPM_TRGM0_DMA_SRC_PWM1_REQ2 (0x6UL) -#define HPM_TRGM0_DMA_SRC_PWM1_REQ3 (0x7UL) -#define HPM_TRGM0_DMA_SRC_PWM2_REQ0 (0x8UL) -#define HPM_TRGM0_DMA_SRC_PWM2_REQ1 (0x9UL) -#define HPM_TRGM0_DMA_SRC_PWM2_REQ2 (0xAUL) -#define HPM_TRGM0_DMA_SRC_PWM2_REQ3 (0xBUL) -#define HPM_TRGM0_DMA_SRC_PWM3_REQ0 (0xCUL) -#define HPM_TRGM0_DMA_SRC_PWM3_REQ1 (0xDUL) -#define HPM_TRGM0_DMA_SRC_PWM3_REQ2 (0xEUL) -#define HPM_TRGM0_DMA_SRC_PWM3_REQ3 (0xFUL) -#define HPM_TRGM0_DMA_SRC_QEI0_REQ (0x10UL) -#define HPM_TRGM0_DMA_SRC_QEI1_REQ (0x11UL) -#define HPM_TRGM0_DMA_SRC_QEI2_REQ (0x12UL) -#define HPM_TRGM0_DMA_SRC_QEI3_REQ (0x13UL) -#define HPM_TRGM0_DMA_SRC_SEI_REQ0 (0x14UL) -#define HPM_TRGM0_DMA_SRC_SEI_REQ1 (0x15UL) -#define HPM_TRGM0_DMA_SRC_SEI_REQ2 (0x16UL) -#define HPM_TRGM0_DMA_SRC_SEI_REQ3 (0x17UL) -#define HPM_TRGM0_DMA_SRC_TRGM0 (0x18UL) -#define HPM_TRGM0_DMA_SRC_TRGM1 (0x19UL) - - - -#endif /* HPM_TRGMMUX_SRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/soc_modules.list b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/soc_modules.list deleted file mode 100644 index 76c232bd36e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/soc_modules.list +++ /dev/null @@ -1,74 +0,0 @@ -# -# Copyright (c) 2024 HPMicro -# -# SPDX-License-Identifier: BSD-3-Clause -# - -HPMSOC_HAS_HPMSDK_MULTICORE=y -HPMSOC_HAS_HPMSDK_GPIO=y -HPMSOC_HAS_HPMSDK_PLIC=y -HPMSOC_HAS_HPMSDK_MCHTMR=y -HPMSOC_HAS_HPMSDK_PLICSW=y -HPMSOC_HAS_HPMSDK_GPTMR=y -HPMSOC_HAS_HPMSDK_UART=y -HPMSOC_HAS_HPMSDK_I2C=y -HPMSOC_HAS_HPMSDK_SPI=y -HPMSOC_HAS_HPMSDK_CRC=y -HPMSOC_HAS_HPMSDK_TSNS=y -HPMSOC_HAS_HPMSDK_MBX=y -HPMSOC_HAS_HPMSDK_EWDG=y -HPMSOC_HAS_HPMSDK_DMAMUX=y -HPMSOC_HAS_HPMSDK_DMAV2=y -HPMSOC_HAS_HPMSDK_PPI=y -HPMSOC_HAS_HPMSDK_GPIOM=y -HPMSOC_HAS_HPMSDK_LOBS=y -HPMSOC_HAS_HPMSDK_ADC16=y -HPMSOC_HAS_HPMSDK_ACMP=y -HPMSOC_HAS_HPMSDK_I2S=y -HPMSOC_HAS_HPMSDK_DAO=y -HPMSOC_HAS_HPMSDK_PDM=y -HPMSOC_HAS_HPMSDK_MCAN=y -HPMSOC_HAS_HPMSDK_PTPC=y -HPMSOC_HAS_HPMSDK_QEIV2=y -HPMSOC_HAS_HPMSDK_QEOV2=y -HPMSOC_HAS_HPMSDK_PWMV2=y -HPMSOC_HAS_HPMSDK_RDC=y -HPMSOC_HAS_HPMSDK_SDM=y -HPMSOC_HAS_HPMSDK_PLB=y -HPMSOC_HAS_HPMSDK_SYNT=y -HPMSOC_HAS_HPMSDK_SEI=y -HPMSOC_HAS_HPMSDK_TRGM=y -HPMSOC_HAS_HPMSDK_MTG=y -HPMSOC_HAS_HPMSDK_VSC=y -HPMSOC_HAS_HPMSDK_CLC=y -HPMSOC_HAS_HPMSDK_ENET=y -HPMSOC_HAS_HPMSDK_USB=y -HPMSOC_HAS_HPMSDK_TSW=y -HPMSOC_HAS_HPMSDK_ESC=y -HPMSOC_HAS_HPMSDK_FEMC=y -HPMSOC_HAS_HPMSDK_FFA=y -HPMSOC_HAS_HPMSDK_SDP=y -HPMSOC_HAS_HPMSDK_PSEC=y -HPMSOC_HAS_HPMSDK_PMON=y -HPMSOC_HAS_HPMSDK_RNG=y -HPMSOC_HAS_HPMSDK_KEYM=y -HPMSOC_HAS_HPMSDK_OTP=y -HPMSOC_HAS_HPMSDK_SYSCTL=y -HPMSOC_HAS_HPMSDK_IOC=y -HPMSOC_HAS_HPMSDK_PLLCTLV2=y -HPMSOC_HAS_HPMSDK_PPOR=y -HPMSOC_HAS_HPMSDK_PCFG=y -HPMSOC_HAS_HPMSDK_PDGO=y -HPMSOC_HAS_HPMSDK_PGPR=y -HPMSOC_HAS_HPMSDK_BACC=y -HPMSOC_HAS_HPMSDK_BPOR=y -HPMSOC_HAS_HPMSDK_BCFG=y -HPMSOC_HAS_HPMSDK_BGPR=y -HPMSOC_HAS_HPMSDK_BSEC=y -HPMSOC_HAS_HPMSDK_RTC=y -HPMSOC_HAS_HPMSDK_BKEY=y -HPMSOC_HAS_HPMSDK_BMON=y -HPMSOC_HAS_HPMSDK_TAMP=y -HPMSOC_HAS_HPMSDK_MONO=y -HPMSOC_HAS_HPMSDK_PMP=y - diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/system.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/system.c deleted file mode 100644 index 3ea422c42ea..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/system.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" - -#ifndef CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP -#define CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP 0 -#endif - -void enable_plic_feature(void) -{ - uint32_t plic_feature = 0; -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* enabled vector mode and preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_VECTORED_MODE; -#endif -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - /* enabled preemptive priority interrupt */ - plic_feature |= HPM_PLIC_FEATURE_PREEMPTIVE_PRIORITY_IRQ; -#endif - __plic_set_feature(HPM_PLIC_BASE, plic_feature); -} - -__attribute__((weak)) void system_init(void) -{ -#ifndef CONFIG_NOT_ENALBE_ACCESS_TO_CYCLE_CSR - uint32_t mcounteren = read_csr(CSR_MCOUNTEREN); - write_csr(CSR_MCOUNTEREN, mcounteren | 1); /* Enable MCYCLE */ -#endif - -#ifdef USE_S_MODE_IRQ - disable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#else - disable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - - disable_irq_from_intc(); -#ifdef USE_S_MODE_IRQ - disable_s_irq_from_intc(); -#endif - - enable_plic_feature(); - enable_irq_from_intc(); - -#ifdef USE_S_MODE_IRQ - delegate_irq(CSR_MIDELEG_SEI_MASK | CSR_MIDELEG_SSI_MASK | CSR_MIDELEG_STI_MASK); - enable_s_irq_from_intc(); -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK | CSR_MSTATUS_SIE_MASK); -#endif -#else -#if !CONFIG_DISABLE_GLOBAL_IRQ_ON_STARTUP - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif -#endif -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash.ld deleted file mode 100644 index 2ee59934e8e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash.ld +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80003000, LENGTH = _flash_size - 0x3000 - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01280000, LENGTH = 256K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_sdram_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_sdram_uf2.ld deleted file mode 100644 index 8d02144a68c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_sdram_uf2.ld +++ /dev/null @@ -1,290 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 768K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_sdram_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_sdram_xip.ld deleted file mode 100644 index ad30df10e5f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_sdram_xip.ld +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 768K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K - SDRAM (wx) : ORIGIN = 0x40000000, LENGTH = (_extram_size - 4M) - SDRAM_NONCACHEABLE (wx) : ORIGIN = 0x40000000 + (_extram_size - 4M), LENGTH = 4M - AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > SDRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > SDRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > SDRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > SDRAM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > SDRAM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > SDRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > SDRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram)) - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(SDRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(SDRAM_NONCACHEABLE) + LENGTH(SDRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_uf2.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_uf2.ld deleted file mode 100644 index a3ef735a9a7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_uf2.ld +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; -UF2_BOOTLOADER_RESERVED_LENGTH = DEFINED(_uf2_bl_length) ? _uf2_bl_length : 0x20000; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH, LENGTH = _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01280000, LENGTH = 256K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - KEEP(*(.uf2_signature)) - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)): { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_xip.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_xip.ld deleted file mode 100644 index 64576f2715f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/flash_xip.ld +++ /dev/null @@ -1,307 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - XPI0 (rx) : ORIGIN = 0x80000000, LENGTH = _flash_size - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01280000, LENGTH = 256K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k -} - -__nor_cfg_option_load_addr__ = ORIGIN(XPI0) + 0x400; -__boot_header_load_addr__ = ORIGIN(XPI0) + 0x1000; -__app_load_addr__ = ORIGIN(XPI0) + 0x3000; -__boot_header_length__ = __boot_header_end__ - __boot_header_start__; -__app_offset__ = __app_load_addr__ - __boot_header_load_addr__; - - -SECTIONS -{ - .nor_cfg_option __nor_cfg_option_load_addr__ : { - KEEP(*(.nor_cfg_option)) - } > XPI0 - - .boot_header __boot_header_load_addr__ : { - __boot_header_start__ = .; - KEEP(*(.boot_header)) - KEEP(*(.fw_info_table)) - KEEP(*(.dc_info)) - __boot_header_end__ = .; - } > XPI0 - - .start __app_load_addr__ : { - . = ALIGN(8); - KEEP(*(.start)) - } > XPI0 - - __vector_load_addr__ = ADDR(.start) + SIZEOF(.start); - .vectors ORIGIN(ILM) : AT(__vector_load_addr__) { - . = ALIGN(8); - __vector_ram_start__ = .; - KEEP(*(.vector_table)) - KEEP(*(.isr_vector)) - KEEP(*(.vector_s_table)) - KEEP(*(.isr_s_vector)) - . = ALIGN(8); - __vector_ram_end__ = .; - } > ILM - - .text (__vector_load_addr__ + SIZEOF(.vectors)) : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - . = ALIGN(8); - } > XPI0 - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > XPI0 - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > XPI0 - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - .rel : { - KEEP(*(.rel*)) - } > XPI0 - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(XPI0)) && (__last_addr__ <= (ORIGIN(XPI0) + LENGTH(XPI0)))), "****** FAILED! XPI0 has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/initfini.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/initfini.c deleted file mode 100644 index 7d2b85799c8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/initfini.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2021-2022 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include - -#ifndef USE_LIBC_INITFINI -#define USE_LIBC_INITFINI 0 -#endif - -#if USE_LIBC_INITFINI - -/* - * The _init() and _fini() will be called respectively when use __libc_init_array() - * and __libc_fnit_array() in libc.a to perform constructor and destructor handling. - * The dummy versions of these functions should be provided. - */ -void _init(void) -{ -} - -void _fini(void) -{ -} - -#else - -/* These magic symbols are provided by the linker. */ -extern void (*__preinit_array_start[])(void) __attribute__((weak)); -extern void (*__preinit_array_end[])(void) __attribute__((weak)); -extern void (*__init_array_start[])(void) __attribute__((weak)); -extern void (*__init_array_end[])(void) __attribute__((weak)); - -/* - * The __libc_init_array()/__libc_fnit_array() function is used to do global - * constructor/destructor and can NOT be compilied to generate the code coverage - * data. We have the function attribute to be 'no_profile_instrument_function' - * to prevent been instrumented for coverage analysis when GCOV=1 is applied. - */ -/* Iterate over all the init routines. */ -void __libc_init_array(void) __attribute__((no_profile_instrument_function)); -void __libc_init_array(void) -{ - uint32_t count; - uint32_t i; - - count = __preinit_array_end - __preinit_array_start; - for (i = 0; i < count; i++) { - __preinit_array_start[i](); - } - - count = __init_array_end - __init_array_start; - for (i = 0; i < count; i++) { - __init_array_start[i](); - } -} - -extern void (*__fini_array_start[])(void) __attribute__((weak)); -extern void (*__fini_array_end[])(void) __attribute__((weak)); - -/* Run all the cleanup routines. */ -void __libc_fini_array(void) __attribute__((no_profile_instrument_function)); -void __libc_fini_array(void) -{ - uint32_t count; - uint32_t i; - - count = __fini_array_end - __fini_array_start; - for (i = count; i > 0; i--) { - __fini_array_start[i - 1](); - } -} - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/ram.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/ram.ld deleted file mode 100644 index d4baa8b500f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/ram.ld +++ /dev/null @@ -1,286 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00000000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00200000, LENGTH = 256K - AXI_SRAM (wx) : ORIGIN = 0x01200000, LENGTH = 512K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01280000, LENGTH = 256K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K - AHB_SRAM (w) : ORIGIN = 0xF0200000, LENGTH = 32k -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .ahb_sram (NOLOAD) : { - KEEP(*(.ahb_sram)) - } > AHB_SRAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/ram_core1.ld b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/ram_core1.ld deleted file mode 100644 index b4599fffc74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/ram_core1.ld +++ /dev/null @@ -1,287 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -ENTRY(_start) - -STACK_SIZE = _stack_size; -HEAP_SIZE = _heap_size; - -MEMORY -{ - ILM (wx) : ORIGIN = 0x00040000, LENGTH = 256K - DLM (w) : ORIGIN = 0x00240000, LENGTH = 256K - AXI_SRAM_NONCACHEABLE (wx) : ORIGIN = 0x01280000, LENGTH = 64K - AXI_SRAM (wx) : ORIGIN = 0x012C0000, LENGTH = 176K - SHARE_RAM (w) : ORIGIN = 0x012FC000, LENGTH = 16K -} - -SECTIONS -{ - .start : { - . = ALIGN(8); - KEEP(*(.start)) - } > ILM - - .vectors : { - . = ALIGN(8); - KEEP(*(.isr_vector)) - KEEP(*(.vector_table)) - KEEP(*(.isr_s_vector)) - KEEP(*(.vector_s_table)) - . = ALIGN(8); - } > ILM - - .rel : { - KEEP(*(.rel*)) - } > ILM - - .text : { - . = ALIGN(8); - *(.text) - *(.text*) - *(.rodata) - *(.rodata*) - *(.srodata) - *(.srodata*) - - *(.hash) - *(.dyn*) - *(.gnu*) - *(.pl*) - - KEEP (*(.init)) - KEEP (*(.fini)) - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* section information for usbh class */ - . = ALIGN(8); - __usbh_class_info_start__ = .; - KEEP(*(.usbh_class_info)) - __usbh_class_info_end__ = .; - - /* RT-Thread related sections - Start */ - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - /* section information for modules */ - . = ALIGN(4); - __rtmsymtab_start = .; - KEEP(*(RTMSymTab)) - __rtmsymtab_end = .; - - /* RT-Thread related sections - end */ - - . = ALIGN(8); - } > ILM - - .eh_frame : - { - __eh_frame_start = .; - KEEP(*(.eh_frame)) - __eh_frame_end = .; - } > ILM - - .eh_frame_hdr : - { - KEEP(*(.eh_frame_hdr)) - } > ILM - __eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0; - __eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0; - - PROVIDE (__etext = .); - PROVIDE (_etext = .); - PROVIDE (etext = .); - - __data_load_addr__ = etext; - .data : AT(__data_load_addr__) { - . = ALIGN(8); - __data_start__ = .; - __global_pointer$ = . + 0x800; - *(.data) - *(.data*) - *(.sdata) - *(.sdata*) - - KEEP(*(.jcr)) - KEEP(*(.dynamic)) - KEEP(*(.got*)) - KEEP(*(.got)) - KEEP(*(.gcc_except_table)) - KEEP(*(.gcc_except_table.*)) - - . = ALIGN(8); - PROVIDE(__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE(__preinit_array_end = .); - - . = ALIGN(8); - PROVIDE(__init_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - - . = ALIGN(8); - PROVIDE(__finit_array_start = .); - KEEP(*(SORT_BY_INIT_PRIORITY(.finit_array.*))) - KEEP(*(.finit_array)) - PROVIDE(__finit_array_end = .); - - . = ALIGN(8); - KEEP(*crtbegin*.o(.ctors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) - KEEP(*(SORT(.ctors.*))) - KEEP(*(.ctors)) - - . = ALIGN(8); - KEEP(*crtbegin*.o(.dtors)) - KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - - . = ALIGN(8); - __data_end__ = .; - PROVIDE (__edata = .); - PROVIDE (_edata = .); - PROVIDE (edata = .); - } > AXI_SRAM - - __fast_load_addr__ = etext + SIZEOF(.data); - .fast : AT(__fast_load_addr__) { - . = ALIGN(8); - PROVIDE(__ramfunc_start__ = .); - *(.fast) - *(.fast.*) - . = ALIGN(8); - PROVIDE(__ramfunc_end__ = .); - } > ILM - - __tdata_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast); - .tdata : AT(__tdata_load_addr__) { - . = ALIGN(8); - PROVIDE(__tdata_start__ = .); - *(.tdata) - *(.tdata.*) - *(.gnu.linkonce.td.*) - . = ALIGN(8); - PROVIDE(__tdata_end__ = .); - } > AXI_SRAM - - .tbss (NOLOAD) : { - . = ALIGN(8); - PROVIDE(__tbss_start__ = .); - __thread_pointer$ = .; - *(.tbss) - *(.tbss.*) - *(.gnu.linkonce.tb.*) - *(.tcommon) - . = ALIGN(8); - PROVIDE(__tbss_end__ = .); - } > AXI_SRAM - - __noncacheable_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata); - .noncacheable.init : AT(__noncacheable_init_load_addr__) { - . = ALIGN(8); - __noncacheable_init_start__ = .; - KEEP(*(.noncacheable.init)) - __noncacheable_init_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - __fast_ram_init_load_addr__ = etext + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init); - .fast_ram.init : AT(__fast_ram_init_load_addr__) { - . = ALIGN(8); - __fast_ram_init_start__ = .; - KEEP(*(.fast_ram.init)) - __fast_ram_init_end__ = .; - . = ALIGN(8); - } > DLM - - .bss (NOLOAD) : { - . = ALIGN(8); - __bss_start__ = .; - *(.bss) - *(.bss*) - *(.sbss*) - *(.scommon) - *(.scommon*) - *(.dynsbss*) - *(COMMON) - . = ALIGN(8); - _end = .; - __bss_end__ = .; - } > AXI_SRAM - - .framebuffer (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.framebuffer)) - . = ALIGN(8); - } > AXI_SRAM - - .noncacheable.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.noncacheable)) - __noncacheable_bss_start__ = .; - KEEP(*(.noncacheable.bss)) - __noncacheable_bss_end__ = .; - . = ALIGN(8); - } > AXI_SRAM_NONCACHEABLE - - .sh_mem (NOLOAD) : { - KEEP(*(.sh_mem)) - } > SHARE_RAM - - .fast_ram.bss (NOLOAD) : { - . = ALIGN(8); - KEEP(*(.fast_ram)) - __fast_ram_bss_start__ = .; - KEEP(*(.fast_ram.bss)) - __fast_ram_bss_end__ = .; - . = ALIGN(8); - } > DLM - - .heap (NOLOAD) : { - . = ALIGN(8); - __heap_start__ = .; - . += HEAP_SIZE; - __heap_end__ = .; - } > DLM - - .stack (NOLOAD) : { - . = ALIGN(16); - __stack_base__ = .; - . += STACK_SIZE; - . = ALIGN(16); - PROVIDE (_stack = .); - PROVIDE (_stack_safe = .); - } > DLM - - __noncacheable_start__ = ORIGIN(AXI_SRAM_NONCACHEABLE); - __noncacheable_end__ = ORIGIN(AXI_SRAM_NONCACHEABLE) + LENGTH(AXI_SRAM_NONCACHEABLE); - __share_mem_start__ = ORIGIN(SHARE_RAM); - __share_mem_end__ = ORIGIN(SHARE_RAM) + LENGTH(SHARE_RAM); - - __fw_size__ = SIZEOF(.start) + SIZEOF(.vectors) + SIZEOF(.rel) + SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.fast) + SIZEOF(.tdata) + SIZEOF(.noncacheable.init) + SIZEOF(.fast_ram.init); - __last_addr__ = __fast_ram_init_load_addr__ + SIZEOF(.fast_ram.init); - ASSERT(((__fw_size__ <= LENGTH(ILM)) && (__last_addr__ <= (ORIGIN(ILM) + LENGTH(ILM)))), "****** FAILED! ILM has not enough space! ******") -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/start.S b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/start.S deleted file mode 100644 index eef76b0faa7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/gcc/start.S +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#include "hpm_csr_regs.h" - - .section .start, "ax" - - .global _start - .type _start,@function - -_start: - /* Initialize global pointer */ - .option push - .option norelax - la gp, __global_pointer$ - la tp, __thread_pointer$ - .option pop - - /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - /* Initialize stack pointer */ - la t0, _stack - mv sp, t0 - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* - * Initialize LMA/VMA sections. - * Relocation for any sections that need to be copied from LMA to VMA. - */ - call c_startup - -#if defined(__SES_RISCV) - /* Initialize the heap */ - la a0, __heap_start__ - la a1, __heap_end__ - sub a1, a1, a0 - la t1, __SEGGER_RTL_init_heap - jalr t1 -#endif - - /* Do global constructors */ - call __libc_init_array - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#ifdef __nds_execit - /* Initialize EXEC.IT table */ - la t0, _ITB_BASE_ - csrw uitb, t0 -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* System reset handler */ - call reset_handler - - /* Infinite loop, if returned accidentally */ -1: j 1b - - .weak exit -exit: -1: j 1b - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_sdram_uf2.icf deleted file mode 100644 index df487ec4846..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_sdram_uf2.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 16M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 768k]; -define region SHARE_RAM = mem:[from 0x012FC000 size 16k]; -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 4M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 4M size 4M]; -define region AHB_SRAM = mem:[from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_sdram_xip.icf deleted file mode 100644 index 078343094c3..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_sdram_xip.icf +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -if (isdefinedsymbol(_extram_size)) { - define symbol __size_exram__ = _extram_size; -} else { - define symbol __size_exram__ = 16M; -} - -define symbol __size_safestack__ = 256; - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x2000 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 768k]; -define region SHARE_RAM = mem:[from 0x012FC000 size 16k]; -define region SDRAM = mem:[from 0x40000000 size __size_exram__ - 4M]; -define region NONCACHEABLE_RAM = mem:[from 0x40000000 + __size_exram__ - 4M size 4M]; -define region AHB_SRAM = mem:[from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM | SDRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK, block SAFESTACK }; // Stack reserved block, Safe Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_uf2.icf deleted file mode 100644 index 9c4b0350189..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_uf2.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region XPI0 = mem:[from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size (__size_flash__ - UF2_BOOTLOADER_RESERVED_LENGTH) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = mem:[from 0x01280000 size 256k]; -define region SHARE_RAM = mem:[from 0x012FC000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of XPI0 { section .uf2_signature }; -place in XPI0 { symbol _start}; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { - section .uf2_signature - }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_xip.icf deleted file mode 100644 index f48d4f526f8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/flash_xip.icf +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -if (isdefinedsymbol(_flash_size)) { - define symbol __size_flash__ = _flash_size; -} else { - define symbol __size_flash__ = 8M; -} - -/* Regions */ -define region NOR_CFG_OPTION = mem:[ from 0x80000400 size 0x0C00 ]; -define region BOOT_HEADER = mem:[ from 0x80001000 size 0x90 ]; -define region XPI0 = mem:[from 0x80003000 size (__size_flash__ - 0x3000) ]; /* XPI0 */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = mem:[from 0x01280000 size 256k]; -define region SHARE_RAM = mem:[from 0x012FC000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; - -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start(NOR_CFG_OPTION); -define exported symbol __boot_header_load_addr__ = start(BOOT_HEADER); -define exported symbol __app_load_addr__ = start(XPI0); -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size(BOOT_HEADER); -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER { block boot_header }; -place at start of XPI0 { symbol _start }; -place in XPI0 { block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place at start of ILM { block vectors, block vectors_s }; -place in ILM { - section .fast, section .fast.*, // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/ram.icf deleted file mode 100644 index 0e014cc459e..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/ram.icf +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -define symbol __size_safestack__ = 256; - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00000000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = mem:[from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = mem:[from 0x01280000 size 256k]; -define region SHARE_RAM = mem:[from 0x012FC000 size 16k]; -define region AHB_SRAM = mem:[from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block SAFESTACK with size = __size_safestack__, alignment = 8 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block SAFESTACK, block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/ram_core1.icf deleted file mode 100644 index 04903e75297..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/ram_core1.icf +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -define exported symbol _link_file_version_2 = 1; - -define memory with size = 4G; - -/* Sizes */ -if (isdefinedsymbol(CSTACK_SIZE)) { - define symbol __size_cstack__ = CSTACK_SIZE; -} else { - define symbol __size_cstack__ = 0x4000; -} - -if (isdefinedsymbol(HEAP_SIZE)) { - define symbol __size_heap__ = HEAP_SIZE; -} else { - define symbol __size_heap__ = 0x4000; -} - -/* Regions */ -define region ILM = mem:[from 0x00040000 size 256k]; /* ILM */ -define region DLM = mem:[from 0x00240000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = mem:[from 0x01280000 size 64k]; /* AXI SRAM1 */ -define region AXI_SRAM = mem:[from 0x012C0000 size 176k]; -define region SHARE_RAM = mem:[from 0x012FC000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block HEAP with size = __size_heap__, alignment = 8 { }; -define block CSTACK with size = __size_cstack__, alignment = 16 { }; -define block RW_DATA with static base GPREL { rw data }; - -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; - -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start(NONCACHEABLE_RAM); -define exported symbol __noncacheable_end__ = end(NONCACHEABLE_RAM) + 1; -define exported symbol __share_mem_start__ = start(SHARE_RAM); -define exported symbol __share_mem_end__ = end(SHARE_RAM) + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections -initialize by copy with packing=none { section .vector_table }; -initialize by copy with packing=none { section .isr_vector }; -initialize by copy with packing=none { section .vector_s_table }; -initialize by copy with packing=none { section .isr_s_vector }; -initialize by copy with packing=auto { section .usbh_class_info }; -initialize by copy { readwrite }; - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM { - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block RW_DATA - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block HEAP }; // Heap reserved block -place at end of DLM { block CSTACK }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, - section FSymTab, - section VSymTab, - section .rti_fn*, - section RTMSymTab - }; -keep symbol __iar_cstart_init_gp; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/startup.s deleted file mode 100644 index 81175908610..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/iar/startup.s +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2023-2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "hpm_csr_regs.h" - - - - MODULE ?startup - - /* Forward declaration of sections */ - SECTION CSTACK:DATA:NOROOT(3) - SECTION SAFESTACK:DATA:NOROOT(3) - SECTION `.vector_table`:CODE:NOROOT(3) - - EXTERN _clean_up - EXTERN reset_handler - EXTERN __low_level_init - EXTERN irq_handler_trap - EXTERN __iar_static_base$$GPREL - EXTERN __iar_data_init2 - EXTERN l1c_ic_disable - EXTERN l1c_ic_enable - EXTERN l1c_dc_invalidate_all - EXTERN l1c_dc_enable - EXTERN l1c_dc_disable - // -------------------------------------------------- - - SECTION `.startup`:CODE:ROOT(2) - EXTERN __iar_program_start - PUBLIC _start - - EXTERN reset_handler -_start: -__iar_cstart_init_gp: - .option push - .option norelax - /* Initialize global pointer */ - la gp, __iar_static_base$$GPREL - .option pop - - /* reset mstatus to 0 */ - csrrw x0, mstatus, x0 - -#ifdef __riscv_flen -__iar_cstart_init_fpu: - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - EXTERN _init_ext_ram -__iar_cstart_init_ext_ram: - la t0, SFE(SAFESTACK) - mv sp, t0 - call _init_ext_ram -#endif - -__iar_cstart_init_stack: - /* Initialize Stack pointer */ - la t0, SFE(CSTACK) - mv sp, t0 - -#ifdef __nds_execit -__iar_cstart_init_uitb: - EXTERN `.exec.itable$$Base` - la a0, `.exec.itable$$Base` - csrw 0x800, a0 -#endif - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - - /* Call IAR low-levle API to initialize BSS, RW Data, RAM Function, etc */ - call __low_level_init - call __iar_data_init2 - fence.i - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - - -__iar_cstart_init_mvec: - #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - EXTERN freertos_risc_v_trap_handler - #define HANDLER_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - EXTERN ucos_risc_v_trap_handler - #define HANDLER_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - EXTERN tx_risc_v_trap_handler - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - EXTERN rtt_risc_v_trap_handler - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, x0 -#else - #define HANDLER_TRAP irq_handler_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, SFB(`.vector_table`) - csrw mtvec, t0 - - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - - /* Jump to reset handler once all settings have done */ - call reset_handler - -__iar_cstart_exit - j __iar_cstart_exit - -#include "../vectors.h" diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/reset.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/reset.c deleted file mode 100644 index e3d725a1d7a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/reset.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "hpm_common.h" -#include "hpm_soc.h" -#include "hpm_l1c_drv.h" -#include "hpm_interrupt.h" - - -extern void system_init(void); - -#ifndef MAIN_ENTRY -#define MAIN_ENTRY main -#endif -extern int MAIN_ENTRY(void); - -__attribute__((weak)) void _clean_up(void) -{ - /* clean up plic, it will help while debugging */ - disable_irq_from_intc(); - intc_m_set_threshold(0); - for (uint32_t irq = 0; irq < 128; irq++) { - intc_m_complete_irq(irq); - } - /* clear any bits left in plic enable register */ - for (uint32_t i = 0; i < 4; i++) { - *(volatile uint32_t *)(HPM_PLIC_BASE + HPM_PLIC_ENABLE_OFFSET + (i << 2)) = 0; - } -} - -__attribute__((weak)) void c_startup(void) -{ - uint32_t i, size; - extern uint8_t __bss_start__[], __bss_end__[]; - extern uint8_t __tdata_start__[], __tdata_end__[]; - extern uint8_t __data_start__[], __data_end__[]; - extern uint8_t __ramfunc_start__[], __ramfunc_end__[]; - extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[]; - extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[]; - extern uint8_t __data_load_addr__[], __tdata_load_addr__[]; - extern uint8_t __fast_load_addr__[], __noncacheable_init_load_addr__[]; - extern uint8_t __fast_ram_bss_start__[], __fast_ram_bss_end__[]; - extern uint8_t __fast_ram_init_start__[], __fast_ram_init_end__[], __fast_ram_init_load_addr__[]; - -#if defined(FLASH_XIP) || defined(FLASH_UF2) - extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[]; - size = __vector_ram_end__ - __vector_ram_start__; - for (i = 0; i < size; i++) { - *(__vector_ram_start__ + i) = *(__vector_load_addr__ + i); - } -#endif - - /* bss section */ - size = __bss_end__ - __bss_start__; - for (i = 0; i < size; i++) { - *(__bss_start__ + i) = 0; - } - - /* noncacheable bss section */ - size = __noncacheable_bss_end__ - __noncacheable_bss_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_bss_start__ + i) = 0; - } - - /* fast_ram bss section */ - size = __fast_ram_bss_end__ - __fast_ram_bss_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_bss_start__ + i) = 0; - } - - /* data section LMA: etext */ - size = __data_end__ - __data_start__; - for (i = 0; i < size; i++) { - *(__data_start__ + i) = *(__data_load_addr__ + i); - } - - /* ramfunc section LMA: etext + data length */ - size = __ramfunc_end__ - __ramfunc_start__; - for (i = 0; i < size; i++) { - *(__ramfunc_start__ + i) = *(__fast_load_addr__ + i); - } - - /* tdata section LMA: etext + data length + ramfunc length */ - size = __tdata_end__ - __tdata_start__; - for (i = 0; i < size; i++) { - *(__tdata_start__ + i) = *(__tdata_load_addr__ + i); - } - - /* noncacheable init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __noncacheable_init_end__ - __noncacheable_init_start__; - for (i = 0; i < size; i++) { - *(__noncacheable_init_start__ + i) = *(__noncacheable_init_load_addr__ + i); - } - - /* fast_ram init section LMA: etext + data length + ramfunc legnth + tdata length*/ - size = __fast_ram_init_end__ - __fast_ram_init_start__; - for (i = 0; i < size; i++) { - *(__fast_ram_init_start__ + i) = *(__fast_ram_init_load_addr__ + i); - } -} - -__attribute__((weak)) int main(void) -{ - while (1) { - ; - } -} - -__attribute__((weak)) void reset_handler(void) -{ - fencei(); - - /* Call platform specific hardware initialization */ - system_init(); - - /* Entry function */ - MAIN_ENTRY(); -} - -/* - * When compiling C++ code with static objects, the compiler inserts - * a call to __cxa_atexit() with __dso_handle as one of the arguments. - * The dummy versions of these symbols should be provided. - */ -__attribute__((weak)) void __cxa_atexit(void (*arg1)(void *), void *arg2, void *arg3) -{ - (void) arg1; - (void) arg2; - (void) arg3; -} - -#if (!defined(__SEGGER_RTL_VERSION) || defined(__riscv_xandes)) && !defined(__ICCRISCV__) -void *__dso_handle = (void *) &__dso_handle; -#endif - -__attribute__((weak)) void _init(void) -{ -} - - -#ifdef __ICCRISCV__ -int __low_level_init(void) -{ -#ifdef IAR_MANUAL_COPY /* Enable this code snippet if the .isr_vector and .vector_table need to be copied to RAM manually */ -#pragma section = ".isr_vector" -#pragma section = ".isr_vector_init" -#pragma section = ".vector_table" -#pragma section = ".vector_table_init" - /* Initialize section .isr_vector, section .vector_table */ - uint8_t *__isr_vector_ram_start = __section_begin(".isr_vector"); - uint32_t __isr_vector_ram_size = __section_size(".isr_vector"); - uint8_t *__isr_vector_rom_start = __section_begin(".isr_vector_init"); - - for (uint32_t i = 0; i < __isr_vector_ram_size; i++) { - __isr_vector_ram_start[i] = __isr_vector_rom_start[i]; - } - - uint8_t *__vector_table_ram_start = __section_begin(".vector_table"); - uint32_t __vector_table_ram_size = __section_size(".vector_table"); - uint8_t *__vector_rom_start = __section_begin(".vector_table_init"); - - for (uint32_t i = 0; i < __vector_table_ram_size; i++) { - __vector_table_ram_start[i] = __vector_rom_start[i]; - } -#endif - - return 1; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash.icf deleted file mode 100644 index fb079c4fabe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash.icf +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region XPI0 = [from 0x80000000 + 0x3000, size _flash_size - 0x3000]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { - section .fast, section .fast.* // "ramfunc" section - }; -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_sdram_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_sdram_uf2.icf deleted file mode 100644 index 02aa4c059b1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_sdram_uf2.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 768k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_sdram_xip.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_sdram_xip.icf deleted file mode 100644 index 93b4518ff3a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_sdram_xip.icf +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region NOR_CFG_OPTION = [ from 0x80000400 size 0x1000 ]; -define region BOOT_HEADER = [ from 0x80001000 size 0x2000 ]; -define region XPI0 = [from 0x80003000 size _flash_size - 0x3000 ]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 768k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; -define region SDRAM = [from 0x40000000 size _extram_size - 4M]; -define region NONCACHEABLE_RAM = [from 0x40000000 + _extram_size - 4M size 4M]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block boot_header with fixed order { section .boot_header, section .fw_info_table, section .dc_info }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __nor_cfg_option_load_addr__ = start of region NOR_CFG_OPTION; -define exported symbol __boot_header_load_addr__ = start of region BOOT_HEADER; -define exported symbol __app_load_addr__ = start of region XPI0; -define exported symbol __app_offset__ = __app_load_addr__ - __boot_header_load_addr__; -define exported symbol __boot_header_length__ = size of block boot_header; -define exported symbol __fw_size__ = 0x1000; - -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place in NOR_CFG_OPTION { section .nor_cfg_option }; -place in BOOT_HEADER with fixed order { block boot_header }; -place at start of XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in SDRAM { block cherryusb_usbh_class_info }; -place in SDRAM { block framebuffer }; -place in AXI_SRAM then SDRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in SDRAM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .nor_cfg_option, section .boot_header, section .fw_info_table, section .dc_info }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_uf2.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_uf2.icf deleted file mode 100644 index 6921e2b7192..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/flash_uf2.icf +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2022-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; -define symbol UF2_BOOTLOADER_RESERVED_LENGTH = 0x20000; - -/* Regions */ -define region XPI0 = [from 0x80000000 + UF2_BOOTLOADER_RESERVED_LENGTH size _flash_size - UF2_BOOTLOADER_RESERVED_LENGTH]; /* XPI0 */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol _stack = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. -initialize by copy { block vectors, block vectors_s }; -initialize by copy { block cherryusb_usbh_class_info }; - -/* Placement */ -place at start of XPI0 with fixed order { section .uf2_signature }; -place in XPI0 with fixed order { symbol _start }; -place at start of ILM with fixed order { block vectors, block vectors_s }; -place in XPI0 with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .uf2_signature }; -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/ram.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/ram.icf deleted file mode 100644 index b951b211366..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/ram.icf +++ /dev/null @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2024 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00000000 size 256k]; /* ILM */ -define region DLM = [from 0x00200000 size 256k]; /* DLM */ -define region AXI_SRAM = [from 0x01200000 size 512k]; -define region NONCACHEABLE_RAM = [from 0x01280000 size 256k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; -define region AHB_SRAM = [from 0xF0200000 size 32k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; -define block cherryusb_usbh_class_info with alignment = 8 { section .usbh_class_info }; -define block framebuffer with alignment = 8 { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in AHB_SRAM { section .ahb_sram}; // AHB SRAM memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/ram_core1.icf b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/ram_core1.icf deleted file mode 100644 index 0d918a1ccc4..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/ram_core1.icf +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * SPDX-License-Identifier: BSD-3-Clause - */ - - -define memory with size = 4G; - -/* Regions */ -define region ILM = [from 0x00040000 size 256k]; /* ILM */ -define region DLM = [from 0x00240000 size 256k]; /* DLM */ -define region NONCACHEABLE_RAM = [from 0x01280000 size 64k]; /* AXI SRAM1 */ -define region AXI_SRAM = [from 0x012C0000 size 176k]; -define region SHARE_RAM = [from 0x012FC000 size 16k]; - -/* Blocks */ -define block vectors with fixed order { section .vector_table, section .isr_vector }; -define block vectors_s with fixed order { section .vector_s_table, section .isr_s_vector }; -define block ctors { section .ctors, section .ctors.*, block with alphabetical order { init_array } }; -define block dtors { section .dtors, section .dtors.*, block with reverse alphabetical order { fini_array } }; -define block eh_frame { section .eh_frame, section .eh_frame.* }; -define block tbss { section .tbss, section .tbss.* }; -define block tdata { section .tdata, section .tdata.* }; -define block tls with fixed order { block tbss, block tdata }; -define block tdata_load { copy of block tdata }; -define block cherryusb_usbh_class_info { section .usbh_class_info }; -define block framebuffer { section .framebuffer }; -define block rtthread_FSymTab { section FSymTab }; -define block rtthread_VSymTab { section VSymTab }; -define block rtthread_rti_fn with alphabetical order { section .rti_fn* }; -define block rtthread_RTMSymTab { section RTMSymTab }; -define block heap with size = __HEAPSIZE__, alignment = 8, /* fill =0x00, */ readwrite access { }; -define block stack with size = __STACKSIZE__, alignment = 16, /* fill =0xCD, */ readwrite access { }; - -/* Symbols */ -define exported symbol __noncacheable_start__ = start of region NONCACHEABLE_RAM; -define exported symbol __noncacheable_end__ = end of region NONCACHEABLE_RAM + 1; -define exported symbol __share_mem_start__ = start of region SHARE_RAM; -define exported symbol __share_mem_end__ = end of region SHARE_RAM + 1; - -define exported symbol _stack = end of block stack + 1; -define exported symbol _stack_safe = end of block stack + 1; -define exported symbol __usbh_class_info_start__ = start of block cherryusb_usbh_class_info; -define exported symbol __usbh_class_info_end__ = end of block cherryusb_usbh_class_info + 1; - -define exported symbol __fsymtab_start = start of block rtthread_FSymTab; -define exported symbol __fsymtab_end = end of block rtthread_FSymTab + 1; - -define exported symbol __vsymtab_start = start of block rtthread_VSymTab; -define exported symbol __vsymtab_end = end of block rtthread_VSymTab + 1; - -define exported symbol __rt_init_start = start of block rtthread_rti_fn; -define exported symbol __rt_init_end = end of block rtthread_rti_fn + 1; - -define exported symbol __rtmsymtab_start = start of block rtthread_RTMSymTab; -define exported symbol __rtmsymtab_end = end of block rtthread_RTMSymTab + 1; - -/* Initialization */ -do not initialize { section .noncacheable, section .fast_ram }; -do not initialize { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* }; -do not initialize { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* }; // Legacy sections, kept for backwards compatibility -do not initialize { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* }; // Legacy sections, used by some SDKs/HALs - -initialize by copy with packing=auto { section .noncacheable.init, section .fast_ram.init }; -initialize by copy with packing=none { section .data, section .data.*, section .*.data, section .*.data.* }; // Static data sections -initialize by copy with packing=auto { section .sdata, section .sdata.* }; -initialize by copy with packing=auto { section .fast, section .fast.*, section .*.fast, section .*.fast.* }; // "RAM Code" sections - -initialize by calling __SEGGER_init_heap { block heap }; // Init the heap if there is one -initialize by calling __SEGGER_init_ctors { block ctors }; // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap. - -/* Placement */ -place at start of ILM { symbol _start }; -place in ILM { block vectors, block vectors_s }; // Vector table section -place in ILM { section .fast, section .fast.* }; // "ramfunc" section -place in ILM with minimum size order { - block tdata_load, // Thread-local-storage load image - block ctors, // Constructors block - block dtors, // Destructors block - block eh_frame, // Exception frames placed directly into flash overriding default placement (sections writable) - block rtthread_FSymTab, - block rtthread_VSymTab, - block rtthread_rti_fn, - block rtthread_RTMSymTab, - readonly, // Catch-all for readonly data (e.g. .rodata, .srodata) - readexec // Catch-all for (readonly) executable code (e.g. .text) - }; - -// -// The GNU compiler creates these exception-related sections as writeable. -// Override the section header flag and make them readonly so they can be -// placed into flash. -// -define access readonly { section .gcc_except_table, section .gcc_except_table.* }; -define access readonly { section .eh_frame, section .eh_frame.* }; -define access readonly { section .sdata.DW.* }; - -place in AXI_SRAM { block cherryusb_usbh_class_info }; -place in AXI_SRAM { block framebuffer }; -place in AXI_SRAM { - block tls, // Thread-local-storage block - readwrite, // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit) - zeroinit // Catch-all for zero-initialized data sections (e.g. .bss) - }; - -place in NONCACHEABLE_RAM { section .noncacheable, section .noncacheable.init, section .noncacheable.bss }; // Noncacheable -place in SHARE_RAM { section .sh_mem}; // Share memory -place in DLM { section .fast_ram.init, section .fast_ram, section .fast_ram.bss}; // Fast access memory -place in DLM { block heap }; // Heap reserved block -place at end of DLM { block stack }; // Stack reserved block - -/* Keep */ -keep { section .usbh_class_info, section FSymTab, section VSymTab, section .rti_fn*, section RTMSymTab }; diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/startup.s b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/startup.s deleted file mode 100644 index 8a7036e137d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/segger/startup.s +++ /dev/null @@ -1,419 +0,0 @@ -/********************************************************************* -* SEGGER Microcontroller GmbH * -* The Embedded Experts * -********************************************************************** -* * -* (c) 2014 - 2021 SEGGER Microcontroller GmbH * -* * -* www.segger.com Support: support@segger.com * -* * -********************************************************************** -* * -* All rights reserved. * -* * -* Redistribution and use in source and binary forms, with or * -* without modification, are permitted provided that the following * -* condition is met: * -* * -* - Redistributions of source code must retain the above copyright * -* notice, this condition and the following disclaimer. * -* * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND * -* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, * -* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * -* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * -* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR * -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT * -* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * -* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * -* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE * -* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH * -* DAMAGE. * -* * -********************************************************************** - --------------------------- END-OF-HEADER ----------------------------- - -File : SEGGER_RISCV_crt0.s -Purpose : Generic runtime init startup code for RISC-V CPUs. - Designed to work with the SEGGER linker to produce - smallest possible executables. - - This file does not normally require any customization. - -Additional information: - Preprocessor Definitions - FULL_LIBRARY - If defined then - - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs(). - - the exit symbol is defined and executes on return from main. - - the exit symbol calls destructors, atexit functions and then - calls SEGGER_SEMIHOST_Exit(). - - If not defined then - - argc and argv are not valid (main is assumed to not take parameters) - - the exit symbol is defined, executes on return from main and - halts in a loop. -*/ - -#include "hpm_csr_regs.h" - -/********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef APP_ENTRY_POINT - #define APP_ENTRY_POINT reset_handler -#endif - -#ifndef ARGSSPACE - #define ARGSSPACE 128 -#endif - -/********************************************************************* -* -* Macros -* -********************************************************************** -*/ -// -// Declare a label as function symbol (without switching sections) -// -.macro MARK_FUNC Name - .global \Name - .type \Name, function -\Name: -.endm - -// -// Declare a regular function. -// Functions from the startup are placed in the init section. -// -.macro START_FUNC Name - .section .init.\Name, "ax" - .global \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Declare a weak function -// -.macro WEAK_FUNC Name - .section .init.\Name, "ax", %progbits - .global \Name - .weak \Name -#if __riscv_compressed - .balign 2 -#else - .balign 4 -#endif - .type \Name, function -\Name: -.endm - -// -// Mark the end of a function and calculate its size -// -.macro END_FUNC name - .size \name,.-\name -.endm - -/********************************************************************* -* -* Externals -* -********************************************************************** -*/ - .extern APP_ENTRY_POINT // typically main - -/********************************************************************* -* -* Global functions -* -********************************************************************** -*/ -/********************************************************************* -* -* _start -* -* Function description -* Entry point for the startup code. -* Usually called by the reset handler. -* Performs all initialisation, based on the entries in the -* linker-generated init table, then calls main(). -* It is device independent, so there should not be any need for an -* end-user to modify it. -* -* Additional information -* At this point, the stack pointer should already have been -* initialized -* - by hardware (such as on Cortex-M), -* - by the device-specific reset handler, -* - or by the debugger (such as for RAM Code). -*/ -#undef L -#define L(label) .L_start_##label - -START_FUNC _start - .option push - .option norelax - lui gp, %hi(__global_pointer$) - addi gp, gp, %lo(__global_pointer$) - lui tp, %hi(__thread_pointer$) - addi tp, tp, %lo(__thread_pointer$) - .option pop - - csrw mstatus, zero - csrw mcause, zero - -#ifdef __riscv_flen - /* Enable FPU */ - li t0, CSR_MSTATUS_FS_MASK - csrrs t0, mstatus, t0 - - /* Initialize FCSR */ - fscsr zero -#endif - -#ifdef INIT_EXT_RAM_FOR_DATA - la t0, _stack_safe - mv sp, t0 - call _init_ext_ram -#endif - - lui t0, %hi(__stack_end__) - addi sp, t0, %lo(__stack_end__) - -#ifdef CONFIG_NOT_ENABLE_ICACHE - call l1c_ic_disable -#else - call l1c_ic_enable -#endif -#ifdef CONFIG_NOT_ENABLE_DCACHE - call l1c_dc_invalidate_all - call l1c_dc_disable -#else - call l1c_dc_enable - call l1c_dc_invalidate_all -#endif - -#ifndef __NO_SYSTEM_INIT - // - // Call _init - // - call _init -#endif - // - // Call linker init functions which in turn performs the following: - // * Perform segment init - // * Perform heap init (if used) - // * Call constructors of global Objects (if any exist) - // - la s0, __SEGGER_init_table__ // Set table pointer to start of initialization table -L(RunInit): - lw a0, (s0) // Get next initialization function from table - add s0, s0, 4 // Increment table pointer to point to function arguments - jalr a0 // Call initialization function - j L(RunInit) - // -MARK_FUNC __SEGGER_init_done - // - // Time to call main(), the application entry point. - // - -#ifndef NO_CLEANUP_AT_START - /* clean up */ - call _clean_up -#endif - -#if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS - #define HANDLER_TRAP freertos_risc_v_trap_handler - #define HANDLER_S_TRAP freertos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_UCOS_III) && CONFIG_UCOS_III - #define HANDLER_TRAP ucos_risc_v_trap_handler - #define HANDLER_S_TRAP ucos_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#elif defined(CONFIG_THREADX) && CONFIG_THREADX - #define HANDLER_TRAP tx_risc_v_trap_handler - #define HANDLER_S_TRAP tx_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 - -#elif defined(CONFIG_RTTHREAD) && CONFIG_RTTHREAD - #define HANDLER_TRAP rtt_risc_v_trap_handler - #define HANDLER_S_TRAP rtt_risc_v_trap_handler - - /* Use mscratch to store isr level */ - csrw mscratch, 0 -#else - #define HANDLER_TRAP irq_handler_trap - #define HANDLER_S_TRAP irq_handler_s_trap -#endif - -#if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0) - /* Initial machine trap-vector Base */ - la t0, __vector_table - csrw mtvec, t0 - -#if defined (USE_S_MODE_IRQ) - la t0, __vector_s_table - csrw stvec, t0 -#endif - /* Enable vectored external PLIC interrupt */ - csrsi CSR_MMISC_CTL, 2 -#else - /* Initial machine trap-vector Base */ - la t0, HANDLER_TRAP - csrw mtvec, t0 -#if defined (USE_S_MODE_IRQ) - la t0, HANDLER_S_TRAP - csrw stvec, t0 -#endif - - /* Disable vectored external PLIC interrupt */ - csrci CSR_MMISC_CTL, 2 -#endif - -__startup_complete: -MARK_FUNC start -#ifndef FULL_LIBRARY - // - // In a real embedded application ("Free-standing environment"), - // main() does not get any arguments, - // which means it is not necessary to init a0 and a1. - // - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - // - // end of _start - // Fall-through to exit if main ever returns. - // -MARK_FUNC exit - // - // In a free-standing environment, if returned from application: - // Loop forever. - // - j . - .size exit,.-exit -#else - // - // In a hosted environment, - // we need to load a0 and a1 with argc and argv, in order to handle - // the command line arguments. - // This is required for some programs running under control of a - // debugger, such as automated tests. - // - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args - - call APP_ENTRY_POINT // Call to application entry point (usually main()) - call exit // Call exit function - j . // If we unexpectedly return from exit, hang. -END_FUNC _start -#endif - -#ifdef FULL_LIBRARY - li a0, ARGSSPACE - la a1, args - call debug_getargs - li a0, ARGSSPACE - la a1, args -#else - li a0, 0 - li a1, 0 -#endif - - call APP_ENTRY_POINT - tail exit - -END_FUNC _start - - // -#ifdef FULL_LIBRARY -/********************************************************************* -* -* exit -* -* Function description -* Exit of the system. -* Called on return from application entry point or explicit call -* to exit. -* -* Additional information -* In a hosted environment exit gracefully, by -* saving the return value, -* calling destructurs of global objects, -* calling registered atexit functions, -* and notifying the host/debugger. -*/ -#undef L -#define L(label) .L_exit_##label - -WEAK_FUNC exit - mv s1, a0 // Save the exit parameter/return result - // - // Call destructors - // - la s0, __dtors_start__ -L(Loop): - la t0, __dtors_end__ - beq s0, t0, L(End) - lw t1, 0(s0) - addi s0, s0, 4 - jalr t1 - j L(Loop) -L(End): - // - // Call atexit functions - // - call _execute_at_exit_fns - // - // Call debug_exit with return result/exit parameter - // - mv a0, s1 - call debug_exit - // - // If execution is not terminated, loop forever - // -L(ExitLoop): - j L(ExitLoop) // Loop forever. -END_FUNC exit -#endif - -#ifdef FULL_LIBRARY - .bss -args: - .space ARGSSPACE - .size args, .-args - .type args, %object -#endif - - .section .isr_vector, "ax" - .weak nmi_handler -nmi_handler: -1: j 1b - -#include "../vectors.h" - -/*************************** End of file ****************************/ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/trap.c b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/trap.c deleted file mode 100644 index 4c35ccd9750..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/trap.c +++ /dev/null @@ -1,282 +0,0 @@ -/* - * Copyright (c) 2021-2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" -#include "hpm_soc.h" - -#ifdef __ICCRISCV__ -#pragma language = extended -#endif - -/********************** MCAUSE exception types **************************************/ -#define MCAUSE_INSTR_ADDR_MISALIGNED (0U) /* !< Instruction Address misaligned */ -#define MCAUSE_INSTR_ACCESS_FAULT (1U) /* !< Instruction access fault */ -#define MCAUSE_ILLEGAL_INSTR (2U) /* !< Illegal instruction */ -#define MCAUSE_BREAKPOINT (3U) /* !< Breakpoint */ -#define MCAUSE_LOAD_ADDR_MISALIGNED (4U) /* !< Load address misaligned */ -#define MCAUSE_LOAD_ACCESS_FAULT (5U) /* !< Load access fault */ -#define MCAUSE_STORE_AMO_ADDR_MISALIGNED (6U) /* !< Store/AMO address misaligned */ -#define MCAUSE_STORE_AMO_ACCESS_FAULT (7U) /* !< Store/AMO access fault */ -#define MCAUSE_ECALL_FROM_USER_MODE (8U) /* !< Environment call from User mode */ -#define MCAUSE_ECALL_FROM_SUPERVISOR_MODE (9U) /* !< Environment call from Supervisor mode */ -#define MCAUSE_ECALL_FROM_MACHINE_MODE (11U) /* !< Environment call from machine mode */ -#define MCAUSE_INSTR_PAGE_FAULT (12U) /* !< Instruction page fault */ -#define MCAUSE_LOAD_PAGE_FAULT (13) /* !< Load page fault */ -#define MCAUSE_STORE_AMO_PAGE_FAULT (15U) /* !< Store/AMO page fault */ - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -__attribute__((weak)) void mchtmr_isr(void) -{ -} - -__attribute__((weak)) void swi_isr(void) -{ -} - -__attribute__((weak)) void syscall_handler(long n, long a0, long a1, long a2, long a3) -{ - (void) n; - (void) a0; - (void) a1; - (void) a2; - (void) a3; -} - -__attribute__((weak)) long exception_handler(long cause, long epc) -{ - switch (cause) { - case MCAUSE_INSTR_ADDR_MISALIGNED: - break; - case MCAUSE_INSTR_ACCESS_FAULT: - break; - case MCAUSE_ILLEGAL_INSTR: - break; - case MCAUSE_BREAKPOINT: - break; - case MCAUSE_LOAD_ADDR_MISALIGNED: - break; - case MCAUSE_LOAD_ACCESS_FAULT: - break; - case MCAUSE_STORE_AMO_ADDR_MISALIGNED: - break; - case MCAUSE_STORE_AMO_ACCESS_FAULT: - break; - case MCAUSE_ECALL_FROM_USER_MODE: - break; - case MCAUSE_ECALL_FROM_SUPERVISOR_MODE: - break; - case MCAUSE_ECALL_FROM_MACHINE_MODE: - break; - case MCAUSE_INSTR_PAGE_FAULT: - break; - case MCAUSE_LOAD_PAGE_FAULT: - break; - case MCAUSE_STORE_AMO_PAGE_FAULT: - break; - default: - break; - } - /* Unhandled Trap */ - return epc; -} - -__attribute__((weak)) long exception_s_handler(long cause, long epc) -{ - (void) cause; - return epc; -} - -__attribute__((weak)) void swi_s_isr(void) -{ -} - -__attribute__((weak)) void mchtmr_s_isr(void) -{ -} - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) && !defined(CONFIG_RTTHREAD) -HPM_ATTR_MACHINE_INTERRUPT void irq_handler_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_trap(void) __attribute__ ((section(".isr_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_table[]; -HPM_ATTR_MACHINE_INTERRUPT -#endif -void irq_handler_trap(void) -{ - long mcause = read_csr(CSR_MCAUSE); - long mepc = read_csr(CSR_MEPC); - long mstatus = read_csr(CSR_MSTATUS); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - long mxstatus = read_csr(CSR_MXSTATUS); -#endif -#ifdef __riscv_dsp - int ucode = read_csr(CSR_UCODE); -#endif -#ifdef __riscv_flen - int fcsr = read_fcsr(); -#endif - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : : "t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : : "a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_TIMER)) { - /* Machine timer interrupt */ - mchtmr_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE); - if (irq_index) { - /* Workaround: irq number returned by __plic_claim_irq might be 0, which is caused by plic. So skip invalid irq_index as a workaround */ -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_global_irq(CSR_MSTATUS_MIE_MASK); -#endif - ((isr_func_t)__vector_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_M_MODE, irq_index); - } - - } -#endif - - else if ((mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == IRQ_M_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_isr(); - intc_m_complete_swi(); - } else if (!(mcause & CSR_MCAUSE_INTERRUPT_MASK) && ((mcause & CSR_MCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_MACHINE_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : : "r"(syscall_handler) : "a4" - ); - mepc += 4; - } else { - mepc = exception_handler(mcause, mepc); - } - - /* Restore CSR */ - write_csr(CSR_MSTATUS, mstatus); - write_csr(CSR_MEPC, mepc); -#if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH - write_csr(CSR_MXSTATUS, mxstatus); -#endif -#ifdef __riscv_dsp - write_csr(CSR_UCODE, ucode); -#endif -#ifdef __riscv_flen - write_fcsr(fcsr); -#endif -} - - -#if !defined(CONFIG_FREERTOS) && !defined(CONFIG_UCOS_III) && !defined(CONFIG_THREADX) -HPM_ATTR_SUPERVISOR_INTERRUPT void irq_handler_s_trap(void); -#define IRQ_HANDLER_TRAP_AS_ISR 1 -#else -void irq_handler_s_trap(void) __attribute__ ((section(".isr_s_vector"))); -#endif - -#if defined(__ICCRISCV__) && (IRQ_HANDLER_TRAP_AS_ISR == 1) -extern int __vector_s_table[]; -HPM_ATTR_SUPERVISOR_INTERRUPT -#endif -void irq_handler_s_trap(void) -{ - long scause = read_csr(CSR_SCAUSE); - long sepc = read_csr(CSR_SEPC); - long sstatus = read_csr(CSR_SSTATUS); - - /* clobbers list for ecall */ -#ifdef __riscv_32e - __asm volatile("" : : : "t0", "a0", "a1", "a2", "a3"); -#else - __asm volatile("" : : : "a7", "a0", "a1", "a2", "a3"); -#endif - - /* Do your trap handling */ - if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_TIMER)) { - /* Machine timer interrupt */ - mchtmr_s_isr(); - } -#ifdef USE_NONVECTOR_MODE - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_EXT)) { - - typedef void(*isr_func_t)(void); - - /* Machine-level interrupt from PLIC */ - uint32_t irq_index = __plic_claim_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE); -#if !defined(DISABLE_IRQ_PREEMPTIVE) || (DISABLE_IRQ_PREEMPTIVE == 0) - enable_s_global_irq(CSR_SSTATUS_SIE_MASK); -#endif - ((isr_func_t)__vector_s_table[irq_index])(); - __plic_complete_irq(HPM_PLIC_BASE, HPM_PLIC_TARGET_S_MODE, irq_index); - - } -#endif - - else if ((scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == IRQ_S_SOFT)) { - /* Machine SWI interrupt */ - intc_m_claim_swi(); - swi_s_isr(); - intc_s_complete_swi(); - } else if (!(scause & CSR_SCAUSE_INTERRUPT_MASK) && ((scause & CSR_SCAUSE_EXCEPTION_CODE_MASK) == MCAUSE_ECALL_FROM_SUPERVISOR_MODE)) { - /* Machine Syscal call */ - __asm volatile( - "mv a4, a3\n" - "mv a3, a2\n" - "mv a2, a1\n" - "mv a1, a0\n" - #ifdef __riscv_32e - "mv a0, t0\n" - #else - "mv a0, a7\n" - #endif - "jalr %0\n" - : : "r"(syscall_handler) : "a4" - ); - sepc += 4; - } else { - sepc = exception_s_handler(scause, sepc); - } - - /* Restore CSR */ - write_csr(CSR_SSTATUS, sstatus); - write_csr(CSR_SEPC, sepc); -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/vectors.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/vectors.h deleted file mode 100644 index 97335da6f23..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/HPM6E80/toolchains/vectors.h +++ /dev/null @@ -1,1089 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_HANDLER macro - dc32 default_isr_\1 - endm - -IRQ_DEFAULT_HANDLER macro - PUBWEAK default_isr_\1 -default_isr_\1 - j default_irq_handler - endm - - SECTION `.isr_vector`:CODE:ROOT(10) - PUBWEAK default_irq_handler -default_irq_handler - j default_irq_handler - IRQ_DEFAULT_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_DEFAULT_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_DEFAULT_HANDLER 7 /* GPIO0_V IRQ handler */ - IRQ_DEFAULT_HANDLER 8 /* GPIO0_W IRQ handler */ - IRQ_DEFAULT_HANDLER 9 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_HANDLER 10 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 11 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 12 /* GPIO1_A IRQ handler */ - IRQ_DEFAULT_HANDLER 13 /* GPIO1_B IRQ handler */ - IRQ_DEFAULT_HANDLER 14 /* GPIO1_C IRQ handler */ - IRQ_DEFAULT_HANDLER 15 /* GPIO1_D IRQ handler */ - IRQ_DEFAULT_HANDLER 16 /* GPIO1_E IRQ handler */ - IRQ_DEFAULT_HANDLER 17 /* GPIO1_F IRQ handler */ - IRQ_DEFAULT_HANDLER 18 /* GPIO1_V IRQ handler */ - IRQ_DEFAULT_HANDLER 19 /* GPIO1_W IRQ handler */ - IRQ_DEFAULT_HANDLER 20 /* GPIO1_X IRQ handler */ - IRQ_DEFAULT_HANDLER 21 /* GPIO1_Y IRQ handler */ - IRQ_DEFAULT_HANDLER 22 /* GPIO1_Z IRQ handler */ - IRQ_DEFAULT_HANDLER 23 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 24 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_HANDLER 25 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_HANDLER 26 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_HANDLER 27 /* GPTMR4 IRQ handler */ - IRQ_DEFAULT_HANDLER 28 /* GPTMR5 IRQ handler */ - IRQ_DEFAULT_HANDLER 29 /* GPTMR6 IRQ handler */ - IRQ_DEFAULT_HANDLER 30 /* GPTMR7 IRQ handler */ - IRQ_DEFAULT_HANDLER 31 /* UART0 IRQ handler */ - IRQ_DEFAULT_HANDLER 32 /* UART1 IRQ handler */ - IRQ_DEFAULT_HANDLER 33 /* UART2 IRQ handler */ - IRQ_DEFAULT_HANDLER 34 /* UART3 IRQ handler */ - IRQ_DEFAULT_HANDLER 35 /* UART4 IRQ handler */ - IRQ_DEFAULT_HANDLER 36 /* UART5 IRQ handler */ - IRQ_DEFAULT_HANDLER 37 /* UART6 IRQ handler */ - IRQ_DEFAULT_HANDLER 38 /* UART7 IRQ handler */ - IRQ_DEFAULT_HANDLER 39 /* I2C0 IRQ handler */ - IRQ_DEFAULT_HANDLER 40 /* I2C1 IRQ handler */ - IRQ_DEFAULT_HANDLER 41 /* I2C2 IRQ handler */ - IRQ_DEFAULT_HANDLER 42 /* I2C3 IRQ handler */ - IRQ_DEFAULT_HANDLER 43 /* SPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 44 /* SPI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 45 /* SPI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 46 /* SPI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 47 /* TSNS IRQ handler */ - IRQ_DEFAULT_HANDLER 48 /* MBX0A IRQ handler */ - IRQ_DEFAULT_HANDLER 49 /* MBX0B IRQ handler */ - IRQ_DEFAULT_HANDLER 50 /* MBX1A IRQ handler */ - IRQ_DEFAULT_HANDLER 51 /* MBX1B IRQ handler */ - IRQ_DEFAULT_HANDLER 52 /* EWDG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 53 /* EWDG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 54 /* EWDG2 IRQ handler */ - IRQ_DEFAULT_HANDLER 55 /* EWDG3 IRQ handler */ - IRQ_DEFAULT_HANDLER 56 /* HDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 57 /* LOBS IRQ handler */ - IRQ_DEFAULT_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 60 /* ADC2 IRQ handler */ - IRQ_DEFAULT_HANDLER 61 /* ADC3 IRQ handler */ - IRQ_DEFAULT_HANDLER 62 /* ACMP0[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 63 /* ACMP0[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 64 /* ACMP1[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 65 /* ACMP1[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 66 /* ACMP2[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 67 /* ACMP2[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 68 /* ACMP3[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 69 /* ACMP3[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 70 /* I2S0 IRQ handler */ - IRQ_DEFAULT_HANDLER 71 /* I2S1 IRQ handler */ - IRQ_DEFAULT_HANDLER 72 /* DAO IRQ handler */ - IRQ_DEFAULT_HANDLER 73 /* PDM IRQ handler */ - IRQ_DEFAULT_HANDLER 74 /* UART8 IRQ handler */ - IRQ_DEFAULT_HANDLER 75 /* UART9 IRQ handler */ - IRQ_DEFAULT_HANDLER 76 /* UART10 IRQ handler */ - IRQ_DEFAULT_HANDLER 77 /* UART11 IRQ handler */ - IRQ_DEFAULT_HANDLER 78 /* UART12 IRQ handler */ - IRQ_DEFAULT_HANDLER 79 /* UART13 IRQ handler */ - IRQ_DEFAULT_HANDLER 80 /* UART14 IRQ handler */ - IRQ_DEFAULT_HANDLER 81 /* UART15 IRQ handler */ - IRQ_DEFAULT_HANDLER 82 /* I2C4 IRQ handler */ - IRQ_DEFAULT_HANDLER 83 /* I2C5 IRQ handler */ - IRQ_DEFAULT_HANDLER 84 /* I2C6 IRQ handler */ - IRQ_DEFAULT_HANDLER 85 /* I2C7 IRQ handler */ - IRQ_DEFAULT_HANDLER 86 /* SPI4 IRQ handler */ - IRQ_DEFAULT_HANDLER 87 /* SPI5 IRQ handler */ - IRQ_DEFAULT_HANDLER 88 /* SPI6 IRQ handler */ - IRQ_DEFAULT_HANDLER 89 /* SPI7 IRQ handler */ - IRQ_DEFAULT_HANDLER 90 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_HANDLER 91 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_HANDLER 92 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_HANDLER 93 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_HANDLER 94 /* MCAN4 IRQ handler */ - IRQ_DEFAULT_HANDLER 95 /* MCAN5 IRQ handler */ - IRQ_DEFAULT_HANDLER 96 /* MCAN6 IRQ handler */ - IRQ_DEFAULT_HANDLER 97 /* MCAN7 IRQ handler */ - IRQ_DEFAULT_HANDLER 98 /* PTPC IRQ handler */ - IRQ_DEFAULT_HANDLER 99 /* QEI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 100 /* QEI1 IRQ handler */ - IRQ_DEFAULT_HANDLER 101 /* QEI2 IRQ handler */ - IRQ_DEFAULT_HANDLER 102 /* QEI3 IRQ handler */ - IRQ_DEFAULT_HANDLER 103 /* PWM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 104 /* PWM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 105 /* PWM2 IRQ handler */ - IRQ_DEFAULT_HANDLER 106 /* PWM3 IRQ handler */ - IRQ_DEFAULT_HANDLER 107 /* RDC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 108 /* RDC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 109 /* SDM0 IRQ handler */ - IRQ_DEFAULT_HANDLER 110 /* SDM1 IRQ handler */ - IRQ_DEFAULT_HANDLER 111 /* SEI[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 112 /* SEI[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 113 /* SEI[2] IRQ handler */ - IRQ_DEFAULT_HANDLER 114 /* SEI[3] IRQ handler */ - IRQ_DEFAULT_HANDLER 115 /* MTG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 116 /* MTG1 IRQ handler */ - IRQ_DEFAULT_HANDLER 117 /* VSC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 118 /* VSC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 119 /* CLC0[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 120 /* CLC0[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 121 /* CLC1[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 122 /* CLC1[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 123 /* TRGMUX0 IRQ handler */ - IRQ_DEFAULT_HANDLER 124 /* TRGMUX1 IRQ handler */ - IRQ_DEFAULT_HANDLER 125 /* ENET0 IRQ handler */ - IRQ_DEFAULT_HANDLER 126 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_HANDLER 127 /* USB0 IRQ handler */ - IRQ_DEFAULT_HANDLER 128 /* TSW[0] IRQ handler */ - IRQ_DEFAULT_HANDLER 129 /* TSW[1] IRQ handler */ - IRQ_DEFAULT_HANDLER 130 /* TSW[2] IRQ handler */ - IRQ_DEFAULT_HANDLER 131 /* TSW[3] IRQ handler */ - IRQ_DEFAULT_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ - IRQ_DEFAULT_HANDLER 133 /* ESC IRQ handler */ - IRQ_DEFAULT_HANDLER 134 /* ESC_SYNC0 IRQ handler */ - IRQ_DEFAULT_HANDLER 135 /* ESC_SYNC1 IRQ handler */ - IRQ_DEFAULT_HANDLER 136 /* ESC_RESET IRQ handler */ - IRQ_DEFAULT_HANDLER 137 /* XPI0 IRQ handler */ - IRQ_DEFAULT_HANDLER 138 /* FEMC IRQ handler */ - IRQ_DEFAULT_HANDLER 139 /* PPI IRQ handler */ - IRQ_DEFAULT_HANDLER 140 /* XDMA IRQ handler */ - IRQ_DEFAULT_HANDLER 141 /* FFA IRQ handler */ - IRQ_DEFAULT_HANDLER 142 /* SDP IRQ handler */ - IRQ_DEFAULT_HANDLER 143 /* RNG IRQ handler */ - IRQ_DEFAULT_HANDLER 144 /* PKA IRQ handler */ - IRQ_DEFAULT_HANDLER 145 /* PSEC IRQ handler */ - IRQ_DEFAULT_HANDLER 146 /* PGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 147 /* PEWDG IRQ handler */ - IRQ_DEFAULT_HANDLER 148 /* PTMR IRQ handler */ - IRQ_DEFAULT_HANDLER 149 /* PUART IRQ handler */ - IRQ_DEFAULT_HANDLER 150 /* FUSE IRQ handler */ - IRQ_DEFAULT_HANDLER 151 /* SECMON IRQ handler */ - IRQ_DEFAULT_HANDLER 152 /* RTC IRQ handler */ - IRQ_DEFAULT_HANDLER 153 /* PAD_WAKEUP IRQ handler */ - IRQ_DEFAULT_HANDLER 154 /* BGPIO IRQ handler */ - IRQ_DEFAULT_HANDLER 155 /* BVIO IRQ handler */ - IRQ_DEFAULT_HANDLER 156 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_HANDLER 157 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_HANDLER 158 /* CPU0 IRQ handler */ - IRQ_DEFAULT_HANDLER 159 /* CPU1 IRQ handler */ - IRQ_DEFAULT_HANDLER 160 /* DEBUG0 IRQ handler */ - IRQ_DEFAULT_HANDLER 161 /* DEBUG1 IRQ handler */ - - EXTERN irq_handler_trap - SECTION `.vector_table`:CODE:ROOT(10) - PUBLIC __vector_table - DATA - -__vector_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_trap -#endif - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_V IRQ handler */ - IRQ_HANDLER 8 /* GPIO0_W IRQ handler */ - IRQ_HANDLER 9 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 11 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 13 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 14 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 15 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 16 /* GPIO1_E IRQ handler */ - IRQ_HANDLER 17 /* GPIO1_F IRQ handler */ - IRQ_HANDLER 18 /* GPIO1_V IRQ handler */ - IRQ_HANDLER 19 /* GPIO1_W IRQ handler */ - IRQ_HANDLER 20 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 21 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 22 /* GPIO1_Z IRQ handler */ - IRQ_HANDLER 23 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 24 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 25 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 26 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 27 /* GPTMR4 IRQ handler */ - IRQ_HANDLER 28 /* GPTMR5 IRQ handler */ - IRQ_HANDLER 29 /* GPTMR6 IRQ handler */ - IRQ_HANDLER 30 /* GPTMR7 IRQ handler */ - IRQ_HANDLER 31 /* UART0 IRQ handler */ - IRQ_HANDLER 32 /* UART1 IRQ handler */ - IRQ_HANDLER 33 /* UART2 IRQ handler */ - IRQ_HANDLER 34 /* UART3 IRQ handler */ - IRQ_HANDLER 35 /* UART4 IRQ handler */ - IRQ_HANDLER 36 /* UART5 IRQ handler */ - IRQ_HANDLER 37 /* UART6 IRQ handler */ - IRQ_HANDLER 38 /* UART7 IRQ handler */ - IRQ_HANDLER 39 /* I2C0 IRQ handler */ - IRQ_HANDLER 40 /* I2C1 IRQ handler */ - IRQ_HANDLER 41 /* I2C2 IRQ handler */ - IRQ_HANDLER 42 /* I2C3 IRQ handler */ - IRQ_HANDLER 43 /* SPI0 IRQ handler */ - IRQ_HANDLER 44 /* SPI1 IRQ handler */ - IRQ_HANDLER 45 /* SPI2 IRQ handler */ - IRQ_HANDLER 46 /* SPI3 IRQ handler */ - IRQ_HANDLER 47 /* TSNS IRQ handler */ - IRQ_HANDLER 48 /* MBX0A IRQ handler */ - IRQ_HANDLER 49 /* MBX0B IRQ handler */ - IRQ_HANDLER 50 /* MBX1A IRQ handler */ - IRQ_HANDLER 51 /* MBX1B IRQ handler */ - IRQ_HANDLER 52 /* EWDG0 IRQ handler */ - IRQ_HANDLER 53 /* EWDG1 IRQ handler */ - IRQ_HANDLER 54 /* EWDG2 IRQ handler */ - IRQ_HANDLER 55 /* EWDG3 IRQ handler */ - IRQ_HANDLER 56 /* HDMA IRQ handler */ - IRQ_HANDLER 57 /* LOBS IRQ handler */ - IRQ_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_HANDLER 60 /* ADC2 IRQ handler */ - IRQ_HANDLER 61 /* ADC3 IRQ handler */ - IRQ_HANDLER 62 /* ACMP0[0] IRQ handler */ - IRQ_HANDLER 63 /* ACMP0[1] IRQ handler */ - IRQ_HANDLER 64 /* ACMP1[0] IRQ handler */ - IRQ_HANDLER 65 /* ACMP1[1] IRQ handler */ - IRQ_HANDLER 66 /* ACMP2[0] IRQ handler */ - IRQ_HANDLER 67 /* ACMP2[1] IRQ handler */ - IRQ_HANDLER 68 /* ACMP3[0] IRQ handler */ - IRQ_HANDLER 69 /* ACMP3[1] IRQ handler */ - IRQ_HANDLER 70 /* I2S0 IRQ handler */ - IRQ_HANDLER 71 /* I2S1 IRQ handler */ - IRQ_HANDLER 72 /* DAO IRQ handler */ - IRQ_HANDLER 73 /* PDM IRQ handler */ - IRQ_HANDLER 74 /* UART8 IRQ handler */ - IRQ_HANDLER 75 /* UART9 IRQ handler */ - IRQ_HANDLER 76 /* UART10 IRQ handler */ - IRQ_HANDLER 77 /* UART11 IRQ handler */ - IRQ_HANDLER 78 /* UART12 IRQ handler */ - IRQ_HANDLER 79 /* UART13 IRQ handler */ - IRQ_HANDLER 80 /* UART14 IRQ handler */ - IRQ_HANDLER 81 /* UART15 IRQ handler */ - IRQ_HANDLER 82 /* I2C4 IRQ handler */ - IRQ_HANDLER 83 /* I2C5 IRQ handler */ - IRQ_HANDLER 84 /* I2C6 IRQ handler */ - IRQ_HANDLER 85 /* I2C7 IRQ handler */ - IRQ_HANDLER 86 /* SPI4 IRQ handler */ - IRQ_HANDLER 87 /* SPI5 IRQ handler */ - IRQ_HANDLER 88 /* SPI6 IRQ handler */ - IRQ_HANDLER 89 /* SPI7 IRQ handler */ - IRQ_HANDLER 90 /* MCAN0 IRQ handler */ - IRQ_HANDLER 91 /* MCAN1 IRQ handler */ - IRQ_HANDLER 92 /* MCAN2 IRQ handler */ - IRQ_HANDLER 93 /* MCAN3 IRQ handler */ - IRQ_HANDLER 94 /* MCAN4 IRQ handler */ - IRQ_HANDLER 95 /* MCAN5 IRQ handler */ - IRQ_HANDLER 96 /* MCAN6 IRQ handler */ - IRQ_HANDLER 97 /* MCAN7 IRQ handler */ - IRQ_HANDLER 98 /* PTPC IRQ handler */ - IRQ_HANDLER 99 /* QEI0 IRQ handler */ - IRQ_HANDLER 100 /* QEI1 IRQ handler */ - IRQ_HANDLER 101 /* QEI2 IRQ handler */ - IRQ_HANDLER 102 /* QEI3 IRQ handler */ - IRQ_HANDLER 103 /* PWM0 IRQ handler */ - IRQ_HANDLER 104 /* PWM1 IRQ handler */ - IRQ_HANDLER 105 /* PWM2 IRQ handler */ - IRQ_HANDLER 106 /* PWM3 IRQ handler */ - IRQ_HANDLER 107 /* RDC0 IRQ handler */ - IRQ_HANDLER 108 /* RDC1 IRQ handler */ - IRQ_HANDLER 109 /* SDM0 IRQ handler */ - IRQ_HANDLER 110 /* SDM1 IRQ handler */ - IRQ_HANDLER 111 /* SEI[0] IRQ handler */ - IRQ_HANDLER 112 /* SEI[1] IRQ handler */ - IRQ_HANDLER 113 /* SEI[2] IRQ handler */ - IRQ_HANDLER 114 /* SEI[3] IRQ handler */ - IRQ_HANDLER 115 /* MTG0 IRQ handler */ - IRQ_HANDLER 116 /* MTG1 IRQ handler */ - IRQ_HANDLER 117 /* VSC0 IRQ handler */ - IRQ_HANDLER 118 /* VSC1 IRQ handler */ - IRQ_HANDLER 119 /* CLC0[0] IRQ handler */ - IRQ_HANDLER 120 /* CLC0[1] IRQ handler */ - IRQ_HANDLER 121 /* CLC1[0] IRQ handler */ - IRQ_HANDLER 122 /* CLC1[1] IRQ handler */ - IRQ_HANDLER 123 /* TRGMUX0 IRQ handler */ - IRQ_HANDLER 124 /* TRGMUX1 IRQ handler */ - IRQ_HANDLER 125 /* ENET0 IRQ handler */ - IRQ_HANDLER 126 /* NTMR0 IRQ handler */ - IRQ_HANDLER 127 /* USB0 IRQ handler */ - IRQ_HANDLER 128 /* TSW[0] IRQ handler */ - IRQ_HANDLER 129 /* TSW[1] IRQ handler */ - IRQ_HANDLER 130 /* TSW[2] IRQ handler */ - IRQ_HANDLER 131 /* TSW[3] IRQ handler */ - IRQ_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ - IRQ_HANDLER 133 /* ESC IRQ handler */ - IRQ_HANDLER 134 /* ESC_SYNC0 IRQ handler */ - IRQ_HANDLER 135 /* ESC_SYNC1 IRQ handler */ - IRQ_HANDLER 136 /* ESC_RESET IRQ handler */ - IRQ_HANDLER 137 /* XPI0 IRQ handler */ - IRQ_HANDLER 138 /* FEMC IRQ handler */ - IRQ_HANDLER 139 /* PPI IRQ handler */ - IRQ_HANDLER 140 /* XDMA IRQ handler */ - IRQ_HANDLER 141 /* FFA IRQ handler */ - IRQ_HANDLER 142 /* SDP IRQ handler */ - IRQ_HANDLER 143 /* RNG IRQ handler */ - IRQ_HANDLER 144 /* PKA IRQ handler */ - IRQ_HANDLER 145 /* PSEC IRQ handler */ - IRQ_HANDLER 146 /* PGPIO IRQ handler */ - IRQ_HANDLER 147 /* PEWDG IRQ handler */ - IRQ_HANDLER 148 /* PTMR IRQ handler */ - IRQ_HANDLER 149 /* PUART IRQ handler */ - IRQ_HANDLER 150 /* FUSE IRQ handler */ - IRQ_HANDLER 151 /* SECMON IRQ handler */ - IRQ_HANDLER 152 /* RTC IRQ handler */ - IRQ_HANDLER 153 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 154 /* BGPIO IRQ handler */ - IRQ_HANDLER 155 /* BVIO IRQ handler */ - IRQ_HANDLER 156 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 157 /* SYSCTL IRQ handler */ - IRQ_HANDLER 158 /* CPU0 IRQ handler */ - IRQ_HANDLER 159 /* CPU1 IRQ handler */ - IRQ_HANDLER 160 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 161 /* DEBUG1 IRQ handler */ - -#else - -.global default_irq_handler -.weak default_irq_handler -.align 2 -default_irq_handler: -1: j 1b - -.macro IRQ_HANDLER irq - .weak default_isr_\irq - .set default_isr_\irq, default_irq_handler - .long default_isr_\irq -.endm - -.section .vector_table, "a" -.global __vector_table -.align 10 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_trap, freertos_risc_v_trap_handler -#else - .set default_isr_trap, irq_handler_trap -#endif - -__vector_table: - .weak default_isr_trap - .long default_isr_trap - IRQ_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_HANDLER 7 /* GPIO0_V IRQ handler */ - IRQ_HANDLER 8 /* GPIO0_W IRQ handler */ - IRQ_HANDLER 9 /* GPIO0_X IRQ handler */ - IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */ - IRQ_HANDLER 11 /* GPIO0_Z IRQ handler */ - IRQ_HANDLER 12 /* GPIO1_A IRQ handler */ - IRQ_HANDLER 13 /* GPIO1_B IRQ handler */ - IRQ_HANDLER 14 /* GPIO1_C IRQ handler */ - IRQ_HANDLER 15 /* GPIO1_D IRQ handler */ - IRQ_HANDLER 16 /* GPIO1_E IRQ handler */ - IRQ_HANDLER 17 /* GPIO1_F IRQ handler */ - IRQ_HANDLER 18 /* GPIO1_V IRQ handler */ - IRQ_HANDLER 19 /* GPIO1_W IRQ handler */ - IRQ_HANDLER 20 /* GPIO1_X IRQ handler */ - IRQ_HANDLER 21 /* GPIO1_Y IRQ handler */ - IRQ_HANDLER 22 /* GPIO1_Z IRQ handler */ - IRQ_HANDLER 23 /* GPTMR0 IRQ handler */ - IRQ_HANDLER 24 /* GPTMR1 IRQ handler */ - IRQ_HANDLER 25 /* GPTMR2 IRQ handler */ - IRQ_HANDLER 26 /* GPTMR3 IRQ handler */ - IRQ_HANDLER 27 /* GPTMR4 IRQ handler */ - IRQ_HANDLER 28 /* GPTMR5 IRQ handler */ - IRQ_HANDLER 29 /* GPTMR6 IRQ handler */ - IRQ_HANDLER 30 /* GPTMR7 IRQ handler */ - IRQ_HANDLER 31 /* UART0 IRQ handler */ - IRQ_HANDLER 32 /* UART1 IRQ handler */ - IRQ_HANDLER 33 /* UART2 IRQ handler */ - IRQ_HANDLER 34 /* UART3 IRQ handler */ - IRQ_HANDLER 35 /* UART4 IRQ handler */ - IRQ_HANDLER 36 /* UART5 IRQ handler */ - IRQ_HANDLER 37 /* UART6 IRQ handler */ - IRQ_HANDLER 38 /* UART7 IRQ handler */ - IRQ_HANDLER 39 /* I2C0 IRQ handler */ - IRQ_HANDLER 40 /* I2C1 IRQ handler */ - IRQ_HANDLER 41 /* I2C2 IRQ handler */ - IRQ_HANDLER 42 /* I2C3 IRQ handler */ - IRQ_HANDLER 43 /* SPI0 IRQ handler */ - IRQ_HANDLER 44 /* SPI1 IRQ handler */ - IRQ_HANDLER 45 /* SPI2 IRQ handler */ - IRQ_HANDLER 46 /* SPI3 IRQ handler */ - IRQ_HANDLER 47 /* TSNS IRQ handler */ - IRQ_HANDLER 48 /* MBX0A IRQ handler */ - IRQ_HANDLER 49 /* MBX0B IRQ handler */ - IRQ_HANDLER 50 /* MBX1A IRQ handler */ - IRQ_HANDLER 51 /* MBX1B IRQ handler */ - IRQ_HANDLER 52 /* EWDG0 IRQ handler */ - IRQ_HANDLER 53 /* EWDG1 IRQ handler */ - IRQ_HANDLER 54 /* EWDG2 IRQ handler */ - IRQ_HANDLER 55 /* EWDG3 IRQ handler */ - IRQ_HANDLER 56 /* HDMA IRQ handler */ - IRQ_HANDLER 57 /* LOBS IRQ handler */ - IRQ_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_HANDLER 60 /* ADC2 IRQ handler */ - IRQ_HANDLER 61 /* ADC3 IRQ handler */ - IRQ_HANDLER 62 /* ACMP0[0] IRQ handler */ - IRQ_HANDLER 63 /* ACMP0[1] IRQ handler */ - IRQ_HANDLER 64 /* ACMP1[0] IRQ handler */ - IRQ_HANDLER 65 /* ACMP1[1] IRQ handler */ - IRQ_HANDLER 66 /* ACMP2[0] IRQ handler */ - IRQ_HANDLER 67 /* ACMP2[1] IRQ handler */ - IRQ_HANDLER 68 /* ACMP3[0] IRQ handler */ - IRQ_HANDLER 69 /* ACMP3[1] IRQ handler */ - IRQ_HANDLER 70 /* I2S0 IRQ handler */ - IRQ_HANDLER 71 /* I2S1 IRQ handler */ - IRQ_HANDLER 72 /* DAO IRQ handler */ - IRQ_HANDLER 73 /* PDM IRQ handler */ - IRQ_HANDLER 74 /* UART8 IRQ handler */ - IRQ_HANDLER 75 /* UART9 IRQ handler */ - IRQ_HANDLER 76 /* UART10 IRQ handler */ - IRQ_HANDLER 77 /* UART11 IRQ handler */ - IRQ_HANDLER 78 /* UART12 IRQ handler */ - IRQ_HANDLER 79 /* UART13 IRQ handler */ - IRQ_HANDLER 80 /* UART14 IRQ handler */ - IRQ_HANDLER 81 /* UART15 IRQ handler */ - IRQ_HANDLER 82 /* I2C4 IRQ handler */ - IRQ_HANDLER 83 /* I2C5 IRQ handler */ - IRQ_HANDLER 84 /* I2C6 IRQ handler */ - IRQ_HANDLER 85 /* I2C7 IRQ handler */ - IRQ_HANDLER 86 /* SPI4 IRQ handler */ - IRQ_HANDLER 87 /* SPI5 IRQ handler */ - IRQ_HANDLER 88 /* SPI6 IRQ handler */ - IRQ_HANDLER 89 /* SPI7 IRQ handler */ - IRQ_HANDLER 90 /* MCAN0 IRQ handler */ - IRQ_HANDLER 91 /* MCAN1 IRQ handler */ - IRQ_HANDLER 92 /* MCAN2 IRQ handler */ - IRQ_HANDLER 93 /* MCAN3 IRQ handler */ - IRQ_HANDLER 94 /* MCAN4 IRQ handler */ - IRQ_HANDLER 95 /* MCAN5 IRQ handler */ - IRQ_HANDLER 96 /* MCAN6 IRQ handler */ - IRQ_HANDLER 97 /* MCAN7 IRQ handler */ - IRQ_HANDLER 98 /* PTPC IRQ handler */ - IRQ_HANDLER 99 /* QEI0 IRQ handler */ - IRQ_HANDLER 100 /* QEI1 IRQ handler */ - IRQ_HANDLER 101 /* QEI2 IRQ handler */ - IRQ_HANDLER 102 /* QEI3 IRQ handler */ - IRQ_HANDLER 103 /* PWM0 IRQ handler */ - IRQ_HANDLER 104 /* PWM1 IRQ handler */ - IRQ_HANDLER 105 /* PWM2 IRQ handler */ - IRQ_HANDLER 106 /* PWM3 IRQ handler */ - IRQ_HANDLER 107 /* RDC0 IRQ handler */ - IRQ_HANDLER 108 /* RDC1 IRQ handler */ - IRQ_HANDLER 109 /* SDM0 IRQ handler */ - IRQ_HANDLER 110 /* SDM1 IRQ handler */ - IRQ_HANDLER 111 /* SEI[0] IRQ handler */ - IRQ_HANDLER 112 /* SEI[1] IRQ handler */ - IRQ_HANDLER 113 /* SEI[2] IRQ handler */ - IRQ_HANDLER 114 /* SEI[3] IRQ handler */ - IRQ_HANDLER 115 /* MTG0 IRQ handler */ - IRQ_HANDLER 116 /* MTG1 IRQ handler */ - IRQ_HANDLER 117 /* VSC0 IRQ handler */ - IRQ_HANDLER 118 /* VSC1 IRQ handler */ - IRQ_HANDLER 119 /* CLC0[0] IRQ handler */ - IRQ_HANDLER 120 /* CLC0[1] IRQ handler */ - IRQ_HANDLER 121 /* CLC1[0] IRQ handler */ - IRQ_HANDLER 122 /* CLC1[1] IRQ handler */ - IRQ_HANDLER 123 /* TRGMUX0 IRQ handler */ - IRQ_HANDLER 124 /* TRGMUX1 IRQ handler */ - IRQ_HANDLER 125 /* ENET0 IRQ handler */ - IRQ_HANDLER 126 /* NTMR0 IRQ handler */ - IRQ_HANDLER 127 /* USB0 IRQ handler */ - IRQ_HANDLER 128 /* TSW[0] IRQ handler */ - IRQ_HANDLER 129 /* TSW[1] IRQ handler */ - IRQ_HANDLER 130 /* TSW[2] IRQ handler */ - IRQ_HANDLER 131 /* TSW[3] IRQ handler */ - IRQ_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ - IRQ_HANDLER 133 /* ESC IRQ handler */ - IRQ_HANDLER 134 /* ESC_SYNC0 IRQ handler */ - IRQ_HANDLER 135 /* ESC_SYNC1 IRQ handler */ - IRQ_HANDLER 136 /* ESC_RESET IRQ handler */ - IRQ_HANDLER 137 /* XPI0 IRQ handler */ - IRQ_HANDLER 138 /* FEMC IRQ handler */ - IRQ_HANDLER 139 /* PPI IRQ handler */ - IRQ_HANDLER 140 /* XDMA IRQ handler */ - IRQ_HANDLER 141 /* FFA IRQ handler */ - IRQ_HANDLER 142 /* SDP IRQ handler */ - IRQ_HANDLER 143 /* RNG IRQ handler */ - IRQ_HANDLER 144 /* PKA IRQ handler */ - IRQ_HANDLER 145 /* PSEC IRQ handler */ - IRQ_HANDLER 146 /* PGPIO IRQ handler */ - IRQ_HANDLER 147 /* PEWDG IRQ handler */ - IRQ_HANDLER 148 /* PTMR IRQ handler */ - IRQ_HANDLER 149 /* PUART IRQ handler */ - IRQ_HANDLER 150 /* FUSE IRQ handler */ - IRQ_HANDLER 151 /* SECMON IRQ handler */ - IRQ_HANDLER 152 /* RTC IRQ handler */ - IRQ_HANDLER 153 /* PAD_WAKEUP IRQ handler */ - IRQ_HANDLER 154 /* BGPIO IRQ handler */ - IRQ_HANDLER 155 /* BVIO IRQ handler */ - IRQ_HANDLER 156 /* BROWNOUT IRQ handler */ - IRQ_HANDLER 157 /* SYSCTL IRQ handler */ - IRQ_HANDLER 158 /* CPU0 IRQ handler */ - IRQ_HANDLER 159 /* CPU1 IRQ handler */ - IRQ_HANDLER 160 /* DEBUG0 IRQ handler */ - IRQ_HANDLER 161 /* DEBUG1 IRQ handler */ - -#endif - -#ifdef __IAR_SYSTEMS_ASM__ - -IRQ_S_HANDLER macro - dc32 default_isr_s_\1 - endm - -IRQ_DEFAULT_S_HANDLER macro - PUBWEAK default_isr_s_\1 -default_isr_s_\1 - j default_irq_s_handler - endm - - SECTION `.isr_s_vector`:CODE:ROOT(10) - PUBWEAK default_irq_s_handler -default_irq_s_handler - j default_irq_s_handler - IRQ_DEFAULT_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_DEFAULT_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_DEFAULT_S_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_DEFAULT_S_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_DEFAULT_S_HANDLER 7 /* GPIO0_V IRQ handler */ - IRQ_DEFAULT_S_HANDLER 8 /* GPIO0_W IRQ handler */ - IRQ_DEFAULT_S_HANDLER 9 /* GPIO0_X IRQ handler */ - IRQ_DEFAULT_S_HANDLER 10 /* GPIO0_Y IRQ handler */ - IRQ_DEFAULT_S_HANDLER 11 /* GPIO0_Z IRQ handler */ - IRQ_DEFAULT_S_HANDLER 12 /* GPIO1_A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 13 /* GPIO1_B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 14 /* GPIO1_C IRQ handler */ - IRQ_DEFAULT_S_HANDLER 15 /* GPIO1_D IRQ handler */ - IRQ_DEFAULT_S_HANDLER 16 /* GPIO1_E IRQ handler */ - IRQ_DEFAULT_S_HANDLER 17 /* GPIO1_F IRQ handler */ - IRQ_DEFAULT_S_HANDLER 18 /* GPIO1_V IRQ handler */ - IRQ_DEFAULT_S_HANDLER 19 /* GPIO1_W IRQ handler */ - IRQ_DEFAULT_S_HANDLER 20 /* GPIO1_X IRQ handler */ - IRQ_DEFAULT_S_HANDLER 21 /* GPIO1_Y IRQ handler */ - IRQ_DEFAULT_S_HANDLER 22 /* GPIO1_Z IRQ handler */ - IRQ_DEFAULT_S_HANDLER 23 /* GPTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 24 /* GPTMR1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 25 /* GPTMR2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 26 /* GPTMR3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 27 /* GPTMR4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 28 /* GPTMR5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 29 /* GPTMR6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 30 /* GPTMR7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 31 /* UART0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 32 /* UART1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 33 /* UART2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 34 /* UART3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 35 /* UART4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 36 /* UART5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 37 /* UART6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 38 /* UART7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 39 /* I2C0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 40 /* I2C1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 41 /* I2C2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 42 /* I2C3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 43 /* SPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 44 /* SPI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 45 /* SPI2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 46 /* SPI3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 47 /* TSNS IRQ handler */ - IRQ_DEFAULT_S_HANDLER 48 /* MBX0A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 49 /* MBX0B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 50 /* MBX1A IRQ handler */ - IRQ_DEFAULT_S_HANDLER 51 /* MBX1B IRQ handler */ - IRQ_DEFAULT_S_HANDLER 52 /* EWDG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 53 /* EWDG1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 54 /* EWDG2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 55 /* EWDG3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 56 /* HDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 57 /* LOBS IRQ handler */ - IRQ_DEFAULT_S_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 60 /* ADC2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 61 /* ADC3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 62 /* ACMP0[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 63 /* ACMP0[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 64 /* ACMP1[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 65 /* ACMP1[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 66 /* ACMP2[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 67 /* ACMP2[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 68 /* ACMP3[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 69 /* ACMP3[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 70 /* I2S0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 71 /* I2S1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 72 /* DAO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 73 /* PDM IRQ handler */ - IRQ_DEFAULT_S_HANDLER 74 /* UART8 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 75 /* UART9 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 76 /* UART10 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 77 /* UART11 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 78 /* UART12 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 79 /* UART13 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 80 /* UART14 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 81 /* UART15 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 82 /* I2C4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 83 /* I2C5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 84 /* I2C6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 85 /* I2C7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 86 /* SPI4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 87 /* SPI5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 88 /* SPI6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 89 /* SPI7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 90 /* MCAN0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 91 /* MCAN1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 92 /* MCAN2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 93 /* MCAN3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 94 /* MCAN4 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 95 /* MCAN5 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 96 /* MCAN6 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 97 /* MCAN7 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 98 /* PTPC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 99 /* QEI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 100 /* QEI1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 101 /* QEI2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 102 /* QEI3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 103 /* PWM0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 104 /* PWM1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 105 /* PWM2 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 106 /* PWM3 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 107 /* RDC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 108 /* RDC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 109 /* SDM0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 110 /* SDM1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 111 /* SEI[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 112 /* SEI[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 113 /* SEI[2] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 114 /* SEI[3] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 115 /* MTG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 116 /* MTG1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 117 /* VSC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 118 /* VSC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 119 /* CLC0[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 120 /* CLC0[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 121 /* CLC1[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 122 /* CLC1[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 123 /* TRGMUX0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 124 /* TRGMUX1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 125 /* ENET0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 126 /* NTMR0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 127 /* USB0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 128 /* TSW[0] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 129 /* TSW[1] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 130 /* TSW[2] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 131 /* TSW[3] IRQ handler */ - IRQ_DEFAULT_S_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ - IRQ_DEFAULT_S_HANDLER 133 /* ESC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 134 /* ESC_SYNC0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 135 /* ESC_SYNC1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 136 /* ESC_RESET IRQ handler */ - IRQ_DEFAULT_S_HANDLER 137 /* XPI0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 138 /* FEMC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 139 /* PPI IRQ handler */ - IRQ_DEFAULT_S_HANDLER 140 /* XDMA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 141 /* FFA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 142 /* SDP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 143 /* RNG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 144 /* PKA IRQ handler */ - IRQ_DEFAULT_S_HANDLER 145 /* PSEC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 146 /* PGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 147 /* PEWDG IRQ handler */ - IRQ_DEFAULT_S_HANDLER 148 /* PTMR IRQ handler */ - IRQ_DEFAULT_S_HANDLER 149 /* PUART IRQ handler */ - IRQ_DEFAULT_S_HANDLER 150 /* FUSE IRQ handler */ - IRQ_DEFAULT_S_HANDLER 151 /* SECMON IRQ handler */ - IRQ_DEFAULT_S_HANDLER 152 /* RTC IRQ handler */ - IRQ_DEFAULT_S_HANDLER 153 /* PAD_WAKEUP IRQ handler */ - IRQ_DEFAULT_S_HANDLER 154 /* BGPIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 155 /* BVIO IRQ handler */ - IRQ_DEFAULT_S_HANDLER 156 /* BROWNOUT IRQ handler */ - IRQ_DEFAULT_S_HANDLER 157 /* SYSCTL IRQ handler */ - IRQ_DEFAULT_S_HANDLER 158 /* CPU0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 159 /* CPU1 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 160 /* DEBUG0 IRQ handler */ - IRQ_DEFAULT_S_HANDLER 161 /* DEBUG1 IRQ handler */ - - EXTERN irq_handler_s_trap - SECTION `.vector_s_table`:CODE:ROOT(10) - PUBLIC __vector_s_table - DATA - -__vector_s_table -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - dc32 freertos_risc_v_trap_handler -#else - dc32 irq_handler_s_trap -#endif - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_V IRQ handler */ - IRQ_S_HANDLER 8 /* GPIO0_W IRQ handler */ - IRQ_S_HANDLER 9 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 10 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 11 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 12 /* GPIO1_A IRQ handler */ - IRQ_S_HANDLER 13 /* GPIO1_B IRQ handler */ - IRQ_S_HANDLER 14 /* GPIO1_C IRQ handler */ - IRQ_S_HANDLER 15 /* GPIO1_D IRQ handler */ - IRQ_S_HANDLER 16 /* GPIO1_E IRQ handler */ - IRQ_S_HANDLER 17 /* GPIO1_F IRQ handler */ - IRQ_S_HANDLER 18 /* GPIO1_V IRQ handler */ - IRQ_S_HANDLER 19 /* GPIO1_W IRQ handler */ - IRQ_S_HANDLER 20 /* GPIO1_X IRQ handler */ - IRQ_S_HANDLER 21 /* GPIO1_Y IRQ handler */ - IRQ_S_HANDLER 22 /* GPIO1_Z IRQ handler */ - IRQ_S_HANDLER 23 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 24 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 25 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 26 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 27 /* GPTMR4 IRQ handler */ - IRQ_S_HANDLER 28 /* GPTMR5 IRQ handler */ - IRQ_S_HANDLER 29 /* GPTMR6 IRQ handler */ - IRQ_S_HANDLER 30 /* GPTMR7 IRQ handler */ - IRQ_S_HANDLER 31 /* UART0 IRQ handler */ - IRQ_S_HANDLER 32 /* UART1 IRQ handler */ - IRQ_S_HANDLER 33 /* UART2 IRQ handler */ - IRQ_S_HANDLER 34 /* UART3 IRQ handler */ - IRQ_S_HANDLER 35 /* UART4 IRQ handler */ - IRQ_S_HANDLER 36 /* UART5 IRQ handler */ - IRQ_S_HANDLER 37 /* UART6 IRQ handler */ - IRQ_S_HANDLER 38 /* UART7 IRQ handler */ - IRQ_S_HANDLER 39 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 40 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 41 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 42 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 43 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 44 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 45 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 46 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 47 /* TSNS IRQ handler */ - IRQ_S_HANDLER 48 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 49 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 50 /* MBX1A IRQ handler */ - IRQ_S_HANDLER 51 /* MBX1B IRQ handler */ - IRQ_S_HANDLER 52 /* EWDG0 IRQ handler */ - IRQ_S_HANDLER 53 /* EWDG1 IRQ handler */ - IRQ_S_HANDLER 54 /* EWDG2 IRQ handler */ - IRQ_S_HANDLER 55 /* EWDG3 IRQ handler */ - IRQ_S_HANDLER 56 /* HDMA IRQ handler */ - IRQ_S_HANDLER 57 /* LOBS IRQ handler */ - IRQ_S_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 60 /* ADC2 IRQ handler */ - IRQ_S_HANDLER 61 /* ADC3 IRQ handler */ - IRQ_S_HANDLER 62 /* ACMP0[0] IRQ handler */ - IRQ_S_HANDLER 63 /* ACMP0[1] IRQ handler */ - IRQ_S_HANDLER 64 /* ACMP1[0] IRQ handler */ - IRQ_S_HANDLER 65 /* ACMP1[1] IRQ handler */ - IRQ_S_HANDLER 66 /* ACMP2[0] IRQ handler */ - IRQ_S_HANDLER 67 /* ACMP2[1] IRQ handler */ - IRQ_S_HANDLER 68 /* ACMP3[0] IRQ handler */ - IRQ_S_HANDLER 69 /* ACMP3[1] IRQ handler */ - IRQ_S_HANDLER 70 /* I2S0 IRQ handler */ - IRQ_S_HANDLER 71 /* I2S1 IRQ handler */ - IRQ_S_HANDLER 72 /* DAO IRQ handler */ - IRQ_S_HANDLER 73 /* PDM IRQ handler */ - IRQ_S_HANDLER 74 /* UART8 IRQ handler */ - IRQ_S_HANDLER 75 /* UART9 IRQ handler */ - IRQ_S_HANDLER 76 /* UART10 IRQ handler */ - IRQ_S_HANDLER 77 /* UART11 IRQ handler */ - IRQ_S_HANDLER 78 /* UART12 IRQ handler */ - IRQ_S_HANDLER 79 /* UART13 IRQ handler */ - IRQ_S_HANDLER 80 /* UART14 IRQ handler */ - IRQ_S_HANDLER 81 /* UART15 IRQ handler */ - IRQ_S_HANDLER 82 /* I2C4 IRQ handler */ - IRQ_S_HANDLER 83 /* I2C5 IRQ handler */ - IRQ_S_HANDLER 84 /* I2C6 IRQ handler */ - IRQ_S_HANDLER 85 /* I2C7 IRQ handler */ - IRQ_S_HANDLER 86 /* SPI4 IRQ handler */ - IRQ_S_HANDLER 87 /* SPI5 IRQ handler */ - IRQ_S_HANDLER 88 /* SPI6 IRQ handler */ - IRQ_S_HANDLER 89 /* SPI7 IRQ handler */ - IRQ_S_HANDLER 90 /* MCAN0 IRQ handler */ - IRQ_S_HANDLER 91 /* MCAN1 IRQ handler */ - IRQ_S_HANDLER 92 /* MCAN2 IRQ handler */ - IRQ_S_HANDLER 93 /* MCAN3 IRQ handler */ - IRQ_S_HANDLER 94 /* MCAN4 IRQ handler */ - IRQ_S_HANDLER 95 /* MCAN5 IRQ handler */ - IRQ_S_HANDLER 96 /* MCAN6 IRQ handler */ - IRQ_S_HANDLER 97 /* MCAN7 IRQ handler */ - IRQ_S_HANDLER 98 /* PTPC IRQ handler */ - IRQ_S_HANDLER 99 /* QEI0 IRQ handler */ - IRQ_S_HANDLER 100 /* QEI1 IRQ handler */ - IRQ_S_HANDLER 101 /* QEI2 IRQ handler */ - IRQ_S_HANDLER 102 /* QEI3 IRQ handler */ - IRQ_S_HANDLER 103 /* PWM0 IRQ handler */ - IRQ_S_HANDLER 104 /* PWM1 IRQ handler */ - IRQ_S_HANDLER 105 /* PWM2 IRQ handler */ - IRQ_S_HANDLER 106 /* PWM3 IRQ handler */ - IRQ_S_HANDLER 107 /* RDC0 IRQ handler */ - IRQ_S_HANDLER 108 /* RDC1 IRQ handler */ - IRQ_S_HANDLER 109 /* SDM0 IRQ handler */ - IRQ_S_HANDLER 110 /* SDM1 IRQ handler */ - IRQ_S_HANDLER 111 /* SEI[0] IRQ handler */ - IRQ_S_HANDLER 112 /* SEI[1] IRQ handler */ - IRQ_S_HANDLER 113 /* SEI[2] IRQ handler */ - IRQ_S_HANDLER 114 /* SEI[3] IRQ handler */ - IRQ_S_HANDLER 115 /* MTG0 IRQ handler */ - IRQ_S_HANDLER 116 /* MTG1 IRQ handler */ - IRQ_S_HANDLER 117 /* VSC0 IRQ handler */ - IRQ_S_HANDLER 118 /* VSC1 IRQ handler */ - IRQ_S_HANDLER 119 /* CLC0[0] IRQ handler */ - IRQ_S_HANDLER 120 /* CLC0[1] IRQ handler */ - IRQ_S_HANDLER 121 /* CLC1[0] IRQ handler */ - IRQ_S_HANDLER 122 /* CLC1[1] IRQ handler */ - IRQ_S_HANDLER 123 /* TRGMUX0 IRQ handler */ - IRQ_S_HANDLER 124 /* TRGMUX1 IRQ handler */ - IRQ_S_HANDLER 125 /* ENET0 IRQ handler */ - IRQ_S_HANDLER 126 /* NTMR0 IRQ handler */ - IRQ_S_HANDLER 127 /* USB0 IRQ handler */ - IRQ_S_HANDLER 128 /* TSW[0] IRQ handler */ - IRQ_S_HANDLER 129 /* TSW[1] IRQ handler */ - IRQ_S_HANDLER 130 /* TSW[2] IRQ handler */ - IRQ_S_HANDLER 131 /* TSW[3] IRQ handler */ - IRQ_S_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ - IRQ_S_HANDLER 133 /* ESC IRQ handler */ - IRQ_S_HANDLER 134 /* ESC_SYNC0 IRQ handler */ - IRQ_S_HANDLER 135 /* ESC_SYNC1 IRQ handler */ - IRQ_S_HANDLER 136 /* ESC_RESET IRQ handler */ - IRQ_S_HANDLER 137 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 138 /* FEMC IRQ handler */ - IRQ_S_HANDLER 139 /* PPI IRQ handler */ - IRQ_S_HANDLER 140 /* XDMA IRQ handler */ - IRQ_S_HANDLER 141 /* FFA IRQ handler */ - IRQ_S_HANDLER 142 /* SDP IRQ handler */ - IRQ_S_HANDLER 143 /* RNG IRQ handler */ - IRQ_S_HANDLER 144 /* PKA IRQ handler */ - IRQ_S_HANDLER 145 /* PSEC IRQ handler */ - IRQ_S_HANDLER 146 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 147 /* PEWDG IRQ handler */ - IRQ_S_HANDLER 148 /* PTMR IRQ handler */ - IRQ_S_HANDLER 149 /* PUART IRQ handler */ - IRQ_S_HANDLER 150 /* FUSE IRQ handler */ - IRQ_S_HANDLER 151 /* SECMON IRQ handler */ - IRQ_S_HANDLER 152 /* RTC IRQ handler */ - IRQ_S_HANDLER 153 /* PAD_WAKEUP IRQ handler */ - IRQ_S_HANDLER 154 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 155 /* BVIO IRQ handler */ - IRQ_S_HANDLER 156 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 157 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 158 /* CPU0 IRQ handler */ - IRQ_S_HANDLER 159 /* CPU1 IRQ handler */ - IRQ_S_HANDLER 160 /* DEBUG0 IRQ handler */ - IRQ_S_HANDLER 161 /* DEBUG1 IRQ handler */ - -#else - -.global default_irq_s_handler -.weak default_irq_s_handler -.align 2 -default_irq_s_handler: -1: j 1b - -.macro IRQ_S_HANDLER irq - .weak default_isr_s_\irq - .set default_isr_s_\irq, default_irq_s_handler - .long default_isr_s_\irq -.endm - -.section .vector_s_table, "a" -.global __vector_s_table -.align 10 - -#if (!defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)) && defined(CONFIG_FREERTOS) - .set default_isr_s_trap, freertos_risc_v_trap_handler -#else - .set default_isr_s_trap, irq_handler_s_trap -#endif - -__vector_s_table: - .weak default_isr_s_trap - .long default_isr_s_trap - IRQ_S_HANDLER 1 /* GPIO0_A IRQ handler */ - IRQ_S_HANDLER 2 /* GPIO0_B IRQ handler */ - IRQ_S_HANDLER 3 /* GPIO0_C IRQ handler */ - IRQ_S_HANDLER 4 /* GPIO0_D IRQ handler */ - IRQ_S_HANDLER 5 /* GPIO0_E IRQ handler */ - IRQ_S_HANDLER 6 /* GPIO0_F IRQ handler */ - IRQ_S_HANDLER 7 /* GPIO0_V IRQ handler */ - IRQ_S_HANDLER 8 /* GPIO0_W IRQ handler */ - IRQ_S_HANDLER 9 /* GPIO0_X IRQ handler */ - IRQ_S_HANDLER 10 /* GPIO0_Y IRQ handler */ - IRQ_S_HANDLER 11 /* GPIO0_Z IRQ handler */ - IRQ_S_HANDLER 12 /* GPIO1_A IRQ handler */ - IRQ_S_HANDLER 13 /* GPIO1_B IRQ handler */ - IRQ_S_HANDLER 14 /* GPIO1_C IRQ handler */ - IRQ_S_HANDLER 15 /* GPIO1_D IRQ handler */ - IRQ_S_HANDLER 16 /* GPIO1_E IRQ handler */ - IRQ_S_HANDLER 17 /* GPIO1_F IRQ handler */ - IRQ_S_HANDLER 18 /* GPIO1_V IRQ handler */ - IRQ_S_HANDLER 19 /* GPIO1_W IRQ handler */ - IRQ_S_HANDLER 20 /* GPIO1_X IRQ handler */ - IRQ_S_HANDLER 21 /* GPIO1_Y IRQ handler */ - IRQ_S_HANDLER 22 /* GPIO1_Z IRQ handler */ - IRQ_S_HANDLER 23 /* GPTMR0 IRQ handler */ - IRQ_S_HANDLER 24 /* GPTMR1 IRQ handler */ - IRQ_S_HANDLER 25 /* GPTMR2 IRQ handler */ - IRQ_S_HANDLER 26 /* GPTMR3 IRQ handler */ - IRQ_S_HANDLER 27 /* GPTMR4 IRQ handler */ - IRQ_S_HANDLER 28 /* GPTMR5 IRQ handler */ - IRQ_S_HANDLER 29 /* GPTMR6 IRQ handler */ - IRQ_S_HANDLER 30 /* GPTMR7 IRQ handler */ - IRQ_S_HANDLER 31 /* UART0 IRQ handler */ - IRQ_S_HANDLER 32 /* UART1 IRQ handler */ - IRQ_S_HANDLER 33 /* UART2 IRQ handler */ - IRQ_S_HANDLER 34 /* UART3 IRQ handler */ - IRQ_S_HANDLER 35 /* UART4 IRQ handler */ - IRQ_S_HANDLER 36 /* UART5 IRQ handler */ - IRQ_S_HANDLER 37 /* UART6 IRQ handler */ - IRQ_S_HANDLER 38 /* UART7 IRQ handler */ - IRQ_S_HANDLER 39 /* I2C0 IRQ handler */ - IRQ_S_HANDLER 40 /* I2C1 IRQ handler */ - IRQ_S_HANDLER 41 /* I2C2 IRQ handler */ - IRQ_S_HANDLER 42 /* I2C3 IRQ handler */ - IRQ_S_HANDLER 43 /* SPI0 IRQ handler */ - IRQ_S_HANDLER 44 /* SPI1 IRQ handler */ - IRQ_S_HANDLER 45 /* SPI2 IRQ handler */ - IRQ_S_HANDLER 46 /* SPI3 IRQ handler */ - IRQ_S_HANDLER 47 /* TSNS IRQ handler */ - IRQ_S_HANDLER 48 /* MBX0A IRQ handler */ - IRQ_S_HANDLER 49 /* MBX0B IRQ handler */ - IRQ_S_HANDLER 50 /* MBX1A IRQ handler */ - IRQ_S_HANDLER 51 /* MBX1B IRQ handler */ - IRQ_S_HANDLER 52 /* EWDG0 IRQ handler */ - IRQ_S_HANDLER 53 /* EWDG1 IRQ handler */ - IRQ_S_HANDLER 54 /* EWDG2 IRQ handler */ - IRQ_S_HANDLER 55 /* EWDG3 IRQ handler */ - IRQ_S_HANDLER 56 /* HDMA IRQ handler */ - IRQ_S_HANDLER 57 /* LOBS IRQ handler */ - IRQ_S_HANDLER 58 /* ADC0 IRQ handler */ - IRQ_S_HANDLER 59 /* ADC1 IRQ handler */ - IRQ_S_HANDLER 60 /* ADC2 IRQ handler */ - IRQ_S_HANDLER 61 /* ADC3 IRQ handler */ - IRQ_S_HANDLER 62 /* ACMP0[0] IRQ handler */ - IRQ_S_HANDLER 63 /* ACMP0[1] IRQ handler */ - IRQ_S_HANDLER 64 /* ACMP1[0] IRQ handler */ - IRQ_S_HANDLER 65 /* ACMP1[1] IRQ handler */ - IRQ_S_HANDLER 66 /* ACMP2[0] IRQ handler */ - IRQ_S_HANDLER 67 /* ACMP2[1] IRQ handler */ - IRQ_S_HANDLER 68 /* ACMP3[0] IRQ handler */ - IRQ_S_HANDLER 69 /* ACMP3[1] IRQ handler */ - IRQ_S_HANDLER 70 /* I2S0 IRQ handler */ - IRQ_S_HANDLER 71 /* I2S1 IRQ handler */ - IRQ_S_HANDLER 72 /* DAO IRQ handler */ - IRQ_S_HANDLER 73 /* PDM IRQ handler */ - IRQ_S_HANDLER 74 /* UART8 IRQ handler */ - IRQ_S_HANDLER 75 /* UART9 IRQ handler */ - IRQ_S_HANDLER 76 /* UART10 IRQ handler */ - IRQ_S_HANDLER 77 /* UART11 IRQ handler */ - IRQ_S_HANDLER 78 /* UART12 IRQ handler */ - IRQ_S_HANDLER 79 /* UART13 IRQ handler */ - IRQ_S_HANDLER 80 /* UART14 IRQ handler */ - IRQ_S_HANDLER 81 /* UART15 IRQ handler */ - IRQ_S_HANDLER 82 /* I2C4 IRQ handler */ - IRQ_S_HANDLER 83 /* I2C5 IRQ handler */ - IRQ_S_HANDLER 84 /* I2C6 IRQ handler */ - IRQ_S_HANDLER 85 /* I2C7 IRQ handler */ - IRQ_S_HANDLER 86 /* SPI4 IRQ handler */ - IRQ_S_HANDLER 87 /* SPI5 IRQ handler */ - IRQ_S_HANDLER 88 /* SPI6 IRQ handler */ - IRQ_S_HANDLER 89 /* SPI7 IRQ handler */ - IRQ_S_HANDLER 90 /* MCAN0 IRQ handler */ - IRQ_S_HANDLER 91 /* MCAN1 IRQ handler */ - IRQ_S_HANDLER 92 /* MCAN2 IRQ handler */ - IRQ_S_HANDLER 93 /* MCAN3 IRQ handler */ - IRQ_S_HANDLER 94 /* MCAN4 IRQ handler */ - IRQ_S_HANDLER 95 /* MCAN5 IRQ handler */ - IRQ_S_HANDLER 96 /* MCAN6 IRQ handler */ - IRQ_S_HANDLER 97 /* MCAN7 IRQ handler */ - IRQ_S_HANDLER 98 /* PTPC IRQ handler */ - IRQ_S_HANDLER 99 /* QEI0 IRQ handler */ - IRQ_S_HANDLER 100 /* QEI1 IRQ handler */ - IRQ_S_HANDLER 101 /* QEI2 IRQ handler */ - IRQ_S_HANDLER 102 /* QEI3 IRQ handler */ - IRQ_S_HANDLER 103 /* PWM0 IRQ handler */ - IRQ_S_HANDLER 104 /* PWM1 IRQ handler */ - IRQ_S_HANDLER 105 /* PWM2 IRQ handler */ - IRQ_S_HANDLER 106 /* PWM3 IRQ handler */ - IRQ_S_HANDLER 107 /* RDC0 IRQ handler */ - IRQ_S_HANDLER 108 /* RDC1 IRQ handler */ - IRQ_S_HANDLER 109 /* SDM0 IRQ handler */ - IRQ_S_HANDLER 110 /* SDM1 IRQ handler */ - IRQ_S_HANDLER 111 /* SEI[0] IRQ handler */ - IRQ_S_HANDLER 112 /* SEI[1] IRQ handler */ - IRQ_S_HANDLER 113 /* SEI[2] IRQ handler */ - IRQ_S_HANDLER 114 /* SEI[3] IRQ handler */ - IRQ_S_HANDLER 115 /* MTG0 IRQ handler */ - IRQ_S_HANDLER 116 /* MTG1 IRQ handler */ - IRQ_S_HANDLER 117 /* VSC0 IRQ handler */ - IRQ_S_HANDLER 118 /* VSC1 IRQ handler */ - IRQ_S_HANDLER 119 /* CLC0[0] IRQ handler */ - IRQ_S_HANDLER 120 /* CLC0[1] IRQ handler */ - IRQ_S_HANDLER 121 /* CLC1[0] IRQ handler */ - IRQ_S_HANDLER 122 /* CLC1[1] IRQ handler */ - IRQ_S_HANDLER 123 /* TRGMUX0 IRQ handler */ - IRQ_S_HANDLER 124 /* TRGMUX1 IRQ handler */ - IRQ_S_HANDLER 125 /* ENET0 IRQ handler */ - IRQ_S_HANDLER 126 /* NTMR0 IRQ handler */ - IRQ_S_HANDLER 127 /* USB0 IRQ handler */ - IRQ_S_HANDLER 128 /* TSW[0] IRQ handler */ - IRQ_S_HANDLER 129 /* TSW[1] IRQ handler */ - IRQ_S_HANDLER 130 /* TSW[2] IRQ handler */ - IRQ_S_HANDLER 131 /* TSW[3] IRQ handler */ - IRQ_S_HANDLER 132 /* TSW_PTP_EVT IRQ handler */ - IRQ_S_HANDLER 133 /* ESC IRQ handler */ - IRQ_S_HANDLER 134 /* ESC_SYNC0 IRQ handler */ - IRQ_S_HANDLER 135 /* ESC_SYNC1 IRQ handler */ - IRQ_S_HANDLER 136 /* ESC_RESET IRQ handler */ - IRQ_S_HANDLER 137 /* XPI0 IRQ handler */ - IRQ_S_HANDLER 138 /* FEMC IRQ handler */ - IRQ_S_HANDLER 139 /* PPI IRQ handler */ - IRQ_S_HANDLER 140 /* XDMA IRQ handler */ - IRQ_S_HANDLER 141 /* FFA IRQ handler */ - IRQ_S_HANDLER 142 /* SDP IRQ handler */ - IRQ_S_HANDLER 143 /* RNG IRQ handler */ - IRQ_S_HANDLER 144 /* PKA IRQ handler */ - IRQ_S_HANDLER 145 /* PSEC IRQ handler */ - IRQ_S_HANDLER 146 /* PGPIO IRQ handler */ - IRQ_S_HANDLER 147 /* PEWDG IRQ handler */ - IRQ_S_HANDLER 148 /* PTMR IRQ handler */ - IRQ_S_HANDLER 149 /* PUART IRQ handler */ - IRQ_S_HANDLER 150 /* FUSE IRQ handler */ - IRQ_S_HANDLER 151 /* SECMON IRQ handler */ - IRQ_S_HANDLER 152 /* RTC IRQ handler */ - IRQ_S_HANDLER 153 /* PAD_WAKEUP IRQ handler */ - IRQ_S_HANDLER 154 /* BGPIO IRQ handler */ - IRQ_S_HANDLER 155 /* BVIO IRQ handler */ - IRQ_S_HANDLER 156 /* BROWNOUT IRQ handler */ - IRQ_S_HANDLER 157 /* SYSCTL IRQ handler */ - IRQ_S_HANDLER 158 /* CPU0 IRQ handler */ - IRQ_S_HANDLER 159 /* CPU1 IRQ handler */ - IRQ_S_HANDLER 160 /* DEBUG0 IRQ handler */ - IRQ_S_HANDLER 161 /* DEBUG1 IRQ handler */ - -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_acmp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_acmp_regs.h deleted file mode 100644 index 1f67819e312..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_acmp_regs.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ACMP_H -#define HPM_ACMP_H - -typedef struct { - struct { - __RW uint32_t CFG; /* 0x0: Configure Register */ - __RW uint32_t DACCFG; /* 0x4: DAC configure register */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - __RW uint32_t SR; /* 0x10: Status register */ - __RW uint32_t IRQEN; /* 0x14: Interrupt request enable register */ - __RW uint32_t DMAEN; /* 0x18: DMA request enable register */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - } CHANNEL[2]; -} ACMP_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CFG */ -/* - * HYST (RW) - * - * This bitfield configure the comparator hysteresis. - * 00: Hysteresis level 0 - * 01: Hysteresis level 1 - * 10: Hysteresis level 2 - * 11: Hysteresis level 3 - */ -#define ACMP_CHANNEL_CFG_HYST_MASK (0xC0000000UL) -#define ACMP_CHANNEL_CFG_HYST_SHIFT (30U) -#define ACMP_CHANNEL_CFG_HYST_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HYST_SHIFT) & ACMP_CHANNEL_CFG_HYST_MASK) -#define ACMP_CHANNEL_CFG_HYST_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HYST_MASK) >> ACMP_CHANNEL_CFG_HYST_SHIFT) - -/* - * DACEN (RW) - * - * This bit enable the comparator internal DAC - * 0: DAC disabled - * 1: DAC enabled - */ -#define ACMP_CHANNEL_CFG_DACEN_MASK (0x20000000UL) -#define ACMP_CHANNEL_CFG_DACEN_SHIFT (29U) -#define ACMP_CHANNEL_CFG_DACEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DACEN_SHIFT) & ACMP_CHANNEL_CFG_DACEN_MASK) -#define ACMP_CHANNEL_CFG_DACEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DACEN_MASK) >> ACMP_CHANNEL_CFG_DACEN_SHIFT) - -/* - * HPMODE (RW) - * - * This bit enable the comparator high performance mode. - * 0: HP mode disabled - * 1: HP mode enabled - */ -#define ACMP_CHANNEL_CFG_HPMODE_MASK (0x10000000UL) -#define ACMP_CHANNEL_CFG_HPMODE_SHIFT (28U) -#define ACMP_CHANNEL_CFG_HPMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_HPMODE_SHIFT) & ACMP_CHANNEL_CFG_HPMODE_MASK) -#define ACMP_CHANNEL_CFG_HPMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_HPMODE_MASK) >> ACMP_CHANNEL_CFG_HPMODE_SHIFT) - -/* - * CMPEN (RW) - * - * This bit enable the comparator. - * 0: ACMP disabled - * 1: ACMP enabled - */ -#define ACMP_CHANNEL_CFG_CMPEN_MASK (0x8000000UL) -#define ACMP_CHANNEL_CFG_CMPEN_SHIFT (27U) -#define ACMP_CHANNEL_CFG_CMPEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPEN_SHIFT) & ACMP_CHANNEL_CFG_CMPEN_MASK) -#define ACMP_CHANNEL_CFG_CMPEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPEN_MASK) >> ACMP_CHANNEL_CFG_CMPEN_SHIFT) - -/* - * MINSEL (RW) - * - * PIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_MINSEL_MASK (0x7000000UL) -#define ACMP_CHANNEL_CFG_MINSEL_SHIFT (24U) -#define ACMP_CHANNEL_CFG_MINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_MINSEL_SHIFT) & ACMP_CHANNEL_CFG_MINSEL_MASK) -#define ACMP_CHANNEL_CFG_MINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_MINSEL_MASK) >> ACMP_CHANNEL_CFG_MINSEL_SHIFT) - -/* - * DAC_TRIG_EN (RW) - * - * if set, the dac value is from moto system when valid - * if clr, use dac_cfg value - */ -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK (0x800000UL) -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT (23U) -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) -#define ACMP_CHANNEL_CFG_DAC_TRIG_EN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_DAC_TRIG_EN_MASK) >> ACMP_CHANNEL_CFG_DAC_TRIG_EN_SHIFT) - -/* - * PINSEL (RW) - * - * MIN select, from pad_ai_acmp[7:1] and dac_out - */ -#define ACMP_CHANNEL_CFG_PINSEL_MASK (0x700000UL) -#define ACMP_CHANNEL_CFG_PINSEL_SHIFT (20U) -#define ACMP_CHANNEL_CFG_PINSEL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_PINSEL_SHIFT) & ACMP_CHANNEL_CFG_PINSEL_MASK) -#define ACMP_CHANNEL_CFG_PINSEL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_PINSEL_MASK) >> ACMP_CHANNEL_CFG_PINSEL_SHIFT) - -/* - * CMPOEN (RW) - * - * This bit enable the comparator output on pad. - * 0: ACMP output disabled - * 1: ACMP output enabled - */ -#define ACMP_CHANNEL_CFG_CMPOEN_MASK (0x80000UL) -#define ACMP_CHANNEL_CFG_CMPOEN_SHIFT (19U) -#define ACMP_CHANNEL_CFG_CMPOEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_CMPOEN_SHIFT) & ACMP_CHANNEL_CFG_CMPOEN_MASK) -#define ACMP_CHANNEL_CFG_CMPOEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_CMPOEN_MASK) >> ACMP_CHANNEL_CFG_CMPOEN_SHIFT) - -/* - * FLTBYPS (RW) - * - * This bit bypass the comparator output digital filter. - * 0: The ACMP output need pass digital filter - * 1: The ACMP output digital filter is bypassed. - */ -#define ACMP_CHANNEL_CFG_FLTBYPS_MASK (0x40000UL) -#define ACMP_CHANNEL_CFG_FLTBYPS_SHIFT (18U) -#define ACMP_CHANNEL_CFG_FLTBYPS_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) -#define ACMP_CHANNEL_CFG_FLTBYPS_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTBYPS_MASK) >> ACMP_CHANNEL_CFG_FLTBYPS_SHIFT) - -/* - * WINEN (RW) - * - * This bit enable the comparator window mode. - * 0: Window mode is disabled - * 1: Window mode is enabled - */ -#define ACMP_CHANNEL_CFG_WINEN_MASK (0x20000UL) -#define ACMP_CHANNEL_CFG_WINEN_SHIFT (17U) -#define ACMP_CHANNEL_CFG_WINEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_WINEN_SHIFT) & ACMP_CHANNEL_CFG_WINEN_MASK) -#define ACMP_CHANNEL_CFG_WINEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_WINEN_MASK) >> ACMP_CHANNEL_CFG_WINEN_SHIFT) - -/* - * OPOL (RW) - * - * The output polarity control bit. - * 0: The ACMP output remain un-changed. - * 1: The ACMP output is inverted. - */ -#define ACMP_CHANNEL_CFG_OPOL_MASK (0x10000UL) -#define ACMP_CHANNEL_CFG_OPOL_SHIFT (16U) -#define ACMP_CHANNEL_CFG_OPOL_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_OPOL_SHIFT) & ACMP_CHANNEL_CFG_OPOL_MASK) -#define ACMP_CHANNEL_CFG_OPOL_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_OPOL_MASK) >> ACMP_CHANNEL_CFG_OPOL_SHIFT) - -/* - * FLTMODE (RW) - * - * This bitfield define the ACMP output digital filter mode: - * 000-bypass - * 100-change immediately; - * 101-change after filter; - * 110-stalbe low; - * 111-stable high - */ -#define ACMP_CHANNEL_CFG_FLTMODE_MASK (0xE000U) -#define ACMP_CHANNEL_CFG_FLTMODE_SHIFT (13U) -#define ACMP_CHANNEL_CFG_FLTMODE_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTMODE_SHIFT) & ACMP_CHANNEL_CFG_FLTMODE_MASK) -#define ACMP_CHANNEL_CFG_FLTMODE_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTMODE_MASK) >> ACMP_CHANNEL_CFG_FLTMODE_SHIFT) - -/* - * SYNCEN (RW) - * - * This bit enable the comparator output synchronization. - * 0: ACMP output not synchronized with ACMP clock. - * 1: ACMP output synchronized with ACMP clock. - */ -#define ACMP_CHANNEL_CFG_SYNCEN_MASK (0x1000U) -#define ACMP_CHANNEL_CFG_SYNCEN_SHIFT (12U) -#define ACMP_CHANNEL_CFG_SYNCEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_SYNCEN_SHIFT) & ACMP_CHANNEL_CFG_SYNCEN_MASK) -#define ACMP_CHANNEL_CFG_SYNCEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_SYNCEN_MASK) >> ACMP_CHANNEL_CFG_SYNCEN_SHIFT) - -/* - * FLTLEN (RW) - * - * This bitfield define the ACMP output digital filter length. The unit is ACMP clock cycle. - */ -#define ACMP_CHANNEL_CFG_FLTLEN_MASK (0xFFFU) -#define ACMP_CHANNEL_CFG_FLTLEN_SHIFT (0U) -#define ACMP_CHANNEL_CFG_FLTLEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_CFG_FLTLEN_SHIFT) & ACMP_CHANNEL_CFG_FLTLEN_MASK) -#define ACMP_CHANNEL_CFG_FLTLEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_CFG_FLTLEN_MASK) >> ACMP_CHANNEL_CFG_FLTLEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DACCFG */ -/* - * DACCFG (RW) - * - * 8bit DAC digital value output to analog block - */ -#define ACMP_CHANNEL_DACCFG_DACCFG_MASK (0xFFU) -#define ACMP_CHANNEL_DACCFG_DACCFG_SHIFT (0U) -#define ACMP_CHANNEL_DACCFG_DACCFG_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) -#define ACMP_CHANNEL_DACCFG_DACCFG_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DACCFG_DACCFG_MASK) >> ACMP_CHANNEL_DACCFG_DACCFG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: SR */ -/* - * FEDGF (RW) - * - * Output falling edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_FEDGF_MASK (0x2U) -#define ACMP_CHANNEL_SR_FEDGF_SHIFT (1U) -#define ACMP_CHANNEL_SR_FEDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_FEDGF_SHIFT) & ACMP_CHANNEL_SR_FEDGF_MASK) -#define ACMP_CHANNEL_SR_FEDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_FEDGF_MASK) >> ACMP_CHANNEL_SR_FEDGF_SHIFT) - -/* - * REDGF (RW) - * - * Output rising edge flag. Write 1 to clear this flag. - */ -#define ACMP_CHANNEL_SR_REDGF_MASK (0x1U) -#define ACMP_CHANNEL_SR_REDGF_SHIFT (0U) -#define ACMP_CHANNEL_SR_REDGF_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_SR_REDGF_SHIFT) & ACMP_CHANNEL_SR_REDGF_MASK) -#define ACMP_CHANNEL_SR_REDGF_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_SR_REDGF_MASK) >> ACMP_CHANNEL_SR_REDGF_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: IRQEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_IRQEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_FEDGEN_MASK) >> ACMP_CHANNEL_IRQEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag interrupt enable bit. - */ -#define ACMP_CHANNEL_IRQEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_IRQEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) -#define ACMP_CHANNEL_IRQEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_IRQEN_REDGEN_MASK) >> ACMP_CHANNEL_IRQEN_REDGEN_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: DMAEN */ -/* - * FEDGEN (RW) - * - * Output falling edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_FEDGEN_MASK (0x2U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT (1U) -#define ACMP_CHANNEL_DMAEN_FEDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_FEDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_FEDGEN_MASK) >> ACMP_CHANNEL_DMAEN_FEDGEN_SHIFT) - -/* - * REDGEN (RW) - * - * Output rising edge flag DMA request enable bit. - */ -#define ACMP_CHANNEL_DMAEN_REDGEN_MASK (0x1U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SHIFT (0U) -#define ACMP_CHANNEL_DMAEN_REDGEN_SET(x) (((uint32_t)(x) << ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) -#define ACMP_CHANNEL_DMAEN_REDGEN_GET(x) (((uint32_t)(x) & ACMP_CHANNEL_DMAEN_REDGEN_MASK) >> ACMP_CHANNEL_DMAEN_REDGEN_SHIFT) - - - -/* CHANNEL register group index macro definition */ -#define ACMP_CHANNEL_CHN0 (0UL) -#define ACMP_CHANNEL_CHN1 (1UL) - - -#endif /* HPM_ACMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_adc16_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_adc16_regs.h deleted file mode 100644 index ed7d3cb6d03..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_adc16_regs.h +++ /dev/null @@ -1,1094 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ADC16_H -#define HPM_ADC16_H - -typedef struct { - __RW uint32_t CONFIG[12]; /* 0x0 - 0x2C: */ - __RW uint32_t TRG_DMA_ADDR; /* 0x30: */ - __RW uint32_t TRG_SW_STA; /* 0x34: */ - __R uint8_t RESERVED0[968]; /* 0x38 - 0x3FF: Reserved */ - __R uint32_t BUS_RESULT[16]; /* 0x400 - 0x43C: */ - __R uint8_t RESERVED1[192]; /* 0x440 - 0x4FF: Reserved */ - __RW uint32_t BUF_CFG0; /* 0x500: */ - __R uint8_t RESERVED2[764]; /* 0x504 - 0x7FF: Reserved */ - __RW uint32_t SEQ_CFG0; /* 0x800: */ - __RW uint32_t SEQ_DMA_ADDR; /* 0x804: */ - __R uint32_t SEQ_WR_ADDR; /* 0x808: */ - __RW uint32_t SEQ_DMA_CFG; /* 0x80C: */ - __RW uint32_t SEQ_QUE[16]; /* 0x810 - 0x84C: */ - __RW uint32_t SEQ_HIGH_CFG; /* 0x850: */ - __R uint8_t RESERVED3[940]; /* 0x854 - 0xBFF: Reserved */ - struct { - __RW uint32_t PRD_CFG; /* 0xC00: */ - __RW uint32_t PRD_THSHD_CFG; /* 0xC04: */ - __R uint32_t PRD_RESULT; /* 0xC08: */ - __R uint8_t RESERVED0[4]; /* 0xC0C - 0xC0F: Reserved */ - } PRD_CFG[16]; - __R uint8_t RESERVED4[768]; /* 0xD00 - 0xFFF: Reserved */ - __RW uint32_t SAMPLE_CFG[16]; /* 0x1000 - 0x103C: */ - __R uint8_t RESERVED5[196]; /* 0x1040 - 0x1103: Reserved */ - __RW uint32_t CONV_CFG1; /* 0x1104: */ - __RW uint32_t ADC_CFG0; /* 0x1108: */ - __R uint8_t RESERVED6[4]; /* 0x110C - 0x110F: Reserved */ - __RW uint32_t INT_STS; /* 0x1110: */ - __RW uint32_t INT_EN; /* 0x1114: */ - __RW uint32_t TRIGMUX_EN; /* 0x1118: */ - __RW uint32_t TRG_CMPT_FLAG; /* 0x111C: */ - __R uint8_t RESERVED7[224]; /* 0x1120 - 0x11FF: Reserved */ - __RW uint32_t ANA_CTRL0; /* 0x1200: */ - __R uint8_t RESERVED8[12]; /* 0x1204 - 0x120F: Reserved */ - __RW uint32_t ANA_STATUS; /* 0x1210: */ - __R uint8_t RESERVED9[492]; /* 0x1214 - 0x13FF: Reserved */ - __RW uint16_t ADC16_PARAMS[34]; /* 0x1400 - 0x1442: */ - __RW uint32_t ADC16_CONFIG0; /* 0x1444: */ - __R uint8_t RESERVED10[24]; /* 0x1448 - 0x145F: Reserved */ - __RW uint32_t ADC16_CONFIG1; /* 0x1460: */ -} ADC16_Type; - - -/* Bitfield definition for register array: CONFIG */ -/* - * TRIG_LEN (WO) - * - * length for current trigger, can up to 4 conversions for one trigger, from 0 to 3 - */ -#define ADC16_CONFIG_TRIG_LEN_MASK (0xC0000000UL) -#define ADC16_CONFIG_TRIG_LEN_SHIFT (30U) -#define ADC16_CONFIG_TRIG_LEN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_TRIG_LEN_SHIFT) & ADC16_CONFIG_TRIG_LEN_MASK) -#define ADC16_CONFIG_TRIG_LEN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_TRIG_LEN_MASK) >> ADC16_CONFIG_TRIG_LEN_SHIFT) - -/* - * INTEN3 (RW) - * - * interrupt enable for 4th conversion - */ -#define ADC16_CONFIG_INTEN3_MASK (0x20000000UL) -#define ADC16_CONFIG_INTEN3_SHIFT (29U) -#define ADC16_CONFIG_INTEN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN3_SHIFT) & ADC16_CONFIG_INTEN3_MASK) -#define ADC16_CONFIG_INTEN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN3_MASK) >> ADC16_CONFIG_INTEN3_SHIFT) - -/* - * CHAN3 (RW) - * - * channel number for 4th conversion - */ -#define ADC16_CONFIG_CHAN3_MASK (0x1F000000UL) -#define ADC16_CONFIG_CHAN3_SHIFT (24U) -#define ADC16_CONFIG_CHAN3_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN3_SHIFT) & ADC16_CONFIG_CHAN3_MASK) -#define ADC16_CONFIG_CHAN3_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN3_MASK) >> ADC16_CONFIG_CHAN3_SHIFT) - -/* - * INTEN2 (RW) - * - * interrupt enable for 3rd conversion - */ -#define ADC16_CONFIG_INTEN2_MASK (0x200000UL) -#define ADC16_CONFIG_INTEN2_SHIFT (21U) -#define ADC16_CONFIG_INTEN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN2_SHIFT) & ADC16_CONFIG_INTEN2_MASK) -#define ADC16_CONFIG_INTEN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN2_MASK) >> ADC16_CONFIG_INTEN2_SHIFT) - -/* - * CHAN2 (RW) - * - * channel number for 3rd conversion - */ -#define ADC16_CONFIG_CHAN2_MASK (0x1F0000UL) -#define ADC16_CONFIG_CHAN2_SHIFT (16U) -#define ADC16_CONFIG_CHAN2_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN2_SHIFT) & ADC16_CONFIG_CHAN2_MASK) -#define ADC16_CONFIG_CHAN2_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN2_MASK) >> ADC16_CONFIG_CHAN2_SHIFT) - -/* - * INTEN1 (RW) - * - * interrupt enable for 2nd conversion - */ -#define ADC16_CONFIG_INTEN1_MASK (0x2000U) -#define ADC16_CONFIG_INTEN1_SHIFT (13U) -#define ADC16_CONFIG_INTEN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN1_SHIFT) & ADC16_CONFIG_INTEN1_MASK) -#define ADC16_CONFIG_INTEN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN1_MASK) >> ADC16_CONFIG_INTEN1_SHIFT) - -/* - * CHAN1 (RW) - * - * channel number for 2nd conversion - */ -#define ADC16_CONFIG_CHAN1_MASK (0x1F00U) -#define ADC16_CONFIG_CHAN1_SHIFT (8U) -#define ADC16_CONFIG_CHAN1_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN1_SHIFT) & ADC16_CONFIG_CHAN1_MASK) -#define ADC16_CONFIG_CHAN1_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN1_MASK) >> ADC16_CONFIG_CHAN1_SHIFT) - -/* - * QUEUE_EN (RW) - * - * preemption queue enable control - */ -#define ADC16_CONFIG_QUEUE_EN_MASK (0x40U) -#define ADC16_CONFIG_QUEUE_EN_SHIFT (6U) -#define ADC16_CONFIG_QUEUE_EN_SET(x) (((uint32_t)(x) << ADC16_CONFIG_QUEUE_EN_SHIFT) & ADC16_CONFIG_QUEUE_EN_MASK) -#define ADC16_CONFIG_QUEUE_EN_GET(x) (((uint32_t)(x) & ADC16_CONFIG_QUEUE_EN_MASK) >> ADC16_CONFIG_QUEUE_EN_SHIFT) - -/* - * INTEN0 (RW) - * - * interrupt enable for 1st conversion - */ -#define ADC16_CONFIG_INTEN0_MASK (0x20U) -#define ADC16_CONFIG_INTEN0_SHIFT (5U) -#define ADC16_CONFIG_INTEN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_INTEN0_SHIFT) & ADC16_CONFIG_INTEN0_MASK) -#define ADC16_CONFIG_INTEN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_INTEN0_MASK) >> ADC16_CONFIG_INTEN0_SHIFT) - -/* - * CHAN0 (RW) - * - * channel number for 1st conversion - */ -#define ADC16_CONFIG_CHAN0_MASK (0x1FU) -#define ADC16_CONFIG_CHAN0_SHIFT (0U) -#define ADC16_CONFIG_CHAN0_SET(x) (((uint32_t)(x) << ADC16_CONFIG_CHAN0_SHIFT) & ADC16_CONFIG_CHAN0_MASK) -#define ADC16_CONFIG_CHAN0_GET(x) (((uint32_t)(x) & ADC16_CONFIG_CHAN0_MASK) >> ADC16_CONFIG_CHAN0_SHIFT) - -/* Bitfield definition for register: TRG_DMA_ADDR */ -/* - * TRG_DMA_ADDR (RW) - * - * buffer start address for trigger queue, 192byte total, 16 bytes for each trigger (4 bytes for each conversion) - */ -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT (2U) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SET(x) (((uint32_t)(x) << ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) -#define ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_GET(x) (((uint32_t)(x) & ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_MASK) >> ADC16_TRG_DMA_ADDR_TRG_DMA_ADDR_SHIFT) - -/* Bitfield definition for register: TRG_SW_STA */ -/* - * TRG_SW_STA (RW) - * - * SW trigger start bit, HW will clear it after all conversions(up to 4) finished. SW should make sure it's 0 before set it. - */ -#define ADC16_TRG_SW_STA_TRG_SW_STA_MASK (0x10U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT (4U) -#define ADC16_TRG_SW_STA_TRG_SW_STA_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) -#define ADC16_TRG_SW_STA_TRG_SW_STA_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRG_SW_STA_MASK) >> ADC16_TRG_SW_STA_TRG_SW_STA_SHIFT) - -/* - * TRIG_SW_INDEX (RW) - * - * which trigger for the SW trigger - * 0 for trig0a, 1 for trig0b… - * 3 for trig1a, …11 for trig3c - */ -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK (0xFU) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT (0U) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_SET(x) (((uint32_t)(x) << ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) -#define ADC16_TRG_SW_STA_TRIG_SW_INDEX_GET(x) (((uint32_t)(x) & ADC16_TRG_SW_STA_TRIG_SW_INDEX_MASK) >> ADC16_TRG_SW_STA_TRIG_SW_INDEX_SHIFT) - -/* Bitfield definition for register array: BUS_RESULT */ -/* - * VALID (RO) - * - * set after conversion finished if wait_dis is set, cleared after software read. - * The first time read with 0 will trigger one new conversion. - * If SW read other channel when one channel conversion is in progress, it will not trigger new conversion at other channel, and will get old result with valid 0, also with read_cflct interrupt status bit set. - * the result may not realtime if software read once and wait long time to read again - */ -#define ADC16_BUS_RESULT_VALID_MASK (0x10000UL) -#define ADC16_BUS_RESULT_VALID_SHIFT (16U) -#define ADC16_BUS_RESULT_VALID_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_VALID_MASK) >> ADC16_BUS_RESULT_VALID_SHIFT) - -/* - * CHAN_RESULT (RO) - * - * read this register will trigger one adc conversion. - * If wait_dis bit is set, SW will get the latest conversion result(not current one) with valid bit is 0, SW need polling valid bit till it's set to get current result - * If wait_dis bit is 0, SW can get the current conversion result with holding the bus, valid bit is always set at this mode. this is not recommended if channel sample time is too long - */ -#define ADC16_BUS_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_BUS_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_BUS_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_BUS_RESULT_CHAN_RESULT_MASK) >> ADC16_BUS_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register: BUF_CFG0 */ -/* - * BUS_MODE_EN (RW) - * - * bus mode enable - */ -#define ADC16_BUF_CFG0_BUS_MODE_EN_MASK (0x2U) -#define ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT (1U) -#define ADC16_BUF_CFG0_BUS_MODE_EN_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) -#define ADC16_BUF_CFG0_BUS_MODE_EN_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_BUS_MODE_EN_MASK) >> ADC16_BUF_CFG0_BUS_MODE_EN_SHIFT) - -/* - * WAIT_DIS (RW) - * - * set to disable read waiting, get result immediately but maybe not current conversion result. - */ -#define ADC16_BUF_CFG0_WAIT_DIS_MASK (0x1U) -#define ADC16_BUF_CFG0_WAIT_DIS_SHIFT (0U) -#define ADC16_BUF_CFG0_WAIT_DIS_SET(x) (((uint32_t)(x) << ADC16_BUF_CFG0_WAIT_DIS_SHIFT) & ADC16_BUF_CFG0_WAIT_DIS_MASK) -#define ADC16_BUF_CFG0_WAIT_DIS_GET(x) (((uint32_t)(x) & ADC16_BUF_CFG0_WAIT_DIS_MASK) >> ADC16_BUF_CFG0_WAIT_DIS_SHIFT) - -/* Bitfield definition for register: SEQ_CFG0 */ -/* - * CYCLE (RO) - * - * current dma write cycle bit - */ -#define ADC16_SEQ_CFG0_CYCLE_MASK (0x80000000UL) -#define ADC16_SEQ_CFG0_CYCLE_SHIFT (31U) -#define ADC16_SEQ_CFG0_CYCLE_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CYCLE_MASK) >> ADC16_SEQ_CFG0_CYCLE_SHIFT) - -/* - * SEQ_LEN (RW) - * - * sequence queue length, 0 for one, 0xF for 16 - */ -#define ADC16_SEQ_CFG0_SEQ_LEN_MASK (0xF00U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SHIFT (8U) -#define ADC16_SEQ_CFG0_SEQ_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) -#define ADC16_SEQ_CFG0_SEQ_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SEQ_LEN_MASK) >> ADC16_SEQ_CFG0_SEQ_LEN_SHIFT) - -/* - * RESTART_EN (RW) - * - * if set together with cont_en, HW will continue process the whole queue after trigger once. - * If cont_en is 0, this bit is not used - */ -#define ADC16_SEQ_CFG0_RESTART_EN_MASK (0x10U) -#define ADC16_SEQ_CFG0_RESTART_EN_SHIFT (4U) -#define ADC16_SEQ_CFG0_RESTART_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_RESTART_EN_SHIFT) & ADC16_SEQ_CFG0_RESTART_EN_MASK) -#define ADC16_SEQ_CFG0_RESTART_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_RESTART_EN_MASK) >> ADC16_SEQ_CFG0_RESTART_EN_SHIFT) - -/* - * CONT_EN (RW) - * - * if set, HW will continue process the queue till end(seq_len) after trigger once - */ -#define ADC16_SEQ_CFG0_CONT_EN_MASK (0x8U) -#define ADC16_SEQ_CFG0_CONT_EN_SHIFT (3U) -#define ADC16_SEQ_CFG0_CONT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_CONT_EN_SHIFT) & ADC16_SEQ_CFG0_CONT_EN_MASK) -#define ADC16_SEQ_CFG0_CONT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_CONT_EN_MASK) >> ADC16_SEQ_CFG0_CONT_EN_SHIFT) - -/* - * SW_TRIG (WO) - * - * SW trigger, pulse signal, cleared by HW one cycle later - */ -#define ADC16_SEQ_CFG0_SW_TRIG_MASK (0x4U) -#define ADC16_SEQ_CFG0_SW_TRIG_SHIFT (2U) -#define ADC16_SEQ_CFG0_SW_TRIG_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_SHIFT) - -/* - * SW_TRIG_EN (RW) - * - * set to enable SW trigger - */ -#define ADC16_SEQ_CFG0_SW_TRIG_EN_MASK (0x2U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT (1U) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_SW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_SW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_SW_TRIG_EN_SHIFT) - -/* - * HW_TRIG_EN (RW) - * - * set to enable external HW trigger, only trigger on posedge - */ -#define ADC16_SEQ_CFG0_HW_TRIG_EN_MASK (0x1U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT (0U) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) -#define ADC16_SEQ_CFG0_HW_TRIG_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_CFG0_HW_TRIG_EN_MASK) >> ADC16_SEQ_CFG0_HW_TRIG_EN_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_ADDR */ -/* - * TAR_ADDR (RW) - * - * dma target address, should be 4-byte aligned - */ -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK (0xFFFFFFFCUL) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT (2U) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) -#define ADC16_SEQ_DMA_ADDR_TAR_ADDR_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_ADDR_TAR_ADDR_MASK) >> ADC16_SEQ_DMA_ADDR_TAR_ADDR_SHIFT) - -/* Bitfield definition for register: SEQ_WR_ADDR */ -/* - * SEQ_WR_POINTER (RO) - * - * HW update this field after each dma write, it indicate the next dma write pointer. - * dma write address is (tar_addr+seq_wr_pointer)*4 - */ -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK (0xFFFFFFUL) -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT (0U) -#define ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_GET(x) (((uint32_t)(x) & ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_MASK) >> ADC16_SEQ_WR_ADDR_SEQ_WR_POINTER_SHIFT) - -/* Bitfield definition for register: SEQ_DMA_CFG */ -/* - * STOP_POS (RW) - * - * if stop_en is set, SW is responsible to update this field to the next read point, HW should not write data to this point since it's not read out by SW yet - */ -#define ADC16_SEQ_DMA_CFG_STOP_POS_MASK (0xFFF0000UL) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT (16U) -#define ADC16_SEQ_DMA_CFG_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_POS_MASK) >> ADC16_SEQ_DMA_CFG_STOP_POS_SHIFT) - -/* - * DMA_RST (RW) - * - * set this bit will reset HW dma write pointer to seq_dma_addr, and set HW cycle bit to 1. dma is halted if this bit is set. - * SW should clear all cycle bit in buffer to 0 before clear dma_rst - */ -#define ADC16_SEQ_DMA_CFG_DMA_RST_MASK (0x2000U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT (13U) -#define ADC16_SEQ_DMA_CFG_DMA_RST_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) -#define ADC16_SEQ_DMA_CFG_DMA_RST_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_DMA_RST_MASK) >> ADC16_SEQ_DMA_CFG_DMA_RST_SHIFT) - -/* - * STOP_EN (RW) - * - * set to stop dma if reach the stop_pos - */ -#define ADC16_SEQ_DMA_CFG_STOP_EN_MASK (0x1000U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT (12U) -#define ADC16_SEQ_DMA_CFG_STOP_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) -#define ADC16_SEQ_DMA_CFG_STOP_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_STOP_EN_MASK) >> ADC16_SEQ_DMA_CFG_STOP_EN_SHIFT) - -/* - * BUF_LEN (RW) - * - * dma buffer length, after write to (tar_addr[31:2]+buf_len)*4, the next dma address will be tar_addr[31:2]*4 - * 0 for 4byte; - * 0xFFF for 16kbyte. - */ -#define ADC16_SEQ_DMA_CFG_BUF_LEN_MASK (0xFFFU) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT (0U) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_SET(x) (((uint32_t)(x) << ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) -#define ADC16_SEQ_DMA_CFG_BUF_LEN_GET(x) (((uint32_t)(x) & ADC16_SEQ_DMA_CFG_BUF_LEN_MASK) >> ADC16_SEQ_DMA_CFG_BUF_LEN_SHIFT) - -/* Bitfield definition for register array: SEQ_QUE */ -/* - * SEQ_INT_EN (RW) - * - * interrupt enable for current conversion - */ -#define ADC16_SEQ_QUE_SEQ_INT_EN_MASK (0x20U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT (5U) -#define ADC16_SEQ_QUE_SEQ_INT_EN_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) -#define ADC16_SEQ_QUE_SEQ_INT_EN_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_SEQ_INT_EN_MASK) >> ADC16_SEQ_QUE_SEQ_INT_EN_SHIFT) - -/* - * CHAN_NUM_4_0 (RW) - * - * channel number for current conversion - */ -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK (0x1FU) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT (0U) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_SET(x) (((uint32_t)(x) << ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) -#define ADC16_SEQ_QUE_CHAN_NUM_4_0_GET(x) (((uint32_t)(x) & ADC16_SEQ_QUE_CHAN_NUM_4_0_MASK) >> ADC16_SEQ_QUE_CHAN_NUM_4_0_SHIFT) - -/* Bitfield definition for register: SEQ_HIGH_CFG */ -/* - * STOP_POS_HIGH (RW) - * - */ -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK (0xFFF000UL) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT (12U) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) -#define ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_STOP_POS_HIGH_SHIFT) - -/* - * BUF_LEN_HIGH (RW) - * - */ -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK (0xFFFU) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT (0U) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SET(x) (((uint32_t)(x) << ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) -#define ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_GET(x) (((uint32_t)(x) & ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_MASK) >> ADC16_SEQ_HIGH_CFG_BUF_LEN_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_CFG */ -/* - * PRESCALE (RW) - * - * 0: 1xclock, 1: 2x, 2: 4x, 3: 8x,…,15: 32768x,…,31: 2Gx - */ -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK (0x1F00U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT (8U) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRESCALE_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRESCALE_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRESCALE_SHIFT) - -/* - * PRD (RW) - * - * conver period, with prescale. - * Set to 0 means disable current channel - */ -#define ADC16_PRD_CFG_PRD_CFG_PRD_MASK (0xFFU) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_CFG_PRD_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) -#define ADC16_PRD_CFG_PRD_CFG_PRD_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_CFG_PRD_MASK) >> ADC16_PRD_CFG_PRD_CFG_PRD_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_THSHD_CFG */ -/* - * THSHDH (RW) - * - * threshold high, assert interrupt(if enabled) if result exceed high or low. - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK (0xFFFF0000UL) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT (16U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDH_SHIFT) - -/* - * THSHDL (RW) - * - * threshold low - */ -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SET(x) (((uint32_t)(x) << ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) -#define ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_MASK) >> ADC16_PRD_CFG_PRD_THSHD_CFG_THSHDL_SHIFT) - -/* Bitfield definition for register of struct array PRD_CFG: PRD_RESULT */ -/* - * CHAN_RESULT (RO) - * - * adc convert result, update after each valid conversion. - * it may be updated period according to config, also may be updated due to other queue convert the same channel - */ -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK (0xFFFFU) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT (0U) -#define ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_GET(x) (((uint32_t)(x) & ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_MASK) >> ADC16_PRD_CFG_PRD_RESULT_CHAN_RESULT_SHIFT) - -/* Bitfield definition for register array: SAMPLE_CFG */ -/* - * SAMPLE_CLOCK_NUMBER_SHIFT (RW) - * - * shift for sample clock number - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK (0xE00U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT (9U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT_SHIFT) - -/* - * SAMPLE_CLOCK_NUMBER (RW) - * - * sample clock number, base on clock_period, default one period - */ -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK (0x1FFU) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT (0U) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) -#define ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_MASK) >> ADC16_SAMPLE_CFG_SAMPLE_CLOCK_NUMBER_SHIFT) - -/* Bitfield definition for register: CONV_CFG1 */ -/* - * CONVERT_CLOCK_NUMBER (RW) - * - * convert clock numbers, set to 21 (0x15) for 16bit mode, which means convert need 21 adc clock cycles(based on clock after divider); - * user can use small value to get faster conversion, but less accuracy, need to config cov_end_cnt at adc16_config1 also. - * Ex: use 200MHz bus clock for adc, set sample_clock_number to 4, sample_clock_number_shift to 0, covert_clk_number to 21 for 16bit mode, clock_divder to 3, then each ADC conversion(plus sample) need 25 cycles(50MHz). - */ -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK (0x1F0U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT (4U) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) -#define ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_MASK) >> ADC16_CONV_CFG1_CONVERT_CLOCK_NUMBER_SHIFT) - -/* - * CLOCK_DIVIDER (RW) - * - * clock_period, N half clock cycle per half adc cycle - * 0 for same adc_clk and bus_clk, - * 1 for 1:2, - * 2 for 1:3, - * ... - * 15 for 1:16 - * Note: set to 2 can genenerate 66.7MHz adc_clk at 200MHz bus_clk - */ -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK (0xFU) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT (0U) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_SET(x) (((uint32_t)(x) << ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) -#define ADC16_CONV_CFG1_CLOCK_DIVIDER_GET(x) (((uint32_t)(x) & ADC16_CONV_CFG1_CLOCK_DIVIDER_MASK) >> ADC16_CONV_CFG1_CLOCK_DIVIDER_SHIFT) - -/* Bitfield definition for register: ADC_CFG0 */ -/* - * SEL_SYNC_AHB (RW) - * - * set to 1 will enable sync AHB bus, to get better bus performance. - * Adc_clk must to be set to same as bus clock at this mode - */ -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK (0x80000000UL) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT (31U) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) -#define ADC16_ADC_CFG0_SEL_SYNC_AHB_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_SEL_SYNC_AHB_MASK) >> ADC16_ADC_CFG0_SEL_SYNC_AHB_SHIFT) - -/* - * ADC_AHB_EN (RW) - * - * set to 1 to enable ADC DMA to write data to soc memory bus, for trig queue and seq queue; - */ -#define ADC16_ADC_CFG0_ADC_AHB_EN_MASK (0x20000000UL) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT (29U) -#define ADC16_ADC_CFG0_ADC_AHB_EN_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) -#define ADC16_ADC_CFG0_ADC_AHB_EN_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_ADC_AHB_EN_MASK) >> ADC16_ADC_CFG0_ADC_AHB_EN_SHIFT) - -/* - * PORT3_REALTIME (RW) - * - * set to enable trg queue stop other queues - */ -#define ADC16_ADC_CFG0_PORT3_REALTIME_MASK (0x1U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT (0U) -#define ADC16_ADC_CFG0_PORT3_REALTIME_SET(x) (((uint32_t)(x) << ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) -#define ADC16_ADC_CFG0_PORT3_REALTIME_GET(x) (((uint32_t)(x) & ADC16_ADC_CFG0_PORT3_REALTIME_MASK) >> ADC16_ADC_CFG0_PORT3_REALTIME_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * TRIG_CMPT (RW1C) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_STS_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_STS_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_STS_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_CMPT_SHIFT) & ADC16_INT_STS_TRIG_CMPT_MASK) -#define ADC16_INT_STS_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_CMPT_MASK) >> ADC16_INT_STS_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_STS_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_SW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_STS_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_STS_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_TRIG_HW_CFLCT_MASK) >> ADC16_INT_STS_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW1C) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_STS_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_STS_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_STS_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_READ_CFLCT_SHIFT) & ADC16_INT_STS_READ_CFLCT_MASK) -#define ADC16_INT_STS_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_READ_CFLCT_MASK) >> ADC16_INT_STS_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW1C) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_STS_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_STS_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_SW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW1C) - * - */ -#define ADC16_INT_STS_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_STS_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_STS_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_HW_CFLCT_MASK) >> ADC16_INT_STS_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW1C) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_STS_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_STS_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_STS_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_DMAABT_SHIFT) & ADC16_INT_STS_SEQ_DMAABT_MASK) -#define ADC16_INT_STS_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_DMAABT_MASK) >> ADC16_INT_STS_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW1C) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_STS_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_STS_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_STS_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CMPT_SHIFT) & ADC16_INT_STS_SEQ_CMPT_MASK) -#define ADC16_INT_STS_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CMPT_MASK) >> ADC16_INT_STS_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW1C) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_STS_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_STS_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_STS_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_STS_SEQ_CVC_SHIFT) & ADC16_INT_STS_SEQ_CVC_MASK) -#define ADC16_INT_STS_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_STS_SEQ_CVC_MASK) >> ADC16_INT_STS_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW1C) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_STS_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_STS_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_STS_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) -#define ADC16_INT_STS_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_STS_DMA_FIFO_FULL_MASK) >> ADC16_INT_STS_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW1C) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_STS_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_STS_AHB_ERR_SHIFT (21U) -#define ADC16_INT_STS_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_STS_AHB_ERR_SHIFT) & ADC16_INT_STS_AHB_ERR_MASK) -#define ADC16_INT_STS_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_STS_AHB_ERR_MASK) >> ADC16_INT_STS_AHB_ERR_SHIFT) - -/* - * STOP_POS (RW1C) - * - */ -#define ADC16_INT_STS_STOP_POS_MASK (0x100000UL) -#define ADC16_INT_STS_STOP_POS_SHIFT (20U) -#define ADC16_INT_STS_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_INT_STS_STOP_POS_SHIFT) & ADC16_INT_STS_STOP_POS_MASK) -#define ADC16_INT_STS_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_INT_STS_STOP_POS_MASK) >> ADC16_INT_STS_STOP_POS_SHIFT) - -/* - * WDOG (RW1C) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_STS_WDOG_MASK (0xFFFFU) -#define ADC16_INT_STS_WDOG_SHIFT (0U) -#define ADC16_INT_STS_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_STS_WDOG_SHIFT) & ADC16_INT_STS_WDOG_MASK) -#define ADC16_INT_STS_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_STS_WDOG_MASK) >> ADC16_INT_STS_WDOG_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * TRIG_CMPT (RW) - * - * interrupt for one trigger conversion complete if enabled - */ -#define ADC16_INT_EN_TRIG_CMPT_MASK (0x80000000UL) -#define ADC16_INT_EN_TRIG_CMPT_SHIFT (31U) -#define ADC16_INT_EN_TRIG_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_CMPT_SHIFT) & ADC16_INT_EN_TRIG_CMPT_MASK) -#define ADC16_INT_EN_TRIG_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_CMPT_MASK) >> ADC16_INT_EN_TRIG_CMPT_SHIFT) - -/* - * TRIG_SW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_SW_CFLCT_MASK (0x40000000UL) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT (30U) -#define ADC16_INT_EN_TRIG_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_SW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_SW_CFLCT_SHIFT) - -/* - * TRIG_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_TRIG_HW_CFLCT_MASK (0x20000000UL) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT (29U) -#define ADC16_INT_EN_TRIG_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) -#define ADC16_INT_EN_TRIG_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_TRIG_HW_CFLCT_MASK) >> ADC16_INT_EN_TRIG_HW_CFLCT_SHIFT) - -/* - * READ_CFLCT (RW) - * - * read conflict interrupt, set if wait_dis is set, one conversion is in progress, SW read another channel - */ -#define ADC16_INT_EN_READ_CFLCT_MASK (0x10000000UL) -#define ADC16_INT_EN_READ_CFLCT_SHIFT (28U) -#define ADC16_INT_EN_READ_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_READ_CFLCT_SHIFT) & ADC16_INT_EN_READ_CFLCT_MASK) -#define ADC16_INT_EN_READ_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_READ_CFLCT_MASK) >> ADC16_INT_EN_READ_CFLCT_SHIFT) - -/* - * SEQ_SW_CFLCT (RW) - * - * sequence queue conflict interrupt, set if HW or SW trigger received during conversion - */ -#define ADC16_INT_EN_SEQ_SW_CFLCT_MASK (0x8000000UL) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT (27U) -#define ADC16_INT_EN_SEQ_SW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_SW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_SW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_SW_CFLCT_SHIFT) - -/* - * SEQ_HW_CFLCT (RW) - * - */ -#define ADC16_INT_EN_SEQ_HW_CFLCT_MASK (0x4000000UL) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT (26U) -#define ADC16_INT_EN_SEQ_HW_CFLCT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) -#define ADC16_INT_EN_SEQ_HW_CFLCT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_HW_CFLCT_MASK) >> ADC16_INT_EN_SEQ_HW_CFLCT_SHIFT) - -/* - * SEQ_DMAABT (RW) - * - * dma abort interrupt, set if seqence dma write pointer reachs sw read pointer if stop_en is set - */ -#define ADC16_INT_EN_SEQ_DMAABT_MASK (0x2000000UL) -#define ADC16_INT_EN_SEQ_DMAABT_SHIFT (25U) -#define ADC16_INT_EN_SEQ_DMAABT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_DMAABT_SHIFT) & ADC16_INT_EN_SEQ_DMAABT_MASK) -#define ADC16_INT_EN_SEQ_DMAABT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_DMAABT_MASK) >> ADC16_INT_EN_SEQ_DMAABT_SHIFT) - -/* - * SEQ_CMPT (RW) - * - * the whole sequence complete interrupt - */ -#define ADC16_INT_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_INT_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_INT_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CMPT_SHIFT) & ADC16_INT_EN_SEQ_CMPT_MASK) -#define ADC16_INT_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CMPT_MASK) >> ADC16_INT_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - * one conversion complete in seq_queue if related seq_int_en is set - */ -#define ADC16_INT_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_INT_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_INT_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_INT_EN_SEQ_CVC_SHIFT) & ADC16_INT_EN_SEQ_CVC_MASK) -#define ADC16_INT_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_INT_EN_SEQ_CVC_MASK) >> ADC16_INT_EN_SEQ_CVC_SHIFT) - -/* - * DMA_FIFO_FULL (RW) - * - * DMA fifo full interrupt, user need to check clock frequency if it's set. - */ -#define ADC16_INT_EN_DMA_FIFO_FULL_MASK (0x400000UL) -#define ADC16_INT_EN_DMA_FIFO_FULL_SHIFT (22U) -#define ADC16_INT_EN_DMA_FIFO_FULL_SET(x) (((uint32_t)(x) << ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) -#define ADC16_INT_EN_DMA_FIFO_FULL_GET(x) (((uint32_t)(x) & ADC16_INT_EN_DMA_FIFO_FULL_MASK) >> ADC16_INT_EN_DMA_FIFO_FULL_SHIFT) - -/* - * AHB_ERR (RW) - * - * set if got hresp=1, generally caused by wrong trg_dma_addr or seq_dma_addr - */ -#define ADC16_INT_EN_AHB_ERR_MASK (0x200000UL) -#define ADC16_INT_EN_AHB_ERR_SHIFT (21U) -#define ADC16_INT_EN_AHB_ERR_SET(x) (((uint32_t)(x) << ADC16_INT_EN_AHB_ERR_SHIFT) & ADC16_INT_EN_AHB_ERR_MASK) -#define ADC16_INT_EN_AHB_ERR_GET(x) (((uint32_t)(x) & ADC16_INT_EN_AHB_ERR_MASK) >> ADC16_INT_EN_AHB_ERR_SHIFT) - -/* - * STOP_POS (RW) - * - */ -#define ADC16_INT_EN_STOP_POS_MASK (0x100000UL) -#define ADC16_INT_EN_STOP_POS_SHIFT (20U) -#define ADC16_INT_EN_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_INT_EN_STOP_POS_SHIFT) & ADC16_INT_EN_STOP_POS_MASK) -#define ADC16_INT_EN_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_INT_EN_STOP_POS_MASK) >> ADC16_INT_EN_STOP_POS_SHIFT) - -/* - * WDOG (RW) - * - * set if one chanel watch dog event triggered - */ -#define ADC16_INT_EN_WDOG_MASK (0xFFFFU) -#define ADC16_INT_EN_WDOG_SHIFT (0U) -#define ADC16_INT_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_INT_EN_WDOG_SHIFT) & ADC16_INT_EN_WDOG_MASK) -#define ADC16_INT_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_INT_EN_WDOG_MASK) >> ADC16_INT_EN_WDOG_SHIFT) - -/* Bitfield definition for register: TRIGMUX_EN */ -/* - * SEQ_CMPT (RW) - * - */ -#define ADC16_TRIGMUX_EN_SEQ_CMPT_MASK (0x1000000UL) -#define ADC16_TRIGMUX_EN_SEQ_CMPT_SHIFT (24U) -#define ADC16_TRIGMUX_EN_SEQ_CMPT_SET(x) (((uint32_t)(x) << ADC16_TRIGMUX_EN_SEQ_CMPT_SHIFT) & ADC16_TRIGMUX_EN_SEQ_CMPT_MASK) -#define ADC16_TRIGMUX_EN_SEQ_CMPT_GET(x) (((uint32_t)(x) & ADC16_TRIGMUX_EN_SEQ_CMPT_MASK) >> ADC16_TRIGMUX_EN_SEQ_CMPT_SHIFT) - -/* - * SEQ_CVC (RW) - * - */ -#define ADC16_TRIGMUX_EN_SEQ_CVC_MASK (0x800000UL) -#define ADC16_TRIGMUX_EN_SEQ_CVC_SHIFT (23U) -#define ADC16_TRIGMUX_EN_SEQ_CVC_SET(x) (((uint32_t)(x) << ADC16_TRIGMUX_EN_SEQ_CVC_SHIFT) & ADC16_TRIGMUX_EN_SEQ_CVC_MASK) -#define ADC16_TRIGMUX_EN_SEQ_CVC_GET(x) (((uint32_t)(x) & ADC16_TRIGMUX_EN_SEQ_CVC_MASK) >> ADC16_TRIGMUX_EN_SEQ_CVC_SHIFT) - -/* - * STOP_POS (RW) - * - */ -#define ADC16_TRIGMUX_EN_STOP_POS_MASK (0x100000UL) -#define ADC16_TRIGMUX_EN_STOP_POS_SHIFT (20U) -#define ADC16_TRIGMUX_EN_STOP_POS_SET(x) (((uint32_t)(x) << ADC16_TRIGMUX_EN_STOP_POS_SHIFT) & ADC16_TRIGMUX_EN_STOP_POS_MASK) -#define ADC16_TRIGMUX_EN_STOP_POS_GET(x) (((uint32_t)(x) & ADC16_TRIGMUX_EN_STOP_POS_MASK) >> ADC16_TRIGMUX_EN_STOP_POS_SHIFT) - -/* - * WDOG (RW) - * - */ -#define ADC16_TRIGMUX_EN_WDOG_MASK (0xFFFFU) -#define ADC16_TRIGMUX_EN_WDOG_SHIFT (0U) -#define ADC16_TRIGMUX_EN_WDOG_SET(x) (((uint32_t)(x) << ADC16_TRIGMUX_EN_WDOG_SHIFT) & ADC16_TRIGMUX_EN_WDOG_MASK) -#define ADC16_TRIGMUX_EN_WDOG_GET(x) (((uint32_t)(x) & ADC16_TRIGMUX_EN_WDOG_MASK) >> ADC16_TRIGMUX_EN_WDOG_SHIFT) - -/* Bitfield definition for register: TRG_CMPT_FLAG */ -/* - * TRG_CMPT_FLAG (RW1C) - * - */ -#define ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_MASK (0xFFFU) -#define ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_SHIFT (0U) -#define ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_SET(x) (((uint32_t)(x) << ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_SHIFT) & ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_MASK) -#define ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_GET(x) (((uint32_t)(x) & ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_MASK) >> ADC16_TRG_CMPT_FLAG_TRG_CMPT_FLAG_SHIFT) - -/* Bitfield definition for register: ANA_CTRL0 */ -/* - * MOTO_EN (RW) - * - * "set to enable moto_soc and moto_valid. - * Should use AHB clock for adc, this bit can be used avoid async output" - */ -#define ADC16_ANA_CTRL0_MOTO_EN_MASK (0x80000000UL) -#define ADC16_ANA_CTRL0_MOTO_EN_SHIFT (31U) -#define ADC16_ANA_CTRL0_MOTO_EN_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_MOTO_EN_SHIFT) & ADC16_ANA_CTRL0_MOTO_EN_MASK) -#define ADC16_ANA_CTRL0_MOTO_EN_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_MOTO_EN_MASK) >> ADC16_ANA_CTRL0_MOTO_EN_SHIFT) - -/* - * ADC_CLK_ON (RW) - * - * set to enable adc clock to analog, Software should set this bit before access to any adc16_* register. - * MUST set clock_period to 0 or 1 for adc16 reg access - */ -#define ADC16_ANA_CTRL0_ADC_CLK_ON_MASK (0x1000U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT (12U) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) -#define ADC16_ANA_CTRL0_ADC_CLK_ON_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_ADC_CLK_ON_MASK) >> ADC16_ANA_CTRL0_ADC_CLK_ON_SHIFT) - -/* - * STARTCAL (RW) - * - * set to start the offset calibration cycle (Active H). user need to clear it after setting it. - */ -#define ADC16_ANA_CTRL0_STARTCAL_MASK (0x4U) -#define ADC16_ANA_CTRL0_STARTCAL_SHIFT (2U) -#define ADC16_ANA_CTRL0_STARTCAL_SET(x) (((uint32_t)(x) << ADC16_ANA_CTRL0_STARTCAL_SHIFT) & ADC16_ANA_CTRL0_STARTCAL_MASK) -#define ADC16_ANA_CTRL0_STARTCAL_GET(x) (((uint32_t)(x) & ADC16_ANA_CTRL0_STARTCAL_MASK) >> ADC16_ANA_CTRL0_STARTCAL_SHIFT) - -/* Bitfield definition for register: ANA_STATUS */ -/* - * CALON (RW) - * - * Indicates if the ADC is in calibration mode (Active H). - */ -#define ADC16_ANA_STATUS_CALON_MASK (0x80U) -#define ADC16_ANA_STATUS_CALON_SHIFT (7U) -#define ADC16_ANA_STATUS_CALON_SET(x) (((uint32_t)(x) << ADC16_ANA_STATUS_CALON_SHIFT) & ADC16_ANA_STATUS_CALON_MASK) -#define ADC16_ANA_STATUS_CALON_GET(x) (((uint32_t)(x) & ADC16_ANA_STATUS_CALON_MASK) >> ADC16_ANA_STATUS_CALON_SHIFT) - -/* Bitfield definition for register array: ADC16_PARAMS */ -/* - * PARAM_VAL (RW) - * - */ -#define ADC16_ADC16_PARAMS_PARAM_VAL_MASK (0xFFFFU) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT (0U) -#define ADC16_ADC16_PARAMS_PARAM_VAL_SET(x) (((uint16_t)(x) << ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) -#define ADC16_ADC16_PARAMS_PARAM_VAL_GET(x) (((uint16_t)(x) & ADC16_ADC16_PARAMS_PARAM_VAL_MASK) >> ADC16_ADC16_PARAMS_PARAM_VAL_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG0 */ -/* - * REG_EN (RW) - * - * set to enable regulator - */ -#define ADC16_ADC16_CONFIG0_REG_EN_MASK (0x1000000UL) -#define ADC16_ADC16_CONFIG0_REG_EN_SHIFT (24U) -#define ADC16_ADC16_CONFIG0_REG_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_REG_EN_SHIFT) & ADC16_ADC16_CONFIG0_REG_EN_MASK) -#define ADC16_ADC16_CONFIG0_REG_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_REG_EN_MASK) >> ADC16_ADC16_CONFIG0_REG_EN_SHIFT) - -/* - * BANDGAP_EN (RW) - * - * set to enable bandgap. user should set reg_en and bandgap_en before use adc16. - */ -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK (0x800000UL) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT (23U) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) -#define ADC16_ADC16_CONFIG0_BANDGAP_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_BANDGAP_EN_MASK) >> ADC16_ADC16_CONFIG0_BANDGAP_EN_SHIFT) - -/* - * CAL_AVG_CFG (RW) - * - * for average the calibration result. - * 0- 1 loop; 1- 2 loops; 2- 4 loops; 3- 8 loops; - * 4- 16 loops; 5-32 loops; others reserved - */ -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK (0x700000UL) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT (20U) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) -#define ADC16_ADC16_CONFIG0_CAL_AVG_CFG_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CAL_AVG_CFG_MASK) >> ADC16_ADC16_CONFIG0_CAL_AVG_CFG_SHIFT) - -/* - * PREEMPT_EN (RW) - * - * set to enable preemption feature - */ -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK (0x4000U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT (14U) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) -#define ADC16_ADC16_CONFIG0_PREEMPT_EN_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_PREEMPT_EN_MASK) >> ADC16_ADC16_CONFIG0_PREEMPT_EN_SHIFT) - -/* - * CONV_PARAM (RW) - * - * conversion parameter - */ -#define ADC16_ADC16_CONFIG0_CONV_PARAM_MASK (0x3FFFU) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT (0U) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) -#define ADC16_ADC16_CONFIG0_CONV_PARAM_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG0_CONV_PARAM_MASK) >> ADC16_ADC16_CONFIG0_CONV_PARAM_SHIFT) - -/* Bitfield definition for register: ADC16_CONFIG1 */ -/* - * COV_END_CNT (RW) - * - * used for faster conversion, user can change it to get higher convert speed(but less accuracy). - * should set to (21-convert_clock_number+1). - */ -#define ADC16_ADC16_CONFIG1_COV_END_CNT_MASK (0x1F00U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT (8U) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_SET(x) (((uint32_t)(x) << ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) -#define ADC16_ADC16_CONFIG1_COV_END_CNT_GET(x) (((uint32_t)(x) & ADC16_ADC16_CONFIG1_COV_END_CNT_MASK) >> ADC16_ADC16_CONFIG1_COV_END_CNT_SHIFT) - - - -/* CONFIG register group index macro definition */ -#define ADC16_CONFIG_TRG0A (0UL) -#define ADC16_CONFIG_TRG0B (1UL) -#define ADC16_CONFIG_TRG0C (2UL) -#define ADC16_CONFIG_TRG1A (3UL) -#define ADC16_CONFIG_TRG1B (4UL) -#define ADC16_CONFIG_TRG1C (5UL) -#define ADC16_CONFIG_TRG2A (6UL) -#define ADC16_CONFIG_TRG2B (7UL) -#define ADC16_CONFIG_TRG2C (8UL) -#define ADC16_CONFIG_TRG3A (9UL) -#define ADC16_CONFIG_TRG3B (10UL) -#define ADC16_CONFIG_TRG3C (11UL) - -/* BUS_RESULT register group index macro definition */ -#define ADC16_BUS_RESULT_CHN0 (0UL) -#define ADC16_BUS_RESULT_CHN1 (1UL) -#define ADC16_BUS_RESULT_CHN2 (2UL) -#define ADC16_BUS_RESULT_CHN3 (3UL) -#define ADC16_BUS_RESULT_CHN4 (4UL) -#define ADC16_BUS_RESULT_CHN5 (5UL) -#define ADC16_BUS_RESULT_CHN6 (6UL) -#define ADC16_BUS_RESULT_CHN7 (7UL) -#define ADC16_BUS_RESULT_CHN8 (8UL) -#define ADC16_BUS_RESULT_CHN9 (9UL) -#define ADC16_BUS_RESULT_CHN10 (10UL) -#define ADC16_BUS_RESULT_CHN11 (11UL) -#define ADC16_BUS_RESULT_CHN12 (12UL) -#define ADC16_BUS_RESULT_CHN13 (13UL) -#define ADC16_BUS_RESULT_CHN14 (14UL) -#define ADC16_BUS_RESULT_CHN15 (15UL) - -/* SEQ_QUE register group index macro definition */ -#define ADC16_SEQ_QUE_CFG0 (0UL) -#define ADC16_SEQ_QUE_CFG1 (1UL) -#define ADC16_SEQ_QUE_CFG2 (2UL) -#define ADC16_SEQ_QUE_CFG3 (3UL) -#define ADC16_SEQ_QUE_CFG4 (4UL) -#define ADC16_SEQ_QUE_CFG5 (5UL) -#define ADC16_SEQ_QUE_CFG6 (6UL) -#define ADC16_SEQ_QUE_CFG7 (7UL) -#define ADC16_SEQ_QUE_CFG8 (8UL) -#define ADC16_SEQ_QUE_CFG9 (9UL) -#define ADC16_SEQ_QUE_CFG10 (10UL) -#define ADC16_SEQ_QUE_CFG11 (11UL) -#define ADC16_SEQ_QUE_CFG12 (12UL) -#define ADC16_SEQ_QUE_CFG13 (13UL) -#define ADC16_SEQ_QUE_CFG14 (14UL) -#define ADC16_SEQ_QUE_CFG15 (15UL) - -/* PRD_CFG register group index macro definition */ -#define ADC16_PRD_CFG_CHN0 (0UL) -#define ADC16_PRD_CFG_CHN1 (1UL) -#define ADC16_PRD_CFG_CHN2 (2UL) -#define ADC16_PRD_CFG_CHN3 (3UL) -#define ADC16_PRD_CFG_CHN4 (4UL) -#define ADC16_PRD_CFG_CHN5 (5UL) -#define ADC16_PRD_CFG_CHN6 (6UL) -#define ADC16_PRD_CFG_CHN7 (7UL) -#define ADC16_PRD_CFG_CHN8 (8UL) -#define ADC16_PRD_CFG_CHN9 (9UL) -#define ADC16_PRD_CFG_CHN10 (10UL) -#define ADC16_PRD_CFG_CHN11 (11UL) -#define ADC16_PRD_CFG_CHN12 (12UL) -#define ADC16_PRD_CFG_CHN13 (13UL) -#define ADC16_PRD_CFG_CHN14 (14UL) -#define ADC16_PRD_CFG_CHN15 (15UL) - -/* SAMPLE_CFG register group index macro definition */ -#define ADC16_SAMPLE_CFG_CHN0 (0UL) -#define ADC16_SAMPLE_CFG_CHN1 (1UL) -#define ADC16_SAMPLE_CFG_CHN2 (2UL) -#define ADC16_SAMPLE_CFG_CHN3 (3UL) -#define ADC16_SAMPLE_CFG_CHN4 (4UL) -#define ADC16_SAMPLE_CFG_CHN5 (5UL) -#define ADC16_SAMPLE_CFG_CHN6 (6UL) -#define ADC16_SAMPLE_CFG_CHN7 (7UL) -#define ADC16_SAMPLE_CFG_CHN8 (8UL) -#define ADC16_SAMPLE_CFG_CHN9 (9UL) -#define ADC16_SAMPLE_CFG_CHN10 (10UL) -#define ADC16_SAMPLE_CFG_CHN11 (11UL) -#define ADC16_SAMPLE_CFG_CHN12 (12UL) -#define ADC16_SAMPLE_CFG_CHN13 (13UL) -#define ADC16_SAMPLE_CFG_CHN14 (14UL) -#define ADC16_SAMPLE_CFG_CHN15 (15UL) - -/* ADC16_PARAMS register group index macro definition */ -#define ADC16_ADC16_PARAMS_ADC16_PARA00 (0UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA01 (1UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA02 (2UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA03 (3UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA04 (4UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA05 (5UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA06 (6UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA07 (7UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA08 (8UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA09 (9UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA10 (10UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA11 (11UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA12 (12UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA13 (13UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA14 (14UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA15 (15UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA16 (16UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA17 (17UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA18 (18UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA19 (19UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA20 (20UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA21 (21UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA22 (22UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA23 (23UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA24 (24UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA25 (25UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA26 (26UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA27 (27UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA28 (28UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA29 (29UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA30 (30UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA31 (31UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA32 (32UL) -#define ADC16_ADC16_PARAMS_ADC16_PARA33 (33UL) - - -#endif /* HPM_ADC16_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bacc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bacc_regs.h deleted file mode 100644 index 597f50ed16c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bacc_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BACC_H -#define HPM_BACC_H - -typedef struct { - __RW uint32_t CONFIG; /* 0x0: Access timing for access */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t PRE_TIME; /* 0x8: Timing gap before rising edge */ - __RW uint32_t POST_TIME; /* 0xC: Timing gap after rising edge */ -} BACC_Type; - - -/* Bitfield definition for register: CONFIG */ -/* - * FAST_WRITE (RW) - * - * Use fast write - * 0: Write normally - * 1: boost write - */ -#define BACC_CONFIG_FAST_WRITE_MASK (0x20000000UL) -#define BACC_CONFIG_FAST_WRITE_SHIFT (29U) -#define BACC_CONFIG_FAST_WRITE_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_WRITE_SHIFT) & BACC_CONFIG_FAST_WRITE_MASK) -#define BACC_CONFIG_FAST_WRITE_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_WRITE_MASK) >> BACC_CONFIG_FAST_WRITE_SHIFT) - -/* - * FAST_READ (RW) - * - * Use fast read - * 0: Read normally - * 1: boost read - */ -#define BACC_CONFIG_FAST_READ_MASK (0x10000000UL) -#define BACC_CONFIG_FAST_READ_SHIFT (28U) -#define BACC_CONFIG_FAST_READ_SET(x) (((uint32_t)(x) << BACC_CONFIG_FAST_READ_SHIFT) & BACC_CONFIG_FAST_READ_MASK) -#define BACC_CONFIG_FAST_READ_GET(x) (((uint32_t)(x) & BACC_CONFIG_FAST_READ_MASK) >> BACC_CONFIG_FAST_READ_SHIFT) - -/* - * TIMING (RW) - * - * Time in APB clock cycles, for battery timing penerate - */ -#define BACC_CONFIG_TIMING_MASK (0xFFFFU) -#define BACC_CONFIG_TIMING_SHIFT (0U) -#define BACC_CONFIG_TIMING_SET(x) (((uint32_t)(x) << BACC_CONFIG_TIMING_SHIFT) & BACC_CONFIG_TIMING_MASK) -#define BACC_CONFIG_TIMING_GET(x) (((uint32_t)(x) & BACC_CONFIG_TIMING_MASK) >> BACC_CONFIG_TIMING_SHIFT) - -/* Bitfield definition for register: PRE_TIME */ -/* - * PRE_RATIO (RW) - * - * Ratio of guard band before rising edge - * 0: 0 - * 1: 1/32768 of low level width - * 2: 1/16384 of low level width - * 14: 1/4 of low level width - * 15: 1/2 of low level width - */ -#define BACC_PRE_TIME_PRE_RATIO_MASK (0xF0000UL) -#define BACC_PRE_TIME_PRE_RATIO_SHIFT (16U) -#define BACC_PRE_TIME_PRE_RATIO_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_RATIO_SHIFT) & BACC_PRE_TIME_PRE_RATIO_MASK) -#define BACC_PRE_TIME_PRE_RATIO_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_RATIO_MASK) >> BACC_PRE_TIME_PRE_RATIO_SHIFT) - -/* - * PRE_OFFSET (RW) - * - * guard band before rising edge - * this value will be added to ratio number - */ -#define BACC_PRE_TIME_PRE_OFFSET_MASK (0xFFFFU) -#define BACC_PRE_TIME_PRE_OFFSET_SHIFT (0U) -#define BACC_PRE_TIME_PRE_OFFSET_SET(x) (((uint32_t)(x) << BACC_PRE_TIME_PRE_OFFSET_SHIFT) & BACC_PRE_TIME_PRE_OFFSET_MASK) -#define BACC_PRE_TIME_PRE_OFFSET_GET(x) (((uint32_t)(x) & BACC_PRE_TIME_PRE_OFFSET_MASK) >> BACC_PRE_TIME_PRE_OFFSET_SHIFT) - -/* Bitfield definition for register: POST_TIME */ -/* - * POST_RATIO (RW) - * - * Ratio of guard band after rising edge - * 0: 0 - * 1: 1/32768 of high level width - * 2: 1/16384 of high level width - * 14: 1/4 of high level width - * 15: 1/2 of high level width - */ -#define BACC_POST_TIME_POST_RATIO_MASK (0xF0000UL) -#define BACC_POST_TIME_POST_RATIO_SHIFT (16U) -#define BACC_POST_TIME_POST_RATIO_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_RATIO_SHIFT) & BACC_POST_TIME_POST_RATIO_MASK) -#define BACC_POST_TIME_POST_RATIO_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_RATIO_MASK) >> BACC_POST_TIME_POST_RATIO_SHIFT) - -/* - * POST_OFFSET (RW) - * - * guard band after rising edge - * this value will be added to ratio number - */ -#define BACC_POST_TIME_POST_OFFSET_MASK (0xFFFFU) -#define BACC_POST_TIME_POST_OFFSET_SHIFT (0U) -#define BACC_POST_TIME_POST_OFFSET_SET(x) (((uint32_t)(x) << BACC_POST_TIME_POST_OFFSET_SHIFT) & BACC_POST_TIME_POST_OFFSET_MASK) -#define BACC_POST_TIME_POST_OFFSET_GET(x) (((uint32_t)(x) & BACC_POST_TIME_POST_OFFSET_MASK) >> BACC_POST_TIME_POST_OFFSET_SHIFT) - - - - -#endif /* HPM_BACC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bcfg_regs.h deleted file mode 100644 index 059283c4cee..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bcfg_regs.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BCFG_H -#define HPM_BCFG_H - -typedef struct { - __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */ - __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */ - __RW uint32_t CLK_CFG; /* 0x10: Clock config */ -} BCFG_Type; - - -/* Bitfield definition for register: VBG_CFG */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL) -#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U) -#define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) -#define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) - -/* - * POWER_SAVE (RW) - * - * Bandgap works in power save mode - * 0: not in power save mode - * 1: bandgap work in power save mode - */ -#define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL) -#define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U) -#define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK) -#define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT) - -/* - * VBG_1P0 (RW) - * - * Bandgap 1.0V output trim - */ -#define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL) -#define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U) -#define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK) -#define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT) - -/* - * VBG_P65 (RW) - * - * Bandgap 0.65V output trim - */ -#define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U) -#define BCFG_VBG_CFG_VBG_P65_SHIFT (8U) -#define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK) -#define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT) - -/* - * VBG_P50 (RW) - * - * Bandgap 0.50V output trim - */ -#define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU) -#define BCFG_VBG_CFG_VBG_P50_SHIFT (0U) -#define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK) -#define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT) - -/* Bitfield definition for register: IRC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) -#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U) -#define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) -#define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: XTAL32K_CFG */ -/* - * HYST_EN (RW) - * - * crystal 32k hysteres enable - */ -#define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U) -#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U) -#define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK) -#define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT) - -/* - * GMSEL (RW) - * - * crystal 32k gm selection - */ -#define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U) -#define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U) -#define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK) -#define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT) - -/* - * CFG (RW) - * - * crystal 32k config - */ -#define BCFG_XTAL32K_CFG_CFG_MASK (0x10U) -#define BCFG_XTAL32K_CFG_CFG_SHIFT (4U) -#define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK) -#define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT) - -/* - * AMP (RW) - * - * crystal 32k amplifier - */ -#define BCFG_XTAL32K_CFG_AMP_MASK (0x3U) -#define BCFG_XTAL32K_CFG_AMP_SHIFT (0U) -#define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK) -#define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT) - -/* Bitfield definition for register: CLK_CFG */ -/* - * XTAL_SEL (RO) - * - * crystal selected - */ -#define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL) -#define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U) -#define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT) - -/* - * KEEP_IRC (RW) - * - * force irc32k run - */ -#define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL) -#define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U) -#define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK) -#define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT) - -/* - * FORCE_XTAL (RW) - * - * force switch to crystal - */ -#define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U) -#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U) -#define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK) -#define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT) - - - - -#endif /* HPM_BCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bgpr_regs.h deleted file mode 100644 index 0d15f92db3b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bgpr_regs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BGPR_H -#define HPM_BGPR_H - -typedef struct { - __RW uint32_t GPR[16]; /* 0x0 - 0x3C: Generic control */ -} BGPR_Type; - - -/* Bitfield definition for register array: GPR */ -/* - * DATA (RW) - * - * Generic control - */ -#define BGPR_GPR_DATA_MASK (0xFFFFFFFFUL) -#define BGPR_GPR_DATA_SHIFT (0U) -#define BGPR_GPR_DATA_SET(x) (((uint32_t)(x) << BGPR_GPR_DATA_SHIFT) & BGPR_GPR_DATA_MASK) -#define BGPR_GPR_DATA_GET(x) (((uint32_t)(x) & BGPR_GPR_DATA_MASK) >> BGPR_GPR_DATA_SHIFT) - - - -/* GPR register group index macro definition */ -#define BGPR_GPR_0 (0UL) -#define BGPR_GPR_1 (1UL) -#define BGPR_GPR_2 (2UL) -#define BGPR_GPR_3 (3UL) -#define BGPR_GPR_4 (4UL) -#define BGPR_GPR_5 (5UL) -#define BGPR_GPR_6 (6UL) -#define BGPR_GPR_7 (7UL) -#define BGPR_GPR_8 (8UL) -#define BGPR_GPR_9 (9UL) -#define BGPR_GPR_10 (10UL) -#define BGPR_GPR_11 (11UL) -#define BGPR_GPR_12 (12UL) -#define BGPR_GPR_13 (13UL) -#define BGPR_GPR_14 (14UL) -#define BGPR_GPR_15 (15UL) - - -#endif /* HPM_BGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bkey_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bkey_regs.h deleted file mode 100644 index 1c82a4b90e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bkey_regs.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BKEY_H -#define HPM_BKEY_H - -typedef struct { - struct { - __RW uint32_t DATA[8]; /* 0x0 - 0x1C: Key data */ - } KEY[2]; - __RW uint32_t ECC[2]; /* 0x40 - 0x44: Key ECC and access control */ - __RW uint32_t SELECT; /* 0x48: Key selection */ -} BKEY_Type; - - -/* Bitfield definition for register of struct array KEY: 0 */ -/* - * DATA (RW) - * - * security key data - */ -#define BKEY_KEY_DATA_DATA_MASK (0xFFFFFFFFUL) -#define BKEY_KEY_DATA_DATA_SHIFT (0U) -#define BKEY_KEY_DATA_DATA_SET(x) (((uint32_t)(x) << BKEY_KEY_DATA_DATA_SHIFT) & BKEY_KEY_DATA_DATA_MASK) -#define BKEY_KEY_DATA_DATA_GET(x) (((uint32_t)(x) & BKEY_KEY_DATA_DATA_MASK) >> BKEY_KEY_DATA_DATA_SHIFT) - -/* Bitfield definition for register array: ECC */ -/* - * WLOCK (RW) - * - * write lock to key0 - * 0: write enable - * 1: write ignored - */ -#define BKEY_ECC_WLOCK_MASK (0x80000000UL) -#define BKEY_ECC_WLOCK_SHIFT (31U) -#define BKEY_ECC_WLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_WLOCK_SHIFT) & BKEY_ECC_WLOCK_MASK) -#define BKEY_ECC_WLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_WLOCK_MASK) >> BKEY_ECC_WLOCK_SHIFT) - -/* - * RLOCK (RW) - * - * read lock to key0 - * 0: key read enable - * 1: key always read as 0 - */ -#define BKEY_ECC_RLOCK_MASK (0x40000000UL) -#define BKEY_ECC_RLOCK_SHIFT (30U) -#define BKEY_ECC_RLOCK_SET(x) (((uint32_t)(x) << BKEY_ECC_RLOCK_SHIFT) & BKEY_ECC_RLOCK_MASK) -#define BKEY_ECC_RLOCK_GET(x) (((uint32_t)(x) & BKEY_ECC_RLOCK_MASK) >> BKEY_ECC_RLOCK_SHIFT) - -/* - * ECC (RW) - * - * Parity check bits for key0 - */ -#define BKEY_ECC_ECC_MASK (0xFFFFU) -#define BKEY_ECC_ECC_SHIFT (0U) -#define BKEY_ECC_ECC_SET(x) (((uint32_t)(x) << BKEY_ECC_ECC_SHIFT) & BKEY_ECC_ECC_MASK) -#define BKEY_ECC_ECC_GET(x) (((uint32_t)(x) & BKEY_ECC_ECC_MASK) >> BKEY_ECC_ECC_SHIFT) - -/* Bitfield definition for register: SELECT */ -/* - * SELECT (RW) - * - * select key, key0 treated as secure key, in non-scure mode, only key1 can be selected - * 0: select key0 in secure mode, key1 in non-secure mode - * 1: select key1 in secure or nonsecure mode - */ -#define BKEY_SELECT_SELECT_MASK (0x1U) -#define BKEY_SELECT_SELECT_SHIFT (0U) -#define BKEY_SELECT_SELECT_SET(x) (((uint32_t)(x) << BKEY_SELECT_SELECT_SHIFT) & BKEY_SELECT_SELECT_MASK) -#define BKEY_SELECT_SELECT_GET(x) (((uint32_t)(x) & BKEY_SELECT_SELECT_MASK) >> BKEY_SELECT_SELECT_SHIFT) - - - -/* DATA register group index macro definition */ -#define BKEY_KEY_DATA_0 (0UL) -#define BKEY_KEY_DATA_1 (1UL) -#define BKEY_KEY_DATA_2 (2UL) -#define BKEY_KEY_DATA_3 (3UL) -#define BKEY_KEY_DATA_4 (4UL) -#define BKEY_KEY_DATA_5 (5UL) -#define BKEY_KEY_DATA_6 (6UL) -#define BKEY_KEY_DATA_7 (7UL) - -/* KEY register group index macro definition */ -#define BKEY_KEY_0 (0UL) -#define BKEY_KEY_1 (1UL) - -/* ECC register group index macro definition */ -#define BKEY_ECC_KEY0 (0UL) -#define BKEY_ECC_KEY1 (1UL) - - -#endif /* HPM_BKEY_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bmon_regs.h deleted file mode 100644 index f297a1dbb93..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bmon_regs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BMON_H -#define HPM_BMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - __R uint8_t RESERVED0[8]; /* 0x8 - 0xF: Reserved */ - } MONITOR[2]; -} BMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define BMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define BMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define BMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ACTIVE_SHIFT) & BMON_MONITOR_CONTROL_ACTIVE_MASK) -#define BMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ACTIVE_MASK) >> BMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define BMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define BMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define BMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << BMON_MONITOR_CONTROL_ENABLE_SHIFT) & BMON_MONITOR_CONTROL_ENABLE_MASK) -#define BMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & BMON_MONITOR_CONTROL_ENABLE_MASK) >> BMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define BMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define BMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define BMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << BMON_MONITOR_STATUS_FLAG_SHIFT) & BMON_MONITOR_STATUS_FLAG_MASK) -#define BMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & BMON_MONITOR_STATUS_FLAG_MASK) >> BMON_MONITOR_STATUS_FLAG_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define BMON_MONITOR_GLITCH0 (0UL) -#define BMON_MONITOR_CLOCK0 (1UL) - - -#endif /* HPM_BMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bpor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bpor_regs.h deleted file mode 100644 index 8d0c023fdb9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bpor_regs.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BPOR_H -#define HPM_BPOR_H - -typedef struct { - __RW uint32_t POR_CONFIG; /* 0x0: Power on reset config */ -} BPOR_Type; - - -/* Bitfield definition for register: POR_CONFIG */ -/* - * RETENTION (RW) - * - * retention battery domain setting - * 0: battery reset on reset pin reset happen - * 1: battery domain retention when reset pin reset happen - */ -#define BPOR_POR_CONFIG_RETENTION_MASK (0x1U) -#define BPOR_POR_CONFIG_RETENTION_SHIFT (0U) -#define BPOR_POR_CONFIG_RETENTION_SET(x) (((uint32_t)(x) << BPOR_POR_CONFIG_RETENTION_SHIFT) & BPOR_POR_CONFIG_RETENTION_MASK) -#define BPOR_POR_CONFIG_RETENTION_GET(x) (((uint32_t)(x) & BPOR_POR_CONFIG_RETENTION_MASK) >> BPOR_POR_CONFIG_RETENTION_SHIFT) - - - - -#endif /* HPM_BPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bsec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bsec_regs.h deleted file mode 100644 index 6167b47be78..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_bsec_regs.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_BSEC_H -#define HPM_BSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ -} BSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * BATT_FAIL (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U) -#define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U) -#define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK) -#define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT) - -/* - * BATT_NSC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U) -#define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U) -#define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK) -#define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT) - -/* - * BATT_SEC (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U) -#define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U) -#define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK) -#define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT) - -/* - * BATT_INS (RW) - * - * BATT secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U) -#define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U) -#define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK) -#define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored - */ -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define BSEC_EVENT_EVENT_SHIFT (16U) -#define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT) - -/* - * BATT_ESC_NSC (RO) - * - * BATT is escalating non-secure event - */ -#define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U) -#define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U) -#define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT) - -/* - * BATT_ESC_SEC (RO) - * - * BATT is escalting ssecure event - */ -#define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U) -#define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U) -#define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT) - - - - -#endif /* HPM_BSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_clc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_clc_regs.h deleted file mode 100644 index d2e74dac393..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_clc_regs.h +++ /dev/null @@ -1,507 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CLC_H -#define HPM_CLC_H - -typedef struct { - struct { - __RW uint32_t MODE; /* 0x0: mode ctrl */ - __RW uint32_t ADC_EXPECT; /* 0x4: adc expect */ - __RW uint32_t ADC_CHAN; /* 0x8: adc used channel */ - __RW uint32_t ADC_OFFSET; /* 0xC: adc used offset */ - __RW uint32_t EADC_LOWTH; /* 0x10: eadc_lowth value used in error adc cofficient selection */ - __RW uint32_t EADC_HIGHTH; /* 0x14: eadc_highth value used in error adc cofficient selection */ - __RW uint32_t EADC_MIDLOWTH; /* 0x18: eadc_midlowth value used in error adc cofficient selection */ - __RW uint32_t EADC_MIDHIGHTH; /* 0x1C: eadc_midhighth value used in error adc cofficient selection */ - __RW uint32_t P2Z2_CLAMP_LO; /* 0x20: 2p2z output clamp low threshold */ - __RW uint32_t P2Z2_CLAMP_HI; /* 0x24: 2p2z output clamp high threshold */ - __RW uint32_t P3Z3_CLAMP_LO; /* 0x28: 3p3z output clamp low threshold */ - __RW uint32_t P3Z3_CLAMP_HI; /* 0x2C: 3p3z output clamp high threshold */ - __R uint8_t RESERVED0[16]; /* 0x30 - 0x3F: Reserved */ - struct { - __RW uint32_t COEFF_B0; /* 0x40: zone b0 */ - __RW uint32_t COEFF_B1; /* 0x44: zone b1 */ - __RW uint32_t COEFF_B2; /* 0x48: zone b2 */ - __RW uint32_t COEFF_B3; /* 0x4C: zone b3 */ - __RW uint32_t COEFF_A0; /* 0x50: zone a0 */ - __RW uint32_t COEFF_A1; /* 0x54: zone a1 */ - __RW uint32_t COEFF_A2; /* 0x58: zone a2 */ - __RW uint32_t COEFF_KS; /* 0x5C: zone kscaling */ - } COEFF[3]; - __RW uint32_t PWM_PERIOD; /* 0xA0: pwm_period */ - __R uint32_t OUTPUT_VALUE; /* 0xA4: output value */ - __R uint32_t TIMESTAMP; /* 0xA8: adc timestamp used */ - __RW uint32_t EADC_CURR; /* 0xAC: error adc latest value */ - __RW uint32_t EADC_PRE0; /* 0xB0: error adc previous0 value */ - __RW uint32_t EADC_PRE1; /* 0xB4: error adc previous1 value */ - __RW uint32_t P2Z2_CURR; /* 0xB8: 2p2z latest value */ - __RW uint32_t P2Z2_PRE0; /* 0xBC: 2p2z previous0 value */ - __R uint8_t RESERVED1[4]; /* 0xC0 - 0xC3: Reserved */ - __RW uint32_t P3Z3_CURR; /* 0xC4: 3p3z latest value */ - __R uint8_t RESERVED2[4]; /* 0xC8 - 0xCB: Reserved */ - __RW uint32_t P3Z3_FORBID_LO; /* 0xCC: 3p3z output forbid low threshold */ - __RW uint32_t P3Z3_FORBID_MD; /* 0xD0: 3p3z output forbid middle threshold */ - __RW uint32_t P3Z3_FORBID_HI; /* 0xD4: 3p3z output forbid high threshold */ - __R uint8_t RESERVED3[8]; /* 0xD8 - 0xDF: Reserved */ - __RW uint32_t ADC_SW; /* 0xE0: adc software inject value */ - __R uint8_t RESERVED4[24]; /* 0xE4 - 0xFB: Reserved */ - __W uint32_t STATUS; /* 0xFC: irq_status */ - } VDVQ_CHAN[2]; - __W uint32_t DQ_ADC_SW_READY; /* 0x200: enable d/q chan software inject adc value */ -} CLC_Type; - - -/* Bitfield definition for register of struct array VDVQ_CHAN: MODE */ -/* - * ENABLE_CLC (RW) - * - * enable CLC - */ -#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK (0x80000000UL) -#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT (31U) -#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK) -#define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT) - -/* - * MASK_MODE (RW) - * - * open mode: CLC keep working even if bad irq status ocurred - */ -#define CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK (0x1000000UL) -#define CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT (24U) -#define CLC_VDVQ_CHAN_MODE_MASK_MODE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK) -#define CLC_VDVQ_CHAN_MODE_MASK_MODE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT) - -/* - * DQ_MODE (RW) - * - * dq mode - */ -#define CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK (0x10000UL) -#define CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT (16U) -#define CLC_VDVQ_CHAN_MODE_DQ_MODE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK) -#define CLC_VDVQ_CHAN_MODE_DQ_MODE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT) - -/* - * ENABLE_IRQ (RW) - * - * enable irq: - * irq_data_in_forbid , // 10 - * irq_forb_err_boundary , // 9 - * irq_p3z3_over_lo , // 8 - * irq_p3z3_over_hi , // 7 - * irq_p3z3_err_boundary , // 6 - * irq_z2_over_sf , // 5 - * irq_z2_over_lo , // 4 - * irq_z2_over_hi , // 3 - * irq_z2_err_boundary , // 2 - * irq_coef_err_boundary , // 1 - * irq_valid_clc // 0 - */ -#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK (0x7FFU) -#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT (0U) -#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK) -#define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: ADC_EXPECT */ -/* - * ADC_EXPECT (RW) - * - * adc expect value - */ -#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT (0U) -#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK) -#define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK) >> CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: ADC_CHAN */ -/* - * ADC_CHAN (RW) - * - * adc used chan ID - */ -#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK (0x1FU) -#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT (0U) -#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK) -#define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK) >> CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: ADC_OFFSET */ -/* - * ADC_OFFSET (RW) - * - * adc used offset - */ -#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT (0U) -#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK) -#define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK) >> CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_LOWTH */ -/* - * EADC_LOWTH (RW) - * - * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - */ -#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK) -#define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_HIGHTH */ -/* - * EADC_HIGHTH (RW) - * - * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - */ -#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK) -#define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_MIDLOWTH */ -/* - * EADC_MIDLOWTH (RW) - * - * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - */ -#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK) -#define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_MIDHIGHTH */ -/* - * EADC_MIDHIGHTH (RW) - * - * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient - */ -#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK) -#define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CLAMP_LO */ -/* - * 2P2Z_CLAMP_LO (RW) - * - * 2p2z output clamp low threshold - */ -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT (0U) -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK) -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CLAMP_HI */ -/* - * 2P2Z_CLAMP_HI (RW) - * - * 2p2z output clamp high threshold - */ -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT (0U) -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK) -#define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CLAMP_LO */ -/* - * 3P3Z_CLAMP_LO (RW) - * - * 3p3z output clamp low threshold - */ -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT (0U) -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK) -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CLAMP_HI */ -/* - * 3P3Z_CLAMP_HI (RW) - * - * 3p3z output clamp high threshold - */ -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT (0U) -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK) -#define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B0 */ -/* - * COEFF_B0 (RW) - * - * coefficient b0 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B1 */ -/* - * COEFF_B1 (RW) - * - * coefficient b1 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B2 */ -/* - * COEFF_B2 (RW) - * - * coefficient b2 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B3 */ -/* - * COEFF_B3 (RW) - * - * coefficient b3 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A0 */ -/* - * COEFF_A0 (RW) - * - * coefficient a0 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A1 */ -/* - * COEFF_A1 (RW) - * - * coefficient a1 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A2 */ -/* - * COEFF_A2 (RW) - * - * coefficient a2 - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_KS */ -/* - * COEFF_KSCALING (RW) - * - * coefficient kscaling - */ -#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK (0x1FU) -#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT (0U) -#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK) -#define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: PWM_PERIOD */ -/* - * PWM_PERIOD (RW) - * - * pwm_period - */ -#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT (0U) -#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK) -#define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK) >> CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: OUTPUT_VALUE */ -/* - * OUTPUT_VALUE (RO) - * - * output_value - */ -#define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT (0U) -#define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK) >> CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: TIMESTAMP */ -/* - * TIMESTAMP (RO) - * - * timestamp - */ -#define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK) >> CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_CURR */ -/* - * EADC_CURR (RW) - * - * error adc latest value - */ -#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK) -#define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK) >> CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_PRE0 */ -/* - * EADC_PRE0 (RW) - * - * error adc previous 0 value - */ -#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK) -#define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK) >> CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: EADC_PRE1 */ -/* - * EADC_PRE1 (RW) - * - * error adc previous 1 value - */ -#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT (0U) -#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK) -#define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK) >> CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CURR */ -/* - * 2P2Z_CURR (RW) - * - * 2p2z latest value - */ -#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT (0U) -#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK) -#define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK) >> CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_PRE0 */ -/* - * 2P2Z_PRE0 (RW) - * - * 2p2z previous 0 value - */ -#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT (0U) -#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK) -#define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK) >> CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CURR */ -/* - * 3P3Z_CURR (RW) - * - * 3p3z latest value - */ -#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT (0U) -#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK) -#define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK) >> CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_LO */ -/* - * 3P3Z_FORBID_LO (RW) - * - * 3p3z output forbid low threshold - */ -#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT (0U) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_MD */ -/* - * 3P3Z_FORBID_MD (RW) - * - * 3p3z output forbid middle threshold - */ -#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT (0U) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_HI */ -/* - * 3P3Z_FORBID_HI (RW) - * - * 3p3z output forbid high threshold - */ -#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT (0U) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK) -#define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: ADC_SW */ -/* - * ADC_SW (RW) - * - * adc software inject value - */ -#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK (0xFFFFFFFFUL) -#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT (0U) -#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK) -#define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK) >> CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT) - -/* Bitfield definition for register of struct array VDVQ_CHAN: STATUS */ -/* - * STATUS (W1C) - * - * status, write 1 to clear it. : - * irq_data_in_forbid , // 10 - * irq_forb_err_boundary , // 9 - * irq_p3z3_over_lo , // 8 - * irq_p3z3_over_hi , // 7 - * irq_p3z3_err_boundary , // 6 - * irq_z2_over_sf , // 5 - * irq_z2_over_lo , // 4 - * irq_z2_over_hi , // 3 - * irq_z2_err_boundary , // 2 - * irq_coef_err_boundary , // 1 - * irq_valid_clc // 0 - */ -#define CLC_VDVQ_CHAN_STATUS_STATUS_MASK (0x7FFU) -#define CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT (0U) -#define CLC_VDVQ_CHAN_STATUS_STATUS_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK) -#define CLC_VDVQ_CHAN_STATUS_STATUS_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK) >> CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: DQ_ADC_SW_READY */ -/* - * DQ_ADC_SW_READY (W1C) - * - * enable d/q chan software inject adc value - */ -#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK (0x1U) -#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT (0U) -#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SET(x) (((uint32_t)(x) << CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK) -#define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_GET(x) (((uint32_t)(x) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK) >> CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT) - - - -/* COEFF register group index macro definition */ -#define CLC_COEFF_0 (0UL) -#define CLC_COEFF_1 (1UL) -#define CLC_COEFF_2 (2UL) - -/* VDVQ_CHAN register group index macro definition */ -#define CLC_VDVQ_CHAN_VD (0UL) -#define CLC_VDVQ_CHAN_VQ (1UL) - - -#endif /* HPM_CLC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_crc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_crc_regs.h deleted file mode 100644 index 7c06d3e0e4c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_crc_regs.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_CRC_H -#define HPM_CRC_H - -typedef struct { - struct { - __RW uint32_t PRE_SET; /* 0x0: pre set for crc setting */ - __RW uint32_t CLR; /* 0x4: chn clear crc result and setting */ - __RW uint32_t POLY; /* 0x8: chn poly */ - __RW uint32_t INIT_DATA; /* 0xC: chn init_data */ - __RW uint32_t XOROUT; /* 0x10: chn xorout */ - __RW uint32_t MISC_SETTING; /* 0x14: chn misc_setting */ - __RW uint32_t DATA; /* 0x18: chn data */ - __RW uint32_t RESULT; /* 0x1C: chn result */ - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - } CHN[8]; -} CRC_Type; - - -/* Bitfield definition for register of struct array CHN: PRE_SET */ -/* - * PRE_SET (RW) - * - * 0: no pre set - * 1: CRC32 - * 2: CRC32-AUTOSAR - * 3: CRC16-CCITT - * 4: CRC16-XMODEM - * 5: CRC16-MODBUS - * 1: CRC32 - * 2: CRC32-autosar - * 3: CRC16-ccitt - * 4: CRC16-xmodem - * 5: CRC16-modbus - * 6: crc16_dnp - * 7: crc16_x25 - * 8: crc16_usb - * 9: crc16_maxim - * 10: crc16_ibm - * 11: crc8_maxim - * 12: crc8_rohc - * 13: crc8_itu - * 14: crc8 - * 15: crc5_usb - */ -#define CRC_CHN_PRE_SET_PRE_SET_MASK (0xFFU) -#define CRC_CHN_PRE_SET_PRE_SET_SHIFT (0U) -#define CRC_CHN_PRE_SET_PRE_SET_SET(x) (((uint32_t)(x) << CRC_CHN_PRE_SET_PRE_SET_SHIFT) & CRC_CHN_PRE_SET_PRE_SET_MASK) -#define CRC_CHN_PRE_SET_PRE_SET_GET(x) (((uint32_t)(x) & CRC_CHN_PRE_SET_PRE_SET_MASK) >> CRC_CHN_PRE_SET_PRE_SET_SHIFT) - -/* Bitfield definition for register of struct array CHN: CLR */ -/* - * CLR (RW) - * - * write 1 to clr crc setting and result for its channel. - * always read 0. - */ -#define CRC_CHN_CLR_CLR_MASK (0x1U) -#define CRC_CHN_CLR_CLR_SHIFT (0U) -#define CRC_CHN_CLR_CLR_SET(x) (((uint32_t)(x) << CRC_CHN_CLR_CLR_SHIFT) & CRC_CHN_CLR_CLR_MASK) -#define CRC_CHN_CLR_CLR_GET(x) (((uint32_t)(x) & CRC_CHN_CLR_CLR_MASK) >> CRC_CHN_CLR_CLR_SHIFT) - -/* Bitfield definition for register of struct array CHN: POLY */ -/* - * POLY (RW) - * - * poly setting - */ -#define CRC_CHN_POLY_POLY_MASK (0xFFFFFFFFUL) -#define CRC_CHN_POLY_POLY_SHIFT (0U) -#define CRC_CHN_POLY_POLY_SET(x) (((uint32_t)(x) << CRC_CHN_POLY_POLY_SHIFT) & CRC_CHN_POLY_POLY_MASK) -#define CRC_CHN_POLY_POLY_GET(x) (((uint32_t)(x) & CRC_CHN_POLY_POLY_MASK) >> CRC_CHN_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array CHN: INIT_DATA */ -/* - * INIT_DATA (RW) - * - * initial data of CRC - */ -#define CRC_CHN_INIT_DATA_INIT_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_INIT_DATA_INIT_DATA_SHIFT (0U) -#define CRC_CHN_INIT_DATA_INIT_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) -#define CRC_CHN_INIT_DATA_INIT_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_INIT_DATA_INIT_DATA_MASK) >> CRC_CHN_INIT_DATA_INIT_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: XOROUT */ -/* - * XOROUT (RW) - * - * XOR for CRC result - */ -#define CRC_CHN_XOROUT_XOROUT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_XOROUT_XOROUT_SHIFT (0U) -#define CRC_CHN_XOROUT_XOROUT_SET(x) (((uint32_t)(x) << CRC_CHN_XOROUT_XOROUT_SHIFT) & CRC_CHN_XOROUT_XOROUT_MASK) -#define CRC_CHN_XOROUT_XOROUT_GET(x) (((uint32_t)(x) & CRC_CHN_XOROUT_XOROUT_MASK) >> CRC_CHN_XOROUT_XOROUT_SHIFT) - -/* Bitfield definition for register of struct array CHN: MISC_SETTING */ -/* - * BYTE_REV (RW) - * - * 0: no wrap input byte order - * 1: wrap input byte order - */ -#define CRC_CHN_MISC_SETTING_BYTE_REV_MASK (0x1000000UL) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT (24U) -#define CRC_CHN_MISC_SETTING_BYTE_REV_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) -#define CRC_CHN_MISC_SETTING_BYTE_REV_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_BYTE_REV_MASK) >> CRC_CHN_MISC_SETTING_BYTE_REV_SHIFT) - -/* - * REV_OUT (RW) - * - * 0: no wrap output bit order - * 1: wrap output bit order - */ -#define CRC_CHN_MISC_SETTING_REV_OUT_MASK (0x10000UL) -#define CRC_CHN_MISC_SETTING_REV_OUT_SHIFT (16U) -#define CRC_CHN_MISC_SETTING_REV_OUT_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) -#define CRC_CHN_MISC_SETTING_REV_OUT_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_OUT_MASK) >> CRC_CHN_MISC_SETTING_REV_OUT_SHIFT) - -/* - * REV_IN (RW) - * - * 0: no wrap input bit order - * 1: wrap input bit order - */ -#define CRC_CHN_MISC_SETTING_REV_IN_MASK (0x100U) -#define CRC_CHN_MISC_SETTING_REV_IN_SHIFT (8U) -#define CRC_CHN_MISC_SETTING_REV_IN_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_REV_IN_SHIFT) & CRC_CHN_MISC_SETTING_REV_IN_MASK) -#define CRC_CHN_MISC_SETTING_REV_IN_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_REV_IN_MASK) >> CRC_CHN_MISC_SETTING_REV_IN_SHIFT) - -/* - * POLY_WIDTH (RW) - * - * crc data length - */ -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK (0x3FU) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT (0U) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_SET(x) (((uint32_t)(x) << CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) -#define CRC_CHN_MISC_SETTING_POLY_WIDTH_GET(x) (((uint32_t)(x) & CRC_CHN_MISC_SETTING_POLY_WIDTH_MASK) >> CRC_CHN_MISC_SETTING_POLY_WIDTH_SHIFT) - -/* Bitfield definition for register of struct array CHN: DATA */ -/* - * DATA (RW) - * - * data for crc - */ -#define CRC_CHN_DATA_DATA_MASK (0xFFFFFFFFUL) -#define CRC_CHN_DATA_DATA_SHIFT (0U) -#define CRC_CHN_DATA_DATA_SET(x) (((uint32_t)(x) << CRC_CHN_DATA_DATA_SHIFT) & CRC_CHN_DATA_DATA_MASK) -#define CRC_CHN_DATA_DATA_GET(x) (((uint32_t)(x) & CRC_CHN_DATA_DATA_MASK) >> CRC_CHN_DATA_DATA_SHIFT) - -/* Bitfield definition for register of struct array CHN: RESULT */ -/* - * RESULT (RW) - * - * crc result - */ -#define CRC_CHN_RESULT_RESULT_MASK (0xFFFFFFFFUL) -#define CRC_CHN_RESULT_RESULT_SHIFT (0U) -#define CRC_CHN_RESULT_RESULT_SET(x) (((uint32_t)(x) << CRC_CHN_RESULT_RESULT_SHIFT) & CRC_CHN_RESULT_RESULT_MASK) -#define CRC_CHN_RESULT_RESULT_GET(x) (((uint32_t)(x) & CRC_CHN_RESULT_RESULT_MASK) >> CRC_CHN_RESULT_RESULT_SHIFT) - - - -/* CHN register group index macro definition */ -#define CRC_CHN_0 (0UL) -#define CRC_CHN_1 (1UL) -#define CRC_CHN_2 (2UL) -#define CRC_CHN_3 (3UL) -#define CRC_CHN_4 (4UL) -#define CRC_CHN_5 (5UL) -#define CRC_CHN_6 (6UL) -#define CRC_CHN_7 (7UL) - - -#endif /* HPM_CRC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dao_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dao_regs.h deleted file mode 100644 index a0bdf2f15d1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dao_regs.h +++ /dev/null @@ -1,250 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DAO_H -#define HPM_DAO_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ - __RW uint32_t CMD; /* 0x8: Command Register */ - __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ - __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ - __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ -} DAO_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * HPF_EN (RW) - * - * Whether HPF is enabled. This HPF is used to filter out the DC part. - */ -#define DAO_CTRL_HPF_EN_MASK (0x20000UL) -#define DAO_CTRL_HPF_EN_SHIFT (17U) -#define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) -#define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) - -/* - * MONO (RW) - * - * Asserted to let the left and right channel output the same value. - */ -#define DAO_CTRL_MONO_MASK (0x80U) -#define DAO_CTRL_MONO_SHIFT (7U) -#define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) -#define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) - -/* - * RIGHT_EN (RW) - * - * Asserted to enable the right channel - */ -#define DAO_CTRL_RIGHT_EN_MASK (0x40U) -#define DAO_CTRL_RIGHT_EN_SHIFT (6U) -#define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) -#define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) - -/* - * LEFT_EN (RW) - * - * Asserted to enable the left channel - */ -#define DAO_CTRL_LEFT_EN_MASK (0x20U) -#define DAO_CTRL_LEFT_EN_SHIFT (5U) -#define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) -#define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) - -/* - * REMAP (RW) - * - * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative - * 0: Don't use remap pwm version - */ -#define DAO_CTRL_REMAP_MASK (0x10U) -#define DAO_CTRL_REMAP_SHIFT (4U) -#define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) -#define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) - -/* - * INVERT (RW) - * - * all the outputs are inverted before sending to pad - */ -#define DAO_CTRL_INVERT_MASK (0x8U) -#define DAO_CTRL_INVERT_SHIFT (3U) -#define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) -#define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) - -/* - * FALSE_LEVEL (RW) - * - * the pad output in False run mode, or when the module is disabled - * 0: all low - * 1: all high - * 2: P-high, N-low - * 3. output is not enabled - */ -#define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) -#define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) -#define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) -#define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) - -/* - * FALSE_RUN (RW) - * - * the module continues to consume data, but all the pads are constant, thus no audio out - */ -#define DAO_CTRL_FALSE_RUN_MASK (0x1U) -#define DAO_CTRL_FALSE_RUN_SHIFT (0U) -#define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) -#define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Self-clear - */ -#define DAO_CMD_SFTRST_MASK (0x2U) -#define DAO_CMD_SFTRST_SHIFT (1U) -#define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) -#define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) - -/* - * RUN (RW) - * - * Enable this module to run. - */ -#define DAO_CMD_RUN_MASK (0x1U) -#define DAO_CMD_RUN_SHIFT (0U) -#define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) -#define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) - -/* Bitfield definition for register: RX_CFGR */ -/* - * FRAME_EDGE (RW) - * - * The start edge of a frame - * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) - * 1: Rising edge indicates a new frame - */ -#define DAO_RX_CFGR_FRAME_EDGE_MASK (0x800U) -#define DAO_RX_CFGR_FRAME_EDGE_SHIFT (11U) -#define DAO_RX_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_FRAME_EDGE_SHIFT) & DAO_RX_CFGR_FRAME_EDGE_MASK) -#define DAO_RX_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_FRAME_EDGE_MASK) >> DAO_RX_CFGR_FRAME_EDGE_SHIFT) - -/* - * CH_MAX (RW) - * - * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 4'h2: 2 channels - * 4'h4: 4 channels - * etc - */ -#define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) -#define DAO_RX_CFGR_CH_MAX_SHIFT (6U) -#define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) -#define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) - -/* - * TDM_EN (RW) - * - * TDM mode - * 0: not TDM mode - * 1: TDM mode - */ -#define DAO_RX_CFGR_TDM_EN_MASK (0x20U) -#define DAO_RX_CFGR_TDM_EN_SHIFT (5U) -#define DAO_RX_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_TDM_EN_SHIFT) & DAO_RX_CFGR_TDM_EN_MASK) -#define DAO_RX_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_TDM_EN_MASK) >> DAO_RX_CFGR_TDM_EN_SHIFT) - -/* - * STD (RW) - * - * I2S standard selection - * 00: I2S Philips standard. - * 01: MSB justified standard (left justified) - * 10: LSB justified standard (right justified) - * 11: PCM standard - * For more details on I2S standards. - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define DAO_RX_CFGR_STD_MASK (0x18U) -#define DAO_RX_CFGR_STD_SHIFT (3U) -#define DAO_RX_CFGR_STD_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_STD_SHIFT) & DAO_RX_CFGR_STD_MASK) -#define DAO_RX_CFGR_STD_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_STD_MASK) >> DAO_RX_CFGR_STD_SHIFT) - -/* - * DATSIZ (RW) - * - * Data length to be transferred - * 00: 16-bit data length - * 01: 24-bit data length - * 10: 32-bit data length - * 11: Not allowed - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define DAO_RX_CFGR_DATSIZ_MASK (0x6U) -#define DAO_RX_CFGR_DATSIZ_SHIFT (1U) -#define DAO_RX_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_DATSIZ_SHIFT) & DAO_RX_CFGR_DATSIZ_MASK) -#define DAO_RX_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_DATSIZ_MASK) >> DAO_RX_CFGR_DATSIZ_SHIFT) - -/* - * CHSIZ (RW) - * - * Channel length (number of bits per audio channel) - * 0: 16-bit wide - * 1: 32-bit wide - * The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. - * Note: For correct operation, this bit should be configured when the I2S is disabled. - */ -#define DAO_RX_CFGR_CHSIZ_MASK (0x1U) -#define DAO_RX_CFGR_CHSIZ_SHIFT (0U) -#define DAO_RX_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CHSIZ_SHIFT) & DAO_RX_CFGR_CHSIZ_MASK) -#define DAO_RX_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CHSIZ_MASK) >> DAO_RX_CFGR_CHSIZ_SHIFT) - -/* Bitfield definition for register: RXSLT */ -/* - * EN (RW) - * - * Slot enable for the channels. - */ -#define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) -#define DAO_RXSLT_EN_SHIFT (0U) -#define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) -#define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_MA_COEF_SHIFT (0U) -#define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) -#define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define DAO_HPF_B_COEF_SHIFT (0U) -#define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) -#define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_DAO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dmamux_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dmamux_regs.h deleted file mode 100644 index 332e6242d42..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dmamux_regs.h +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAMUX_H -#define HPM_DMAMUX_H - -typedef struct { - __W uint32_t MUXCFG[64]; /* 0x0 - 0xFC: HDMA MUX0 Configuration */ -} DMAMUX_Type; - - -/* Bitfield definition for register array: MUXCFG */ -/* - * ENABLE (WO) - * - * DMA Mux Channel Enable - * Enables the channel for DMA Mux. The DMA has separate channel enables/disables, which should be - * used to disable or reconfigure a DMA channel. - * 0b - DMA Mux channel is disabled - * 1b - DMA Mux channel is enabled - */ -#define DMAMUX_MUXCFG_ENABLE_MASK (0x80000000UL) -#define DMAMUX_MUXCFG_ENABLE_SHIFT (31U) -#define DMAMUX_MUXCFG_ENABLE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_ENABLE_SHIFT) & DMAMUX_MUXCFG_ENABLE_MASK) -#define DMAMUX_MUXCFG_ENABLE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_ENABLE_MASK) >> DMAMUX_MUXCFG_ENABLE_SHIFT) - -/* - * SOURCE (WO) - * - * DMA Channel Source - * Specifies which DMA source, if any, is routed to a particular DMA channel. See the "DMA MUX Mapping" - */ -#define DMAMUX_MUXCFG_SOURCE_MASK (0x7FU) -#define DMAMUX_MUXCFG_SOURCE_SHIFT (0U) -#define DMAMUX_MUXCFG_SOURCE_SET(x) (((uint32_t)(x) << DMAMUX_MUXCFG_SOURCE_SHIFT) & DMAMUX_MUXCFG_SOURCE_MASK) -#define DMAMUX_MUXCFG_SOURCE_GET(x) (((uint32_t)(x) & DMAMUX_MUXCFG_SOURCE_MASK) >> DMAMUX_MUXCFG_SOURCE_SHIFT) - - - -/* MUXCFG register group index macro definition */ -#define DMAMUX_MUXCFG_HDMA_MUX0 (0UL) -#define DMAMUX_MUXCFG_HDMA_MUX1 (1UL) -#define DMAMUX_MUXCFG_HDMA_MUX2 (2UL) -#define DMAMUX_MUXCFG_HDMA_MUX3 (3UL) -#define DMAMUX_MUXCFG_HDMA_MUX4 (4UL) -#define DMAMUX_MUXCFG_HDMA_MUX5 (5UL) -#define DMAMUX_MUXCFG_HDMA_MUX6 (6UL) -#define DMAMUX_MUXCFG_HDMA_MUX7 (7UL) -#define DMAMUX_MUXCFG_HDMA_MUX8 (8UL) -#define DMAMUX_MUXCFG_HDMA_MUX9 (9UL) -#define DMAMUX_MUXCFG_HDMA_MUX10 (10UL) -#define DMAMUX_MUXCFG_HDMA_MUX11 (11UL) -#define DMAMUX_MUXCFG_HDMA_MUX12 (12UL) -#define DMAMUX_MUXCFG_HDMA_MUX13 (13UL) -#define DMAMUX_MUXCFG_HDMA_MUX14 (14UL) -#define DMAMUX_MUXCFG_HDMA_MUX15 (15UL) -#define DMAMUX_MUXCFG_HDMA_MUX16 (16UL) -#define DMAMUX_MUXCFG_HDMA_MUX17 (17UL) -#define DMAMUX_MUXCFG_HDMA_MUX18 (18UL) -#define DMAMUX_MUXCFG_HDMA_MUX19 (19UL) -#define DMAMUX_MUXCFG_HDMA_MUX20 (20UL) -#define DMAMUX_MUXCFG_HDMA_MUX21 (21UL) -#define DMAMUX_MUXCFG_HDMA_MUX22 (22UL) -#define DMAMUX_MUXCFG_HDMA_MUX23 (23UL) -#define DMAMUX_MUXCFG_HDMA_MUX24 (24UL) -#define DMAMUX_MUXCFG_HDMA_MUX25 (25UL) -#define DMAMUX_MUXCFG_HDMA_MUX26 (26UL) -#define DMAMUX_MUXCFG_HDMA_MUX27 (27UL) -#define DMAMUX_MUXCFG_HDMA_MUX28 (28UL) -#define DMAMUX_MUXCFG_HDMA_MUX29 (29UL) -#define DMAMUX_MUXCFG_HDMA_MUX30 (30UL) -#define DMAMUX_MUXCFG_HDMA_MUX31 (31UL) -#define DMAMUX_MUXCFG_XDMA_MUX0 (32UL) -#define DMAMUX_MUXCFG_XDMA_MUX1 (33UL) -#define DMAMUX_MUXCFG_XDMA_MUX2 (34UL) -#define DMAMUX_MUXCFG_XDMA_MUX3 (35UL) -#define DMAMUX_MUXCFG_XDMA_MUX4 (36UL) -#define DMAMUX_MUXCFG_XDMA_MUX5 (37UL) -#define DMAMUX_MUXCFG_XDMA_MUX6 (38UL) -#define DMAMUX_MUXCFG_XDMA_MUX7 (39UL) -#define DMAMUX_MUXCFG_XDMA_MUX8 (40UL) -#define DMAMUX_MUXCFG_XDMA_MUX9 (41UL) -#define DMAMUX_MUXCFG_XDMA_MUX10 (42UL) -#define DMAMUX_MUXCFG_XDMA_MUX11 (43UL) -#define DMAMUX_MUXCFG_XDMA_MUX12 (44UL) -#define DMAMUX_MUXCFG_XDMA_MUX13 (45UL) -#define DMAMUX_MUXCFG_XDMA_MUX14 (46UL) -#define DMAMUX_MUXCFG_XDMA_MUX15 (47UL) -#define DMAMUX_MUXCFG_XDMA_MUX16 (48UL) -#define DMAMUX_MUXCFG_XDMA_MUX17 (49UL) -#define DMAMUX_MUXCFG_XDMA_MUX18 (50UL) -#define DMAMUX_MUXCFG_XDMA_MUX19 (51UL) -#define DMAMUX_MUXCFG_XDMA_MUX20 (52UL) -#define DMAMUX_MUXCFG_XDMA_MUX21 (53UL) -#define DMAMUX_MUXCFG_XDMA_MUX22 (54UL) -#define DMAMUX_MUXCFG_XDMA_MUX23 (55UL) -#define DMAMUX_MUXCFG_XDMA_MUX24 (56UL) -#define DMAMUX_MUXCFG_XDMA_MUX25 (57UL) -#define DMAMUX_MUXCFG_XDMA_MUX26 (58UL) -#define DMAMUX_MUXCFG_XDMA_MUX27 (59UL) -#define DMAMUX_MUXCFG_XDMA_MUX28 (60UL) -#define DMAMUX_MUXCFG_XDMA_MUX29 (61UL) -#define DMAMUX_MUXCFG_XDMA_MUX30 (62UL) -#define DMAMUX_MUXCFG_XDMA_MUX31 (63UL) - - -#endif /* HPM_DMAMUX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dmav2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dmav2_regs.h deleted file mode 100644 index f36d81a8bd7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_dmav2_regs.h +++ /dev/null @@ -1,643 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_DMAV2_H -#define HPM_DMAV2_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t IDMISC; /* 0x4: ID Misc */ - __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */ - __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ - __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */ - __W uint32_t CHABORT; /* 0x18: Channel Abort Register */ - __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */ - __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */ - __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */ - __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */ - __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */ - __R uint32_t CHEN; /* 0x34: Channel Enable Register */ - __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ - struct { - __RW uint32_t CTRL; /* 0x40: Channel Control Register */ - __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */ - __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */ - __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */ - __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */ - __RW uint32_t SWAPTABLE; /* 0x54: swap table register */ - __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */ - __R uint8_t RESERVED0[4]; /* 0x5C - 0x5F: Reserved */ - } CHCTRL[32]; -} DMAV2_Type; - - -/* Bitfield definition for register: IDMISC */ -/* - * DMASTATE (RO) - * - * DMA state machine - * localparam ST_IDLE = 3'b000; - * localparam ST_READ = 3'b001; - * localparam ST_READ_ACK = 3'b010; - * localparam ST_WRITE = 3'b011; - * localparam ST_WRITE_ACK = 3'b100; - * localparam ST_LL = 3'b101; - * localparam ST_END = 3'b110; - * localparam ST_END_WAIT = 3'b111; - */ -#define DMAV2_IDMISC_DMASTATE_MASK (0xE000U) -#define DMAV2_IDMISC_DMASTATE_SHIFT (13U) -#define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT) - -/* - * CURCHAN (RO) - * - * current channel in used - */ -#define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U) -#define DMAV2_IDMISC_CURCHAN_SHIFT (8U) -#define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT) - -/* Bitfield definition for register: DMACFG */ -/* - * CHAINXFR (RO) - * - * Chain transfer - * 0x0: Chain transfer is not configured - * 0x1: Chain transfer is configured - */ -#define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL) -#define DMAV2_DMACFG_CHAINXFR_SHIFT (31U) -#define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT) - -/* - * REQSYNC (RO) - * - * DMA request synchronization. - * The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, - * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. - * 0x0: Request synchronization is not configured - * 0x1: Request synchronization is configured - */ -#define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL) -#define DMAV2_DMACFG_REQSYNC_SHIFT (30U) -#define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT) - -/* - * DATAWIDTH (RO) - * - * AXI bus data width - * 0x0: 32 bits - * 0x1: 64 bits - * 0x2: 128 bits - * 0x3: 256 bits - */ -#define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL) -#define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U) -#define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT) - -/* - * ADDRWIDTH (RO) - * - * AXI bus address width - * 0x18: 24 bits - * 0x19: 25 bits - * ... - * 0x40: 64 bits - * Others: Invalid - */ -#define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) -#define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U) -#define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT) - -/* - * CORENUM (RO) - * - * DMA core number - * 0x0: 1 core - * 0x1: 2 cores - */ -#define DMAV2_DMACFG_CORENUM_MASK (0x10000UL) -#define DMAV2_DMACFG_CORENUM_SHIFT (16U) -#define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT) - -/* - * BUSNUM (RO) - * - * AXI bus interface number - * 0x0: 1 AXI bus - * 0x1: 2 AXI busses - */ -#define DMAV2_DMACFG_BUSNUM_MASK (0x8000U) -#define DMAV2_DMACFG_BUSNUM_SHIFT (15U) -#define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT) - -/* - * REQNUM (RO) - * - * Request/acknowledge pair number - * 0x0: 0 pair - * 0x1: 1 pair - * 0x2: 2 pairs - * ... - * 0x10: 16 pairs - */ -#define DMAV2_DMACFG_REQNUM_MASK (0x7C00U) -#define DMAV2_DMACFG_REQNUM_SHIFT (10U) -#define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT) - -/* - * FIFODEPTH (RO) - * - * FIFO depth - * 0x4: 4 entries - * 0x8: 8 entries - * 0x10: 16 entries - * 0x20: 32 entries - * Others: Invalid - */ -#define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U) -#define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U) -#define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT) - -/* - * CHANNELNUM (RO) - * - * Channel number - * 0x1: 1 channel - * 0x2: 2 channels - * ... - * 0x8: 8 channels - * Others: Invalid - */ -#define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU) -#define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U) -#define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT) - -/* Bitfield definition for register: DMACTRL */ -/* - * RESET (WO) - * - * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. - * Note: The software reset may cause the in-completion of AXI transaction. - */ -#define DMAV2_DMACTRL_RESET_MASK (0x1U) -#define DMAV2_DMACTRL_RESET_SHIFT (0U) -#define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK) -#define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT) - -/* Bitfield definition for register: CHABORT */ -/* - * CHABORT (WO) - * - * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. - * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) - */ -#define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) -#define DMAV2_CHABORT_CHABORT_SHIFT (0U) -#define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK) -#define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT) - -/* Bitfield definition for register: INTHALFSTS */ -/* - * STS (RW) - * - * half transfer done irq status - */ -#define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTHALFSTS_STS_SHIFT (0U) -#define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK) -#define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT) - -/* Bitfield definition for register: INTTCSTS */ -/* - * STS (W1C) - * - * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. - * 0x0: Channel n has no terminal count status - * 0x1: Channel n has terminal count status - */ -#define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTTCSTS_STS_SHIFT (0U) -#define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK) -#define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT) - -/* Bitfield definition for register: INTABORTSTS */ -/* - * STS (W1C) - * - * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. - * 0x0: Channel n has no abort status - * 0x1: Channel n has abort status - */ -#define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTABORTSTS_STS_SHIFT (0U) -#define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK) -#define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT) - -/* Bitfield definition for register: INTERRSTS */ -/* - * STS (W1C) - * - * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: - * - Bus error - * - Unaligned address - * - Unaligned transfer width - * - Reserved configuration - * 0x0: Channel n has no error status - * 0x1: Channel n has error status - */ -#define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL) -#define DMAV2_INTERRSTS_STS_SHIFT (0U) -#define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK) -#define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT) - -/* Bitfield definition for register: CHEN */ -/* - * CHEN (RO) - * - * Alias of the Enable field of all ChnCtrl registers - */ -#define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL) -#define DMAV2_CHEN_CHEN_SHIFT (0U) -#define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CTRL */ -/* - * INFINITELOOP (RW) - * - * set to loop current config infinitely - */ -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) -#define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) - -/* - * HANDSHAKEOPT (RW) - * - * 0: one request to transfer one burst - * 1: one request to transfer all the data defined in ch_tts - */ -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) -#define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) - -/* - * PRIORITY (RW) - * - * Channel priority level - * 0x0: Lower priority - * 0x1: Higher priority - */ -#define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) -#define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U) -#define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) -#define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) - -/* - * BURSTOPT (RW) - * - * set to change burst_size definition - */ -#define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) -#define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) - -/* - * SRCBURSTSIZE (RW) - * - * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. - * The burst transfer byte number is (SrcBurstSize * SrcWidth). - * 0x0: 1 transfer - * 0x1: 2 transfers - * 0x2: 4 transfers - * 0x3: 8 transfers - * 0x4: 16 transfers - * 0x5: 32 transfers - * 0x6: 64 transfers - * 0x7: 128 transfers - * 0x8: 256 transfers - * 0x9:512 transfers - * 0xa: 1024 transfers - * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) -#define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) - -/* - * SRCWIDTH (RW) - * - * Source transfer width - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) -#define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) - -/* - * DSTWIDTH (RW) - * - * Destination transfer width. - * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; - * otherwise the error event will be triggered. - * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. - * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. - * 0x0: Byte transfer - * 0x1: Half-word transfer - * 0x2: Word transfer - * 0x3: Double word transfer - * 0x4: Quad word transfer - * 0x5: Eight word transfer - * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) -#define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) - -/* - * SRCMODE (RW) - * - * Source DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - * Normal mode is enabled and started by software set Enable bit; - * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block - */ -#define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) -#define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U) -#define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) -#define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) - -/* - * DSTMODE (RW) - * - * Destination DMA handshake mode - * 0x0: Normal mode - * 0x1: Handshake mode - * the difference bewteen Source/Destination handshake mode is: - * the dma block will response hardware request after read in Source handshake mode; - * the dma block will response hardware request after write in Destination handshake mode; - * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown. - */ -#define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) -#define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U) -#define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) -#define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) - -/* - * SRCADDRCTRL (RW) - * - * Source address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) -#define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) - -/* - * DSTADDRCTRL (RW) - * - * Destination address control - * 0x0: Increment address - * 0x1: Decrement address - * 0x2: Fixed address - * 0x3: Reserved, setting the field with this value triggers the error exception - */ -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) -#define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) - -/* - * SRC_FIXBURST (RW) - * - * set to loop current burst, omit setting in src_addr_ctrl - */ -#define DMAV2_CHCTRL_CTRL_SRC_FIXBURST_MASK (0x400U) -#define DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SHIFT (10U) -#define DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SHIFT) & DMAV2_CHCTRL_CTRL_SRC_FIXBURST_MASK) -#define DMAV2_CHCTRL_CTRL_SRC_FIXBURST_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRC_FIXBURST_MASK) >> DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SHIFT) - -/* - * DST_FIXBURST (RW) - * - * set to loop current burst, omit setting in dst_addr_ctrl - */ -#define DMAV2_CHCTRL_CTRL_DST_FIXBURST_MASK (0x100U) -#define DMAV2_CHCTRL_CTRL_DST_FIXBURST_SHIFT (8U) -#define DMAV2_CHCTRL_CTRL_DST_FIXBURST_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DST_FIXBURST_SHIFT) & DMAV2_CHCTRL_CTRL_DST_FIXBURST_MASK) -#define DMAV2_CHCTRL_CTRL_DST_FIXBURST_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DST_FIXBURST_MASK) >> DMAV2_CHCTRL_CTRL_DST_FIXBURST_SHIFT) - -/* - * SWAP_CTL (RW) - * - * 00 ：use swap table(if swap table all 0, then act nothing) - * 01 : byte swap - * 10 : 16bit swap - * 11 : 32bit swap - */ -#define DMAV2_CHCTRL_CTRL_SWAP_CTL_MASK (0xC0U) -#define DMAV2_CHCTRL_CTRL_SWAP_CTL_SHIFT (6U) -#define DMAV2_CHCTRL_CTRL_SWAP_CTL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SWAP_CTL_SHIFT) & DMAV2_CHCTRL_CTRL_SWAP_CTL_MASK) -#define DMAV2_CHCTRL_CTRL_SWAP_CTL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SWAP_CTL_MASK) >> DMAV2_CHCTRL_CTRL_SWAP_CTL_SHIFT) - -/* - * INTHALFCNTMASK (RW) - * - * Channel half interrupt mask - * 0x0: Allow the half interrupt to be triggered - * 0x1: Disable the half interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) - -/* - * INTABTMASK (RW) - * - * Channel abort interrupt mask - * 0x0: Allow the abort interrupt to be triggered - * 0x1: Disable the abort interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) - -/* - * INTERRMASK (RW) - * - * Channel error interrupt mask - * 0x0: Allow the error interrupt to be triggered - * 0x1: Disable the error interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) - -/* - * INTTCMASK (RW) - * - * Channel terminal count interrupt mask - * 0x0: Allow the terminal count interrupt to be triggered - * 0x1: Disable the terminal count interrupt - */ -#define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) -#define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) - -/* - * ENABLE (RW) - * - * Channel enable bit - * 0x0: Disable - * 0x1: Enable - */ -#define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U) -#define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U) -#define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) -#define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ -/* - * TRANSIZE (RW) - * - * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. - * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. - */ -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) -#define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SRCADDR */ -/* - * SRCADDRL (RW) - * - * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. - * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. - */ -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) -#define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */ -/* - * SRCREQSEL (RW) - * - * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. - */ -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) -#define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) - -/* - * DSTREQSEL (RW) - * - * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. - */ -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) -#define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: DSTADDR */ -/* - * DSTADDRL (RW) - * - * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. - * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. - */ -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) -#define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: SWAPTABLE */ -/* - * TABLE (RW) - * - * "4bit for one byte, define how to swap, default is no swap. - * For HDMA, support up to 4-byte, the register default value is 0x3210" - */ -#define DMAV2_CHCTRL_SWAPTABLE_TABLE_MASK (0xFFFFFFFFUL) -#define DMAV2_CHCTRL_SWAPTABLE_TABLE_SHIFT (0U) -#define DMAV2_CHCTRL_SWAPTABLE_TABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SWAPTABLE_TABLE_SHIFT) & DMAV2_CHCTRL_SWAPTABLE_TABLE_MASK) -#define DMAV2_CHCTRL_SWAPTABLE_TABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SWAPTABLE_TABLE_MASK) >> DMAV2_CHCTRL_SWAPTABLE_TABLE_SHIFT) - -/* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ -/* - * LLPOINTERL (RW) - * - * Low part of the pointer to the next descriptor. The pointer must be double word aligned. - */ -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) -#define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) - - - -/* CHCTRL register group index macro definition */ -#define DMAV2_CHCTRL_CH0 (0UL) -#define DMAV2_CHCTRL_CH1 (1UL) -#define DMAV2_CHCTRL_CH2 (2UL) -#define DMAV2_CHCTRL_CH3 (3UL) -#define DMAV2_CHCTRL_CH4 (4UL) -#define DMAV2_CHCTRL_CH5 (5UL) -#define DMAV2_CHCTRL_CH6 (6UL) -#define DMAV2_CHCTRL_CH7 (7UL) -#define DMAV2_CHCTRL_CH8 (8UL) -#define DMAV2_CHCTRL_CH9 (9UL) -#define DMAV2_CHCTRL_CH10 (10UL) -#define DMAV2_CHCTRL_CH11 (11UL) -#define DMAV2_CHCTRL_CH12 (12UL) -#define DMAV2_CHCTRL_CH13 (13UL) -#define DMAV2_CHCTRL_CH14 (14UL) -#define DMAV2_CHCTRL_CH15 (15UL) -#define DMAV2_CHCTRL_CH16 (16UL) -#define DMAV2_CHCTRL_CH17 (17UL) -#define DMAV2_CHCTRL_CH18 (18UL) -#define DMAV2_CHCTRL_CH19 (19UL) -#define DMAV2_CHCTRL_CH20 (20UL) -#define DMAV2_CHCTRL_CH21 (21UL) -#define DMAV2_CHCTRL_CH22 (22UL) -#define DMAV2_CHCTRL_CH23 (23UL) -#define DMAV2_CHCTRL_CH24 (24UL) -#define DMAV2_CHCTRL_CH25 (25UL) -#define DMAV2_CHCTRL_CH26 (26UL) -#define DMAV2_CHCTRL_CH27 (27UL) -#define DMAV2_CHCTRL_CH28 (28UL) -#define DMAV2_CHCTRL_CH29 (29UL) -#define DMAV2_CHCTRL_CH30 (30UL) -#define DMAV2_CHCTRL_CH31 (31UL) - - -#endif /* HPM_DMAV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_enet_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_enet_regs.h deleted file mode 100644 index 969988a78e6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_enet_regs.h +++ /dev/null @@ -1,6143 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ENET_H -#define HPM_ENET_H - -typedef struct { - __RW uint32_t MACCFG; /* 0x0: MAC Configuration Register */ - __RW uint32_t MACFF; /* 0x4: MAC Frame Filter */ - __RW uint32_t HASH_H; /* 0x8: Hash Table High Register */ - __RW uint32_t HASH_L; /* 0xC: Hash Table Low Register */ - __RW uint32_t GMII_ADDR; /* 0x10: GMII Address Register */ - __RW uint32_t GMII_DATA; /* 0x14: GMII Data Register */ - __RW uint32_t FLOWCTRL; /* 0x18: Flow Control Register */ - __RW uint32_t VLAN_TAG; /* 0x1C: VLAN Tag Register */ - __R uint8_t RESERVED0[8]; /* 0x20 - 0x27: Reserved */ - __RW uint32_t RWKFRMFILT; /* 0x28: Remote Wake-Up Frame Filter Register */ - __RW uint32_t PMT_CSR; /* 0x2C: PMT Control and Status Register */ - __RW uint32_t LPI_CSR; /* 0x30: LPI Control and Status Register */ - __RW uint32_t LPI_TCR; /* 0x34: LPI Timers Control Register */ - __R uint32_t INTR_STATUS; /* 0x38: Interrupt Status Register */ - __RW uint32_t INTR_MASK; /* 0x3C: Interrupt Mask Register */ - __RW uint32_t MAC_ADDR_0_HIGH; /* 0x40: MAC Address 0 High Register */ - __RW uint32_t MAC_ADDR_0_LOW; /* 0x44: MAC Address 0 Low Register */ - struct { - __RW uint32_t HIGH; /* 0x48: MAC Address High Register */ - __RW uint32_t LOW; /* 0x4C: MAC Address Low Register */ - } MAC_ADDR[4]; - __R uint8_t RESERVED1[112]; /* 0x68 - 0xD7: Reserved */ - __RW uint32_t XMII_CSR; /* 0xD8: SGMII/RGMII/SMII Control and Status Register */ - __RW uint32_t WDOG_WTO; /* 0xDC: Watchdog Timeout Register */ - __R uint8_t RESERVED2[32]; /* 0xE0 - 0xFF: Reserved */ - __RW uint32_t MMC_CNTRL; /* 0x100: MMC Control establishes the operating mode of MMC. */ - __RW uint32_t MMC_INTR_RX; /* 0x104: MMC Receive Interrupt */ - __RW uint32_t MMC_INTR_TX; /* 0x108: MMC Transmit Interrupt */ - __RW uint32_t MMC_INTR_MASK_RX; /* 0x10C: MMC Receive Interrupt mask */ - __RW uint32_t MMC_INTR_MASK_TX; /* 0x110: MMC Transmit Interrupt Mask */ - __R uint8_t RESERVED3[16]; /* 0x114 - 0x123: Reserved */ - __RW uint32_t TX64OCTETS_GB; /* 0x124: Number of good and bad frames transmitted with length 64 bytes, -exclusive of preamble and retried frames. */ - __RW uint32_t TX65TO127OCTETS_GB; /* 0x128: Number of good and bad frames transmitted with length between -65 and 127 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX128TO255OCTETS_GB; /* 0x12C: Number of good and bad frames transmitted with length between -128 and 255 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX256TO511OCTETS_GB; /* 0x130: Number of good and bad frames transmitted with length between -256 and 511 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX512TO1023OCTETS_GB; /* 0x134: Number of good and bad frames transmitted with length between -512 and 1,023 (inclusive) bytes, exclusive of preamble and retried -frames. */ - __RW uint32_t TX1024TOMAXOCTETS_GB; /* 0x138: Number of good and bad frames transmitted with length between -1,024 and maxsize (inclusive) bytes, exclusive of preamble and -retried frames. */ - __R uint8_t RESERVED4[68]; /* 0x13C - 0x17F: Reserved */ - __RW uint32_t RXFRAMECOUNT_GB; /* 0x180: Number of good and bad frames received */ - __R uint8_t RESERVED5[124]; /* 0x184 - 0x1FF: Reserved */ - __RW uint32_t MMC_IPC_INTR_MASK_RX; /* 0x200: MMC IPC Receive Checksum Offload Interrupt Mask maintains -the mask for the interrupt generated from the receive IPC statistic -counters. */ - __R uint8_t RESERVED6[4]; /* 0x204 - 0x207: Reserved */ - __RW uint32_t MMC_IPC_INTR_RX; /* 0x208: MMC Receive Checksum Offload Interrupt maintains the interrupt -that the receive IPC statistic counters generate. See Table 4-25 -for further detail. */ - __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */ - __RW uint32_t RXIPV4_GD_FMS; /* 0x210: Number of good IPv4 datagrams received with the TCP, UDP, or -ICMP payload */ - __R uint8_t RESERVED8[492]; /* 0x214 - 0x3FF: Reserved */ - struct { - __RW uint32_t L3_L4_CTRL; /* 0x400: Layer 3 and Layer 4 Control Register */ - __RW uint32_t L4_ADDR; /* 0x404: Layer 4 Address Register */ - __R uint8_t RESERVED0[8]; /* 0x408 - 0x40F: Reserved */ - __RW uint32_t L3_ADDR_0; /* 0x410: Layer 3 Address 0 Register */ - __RW uint32_t L3_ADDR_1; /* 0x414: Layer 3 Address 1 Register */ - __RW uint32_t L3_ADDR_2; /* 0x418: Layer 3 Address 2 Register */ - __RW uint32_t L3_ADDR_3; /* 0x41C: Layer 3 Address 3 Register */ - } L3_L4_CFG[1]; - __R uint8_t RESERVED9[356]; /* 0x420 - 0x583: Reserved */ - __RW uint32_t VLAN_TAG_INC_RPL; /* 0x584: VLAN Tag Inclusion or Replacement Register */ - __RW uint32_t VLAN_HASH; /* 0x588: VLAN Hash Table Register */ - __R uint8_t RESERVED10[372]; /* 0x58C - 0x6FF: Reserved */ - __RW uint32_t TS_CTRL; /* 0x700: Timestamp Control Register */ - __RW uint32_t SUB_SEC_INCR; /* 0x704: Sub-Second Increment Register */ - __R uint32_t SYST_SEC; /* 0x708: System Time - Seconds Register */ - __R uint32_t SYST_NSEC; /* 0x70C: System Time - Nanoseconds Register */ - __RW uint32_t SYST_SEC_UPD; /* 0x710: System Time - Seconds Update Register */ - __RW uint32_t SYST_NSEC_UPD; /* 0x714: System Time - Nanoseconds Update Register */ - __RW uint32_t TS_ADDEND; /* 0x718: Timestamp Addend Register */ - __RW uint32_t TGTTM_SEC; /* 0x71C: Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x720: Target Time Nanoseconds Register */ - __RW uint32_t SYSTM_H_SEC; /* 0x724: System Time - Higher Word Seconds Register */ - __R uint32_t TS_STATUS; /* 0x728: Timestamp Status Register */ - __RW uint32_t PPS_CTRL; /* 0x72C: PPS Control Register */ - __R uint32_t AUX_TS_NSEC; /* 0x730: Auxiliary Timestamp - Nanoseconds Register */ - __R uint32_t AUX_TS_SEC; /* 0x734: Auxiliary Timestamp - Seconds Register */ - __R uint8_t RESERVED11[40]; /* 0x738 - 0x75F: Reserved */ - __RW uint32_t PPS0_INTERVAL; /* 0x760: PPS Interval Register */ - __RW uint32_t PPS0_WIDTH; /* 0x764: PPS Width Register */ - __R uint8_t RESERVED12[24]; /* 0x768 - 0x77F: Reserved */ - struct { - __RW uint32_t TGTTM_SEC; /* 0x780: PPS Target Time Seconds Register */ - __RW uint32_t TGTTM_NSEC; /* 0x784: PPS Target Time Nanoseconds Register */ - __RW uint32_t INTERVAL; /* 0x788: PPS Interval Register */ - __RW uint32_t WIDTH; /* 0x78C: PPS Width Register */ - __R uint8_t RESERVED0[16]; /* 0x790 - 0x79F: Reserved */ - } PPS[3]; - __R uint8_t RESERVED13[2080]; /* 0x7E0 - 0xFFF: Reserved */ - __RW uint32_t DMA_BUS_MODE; /* 0x1000: Bus Mode Register */ - __RW uint32_t DMA_TX_POLL_DEMAND; /* 0x1004: Transmit Poll Demand Register */ - __RW uint32_t DMA_RX_POLL_DEMAND; /* 0x1008: Receive Poll Demand Register */ - __RW uint32_t DMA_RX_DESC_LIST_ADDR; /* 0x100C: Receive Descriptor List Address Register */ - __RW uint32_t DMA_TX_DESC_LIST_ADDR; /* 0x1010: Transmit Descriptor List Address Register */ - __RW uint32_t DMA_STATUS; /* 0x1014: Status Register */ - __RW uint32_t DMA_OP_MODE; /* 0x1018: Operation Mode Register */ - __RW uint32_t DMA_INTR_EN; /* 0x101C: Interrupt Enable Register */ - __RW uint32_t DMA_MISS_OVF_CNT; /* 0x1020: Missed Frame And Buffer Overflow Counter Register */ - __RW uint32_t DMA_RX_INTR_WDOG; /* 0x1024: Receive Interrupt Watchdog Timer Register */ - __RW uint32_t DMA_AXI_MODE; /* 0x1028: AXI Bus Mode Register */ - __RW uint32_t DMA_BUS_STATUS; /* 0x102C: AHB or AXI Status Register */ - __R uint8_t RESERVED14[24]; /* 0x1030 - 0x1047: Reserved */ - __RW uint32_t DMA_CURR_HOST_TX_DESC; /* 0x1048: Current Host Transmit Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_RX_DESC; /* 0x104C: Current Host Receive Descriptor Register */ - __RW uint32_t DMA_CURR_HOST_TX_BUF; /* 0x1050: Current Host Transmit Buffer Address Register */ - __RW uint32_t DMA_CURR_HOST_RX_BUF; /* 0x1054: Current Host Receive Buffer Address Register */ - __R uint8_t RESERVED15[8104]; /* 0x1058 - 0x2FFF: Reserved */ - __RW uint32_t CTRL0; /* 0x3000: Control Register 0 */ - __R uint8_t RESERVED16[4]; /* 0x3004 - 0x3007: Reserved */ - __RW uint32_t CTRL2; /* 0x3008: Control Register 1 */ - __R uint8_t RESERVED17[28]; /* 0x300C - 0x3027: Reserved */ -} ENET_Type; - - -/* Bitfield definition for register: MACCFG */ -/* - * SARC (RW) - * - * Source Address Insertion or Replacement Control - * This field controls the source address insertion or replacement for all transmitted frames. - * Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: - * - 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. - * - 2'b10: - If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * - 2'b11: - If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames. - * - If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, - * the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames. - * Note: - Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, - * that is, the current frame does not use the updated value. - * - These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion on TX feature is not selected during core configuration. - */ -#define ENET_MACCFG_SARC_MASK (0x70000000UL) -#define ENET_MACCFG_SARC_SHIFT (28U) -#define ENET_MACCFG_SARC_SET(x) (((uint32_t)(x) << ENET_MACCFG_SARC_SHIFT) & ENET_MACCFG_SARC_MASK) -#define ENET_MACCFG_SARC_GET(x) (((uint32_t)(x) & ENET_MACCFG_SARC_MASK) >> ENET_MACCFG_SARC_SHIFT) - -/* - * TWOKPE (RW) - * - * IEEE 802.3as Support for 2K Packets - * When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. - * When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. - * When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. - * When Bit 20 is set, setting this bit has no effect on Giant Frame status. - */ -#define ENET_MACCFG_TWOKPE_MASK (0x8000000UL) -#define ENET_MACCFG_TWOKPE_SHIFT (27U) -#define ENET_MACCFG_TWOKPE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TWOKPE_SHIFT) & ENET_MACCFG_TWOKPE_MASK) -#define ENET_MACCFG_TWOKPE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TWOKPE_MASK) >> ENET_MACCFG_TWOKPE_SHIFT) - -/* - * SFTERR (RW) - * - * SMII Force Transmit Error - * When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_SFTERR_MASK (0x4000000UL) -#define ENET_MACCFG_SFTERR_SHIFT (26U) -#define ENET_MACCFG_SFTERR_SET(x) (((uint32_t)(x) << ENET_MACCFG_SFTERR_SHIFT) & ENET_MACCFG_SFTERR_MASK) -#define ENET_MACCFG_SFTERR_GET(x) (((uint32_t)(x) & ENET_MACCFG_SFTERR_MASK) >> ENET_MACCFG_SFTERR_SHIFT) - -/* - * CST (RW) - * - * CRC Stripping for Type Frames - * When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. - * This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled. - */ -#define ENET_MACCFG_CST_MASK (0x2000000UL) -#define ENET_MACCFG_CST_SHIFT (25U) -#define ENET_MACCFG_CST_SET(x) (((uint32_t)(x) << ENET_MACCFG_CST_SHIFT) & ENET_MACCFG_CST_MASK) -#define ENET_MACCFG_CST_GET(x) (((uint32_t)(x) & ENET_MACCFG_CST_MASK) >> ENET_MACCFG_CST_SHIFT) - -/* - * TC (RW) - * - * Transmit Configuration in RGMII, SGMII, or SMII - * When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, - * or SGMII port. When this bit is reset, no such information is driven to the PHY. - * This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration. - */ -#define ENET_MACCFG_TC_MASK (0x1000000UL) -#define ENET_MACCFG_TC_SHIFT (24U) -#define ENET_MACCFG_TC_SET(x) (((uint32_t)(x) << ENET_MACCFG_TC_SHIFT) & ENET_MACCFG_TC_MASK) -#define ENET_MACCFG_TC_GET(x) (((uint32_t)(x) & ENET_MACCFG_TC_MASK) >> ENET_MACCFG_TC_SHIFT) - -/* - * WD (RW) - * - * Watchdog Disable - * When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,383 bytes. - */ -#define ENET_MACCFG_WD_MASK (0x800000UL) -#define ENET_MACCFG_WD_SHIFT (23U) -#define ENET_MACCFG_WD_SET(x) (((uint32_t)(x) << ENET_MACCFG_WD_SHIFT) & ENET_MACCFG_WD_MASK) -#define ENET_MACCFG_WD_GET(x) (((uint32_t)(x) & ENET_MACCFG_WD_MASK) >> ENET_MACCFG_WD_SHIFT) - -/* - * JD (RW) - * - * Jabber Disable - * When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,383 bytes. - * When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission. - */ -#define ENET_MACCFG_JD_MASK (0x400000UL) -#define ENET_MACCFG_JD_SHIFT (22U) -#define ENET_MACCFG_JD_SET(x) (((uint32_t)(x) << ENET_MACCFG_JD_SHIFT) & ENET_MACCFG_JD_MASK) -#define ENET_MACCFG_JD_GET(x) (((uint32_t)(x) & ENET_MACCFG_JD_MASK) >> ENET_MACCFG_JD_SHIFT) - -/* - * BE (RW) - * - * Frame Burst Enable - * When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations. - */ -#define ENET_MACCFG_BE_MASK (0x200000UL) -#define ENET_MACCFG_BE_SHIFT (21U) -#define ENET_MACCFG_BE_SET(x) (((uint32_t)(x) << ENET_MACCFG_BE_SHIFT) & ENET_MACCFG_BE_MASK) -#define ENET_MACCFG_BE_GET(x) (((uint32_t)(x) & ENET_MACCFG_BE_MASK) >> ENET_MACCFG_BE_SHIFT) - -/* - * JE (RW) - * - * Jumbo Frame Enable - * When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. - */ -#define ENET_MACCFG_JE_MASK (0x100000UL) -#define ENET_MACCFG_JE_SHIFT (20U) -#define ENET_MACCFG_JE_SET(x) (((uint32_t)(x) << ENET_MACCFG_JE_SHIFT) & ENET_MACCFG_JE_MASK) -#define ENET_MACCFG_JE_GET(x) (((uint32_t)(x) & ENET_MACCFG_JE_MASK) >> ENET_MACCFG_JE_SHIFT) - -/* - * IFG (RW) - * - * Inter-Frame Gap - * These bits control the minimum IFG between frames during transmission. - * - 000: 96 bit times - * - 001: 88 bit times - * - 010: 80 bit times - ... - * - 111: 40 bit times In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). - * Lower values are not considered. - * In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations. - * When a JAM pattern is being transmitted because of backpressure activation, the MAC does not consider the minimum IFG. - */ -#define ENET_MACCFG_IFG_MASK (0xE0000UL) -#define ENET_MACCFG_IFG_SHIFT (17U) -#define ENET_MACCFG_IFG_SET(x) (((uint32_t)(x) << ENET_MACCFG_IFG_SHIFT) & ENET_MACCFG_IFG_MASK) -#define ENET_MACCFG_IFG_GET(x) (((uint32_t)(x) & ENET_MACCFG_IFG_MASK) >> ENET_MACCFG_IFG_SHIFT) - -/* - * DCRS (RW) - * - * Disable Carrier Sense During Transmission - * When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. - * This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. - * When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. - */ -#define ENET_MACCFG_DCRS_MASK (0x10000UL) -#define ENET_MACCFG_DCRS_SHIFT (16U) -#define ENET_MACCFG_DCRS_SET(x) (((uint32_t)(x) << ENET_MACCFG_DCRS_SHIFT) & ENET_MACCFG_DCRS_MASK) -#define ENET_MACCFG_DCRS_GET(x) (((uint32_t)(x) & ENET_MACCFG_DCRS_MASK) >> ENET_MACCFG_DCRS_SHIFT) - -/* - * PS (RW) - * - * Port Select - * This bit selects the Ethernet line speed. - * - 0: For 1000 Mbps operations - * - 1: For 10 or 100 Mbps operations In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. - * In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10/100/1000 Mbps configuration, - * this bit is R_W. The mac_portselect_o or mac_speed_o[1] signal reflects the value of this bit. - */ -#define ENET_MACCFG_PS_MASK (0x8000U) -#define ENET_MACCFG_PS_SHIFT (15U) -#define ENET_MACCFG_PS_SET(x) (((uint32_t)(x) << ENET_MACCFG_PS_SHIFT) & ENET_MACCFG_PS_MASK) -#define ENET_MACCFG_PS_GET(x) (((uint32_t)(x) & ENET_MACCFG_PS_MASK) >> ENET_MACCFG_PS_SHIFT) - -/* - * FES (RW) - * - * Speed - * This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface: - * - 0: 10 Mbps - * - 1: 100 Mbps This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. - * This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. - * This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface. - * In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. - * In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal. - */ -#define ENET_MACCFG_FES_MASK (0x4000U) -#define ENET_MACCFG_FES_SHIFT (14U) -#define ENET_MACCFG_FES_SET(x) (((uint32_t)(x) << ENET_MACCFG_FES_SHIFT) & ENET_MACCFG_FES_MASK) -#define ENET_MACCFG_FES_GET(x) (((uint32_t)(x) & ENET_MACCFG_FES_MASK) >> ENET_MACCFG_FES_SHIFT) - -/* - * DO (RW) - * - * Disable Receive Own - * When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode. - * When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting. - * This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full-duplex-only operation. - */ -#define ENET_MACCFG_DO_MASK (0x2000U) -#define ENET_MACCFG_DO_SHIFT (13U) -#define ENET_MACCFG_DO_SET(x) (((uint32_t)(x) << ENET_MACCFG_DO_SHIFT) & ENET_MACCFG_DO_MASK) -#define ENET_MACCFG_DO_GET(x) (((uint32_t)(x) & ENET_MACCFG_DO_MASK) >> ENET_MACCFG_DO_SHIFT) - -/* - * LM (RW) - * - * Loopback Mode - * When this bit is set, the MAC operates in the loopback mode at GMII or MII. - * The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally. - */ -#define ENET_MACCFG_LM_MASK (0x1000U) -#define ENET_MACCFG_LM_SHIFT (12U) -#define ENET_MACCFG_LM_SET(x) (((uint32_t)(x) << ENET_MACCFG_LM_SHIFT) & ENET_MACCFG_LM_MASK) -#define ENET_MACCFG_LM_GET(x) (((uint32_t)(x) & ENET_MACCFG_LM_MASK) >> ENET_MACCFG_LM_SHIFT) - -/* - * DM (RW) - * - * Duplex Mode - * When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. - */ -#define ENET_MACCFG_DM_MASK (0x800U) -#define ENET_MACCFG_DM_SHIFT (11U) -#define ENET_MACCFG_DM_SET(x) (((uint32_t)(x) << ENET_MACCFG_DM_SHIFT) & ENET_MACCFG_DM_MASK) -#define ENET_MACCFG_DM_GET(x) (((uint32_t)(x) & ENET_MACCFG_DM_MASK) >> ENET_MACCFG_DM_SHIFT) - -/* - * IPC (RW) - * - * Checksum Offload - * When this bit is set, the MAC calculates the 16-bit one’s complement of the one’s complement sum of all received Ethernet frame payloads. - * It also checks whether the IPv4 Header checksum (assumed to be bytes 25–26 or 29–30 (VLAN-tagged) - * of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. - * The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) - * and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). - * When this bit is reset, this function is disabled. - * When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. - */ -#define ENET_MACCFG_IPC_MASK (0x400U) -#define ENET_MACCFG_IPC_SHIFT (10U) -#define ENET_MACCFG_IPC_SET(x) (((uint32_t)(x) << ENET_MACCFG_IPC_SHIFT) & ENET_MACCFG_IPC_MASK) -#define ENET_MACCFG_IPC_GET(x) (((uint32_t)(x) & ENET_MACCFG_IPC_MASK) >> ENET_MACCFG_IPC_SHIFT) - -/* - * DR (RW) - * - * Disable Retry - * When this bit is set, the MAC attempts only one transmission. - * When a collision occurs on the GMII or MII interface, - * the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. - * When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). - */ -#define ENET_MACCFG_DR_MASK (0x200U) -#define ENET_MACCFG_DR_SHIFT (9U) -#define ENET_MACCFG_DR_SET(x) (((uint32_t)(x) << ENET_MACCFG_DR_SHIFT) & ENET_MACCFG_DR_MASK) -#define ENET_MACCFG_DR_GET(x) (((uint32_t)(x) & ENET_MACCFG_DR_MASK) >> ENET_MACCFG_DR_SHIFT) - -/* - * LUD (RW) - * - * Link Up or Down - * This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface: - * - 0: Link Down - * - 1: Link Up - */ -#define ENET_MACCFG_LUD_MASK (0x100U) -#define ENET_MACCFG_LUD_SHIFT (8U) -#define ENET_MACCFG_LUD_SET(x) (((uint32_t)(x) << ENET_MACCFG_LUD_SHIFT) & ENET_MACCFG_LUD_MASK) -#define ENET_MACCFG_LUD_GET(x) (((uint32_t)(x) & ENET_MACCFG_LUD_MASK) >> ENET_MACCFG_LUD_SHIFT) - -/* - * ACS (RW) - * - * Automatic Pad or CRC Stripping - * When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. - * All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field. - * When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host. - */ -#define ENET_MACCFG_ACS_MASK (0x80U) -#define ENET_MACCFG_ACS_SHIFT (7U) -#define ENET_MACCFG_ACS_SET(x) (((uint32_t)(x) << ENET_MACCFG_ACS_SHIFT) & ENET_MACCFG_ACS_MASK) -#define ENET_MACCFG_ACS_GET(x) (((uint32_t)(x) & ENET_MACCFG_ACS_MASK) >> ENET_MACCFG_ACS_SHIFT) - -/* - * BL (RW) - * - * Back-Off Limit - * The Back-Off limit determines the random integer number (r) of slot time delays - * (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. - * This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration. - * - 00: k= min (n, 10) - * - 01: k = min (n, 8) - * - 10: k = min (n, 4) - * - 11: k = min (n, 1) where n = retransmission attempt. The random integer r takes the value in the range 0 ≤ r < 2k - */ -#define ENET_MACCFG_BL_MASK (0x60U) -#define ENET_MACCFG_BL_SHIFT (5U) -#define ENET_MACCFG_BL_SET(x) (((uint32_t)(x) << ENET_MACCFG_BL_SHIFT) & ENET_MACCFG_BL_MASK) -#define ENET_MACCFG_BL_GET(x) (((uint32_t)(x) & ENET_MACCFG_BL_MASK) >> ENET_MACCFG_BL_SHIFT) - -/* - * DC (RW) - * - * Deferral Check - * When this bit is set, the deferral check function is enabled in the MAC. - * The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, - * when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. - * If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, - * the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, - * but it is prevented because of an active carrier sense signal (CRS) on GMII or MII. The defer time is not cumulative. - * For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, - * the transmitter transmits and collision happens. - * Because of collision, the transmitter needs to back off and then defer again after back off completion. - * In such a scenario, the deferral timer is reset to 0 and it is restarted. - */ -#define ENET_MACCFG_DC_MASK (0x10U) -#define ENET_MACCFG_DC_SHIFT (4U) -#define ENET_MACCFG_DC_SET(x) (((uint32_t)(x) << ENET_MACCFG_DC_SHIFT) & ENET_MACCFG_DC_MASK) -#define ENET_MACCFG_DC_GET(x) (((uint32_t)(x) & ENET_MACCFG_DC_MASK) >> ENET_MACCFG_DC_SHIFT) - -/* - * TE (RW) - * - * Transmitter Enable - * When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, - * the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. - */ -#define ENET_MACCFG_TE_MASK (0x8U) -#define ENET_MACCFG_TE_SHIFT (3U) -#define ENET_MACCFG_TE_SET(x) (((uint32_t)(x) << ENET_MACCFG_TE_SHIFT) & ENET_MACCFG_TE_MASK) -#define ENET_MACCFG_TE_GET(x) (((uint32_t)(x) & ENET_MACCFG_TE_MASK) >> ENET_MACCFG_TE_SHIFT) - -/* - * RE (RW) - * - * Receiver Enable - * When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, - * the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII. - */ -#define ENET_MACCFG_RE_MASK (0x4U) -#define ENET_MACCFG_RE_SHIFT (2U) -#define ENET_MACCFG_RE_SET(x) (((uint32_t)(x) << ENET_MACCFG_RE_SHIFT) & ENET_MACCFG_RE_MASK) -#define ENET_MACCFG_RE_GET(x) (((uint32_t)(x) & ENET_MACCFG_RE_MASK) >> ENET_MACCFG_RE_SHIFT) - -/* - * PRELEN (RW) - * - * Preamble Length for Transmit frames - * These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. - * The preamble reduction occurs only when the MAC is operating in the full-duplex mode. - * - 2'b00: 7 bytes of preamble - * - 2'b01: 5 bytes of preamble - * - 2'b10: 3 bytes of preamble - * - 2'b11: Reserved - */ -#define ENET_MACCFG_PRELEN_MASK (0x3U) -#define ENET_MACCFG_PRELEN_SHIFT (0U) -#define ENET_MACCFG_PRELEN_SET(x) (((uint32_t)(x) << ENET_MACCFG_PRELEN_SHIFT) & ENET_MACCFG_PRELEN_MASK) -#define ENET_MACCFG_PRELEN_GET(x) (((uint32_t)(x) & ENET_MACCFG_PRELEN_MASK) >> ENET_MACCFG_PRELEN_SHIFT) - -/* Bitfield definition for register: MACFF */ -/* - * RA (RW) - * - * Receive All - * When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. - * The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset, - * the Receiver module passes only those frames to the Application that pass the SA or DA address filter. - */ -#define ENET_MACFF_RA_MASK (0x80000000UL) -#define ENET_MACFF_RA_SHIFT (31U) -#define ENET_MACFF_RA_SET(x) (((uint32_t)(x) << ENET_MACFF_RA_SHIFT) & ENET_MACFF_RA_MASK) -#define ENET_MACFF_RA_GET(x) (((uint32_t)(x) & ENET_MACFF_RA_MASK) >> ENET_MACFF_RA_SHIFT) - -/* - * DNTU (RW) - * - * Drop non-TCP/UDP over IP Frames - * When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter. - * When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames. - */ -#define ENET_MACFF_DNTU_MASK (0x200000UL) -#define ENET_MACFF_DNTU_SHIFT (21U) -#define ENET_MACFF_DNTU_SET(x) (((uint32_t)(x) << ENET_MACFF_DNTU_SHIFT) & ENET_MACFF_DNTU_MASK) -#define ENET_MACFF_DNTU_GET(x) (((uint32_t)(x) & ENET_MACFF_DNTU_MASK) >> ENET_MACFF_DNTU_SHIFT) - -/* - * IPFE (RW) - * - * Layer 3 and Layer 4 Filter Enable - * When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, - * this bit does not have any effect. When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields. - */ -#define ENET_MACFF_IPFE_MASK (0x100000UL) -#define ENET_MACFF_IPFE_SHIFT (20U) -#define ENET_MACFF_IPFE_SET(x) (((uint32_t)(x) << ENET_MACFF_IPFE_SHIFT) & ENET_MACFF_IPFE_MASK) -#define ENET_MACFF_IPFE_GET(x) (((uint32_t)(x) & ENET_MACFF_IPFE_MASK) >> ENET_MACFF_IPFE_SHIFT) - -/* - * VTFE (RW) - * - * VLAN Tag Filter Enable - * When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison. - * When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag. - */ -#define ENET_MACFF_VTFE_MASK (0x8000U) -#define ENET_MACFF_VTFE_SHIFT (15U) -#define ENET_MACFF_VTFE_SET(x) (((uint32_t)(x) << ENET_MACFF_VTFE_SHIFT) & ENET_MACFF_VTFE_MASK) -#define ENET_MACFF_VTFE_GET(x) (((uint32_t)(x) & ENET_MACFF_VTFE_MASK) >> ENET_MACFF_VTFE_SHIFT) - -/* - * HPF (RW) - * - * Hash or Perfect Filter - * When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits. - * When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. - */ -#define ENET_MACFF_HPF_MASK (0x400U) -#define ENET_MACFF_HPF_SHIFT (10U) -#define ENET_MACFF_HPF_SET(x) (((uint32_t)(x) << ENET_MACFF_HPF_SHIFT) & ENET_MACFF_HPF_MASK) -#define ENET_MACFF_HPF_GET(x) (((uint32_t)(x) & ENET_MACFF_HPF_MASK) >> ENET_MACFF_HPF_SHIFT) - -/* - * SAF (RW) - * - * Source Address Filter Enable - * When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, - * the MAC drops the frame. When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. - */ -#define ENET_MACFF_SAF_MASK (0x200U) -#define ENET_MACFF_SAF_SHIFT (9U) -#define ENET_MACFF_SAF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAF_SHIFT) & ENET_MACFF_SAF_MASK) -#define ENET_MACFF_SAF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAF_MASK) >> ENET_MACFF_SAF_SHIFT) - -/* - * SAIF (RW) - * - * SA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. - * When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter. - */ -#define ENET_MACFF_SAIF_MASK (0x100U) -#define ENET_MACFF_SAIF_SHIFT (8U) -#define ENET_MACFF_SAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_SAIF_SHIFT) & ENET_MACFF_SAIF_MASK) -#define ENET_MACFF_SAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_SAIF_MASK) >> ENET_MACFF_SAIF_SHIFT) - -/* - * PCF (RW) - * - * Pass Control Frames - * These bits control the forwarding of all control frames (including unicast and multicast Pause frames). - * - 00: MAC filters all control frames from reaching the application. - * - 01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. - * - 10: MAC forwards all control frames to application even if they fail the Address Filter. - * - 11: MAC forwards control frames that pass the Address Filter. - * The following conditions should be true for the Pause frames processing: - * - Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1. - * - Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set. - * - Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001. - * Note: This field should be set to 01 only when the Condition 1 is true, - * that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. - * Otherwise, the Pause frame filtering may be inconsistent. - * When Condition 1 is false, the Pause frames are considered as generic control frames. - * Therefore, to pass all control frames (including Pause frames) when the full-duplex mode and flow control is not enabled, - * you should set the PCF field to 10 or 11 (as required by the application). - */ -#define ENET_MACFF_PCF_MASK (0xC0U) -#define ENET_MACFF_PCF_SHIFT (6U) -#define ENET_MACFF_PCF_SET(x) (((uint32_t)(x) << ENET_MACFF_PCF_SHIFT) & ENET_MACFF_PCF_MASK) -#define ENET_MACFF_PCF_GET(x) (((uint32_t)(x) & ENET_MACFF_PCF_MASK) >> ENET_MACFF_PCF_SHIFT) - -/* - * DBF (RW) - * - * Disable Broadcast Frames - * When this bit is set, the AFM module blocks all incoming broadcast frames. In addition, it overrides all other filter settings. - * When this bit is reset, the AFM module passes all received broadcast frames. - */ -#define ENET_MACFF_DBF_MASK (0x20U) -#define ENET_MACFF_DBF_SHIFT (5U) -#define ENET_MACFF_DBF_SET(x) (((uint32_t)(x) << ENET_MACFF_DBF_SHIFT) & ENET_MACFF_DBF_MASK) -#define ENET_MACFF_DBF_GET(x) (((uint32_t)(x) & ENET_MACFF_DBF_MASK) >> ENET_MACFF_DBF_SHIFT) - -/* - * PM (RW) - * - * Pass All Multicast - * When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. - * When reset, filtering of multicast frame depends on HMC bit. - */ -#define ENET_MACFF_PM_MASK (0x10U) -#define ENET_MACFF_PM_SHIFT (4U) -#define ENET_MACFF_PM_SET(x) (((uint32_t)(x) << ENET_MACFF_PM_SHIFT) & ENET_MACFF_PM_MASK) -#define ENET_MACFF_PM_GET(x) (((uint32_t)(x) & ENET_MACFF_PM_MASK) >> ENET_MACFF_PM_SHIFT) - -/* - * DAIF (RW) - * - * DA Inverse Filtering - * When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. - * When reset, normal filtering of frames is performed. - */ -#define ENET_MACFF_DAIF_MASK (0x8U) -#define ENET_MACFF_DAIF_SHIFT (3U) -#define ENET_MACFF_DAIF_SET(x) (((uint32_t)(x) << ENET_MACFF_DAIF_SHIFT) & ENET_MACFF_DAIF_MASK) -#define ENET_MACFF_DAIF_GET(x) (((uint32_t)(x) & ENET_MACFF_DAIF_MASK) >> ENET_MACFF_DAIF_SHIFT) - -/* - * HMC (RW) - * - * Hash Multicast - * When set, the MAC performs destination address filtering of received multicast frames according to the hash table. When reset, - * the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HMC_MASK (0x4U) -#define ENET_MACFF_HMC_SHIFT (2U) -#define ENET_MACFF_HMC_SET(x) (((uint32_t)(x) << ENET_MACFF_HMC_SHIFT) & ENET_MACFF_HMC_MASK) -#define ENET_MACFF_HMC_GET(x) (((uint32_t)(x) & ENET_MACFF_HMC_MASK) >> ENET_MACFF_HMC_SHIFT) - -/* - * HUC (RW) - * - * Hash Unicast - * When set, the MAC performs destination address filtering of unicast frames according to the hash table. - * When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers. - */ -#define ENET_MACFF_HUC_MASK (0x2U) -#define ENET_MACFF_HUC_SHIFT (1U) -#define ENET_MACFF_HUC_SET(x) (((uint32_t)(x) << ENET_MACFF_HUC_SHIFT) & ENET_MACFF_HUC_MASK) -#define ENET_MACFF_HUC_GET(x) (((uint32_t)(x) & ENET_MACFF_HUC_MASK) >> ENET_MACFF_HUC_SHIFT) - -/* - * PR (RW) - * - * Promiscuous Mode - * When this bit is set, the Address Filter module passes all incoming frames irrespective of the destination or source address. - * The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set. - */ -#define ENET_MACFF_PR_MASK (0x1U) -#define ENET_MACFF_PR_SHIFT (0U) -#define ENET_MACFF_PR_SET(x) (((uint32_t)(x) << ENET_MACFF_PR_SHIFT) & ENET_MACFF_PR_MASK) -#define ENET_MACFF_PR_GET(x) (((uint32_t)(x) & ENET_MACFF_PR_MASK) >> ENET_MACFF_PR_SHIFT) - -/* Bitfield definition for register: HASH_H */ -/* - * HTH (RW) - * - * Hash Table High - * This field contains the upper 32 bits of the Hash table. - */ -#define ENET_HASH_H_HTH_MASK (0xFFFFFFFFUL) -#define ENET_HASH_H_HTH_SHIFT (0U) -#define ENET_HASH_H_HTH_SET(x) (((uint32_t)(x) << ENET_HASH_H_HTH_SHIFT) & ENET_HASH_H_HTH_MASK) -#define ENET_HASH_H_HTH_GET(x) (((uint32_t)(x) & ENET_HASH_H_HTH_MASK) >> ENET_HASH_H_HTH_SHIFT) - -/* Bitfield definition for register: HASH_L */ -/* - * HTL (RW) - * - * Hash Table Low - * This field contains the lower 32 bits of the Hash table. - */ -#define ENET_HASH_L_HTL_MASK (0xFFFFFFFFUL) -#define ENET_HASH_L_HTL_SHIFT (0U) -#define ENET_HASH_L_HTL_SET(x) (((uint32_t)(x) << ENET_HASH_L_HTL_SHIFT) & ENET_HASH_L_HTL_MASK) -#define ENET_HASH_L_HTL_GET(x) (((uint32_t)(x) & ENET_HASH_L_HTL_MASK) >> ENET_HASH_L_HTL_SHIFT) - -/* Bitfield definition for register: GMII_ADDR */ -/* - * PA (RW) - * - * Physical Layer Address - * This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. - */ -#define ENET_GMII_ADDR_PA_MASK (0xF800U) -#define ENET_GMII_ADDR_PA_SHIFT (11U) -#define ENET_GMII_ADDR_PA_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_PA_SHIFT) & ENET_GMII_ADDR_PA_MASK) -#define ENET_GMII_ADDR_PA_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_PA_MASK) >> ENET_GMII_ADDR_PA_SHIFT) - -/* - * GR (RW) - * - * GMII Register - * These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. - */ -#define ENET_GMII_ADDR_GR_MASK (0x7C0U) -#define ENET_GMII_ADDR_GR_SHIFT (6U) -#define ENET_GMII_ADDR_GR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GR_SHIFT) & ENET_GMII_ADDR_GR_MASK) -#define ENET_GMII_ADDR_GR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GR_MASK) >> ENET_GMII_ADDR_GR_SHIFT) - -/* - * CR (RW) - * - * CSR Clock Range - * The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. - * The CSR clock corresponding to different GMAC configurations is given in Table 9-2 on page 564. - * The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) - * ensures that the MDC clock is approximately between the frequency range 1.0 MHz–2.5 MHz. - * - 0000: The CSR clock frequency is 60–100 MHz and the MDC clock frequency is CSR clock/42. - * - 0001: The CSR clock frequency is 100–150 MHz and the MDC clock frequency is CSR clock/62. - * - 0010: The CSR clock frequency is 20–35 MHz and the MDC clock frequency is CSR clock/16. - * - 0011: The CSR clock frequency is 35–60 MHz and the MDC clock frequency is CSR clock/26. - * - 0100: The CSR clock frequency is 150–250 MHz and the MDC clock frequency is CSR clock/102. - * - 0101: The CSR clock frequency is 250–300 MHz and the MDC clock is CSR clock/124. - * - 0110, 0111: Reserved - * When Bit 5 is set, you can achieve higher frequency of the MDC clock than the frequency limit of 2.5 MHz (specified in the IEEE Std 802.3) and program a clock divider of lower value. - * For example, - * when CSR clock is of 100 MHz frequency and you program these bits as 1010, - * then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. - * Program the following values only if the interfacing chips support faster MDC clocks. - * - 1000: CSR clock/4 - * - 1001: CSR clock/6 - * - 1010: CSR clock/8 - * - 1011: CSR clock/10 - * - 1100: CSR clock/12 - * - 1101: CSR clock/14 - * - 1110: CSR clock/16 - * - 1111: CSR clock/18 These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. - */ -#define ENET_GMII_ADDR_CR_MASK (0x3CU) -#define ENET_GMII_ADDR_CR_SHIFT (2U) -#define ENET_GMII_ADDR_CR_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_CR_SHIFT) & ENET_GMII_ADDR_CR_MASK) -#define ENET_GMII_ADDR_CR_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_CR_MASK) >> ENET_GMII_ADDR_CR_SHIFT) - -/* - * GW (RW) - * - * GMII Write - * When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, - * it indicates that this is a Read operation, that is, placing the data in the GMII Data register. - */ -#define ENET_GMII_ADDR_GW_MASK (0x2U) -#define ENET_GMII_ADDR_GW_SHIFT (1U) -#define ENET_GMII_ADDR_GW_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GW_SHIFT) & ENET_GMII_ADDR_GW_MASK) -#define ENET_GMII_ADDR_GW_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GW_MASK) >> ENET_GMII_ADDR_GW_SHIFT) - -/* - * GB (RW) - * - * GMII Busy - * This bit should read logic 0 before writing to Register 4 and Register 5. - * During a PHY or RevMII register access, the software sets this bit to 1’b1 to indicate that a Read or Write access is in progress. - * Register 5 is invalid until this bit is cleared by the MAC. - * Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. - * Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. - * The subsequent read or write operation should happen only after the previous operation is complete. - * Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, - * there is no change in the functionality of this bit even when the PHY is not present. - */ -#define ENET_GMII_ADDR_GB_MASK (0x1U) -#define ENET_GMII_ADDR_GB_SHIFT (0U) -#define ENET_GMII_ADDR_GB_SET(x) (((uint32_t)(x) << ENET_GMII_ADDR_GB_SHIFT) & ENET_GMII_ADDR_GB_MASK) -#define ENET_GMII_ADDR_GB_GET(x) (((uint32_t)(x) & ENET_GMII_ADDR_GB_MASK) >> ENET_GMII_ADDR_GB_SHIFT) - -/* Bitfield definition for register: GMII_DATA */ -/* - * GD (RW) - * - * GMII Data - * This field contains the 16-bit data value read from the PHY or RevMII after a Management Read operation - * or the 16-bit data value to be written to the PHY or RevMII before a Management Write operation. - */ -#define ENET_GMII_DATA_GD_MASK (0xFFFFU) -#define ENET_GMII_DATA_GD_SHIFT (0U) -#define ENET_GMII_DATA_GD_SET(x) (((uint32_t)(x) << ENET_GMII_DATA_GD_SHIFT) & ENET_GMII_DATA_GD_MASK) -#define ENET_GMII_DATA_GD_GET(x) (((uint32_t)(x) & ENET_GMII_DATA_GD_MASK) >> ENET_GMII_DATA_GD_SHIFT) - -/* Bitfield definition for register: FLOWCTRL */ -/* - * PT (RW) - * - * Pause Time - * This field holds the value to be used in the Pause Time field in the transmit control frame. - * If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, - * then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. - */ -#define ENET_FLOWCTRL_PT_MASK (0xFFFF0000UL) -#define ENET_FLOWCTRL_PT_SHIFT (16U) -#define ENET_FLOWCTRL_PT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PT_SHIFT) & ENET_FLOWCTRL_PT_MASK) -#define ENET_FLOWCTRL_PT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PT_MASK) >> ENET_FLOWCTRL_PT_SHIFT) - -/* - * DZPQ (RW) - * - * Disable Zero-Quanta Pause - * When this bit is set, it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of - * the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i). - * When this bit is reset, normal operation with automatic Zero-Quanta Pause frame generation is enabled. - */ -#define ENET_FLOWCTRL_DZPQ_MASK (0x80U) -#define ENET_FLOWCTRL_DZPQ_SHIFT (7U) -#define ENET_FLOWCTRL_DZPQ_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_DZPQ_SHIFT) & ENET_FLOWCTRL_DZPQ_MASK) -#define ENET_FLOWCTRL_DZPQ_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_DZPQ_MASK) >> ENET_FLOWCTRL_DZPQ_SHIFT) - -/* - * PLT (RW) - * - * Pause Low Threshold - * This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause frame. - * The threshold values should be always less than the Pause Time configured in Bits[31:16]. - * For example, if PT = 100H (256 slot-times), and PLT = 01, - * then a second Pause frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 – 28) slot times after the first Pause frame is transmitted. - * The following list provides the threshold values for different values: - * - 00: The threshold is Pause time minus 4 slot times (PT – 4 slot times). - * - 01: The threshold is Pause time minus 28 slot times (PT – 28 slot times). - * - 10: The threshold is Pause time minus 144 slot times (PT – 144 slot times). - * - 11: The threshold is Pause time minus 256 slot times (PT – 256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface. - */ -#define ENET_FLOWCTRL_PLT_MASK (0x30U) -#define ENET_FLOWCTRL_PLT_SHIFT (4U) -#define ENET_FLOWCTRL_PLT_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_PLT_SHIFT) & ENET_FLOWCTRL_PLT_MASK) -#define ENET_FLOWCTRL_PLT_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_PLT_MASK) >> ENET_FLOWCTRL_PLT_SHIFT) - -/* - * UP (RW) - * - * Unicast Pause Frame Detect A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. - * When this bit is set, the MAC can also detect Pause frames with unicast address of the station. - * This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register. - * When this bit is reset, the MAC only detects Pause frames with unique multicast address. - */ -#define ENET_FLOWCTRL_UP_MASK (0x8U) -#define ENET_FLOWCTRL_UP_SHIFT (3U) -#define ENET_FLOWCTRL_UP_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_UP_SHIFT) & ENET_FLOWCTRL_UP_MASK) -#define ENET_FLOWCTRL_UP_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_UP_MASK) >> ENET_FLOWCTRL_UP_SHIFT) - -/* - * RFE (RW) - * - * Receive Flow Control Enable - * When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled. - */ -#define ENET_FLOWCTRL_RFE_MASK (0x4U) -#define ENET_FLOWCTRL_RFE_SHIFT (2U) -#define ENET_FLOWCTRL_RFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_RFE_SHIFT) & ENET_FLOWCTRL_RFE_MASK) -#define ENET_FLOWCTRL_RFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_RFE_MASK) >> ENET_FLOWCTRL_RFE_SHIFT) - -/* - * TFE (RW) - * - * Transmit Flow Control Enable - * In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. - * When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames. - * In the half-duplex mode, when this bit is set, the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is disabled. - */ -#define ENET_FLOWCTRL_TFE_MASK (0x2U) -#define ENET_FLOWCTRL_TFE_SHIFT (1U) -#define ENET_FLOWCTRL_TFE_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_TFE_SHIFT) & ENET_FLOWCTRL_TFE_MASK) -#define ENET_FLOWCTRL_TFE_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_TFE_MASK) >> ENET_FLOWCTRL_TFE_SHIFT) - -/* - * FCB_BPA (RW) - * - * Flow Control Busy or Backpressure Activate - * This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. - * In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. - * To initiate a Pause frame, the Application must set this bit to 1'b1. - * During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. - * After the completion of Pause frame transmission, the MAC resets this bit to 1'b0. - * The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode, - * when this bit is set (and TFE is set), then backpressure is asserted by the MAC. - * During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. - * This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. - * When the MAC is configured for the full-duplex mode, the BPA is automatically disabled. - */ -#define ENET_FLOWCTRL_FCB_BPA_MASK (0x1U) -#define ENET_FLOWCTRL_FCB_BPA_SHIFT (0U) -#define ENET_FLOWCTRL_FCB_BPA_SET(x) (((uint32_t)(x) << ENET_FLOWCTRL_FCB_BPA_SHIFT) & ENET_FLOWCTRL_FCB_BPA_MASK) -#define ENET_FLOWCTRL_FCB_BPA_GET(x) (((uint32_t)(x) & ENET_FLOWCTRL_FCB_BPA_MASK) >> ENET_FLOWCTRL_FCB_BPA_SHIFT) - -/* Bitfield definition for register: VLAN_TAG */ -/* - * VTHM (RW) - * - * VLAN Tag Hash Table Match Enable - * When set, the most significant four bits of the VLAN tag’s CRC are used to index the content of Register 354 (VLAN Hash Table Register). - * A value of 1 in the VLAN Hash Table register, corresponding to the index, indicates that the frame matched the VLAN hash table. - * When Bit 16 (ETV) is set, the CRC of the 12-bit VLAN Identifier (VID) is used for comparison whereas when ETV is reset, - * the CRC of the 16-bit VLAN tag is used for comparison. When reset, the VLAN Hash Match operation is not performed. - */ -#define ENET_VLAN_TAG_VTHM_MASK (0x80000UL) -#define ENET_VLAN_TAG_VTHM_SHIFT (19U) -#define ENET_VLAN_TAG_VTHM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTHM_SHIFT) & ENET_VLAN_TAG_VTHM_MASK) -#define ENET_VLAN_TAG_VTHM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTHM_MASK) >> ENET_VLAN_TAG_VTHM_SHIFT) - -/* - * ESVL (RW) - * - * Enable S-VLAN - * When this bit is set, the MAC transmitter and receiver also consider the S-VLAN (Type = 0x88A8) frames as valid VLAN tagged frames. - */ -#define ENET_VLAN_TAG_ESVL_MASK (0x40000UL) -#define ENET_VLAN_TAG_ESVL_SHIFT (18U) -#define ENET_VLAN_TAG_ESVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ESVL_SHIFT) & ENET_VLAN_TAG_ESVL_MASK) -#define ENET_VLAN_TAG_ESVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ESVL_MASK) >> ENET_VLAN_TAG_ESVL_SHIFT) - -/* - * VTIM (RW) - * - * VLAN Tag Inverse Match Enable - * When set, this bit enables the VLAN Tag inverse matching. The frames that do not have matching VLAN Tag are marked as matched. When reset, this bit enables the VLAN Tag perfect matching. - * The frames with matched VLAN Tag are marked as matched. - */ -#define ENET_VLAN_TAG_VTIM_MASK (0x20000UL) -#define ENET_VLAN_TAG_VTIM_SHIFT (17U) -#define ENET_VLAN_TAG_VTIM_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VTIM_SHIFT) & ENET_VLAN_TAG_VTIM_MASK) -#define ENET_VLAN_TAG_VTIM_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VTIM_MASK) >> ENET_VLAN_TAG_VTIM_SHIFT) - -/* - * ETV (RW) - * - * Enable 12-Bit VLAN Tag Comparison - * When this bit is set, a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. - * Bits [11:0] of VLAN tag are compared with the corresponding field in the received VLAN-tagged frame. Similarly, when enabled, - * only 12 bits of the VLAN tag in the received frame are used for hash-based VLAN filtering. - * When this bit is reset, all 16 bits of the 15th and 16th bytes of the received VLAN frame are used for comparison and VLAN hash filtering. - */ -#define ENET_VLAN_TAG_ETV_MASK (0x10000UL) -#define ENET_VLAN_TAG_ETV_SHIFT (16U) -#define ENET_VLAN_TAG_ETV_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_ETV_SHIFT) & ENET_VLAN_TAG_ETV_MASK) -#define ENET_VLAN_TAG_ETV_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_ETV_MASK) >> ENET_VLAN_TAG_ETV_SHIFT) - -/* - * VL (RW) - * - * VLAN Tag Identifier for Receive Frames - * This field contains the 802.1Q VLAN tag to identify the VLAN frames and is compared to the 15th and 16th bytes of the frames being received for VLAN frames. - * The following list describes the bits of this field: - * - Bits [15:13]: User Priority - * - Bit 12: Canonical Format Indicator (CFI) or Drop Eligible Indicator (DEI) - * - Bits[11:0]: VLAN tag’s VLAN Identifier (VID) field When the ETV bit is set, only the VID (Bits[11:0]) is used for comparison. - * If VL (VL[11:0] if ETV is set) is all zeros, the MAC does not check the fifteenth and 16th bytes for VLAN tag comparison, - * and declares all frames with a Type field value of 0x8100 or 0x88a8 as VLAN frames. - */ -#define ENET_VLAN_TAG_VL_MASK (0xFFFFU) -#define ENET_VLAN_TAG_VL_SHIFT (0U) -#define ENET_VLAN_TAG_VL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_VL_SHIFT) & ENET_VLAN_TAG_VL_MASK) -#define ENET_VLAN_TAG_VL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_VL_MASK) >> ENET_VLAN_TAG_VL_SHIFT) - -/* Bitfield definition for register: RWKFRMFILT */ -/* - * WKUPFRMFILT (RW) - * - * This is the address through which the application writes or reads the remote wake-up frame filter registers (wkupfmfilter_reg). - * The wkupfmfilter_reg register is a pointer to eight wkupfmfilter_reg registers. - * The wkupfmfilter_reg register is loaded by sequentially loading the eight register values. - * Eight sequential writes to this address (0x0028) write all wkupfmfilter_reg registers. - * Similarly, eight sequential reads from this address (0x0028) read all wkupfmfilter_reg registers - */ -#define ENET_RWKFRMFILT_WKUPFRMFILT_MASK (0xFFFFFFFFUL) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT (0U) -#define ENET_RWKFRMFILT_WKUPFRMFILT_SET(x) (((uint32_t)(x) << ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) -#define ENET_RWKFRMFILT_WKUPFRMFILT_GET(x) (((uint32_t)(x) & ENET_RWKFRMFILT_WKUPFRMFILT_MASK) >> ENET_RWKFRMFILT_WKUPFRMFILT_SHIFT) - -/* Bitfield definition for register: PMT_CSR */ -/* - * RWKFILTRST (RW) - * - * Remote Wake-Up Frame Filter Register Pointer Reset - * When this bit is set, it resets the remote wake-up frame filter register pointer to 3’b000. It is automatically cleared after 1 clock cycle. - */ -#define ENET_PMT_CSR_RWKFILTRST_MASK (0x80000000UL) -#define ENET_PMT_CSR_RWKFILTRST_SHIFT (31U) -#define ENET_PMT_CSR_RWKFILTRST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKFILTRST_SHIFT) & ENET_PMT_CSR_RWKFILTRST_MASK) -#define ENET_PMT_CSR_RWKFILTRST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKFILTRST_MASK) >> ENET_PMT_CSR_RWKFILTRST_SHIFT) - -/* - * RWKPTR (RW) - * - * Remote Wake-up FIFO Pointer - * This field gives the current value (0 to 31) of the Remote Wake-up Frame filter register pointer. When the value of this pointer is equal to 7, 15, 23 or 31, - * the contents of the Remote Wake-up Frame Filter Register are transferred to the clk_rx_i domain when a write occurs to that register. - * The maximum value of the pointer is 7, 15, 23 and 31 respectively depending on the number of Remote Wakeup Filters selected during configuration. - */ -#define ENET_PMT_CSR_RWKPTR_MASK (0x1F000000UL) -#define ENET_PMT_CSR_RWKPTR_SHIFT (24U) -#define ENET_PMT_CSR_RWKPTR_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPTR_SHIFT) & ENET_PMT_CSR_RWKPTR_MASK) -#define ENET_PMT_CSR_RWKPTR_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPTR_MASK) >> ENET_PMT_CSR_RWKPTR_SHIFT) - -/* - * GLBLUCAST (RW) - * - * Global Unicast - * When set, enables any unicast packet filtered by the MAC (DAF) address recognition to be a remote wake-up frame. - */ -#define ENET_PMT_CSR_GLBLUCAST_MASK (0x200U) -#define ENET_PMT_CSR_GLBLUCAST_SHIFT (9U) -#define ENET_PMT_CSR_GLBLUCAST_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_GLBLUCAST_SHIFT) & ENET_PMT_CSR_GLBLUCAST_MASK) -#define ENET_PMT_CSR_GLBLUCAST_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_GLBLUCAST_MASK) >> ENET_PMT_CSR_GLBLUCAST_SHIFT) - -/* - * RWKPRCVD (RW) - * - * Remote Wake-Up Frame Received - * When set, this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_RWKPRCVD_MASK (0x40U) -#define ENET_PMT_CSR_RWKPRCVD_SHIFT (6U) -#define ENET_PMT_CSR_RWKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPRCVD_SHIFT) & ENET_PMT_CSR_RWKPRCVD_MASK) -#define ENET_PMT_CSR_RWKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPRCVD_MASK) >> ENET_PMT_CSR_RWKPRCVD_SHIFT) - -/* - * MGKPRCVD (RW) - * - * Magic Packet Received - * When set, this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. - */ -#define ENET_PMT_CSR_MGKPRCVD_MASK (0x20U) -#define ENET_PMT_CSR_MGKPRCVD_SHIFT (5U) -#define ENET_PMT_CSR_MGKPRCVD_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPRCVD_SHIFT) & ENET_PMT_CSR_MGKPRCVD_MASK) -#define ENET_PMT_CSR_MGKPRCVD_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPRCVD_MASK) >> ENET_PMT_CSR_MGKPRCVD_SHIFT) - -/* - * RWKPKTEN (RW) - * - * Remote Wake-Up Frame Enable - * When set, enables generation of a power management event because of remote wake-up frame reception. - */ -#define ENET_PMT_CSR_RWKPKTEN_MASK (0x4U) -#define ENET_PMT_CSR_RWKPKTEN_SHIFT (2U) -#define ENET_PMT_CSR_RWKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_RWKPKTEN_SHIFT) & ENET_PMT_CSR_RWKPKTEN_MASK) -#define ENET_PMT_CSR_RWKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_RWKPKTEN_MASK) >> ENET_PMT_CSR_RWKPKTEN_SHIFT) - -/* - * MGKPKTEN (RW) - * - * Magic Packet Enable - * When set, enables generation of a power management event because of magic packet reception. - */ -#define ENET_PMT_CSR_MGKPKTEN_MASK (0x2U) -#define ENET_PMT_CSR_MGKPKTEN_SHIFT (1U) -#define ENET_PMT_CSR_MGKPKTEN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_MGKPKTEN_SHIFT) & ENET_PMT_CSR_MGKPKTEN_MASK) -#define ENET_PMT_CSR_MGKPKTEN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_MGKPKTEN_MASK) >> ENET_PMT_CSR_MGKPKTEN_SHIFT) - -/* - * PWRDWN (RW) - * - * Power Down - * When set, the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame. - * This bit is then self-cleared and the power-down mode is disabled. - * The Software can also clear this bit before the expected magic packet or remote wake-up frame is received. - * The frames, received by the MAC after this bit is cleared, are forwarded to the application. - * This bit must only be set when the Magic Packet Enable, Global Unicast, or Remote Wake-Upr Fame Enable bit is set high. - * Note: You can gate-off the CSR clock during the power-down mode. - * However, when the CSR clock is gated-off, you cannot perform any read or write operations on this register. Therefore, the Software cannot clear this bit. - */ -#define ENET_PMT_CSR_PWRDWN_MASK (0x1U) -#define ENET_PMT_CSR_PWRDWN_SHIFT (0U) -#define ENET_PMT_CSR_PWRDWN_SET(x) (((uint32_t)(x) << ENET_PMT_CSR_PWRDWN_SHIFT) & ENET_PMT_CSR_PWRDWN_MASK) -#define ENET_PMT_CSR_PWRDWN_GET(x) (((uint32_t)(x) & ENET_PMT_CSR_PWRDWN_MASK) >> ENET_PMT_CSR_PWRDWN_SHIFT) - -/* Bitfield definition for register: LPI_CSR */ -/* - * LPITXA (RW) - * - * LPI TX Automate - * This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. - * This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, - * the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. - * The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. - * In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. - * If TX FIFO Flush is set in Bit 20 of Register 6 (Operation Mode Register), - * when the MAC is in the LPI mode, the MAC exits the LPI mode. - * When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. - */ -#define ENET_LPI_CSR_LPITXA_MASK (0x80000UL) -#define ENET_LPI_CSR_LPITXA_SHIFT (19U) -#define ENET_LPI_CSR_LPITXA_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPITXA_SHIFT) & ENET_LPI_CSR_LPITXA_MASK) -#define ENET_LPI_CSR_LPITXA_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPITXA_MASK) >> ENET_LPI_CSR_LPITXA_SHIFT) - -/* - * PLSEN (RW) - * - * PHY Link Status Enable - * This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. - * When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Control and Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. - * When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. - */ -#define ENET_LPI_CSR_PLSEN_MASK (0x40000UL) -#define ENET_LPI_CSR_PLSEN_SHIFT (18U) -#define ENET_LPI_CSR_PLSEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLSEN_SHIFT) & ENET_LPI_CSR_PLSEN_MASK) -#define ENET_LPI_CSR_PLSEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLSEN_MASK) >> ENET_LPI_CSR_PLSEN_SHIFT) - -/* - * PLS (RW) - * - * PHY Link Status - * This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. - * When set, the link is considered to be okay (up) and when reset, the link is considered to be down. - */ -#define ENET_LPI_CSR_PLS_MASK (0x20000UL) -#define ENET_LPI_CSR_PLS_SHIFT (17U) -#define ENET_LPI_CSR_PLS_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_PLS_SHIFT) & ENET_LPI_CSR_PLS_MASK) -#define ENET_LPI_CSR_PLS_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_PLS_MASK) >> ENET_LPI_CSR_PLS_SHIFT) - -/* - * LPIEN (RW) - * - * LPI Enable - * When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. - * This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. - */ -#define ENET_LPI_CSR_LPIEN_MASK (0x10000UL) -#define ENET_LPI_CSR_LPIEN_SHIFT (16U) -#define ENET_LPI_CSR_LPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_LPIEN_SHIFT) & ENET_LPI_CSR_LPIEN_MASK) -#define ENET_LPI_CSR_LPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_LPIEN_MASK) >> ENET_LPI_CSR_LPIEN_SHIFT) - -/* - * RLPIST (RW) - * - * Receive LPI State - * When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_RLPIST_MASK (0x200U) -#define ENET_LPI_CSR_RLPIST_SHIFT (9U) -#define ENET_LPI_CSR_RLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIST_SHIFT) & ENET_LPI_CSR_RLPIST_MASK) -#define ENET_LPI_CSR_RLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIST_MASK) >> ENET_LPI_CSR_RLPIST_SHIFT) - -/* - * TLPIST (RW) - * - * Transmit LPI State - * When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. - */ -#define ENET_LPI_CSR_TLPIST_MASK (0x100U) -#define ENET_LPI_CSR_TLPIST_SHIFT (8U) -#define ENET_LPI_CSR_TLPIST_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIST_SHIFT) & ENET_LPI_CSR_TLPIST_MASK) -#define ENET_LPI_CSR_TLPIST_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIST_MASK) >> ENET_LPI_CSR_TLPIST_SHIFT) - -/* - * RLPIEX (RW) - * - * Receive LPI Exit - * When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. - * This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEX_MASK (0x8U) -#define ENET_LPI_CSR_RLPIEX_SHIFT (3U) -#define ENET_LPI_CSR_RLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEX_SHIFT) & ENET_LPI_CSR_RLPIEX_MASK) -#define ENET_LPI_CSR_RLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEX_MASK) >> ENET_LPI_CSR_RLPIEX_SHIFT) - -/* - * RLPIEN (RW) - * - * Receive LPI Entry - * When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. - * Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. - */ -#define ENET_LPI_CSR_RLPIEN_MASK (0x4U) -#define ENET_LPI_CSR_RLPIEN_SHIFT (2U) -#define ENET_LPI_CSR_RLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_RLPIEN_SHIFT) & ENET_LPI_CSR_RLPIEN_MASK) -#define ENET_LPI_CSR_RLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_RLPIEN_MASK) >> ENET_LPI_CSR_RLPIEN_SHIFT) - -/* - * TLPIEX (RW) - * - * Transmit LPI Exit - * When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEX_MASK (0x2U) -#define ENET_LPI_CSR_TLPIEX_SHIFT (1U) -#define ENET_LPI_CSR_TLPIEX_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEX_SHIFT) & ENET_LPI_CSR_TLPIEX_MASK) -#define ENET_LPI_CSR_TLPIEX_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEX_MASK) >> ENET_LPI_CSR_TLPIEX_SHIFT) - -/* - * TLPIEN (RW) - * - * Transmit LPI Entry - * When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. - */ -#define ENET_LPI_CSR_TLPIEN_MASK (0x1U) -#define ENET_LPI_CSR_TLPIEN_SHIFT (0U) -#define ENET_LPI_CSR_TLPIEN_SET(x) (((uint32_t)(x) << ENET_LPI_CSR_TLPIEN_SHIFT) & ENET_LPI_CSR_TLPIEN_MASK) -#define ENET_LPI_CSR_TLPIEN_GET(x) (((uint32_t)(x) & ENET_LPI_CSR_TLPIEN_MASK) >> ENET_LPI_CSR_TLPIEN_SHIFT) - -/* Bitfield definition for register: LPI_TCR */ -/* - * LST (RW) - * - * LPI LS TIMER - * This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. - * The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. - * The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard. - */ -#define ENET_LPI_TCR_LST_MASK (0x3FF0000UL) -#define ENET_LPI_TCR_LST_SHIFT (16U) -#define ENET_LPI_TCR_LST_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_LST_SHIFT) & ENET_LPI_TCR_LST_MASK) -#define ENET_LPI_TCR_LST_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_LST_MASK) >> ENET_LPI_TCR_LST_SHIFT) - -/* - * TWT (RW) - * - * LPI TW TIMER - * This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting - * the LPI pattern to the PHY and before it resumes the normal transmission. - * The TLPIEX status bit is set after the expiry of this timer. - */ -#define ENET_LPI_TCR_TWT_MASK (0xFFFFU) -#define ENET_LPI_TCR_TWT_SHIFT (0U) -#define ENET_LPI_TCR_TWT_SET(x) (((uint32_t)(x) << ENET_LPI_TCR_TWT_SHIFT) & ENET_LPI_TCR_TWT_MASK) -#define ENET_LPI_TCR_TWT_GET(x) (((uint32_t)(x) & ENET_LPI_TCR_TWT_MASK) >> ENET_LPI_TCR_TWT_SHIFT) - -/* Bitfield definition for register: INTR_STATUS */ -/* - * GPIIS (RO) - * - * GPI Interrupt Status - * When the GPIO feature is enabled, this bit is set when any active event (LL or LH) occurs on the GPIS field (Bits [3:0]) - * of Register 56 (General Purpose IO Register) and the corresponding GPIE bit is enabled. - * This bit is cleared on reading lane 0 (GPIS) of Register 56 (General Purpose IO Register). - * When the GPIO feature is not enabled, this bit is reserved. - */ -#define ENET_INTR_STATUS_GPIIS_MASK (0x800U) -#define ENET_INTR_STATUS_GPIIS_SHIFT (11U) -#define ENET_INTR_STATUS_GPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_GPIIS_MASK) >> ENET_INTR_STATUS_GPIIS_SHIFT) - -/* - * LPIIS (RO) - * - * LPI Interrupt Status - * When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. - * This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved. - */ -#define ENET_INTR_STATUS_LPIIS_MASK (0x400U) -#define ENET_INTR_STATUS_LPIIS_SHIFT (10U) -#define ENET_INTR_STATUS_LPIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_LPIIS_MASK) >> ENET_INTR_STATUS_LPIIS_SHIFT) - -/* - * TSIS (RO) - * - * Timestamp Interrupt Status - * When the Advanced Timestamp feature is enabled, this bit is set when any of the following conditions is true: - * - The system time value equals or exceeds the value specified in the Target Time High and Low registers. - * - There is an overflow in the seconds register. - * - The Auxiliary snapshot trigger is asserted. This bit is cleared on reading Bit 0 of Register 458 (Timestamp Status Register). - */ -#define ENET_INTR_STATUS_TSIS_MASK (0x200U) -#define ENET_INTR_STATUS_TSIS_SHIFT (9U) -#define ENET_INTR_STATUS_TSIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_TSIS_MASK) >> ENET_INTR_STATUS_TSIS_SHIFT) - -/* - * MMCRXIPIS (RO) - * - * MMC Receive Checksum Offload Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIPIS_MASK (0x80U) -#define ENET_INTR_STATUS_MMCRXIPIS_SHIFT (7U) -#define ENET_INTR_STATUS_MMCRXIPIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIPIS_MASK) >> ENET_INTR_STATUS_MMCRXIPIS_SHIFT) - -/* - * MMCTXIS (RO) - * - * MMC Transmit Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCTXIS_MASK (0x40U) -#define ENET_INTR_STATUS_MMCTXIS_SHIFT (6U) -#define ENET_INTR_STATUS_MMCTXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCTXIS_MASK) >> ENET_INTR_STATUS_MMCTXIS_SHIFT) - -/* - * MMCRXIS (RO) - * - * MMC Receive Interrupt Status - * This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared. - */ -#define ENET_INTR_STATUS_MMCRXIS_MASK (0x20U) -#define ENET_INTR_STATUS_MMCRXIS_SHIFT (5U) -#define ENET_INTR_STATUS_MMCRXIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCRXIS_MASK) >> ENET_INTR_STATUS_MMCRXIS_SHIFT) - -/* - * MMCIS (RO) - * - * MMC Interrupt Status - * This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low. - */ -#define ENET_INTR_STATUS_MMCIS_MASK (0x10U) -#define ENET_INTR_STATUS_MMCIS_SHIFT (4U) -#define ENET_INTR_STATUS_MMCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_MMCIS_MASK) >> ENET_INTR_STATUS_MMCIS_SHIFT) - -/* - * PMTIS (RO) - * - * PMT Interrupt Status - * This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bits 5 and 6 in the PMT Control and Status Register). - * This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. - */ -#define ENET_INTR_STATUS_PMTIS_MASK (0x8U) -#define ENET_INTR_STATUS_PMTIS_SHIFT (3U) -#define ENET_INTR_STATUS_PMTIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PMTIS_MASK) >> ENET_INTR_STATUS_PMTIS_SHIFT) - -/* - * PCSANCIS (RO) - * - * PCS Auto-Negotiation Complete - * This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation to the AN Status register. - */ -#define ENET_INTR_STATUS_PCSANCIS_MASK (0x4U) -#define ENET_INTR_STATUS_PCSANCIS_SHIFT (2U) -#define ENET_INTR_STATUS_PCSANCIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSANCIS_MASK) >> ENET_INTR_STATUS_PCSANCIS_SHIFT) - -/* - * PCSLCHGIS (RO) - * - * PCS Link Status Changed - * This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). - * This bit is cleared when you perform a read operation on the AN Status register. - */ -#define ENET_INTR_STATUS_PCSLCHGIS_MASK (0x2U) -#define ENET_INTR_STATUS_PCSLCHGIS_SHIFT (1U) -#define ENET_INTR_STATUS_PCSLCHGIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_PCSLCHGIS_MASK) >> ENET_INTR_STATUS_PCSLCHGIS_SHIFT) - -/* - * RGSMIIIS (RO) - * - * RGMII or SMII Interrupt Status - * This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Control and Status Register)). - * This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Control and Status Register. - */ -#define ENET_INTR_STATUS_RGSMIIIS_MASK (0x1U) -#define ENET_INTR_STATUS_RGSMIIIS_SHIFT (0U) -#define ENET_INTR_STATUS_RGSMIIIS_GET(x) (((uint32_t)(x) & ENET_INTR_STATUS_RGSMIIIS_MASK) >> ENET_INTR_STATUS_RGSMIIIS_SHIFT) - -/* Bitfield definition for register: INTR_MASK */ -/* - * LPIIM (RW) - * - * LPI Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_LPIIM_MASK (0x400U) -#define ENET_INTR_MASK_LPIIM_SHIFT (10U) -#define ENET_INTR_MASK_LPIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_LPIIM_SHIFT) & ENET_INTR_MASK_LPIIM_MASK) -#define ENET_INTR_MASK_LPIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_LPIIM_MASK) >> ENET_INTR_MASK_LPIIM_SHIFT) - -/* - * TSIM (RW) - * - * Timestamp Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_TSIM_MASK (0x200U) -#define ENET_INTR_MASK_TSIM_SHIFT (9U) -#define ENET_INTR_MASK_TSIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_TSIM_SHIFT) & ENET_INTR_MASK_TSIM_MASK) -#define ENET_INTR_MASK_TSIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_TSIM_MASK) >> ENET_INTR_MASK_TSIM_SHIFT) - -/* - * PMTIM (RW) - * - * PMT Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PMTIM_MASK (0x8U) -#define ENET_INTR_MASK_PMTIM_SHIFT (3U) -#define ENET_INTR_MASK_PMTIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PMTIM_SHIFT) & ENET_INTR_MASK_PMTIM_MASK) -#define ENET_INTR_MASK_PMTIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PMTIM_MASK) >> ENET_INTR_MASK_PMTIM_SHIFT) - -/* - * PCSANCIM (RW) - * - * PCS AN Completion Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSANCIM_MASK (0x4U) -#define ENET_INTR_MASK_PCSANCIM_SHIFT (2U) -#define ENET_INTR_MASK_PCSANCIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSANCIM_SHIFT) & ENET_INTR_MASK_PCSANCIM_MASK) -#define ENET_INTR_MASK_PCSANCIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSANCIM_MASK) >> ENET_INTR_MASK_PCSANCIM_SHIFT) - -/* - * PCSLCHGIM (RW) - * - * PCS Link Status Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_PCSLCHGIM_MASK (0x2U) -#define ENET_INTR_MASK_PCSLCHGIM_SHIFT (1U) -#define ENET_INTR_MASK_PCSLCHGIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_PCSLCHGIM_SHIFT) & ENET_INTR_MASK_PCSLCHGIM_MASK) -#define ENET_INTR_MASK_PCSLCHGIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_PCSLCHGIM_MASK) >> ENET_INTR_MASK_PCSLCHGIM_SHIFT) - -/* - * RGSMIIIM (RW) - * - * RGMII or SMII Interrupt Mask - * When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register). - */ -#define ENET_INTR_MASK_RGSMIIIM_MASK (0x1U) -#define ENET_INTR_MASK_RGSMIIIM_SHIFT (0U) -#define ENET_INTR_MASK_RGSMIIIM_SET(x) (((uint32_t)(x) << ENET_INTR_MASK_RGSMIIIM_SHIFT) & ENET_INTR_MASK_RGSMIIIM_MASK) -#define ENET_INTR_MASK_RGSMIIIM_GET(x) (((uint32_t)(x) & ENET_INTR_MASK_RGSMIIIM_MASK) >> ENET_INTR_MASK_RGSMIIIM_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_HIGH */ -/* - * AE (RO) - * - * Address Enable - * This bit is RO. The bit value is fixed at 1. - */ -#define ENET_MAC_ADDR_0_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_0_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_0_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_AE_MASK) >> ENET_MAC_ADDR_0_HIGH_AE_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address0 [47:32] - * This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_0_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_0_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register: MAC_ADDR_0_LOW */ -/* - * ADDRLO (RW) - * - * MAC Address0 [31:0] - * This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. - */ -#define ENET_MAC_ADDR_0_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_0_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_0_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_0_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: HIGH */ -/* - * AE (RW) - * - * Address Enable - * When this bit is set, the address filter module uses the second MAC address for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering. - */ -#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000UL) -#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) -#define ENET_MAC_ADDR_HIGH_AE_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_AE_SHIFT) & ENET_MAC_ADDR_HIGH_AE_MASK) -#define ENET_MAC_ADDR_HIGH_AE_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_AE_MASK) >> ENET_MAC_ADDR_HIGH_AE_SHIFT) - -/* - * SA (RW) - * - * Source Address - * When this bit is set, the MAC Address1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset, the MAC Address1[47:0] is used to compare with the DA fields of the received frame. - */ -#define ENET_MAC_ADDR_HIGH_SA_MASK (0x40000000UL) -#define ENET_MAC_ADDR_HIGH_SA_SHIFT (30U) -#define ENET_MAC_ADDR_HIGH_SA_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_SA_SHIFT) & ENET_MAC_ADDR_HIGH_SA_MASK) -#define ENET_MAC_ADDR_HIGH_SA_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_SA_MASK) >> ENET_MAC_ADDR_HIGH_SA_SHIFT) - -/* - * MBC (RW) - * - * Mask Byte Control - * These bits are mask control bits for comparison of each of the MAC Address bytes. - * When set high, the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. - * Each bit controls the masking of the bytes as follows: - * - Bit 29: Register 18[15:8] - * - Bit 28: Register 18[7:0] - * - Bit 27: Register 19[31:24] - - * ... - * - Bit 24: Register 19[7:0] - * You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address. - */ -#define ENET_MAC_ADDR_HIGH_MBC_MASK (0x3F000000UL) -#define ENET_MAC_ADDR_HIGH_MBC_SHIFT (24U) -#define ENET_MAC_ADDR_HIGH_MBC_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_MBC_SHIFT) & ENET_MAC_ADDR_HIGH_MBC_MASK) -#define ENET_MAC_ADDR_HIGH_MBC_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_MBC_MASK) >> ENET_MAC_ADDR_HIGH_MBC_SHIFT) - -/* - * ADDRHI (RW) - * - * MAC Address1 [47:32] - * This field contains the upper 16 bits (47:32) of the second 6-byte MAC address. - */ -#define ENET_MAC_ADDR_HIGH_ADDRHI_MASK (0xFFFFU) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT (0U) -#define ENET_MAC_ADDR_HIGH_ADDRHI_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) -#define ENET_MAC_ADDR_HIGH_ADDRHI_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_HIGH_ADDRHI_MASK) >> ENET_MAC_ADDR_HIGH_ADDRHI_SHIFT) - -/* Bitfield definition for register of struct array MAC_ADDR: LOW */ -/* - * ADDRLO (RW) - * - * MAC Address1 [31:0] - * This field contains the lower 32 bits of the second 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process. - */ -#define ENET_MAC_ADDR_LOW_ADDRLO_MASK (0xFFFFFFFFUL) -#define ENET_MAC_ADDR_LOW_ADDRLO_SHIFT (0U) -#define ENET_MAC_ADDR_LOW_ADDRLO_SET(x) (((uint32_t)(x) << ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) -#define ENET_MAC_ADDR_LOW_ADDRLO_GET(x) (((uint32_t)(x) & ENET_MAC_ADDR_LOW_ADDRLO_MASK) >> ENET_MAC_ADDR_LOW_ADDRLO_SHIFT) - -/* Bitfield definition for register: XMII_CSR */ -/* - * FALSCARDET (RW) - * - * False Carrier Detected - * This bit indicates whether the SMII PHY detected false carrier (1'b1). This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_FALSCARDET_MASK (0x20U) -#define ENET_XMII_CSR_FALSCARDET_SHIFT (5U) -#define ENET_XMII_CSR_FALSCARDET_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_FALSCARDET_SHIFT) & ENET_XMII_CSR_FALSCARDET_MASK) -#define ENET_XMII_CSR_FALSCARDET_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_FALSCARDET_MASK) >> ENET_XMII_CSR_FALSCARDET_SHIFT) - -/* - * JABTO (RW) - * - * Jabber Timeout - * This bit indicates whether there is jabber timeout error (1'b1) in the received frame. This bit is reserved when the MAC is configured for the SGMII or RGMII PHY interface. - */ -#define ENET_XMII_CSR_JABTO_MASK (0x10U) -#define ENET_XMII_CSR_JABTO_SHIFT (4U) -#define ENET_XMII_CSR_JABTO_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_JABTO_SHIFT) & ENET_XMII_CSR_JABTO_MASK) -#define ENET_XMII_CSR_JABTO_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_JABTO_MASK) >> ENET_XMII_CSR_JABTO_SHIFT) - -/* - * LNKSTS (RW) - * - * Link Status - * This bit indicates whether the link between the local PHY and the remote PHY is up or down. - * It gives the status of the link between the SGMII of MAC and the SGMII of the local PHY. - * The status bits are received from the local PHY during ANEG betweent he MAC and PHY on the SGMII link. - */ -#define ENET_XMII_CSR_LNKSTS_MASK (0x8U) -#define ENET_XMII_CSR_LNKSTS_SHIFT (3U) -#define ENET_XMII_CSR_LNKSTS_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSTS_SHIFT) & ENET_XMII_CSR_LNKSTS_MASK) -#define ENET_XMII_CSR_LNKSTS_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSTS_MASK) >> ENET_XMII_CSR_LNKSTS_SHIFT) - -/* - * LNKSPEED (RW) - * - * Link Speed - * This bit indicates the current speed of the link: - * - 00: 2.5 MHz - * - 01: 25 MHz - * - 10: 125 MHz Bit 2 is reserved when the MAC is configured for the SMII PHY interface. - */ -#define ENET_XMII_CSR_LNKSPEED_MASK (0x6U) -#define ENET_XMII_CSR_LNKSPEED_SHIFT (1U) -#define ENET_XMII_CSR_LNKSPEED_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKSPEED_SHIFT) & ENET_XMII_CSR_LNKSPEED_MASK) -#define ENET_XMII_CSR_LNKSPEED_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKSPEED_MASK) >> ENET_XMII_CSR_LNKSPEED_SHIFT) - -/* - * LNKMOD (RW) - * - * Link Mode - * This bit indicates the current mode of operation of the link: - * - 1’b0: Half-duplex mode - * - 1’b1: Full-duplex mode - */ -#define ENET_XMII_CSR_LNKMOD_MASK (0x1U) -#define ENET_XMII_CSR_LNKMOD_SHIFT (0U) -#define ENET_XMII_CSR_LNKMOD_SET(x) (((uint32_t)(x) << ENET_XMII_CSR_LNKMOD_SHIFT) & ENET_XMII_CSR_LNKMOD_MASK) -#define ENET_XMII_CSR_LNKMOD_GET(x) (((uint32_t)(x) & ENET_XMII_CSR_LNKMOD_MASK) >> ENET_XMII_CSR_LNKMOD_SHIFT) - -/* Bitfield definition for register: WDOG_WTO */ -/* - * PWE (RW) - * - * Programmable Watchdog Enable - * When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. - * When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). - */ -#define ENET_WDOG_WTO_PWE_MASK (0x10000UL) -#define ENET_WDOG_WTO_PWE_SHIFT (16U) -#define ENET_WDOG_WTO_PWE_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_PWE_SHIFT) & ENET_WDOG_WTO_PWE_MASK) -#define ENET_WDOG_WTO_PWE_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_PWE_MASK) >> ENET_WDOG_WTO_PWE_SHIFT) - -/* - * WTO (RW) - * - * Watchdog Timeout - * When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, - * this field is used as watchdog timeout for a received frame. - * If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. - * Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). - * Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. - */ -#define ENET_WDOG_WTO_WTO_MASK (0x3FFFU) -#define ENET_WDOG_WTO_WTO_SHIFT (0U) -#define ENET_WDOG_WTO_WTO_SET(x) (((uint32_t)(x) << ENET_WDOG_WTO_WTO_SHIFT) & ENET_WDOG_WTO_WTO_MASK) -#define ENET_WDOG_WTO_WTO_GET(x) (((uint32_t)(x) & ENET_WDOG_WTO_WTO_MASK) >> ENET_WDOG_WTO_WTO_SHIFT) - -/* Bitfield definition for register: MMC_CNTRL */ -/* - * UCDBC (RW) - * - * Update MMC Counters for Dropped Broadcast Frames - * When set, the MAC updates all related MMC Counters for Broadcast frames that are dropped because of the setting of Bit 5 (DBF) of Register 1 (MAC Frame Filter). - * When reset, the MMC Counters are not updated for dropped Broadcast frames. - */ -#define ENET_MMC_CNTRL_UCDBC_MASK (0x100U) -#define ENET_MMC_CNTRL_UCDBC_SHIFT (8U) -#define ENET_MMC_CNTRL_UCDBC_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_UCDBC_SHIFT) & ENET_MMC_CNTRL_UCDBC_MASK) -#define ENET_MMC_CNTRL_UCDBC_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_UCDBC_MASK) >> ENET_MMC_CNTRL_UCDBC_SHIFT) - -/* - * CNTPRSTLVL (RW) - * - * Full-Half Preset - * When this bit is low and Bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - * - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - * - 16). When this bit is high and Bit 4 is set, all MMC counters get preset to almost-full value. All octet counters get preset to 0xFFFF_F800 (full - * - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - * - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. - */ -#define ENET_MMC_CNTRL_CNTPRSTLVL_MASK (0x20U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT (5U) -#define ENET_MMC_CNTRL_CNTPRSTLVL_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) -#define ENET_MMC_CNTRL_CNTPRSTLVL_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRSTLVL_MASK) >> ENET_MMC_CNTRL_CNTPRSTLVL_SHIFT) - -/* - * CNTPRST (RW) - * - * Counters Preset - * When this bit is set, all counters are initialized or preset to almost full or almost half according to Bit 5. This bit is cleared automatically after 1 clock cycle. - * This bit, along with Bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. - */ -#define ENET_MMC_CNTRL_CNTPRST_MASK (0x10U) -#define ENET_MMC_CNTRL_CNTPRST_SHIFT (4U) -#define ENET_MMC_CNTRL_CNTPRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTPRST_SHIFT) & ENET_MMC_CNTRL_CNTPRST_MASK) -#define ENET_MMC_CNTRL_CNTPRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTPRST_MASK) >> ENET_MMC_CNTRL_CNTPRST_SHIFT) - -/* - * CNTFREEZ (RW) - * - * MMC Counter Freeze - * When this bit is set, it freezes all MMC counters to their current value. - * Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. - * If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. - */ -#define ENET_MMC_CNTRL_CNTFREEZ_MASK (0x8U) -#define ENET_MMC_CNTRL_CNTFREEZ_SHIFT (3U) -#define ENET_MMC_CNTRL_CNTFREEZ_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTFREEZ_SHIFT) & ENET_MMC_CNTRL_CNTFREEZ_MASK) -#define ENET_MMC_CNTRL_CNTFREEZ_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTFREEZ_MASK) >> ENET_MMC_CNTRL_CNTFREEZ_SHIFT) - -/* - * RSTONRD (RW) - * - * Reset on Read - * When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. - */ -#define ENET_MMC_CNTRL_RSTONRD_MASK (0x4U) -#define ENET_MMC_CNTRL_RSTONRD_SHIFT (2U) -#define ENET_MMC_CNTRL_RSTONRD_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_RSTONRD_SHIFT) & ENET_MMC_CNTRL_RSTONRD_MASK) -#define ENET_MMC_CNTRL_RSTONRD_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_RSTONRD_MASK) >> ENET_MMC_CNTRL_RSTONRD_SHIFT) - -/* - * CNTSTOPRO (RW) - * - * Counter Stop Rollover - * When this bit is set, the counter does not roll over to zero after reaching the maximum value. - */ -#define ENET_MMC_CNTRL_CNTSTOPRO_MASK (0x2U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SHIFT (1U) -#define ENET_MMC_CNTRL_CNTSTOPRO_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) -#define ENET_MMC_CNTRL_CNTSTOPRO_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTSTOPRO_MASK) >> ENET_MMC_CNTRL_CNTSTOPRO_SHIFT) - -/* - * CNTRST (RW) - * - * Counters Reset - * When this bit is set, all counters are reset. This bit is cleared automatically after 1 clock cycle - */ -#define ENET_MMC_CNTRL_CNTRST_MASK (0x1U) -#define ENET_MMC_CNTRL_CNTRST_SHIFT (0U) -#define ENET_MMC_CNTRL_CNTRST_SET(x) (((uint32_t)(x) << ENET_MMC_CNTRL_CNTRST_SHIFT) & ENET_MMC_CNTRL_CNTRST_MASK) -#define ENET_MMC_CNTRL_CNTRST_GET(x) (((uint32_t)(x) & ENET_MMC_CNTRL_CNTRST_MASK) >> ENET_MMC_CNTRL_CNTRST_SHIFT) - -/* Bitfield definition for register: MMC_INTR_RX */ -/* - * RXCTRLFIS (RW) - * - * MMC Receive Control Frame Counter Interrupt Status - * This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCTRLFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT (25U) -#define ENET_MMC_INTR_RX_RXCTRLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) -#define ENET_MMC_INTR_RX_RXCTRLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCTRLFIS_MASK) >> ENET_MMC_INTR_RX_RXCTRLFIS_SHIFT) - -/* - * RXRCVERRFIS (RW) - * - * MMC Receive Error Frame Counter Interrupt Status - * This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRCVERRFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT (24U) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) -#define ENET_MMC_INTR_RX_RXRCVERRFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRCVERRFIS_MASK) >> ENET_MMC_INTR_RX_RXRCVERRFIS_SHIFT) - -/* - * RXWDOGFIS (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Status - * This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXWDOGFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT (23U) -#define ENET_MMC_INTR_RX_RXWDOGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) -#define ENET_MMC_INTR_RX_RXWDOGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXWDOGFIS_MASK) >> ENET_MMC_INTR_RX_RXWDOGFIS_SHIFT) - -/* - * RXVLANGBFIS (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Status - * This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXVLANGBFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT (22U) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) -#define ENET_MMC_INTR_RX_RXVLANGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXVLANGBFIS_MASK) >> ENET_MMC_INTR_RX_RXVLANGBFIS_SHIFT) - -/* - * RXFOVFIS (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Status - * This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXFOVFIS_MASK (0x200000UL) -#define ENET_MMC_INTR_RX_RXFOVFIS_SHIFT (21U) -#define ENET_MMC_INTR_RX_RXFOVFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) -#define ENET_MMC_INTR_RX_RXFOVFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXFOVFIS_MASK) >> ENET_MMC_INTR_RX_RXFOVFIS_SHIFT) - -/* - * RXPAUSFIS (RW) - * - * MMC Receive Pause Frame Counter Interrupt Status - * This bit is set when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXPAUSFIS_MASK (0x100000UL) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT (20U) -#define ENET_MMC_INTR_RX_RXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) -#define ENET_MMC_INTR_RX_RXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXPAUSFIS_MASK) >> ENET_MMC_INTR_RX_RXPAUSFIS_SHIFT) - -/* - * RXORANGEFIS (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Status. - * This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXORANGEFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT (19U) -#define ENET_MMC_INTR_RX_RXORANGEFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) -#define ENET_MMC_INTR_RX_RXORANGEFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXORANGEFIS_MASK) >> ENET_MMC_INTR_RX_RXORANGEFIS_SHIFT) - -/* - * RXLENERFIS (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Status - * This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXLENERFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_RX_RXLENERFIS_SHIFT (18U) -#define ENET_MMC_INTR_RX_RXLENERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) -#define ENET_MMC_INTR_RX_RXLENERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXLENERFIS_MASK) >> ENET_MMC_INTR_RX_RXLENERFIS_SHIFT) - -/* - * RXUCGFIS (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Status - * This bit is set when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUCGFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_RX_RXUCGFIS_SHIFT (17U) -#define ENET_MMC_INTR_RX_RXUCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUCGFIS_MASK) >> ENET_MMC_INTR_RX_RXUCGFIS_SHIFT) - -/* - * RX1024TMAXOCTGBFIS (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status. - * This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT (16U) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX1024TMAXOCTGBFIS_SHIFT) - -/* - * RX512T1023OCTGBFIS (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK (0x8000U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT (15U) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX512T1023OCTGBFIS_SHIFT) - -/* - * RX256T511OCTGBFIS (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK (0x4000U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT (14U) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX256T511OCTGBFIS_SHIFT) - -/* - * RX128T255OCTGBFIS (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK (0x2000U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT (13U) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX128T255OCTGBFIS_SHIFT) - -/* - * RX65T127OCTGBFIS (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX65T127OCTGBFIS_SHIFT) - -/* - * RX64OCTGBFIS (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_RX_RX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RX64OCTGBFIS_MASK) >> ENET_MMC_INTR_RX_RX64OCTGBFIS_SHIFT) - -/* - * RXOSIZEGFIS (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Status - * This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK (0x400U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT (10U) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXOSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXOSIZEGFIS_SHIFT) - -/* - * RXUSIZEGFIS (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Status - * This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK (0x200U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT (9U) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) -#define ENET_MMC_INTR_RX_RXUSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXUSIZEGFIS_MASK) >> ENET_MMC_INTR_RX_RXUSIZEGFIS_SHIFT) - -/* - * RXJABERFIS (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Status - * This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXJABERFIS_MASK (0x100U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SHIFT (8U) -#define ENET_MMC_INTR_RX_RXJABERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) -#define ENET_MMC_INTR_RX_RXJABERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXJABERFIS_MASK) >> ENET_MMC_INTR_RX_RXJABERFIS_SHIFT) - -/* - * RXRUNTFIS (RW) - * - * MMC Receive Runt Frame Counter Interrupt Status - * This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXRUNTFIS_MASK (0x80U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT (7U) -#define ENET_MMC_INTR_RX_RXRUNTFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) -#define ENET_MMC_INTR_RX_RXRUNTFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXRUNTFIS_MASK) >> ENET_MMC_INTR_RX_RXRUNTFIS_SHIFT) - -/* - * RXALGNERFIS (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Status - * This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXALGNERFIS_MASK (0x40U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT (6U) -#define ENET_MMC_INTR_RX_RXALGNERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) -#define ENET_MMC_INTR_RX_RXALGNERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXALGNERFIS_MASK) >> ENET_MMC_INTR_RX_RXALGNERFIS_SHIFT) - -/* - * RXCRCERFIS (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Status - * This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXCRCERFIS_MASK (0x20U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT (5U) -#define ENET_MMC_INTR_RX_RXCRCERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) -#define ENET_MMC_INTR_RX_RXCRCERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXCRCERFIS_MASK) >> ENET_MMC_INTR_RX_RXCRCERFIS_SHIFT) - -/* - * RXMCGFIS (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Status - * This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXMCGFIS_MASK (0x10U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SHIFT (4U) -#define ENET_MMC_INTR_RX_RXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXMCGFIS_MASK) >> ENET_MMC_INTR_RX_RXMCGFIS_SHIFT) - -/* - * RXBCGFIS (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Status - * This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXBCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_RX_RXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) -#define ENET_MMC_INTR_RX_RXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXBCGFIS_MASK) >> ENET_MMC_INTR_RX_RXBCGFIS_SHIFT) - -/* - * RXGOCTIS (RW) - * - * MMC Receive Good Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGOCTIS_MASK (0x4U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SHIFT (2U) -#define ENET_MMC_INTR_RX_RXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGOCTIS_SHIFT) - -/* - * RXGBOCTIS (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Status - * This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBOCTIS_MASK (0x2U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT (1U) -#define ENET_MMC_INTR_RX_RXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) -#define ENET_MMC_INTR_RX_RXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBOCTIS_MASK) >> ENET_MMC_INTR_RX_RXGBOCTIS_SHIFT) - -/* - * RXGBFRMIS (RW) - * - * MMC Receive Good Bad Frame Counter Interrupt Status - * This bit is set when the rxframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_RX_RXGBFRMIS_MASK (0x1U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT (0U) -#define ENET_MMC_INTR_RX_RXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) -#define ENET_MMC_INTR_RX_RXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_RX_RXGBFRMIS_MASK) >> ENET_MMC_INTR_RX_RXGBFRMIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_TX */ -/* - * TXOSIZEGFIS (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Status - * This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK (0x2000000UL) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT (25U) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) -#define ENET_MMC_INTR_TX_TXOSIZEGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXOSIZEGFIS_MASK) >> ENET_MMC_INTR_TX_TXOSIZEGFIS_SHIFT) - -/* - * TXVLANGFIS (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Status - * This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXVLANGFIS_MASK (0x1000000UL) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT (24U) -#define ENET_MMC_INTR_TX_TXVLANGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) -#define ENET_MMC_INTR_TX_TXVLANGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXVLANGFIS_MASK) >> ENET_MMC_INTR_TX_TXVLANGFIS_SHIFT) - -/* - * TXPAUSFIS (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Status - * This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXPAUSFIS_MASK (0x800000UL) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT (23U) -#define ENET_MMC_INTR_TX_TXPAUSFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) -#define ENET_MMC_INTR_TX_TXPAUSFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXPAUSFIS_MASK) >> ENET_MMC_INTR_TX_TXPAUSFIS_SHIFT) - -/* - * TXEXDEFFIS (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Status - * This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXDEFFIS_MASK (0x400000UL) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT (22U) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXEXDEFFIS_SHIFT) - -/* - * TXGFRMIS (RW) - * - * MMC Transmit Good Frame Counter Interrupt Status - * This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGFRMIS_MASK (0x200000UL) -#define ENET_MMC_INTR_TX_TXGFRMIS_SHIFT (21U) -#define ENET_MMC_INTR_TX_TXGFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGFRMIS_SHIFT) - -/* - * TXGOCTIS (RW) - * - * MMC Transmit Good Octet Counter Interrupt Status - * This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGOCTIS_MASK (0x100000UL) -#define ENET_MMC_INTR_TX_TXGOCTIS_SHIFT (20U) -#define ENET_MMC_INTR_TX_TXGOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGOCTIS_SHIFT) - -/* - * TXCARERFIS (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Status - * This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXCARERFIS_MASK (0x80000UL) -#define ENET_MMC_INTR_TX_TXCARERFIS_SHIFT (19U) -#define ENET_MMC_INTR_TX_TXCARERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) -#define ENET_MMC_INTR_TX_TXCARERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXCARERFIS_MASK) >> ENET_MMC_INTR_TX_TXCARERFIS_SHIFT) - -/* - * TXEXCOLFIS (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Status - * This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXEXCOLFIS_MASK (0x40000UL) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT (18U) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXEXCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXEXCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXEXCOLFIS_SHIFT) - -/* - * TXLATCOLFIS (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Status - * This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXLATCOLFIS_MASK (0x20000UL) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT (17U) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) -#define ENET_MMC_INTR_TX_TXLATCOLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXLATCOLFIS_MASK) >> ENET_MMC_INTR_TX_TXLATCOLFIS_SHIFT) - -/* - * TXDEFFIS (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Status - * This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXDEFFIS_MASK (0x10000UL) -#define ENET_MMC_INTR_TX_TXDEFFIS_SHIFT (16U) -#define ENET_MMC_INTR_TX_TXDEFFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) -#define ENET_MMC_INTR_TX_TXDEFFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXDEFFIS_MASK) >> ENET_MMC_INTR_TX_TXDEFFIS_SHIFT) - -/* - * TXMCOLGFIS (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Status - * This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCOLGFIS_MASK (0x8000U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT (15U) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCOLGFIS_SHIFT) - -/* - * TXSCOLGFIS (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Status - * This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXSCOLGFIS_MASK (0x4000U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT (14U) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) -#define ENET_MMC_INTR_TX_TXSCOLGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXSCOLGFIS_MASK) >> ENET_MMC_INTR_TX_TXSCOLGFIS_SHIFT) - -/* - * TXUFLOWERFIS (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Status - * This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK (0x2000U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT (13U) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) -#define ENET_MMC_INTR_TX_TXUFLOWERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUFLOWERFIS_MASK) >> ENET_MMC_INTR_TX_TXUFLOWERFIS_SHIFT) - -/* - * TXBCGBFIS (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGBFIS_MASK (0x1000U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT (12U) -#define ENET_MMC_INTR_TX_TXBCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGBFIS_SHIFT) - -/* - * TXMCGBFIS (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Status - * The bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGBFIS_MASK (0x800U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT (11U) -#define ENET_MMC_INTR_TX_TXMCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGBFIS_SHIFT) - -/* - * TXUCGBFIS (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Status - * This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXUCGBFIS_MASK (0x400U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT (10U) -#define ENET_MMC_INTR_TX_TXUCGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) -#define ENET_MMC_INTR_TX_TXUCGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXUCGBFIS_MASK) >> ENET_MMC_INTR_TX_TXUCGBFIS_SHIFT) - -/* - * TX1024TMAXOCTGBFIS (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK (0x200U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT (9U) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX1024TMAXOCTGBFIS_SHIFT) - -/* - * TX512T1023OCTGBFIS (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK (0x100U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT (8U) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX512T1023OCTGBFIS_SHIFT) - -/* - * TX256T511OCTGBFIS (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK (0x80U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT (7U) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX256T511OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX256T511OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX256T511OCTGBFIS_SHIFT) - -/* - * TX128T255OCTGBFIS (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK (0x40U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT (6U) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX128T255OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX128T255OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX128T255OCTGBFIS_SHIFT) - -/* - * TX65T127OCTGBFIS (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it reaches the maximum value. - */ -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK (0x20U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT (5U) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX65T127OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX65T127OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX65T127OCTGBFIS_SHIFT) - -/* - * TX64OCTGBFIS (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status - * This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK (0x10U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT (4U) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) -#define ENET_MMC_INTR_TX_TX64OCTGBFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TX64OCTGBFIS_MASK) >> ENET_MMC_INTR_TX_TX64OCTGBFIS_SHIFT) - -/* - * TXMCGFIS (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Status - * This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXMCGFIS_MASK (0x8U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SHIFT (3U) -#define ENET_MMC_INTR_TX_TXMCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXMCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXMCGFIS_MASK) >> ENET_MMC_INTR_TX_TXMCGFIS_SHIFT) - -/* - * TXBCGFIS (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Status - * This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXBCGFIS_MASK (0x4U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SHIFT (2U) -#define ENET_MMC_INTR_TX_TXBCGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) -#define ENET_MMC_INTR_TX_TXBCGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXBCGFIS_MASK) >> ENET_MMC_INTR_TX_TXBCGFIS_SHIFT) - -/* - * TXGBFRMIS (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Status - * This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBFRMIS_MASK (0x2U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT (1U) -#define ENET_MMC_INTR_TX_TXGBFRMIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) -#define ENET_MMC_INTR_TX_TXGBFRMIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBFRMIS_MASK) >> ENET_MMC_INTR_TX_TXGBFRMIS_SHIFT) - -/* - * TXGBOCTIS (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Status - * This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_TX_TXGBOCTIS_MASK (0x1U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT (0U) -#define ENET_MMC_INTR_TX_TXGBOCTIS_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) -#define ENET_MMC_INTR_TX_TXGBOCTIS_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_TX_TXGBOCTIS_MASK) >> ENET_MMC_INTR_TX_TXGBOCTIS_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_RX */ -/* - * RXCTRLFIM (RW) - * - * MMC Receive Control Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxctrlframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCTRLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCTRLFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCTRLFIM_SHIFT) - -/* - * RXRCVERRFIM (RW) - * - * MMC Receive Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRCVERRFIM_SHIFT) - -/* - * RXWDOGFIM (RW) - * - * MMC Receive Watchdog Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXWDOGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXWDOGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXWDOGFIM_SHIFT) - -/* - * RXVLANGBFIM (RW) - * - * MMC Receive VLAN Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXVLANGBFIM_SHIFT) - -/* - * RXFOVFIM (RW) - * - * MMC Receive FIFO Overflow Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXFOVFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXFOVFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXFOVFIM_SHIFT) - -/* - * RXPAUSFIM (RW) - * - * MMC Receive Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXPAUSFIM_SHIFT) - -/* - * RXORANGEFIM (RW) - * - * MMC Receive Out Of Range Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXORANGEFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXORANGEFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXORANGEFIM_SHIFT) - -/* - * RXLENERFIM (RW) - * - * MMC Receive Length Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXLENERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXLENERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXLENERFIM_SHIFT) - -/* - * RXUCGFIM (RW) - * - * MMC Receive Unicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUCGFIM_SHIFT) - -/* - * RX1024TMAXOCTGBFIM (RW) - * - * MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX1024TMAXOCTGBFIM_SHIFT) - -/* - * RX512T1023OCTGBFIM (RW) - * - * MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX512T1023OCTGBFIM_SHIFT) - -/* - * RX256T511OCTGBFIM (RW) - * - * MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX256T511OCTGBFIM_SHIFT) - -/* - * RX128T255OCTGBFIM (RW) - * - * MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX128T255OCTGBFIM_SHIFT) - -/* - * RX65T127OCTGBFIM (RW) - * - * MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX65T127OCTGBFIM_SHIFT) - -/* - * RX64OCTGBFIM (RW) - * - * MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RX64OCTGBFIM_SHIFT) - -/* - * RXOSIZEGFIM (RW) - * - * MMC Receive Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXOSIZEGFIM_SHIFT) - -/* - * RXUSIZEGFIM (RW) - * - * MMC Receive Undersize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXUSIZEGFIM_SHIFT) - -/* - * RXJABERFIM (RW) - * - * MMC Receive Jabber Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXJABERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXJABERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXJABERFIM_SHIFT) - -/* - * RXRUNTFIM (RW) - * - * MMC Receive Runt Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXRUNTFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXRUNTFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXRUNTFIM_SHIFT) - -/* - * RXALGNERFIM (RW) - * - * MMC Receive Alignment Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXALGNERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXALGNERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXALGNERFIM_SHIFT) - -/* - * RXCRCERFIM (RW) - * - * MMC Receive CRC Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXCRCERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXCRCERFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXCRCERFIM_SHIFT) - -/* - * RXMCGFIM (RW) - * - * MMC Receive Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXMCGFIM_SHIFT) - -/* - * RXBCGFIM (RW) - * - * MMC Receive Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXBCGFIM_SHIFT) - -/* - * RXGOCTIM (RW) - * - * MMC Receive Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGOCTIM_SHIFT) - -/* - * RXGBOCTIM (RW) - * - * MMC Receive Good Bad Octet Counter Interrupt Mask. - * Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_RX_RXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_RX_RXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_RX_RXGBOCTIM_SHIFT) - -/* Bitfield definition for register: MMC_INTR_MASK_TX */ -/* - * TXOSIZEGFIM (RW) - * - * MMC Transmit Oversize Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK (0x2000000UL) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT (25U) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXOSIZEGFIM_SHIFT) - -/* - * TXVLANGFIM (RW) - * - * MMC Transmit VLAN Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK (0x1000000UL) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT (24U) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXVLANGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXVLANGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXVLANGFIM_SHIFT) - -/* - * TXPAUSFIM (RW) - * - * MMC Transmit Pause Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK (0x800000UL) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT (23U) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXPAUSFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXPAUSFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXPAUSFIM_SHIFT) - -/* - * TXEXDEFFIM (RW) - * - * MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK (0x400000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT (22U) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXDEFFIM_SHIFT) - -/* - * TXGFRMIM (RW) - * - * MMC Transmit Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK (0x200000UL) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT (21U) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGFRMIM_SHIFT) - -/* - * TXGOCTIM (RW) - * - * MMC Transmit Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK (0x100000UL) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT (20U) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGOCTIM_SHIFT) - -/* - * TXCARERFIM (RW) - * - * MMC Transmit Carrier Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK (0x80000UL) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT (19U) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXCARERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXCARERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXCARERFIM_SHIFT) - -/* - * TXEXCOLFIM (RW) - * - * MMC Transmit Excessive Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK (0x40000UL) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT (18U) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXEXCOLFIM_SHIFT) - -/* - * TXLATCOLFIM (RW) - * - * MMC Transmit Late Collision Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK (0x20000UL) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT (17U) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXLATCOLFIM_SHIFT) - -/* - * TXDEFFIM (RW) - * - * MMC Transmit Deferred Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK (0x10000UL) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT (16U) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXDEFFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXDEFFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXDEFFIM_SHIFT) - -/* - * TXMCOLGFIM (RW) - * - * MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK (0x8000U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT (15U) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCOLGFIM_SHIFT) - -/* - * TXSCOLGFIM (RW) - * - * MMC Transmit Single Collision Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK (0x4000U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT (14U) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXSCOLGFIM_SHIFT) - -/* - * TXUFLOWERFIM (RW) - * - * MMC Transmit Underflow Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK (0x2000U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT (13U) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUFLOWERFIM_SHIFT) - -/* - * TXBCGBFIM (RW) - * - * MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK (0x1000U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT (12U) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGBFIM_SHIFT) - -/* - * TXMCGBFIM (RW) - * - * MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK (0x800U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT (11U) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGBFIM_SHIFT) - -/* - * TXUCGBFIM (RW) - * - * MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK (0x400U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT (10U) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXUCGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXUCGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXUCGBFIM_SHIFT) - -/* - * TX1024TMAXOCTGBFIM (RW) - * - * MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK (0x200U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT (9U) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX1024TMAXOCTGBFIM_SHIFT) - -/* - * TX512T1023OCTGBFIM (RW) - * - * MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK (0x100U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT (8U) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX512T1023OCTGBFIM_SHIFT) - -/* - * TX256T511OCTGBFIM (RW) - * - * MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK (0x80U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT (7U) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX256T511OCTGBFIM_SHIFT) - -/* - * TX128T255OCTGBFIM (RW) - * - * MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK (0x40U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT (6U) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX128T255OCTGBFIM_SHIFT) - -/* - * TX65T127OCTGBFIM (RW) - * - * MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK (0x20U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT (5U) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX65T127OCTGBFIM_SHIFT) - -/* - * TX64OCTGBFIM (RW) - * - * MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK (0x10U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT (4U) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TX64OCTGBFIM_SHIFT) - -/* - * TXMCGFIM (RW) - * - * MMC Transmit Multicast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK (0x8U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT (3U) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXMCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXMCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXMCGFIM_SHIFT) - -/* - * TXBCGFIM (RW) - * - * MMC Transmit Broadcast Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK (0x4U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT (2U) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXBCGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXBCGFIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXBCGFIM_SHIFT) - -/* - * TXGBFRMIM (RW) - * - * MMC Transmit Good Bad Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK (0x2U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT (1U) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBFRMIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBFRMIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBFRMIM_SHIFT) - -/* - * TXGBOCTIM (RW) - * - * MMC Transmit Good Bad Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK (0x1U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT (0U) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SET(x) (((uint32_t)(x) << ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) -#define ENET_MMC_INTR_MASK_TX_TXGBOCTIM_GET(x) (((uint32_t)(x) & ENET_MMC_INTR_MASK_TX_TXGBOCTIM_MASK) >> ENET_MMC_INTR_MASK_TX_TXGBOCTIM_SHIFT) - -/* Bitfield definition for register: TX64OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length 64 bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX64OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX64OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX64OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX64OCTETS_GB_FRMCNT_SHIFT) & ENET_TX64OCTETS_GB_FRMCNT_MASK) -#define ENET_TX64OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX64OCTETS_GB_FRMCNT_MASK) >> ENET_TX64OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX65TO127OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX65TO127OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) -#define ENET_TX65TO127OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX65TO127OCTETS_GB_FRMCNT_MASK) >> ENET_TX65TO127OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX128TO255OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX128TO255OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) -#define ENET_TX128TO255OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX128TO255OCTETS_GB_FRMCNT_MASK) >> ENET_TX128TO255OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX256TO511OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX256TO511OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) -#define ENET_TX256TO511OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX256TO511OCTETS_GB_FRMCNT_MASK) >> ENET_TX256TO511OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX512TO1023OCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) -#define ENET_TX512TO1023OCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX512TO1023OCTETS_GB_FRMCNT_MASK) >> ENET_TX512TO1023OCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: TX1024TOMAXOCTETS_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames. - */ -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT (0U) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) -#define ENET_TX1024TOMAXOCTETS_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_TX1024TOMAXOCTETS_GB_FRMCNT_MASK) >> ENET_TX1024TOMAXOCTETS_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: RXFRAMECOUNT_GB */ -/* - * FRMCNT (RW) - * - * Number of good and bad frames received. - */ -#define ENET_RXFRAMECOUNT_GB_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT (0U) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) -#define ENET_RXFRAMECOUNT_GB_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXFRAMECOUNT_GB_FRMCNT_MASK) >> ENET_RXFRAMECOUNT_GB_FRMCNT_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_MASK_RX */ -/* - * RXICMPEROIM (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT (29U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPEROIM_SHIFT) - -/* - * RXICMPGOIM (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT (28U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGOIM_SHIFT) - -/* - * RXTCPEROIM (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT (27U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPEROIM_SHIFT) - -/* - * RXTCPGOIM (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT (26U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGOIM_SHIFT) - -/* - * RXUDPEROIM (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT (25U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPEROIM_SHIFT) - -/* - * RXUDPGOIM (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT (24U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGOIM_SHIFT) - -/* - * RXIPV6NOPAYOIM (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT (23U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYOIM_SHIFT) - -/* - * RXIPV6HEROIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT (22U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HEROIM_SHIFT) - -/* - * RXIPV6GOIM (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT (21U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GOIM_SHIFT) - -/* - * RXIPV4UDSBLOIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT (20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLOIM_SHIFT) - -/* - * RXIPV4FRAGOIM (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT (19U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGOIM_SHIFT) - -/* - * RXIPV4NOPAYOIM (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT (18U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYOIM_SHIFT) - -/* - * RXIPV4HEROIM (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT (17U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HEROIM_SHIFT) - -/* - * RXIPV4GOIM (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT (16U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GOIM_SHIFT) - -/* - * RXICMPERFIM (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT (13U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPERFIM_SHIFT) - -/* - * RXICMPGFIM (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT (12U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXICMPGFIM_SHIFT) - -/* - * RXTCPERFIM (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK (0x800U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT (11U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPERFIM_SHIFT) - -/* - * RXTCPGFIM (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK (0x400U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT (10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXTCPGFIM_SHIFT) - -/* - * RXUDPERFIM (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK (0x200U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT (9U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPERFIM_SHIFT) - -/* - * RXUDPGFIM (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK (0x100U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT (8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXUDPGFIM_SHIFT) - -/* - * RXIPV6NOPAYFIM (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK (0x80U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT (7U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6NOPAYFIM_SHIFT) - -/* - * RXIPV6HERFIM (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK (0x40U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT (6U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6HERFIM_SHIFT) - -/* - * RXIPV6GFIM (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK (0x20U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT (5U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV6GFIM_SHIFT) - -/* - * RXIPV4UDSBLFIM (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK (0x10U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT (4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4UDSBLFIM_SHIFT) - -/* - * RXIPV4FRAGFIM (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK (0x8U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT (3U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4FRAGFIM_SHIFT) - -/* - * RXIPV4NOPAYFIM (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK (0x4U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT (2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4NOPAYFIM_SHIFT) - -/* - * RXIPV4HERFIM (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK (0x2U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT (1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4HERFIM_SHIFT) - -/* - * RXIPV4GFIM (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Mask - * Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK (0x1U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT (0U) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) -#define ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_MASK) >> ENET_MMC_IPC_INTR_MASK_RX_RXIPV4GFIM_SHIFT) - -/* Bitfield definition for register: MMC_IPC_INTR_RX */ -/* - * RXICMPEROIS (RW) - * - * MMC Receive ICMP Error Octet Counter Interrupt Status - * This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK (0x20000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT (29U) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPEROIS_SHIFT) - -/* - * RXICMPGOIS (RW) - * - * MMC Receive ICMP Good Octet Counter Interrupt Status - * This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK (0x10000000UL) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT (28U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGOIS_SHIFT) - -/* - * RXTCPEROIS (RW) - * - * MMC Receive TCP Error Octet Counter Interrupt Status - * This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK (0x8000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT (27U) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPEROIS_SHIFT) - -/* - * RXTCPGOIS (RW) - * - * MMC Receive TCP Good Octet Counter Interrupt Status - * This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK (0x4000000UL) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT (26U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGOIS_SHIFT) - -/* - * RXUDPEROIS (RW) - * - * MMC Receive UDP Error Octet Counter Interrupt Status - * This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK (0x2000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT (25U) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPEROIS_SHIFT) - -/* - * RXUDPGOIS (RW) - * - * MMC Receive UDP Good Octet Counter Interrupt Status - * This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK (0x1000000UL) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT (24U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGOIS_SHIFT) - -/* - * RXIPV6NOPAYOIS (RW) - * - * MMC Receive IPV6 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK (0x800000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT (23U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYOIS_SHIFT) - -/* - * RXIPV6HEROIS (RW) - * - * MMC Receive IPV6 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK (0x400000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT (22U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HEROIS_SHIFT) - -/* - * RXIPV6GOIS (RW) - * - * MMC Receive IPV6 Good Octet Counter Interrupt Status - * This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK (0x200000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT (21U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GOIS_SHIFT) - -/* - * RXIPV4UDSBLOIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK (0x100000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT (20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLOIS_SHIFT) - -/* - * RXIPV4FRAGOIS (RW) - * - * MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - * This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK (0x80000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT (19U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGOIS_SHIFT) - -/* - * RXIPV4NOPAYOIS (RW) - * - * MMC Receive IPV4 No Payload Octet Counter Interrupt Status - * This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK (0x40000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT (18U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYOIS_SHIFT) - -/* - * RXIPV4HEROIS (RW) - * - * MMC Receive IPV4 Header Error Octet Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK (0x20000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT (17U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HEROIS_SHIFT) - -/* - * RXIPV4GOIS (RW) - * - * MMC Receive IPV4 Good Octet Counter Interrupt Status - * This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK (0x10000UL) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT (16U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GOIS_SHIFT) - -/* - * RXICMPERFIS (RW) - * - * MMC Receive ICMP Error Frame Counter Interrupt Status - * This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK (0x2000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT (13U) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPERFIS_SHIFT) - -/* - * RXICMPGFIS (RW) - * - * MMC Receive ICMP Good Frame Counter Interrupt Status - * This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK (0x1000U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT (12U) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXICMPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXICMPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXICMPGFIS_SHIFT) - -/* - * RXTCPERFIS (RW) - * - * MMC Receive TCP Error Frame Counter Interrupt Status - * This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK (0x800U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT (11U) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPERFIS_SHIFT) - -/* - * RXTCPGFIS (RW) - * - * MMC Receive TCP Good Frame Counter Interrupt Status - * This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK (0x400U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT (10U) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXTCPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXTCPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXTCPGFIS_SHIFT) - -/* - * RXUDPERFIS (RW) - * - * MMC Receive UDP Error Frame Counter Interrupt Status - * This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK (0x200U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT (9U) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPERFIS_SHIFT) - -/* - * RXUDPGFIS (RW) - * - * MMC Receive UDP Good Frame Counter Interrupt Status - * This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK (0x100U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT (8U) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXUDPGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXUDPGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXUDPGFIS_SHIFT) - -/* - * RXIPV6NOPAYFIS (RW) - * - * MMC Receive IPV6 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK (0x80U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT (7U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6NOPAYFIS_SHIFT) - -/* - * RXIPV6HERFIS (RW) - * - * MMC Receive IPV6 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK (0x40U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT (6U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6HERFIS_SHIFT) - -/* - * RXIPV6GFIS (RW) - * - * MMC Receive IPV6 Good Frame Counter Interrupt Status - * This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK (0x20U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT (5U) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV6GFIS_SHIFT) - -/* - * RXIPV4UDSBLFIS (RW) - * - * MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - * This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK (0x10U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT (4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4UDSBLFIS_SHIFT) - -/* - * RXIPV4FRAGFIS (RW) - * - * MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - * This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK (0x8U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT (3U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4FRAGFIS_SHIFT) - -/* - * RXIPV4NOPAYFIS (RW) - * - * MMC Receive IPV4 No Payload Frame Counter Interrupt Status - * This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK (0x4U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT (2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4NOPAYFIS_SHIFT) - -/* - * RXIPV4HERFIS (RW) - * - * MMC Receive IPV4 Header Error Frame Counter Interrupt Status - * This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK (0x2U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT (1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4HERFIS_SHIFT) - -/* - * RXIPV4GFIS (RW) - * - * MMC Receive IPV4 Good Frame Counter Interrupt Status - * This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value. - */ -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK (0x1U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT (0U) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SET(x) (((uint32_t)(x) << ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) -#define ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_GET(x) (((uint32_t)(x) & ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_MASK) >> ENET_MMC_IPC_INTR_RX_RXIPV4GFIS_SHIFT) - -/* Bitfield definition for register: RXIPV4_GD_FMS */ -/* - * FRMCNT (RW) - * - * Number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload - */ -#define ENET_RXIPV4_GD_FMS_FRMCNT_MASK (0xFFFFFFFFUL) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT (0U) -#define ENET_RXIPV4_GD_FMS_FRMCNT_SET(x) (((uint32_t)(x) << ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) -#define ENET_RXIPV4_GD_FMS_FRMCNT_GET(x) (((uint32_t)(x) & ENET_RXIPV4_GD_FMS_FRMCNT_MASK) >> ENET_RXIPV4_GD_FMS_FRMCNT_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_L4_CTRL */ -/* - * L4DPIM0 (RW) - * - * Layer 4 Destination Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK (0x200000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT (21U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPIM0_SHIFT) - -/* - * L4DPM0 (RW) - * - * Layer 4 Destination Port Match Enable - * When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. - * When reset, the MAC ignores the Layer 4 Destination Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK (0x100000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT (20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4DPM0_SHIFT) - -/* - * L4SPIM0 (RW) - * - * Layer 4 Source Port Inverse Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK (0x80000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT (19U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPIM0_SHIFT) - -/* - * L4SPM0 (RW) - * - * Layer 4 Source Port Match Enable - * When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK (0x40000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT (18U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4SPM0_SHIFT) - -/* - * L4PEN0 (RW) - * - * Layer 4 Protocol Enable - * When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. - * When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. - * The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK (0x10000UL) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT (16U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L4PEN0_SHIFT) - -/* - * L3HDBM0 (RW) - * - * Layer 3 IP DA Higher Bits Match - * IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, - * which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. - * The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - … - * - 127: All bits except MSb are masked. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK (0xF800U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT (11U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HDBM0_SHIFT) - -/* - * L3HSBM0 (RW) - * - * Layer 3 IP SA Higher Bits Match - * IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field: - * - 0: No bits are masked. - * - 1: LSb[0] is masked. - * - 2: Two LSbs [1:0] are masked. - ... - * - 31: All bits except MSb are masked. IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. - * This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK (0x7C0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT (6U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3HSBM0_SHIFT) - -/* - * L3DAIM0 (RW) - * - * Layer 3 IP DA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. - * When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK (0x20U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT (5U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAIM0_SHIFT) - -/* - * L3DAM0 (RW) - * - * Layer 3 IP DA Match Enable - * When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. - * Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK (0x10U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT (4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3DAM0_SHIFT) - -/* - * L3SAIM0 (RW) - * - * Layer 3 IP SA Inverse Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. - * This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK (0x8U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT (3U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAIM0_SHIFT) - -/* - * L3SAM0 (RW) - * - * Layer 3 IP SA Match Enable - * When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK (0x4U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT (2U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3SAM0_SHIFT) - -/* - * L3PEN0 (RW) - * - * Layer 3 Protocol Enable - * When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. - * When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. - * The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. - */ -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK (0x1U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) -#define ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_MASK) >> ENET_L3_L4_CFG_L3_L4_CTRL_L3PEN0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L4_ADDR */ -/* - * L4DP0 (RW) - * - * Layer 4 Destination Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK (0xFFFF0000UL) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT (16U) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4DP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4DP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4DP0_SHIFT) - -/* - * L4SP0 (RW) - * - * Layer 4 Source Port Number Field - * When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames. - * When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames. - */ -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK (0xFFFFU) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT (0U) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) -#define ENET_L3_L4_CFG_L4_ADDR_L4SP0_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L4_ADDR_L4SP0_MASK) >> ENET_L3_L4_CFG_L4_ADDR_L4SP0_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_0 */ -/* - * L3A00 (RW) - * - * Layer 3 Address 0 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Source Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_0_L3A00_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_0_L3A00_MASK) >> ENET_L3_L4_CFG_L3_ADDR_0_L3A00_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_1 */ -/* - * L3A10 (RW) - * - * Layer 3 Address 1 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [63:32] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset and Bit 4 (L3DAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with the IP Destination Address field in the IPv4 frames. - */ -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_1_L3A10_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_1_L3A10_MASK) >> ENET_L3_L4_CFG_L3_ADDR_1_L3A10_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_2 */ -/* - * L3A20 (RW) - * - * Layer 3 Address 2 Field - * When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [95:64] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains value to be matched with Bits [95:64] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_2_L3A20_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_2_L3A20_MASK) >> ENET_L3_L4_CFG_L3_ADDR_2_L3A20_SHIFT) - -/* Bitfield definition for register of struct array L3_L4_CFG: L3_ADDR_3 */ -/* - * L3A30 (RW) - * - * Layer 3 Address 3 Field When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Source Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), - * this field contains the value to be matched with Bits [127:96] of the IP Destination Address field in the IPv6 frames. - * When Bit 0 (L3PEN0) is reset in Register 256 (Layer 3 and Layer 4 Control Register 0), this register is not used. - */ -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK (0xFFFFFFFFUL) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT (0U) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SET(x) (((uint32_t)(x) << ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) -#define ENET_L3_L4_CFG_L3_ADDR_3_L3A30_GET(x) (((uint32_t)(x) & ENET_L3_L4_CFG_L3_ADDR_3_L3A30_MASK) >> ENET_L3_L4_CFG_L3_ADDR_3_L3A30_SHIFT) - -/* Bitfield definition for register: VLAN_TAG_INC_RPL */ -/* - * CSVL (RW) - * - * C-VLAN or S-VLAN - * When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted frames. When this bit is reset, C-VLAN type (0x8100) is inserted or replaced in the transmitted frames. - */ -#define ENET_VLAN_TAG_INC_RPL_CSVL_MASK (0x80000UL) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT (19U) -#define ENET_VLAN_TAG_INC_RPL_CSVL_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) -#define ENET_VLAN_TAG_INC_RPL_CSVL_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_CSVL_MASK) >> ENET_VLAN_TAG_INC_RPL_CSVL_SHIFT) - -/* - * VLP (RW) - * - * VLAN Priority Control - * When this bit is set, the control Bits [17:16] are used for VLAN deletion, insertion, or replacement. When this bit is reset, the mti_vlan_ctrl_i control input is used, and Bits [17:16] are ignored. - */ -#define ENET_VLAN_TAG_INC_RPL_VLP_MASK (0x40000UL) -#define ENET_VLAN_TAG_INC_RPL_VLP_SHIFT (18U) -#define ENET_VLAN_TAG_INC_RPL_VLP_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLP_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLP_MASK) >> ENET_VLAN_TAG_INC_RPL_VLP_SHIFT) - -/* - * VLC (RW) - * - * VLAN Tag Control in Transmit Frames - * - 2’b00: No VLAN tag deletion, insertion, or replacement - * - 2’b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted frames with VLAN tags. - * - 2’b10: VLAN tag insertion The MAC inserts VLT in bytes 15 and 16 of the frame after inserting the Type value (0x8100/0x88a8) in bytes 13 and 14. - * This operation is performed on all transmitted frames, irrespective of whether they already have a VLAN tag. - * - 2’b11: VLAN tag replacement The MAC replaces VLT in bytes 15 and 16 of all VLAN-type transmitted frames (Bytes 13 and 14 are 0x8100/0x88a8). - * Note: Changes to this field take effect only on the start of a frame. - * If you write this register field when a frame is being transmitted, only the subsequent frame can use the updated value, that is, the current frame does not use the updated value. - */ -#define ENET_VLAN_TAG_INC_RPL_VLC_MASK (0x30000UL) -#define ENET_VLAN_TAG_INC_RPL_VLC_SHIFT (16U) -#define ENET_VLAN_TAG_INC_RPL_VLC_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLC_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLC_MASK) >> ENET_VLAN_TAG_INC_RPL_VLC_SHIFT) - -/* - * VLT (RW) - * - * VLAN Tag for Transmit Frames - * This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. - * Bits[15:13] are the User Priority, Bit 12 is the CFI/DEI, and Bits[11:0] are the VLAN tag’s VID field. - */ -#define ENET_VLAN_TAG_INC_RPL_VLT_MASK (0xFFFFU) -#define ENET_VLAN_TAG_INC_RPL_VLT_SHIFT (0U) -#define ENET_VLAN_TAG_INC_RPL_VLT_SET(x) (((uint32_t)(x) << ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) -#define ENET_VLAN_TAG_INC_RPL_VLT_GET(x) (((uint32_t)(x) & ENET_VLAN_TAG_INC_RPL_VLT_MASK) >> ENET_VLAN_TAG_INC_RPL_VLT_SHIFT) - -/* Bitfield definition for register: VLAN_HASH */ -/* - * VLHT (RW) - * - * VLAN Hash Table - * This field contains the 16-bit VLAN Hash Table. - */ -#define ENET_VLAN_HASH_VLHT_MASK (0xFFFFU) -#define ENET_VLAN_HASH_VLHT_SHIFT (0U) -#define ENET_VLAN_HASH_VLHT_SET(x) (((uint32_t)(x) << ENET_VLAN_HASH_VLHT_SHIFT) & ENET_VLAN_HASH_VLHT_MASK) -#define ENET_VLAN_HASH_VLHT_GET(x) (((uint32_t)(x) & ENET_VLAN_HASH_VLHT_MASK) >> ENET_VLAN_HASH_VLHT_SHIFT) - -/* Bitfield definition for register: TS_CTRL */ -/* - * ATSEN3 (RW) - * - * Auxiliary Snapshot 3 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. - */ -#define ENET_TS_CTRL_ATSEN3_MASK (0x10000000UL) -#define ENET_TS_CTRL_ATSEN3_SHIFT (28U) -#define ENET_TS_CTRL_ATSEN3_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN3_SHIFT) & ENET_TS_CTRL_ATSEN3_MASK) -#define ENET_TS_CTRL_ATSEN3_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN3_MASK) >> ENET_TS_CTRL_ATSEN3_SHIFT) - -/* - * ATSEN2 (RW) - * - * Auxiliary Snapshot 2 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. - */ -#define ENET_TS_CTRL_ATSEN2_MASK (0x8000000UL) -#define ENET_TS_CTRL_ATSEN2_SHIFT (27U) -#define ENET_TS_CTRL_ATSEN2_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN2_SHIFT) & ENET_TS_CTRL_ATSEN2_MASK) -#define ENET_TS_CTRL_ATSEN2_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN2_MASK) >> ENET_TS_CTRL_ATSEN2_SHIFT) - -/* - * ATSEN1 (RW) - * - * Auxiliary Snapshot 1 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. - */ -#define ENET_TS_CTRL_ATSEN1_MASK (0x4000000UL) -#define ENET_TS_CTRL_ATSEN1_SHIFT (26U) -#define ENET_TS_CTRL_ATSEN1_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN1_SHIFT) & ENET_TS_CTRL_ATSEN1_MASK) -#define ENET_TS_CTRL_ATSEN1_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN1_MASK) >> ENET_TS_CTRL_ATSEN1_SHIFT) - -/* - * ATSEN0 (RW) - * - * Auxiliary Snapshot 0 Enable - * This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. - */ -#define ENET_TS_CTRL_ATSEN0_MASK (0x2000000UL) -#define ENET_TS_CTRL_ATSEN0_SHIFT (25U) -#define ENET_TS_CTRL_ATSEN0_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSEN0_SHIFT) & ENET_TS_CTRL_ATSEN0_MASK) -#define ENET_TS_CTRL_ATSEN0_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSEN0_MASK) >> ENET_TS_CTRL_ATSEN0_SHIFT) - -/* - * ATSFC (RW) - * - * Auxiliary Snapshot FIFO Clear - * When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. - * This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. - */ -#define ENET_TS_CTRL_ATSFC_MASK (0x1000000UL) -#define ENET_TS_CTRL_ATSFC_SHIFT (24U) -#define ENET_TS_CTRL_ATSFC_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_ATSFC_SHIFT) & ENET_TS_CTRL_ATSFC_MASK) -#define ENET_TS_CTRL_ATSFC_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_ATSFC_MASK) >> ENET_TS_CTRL_ATSFC_SHIFT) - -/* - * TSENMACADDR (RW) - * - * Enable MAC address for PTP Frame Filtering - * When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. - */ -#define ENET_TS_CTRL_TSENMACADDR_MASK (0x40000UL) -#define ENET_TS_CTRL_TSENMACADDR_SHIFT (18U) -#define ENET_TS_CTRL_TSENMACADDR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENMACADDR_SHIFT) & ENET_TS_CTRL_TSENMACADDR_MASK) -#define ENET_TS_CTRL_TSENMACADDR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENMACADDR_MASK) >> ENET_TS_CTRL_TSENMACADDR_SHIFT) - -/* - * SNAPTYPSEL (RW) - * - * Select PTP packets for Taking Snapshots - * These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. - */ -#define ENET_TS_CTRL_SNAPTYPSEL_MASK (0x30000UL) -#define ENET_TS_CTRL_SNAPTYPSEL_SHIFT (16U) -#define ENET_TS_CTRL_SNAPTYPSEL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_SNAPTYPSEL_SHIFT) & ENET_TS_CTRL_SNAPTYPSEL_MASK) -#define ENET_TS_CTRL_SNAPTYPSEL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_SNAPTYPSEL_MASK) >> ENET_TS_CTRL_SNAPTYPSEL_SHIFT) - -/* - * TSMSTRENA (RW) - * - * Enable Snapshot for Messages Relevant to Master - * When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. - */ -#define ENET_TS_CTRL_TSMSTRENA_MASK (0x8000U) -#define ENET_TS_CTRL_TSMSTRENA_SHIFT (15U) -#define ENET_TS_CTRL_TSMSTRENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSMSTRENA_SHIFT) & ENET_TS_CTRL_TSMSTRENA_MASK) -#define ENET_TS_CTRL_TSMSTRENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSMSTRENA_MASK) >> ENET_TS_CTRL_TSMSTRENA_SHIFT) - -/* - * TSEVNTENA (RW) - * - * Enable Timestamp Snapshot for Event Messages - * When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. - */ -#define ENET_TS_CTRL_TSEVNTENA_MASK (0x4000U) -#define ENET_TS_CTRL_TSEVNTENA_SHIFT (14U) -#define ENET_TS_CTRL_TSEVNTENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSEVNTENA_SHIFT) & ENET_TS_CTRL_TSEVNTENA_MASK) -#define ENET_TS_CTRL_TSEVNTENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSEVNTENA_MASK) >> ENET_TS_CTRL_TSEVNTENA_SHIFT) - -/* - * TSIPV4ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv4-UDP - * When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. - */ -#define ENET_TS_CTRL_TSIPV4ENA_MASK (0x2000U) -#define ENET_TS_CTRL_TSIPV4ENA_SHIFT (13U) -#define ENET_TS_CTRL_TSIPV4ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV4ENA_SHIFT) & ENET_TS_CTRL_TSIPV4ENA_MASK) -#define ENET_TS_CTRL_TSIPV4ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV4ENA_MASK) >> ENET_TS_CTRL_TSIPV4ENA_SHIFT) - -/* - * TSIPV6ENA (RW) - * - * Enable Processing of PTP Frames Sent over IPv6-UDP - * When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv6 packets. - */ -#define ENET_TS_CTRL_TSIPV6ENA_MASK (0x1000U) -#define ENET_TS_CTRL_TSIPV6ENA_SHIFT (12U) -#define ENET_TS_CTRL_TSIPV6ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPV6ENA_SHIFT) & ENET_TS_CTRL_TSIPV6ENA_MASK) -#define ENET_TS_CTRL_TSIPV6ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPV6ENA_MASK) >> ENET_TS_CTRL_TSIPV6ENA_SHIFT) - -/* - * TSIPENA (RW) - * - * Enable Processing of PTP over Ethernet Frames - * When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets - */ -#define ENET_TS_CTRL_TSIPENA_MASK (0x800U) -#define ENET_TS_CTRL_TSIPENA_SHIFT (11U) -#define ENET_TS_CTRL_TSIPENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSIPENA_SHIFT) & ENET_TS_CTRL_TSIPENA_MASK) -#define ENET_TS_CTRL_TSIPENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSIPENA_MASK) >> ENET_TS_CTRL_TSIPENA_SHIFT) - -/* - * TSVER2ENA (RW) - * - * Enable PTP packet Processing for Version 2 Format - * When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. - */ -#define ENET_TS_CTRL_TSVER2ENA_MASK (0x400U) -#define ENET_TS_CTRL_TSVER2ENA_SHIFT (10U) -#define ENET_TS_CTRL_TSVER2ENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSVER2ENA_SHIFT) & ENET_TS_CTRL_TSVER2ENA_MASK) -#define ENET_TS_CTRL_TSVER2ENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSVER2ENA_MASK) >> ENET_TS_CTRL_TSVER2ENA_SHIFT) - -/* - * TSCTRLSSR (RW) - * - * Timestamp Digital or Binary Rollover Control - * When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. - * When reset, the rollover value of sub-second register is 0x7FFF_FFFF. - * The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. - */ -#define ENET_TS_CTRL_TSCTRLSSR_MASK (0x200U) -#define ENET_TS_CTRL_TSCTRLSSR_SHIFT (9U) -#define ENET_TS_CTRL_TSCTRLSSR_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCTRLSSR_SHIFT) & ENET_TS_CTRL_TSCTRLSSR_MASK) -#define ENET_TS_CTRL_TSCTRLSSR_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCTRLSSR_MASK) >> ENET_TS_CTRL_TSCTRLSSR_SHIFT) - -/* - * TSENALL (RW) - * - * Enable Timestamp for All Frames - * When set, the timestamp snapshot is enabled for all frames received by the MAC. - */ -#define ENET_TS_CTRL_TSENALL_MASK (0x100U) -#define ENET_TS_CTRL_TSENALL_SHIFT (8U) -#define ENET_TS_CTRL_TSENALL_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENALL_SHIFT) & ENET_TS_CTRL_TSENALL_MASK) -#define ENET_TS_CTRL_TSENALL_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENALL_MASK) >> ENET_TS_CTRL_TSENALL_SHIFT) - -/* - * TSADDREG (RW) - * - * Addend Reg Update - * When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. - * This register bit should be zero before setting it. - */ -#define ENET_TS_CTRL_TSADDREG_MASK (0x20U) -#define ENET_TS_CTRL_TSADDREG_SHIFT (5U) -#define ENET_TS_CTRL_TSADDREG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSADDREG_SHIFT) & ENET_TS_CTRL_TSADDREG_MASK) -#define ENET_TS_CTRL_TSADDREG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSADDREG_MASK) >> ENET_TS_CTRL_TSADDREG_SHIFT) - -/* - * TSTRIG (RW) - * - * Timestamp Interrupt Trigger Enable - * When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. - * This bit is reset after the generation of the Timestamp Trigger Interrupt. - */ -#define ENET_TS_CTRL_TSTRIG_MASK (0x10U) -#define ENET_TS_CTRL_TSTRIG_SHIFT (4U) -#define ENET_TS_CTRL_TSTRIG_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSTRIG_SHIFT) & ENET_TS_CTRL_TSTRIG_MASK) -#define ENET_TS_CTRL_TSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSTRIG_MASK) >> ENET_TS_CTRL_TSTRIG_SHIFT) - -/* - * TSUPDT (RW) - * - * Timestamp Update - * When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the update is completed in hardware. The “Timestamp Higher Word” register (if enabled during core configuration) is not updated. - */ -#define ENET_TS_CTRL_TSUPDT_MASK (0x8U) -#define ENET_TS_CTRL_TSUPDT_SHIFT (3U) -#define ENET_TS_CTRL_TSUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSUPDT_SHIFT) & ENET_TS_CTRL_TSUPDT_MASK) -#define ENET_TS_CTRL_TSUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSUPDT_MASK) >> ENET_TS_CTRL_TSUPDT_SHIFT) - -/* - * TSINIT (RW) - * - * Timestamp Initialize - * When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time – Seconds Update Register) - * and Register 453 (System Time – Nanoseconds Update Register). This bit should be read zero before updating it. - * This bit is reset when the initialization is complete. - * The “Timestamp Higher Word” register (if enabled during core configuration) can only be initialized. - */ -#define ENET_TS_CTRL_TSINIT_MASK (0x4U) -#define ENET_TS_CTRL_TSINIT_SHIFT (2U) -#define ENET_TS_CTRL_TSINIT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSINIT_SHIFT) & ENET_TS_CTRL_TSINIT_MASK) -#define ENET_TS_CTRL_TSINIT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSINIT_MASK) >> ENET_TS_CTRL_TSINIT_SHIFT) - -/* - * TSCFUPDT (RW) - * - * Timestamp Fine or Coarse Update - * When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. - */ -#define ENET_TS_CTRL_TSCFUPDT_MASK (0x2U) -#define ENET_TS_CTRL_TSCFUPDT_SHIFT (1U) -#define ENET_TS_CTRL_TSCFUPDT_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSCFUPDT_SHIFT) & ENET_TS_CTRL_TSCFUPDT_MASK) -#define ENET_TS_CTRL_TSCFUPDT_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSCFUPDT_MASK) >> ENET_TS_CTRL_TSCFUPDT_SHIFT) - -/* - * TSENA (RW) - * - * Timestamp Enable - * When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. - * You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. - */ -#define ENET_TS_CTRL_TSENA_MASK (0x1U) -#define ENET_TS_CTRL_TSENA_SHIFT (0U) -#define ENET_TS_CTRL_TSENA_SET(x) (((uint32_t)(x) << ENET_TS_CTRL_TSENA_SHIFT) & ENET_TS_CTRL_TSENA_MASK) -#define ENET_TS_CTRL_TSENA_GET(x) (((uint32_t)(x) & ENET_TS_CTRL_TSENA_MASK) >> ENET_TS_CTRL_TSENA_SHIFT) - -/* Bitfield definition for register: SUB_SEC_INCR */ -/* - * SSINC (RW) - * - * Sub-second Increment Value - * The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. - * For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) - * when the System Time- Nanoseconds register has an accuracy of 1 ns [Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register)]. - * When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. - * In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465. - */ -#define ENET_SUB_SEC_INCR_SSINC_MASK (0xFFU) -#define ENET_SUB_SEC_INCR_SSINC_SHIFT (0U) -#define ENET_SUB_SEC_INCR_SSINC_SET(x) (((uint32_t)(x) << ENET_SUB_SEC_INCR_SSINC_SHIFT) & ENET_SUB_SEC_INCR_SSINC_MASK) -#define ENET_SUB_SEC_INCR_SSINC_GET(x) (((uint32_t)(x) & ENET_SUB_SEC_INCR_SSINC_MASK) >> ENET_SUB_SEC_INCR_SSINC_SHIFT) - -/* Bitfield definition for register: SYST_SEC */ -/* - * TSS (RO) - * - * Timestamp Second - * The value in this field indicates the current value in seconds of the System Time maintained by the MAC. - */ -#define ENET_SYST_SEC_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_TSS_SHIFT (0U) -#define ENET_SYST_SEC_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_TSS_MASK) >> ENET_SYST_SEC_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC */ -/* - * TSSS (RO) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the maximum value is 0x3B9A_C9FF, after which it rolls-over to zero. - */ -#define ENET_SYST_NSEC_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_TSSS_MASK) >> ENET_SYST_NSEC_TSSS_SHIFT) - -/* Bitfield definition for register: SYST_SEC_UPD */ -/* - * TSS (RW) - * - * Timestamp Second - * The value in this field indicates the time in seconds to be initialized or added to the system time. - */ -#define ENET_SYST_SEC_UPD_TSS_MASK (0xFFFFFFFFUL) -#define ENET_SYST_SEC_UPD_TSS_SHIFT (0U) -#define ENET_SYST_SEC_UPD_TSS_SET(x) (((uint32_t)(x) << ENET_SYST_SEC_UPD_TSS_SHIFT) & ENET_SYST_SEC_UPD_TSS_MASK) -#define ENET_SYST_SEC_UPD_TSS_GET(x) (((uint32_t)(x) & ENET_SYST_SEC_UPD_TSS_MASK) >> ENET_SYST_SEC_UPD_TSS_SHIFT) - -/* Bitfield definition for register: SYST_NSEC_UPD */ -/* - * ADDSUB (RW) - * - * Add or Subtract Time - * When this bit is set, the time value is subtracted with the contents of the update register. When this bit is reset, the time value is added with the contents of the update register. - */ -#define ENET_SYST_NSEC_UPD_ADDSUB_MASK (0x80000000UL) -#define ENET_SYST_NSEC_UPD_ADDSUB_SHIFT (31U) -#define ENET_SYST_NSEC_UPD_ADDSUB_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) -#define ENET_SYST_NSEC_UPD_ADDSUB_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_ADDSUB_MASK) >> ENET_SYST_NSEC_UPD_ADDSUB_SHIFT) - -/* - * TSSS (RW) - * - * Timestamp Sub Seconds - * The value in this field has the sub second representation of time, with an accuracy of 0.46 ns. - * When Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register), each bit represents 1 ns and the programmed value should not exceed 0x3B9A_C9FF. - */ -#define ENET_SYST_NSEC_UPD_TSSS_MASK (0x7FFFFFFFUL) -#define ENET_SYST_NSEC_UPD_TSSS_SHIFT (0U) -#define ENET_SYST_NSEC_UPD_TSSS_SET(x) (((uint32_t)(x) << ENET_SYST_NSEC_UPD_TSSS_SHIFT) & ENET_SYST_NSEC_UPD_TSSS_MASK) -#define ENET_SYST_NSEC_UPD_TSSS_GET(x) (((uint32_t)(x) & ENET_SYST_NSEC_UPD_TSSS_MASK) >> ENET_SYST_NSEC_UPD_TSSS_SHIFT) - -/* Bitfield definition for register: TS_ADDEND */ -/* - * TSAR (RW) - * - * Timestamp Addend Register - * This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization. - */ -#define ENET_TS_ADDEND_TSAR_MASK (0xFFFFFFFFUL) -#define ENET_TS_ADDEND_TSAR_SHIFT (0U) -#define ENET_TS_ADDEND_TSAR_SET(x) (((uint32_t)(x) << ENET_TS_ADDEND_TSAR_SHIFT) & ENET_TS_ADDEND_TSAR_MASK) -#define ENET_TS_ADDEND_TSAR_GET(x) (((uint32_t)(x) & ENET_TS_ADDEND_TSAR_MASK) >> ENET_TS_ADDEND_TSAR_SHIFT) - -/* Bitfield definition for register: TGTTM_SEC */ -/* - * TSTR (RW) - * - * Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [6:5] of Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_TGTTM_SEC_TSTR_MASK (0xFFFFFFFFUL) -#define ENET_TGTTM_SEC_TSTR_SHIFT (0U) -#define ENET_TGTTM_SEC_TSTR_SET(x) (((uint32_t)(x) << ENET_TGTTM_SEC_TSTR_SHIFT) & ENET_TGTTM_SEC_TSTR_MASK) -#define ENET_TGTTM_SEC_TSTR_GET(x) (((uint32_t)(x) & ENET_TGTTM_SEC_TSTR_MASK) >> ENET_TGTTM_SEC_TSTR_SHIFT) - -/* Bitfield definition for register: TGTTM_NSEC */ -/* - * TRGTBUSY (RW) - * - * Target Time Register Busy - * The MAC sets this bit when the PPSCMD field (Bit [3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Target Time Registers when this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected. - */ -#define ENET_TGTTM_NSEC_TRGTBUSY_MASK (0x80000000UL) -#define ENET_TGTTM_NSEC_TRGTBUSY_SHIFT (31U) -#define ENET_TGTTM_NSEC_TRGTBUSY_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) -#define ENET_TGTTM_NSEC_TRGTBUSY_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TRGTBUSY_MASK) >> ENET_TGTTM_NSEC_TRGTBUSY_SHIFT) - -/* - * TTSLO (RW) - * - * Target Timestamp Low Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_TGTTM_NSEC_TTSLO_MASK (0x7FFFFFFFUL) -#define ENET_TGTTM_NSEC_TTSLO_SHIFT (0U) -#define ENET_TGTTM_NSEC_TTSLO_SET(x) (((uint32_t)(x) << ENET_TGTTM_NSEC_TTSLO_SHIFT) & ENET_TGTTM_NSEC_TTSLO_MASK) -#define ENET_TGTTM_NSEC_TTSLO_GET(x) (((uint32_t)(x) & ENET_TGTTM_NSEC_TTSLO_MASK) >> ENET_TGTTM_NSEC_TTSLO_SHIFT) - -/* Bitfield definition for register: SYSTM_H_SEC */ -/* - * TSHWR (RW) - * - * Timestamp Higher Word Register - * This field contains the most significant 16-bits of the timestamp seconds value. This register is optional and can be selected using the Enable IEEE 1588 Higher Word Register option during core configuration. - * The register is directly written to initialize the value. This register is incremented when there is an overflow from the 32-bits of the System Time - Seconds register. - */ -#define ENET_SYSTM_H_SEC_TSHWR_MASK (0xFFFFU) -#define ENET_SYSTM_H_SEC_TSHWR_SHIFT (0U) -#define ENET_SYSTM_H_SEC_TSHWR_SET(x) (((uint32_t)(x) << ENET_SYSTM_H_SEC_TSHWR_SHIFT) & ENET_SYSTM_H_SEC_TSHWR_MASK) -#define ENET_SYSTM_H_SEC_TSHWR_GET(x) (((uint32_t)(x) & ENET_SYSTM_H_SEC_TSHWR_MASK) >> ENET_SYSTM_H_SEC_TSHWR_SHIFT) - -/* Bitfield definition for register: TS_STATUS */ -/* - * ATSNS (RO) - * - * Number of Auxiliary Timestamp Snapshots - * This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4, 8, or 16) indicates that the Auxiliary Snapshot FIFO is full. - * These bits are cleared (to 00000) when the Auxiliary snapshot FIFO clear bit is set. - * This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSNS_MASK (0x3E000000UL) -#define ENET_TS_STATUS_ATSNS_SHIFT (25U) -#define ENET_TS_STATUS_ATSNS_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSNS_MASK) >> ENET_TS_STATUS_ATSNS_SHIFT) - -/* - * ATSSTM (RO) - * - * Auxiliary Timestamp Snapshot Trigger Missed - * This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. - * This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected during core configuration. - */ -#define ENET_TS_STATUS_ATSSTM_MASK (0x1000000UL) -#define ENET_TS_STATUS_ATSSTM_SHIFT (24U) -#define ENET_TS_STATUS_ATSSTM_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTM_MASK) >> ENET_TS_STATUS_ATSSTM_SHIFT) - -/* - * ATSSTN (RO) - * - * Auxiliary Timestamp Snapshot Trigger Identifier - * These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. - * When more than one bit is set at the same time, it means that corresponding auxiliary triggers were sampled at the same clock. - * These bits are applicable only if the number of Auxiliary snapshots is more than one. - * One bit is assigned for each trigger as shown in the following list: - * - Bit 16: Auxiliary trigger 0 - * - Bit 17: Auxiliary trigger 1 - * - Bit 18: Auxiliary trigger 2 - * - Bit 19: Auxiliary trigger 3 - * The software can read this register to find the triggers that are set when the timestamp is taken. - */ -#define ENET_TS_STATUS_ATSSTN_MASK (0xF0000UL) -#define ENET_TS_STATUS_ATSSTN_SHIFT (16U) -#define ENET_TS_STATUS_ATSSTN_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_ATSSTN_MASK) >> ENET_TS_STATUS_ATSSTN_SHIFT) - -/* - * TSTRGTERR3 (RO) - * - * Timestamp Target Time Error - * This bit is set when the target time, being programmed in Register 496 and Register 497, is already elapsed. This bit is cleared when read by the application. - */ -#define ENET_TS_STATUS_TSTRGTERR3_MASK (0x200U) -#define ENET_TS_STATUS_TSTRGTERR3_SHIFT (9U) -#define ENET_TS_STATUS_TSTRGTERR3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR3_MASK) >> ENET_TS_STATUS_TSTRGTERR3_SHIFT) - -/* - * TSTARGT3 (RO) - * - * Timestamp Target Time Reached for Target Time PPS3 - * When set, this bit indicates that the value of system time is greater than or equal to the value specified in Register 496 (PPS3 Target Time High Register) and Register 497 (PPS3 Target Time Low Register). - */ -#define ENET_TS_STATUS_TSTARGT3_MASK (0x100U) -#define ENET_TS_STATUS_TSTARGT3_SHIFT (8U) -#define ENET_TS_STATUS_TSTARGT3_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT3_MASK) >> ENET_TS_STATUS_TSTARGT3_SHIFT) - -/* - * TSTRGTERR2 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR2_MASK (0x80U) -#define ENET_TS_STATUS_TSTRGTERR2_SHIFT (7U) -#define ENET_TS_STATUS_TSTRGTERR2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR2_MASK) >> ENET_TS_STATUS_TSTRGTERR2_SHIFT) - -/* - * TSTARGT2 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT2_MASK (0x40U) -#define ENET_TS_STATUS_TSTARGT2_SHIFT (6U) -#define ENET_TS_STATUS_TSTARGT2_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT2_MASK) >> ENET_TS_STATUS_TSTARGT2_SHIFT) - -/* - * TSTRGTERR1 (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR1_MASK (0x20U) -#define ENET_TS_STATUS_TSTRGTERR1_SHIFT (5U) -#define ENET_TS_STATUS_TSTRGTERR1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR1_MASK) >> ENET_TS_STATUS_TSTRGTERR1_SHIFT) - -/* - * TSTARGT1 (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT1_MASK (0x10U) -#define ENET_TS_STATUS_TSTARGT1_SHIFT (4U) -#define ENET_TS_STATUS_TSTARGT1_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT1_MASK) >> ENET_TS_STATUS_TSTARGT1_SHIFT) - -/* - * TSTRGTERR (RO) - * - */ -#define ENET_TS_STATUS_TSTRGTERR_MASK (0x8U) -#define ENET_TS_STATUS_TSTRGTERR_SHIFT (3U) -#define ENET_TS_STATUS_TSTRGTERR_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTRGTERR_MASK) >> ENET_TS_STATUS_TSTRGTERR_SHIFT) - -/* - * AUXTSTRIG (RO) - * - */ -#define ENET_TS_STATUS_AUXTSTRIG_MASK (0x4U) -#define ENET_TS_STATUS_AUXTSTRIG_SHIFT (2U) -#define ENET_TS_STATUS_AUXTSTRIG_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_AUXTSTRIG_MASK) >> ENET_TS_STATUS_AUXTSTRIG_SHIFT) - -/* - * TSTARGT (RO) - * - */ -#define ENET_TS_STATUS_TSTARGT_MASK (0x2U) -#define ENET_TS_STATUS_TSTARGT_SHIFT (1U) -#define ENET_TS_STATUS_TSTARGT_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSTARGT_MASK) >> ENET_TS_STATUS_TSTARGT_SHIFT) - -/* - * TSSOVF (RO) - * - */ -#define ENET_TS_STATUS_TSSOVF_MASK (0x1U) -#define ENET_TS_STATUS_TSSOVF_SHIFT (0U) -#define ENET_TS_STATUS_TSSOVF_GET(x) (((uint32_t)(x) & ENET_TS_STATUS_TSSOVF_MASK) >> ENET_TS_STATUS_TSSOVF_SHIFT) - -/* Bitfield definition for register: PPS_CTRL */ -/* - * TRGTMODSEL3 (RW) - * - * Target Time Register Mode for PPS3 Output - * This field indicates the Target Time registers (register 496 and 497) mode for PPS3 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL3_MASK (0x60000000UL) -#define ENET_PPS_CTRL_TRGTMODSEL3_SHIFT (29U) -#define ENET_PPS_CTRL_TRGTMODSEL3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL3_MASK) >> ENET_PPS_CTRL_TRGTMODSEL3_SHIFT) - -/* - * PPSCMD3 (WO) - * - * Flexible PPS3 Output Control - * This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD3_MASK (0x7000000UL) -#define ENET_PPS_CTRL_PPSCMD3_SHIFT (24U) -#define ENET_PPS_CTRL_PPSCMD3_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD3_SHIFT) & ENET_PPS_CTRL_PPSCMD3_MASK) -#define ENET_PPS_CTRL_PPSCMD3_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD3_MASK) >> ENET_PPS_CTRL_PPSCMD3_SHIFT) - -/* - * TRGTMODSEL2 (RW) - * - * Target Time Register Mode for PPS2 Output - * This field indicates the Target Time registers (register 488 and 489) mode for PPS2 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL2_MASK (0x600000UL) -#define ENET_PPS_CTRL_TRGTMODSEL2_SHIFT (21U) -#define ENET_PPS_CTRL_TRGTMODSEL2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL2_MASK) >> ENET_PPS_CTRL_TRGTMODSEL2_SHIFT) - -/* - * PPSCMD2 (WO) - * - * Flexible PPS2 Output Control - * This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD2_MASK (0x70000UL) -#define ENET_PPS_CTRL_PPSCMD2_SHIFT (16U) -#define ENET_PPS_CTRL_PPSCMD2_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD2_SHIFT) & ENET_PPS_CTRL_PPSCMD2_MASK) -#define ENET_PPS_CTRL_PPSCMD2_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD2_MASK) >> ENET_PPS_CTRL_PPSCMD2_SHIFT) - -/* - * TRGTMODSEL1 (RW) - * - * Target Time Register Mode for PPS1 Output - * This field indicates the Target Time registers (register 480 and 481) mode for PPS1 output signal. This field is similar to the TRGTMODSEL0 field. - */ -#define ENET_PPS_CTRL_TRGTMODSEL1_MASK (0x6000U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SHIFT (13U) -#define ENET_PPS_CTRL_TRGTMODSEL1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL1_MASK) >> ENET_PPS_CTRL_TRGTMODSEL1_SHIFT) - -/* - * PPSCMD1 (WO) - * - * Flexible PPS1 Output Control - * This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to PPSCMD0[2:0] in functionality. - */ -#define ENET_PPS_CTRL_PPSCMD1_MASK (0x700U) -#define ENET_PPS_CTRL_PPSCMD1_SHIFT (8U) -#define ENET_PPS_CTRL_PPSCMD1_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCMD1_SHIFT) & ENET_PPS_CTRL_PPSCMD1_MASK) -#define ENET_PPS_CTRL_PPSCMD1_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCMD1_MASK) >> ENET_PPS_CTRL_PPSCMD1_SHIFT) - -/* - * TRGTMODSEL0 (RW) - * - * Target Time Register Mode for PPS0 Output - * This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal: - * - 00: Indicates that the Target Time registers are programmed only for generating the interrupt event. - * - 01: Reserved - * - 10: Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the PPS0 output signal. - * - 11: Indicates that the Target Time registers are programmed only for starting or stopping the generation of the PPS0 output signal. No interrupt is asserted. - */ -#define ENET_PPS_CTRL_TRGTMODSEL0_MASK (0x60U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SHIFT (5U) -#define ENET_PPS_CTRL_TRGTMODSEL0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) -#define ENET_PPS_CTRL_TRGTMODSEL0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_TRGTMODSEL0_MASK) >> ENET_PPS_CTRL_TRGTMODSEL0_SHIFT) - -/* - * PPSEN0 (RW) - * - * Flexible PPS Output Mode Enable - * When set low, Bits [3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD. - */ -#define ENET_PPS_CTRL_PPSEN0_MASK (0x10U) -#define ENET_PPS_CTRL_PPSEN0_SHIFT (4U) -#define ENET_PPS_CTRL_PPSEN0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSEN0_SHIFT) & ENET_PPS_CTRL_PPSEN0_MASK) -#define ENET_PPS_CTRL_PPSEN0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSEN0_MASK) >> ENET_PPS_CTRL_PPSEN0_SHIFT) - -/* - * PPSCTRLCMD0 (RW/WO) - * - * PPSCTRL0: PPS0 Output Frequency Control - * This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. - * The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. - * For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies: - * - 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz. - * - 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz. - * - 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz. - * - 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz. - ... - * - 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz. - * Note: In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies. - * In the digital rollover mode, the PPS output frequency is an average number. - * The actual clock is of different frequency that gets synchronized every second. For example: - * - When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms - * - When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of: - * - One clock of 50 percent duty cycle and 537 ms period - * - Second clock of 463 ms period (268 ms low and 195 ms high) - * - When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of: - * - Three clocks of 50 percent duty cycle and 268 ms period - * - Fourth clock of 195 ms period (134 ms low and 61 ms high) - * PPSCMD0: Flexible PPS0 Output Control - * 0000: No Command - * 0001: START Single Pulse - * This command generates single pulse rising at the start point defined in - * Target Time Registers and of a duration defined - * in the PPS0 Width Register. - * 0010: START Pulse Train - * This command generates the train of pulses rising at the start point - * defined in the Target Time Registers and of a duration defined in the - * PPS0 Width Register and repeated at interval defined in the PPS - * Interval Register. By default, the PPS pulse train is free-running unless - * stopped by ‘STOP Pulse train at time’ or ‘STOP Pulse Train - * immediately’ commands. - * 0011: Cancel START - * This command cancels the START Single Pulse and START Pulse Train - * commands if the system time has not crossed the programmed start - * time. - * 0100: STOP Pulse train at time - * This command stops the train of pulses initiated by the START Pulse - * Train command (PPSCMD = 0010) after the time programmed in the - * Target Time registers elapses. - * 0101: STOP Pulse Train immediately - * This command immediately stops the train of pulses initiated by the - * START Pulse Train command (PPSCMD = 0010). - * 0110: Cancel STOP Pulse train - * This command cancels the STOP pulse train at time command if the - * programmed stop time has not elapsed. The PPS pulse train becomes - * free-running on the successful execution of this command. - * 0111-1111: Reserved - * Note: These bits get cleared automatically - */ -#define ENET_PPS_CTRL_PPSCTRLCMD0_MASK (0xFU) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT (0U) -#define ENET_PPS_CTRL_PPSCTRLCMD0_SET(x) (((uint32_t)(x) << ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) -#define ENET_PPS_CTRL_PPSCTRLCMD0_GET(x) (((uint32_t)(x) & ENET_PPS_CTRL_PPSCTRLCMD0_MASK) >> ENET_PPS_CTRL_PPSCTRLCMD0_SHIFT) - -/* Bitfield definition for register: AUX_TS_NSEC */ -/* - * AUXTSLO (RO) - * - * Contains the lower 31 bits (nano-seconds field) of the auxiliary timestamp. - */ -#define ENET_AUX_TS_NSEC_AUXTSLO_MASK (0x7FFFFFFFUL) -#define ENET_AUX_TS_NSEC_AUXTSLO_SHIFT (0U) -#define ENET_AUX_TS_NSEC_AUXTSLO_GET(x) (((uint32_t)(x) & ENET_AUX_TS_NSEC_AUXTSLO_MASK) >> ENET_AUX_TS_NSEC_AUXTSLO_SHIFT) - -/* Bitfield definition for register: AUX_TS_SEC */ -/* - * AUXTSHI (RO) - * - * Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. - */ -#define ENET_AUX_TS_SEC_AUXTSHI_MASK (0xFFFFFFFFUL) -#define ENET_AUX_TS_SEC_AUXTSHI_SHIFT (0U) -#define ENET_AUX_TS_SEC_AUXTSHI_GET(x) (((uint32_t)(x) & ENET_AUX_TS_SEC_AUXTSHI_MASK) >> ENET_AUX_TS_SEC_AUXTSHI_SHIFT) - -/* Bitfield definition for register: PPS0_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS0 Output Signal Interval - * These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS0 signal output is 100ns - * (that is, five units of sub-second increment value), then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS0_INTERVAL_PPSINT_SHIFT) & ENET_PPS0_INTERVAL_PPSINT_MASK) -#define ENET_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS0_INTERVAL_PPSINT_MASK) >> ENET_PPS0_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PPS0_WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS0 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. - * For example, if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns - * (that is, four units of sub-second increment value), then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS0_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS0_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS0_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS0_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS0_WIDTH_PPSWIDTH_MASK) >> ENET_PPS0_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_SEC */ -/* - * TSTRH1 (RW) - * - * PPS1 Target Time Seconds Register - * This register stores the time in seconds. - * When the timestamp value matches or exceeds both Target Timestamp registers, - * then based on Bits [14:13], TRGTMODSEL1, of Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - */ -#define ENET_PPS_TGTTM_SEC_TSTRH1_MASK (0xFFFFFFFFUL) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT (0U) -#define ENET_PPS_TGTTM_SEC_TSTRH1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) -#define ENET_PPS_TGTTM_SEC_TSTRH1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_SEC_TSTRH1_MASK) >> ENET_PPS_TGTTM_SEC_TSTRH1_SHIFT) - -/* Bitfield definition for register of struct array PPS: TGTTM_NSEC */ -/* - * TRGTBUSY1 (RW) - * - * PPS1 Target Time Register Busy - * The MAC sets this bit when the PPSCMD1 field (Bits [10:8]) in Register 459 (PPS Control Register) is programmed to 010 or 011. - * Programming the PPSCMD1 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to the PTP clock domain. - * The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain - * The application must not update the Targeers wht Time Registen this bit is read as 1. - * Otherwise, the synchronization of the previous programmed time gets corrupted. - */ -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK (0x80000000UL) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT (31U) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) -#define ENET_PPS_TGTTM_NSEC_TRGTBUSY1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TRGTBUSY1_MASK) >> ENET_PPS_TGTTM_NSEC_TRGTBUSY1_SHIFT) - -/* - * TTSL1 (RW) - * - * Target Time Low for PPS1 Register - * This register stores the time in (signed) nanoseconds. - * When the value of the timestamp matches the both Target Timestamp registers, - * then based on the TRGTMODSEL1 field (Bits [14:13]) in Register 459 (PPS Control Register), - * the MAC starts or stops the PPS signal output and generates an interrupt (if enabled). - * This value should not exceed 0x3B9A_C9FF when Bit 9 (TSCTRLSSR) is set in Register 448 (Timestamp Control Register). - * The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value. - */ -#define ENET_PPS_TGTTM_NSEC_TTSL1_MASK (0x7FFFFFFFUL) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT (0U) -#define ENET_PPS_TGTTM_NSEC_TTSL1_SET(x) (((uint32_t)(x) << ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) -#define ENET_PPS_TGTTM_NSEC_TTSL1_GET(x) (((uint32_t)(x) & ENET_PPS_TGTTM_NSEC_TTSL1_MASK) >> ENET_PPS_TGTTM_NSEC_TTSL1_SHIFT) - -/* Bitfield definition for register of struct array PPS: INTERVAL */ -/* - * PPSINT (RW) - * - * PPS1 Output Signal Interval - * These bits store the interval between the rising edges of PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), - * and desired interval between rising edges of PPS1 signal output is 100ns (that is, five units of sub-second increment value), - * then you should program value 4 (5 – 1) in this register. - */ -#define ENET_PPS_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define ENET_PPS_INTERVAL_PPSINT_SHIFT (0U) -#define ENET_PPS_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << ENET_PPS_INTERVAL_PPSINT_SHIFT) & ENET_PPS_INTERVAL_PPSINT_MASK) -#define ENET_PPS_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & ENET_PPS_INTERVAL_PPSINT_MASK) >> ENET_PPS_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register of struct array PPS: WIDTH */ -/* - * PPSWIDTH (RW) - * - * PPS1 Output Signal Width - * These bits store the width between the rising edge and corresponding falling edge of the PPS1 signal output in terms of units of sub-second increment value. - * You need to program one value less than the required interval. For example, - * if PTP reference clock is 50 MHz (period of 20ns), - * and desired width between the rising and corresponding falling edges of PPS1 signal output is 80ns (that is, four units of sub-second increment value), - * then you should program value 3 (4 – 1) in this register. - */ -#define ENET_PPS_WIDTH_PPSWIDTH_MASK (0xFFFFFFFFUL) -#define ENET_PPS_WIDTH_PPSWIDTH_SHIFT (0U) -#define ENET_PPS_WIDTH_PPSWIDTH_SET(x) (((uint32_t)(x) << ENET_PPS_WIDTH_PPSWIDTH_SHIFT) & ENET_PPS_WIDTH_PPSWIDTH_MASK) -#define ENET_PPS_WIDTH_PPSWIDTH_GET(x) (((uint32_t)(x) & ENET_PPS_WIDTH_PPSWIDTH_MASK) >> ENET_PPS_WIDTH_PPSWIDTH_SHIFT) - -/* Bitfield definition for register: DMA_BUS_MODE */ -/* - * RIB (RW) - * - * Rebuild INCRx Burst - * When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), - * the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. - * The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. - * By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. - */ -#define ENET_DMA_BUS_MODE_RIB_MASK (0x80000000UL) -#define ENET_DMA_BUS_MODE_RIB_SHIFT (31U) -#define ENET_DMA_BUS_MODE_RIB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RIB_SHIFT) & ENET_DMA_BUS_MODE_RIB_MASK) -#define ENET_DMA_BUS_MODE_RIB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RIB_MASK) >> ENET_DMA_BUS_MODE_RIB_SHIFT) - -/* - * PRWG (RW) - * - * Channel Priority - * Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus. - * - 00: The priority weight is 1. - * - 01: The priority weight is 2. - * - 10: The priority weight is 3. - * - 11: The priority weight is 4. This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_PRWG_MASK (0x30000000UL) -#define ENET_DMA_BUS_MODE_PRWG_SHIFT (28U) -#define ENET_DMA_BUS_MODE_PRWG_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PRWG_SHIFT) & ENET_DMA_BUS_MODE_PRWG_MASK) -#define ENET_DMA_BUS_MODE_PRWG_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PRWG_MASK) >> ENET_DMA_BUS_MODE_PRWG_SHIFT) - -/* - * TXPR (RW) - * - * Transmit Priority - * When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). - */ -#define ENET_DMA_BUS_MODE_TXPR_MASK (0x8000000UL) -#define ENET_DMA_BUS_MODE_TXPR_SHIFT (27U) -#define ENET_DMA_BUS_MODE_TXPR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_TXPR_SHIFT) & ENET_DMA_BUS_MODE_TXPR_MASK) -#define ENET_DMA_BUS_MODE_TXPR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_TXPR_MASK) >> ENET_DMA_BUS_MODE_TXPR_SHIFT) - -/* - * MB (RW) - * - * Mixed Burst - * When this bit is set high and the FB bit is low, the AHB master interface starts all bursts of length more than 16 with INCR (undefined burst), - * whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. - */ -#define ENET_DMA_BUS_MODE_MB_MASK (0x4000000UL) -#define ENET_DMA_BUS_MODE_MB_SHIFT (26U) -#define ENET_DMA_BUS_MODE_MB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_MB_SHIFT) & ENET_DMA_BUS_MODE_MB_MASK) -#define ENET_DMA_BUS_MODE_MB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_MB_MASK) >> ENET_DMA_BUS_MODE_MB_SHIFT) - -/* - * AAL (RW) - * - * Address-Aligned Beats - * When this bit is set high and the FB bit is equal to 1, - * the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, - * the first burst (accessing the start address of data buffer) is not aligned, but subsequent bursts are aligned to the address. - */ -#define ENET_DMA_BUS_MODE_AAL_MASK (0x2000000UL) -#define ENET_DMA_BUS_MODE_AAL_SHIFT (25U) -#define ENET_DMA_BUS_MODE_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_AAL_SHIFT) & ENET_DMA_BUS_MODE_AAL_MASK) -#define ENET_DMA_BUS_MODE_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_AAL_MASK) >> ENET_DMA_BUS_MODE_AAL_SHIFT) - -/* - * PBLX8 (RW) - * - * PBLx8 Mode - * When set high, this bit multiplies the programmed PBL value (Bits [22:17] and Bits[13:8]) eight times. - * Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. - */ -#define ENET_DMA_BUS_MODE_PBLX8_MASK (0x1000000UL) -#define ENET_DMA_BUS_MODE_PBLX8_SHIFT (24U) -#define ENET_DMA_BUS_MODE_PBLX8_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBLX8_SHIFT) & ENET_DMA_BUS_MODE_PBLX8_MASK) -#define ENET_DMA_BUS_MODE_PBLX8_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBLX8_MASK) >> ENET_DMA_BUS_MODE_PBLX8_SHIFT) - -/* - * USP (RW) - * - * Use Separate PBL - * When set high, this bit configures the Rx DMA to use the value configured in Bits [22:17] as PBL. - * The PBL value in Bits [13:8] is applicable only to the Tx DMA operations. - * When reset to low, the PBL value in Bits [13:8] is applicable for both DMA engines. - */ -#define ENET_DMA_BUS_MODE_USP_MASK (0x800000UL) -#define ENET_DMA_BUS_MODE_USP_SHIFT (23U) -#define ENET_DMA_BUS_MODE_USP_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_USP_SHIFT) & ENET_DMA_BUS_MODE_USP_MASK) -#define ENET_DMA_BUS_MODE_USP_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_USP_MASK) >> ENET_DMA_BUS_MODE_USP_SHIFT) - -/* - * RPBL (RW) - * - * Rx DMA PBL - * This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. - * You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. - * This field is valid and applicable only when USP is set high. - */ -#define ENET_DMA_BUS_MODE_RPBL_MASK (0x7E0000UL) -#define ENET_DMA_BUS_MODE_RPBL_SHIFT (17U) -#define ENET_DMA_BUS_MODE_RPBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_RPBL_SHIFT) & ENET_DMA_BUS_MODE_RPBL_MASK) -#define ENET_DMA_BUS_MODE_RPBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_RPBL_MASK) >> ENET_DMA_BUS_MODE_RPBL_SHIFT) - -/* - * FB (RW) - * - * Fixed Burst - * This bit controls whether the AHB or AXI master interface performs fixed burst transfers or not. - * When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. - * When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. - */ -#define ENET_DMA_BUS_MODE_FB_MASK (0x10000UL) -#define ENET_DMA_BUS_MODE_FB_SHIFT (16U) -#define ENET_DMA_BUS_MODE_FB_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_FB_SHIFT) & ENET_DMA_BUS_MODE_FB_MASK) -#define ENET_DMA_BUS_MODE_FB_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_FB_MASK) >> ENET_DMA_BUS_MODE_FB_SHIFT) - -/* - * PR (RW) - * - * Priority Ratio - * These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. - * These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set. - * - 00: The Priority Ratio is 1:1. - * - 01: The Priority Ratio is 2:1. - * - 10: The Priority Ratio is 3:1. - * - 11: The Priority Ratio is 4:1. - */ -#define ENET_DMA_BUS_MODE_PR_MASK (0xC000U) -#define ENET_DMA_BUS_MODE_PR_SHIFT (14U) -#define ENET_DMA_BUS_MODE_PR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PR_SHIFT) & ENET_DMA_BUS_MODE_PR_MASK) -#define ENET_DMA_BUS_MODE_PR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PR_MASK) >> ENET_DMA_BUS_MODE_PR_SHIFT) - -/* - * PBL (RW) - * - * Programmable Burst Length - * These bits indicate the maximum number of beats to be transferred in one DMA transaction. - * This is the maximum value that is used in a single block Read or Write. - * The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. - * PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. - * Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. - * If the number of beats to be transferred is more than 32, then perform the following steps: 1. Set the PBLx8 mode. 2. Set the PBL. - */ -#define ENET_DMA_BUS_MODE_PBL_MASK (0x3F00U) -#define ENET_DMA_BUS_MODE_PBL_SHIFT (8U) -#define ENET_DMA_BUS_MODE_PBL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_PBL_SHIFT) & ENET_DMA_BUS_MODE_PBL_MASK) -#define ENET_DMA_BUS_MODE_PBL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_PBL_MASK) >> ENET_DMA_BUS_MODE_PBL_SHIFT) - -/* - * ATDS (RW) - * - * Alternate Descriptor Size - * When set, the size of the alternate descriptor (described in “Alternate or Enhanced Descriptors” on page 545) increases to 32 bytes (8 DWORDS). - * This is required when the Advanced Timestamp feature or the IPC Full Checksum Offload Engine (Type 2) is enabled in the receiver. - * The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features are not enabled. - * In such case, you can use the 16 bytes descriptor to save 4 bytes of memory. - * This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration: - * - Advanced Timestamp feature - IPC Full Checksum Offload Engine (Type 2) feature Otherwise, this bit is reserved and is read-only. - * When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). - */ -#define ENET_DMA_BUS_MODE_ATDS_MASK (0x80U) -#define ENET_DMA_BUS_MODE_ATDS_SHIFT (7U) -#define ENET_DMA_BUS_MODE_ATDS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_ATDS_SHIFT) & ENET_DMA_BUS_MODE_ATDS_MASK) -#define ENET_DMA_BUS_MODE_ATDS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_ATDS_MASK) >> ENET_DMA_BUS_MODE_ATDS_SHIFT) - -/* - * DSL (RW) - * - * Descriptor Skip Length - * This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. - * The address skipping starts from the end of current descriptor to the start of next descriptor. - * When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. - */ -#define ENET_DMA_BUS_MODE_DSL_MASK (0x7CU) -#define ENET_DMA_BUS_MODE_DSL_SHIFT (2U) -#define ENET_DMA_BUS_MODE_DSL_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DSL_SHIFT) & ENET_DMA_BUS_MODE_DSL_MASK) -#define ENET_DMA_BUS_MODE_DSL_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DSL_MASK) >> ENET_DMA_BUS_MODE_DSL_SHIFT) - -/* - * DA (RW) - * - * DMA Arbitration Scheme - * This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0. - * - 0: Weighted round-robin with Rx:Tx or Tx:Rx The priority between the paths is according to the priority specified in Bits [15:14] (PR) and priority weights specified in Bit 27 (TXPR). - * - 1: Fixed priority The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. - */ -#define ENET_DMA_BUS_MODE_DA_MASK (0x2U) -#define ENET_DMA_BUS_MODE_DA_SHIFT (1U) -#define ENET_DMA_BUS_MODE_DA_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_DA_SHIFT) & ENET_DMA_BUS_MODE_DA_MASK) -#define ENET_DMA_BUS_MODE_DA_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_DA_MASK) >> ENET_DMA_BUS_MODE_DA_SHIFT) - -/* - * SWR (RW) - * - * Software Reset - * When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. - * It is cleared automatically after the reset operation is complete in all of the DWC_gmac clock domains. - * Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit. - * Note: - The Software reset function is driven only by this bit. - * Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function. - * - The reset operation is completed only when all resets in all active clock domains are de-asserted. - * Therefore, it is essential that all PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion. - * The time to complete the software reset operation depends on the frequency of the slowest active clock. - */ -#define ENET_DMA_BUS_MODE_SWR_MASK (0x1U) -#define ENET_DMA_BUS_MODE_SWR_SHIFT (0U) -#define ENET_DMA_BUS_MODE_SWR_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_MODE_SWR_SHIFT) & ENET_DMA_BUS_MODE_SWR_MASK) -#define ENET_DMA_BUS_MODE_SWR_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_MODE_SWR_MASK) >> ENET_DMA_BUS_MODE_SWR_SHIFT) - -/* Bitfield definition for register: DMA_TX_POLL_DEMAND */ -/* - * TPD (RW) - * - * Transmit Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 18 (Current Host Transmit Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the transmission returns to the Suspend state and Bit 2 (TU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the transmission resumes. - */ -#define ENET_DMA_TX_POLL_DEMAND_TPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT (0U) -#define ENET_DMA_TX_POLL_DEMAND_TPD_SET(x) (((uint32_t)(x) << ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) -#define ENET_DMA_TX_POLL_DEMAND_TPD_GET(x) (((uint32_t)(x) & ENET_DMA_TX_POLL_DEMAND_TPD_MASK) >> ENET_DMA_TX_POLL_DEMAND_TPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_POLL_DEMAND */ -/* - * RPD (RW) - * - * Receive Poll Demand - * When these bits are written with any value, - * the DMA reads the current descriptor to which the Register 19 (Current Host Receive Descriptor Register) is pointing. - * If that descriptor is not available (owned by the Host), - * the reception returns to the Suspended state and Bit 7 (RU) of Register 5 (Status Register) is asserted. - * If the descriptor is available, the Rx DMA returns to the active state. - */ -#define ENET_DMA_RX_POLL_DEMAND_RPD_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT (0U) -#define ENET_DMA_RX_POLL_DEMAND_RPD_SET(x) (((uint32_t)(x) << ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) -#define ENET_DMA_RX_POLL_DEMAND_RPD_GET(x) (((uint32_t)(x) & ENET_DMA_RX_POLL_DEMAND_RPD_MASK) >> ENET_DMA_RX_POLL_DEMAND_RPD_SHIFT) - -/* Bitfield definition for register: DMA_RX_DESC_LIST_ADDR */ -/* - * RDESLA (RW) - * - * Start of Receive List - * This field contains the base address of the first descriptor in the Receive Descriptor list. - * The LSB bits (1:0, 2:0, or 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT (0U) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) -#define ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_MASK) >> ENET_DMA_RX_DESC_LIST_ADDR_RDESLA_SHIFT) - -/* Bitfield definition for register: DMA_TX_DESC_LIST_ADDR */ -/* - * TDESLA (RW) - * - * Start of Transmit List - * This field contains the base address of the first descriptor in the Transmit Descriptor list. - * The LSB bits (1:0, 2:0, 3:0) for 32-bit, 64-bit, or 128-bit bus width are ignored and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO). - */ -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFFFUL) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT (0U) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SET(x) (((uint32_t)(x) << ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) -#define ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_GET(x) (((uint32_t)(x) & ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_MASK) >> ENET_DMA_TX_DESC_LIST_ADDR_TDESLA_SHIFT) - -/* Bitfield definition for register: DMA_STATUS */ -/* - * GLPII (RW) - * - * GLPII: GMAC LPI Interrupt (for Channel 0) - * This bit indicates an interrupt event in the LPI logic of the MAC. - * To reset this bit to 1'b0, the software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source. - * Note: GLPII status is given only in Channel 0 DMA register and is applicable only when the Energy Efficient Ethernet feature is enabled. Otherwise, this bit is reserved. - * When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - * -or- GTMSI: GMAC TMS Interrupt (for Channel 1 and Channel 2) This bit indicates an interrupt event in the traffic manager and scheduler logic of DWC_gmac. - * To reset this bit, the software must read the corresponding registers (Channel Status Register) to get the exact cause of the interrupt and clear its source. - * Note: GTMSI status is given only in Channel 1 and Channel 2 DMA register when the AV feature is enabled and corresponding additional transmit channels are present. - * Otherwise, this bit is reserved. When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high. - */ -#define ENET_DMA_STATUS_GLPII_MASK (0x40000000UL) -#define ENET_DMA_STATUS_GLPII_SHIFT (30U) -#define ENET_DMA_STATUS_GLPII_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLPII_SHIFT) & ENET_DMA_STATUS_GLPII_MASK) -#define ENET_DMA_STATUS_GLPII_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLPII_MASK) >> ENET_DMA_STATUS_GLPII_SHIFT) - -/* - * TTI (RW) - * - * Timestamp Trigger Interrupt - * This bit indicates an interrupt event in the Timestamp Generator block of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0. - * When this bit is high, the interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high. - * This bit is applicable only when the IEEE 1588 Timestamp feature is enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_TTI_MASK (0x20000000UL) -#define ENET_DMA_STATUS_TTI_SHIFT (29U) -#define ENET_DMA_STATUS_TTI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TTI_SHIFT) & ENET_DMA_STATUS_TTI_MASK) -#define ENET_DMA_STATUS_TTI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TTI_MASK) >> ENET_DMA_STATUS_TTI_SHIFT) - -/* - * GPI (RW) - * - * GMAC PMT Interrupt - * This bit indicates an interrupt event in the PMT module of the DWC_gmac. - * The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the Power Management feature is enabled. - * Otherwise, this bit is reserved. Note: The GPI and pmt_intr_o interrupts are generated in different clock domains. - */ -#define ENET_DMA_STATUS_GPI_MASK (0x10000000UL) -#define ENET_DMA_STATUS_GPI_SHIFT (28U) -#define ENET_DMA_STATUS_GPI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GPI_SHIFT) & ENET_DMA_STATUS_GPI_MASK) -#define ENET_DMA_STATUS_GPI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GPI_MASK) >> ENET_DMA_STATUS_GPI_SHIFT) - -/* - * GMI (RW) - * - * GMAC MMC Interrupt - * This bit reflects an interrupt event in the MMC module of the DWC_gmac. - * The software must read the corresponding registers in the DWC_gmac - * to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1’b0. - * The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - * This bit is applicable only when the MAC Management Counters (MMC) are enabled. Otherwise, this bit is reserved. - */ -#define ENET_DMA_STATUS_GMI_MASK (0x8000000UL) -#define ENET_DMA_STATUS_GMI_SHIFT (27U) -#define ENET_DMA_STATUS_GMI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GMI_SHIFT) & ENET_DMA_STATUS_GMI_MASK) -#define ENET_DMA_STATUS_GMI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GMI_MASK) >> ENET_DMA_STATUS_GMI_SHIFT) - -/* - * GLI (RW) - * - * GMAC Line Interface Interrupt - * When set, this bit reflects any of the following interrupt events in the DWC_gmac interfaces (if present and enabled in your configuration): - * - PCS (TBI, RTBI, or SGMII): Link change or auto-negotiation complete event - * - SMII or RGMII: Link change event - General Purpose Input Status (GPIS): - * Any LL or LH event on the gpi_i input ports To identify the exact cause of the interrupt, - * the software must first read Bit 11 and Bits[2:0] of Register 14 (Interrupt Status Register) and then to clear the source of interrupt (which also clears the GLI interrupt), - * read any of the following corresponding registers: - * - PCS (TBI, RTBI, or SGMII): Register 49 (AN Status Register) - * - SMII or RGMII: Register 54 (SGMII/RGMII/SMII Control and Status Register) - * - General Purpose Input (GPI): Register 56 (General Purpose IO Register) The interrupt signal from the DWC_gmac subsystem (sbd_intr_o) is high when this bit is high. - */ -#define ENET_DMA_STATUS_GLI_MASK (0x4000000UL) -#define ENET_DMA_STATUS_GLI_SHIFT (26U) -#define ENET_DMA_STATUS_GLI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_GLI_SHIFT) & ENET_DMA_STATUS_GLI_MASK) -#define ENET_DMA_STATUS_GLI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_GLI_MASK) >> ENET_DMA_STATUS_GLI_SHIFT) - -/* - * EB (RW) - * - * Error Bits - * This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. - * This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt. - * - 0 0 0: Error during Rx DMA Write Data Transfer - * - 0 1 1: Error during Tx DMA Read Data Transfer - * - 1 0 0: Error during Rx DMA Descriptor Write Access - * - 1 0 1: Error during Tx DMA Descriptor Write Access - * - 1 1 0: Error during Rx DMA Descriptor Read Access - * - 1 1 1: Error during Tx DMA Descriptor Read Access Note: 001 and 010 are reserved. - */ -#define ENET_DMA_STATUS_EB_MASK (0x3800000UL) -#define ENET_DMA_STATUS_EB_SHIFT (23U) -#define ENET_DMA_STATUS_EB_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_EB_SHIFT) & ENET_DMA_STATUS_EB_MASK) -#define ENET_DMA_STATUS_EB_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_EB_MASK) >> ENET_DMA_STATUS_EB_SHIFT) - -/* - * TS (RW) - * - * Transmit Process State - * This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped; Reset or Stop Transmit Command issued - * - 3’b001: Running; Fetching Transmit Transfer Descriptor - * - 3’b010: Running; Waiting for status - * - 3’b011: Running; Reading Data from host memory buffer and queuing it to transmit buffer (Tx FIFO) - * - 3’b100: TIME_STAMP write state - * - 3’b101: Reserved for future use - * - 3’b110: Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow - * - 3’b111: Running; Closing Transmit Descriptor - */ -#define ENET_DMA_STATUS_TS_MASK (0x700000UL) -#define ENET_DMA_STATUS_TS_SHIFT (20U) -#define ENET_DMA_STATUS_TS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TS_SHIFT) & ENET_DMA_STATUS_TS_MASK) -#define ENET_DMA_STATUS_TS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TS_MASK) >> ENET_DMA_STATUS_TS_SHIFT) - -/* - * RS (RW) - * - * Receive Process State - * This field indicates the Receive DMA FSM state. This field does not generate an interrupt. - * - 3’b000: Stopped: Reset or Stop Receive Command issued - * - 3’b001: Running: Fetching Receive Transfer Descriptor - * - 3’b010: Reserved for future use - * - 3’b011: Running: Waiting for receive packet - * - 3’b100: Suspended: Receive Descriptor Unavailable - * - 3’b101: Running: Closing Receive Descriptor - * - 3’b110: TIME_STAMP write state - * - 3’b111: Running: Transferring the receive packet data from receive buffer to host memory - */ -#define ENET_DMA_STATUS_RS_MASK (0xE0000UL) -#define ENET_DMA_STATUS_RS_SHIFT (17U) -#define ENET_DMA_STATUS_RS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RS_SHIFT) & ENET_DMA_STATUS_RS_MASK) -#define ENET_DMA_STATUS_RS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RS_MASK) >> ENET_DMA_STATUS_RS_SHIFT) - -/* - * NIS (RW) - * - * Normal Interrupt Summary - * Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in - * Register 7 (Interrupt Enable Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt Only unmasked bits - * (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_NIS_MASK (0x10000UL) -#define ENET_DMA_STATUS_NIS_SHIFT (16U) -#define ENET_DMA_STATUS_NIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_NIS_SHIFT) & ENET_DMA_STATUS_NIS_MASK) -#define ENET_DMA_STATUS_NIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_NIS_MASK) >> ENET_DMA_STATUS_NIS_SHIFT) - -/* - * AIS (RW) - * - * Abnormal Interrupt Summary - * Abnormal Interrupt Summary bit value is the logical OR of the following - * when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive FIFO Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error Only unmasked bits affect the Abnormal Interrupt Summary bit. - * This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes AIS to be set, is cleared. - */ -#define ENET_DMA_STATUS_AIS_MASK (0x8000U) -#define ENET_DMA_STATUS_AIS_SHIFT (15U) -#define ENET_DMA_STATUS_AIS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_AIS_SHIFT) & ENET_DMA_STATUS_AIS_MASK) -#define ENET_DMA_STATUS_AIS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_AIS_MASK) >> ENET_DMA_STATUS_AIS_SHIFT) - -/* - * ERI (RW) - * - * Early Receive Interrupt - * This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or Bit 6 (RI) of this register is set (whichever occurs earlier). - */ -#define ENET_DMA_STATUS_ERI_MASK (0x4000U) -#define ENET_DMA_STATUS_ERI_SHIFT (14U) -#define ENET_DMA_STATUS_ERI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ERI_SHIFT) & ENET_DMA_STATUS_ERI_MASK) -#define ENET_DMA_STATUS_ERI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ERI_MASK) >> ENET_DMA_STATUS_ERI_SHIFT) - -/* - * FBI (RW) - * - * Fatal Bus Error Interrupt - * This bit indicates that a bus error occurred, as described in Bits [25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses. - */ -#define ENET_DMA_STATUS_FBI_MASK (0x2000U) -#define ENET_DMA_STATUS_FBI_SHIFT (13U) -#define ENET_DMA_STATUS_FBI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_FBI_SHIFT) & ENET_DMA_STATUS_FBI_MASK) -#define ENET_DMA_STATUS_FBI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_FBI_MASK) >> ENET_DMA_STATUS_FBI_SHIFT) - -/* - * ETI (RW) - * - * Early Transmit Interrupt - * This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. - */ -#define ENET_DMA_STATUS_ETI_MASK (0x400U) -#define ENET_DMA_STATUS_ETI_SHIFT (10U) -#define ENET_DMA_STATUS_ETI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_ETI_SHIFT) & ENET_DMA_STATUS_ETI_MASK) -#define ENET_DMA_STATUS_ETI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_ETI_MASK) >> ENET_DMA_STATUS_ETI_SHIFT) - -/* - * RWT (RW) - * - * Receive Watchdog Timeout - * When set, this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. - */ -#define ENET_DMA_STATUS_RWT_MASK (0x200U) -#define ENET_DMA_STATUS_RWT_SHIFT (9U) -#define ENET_DMA_STATUS_RWT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RWT_SHIFT) & ENET_DMA_STATUS_RWT_MASK) -#define ENET_DMA_STATUS_RWT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RWT_MASK) >> ENET_DMA_STATUS_RWT_SHIFT) - -/* - * RPS (RW) - * - * Receive Process Stopped - * This bit is asserted when the Receive Process enters the Stopped state. - */ -#define ENET_DMA_STATUS_RPS_MASK (0x100U) -#define ENET_DMA_STATUS_RPS_SHIFT (8U) -#define ENET_DMA_STATUS_RPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RPS_SHIFT) & ENET_DMA_STATUS_RPS_MASK) -#define ENET_DMA_STATUS_RPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RPS_MASK) >> ENET_DMA_STATUS_RPS_SHIFT) - -/* - * RU (RW) - * - * Receive Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. - * The Receive Process is suspended. To resume processing Receive descriptors, - * the host should change the ownership of the descriptor and issue a Receive Poll Demand command. - * If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. - * This bit is set only when the previous Receive Descriptor is owned by the DMA. - */ -#define ENET_DMA_STATUS_RU_MASK (0x80U) -#define ENET_DMA_STATUS_RU_SHIFT (7U) -#define ENET_DMA_STATUS_RU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RU_SHIFT) & ENET_DMA_STATUS_RU_MASK) -#define ENET_DMA_STATUS_RU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RU_MASK) >> ENET_DMA_STATUS_RU_SHIFT) - -/* - * RI (RW) - * - * Receive Interrupt - * This bit indicates that the frame reception is complete. - * When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, - * and the specific frame status information is updated in the descriptor. - * The reception remains in the Running state. - */ -#define ENET_DMA_STATUS_RI_MASK (0x40U) -#define ENET_DMA_STATUS_RI_SHIFT (6U) -#define ENET_DMA_STATUS_RI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_RI_SHIFT) & ENET_DMA_STATUS_RI_MASK) -#define ENET_DMA_STATUS_RI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_RI_MASK) >> ENET_DMA_STATUS_RI_SHIFT) - -/* - * UNF (RW) - * - * Transmit Underflow - * This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set. - */ -#define ENET_DMA_STATUS_UNF_MASK (0x20U) -#define ENET_DMA_STATUS_UNF_SHIFT (5U) -#define ENET_DMA_STATUS_UNF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_UNF_SHIFT) & ENET_DMA_STATUS_UNF_MASK) -#define ENET_DMA_STATUS_UNF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_UNF_MASK) >> ENET_DMA_STATUS_UNF_SHIFT) - -/* - * OVF (RW) - * - * Receive Overflow - * This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11]. - */ -#define ENET_DMA_STATUS_OVF_MASK (0x10U) -#define ENET_DMA_STATUS_OVF_SHIFT (4U) -#define ENET_DMA_STATUS_OVF_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_OVF_SHIFT) & ENET_DMA_STATUS_OVF_MASK) -#define ENET_DMA_STATUS_OVF_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_OVF_MASK) >> ENET_DMA_STATUS_OVF_SHIFT) - -/* - * TJT (RW) - * - * Transmit Jabber Timeout - * This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). - * When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert. - */ -#define ENET_DMA_STATUS_TJT_MASK (0x8U) -#define ENET_DMA_STATUS_TJT_SHIFT (3U) -#define ENET_DMA_STATUS_TJT_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TJT_SHIFT) & ENET_DMA_STATUS_TJT_MASK) -#define ENET_DMA_STATUS_TJT_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TJT_MASK) >> ENET_DMA_STATUS_TJT_SHIFT) - -/* - * TU (RW) - * - * Transmit Buffer Unavailable - * This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. - * To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command. - */ -#define ENET_DMA_STATUS_TU_MASK (0x4U) -#define ENET_DMA_STATUS_TU_SHIFT (2U) -#define ENET_DMA_STATUS_TU_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TU_SHIFT) & ENET_DMA_STATUS_TU_MASK) -#define ENET_DMA_STATUS_TU_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TU_MASK) >> ENET_DMA_STATUS_TU_SHIFT) - -/* - * TPS (RW) - * - * Transmit Process Stopped - * This bit is set when the transmission is stopped. - */ -#define ENET_DMA_STATUS_TPS_MASK (0x2U) -#define ENET_DMA_STATUS_TPS_SHIFT (1U) -#define ENET_DMA_STATUS_TPS_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TPS_SHIFT) & ENET_DMA_STATUS_TPS_MASK) -#define ENET_DMA_STATUS_TPS_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TPS_MASK) >> ENET_DMA_STATUS_TPS_SHIFT) - -/* - * TI (RW) - * - * Transmit Interrupt - * This bit indicates that the frame transmission is complete. When transmission is complete, Bit 31 (OWN) of TDES0 is reset, and the specific frame status information is updated in the descriptor. - */ -#define ENET_DMA_STATUS_TI_MASK (0x1U) -#define ENET_DMA_STATUS_TI_SHIFT (0U) -#define ENET_DMA_STATUS_TI_SET(x) (((uint32_t)(x) << ENET_DMA_STATUS_TI_SHIFT) & ENET_DMA_STATUS_TI_MASK) -#define ENET_DMA_STATUS_TI_GET(x) (((uint32_t)(x) & ENET_DMA_STATUS_TI_MASK) >> ENET_DMA_STATUS_TI_SHIFT) - -/* Bitfield definition for register: DMA_OP_MODE */ -/* - * DT (RW) - * - * Disable Dropping of TCP/IP Checksum Error Frames - * When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. - * Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. - * When this bit is reset, all error frames are dropped if the FEF bit is reset. If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0). - */ -#define ENET_DMA_OP_MODE_DT_MASK (0x10000000UL) -#define ENET_DMA_OP_MODE_DT_SHIFT (28U) -#define ENET_DMA_OP_MODE_DT_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DT_SHIFT) & ENET_DMA_OP_MODE_DT_MASK) -#define ENET_DMA_OP_MODE_DT_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DT_MASK) >> ENET_DMA_OP_MODE_DT_SHIFT) - -/* - * RSF (RW) - * - * Receive Store and Forward - * When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. - * When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. - */ -#define ENET_DMA_OP_MODE_RSF_MASK (0x2000000UL) -#define ENET_DMA_OP_MODE_RSF_SHIFT (25U) -#define ENET_DMA_OP_MODE_RSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RSF_SHIFT) & ENET_DMA_OP_MODE_RSF_MASK) -#define ENET_DMA_OP_MODE_RSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RSF_MASK) >> ENET_DMA_OP_MODE_RSF_SHIFT) - -/* - * DFF (RW) - * - * Disable Flushing of Received Frames - * When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. (See “Receive Process Suspended” on page 83.) - */ -#define ENET_DMA_OP_MODE_DFF_MASK (0x1000000UL) -#define ENET_DMA_OP_MODE_DFF_SHIFT (24U) -#define ENET_DMA_OP_MODE_DFF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DFF_SHIFT) & ENET_DMA_OP_MODE_DFF_MASK) -#define ENET_DMA_OP_MODE_DFF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DFF_MASK) >> ENET_DMA_OP_MODE_DFF_SHIFT) - -/* - * RFA_2 (RW) - * - * MSB of Threshold for Activating Flow Control - * If the DWC_gmac is configured for an Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit), along with the RFA (Bits [10:9]), gives the following thresholds for activating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFA_2_MASK (0x800000UL) -#define ENET_DMA_OP_MODE_RFA_2_SHIFT (23U) -#define ENET_DMA_OP_MODE_RFA_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_2_SHIFT) & ENET_DMA_OP_MODE_RFA_2_MASK) -#define ENET_DMA_OP_MODE_RFA_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_2_MASK) >> ENET_DMA_OP_MODE_RFA_2_SHIFT) - -/* - * RFD_2 (RW) - * - * MSB of Threshold for Deactivating Flow Control - * If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, - * this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. - * This bit (as Most Significant Bit) along with the RFD (Bits [12:11]) gives the following thresholds for deactivating flow control: - * - 100: Full minus 5 KB, that is, FULL — 5 KB - * - 101: Full minus 6 KB, that is, FULL — 6 KB - * - 110: Full minus 7 KB, that is, FULL — 7 KB - * - 111: Reserved This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep. - */ -#define ENET_DMA_OP_MODE_RFD_2_MASK (0x400000UL) -#define ENET_DMA_OP_MODE_RFD_2_SHIFT (22U) -#define ENET_DMA_OP_MODE_RFD_2_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_2_SHIFT) & ENET_DMA_OP_MODE_RFD_2_MASK) -#define ENET_DMA_OP_MODE_RFD_2_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_2_MASK) >> ENET_DMA_OP_MODE_RFD_2_SHIFT) - -/* - * TSF (RW) - * - * Transmit Store and Forward - * When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. - * When this bit is set, the TTC values specified in Bits [16:14] are ignored. - * This bit should be changed only when the transmission is stopped. - */ -#define ENET_DMA_OP_MODE_TSF_MASK (0x200000UL) -#define ENET_DMA_OP_MODE_TSF_SHIFT (21U) -#define ENET_DMA_OP_MODE_TSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TSF_SHIFT) & ENET_DMA_OP_MODE_TSF_MASK) -#define ENET_DMA_OP_MODE_TSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TSF_MASK) >> ENET_DMA_OP_MODE_TSF_SHIFT) - -/* - * FTF (RW) - * - * Flush Transmit FIFO - * When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. - * This bit is cleared internally when the flushing operation is complete. - * The Operation Mode register should not be written to until this bit is cleared. - * The data which is already accepted by the MAC transmitter is not flushed. - * It is scheduled for transmission and results in underflow and runt frame transmission. - */ -#define ENET_DMA_OP_MODE_FTF_MASK (0x100000UL) -#define ENET_DMA_OP_MODE_FTF_SHIFT (20U) -#define ENET_DMA_OP_MODE_FTF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FTF_SHIFT) & ENET_DMA_OP_MODE_FTF_MASK) -#define ENET_DMA_OP_MODE_FTF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FTF_MASK) >> ENET_DMA_OP_MODE_FTF_SHIFT) - -/* - * TTC (RW) - * - * Transmit Threshold Control - * These bits control the threshold level of the MTL Transmit FIFO. - * Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. - * In addition, full frames with a length less than the threshold are also transmitted. - * These bits are used only when Bit 21 (TSF) is reset. - * - 000: 64 - * - 001: 128 - * - 010: 192 - * - 011: 256 - * - 100: 40 - * - 101: 32 - * - 110: 24 - * - 111: 16 - */ -#define ENET_DMA_OP_MODE_TTC_MASK (0x1C000UL) -#define ENET_DMA_OP_MODE_TTC_SHIFT (14U) -#define ENET_DMA_OP_MODE_TTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_TTC_SHIFT) & ENET_DMA_OP_MODE_TTC_MASK) -#define ENET_DMA_OP_MODE_TTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_TTC_MASK) >> ENET_DMA_OP_MODE_TTC_SHIFT) - -/* - * ST (RW) - * - * Start or Stop Transmission Command - * When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. - * Descriptor acquisition is attempted either from the current position in the list, - * which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), - * or from the position retained when transmission was stopped previously. - * If the DMA does not own the current descriptor, - * transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Transmission command is effective only when transmission is stopped. - * If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), - * then the DMA behavior is unpredictable. When this bit is reset, - * the transmission process is placed in the Stopped state after completing the transmission of the current frame. - * The Next Descriptor position in the Transmit List is saved, - * and it becomes the current position when transmission is restarted. - * To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. - * The new value is considered when this bit is set again. - * The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. - */ -#define ENET_DMA_OP_MODE_ST_MASK (0x2000U) -#define ENET_DMA_OP_MODE_ST_SHIFT (13U) -#define ENET_DMA_OP_MODE_ST_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_ST_SHIFT) & ENET_DMA_OP_MODE_ST_MASK) -#define ENET_DMA_OP_MODE_ST_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_ST_MASK) >> ENET_DMA_OP_MODE_ST_SHIFT) - -/* - * RFD (RW) - * - * Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. - * - 00: Full minus 1 KB, that is, FULL — 1 KB - * - 01: Full minus 2 KB, that is, FULL — 2 KB - * - 10: Full minus 3 KB, that is, FULL — 3 KB - * - 11: Full minus 4 KB, that is, FULL — 4 KB - * The de-assertion is effective only after flow control is asserted. - * If the Rx FIFO is 8 KB or more, an additional Bit (RFD_2) is used for more threshold levels as described in Bit 22. - * These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_RFD_MASK (0x1800U) -#define ENET_DMA_OP_MODE_RFD_SHIFT (11U) -#define ENET_DMA_OP_MODE_RFD_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFD_SHIFT) & ENET_DMA_OP_MODE_RFD_MASK) -#define ENET_DMA_OP_MODE_RFD_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFD_MASK) >> ENET_DMA_OP_MODE_RFD_SHIFT) - -/* - * RFA (RW) - * - * Threshold for Activating Flow Control (in half-duplex and full-duplex modes) - * These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. - * - 00: Full minus 1 KB, that is, FULL—1KB. - * - 01: Full minus 2 KB, that is, FULL—2KB. - * - 10: Full minus 3 KB, that is, FULL—3KB. - * - 11: Full minus 4 KB, that is, FULL—4KB. - * These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, - * an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. - * These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB. - * Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, - * the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition - */ -#define ENET_DMA_OP_MODE_RFA_MASK (0x600U) -#define ENET_DMA_OP_MODE_RFA_SHIFT (9U) -#define ENET_DMA_OP_MODE_RFA_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RFA_SHIFT) & ENET_DMA_OP_MODE_RFA_MASK) -#define ENET_DMA_OP_MODE_RFA_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RFA_MASK) >> ENET_DMA_OP_MODE_RFA_SHIFT) - -/* - * EFC (RW) - * - * Enable HW Flow Control - * When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. - * When reset, the flow control operation is disabled. - * This bit is not used (reserved and always reset) when the Rx FIFO is less than 4 KB. - */ -#define ENET_DMA_OP_MODE_EFC_MASK (0x100U) -#define ENET_DMA_OP_MODE_EFC_SHIFT (8U) -#define ENET_DMA_OP_MODE_EFC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_EFC_SHIFT) & ENET_DMA_OP_MODE_EFC_MASK) -#define ENET_DMA_OP_MODE_EFC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_EFC_MASK) >> ENET_DMA_OP_MODE_EFC_SHIFT) - -/* - * FEF (RW) - * - * Forward Error Frames - * When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). - * However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), - * then the frame is not dropped. In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, - * the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus. - * When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. - * If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, - * then the frame is dropped irrespective of the FEF bit setting. - * However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. - * Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status (in Table 8-6 or Table 8-23) in the following configurations: - * - The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected. - * - The advanced timestamp feature is not selected but the extended status is selected. - * The extended status is available with the following features: - * - L3-L4 filter in GMAC-CORE or GMAC-MTL configurations - * - Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations. - */ -#define ENET_DMA_OP_MODE_FEF_MASK (0x80U) -#define ENET_DMA_OP_MODE_FEF_SHIFT (7U) -#define ENET_DMA_OP_MODE_FEF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FEF_SHIFT) & ENET_DMA_OP_MODE_FEF_MASK) -#define ENET_DMA_OP_MODE_FEF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FEF_MASK) >> ENET_DMA_OP_MODE_FEF_SHIFT) - -/* - * FUF (RW) - * - * Forward Undersized Good Frames - * When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error and length less than 64 bytes) including pad-bytes and CRC - * When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. - */ -#define ENET_DMA_OP_MODE_FUF_MASK (0x40U) -#define ENET_DMA_OP_MODE_FUF_SHIFT (6U) -#define ENET_DMA_OP_MODE_FUF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_FUF_SHIFT) & ENET_DMA_OP_MODE_FUF_MASK) -#define ENET_DMA_OP_MODE_FUF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_FUF_MASK) >> ENET_DMA_OP_MODE_FUF_SHIFT) - -/* - * DGF (RW) - * - * Drop Giant Frames - * When set, the MAC drops the received giant frames in the Rx FIFO, - * that is, frames that are larger than the computed giant frame limit. - * When reset, the MAC does not drop the giant frames in the Rx FIFO. - * Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default: - * - Configurations in which IP Checksum Offload (Type 1) is selected in Rx - * - Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format - * - Configurations in which the Advanced Timestamp feature is selected In all other configurations, this bit is not used (reserved and always reset). - */ -#define ENET_DMA_OP_MODE_DGF_MASK (0x20U) -#define ENET_DMA_OP_MODE_DGF_SHIFT (5U) -#define ENET_DMA_OP_MODE_DGF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_DGF_SHIFT) & ENET_DMA_OP_MODE_DGF_MASK) -#define ENET_DMA_OP_MODE_DGF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_DGF_MASK) >> ENET_DMA_OP_MODE_DGF_SHIFT) - -/* - * RTC (RW) - * - * Receive Threshold Control - * These two bits control the threshold level of the MTL Receive FIFO. - * Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. - * In addition, full frames with length less than the threshold are automatically transferred. - * The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. - * These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. - * - 00: 64 - * - 01: 32 - * - 10: 96 - * - 11: 128 - */ -#define ENET_DMA_OP_MODE_RTC_MASK (0x18U) -#define ENET_DMA_OP_MODE_RTC_SHIFT (3U) -#define ENET_DMA_OP_MODE_RTC_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_RTC_SHIFT) & ENET_DMA_OP_MODE_RTC_MASK) -#define ENET_DMA_OP_MODE_RTC_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_RTC_MASK) >> ENET_DMA_OP_MODE_RTC_SHIFT) - -/* - * OSF (RW) - * - * Operate on Second Frame - * When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. - */ -#define ENET_DMA_OP_MODE_OSF_MASK (0x4U) -#define ENET_DMA_OP_MODE_OSF_SHIFT (2U) -#define ENET_DMA_OP_MODE_OSF_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_OSF_SHIFT) & ENET_DMA_OP_MODE_OSF_MASK) -#define ENET_DMA_OP_MODE_OSF_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_OSF_MASK) >> ENET_DMA_OP_MODE_OSF_SHIFT) - -/* - * SR (RW) - * - * Start or Stop Receive - * When this bit is set, the Receive process is placed in the Running state. - * The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. - * The descriptor acquisition is attempted from the current position in the list, - * which is the address set by the Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. - * If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. - * The Start Receive command is effective only when the reception has stopped. - * If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. - * When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. - * The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. - * The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. - */ -#define ENET_DMA_OP_MODE_SR_MASK (0x2U) -#define ENET_DMA_OP_MODE_SR_SHIFT (1U) -#define ENET_DMA_OP_MODE_SR_SET(x) (((uint32_t)(x) << ENET_DMA_OP_MODE_SR_SHIFT) & ENET_DMA_OP_MODE_SR_MASK) -#define ENET_DMA_OP_MODE_SR_GET(x) (((uint32_t)(x) & ENET_DMA_OP_MODE_SR_MASK) >> ENET_DMA_OP_MODE_SR_SHIFT) - -/* Bitfield definition for register: DMA_INTR_EN */ -/* - * NIE (RW) - * - * Normal Interrupt Summary Enable - * When this bit is set, normal interrupt summary is enabled. - * When this bit is reset, normal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[0]: Transmit Interrupt - * - Register 5[2]: Transmit Buffer Unavailable - * - Register 5[6]: Receive Interrupt - * - Register 5[14]: Early Receive Interrupt - */ -#define ENET_DMA_INTR_EN_NIE_MASK (0x10000UL) -#define ENET_DMA_INTR_EN_NIE_SHIFT (16U) -#define ENET_DMA_INTR_EN_NIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_NIE_SHIFT) & ENET_DMA_INTR_EN_NIE_MASK) -#define ENET_DMA_INTR_EN_NIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_NIE_MASK) >> ENET_DMA_INTR_EN_NIE_SHIFT) - -/* - * AIE (RW) - * - * Abnormal Interrupt Summary Enable - * When this bit is set, abnormal interrupt summary is enabled. - * When this bit is reset, the abnormal interrupt summary is disabled. - * This bit enables the following interrupts in Register 5 (Status Register): - * - Register 5[1]: Transmit Process Stopped - * - Register 5[3]: Transmit Jabber Timeout - * - Register 5[4]: Receive Overflow - * - Register 5[5]: Transmit Underflow - * - Register 5[7]: Receive Buffer Unavailable - * - Register 5[8]: Receive Process Stopped - * - Register 5[9]: Receive Watchdog Timeout - * - Register 5[10]: Early Transmit Interrupt - * - Register 5[13]: Fatal Bus Error - */ -#define ENET_DMA_INTR_EN_AIE_MASK (0x8000U) -#define ENET_DMA_INTR_EN_AIE_SHIFT (15U) -#define ENET_DMA_INTR_EN_AIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_AIE_SHIFT) & ENET_DMA_INTR_EN_AIE_MASK) -#define ENET_DMA_INTR_EN_AIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_AIE_MASK) >> ENET_DMA_INTR_EN_AIE_SHIFT) - -/* - * ERE (RW) - * - * Early Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ERE_MASK (0x4000U) -#define ENET_DMA_INTR_EN_ERE_SHIFT (14U) -#define ENET_DMA_INTR_EN_ERE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ERE_SHIFT) & ENET_DMA_INTR_EN_ERE_MASK) -#define ENET_DMA_INTR_EN_ERE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ERE_MASK) >> ENET_DMA_INTR_EN_ERE_SHIFT) - -/* - * FBE (RW) - * - * Fatal Bus Error Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_FBE_MASK (0x2000U) -#define ENET_DMA_INTR_EN_FBE_SHIFT (13U) -#define ENET_DMA_INTR_EN_FBE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_FBE_SHIFT) & ENET_DMA_INTR_EN_FBE_MASK) -#define ENET_DMA_INTR_EN_FBE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_FBE_MASK) >> ENET_DMA_INTR_EN_FBE_SHIFT) - -/* - * ETE (RW) - * - * Early Transmit Interrupt Enable - * When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_ETE_MASK (0x400U) -#define ENET_DMA_INTR_EN_ETE_SHIFT (10U) -#define ENET_DMA_INTR_EN_ETE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_ETE_SHIFT) & ENET_DMA_INTR_EN_ETE_MASK) -#define ENET_DMA_INTR_EN_ETE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_ETE_MASK) >> ENET_DMA_INTR_EN_ETE_SHIFT) - -/* - * RWE (RW) - * - * Receive Watchdog Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RWE_MASK (0x200U) -#define ENET_DMA_INTR_EN_RWE_SHIFT (9U) -#define ENET_DMA_INTR_EN_RWE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RWE_SHIFT) & ENET_DMA_INTR_EN_RWE_MASK) -#define ENET_DMA_INTR_EN_RWE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RWE_MASK) >> ENET_DMA_INTR_EN_RWE_SHIFT) - -/* - * RSE (RW) - * - * Receive Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RSE_MASK (0x100U) -#define ENET_DMA_INTR_EN_RSE_SHIFT (8U) -#define ENET_DMA_INTR_EN_RSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RSE_SHIFT) & ENET_DMA_INTR_EN_RSE_MASK) -#define ENET_DMA_INTR_EN_RSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RSE_MASK) >> ENET_DMA_INTR_EN_RSE_SHIFT) - -/* - * RUE (RW) - * - * Receive Buffer Unavailable Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RUE_MASK (0x80U) -#define ENET_DMA_INTR_EN_RUE_SHIFT (7U) -#define ENET_DMA_INTR_EN_RUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RUE_SHIFT) & ENET_DMA_INTR_EN_RUE_MASK) -#define ENET_DMA_INTR_EN_RUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RUE_MASK) >> ENET_DMA_INTR_EN_RUE_SHIFT) - -/* - * RIE (RW) - * - * Receive Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_RIE_MASK (0x40U) -#define ENET_DMA_INTR_EN_RIE_SHIFT (6U) -#define ENET_DMA_INTR_EN_RIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_RIE_SHIFT) & ENET_DMA_INTR_EN_RIE_MASK) -#define ENET_DMA_INTR_EN_RIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_RIE_MASK) >> ENET_DMA_INTR_EN_RIE_SHIFT) - -/* - * UNE (RW) - * - * Underflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_UNE_MASK (0x20U) -#define ENET_DMA_INTR_EN_UNE_SHIFT (5U) -#define ENET_DMA_INTR_EN_UNE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_UNE_SHIFT) & ENET_DMA_INTR_EN_UNE_MASK) -#define ENET_DMA_INTR_EN_UNE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_UNE_MASK) >> ENET_DMA_INTR_EN_UNE_SHIFT) - -/* - * OVE (RW) - * - * Overflow Interrupt Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_OVE_MASK (0x10U) -#define ENET_DMA_INTR_EN_OVE_SHIFT (4U) -#define ENET_DMA_INTR_EN_OVE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_OVE_SHIFT) & ENET_DMA_INTR_EN_OVE_MASK) -#define ENET_DMA_INTR_EN_OVE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_OVE_MASK) >> ENET_DMA_INTR_EN_OVE_SHIFT) - -/* - * TJE (RW) - * - * Transmit Jabber Timeout Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TJE_MASK (0x8U) -#define ENET_DMA_INTR_EN_TJE_SHIFT (3U) -#define ENET_DMA_INTR_EN_TJE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TJE_SHIFT) & ENET_DMA_INTR_EN_TJE_MASK) -#define ENET_DMA_INTR_EN_TJE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TJE_MASK) >> ENET_DMA_INTR_EN_TJE_SHIFT) - -/* - * TUE (RW) - * - * Transmit Buffer Unavailable Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TUE_MASK (0x4U) -#define ENET_DMA_INTR_EN_TUE_SHIFT (2U) -#define ENET_DMA_INTR_EN_TUE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TUE_SHIFT) & ENET_DMA_INTR_EN_TUE_MASK) -#define ENET_DMA_INTR_EN_TUE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TUE_MASK) >> ENET_DMA_INTR_EN_TUE_SHIFT) - -/* - * TSE (RW) - * - * Transmit Stopped Enable - * When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TSE_MASK (0x2U) -#define ENET_DMA_INTR_EN_TSE_SHIFT (1U) -#define ENET_DMA_INTR_EN_TSE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TSE_SHIFT) & ENET_DMA_INTR_EN_TSE_MASK) -#define ENET_DMA_INTR_EN_TSE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TSE_MASK) >> ENET_DMA_INTR_EN_TSE_SHIFT) - -/* - * TIE (RW) - * - * Transmit Interrupt Enable - * When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled. - */ -#define ENET_DMA_INTR_EN_TIE_MASK (0x1U) -#define ENET_DMA_INTR_EN_TIE_SHIFT (0U) -#define ENET_DMA_INTR_EN_TIE_SET(x) (((uint32_t)(x) << ENET_DMA_INTR_EN_TIE_SHIFT) & ENET_DMA_INTR_EN_TIE_MASK) -#define ENET_DMA_INTR_EN_TIE_GET(x) (((uint32_t)(x) & ENET_DMA_INTR_EN_TIE_MASK) >> ENET_DMA_INTR_EN_TIE_SHIFT) - -/* Bitfield definition for register: DMA_MISS_OVF_CNT */ -/* - * ONFCNTOVF (RW) - * - * Overflow Bit for FIFO Overflow Counter - * This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, - * that is, the Rx FIFO overflows with the overflow frame counter at maximum value. - * In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK (0x10000000UL) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT (28U) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_ONFCNTOVF_SHIFT) - -/* - * OVFFRMCNT (RW) - * - * Overflow Frame Counter - * This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK (0xFFE0000UL) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT (17U) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_OVFFRMCNT_SHIFT) - -/* - * MISCNTOVF (RW) - * - * Overflow Bit for Missed Frame Counter - * This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, - * that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, - * the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. - */ -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK (0x10000UL) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT (16U) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISCNTOVF_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISCNTOVF_MASK) >> ENET_DMA_MISS_OVF_CNT_MISCNTOVF_SHIFT) - -/* - * MISFRMCNT (RW) - * - * Missed Frame Counter - * This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. - * This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1’b1. - */ -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK (0xFFFFU) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT (0U) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SET(x) (((uint32_t)(x) << ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) -#define ENET_DMA_MISS_OVF_CNT_MISFRMCNT_GET(x) (((uint32_t)(x) & ENET_DMA_MISS_OVF_CNT_MISFRMCNT_MASK) >> ENET_DMA_MISS_OVF_CNT_MISFRMCNT_SHIFT) - -/* Bitfield definition for register: DMA_RX_INTR_WDOG */ -/* - * RIWT (RW) - * - * RI Watchdog Timer Count - * This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. - * The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer - * of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. - * When the watchdog timer runs out, the RI bit is set and the timer is stopped. - * The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame. - */ -#define ENET_DMA_RX_INTR_WDOG_RIWT_MASK (0xFFU) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT (0U) -#define ENET_DMA_RX_INTR_WDOG_RIWT_SET(x) (((uint32_t)(x) << ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) -#define ENET_DMA_RX_INTR_WDOG_RIWT_GET(x) (((uint32_t)(x) & ENET_DMA_RX_INTR_WDOG_RIWT_MASK) >> ENET_DMA_RX_INTR_WDOG_RIWT_SHIFT) - -/* Bitfield definition for register: DMA_AXI_MODE */ -/* - * EN_LPI (RW) - * - * Enable Low Power Interface (LPI) - * When set to 1, this bit enables the LPI mode supported by the GMAC-AXI configuration and accepts the LPI request from the AXI System Clock controller. - * When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. - */ -#define ENET_DMA_AXI_MODE_EN_LPI_MASK (0x80000000UL) -#define ENET_DMA_AXI_MODE_EN_LPI_SHIFT (31U) -#define ENET_DMA_AXI_MODE_EN_LPI_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_EN_LPI_SHIFT) & ENET_DMA_AXI_MODE_EN_LPI_MASK) -#define ENET_DMA_AXI_MODE_EN_LPI_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_EN_LPI_MASK) >> ENET_DMA_AXI_MODE_EN_LPI_SHIFT) - -/* - * LPI_XIT_FRM (RW) - * - * Unlock on Magic Packet or Remote Wake-Up Frame - * When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the magic packet or remote wake-up frame is received. - * When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. - */ -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK (0x40000000UL) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT (30U) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) -#define ENET_DMA_AXI_MODE_LPI_XIT_FRM_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_LPI_XIT_FRM_MASK) >> ENET_DMA_AXI_MODE_LPI_XIT_FRM_SHIFT) - -/* - * WR_OSR_LMT (RW) - * - * AXI Maximum Write Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI write interface. - * Maximum outstanding requests = WR_OSR_LMT+1 Note: - Bit 22 is reserved if AXI_GM_MAX_WR_REQUESTS = 4. - Bit 23 bit is reserved if AXI_GM_MAX_WR_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK (0xF00000UL) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT (20U) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_WR_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_WR_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_WR_OSR_LMT_SHIFT) - -/* - * RD_OSR_LMT (RW) - * - * AXI Maximum Read Outstanding Request Limit - * This value limits the maximum outstanding request on the AXI read interface. - * Maximum outstanding requests = RD_OSR_LMT+1 Note: - Bit 18 is reserved if AXI_GM_MAX_RD_REQUESTS = 4. - Bit 19 is reserved if AXI_GM_MAX_RD_REQUESTS != 16. - */ -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK (0xF0000UL) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT (16U) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) -#define ENET_DMA_AXI_MODE_RD_OSR_LMT_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_RD_OSR_LMT_MASK) >> ENET_DMA_AXI_MODE_RD_OSR_LMT_SHIFT) - -/* - * ONEKBBE (RW) - * - * 1 KB Boundary Crossing Enable for the GMAC-AXI Master - * When set, the GMAC-AXI master performs burst transfers that do not cross 1 KB boundary. - * When reset, the GMAC-AXI master performs burst transfers that do not cross 4 KB boundary. - */ -#define ENET_DMA_AXI_MODE_ONEKBBE_MASK (0x2000U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SHIFT (13U) -#define ENET_DMA_AXI_MODE_ONEKBBE_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) -#define ENET_DMA_AXI_MODE_ONEKBBE_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_ONEKBBE_MASK) >> ENET_DMA_AXI_MODE_ONEKBBE_SHIFT) - -/* - * AXI_AAL (RW) - * - * Address-Aligned Beats - * This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). - * When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. - */ -#define ENET_DMA_AXI_MODE_AXI_AAL_MASK (0x1000U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SHIFT (12U) -#define ENET_DMA_AXI_MODE_AXI_AAL_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) -#define ENET_DMA_AXI_MODE_AXI_AAL_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_AXI_AAL_MASK) >> ENET_DMA_AXI_MODE_AXI_AAL_SHIFT) - -/* - * BLEN256 (RW) - * - * AXI Burst Length 256 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 256 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 256. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN256_MASK (0x80U) -#define ENET_DMA_AXI_MODE_BLEN256_SHIFT (7U) -#define ENET_DMA_AXI_MODE_BLEN256_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN256_SHIFT) & ENET_DMA_AXI_MODE_BLEN256_MASK) -#define ENET_DMA_AXI_MODE_BLEN256_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN256_MASK) >> ENET_DMA_AXI_MODE_BLEN256_SHIFT) - -/* - * BLEN128 (RW) - * - * AXI Burst Length 128 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 128 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 128 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN128_MASK (0x40U) -#define ENET_DMA_AXI_MODE_BLEN128_SHIFT (6U) -#define ENET_DMA_AXI_MODE_BLEN128_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN128_SHIFT) & ENET_DMA_AXI_MODE_BLEN128_MASK) -#define ENET_DMA_AXI_MODE_BLEN128_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN128_MASK) >> ENET_DMA_AXI_MODE_BLEN128_SHIFT) - -/* - * BLEN64 (RW) - * - * AXI Burst Length 64 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 64 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 64 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN64_MASK (0x20U) -#define ENET_DMA_AXI_MODE_BLEN64_SHIFT (5U) -#define ENET_DMA_AXI_MODE_BLEN64_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN64_SHIFT) & ENET_DMA_AXI_MODE_BLEN64_MASK) -#define ENET_DMA_AXI_MODE_BLEN64_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN64_MASK) >> ENET_DMA_AXI_MODE_BLEN64_SHIFT) - -/* - * BLEN32 (RW) - * - * AXI Burst Length 32 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 32 on the AXI master interface. - * This bit is present only when the configuration parameter AXI_BL is set to 32 or more. Otherwise, this bit is reserved and is read-only (RO). - */ -#define ENET_DMA_AXI_MODE_BLEN32_MASK (0x10U) -#define ENET_DMA_AXI_MODE_BLEN32_SHIFT (4U) -#define ENET_DMA_AXI_MODE_BLEN32_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN32_SHIFT) & ENET_DMA_AXI_MODE_BLEN32_MASK) -#define ENET_DMA_AXI_MODE_BLEN32_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN32_MASK) >> ENET_DMA_AXI_MODE_BLEN32_SHIFT) - -/* - * BLEN16 (RW) - * - * AXI Burst Length 16 - * When this bit is set to 1 or UNDEF is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI master interface. - */ -#define ENET_DMA_AXI_MODE_BLEN16_MASK (0x8U) -#define ENET_DMA_AXI_MODE_BLEN16_SHIFT (3U) -#define ENET_DMA_AXI_MODE_BLEN16_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN16_SHIFT) & ENET_DMA_AXI_MODE_BLEN16_MASK) -#define ENET_DMA_AXI_MODE_BLEN16_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN16_MASK) >> ENET_DMA_AXI_MODE_BLEN16_SHIFT) - -/* - * BLEN8 (RW) - * - * AXI Burst Length 8 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN8_MASK (0x4U) -#define ENET_DMA_AXI_MODE_BLEN8_SHIFT (2U) -#define ENET_DMA_AXI_MODE_BLEN8_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN8_SHIFT) & ENET_DMA_AXI_MODE_BLEN8_MASK) -#define ENET_DMA_AXI_MODE_BLEN8_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN8_MASK) >> ENET_DMA_AXI_MODE_BLEN8_SHIFT) - -/* - * BLEN4 (RW) - * - * AXI Burst Length 4 - * When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI master interface. - * Setting this bit has no effect when UNDEF is set to 1. - */ -#define ENET_DMA_AXI_MODE_BLEN4_MASK (0x2U) -#define ENET_DMA_AXI_MODE_BLEN4_SHIFT (1U) -#define ENET_DMA_AXI_MODE_BLEN4_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_BLEN4_SHIFT) & ENET_DMA_AXI_MODE_BLEN4_MASK) -#define ENET_DMA_AXI_MODE_BLEN4_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_BLEN4_MASK) >> ENET_DMA_AXI_MODE_BLEN4_SHIFT) - -/* - * UNDEF (RW) - * - * AXI Undefined Burst Length - * This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register). - * - When this bit is set to 1, the GMAC-AXI is allowed to perform any burst length equal to or below the maximum allowed burst length programmed in Bits[7:3]. - * - When this bit is set to 0, the GMAC-AXI is allowed to perform only fixed burst lengths as indicated by BLEN256, BLEN128, BLEN64, BLEN32, BLEN16, BLEN8, or BLEN4, or a burst length of 1. - * If UNDEF is set and none of the BLEN bits is set, then GMAC-AXI is allowed to perform a burst length of 16. - */ -#define ENET_DMA_AXI_MODE_UNDEF_MASK (0x1U) -#define ENET_DMA_AXI_MODE_UNDEF_SHIFT (0U) -#define ENET_DMA_AXI_MODE_UNDEF_SET(x) (((uint32_t)(x) << ENET_DMA_AXI_MODE_UNDEF_SHIFT) & ENET_DMA_AXI_MODE_UNDEF_MASK) -#define ENET_DMA_AXI_MODE_UNDEF_GET(x) (((uint32_t)(x) & ENET_DMA_AXI_MODE_UNDEF_MASK) >> ENET_DMA_AXI_MODE_UNDEF_SHIFT) - -/* Bitfield definition for register: DMA_BUS_STATUS */ -/* - * AXIRDSTS (RW) - * - * AXI Master Read Channel Status - * When high, it indicates that AXI master's read channel is active and transferring data. - */ -#define ENET_DMA_BUS_STATUS_AXIRDSTS_MASK (0x2U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT (1U) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXIRDSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXIRDSTS_MASK) >> ENET_DMA_BUS_STATUS_AXIRDSTS_SHIFT) - -/* - * AXWHSTS (RW) - * - * AXI Master Write Channel or AHB Master Status - * When high, it indicates that AXI master's write channel is active and transferring data in the GMAC-AXI configuration. In the GMAC-AHB configuration, - * it indicates that the AHB master interface FSMs are in the non-idle state. - */ -#define ENET_DMA_BUS_STATUS_AXWHSTS_MASK (0x1U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT (0U) -#define ENET_DMA_BUS_STATUS_AXWHSTS_SET(x) (((uint32_t)(x) << ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) -#define ENET_DMA_BUS_STATUS_AXWHSTS_GET(x) (((uint32_t)(x) & ENET_DMA_BUS_STATUS_AXWHSTS_MASK) >> ENET_DMA_BUS_STATUS_AXWHSTS_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_DESC */ -/* - * CURTDESAPTR (RW) - * - * Host Transmit Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_DESC_CURTDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_DESC */ -/* - * CURRDESAPTR (RW) - * - * Host Receive Descriptor Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_DESC_CURRDESAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_TX_BUF */ -/* - * CURTBUFAPTR (RW) - * - * Host Transmit Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_TX_BUF_CURTBUFAPTR_SHIFT) - -/* Bitfield definition for register: DMA_CURR_HOST_RX_BUF */ -/* - * CURRBUFAPTR (RW) - * - * Host Receive Buffer Address Pointer - * Cleared on Reset. Pointer updated by the DMA during operation. - */ -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK (0xFFFFFFFFUL) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT (0U) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SET(x) (((uint32_t)(x) << ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) -#define ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_GET(x) (((uint32_t)(x) & ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_MASK) >> ENET_DMA_CURR_HOST_RX_BUF_CURRBUFAPTR_SHIFT) - -/* Bitfield definition for register: CTRL0 */ -/* - * ENET0_RXCLK_DLY_SEL (RW) - * - */ -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK (0x3F00U) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT (8U) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) -#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SHIFT) - -/* - * ENET0_TXCLK_DLY_SEL (RW) - * - */ -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK (0x3FU) -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT (0U) -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) -#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK) >> ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SHIFT) - -/* Bitfield definition for register: CTRL2 */ -/* - * ENET0_LPI_IRQ_EN (RW) - * - * lowpower interrupt enable, for internal use only, user should use core registers for enable/disable interrupt - */ -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK (0x20000000UL) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT (29U) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) -#define ENET_CTRL2_ENET0_LPI_IRQ_EN_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK) >> ENET_CTRL2_ENET0_LPI_IRQ_EN_SHIFT) - -/* - * ENET0_REFCLK_OE (RW) - * - * set to enable output 50MHz clock to rmii phy. - * User should set it if use soc internal clock as refclk - */ -#define ENET_CTRL2_ENET0_REFCLK_OE_MASK (0x80000UL) -#define ENET_CTRL2_ENET0_REFCLK_OE_SHIFT (19U) -#define ENET_CTRL2_ENET0_REFCLK_OE_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) -#define ENET_CTRL2_ENET0_REFCLK_OE_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_REFCLK_OE_MASK) >> ENET_CTRL2_ENET0_REFCLK_OE_SHIFT) - -/* - * ENET0_PHY_INF_SEL (RW) - * - * PHY mode select - * 000MII; 001RGMII; 100RMII; - * should be set before config IOMUX, otherwise may cause glitch for RGMII - */ -#define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK (0xE000U) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT (13U) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) -#define ENET_CTRL2_ENET0_PHY_INF_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_PHY_INF_SEL_MASK) >> ENET_CTRL2_ENET0_PHY_INF_SEL_SHIFT) - -/* - * ENET0_FLOWCTRL (RW) - * - * flow control request - */ -#define ENET_CTRL2_ENET0_FLOWCTRL_MASK (0x1000U) -#define ENET_CTRL2_ENET0_FLOWCTRL_SHIFT (12U) -#define ENET_CTRL2_ENET0_FLOWCTRL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) -#define ENET_CTRL2_ENET0_FLOWCTRL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_FLOWCTRL_MASK) >> ENET_CTRL2_ENET0_FLOWCTRL_SHIFT) - -/* - * ENET0_RMII_TXCLK_SEL (RW) - * - * RMII mode output clock pad select - * set to use txck as RMII refclk; - * clr to use rxck as RMII refclk; default 0(rxck) - * refclk is always from pad, can use external clock from pad, or use internal clock output to pad then loopback. - */ -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK (0x400U) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT (10U) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) -#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK) >> ENET_CTRL2_ENET0_RMII_TXCLK_SEL_SHIFT) - - - -/* MAC_ADDR register group index macro definition */ -#define ENET_MAC_ADDR_1 (0UL) -#define ENET_MAC_ADDR_2 (1UL) -#define ENET_MAC_ADDR_3 (2UL) -#define ENET_MAC_ADDR_4 (3UL) - -/* L3_L4_CFG register group index macro definition */ -#define ENET_L3_L4_CFG_0 (0UL) - -/* PPS register group index macro definition */ -#define ENET_PPS_1 (0UL) -#define ENET_PPS_2 (1UL) -#define ENET_PPS_3 (2UL) - - -#endif /* HPM_ENET_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_esc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_esc_regs.h deleted file mode 100644 index 033fa6d1e18..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_esc_regs.h +++ /dev/null @@ -1,4534 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_ESC_H -#define HPM_ESC_H - -typedef struct { - __R uint8_t TYPE; /* 0x0: Type of EtherCAT controller */ - __R uint8_t REVISION; /* 0x1: Revision of EtherCAT controller */ - __R uint16_t BUILD; /* 0x2: Build of EtherCAT controller */ - __R uint8_t FMMU_NUM; /* 0x4: FMMU supported */ - __R uint8_t SYNCM_NUM; /* 0x5: SyncManagers supported */ - __R uint8_t RAM_SIZE; /* 0x6: RAM Size */ - __R uint8_t PORT_DESC; /* 0x7: Port Descriptor */ - __R uint16_t FEATURE; /* 0x8: ESC Feature supported */ - __R uint8_t RESERVED0[6]; /* 0xA - 0xF: Reserved */ - __R uint16_t STATION_ADDR; /* 0x10: Configured Station Address */ - __RW uint16_t STATION_ALS; /* 0x12: Configured Station Alias */ - __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ - __R uint8_t REG_WEN; /* 0x20: Register Write Enable */ - __R uint8_t REG_WP; /* 0x21: Register Write Protection */ - __R uint8_t RESERVED2[14]; /* 0x22 - 0x2F: Reserved */ - __R uint8_t ESC_WEN; /* 0x30: ESC Write Enable */ - __R uint8_t ESC_WP; /* 0x31: ESC Write Protection */ - __R uint8_t RESERVED3[14]; /* 0x32 - 0x3F: Reserved */ - __R uint8_t ESC_RST_ECAT; /* 0x40: ESC Reset ECAT */ - __RW uint8_t ESC_RST_PDI; /* 0x41: ESC Reset PDI */ - __R uint8_t RESERVED4[190]; /* 0x42 - 0xFF: Reserved */ - __R uint32_t ESC_DL_CTRL; /* 0x100: ESC DL Control */ - __R uint8_t RESERVED5[4]; /* 0x104 - 0x107: Reserved */ - __R uint16_t PHYSICAL_RW_OFFSET; /* 0x108: Physical Read/Write Offset */ - __R uint8_t RESERVED6[6]; /* 0x10A - 0x10F: Reserved */ - __R uint16_t ESC_DL_STAT; /* 0x110: ESC DL Status */ - __R uint8_t RESERVED7[14]; /* 0x112 - 0x11F: Reserved */ - __RW uint16_t AL_CTRL; /* 0x120: AL Control */ - __R uint8_t RESERVED8[14]; /* 0x122 - 0x12F: Reserved */ - __RW uint16_t AL_STAT; /* 0x130: AL Status */ - __R uint8_t RESERVED9[2]; /* 0x132 - 0x133: Reserved */ - __RW uint16_t AL_STAT_CODE; /* 0x134: AL Status Code */ - __R uint8_t RESERVED10[2]; /* 0x136 - 0x137: Reserved */ - __RW uint8_t RUN_LED_OVRD; /* 0x138: RUN LED Override */ - __RW uint8_t ERR_LED_OVRD; /* 0x139: ERR LED Override */ - __R uint8_t RESERVED11[6]; /* 0x13A - 0x13F: Reserved */ - __R uint8_t PDI_CTRL; /* 0x140: PDI Control */ - __R uint8_t ESC_CFG; /* 0x141: ESC Configuration */ - __R uint8_t RESERVED12[12]; /* 0x142 - 0x14D: Reserved */ - __R uint16_t PDI_INFO; /* 0x14E: PDI Information */ - __R uint8_t PDI_CFG; /* 0x150: PDI Configuration */ - __R uint8_t PDI_SL_CFG; /* 0x151: PDI Sync/Latch[1:0] Configuration */ - __RW uint16_t PDI_EXT_CFG; /* 0x152: PDI Extended Configuration */ - __R uint8_t RESERVED13[172]; /* 0x154 - 0x1FF: Reserved */ - __R uint16_t ECAT_EVT_MSK; /* 0x200: ECAT Event Mask */ - __R uint8_t RESERVED14[2]; /* 0x202 - 0x203: Reserved */ - __RW uint32_t PDI_AL_EVT_MSK; /* 0x204: PDI AL Event Mask */ - __R uint8_t RESERVED15[8]; /* 0x208 - 0x20F: Reserved */ - __R uint16_t ECAT_EVT_REQ; /* 0x210: ECAT Event Request */ - __R uint8_t RESERVED16[14]; /* 0x212 - 0x21F: Reserved */ - __R uint32_t AL_EVT_REQ; /* 0x220: AL Event Request */ - __R uint8_t RESERVED17[220]; /* 0x224 - 0x2FF: Reserved */ - __R uint16_t RX_ERR_CNT[4]; /* 0x300 - 0x306: RX Error Counter */ - __R uint8_t FWD_RX_ERR_CNT[4]; /* 0x308 - 0x30B: Forwarded RX Error Counter */ - __R uint8_t ECAT_PU_ERR_CNT; /* 0x30C: ECAT Processing Unit Error Counter */ - __R uint8_t PDI_ERR_CNT; /* 0x30D: PDI Error Counter */ - __R uint8_t RESERVED18[2]; /* 0x30E - 0x30F: Reserved */ - __R uint8_t LOST_LINK_CNT[4]; /* 0x310 - 0x313: Lost Link Counter */ - __R uint8_t RESERVED19[236]; /* 0x314 - 0x3FF: Reserved */ - __R uint16_t WDG_DIV; /* 0x400: Watchdog Divider */ - __R uint8_t RESERVED20[14]; /* 0x402 - 0x40F: Reserved */ - __R uint16_t WDG_TIME_PDI; /* 0x410: Watchdog Time PDI */ - __R uint8_t RESERVED21[14]; /* 0x412 - 0x41F: Reserved */ - __R uint16_t WDG_TIME_PDAT; /* 0x420: Watchdog Time Process Data */ - __R uint8_t RESERVED22[30]; /* 0x422 - 0x43F: Reserved */ - __RW uint16_t WDG_STAT_PDAT; /* 0x440: Watchdog Status Process Data */ - __R uint8_t WDG_CNT_PDAT; /* 0x442: Watchdog Counter Process Data */ - __R uint8_t WDG_CNT_PDI; /* 0x443: Watchdog Counter PDI */ - __R uint8_t RESERVED23[188]; /* 0x444 - 0x4FF: Reserved */ - __R uint8_t EEPROM_CFG; /* 0x500: EEPROM Configuration */ - __RW uint8_t EEPROM_PDI_ACC_STAT; /* 0x501: EEPROM PDI Access State */ - __RW uint16_t EEPROM_CTRL_STAT; /* 0x502: EEPROM Control/Status */ - __RW uint32_t EEPROM_ADDR; /* 0x504: EEPROM Address */ - __RW uint64_t EEPROM_DATA; /* 0x508: EEPROM Data */ - __RW uint16_t MII_MNG_CS; /* 0x510: MII Management Control/Status */ - __RW uint8_t PHY_ADDR; /* 0x512: PHY Address */ - __RW uint8_t PHY_REG_ADDR; /* 0x513: PHY Register Address */ - __RW uint16_t PHY_DATA; /* 0x514: PHY Data */ - __R uint8_t MIIM_ECAT_ACC_STAT; /* 0x516: MII Management ECAT Access State */ - __RW uint8_t MIIM_PDI_ACC_STAT; /* 0x517: MII Management PDI Access State */ - __RW uint8_t PHY_STAT[4]; /* 0x518 - 0x51B: PHY Port */ - __R uint8_t RESERVED24[228]; /* 0x51C - 0x5FF: Reserved */ - struct { - __R uint32_t LOGIC_START_ADDR; /* 0x600: Logical Start Address */ - __R uint16_t LENGTH; /* 0x604: Length */ - __R uint8_t LOGIC_START_BIT; /* 0x606: Logical Start Bit */ - __R uint8_t LOGIC_STOP_BIT; /* 0x607: Logical Stop Bit */ - __R uint16_t PHYSICAL_START_ADDR; /* 0x608: Physical Start Address */ - __R uint8_t PHYSICAL_START_BIT; /* 0x60A: Physical Start Bit */ - __R uint8_t TYPE; /* 0x60B: Type */ - __R uint8_t ACTIVATE; /* 0x60C: Activate */ - __R uint8_t RESERVED0[3]; /* 0x60D - 0x60F: Reserved */ - } FMMU[8]; - __R uint8_t RESERVED25[384]; /* 0x680 - 0x7FF: Reserved */ - struct { - __R uint16_t PHYSICAL_START_ADDR; /* 0x800: Physical Start Address */ - __R uint16_t LENGTH; /* 0x802: Length */ - __R uint8_t CONTROL; /* 0x804: Control */ - __R uint8_t STATUS; /* 0x805: Status */ - __RW uint8_t ACTIVATE; /* 0x806: Activate */ - __RW uint8_t PDI_CTRL; /* 0x807: PDI Control */ - } SYNCM[8]; - __R uint8_t RESERVED26[192]; /* 0x840 - 0x8FF: Reserved */ - __R uint32_t RCV_TIME[4]; /* 0x900 - 0x90C: Receive Time */ - __RW uint64_t SYS_TIME; /* 0x910: System Time */ - __R uint64_t RCVT_ECAT_PU; /* 0x918: Receive Time ECAT Processing Unit */ - __RW uint64_t SYS_TIME_OFFSET; /* 0x920: System Time Offset */ - __RW uint32_t SYS_TIME_DELAY; /* 0x928: System Time Delay */ - __R uint32_t SYS_TIME_DIFF; /* 0x92C: System Time Difference */ - __RW uint16_t SPD_CNT_START; /* 0x930: Speed Counter Start */ - __R uint16_t SPD_CNT_DIFF; /* 0x932: Speed Counter Diff */ - __RW uint8_t SYS_TIME_DIFF_FD; /* 0x934: System Time Difference Filter Depth */ - __RW uint8_t SPD_CNT_FD; /* 0x935: Speed Counter Filter Depth */ - __R uint8_t RCV_TIME_LM; /* 0x936: Receive Time Latch Mode */ - __R uint8_t RESERVED27[73]; /* 0x937 - 0x97F: Reserved */ - __R uint8_t CYC_UNIT_CTRL; /* 0x980: Cyclic Unit Control */ - __RW uint8_t SYNCO_ACT; /* 0x981: SYNC Out Unit Activation */ - __R uint16_t PULSE_LEN; /* 0x982: Pulse Length of SyncSignals */ - __R uint8_t ACT_STAT; /* 0x984: Activation Status */ - __R uint8_t RESERVED28[9]; /* 0x985 - 0x98D: Reserved */ - __RW uint8_t SYNC0_STAT; /* 0x98E: SYNC0 Status */ - __RW uint8_t SYNC1_STAT; /* 0x98F: SYNC1 Status */ - __RW uint64_t START_TIME_CO; /* 0x990: Start Time Cyclic Operation */ - __R uint64_t NXT_SYNC1_PULSE; /* 0x998: Next SYNC1 Pulse */ - __RW uint32_t SYNC0_CYC_TIME; /* 0x9A0: SYNC0 Cycle Time */ - __RW uint32_t SYNC1_CYC_TIME; /* 0x9A4: SYNC1 Cycle Time */ - __RW uint8_t LATCH0_CTRL; /* 0x9A8: Latch0 Control */ - __RW uint8_t LATCH1_CTRL; /* 0x9A9: Latch1 Control */ - __R uint8_t RESERVED29[4]; /* 0x9AA - 0x9AD: Reserved */ - __R uint8_t LATCH0_STAT; /* 0x9AE: Latch0 Status */ - __R uint8_t LATCH1_STAT; /* 0x9AF: Latch1 Status */ - __RW uint64_t LATCH0_TIME_PE; /* 0x9B0: Latch0 Time Positive Edge */ - __RW uint64_t LATCH0_TIME_NE; /* 0x9B8: Latch0 Time Negative Edge */ - __RW uint64_t LATCH1_TIME_PE; /* 0x9C0: Latch1 Time Positive Edge */ - __RW uint64_t LATCH1_TIME_NE; /* 0x9C8: Latch1 Time Negative Edge */ - __R uint8_t RESERVED30[32]; /* 0x9D0 - 0x9EF: Reserved */ - __R uint32_t ECAT_BUF_CET; /* 0x9F0: EtherCAT Buffer Change Event Time */ - __R uint8_t RESERVED31[4]; /* 0x9F4 - 0x9F7: Reserved */ - __R uint32_t PDI_BUF_SET; /* 0x9F8: PDI Buffer Start Event Time */ - __R uint32_t PDI_BUF_CET; /* 0x9FC: PDI Buffer Change Event Time */ - __R uint8_t RESERVED32[1024]; /* 0xA00 - 0xDFF: Reserved */ - __R uint64_t PID; /* 0xE00: Product ID */ - __R uint64_t VID; /* 0xE08: Vendor ID */ - __R uint8_t RESERVED33[240]; /* 0xE10 - 0xEFF: Reserved */ - __R uint32_t DIO_OUT_DATA; /* 0xF00: Digital I/O Output Data */ - __R uint8_t RESERVED34[12]; /* 0xF04 - 0xF0F: Reserved */ - __RW uint64_t GPO; /* 0xF10: General Purpose Outputs */ - __R uint64_t GPI; /* 0xF18: General Purpose Inputs */ - __R uint8_t RESERVED35[96]; /* 0xF20 - 0xF7F: Reserved */ - __RW uint8_t USER_RAM_BYTE0; /* 0xF80: User Ram Byte 0 */ - __RW uint8_t USER_RAM_BYTE1; /* 0xF81: User Ram Byte 1 */ - __RW uint8_t USER_RAM_BYTE2; /* 0xF82: User Ram Byte 2 */ - __RW uint8_t USER_RAM_BYTE3; /* 0xF83: User Ram Byte 3 */ - __RW uint8_t USER_RAM_BYTE4; /* 0xF84: User Ram Byte 4 */ - __RW uint8_t USER_RAM_BYTE5; /* 0xF85: User Ram Byte 5 */ - __RW uint8_t USER_RAM_BYTE6; /* 0xF86: User Ram Byte 6 */ - __RW uint8_t USER_RAM_BYTE7; /* 0xF87: User Ram Byte 7 */ - __RW uint8_t USER_RAM_BYTE8; /* 0xF88: User Ram Byte 8 */ - __RW uint8_t USER_RAM_BYTE9; /* 0xF89: User Ram Byte 9 */ - __RW uint8_t USER_RAM_BYTE10; /* 0xF8A: User Ram Byte 10 */ - __RW uint8_t USER_RAM_BYTE11; /* 0xF8B: User Ram Byte 11 */ - __R uint8_t RESERVED36[2]; /* 0xF8C - 0xF8D: Reserved */ - __RW uint8_t USER_RAM_BYTE14; /* 0xF8E: User Ram Byte 14 */ - __RW uint8_t USER_RAM_BYTE15; /* 0xF8F: User Ram Byte 15 */ - __R uint8_t RESERVED37[3]; /* 0xF90 - 0xF92: Reserved */ - __RW uint8_t USER_RAM_BYTE19; /* 0xF93: User Ram Byte 19 */ - __R uint8_t RESERVED38[108]; /* 0xF94 - 0xFFF: Reserved */ - __RW uint32_t PDRAM; /* 0x1000: Process Data Ram */ - __R uint8_t RESERVED39[61436]; /* 0x1004 - 0xFFFF: Reserved */ - __RW uint32_t PDRAM_ALS; /* 0x10000: Process Data Ram Alias */ - __R uint8_t RESERVED40[61436]; /* 0x10004 - 0x1EFFF: Reserved */ - __RW uint32_t GPR_CFG0; /* 0x1F000: General Purpose Configure 0 */ - __RW uint32_t GPR_CFG1; /* 0x1F004: General Purpose Configure 1 */ - __RW uint32_t GPR_CFG2; /* 0x1F008: General Purpose Configure 2 */ - __R uint8_t RESERVED41[4]; /* 0x1F00C - 0x1F00F: Reserved */ - __RW uint32_t PHY_CFG0; /* 0x1F010: PHY Configure 0 */ - __RW uint32_t PHY_CFG1; /* 0x1F014: PHY Configure 1 */ - __R uint8_t RESERVED42[8]; /* 0x1F018 - 0x1F01F: Reserved */ - __RW uint32_t GPIO_CTRL; /* 0x1F020: GPIO Output Enable */ - __R uint8_t RESERVED43[12]; /* 0x1F024 - 0x1F02F: Reserved */ - __RW uint32_t GPI_OVERRIDE0; /* 0x1F030: GPI low word Override value */ - __RW uint32_t GPI_OVERRIDE1; /* 0x1F034: GPI high word Override value */ - __R uint32_t GPO_REG0; /* 0x1F038: GPO low word read value */ - __R uint32_t GPO_REG1; /* 0x1F03C: GPO high word read value */ - __R uint32_t GPI_REG0; /* 0x1F040: GPI low word read value */ - __R uint32_t GPI_REG1; /* 0x1F044: GPI high word read value */ - __R uint8_t RESERVED44[24]; /* 0x1F048 - 0x1F05F: Reserved */ - __R uint32_t GPR_STATUS; /* 0x1F060: global status register */ - __R uint8_t RESERVED45[28]; /* 0x1F064 - 0x1F07F: Reserved */ - __RW uint32_t IO_CFG[9]; /* 0x1F080 - 0x1F0A0: CTR IO Configure */ -} ESC_Type; - - -/* Bitfield definition for register: TYPE */ -/* - * TYPE (RO) - * - * Controller type - */ -#define ESC_TYPE_TYPE_MASK (0xFFU) -#define ESC_TYPE_TYPE_SHIFT (0U) -#define ESC_TYPE_TYPE_GET(x) (((uint8_t)(x) & ESC_TYPE_TYPE_MASK) >> ESC_TYPE_TYPE_SHIFT) - -/* Bitfield definition for register: REVISION */ -/* - * X (RO) - * - * major version X - */ -#define ESC_REVISION_X_MASK (0xFFU) -#define ESC_REVISION_X_SHIFT (0U) -#define ESC_REVISION_X_GET(x) (((uint8_t)(x) & ESC_REVISION_X_MASK) >> ESC_REVISION_X_SHIFT) - -/* Bitfield definition for register: BUILD */ -/* - * BUILD (RO) - * - */ -#define ESC_BUILD_BUILD_MASK (0xFF00U) -#define ESC_BUILD_BUILD_SHIFT (8U) -#define ESC_BUILD_BUILD_GET(x) (((uint16_t)(x) & ESC_BUILD_BUILD_MASK) >> ESC_BUILD_BUILD_SHIFT) - -/* - * Y (RO) - * - * minor version Y - */ -#define ESC_BUILD_Y_MASK (0xF0U) -#define ESC_BUILD_Y_SHIFT (4U) -#define ESC_BUILD_Y_GET(x) (((uint16_t)(x) & ESC_BUILD_Y_MASK) >> ESC_BUILD_Y_SHIFT) - -/* - * Z (RO) - * - * maintenance version Z - */ -#define ESC_BUILD_Z_MASK (0xFU) -#define ESC_BUILD_Z_SHIFT (0U) -#define ESC_BUILD_Z_GET(x) (((uint16_t)(x) & ESC_BUILD_Z_MASK) >> ESC_BUILD_Z_SHIFT) - -/* Bitfield definition for register: FMMU_NUM */ -/* - * NUM (RO) - * - * Number of supported FMMU channels (or entities) - */ -#define ESC_FMMU_NUM_NUM_MASK (0xFFU) -#define ESC_FMMU_NUM_NUM_SHIFT (0U) -#define ESC_FMMU_NUM_NUM_GET(x) (((uint8_t)(x) & ESC_FMMU_NUM_NUM_MASK) >> ESC_FMMU_NUM_NUM_SHIFT) - -/* Bitfield definition for register: SYNCM_NUM */ -/* - * NUM (RO) - * - * Number of supported SyncManager channels (or entities) - */ -#define ESC_SYNCM_NUM_NUM_MASK (0xFFU) -#define ESC_SYNCM_NUM_NUM_SHIFT (0U) -#define ESC_SYNCM_NUM_NUM_GET(x) (((uint8_t)(x) & ESC_SYNCM_NUM_NUM_MASK) >> ESC_SYNCM_NUM_NUM_SHIFT) - -/* Bitfield definition for register: RAM_SIZE */ -/* - * SIZE (RO) - * - * Process Data RAM size supported in KByte - */ -#define ESC_RAM_SIZE_SIZE_MASK (0xFFU) -#define ESC_RAM_SIZE_SIZE_SHIFT (0U) -#define ESC_RAM_SIZE_SIZE_GET(x) (((uint8_t)(x) & ESC_RAM_SIZE_SIZE_MASK) >> ESC_RAM_SIZE_SIZE_SHIFT) - -/* Bitfield definition for register: PORT_DESC */ -/* - * PORT3 (RO) - * - * Port configuration: - * 00:Not implemented - * 01:Not configured (SII EEPROM) - * 10:EBUS - * 11:MII/RMII/RGMII - */ -#define ESC_PORT_DESC_PORT3_MASK (0xC0U) -#define ESC_PORT_DESC_PORT3_SHIFT (6U) -#define ESC_PORT_DESC_PORT3_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT3_MASK) >> ESC_PORT_DESC_PORT3_SHIFT) - -/* - * PORT2 (RO) - * - * Port configuration: - * 00:Not implemented - * 01:Not configured (SII EEPROM) - * 10:EBUS - * 11:MII/RMII/RGMII - */ -#define ESC_PORT_DESC_PORT2_MASK (0x30U) -#define ESC_PORT_DESC_PORT2_SHIFT (4U) -#define ESC_PORT_DESC_PORT2_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT2_MASK) >> ESC_PORT_DESC_PORT2_SHIFT) - -/* - * PORT1 (RO) - * - * Port configuration: - * 00:Not implemented - * 01:Not configured (SII EEPROM) - * 10:EBUS - * 11:MII/RMII/RGMII - */ -#define ESC_PORT_DESC_PORT1_MASK (0xCU) -#define ESC_PORT_DESC_PORT1_SHIFT (2U) -#define ESC_PORT_DESC_PORT1_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT1_MASK) >> ESC_PORT_DESC_PORT1_SHIFT) - -/* - * PORT0 (RO) - * - * Port configuration: - * 00:Not implemented - * 01:Not configured (SII EEPROM) - * 10:EBUS - * 11:MII/RMII/RGMII - */ -#define ESC_PORT_DESC_PORT0_MASK (0x3U) -#define ESC_PORT_DESC_PORT0_SHIFT (0U) -#define ESC_PORT_DESC_PORT0_GET(x) (((uint8_t)(x) & ESC_PORT_DESC_PORT0_MASK) >> ESC_PORT_DESC_PORT0_SHIFT) - -/* Bitfield definition for register: FEATURE */ -/* - * FFSC (RO) - * - * Fixed FMMU/SyncManager configuration: - * 0:Variable configuration - * 1:Fixed configuration (refer to documentation of supporting ESCs) - */ -#define ESC_FEATURE_FFSC_MASK (0x800U) -#define ESC_FEATURE_FFSC_SHIFT (11U) -#define ESC_FEATURE_FFSC_GET(x) (((uint16_t)(x) & ESC_FEATURE_FFSC_MASK) >> ESC_FEATURE_FFSC_SHIFT) - -/* - * RWC (RO) - * - * EtherCAT read/write command support(BRW,APRW,FPRW): - * 0:Supported - * 1:Not supported - */ -#define ESC_FEATURE_RWC_MASK (0x400U) -#define ESC_FEATURE_RWC_SHIFT (10U) -#define ESC_FEATURE_RWC_GET(x) (((uint16_t)(x) & ESC_FEATURE_RWC_MASK) >> ESC_FEATURE_RWC_SHIFT) - -/* - * LRW (RO) - * - * EtherCAT LRW command support: - * 0:Supported - * 1:Not supported - */ -#define ESC_FEATURE_LRW_MASK (0x200U) -#define ESC_FEATURE_LRW_SHIFT (9U) -#define ESC_FEATURE_LRW_GET(x) (((uint16_t)(x) & ESC_FEATURE_LRW_MASK) >> ESC_FEATURE_LRW_SHIFT) - -/* - * EDSA (RO) - * - * Enhanced DC SYNC Activation: - * 0:Not available - * 1:Available - * Note:This feature refers to registers 0x981[7:3] and 0x0984 - */ -#define ESC_FEATURE_EDSA_MASK (0x100U) -#define ESC_FEATURE_EDSA_SHIFT (8U) -#define ESC_FEATURE_EDSA_GET(x) (((uint16_t)(x) & ESC_FEATURE_EDSA_MASK) >> ESC_FEATURE_EDSA_SHIFT) - -/* - * SHFE (RO) - * - * Seperate Handling of FCS Errors: - * 0:Not supported - * 1:Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter - */ -#define ESC_FEATURE_SHFE_MASK (0x80U) -#define ESC_FEATURE_SHFE_SHIFT (7U) -#define ESC_FEATURE_SHFE_GET(x) (((uint16_t)(x) & ESC_FEATURE_SHFE_MASK) >> ESC_FEATURE_SHFE_SHIFT) - -/* - * ELDM (RO) - * - * Enhanced Link Detection MII: - * 0:Not available - * 1:Available - */ -#define ESC_FEATURE_ELDM_MASK (0x40U) -#define ESC_FEATURE_ELDM_SHIFT (6U) -#define ESC_FEATURE_ELDM_GET(x) (((uint16_t)(x) & ESC_FEATURE_ELDM_MASK) >> ESC_FEATURE_ELDM_SHIFT) - -/* - * DCW (RO) - * - * Distributed Clocks width: - * 0:32 bit - * 1:64 bit - */ -#define ESC_FEATURE_DCW_MASK (0x8U) -#define ESC_FEATURE_DCW_SHIFT (3U) -#define ESC_FEATURE_DCW_GET(x) (((uint16_t)(x) & ESC_FEATURE_DCW_MASK) >> ESC_FEATURE_DCW_SHIFT) - -/* - * DC (RO) - * - * Distributed Clocks: - * 0:Not available - * 1:Available - */ -#define ESC_FEATURE_DC_MASK (0x4U) -#define ESC_FEATURE_DC_SHIFT (2U) -#define ESC_FEATURE_DC_GET(x) (((uint16_t)(x) & ESC_FEATURE_DC_MASK) >> ESC_FEATURE_DC_SHIFT) - -/* - * FMMU (RO) - * - * FMMU Operation: - * 0:Bit oriented - * 1:Byte oriented - */ -#define ESC_FEATURE_FMMU_MASK (0x1U) -#define ESC_FEATURE_FMMU_SHIFT (0U) -#define ESC_FEATURE_FMMU_GET(x) (((uint16_t)(x) & ESC_FEATURE_FMMU_MASK) >> ESC_FEATURE_FMMU_SHIFT) - -/* Bitfield definition for register: STATION_ADDR */ -/* - * ADDR (RO) - * - * Address used for node addressing - * (FPRD/FPWR/FPRW/FRMW commands) - */ -#define ESC_STATION_ADDR_ADDR_MASK (0xFFFFU) -#define ESC_STATION_ADDR_ADDR_SHIFT (0U) -#define ESC_STATION_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_STATION_ADDR_ADDR_MASK) >> ESC_STATION_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: STATION_ALS */ -/* - * ADDR (RW) - * - * Alias Address used for node addressing - * (FPRD/FPWR/FPRW/FRMW commands). - * The use of this alias is activated by Register - * DL Control Bit 0x0100[24]. - * NOTE:EEPROM value is only transferred into this - * register at first EEPROM load after power-on or - * reset. - * ESC20 exception:EEPROM value is transferred - * into this register after each EEPROM reload - * command. - */ -#define ESC_STATION_ALS_ADDR_MASK (0xFFFFU) -#define ESC_STATION_ALS_ADDR_SHIFT (0U) -#define ESC_STATION_ALS_ADDR_SET(x) (((uint16_t)(x) << ESC_STATION_ALS_ADDR_SHIFT) & ESC_STATION_ALS_ADDR_MASK) -#define ESC_STATION_ALS_ADDR_GET(x) (((uint16_t)(x) & ESC_STATION_ALS_ADDR_MASK) >> ESC_STATION_ALS_ADDR_SHIFT) - -/* Bitfield definition for register: REG_WEN */ -/* - * EN (RO) - * - * If register write protection is enabled, this - * register has to be written in the same - * Ethernet frame (value does not matter) - * before other writes to this station are allowed. - * This bit is self-clearing at the beginning of the - * next frame (SOF), or if Register Write - * Protection is disabled. - */ -#define ESC_REG_WEN_EN_MASK (0x1U) -#define ESC_REG_WEN_EN_SHIFT (0U) -#define ESC_REG_WEN_EN_GET(x) (((uint8_t)(x) & ESC_REG_WEN_EN_MASK) >> ESC_REG_WEN_EN_SHIFT) - -/* Bitfield definition for register: REG_WP */ -/* - * WP (RO) - * - * Register write protection: - * 0:Protection disabled - * 1:Protection enabled - * Registers 0x0000:0x0F7F are write-protected, - * except for 0x0020 and 0x0030 - */ -#define ESC_REG_WP_WP_MASK (0x1U) -#define ESC_REG_WP_WP_SHIFT (0U) -#define ESC_REG_WP_WP_GET(x) (((uint8_t)(x) & ESC_REG_WP_WP_MASK) >> ESC_REG_WP_WP_SHIFT) - -/* Bitfield definition for register: ESC_WEN */ -/* - * EN (RO) - * - * If ESC write protection is enabled, this - * register has to be written in the same - * Ethernet frame (value does not matter) - * before other writes to this station are allowed. - * This bit is self-clearing at the beginning of the - * next frame (SOF), or if ESC Write Protection - * is disabled. - */ -#define ESC_ESC_WEN_EN_MASK (0x1U) -#define ESC_ESC_WEN_EN_SHIFT (0U) -#define ESC_ESC_WEN_EN_GET(x) (((uint8_t)(x) & ESC_ESC_WEN_EN_MASK) >> ESC_ESC_WEN_EN_SHIFT) - -/* Bitfield definition for register: ESC_WP */ -/* - * WP (RO) - * - * Write protect: - * 0:Protection disabled - * 1:Protection enabled - * All areas are write-protected, except for 0x0030. - */ -#define ESC_ESC_WP_WP_MASK (0x1U) -#define ESC_ESC_WP_WP_SHIFT (0U) -#define ESC_ESC_WP_WP_GET(x) (((uint8_t)(x) & ESC_ESC_WP_WP_MASK) >> ESC_ESC_WP_WP_SHIFT) - -/* Bitfield definition for register: ESC_RST_ECAT */ -/* - * PR (RO) - * - * Progress of the reset procedure: - * 00:initial/reset state - * 01:after writing 0x52 ('R'), when previous - * state was 00 - * 10:after writing 0x45 ('E'), when previous - * state was 01 - * 11:after writing 0x53 ('S'), when previous - * state was 10. - * This value must not be observed - * because the ESC enters reset when this - * state is reached, resulting in state 00 - */ -#define ESC_ESC_RST_ECAT_PR_MASK (0x3U) -#define ESC_ESC_RST_ECAT_PR_SHIFT (0U) -#define ESC_ESC_RST_ECAT_PR_GET(x) (((uint8_t)(x) & ESC_ESC_RST_ECAT_PR_MASK) >> ESC_ESC_RST_ECAT_PR_SHIFT) - -/* Bitfield definition for register: ESC_RST_PDI */ -/* - * RST (RW) - * - * A reset is asserted after writing the reset - * sequence 0x52 ('R'), 0x45 ('E') and 0x53 ('S') - * in this register with 3 consecutive commands. - * Any other command which does not continue - * the sequence by writing the next expected - * value will cancel the reset procedure - */ -#define ESC_ESC_RST_PDI_RST_MASK (0xFFU) -#define ESC_ESC_RST_PDI_RST_SHIFT (0U) -#define ESC_ESC_RST_PDI_RST_SET(x) (((uint8_t)(x) << ESC_ESC_RST_PDI_RST_SHIFT) & ESC_ESC_RST_PDI_RST_MASK) -#define ESC_ESC_RST_PDI_RST_GET(x) (((uint8_t)(x) & ESC_ESC_RST_PDI_RST_MASK) >> ESC_ESC_RST_PDI_RST_SHIFT) - -/* Bitfield definition for register: ESC_DL_CTRL */ -/* - * SA (RO) - * - * Station alias: - * 0:Ignore Station Alias - * 1:Alias can be used for all configured - * address comm - */ -#define ESC_ESC_DL_CTRL_SA_MASK (0x1000000UL) -#define ESC_ESC_DL_CTRL_SA_SHIFT (24U) -#define ESC_ESC_DL_CTRL_SA_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_SA_MASK) >> ESC_ESC_DL_CTRL_SA_SHIFT) - -/* - * RFS (RO) - * - * RX FIFO Size (ESC delays start of - * forwarding until FIFO is at least half full). - * RX FIFO Size/RX delay reduction** : - * Value:EBUS:MII: - * 0:-50 ns -40 ns (-80 ns***) - * 1:-40 ns -40 ns (-80 ns***) - * 2:-30 ns -40 ns - * 3:-20 ns -40 ns - * 4:-10 ns no change - * 5:no change no change - * 6:no change no change - * 7:default default - * NOTE:EEPROM value is only taken over at first - * EEPROM load after power-on or reset - */ -#define ESC_ESC_DL_CTRL_RFS_MASK (0x70000UL) -#define ESC_ESC_DL_CTRL_RFS_SHIFT (16U) -#define ESC_ESC_DL_CTRL_RFS_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_RFS_MASK) >> ESC_ESC_DL_CTRL_RFS_SHIFT) - -/* - * LP3 (RO) - * - * Loop Port 3: - * 00:Auto - * 01:Auto Close - * 10:Open - * 11:Closed - */ -#define ESC_ESC_DL_CTRL_LP3_MASK (0xC000U) -#define ESC_ESC_DL_CTRL_LP3_SHIFT (14U) -#define ESC_ESC_DL_CTRL_LP3_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP3_MASK) >> ESC_ESC_DL_CTRL_LP3_SHIFT) - -/* - * LP2 (RO) - * - * Loop Port 2: - * 00:Auto - * 01:Auto Close - * 10:Open - * 11:Closed - */ -#define ESC_ESC_DL_CTRL_LP2_MASK (0x3000U) -#define ESC_ESC_DL_CTRL_LP2_SHIFT (12U) -#define ESC_ESC_DL_CTRL_LP2_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP2_MASK) >> ESC_ESC_DL_CTRL_LP2_SHIFT) - -/* - * LP1 (RO) - * - * Loop Port 1: - * 00:Auto - * 01:Auto Close - * 10:Open - * 11:Closed - */ -#define ESC_ESC_DL_CTRL_LP1_MASK (0xC00U) -#define ESC_ESC_DL_CTRL_LP1_SHIFT (10U) -#define ESC_ESC_DL_CTRL_LP1_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP1_MASK) >> ESC_ESC_DL_CTRL_LP1_SHIFT) - -/* - * LP0 (RO) - * - * Loop Port 0: - * 00:Auto - * 01:Auto Close - * 10:Open - * 11:Closed - * NOTE: - * Loop open means sending/receiving over this port - * is enabled, loop closed means sending/receiving - * is disabled and frames are forwarded to the next - * open port internally. - * Auto:loop closed at link down, opened at link up - * Auto Close:loop closed at link down, opened with - * writing 01 again after link up (or receiving a valid - * Ethernet frame at the closed port) - * Open:loop open regardless of link state - * Closed:loop closed regardless of link state - */ -#define ESC_ESC_DL_CTRL_LP0_MASK (0x300U) -#define ESC_ESC_DL_CTRL_LP0_SHIFT (8U) -#define ESC_ESC_DL_CTRL_LP0_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_LP0_MASK) >> ESC_ESC_DL_CTRL_LP0_SHIFT) - -/* - * TU (RO) - * - * Temporary use of settings in - * 0x0100:0x0103[8:15]: - * 0:permanent use - * 1:use for about 1 second, then revert to - * previous settings - */ -#define ESC_ESC_DL_CTRL_TU_MASK (0x2U) -#define ESC_ESC_DL_CTRL_TU_SHIFT (1U) -#define ESC_ESC_DL_CTRL_TU_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_TU_MASK) >> ESC_ESC_DL_CTRL_TU_SHIFT) - -/* - * FR (RO) - * - * Forwarding rule: - * 0:Forward non-EtherCAT frames: - * EtherCAT frames are processed, - * non-EtherCAT frames are forwarded - * without processing or modification. - * The source MAC address is not - * changed for any frame. - * 1:Destroy non-EtherCAT frames: - * EtherCAT frames are processed, non-EtherCAT frames are destroyed. - * The source MAC address is changed by - * the Processing Unit for every frame - * (SOURCE_MAC[1] is set - */ -#define ESC_ESC_DL_CTRL_FR_MASK (0x1U) -#define ESC_ESC_DL_CTRL_FR_SHIFT (0U) -#define ESC_ESC_DL_CTRL_FR_GET(x) (((uint32_t)(x) & ESC_ESC_DL_CTRL_FR_MASK) >> ESC_ESC_DL_CTRL_FR_SHIFT) - -/* Bitfield definition for register: PHYSICAL_RW_OFFSET */ -/* - * OFFSET (RO) - * - * This register is used for ReadWrite - * commands in Device Addressing mode - * (FPRW, APRW, BRW). - * The internal read address is directly taken - * from the offset address field of the EtherCAT - * datagram header, while the internal write - * address is calculated by adding the Physical - * Read/Write Offset value to the offset address - * field. - * Internal read address = ADR, - * internal write address = ADR + R/W-Offset - */ -#define ESC_PHYSICAL_RW_OFFSET_OFFSET_MASK (0xFFFFU) -#define ESC_PHYSICAL_RW_OFFSET_OFFSET_SHIFT (0U) -#define ESC_PHYSICAL_RW_OFFSET_OFFSET_GET(x) (((uint16_t)(x) & ESC_PHYSICAL_RW_OFFSET_OFFSET_MASK) >> ESC_PHYSICAL_RW_OFFSET_OFFSET_SHIFT) - -/* Bitfield definition for register: ESC_DL_STAT */ -/* - * CP3 (RO) - * - * Communication on Port 3: - * 0:No stable communication - * 1:Communication established - */ -#define ESC_ESC_DL_STAT_CP3_MASK (0x8000U) -#define ESC_ESC_DL_STAT_CP3_SHIFT (15U) -#define ESC_ESC_DL_STAT_CP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP3_MASK) >> ESC_ESC_DL_STAT_CP3_SHIFT) - -/* - * LP3 (RO) - * - * Loop Port 3: - * 0:Open - * 1:Closed - */ -#define ESC_ESC_DL_STAT_LP3_MASK (0x4000U) -#define ESC_ESC_DL_STAT_LP3_SHIFT (14U) -#define ESC_ESC_DL_STAT_LP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP3_MASK) >> ESC_ESC_DL_STAT_LP3_SHIFT) - -/* - * CP2 (RO) - * - * Communication on Port 2: - * 0:No stable communication - * 1:Communication established - */ -#define ESC_ESC_DL_STAT_CP2_MASK (0x2000U) -#define ESC_ESC_DL_STAT_CP2_SHIFT (13U) -#define ESC_ESC_DL_STAT_CP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP2_MASK) >> ESC_ESC_DL_STAT_CP2_SHIFT) - -/* - * LP2 (RO) - * - * Loop Port 2: - * 0:Open - * 1:Closed - */ -#define ESC_ESC_DL_STAT_LP2_MASK (0x1000U) -#define ESC_ESC_DL_STAT_LP2_SHIFT (12U) -#define ESC_ESC_DL_STAT_LP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP2_MASK) >> ESC_ESC_DL_STAT_LP2_SHIFT) - -/* - * CP1 (RO) - * - * Communication on Port 1: - * 0:No stable communication - * 1:Communication established - */ -#define ESC_ESC_DL_STAT_CP1_MASK (0x800U) -#define ESC_ESC_DL_STAT_CP1_SHIFT (11U) -#define ESC_ESC_DL_STAT_CP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP1_MASK) >> ESC_ESC_DL_STAT_CP1_SHIFT) - -/* - * LP1 (RO) - * - * Loop Port 1: - * 0:Open - * 1:Closed - */ -#define ESC_ESC_DL_STAT_LP1_MASK (0x400U) -#define ESC_ESC_DL_STAT_LP1_SHIFT (10U) -#define ESC_ESC_DL_STAT_LP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP1_MASK) >> ESC_ESC_DL_STAT_LP1_SHIFT) - -/* - * CP0 (RO) - * - * Communication on Port 0: - * 0:No stable communication - * 1:Communication established - */ -#define ESC_ESC_DL_STAT_CP0_MASK (0x200U) -#define ESC_ESC_DL_STAT_CP0_SHIFT (9U) -#define ESC_ESC_DL_STAT_CP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_CP0_MASK) >> ESC_ESC_DL_STAT_CP0_SHIFT) - -/* - * LP0 (RO) - * - * Loop Port 0: - * 0:Open - * 1:Closed - */ -#define ESC_ESC_DL_STAT_LP0_MASK (0x100U) -#define ESC_ESC_DL_STAT_LP0_SHIFT (8U) -#define ESC_ESC_DL_STAT_LP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_LP0_MASK) >> ESC_ESC_DL_STAT_LP0_SHIFT) - -/* - * PLP3 (RO) - * - * Physical link on Port 3: - * 0:No link - * 1:Link detected - */ -#define ESC_ESC_DL_STAT_PLP3_MASK (0x80U) -#define ESC_ESC_DL_STAT_PLP3_SHIFT (7U) -#define ESC_ESC_DL_STAT_PLP3_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP3_MASK) >> ESC_ESC_DL_STAT_PLP3_SHIFT) - -/* - * PLP2 (RO) - * - * Physical link on Port 2: - * 0:No link - * 1:Link detected - */ -#define ESC_ESC_DL_STAT_PLP2_MASK (0x40U) -#define ESC_ESC_DL_STAT_PLP2_SHIFT (6U) -#define ESC_ESC_DL_STAT_PLP2_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP2_MASK) >> ESC_ESC_DL_STAT_PLP2_SHIFT) - -/* - * PLP1 (RO) - * - * Physical link on Port 1: - * 0:No link - * 1:Link detected - */ -#define ESC_ESC_DL_STAT_PLP1_MASK (0x20U) -#define ESC_ESC_DL_STAT_PLP1_SHIFT (5U) -#define ESC_ESC_DL_STAT_PLP1_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP1_MASK) >> ESC_ESC_DL_STAT_PLP1_SHIFT) - -/* - * PLP0 (RO) - * - * Physical link on Port 0: - * 0:No link - * 1:Link detected - */ -#define ESC_ESC_DL_STAT_PLP0_MASK (0x10U) -#define ESC_ESC_DL_STAT_PLP0_SHIFT (4U) -#define ESC_ESC_DL_STAT_PLP0_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_PLP0_MASK) >> ESC_ESC_DL_STAT_PLP0_SHIFT) - -/* - * ELD (RO) - * - * Enhanced Link detection: - * 0:Deactivated for all ports - * 1:Activated for at least one port - * NOTE:EEPROM value is only transferred into this - * register at first EEPROM load after power-on or - * reset - */ -#define ESC_ESC_DL_STAT_ELD_MASK (0x4U) -#define ESC_ESC_DL_STAT_ELD_SHIFT (2U) -#define ESC_ESC_DL_STAT_ELD_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_ELD_MASK) >> ESC_ESC_DL_STAT_ELD_SHIFT) - -/* - * WDS (RO) - * - * PDI Watchdog Status: - * 0:Watchdog expired - * 1:Watchdog reloaded - */ -#define ESC_ESC_DL_STAT_WDS_MASK (0x2U) -#define ESC_ESC_DL_STAT_WDS_SHIFT (1U) -#define ESC_ESC_DL_STAT_WDS_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_WDS_MASK) >> ESC_ESC_DL_STAT_WDS_SHIFT) - -/* - * EPLC (RO) - * - * PDI operational/EEPROM loaded correctly: - * 0:EEPROM not loaded, PDI not - * operational (no access to Process Data - * RAM) - * 1:EEPROM loaded correctly, PDI - * operational (access to Process Data - * RAM) - */ -#define ESC_ESC_DL_STAT_EPLC_MASK (0x1U) -#define ESC_ESC_DL_STAT_EPLC_SHIFT (0U) -#define ESC_ESC_DL_STAT_EPLC_GET(x) (((uint16_t)(x) & ESC_ESC_DL_STAT_EPLC_MASK) >> ESC_ESC_DL_STAT_EPLC_SHIFT) - -/* Bitfield definition for register: AL_CTRL */ -/* - * DI (RW) - * - * Device Identification: - * 0:No request - * 1:Device Identification request - */ -#define ESC_AL_CTRL_DI_MASK (0x20U) -#define ESC_AL_CTRL_DI_SHIFT (5U) -#define ESC_AL_CTRL_DI_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_DI_SHIFT) & ESC_AL_CTRL_DI_MASK) -#define ESC_AL_CTRL_DI_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_DI_MASK) >> ESC_AL_CTRL_DI_SHIFT) - -/* - * EIA (RW) - * - * Error Ind Ack: - * 0:No Ack of Error Ind in AL status register - * 1:Ack of Error Ind in AL status register - */ -#define ESC_AL_CTRL_EIA_MASK (0x10U) -#define ESC_AL_CTRL_EIA_SHIFT (4U) -#define ESC_AL_CTRL_EIA_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_EIA_SHIFT) & ESC_AL_CTRL_EIA_MASK) -#define ESC_AL_CTRL_EIA_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_EIA_MASK) >> ESC_AL_CTRL_EIA_SHIFT) - -/* - * IST (RW) - * - * Initiate State Transition of the Device State - * Machine: - * 1:Request Init State - * 3:Request Bootstrap State - * 2:Request Pre-Operational State - * 4:Request Safe-Operational State - * 8:Request Operational State - */ -#define ESC_AL_CTRL_IST_MASK (0xFU) -#define ESC_AL_CTRL_IST_SHIFT (0U) -#define ESC_AL_CTRL_IST_SET(x) (((uint16_t)(x) << ESC_AL_CTRL_IST_SHIFT) & ESC_AL_CTRL_IST_MASK) -#define ESC_AL_CTRL_IST_GET(x) (((uint16_t)(x) & ESC_AL_CTRL_IST_MASK) >> ESC_AL_CTRL_IST_SHIFT) - -/* Bitfield definition for register: AL_STAT */ -/* - * DI (RW) - * - * Device Identification: - * 0:Device Identification not valid - * 1:Device Identification loaded - */ -#define ESC_AL_STAT_DI_MASK (0x20U) -#define ESC_AL_STAT_DI_SHIFT (5U) -#define ESC_AL_STAT_DI_SET(x) (((uint16_t)(x) << ESC_AL_STAT_DI_SHIFT) & ESC_AL_STAT_DI_MASK) -#define ESC_AL_STAT_DI_GET(x) (((uint16_t)(x) & ESC_AL_STAT_DI_MASK) >> ESC_AL_STAT_DI_SHIFT) - -/* - * EI (RW) - * - * Error Ind: - * 0:Device is in State as requested or Flag - * cleared by command - * 1:Device has not entered requested State - * or changed State as result of a local - * action - */ -#define ESC_AL_STAT_EI_MASK (0x10U) -#define ESC_AL_STAT_EI_SHIFT (4U) -#define ESC_AL_STAT_EI_SET(x) (((uint16_t)(x) << ESC_AL_STAT_EI_SHIFT) & ESC_AL_STAT_EI_MASK) -#define ESC_AL_STAT_EI_GET(x) (((uint16_t)(x) & ESC_AL_STAT_EI_MASK) >> ESC_AL_STAT_EI_SHIFT) - -/* - * AS (RW) - * - * Actual State of the Device State Machine: - * 1:Init State - * 3:Bootstrap State - * 2:Pre-Operational State - * 4:Safe-Operational State - * 8:Operational State - */ -#define ESC_AL_STAT_AS_MASK (0xFU) -#define ESC_AL_STAT_AS_SHIFT (0U) -#define ESC_AL_STAT_AS_SET(x) (((uint16_t)(x) << ESC_AL_STAT_AS_SHIFT) & ESC_AL_STAT_AS_MASK) -#define ESC_AL_STAT_AS_GET(x) (((uint16_t)(x) & ESC_AL_STAT_AS_MASK) >> ESC_AL_STAT_AS_SHIFT) - -/* Bitfield definition for register: AL_STAT_CODE */ -/* - * CODE (RW) - * - * AL Status Code - */ -#define ESC_AL_STAT_CODE_CODE_MASK (0xFFFFU) -#define ESC_AL_STAT_CODE_CODE_SHIFT (0U) -#define ESC_AL_STAT_CODE_CODE_SET(x) (((uint16_t)(x) << ESC_AL_STAT_CODE_CODE_SHIFT) & ESC_AL_STAT_CODE_CODE_MASK) -#define ESC_AL_STAT_CODE_CODE_GET(x) (((uint16_t)(x) & ESC_AL_STAT_CODE_CODE_MASK) >> ESC_AL_STAT_CODE_CODE_SHIFT) - -/* Bitfield definition for register: RUN_LED_OVRD */ -/* - * EN_OVRD (RW) - * - * Enable Override: - * 0:Override disabled - * 1:Override enabled - */ -#define ESC_RUN_LED_OVRD_EN_OVRD_MASK (0x10U) -#define ESC_RUN_LED_OVRD_EN_OVRD_SHIFT (4U) -#define ESC_RUN_LED_OVRD_EN_OVRD_SET(x) (((uint8_t)(x) << ESC_RUN_LED_OVRD_EN_OVRD_SHIFT) & ESC_RUN_LED_OVRD_EN_OVRD_MASK) -#define ESC_RUN_LED_OVRD_EN_OVRD_GET(x) (((uint8_t)(x) & ESC_RUN_LED_OVRD_EN_OVRD_MASK) >> ESC_RUN_LED_OVRD_EN_OVRD_SHIFT) - -/* - * LED_CODE (RW) - * - * LED code: - * 0x0:Off - * 0x1:Flash 1x - * 0x2-0xC:Flash 2x – 12x - * 0xD:Blinking - * 0xE:Flickering - * 0xF:On - */ -#define ESC_RUN_LED_OVRD_LED_CODE_MASK (0xFU) -#define ESC_RUN_LED_OVRD_LED_CODE_SHIFT (0U) -#define ESC_RUN_LED_OVRD_LED_CODE_SET(x) (((uint8_t)(x) << ESC_RUN_LED_OVRD_LED_CODE_SHIFT) & ESC_RUN_LED_OVRD_LED_CODE_MASK) -#define ESC_RUN_LED_OVRD_LED_CODE_GET(x) (((uint8_t)(x) & ESC_RUN_LED_OVRD_LED_CODE_MASK) >> ESC_RUN_LED_OVRD_LED_CODE_SHIFT) - -/* Bitfield definition for register: ERR_LED_OVRD */ -/* - * EN_OVRD (RW) - * - * Enable Override: - * 0:Override disabled - * 1:Override enabled - */ -#define ESC_ERR_LED_OVRD_EN_OVRD_MASK (0x10U) -#define ESC_ERR_LED_OVRD_EN_OVRD_SHIFT (4U) -#define ESC_ERR_LED_OVRD_EN_OVRD_SET(x) (((uint8_t)(x) << ESC_ERR_LED_OVRD_EN_OVRD_SHIFT) & ESC_ERR_LED_OVRD_EN_OVRD_MASK) -#define ESC_ERR_LED_OVRD_EN_OVRD_GET(x) (((uint8_t)(x) & ESC_ERR_LED_OVRD_EN_OVRD_MASK) >> ESC_ERR_LED_OVRD_EN_OVRD_SHIFT) - -/* - * LED_CODE (RW) - * - * LED code: - * 0x0:Off - * 0x1-0xC:Flash 1x – 12x - * 0xD:Blinking - * 0xE:Flickering - * 0xF:On - */ -#define ESC_ERR_LED_OVRD_LED_CODE_MASK (0xFU) -#define ESC_ERR_LED_OVRD_LED_CODE_SHIFT (0U) -#define ESC_ERR_LED_OVRD_LED_CODE_SET(x) (((uint8_t)(x) << ESC_ERR_LED_OVRD_LED_CODE_SHIFT) & ESC_ERR_LED_OVRD_LED_CODE_MASK) -#define ESC_ERR_LED_OVRD_LED_CODE_GET(x) (((uint8_t)(x) & ESC_ERR_LED_OVRD_LED_CODE_MASK) >> ESC_ERR_LED_OVRD_LED_CODE_SHIFT) - -/* Bitfield definition for register: PDI_CTRL */ -/* - * PDI (RO) - * - * Process data interface: - * 0x00:Interface deactivated (no PDI) - * 0x01:4 Digital Input - * 0x02:4 Digital Output - * 0x03:2 Digital Input and 2 Digital Output - * 0x04:Digital I/O - * 0x05:SPI Slave - * 0x06:Oversampling I/O - * 0x07:EtherCAT Bridge (port 3) - * 0x08:16 Bit asynchronous Microcontroller - * interface - * 0x09:8 Bit asynchronous Microcontroller - * interface - * 0x0A:16 Bit synchronous Microcontroller - * interface - * 0x0B:8 Bit synchronous Microcontroller - * interface - * 0x10:32 Digital Input and 0 Digital Output - * 0x11:24 Digital Input and 8 Digital Output - * 0x12:16 Digital Input and 16 Digital Output - * 0x13:8 Digital Input and 24 Digital Output - * 0x14:0 Digital Input and 32 Digital Output - * 0x80:On-chip bus - * Others:Reserved - */ -#define ESC_PDI_CTRL_PDI_MASK (0xFFU) -#define ESC_PDI_CTRL_PDI_SHIFT (0U) -#define ESC_PDI_CTRL_PDI_GET(x) (((uint8_t)(x) & ESC_PDI_CTRL_PDI_MASK) >> ESC_PDI_CTRL_PDI_SHIFT) - -/* Bitfield definition for register: ESC_CFG */ -/* - * ELP3 (RO) - * - * Enhanced Link port 3: - * 0:disabled (if bit 1=0) - * 1:enabled - */ -#define ESC_ESC_CFG_ELP3_MASK (0x80U) -#define ESC_ESC_CFG_ELP3_SHIFT (7U) -#define ESC_ESC_CFG_ELP3_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP3_MASK) >> ESC_ESC_CFG_ELP3_SHIFT) - -/* - * ELP2 (RO) - * - * Enhanced Link port 2: - * 0:disabled (if bit 1=0) - * 1:enabled - */ -#define ESC_ESC_CFG_ELP2_MASK (0x40U) -#define ESC_ESC_CFG_ELP2_SHIFT (6U) -#define ESC_ESC_CFG_ELP2_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP2_MASK) >> ESC_ESC_CFG_ELP2_SHIFT) - -/* - * ELP1 (RO) - * - * Enhanced Link port 1: - * 0:disabled (if bit 1=0) - * 1:enabled - */ -#define ESC_ESC_CFG_ELP1_MASK (0x20U) -#define ESC_ESC_CFG_ELP1_SHIFT (5U) -#define ESC_ESC_CFG_ELP1_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP1_MASK) >> ESC_ESC_CFG_ELP1_SHIFT) - -/* - * ELP0 (RO) - * - * Enhanced Link port 0: - * 0:disabled (if bit 1=0) - * 1:enabled - */ -#define ESC_ESC_CFG_ELP0_MASK (0x10U) -#define ESC_ESC_CFG_ELP0_SHIFT (4U) -#define ESC_ESC_CFG_ELP0_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELP0_MASK) >> ESC_ESC_CFG_ELP0_SHIFT) - -/* - * CDLIU (RO) - * - * Distributed Clocks Latch In Unit: - * 0:disabled (power saving) - * 1:enabled - */ -#define ESC_ESC_CFG_CDLIU_MASK (0x8U) -#define ESC_ESC_CFG_CDLIU_SHIFT (3U) -#define ESC_ESC_CFG_CDLIU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_CDLIU_MASK) >> ESC_ESC_CFG_CDLIU_SHIFT) - -/* - * DCSOU (RO) - * - * Distributed Clocks SYNC Out Unit: - * 0:disabled (power saving) - * 1:enabled - */ -#define ESC_ESC_CFG_DCSOU_MASK (0x4U) -#define ESC_ESC_CFG_DCSOU_SHIFT (2U) -#define ESC_ESC_CFG_DCSOU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_DCSOU_MASK) >> ESC_ESC_CFG_DCSOU_SHIFT) - -/* - * ELDAP (RO) - * - * Enhanced Link detection all ports: - * 0:disabled (if bits [7:4]=0) - * 1:enabled at all ports (overrides bits [7:4]) - */ -#define ESC_ESC_CFG_ELDAP_MASK (0x2U) -#define ESC_ESC_CFG_ELDAP_SHIFT (1U) -#define ESC_ESC_CFG_ELDAP_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_ELDAP_MASK) >> ESC_ESC_CFG_ELDAP_SHIFT) - -/* - * DEV_EMU (RO) - * - * Device emulation (control of AL status): - * 0:AL status register has to be set by PDI - * 1:AL status register will be set to value - * written to AL control register - */ -#define ESC_ESC_CFG_DEV_EMU_MASK (0x1U) -#define ESC_ESC_CFG_DEV_EMU_SHIFT (0U) -#define ESC_ESC_CFG_DEV_EMU_GET(x) (((uint8_t)(x) & ESC_ESC_CFG_DEV_EMU_MASK) >> ESC_ESC_CFG_DEV_EMU_SHIFT) - -/* Bitfield definition for register: PDI_INFO */ -/* - * PDICN (RO) - * - * PDI configuration invalid: - * 0:PDI configuration ok - * 1:PDI configuration invalid - */ -#define ESC_PDI_INFO_PDICN_MASK (0x8U) -#define ESC_PDI_INFO_PDICN_SHIFT (3U) -#define ESC_PDI_INFO_PDICN_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PDICN_MASK) >> ESC_PDI_INFO_PDICN_SHIFT) - -/* - * PDIA (RO) - * - * PDI active: - * 0:PDI not active - * 1:PDI active - */ -#define ESC_PDI_INFO_PDIA_MASK (0x4U) -#define ESC_PDI_INFO_PDIA_SHIFT (2U) -#define ESC_PDI_INFO_PDIA_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PDIA_MASK) >> ESC_PDI_INFO_PDIA_SHIFT) - -/* - * ECLFE (RO) - * - * ESC configuration area loaded from - * EEPROM: - * 0:not loaded - * 1:loaded - */ -#define ESC_PDI_INFO_ECLFE_MASK (0x2U) -#define ESC_PDI_INFO_ECLFE_SHIFT (1U) -#define ESC_PDI_INFO_ECLFE_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_ECLFE_MASK) >> ESC_PDI_INFO_ECLFE_SHIFT) - -/* - * PFABW (RO) - * - * DI function acknowledge by write: - * 0:Disabled - * 1:Enabled - */ -#define ESC_PDI_INFO_PFABW_MASK (0x1U) -#define ESC_PDI_INFO_PFABW_SHIFT (0U) -#define ESC_PDI_INFO_PFABW_GET(x) (((uint16_t)(x) & ESC_PDI_INFO_PFABW_MASK) >> ESC_PDI_INFO_PFABW_SHIFT) - -/* Bitfield definition for register: PDI_CFG */ -/* - * BUS (RO) - * - * On-chip bus: - * 000:Intel® Avalon® - * 001:AXI® - * 010:Xilinx® PLB v4.6 - * 100:Xilinx OPB - * others:reserved - */ -#define ESC_PDI_CFG_BUS_MASK (0xE0U) -#define ESC_PDI_CFG_BUS_SHIFT (5U) -#define ESC_PDI_CFG_BUS_GET(x) (((uint8_t)(x) & ESC_PDI_CFG_BUS_MASK) >> ESC_PDI_CFG_BUS_SHIFT) - -/* - * CLK (RO) - * - * On-chip bus clock: - * 0:asynchronous - * 1-31:synchronous multiplication factor - * (N * 25 MHz) - */ -#define ESC_PDI_CFG_CLK_MASK (0x1FU) -#define ESC_PDI_CFG_CLK_SHIFT (0U) -#define ESC_PDI_CFG_CLK_GET(x) (((uint8_t)(x) & ESC_PDI_CFG_CLK_MASK) >> ESC_PDI_CFG_CLK_SHIFT) - -/* Bitfield definition for register: PDI_SL_CFG */ -/* - * SYNC1_MAER (RO) - * - * SYNC1 mapped to AL Event Request - * register 0x0220[3]: - * 0:Disabled - * 1:Enabled - */ -#define ESC_PDI_SL_CFG_SYNC1_MAER_MASK (0x80U) -#define ESC_PDI_SL_CFG_SYNC1_MAER_SHIFT (7U) -#define ESC_PDI_SL_CFG_SYNC1_MAER_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_MAER_MASK) >> ESC_PDI_SL_CFG_SYNC1_MAER_SHIFT) - -/* - * SYNC1_CFG (RO) - * - * SYNC1/LATCH1 configuration*: - * 0:LATCH1 input - * 1:SYNC1 output - */ -#define ESC_PDI_SL_CFG_SYNC1_CFG_MASK (0x40U) -#define ESC_PDI_SL_CFG_SYNC1_CFG_SHIFT (6U) -#define ESC_PDI_SL_CFG_SYNC1_CFG_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_CFG_MASK) >> ESC_PDI_SL_CFG_SYNC1_CFG_SHIFT) - -/* - * SYNC1_ODP (RO) - * - * SYNC1 output driver/polarity: - * 00:Push-Pull active low - * 01:Open Drain (active low) - * 10:Push-Pull active high - * 11:Open Source (active high) - */ -#define ESC_PDI_SL_CFG_SYNC1_ODP_MASK (0x30U) -#define ESC_PDI_SL_CFG_SYNC1_ODP_SHIFT (4U) -#define ESC_PDI_SL_CFG_SYNC1_ODP_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC1_ODP_MASK) >> ESC_PDI_SL_CFG_SYNC1_ODP_SHIFT) - -/* - * SYNC0_MAER (RO) - * - * SYNC0 mapped to AL Event Request - * register 0x0220[2]: - * 0:Disabled - * 1:Enabled - */ -#define ESC_PDI_SL_CFG_SYNC0_MAER_MASK (0x8U) -#define ESC_PDI_SL_CFG_SYNC0_MAER_SHIFT (3U) -#define ESC_PDI_SL_CFG_SYNC0_MAER_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_MAER_MASK) >> ESC_PDI_SL_CFG_SYNC0_MAER_SHIFT) - -/* - * SYNC0_CFG (RO) - * - * SYNC0/LATCH0 configuration*: - * 0:LATCH0 Input - * 1:SYNC0 Output - */ -#define ESC_PDI_SL_CFG_SYNC0_CFG_MASK (0x4U) -#define ESC_PDI_SL_CFG_SYNC0_CFG_SHIFT (2U) -#define ESC_PDI_SL_CFG_SYNC0_CFG_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_CFG_MASK) >> ESC_PDI_SL_CFG_SYNC0_CFG_SHIFT) - -/* - * SYNC0_ODP (RO) - * - * SYNC0 output driver/polarity: - * 00:Push-Pull active low - * 01:Open Drain (active low) - * 10:Push-Pull active high - * 11:Open Source (active high) - */ -#define ESC_PDI_SL_CFG_SYNC0_ODP_MASK (0x3U) -#define ESC_PDI_SL_CFG_SYNC0_ODP_SHIFT (0U) -#define ESC_PDI_SL_CFG_SYNC0_ODP_GET(x) (((uint8_t)(x) & ESC_PDI_SL_CFG_SYNC0_ODP_MASK) >> ESC_PDI_SL_CFG_SYNC0_ODP_SHIFT) - -/* Bitfield definition for register: PDI_EXT_CFG */ -/* - * OCBST (RW) - * - * On-chip bus sub-type for AXI: - * 000:AXI3 - * 001:AXI4 - * 010:AXI4 LITE - * others:reserved - */ -#define ESC_PDI_EXT_CFG_OCBST_MASK (0x700U) -#define ESC_PDI_EXT_CFG_OCBST_SHIFT (8U) -#define ESC_PDI_EXT_CFG_OCBST_SET(x) (((uint16_t)(x) << ESC_PDI_EXT_CFG_OCBST_SHIFT) & ESC_PDI_EXT_CFG_OCBST_MASK) -#define ESC_PDI_EXT_CFG_OCBST_GET(x) (((uint16_t)(x) & ESC_PDI_EXT_CFG_OCBST_MASK) >> ESC_PDI_EXT_CFG_OCBST_SHIFT) - -/* - * RPS (RO) - * - * Read prefetch size (in cycles of PDI width): - * 0:4 cycles - * 1:1 cycle (typical) - * 2:2 cycles - * 3:Reserved - */ -#define ESC_PDI_EXT_CFG_RPS_MASK (0x3U) -#define ESC_PDI_EXT_CFG_RPS_SHIFT (0U) -#define ESC_PDI_EXT_CFG_RPS_GET(x) (((uint16_t)(x) & ESC_PDI_EXT_CFG_RPS_MASK) >> ESC_PDI_EXT_CFG_RPS_SHIFT) - -/* Bitfield definition for register: ECAT_EVT_MSK */ -/* - * MASK (RO) - * - * ECAT Event masking of the ECAT Event - * Request Events for mapping into ECAT event - * field of EtherCAT frames: - * 0:Corresponding ECAT Event Request - * register bit is not mapped - * 1:Corresponding ECAT Event Request - * register bit is mapped - */ -#define ESC_ECAT_EVT_MSK_MASK_MASK (0xFFFFU) -#define ESC_ECAT_EVT_MSK_MASK_SHIFT (0U) -#define ESC_ECAT_EVT_MSK_MASK_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_MSK_MASK_MASK) >> ESC_ECAT_EVT_MSK_MASK_SHIFT) - -/* Bitfield definition for register: PDI_AL_EVT_MSK */ -/* - * MASK (RW) - * - * AL Event masking of the AL Event Request - * register Events for mapping to PDI IRQ - * signal: - * 0:Corresponding AL Event Request - * register bit is not mapped - * 1:Corresponding AL Event Request - * register bit is mapped - */ -#define ESC_PDI_AL_EVT_MSK_MASK_MASK (0xFFFFFFFFUL) -#define ESC_PDI_AL_EVT_MSK_MASK_SHIFT (0U) -#define ESC_PDI_AL_EVT_MSK_MASK_SET(x) (((uint32_t)(x) << ESC_PDI_AL_EVT_MSK_MASK_SHIFT) & ESC_PDI_AL_EVT_MSK_MASK_MASK) -#define ESC_PDI_AL_EVT_MSK_MASK_GET(x) (((uint32_t)(x) & ESC_PDI_AL_EVT_MSK_MASK_MASK) >> ESC_PDI_AL_EVT_MSK_MASK_SHIFT) - -/* Bitfield definition for register: ECAT_EVT_REQ */ -/* - * MV (RO) - * - * Mirrors values of each SyncManager Status: - * 0:No Sync Channel 0 event - * 1:Sync Channel 0 event pending - * 0:No Sync Channel 1 event - * 1:Sync Channel 1 event pending - * … - * 0:No Sync Channel 7 event - * 1:Sync Channel 7 event pending - */ -#define ESC_ECAT_EVT_REQ_MV_MASK (0xFF0U) -#define ESC_ECAT_EVT_REQ_MV_SHIFT (4U) -#define ESC_ECAT_EVT_REQ_MV_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_MV_MASK) >> ESC_ECAT_EVT_REQ_MV_SHIFT) - -/* - * ALS_EVT (RO) - * - * AL Status event: - * 0:No change in AL Status - * 1:AL Status change - * (Bit is cleared by reading out AL Status - * 0x0130:0x0131 from ECAT) - */ -#define ESC_ECAT_EVT_REQ_ALS_EVT_MASK (0x8U) -#define ESC_ECAT_EVT_REQ_ALS_EVT_SHIFT (3U) -#define ESC_ECAT_EVT_REQ_ALS_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_ALS_EVT_MASK) >> ESC_ECAT_EVT_REQ_ALS_EVT_SHIFT) - -/* - * DLS_EVT (RO) - * - * DL Status event: - * 0:No change in DL Status - * 1:DL Status change - * (Bit is cleared by reading out DL Status - * 0x0110:0x0111 from ECAT) - */ -#define ESC_ECAT_EVT_REQ_DLS_EVT_MASK (0x4U) -#define ESC_ECAT_EVT_REQ_DLS_EVT_SHIFT (2U) -#define ESC_ECAT_EVT_REQ_DLS_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_DLS_EVT_MASK) >> ESC_ECAT_EVT_REQ_DLS_EVT_SHIFT) - -/* - * DCL_EVT (RO) - * - * DC Latch event: - * 0:No change on DC Latch Inputs - * 1:At least one change on DC Latch Inputs - * (Bit is cleared by reading DC Latch event - * times from ECAT for ECAT-controlled Latch - * Units, so that Latch 0/1 Status - * 0x09AE:0x09AF indicates no event) - */ -#define ESC_ECAT_EVT_REQ_DCL_EVT_MASK (0x1U) -#define ESC_ECAT_EVT_REQ_DCL_EVT_SHIFT (0U) -#define ESC_ECAT_EVT_REQ_DCL_EVT_GET(x) (((uint16_t)(x) & ESC_ECAT_EVT_REQ_DCL_EVT_MASK) >> ESC_ECAT_EVT_REQ_DCL_EVT_SHIFT) - -/* Bitfield definition for register: AL_EVT_REQ */ -/* - * SM_INT (RO) - * - * SyncManager interrupts (SyncManager - * register offset 0x5, bit [0] or [1]): - * 0:No SyncManager 0 interrupt - * 1:SyncManager 0 interrupt pending - * 0:No SyncManager 1 interrupt - * 1:SyncManager 1 interrupt pending - * … - * 0:No SyncManager 15 interrupt - * 1:SyncManager 15 interrupt pending - */ -#define ESC_AL_EVT_REQ_SM_INT_MASK (0xFFFF00UL) -#define ESC_AL_EVT_REQ_SM_INT_SHIFT (8U) -#define ESC_AL_EVT_REQ_SM_INT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_SM_INT_MASK) >> ESC_AL_EVT_REQ_SM_INT_SHIFT) - -/* - * WDG_PD (RO) - * - * Watchdog Process Data: - * 0:Has not expired - * 1:Has expired - * (Bit is cleared by reading Watchdog Status - * Process Data 0x0440 from PDI) - */ -#define ESC_AL_EVT_REQ_WDG_PD_MASK (0x40U) -#define ESC_AL_EVT_REQ_WDG_PD_SHIFT (6U) -#define ESC_AL_EVT_REQ_WDG_PD_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_WDG_PD_MASK) >> ESC_AL_EVT_REQ_WDG_PD_SHIFT) - -/* - * EE_EMU (RO) - * - * EEPROM Emulation: - * 0:No command pending - * 1:EEPROM command pending - * (Bit is cleared by acknowledging the - * command in EEPROM Control/Status - * register 0x0502:0x0503[10:8] from PDI) - */ -#define ESC_AL_EVT_REQ_EE_EMU_MASK (0x20U) -#define ESC_AL_EVT_REQ_EE_EMU_SHIFT (5U) -#define ESC_AL_EVT_REQ_EE_EMU_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_EE_EMU_MASK) >> ESC_AL_EVT_REQ_EE_EMU_SHIFT) - -/* - * SM_ACT (RO) - * - * SyncManager activation register - * (SyncManager register offset 0x6) changed: - * 0:No change in any SyncManager - * 1:At least one SyncManager changed - * (Bit is cleared by reading SyncManager - * Activation registers 0x0806 etc. from PDI) - */ -#define ESC_AL_EVT_REQ_SM_ACT_MASK (0x10U) -#define ESC_AL_EVT_REQ_SM_ACT_SHIFT (4U) -#define ESC_AL_EVT_REQ_SM_ACT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_SM_ACT_MASK) >> ESC_AL_EVT_REQ_SM_ACT_SHIFT) - -/* - * ST_DC_SYNC1 (RO) - * - * State of DC SYNC1 (if register - * 0x0151[7]=1): - * (Bit is cleared by reading of SYNC1 status - * 0x098F from PDI, use only in Acknowledge - * mode) - */ -#define ESC_AL_EVT_REQ_ST_DC_SYNC1_MASK (0x8U) -#define ESC_AL_EVT_REQ_ST_DC_SYNC1_SHIFT (3U) -#define ESC_AL_EVT_REQ_ST_DC_SYNC1_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ST_DC_SYNC1_MASK) >> ESC_AL_EVT_REQ_ST_DC_SYNC1_SHIFT) - -/* - * ST_DC_SYNC0 (RO) - * - * State of DC SYNC0 (if register - * 0x0151[3]=1): - * (Bit is cleared by reading SYNC0 status - * 0x098E from PDI, use only in Acknowledge - * mode) - */ -#define ESC_AL_EVT_REQ_ST_DC_SYNC0_MASK (0x4U) -#define ESC_AL_EVT_REQ_ST_DC_SYNC0_SHIFT (2U) -#define ESC_AL_EVT_REQ_ST_DC_SYNC0_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ST_DC_SYNC0_MASK) >> ESC_AL_EVT_REQ_ST_DC_SYNC0_SHIFT) - -/* - * DCL_EVT (RO) - * - * DC Latch event: - * 0:No change on DC Latch Inputs - * 1:At least one change on DC Latch Inputs - * (Bit is cleared by reading DC Latch event - * times from PDI, so that Latch 0/1 Status - * 0x09AE:0x09AF indicates no event. Available - * if Latch Unit is PDI-controlled) - */ -#define ESC_AL_EVT_REQ_DCL_EVT_MASK (0x2U) -#define ESC_AL_EVT_REQ_DCL_EVT_SHIFT (1U) -#define ESC_AL_EVT_REQ_DCL_EVT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_DCL_EVT_MASK) >> ESC_AL_EVT_REQ_DCL_EVT_SHIFT) - -/* - * ALC_EVT (RO) - * - * AL Control event: - * 0:No AL Control Register change - * 1:AL Control Register has been written3 - * (Bit is cleared by reading AL Control register - * 0x0120:0x0121 from PDI) - */ -#define ESC_AL_EVT_REQ_ALC_EVT_MASK (0x1U) -#define ESC_AL_EVT_REQ_ALC_EVT_SHIFT (0U) -#define ESC_AL_EVT_REQ_ALC_EVT_GET(x) (((uint32_t)(x) & ESC_AL_EVT_REQ_ALC_EVT_MASK) >> ESC_AL_EVT_REQ_ALC_EVT_SHIFT) - -/* Bitfield definition for register array: RX_ERR_CNT */ -/* - * RX_ERR (RO) - * - * RX Error counter of Port y (counting is - * stopped when 0xFF is reached). - */ -#define ESC_RX_ERR_CNT_RX_ERR_MASK (0xFF00U) -#define ESC_RX_ERR_CNT_RX_ERR_SHIFT (8U) -#define ESC_RX_ERR_CNT_RX_ERR_GET(x) (((uint16_t)(x) & ESC_RX_ERR_CNT_RX_ERR_MASK) >> ESC_RX_ERR_CNT_RX_ERR_SHIFT) - -/* - * IVD_FRM (RO) - * - * Invalid frame counter of Port y (counting is - * stopped when 0xFF is reached). - */ -#define ESC_RX_ERR_CNT_IVD_FRM_MASK (0xFFU) -#define ESC_RX_ERR_CNT_IVD_FRM_SHIFT (0U) -#define ESC_RX_ERR_CNT_IVD_FRM_GET(x) (((uint16_t)(x) & ESC_RX_ERR_CNT_IVD_FRM_MASK) >> ESC_RX_ERR_CNT_IVD_FRM_SHIFT) - -/* Bitfield definition for register array: FWD_RX_ERR_CNT */ -/* - * ERR_CNT (RO) - * - * Forwarded error counter of Port y (counting is - * stopped when 0xFF is reached). - */ -#define ESC_FWD_RX_ERR_CNT_ERR_CNT_MASK (0xFFU) -#define ESC_FWD_RX_ERR_CNT_ERR_CNT_SHIFT (0U) -#define ESC_FWD_RX_ERR_CNT_ERR_CNT_GET(x) (((uint8_t)(x) & ESC_FWD_RX_ERR_CNT_ERR_CNT_MASK) >> ESC_FWD_RX_ERR_CNT_ERR_CNT_SHIFT) - -/* Bitfield definition for register: ECAT_PU_ERR_CNT */ -/* - * CNT (RO) - * - * ECAT Processing Unit error counter - * (counting is stopped when 0xFF is reached). - * Counts errors of frames passing the - * Processing Unit. - */ -#define ESC_ECAT_PU_ERR_CNT_CNT_MASK (0xFFU) -#define ESC_ECAT_PU_ERR_CNT_CNT_SHIFT (0U) -#define ESC_ECAT_PU_ERR_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_ECAT_PU_ERR_CNT_CNT_MASK) >> ESC_ECAT_PU_ERR_CNT_CNT_SHIFT) - -/* Bitfield definition for register: PDI_ERR_CNT */ -/* - * CNT (RO) - * - * PDI Error counter (counting is stopped when - * 0xFF is reached). Counts if a PDI access has - * an interface error. - */ -#define ESC_PDI_ERR_CNT_CNT_MASK (0xFFU) -#define ESC_PDI_ERR_CNT_CNT_SHIFT (0U) -#define ESC_PDI_ERR_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_PDI_ERR_CNT_CNT_MASK) >> ESC_PDI_ERR_CNT_CNT_SHIFT) - -/* Bitfield definition for register array: LOST_LINK_CNT */ -/* - * CNT (RO) - * - * Lost Link counter of Port y (counting is - * stopped when 0xff is reached). Counts only if - * port is open and loop is Auto. - */ -#define ESC_LOST_LINK_CNT_CNT_MASK (0xFFU) -#define ESC_LOST_LINK_CNT_CNT_SHIFT (0U) -#define ESC_LOST_LINK_CNT_CNT_GET(x) (((uint8_t)(x) & ESC_LOST_LINK_CNT_CNT_MASK) >> ESC_LOST_LINK_CNT_CNT_SHIFT) - -/* Bitfield definition for register: WDG_DIV */ -/* - * DIV (RO) - * - * Watchdog divider:Number of 25 MHz tics - * (minus 2) that represent the basic watchdog - * increment. (Default value is 100µs = 2498) - */ -#define ESC_WDG_DIV_DIV_MASK (0xFFFFU) -#define ESC_WDG_DIV_DIV_SHIFT (0U) -#define ESC_WDG_DIV_DIV_GET(x) (((uint16_t)(x) & ESC_WDG_DIV_DIV_MASK) >> ESC_WDG_DIV_DIV_SHIFT) - -/* Bitfield definition for register: WDG_TIME_PDI */ -/* - * TIME (RO) - * - * Watchdog Time PDI:number of basic - * watchdog increments - * (Default value with Watchdog divider 100µs - * means 100ms Watchdog) - */ -#define ESC_WDG_TIME_PDI_TIME_MASK (0xFFFFU) -#define ESC_WDG_TIME_PDI_TIME_SHIFT (0U) -#define ESC_WDG_TIME_PDI_TIME_GET(x) (((uint16_t)(x) & ESC_WDG_TIME_PDI_TIME_MASK) >> ESC_WDG_TIME_PDI_TIME_SHIFT) - -/* Bitfield definition for register: WDG_TIME_PDAT */ -/* - * TIME (RO) - * - * Watchdog Time Process Data:number of - * basic watchdog increments - * (Default value with Watchdog divider 100µs - * means 100ms Watchdog) - */ -#define ESC_WDG_TIME_PDAT_TIME_MASK (0xFFFFU) -#define ESC_WDG_TIME_PDAT_TIME_SHIFT (0U) -#define ESC_WDG_TIME_PDAT_TIME_GET(x) (((uint16_t)(x) & ESC_WDG_TIME_PDAT_TIME_MASK) >> ESC_WDG_TIME_PDAT_TIME_SHIFT) - -/* Bitfield definition for register: WDG_STAT_PDAT */ -/* - * ST (RW) - * - * Watchdog Status of Process Data (triggered - * by SyncManagers) - * 0:Watchdog Process Data expired - * 1:Watchdog Process Data is active or - * disabled - */ -#define ESC_WDG_STAT_PDAT_ST_MASK (0x1U) -#define ESC_WDG_STAT_PDAT_ST_SHIFT (0U) -#define ESC_WDG_STAT_PDAT_ST_SET(x) (((uint16_t)(x) << ESC_WDG_STAT_PDAT_ST_SHIFT) & ESC_WDG_STAT_PDAT_ST_MASK) -#define ESC_WDG_STAT_PDAT_ST_GET(x) (((uint16_t)(x) & ESC_WDG_STAT_PDAT_ST_MASK) >> ESC_WDG_STAT_PDAT_ST_SHIFT) - -/* Bitfield definition for register: WDG_CNT_PDAT */ -/* - * CNT (RO) - * - * Watchdog Counter Process Data (counting is - * stopped when 0xFF is reached). Counts if - * Process Data Watchdog expires. - */ -#define ESC_WDG_CNT_PDAT_CNT_MASK (0xFFU) -#define ESC_WDG_CNT_PDAT_CNT_SHIFT (0U) -#define ESC_WDG_CNT_PDAT_CNT_GET(x) (((uint8_t)(x) & ESC_WDG_CNT_PDAT_CNT_MASK) >> ESC_WDG_CNT_PDAT_CNT_SHIFT) - -/* Bitfield definition for register: WDG_CNT_PDI */ -/* - * CNT (RO) - * - * Watchdog PDI counter (counting is stopped - * when 0xFF is reached). Counts if PDI - * Watchdog expires. - */ -#define ESC_WDG_CNT_PDI_CNT_MASK (0xFFU) -#define ESC_WDG_CNT_PDI_CNT_SHIFT (0U) -#define ESC_WDG_CNT_PDI_CNT_GET(x) (((uint8_t)(x) & ESC_WDG_CNT_PDI_CNT_MASK) >> ESC_WDG_CNT_PDI_CNT_SHIFT) - -/* Bitfield definition for register: EEPROM_CFG */ -/* - * FORCE_ECAT (RO) - * - * Force ECAT access: - * 0:Do not change Bit 0x0501[0] - * 1:Reset Bit 0x0501[0] to 0 - */ -#define ESC_EEPROM_CFG_FORCE_ECAT_MASK (0x2U) -#define ESC_EEPROM_CFG_FORCE_ECAT_SHIFT (1U) -#define ESC_EEPROM_CFG_FORCE_ECAT_GET(x) (((uint8_t)(x) & ESC_EEPROM_CFG_FORCE_ECAT_MASK) >> ESC_EEPROM_CFG_FORCE_ECAT_SHIFT) - -/* - * PDI (RO) - * - * EEPROM control is offered to PDI: - * 0:no - * 1:yes (PDI has EEPROM control) - */ -#define ESC_EEPROM_CFG_PDI_MASK (0x1U) -#define ESC_EEPROM_CFG_PDI_SHIFT (0U) -#define ESC_EEPROM_CFG_PDI_GET(x) (((uint8_t)(x) & ESC_EEPROM_CFG_PDI_MASK) >> ESC_EEPROM_CFG_PDI_SHIFT) - -/* Bitfield definition for register: EEPROM_PDI_ACC_STAT */ -/* - * ACCESS (RW) - * - * Access to EEPROM: - * 0:PDI releases EEPROM access - * 1:PDI takes EEPROM access (PDI has - * EEPROM control) - */ -#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK (0x1U) -#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT (0U) -#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_SET(x) (((uint8_t)(x) << ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT) & ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK) -#define ESC_EEPROM_PDI_ACC_STAT_ACCESS_GET(x) (((uint8_t)(x) & ESC_EEPROM_PDI_ACC_STAT_ACCESS_MASK) >> ESC_EEPROM_PDI_ACC_STAT_ACCESS_SHIFT) - -/* Bitfield definition for register: EEPROM_CTRL_STAT */ -/* - * BUSY (RO) - * - * Busy: - * 0:EEPROM Interface is idle - * 1:EEPROM Interface is busy - */ -#define ESC_EEPROM_CTRL_STAT_BUSY_MASK (0x8000U) -#define ESC_EEPROM_CTRL_STAT_BUSY_SHIFT (15U) -#define ESC_EEPROM_CTRL_STAT_BUSY_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_BUSY_MASK) >> ESC_EEPROM_CTRL_STAT_BUSY_SHIFT) - -/* - * ERR_WEN (RO) - * - * Error Write Enable*3 - * : - * 0:No error - * 1:Write Command without Write enable - */ -#define ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK (0x4000U) -#define ESC_EEPROM_CTRL_STAT_ERR_WEN_SHIFT (14U) -#define ESC_EEPROM_CTRL_STAT_ERR_WEN_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ERR_WEN_MASK) >> ESC_EEPROM_CTRL_STAT_ERR_WEN_SHIFT) - -/* - * ERR_ACK_CMD (RW) - * - * Error Acknowledge/Command*3 - * : - * 0:No error - * 1:Missing EEPROM acknowledge or invalid - * command - * EEPROM emulation only:PDI writes 1 if a temporary - * failure has occurred. - */ -#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK (0x2000U) -#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT (13U) -#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) -#define ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_MASK) >> ESC_EEPROM_CTRL_STAT_ERR_ACK_CMD_SHIFT) - -/* - * EE_LDS (RO) - * - * EEPROM loading status: - * 0:EEPROM loaded, device information ok - * 1:EEPROM not loaded, device information not - * available (EEPROM loading in progress or - * finished with a failure) - */ -#define ESC_EEPROM_CTRL_STAT_EE_LDS_MASK (0x1000U) -#define ESC_EEPROM_CTRL_STAT_EE_LDS_SHIFT (12U) -#define ESC_EEPROM_CTRL_STAT_EE_LDS_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_LDS_MASK) >> ESC_EEPROM_CTRL_STAT_EE_LDS_SHIFT) - -/* - * CKSM_ERR (RW) - * - * Checksum Error in ESC Configuration Area: - * 0:Checksum ok - * 1:Checksum error - * EEPROM emulation for IP Core only:PDI writes 1 if a - * CRC failure has occurred for a reload command. - */ -#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK (0x800U) -#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT (11U) -#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT) & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) -#define ESC_EEPROM_CTRL_STAT_CKSM_ERR_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_CKSM_ERR_MASK) >> ESC_EEPROM_CTRL_STAT_CKSM_ERR_SHIFT) - -/* - * CMD (RW) - * - * Command register*2: - * Write:Initiate command. - * Read:Currently executed command - * Commands: - * 000:No command/EEPROM idle (clear error bits) - * 001:Read - * 010:Write - * 100:Reload - * Others:Reserved/invalid commands (do not issue) - * EEPROM emulation only:after execution, PDI writes - * command value to indicate operation is ready. - */ -#define ESC_EEPROM_CTRL_STAT_CMD_MASK (0x700U) -#define ESC_EEPROM_CTRL_STAT_CMD_SHIFT (8U) -#define ESC_EEPROM_CTRL_STAT_CMD_SET(x) (((uint16_t)(x) << ESC_EEPROM_CTRL_STAT_CMD_SHIFT) & ESC_EEPROM_CTRL_STAT_CMD_MASK) -#define ESC_EEPROM_CTRL_STAT_CMD_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_CMD_MASK) >> ESC_EEPROM_CTRL_STAT_CMD_SHIFT) - -/* - * EE_ALGM (RO) - * - * Selected EEPROM Algorithm: - * 0:1 address byte (1Kbit – 16Kbit EEPROMs) - * 1:2 address bytes (32Kbit – 4 Mbit EEPROMs) - */ -#define ESC_EEPROM_CTRL_STAT_EE_ALGM_MASK (0x80U) -#define ESC_EEPROM_CTRL_STAT_EE_ALGM_SHIFT (7U) -#define ESC_EEPROM_CTRL_STAT_EE_ALGM_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_ALGM_MASK) >> ESC_EEPROM_CTRL_STAT_EE_ALGM_SHIFT) - -/* - * NUM_RD_BYTE (RO) - * - * Supported number of EEPROM read bytes: - * 0:4 Bytes - * 1:8 Bytes - */ -#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_MASK (0x40U) -#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_SHIFT (6U) -#define ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_MASK) >> ESC_EEPROM_CTRL_STAT_NUM_RD_BYTE_SHIFT) - -/* - * EE_EMU (RO) - * - * EPROM emulation: - * 0:Normal operation (I²C interface used) - * 1:PDI emulates EEPROM (I²C not used) - */ -#define ESC_EEPROM_CTRL_STAT_EE_EMU_MASK (0x20U) -#define ESC_EEPROM_CTRL_STAT_EE_EMU_SHIFT (5U) -#define ESC_EEPROM_CTRL_STAT_EE_EMU_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_EE_EMU_MASK) >> ESC_EEPROM_CTRL_STAT_EE_EMU_SHIFT) - -/* - * ECAT_WEN (RO) - * - * ECAT write enable*2 - * : - * 0:Write requests are disabled - * 1:Write requests are enabled - * This bit is always 1 if PDI has EEPROM control. - */ -#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_MASK (0x1U) -#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_SHIFT (0U) -#define ESC_EEPROM_CTRL_STAT_ECAT_WEN_GET(x) (((uint16_t)(x) & ESC_EEPROM_CTRL_STAT_ECAT_WEN_MASK) >> ESC_EEPROM_CTRL_STAT_ECAT_WEN_SHIFT) - -/* Bitfield definition for register: EEPROM_ADDR */ -/* - * ADDR (RW) - * - * EEPROM Address - * 0:First word (= 16 bit) - * 1:Second word - * … - * Actually used EEPROM Address bits: - * [9-0] : EEPROM size up to 16 Kbit - * [17-0] : EEPROM size 32 Kbit – 4 Mbit - * [31-0] : EEPROM Emulation - */ -#define ESC_EEPROM_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define ESC_EEPROM_ADDR_ADDR_SHIFT (0U) -#define ESC_EEPROM_ADDR_ADDR_SET(x) (((uint32_t)(x) << ESC_EEPROM_ADDR_ADDR_SHIFT) & ESC_EEPROM_ADDR_ADDR_MASK) -#define ESC_EEPROM_ADDR_ADDR_GET(x) (((uint32_t)(x) & ESC_EEPROM_ADDR_ADDR_MASK) >> ESC_EEPROM_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: EEPROM_DATA */ -/* - * HI (RW) - * - * EEPROM Read data (data read from - * EEPROM, higher bytes) - */ -#define ESC_EEPROM_DATA_HI_MASK (0xFFFFFFFFFFFF0000ULL) -#define ESC_EEPROM_DATA_HI_SHIFT (16U) -#define ESC_EEPROM_DATA_HI_SET(x) (((uint64_t)(x) << ESC_EEPROM_DATA_HI_SHIFT) & ESC_EEPROM_DATA_HI_MASK) -#define ESC_EEPROM_DATA_HI_GET(x) (((uint64_t)(x) & ESC_EEPROM_DATA_HI_MASK) >> ESC_EEPROM_DATA_HI_SHIFT) - -/* - * LO (RW) - * - * EEPROM Write data (data to be written to - * EEPROM) or - * EEPROM Read data (data read from - * EEPROM, lower bytes) - */ -#define ESC_EEPROM_DATA_LO_MASK (0xFFFFU) -#define ESC_EEPROM_DATA_LO_SHIFT (0U) -#define ESC_EEPROM_DATA_LO_SET(x) (((uint64_t)(x) << ESC_EEPROM_DATA_LO_SHIFT) & ESC_EEPROM_DATA_LO_MASK) -#define ESC_EEPROM_DATA_LO_GET(x) (((uint64_t)(x) & ESC_EEPROM_DATA_LO_MASK) >> ESC_EEPROM_DATA_LO_SHIFT) - -/* Bitfield definition for register: MII_MNG_CS */ -/* - * BUSY (RO) - * - * Busy: - * 0:MII Management Interface is idle - * 1:MII Management Interface is busy - */ -#define ESC_MII_MNG_CS_BUSY_MASK (0x8000U) -#define ESC_MII_MNG_CS_BUSY_SHIFT (15U) -#define ESC_MII_MNG_CS_BUSY_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_BUSY_MASK) >> ESC_MII_MNG_CS_BUSY_SHIFT) - -/* - * CMD_ERR (RO) - * - * Command error: - * 0:Last Command was successful - * 1:Invalid command or write command - * without Write Enable - * Cleared by executing a valid command or by - * writing “00” to Command register bits [9:8]. - */ -#define ESC_MII_MNG_CS_CMD_ERR_MASK (0x4000U) -#define ESC_MII_MNG_CS_CMD_ERR_SHIFT (14U) -#define ESC_MII_MNG_CS_CMD_ERR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_CMD_ERR_MASK) >> ESC_MII_MNG_CS_CMD_ERR_SHIFT) - -/* - * RD_ERR (RO) - * - * Read error: - * 0:No read error - * 1:Read error occurred (PHY or register - * not available) - * Cleared by writing to register 0x0511 - */ -#define ESC_MII_MNG_CS_RD_ERR_MASK (0x2000U) -#define ESC_MII_MNG_CS_RD_ERR_SHIFT (13U) -#define ESC_MII_MNG_CS_RD_ERR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_RD_ERR_MASK) >> ESC_MII_MNG_CS_RD_ERR_SHIFT) - -/* - * CMD (RW) - * - * Command register*: - * Write:Initiate command. - * Read:Currently executed command - * 00:No command/MI idle (clear error bits) - * 01:Read - * 10:Write - * Others:Reserved/invalid command (do not - * issue) - */ -#define ESC_MII_MNG_CS_CMD_MASK (0x300U) -#define ESC_MII_MNG_CS_CMD_SHIFT (8U) -#define ESC_MII_MNG_CS_CMD_SET(x) (((uint16_t)(x) << ESC_MII_MNG_CS_CMD_SHIFT) & ESC_MII_MNG_CS_CMD_MASK) -#define ESC_MII_MNG_CS_CMD_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_CMD_MASK) >> ESC_MII_MNG_CS_CMD_SHIFT) - -/* - * PHY_ADDR (RO) - * - * PHY address of port 0 - * (this is equal to the PHY address offset, if the - * PHY addresses are consecutive) - * IP Core since V3.0.0/3.00c: - * Translation 0x0512[7]=0: - * Register 0x0510[7:3] shows PHY address of - * port 0 - * Translation 0x0512[7]=1: - * Register 0x0510[7:3] shows the PHY address - * which will be used for port 0-3 as requested - * by 0x0512[4:0] (valid values 0-3) - */ -#define ESC_MII_MNG_CS_PHY_ADDR_MASK (0xF8U) -#define ESC_MII_MNG_CS_PHY_ADDR_SHIFT (3U) -#define ESC_MII_MNG_CS_PHY_ADDR_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_PHY_ADDR_MASK) >> ESC_MII_MNG_CS_PHY_ADDR_SHIFT) - -/* - * LINK_DC (RO) - * - * MI link detection and configuration: - * 0:Disabled for all ports - * 1:Enabled for at least one MII port, refer - * to PHY Port Status (0x0518 ff.) for - * details - */ -#define ESC_MII_MNG_CS_LINK_DC_MASK (0x4U) -#define ESC_MII_MNG_CS_LINK_DC_SHIFT (2U) -#define ESC_MII_MNG_CS_LINK_DC_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_LINK_DC_MASK) >> ESC_MII_MNG_CS_LINK_DC_SHIFT) - -/* - * PDI (RO) - * - * Management Interface can be controlled by - * PDI (registers 0x0516-0x0517): - * 0:Only ECAT control - * 1:PDI control possible - */ -#define ESC_MII_MNG_CS_PDI_MASK (0x2U) -#define ESC_MII_MNG_CS_PDI_SHIFT (1U) -#define ESC_MII_MNG_CS_PDI_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_PDI_MASK) >> ESC_MII_MNG_CS_PDI_SHIFT) - -/* - * WEN (RO) - * - * Write enable*: - * 0:Write disabled - * 1:Write enabled - * This bit is always 1 if PDI has MI control. - * ET1100-0000/-0001 exception: - * Bit is not always 1 if PDI has MI control, and - * bit is writable by PDI. - */ -#define ESC_MII_MNG_CS_WEN_MASK (0x1U) -#define ESC_MII_MNG_CS_WEN_SHIFT (0U) -#define ESC_MII_MNG_CS_WEN_GET(x) (((uint16_t)(x) & ESC_MII_MNG_CS_WEN_MASK) >> ESC_MII_MNG_CS_WEN_SHIFT) - -/* Bitfield definition for register: PHY_ADDR */ -/* - * SHOW (RW) - * - * Target PHY Address translation: - * 0:Enabled - * 1:Disabled - * Refer to 0x0512[4:0] and 0x0510[7:3] for - * details. - */ -#define ESC_PHY_ADDR_SHOW_MASK (0x80U) -#define ESC_PHY_ADDR_SHOW_SHIFT (7U) -#define ESC_PHY_ADDR_SHOW_SET(x) (((uint8_t)(x) << ESC_PHY_ADDR_SHOW_SHIFT) & ESC_PHY_ADDR_SHOW_MASK) -#define ESC_PHY_ADDR_SHOW_GET(x) (((uint8_t)(x) & ESC_PHY_ADDR_SHOW_MASK) >> ESC_PHY_ADDR_SHOW_SHIFT) - -/* - * ADDR (RW) - * - * Target PHY Address - * Translation 0x0512[7]=0: - * 0-3:Target PHY Addresses 0-3 are used - * to access the PHYs at port 0-3, when - * the PHY addresses are properly - * configured - * 4-31:The configured PHY address of port 0 - * (PHY address offset) is added to the - * Target PHY Address values 4-31 - * when accessing a PHY - * Translation 0x0512[7]=1: - * 0-31:Target PHY Addresses is used when - * accessing a PHY without translation - */ -#define ESC_PHY_ADDR_ADDR_MASK (0x1FU) -#define ESC_PHY_ADDR_ADDR_SHIFT (0U) -#define ESC_PHY_ADDR_ADDR_SET(x) (((uint8_t)(x) << ESC_PHY_ADDR_ADDR_SHIFT) & ESC_PHY_ADDR_ADDR_MASK) -#define ESC_PHY_ADDR_ADDR_GET(x) (((uint8_t)(x) & ESC_PHY_ADDR_ADDR_MASK) >> ESC_PHY_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: PHY_REG_ADDR */ -/* - * ADDR (RW) - * - * Address of PHY Register that shall be - * read/written - */ -#define ESC_PHY_REG_ADDR_ADDR_MASK (0x1FU) -#define ESC_PHY_REG_ADDR_ADDR_SHIFT (0U) -#define ESC_PHY_REG_ADDR_ADDR_SET(x) (((uint8_t)(x) << ESC_PHY_REG_ADDR_ADDR_SHIFT) & ESC_PHY_REG_ADDR_ADDR_MASK) -#define ESC_PHY_REG_ADDR_ADDR_GET(x) (((uint8_t)(x) & ESC_PHY_REG_ADDR_ADDR_MASK) >> ESC_PHY_REG_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: PHY_DATA */ -/* - * DATA (RW) - * - * PHY Read/Write Data - */ -#define ESC_PHY_DATA_DATA_MASK (0xFFFFU) -#define ESC_PHY_DATA_DATA_SHIFT (0U) -#define ESC_PHY_DATA_DATA_SET(x) (((uint16_t)(x) << ESC_PHY_DATA_DATA_SHIFT) & ESC_PHY_DATA_DATA_MASK) -#define ESC_PHY_DATA_DATA_GET(x) (((uint16_t)(x) & ESC_PHY_DATA_DATA_MASK) >> ESC_PHY_DATA_DATA_SHIFT) - -/* Bitfield definition for register: MIIM_ECAT_ACC_STAT */ -/* - * ACC (RO) - * - * Access to MII management: - * 0:ECAT enables PDI takeover of MII - * management interface - * 1:ECAT claims exclusive access to MII - * management interface - */ -#define ESC_MIIM_ECAT_ACC_STAT_ACC_MASK (0x1U) -#define ESC_MIIM_ECAT_ACC_STAT_ACC_SHIFT (0U) -#define ESC_MIIM_ECAT_ACC_STAT_ACC_GET(x) (((uint8_t)(x) & ESC_MIIM_ECAT_ACC_STAT_ACC_MASK) >> ESC_MIIM_ECAT_ACC_STAT_ACC_SHIFT) - -/* Bitfield definition for register: MIIM_PDI_ACC_STAT */ -/* - * FORCE (RO) - * - * Force PDI Access State: - * 0:Do not change Bit 0x0517[0] - * 1:Reset Bit 0x0517[0] to 0 - */ -#define ESC_MIIM_PDI_ACC_STAT_FORCE_MASK (0x2U) -#define ESC_MIIM_PDI_ACC_STAT_FORCE_SHIFT (1U) -#define ESC_MIIM_PDI_ACC_STAT_FORCE_GET(x) (((uint8_t)(x) & ESC_MIIM_PDI_ACC_STAT_FORCE_MASK) >> ESC_MIIM_PDI_ACC_STAT_FORCE_SHIFT) - -/* - * ACC (RW) - * - * Access to MII management: - * 0:ECAT has access to MII management - * 1:PDI has access to MII management - */ -#define ESC_MIIM_PDI_ACC_STAT_ACC_MASK (0x1U) -#define ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT (0U) -#define ESC_MIIM_PDI_ACC_STAT_ACC_SET(x) (((uint8_t)(x) << ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT) & ESC_MIIM_PDI_ACC_STAT_ACC_MASK) -#define ESC_MIIM_PDI_ACC_STAT_ACC_GET(x) (((uint8_t)(x) & ESC_MIIM_PDI_ACC_STAT_ACC_MASK) >> ESC_MIIM_PDI_ACC_STAT_ACC_SHIFT) - -/* Bitfield definition for register array: PHY_STAT */ -/* - * PCU (RW) - * - * PHY configuration updated: - * 0:No update - * 1:PHY configuration was updated - * Cleared by writing any value to at least one - * of the PHY Port y Status registers. - */ -#define ESC_PHY_STAT_PCU_MASK (0x20U) -#define ESC_PHY_STAT_PCU_SHIFT (5U) -#define ESC_PHY_STAT_PCU_SET(x) (((uint8_t)(x) << ESC_PHY_STAT_PCU_SHIFT) & ESC_PHY_STAT_PCU_MASK) -#define ESC_PHY_STAT_PCU_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_PCU_MASK) >> ESC_PHY_STAT_PCU_SHIFT) - -/* - * LPE (RO) - * - * Link partner error: - * 0:No error detected - * 1:Link partner error - */ -#define ESC_PHY_STAT_LPE_MASK (0x10U) -#define ESC_PHY_STAT_LPE_SHIFT (4U) -#define ESC_PHY_STAT_LPE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LPE_MASK) >> ESC_PHY_STAT_LPE_SHIFT) - -/* - * RE (RW) - * - * Read error: - * 0:No read error occurred - * 1:A read error has occurred - * Cleared by writing any value to at least one - * of the PHY Port y Status registers. - */ -#define ESC_PHY_STAT_RE_MASK (0x8U) -#define ESC_PHY_STAT_RE_SHIFT (3U) -#define ESC_PHY_STAT_RE_SET(x) (((uint8_t)(x) << ESC_PHY_STAT_RE_SHIFT) & ESC_PHY_STAT_RE_MASK) -#define ESC_PHY_STAT_RE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_RE_MASK) >> ESC_PHY_STAT_RE_SHIFT) - -/* - * LSE (RO) - * - * Link status error: - * 0:No error - * 1:Link error, link inhibited - */ -#define ESC_PHY_STAT_LSE_MASK (0x4U) -#define ESC_PHY_STAT_LSE_SHIFT (2U) -#define ESC_PHY_STAT_LSE_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LSE_MASK) >> ESC_PHY_STAT_LSE_SHIFT) - -/* - * LS (RO) - * - * Link status (100 Mbit/s, Full Duplex, Auto - * negotiation): - * 0:No link - * 1:Link detected - */ -#define ESC_PHY_STAT_LS_MASK (0x2U) -#define ESC_PHY_STAT_LS_SHIFT (1U) -#define ESC_PHY_STAT_LS_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_LS_MASK) >> ESC_PHY_STAT_LS_SHIFT) - -/* - * PLS (RO) - * - * Physical link status (PHY status register 1.2): - * 0:No physical link - * 1:Physical link detected - */ -#define ESC_PHY_STAT_PLS_MASK (0x1U) -#define ESC_PHY_STAT_PLS_SHIFT (0U) -#define ESC_PHY_STAT_PLS_GET(x) (((uint8_t)(x) & ESC_PHY_STAT_PLS_MASK) >> ESC_PHY_STAT_PLS_SHIFT) - -/* Bitfield definition for register of struct array FMMU: LOGIC_START_ADDR */ -/* - * ADDR (RO) - * - * Logical start address within the EtherCAT - * Address Space. - */ -#define ESC_FMMU_LOGIC_START_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define ESC_FMMU_LOGIC_START_ADDR_ADDR_SHIFT (0U) -#define ESC_FMMU_LOGIC_START_ADDR_ADDR_GET(x) (((uint32_t)(x) & ESC_FMMU_LOGIC_START_ADDR_ADDR_MASK) >> ESC_FMMU_LOGIC_START_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register of struct array FMMU: LENGTH */ -/* - * OFFSET (RO) - * - * Offset from the first logical FMMU byte to the - * last FMMU byte + 1 (e.g., if two bytes are - * used, then this parameter shall contain 2) - */ -#define ESC_FMMU_LENGTH_OFFSET_MASK (0xFFFFU) -#define ESC_FMMU_LENGTH_OFFSET_SHIFT (0U) -#define ESC_FMMU_LENGTH_OFFSET_GET(x) (((uint16_t)(x) & ESC_FMMU_LENGTH_OFFSET_MASK) >> ESC_FMMU_LENGTH_OFFSET_SHIFT) - -/* Bitfield definition for register of struct array FMMU: LOGIC_START_BIT */ -/* - * START (RO) - * - * Logical starting bit that shall be mapped (bits - * are counted from least significant bit 0 to - * most significant bit 7) - */ -#define ESC_FMMU_LOGIC_START_BIT_START_MASK (0x7U) -#define ESC_FMMU_LOGIC_START_BIT_START_SHIFT (0U) -#define ESC_FMMU_LOGIC_START_BIT_START_GET(x) (((uint8_t)(x) & ESC_FMMU_LOGIC_START_BIT_START_MASK) >> ESC_FMMU_LOGIC_START_BIT_START_SHIFT) - -/* Bitfield definition for register of struct array FMMU: LOGIC_STOP_BIT */ -/* - * STOP (RO) - * - * Last logical bit that shall be mapped (bits are - * counted from least significant bit 0 to most - * significant bit 7) - */ -#define ESC_FMMU_LOGIC_STOP_BIT_STOP_MASK (0x7U) -#define ESC_FMMU_LOGIC_STOP_BIT_STOP_SHIFT (0U) -#define ESC_FMMU_LOGIC_STOP_BIT_STOP_GET(x) (((uint8_t)(x) & ESC_FMMU_LOGIC_STOP_BIT_STOP_MASK) >> ESC_FMMU_LOGIC_STOP_BIT_STOP_SHIFT) - -/* Bitfield definition for register of struct array FMMU: PHYSICAL_START_ADDR */ -/* - * ADDR (RO) - * - * Physical Start Address (mapped to logical - * Start address) - */ -#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_MASK (0xFFFFU) -#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_SHIFT (0U) -#define ESC_FMMU_PHYSICAL_START_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_FMMU_PHYSICAL_START_ADDR_ADDR_MASK) >> ESC_FMMU_PHYSICAL_START_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register of struct array FMMU: PHYSICAL_START_BIT */ -/* - * START (RO) - * - * Physical starting bit as target of logical start - * bit mapping (bits are counted from least - * significant bit 0 to most significant bit 7) - */ -#define ESC_FMMU_PHYSICAL_START_BIT_START_MASK (0x7U) -#define ESC_FMMU_PHYSICAL_START_BIT_START_SHIFT (0U) -#define ESC_FMMU_PHYSICAL_START_BIT_START_GET(x) (((uint8_t)(x) & ESC_FMMU_PHYSICAL_START_BIT_START_MASK) >> ESC_FMMU_PHYSICAL_START_BIT_START_SHIFT) - -/* Bitfield definition for register of struct array FMMU: TYPE */ -/* - * MAP_WR (RO) - * - * 0:Ignore mapping for write accesses - * 1:Use mapping for write accesses - */ -#define ESC_FMMU_TYPE_MAP_WR_MASK (0x2U) -#define ESC_FMMU_TYPE_MAP_WR_SHIFT (1U) -#define ESC_FMMU_TYPE_MAP_WR_GET(x) (((uint8_t)(x) & ESC_FMMU_TYPE_MAP_WR_MASK) >> ESC_FMMU_TYPE_MAP_WR_SHIFT) - -/* - * MAP_RD (RO) - * - * 0:Ignore mapping for read accesses - * 1:Use mapping for read accesses - */ -#define ESC_FMMU_TYPE_MAP_RD_MASK (0x1U) -#define ESC_FMMU_TYPE_MAP_RD_SHIFT (0U) -#define ESC_FMMU_TYPE_MAP_RD_GET(x) (((uint8_t)(x) & ESC_FMMU_TYPE_MAP_RD_MASK) >> ESC_FMMU_TYPE_MAP_RD_SHIFT) - -/* Bitfield definition for register of struct array FMMU: ACTIVATE */ -/* - * ACT (RO) - * - * 0:FMMU deactivated - * 1:FMMU activated. FMMU checks - * logically addressed blocks to be - * mapped according to configured - * mapping - */ -#define ESC_FMMU_ACTIVATE_ACT_MASK (0x1U) -#define ESC_FMMU_ACTIVATE_ACT_SHIFT (0U) -#define ESC_FMMU_ACTIVATE_ACT_GET(x) (((uint8_t)(x) & ESC_FMMU_ACTIVATE_ACT_MASK) >> ESC_FMMU_ACTIVATE_ACT_SHIFT) - -/* Bitfield definition for register of struct array SYNCM: PHYSICAL_START_ADDR */ -/* - * ADDR (RO) - * - * First byte that will be handled by - * SyncManager - */ -#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_MASK (0xFFFFU) -#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_SHIFT (0U) -#define ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_GET(x) (((uint16_t)(x) & ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_MASK) >> ESC_SYNCM_PHYSICAL_START_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register of struct array SYNCM: LENGTH */ -/* - * LEN (RO) - * - * Number of bytes assigned to SyncManager - * (shall be greater than 1, otherwise - * SyncManager is not activated. If set to 1, only - * Watchdog Trigger is generated if configured) - */ -#define ESC_SYNCM_LENGTH_LEN_MASK (0xFFFFU) -#define ESC_SYNCM_LENGTH_LEN_SHIFT (0U) -#define ESC_SYNCM_LENGTH_LEN_GET(x) (((uint16_t)(x) & ESC_SYNCM_LENGTH_LEN_MASK) >> ESC_SYNCM_LENGTH_LEN_SHIFT) - -/* Bitfield definition for register of struct array SYNCM: CONTROL */ -/* - * WDG_TRG_EN (RO) - * - * Watchdog Trigger Enable: - * 0:Disabled - * 1:Enabled - */ -#define ESC_SYNCM_CONTROL_WDG_TRG_EN_MASK (0x40U) -#define ESC_SYNCM_CONTROL_WDG_TRG_EN_SHIFT (6U) -#define ESC_SYNCM_CONTROL_WDG_TRG_EN_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_WDG_TRG_EN_MASK) >> ESC_SYNCM_CONTROL_WDG_TRG_EN_SHIFT) - -/* - * INT_AL (RO) - * - * Interrupt in AL Event Request Register: - * 0:Disabled - * 1:Enabled - */ -#define ESC_SYNCM_CONTROL_INT_AL_MASK (0x20U) -#define ESC_SYNCM_CONTROL_INT_AL_SHIFT (5U) -#define ESC_SYNCM_CONTROL_INT_AL_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_INT_AL_MASK) >> ESC_SYNCM_CONTROL_INT_AL_SHIFT) - -/* - * INT_ECAT (RO) - * - * Interrupt in ECAT Event Request Register: - * 0:Disabled - * 1:Enabled - */ -#define ESC_SYNCM_CONTROL_INT_ECAT_MASK (0x10U) -#define ESC_SYNCM_CONTROL_INT_ECAT_SHIFT (4U) -#define ESC_SYNCM_CONTROL_INT_ECAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_INT_ECAT_MASK) >> ESC_SYNCM_CONTROL_INT_ECAT_SHIFT) - -/* - * DIR (RO) - * - * Direction: - * 00:Read:ECAT read access, PDI write - * access. - * 01:Write:ECAT write access, PDI read - * access. - * 10:Reserved - * 11:Reserved - */ -#define ESC_SYNCM_CONTROL_DIR_MASK (0xCU) -#define ESC_SYNCM_CONTROL_DIR_SHIFT (2U) -#define ESC_SYNCM_CONTROL_DIR_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_DIR_MASK) >> ESC_SYNCM_CONTROL_DIR_SHIFT) - -/* - * OP_MODE (RO) - * - * Operation Mode: - * 00:Buffered (3 buffer mode) - * 01:Reserved - * 10:Mailbox (Single buffer mode) - * 11:Reserved - */ -#define ESC_SYNCM_CONTROL_OP_MODE_MASK (0x3U) -#define ESC_SYNCM_CONTROL_OP_MODE_SHIFT (0U) -#define ESC_SYNCM_CONTROL_OP_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_CONTROL_OP_MODE_MASK) >> ESC_SYNCM_CONTROL_OP_MODE_SHIFT) - -/* Bitfield definition for register of struct array SYNCM: STATUS */ -/* - * WB_INUSE (RO) - * - * Write buffer in use (opened) - */ -#define ESC_SYNCM_STATUS_WB_INUSE_MASK (0x80U) -#define ESC_SYNCM_STATUS_WB_INUSE_SHIFT (7U) -#define ESC_SYNCM_STATUS_WB_INUSE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_WB_INUSE_MASK) >> ESC_SYNCM_STATUS_WB_INUSE_SHIFT) - -/* - * RB_INUSE (RO) - * - * Read buffer in use (opened) - */ -#define ESC_SYNCM_STATUS_RB_INUSE_MASK (0x40U) -#define ESC_SYNCM_STATUS_RB_INUSE_SHIFT (6U) -#define ESC_SYNCM_STATUS_RB_INUSE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_RB_INUSE_MASK) >> ESC_SYNCM_STATUS_RB_INUSE_SHIFT) - -/* - * BUF_MODE (RO) - * - * Buffered mode:buffer status (last written - * buffer): - * 00:1 - * st buffer - * 01:2 - * nd buffer - * 10:3 - * rd buffer - * 11:(no buffer written) - * Mailbox mode:reserved - */ -#define ESC_SYNCM_STATUS_BUF_MODE_MASK (0x30U) -#define ESC_SYNCM_STATUS_BUF_MODE_SHIFT (4U) -#define ESC_SYNCM_STATUS_BUF_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_BUF_MODE_MASK) >> ESC_SYNCM_STATUS_BUF_MODE_SHIFT) - -/* - * MBX_MODE (RO) - * - * Mailbox mode:mailbox status: - * 0:Mailbox empty - * 1:Mailbox full - * Buffered mode:reserved - */ -#define ESC_SYNCM_STATUS_MBX_MODE_MASK (0x8U) -#define ESC_SYNCM_STATUS_MBX_MODE_SHIFT (3U) -#define ESC_SYNCM_STATUS_MBX_MODE_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_MBX_MODE_MASK) >> ESC_SYNCM_STATUS_MBX_MODE_SHIFT) - -/* - * INT_RD (RO) - * - * Interrupt Read: - * 1:Interrupt after buffer was completely and - * successfully read - * 0:Interrupt cleared after first byte of buffer - * was written - * NOTE:This interrupt is signalled to the writing - * side if enabled in the SM Control register - */ -#define ESC_SYNCM_STATUS_INT_RD_MASK (0x2U) -#define ESC_SYNCM_STATUS_INT_RD_SHIFT (1U) -#define ESC_SYNCM_STATUS_INT_RD_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_INT_RD_MASK) >> ESC_SYNCM_STATUS_INT_RD_SHIFT) - -/* - * INT_WR (RO) - * - * Interrupt Write: - * 1:Interrupt after buffer was completely and - * successfully written - * 0:Interrupt cleared after first byte of buffer - * was read - * NOTE:This interrupt is signalled to the reading - * side if enabled in the SM Control register - */ -#define ESC_SYNCM_STATUS_INT_WR_MASK (0x1U) -#define ESC_SYNCM_STATUS_INT_WR_SHIFT (0U) -#define ESC_SYNCM_STATUS_INT_WR_GET(x) (((uint8_t)(x) & ESC_SYNCM_STATUS_INT_WR_MASK) >> ESC_SYNCM_STATUS_INT_WR_SHIFT) - -/* Bitfield definition for register of struct array SYNCM: ACTIVATE */ -/* - * LATCH_PDI (RO) - * - * Latch Event PDI: - * 0:No - * 1:Generate Latch events when PDI issues - * a buffer exchange or when PDI - * accesses buffer start address - */ -#define ESC_SYNCM_ACTIVATE_LATCH_PDI_MASK (0x80U) -#define ESC_SYNCM_ACTIVATE_LATCH_PDI_SHIFT (7U) -#define ESC_SYNCM_ACTIVATE_LATCH_PDI_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_LATCH_PDI_MASK) >> ESC_SYNCM_ACTIVATE_LATCH_PDI_SHIFT) - -/* - * LATCH_ECAT (RO) - * - * Latch Event ECAT: - * 0:No - * 1:Generate Latch event when EtherCAT - * master issues a buffer exchange - */ -#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_MASK (0x40U) -#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_SHIFT (6U) -#define ESC_SYNCM_ACTIVATE_LATCH_ECAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_LATCH_ECAT_MASK) >> ESC_SYNCM_ACTIVATE_LATCH_ECAT_SHIFT) - -/* - * REPEAT (RO) - * - * Repeat Request: - * A toggle of Repeat Request means that a - * mailbox retry is needed (primarily used in - * conjunction with ECAT Read Mailbox) - */ -#define ESC_SYNCM_ACTIVATE_REPEAT_MASK (0x2U) -#define ESC_SYNCM_ACTIVATE_REPEAT_SHIFT (1U) -#define ESC_SYNCM_ACTIVATE_REPEAT_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_REPEAT_MASK) >> ESC_SYNCM_ACTIVATE_REPEAT_SHIFT) - -/* - * EN (RW) - * - * SyncManager Enable/Disable: - * 0:Disable:Access to Memory without - * SyncManager control - * 1:Enable:SyncManager is active and - * controls Memory area set in - * configuration - */ -#define ESC_SYNCM_ACTIVATE_EN_MASK (0x1U) -#define ESC_SYNCM_ACTIVATE_EN_SHIFT (0U) -#define ESC_SYNCM_ACTIVATE_EN_SET(x) (((uint8_t)(x) << ESC_SYNCM_ACTIVATE_EN_SHIFT) & ESC_SYNCM_ACTIVATE_EN_MASK) -#define ESC_SYNCM_ACTIVATE_EN_GET(x) (((uint8_t)(x) & ESC_SYNCM_ACTIVATE_EN_MASK) >> ESC_SYNCM_ACTIVATE_EN_SHIFT) - -/* Bitfield definition for register of struct array SYNCM: PDI_CTRL */ -/* - * REPEAT_ACK (RW) - * - * Repeat Ack: - * If this is set to the same value as that set by - * Repeat Request, the PDI acknowledges the - * execution of a previous set Repeat request. - */ -#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK (0x2U) -#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT (1U) -#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT) & ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK) -#define ESC_SYNCM_PDI_CTRL_REPEAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNCM_PDI_CTRL_REPEAT_ACK_MASK) >> ESC_SYNCM_PDI_CTRL_REPEAT_ACK_SHIFT) - -/* - * DEACT (RW) - * - * Deactivate SyncManager: - * Read: - * 0:Normal operation, SyncManager - * activated. - * 1:SyncManager deactivated and reset. - * SyncManager locks access to Memory - * area. - * Write: - * 0:Activate SyncManager - * 1:Request SyncManager deactivation - * NOTE:Writing 1 is delayed until the end of the - * frame, which is currently processed. - */ -#define ESC_SYNCM_PDI_CTRL_DEACT_MASK (0x1U) -#define ESC_SYNCM_PDI_CTRL_DEACT_SHIFT (0U) -#define ESC_SYNCM_PDI_CTRL_DEACT_SET(x) (((uint8_t)(x) << ESC_SYNCM_PDI_CTRL_DEACT_SHIFT) & ESC_SYNCM_PDI_CTRL_DEACT_MASK) -#define ESC_SYNCM_PDI_CTRL_DEACT_GET(x) (((uint8_t)(x) & ESC_SYNCM_PDI_CTRL_DEACT_MASK) >> ESC_SYNCM_PDI_CTRL_DEACT_SHIFT) - -/* Bitfield definition for register array: RCV_TIME */ -/* - * LT (RO) - * - * Local time at the beginning of the last receive - * frame containing a write access to register - * 0x0900. - */ -#define ESC_RCV_TIME_LT_MASK (0xFFFFFF00UL) -#define ESC_RCV_TIME_LT_SHIFT (8U) -#define ESC_RCV_TIME_LT_GET(x) (((uint32_t)(x) & ESC_RCV_TIME_LT_MASK) >> ESC_RCV_TIME_LT_SHIFT) - -/* - * REQ (RO) - * - * Write: - * A write access to register 0x0900 with - * BWR or FPWR latches the local time at - * the beginning of the receive frame (start - * first bit of preamble) at each port. - * Write (ESC20, ET1200 exception): - * A write access latches the local time at - * the beginning of the receive frame at - * port 0. It enables the time stamping at - * the other ports. - * Read: - * Local time at the beginning of the last - * receive frame containing a write access - * to this register. - * NOTE:FPWR requires an address match for - * accessing this register like any FPWR command. - * All write commands with address match will - * increment the working counter (e.g., APWR), but - * they will not trigger receive time latching. - */ -#define ESC_RCV_TIME_REQ_MASK (0xFFU) -#define ESC_RCV_TIME_REQ_SHIFT (0U) -#define ESC_RCV_TIME_REQ_GET(x) (((uint32_t)(x) & ESC_RCV_TIME_REQ_MASK) >> ESC_RCV_TIME_REQ_SHIFT) - -/* Bitfield definition for register: SYS_TIME */ -/* - * ST (RW) - * - */ -#define ESC_SYS_TIME_ST_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_SYS_TIME_ST_SHIFT (0U) -#define ESC_SYS_TIME_ST_SET(x) (((uint64_t)(x) << ESC_SYS_TIME_ST_SHIFT) & ESC_SYS_TIME_ST_MASK) -#define ESC_SYS_TIME_ST_GET(x) (((uint64_t)(x) & ESC_SYS_TIME_ST_MASK) >> ESC_SYS_TIME_ST_SHIFT) - -/* Bitfield definition for register: RCVT_ECAT_PU */ -/* - * LT (RO) - * - * Local time at the beginning of a frame (start - * first bit of preamble) received at the ECAT - * Processing Unit containing a write access to - * register 0x0900 - * NOTE:E.g., if port 0 is open, this register reflects - * the Receive Time Port 0 as a 64 Bit value. - * Any valid EtherCAT write access to register - * 0x0900 triggers latching, not only BWR/FPWR - * commands as with register 0x0900. - */ -#define ESC_RCVT_ECAT_PU_LT_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_RCVT_ECAT_PU_LT_SHIFT (0U) -#define ESC_RCVT_ECAT_PU_LT_GET(x) (((uint64_t)(x) & ESC_RCVT_ECAT_PU_LT_MASK) >> ESC_RCVT_ECAT_PU_LT_SHIFT) - -/* Bitfield definition for register: SYS_TIME_OFFSET */ -/* - * OFFSET (RW) - * - * Difference between local time and System - * Time. Offset is added to the local time. - */ -#define ESC_SYS_TIME_OFFSET_OFFSET_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_SYS_TIME_OFFSET_OFFSET_SHIFT (0U) -#define ESC_SYS_TIME_OFFSET_OFFSET_SET(x) (((uint64_t)(x) << ESC_SYS_TIME_OFFSET_OFFSET_SHIFT) & ESC_SYS_TIME_OFFSET_OFFSET_MASK) -#define ESC_SYS_TIME_OFFSET_OFFSET_GET(x) (((uint64_t)(x) & ESC_SYS_TIME_OFFSET_OFFSET_MASK) >> ESC_SYS_TIME_OFFSET_OFFSET_SHIFT) - -/* Bitfield definition for register: SYS_TIME_DELAY */ -/* - * DLY (RW) - * - * Delay between Reference Clock and the - * ESC - */ -#define ESC_SYS_TIME_DELAY_DLY_MASK (0xFFFFFFFFUL) -#define ESC_SYS_TIME_DELAY_DLY_SHIFT (0U) -#define ESC_SYS_TIME_DELAY_DLY_SET(x) (((uint32_t)(x) << ESC_SYS_TIME_DELAY_DLY_SHIFT) & ESC_SYS_TIME_DELAY_DLY_MASK) -#define ESC_SYS_TIME_DELAY_DLY_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DELAY_DLY_MASK) >> ESC_SYS_TIME_DELAY_DLY_SHIFT) - -/* Bitfield definition for register: SYS_TIME_DIFF */ -/* - * DIFF (RO) - * - * 0:Local copy of System Time less than - * received System Time - * 1:Local copy of System Time greater than - * or equal to received System Time - */ -#define ESC_SYS_TIME_DIFF_DIFF_MASK (0x80000000UL) -#define ESC_SYS_TIME_DIFF_DIFF_SHIFT (31U) -#define ESC_SYS_TIME_DIFF_DIFF_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DIFF_DIFF_MASK) >> ESC_SYS_TIME_DIFF_DIFF_SHIFT) - -/* - * NUM (RO) - * - * Mean difference between local copy of - * System Time and received System Time - * values - * Difference = Received System Time – - * local copy of System Time - */ -#define ESC_SYS_TIME_DIFF_NUM_MASK (0x7FFFFFFFUL) -#define ESC_SYS_TIME_DIFF_NUM_SHIFT (0U) -#define ESC_SYS_TIME_DIFF_NUM_GET(x) (((uint32_t)(x) & ESC_SYS_TIME_DIFF_NUM_MASK) >> ESC_SYS_TIME_DIFF_NUM_SHIFT) - -/* Bitfield definition for register: SPD_CNT_START */ -/* - * BW (RW) - * - * Bandwidth for adjustment of local copy of - * System Time (larger values → smaller - * bandwidth and smoother adjustment) - * A write access resets System Time - * Difference (0x092C:0x092F) and Speed - * Counter Diff (0x0932:0x0933). - * Valid values:0x0080 to 0x3FFF - */ -#define ESC_SPD_CNT_START_BW_MASK (0x7FFFU) -#define ESC_SPD_CNT_START_BW_SHIFT (0U) -#define ESC_SPD_CNT_START_BW_SET(x) (((uint16_t)(x) << ESC_SPD_CNT_START_BW_SHIFT) & ESC_SPD_CNT_START_BW_MASK) -#define ESC_SPD_CNT_START_BW_GET(x) (((uint16_t)(x) & ESC_SPD_CNT_START_BW_MASK) >> ESC_SPD_CNT_START_BW_SHIFT) - -/* Bitfield definition for register: SPD_CNT_DIFF */ -/* - * DIFF (RO) - * - * Representation of the deviation between - * local clock period and Reference Clock's - * clock period (representation:two's - * complement) - * Range:±(Speed Counter Start – 0x7F) - */ -#define ESC_SPD_CNT_DIFF_DIFF_MASK (0xFFFFU) -#define ESC_SPD_CNT_DIFF_DIFF_SHIFT (0U) -#define ESC_SPD_CNT_DIFF_DIFF_GET(x) (((uint16_t)(x) & ESC_SPD_CNT_DIFF_DIFF_MASK) >> ESC_SPD_CNT_DIFF_DIFF_SHIFT) - -/* Bitfield definition for register: SYS_TIME_DIFF_FD */ -/* - * DEPTH (RW) - * - * Filter depth for averaging the received - * System Time deviation - * IP Core since V2.2.0/V2.02a: - * A write access resets System Time - * Difference (0x092C:0x092F) - */ -#define ESC_SYS_TIME_DIFF_FD_DEPTH_MASK (0xFU) -#define ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT (0U) -#define ESC_SYS_TIME_DIFF_FD_DEPTH_SET(x) (((uint8_t)(x) << ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT) & ESC_SYS_TIME_DIFF_FD_DEPTH_MASK) -#define ESC_SYS_TIME_DIFF_FD_DEPTH_GET(x) (((uint8_t)(x) & ESC_SYS_TIME_DIFF_FD_DEPTH_MASK) >> ESC_SYS_TIME_DIFF_FD_DEPTH_SHIFT) - -/* Bitfield definition for register: SPD_CNT_FD */ -/* - * DEPTH (RW) - * - * Filter depth for averaging the clock period - * deviation - * IP Core since V2.2.0/V2.02a: - * A write access resets the internal speed - * counter filter - */ -#define ESC_SPD_CNT_FD_DEPTH_MASK (0xFU) -#define ESC_SPD_CNT_FD_DEPTH_SHIFT (0U) -#define ESC_SPD_CNT_FD_DEPTH_SET(x) (((uint8_t)(x) << ESC_SPD_CNT_FD_DEPTH_SHIFT) & ESC_SPD_CNT_FD_DEPTH_MASK) -#define ESC_SPD_CNT_FD_DEPTH_GET(x) (((uint8_t)(x) & ESC_SPD_CNT_FD_DEPTH_MASK) >> ESC_SPD_CNT_FD_DEPTH_SHIFT) - -/* Bitfield definition for register: RCV_TIME_LM */ -/* - * LATCH_MODE (RO) - * - * Receive Time Latch Mode: - * 0:Forwarding mode (used if frames are - * entering the ESC at port 0 first): - * Receive time stamps of ports 1-3 are - * enabled after the write access to - * 0x0900, so the following frame at ports - * 1-3 will be time stamped (this is typically - * the write frame to 0x0900 coming back - * from the network behind the ESC). - * 1:Reverse mode (used if frames are - * entering ESC at port 1-3 first): - * Receive time stamps of ports 1-3 are - * immediately taken over from the internal - * hidden time stamp registers, so the - * previous frame entering the ESC at - * ports 1-3 will be time stamped when the - * write frame to 0x0900 enters port 0 (the - * previous frame at ports 1-3 is typically - * the write frame to 0x0900 coming from - * the master, which will enable time - * stamp - */ -#define ESC_RCV_TIME_LM_LATCH_MODE_MASK (0x1U) -#define ESC_RCV_TIME_LM_LATCH_MODE_SHIFT (0U) -#define ESC_RCV_TIME_LM_LATCH_MODE_GET(x) (((uint8_t)(x) & ESC_RCV_TIME_LM_LATCH_MODE_MASK) >> ESC_RCV_TIME_LM_LATCH_MODE_SHIFT) - -/* Bitfield definition for register: CYC_UNIT_CTRL */ -/* - * LATCHI1 (RO) - * - * Latch In unit 1: - * 0:ECAT-controlled - * 1:PDI-controlled - * NOTE:Latch interrupt is routed to ECAT/PDI - * depending on this setting - */ -#define ESC_CYC_UNIT_CTRL_LATCHI1_MASK (0x20U) -#define ESC_CYC_UNIT_CTRL_LATCHI1_SHIFT (5U) -#define ESC_CYC_UNIT_CTRL_LATCHI1_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_LATCHI1_MASK) >> ESC_CYC_UNIT_CTRL_LATCHI1_SHIFT) - -/* - * LATCHI0 (RO) - * - * Latch In unit 0: - * 0:ECAT-controlled - * 1:PDI-controlled - * NOTE:Latch interrupt is routed to ECAT/PDI - * depending on this setting. - * Always 1 (PDI-controlled) if System Time is PDIcontrolled. - */ -#define ESC_CYC_UNIT_CTRL_LATCHI0_MASK (0x10U) -#define ESC_CYC_UNIT_CTRL_LATCHI0_SHIFT (4U) -#define ESC_CYC_UNIT_CTRL_LATCHI0_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_LATCHI0_MASK) >> ESC_CYC_UNIT_CTRL_LATCHI0_SHIFT) - -/* - * SYNCO (RO) - * - * Cyclic Unit and SYNC0 out unit control: - * 0:ECAT-controlled - * 1:PDI-controlled - */ -#define ESC_CYC_UNIT_CTRL_SYNCO_MASK (0x1U) -#define ESC_CYC_UNIT_CTRL_SYNCO_SHIFT (0U) -#define ESC_CYC_UNIT_CTRL_SYNCO_GET(x) (((uint8_t)(x) & ESC_CYC_UNIT_CTRL_SYNCO_MASK) >> ESC_CYC_UNIT_CTRL_SYNCO_SHIFT) - -/* Bitfield definition for register: SYNCO_ACT */ -/* - * SSDP (RW) - * - * SyncSignal debug pulse (Vasily bit): - * 0:Deactivated - * 1:Immediately generate one ping only on - * SYNC0-1 according to 0x0981[2:1 for - * debugging - * This bit is self-clearing, always read 0. - * All pulses are generated at the same time, - * the cycle time is ignored. The configured - * pulse length is used. - */ -#define ESC_SYNCO_ACT_SSDP_MASK (0x80U) -#define ESC_SYNCO_ACT_SSDP_SHIFT (7U) -#define ESC_SYNCO_ACT_SSDP_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SSDP_SHIFT) & ESC_SYNCO_ACT_SSDP_MASK) -#define ESC_SYNCO_ACT_SSDP_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SSDP_MASK) >> ESC_SYNCO_ACT_SSDP_SHIFT) - -/* - * NFC (RW) - * - * Near future configuration (approx.): - * 0:½ DC width future (231 ns or 263 ns) - * 1:~2.1 sec. future (231 ns) - */ -#define ESC_SYNCO_ACT_NFC_MASK (0x40U) -#define ESC_SYNCO_ACT_NFC_SHIFT (6U) -#define ESC_SYNCO_ACT_NFC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_NFC_SHIFT) & ESC_SYNCO_ACT_NFC_MASK) -#define ESC_SYNCO_ACT_NFC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_NFC_MASK) >> ESC_SYNCO_ACT_NFC_SHIFT) - -/* - * STPC (RW) - * - * Start Time plausibility check: - * 0:Disabled. SyncSignal generation if Start - * Time is reached. - * 1:Immediate SyncSignal generation if - * Start Time is outside near future (see - * 0x0981[6]) - */ -#define ESC_SYNCO_ACT_STPC_MASK (0x20U) -#define ESC_SYNCO_ACT_STPC_SHIFT (5U) -#define ESC_SYNCO_ACT_STPC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_STPC_SHIFT) & ESC_SYNCO_ACT_STPC_MASK) -#define ESC_SYNCO_ACT_STPC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_STPC_MASK) >> ESC_SYNCO_ACT_STPC_SHIFT) - -/* - * EXT (RW) - * - * Extension of Start Time Cyclic Operation - * (0x0990:0x0993): - * 0:No extension - * 1:Extend 32 bit written Start Time to 64 bit - */ -#define ESC_SYNCO_ACT_EXT_MASK (0x10U) -#define ESC_SYNCO_ACT_EXT_SHIFT (4U) -#define ESC_SYNCO_ACT_EXT_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_EXT_SHIFT) & ESC_SYNCO_ACT_EXT_MASK) -#define ESC_SYNCO_ACT_EXT_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_EXT_MASK) >> ESC_SYNCO_ACT_EXT_SHIFT) - -/* - * AC (RW) - * - * Auto-activation by writing Start Time Cyclic - * Operation (0x0990:0x0997): - * 0:Disabled - * 1:Auto-activation enabled. 0x0981[0] is - * set automatically after Start Time is - * written. - */ -#define ESC_SYNCO_ACT_AC_MASK (0x8U) -#define ESC_SYNCO_ACT_AC_SHIFT (3U) -#define ESC_SYNCO_ACT_AC_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_AC_SHIFT) & ESC_SYNCO_ACT_AC_MASK) -#define ESC_SYNCO_ACT_AC_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_AC_MASK) >> ESC_SYNCO_ACT_AC_SHIFT) - -/* - * SYNC1_GEN (RW) - * - * SYNC1 generation: - * 0:Deactivated - * 1:SYNC1 pulse is generated - */ -#define ESC_SYNCO_ACT_SYNC1_GEN_MASK (0x4U) -#define ESC_SYNCO_ACT_SYNC1_GEN_SHIFT (2U) -#define ESC_SYNCO_ACT_SYNC1_GEN_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SYNC1_GEN_SHIFT) & ESC_SYNCO_ACT_SYNC1_GEN_MASK) -#define ESC_SYNCO_ACT_SYNC1_GEN_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SYNC1_GEN_MASK) >> ESC_SYNCO_ACT_SYNC1_GEN_SHIFT) - -/* - * SYNC0_GEN (RW) - * - * SYNC0 generation: - * 0:Deactivated - * 1:SYNC0 pulse is generated - */ -#define ESC_SYNCO_ACT_SYNC0_GEN_MASK (0x2U) -#define ESC_SYNCO_ACT_SYNC0_GEN_SHIFT (1U) -#define ESC_SYNCO_ACT_SYNC0_GEN_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SYNC0_GEN_SHIFT) & ESC_SYNCO_ACT_SYNC0_GEN_MASK) -#define ESC_SYNCO_ACT_SYNC0_GEN_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SYNC0_GEN_MASK) >> ESC_SYNCO_ACT_SYNC0_GEN_SHIFT) - -/* - * SOUA (RW) - * - * Sync Out Unit activation: - * 0:Deactivated - * 1:Activated - */ -#define ESC_SYNCO_ACT_SOUA_MASK (0x1U) -#define ESC_SYNCO_ACT_SOUA_SHIFT (0U) -#define ESC_SYNCO_ACT_SOUA_SET(x) (((uint8_t)(x) << ESC_SYNCO_ACT_SOUA_SHIFT) & ESC_SYNCO_ACT_SOUA_MASK) -#define ESC_SYNCO_ACT_SOUA_GET(x) (((uint8_t)(x) & ESC_SYNCO_ACT_SOUA_MASK) >> ESC_SYNCO_ACT_SOUA_SHIFT) - -/* Bitfield definition for register: PULSE_LEN */ -/* - * LEN (RO) - * - * Pulse length of SyncSignals (in Units of - * 10ns) - * 0:Acknowledge mode:SyncSignal will be - * cleared by reading SYNC[1:0] Status - * register - */ -#define ESC_PULSE_LEN_LEN_MASK (0xFFFFU) -#define ESC_PULSE_LEN_LEN_SHIFT (0U) -#define ESC_PULSE_LEN_LEN_GET(x) (((uint16_t)(x) & ESC_PULSE_LEN_LEN_MASK) >> ESC_PULSE_LEN_LEN_SHIFT) - -/* Bitfield definition for register: ACT_STAT */ -/* - * CHK_RSLT (RO) - * - * Start Time Cyclic Operation (0x0990:0x0997) - * plausibility check result when Sync Out Unit - * was activated: - * 0:Start Time was within near future - * 1:Start Time was out of near future - * (0x0981[6]) - */ -#define ESC_ACT_STAT_CHK_RSLT_MASK (0x4U) -#define ESC_ACT_STAT_CHK_RSLT_SHIFT (2U) -#define ESC_ACT_STAT_CHK_RSLT_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_CHK_RSLT_MASK) >> ESC_ACT_STAT_CHK_RSLT_SHIFT) - -/* - * SYNC1 (RO) - * - * SYNC1 activation state: - * 0:First SYNC1 pulse is not pending - * 1:First SYNC1 pulse is pending - */ -#define ESC_ACT_STAT_SYNC1_MASK (0x2U) -#define ESC_ACT_STAT_SYNC1_SHIFT (1U) -#define ESC_ACT_STAT_SYNC1_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_SYNC1_MASK) >> ESC_ACT_STAT_SYNC1_SHIFT) - -/* - * SYNC0 (RO) - * - * SYNC0 activation state: - * 0:First SYNC0 pulse is not pending - * 1:First SYNC0 pulse is pending - */ -#define ESC_ACT_STAT_SYNC0_MASK (0x1U) -#define ESC_ACT_STAT_SYNC0_SHIFT (0U) -#define ESC_ACT_STAT_SYNC0_GET(x) (((uint8_t)(x) & ESC_ACT_STAT_SYNC0_MASK) >> ESC_ACT_STAT_SYNC0_SHIFT) - -/* Bitfield definition for register: SYNC0_STAT */ -/* - * ACK (RW) - * - * SYNC0 state for Acknowledge mode. - * SYNC0 in Acknowledge mode is cleared by - * reading this register from PDI, use only in - * Acknowledge mode - */ -#define ESC_SYNC0_STAT_ACK_MASK (0x1U) -#define ESC_SYNC0_STAT_ACK_SHIFT (0U) -#define ESC_SYNC0_STAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNC0_STAT_ACK_SHIFT) & ESC_SYNC0_STAT_ACK_MASK) -#define ESC_SYNC0_STAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNC0_STAT_ACK_MASK) >> ESC_SYNC0_STAT_ACK_SHIFT) - -/* Bitfield definition for register: SYNC1_STAT */ -/* - * ACK (RW) - * - * SYNC1 state for Acknowledge mode. - * SYNC1 in Acknowledge mode is cleared by - * reading this register from PDI, use only in - * Acknowledge mode - */ -#define ESC_SYNC1_STAT_ACK_MASK (0x1U) -#define ESC_SYNC1_STAT_ACK_SHIFT (0U) -#define ESC_SYNC1_STAT_ACK_SET(x) (((uint8_t)(x) << ESC_SYNC1_STAT_ACK_SHIFT) & ESC_SYNC1_STAT_ACK_MASK) -#define ESC_SYNC1_STAT_ACK_GET(x) (((uint8_t)(x) & ESC_SYNC1_STAT_ACK_MASK) >> ESC_SYNC1_STAT_ACK_SHIFT) - -/* Bitfield definition for register: START_TIME_CO */ -/* - * ST (RW) - * - * Write:Start time (System time) of cyclic - * operation in ns - * Read:System time of next SYNC0 pulse in - * ns - */ -#define ESC_START_TIME_CO_ST_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_START_TIME_CO_ST_SHIFT (0U) -#define ESC_START_TIME_CO_ST_SET(x) (((uint64_t)(x) << ESC_START_TIME_CO_ST_SHIFT) & ESC_START_TIME_CO_ST_MASK) -#define ESC_START_TIME_CO_ST_GET(x) (((uint64_t)(x) & ESC_START_TIME_CO_ST_MASK) >> ESC_START_TIME_CO_ST_SHIFT) - -/* Bitfield definition for register: NXT_SYNC1_PULSE */ -/* - * TIME (RO) - * - * System time of next SYNC1 pulse in ns - */ -#define ESC_NXT_SYNC1_PULSE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_NXT_SYNC1_PULSE_TIME_SHIFT (0U) -#define ESC_NXT_SYNC1_PULSE_TIME_GET(x) (((uint64_t)(x) & ESC_NXT_SYNC1_PULSE_TIME_MASK) >> ESC_NXT_SYNC1_PULSE_TIME_SHIFT) - -/* Bitfield definition for register: SYNC0_CYC_TIME */ -/* - * CYC (RW) - * - * Time between two consecutive SYNC0 - * pulses in ns. - * 0:Single shot mode, generate only one - * SYNC0 pulse. - */ -#define ESC_SYNC0_CYC_TIME_CYC_MASK (0xFFFFFFFFUL) -#define ESC_SYNC0_CYC_TIME_CYC_SHIFT (0U) -#define ESC_SYNC0_CYC_TIME_CYC_SET(x) (((uint32_t)(x) << ESC_SYNC0_CYC_TIME_CYC_SHIFT) & ESC_SYNC0_CYC_TIME_CYC_MASK) -#define ESC_SYNC0_CYC_TIME_CYC_GET(x) (((uint32_t)(x) & ESC_SYNC0_CYC_TIME_CYC_MASK) >> ESC_SYNC0_CYC_TIME_CYC_SHIFT) - -/* Bitfield definition for register: SYNC1_CYC_TIME */ -/* - * CYC (RW) - * - * Time between SYNC0 pulse and SYNC1 - * pulse in ns - */ -#define ESC_SYNC1_CYC_TIME_CYC_MASK (0xFFFFFFFFUL) -#define ESC_SYNC1_CYC_TIME_CYC_SHIFT (0U) -#define ESC_SYNC1_CYC_TIME_CYC_SET(x) (((uint32_t)(x) << ESC_SYNC1_CYC_TIME_CYC_SHIFT) & ESC_SYNC1_CYC_TIME_CYC_MASK) -#define ESC_SYNC1_CYC_TIME_CYC_GET(x) (((uint32_t)(x) & ESC_SYNC1_CYC_TIME_CYC_MASK) >> ESC_SYNC1_CYC_TIME_CYC_SHIFT) - -/* Bitfield definition for register: LATCH0_CTRL */ -/* - * NEG_EDGE (RW) - * - * Latch0 negative edge: - * 0:Continuous Latch active - * 1:Single event (only first event active) - */ -#define ESC_LATCH0_CTRL_NEG_EDGE_MASK (0x2U) -#define ESC_LATCH0_CTRL_NEG_EDGE_SHIFT (1U) -#define ESC_LATCH0_CTRL_NEG_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH0_CTRL_NEG_EDGE_SHIFT) & ESC_LATCH0_CTRL_NEG_EDGE_MASK) -#define ESC_LATCH0_CTRL_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_CTRL_NEG_EDGE_MASK) >> ESC_LATCH0_CTRL_NEG_EDGE_SHIFT) - -/* - * POS_EDGE (RW) - * - * Latch0 positive edge: - * 0:Continuous Latch active - * 1:Single event (only first event active) - */ -#define ESC_LATCH0_CTRL_POS_EDGE_MASK (0x1U) -#define ESC_LATCH0_CTRL_POS_EDGE_SHIFT (0U) -#define ESC_LATCH0_CTRL_POS_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH0_CTRL_POS_EDGE_SHIFT) & ESC_LATCH0_CTRL_POS_EDGE_MASK) -#define ESC_LATCH0_CTRL_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_CTRL_POS_EDGE_MASK) >> ESC_LATCH0_CTRL_POS_EDGE_SHIFT) - -/* Bitfield definition for register: LATCH1_CTRL */ -/* - * NEG_EDGE (RW) - * - * Latch1 negative edge: - * 0:Continuous Latch active - * 1:Single event (only first event active) - */ -#define ESC_LATCH1_CTRL_NEG_EDGE_MASK (0x2U) -#define ESC_LATCH1_CTRL_NEG_EDGE_SHIFT (1U) -#define ESC_LATCH1_CTRL_NEG_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH1_CTRL_NEG_EDGE_SHIFT) & ESC_LATCH1_CTRL_NEG_EDGE_MASK) -#define ESC_LATCH1_CTRL_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_CTRL_NEG_EDGE_MASK) >> ESC_LATCH1_CTRL_NEG_EDGE_SHIFT) - -/* - * POS_EDGE (RW) - * - * Latch1 positive edge: - * 0:Continuous Latch active - * 1:Single event (only first event active) - */ -#define ESC_LATCH1_CTRL_POS_EDGE_MASK (0x1U) -#define ESC_LATCH1_CTRL_POS_EDGE_SHIFT (0U) -#define ESC_LATCH1_CTRL_POS_EDGE_SET(x) (((uint8_t)(x) << ESC_LATCH1_CTRL_POS_EDGE_SHIFT) & ESC_LATCH1_CTRL_POS_EDGE_MASK) -#define ESC_LATCH1_CTRL_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_CTRL_POS_EDGE_MASK) >> ESC_LATCH1_CTRL_POS_EDGE_SHIFT) - -/* Bitfield definition for register: LATCH0_STAT */ -/* - * PIN_STAT (RO) - * - * Latch0 pin state - */ -#define ESC_LATCH0_STAT_PIN_STAT_MASK (0x4U) -#define ESC_LATCH0_STAT_PIN_STAT_SHIFT (2U) -#define ESC_LATCH0_STAT_PIN_STAT_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_PIN_STAT_MASK) >> ESC_LATCH0_STAT_PIN_STAT_SHIFT) - -/* - * NEG_EDGE (RO) - * - * Event Latch0 negative edge. - * 0:Negative edge not detected or - * continuous mode - * 1:Negative edge detected in single event - * mode only. - * Flag cleared by reading out Latch0 Time - * Negative Edge. - */ -#define ESC_LATCH0_STAT_NEG_EDGE_MASK (0x2U) -#define ESC_LATCH0_STAT_NEG_EDGE_SHIFT (1U) -#define ESC_LATCH0_STAT_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_NEG_EDGE_MASK) >> ESC_LATCH0_STAT_NEG_EDGE_SHIFT) - -/* - * POS_EDGE (RO) - * - * Event Latch0 positive edge. - * 0:Positive edge not detected or - * continuous mode - * 1:Positive edge detected in single event - * mode only. - * Flag cleared by reading out Latch0 Time - * Positive Edge. - */ -#define ESC_LATCH0_STAT_POS_EDGE_MASK (0x1U) -#define ESC_LATCH0_STAT_POS_EDGE_SHIFT (0U) -#define ESC_LATCH0_STAT_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH0_STAT_POS_EDGE_MASK) >> ESC_LATCH0_STAT_POS_EDGE_SHIFT) - -/* Bitfield definition for register: LATCH1_STAT */ -/* - * PIN_STAT (RO) - * - * Latch1 pin state - */ -#define ESC_LATCH1_STAT_PIN_STAT_MASK (0x4U) -#define ESC_LATCH1_STAT_PIN_STAT_SHIFT (2U) -#define ESC_LATCH1_STAT_PIN_STAT_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_PIN_STAT_MASK) >> ESC_LATCH1_STAT_PIN_STAT_SHIFT) - -/* - * NEG_EDGE (RO) - * - * Event Latch1 negative edge. - * 0:Negative edge not detected or - * continuous mode - * 1:Negative edge detected in single event - * mode only. - * Flag cleared by reading out Latch1 Time - * Negative Edge. - */ -#define ESC_LATCH1_STAT_NEG_EDGE_MASK (0x2U) -#define ESC_LATCH1_STAT_NEG_EDGE_SHIFT (1U) -#define ESC_LATCH1_STAT_NEG_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_NEG_EDGE_MASK) >> ESC_LATCH1_STAT_NEG_EDGE_SHIFT) - -/* - * POS_EDGE (RO) - * - * Event Latch1 positive edge. - * 0:Positive edge not detected or - * continuous mode - * 1:Positive edge detected in single event - * mode only. - * Flag cleared by reading out Latch1 Time - * Positive Edge. - */ -#define ESC_LATCH1_STAT_POS_EDGE_MASK (0x1U) -#define ESC_LATCH1_STAT_POS_EDGE_SHIFT (0U) -#define ESC_LATCH1_STAT_POS_EDGE_GET(x) (((uint8_t)(x) & ESC_LATCH1_STAT_POS_EDGE_MASK) >> ESC_LATCH1_STAT_POS_EDGE_SHIFT) - -/* Bitfield definition for register: LATCH0_TIME_PE */ -/* - * TIME (RW) - * - * System time at the positive edge of the - * Latch0 signal. - */ -#define ESC_LATCH0_TIME_PE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_LATCH0_TIME_PE_TIME_SHIFT (0U) -#define ESC_LATCH0_TIME_PE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH0_TIME_PE_TIME_SHIFT) & ESC_LATCH0_TIME_PE_TIME_MASK) -#define ESC_LATCH0_TIME_PE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH0_TIME_PE_TIME_MASK) >> ESC_LATCH0_TIME_PE_TIME_SHIFT) - -/* Bitfield definition for register: LATCH0_TIME_NE */ -/* - * TIME (RW) - * - * System time at the negative edge of the - * Latch0 signal. - */ -#define ESC_LATCH0_TIME_NE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_LATCH0_TIME_NE_TIME_SHIFT (0U) -#define ESC_LATCH0_TIME_NE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH0_TIME_NE_TIME_SHIFT) & ESC_LATCH0_TIME_NE_TIME_MASK) -#define ESC_LATCH0_TIME_NE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH0_TIME_NE_TIME_MASK) >> ESC_LATCH0_TIME_NE_TIME_SHIFT) - -/* Bitfield definition for register: LATCH1_TIME_PE */ -/* - * TIME (RW) - * - * System time at the positive edge of the - * Latch1 signal. - */ -#define ESC_LATCH1_TIME_PE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_LATCH1_TIME_PE_TIME_SHIFT (0U) -#define ESC_LATCH1_TIME_PE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH1_TIME_PE_TIME_SHIFT) & ESC_LATCH1_TIME_PE_TIME_MASK) -#define ESC_LATCH1_TIME_PE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH1_TIME_PE_TIME_MASK) >> ESC_LATCH1_TIME_PE_TIME_SHIFT) - -/* Bitfield definition for register: LATCH1_TIME_NE */ -/* - * TIME (RW) - * - * System time at the negative edge of the - * Latch1 signal. - */ -#define ESC_LATCH1_TIME_NE_TIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_LATCH1_TIME_NE_TIME_SHIFT (0U) -#define ESC_LATCH1_TIME_NE_TIME_SET(x) (((uint64_t)(x) << ESC_LATCH1_TIME_NE_TIME_SHIFT) & ESC_LATCH1_TIME_NE_TIME_MASK) -#define ESC_LATCH1_TIME_NE_TIME_GET(x) (((uint64_t)(x) & ESC_LATCH1_TIME_NE_TIME_MASK) >> ESC_LATCH1_TIME_NE_TIME_SHIFT) - -/* Bitfield definition for register: ECAT_BUF_CET */ -/* - * TIME (RO) - * - * Local time at the beginning of the frame - * which causes at least one SyncManager to - * assert an ECAT event - */ -#define ESC_ECAT_BUF_CET_TIME_MASK (0xFFFFFFFFUL) -#define ESC_ECAT_BUF_CET_TIME_SHIFT (0U) -#define ESC_ECAT_BUF_CET_TIME_GET(x) (((uint32_t)(x) & ESC_ECAT_BUF_CET_TIME_MASK) >> ESC_ECAT_BUF_CET_TIME_SHIFT) - -/* Bitfield definition for register: PDI_BUF_SET */ -/* - * TIME (RO) - * - * Local time when at least one SyncManager - * asserts a PDI buffer start event - */ -#define ESC_PDI_BUF_SET_TIME_MASK (0xFFFFFFFFUL) -#define ESC_PDI_BUF_SET_TIME_SHIFT (0U) -#define ESC_PDI_BUF_SET_TIME_GET(x) (((uint32_t)(x) & ESC_PDI_BUF_SET_TIME_MASK) >> ESC_PDI_BUF_SET_TIME_SHIFT) - -/* Bitfield definition for register: PDI_BUF_CET */ -/* - * TIME (RO) - * - * Local time when at least one SyncManager - * asserts a PDI buffer change event - */ -#define ESC_PDI_BUF_CET_TIME_MASK (0xFFFFFFFFUL) -#define ESC_PDI_BUF_CET_TIME_SHIFT (0U) -#define ESC_PDI_BUF_CET_TIME_GET(x) (((uint32_t)(x) & ESC_PDI_BUF_CET_TIME_MASK) >> ESC_PDI_BUF_CET_TIME_SHIFT) - -/* Bitfield definition for register: PID */ -/* - * PID (RO) - * - * Product ID - */ -#define ESC_PID_PID_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_PID_PID_SHIFT (0U) -#define ESC_PID_PID_GET(x) (((uint64_t)(x) & ESC_PID_PID_MASK) >> ESC_PID_PID_SHIFT) - -/* Bitfield definition for register: VID */ -/* - * VID (RO) - * - * Vendor ID: - * [23-0] Company - * [31-24] Department - * NOTE:Test Vendor IDs have [31:28]=0xE - */ -#define ESC_VID_VID_MASK (0xFFFFFFFFUL) -#define ESC_VID_VID_SHIFT (0U) -#define ESC_VID_VID_GET(x) (((uint64_t)(x) & ESC_VID_VID_MASK) >> ESC_VID_VID_SHIFT) - -/* Bitfield definition for register: DIO_OUT_DATA */ -/* - * OD (RO) - * - * Output Data - */ -#define ESC_DIO_OUT_DATA_OD_MASK (0xFFFFFFFFUL) -#define ESC_DIO_OUT_DATA_OD_SHIFT (0U) -#define ESC_DIO_OUT_DATA_OD_GET(x) (((uint32_t)(x) & ESC_DIO_OUT_DATA_OD_MASK) >> ESC_DIO_OUT_DATA_OD_SHIFT) - -/* Bitfield definition for register: GPO */ -/* - * GPOD (RW) - * - * General Purpose Output Data - */ -#define ESC_GPO_GPOD_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_GPO_GPOD_SHIFT (0U) -#define ESC_GPO_GPOD_SET(x) (((uint64_t)(x) << ESC_GPO_GPOD_SHIFT) & ESC_GPO_GPOD_MASK) -#define ESC_GPO_GPOD_GET(x) (((uint64_t)(x) & ESC_GPO_GPOD_MASK) >> ESC_GPO_GPOD_SHIFT) - -/* Bitfield definition for register: GPI */ -/* - * GPID (RO) - * - * General Purpose Input Data - */ -#define ESC_GPI_GPID_MASK (0xFFFFFFFFFFFFFFFFULL) -#define ESC_GPI_GPID_SHIFT (0U) -#define ESC_GPI_GPID_GET(x) (((uint64_t)(x) & ESC_GPI_GPID_MASK) >> ESC_GPI_GPID_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE0 */ -/* - * EXTF (RW) - * - * Number of extended feature bits - */ -#define ESC_USER_RAM_BYTE0_EXTF_MASK (0xFFU) -#define ESC_USER_RAM_BYTE0_EXTF_SHIFT (0U) -#define ESC_USER_RAM_BYTE0_EXTF_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE0_EXTF_SHIFT) & ESC_USER_RAM_BYTE0_EXTF_MASK) -#define ESC_USER_RAM_BYTE0_EXTF_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE0_EXTF_MASK) >> ESC_USER_RAM_BYTE0_EXTF_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE1 */ -/* - * PRWO (RW) - * - * Physical Read/Write Offset (0x0108:0x0109) - */ -#define ESC_USER_RAM_BYTE1_PRWO_MASK (0x80U) -#define ESC_USER_RAM_BYTE1_PRWO_SHIFT (7U) -#define ESC_USER_RAM_BYTE1_PRWO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_PRWO_SHIFT) & ESC_USER_RAM_BYTE1_PRWO_MASK) -#define ESC_USER_RAM_BYTE1_PRWO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_PRWO_MASK) >> ESC_USER_RAM_BYTE1_PRWO_SHIFT) - -/* - * AEMW (RW) - * - * AL Event Mask writable (0x0204:0x0207) - */ -#define ESC_USER_RAM_BYTE1_AEMW_MASK (0x40U) -#define ESC_USER_RAM_BYTE1_AEMW_SHIFT (6U) -#define ESC_USER_RAM_BYTE1_AEMW_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_AEMW_SHIFT) & ESC_USER_RAM_BYTE1_AEMW_MASK) -#define ESC_USER_RAM_BYTE1_AEMW_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_AEMW_MASK) >> ESC_USER_RAM_BYTE1_AEMW_SHIFT) - -/* - * GPO (RW) - * - * General Purpose Outputs (0x0F10:0x0F17) - */ -#define ESC_USER_RAM_BYTE1_GPO_MASK (0x20U) -#define ESC_USER_RAM_BYTE1_GPO_SHIFT (5U) -#define ESC_USER_RAM_BYTE1_GPO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_GPO_SHIFT) & ESC_USER_RAM_BYTE1_GPO_MASK) -#define ESC_USER_RAM_BYTE1_GPO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_GPO_MASK) >> ESC_USER_RAM_BYTE1_GPO_SHIFT) - -/* - * GPI (RW) - * - * General Purpose Inputs (0x0F18:0x0F1F) - */ -#define ESC_USER_RAM_BYTE1_GPI_MASK (0x10U) -#define ESC_USER_RAM_BYTE1_GPI_SHIFT (4U) -#define ESC_USER_RAM_BYTE1_GPI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_GPI_SHIFT) & ESC_USER_RAM_BYTE1_GPI_MASK) -#define ESC_USER_RAM_BYTE1_GPI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_GPI_MASK) >> ESC_USER_RAM_BYTE1_GPI_SHIFT) - -/* - * CSA (RW) - * - * Configured Station Alias (0x0012:0x0013) - */ -#define ESC_USER_RAM_BYTE1_CSA_MASK (0x8U) -#define ESC_USER_RAM_BYTE1_CSA_SHIFT (3U) -#define ESC_USER_RAM_BYTE1_CSA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_CSA_SHIFT) & ESC_USER_RAM_BYTE1_CSA_MASK) -#define ESC_USER_RAM_BYTE1_CSA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_CSA_MASK) >> ESC_USER_RAM_BYTE1_CSA_SHIFT) - -/* - * EIM (RW) - * - * ECAT Interrupt Mask (0x0200:0x0201) - */ -#define ESC_USER_RAM_BYTE1_EIM_MASK (0x4U) -#define ESC_USER_RAM_BYTE1_EIM_SHIFT (2U) -#define ESC_USER_RAM_BYTE1_EIM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_EIM_SHIFT) & ESC_USER_RAM_BYTE1_EIM_MASK) -#define ESC_USER_RAM_BYTE1_EIM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_EIM_MASK) >> ESC_USER_RAM_BYTE1_EIM_SHIFT) - -/* - * ALSCR (RW) - * - * AL Status Code Register (0x0134:0x0135) - */ -#define ESC_USER_RAM_BYTE1_ALSCR_MASK (0x2U) -#define ESC_USER_RAM_BYTE1_ALSCR_SHIFT (1U) -#define ESC_USER_RAM_BYTE1_ALSCR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_ALSCR_SHIFT) & ESC_USER_RAM_BYTE1_ALSCR_MASK) -#define ESC_USER_RAM_BYTE1_ALSCR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_ALSCR_MASK) >> ESC_USER_RAM_BYTE1_ALSCR_SHIFT) - -/* - * EDLCR (RW) - * - * Extended DL Control Register (0x0102:0x0103) - */ -#define ESC_USER_RAM_BYTE1_EDLCR_MASK (0x1U) -#define ESC_USER_RAM_BYTE1_EDLCR_SHIFT (0U) -#define ESC_USER_RAM_BYTE1_EDLCR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE1_EDLCR_SHIFT) & ESC_USER_RAM_BYTE1_EDLCR_MASK) -#define ESC_USER_RAM_BYTE1_EDLCR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE1_EDLCR_MASK) >> ESC_USER_RAM_BYTE1_EDLCR_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE2 */ -/* - * ESCFG (RW) - * - * EEPROM Size configurable (0x0502[7]): - * 0:EEPROM Size fixed to sizes up to 16 Kbit - * 1:EEPROM Size configurable - */ -#define ESC_USER_RAM_BYTE2_ESCFG_MASK (0x80U) -#define ESC_USER_RAM_BYTE2_ESCFG_SHIFT (7U) -#define ESC_USER_RAM_BYTE2_ESCFG_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_ESCFG_SHIFT) & ESC_USER_RAM_BYTE2_ESCFG_MASK) -#define ESC_USER_RAM_BYTE2_ESCFG_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_ESCFG_MASK) >> ESC_USER_RAM_BYTE2_ESCFG_SHIFT) - -/* - * EPUPEC (RW) - * - * ECAT Processing Unit/PDI Error Counter - * (0x030C:0x030D) - */ -#define ESC_USER_RAM_BYTE2_EPUPEC_MASK (0x40U) -#define ESC_USER_RAM_BYTE2_EPUPEC_SHIFT (6U) -#define ESC_USER_RAM_BYTE2_EPUPEC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_EPUPEC_SHIFT) & ESC_USER_RAM_BYTE2_EPUPEC_MASK) -#define ESC_USER_RAM_BYTE2_EPUPEC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_EPUPEC_MASK) >> ESC_USER_RAM_BYTE2_EPUPEC_SHIFT) - -/* - * DCSMET (RW) - * - * DC SyncManager Event Times (0x09F0:0x09FF) - */ -#define ESC_USER_RAM_BYTE2_DCSMET_MASK (0x20U) -#define ESC_USER_RAM_BYTE2_DCSMET_SHIFT (5U) -#define ESC_USER_RAM_BYTE2_DCSMET_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_DCSMET_SHIFT) & ESC_USER_RAM_BYTE2_DCSMET_MASK) -#define ESC_USER_RAM_BYTE2_DCSMET_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_DCSMET_MASK) >> ESC_USER_RAM_BYTE2_DCSMET_SHIFT) - -/* - * RESET (RW) - * - * Reset (0x0040:0x0041) - */ -#define ESC_USER_RAM_BYTE2_RESET_MASK (0x8U) -#define ESC_USER_RAM_BYTE2_RESET_SHIFT (3U) -#define ESC_USER_RAM_BYTE2_RESET_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_RESET_SHIFT) & ESC_USER_RAM_BYTE2_RESET_MASK) -#define ESC_USER_RAM_BYTE2_RESET_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_RESET_MASK) >> ESC_USER_RAM_BYTE2_RESET_SHIFT) - -/* - * WP (RW) - * - * Write Protection (0x0020:0x0031) - */ -#define ESC_USER_RAM_BYTE2_WP_MASK (0x4U) -#define ESC_USER_RAM_BYTE2_WP_SHIFT (2U) -#define ESC_USER_RAM_BYTE2_WP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WP_SHIFT) & ESC_USER_RAM_BYTE2_WP_MASK) -#define ESC_USER_RAM_BYTE2_WP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WP_MASK) >> ESC_USER_RAM_BYTE2_WP_SHIFT) - -/* - * WDGCNT (RW) - * - * Watchdog counters (0x0442:0x0443) - */ -#define ESC_USER_RAM_BYTE2_WDGCNT_MASK (0x2U) -#define ESC_USER_RAM_BYTE2_WDGCNT_SHIFT (1U) -#define ESC_USER_RAM_BYTE2_WDGCNT_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WDGCNT_SHIFT) & ESC_USER_RAM_BYTE2_WDGCNT_MASK) -#define ESC_USER_RAM_BYTE2_WDGCNT_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WDGCNT_MASK) >> ESC_USER_RAM_BYTE2_WDGCNT_SHIFT) - -/* - * WDW (RW) - * - * Watchdog divider writable (0x0400:0x0401) and - * Watchdog PDI (0x0410:0x0411) - */ -#define ESC_USER_RAM_BYTE2_WDW_MASK (0x1U) -#define ESC_USER_RAM_BYTE2_WDW_SHIFT (0U) -#define ESC_USER_RAM_BYTE2_WDW_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE2_WDW_SHIFT) & ESC_USER_RAM_BYTE2_WDW_MASK) -#define ESC_USER_RAM_BYTE2_WDW_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE2_WDW_MASK) >> ESC_USER_RAM_BYTE2_WDW_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE3 */ -/* - * RLED (RW) - * - * Run LED (DEV_STATE LED) - */ -#define ESC_USER_RAM_BYTE3_RLED_MASK (0x80U) -#define ESC_USER_RAM_BYTE3_RLED_SHIFT (7U) -#define ESC_USER_RAM_BYTE3_RLED_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_RLED_SHIFT) & ESC_USER_RAM_BYTE3_RLED_MASK) -#define ESC_USER_RAM_BYTE3_RLED_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_RLED_MASK) >> ESC_USER_RAM_BYTE3_RLED_SHIFT) - -/* - * ELDE (RW) - * - * Enhanced Link Detection EBUS - */ -#define ESC_USER_RAM_BYTE3_ELDE_MASK (0x40U) -#define ESC_USER_RAM_BYTE3_ELDE_SHIFT (6U) -#define ESC_USER_RAM_BYTE3_ELDE_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_ELDE_SHIFT) & ESC_USER_RAM_BYTE3_ELDE_MASK) -#define ESC_USER_RAM_BYTE3_ELDE_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_ELDE_MASK) >> ESC_USER_RAM_BYTE3_ELDE_SHIFT) - -/* - * ELDM (RW) - * - * Enhanced Link Detection MII - */ -#define ESC_USER_RAM_BYTE3_ELDM_MASK (0x20U) -#define ESC_USER_RAM_BYTE3_ELDM_SHIFT (5U) -#define ESC_USER_RAM_BYTE3_ELDM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_ELDM_SHIFT) & ESC_USER_RAM_BYTE3_ELDM_MASK) -#define ESC_USER_RAM_BYTE3_ELDM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_ELDM_MASK) >> ESC_USER_RAM_BYTE3_ELDM_SHIFT) - -/* - * MMI (RW) - * - * MII Management Interface (0x0510:0x0515) - */ -#define ESC_USER_RAM_BYTE3_MMI_MASK (0x10U) -#define ESC_USER_RAM_BYTE3_MMI_SHIFT (4U) -#define ESC_USER_RAM_BYTE3_MMI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_MMI_SHIFT) & ESC_USER_RAM_BYTE3_MMI_MASK) -#define ESC_USER_RAM_BYTE3_MMI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_MMI_MASK) >> ESC_USER_RAM_BYTE3_MMI_SHIFT) - -/* - * LLC (RW) - * - * Lost Link Counter (0x0310:0x0313) - */ -#define ESC_USER_RAM_BYTE3_LLC_MASK (0x8U) -#define ESC_USER_RAM_BYTE3_LLC_SHIFT (3U) -#define ESC_USER_RAM_BYTE3_LLC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE3_LLC_SHIFT) & ESC_USER_RAM_BYTE3_LLC_MASK) -#define ESC_USER_RAM_BYTE3_LLC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE3_LLC_MASK) >> ESC_USER_RAM_BYTE3_LLC_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE4 */ -/* - * LDCM (RW) - * - * Link detection and configuration by MI - */ -#define ESC_USER_RAM_BYTE4_LDCM_MASK (0x80U) -#define ESC_USER_RAM_BYTE4_LDCM_SHIFT (7U) -#define ESC_USER_RAM_BYTE4_LDCM_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_LDCM_SHIFT) & ESC_USER_RAM_BYTE4_LDCM_MASK) -#define ESC_USER_RAM_BYTE4_LDCM_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_LDCM_MASK) >> ESC_USER_RAM_BYTE4_LDCM_SHIFT) - -/* - * DTLC (RW) - * - * DC Time loop control assigned to PDI - */ -#define ESC_USER_RAM_BYTE4_DTLC_MASK (0x40U) -#define ESC_USER_RAM_BYTE4_DTLC_SHIFT (6U) -#define ESC_USER_RAM_BYTE4_DTLC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DTLC_SHIFT) & ESC_USER_RAM_BYTE4_DTLC_MASK) -#define ESC_USER_RAM_BYTE4_DTLC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DTLC_MASK) >> ESC_USER_RAM_BYTE4_DTLC_SHIFT) - -/* - * DSOU (RW) - * - * DC Sync Out Unit - */ -#define ESC_USER_RAM_BYTE4_DSOU_MASK (0x20U) -#define ESC_USER_RAM_BYTE4_DSOU_SHIFT (5U) -#define ESC_USER_RAM_BYTE4_DSOU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DSOU_SHIFT) & ESC_USER_RAM_BYTE4_DSOU_MASK) -#define ESC_USER_RAM_BYTE4_DSOU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DSOU_MASK) >> ESC_USER_RAM_BYTE4_DSOU_SHIFT) - -/* - * DLIU (RW) - * - * DC Latch In Unit - */ -#define ESC_USER_RAM_BYTE4_DLIU_MASK (0x8U) -#define ESC_USER_RAM_BYTE4_DLIU_SHIFT (3U) -#define ESC_USER_RAM_BYTE4_DLIU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_DLIU_SHIFT) & ESC_USER_RAM_BYTE4_DLIU_MASK) -#define ESC_USER_RAM_BYTE4_DLIU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_DLIU_MASK) >> ESC_USER_RAM_BYTE4_DLIU_SHIFT) - -/* - * LALED (RW) - * - * Link/Activity LED - */ -#define ESC_USER_RAM_BYTE4_LALED_MASK (0x1U) -#define ESC_USER_RAM_BYTE4_LALED_SHIFT (0U) -#define ESC_USER_RAM_BYTE4_LALED_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE4_LALED_SHIFT) & ESC_USER_RAM_BYTE4_LALED_MASK) -#define ESC_USER_RAM_BYTE4_LALED_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE4_LALED_MASK) >> ESC_USER_RAM_BYTE4_LALED_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE5 */ -/* - * DDIOR (RW) - * - * Disable Digital I/O register (0x0F00:0x0F03) - */ -#define ESC_USER_RAM_BYTE5_DDIOR_MASK (0x20U) -#define ESC_USER_RAM_BYTE5_DDIOR_SHIFT (5U) -#define ESC_USER_RAM_BYTE5_DDIOR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_DDIOR_SHIFT) & ESC_USER_RAM_BYTE5_DDIOR_MASK) -#define ESC_USER_RAM_BYTE5_DDIOR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_DDIOR_MASK) >> ESC_USER_RAM_BYTE5_DDIOR_SHIFT) - -/* - * EEU (RW) - * - * EEPROM emulation by µController - */ -#define ESC_USER_RAM_BYTE5_EEU_MASK (0x4U) -#define ESC_USER_RAM_BYTE5_EEU_SHIFT (2U) -#define ESC_USER_RAM_BYTE5_EEU_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_EEU_SHIFT) & ESC_USER_RAM_BYTE5_EEU_MASK) -#define ESC_USER_RAM_BYTE5_EEU_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_EEU_MASK) >> ESC_USER_RAM_BYTE5_EEU_SHIFT) - -/* - * ATS (RW) - * - * Automatic TX shift - */ -#define ESC_USER_RAM_BYTE5_ATS_MASK (0x2U) -#define ESC_USER_RAM_BYTE5_ATS_SHIFT (1U) -#define ESC_USER_RAM_BYTE5_ATS_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_ATS_SHIFT) & ESC_USER_RAM_BYTE5_ATS_MASK) -#define ESC_USER_RAM_BYTE5_ATS_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_ATS_MASK) >> ESC_USER_RAM_BYTE5_ATS_SHIFT) - -/* - * MCPP (RW) - * - * MI control by PDI possible - */ -#define ESC_USER_RAM_BYTE5_MCPP_MASK (0x1U) -#define ESC_USER_RAM_BYTE5_MCPP_SHIFT (0U) -#define ESC_USER_RAM_BYTE5_MCPP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE5_MCPP_SHIFT) & ESC_USER_RAM_BYTE5_MCPP_MASK) -#define ESC_USER_RAM_BYTE5_MCPP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE5_MCPP_MASK) >> ESC_USER_RAM_BYTE5_MCPP_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE6 */ -/* - * RELEDOR (RW) - * - * RUN/ERR LED Override (0x0138:0x0139) - */ -#define ESC_USER_RAM_BYTE6_RELEDOR_MASK (0x4U) -#define ESC_USER_RAM_BYTE6_RELEDOR_SHIFT (2U) -#define ESC_USER_RAM_BYTE6_RELEDOR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE6_RELEDOR_SHIFT) & ESC_USER_RAM_BYTE6_RELEDOR_MASK) -#define ESC_USER_RAM_BYTE6_RELEDOR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE6_RELEDOR_MASK) >> ESC_USER_RAM_BYTE6_RELEDOR_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE7 */ -/* - * DCST (RW) - * - * DC System Time (0x0910:0x0936) - */ -#define ESC_USER_RAM_BYTE7_DCST_MASK (0x80U) -#define ESC_USER_RAM_BYTE7_DCST_SHIFT (7U) -#define ESC_USER_RAM_BYTE7_DCST_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCST_SHIFT) & ESC_USER_RAM_BYTE7_DCST_MASK) -#define ESC_USER_RAM_BYTE7_DCST_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCST_MASK) >> ESC_USER_RAM_BYTE7_DCST_SHIFT) - -/* - * DCRT (RW) - * - * DC Receive Times (0x0900:0x090F) - */ -#define ESC_USER_RAM_BYTE7_DCRT_MASK (0x40U) -#define ESC_USER_RAM_BYTE7_DCRT_SHIFT (6U) -#define ESC_USER_RAM_BYTE7_DCRT_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCRT_SHIFT) & ESC_USER_RAM_BYTE7_DCRT_MASK) -#define ESC_USER_RAM_BYTE7_DCRT_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCRT_MASK) >> ESC_USER_RAM_BYTE7_DCRT_SHIFT) - -/* - * DCS1D (RW) - * - * DC Sync1 disable - */ -#define ESC_USER_RAM_BYTE7_DCS1D_MASK (0x8U) -#define ESC_USER_RAM_BYTE7_DCS1D_SHIFT (3U) -#define ESC_USER_RAM_BYTE7_DCS1D_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE7_DCS1D_SHIFT) & ESC_USER_RAM_BYTE7_DCS1D_MASK) -#define ESC_USER_RAM_BYTE7_DCS1D_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE7_DCS1D_MASK) >> ESC_USER_RAM_BYTE7_DCS1D_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE8 */ -/* - * PPDI (RW) - * - * PLB PDI - */ -#define ESC_USER_RAM_BYTE8_PPDI_MASK (0x20U) -#define ESC_USER_RAM_BYTE8_PPDI_SHIFT (5U) -#define ESC_USER_RAM_BYTE8_PPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_PPDI_SHIFT) & ESC_USER_RAM_BYTE8_PPDI_MASK) -#define ESC_USER_RAM_BYTE8_PPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_PPDI_MASK) >> ESC_USER_RAM_BYTE8_PPDI_SHIFT) - -/* - * OPDI (RW) - * - * OPB PDI - */ -#define ESC_USER_RAM_BYTE8_OPDI_MASK (0x10U) -#define ESC_USER_RAM_BYTE8_OPDI_SHIFT (4U) -#define ESC_USER_RAM_BYTE8_OPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_OPDI_SHIFT) & ESC_USER_RAM_BYTE8_OPDI_MASK) -#define ESC_USER_RAM_BYTE8_OPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_OPDI_MASK) >> ESC_USER_RAM_BYTE8_OPDI_SHIFT) - -/* - * APDI (RW) - * - * Avalon PDI - */ -#define ESC_USER_RAM_BYTE8_APDI_MASK (0x8U) -#define ESC_USER_RAM_BYTE8_APDI_SHIFT (3U) -#define ESC_USER_RAM_BYTE8_APDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_APDI_SHIFT) & ESC_USER_RAM_BYTE8_APDI_MASK) -#define ESC_USER_RAM_BYTE8_APDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_APDI_MASK) >> ESC_USER_RAM_BYTE8_APDI_SHIFT) - -/* - * PDICEC (RW) - * - * PDI clears error counter - */ -#define ESC_USER_RAM_BYTE8_PDICEC_MASK (0x4U) -#define ESC_USER_RAM_BYTE8_PDICEC_SHIFT (2U) -#define ESC_USER_RAM_BYTE8_PDICEC_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_PDICEC_SHIFT) & ESC_USER_RAM_BYTE8_PDICEC_MASK) -#define ESC_USER_RAM_BYTE8_PDICEC_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_PDICEC_MASK) >> ESC_USER_RAM_BYTE8_PDICEC_SHIFT) - -/* - * DC64 (RW) - * - * DC 64 bit - */ -#define ESC_USER_RAM_BYTE8_DC64_MASK (0x1U) -#define ESC_USER_RAM_BYTE8_DC64_SHIFT (0U) -#define ESC_USER_RAM_BYTE8_DC64_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE8_DC64_SHIFT) & ESC_USER_RAM_BYTE8_DC64_MASK) -#define ESC_USER_RAM_BYTE8_DC64_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE8_DC64_MASK) >> ESC_USER_RAM_BYTE8_DC64_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE9 */ -/* - * DR (RW) - * - * Direct RESET - */ -#define ESC_USER_RAM_BYTE9_DR_MASK (0x80U) -#define ESC_USER_RAM_BYTE9_DR_SHIFT (7U) -#define ESC_USER_RAM_BYTE9_DR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE9_DR_SHIFT) & ESC_USER_RAM_BYTE9_DR_MASK) -#define ESC_USER_RAM_BYTE9_DR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE9_DR_MASK) >> ESC_USER_RAM_BYTE9_DR_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE10 */ -/* - * PDIIR (RW) - * - * PDI Information register (0x014E:0x014F) - */ -#define ESC_USER_RAM_BYTE10_PDIIR_MASK (0x80U) -#define ESC_USER_RAM_BYTE10_PDIIR_SHIFT (7U) -#define ESC_USER_RAM_BYTE10_PDIIR_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_PDIIR_SHIFT) & ESC_USER_RAM_BYTE10_PDIIR_MASK) -#define ESC_USER_RAM_BYTE10_PDIIR_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_PDIIR_MASK) >> ESC_USER_RAM_BYTE10_PDIIR_SHIFT) - -/* - * PDIFA (RW) - * - * PDI function acknowledge by PDI write - */ -#define ESC_USER_RAM_BYTE10_PDIFA_MASK (0x40U) -#define ESC_USER_RAM_BYTE10_PDIFA_SHIFT (6U) -#define ESC_USER_RAM_BYTE10_PDIFA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_PDIFA_SHIFT) & ESC_USER_RAM_BYTE10_PDIFA_MASK) -#define ESC_USER_RAM_BYTE10_PDIFA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_PDIFA_MASK) >> ESC_USER_RAM_BYTE10_PDIFA_SHIFT) - -/* - * APDI (RW) - * - * AXI PDI - */ -#define ESC_USER_RAM_BYTE10_APDI_MASK (0x8U) -#define ESC_USER_RAM_BYTE10_APDI_SHIFT (3U) -#define ESC_USER_RAM_BYTE10_APDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_APDI_SHIFT) & ESC_USER_RAM_BYTE10_APDI_MASK) -#define ESC_USER_RAM_BYTE10_APDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_APDI_MASK) >> ESC_USER_RAM_BYTE10_APDI_SHIFT) - -/* - * DCL1D (RW) - * - * DC Latch1 disable - */ -#define ESC_USER_RAM_BYTE10_DCL1D_MASK (0x4U) -#define ESC_USER_RAM_BYTE10_DCL1D_SHIFT (2U) -#define ESC_USER_RAM_BYTE10_DCL1D_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE10_DCL1D_SHIFT) & ESC_USER_RAM_BYTE10_DCL1D_MASK) -#define ESC_USER_RAM_BYTE10_DCL1D_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE10_DCL1D_MASK) >> ESC_USER_RAM_BYTE10_DCL1D_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE11 */ -/* - * LEDTST (RW) - * - * LED test - */ -#define ESC_USER_RAM_BYTE11_LEDTST_MASK (0x8U) -#define ESC_USER_RAM_BYTE11_LEDTST_SHIFT (3U) -#define ESC_USER_RAM_BYTE11_LEDTST_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE11_LEDTST_SHIFT) & ESC_USER_RAM_BYTE11_LEDTST_MASK) -#define ESC_USER_RAM_BYTE11_LEDTST_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE11_LEDTST_MASK) >> ESC_USER_RAM_BYTE11_LEDTST_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE14 */ -/* - * DIOBS (RW) - * - * Digital I/O PDI byte size - */ -#define ESC_USER_RAM_BYTE14_DIOBS_MASK (0xC0U) -#define ESC_USER_RAM_BYTE14_DIOBS_SHIFT (6U) -#define ESC_USER_RAM_BYTE14_DIOBS_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE14_DIOBS_SHIFT) & ESC_USER_RAM_BYTE14_DIOBS_MASK) -#define ESC_USER_RAM_BYTE14_DIOBS_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE14_DIOBS_MASK) >> ESC_USER_RAM_BYTE14_DIOBS_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE15 */ -/* - * AUCPDI (RW) - * - * Asynchronous µC PDI - */ -#define ESC_USER_RAM_BYTE15_AUCPDI_MASK (0x10U) -#define ESC_USER_RAM_BYTE15_AUCPDI_SHIFT (4U) -#define ESC_USER_RAM_BYTE15_AUCPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_AUCPDI_SHIFT) & ESC_USER_RAM_BYTE15_AUCPDI_MASK) -#define ESC_USER_RAM_BYTE15_AUCPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_AUCPDI_MASK) >> ESC_USER_RAM_BYTE15_AUCPDI_SHIFT) - -/* - * SSPDI (RW) - * - * SPI Slave PDI - */ -#define ESC_USER_RAM_BYTE15_SSPDI_MASK (0x8U) -#define ESC_USER_RAM_BYTE15_SSPDI_SHIFT (3U) -#define ESC_USER_RAM_BYTE15_SSPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_SSPDI_SHIFT) & ESC_USER_RAM_BYTE15_SSPDI_MASK) -#define ESC_USER_RAM_BYTE15_SSPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_SSPDI_MASK) >> ESC_USER_RAM_BYTE15_SSPDI_SHIFT) - -/* - * DIOPDI (RW) - * - * Digital I/O PDI - */ -#define ESC_USER_RAM_BYTE15_DIOPDI_MASK (0x4U) -#define ESC_USER_RAM_BYTE15_DIOPDI_SHIFT (2U) -#define ESC_USER_RAM_BYTE15_DIOPDI_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE15_DIOPDI_SHIFT) & ESC_USER_RAM_BYTE15_DIOPDI_MASK) -#define ESC_USER_RAM_BYTE15_DIOPDI_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE15_DIOPDI_MASK) >> ESC_USER_RAM_BYTE15_DIOPDI_SHIFT) - -/* Bitfield definition for register: USER_RAM_BYTE19 */ -/* - * SCP (RW) - * - * Security CPLD protection - */ -#define ESC_USER_RAM_BYTE19_SCP_MASK (0x40U) -#define ESC_USER_RAM_BYTE19_SCP_SHIFT (6U) -#define ESC_USER_RAM_BYTE19_SCP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_SCP_SHIFT) & ESC_USER_RAM_BYTE19_SCP_MASK) -#define ESC_USER_RAM_BYTE19_SCP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_SCP_MASK) >> ESC_USER_RAM_BYTE19_SCP_SHIFT) - -/* - * RMII (RW) - * - * RMII - */ -#define ESC_USER_RAM_BYTE19_RMII_MASK (0x20U) -#define ESC_USER_RAM_BYTE19_RMII_SHIFT (5U) -#define ESC_USER_RAM_BYTE19_RMII_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_RMII_SHIFT) & ESC_USER_RAM_BYTE19_RMII_MASK) -#define ESC_USER_RAM_BYTE19_RMII_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_RMII_MASK) >> ESC_USER_RAM_BYTE19_RMII_SHIFT) - -/* - * URGP (RW) - * - * Use RGMII GTX_CLK phase shifted clock input - */ -#define ESC_USER_RAM_BYTE19_URGP_MASK (0x10U) -#define ESC_USER_RAM_BYTE19_URGP_SHIFT (4U) -#define ESC_USER_RAM_BYTE19_URGP_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_URGP_SHIFT) & ESC_USER_RAM_BYTE19_URGP_MASK) -#define ESC_USER_RAM_BYTE19_URGP_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_URGP_MASK) >> ESC_USER_RAM_BYTE19_URGP_SHIFT) - -/* - * CIA (RW) - * - * CLK_PDI_EXT is asynchronous - */ -#define ESC_USER_RAM_BYTE19_CIA_MASK (0x4U) -#define ESC_USER_RAM_BYTE19_CIA_SHIFT (2U) -#define ESC_USER_RAM_BYTE19_CIA_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_CIA_SHIFT) & ESC_USER_RAM_BYTE19_CIA_MASK) -#define ESC_USER_RAM_BYTE19_CIA_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_CIA_MASK) >> ESC_USER_RAM_BYTE19_CIA_SHIFT) - -/* - * IPARO (RW) - * - * Individual PHY address read out (0x0510[7:3]) - */ -#define ESC_USER_RAM_BYTE19_IPARO_MASK (0x2U) -#define ESC_USER_RAM_BYTE19_IPARO_SHIFT (1U) -#define ESC_USER_RAM_BYTE19_IPARO_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_IPARO_SHIFT) & ESC_USER_RAM_BYTE19_IPARO_MASK) -#define ESC_USER_RAM_BYTE19_IPARO_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_IPARO_MASK) >> ESC_USER_RAM_BYTE19_IPARO_SHIFT) - -/* - * RGMII (RW) - * - * RGMII - */ -#define ESC_USER_RAM_BYTE19_RGMII_MASK (0x1U) -#define ESC_USER_RAM_BYTE19_RGMII_SHIFT (0U) -#define ESC_USER_RAM_BYTE19_RGMII_SET(x) (((uint8_t)(x) << ESC_USER_RAM_BYTE19_RGMII_SHIFT) & ESC_USER_RAM_BYTE19_RGMII_MASK) -#define ESC_USER_RAM_BYTE19_RGMII_GET(x) (((uint8_t)(x) & ESC_USER_RAM_BYTE19_RGMII_MASK) >> ESC_USER_RAM_BYTE19_RGMII_SHIFT) - -/* Bitfield definition for register: PDRAM */ -/* - * DATA (RW) - * - * Input Data - */ -#define ESC_PDRAM_DATA_MASK (0xFFFFFFFFUL) -#define ESC_PDRAM_DATA_SHIFT (0U) -#define ESC_PDRAM_DATA_SET(x) (((uint32_t)(x) << ESC_PDRAM_DATA_SHIFT) & ESC_PDRAM_DATA_MASK) -#define ESC_PDRAM_DATA_GET(x) (((uint32_t)(x) & ESC_PDRAM_DATA_MASK) >> ESC_PDRAM_DATA_SHIFT) - -/* Bitfield definition for register: PDRAM_ALS */ -/* - * DATA (RW) - * - */ -#define ESC_PDRAM_ALS_DATA_MASK (0xFFFFFFFFUL) -#define ESC_PDRAM_ALS_DATA_SHIFT (0U) -#define ESC_PDRAM_ALS_DATA_SET(x) (((uint32_t)(x) << ESC_PDRAM_ALS_DATA_SHIFT) & ESC_PDRAM_ALS_DATA_MASK) -#define ESC_PDRAM_ALS_DATA_GET(x) (((uint32_t)(x) & ESC_PDRAM_ALS_DATA_MASK) >> ESC_PDRAM_ALS_DATA_SHIFT) - -/* Bitfield definition for register: GPR_CFG0 */ -/* - * CLK100_EN (RW) - * - */ -#define ESC_GPR_CFG0_CLK100_EN_MASK (0x2000U) -#define ESC_GPR_CFG0_CLK100_EN_SHIFT (13U) -#define ESC_GPR_CFG0_CLK100_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_CLK100_EN_SHIFT) & ESC_GPR_CFG0_CLK100_EN_MASK) -#define ESC_GPR_CFG0_CLK100_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_CLK100_EN_MASK) >> ESC_GPR_CFG0_CLK100_EN_SHIFT) - -/* - * EEPROM_EMU (RW) - * - * 1 is EEPROM emulation mode (default) - */ -#define ESC_GPR_CFG0_EEPROM_EMU_MASK (0x1000U) -#define ESC_GPR_CFG0_EEPROM_EMU_SHIFT (12U) -#define ESC_GPR_CFG0_EEPROM_EMU_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_EEPROM_EMU_SHIFT) & ESC_GPR_CFG0_EEPROM_EMU_MASK) -#define ESC_GPR_CFG0_EEPROM_EMU_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_EEPROM_EMU_MASK) >> ESC_GPR_CFG0_EEPROM_EMU_SHIFT) - -/* - * I2C_SCLK_EN (RW) - * - */ -#define ESC_GPR_CFG0_I2C_SCLK_EN_MASK (0x8U) -#define ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT (3U) -#define ESC_GPR_CFG0_I2C_SCLK_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT) & ESC_GPR_CFG0_I2C_SCLK_EN_MASK) -#define ESC_GPR_CFG0_I2C_SCLK_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_I2C_SCLK_EN_MASK) >> ESC_GPR_CFG0_I2C_SCLK_EN_SHIFT) - -/* - * PROM_SIZE (RW) - * - * Sets EEPROM size: - * 0:up to 16 kbit EEPROM - * 1:32 kbit-4Mbit EEPROM - */ -#define ESC_GPR_CFG0_PROM_SIZE_MASK (0x1U) -#define ESC_GPR_CFG0_PROM_SIZE_SHIFT (0U) -#define ESC_GPR_CFG0_PROM_SIZE_SET(x) (((uint32_t)(x) << ESC_GPR_CFG0_PROM_SIZE_SHIFT) & ESC_GPR_CFG0_PROM_SIZE_MASK) -#define ESC_GPR_CFG0_PROM_SIZE_GET(x) (((uint32_t)(x) & ESC_GPR_CFG0_PROM_SIZE_MASK) >> ESC_GPR_CFG0_PROM_SIZE_SHIFT) - -/* Bitfield definition for register: GPR_CFG1 */ -/* - * SYNC1_IRQ_EN (RW) - * - */ -#define ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK (0x80000000UL) -#define ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT (31U) -#define ESC_GPR_CFG1_SYNC1_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT) & ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK) -#define ESC_GPR_CFG1_SYNC1_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC1_IRQ_EN_MASK) >> ESC_GPR_CFG1_SYNC1_IRQ_EN_SHIFT) - -/* - * SYNC0_IRQ_EN (RW) - * - */ -#define ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK (0x40000000UL) -#define ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT (30U) -#define ESC_GPR_CFG1_SYNC0_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT) & ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK) -#define ESC_GPR_CFG1_SYNC0_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC0_IRQ_EN_MASK) >> ESC_GPR_CFG1_SYNC0_IRQ_EN_SHIFT) - -/* - * RSTO_IRQ_EN (RW) - * - */ -#define ESC_GPR_CFG1_RSTO_IRQ_EN_MASK (0x20000000UL) -#define ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT (29U) -#define ESC_GPR_CFG1_RSTO_IRQ_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT) & ESC_GPR_CFG1_RSTO_IRQ_EN_MASK) -#define ESC_GPR_CFG1_RSTO_IRQ_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_IRQ_EN_MASK) >> ESC_GPR_CFG1_RSTO_IRQ_EN_SHIFT) - -/* - * SYNC1_DMA_EN (RW) - * - */ -#define ESC_GPR_CFG1_SYNC1_DMA_EN_MASK (0x2000U) -#define ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT (13U) -#define ESC_GPR_CFG1_SYNC1_DMA_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT) & ESC_GPR_CFG1_SYNC1_DMA_EN_MASK) -#define ESC_GPR_CFG1_SYNC1_DMA_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC1_DMA_EN_MASK) >> ESC_GPR_CFG1_SYNC1_DMA_EN_SHIFT) - -/* - * SYNC0_DMA_EN (RW) - * - */ -#define ESC_GPR_CFG1_SYNC0_DMA_EN_MASK (0x1000U) -#define ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT (12U) -#define ESC_GPR_CFG1_SYNC0_DMA_EN_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT) & ESC_GPR_CFG1_SYNC0_DMA_EN_MASK) -#define ESC_GPR_CFG1_SYNC0_DMA_EN_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_SYNC0_DMA_EN_MASK) >> ESC_GPR_CFG1_SYNC0_DMA_EN_SHIFT) - -/* - * LATCH1_FROM_IO (RW) - * - * 0:from NTM - */ -#define ESC_GPR_CFG1_LATCH1_FROM_IO_MASK (0x200U) -#define ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT (9U) -#define ESC_GPR_CFG1_LATCH1_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT) & ESC_GPR_CFG1_LATCH1_FROM_IO_MASK) -#define ESC_GPR_CFG1_LATCH1_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_LATCH1_FROM_IO_MASK) >> ESC_GPR_CFG1_LATCH1_FROM_IO_SHIFT) - -/* - * LATCH0_FROM_IO (RW) - * - * 0:from TRIGGER_MUX - */ -#define ESC_GPR_CFG1_LATCH0_FROM_IO_MASK (0x100U) -#define ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT (8U) -#define ESC_GPR_CFG1_LATCH0_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT) & ESC_GPR_CFG1_LATCH0_FROM_IO_MASK) -#define ESC_GPR_CFG1_LATCH0_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_LATCH0_FROM_IO_MASK) >> ESC_GPR_CFG1_LATCH0_FROM_IO_SHIFT) - -/* - * RSTO_OVRD (RW) - * - */ -#define ESC_GPR_CFG1_RSTO_OVRD_MASK (0x80U) -#define ESC_GPR_CFG1_RSTO_OVRD_SHIFT (7U) -#define ESC_GPR_CFG1_RSTO_OVRD_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_OVRD_SHIFT) & ESC_GPR_CFG1_RSTO_OVRD_MASK) -#define ESC_GPR_CFG1_RSTO_OVRD_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_OVRD_MASK) >> ESC_GPR_CFG1_RSTO_OVRD_SHIFT) - -/* - * RSTO_OVRD_ENJ (RW) - * - */ -#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK (0x40U) -#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT (6U) -#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_SET(x) (((uint32_t)(x) << ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT) & ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK) -#define ESC_GPR_CFG1_RSTO_OVRD_ENJ_GET(x) (((uint32_t)(x) & ESC_GPR_CFG1_RSTO_OVRD_ENJ_MASK) >> ESC_GPR_CFG1_RSTO_OVRD_ENJ_SHIFT) - -/* Bitfield definition for register: GPR_CFG2 */ -/* - * NMII_LINK2_FROM_IO (RW) - * - */ -#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK (0x20000000UL) -#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT (29U) -#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK) -#define ESC_GPR_CFG2_NMII_LINK2_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK2_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK2_FROM_IO_SHIFT) - -/* - * NMII_LINK2_GPR (RW) - * - */ -#define ESC_GPR_CFG2_NMII_LINK2_GPR_MASK (0x10000000UL) -#define ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT (28U) -#define ESC_GPR_CFG2_NMII_LINK2_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK2_GPR_MASK) -#define ESC_GPR_CFG2_NMII_LINK2_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK2_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK2_GPR_SHIFT) - -/* - * NMII_LINK1_FROM_IO (RW) - * - */ -#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK (0x2000000UL) -#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT (25U) -#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK) -#define ESC_GPR_CFG2_NMII_LINK1_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK1_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK1_FROM_IO_SHIFT) - -/* - * NMII_LINK1_GPR (RW) - * - */ -#define ESC_GPR_CFG2_NMII_LINK1_GPR_MASK (0x1000000UL) -#define ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT (24U) -#define ESC_GPR_CFG2_NMII_LINK1_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK1_GPR_MASK) -#define ESC_GPR_CFG2_NMII_LINK1_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK1_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK1_GPR_SHIFT) - -/* - * NMII_LINK0_FROM_IO (RW) - * - */ -#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK (0x200000UL) -#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT (21U) -#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT) & ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK) -#define ESC_GPR_CFG2_NMII_LINK0_FROM_IO_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK0_FROM_IO_MASK) >> ESC_GPR_CFG2_NMII_LINK0_FROM_IO_SHIFT) - -/* - * NMII_LINK0_GPR (RW) - * - */ -#define ESC_GPR_CFG2_NMII_LINK0_GPR_MASK (0x100000UL) -#define ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT (20U) -#define ESC_GPR_CFG2_NMII_LINK0_GPR_SET(x) (((uint32_t)(x) << ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT) & ESC_GPR_CFG2_NMII_LINK0_GPR_MASK) -#define ESC_GPR_CFG2_NMII_LINK0_GPR_GET(x) (((uint32_t)(x) & ESC_GPR_CFG2_NMII_LINK0_GPR_MASK) >> ESC_GPR_CFG2_NMII_LINK0_GPR_SHIFT) - -/* Bitfield definition for register: PHY_CFG0 */ -/* - * MAC_SPEED (RW) - * - * 1:100M - */ -#define ESC_PHY_CFG0_MAC_SPEED_MASK (0x40000000UL) -#define ESC_PHY_CFG0_MAC_SPEED_SHIFT (30U) -#define ESC_PHY_CFG0_MAC_SPEED_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_MAC_SPEED_SHIFT) & ESC_PHY_CFG0_MAC_SPEED_MASK) -#define ESC_PHY_CFG0_MAC_SPEED_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_MAC_SPEED_MASK) >> ESC_PHY_CFG0_MAC_SPEED_SHIFT) - -/* - * PORT2_RMII_EN (RW) - * - */ -#define ESC_PHY_CFG0_PORT2_RMII_EN_MASK (0x800000UL) -#define ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT (23U) -#define ESC_PHY_CFG0_PORT2_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT2_RMII_EN_MASK) -#define ESC_PHY_CFG0_PORT2_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT2_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT2_RMII_EN_SHIFT) - -/* - * PORT1_RMII_EN (RW) - * - */ -#define ESC_PHY_CFG0_PORT1_RMII_EN_MASK (0x8000U) -#define ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT (15U) -#define ESC_PHY_CFG0_PORT1_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT1_RMII_EN_MASK) -#define ESC_PHY_CFG0_PORT1_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT1_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT1_RMII_EN_SHIFT) - -/* - * PORT0_RMII_EN (RW) - * - */ -#define ESC_PHY_CFG0_PORT0_RMII_EN_MASK (0x80U) -#define ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT (7U) -#define ESC_PHY_CFG0_PORT0_RMII_EN_SET(x) (((uint32_t)(x) << ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT) & ESC_PHY_CFG0_PORT0_RMII_EN_MASK) -#define ESC_PHY_CFG0_PORT0_RMII_EN_GET(x) (((uint32_t)(x) & ESC_PHY_CFG0_PORT0_RMII_EN_MASK) >> ESC_PHY_CFG0_PORT0_RMII_EN_SHIFT) - -/* Bitfield definition for register: PHY_CFG1 */ -/* - * RMII_REFCLK_SEL (RW) - * - * 0:use RXCK as 50M refclk. 1:use TXCK as 50M refclk - */ -#define ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK (0x700U) -#define ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT (8U) -#define ESC_PHY_CFG1_RMII_REFCLK_SEL_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT) & ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK) -#define ESC_PHY_CFG1_RMII_REFCLK_SEL_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_REFCLK_SEL_MASK) >> ESC_PHY_CFG1_RMII_REFCLK_SEL_SHIFT) - -/* - * REFCK_25M_INV (RW) - * - */ -#define ESC_PHY_CFG1_REFCK_25M_INV_MASK (0x80U) -#define ESC_PHY_CFG1_REFCK_25M_INV_SHIFT (7U) -#define ESC_PHY_CFG1_REFCK_25M_INV_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_REFCK_25M_INV_SHIFT) & ESC_PHY_CFG1_REFCK_25M_INV_MASK) -#define ESC_PHY_CFG1_REFCK_25M_INV_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_INV_MASK) >> ESC_PHY_CFG1_REFCK_25M_INV_SHIFT) - -/* - * RMII_P2_RXCK_REFCLK_OE (RW) - * - */ -#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK (0x40U) -#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT (6U) -#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) -#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) - -/* - * RMII_P1_RXCK_REFCLK_OE (RW) - * - */ -#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK (0x20U) -#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT (5U) -#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) -#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) - -/* - * RMII_P0_RXCK_REFCLK_OE (RW) - * - */ -#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK (0x10U) -#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT (4U) -#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) -#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) - -/* - * REFCK_25M_OE (RW) - * - */ -#define ESC_PHY_CFG1_REFCK_25M_OE_MASK (0x8U) -#define ESC_PHY_CFG1_REFCK_25M_OE_SHIFT (3U) -#define ESC_PHY_CFG1_REFCK_25M_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_REFCK_25M_OE_SHIFT) & ESC_PHY_CFG1_REFCK_25M_OE_MASK) -#define ESC_PHY_CFG1_REFCK_25M_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_OE_MASK) >> ESC_PHY_CFG1_REFCK_25M_OE_SHIFT) - -/* - * RMII_P2_TXCK_REFCLK_OE (RW) - * - */ -#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK (0x4U) -#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT (2U) -#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) -#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) - -/* - * RMII_P1_TXCK_REFCLK_OE (RW) - * - */ -#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK (0x2U) -#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT (1U) -#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) -#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) - -/* - * RMII_P0_TXCK_REFCLK_OE (RW) - * - */ -#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK (0x1U) -#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT (0U) -#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) -#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) - -/* Bitfield definition for register: GPIO_CTRL */ -/* - * SW_LATCH_GPI (WO) - * - * if gpi_trig_sel is set to 4'b1001, setting this bit will latch GPI to gpi_reg0/1 - */ -#define ESC_GPIO_CTRL_SW_LATCH_GPI_MASK (0x80000000UL) -#define ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT (31U) -#define ESC_GPIO_CTRL_SW_LATCH_GPI_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT) & ESC_GPIO_CTRL_SW_LATCH_GPI_MASK) -#define ESC_GPIO_CTRL_SW_LATCH_GPI_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_SW_LATCH_GPI_MASK) >> ESC_GPIO_CTRL_SW_LATCH_GPI_SHIFT) - -/* - * SW_LATCH_GPO (WO) - * - * if gpo_trig_sel is set to 4'b1001, setting this bit will latch GPO to gpo_reg0/1 - */ -#define ESC_GPIO_CTRL_SW_LATCH_GPO_MASK (0x40000000UL) -#define ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT (30U) -#define ESC_GPIO_CTRL_SW_LATCH_GPO_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT) & ESC_GPIO_CTRL_SW_LATCH_GPO_MASK) -#define ESC_GPIO_CTRL_SW_LATCH_GPO_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_SW_LATCH_GPO_MASK) >> ESC_GPIO_CTRL_SW_LATCH_GPO_SHIFT) - -/* - * GPI_OVERRIDE_EN (RW) - * - * set this bit will use GPI from the software register gpi_override0/1 - * clr to use GPI from pad directly - */ -#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK (0x2000U) -#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT (13U) -#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT) & ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK) -#define ESC_GPIO_CTRL_GPI_OVERRIDE_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_OVERRIDE_EN_MASK) >> ESC_GPIO_CTRL_GPI_OVERRIDE_EN_SHIFT) - -/* - * GPI_TRIG_EN (RW) - * - * use gpi_trig_sel can select the trigger event to latch GPI signal(from reg or pad) - * set to use triggered signal; - * clr to use signals direclty(from reg or pad) - * assign pdi_gpi = gpi_trig_en ? gpi_reg : - * (gpi_override_en ? gpi_override :pad_di_ecat_gpi); - */ -#define ESC_GPIO_CTRL_GPI_TRIG_EN_MASK (0x1000U) -#define ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT (12U) -#define ESC_GPIO_CTRL_GPI_TRIG_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT) & ESC_GPIO_CTRL_GPI_TRIG_EN_MASK) -#define ESC_GPIO_CTRL_GPI_TRIG_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_TRIG_EN_MASK) >> ESC_GPIO_CTRL_GPI_TRIG_EN_SHIFT) - -/* - * GPI_TRIG_SEL (RW) - * - * select the trigger signal to latch GPI. - * 0000: SOF; 0001: EOF; 0010: pos of SYNC0; 0011: pos of SYNC1; - * 0100: pos of LATCH0; 0101: pos of LATCH1; 0110: neg of LATCH0; 0111: neg of LATCH1 - * 1000: wdog trigger; 1001: sw set gpio_ctrl[31]; others no trigger - */ -#define ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK (0xF00U) -#define ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT (8U) -#define ESC_GPIO_CTRL_GPI_TRIG_SEL_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT) & ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK) -#define ESC_GPIO_CTRL_GPI_TRIG_SEL_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPI_TRIG_SEL_MASK) >> ESC_GPIO_CTRL_GPI_TRIG_SEL_SHIFT) - -/* - * GPO_TRIG_EN (RW) - * - * use gpo_trig_sel can select the trigger event to latch GPO signal(from core) - * set to use triggered signal; - * clr to use GPO signals direclty(from reg or pad) - */ -#define ESC_GPIO_CTRL_GPO_TRIG_EN_MASK (0x10U) -#define ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT (4U) -#define ESC_GPIO_CTRL_GPO_TRIG_EN_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT) & ESC_GPIO_CTRL_GPO_TRIG_EN_MASK) -#define ESC_GPIO_CTRL_GPO_TRIG_EN_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPO_TRIG_EN_MASK) >> ESC_GPIO_CTRL_GPO_TRIG_EN_SHIFT) - -/* - * GPO_TRIG_SEL (RW) - * - * select the trigger signal to latch GPO. - * 0000: SOF; 0001: EOF; 0010: pos of SYNC0; 0011: pos of SYNC1; - * 0100: pos of LATCH0; 0101: pos of LATCH1; 0110: neg of LATCH0; 0111: neg of LATCH1 - * 1000: wdog trigger; 1001: sw set gpio_ctrl[30]; others no trigger - */ -#define ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK (0xFU) -#define ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT (0U) -#define ESC_GPIO_CTRL_GPO_TRIG_SEL_SET(x) (((uint32_t)(x) << ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT) & ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK) -#define ESC_GPIO_CTRL_GPO_TRIG_SEL_GET(x) (((uint32_t)(x) & ESC_GPIO_CTRL_GPO_TRIG_SEL_MASK) >> ESC_GPIO_CTRL_GPO_TRIG_SEL_SHIFT) - -/* Bitfield definition for register: GPI_OVERRIDE0 */ -/* - * GPR_OVERRIDE_LOW (RW) - * - */ -#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK (0xFFFFFFFFUL) -#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT (0U) -#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SET(x) (((uint32_t)(x) << ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT) & ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK) -#define ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_GET(x) (((uint32_t)(x) & ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_MASK) >> ESC_GPI_OVERRIDE0_GPR_OVERRIDE_LOW_SHIFT) - -/* Bitfield definition for register: GPI_OVERRIDE1 */ -/* - * GPR_OVERRIDE_HIGH (RW) - * - */ -#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK (0xFFFFFFFFUL) -#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT (0U) -#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SET(x) (((uint32_t)(x) << ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT) & ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK) -#define ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_GET(x) (((uint32_t)(x) & ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_MASK) >> ESC_GPI_OVERRIDE1_GPR_OVERRIDE_HIGH_SHIFT) - -/* Bitfield definition for register: GPO_REG0 */ -/* - * VALUE (RO) - * - */ -#define ESC_GPO_REG0_VALUE_MASK (0xFFFFFFFFUL) -#define ESC_GPO_REG0_VALUE_SHIFT (0U) -#define ESC_GPO_REG0_VALUE_GET(x) (((uint32_t)(x) & ESC_GPO_REG0_VALUE_MASK) >> ESC_GPO_REG0_VALUE_SHIFT) - -/* Bitfield definition for register: GPO_REG1 */ -/* - * VALUE (RO) - * - */ -#define ESC_GPO_REG1_VALUE_MASK (0xFFFFFFFFUL) -#define ESC_GPO_REG1_VALUE_SHIFT (0U) -#define ESC_GPO_REG1_VALUE_GET(x) (((uint32_t)(x) & ESC_GPO_REG1_VALUE_MASK) >> ESC_GPO_REG1_VALUE_SHIFT) - -/* Bitfield definition for register: GPI_REG0 */ -/* - * VALUE (RO) - * - */ -#define ESC_GPI_REG0_VALUE_MASK (0xFFFFFFFFUL) -#define ESC_GPI_REG0_VALUE_SHIFT (0U) -#define ESC_GPI_REG0_VALUE_GET(x) (((uint32_t)(x) & ESC_GPI_REG0_VALUE_MASK) >> ESC_GPI_REG0_VALUE_SHIFT) - -/* Bitfield definition for register: GPI_REG1 */ -/* - * VALUE (RO) - * - */ -#define ESC_GPI_REG1_VALUE_MASK (0xFFFFFFFFUL) -#define ESC_GPI_REG1_VALUE_SHIFT (0U) -#define ESC_GPI_REG1_VALUE_GET(x) (((uint32_t)(x) & ESC_GPI_REG1_VALUE_MASK) >> ESC_GPI_REG1_VALUE_SHIFT) - -/* Bitfield definition for register: GPR_STATUS */ -/* - * NLINK2_PADSEL (RO) - * - */ -#define ESC_GPR_STATUS_NLINK2_PADSEL_MASK (0xF0000000UL) -#define ESC_GPR_STATUS_NLINK2_PADSEL_SHIFT (28U) -#define ESC_GPR_STATUS_NLINK2_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK2_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK2_PADSEL_SHIFT) - -/* - * NLINK1_PADSEL (RO) - * - */ -#define ESC_GPR_STATUS_NLINK1_PADSEL_MASK (0xF000000UL) -#define ESC_GPR_STATUS_NLINK1_PADSEL_SHIFT (24U) -#define ESC_GPR_STATUS_NLINK1_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK1_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK1_PADSEL_SHIFT) - -/* - * NLINK0_PADSEL (RO) - * - */ -#define ESC_GPR_STATUS_NLINK0_PADSEL_MASK (0xF00000UL) -#define ESC_GPR_STATUS_NLINK0_PADSEL_SHIFT (20U) -#define ESC_GPR_STATUS_NLINK0_PADSEL_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_NLINK0_PADSEL_MASK) >> ESC_GPR_STATUS_NLINK0_PADSEL_SHIFT) - -/* - * PDI_SOF (RO) - * - */ -#define ESC_GPR_STATUS_PDI_SOF_MASK (0x80000UL) -#define ESC_GPR_STATUS_PDI_SOF_SHIFT (19U) -#define ESC_GPR_STATUS_PDI_SOF_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_SOF_MASK) >> ESC_GPR_STATUS_PDI_SOF_SHIFT) - -/* - * PDI_EOF (RO) - * - */ -#define ESC_GPR_STATUS_PDI_EOF_MASK (0x40000UL) -#define ESC_GPR_STATUS_PDI_EOF_SHIFT (18U) -#define ESC_GPR_STATUS_PDI_EOF_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_EOF_MASK) >> ESC_GPR_STATUS_PDI_EOF_SHIFT) - -/* - * PDI_WD_TRIGGER (RO) - * - */ -#define ESC_GPR_STATUS_PDI_WD_TRIGGER_MASK (0x20000UL) -#define ESC_GPR_STATUS_PDI_WD_TRIGGER_SHIFT (17U) -#define ESC_GPR_STATUS_PDI_WD_TRIGGER_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_WD_TRIGGER_MASK) >> ESC_GPR_STATUS_PDI_WD_TRIGGER_SHIFT) - -/* - * PDI_WD_STATE (RO) - * - */ -#define ESC_GPR_STATUS_PDI_WD_STATE_MASK (0x10000UL) -#define ESC_GPR_STATUS_PDI_WD_STATE_SHIFT (16U) -#define ESC_GPR_STATUS_PDI_WD_STATE_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_PDI_WD_STATE_MASK) >> ESC_GPR_STATUS_PDI_WD_STATE_SHIFT) - -/* - * SYNC_OUT1 (RO) - * - */ -#define ESC_GPR_STATUS_SYNC_OUT1_MASK (0x200U) -#define ESC_GPR_STATUS_SYNC_OUT1_SHIFT (9U) -#define ESC_GPR_STATUS_SYNC_OUT1_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_SYNC_OUT1_MASK) >> ESC_GPR_STATUS_SYNC_OUT1_SHIFT) - -/* - * SYNC_OUT0 (RO) - * - */ -#define ESC_GPR_STATUS_SYNC_OUT0_MASK (0x100U) -#define ESC_GPR_STATUS_SYNC_OUT0_SHIFT (8U) -#define ESC_GPR_STATUS_SYNC_OUT0_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_SYNC_OUT0_MASK) >> ESC_GPR_STATUS_SYNC_OUT0_SHIFT) - -/* - * LED_STATE_RUN (RO) - * - */ -#define ESC_GPR_STATUS_LED_STATE_RUN_MASK (0x40U) -#define ESC_GPR_STATUS_LED_STATE_RUN_SHIFT (6U) -#define ESC_GPR_STATUS_LED_STATE_RUN_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_STATE_RUN_MASK) >> ESC_GPR_STATUS_LED_STATE_RUN_SHIFT) - -/* - * LED_ERR (RO) - * - */ -#define ESC_GPR_STATUS_LED_ERR_MASK (0x20U) -#define ESC_GPR_STATUS_LED_ERR_SHIFT (5U) -#define ESC_GPR_STATUS_LED_ERR_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_ERR_MASK) >> ESC_GPR_STATUS_LED_ERR_SHIFT) - -/* - * LED_RUN (RO) - * - */ -#define ESC_GPR_STATUS_LED_RUN_MASK (0x10U) -#define ESC_GPR_STATUS_LED_RUN_SHIFT (4U) -#define ESC_GPR_STATUS_LED_RUN_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LED_RUN_MASK) >> ESC_GPR_STATUS_LED_RUN_SHIFT) - -/* - * DEV_STATE (RO) - * - */ -#define ESC_GPR_STATUS_DEV_STATE_MASK (0x8U) -#define ESC_GPR_STATUS_DEV_STATE_SHIFT (3U) -#define ESC_GPR_STATUS_DEV_STATE_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_DEV_STATE_MASK) >> ESC_GPR_STATUS_DEV_STATE_SHIFT) - -/* - * LINK_ACT (RO) - * - */ -#define ESC_GPR_STATUS_LINK_ACT_MASK (0x7U) -#define ESC_GPR_STATUS_LINK_ACT_SHIFT (0U) -#define ESC_GPR_STATUS_LINK_ACT_GET(x) (((uint32_t)(x) & ESC_GPR_STATUS_LINK_ACT_MASK) >> ESC_GPR_STATUS_LINK_ACT_SHIFT) - -/* Bitfield definition for register array: IO_CFG */ -/* - * INVERT (RW) - * - * 1:invert the IO - */ -#define ESC_IO_CFG_INVERT_MASK (0x10U) -#define ESC_IO_CFG_INVERT_SHIFT (4U) -#define ESC_IO_CFG_INVERT_SET(x) (((uint32_t)(x) << ESC_IO_CFG_INVERT_SHIFT) & ESC_IO_CFG_INVERT_MASK) -#define ESC_IO_CFG_INVERT_GET(x) (((uint32_t)(x) & ESC_IO_CFG_INVERT_MASK) >> ESC_IO_CFG_INVERT_SHIFT) - -/* - * FUNC_ALT (RW) - * - * IO usage: - * 0:NMII_LINK0 - * 1:NMII_LINK1 - * 2:NMII_LINK2 - * 3:LINK_ACT0 - * 4:LINK_ACT1 - * 5:LINK_ACT2 - * 6:LED_RUN - * 7:LED_ERR - * 8:RESET_OUT - */ -#define ESC_IO_CFG_FUNC_ALT_MASK (0xFU) -#define ESC_IO_CFG_FUNC_ALT_SHIFT (0U) -#define ESC_IO_CFG_FUNC_ALT_SET(x) (((uint32_t)(x) << ESC_IO_CFG_FUNC_ALT_SHIFT) & ESC_IO_CFG_FUNC_ALT_MASK) -#define ESC_IO_CFG_FUNC_ALT_GET(x) (((uint32_t)(x) & ESC_IO_CFG_FUNC_ALT_MASK) >> ESC_IO_CFG_FUNC_ALT_SHIFT) - - - -/* RX_ERR_CNT register group index macro definition */ -#define ESC_RX_ERR_CNT_PORT0 (0UL) -#define ESC_RX_ERR_CNT_PORT1 (1UL) -#define ESC_RX_ERR_CNT_PORT2 (2UL) -#define ESC_RX_ERR_CNT_PORT3 (3UL) - -/* FWD_RX_ERR_CNT register group index macro definition */ -#define ESC_FWD_RX_ERR_CNT_PORT0 (0UL) -#define ESC_FWD_RX_ERR_CNT_PORT1 (1UL) -#define ESC_FWD_RX_ERR_CNT_PORT2 (2UL) -#define ESC_FWD_RX_ERR_CNT_PORT3 (3UL) - -/* LOST_LINK_CNT register group index macro definition */ -#define ESC_LOST_LINK_CNT_PORT0 (0UL) -#define ESC_LOST_LINK_CNT_PORT1 (1UL) -#define ESC_LOST_LINK_CNT_PORT2 (2UL) -#define ESC_LOST_LINK_CNT_PORT3 (3UL) - -/* PHY_STAT register group index macro definition */ -#define ESC_PHY_STAT_PORT0 (0UL) -#define ESC_PHY_STAT_PORT1 (1UL) -#define ESC_PHY_STAT_PORT2 (2UL) -#define ESC_PHY_STAT_PORT3 (3UL) - -/* FMMU register group index macro definition */ -#define ESC_FMMU_0 (0UL) -#define ESC_FMMU_1 (1UL) -#define ESC_FMMU_2 (2UL) -#define ESC_FMMU_3 (3UL) -#define ESC_FMMU_4 (4UL) -#define ESC_FMMU_5 (5UL) -#define ESC_FMMU_6 (6UL) -#define ESC_FMMU_7 (7UL) - -/* SYNCM register group index macro definition */ -#define ESC_SYNCM_0 (0UL) -#define ESC_SYNCM_1 (1UL) -#define ESC_SYNCM_2 (2UL) -#define ESC_SYNCM_3 (3UL) -#define ESC_SYNCM_4 (4UL) -#define ESC_SYNCM_5 (5UL) -#define ESC_SYNCM_6 (6UL) -#define ESC_SYNCM_7 (7UL) - -/* RCV_TIME register group index macro definition */ -#define ESC_RCV_TIME_PORT0 (0UL) -#define ESC_RCV_TIME_PORT1 (1UL) -#define ESC_RCV_TIME_PORT2 (2UL) -#define ESC_RCV_TIME_PORT3 (3UL) - -/* IO_CFG register group index macro definition */ -#define ESC_IO_CFG_CTR0 (0UL) -#define ESC_IO_CFG_CTR1 (1UL) -#define ESC_IO_CFG_CTR2 (2UL) -#define ESC_IO_CFG_CTR3 (3UL) -#define ESC_IO_CFG_CTR4 (4UL) -#define ESC_IO_CFG_CTR5 (5UL) -#define ESC_IO_CFG_CTR6 (6UL) -#define ESC_IO_CFG_CTR7 (7UL) -#define ESC_IO_CFG_CTR8 (8UL) - - -#endif /* HPM_ESC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ewdg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ewdg_regs.h deleted file mode 100644 index aacfa33c742..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ewdg_regs.h +++ /dev/null @@ -1,467 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_EWDG_H -#define HPM_EWDG_H - -typedef struct { - __RW uint32_t CTRL0; /* 0x0: wdog ctrl register 0 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ - __RW uint32_t CTRL1; /* 0x4: wdog ctrl register 1 -Note: Parity check is required once writing to this register. The result should be zero by modular two addition of all bits */ - __RW uint32_t OT_INT_VAL; /* 0x8: wdog timeout interrupt counter value */ - __RW uint32_t OT_RST_VAL; /* 0xC: wdog timeout reset counter value */ - __W uint32_t WDT_REFRESH_REG; /* 0x10: wdog refresh register */ - __W uint32_t WDT_STATUS; /* 0x14: wdog status register */ - __RW uint32_t CFG_PROT; /* 0x18: ctrl register protection register */ - __RW uint32_t REF_PROT; /* 0x1C: refresh protection register */ - __RW uint32_t WDT_EN; /* 0x20: Wdog enable */ - __RW uint32_t REF_TIME; /* 0x24: Refresh period value */ -} EWDG_Type; - - -/* Bitfield definition for register: CTRL0 */ -/* - * CLK_SEL (RW) - * - * clock select - * 0：bus clock - * 1：ext clock - */ -#define EWDG_CTRL0_CLK_SEL_MASK (0x20000000UL) -#define EWDG_CTRL0_CLK_SEL_SHIFT (29U) -#define EWDG_CTRL0_CLK_SEL_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CLK_SEL_SHIFT) & EWDG_CTRL0_CLK_SEL_MASK) -#define EWDG_CTRL0_CLK_SEL_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CLK_SEL_MASK) >> EWDG_CTRL0_CLK_SEL_SHIFT) - -/* - * DIV_VALUE (RW) - * - * clock divider, the clock divider works as 2 ^ div_value for wdt counter - */ -#define EWDG_CTRL0_DIV_VALUE_MASK (0xE000000UL) -#define EWDG_CTRL0_DIV_VALUE_SHIFT (25U) -#define EWDG_CTRL0_DIV_VALUE_SET(x) (((uint32_t)(x) << EWDG_CTRL0_DIV_VALUE_SHIFT) & EWDG_CTRL0_DIV_VALUE_MASK) -#define EWDG_CTRL0_DIV_VALUE_GET(x) (((uint32_t)(x) & EWDG_CTRL0_DIV_VALUE_MASK) >> EWDG_CTRL0_DIV_VALUE_SHIFT) - -/* - * WIN_EN (RW) - * - * window mode enable - */ -#define EWDG_CTRL0_WIN_EN_MASK (0x1000000UL) -#define EWDG_CTRL0_WIN_EN_SHIFT (24U) -#define EWDG_CTRL0_WIN_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_EN_SHIFT) & EWDG_CTRL0_WIN_EN_MASK) -#define EWDG_CTRL0_WIN_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_EN_MASK) >> EWDG_CTRL0_WIN_EN_SHIFT) - -/* - * WIN_LOWER (RW) - * - * Once window mode is opened, the lower counter value to refresh wdt - * 00: 4/8 overtime value - * 01: 5/8 of overtime value - * 10: 6/8 of overtime value - * 11: 7/8 of overtime value - */ -#define EWDG_CTRL0_WIN_LOWER_MASK (0xC00000UL) -#define EWDG_CTRL0_WIN_LOWER_SHIFT (22U) -#define EWDG_CTRL0_WIN_LOWER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_LOWER_SHIFT) & EWDG_CTRL0_WIN_LOWER_MASK) -#define EWDG_CTRL0_WIN_LOWER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_LOWER_MASK) >> EWDG_CTRL0_WIN_LOWER_SHIFT) - -/* - * CFG_LOCK (RW) - * - * The register is locked and unlock is needed before re-config registers - * Once the lock mechanism takes effect, the CTRL0, CTRL1, timeout int register, timeout rst register, needs unlock before re-config them. - * The register update needs to be finished in the required period defined by UPD_OT_TIME register - */ -#define EWDG_CTRL0_CFG_LOCK_MASK (0x200000UL) -#define EWDG_CTRL0_CFG_LOCK_SHIFT (21U) -#define EWDG_CTRL0_CFG_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_CFG_LOCK_SHIFT) & EWDG_CTRL0_CFG_LOCK_MASK) -#define EWDG_CTRL0_CFG_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_CFG_LOCK_MASK) >> EWDG_CTRL0_CFG_LOCK_SHIFT) - -/* - * OT_SELF_CLEAR (RW) - * - * overtime reset can be self released after 32 function cycles - */ -#define EWDG_CTRL0_OT_SELF_CLEAR_MASK (0x20000UL) -#define EWDG_CTRL0_OT_SELF_CLEAR_SHIFT (17U) -#define EWDG_CTRL0_OT_SELF_CLEAR_SET(x) (((uint32_t)(x) << EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) -#define EWDG_CTRL0_OT_SELF_CLEAR_GET(x) (((uint32_t)(x) & EWDG_CTRL0_OT_SELF_CLEAR_MASK) >> EWDG_CTRL0_OT_SELF_CLEAR_SHIFT) - -/* - * REF_OT_REQ (RW) - * - * If refresh event has to be limited into a period after refresh unlocked. - * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - */ -#define EWDG_CTRL0_REF_OT_REQ_MASK (0x8000U) -#define EWDG_CTRL0_REF_OT_REQ_SHIFT (15U) -#define EWDG_CTRL0_REF_OT_REQ_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_OT_REQ_SHIFT) & EWDG_CTRL0_REF_OT_REQ_MASK) -#define EWDG_CTRL0_REF_OT_REQ_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_OT_REQ_MASK) >> EWDG_CTRL0_REF_OT_REQ_SHIFT) - -/* - * WIN_UPPER (RW) - * - * The upper threshold of window value - * The window period upper limit is: lower_limit + (overtime_rst_value / 16) * upper_reg_value - * If this register value is zero, then no upper level limitation - */ -#define EWDG_CTRL0_WIN_UPPER_MASK (0x7000U) -#define EWDG_CTRL0_WIN_UPPER_SHIFT (12U) -#define EWDG_CTRL0_WIN_UPPER_SET(x) (((uint32_t)(x) << EWDG_CTRL0_WIN_UPPER_SHIFT) & EWDG_CTRL0_WIN_UPPER_MASK) -#define EWDG_CTRL0_WIN_UPPER_GET(x) (((uint32_t)(x) & EWDG_CTRL0_WIN_UPPER_MASK) >> EWDG_CTRL0_WIN_UPPER_SHIFT) - -/* - * REF_LOCK (RW) - * - * WDT refresh has to be unlocked firstly once refresh lock is enable. - */ -#define EWDG_CTRL0_REF_LOCK_MASK (0x20U) -#define EWDG_CTRL0_REF_LOCK_SHIFT (5U) -#define EWDG_CTRL0_REF_LOCK_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_LOCK_SHIFT) & EWDG_CTRL0_REF_LOCK_MASK) -#define EWDG_CTRL0_REF_LOCK_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_LOCK_MASK) >> EWDG_CTRL0_REF_LOCK_SHIFT) - -/* - * REF_UNLOCK_MEC (RW) - * - * Unlock refresh mechanism - * 00: the required unlock password is the same with refresh_psd_register - * 01: the required unlock password is a ring shift left value of refresh_psd_register - * 10: the required unlock password is always 16'h55AA, no matter what refresh_psd_register is - * 11: the required unlock password is a LSFR result of refresh_psd_register, the characteristic polynomial is X^15 + 1 - */ -#define EWDG_CTRL0_REF_UNLOCK_MEC_MASK (0x18U) -#define EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT (3U) -#define EWDG_CTRL0_REF_UNLOCK_MEC_SET(x) (((uint32_t)(x) << EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) -#define EWDG_CTRL0_REF_UNLOCK_MEC_GET(x) (((uint32_t)(x) & EWDG_CTRL0_REF_UNLOCK_MEC_MASK) >> EWDG_CTRL0_REF_UNLOCK_MEC_SHIFT) - -/* - * EN_DBG (RW) - * - * WTD enable or not in debug mode - */ -#define EWDG_CTRL0_EN_DBG_MASK (0x4U) -#define EWDG_CTRL0_EN_DBG_SHIFT (2U) -#define EWDG_CTRL0_EN_DBG_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_DBG_SHIFT) & EWDG_CTRL0_EN_DBG_MASK) -#define EWDG_CTRL0_EN_DBG_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_DBG_MASK) >> EWDG_CTRL0_EN_DBG_SHIFT) - -/* - * EN_LP (RW) - * - * WDT enable or not in low power mode - * 2'b00: wdt is halted once in low power mode - * 2'b01: wdt will work with 1/4 normal clock freq in low power mode - * 2'b10: wdt will work with 1/2 normal clock freq in low power mode - * 2'b11: wdt will work with normal clock freq in low power mode - */ -#define EWDG_CTRL0_EN_LP_MASK (0x3U) -#define EWDG_CTRL0_EN_LP_SHIFT (0U) -#define EWDG_CTRL0_EN_LP_SET(x) (((uint32_t)(x) << EWDG_CTRL0_EN_LP_SHIFT) & EWDG_CTRL0_EN_LP_MASK) -#define EWDG_CTRL0_EN_LP_GET(x) (((uint32_t)(x) & EWDG_CTRL0_EN_LP_MASK) >> EWDG_CTRL0_EN_LP_SHIFT) - -/* Bitfield definition for register: CTRL1 */ -/* - * REF_FAIL_RST_EN (RW) - * - * Refresh violation will trigger an reset. - * These event will be taken as a refresh violation: - * 1) Not refresh in the window once window mode is enabled - * 2) Not unlock refresh firstly if unlock is required - * 3) Not refresh in the required time after unlock, once refresh unlock overtime is enabled. - * 4) Not write the required word to refresh wdt. - */ -#define EWDG_CTRL1_REF_FAIL_RST_EN_MASK (0x800000UL) -#define EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT (23U) -#define EWDG_CTRL1_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_REF_FAIL_RST_EN_SHIFT) - -/* - * REF_FAIL_INT_EN (RW) - * - * Refresh violation will trigger an interrupt - */ -#define EWDG_CTRL1_REF_FAIL_INT_EN_MASK (0x400000UL) -#define EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT (22U) -#define EWDG_CTRL1_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_REF_FAIL_INT_EN_SHIFT) - -/* - * UNL_REF_FAIL_RST_EN (RW) - * - * Refresh unlock fail will trigger a reset - */ -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK (0x200000UL) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT (21U) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_UNL_REF_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_RST_EN_SHIFT) - -/* - * UNL_REF_FAIL_INT_EN (RW) - * - * Refresh unlock fail will trigger a interrupt - */ -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK (0x100000UL) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT (20U) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_UNL_REF_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_REF_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_REF_FAIL_INT_EN_SHIFT) - -/* - * OT_RST_EN (RW) - * - * WDT overtime will generate a reset - */ -#define EWDG_CTRL1_OT_RST_EN_MASK (0x20000UL) -#define EWDG_CTRL1_OT_RST_EN_SHIFT (17U) -#define EWDG_CTRL1_OT_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_RST_EN_SHIFT) & EWDG_CTRL1_OT_RST_EN_MASK) -#define EWDG_CTRL1_OT_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_RST_EN_MASK) >> EWDG_CTRL1_OT_RST_EN_SHIFT) - -/* - * OT_INT_EN (RW) - * - * WDT can generate an interrupt warning before timeout - */ -#define EWDG_CTRL1_OT_INT_EN_MASK (0x10000UL) -#define EWDG_CTRL1_OT_INT_EN_SHIFT (16U) -#define EWDG_CTRL1_OT_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_OT_INT_EN_SHIFT) & EWDG_CTRL1_OT_INT_EN_MASK) -#define EWDG_CTRL1_OT_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_OT_INT_EN_MASK) >> EWDG_CTRL1_OT_INT_EN_SHIFT) - -/* - * CTL_VIO_RST_EN (RW) - * - * Ctrl update violation will trigger a reset - * The violation event is to try updating the locked register before unlock them - */ -#define EWDG_CTRL1_CTL_VIO_RST_EN_MASK (0x80U) -#define EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT (7U) -#define EWDG_CTRL1_CTL_VIO_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) -#define EWDG_CTRL1_CTL_VIO_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_RST_EN_MASK) >> EWDG_CTRL1_CTL_VIO_RST_EN_SHIFT) - -/* - * CTL_VIO_INT_EN (RW) - * - * Ctrl update violation will trigger a interrupt - */ -#define EWDG_CTRL1_CTL_VIO_INT_EN_MASK (0x40U) -#define EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT (6U) -#define EWDG_CTRL1_CTL_VIO_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) -#define EWDG_CTRL1_CTL_VIO_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_CTL_VIO_INT_EN_MASK) >> EWDG_CTRL1_CTL_VIO_INT_EN_SHIFT) - -/* - * UNL_CTL_FAIL_RST_EN (RW) - * - * Unlock register update failure will trigger a reset - */ -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK (0x20U) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT (5U) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_RST_EN_SHIFT) - -/* - * UNL_CTL_FAIL_INT_EN (RW) - * - * Unlock register update failure will trigger a interrupt - */ -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK (0x10U) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT (4U) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_MASK) >> EWDG_CTRL1_UNL_CTL_FAIL_INT_EN_SHIFT) - -/* - * PARITY_FAIL_RST_EN (RW) - * - * Parity error will trigger a reset - * A parity check is required once writing to ctrl0 and ctrl1 register. The result should be zero by modular two addition of all bits - */ -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK (0x8U) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT (3U) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) -#define EWDG_CTRL1_PARITY_FAIL_RST_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_RST_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_RST_EN_SHIFT) - -/* - * PARITY_FAIL_INT_EN (RW) - * - * Parity error will trigger a interrupt - */ -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK (0x4U) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT (2U) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_SET(x) (((uint32_t)(x) << EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) -#define EWDG_CTRL1_PARITY_FAIL_INT_EN_GET(x) (((uint32_t)(x) & EWDG_CTRL1_PARITY_FAIL_INT_EN_MASK) >> EWDG_CTRL1_PARITY_FAIL_INT_EN_SHIFT) - -/* Bitfield definition for register: OT_INT_VAL */ -/* - * OT_INT_VAL (RW) - * - * WDT timeout interrupt value - */ -#define EWDG_OT_INT_VAL_OT_INT_VAL_MASK (0xFFFFU) -#define EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT (0U) -#define EWDG_OT_INT_VAL_OT_INT_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) -#define EWDG_OT_INT_VAL_OT_INT_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_INT_VAL_OT_INT_VAL_MASK) >> EWDG_OT_INT_VAL_OT_INT_VAL_SHIFT) - -/* Bitfield definition for register: OT_RST_VAL */ -/* - * OT_RST_VAL (RW) - * - * WDT timeout reset value - */ -#define EWDG_OT_RST_VAL_OT_RST_VAL_MASK (0xFFFFU) -#define EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT (0U) -#define EWDG_OT_RST_VAL_OT_RST_VAL_SET(x) (((uint32_t)(x) << EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) -#define EWDG_OT_RST_VAL_OT_RST_VAL_GET(x) (((uint32_t)(x) & EWDG_OT_RST_VAL_OT_RST_VAL_MASK) >> EWDG_OT_RST_VAL_OT_RST_VAL_SHIFT) - -/* Bitfield definition for register: WDT_REFRESH_REG */ -/* - * WDT_REFRESH_REG (WO) - * - * Write this register by 32'h5A45_524F to refresh wdog - * Note: Reading this register can read back wdt real time counter value, while it is only used by debug purpose - */ -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK (0xFFFFFFFFUL) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT (0U) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SET(x) (((uint32_t)(x) << EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) -#define EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_GET(x) (((uint32_t)(x) & EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_MASK) >> EWDG_WDT_REFRESH_REG_WDT_REFRESH_REG_SHIFT) - -/* Bitfield definition for register: WDT_STATUS */ -/* - * PARITY_ERROR (W1C) - * - * parity error - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_PARITY_ERROR_MASK (0x40U) -#define EWDG_WDT_STATUS_PARITY_ERROR_SHIFT (6U) -#define EWDG_WDT_STATUS_PARITY_ERROR_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) -#define EWDG_WDT_STATUS_PARITY_ERROR_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_PARITY_ERROR_MASK) >> EWDG_WDT_STATUS_PARITY_ERROR_SHIFT) - -/* - * OT_RST (W1C) - * - * Timeout happens, a reset will happen once enable bit set - * This bit can be cleared only by refreshing wdt or reset - */ -#define EWDG_WDT_STATUS_OT_RST_MASK (0x20U) -#define EWDG_WDT_STATUS_OT_RST_SHIFT (5U) -#define EWDG_WDT_STATUS_OT_RST_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_OT_RST_SHIFT) & EWDG_WDT_STATUS_OT_RST_MASK) -#define EWDG_WDT_STATUS_OT_RST_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_RST_MASK) >> EWDG_WDT_STATUS_OT_RST_SHIFT) - -/* - * OT_INT (W1C) - * - * Timeout happens, a interrupt will happen once enable bit set - * This bit can be cleared only by refreshing wdt or reset - */ -#define EWDG_WDT_STATUS_OT_INT_MASK (0x10U) -#define EWDG_WDT_STATUS_OT_INT_SHIFT (4U) -#define EWDG_WDT_STATUS_OT_INT_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_OT_INT_SHIFT) & EWDG_WDT_STATUS_OT_INT_MASK) -#define EWDG_WDT_STATUS_OT_INT_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_OT_INT_MASK) >> EWDG_WDT_STATUS_OT_INT_SHIFT) - -/* - * CTL_UNL_FAIL (W1C) - * - * Unlock ctrl reg update protection fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK (0x8U) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT (3U) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) -#define EWDG_WDT_STATUS_CTL_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_CTL_UNL_FAIL_SHIFT) - -/* - * CTL_VIO (W1C) - * - * Violate register update protection mechanism - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_CTL_VIO_MASK (0x4U) -#define EWDG_WDT_STATUS_CTL_VIO_SHIFT (2U) -#define EWDG_WDT_STATUS_CTL_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_CTL_VIO_SHIFT) & EWDG_WDT_STATUS_CTL_VIO_MASK) -#define EWDG_WDT_STATUS_CTL_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_CTL_VIO_MASK) >> EWDG_WDT_STATUS_CTL_VIO_SHIFT) - -/* - * REF_UNL_FAIL (W1C) - * - * Refresh unlock fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_REF_UNL_FAIL_MASK (0x2U) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT (1U) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) -#define EWDG_WDT_STATUS_REF_UNL_FAIL_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_UNL_FAIL_MASK) >> EWDG_WDT_STATUS_REF_UNL_FAIL_SHIFT) - -/* - * REF_VIO (W1C) - * - * Refresh fail - * Write one to clear the bit - */ -#define EWDG_WDT_STATUS_REF_VIO_MASK (0x1U) -#define EWDG_WDT_STATUS_REF_VIO_SHIFT (0U) -#define EWDG_WDT_STATUS_REF_VIO_SET(x) (((uint32_t)(x) << EWDG_WDT_STATUS_REF_VIO_SHIFT) & EWDG_WDT_STATUS_REF_VIO_MASK) -#define EWDG_WDT_STATUS_REF_VIO_GET(x) (((uint32_t)(x) & EWDG_WDT_STATUS_REF_VIO_MASK) >> EWDG_WDT_STATUS_REF_VIO_SHIFT) - -/* Bitfield definition for register: CFG_PROT */ -/* - * UPD_OT_TIME (RW) - * - * The period in which register update has to be in after unlock - * The required period is less than： 128 * 2 ^ UPD_OT_TIME * bus_clock_cycle - */ -#define EWDG_CFG_PROT_UPD_OT_TIME_MASK (0xF0000UL) -#define EWDG_CFG_PROT_UPD_OT_TIME_SHIFT (16U) -#define EWDG_CFG_PROT_UPD_OT_TIME_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) -#define EWDG_CFG_PROT_UPD_OT_TIME_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_OT_TIME_MASK) >> EWDG_CFG_PROT_UPD_OT_TIME_SHIFT) - -/* - * UPD_PSD (RW) - * - * The password of unlocking register update - */ -#define EWDG_CFG_PROT_UPD_PSD_MASK (0xFFFFU) -#define EWDG_CFG_PROT_UPD_PSD_SHIFT (0U) -#define EWDG_CFG_PROT_UPD_PSD_SET(x) (((uint32_t)(x) << EWDG_CFG_PROT_UPD_PSD_SHIFT) & EWDG_CFG_PROT_UPD_PSD_MASK) -#define EWDG_CFG_PROT_UPD_PSD_GET(x) (((uint32_t)(x) & EWDG_CFG_PROT_UPD_PSD_MASK) >> EWDG_CFG_PROT_UPD_PSD_SHIFT) - -/* Bitfield definition for register: REF_PROT */ -/* - * REF_UNL_PSD (RW) - * - * The password to unlock refreshing - */ -#define EWDG_REF_PROT_REF_UNL_PSD_MASK (0xFFFFU) -#define EWDG_REF_PROT_REF_UNL_PSD_SHIFT (0U) -#define EWDG_REF_PROT_REF_UNL_PSD_SET(x) (((uint32_t)(x) << EWDG_REF_PROT_REF_UNL_PSD_SHIFT) & EWDG_REF_PROT_REF_UNL_PSD_MASK) -#define EWDG_REF_PROT_REF_UNL_PSD_GET(x) (((uint32_t)(x) & EWDG_REF_PROT_REF_UNL_PSD_MASK) >> EWDG_REF_PROT_REF_UNL_PSD_SHIFT) - -/* Bitfield definition for register: WDT_EN */ -/* - * WDOG_EN (RW) - * - * Wdog is enabled, the re-written of this register is impacted by enable lock function - */ -#define EWDG_WDT_EN_WDOG_EN_MASK (0x1U) -#define EWDG_WDT_EN_WDOG_EN_SHIFT (0U) -#define EWDG_WDT_EN_WDOG_EN_SET(x) (((uint32_t)(x) << EWDG_WDT_EN_WDOG_EN_SHIFT) & EWDG_WDT_EN_WDOG_EN_MASK) -#define EWDG_WDT_EN_WDOG_EN_GET(x) (((uint32_t)(x) & EWDG_WDT_EN_WDOG_EN_MASK) >> EWDG_WDT_EN_WDOG_EN_SHIFT) - -/* Bitfield definition for register: REF_TIME */ -/* - * REFRESH_PERIOD (RW) - * - * The refresh period after refresh unlocked - * Note: the refresh overtime counter works in bus clock domain, not in wdt function clock domain. The wdt divider doesn't take effect for refresh counter - */ -#define EWDG_REF_TIME_REFRESH_PERIOD_MASK (0xFFFFU) -#define EWDG_REF_TIME_REFRESH_PERIOD_SHIFT (0U) -#define EWDG_REF_TIME_REFRESH_PERIOD_SET(x) (((uint32_t)(x) << EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) -#define EWDG_REF_TIME_REFRESH_PERIOD_GET(x) (((uint32_t)(x) & EWDG_REF_TIME_REFRESH_PERIOD_MASK) >> EWDG_REF_TIME_REFRESH_PERIOD_SHIFT) - - - - -#endif /* HPM_EWDG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_femc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_femc_regs.h deleted file mode 100644 index f450817a80b..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_femc_regs.h +++ /dev/null @@ -1,981 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_FEMC_H -#define HPM_FEMC_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t IOCTRL; /* 0x4: IO Mux Control Register */ - __RW uint32_t BMW0; /* 0x8: Bus (AXI) Weight Control Register 0 */ - __RW uint32_t BMW1; /* 0xC: Bus (AXI) Weight Control Register 1 */ - __RW uint32_t BR[7]; /* 0x10 - 0x28: Base Register 0 (for SDRAM CS0 device) */ - __R uint8_t RESERVED0[12]; /* 0x2C - 0x37: Reserved */ - __RW uint32_t INTEN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTR; /* 0x3C: Interrupt Status Register */ - __RW uint32_t SDRCTRL0; /* 0x40: SDRAM Control Register 0 */ - __RW uint32_t SDRCTRL1; /* 0x44: SDRAM Control Register 1 */ - __RW uint32_t SDRCTRL2; /* 0x48: SDRAM Control Register 2 */ - __RW uint32_t SDRCTRL3; /* 0x4C: SDRAM Control Register 3 */ - __R uint8_t RESERVED1[32]; /* 0x50 - 0x6F: Reserved */ - __RW uint32_t SRCTRL0; /* 0x70: SRAM control register 0 */ - __RW uint32_t SRCTRL1; /* 0x74: SRAM control register 1 */ - __R uint8_t RESERVED2[24]; /* 0x78 - 0x8F: Reserved */ - __RW uint32_t SADDR; /* 0x90: IP Command Control Register 0 */ - __RW uint32_t DATSZ; /* 0x94: IP Command Control Register 1 */ - __RW uint32_t BYTEMSK; /* 0x98: IP Command Control Register 2 */ - __RW uint32_t IPCMD; /* 0x9C: IP Command Register */ - __RW uint32_t IPTX; /* 0xA0: TX DATA Register */ - __R uint8_t RESERVED3[12]; /* 0xA4 - 0xAF: Reserved */ - __RW uint32_t IPRX; /* 0xB0: RX DATA Register */ - __R uint8_t RESERVED4[12]; /* 0xB4 - 0xBF: Reserved */ - __R uint32_t STAT0; /* 0xC0: Status Register 0 */ - __R uint8_t RESERVED5[140]; /* 0xC4 - 0x14F: Reserved */ - __RW uint32_t DLYCFG; /* 0x150: Delay Line Config Register */ -} FEMC_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * BTO (RW) - * - * Bus timeout cycles - * AXI Bus timeout cycle is as following (255*(2^BTO)): - * 00000b - 255*1 - * 00001-11110b - 255*2 - 255*2^30 - * 11111b - 255*2^31 - */ -#define FEMC_CTRL_BTO_MASK (0x1F000000UL) -#define FEMC_CTRL_BTO_SHIFT (24U) -#define FEMC_CTRL_BTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_BTO_SHIFT) & FEMC_CTRL_BTO_MASK) -#define FEMC_CTRL_BTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_BTO_MASK) >> FEMC_CTRL_BTO_SHIFT) - -/* - * CTO (RW) - * - * Command Execution timeout cycles - * When Command Execution time exceed this timeout cycles, IPCMDERR or AXICMDERR interrupt is - * generated. When CTO is set to zero, timeout cycle is 256*1024 cycle. otherwisee timeout cycle is - * CTO*1024 cycle. - */ -#define FEMC_CTRL_CTO_MASK (0xFF0000UL) -#define FEMC_CTRL_CTO_SHIFT (16U) -#define FEMC_CTRL_CTO_SET(x) (((uint32_t)(x) << FEMC_CTRL_CTO_SHIFT) & FEMC_CTRL_CTO_MASK) -#define FEMC_CTRL_CTO_GET(x) (((uint32_t)(x) & FEMC_CTRL_CTO_MASK) >> FEMC_CTRL_CTO_SHIFT) - -/* - * DQS (RW) - * - * DQS (read strobe) mode - * 0b - Dummy read strobe loopbacked internally - * 1b - Dummy read strobe loopbacked from DQS pad - */ -#define FEMC_CTRL_DQS_MASK (0x4U) -#define FEMC_CTRL_DQS_SHIFT (2U) -#define FEMC_CTRL_DQS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DQS_SHIFT) & FEMC_CTRL_DQS_MASK) -#define FEMC_CTRL_DQS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DQS_MASK) >> FEMC_CTRL_DQS_SHIFT) - -/* - * DIS (RW) - * - * Module Disable - * 0b - Module enabled - * 1b - Module disabled - */ -#define FEMC_CTRL_DIS_MASK (0x2U) -#define FEMC_CTRL_DIS_SHIFT (1U) -#define FEMC_CTRL_DIS_SET(x) (((uint32_t)(x) << FEMC_CTRL_DIS_SHIFT) & FEMC_CTRL_DIS_MASK) -#define FEMC_CTRL_DIS_GET(x) (((uint32_t)(x) & FEMC_CTRL_DIS_MASK) >> FEMC_CTRL_DIS_SHIFT) - -/* - * RST (RW) - * - * Software Reset - * Reset all internal logic in SEMC except configuration register - */ -#define FEMC_CTRL_RST_MASK (0x1U) -#define FEMC_CTRL_RST_SHIFT (0U) -#define FEMC_CTRL_RST_SET(x) (((uint32_t)(x) << FEMC_CTRL_RST_SHIFT) & FEMC_CTRL_RST_MASK) -#define FEMC_CTRL_RST_GET(x) (((uint32_t)(x) & FEMC_CTRL_RST_MASK) >> FEMC_CTRL_RST_SHIFT) - -/* Bitfield definition for register: IOCTRL */ -/* - * IO_CSX (RW) - * - * IO_CSX output selection - * 0001b - SDRAM CS1 - * 0110b - SRAM CE# - */ -#define FEMC_IOCTRL_IO_CSX_MASK (0xF0U) -#define FEMC_IOCTRL_IO_CSX_SHIFT (4U) -#define FEMC_IOCTRL_IO_CSX_SET(x) (((uint32_t)(x) << FEMC_IOCTRL_IO_CSX_SHIFT) & FEMC_IOCTRL_IO_CSX_MASK) -#define FEMC_IOCTRL_IO_CSX_GET(x) (((uint32_t)(x) & FEMC_IOCTRL_IO_CSX_MASK) >> FEMC_IOCTRL_IO_CSX_SHIFT) - -/* Bitfield definition for register: BMW0 */ -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define FEMC_BMW0_RWS_MASK (0xFF0000UL) -#define FEMC_BMW0_RWS_SHIFT (16U) -#define FEMC_BMW0_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW0_RWS_SHIFT) & FEMC_BMW0_RWS_MASK) -#define FEMC_BMW0_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW0_RWS_MASK) >> FEMC_BMW0_RWS_SHIFT) - -/* - * SH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define FEMC_BMW0_SH_MASK (0xFF00U) -#define FEMC_BMW0_SH_SHIFT (8U) -#define FEMC_BMW0_SH_SET(x) (((uint32_t)(x) << FEMC_BMW0_SH_SHIFT) & FEMC_BMW0_SH_MASK) -#define FEMC_BMW0_SH_GET(x) (((uint32_t)(x) & FEMC_BMW0_SH_MASK) >> FEMC_BMW0_SH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define FEMC_BMW0_AGE_MASK (0xF0U) -#define FEMC_BMW0_AGE_SHIFT (4U) -#define FEMC_BMW0_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW0_AGE_SHIFT) & FEMC_BMW0_AGE_MASK) -#define FEMC_BMW0_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW0_AGE_MASK) >> FEMC_BMW0_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define FEMC_BMW0_QOS_MASK (0xFU) -#define FEMC_BMW0_QOS_SHIFT (0U) -#define FEMC_BMW0_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW0_QOS_SHIFT) & FEMC_BMW0_QOS_MASK) -#define FEMC_BMW0_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW0_QOS_MASK) >> FEMC_BMW0_QOS_SHIFT) - -/* Bitfield definition for register: BMW1 */ -/* - * BR (RW) - * - * Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current - * executing command. - */ -#define FEMC_BMW1_BR_MASK (0xFF000000UL) -#define FEMC_BMW1_BR_SHIFT (24U) -#define FEMC_BMW1_BR_SET(x) (((uint32_t)(x) << FEMC_BMW1_BR_SHIFT) & FEMC_BMW1_BR_MASK) -#define FEMC_BMW1_BR_GET(x) (((uint32_t)(x) & FEMC_BMW1_BR_MASK) >> FEMC_BMW1_BR_SHIFT) - -/* - * RWS (RW) - * - * Weight of slave hit with Read/Write Switch. This weight score is valid when queue command's slave is - * same as current executing command with read/write operation switch. - */ -#define FEMC_BMW1_RWS_MASK (0xFF0000UL) -#define FEMC_BMW1_RWS_SHIFT (16U) -#define FEMC_BMW1_RWS_SET(x) (((uint32_t)(x) << FEMC_BMW1_RWS_SHIFT) & FEMC_BMW1_RWS_MASK) -#define FEMC_BMW1_RWS_GET(x) (((uint32_t)(x) & FEMC_BMW1_RWS_MASK) >> FEMC_BMW1_RWS_SHIFT) - -/* - * PH (RW) - * - * Weight of Slave Hit without read/write switch. This weight score is valid when queue command's slave is - * same as current executing command without read/write operation switch. - */ -#define FEMC_BMW1_PH_MASK (0xFF00U) -#define FEMC_BMW1_PH_SHIFT (8U) -#define FEMC_BMW1_PH_SET(x) (((uint32_t)(x) << FEMC_BMW1_PH_SHIFT) & FEMC_BMW1_PH_MASK) -#define FEMC_BMW1_PH_GET(x) (((uint32_t)(x) & FEMC_BMW1_PH_MASK) >> FEMC_BMW1_PH_SHIFT) - -/* - * AGE (RW) - * - * Weight of AGE calculation. Each command in queue has an age signal to indicate its wait period. It is - * multiplied by WAGE to get weight score. - */ -#define FEMC_BMW1_AGE_MASK (0xF0U) -#define FEMC_BMW1_AGE_SHIFT (4U) -#define FEMC_BMW1_AGE_SET(x) (((uint32_t)(x) << FEMC_BMW1_AGE_SHIFT) & FEMC_BMW1_AGE_MASK) -#define FEMC_BMW1_AGE_GET(x) (((uint32_t)(x) & FEMC_BMW1_AGE_MASK) >> FEMC_BMW1_AGE_SHIFT) - -/* - * QOS (RW) - * - * Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a priority indicator - * for the associated write or read transaction. A higher value indicates a higher priority transaction. AxQOS - * is multiplied by WQOS to get weight score. - */ -#define FEMC_BMW1_QOS_MASK (0xFU) -#define FEMC_BMW1_QOS_SHIFT (0U) -#define FEMC_BMW1_QOS_SET(x) (((uint32_t)(x) << FEMC_BMW1_QOS_SHIFT) & FEMC_BMW1_QOS_MASK) -#define FEMC_BMW1_QOS_GET(x) (((uint32_t)(x) & FEMC_BMW1_QOS_MASK) >> FEMC_BMW1_QOS_SHIFT) - -/* Bitfield definition for register array: BR */ -/* - * BASE (RW) - * - * Base Address - * This field determines high position 20 bits of SoC level Base Address. SoC level Base Address low - * position 12 bits are all zero. - */ -#define FEMC_BR_BASE_MASK (0xFFFFF000UL) -#define FEMC_BR_BASE_SHIFT (12U) -#define FEMC_BR_BASE_SET(x) (((uint32_t)(x) << FEMC_BR_BASE_SHIFT) & FEMC_BR_BASE_MASK) -#define FEMC_BR_BASE_GET(x) (((uint32_t)(x) & FEMC_BR_BASE_MASK) >> FEMC_BR_BASE_SHIFT) - -/* - * SIZE (RW) - * - * Memory size - * 00000b - 4KB - * 00001b - 8KB - * 00010b - 16KB - * 00011b - 32KB - * 00100b - 64KB - * 00101b - 128KB - * 00110b - 256KB - * 00111b - 512KB - * 01000b - 1MB - * 01001b - 2MB - * 01010b - 4MB - * 01011b - 8MB - * 01100b - 16MB - * 01101b - 32MB - * 01110b - 64MB - * 01111b - 128MB - * 10000b - 256MB - * 10001b - 512MB - * 10010b - 1GB - * 10011b - 2GB - * 10100-11111b - 4GB - */ -#define FEMC_BR_SIZE_MASK (0x3EU) -#define FEMC_BR_SIZE_SHIFT (1U) -#define FEMC_BR_SIZE_SET(x) (((uint32_t)(x) << FEMC_BR_SIZE_SHIFT) & FEMC_BR_SIZE_MASK) -#define FEMC_BR_SIZE_GET(x) (((uint32_t)(x) & FEMC_BR_SIZE_MASK) >> FEMC_BR_SIZE_SHIFT) - -/* - * VLD (RW) - * - * Valid - */ -#define FEMC_BR_VLD_MASK (0x1U) -#define FEMC_BR_VLD_SHIFT (0U) -#define FEMC_BR_VLD_SET(x) (((uint32_t)(x) << FEMC_BR_VLD_SHIFT) & FEMC_BR_VLD_MASK) -#define FEMC_BR_VLD_GET(x) (((uint32_t)(x) & FEMC_BR_VLD_MASK) >> FEMC_BR_VLD_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * AXIBUSERR (RW) - * - * AXI BUS error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_AXIBUSERR_MASK (0x8U) -#define FEMC_INTEN_AXIBUSERR_SHIFT (3U) -#define FEMC_INTEN_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXIBUSERR_SHIFT) & FEMC_INTEN_AXIBUSERR_MASK) -#define FEMC_INTEN_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXIBUSERR_MASK) >> FEMC_INTEN_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (RW) - * - * AXI command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_AXICMDERR_MASK (0x4U) -#define FEMC_INTEN_AXICMDERR_SHIFT (2U) -#define FEMC_INTEN_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_AXICMDERR_SHIFT) & FEMC_INTEN_AXICMDERR_MASK) -#define FEMC_INTEN_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_AXICMDERR_MASK) >> FEMC_INTEN_AXICMDERR_SHIFT) - -/* - * IPCMDERR (RW) - * - * IP command error interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_IPCMDERR_MASK (0x2U) -#define FEMC_INTEN_IPCMDERR_SHIFT (1U) -#define FEMC_INTEN_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDERR_SHIFT) & FEMC_INTEN_IPCMDERR_MASK) -#define FEMC_INTEN_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDERR_MASK) >> FEMC_INTEN_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (RW) - * - * IP command done interrupt enable - * 0b - Interrupt is disabled - * 1b - Interrupt is enabled - */ -#define FEMC_INTEN_IPCMDDONE_MASK (0x1U) -#define FEMC_INTEN_IPCMDDONE_SHIFT (0U) -#define FEMC_INTEN_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTEN_IPCMDDONE_SHIFT) & FEMC_INTEN_IPCMDDONE_MASK) -#define FEMC_INTEN_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTEN_IPCMDDONE_MASK) >> FEMC_INTEN_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: INTR */ -/* - * AXIBUSERR (W1C) - * - * AXI bus error interrupt - * AXI Bus error interrupt is generated in following cases: - * • AXI address is invalid - * • AXI 8-bit or 16-bit WRAP write/read - */ -#define FEMC_INTR_AXIBUSERR_MASK (0x8U) -#define FEMC_INTR_AXIBUSERR_SHIFT (3U) -#define FEMC_INTR_AXIBUSERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXIBUSERR_SHIFT) & FEMC_INTR_AXIBUSERR_MASK) -#define FEMC_INTR_AXIBUSERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXIBUSERR_MASK) >> FEMC_INTR_AXIBUSERR_SHIFT) - -/* - * AXICMDERR (W1C) - * - * AXI command error interrupt - * AXI command error interrupt is generated when AXI command execution timeout. - */ -#define FEMC_INTR_AXICMDERR_MASK (0x4U) -#define FEMC_INTR_AXICMDERR_SHIFT (2U) -#define FEMC_INTR_AXICMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_AXICMDERR_SHIFT) & FEMC_INTR_AXICMDERR_MASK) -#define FEMC_INTR_AXICMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_AXICMDERR_MASK) >> FEMC_INTR_AXICMDERR_SHIFT) - -/* - * IPCMDERR (W1C) - * - * IP command error done interrupt - * IP command error interrupt is generated in following case: - * • IP Command Address target invalid device space - * • IP Command Code unsupported - * • IP Command triggered when previous command - */ -#define FEMC_INTR_IPCMDERR_MASK (0x2U) -#define FEMC_INTR_IPCMDERR_SHIFT (1U) -#define FEMC_INTR_IPCMDERR_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDERR_SHIFT) & FEMC_INTR_IPCMDERR_MASK) -#define FEMC_INTR_IPCMDERR_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDERR_MASK) >> FEMC_INTR_IPCMDERR_SHIFT) - -/* - * IPCMDDONE (W1C) - * - * IP command normal done interrupt - */ -#define FEMC_INTR_IPCMDDONE_MASK (0x1U) -#define FEMC_INTR_IPCMDDONE_SHIFT (0U) -#define FEMC_INTR_IPCMDDONE_SET(x) (((uint32_t)(x) << FEMC_INTR_IPCMDDONE_SHIFT) & FEMC_INTR_IPCMDDONE_MASK) -#define FEMC_INTR_IPCMDDONE_GET(x) (((uint32_t)(x) & FEMC_INTR_IPCMDDONE_MASK) >> FEMC_INTR_IPCMDDONE_SHIFT) - -/* Bitfield definition for register: SDRCTRL0 */ -/* - * BANK2 (RW) - * - * 2 Bank selection bit - * 0b - SDRAM device has 4 banks. - * 1b - SDRAM device has 2 banks. - */ -#define FEMC_SDRCTRL0_BANK2_MASK (0x4000U) -#define FEMC_SDRCTRL0_BANK2_SHIFT (14U) -#define FEMC_SDRCTRL0_BANK2_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BANK2_SHIFT) & FEMC_SDRCTRL0_BANK2_MASK) -#define FEMC_SDRCTRL0_BANK2_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BANK2_MASK) >> FEMC_SDRCTRL0_BANK2_SHIFT) - -/* - * CAS (RW) - * - * CAS Latency - * 00b - 1 - * 01b - 1 - * 10b - 2 - * 11b - 3 - */ -#define FEMC_SDRCTRL0_CAS_MASK (0xC00U) -#define FEMC_SDRCTRL0_CAS_SHIFT (10U) -#define FEMC_SDRCTRL0_CAS_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_CAS_SHIFT) & FEMC_SDRCTRL0_CAS_MASK) -#define FEMC_SDRCTRL0_CAS_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_CAS_MASK) >> FEMC_SDRCTRL0_CAS_SHIFT) - -/* - * COL (RW) - * - * Column address bit number - * 00b - 12 bit - * 01b - 11 bit - * 10b - 10 bit - * 11b - 9 bit - */ -#define FEMC_SDRCTRL0_COL_MASK (0x300U) -#define FEMC_SDRCTRL0_COL_SHIFT (8U) -#define FEMC_SDRCTRL0_COL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL_SHIFT) & FEMC_SDRCTRL0_COL_MASK) -#define FEMC_SDRCTRL0_COL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL_MASK) >> FEMC_SDRCTRL0_COL_SHIFT) - -/* - * COL8 (RW) - * - * Column 8 selection bit - * 0b - Column address bit number is decided by COL field. - * 1b - Column address bit number is 8. COL field is ignored. - */ -#define FEMC_SDRCTRL0_COL8_MASK (0x80U) -#define FEMC_SDRCTRL0_COL8_SHIFT (7U) -#define FEMC_SDRCTRL0_COL8_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_COL8_SHIFT) & FEMC_SDRCTRL0_COL8_MASK) -#define FEMC_SDRCTRL0_COL8_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_COL8_MASK) >> FEMC_SDRCTRL0_COL8_SHIFT) - -/* - * BURSTLEN (RW) - * - * Burst Length - * 000b - 1 - * 001b - 2 - * 010b - 4 - * 011b - 8 - * 100b - 8 - * 101b - 8 - * 110b - 8 - * 111b - 8 - */ -#define FEMC_SDRCTRL0_BURSTLEN_MASK (0x70U) -#define FEMC_SDRCTRL0_BURSTLEN_SHIFT (4U) -#define FEMC_SDRCTRL0_BURSTLEN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_BURSTLEN_SHIFT) & FEMC_SDRCTRL0_BURSTLEN_MASK) -#define FEMC_SDRCTRL0_BURSTLEN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_BURSTLEN_MASK) >> FEMC_SDRCTRL0_BURSTLEN_SHIFT) - -/* - * HIGHBAND (RW) - * - * high band select - * 0: use data[15:0] for 16bit SDRAM; - * 1: use data[31:16] for 16bit SDRAM; - * only used when Port Size is 16bit(PORTSZ=01b) - */ -#define FEMC_SDRCTRL0_HIGHBAND_MASK (0x8U) -#define FEMC_SDRCTRL0_HIGHBAND_SHIFT (3U) -#define FEMC_SDRCTRL0_HIGHBAND_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_HIGHBAND_SHIFT) & FEMC_SDRCTRL0_HIGHBAND_MASK) -#define FEMC_SDRCTRL0_HIGHBAND_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_HIGHBAND_MASK) >> FEMC_SDRCTRL0_HIGHBAND_SHIFT) - -/* - * PORTSZ (RW) - * - * Port Size - * 00b - 8bit - * 01b - 16bit - * 10b - 32bit - */ -#define FEMC_SDRCTRL0_PORTSZ_MASK (0x3U) -#define FEMC_SDRCTRL0_PORTSZ_SHIFT (0U) -#define FEMC_SDRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL0_PORTSZ_SHIFT) & FEMC_SDRCTRL0_PORTSZ_MASK) -#define FEMC_SDRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL0_PORTSZ_MASK) >> FEMC_SDRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SDRCTRL1 */ -/* - * ACT2PRE (RW) - * - * ACT to Precharge minimum time - * It is promised ACT2PRE+1 clock cycles delay between ACTIVE command to PRECHARGE/PRECHARGE_ALL command. - */ -#define FEMC_SDRCTRL1_ACT2PRE_MASK (0xF00000UL) -#define FEMC_SDRCTRL1_ACT2PRE_SHIFT (20U) -#define FEMC_SDRCTRL1_ACT2PRE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2PRE_SHIFT) & FEMC_SDRCTRL1_ACT2PRE_MASK) -#define FEMC_SDRCTRL1_ACT2PRE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2PRE_MASK) >> FEMC_SDRCTRL1_ACT2PRE_SHIFT) - -/* - * CKEOFF (RW) - * - * CKE OFF minimum time - * It is promised clock suspend last at leat CKEOFF+1 clock cycles. - */ -#define FEMC_SDRCTRL1_CKEOFF_MASK (0xF0000UL) -#define FEMC_SDRCTRL1_CKEOFF_SHIFT (16U) -#define FEMC_SDRCTRL1_CKEOFF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_CKEOFF_SHIFT) & FEMC_SDRCTRL1_CKEOFF_MASK) -#define FEMC_SDRCTRL1_CKEOFF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_CKEOFF_MASK) >> FEMC_SDRCTRL1_CKEOFF_SHIFT) - -/* - * WRC (RW) - * - * Write recovery time - * It is promised WRC+1 clock cycles delay between WRITE command to PRECHARGE/PRECHARGE_ALL command. This could help to meet tWR timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_WRC_MASK (0xE000U) -#define FEMC_SDRCTRL1_WRC_SHIFT (13U) -#define FEMC_SDRCTRL1_WRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_WRC_SHIFT) & FEMC_SDRCTRL1_WRC_MASK) -#define FEMC_SDRCTRL1_WRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_WRC_MASK) >> FEMC_SDRCTRL1_WRC_SHIFT) - -/* - * RFRC (RW) - * - * Refresh recovery time - * It is promised RFRC+1 clock cycles delay between REFRESH command to ACTIVE command. Thiscould help to meet tRFC timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_RFRC_MASK (0x1F00U) -#define FEMC_SDRCTRL1_RFRC_SHIFT (8U) -#define FEMC_SDRCTRL1_RFRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_RFRC_SHIFT) & FEMC_SDRCTRL1_RFRC_MASK) -#define FEMC_SDRCTRL1_RFRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_RFRC_MASK) >> FEMC_SDRCTRL1_RFRC_SHIFT) - -/* - * ACT2RW (RW) - * - * ACT to Read/Write wait time - * It is promised ACT2RW+1 clock cycles delay between ACTIVE command to READ/WRITE command.This could help to meet tRCD timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_ACT2RW_MASK (0xF0U) -#define FEMC_SDRCTRL1_ACT2RW_SHIFT (4U) -#define FEMC_SDRCTRL1_ACT2RW_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_ACT2RW_SHIFT) & FEMC_SDRCTRL1_ACT2RW_MASK) -#define FEMC_SDRCTRL1_ACT2RW_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_ACT2RW_MASK) >> FEMC_SDRCTRL1_ACT2RW_SHIFT) - -/* - * PRE2ACT (RW) - * - * PRECHARGE to ACT/Refresh wait time - * It is promised PRE2ACT+1 clock cycles delay between PRECHARGE/PRECHARGE_ALL commandto ACTIVE/REFRESH command. This could help to meet tRP timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL1_PRE2ACT_MASK (0xFU) -#define FEMC_SDRCTRL1_PRE2ACT_SHIFT (0U) -#define FEMC_SDRCTRL1_PRE2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL1_PRE2ACT_SHIFT) & FEMC_SDRCTRL1_PRE2ACT_MASK) -#define FEMC_SDRCTRL1_PRE2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL1_PRE2ACT_MASK) >> FEMC_SDRCTRL1_PRE2ACT_SHIFT) - -/* Bitfield definition for register: SDRCTRL2 */ -/* - * ITO (RW) - * - * SDRAM Idle timeout - * It closes all opened pages if the SDRAM idle time lasts more than idle timeout period. SDRAM is - * considered idle when there is no AXI Bus transfer and no SDRAM command pending. - * 00000000b - IDLE timeout period is 256*Prescale period. - * 00000001-11111111b - IDLE timeout period is ITO*Prescale period. - */ -#define FEMC_SDRCTRL2_ITO_MASK (0xFF000000UL) -#define FEMC_SDRCTRL2_ITO_SHIFT (24U) -#define FEMC_SDRCTRL2_ITO_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ITO_SHIFT) & FEMC_SDRCTRL2_ITO_MASK) -#define FEMC_SDRCTRL2_ITO_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ITO_MASK) >> FEMC_SDRCTRL2_ITO_SHIFT) - -/* - * ACT2ACT (RW) - * - * ACT to ACT wait time - * It is promised ACT2ACT+1 clock cycles delay between ACTIVE command to ACTIVE command. This - * could help to meet tRRD timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL2_ACT2ACT_MASK (0xFF0000UL) -#define FEMC_SDRCTRL2_ACT2ACT_SHIFT (16U) -#define FEMC_SDRCTRL2_ACT2ACT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_ACT2ACT_SHIFT) & FEMC_SDRCTRL2_ACT2ACT_MASK) -#define FEMC_SDRCTRL2_ACT2ACT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_ACT2ACT_MASK) >> FEMC_SDRCTRL2_ACT2ACT_SHIFT) - -/* - * REF2REF (RW) - * - * Refresh to Refresh wait time - * It is promised REF2REF+1 clock cycles delay between REFRESH command to REFRESH command. - * This could help to meet tRFC timing requirement by SDRAM device. - */ -#define FEMC_SDRCTRL2_REF2REF_MASK (0xFF00U) -#define FEMC_SDRCTRL2_REF2REF_SHIFT (8U) -#define FEMC_SDRCTRL2_REF2REF_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_REF2REF_SHIFT) & FEMC_SDRCTRL2_REF2REF_MASK) -#define FEMC_SDRCTRL2_REF2REF_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_REF2REF_MASK) >> FEMC_SDRCTRL2_REF2REF_SHIFT) - -/* - * SRRC (RW) - * - * Self Refresh Recovery time - * It is promised SRRC+1 clock cycles delay between Self-REFRESH command to any command. - */ -#define FEMC_SDRCTRL2_SRRC_MASK (0xFFU) -#define FEMC_SDRCTRL2_SRRC_SHIFT (0U) -#define FEMC_SDRCTRL2_SRRC_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL2_SRRC_SHIFT) & FEMC_SDRCTRL2_SRRC_MASK) -#define FEMC_SDRCTRL2_SRRC_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL2_SRRC_MASK) >> FEMC_SDRCTRL2_SRRC_SHIFT) - -/* Bitfield definition for register: SDRCTRL3 */ -/* - * UT (RW) - * - * Refresh urgent threshold - * Internal refresh request is generated on every Refresh period. Before internal request timer count up to - * urgent request threshold, the refresh request is considered as normal refresh request. Normal refresh - * request is handled in lower priority than any pending AXI command or IP command to SDRAM device. - * When internal request timer count up to this urgent threshold, refresh request is considered as urgent - * refresh request. Urgent refresh request is handled in higher priority than any pending AXI command or IP - * command to SDRAM device. - * NOTE: When urgent threshold is no less than refresh period, refresh request is always considered as - * urgent refresh request. - * Refresh urgent threshold is as follwoing: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - UT*Prescaler period - */ -#define FEMC_SDRCTRL3_UT_MASK (0xFF000000UL) -#define FEMC_SDRCTRL3_UT_SHIFT (24U) -#define FEMC_SDRCTRL3_UT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_UT_SHIFT) & FEMC_SDRCTRL3_UT_MASK) -#define FEMC_SDRCTRL3_UT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_UT_MASK) >> FEMC_SDRCTRL3_UT_SHIFT) - -/* - * RT (RW) - * - * Refresh timer period - * Refresh timer period is as following: - * 00000000b - 256*Prescaler period - * 00000001-11111111b - RT*Prescaler period - */ -#define FEMC_SDRCTRL3_RT_MASK (0xFF0000UL) -#define FEMC_SDRCTRL3_RT_SHIFT (16U) -#define FEMC_SDRCTRL3_RT_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_RT_SHIFT) & FEMC_SDRCTRL3_RT_MASK) -#define FEMC_SDRCTRL3_RT_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_RT_MASK) >> FEMC_SDRCTRL3_RT_SHIFT) - -/* - * PRESCALE (RW) - * - * Prescaler timer period - * Prescaler timer period is as following: - * 00000000b - 256*16 clock cycles - * 00000001-11111111b - PRESCALE*16 clock cycles - */ -#define FEMC_SDRCTRL3_PRESCALE_MASK (0xFF00U) -#define FEMC_SDRCTRL3_PRESCALE_SHIFT (8U) -#define FEMC_SDRCTRL3_PRESCALE_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_PRESCALE_SHIFT) & FEMC_SDRCTRL3_PRESCALE_MASK) -#define FEMC_SDRCTRL3_PRESCALE_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_PRESCALE_MASK) >> FEMC_SDRCTRL3_PRESCALE_SHIFT) - -/* - * REBL (RW) - * - * Refresh burst length - * It could send multiple Auto-Refresh command in one burst when REBL is set to non-zero. The - * number of Auto-Refresh command cycle sent to all SDRAM device in one refresh period is as following. - * 000b - 1 - * 001b - 2 - * 010b - 3 - * 011b - 4 - * 100b - 5 - * 101b - 6 - * 110b - 7 - * 111b - 8 - */ -#define FEMC_SDRCTRL3_REBL_MASK (0xEU) -#define FEMC_SDRCTRL3_REBL_SHIFT (1U) -#define FEMC_SDRCTRL3_REBL_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REBL_SHIFT) & FEMC_SDRCTRL3_REBL_MASK) -#define FEMC_SDRCTRL3_REBL_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REBL_MASK) >> FEMC_SDRCTRL3_REBL_SHIFT) - -/* - * REN (RW) - * - * Refresh enable - */ -#define FEMC_SDRCTRL3_REN_MASK (0x1U) -#define FEMC_SDRCTRL3_REN_SHIFT (0U) -#define FEMC_SDRCTRL3_REN_SET(x) (((uint32_t)(x) << FEMC_SDRCTRL3_REN_SHIFT) & FEMC_SDRCTRL3_REN_MASK) -#define FEMC_SDRCTRL3_REN_GET(x) (((uint32_t)(x) & FEMC_SDRCTRL3_REN_MASK) >> FEMC_SDRCTRL3_REN_SHIFT) - -/* Bitfield definition for register: SRCTRL0 */ -/* - * ADVH (RW) - * - * ADV hold state - * 0b - ADV is high during address hold state - * 1b - ADV is low during address hold state - */ -#define FEMC_SRCTRL0_ADVH_MASK (0x800U) -#define FEMC_SRCTRL0_ADVH_SHIFT (11U) -#define FEMC_SRCTRL0_ADVH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVH_SHIFT) & FEMC_SRCTRL0_ADVH_MASK) -#define FEMC_SRCTRL0_ADVH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVH_MASK) >> FEMC_SRCTRL0_ADVH_SHIFT) - -/* - * ADVP (RW) - * - * ADV polarity - * 0b - ADV is active low - * 1b - ADV is active high - */ -#define FEMC_SRCTRL0_ADVP_MASK (0x400U) -#define FEMC_SRCTRL0_ADVP_SHIFT (10U) -#define FEMC_SRCTRL0_ADVP_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADVP_SHIFT) & FEMC_SRCTRL0_ADVP_MASK) -#define FEMC_SRCTRL0_ADVP_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADVP_MASK) >> FEMC_SRCTRL0_ADVP_SHIFT) - -/* - * ADM (RW) - * - * address data mode - * 00b - address and data MUX mode - * 11b - address and data non-MUX mode - */ -#define FEMC_SRCTRL0_ADM_MASK (0x300U) -#define FEMC_SRCTRL0_ADM_SHIFT (8U) -#define FEMC_SRCTRL0_ADM_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_ADM_SHIFT) & FEMC_SRCTRL0_ADM_MASK) -#define FEMC_SRCTRL0_ADM_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_ADM_MASK) >> FEMC_SRCTRL0_ADM_SHIFT) - -/* - * PORTSZ (RW) - * - * port size - * 0b - 8bit - * 1b - 16bit - */ -#define FEMC_SRCTRL0_PORTSZ_MASK (0x1U) -#define FEMC_SRCTRL0_PORTSZ_SHIFT (0U) -#define FEMC_SRCTRL0_PORTSZ_SET(x) (((uint32_t)(x) << FEMC_SRCTRL0_PORTSZ_SHIFT) & FEMC_SRCTRL0_PORTSZ_MASK) -#define FEMC_SRCTRL0_PORTSZ_GET(x) (((uint32_t)(x) & FEMC_SRCTRL0_PORTSZ_MASK) >> FEMC_SRCTRL0_PORTSZ_SHIFT) - -/* Bitfield definition for register: SRCTRL1 */ -/* - * OEH (RW) - * - * OE high time, is OEH+1 clock cycles - */ -#define FEMC_SRCTRL1_OEH_MASK (0xF0000000UL) -#define FEMC_SRCTRL1_OEH_SHIFT (28U) -#define FEMC_SRCTRL1_OEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEH_SHIFT) & FEMC_SRCTRL1_OEH_MASK) -#define FEMC_SRCTRL1_OEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEH_MASK) >> FEMC_SRCTRL1_OEH_SHIFT) - -/* - * OEL (RW) - * - * OE low time, is OEL+1 clock cycles - */ -#define FEMC_SRCTRL1_OEL_MASK (0xF000000UL) -#define FEMC_SRCTRL1_OEL_SHIFT (24U) -#define FEMC_SRCTRL1_OEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_OEL_SHIFT) & FEMC_SRCTRL1_OEL_MASK) -#define FEMC_SRCTRL1_OEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_OEL_MASK) >> FEMC_SRCTRL1_OEL_SHIFT) - -/* - * WEH (RW) - * - * WE high time, is WEH+1 clock cycles - */ -#define FEMC_SRCTRL1_WEH_MASK (0xF00000UL) -#define FEMC_SRCTRL1_WEH_SHIFT (20U) -#define FEMC_SRCTRL1_WEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEH_SHIFT) & FEMC_SRCTRL1_WEH_MASK) -#define FEMC_SRCTRL1_WEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEH_MASK) >> FEMC_SRCTRL1_WEH_SHIFT) - -/* - * WEL (RW) - * - * WE low time, is WEL+1 clock cycles - */ -#define FEMC_SRCTRL1_WEL_MASK (0xF0000UL) -#define FEMC_SRCTRL1_WEL_SHIFT (16U) -#define FEMC_SRCTRL1_WEL_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_WEL_SHIFT) & FEMC_SRCTRL1_WEL_MASK) -#define FEMC_SRCTRL1_WEL_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_WEL_MASK) >> FEMC_SRCTRL1_WEL_SHIFT) - -/* - * AH (RW) - * - * Address hold time, is AH+1 clock cycles - */ -#define FEMC_SRCTRL1_AH_MASK (0xF000U) -#define FEMC_SRCTRL1_AH_SHIFT (12U) -#define FEMC_SRCTRL1_AH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AH_SHIFT) & FEMC_SRCTRL1_AH_MASK) -#define FEMC_SRCTRL1_AH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AH_MASK) >> FEMC_SRCTRL1_AH_SHIFT) - -/* - * AS (RW) - * - * Address setup time, is AS+1 clock cycles - */ -#define FEMC_SRCTRL1_AS_MASK (0xF00U) -#define FEMC_SRCTRL1_AS_SHIFT (8U) -#define FEMC_SRCTRL1_AS_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_AS_SHIFT) & FEMC_SRCTRL1_AS_MASK) -#define FEMC_SRCTRL1_AS_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_AS_MASK) >> FEMC_SRCTRL1_AS_SHIFT) - -/* - * CEH (RW) - * - * Chip enable hold time, is CEH+1 clock cycles - */ -#define FEMC_SRCTRL1_CEH_MASK (0xF0U) -#define FEMC_SRCTRL1_CEH_SHIFT (4U) -#define FEMC_SRCTRL1_CEH_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CEH_SHIFT) & FEMC_SRCTRL1_CEH_MASK) -#define FEMC_SRCTRL1_CEH_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CEH_MASK) >> FEMC_SRCTRL1_CEH_SHIFT) - -/* - * CES (RW) - * - * Chip enable setup time, is CES+1 clock cycles - */ -#define FEMC_SRCTRL1_CES_MASK (0xFU) -#define FEMC_SRCTRL1_CES_SHIFT (0U) -#define FEMC_SRCTRL1_CES_SET(x) (((uint32_t)(x) << FEMC_SRCTRL1_CES_SHIFT) & FEMC_SRCTRL1_CES_MASK) -#define FEMC_SRCTRL1_CES_GET(x) (((uint32_t)(x) & FEMC_SRCTRL1_CES_MASK) >> FEMC_SRCTRL1_CES_SHIFT) - -/* Bitfield definition for register: SADDR */ -/* - * SA (RW) - * - * Slave address - */ -#define FEMC_SADDR_SA_MASK (0xFFFFFFFFUL) -#define FEMC_SADDR_SA_SHIFT (0U) -#define FEMC_SADDR_SA_SET(x) (((uint32_t)(x) << FEMC_SADDR_SA_SHIFT) & FEMC_SADDR_SA_MASK) -#define FEMC_SADDR_SA_GET(x) (((uint32_t)(x) & FEMC_SADDR_SA_MASK) >> FEMC_SADDR_SA_SHIFT) - -/* Bitfield definition for register: DATSZ */ -/* - * DATSZ (RW) - * - * Data Size in Byte - * When IP command is not a write/read operation, DATSZ field would be ignored. - * 000b - 4 - * 001b - 1 - * 010b - 2 - * 011b - 3 - * 100b - 4 - * 101b - 4 - * 110b - 4 - * 111b - 4 - */ -#define FEMC_DATSZ_DATSZ_MASK (0x7U) -#define FEMC_DATSZ_DATSZ_SHIFT (0U) -#define FEMC_DATSZ_DATSZ_SET(x) (((uint32_t)(x) << FEMC_DATSZ_DATSZ_SHIFT) & FEMC_DATSZ_DATSZ_MASK) -#define FEMC_DATSZ_DATSZ_GET(x) (((uint32_t)(x) & FEMC_DATSZ_DATSZ_MASK) >> FEMC_DATSZ_DATSZ_SHIFT) - -/* Bitfield definition for register: BYTEMSK */ -/* - * BM3 (RW) - * - * Byte Mask for Byte 3 (IPTXD bit 31:24) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM3_MASK (0x8U) -#define FEMC_BYTEMSK_BM3_SHIFT (3U) -#define FEMC_BYTEMSK_BM3_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM3_SHIFT) & FEMC_BYTEMSK_BM3_MASK) -#define FEMC_BYTEMSK_BM3_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM3_MASK) >> FEMC_BYTEMSK_BM3_SHIFT) - -/* - * BM2 (RW) - * - * Byte Mask for Byte 2 (IPTXD bit 23:16) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM2_MASK (0x4U) -#define FEMC_BYTEMSK_BM2_SHIFT (2U) -#define FEMC_BYTEMSK_BM2_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM2_SHIFT) & FEMC_BYTEMSK_BM2_MASK) -#define FEMC_BYTEMSK_BM2_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM2_MASK) >> FEMC_BYTEMSK_BM2_SHIFT) - -/* - * BM1 (RW) - * - * Byte Mask for Byte 1 (IPTXD bit 15:8) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM1_MASK (0x2U) -#define FEMC_BYTEMSK_BM1_SHIFT (1U) -#define FEMC_BYTEMSK_BM1_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM1_SHIFT) & FEMC_BYTEMSK_BM1_MASK) -#define FEMC_BYTEMSK_BM1_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM1_MASK) >> FEMC_BYTEMSK_BM1_SHIFT) - -/* - * BM0 (RW) - * - * Byte Mask for Byte 0 (IPTXD bit 7:0) - * 0b - Byte Unmasked - * 1b - Byte Masked - */ -#define FEMC_BYTEMSK_BM0_MASK (0x1U) -#define FEMC_BYTEMSK_BM0_SHIFT (0U) -#define FEMC_BYTEMSK_BM0_SET(x) (((uint32_t)(x) << FEMC_BYTEMSK_BM0_SHIFT) & FEMC_BYTEMSK_BM0_MASK) -#define FEMC_BYTEMSK_BM0_GET(x) (((uint32_t)(x) & FEMC_BYTEMSK_BM0_MASK) >> FEMC_BYTEMSK_BM0_SHIFT) - -/* Bitfield definition for register: IPCMD */ -/* - * KEY (WO) - * - * This field should be written with 0x5AA5 when trigging an IP command for all device types. The memory - * device is selected by BRx settings and IPCR0 registers. - */ -#define FEMC_IPCMD_KEY_MASK (0xFFFF0000UL) -#define FEMC_IPCMD_KEY_SHIFT (16U) -#define FEMC_IPCMD_KEY_SET(x) (((uint32_t)(x) << FEMC_IPCMD_KEY_SHIFT) & FEMC_IPCMD_KEY_MASK) -#define FEMC_IPCMD_KEY_GET(x) (((uint32_t)(x) & FEMC_IPCMD_KEY_MASK) >> FEMC_IPCMD_KEY_SHIFT) - -/* - * CMD (RW) - * - * SDRAM Commands: - * • 0x8: READ - * • 0x9: WRITE - * • 0xA: MODESET - * • 0xB: ACTIVE - * • 0xC: AUTO REFRESH - * • 0xD: SELF REFRESH - * • 0xE: PRECHARGE - * • 0xF: PRECHARGE ALL - * • Others: RSVD - * NOTE: SELF REFRESH is sent to all SDRAM devices because they shared same CLK pin. - */ -#define FEMC_IPCMD_CMD_MASK (0xFFFFU) -#define FEMC_IPCMD_CMD_SHIFT (0U) -#define FEMC_IPCMD_CMD_SET(x) (((uint32_t)(x) << FEMC_IPCMD_CMD_SHIFT) & FEMC_IPCMD_CMD_MASK) -#define FEMC_IPCMD_CMD_GET(x) (((uint32_t)(x) & FEMC_IPCMD_CMD_MASK) >> FEMC_IPCMD_CMD_SHIFT) - -/* Bitfield definition for register: IPTX */ -/* - * DAT (RW) - * - * Data - */ -#define FEMC_IPTX_DAT_MASK (0xFFFFFFFFUL) -#define FEMC_IPTX_DAT_SHIFT (0U) -#define FEMC_IPTX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPTX_DAT_SHIFT) & FEMC_IPTX_DAT_MASK) -#define FEMC_IPTX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPTX_DAT_MASK) >> FEMC_IPTX_DAT_SHIFT) - -/* Bitfield definition for register: IPRX */ -/* - * DAT (RW) - * - * Data - */ -#define FEMC_IPRX_DAT_MASK (0xFFFFFFFFUL) -#define FEMC_IPRX_DAT_SHIFT (0U) -#define FEMC_IPRX_DAT_SET(x) (((uint32_t)(x) << FEMC_IPRX_DAT_SHIFT) & FEMC_IPRX_DAT_MASK) -#define FEMC_IPRX_DAT_GET(x) (((uint32_t)(x) & FEMC_IPRX_DAT_MASK) >> FEMC_IPRX_DAT_SHIFT) - -/* Bitfield definition for register: STAT0 */ -/* - * IDLE (RO) - * - * Indicating whether it is in IDLE state. - * When IDLE=1, it is in IDLE state. There is no pending AXI command in internal queue and no - * pending device access. - */ -#define FEMC_STAT0_IDLE_MASK (0x1U) -#define FEMC_STAT0_IDLE_SHIFT (0U) -#define FEMC_STAT0_IDLE_GET(x) (((uint32_t)(x) & FEMC_STAT0_IDLE_MASK) >> FEMC_STAT0_IDLE_SHIFT) - -/* Bitfield definition for register: DLYCFG */ -/* - * OE (RW) - * - * delay clock output enable, should be set after setting DLYEN and DLYSEL - */ -#define FEMC_DLYCFG_OE_MASK (0x2000U) -#define FEMC_DLYCFG_OE_SHIFT (13U) -#define FEMC_DLYCFG_OE_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_OE_SHIFT) & FEMC_DLYCFG_OE_MASK) -#define FEMC_DLYCFG_OE_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_OE_MASK) >> FEMC_DLYCFG_OE_SHIFT) - -/* - * DLYSEL (RW) - * - * delay line select, 0 for 1 cell, 31 for all 32 cells - */ -#define FEMC_DLYCFG_DLYSEL_MASK (0x3EU) -#define FEMC_DLYCFG_DLYSEL_SHIFT (1U) -#define FEMC_DLYCFG_DLYSEL_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYSEL_SHIFT) & FEMC_DLYCFG_DLYSEL_MASK) -#define FEMC_DLYCFG_DLYSEL_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYSEL_MASK) >> FEMC_DLYCFG_DLYSEL_SHIFT) - -/* - * DLYEN (RW) - * - * delay line enable - */ -#define FEMC_DLYCFG_DLYEN_MASK (0x1U) -#define FEMC_DLYCFG_DLYEN_SHIFT (0U) -#define FEMC_DLYCFG_DLYEN_SET(x) (((uint32_t)(x) << FEMC_DLYCFG_DLYEN_SHIFT) & FEMC_DLYCFG_DLYEN_MASK) -#define FEMC_DLYCFG_DLYEN_GET(x) (((uint32_t)(x) & FEMC_DLYCFG_DLYEN_MASK) >> FEMC_DLYCFG_DLYEN_SHIFT) - - - -/* BR register group index macro definition */ -#define FEMC_BR_BASE0 (0UL) -#define FEMC_BR_BASE1 (1UL) -#define FEMC_BR_BASE6 (6UL) - - -#endif /* HPM_FEMC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ffa_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ffa_regs.h deleted file mode 100644 index b1e164caf00..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ffa_regs.h +++ /dev/null @@ -1,743 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_FFA_H -#define HPM_FFA_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: */ - __RW uint32_t STATUS; /* 0x4: */ - __RW uint32_t INT_EN; /* 0x8: */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t FP_CTRL; /* 0x10: */ - __RW uint32_t FP_ST; /* 0x14: */ - __R uint8_t RESERVED1[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t OP_CTRL; /* 0x20: */ - __RW uint32_t OP_CMD; /* 0x24: */ - union { - __RW uint32_t OP_REG0; /* 0x28: */ - __RW uint32_t OP_FIR_MISC; /* 0x28: */ - __RW uint32_t OP_FFT_MISC; /* 0x28: */ - }; - union { - __RW uint32_t OP_REG1; /* 0x2C: */ - __RW uint32_t OP_FIR_MISC1; /* 0x2C: */ - }; - union { - __RW uint32_t OP_REG2; /* 0x30: */ - __RW uint32_t OP_FFT_INRBUF; /* 0x30: */ - }; - union { - __RW uint32_t OP_REG3; /* 0x34: */ - __RW uint32_t OP_FIR_INBUF; /* 0x34: */ - }; - union { - __RW uint32_t OP_REG4; /* 0x38: */ - __RW uint32_t OP_FIR_COEFBUF; /* 0x38: */ - __RW uint32_t OP_FFT_OUTRBUF; /* 0x38: */ - }; - union { - __RW uint32_t OP_REG5; /* 0x3C: */ - __RW uint32_t OP_FIR_OUTBUF; /* 0x3C: */ - }; - __RW uint32_t OP_REG6; /* 0x40: */ - __RW uint32_t OP_REG7; /* 0x44: */ -} FFA_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module if asserted to be 1. - * EN is only active after this bit is zero. - */ -#define FFA_CTRL_SFTRST_MASK (0x80000000UL) -#define FFA_CTRL_SFTRST_SHIFT (31U) -#define FFA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << FFA_CTRL_SFTRST_SHIFT) & FFA_CTRL_SFTRST_MASK) -#define FFA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & FFA_CTRL_SFTRST_MASK) >> FFA_CTRL_SFTRST_SHIFT) - -/* - * EN (RW) - * - * Asserted to enable the module - */ -#define FFA_CTRL_EN_MASK (0x1U) -#define FFA_CTRL_EN_SHIFT (0U) -#define FFA_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_CTRL_EN_SHIFT) & FFA_CTRL_EN_MASK) -#define FFA_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_CTRL_EN_MASK) >> FFA_CTRL_EN_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * FP_NAN (RO) - * - * Ored together by ( FP_ST[IN_NAN] & FP_CTRL[IN_NAN_IE] ) | ( FP_ST[COEF_NAN] & FP_CTRL[COEF_NAN_IE] ) - */ -#define FFA_STATUS_FP_NAN_MASK (0x200U) -#define FFA_STATUS_FP_NAN_SHIFT (9U) -#define FFA_STATUS_FP_NAN_GET(x) (((uint32_t)(x) & FFA_STATUS_FP_NAN_MASK) >> FFA_STATUS_FP_NAN_SHIFT) - -/* - * FP_SAT (RO) - * - * Ored together by ( FP_ST[IN_SAT] & FP_CTRL[IN_SAT_IE] ) | ( FP_ST[COEF_SAT] & FP_CTRL[COEF_SAT_IE] ) - */ -#define FFA_STATUS_FP_SAT_MASK (0x100U) -#define FFA_STATUS_FP_SAT_SHIFT (8U) -#define FFA_STATUS_FP_SAT_GET(x) (((uint32_t)(x) & FFA_STATUS_FP_SAT_MASK) >> FFA_STATUS_FP_SAT_SHIFT) - -/* - * FIR_OV (W1C) - * - * FIR Overflow err - */ -#define FFA_STATUS_FIR_OV_MASK (0x80U) -#define FFA_STATUS_FIR_OV_SHIFT (7U) -#define FFA_STATUS_FIR_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FIR_OV_SHIFT) & FFA_STATUS_FIR_OV_MASK) -#define FFA_STATUS_FIR_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FIR_OV_MASK) >> FFA_STATUS_FIR_OV_SHIFT) - -/* - * FFT_OV (W1C) - * - * FFT Overflow Err - */ -#define FFA_STATUS_FFT_OV_MASK (0x40U) -#define FFA_STATUS_FFT_OV_SHIFT (6U) -#define FFA_STATUS_FFT_OV_SET(x) (((uint32_t)(x) << FFA_STATUS_FFT_OV_SHIFT) & FFA_STATUS_FFT_OV_MASK) -#define FFA_STATUS_FFT_OV_GET(x) (((uint32_t)(x) & FFA_STATUS_FFT_OV_MASK) >> FFA_STATUS_FFT_OV_SHIFT) - -/* - * WR_ERR (W1C) - * - * AXI Data Write Error - */ -#define FFA_STATUS_WR_ERR_MASK (0x20U) -#define FFA_STATUS_WR_ERR_SHIFT (5U) -#define FFA_STATUS_WR_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_WR_ERR_SHIFT) & FFA_STATUS_WR_ERR_MASK) -#define FFA_STATUS_WR_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_WR_ERR_MASK) >> FFA_STATUS_WR_ERR_SHIFT) - -/* - * RD_NXT_ERR (W1C) - * - * AXI Read Bus Error for NXT DATA - */ -#define FFA_STATUS_RD_NXT_ERR_MASK (0x10U) -#define FFA_STATUS_RD_NXT_ERR_SHIFT (4U) -#define FFA_STATUS_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_NXT_ERR_SHIFT) & FFA_STATUS_RD_NXT_ERR_MASK) -#define FFA_STATUS_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_NXT_ERR_MASK) >> FFA_STATUS_RD_NXT_ERR_SHIFT) - -/* - * RD_ERR (W1C) - * - * AXI Data Read Error - */ -#define FFA_STATUS_RD_ERR_MASK (0x8U) -#define FFA_STATUS_RD_ERR_SHIFT (3U) -#define FFA_STATUS_RD_ERR_SET(x) (((uint32_t)(x) << FFA_STATUS_RD_ERR_SHIFT) & FFA_STATUS_RD_ERR_MASK) -#define FFA_STATUS_RD_ERR_GET(x) (((uint32_t)(x) & FFA_STATUS_RD_ERR_MASK) >> FFA_STATUS_RD_ERR_SHIFT) - -/* - * NXT_CMD_RD_DONE (W1C) - * - * Indicate that next command sequence is already read into the module. - */ -#define FFA_STATUS_NXT_CMD_RD_DONE_MASK (0x2U) -#define FFA_STATUS_NXT_CMD_RD_DONE_SHIFT (1U) -#define FFA_STATUS_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) -#define FFA_STATUS_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_NXT_CMD_RD_DONE_MASK) >> FFA_STATUS_NXT_CMD_RD_DONE_SHIFT) - -/* - * OP_CMD_DONE (W1C) - * - * Indicate that operation cmd is done, and data are available in system memory. - */ -#define FFA_STATUS_OP_CMD_DONE_MASK (0x1U) -#define FFA_STATUS_OP_CMD_DONE_SHIFT (0U) -#define FFA_STATUS_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_STATUS_OP_CMD_DONE_SHIFT) & FFA_STATUS_OP_CMD_DONE_MASK) -#define FFA_STATUS_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_STATUS_OP_CMD_DONE_MASK) >> FFA_STATUS_OP_CMD_DONE_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRSV1 (RW) - * - * Reserved - */ -#define FFA_INT_EN_WRSV1_MASK (0xFFFFFF00UL) -#define FFA_INT_EN_WRSV1_SHIFT (8U) -#define FFA_INT_EN_WRSV1_SET(x) (((uint32_t)(x) << FFA_INT_EN_WRSV1_SHIFT) & FFA_INT_EN_WRSV1_MASK) -#define FFA_INT_EN_WRSV1_GET(x) (((uint32_t)(x) & FFA_INT_EN_WRSV1_MASK) >> FFA_INT_EN_WRSV1_SHIFT) - -/* - * FIR_OV (RW) - * - * FIR Overflow err - */ -#define FFA_INT_EN_FIR_OV_MASK (0x80U) -#define FFA_INT_EN_FIR_OV_SHIFT (7U) -#define FFA_INT_EN_FIR_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FIR_OV_SHIFT) & FFA_INT_EN_FIR_OV_MASK) -#define FFA_INT_EN_FIR_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FIR_OV_MASK) >> FFA_INT_EN_FIR_OV_SHIFT) - -/* - * FFT_OV (RW) - * - * FFT Overflow Err - */ -#define FFA_INT_EN_FFT_OV_MASK (0x40U) -#define FFA_INT_EN_FFT_OV_SHIFT (6U) -#define FFA_INT_EN_FFT_OV_SET(x) (((uint32_t)(x) << FFA_INT_EN_FFT_OV_SHIFT) & FFA_INT_EN_FFT_OV_MASK) -#define FFA_INT_EN_FFT_OV_GET(x) (((uint32_t)(x) & FFA_INT_EN_FFT_OV_MASK) >> FFA_INT_EN_FFT_OV_SHIFT) - -/* - * WR_ERR (RW) - * - * Enable Data Write Error interrupt - */ -#define FFA_INT_EN_WR_ERR_MASK (0x20U) -#define FFA_INT_EN_WR_ERR_SHIFT (5U) -#define FFA_INT_EN_WR_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_WR_ERR_SHIFT) & FFA_INT_EN_WR_ERR_MASK) -#define FFA_INT_EN_WR_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_WR_ERR_MASK) >> FFA_INT_EN_WR_ERR_SHIFT) - -/* - * RD_NXT_ERR (RW) - * - * Enable Read Bus Error for NXT DATA interrupt - */ -#define FFA_INT_EN_RD_NXT_ERR_MASK (0x10U) -#define FFA_INT_EN_RD_NXT_ERR_SHIFT (4U) -#define FFA_INT_EN_RD_NXT_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_NXT_ERR_SHIFT) & FFA_INT_EN_RD_NXT_ERR_MASK) -#define FFA_INT_EN_RD_NXT_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_NXT_ERR_MASK) >> FFA_INT_EN_RD_NXT_ERR_SHIFT) - -/* - * RD_ERR (RW) - * - * Enable Data Read Error interrupt - */ -#define FFA_INT_EN_RD_ERR_MASK (0x8U) -#define FFA_INT_EN_RD_ERR_SHIFT (3U) -#define FFA_INT_EN_RD_ERR_SET(x) (((uint32_t)(x) << FFA_INT_EN_RD_ERR_SHIFT) & FFA_INT_EN_RD_ERR_MASK) -#define FFA_INT_EN_RD_ERR_GET(x) (((uint32_t)(x) & FFA_INT_EN_RD_ERR_MASK) >> FFA_INT_EN_RD_ERR_SHIFT) - -/* - * NXT_CMD_RD_DONE (RW) - * - * Indicate that next command sequence is already read into the module. - */ -#define FFA_INT_EN_NXT_CMD_RD_DONE_MASK (0x2U) -#define FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT (1U) -#define FFA_INT_EN_NXT_CMD_RD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) -#define FFA_INT_EN_NXT_CMD_RD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_NXT_CMD_RD_DONE_MASK) >> FFA_INT_EN_NXT_CMD_RD_DONE_SHIFT) - -/* - * OP_CMD_DONE (RW) - * - * Indicate that operation cmd is done, and data are available in system memory. - */ -#define FFA_INT_EN_OP_CMD_DONE_MASK (0x1U) -#define FFA_INT_EN_OP_CMD_DONE_SHIFT (0U) -#define FFA_INT_EN_OP_CMD_DONE_SET(x) (((uint32_t)(x) << FFA_INT_EN_OP_CMD_DONE_SHIFT) & FFA_INT_EN_OP_CMD_DONE_MASK) -#define FFA_INT_EN_OP_CMD_DONE_GET(x) (((uint32_t)(x) & FFA_INT_EN_OP_CMD_DONE_MASK) >> FFA_INT_EN_OP_CMD_DONE_SHIFT) - -/* Bitfield definition for register: FP_CTRL */ -/* - * IN_SAT_IE (RW) - * - * IN_SAT interrupt enable - */ -#define FFA_FP_CTRL_IN_SAT_IE_MASK (0x80000000UL) -#define FFA_FP_CTRL_IN_SAT_IE_SHIFT (31U) -#define FFA_FP_CTRL_IN_SAT_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_IN_SAT_IE_SHIFT) & FFA_FP_CTRL_IN_SAT_IE_MASK) -#define FFA_FP_CTRL_IN_SAT_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_IN_SAT_IE_MASK) >> FFA_FP_CTRL_IN_SAT_IE_SHIFT) - -/* - * COEF_SAT_IE (RW) - * - * COEF_SAT interrupt enable - */ -#define FFA_FP_CTRL_COEF_SAT_IE_MASK (0x20000000UL) -#define FFA_FP_CTRL_COEF_SAT_IE_SHIFT (29U) -#define FFA_FP_CTRL_COEF_SAT_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_COEF_SAT_IE_SHIFT) & FFA_FP_CTRL_COEF_SAT_IE_MASK) -#define FFA_FP_CTRL_COEF_SAT_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_COEF_SAT_IE_MASK) >> FFA_FP_CTRL_COEF_SAT_IE_SHIFT) - -/* - * IN_NAN_IE (RW) - * - * IN_NAN interrupt enable - */ -#define FFA_FP_CTRL_IN_NAN_IE_MASK (0x10000000UL) -#define FFA_FP_CTRL_IN_NAN_IE_SHIFT (28U) -#define FFA_FP_CTRL_IN_NAN_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_IN_NAN_IE_SHIFT) & FFA_FP_CTRL_IN_NAN_IE_MASK) -#define FFA_FP_CTRL_IN_NAN_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_IN_NAN_IE_MASK) >> FFA_FP_CTRL_IN_NAN_IE_SHIFT) - -/* - * COEF_NAN_IE (RW) - * - * COEF_NAN interrupt enable - */ -#define FFA_FP_CTRL_COEF_NAN_IE_MASK (0x8000000UL) -#define FFA_FP_CTRL_COEF_NAN_IE_SHIFT (27U) -#define FFA_FP_CTRL_COEF_NAN_IE_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_COEF_NAN_IE_SHIFT) & FFA_FP_CTRL_COEF_NAN_IE_MASK) -#define FFA_FP_CTRL_COEF_NAN_IE_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_COEF_NAN_IE_MASK) >> FFA_FP_CTRL_COEF_NAN_IE_SHIFT) - -/* - * EXP_ST_SEL (RW) - * - * 2'b00: exp for input data - * 2'b01: exp for output data - * 2'b10: exp for coef data - */ -#define FFA_FP_CTRL_EXP_ST_SEL_MASK (0x6000000UL) -#define FFA_FP_CTRL_EXP_ST_SEL_SHIFT (25U) -#define FFA_FP_CTRL_EXP_ST_SEL_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_EXP_ST_SEL_SHIFT) & FFA_FP_CTRL_EXP_ST_SEL_MASK) -#define FFA_FP_CTRL_EXP_ST_SEL_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_EXP_ST_SEL_MASK) >> FFA_FP_CTRL_EXP_ST_SEL_SHIFT) - -/* - * OPT_BIAS_EXP (RW) - * - * Asserted to use biased exp as exp input and exp output - */ -#define FFA_FP_CTRL_OPT_BIAS_EXP_MASK (0x1000000UL) -#define FFA_FP_CTRL_OPT_BIAS_EXP_SHIFT (24U) -#define FFA_FP_CTRL_OPT_BIAS_EXP_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_OPT_BIAS_EXP_SHIFT) & FFA_FP_CTRL_OPT_BIAS_EXP_MASK) -#define FFA_FP_CTRL_OPT_BIAS_EXP_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_OPT_BIAS_EXP_MASK) >> FFA_FP_CTRL_OPT_BIAS_EXP_SHIFT) - -/* - * COEF_MAX (RW) - * - * The coef max exp for float. When used as float input, this field must be configured. The absolute value of coefficients should be smalller than pow(2, (COEF_MAX+1)). So this suggested value is (ceil(log2(fabs(coef[])))-1). - */ -#define FFA_FP_CTRL_COEF_MAX_MASK (0xFF0000UL) -#define FFA_FP_CTRL_COEF_MAX_SHIFT (16U) -#define FFA_FP_CTRL_COEF_MAX_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_COEF_MAX_SHIFT) & FFA_FP_CTRL_COEF_MAX_MASK) -#define FFA_FP_CTRL_COEF_MAX_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_COEF_MAX_MASK) >> FFA_FP_CTRL_COEF_MAX_SHIFT) - -/* - * OUT_MAX (RW) - * - * The output max exp for float. When used as float output, this field must be configured. The absolute value of output data should be smalller than pow(2, (OUT_MAX+1)). So this suggested value is (ceil(log2(fabs(out[])))-1). - */ -#define FFA_FP_CTRL_OUT_MAX_MASK (0xFF00U) -#define FFA_FP_CTRL_OUT_MAX_SHIFT (8U) -#define FFA_FP_CTRL_OUT_MAX_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_OUT_MAX_SHIFT) & FFA_FP_CTRL_OUT_MAX_MASK) -#define FFA_FP_CTRL_OUT_MAX_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_OUT_MAX_MASK) >> FFA_FP_CTRL_OUT_MAX_SHIFT) - -/* - * IN_MAX (RW) - * - * The input max exp for float. When used as float input, this field must be configured. The absolute value of input data should be smalller than pow(2, (IN_MAX+1)). So this suggested value is (ceil(log2(fabs(in[])))-1). - */ -#define FFA_FP_CTRL_IN_MAX_MASK (0xFFU) -#define FFA_FP_CTRL_IN_MAX_SHIFT (0U) -#define FFA_FP_CTRL_IN_MAX_SET(x) (((uint32_t)(x) << FFA_FP_CTRL_IN_MAX_SHIFT) & FFA_FP_CTRL_IN_MAX_MASK) -#define FFA_FP_CTRL_IN_MAX_GET(x) (((uint32_t)(x) & FFA_FP_CTRL_IN_MAX_MASK) >> FFA_FP_CTRL_IN_MAX_SHIFT) - -/* Bitfield definition for register: FP_ST */ -/* - * IN_SAT (W1C) - * - * the float input is saturated when converted from float to fix due to small FLT_CTRL[IN_MAX]. - */ -#define FFA_FP_ST_IN_SAT_MASK (0x80000000UL) -#define FFA_FP_ST_IN_SAT_SHIFT (31U) -#define FFA_FP_ST_IN_SAT_SET(x) (((uint32_t)(x) << FFA_FP_ST_IN_SAT_SHIFT) & FFA_FP_ST_IN_SAT_MASK) -#define FFA_FP_ST_IN_SAT_GET(x) (((uint32_t)(x) & FFA_FP_ST_IN_SAT_MASK) >> FFA_FP_ST_IN_SAT_SHIFT) - -/* - * COEF_SAT (W1C) - * - * the float coef is saturated when converted from float to fix due to small FLT_CTRL[COEF_MAX]. - */ -#define FFA_FP_ST_COEF_SAT_MASK (0x20000000UL) -#define FFA_FP_ST_COEF_SAT_SHIFT (29U) -#define FFA_FP_ST_COEF_SAT_SET(x) (((uint32_t)(x) << FFA_FP_ST_COEF_SAT_SHIFT) & FFA_FP_ST_COEF_SAT_MASK) -#define FFA_FP_ST_COEF_SAT_GET(x) (((uint32_t)(x) & FFA_FP_ST_COEF_SAT_MASK) >> FFA_FP_ST_COEF_SAT_SHIFT) - -/* - * IN_NAN (W1C) - * - * IN_NAN found - */ -#define FFA_FP_ST_IN_NAN_MASK (0x10000000UL) -#define FFA_FP_ST_IN_NAN_SHIFT (28U) -#define FFA_FP_ST_IN_NAN_SET(x) (((uint32_t)(x) << FFA_FP_ST_IN_NAN_SHIFT) & FFA_FP_ST_IN_NAN_MASK) -#define FFA_FP_ST_IN_NAN_GET(x) (((uint32_t)(x) & FFA_FP_ST_IN_NAN_MASK) >> FFA_FP_ST_IN_NAN_SHIFT) - -/* - * COEF_NAN (W1C) - * - * COEF_NAN found - */ -#define FFA_FP_ST_COEF_NAN_MASK (0x8000000UL) -#define FFA_FP_ST_COEF_NAN_SHIFT (27U) -#define FFA_FP_ST_COEF_NAN_SET(x) (((uint32_t)(x) << FFA_FP_ST_COEF_NAN_SHIFT) & FFA_FP_ST_COEF_NAN_MASK) -#define FFA_FP_ST_COEF_NAN_GET(x) (((uint32_t)(x) & FFA_FP_ST_COEF_NAN_MASK) >> FFA_FP_ST_COEF_NAN_SHIFT) - -/* - * EXP_MAX (RO) - * - * The max exp for float - */ -#define FFA_FP_ST_EXP_MAX_MASK (0xFF00U) -#define FFA_FP_ST_EXP_MAX_SHIFT (8U) -#define FFA_FP_ST_EXP_MAX_GET(x) (((uint32_t)(x) & FFA_FP_ST_EXP_MAX_MASK) >> FFA_FP_ST_EXP_MAX_SHIFT) - -/* - * EXP_MIN (RO) - * - * The min exp for float - */ -#define FFA_FP_ST_EXP_MIN_MASK (0xFFU) -#define FFA_FP_ST_EXP_MIN_SHIFT (0U) -#define FFA_FP_ST_EXP_MIN_GET(x) (((uint32_t)(x) & FFA_FP_ST_EXP_MIN_MASK) >> FFA_FP_ST_EXP_MIN_SHIFT) - -/* Bitfield definition for register: OP_CTRL */ -/* - * NXT_ADDR (RW) - * - * The address for the next command. - * It will be processed after CUR_CMD is executed and done.. - */ -#define FFA_OP_CTRL_NXT_ADDR_MASK (0xFFFFFFFCUL) -#define FFA_OP_CTRL_NXT_ADDR_SHIFT (2U) -#define FFA_OP_CTRL_NXT_ADDR_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_ADDR_SHIFT) & FFA_OP_CTRL_NXT_ADDR_MASK) -#define FFA_OP_CTRL_NXT_ADDR_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_ADDR_MASK) >> FFA_OP_CTRL_NXT_ADDR_SHIFT) - -/* - * NXT_EN (RW) - * - * Whether NXT_CMD is enabled. - * Asserted to enable the NXT_CMD when CUR_CMD is done, or CUR_CMD is not enabled.. - */ -#define FFA_OP_CTRL_NXT_EN_MASK (0x2U) -#define FFA_OP_CTRL_NXT_EN_SHIFT (1U) -#define FFA_OP_CTRL_NXT_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_NXT_EN_SHIFT) & FFA_OP_CTRL_NXT_EN_MASK) -#define FFA_OP_CTRL_NXT_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_NXT_EN_MASK) >> FFA_OP_CTRL_NXT_EN_SHIFT) - -/* - * EN (RW) - * - * Whether CUR_CMD is enabled. - * Asserted to enable the CUR_CMD - */ -#define FFA_OP_CTRL_EN_MASK (0x1U) -#define FFA_OP_CTRL_EN_SHIFT (0U) -#define FFA_OP_CTRL_EN_SET(x) (((uint32_t)(x) << FFA_OP_CTRL_EN_SHIFT) & FFA_OP_CTRL_EN_MASK) -#define FFA_OP_CTRL_EN_GET(x) (((uint32_t)(x) & FFA_OP_CTRL_EN_MASK) >> FFA_OP_CTRL_EN_SHIFT) - -/* Bitfield definition for register: OP_CMD */ -/* - * CONJ_C (RW) - * - * asserted to have conjuate value for coefs in computation - */ -#define FFA_OP_CMD_CONJ_C_MASK (0x1000000UL) -#define FFA_OP_CMD_CONJ_C_SHIFT (24U) -#define FFA_OP_CMD_CONJ_C_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CONJ_C_SHIFT) & FFA_OP_CMD_CONJ_C_MASK) -#define FFA_OP_CMD_CONJ_C_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CONJ_C_MASK) >> FFA_OP_CMD_CONJ_C_SHIFT) - -/* - * CMD (RW) - * - * The Command Used: - * 0: FIR - * 2: FFT - * Others: Reserved - */ -#define FFA_OP_CMD_CMD_MASK (0xFC0000UL) -#define FFA_OP_CMD_CMD_SHIFT (18U) -#define FFA_OP_CMD_CMD_SET(x) (((uint32_t)(x) << FFA_OP_CMD_CMD_SHIFT) & FFA_OP_CMD_CMD_MASK) -#define FFA_OP_CMD_CMD_GET(x) (((uint32_t)(x) & FFA_OP_CMD_CMD_MASK) >> FFA_OP_CMD_CMD_SHIFT) - -/* - * OUTD_TYPE (RW) - * - * Output data type: - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_OUTD_TYPE_MASK (0x38000UL) -#define FFA_OP_CMD_OUTD_TYPE_SHIFT (15U) -#define FFA_OP_CMD_OUTD_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_OUTD_TYPE_SHIFT) & FFA_OP_CMD_OUTD_TYPE_MASK) -#define FFA_OP_CMD_OUTD_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_OUTD_TYPE_MASK) >> FFA_OP_CMD_OUTD_TYPE_SHIFT) - -/* - * COEF_TYPE (RW) - * - * Coef data type (used for FIR): - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_COEF_TYPE_MASK (0x7000U) -#define FFA_OP_CMD_COEF_TYPE_SHIFT (12U) -#define FFA_OP_CMD_COEF_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_COEF_TYPE_SHIFT) & FFA_OP_CMD_COEF_TYPE_MASK) -#define FFA_OP_CMD_COEF_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_COEF_TYPE_MASK) >> FFA_OP_CMD_COEF_TYPE_SHIFT) - -/* - * IND_TYPE (RW) - * - * Input data type: - * 0:Real Q31, 1:Real Q15, 2:Complex Q31, 3:Complex Q15 - * 4:complex sp float 5: real sp float - */ -#define FFA_OP_CMD_IND_TYPE_MASK (0xE00U) -#define FFA_OP_CMD_IND_TYPE_SHIFT (9U) -#define FFA_OP_CMD_IND_TYPE_SET(x) (((uint32_t)(x) << FFA_OP_CMD_IND_TYPE_SHIFT) & FFA_OP_CMD_IND_TYPE_MASK) -#define FFA_OP_CMD_IND_TYPE_GET(x) (((uint32_t)(x) & FFA_OP_CMD_IND_TYPE_MASK) >> FFA_OP_CMD_IND_TYPE_SHIFT) - -/* - * NXT_CMD_LEN (RW) - * - * The length of nxt commands in 32-bit words - */ -#define FFA_OP_CMD_NXT_CMD_LEN_MASK (0xFFU) -#define FFA_OP_CMD_NXT_CMD_LEN_SHIFT (0U) -#define FFA_OP_CMD_NXT_CMD_LEN_SET(x) (((uint32_t)(x) << FFA_OP_CMD_NXT_CMD_LEN_SHIFT) & FFA_OP_CMD_NXT_CMD_LEN_MASK) -#define FFA_OP_CMD_NXT_CMD_LEN_GET(x) (((uint32_t)(x) & FFA_OP_CMD_NXT_CMD_LEN_MASK) >> FFA_OP_CMD_NXT_CMD_LEN_SHIFT) - -/* Bitfield definition for register: OP_REG0 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG0_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG0_CT_SHIFT (0U) -#define FFA_OP_REG0_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG0_CT_SHIFT) & FFA_OP_REG0_CT_MASK) -#define FFA_OP_REG0_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG0_CT_MASK) >> FFA_OP_REG0_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_MISC */ -/* - * FIR_COEF_TAPS (RW) - * - * Length of FIR coefs （max 256） - */ -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK (0x3FFFU) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT (0U) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) -#define FFA_OP_FIR_MISC_FIR_COEF_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC_FIR_COEF_TAPS_MASK) >> FFA_OP_FIR_MISC_FIR_COEF_TAPS_SHIFT) - -/* Bitfield definition for register: OP_FFT_MISC */ -/* - * FFT_LEN (RW) - * - * FFT length - * 0:8, - * ..., - * n:2^(3+n) - */ -#define FFA_OP_FFT_MISC_FFT_LEN_MASK (0x780U) -#define FFA_OP_FFT_MISC_FFT_LEN_SHIFT (7U) -#define FFA_OP_FFT_MISC_FFT_LEN_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_FFT_LEN_SHIFT) & FFA_OP_FFT_MISC_FFT_LEN_MASK) -#define FFA_OP_FFT_MISC_FFT_LEN_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_FFT_LEN_MASK) >> FFA_OP_FFT_MISC_FFT_LEN_SHIFT) - -/* - * IFFT (RW) - * - * Asserted to indicate IFFT - */ -#define FFA_OP_FFT_MISC_IFFT_MASK (0x40U) -#define FFA_OP_FFT_MISC_IFFT_SHIFT (6U) -#define FFA_OP_FFT_MISC_IFFT_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IFFT_SHIFT) & FFA_OP_FFT_MISC_IFFT_MASK) -#define FFA_OP_FFT_MISC_IFFT_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IFFT_MASK) >> FFA_OP_FFT_MISC_IFFT_SHIFT) - -/* - * TMP_BLK (RW) - * - * Memory block for indata. Should be assigned as 1 - */ -#define FFA_OP_FFT_MISC_TMP_BLK_MASK (0xCU) -#define FFA_OP_FFT_MISC_TMP_BLK_SHIFT (2U) -#define FFA_OP_FFT_MISC_TMP_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_TMP_BLK_SHIFT) & FFA_OP_FFT_MISC_TMP_BLK_MASK) -#define FFA_OP_FFT_MISC_TMP_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_TMP_BLK_MASK) >> FFA_OP_FFT_MISC_TMP_BLK_SHIFT) - -/* - * IND_BLK (RW) - * - * Memory block for indata. Should be assigned as 0 - */ -#define FFA_OP_FFT_MISC_IND_BLK_MASK (0x3U) -#define FFA_OP_FFT_MISC_IND_BLK_SHIFT (0U) -#define FFA_OP_FFT_MISC_IND_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FFT_MISC_IND_BLK_SHIFT) & FFA_OP_FFT_MISC_IND_BLK_MASK) -#define FFA_OP_FFT_MISC_IND_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FFT_MISC_IND_BLK_MASK) >> FFA_OP_FFT_MISC_IND_BLK_SHIFT) - -/* Bitfield definition for register: OP_REG1 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG1_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG1_CT_SHIFT (0U) -#define FFA_OP_REG1_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG1_CT_SHIFT) & FFA_OP_REG1_CT_MASK) -#define FFA_OP_REG1_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG1_CT_MASK) >> FFA_OP_REG1_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_MISC1 */ -/* - * OUTD_MEM_BLK (RW) - * - * Should be assigned as 0 - */ -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK (0x300000UL) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT (20U) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_OUTD_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_OUTD_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_OUTD_MEM_BLK_SHIFT) - -/* - * COEF_MEM_BLK (RW) - * - * Should be assigned as 1 - */ -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK (0xC0000UL) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT (18U) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_COEF_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_COEF_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_COEF_MEM_BLK_SHIFT) - -/* - * IND_MEM_BLK (RW) - * - * Should be assigned as 2 - */ -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK (0x30000UL) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT (16U) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) -#define FFA_OP_FIR_MISC1_IND_MEM_BLK_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_IND_MEM_BLK_MASK) >> FFA_OP_FIR_MISC1_IND_MEM_BLK_SHIFT) - -/* - * FIR_DATA_TAPS (RW) - * - * The input data data length - */ -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK (0xFFFFU) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT (0U) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SET(x) (((uint32_t)(x) << FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) -#define FFA_OP_FIR_MISC1_FIR_DATA_TAPS_GET(x) (((uint32_t)(x) & FFA_OP_FIR_MISC1_FIR_DATA_TAPS_MASK) >> FFA_OP_FIR_MISC1_FIR_DATA_TAPS_SHIFT) - -/* Bitfield definition for register: OP_REG2 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG2_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG2_CT_SHIFT (0U) -#define FFA_OP_REG2_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG2_CT_SHIFT) & FFA_OP_REG2_CT_MASK) -#define FFA_OP_REG2_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG2_CT_MASK) >> FFA_OP_REG2_CT_SHIFT) - -/* Bitfield definition for register: OP_FFT_INRBUF */ -/* - * LOC (RW) - * - * The input (real) data buffer pointer - */ -#define FFA_OP_FFT_INRBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FFT_INRBUF_LOC_SHIFT (0U) -#define FFA_OP_FFT_INRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_INRBUF_LOC_SHIFT) & FFA_OP_FFT_INRBUF_LOC_MASK) -#define FFA_OP_FFT_INRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_INRBUF_LOC_MASK) >> FFA_OP_FFT_INRBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG3 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG3_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG3_CT_SHIFT (0U) -#define FFA_OP_REG3_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG3_CT_SHIFT) & FFA_OP_REG3_CT_MASK) -#define FFA_OP_REG3_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG3_CT_MASK) >> FFA_OP_REG3_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_INBUF */ -/* - * LOC (RW) - * - * The input data buffer pointer - */ -#define FFA_OP_FIR_INBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_INBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_INBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_INBUF_LOC_SHIFT) & FFA_OP_FIR_INBUF_LOC_MASK) -#define FFA_OP_FIR_INBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_INBUF_LOC_MASK) >> FFA_OP_FIR_INBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG4 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG4_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG4_CT_SHIFT (0U) -#define FFA_OP_REG4_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG4_CT_SHIFT) & FFA_OP_REG4_CT_MASK) -#define FFA_OP_REG4_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG4_CT_MASK) >> FFA_OP_REG4_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_COEFBUF */ -/* - * LOC (RW) - * - * The coef buf pointer - */ -#define FFA_OP_FIR_COEFBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_COEFBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_COEFBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_COEFBUF_LOC_SHIFT) & FFA_OP_FIR_COEFBUF_LOC_MASK) -#define FFA_OP_FIR_COEFBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_COEFBUF_LOC_MASK) >> FFA_OP_FIR_COEFBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_FFT_OUTRBUF */ -/* - * LOC (RW) - * - * The output (real) data buffer pointer - */ -#define FFA_OP_FFT_OUTRBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FFT_OUTRBUF_LOC_SHIFT (0U) -#define FFA_OP_FFT_OUTRBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FFT_OUTRBUF_LOC_SHIFT) & FFA_OP_FFT_OUTRBUF_LOC_MASK) -#define FFA_OP_FFT_OUTRBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FFT_OUTRBUF_LOC_MASK) >> FFA_OP_FFT_OUTRBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG5 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG5_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG5_CT_SHIFT (0U) -#define FFA_OP_REG5_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG5_CT_SHIFT) & FFA_OP_REG5_CT_MASK) -#define FFA_OP_REG5_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG5_CT_MASK) >> FFA_OP_REG5_CT_SHIFT) - -/* Bitfield definition for register: OP_FIR_OUTBUF */ -/* - * LOC (RW) - * - * The output data buffer pointer. The length of the output buffer should be （FIR_DATA_TAPS - FIR_COEF_TAPS + 1） - */ -#define FFA_OP_FIR_OUTBUF_LOC_MASK (0xFFFFFFFFUL) -#define FFA_OP_FIR_OUTBUF_LOC_SHIFT (0U) -#define FFA_OP_FIR_OUTBUF_LOC_SET(x) (((uint32_t)(x) << FFA_OP_FIR_OUTBUF_LOC_SHIFT) & FFA_OP_FIR_OUTBUF_LOC_MASK) -#define FFA_OP_FIR_OUTBUF_LOC_GET(x) (((uint32_t)(x) & FFA_OP_FIR_OUTBUF_LOC_MASK) >> FFA_OP_FIR_OUTBUF_LOC_SHIFT) - -/* Bitfield definition for register: OP_REG6 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG6_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG6_CT_SHIFT (0U) -#define FFA_OP_REG6_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG6_CT_SHIFT) & FFA_OP_REG6_CT_MASK) -#define FFA_OP_REG6_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG6_CT_MASK) >> FFA_OP_REG6_CT_SHIFT) - -/* Bitfield definition for register: OP_REG7 */ -/* - * CT (RW) - * - * Contents - */ -#define FFA_OP_REG7_CT_MASK (0xFFFFFFFFUL) -#define FFA_OP_REG7_CT_SHIFT (0U) -#define FFA_OP_REG7_CT_SET(x) (((uint32_t)(x) << FFA_OP_REG7_CT_SHIFT) & FFA_OP_REG7_CT_MASK) -#define FFA_OP_REG7_CT_GET(x) (((uint32_t)(x) & FFA_OP_REG7_CT_MASK) >> FFA_OP_REG7_CT_SHIFT) - - - - -#endif /* HPM_FFA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gpio_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gpio_regs.h deleted file mode 100644 index 5433af5e5cc..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gpio_regs.h +++ /dev/null @@ -1,579 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIO_H -#define HPM_GPIO_H - -typedef struct { - struct { - __R uint32_t VALUE; /* 0x0: GPIO input value */ - __R uint8_t RESERVED0[12]; /* 0x4 - 0xF: Reserved */ - } DI[16]; - struct { - __RW uint32_t VALUE; /* 0x100: GPIO output value */ - __RW uint32_t SET; /* 0x104: GPIO output set */ - __RW uint32_t CLEAR; /* 0x108: GPIO output clear */ - __RW uint32_t TOGGLE; /* 0x10C: GPIO output toggle */ - } DO[16]; - struct { - __RW uint32_t VALUE; /* 0x200: GPIO direction value */ - __RW uint32_t SET; /* 0x204: GPIO direction set */ - __RW uint32_t CLEAR; /* 0x208: GPIO direction clear */ - __RW uint32_t TOGGLE; /* 0x20C: GPIO direction toggle */ - } OE[16]; - struct { - __W uint32_t VALUE; /* 0x300: GPIO interrupt flag value */ - __R uint8_t RESERVED0[12]; /* 0x304 - 0x30F: Reserved */ - } IF[16]; - struct { - __RW uint32_t VALUE; /* 0x400: GPIO interrupt enable value */ - __RW uint32_t SET; /* 0x404: GPIO interrupt enable set */ - __RW uint32_t CLEAR; /* 0x408: GPIO interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x40C: GPIO interrupt enable toggle */ - } IE[16]; - struct { - __RW uint32_t VALUE; /* 0x500: GPIO interrupt polarity value */ - __RW uint32_t SET; /* 0x504: GPIO interrupt polarity set */ - __RW uint32_t CLEAR; /* 0x508: GPIO interrupt polarity clear */ - __RW uint32_t TOGGLE; /* 0x50C: GPIO interrupt polarity toggle */ - } PL[16]; - struct { - __RW uint32_t VALUE; /* 0x600: GPIO interrupt type value */ - __RW uint32_t SET; /* 0x604: GPIO interrupt type set */ - __RW uint32_t CLEAR; /* 0x608: GPIO interrupt type clear */ - __RW uint32_t TOGGLE; /* 0x60C: GPIO interrupt type toggle */ - } TP[16]; - struct { - __RW uint32_t VALUE; /* 0x700: GPIO interrupt asynchronous value */ - __RW uint32_t SET; /* 0x704: GPIO interrupt asynchronous set */ - __RW uint32_t CLEAR; /* 0x708: GPIO interrupt asynchronous clear */ - __RW uint32_t TOGGLE; /* 0x70C: GPIO interrupt asynchronous toggle */ - } AS[16]; - struct { - __RW uint32_t VALUE; /* 0x800: GPIO dual edge interrupt enable value */ - __RW uint32_t SET; /* 0x804: GPIO dual edge interrupt enable set */ - __RW uint32_t CLEAR; /* 0x808: GPIO dual edge interrupt enable clear */ - __RW uint32_t TOGGLE; /* 0x80C: GPIO dual edge interrupt enable toggle */ - } PD[16]; -} GPIO_Type; - - -/* Bitfield definition for register of struct array DI: VALUE */ -/* - * INPUT (RO) - * - * GPIO input bus value, each bit represents a bus bit - * 0: low level presents on chip pin - * 1: high level presents on chip pin - */ -#define GPIO_DI_VALUE_INPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DI_VALUE_INPUT_SHIFT (0U) -#define GPIO_DI_VALUE_INPUT_GET(x) (((uint32_t)(x) & GPIO_DI_VALUE_INPUT_MASK) >> GPIO_DI_VALUE_INPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: VALUE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_VALUE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_VALUE_OUTPUT_SHIFT (0U) -#define GPIO_DO_VALUE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_VALUE_OUTPUT_SHIFT) & GPIO_DO_VALUE_OUTPUT_MASK) -#define GPIO_DO_VALUE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_VALUE_OUTPUT_MASK) >> GPIO_DO_VALUE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: SET */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_SET_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_SET_OUTPUT_SHIFT (0U) -#define GPIO_DO_SET_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_SET_OUTPUT_SHIFT) & GPIO_DO_SET_OUTPUT_MASK) -#define GPIO_DO_SET_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_SET_OUTPUT_MASK) >> GPIO_DO_SET_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: CLEAR */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_CLEAR_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_CLEAR_OUTPUT_SHIFT (0U) -#define GPIO_DO_CLEAR_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_CLEAR_OUTPUT_SHIFT) & GPIO_DO_CLEAR_OUTPUT_MASK) -#define GPIO_DO_CLEAR_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_CLEAR_OUTPUT_MASK) >> GPIO_DO_CLEAR_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array DO: TOGGLE */ -/* - * OUTPUT (RW) - * - * GPIO output register value, each bit represents a bus bit - * 0: chip pin output low level when direction is output - * 1: chip pin output high level when direction is output - */ -#define GPIO_DO_TOGGLE_OUTPUT_MASK (0xFFFFFFFFUL) -#define GPIO_DO_TOGGLE_OUTPUT_SHIFT (0U) -#define GPIO_DO_TOGGLE_OUTPUT_SET(x) (((uint32_t)(x) << GPIO_DO_TOGGLE_OUTPUT_SHIFT) & GPIO_DO_TOGGLE_OUTPUT_MASK) -#define GPIO_DO_TOGGLE_OUTPUT_GET(x) (((uint32_t)(x) & GPIO_DO_TOGGLE_OUTPUT_MASK) >> GPIO_DO_TOGGLE_OUTPUT_SHIFT) - -/* Bitfield definition for register of struct array OE: VALUE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_VALUE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_VALUE_DIRECTION_SHIFT (0U) -#define GPIO_OE_VALUE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_VALUE_DIRECTION_SHIFT) & GPIO_OE_VALUE_DIRECTION_MASK) -#define GPIO_OE_VALUE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_VALUE_DIRECTION_MASK) >> GPIO_OE_VALUE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: SET */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_SET_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_SET_DIRECTION_SHIFT (0U) -#define GPIO_OE_SET_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_SET_DIRECTION_SHIFT) & GPIO_OE_SET_DIRECTION_MASK) -#define GPIO_OE_SET_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_SET_DIRECTION_MASK) >> GPIO_OE_SET_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: CLEAR */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_CLEAR_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_CLEAR_DIRECTION_SHIFT (0U) -#define GPIO_OE_CLEAR_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_CLEAR_DIRECTION_SHIFT) & GPIO_OE_CLEAR_DIRECTION_MASK) -#define GPIO_OE_CLEAR_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_CLEAR_DIRECTION_MASK) >> GPIO_OE_CLEAR_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array OE: TOGGLE */ -/* - * DIRECTION (RW) - * - * GPIO direction, each bit represents a bus bit - * 0: input - * 1: output - */ -#define GPIO_OE_TOGGLE_DIRECTION_MASK (0xFFFFFFFFUL) -#define GPIO_OE_TOGGLE_DIRECTION_SHIFT (0U) -#define GPIO_OE_TOGGLE_DIRECTION_SET(x) (((uint32_t)(x) << GPIO_OE_TOGGLE_DIRECTION_SHIFT) & GPIO_OE_TOGGLE_DIRECTION_MASK) -#define GPIO_OE_TOGGLE_DIRECTION_GET(x) (((uint32_t)(x) & GPIO_OE_TOGGLE_DIRECTION_MASK) >> GPIO_OE_TOGGLE_DIRECTION_SHIFT) - -/* Bitfield definition for register of struct array IF: VALUE */ -/* - * IRQ_FLAG (W1C) - * - * GPIO interrupt flag, write 1 to clear this flag - * 0: no irq - * 1: irq pending - */ -#define GPIO_IF_VALUE_IRQ_FLAG_MASK (0xFFFFFFFFUL) -#define GPIO_IF_VALUE_IRQ_FLAG_SHIFT (0U) -#define GPIO_IF_VALUE_IRQ_FLAG_SET(x) (((uint32_t)(x) << GPIO_IF_VALUE_IRQ_FLAG_SHIFT) & GPIO_IF_VALUE_IRQ_FLAG_MASK) -#define GPIO_IF_VALUE_IRQ_FLAG_GET(x) (((uint32_t)(x) & GPIO_IF_VALUE_IRQ_FLAG_MASK) >> GPIO_IF_VALUE_IRQ_FLAG_SHIFT) - -/* Bitfield definition for register of struct array IE: VALUE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_VALUE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_VALUE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_VALUE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_VALUE_IRQ_EN_SHIFT) & GPIO_IE_VALUE_IRQ_EN_MASK) -#define GPIO_IE_VALUE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_VALUE_IRQ_EN_MASK) >> GPIO_IE_VALUE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: SET */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_SET_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_SET_IRQ_EN_SHIFT (0U) -#define GPIO_IE_SET_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_SET_IRQ_EN_SHIFT) & GPIO_IE_SET_IRQ_EN_MASK) -#define GPIO_IE_SET_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_SET_IRQ_EN_MASK) >> GPIO_IE_SET_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: CLEAR */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_CLEAR_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_CLEAR_IRQ_EN_SHIFT (0U) -#define GPIO_IE_CLEAR_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_CLEAR_IRQ_EN_SHIFT) & GPIO_IE_CLEAR_IRQ_EN_MASK) -#define GPIO_IE_CLEAR_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_CLEAR_IRQ_EN_MASK) >> GPIO_IE_CLEAR_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array IE: TOGGLE */ -/* - * IRQ_EN (RW) - * - * GPIO interrupt enable, each bit represents a bus bit - * 0: irq is disabled - * 1: irq is enable - */ -#define GPIO_IE_TOGGLE_IRQ_EN_MASK (0xFFFFFFFFUL) -#define GPIO_IE_TOGGLE_IRQ_EN_SHIFT (0U) -#define GPIO_IE_TOGGLE_IRQ_EN_SET(x) (((uint32_t)(x) << GPIO_IE_TOGGLE_IRQ_EN_SHIFT) & GPIO_IE_TOGGLE_IRQ_EN_MASK) -#define GPIO_IE_TOGGLE_IRQ_EN_GET(x) (((uint32_t)(x) & GPIO_IE_TOGGLE_IRQ_EN_MASK) >> GPIO_IE_TOGGLE_IRQ_EN_SHIFT) - -/* Bitfield definition for register of struct array PL: VALUE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_VALUE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_VALUE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_VALUE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_VALUE_IRQ_POL_SHIFT) & GPIO_PL_VALUE_IRQ_POL_MASK) -#define GPIO_PL_VALUE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_VALUE_IRQ_POL_MASK) >> GPIO_PL_VALUE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: SET */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_SET_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_SET_IRQ_POL_SHIFT (0U) -#define GPIO_PL_SET_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_SET_IRQ_POL_SHIFT) & GPIO_PL_SET_IRQ_POL_MASK) -#define GPIO_PL_SET_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_SET_IRQ_POL_MASK) >> GPIO_PL_SET_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: CLEAR */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_CLEAR_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_CLEAR_IRQ_POL_SHIFT (0U) -#define GPIO_PL_CLEAR_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_CLEAR_IRQ_POL_SHIFT) & GPIO_PL_CLEAR_IRQ_POL_MASK) -#define GPIO_PL_CLEAR_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_CLEAR_IRQ_POL_MASK) >> GPIO_PL_CLEAR_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array PL: TOGGLE */ -/* - * IRQ_POL (RW) - * - * GPIO interrupt polarity, each bit represents a bus bit - * 0: irq is high level or rising edge - * 1: irq is low level or falling edge - */ -#define GPIO_PL_TOGGLE_IRQ_POL_MASK (0xFFFFFFFFUL) -#define GPIO_PL_TOGGLE_IRQ_POL_SHIFT (0U) -#define GPIO_PL_TOGGLE_IRQ_POL_SET(x) (((uint32_t)(x) << GPIO_PL_TOGGLE_IRQ_POL_SHIFT) & GPIO_PL_TOGGLE_IRQ_POL_MASK) -#define GPIO_PL_TOGGLE_IRQ_POL_GET(x) (((uint32_t)(x) & GPIO_PL_TOGGLE_IRQ_POL_MASK) >> GPIO_PL_TOGGLE_IRQ_POL_SHIFT) - -/* Bitfield definition for register of struct array TP: VALUE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_VALUE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_VALUE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_VALUE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_VALUE_IRQ_TYPE_SHIFT) & GPIO_TP_VALUE_IRQ_TYPE_MASK) -#define GPIO_TP_VALUE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_VALUE_IRQ_TYPE_MASK) >> GPIO_TP_VALUE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: SET */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_SET_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_SET_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_SET_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_SET_IRQ_TYPE_SHIFT) & GPIO_TP_SET_IRQ_TYPE_MASK) -#define GPIO_TP_SET_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_SET_IRQ_TYPE_MASK) >> GPIO_TP_SET_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: CLEAR */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_CLEAR_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_CLEAR_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_CLEAR_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) -#define GPIO_TP_CLEAR_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_CLEAR_IRQ_TYPE_MASK) >> GPIO_TP_CLEAR_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array TP: TOGGLE */ -/* - * IRQ_TYPE (RW) - * - * GPIO interrupt type, each bit represents a bus bit - * 0: irq is triggered by level - * 1: irq is triggered by edge - */ -#define GPIO_TP_TOGGLE_IRQ_TYPE_MASK (0xFFFFFFFFUL) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT (0U) -#define GPIO_TP_TOGGLE_IRQ_TYPE_SET(x) (((uint32_t)(x) << GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) -#define GPIO_TP_TOGGLE_IRQ_TYPE_GET(x) (((uint32_t)(x) & GPIO_TP_TOGGLE_IRQ_TYPE_MASK) >> GPIO_TP_TOGGLE_IRQ_TYPE_SHIFT) - -/* Bitfield definition for register of struct array AS: VALUE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_VALUE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_VALUE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_VALUE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) -#define GPIO_AS_VALUE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_VALUE_IRQ_ASYNC_MASK) >> GPIO_AS_VALUE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: SET */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_SET_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_SET_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_SET_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_SET_IRQ_ASYNC_SHIFT) & GPIO_AS_SET_IRQ_ASYNC_MASK) -#define GPIO_AS_SET_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_SET_IRQ_ASYNC_MASK) >> GPIO_AS_SET_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: CLEAR */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_CLEAR_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_CLEAR_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) -#define GPIO_AS_CLEAR_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_CLEAR_IRQ_ASYNC_MASK) >> GPIO_AS_CLEAR_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array AS: TOGGLE */ -/* - * IRQ_ASYNC (RW) - * - * GPIO interrupt asynchronous, each bit represents a bus bit - * 0: irq is triggered base on system clock - * 1: irq is triggered combinational - * Note: combinational interrupt is sensitive to environment noise - */ -#define GPIO_AS_TOGGLE_IRQ_ASYNC_MASK (0xFFFFFFFFUL) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT (0U) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_SET(x) (((uint32_t)(x) << GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) -#define GPIO_AS_TOGGLE_IRQ_ASYNC_GET(x) (((uint32_t)(x) & GPIO_AS_TOGGLE_IRQ_ASYNC_MASK) >> GPIO_AS_TOGGLE_IRQ_ASYNC_SHIFT) - -/* Bitfield definition for register of struct array PD: VALUE */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable - * 0: single edge interrupt - * 1: dual edge interrupt enable - */ -#define GPIO_PD_VALUE_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_VALUE_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_VALUE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_VALUE_IRQ_DUAL_SHIFT) & GPIO_PD_VALUE_IRQ_DUAL_MASK) -#define GPIO_PD_VALUE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_VALUE_IRQ_DUAL_MASK) >> GPIO_PD_VALUE_IRQ_DUAL_SHIFT) - -/* Bitfield definition for register of struct array PD: SET */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable set - * 0: keep original edge interrupt type - * 1: dual edge interrupt enable - */ -#define GPIO_PD_SET_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_SET_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_SET_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_SET_IRQ_DUAL_SHIFT) & GPIO_PD_SET_IRQ_DUAL_MASK) -#define GPIO_PD_SET_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_SET_IRQ_DUAL_MASK) >> GPIO_PD_SET_IRQ_DUAL_SHIFT) - -/* Bitfield definition for register of struct array PD: CLEAR */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable clear - * 0: keep original edge interrupt type - * 1: single edge interrupt enable - */ -#define GPIO_PD_CLEAR_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_CLEAR_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_CLEAR_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) -#define GPIO_PD_CLEAR_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_CLEAR_IRQ_DUAL_MASK) >> GPIO_PD_CLEAR_IRQ_DUAL_SHIFT) - -/* Bitfield definition for register of struct array PD: TOGGLE */ -/* - * IRQ_DUAL (RW) - * - * GPIO dual edge interrupt enable toggle - * 0: keep original edge interrupt type - * 1: change original edge interrupt type to another one. - */ -#define GPIO_PD_TOGGLE_IRQ_DUAL_MASK (0x1U) -#define GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT (0U) -#define GPIO_PD_TOGGLE_IRQ_DUAL_SET(x) (((uint32_t)(x) << GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) -#define GPIO_PD_TOGGLE_IRQ_DUAL_GET(x) (((uint32_t)(x) & GPIO_PD_TOGGLE_IRQ_DUAL_MASK) >> GPIO_PD_TOGGLE_IRQ_DUAL_SHIFT) - - - -/* DI register group index macro definition */ -#define GPIO_DI_GPIOA (0UL) -#define GPIO_DI_GPIOB (1UL) -#define GPIO_DI_GPIOC (2UL) -#define GPIO_DI_GPIOD (3UL) -#define GPIO_DI_GPIOE (4UL) -#define GPIO_DI_GPIOF (5UL) -#define GPIO_DI_GPIOV (11UL) -#define GPIO_DI_GPIOW (12UL) -#define GPIO_DI_GPIOX (13UL) -#define GPIO_DI_GPIOY (14UL) -#define GPIO_DI_GPIOZ (15UL) - -/* DO register group index macro definition */ -#define GPIO_DO_GPIOA (0UL) -#define GPIO_DO_GPIOB (1UL) -#define GPIO_DO_GPIOC (2UL) -#define GPIO_DO_GPIOD (3UL) -#define GPIO_DO_GPIOE (4UL) -#define GPIO_DO_GPIOF (5UL) -#define GPIO_DO_GPIOV (11UL) -#define GPIO_DO_GPIOW (12UL) -#define GPIO_DO_GPIOX (13UL) -#define GPIO_DO_GPIOY (14UL) -#define GPIO_DO_GPIOZ (15UL) - -/* OE register group index macro definition */ -#define GPIO_OE_GPIOA (0UL) -#define GPIO_OE_GPIOB (1UL) -#define GPIO_OE_GPIOC (2UL) -#define GPIO_OE_GPIOD (3UL) -#define GPIO_OE_GPIOE (4UL) -#define GPIO_OE_GPIOF (5UL) -#define GPIO_OE_GPIOV (11UL) -#define GPIO_OE_GPIOW (12UL) -#define GPIO_OE_GPIOX (13UL) -#define GPIO_OE_GPIOY (14UL) -#define GPIO_OE_GPIOZ (15UL) - -/* IF register group index macro definition */ -#define GPIO_IF_GPIOA (0UL) -#define GPIO_IF_GPIOB (1UL) -#define GPIO_IF_GPIOC (2UL) -#define GPIO_IF_GPIOD (3UL) -#define GPIO_IF_GPIOE (4UL) -#define GPIO_IF_GPIOF (5UL) -#define GPIO_IF_GPIOV (11UL) -#define GPIO_IF_GPIOW (12UL) -#define GPIO_IF_GPIOX (13UL) -#define GPIO_IF_GPIOY (14UL) -#define GPIO_IF_GPIOZ (15UL) - -/* IE register group index macro definition */ -#define GPIO_IE_GPIOA (0UL) -#define GPIO_IE_GPIOB (1UL) -#define GPIO_IE_GPIOC (2UL) -#define GPIO_IE_GPIOD (3UL) -#define GPIO_IE_GPIOE (4UL) -#define GPIO_IE_GPIOF (5UL) -#define GPIO_IE_GPIOV (11UL) -#define GPIO_IE_GPIOW (12UL) -#define GPIO_IE_GPIOX (13UL) -#define GPIO_IE_GPIOY (14UL) -#define GPIO_IE_GPIOZ (15UL) - -/* PL register group index macro definition */ -#define GPIO_PL_GPIOA (0UL) -#define GPIO_PL_GPIOB (1UL) -#define GPIO_PL_GPIOC (2UL) -#define GPIO_PL_GPIOD (3UL) -#define GPIO_PL_GPIOE (4UL) -#define GPIO_PL_GPIOF (5UL) -#define GPIO_PL_GPIOV (11UL) -#define GPIO_PL_GPIOW (12UL) -#define GPIO_PL_GPIOX (13UL) -#define GPIO_PL_GPIOY (14UL) -#define GPIO_PL_GPIOZ (15UL) - -/* TP register group index macro definition */ -#define GPIO_TP_GPIOA (0UL) -#define GPIO_TP_GPIOB (1UL) -#define GPIO_TP_GPIOC (2UL) -#define GPIO_TP_GPIOD (3UL) -#define GPIO_TP_GPIOE (4UL) -#define GPIO_TP_GPIOF (5UL) -#define GPIO_TP_GPIOV (11UL) -#define GPIO_TP_GPIOW (12UL) -#define GPIO_TP_GPIOX (13UL) -#define GPIO_TP_GPIOY (14UL) -#define GPIO_TP_GPIOZ (15UL) - -/* AS register group index macro definition */ -#define GPIO_AS_GPIOA (0UL) -#define GPIO_AS_GPIOB (1UL) -#define GPIO_AS_GPIOC (2UL) -#define GPIO_AS_GPIOD (3UL) -#define GPIO_AS_GPIOE (4UL) -#define GPIO_AS_GPIOF (5UL) -#define GPIO_AS_GPIOV (11UL) -#define GPIO_AS_GPIOW (12UL) -#define GPIO_AS_GPIOX (13UL) -#define GPIO_AS_GPIOY (14UL) -#define GPIO_AS_GPIOZ (15UL) - -/* PD register group index macro definition */ -#define GPIO_PD_GPIOA (0UL) -#define GPIO_PD_GPIOB (1UL) -#define GPIO_PD_GPIOC (2UL) -#define GPIO_PD_GPIOD (3UL) -#define GPIO_PD_GPIOE (4UL) -#define GPIO_PD_GPIOF (5UL) -#define GPIO_PD_GPIOV (11UL) -#define GPIO_PD_GPIOW (12UL) -#define GPIO_PD_GPIOX (13UL) -#define GPIO_PD_GPIOY (14UL) -#define GPIO_PD_GPIOZ (15UL) - - -#endif /* HPM_GPIO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gpiom_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gpiom_regs.h deleted file mode 100644 index bd163813d51..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gpiom_regs.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPIOM_H -#define HPM_GPIOM_H - -typedef struct { - struct { - __RW uint32_t PIN[32]; /* 0x0 - 0x7C: GPIO mananger */ - } ASSIGN[16]; -} GPIOM_Type; - - -/* Bitfield definition for register of struct array ASSIGN: PIN00 */ -/* - * LOCK (RW) - * - * lock fields in this register, lock can only be cleared by soc reset - * 0: fields can be changed - * 1: fields locked to current value, not changeable - */ -#define GPIOM_ASSIGN_PIN_LOCK_MASK (0x80000000UL) -#define GPIOM_ASSIGN_PIN_LOCK_SHIFT (31U) -#define GPIOM_ASSIGN_PIN_LOCK_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_LOCK_SHIFT) & GPIOM_ASSIGN_PIN_LOCK_MASK) -#define GPIOM_ASSIGN_PIN_LOCK_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_LOCK_MASK) >> GPIOM_ASSIGN_PIN_LOCK_SHIFT) - -/* - * HIDE (RW) - * - * pin value visibility to gpios, - * bit0: 1, invisible to soc gpio0; 0: visible to soc gpio0 - * bit1: 1, invisible to soc gpio1; 0: visible to soc gpio1 - * bit2: 1, invisible to cpu0 fast gpio; 0: visible to cpu0 fast gpio - * bit3: 1, invisible to cpu1 fast gpio; 0: visible to cpu1 fast gpio - */ -#define GPIOM_ASSIGN_PIN_HIDE_MASK (0xF00U) -#define GPIOM_ASSIGN_PIN_HIDE_SHIFT (8U) -#define GPIOM_ASSIGN_PIN_HIDE_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_HIDE_SHIFT) & GPIOM_ASSIGN_PIN_HIDE_MASK) -#define GPIOM_ASSIGN_PIN_HIDE_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_HIDE_MASK) >> GPIOM_ASSIGN_PIN_HIDE_SHIFT) - -/* - * SELECT (RW) - * - * select which gpio controls chip pin, - * 0: soc gpio0; - * 1: soc gpio1; - * 2: cpu0 fastgpio - * 3: cpu1 fast gpio - */ -#define GPIOM_ASSIGN_PIN_SELECT_MASK (0x3U) -#define GPIOM_ASSIGN_PIN_SELECT_SHIFT (0U) -#define GPIOM_ASSIGN_PIN_SELECT_SET(x) (((uint32_t)(x) << GPIOM_ASSIGN_PIN_SELECT_SHIFT) & GPIOM_ASSIGN_PIN_SELECT_MASK) -#define GPIOM_ASSIGN_PIN_SELECT_GET(x) (((uint32_t)(x) & GPIOM_ASSIGN_PIN_SELECT_MASK) >> GPIOM_ASSIGN_PIN_SELECT_SHIFT) - - - -/* PIN register group index macro definition */ -#define GPIOM_ASSIGN_PIN_PIN00 (0UL) -#define GPIOM_ASSIGN_PIN_PIN01 (1UL) -#define GPIOM_ASSIGN_PIN_PIN02 (2UL) -#define GPIOM_ASSIGN_PIN_PIN03 (3UL) -#define GPIOM_ASSIGN_PIN_PIN04 (4UL) -#define GPIOM_ASSIGN_PIN_PIN05 (5UL) -#define GPIOM_ASSIGN_PIN_PIN06 (6UL) -#define GPIOM_ASSIGN_PIN_PIN07 (7UL) -#define GPIOM_ASSIGN_PIN_PIN08 (8UL) -#define GPIOM_ASSIGN_PIN_PIN09 (9UL) -#define GPIOM_ASSIGN_PIN_PIN10 (10UL) -#define GPIOM_ASSIGN_PIN_PIN11 (11UL) -#define GPIOM_ASSIGN_PIN_PIN12 (12UL) -#define GPIOM_ASSIGN_PIN_PIN13 (13UL) -#define GPIOM_ASSIGN_PIN_PIN14 (14UL) -#define GPIOM_ASSIGN_PIN_PIN15 (15UL) -#define GPIOM_ASSIGN_PIN_PIN16 (16UL) -#define GPIOM_ASSIGN_PIN_PIN17 (17UL) -#define GPIOM_ASSIGN_PIN_PIN18 (18UL) -#define GPIOM_ASSIGN_PIN_PIN19 (19UL) -#define GPIOM_ASSIGN_PIN_PIN20 (20UL) -#define GPIOM_ASSIGN_PIN_PIN21 (21UL) -#define GPIOM_ASSIGN_PIN_PIN22 (22UL) -#define GPIOM_ASSIGN_PIN_PIN23 (23UL) -#define GPIOM_ASSIGN_PIN_PIN24 (24UL) -#define GPIOM_ASSIGN_PIN_PIN25 (25UL) -#define GPIOM_ASSIGN_PIN_PIN26 (26UL) -#define GPIOM_ASSIGN_PIN_PIN27 (27UL) -#define GPIOM_ASSIGN_PIN_PIN28 (28UL) -#define GPIOM_ASSIGN_PIN_PIN29 (29UL) -#define GPIOM_ASSIGN_PIN_PIN30 (30UL) -#define GPIOM_ASSIGN_PIN_PIN31 (31UL) - -/* ASSIGN register group index macro definition */ -#define GPIOM_ASSIGN_GPIOA (0UL) -#define GPIOM_ASSIGN_GPIOB (1UL) -#define GPIOM_ASSIGN_GPIOC (2UL) -#define GPIOM_ASSIGN_GPIOD (3UL) -#define GPIOM_ASSIGN_GPIOE (4UL) -#define GPIOM_ASSIGN_GPIOF (5UL) -#define GPIOM_ASSIGN_GPIOY (14UL) -#define GPIOM_ASSIGN_GPIOZ (15UL) - - -#endif /* HPM_GPIOM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gptmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gptmr_regs.h deleted file mode 100644 index 3ab05475ca9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_gptmr_regs.h +++ /dev/null @@ -1,655 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_GPTMR_H -#define HPM_GPTMR_H - -typedef struct { - struct { - __RW uint32_t CR; /* 0x0: Control Register */ - __RW uint32_t CMP[2]; /* 0x4 - 0x8: Comparator register 0 */ - __RW uint32_t RLD; /* 0xC: Reload register */ - __RW uint32_t CNTUPTVAL; /* 0x10: Counter update value register */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t CAPPOS; /* 0x20: Capture rising edge register */ - __R uint32_t CAPNEG; /* 0x24: Capture falling edge register */ - __R uint32_t CAPPRD; /* 0x28: PWM period measure register */ - __R uint32_t CAPDTY; /* 0x2C: PWM duty cycle measure register */ - __R uint32_t CNT; /* 0x30: Counter */ - __R uint8_t RESERVED1[12]; /* 0x34 - 0x3F: Reserved */ - } CHANNEL[4]; - __R uint8_t RESERVED0[256]; /* 0x100 - 0x1FF: Reserved */ - __RW uint32_t SR; /* 0x200: Status register */ - __RW uint32_t IRQEN; /* 0x204: Interrupt request enable register */ - __RW uint32_t GCR; /* 0x208: Global control register */ -} GPTMR_Type; - - -/* Bitfield definition for register of struct array CHANNEL: CR */ -/* - * CNTUPT (WO) - * - * 1- update counter to new value as CNTUPTVAL - * This bit will be auto cleared after 1 cycle - */ -#define GPTMR_CHANNEL_CR_CNTUPT_MASK (0x80000000UL) -#define GPTMR_CHANNEL_CR_CNTUPT_SHIFT (31U) -#define GPTMR_CHANNEL_CR_CNTUPT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTUPT_SHIFT) & GPTMR_CHANNEL_CR_CNTUPT_MASK) -#define GPTMR_CHANNEL_CR_CNTUPT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTUPT_MASK) >> GPTMR_CHANNEL_CR_CNTUPT_SHIFT) - -/* - * CNT_MODE (RW) - * - * 0: internal counting mode, timer increase each gptmr clock cycle. - * 1: external counting mode, timer increase at each input signal posedge, reload/compare feature can still work but change at input signal posedge. - */ -#define GPTMR_CHANNEL_CR_CNT_MODE_MASK (0x40000UL) -#define GPTMR_CHANNEL_CR_CNT_MODE_SHIFT (18U) -#define GPTMR_CHANNEL_CR_CNT_MODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNT_MODE_SHIFT) & GPTMR_CHANNEL_CR_CNT_MODE_MASK) -#define GPTMR_CHANNEL_CR_CNT_MODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNT_MODE_MASK) >> GPTMR_CHANNEL_CR_CNT_MODE_SHIFT) - -/* - * OPMODE (RW) - * - * 0: round mode - * 1: one-shot mode, timer will stopped at reload point.user need clear CEN and set it to start timer agian. - * NOTE: reload irq will be always set at one-shot mode at end - */ -#define GPTMR_CHANNEL_CR_OPMODE_MASK (0x20000UL) -#define GPTMR_CHANNEL_CR_OPMODE_SHIFT (17U) -#define GPTMR_CHANNEL_CR_OPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_OPMODE_SHIFT) & GPTMR_CHANNEL_CR_OPMODE_MASK) -#define GPTMR_CHANNEL_CR_OPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_OPMODE_MASK) >> GPTMR_CHANNEL_CR_OPMODE_SHIFT) - -/* - * MONITOR_SEL (RW) - * - * set to monitor input signal high level time(chan_meas_high) - * clr to monitor input signal period(chan_meas_prd) - */ -#define GPTMR_CHANNEL_CR_MONITOR_SEL_MASK (0x10000UL) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT (16U) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) -#define GPTMR_CHANNEL_CR_MONITOR_SEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_SEL_MASK) >> GPTMR_CHANNEL_CR_MONITOR_SEL_SHIFT) - -/* - * MONITOR_EN (RW) - * - * set to monitor input signal period or high level time. - * When this bit is set, if detected period less than val_0 or more than val_1, will set related irq_sts - * * only can be used when trig_mode is selected as measure mode(100) - * * the time may not correct after reload, so monitor is disabled after reload point, and enabled again after two continul posedge. - * if no posedge after reload for more than val_1, will also assert irq_capt - */ -#define GPTMR_CHANNEL_CR_MONITOR_EN_MASK (0x8000U) -#define GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT (15U) -#define GPTMR_CHANNEL_CR_MONITOR_EN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) -#define GPTMR_CHANNEL_CR_MONITOR_EN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_MONITOR_EN_MASK) >> GPTMR_CHANNEL_CR_MONITOR_EN_SHIFT) - -/* - * CNTRST (RW) - * - * 1- reset counter - */ -#define GPTMR_CHANNEL_CR_CNTRST_MASK (0x4000U) -#define GPTMR_CHANNEL_CR_CNTRST_SHIFT (14U) -#define GPTMR_CHANNEL_CR_CNTRST_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CNTRST_SHIFT) & GPTMR_CHANNEL_CR_CNTRST_MASK) -#define GPTMR_CHANNEL_CR_CNTRST_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CNTRST_MASK) >> GPTMR_CHANNEL_CR_CNTRST_SHIFT) - -/* - * SYNCFLW (RW) - * - * 1- enable this channel to reset counter to reload(RLD) together with its previous channel. - * This bit is not valid for channel 0. - */ -#define GPTMR_CHANNEL_CR_SYNCFLW_MASK (0x2000U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SHIFT (13U) -#define GPTMR_CHANNEL_CR_SYNCFLW_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) -#define GPTMR_CHANNEL_CR_SYNCFLW_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCFLW_MASK) >> GPTMR_CHANNEL_CR_SYNCFLW_SHIFT) - -/* - * SYNCIFEN (RW) - * - * 1- SYNCI is valid on its falling edge - */ -#define GPTMR_CHANNEL_CR_SYNCIFEN_MASK (0x1000U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT (12U) -#define GPTMR_CHANNEL_CR_SYNCIFEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIFEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIFEN_MASK) >> GPTMR_CHANNEL_CR_SYNCIFEN_SHIFT) - -/* - * SYNCIREN (RW) - * - * 1- SYNCI is valid on its rising edge - */ -#define GPTMR_CHANNEL_CR_SYNCIREN_MASK (0x800U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SHIFT (11U) -#define GPTMR_CHANNEL_CR_SYNCIREN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) -#define GPTMR_CHANNEL_CR_SYNCIREN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SYNCIREN_MASK) >> GPTMR_CHANNEL_CR_SYNCIREN_SHIFT) - -/* - * CEN (RW) - * - * 1- counter enable - */ -#define GPTMR_CHANNEL_CR_CEN_MASK (0x400U) -#define GPTMR_CHANNEL_CR_CEN_SHIFT (10U) -#define GPTMR_CHANNEL_CR_CEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CEN_SHIFT) & GPTMR_CHANNEL_CR_CEN_MASK) -#define GPTMR_CHANNEL_CR_CEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CEN_MASK) >> GPTMR_CHANNEL_CR_CEN_SHIFT) - -/* - * CMPINIT (RW) - * - * Output compare initial poliarity - * 1- The channel output initial level is high - * 0- The channel output initial level is low - * User should set this bit before set CMPEN to 1. - */ -#define GPTMR_CHANNEL_CR_CMPINIT_MASK (0x200U) -#define GPTMR_CHANNEL_CR_CMPINIT_SHIFT (9U) -#define GPTMR_CHANNEL_CR_CMPINIT_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPINIT_SHIFT) & GPTMR_CHANNEL_CR_CMPINIT_MASK) -#define GPTMR_CHANNEL_CR_CMPINIT_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPINIT_MASK) >> GPTMR_CHANNEL_CR_CMPINIT_SHIFT) - -/* - * CMPEN (RW) - * - * 1- Enable the channel output compare function. The output signal can be generated per comparator (CMPx) settings. - */ -#define GPTMR_CHANNEL_CR_CMPEN_MASK (0x100U) -#define GPTMR_CHANNEL_CR_CMPEN_SHIFT (8U) -#define GPTMR_CHANNEL_CR_CMPEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CMPEN_SHIFT) & GPTMR_CHANNEL_CR_CMPEN_MASK) -#define GPTMR_CHANNEL_CR_CMPEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CMPEN_MASK) >> GPTMR_CHANNEL_CR_CMPEN_SHIFT) - -/* - * DMASEL (RW) - * - * select one of DMA request: - * 00- CMP0 flag - * 01- CMP1 flag - * 10- Input signal toggle captured - * 11- RLD flag, counter reload; - */ -#define GPTMR_CHANNEL_CR_DMASEL_MASK (0xC0U) -#define GPTMR_CHANNEL_CR_DMASEL_SHIFT (6U) -#define GPTMR_CHANNEL_CR_DMASEL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMASEL_SHIFT) & GPTMR_CHANNEL_CR_DMASEL_MASK) -#define GPTMR_CHANNEL_CR_DMASEL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMASEL_MASK) >> GPTMR_CHANNEL_CR_DMASEL_SHIFT) - -/* - * DMAEN (RW) - * - * 1- enable dma - */ -#define GPTMR_CHANNEL_CR_DMAEN_MASK (0x20U) -#define GPTMR_CHANNEL_CR_DMAEN_SHIFT (5U) -#define GPTMR_CHANNEL_CR_DMAEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DMAEN_SHIFT) & GPTMR_CHANNEL_CR_DMAEN_MASK) -#define GPTMR_CHANNEL_CR_DMAEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DMAEN_MASK) >> GPTMR_CHANNEL_CR_DMAEN_SHIFT) - -/* - * SWSYNCIEN (RW) - * - * 1- enable software sync. When this bit is set, counter will reset to RLD when swsynct bit is set - */ -#define GPTMR_CHANNEL_CR_SWSYNCIEN_MASK (0x10U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT (4U) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) -#define GPTMR_CHANNEL_CR_SWSYNCIEN_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_SWSYNCIEN_MASK) >> GPTMR_CHANNEL_CR_SWSYNCIEN_SHIFT) - -/* - * DBGPAUSE (RW) - * - * 1- counter will pause if chip is in debug mode - */ -#define GPTMR_CHANNEL_CR_DBGPAUSE_MASK (0x8U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT (3U) -#define GPTMR_CHANNEL_CR_DBGPAUSE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) -#define GPTMR_CHANNEL_CR_DBGPAUSE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_DBGPAUSE_MASK) >> GPTMR_CHANNEL_CR_DBGPAUSE_SHIFT) - -/* - * CAPMODE (RW) - * - * This bitfield define the input capture mode - * 100: width measure mode, timer will calculate the input signal period and duty cycle - * 011: capture at both rising edge and falling edge - * 010: capture at falling edge - * 001: capture at rising edge - * 000: No capture - */ -#define GPTMR_CHANNEL_CR_CAPMODE_MASK (0x7U) -#define GPTMR_CHANNEL_CR_CAPMODE_SHIFT (0U) -#define GPTMR_CHANNEL_CR_CAPMODE_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CR_CAPMODE_SHIFT) & GPTMR_CHANNEL_CR_CAPMODE_MASK) -#define GPTMR_CHANNEL_CR_CAPMODE_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CR_CAPMODE_MASK) >> GPTMR_CHANNEL_CR_CAPMODE_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CMP0 */ -/* - * CMP (RW) - * - * compare value 0 - */ -#define GPTMR_CHANNEL_CMP_CMP_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CMP_CMP_SHIFT (0U) -#define GPTMR_CHANNEL_CMP_CMP_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CMP_CMP_SHIFT) & GPTMR_CHANNEL_CMP_CMP_MASK) -#define GPTMR_CHANNEL_CMP_CMP_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CMP_CMP_MASK) >> GPTMR_CHANNEL_CMP_CMP_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: RLD */ -/* - * RLD (RW) - * - * reload value - */ -#define GPTMR_CHANNEL_RLD_RLD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_RLD_RLD_SHIFT (0U) -#define GPTMR_CHANNEL_RLD_RLD_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_RLD_RLD_SHIFT) & GPTMR_CHANNEL_RLD_RLD_MASK) -#define GPTMR_CHANNEL_RLD_RLD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_RLD_RLD_MASK) >> GPTMR_CHANNEL_RLD_RLD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNTUPTVAL */ -/* - * CNTUPTVAL (RW) - * - * counter will be set to this value when software write cntupt bit in CR - */ -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT (0U) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SET(x) (((uint32_t)(x) << GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) -#define GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_MASK) >> GPTMR_CHANNEL_CNTUPTVAL_CNTUPTVAL_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPOS */ -/* - * CAPPOS (RO) - * - * This register contains the counter value captured at input signal rising edge - */ -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPOS_CAPPOS_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPOS_CAPPOS_MASK) >> GPTMR_CHANNEL_CAPPOS_CAPPOS_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPNEG */ -/* - * CAPNEG (RO) - * - * This register contains the counter value captured at input signal falling edge - */ -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT (0U) -#define GPTMR_CHANNEL_CAPNEG_CAPNEG_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPNEG_CAPNEG_MASK) >> GPTMR_CHANNEL_CAPNEG_CAPNEG_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPPRD */ -/* - * CAPPRD (RO) - * - * This register contains the input signal period when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT (0U) -#define GPTMR_CHANNEL_CAPPRD_CAPPRD_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPPRD_CAPPRD_MASK) >> GPTMR_CHANNEL_CAPPRD_CAPPRD_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CAPDTY */ -/* - * MEAS_HIGH (RO) - * - * This register contains the input signal duty cycle when channel is configured to input capture measure mode. - */ -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT (0U) -#define GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_MASK) >> GPTMR_CHANNEL_CAPDTY_MEAS_HIGH_SHIFT) - -/* Bitfield definition for register of struct array CHANNEL: CNT */ -/* - * COUNTER (RO) - * - * 32 bit counter value - */ -#define GPTMR_CHANNEL_CNT_COUNTER_MASK (0xFFFFFFFFUL) -#define GPTMR_CHANNEL_CNT_COUNTER_SHIFT (0U) -#define GPTMR_CHANNEL_CNT_COUNTER_GET(x) (((uint32_t)(x) & GPTMR_CHANNEL_CNT_COUNTER_MASK) >> GPTMR_CHANNEL_CNT_COUNTER_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * CH3CMP1F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP1F_MASK (0x8000U) -#define GPTMR_SR_CH3CMP1F_SHIFT (15U) -#define GPTMR_SR_CH3CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP1F_SHIFT) & GPTMR_SR_CH3CMP1F_MASK) -#define GPTMR_SR_CH3CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP1F_MASK) >> GPTMR_SR_CH3CMP1F_SHIFT) - -/* - * CH3CMP0F (W1C) - * - * channel 3 compare value 1 match flag - */ -#define GPTMR_SR_CH3CMP0F_MASK (0x4000U) -#define GPTMR_SR_CH3CMP0F_SHIFT (14U) -#define GPTMR_SR_CH3CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CMP0F_SHIFT) & GPTMR_SR_CH3CMP0F_MASK) -#define GPTMR_SR_CH3CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CMP0F_MASK) >> GPTMR_SR_CH3CMP0F_SHIFT) - -/* - * CH3CAPF (W1C) - * - * channel 3 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH3CAPF_MASK (0x2000U) -#define GPTMR_SR_CH3CAPF_SHIFT (13U) -#define GPTMR_SR_CH3CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3CAPF_SHIFT) & GPTMR_SR_CH3CAPF_MASK) -#define GPTMR_SR_CH3CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3CAPF_MASK) >> GPTMR_SR_CH3CAPF_SHIFT) - -/* - * CH3RLDF (W1C) - * - * channel 3 counter reload flag - */ -#define GPTMR_SR_CH3RLDF_MASK (0x1000U) -#define GPTMR_SR_CH3RLDF_SHIFT (12U) -#define GPTMR_SR_CH3RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH3RLDF_SHIFT) & GPTMR_SR_CH3RLDF_MASK) -#define GPTMR_SR_CH3RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH3RLDF_MASK) >> GPTMR_SR_CH3RLDF_SHIFT) - -/* - * CH2CMP1F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP1F_MASK (0x800U) -#define GPTMR_SR_CH2CMP1F_SHIFT (11U) -#define GPTMR_SR_CH2CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP1F_SHIFT) & GPTMR_SR_CH2CMP1F_MASK) -#define GPTMR_SR_CH2CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP1F_MASK) >> GPTMR_SR_CH2CMP1F_SHIFT) - -/* - * CH2CMP0F (W1C) - * - * channel 2 compare value 1 match flag - */ -#define GPTMR_SR_CH2CMP0F_MASK (0x400U) -#define GPTMR_SR_CH2CMP0F_SHIFT (10U) -#define GPTMR_SR_CH2CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CMP0F_SHIFT) & GPTMR_SR_CH2CMP0F_MASK) -#define GPTMR_SR_CH2CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CMP0F_MASK) >> GPTMR_SR_CH2CMP0F_SHIFT) - -/* - * CH2CAPF (W1C) - * - * channel 2 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH2CAPF_MASK (0x200U) -#define GPTMR_SR_CH2CAPF_SHIFT (9U) -#define GPTMR_SR_CH2CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2CAPF_SHIFT) & GPTMR_SR_CH2CAPF_MASK) -#define GPTMR_SR_CH2CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2CAPF_MASK) >> GPTMR_SR_CH2CAPF_SHIFT) - -/* - * CH2RLDF (W1C) - * - * channel 2 counter reload flag - */ -#define GPTMR_SR_CH2RLDF_MASK (0x100U) -#define GPTMR_SR_CH2RLDF_SHIFT (8U) -#define GPTMR_SR_CH2RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH2RLDF_SHIFT) & GPTMR_SR_CH2RLDF_MASK) -#define GPTMR_SR_CH2RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH2RLDF_MASK) >> GPTMR_SR_CH2RLDF_SHIFT) - -/* - * CH1CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP1F_MASK (0x80U) -#define GPTMR_SR_CH1CMP1F_SHIFT (7U) -#define GPTMR_SR_CH1CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP1F_SHIFT) & GPTMR_SR_CH1CMP1F_MASK) -#define GPTMR_SR_CH1CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP1F_MASK) >> GPTMR_SR_CH1CMP1F_SHIFT) - -/* - * CH1CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH1CMP0F_MASK (0x40U) -#define GPTMR_SR_CH1CMP0F_SHIFT (6U) -#define GPTMR_SR_CH1CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CMP0F_SHIFT) & GPTMR_SR_CH1CMP0F_MASK) -#define GPTMR_SR_CH1CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CMP0F_MASK) >> GPTMR_SR_CH1CMP0F_SHIFT) - -/* - * CH1CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH1CAPF_MASK (0x20U) -#define GPTMR_SR_CH1CAPF_SHIFT (5U) -#define GPTMR_SR_CH1CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1CAPF_SHIFT) & GPTMR_SR_CH1CAPF_MASK) -#define GPTMR_SR_CH1CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1CAPF_MASK) >> GPTMR_SR_CH1CAPF_SHIFT) - -/* - * CH1RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH1RLDF_MASK (0x10U) -#define GPTMR_SR_CH1RLDF_SHIFT (4U) -#define GPTMR_SR_CH1RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH1RLDF_SHIFT) & GPTMR_SR_CH1RLDF_MASK) -#define GPTMR_SR_CH1RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH1RLDF_MASK) >> GPTMR_SR_CH1RLDF_SHIFT) - -/* - * CH0CMP1F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP1F_MASK (0x8U) -#define GPTMR_SR_CH0CMP1F_SHIFT (3U) -#define GPTMR_SR_CH0CMP1F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP1F_SHIFT) & GPTMR_SR_CH0CMP1F_MASK) -#define GPTMR_SR_CH0CMP1F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP1F_MASK) >> GPTMR_SR_CH0CMP1F_SHIFT) - -/* - * CH0CMP0F (W1C) - * - * channel 1 compare value 1 match flag - */ -#define GPTMR_SR_CH0CMP0F_MASK (0x4U) -#define GPTMR_SR_CH0CMP0F_SHIFT (2U) -#define GPTMR_SR_CH0CMP0F_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CMP0F_SHIFT) & GPTMR_SR_CH0CMP0F_MASK) -#define GPTMR_SR_CH0CMP0F_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CMP0F_MASK) >> GPTMR_SR_CH0CMP0F_SHIFT) - -/* - * CH0CAPF (W1C) - * - * channel 1 capture flag, the flag will be set at the valid capture edge per CAPMODE setting. If the capture channel is set to measure mode, the flag will be set at rising edge. - */ -#define GPTMR_SR_CH0CAPF_MASK (0x2U) -#define GPTMR_SR_CH0CAPF_SHIFT (1U) -#define GPTMR_SR_CH0CAPF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0CAPF_SHIFT) & GPTMR_SR_CH0CAPF_MASK) -#define GPTMR_SR_CH0CAPF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0CAPF_MASK) >> GPTMR_SR_CH0CAPF_SHIFT) - -/* - * CH0RLDF (W1C) - * - * channel 1 counter reload flag - */ -#define GPTMR_SR_CH0RLDF_MASK (0x1U) -#define GPTMR_SR_CH0RLDF_SHIFT (0U) -#define GPTMR_SR_CH0RLDF_SET(x) (((uint32_t)(x) << GPTMR_SR_CH0RLDF_SHIFT) & GPTMR_SR_CH0RLDF_MASK) -#define GPTMR_SR_CH0RLDF_GET(x) (((uint32_t)(x) & GPTMR_SR_CH0RLDF_MASK) >> GPTMR_SR_CH0RLDF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * CH3CMP1EN (RW) - * - * 1- generate interrupt request when ch3cmp1f flag is set - */ -#define GPTMR_IRQEN_CH3CMP1EN_MASK (0x8000U) -#define GPTMR_IRQEN_CH3CMP1EN_SHIFT (15U) -#define GPTMR_IRQEN_CH3CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP1EN_SHIFT) & GPTMR_IRQEN_CH3CMP1EN_MASK) -#define GPTMR_IRQEN_CH3CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP1EN_MASK) >> GPTMR_IRQEN_CH3CMP1EN_SHIFT) - -/* - * CH3CMP0EN (RW) - * - * 1- generate interrupt request when ch3cmp0f flag is set - */ -#define GPTMR_IRQEN_CH3CMP0EN_MASK (0x4000U) -#define GPTMR_IRQEN_CH3CMP0EN_SHIFT (14U) -#define GPTMR_IRQEN_CH3CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CMP0EN_SHIFT) & GPTMR_IRQEN_CH3CMP0EN_MASK) -#define GPTMR_IRQEN_CH3CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CMP0EN_MASK) >> GPTMR_IRQEN_CH3CMP0EN_SHIFT) - -/* - * CH3CAPEN (RW) - * - * 1- generate interrupt request when ch3capf flag is set - */ -#define GPTMR_IRQEN_CH3CAPEN_MASK (0x2000U) -#define GPTMR_IRQEN_CH3CAPEN_SHIFT (13U) -#define GPTMR_IRQEN_CH3CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3CAPEN_SHIFT) & GPTMR_IRQEN_CH3CAPEN_MASK) -#define GPTMR_IRQEN_CH3CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3CAPEN_MASK) >> GPTMR_IRQEN_CH3CAPEN_SHIFT) - -/* - * CH3RLDEN (RW) - * - * 1- generate interrupt request when ch3rldf flag is set - */ -#define GPTMR_IRQEN_CH3RLDEN_MASK (0x1000U) -#define GPTMR_IRQEN_CH3RLDEN_SHIFT (12U) -#define GPTMR_IRQEN_CH3RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH3RLDEN_SHIFT) & GPTMR_IRQEN_CH3RLDEN_MASK) -#define GPTMR_IRQEN_CH3RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH3RLDEN_MASK) >> GPTMR_IRQEN_CH3RLDEN_SHIFT) - -/* - * CH2CMP1EN (RW) - * - * 1- generate interrupt request when ch2cmp1f flag is set - */ -#define GPTMR_IRQEN_CH2CMP1EN_MASK (0x800U) -#define GPTMR_IRQEN_CH2CMP1EN_SHIFT (11U) -#define GPTMR_IRQEN_CH2CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP1EN_SHIFT) & GPTMR_IRQEN_CH2CMP1EN_MASK) -#define GPTMR_IRQEN_CH2CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP1EN_MASK) >> GPTMR_IRQEN_CH2CMP1EN_SHIFT) - -/* - * CH2CMP0EN (RW) - * - * 1- generate interrupt request when ch2cmp0f flag is set - */ -#define GPTMR_IRQEN_CH2CMP0EN_MASK (0x400U) -#define GPTMR_IRQEN_CH2CMP0EN_SHIFT (10U) -#define GPTMR_IRQEN_CH2CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CMP0EN_SHIFT) & GPTMR_IRQEN_CH2CMP0EN_MASK) -#define GPTMR_IRQEN_CH2CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CMP0EN_MASK) >> GPTMR_IRQEN_CH2CMP0EN_SHIFT) - -/* - * CH2CAPEN (RW) - * - * 1- generate interrupt request when ch2capf flag is set - */ -#define GPTMR_IRQEN_CH2CAPEN_MASK (0x200U) -#define GPTMR_IRQEN_CH2CAPEN_SHIFT (9U) -#define GPTMR_IRQEN_CH2CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2CAPEN_SHIFT) & GPTMR_IRQEN_CH2CAPEN_MASK) -#define GPTMR_IRQEN_CH2CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2CAPEN_MASK) >> GPTMR_IRQEN_CH2CAPEN_SHIFT) - -/* - * CH2RLDEN (RW) - * - * 1- generate interrupt request when ch2rldf flag is set - */ -#define GPTMR_IRQEN_CH2RLDEN_MASK (0x100U) -#define GPTMR_IRQEN_CH2RLDEN_SHIFT (8U) -#define GPTMR_IRQEN_CH2RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH2RLDEN_SHIFT) & GPTMR_IRQEN_CH2RLDEN_MASK) -#define GPTMR_IRQEN_CH2RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH2RLDEN_MASK) >> GPTMR_IRQEN_CH2RLDEN_SHIFT) - -/* - * CH1CMP1EN (RW) - * - * 1- generate interrupt request when ch1cmp1f flag is set - */ -#define GPTMR_IRQEN_CH1CMP1EN_MASK (0x80U) -#define GPTMR_IRQEN_CH1CMP1EN_SHIFT (7U) -#define GPTMR_IRQEN_CH1CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP1EN_SHIFT) & GPTMR_IRQEN_CH1CMP1EN_MASK) -#define GPTMR_IRQEN_CH1CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP1EN_MASK) >> GPTMR_IRQEN_CH1CMP1EN_SHIFT) - -/* - * CH1CMP0EN (RW) - * - * 1- generate interrupt request when ch1cmp0f flag is set - */ -#define GPTMR_IRQEN_CH1CMP0EN_MASK (0x40U) -#define GPTMR_IRQEN_CH1CMP0EN_SHIFT (6U) -#define GPTMR_IRQEN_CH1CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CMP0EN_SHIFT) & GPTMR_IRQEN_CH1CMP0EN_MASK) -#define GPTMR_IRQEN_CH1CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CMP0EN_MASK) >> GPTMR_IRQEN_CH1CMP0EN_SHIFT) - -/* - * CH1CAPEN (RW) - * - * 1- generate interrupt request when ch1capf flag is set - */ -#define GPTMR_IRQEN_CH1CAPEN_MASK (0x20U) -#define GPTMR_IRQEN_CH1CAPEN_SHIFT (5U) -#define GPTMR_IRQEN_CH1CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1CAPEN_SHIFT) & GPTMR_IRQEN_CH1CAPEN_MASK) -#define GPTMR_IRQEN_CH1CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1CAPEN_MASK) >> GPTMR_IRQEN_CH1CAPEN_SHIFT) - -/* - * CH1RLDEN (RW) - * - * 1- generate interrupt request when ch1rldf flag is set - */ -#define GPTMR_IRQEN_CH1RLDEN_MASK (0x10U) -#define GPTMR_IRQEN_CH1RLDEN_SHIFT (4U) -#define GPTMR_IRQEN_CH1RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH1RLDEN_SHIFT) & GPTMR_IRQEN_CH1RLDEN_MASK) -#define GPTMR_IRQEN_CH1RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH1RLDEN_MASK) >> GPTMR_IRQEN_CH1RLDEN_SHIFT) - -/* - * CH0CMP1EN (RW) - * - * 1- generate interrupt request when ch0cmp1f flag is set - */ -#define GPTMR_IRQEN_CH0CMP1EN_MASK (0x8U) -#define GPTMR_IRQEN_CH0CMP1EN_SHIFT (3U) -#define GPTMR_IRQEN_CH0CMP1EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP1EN_SHIFT) & GPTMR_IRQEN_CH0CMP1EN_MASK) -#define GPTMR_IRQEN_CH0CMP1EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP1EN_MASK) >> GPTMR_IRQEN_CH0CMP1EN_SHIFT) - -/* - * CH0CMP0EN (RW) - * - * 1- generate interrupt request when ch0cmp0f flag is set - */ -#define GPTMR_IRQEN_CH0CMP0EN_MASK (0x4U) -#define GPTMR_IRQEN_CH0CMP0EN_SHIFT (2U) -#define GPTMR_IRQEN_CH0CMP0EN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CMP0EN_SHIFT) & GPTMR_IRQEN_CH0CMP0EN_MASK) -#define GPTMR_IRQEN_CH0CMP0EN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CMP0EN_MASK) >> GPTMR_IRQEN_CH0CMP0EN_SHIFT) - -/* - * CH0CAPEN (RW) - * - * 1- generate interrupt request when ch0capf flag is set - */ -#define GPTMR_IRQEN_CH0CAPEN_MASK (0x2U) -#define GPTMR_IRQEN_CH0CAPEN_SHIFT (1U) -#define GPTMR_IRQEN_CH0CAPEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0CAPEN_SHIFT) & GPTMR_IRQEN_CH0CAPEN_MASK) -#define GPTMR_IRQEN_CH0CAPEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0CAPEN_MASK) >> GPTMR_IRQEN_CH0CAPEN_SHIFT) - -/* - * CH0RLDEN (RW) - * - * 1- generate interrupt request when ch0rldf flag is set - */ -#define GPTMR_IRQEN_CH0RLDEN_MASK (0x1U) -#define GPTMR_IRQEN_CH0RLDEN_SHIFT (0U) -#define GPTMR_IRQEN_CH0RLDEN_SET(x) (((uint32_t)(x) << GPTMR_IRQEN_CH0RLDEN_SHIFT) & GPTMR_IRQEN_CH0RLDEN_MASK) -#define GPTMR_IRQEN_CH0RLDEN_GET(x) (((uint32_t)(x) & GPTMR_IRQEN_CH0RLDEN_MASK) >> GPTMR_IRQEN_CH0RLDEN_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * SWSYNCT (RW) - * - * set this bitfield to trigger software counter sync event - */ -#define GPTMR_GCR_SWSYNCT_MASK (0xFU) -#define GPTMR_GCR_SWSYNCT_SHIFT (0U) -#define GPTMR_GCR_SWSYNCT_SET(x) (((uint32_t)(x) << GPTMR_GCR_SWSYNCT_SHIFT) & GPTMR_GCR_SWSYNCT_MASK) -#define GPTMR_GCR_SWSYNCT_GET(x) (((uint32_t)(x) & GPTMR_GCR_SWSYNCT_MASK) >> GPTMR_GCR_SWSYNCT_SHIFT) - - - -/* CMP register group index macro definition */ -#define GPTMR_CHANNEL_CMP_CMP0 (0UL) -#define GPTMR_CHANNEL_CMP_CMP1 (1UL) - -/* CHANNEL register group index macro definition */ -#define GPTMR_CHANNEL_CH0 (0UL) -#define GPTMR_CHANNEL_CH1 (1UL) -#define GPTMR_CHANNEL_CH2 (2UL) -#define GPTMR_CHANNEL_CH3 (3UL) - - -#endif /* HPM_GPTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_i2c_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_i2c_regs.h deleted file mode 100644 index 1446ec912e7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_i2c_regs.h +++ /dev/null @@ -1,602 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2C_H -#define HPM_I2C_H - -typedef struct { - __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t INTEN; /* 0x14: Interrupt Enable Register */ - __RW uint32_t STATUS; /* 0x18: Status Register */ - __RW uint32_t ADDR; /* 0x1C: Address Register */ - __RW uint32_t DATA; /* 0x20: Data Register */ - __RW uint32_t CTRL; /* 0x24: Control Register */ - __RW uint32_t CMD; /* 0x28: Command Register */ - __RW uint32_t SETUP; /* 0x2C: Setup Register */ - __RW uint32_t TPM; /* 0x30: I2C Timing Paramater Multiplier */ -} I2C_Type; - - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * FIFO Size: - * 0: 2 bytes - * 1: 4 bytes - * 2: 8 bytes - * 3: 16 bytes - */ -#define I2C_CFG_FIFOSIZE_MASK (0x3U) -#define I2C_CFG_FIFOSIZE_SHIFT (0U) -#define I2C_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & I2C_CFG_FIFOSIZE_MASK) >> I2C_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * CMPL (RW) - * - * Set to enable the Completion Interrupt. - * Master: interrupts when a transaction is issued from this master and completed without losing the bus arbitration. - * Slave: interrupts when a transaction addressing the controller is completed. - */ -#define I2C_INTEN_CMPL_MASK (0x200U) -#define I2C_INTEN_CMPL_SHIFT (9U) -#define I2C_INTEN_CMPL_SET(x) (((uint32_t)(x) << I2C_INTEN_CMPL_SHIFT) & I2C_INTEN_CMPL_MASK) -#define I2C_INTEN_CMPL_GET(x) (((uint32_t)(x) & I2C_INTEN_CMPL_MASK) >> I2C_INTEN_CMPL_SHIFT) - -/* - * BYTERECV (RW) - * - * Set to enable the Byte Receive Interrupt. - * Interrupts when a byte of data is received - * Auto-ACK will be disabled if this interrupt is enabled, that is, the software needs to ACK/NACK the received byte manually. - */ -#define I2C_INTEN_BYTERECV_MASK (0x100U) -#define I2C_INTEN_BYTERECV_SHIFT (8U) -#define I2C_INTEN_BYTERECV_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTERECV_SHIFT) & I2C_INTEN_BYTERECV_MASK) -#define I2C_INTEN_BYTERECV_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTERECV_MASK) >> I2C_INTEN_BYTERECV_SHIFT) - -/* - * BYTETRANS (RW) - * - * Set to enable the Byte Transmit Interrupt. - * Interrupts when a byte of data is transmitted. - */ -#define I2C_INTEN_BYTETRANS_MASK (0x80U) -#define I2C_INTEN_BYTETRANS_SHIFT (7U) -#define I2C_INTEN_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_INTEN_BYTETRANS_SHIFT) & I2C_INTEN_BYTETRANS_MASK) -#define I2C_INTEN_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_INTEN_BYTETRANS_MASK) >> I2C_INTEN_BYTETRANS_SHIFT) - -/* - * START (RW) - * - * Set to enable the START Condition Interrupt. - * Interrupts when a START condition/repeated START condition is detected. - */ -#define I2C_INTEN_START_MASK (0x40U) -#define I2C_INTEN_START_SHIFT (6U) -#define I2C_INTEN_START_SET(x) (((uint32_t)(x) << I2C_INTEN_START_SHIFT) & I2C_INTEN_START_MASK) -#define I2C_INTEN_START_GET(x) (((uint32_t)(x) & I2C_INTEN_START_MASK) >> I2C_INTEN_START_SHIFT) - -/* - * STOP (RW) - * - * Set to enable the STOP Condition Interrupt - * Interrupts when a STOP condition is detected. - */ -#define I2C_INTEN_STOP_MASK (0x20U) -#define I2C_INTEN_STOP_SHIFT (5U) -#define I2C_INTEN_STOP_SET(x) (((uint32_t)(x) << I2C_INTEN_STOP_SHIFT) & I2C_INTEN_STOP_MASK) -#define I2C_INTEN_STOP_GET(x) (((uint32_t)(x) & I2C_INTEN_STOP_MASK) >> I2C_INTEN_STOP_SHIFT) - -/* - * ARBLOSE (RW) - * - * Set to enable the Arbitration Lose Interrupt. - * Master: interrupts when the controller loses the bus arbitration - * Slave: not available in this mode. - */ -#define I2C_INTEN_ARBLOSE_MASK (0x10U) -#define I2C_INTEN_ARBLOSE_SHIFT (4U) -#define I2C_INTEN_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_INTEN_ARBLOSE_SHIFT) & I2C_INTEN_ARBLOSE_MASK) -#define I2C_INTEN_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_INTEN_ARBLOSE_MASK) >> I2C_INTEN_ARBLOSE_SHIFT) - -/* - * ADDRHIT (RW) - * - * Set to enable the Address Hit Interrupt. - * Master: interrupts when the addressed slave returned an ACK. - * Slave: interrupts when the controller is addressed. - */ -#define I2C_INTEN_ADDRHIT_MASK (0x8U) -#define I2C_INTEN_ADDRHIT_SHIFT (3U) -#define I2C_INTEN_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_INTEN_ADDRHIT_SHIFT) & I2C_INTEN_ADDRHIT_MASK) -#define I2C_INTEN_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_INTEN_ADDRHIT_MASK) >> I2C_INTEN_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RW) - * - * Set to enable the FIFO Half Interrupt. - * Receiver: Interrupts when the FIFO is half-empty, i.e, there is >= 1/2 entries in the FIFO. - * Transmitter: Interrupts when the FIFO is half-empty, i.e. there is <= 1/2 entries in the FIFO. - * This interrupt depends on the transaction direction; don’t enable this interrupt unless the transfer direction is determined, otherwise unintended interrupts may be triggered. - */ -#define I2C_INTEN_FIFOHALF_MASK (0x4U) -#define I2C_INTEN_FIFOHALF_SHIFT (2U) -#define I2C_INTEN_FIFOHALF_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOHALF_SHIFT) & I2C_INTEN_FIFOHALF_MASK) -#define I2C_INTEN_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOHALF_MASK) >> I2C_INTEN_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RW) - * - * Set to enable the FIFO Full Interrupt. - * Interrupts when the FIFO is full. - */ -#define I2C_INTEN_FIFOFULL_MASK (0x2U) -#define I2C_INTEN_FIFOFULL_SHIFT (1U) -#define I2C_INTEN_FIFOFULL_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOFULL_SHIFT) & I2C_INTEN_FIFOFULL_MASK) -#define I2C_INTEN_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOFULL_MASK) >> I2C_INTEN_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RW) - * - * Set to enabled the FIFO Empty Interrupt - * Interrupts when the FIFO is empty. - */ -#define I2C_INTEN_FIFOEMPTY_MASK (0x1U) -#define I2C_INTEN_FIFOEMPTY_SHIFT (0U) -#define I2C_INTEN_FIFOEMPTY_SET(x) (((uint32_t)(x) << I2C_INTEN_FIFOEMPTY_SHIFT) & I2C_INTEN_FIFOEMPTY_MASK) -#define I2C_INTEN_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_INTEN_FIFOEMPTY_MASK) >> I2C_INTEN_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * LINESDA (RO) - * - * Indicates the current status of the SDA line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESDA_MASK (0x4000U) -#define I2C_STATUS_LINESDA_SHIFT (14U) -#define I2C_STATUS_LINESDA_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESDA_MASK) >> I2C_STATUS_LINESDA_SHIFT) - -/* - * LINESCL (RO) - * - * Indicates the current status of the SCL line on the bus - * 1: high - * 0: low - */ -#define I2C_STATUS_LINESCL_MASK (0x2000U) -#define I2C_STATUS_LINESCL_SHIFT (13U) -#define I2C_STATUS_LINESCL_GET(x) (((uint32_t)(x) & I2C_STATUS_LINESCL_MASK) >> I2C_STATUS_LINESCL_SHIFT) - -/* - * GENCALL (RO) - * - * Indicates that the address of the current transaction is a general call address: - * 1: General call - * 0: Not general call - */ -#define I2C_STATUS_GENCALL_MASK (0x1000U) -#define I2C_STATUS_GENCALL_SHIFT (12U) -#define I2C_STATUS_GENCALL_GET(x) (((uint32_t)(x) & I2C_STATUS_GENCALL_MASK) >> I2C_STATUS_GENCALL_SHIFT) - -/* - * BUSBUSY (RO) - * - * Indicates that the bus is busy - * The bus is busy when a START condition is on bus and it ends when a STOP condition is seen on bus - * 1: Busy - * 0: Not busy - */ -#define I2C_STATUS_BUSBUSY_MASK (0x800U) -#define I2C_STATUS_BUSBUSY_SHIFT (11U) -#define I2C_STATUS_BUSBUSY_GET(x) (((uint32_t)(x) & I2C_STATUS_BUSBUSY_MASK) >> I2C_STATUS_BUSBUSY_SHIFT) - -/* - * ACK (RO) - * - * Indicates the type of the last received/transmitted acknowledgement bit: - * 1: ACK - * 0: NACK - */ -#define I2C_STATUS_ACK_MASK (0x400U) -#define I2C_STATUS_ACK_SHIFT (10U) -#define I2C_STATUS_ACK_GET(x) (((uint32_t)(x) & I2C_STATUS_ACK_MASK) >> I2C_STATUS_ACK_SHIFT) - -/* - * CMPL (W1C) - * - * Transaction Completion - * Master: Indicates that a transaction has been issued from this master and completed without losing the bus arbitration - * Slave: Indicates that a transaction addressing the controller has been completed. This status bit must be cleared to receive the next transaction; otherwise, the next incoming transaction will be blocked. - */ -#define I2C_STATUS_CMPL_MASK (0x200U) -#define I2C_STATUS_CMPL_SHIFT (9U) -#define I2C_STATUS_CMPL_SET(x) (((uint32_t)(x) << I2C_STATUS_CMPL_SHIFT) & I2C_STATUS_CMPL_MASK) -#define I2C_STATUS_CMPL_GET(x) (((uint32_t)(x) & I2C_STATUS_CMPL_MASK) >> I2C_STATUS_CMPL_SHIFT) - -/* - * BYTERECV (W1C) - * - * Indicates that a byte of data has been received. - */ -#define I2C_STATUS_BYTERECV_MASK (0x100U) -#define I2C_STATUS_BYTERECV_SHIFT (8U) -#define I2C_STATUS_BYTERECV_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTERECV_SHIFT) & I2C_STATUS_BYTERECV_MASK) -#define I2C_STATUS_BYTERECV_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTERECV_MASK) >> I2C_STATUS_BYTERECV_SHIFT) - -/* - * BYTETRANS (W1C) - * - * Indicates that a byte of data has been transmitted. - */ -#define I2C_STATUS_BYTETRANS_MASK (0x80U) -#define I2C_STATUS_BYTETRANS_SHIFT (7U) -#define I2C_STATUS_BYTETRANS_SET(x) (((uint32_t)(x) << I2C_STATUS_BYTETRANS_SHIFT) & I2C_STATUS_BYTETRANS_MASK) -#define I2C_STATUS_BYTETRANS_GET(x) (((uint32_t)(x) & I2C_STATUS_BYTETRANS_MASK) >> I2C_STATUS_BYTETRANS_SHIFT) - -/* - * START (W1C) - * - * Indicates that a START Condition or a repeated START condition has been transmitted/received. - */ -#define I2C_STATUS_START_MASK (0x40U) -#define I2C_STATUS_START_SHIFT (6U) -#define I2C_STATUS_START_SET(x) (((uint32_t)(x) << I2C_STATUS_START_SHIFT) & I2C_STATUS_START_MASK) -#define I2C_STATUS_START_GET(x) (((uint32_t)(x) & I2C_STATUS_START_MASK) >> I2C_STATUS_START_SHIFT) - -/* - * STOP (W1C) - * - * Indicates that a STOP Condition has been transmitted/received. - */ -#define I2C_STATUS_STOP_MASK (0x20U) -#define I2C_STATUS_STOP_SHIFT (5U) -#define I2C_STATUS_STOP_SET(x) (((uint32_t)(x) << I2C_STATUS_STOP_SHIFT) & I2C_STATUS_STOP_MASK) -#define I2C_STATUS_STOP_GET(x) (((uint32_t)(x) & I2C_STATUS_STOP_MASK) >> I2C_STATUS_STOP_SHIFT) - -/* - * ARBLOSE (W1C) - * - * Indicates that the controller has lost the bus arbitration. - */ -#define I2C_STATUS_ARBLOSE_MASK (0x10U) -#define I2C_STATUS_ARBLOSE_SHIFT (4U) -#define I2C_STATUS_ARBLOSE_SET(x) (((uint32_t)(x) << I2C_STATUS_ARBLOSE_SHIFT) & I2C_STATUS_ARBLOSE_MASK) -#define I2C_STATUS_ARBLOSE_GET(x) (((uint32_t)(x) & I2C_STATUS_ARBLOSE_MASK) >> I2C_STATUS_ARBLOSE_SHIFT) - -/* - * ADDRHIT (W1C) - * - * Master: indicates that a slave has responded to the transaction. - * Slave: indicates that a transaction is targeting the controller (including the General Call). - */ -#define I2C_STATUS_ADDRHIT_MASK (0x8U) -#define I2C_STATUS_ADDRHIT_SHIFT (3U) -#define I2C_STATUS_ADDRHIT_SET(x) (((uint32_t)(x) << I2C_STATUS_ADDRHIT_SHIFT) & I2C_STATUS_ADDRHIT_MASK) -#define I2C_STATUS_ADDRHIT_GET(x) (((uint32_t)(x) & I2C_STATUS_ADDRHIT_MASK) >> I2C_STATUS_ADDRHIT_SHIFT) - -/* - * FIFOHALF (RO) - * - * Transmitter: Indicates that the FIFO is half-empty. - */ -#define I2C_STATUS_FIFOHALF_MASK (0x4U) -#define I2C_STATUS_FIFOHALF_SHIFT (2U) -#define I2C_STATUS_FIFOHALF_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOHALF_MASK) >> I2C_STATUS_FIFOHALF_SHIFT) - -/* - * FIFOFULL (RO) - * - * Indicates that the FIFO is full. - */ -#define I2C_STATUS_FIFOFULL_MASK (0x2U) -#define I2C_STATUS_FIFOFULL_SHIFT (1U) -#define I2C_STATUS_FIFOFULL_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOFULL_MASK) >> I2C_STATUS_FIFOFULL_SHIFT) - -/* - * FIFOEMPTY (RO) - * - * Indicates that the FIFO is empty. - */ -#define I2C_STATUS_FIFOEMPTY_MASK (0x1U) -#define I2C_STATUS_FIFOEMPTY_SHIFT (0U) -#define I2C_STATUS_FIFOEMPTY_GET(x) (((uint32_t)(x) & I2C_STATUS_FIFOEMPTY_MASK) >> I2C_STATUS_FIFOEMPTY_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * The slave address. - * For 7-bit addressing mode, the most significant 3 bits are ignored and only the least-significant 7 bits of Addr are valid - */ -#define I2C_ADDR_ADDR_MASK (0x3FFU) -#define I2C_ADDR_ADDR_SHIFT (0U) -#define I2C_ADDR_ADDR_SET(x) (((uint32_t)(x) << I2C_ADDR_ADDR_SHIFT) & I2C_ADDR_ADDR_MASK) -#define I2C_ADDR_ADDR_GET(x) (((uint32_t)(x) & I2C_ADDR_ADDR_MASK) >> I2C_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Write this register to put one byte of data to the FIFO. - * Read this register to get one byte of data from the FIFO. - */ -#define I2C_DATA_DATA_MASK (0xFFU) -#define I2C_DATA_DATA_SHIFT (0U) -#define I2C_DATA_DATA_SET(x) (((uint32_t)(x) << I2C_DATA_DATA_SHIFT) & I2C_DATA_DATA_MASK) -#define I2C_DATA_DATA_GET(x) (((uint32_t)(x) & I2C_DATA_DATA_MASK) >> I2C_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * DATACNT_HIGH (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_HIGH_MASK (0xFF000000UL) -#define I2C_CTRL_DATACNT_HIGH_SHIFT (24U) -#define I2C_CTRL_DATACNT_HIGH_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_HIGH_SHIFT) & I2C_CTRL_DATACNT_HIGH_MASK) -#define I2C_CTRL_DATACNT_HIGH_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_HIGH_MASK) >> I2C_CTRL_DATACNT_HIGH_SHIFT) - -/* - * RESET_LEN (RW) - * - * reset clock cycles. the clock high/low time is defined by Setup.T_SCLHi, 50% duty cycle. - */ -#define I2C_CTRL_RESET_LEN_MASK (0xF00000UL) -#define I2C_CTRL_RESET_LEN_SHIFT (20U) -#define I2C_CTRL_RESET_LEN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_LEN_SHIFT) & I2C_CTRL_RESET_LEN_MASK) -#define I2C_CTRL_RESET_LEN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_LEN_MASK) >> I2C_CTRL_RESET_LEN_SHIFT) - -/* - * RESET_HOLD_SCKIN (RW) - * - * set to hold input clock to high when reset is active - */ -#define I2C_CTRL_RESET_HOLD_SCKIN_MASK (0x4000U) -#define I2C_CTRL_RESET_HOLD_SCKIN_SHIFT (14U) -#define I2C_CTRL_RESET_HOLD_SCKIN_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) -#define I2C_CTRL_RESET_HOLD_SCKIN_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_HOLD_SCKIN_MASK) >> I2C_CTRL_RESET_HOLD_SCKIN_SHIFT) - -/* - * RESET_ON (RW) - * - * set to send reset signals(just toggle clock bus defined by reset_len). - * this register is clered when reset is end, can't be cleared by software - */ -#define I2C_CTRL_RESET_ON_MASK (0x2000U) -#define I2C_CTRL_RESET_ON_SHIFT (13U) -#define I2C_CTRL_RESET_ON_SET(x) (((uint32_t)(x) << I2C_CTRL_RESET_ON_SHIFT) & I2C_CTRL_RESET_ON_MASK) -#define I2C_CTRL_RESET_ON_GET(x) (((uint32_t)(x) & I2C_CTRL_RESET_ON_MASK) >> I2C_CTRL_RESET_ON_SHIFT) - -/* - * PHASE_START (RW) - * - * Enable this bit to send a START condition at the beginning of transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_START_MASK (0x1000U) -#define I2C_CTRL_PHASE_START_SHIFT (12U) -#define I2C_CTRL_PHASE_START_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_START_SHIFT) & I2C_CTRL_PHASE_START_MASK) -#define I2C_CTRL_PHASE_START_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_START_MASK) >> I2C_CTRL_PHASE_START_SHIFT) - -/* - * PHASE_ADDR (RW) - * - * Enable this bit to send the address after START condition. - * Master mode only. - */ -#define I2C_CTRL_PHASE_ADDR_MASK (0x800U) -#define I2C_CTRL_PHASE_ADDR_SHIFT (11U) -#define I2C_CTRL_PHASE_ADDR_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_ADDR_SHIFT) & I2C_CTRL_PHASE_ADDR_MASK) -#define I2C_CTRL_PHASE_ADDR_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_ADDR_MASK) >> I2C_CTRL_PHASE_ADDR_SHIFT) - -/* - * PHASE_DATA (RW) - * - * Enable this bit to send the data after Address phase. - * Master mode only. - */ -#define I2C_CTRL_PHASE_DATA_MASK (0x400U) -#define I2C_CTRL_PHASE_DATA_SHIFT (10U) -#define I2C_CTRL_PHASE_DATA_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_DATA_SHIFT) & I2C_CTRL_PHASE_DATA_MASK) -#define I2C_CTRL_PHASE_DATA_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_DATA_MASK) >> I2C_CTRL_PHASE_DATA_SHIFT) - -/* - * PHASE_STOP (RW) - * - * Enable this bit to send a STOP condition at the end of a transaction. - * Master mode only. - */ -#define I2C_CTRL_PHASE_STOP_MASK (0x200U) -#define I2C_CTRL_PHASE_STOP_SHIFT (9U) -#define I2C_CTRL_PHASE_STOP_SET(x) (((uint32_t)(x) << I2C_CTRL_PHASE_STOP_SHIFT) & I2C_CTRL_PHASE_STOP_MASK) -#define I2C_CTRL_PHASE_STOP_GET(x) (((uint32_t)(x) & I2C_CTRL_PHASE_STOP_MASK) >> I2C_CTRL_PHASE_STOP_SHIFT) - -/* - * DIR (RW) - * - * Transaction direction - * Master: Set this bit to determine the direction for the next transaction. - * 0: Transmitter - * 1: Receiver - * Slave: The direction of the last received transaction. - * 0: Receiver - * 1: Transmitter - */ -#define I2C_CTRL_DIR_MASK (0x100U) -#define I2C_CTRL_DIR_SHIFT (8U) -#define I2C_CTRL_DIR_SET(x) (((uint32_t)(x) << I2C_CTRL_DIR_SHIFT) & I2C_CTRL_DIR_MASK) -#define I2C_CTRL_DIR_GET(x) (((uint32_t)(x) & I2C_CTRL_DIR_MASK) >> I2C_CTRL_DIR_SHIFT) - -/* - * DATACNT (RW) - * - * Data counts in bytes. - * Master: The number of bytes to transmit/receive. 0 means max length. DataCnt will be decreased by one for each byte transmitted/received. - * Slave: the meaning of DataCnt depends on the DMA mode: - * If DMA is not enabled, DataCnt is the number of bytes transmitted/received from the bus master. It is reset to 0 when the controller is addressed and then increased by one for each byte of data transmitted/received. - * If DMA is enabled, DataCnt is the number of bytes to transmit/receive. It will not be reset to 0 when the slave is addressed and it will be decreased by one for each byte of data transmitted/received. - */ -#define I2C_CTRL_DATACNT_MASK (0xFFU) -#define I2C_CTRL_DATACNT_SHIFT (0U) -#define I2C_CTRL_DATACNT_SET(x) (((uint32_t)(x) << I2C_CTRL_DATACNT_SHIFT) & I2C_CTRL_DATACNT_MASK) -#define I2C_CTRL_DATACNT_GET(x) (((uint32_t)(x) & I2C_CTRL_DATACNT_MASK) >> I2C_CTRL_DATACNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * Write this register with the following values to perform the corresponding actions: - * 0x0: no action - * 0x1: issue a data transaction (Master only) - * 0x2: respond with an ACK to the received byte - * 0x3: respond with a NACK to the received byte - * 0x4: clear the FIFO - * 0x5: reset the I2C controller (abort current transaction, set the SDA and SCL line to the open-drain mode, reset the Status Register and the Interrupt Enable Register, and empty the FIFO) - * When issuing a data transaction by writing 0x1 to this register, the CMD field stays at 0x1 for the duration of the entire transaction, and it is only cleared to 0x0 after when the transaction has completed or when the controller loses the arbitration. - * Note: No transaction will be issued by the controller when all phases (Start, Address, Data and Stop) are disabled. - */ -#define I2C_CMD_CMD_MASK (0x7U) -#define I2C_CMD_CMD_SHIFT (0U) -#define I2C_CMD_CMD_SET(x) (((uint32_t)(x) << I2C_CMD_CMD_SHIFT) & I2C_CMD_CMD_MASK) -#define I2C_CMD_CMD_GET(x) (((uint32_t)(x) & I2C_CMD_CMD_MASK) >> I2C_CMD_CMD_SHIFT) - -/* Bitfield definition for register: SETUP */ -/* - * T_SUDAT (RW) - * - * T_SUDAT defines the data setup time before releasing the SCL. - * Setup time = (2 * tpclk) + (2 + T_SP + T_SUDAT) * tpclk* (TPM+1) - * tpclk = PCLK period - * TPM = The multiplier value in Timing Parameter Multiplier Register - */ -#define I2C_SETUP_T_SUDAT_MASK (0x1F000000UL) -#define I2C_SETUP_T_SUDAT_SHIFT (24U) -#define I2C_SETUP_T_SUDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SUDAT_SHIFT) & I2C_SETUP_T_SUDAT_MASK) -#define I2C_SETUP_T_SUDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SUDAT_MASK) >> I2C_SETUP_T_SUDAT_SHIFT) - -/* - * T_SP (RW) - * - * T_SP defines the pulse width of spikes that must be suppressed by the input filter. - * Pulse width = T_SP * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_SP_MASK (0xE00000UL) -#define I2C_SETUP_T_SP_SHIFT (21U) -#define I2C_SETUP_T_SP_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SP_SHIFT) & I2C_SETUP_T_SP_MASK) -#define I2C_SETUP_T_SP_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SP_MASK) >> I2C_SETUP_T_SP_SHIFT) - -/* - * T_HDDAT (RW) - * - * T_HDDAT defines the data hold time after SCL goes LOW - * Hold time = (2 * tpclk) + (2 + T_SP + T_HDDAT) * tpclk* (TPM+1) - */ -#define I2C_SETUP_T_HDDAT_MASK (0x1F0000UL) -#define I2C_SETUP_T_HDDAT_SHIFT (16U) -#define I2C_SETUP_T_HDDAT_SET(x) (((uint32_t)(x) << I2C_SETUP_T_HDDAT_SHIFT) & I2C_SETUP_T_HDDAT_MASK) -#define I2C_SETUP_T_HDDAT_GET(x) (((uint32_t)(x) & I2C_SETUP_T_HDDAT_MASK) >> I2C_SETUP_T_HDDAT_SHIFT) - -/* - * T_SCLRADIO (RW) - * - * The LOW period of the generated SCL clock is defined by the combination of T_SCLRatio and T_SCLHi values. When T_SCLRatio = 0, the LOW period is equal to HIGH period. When T_SCLRatio = 1, the LOW period is roughly two times of HIGH period. - * SCL LOW period = (2 * tpclk) + (2 + T_SP + T_SCLHi * ratio) * tpclk * (TPM+1) - * 1: ratio = 2 - * 0: ratio = 1 - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLRADIO_MASK (0x2000U) -#define I2C_SETUP_T_SCLRADIO_SHIFT (13U) -#define I2C_SETUP_T_SCLRADIO_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLRADIO_SHIFT) & I2C_SETUP_T_SCLRADIO_MASK) -#define I2C_SETUP_T_SCLRADIO_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLRADIO_MASK) >> I2C_SETUP_T_SCLRADIO_SHIFT) - -/* - * T_SCLHI (RW) - * - * The HIGH period of generated SCL clock is defined by T_SCLHi. - * SCL HIGH period = (2 * tpclk) + (2 + T_SP + T_SCLHi) * tpclk* (TPM+1) - * The T_SCLHi value must be greater than T_SP and T_HDDAT values. - * This field is only valid when the controller is in the master mode. - */ -#define I2C_SETUP_T_SCLHI_MASK (0x1FF0U) -#define I2C_SETUP_T_SCLHI_SHIFT (4U) -#define I2C_SETUP_T_SCLHI_SET(x) (((uint32_t)(x) << I2C_SETUP_T_SCLHI_SHIFT) & I2C_SETUP_T_SCLHI_MASK) -#define I2C_SETUP_T_SCLHI_GET(x) (((uint32_t)(x) & I2C_SETUP_T_SCLHI_MASK) >> I2C_SETUP_T_SCLHI_SHIFT) - -/* - * DMAEN (RW) - * - * Enable the direct memory access mode data transfer. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_DMAEN_MASK (0x8U) -#define I2C_SETUP_DMAEN_SHIFT (3U) -#define I2C_SETUP_DMAEN_SET(x) (((uint32_t)(x) << I2C_SETUP_DMAEN_SHIFT) & I2C_SETUP_DMAEN_MASK) -#define I2C_SETUP_DMAEN_GET(x) (((uint32_t)(x) & I2C_SETUP_DMAEN_MASK) >> I2C_SETUP_DMAEN_SHIFT) - -/* - * MASTER (RW) - * - * Configure this device as a master or a slave. - * 1: Master mode - * 0: Slave mode - */ -#define I2C_SETUP_MASTER_MASK (0x4U) -#define I2C_SETUP_MASTER_SHIFT (2U) -#define I2C_SETUP_MASTER_SET(x) (((uint32_t)(x) << I2C_SETUP_MASTER_SHIFT) & I2C_SETUP_MASTER_MASK) -#define I2C_SETUP_MASTER_GET(x) (((uint32_t)(x) & I2C_SETUP_MASTER_MASK) >> I2C_SETUP_MASTER_SHIFT) - -/* - * ADDRESSING (RW) - * - * I2C addressing mode: - * 1: 10-bit addressing mode - * 0: 7-bit addressing mode - */ -#define I2C_SETUP_ADDRESSING_MASK (0x2U) -#define I2C_SETUP_ADDRESSING_SHIFT (1U) -#define I2C_SETUP_ADDRESSING_SET(x) (((uint32_t)(x) << I2C_SETUP_ADDRESSING_SHIFT) & I2C_SETUP_ADDRESSING_MASK) -#define I2C_SETUP_ADDRESSING_GET(x) (((uint32_t)(x) & I2C_SETUP_ADDRESSING_MASK) >> I2C_SETUP_ADDRESSING_SHIFT) - -/* - * IICEN (RW) - * - * Enable the I2C controller. - * 1: Enable - * 0: Disable - */ -#define I2C_SETUP_IICEN_MASK (0x1U) -#define I2C_SETUP_IICEN_SHIFT (0U) -#define I2C_SETUP_IICEN_SET(x) (((uint32_t)(x) << I2C_SETUP_IICEN_SHIFT) & I2C_SETUP_IICEN_MASK) -#define I2C_SETUP_IICEN_GET(x) (((uint32_t)(x) & I2C_SETUP_IICEN_MASK) >> I2C_SETUP_IICEN_SHIFT) - -/* Bitfield definition for register: TPM */ -/* - * TPM (RW) - * - * A multiplication value for I2C timing parameters. All the timing parameters in the Setup Register are multiplied by (TPM+1). - */ -#define I2C_TPM_TPM_MASK (0x1FU) -#define I2C_TPM_TPM_SHIFT (0U) -#define I2C_TPM_TPM_SET(x) (((uint32_t)(x) << I2C_TPM_TPM_SHIFT) & I2C_TPM_TPM_MASK) -#define I2C_TPM_TPM_GET(x) (((uint32_t)(x) & I2C_TPM_TPM_MASK) >> I2C_TPM_TPM_SHIFT) - - - - -#endif /* HPM_I2C_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_i2s_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_i2s_regs.h deleted file mode 100644 index 3d3b34d7aab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_i2s_regs.h +++ /dev/null @@ -1,591 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_I2S_H -#define HPM_I2S_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint32_t RFIFO_FILLINGS; /* 0x4: Rx FIFO Filling Level */ - __R uint32_t TFIFO_FILLINGS; /* 0x8: Tx FIFO Filling Level */ - __RW uint32_t FIFO_THRESH; /* 0xC: TX/RX FIFO Threshold setting. */ - __RW uint32_t STA; /* 0x10: Status Registers */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXD[4]; /* 0x20 - 0x2C: Rx Data0 */ - __W uint32_t TXD[4]; /* 0x30 - 0x3C: Tx Data0 */ - __R uint8_t RESERVED1[16]; /* 0x40 - 0x4F: Reserved */ - __RW uint32_t CFGR; /* 0x50: Configruation Regsiters */ - __R uint8_t RESERVED2[4]; /* 0x54 - 0x57: Reserved */ - __RW uint32_t MISC_CFGR; /* 0x58: Misc configuration Registers */ - __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */ - __RW uint32_t RXDSLOT[4]; /* 0x60 - 0x6C: Rx Slots Enable for Rx Data0 */ - __RW uint32_t TXDSLOT[4]; /* 0x70 - 0x7C: Tx Slots Enable for Tx Data0. */ -} I2S_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST_RX (RW) - * - * software reset the RX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_RX_MASK (0x40000UL) -#define I2S_CTRL_SFTRST_RX_SHIFT (18U) -#define I2S_CTRL_SFTRST_RX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_RX_SHIFT) & I2S_CTRL_SFTRST_RX_MASK) -#define I2S_CTRL_SFTRST_RX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_RX_MASK) >> I2S_CTRL_SFTRST_RX_SHIFT) - -/* - * SFTRST_TX (RW) - * - * software reset the TX module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_TX_MASK (0x20000UL) -#define I2S_CTRL_SFTRST_TX_SHIFT (17U) -#define I2S_CTRL_SFTRST_TX_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_TX_SHIFT) & I2S_CTRL_SFTRST_TX_MASK) -#define I2S_CTRL_SFTRST_TX_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_TX_MASK) >> I2S_CTRL_SFTRST_TX_SHIFT) - -/* - * SFTRST_CLKGEN (RW) - * - * software reset the CLK GEN module if asserted to be 1'b1. Self-clear. - */ -#define I2S_CTRL_SFTRST_CLKGEN_MASK (0x10000UL) -#define I2S_CTRL_SFTRST_CLKGEN_SHIFT (16U) -#define I2S_CTRL_SFTRST_CLKGEN_SET(x) (((uint32_t)(x) << I2S_CTRL_SFTRST_CLKGEN_SHIFT) & I2S_CTRL_SFTRST_CLKGEN_MASK) -#define I2S_CTRL_SFTRST_CLKGEN_GET(x) (((uint32_t)(x) & I2S_CTRL_SFTRST_CLKGEN_MASK) >> I2S_CTRL_SFTRST_CLKGEN_SHIFT) - -/* - * TXDNIE (RW) - * - * TX buffer data needed interrupt enable - * 0: TXE interrupt masked - * 1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set. - */ -#define I2S_CTRL_TXDNIE_MASK (0x8000U) -#define I2S_CTRL_TXDNIE_SHIFT (15U) -#define I2S_CTRL_TXDNIE_SET(x) (((uint32_t)(x) << I2S_CTRL_TXDNIE_SHIFT) & I2S_CTRL_TXDNIE_MASK) -#define I2S_CTRL_TXDNIE_GET(x) (((uint32_t)(x) & I2S_CTRL_TXDNIE_MASK) >> I2S_CTRL_TXDNIE_SHIFT) - -/* - * RXDAIE (RW) - * - * RX buffer data available interrupt enable - * 0: RXNE interrupt masked - * 1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set. - */ -#define I2S_CTRL_RXDAIE_MASK (0x4000U) -#define I2S_CTRL_RXDAIE_SHIFT (14U) -#define I2S_CTRL_RXDAIE_SET(x) (((uint32_t)(x) << I2S_CTRL_RXDAIE_SHIFT) & I2S_CTRL_RXDAIE_MASK) -#define I2S_CTRL_RXDAIE_GET(x) (((uint32_t)(x) & I2S_CTRL_RXDAIE_MASK) >> I2S_CTRL_RXDAIE_SHIFT) - -/* - * ERRIE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (UD, OV) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define I2S_CTRL_ERRIE_MASK (0x2000U) -#define I2S_CTRL_ERRIE_SHIFT (13U) -#define I2S_CTRL_ERRIE_SET(x) (((uint32_t)(x) << I2S_CTRL_ERRIE_SHIFT) & I2S_CTRL_ERRIE_MASK) -#define I2S_CTRL_ERRIE_GET(x) (((uint32_t)(x) & I2S_CTRL_ERRIE_MASK) >> I2S_CTRL_ERRIE_SHIFT) - -/* - * TX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_TX_DMA_EN_MASK (0x1000U) -#define I2S_CTRL_TX_DMA_EN_SHIFT (12U) -#define I2S_CTRL_TX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_DMA_EN_SHIFT) & I2S_CTRL_TX_DMA_EN_MASK) -#define I2S_CTRL_TX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_DMA_EN_MASK) >> I2S_CTRL_TX_DMA_EN_SHIFT) - -/* - * RX_DMA_EN (RW) - * - * Asserted to use DMA, else to use interrupt - */ -#define I2S_CTRL_RX_DMA_EN_MASK (0x800U) -#define I2S_CTRL_RX_DMA_EN_SHIFT (11U) -#define I2S_CTRL_RX_DMA_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_DMA_EN_SHIFT) & I2S_CTRL_RX_DMA_EN_MASK) -#define I2S_CTRL_RX_DMA_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_DMA_EN_MASK) >> I2S_CTRL_RX_DMA_EN_SHIFT) - -/* - * TXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_TXFIFOCLR_MASK (0x400U) -#define I2S_CTRL_TXFIFOCLR_SHIFT (10U) -#define I2S_CTRL_TXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_TXFIFOCLR_SHIFT) & I2S_CTRL_TXFIFOCLR_MASK) -#define I2S_CTRL_TXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_TXFIFOCLR_MASK) >> I2S_CTRL_TXFIFOCLR_SHIFT) - -/* - * RXFIFOCLR (RW) - * - * Self-clear - */ -#define I2S_CTRL_RXFIFOCLR_MASK (0x200U) -#define I2S_CTRL_RXFIFOCLR_SHIFT (9U) -#define I2S_CTRL_RXFIFOCLR_SET(x) (((uint32_t)(x) << I2S_CTRL_RXFIFOCLR_SHIFT) & I2S_CTRL_RXFIFOCLR_MASK) -#define I2S_CTRL_RXFIFOCLR_GET(x) (((uint32_t)(x) & I2S_CTRL_RXFIFOCLR_MASK) >> I2S_CTRL_RXFIFOCLR_SHIFT) - -/* - * TX_EN (RW) - * - * enable for each TX data pad - */ -#define I2S_CTRL_TX_EN_MASK (0x1E0U) -#define I2S_CTRL_TX_EN_SHIFT (5U) -#define I2S_CTRL_TX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_TX_EN_SHIFT) & I2S_CTRL_TX_EN_MASK) -#define I2S_CTRL_TX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_TX_EN_MASK) >> I2S_CTRL_TX_EN_SHIFT) - -/* - * RX_EN (RW) - * - * enable for each RX data pad - */ -#define I2S_CTRL_RX_EN_MASK (0x1EU) -#define I2S_CTRL_RX_EN_SHIFT (1U) -#define I2S_CTRL_RX_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_RX_EN_SHIFT) & I2S_CTRL_RX_EN_MASK) -#define I2S_CTRL_RX_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_RX_EN_MASK) >> I2S_CTRL_RX_EN_SHIFT) - -/* - * I2S_EN (RW) - * - * enable for the module - */ -#define I2S_CTRL_I2S_EN_MASK (0x1U) -#define I2S_CTRL_I2S_EN_SHIFT (0U) -#define I2S_CTRL_I2S_EN_SET(x) (((uint32_t)(x) << I2S_CTRL_I2S_EN_SHIFT) & I2S_CTRL_I2S_EN_MASK) -#define I2S_CTRL_I2S_EN_GET(x) (((uint32_t)(x) & I2S_CTRL_I2S_EN_MASK) >> I2S_CTRL_I2S_EN_SHIFT) - -/* Bitfield definition for register: RFIFO_FILLINGS */ -/* - * RX3 (RO) - * - * RX3 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX3_MASK (0xFF000000UL) -#define I2S_RFIFO_FILLINGS_RX3_SHIFT (24U) -#define I2S_RFIFO_FILLINGS_RX3_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX3_MASK) >> I2S_RFIFO_FILLINGS_RX3_SHIFT) - -/* - * RX2 (RO) - * - * RX2 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX2_MASK (0xFF0000UL) -#define I2S_RFIFO_FILLINGS_RX2_SHIFT (16U) -#define I2S_RFIFO_FILLINGS_RX2_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX2_MASK) >> I2S_RFIFO_FILLINGS_RX2_SHIFT) - -/* - * RX1 (RO) - * - * RX1 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX1_MASK (0xFF00U) -#define I2S_RFIFO_FILLINGS_RX1_SHIFT (8U) -#define I2S_RFIFO_FILLINGS_RX1_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX1_MASK) >> I2S_RFIFO_FILLINGS_RX1_SHIFT) - -/* - * RX0 (RO) - * - * RX0 fifo fillings - */ -#define I2S_RFIFO_FILLINGS_RX0_MASK (0xFFU) -#define I2S_RFIFO_FILLINGS_RX0_SHIFT (0U) -#define I2S_RFIFO_FILLINGS_RX0_GET(x) (((uint32_t)(x) & I2S_RFIFO_FILLINGS_RX0_MASK) >> I2S_RFIFO_FILLINGS_RX0_SHIFT) - -/* Bitfield definition for register: TFIFO_FILLINGS */ -/* - * TX3 (RO) - * - * TX3 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX3_MASK (0xFF000000UL) -#define I2S_TFIFO_FILLINGS_TX3_SHIFT (24U) -#define I2S_TFIFO_FILLINGS_TX3_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX3_MASK) >> I2S_TFIFO_FILLINGS_TX3_SHIFT) - -/* - * TX2 (RO) - * - * TX2 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX2_MASK (0xFF0000UL) -#define I2S_TFIFO_FILLINGS_TX2_SHIFT (16U) -#define I2S_TFIFO_FILLINGS_TX2_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX2_MASK) >> I2S_TFIFO_FILLINGS_TX2_SHIFT) - -/* - * TX1 (RO) - * - * TX1 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX1_MASK (0xFF00U) -#define I2S_TFIFO_FILLINGS_TX1_SHIFT (8U) -#define I2S_TFIFO_FILLINGS_TX1_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX1_MASK) >> I2S_TFIFO_FILLINGS_TX1_SHIFT) - -/* - * TX0 (RO) - * - * TX0 fifo fillings - */ -#define I2S_TFIFO_FILLINGS_TX0_MASK (0xFFU) -#define I2S_TFIFO_FILLINGS_TX0_SHIFT (0U) -#define I2S_TFIFO_FILLINGS_TX0_GET(x) (((uint32_t)(x) & I2S_TFIFO_FILLINGS_TX0_MASK) >> I2S_TFIFO_FILLINGS_TX0_SHIFT) - -/* Bitfield definition for register: FIFO_THRESH */ -/* - * TX (RW) - * - * TX fifo threshold to trigger STA[tx_dn]. When tx fifo filling is smaller than or equal to the threshold, assert the tx_dn flag. - */ -#define I2S_FIFO_THRESH_TX_MASK (0xFF00U) -#define I2S_FIFO_THRESH_TX_SHIFT (8U) -#define I2S_FIFO_THRESH_TX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_TX_SHIFT) & I2S_FIFO_THRESH_TX_MASK) -#define I2S_FIFO_THRESH_TX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_TX_MASK) >> I2S_FIFO_THRESH_TX_SHIFT) - -/* - * RX (RW) - * - * RX fifo threshold to trigger STA[rx_da]. When rx fifo filling is greater than or equal to the threshold, assert the rx_da flag. - */ -#define I2S_FIFO_THRESH_RX_MASK (0xFFU) -#define I2S_FIFO_THRESH_RX_SHIFT (0U) -#define I2S_FIFO_THRESH_RX_SET(x) (((uint32_t)(x) << I2S_FIFO_THRESH_RX_SHIFT) & I2S_FIFO_THRESH_RX_MASK) -#define I2S_FIFO_THRESH_RX_GET(x) (((uint32_t)(x) & I2S_FIFO_THRESH_RX_MASK) >> I2S_FIFO_THRESH_RX_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TX_UD (W1C) - * - * Asserted when tx fifo is underflow. Should be ANDed with CTRL[tx_en] the for correct value. Write 1 to any of these 4 bits will clear the underflow error. - */ -#define I2S_STA_TX_UD_MASK (0x1E000UL) -#define I2S_STA_TX_UD_SHIFT (13U) -#define I2S_STA_TX_UD_SET(x) (((uint32_t)(x) << I2S_STA_TX_UD_SHIFT) & I2S_STA_TX_UD_MASK) -#define I2S_STA_TX_UD_GET(x) (((uint32_t)(x) & I2S_STA_TX_UD_MASK) >> I2S_STA_TX_UD_SHIFT) - -/* - * RX_OV (W1C) - * - * Asserted when rx fifo is overflow. Write 1 to any of these 4 bits will clear the overflow error. - */ -#define I2S_STA_RX_OV_MASK (0x1E00U) -#define I2S_STA_RX_OV_SHIFT (9U) -#define I2S_STA_RX_OV_SET(x) (((uint32_t)(x) << I2S_STA_RX_OV_SHIFT) & I2S_STA_RX_OV_MASK) -#define I2S_STA_RX_OV_GET(x) (((uint32_t)(x) & I2S_STA_RX_OV_MASK) >> I2S_STA_RX_OV_SHIFT) - -/* - * TX_DN (RO) - * - * Asserted when tx fifo data are needed. - */ -#define I2S_STA_TX_DN_MASK (0x1E0U) -#define I2S_STA_TX_DN_SHIFT (5U) -#define I2S_STA_TX_DN_GET(x) (((uint32_t)(x) & I2S_STA_TX_DN_MASK) >> I2S_STA_TX_DN_SHIFT) - -/* - * RX_DA (RO) - * - * Asserted when rx fifo data are available. - */ -#define I2S_STA_RX_DA_MASK (0x1EU) -#define I2S_STA_RX_DA_SHIFT (1U) -#define I2S_STA_RX_DA_GET(x) (((uint32_t)(x) & I2S_STA_RX_DA_MASK) >> I2S_STA_RX_DA_SHIFT) - -/* Bitfield definition for register array: RXD */ -/* - * D (RO) - * - */ -#define I2S_RXD_D_MASK (0xFFFFFFFFUL) -#define I2S_RXD_D_SHIFT (0U) -#define I2S_RXD_D_GET(x) (((uint32_t)(x) & I2S_RXD_D_MASK) >> I2S_RXD_D_SHIFT) - -/* Bitfield definition for register array: TXD */ -/* - * D (WO) - * - */ -#define I2S_TXD_D_MASK (0xFFFFFFFFUL) -#define I2S_TXD_D_SHIFT (0U) -#define I2S_TXD_D_SET(x) (((uint32_t)(x) << I2S_TXD_D_SHIFT) & I2S_TXD_D_MASK) -#define I2S_TXD_D_GET(x) (((uint32_t)(x) & I2S_TXD_D_MASK) >> I2S_TXD_D_SHIFT) - -/* Bitfield definition for register: CFGR */ -/* - * BCLK_GATEOFF (RW) - * - * Gate off the bclk. Asserted to gate-off the BCLK. - */ -#define I2S_CFGR_BCLK_GATEOFF_MASK (0x40000000UL) -#define I2S_CFGR_BCLK_GATEOFF_SHIFT (30U) -#define I2S_CFGR_BCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_GATEOFF_SHIFT) & I2S_CFGR_BCLK_GATEOFF_MASK) -#define I2S_CFGR_BCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_GATEOFF_MASK) >> I2S_CFGR_BCLK_GATEOFF_SHIFT) - -/* - * BCLK_DIV (RW) - * - * Linear prescaler to generate BCLK from MCLK. - * BCLK_DIV [8:0] = 0: BCLK=No CLK. - * BCLK_DIV [8:0] = 1: BCLK=MCLK/1 - * BCLK_DIV [8:0] = n: BCLK=MCLK/(n). - * Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_CFGR_BCLK_DIV_MASK (0x3FE00000UL) -#define I2S_CFGR_BCLK_DIV_SHIFT (21U) -#define I2S_CFGR_BCLK_DIV_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_DIV_SHIFT) & I2S_CFGR_BCLK_DIV_MASK) -#define I2S_CFGR_BCLK_DIV_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_DIV_MASK) >> I2S_CFGR_BCLK_DIV_SHIFT) - -/* - * INV_BCLK_OUT (RW) - * - * Invert the BCLK before sending it out to pad. Only valid in BCLK master mode - */ -#define I2S_CFGR_INV_BCLK_OUT_MASK (0x100000UL) -#define I2S_CFGR_INV_BCLK_OUT_SHIFT (20U) -#define I2S_CFGR_INV_BCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_OUT_SHIFT) & I2S_CFGR_INV_BCLK_OUT_MASK) -#define I2S_CFGR_INV_BCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_OUT_MASK) >> I2S_CFGR_INV_BCLK_OUT_SHIFT) - -/* - * INV_BCLK_IN (RW) - * - * Invert the BCLK pad input before using it internally. Only valid in BCLK slave mode - */ -#define I2S_CFGR_INV_BCLK_IN_MASK (0x80000UL) -#define I2S_CFGR_INV_BCLK_IN_SHIFT (19U) -#define I2S_CFGR_INV_BCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_BCLK_IN_SHIFT) & I2S_CFGR_INV_BCLK_IN_MASK) -#define I2S_CFGR_INV_BCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_BCLK_IN_MASK) >> I2S_CFGR_INV_BCLK_IN_SHIFT) - -/* - * INV_FCLK_OUT (RW) - * - * Invert the FCLK before sending it out to pad. Only valid in FCLK master mode - */ -#define I2S_CFGR_INV_FCLK_OUT_MASK (0x40000UL) -#define I2S_CFGR_INV_FCLK_OUT_SHIFT (18U) -#define I2S_CFGR_INV_FCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_OUT_SHIFT) & I2S_CFGR_INV_FCLK_OUT_MASK) -#define I2S_CFGR_INV_FCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_OUT_MASK) >> I2S_CFGR_INV_FCLK_OUT_SHIFT) - -/* - * INV_FCLK_IN (RW) - * - * Invert the FCLK pad input before using it internally. Only valid in FCLK slave mode - */ -#define I2S_CFGR_INV_FCLK_IN_MASK (0x20000UL) -#define I2S_CFGR_INV_FCLK_IN_SHIFT (17U) -#define I2S_CFGR_INV_FCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_FCLK_IN_SHIFT) & I2S_CFGR_INV_FCLK_IN_MASK) -#define I2S_CFGR_INV_FCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_FCLK_IN_MASK) >> I2S_CFGR_INV_FCLK_IN_SHIFT) - -/* - * INV_MCLK_OUT (RW) - * - * Invert the MCLK before sending it out to pad. Only valid in MCLK master mode - */ -#define I2S_CFGR_INV_MCLK_OUT_MASK (0x10000UL) -#define I2S_CFGR_INV_MCLK_OUT_SHIFT (16U) -#define I2S_CFGR_INV_MCLK_OUT_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_OUT_SHIFT) & I2S_CFGR_INV_MCLK_OUT_MASK) -#define I2S_CFGR_INV_MCLK_OUT_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_OUT_MASK) >> I2S_CFGR_INV_MCLK_OUT_SHIFT) - -/* - * INV_MCLK_IN (RW) - * - * Invert the MCLK pad input before using it internally. Only valid in MCLK slave mode - */ -#define I2S_CFGR_INV_MCLK_IN_MASK (0x8000U) -#define I2S_CFGR_INV_MCLK_IN_SHIFT (15U) -#define I2S_CFGR_INV_MCLK_IN_SET(x) (((uint32_t)(x) << I2S_CFGR_INV_MCLK_IN_SHIFT) & I2S_CFGR_INV_MCLK_IN_MASK) -#define I2S_CFGR_INV_MCLK_IN_GET(x) (((uint32_t)(x) & I2S_CFGR_INV_MCLK_IN_MASK) >> I2S_CFGR_INV_MCLK_IN_SHIFT) - -/* - * BCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_BCLK_SEL_OP_MASK (0x4000U) -#define I2S_CFGR_BCLK_SEL_OP_SHIFT (14U) -#define I2S_CFGR_BCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_BCLK_SEL_OP_SHIFT) & I2S_CFGR_BCLK_SEL_OP_MASK) -#define I2S_CFGR_BCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_BCLK_SEL_OP_MASK) >> I2S_CFGR_BCLK_SEL_OP_SHIFT) - -/* - * FCLK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_FCLK_SEL_OP_MASK (0x2000U) -#define I2S_CFGR_FCLK_SEL_OP_SHIFT (13U) -#define I2S_CFGR_FCLK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_FCLK_SEL_OP_SHIFT) & I2S_CFGR_FCLK_SEL_OP_MASK) -#define I2S_CFGR_FCLK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_FCLK_SEL_OP_MASK) >> I2S_CFGR_FCLK_SEL_OP_SHIFT) - -/* - * MCK_SEL_OP (RW) - * - * asserted to use external clk source - */ -#define I2S_CFGR_MCK_SEL_OP_MASK (0x1000U) -#define I2S_CFGR_MCK_SEL_OP_SHIFT (12U) -#define I2S_CFGR_MCK_SEL_OP_SET(x) (((uint32_t)(x) << I2S_CFGR_MCK_SEL_OP_SHIFT) & I2S_CFGR_MCK_SEL_OP_MASK) -#define I2S_CFGR_MCK_SEL_OP_GET(x) (((uint32_t)(x) & I2S_CFGR_MCK_SEL_OP_MASK) >> I2S_CFGR_MCK_SEL_OP_SHIFT) - -/* - * FRAME_EDGE (RW) - * - * The start edge of a frame - * 0: Falling edge indicates a new frame (Just like standard I2S Philips standard) - * 1: Rising edge indicates a new frame - */ -#define I2S_CFGR_FRAME_EDGE_MASK (0x800U) -#define I2S_CFGR_FRAME_EDGE_SHIFT (11U) -#define I2S_CFGR_FRAME_EDGE_SET(x) (((uint32_t)(x) << I2S_CFGR_FRAME_EDGE_SHIFT) & I2S_CFGR_FRAME_EDGE_MASK) -#define I2S_CFGR_FRAME_EDGE_GET(x) (((uint32_t)(x) & I2S_CFGR_FRAME_EDGE_MASK) >> I2S_CFGR_FRAME_EDGE_SHIFT) - -/* - * CH_MAX (RW) - * - * CH_MAX[4:0] s the number of channels supported in TDM mode. When not in TDM mode, it must be set as 2. - * It must be an even number, so CH_MAX[0] is always 0. - * 5'h2: 2 channels - * 5'h4: 4 channels - * ... - * 5‘h10: 16 channels (max) - */ -#define I2S_CFGR_CH_MAX_MASK (0x7C0U) -#define I2S_CFGR_CH_MAX_SHIFT (6U) -#define I2S_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << I2S_CFGR_CH_MAX_SHIFT) & I2S_CFGR_CH_MAX_MASK) -#define I2S_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & I2S_CFGR_CH_MAX_MASK) >> I2S_CFGR_CH_MAX_SHIFT) - -/* - * TDM_EN (RW) - * - * TDM mode - * 0: not TDM mode - * 1: TDM mode - */ -#define I2S_CFGR_TDM_EN_MASK (0x20U) -#define I2S_CFGR_TDM_EN_SHIFT (5U) -#define I2S_CFGR_TDM_EN_SET(x) (((uint32_t)(x) << I2S_CFGR_TDM_EN_SHIFT) & I2S_CFGR_TDM_EN_MASK) -#define I2S_CFGR_TDM_EN_GET(x) (((uint32_t)(x) & I2S_CFGR_TDM_EN_MASK) >> I2S_CFGR_TDM_EN_SHIFT) - -/* - * STD (RW) - * - * I2S standard selection - * 00: I2S Philips standard. - * 01: MSB justified standard (left justified) - * 10: LSB justified standard (right justified) - * 11: PCM standard - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_STD_MASK (0x18U) -#define I2S_CFGR_STD_SHIFT (3U) -#define I2S_CFGR_STD_SET(x) (((uint32_t)(x) << I2S_CFGR_STD_SHIFT) & I2S_CFGR_STD_MASK) -#define I2S_CFGR_STD_GET(x) (((uint32_t)(x) & I2S_CFGR_STD_MASK) >> I2S_CFGR_STD_SHIFT) - -/* - * DATSIZ (RW) - * - * Data length to be transferred - * 00: 16-bit data length - * 01: 24-bit data length - * 10: 32-bit data length - * 11: Not allowed - * Note: For correct operation, these bits should be configured when the I2S is disabled. - */ -#define I2S_CFGR_DATSIZ_MASK (0x6U) -#define I2S_CFGR_DATSIZ_SHIFT (1U) -#define I2S_CFGR_DATSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_DATSIZ_SHIFT) & I2S_CFGR_DATSIZ_MASK) -#define I2S_CFGR_DATSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_DATSIZ_MASK) >> I2S_CFGR_DATSIZ_SHIFT) - -/* - * CHSIZ (RW) - * - * Channel length (number of bits per audio channel) - * 0: 16-bit wide - * 1: 32-bit wide - * The bit write operation has a meaning only if DATSIZ = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. - * Note: For correct operation, this bit should be configured when the I2S is disabled. - */ -#define I2S_CFGR_CHSIZ_MASK (0x1U) -#define I2S_CFGR_CHSIZ_SHIFT (0U) -#define I2S_CFGR_CHSIZ_SET(x) (((uint32_t)(x) << I2S_CFGR_CHSIZ_SHIFT) & I2S_CFGR_CHSIZ_MASK) -#define I2S_CFGR_CHSIZ_GET(x) (((uint32_t)(x) & I2S_CFGR_CHSIZ_MASK) >> I2S_CFGR_CHSIZ_SHIFT) - -/* Bitfield definition for register: MISC_CFGR */ -/* - * MCLK_GATEOFF (RW) - * - * Gate off the mclk. This mclk is the output of a glitch prone mux, so every time to switch the mclk, the gate off clock should be asserted at first. After the clock is switched, de-assert this bit to ungate off the mclk. - */ -#define I2S_MISC_CFGR_MCLK_GATEOFF_MASK (0x2000U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT (13U) -#define I2S_MISC_CFGR_MCLK_GATEOFF_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) -#define I2S_MISC_CFGR_MCLK_GATEOFF_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLK_GATEOFF_MASK) >> I2S_MISC_CFGR_MCLK_GATEOFF_SHIFT) - -/* - * MCLKOE (RW) - * - * Master clock output to pad enable - * 0: Master clock output is disabled - * 1: Master clock output is enabled - * Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master mode. - */ -#define I2S_MISC_CFGR_MCLKOE_MASK (0x1U) -#define I2S_MISC_CFGR_MCLKOE_SHIFT (0U) -#define I2S_MISC_CFGR_MCLKOE_SET(x) (((uint32_t)(x) << I2S_MISC_CFGR_MCLKOE_SHIFT) & I2S_MISC_CFGR_MCLKOE_MASK) -#define I2S_MISC_CFGR_MCLKOE_GET(x) (((uint32_t)(x) & I2S_MISC_CFGR_MCLKOE_MASK) >> I2S_MISC_CFGR_MCLKOE_SHIFT) - -/* Bitfield definition for register array: RXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_RXDSLOT_EN_MASK (0xFFFFU) -#define I2S_RXDSLOT_EN_SHIFT (0U) -#define I2S_RXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_RXDSLOT_EN_SHIFT) & I2S_RXDSLOT_EN_MASK) -#define I2S_RXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_RXDSLOT_EN_MASK) >> I2S_RXDSLOT_EN_SHIFT) - -/* Bitfield definition for register array: TXDSLOT */ -/* - * EN (RW) - * - */ -#define I2S_TXDSLOT_EN_MASK (0xFFFFU) -#define I2S_TXDSLOT_EN_SHIFT (0U) -#define I2S_TXDSLOT_EN_SET(x) (((uint32_t)(x) << I2S_TXDSLOT_EN_SHIFT) & I2S_TXDSLOT_EN_MASK) -#define I2S_TXDSLOT_EN_GET(x) (((uint32_t)(x) & I2S_TXDSLOT_EN_MASK) >> I2S_TXDSLOT_EN_SHIFT) - - - -/* RXD register group index macro definition */ -#define I2S_RXD_DATA0 (0UL) -#define I2S_RXD_DATA1 (1UL) -#define I2S_RXD_DATA2 (2UL) -#define I2S_RXD_DATA3 (3UL) - -/* TXD register group index macro definition */ -#define I2S_TXD_DATA0 (0UL) -#define I2S_TXD_DATA1 (1UL) -#define I2S_TXD_DATA2 (2UL) -#define I2S_TXD_DATA3 (3UL) - -/* RXDSLOT register group index macro definition */ -#define I2S_RXDSLOT_DATA0 (0UL) -#define I2S_RXDSLOT_DATA1 (1UL) -#define I2S_RXDSLOT_DATA2 (2UL) -#define I2S_RXDSLOT_DATA3 (3UL) - -/* TXDSLOT register group index macro definition */ -#define I2S_TXDSLOT_DATA0 (0UL) -#define I2S_TXDSLOT_DATA1 (1UL) -#define I2S_TXDSLOT_DATA2 (2UL) -#define I2S_TXDSLOT_DATA3 (3UL) - - -#endif /* HPM_I2S_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ioc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ioc_regs.h deleted file mode 100644 index 9a1f46ee39d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ioc_regs.h +++ /dev/null @@ -1,451 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_IOC_H -#define HPM_IOC_H - -typedef struct { - struct { - __RW uint32_t FUNC_CTL; /* 0x0: ALT SELECT */ - __RW uint32_t PAD_CTL; /* 0x4: PAD SETTINGS */ - } PAD[488]; -} IOC_Type; - - -/* Bitfield definition for register of struct array PAD: FUNC_CTL */ -/* - * LOOP_BACK (RW) - * - * force input on - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_LOOP_BACK_MASK (0x10000UL) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT (16U) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) -#define IOC_PAD_FUNC_CTL_LOOP_BACK_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_LOOP_BACK_MASK) >> IOC_PAD_FUNC_CTL_LOOP_BACK_SHIFT) - -/* - * ANALOG (RW) - * - * select analog pin in pad - * 0: disable - * 1: enable - */ -#define IOC_PAD_FUNC_CTL_ANALOG_MASK (0x100U) -#define IOC_PAD_FUNC_CTL_ANALOG_SHIFT (8U) -#define IOC_PAD_FUNC_CTL_ANALOG_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ANALOG_SHIFT) & IOC_PAD_FUNC_CTL_ANALOG_MASK) -#define IOC_PAD_FUNC_CTL_ANALOG_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ANALOG_MASK) >> IOC_PAD_FUNC_CTL_ANALOG_SHIFT) - -/* - * ALT_SELECT (RW) - * - * alt select - * 0: ALT0 - * 1: ALT1 - * ... - * 31:ALT31 - */ -#define IOC_PAD_FUNC_CTL_ALT_SELECT_MASK (0x1FU) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT (0U) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_SET(x) (((uint32_t)(x) << IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) -#define IOC_PAD_FUNC_CTL_ALT_SELECT_GET(x) (((uint32_t)(x) & IOC_PAD_FUNC_CTL_ALT_SELECT_MASK) >> IOC_PAD_FUNC_CTL_ALT_SELECT_SHIFT) - -/* Bitfield definition for register of struct array PAD: PAD_CTL */ -/* - * HYS (RW) - * - * schmitt trigger enable - * 0: disable - * 1: enable - */ -#define IOC_PAD_PAD_CTL_HYS_MASK (0x1000000UL) -#define IOC_PAD_PAD_CTL_HYS_SHIFT (24U) -#define IOC_PAD_PAD_CTL_HYS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_HYS_SHIFT) & IOC_PAD_PAD_CTL_HYS_MASK) -#define IOC_PAD_PAD_CTL_HYS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_HYS_MASK) >> IOC_PAD_PAD_CTL_HYS_SHIFT) - -/* - * PRS (RW) - * - * select pull up/down internal resistance strength: - * For pull down, only have 100 Kohm resistance - * For pull up: - * 00: 100 KOhm - * 01: 47 KOhm - * 10: 22 KOhm - * 11: 22 KOhm - */ -#define IOC_PAD_PAD_CTL_PRS_MASK (0x300000UL) -#define IOC_PAD_PAD_CTL_PRS_SHIFT (20U) -#define IOC_PAD_PAD_CTL_PRS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PRS_SHIFT) & IOC_PAD_PAD_CTL_PRS_MASK) -#define IOC_PAD_PAD_CTL_PRS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PRS_MASK) >> IOC_PAD_PAD_CTL_PRS_SHIFT) - -/* - * PS (RW) - * - * pull select - * 0: pull down - * 1: pull up - */ -#define IOC_PAD_PAD_CTL_PS_MASK (0x40000UL) -#define IOC_PAD_PAD_CTL_PS_SHIFT (18U) -#define IOC_PAD_PAD_CTL_PS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PS_SHIFT) & IOC_PAD_PAD_CTL_PS_MASK) -#define IOC_PAD_PAD_CTL_PS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PS_MASK) >> IOC_PAD_PAD_CTL_PS_SHIFT) - -/* - * PE (RW) - * - * pull enable - * 0: pull disable - * 1: pull enable - */ -#define IOC_PAD_PAD_CTL_PE_MASK (0x20000UL) -#define IOC_PAD_PAD_CTL_PE_SHIFT (17U) -#define IOC_PAD_PAD_CTL_PE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_PE_SHIFT) & IOC_PAD_PAD_CTL_PE_MASK) -#define IOC_PAD_PAD_CTL_PE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_PE_MASK) >> IOC_PAD_PAD_CTL_PE_SHIFT) - -/* - * KE (RW) - * - * keeper capability enable - * 0: keeper disable - * 1: keeper enable - */ -#define IOC_PAD_PAD_CTL_KE_MASK (0x10000UL) -#define IOC_PAD_PAD_CTL_KE_SHIFT (16U) -#define IOC_PAD_PAD_CTL_KE_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_KE_SHIFT) & IOC_PAD_PAD_CTL_KE_MASK) -#define IOC_PAD_PAD_CTL_KE_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_KE_MASK) >> IOC_PAD_PAD_CTL_KE_SHIFT) - -/* - * OD (RW) - * - * open drain - * 0: open drain disable - * 1: open drain enable - */ -#define IOC_PAD_PAD_CTL_OD_MASK (0x100U) -#define IOC_PAD_PAD_CTL_OD_SHIFT (8U) -#define IOC_PAD_PAD_CTL_OD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_OD_SHIFT) & IOC_PAD_PAD_CTL_OD_MASK) -#define IOC_PAD_PAD_CTL_OD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_OD_MASK) >> IOC_PAD_PAD_CTL_OD_SHIFT) - -/* - * SR (RW) - * - * slew rate - * 0: Slow slew rate - * 1: Fast slew rate - */ -#define IOC_PAD_PAD_CTL_SR_MASK (0x40U) -#define IOC_PAD_PAD_CTL_SR_SHIFT (6U) -#define IOC_PAD_PAD_CTL_SR_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SR_SHIFT) & IOC_PAD_PAD_CTL_SR_MASK) -#define IOC_PAD_PAD_CTL_SR_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SR_MASK) >> IOC_PAD_PAD_CTL_SR_SHIFT) - -/* - * SPD (RW) - * - * additional 2-bit slew rate to select IO cell operation frequency range with reduced switching noise - * 00: Slow frequency slew rate(50Mhz) - * 01: Medium frequency slew rate(100 Mhz) - * 10: Fast frequency slew rate(150 Mhz) - * 11: Max frequency slew rate(200Mhz) - */ -#define IOC_PAD_PAD_CTL_SPD_MASK (0x30U) -#define IOC_PAD_PAD_CTL_SPD_SHIFT (4U) -#define IOC_PAD_PAD_CTL_SPD_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_SPD_SHIFT) & IOC_PAD_PAD_CTL_SPD_MASK) -#define IOC_PAD_PAD_CTL_SPD_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_SPD_MASK) >> IOC_PAD_PAD_CTL_SPD_SHIFT) - -/* - * DS (RW) - * - * drive strength - * 1.8V Mode: - * 000: 260 Ohm - * 001: 260 Ohm - * 010: 130 Ohm - * 011: 88 Ohm - * 100: 65 Ohm - * 101: 52 Ohm - * 110: 43 Ohm - * 111: 37 Ohm - * 3.3V Mode: - * 000: 157 Ohm - * 001: 157 Ohm - * 010: 78 Ohm - * 011: 53 Ohm - * 100: 39 Ohm - * 101: 32 Ohm - * 110: 26 Ohm - * 111: 23 Ohm - */ -#define IOC_PAD_PAD_CTL_DS_MASK (0x7U) -#define IOC_PAD_PAD_CTL_DS_SHIFT (0U) -#define IOC_PAD_PAD_CTL_DS_SET(x) (((uint32_t)(x) << IOC_PAD_PAD_CTL_DS_SHIFT) & IOC_PAD_PAD_CTL_DS_MASK) -#define IOC_PAD_PAD_CTL_DS_GET(x) (((uint32_t)(x) & IOC_PAD_PAD_CTL_DS_MASK) >> IOC_PAD_PAD_CTL_DS_SHIFT) - - - -/* PAD register group index macro definition */ -#define IOC_PAD_PA00 (0UL) -#define IOC_PAD_PA01 (1UL) -#define IOC_PAD_PA02 (2UL) -#define IOC_PAD_PA03 (3UL) -#define IOC_PAD_PA04 (4UL) -#define IOC_PAD_PA05 (5UL) -#define IOC_PAD_PA06 (6UL) -#define IOC_PAD_PA07 (7UL) -#define IOC_PAD_PA08 (8UL) -#define IOC_PAD_PA09 (9UL) -#define IOC_PAD_PA10 (10UL) -#define IOC_PAD_PA11 (11UL) -#define IOC_PAD_PA12 (12UL) -#define IOC_PAD_PA13 (13UL) -#define IOC_PAD_PA14 (14UL) -#define IOC_PAD_PA15 (15UL) -#define IOC_PAD_PA16 (16UL) -#define IOC_PAD_PA17 (17UL) -#define IOC_PAD_PA18 (18UL) -#define IOC_PAD_PA19 (19UL) -#define IOC_PAD_PA20 (20UL) -#define IOC_PAD_PA21 (21UL) -#define IOC_PAD_PA22 (22UL) -#define IOC_PAD_PA23 (23UL) -#define IOC_PAD_PA24 (24UL) -#define IOC_PAD_PA25 (25UL) -#define IOC_PAD_PA26 (26UL) -#define IOC_PAD_PA27 (27UL) -#define IOC_PAD_PA28 (28UL) -#define IOC_PAD_PA29 (29UL) -#define IOC_PAD_PA30 (30UL) -#define IOC_PAD_PA31 (31UL) -#define IOC_PAD_PB00 (32UL) -#define IOC_PAD_PB01 (33UL) -#define IOC_PAD_PB02 (34UL) -#define IOC_PAD_PB03 (35UL) -#define IOC_PAD_PB04 (36UL) -#define IOC_PAD_PB05 (37UL) -#define IOC_PAD_PB06 (38UL) -#define IOC_PAD_PB07 (39UL) -#define IOC_PAD_PB08 (40UL) -#define IOC_PAD_PB09 (41UL) -#define IOC_PAD_PB10 (42UL) -#define IOC_PAD_PB11 (43UL) -#define IOC_PAD_PB12 (44UL) -#define IOC_PAD_PB13 (45UL) -#define IOC_PAD_PB14 (46UL) -#define IOC_PAD_PB15 (47UL) -#define IOC_PAD_PB16 (48UL) -#define IOC_PAD_PB17 (49UL) -#define IOC_PAD_PB18 (50UL) -#define IOC_PAD_PB19 (51UL) -#define IOC_PAD_PB20 (52UL) -#define IOC_PAD_PB21 (53UL) -#define IOC_PAD_PB22 (54UL) -#define IOC_PAD_PB23 (55UL) -#define IOC_PAD_PB24 (56UL) -#define IOC_PAD_PB25 (57UL) -#define IOC_PAD_PB26 (58UL) -#define IOC_PAD_PB27 (59UL) -#define IOC_PAD_PB28 (60UL) -#define IOC_PAD_PB29 (61UL) -#define IOC_PAD_PB30 (62UL) -#define IOC_PAD_PB31 (63UL) -#define IOC_PAD_PC00 (64UL) -#define IOC_PAD_PC01 (65UL) -#define IOC_PAD_PC02 (66UL) -#define IOC_PAD_PC03 (67UL) -#define IOC_PAD_PC04 (68UL) -#define IOC_PAD_PC05 (69UL) -#define IOC_PAD_PC06 (70UL) -#define IOC_PAD_PC07 (71UL) -#define IOC_PAD_PC08 (72UL) -#define IOC_PAD_PC09 (73UL) -#define IOC_PAD_PC10 (74UL) -#define IOC_PAD_PC11 (75UL) -#define IOC_PAD_PC12 (76UL) -#define IOC_PAD_PC13 (77UL) -#define IOC_PAD_PC14 (78UL) -#define IOC_PAD_PC15 (79UL) -#define IOC_PAD_PC16 (80UL) -#define IOC_PAD_PC17 (81UL) -#define IOC_PAD_PC18 (82UL) -#define IOC_PAD_PC19 (83UL) -#define IOC_PAD_PC20 (84UL) -#define IOC_PAD_PC21 (85UL) -#define IOC_PAD_PC22 (86UL) -#define IOC_PAD_PC23 (87UL) -#define IOC_PAD_PC24 (88UL) -#define IOC_PAD_PC25 (89UL) -#define IOC_PAD_PC26 (90UL) -#define IOC_PAD_PC27 (91UL) -#define IOC_PAD_PC28 (92UL) -#define IOC_PAD_PC29 (93UL) -#define IOC_PAD_PC30 (94UL) -#define IOC_PAD_PC31 (95UL) -#define IOC_PAD_PD00 (96UL) -#define IOC_PAD_PD01 (97UL) -#define IOC_PAD_PD02 (98UL) -#define IOC_PAD_PD03 (99UL) -#define IOC_PAD_PD04 (100UL) -#define IOC_PAD_PD05 (101UL) -#define IOC_PAD_PD06 (102UL) -#define IOC_PAD_PD07 (103UL) -#define IOC_PAD_PD08 (104UL) -#define IOC_PAD_PD09 (105UL) -#define IOC_PAD_PD10 (106UL) -#define IOC_PAD_PD11 (107UL) -#define IOC_PAD_PD12 (108UL) -#define IOC_PAD_PD13 (109UL) -#define IOC_PAD_PD14 (110UL) -#define IOC_PAD_PD15 (111UL) -#define IOC_PAD_PD16 (112UL) -#define IOC_PAD_PD17 (113UL) -#define IOC_PAD_PD18 (114UL) -#define IOC_PAD_PD19 (115UL) -#define IOC_PAD_PD20 (116UL) -#define IOC_PAD_PD21 (117UL) -#define IOC_PAD_PD22 (118UL) -#define IOC_PAD_PD23 (119UL) -#define IOC_PAD_PD24 (120UL) -#define IOC_PAD_PD25 (121UL) -#define IOC_PAD_PD26 (122UL) -#define IOC_PAD_PD27 (123UL) -#define IOC_PAD_PD28 (124UL) -#define IOC_PAD_PD29 (125UL) -#define IOC_PAD_PD30 (126UL) -#define IOC_PAD_PD31 (127UL) -#define IOC_PAD_PE00 (128UL) -#define IOC_PAD_PE01 (129UL) -#define IOC_PAD_PE02 (130UL) -#define IOC_PAD_PE03 (131UL) -#define IOC_PAD_PE04 (132UL) -#define IOC_PAD_PE05 (133UL) -#define IOC_PAD_PE06 (134UL) -#define IOC_PAD_PE07 (135UL) -#define IOC_PAD_PE08 (136UL) -#define IOC_PAD_PE09 (137UL) -#define IOC_PAD_PE10 (138UL) -#define IOC_PAD_PE11 (139UL) -#define IOC_PAD_PE12 (140UL) -#define IOC_PAD_PE13 (141UL) -#define IOC_PAD_PE14 (142UL) -#define IOC_PAD_PE15 (143UL) -#define IOC_PAD_PE16 (144UL) -#define IOC_PAD_PE17 (145UL) -#define IOC_PAD_PE18 (146UL) -#define IOC_PAD_PE19 (147UL) -#define IOC_PAD_PE20 (148UL) -#define IOC_PAD_PE21 (149UL) -#define IOC_PAD_PE22 (150UL) -#define IOC_PAD_PE23 (151UL) -#define IOC_PAD_PE24 (152UL) -#define IOC_PAD_PE25 (153UL) -#define IOC_PAD_PE26 (154UL) -#define IOC_PAD_PE27 (155UL) -#define IOC_PAD_PE28 (156UL) -#define IOC_PAD_PE29 (157UL) -#define IOC_PAD_PE30 (158UL) -#define IOC_PAD_PE31 (159UL) -#define IOC_PAD_PF00 (160UL) -#define IOC_PAD_PF01 (161UL) -#define IOC_PAD_PF02 (162UL) -#define IOC_PAD_PF03 (163UL) -#define IOC_PAD_PF04 (164UL) -#define IOC_PAD_PF05 (165UL) -#define IOC_PAD_PF06 (166UL) -#define IOC_PAD_PF07 (167UL) -#define IOC_PAD_PF08 (168UL) -#define IOC_PAD_PF09 (169UL) -#define IOC_PAD_PF10 (170UL) -#define IOC_PAD_PF11 (171UL) -#define IOC_PAD_PF12 (172UL) -#define IOC_PAD_PF13 (173UL) -#define IOC_PAD_PF14 (174UL) -#define IOC_PAD_PF15 (175UL) -#define IOC_PAD_PF16 (176UL) -#define IOC_PAD_PF17 (177UL) -#define IOC_PAD_PF18 (178UL) -#define IOC_PAD_PF19 (179UL) -#define IOC_PAD_PF20 (180UL) -#define IOC_PAD_PF21 (181UL) -#define IOC_PAD_PF22 (182UL) -#define IOC_PAD_PF23 (183UL) -#define IOC_PAD_PF24 (184UL) -#define IOC_PAD_PF25 (185UL) -#define IOC_PAD_PF26 (186UL) -#define IOC_PAD_PF27 (187UL) -#define IOC_PAD_PF28 (188UL) -#define IOC_PAD_PF29 (189UL) -#define IOC_PAD_PF30 (190UL) -#define IOC_PAD_PF31 (191UL) -#define IOC_PAD_PV00 (352UL) -#define IOC_PAD_PV01 (353UL) -#define IOC_PAD_PV02 (354UL) -#define IOC_PAD_PV03 (355UL) -#define IOC_PAD_PV04 (356UL) -#define IOC_PAD_PV05 (357UL) -#define IOC_PAD_PV06 (358UL) -#define IOC_PAD_PV07 (359UL) -#define IOC_PAD_PV08 (360UL) -#define IOC_PAD_PV09 (361UL) -#define IOC_PAD_PV10 (362UL) -#define IOC_PAD_PV11 (363UL) -#define IOC_PAD_PV12 (364UL) -#define IOC_PAD_PV13 (365UL) -#define IOC_PAD_PV14 (366UL) -#define IOC_PAD_PV15 (367UL) -#define IOC_PAD_PW00 (384UL) -#define IOC_PAD_PW01 (385UL) -#define IOC_PAD_PW02 (386UL) -#define IOC_PAD_PW03 (387UL) -#define IOC_PAD_PW04 (388UL) -#define IOC_PAD_PW05 (389UL) -#define IOC_PAD_PW06 (390UL) -#define IOC_PAD_PW07 (391UL) -#define IOC_PAD_PW08 (392UL) -#define IOC_PAD_PW09 (393UL) -#define IOC_PAD_PW10 (394UL) -#define IOC_PAD_PW11 (395UL) -#define IOC_PAD_PW12 (396UL) -#define IOC_PAD_PW13 (397UL) -#define IOC_PAD_PW14 (398UL) -#define IOC_PAD_PW15 (399UL) -#define IOC_PAD_PW16 (400UL) -#define IOC_PAD_PW17 (401UL) -#define IOC_PAD_PW18 (402UL) -#define IOC_PAD_PW19 (403UL) -#define IOC_PAD_PW20 (404UL) -#define IOC_PAD_PW21 (405UL) -#define IOC_PAD_PW22 (406UL) -#define IOC_PAD_PW23 (407UL) -#define IOC_PAD_PX00 (416UL) -#define IOC_PAD_PX01 (417UL) -#define IOC_PAD_PX02 (418UL) -#define IOC_PAD_PX03 (419UL) -#define IOC_PAD_PX04 (420UL) -#define IOC_PAD_PX05 (421UL) -#define IOC_PAD_PX06 (422UL) -#define IOC_PAD_PX07 (423UL) -#define IOC_PAD_PY00 (448UL) -#define IOC_PAD_PY01 (449UL) -#define IOC_PAD_PY02 (450UL) -#define IOC_PAD_PY03 (451UL) -#define IOC_PAD_PY04 (452UL) -#define IOC_PAD_PY05 (453UL) -#define IOC_PAD_PY06 (454UL) -#define IOC_PAD_PY07 (455UL) -#define IOC_PAD_PZ00 (480UL) -#define IOC_PAD_PZ01 (481UL) -#define IOC_PAD_PZ02 (482UL) -#define IOC_PAD_PZ03 (483UL) -#define IOC_PAD_PZ04 (484UL) -#define IOC_PAD_PZ05 (485UL) -#define IOC_PAD_PZ06 (486UL) -#define IOC_PAD_PZ07 (487UL) - - -#endif /* HPM_IOC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_keym_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_keym_regs.h deleted file mode 100644 index 0d97ce1ecb5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_keym_regs.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_KEYM_H -#define HPM_KEYM_H - -typedef struct { - __RW uint32_t SOFTMKEY[8]; /* 0x0 - 0x1C: software set symmetric key */ - __RW uint32_t SOFTPKEY[8]; /* 0x20 - 0x3C: system asymmetric key */ - __RW uint32_t SEC_KEY_CTL; /* 0x40: secure key generation */ - __RW uint32_t NSC_KEY_CTL; /* 0x44: non-secure key generation */ - __RW uint32_t RNG; /* 0x48: Random number interface behavior */ - __RW uint32_t READ_CONTROL; /* 0x4C: key read out control */ -} KEYM_Type; - - -/* Bitfield definition for register array: SOFTMKEY */ -/* - * KEY (RW) - * - * software symmetric key - * key will be scambled to 4 variants for software to use, and replicable on same chip. - * scramble keys are chip different, and not replicable on different chip - * must be write sequencely from 0 - 7, otherwise key value will be treated as all 0 - */ -#define KEYM_SOFTMKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTMKEY_KEY_SHIFT (0U) -#define KEYM_SOFTMKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTMKEY_KEY_SHIFT) & KEYM_SOFTMKEY_KEY_MASK) -#define KEYM_SOFTMKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTMKEY_KEY_MASK) >> KEYM_SOFTMKEY_KEY_SHIFT) - -/* Bitfield definition for register array: SOFTPKEY */ -/* - * KEY (RW) - * - * software asymmetric key - * key is derived from scrambles of fuse private key, software input key, SRK, and system security status. - * This key os read once, sencondary read will read out 0 - */ -#define KEYM_SOFTPKEY_KEY_MASK (0xFFFFFFFFUL) -#define KEYM_SOFTPKEY_KEY_SHIFT (0U) -#define KEYM_SOFTPKEY_KEY_SET(x) (((uint32_t)(x) << KEYM_SOFTPKEY_KEY_SHIFT) & KEYM_SOFTPKEY_KEY_MASK) -#define KEYM_SOFTPKEY_KEY_GET(x) (((uint32_t)(x) & KEYM_SOFTPKEY_KEY_MASK) >> KEYM_SOFTPKEY_KEY_SHIFT) - -/* Bitfield definition for register: SEC_KEY_CTL */ -/* - * LOCK_SEC_CTL (RW) - * - * block secure state key setting being changed - */ -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK (0x80000000UL) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT (31U) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) -#define KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_MASK) >> KEYM_SEC_KEY_CTL_LOCK_SEC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_SEC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_SEC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_SEC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SK_VAL_MASK) >> KEYM_SEC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use origin value in software symmetric key - * 1: use scramble version of software symmetric key - */ -#define KEYM_SEC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_SEC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_SMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_SEC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use alnertave scramble of fuse symmetric key - */ -#define KEYM_SEC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_SEC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_SEC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_FMK_SEL_MASK) >> KEYM_SEC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_SEC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_SEC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_SEC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_SEC_KEY_CTL_KEY_SEL_MASK) >> KEYM_SEC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: NSC_KEY_CTL */ -/* - * LOCK_NSC_CTL (RW) - * - * block non-secure state key setting being changed - */ -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK (0x80000000UL) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT (31U) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) -#define KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_MASK) >> KEYM_NSC_KEY_CTL_LOCK_NSC_CTL_SHIFT) - -/* - * SK_VAL (RO) - * - * session key valid - * 0: session key is all 0's and not usable - * 1: session key is valid - */ -#define KEYM_NSC_KEY_CTL_SK_VAL_MASK (0x10000UL) -#define KEYM_NSC_KEY_CTL_SK_VAL_SHIFT (16U) -#define KEYM_NSC_KEY_CTL_SK_VAL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SK_VAL_MASK) >> KEYM_NSC_KEY_CTL_SK_VAL_SHIFT) - -/* - * SMK_SEL (RW) - * - * software symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_SMK_SEL_MASK (0x1000U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT (12U) -#define KEYM_NSC_KEY_CTL_SMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_SMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_SMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_SMK_SEL_SHIFT) - -/* - * ZMK_SEL (RW) - * - * batt symmetric key selection - * 0: use scramble version of software symmetric key - * 1: use origin value in software symmetric key - */ -#define KEYM_NSC_KEY_CTL_ZMK_SEL_MASK (0x100U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT (8U) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_ZMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_ZMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_ZMK_SEL_SHIFT) - -/* - * FMK_SEL (RW) - * - * fuse symmetric key selection - * 0: use scramble version of fuse symmetric key - * 1: use origin value in fuse symmetric key - */ -#define KEYM_NSC_KEY_CTL_FMK_SEL_MASK (0x10U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT (4U) -#define KEYM_NSC_KEY_CTL_FMK_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) -#define KEYM_NSC_KEY_CTL_FMK_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_FMK_SEL_MASK) >> KEYM_NSC_KEY_CTL_FMK_SEL_SHIFT) - -/* - * KEY_SEL (RW) - * - * non-secure symmtric key synthesize setting, key is a XOR of following - * bit0: fuse mk, 0: not selected, 1:selected - * bit1: zmk from batt, 0: not selected, 1:selected - * bit2: software key 0: not selected, 1:selected - */ -#define KEYM_NSC_KEY_CTL_KEY_SEL_MASK (0x7U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT (0U) -#define KEYM_NSC_KEY_CTL_KEY_SEL_SET(x) (((uint32_t)(x) << KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) -#define KEYM_NSC_KEY_CTL_KEY_SEL_GET(x) (((uint32_t)(x) & KEYM_NSC_KEY_CTL_KEY_SEL_MASK) >> KEYM_NSC_KEY_CTL_KEY_SEL_SHIFT) - -/* Bitfield definition for register: RNG */ -/* - * BLOCK_RNG_XOR (RW) - * - * block RNG_XOR bit from changing, if this bit is written to 1, it will hold 1 until next reset - * 0: RNG_XOR can be changed by software - * 1: RNG_XOR ignore software change from software - */ -#define KEYM_RNG_BLOCK_RNG_XOR_MASK (0x10000UL) -#define KEYM_RNG_BLOCK_RNG_XOR_SHIFT (16U) -#define KEYM_RNG_BLOCK_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_BLOCK_RNG_XOR_SHIFT) & KEYM_RNG_BLOCK_RNG_XOR_MASK) -#define KEYM_RNG_BLOCK_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_BLOCK_RNG_XOR_MASK) >> KEYM_RNG_BLOCK_RNG_XOR_SHIFT) - -/* - * RNG_XOR (RW) - * - * control how SFK is accepted from random number generator - * 0: SFK value replaced by random number input - * 1: SFK value exclusive or with random number input,this help generate random number using 2 rings inside RNG - */ -#define KEYM_RNG_RNG_XOR_MASK (0x1U) -#define KEYM_RNG_RNG_XOR_SHIFT (0U) -#define KEYM_RNG_RNG_XOR_SET(x) (((uint32_t)(x) << KEYM_RNG_RNG_XOR_SHIFT) & KEYM_RNG_RNG_XOR_MASK) -#define KEYM_RNG_RNG_XOR_GET(x) (((uint32_t)(x) & KEYM_RNG_RNG_XOR_MASK) >> KEYM_RNG_RNG_XOR_SHIFT) - -/* Bitfield definition for register: READ_CONTROL */ -/* - * BLOCK_PK_READ (RW) - * - * asymmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_PK_READ_MASK (0x10000UL) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT (16U) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_PK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_PK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_PK_READ_SHIFT) - -/* - * BLOCK_SMK_READ (RW) - * - * symmetric key readout control, if this bit is written to 1, it will hold 1 until next reset - * 0: key can be read out - * 1: key cannot be read out - */ -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK (0x1U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT (0U) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_SET(x) (((uint32_t)(x) << KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) -#define KEYM_READ_CONTROL_BLOCK_SMK_READ_GET(x) (((uint32_t)(x) & KEYM_READ_CONTROL_BLOCK_SMK_READ_MASK) >> KEYM_READ_CONTROL_BLOCK_SMK_READ_SHIFT) - - - -/* SOFTMKEY register group index macro definition */ -#define KEYM_SOFTMKEY_SFK0 (0UL) -#define KEYM_SOFTMKEY_SFK1 (1UL) -#define KEYM_SOFTMKEY_SFK2 (2UL) -#define KEYM_SOFTMKEY_SFK3 (3UL) -#define KEYM_SOFTMKEY_SFK4 (4UL) -#define KEYM_SOFTMKEY_SFK5 (5UL) -#define KEYM_SOFTMKEY_SFK6 (6UL) -#define KEYM_SOFTMKEY_SFK7 (7UL) - -/* SOFTPKEY register group index macro definition */ -#define KEYM_SOFTPKEY_SPK0 (0UL) -#define KEYM_SOFTPKEY_SPK1 (1UL) -#define KEYM_SOFTPKEY_SPK2 (2UL) -#define KEYM_SOFTPKEY_SPK3 (3UL) -#define KEYM_SOFTPKEY_SPK4 (4UL) -#define KEYM_SOFTPKEY_SPK5 (5UL) -#define KEYM_SOFTPKEY_SPK6 (6UL) -#define KEYM_SOFTPKEY_SPK7 (7UL) - - -#endif /* HPM_KEYM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_lobs_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_lobs_regs.h deleted file mode 100644 index 719dcd66da1..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_lobs_regs.h +++ /dev/null @@ -1,622 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_LOBS_H -#define HPM_LOBS_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __R uint8_t RESERVED0[8]; /* 0x4 - 0xB: Reserved */ - __RW uint32_t STREAMCTRL; /* 0xC: Stream Control Register */ - __RW uint32_t PTACTION; /* 0x10: Pre-trigger Action Register */ - __RW uint32_t STARTADDR; /* 0x14: Start Address Register */ - __RW uint32_t ENDADDR; /* 0x18: End Address Register */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - __R uint32_t CTSR; /* 0x20: Current Trigger State Register */ - __R uint32_t CCVR; /* 0x24: Current Counter Value Register */ - __R uint32_t CAVR; /* 0x28: Current Action Value Register */ - __R uint8_t RESERVED2[4]; /* 0x2C - 0x2F: Reserved */ - __R uint32_t FIFOSTATE; /* 0x30: Fifo State Register */ - __RW uint32_t FINALADDR; /* 0x34: Final Address Register */ - __R uint8_t RESERVED3[24]; /* 0x38 - 0x4F: Reserved */ - __RW uint32_t GRPSELA; /* 0x50: Group Select Register */ - __RW uint32_t GRPENA; /* 0x54: Group Enable Register */ - __RW uint32_t SIGSELA1; /* 0x58: Signal Select1 Register */ - __R uint8_t RESERVED4[4]; /* 0x5C - 0x5F: Reserved */ - __RW uint32_t SIGSELA2; /* 0x60: Signal Select2 Register */ - __R uint8_t RESERVED5[52]; /* 0x64 - 0x97: Reserved */ - __RW uint32_t SIGENA; /* 0x98: Signal Enable Register */ - __R uint8_t RESERVED6[100]; /* 0x9C - 0xFF: Reserved */ - struct { - __RW uint32_t SIGSEL; /* 0x100: Signal Select Register */ - __RW uint32_t TRIGCTRL; /* 0x104: Trigger Control Register */ - __RW uint32_t NEXTSTATE; /* 0x108: Next State Register */ - __RW uint32_t ACTION; /* 0x10C: Action Register */ - __R uint8_t RESERVED0[16]; /* 0x110 - 0x11F: Reserved */ - __RW uint32_t COUNTCOMP; /* 0x120: Counter Compare Register */ - __R uint8_t RESERVED1[12]; /* 0x124 - 0x12F: Reserved */ - __RW uint32_t EXTMASK; /* 0x130: External Mask Register */ - __RW uint32_t EXTCOMP; /* 0x134: External Compare Register */ - __R uint8_t RESERVED2[8]; /* 0x138 - 0x13F: Reserved */ - __RW uint32_t SIGMASK; /* 0x140: Signal Mask Register */ - __RW uint32_t COMPEN; /* 0x144: Compare Enable register */ - __R uint8_t RESERVED3[56]; /* 0x148 - 0x17F: Reserved */ - __RW uint32_t SIGCOMP0; /* 0x180: Signal Compare Register0 */ - __RW uint32_t SIGCOMP1; /* 0x184: Signal Compare Register1 */ - __RW uint32_t SIGCOMP2; /* 0x188: Signal Compare Register2 */ - __RW uint32_t SIGCOMP3; /* 0x18C: Signal Compare Register3 */ - __R uint8_t RESERVED4[112]; /* 0x190 - 0x1FF: Reserved */ - } STATE[5]; - __R uint8_t RESERVED7[2480]; /* 0x600 - 0xFAF: Reserved */ - __RW uint32_t LAR; /* 0xFB0: Lock Access Register */ -} LOBS_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * RUN (RW) - * - * Run control. - * 0 LOBS disabled. Register programming permitted. - * 1 LOBS enabled - */ -#define LOBS_CTRL_RUN_MASK (0x1U) -#define LOBS_CTRL_RUN_SHIFT (0U) -#define LOBS_CTRL_RUN_SET(x) (((uint32_t)(x) << LOBS_CTRL_RUN_SHIFT) & LOBS_CTRL_RUN_MASK) -#define LOBS_CTRL_RUN_GET(x) (((uint32_t)(x) & LOBS_CTRL_RUN_MASK) >> LOBS_CTRL_RUN_SHIFT) - -/* Bitfield definition for register: STREAMCTRL */ -/* - * SEL (RW) - * - * Signal Group Select - * 0 128bit from one group - * 1 from 2 groups, 4bit in each group - */ -#define LOBS_STREAMCTRL_SEL_MASK (0x100U) -#define LOBS_STREAMCTRL_SEL_SHIFT (8U) -#define LOBS_STREAMCTRL_SEL_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SEL_SHIFT) & LOBS_STREAMCTRL_SEL_MASK) -#define LOBS_STREAMCTRL_SEL_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SEL_MASK) >> LOBS_STREAMCTRL_SEL_SHIFT) - -/* - * FULL_CLEAR (RW) - * - * FIFO Overflow Clear - */ -#define LOBS_STREAMCTRL_FULL_CLEAR_MASK (0x80U) -#define LOBS_STREAMCTRL_FULL_CLEAR_SHIFT (7U) -#define LOBS_STREAMCTRL_FULL_CLEAR_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_FULL_CLEAR_SHIFT) & LOBS_STREAMCTRL_FULL_CLEAR_MASK) -#define LOBS_STREAMCTRL_FULL_CLEAR_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_FULL_CLEAR_MASK) >> LOBS_STREAMCTRL_FULL_CLEAR_SHIFT) - -/* - * SAMPLE (RW) - * - * Sample Rate - * 4 take one every 5 - * 5 take one every 6 - * 6 take one every 7 - */ -#define LOBS_STREAMCTRL_SAMPLE_MASK (0x78U) -#define LOBS_STREAMCTRL_SAMPLE_SHIFT (3U) -#define LOBS_STREAMCTRL_SAMPLE_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SAMPLE_SHIFT) & LOBS_STREAMCTRL_SAMPLE_MASK) -#define LOBS_STREAMCTRL_SAMPLE_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SAMPLE_MASK) >> LOBS_STREAMCTRL_SAMPLE_SHIFT) - -/* - * BURST (RW) - * - * Burst Cfg - * 3b011 Incr4 - * 3b101 Incr8 - * 3b111 Incr16 - */ -#define LOBS_STREAMCTRL_BURST_MASK (0x7U) -#define LOBS_STREAMCTRL_BURST_SHIFT (0U) -#define LOBS_STREAMCTRL_BURST_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_BURST_SHIFT) & LOBS_STREAMCTRL_BURST_MASK) -#define LOBS_STREAMCTRL_BURST_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_BURST_MASK) >> LOBS_STREAMCTRL_BURST_SHIFT) - -/* Bitfield definition for register: PTACTION */ -/* - * TRACE (RW) - * - * Enables trace - */ -#define LOBS_PTACTION_TRACE_MASK (0x8U) -#define LOBS_PTACTION_TRACE_SHIFT (3U) -#define LOBS_PTACTION_TRACE_SET(x) (((uint32_t)(x) << LOBS_PTACTION_TRACE_SHIFT) & LOBS_PTACTION_TRACE_MASK) -#define LOBS_PTACTION_TRACE_GET(x) (((uint32_t)(x) & LOBS_PTACTION_TRACE_MASK) >> LOBS_PTACTION_TRACE_SHIFT) - -/* Bitfield definition for register: STARTADDR */ -/* - * ADDR (RW) - * - * Start address - */ -#define LOBS_STARTADDR_ADDR_MASK (0xFFFFFFFFUL) -#define LOBS_STARTADDR_ADDR_SHIFT (0U) -#define LOBS_STARTADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_STARTADDR_ADDR_SHIFT) & LOBS_STARTADDR_ADDR_MASK) -#define LOBS_STARTADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_STARTADDR_ADDR_MASK) >> LOBS_STARTADDR_ADDR_SHIFT) - -/* Bitfield definition for register: ENDADDR */ -/* - * ADDR (RW) - * - * End address - */ -#define LOBS_ENDADDR_ADDR_MASK (0xFFFFFFFFUL) -#define LOBS_ENDADDR_ADDR_SHIFT (0U) -#define LOBS_ENDADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_ENDADDR_ADDR_SHIFT) & LOBS_ENDADDR_ADDR_MASK) -#define LOBS_ENDADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_ENDADDR_ADDR_MASK) >> LOBS_ENDADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CTSR */ -/* - * FINALSTATE (RO) - * - * 0 LOBS is still tracing. - * 1 Indicates that the LOBS has stopped advancing Trigger States and stopped trace. - * FINALSTATE can be set by TRIGCTRL.COUNTBRK reaching the final loop count, or by programming NEXTSTATEto zero - */ -#define LOBS_CTSR_FINALSTATE_MASK (0x80000000UL) -#define LOBS_CTSR_FINALSTATE_SHIFT (31U) -#define LOBS_CTSR_FINALSTATE_GET(x) (((uint32_t)(x) & LOBS_CTSR_FINALSTATE_MASK) >> LOBS_CTSR_FINALSTATE_SHIFT) - -/* - * CTSR (RO) - * - * Reads current Trigger State. This is a one-hot encoded field. - * When CTRL.RUN: - * 0 RAZ. - * 1 Returns current Trigger State. - * If FINALSTATE is 1, then the CTSR field gives the Trigger State when FINALSTATE became 1 - */ -#define LOBS_CTSR_CTSR_MASK (0x1FU) -#define LOBS_CTSR_CTSR_SHIFT (0U) -#define LOBS_CTSR_CTSR_GET(x) (((uint32_t)(x) & LOBS_CTSR_CTSR_MASK) >> LOBS_CTSR_CTSR_SHIFT) - -/* Bitfield definition for register: CCVR */ -/* - * CCVR (RO) - * - * Returns the counter value when the CTSR was last read. If the CTSR has never been read, then the value in the CCVR is undefined - */ -#define LOBS_CCVR_CCVR_MASK (0xFFFFFFFFUL) -#define LOBS_CCVR_CCVR_SHIFT (0U) -#define LOBS_CCVR_CCVR_GET(x) (((uint32_t)(x) & LOBS_CCVR_CCVR_MASK) >> LOBS_CCVR_CCVR_SHIFT) - -/* Bitfield definition for register: CAVR */ -/* - * TRACE (RO) - * - * Trace active. - * 0b0 Trace is not active. - * 0b1 Trace is active. - */ -#define LOBS_CAVR_TRACE_MASK (0x8U) -#define LOBS_CAVR_TRACE_SHIFT (3U) -#define LOBS_CAVR_TRACE_GET(x) (((uint32_t)(x) & LOBS_CAVR_TRACE_MASK) >> LOBS_CAVR_TRACE_SHIFT) - -/* Bitfield definition for register: FIFOSTATE */ -/* - * FULL (RO) - * - * FIFO full - */ -#define LOBS_FIFOSTATE_FULL_MASK (0x2U) -#define LOBS_FIFOSTATE_FULL_SHIFT (1U) -#define LOBS_FIFOSTATE_FULL_GET(x) (((uint32_t)(x) & LOBS_FIFOSTATE_FULL_MASK) >> LOBS_FIFOSTATE_FULL_SHIFT) - -/* - * EMPTY (RO) - * - * FIFO empty - */ -#define LOBS_FIFOSTATE_EMPTY_MASK (0x1U) -#define LOBS_FIFOSTATE_EMPTY_SHIFT (0U) -#define LOBS_FIFOSTATE_EMPTY_GET(x) (((uint32_t)(x) & LOBS_FIFOSTATE_EMPTY_MASK) >> LOBS_FIFOSTATE_EMPTY_SHIFT) - -/* Bitfield definition for register: FINALADDR */ -/* - * ADDR (RW) - * - * Final address - */ -#define LOBS_FINALADDR_ADDR_MASK (0xFFFFFFFFUL) -#define LOBS_FINALADDR_ADDR_SHIFT (0U) -#define LOBS_FINALADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_FINALADDR_ADDR_SHIFT) & LOBS_FINALADDR_ADDR_MASK) -#define LOBS_FINALADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_FINALADDR_ADDR_MASK) >> LOBS_FINALADDR_ADDR_SHIFT) - -/* Bitfield definition for register: GRPSELA */ -/* - * NUM2 (RW) - * - * Select sample group number2 - */ -#define LOBS_GRPSELA_NUM2_MASK (0xF0U) -#define LOBS_GRPSELA_NUM2_SHIFT (4U) -#define LOBS_GRPSELA_NUM2_SET(x) (((uint32_t)(x) << LOBS_GRPSELA_NUM2_SHIFT) & LOBS_GRPSELA_NUM2_MASK) -#define LOBS_GRPSELA_NUM2_GET(x) (((uint32_t)(x) & LOBS_GRPSELA_NUM2_MASK) >> LOBS_GRPSELA_NUM2_SHIFT) - -/* - * NUM1 (RW) - * - * Select sample group number1 - */ -#define LOBS_GRPSELA_NUM1_MASK (0xFU) -#define LOBS_GRPSELA_NUM1_SHIFT (0U) -#define LOBS_GRPSELA_NUM1_SET(x) (((uint32_t)(x) << LOBS_GRPSELA_NUM1_SHIFT) & LOBS_GRPSELA_NUM1_MASK) -#define LOBS_GRPSELA_NUM1_GET(x) (((uint32_t)(x) & LOBS_GRPSELA_NUM1_MASK) >> LOBS_GRPSELA_NUM1_SHIFT) - -/* Bitfield definition for register: GRPENA */ -/* - * EN2 (RW) - * - * Enable sample group number2 - */ -#define LOBS_GRPENA_EN2_MASK (0x2U) -#define LOBS_GRPENA_EN2_SHIFT (1U) -#define LOBS_GRPENA_EN2_SET(x) (((uint32_t)(x) << LOBS_GRPENA_EN2_SHIFT) & LOBS_GRPENA_EN2_MASK) -#define LOBS_GRPENA_EN2_GET(x) (((uint32_t)(x) & LOBS_GRPENA_EN2_MASK) >> LOBS_GRPENA_EN2_SHIFT) - -/* - * EN1 (RW) - * - * Enable sample group number1 - */ -#define LOBS_GRPENA_EN1_MASK (0x1U) -#define LOBS_GRPENA_EN1_SHIFT (0U) -#define LOBS_GRPENA_EN1_SET(x) (((uint32_t)(x) << LOBS_GRPENA_EN1_SHIFT) & LOBS_GRPENA_EN1_MASK) -#define LOBS_GRPENA_EN1_GET(x) (((uint32_t)(x) & LOBS_GRPENA_EN1_MASK) >> LOBS_GRPENA_EN1_SHIFT) - -/* Bitfield definition for register: SIGSELA1 */ -/* - * NUM4 (RW) - * - * Select sample signal bit number4 in first group - */ -#define LOBS_SIGSELA1_NUM4_MASK (0xFF000000UL) -#define LOBS_SIGSELA1_NUM4_SHIFT (24U) -#define LOBS_SIGSELA1_NUM4_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM4_SHIFT) & LOBS_SIGSELA1_NUM4_MASK) -#define LOBS_SIGSELA1_NUM4_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM4_MASK) >> LOBS_SIGSELA1_NUM4_SHIFT) - -/* - * NUM3 (RW) - * - * Select sample signal bit number3 in first group - */ -#define LOBS_SIGSELA1_NUM3_MASK (0xFF0000UL) -#define LOBS_SIGSELA1_NUM3_SHIFT (16U) -#define LOBS_SIGSELA1_NUM3_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM3_SHIFT) & LOBS_SIGSELA1_NUM3_MASK) -#define LOBS_SIGSELA1_NUM3_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM3_MASK) >> LOBS_SIGSELA1_NUM3_SHIFT) - -/* - * NUM2 (RW) - * - * Select sample signal bit number2 in first group - */ -#define LOBS_SIGSELA1_NUM2_MASK (0xFF00U) -#define LOBS_SIGSELA1_NUM2_SHIFT (8U) -#define LOBS_SIGSELA1_NUM2_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM2_SHIFT) & LOBS_SIGSELA1_NUM2_MASK) -#define LOBS_SIGSELA1_NUM2_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM2_MASK) >> LOBS_SIGSELA1_NUM2_SHIFT) - -/* - * NUM1 (RW) - * - * Select sample signal bit number1 in first group - */ -#define LOBS_SIGSELA1_NUM1_MASK (0xFFU) -#define LOBS_SIGSELA1_NUM1_SHIFT (0U) -#define LOBS_SIGSELA1_NUM1_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM1_SHIFT) & LOBS_SIGSELA1_NUM1_MASK) -#define LOBS_SIGSELA1_NUM1_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM1_MASK) >> LOBS_SIGSELA1_NUM1_SHIFT) - -/* Bitfield definition for register: SIGSELA2 */ -/* - * NUM4 (RW) - * - * Select sample signal bit number4 in second group - */ -#define LOBS_SIGSELA2_NUM4_MASK (0xFF000000UL) -#define LOBS_SIGSELA2_NUM4_SHIFT (24U) -#define LOBS_SIGSELA2_NUM4_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM4_SHIFT) & LOBS_SIGSELA2_NUM4_MASK) -#define LOBS_SIGSELA2_NUM4_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM4_MASK) >> LOBS_SIGSELA2_NUM4_SHIFT) - -/* - * NUM3 (RW) - * - * Select sample signal bit number3 in second group - */ -#define LOBS_SIGSELA2_NUM3_MASK (0xFF0000UL) -#define LOBS_SIGSELA2_NUM3_SHIFT (16U) -#define LOBS_SIGSELA2_NUM3_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM3_SHIFT) & LOBS_SIGSELA2_NUM3_MASK) -#define LOBS_SIGSELA2_NUM3_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM3_MASK) >> LOBS_SIGSELA2_NUM3_SHIFT) - -/* - * NUM2 (RW) - * - * Select sample signal bit number2 in second group - */ -#define LOBS_SIGSELA2_NUM2_MASK (0xFF00U) -#define LOBS_SIGSELA2_NUM2_SHIFT (8U) -#define LOBS_SIGSELA2_NUM2_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM2_SHIFT) & LOBS_SIGSELA2_NUM2_MASK) -#define LOBS_SIGSELA2_NUM2_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM2_MASK) >> LOBS_SIGSELA2_NUM2_SHIFT) - -/* - * NUM1 (RW) - * - * Select sample signal bit number1 in second group - */ -#define LOBS_SIGSELA2_NUM1_MASK (0xFFU) -#define LOBS_SIGSELA2_NUM1_SHIFT (0U) -#define LOBS_SIGSELA2_NUM1_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM1_SHIFT) & LOBS_SIGSELA2_NUM1_MASK) -#define LOBS_SIGSELA2_NUM1_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM1_MASK) >> LOBS_SIGSELA2_NUM1_SHIFT) - -/* Bitfield definition for register: SIGENA */ -/* - * EN2 (RW) - * - * Enable sample signal number2 - */ -#define LOBS_SIGENA_EN2_MASK (0xF0U) -#define LOBS_SIGENA_EN2_SHIFT (4U) -#define LOBS_SIGENA_EN2_SET(x) (((uint32_t)(x) << LOBS_SIGENA_EN2_SHIFT) & LOBS_SIGENA_EN2_MASK) -#define LOBS_SIGENA_EN2_GET(x) (((uint32_t)(x) & LOBS_SIGENA_EN2_MASK) >> LOBS_SIGENA_EN2_SHIFT) - -/* - * EN1 (RW) - * - * Enable sample signal number1 - */ -#define LOBS_SIGENA_EN1_MASK (0xFU) -#define LOBS_SIGENA_EN1_SHIFT (0U) -#define LOBS_SIGENA_EN1_SET(x) (((uint32_t)(x) << LOBS_SIGENA_EN1_SHIFT) & LOBS_SIGENA_EN1_MASK) -#define LOBS_SIGENA_EN1_GET(x) (((uint32_t)(x) & LOBS_SIGENA_EN1_MASK) >> LOBS_SIGENA_EN1_SHIFT) - -/* Bitfield definition for register of struct array STATE: SIGSEL */ -/* - * EN (RW) - * - * Selects Signal Group. - * 0x1 Selects Signal Group 0. - * 0x2 Selects Signal Group 1. - * 0x4 Selects Signal Group 2. - * 0x8 Selects Signal Group 3. - * 0x10 Selects Signal Group 4. - * 0x20 Selects Signal Group 5. - * 0x40 Selects Signal Group 6. - * 0x80 Selects Signal Group 7. - * 0x100 Selects Signal Group 8. - * 0x200 Selects Signal Group 9. - * 0x400 Selects Signal Group 10. - * 0x800 Selects Signal Group 11. - */ -#define LOBS_STATE_SIGSEL_EN_MASK (0xFFFU) -#define LOBS_STATE_SIGSEL_EN_SHIFT (0U) -#define LOBS_STATE_SIGSEL_EN_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGSEL_EN_SHIFT) & LOBS_STATE_SIGSEL_EN_MASK) -#define LOBS_STATE_SIGSEL_EN_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGSEL_EN_MASK) >> LOBS_STATE_SIGSEL_EN_SHIFT) - -/* Bitfield definition for register of struct array STATE: TRIGCTRL */ -/* - * TRACE (RW) - * - * Trace capture control. - * 0b10 Trace is captured every ELACLK cycle. - * others Reserved. - */ -#define LOBS_STATE_TRIGCTRL_TRACE_MASK (0xC0U) -#define LOBS_STATE_TRIGCTRL_TRACE_SHIFT (6U) -#define LOBS_STATE_TRIGCTRL_TRACE_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_TRACE_SHIFT) & LOBS_STATE_TRIGCTRL_TRACE_MASK) -#define LOBS_STATE_TRIGCTRL_TRACE_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_TRACE_MASK) >> LOBS_STATE_TRIGCTRL_TRACE_SHIFT) - -/* - * COMPSEL (RW) - * - * Comparison mode. Acts as both a counter enable and a select for the comparison mode. - * 0b0 Disable counters and select Trigger Signal Comparison mode. - * 0b1 Enable counters and select Trigger Counter Comparison mode. - */ -#define LOBS_STATE_TRIGCTRL_COMPSEL_MASK (0x8U) -#define LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT (3U) -#define LOBS_STATE_TRIGCTRL_COMPSEL_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT) & LOBS_STATE_TRIGCTRL_COMPSEL_MASK) -#define LOBS_STATE_TRIGCTRL_COMPSEL_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_COMPSEL_MASK) >> LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT) - -/* - * COMP (RW) - * - * Trigger Signal Comparison type select. - * 0b000 Trigger Signal Comparisons disabled. The enabled counters count clocks immediately after the Trigger State has been entered and generate a programmable Output Action and transition to the next Trigger State when the Counter Compare Register count is reached, that is when a Trigger Counter Comparison match occurs. - * 0b001 Compare type is equal (==). - * 0b010 Compare type is greater than (>). - * 0b011 Compare type is greater than or equal (>=). - * 0b101 Compare type is not equal (!=). - * 0b110 Compare type is less than (<). - * 0b111 Compare type is less than or equal (<=). - */ -#define LOBS_STATE_TRIGCTRL_COMP_MASK (0x7U) -#define LOBS_STATE_TRIGCTRL_COMP_SHIFT (0U) -#define LOBS_STATE_TRIGCTRL_COMP_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_COMP_SHIFT) & LOBS_STATE_TRIGCTRL_COMP_MASK) -#define LOBS_STATE_TRIGCTRL_COMP_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_COMP_MASK) >> LOBS_STATE_TRIGCTRL_COMP_SHIFT) - -/* Bitfield definition for register of struct array STATE: NEXTSTATE */ -/* - * NEXTSTATE (RW) - * - * Selects the next state to move to after the Trigger Condition has been met in the current state. - * 0x0 Do not change state. This is the final Trigger State. - * 0x1 Selects Trigger State 0. - * 0x2 Selects Trigger State 1. - * 0x4 Selects Trigger State 2. - * 0x8 Selects Trigger State 3. - * 0x10 Selects Trigger State 4. - */ -#define LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK (0x1FU) -#define LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT (0U) -#define LOBS_STATE_NEXTSTATE_NEXTSTATE_SET(x) (((uint32_t)(x) << LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT) & LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK) -#define LOBS_STATE_NEXTSTATE_NEXTSTATE_GET(x) (((uint32_t)(x) & LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK) >> LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT) - -/* Bitfield definition for register of struct array STATE: ACTION */ -/* - * TRACE (RW) - * - * Trace active. - * 0b0 Trace disable. - * 0b1 Trace enable. - */ -#define LOBS_STATE_ACTION_TRACE_MASK (0x8U) -#define LOBS_STATE_ACTION_TRACE_SHIFT (3U) -#define LOBS_STATE_ACTION_TRACE_SET(x) (((uint32_t)(x) << LOBS_STATE_ACTION_TRACE_SHIFT) & LOBS_STATE_ACTION_TRACE_MASK) -#define LOBS_STATE_ACTION_TRACE_GET(x) (((uint32_t)(x) & LOBS_STATE_ACTION_TRACE_MASK) >> LOBS_STATE_ACTION_TRACE_SHIFT) - -/* Bitfield definition for register of struct array STATE: COUNTCOMP */ -/* - * VALUE (RW) - * - * A value that, when reached in the associated up-counter for this Trigger State, causes a Trigger Counter Comparison match to occur. - */ -#define LOBS_STATE_COUNTCOMP_VALUE_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_COUNTCOMP_VALUE_SHIFT (0U) -#define LOBS_STATE_COUNTCOMP_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_COUNTCOMP_VALUE_SHIFT) & LOBS_STATE_COUNTCOMP_VALUE_MASK) -#define LOBS_STATE_COUNTCOMP_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_COUNTCOMP_VALUE_MASK) >> LOBS_STATE_COUNTCOMP_VALUE_SHIFT) - -/* Bitfield definition for register of struct array STATE: EXTMASK */ -/* - * VALUE (RW) - * - * External Mask - */ -#define LOBS_STATE_EXTMASK_VALUE_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_EXTMASK_VALUE_SHIFT (0U) -#define LOBS_STATE_EXTMASK_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_EXTMASK_VALUE_SHIFT) & LOBS_STATE_EXTMASK_VALUE_MASK) -#define LOBS_STATE_EXTMASK_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_EXTMASK_VALUE_MASK) >> LOBS_STATE_EXTMASK_VALUE_SHIFT) - -/* Bitfield definition for register of struct array STATE: EXTCOMP */ -/* - * VALUE (RW) - * - * External Compare - */ -#define LOBS_STATE_EXTCOMP_VALUE_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_EXTCOMP_VALUE_SHIFT (0U) -#define LOBS_STATE_EXTCOMP_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_EXTCOMP_VALUE_SHIFT) & LOBS_STATE_EXTCOMP_VALUE_MASK) -#define LOBS_STATE_EXTCOMP_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_EXTCOMP_VALUE_MASK) >> LOBS_STATE_EXTCOMP_VALUE_SHIFT) - -/* Bitfield definition for register of struct array STATE: SIGMASK */ -/* - * NUM3 (RW) - * - * Select compare signal number3 - */ -#define LOBS_STATE_SIGMASK_NUM3_MASK (0xFF000000UL) -#define LOBS_STATE_SIGMASK_NUM3_SHIFT (24U) -#define LOBS_STATE_SIGMASK_NUM3_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM3_SHIFT) & LOBS_STATE_SIGMASK_NUM3_MASK) -#define LOBS_STATE_SIGMASK_NUM3_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM3_MASK) >> LOBS_STATE_SIGMASK_NUM3_SHIFT) - -/* - * NUM2 (RW) - * - * Select compare signal number2 - */ -#define LOBS_STATE_SIGMASK_NUM2_MASK (0xFF0000UL) -#define LOBS_STATE_SIGMASK_NUM2_SHIFT (16U) -#define LOBS_STATE_SIGMASK_NUM2_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM2_SHIFT) & LOBS_STATE_SIGMASK_NUM2_MASK) -#define LOBS_STATE_SIGMASK_NUM2_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM2_MASK) >> LOBS_STATE_SIGMASK_NUM2_SHIFT) - -/* - * NUM1 (RW) - * - * Select compare signal number1 - */ -#define LOBS_STATE_SIGMASK_NUM1_MASK (0xFF00U) -#define LOBS_STATE_SIGMASK_NUM1_SHIFT (8U) -#define LOBS_STATE_SIGMASK_NUM1_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM1_SHIFT) & LOBS_STATE_SIGMASK_NUM1_MASK) -#define LOBS_STATE_SIGMASK_NUM1_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM1_MASK) >> LOBS_STATE_SIGMASK_NUM1_SHIFT) - -/* - * NUM0 (RW) - * - * Select compare signal number0 - */ -#define LOBS_STATE_SIGMASK_NUM0_MASK (0xFFU) -#define LOBS_STATE_SIGMASK_NUM0_SHIFT (0U) -#define LOBS_STATE_SIGMASK_NUM0_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM0_SHIFT) & LOBS_STATE_SIGMASK_NUM0_MASK) -#define LOBS_STATE_SIGMASK_NUM0_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM0_MASK) >> LOBS_STATE_SIGMASK_NUM0_SHIFT) - -/* Bitfield definition for register of struct array STATE: COMPEN */ -/* - * EN (RW) - * - * Select compare signal number0-3 - */ -#define LOBS_STATE_COMPEN_EN_MASK (0xFU) -#define LOBS_STATE_COMPEN_EN_SHIFT (0U) -#define LOBS_STATE_COMPEN_EN_SET(x) (((uint32_t)(x) << LOBS_STATE_COMPEN_EN_SHIFT) & LOBS_STATE_COMPEN_EN_MASK) -#define LOBS_STATE_COMPEN_EN_GET(x) (((uint32_t)(x) & LOBS_STATE_COMPEN_EN_MASK) >> LOBS_STATE_COMPEN_EN_SHIFT) - -/* Bitfield definition for register of struct array STATE: SIGCOMP0 */ -/* - * VALUE0 (RW) - * - * Compare golden value for Signal Group signals[31:0]. - */ -#define LOBS_STATE_SIGCOMP0_VALUE0_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_SIGCOMP0_VALUE0_SHIFT (0U) -#define LOBS_STATE_SIGCOMP0_VALUE0_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP0_VALUE0_SHIFT) & LOBS_STATE_SIGCOMP0_VALUE0_MASK) -#define LOBS_STATE_SIGCOMP0_VALUE0_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP0_VALUE0_MASK) >> LOBS_STATE_SIGCOMP0_VALUE0_SHIFT) - -/* Bitfield definition for register of struct array STATE: SIGCOMP1 */ -/* - * VALUE1 (RW) - * - * Compare golden value for Signal Group signals[63:32]. - */ -#define LOBS_STATE_SIGCOMP1_VALUE1_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_SIGCOMP1_VALUE1_SHIFT (0U) -#define LOBS_STATE_SIGCOMP1_VALUE1_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP1_VALUE1_SHIFT) & LOBS_STATE_SIGCOMP1_VALUE1_MASK) -#define LOBS_STATE_SIGCOMP1_VALUE1_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP1_VALUE1_MASK) >> LOBS_STATE_SIGCOMP1_VALUE1_SHIFT) - -/* Bitfield definition for register of struct array STATE: SIGCOMP2 */ -/* - * VALUE2 (RW) - * - * Compare golden value for Signal Group signals[95:64]. - */ -#define LOBS_STATE_SIGCOMP2_VALUE2_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_SIGCOMP2_VALUE2_SHIFT (0U) -#define LOBS_STATE_SIGCOMP2_VALUE2_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP2_VALUE2_SHIFT) & LOBS_STATE_SIGCOMP2_VALUE2_MASK) -#define LOBS_STATE_SIGCOMP2_VALUE2_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP2_VALUE2_MASK) >> LOBS_STATE_SIGCOMP2_VALUE2_SHIFT) - -/* Bitfield definition for register of struct array STATE: SIGCOMP3 */ -/* - * VALUE3 (RW) - * - * Compare golden value for Signal Group signals[127:96]. - */ -#define LOBS_STATE_SIGCOMP3_VALUE3_MASK (0xFFFFFFFFUL) -#define LOBS_STATE_SIGCOMP3_VALUE3_SHIFT (0U) -#define LOBS_STATE_SIGCOMP3_VALUE3_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP3_VALUE3_SHIFT) & LOBS_STATE_SIGCOMP3_VALUE3_MASK) -#define LOBS_STATE_SIGCOMP3_VALUE3_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP3_VALUE3_MASK) >> LOBS_STATE_SIGCOMP3_VALUE3_SHIFT) - -/* Bitfield definition for register: LAR */ -/* - * VALUE (RW) - * - * Lock Access Value - */ -#define LOBS_LAR_VALUE_MASK (0xFFFFFFFFUL) -#define LOBS_LAR_VALUE_SHIFT (0U) -#define LOBS_LAR_VALUE_SET(x) (((uint32_t)(x) << LOBS_LAR_VALUE_SHIFT) & LOBS_LAR_VALUE_MASK) -#define LOBS_LAR_VALUE_GET(x) (((uint32_t)(x) & LOBS_LAR_VALUE_MASK) >> LOBS_LAR_VALUE_SHIFT) - - - -/* STATE register group index macro definition */ -#define LOBS_STATE_0 (0UL) -#define LOBS_STATE_1 (1UL) -#define LOBS_STATE_2 (2UL) -#define LOBS_STATE_3 (3UL) -#define LOBS_STATE_4 (4UL) - - -#endif /* HPM_LOBS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mbx_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mbx_regs.h deleted file mode 100644 index d159b97303a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mbx_regs.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MBX_H -#define HPM_MBX_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Command Registers */ - __RW uint32_t SR; /* 0x4: Status Registers */ - __W uint32_t TXREG; /* 0x8: Transmit word message to other core. */ - __R uint32_t RXREG; /* 0xC: Receive word message from other core. */ - __W uint32_t TXWRD[1]; /* 0x10: TXFIFO for sending message to other core */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t RXWRD[1]; /* 0x20: RXFIFO for receiving message from other core */ -} MBX_Type; - - -/* Bitfield definition for register: CR */ -/* - * TXRESET (RW) - * - * Reset TX Fifo and word. - */ -#define MBX_CR_TXRESET_MASK (0x80000000UL) -#define MBX_CR_TXRESET_SHIFT (31U) -#define MBX_CR_TXRESET_SET(x) (((uint32_t)(x) << MBX_CR_TXRESET_SHIFT) & MBX_CR_TXRESET_MASK) -#define MBX_CR_TXRESET_GET(x) (((uint32_t)(x) & MBX_CR_TXRESET_MASK) >> MBX_CR_TXRESET_SHIFT) - -/* - * BARCTL (RW) - * - * Bus Access Response Control, when bit 15:14= - * 00: no bus error will be generated, no wait for fifo write when fifo full and no wait for word/fifo read when word message invalid or fifo empty; or when write to word/fifo message will be ignored. - * 01: bus error will be generated when: 1, access invalid address; 2, write to ready only addr; 3, write to fulled fifo or valid message; 4, read from a emptied fifo/word message. - * 10: no error will be generated, but bus will wait when 1, write to fulled fifo/reg message; 2, read from a emptied fifo/reg message; write to word message will overwrite the existing reg value enven word message are still valid; read from invalid word message will read out last read out message data.happen. - * 11: reserved. - */ -#define MBX_CR_BARCTL_MASK (0xC000U) -#define MBX_CR_BARCTL_SHIFT (14U) -#define MBX_CR_BARCTL_SET(x) (((uint32_t)(x) << MBX_CR_BARCTL_SHIFT) & MBX_CR_BARCTL_MASK) -#define MBX_CR_BARCTL_GET(x) (((uint32_t)(x) & MBX_CR_BARCTL_MASK) >> MBX_CR_BARCTL_SHIFT) - -/* - * BEIE (RW) - * - * Bus Error Interrupt Enable, will enable the interrupt for any bus error as described in the SR bit 13 to bit 8. - * 1, enable the bus access error interrupt. - * 0, disable the bus access error interrupt. - */ -#define MBX_CR_BEIE_MASK (0x100U) -#define MBX_CR_BEIE_SHIFT (8U) -#define MBX_CR_BEIE_SET(x) (((uint32_t)(x) << MBX_CR_BEIE_SHIFT) & MBX_CR_BEIE_MASK) -#define MBX_CR_BEIE_GET(x) (((uint32_t)(x) & MBX_CR_BEIE_MASK) >> MBX_CR_BEIE_SHIFT) - -/* - * TFMAIE (RW) - * - * TX FIFO message available interrupt enable. - * 1, enable the TX FIFO massage available interrupt. - * 0, disable the TX FIFO message available interrupt. - */ -#define MBX_CR_TFMAIE_MASK (0x80U) -#define MBX_CR_TFMAIE_SHIFT (7U) -#define MBX_CR_TFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMAIE_SHIFT) & MBX_CR_TFMAIE_MASK) -#define MBX_CR_TFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMAIE_MASK) >> MBX_CR_TFMAIE_SHIFT) - -/* - * TFMEIE (RW) - * - * TX FIFO message empty interrupt enable. - * 1, enable the TX FIFO massage empty interrupt. - * 0, disable the TX FIFO message empty interrupt. - */ -#define MBX_CR_TFMEIE_MASK (0x40U) -#define MBX_CR_TFMEIE_SHIFT (6U) -#define MBX_CR_TFMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TFMEIE_SHIFT) & MBX_CR_TFMEIE_MASK) -#define MBX_CR_TFMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TFMEIE_MASK) >> MBX_CR_TFMEIE_SHIFT) - -/* - * RFMAIE (RW) - * - * RX FIFO message available interrupt enable. - * 1, enable the RX FIFO massage available interrupt. - * 0, disable the RX FIFO message available interrupt. - */ -#define MBX_CR_RFMAIE_MASK (0x20U) -#define MBX_CR_RFMAIE_SHIFT (5U) -#define MBX_CR_RFMAIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMAIE_SHIFT) & MBX_CR_RFMAIE_MASK) -#define MBX_CR_RFMAIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMAIE_MASK) >> MBX_CR_RFMAIE_SHIFT) - -/* - * RFMFIE (RW) - * - * RX fifo message full interrupt enable. - * 1, enable the RX fifo message full interrupt. - * 0, disable the RX fifo message full interrupt. - */ -#define MBX_CR_RFMFIE_MASK (0x10U) -#define MBX_CR_RFMFIE_SHIFT (4U) -#define MBX_CR_RFMFIE_SET(x) (((uint32_t)(x) << MBX_CR_RFMFIE_SHIFT) & MBX_CR_RFMFIE_MASK) -#define MBX_CR_RFMFIE_GET(x) (((uint32_t)(x) & MBX_CR_RFMFIE_MASK) >> MBX_CR_RFMFIE_SHIFT) - -/* - * TWMEIE (RW) - * - * TX word message empty interrupt enable. - * 1, enable the TX word massage empty interrupt. - * 0, disable the TX word message empty interrupt. - */ -#define MBX_CR_TWMEIE_MASK (0x2U) -#define MBX_CR_TWMEIE_SHIFT (1U) -#define MBX_CR_TWMEIE_SET(x) (((uint32_t)(x) << MBX_CR_TWMEIE_SHIFT) & MBX_CR_TWMEIE_MASK) -#define MBX_CR_TWMEIE_GET(x) (((uint32_t)(x) & MBX_CR_TWMEIE_MASK) >> MBX_CR_TWMEIE_SHIFT) - -/* - * RWMVIE (RW) - * - * RX word message valid interrupt enable. - * 1, enable the RX word massage valid interrupt. - * 0, disable the RX word message valid interrupt. - */ -#define MBX_CR_RWMVIE_MASK (0x1U) -#define MBX_CR_RWMVIE_SHIFT (0U) -#define MBX_CR_RWMVIE_SET(x) (((uint32_t)(x) << MBX_CR_RWMVIE_SHIFT) & MBX_CR_RWMVIE_MASK) -#define MBX_CR_RWMVIE_GET(x) (((uint32_t)(x) & MBX_CR_RWMVIE_MASK) >> MBX_CR_RWMVIE_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * RFVC (RO) - * - * RX FIFO valid message count - */ -#define MBX_SR_RFVC_MASK (0xF00000UL) -#define MBX_SR_RFVC_SHIFT (20U) -#define MBX_SR_RFVC_GET(x) (((uint32_t)(x) & MBX_SR_RFVC_MASK) >> MBX_SR_RFVC_SHIFT) - -/* - * TFEC (RO) - * - * TX FIFO empty message word count - */ -#define MBX_SR_TFEC_MASK (0xF0000UL) -#define MBX_SR_TFEC_SHIFT (16U) -#define MBX_SR_TFEC_GET(x) (((uint32_t)(x) & MBX_SR_TFEC_MASK) >> MBX_SR_TFEC_SHIFT) - -/* - * ERRRE (W1C) - * - * bus Error for read when rx word message are still invalid, this bit is W1C bit. - * 1, read from word message when the word message are still invalid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRRE_MASK (0x2000U) -#define MBX_SR_ERRRE_SHIFT (13U) -#define MBX_SR_ERRRE_SET(x) (((uint32_t)(x) << MBX_SR_ERRRE_SHIFT) & MBX_SR_ERRRE_MASK) -#define MBX_SR_ERRRE_GET(x) (((uint32_t)(x) & MBX_SR_ERRRE_MASK) >> MBX_SR_ERRRE_SHIFT) - -/* - * EWTRF (W1C) - * - * bus Error for write when tx word message are still valid, this bit is W1C bit. - * 1, write to word message when the word message are still valid will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTRF_MASK (0x1000U) -#define MBX_SR_EWTRF_SHIFT (12U) -#define MBX_SR_EWTRF_SET(x) (((uint32_t)(x) << MBX_SR_EWTRF_SHIFT) & MBX_SR_EWTRF_MASK) -#define MBX_SR_EWTRF_GET(x) (((uint32_t)(x) & MBX_SR_EWTRF_MASK) >> MBX_SR_EWTRF_SHIFT) - -/* - * ERRFE (W1C) - * - * bus Error for read when rx fifo empty, this bit is W1C bit. - * 1, read from a empty rx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_ERRFE_MASK (0x800U) -#define MBX_SR_ERRFE_SHIFT (11U) -#define MBX_SR_ERRFE_SET(x) (((uint32_t)(x) << MBX_SR_ERRFE_SHIFT) & MBX_SR_ERRFE_MASK) -#define MBX_SR_ERRFE_GET(x) (((uint32_t)(x) & MBX_SR_ERRFE_MASK) >> MBX_SR_ERRFE_SHIFT) - -/* - * EWTFF (W1C) - * - * bus Error for write when tx fifo full, this bit is W1C bit. - * 1, write to a fulled tx fifo will cause this error bit set. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EWTFF_MASK (0x400U) -#define MBX_SR_EWTFF_SHIFT (10U) -#define MBX_SR_EWTFF_SET(x) (((uint32_t)(x) << MBX_SR_EWTFF_SHIFT) & MBX_SR_EWTFF_MASK) -#define MBX_SR_EWTFF_GET(x) (((uint32_t)(x) & MBX_SR_EWTFF_MASK) >> MBX_SR_EWTFF_SHIFT) - -/* - * EAIVA (W1C) - * - * bus Error for Accessing Invalid Address; this bit is W1C bit. - * 1, read and write to invalid address in the bus of this block, will set this bit. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EAIVA_MASK (0x200U) -#define MBX_SR_EAIVA_SHIFT (9U) -#define MBX_SR_EAIVA_SET(x) (((uint32_t)(x) << MBX_SR_EAIVA_SHIFT) & MBX_SR_EAIVA_MASK) -#define MBX_SR_EAIVA_GET(x) (((uint32_t)(x) & MBX_SR_EAIVA_MASK) >> MBX_SR_EAIVA_SHIFT) - -/* - * EW2RO (W1C) - * - * bus Error for Write to Read Only address; this bit is W1C bit. - * 1, write to read only address happened in the bus of this block. - * 0, nothis kind of bus error; write this bit to 1 will clear this bit when this kind of error happen. - */ -#define MBX_SR_EW2RO_MASK (0x100U) -#define MBX_SR_EW2RO_SHIFT (8U) -#define MBX_SR_EW2RO_SET(x) (((uint32_t)(x) << MBX_SR_EW2RO_SHIFT) & MBX_SR_EW2RO_MASK) -#define MBX_SR_EW2RO_GET(x) (((uint32_t)(x) & MBX_SR_EW2RO_MASK) >> MBX_SR_EW2RO_SHIFT) - -/* - * TFMA (RW) - * - * TX FIFO Message slot available, the 4x32 TX FIFO message buffer to the other core full, will not trigger any interrupt. - * 1, TXFIFO message buffer has slot available - * 0, no slot available (fifo full) - */ -#define MBX_SR_TFMA_MASK (0x80U) -#define MBX_SR_TFMA_SHIFT (7U) -#define MBX_SR_TFMA_SET(x) (((uint32_t)(x) << MBX_SR_TFMA_SHIFT) & MBX_SR_TFMA_MASK) -#define MBX_SR_TFMA_GET(x) (((uint32_t)(x) & MBX_SR_TFMA_MASK) >> MBX_SR_TFMA_SHIFT) - -/* - * TFME (RW) - * - * TX FIFO Message Empty, no any data in the message FIFO buffer from other core, will not trigger any interrupt.message from other core. - * 1, no any message data in TXFIFO from other core. - * 0, there are some data in the 4x32 TX FIFO from other core yet. - */ -#define MBX_SR_TFME_MASK (0x40U) -#define MBX_SR_TFME_SHIFT (6U) -#define MBX_SR_TFME_SET(x) (((uint32_t)(x) << MBX_SR_TFME_SHIFT) & MBX_SR_TFME_MASK) -#define MBX_SR_TFME_GET(x) (((uint32_t)(x) & MBX_SR_TFME_MASK) >> MBX_SR_TFME_SHIFT) - -/* - * RFMA (RO) - * - * RX FIFO Message Available, available data in the 4x32 TX FIFO message buffer to the other core, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, no any data in the 4x32 TXFIFO message buffer. - * 0, there are some data in the the 4x32 TXFIFO message buffer already. - */ -#define MBX_SR_RFMA_MASK (0x20U) -#define MBX_SR_RFMA_SHIFT (5U) -#define MBX_SR_RFMA_GET(x) (((uint32_t)(x) & MBX_SR_RFMA_MASK) >> MBX_SR_RFMA_SHIFT) - -/* - * RFMF (RO) - * - * RX FIFO Message Full, message from other core; will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written 4x32 message in the RXFIFO. - * 0, no 4x32 RX FIFO message from other core yet. - */ -#define MBX_SR_RFMF_MASK (0x10U) -#define MBX_SR_RFMF_SHIFT (4U) -#define MBX_SR_RFMF_GET(x) (((uint32_t)(x) & MBX_SR_RFMF_MASK) >> MBX_SR_RFMF_SHIFT) - -/* - * TWME (RO) - * - * TX word message empty, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, means this core had write word message to TXREG. - * 0, means no valid word message in the TXREG yet. - */ -#define MBX_SR_TWME_MASK (0x2U) -#define MBX_SR_TWME_SHIFT (1U) -#define MBX_SR_TWME_GET(x) (((uint32_t)(x) & MBX_SR_TWME_MASK) >> MBX_SR_TWME_SHIFT) - -/* - * RWMV (RO) - * - * RX word message valid, will trigger interrupt if the related interrupt enable bit set in the control (CR) registrer. - * 1, the other core had written word message in the RXREG. - * 0, no valid word message yet in the RXREG. - */ -#define MBX_SR_RWMV_MASK (0x1U) -#define MBX_SR_RWMV_SHIFT (0U) -#define MBX_SR_RWMV_GET(x) (((uint32_t)(x) & MBX_SR_RWMV_MASK) >> MBX_SR_RWMV_SHIFT) - -/* Bitfield definition for register: TXREG */ -/* - * TXREG (WO) - * - * Transmit word message to other core. - */ -#define MBX_TXREG_TXREG_MASK (0xFFFFFFFFUL) -#define MBX_TXREG_TXREG_SHIFT (0U) -#define MBX_TXREG_TXREG_SET(x) (((uint32_t)(x) << MBX_TXREG_TXREG_SHIFT) & MBX_TXREG_TXREG_MASK) -#define MBX_TXREG_TXREG_GET(x) (((uint32_t)(x) & MBX_TXREG_TXREG_MASK) >> MBX_TXREG_TXREG_SHIFT) - -/* Bitfield definition for register: RXREG */ -/* - * RXREG (RO) - * - * Receive word message from other core. - */ -#define MBX_RXREG_RXREG_MASK (0xFFFFFFFFUL) -#define MBX_RXREG_RXREG_SHIFT (0U) -#define MBX_RXREG_RXREG_GET(x) (((uint32_t)(x) & MBX_RXREG_RXREG_MASK) >> MBX_RXREG_RXREG_SHIFT) - -/* Bitfield definition for register array: TXWRD */ -/* - * TXFIFO (WO) - * - * TXFIFO for sending message to other core, FIFO size, 4x32 - * can write one of the word address to push data to the FIFO; - * can also use 4x32 burst write from 0x010 to push 4 words to the FIFO. - */ -#define MBX_TXWRD_TXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_TXWRD_TXFIFO_SHIFT (0U) -#define MBX_TXWRD_TXFIFO_SET(x) (((uint32_t)(x) << MBX_TXWRD_TXFIFO_SHIFT) & MBX_TXWRD_TXFIFO_MASK) -#define MBX_TXWRD_TXFIFO_GET(x) (((uint32_t)(x) & MBX_TXWRD_TXFIFO_MASK) >> MBX_TXWRD_TXFIFO_SHIFT) - -/* Bitfield definition for register array: RXWRD */ -/* - * RXFIFO (RO) - * - * RXFIFO for receiving message from other core, FIFO size, 4x32 - * can read one of the word address to pop data to the FIFO; - * can also use 4x32 burst read from 0x020 to read 4 words from the FIFO. - */ -#define MBX_RXWRD_RXFIFO_MASK (0xFFFFFFFFUL) -#define MBX_RXWRD_RXFIFO_SHIFT (0U) -#define MBX_RXWRD_RXFIFO_GET(x) (((uint32_t)(x) & MBX_RXWRD_RXFIFO_MASK) >> MBX_RXWRD_RXFIFO_SHIFT) - - - -/* TXWRD register group index macro definition */ -#define MBX_TXWRD_TXFIFO0 (0UL) - -/* RXWRD register group index macro definition */ -#define MBX_RXWRD_RXFIFO0 (0UL) - - -#endif /* HPM_MBX_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mcan_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mcan_regs.h deleted file mode 100644 index 0b0c83d3e77..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mcan_regs.h +++ /dev/null @@ -1,2951 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCAN_H -#define HPM_MCAN_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __R uint32_t ENDN; /* 0x4: endian register */ - __R uint8_t RESERVED1[4]; /* 0x8 - 0xB: Reserved */ - __RW uint32_t DBTP; /* 0xC: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set */ - __RW uint32_t TEST; /* 0x10: test register */ - __RW uint32_t RWD; /* 0x14: ram watchdog */ - __RW uint32_t CCCR; /* 0x18: CC control register */ - __RW uint32_t NBTP; /* 0x1C: nominal bit timing and prescaler register */ - __RW uint32_t TSCC; /* 0x20: timestamp counter configuration */ - __R uint32_t TSCV; /* 0x24: timestamp counter value */ - __RW uint32_t TOCC; /* 0x28: timeout counter configuration */ - __R uint32_t TOCV; /* 0x2C: timeout counter value */ - __R uint8_t RESERVED2[16]; /* 0x30 - 0x3F: Reserved */ - __R uint32_t ECR; /* 0x40: error counter register */ - __R uint32_t PSR; /* 0x44: protocol status register */ - __RW uint32_t TDCR; /* 0x48: transmitter delay compensation */ - __R uint8_t RESERVED3[4]; /* 0x4C - 0x4F: Reserved */ - __RW uint32_t IR; /* 0x50: interrupt register */ - __RW uint32_t IE; /* 0x54: interrupt enable */ - __RW uint32_t ILS; /* 0x58: interrupt line select */ - __RW uint32_t ILE; /* 0x5C: interrupt line enable */ - __R uint8_t RESERVED4[32]; /* 0x60 - 0x7F: Reserved */ - __RW uint32_t GFC; /* 0x80: global filter configuration */ - __RW uint32_t SIDFC; /* 0x84: standard ID filter configuration */ - __RW uint32_t XIDFC; /* 0x88: extended ID filter configuration */ - __R uint8_t RESERVED5[4]; /* 0x8C - 0x8F: Reserved */ - __RW uint32_t XIDAM; /* 0x90: extended id and mask */ - __R uint32_t HPMS; /* 0x94: high priority message status */ - __RW uint32_t NDAT1; /* 0x98: new data1 */ - __RW uint32_t NDAT2; /* 0x9C: new data2 */ - __RW uint32_t RXF0C; /* 0xA0: rx fifo 0 configuration */ - __R uint32_t RXF0S; /* 0xA4: rx fifo 0 status */ - __RW uint32_t RXF0A; /* 0xA8: rx fifo0 acknowledge */ - __RW uint32_t RXBC; /* 0xAC: rx buffer configuration */ - __RW uint32_t RXF1C; /* 0xB0: rx fifo1 configuration */ - __R uint32_t RXF1S; /* 0xB4: rx fifo1 status */ - __RW uint32_t RXF1A; /* 0xB8: rx fifo 1 acknowledge */ - __RW uint32_t RXESC; /* 0xBC: rx buffer/fifo element size configuration */ - __RW uint32_t TXBC; /* 0xC0: tx buffer configuration */ - __R uint32_t TXFQS; /* 0xC4: tx fifo/queue status */ - __RW uint32_t TXESC; /* 0xC8: tx buffer element size configuration */ - __R uint32_t TXBRP; /* 0xCC: tx buffer request pending */ - __RW uint32_t TXBAR; /* 0xD0: tx buffer add request */ - __RW uint32_t TXBCR; /* 0xD4: tx buffer cancellation request */ - __R uint32_t TXBTO; /* 0xD8: tx buffer transmission occurred */ - __R uint32_t TXBCF; /* 0xDC: tx buffer cancellation finished */ - __RW uint32_t TXBTIE; /* 0xE0: tx buffer transmission interrupt enable */ - __RW uint32_t TXBCIE; /* 0xE4: tx buffer cancellation finished interrupt enable */ - __R uint8_t RESERVED6[8]; /* 0xE8 - 0xEF: Reserved */ - __RW uint32_t TXEFC; /* 0xF0: tx event fifo configuration */ - __R uint32_t TXEFS; /* 0xF4: tx event fifo status */ - __RW uint32_t TXEFA; /* 0xF8: tx event fifo acknowledge */ - __R uint8_t RESERVED7[260]; /* 0xFC - 0x1FF: Reserved */ - __R uint32_t TS_SEL[16]; /* 0x200 - 0x23C: timestamp 0 */ - __R uint32_t CREL; /* 0x240: core release register */ - __RW uint32_t TSCFG; /* 0x244: timestamp configuration */ - __R uint32_t TSS1; /* 0x248: timestamp status1 */ - __R uint32_t TSS2; /* 0x24C: timestamp status2 */ - __R uint32_t ATB; /* 0x250: actual timebase */ - __R uint32_t ATBH; /* 0x254: actual timebase high */ - __R uint8_t RESERVED8[424]; /* 0x258 - 0x3FF: Reserved */ - __RW uint32_t GLB_CTL; /* 0x400: global control */ - __R uint32_t GLB_STATUS; /* 0x404: global status */ - __R uint8_t RESERVED9[4]; /* 0x408 - 0x40B: Reserved */ -} MCAN_Type; - - -/* Bitfield definition for register: ENDN */ -/* - * EVT (R) - * - * Endianness Test Value - * The endianness test value is 0x87654321. - */ -#define MCAN_ENDN_EVT_MASK (0xFFFFFFFFUL) -#define MCAN_ENDN_EVT_SHIFT (0U) -#define MCAN_ENDN_EVT_GET(x) (((uint32_t)(x) & MCAN_ENDN_EVT_MASK) >> MCAN_ENDN_EVT_SHIFT) - -/* Bitfield definition for register: DBTP */ -/* - * TDC (RW) - * - * transmitter delay compensation enable - * 0= Transmitter Delay Compensation disabled - * 1= Transmitter Delay Compensation enabled - */ -#define MCAN_DBTP_TDC_MASK (0x800000UL) -#define MCAN_DBTP_TDC_SHIFT (23U) -#define MCAN_DBTP_TDC_SET(x) (((uint32_t)(x) << MCAN_DBTP_TDC_SHIFT) & MCAN_DBTP_TDC_MASK) -#define MCAN_DBTP_TDC_GET(x) (((uint32_t)(x) & MCAN_DBTP_TDC_MASK) >> MCAN_DBTP_TDC_SHIFT) - -/* - * DBRP (RW) - * - * Data Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 31. - * When TDC = ‘1’, the range is limited to 0,1. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DBRP_MASK (0x1F0000UL) -#define MCAN_DBTP_DBRP_SHIFT (16U) -#define MCAN_DBTP_DBRP_SET(x) (((uint32_t)(x) << MCAN_DBTP_DBRP_SHIFT) & MCAN_DBTP_DBRP_MASK) -#define MCAN_DBTP_DBRP_GET(x) (((uint32_t)(x) & MCAN_DBTP_DBRP_MASK) >> MCAN_DBTP_DBRP_SHIFT) - -/* - * DTSEG1 (RW) - * - * Data time segment before sample point - * Valid values are 0 to 31. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG1_MASK (0x1F00U) -#define MCAN_DBTP_DTSEG1_SHIFT (8U) -#define MCAN_DBTP_DTSEG1_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG1_SHIFT) & MCAN_DBTP_DTSEG1_MASK) -#define MCAN_DBTP_DTSEG1_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG1_MASK) >> MCAN_DBTP_DTSEG1_SHIFT) - -/* - * DTSEG2 (RW) - * - * Data time segment after sample point - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_DBTP_DTSEG2_MASK (0xF0U) -#define MCAN_DBTP_DTSEG2_SHIFT (4U) -#define MCAN_DBTP_DTSEG2_SET(x) (((uint32_t)(x) << MCAN_DBTP_DTSEG2_SHIFT) & MCAN_DBTP_DTSEG2_MASK) -#define MCAN_DBTP_DTSEG2_GET(x) (((uint32_t)(x) & MCAN_DBTP_DTSEG2_MASK) >> MCAN_DBTP_DTSEG2_SHIFT) - -/* - * DSJW (RW) - * - * Data (Re)Synchronization Jump Width - * Valid values are 0 to 15. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_DBTP_DSJW_MASK (0xFU) -#define MCAN_DBTP_DSJW_SHIFT (0U) -#define MCAN_DBTP_DSJW_SET(x) (((uint32_t)(x) << MCAN_DBTP_DSJW_SHIFT) & MCAN_DBTP_DSJW_MASK) -#define MCAN_DBTP_DSJW_GET(x) (((uint32_t)(x) & MCAN_DBTP_DSJW_MASK) >> MCAN_DBTP_DSJW_SHIFT) - -/* Bitfield definition for register: TEST */ -/* - * SVAL (R) - * - * Started Valid - * 0= Value of TXBNS not valid - * 1= Value of TXBNS valid - */ -#define MCAN_TEST_SVAL_MASK (0x200000UL) -#define MCAN_TEST_SVAL_SHIFT (21U) -#define MCAN_TEST_SVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_SVAL_MASK) >> MCAN_TEST_SVAL_SHIFT) - -/* - * TXBNS (R) - * - * Tx Buffer Number Started - * Tx Buffer number of message whose transmission was started last. Valid when SVAL is set. Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNS_MASK (0x1F0000UL) -#define MCAN_TEST_TXBNS_SHIFT (16U) -#define MCAN_TEST_TXBNS_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNS_MASK) >> MCAN_TEST_TXBNS_SHIFT) - -/* - * PVAL (R) - * - * Prepared Valid - * 0= Value of TXBNP not valid - * 1= Value of TXBNP valid - */ -#define MCAN_TEST_PVAL_MASK (0x2000U) -#define MCAN_TEST_PVAL_SHIFT (13U) -#define MCAN_TEST_PVAL_GET(x) (((uint32_t)(x) & MCAN_TEST_PVAL_MASK) >> MCAN_TEST_PVAL_SHIFT) - -/* - * TXBNP (R) - * - * Tx Buffer Number Prepared - * Tx Buffer number of message that is ready for transmission. Valid when PVAL is set.Valid values are 0 to 31. - */ -#define MCAN_TEST_TXBNP_MASK (0x1F00U) -#define MCAN_TEST_TXBNP_SHIFT (8U) -#define MCAN_TEST_TXBNP_GET(x) (((uint32_t)(x) & MCAN_TEST_TXBNP_MASK) >> MCAN_TEST_TXBNP_SHIFT) - -/* - * RX (R) - * - * Receive Pin - * Monitors the actual value of pin m_can_rx - * 0= The CAN bus is dominant (m_can_rx = ‘0’) - * 1= The CAN bus is recessive (m_can_rx = ‘1’) - */ -#define MCAN_TEST_RX_MASK (0x80U) -#define MCAN_TEST_RX_SHIFT (7U) -#define MCAN_TEST_RX_GET(x) (((uint32_t)(x) & MCAN_TEST_RX_MASK) >> MCAN_TEST_RX_SHIFT) - -/* - * TX (RW) - * - * Control of Transmit Pin - * 00 Reset value, m_can_tx controlled by the CAN Core, updated at the end of the CAN bit time - * 01 Sample Point can be monitored at pin m_can_tx - * 10 Dominant (‘0’) level at pin m_can_tx - * 11 Recessive (‘1’) at pin m_can_tx - */ -#define MCAN_TEST_TX_MASK (0x60U) -#define MCAN_TEST_TX_SHIFT (5U) -#define MCAN_TEST_TX_SET(x) (((uint32_t)(x) << MCAN_TEST_TX_SHIFT) & MCAN_TEST_TX_MASK) -#define MCAN_TEST_TX_GET(x) (((uint32_t)(x) & MCAN_TEST_TX_MASK) >> MCAN_TEST_TX_SHIFT) - -/* - * LBCK (RW) - * - * Loop Back Mode - * 0= Reset value, Loop Back Mode is disabled - * 1= Loop Back Mode is enabled - */ -#define MCAN_TEST_LBCK_MASK (0x10U) -#define MCAN_TEST_LBCK_SHIFT (4U) -#define MCAN_TEST_LBCK_SET(x) (((uint32_t)(x) << MCAN_TEST_LBCK_SHIFT) & MCAN_TEST_LBCK_MASK) -#define MCAN_TEST_LBCK_GET(x) (((uint32_t)(x) & MCAN_TEST_LBCK_MASK) >> MCAN_TEST_LBCK_SHIFT) - -/* Bitfield definition for register: RWD */ -/* - * WDV (R) - * - * Watchdog Value - * Actual Message RAM Watchdog Counter Value. - */ -#define MCAN_RWD_WDV_MASK (0xFF00U) -#define MCAN_RWD_WDV_SHIFT (8U) -#define MCAN_RWD_WDV_GET(x) (((uint32_t)(x) & MCAN_RWD_WDV_MASK) >> MCAN_RWD_WDV_SHIFT) - -/* - * WDC (RW) - * - * Watchdog Configuration - * Start value of the Message RAM Watchdog Counter. With the reset value of “00” the counter is disabled. - */ -#define MCAN_RWD_WDC_MASK (0xFFU) -#define MCAN_RWD_WDC_SHIFT (0U) -#define MCAN_RWD_WDC_SET(x) (((uint32_t)(x) << MCAN_RWD_WDC_SHIFT) & MCAN_RWD_WDC_MASK) -#define MCAN_RWD_WDC_GET(x) (((uint32_t)(x) & MCAN_RWD_WDC_MASK) >> MCAN_RWD_WDC_SHIFT) - -/* Bitfield definition for register: CCCR */ -/* - * NISO (RW) - * - * Non ISO Operation - * If this bit is set, the M_CAN uses the CAN FD frame format as specified by the Bosch CAN FD - * Specification V1.0. - * 0= CAN FD frame format according to ISO 11898-1:2015 - * 1= CAN FD frame format according to Bosch CAN FD Specification V1.0 - * Note: When the generic parameter iso_only_g is set to ‘1’ in hardware synthesis, this bit becomes reserved and is read as ‘0’. The M_CAN always operates with the CAN FD frame format according to ISO 11898-1:2015. - */ -#define MCAN_CCCR_NISO_MASK (0x8000U) -#define MCAN_CCCR_NISO_SHIFT (15U) -#define MCAN_CCCR_NISO_SET(x) (((uint32_t)(x) << MCAN_CCCR_NISO_SHIFT) & MCAN_CCCR_NISO_MASK) -#define MCAN_CCCR_NISO_GET(x) (((uint32_t)(x) & MCAN_CCCR_NISO_MASK) >> MCAN_CCCR_NISO_SHIFT) - -/* - * TXP (RW) - * - * Transmit Pause - * If this bit is set, the M_CAN pauses for two CAN bit times before starting the next transmission after - * itself has successfully transmitted a frame (see Section 3.5). - * 0= Transmit pause disabled - * 1= Transmit pause enabled - */ -#define MCAN_CCCR_TXP_MASK (0x4000U) -#define MCAN_CCCR_TXP_SHIFT (14U) -#define MCAN_CCCR_TXP_SET(x) (((uint32_t)(x) << MCAN_CCCR_TXP_SHIFT) & MCAN_CCCR_TXP_MASK) -#define MCAN_CCCR_TXP_GET(x) (((uint32_t)(x) & MCAN_CCCR_TXP_MASK) >> MCAN_CCCR_TXP_SHIFT) - -/* - * EFBI (RW) - * - * Edge Filtering during Bus Integration - * 0= Edge filtering disabled - * 1= Two consecutive dominant tq required to detect an edge for hard synchronization - */ -#define MCAN_CCCR_EFBI_MASK (0x2000U) -#define MCAN_CCCR_EFBI_SHIFT (13U) -#define MCAN_CCCR_EFBI_SET(x) (((uint32_t)(x) << MCAN_CCCR_EFBI_SHIFT) & MCAN_CCCR_EFBI_MASK) -#define MCAN_CCCR_EFBI_GET(x) (((uint32_t)(x) & MCAN_CCCR_EFBI_MASK) >> MCAN_CCCR_EFBI_SHIFT) - -/* - * PXHD (RW) - * - * Protocol Exception Handling Disable - * 0= Protocol exception handling enabled - * 1= Protocol exception handling disabled - * Note: When protocol exception handling is disabled, the M_CAN will transmit an error frame when it detects a protocol exception condition. - */ -#define MCAN_CCCR_PXHD_MASK (0x1000U) -#define MCAN_CCCR_PXHD_SHIFT (12U) -#define MCAN_CCCR_PXHD_SET(x) (((uint32_t)(x) << MCAN_CCCR_PXHD_SHIFT) & MCAN_CCCR_PXHD_MASK) -#define MCAN_CCCR_PXHD_GET(x) (((uint32_t)(x) & MCAN_CCCR_PXHD_MASK) >> MCAN_CCCR_PXHD_SHIFT) - -/* - * WMM (RW) - * - * Wide Message Marker - * Enables the use of 16-bit Wide Message Markers. When 16-bit Wide Message Markers are used (WMM = ‘1’), 16-bit internal timestamping is disabled for the Tx Event FIFO. - * 0= 8-bit Message Marker used - * 1= 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO - */ -#define MCAN_CCCR_WMM_MASK (0x800U) -#define MCAN_CCCR_WMM_SHIFT (11U) -#define MCAN_CCCR_WMM_SET(x) (((uint32_t)(x) << MCAN_CCCR_WMM_SHIFT) & MCAN_CCCR_WMM_MASK) -#define MCAN_CCCR_WMM_GET(x) (((uint32_t)(x) & MCAN_CCCR_WMM_MASK) >> MCAN_CCCR_WMM_SHIFT) - -/* - * UTSU (RW) - * - * Use Timestamping Unit - * When UTSU is set, 16-bit Wide Message Markers are also enabled regardless of the value of WMM. - * 0= Internal time stamping - * 1= External time stamping by TSU - * Note: When generic parameter connected_tsu_g = ‘0’, there is no TSU connected to the M_CAN. - * In this case bit UTSU is fixed to zero by synthesis. - */ -#define MCAN_CCCR_UTSU_MASK (0x400U) -#define MCAN_CCCR_UTSU_SHIFT (10U) -#define MCAN_CCCR_UTSU_SET(x) (((uint32_t)(x) << MCAN_CCCR_UTSU_SHIFT) & MCAN_CCCR_UTSU_MASK) -#define MCAN_CCCR_UTSU_GET(x) (((uint32_t)(x) & MCAN_CCCR_UTSU_MASK) >> MCAN_CCCR_UTSU_SHIFT) - -/* - * BRSE (RW) - * - * Bit Rate Switch Enable - * 0= Bit rate switching for transmissions disabled - * 1= Bit rate switching for transmissions enabled - * Note: When CAN FD operation is disabled FDOE = ‘0’, BRSE is not evaluated. - */ -#define MCAN_CCCR_BRSE_MASK (0x200U) -#define MCAN_CCCR_BRSE_SHIFT (9U) -#define MCAN_CCCR_BRSE_SET(x) (((uint32_t)(x) << MCAN_CCCR_BRSE_SHIFT) & MCAN_CCCR_BRSE_MASK) -#define MCAN_CCCR_BRSE_GET(x) (((uint32_t)(x) & MCAN_CCCR_BRSE_MASK) >> MCAN_CCCR_BRSE_SHIFT) - -/* - * FDOE (RW) - * - * FD Operation Enable - * 0= FD operation disabled - * 1= FD operation enabled - */ -#define MCAN_CCCR_FDOE_MASK (0x100U) -#define MCAN_CCCR_FDOE_SHIFT (8U) -#define MCAN_CCCR_FDOE_SET(x) (((uint32_t)(x) << MCAN_CCCR_FDOE_SHIFT) & MCAN_CCCR_FDOE_MASK) -#define MCAN_CCCR_FDOE_GET(x) (((uint32_t)(x) & MCAN_CCCR_FDOE_MASK) >> MCAN_CCCR_FDOE_SHIFT) - -/* - * TEST (RW) - * - * Test Mode Enable - * 0= Normal operation, register TEST holds reset values - * 1= Test Mode, write access to register TEST enabled - */ -#define MCAN_CCCR_TEST_MASK (0x80U) -#define MCAN_CCCR_TEST_SHIFT (7U) -#define MCAN_CCCR_TEST_SET(x) (((uint32_t)(x) << MCAN_CCCR_TEST_SHIFT) & MCAN_CCCR_TEST_MASK) -#define MCAN_CCCR_TEST_GET(x) (((uint32_t)(x) & MCAN_CCCR_TEST_MASK) >> MCAN_CCCR_TEST_SHIFT) - -/* - * DAR (RW) - * - * Disable Automatic Retransmission - * 0= Automatic retransmission of messages not transmitted successfully enabled - * 1= Automatic retransmission disabled - */ -#define MCAN_CCCR_DAR_MASK (0x40U) -#define MCAN_CCCR_DAR_SHIFT (6U) -#define MCAN_CCCR_DAR_SET(x) (((uint32_t)(x) << MCAN_CCCR_DAR_SHIFT) & MCAN_CCCR_DAR_MASK) -#define MCAN_CCCR_DAR_GET(x) (((uint32_t)(x) & MCAN_CCCR_DAR_MASK) >> MCAN_CCCR_DAR_SHIFT) - -/* - * MON (RW) - * - * Bus Monitoring Mode - * Bit MON can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. - * 0= Bus Monitoring Mode is disabled - * 1= Bus Monitoring Mode is enabled - */ -#define MCAN_CCCR_MON_MASK (0x20U) -#define MCAN_CCCR_MON_SHIFT (5U) -#define MCAN_CCCR_MON_SET(x) (((uint32_t)(x) << MCAN_CCCR_MON_SHIFT) & MCAN_CCCR_MON_MASK) -#define MCAN_CCCR_MON_GET(x) (((uint32_t)(x) & MCAN_CCCR_MON_MASK) >> MCAN_CCCR_MON_SHIFT) - -/* - * CSR (RW) - * - * Clock Stop Request - * 0= No clock stop is requested - * 1= Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pending transfer requests have been completed and the CAN bus reached idle. - */ -#define MCAN_CCCR_CSR_MASK (0x10U) -#define MCAN_CCCR_CSR_SHIFT (4U) -#define MCAN_CCCR_CSR_SET(x) (((uint32_t)(x) << MCAN_CCCR_CSR_SHIFT) & MCAN_CCCR_CSR_MASK) -#define MCAN_CCCR_CSR_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSR_MASK) >> MCAN_CCCR_CSR_SHIFT) - -/* - * CSA (R) - * - * Clock Stop Acknowledge - * 0= No clock stop acknowledged - * 1= M_CAN may be set in power down by stopping m_can_hclk and m_can_cclk - */ -#define MCAN_CCCR_CSA_MASK (0x8U) -#define MCAN_CCCR_CSA_SHIFT (3U) -#define MCAN_CCCR_CSA_GET(x) (((uint32_t)(x) & MCAN_CCCR_CSA_MASK) >> MCAN_CCCR_CSA_SHIFT) - -/* - * ASM (RW) - * - * Restricted Operation Mode - * Bit ASM can only be set by the Host when both CCE and INIT are set to ‘1’. The bit can be reset by the Host at any time. For a description of the Restricted Operation Mode see Section 3.1.5. - * 0= Normal CAN operation - * 1= Restricted Operation Mode active - */ -#define MCAN_CCCR_ASM_MASK (0x4U) -#define MCAN_CCCR_ASM_SHIFT (2U) -#define MCAN_CCCR_ASM_SET(x) (((uint32_t)(x) << MCAN_CCCR_ASM_SHIFT) & MCAN_CCCR_ASM_MASK) -#define MCAN_CCCR_ASM_GET(x) (((uint32_t)(x) & MCAN_CCCR_ASM_MASK) >> MCAN_CCCR_ASM_SHIFT) - -/* - * CCE (RW) - * - * Configuration Change Enable - * 0= The CPU has no write access to the protected configuration registers - * 1= The CPU has write access to the protected configuration registers (while CCCR.INIT = ‘1’) - */ -#define MCAN_CCCR_CCE_MASK (0x2U) -#define MCAN_CCCR_CCE_SHIFT (1U) -#define MCAN_CCCR_CCE_SET(x) (((uint32_t)(x) << MCAN_CCCR_CCE_SHIFT) & MCAN_CCCR_CCE_MASK) -#define MCAN_CCCR_CCE_GET(x) (((uint32_t)(x) & MCAN_CCCR_CCE_MASK) >> MCAN_CCCR_CCE_SHIFT) - -/* - * INIT (RW) - * - * Initialization - * 0= Normal Operation - * 1= Initialization is started - */ -#define MCAN_CCCR_INIT_MASK (0x1U) -#define MCAN_CCCR_INIT_SHIFT (0U) -#define MCAN_CCCR_INIT_SET(x) (((uint32_t)(x) << MCAN_CCCR_INIT_SHIFT) & MCAN_CCCR_INIT_MASK) -#define MCAN_CCCR_INIT_GET(x) (((uint32_t)(x) & MCAN_CCCR_INIT_MASK) >> MCAN_CCCR_INIT_SHIFT) - -/* Bitfield definition for register: NBTP */ -/* - * NSJW (RW) - * - * Nominal (Re)Synchronization Jump Width - * Valid values are 0 to 127. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NSJW_MASK (0xFE000000UL) -#define MCAN_NBTP_NSJW_SHIFT (25U) -#define MCAN_NBTP_NSJW_SET(x) (((uint32_t)(x) << MCAN_NBTP_NSJW_SHIFT) & MCAN_NBTP_NSJW_MASK) -#define MCAN_NBTP_NSJW_GET(x) (((uint32_t)(x) & MCAN_NBTP_NSJW_MASK) >> MCAN_NBTP_NSJW_SHIFT) - -/* - * NBRP (RW) - * - * Nominal Bit Rate Prescaler - * The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Bit Rate Prescaler are 0 to 511. The actual interpretation by the hardware of this value is - * such that one more than the value programmed here is used. - */ -#define MCAN_NBTP_NBRP_MASK (0x1FF0000UL) -#define MCAN_NBTP_NBRP_SHIFT (16U) -#define MCAN_NBTP_NBRP_SET(x) (((uint32_t)(x) << MCAN_NBTP_NBRP_SHIFT) & MCAN_NBTP_NBRP_MASK) -#define MCAN_NBTP_NBRP_GET(x) (((uint32_t)(x) & MCAN_NBTP_NBRP_MASK) >> MCAN_NBTP_NBRP_SHIFT) - -/* - * NTSEG1 (RW) - * - * Nominal Time segment before sample point - * Valid values are 1 to 255. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG1_MASK (0xFF00U) -#define MCAN_NBTP_NTSEG1_SHIFT (8U) -#define MCAN_NBTP_NTSEG1_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG1_SHIFT) & MCAN_NBTP_NTSEG1_MASK) -#define MCAN_NBTP_NTSEG1_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG1_MASK) >> MCAN_NBTP_NTSEG1_SHIFT) - -/* - * NTSEG2 (RW) - * - * Nominal Time segment after sample point - * Valid values are 1 to 127. The actual interpretation by the hardware of this value is such that one more than the programmed value is used. - */ -#define MCAN_NBTP_NTSEG2_MASK (0x7FU) -#define MCAN_NBTP_NTSEG2_SHIFT (0U) -#define MCAN_NBTP_NTSEG2_SET(x) (((uint32_t)(x) << MCAN_NBTP_NTSEG2_SHIFT) & MCAN_NBTP_NTSEG2_MASK) -#define MCAN_NBTP_NTSEG2_GET(x) (((uint32_t)(x) & MCAN_NBTP_NTSEG2_MASK) >> MCAN_NBTP_NTSEG2_SHIFT) - -/* Bitfield definition for register: TSCC */ -/* - * TCP (RW) - * - * Timestamp Counter Prescaler - * Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1…16]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. - */ -#define MCAN_TSCC_TCP_MASK (0xF0000UL) -#define MCAN_TSCC_TCP_SHIFT (16U) -#define MCAN_TSCC_TCP_SET(x) (((uint32_t)(x) << MCAN_TSCC_TCP_SHIFT) & MCAN_TSCC_TCP_MASK) -#define MCAN_TSCC_TCP_GET(x) (((uint32_t)(x) & MCAN_TSCC_TCP_MASK) >> MCAN_TSCC_TCP_SHIFT) - -/* - * TSS (RW) - * - * timestamp Select - * 00= Timestamp counter value always 0x0000 - * 01= Timestamp counter value incremented according to TCP - * 10= External timestamp counter value used - * 11= Same as “00” - */ -#define MCAN_TSCC_TSS_MASK (0x3U) -#define MCAN_TSCC_TSS_SHIFT (0U) -#define MCAN_TSCC_TSS_SET(x) (((uint32_t)(x) << MCAN_TSCC_TSS_SHIFT) & MCAN_TSCC_TSS_MASK) -#define MCAN_TSCC_TSS_GET(x) (((uint32_t)(x) & MCAN_TSCC_TSS_MASK) >> MCAN_TSCC_TSS_SHIFT) - -/* Bitfield definition for register: TSCV */ -/* - * TSC (RC) - * - * Timestamp Counter - * The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx).When TSCC.TSS = “01”, the Timestamp Counter is incremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * A wrap around sets interrupt flag IR.TSW. Write access resets the counter to zero. When TSCC.TSS = “10”, TSC reflects the external Timestamp Counter value. A write access has no impact. - */ -#define MCAN_TSCV_TSC_MASK (0xFFFFU) -#define MCAN_TSCV_TSC_SHIFT (0U) -#define MCAN_TSCV_TSC_GET(x) (((uint32_t)(x) & MCAN_TSCV_TSC_MASK) >> MCAN_TSCV_TSC_SHIFT) - -/* Bitfield definition for register: TOCC */ -/* - * TOP (RW) - * - * Timeout Period - * Start value of the Timeout Counter (down-counter). Configures the Timeout Period. - */ -#define MCAN_TOCC_TOP_MASK (0xFFFF0000UL) -#define MCAN_TOCC_TOP_SHIFT (16U) -#define MCAN_TOCC_TOP_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOP_SHIFT) & MCAN_TOCC_TOP_MASK) -#define MCAN_TOCC_TOP_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOP_MASK) >> MCAN_TOCC_TOP_SHIFT) - -/* - * TOS (RW) - * - * Timeout Select - * When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting. - * When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC.TOP. Down-counting is started when the first FIFO element is stored. - * 00= Continuous operation - * 01= Timeout controlled by Tx Event FIFO - * 10= Timeout controlled by Rx FIFO 0 - * 11= Timeout controlled by Rx FIFO 1 - */ -#define MCAN_TOCC_TOS_MASK (0x6U) -#define MCAN_TOCC_TOS_SHIFT (1U) -#define MCAN_TOCC_TOS_SET(x) (((uint32_t)(x) << MCAN_TOCC_TOS_SHIFT) & MCAN_TOCC_TOS_MASK) -#define MCAN_TOCC_TOS_GET(x) (((uint32_t)(x) & MCAN_TOCC_TOS_MASK) >> MCAN_TOCC_TOS_SHIFT) - -/* - * RP (RW) - * - * Enable Timeout Counter - * 0= Timeout Counter disabled - * 1= Timeout Counter enabled - */ -#define MCAN_TOCC_RP_MASK (0x1U) -#define MCAN_TOCC_RP_SHIFT (0U) -#define MCAN_TOCC_RP_SET(x) (((uint32_t)(x) << MCAN_TOCC_RP_SHIFT) & MCAN_TOCC_RP_MASK) -#define MCAN_TOCC_RP_GET(x) (((uint32_t)(x) & MCAN_TOCC_RP_MASK) >> MCAN_TOCC_RP_SHIFT) - -/* Bitfield definition for register: TOCV */ -/* - * TOC (RC) - * - * Timeout Counter - * The Timeout Counter is decremented in multiples of CAN bit times [1…16] depending on the configuration of TSCC.TCP. - * When decremented to zero, interrupt flag IR.TOO is set and the Timeout Counter is stopped. Start and reset/restart conditions are configured via TOCC.TOS. - * Note: Byte access: when TOCC.TOS = “00，writing one of the register bytes 3/2/1/0 will preset the Timeout Counter. - */ -#define MCAN_TOCV_TOC_MASK (0xFFFFU) -#define MCAN_TOCV_TOC_SHIFT (0U) -#define MCAN_TOCV_TOC_GET(x) (((uint32_t)(x) & MCAN_TOCV_TOC_MASK) >> MCAN_TOCV_TOC_SHIFT) - -/* Bitfield definition for register: ECR */ -/* - * CEL (X) - * - * CAN Error Logging - * The counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented. - * The counter is also incremented when the Bus_Off limit is reached. It is not incremented when only RP is set without changing REC. The increment of CEL follows after the increment of REC or TEC. - * The counter is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR.ELO. - * Note: Byte access: Reading byte 2 will reset CEL to zero, reading bytes 3/1/0 has no impact. - */ -#define MCAN_ECR_CEL_MASK (0xFF0000UL) -#define MCAN_ECR_CEL_SHIFT (16U) -#define MCAN_ECR_CEL_GET(x) (((uint32_t)(x) & MCAN_ECR_CEL_MASK) >> MCAN_ECR_CEL_SHIFT) - -/* - * RP (R) - * - * Receive Error Passive - * 0= The Receive Error Counter is below the error passive level of 128 - * 1= The Receive Error Counter has reached the error passive level of 128 - */ -#define MCAN_ECR_RP_MASK (0x8000U) -#define MCAN_ECR_RP_SHIFT (15U) -#define MCAN_ECR_RP_GET(x) (((uint32_t)(x) & MCAN_ECR_RP_MASK) >> MCAN_ECR_RP_SHIFT) - -/* - * REC (R) - * - * Receive Error Counter - * Actual state of the Receive Error Counter, values between 0 and 127 - */ -#define MCAN_ECR_REC_MASK (0x7F00U) -#define MCAN_ECR_REC_SHIFT (8U) -#define MCAN_ECR_REC_GET(x) (((uint32_t)(x) & MCAN_ECR_REC_MASK) >> MCAN_ECR_REC_SHIFT) - -/* - * TEC (R) - * - * Transmit Error Counter - * Actual state of the Transmit Error Counter, values between 0 and 255 - * Note: When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented. - */ -#define MCAN_ECR_TEC_MASK (0xFFU) -#define MCAN_ECR_TEC_SHIFT (0U) -#define MCAN_ECR_TEC_GET(x) (((uint32_t)(x) & MCAN_ECR_TEC_MASK) >> MCAN_ECR_TEC_SHIFT) - -/* Bitfield definition for register: PSR */ -/* - * TDCV (R) - * - * Transmitter Delay Compensation Value - * Position of the secondary sample point, defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO. - * The SSP position is, in the data phase, the number of mtq between the start of the transmitted bit and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_PSR_TDCV_MASK (0x7F0000UL) -#define MCAN_PSR_TDCV_SHIFT (16U) -#define MCAN_PSR_TDCV_GET(x) (((uint32_t)(x) & MCAN_PSR_TDCV_MASK) >> MCAN_PSR_TDCV_SHIFT) - -/* - * PXE (X) - * - * Protocol Exception Event - * 0= No protocol exception event occurred since last read access - * 1= Protocol exception event occurred - * Note: Byte access: Reading byte 0 will reset PXE, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_PXE_MASK (0x4000U) -#define MCAN_PSR_PXE_SHIFT (14U) -#define MCAN_PSR_PXE_GET(x) (((uint32_t)(x) & MCAN_PSR_PXE_MASK) >> MCAN_PSR_PXE_SHIFT) - -/* - * RFDF (X) - * - * Received a CAN FD Message - * This bit is set independent of acceptance filtering. - * 0= Since this bit was reset by the CPU, no CAN FD message has been received - * 1= Message in CAN FD format with FDF flag set has been received - * Note: Byte access: Reading byte 0 will reset RFDF, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RFDF_MASK (0x2000U) -#define MCAN_PSR_RFDF_SHIFT (13U) -#define MCAN_PSR_RFDF_GET(x) (((uint32_t)(x) & MCAN_PSR_RFDF_MASK) >> MCAN_PSR_RFDF_SHIFT) - -/* - * RBRS (X) - * - * BRS flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its BRS flag set - * 1= Last received CAN FD message had its BRS flag set - * Note: Byte access: Reading byte 0 will reset RBRS, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RBRS_MASK (0x1000U) -#define MCAN_PSR_RBRS_SHIFT (12U) -#define MCAN_PSR_RBRS_GET(x) (((uint32_t)(x) & MCAN_PSR_RBRS_MASK) >> MCAN_PSR_RBRS_SHIFT) - -/* - * RESI (X) - * - * ESI flag of last received CAN FD Message - * This bit is set together with RFDF, independent of acceptance filtering. - * 0= Last received CAN FD message did not have its ESI flag set - * 1= Last received CAN FD message had its ESI flag set - * Note: Byte access: Reading byte 0 will reset RESI, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_RESI_MASK (0x800U) -#define MCAN_PSR_RESI_SHIFT (11U) -#define MCAN_PSR_RESI_GET(x) (((uint32_t)(x) & MCAN_PSR_RESI_MASK) >> MCAN_PSR_RESI_SHIFT) - -/* - * DLEC (S) - * - * Data Phase Last Error Code - * Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set.Coding is the same as for LEC. This field will be cleared to zero when a CAN FD format frame with - * its BRS flag set has been transferred (reception or transmission) without error. - * Note: Byte access: Reading byte 0 will set DLEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_DLEC_MASK (0x700U) -#define MCAN_PSR_DLEC_SHIFT (8U) -#define MCAN_PSR_DLEC_GET(x) (((uint32_t)(x) & MCAN_PSR_DLEC_MASK) >> MCAN_PSR_DLEC_SHIFT) - -/* - * BO (R) - * - * Bus_Off Status - * 0= The M_CAN is not Bus_Off - * 1= The M_CAN is in Bus_Off state - */ -#define MCAN_PSR_BO_MASK (0x80U) -#define MCAN_PSR_BO_SHIFT (7U) -#define MCAN_PSR_BO_GET(x) (((uint32_t)(x) & MCAN_PSR_BO_MASK) >> MCAN_PSR_BO_SHIFT) - -/* - * EW (R) - * - * Warning Status - * 0= Both error counters are below the Error_Warning limit of 96 - * 1= At least one of error counter has reached the Error_Warning limit of 96 - */ -#define MCAN_PSR_EW_MASK (0x40U) -#define MCAN_PSR_EW_SHIFT (6U) -#define MCAN_PSR_EW_GET(x) (((uint32_t)(x) & MCAN_PSR_EW_MASK) >> MCAN_PSR_EW_SHIFT) - -/* - * EP (R) - * - * Error Passive - * 0= The M_CAN is in the Error_Active state. It normally takes part in bus communication and sends an active error flag when an error has been detected - * 1= The M_CAN is in the Error_Passive state - */ -#define MCAN_PSR_EP_MASK (0x20U) -#define MCAN_PSR_EP_SHIFT (5U) -#define MCAN_PSR_EP_GET(x) (((uint32_t)(x) & MCAN_PSR_EP_MASK) >> MCAN_PSR_EP_SHIFT) - -/* - * ACT (R) - * - * Activity - * Monitors the module’s CAN communication state. - * 00= Synchronizing - node is synchronizing on CAN communication - * 01= Idle - node is neither receiver nor transmitter - * 10= Receiver - node is operating as receiver - * 11= Transmitter - node is operating as transmitter - * Note: ACT is set to “00” by a Protocol Exception Event. - */ -#define MCAN_PSR_ACT_MASK (0x18U) -#define MCAN_PSR_ACT_SHIFT (3U) -#define MCAN_PSR_ACT_GET(x) (((uint32_t)(x) & MCAN_PSR_ACT_MASK) >> MCAN_PSR_ACT_SHIFT) - -/* - * LEC (S) - * - * Last Error Code - * The LEC indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’when a message has been transferred (reception or transmission) without error. - * 0= No Error: No error occurred since LEC has been reset by successful reception or transmission. - * 1= Stuff Error: More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. - * 2= Form Error: A fixed format part of a received frame has the wrong format. - * 3= AckError: The message transmitted by the M_CAN was not acknowledged by another node. - * 4= Bit1Error: During the transmission of a message (with the exception of the arbitration field), - * the device wanted to send a recessive level (bit of logical value ‘1’), but the monitored bus - * value was dominant. - * 5= Bit0Error: During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value‘0’), but the monitored bus value was recessive. - * During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at - * dominant or continuously disturbed). - * 6= CRCError: The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. - * 7= NoChange: Any read access to the Protocol Status Register re-initializes the LEC to ‘7’. When the LEC shows the value ‘7’, no CAN bus event was detected since the last CPU read access to the Protocol Status Register. - * Note: When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event (error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD CRC sequence will be shown as a Form Error, not Stuff Error. - * Note: The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord,stopping all bus activities. - * Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. - * At the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been monitored, a Bit0Error code is written to PSR.LEC, - * enabling the CPU to readily check up whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery sequence. ECR.REC is used to count these sequences. - * Note: Byte access: Reading byte 0 will set LEC to “111”, reading bytes 3/2/1 has no impact. - */ -#define MCAN_PSR_LEC_MASK (0x7U) -#define MCAN_PSR_LEC_SHIFT (0U) -#define MCAN_PSR_LEC_GET(x) (((uint32_t)(x) & MCAN_PSR_LEC_MASK) >> MCAN_PSR_LEC_SHIFT) - -/* Bitfield definition for register: TDCR */ -/* - * TDCO (RW) - * - * Transmitter Delay Compensation SSP Offset - * Offset value defining the distance between the measured delay from m_can_tx to m_can_rx and the secondary sample point. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCO_MASK (0x7F00U) -#define MCAN_TDCR_TDCO_SHIFT (8U) -#define MCAN_TDCR_TDCO_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCO_SHIFT) & MCAN_TDCR_TDCO_MASK) -#define MCAN_TDCR_TDCO_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCO_MASK) >> MCAN_TDCR_TDCO_SHIFT) - -/* - * TDCF (RW) - * - * Transmitter Delay Compensation Filter Window Length - * Defines the minimum value for the SSP position, dominant edges on m_can_rx that would result in an earlier SSP position are ignored for transmitter delay measurement. - * The feature is enabled when TDCF is configured to a value greater than TDCO. Valid values are 0 to 127 mtq. - */ -#define MCAN_TDCR_TDCF_MASK (0x7FU) -#define MCAN_TDCR_TDCF_SHIFT (0U) -#define MCAN_TDCR_TDCF_SET(x) (((uint32_t)(x) << MCAN_TDCR_TDCF_SHIFT) & MCAN_TDCR_TDCF_MASK) -#define MCAN_TDCR_TDCF_GET(x) (((uint32_t)(x) & MCAN_TDCR_TDCF_MASK) >> MCAN_TDCR_TDCF_SHIFT) - -/* Bitfield definition for register: IR */ -/* - * ARA (RW) - * - * Access to Reserved Address - * 0= No access to reserved address occurred - * 1= Access to reserved address occurred - */ -#define MCAN_IR_ARA_MASK (0x20000000UL) -#define MCAN_IR_ARA_SHIFT (29U) -#define MCAN_IR_ARA_SET(x) (((uint32_t)(x) << MCAN_IR_ARA_SHIFT) & MCAN_IR_ARA_MASK) -#define MCAN_IR_ARA_GET(x) (((uint32_t)(x) & MCAN_IR_ARA_MASK) >> MCAN_IR_ARA_SHIFT) - -/* - * PED (RW) - * - * Protocol Error in Data Phase (Data Bit Time is used) - * 0= No protocol error in data phase - * 1= Protocol error in data phase detected (PSR.DLEC ≠ 0,7) - */ -#define MCAN_IR_PED_MASK (0x10000000UL) -#define MCAN_IR_PED_SHIFT (28U) -#define MCAN_IR_PED_SET(x) (((uint32_t)(x) << MCAN_IR_PED_SHIFT) & MCAN_IR_PED_MASK) -#define MCAN_IR_PED_GET(x) (((uint32_t)(x) & MCAN_IR_PED_MASK) >> MCAN_IR_PED_SHIFT) - -/* - * PEA (RW) - * - * Protocol Error in Arbitration Phase (Nominal Bit Time is used) - * 0= No protocol error in arbitration phase - * 1= Protocol error in arbitration phase detected (PSR.LEC ≠ 0,7) - */ -#define MCAN_IR_PEA_MASK (0x8000000UL) -#define MCAN_IR_PEA_SHIFT (27U) -#define MCAN_IR_PEA_SET(x) (((uint32_t)(x) << MCAN_IR_PEA_SHIFT) & MCAN_IR_PEA_MASK) -#define MCAN_IR_PEA_GET(x) (((uint32_t)(x) & MCAN_IR_PEA_MASK) >> MCAN_IR_PEA_SHIFT) - -/* - * WDI (RW) - * - * Watchdog Interrupt - * 0= No Message RAM Watchdog event occurred - * 1= Message RAM Watchdog event due to missing READY - */ -#define MCAN_IR_WDI_MASK (0x4000000UL) -#define MCAN_IR_WDI_SHIFT (26U) -#define MCAN_IR_WDI_SET(x) (((uint32_t)(x) << MCAN_IR_WDI_SHIFT) & MCAN_IR_WDI_MASK) -#define MCAN_IR_WDI_GET(x) (((uint32_t)(x) & MCAN_IR_WDI_MASK) >> MCAN_IR_WDI_SHIFT) - -/* - * BO (RW) - * - * Bus_Off Status - * 0= Bus_Off status unchanged - * 1= Bus_Off status changed - */ -#define MCAN_IR_BO_MASK (0x2000000UL) -#define MCAN_IR_BO_SHIFT (25U) -#define MCAN_IR_BO_SET(x) (((uint32_t)(x) << MCAN_IR_BO_SHIFT) & MCAN_IR_BO_MASK) -#define MCAN_IR_BO_GET(x) (((uint32_t)(x) & MCAN_IR_BO_MASK) >> MCAN_IR_BO_SHIFT) - -/* - * EW (RW) - * - * Warning Status - * 0= Error_Warning status unchanged - * 1= Error_Warning status changed - */ -#define MCAN_IR_EW_MASK (0x1000000UL) -#define MCAN_IR_EW_SHIFT (24U) -#define MCAN_IR_EW_SET(x) (((uint32_t)(x) << MCAN_IR_EW_SHIFT) & MCAN_IR_EW_MASK) -#define MCAN_IR_EW_GET(x) (((uint32_t)(x) & MCAN_IR_EW_MASK) >> MCAN_IR_EW_SHIFT) - -/* - * EP (RW) - * - * Error Passive - * 0= Error_Passive status unchanged - * 1= Error_Passive status changed - */ -#define MCAN_IR_EP_MASK (0x800000UL) -#define MCAN_IR_EP_SHIFT (23U) -#define MCAN_IR_EP_SET(x) (((uint32_t)(x) << MCAN_IR_EP_SHIFT) & MCAN_IR_EP_MASK) -#define MCAN_IR_EP_GET(x) (((uint32_t)(x) & MCAN_IR_EP_MASK) >> MCAN_IR_EP_SHIFT) - -/* - * ELO (RW) - * - * Error Logging Overflow - * 0= CAN Error Logging Counter did not overflow - * 1= Overflow of CAN Error Logging Counter occurred - */ -#define MCAN_IR_ELO_MASK (0x400000UL) -#define MCAN_IR_ELO_SHIFT (22U) -#define MCAN_IR_ELO_SET(x) (((uint32_t)(x) << MCAN_IR_ELO_SHIFT) & MCAN_IR_ELO_MASK) -#define MCAN_IR_ELO_GET(x) (((uint32_t)(x) & MCAN_IR_ELO_MASK) >> MCAN_IR_ELO_SHIFT) - -/* - * BEU (RW) - * - * Bit Error Uncorrected - * Message RAM bit error detected, uncorrected. Controlled by input signal m_can_aeim_berr[1] generated by an optional external parity / ECC logic attached to the Message RAM. - * An uncorrected Message RAM bit error sets CCCR.INIT to ‘1’. This is done to avoid transmission of corrupted data. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected, uncorrected (e.g. parity logic) - */ -#define MCAN_IR_BEU_MASK (0x200000UL) -#define MCAN_IR_BEU_SHIFT (21U) -#define MCAN_IR_BEU_SET(x) (((uint32_t)(x) << MCAN_IR_BEU_SHIFT) & MCAN_IR_BEU_MASK) -#define MCAN_IR_BEU_GET(x) (((uint32_t)(x) & MCAN_IR_BEU_MASK) >> MCAN_IR_BEU_SHIFT) - -/* - * BEC (RW) - * - * Bit Error Corrected - * Message RAM bit error detected and corrected. Controlled by input signal m_can_aeim_berr[0] generated by an optional external parity / ECC logic attached to the Message RAM. - * 0= No bit error detected when reading from Message RAM - * 1= Bit error detected and corrected (e.g. ECC) - */ -#define MCAN_IR_BEC_MASK (0x100000UL) -#define MCAN_IR_BEC_SHIFT (20U) -#define MCAN_IR_BEC_SET(x) (((uint32_t)(x) << MCAN_IR_BEC_SHIFT) & MCAN_IR_BEC_MASK) -#define MCAN_IR_BEC_GET(x) (((uint32_t)(x) & MCAN_IR_BEC_MASK) >> MCAN_IR_BEC_SHIFT) - -/* - * DRX (RW) - * - * Message stored to Dedicated Rx Buffer - * The flag is set whenever a received message has been stored into a dedicated Rx Buffer. - * 0= No Rx Buffer updated - * 1= At least one received message stored into an Rx Buffer - */ -#define MCAN_IR_DRX_MASK (0x80000UL) -#define MCAN_IR_DRX_SHIFT (19U) -#define MCAN_IR_DRX_SET(x) (((uint32_t)(x) << MCAN_IR_DRX_SHIFT) & MCAN_IR_DRX_MASK) -#define MCAN_IR_DRX_GET(x) (((uint32_t)(x) & MCAN_IR_DRX_MASK) >> MCAN_IR_DRX_SHIFT) - -/* - * TOO (RW) - * - * Timeout Occurred - * 0= No timeout - * 1= Timeout reached - */ -#define MCAN_IR_TOO_MASK (0x40000UL) -#define MCAN_IR_TOO_SHIFT (18U) -#define MCAN_IR_TOO_SET(x) (((uint32_t)(x) << MCAN_IR_TOO_SHIFT) & MCAN_IR_TOO_MASK) -#define MCAN_IR_TOO_GET(x) (((uint32_t)(x) & MCAN_IR_TOO_MASK) >> MCAN_IR_TOO_SHIFT) - -/* - * MRAF (RW) - * - * Message RAM Access Failure - * The flag is set, when the Rx Handler - * .has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received. In this case acceptance filtering or message - * storage is aborted and the Rx Handler starts processing of the following message. - * .was not able to write a message to the Message RAM. In this case message storage is aborted. - * In both cases the FIFO put index is not updated resp. the New Data flag for a dedicated Rx Buffer is not set, a partly stored message is overwritten when the next message is stored to this location. - * The flag is also set when the Tx Handler was not able to read a message from the Message RAM in time. In this case message transmission is aborted. In case of a Tx Handler access failure the - * M_CAN is switched into Restricted Operation Mode (see Section 3.1.5). To leave Restricted Operation Mode, the Host CPU has to reset CCCR.ASM. - * 0= No Message RAM access failure occurred - * 1= Message RAM access failure occurred - */ -#define MCAN_IR_MRAF_MASK (0x20000UL) -#define MCAN_IR_MRAF_SHIFT (17U) -#define MCAN_IR_MRAF_SET(x) (((uint32_t)(x) << MCAN_IR_MRAF_SHIFT) & MCAN_IR_MRAF_MASK) -#define MCAN_IR_MRAF_GET(x) (((uint32_t)(x) & MCAN_IR_MRAF_MASK) >> MCAN_IR_MRAF_SHIFT) - -/* - * TSW (RW) - * - * Timestamp Wraparound - * 0= No timestamp counter wrap-around - * 1= Timestamp counter wrapped around - */ -#define MCAN_IR_TSW_MASK (0x10000UL) -#define MCAN_IR_TSW_SHIFT (16U) -#define MCAN_IR_TSW_SET(x) (((uint32_t)(x) << MCAN_IR_TSW_SHIFT) & MCAN_IR_TSW_MASK) -#define MCAN_IR_TSW_GET(x) (((uint32_t)(x) & MCAN_IR_TSW_MASK) >> MCAN_IR_TSW_SHIFT) - -/* - * TEFL (RW) - * - * Tx Event FIFO Element Lost - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero - */ -#define MCAN_IR_TEFL_MASK (0x8000U) -#define MCAN_IR_TEFL_SHIFT (15U) -#define MCAN_IR_TEFL_SET(x) (((uint32_t)(x) << MCAN_IR_TEFL_SHIFT) & MCAN_IR_TEFL_MASK) -#define MCAN_IR_TEFL_GET(x) (((uint32_t)(x) & MCAN_IR_TEFL_MASK) >> MCAN_IR_TEFL_SHIFT) - -/* - * TEFF (RW) - * - * Tx Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_IR_TEFF_MASK (0x4000U) -#define MCAN_IR_TEFF_SHIFT (14U) -#define MCAN_IR_TEFF_SET(x) (((uint32_t)(x) << MCAN_IR_TEFF_SHIFT) & MCAN_IR_TEFF_MASK) -#define MCAN_IR_TEFF_GET(x) (((uint32_t)(x) & MCAN_IR_TEFF_MASK) >> MCAN_IR_TEFF_SHIFT) - -/* - * TEFW (RW) - * - * Tx Event FIFO Watermark Reached - * 0= Tx Event FIFO fill level below watermark - * 1= Tx Event FIFO fill level reached watermark - */ -#define MCAN_IR_TEFW_MASK (0x2000U) -#define MCAN_IR_TEFW_SHIFT (13U) -#define MCAN_IR_TEFW_SET(x) (((uint32_t)(x) << MCAN_IR_TEFW_SHIFT) & MCAN_IR_TEFW_MASK) -#define MCAN_IR_TEFW_GET(x) (((uint32_t)(x) & MCAN_IR_TEFW_MASK) >> MCAN_IR_TEFW_SHIFT) - -/* - * TEFN (RW) - * - * Tx Event FIFO New Entry - * 0= Tx Event FIFO unchanged - * 1= Tx Handler wrote Tx Event FIFO element - */ -#define MCAN_IR_TEFN_MASK (0x1000U) -#define MCAN_IR_TEFN_SHIFT (12U) -#define MCAN_IR_TEFN_SET(x) (((uint32_t)(x) << MCAN_IR_TEFN_SHIFT) & MCAN_IR_TEFN_MASK) -#define MCAN_IR_TEFN_GET(x) (((uint32_t)(x) & MCAN_IR_TEFN_MASK) >> MCAN_IR_TEFN_SHIFT) - -/* - * TFE (RW) - * - * Tx FIFO Empty - * 0= Tx FIFO non-empty - * 1= Tx FIFO empty - */ -#define MCAN_IR_TFE_MASK (0x800U) -#define MCAN_IR_TFE_SHIFT (11U) -#define MCAN_IR_TFE_SET(x) (((uint32_t)(x) << MCAN_IR_TFE_SHIFT) & MCAN_IR_TFE_MASK) -#define MCAN_IR_TFE_GET(x) (((uint32_t)(x) & MCAN_IR_TFE_MASK) >> MCAN_IR_TFE_SHIFT) - -/* - * TCF (RW) - * - * Transmission Cancellation Finished - * 0= No transmission cancellation finished - * 1= Transmission cancellation finished - */ -#define MCAN_IR_TCF_MASK (0x400U) -#define MCAN_IR_TCF_SHIFT (10U) -#define MCAN_IR_TCF_SET(x) (((uint32_t)(x) << MCAN_IR_TCF_SHIFT) & MCAN_IR_TCF_MASK) -#define MCAN_IR_TCF_GET(x) (((uint32_t)(x) & MCAN_IR_TCF_MASK) >> MCAN_IR_TCF_SHIFT) - -/* - * TC (RW) - * - * Transmission Completed - * 0= No transmission completed - * 1= Transmission completed - */ -#define MCAN_IR_TC_MASK (0x200U) -#define MCAN_IR_TC_SHIFT (9U) -#define MCAN_IR_TC_SET(x) (((uint32_t)(x) << MCAN_IR_TC_SHIFT) & MCAN_IR_TC_MASK) -#define MCAN_IR_TC_GET(x) (((uint32_t)(x) & MCAN_IR_TC_MASK) >> MCAN_IR_TC_SHIFT) - -/* - * HPM (RW) - * - * High Priority Message - * 0= No high priority message received - * 1= High priority message received - */ -#define MCAN_IR_HPM_MASK (0x100U) -#define MCAN_IR_HPM_SHIFT (8U) -#define MCAN_IR_HPM_SET(x) (((uint32_t)(x) << MCAN_IR_HPM_SHIFT) & MCAN_IR_HPM_MASK) -#define MCAN_IR_HPM_GET(x) (((uint32_t)(x) & MCAN_IR_HPM_MASK) >> MCAN_IR_HPM_SHIFT) - -/* - * RF1L (RW) - * - * Rx FIFO 1 Message Lost - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - */ -#define MCAN_IR_RF1L_MASK (0x80U) -#define MCAN_IR_RF1L_SHIFT (7U) -#define MCAN_IR_RF1L_SET(x) (((uint32_t)(x) << MCAN_IR_RF1L_SHIFT) & MCAN_IR_RF1L_MASK) -#define MCAN_IR_RF1L_GET(x) (((uint32_t)(x) & MCAN_IR_RF1L_MASK) >> MCAN_IR_RF1L_SHIFT) - -/* - * RF1F (RW) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_IR_RF1F_MASK (0x40U) -#define MCAN_IR_RF1F_SHIFT (6U) -#define MCAN_IR_RF1F_SET(x) (((uint32_t)(x) << MCAN_IR_RF1F_SHIFT) & MCAN_IR_RF1F_MASK) -#define MCAN_IR_RF1F_GET(x) (((uint32_t)(x) & MCAN_IR_RF1F_MASK) >> MCAN_IR_RF1F_SHIFT) - -/* - * RF1W (RW) - * - * Rx FIFO 1 Watermark Reached - * 0= Rx FIFO 1 fill level below watermark - * 1= Rx FIFO 1 fill level reached watermark - */ -#define MCAN_IR_RF1W_MASK (0x20U) -#define MCAN_IR_RF1W_SHIFT (5U) -#define MCAN_IR_RF1W_SET(x) (((uint32_t)(x) << MCAN_IR_RF1W_SHIFT) & MCAN_IR_RF1W_MASK) -#define MCAN_IR_RF1W_GET(x) (((uint32_t)(x) & MCAN_IR_RF1W_MASK) >> MCAN_IR_RF1W_SHIFT) - -/* - * RF1N (RW) - * - * Rx FIFO 1 New Message - * 0= No new message written to Rx FIFO 1 - * 1= New message written to Rx FIFO 1 - */ -#define MCAN_IR_RF1N_MASK (0x10U) -#define MCAN_IR_RF1N_SHIFT (4U) -#define MCAN_IR_RF1N_SET(x) (((uint32_t)(x) << MCAN_IR_RF1N_SHIFT) & MCAN_IR_RF1N_MASK) -#define MCAN_IR_RF1N_GET(x) (((uint32_t)(x) & MCAN_IR_RF1N_MASK) >> MCAN_IR_RF1N_SHIFT) - -/* - * RF0L (RW) - * - * Rx FIFO 0 Message Lost - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - */ -#define MCAN_IR_RF0L_MASK (0x8U) -#define MCAN_IR_RF0L_SHIFT (3U) -#define MCAN_IR_RF0L_SET(x) (((uint32_t)(x) << MCAN_IR_RF0L_SHIFT) & MCAN_IR_RF0L_MASK) -#define MCAN_IR_RF0L_GET(x) (((uint32_t)(x) & MCAN_IR_RF0L_MASK) >> MCAN_IR_RF0L_SHIFT) - -/* - * RF0F (RW) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_IR_RF0F_MASK (0x4U) -#define MCAN_IR_RF0F_SHIFT (2U) -#define MCAN_IR_RF0F_SET(x) (((uint32_t)(x) << MCAN_IR_RF0F_SHIFT) & MCAN_IR_RF0F_MASK) -#define MCAN_IR_RF0F_GET(x) (((uint32_t)(x) & MCAN_IR_RF0F_MASK) >> MCAN_IR_RF0F_SHIFT) - -/* - * RF0W (RW) - * - * Rx FIFO 0 Watermark Reached - * 0= Rx FIFO 0 fill level below watermark - * 1= Rx FIFO 0 fill level reached watermark - */ -#define MCAN_IR_RF0W_MASK (0x2U) -#define MCAN_IR_RF0W_SHIFT (1U) -#define MCAN_IR_RF0W_SET(x) (((uint32_t)(x) << MCAN_IR_RF0W_SHIFT) & MCAN_IR_RF0W_MASK) -#define MCAN_IR_RF0W_GET(x) (((uint32_t)(x) & MCAN_IR_RF0W_MASK) >> MCAN_IR_RF0W_SHIFT) - -/* - * RF0N (RW) - * - * Rx FIFO 0 New Message - * 0= No new message written to Rx FIFO 0 - * 1= New message written to Rx FIFO 0 - */ -#define MCAN_IR_RF0N_MASK (0x1U) -#define MCAN_IR_RF0N_SHIFT (0U) -#define MCAN_IR_RF0N_SET(x) (((uint32_t)(x) << MCAN_IR_RF0N_SHIFT) & MCAN_IR_RF0N_MASK) -#define MCAN_IR_RF0N_GET(x) (((uint32_t)(x) & MCAN_IR_RF0N_MASK) >> MCAN_IR_RF0N_SHIFT) - -/* Bitfield definition for register: IE */ -/* - * ARAE (RW) - * - * Access to Reserved Address Enable - */ -#define MCAN_IE_ARAE_MASK (0x20000000UL) -#define MCAN_IE_ARAE_SHIFT (29U) -#define MCAN_IE_ARAE_SET(x) (((uint32_t)(x) << MCAN_IE_ARAE_SHIFT) & MCAN_IE_ARAE_MASK) -#define MCAN_IE_ARAE_GET(x) (((uint32_t)(x) & MCAN_IE_ARAE_MASK) >> MCAN_IE_ARAE_SHIFT) - -/* - * PEDE (RW) - * - * Protocol Error in Data Phase Enable - */ -#define MCAN_IE_PEDE_MASK (0x10000000UL) -#define MCAN_IE_PEDE_SHIFT (28U) -#define MCAN_IE_PEDE_SET(x) (((uint32_t)(x) << MCAN_IE_PEDE_SHIFT) & MCAN_IE_PEDE_MASK) -#define MCAN_IE_PEDE_GET(x) (((uint32_t)(x) & MCAN_IE_PEDE_MASK) >> MCAN_IE_PEDE_SHIFT) - -/* - * PEAE (RW) - * - * Protocol Error in Arbitration Phase Enable - */ -#define MCAN_IE_PEAE_MASK (0x8000000UL) -#define MCAN_IE_PEAE_SHIFT (27U) -#define MCAN_IE_PEAE_SET(x) (((uint32_t)(x) << MCAN_IE_PEAE_SHIFT) & MCAN_IE_PEAE_MASK) -#define MCAN_IE_PEAE_GET(x) (((uint32_t)(x) & MCAN_IE_PEAE_MASK) >> MCAN_IE_PEAE_SHIFT) - -/* - * WDIE (RW) - * - * Watchdog Interrupt Enable - */ -#define MCAN_IE_WDIE_MASK (0x4000000UL) -#define MCAN_IE_WDIE_SHIFT (26U) -#define MCAN_IE_WDIE_SET(x) (((uint32_t)(x) << MCAN_IE_WDIE_SHIFT) & MCAN_IE_WDIE_MASK) -#define MCAN_IE_WDIE_GET(x) (((uint32_t)(x) & MCAN_IE_WDIE_MASK) >> MCAN_IE_WDIE_SHIFT) - -/* - * BOE (RW) - * - * Bus_Off Status Interrupt Enable - */ -#define MCAN_IE_BOE_MASK (0x2000000UL) -#define MCAN_IE_BOE_SHIFT (25U) -#define MCAN_IE_BOE_SET(x) (((uint32_t)(x) << MCAN_IE_BOE_SHIFT) & MCAN_IE_BOE_MASK) -#define MCAN_IE_BOE_GET(x) (((uint32_t)(x) & MCAN_IE_BOE_MASK) >> MCAN_IE_BOE_SHIFT) - -/* - * EWE (RW) - * - * Warning Status Interrupt Enable - */ -#define MCAN_IE_EWE_MASK (0x1000000UL) -#define MCAN_IE_EWE_SHIFT (24U) -#define MCAN_IE_EWE_SET(x) (((uint32_t)(x) << MCAN_IE_EWE_SHIFT) & MCAN_IE_EWE_MASK) -#define MCAN_IE_EWE_GET(x) (((uint32_t)(x) & MCAN_IE_EWE_MASK) >> MCAN_IE_EWE_SHIFT) - -/* - * EPE (RW) - * - * Error Passive Interrupt Enable - */ -#define MCAN_IE_EPE_MASK (0x800000UL) -#define MCAN_IE_EPE_SHIFT (23U) -#define MCAN_IE_EPE_SET(x) (((uint32_t)(x) << MCAN_IE_EPE_SHIFT) & MCAN_IE_EPE_MASK) -#define MCAN_IE_EPE_GET(x) (((uint32_t)(x) & MCAN_IE_EPE_MASK) >> MCAN_IE_EPE_SHIFT) - -/* - * ELOE (RW) - * - * Error Logging Overflow Interrupt Enable - */ -#define MCAN_IE_ELOE_MASK (0x400000UL) -#define MCAN_IE_ELOE_SHIFT (22U) -#define MCAN_IE_ELOE_SET(x) (((uint32_t)(x) << MCAN_IE_ELOE_SHIFT) & MCAN_IE_ELOE_MASK) -#define MCAN_IE_ELOE_GET(x) (((uint32_t)(x) & MCAN_IE_ELOE_MASK) >> MCAN_IE_ELOE_SHIFT) - -/* - * BEUE (RW) - * - * Bit Error Uncorrected Interrupt Enable - */ -#define MCAN_IE_BEUE_MASK (0x200000UL) -#define MCAN_IE_BEUE_SHIFT (21U) -#define MCAN_IE_BEUE_SET(x) (((uint32_t)(x) << MCAN_IE_BEUE_SHIFT) & MCAN_IE_BEUE_MASK) -#define MCAN_IE_BEUE_GET(x) (((uint32_t)(x) & MCAN_IE_BEUE_MASK) >> MCAN_IE_BEUE_SHIFT) - -/* - * BECE (RW) - * - * Bit Error Corrected Interrupt Enable - */ -#define MCAN_IE_BECE_MASK (0x100000UL) -#define MCAN_IE_BECE_SHIFT (20U) -#define MCAN_IE_BECE_SET(x) (((uint32_t)(x) << MCAN_IE_BECE_SHIFT) & MCAN_IE_BECE_MASK) -#define MCAN_IE_BECE_GET(x) (((uint32_t)(x) & MCAN_IE_BECE_MASK) >> MCAN_IE_BECE_SHIFT) - -/* - * DRXE (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Enable - */ -#define MCAN_IE_DRXE_MASK (0x80000UL) -#define MCAN_IE_DRXE_SHIFT (19U) -#define MCAN_IE_DRXE_SET(x) (((uint32_t)(x) << MCAN_IE_DRXE_SHIFT) & MCAN_IE_DRXE_MASK) -#define MCAN_IE_DRXE_GET(x) (((uint32_t)(x) & MCAN_IE_DRXE_MASK) >> MCAN_IE_DRXE_SHIFT) - -/* - * TOOE (RW) - * - * Timeout Occurred Interrupt Enable - */ -#define MCAN_IE_TOOE_MASK (0x40000UL) -#define MCAN_IE_TOOE_SHIFT (18U) -#define MCAN_IE_TOOE_SET(x) (((uint32_t)(x) << MCAN_IE_TOOE_SHIFT) & MCAN_IE_TOOE_MASK) -#define MCAN_IE_TOOE_GET(x) (((uint32_t)(x) & MCAN_IE_TOOE_MASK) >> MCAN_IE_TOOE_SHIFT) - -/* - * MRAFE (RW) - * - * Message RAM Access Failure Interrupt Enable - */ -#define MCAN_IE_MRAFE_MASK (0x20000UL) -#define MCAN_IE_MRAFE_SHIFT (17U) -#define MCAN_IE_MRAFE_SET(x) (((uint32_t)(x) << MCAN_IE_MRAFE_SHIFT) & MCAN_IE_MRAFE_MASK) -#define MCAN_IE_MRAFE_GET(x) (((uint32_t)(x) & MCAN_IE_MRAFE_MASK) >> MCAN_IE_MRAFE_SHIFT) - -/* - * TSWE (RW) - * - * Timestamp Wraparound Interrupt Enable - */ -#define MCAN_IE_TSWE_MASK (0x10000UL) -#define MCAN_IE_TSWE_SHIFT (16U) -#define MCAN_IE_TSWE_SET(x) (((uint32_t)(x) << MCAN_IE_TSWE_SHIFT) & MCAN_IE_TSWE_MASK) -#define MCAN_IE_TSWE_GET(x) (((uint32_t)(x) & MCAN_IE_TSWE_MASK) >> MCAN_IE_TSWE_SHIFT) - -/* - * TEFLE (RW) - * - * Tx Event FIFO Event Lost Interrupt Enable - */ -#define MCAN_IE_TEFLE_MASK (0x8000U) -#define MCAN_IE_TEFLE_SHIFT (15U) -#define MCAN_IE_TEFLE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFLE_SHIFT) & MCAN_IE_TEFLE_MASK) -#define MCAN_IE_TEFLE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFLE_MASK) >> MCAN_IE_TEFLE_SHIFT) - -/* - * TEFFE (RW) - * - * Tx Event FIFO Full Interrupt Enable - */ -#define MCAN_IE_TEFFE_MASK (0x4000U) -#define MCAN_IE_TEFFE_SHIFT (14U) -#define MCAN_IE_TEFFE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFFE_SHIFT) & MCAN_IE_TEFFE_MASK) -#define MCAN_IE_TEFFE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFFE_MASK) >> MCAN_IE_TEFFE_SHIFT) - -/* - * TEFWE (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Enable - */ -#define MCAN_IE_TEFWE_MASK (0x2000U) -#define MCAN_IE_TEFWE_SHIFT (13U) -#define MCAN_IE_TEFWE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFWE_SHIFT) & MCAN_IE_TEFWE_MASK) -#define MCAN_IE_TEFWE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFWE_MASK) >> MCAN_IE_TEFWE_SHIFT) - -/* - * TEFNE (RW) - * - * Tx Event FIFO New Entry Interrupt Enable - */ -#define MCAN_IE_TEFNE_MASK (0x1000U) -#define MCAN_IE_TEFNE_SHIFT (12U) -#define MCAN_IE_TEFNE_SET(x) (((uint32_t)(x) << MCAN_IE_TEFNE_SHIFT) & MCAN_IE_TEFNE_MASK) -#define MCAN_IE_TEFNE_GET(x) (((uint32_t)(x) & MCAN_IE_TEFNE_MASK) >> MCAN_IE_TEFNE_SHIFT) - -/* - * TFEE (RW) - * - * Tx FIFO Empty Interrupt Enable - */ -#define MCAN_IE_TFEE_MASK (0x800U) -#define MCAN_IE_TFEE_SHIFT (11U) -#define MCAN_IE_TFEE_SET(x) (((uint32_t)(x) << MCAN_IE_TFEE_SHIFT) & MCAN_IE_TFEE_MASK) -#define MCAN_IE_TFEE_GET(x) (((uint32_t)(x) & MCAN_IE_TFEE_MASK) >> MCAN_IE_TFEE_SHIFT) - -/* - * TCFE (RW) - * - * Transmission Cancellation Finished Interrupt Enable - */ -#define MCAN_IE_TCFE_MASK (0x400U) -#define MCAN_IE_TCFE_SHIFT (10U) -#define MCAN_IE_TCFE_SET(x) (((uint32_t)(x) << MCAN_IE_TCFE_SHIFT) & MCAN_IE_TCFE_MASK) -#define MCAN_IE_TCFE_GET(x) (((uint32_t)(x) & MCAN_IE_TCFE_MASK) >> MCAN_IE_TCFE_SHIFT) - -/* - * TCE (RW) - * - * Transmission Completed Interrupt Enable - */ -#define MCAN_IE_TCE_MASK (0x200U) -#define MCAN_IE_TCE_SHIFT (9U) -#define MCAN_IE_TCE_SET(x) (((uint32_t)(x) << MCAN_IE_TCE_SHIFT) & MCAN_IE_TCE_MASK) -#define MCAN_IE_TCE_GET(x) (((uint32_t)(x) & MCAN_IE_TCE_MASK) >> MCAN_IE_TCE_SHIFT) - -/* - * HPME (RW) - * - * High Priority Message Interrupt Enable - */ -#define MCAN_IE_HPME_MASK (0x100U) -#define MCAN_IE_HPME_SHIFT (8U) -#define MCAN_IE_HPME_SET(x) (((uint32_t)(x) << MCAN_IE_HPME_SHIFT) & MCAN_IE_HPME_MASK) -#define MCAN_IE_HPME_GET(x) (((uint32_t)(x) & MCAN_IE_HPME_MASK) >> MCAN_IE_HPME_SHIFT) - -/* - * RF1LE (RW) - * - * Rx FIFO 1 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF1LE_MASK (0x80U) -#define MCAN_IE_RF1LE_SHIFT (7U) -#define MCAN_IE_RF1LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1LE_SHIFT) & MCAN_IE_RF1LE_MASK) -#define MCAN_IE_RF1LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1LE_MASK) >> MCAN_IE_RF1LE_SHIFT) - -/* - * RF1FE (RW) - * - * Rx FIFO 1 Full Interrupt Enable - */ -#define MCAN_IE_RF1FE_MASK (0x40U) -#define MCAN_IE_RF1FE_SHIFT (6U) -#define MCAN_IE_RF1FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1FE_SHIFT) & MCAN_IE_RF1FE_MASK) -#define MCAN_IE_RF1FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1FE_MASK) >> MCAN_IE_RF1FE_SHIFT) - -/* - * RF1WE (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF1WE_MASK (0x20U) -#define MCAN_IE_RF1WE_SHIFT (5U) -#define MCAN_IE_RF1WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1WE_SHIFT) & MCAN_IE_RF1WE_MASK) -#define MCAN_IE_RF1WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1WE_MASK) >> MCAN_IE_RF1WE_SHIFT) - -/* - * RF1NE (RW) - * - * Rx FIFO 1 New Message Interrupt Enable - */ -#define MCAN_IE_RF1NE_MASK (0x10U) -#define MCAN_IE_RF1NE_SHIFT (4U) -#define MCAN_IE_RF1NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF1NE_SHIFT) & MCAN_IE_RF1NE_MASK) -#define MCAN_IE_RF1NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF1NE_MASK) >> MCAN_IE_RF1NE_SHIFT) - -/* - * RF0LE (RW) - * - * Rx FIFO 0 Message Lost Interrupt Enable - */ -#define MCAN_IE_RF0LE_MASK (0x8U) -#define MCAN_IE_RF0LE_SHIFT (3U) -#define MCAN_IE_RF0LE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0LE_SHIFT) & MCAN_IE_RF0LE_MASK) -#define MCAN_IE_RF0LE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0LE_MASK) >> MCAN_IE_RF0LE_SHIFT) - -/* - * RF0FE (RW) - * - * Rx FIFO 0 Full Interrupt Enable - */ -#define MCAN_IE_RF0FE_MASK (0x4U) -#define MCAN_IE_RF0FE_SHIFT (2U) -#define MCAN_IE_RF0FE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0FE_SHIFT) & MCAN_IE_RF0FE_MASK) -#define MCAN_IE_RF0FE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0FE_MASK) >> MCAN_IE_RF0FE_SHIFT) - -/* - * RF0WE (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Enable - */ -#define MCAN_IE_RF0WE_MASK (0x2U) -#define MCAN_IE_RF0WE_SHIFT (1U) -#define MCAN_IE_RF0WE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0WE_SHIFT) & MCAN_IE_RF0WE_MASK) -#define MCAN_IE_RF0WE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0WE_MASK) >> MCAN_IE_RF0WE_SHIFT) - -/* - * RF0NE (RW) - * - * Rx FIFO 0 New Message Interrupt Enable - */ -#define MCAN_IE_RF0NE_MASK (0x1U) -#define MCAN_IE_RF0NE_SHIFT (0U) -#define MCAN_IE_RF0NE_SET(x) (((uint32_t)(x) << MCAN_IE_RF0NE_SHIFT) & MCAN_IE_RF0NE_MASK) -#define MCAN_IE_RF0NE_GET(x) (((uint32_t)(x) & MCAN_IE_RF0NE_MASK) >> MCAN_IE_RF0NE_SHIFT) - -/* Bitfield definition for register: ILS */ -/* - * ARAL (RW) - * - * Access to Reserved Address Line - */ -#define MCAN_ILS_ARAL_MASK (0x20000000UL) -#define MCAN_ILS_ARAL_SHIFT (29U) -#define MCAN_ILS_ARAL_SET(x) (((uint32_t)(x) << MCAN_ILS_ARAL_SHIFT) & MCAN_ILS_ARAL_MASK) -#define MCAN_ILS_ARAL_GET(x) (((uint32_t)(x) & MCAN_ILS_ARAL_MASK) >> MCAN_ILS_ARAL_SHIFT) - -/* - * PEDL (RW) - * - * Protocol Error in Data Phase Line - */ -#define MCAN_ILS_PEDL_MASK (0x10000000UL) -#define MCAN_ILS_PEDL_SHIFT (28U) -#define MCAN_ILS_PEDL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEDL_SHIFT) & MCAN_ILS_PEDL_MASK) -#define MCAN_ILS_PEDL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEDL_MASK) >> MCAN_ILS_PEDL_SHIFT) - -/* - * PEAL (RW) - * - * Protocol Error in Arbitration Phase Line - */ -#define MCAN_ILS_PEAL_MASK (0x8000000UL) -#define MCAN_ILS_PEAL_SHIFT (27U) -#define MCAN_ILS_PEAL_SET(x) (((uint32_t)(x) << MCAN_ILS_PEAL_SHIFT) & MCAN_ILS_PEAL_MASK) -#define MCAN_ILS_PEAL_GET(x) (((uint32_t)(x) & MCAN_ILS_PEAL_MASK) >> MCAN_ILS_PEAL_SHIFT) - -/* - * WDIL (RW) - * - * Watchdog Interrupt Line - */ -#define MCAN_ILS_WDIL_MASK (0x4000000UL) -#define MCAN_ILS_WDIL_SHIFT (26U) -#define MCAN_ILS_WDIL_SET(x) (((uint32_t)(x) << MCAN_ILS_WDIL_SHIFT) & MCAN_ILS_WDIL_MASK) -#define MCAN_ILS_WDIL_GET(x) (((uint32_t)(x) & MCAN_ILS_WDIL_MASK) >> MCAN_ILS_WDIL_SHIFT) - -/* - * BOL (RW) - * - * Bus_Off Status Interrupt Line - */ -#define MCAN_ILS_BOL_MASK (0x2000000UL) -#define MCAN_ILS_BOL_SHIFT (25U) -#define MCAN_ILS_BOL_SET(x) (((uint32_t)(x) << MCAN_ILS_BOL_SHIFT) & MCAN_ILS_BOL_MASK) -#define MCAN_ILS_BOL_GET(x) (((uint32_t)(x) & MCAN_ILS_BOL_MASK) >> MCAN_ILS_BOL_SHIFT) - -/* - * EWL (RW) - * - * Warning Status Interrupt Line - */ -#define MCAN_ILS_EWL_MASK (0x1000000UL) -#define MCAN_ILS_EWL_SHIFT (24U) -#define MCAN_ILS_EWL_SET(x) (((uint32_t)(x) << MCAN_ILS_EWL_SHIFT) & MCAN_ILS_EWL_MASK) -#define MCAN_ILS_EWL_GET(x) (((uint32_t)(x) & MCAN_ILS_EWL_MASK) >> MCAN_ILS_EWL_SHIFT) - -/* - * EPL (RW) - * - * Error Passive Interrupt Line - */ -#define MCAN_ILS_EPL_MASK (0x800000UL) -#define MCAN_ILS_EPL_SHIFT (23U) -#define MCAN_ILS_EPL_SET(x) (((uint32_t)(x) << MCAN_ILS_EPL_SHIFT) & MCAN_ILS_EPL_MASK) -#define MCAN_ILS_EPL_GET(x) (((uint32_t)(x) & MCAN_ILS_EPL_MASK) >> MCAN_ILS_EPL_SHIFT) - -/* - * ELOL (RW) - * - * Error Logging Overflow Interrupt Line - */ -#define MCAN_ILS_ELOL_MASK (0x400000UL) -#define MCAN_ILS_ELOL_SHIFT (22U) -#define MCAN_ILS_ELOL_SET(x) (((uint32_t)(x) << MCAN_ILS_ELOL_SHIFT) & MCAN_ILS_ELOL_MASK) -#define MCAN_ILS_ELOL_GET(x) (((uint32_t)(x) & MCAN_ILS_ELOL_MASK) >> MCAN_ILS_ELOL_SHIFT) - -/* - * BEUL (RW) - * - * Bit Error Uncorrected Interrupt Line - */ -#define MCAN_ILS_BEUL_MASK (0x200000UL) -#define MCAN_ILS_BEUL_SHIFT (21U) -#define MCAN_ILS_BEUL_SET(x) (((uint32_t)(x) << MCAN_ILS_BEUL_SHIFT) & MCAN_ILS_BEUL_MASK) -#define MCAN_ILS_BEUL_GET(x) (((uint32_t)(x) & MCAN_ILS_BEUL_MASK) >> MCAN_ILS_BEUL_SHIFT) - -/* - * BECL (RW) - * - * Bit Error Corrected Interrupt Line - */ -#define MCAN_ILS_BECL_MASK (0x100000UL) -#define MCAN_ILS_BECL_SHIFT (20U) -#define MCAN_ILS_BECL_SET(x) (((uint32_t)(x) << MCAN_ILS_BECL_SHIFT) & MCAN_ILS_BECL_MASK) -#define MCAN_ILS_BECL_GET(x) (((uint32_t)(x) & MCAN_ILS_BECL_MASK) >> MCAN_ILS_BECL_SHIFT) - -/* - * DRXL (RW) - * - * Message stored to Dedicated Rx Buffer Interrupt Line - */ -#define MCAN_ILS_DRXL_MASK (0x80000UL) -#define MCAN_ILS_DRXL_SHIFT (19U) -#define MCAN_ILS_DRXL_SET(x) (((uint32_t)(x) << MCAN_ILS_DRXL_SHIFT) & MCAN_ILS_DRXL_MASK) -#define MCAN_ILS_DRXL_GET(x) (((uint32_t)(x) & MCAN_ILS_DRXL_MASK) >> MCAN_ILS_DRXL_SHIFT) - -/* - * TOOL (RW) - * - * Timeout Occurred Interrupt Line - */ -#define MCAN_ILS_TOOL_MASK (0x40000UL) -#define MCAN_ILS_TOOL_SHIFT (18U) -#define MCAN_ILS_TOOL_SET(x) (((uint32_t)(x) << MCAN_ILS_TOOL_SHIFT) & MCAN_ILS_TOOL_MASK) -#define MCAN_ILS_TOOL_GET(x) (((uint32_t)(x) & MCAN_ILS_TOOL_MASK) >> MCAN_ILS_TOOL_SHIFT) - -/* - * MRAFL (RW) - * - * Message RAM Access Failure Interrupt Line - */ -#define MCAN_ILS_MRAFL_MASK (0x20000UL) -#define MCAN_ILS_MRAFL_SHIFT (17U) -#define MCAN_ILS_MRAFL_SET(x) (((uint32_t)(x) << MCAN_ILS_MRAFL_SHIFT) & MCAN_ILS_MRAFL_MASK) -#define MCAN_ILS_MRAFL_GET(x) (((uint32_t)(x) & MCAN_ILS_MRAFL_MASK) >> MCAN_ILS_MRAFL_SHIFT) - -/* - * TSWL (RW) - * - * Timestamp Wraparound Interrupt Line - */ -#define MCAN_ILS_TSWL_MASK (0x10000UL) -#define MCAN_ILS_TSWL_SHIFT (16U) -#define MCAN_ILS_TSWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TSWL_SHIFT) & MCAN_ILS_TSWL_MASK) -#define MCAN_ILS_TSWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TSWL_MASK) >> MCAN_ILS_TSWL_SHIFT) - -/* - * TEFLL (RW) - * - * Tx Event FIFO Event Lost Interrupt Line - */ -#define MCAN_ILS_TEFLL_MASK (0x8000U) -#define MCAN_ILS_TEFLL_SHIFT (15U) -#define MCAN_ILS_TEFLL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFLL_SHIFT) & MCAN_ILS_TEFLL_MASK) -#define MCAN_ILS_TEFLL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFLL_MASK) >> MCAN_ILS_TEFLL_SHIFT) - -/* - * TEFFL (RW) - * - * Tx Event FIFO Full Interrupt Line - */ -#define MCAN_ILS_TEFFL_MASK (0x4000U) -#define MCAN_ILS_TEFFL_SHIFT (14U) -#define MCAN_ILS_TEFFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFFL_SHIFT) & MCAN_ILS_TEFFL_MASK) -#define MCAN_ILS_TEFFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFFL_MASK) >> MCAN_ILS_TEFFL_SHIFT) - -/* - * TEFWL (RW) - * - * Tx Event FIFO Watermark Reached Interrupt Line - */ -#define MCAN_ILS_TEFWL_MASK (0x2000U) -#define MCAN_ILS_TEFWL_SHIFT (13U) -#define MCAN_ILS_TEFWL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFWL_SHIFT) & MCAN_ILS_TEFWL_MASK) -#define MCAN_ILS_TEFWL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFWL_MASK) >> MCAN_ILS_TEFWL_SHIFT) - -/* - * TEFNL (RW) - * - * Tx Event FIFO New Entry Interrupt Line - */ -#define MCAN_ILS_TEFNL_MASK (0x1000U) -#define MCAN_ILS_TEFNL_SHIFT (12U) -#define MCAN_ILS_TEFNL_SET(x) (((uint32_t)(x) << MCAN_ILS_TEFNL_SHIFT) & MCAN_ILS_TEFNL_MASK) -#define MCAN_ILS_TEFNL_GET(x) (((uint32_t)(x) & MCAN_ILS_TEFNL_MASK) >> MCAN_ILS_TEFNL_SHIFT) - -/* - * TFEL (RW) - * - * Tx FIFO Empty Interrupt Line - */ -#define MCAN_ILS_TFEL_MASK (0x800U) -#define MCAN_ILS_TFEL_SHIFT (11U) -#define MCAN_ILS_TFEL_SET(x) (((uint32_t)(x) << MCAN_ILS_TFEL_SHIFT) & MCAN_ILS_TFEL_MASK) -#define MCAN_ILS_TFEL_GET(x) (((uint32_t)(x) & MCAN_ILS_TFEL_MASK) >> MCAN_ILS_TFEL_SHIFT) - -/* - * TCFL (RW) - * - * Transmission Cancellation Finished Interrupt Line - */ -#define MCAN_ILS_TCFL_MASK (0x400U) -#define MCAN_ILS_TCFL_SHIFT (10U) -#define MCAN_ILS_TCFL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCFL_SHIFT) & MCAN_ILS_TCFL_MASK) -#define MCAN_ILS_TCFL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCFL_MASK) >> MCAN_ILS_TCFL_SHIFT) - -/* - * TCL (RW) - * - * Transmission Completed Interrupt Line - */ -#define MCAN_ILS_TCL_MASK (0x200U) -#define MCAN_ILS_TCL_SHIFT (9U) -#define MCAN_ILS_TCL_SET(x) (((uint32_t)(x) << MCAN_ILS_TCL_SHIFT) & MCAN_ILS_TCL_MASK) -#define MCAN_ILS_TCL_GET(x) (((uint32_t)(x) & MCAN_ILS_TCL_MASK) >> MCAN_ILS_TCL_SHIFT) - -/* - * HPML (RW) - * - * High Priority Message Interrupt Line - */ -#define MCAN_ILS_HPML_MASK (0x100U) -#define MCAN_ILS_HPML_SHIFT (8U) -#define MCAN_ILS_HPML_SET(x) (((uint32_t)(x) << MCAN_ILS_HPML_SHIFT) & MCAN_ILS_HPML_MASK) -#define MCAN_ILS_HPML_GET(x) (((uint32_t)(x) & MCAN_ILS_HPML_MASK) >> MCAN_ILS_HPML_SHIFT) - -/* - * RF1LL (RW) - * - * Rx FIFO 1 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF1LL_MASK (0x80U) -#define MCAN_ILS_RF1LL_SHIFT (7U) -#define MCAN_ILS_RF1LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1LL_SHIFT) & MCAN_ILS_RF1LL_MASK) -#define MCAN_ILS_RF1LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1LL_MASK) >> MCAN_ILS_RF1LL_SHIFT) - -/* - * RF1FL (RW) - * - * Rx FIFO 1 Full Interrupt Line - */ -#define MCAN_ILS_RF1FL_MASK (0x40U) -#define MCAN_ILS_RF1FL_SHIFT (6U) -#define MCAN_ILS_RF1FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1FL_SHIFT) & MCAN_ILS_RF1FL_MASK) -#define MCAN_ILS_RF1FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1FL_MASK) >> MCAN_ILS_RF1FL_SHIFT) - -/* - * RF1WL (RW) - * - * Rx FIFO 1 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF1WL_MASK (0x20U) -#define MCAN_ILS_RF1WL_SHIFT (5U) -#define MCAN_ILS_RF1WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1WL_SHIFT) & MCAN_ILS_RF1WL_MASK) -#define MCAN_ILS_RF1WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1WL_MASK) >> MCAN_ILS_RF1WL_SHIFT) - -/* - * RF1NL (RW) - * - * Rx FIFO 1 New Message Interrupt Line - */ -#define MCAN_ILS_RF1NL_MASK (0x10U) -#define MCAN_ILS_RF1NL_SHIFT (4U) -#define MCAN_ILS_RF1NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF1NL_SHIFT) & MCAN_ILS_RF1NL_MASK) -#define MCAN_ILS_RF1NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF1NL_MASK) >> MCAN_ILS_RF1NL_SHIFT) - -/* - * RF0LL (RW) - * - * Rx FIFO 0 Message Lost Interrupt Line - */ -#define MCAN_ILS_RF0LL_MASK (0x8U) -#define MCAN_ILS_RF0LL_SHIFT (3U) -#define MCAN_ILS_RF0LL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0LL_SHIFT) & MCAN_ILS_RF0LL_MASK) -#define MCAN_ILS_RF0LL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0LL_MASK) >> MCAN_ILS_RF0LL_SHIFT) - -/* - * RF0FL (RW) - * - * Rx FIFO 0 Full Interrupt Line - */ -#define MCAN_ILS_RF0FL_MASK (0x4U) -#define MCAN_ILS_RF0FL_SHIFT (2U) -#define MCAN_ILS_RF0FL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0FL_SHIFT) & MCAN_ILS_RF0FL_MASK) -#define MCAN_ILS_RF0FL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0FL_MASK) >> MCAN_ILS_RF0FL_SHIFT) - -/* - * RF0WL (RW) - * - * Rx FIFO 0 Watermark Reached Interrupt Line - */ -#define MCAN_ILS_RF0WL_MASK (0x2U) -#define MCAN_ILS_RF0WL_SHIFT (1U) -#define MCAN_ILS_RF0WL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0WL_SHIFT) & MCAN_ILS_RF0WL_MASK) -#define MCAN_ILS_RF0WL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0WL_MASK) >> MCAN_ILS_RF0WL_SHIFT) - -/* - * RF0NL (RW) - * - * Rx FIFO 0 New Message Interrupt Line - */ -#define MCAN_ILS_RF0NL_MASK (0x1U) -#define MCAN_ILS_RF0NL_SHIFT (0U) -#define MCAN_ILS_RF0NL_SET(x) (((uint32_t)(x) << MCAN_ILS_RF0NL_SHIFT) & MCAN_ILS_RF0NL_MASK) -#define MCAN_ILS_RF0NL_GET(x) (((uint32_t)(x) & MCAN_ILS_RF0NL_MASK) >> MCAN_ILS_RF0NL_SHIFT) - -/* Bitfield definition for register: ILE */ -/* - * EINT1 (RW) - * - * Enable Interrupt Line 1 - * 0= Interrupt line m_can_int1 disabled - * 1= Interrupt line m_can_int1 enabled - */ -#define MCAN_ILE_EINT1_MASK (0x2U) -#define MCAN_ILE_EINT1_SHIFT (1U) -#define MCAN_ILE_EINT1_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT1_SHIFT) & MCAN_ILE_EINT1_MASK) -#define MCAN_ILE_EINT1_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT1_MASK) >> MCAN_ILE_EINT1_SHIFT) - -/* - * EINT0 (RW) - * - * Enable Interrupt Line 0 - * 0= Interrupt line m_can_int0 disabled - * 1= Interrupt line m_can_int0 enabled - */ -#define MCAN_ILE_EINT0_MASK (0x1U) -#define MCAN_ILE_EINT0_SHIFT (0U) -#define MCAN_ILE_EINT0_SET(x) (((uint32_t)(x) << MCAN_ILE_EINT0_SHIFT) & MCAN_ILE_EINT0_MASK) -#define MCAN_ILE_EINT0_GET(x) (((uint32_t)(x) & MCAN_ILE_EINT0_MASK) >> MCAN_ILE_EINT0_SHIFT) - -/* Bitfield definition for register: GFC */ -/* - * ANFS (RW) - * - * Accept Non-matching Frames Standard - * Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFS_MASK (0x30U) -#define MCAN_GFC_ANFS_SHIFT (4U) -#define MCAN_GFC_ANFS_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFS_SHIFT) & MCAN_GFC_ANFS_MASK) -#define MCAN_GFC_ANFS_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFS_MASK) >> MCAN_GFC_ANFS_SHIFT) - -/* - * ANFE (RW) - * - * Accept Non-matching Frames Extended - * Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. - * 00= Accept in Rx FIFO 0 - * 01= Accept in Rx FIFO 1 - * 10= Reject - * 11= Reject - */ -#define MCAN_GFC_ANFE_MASK (0xCU) -#define MCAN_GFC_ANFE_SHIFT (2U) -#define MCAN_GFC_ANFE_SET(x) (((uint32_t)(x) << MCAN_GFC_ANFE_SHIFT) & MCAN_GFC_ANFE_MASK) -#define MCAN_GFC_ANFE_GET(x) (((uint32_t)(x) & MCAN_GFC_ANFE_MASK) >> MCAN_GFC_ANFE_SHIFT) - -/* - * RRFS (RW) - * - * Reject Remote Frames Standard - * 0= Filter remote frames with 11-bit standard IDs - * 1= Reject all remote frames with 11-bit standard IDs - */ -#define MCAN_GFC_RRFS_MASK (0x2U) -#define MCAN_GFC_RRFS_SHIFT (1U) -#define MCAN_GFC_RRFS_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFS_SHIFT) & MCAN_GFC_RRFS_MASK) -#define MCAN_GFC_RRFS_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFS_MASK) >> MCAN_GFC_RRFS_SHIFT) - -/* - * RRFE (RW) - * - * Reject Remote Frames Extended - * 0= Filter remote frames with 29-bit extended IDs - * 1= Reject all remote frames with 29-bit extended IDs - */ -#define MCAN_GFC_RRFE_MASK (0x1U) -#define MCAN_GFC_RRFE_SHIFT (0U) -#define MCAN_GFC_RRFE_SET(x) (((uint32_t)(x) << MCAN_GFC_RRFE_SHIFT) & MCAN_GFC_RRFE_MASK) -#define MCAN_GFC_RRFE_GET(x) (((uint32_t)(x) & MCAN_GFC_RRFE_MASK) >> MCAN_GFC_RRFE_SHIFT) - -/* Bitfield definition for register: SIDFC */ -/* - * LSS (RW) - * - * List Size Standard - * 0= No standard Message ID filter - * 1-128= Number of standard Message ID filter elements - * >128= Values greater than 128 are interpreted as 128 - */ -#define MCAN_SIDFC_LSS_MASK (0xFF0000UL) -#define MCAN_SIDFC_LSS_SHIFT (16U) -#define MCAN_SIDFC_LSS_SET(x) (((uint32_t)(x) << MCAN_SIDFC_LSS_SHIFT) & MCAN_SIDFC_LSS_MASK) -#define MCAN_SIDFC_LSS_GET(x) (((uint32_t)(x) & MCAN_SIDFC_LSS_MASK) >> MCAN_SIDFC_LSS_SHIFT) - -/* - * FLSSA (RW) - * - * Filter List Standard Start Address - * Start address of standard Message ID filter list (32-bit word address) - */ -#define MCAN_SIDFC_FLSSA_MASK (0xFFFCU) -#define MCAN_SIDFC_FLSSA_SHIFT (2U) -#define MCAN_SIDFC_FLSSA_SET(x) (((uint32_t)(x) << MCAN_SIDFC_FLSSA_SHIFT) & MCAN_SIDFC_FLSSA_MASK) -#define MCAN_SIDFC_FLSSA_GET(x) (((uint32_t)(x) & MCAN_SIDFC_FLSSA_MASK) >> MCAN_SIDFC_FLSSA_SHIFT) - -/* Bitfield definition for register: XIDFC */ -/* - * LSE (RW) - * - * List Size Extended - * 0= No extended Message ID filter - * 1-64= Number of extended Message ID filter elements - * >64= Values greater than 64 are interpreted as 64 - */ -#define MCAN_XIDFC_LSE_MASK (0x7F0000UL) -#define MCAN_XIDFC_LSE_SHIFT (16U) -#define MCAN_XIDFC_LSE_SET(x) (((uint32_t)(x) << MCAN_XIDFC_LSE_SHIFT) & MCAN_XIDFC_LSE_MASK) -#define MCAN_XIDFC_LSE_GET(x) (((uint32_t)(x) & MCAN_XIDFC_LSE_MASK) >> MCAN_XIDFC_LSE_SHIFT) - -/* - * FLESA (RW) - * - * Filter List Extended Start Address - * Start address of extended Message ID filter list (32-bit word address). - */ -#define MCAN_XIDFC_FLESA_MASK (0xFFFCU) -#define MCAN_XIDFC_FLESA_SHIFT (2U) -#define MCAN_XIDFC_FLESA_SET(x) (((uint32_t)(x) << MCAN_XIDFC_FLESA_SHIFT) & MCAN_XIDFC_FLESA_MASK) -#define MCAN_XIDFC_FLESA_GET(x) (((uint32_t)(x) & MCAN_XIDFC_FLESA_MASK) >> MCAN_XIDFC_FLESA_SHIFT) - -/* Bitfield definition for register: XIDAM */ -/* - * EIDM (RW) - * - * Extended ID Mask - * For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame. - * Intended for masking of 29-bit IDs in SAE J1939. With the reset value of all bits set to one the mask is not active. - */ -#define MCAN_XIDAM_EIDM_MASK (0x1FFFFFFFUL) -#define MCAN_XIDAM_EIDM_SHIFT (0U) -#define MCAN_XIDAM_EIDM_SET(x) (((uint32_t)(x) << MCAN_XIDAM_EIDM_SHIFT) & MCAN_XIDAM_EIDM_MASK) -#define MCAN_XIDAM_EIDM_GET(x) (((uint32_t)(x) & MCAN_XIDAM_EIDM_MASK) >> MCAN_XIDAM_EIDM_SHIFT) - -/* Bitfield definition for register: HPMS */ -/* - * FLST (R) - * - * Filter List - * Indicates the filter list of the matching filter element. - * 0= Standard Filter List - * 1= Extended Filter List - */ -#define MCAN_HPMS_FLST_MASK (0x8000U) -#define MCAN_HPMS_FLST_SHIFT (15U) -#define MCAN_HPMS_FLST_GET(x) (((uint32_t)(x) & MCAN_HPMS_FLST_MASK) >> MCAN_HPMS_FLST_SHIFT) - -/* - * FIDX (R) - * - * Filter Index - * Index of matching filter element. Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1. - */ -#define MCAN_HPMS_FIDX_MASK (0x7F00U) -#define MCAN_HPMS_FIDX_SHIFT (8U) -#define MCAN_HPMS_FIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_FIDX_MASK) >> MCAN_HPMS_FIDX_SHIFT) - -/* - * MSI (R) - * - * Message Storage Indicator - * 00= No FIFO selected - * 01= FIFO message lost - * 10= Message stored in FIFO 0 - * 11= Message stored in FIFO 1 - */ -#define MCAN_HPMS_MSI_MASK (0xC0U) -#define MCAN_HPMS_MSI_SHIFT (6U) -#define MCAN_HPMS_MSI_GET(x) (((uint32_t)(x) & MCAN_HPMS_MSI_MASK) >> MCAN_HPMS_MSI_SHIFT) - -/* - * BIDX (R) - * - * Buffer Index - * Index of Rx FIFO element to which the message was stored. Only valid when MSI[1] = ‘1’. - */ -#define MCAN_HPMS_BIDX_MASK (0x3FU) -#define MCAN_HPMS_BIDX_SHIFT (0U) -#define MCAN_HPMS_BIDX_GET(x) (((uint32_t)(x) & MCAN_HPMS_BIDX_MASK) >> MCAN_HPMS_BIDX_SHIFT) - -/* Bitfield definition for register: NDAT1 */ -/* - * ND1 (RW) - * - * New Data[31:0] - * The register holds the New Data flags of Rx Buffers 0 to 31. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them.A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT1_ND1_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT1_ND1_SHIFT (0U) -#define MCAN_NDAT1_ND1_SET(x) (((uint32_t)(x) << MCAN_NDAT1_ND1_SHIFT) & MCAN_NDAT1_ND1_MASK) -#define MCAN_NDAT1_ND1_GET(x) (((uint32_t)(x) & MCAN_NDAT1_ND1_MASK) >> MCAN_NDAT1_ND1_SHIFT) - -/* Bitfield definition for register: NDAT2 */ -/* - * ND2 (RW) - * - * New Data[63:32] - * The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. - * The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register. - * 0= Rx Buffer not updated - * 1= Rx Buffer updated from new message - */ -#define MCAN_NDAT2_ND2_MASK (0xFFFFFFFFUL) -#define MCAN_NDAT2_ND2_SHIFT (0U) -#define MCAN_NDAT2_ND2_SET(x) (((uint32_t)(x) << MCAN_NDAT2_ND2_SHIFT) & MCAN_NDAT2_ND2_MASK) -#define MCAN_NDAT2_ND2_GET(x) (((uint32_t)(x) & MCAN_NDAT2_ND2_MASK) >> MCAN_NDAT2_ND2_SHIFT) - -/* Bitfield definition for register: RXF0C */ -/* - * F0OM (RW) - * - * FIFO 0 Operation Mode - * FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 0 blocking mode - * 1= FIFO 0 overwrite mode - */ -#define MCAN_RXF0C_F0OM_MASK (0x80000000UL) -#define MCAN_RXF0C_F0OM_SHIFT (31U) -#define MCAN_RXF0C_F0OM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0OM_SHIFT) & MCAN_RXF0C_F0OM_MASK) -#define MCAN_RXF0C_F0OM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0OM_MASK) >> MCAN_RXF0C_F0OM_SHIFT) - -/* - * F0WM (RW) - * - * Rx FIFO 0 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 0 watermark interrupt (IR.RF0W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF0C_F0WM_MASK (0x7F000000UL) -#define MCAN_RXF0C_F0WM_SHIFT (24U) -#define MCAN_RXF0C_F0WM_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0WM_SHIFT) & MCAN_RXF0C_F0WM_MASK) -#define MCAN_RXF0C_F0WM_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0WM_MASK) >> MCAN_RXF0C_F0WM_SHIFT) - -/* - * F0S (RW) - * - * Rx FIFO 0 Size - * 0= No Rx FIFO 0 - * 1-64= Number of Rx FIFO 0 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 0 elements are indexed from 0 to F0S-1 - */ -#define MCAN_RXF0C_F0S_MASK (0x7F0000UL) -#define MCAN_RXF0C_F0S_SHIFT (16U) -#define MCAN_RXF0C_F0S_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0S_SHIFT) & MCAN_RXF0C_F0S_MASK) -#define MCAN_RXF0C_F0S_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0S_MASK) >> MCAN_RXF0C_F0S_SHIFT) - -/* - * F0SA (RW) - * - * Rx FIFO 0 Start Address - * Start address of Rx FIFO 0 in Message RAM (32-bit word address) - */ -#define MCAN_RXF0C_F0SA_MASK (0xFFFCU) -#define MCAN_RXF0C_F0SA_SHIFT (2U) -#define MCAN_RXF0C_F0SA_SET(x) (((uint32_t)(x) << MCAN_RXF0C_F0SA_SHIFT) & MCAN_RXF0C_F0SA_MASK) -#define MCAN_RXF0C_F0SA_GET(x) (((uint32_t)(x) & MCAN_RXF0C_F0SA_MASK) >> MCAN_RXF0C_F0SA_SHIFT) - -/* Bitfield definition for register: RXF0S */ -/* - * RF0L (R) - * - * Rx FIFO 0 Message Lost - * This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is reset, this bit is also reset. - * 0= No Rx FIFO 0 message lost - * 1= Rx FIFO 0 message lost, also set after write attempt to Rx FIFO 0 of size zero - * Note: Overwriting the oldest message when RXF0C.F0OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF0S_RF0L_MASK (0x2000000UL) -#define MCAN_RXF0S_RF0L_SHIFT (25U) -#define MCAN_RXF0S_RF0L_GET(x) (((uint32_t)(x) & MCAN_RXF0S_RF0L_MASK) >> MCAN_RXF0S_RF0L_SHIFT) - -/* - * F0F (R) - * - * Rx FIFO 0 Full - * 0= Rx FIFO 0 not full - * 1= Rx FIFO 0 full - */ -#define MCAN_RXF0S_F0F_MASK (0x1000000UL) -#define MCAN_RXF0S_F0F_SHIFT (24U) -#define MCAN_RXF0S_F0F_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0F_MASK) >> MCAN_RXF0S_F0F_SHIFT) - -/* - * F0PI (R) - * - * Rx FIFO 0 Put Index - * Rx FIFO 0 write index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0PI_MASK (0x3F0000UL) -#define MCAN_RXF0S_F0PI_SHIFT (16U) -#define MCAN_RXF0S_F0PI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0PI_MASK) >> MCAN_RXF0S_F0PI_SHIFT) - -/* - * F0GI (R) - * - * Rx FIFO 0 Get Index - * Rx FIFO 0 read index pointer, range 0 to 63. - */ -#define MCAN_RXF0S_F0GI_MASK (0x3F00U) -#define MCAN_RXF0S_F0GI_SHIFT (8U) -#define MCAN_RXF0S_F0GI_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0GI_MASK) >> MCAN_RXF0S_F0GI_SHIFT) - -/* - * F0FL (R) - * - * Rx FIFO 0 Fill Level - * Number of elements stored in Rx FIFO 0, range 0 to 64. - */ -#define MCAN_RXF0S_F0FL_MASK (0x7FU) -#define MCAN_RXF0S_F0FL_SHIFT (0U) -#define MCAN_RXF0S_F0FL_GET(x) (((uint32_t)(x) & MCAN_RXF0S_F0FL_MASK) >> MCAN_RXF0S_F0FL_SHIFT) - -/* Bitfield definition for register: RXF0A */ -/* - * F0AI (RW) - * - * Rx FIFO 0 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI. - * This will set the Rx FIFO 0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill Level RXF0S.F0FL. - */ -#define MCAN_RXF0A_F0AI_MASK (0x3FU) -#define MCAN_RXF0A_F0AI_SHIFT (0U) -#define MCAN_RXF0A_F0AI_SET(x) (((uint32_t)(x) << MCAN_RXF0A_F0AI_SHIFT) & MCAN_RXF0A_F0AI_MASK) -#define MCAN_RXF0A_F0AI_GET(x) (((uint32_t)(x) & MCAN_RXF0A_F0AI_MASK) >> MCAN_RXF0A_F0AI_SHIFT) - -/* Bitfield definition for register: RXBC */ -/* - * RBSA (RW) - * - * Rx Buffer Start Address - * Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address).Also used to reference debug messages A,B,C. - */ -#define MCAN_RXBC_RBSA_MASK (0xFFFCU) -#define MCAN_RXBC_RBSA_SHIFT (2U) -#define MCAN_RXBC_RBSA_SET(x) (((uint32_t)(x) << MCAN_RXBC_RBSA_SHIFT) & MCAN_RXBC_RBSA_MASK) -#define MCAN_RXBC_RBSA_GET(x) (((uint32_t)(x) & MCAN_RXBC_RBSA_MASK) >> MCAN_RXBC_RBSA_SHIFT) - -/* Bitfield definition for register: RXF1C */ -/* - * F1OM (RW) - * - * FIFO 1 Operation Mode - * FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2). - * 0= FIFO 1 blocking mode - * 1= FIFO 1 overwrite mode - */ -#define MCAN_RXF1C_F1OM_MASK (0x80000000UL) -#define MCAN_RXF1C_F1OM_SHIFT (31U) -#define MCAN_RXF1C_F1OM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1OM_SHIFT) & MCAN_RXF1C_F1OM_MASK) -#define MCAN_RXF1C_F1OM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1OM_MASK) >> MCAN_RXF1C_F1OM_SHIFT) - -/* - * F1WM (RW) - * - * Rx FIFO 1 Watermark - * 0= Watermark interrupt disabled - * 1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W) - * >64= Watermark interrupt disabled - */ -#define MCAN_RXF1C_F1WM_MASK (0x7F000000UL) -#define MCAN_RXF1C_F1WM_SHIFT (24U) -#define MCAN_RXF1C_F1WM_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1WM_SHIFT) & MCAN_RXF1C_F1WM_MASK) -#define MCAN_RXF1C_F1WM_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1WM_MASK) >> MCAN_RXF1C_F1WM_SHIFT) - -/* - * F1S (RW) - * - * Rx FIFO 1 Size - * 0= No Rx FIFO 1 - * 1-64= Number of Rx FIFO 1 elements - * >64= Values greater than 64 are interpreted as 64 - * The Rx FIFO 1 elements are indexed from 0 to F1S - 1 - */ -#define MCAN_RXF1C_F1S_MASK (0x7F0000UL) -#define MCAN_RXF1C_F1S_SHIFT (16U) -#define MCAN_RXF1C_F1S_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1S_SHIFT) & MCAN_RXF1C_F1S_MASK) -#define MCAN_RXF1C_F1S_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1S_MASK) >> MCAN_RXF1C_F1S_SHIFT) - -/* - * F1SA (RW) - * - * Rx FIFO 1 Start Address - * Start address of Rx FIFO 1 in Message RAM (32-bit word address) - */ -#define MCAN_RXF1C_F1SA_MASK (0xFFFCU) -#define MCAN_RXF1C_F1SA_SHIFT (2U) -#define MCAN_RXF1C_F1SA_SET(x) (((uint32_t)(x) << MCAN_RXF1C_F1SA_SHIFT) & MCAN_RXF1C_F1SA_MASK) -#define MCAN_RXF1C_F1SA_GET(x) (((uint32_t)(x) & MCAN_RXF1C_F1SA_MASK) >> MCAN_RXF1C_F1SA_SHIFT) - -/* Bitfield definition for register: RXF1S */ -/* - * DMS (R) - * - * Debug Message Status - * 00= Idle state, wait for reception of debug messages, DMA request is cleared - * 01= Debug message A received - * 10= Debug messages A, B received - * 11= Debug messages A, B, C received, DMA request is set - */ -#define MCAN_RXF1S_DMS_MASK (0xC0000000UL) -#define MCAN_RXF1S_DMS_SHIFT (30U) -#define MCAN_RXF1S_DMS_GET(x) (((uint32_t)(x) & MCAN_RXF1S_DMS_MASK) >> MCAN_RXF1S_DMS_SHIFT) - -/* - * RF1L (R) - * - * Rx FIFO 1 Message Lost - * This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is reset, this bit is also reset. - * 0= No Rx FIFO 1 message lost - * 1= Rx FIFO 1 message lost, also set after write attempt to Rx FIFO 1 of size zero - * Note: Overwriting the oldest message when RXF1C.F1OM = ‘1’ will not set this flag. - */ -#define MCAN_RXF1S_RF1L_MASK (0x2000000UL) -#define MCAN_RXF1S_RF1L_SHIFT (25U) -#define MCAN_RXF1S_RF1L_GET(x) (((uint32_t)(x) & MCAN_RXF1S_RF1L_MASK) >> MCAN_RXF1S_RF1L_SHIFT) - -/* - * F1F (R) - * - * Rx FIFO 1 Full - * 0= Rx FIFO 1 not full - * 1= Rx FIFO 1 full - */ -#define MCAN_RXF1S_F1F_MASK (0x1000000UL) -#define MCAN_RXF1S_F1F_SHIFT (24U) -#define MCAN_RXF1S_F1F_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1F_MASK) >> MCAN_RXF1S_F1F_SHIFT) - -/* - * F1PI (R) - * - * Rx FIFO 1 Put Index - * Rx FIFO 1 write index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1PI_MASK (0x3F0000UL) -#define MCAN_RXF1S_F1PI_SHIFT (16U) -#define MCAN_RXF1S_F1PI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1PI_MASK) >> MCAN_RXF1S_F1PI_SHIFT) - -/* - * F1GI (R) - * - * Rx FIFO 1 Get Index - * Rx FIFO 1 read index pointer, range 0 to 63. - */ -#define MCAN_RXF1S_F1GI_MASK (0x3F00U) -#define MCAN_RXF1S_F1GI_SHIFT (8U) -#define MCAN_RXF1S_F1GI_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1GI_MASK) >> MCAN_RXF1S_F1GI_SHIFT) - -/* - * F1FL (R) - * - * Rx FIFO 1 Fill Level - * Number of elements stored in Rx FIFO 1, range 0 to 64. - */ -#define MCAN_RXF1S_F1FL_MASK (0x7FU) -#define MCAN_RXF1S_F1FL_SHIFT (0U) -#define MCAN_RXF1S_F1FL_GET(x) (((uint32_t)(x) & MCAN_RXF1S_F1FL_MASK) >> MCAN_RXF1S_F1FL_SHIFT) - -/* Bitfield definition for register: RXF1A */ -/* - * F1AI (RW) - * - * Rx FIFO 1 Acknowledge Index - * After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI. - * This will set the Rx FIFO 1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill Level RXF1S.F1FL. - */ -#define MCAN_RXF1A_F1AI_MASK (0x3FU) -#define MCAN_RXF1A_F1AI_SHIFT (0U) -#define MCAN_RXF1A_F1AI_SET(x) (((uint32_t)(x) << MCAN_RXF1A_F1AI_SHIFT) & MCAN_RXF1A_F1AI_MASK) -#define MCAN_RXF1A_F1AI_GET(x) (((uint32_t)(x) & MCAN_RXF1A_F1AI_MASK) >> MCAN_RXF1A_F1AI_SHIFT) - -/* Bitfield definition for register: RXESC */ -/* - * RBDS (RW) - * - * Rx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_RBDS_MASK (0x700U) -#define MCAN_RXESC_RBDS_SHIFT (8U) -#define MCAN_RXESC_RBDS_SET(x) (((uint32_t)(x) << MCAN_RXESC_RBDS_SHIFT) & MCAN_RXESC_RBDS_MASK) -#define MCAN_RXESC_RBDS_GET(x) (((uint32_t)(x) & MCAN_RXESC_RBDS_MASK) >> MCAN_RXESC_RBDS_SHIFT) - -/* - * F1DS (RW) - * - * Rx FIFO 1 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - */ -#define MCAN_RXESC_F1DS_MASK (0x70U) -#define MCAN_RXESC_F1DS_SHIFT (4U) -#define MCAN_RXESC_F1DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F1DS_SHIFT) & MCAN_RXESC_F1DS_MASK) -#define MCAN_RXESC_F1DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F1DS_MASK) >> MCAN_RXESC_F1DS_SHIFT) - -/* - * F0DS (RW) - * - * Rx FIFO 0 Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO, - * only the number of bytes as configured by RXESC are stored to the Rx Buffer resp. Rx FIFO element. The rest of the frame’s data field is ignored. - */ -#define MCAN_RXESC_F0DS_MASK (0x7U) -#define MCAN_RXESC_F0DS_SHIFT (0U) -#define MCAN_RXESC_F0DS_SET(x) (((uint32_t)(x) << MCAN_RXESC_F0DS_SHIFT) & MCAN_RXESC_F0DS_MASK) -#define MCAN_RXESC_F0DS_GET(x) (((uint32_t)(x) & MCAN_RXESC_F0DS_MASK) >> MCAN_RXESC_F0DS_SHIFT) - -/* Bitfield definition for register: TXBC */ -/* - * TFQM (RW) - * - * Tx FIFO/Queue Mode - * 0= Tx FIFO operation - * 1= Tx Queue operation - */ -#define MCAN_TXBC_TFQM_MASK (0x40000000UL) -#define MCAN_TXBC_TFQM_SHIFT (30U) -#define MCAN_TXBC_TFQM_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQM_SHIFT) & MCAN_TXBC_TFQM_MASK) -#define MCAN_TXBC_TFQM_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQM_MASK) >> MCAN_TXBC_TFQM_SHIFT) - -/* - * TFQS (RW) - * - * Transmit FIFO/Queue Size - * 0= No Tx FIFO/Queue - * 1-32= Number of Tx Buffers used for Tx FIFO/Queue - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_TFQS_MASK (0x3F000000UL) -#define MCAN_TXBC_TFQS_SHIFT (24U) -#define MCAN_TXBC_TFQS_SET(x) (((uint32_t)(x) << MCAN_TXBC_TFQS_SHIFT) & MCAN_TXBC_TFQS_MASK) -#define MCAN_TXBC_TFQS_GET(x) (((uint32_t)(x) & MCAN_TXBC_TFQS_MASK) >> MCAN_TXBC_TFQS_SHIFT) - -/* - * NDTB (RW) - * - * Number of Dedicated Transmit Buffers - * 0= No Dedicated Tx Buffers - * 1-32= Number of Dedicated Tx Buffers - * >32= Values greater than 32 are interpreted as 32 - */ -#define MCAN_TXBC_NDTB_MASK (0x3F0000UL) -#define MCAN_TXBC_NDTB_SHIFT (16U) -#define MCAN_TXBC_NDTB_SET(x) (((uint32_t)(x) << MCAN_TXBC_NDTB_SHIFT) & MCAN_TXBC_NDTB_MASK) -#define MCAN_TXBC_NDTB_GET(x) (((uint32_t)(x) & MCAN_TXBC_NDTB_MASK) >> MCAN_TXBC_NDTB_SHIFT) - -/* - * TBSA (RW) - * - * Tx Buffers Start Address - * Start address of Tx Buffers section in Message RAM (32-bit word address, see Figure 2). - * Note: Be aware that the sum of TFQS and NDTB may be not greater than 32. There is no check for erroneous configurations. The Tx Buffers section in the Message RAM starts with the dedicated Tx Buffers. - */ -#define MCAN_TXBC_TBSA_MASK (0xFFFCU) -#define MCAN_TXBC_TBSA_SHIFT (2U) -#define MCAN_TXBC_TBSA_SET(x) (((uint32_t)(x) << MCAN_TXBC_TBSA_SHIFT) & MCAN_TXBC_TBSA_MASK) -#define MCAN_TXBC_TBSA_GET(x) (((uint32_t)(x) & MCAN_TXBC_TBSA_MASK) >> MCAN_TXBC_TBSA_SHIFT) - -/* Bitfield definition for register: TXFQS */ -/* - * TFQF (R) - * - * Tx FIFO/Queue Full - * 0= Tx FIFO/Queue not full - * 1= Tx FIFO/Queue full - */ -#define MCAN_TXFQS_TFQF_MASK (0x200000UL) -#define MCAN_TXFQS_TFQF_SHIFT (21U) -#define MCAN_TXFQS_TFQF_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQF_MASK) >> MCAN_TXFQS_TFQF_SHIFT) - -/* - * TFQPI (R) - * - * Tx FIFO/Queue Put Index - * Tx FIFO/Queue write index pointer, range 0 to 31. - */ -#define MCAN_TXFQS_TFQPI_MASK (0x1F0000UL) -#define MCAN_TXFQS_TFQPI_SHIFT (16U) -#define MCAN_TXFQS_TFQPI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFQPI_MASK) >> MCAN_TXFQS_TFQPI_SHIFT) - -/* - * TFGI (R) - * - * Tx FIFO Get Index - * Tx FIFO read index pointer, range 0 to 31. Read as zero when Tx Queue operation is configured - * (TXBC.TFQM = ‘1’). - */ -#define MCAN_TXFQS_TFGI_MASK (0x1F00U) -#define MCAN_TXFQS_TFGI_SHIFT (8U) -#define MCAN_TXFQS_TFGI_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFGI_MASK) >> MCAN_TXFQS_TFGI_SHIFT) - -/* - * TFFL (R) - * - * Tx FIFO Free Level - * Number of consecutive free Tx FIFO elements starting from TFGI, range 0 to 32. Read as zero when Tx Queue operation is configured (TXBC.TFQM = ‘1’) - * Note: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue, the Put and Get Indices indicate the number of the Tx Buffer starting with - * the first dedicated Tx Buffers. - * Example: For a configuration of 12 dedicated Tx Buffers and a Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth buffer of the Tx FIFO. - */ -#define MCAN_TXFQS_TFFL_MASK (0x3FU) -#define MCAN_TXFQS_TFFL_SHIFT (0U) -#define MCAN_TXFQS_TFFL_GET(x) (((uint32_t)(x) & MCAN_TXFQS_TFFL_MASK) >> MCAN_TXFQS_TFFL_SHIFT) - -/* Bitfield definition for register: TXESC */ -/* - * TBDS (RW) - * - * Tx Buffer Data Field Size - * 000= 8 byte data field - * 001= 12 byte data field - * 010= 16 byte data field - * 011= 20 byte data field - * 100= 24 byte data field - * 101= 32 byte data field - * 110= 48 byte data field - * 111= 64 byte data field - * Note: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size TXESC.TBDS, the bytes not defined by the Tx Buffer are transmitted as “0xCC” (padding bytes). - */ -#define MCAN_TXESC_TBDS_MASK (0x7U) -#define MCAN_TXESC_TBDS_SHIFT (0U) -#define MCAN_TXESC_TBDS_SET(x) (((uint32_t)(x) << MCAN_TXESC_TBDS_SHIFT) & MCAN_TXESC_TBDS_MASK) -#define MCAN_TXESC_TBDS_GET(x) (((uint32_t)(x) & MCAN_TXESC_TBDS_MASK) >> MCAN_TXESC_TBDS_SHIFT) - -/* Bitfield definition for register: TXBRP */ -/* - * TRP (R) - * - * Transmission Request Pending - * Each Tx Buffer has its own Transmission Request Pending bit. The bits are set via register TXBAR.The bits are reset after a requested transmission has completed or has been cancelled via register - * TXBCR. - * TXBRP bits are set only for those Tx Buffers configured via TXBC. After a TXBRP bit has been set, a Tx scan (see Section 3.5, Tx Handling) is started to check for the pending Tx request with the - * highest priority (Tx Buffer with lowest Message ID). - * A cancellation request resets the corresponding transmission request pending bit of register TXBRP. In case a transmission has already been started when a cancellation is requested, - * this is done at the end of the transmission, regardless whether the transmission was successful or not. The cancellation request bits are reset directly after the corresponding TXBRP bit has been reset. - * After a cancellation has been requested, a finished cancellation is signalled via TXBCF - * ? after successful transmission together with the corresponding TXBTO bit - * ? when the transmission has not yet been started at the point of cancellation - * ? when the transmission has been aborted due to lost arbitration - * ? when an error occurred during frame transmission - * In DAR mode all transmissions are automatically cancelled if they are not successful. The corresponding TXBCF bit is set for all unsuccessful transmissions. - * 0= No transmission request pending - * 1= Transmission request pending - * Note: TXBRP bits which are set while a Tx scan is in progress are not considered during this particular Tx scan. In case a cancellation is requested for such a Tx Buffer, this Add Request is cancelled immediately, the corresponding TXBRP bit is reset. - */ -#define MCAN_TXBRP_TRP_MASK (0xFFFFFFFFUL) -#define MCAN_TXBRP_TRP_SHIFT (0U) -#define MCAN_TXBRP_TRP_GET(x) (((uint32_t)(x) & MCAN_TXBRP_TRP_MASK) >> MCAN_TXBRP_TRP_SHIFT) - -/* Bitfield definition for register: TXBAR */ -/* - * AR (RW) - * - * Add Request - * Each Tx Buffer has its own Add Request bit. Writing a ‘1’ will set the corresponding Add Request bit; writing a ‘0’ has no impact. This enables the Host to set transmission requests for multiple Tx - * Buffers with one write to TXBAR. TXBAR bits are set only for those Tx Buffers configured via TXBC. - * When no Tx scan is running, the bits are reset immediately, else the bits remain set until the Tx scan process has completed. - * 0= No transmission request added - * 1= Transmission requested added - * Note: If an add request is applied for a Tx Buffer with pending transmission request (corresponding TXBRP bit already set), this add request is ignored. - */ -#define MCAN_TXBAR_AR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBAR_AR_SHIFT (0U) -#define MCAN_TXBAR_AR_SET(x) (((uint32_t)(x) << MCAN_TXBAR_AR_SHIFT) & MCAN_TXBAR_AR_MASK) -#define MCAN_TXBAR_AR_GET(x) (((uint32_t)(x) & MCAN_TXBAR_AR_MASK) >> MCAN_TXBAR_AR_SHIFT) - -/* Bitfield definition for register: TXBCR */ -/* - * CR (RW) - * - * Cancellation Request - * Each Tx Buffer has its own Cancellation Request bit. Writing a ‘1’ will set the corresponding Cancellation Request bit; writing a ‘0’ has no impact. - * This enables the Host to set cancellation requests for multiple Tx Buffers with one write to TXBCR. TXBCR bits are set only for those Tx Buffers configured via TXBC. The bits remain set until the corresponding bit of TXBRP is reset. - * 0= No cancellation pending - * 1= Cancellation pending - */ -#define MCAN_TXBCR_CR_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCR_CR_SHIFT (0U) -#define MCAN_TXBCR_CR_SET(x) (((uint32_t)(x) << MCAN_TXBCR_CR_SHIFT) & MCAN_TXBCR_CR_MASK) -#define MCAN_TXBCR_CR_GET(x) (((uint32_t)(x) & MCAN_TXBCR_CR_MASK) >> MCAN_TXBCR_CR_SHIFT) - -/* Bitfield definition for register: TXBTO */ -/* - * TO (R) - * - * Transmission Occurred - * Each Tx Buffer has its own Transmission Occurred bit. The bits are set when the corresponding TXBRP bit is cleared after a successful transmission. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmission occurred - * 1= Transmission occurred - */ -#define MCAN_TXBTO_TO_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTO_TO_SHIFT (0U) -#define MCAN_TXBTO_TO_GET(x) (((uint32_t)(x) & MCAN_TXBTO_TO_MASK) >> MCAN_TXBTO_TO_SHIFT) - -/* Bitfield definition for register: TXBCF */ -/* - * CF (R) - * - * Cancellation Finished - * Each Tx Buffer has its own Cancellation Finished bit. The bits are set when the corresponding TXBRP bit is cleared after a cancellation was requested via TXBCR. - * In case the corresponding TXBRP bit was not set at the point of cancellation, CF is set immediately. The bits are reset when a new transmission is requested by writing a ‘1’ to the corresponding bit of register TXBAR. - * 0= No transmit buffer cancellation - * 1= Transmit buffer cancellation finished - */ -#define MCAN_TXBCF_CF_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCF_CF_SHIFT (0U) -#define MCAN_TXBCF_CF_GET(x) (((uint32_t)(x) & MCAN_TXBCF_CF_MASK) >> MCAN_TXBCF_CF_SHIFT) - -/* Bitfield definition for register: TXBTIE */ -/* - * TIE (RW) - * - * Transmission Interrupt Enable - * Each Tx Buffer has its own Transmission Interrupt Enable bit. - * 0= Transmission interrupt disabled - * 1= Transmission interrupt enable - */ -#define MCAN_TXBTIE_TIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBTIE_TIE_SHIFT (0U) -#define MCAN_TXBTIE_TIE_SET(x) (((uint32_t)(x) << MCAN_TXBTIE_TIE_SHIFT) & MCAN_TXBTIE_TIE_MASK) -#define MCAN_TXBTIE_TIE_GET(x) (((uint32_t)(x) & MCAN_TXBTIE_TIE_MASK) >> MCAN_TXBTIE_TIE_SHIFT) - -/* Bitfield definition for register: TXBCIE */ -/* - * CFIE (RW) - * - * Cancellation Finished Interrupt Enable - * Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit. - * 0= Cancellation finished interrupt disabled - * 1= Cancellation finished interrupt enabled - */ -#define MCAN_TXBCIE_CFIE_MASK (0xFFFFFFFFUL) -#define MCAN_TXBCIE_CFIE_SHIFT (0U) -#define MCAN_TXBCIE_CFIE_SET(x) (((uint32_t)(x) << MCAN_TXBCIE_CFIE_SHIFT) & MCAN_TXBCIE_CFIE_MASK) -#define MCAN_TXBCIE_CFIE_GET(x) (((uint32_t)(x) & MCAN_TXBCIE_CFIE_MASK) >> MCAN_TXBCIE_CFIE_SHIFT) - -/* Bitfield definition for register: TXEFC */ -/* - * EFWM (RW) - * - * Event FIFO Watermark - * 0= Watermark interrupt disabled - * 1-32= Level for Tx Event FIFO watermark interrupt (IR.TEFW) - * >32= Watermark interrupt disabled - */ -#define MCAN_TXEFC_EFWM_MASK (0x3F000000UL) -#define MCAN_TXEFC_EFWM_SHIFT (24U) -#define MCAN_TXEFC_EFWM_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFWM_SHIFT) & MCAN_TXEFC_EFWM_MASK) -#define MCAN_TXEFC_EFWM_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFWM_MASK) >> MCAN_TXEFC_EFWM_SHIFT) - -/* - * EFS (RW) - * - * Event FIFO Size - * 0= Tx Event FIFO disabled - * 1-32= Number of Tx Event FIFO elements - * >32= Values greater than 32 are interpreted as 32 - * The Tx Event FIFO elements are indexed from 0 to EFS - 1 - */ -#define MCAN_TXEFC_EFS_MASK (0x3F0000UL) -#define MCAN_TXEFC_EFS_SHIFT (16U) -#define MCAN_TXEFC_EFS_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFS_SHIFT) & MCAN_TXEFC_EFS_MASK) -#define MCAN_TXEFC_EFS_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFS_MASK) >> MCAN_TXEFC_EFS_SHIFT) - -/* - * EFSA (RW) - * - * Event FIFO Start Address - * Start address of Tx Event FIFO in Message RAM (32-bit word address) - */ -#define MCAN_TXEFC_EFSA_MASK (0xFFFCU) -#define MCAN_TXEFC_EFSA_SHIFT (2U) -#define MCAN_TXEFC_EFSA_SET(x) (((uint32_t)(x) << MCAN_TXEFC_EFSA_SHIFT) & MCAN_TXEFC_EFSA_MASK) -#define MCAN_TXEFC_EFSA_GET(x) (((uint32_t)(x) & MCAN_TXEFC_EFSA_MASK) >> MCAN_TXEFC_EFSA_SHIFT) - -/* Bitfield definition for register: TXEFS */ -/* - * TEFL (R) - * - * Tx Event FIFO Element Lost - * This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. - * 0= No Tx Event FIFO element lost - * 1= Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. - */ -#define MCAN_TXEFS_TEFL_MASK (0x2000000UL) -#define MCAN_TXEFS_TEFL_SHIFT (25U) -#define MCAN_TXEFS_TEFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_TEFL_MASK) >> MCAN_TXEFS_TEFL_SHIFT) - -/* - * EFF (R) - * - * Event FIFO Full - * 0= Tx Event FIFO not full - * 1= Tx Event FIFO full - */ -#define MCAN_TXEFS_EFF_MASK (0x1000000UL) -#define MCAN_TXEFS_EFF_SHIFT (24U) -#define MCAN_TXEFS_EFF_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFF_MASK) >> MCAN_TXEFS_EFF_SHIFT) - -/* - * EFPI (R) - * - * Event FIFO Put Index - * Tx Event FIFO write index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFPI_MASK (0x1F0000UL) -#define MCAN_TXEFS_EFPI_SHIFT (16U) -#define MCAN_TXEFS_EFPI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFPI_MASK) >> MCAN_TXEFS_EFPI_SHIFT) - -/* - * EFGI (R) - * - * Event FIFO Get Index - * Tx Event FIFO read index pointer, range 0 to 31. - */ -#define MCAN_TXEFS_EFGI_MASK (0x1F00U) -#define MCAN_TXEFS_EFGI_SHIFT (8U) -#define MCAN_TXEFS_EFGI_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFGI_MASK) >> MCAN_TXEFS_EFGI_SHIFT) - -/* - * EFFL (R) - * - * Event FIFO Fill Level - * Number of elements stored in Tx Event FIFO, range 0 to 32. - */ -#define MCAN_TXEFS_EFFL_MASK (0x3FU) -#define MCAN_TXEFS_EFFL_SHIFT (0U) -#define MCAN_TXEFS_EFFL_GET(x) (((uint32_t)(x) & MCAN_TXEFS_EFFL_MASK) >> MCAN_TXEFS_EFFL_SHIFT) - -/* Bitfield definition for register: TXEFA */ -/* - * EFAI (RW) - * - * Event FIFO Acknowledge Index - * After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI. This will set the Tx Event FIFO Get - * Index TXEFS.EFGI to EFAI + 1 and update the Event FIFO Fill Level TXEFS.EFFL. - */ -#define MCAN_TXEFA_EFAI_MASK (0x1FU) -#define MCAN_TXEFA_EFAI_SHIFT (0U) -#define MCAN_TXEFA_EFAI_SET(x) (((uint32_t)(x) << MCAN_TXEFA_EFAI_SHIFT) & MCAN_TXEFA_EFAI_MASK) -#define MCAN_TXEFA_EFAI_GET(x) (((uint32_t)(x) & MCAN_TXEFA_EFAI_MASK) >> MCAN_TXEFA_EFAI_SHIFT) - -/* Bitfield definition for register array: TS_SEL */ -/* - * TS (R) - * - * Timestamp Word TS - * default can save 16 timestamps with 32bit; - * if ts64_en is set, then work at 64bit mode, can save 8 timestamps with 01/23/45…. - */ -#define MCAN_TS_SEL_TS_MASK (0xFFFFFFFFUL) -#define MCAN_TS_SEL_TS_SHIFT (0U) -#define MCAN_TS_SEL_TS_GET(x) (((uint32_t)(x) & MCAN_TS_SEL_TS_MASK) >> MCAN_TS_SEL_TS_SHIFT) - -/* Bitfield definition for register: CREL */ -/* - * REL (R) - * - * Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_REL_MASK (0xF0000000UL) -#define MCAN_CREL_REL_SHIFT (28U) -#define MCAN_CREL_REL_GET(x) (((uint32_t)(x) & MCAN_CREL_REL_MASK) >> MCAN_CREL_REL_SHIFT) - -/* - * STEP (R) - * - * Step of Core Release - * One digit, BCD-coded. - */ -#define MCAN_CREL_STEP_MASK (0xF000000UL) -#define MCAN_CREL_STEP_SHIFT (24U) -#define MCAN_CREL_STEP_GET(x) (((uint32_t)(x) & MCAN_CREL_STEP_MASK) >> MCAN_CREL_STEP_SHIFT) - -/* - * SUBSTEP (R) - * - * Sub-step of Core Release - * One digit, BCD-coded - */ -#define MCAN_CREL_SUBSTEP_MASK (0xF00000UL) -#define MCAN_CREL_SUBSTEP_SHIFT (20U) -#define MCAN_CREL_SUBSTEP_GET(x) (((uint32_t)(x) & MCAN_CREL_SUBSTEP_MASK) >> MCAN_CREL_SUBSTEP_SHIFT) - -/* - * YEAR (R) - * - * Timestamp Year - * One digit, BCD-coded. This field is set by generic parameter on - * synthesis. - */ -#define MCAN_CREL_YEAR_MASK (0xF0000UL) -#define MCAN_CREL_YEAR_SHIFT (16U) -#define MCAN_CREL_YEAR_GET(x) (((uint32_t)(x) & MCAN_CREL_YEAR_MASK) >> MCAN_CREL_YEAR_SHIFT) - -/* - * MON (R) - * - * Timestamp Month - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_MON_MASK (0xFF00U) -#define MCAN_CREL_MON_SHIFT (8U) -#define MCAN_CREL_MON_GET(x) (((uint32_t)(x) & MCAN_CREL_MON_MASK) >> MCAN_CREL_MON_SHIFT) - -/* - * DAY (R) - * - * Timestamp Day - * Two digits, BCD-coded. This field is set by generic parameter - * on synthesis. - */ -#define MCAN_CREL_DAY_MASK (0xFFU) -#define MCAN_CREL_DAY_SHIFT (0U) -#define MCAN_CREL_DAY_GET(x) (((uint32_t)(x) & MCAN_CREL_DAY_MASK) >> MCAN_CREL_DAY_SHIFT) - -/* Bitfield definition for register: TSCFG */ -/* - * TBPRE (RW) - * - * Timebase Prescaler - * 0x00 to 0xFF - * The value by which the oscillator frequency is divided for - * generating the timebase counter clock. Valid values for the - * Timebase Prescaler are 0 to 255. The actual interpretation by - * the hardware of this value is such that one more than the value - * programmed here is used. Affects only the TSU internal - * timebase. When the internal timebase is excluded by synthesis, - * TBPRE[7:0] is fixed to 0x00, the Timestamp Prescaler is not - * used. - */ -#define MCAN_TSCFG_TBPRE_MASK (0xFF00U) -#define MCAN_TSCFG_TBPRE_SHIFT (8U) -#define MCAN_TSCFG_TBPRE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBPRE_SHIFT) & MCAN_TSCFG_TBPRE_MASK) -#define MCAN_TSCFG_TBPRE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBPRE_MASK) >> MCAN_TSCFG_TBPRE_SHIFT) - -/* - * EN64 (RW) - * - * set to use 64bit timestamp. - * when enabled, tsu can save up to 8 different timestamps, TS(k) and TS(k+1) are used for one 64bit timestamp, k is 0~7. - * TSP can be used to select different one - */ -#define MCAN_TSCFG_EN64_MASK (0x8U) -#define MCAN_TSCFG_EN64_SHIFT (3U) -#define MCAN_TSCFG_EN64_SET(x) (((uint32_t)(x) << MCAN_TSCFG_EN64_SHIFT) & MCAN_TSCFG_EN64_MASK) -#define MCAN_TSCFG_EN64_GET(x) (((uint32_t)(x) & MCAN_TSCFG_EN64_MASK) >> MCAN_TSCFG_EN64_SHIFT) - -/* - * SCP (RW) - * - * Select Capturing Position - * 0: Capture Timestamp at EOF - * 1: Capture Timestamp at SOF - */ -#define MCAN_TSCFG_SCP_MASK (0x4U) -#define MCAN_TSCFG_SCP_SHIFT (2U) -#define MCAN_TSCFG_SCP_SET(x) (((uint32_t)(x) << MCAN_TSCFG_SCP_SHIFT) & MCAN_TSCFG_SCP_MASK) -#define MCAN_TSCFG_SCP_GET(x) (((uint32_t)(x) & MCAN_TSCFG_SCP_MASK) >> MCAN_TSCFG_SCP_SHIFT) - -/* - * TBCS (RW) - * - * Timebase Counter Select - * When the internal timebase is excluded by synthesis, TBCS is - * fixed to ‘1’. - * 0: Timestamp value captured from internal timebase counter, - * ATB.TB[31:0] is the internal timbase counter - * 1: Timestamp value captured from input tsu_tbin[31:0],ATB.TB[31:0] is tsu_tbin[31:0] - */ -#define MCAN_TSCFG_TBCS_MASK (0x2U) -#define MCAN_TSCFG_TBCS_SHIFT (1U) -#define MCAN_TSCFG_TBCS_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TBCS_SHIFT) & MCAN_TSCFG_TBCS_MASK) -#define MCAN_TSCFG_TBCS_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TBCS_MASK) >> MCAN_TSCFG_TBCS_SHIFT) - -/* - * TSUE (RW) - * - * Timestamp Unit Enable - * 0: TSU disabled - * 1: TSU enabled - */ -#define MCAN_TSCFG_TSUE_MASK (0x1U) -#define MCAN_TSCFG_TSUE_SHIFT (0U) -#define MCAN_TSCFG_TSUE_SET(x) (((uint32_t)(x) << MCAN_TSCFG_TSUE_SHIFT) & MCAN_TSCFG_TSUE_MASK) -#define MCAN_TSCFG_TSUE_GET(x) (((uint32_t)(x) & MCAN_TSCFG_TSUE_MASK) >> MCAN_TSCFG_TSUE_SHIFT) - -/* Bitfield definition for register: TSS1 */ -/* - * TSL (R) - * - * Timestamp Lost - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when the timestamp stored in the related Timestamp register was overwritten before it was read. - * Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSL_MASK (0xFFFF0000UL) -#define MCAN_TSS1_TSL_SHIFT (16U) -#define MCAN_TSS1_TSL_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSL_MASK) >> MCAN_TSS1_TSL_SHIFT) - -/* - * TSN (R) - * - * Timestamp New - * Each Timestamp register (TS0-TS15) is assigned one bit. The bits are set when a timestamp was stored in the related - * Timestamp register. Reading a Timestamp register resets the related bit. - */ -#define MCAN_TSS1_TSN_MASK (0xFFFFU) -#define MCAN_TSS1_TSN_SHIFT (0U) -#define MCAN_TSS1_TSN_GET(x) (((uint32_t)(x) & MCAN_TSS1_TSN_MASK) >> MCAN_TSS1_TSN_SHIFT) - -/* Bitfield definition for register: TSS2 */ -/* - * TSP (R) - * - * Timestamp Pointer - * The Timestamp Pointer is incremented by one each time a timestamp is captured. From its maximum value (3, 7, or 15 - * depending on number_ts_g), it is incremented to 0. - * Value also signalled on output m_can_tsp[3:0]. - */ -#define MCAN_TSS2_TSP_MASK (0xFU) -#define MCAN_TSS2_TSP_SHIFT (0U) -#define MCAN_TSS2_TSP_GET(x) (((uint32_t)(x) & MCAN_TSS2_TSP_MASK) >> MCAN_TSS2_TSP_SHIFT) - -/* Bitfield definition for register: ATB */ -/* - * TB (RC) - * - * timebase for timestamp generation 31-0 - */ -#define MCAN_ATB_TB_MASK (0xFFFFFFFFUL) -#define MCAN_ATB_TB_SHIFT (0U) -#define MCAN_ATB_TB_GET(x) (((uint32_t)(x) & MCAN_ATB_TB_MASK) >> MCAN_ATB_TB_SHIFT) - -/* Bitfield definition for register: ATBH */ -/* - * TBH (RC) - * - * timebase for timestamp generation 63-32 - */ -#define MCAN_ATBH_TBH_MASK (0xFFFFFFFFUL) -#define MCAN_ATBH_TBH_SHIFT (0U) -#define MCAN_ATBH_TBH_GET(x) (((uint32_t)(x) & MCAN_ATBH_TBH_MASK) >> MCAN_ATBH_TBH_SHIFT) - -/* Bitfield definition for register: GLB_CTL */ -/* - * M_CAN_STBY (RW) - * - * m_can standby control - */ -#define MCAN_GLB_CTL_M_CAN_STBY_MASK (0x80000000UL) -#define MCAN_GLB_CTL_M_CAN_STBY_SHIFT (31U) -#define MCAN_GLB_CTL_M_CAN_STBY_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_M_CAN_STBY_SHIFT) & MCAN_GLB_CTL_M_CAN_STBY_MASK) -#define MCAN_GLB_CTL_M_CAN_STBY_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_M_CAN_STBY_MASK) >> MCAN_GLB_CTL_M_CAN_STBY_SHIFT) - -/* - * STBY_CLR_EN (RW) - * - * m_can standby clear control - * 0:controlled by software by standby bit[bit31] - * 1:auto clear standby by hardware when rx data is 0 - */ -#define MCAN_GLB_CTL_STBY_CLR_EN_MASK (0x40000000UL) -#define MCAN_GLB_CTL_STBY_CLR_EN_SHIFT (30U) -#define MCAN_GLB_CTL_STBY_CLR_EN_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) -#define MCAN_GLB_CTL_STBY_CLR_EN_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_CLR_EN_MASK) >> MCAN_GLB_CTL_STBY_CLR_EN_SHIFT) - -/* - * STBY_POL (RW) - * - * standby polarity selection - */ -#define MCAN_GLB_CTL_STBY_POL_MASK (0x20000000UL) -#define MCAN_GLB_CTL_STBY_POL_SHIFT (29U) -#define MCAN_GLB_CTL_STBY_POL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_STBY_POL_SHIFT) & MCAN_GLB_CTL_STBY_POL_MASK) -#define MCAN_GLB_CTL_STBY_POL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_STBY_POL_MASK) >> MCAN_GLB_CTL_STBY_POL_SHIFT) - -/* - * TSU_TBIN_SEL (RW) - * - * external timestamp select. each CAN block has 4 timestamp input, this register is used to select one of them as timestame if TSCFG.TBCS is set to 1 - */ -#define MCAN_GLB_CTL_TSU_TBIN_SEL_MASK (0x3U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT (0U) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_SET(x) (((uint32_t)(x) << MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) -#define MCAN_GLB_CTL_TSU_TBIN_SEL_GET(x) (((uint32_t)(x) & MCAN_GLB_CTL_TSU_TBIN_SEL_MASK) >> MCAN_GLB_CTL_TSU_TBIN_SEL_SHIFT) - -/* Bitfield definition for register: GLB_STATUS */ -/* - * M_CAN_INT1 (R) - * - * m_can interrupt status1 - */ -#define MCAN_GLB_STATUS_M_CAN_INT1_MASK (0x8U) -#define MCAN_GLB_STATUS_M_CAN_INT1_SHIFT (3U) -#define MCAN_GLB_STATUS_M_CAN_INT1_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT1_MASK) >> MCAN_GLB_STATUS_M_CAN_INT1_SHIFT) - -/* - * M_CAN_INT0 (R) - * - * m_can interrupt status0 - */ -#define MCAN_GLB_STATUS_M_CAN_INT0_MASK (0x4U) -#define MCAN_GLB_STATUS_M_CAN_INT0_SHIFT (2U) -#define MCAN_GLB_STATUS_M_CAN_INT0_GET(x) (((uint32_t)(x) & MCAN_GLB_STATUS_M_CAN_INT0_MASK) >> MCAN_GLB_STATUS_M_CAN_INT0_SHIFT) - - - -/* TS_SEL register group index macro definition */ -#define MCAN_TS_SEL_TS_SEL0 (0UL) -#define MCAN_TS_SEL_TS_SEL1 (1UL) -#define MCAN_TS_SEL_TS_SEL2 (2UL) -#define MCAN_TS_SEL_TS_SEL3 (3UL) -#define MCAN_TS_SEL_TS_SEL4 (4UL) -#define MCAN_TS_SEL_TS_SEL5 (5UL) -#define MCAN_TS_SEL_TS_SEL6 (6UL) -#define MCAN_TS_SEL_TS_SEL7 (7UL) -#define MCAN_TS_SEL_TS_SEL8 (8UL) -#define MCAN_TS_SEL_TS_SEL9 (9UL) -#define MCAN_TS_SEL_TS_SEL10 (10UL) -#define MCAN_TS_SEL_TS_SEL11 (11UL) -#define MCAN_TS_SEL_TS_SEL12 (12UL) -#define MCAN_TS_SEL_TS_SEL13 (13UL) -#define MCAN_TS_SEL_TS_SEL14 (14UL) -#define MCAN_TS_SEL_TS_SEL15 (15UL) - - -#endif /* HPM_MCAN_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mchtmr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mchtmr_regs.h deleted file mode 100644 index d9dfe58a7b9..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mchtmr_regs.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MCHTMR_H -#define HPM_MCHTMR_H - -typedef struct { - __RW uint64_t MTIME; /* 0x0: Machine Time */ - __RW uint64_t MTIMECMP; /* 0x8: Machine Time Compare */ -} MCHTMR_Type; - - -/* Bitfield definition for register: MTIME */ -/* - * MTIME (RW) - * - * Machine time - */ -#define MCHTMR_MTIME_MTIME_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIME_MTIME_SHIFT (0U) -#define MCHTMR_MTIME_MTIME_SET(x) (((uint64_t)(x) << MCHTMR_MTIME_MTIME_SHIFT) & MCHTMR_MTIME_MTIME_MASK) -#define MCHTMR_MTIME_MTIME_GET(x) (((uint64_t)(x) & MCHTMR_MTIME_MTIME_MASK) >> MCHTMR_MTIME_MTIME_SHIFT) - -/* Bitfield definition for register: MTIMECMP */ -/* - * MTIMECMP (RW) - * - * Machine time compare - */ -#define MCHTMR_MTIMECMP_MTIMECMP_MASK (0xFFFFFFFFFFFFFFFFULL) -#define MCHTMR_MTIMECMP_MTIMECMP_SHIFT (0U) -#define MCHTMR_MTIMECMP_MTIMECMP_SET(x) (((uint64_t)(x) << MCHTMR_MTIMECMP_MTIMECMP_SHIFT) & MCHTMR_MTIMECMP_MTIMECMP_MASK) -#define MCHTMR_MTIMECMP_MTIMECMP_GET(x) (((uint64_t)(x) & MCHTMR_MTIMECMP_MTIMECMP_MASK) >> MCHTMR_MTIMECMP_MTIMECMP_SHIFT) - - - - -#endif /* HPM_MCHTMR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mono_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mono_regs.h deleted file mode 100644 index 2c6c3a3d2fe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mono_regs.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MONO_H -#define HPM_MONO_H - -typedef struct { - __RW uint32_t MONOL; /* 0x0: Low part of monotonic counter */ - __RW uint32_t MONOH; /* 0x4: High part of monotonic counter */ -} MONO_Type; - - -/* Bitfield definition for register: MONOL */ -/* - * COUNTER (RW) - * - * low part of monotonica counter, write to this counter will cause counter increase by 1 - */ -#define MONO_MONOL_COUNTER_MASK (0xFFFFFFFFUL) -#define MONO_MONOL_COUNTER_SHIFT (0U) -#define MONO_MONOL_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOL_COUNTER_SHIFT) & MONO_MONOL_COUNTER_MASK) -#define MONO_MONOL_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOL_COUNTER_MASK) >> MONO_MONOL_COUNTER_SHIFT) - -/* Bitfield definition for register: MONOH */ -/* - * EPOCH (RW) - * - * Fuse value for high part of monotonica - */ -#define MONO_MONOH_EPOCH_MASK (0xFFFF0000UL) -#define MONO_MONOH_EPOCH_SHIFT (16U) -#define MONO_MONOH_EPOCH_SET(x) (((uint32_t)(x) << MONO_MONOH_EPOCH_SHIFT) & MONO_MONOH_EPOCH_MASK) -#define MONO_MONOH_EPOCH_GET(x) (((uint32_t)(x) & MONO_MONOH_EPOCH_MASK) >> MONO_MONOH_EPOCH_SHIFT) - -/* - * COUNTER (RW) - * - * high part of monotonica counter, write to this counter will cause counter increase by 1 if low part overflow - */ -#define MONO_MONOH_COUNTER_MASK (0xFFFFU) -#define MONO_MONOH_COUNTER_SHIFT (0U) -#define MONO_MONOH_COUNTER_SET(x) (((uint32_t)(x) << MONO_MONOH_COUNTER_SHIFT) & MONO_MONOH_COUNTER_MASK) -#define MONO_MONOH_COUNTER_GET(x) (((uint32_t)(x) & MONO_MONOH_COUNTER_MASK) >> MONO_MONOH_COUNTER_SHIFT) - - - - -#endif /* HPM_MONO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mtg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mtg_regs.h deleted file mode 100644 index 4baeb7b62ae..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_mtg_regs.h +++ /dev/null @@ -1,1473 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_MTG_H -#define HPM_MTG_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: tra_control */ - __RW uint32_t SHIFT; /* 0x4: tra_shift */ - __RW uint32_t LINK; /* 0x8: tra_link */ - __R uint8_t RESERVED0[20]; /* 0xC - 0x1F: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x20: tra_cmd_control */ - __RW uint32_t REV_PRESET; /* 0x24: tra_cmd_rev_preset */ - __RW uint32_t POS_PRESET; /* 0x28: tra_cmd_pos_preset */ - __RW uint32_t VEL_PRESET; /* 0x2C: tra_cmd_vel_preset */ - __RW uint32_t ACC_PRESET; /* 0x30: tra_cmd_acc_preset */ - __RW uint32_t JER_PRESET; /* 0x34: tra_cmd_jer_preset */ - __R uint32_t TIMESTAMP; /* 0x38: tra_cmd_timestamp */ - __R uint8_t RESERVED0[4]; /* 0x3C - 0x3F: Reserved */ - } CMD[4]; - __R uint32_t LOCK_REV; /* 0xA0: tra_lock_rev */ - __R uint32_t LOCK_POS; /* 0xA4: tra_lock_pos */ - __R uint32_t LOCK_VEL; /* 0xA8: tra_lock_vel */ - __R uint32_t LOCK_ACC; /* 0xAC: tra_lock_acc */ - __R uint32_t LOCK_TIME; /* 0xB0: tra_lock_time */ - __R uint8_t RESERVED1[12]; /* 0xB4 - 0xBF: Reserved */ - __RW uint32_t STEP_LIMIT_CTRL; /* 0xC0: tra_step_limit_ctrl */ - __RW uint32_t VEL_STEP_MAX; /* 0xC4: tra_vel_step_max */ - __RW uint32_t VEL_STEP_MIN; /* 0xC8: tra_vel_step_min */ - __RW uint32_t POS_STEP_MAX; /* 0xCC: tra_pos_step_max */ - __RW uint32_t POS_STEP_MIN; /* 0xD0: tra_pos_step_min */ - __RW uint32_t VEL_LIMIT_P; /* 0xD4: tra_vel_limit_p */ - __RW uint32_t VEL_LIMIT_N; /* 0xD8: tra_vel_limit_n */ - __R uint8_t RESERVED2[3876]; /* 0xDC - 0xFFF: Reserved */ - } TRA[2]; - struct { - __RW uint32_t CONTROL; /* 0x2000: event_control */ - __RW uint32_t PRESET_0; /* 0x2004: event_preset_0 */ - __RW uint32_t PRESET_1; /* 0x2008: event_preset_1 */ - __RW uint32_t PRESET_2; /* 0x200C: event_preset_2 */ - __RW uint32_t PRESET_3; /* 0x2010: event_preset_3 */ - __R uint32_t TIMESTAMP; /* 0x2014: event_timestamp */ - __R uint8_t RESERVED0[8]; /* 0x2018 - 0x201F: Reserved */ - } EVENT[4]; - __RW uint32_t SW_EVENT; /* 0x2080: sw_event */ - __W uint32_t SW_GLB_RESET; /* 0x2084: sw_glb_reset */ - __R uint8_t RESERVED0[3960]; /* 0x2088 - 0x2FFF: Reserved */ - __RW uint32_t FILTER_CONTROL; /* 0x3000: filter_control */ - __R uint8_t RESERVED1[12]; /* 0x3004 - 0x300F: Reserved */ - __RW uint32_t FILTER_REV_VALUE; /* 0x3010: filter_rev_value */ - __RW uint32_t FILTER_POS_VALUE; /* 0x3014: filter_pos_value */ - __RW uint32_t FILTER_VEL_VALUE; /* 0x3018: filter_vel_value */ - __RW uint32_t FILTER_ACC_VALUE; /* 0x301C: filter_acc_value */ - __RW uint32_t FILTER_MOT_SEL; /* 0x3020: filter_mot_sel */ - __RW uint32_t FILTER_STAGE_SEL; /* 0x3024: filter_stage_sel */ - __RW uint32_t FILTER_TIME_CONSTANT_TP; /* 0x3028: filter_time_constant_tp */ - __RW uint32_t FILTER_TIME_CONSTANT_TZ; /* 0x302C: filter_time_constant_tz */ - __RW uint32_t FILTER_TIME_CONSTANT_TZ_1; /* 0x3030: filter_time_constant_tz_1 */ - __RW uint32_t FILTER_ZERO_TZ_SEL; /* 0x3034: filter_zero_tz_sel */ - __RW uint32_t FILTER_GAIN; /* 0x3038: filter_gain */ - __RW uint32_t FILTER_STAGE_SHIFT0; /* 0x303C: filter_stage_shift0 */ - __RW uint32_t FILTER_STAGE_SHIFT1; /* 0x3040: filter_stage_shift1 */ - __RW uint32_t FILTER_PARAM_SHIFT; /* 0x3044: filter_param_shift */ - __RW uint32_t FILTER_TIME_SHIFT; /* 0x3048: filter_time_shift */ - __RW uint32_t FILTER_FF_SHIFT; /* 0x304C: filter_ff_shift */ - __RW uint32_t FILTER_TIME1_SW_ADJUST; /* 0x3050: filter_time1_sw_adjust */ - __RW uint32_t FILTER_TIME0_SW_ADJUST; /* 0x3054: filter_time0_sw_adjust */ - __R uint8_t RESERVED2[8]; /* 0x3058 - 0x305F: Reserved */ - __RW uint32_t FILTER_ERROR_LIMIT_L; /* 0x3060: filter_error_limit */ - __RW uint32_t FILTER_ERROR_LIMIT_H; /* 0x3064: filter_error_limit */ - __R uint8_t RESERVED3[4]; /* 0x3068 - 0x306B: Reserved */ - __RW uint32_t FILTER_TIMEOUT_CNT; /* 0x306C: filter_timeout_cnt */ - __R uint32_t FILTER_REV_LOCK; /* 0x3070: filter_rev_lock */ - __R uint32_t FILTER_POS_LOCK; /* 0x3074: filter_pos_lock */ - __R uint32_t FILTER_VEL_LOCK; /* 0x3078: filter_vel_lock */ - __R uint32_t FILTER_ACC_LOCK; /* 0x307C: filter_acc_lock */ -} MTG_Type; - - -/* Bitfield definition for register of struct array TRA: CONTROL */ -/* - * CMD_FAIL_IRQ_EN (RW) - * - */ -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK (0x20U) -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT (5U) -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK) -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_MASK) >> MTG_TRA_CONTROL_CMD_FAIL_IRQ_EN_SHIFT) - -/* - * LOCK_IRQ_EN (RW) - * - */ -#define MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK (0x10U) -#define MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT (4U) -#define MTG_TRA_CONTROL_LOCK_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT) & MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK) -#define MTG_TRA_CONTROL_LOCK_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_LOCK_IRQ_EN_MASK) >> MTG_TRA_CONTROL_LOCK_IRQ_EN_SHIFT) - -/* - * CMD_FAIL_IRQ (W1C) - * - */ -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK (0x8U) -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT (3U) -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK) -#define MTG_TRA_CONTROL_CMD_FAIL_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_CMD_FAIL_IRQ_MASK) >> MTG_TRA_CONTROL_CMD_FAIL_IRQ_SHIFT) - -/* - * LOCK_IRQ (W1C) - * - */ -#define MTG_TRA_CONTROL_LOCK_IRQ_MASK (0x4U) -#define MTG_TRA_CONTROL_LOCK_IRQ_SHIFT (2U) -#define MTG_TRA_CONTROL_LOCK_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_LOCK_IRQ_SHIFT) & MTG_TRA_CONTROL_LOCK_IRQ_MASK) -#define MTG_TRA_CONTROL_LOCK_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_LOCK_IRQ_MASK) >> MTG_TRA_CONTROL_LOCK_IRQ_SHIFT) - -/* - * SW_LOCK (RW) - * - */ -#define MTG_TRA_CONTROL_SW_LOCK_MASK (0x2U) -#define MTG_TRA_CONTROL_SW_LOCK_SHIFT (1U) -#define MTG_TRA_CONTROL_SW_LOCK_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_SW_LOCK_SHIFT) & MTG_TRA_CONTROL_SW_LOCK_MASK) -#define MTG_TRA_CONTROL_SW_LOCK_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_SW_LOCK_MASK) >> MTG_TRA_CONTROL_SW_LOCK_SHIFT) - -/* - * OVALID_CLEAR (RW) - * - */ -#define MTG_TRA_CONTROL_OVALID_CLEAR_MASK (0x1U) -#define MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT (0U) -#define MTG_TRA_CONTROL_OVALID_CLEAR_SET(x) (((uint32_t)(x) << MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT) & MTG_TRA_CONTROL_OVALID_CLEAR_MASK) -#define MTG_TRA_CONTROL_OVALID_CLEAR_GET(x) (((uint32_t)(x) & MTG_TRA_CONTROL_OVALID_CLEAR_MASK) >> MTG_TRA_CONTROL_OVALID_CLEAR_SHIFT) - -/* Bitfield definition for register of struct array TRA: SHIFT */ -/* - * ACC_SHIFT_FAIL_IRQ (W1C) - * - */ -#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK (0x80000000UL) -#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT (31U) -#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT) & MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK) -#define MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_MASK) >> MTG_TRA_SHIFT_ACC_SHIFT_FAIL_IRQ_SHIFT) - -/* - * VEL_SHIFT_FAIL_IRQ (W1C) - * - */ -#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK (0x40000000UL) -#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT (30U) -#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT) & MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK) -#define MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_MASK) >> MTG_TRA_SHIFT_VEL_SHIFT_FAIL_IRQ_SHIFT) - -/* - * SHIFT_FAIL_EN (RW) - * - */ -#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK (0x20000000UL) -#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT (29U) -#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT) & MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK) -#define MTG_TRA_SHIFT_SHIFT_FAIL_EN_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_SHIFT_FAIL_EN_MASK) >> MTG_TRA_SHIFT_SHIFT_FAIL_EN_SHIFT) - -/* - * JER_SHIFT (RW) - * - */ -#define MTG_TRA_SHIFT_JER_SHIFT_MASK (0x700U) -#define MTG_TRA_SHIFT_JER_SHIFT_SHIFT (8U) -#define MTG_TRA_SHIFT_JER_SHIFT_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_JER_SHIFT_SHIFT) & MTG_TRA_SHIFT_JER_SHIFT_MASK) -#define MTG_TRA_SHIFT_JER_SHIFT_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_JER_SHIFT_MASK) >> MTG_TRA_SHIFT_JER_SHIFT_SHIFT) - -/* - * ACC_SHIFT (RW) - * - */ -#define MTG_TRA_SHIFT_ACC_SHIFT_MASK (0x70U) -#define MTG_TRA_SHIFT_ACC_SHIFT_SHIFT (4U) -#define MTG_TRA_SHIFT_ACC_SHIFT_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_ACC_SHIFT_SHIFT) & MTG_TRA_SHIFT_ACC_SHIFT_MASK) -#define MTG_TRA_SHIFT_ACC_SHIFT_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_ACC_SHIFT_MASK) >> MTG_TRA_SHIFT_ACC_SHIFT_SHIFT) - -/* - * VEL_SHIFT (RW) - * - */ -#define MTG_TRA_SHIFT_VEL_SHIFT_MASK (0xFU) -#define MTG_TRA_SHIFT_VEL_SHIFT_SHIFT (0U) -#define MTG_TRA_SHIFT_VEL_SHIFT_SET(x) (((uint32_t)(x) << MTG_TRA_SHIFT_VEL_SHIFT_SHIFT) & MTG_TRA_SHIFT_VEL_SHIFT_MASK) -#define MTG_TRA_SHIFT_VEL_SHIFT_GET(x) (((uint32_t)(x) & MTG_TRA_SHIFT_VEL_SHIFT_MASK) >> MTG_TRA_SHIFT_VEL_SHIFT_SHIFT) - -/* Bitfield definition for register of struct array TRA: LINK */ -/* - * LINK_CFG_3 (RW) - * - */ -#define MTG_TRA_LINK_LINK_CFG_3_MASK (0x7000U) -#define MTG_TRA_LINK_LINK_CFG_3_SHIFT (12U) -#define MTG_TRA_LINK_LINK_CFG_3_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_3_SHIFT) & MTG_TRA_LINK_LINK_CFG_3_MASK) -#define MTG_TRA_LINK_LINK_CFG_3_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_3_MASK) >> MTG_TRA_LINK_LINK_CFG_3_SHIFT) - -/* - * LINK_CFG_2 (RW) - * - */ -#define MTG_TRA_LINK_LINK_CFG_2_MASK (0x700U) -#define MTG_TRA_LINK_LINK_CFG_2_SHIFT (8U) -#define MTG_TRA_LINK_LINK_CFG_2_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_2_SHIFT) & MTG_TRA_LINK_LINK_CFG_2_MASK) -#define MTG_TRA_LINK_LINK_CFG_2_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_2_MASK) >> MTG_TRA_LINK_LINK_CFG_2_SHIFT) - -/* - * LINK_CFG_1 (RW) - * - */ -#define MTG_TRA_LINK_LINK_CFG_1_MASK (0x70U) -#define MTG_TRA_LINK_LINK_CFG_1_SHIFT (4U) -#define MTG_TRA_LINK_LINK_CFG_1_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_1_SHIFT) & MTG_TRA_LINK_LINK_CFG_1_MASK) -#define MTG_TRA_LINK_LINK_CFG_1_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_1_MASK) >> MTG_TRA_LINK_LINK_CFG_1_SHIFT) - -/* - * LINK_CFG_0 (RW) - * - */ -#define MTG_TRA_LINK_LINK_CFG_0_MASK (0x7U) -#define MTG_TRA_LINK_LINK_CFG_0_SHIFT (0U) -#define MTG_TRA_LINK_LINK_CFG_0_SET(x) (((uint32_t)(x) << MTG_TRA_LINK_LINK_CFG_0_SHIFT) & MTG_TRA_LINK_LINK_CFG_0_MASK) -#define MTG_TRA_LINK_LINK_CFG_0_GET(x) (((uint32_t)(x) & MTG_TRA_LINK_LINK_CFG_0_MASK) >> MTG_TRA_LINK_LINK_CFG_0_SHIFT) - -/* Bitfield definition for register of struct array TRA: CONTROL */ -/* - * PASS_IRQ (W1C) - * - */ -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK (0x80000000UL) -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT (31U) -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT) & MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK) -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_PASS_IRQ_MASK) >> MTG_TRA_CMD_CONTROL_PASS_IRQ_SHIFT) - -/* - * PASS_IRQ_EN (RW) - * - */ -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK (0x40000000UL) -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT (30U) -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT) & MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK) -#define MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_MASK) >> MTG_TRA_CMD_CONTROL_PASS_IRQ_EN_SHIFT) - -/* - * MODE (RW) - * - */ -#define MTG_TRA_CMD_CONTROL_MODE_MASK (0x20000000UL) -#define MTG_TRA_CMD_CONTROL_MODE_SHIFT (29U) -#define MTG_TRA_CMD_CONTROL_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_MODE_SHIFT) & MTG_TRA_CMD_CONTROL_MODE_MASK) -#define MTG_TRA_CMD_CONTROL_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_MODE_MASK) >> MTG_TRA_CMD_CONTROL_MODE_SHIFT) - -/* - * OBJECT (RW) - * - */ -#define MTG_TRA_CMD_CONTROL_OBJECT_MASK (0x1FU) -#define MTG_TRA_CMD_CONTROL_OBJECT_SHIFT (0U) -#define MTG_TRA_CMD_CONTROL_OBJECT_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_CONTROL_OBJECT_SHIFT) & MTG_TRA_CMD_CONTROL_OBJECT_MASK) -#define MTG_TRA_CMD_CONTROL_OBJECT_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_CONTROL_OBJECT_MASK) >> MTG_TRA_CMD_CONTROL_OBJECT_SHIFT) - -/* Bitfield definition for register of struct array TRA: REV_PRESET */ -/* - * REV_PRESET (RW) - * - */ -#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT (0U) -#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT) & MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK) -#define MTG_TRA_CMD_REV_PRESET_REV_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_REV_PRESET_REV_PRESET_MASK) >> MTG_TRA_CMD_REV_PRESET_REV_PRESET_SHIFT) - -/* Bitfield definition for register of struct array TRA: POS_PRESET */ -/* - * POS_PRESET (RW) - * - */ -#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT (0U) -#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT) & MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK) -#define MTG_TRA_CMD_POS_PRESET_POS_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_POS_PRESET_POS_PRESET_MASK) >> MTG_TRA_CMD_POS_PRESET_POS_PRESET_SHIFT) - -/* Bitfield definition for register of struct array TRA: VEL_PRESET */ -/* - * VEL_PRESET (RW) - * - */ -#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT (0U) -#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT) & MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK) -#define MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_MASK) >> MTG_TRA_CMD_VEL_PRESET_VEL_PRESET_SHIFT) - -/* Bitfield definition for register of struct array TRA: ACC_PRESET */ -/* - * ACC_PRESET (RW) - * - */ -#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT (0U) -#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT) & MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK) -#define MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_MASK) >> MTG_TRA_CMD_ACC_PRESET_ACC_PRESET_SHIFT) - -/* Bitfield definition for register of struct array TRA: JER_PRESET */ -/* - * JER_PRESET (RW) - * - */ -#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT (0U) -#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_SET(x) (((uint32_t)(x) << MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT) & MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK) -#define MTG_TRA_CMD_JER_PRESET_JER_PRESET_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_JER_PRESET_JER_PRESET_MASK) >> MTG_TRA_CMD_JER_PRESET_JER_PRESET_SHIFT) - -/* Bitfield definition for register of struct array TRA: TIMESTAMP */ -/* - * TIMESTAMP (RO) - * - */ -#define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) -#define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_MASK) >> MTG_TRA_CMD_TIMESTAMP_TIMESTAMP_SHIFT) - -/* Bitfield definition for register of struct array TRA: LOCK_REV */ -/* - * LOCK_REV (RO) - * - */ -#define MTG_TRA_LOCK_REV_LOCK_REV_MASK (0xFFFFFFFFUL) -#define MTG_TRA_LOCK_REV_LOCK_REV_SHIFT (0U) -#define MTG_TRA_LOCK_REV_LOCK_REV_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_REV_LOCK_REV_MASK) >> MTG_TRA_LOCK_REV_LOCK_REV_SHIFT) - -/* Bitfield definition for register of struct array TRA: LOCK_POS */ -/* - * LOCK_POS (RO) - * - */ -#define MTG_TRA_LOCK_POS_LOCK_POS_MASK (0xFFFFFFFFUL) -#define MTG_TRA_LOCK_POS_LOCK_POS_SHIFT (0U) -#define MTG_TRA_LOCK_POS_LOCK_POS_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_POS_LOCK_POS_MASK) >> MTG_TRA_LOCK_POS_LOCK_POS_SHIFT) - -/* Bitfield definition for register of struct array TRA: LOCK_VEL */ -/* - * LOCK_VEL (RO) - * - */ -#define MTG_TRA_LOCK_VEL_LOCK_VEL_MASK (0xFFFFFFFFUL) -#define MTG_TRA_LOCK_VEL_LOCK_VEL_SHIFT (0U) -#define MTG_TRA_LOCK_VEL_LOCK_VEL_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_VEL_LOCK_VEL_MASK) >> MTG_TRA_LOCK_VEL_LOCK_VEL_SHIFT) - -/* Bitfield definition for register of struct array TRA: LOCK_ACC */ -/* - * LOCK_ACC (RO) - * - */ -#define MTG_TRA_LOCK_ACC_LOCK_ACC_MASK (0xFFFFFFFFUL) -#define MTG_TRA_LOCK_ACC_LOCK_ACC_SHIFT (0U) -#define MTG_TRA_LOCK_ACC_LOCK_ACC_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_ACC_LOCK_ACC_MASK) >> MTG_TRA_LOCK_ACC_LOCK_ACC_SHIFT) - -/* Bitfield definition for register of struct array TRA: LOCK_TIME */ -/* - * LOCK_TIME (RO) - * - */ -#define MTG_TRA_LOCK_TIME_LOCK_TIME_MASK (0xFFFFFFFFUL) -#define MTG_TRA_LOCK_TIME_LOCK_TIME_SHIFT (0U) -#define MTG_TRA_LOCK_TIME_LOCK_TIME_GET(x) (((uint32_t)(x) & MTG_TRA_LOCK_TIME_LOCK_TIME_MASK) >> MTG_TRA_LOCK_TIME_LOCK_TIME_SHIFT) - -/* Bitfield definition for register of struct array TRA: STEP_LIMIT_CTRL */ -/* - * POS_ONE_WAY_FORCE_MODE (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK (0x1000U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT (12U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_FORCE_MODE_SHIFT) - -/* - * POS_ONE_WAY_MODE (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK (0x800U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT (11U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_MODE_SHIFT) - -/* - * POS_ONE_WAY_EN (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK (0x400U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT (10U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_ONE_WAY_EN_SHIFT) - -/* - * POS_STEP_MODE (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK (0x200U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT (9U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_MODE_SHIFT) - -/* - * POS_STEP_EN (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK (0x100U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT (8U) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_POS_STEP_EN_SHIFT) - -/* - * VEL_ONE_WAY_MODE (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK (0x4U) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT (2U) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_MODE_SHIFT) - -/* - * VEL_ONE_WAY_EN (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK (0x2U) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT (1U) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_ONE_WAY_EN_SHIFT) - -/* - * VEL_STEP_EN (RW) - * - */ -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK (0x1U) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT (0U) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SET(x) (((uint32_t)(x) << MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT) & MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK) -#define MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_GET(x) (((uint32_t)(x) & MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_MASK) >> MTG_TRA_STEP_LIMIT_CTRL_VEL_STEP_EN_SHIFT) - -/* Bitfield definition for register of struct array TRA: VEL_STEP_MAX */ -/* - * VEL_STEP_MAX (RW) - * - */ -#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK (0xFFFFFFFFUL) -#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT (0U) -#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT) & MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK) -#define MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_MASK) >> MTG_TRA_VEL_STEP_MAX_VEL_STEP_MAX_SHIFT) - -/* Bitfield definition for register of struct array TRA: VEL_STEP_MIN */ -/* - * VEL_STEP_MIN (RW) - * - */ -#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK (0xFFFFFFFFUL) -#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT (0U) -#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT) & MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK) -#define MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_MASK) >> MTG_TRA_VEL_STEP_MIN_VEL_STEP_MIN_SHIFT) - -/* Bitfield definition for register of struct array TRA: POS_STEP_MAX */ -/* - * POS_STEP_MAX (RW) - * - */ -#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK (0xFFFFFFFFUL) -#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT (0U) -#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SET(x) (((uint32_t)(x) << MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT) & MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK) -#define MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_GET(x) (((uint32_t)(x) & MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_MASK) >> MTG_TRA_POS_STEP_MAX_POS_STEP_MAX_SHIFT) - -/* Bitfield definition for register of struct array TRA: POS_STEP_MIN */ -/* - * POS_STEP_MIN (RW) - * - */ -#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK (0xFFFFFFFFUL) -#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT (0U) -#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SET(x) (((uint32_t)(x) << MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT) & MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK) -#define MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_GET(x) (((uint32_t)(x) & MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_MASK) >> MTG_TRA_POS_STEP_MIN_POS_STEP_MIN_SHIFT) - -/* Bitfield definition for register of struct array TRA: VEL_LIMIT_P */ -/* - * VEL_LIMIT_P (RW) - * - */ -#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK (0xFFFFFFFFUL) -#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT (0U) -#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT) & MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK) -#define MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_MASK) >> MTG_TRA_VEL_LIMIT_P_VEL_LIMIT_P_SHIFT) - -/* Bitfield definition for register of struct array TRA: VEL_LIMIT_N */ -/* - * VEL_LIMIT_N (RW) - * - */ -#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK (0xFFFFFFFFUL) -#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT (0U) -#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SET(x) (((uint32_t)(x) << MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT) & MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK) -#define MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_GET(x) (((uint32_t)(x) & MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_MASK) >> MTG_TRA_VEL_LIMIT_N_VEL_LIMIT_N_SHIFT) - -/* Bitfield definition for register of struct array EVENT: CONTROL */ -/* - * ENABLE (RW) - * - */ -#define MTG_EVENT_CONTROL_ENABLE_MASK (0x80000000UL) -#define MTG_EVENT_CONTROL_ENABLE_SHIFT (31U) -#define MTG_EVENT_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_ENABLE_SHIFT) & MTG_EVENT_CONTROL_ENABLE_MASK) -#define MTG_EVENT_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_ENABLE_MASK) >> MTG_EVENT_CONTROL_ENABLE_SHIFT) - -/* - * SOURCE_MUX (RW) - * - */ -#define MTG_EVENT_CONTROL_SOURCE_MUX_MASK (0x78000000UL) -#define MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT (27U) -#define MTG_EVENT_CONTROL_SOURCE_MUX_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT) & MTG_EVENT_CONTROL_SOURCE_MUX_MASK) -#define MTG_EVENT_CONTROL_SOURCE_MUX_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_SOURCE_MUX_MASK) >> MTG_EVENT_CONTROL_SOURCE_MUX_SHIFT) - -/* - * OBJECT (RW) - * - */ -#define MTG_EVENT_CONTROL_OBJECT_MASK (0x7800000UL) -#define MTG_EVENT_CONTROL_OBJECT_SHIFT (23U) -#define MTG_EVENT_CONTROL_OBJECT_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_OBJECT_SHIFT) & MTG_EVENT_CONTROL_OBJECT_MASK) -#define MTG_EVENT_CONTROL_OBJECT_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_OBJECT_MASK) >> MTG_EVENT_CONTROL_OBJECT_SHIFT) - -/* - * MODE (RW) - * - */ -#define MTG_EVENT_CONTROL_MODE_MASK (0x780000UL) -#define MTG_EVENT_CONTROL_MODE_SHIFT (19U) -#define MTG_EVENT_CONTROL_MODE_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_MODE_SHIFT) & MTG_EVENT_CONTROL_MODE_MASK) -#define MTG_EVENT_CONTROL_MODE_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_MODE_MASK) >> MTG_EVENT_CONTROL_MODE_SHIFT) - -/* - * DIR (RW) - * - */ -#define MTG_EVENT_CONTROL_DIR_MASK (0x60000UL) -#define MTG_EVENT_CONTROL_DIR_SHIFT (17U) -#define MTG_EVENT_CONTROL_DIR_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_DIR_SHIFT) & MTG_EVENT_CONTROL_DIR_MASK) -#define MTG_EVENT_CONTROL_DIR_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_DIR_MASK) >> MTG_EVENT_CONTROL_DIR_SHIFT) - -/* - * DIR_MODE (RW) - * - */ -#define MTG_EVENT_CONTROL_DIR_MODE_MASK (0x10000UL) -#define MTG_EVENT_CONTROL_DIR_MODE_SHIFT (16U) -#define MTG_EVENT_CONTROL_DIR_MODE_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_DIR_MODE_SHIFT) & MTG_EVENT_CONTROL_DIR_MODE_MASK) -#define MTG_EVENT_CONTROL_DIR_MODE_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_DIR_MODE_MASK) >> MTG_EVENT_CONTROL_DIR_MODE_SHIFT) - -/* - * OVER_MODE_CMP (RW) - * - */ -#define MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK (0x8000U) -#define MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT (15U) -#define MTG_EVENT_CONTROL_OVER_MODE_CMP_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT) & MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK) -#define MTG_EVENT_CONTROL_OVER_MODE_CMP_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_OVER_MODE_CMP_MASK) >> MTG_EVENT_CONTROL_OVER_MODE_CMP_SHIFT) - -/* - * TRIG_NUM (RW) - * - */ -#define MTG_EVENT_CONTROL_TRIG_NUM_MASK (0x4000U) -#define MTG_EVENT_CONTROL_TRIG_NUM_SHIFT (14U) -#define MTG_EVENT_CONTROL_TRIG_NUM_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_TRIG_NUM_SHIFT) & MTG_EVENT_CONTROL_TRIG_NUM_MASK) -#define MTG_EVENT_CONTROL_TRIG_NUM_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_TRIG_NUM_MASK) >> MTG_EVENT_CONTROL_TRIG_NUM_SHIFT) - -/* - * EVENT_OVER_IRQ_EN (RW) - * - */ -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK (0x8U) -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT (3U) -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK) -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_MASK) >> MTG_EVENT_CONTROL_EVENT_OVER_IRQ_EN_SHIFT) - -/* - * EVENT_IRQ_EN (RW) - * - */ -#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK (0x4U) -#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT (2U) -#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT) & MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK) -#define MTG_EVENT_CONTROL_EVENT_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_IRQ_EN_MASK) >> MTG_EVENT_CONTROL_EVENT_IRQ_EN_SHIFT) - -/* - * EVENT_OVER_IRQ (W1C) - * - */ -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK (0x2U) -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT (1U) -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK) -#define MTG_EVENT_CONTROL_EVENT_OVER_IRQ_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_OVER_IRQ_MASK) >> MTG_EVENT_CONTROL_EVENT_OVER_IRQ_SHIFT) - -/* - * EVENT_IRQ (W1C) - * - */ -#define MTG_EVENT_CONTROL_EVENT_IRQ_MASK (0x1U) -#define MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT (0U) -#define MTG_EVENT_CONTROL_EVENT_IRQ_SET(x) (((uint32_t)(x) << MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT) & MTG_EVENT_CONTROL_EVENT_IRQ_MASK) -#define MTG_EVENT_CONTROL_EVENT_IRQ_GET(x) (((uint32_t)(x) & MTG_EVENT_CONTROL_EVENT_IRQ_MASK) >> MTG_EVENT_CONTROL_EVENT_IRQ_SHIFT) - -/* Bitfield definition for register of struct array EVENT: PRESET_0 */ -/* - * PRESET (RW) - * - */ -#define MTG_EVENT_PRESET_0_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_EVENT_PRESET_0_PRESET_SHIFT (0U) -#define MTG_EVENT_PRESET_0_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_0_PRESET_SHIFT) & MTG_EVENT_PRESET_0_PRESET_MASK) -#define MTG_EVENT_PRESET_0_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_0_PRESET_MASK) >> MTG_EVENT_PRESET_0_PRESET_SHIFT) - -/* Bitfield definition for register of struct array EVENT: PRESET_1 */ -/* - * PRESET (RW) - * - */ -#define MTG_EVENT_PRESET_1_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_EVENT_PRESET_1_PRESET_SHIFT (0U) -#define MTG_EVENT_PRESET_1_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_1_PRESET_SHIFT) & MTG_EVENT_PRESET_1_PRESET_MASK) -#define MTG_EVENT_PRESET_1_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_1_PRESET_MASK) >> MTG_EVENT_PRESET_1_PRESET_SHIFT) - -/* Bitfield definition for register of struct array EVENT: PRESET_2 */ -/* - * PRESET (RW) - * - */ -#define MTG_EVENT_PRESET_2_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_EVENT_PRESET_2_PRESET_SHIFT (0U) -#define MTG_EVENT_PRESET_2_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_2_PRESET_SHIFT) & MTG_EVENT_PRESET_2_PRESET_MASK) -#define MTG_EVENT_PRESET_2_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_2_PRESET_MASK) >> MTG_EVENT_PRESET_2_PRESET_SHIFT) - -/* Bitfield definition for register of struct array EVENT: PRESET_3 */ -/* - * PRESET (RW) - * - */ -#define MTG_EVENT_PRESET_3_PRESET_MASK (0xFFFFFFFFUL) -#define MTG_EVENT_PRESET_3_PRESET_SHIFT (0U) -#define MTG_EVENT_PRESET_3_PRESET_SET(x) (((uint32_t)(x) << MTG_EVENT_PRESET_3_PRESET_SHIFT) & MTG_EVENT_PRESET_3_PRESET_MASK) -#define MTG_EVENT_PRESET_3_PRESET_GET(x) (((uint32_t)(x) & MTG_EVENT_PRESET_3_PRESET_MASK) >> MTG_EVENT_PRESET_3_PRESET_SHIFT) - -/* Bitfield definition for register of struct array EVENT: TIMESTAMP */ -/* - * TIMESTAMP (RO) - * - */ -#define MTG_EVENT_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) -#define MTG_EVENT_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define MTG_EVENT_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & MTG_EVENT_TIMESTAMP_TIMESTAMP_MASK) >> MTG_EVENT_TIMESTAMP_TIMESTAMP_SHIFT) - -/* Bitfield definition for register: SW_EVENT */ -/* - * SW_EVENT_TRIG (RW) - * - */ -#define MTG_SW_EVENT_SW_EVENT_TRIG_MASK (0x1U) -#define MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT (0U) -#define MTG_SW_EVENT_SW_EVENT_TRIG_SET(x) (((uint32_t)(x) << MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT) & MTG_SW_EVENT_SW_EVENT_TRIG_MASK) -#define MTG_SW_EVENT_SW_EVENT_TRIG_GET(x) (((uint32_t)(x) & MTG_SW_EVENT_SW_EVENT_TRIG_MASK) >> MTG_SW_EVENT_SW_EVENT_TRIG_SHIFT) - -/* Bitfield definition for register: SW_GLB_RESET */ -/* - * SW_GLB_RESET (WO) - * - */ -#define MTG_SW_GLB_RESET_SW_GLB_RESET_MASK (0x1U) -#define MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT (0U) -#define MTG_SW_GLB_RESET_SW_GLB_RESET_SET(x) (((uint32_t)(x) << MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT) & MTG_SW_GLB_RESET_SW_GLB_RESET_MASK) -#define MTG_SW_GLB_RESET_SW_GLB_RESET_GET(x) (((uint32_t)(x) & MTG_SW_GLB_RESET_SW_GLB_RESET_MASK) >> MTG_SW_GLB_RESET_SW_GLB_RESET_SHIFT) - -/* Bitfield definition for register: FILTER_CONTROL */ -/* - * MUL_ERR_IRQ_0 (W1C) - * - */ -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK (0x80000000UL) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT (31U) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_0_SHIFT) - -/* - * MUL_ERR_IRQ_1 (W1C) - * - */ -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK (0x40000000UL) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT (30U) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_1_SHIFT) - -/* - * MUL_ERR_IRQ_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK (0x20000000UL) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT (29U) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK) -#define MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_MASK) >> MTG_FILTER_CONTROL_MUL_ERR_IRQ_EN_SHIFT) - -/* - * ERR_BYPASS_STATUS (RO) - * - */ -#define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_MASK (0x800000UL) -#define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_SHIFT (23U) -#define MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_STATUS_SHIFT) - -/* - * ERR_BYPASS_F_I_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK (0x400000UL) -#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT (22U) -#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK) -#define MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_F_I_EN_SHIFT) - -/* - * ERR_BYPASS_I_F_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK (0x200000UL) -#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT (21U) -#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK) -#define MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_I_F_EN_SHIFT) - -/* - * SW_LOCK (RW) - * - */ -#define MTG_FILTER_CONTROL_SW_LOCK_MASK (0x100000UL) -#define MTG_FILTER_CONTROL_SW_LOCK_SHIFT (20U) -#define MTG_FILTER_CONTROL_SW_LOCK_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_SW_LOCK_SHIFT) & MTG_FILTER_CONTROL_SW_LOCK_MASK) -#define MTG_FILTER_CONTROL_SW_LOCK_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_SW_LOCK_MASK) >> MTG_FILTER_CONTROL_SW_LOCK_SHIFT) - -/* - * TIMEOUT_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_TIMEOUT_EN_MASK (0x80000UL) -#define MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT (19U) -#define MTG_FILTER_CONTROL_TIMEOUT_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT) & MTG_FILTER_CONTROL_TIMEOUT_EN_MASK) -#define MTG_FILTER_CONTROL_TIMEOUT_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_TIMEOUT_EN_MASK) >> MTG_FILTER_CONTROL_TIMEOUT_EN_SHIFT) - -/* - * REV_INI_MODE (RW) - * - */ -#define MTG_FILTER_CONTROL_REV_INI_MODE_MASK (0x20000UL) -#define MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT (17U) -#define MTG_FILTER_CONTROL_REV_INI_MODE_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT) & MTG_FILTER_CONTROL_REV_INI_MODE_MASK) -#define MTG_FILTER_CONTROL_REV_INI_MODE_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_REV_INI_MODE_MASK) >> MTG_FILTER_CONTROL_REV_INI_MODE_SHIFT) - -/* - * SEL_TIME1 (RW) - * - */ -#define MTG_FILTER_CONTROL_SEL_TIME1_MASK (0x3000U) -#define MTG_FILTER_CONTROL_SEL_TIME1_SHIFT (12U) -#define MTG_FILTER_CONTROL_SEL_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_SEL_TIME1_SHIFT) & MTG_FILTER_CONTROL_SEL_TIME1_MASK) -#define MTG_FILTER_CONTROL_SEL_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_SEL_TIME1_MASK) >> MTG_FILTER_CONTROL_SEL_TIME1_SHIFT) - -/* - * SEL_TIME0 (RW) - * - */ -#define MTG_FILTER_CONTROL_SEL_TIME0_MASK (0xC00U) -#define MTG_FILTER_CONTROL_SEL_TIME0_SHIFT (10U) -#define MTG_FILTER_CONTROL_SEL_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_SEL_TIME0_SHIFT) & MTG_FILTER_CONTROL_SEL_TIME0_MASK) -#define MTG_FILTER_CONTROL_SEL_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_SEL_TIME0_MASK) >> MTG_FILTER_CONTROL_SEL_TIME0_SHIFT) - -/* - * EN_TIME1 (RW) - * - */ -#define MTG_FILTER_CONTROL_EN_TIME1_MASK (0x200U) -#define MTG_FILTER_CONTROL_EN_TIME1_SHIFT (9U) -#define MTG_FILTER_CONTROL_EN_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_EN_TIME1_SHIFT) & MTG_FILTER_CONTROL_EN_TIME1_MASK) -#define MTG_FILTER_CONTROL_EN_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_EN_TIME1_MASK) >> MTG_FILTER_CONTROL_EN_TIME1_SHIFT) - -/* - * EN_TIME0 (RW) - * - */ -#define MTG_FILTER_CONTROL_EN_TIME0_MASK (0x100U) -#define MTG_FILTER_CONTROL_EN_TIME0_SHIFT (8U) -#define MTG_FILTER_CONTROL_EN_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_EN_TIME0_SHIFT) & MTG_FILTER_CONTROL_EN_TIME0_MASK) -#define MTG_FILTER_CONTROL_EN_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_EN_TIME0_MASK) >> MTG_FILTER_CONTROL_EN_TIME0_SHIFT) - -/* - * A_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_A_EN_MASK (0x40U) -#define MTG_FILTER_CONTROL_A_EN_SHIFT (6U) -#define MTG_FILTER_CONTROL_A_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_A_EN_SHIFT) & MTG_FILTER_CONTROL_A_EN_MASK) -#define MTG_FILTER_CONTROL_A_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_A_EN_MASK) >> MTG_FILTER_CONTROL_A_EN_SHIFT) - -/* - * ERR_INI (RW) - * - */ -#define MTG_FILTER_CONTROL_ERR_INI_MASK (0x20U) -#define MTG_FILTER_CONTROL_ERR_INI_SHIFT (5U) -#define MTG_FILTER_CONTROL_ERR_INI_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_INI_SHIFT) & MTG_FILTER_CONTROL_ERR_INI_MASK) -#define MTG_FILTER_CONTROL_ERR_INI_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_INI_MASK) >> MTG_FILTER_CONTROL_ERR_INI_SHIFT) - -/* - * ERR_BYPASS_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK (0x10U) -#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT (4U) -#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT) & MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK) -#define MTG_FILTER_CONTROL_ERR_BYPASS_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ERR_BYPASS_EN_MASK) >> MTG_FILTER_CONTROL_ERR_BYPASS_EN_SHIFT) - -/* - * FF_MODE (RW) - * - */ -#define MTG_FILTER_CONTROL_FF_MODE_MASK (0x8U) -#define MTG_FILTER_CONTROL_FF_MODE_SHIFT (3U) -#define MTG_FILTER_CONTROL_FF_MODE_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_FF_MODE_SHIFT) & MTG_FILTER_CONTROL_FF_MODE_MASK) -#define MTG_FILTER_CONTROL_FF_MODE_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_FF_MODE_MASK) >> MTG_FILTER_CONTROL_FF_MODE_SHIFT) - -/* - * FF_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_FF_EN_MASK (0x4U) -#define MTG_FILTER_CONTROL_FF_EN_SHIFT (2U) -#define MTG_FILTER_CONTROL_FF_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_FF_EN_SHIFT) & MTG_FILTER_CONTROL_FF_EN_MASK) -#define MTG_FILTER_CONTROL_FF_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_FF_EN_MASK) >> MTG_FILTER_CONTROL_FF_EN_SHIFT) - -/* - * INIT_EN (RW) - * - */ -#define MTG_FILTER_CONTROL_INIT_EN_MASK (0x2U) -#define MTG_FILTER_CONTROL_INIT_EN_SHIFT (1U) -#define MTG_FILTER_CONTROL_INIT_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_INIT_EN_SHIFT) & MTG_FILTER_CONTROL_INIT_EN_MASK) -#define MTG_FILTER_CONTROL_INIT_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_INIT_EN_MASK) >> MTG_FILTER_CONTROL_INIT_EN_SHIFT) - -/* - * ENABLE (RW) - * - */ -#define MTG_FILTER_CONTROL_ENABLE_MASK (0x1U) -#define MTG_FILTER_CONTROL_ENABLE_SHIFT (0U) -#define MTG_FILTER_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << MTG_FILTER_CONTROL_ENABLE_SHIFT) & MTG_FILTER_CONTROL_ENABLE_MASK) -#define MTG_FILTER_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & MTG_FILTER_CONTROL_ENABLE_MASK) >> MTG_FILTER_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register: FILTER_REV_VALUE */ -/* - * VALUE (RW) - * - */ -#define MTG_FILTER_REV_VALUE_VALUE_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_REV_VALUE_VALUE_SHIFT (0U) -#define MTG_FILTER_REV_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_REV_VALUE_VALUE_SHIFT) & MTG_FILTER_REV_VALUE_VALUE_MASK) -#define MTG_FILTER_REV_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_REV_VALUE_VALUE_MASK) >> MTG_FILTER_REV_VALUE_VALUE_SHIFT) - -/* Bitfield definition for register: FILTER_POS_VALUE */ -/* - * VALUE (RW) - * - */ -#define MTG_FILTER_POS_VALUE_VALUE_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_POS_VALUE_VALUE_SHIFT (0U) -#define MTG_FILTER_POS_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_POS_VALUE_VALUE_SHIFT) & MTG_FILTER_POS_VALUE_VALUE_MASK) -#define MTG_FILTER_POS_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_POS_VALUE_VALUE_MASK) >> MTG_FILTER_POS_VALUE_VALUE_SHIFT) - -/* Bitfield definition for register: FILTER_VEL_VALUE */ -/* - * VALUE (RW) - * - */ -#define MTG_FILTER_VEL_VALUE_VALUE_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_VEL_VALUE_VALUE_SHIFT (0U) -#define MTG_FILTER_VEL_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_VEL_VALUE_VALUE_SHIFT) & MTG_FILTER_VEL_VALUE_VALUE_MASK) -#define MTG_FILTER_VEL_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_VEL_VALUE_VALUE_MASK) >> MTG_FILTER_VEL_VALUE_VALUE_SHIFT) - -/* Bitfield definition for register: FILTER_ACC_VALUE */ -/* - * VALUE (RW) - * - */ -#define MTG_FILTER_ACC_VALUE_VALUE_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_ACC_VALUE_VALUE_SHIFT (0U) -#define MTG_FILTER_ACC_VALUE_VALUE_SET(x) (((uint32_t)(x) << MTG_FILTER_ACC_VALUE_VALUE_SHIFT) & MTG_FILTER_ACC_VALUE_VALUE_MASK) -#define MTG_FILTER_ACC_VALUE_VALUE_GET(x) (((uint32_t)(x) & MTG_FILTER_ACC_VALUE_VALUE_MASK) >> MTG_FILTER_ACC_VALUE_VALUE_SHIFT) - -/* Bitfield definition for register: FILTER_MOT_SEL */ -/* - * OUTPUT_VEL_SEL (RW) - * - */ -#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK (0x3F000000UL) -#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT (24U) -#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT) & MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK) -#define MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_MASK) >> MTG_FILTER_MOT_SEL_OUTPUT_VEL_SEL_SHIFT) - -/* - * OUTPUT_ACC_SEL (RW) - * - */ -#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK (0x3F0000UL) -#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT (16U) -#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT) & MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK) -#define MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_MASK) >> MTG_FILTER_MOT_SEL_OUTPUT_ACC_SEL_SHIFT) - -/* - * FILTER_VEL_SEL (RW) - * - */ -#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK (0x3F00U) -#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT (8U) -#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT) & MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK) -#define MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_MASK) >> MTG_FILTER_MOT_SEL_FILTER_VEL_SEL_SHIFT) - -/* - * FILTER_ACC_SEL (RW) - * - */ -#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK (0x3FU) -#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT (0U) -#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT) & MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK) -#define MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_MASK) >> MTG_FILTER_MOT_SEL_FILTER_ACC_SEL_SHIFT) - -/* Bitfield definition for register: FILTER_STAGE_SEL */ -/* - * STAGE5_SEL (RW) - * - */ -#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK (0x3E000000UL) -#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT (25U) -#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK) -#define MTG_FILTER_STAGE_SEL_STAGE5_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE5_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE5_SEL_SHIFT) - -/* - * STAGE4_SEL (RW) - * - */ -#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK (0x1F00000UL) -#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT (20U) -#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK) -#define MTG_FILTER_STAGE_SEL_STAGE4_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE4_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE4_SEL_SHIFT) - -/* - * STAGE3_SEL (RW) - * - */ -#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK (0xF8000UL) -#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT (15U) -#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK) -#define MTG_FILTER_STAGE_SEL_STAGE3_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE3_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE3_SEL_SHIFT) - -/* - * STAGE2_SEL (RW) - * - */ -#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK (0x7C00U) -#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT (10U) -#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK) -#define MTG_FILTER_STAGE_SEL_STAGE2_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE2_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE2_SEL_SHIFT) - -/* - * STAGE1_SEL (RW) - * - */ -#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK (0x3E0U) -#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT (5U) -#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK) -#define MTG_FILTER_STAGE_SEL_STAGE1_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE1_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE1_SEL_SHIFT) - -/* - * STAGE0_SEL (RW) - * - */ -#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK (0x1FU) -#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT (0U) -#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT) & MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK) -#define MTG_FILTER_STAGE_SEL_STAGE0_SEL_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SEL_STAGE0_SEL_MASK) >> MTG_FILTER_STAGE_SEL_STAGE0_SEL_SHIFT) - -/* Bitfield definition for register: FILTER_TIME_CONSTANT_TP */ -/* - * TP (RW) - * - */ -#define MTG_FILTER_TIME_CONSTANT_TP_TP_MASK (0xFFFFFFUL) -#define MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT (0U) -#define MTG_FILTER_TIME_CONSTANT_TP_TP_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT) & MTG_FILTER_TIME_CONSTANT_TP_TP_MASK) -#define MTG_FILTER_TIME_CONSTANT_TP_TP_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TP_TP_MASK) >> MTG_FILTER_TIME_CONSTANT_TP_TP_SHIFT) - -/* Bitfield definition for register: FILTER_TIME_CONSTANT_TZ */ -/* - * TZ (RW) - * - */ -#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK (0xFFFFFFUL) -#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT (0U) -#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT) & MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK) -#define MTG_FILTER_TIME_CONSTANT_TZ_TZ_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TZ_TZ_MASK) >> MTG_FILTER_TIME_CONSTANT_TZ_TZ_SHIFT) - -/* Bitfield definition for register: FILTER_TIME_CONSTANT_TZ_1 */ -/* - * TZ_1 (RW) - * - */ -#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK (0xFFFFFFUL) -#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT (0U) -#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT) & MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK) -#define MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_MASK) >> MTG_FILTER_TIME_CONSTANT_TZ_1_TZ_1_SHIFT) - -/* Bitfield definition for register: FILTER_ZERO_TZ_SEL */ -/* - * STAGE5 (RW) - * - */ -#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK (0x20U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT (5U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE5_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE5_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE5_SHIFT) - -/* - * STAGE4 (RW) - * - */ -#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK (0x10U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT (4U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE4_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE4_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE4_SHIFT) - -/* - * STAGE3 (RW) - * - */ -#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK (0x8U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT (3U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE3_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE3_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE3_SHIFT) - -/* - * STAGE2 (RW) - * - */ -#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK (0x4U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT (2U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE2_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE2_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE2_SHIFT) - -/* - * STAGE1 (RW) - * - */ -#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK (0x2U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT (1U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE1_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE1_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE1_SHIFT) - -/* - * STAGE0 (RW) - * - */ -#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK (0x1U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT (0U) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_SET(x) (((uint32_t)(x) << MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT) & MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK) -#define MTG_FILTER_ZERO_TZ_SEL_STAGE0_GET(x) (((uint32_t)(x) & MTG_FILTER_ZERO_TZ_SEL_STAGE0_MASK) >> MTG_FILTER_ZERO_TZ_SEL_STAGE0_SHIFT) - -/* Bitfield definition for register: FILTER_GAIN */ -/* - * GAIN_T0_EN (RW) - * - */ -#define MTG_FILTER_GAIN_GAIN_T0_EN_MASK (0x80000000UL) -#define MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT (31U) -#define MTG_FILTER_GAIN_GAIN_T0_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT) & MTG_FILTER_GAIN_GAIN_T0_EN_MASK) -#define MTG_FILTER_GAIN_GAIN_T0_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_GAIN_GAIN_T0_EN_MASK) >> MTG_FILTER_GAIN_GAIN_T0_EN_SHIFT) - -/* - * GAIN_T1_EN (RW) - * - */ -#define MTG_FILTER_GAIN_GAIN_T1_EN_MASK (0x40000000UL) -#define MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT (30U) -#define MTG_FILTER_GAIN_GAIN_T1_EN_SET(x) (((uint32_t)(x) << MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT) & MTG_FILTER_GAIN_GAIN_T1_EN_MASK) -#define MTG_FILTER_GAIN_GAIN_T1_EN_GET(x) (((uint32_t)(x) & MTG_FILTER_GAIN_GAIN_T1_EN_MASK) >> MTG_FILTER_GAIN_GAIN_T1_EN_SHIFT) - -/* - * K (RW) - * - */ -#define MTG_FILTER_GAIN_K_MASK (0xFFFFFFUL) -#define MTG_FILTER_GAIN_K_SHIFT (0U) -#define MTG_FILTER_GAIN_K_SET(x) (((uint32_t)(x) << MTG_FILTER_GAIN_K_SHIFT) & MTG_FILTER_GAIN_K_MASK) -#define MTG_FILTER_GAIN_K_GET(x) (((uint32_t)(x) & MTG_FILTER_GAIN_K_MASK) >> MTG_FILTER_GAIN_K_SHIFT) - -/* Bitfield definition for register: FILTER_STAGE_SHIFT0 */ -/* - * STAGE3_SHIFT1 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK (0xF0000000UL) -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT (28U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT1_SHIFT) - -/* - * STAGE3_SHIFT0 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK (0xF000000UL) -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT (24U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE3_SHIFT0_SHIFT) - -/* - * STAGE2_SHIFT1 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK (0xF00000UL) -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT (20U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT1_SHIFT) - -/* - * STAGE2_SHIFT0 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK (0xF0000UL) -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT (16U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE2_SHIFT0_SHIFT) - -/* - * STAGE1_SHIFT1 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK (0xF000U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT (12U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT1_SHIFT) - -/* - * STAGE1_SHIFT0 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK (0xF00U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT (8U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE1_SHIFT0_SHIFT) - -/* - * STAGE0_SHIFT1 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK (0xF0U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT (4U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT1_SHIFT) - -/* - * STAGE0_SHIFT0 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK (0xFU) -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT (0U) -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK) -#define MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT0_STAGE0_SHIFT0_SHIFT) - -/* Bitfield definition for register: FILTER_STAGE_SHIFT1 */ -/* - * STAGE5_SHIFT1 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK (0xF000U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT (12U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK) -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT1_SHIFT) - -/* - * STAGE5_SHIFT0 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK (0xF00U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT (8U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK) -#define MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE5_SHIFT0_SHIFT) - -/* - * STAGE4_SHIFT1 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK (0xF0U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT (4U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK) -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT1_SHIFT) - -/* - * STAGE4_SHIFT0 (RW) - * - */ -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK (0xFU) -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT (0U) -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SET(x) (((uint32_t)(x) << MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK) -#define MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_GET(x) (((uint32_t)(x) & MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_MASK) >> MTG_FILTER_STAGE_SHIFT1_STAGE4_SHIFT0_SHIFT) - -/* Bitfield definition for register: FILTER_PARAM_SHIFT */ -/* - * ACC_SHIFT_PARAM (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK (0xF0000000UL) -#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT (28U) -#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT) & MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK) -#define MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_MASK) >> MTG_FILTER_PARAM_SHIFT_ACC_SHIFT_PARAM_SHIFT) - -/* - * VEL_SHIFT_PARAM (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK (0xF000000UL) -#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT (24U) -#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT) & MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK) -#define MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_MASK) >> MTG_FILTER_PARAM_SHIFT_VEL_SHIFT_PARAM_SHIFT) - -/* - * GAIN_K_SHIFT (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK (0xF00000UL) -#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT (20U) -#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK) -#define MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_K_SHIFT_SHIFT) - -/* - * GAIN_T0_SHIFT (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK (0xF0000UL) -#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT (16U) -#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK) -#define MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_T0_SHIFT_SHIFT) - -/* - * GAIN_T1_SHIFT (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK (0xF000U) -#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT (12U) -#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK) -#define MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_GAIN_T1_SHIFT_SHIFT) - -/* - * TP_SHIFT (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK (0xF00U) -#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT (8U) -#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK) -#define MTG_FILTER_PARAM_SHIFT_TP_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TP_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TP_SHIFT_SHIFT) - -/* - * TZ_1_SHIFT (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK (0xF0U) -#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT (4U) -#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK) -#define MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TZ_1_SHIFT_SHIFT) - -/* - * TZ_SHIFT (RW) - * - */ -#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK (0xFU) -#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT (0U) -#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT) & MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK) -#define MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_MASK) >> MTG_FILTER_PARAM_SHIFT_TZ_SHIFT_SHIFT) - -/* Bitfield definition for register: FILTER_TIME_SHIFT */ -/* - * ACC_SHIFT_TIME1 (RW) - * - */ -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK (0xF000U) -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT (12U) -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK) -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_MASK) >> MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME1_SHIFT) - -/* - * VEL_SHIFT_TIME1 (RW) - * - */ -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK (0xF00U) -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT (8U) -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK) -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_MASK) >> MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME1_SHIFT) - -/* - * ACC_SHIFT_TIME0 (RW) - * - */ -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK (0xF0U) -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT (4U) -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK) -#define MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_MASK) >> MTG_FILTER_TIME_SHIFT_ACC_SHIFT_TIME0_SHIFT) - -/* - * VEL_SHIFT_TIME0 (RW) - * - */ -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK (0xFU) -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT (0U) -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK) -#define MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_MASK) >> MTG_FILTER_TIME_SHIFT_VEL_SHIFT_TIME0_SHIFT) - -/* Bitfield definition for register: FILTER_FF_SHIFT */ -/* - * OUTPUT_ACC_SHIFT (RW) - * - */ -#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK (0xF000U) -#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT (12U) -#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK) -#define MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_OUTPUT_ACC_SHIFT_SHIFT) - -/* - * FILTER_ACC_SHIFT (RW) - * - */ -#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK (0xF00U) -#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT (8U) -#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK) -#define MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_FILTER_ACC_SHIFT_SHIFT) - -/* - * OUTPUT_VEL_SHIFT (RW) - * - */ -#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK (0xF0U) -#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT (4U) -#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK) -#define MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_OUTPUT_VEL_SHIFT_SHIFT) - -/* - * FILTER_VEL_SHIFT (RW) - * - */ -#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK (0xFU) -#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT (0U) -#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SET(x) (((uint32_t)(x) << MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT) & MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK) -#define MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_GET(x) (((uint32_t)(x) & MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_MASK) >> MTG_FILTER_FF_SHIFT_FILTER_VEL_SHIFT_SHIFT) - -/* Bitfield definition for register: FILTER_TIME1_SW_ADJUST */ -/* - * TIME (RW) - * - */ -#define MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT (0U) -#define MTG_FILTER_TIME1_SW_ADJUST_TIME_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT) & MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK) -#define MTG_FILTER_TIME1_SW_ADJUST_TIME_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME1_SW_ADJUST_TIME_MASK) >> MTG_FILTER_TIME1_SW_ADJUST_TIME_SHIFT) - -/* Bitfield definition for register: FILTER_TIME0_SW_ADJUST */ -/* - * TIME (RW) - * - */ -#define MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT (0U) -#define MTG_FILTER_TIME0_SW_ADJUST_TIME_SET(x) (((uint32_t)(x) << MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT) & MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK) -#define MTG_FILTER_TIME0_SW_ADJUST_TIME_GET(x) (((uint32_t)(x) & MTG_FILTER_TIME0_SW_ADJUST_TIME_MASK) >> MTG_FILTER_TIME0_SW_ADJUST_TIME_SHIFT) - -/* Bitfield definition for register: FILTER_ERROR_LIMIT_L */ -/* - * ERROR_LIMIT_L (RW) - * - */ -#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT (0U) -#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SET(x) (((uint32_t)(x) << MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT) & MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK) -#define MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_GET(x) (((uint32_t)(x) & MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_MASK) >> MTG_FILTER_ERROR_LIMIT_L_ERROR_LIMIT_L_SHIFT) - -/* Bitfield definition for register: FILTER_ERROR_LIMIT_H */ -/* - * ERROR_LIMIT_H (RW) - * - */ -#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT (0U) -#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SET(x) (((uint32_t)(x) << MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT) & MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK) -#define MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_GET(x) (((uint32_t)(x) & MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_MASK) >> MTG_FILTER_ERROR_LIMIT_H_ERROR_LIMIT_H_SHIFT) - -/* Bitfield definition for register: FILTER_TIMEOUT_CNT */ -/* - * TIMEOUT_CNT (RW) - * - */ -#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT (0U) -#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SET(x) (((uint32_t)(x) << MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT) & MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK) -#define MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_GET(x) (((uint32_t)(x) & MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_MASK) >> MTG_FILTER_TIMEOUT_CNT_TIMEOUT_CNT_SHIFT) - -/* Bitfield definition for register: FILTER_REV_LOCK */ -/* - * REV_STATUS (RO) - * - */ -#define MTG_FILTER_REV_LOCK_REV_STATUS_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_REV_LOCK_REV_STATUS_SHIFT (0U) -#define MTG_FILTER_REV_LOCK_REV_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_REV_LOCK_REV_STATUS_MASK) >> MTG_FILTER_REV_LOCK_REV_STATUS_SHIFT) - -/* Bitfield definition for register: FILTER_POS_LOCK */ -/* - * POS_STATUS (RO) - * - */ -#define MTG_FILTER_POS_LOCK_POS_STATUS_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_POS_LOCK_POS_STATUS_SHIFT (0U) -#define MTG_FILTER_POS_LOCK_POS_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_POS_LOCK_POS_STATUS_MASK) >> MTG_FILTER_POS_LOCK_POS_STATUS_SHIFT) - -/* Bitfield definition for register: FILTER_VEL_LOCK */ -/* - * VEL_STATUS (RO) - * - */ -#define MTG_FILTER_VEL_LOCK_VEL_STATUS_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_VEL_LOCK_VEL_STATUS_SHIFT (0U) -#define MTG_FILTER_VEL_LOCK_VEL_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_VEL_LOCK_VEL_STATUS_MASK) >> MTG_FILTER_VEL_LOCK_VEL_STATUS_SHIFT) - -/* Bitfield definition for register: FILTER_ACC_LOCK */ -/* - * ACC_STATUS (RO) - * - */ -#define MTG_FILTER_ACC_LOCK_ACC_STATUS_MASK (0xFFFFFFFFUL) -#define MTG_FILTER_ACC_LOCK_ACC_STATUS_SHIFT (0U) -#define MTG_FILTER_ACC_LOCK_ACC_STATUS_GET(x) (((uint32_t)(x) & MTG_FILTER_ACC_LOCK_ACC_STATUS_MASK) >> MTG_FILTER_ACC_LOCK_ACC_STATUS_SHIFT) - - - -/* CMD register group index macro definition */ -#define MTG_CMD_0 (0UL) -#define MTG_CMD_1 (1UL) -#define MTG_CMD_2 (2UL) -#define MTG_CMD_3 (3UL) - -/* TRA register group index macro definition */ -#define MTG_TRA_0 (0UL) -#define MTG_TRA_1 (1UL) - -/* EVENT register group index macro definition */ -#define MTG_EVENT_0 (0UL) -#define MTG_EVENT_1 (1UL) -#define MTG_EVENT_2 (2UL) -#define MTG_EVENT_3 (3UL) - - -#endif /* HPM_MTG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_otp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_otp_regs.h deleted file mode 100644 index feb5f9c2efe..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_otp_regs.h +++ /dev/null @@ -1,560 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_OTP_H -#define HPM_OTP_H - -typedef struct { - __RW uint32_t SHADOW[128]; /* 0x0 - 0x1FC: Fuse shadow registers */ - __RW uint32_t SHADOW_LOCK[8]; /* 0x200 - 0x21C: Fuse shadow lock */ - __R uint8_t RESERVED0[480]; /* 0x220 - 0x3FF: Reserved */ - __RW uint32_t FUSE[128]; /* 0x400 - 0x5FC: Fuse Array */ - __RW uint32_t FUSE_LOCK[8]; /* 0x600 - 0x61C: Fuse lock */ - __R uint8_t RESERVED1[480]; /* 0x620 - 0x7FF: Reserved */ - __RW uint32_t UNLOCK; /* 0x800: UNLOCK */ - __RW uint32_t DATA; /* 0x804: DATA */ - __RW uint32_t ADDR; /* 0x808: ADDR */ - __RW uint32_t CMD; /* 0x80C: CMD */ - __R uint8_t RESERVED2[496]; /* 0x810 - 0x9FF: Reserved */ - __RW uint32_t LOAD_REQ; /* 0xA00: LOAD Request */ - __RW uint32_t LOAD_COMP; /* 0xA04: LOAD complete */ - __R uint8_t RESERVED3[24]; /* 0xA08 - 0xA1F: Reserved */ - __RW uint32_t REGION[4]; /* 0xA20 - 0xA2C: LOAD region */ - __R uint8_t RESERVED4[464]; /* 0xA30 - 0xBFF: Reserved */ - __RW uint32_t INT_FLAG; /* 0xC00: interrupt flag */ - __RW uint32_t INT_EN; /* 0xC04: interrupt enable */ -} OTP_Type; - - -/* Bitfield definition for register array: SHADOW */ -/* - * SHADOW (RW) - * - * shadow register of fuse for pmic area - * for PMIC, index valid for 0-15, for SOC index valid for 16-128 - */ -#define OTP_SHADOW_SHADOW_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_SHADOW_SHIFT (0U) -#define OTP_SHADOW_SHADOW_SET(x) (((uint32_t)(x) << OTP_SHADOW_SHADOW_SHIFT) & OTP_SHADOW_SHADOW_MASK) -#define OTP_SHADOW_SHADOW_GET(x) (((uint32_t)(x) & OTP_SHADOW_SHADOW_MASK) >> OTP_SHADOW_SHADOW_SHIFT) - -/* Bitfield definition for register array: SHADOW_LOCK */ -/* - * LOCK (RW) - * - * lock for pmic part shadow registers, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_SHADOW_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_SHADOW_LOCK_LOCK_SHIFT (0U) -#define OTP_SHADOW_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_SHADOW_LOCK_LOCK_SHIFT) & OTP_SHADOW_LOCK_LOCK_MASK) -#define OTP_SHADOW_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_SHADOW_LOCK_LOCK_MASK) >> OTP_SHADOW_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register array: FUSE */ -/* - * FUSE (RW) - * - * fuse array, valid in PMIC part only - * read operation will read out value in fuse array - * write operation will update fuse array value(please make sure fuse is unlocked and 2.5V power is ready) - */ -#define OTP_FUSE_FUSE_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_FUSE_SHIFT (0U) -#define OTP_FUSE_FUSE_SET(x) (((uint32_t)(x) << OTP_FUSE_FUSE_SHIFT) & OTP_FUSE_FUSE_MASK) -#define OTP_FUSE_FUSE_GET(x) (((uint32_t)(x) & OTP_FUSE_FUSE_MASK) >> OTP_FUSE_FUSE_SHIFT) - -/* Bitfield definition for register array: FUSE_LOCK */ -/* - * LOCK (RW) - * - * lock for fuse array, 2 bits per 32 bit word, lock behavior is different between different fuse types - * 00: not locked - * 01: soft locked - * 10: not locked, and cannot lock in furture - * 11: double locked - */ -#define OTP_FUSE_LOCK_LOCK_MASK (0xFFFFFFFFUL) -#define OTP_FUSE_LOCK_LOCK_SHIFT (0U) -#define OTP_FUSE_LOCK_LOCK_SET(x) (((uint32_t)(x) << OTP_FUSE_LOCK_LOCK_SHIFT) & OTP_FUSE_LOCK_LOCK_MASK) -#define OTP_FUSE_LOCK_LOCK_GET(x) (((uint32_t)(x) & OTP_FUSE_LOCK_LOCK_MASK) >> OTP_FUSE_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK (RW) - * - * unlock word for fuse array operation - * write "OPEN" to unlock fuse array, write any other value will lock write to fuse. - * Please make sure 24M crystal is running and 2.5V LDO working properly - */ -#define OTP_UNLOCK_UNLOCK_MASK (0xFFFFFFFFUL) -#define OTP_UNLOCK_UNLOCK_SHIFT (0U) -#define OTP_UNLOCK_UNLOCK_SET(x) (((uint32_t)(x) << OTP_UNLOCK_UNLOCK_SHIFT) & OTP_UNLOCK_UNLOCK_MASK) -#define OTP_UNLOCK_UNLOCK_GET(x) (((uint32_t)(x) & OTP_UNLOCK_UNLOCK_MASK) >> OTP_UNLOCK_UNLOCK_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * data register for non-blocking access - * this register hold dat read from fuse array or data to by programmed to fuse array - */ -#define OTP_DATA_DATA_MASK (0xFFFFFFFFUL) -#define OTP_DATA_DATA_SHIFT (0U) -#define OTP_DATA_DATA_SET(x) (((uint32_t)(x) << OTP_DATA_DATA_SHIFT) & OTP_DATA_DATA_MASK) -#define OTP_DATA_DATA_GET(x) (((uint32_t)(x) & OTP_DATA_DATA_MASK) >> OTP_DATA_DATA_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * word address to be read or write - */ -#define OTP_ADDR_ADDR_MASK (0x7FU) -#define OTP_ADDR_ADDR_SHIFT (0U) -#define OTP_ADDR_ADDR_SET(x) (((uint32_t)(x) << OTP_ADDR_ADDR_SHIFT) & OTP_ADDR_ADDR_MASK) -#define OTP_ADDR_ADDR_GET(x) (((uint32_t)(x) & OTP_ADDR_ADDR_MASK) >> OTP_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * command to access fure array - * "BLOW" will update fuse word at ADDR to value hold in DATA - * "READ" will fetch fuse value in at ADDR to DATA register - */ -#define OTP_CMD_CMD_MASK (0xFFFFFFFFUL) -#define OTP_CMD_CMD_SHIFT (0U) -#define OTP_CMD_CMD_SET(x) (((uint32_t)(x) << OTP_CMD_CMD_SHIFT) & OTP_CMD_CMD_MASK) -#define OTP_CMD_CMD_GET(x) (((uint32_t)(x) & OTP_CMD_CMD_MASK) >> OTP_CMD_CMD_SHIFT) - -/* Bitfield definition for register: LOAD_REQ */ -/* - * REQUEST (RW) - * - * reload request for 4 regions - * bit0: region0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_REQ_REQUEST_MASK (0xFU) -#define OTP_LOAD_REQ_REQUEST_SHIFT (0U) -#define OTP_LOAD_REQ_REQUEST_SET(x) (((uint32_t)(x) << OTP_LOAD_REQ_REQUEST_SHIFT) & OTP_LOAD_REQ_REQUEST_MASK) -#define OTP_LOAD_REQ_REQUEST_GET(x) (((uint32_t)(x) & OTP_LOAD_REQ_REQUEST_MASK) >> OTP_LOAD_REQ_REQUEST_SHIFT) - -/* Bitfield definition for register: LOAD_COMP */ -/* - * COMPLETE (RW) - * - * reload complete sign for 4 regions - * bit0: region 0 - * bit1: region1 - * bit2: region2 - * bit3: region3 - */ -#define OTP_LOAD_COMP_COMPLETE_MASK (0xFU) -#define OTP_LOAD_COMP_COMPLETE_SHIFT (0U) -#define OTP_LOAD_COMP_COMPLETE_SET(x) (((uint32_t)(x) << OTP_LOAD_COMP_COMPLETE_SHIFT) & OTP_LOAD_COMP_COMPLETE_MASK) -#define OTP_LOAD_COMP_COMPLETE_GET(x) (((uint32_t)(x) & OTP_LOAD_COMP_COMPLETE_MASK) >> OTP_LOAD_COMP_COMPLETE_SHIFT) - -/* Bitfield definition for register array: REGION */ -/* - * STOP (RW) - * - * stop address of load region, fuse word at end address will NOT be reloaded - * region0: fixed at 8 - * region1: fixed at 16 - * region2: fixed at 0, - * region3: usrer configurable - */ -#define OTP_REGION_STOP_MASK (0x7F00U) -#define OTP_REGION_STOP_SHIFT (8U) -#define OTP_REGION_STOP_SET(x) (((uint32_t)(x) << OTP_REGION_STOP_SHIFT) & OTP_REGION_STOP_MASK) -#define OTP_REGION_STOP_GET(x) (((uint32_t)(x) & OTP_REGION_STOP_MASK) >> OTP_REGION_STOP_SHIFT) - -/* - * START (RW) - * - * start address of load region, fuse word at start address will be reloaded - * region0: fixed at 0 - * region1: fixed at 8 - * region2: fixed at 16, - * region3: usrer configurable - */ -#define OTP_REGION_START_MASK (0x7FU) -#define OTP_REGION_START_SHIFT (0U) -#define OTP_REGION_START_SET(x) (((uint32_t)(x) << OTP_REGION_START_SHIFT) & OTP_REGION_START_MASK) -#define OTP_REGION_START_GET(x) (((uint32_t)(x) & OTP_REGION_START_MASK) >> OTP_REGION_START_SHIFT) - -/* Bitfield definition for register: INT_FLAG */ -/* - * WRITE (RW) - * - * fuse write flag, write 1 to clear - * 0: fuse is not written or writing - * 1: value in DATA register is programmed into fuse - */ -#define OTP_INT_FLAG_WRITE_MASK (0x4U) -#define OTP_INT_FLAG_WRITE_SHIFT (2U) -#define OTP_INT_FLAG_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_WRITE_SHIFT) & OTP_INT_FLAG_WRITE_MASK) -#define OTP_INT_FLAG_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_WRITE_MASK) >> OTP_INT_FLAG_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read flag, write 1 to clear - * 0: fuse is not read or reading - * 1: fuse value is put in DATA register - */ -#define OTP_INT_FLAG_READ_MASK (0x2U) -#define OTP_INT_FLAG_READ_SHIFT (1U) -#define OTP_INT_FLAG_READ_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_READ_SHIFT) & OTP_INT_FLAG_READ_MASK) -#define OTP_INT_FLAG_READ_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_READ_MASK) >> OTP_INT_FLAG_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load flag, write 1 to clear - * 0: fuse is not loaded or loading - * 1: fuse loaded - */ -#define OTP_INT_FLAG_LOAD_MASK (0x1U) -#define OTP_INT_FLAG_LOAD_SHIFT (0U) -#define OTP_INT_FLAG_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_FLAG_LOAD_SHIFT) & OTP_INT_FLAG_LOAD_MASK) -#define OTP_INT_FLAG_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_FLAG_LOAD_MASK) >> OTP_INT_FLAG_LOAD_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * WRITE (RW) - * - * fuse write interrupt enable - * 0: fuse write interrupt is not enable - * 1: fuse write interrupt is enable - */ -#define OTP_INT_EN_WRITE_MASK (0x4U) -#define OTP_INT_EN_WRITE_SHIFT (2U) -#define OTP_INT_EN_WRITE_SET(x) (((uint32_t)(x) << OTP_INT_EN_WRITE_SHIFT) & OTP_INT_EN_WRITE_MASK) -#define OTP_INT_EN_WRITE_GET(x) (((uint32_t)(x) & OTP_INT_EN_WRITE_MASK) >> OTP_INT_EN_WRITE_SHIFT) - -/* - * READ (RW) - * - * fuse read interrupt enable - * 0: fuse read interrupt is not enable - * 1: fuse read interrupt is enable - */ -#define OTP_INT_EN_READ_MASK (0x2U) -#define OTP_INT_EN_READ_SHIFT (1U) -#define OTP_INT_EN_READ_SET(x) (((uint32_t)(x) << OTP_INT_EN_READ_SHIFT) & OTP_INT_EN_READ_MASK) -#define OTP_INT_EN_READ_GET(x) (((uint32_t)(x) & OTP_INT_EN_READ_MASK) >> OTP_INT_EN_READ_SHIFT) - -/* - * LOAD (RW) - * - * fuse load interrupt enable - * 0: fuse load interrupt is not enable - * 1: fuse load interrupt is enable - */ -#define OTP_INT_EN_LOAD_MASK (0x1U) -#define OTP_INT_EN_LOAD_SHIFT (0U) -#define OTP_INT_EN_LOAD_SET(x) (((uint32_t)(x) << OTP_INT_EN_LOAD_SHIFT) & OTP_INT_EN_LOAD_MASK) -#define OTP_INT_EN_LOAD_GET(x) (((uint32_t)(x) & OTP_INT_EN_LOAD_MASK) >> OTP_INT_EN_LOAD_SHIFT) - - - -/* SHADOW register group index macro definition */ -#define OTP_SHADOW_SHADOW000 (0UL) -#define OTP_SHADOW_SHADOW001 (1UL) -#define OTP_SHADOW_SHADOW002 (2UL) -#define OTP_SHADOW_SHADOW003 (3UL) -#define OTP_SHADOW_SHADOW004 (4UL) -#define OTP_SHADOW_SHADOW005 (5UL) -#define OTP_SHADOW_SHADOW006 (6UL) -#define OTP_SHADOW_SHADOW007 (7UL) -#define OTP_SHADOW_SHADOW008 (8UL) -#define OTP_SHADOW_SHADOW009 (9UL) -#define OTP_SHADOW_SHADOW010 (10UL) -#define OTP_SHADOW_SHADOW011 (11UL) -#define OTP_SHADOW_SHADOW012 (12UL) -#define OTP_SHADOW_SHADOW013 (13UL) -#define OTP_SHADOW_SHADOW014 (14UL) -#define OTP_SHADOW_SHADOW015 (15UL) -#define OTP_SHADOW_SHADOW016 (16UL) -#define OTP_SHADOW_SHADOW017 (17UL) -#define OTP_SHADOW_SHADOW018 (18UL) -#define OTP_SHADOW_SHADOW019 (19UL) -#define OTP_SHADOW_SHADOW020 (20UL) -#define OTP_SHADOW_SHADOW021 (21UL) -#define OTP_SHADOW_SHADOW022 (22UL) -#define OTP_SHADOW_SHADOW023 (23UL) -#define OTP_SHADOW_SHADOW024 (24UL) -#define OTP_SHADOW_SHADOW025 (25UL) -#define OTP_SHADOW_SHADOW026 (26UL) -#define OTP_SHADOW_SHADOW027 (27UL) -#define OTP_SHADOW_SHADOW028 (28UL) -#define OTP_SHADOW_SHADOW029 (29UL) -#define OTP_SHADOW_SHADOW030 (30UL) -#define OTP_SHADOW_SHADOW031 (31UL) -#define OTP_SHADOW_SHADOW032 (32UL) -#define OTP_SHADOW_SHADOW033 (33UL) -#define OTP_SHADOW_SHADOW034 (34UL) -#define OTP_SHADOW_SHADOW035 (35UL) -#define OTP_SHADOW_SHADOW036 (36UL) -#define OTP_SHADOW_SHADOW037 (37UL) -#define OTP_SHADOW_SHADOW038 (38UL) -#define OTP_SHADOW_SHADOW039 (39UL) -#define OTP_SHADOW_SHADOW040 (40UL) -#define OTP_SHADOW_SHADOW041 (41UL) -#define OTP_SHADOW_SHADOW042 (42UL) -#define OTP_SHADOW_SHADOW043 (43UL) -#define OTP_SHADOW_SHADOW044 (44UL) -#define OTP_SHADOW_SHADOW045 (45UL) -#define OTP_SHADOW_SHADOW046 (46UL) -#define OTP_SHADOW_SHADOW047 (47UL) -#define OTP_SHADOW_SHADOW048 (48UL) -#define OTP_SHADOW_SHADOW049 (49UL) -#define OTP_SHADOW_SHADOW050 (50UL) -#define OTP_SHADOW_SHADOW051 (51UL) -#define OTP_SHADOW_SHADOW052 (52UL) -#define OTP_SHADOW_SHADOW053 (53UL) -#define OTP_SHADOW_SHADOW054 (54UL) -#define OTP_SHADOW_SHADOW055 (55UL) -#define OTP_SHADOW_SHADOW056 (56UL) -#define OTP_SHADOW_SHADOW057 (57UL) -#define OTP_SHADOW_SHADOW058 (58UL) -#define OTP_SHADOW_SHADOW059 (59UL) -#define OTP_SHADOW_SHADOW060 (60UL) -#define OTP_SHADOW_SHADOW061 (61UL) -#define OTP_SHADOW_SHADOW062 (62UL) -#define OTP_SHADOW_SHADOW063 (63UL) -#define OTP_SHADOW_SHADOW064 (64UL) -#define OTP_SHADOW_SHADOW065 (65UL) -#define OTP_SHADOW_SHADOW066 (66UL) -#define OTP_SHADOW_SHADOW067 (67UL) -#define OTP_SHADOW_SHADOW068 (68UL) -#define OTP_SHADOW_SHADOW069 (69UL) -#define OTP_SHADOW_SHADOW070 (70UL) -#define OTP_SHADOW_SHADOW071 (71UL) -#define OTP_SHADOW_SHADOW072 (72UL) -#define OTP_SHADOW_SHADOW073 (73UL) -#define OTP_SHADOW_SHADOW074 (74UL) -#define OTP_SHADOW_SHADOW075 (75UL) -#define OTP_SHADOW_SHADOW076 (76UL) -#define OTP_SHADOW_SHADOW077 (77UL) -#define OTP_SHADOW_SHADOW078 (78UL) -#define OTP_SHADOW_SHADOW079 (79UL) -#define OTP_SHADOW_SHADOW080 (80UL) -#define OTP_SHADOW_SHADOW081 (81UL) -#define OTP_SHADOW_SHADOW082 (82UL) -#define OTP_SHADOW_SHADOW083 (83UL) -#define OTP_SHADOW_SHADOW084 (84UL) -#define OTP_SHADOW_SHADOW085 (85UL) -#define OTP_SHADOW_SHADOW086 (86UL) -#define OTP_SHADOW_SHADOW087 (87UL) -#define OTP_SHADOW_SHADOW088 (88UL) -#define OTP_SHADOW_SHADOW089 (89UL) -#define OTP_SHADOW_SHADOW090 (90UL) -#define OTP_SHADOW_SHADOW091 (91UL) -#define OTP_SHADOW_SHADOW092 (92UL) -#define OTP_SHADOW_SHADOW093 (93UL) -#define OTP_SHADOW_SHADOW094 (94UL) -#define OTP_SHADOW_SHADOW095 (95UL) -#define OTP_SHADOW_SHADOW096 (96UL) -#define OTP_SHADOW_SHADOW097 (97UL) -#define OTP_SHADOW_SHADOW098 (98UL) -#define OTP_SHADOW_SHADOW099 (99UL) -#define OTP_SHADOW_SHADOW100 (100UL) -#define OTP_SHADOW_SHADOW101 (101UL) -#define OTP_SHADOW_SHADOW102 (102UL) -#define OTP_SHADOW_SHADOW103 (103UL) -#define OTP_SHADOW_SHADOW104 (104UL) -#define OTP_SHADOW_SHADOW105 (105UL) -#define OTP_SHADOW_SHADOW106 (106UL) -#define OTP_SHADOW_SHADOW107 (107UL) -#define OTP_SHADOW_SHADOW108 (108UL) -#define OTP_SHADOW_SHADOW109 (109UL) -#define OTP_SHADOW_SHADOW110 (110UL) -#define OTP_SHADOW_SHADOW111 (111UL) -#define OTP_SHADOW_SHADOW112 (112UL) -#define OTP_SHADOW_SHADOW113 (113UL) -#define OTP_SHADOW_SHADOW114 (114UL) -#define OTP_SHADOW_SHADOW115 (115UL) -#define OTP_SHADOW_SHADOW116 (116UL) -#define OTP_SHADOW_SHADOW117 (117UL) -#define OTP_SHADOW_SHADOW118 (118UL) -#define OTP_SHADOW_SHADOW119 (119UL) -#define OTP_SHADOW_SHADOW120 (120UL) -#define OTP_SHADOW_SHADOW121 (121UL) -#define OTP_SHADOW_SHADOW122 (122UL) -#define OTP_SHADOW_SHADOW123 (123UL) -#define OTP_SHADOW_SHADOW124 (124UL) -#define OTP_SHADOW_SHADOW125 (125UL) -#define OTP_SHADOW_SHADOW126 (126UL) -#define OTP_SHADOW_SHADOW127 (127UL) - -/* SHADOW_LOCK register group index macro definition */ -#define OTP_SHADOW_LOCK_LOCK00 (0UL) -#define OTP_SHADOW_LOCK_LOCK01 (1UL) -#define OTP_SHADOW_LOCK_LOCK02 (2UL) -#define OTP_SHADOW_LOCK_LOCK03 (3UL) -#define OTP_SHADOW_LOCK_LOCK04 (4UL) -#define OTP_SHADOW_LOCK_LOCK05 (5UL) -#define OTP_SHADOW_LOCK_LOCK06 (6UL) -#define OTP_SHADOW_LOCK_LOCK07 (7UL) - -/* FUSE register group index macro definition */ -#define OTP_FUSE_FUSE000 (0UL) -#define OTP_FUSE_FUSE001 (1UL) -#define OTP_FUSE_FUSE002 (2UL) -#define OTP_FUSE_FUSE003 (3UL) -#define OTP_FUSE_FUSE004 (4UL) -#define OTP_FUSE_FUSE005 (5UL) -#define OTP_FUSE_FUSE006 (6UL) -#define OTP_FUSE_FUSE007 (7UL) -#define OTP_FUSE_FUSE008 (8UL) -#define OTP_FUSE_FUSE009 (9UL) -#define OTP_FUSE_FUSE010 (10UL) -#define OTP_FUSE_FUSE011 (11UL) -#define OTP_FUSE_FUSE012 (12UL) -#define OTP_FUSE_FUSE013 (13UL) -#define OTP_FUSE_FUSE014 (14UL) -#define OTP_FUSE_FUSE015 (15UL) -#define OTP_FUSE_FUSE016 (16UL) -#define OTP_FUSE_FUSE017 (17UL) -#define OTP_FUSE_FUSE018 (18UL) -#define OTP_FUSE_FUSE019 (19UL) -#define OTP_FUSE_FUSE020 (20UL) -#define OTP_FUSE_FUSE021 (21UL) -#define OTP_FUSE_FUSE022 (22UL) -#define OTP_FUSE_FUSE023 (23UL) -#define OTP_FUSE_FUSE024 (24UL) -#define OTP_FUSE_FUSE025 (25UL) -#define OTP_FUSE_FUSE026 (26UL) -#define OTP_FUSE_FUSE027 (27UL) -#define OTP_FUSE_FUSE028 (28UL) -#define OTP_FUSE_FUSE029 (29UL) -#define OTP_FUSE_FUSE030 (30UL) -#define OTP_FUSE_FUSE031 (31UL) -#define OTP_FUSE_FUSE032 (32UL) -#define OTP_FUSE_FUSE033 (33UL) -#define OTP_FUSE_FUSE034 (34UL) -#define OTP_FUSE_FUSE035 (35UL) -#define OTP_FUSE_FUSE036 (36UL) -#define OTP_FUSE_FUSE037 (37UL) -#define OTP_FUSE_FUSE038 (38UL) -#define OTP_FUSE_FUSE039 (39UL) -#define OTP_FUSE_FUSE040 (40UL) -#define OTP_FUSE_FUSE041 (41UL) -#define OTP_FUSE_FUSE042 (42UL) -#define OTP_FUSE_FUSE043 (43UL) -#define OTP_FUSE_FUSE044 (44UL) -#define OTP_FUSE_FUSE045 (45UL) -#define OTP_FUSE_FUSE046 (46UL) -#define OTP_FUSE_FUSE047 (47UL) -#define OTP_FUSE_FUSE048 (48UL) -#define OTP_FUSE_FUSE049 (49UL) -#define OTP_FUSE_FUSE050 (50UL) -#define OTP_FUSE_FUSE051 (51UL) -#define OTP_FUSE_FUSE052 (52UL) -#define OTP_FUSE_FUSE053 (53UL) -#define OTP_FUSE_FUSE054 (54UL) -#define OTP_FUSE_FUSE055 (55UL) -#define OTP_FUSE_FUSE056 (56UL) -#define OTP_FUSE_FUSE057 (57UL) -#define OTP_FUSE_FUSE058 (58UL) -#define OTP_FUSE_FUSE059 (59UL) -#define OTP_FUSE_FUSE060 (60UL) -#define OTP_FUSE_FUSE061 (61UL) -#define OTP_FUSE_FUSE062 (62UL) -#define OTP_FUSE_FUSE063 (63UL) -#define OTP_FUSE_FUSE064 (64UL) -#define OTP_FUSE_FUSE065 (65UL) -#define OTP_FUSE_FUSE066 (66UL) -#define OTP_FUSE_FUSE067 (67UL) -#define OTP_FUSE_FUSE068 (68UL) -#define OTP_FUSE_FUSE069 (69UL) -#define OTP_FUSE_FUSE070 (70UL) -#define OTP_FUSE_FUSE071 (71UL) -#define OTP_FUSE_FUSE072 (72UL) -#define OTP_FUSE_FUSE073 (73UL) -#define OTP_FUSE_FUSE074 (74UL) -#define OTP_FUSE_FUSE075 (75UL) -#define OTP_FUSE_FUSE076 (76UL) -#define OTP_FUSE_FUSE077 (77UL) -#define OTP_FUSE_FUSE078 (78UL) -#define OTP_FUSE_FUSE079 (79UL) -#define OTP_FUSE_FUSE080 (80UL) -#define OTP_FUSE_FUSE081 (81UL) -#define OTP_FUSE_FUSE082 (82UL) -#define OTP_FUSE_FUSE083 (83UL) -#define OTP_FUSE_FUSE084 (84UL) -#define OTP_FUSE_FUSE085 (85UL) -#define OTP_FUSE_FUSE086 (86UL) -#define OTP_FUSE_FUSE087 (87UL) -#define OTP_FUSE_FUSE088 (88UL) -#define OTP_FUSE_FUSE089 (89UL) -#define OTP_FUSE_FUSE090 (90UL) -#define OTP_FUSE_FUSE091 (91UL) -#define OTP_FUSE_FUSE092 (92UL) -#define OTP_FUSE_FUSE093 (93UL) -#define OTP_FUSE_FUSE094 (94UL) -#define OTP_FUSE_FUSE095 (95UL) -#define OTP_FUSE_FUSE096 (96UL) -#define OTP_FUSE_FUSE097 (97UL) -#define OTP_FUSE_FUSE098 (98UL) -#define OTP_FUSE_FUSE099 (99UL) -#define OTP_FUSE_FUSE100 (100UL) -#define OTP_FUSE_FUSE101 (101UL) -#define OTP_FUSE_FUSE102 (102UL) -#define OTP_FUSE_FUSE103 (103UL) -#define OTP_FUSE_FUSE104 (104UL) -#define OTP_FUSE_FUSE105 (105UL) -#define OTP_FUSE_FUSE106 (106UL) -#define OTP_FUSE_FUSE107 (107UL) -#define OTP_FUSE_FUSE108 (108UL) -#define OTP_FUSE_FUSE109 (109UL) -#define OTP_FUSE_FUSE110 (110UL) -#define OTP_FUSE_FUSE111 (111UL) -#define OTP_FUSE_FUSE112 (112UL) -#define OTP_FUSE_FUSE113 (113UL) -#define OTP_FUSE_FUSE114 (114UL) -#define OTP_FUSE_FUSE115 (115UL) -#define OTP_FUSE_FUSE116 (116UL) -#define OTP_FUSE_FUSE117 (117UL) -#define OTP_FUSE_FUSE118 (118UL) -#define OTP_FUSE_FUSE119 (119UL) -#define OTP_FUSE_FUSE120 (120UL) -#define OTP_FUSE_FUSE121 (121UL) -#define OTP_FUSE_FUSE122 (122UL) -#define OTP_FUSE_FUSE123 (123UL) -#define OTP_FUSE_FUSE124 (124UL) -#define OTP_FUSE_FUSE125 (125UL) -#define OTP_FUSE_FUSE126 (126UL) -#define OTP_FUSE_FUSE127 (127UL) - -/* FUSE_LOCK register group index macro definition */ -#define OTP_FUSE_LOCK_LOCK00 (0UL) -#define OTP_FUSE_LOCK_LOCK01 (1UL) -#define OTP_FUSE_LOCK_LOCK02 (2UL) -#define OTP_FUSE_LOCK_LOCK03 (3UL) -#define OTP_FUSE_LOCK_LOCK04 (4UL) -#define OTP_FUSE_LOCK_LOCK05 (5UL) -#define OTP_FUSE_LOCK_LOCK06 (6UL) -#define OTP_FUSE_LOCK_LOCK07 (7UL) - -/* REGION register group index macro definition */ -#define OTP_REGION_LOAD_REGION0 (0UL) -#define OTP_REGION_LOAD_REGION1 (1UL) -#define OTP_REGION_LOAD_REGION2 (2UL) -#define OTP_REGION_LOAD_REGION3 (3UL) - - -#endif /* HPM_OTP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pcfg_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pcfg_regs.h deleted file mode 100644 index 4bcd2b00db7..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pcfg_regs.h +++ /dev/null @@ -1,840 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PCFG_H -#define HPM_PCFG_H - -typedef struct { - __RW uint32_t BANDGAP; /* 0x0: BANGGAP control */ - __RW uint32_t LDO1P1; /* 0x4: 1V LDO config */ - __RW uint32_t LDO2P5; /* 0x8: 2.5V LDO config */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t DCDC_MODE; /* 0x10: DCDC mode select */ - __RW uint32_t DCDC_LPMODE; /* 0x14: DCDC low power mode */ - __RW uint32_t DCDC_PROT; /* 0x18: DCDC protection */ - __RW uint32_t DCDC_CURRENT; /* 0x1C: DCDC current estimation */ - __RW uint32_t DCDC_ADVMODE; /* 0x20: DCDC advance setting */ - __RW uint32_t DCDC_ADVPARAM; /* 0x24: DCDC advance parameter */ - __RW uint32_t DCDC_MISC; /* 0x28: DCDC misc parameter */ - __RW uint32_t DCDC_DEBUG; /* 0x2C: DCDC Debug */ - __RW uint32_t DCDC_START_TIME; /* 0x30: DCDC ramp time */ - __RW uint32_t DCDC_RESUME_TIME; /* 0x34: DCDC resume time */ - __R uint8_t RESERVED1[8]; /* 0x38 - 0x3F: Reserved */ - __RW uint32_t POWER_TRAP; /* 0x40: SOC power trap */ - __RW uint32_t WAKE_CAUSE; /* 0x44: Wake up source */ - __RW uint32_t WAKE_MASK; /* 0x48: Wake up mask */ - __RW uint32_t SCG_CTRL; /* 0x4C: Clock gate control in PMIC */ - __R uint8_t RESERVED2[16]; /* 0x50 - 0x5F: Reserved */ - __RW uint32_t RC24M; /* 0x60: RC 24M config */ - __RW uint32_t RC24M_TRACK; /* 0x64: RC 24M track mode */ - __RW uint32_t TRACK_TARGET; /* 0x68: RC 24M track target */ - __R uint32_t STATUS; /* 0x6C: RC 24M track status */ -} PCFG_Type; - - -/* Bitfield definition for register: BANDGAP */ -/* - * VBG_TRIMMED (RW) - * - * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: bandgap is not trimmed - * 1: bandgap is trimmed - */ -#define PCFG_BANDGAP_VBG_TRIMMED_MASK (0x80000000UL) -#define PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31U) -#define PCFG_BANDGAP_VBG_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_TRIMMED_SHIFT) & PCFG_BANDGAP_VBG_TRIMMED_MASK) -#define PCFG_BANDGAP_VBG_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_TRIMMED_MASK) >> PCFG_BANDGAP_VBG_TRIMMED_SHIFT) - -/* - * VBG_1P0_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F0000UL) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16U) -#define PCFG_BANDGAP_VBG_1P0_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) -#define PCFG_BANDGAP_VBG_1P0_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_1P0_TRIM_MASK) >> PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) - -/* - * VBG_P65_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F00U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8U) -#define PCFG_BANDGAP_VBG_P65_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P65_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P65_TRIM_MASK) >> PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) - -/* - * VBG_P50_TRIM (RW) - * - * Banggap 1.0V output trim value - */ -#define PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1FU) -#define PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0U) -#define PCFG_BANDGAP_VBG_P50_TRIM_SET(x) (((uint32_t)(x) << PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) -#define PCFG_BANDGAP_VBG_P50_TRIM_GET(x) (((uint32_t)(x) & PCFG_BANDGAP_VBG_P50_TRIM_MASK) >> PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) - -/* Bitfield definition for register: LDO1P1 */ -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 700-1320, , step 20mV. Hardware select voltage no less than target if not on valid steps, with maximum 1320mV. - * 700: 700mV - * 720: 720mV - * . . . - * 1320:1320mV - */ -#define PCFG_LDO1P1_VOLT_MASK (0xFFFU) -#define PCFG_LDO1P1_VOLT_SHIFT (0U) -#define PCFG_LDO1P1_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO1P1_VOLT_SHIFT) & PCFG_LDO1P1_VOLT_MASK) -#define PCFG_LDO1P1_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO1P1_VOLT_MASK) >> PCFG_LDO1P1_VOLT_SHIFT) - -/* Bitfield definition for register: LDO2P5 */ -/* - * READY (RO) - * - * Ready flag, will set 1ms after enabled or voltage change - * 0: LDO is not ready for use - * 1: LDO is ready - */ -#define PCFG_LDO2P5_READY_MASK (0x10000000UL) -#define PCFG_LDO2P5_READY_SHIFT (28U) -#define PCFG_LDO2P5_READY_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_READY_MASK) >> PCFG_LDO2P5_READY_SHIFT) - -/* - * ENABLE (RW) - * - * LDO enable - * 0: turn off LDO - * 1: turn on LDO - */ -#define PCFG_LDO2P5_ENABLE_MASK (0x10000UL) -#define PCFG_LDO2P5_ENABLE_SHIFT (16U) -#define PCFG_LDO2P5_ENABLE_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_ENABLE_SHIFT) & PCFG_LDO2P5_ENABLE_MASK) -#define PCFG_LDO2P5_ENABLE_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_ENABLE_MASK) >> PCFG_LDO2P5_ENABLE_SHIFT) - -/* - * VOLT (RW) - * - * LDO output voltage in mV, value valid through 2125-2900, step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 2900mV. - * 2125: 2125mV - * 2150: 2150mV - * . . . - * 2900:2900mV - */ -#define PCFG_LDO2P5_VOLT_MASK (0xFFFU) -#define PCFG_LDO2P5_VOLT_SHIFT (0U) -#define PCFG_LDO2P5_VOLT_SET(x) (((uint32_t)(x) << PCFG_LDO2P5_VOLT_SHIFT) & PCFG_LDO2P5_VOLT_MASK) -#define PCFG_LDO2P5_VOLT_GET(x) (((uint32_t)(x) & PCFG_LDO2P5_VOLT_MASK) >> PCFG_LDO2P5_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_MODE */ -/* - * READY (RO) - * - * Ready flag - * 0: DCDC is applying new change - * 1: DCDC is ready - */ -#define PCFG_DCDC_MODE_READY_MASK (0x10000000UL) -#define PCFG_DCDC_MODE_READY_SHIFT (28U) -#define PCFG_DCDC_MODE_READY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_READY_MASK) >> PCFG_DCDC_MODE_READY_SHIFT) - -/* - * MODE (RW) - * - * DCDC work mode - * XX0: trun off - * 001: basic mode - * 011: generic mode - * 101: automatic mode - * 111: expert mode - */ -#define PCFG_DCDC_MODE_MODE_MASK (0x70000UL) -#define PCFG_DCDC_MODE_MODE_SHIFT (16U) -#define PCFG_DCDC_MODE_MODE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_MODE_SHIFT) & PCFG_DCDC_MODE_MODE_MASK) -#define PCFG_DCDC_MODE_MODE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_MODE_MASK) >> PCFG_DCDC_MODE_MODE_SHIFT) - -/* - * VOLT (RW) - * - * DCDC voltage in mV in normal mode, value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_MODE_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_MODE_VOLT_SHIFT (0U) -#define PCFG_DCDC_MODE_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_MODE_VOLT_SHIFT) & PCFG_DCDC_MODE_VOLT_MASK) -#define PCFG_DCDC_MODE_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_MODE_VOLT_MASK) >> PCFG_DCDC_MODE_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_LPMODE */ -/* - * STBY_VOLT (RW) - * - * DCDC voltage in mV in standby mode, , value valid through 600-1375, , step 25mV. Hardware select voltage no less than target if not on valid steps, with maximum 1375mV. - * 600: 600mV - * 625: 625mV - * . . . - * 1375:1375mV - */ -#define PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0xFFFU) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0U) -#define PCFG_DCDC_LPMODE_STBY_VOLT_SET(x) (((uint32_t)(x) << PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) -#define PCFG_DCDC_LPMODE_STBY_VOLT_GET(x) (((uint32_t)(x) & PCFG_DCDC_LPMODE_STBY_VOLT_MASK) >> PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) - -/* Bitfield definition for register: DCDC_PROT */ -/* - * ILIMIT_LP (RW) - * - * over current setting for low power mode - * 0:250mA - * 1:200mA - */ -#define PCFG_DCDC_PROT_ILIMIT_LP_MASK (0x10000000UL) -#define PCFG_DCDC_PROT_ILIMIT_LP_SHIFT (28U) -#define PCFG_DCDC_PROT_ILIMIT_LP_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) -#define PCFG_DCDC_PROT_ILIMIT_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_ILIMIT_LP_MASK) >> PCFG_DCDC_PROT_ILIMIT_LP_SHIFT) - -/* - * OVERLOAD_LP (RO) - * - * over current in low power mode - * 0: current is below setting - * 1: overcurrent happened in low power mode - */ -#define PCFG_DCDC_PROT_OVERLOAD_LP_MASK (0x1000000UL) -#define PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT (24U) -#define PCFG_DCDC_PROT_OVERLOAD_LP_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERLOAD_LP_MASK) >> PCFG_DCDC_PROT_OVERLOAD_LP_SHIFT) - -/* - * POWER_LOSS_FLAG (RO) - * - * power loss - * 0: input power is good - * 1: input power is too low - */ -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK (0x10000UL) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT (16U) -#define PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_POWER_LOSS_FLAG_MASK) >> PCFG_DCDC_PROT_POWER_LOSS_FLAG_SHIFT) - -/* - * DISABLE_OVERVOLTAGE (RW) - * - * ouput over voltage protection - * 0: protection enabled, DCDC will shut down is output voltage is unexpected high - * 1: protection disabled, DCDC continue to adjust output voltage - */ -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK (0x8000U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT (15U) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) -#define PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK) >> PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_SHIFT) - -/* - * OVERVOLT_FLAG (RO) - * - * output over voltage flag - * 0: output is normal - * 1: output is unexpected high - */ -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK (0x100U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT (8U) -#define PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_OVERVOLT_FLAG_MASK) >> PCFG_DCDC_PROT_OVERVOLT_FLAG_SHIFT) - -/* - * DISABLE_SHORT (RW) - * - * disable output short circuit protection - * 0: short circuits protection enabled, DCDC shut down if short circuit on ouput detected - * 1: short circuit protection disabled - */ -#define PCFG_DCDC_PROT_DISABLE_SHORT_MASK (0x80U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT (7U) -#define PCFG_DCDC_PROT_DISABLE_SHORT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) -#define PCFG_DCDC_PROT_DISABLE_SHORT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_DISABLE_SHORT_MASK) >> PCFG_DCDC_PROT_DISABLE_SHORT_SHIFT) - -/* - * SHORT_CURRENT (RW) - * - * short circuit current setting - * 0: 2.0A, - * 1: 1.3A - */ -#define PCFG_DCDC_PROT_SHORT_CURRENT_MASK (0x10U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT (4U) -#define PCFG_DCDC_PROT_SHORT_CURRENT_SET(x) (((uint32_t)(x) << PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) -#define PCFG_DCDC_PROT_SHORT_CURRENT_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_CURRENT_MASK) >> PCFG_DCDC_PROT_SHORT_CURRENT_SHIFT) - -/* - * SHORT_FLAG (RO) - * - * short circuit flag - * 0: current is within limit - * 1: short circuits detected - */ -#define PCFG_DCDC_PROT_SHORT_FLAG_MASK (0x1U) -#define PCFG_DCDC_PROT_SHORT_FLAG_SHIFT (0U) -#define PCFG_DCDC_PROT_SHORT_FLAG_GET(x) (((uint32_t)(x) & PCFG_DCDC_PROT_SHORT_FLAG_MASK) >> PCFG_DCDC_PROT_SHORT_FLAG_SHIFT) - -/* Bitfield definition for register: DCDC_CURRENT */ -/* - * ESTI_EN (RW) - * - * enable current measure - */ -#define PCFG_DCDC_CURRENT_ESTI_EN_MASK (0x8000U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SHIFT (15U) -#define PCFG_DCDC_CURRENT_ESTI_EN_SET(x) (((uint32_t)(x) << PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) -#define PCFG_DCDC_CURRENT_ESTI_EN_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_ESTI_EN_MASK) >> PCFG_DCDC_CURRENT_ESTI_EN_SHIFT) - -/* - * VALID (RO) - * - * Current level valid - * 0: data is invalid - * 1: data is valid - */ -#define PCFG_DCDC_CURRENT_VALID_MASK (0x100U) -#define PCFG_DCDC_CURRENT_VALID_SHIFT (8U) -#define PCFG_DCDC_CURRENT_VALID_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_VALID_MASK) >> PCFG_DCDC_CURRENT_VALID_SHIFT) - -/* - * LEVEL (RO) - * - * DCDC current level, current level is num * 50mA - */ -#define PCFG_DCDC_CURRENT_LEVEL_MASK (0x1FU) -#define PCFG_DCDC_CURRENT_LEVEL_SHIFT (0U) -#define PCFG_DCDC_CURRENT_LEVEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_CURRENT_LEVEL_MASK) >> PCFG_DCDC_CURRENT_LEVEL_SHIFT) - -/* Bitfield definition for register: DCDC_ADVMODE */ -/* - * EN_RCSCALE (RW) - * - * Enable RC scale - */ -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK (0x7000000UL) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT (24U) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) -#define PCFG_DCDC_ADVMODE_EN_RCSCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_RCSCALE_MASK) >> PCFG_DCDC_ADVMODE_EN_RCSCALE_SHIFT) - -/* - * DC_C (RW) - * - * Loop C number - */ -#define PCFG_DCDC_ADVMODE_DC_C_MASK (0x300000UL) -#define PCFG_DCDC_ADVMODE_DC_C_SHIFT (20U) -#define PCFG_DCDC_ADVMODE_DC_C_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_C_SHIFT) & PCFG_DCDC_ADVMODE_DC_C_MASK) -#define PCFG_DCDC_ADVMODE_DC_C_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_C_MASK) >> PCFG_DCDC_ADVMODE_DC_C_SHIFT) - -/* - * DC_R (RW) - * - * Loop R number - */ -#define PCFG_DCDC_ADVMODE_DC_R_MASK (0xF0000UL) -#define PCFG_DCDC_ADVMODE_DC_R_SHIFT (16U) -#define PCFG_DCDC_ADVMODE_DC_R_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_DC_R_SHIFT) & PCFG_DCDC_ADVMODE_DC_R_MASK) -#define PCFG_DCDC_ADVMODE_DC_R_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_DC_R_MASK) >> PCFG_DCDC_ADVMODE_DC_R_SHIFT) - -/* - * EN_FF_DET (RW) - * - * enable feed forward detect - * 0: feed forward detect is disabled - * 1: feed forward detect is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_DET_MASK (0x40U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT (6U) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_DET_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_DET_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_DET_SHIFT) - -/* - * EN_FF_LOOP (RW) - * - * enable feed forward loop - * 0: feed forward loop is disabled - * 1: feed forward loop is enabled - */ -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK (0x20U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT (5U) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) -#define PCFG_DCDC_ADVMODE_EN_FF_LOOP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_FF_LOOP_MASK) >> PCFG_DCDC_ADVMODE_EN_FF_LOOP_SHIFT) - -/* - * EN_AUTOLP (RW) - * - * enable auto enter low power mode - * 0: do not enter low power mode - * 1: enter low power mode if current is detected low - */ -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK (0x10U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT (4U) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) -#define PCFG_DCDC_ADVMODE_EN_AUTOLP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_AUTOLP_MASK) >> PCFG_DCDC_ADVMODE_EN_AUTOLP_SHIFT) - -/* - * EN_DCM_EXIT (RW) - * - * avoid over voltage - * 0: stay in DCM mode when voltage excess - * 1: change to CCM mode when voltage excess - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK (0x8U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT (3U) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_EXIT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_EXIT_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_EXIT_SHIFT) - -/* - * EN_SKIP (RW) - * - * enable skip on narrow pulse - * 0: do not skip narrow pulse - * 1: skip narrow pulse - */ -#define PCFG_DCDC_ADVMODE_EN_SKIP_MASK (0x4U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT (2U) -#define PCFG_DCDC_ADVMODE_EN_SKIP_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) -#define PCFG_DCDC_ADVMODE_EN_SKIP_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_SKIP_MASK) >> PCFG_DCDC_ADVMODE_EN_SKIP_SHIFT) - -/* - * EN_IDLE (RW) - * - * enable skip when voltage is higher than threshold - * 0: do not skip - * 1: skip if voltage is excess - */ -#define PCFG_DCDC_ADVMODE_EN_IDLE_MASK (0x2U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT (1U) -#define PCFG_DCDC_ADVMODE_EN_IDLE_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) -#define PCFG_DCDC_ADVMODE_EN_IDLE_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_IDLE_MASK) >> PCFG_DCDC_ADVMODE_EN_IDLE_SHIFT) - -/* - * EN_DCM (RW) - * - * DCM mode - * 0: CCM mode - * 1: DCM mode - */ -#define PCFG_DCDC_ADVMODE_EN_DCM_MASK (0x1U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SHIFT (0U) -#define PCFG_DCDC_ADVMODE_EN_DCM_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) -#define PCFG_DCDC_ADVMODE_EN_DCM_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVMODE_EN_DCM_MASK) >> PCFG_DCDC_ADVMODE_EN_DCM_SHIFT) - -/* Bitfield definition for register: DCDC_ADVPARAM */ -/* - * MIN_DUT (RW) - * - * minimum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MIN_DUT_MASK (0x7F00U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT (8U) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MIN_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MIN_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MIN_DUT_SHIFT) - -/* - * MAX_DUT (RW) - * - * maximum duty cycle - */ -#define PCFG_DCDC_ADVPARAM_MAX_DUT_MASK (0x7FU) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT (0U) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_SET(x) (((uint32_t)(x) << PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) -#define PCFG_DCDC_ADVPARAM_MAX_DUT_GET(x) (((uint32_t)(x) & PCFG_DCDC_ADVPARAM_MAX_DUT_MASK) >> PCFG_DCDC_ADVPARAM_MAX_DUT_SHIFT) - -/* Bitfield definition for register: DCDC_MISC */ -/* - * EN_HYST (RW) - * - * hysteres enable - */ -#define PCFG_DCDC_MISC_EN_HYST_MASK (0x10000000UL) -#define PCFG_DCDC_MISC_EN_HYST_SHIFT (28U) -#define PCFG_DCDC_MISC_EN_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_HYST_SHIFT) & PCFG_DCDC_MISC_EN_HYST_MASK) -#define PCFG_DCDC_MISC_EN_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_HYST_MASK) >> PCFG_DCDC_MISC_EN_HYST_SHIFT) - -/* - * HYST_SIGN (RW) - * - * hysteres sign - */ -#define PCFG_DCDC_MISC_HYST_SIGN_MASK (0x2000000UL) -#define PCFG_DCDC_MISC_HYST_SIGN_SHIFT (25U) -#define PCFG_DCDC_MISC_HYST_SIGN_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_SIGN_SHIFT) & PCFG_DCDC_MISC_HYST_SIGN_MASK) -#define PCFG_DCDC_MISC_HYST_SIGN_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_SIGN_MASK) >> PCFG_DCDC_MISC_HYST_SIGN_SHIFT) - -/* - * HYST_THRS (RW) - * - * hysteres threshold - */ -#define PCFG_DCDC_MISC_HYST_THRS_MASK (0x1000000UL) -#define PCFG_DCDC_MISC_HYST_THRS_SHIFT (24U) -#define PCFG_DCDC_MISC_HYST_THRS_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_HYST_THRS_SHIFT) & PCFG_DCDC_MISC_HYST_THRS_MASK) -#define PCFG_DCDC_MISC_HYST_THRS_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_HYST_THRS_MASK) >> PCFG_DCDC_MISC_HYST_THRS_SHIFT) - -/* - * RC_SCALE (RW) - * - * Loop RC scale threshold - */ -#define PCFG_DCDC_MISC_RC_SCALE_MASK (0x100000UL) -#define PCFG_DCDC_MISC_RC_SCALE_SHIFT (20U) -#define PCFG_DCDC_MISC_RC_SCALE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_RC_SCALE_SHIFT) & PCFG_DCDC_MISC_RC_SCALE_MASK) -#define PCFG_DCDC_MISC_RC_SCALE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_RC_SCALE_MASK) >> PCFG_DCDC_MISC_RC_SCALE_SHIFT) - -/* - * DC_FF (RW) - * - * Loop feed forward number - */ -#define PCFG_DCDC_MISC_DC_FF_MASK (0x70000UL) -#define PCFG_DCDC_MISC_DC_FF_SHIFT (16U) -#define PCFG_DCDC_MISC_DC_FF_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DC_FF_SHIFT) & PCFG_DCDC_MISC_DC_FF_MASK) -#define PCFG_DCDC_MISC_DC_FF_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DC_FF_MASK) >> PCFG_DCDC_MISC_DC_FF_SHIFT) - -/* - * OL_THRE (RW) - * - * overload for threshold for lod power mode - */ -#define PCFG_DCDC_MISC_OL_THRE_MASK (0x300U) -#define PCFG_DCDC_MISC_OL_THRE_SHIFT (8U) -#define PCFG_DCDC_MISC_OL_THRE_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_THRE_SHIFT) & PCFG_DCDC_MISC_OL_THRE_MASK) -#define PCFG_DCDC_MISC_OL_THRE_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_THRE_MASK) >> PCFG_DCDC_MISC_OL_THRE_SHIFT) - -/* - * OL_HYST (RW) - * - * current hysteres range - * 0: 12.5mV - * 1: 25mV - */ -#define PCFG_DCDC_MISC_OL_HYST_MASK (0x10U) -#define PCFG_DCDC_MISC_OL_HYST_SHIFT (4U) -#define PCFG_DCDC_MISC_OL_HYST_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_OL_HYST_SHIFT) & PCFG_DCDC_MISC_OL_HYST_MASK) -#define PCFG_DCDC_MISC_OL_HYST_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_OL_HYST_MASK) >> PCFG_DCDC_MISC_OL_HYST_SHIFT) - -/* - * DELAY (RW) - * - * enable delay - * 0: delay disabled, - * 1: delay enabled - */ -#define PCFG_DCDC_MISC_DELAY_MASK (0x4U) -#define PCFG_DCDC_MISC_DELAY_SHIFT (2U) -#define PCFG_DCDC_MISC_DELAY_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_DELAY_SHIFT) & PCFG_DCDC_MISC_DELAY_MASK) -#define PCFG_DCDC_MISC_DELAY_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_DELAY_MASK) >> PCFG_DCDC_MISC_DELAY_SHIFT) - -/* - * CLK_SEL (RW) - * - * clock selection - * 0: select DCDC internal oscillator - * 1: select RC24M oscillator - */ -#define PCFG_DCDC_MISC_CLK_SEL_MASK (0x2U) -#define PCFG_DCDC_MISC_CLK_SEL_SHIFT (1U) -#define PCFG_DCDC_MISC_CLK_SEL_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_CLK_SEL_SHIFT) & PCFG_DCDC_MISC_CLK_SEL_MASK) -#define PCFG_DCDC_MISC_CLK_SEL_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_CLK_SEL_MASK) >> PCFG_DCDC_MISC_CLK_SEL_SHIFT) - -/* - * EN_STEP (RW) - * - * enable stepping in voltage change - * 0: stepping disabled, - * 1: steping enabled - */ -#define PCFG_DCDC_MISC_EN_STEP_MASK (0x1U) -#define PCFG_DCDC_MISC_EN_STEP_SHIFT (0U) -#define PCFG_DCDC_MISC_EN_STEP_SET(x) (((uint32_t)(x) << PCFG_DCDC_MISC_EN_STEP_SHIFT) & PCFG_DCDC_MISC_EN_STEP_MASK) -#define PCFG_DCDC_MISC_EN_STEP_GET(x) (((uint32_t)(x) & PCFG_DCDC_MISC_EN_STEP_MASK) >> PCFG_DCDC_MISC_EN_STEP_SHIFT) - -/* Bitfield definition for register: DCDC_DEBUG */ -/* - * UPDATE_TIME (RW) - * - * DCDC voltage change time in 24M clock cycles, default value is 1mS - */ -#define PCFG_DCDC_DEBUG_UPDATE_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT (0U) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) -#define PCFG_DCDC_DEBUG_UPDATE_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_DEBUG_UPDATE_TIME_MASK) >> PCFG_DCDC_DEBUG_UPDATE_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_START_TIME */ -/* - * START_TIME (RW) - * - * Start delay for DCDC to turn on, in 24M clock cycles, default value is 3mS - */ -#define PCFG_DCDC_START_TIME_START_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_START_TIME_START_TIME_SHIFT (0U) -#define PCFG_DCDC_START_TIME_START_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_START_TIME_START_TIME_SHIFT) & PCFG_DCDC_START_TIME_START_TIME_MASK) -#define PCFG_DCDC_START_TIME_START_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_START_TIME_START_TIME_MASK) >> PCFG_DCDC_START_TIME_START_TIME_SHIFT) - -/* Bitfield definition for register: DCDC_RESUME_TIME */ -/* - * RESUME_TIME (RW) - * - * Resume delay for DCDC to recover from low power mode, in 24M clock cycles, default value is 1.5mS - */ -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK (0xFFFFFUL) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT (0U) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(x) (((uint32_t)(x) << PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) -#define PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(x) (((uint32_t)(x) & PCFG_DCDC_RESUME_TIME_RESUME_TIME_MASK) >> PCFG_DCDC_RESUME_TIME_RESUME_TIME_SHIFT) - -/* Bitfield definition for register: POWER_TRAP */ -/* - * TRIGGERED (RW) - * - * Low power trap status, thit bit will set when power related low power flow triggered, write 1 to clear this flag. - * 0: low power trap is not triggered - * 1: low power trap triggered - */ -#define PCFG_POWER_TRAP_TRIGGERED_MASK (0x80000000UL) -#define PCFG_POWER_TRAP_TRIGGERED_SHIFT (31U) -#define PCFG_POWER_TRAP_TRIGGERED_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRIGGERED_SHIFT) & PCFG_POWER_TRAP_TRIGGERED_MASK) -#define PCFG_POWER_TRAP_TRIGGERED_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRIGGERED_MASK) >> PCFG_POWER_TRAP_TRIGGERED_SHIFT) - -/* - * RETENTION (RW) - * - * DCDC enter standby mode, which will reduce voltage for memory content retention - * 0: Shutdown DCDC - * 1: reduce DCDC voltage - */ -#define PCFG_POWER_TRAP_RETENTION_MASK (0x10000UL) -#define PCFG_POWER_TRAP_RETENTION_SHIFT (16U) -#define PCFG_POWER_TRAP_RETENTION_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_RETENTION_SHIFT) & PCFG_POWER_TRAP_RETENTION_MASK) -#define PCFG_POWER_TRAP_RETENTION_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_RETENTION_MASK) >> PCFG_POWER_TRAP_RETENTION_SHIFT) - -/* - * TRAP (RW) - * - * Enable trap of SOC power supply, trap is used to hold SOC in low power mode for DCDC to enter further low power mode, this bit will self-clear when power related low pwer flow triggered - * 0: trap not enabled, pmic side low power function disabled - * 1: trap enabled, STOP operation leads to PMIC low power flow if SOC is not retentioned. - */ -#define PCFG_POWER_TRAP_TRAP_MASK (0x1U) -#define PCFG_POWER_TRAP_TRAP_SHIFT (0U) -#define PCFG_POWER_TRAP_TRAP_SET(x) (((uint32_t)(x) << PCFG_POWER_TRAP_TRAP_SHIFT) & PCFG_POWER_TRAP_TRAP_MASK) -#define PCFG_POWER_TRAP_TRAP_GET(x) (((uint32_t)(x) & PCFG_POWER_TRAP_TRAP_MASK) >> PCFG_POWER_TRAP_TRAP_SHIFT) - -/* Bitfield definition for register: WAKE_CAUSE */ -/* - * CAUSE (RW) - * - * wake up cause, each bit represents one wake up source, write 1 to clear the register bit - * 0: wake up source is not active during last wakeup - * 1: wake up source is active furing last wakeup - * bit 0: pmic_enable - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit16: batt security interrupt - * bit17:batt gpio interrupt - * bit19:rtc interrupt - * bit31: pin wakeup - */ -#define PCFG_WAKE_CAUSE_CAUSE_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_CAUSE_CAUSE_SHIFT (0U) -#define PCFG_WAKE_CAUSE_CAUSE_SET(x) (((uint32_t)(x) << PCFG_WAKE_CAUSE_CAUSE_SHIFT) & PCFG_WAKE_CAUSE_CAUSE_MASK) -#define PCFG_WAKE_CAUSE_CAUSE_GET(x) (((uint32_t)(x) & PCFG_WAKE_CAUSE_CAUSE_MASK) >> PCFG_WAKE_CAUSE_CAUSE_SHIFT) - -/* Bitfield definition for register: WAKE_MASK */ -/* - * MASK (RW) - * - * mask for wake up sources, each bit represents one wakeup source - * 0: allow source to wake up system - * 1: disallow source to wakeup system - * bit 0: pmic_enable - * bit 7: UART interrupt - * bit 8: TMR interrupt - * bit 9: WDG interrupt - * bit10: GPIO in PMIC interrupt - * bit16: batt security interrupt - * bit17:batt gpio interrupt - * bit19:rtc interrupt - * bit31: pin wakeup - */ -#define PCFG_WAKE_MASK_MASK_MASK (0xFFFFFFFFUL) -#define PCFG_WAKE_MASK_MASK_SHIFT (0U) -#define PCFG_WAKE_MASK_MASK_SET(x) (((uint32_t)(x) << PCFG_WAKE_MASK_MASK_SHIFT) & PCFG_WAKE_MASK_MASK_MASK) -#define PCFG_WAKE_MASK_MASK_GET(x) (((uint32_t)(x) & PCFG_WAKE_MASK_MASK_MASK) >> PCFG_WAKE_MASK_MASK_SHIFT) - -/* Bitfield definition for register: SCG_CTRL */ -/* - * SCG (RW) - * - * control whether clock being gated during PMIC low power flow, 2 bits for each peripheral - * 00,01: reserved - * 10: clock is always off - * 11: clock is always on - * bit6-7:gpio - * bit8-9:ioc - * bit10-11: timer - * bit12-13:wdog - * bit14-15:uart - */ -#define PCFG_SCG_CTRL_SCG_MASK (0xFFFFFFFFUL) -#define PCFG_SCG_CTRL_SCG_SHIFT (0U) -#define PCFG_SCG_CTRL_SCG_SET(x) (((uint32_t)(x) << PCFG_SCG_CTRL_SCG_SHIFT) & PCFG_SCG_CTRL_SCG_MASK) -#define PCFG_SCG_CTRL_SCG_GET(x) (((uint32_t)(x) & PCFG_SCG_CTRL_SCG_MASK) >> PCFG_SCG_CTRL_SCG_SHIFT) - -/* Bitfield definition for register: RC24M */ -/* - * RC_TRIMMED (RW) - * - * RC24M trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: RC is not trimmed - * 1: RC is trimmed - */ -#define PCFG_RC24M_RC_TRIMMED_MASK (0x80000000UL) -#define PCFG_RC24M_RC_TRIMMED_SHIFT (31U) -#define PCFG_RC24M_RC_TRIMMED_SET(x) (((uint32_t)(x) << PCFG_RC24M_RC_TRIMMED_SHIFT) & PCFG_RC24M_RC_TRIMMED_MASK) -#define PCFG_RC24M_RC_TRIMMED_GET(x) (((uint32_t)(x) & PCFG_RC24M_RC_TRIMMED_MASK) >> PCFG_RC24M_RC_TRIMMED_SHIFT) - -/* - * TRIM_C (RW) - * - * Coarse trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_C_MASK (0x700U) -#define PCFG_RC24M_TRIM_C_SHIFT (8U) -#define PCFG_RC24M_TRIM_C_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_C_SHIFT) & PCFG_RC24M_TRIM_C_MASK) -#define PCFG_RC24M_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_C_MASK) >> PCFG_RC24M_TRIM_C_SHIFT) - -/* - * TRIM_F (RW) - * - * Fine trim for RC24M, bigger value means faster - */ -#define PCFG_RC24M_TRIM_F_MASK (0x1FU) -#define PCFG_RC24M_TRIM_F_SHIFT (0U) -#define PCFG_RC24M_TRIM_F_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRIM_F_SHIFT) & PCFG_RC24M_TRIM_F_MASK) -#define PCFG_RC24M_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRIM_F_MASK) >> PCFG_RC24M_TRIM_F_SHIFT) - -/* Bitfield definition for register: RC24M_TRACK */ -/* - * SEL24M (RW) - * - * Select track reference - * 0: select 32K as reference - * 1: select 24M XTAL as reference - */ -#define PCFG_RC24M_TRACK_SEL24M_MASK (0x10000UL) -#define PCFG_RC24M_TRACK_SEL24M_SHIFT (16U) -#define PCFG_RC24M_TRACK_SEL24M_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_SEL24M_SHIFT) & PCFG_RC24M_TRACK_SEL24M_MASK) -#define PCFG_RC24M_TRACK_SEL24M_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_SEL24M_MASK) >> PCFG_RC24M_TRACK_SEL24M_SHIFT) - -/* - * RETURN (RW) - * - * Retrun default value when XTAL loss - * 0: remain last tracking value - * 1: switch to default value - */ -#define PCFG_RC24M_TRACK_RETURN_MASK (0x10U) -#define PCFG_RC24M_TRACK_RETURN_SHIFT (4U) -#define PCFG_RC24M_TRACK_RETURN_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_RETURN_SHIFT) & PCFG_RC24M_TRACK_RETURN_MASK) -#define PCFG_RC24M_TRACK_RETURN_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_RETURN_MASK) >> PCFG_RC24M_TRACK_RETURN_SHIFT) - -/* - * TRACK (RW) - * - * track mode - * 0: RC24M free running - * 1: track RC24M to external XTAL - */ -#define PCFG_RC24M_TRACK_TRACK_MASK (0x1U) -#define PCFG_RC24M_TRACK_TRACK_SHIFT (0U) -#define PCFG_RC24M_TRACK_TRACK_SET(x) (((uint32_t)(x) << PCFG_RC24M_TRACK_TRACK_SHIFT) & PCFG_RC24M_TRACK_TRACK_MASK) -#define PCFG_RC24M_TRACK_TRACK_GET(x) (((uint32_t)(x) & PCFG_RC24M_TRACK_TRACK_MASK) >> PCFG_RC24M_TRACK_TRACK_SHIFT) - -/* Bitfield definition for register: TRACK_TARGET */ -/* - * PRE_DIV (RW) - * - * Divider for reference source - */ -#define PCFG_TRACK_TARGET_PRE_DIV_MASK (0xFFFF0000UL) -#define PCFG_TRACK_TARGET_PRE_DIV_SHIFT (16U) -#define PCFG_TRACK_TARGET_PRE_DIV_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_PRE_DIV_SHIFT) & PCFG_TRACK_TARGET_PRE_DIV_MASK) -#define PCFG_TRACK_TARGET_PRE_DIV_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_PRE_DIV_MASK) >> PCFG_TRACK_TARGET_PRE_DIV_SHIFT) - -/* - * TARGET (RW) - * - * Target frequency multiplier of divided source - */ -#define PCFG_TRACK_TARGET_TARGET_MASK (0xFFFFU) -#define PCFG_TRACK_TARGET_TARGET_SHIFT (0U) -#define PCFG_TRACK_TARGET_TARGET_SET(x) (((uint32_t)(x) << PCFG_TRACK_TARGET_TARGET_SHIFT) & PCFG_TRACK_TARGET_TARGET_MASK) -#define PCFG_TRACK_TARGET_TARGET_GET(x) (((uint32_t)(x) & PCFG_TRACK_TARGET_TARGET_MASK) >> PCFG_TRACK_TARGET_TARGET_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * SEL32K (RO) - * - * track is using XTAL32K - * 0: track is not using XTAL32K - * 1: track is using XTAL32K - */ -#define PCFG_STATUS_SEL32K_MASK (0x100000UL) -#define PCFG_STATUS_SEL32K_SHIFT (20U) -#define PCFG_STATUS_SEL32K_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL32K_MASK) >> PCFG_STATUS_SEL32K_SHIFT) - -/* - * SEL24M (RO) - * - * track is using XTAL24M - * 0: track is not using XTAL24M - * 1: track is using XTAL24M - */ -#define PCFG_STATUS_SEL24M_MASK (0x10000UL) -#define PCFG_STATUS_SEL24M_SHIFT (16U) -#define PCFG_STATUS_SEL24M_GET(x) (((uint32_t)(x) & PCFG_STATUS_SEL24M_MASK) >> PCFG_STATUS_SEL24M_SHIFT) - -/* - * EN_TRIM (RO) - * - * default value takes effect - * 0: default value is invalid - * 1: default value is valid - */ -#define PCFG_STATUS_EN_TRIM_MASK (0x8000U) -#define PCFG_STATUS_EN_TRIM_SHIFT (15U) -#define PCFG_STATUS_EN_TRIM_GET(x) (((uint32_t)(x) & PCFG_STATUS_EN_TRIM_MASK) >> PCFG_STATUS_EN_TRIM_SHIFT) - -/* - * TRIM_C (RO) - * - * default coarse trim value - */ -#define PCFG_STATUS_TRIM_C_MASK (0x700U) -#define PCFG_STATUS_TRIM_C_SHIFT (8U) -#define PCFG_STATUS_TRIM_C_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_C_MASK) >> PCFG_STATUS_TRIM_C_SHIFT) - -/* - * TRIM_F (RO) - * - * default fine trim value - */ -#define PCFG_STATUS_TRIM_F_MASK (0x1FU) -#define PCFG_STATUS_TRIM_F_SHIFT (0U) -#define PCFG_STATUS_TRIM_F_GET(x) (((uint32_t)(x) & PCFG_STATUS_TRIM_F_MASK) >> PCFG_STATUS_TRIM_F_SHIFT) - - - - -#endif /* HPM_PCFG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pdgo_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pdgo_regs.h deleted file mode 100644 index 5f4c0feeb19..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pdgo_regs.h +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDGO_H -#define HPM_PDGO_H - -typedef struct { - __W uint32_t DGO_TURNOFF; /* 0x0: trunoff control */ - __RW uint32_t DGO_RC32K_CFG; /* 0x4: RC32K CLOCK */ - __R uint8_t RESERVED0[1528]; /* 0x8 - 0x5FF: Reserved */ - __RW uint32_t DGO_GPR00; /* 0x600: Generic control 0 */ - __RW uint32_t DGO_GPR01; /* 0x604: Generic control 1 */ - __RW uint32_t DGO_GPR02; /* 0x608: Generic control 2 */ - __RW uint32_t DGO_GPR03; /* 0x60C: Generic control 3 */ - __R uint8_t RESERVED1[240]; /* 0x610 - 0x6FF: Reserved */ - __RW uint32_t DGO_CTR0; /* 0x700: control register 0 */ - __RW uint32_t DGO_CTR1; /* 0x704: control register 1 */ - __RW uint32_t DGO_CTR2; /* 0x708: control register 2 */ - __RW uint32_t DGO_CTR3; /* 0x70C: control register 3 */ - __RW uint32_t DGO_CTR4; /* 0x710: control register 4 */ -} PDGO_Type; - - -/* Bitfield definition for register: DGO_TURNOFF */ -/* - * COUNTER (WO) - * - * trunoff counter, counter stops when it counts down to 0, the trunoff occurs when the counter value is 1. - */ -#define PDGO_DGO_TURNOFF_COUNTER_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_TURNOFF_COUNTER_SHIFT (0U) -#define PDGO_DGO_TURNOFF_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_TURNOFF_COUNTER_SHIFT) & PDGO_DGO_TURNOFF_COUNTER_MASK) -#define PDGO_DGO_TURNOFF_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_TURNOFF_COUNTER_MASK) >> PDGO_DGO_TURNOFF_COUNTER_SHIFT) - -/* Bitfield definition for register: DGO_RC32K_CFG */ -/* - * IRC_TRIMMED (RW) - * - * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value - * 0: irc is not trimmed - * 1: irc is trimmed - */ -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL) -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT (31U) -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) -#define PDGO_DGO_RC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_IRC_TRIMMED_MASK) >> PDGO_DGO_RC32K_CFG_IRC_TRIMMED_SHIFT) - -/* - * CAPEX7_TRIM (RW) - * - * IRC32K bit 7 - */ -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL) -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT (23U) -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) -#define PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX7_TRIM_SHIFT) - -/* - * CAPEX6_TRIM (RW) - * - * IRC32K bit 6 - */ -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL) -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT (22U) -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) -#define PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAPEX6_TRIM_SHIFT) - -/* - * CAP_TRIM (RW) - * - * capacitor trim bits - */ -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK (0x1FFU) -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT (0U) -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) -#define PDGO_DGO_RC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & PDGO_DGO_RC32K_CFG_CAP_TRIM_MASK) >> PDGO_DGO_RC32K_CFG_CAP_TRIM_SHIFT) - -/* Bitfield definition for register: DGO_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR00_GPR_SHIFT (0U) -#define PDGO_DGO_GPR00_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR00_GPR_SHIFT) & PDGO_DGO_GPR00_GPR_MASK) -#define PDGO_DGO_GPR00_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR00_GPR_MASK) >> PDGO_DGO_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: DGO_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR01_GPR_SHIFT (0U) -#define PDGO_DGO_GPR01_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR01_GPR_SHIFT) & PDGO_DGO_GPR01_GPR_MASK) -#define PDGO_DGO_GPR01_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR01_GPR_MASK) >> PDGO_DGO_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: DGO_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR02_GPR_SHIFT (0U) -#define PDGO_DGO_GPR02_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR02_GPR_SHIFT) & PDGO_DGO_GPR02_GPR_MASK) -#define PDGO_DGO_GPR02_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR02_GPR_MASK) >> PDGO_DGO_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: DGO_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PDGO_DGO_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_GPR03_GPR_SHIFT (0U) -#define PDGO_DGO_GPR03_GPR_SET(x) (((uint32_t)(x) << PDGO_DGO_GPR03_GPR_SHIFT) & PDGO_DGO_GPR03_GPR_MASK) -#define PDGO_DGO_GPR03_GPR_GET(x) (((uint32_t)(x) & PDGO_DGO_GPR03_GPR_MASK) >> PDGO_DGO_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: DGO_CTR0 */ -/* - * RETENTION (RW) - * - * dgo register status retenion - */ -#define PDGO_DGO_CTR0_RETENTION_MASK (0x10000UL) -#define PDGO_DGO_CTR0_RETENTION_SHIFT (16U) -#define PDGO_DGO_CTR0_RETENTION_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR0_RETENTION_SHIFT) & PDGO_DGO_CTR0_RETENTION_MASK) -#define PDGO_DGO_CTR0_RETENTION_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR0_RETENTION_MASK) >> PDGO_DGO_CTR0_RETENTION_SHIFT) - -/* Bitfield definition for register: DGO_CTR1 */ -/* - * AOTO_SYS_WAKEUP (RW) - * - * software wakeup： 0 : wakeup once； 1：auto wakeup Continuously - */ -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK (0x80000000UL) -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT (31U) -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) -#define PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_MASK) >> PDGO_DGO_CTR1_AOTO_SYS_WAKEUP_SHIFT) - -/* - * WAKEUP_EN (RW) - * - * permit wakeup pin or software wakeup - */ -#define PDGO_DGO_CTR1_WAKEUP_EN_MASK (0x10000UL) -#define PDGO_DGO_CTR1_WAKEUP_EN_SHIFT (16U) -#define PDGO_DGO_CTR1_WAKEUP_EN_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) -#define PDGO_DGO_CTR1_WAKEUP_EN_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_WAKEUP_EN_MASK) >> PDGO_DGO_CTR1_WAKEUP_EN_SHIFT) - -/* - * PIN_WAKEUP_STATUS (RO) - * - * wakeup pin status - */ -#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK (0x1U) -#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT (0U) -#define PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_MASK) >> PDGO_DGO_CTR1_PIN_WAKEUP_STATUS_SHIFT) - -/* Bitfield definition for register: DGO_CTR2 */ -/* - * RESETN_PULLUP_DISABLE (RW) - * - * resetn pin pull up disable - */ -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK (0x1000000UL) -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT (24U) -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) -#define PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_MASK) >> PDGO_DGO_CTR2_RESETN_PULLUP_DISABLE_SHIFT) - -/* - * WAKEUP_PULLDN_DISABLE (RW) - * - * wakeup pin pull down disable - */ -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK (0x10000UL) -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT (16U) -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) -#define PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_MASK) >> PDGO_DGO_CTR2_WAKEUP_PULLDN_DISABLE_SHIFT) - -/* Bitfield definition for register: DGO_CTR3 */ -/* - * WAKEUP_COUNTER (RW) - * - * software wakeup counter - */ -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK (0xFFFFFFFFUL) -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT (0U) -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) -#define PDGO_DGO_CTR3_WAKEUP_COUNTER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR3_WAKEUP_COUNTER_MASK) >> PDGO_DGO_CTR3_WAKEUP_COUNTER_SHIFT) - -/* Bitfield definition for register: DGO_CTR4 */ -/* - * BANDGAP_LESS_POWER (RW) - * - * Banggap work in power save mode, banggap function normally - * 0: banggap works in high performance mode - * 1: banggap works in power saving mode - */ -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK (0x2U) -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT (1U) -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) -#define PDGO_DGO_CTR4_BANDGAP_LESS_POWER_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LESS_POWER_MASK) >> PDGO_DGO_CTR4_BANDGAP_LESS_POWER_SHIFT) - -/* - * BANDGAP_LP_MODE (RW) - * - * Banggap work in low power mode, banggap function limited - * 0: banggap works in normal mode - * 1: banggap works in low power mode - */ -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK (0x1U) -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT (0U) -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_SET(x) (((uint32_t)(x) << PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) -#define PDGO_DGO_CTR4_BANDGAP_LP_MODE_GET(x) (((uint32_t)(x) & PDGO_DGO_CTR4_BANDGAP_LP_MODE_MASK) >> PDGO_DGO_CTR4_BANDGAP_LP_MODE_SHIFT) - - - - -#endif /* HPM_PDGO_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pdm_regs.h deleted file mode 100644 index 94b550e0ee2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pdm_regs.h +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PDM_H -#define HPM_PDM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: Control Register */ - __RW uint32_t CH_CTRL; /* 0x4: Channel Control Register */ - __W uint32_t ST; /* 0x8: Status Register */ - __RW uint32_t CH_CFG; /* 0xC: Channel Configuration Register */ - __RW uint32_t CIC_CFG; /* 0x10: CIC configuration register */ - __RW uint32_t CTRL_INBUF; /* 0x14: In Buf Control Register */ - __RW uint32_t CTRL_FILT0; /* 0x18: Filter 0 Control Register */ - __RW uint32_t CTRL_FILT1; /* 0x1C: Filter 1 Control Register */ - __RW uint32_t RUN; /* 0x20: Run Register */ - __RW uint32_t MEMADDR; /* 0x24: Memory Access Address */ - __RW uint32_t MEMDATA; /* 0x28: Memory Access Data */ - __RW uint32_t HPF_MA; /* 0x2C: HPF A Coef Register */ - __RW uint32_t HPF_B; /* 0x30: HPF B Coef Register */ -} PDM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module. Self-clear. - */ -#define PDM_CTRL_SFTRST_MASK (0x80000000UL) -#define PDM_CTRL_SFTRST_SHIFT (31U) -#define PDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PDM_CTRL_SFTRST_SHIFT) & PDM_CTRL_SFTRST_MASK) -#define PDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PDM_CTRL_SFTRST_MASK) >> PDM_CTRL_SFTRST_SHIFT) - -/* - * SOF_FEDGE (RW) - * - * asserted if the falling edge of the ref fclk from DAO is the start of a new frame. This is used to to align DAO feedback signal. - */ -#define PDM_CTRL_SOF_FEDGE_MASK (0x800000UL) -#define PDM_CTRL_SOF_FEDGE_SHIFT (23U) -#define PDM_CTRL_SOF_FEDGE_SET(x) (((uint32_t)(x) << PDM_CTRL_SOF_FEDGE_SHIFT) & PDM_CTRL_SOF_FEDGE_MASK) -#define PDM_CTRL_SOF_FEDGE_GET(x) (((uint32_t)(x) & PDM_CTRL_SOF_FEDGE_MASK) >> PDM_CTRL_SOF_FEDGE_SHIFT) - -/* - * USE_COEF_RAM (RW) - * - * Asserted to use Coef RAM instead of Coef ROM - */ -#define PDM_CTRL_USE_COEF_RAM_MASK (0x100000UL) -#define PDM_CTRL_USE_COEF_RAM_SHIFT (20U) -#define PDM_CTRL_USE_COEF_RAM_SET(x) (((uint32_t)(x) << PDM_CTRL_USE_COEF_RAM_SHIFT) & PDM_CTRL_USE_COEF_RAM_MASK) -#define PDM_CTRL_USE_COEF_RAM_GET(x) (((uint32_t)(x) & PDM_CTRL_USE_COEF_RAM_MASK) >> PDM_CTRL_USE_COEF_RAM_SHIFT) - -/* - * FILT_CRX_ERR_IE (RW) - * - * data accessed out of boundary error interruput enable. The error happens when the module cannot calculate the enough number of data in time. - */ -#define PDM_CTRL_FILT_CRX_ERR_IE_MASK (0x80000UL) -#define PDM_CTRL_FILT_CRX_ERR_IE_SHIFT (19U) -#define PDM_CTRL_FILT_CRX_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) -#define PDM_CTRL_FILT_CRX_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT_CRX_ERR_IE_MASK) >> PDM_CTRL_FILT_CRX_ERR_IE_SHIFT) - -/* - * OFIFO_OVFL_ERR_IE (RW) - * - * output fifo overflow error interrupt enable - */ -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK (0x40000UL) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT (18U) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) -#define PDM_CTRL_OFIFO_OVFL_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_OFIFO_OVFL_ERR_IE_MASK) >> PDM_CTRL_OFIFO_OVFL_ERR_IE_SHIFT) - -/* - * CIC_OVLD_ERR_IE (RW) - * - * CIC overload error interrupt enable - */ -#define PDM_CTRL_CIC_OVLD_ERR_IE_MASK (0x20000UL) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT (17U) -#define PDM_CTRL_CIC_OVLD_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) -#define PDM_CTRL_CIC_OVLD_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_OVLD_ERR_IE_MASK) >> PDM_CTRL_CIC_OVLD_ERR_IE_SHIFT) - -/* - * CIC_SAT_ERR_IE (RW) - * - * Error interrupt enable - * This bit controls the generation of an interrupt when an error condition (CIC saturation) occurs. - * 0: Error interrupt is masked - * 1: Error interrupt is enabled - */ -#define PDM_CTRL_CIC_SAT_ERR_IE_MASK (0x10000UL) -#define PDM_CTRL_CIC_SAT_ERR_IE_SHIFT (16U) -#define PDM_CTRL_CIC_SAT_ERR_IE_SET(x) (((uint32_t)(x) << PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) -#define PDM_CTRL_CIC_SAT_ERR_IE_GET(x) (((uint32_t)(x) & PDM_CTRL_CIC_SAT_ERR_IE_MASK) >> PDM_CTRL_CIC_SAT_ERR_IE_SHIFT) - -/* - * DEC_AFT_CIC (RW) - * - * decimation rate after CIC. Now it is forced to be 3. - */ -#define PDM_CTRL_DEC_AFT_CIC_MASK (0xF000U) -#define PDM_CTRL_DEC_AFT_CIC_SHIFT (12U) -#define PDM_CTRL_DEC_AFT_CIC_SET(x) (((uint32_t)(x) << PDM_CTRL_DEC_AFT_CIC_SHIFT) & PDM_CTRL_DEC_AFT_CIC_MASK) -#define PDM_CTRL_DEC_AFT_CIC_GET(x) (((uint32_t)(x) & PDM_CTRL_DEC_AFT_CIC_MASK) >> PDM_CTRL_DEC_AFT_CIC_SHIFT) - -/* - * CAPT_DLY (RW) - * - * Capture cycle delay>=0, should be less than PDM_CLK_HFDIV - */ -#define PDM_CTRL_CAPT_DLY_MASK (0x780U) -#define PDM_CTRL_CAPT_DLY_SHIFT (7U) -#define PDM_CTRL_CAPT_DLY_SET(x) (((uint32_t)(x) << PDM_CTRL_CAPT_DLY_SHIFT) & PDM_CTRL_CAPT_DLY_MASK) -#define PDM_CTRL_CAPT_DLY_GET(x) (((uint32_t)(x) & PDM_CTRL_CAPT_DLY_MASK) >> PDM_CTRL_CAPT_DLY_SHIFT) - -/* - * PDM_CLK_HFDIV (RW) - * - * The clock divider will work at least 4. - * 0: div-by-2, - * 1: div-by-4 - * . . . - * n: div-by-2*(n+1) - */ -#define PDM_CTRL_PDM_CLK_HFDIV_MASK (0x78U) -#define PDM_CTRL_PDM_CLK_HFDIV_SHIFT (3U) -#define PDM_CTRL_PDM_CLK_HFDIV_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_HFDIV_SHIFT) & PDM_CTRL_PDM_CLK_HFDIV_MASK) -#define PDM_CTRL_PDM_CLK_HFDIV_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_HFDIV_MASK) >> PDM_CTRL_PDM_CLK_HFDIV_SHIFT) - -/* - * PDM_CLK_DIV_BYPASS (RW) - * - * asserted to bypass the pdm clock divider - */ -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK (0x4U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT (2U) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) -#define PDM_CTRL_PDM_CLK_DIV_BYPASS_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_DIV_BYPASS_MASK) >> PDM_CTRL_PDM_CLK_DIV_BYPASS_SHIFT) - -/* - * PDM_CLK_OE (RW) - * - * pdm_clk_output_en - */ -#define PDM_CTRL_PDM_CLK_OE_MASK (0x2U) -#define PDM_CTRL_PDM_CLK_OE_SHIFT (1U) -#define PDM_CTRL_PDM_CLK_OE_SET(x) (((uint32_t)(x) << PDM_CTRL_PDM_CLK_OE_SHIFT) & PDM_CTRL_PDM_CLK_OE_MASK) -#define PDM_CTRL_PDM_CLK_OE_GET(x) (((uint32_t)(x) & PDM_CTRL_PDM_CLK_OE_MASK) >> PDM_CTRL_PDM_CLK_OE_SHIFT) - -/* - * HPF_EN (RW) - * - * pdm high pass filter enable. This order-1 HPF only applies to the PDM mic data. - */ -#define PDM_CTRL_HPF_EN_MASK (0x1U) -#define PDM_CTRL_HPF_EN_SHIFT (0U) -#define PDM_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << PDM_CTRL_HPF_EN_SHIFT) & PDM_CTRL_HPF_EN_MASK) -#define PDM_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & PDM_CTRL_HPF_EN_MASK) >> PDM_CTRL_HPF_EN_SHIFT) - -/* Bitfield definition for register: CH_CTRL */ -/* - * CH_POL (RW) - * - * Asserted to select PDM_CLK high level captured, otherwise to select PDM_CLK low level captured. - */ -#define PDM_CH_CTRL_CH_POL_MASK (0xFF0000UL) -#define PDM_CH_CTRL_CH_POL_SHIFT (16U) -#define PDM_CH_CTRL_CH_POL_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_POL_SHIFT) & PDM_CH_CTRL_CH_POL_MASK) -#define PDM_CH_CTRL_CH_POL_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_POL_MASK) >> PDM_CH_CTRL_CH_POL_SHIFT) - -/* - * CH_EN (RW) - * - * Asserted to enable the channel. - * Ch8 & 9 are refs. - * Ch0-7 are pdm mics. - */ -#define PDM_CH_CTRL_CH_EN_MASK (0x3FFU) -#define PDM_CH_CTRL_CH_EN_SHIFT (0U) -#define PDM_CH_CTRL_CH_EN_SET(x) (((uint32_t)(x) << PDM_CH_CTRL_CH_EN_SHIFT) & PDM_CH_CTRL_CH_EN_MASK) -#define PDM_CH_CTRL_CH_EN_GET(x) (((uint32_t)(x) & PDM_CH_CTRL_CH_EN_MASK) >> PDM_CH_CTRL_CH_EN_SHIFT) - -/* Bitfield definition for register: ST */ -/* - * FILT_CRX_ERR (W1C) - * - * data accessed out of boundary error - */ -#define PDM_ST_FILT_CRX_ERR_MASK (0x8U) -#define PDM_ST_FILT_CRX_ERR_SHIFT (3U) -#define PDM_ST_FILT_CRX_ERR_SET(x) (((uint32_t)(x) << PDM_ST_FILT_CRX_ERR_SHIFT) & PDM_ST_FILT_CRX_ERR_MASK) -#define PDM_ST_FILT_CRX_ERR_GET(x) (((uint32_t)(x) & PDM_ST_FILT_CRX_ERR_MASK) >> PDM_ST_FILT_CRX_ERR_SHIFT) - -/* - * OFIFO_OVFL_ERR (W1C) - * - * output fifo overflow error. The reason may be sampling frequency mismatch, either fast or slow. - */ -#define PDM_ST_OFIFO_OVFL_ERR_MASK (0x4U) -#define PDM_ST_OFIFO_OVFL_ERR_SHIFT (2U) -#define PDM_ST_OFIFO_OVFL_ERR_SET(x) (((uint32_t)(x) << PDM_ST_OFIFO_OVFL_ERR_SHIFT) & PDM_ST_OFIFO_OVFL_ERR_MASK) -#define PDM_ST_OFIFO_OVFL_ERR_GET(x) (((uint32_t)(x) & PDM_ST_OFIFO_OVFL_ERR_MASK) >> PDM_ST_OFIFO_OVFL_ERR_SHIFT) - -/* - * CIC_OVLD_ERR (W1C) - * - * CIC overload error. write 1 clear - */ -#define PDM_ST_CIC_OVLD_ERR_MASK (0x2U) -#define PDM_ST_CIC_OVLD_ERR_SHIFT (1U) -#define PDM_ST_CIC_OVLD_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_OVLD_ERR_SHIFT) & PDM_ST_CIC_OVLD_ERR_MASK) -#define PDM_ST_CIC_OVLD_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_OVLD_ERR_MASK) >> PDM_ST_CIC_OVLD_ERR_SHIFT) - -/* - * CIC_SAT_ERR (W1C) - * - * CIC saturation. Write 1 clear - */ -#define PDM_ST_CIC_SAT_ERR_MASK (0x1U) -#define PDM_ST_CIC_SAT_ERR_SHIFT (0U) -#define PDM_ST_CIC_SAT_ERR_SET(x) (((uint32_t)(x) << PDM_ST_CIC_SAT_ERR_SHIFT) & PDM_ST_CIC_SAT_ERR_MASK) -#define PDM_ST_CIC_SAT_ERR_GET(x) (((uint32_t)(x) & PDM_ST_CIC_SAT_ERR_MASK) >> PDM_ST_CIC_SAT_ERR_SHIFT) - -/* Bitfield definition for register: CH_CFG */ -/* - * CH9_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH9_TYPE_MASK (0xC0000UL) -#define PDM_CH_CFG_CH9_TYPE_SHIFT (18U) -#define PDM_CH_CFG_CH9_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH9_TYPE_SHIFT) & PDM_CH_CFG_CH9_TYPE_MASK) -#define PDM_CH_CFG_CH9_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH9_TYPE_MASK) >> PDM_CH_CFG_CH9_TYPE_SHIFT) - -/* - * CH8_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH8_TYPE_MASK (0x30000UL) -#define PDM_CH_CFG_CH8_TYPE_SHIFT (16U) -#define PDM_CH_CFG_CH8_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH8_TYPE_SHIFT) & PDM_CH_CFG_CH8_TYPE_MASK) -#define PDM_CH_CFG_CH8_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH8_TYPE_MASK) >> PDM_CH_CFG_CH8_TYPE_SHIFT) - -/* - * CH7_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH7_TYPE_MASK (0xC000U) -#define PDM_CH_CFG_CH7_TYPE_SHIFT (14U) -#define PDM_CH_CFG_CH7_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH7_TYPE_SHIFT) & PDM_CH_CFG_CH7_TYPE_MASK) -#define PDM_CH_CFG_CH7_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH7_TYPE_MASK) >> PDM_CH_CFG_CH7_TYPE_SHIFT) - -/* - * CH6_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH6_TYPE_MASK (0x3000U) -#define PDM_CH_CFG_CH6_TYPE_SHIFT (12U) -#define PDM_CH_CFG_CH6_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH6_TYPE_SHIFT) & PDM_CH_CFG_CH6_TYPE_MASK) -#define PDM_CH_CFG_CH6_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH6_TYPE_MASK) >> PDM_CH_CFG_CH6_TYPE_SHIFT) - -/* - * CH5_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH5_TYPE_MASK (0xC00U) -#define PDM_CH_CFG_CH5_TYPE_SHIFT (10U) -#define PDM_CH_CFG_CH5_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH5_TYPE_SHIFT) & PDM_CH_CFG_CH5_TYPE_MASK) -#define PDM_CH_CFG_CH5_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH5_TYPE_MASK) >> PDM_CH_CFG_CH5_TYPE_SHIFT) - -/* - * CH4_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH4_TYPE_MASK (0x300U) -#define PDM_CH_CFG_CH4_TYPE_SHIFT (8U) -#define PDM_CH_CFG_CH4_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH4_TYPE_SHIFT) & PDM_CH_CFG_CH4_TYPE_MASK) -#define PDM_CH_CFG_CH4_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH4_TYPE_MASK) >> PDM_CH_CFG_CH4_TYPE_SHIFT) - -/* - * CH3_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH3_TYPE_MASK (0xC0U) -#define PDM_CH_CFG_CH3_TYPE_SHIFT (6U) -#define PDM_CH_CFG_CH3_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH3_TYPE_SHIFT) & PDM_CH_CFG_CH3_TYPE_MASK) -#define PDM_CH_CFG_CH3_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH3_TYPE_MASK) >> PDM_CH_CFG_CH3_TYPE_SHIFT) - -/* - * CH2_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH2_TYPE_MASK (0x30U) -#define PDM_CH_CFG_CH2_TYPE_SHIFT (4U) -#define PDM_CH_CFG_CH2_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH2_TYPE_SHIFT) & PDM_CH_CFG_CH2_TYPE_MASK) -#define PDM_CH_CFG_CH2_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH2_TYPE_MASK) >> PDM_CH_CFG_CH2_TYPE_SHIFT) - -/* - * CH1_TYPE (RW) - * - */ -#define PDM_CH_CFG_CH1_TYPE_MASK (0xCU) -#define PDM_CH_CFG_CH1_TYPE_SHIFT (2U) -#define PDM_CH_CFG_CH1_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH1_TYPE_SHIFT) & PDM_CH_CFG_CH1_TYPE_MASK) -#define PDM_CH_CFG_CH1_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH1_TYPE_MASK) >> PDM_CH_CFG_CH1_TYPE_SHIFT) - -/* - * CH0_TYPE (RW) - * - * Type of Channel 0 - * 2'b00: dec-by-3 wiith filter type0 (CIC Compenstation+norm filter) - * 2'b01: dec-by-3 with filter type 1 (No CIC compenstation, only norm filter) - */ -#define PDM_CH_CFG_CH0_TYPE_MASK (0x3U) -#define PDM_CH_CFG_CH0_TYPE_SHIFT (0U) -#define PDM_CH_CFG_CH0_TYPE_SET(x) (((uint32_t)(x) << PDM_CH_CFG_CH0_TYPE_SHIFT) & PDM_CH_CFG_CH0_TYPE_MASK) -#define PDM_CH_CFG_CH0_TYPE_GET(x) (((uint32_t)(x) & PDM_CH_CFG_CH0_TYPE_MASK) >> PDM_CH_CFG_CH0_TYPE_SHIFT) - -/* Bitfield definition for register: CIC_CFG */ -/* - * POST_SCALE (RW) - * - * the shift value after CIC results. - */ -#define PDM_CIC_CFG_POST_SCALE_MASK (0xFC00U) -#define PDM_CIC_CFG_POST_SCALE_SHIFT (10U) -#define PDM_CIC_CFG_POST_SCALE_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_POST_SCALE_SHIFT) & PDM_CIC_CFG_POST_SCALE_MASK) -#define PDM_CIC_CFG_POST_SCALE_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_POST_SCALE_MASK) >> PDM_CIC_CFG_POST_SCALE_SHIFT) - -/* - * SGD (RW) - * - * Sigma_delta_order[1:0] - * 2'b00: 7 - * 2'b01: 6 - * 2'b10: 5 - * Others: unused - */ -#define PDM_CIC_CFG_SGD_MASK (0x300U) -#define PDM_CIC_CFG_SGD_SHIFT (8U) -#define PDM_CIC_CFG_SGD_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_SGD_SHIFT) & PDM_CIC_CFG_SGD_MASK) -#define PDM_CIC_CFG_SGD_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_SGD_MASK) >> PDM_CIC_CFG_SGD_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation factor - */ -#define PDM_CIC_CFG_CIC_DEC_RATIO_MASK (0xFFU) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT (0U) -#define PDM_CIC_CFG_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) -#define PDM_CIC_CFG_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & PDM_CIC_CFG_CIC_DEC_RATIO_MASK) >> PDM_CIC_CFG_CIC_DEC_RATIO_SHIFT) - -/* Bitfield definition for register: CTRL_INBUF */ -/* - * MAX_PTR (RW) - * - * The buf size-1 for each channel - */ -#define PDM_CTRL_INBUF_MAX_PTR_MASK (0x3FC00000UL) -#define PDM_CTRL_INBUF_MAX_PTR_SHIFT (22U) -#define PDM_CTRL_INBUF_MAX_PTR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_MAX_PTR_SHIFT) & PDM_CTRL_INBUF_MAX_PTR_MASK) -#define PDM_CTRL_INBUF_MAX_PTR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_MAX_PTR_MASK) >> PDM_CTRL_INBUF_MAX_PTR_SHIFT) - -/* - * PITCH (RW) - * - * The spacing between starting address of adjacent channels - */ -#define PDM_CTRL_INBUF_PITCH_MASK (0x3FF800UL) -#define PDM_CTRL_INBUF_PITCH_SHIFT (11U) -#define PDM_CTRL_INBUF_PITCH_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_PITCH_SHIFT) & PDM_CTRL_INBUF_PITCH_MASK) -#define PDM_CTRL_INBUF_PITCH_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_PITCH_MASK) >> PDM_CTRL_INBUF_PITCH_SHIFT) - -/* - * START_ADDR (RW) - * - * The starting address of channel 0 in filter data buffer - */ -#define PDM_CTRL_INBUF_START_ADDR_MASK (0x7FFU) -#define PDM_CTRL_INBUF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_INBUF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_INBUF_START_ADDR_SHIFT) & PDM_CTRL_INBUF_START_ADDR_MASK) -#define PDM_CTRL_INBUF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_INBUF_START_ADDR_MASK) >> PDM_CTRL_INBUF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT0 */ -/* - * COEF_LEN_M0 (RW) - * - * Coef length of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_LEN_M0_MASK (0xFF00U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT (8U) -#define PDM_CTRL_FILT0_COEF_LEN_M0_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) -#define PDM_CTRL_FILT0_COEF_LEN_M0_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_LEN_M0_MASK) >> PDM_CTRL_FILT0_COEF_LEN_M0_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b00 in coef memory - */ -#define PDM_CTRL_FILT0_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT0_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT0_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT0_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT0_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: CTRL_FILT1 */ -/* - * COEF_LEN_M1 (RW) - * - * Coef length of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_LEN_M1_MASK (0xFF00U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT (8U) -#define PDM_CTRL_FILT1_COEF_LEN_M1_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) -#define PDM_CTRL_FILT1_COEF_LEN_M1_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_LEN_M1_MASK) >> PDM_CTRL_FILT1_COEF_LEN_M1_SHIFT) - -/* - * COEF_START_ADDR (RW) - * - * Starting address of Coef of filter type 2'b01 in coef memory - */ -#define PDM_CTRL_FILT1_COEF_START_ADDR_MASK (0xFFU) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT (0U) -#define PDM_CTRL_FILT1_COEF_START_ADDR_SET(x) (((uint32_t)(x) << PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) -#define PDM_CTRL_FILT1_COEF_START_ADDR_GET(x) (((uint32_t)(x) & PDM_CTRL_FILT1_COEF_START_ADDR_MASK) >> PDM_CTRL_FILT1_COEF_START_ADDR_SHIFT) - -/* Bitfield definition for register: RUN */ -/* - * PDM_EN (RW) - * - * Asserted to enable the module - */ -#define PDM_RUN_PDM_EN_MASK (0x1U) -#define PDM_RUN_PDM_EN_SHIFT (0U) -#define PDM_RUN_PDM_EN_SET(x) (((uint32_t)(x) << PDM_RUN_PDM_EN_SHIFT) & PDM_RUN_PDM_EN_MASK) -#define PDM_RUN_PDM_EN_GET(x) (((uint32_t)(x) & PDM_RUN_PDM_EN_MASK) >> PDM_RUN_PDM_EN_SHIFT) - -/* Bitfield definition for register: MEMADDR */ -/* - * ADDR (RW) - * - * 0--0x0FFFFFFF: COEF_RAM - * 0x10000000--0x1FFFFFFF: DATA_RAM - */ -#define PDM_MEMADDR_ADDR_MASK (0xFFFFFFFFUL) -#define PDM_MEMADDR_ADDR_SHIFT (0U) -#define PDM_MEMADDR_ADDR_SET(x) (((uint32_t)(x) << PDM_MEMADDR_ADDR_SHIFT) & PDM_MEMADDR_ADDR_MASK) -#define PDM_MEMADDR_ADDR_GET(x) (((uint32_t)(x) & PDM_MEMADDR_ADDR_MASK) >> PDM_MEMADDR_ADDR_SHIFT) - -/* Bitfield definition for register: MEMDATA */ -/* - * DATA (RW) - * - * The data write-to/read-from buffer - */ -#define PDM_MEMDATA_DATA_MASK (0xFFFFFFFFUL) -#define PDM_MEMDATA_DATA_SHIFT (0U) -#define PDM_MEMDATA_DATA_SET(x) (((uint32_t)(x) << PDM_MEMDATA_DATA_SHIFT) & PDM_MEMDATA_DATA_MASK) -#define PDM_MEMDATA_DATA_GET(x) (((uint32_t)(x) & PDM_MEMDATA_DATA_MASK) >> PDM_MEMDATA_DATA_SHIFT) - -/* Bitfield definition for register: HPF_MA */ -/* - * COEF (RW) - * - * Composite value of coef A of the Order-1 HPF - */ -#define PDM_HPF_MA_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_MA_COEF_SHIFT (0U) -#define PDM_HPF_MA_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_MA_COEF_SHIFT) & PDM_HPF_MA_COEF_MASK) -#define PDM_HPF_MA_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_MA_COEF_MASK) >> PDM_HPF_MA_COEF_SHIFT) - -/* Bitfield definition for register: HPF_B */ -/* - * COEF (RW) - * - * coef B of the Order-1 HPF - */ -#define PDM_HPF_B_COEF_MASK (0xFFFFFFFFUL) -#define PDM_HPF_B_COEF_SHIFT (0U) -#define PDM_HPF_B_COEF_SET(x) (((uint32_t)(x) << PDM_HPF_B_COEF_SHIFT) & PDM_HPF_B_COEF_MASK) -#define PDM_HPF_B_COEF_GET(x) (((uint32_t)(x) & PDM_HPF_B_COEF_MASK) >> PDM_HPF_B_COEF_SHIFT) - - - - -#endif /* HPM_PDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pgpr_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pgpr_regs.h deleted file mode 100644 index acf20cfecd5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pgpr_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PGPR_H -#define HPM_PGPR_H - -typedef struct { - __RW uint32_t PMIC_GPR00; /* 0x0: Generic control */ - __RW uint32_t PMIC_GPR01; /* 0x4: Generic control */ - __RW uint32_t PMIC_GPR02; /* 0x8: Generic control */ - __RW uint32_t PMIC_GPR03; /* 0xC: Generic control */ - __RW uint32_t PMIC_GPR04; /* 0x10: Generic control */ - __RW uint32_t PMIC_GPR05; /* 0x14: Generic control */ - __RW uint32_t PMIC_GPR06; /* 0x18: Generic control */ - __RW uint32_t PMIC_GPR07; /* 0x1C: Generic control */ - __RW uint32_t PMIC_GPR08; /* 0x20: Generic control */ - __RW uint32_t PMIC_GPR09; /* 0x24: Generic control */ - __RW uint32_t PMIC_GPR10; /* 0x28: Generic control */ - __RW uint32_t PMIC_GPR11; /* 0x2C: Generic control */ - __RW uint32_t PMIC_GPR12; /* 0x30: Generic control */ - __RW uint32_t PMIC_GPR13; /* 0x34: Generic control */ - __RW uint32_t PMIC_GPR14; /* 0x38: Generic control */ - __RW uint32_t PMIC_GPR15; /* 0x3C: Generic control */ -} PGPR_Type; - - -/* Bitfield definition for register: PMIC_GPR00 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR00_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR00_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR00_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR00_GPR_SHIFT) & PGPR_PMIC_GPR00_GPR_MASK) -#define PGPR_PMIC_GPR00_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR00_GPR_MASK) >> PGPR_PMIC_GPR00_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR01 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR01_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR01_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR01_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR01_GPR_SHIFT) & PGPR_PMIC_GPR01_GPR_MASK) -#define PGPR_PMIC_GPR01_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR01_GPR_MASK) >> PGPR_PMIC_GPR01_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR02 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR02_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR02_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR02_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR02_GPR_SHIFT) & PGPR_PMIC_GPR02_GPR_MASK) -#define PGPR_PMIC_GPR02_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR02_GPR_MASK) >> PGPR_PMIC_GPR02_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR03 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR03_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR03_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR03_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR03_GPR_SHIFT) & PGPR_PMIC_GPR03_GPR_MASK) -#define PGPR_PMIC_GPR03_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR03_GPR_MASK) >> PGPR_PMIC_GPR03_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR04 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR04_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR04_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR04_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR04_GPR_SHIFT) & PGPR_PMIC_GPR04_GPR_MASK) -#define PGPR_PMIC_GPR04_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR04_GPR_MASK) >> PGPR_PMIC_GPR04_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR05 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR05_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR05_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR05_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR05_GPR_SHIFT) & PGPR_PMIC_GPR05_GPR_MASK) -#define PGPR_PMIC_GPR05_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR05_GPR_MASK) >> PGPR_PMIC_GPR05_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR06 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR06_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR06_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR06_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR06_GPR_SHIFT) & PGPR_PMIC_GPR06_GPR_MASK) -#define PGPR_PMIC_GPR06_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR06_GPR_MASK) >> PGPR_PMIC_GPR06_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR07 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR07_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR07_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR07_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR07_GPR_SHIFT) & PGPR_PMIC_GPR07_GPR_MASK) -#define PGPR_PMIC_GPR07_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR07_GPR_MASK) >> PGPR_PMIC_GPR07_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR08 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR08_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR08_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR08_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR08_GPR_SHIFT) & PGPR_PMIC_GPR08_GPR_MASK) -#define PGPR_PMIC_GPR08_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR08_GPR_MASK) >> PGPR_PMIC_GPR08_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR09 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR09_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR09_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR09_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR09_GPR_SHIFT) & PGPR_PMIC_GPR09_GPR_MASK) -#define PGPR_PMIC_GPR09_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR09_GPR_MASK) >> PGPR_PMIC_GPR09_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR10 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR10_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR10_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR10_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR10_GPR_SHIFT) & PGPR_PMIC_GPR10_GPR_MASK) -#define PGPR_PMIC_GPR10_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR10_GPR_MASK) >> PGPR_PMIC_GPR10_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR11 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR11_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR11_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR11_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR11_GPR_SHIFT) & PGPR_PMIC_GPR11_GPR_MASK) -#define PGPR_PMIC_GPR11_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR11_GPR_MASK) >> PGPR_PMIC_GPR11_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR12 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR12_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR12_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR12_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR12_GPR_SHIFT) & PGPR_PMIC_GPR12_GPR_MASK) -#define PGPR_PMIC_GPR12_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR12_GPR_MASK) >> PGPR_PMIC_GPR12_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR13 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR13_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR13_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR13_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR13_GPR_SHIFT) & PGPR_PMIC_GPR13_GPR_MASK) -#define PGPR_PMIC_GPR13_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR13_GPR_MASK) >> PGPR_PMIC_GPR13_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR14 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR14_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR14_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR14_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR14_GPR_SHIFT) & PGPR_PMIC_GPR14_GPR_MASK) -#define PGPR_PMIC_GPR14_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR14_GPR_MASK) >> PGPR_PMIC_GPR14_GPR_SHIFT) - -/* Bitfield definition for register: PMIC_GPR15 */ -/* - * GPR (RW) - * - * Generic control - */ -#define PGPR_PMIC_GPR15_GPR_MASK (0xFFFFFFFFUL) -#define PGPR_PMIC_GPR15_GPR_SHIFT (0U) -#define PGPR_PMIC_GPR15_GPR_SET(x) (((uint32_t)(x) << PGPR_PMIC_GPR15_GPR_SHIFT) & PGPR_PMIC_GPR15_GPR_MASK) -#define PGPR_PMIC_GPR15_GPR_GET(x) (((uint32_t)(x) & PGPR_PMIC_GPR15_GPR_MASK) >> PGPR_PMIC_GPR15_GPR_SHIFT) - - - - -#endif /* HPM_PGPR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pka_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pka_regs.h deleted file mode 100644 index 04def31f5b8..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pka_regs.h +++ /dev/null @@ -1,888 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PKA_H -#define HPM_PKA_H - -typedef struct { - __R uint8_t RESERVED0[49152]; /* 0x0 - 0xBFFF: Reserved */ - __RW uint32_t CTRL; /* 0xC000: Control Register */ - __R uint32_t STA; /* 0xC004: Status Register */ - __RW uint32_t INT_EN_REG; /* 0xC008: Interrupt Enable Register */ - __R uint8_t RESERVED1[52]; /* 0xC00C - 0xC03F: Reserved */ - union { - __RW uint32_t OP_CTRL0; /* 0xC040: Operation Control Register 0 */ - __RW uint32_t RSA_OP_CTRL; /* 0xC040: RSA Operation Control Register */ - __RW uint32_t ECC_OP_CTRL; /* 0xC040: ECC Operation Control Register */ - }; - union { - __RW uint32_t OP_CTRL1; /* 0xC044: Operation Control Register 1 */ - __RW uint32_t RSA_KEY_SIZE; /* 0xC044: RSA Private Key Size Register */ - __RW uint32_t ECC_NP0_ORDER_N; /* 0xC044: ECC Montgomery Parameter NP0 for Order N Register */ - }; - union { - __RW uint32_t OP_CTRL2; /* 0xC048: Operation Control Register 2 */ - __RW uint32_t RSA_MONT_N_SIZE; /* 0xC048: RSA Parameter N Size Register */ - __RW uint32_t ECC_P_SIZE; /* 0xC048: ECC Parameter P Size Register */ - }; - union { - __RW uint32_t OP_CTRL3; /* 0xC04C: Operation Control Register 3 */ - __R uint32_t RSA_MONT_R_SIZE; /* 0xC04C: RSA Montgomery Parameter R Size Register */ - __RW uint32_t ECC_MONT_R_SIZE; /* 0xC04C: ECC Montgomery Parameter R Size Register */ - }; - union { - __RW uint32_t OP_CTRL4; /* 0xC050: Operation Control Register 4 */ - __R uint32_t RSA_MONT_NP0; /* 0xC050: RSA Montgomery Parameter NP0 Register */ - __RW uint32_t ECC_MONT_NP0; /* 0xC050: ECC Montgomery Parameter NP0 Register */ - }; - union { - __RW uint32_t OP_CTRL5; /* 0xC054: Operation Control Register 5 */ - __RW uint32_t RSA_MONT_R2_MOD_N_PTR; /* 0xC054: RSA Montgomery Parameter R2N Register */ - __RW uint32_t ECC_MONT_R2_MOD_P_PTR; /* 0xC054: ECC Montgomery Parameter R2P Register */ - }; - union { - __RW uint32_t OP_CTRL6; /* 0xC058: Operation Control Register 6 */ - __RW uint32_t RSA_BIG_PRIME_PROD; /* 0xC058: RSA Public Parameter N Register */ - __RW uint32_t ECC_A; /* 0xC058: ECC Public Parameter A Register */ - }; - union { - __RW uint32_t OP_CTRL7; /* 0xC05C: Operation Control Register 7 */ - __RW uint32_t RSA_PUB_KEY; /* 0xC05C: RSA Public Key Register */ - __RW uint32_t ECC_B; /* 0xC05C: ECC Public Parameter B Register */ - }; - union { - __RW uint32_t OP_CTRL8; /* 0xC060: Operation Control Register 8 */ - __RW uint32_t ECC_P; /* 0xC060: ECC Public Parameter P Register */ - }; - union { - __RW uint32_t OP_CTRL9; /* 0xC064: Operation Control Register 9 */ - __RW uint32_t RSA_M; /* 0xC064: RSA M Register */ - __RW uint32_t ECC_GEN_X; /* 0xC064: ECC Public Parameter GX Register */ - }; - union { - __RW uint32_t OP_CTRLA; /* 0xC068: Operation Control Register A */ - __RW uint32_t RSA_TM0; /* 0xC068: RSA TM0 Register */ - __RW uint32_t ECC_GEN_Y; /* 0xC068: ECC Public Parameter GY Register */ - }; - union { - __RW uint32_t OP_CTRLB; /* 0xC06C: Operation Control Register B */ - __RW uint32_t RSA_TM1; /* 0xC06C: RSA TM1 Register */ - __RW uint32_t ECC_PUB_X; /* 0xC06C: ECC Public Parameter PX Register */ - }; - union { - __RW uint32_t OP_CTRLC; /* 0xC070: Operation Control Register C */ - __RW uint32_t RSA_O; /* 0xC070: RSA O Register */ - __RW uint32_t ECC_PUB_Y; /* 0xC070: ECC Public Parameter PY Register */ - }; - union { - __RW uint32_t OP_CTRLD; /* 0xC074: Operation Control Register D */ - __RW uint32_t RSA_PRIV_KEY; /* 0xC074: RSA Private Parameter d Register */ - __RW uint32_t ECC_PRIV_K; /* 0xC074: ECC Private Parameter K Register */ - }; - union { - __RW uint32_t OP_CTRLE; /* 0xC078: Operation Control Register E */ - __RW uint32_t ECC_GENORD_N; /* 0xC078: ECC Public Parameter Order N Register */ - }; - union { - __RW uint32_t OP_CTRLF; /* 0xC07C: Operation Control Register F */ - __RW uint32_t ECC_R2N_ORDER_N; /* 0xC07C: ECC Montgomery Parameter R2N Register */ - }; -} PKA_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * DIS_CIPHER (RW) - * - * Sticky at 1. - * 1: Disable Cipher Operation. When Disabled, clear all memory contents, and run in infinite loop. Only module reset can recover the module. - */ -#define PKA_CTRL_DIS_CIPHER_MASK (0x80000000UL) -#define PKA_CTRL_DIS_CIPHER_SHIFT (31U) -#define PKA_CTRL_DIS_CIPHER_SET(x) (((uint32_t)(x) << PKA_CTRL_DIS_CIPHER_SHIFT) & PKA_CTRL_DIS_CIPHER_MASK) -#define PKA_CTRL_DIS_CIPHER_GET(x) (((uint32_t)(x) & PKA_CTRL_DIS_CIPHER_MASK) >> PKA_CTRL_DIS_CIPHER_SHIFT) - -/* - * PRIM_OP (RW) - * - * 1: Run primitive operations. - * 0: Run composite operations - */ -#define PKA_CTRL_PRIM_OP_MASK (0x40000000UL) -#define PKA_CTRL_PRIM_OP_SHIFT (30U) -#define PKA_CTRL_PRIM_OP_SET(x) (((uint32_t)(x) << PKA_CTRL_PRIM_OP_SHIFT) & PKA_CTRL_PRIM_OP_MASK) -#define PKA_CTRL_PRIM_OP_GET(x) (((uint32_t)(x) & PKA_CTRL_PRIM_OP_MASK) >> PKA_CTRL_PRIM_OP_SHIFT) - -/* - * SFTRST (RW) - * - * Software reset - */ -#define PKA_CTRL_SFTRST_MASK (0x400U) -#define PKA_CTRL_SFTRST_SHIFT (10U) -#define PKA_CTRL_SFTRST_SET(x) (((uint32_t)(x) << PKA_CTRL_SFTRST_SHIFT) & PKA_CTRL_SFTRST_MASK) -#define PKA_CTRL_SFTRST_GET(x) (((uint32_t)(x) & PKA_CTRL_SFTRST_MASK) >> PKA_CTRL_SFTRST_SHIFT) - -/* - * CRYPTO_OP (RW) - * - * When CTRL[PRIM_OP]=1, - * 0: Modulus MULT - * 0x1: Modulus ADD - * 0x2: Modulus MINUS - * 0x3: GCD - * 0x4: memory copy (address range should not overlap, no check of this) - * 0x5: asr1 - * 0x6: sr1 - * 0x7: bn_len - * 0x8: DeProj - * 0x9: disable memory copy - * 0xA. Find BN modulus - * 0xC. KEY2SDP (copy key from internal to sdp interface) - * 0xD. ECCPointAdd - * 0xE. SCL_MOD (cal h*k mod n, GFp domain) - * When CTRL[PRIM_OP]=0, - * 0x0: ini the PKA parameters. This is to store the config parameters that are assigned in interface regs, and do norm2mont transfers to the related ECC A/B/GX/GY. - * 0x2: For ECC, do scalar multiplication. For RSA, do power modulus. So this mode can be used to generate the public key. - * For RSA, Before entering key generation, whole mem rd is blocked. --> During key generation. Np is p, pub_key is q, --> prod is p*q, encrpt_msg is phi, Np and pub_key is cleared --> then priv_key is priv_key, --> then pub_key is cal --> encrpt_msg is cleaed --> mem blockage removed. - * For ECC, Before entering key generation, whole mem rd is blocked. --> check A/B/P are valid values --> randomly choose GX --> search for GY --> cal order N, stored in NP --> if N is great enough, randomly choose private K --> cal PX, PY --> NP is cleaed --> mem blockage removed. - * 0x5: SM2 DSA gen (must use internal stored ECC parameters) - * 0xC: SM2 DSA verify (must use internal stored ECC parameters, with PAX, PAY not in mont type yet) - * 0x1C: SM2 DSA verify (with PAX, PAY already in mont type) - */ -#define PKA_CTRL_CRYPTO_OP_MASK (0xF8U) -#define PKA_CTRL_CRYPTO_OP_SHIFT (3U) -#define PKA_CTRL_CRYPTO_OP_SET(x) (((uint32_t)(x) << PKA_CTRL_CRYPTO_OP_SHIFT) & PKA_CTRL_CRYPTO_OP_MASK) -#define PKA_CTRL_CRYPTO_OP_GET(x) (((uint32_t)(x) & PKA_CTRL_CRYPTO_OP_MASK) >> PKA_CTRL_CRYPTO_OP_SHIFT) - -/* - * OP_ACTIVE (RW) - * - * 1: operation active. Self clear - * 0: operation not active - */ -#define PKA_CTRL_OP_ACTIVE_MASK (0x4U) -#define PKA_CTRL_OP_ACTIVE_SHIFT (2U) -#define PKA_CTRL_OP_ACTIVE_SET(x) (((uint32_t)(x) << PKA_CTRL_OP_ACTIVE_SHIFT) & PKA_CTRL_OP_ACTIVE_MASK) -#define PKA_CTRL_OP_ACTIVE_GET(x) (((uint32_t)(x) & PKA_CTRL_OP_ACTIVE_MASK) >> PKA_CTRL_OP_ACTIVE_SHIFT) - -/* - * ECC1_RSA0 (RW) - * - * crypto_op - */ -#define PKA_CTRL_ECC1_RSA0_MASK (0x2U) -#define PKA_CTRL_ECC1_RSA0_SHIFT (1U) -#define PKA_CTRL_ECC1_RSA0_SET(x) (((uint32_t)(x) << PKA_CTRL_ECC1_RSA0_SHIFT) & PKA_CTRL_ECC1_RSA0_MASK) -#define PKA_CTRL_ECC1_RSA0_GET(x) (((uint32_t)(x) & PKA_CTRL_ECC1_RSA0_MASK) >> PKA_CTRL_ECC1_RSA0_SHIFT) - -/* - * PKA_EN (RW) - * - * 1b-Enabled - */ -#define PKA_CTRL_PKA_EN_MASK (0x1U) -#define PKA_CTRL_PKA_EN_SHIFT (0U) -#define PKA_CTRL_PKA_EN_SET(x) (((uint32_t)(x) << PKA_CTRL_PKA_EN_SHIFT) & PKA_CTRL_PKA_EN_MASK) -#define PKA_CTRL_PKA_EN_GET(x) (((uint32_t)(x) & PKA_CTRL_PKA_EN_MASK) >> PKA_CTRL_PKA_EN_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * OSTA (RO) - * - * Multiplexed STA. This is the STA from internal firmware. - */ -#define PKA_STA_OSTA_MASK (0xFFFF0000UL) -#define PKA_STA_OSTA_SHIFT (16U) -#define PKA_STA_OSTA_GET(x) (((uint32_t)(x) & PKA_STA_OSTA_MASK) >> PKA_STA_OSTA_SHIFT) - -/* - * INI_DONE (RO) - * - * 1: Initialization Done. - * 0: Initialization not done. - */ -#define PKA_STA_INI_DONE_MASK (0x10U) -#define PKA_STA_INI_DONE_SHIFT (4U) -#define PKA_STA_INI_DONE_GET(x) (((uint32_t)(x) & PKA_STA_INI_DONE_MASK) >> PKA_STA_INI_DONE_SHIFT) - -/* - * OP_DONE (RO) - * - * Operation Done - */ -#define PKA_STA_OP_DONE_MASK (0x1U) -#define PKA_STA_OP_DONE_SHIFT (0U) -#define PKA_STA_OP_DONE_GET(x) (((uint32_t)(x) & PKA_STA_OP_DONE_MASK) >> PKA_STA_OP_DONE_SHIFT) - -/* Bitfield definition for register: INT_EN_REG */ -/* - * OSTA_IE (RW) - * - * interrupt enale for Multiplexed STA bits. - */ -#define PKA_INT_EN_REG_OSTA_IE_MASK (0xFFFF0000UL) -#define PKA_INT_EN_REG_OSTA_IE_SHIFT (16U) -#define PKA_INT_EN_REG_OSTA_IE_SET(x) (((uint32_t)(x) << PKA_INT_EN_REG_OSTA_IE_SHIFT) & PKA_INT_EN_REG_OSTA_IE_MASK) -#define PKA_INT_EN_REG_OSTA_IE_GET(x) (((uint32_t)(x) & PKA_INT_EN_REG_OSTA_IE_MASK) >> PKA_INT_EN_REG_OSTA_IE_SHIFT) - -/* - * OP_DONE_IE (RW) - * - * interrupt enale - */ -#define PKA_INT_EN_REG_OP_DONE_IE_MASK (0x1U) -#define PKA_INT_EN_REG_OP_DONE_IE_SHIFT (0U) -#define PKA_INT_EN_REG_OP_DONE_IE_SET(x) (((uint32_t)(x) << PKA_INT_EN_REG_OP_DONE_IE_SHIFT) & PKA_INT_EN_REG_OP_DONE_IE_MASK) -#define PKA_INT_EN_REG_OP_DONE_IE_GET(x) (((uint32_t)(x) & PKA_INT_EN_REG_OP_DONE_IE_MASK) >> PKA_INT_EN_REG_OP_DONE_IE_SHIFT) - -/* Bitfield definition for register: OP_CTRL0 */ -/* - * INFO_BLK_IDX (RW) - * - * The loc index of related information for storage or retrieve - * bit 1:0 -- the memory location - * bit 4:2 -- the info idx - */ -#define PKA_OP_CTRL0_INFO_BLK_IDX_MASK (0xF8000000UL) -#define PKA_OP_CTRL0_INFO_BLK_IDX_SHIFT (27U) -#define PKA_OP_CTRL0_INFO_BLK_IDX_SET(x) (((uint32_t)(x) << PKA_OP_CTRL0_INFO_BLK_IDX_SHIFT) & PKA_OP_CTRL0_INFO_BLK_IDX_MASK) -#define PKA_OP_CTRL0_INFO_BLK_IDX_GET(x) (((uint32_t)(x) & PKA_OP_CTRL0_INFO_BLK_IDX_MASK) >> PKA_OP_CTRL0_INFO_BLK_IDX_SHIFT) - -/* - * INFO_OP (RW) - * - * 1: Storage. The following info will be stored into the internal memory. Some Mont transform will be done. So some stored info will be in Mont format. - * 0: Retrieve. The stored info will be used instead of the following configurations. - */ -#define PKA_OP_CTRL0_INFO_OP_MASK (0x4000000UL) -#define PKA_OP_CTRL0_INFO_OP_SHIFT (26U) -#define PKA_OP_CTRL0_INFO_OP_SET(x) (((uint32_t)(x) << PKA_OP_CTRL0_INFO_OP_SHIFT) & PKA_OP_CTRL0_INFO_OP_MASK) -#define PKA_OP_CTRL0_INFO_OP_GET(x) (((uint32_t)(x) & PKA_OP_CTRL0_INFO_OP_MASK) >> PKA_OP_CTRL0_INFO_OP_SHIFT) - -/* Bitfield definition for register: RSA_OP_CTRL */ -/* - * INFO_BLK_IDX (RW) - * - * The loc index of related information for storage or retrieve - * bit 1:0 -- the memory location - * bit 4:2 -- the info idx - */ -#define PKA_RSA_OP_CTRL_INFO_BLK_IDX_MASK (0xF8000000UL) -#define PKA_RSA_OP_CTRL_INFO_BLK_IDX_SHIFT (27U) -#define PKA_RSA_OP_CTRL_INFO_BLK_IDX_SET(x) (((uint32_t)(x) << PKA_RSA_OP_CTRL_INFO_BLK_IDX_SHIFT) & PKA_RSA_OP_CTRL_INFO_BLK_IDX_MASK) -#define PKA_RSA_OP_CTRL_INFO_BLK_IDX_GET(x) (((uint32_t)(x) & PKA_RSA_OP_CTRL_INFO_BLK_IDX_MASK) >> PKA_RSA_OP_CTRL_INFO_BLK_IDX_SHIFT) - -/* - * INFO_OP (RW) - * - * 1: Storage. The following info will be stored into the internal memory. Some Mont transform will be done. So some stored info will be in Mont format. - * 0: Retrieve. The stored info will be used instead of the following configurations. - */ -#define PKA_RSA_OP_CTRL_INFO_OP_MASK (0x4000000UL) -#define PKA_RSA_OP_CTRL_INFO_OP_SHIFT (26U) -#define PKA_RSA_OP_CTRL_INFO_OP_SET(x) (((uint32_t)(x) << PKA_RSA_OP_CTRL_INFO_OP_SHIFT) & PKA_RSA_OP_CTRL_INFO_OP_MASK) -#define PKA_RSA_OP_CTRL_INFO_OP_GET(x) (((uint32_t)(x) & PKA_RSA_OP_CTRL_INFO_OP_MASK) >> PKA_RSA_OP_CTRL_INFO_OP_SHIFT) - -/* - * EQUALIZED_CTRL (RW) - * - * the prcessing will be in equalized state. Can only be used for PKA[RSA_BIG_PRIME_PROD] with a size smaller than or equal to 2048. - */ -#define PKA_RSA_OP_CTRL_EQUALIZED_CTRL_MASK (0x2U) -#define PKA_RSA_OP_CTRL_EQUALIZED_CTRL_SHIFT (1U) -#define PKA_RSA_OP_CTRL_EQUALIZED_CTRL_SET(x) (((uint32_t)(x) << PKA_RSA_OP_CTRL_EQUALIZED_CTRL_SHIFT) & PKA_RSA_OP_CTRL_EQUALIZED_CTRL_MASK) -#define PKA_RSA_OP_CTRL_EQUALIZED_CTRL_GET(x) (((uint32_t)(x) & PKA_RSA_OP_CTRL_EQUALIZED_CTRL_MASK) >> PKA_RSA_OP_CTRL_EQUALIZED_CTRL_SHIFT) - -/* - * ECC1_RSA0 (RW) - * - * Should be 0 to select RSA - */ -#define PKA_RSA_OP_CTRL_ECC1_RSA0_MASK (0x1U) -#define PKA_RSA_OP_CTRL_ECC1_RSA0_SHIFT (0U) -#define PKA_RSA_OP_CTRL_ECC1_RSA0_SET(x) (((uint32_t)(x) << PKA_RSA_OP_CTRL_ECC1_RSA0_SHIFT) & PKA_RSA_OP_CTRL_ECC1_RSA0_MASK) -#define PKA_RSA_OP_CTRL_ECC1_RSA0_GET(x) (((uint32_t)(x) & PKA_RSA_OP_CTRL_ECC1_RSA0_MASK) >> PKA_RSA_OP_CTRL_ECC1_RSA0_SHIFT) - -/* Bitfield definition for register: ECC_OP_CTRL */ -/* - * INFO_BLK_IDX (RW) - * - * The loc index of related information for storage or retrieve - * bit 1:0 -- the memory location - * bit 4:2 -- the info idx - */ -#define PKA_ECC_OP_CTRL_INFO_BLK_IDX_MASK (0xF8000000UL) -#define PKA_ECC_OP_CTRL_INFO_BLK_IDX_SHIFT (27U) -#define PKA_ECC_OP_CTRL_INFO_BLK_IDX_SET(x) (((uint32_t)(x) << PKA_ECC_OP_CTRL_INFO_BLK_IDX_SHIFT) & PKA_ECC_OP_CTRL_INFO_BLK_IDX_MASK) -#define PKA_ECC_OP_CTRL_INFO_BLK_IDX_GET(x) (((uint32_t)(x) & PKA_ECC_OP_CTRL_INFO_BLK_IDX_MASK) >> PKA_ECC_OP_CTRL_INFO_BLK_IDX_SHIFT) - -/* - * INFO_OP (RW) - * - * 1: Storage. The following info will be stored into the internal memory. Some Mont transform will be done. So some stored info will be in Mont format. - * 0: Retrieve. The stored info will be used instead of the following configurations. - */ -#define PKA_ECC_OP_CTRL_INFO_OP_MASK (0x4000000UL) -#define PKA_ECC_OP_CTRL_INFO_OP_SHIFT (26U) -#define PKA_ECC_OP_CTRL_INFO_OP_SET(x) (((uint32_t)(x) << PKA_ECC_OP_CTRL_INFO_OP_SHIFT) & PKA_ECC_OP_CTRL_INFO_OP_MASK) -#define PKA_ECC_OP_CTRL_INFO_OP_GET(x) (((uint32_t)(x) & PKA_ECC_OP_CTRL_INFO_OP_MASK) >> PKA_ECC_OP_CTRL_INFO_OP_SHIFT) - -/* - * GF_OPT (RW) - * - * 1: GF2m - * 0: GFp - */ -#define PKA_ECC_OP_CTRL_GF_OPT_MASK (0x4U) -#define PKA_ECC_OP_CTRL_GF_OPT_SHIFT (2U) -#define PKA_ECC_OP_CTRL_GF_OPT_SET(x) (((uint32_t)(x) << PKA_ECC_OP_CTRL_GF_OPT_SHIFT) & PKA_ECC_OP_CTRL_GF_OPT_MASK) -#define PKA_ECC_OP_CTRL_GF_OPT_GET(x) (((uint32_t)(x) & PKA_ECC_OP_CTRL_GF_OPT_MASK) >> PKA_ECC_OP_CTRL_GF_OPT_SHIFT) - -/* - * EQUALIZED_CTRL (RW) - * - * the prcessing will be in equalized state - */ -#define PKA_ECC_OP_CTRL_EQUALIZED_CTRL_MASK (0x2U) -#define PKA_ECC_OP_CTRL_EQUALIZED_CTRL_SHIFT (1U) -#define PKA_ECC_OP_CTRL_EQUALIZED_CTRL_SET(x) (((uint32_t)(x) << PKA_ECC_OP_CTRL_EQUALIZED_CTRL_SHIFT) & PKA_ECC_OP_CTRL_EQUALIZED_CTRL_MASK) -#define PKA_ECC_OP_CTRL_EQUALIZED_CTRL_GET(x) (((uint32_t)(x) & PKA_ECC_OP_CTRL_EQUALIZED_CTRL_MASK) >> PKA_ECC_OP_CTRL_EQUALIZED_CTRL_SHIFT) - -/* - * ECC1_RSA0 (RW) - * - * Should be 1 to select ECC - */ -#define PKA_ECC_OP_CTRL_ECC1_RSA0_MASK (0x1U) -#define PKA_ECC_OP_CTRL_ECC1_RSA0_SHIFT (0U) -#define PKA_ECC_OP_CTRL_ECC1_RSA0_SET(x) (((uint32_t)(x) << PKA_ECC_OP_CTRL_ECC1_RSA0_SHIFT) & PKA_ECC_OP_CTRL_ECC1_RSA0_MASK) -#define PKA_ECC_OP_CTRL_ECC1_RSA0_GET(x) (((uint32_t)(x) & PKA_ECC_OP_CTRL_ECC1_RSA0_MASK) >> PKA_ECC_OP_CTRL_ECC1_RSA0_SHIFT) - -/* Bitfield definition for register: OP_CTRL1 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL1_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL1_VAL_SHIFT (0U) -#define PKA_OP_CTRL1_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL1_VAL_SHIFT) & PKA_OP_CTRL1_VAL_MASK) -#define PKA_OP_CTRL1_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL1_VAL_MASK) >> PKA_OP_CTRL1_VAL_SHIFT) - -/* Bitfield definition for register: RSA_KEY_SIZE */ -/* - * VAL (RW) - * - * The bit length-1 of RSA key (max 4096-1) - */ -#define PKA_RSA_KEY_SIZE_VAL_MASK (0x1FFFU) -#define PKA_RSA_KEY_SIZE_VAL_SHIFT (0U) -#define PKA_RSA_KEY_SIZE_VAL_SET(x) (((uint32_t)(x) << PKA_RSA_KEY_SIZE_VAL_SHIFT) & PKA_RSA_KEY_SIZE_VAL_MASK) -#define PKA_RSA_KEY_SIZE_VAL_GET(x) (((uint32_t)(x) & PKA_RSA_KEY_SIZE_VAL_MASK) >> PKA_RSA_KEY_SIZE_VAL_SHIFT) - -/* Bitfield definition for register: ECC_NP0_ORDER_N */ -/* - * VAL (RW) - * - * The NP0 parameter for Montegomery transform of ECC order N - */ -#define PKA_ECC_NP0_ORDER_N_VAL_MASK (0xFFFFFFFFUL) -#define PKA_ECC_NP0_ORDER_N_VAL_SHIFT (0U) -#define PKA_ECC_NP0_ORDER_N_VAL_SET(x) (((uint32_t)(x) << PKA_ECC_NP0_ORDER_N_VAL_SHIFT) & PKA_ECC_NP0_ORDER_N_VAL_MASK) -#define PKA_ECC_NP0_ORDER_N_VAL_GET(x) (((uint32_t)(x) & PKA_ECC_NP0_ORDER_N_VAL_MASK) >> PKA_ECC_NP0_ORDER_N_VAL_SHIFT) - -/* Bitfield definition for register: OP_CTRL2 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL2_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL2_VAL_SHIFT (0U) -#define PKA_OP_CTRL2_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL2_VAL_SHIFT) & PKA_OP_CTRL2_VAL_MASK) -#define PKA_OP_CTRL2_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL2_VAL_MASK) >> PKA_OP_CTRL2_VAL_SHIFT) - -/* Bitfield definition for register: RSA_MONT_N_SIZE */ -/* - * VAL (RW) - * - * The bit length of RSA N parameter - */ -#define PKA_RSA_MONT_N_SIZE_VAL_MASK (0x1FFFU) -#define PKA_RSA_MONT_N_SIZE_VAL_SHIFT (0U) -#define PKA_RSA_MONT_N_SIZE_VAL_SET(x) (((uint32_t)(x) << PKA_RSA_MONT_N_SIZE_VAL_SHIFT) & PKA_RSA_MONT_N_SIZE_VAL_MASK) -#define PKA_RSA_MONT_N_SIZE_VAL_GET(x) (((uint32_t)(x) & PKA_RSA_MONT_N_SIZE_VAL_MASK) >> PKA_RSA_MONT_N_SIZE_VAL_SHIFT) - -/* Bitfield definition for register: ECC_P_SIZE */ -/* - * H_VAL (RW) - * - * Cofactor value - */ -#define PKA_ECC_P_SIZE_H_VAL_MASK (0xFFFF0000UL) -#define PKA_ECC_P_SIZE_H_VAL_SHIFT (16U) -#define PKA_ECC_P_SIZE_H_VAL_SET(x) (((uint32_t)(x) << PKA_ECC_P_SIZE_H_VAL_SHIFT) & PKA_ECC_P_SIZE_H_VAL_MASK) -#define PKA_ECC_P_SIZE_H_VAL_GET(x) (((uint32_t)(x) & PKA_ECC_P_SIZE_H_VAL_MASK) >> PKA_ECC_P_SIZE_H_VAL_SHIFT) - -/* - * VAL (RW) - * - * The bit length of ECC P parameter - */ -#define PKA_ECC_P_SIZE_VAL_MASK (0x1FFFU) -#define PKA_ECC_P_SIZE_VAL_SHIFT (0U) -#define PKA_ECC_P_SIZE_VAL_SET(x) (((uint32_t)(x) << PKA_ECC_P_SIZE_VAL_SHIFT) & PKA_ECC_P_SIZE_VAL_MASK) -#define PKA_ECC_P_SIZE_VAL_GET(x) (((uint32_t)(x) & PKA_ECC_P_SIZE_VAL_MASK) >> PKA_ECC_P_SIZE_VAL_SHIFT) - -/* Bitfield definition for register: OP_CTRL3 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL3_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL3_VAL_SHIFT (0U) -#define PKA_OP_CTRL3_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL3_VAL_SHIFT) & PKA_OP_CTRL3_VAL_MASK) -#define PKA_OP_CTRL3_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL3_VAL_MASK) >> PKA_OP_CTRL3_VAL_SHIFT) - -/* Bitfield definition for register: RSA_MONT_R_SIZE */ -/* - * VAL (RE) - * - * The bit length of RSA R parameter for Montegomery transform. Should be equal to 32*n+1 - */ -#define PKA_RSA_MONT_R_SIZE_VAL_MASK (0x1FFFU) -#define PKA_RSA_MONT_R_SIZE_VAL_SHIFT (0U) -#define PKA_RSA_MONT_R_SIZE_VAL_GET(x) (((uint32_t)(x) & PKA_RSA_MONT_R_SIZE_VAL_MASK) >> PKA_RSA_MONT_R_SIZE_VAL_SHIFT) - -/* Bitfield definition for register: ECC_MONT_R_SIZE */ -/* - * KEY_SIZE (RW) - * - * The bit length-1 of ECC key - */ -#define PKA_ECC_MONT_R_SIZE_KEY_SIZE_MASK (0xFFFF0000UL) -#define PKA_ECC_MONT_R_SIZE_KEY_SIZE_SHIFT (16U) -#define PKA_ECC_MONT_R_SIZE_KEY_SIZE_SET(x) (((uint32_t)(x) << PKA_ECC_MONT_R_SIZE_KEY_SIZE_SHIFT) & PKA_ECC_MONT_R_SIZE_KEY_SIZE_MASK) -#define PKA_ECC_MONT_R_SIZE_KEY_SIZE_GET(x) (((uint32_t)(x) & PKA_ECC_MONT_R_SIZE_KEY_SIZE_MASK) >> PKA_ECC_MONT_R_SIZE_KEY_SIZE_SHIFT) - -/* - * VAL (RW) - * - * The bit length of ECC R parameter for Montegomery transform. Should be equal to 32*n+1 - */ -#define PKA_ECC_MONT_R_SIZE_VAL_MASK (0x1FFFU) -#define PKA_ECC_MONT_R_SIZE_VAL_SHIFT (0U) -#define PKA_ECC_MONT_R_SIZE_VAL_SET(x) (((uint32_t)(x) << PKA_ECC_MONT_R_SIZE_VAL_SHIFT) & PKA_ECC_MONT_R_SIZE_VAL_MASK) -#define PKA_ECC_MONT_R_SIZE_VAL_GET(x) (((uint32_t)(x) & PKA_ECC_MONT_R_SIZE_VAL_MASK) >> PKA_ECC_MONT_R_SIZE_VAL_SHIFT) - -/* Bitfield definition for register: OP_CTRL4 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL4_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL4_VAL_SHIFT (0U) -#define PKA_OP_CTRL4_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL4_VAL_SHIFT) & PKA_OP_CTRL4_VAL_MASK) -#define PKA_OP_CTRL4_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL4_VAL_MASK) >> PKA_OP_CTRL4_VAL_SHIFT) - -/* Bitfield definition for register: RSA_MONT_NP0 */ -/* - * VAL (RE) - * - * The NP0 parameter for Montegomery transform of RSA - */ -#define PKA_RSA_MONT_NP0_VAL_MASK (0xFFFFFFFFUL) -#define PKA_RSA_MONT_NP0_VAL_SHIFT (0U) -#define PKA_RSA_MONT_NP0_VAL_GET(x) (((uint32_t)(x) & PKA_RSA_MONT_NP0_VAL_MASK) >> PKA_RSA_MONT_NP0_VAL_SHIFT) - -/* Bitfield definition for register: ECC_MONT_NP0 */ -/* - * VAL (RW) - * - * The NP0 parameter for ECC P-based Montegomery transform of ECC - */ -#define PKA_ECC_MONT_NP0_VAL_MASK (0xFFFFFFFFUL) -#define PKA_ECC_MONT_NP0_VAL_SHIFT (0U) -#define PKA_ECC_MONT_NP0_VAL_SET(x) (((uint32_t)(x) << PKA_ECC_MONT_NP0_VAL_SHIFT) & PKA_ECC_MONT_NP0_VAL_MASK) -#define PKA_ECC_MONT_NP0_VAL_GET(x) (((uint32_t)(x) & PKA_ECC_MONT_NP0_VAL_MASK) >> PKA_ECC_MONT_NP0_VAL_SHIFT) - -/* Bitfield definition for register: OP_CTRL5 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL5_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL5_VAL_SHIFT (0U) -#define PKA_OP_CTRL5_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL5_VAL_SHIFT) & PKA_OP_CTRL5_VAL_MASK) -#define PKA_OP_CTRL5_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL5_VAL_MASK) >> PKA_OP_CTRL5_VAL_SHIFT) - -/* Bitfield definition for register: RSA_MONT_R2_MOD_N_PTR */ -/* - * VAL (RW) - * - * The address pointer value for holding the value of mod(R*R, N) for Montegomery transform - */ -#define PKA_RSA_MONT_R2_MOD_N_PTR_VAL_MASK (0x1FFFU) -#define PKA_RSA_MONT_R2_MOD_N_PTR_VAL_SHIFT (0U) -#define PKA_RSA_MONT_R2_MOD_N_PTR_VAL_SET(x) (((uint32_t)(x) << PKA_RSA_MONT_R2_MOD_N_PTR_VAL_SHIFT) & PKA_RSA_MONT_R2_MOD_N_PTR_VAL_MASK) -#define PKA_RSA_MONT_R2_MOD_N_PTR_VAL_GET(x) (((uint32_t)(x) & PKA_RSA_MONT_R2_MOD_N_PTR_VAL_MASK) >> PKA_RSA_MONT_R2_MOD_N_PTR_VAL_SHIFT) - -/* Bitfield definition for register: ECC_MONT_R2_MOD_P_PTR */ -/* - * VAL (RW) - * - * The address pointer value for holding the value of mod(R*R, P) for Montegomery transform - */ -#define PKA_ECC_MONT_R2_MOD_P_PTR_VAL_MASK (0x1FFFU) -#define PKA_ECC_MONT_R2_MOD_P_PTR_VAL_SHIFT (0U) -#define PKA_ECC_MONT_R2_MOD_P_PTR_VAL_SET(x) (((uint32_t)(x) << PKA_ECC_MONT_R2_MOD_P_PTR_VAL_SHIFT) & PKA_ECC_MONT_R2_MOD_P_PTR_VAL_MASK) -#define PKA_ECC_MONT_R2_MOD_P_PTR_VAL_GET(x) (((uint32_t)(x) & PKA_ECC_MONT_R2_MOD_P_PTR_VAL_MASK) >> PKA_ECC_MONT_R2_MOD_P_PTR_VAL_SHIFT) - -/* Bitfield definition for register: OP_CTRL6 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL6_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL6_VAL_SHIFT (0U) -#define PKA_OP_CTRL6_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL6_VAL_SHIFT) & PKA_OP_CTRL6_VAL_MASK) -#define PKA_OP_CTRL6_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL6_VAL_MASK) >> PKA_OP_CTRL6_VAL_SHIFT) - -/* Bitfield definition for register: RSA_BIG_PRIME_PROD */ -/* - * ADDR (RW) - * - * The starting location of RSA big prime production inside the local 256-bits blocks - */ -#define PKA_RSA_BIG_PRIME_PROD_ADDR_MASK (0x1FFFU) -#define PKA_RSA_BIG_PRIME_PROD_ADDR_SHIFT (0U) -#define PKA_RSA_BIG_PRIME_PROD_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_BIG_PRIME_PROD_ADDR_SHIFT) & PKA_RSA_BIG_PRIME_PROD_ADDR_MASK) -#define PKA_RSA_BIG_PRIME_PROD_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_BIG_PRIME_PROD_ADDR_MASK) >> PKA_RSA_BIG_PRIME_PROD_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_A */ -/* - * ADDR (RW) - * - * The address of the ECC Curve parameter A inside the local 256-bits blocks - */ -#define PKA_ECC_A_ADDR_MASK (0x1FFFU) -#define PKA_ECC_A_ADDR_SHIFT (0U) -#define PKA_ECC_A_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_A_ADDR_SHIFT) & PKA_ECC_A_ADDR_MASK) -#define PKA_ECC_A_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_A_ADDR_MASK) >> PKA_ECC_A_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRL7 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL7_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL7_VAL_SHIFT (0U) -#define PKA_OP_CTRL7_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL7_VAL_SHIFT) & PKA_OP_CTRL7_VAL_MASK) -#define PKA_OP_CTRL7_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL7_VAL_MASK) >> PKA_OP_CTRL7_VAL_SHIFT) - -/* Bitfield definition for register: RSA_PUB_KEY */ -/* - * ADDR (RW) - * - * The starting location of RSA public key inside the local 256-bits blocks - */ -#define PKA_RSA_PUB_KEY_ADDR_MASK (0x1FFFU) -#define PKA_RSA_PUB_KEY_ADDR_SHIFT (0U) -#define PKA_RSA_PUB_KEY_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_PUB_KEY_ADDR_SHIFT) & PKA_RSA_PUB_KEY_ADDR_MASK) -#define PKA_RSA_PUB_KEY_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_PUB_KEY_ADDR_MASK) >> PKA_RSA_PUB_KEY_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_B */ -/* - * ADDR (RW) - * - * The address of the ECC Curve parameter B inside the local 256-bits blocks - */ -#define PKA_ECC_B_ADDR_MASK (0x1FFFU) -#define PKA_ECC_B_ADDR_SHIFT (0U) -#define PKA_ECC_B_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_B_ADDR_SHIFT) & PKA_ECC_B_ADDR_MASK) -#define PKA_ECC_B_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_B_ADDR_MASK) >> PKA_ECC_B_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRL8 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL8_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL8_VAL_SHIFT (0U) -#define PKA_OP_CTRL8_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL8_VAL_SHIFT) & PKA_OP_CTRL8_VAL_MASK) -#define PKA_OP_CTRL8_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL8_VAL_MASK) >> PKA_OP_CTRL8_VAL_SHIFT) - -/* Bitfield definition for register: ECC_P */ -/* - * ADDR (RW) - * - * The address of the ECC parameter P inside the local 256-bits blocks - */ -#define PKA_ECC_P_ADDR_MASK (0x1FFFU) -#define PKA_ECC_P_ADDR_SHIFT (0U) -#define PKA_ECC_P_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_P_ADDR_SHIFT) & PKA_ECC_P_ADDR_MASK) -#define PKA_ECC_P_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_P_ADDR_MASK) >> PKA_ECC_P_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRL9 */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRL9_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRL9_VAL_SHIFT (0U) -#define PKA_OP_CTRL9_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRL9_VAL_SHIFT) & PKA_OP_CTRL9_VAL_MASK) -#define PKA_OP_CTRL9_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRL9_VAL_MASK) >> PKA_OP_CTRL9_VAL_SHIFT) - -/* Bitfield definition for register: RSA_M */ -/* - * ADDR (RW) - * - * The starting location of RSA buffer M inside the local 256-bits blocks - */ -#define PKA_RSA_M_ADDR_MASK (0x1FFFU) -#define PKA_RSA_M_ADDR_SHIFT (0U) -#define PKA_RSA_M_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_M_ADDR_SHIFT) & PKA_RSA_M_ADDR_MASK) -#define PKA_RSA_M_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_M_ADDR_MASK) >> PKA_RSA_M_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_GEN_X */ -/* - * ADDR (RW) - * - * The address of the ECC generator X location inside the local 256-bits blocks - */ -#define PKA_ECC_GEN_X_ADDR_MASK (0x1FFFU) -#define PKA_ECC_GEN_X_ADDR_SHIFT (0U) -#define PKA_ECC_GEN_X_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_GEN_X_ADDR_SHIFT) & PKA_ECC_GEN_X_ADDR_MASK) -#define PKA_ECC_GEN_X_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_GEN_X_ADDR_MASK) >> PKA_ECC_GEN_X_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRLA */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRLA_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRLA_VAL_SHIFT (0U) -#define PKA_OP_CTRLA_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRLA_VAL_SHIFT) & PKA_OP_CTRLA_VAL_MASK) -#define PKA_OP_CTRLA_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRLA_VAL_MASK) >> PKA_OP_CTRLA_VAL_SHIFT) - -/* Bitfield definition for register: RSA_TM0 */ -/* - * ADDR (RW) - * - * The starting location of RSA buffer TM0 inside the local 256-bits blocks - */ -#define PKA_RSA_TM0_ADDR_MASK (0x1FFFU) -#define PKA_RSA_TM0_ADDR_SHIFT (0U) -#define PKA_RSA_TM0_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_TM0_ADDR_SHIFT) & PKA_RSA_TM0_ADDR_MASK) -#define PKA_RSA_TM0_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_TM0_ADDR_MASK) >> PKA_RSA_TM0_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_GEN_Y */ -/* - * ADDR (RW) - * - * The address of the ECC generator Y location inside the local 256-bits blocks - */ -#define PKA_ECC_GEN_Y_ADDR_MASK (0x1FFFU) -#define PKA_ECC_GEN_Y_ADDR_SHIFT (0U) -#define PKA_ECC_GEN_Y_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_GEN_Y_ADDR_SHIFT) & PKA_ECC_GEN_Y_ADDR_MASK) -#define PKA_ECC_GEN_Y_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_GEN_Y_ADDR_MASK) >> PKA_ECC_GEN_Y_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRLB */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRLB_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRLB_VAL_SHIFT (0U) -#define PKA_OP_CTRLB_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRLB_VAL_SHIFT) & PKA_OP_CTRLB_VAL_MASK) -#define PKA_OP_CTRLB_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRLB_VAL_MASK) >> PKA_OP_CTRLB_VAL_SHIFT) - -/* Bitfield definition for register: RSA_TM1 */ -/* - * ADDR (RW) - * - * The starting location of RSA buffer TM1 inside the local 256-bits blocks - */ -#define PKA_RSA_TM1_ADDR_MASK (0x1FFFU) -#define PKA_RSA_TM1_ADDR_SHIFT (0U) -#define PKA_RSA_TM1_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_TM1_ADDR_SHIFT) & PKA_RSA_TM1_ADDR_MASK) -#define PKA_RSA_TM1_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_TM1_ADDR_MASK) >> PKA_RSA_TM1_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_PUB_X */ -/* - * ADDR (RW) - * - * The address of the ECC public key X location inside the local 256-bits blocks - */ -#define PKA_ECC_PUB_X_ADDR_MASK (0x1FFFU) -#define PKA_ECC_PUB_X_ADDR_SHIFT (0U) -#define PKA_ECC_PUB_X_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_PUB_X_ADDR_SHIFT) & PKA_ECC_PUB_X_ADDR_MASK) -#define PKA_ECC_PUB_X_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_PUB_X_ADDR_MASK) >> PKA_ECC_PUB_X_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRLC */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRLC_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRLC_VAL_SHIFT (0U) -#define PKA_OP_CTRLC_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRLC_VAL_SHIFT) & PKA_OP_CTRLC_VAL_MASK) -#define PKA_OP_CTRLC_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRLC_VAL_MASK) >> PKA_OP_CTRLC_VAL_SHIFT) - -/* Bitfield definition for register: RSA_O */ -/* - * ADDR (RW) - * - * The starting location of RSA buffer O inside the local 256-bits blocks - */ -#define PKA_RSA_O_ADDR_MASK (0x1FFFU) -#define PKA_RSA_O_ADDR_SHIFT (0U) -#define PKA_RSA_O_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_O_ADDR_SHIFT) & PKA_RSA_O_ADDR_MASK) -#define PKA_RSA_O_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_O_ADDR_MASK) >> PKA_RSA_O_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_PUB_Y */ -/* - * ADDR (RW) - * - * The address of the ECC public key Y location inside the local 256-bits blocks - */ -#define PKA_ECC_PUB_Y_ADDR_MASK (0x1FFFU) -#define PKA_ECC_PUB_Y_ADDR_SHIFT (0U) -#define PKA_ECC_PUB_Y_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_PUB_Y_ADDR_SHIFT) & PKA_ECC_PUB_Y_ADDR_MASK) -#define PKA_ECC_PUB_Y_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_PUB_Y_ADDR_MASK) >> PKA_ECC_PUB_Y_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRLD */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRLD_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRLD_VAL_SHIFT (0U) -#define PKA_OP_CTRLD_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRLD_VAL_SHIFT) & PKA_OP_CTRLD_VAL_MASK) -#define PKA_OP_CTRLD_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRLD_VAL_MASK) >> PKA_OP_CTRLD_VAL_SHIFT) - -/* Bitfield definition for register: RSA_PRIV_KEY */ -/* - * SRC_CHOICE (RW) - * - * Key Choice - * 0: key inside memory. The below ADDR is the src storage loc. - * 1: key from efuse - * 2: key from rng, - */ -#define PKA_RSA_PRIV_KEY_SRC_CHOICE_MASK (0x60000000UL) -#define PKA_RSA_PRIV_KEY_SRC_CHOICE_SHIFT (29U) -#define PKA_RSA_PRIV_KEY_SRC_CHOICE_SET(x) (((uint32_t)(x) << PKA_RSA_PRIV_KEY_SRC_CHOICE_SHIFT) & PKA_RSA_PRIV_KEY_SRC_CHOICE_MASK) -#define PKA_RSA_PRIV_KEY_SRC_CHOICE_GET(x) (((uint32_t)(x) & PKA_RSA_PRIV_KEY_SRC_CHOICE_MASK) >> PKA_RSA_PRIV_KEY_SRC_CHOICE_SHIFT) - -/* - * STR_CHOICE (RW) - * - * Key Store Choice: only active when key is not inside memory - * 0: don't copy key from key management - * 1: copy key to internal memory indicated by the ADDR field in this config register. Then clear this bit and SRC_CHOICE bits stored in internal memory. - */ -#define PKA_RSA_PRIV_KEY_STR_CHOICE_MASK (0x10000000UL) -#define PKA_RSA_PRIV_KEY_STR_CHOICE_SHIFT (28U) -#define PKA_RSA_PRIV_KEY_STR_CHOICE_SET(x) (((uint32_t)(x) << PKA_RSA_PRIV_KEY_STR_CHOICE_SHIFT) & PKA_RSA_PRIV_KEY_STR_CHOICE_MASK) -#define PKA_RSA_PRIV_KEY_STR_CHOICE_GET(x) (((uint32_t)(x) & PKA_RSA_PRIV_KEY_STR_CHOICE_MASK) >> PKA_RSA_PRIV_KEY_STR_CHOICE_SHIFT) - -/* - * ADDR (RW) - * - * The starting location of RSA private key inside the local 256-bits blocks - */ -#define PKA_RSA_PRIV_KEY_ADDR_MASK (0x1FFFU) -#define PKA_RSA_PRIV_KEY_ADDR_SHIFT (0U) -#define PKA_RSA_PRIV_KEY_ADDR_SET(x) (((uint32_t)(x) << PKA_RSA_PRIV_KEY_ADDR_SHIFT) & PKA_RSA_PRIV_KEY_ADDR_MASK) -#define PKA_RSA_PRIV_KEY_ADDR_GET(x) (((uint32_t)(x) & PKA_RSA_PRIV_KEY_ADDR_MASK) >> PKA_RSA_PRIV_KEY_ADDR_SHIFT) - -/* Bitfield definition for register: ECC_PRIV_K */ -/* - * SRC_CHOICE (RW) - * - * Key Choice - * 0: key inside memory. The below ADDR is the src storage loc. - * 1: key from efuse - * 2: key from rng, - */ -#define PKA_ECC_PRIV_K_SRC_CHOICE_MASK (0x60000000UL) -#define PKA_ECC_PRIV_K_SRC_CHOICE_SHIFT (29U) -#define PKA_ECC_PRIV_K_SRC_CHOICE_SET(x) (((uint32_t)(x) << PKA_ECC_PRIV_K_SRC_CHOICE_SHIFT) & PKA_ECC_PRIV_K_SRC_CHOICE_MASK) -#define PKA_ECC_PRIV_K_SRC_CHOICE_GET(x) (((uint32_t)(x) & PKA_ECC_PRIV_K_SRC_CHOICE_MASK) >> PKA_ECC_PRIV_K_SRC_CHOICE_SHIFT) - -/* - * ADDR (RW) - * - * The address of the ECC private key K location inside the local 256-bits blocks - */ -#define PKA_ECC_PRIV_K_ADDR_MASK (0x1FFFU) -#define PKA_ECC_PRIV_K_ADDR_SHIFT (0U) -#define PKA_ECC_PRIV_K_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_PRIV_K_ADDR_SHIFT) & PKA_ECC_PRIV_K_ADDR_MASK) -#define PKA_ECC_PRIV_K_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_PRIV_K_ADDR_MASK) >> PKA_ECC_PRIV_K_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRLE */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRLE_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRLE_VAL_SHIFT (0U) -#define PKA_OP_CTRLE_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRLE_VAL_SHIFT) & PKA_OP_CTRLE_VAL_MASK) -#define PKA_OP_CTRLE_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRLE_VAL_MASK) >> PKA_OP_CTRLE_VAL_SHIFT) - -/* Bitfield definition for register: ECC_GENORD_N */ -/* - * ADDR (RW) - * - * The address of the order N of ECC generator inside the local 256-bits blocks - */ -#define PKA_ECC_GENORD_N_ADDR_MASK (0x1FFFU) -#define PKA_ECC_GENORD_N_ADDR_SHIFT (0U) -#define PKA_ECC_GENORD_N_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_GENORD_N_ADDR_SHIFT) & PKA_ECC_GENORD_N_ADDR_MASK) -#define PKA_ECC_GENORD_N_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_GENORD_N_ADDR_MASK) >> PKA_ECC_GENORD_N_ADDR_SHIFT) - -/* Bitfield definition for register: OP_CTRLF */ -/* - * VAL (RW) - * - * The config words contents - */ -#define PKA_OP_CTRLF_VAL_MASK (0xFFFFFFFFUL) -#define PKA_OP_CTRLF_VAL_SHIFT (0U) -#define PKA_OP_CTRLF_VAL_SET(x) (((uint32_t)(x) << PKA_OP_CTRLF_VAL_SHIFT) & PKA_OP_CTRLF_VAL_MASK) -#define PKA_OP_CTRLF_VAL_GET(x) (((uint32_t)(x) & PKA_OP_CTRLF_VAL_MASK) >> PKA_OP_CTRLF_VAL_SHIFT) - -/* Bitfield definition for register: ECC_R2N_ORDER_N */ -/* - * ADDR (RW) - * - * The address of mod(R*R, N) for the order N of ECC generators inside the local 256-bits blocks - */ -#define PKA_ECC_R2N_ORDER_N_ADDR_MASK (0x1FFFU) -#define PKA_ECC_R2N_ORDER_N_ADDR_SHIFT (0U) -#define PKA_ECC_R2N_ORDER_N_ADDR_SET(x) (((uint32_t)(x) << PKA_ECC_R2N_ORDER_N_ADDR_SHIFT) & PKA_ECC_R2N_ORDER_N_ADDR_MASK) -#define PKA_ECC_R2N_ORDER_N_ADDR_GET(x) (((uint32_t)(x) & PKA_ECC_R2N_ORDER_N_ADDR_MASK) >> PKA_ECC_R2N_ORDER_N_ADDR_SHIFT) - - - - -#endif /* HPM_PKA_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plb_regs.h deleted file mode 100644 index ec88ca1a712..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plb_regs.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLB_H -#define HPM_PLB_H - -typedef struct { - struct { - __RW uint32_t LOOKUP_TABLE[4]; /* 0x0 - 0xC: TYPE A CHN lookup_table 0 */ - __RW uint32_t SW_INJECT; /* 0x10: TYPE A CHN software inject */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - } TYPE_A[8]; - __R uint8_t RESERVED0[768]; /* 0x100 - 0x3FF: Reserved */ - struct { - __RW uint32_t LUT[2]; /* 0x400 - 0x404: TYPE B CHN lookup table 0 */ - __RW uint32_t CMP[4]; /* 0x408 - 0x414: TYPE B CHN data unit cmp0 */ - __RW uint32_t MODE; /* 0x418: TYPE B CHN mode ctrl */ - __RW uint32_t SW_INJECT; /* 0x41C: TYPE B CHN software inject */ - } TYPE_B[8]; -} PLB_Type; - - -/* Bitfield definition for register of struct array TYPE_A: 0 */ -/* - * LOOKUP_TABLE (RW) - * - * using 4 bit trig_in as lookup index. software can program this register as trig_in's true table. - */ -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK (0xFFFFU) -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT (0U) -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) -#define PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_MASK) >> PLB_TYPE_A_LOOKUP_TABLE_LOOKUP_TABLE_SHIFT) - -/* Bitfield definition for register of struct array TYPE_A: SW_INJECT */ -/* - * SW_INJECT (RW) - * - * software can inject value to TYPEA's output - */ -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK (0xFU) -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT (0U) -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) -#define PLB_TYPE_A_SW_INJECT_SW_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_A_SW_INJECT_SW_INJECT_MASK) >> PLB_TYPE_A_SW_INJECT_SW_INJECT_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: 0 */ -/* - * LOOKUP_TABLE (RW) - * - * lut0 and lut1 union as 64bit, consider each 4bit as one slice. then, total 16 slice. slice0 as bit3:0, slice1 as bit7:4...etc. using 4bit trig in as index of slice. the operate sel in data unit of type B channle is decided by which slice value choosed by trig_in - */ -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK (0xFFFFFFFFUL) -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT (0U) -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) -#define PLB_TYPE_B_LUT_LOOKUP_TABLE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_LUT_LOOKUP_TABLE_MASK) >> PLB_TYPE_B_LUT_LOOKUP_TABLE_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: 0 */ -/* - * CMP_VALUE (RW) - * - * cmp value, using as data unit operation - */ -#define PLB_TYPE_B_CMP_CMP_VALUE_MASK (0xFFFFFFFFUL) -#define PLB_TYPE_B_CMP_CMP_VALUE_SHIFT (0U) -#define PLB_TYPE_B_CMP_CMP_VALUE_SET(x) (((uint32_t)(x) << PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) -#define PLB_TYPE_B_CMP_CMP_VALUE_GET(x) (((uint32_t)(x) & PLB_TYPE_B_CMP_CMP_VALUE_MASK) >> PLB_TYPE_B_CMP_CMP_VALUE_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: MODE */ -/* - * OPT_SEL (RW) - * - * operation selection in data unit. - */ -#define PLB_TYPE_B_MODE_OPT_SEL_MASK (0x10000UL) -#define PLB_TYPE_B_MODE_OPT_SEL_SHIFT (16U) -#define PLB_TYPE_B_MODE_OPT_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OPT_SEL_SHIFT) & PLB_TYPE_B_MODE_OPT_SEL_MASK) -#define PLB_TYPE_B_MODE_OPT_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OPT_SEL_MASK) >> PLB_TYPE_B_MODE_OPT_SEL_SHIFT) - -/* - * OUT3_SEL (RW) - * - * trig out 3 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT3_SEL_MASK (0xF000U) -#define PLB_TYPE_B_MODE_OUT3_SEL_SHIFT (12U) -#define PLB_TYPE_B_MODE_OUT3_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT3_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT3_SEL_MASK) >> PLB_TYPE_B_MODE_OUT3_SEL_SHIFT) - -/* - * OUT2_SEL (RW) - * - * trig out 2 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT2_SEL_MASK (0xF00U) -#define PLB_TYPE_B_MODE_OUT2_SEL_SHIFT (8U) -#define PLB_TYPE_B_MODE_OUT2_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT2_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT2_SEL_MASK) >> PLB_TYPE_B_MODE_OUT2_SEL_SHIFT) - -/* - * OUT1_SEL (RW) - * - * trig out 1 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT1_SEL_MASK (0xF0U) -#define PLB_TYPE_B_MODE_OUT1_SEL_SHIFT (4U) -#define PLB_TYPE_B_MODE_OUT1_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT1_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT1_SEL_MASK) >> PLB_TYPE_B_MODE_OUT1_SEL_SHIFT) - -/* - * OUT0_SEL (RW) - * - * trig out 0 output type in current channel - */ -#define PLB_TYPE_B_MODE_OUT0_SEL_MASK (0xFU) -#define PLB_TYPE_B_MODE_OUT0_SEL_SHIFT (0U) -#define PLB_TYPE_B_MODE_OUT0_SEL_SET(x) (((uint32_t)(x) << PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) -#define PLB_TYPE_B_MODE_OUT0_SEL_GET(x) (((uint32_t)(x) & PLB_TYPE_B_MODE_OUT0_SEL_MASK) >> PLB_TYPE_B_MODE_OUT0_SEL_SHIFT) - -/* Bitfield definition for register of struct array TYPE_B: SW_INJECT */ -/* - * SOFTWARE_INJECT (RW) - * - * data unit value can be changed if program this register - */ -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK (0xFFFFFFFFUL) -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT (0U) -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SET(x) (((uint32_t)(x) << PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) -#define PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_GET(x) (((uint32_t)(x) & PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_MASK) >> PLB_TYPE_B_SW_INJECT_SOFTWARE_INJECT_SHIFT) - - - -/* LOOKUP_TABLE register group index macro definition */ -#define PLB_TYPE_A_LOOKUP_TABLE_0 (0UL) -#define PLB_TYPE_A_LOOKUP_TABLE_1 (1UL) -#define PLB_TYPE_A_LOOKUP_TABLE_2 (2UL) -#define PLB_TYPE_A_LOOKUP_TABLE_3 (3UL) - -/* TYPE_A register group index macro definition */ -#define PLB_TYPE_A_0 (0UL) -#define PLB_TYPE_A_1 (1UL) -#define PLB_TYPE_A_2 (2UL) -#define PLB_TYPE_A_3 (3UL) -#define PLB_TYPE_A_4 (4UL) -#define PLB_TYPE_A_5 (5UL) -#define PLB_TYPE_A_6 (6UL) -#define PLB_TYPE_A_7 (7UL) - -/* LUT register group index macro definition */ -#define PLB_TYPE_B_LUT_0 (0UL) -#define PLB_TYPE_B_LUT_1 (1UL) - -/* CMP register group index macro definition */ -#define PLB_TYPE_B_CMP_0 (0UL) -#define PLB_TYPE_B_CMP_1 (1UL) -#define PLB_TYPE_B_CMP_2 (2UL) -#define PLB_TYPE_B_CMP_3 (3UL) - -/* TYPE_B register group index macro definition */ -#define PLB_TYPE_B_0 (0UL) -#define PLB_TYPE_B_1 (1UL) -#define PLB_TYPE_B_2 (2UL) -#define PLB_TYPE_B_3 (3UL) -#define PLB_TYPE_B_4 (4UL) -#define PLB_TYPE_B_5 (5UL) -#define PLB_TYPE_B_6 (6UL) -#define PLB_TYPE_B_7 (7UL) - - -#endif /* HPM_PLB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plic_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plic_regs.h deleted file mode 100644 index eb5a6504d9c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plic_regs.h +++ /dev/null @@ -1,339 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_H -#define HPM_PLIC_H - -typedef struct { - __RW uint32_t FEATURE; /* 0x0: Feature enable register */ - __RW uint32_t PRIORITY[127]; /* 0x4 - 0x1FC: Source priority */ - __R uint8_t RESERVED0[3584]; /* 0x200 - 0xFFF: Reserved */ - __RW uint32_t PENDING[4]; /* 0x1000 - 0x100C: Pending status */ - __R uint8_t RESERVED1[112]; /* 0x1010 - 0x107F: Reserved */ - __R uint32_t TRIGGER[4]; /* 0x1080 - 0x108C: Trigger type */ - __R uint8_t RESERVED2[112]; /* 0x1090 - 0x10FF: Reserved */ - __R uint32_t NUMBER; /* 0x1100: Number of supported interrupt sources and targets */ - __R uint32_t INFO; /* 0x1104: Version and the maximum priority */ - __R uint8_t RESERVED3[3832]; /* 0x1108 - 0x1FFF: Reserved */ - struct { - __RW uint32_t INTEN[4]; /* 0x2000 - 0x200C: machine interrupt enable */ - __R uint8_t RESERVED0[112]; /* 0x2010 - 0x207F: Reserved */ - } TARGETINT[2]; - __R uint8_t RESERVED4[2088704]; /* 0x2100 - 0x1FFFFF: Reserved */ - struct { - __RW uint32_t THRESHOLD; /* 0x200000: Target0 priority threshold */ - __RW uint32_t CLAIM; /* 0x200004: Target claim and complete */ - __R uint8_t RESERVED0[1016]; /* 0x200008 - 0x2003FF: Reserved */ - __RW uint32_t PPS; /* 0x200400: Preempted priority stack */ - __R uint8_t RESERVED1[3068]; /* 0x200404 - 0x200FFF: Reserved */ - } TARGETCONFIG[2]; -} PLIC_Type; - - -/* Bitfield definition for register: FEATURE */ -/* - * VECTORED (RW) - * - * Vector mode enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_VECTORED_MASK (0x2U) -#define PLIC_FEATURE_VECTORED_SHIFT (1U) -#define PLIC_FEATURE_VECTORED_SET(x) (((uint32_t)(x) << PLIC_FEATURE_VECTORED_SHIFT) & PLIC_FEATURE_VECTORED_MASK) -#define PLIC_FEATURE_VECTORED_GET(x) (((uint32_t)(x) & PLIC_FEATURE_VECTORED_MASK) >> PLIC_FEATURE_VECTORED_SHIFT) - -/* - * PREEMPT (RW) - * - * Preemptive priority interrupt enable - * 0: Disabled - * 1: Enabled - */ -#define PLIC_FEATURE_PREEMPT_MASK (0x1U) -#define PLIC_FEATURE_PREEMPT_SHIFT (0U) -#define PLIC_FEATURE_PREEMPT_SET(x) (((uint32_t)(x) << PLIC_FEATURE_PREEMPT_SHIFT) & PLIC_FEATURE_PREEMPT_MASK) -#define PLIC_FEATURE_PREEMPT_GET(x) (((uint32_t)(x) & PLIC_FEATURE_PREEMPT_MASK) >> PLIC_FEATURE_PREEMPT_SHIFT) - -/* Bitfield definition for register array: PRIORITY */ -/* - * PRIORITY (RW) - * - * Interrupt source priority. The valid range of this field is 0-7. - * 0: Never interrupt - * 1-7: Interrupt source priority. The larger the value, the higher the priority. - */ -#define PLIC_PRIORITY_PRIORITY_MASK (0xFFFFFFFFUL) -#define PLIC_PRIORITY_PRIORITY_SHIFT (0U) -#define PLIC_PRIORITY_PRIORITY_SET(x) (((uint32_t)(x) << PLIC_PRIORITY_PRIORITY_SHIFT) & PLIC_PRIORITY_PRIORITY_MASK) -#define PLIC_PRIORITY_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_PRIORITY_PRIORITY_MASK) >> PLIC_PRIORITY_PRIORITY_SHIFT) - -/* Bitfield definition for register array: PENDING */ -/* - * INTERRUPT (RW) - * - * The interrupt pending status of inpterrupt sources. Every interrupt source occupies 1 bit. - */ -#define PLIC_PENDING_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_PENDING_INTERRUPT_SHIFT (0U) -#define PLIC_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_PENDING_INTERRUPT_SHIFT) & PLIC_PENDING_INTERRUPT_MASK) -#define PLIC_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_PENDING_INTERRUPT_MASK) >> PLIC_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register array: TRIGGER */ -/* - * INTERRUPT (RO) - * - * The interrupt trigger type of interrupt sources. Every interrupt source occupies 1 bit. - * 0: Level-triggered interrupt - * 1: Edge-triggered interrupt - */ -#define PLIC_TRIGGER_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TRIGGER_INTERRUPT_SHIFT (0U) -#define PLIC_TRIGGER_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TRIGGER_INTERRUPT_MASK) >> PLIC_TRIGGER_INTERRUPT_SHIFT) - -/* Bitfield definition for register: NUMBER */ -/* - * NUM_TARGET (RO) - * - * The number of supported targets - */ -#define PLIC_NUMBER_NUM_TARGET_MASK (0xFFFF0000UL) -#define PLIC_NUMBER_NUM_TARGET_SHIFT (16U) -#define PLIC_NUMBER_NUM_TARGET_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_TARGET_MASK) >> PLIC_NUMBER_NUM_TARGET_SHIFT) - -/* - * NUM_INTERRUPT (RO) - * - * The number of supported interrupt sources - */ -#define PLIC_NUMBER_NUM_INTERRUPT_MASK (0xFFFFU) -#define PLIC_NUMBER_NUM_INTERRUPT_SHIFT (0U) -#define PLIC_NUMBER_NUM_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_NUMBER_NUM_INTERRUPT_MASK) >> PLIC_NUMBER_NUM_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INFO */ -/* - * MAX_PRIORITY (RO) - * - * The maximum priority supported - */ -#define PLIC_INFO_MAX_PRIORITY_MASK (0xFFFF0000UL) -#define PLIC_INFO_MAX_PRIORITY_SHIFT (16U) -#define PLIC_INFO_MAX_PRIORITY_GET(x) (((uint32_t)(x) & PLIC_INFO_MAX_PRIORITY_MASK) >> PLIC_INFO_MAX_PRIORITY_SHIFT) - -/* - * VERSION (RO) - * - * The version of the PLIC design - */ -#define PLIC_INFO_VERSION_MASK (0xFFFFU) -#define PLIC_INFO_VERSION_SHIFT (0U) -#define PLIC_INFO_VERSION_GET(x) (((uint32_t)(x) & PLIC_INFO_VERSION_MASK) >> PLIC_INFO_VERSION_SHIFT) - -/* Bitfield definition for register of struct array TARGETINT: INTEN0 */ -/* - * INTERRUPT (RW) - * - * The interrupt enable bit for interrupt. Every interrupt source occupies 1 bit. - */ -#define PLIC_TARGETINT_INTEN_INTERRUPT_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_TARGETINT_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) -#define PLIC_TARGETINT_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_TARGETINT_INTEN_INTERRUPT_MASK) >> PLIC_TARGETINT_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: THRESHOLD */ -/* - * THRESHOLD (RW) - * - * Interrupt priority threshold. - */ -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT (0U) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) -#define PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_MASK) >> PLIC_TARGETCONFIG_THRESHOLD_THRESHOLD_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK (0x3FFU) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_MASK) >> PLIC_TARGETCONFIG_CLAIM_INTERRUPT_ID_SHIFT) - -/* Bitfield definition for register of struct array TARGETCONFIG: PPS */ -/* - * PRIORITY_PREEMPTED (RW) - * - * Each bit indicates if the corresponding priority level has been preempted by a higher-priority interrupt. - */ -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK (0xFFFFFFFFUL) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT (0U) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SET(x) (((uint32_t)(x) << PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) -#define PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_GET(x) (((uint32_t)(x) & PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_MASK) >> PLIC_TARGETCONFIG_PPS_PRIORITY_PREEMPTED_SHIFT) - - - -/* PRIORITY register group index macro definition */ -#define PLIC_PRIORITY_PRIORITY1 (0UL) -#define PLIC_PRIORITY_PRIORITY2 (1UL) -#define PLIC_PRIORITY_PRIORITY3 (2UL) -#define PLIC_PRIORITY_PRIORITY4 (3UL) -#define PLIC_PRIORITY_PRIORITY5 (4UL) -#define PLIC_PRIORITY_PRIORITY6 (5UL) -#define PLIC_PRIORITY_PRIORITY7 (6UL) -#define PLIC_PRIORITY_PRIORITY8 (7UL) -#define PLIC_PRIORITY_PRIORITY9 (8UL) -#define PLIC_PRIORITY_PRIORITY10 (9UL) -#define PLIC_PRIORITY_PRIORITY11 (10UL) -#define PLIC_PRIORITY_PRIORITY12 (11UL) -#define PLIC_PRIORITY_PRIORITY13 (12UL) -#define PLIC_PRIORITY_PRIORITY14 (13UL) -#define PLIC_PRIORITY_PRIORITY15 (14UL) -#define PLIC_PRIORITY_PRIORITY16 (15UL) -#define PLIC_PRIORITY_PRIORITY17 (16UL) -#define PLIC_PRIORITY_PRIORITY18 (17UL) -#define PLIC_PRIORITY_PRIORITY19 (18UL) -#define PLIC_PRIORITY_PRIORITY20 (19UL) -#define PLIC_PRIORITY_PRIORITY21 (20UL) -#define PLIC_PRIORITY_PRIORITY22 (21UL) -#define PLIC_PRIORITY_PRIORITY23 (22UL) -#define PLIC_PRIORITY_PRIORITY24 (23UL) -#define PLIC_PRIORITY_PRIORITY25 (24UL) -#define PLIC_PRIORITY_PRIORITY26 (25UL) -#define PLIC_PRIORITY_PRIORITY27 (26UL) -#define PLIC_PRIORITY_PRIORITY28 (27UL) -#define PLIC_PRIORITY_PRIORITY29 (28UL) -#define PLIC_PRIORITY_PRIORITY30 (29UL) -#define PLIC_PRIORITY_PRIORITY31 (30UL) -#define PLIC_PRIORITY_PRIORITY32 (31UL) -#define PLIC_PRIORITY_PRIORITY33 (32UL) -#define PLIC_PRIORITY_PRIORITY34 (33UL) -#define PLIC_PRIORITY_PRIORITY35 (34UL) -#define PLIC_PRIORITY_PRIORITY36 (35UL) -#define PLIC_PRIORITY_PRIORITY37 (36UL) -#define PLIC_PRIORITY_PRIORITY38 (37UL) -#define PLIC_PRIORITY_PRIORITY39 (38UL) -#define PLIC_PRIORITY_PRIORITY40 (39UL) -#define PLIC_PRIORITY_PRIORITY41 (40UL) -#define PLIC_PRIORITY_PRIORITY42 (41UL) -#define PLIC_PRIORITY_PRIORITY43 (42UL) -#define PLIC_PRIORITY_PRIORITY44 (43UL) -#define PLIC_PRIORITY_PRIORITY45 (44UL) -#define PLIC_PRIORITY_PRIORITY46 (45UL) -#define PLIC_PRIORITY_PRIORITY47 (46UL) -#define PLIC_PRIORITY_PRIORITY48 (47UL) -#define PLIC_PRIORITY_PRIORITY49 (48UL) -#define PLIC_PRIORITY_PRIORITY50 (49UL) -#define PLIC_PRIORITY_PRIORITY51 (50UL) -#define PLIC_PRIORITY_PRIORITY52 (51UL) -#define PLIC_PRIORITY_PRIORITY53 (52UL) -#define PLIC_PRIORITY_PRIORITY54 (53UL) -#define PLIC_PRIORITY_PRIORITY55 (54UL) -#define PLIC_PRIORITY_PRIORITY56 (55UL) -#define PLIC_PRIORITY_PRIORITY57 (56UL) -#define PLIC_PRIORITY_PRIORITY58 (57UL) -#define PLIC_PRIORITY_PRIORITY59 (58UL) -#define PLIC_PRIORITY_PRIORITY60 (59UL) -#define PLIC_PRIORITY_PRIORITY61 (60UL) -#define PLIC_PRIORITY_PRIORITY62 (61UL) -#define PLIC_PRIORITY_PRIORITY63 (62UL) -#define PLIC_PRIORITY_PRIORITY64 (63UL) -#define PLIC_PRIORITY_PRIORITY65 (64UL) -#define PLIC_PRIORITY_PRIORITY66 (65UL) -#define PLIC_PRIORITY_PRIORITY67 (66UL) -#define PLIC_PRIORITY_PRIORITY68 (67UL) -#define PLIC_PRIORITY_PRIORITY69 (68UL) -#define PLIC_PRIORITY_PRIORITY70 (69UL) -#define PLIC_PRIORITY_PRIORITY71 (70UL) -#define PLIC_PRIORITY_PRIORITY72 (71UL) -#define PLIC_PRIORITY_PRIORITY73 (72UL) -#define PLIC_PRIORITY_PRIORITY74 (73UL) -#define PLIC_PRIORITY_PRIORITY75 (74UL) -#define PLIC_PRIORITY_PRIORITY76 (75UL) -#define PLIC_PRIORITY_PRIORITY77 (76UL) -#define PLIC_PRIORITY_PRIORITY78 (77UL) -#define PLIC_PRIORITY_PRIORITY79 (78UL) -#define PLIC_PRIORITY_PRIORITY80 (79UL) -#define PLIC_PRIORITY_PRIORITY81 (80UL) -#define PLIC_PRIORITY_PRIORITY82 (81UL) -#define PLIC_PRIORITY_PRIORITY83 (82UL) -#define PLIC_PRIORITY_PRIORITY84 (83UL) -#define PLIC_PRIORITY_PRIORITY85 (84UL) -#define PLIC_PRIORITY_PRIORITY86 (85UL) -#define PLIC_PRIORITY_PRIORITY87 (86UL) -#define PLIC_PRIORITY_PRIORITY88 (87UL) -#define PLIC_PRIORITY_PRIORITY89 (88UL) -#define PLIC_PRIORITY_PRIORITY90 (89UL) -#define PLIC_PRIORITY_PRIORITY91 (90UL) -#define PLIC_PRIORITY_PRIORITY92 (91UL) -#define PLIC_PRIORITY_PRIORITY93 (92UL) -#define PLIC_PRIORITY_PRIORITY94 (93UL) -#define PLIC_PRIORITY_PRIORITY95 (94UL) -#define PLIC_PRIORITY_PRIORITY96 (95UL) -#define PLIC_PRIORITY_PRIORITY97 (96UL) -#define PLIC_PRIORITY_PRIORITY98 (97UL) -#define PLIC_PRIORITY_PRIORITY99 (98UL) -#define PLIC_PRIORITY_PRIORITY100 (99UL) -#define PLIC_PRIORITY_PRIORITY101 (100UL) -#define PLIC_PRIORITY_PRIORITY102 (101UL) -#define PLIC_PRIORITY_PRIORITY103 (102UL) -#define PLIC_PRIORITY_PRIORITY104 (103UL) -#define PLIC_PRIORITY_PRIORITY105 (104UL) -#define PLIC_PRIORITY_PRIORITY106 (105UL) -#define PLIC_PRIORITY_PRIORITY107 (106UL) -#define PLIC_PRIORITY_PRIORITY108 (107UL) -#define PLIC_PRIORITY_PRIORITY109 (108UL) -#define PLIC_PRIORITY_PRIORITY110 (109UL) -#define PLIC_PRIORITY_PRIORITY111 (110UL) -#define PLIC_PRIORITY_PRIORITY112 (111UL) -#define PLIC_PRIORITY_PRIORITY113 (112UL) -#define PLIC_PRIORITY_PRIORITY114 (113UL) -#define PLIC_PRIORITY_PRIORITY115 (114UL) -#define PLIC_PRIORITY_PRIORITY116 (115UL) -#define PLIC_PRIORITY_PRIORITY117 (116UL) -#define PLIC_PRIORITY_PRIORITY118 (117UL) -#define PLIC_PRIORITY_PRIORITY119 (118UL) -#define PLIC_PRIORITY_PRIORITY120 (119UL) -#define PLIC_PRIORITY_PRIORITY121 (120UL) -#define PLIC_PRIORITY_PRIORITY122 (121UL) -#define PLIC_PRIORITY_PRIORITY123 (122UL) -#define PLIC_PRIORITY_PRIORITY124 (123UL) -#define PLIC_PRIORITY_PRIORITY125 (124UL) -#define PLIC_PRIORITY_PRIORITY126 (125UL) -#define PLIC_PRIORITY_PRIORITY127 (126UL) - -/* PENDING register group index macro definition */ -#define PLIC_PENDING_PENDING0 (0UL) -#define PLIC_PENDING_PENDING1 (1UL) -#define PLIC_PENDING_PENDING2 (2UL) -#define PLIC_PENDING_PENDING3 (3UL) - -/* TRIGGER register group index macro definition */ -#define PLIC_TRIGGER_TRIGGER0 (0UL) -#define PLIC_TRIGGER_TRIGGER1 (1UL) -#define PLIC_TRIGGER_TRIGGER2 (2UL) -#define PLIC_TRIGGER_TRIGGER3 (3UL) - -/* INTEN register group index macro definition */ -#define PLIC_TARGETINT_INTEN_INTEN0 (0UL) -#define PLIC_TARGETINT_INTEN_INTEN1 (1UL) -#define PLIC_TARGETINT_INTEN_INTEN2 (2UL) -#define PLIC_TARGETINT_INTEN_INTEN3 (3UL) - -/* TARGETINT register group index macro definition */ -#define PLIC_TARGETINT_TARGET0 (0UL) -#define PLIC_TARGETINT_TARGET1 (1UL) - -/* TARGETCONFIG register group index macro definition */ -#define PLIC_TARGETCONFIG_TARGET0 (0UL) -#define PLIC_TARGETCONFIG_TARGET1 (1UL) - - -#endif /* HPM_PLIC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plic_sw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plic_sw_regs.h deleted file mode 100644 index 998dafa2d57..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_plic_sw_regs.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLIC_SW_H -#define HPM_PLIC_SW_H - -typedef struct { - __R uint8_t RESERVED0[4096]; /* 0x0 - 0xFFF: Reserved */ - __RW uint32_t PENDING; /* 0x1000: Pending status */ - __R uint8_t RESERVED1[4092]; /* 0x1004 - 0x1FFF: Reserved */ - __RW uint32_t INTEN; /* 0x2000: Interrupt enable */ - __R uint8_t RESERVED2[2088960]; /* 0x2004 - 0x200003: Reserved */ - __RW uint32_t CLAIM; /* 0x200004: Claim and complete. */ -} PLIC_SW_Type; - - -/* Bitfield definition for register: PENDING */ -/* - * INTERRUPT (RW) - * - * writing 1 to trigger software interrupt - */ -#define PLIC_SW_PENDING_INTERRUPT_MASK (0x2U) -#define PLIC_SW_PENDING_INTERRUPT_SHIFT (1U) -#define PLIC_SW_PENDING_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_PENDING_INTERRUPT_SHIFT) & PLIC_SW_PENDING_INTERRUPT_MASK) -#define PLIC_SW_PENDING_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_PENDING_INTERRUPT_MASK) >> PLIC_SW_PENDING_INTERRUPT_SHIFT) - -/* Bitfield definition for register: INTEN */ -/* - * INTERRUPT (RW) - * - * enable software interrupt - */ -#define PLIC_SW_INTEN_INTERRUPT_MASK (0x1U) -#define PLIC_SW_INTEN_INTERRUPT_SHIFT (0U) -#define PLIC_SW_INTEN_INTERRUPT_SET(x) (((uint32_t)(x) << PLIC_SW_INTEN_INTERRUPT_SHIFT) & PLIC_SW_INTEN_INTERRUPT_MASK) -#define PLIC_SW_INTEN_INTERRUPT_GET(x) (((uint32_t)(x) & PLIC_SW_INTEN_INTERRUPT_MASK) >> PLIC_SW_INTEN_INTERRUPT_SHIFT) - -/* Bitfield definition for register: CLAIM */ -/* - * INTERRUPT_ID (RW) - * - * On reads, indicating the interrupt source that has being claimed. On writes, indicating the interrupt source that has been handled (completed). - */ -#define PLIC_SW_CLAIM_INTERRUPT_ID_MASK (0x1U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT (0U) -#define PLIC_SW_CLAIM_INTERRUPT_ID_SET(x) (((uint32_t)(x) << PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) -#define PLIC_SW_CLAIM_INTERRUPT_ID_GET(x) (((uint32_t)(x) & PLIC_SW_CLAIM_INTERRUPT_ID_MASK) >> PLIC_SW_CLAIM_INTERRUPT_ID_SHIFT) - - - - -#endif /* HPM_PLIC_SW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pllctlv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pllctlv2_regs.h deleted file mode 100644 index f9bdd046b74..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pllctlv2_regs.h +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PLLCTLV2_H -#define HPM_PLLCTLV2_H - -typedef struct { - __RW uint32_t XTAL; /* 0x0: OSC configuration */ - __R uint8_t RESERVED0[124]; /* 0x4 - 0x7F: Reserved */ - struct { - __RW uint32_t MFI; /* 0x80: PLL0 multiple register */ - __RW uint32_t MFN; /* 0x84: PLL0 fraction numerator register */ - __RW uint32_t MFD; /* 0x88: PLL0 fraction demoninator register */ - __RW uint32_t SS_STEP; /* 0x8C: PLL0 spread spectrum step register */ - __RW uint32_t SS_STOP; /* 0x90: PLL0 spread spectrum stop register */ - __RW uint32_t CONFIG; /* 0x94: PLL0 confguration register */ - __RW uint32_t LOCKTIME; /* 0x98: PLL0 lock time register */ - __RW uint32_t STEPTIME; /* 0x9C: PLL0 step time register */ - __RW uint32_t ADVANCED; /* 0xA0: PLL0 advance configuration register */ - __R uint8_t RESERVED0[28]; /* 0xA4 - 0xBF: Reserved */ - __RW uint32_t DIV[3]; /* 0xC0 - 0xC8: PLL0 divider output 0 configuration register */ - __R uint8_t RESERVED1[52]; /* 0xCC - 0xFF: Reserved */ - } PLL[3]; -} PLLCTLV2_Type; - - -/* Bitfield definition for register: XTAL */ -/* - * BUSY (RO) - * - * Busy flag - * 0: Oscillator is working or shutdown - * 1: Oscillator is changing status - */ -#define PLLCTLV2_XTAL_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_XTAL_BUSY_SHIFT (31U) -#define PLLCTLV2_XTAL_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_BUSY_MASK) >> PLLCTLV2_XTAL_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Crystal oscillator status - * 0: Oscillator is not stable - * 1: Oscillator is stable for use - */ -#define PLLCTLV2_XTAL_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_XTAL_RESPONSE_SHIFT (29U) -#define PLLCTLV2_XTAL_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RESPONSE_MASK) >> PLLCTLV2_XTAL_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Crystal oscillator enable status - * 0: Oscillator is off - * 1: Oscillator is on - */ -#define PLLCTLV2_XTAL_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_XTAL_ENABLE_SHIFT (28U) -#define PLLCTLV2_XTAL_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_ENABLE_MASK) >> PLLCTLV2_XTAL_ENABLE_SHIFT) - -/* - * RAMP_TIME (RW) - * - * Rampup time of XTAL oscillator in cycles of RC24M clock - * 0: 0 cycle - * 1: 1 cycle - * 2: 2 cycle - * 1048575: 1048575 cycles - */ -#define PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) -#define PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) -#define PLLCTLV2_XTAL_RAMP_TIME_SET(x) (((uint32_t)(x) << PLLCTLV2_XTAL_RAMP_TIME_SHIFT) & PLLCTLV2_XTAL_RAMP_TIME_MASK) -#define PLLCTLV2_XTAL_RAMP_TIME_GET(x) (((uint32_t)(x) & PLLCTLV2_XTAL_RAMP_TIME_MASK) >> PLLCTLV2_XTAL_RAMP_TIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFI */ -/* - * BUSY (RO) - * - * Busy flag - * 0: PLL is stable or shutdown - * 1: PLL is changing status - */ -#define PLLCTLV2_PLL_MFI_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_MFI_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_MFI_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_BUSY_MASK) >> PLLCTLV2_PLL_MFI_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * PLL status - * 0: PLL is not stable - * 1: PLL is stable for use - */ -#define PLLCTLV2_PLL_MFI_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_MFI_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_MFI_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_RESPONSE_MASK) >> PLLCTLV2_PLL_MFI_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * PLL enable status - * 0: PLL is off - * 1: PLL is on - */ -#define PLLCTLV2_PLL_MFI_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_MFI_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_MFI_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_ENABLE_MASK) >> PLLCTLV2_PLL_MFI_ENABLE_SHIFT) - -/* - * MFI (RW) - * - * loop back divider of PLL, support from 13 to 42, f=fref*(mfi + mfn/mfd) - * 0-15: invalid - * 16: divide by 16 - * 17: divide by17 - * . . . - * 42: divide by 42 - * 43~:invalid - */ -#define PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) -#define PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) -#define PLLCTLV2_PLL_MFI_MFI_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFI_MFI_SHIFT) & PLLCTLV2_PLL_MFI_MFI_MASK) -#define PLLCTLV2_PLL_MFI_MFI_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFI_MFI_MASK) >> PLLCTLV2_PLL_MFI_MFI_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFN */ -/* - * MFN (RW) - * - * Numeratorof fractional part,f=fref*(mfi + mfn/mfd). This field supports changing while running. - */ -#define PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) -#define PLLCTLV2_PLL_MFN_MFN_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) & PLLCTLV2_PLL_MFN_MFN_MASK) -#define PLLCTLV2_PLL_MFN_MFN_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFN_MFN_MASK) >> PLLCTLV2_PLL_MFN_MFN_SHIFT) - -/* Bitfield definition for register of struct array PLL: MFD */ -/* - * MFD (RW) - * - * Demoninator of fraction part,f=fref*(mfi + mfn/mfd). This field should not be changed during PLL enabled. If changed, change will take efftect when PLL re-enabled. - */ -#define PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) -#define PLLCTLV2_PLL_MFD_MFD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_MFD_MFD_SHIFT) & PLLCTLV2_PLL_MFD_MFD_MASK) -#define PLLCTLV2_PLL_MFD_MFD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_MFD_MFD_MASK) >> PLLCTLV2_PLL_MFD_MFD_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STEP */ -/* - * STEP (RW) - * - * Step of spread spectrum modulator. - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STEP_STEP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) -#define PLLCTLV2_PLL_SS_STEP_STEP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STEP_STEP_MASK) >> PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) - -/* Bitfield definition for register of struct array PLL: SS_STOP */ -/* - * STOP (RW) - * - * Stop point of spread spectrum modulator - * This register should not be changed during PLL and spread spectrum enabled. If changed, new value will take effect when PLL disabled or spread spectrum disabled. - */ -#define PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) -#define PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) -#define PLLCTLV2_PLL_SS_STOP_STOP_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) -#define PLLCTLV2_PLL_SS_STOP_STOP_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_SS_STOP_STOP_MASK) >> PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) - -/* Bitfield definition for register of struct array PLL: CONFIG */ -/* - * SPREAD (RW) - * - * Enable spread spectrum function. This field supports changing during PLL running. - */ -#define PLLCTLV2_PLL_CONFIG_SPREAD_MASK (0x100U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT (8U) -#define PLLCTLV2_PLL_CONFIG_SPREAD_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) -#define PLLCTLV2_PLL_CONFIG_SPREAD_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_SPREAD_MASK) >> PLLCTLV2_PLL_CONFIG_SPREAD_SHIFT) - -/* - * REFSEL (RW) - * - * Select reference clock, This filed support changing while running, but application must take frequency error and jitter into consideration. And if MFN changed before reference switch, application need make sure time is enough for MFN updating. - * 0: XTAL24M - * 1: IRC24M - */ -#define PLLCTLV2_PLL_CONFIG_REFSEL_MASK (0x1U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT (0U) -#define PLLCTLV2_PLL_CONFIG_REFSEL_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) -#define PLLCTLV2_PLL_CONFIG_REFSEL_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_CONFIG_REFSEL_MASK) >> PLLCTLV2_PLL_CONFIG_REFSEL_SHIFT) - -/* Bitfield definition for register of struct array PLL: LOCKTIME */ -/* - * LOCKTIME (RW) - * - * Lock time of PLL in 24M clock cycles, typical value is 2500. If MFI changed during PLL startup, PLL lock time may be longer than this setting. - */ -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) -#define PLLCTLV2_PLL_LOCKTIME_LOCKTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK) >> PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: STEPTIME */ -/* - * STEPTIME (RW) - * - * Step time for MFI on-the-fly change in 24M clock cycles, typical value is 2500. - */ -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) -#define PLLCTLV2_PLL_STEPTIME_STEPTIME_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK) >> PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) - -/* Bitfield definition for register of struct array PLL: ADVANCED */ -/* - * SLOW (RW) - * - * Use slow lock flow, PLL lock expendite is disabled. This mode might be stabler. And software need config LOCKTIME field accordingly. - * 0: fast lock enabled, lock time is 100us - * 1: fast lock disabled, lock time is 400us - */ -#define PLLCTLV2_PLL_ADVANCED_SLOW_MASK (0x10000000UL) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT (28U) -#define PLLCTLV2_PLL_ADVANCED_SLOW_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) -#define PLLCTLV2_PLL_ADVANCED_SLOW_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_SLOW_MASK) >> PLLCTLV2_PLL_ADVANCED_SLOW_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither function - */ -#define PLLCTLV2_PLL_ADVANCED_DITHER_MASK (0x1000000UL) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT (24U) -#define PLLCTLV2_PLL_ADVANCED_DITHER_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) -#define PLLCTLV2_PLL_ADVANCED_DITHER_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_ADVANCED_DITHER_MASK) >> PLLCTLV2_PLL_ADVANCED_DITHER_SHIFT) - -/* Bitfield definition for register of struct array PLL: DIV0 */ -/* - * BUSY (RO) - * - * Busy flag - * 0: divider is working - * 1: divider is changing status - */ -#define PLLCTLV2_PLL_DIV_BUSY_MASK (0x80000000UL) -#define PLLCTLV2_PLL_DIV_BUSY_SHIFT (31U) -#define PLLCTLV2_PLL_DIV_BUSY_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_BUSY_MASK) >> PLLCTLV2_PLL_DIV_BUSY_SHIFT) - -/* - * RESPONSE (RO) - * - * Divider response status - * 0: Divider is not stable - * 1: Divider is stable for use - */ -#define PLLCTLV2_PLL_DIV_RESPONSE_MASK (0x20000000UL) -#define PLLCTLV2_PLL_DIV_RESPONSE_SHIFT (29U) -#define PLLCTLV2_PLL_DIV_RESPONSE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_RESPONSE_MASK) >> PLLCTLV2_PLL_DIV_RESPONSE_SHIFT) - -/* - * ENABLE (RO) - * - * Divider enable status - * 0: Divider is off - * 1: Divider is on - */ -#define PLLCTLV2_PLL_DIV_ENABLE_MASK (0x10000000UL) -#define PLLCTLV2_PLL_DIV_ENABLE_SHIFT (28U) -#define PLLCTLV2_PLL_DIV_ENABLE_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_ENABLE_MASK) >> PLLCTLV2_PLL_DIV_ENABLE_SHIFT) - -/* - * DIV (RW) - * - * Divider factor, divider factor is DIV/5 + 1 - * 0: divide by 1 - * 1: divide by 1.2 - * 2: divide by 1.4 - * . . . - * 63: divide by 13.6 - */ -#define PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) -#define PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) -#define PLLCTLV2_PLL_DIV_DIV_SET(x) (((uint32_t)(x) << PLLCTLV2_PLL_DIV_DIV_SHIFT) & PLLCTLV2_PLL_DIV_DIV_MASK) -#define PLLCTLV2_PLL_DIV_DIV_GET(x) (((uint32_t)(x) & PLLCTLV2_PLL_DIV_DIV_MASK) >> PLLCTLV2_PLL_DIV_DIV_SHIFT) - - - -/* DIV register group index macro definition */ -#define PLLCTLV2_PLL_DIV_DIV0 (0UL) -#define PLLCTLV2_PLL_DIV_DIV1 (1UL) -#define PLLCTLV2_PLL_DIV_DIV2 (2UL) - -/* PLL register group index macro definition */ -#define PLLCTLV2_PLL_PLL0 (0UL) -#define PLLCTLV2_PLL_PLL1 (1UL) -#define PLLCTLV2_PLL_PLL2 (2UL) - - -#endif /* HPM_PLLCTLV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pmon_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pmon_regs.h deleted file mode 100644 index 7e3a0798d2a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pmon_regs.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PMON_H -#define HPM_PMON_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Glitch and clock monitor control */ - __RW uint32_t STATUS; /* 0x4: Glitch and clock monitor status */ - } MONITOR[4]; - __R uint8_t RESERVED0[32]; /* 0x20 - 0x3F: Reserved */ - __RW uint32_t IRQ_FLAG; /* 0x40: */ - __RW uint32_t IRQ_ENABLE; /* 0x44: */ -} PMON_Type; - - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * ACTIVE (RW) - * - * select glitch works in active mode or passve mode. - * 0: passive mode, depends on power glitch destroy DFF value - * 1: active mode, check glitch by DFF chain - */ -#define PMON_MONITOR_CONTROL_ACTIVE_MASK (0x10U) -#define PMON_MONITOR_CONTROL_ACTIVE_SHIFT (4U) -#define PMON_MONITOR_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ACTIVE_SHIFT) & PMON_MONITOR_CONTROL_ACTIVE_MASK) -#define PMON_MONITOR_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ACTIVE_MASK) >> PMON_MONITOR_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable glitch detector - * 0: detector disabled - * 1: detector enabled - */ -#define PMON_MONITOR_CONTROL_ENABLE_MASK (0x1U) -#define PMON_MONITOR_CONTROL_ENABLE_SHIFT (0U) -#define PMON_MONITOR_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << PMON_MONITOR_CONTROL_ENABLE_SHIFT) & PMON_MONITOR_CONTROL_ENABLE_MASK) -#define PMON_MONITOR_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & PMON_MONITOR_CONTROL_ENABLE_MASK) >> PMON_MONITOR_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: STATUS */ -/* - * FLAG (RW) - * - * flag for glitch detected, write 1 to clear this flag - * 0: glitch not detected - * 1: glitch detected - */ -#define PMON_MONITOR_STATUS_FLAG_MASK (0x1U) -#define PMON_MONITOR_STATUS_FLAG_SHIFT (0U) -#define PMON_MONITOR_STATUS_FLAG_SET(x) (((uint32_t)(x) << PMON_MONITOR_STATUS_FLAG_SHIFT) & PMON_MONITOR_STATUS_FLAG_MASK) -#define PMON_MONITOR_STATUS_FLAG_GET(x) (((uint32_t)(x) & PMON_MONITOR_STATUS_FLAG_MASK) >> PMON_MONITOR_STATUS_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_FLAG */ -/* - * FLAG (RW) - * - * interrupt flag, each bit represents for one monitor, write 1 to clear interrupt flag - * 0: no monitor interrupt - * 1: monitor interrupt happened - */ -#define PMON_IRQ_FLAG_FLAG_MASK (0xFU) -#define PMON_IRQ_FLAG_FLAG_SHIFT (0U) -#define PMON_IRQ_FLAG_FLAG_SET(x) (((uint32_t)(x) << PMON_IRQ_FLAG_FLAG_SHIFT) & PMON_IRQ_FLAG_FLAG_MASK) -#define PMON_IRQ_FLAG_FLAG_GET(x) (((uint32_t)(x) & PMON_IRQ_FLAG_FLAG_MASK) >> PMON_IRQ_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * ENABLE (RW) - * - * interrupt enable, each bit represents for one monitor - * 0: monitor interrupt disabled - * 1: monitor interrupt enabled - */ -#define PMON_IRQ_ENABLE_ENABLE_MASK (0xFU) -#define PMON_IRQ_ENABLE_ENABLE_SHIFT (0U) -#define PMON_IRQ_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PMON_IRQ_ENABLE_ENABLE_SHIFT) & PMON_IRQ_ENABLE_ENABLE_MASK) -#define PMON_IRQ_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PMON_IRQ_ENABLE_ENABLE_MASK) >> PMON_IRQ_ENABLE_ENABLE_SHIFT) - - - -/* MONITOR register group index macro definition */ -#define PMON_MONITOR_GLITCH0 (0UL) -#define PMON_MONITOR_GLITCH1 (1UL) -#define PMON_MONITOR_CLOCK0 (2UL) -#define PMON_MONITOR_CLOCK1 (3UL) - - -#endif /* HPM_PMON_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ppi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ppi_regs.h deleted file mode 100644 index 0dc072ea743..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ppi_regs.h +++ /dev/null @@ -1,701 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPI_H -#define HPM_PPI_H - -typedef struct { - __RW uint32_t GLB_CFG; /* 0x0: glb_cfg */ - __RW uint32_t PAD_CFG; /* 0x4: pad_cfg */ - __R uint8_t RESERVED0[12]; /* 0x8 - 0x13: Reserved */ - __RW uint32_t CLKPIN_CFG; /* 0x14: clkpin_cfg */ - __RW uint32_t TM_CFG; /* 0x18: tm_cfg */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - __RW uint32_t IRQ_STS; /* 0x20: irq_sts */ - __RW uint32_t IRQ_EN; /* 0x24: irq_en */ - __R uint8_t RESERVED2[24]; /* 0x28 - 0x3F: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x40: cfg0 */ - __RW uint32_t CFG1; /* 0x44: cfg1 */ - __RW uint32_t CFG2; /* 0x48: cfg2 */ - __RW uint32_t CFG3; /* 0x4C: cfg3 */ - __RW uint32_t CFG4; /* 0x50: cfg4 */ - __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */ - } CS[4]; - __R uint8_t RESERVED3[832]; /* 0xC0 - 0x3FF: Reserved */ - struct { - __RW uint32_t CMD_CFG; /* 0x400: cmd_cfg */ - __RW uint32_t AD_CFG; /* 0x404: ad_cfg */ - __RW uint32_t CTRL_CFG; /* 0x408: ctrl_cfg */ - __R uint8_t RESERVED0[4]; /* 0x40C - 0x40F: Reserved */ - } CMD[64]; -} PPI_Type; - - -/* Bitfield definition for register: GLB_CFG */ -/* - * PAD_OUT_REG_ENJ (RW) - * - * 0: register output, one cycle delay; - * 1: direct output， no delay but may have timing issue - */ -#define PPI_GLB_CFG_PAD_OUT_REG_ENJ_MASK (0x2U) -#define PPI_GLB_CFG_PAD_OUT_REG_ENJ_SHIFT (1U) -#define PPI_GLB_CFG_PAD_OUT_REG_ENJ_SET(x) (((uint32_t)(x) << PPI_GLB_CFG_PAD_OUT_REG_ENJ_SHIFT) & PPI_GLB_CFG_PAD_OUT_REG_ENJ_MASK) -#define PPI_GLB_CFG_PAD_OUT_REG_ENJ_GET(x) (((uint32_t)(x) & PPI_GLB_CFG_PAD_OUT_REG_ENJ_MASK) >> PPI_GLB_CFG_PAD_OUT_REG_ENJ_SHIFT) - -/* - * SOFT_RESET (RW) - * - * software reset - */ -#define PPI_GLB_CFG_SOFT_RESET_MASK (0x1U) -#define PPI_GLB_CFG_SOFT_RESET_SHIFT (0U) -#define PPI_GLB_CFG_SOFT_RESET_SET(x) (((uint32_t)(x) << PPI_GLB_CFG_SOFT_RESET_SHIFT) & PPI_GLB_CFG_SOFT_RESET_MASK) -#define PPI_GLB_CFG_SOFT_RESET_GET(x) (((uint32_t)(x) & PPI_GLB_CFG_SOFT_RESET_MASK) >> PPI_GLB_CFG_SOFT_RESET_SHIFT) - -/* Bitfield definition for register: PAD_CFG */ -/* - * CS_IDLE_ST (RW) - * - * cs pin idle state, default high for active low - */ -#define PPI_PAD_CFG_CS_IDLE_ST_MASK (0xF000000UL) -#define PPI_PAD_CFG_CS_IDLE_ST_SHIFT (24U) -#define PPI_PAD_CFG_CS_IDLE_ST_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_CS_IDLE_ST_SHIFT) & PPI_PAD_CFG_CS_IDLE_ST_MASK) -#define PPI_PAD_CFG_CS_IDLE_ST_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_CS_IDLE_ST_MASK) >> PPI_PAD_CFG_CS_IDLE_ST_SHIFT) - -/* - * DM_PAD_POL (RW) - * - * dm pin polarity - */ -#define PPI_PAD_CFG_DM_PAD_POL_MASK (0xF0000UL) -#define PPI_PAD_CFG_DM_PAD_POL_SHIFT (16U) -#define PPI_PAD_CFG_DM_PAD_POL_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_DM_PAD_POL_SHIFT) & PPI_PAD_CFG_DM_PAD_POL_MASK) -#define PPI_PAD_CFG_DM_PAD_POL_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_DM_PAD_POL_MASK) >> PPI_PAD_CFG_DM_PAD_POL_SHIFT) - -/* - * CTRL_PAD_OE (RW) - * - * the pad output enable signal. 0 for IN; 1 for OUT. - * NOTE: for unused pads, set both ctrl_pad_oe and ctrl_pad_pol to 0 - */ -#define PPI_PAD_CFG_CTRL_PAD_OE_MASK (0xFF00U) -#define PPI_PAD_CFG_CTRL_PAD_OE_SHIFT (8U) -#define PPI_PAD_CFG_CTRL_PAD_OE_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_CTRL_PAD_OE_SHIFT) & PPI_PAD_CFG_CTRL_PAD_OE_MASK) -#define PPI_PAD_CFG_CTRL_PAD_OE_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_CTRL_PAD_OE_MASK) >> PPI_PAD_CFG_CTRL_PAD_OE_SHIFT) - -/* - * CTRL_PAD_POL (RW) - * - * for OUT pad: - * 0: output the value in cmd - * 1: output reversed value in cmd - * for IN pad, defines the signal active value, when ctrl_cfg.io_cfg is set, - * will wait the active value for ready(generally read or write ready) - */ -#define PPI_PAD_CFG_CTRL_PAD_POL_MASK (0xFFU) -#define PPI_PAD_CFG_CTRL_PAD_POL_SHIFT (0U) -#define PPI_PAD_CFG_CTRL_PAD_POL_SET(x) (((uint32_t)(x) << PPI_PAD_CFG_CTRL_PAD_POL_SHIFT) & PPI_PAD_CFG_CTRL_PAD_POL_MASK) -#define PPI_PAD_CFG_CTRL_PAD_POL_GET(x) (((uint32_t)(x) & PPI_PAD_CFG_CTRL_PAD_POL_MASK) >> PPI_PAD_CFG_CTRL_PAD_POL_SHIFT) - -/* Bitfield definition for register: CLKPIN_CFG */ -/* - * CYCLE (RW) - * - * there will be a system counter run from 0 to cycle, - * clk output will be set to high when counter is clk_high, and low when counter is clk_low. - * The output will be system clock if cycle is 0. - * All 4 CS share same clock configuration(one clock pin with configured frequency). - * different CS can be assert at different counter value. - */ -#define PPI_CLKPIN_CFG_CYCLE_MASK (0xF000000UL) -#define PPI_CLKPIN_CFG_CYCLE_SHIFT (24U) -#define PPI_CLKPIN_CFG_CYCLE_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_CYCLE_SHIFT) & PPI_CLKPIN_CFG_CYCLE_MASK) -#define PPI_CLKPIN_CFG_CYCLE_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_CYCLE_MASK) >> PPI_CLKPIN_CFG_CYCLE_SHIFT) - -/* - * HIGH (RW) - * - * clock high numer - */ -#define PPI_CLKPIN_CFG_HIGH_MASK (0xF0000UL) -#define PPI_CLKPIN_CFG_HIGH_SHIFT (16U) -#define PPI_CLKPIN_CFG_HIGH_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_HIGH_SHIFT) & PPI_CLKPIN_CFG_HIGH_MASK) -#define PPI_CLKPIN_CFG_HIGH_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_HIGH_MASK) >> PPI_CLKPIN_CFG_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock low number - */ -#define PPI_CLKPIN_CFG_LOW_MASK (0xF00U) -#define PPI_CLKPIN_CFG_LOW_SHIFT (8U) -#define PPI_CLKPIN_CFG_LOW_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_LOW_SHIFT) & PPI_CLKPIN_CFG_LOW_MASK) -#define PPI_CLKPIN_CFG_LOW_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_LOW_MASK) >> PPI_CLKPIN_CFG_LOW_SHIFT) - -/* - * INVERT (RW) - * - * set to invert clock output - */ -#define PPI_CLKPIN_CFG_INVERT_MASK (0x20U) -#define PPI_CLKPIN_CFG_INVERT_SHIFT (5U) -#define PPI_CLKPIN_CFG_INVERT_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_INVERT_SHIFT) & PPI_CLKPIN_CFG_INVERT_MASK) -#define PPI_CLKPIN_CFG_INVERT_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_INVERT_MASK) >> PPI_CLKPIN_CFG_INVERT_SHIFT) - -/* - * AON (RW) - * - * 0: use clk_gate in cmd sequence for whether output clock - * 1: always enable clock output; - */ -#define PPI_CLKPIN_CFG_AON_MASK (0x2U) -#define PPI_CLKPIN_CFG_AON_SHIFT (1U) -#define PPI_CLKPIN_CFG_AON_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_AON_SHIFT) & PPI_CLKPIN_CFG_AON_MASK) -#define PPI_CLKPIN_CFG_AON_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_AON_MASK) >> PPI_CLKPIN_CFG_AON_SHIFT) - -/* - * EN (RW) - * - * set to enable clock logic - */ -#define PPI_CLKPIN_CFG_EN_MASK (0x1U) -#define PPI_CLKPIN_CFG_EN_SHIFT (0U) -#define PPI_CLKPIN_CFG_EN_SET(x) (((uint32_t)(x) << PPI_CLKPIN_CFG_EN_SHIFT) & PPI_CLKPIN_CFG_EN_MASK) -#define PPI_CLKPIN_CFG_EN_GET(x) (((uint32_t)(x) & PPI_CLKPIN_CFG_EN_MASK) >> PPI_CLKPIN_CFG_EN_SHIFT) - -/* Bitfield definition for register: TM_CFG */ -/* - * TM_EN (RW) - * - * timeout enable. - * if enabled, then if each AHB transfer time exceed tm_cfg clock cycles, will assert irq - */ -#define PPI_TM_CFG_TM_EN_MASK (0x10000UL) -#define PPI_TM_CFG_TM_EN_SHIFT (16U) -#define PPI_TM_CFG_TM_EN_SET(x) (((uint32_t)(x) << PPI_TM_CFG_TM_EN_SHIFT) & PPI_TM_CFG_TM_EN_MASK) -#define PPI_TM_CFG_TM_EN_GET(x) (((uint32_t)(x) & PPI_TM_CFG_TM_EN_MASK) >> PPI_TM_CFG_TM_EN_SHIFT) - -/* - * TM_CFG (RW) - * - * timeout value, max 20us at 200MHz clock - */ -#define PPI_TM_CFG_TM_CFG_MASK (0xFFFU) -#define PPI_TM_CFG_TM_CFG_SHIFT (0U) -#define PPI_TM_CFG_TM_CFG_SET(x) (((uint32_t)(x) << PPI_TM_CFG_TM_CFG_SHIFT) & PPI_TM_CFG_TM_CFG_MASK) -#define PPI_TM_CFG_TM_CFG_GET(x) (((uint32_t)(x) & PPI_TM_CFG_TM_CFG_MASK) >> PPI_TM_CFG_TM_CFG_SHIFT) - -/* Bitfield definition for register: IRQ_STS */ -/* - * IRQ_TMOUT_STS (RW1C) - * - * tiemout interrupt status, write 1 to clear - */ -#define PPI_IRQ_STS_IRQ_TMOUT_STS_MASK (0x1U) -#define PPI_IRQ_STS_IRQ_TMOUT_STS_SHIFT (0U) -#define PPI_IRQ_STS_IRQ_TMOUT_STS_SET(x) (((uint32_t)(x) << PPI_IRQ_STS_IRQ_TMOUT_STS_SHIFT) & PPI_IRQ_STS_IRQ_TMOUT_STS_MASK) -#define PPI_IRQ_STS_IRQ_TMOUT_STS_GET(x) (((uint32_t)(x) & PPI_IRQ_STS_IRQ_TMOUT_STS_MASK) >> PPI_IRQ_STS_IRQ_TMOUT_STS_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * IRQ_TMOUT_EN (RW) - * - * timeout interrupt enable - */ -#define PPI_IRQ_EN_IRQ_TMOUT_EN_MASK (0x1U) -#define PPI_IRQ_EN_IRQ_TMOUT_EN_SHIFT (0U) -#define PPI_IRQ_EN_IRQ_TMOUT_EN_SET(x) (((uint32_t)(x) << PPI_IRQ_EN_IRQ_TMOUT_EN_SHIFT) & PPI_IRQ_EN_IRQ_TMOUT_EN_MASK) -#define PPI_IRQ_EN_IRQ_TMOUT_EN_GET(x) (((uint32_t)(x) & PPI_IRQ_EN_IRQ_TMOUT_EN_MASK) >> PPI_IRQ_EN_IRQ_TMOUT_EN_SHIFT) - -/* Bitfield definition for register of struct array CS: CFG0 */ -/* - * ADDR_END (RW) - * - */ -#define PPI_CS_CFG0_ADDR_END_MASK (0xFFF0000UL) -#define PPI_CS_CFG0_ADDR_END_SHIFT (16U) -#define PPI_CS_CFG0_ADDR_END_SET(x) (((uint32_t)(x) << PPI_CS_CFG0_ADDR_END_SHIFT) & PPI_CS_CFG0_ADDR_END_MASK) -#define PPI_CS_CFG0_ADDR_END_GET(x) (((uint32_t)(x) & PPI_CS_CFG0_ADDR_END_MASK) >> PPI_CS_CFG0_ADDR_END_SHIFT) - -/* - * ADDR_START (RW) - * - * addr_start and addr_end config the address slot for CS0, use high 12bit, - * the minimun slot is 1Mbyte(addr_start==addr_end) - */ -#define PPI_CS_CFG0_ADDR_START_MASK (0xFFFU) -#define PPI_CS_CFG0_ADDR_START_SHIFT (0U) -#define PPI_CS_CFG0_ADDR_START_SET(x) (((uint32_t)(x) << PPI_CS_CFG0_ADDR_START_SHIFT) & PPI_CS_CFG0_ADDR_START_MASK) -#define PPI_CS_CFG0_ADDR_START_GET(x) (((uint32_t)(x) & PPI_CS_CFG0_ADDR_START_MASK) >> PPI_CS_CFG0_ADDR_START_SHIFT) - -/* Bitfield definition for register of struct array CS: CFG1 */ -/* - * ADDR_MASK (RW) - * - * the high AHB address will AND with {cs0_mask[15:0], 16'hFFFF}, - * shift right with addr_shift, then output as real address. - */ -#define PPI_CS_CFG1_ADDR_MASK_MASK (0xFFFF0000UL) -#define PPI_CS_CFG1_ADDR_MASK_SHIFT (16U) -#define PPI_CS_CFG1_ADDR_MASK_SET(x) (((uint32_t)(x) << PPI_CS_CFG1_ADDR_MASK_SHIFT) & PPI_CS_CFG1_ADDR_MASK_MASK) -#define PPI_CS_CFG1_ADDR_MASK_GET(x) (((uint32_t)(x) & PPI_CS_CFG1_ADDR_MASK_MASK) >> PPI_CS_CFG1_ADDR_MASK_SHIFT) - -/* - * ADDR_SHIFT (RW) - * - * gennerally should be configured according to port size, - * 0 for 8bit; 1 for 16bit; 2 for 32bit; - */ -#define PPI_CS_CFG1_ADDR_SHIFT_MASK (0xFU) -#define PPI_CS_CFG1_ADDR_SHIFT_SHIFT (0U) -#define PPI_CS_CFG1_ADDR_SHIFT_SET(x) (((uint32_t)(x) << PPI_CS_CFG1_ADDR_SHIFT_SHIFT) & PPI_CS_CFG1_ADDR_SHIFT_MASK) -#define PPI_CS_CFG1_ADDR_SHIFT_GET(x) (((uint32_t)(x) & PPI_CS_CFG1_ADDR_SHIFT_MASK) >> PPI_CS_CFG1_ADDR_SHIFT_SHIFT) - -/* Bitfield definition for register of struct array CS: CFG2 */ -/* - * CS_SYNC_EN (RW) - * - * set to enable CS pin sync with clock counter. - * Clr if use async mode(no clk pin), or not care the CS start time with clk pin - */ -#define PPI_CS_CFG2_CS_SYNC_EN_MASK (0x10000000UL) -#define PPI_CS_CFG2_CS_SYNC_EN_SHIFT (28U) -#define PPI_CS_CFG2_CS_SYNC_EN_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_CS_SYNC_EN_SHIFT) & PPI_CS_CFG2_CS_SYNC_EN_MASK) -#define PPI_CS_CFG2_CS_SYNC_EN_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_CS_SYNC_EN_MASK) >> PPI_CS_CFG2_CS_SYNC_EN_SHIFT) - -/* - * SYNC_CLK_SEL (RW) - * - * CS assert at when clk_div_cnt equal to sync_clk_sel - */ -#define PPI_CS_CFG2_SYNC_CLK_SEL_MASK (0xF00000UL) -#define PPI_CS_CFG2_SYNC_CLK_SEL_SHIFT (20U) -#define PPI_CS_CFG2_SYNC_CLK_SEL_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_SYNC_CLK_SEL_SHIFT) & PPI_CS_CFG2_SYNC_CLK_SEL_MASK) -#define PPI_CS_CFG2_SYNC_CLK_SEL_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_SYNC_CLK_SEL_MASK) >> PPI_CS_CFG2_SYNC_CLK_SEL_SHIFT) - -/* - * READY_IN_SEL (RW) - * - * 0: use two stage sync; - * 1: use one stage sync - */ -#define PPI_CS_CFG2_READY_IN_SEL_MASK (0x1000U) -#define PPI_CS_CFG2_READY_IN_SEL_SHIFT (12U) -#define PPI_CS_CFG2_READY_IN_SEL_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_READY_IN_SEL_SHIFT) & PPI_CS_CFG2_READY_IN_SEL_MASK) -#define PPI_CS_CFG2_READY_IN_SEL_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_READY_IN_SEL_MASK) >> PPI_CS_CFG2_READY_IN_SEL_SHIFT) - -/* - * INTER_CMD_DLY (RW) - * - * set to none-zero value, will add delay between each command sequence for burst cmd, - * or splited transfer cmd sequence(such as transfer 32bit on 16bit port), - * CS will be de-assert during the delay. - */ -#define PPI_CS_CFG2_INTER_CMD_DLY_MASK (0xF0U) -#define PPI_CS_CFG2_INTER_CMD_DLY_SHIFT (4U) -#define PPI_CS_CFG2_INTER_CMD_DLY_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_INTER_CMD_DLY_SHIFT) & PPI_CS_CFG2_INTER_CMD_DLY_MASK) -#define PPI_CS_CFG2_INTER_CMD_DLY_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_INTER_CMD_DLY_MASK) >> PPI_CS_CFG2_INTER_CMD_DLY_SHIFT) - -/* - * PORT_SIZE (RW) - * - * 00-8bit; 01-16bit; 10-32bit; 11-reserved - */ -#define PPI_CS_CFG2_PORT_SIZE_MASK (0x6U) -#define PPI_CS_CFG2_PORT_SIZE_SHIFT (1U) -#define PPI_CS_CFG2_PORT_SIZE_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_PORT_SIZE_SHIFT) & PPI_CS_CFG2_PORT_SIZE_MASK) -#define PPI_CS_CFG2_PORT_SIZE_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_PORT_SIZE_MASK) >> PPI_CS_CFG2_PORT_SIZE_SHIFT) - -/* - * ENABLE (RW) - * - * CS enable - */ -#define PPI_CS_CFG2_ENABLE_MASK (0x1U) -#define PPI_CS_CFG2_ENABLE_SHIFT (0U) -#define PPI_CS_CFG2_ENABLE_SET(x) (((uint32_t)(x) << PPI_CS_CFG2_ENABLE_SHIFT) & PPI_CS_CFG2_ENABLE_MASK) -#define PPI_CS_CFG2_ENABLE_GET(x) (((uint32_t)(x) & PPI_CS_CFG2_ENABLE_MASK) >> PPI_CS_CFG2_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CS: CFG3 */ -/* - * RCMD_END1 (RW) - * - * sequential read cmd end index - */ -#define PPI_CS_CFG3_RCMD_END1_MASK (0x3F000000UL) -#define PPI_CS_CFG3_RCMD_END1_SHIFT (24U) -#define PPI_CS_CFG3_RCMD_END1_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_END1_SHIFT) & PPI_CS_CFG3_RCMD_END1_MASK) -#define PPI_CS_CFG3_RCMD_END1_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_END1_MASK) >> PPI_CS_CFG3_RCMD_END1_SHIFT) - -/* - * RCMD_START1 (RW) - * - * sequential read cmd start index - */ -#define PPI_CS_CFG3_RCMD_START1_MASK (0x3F0000UL) -#define PPI_CS_CFG3_RCMD_START1_SHIFT (16U) -#define PPI_CS_CFG3_RCMD_START1_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_START1_SHIFT) & PPI_CS_CFG3_RCMD_START1_MASK) -#define PPI_CS_CFG3_RCMD_START1_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_START1_MASK) >> PPI_CS_CFG3_RCMD_START1_SHIFT) - -/* - * RCMD_END0 (RW) - * - * first read cmd end index - */ -#define PPI_CS_CFG3_RCMD_END0_MASK (0x3F00U) -#define PPI_CS_CFG3_RCMD_END0_SHIFT (8U) -#define PPI_CS_CFG3_RCMD_END0_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_END0_SHIFT) & PPI_CS_CFG3_RCMD_END0_MASK) -#define PPI_CS_CFG3_RCMD_END0_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_END0_MASK) >> PPI_CS_CFG3_RCMD_END0_SHIFT) - -/* - * RCMD_START0 (RW) - * - * first read cmd start index - */ -#define PPI_CS_CFG3_RCMD_START0_MASK (0x3FU) -#define PPI_CS_CFG3_RCMD_START0_SHIFT (0U) -#define PPI_CS_CFG3_RCMD_START0_SET(x) (((uint32_t)(x) << PPI_CS_CFG3_RCMD_START0_SHIFT) & PPI_CS_CFG3_RCMD_START0_MASK) -#define PPI_CS_CFG3_RCMD_START0_GET(x) (((uint32_t)(x) & PPI_CS_CFG3_RCMD_START0_MASK) >> PPI_CS_CFG3_RCMD_START0_SHIFT) - -/* Bitfield definition for register of struct array CS: CFG4 */ -/* - * WCMD_END1 (RW) - * - * sequential write cmd end index - */ -#define PPI_CS_CFG4_WCMD_END1_MASK (0x3F000000UL) -#define PPI_CS_CFG4_WCMD_END1_SHIFT (24U) -#define PPI_CS_CFG4_WCMD_END1_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_END1_SHIFT) & PPI_CS_CFG4_WCMD_END1_MASK) -#define PPI_CS_CFG4_WCMD_END1_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_END1_MASK) >> PPI_CS_CFG4_WCMD_END1_SHIFT) - -/* - * WCMD_START1 (RW) - * - * sequential write cmd start index - */ -#define PPI_CS_CFG4_WCMD_START1_MASK (0x3F0000UL) -#define PPI_CS_CFG4_WCMD_START1_SHIFT (16U) -#define PPI_CS_CFG4_WCMD_START1_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_START1_SHIFT) & PPI_CS_CFG4_WCMD_START1_MASK) -#define PPI_CS_CFG4_WCMD_START1_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_START1_MASK) >> PPI_CS_CFG4_WCMD_START1_SHIFT) - -/* - * WCMD_END0 (RW) - * - * first write cmd end index - */ -#define PPI_CS_CFG4_WCMD_END0_MASK (0x3F00U) -#define PPI_CS_CFG4_WCMD_END0_SHIFT (8U) -#define PPI_CS_CFG4_WCMD_END0_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_END0_SHIFT) & PPI_CS_CFG4_WCMD_END0_MASK) -#define PPI_CS_CFG4_WCMD_END0_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_END0_MASK) >> PPI_CS_CFG4_WCMD_END0_SHIFT) - -/* - * WCMD_START0 (RW) - * - * first write cmd start index - */ -#define PPI_CS_CFG4_WCMD_START0_MASK (0x3FU) -#define PPI_CS_CFG4_WCMD_START0_SHIFT (0U) -#define PPI_CS_CFG4_WCMD_START0_SET(x) (((uint32_t)(x) << PPI_CS_CFG4_WCMD_START0_SHIFT) & PPI_CS_CFG4_WCMD_START0_MASK) -#define PPI_CS_CFG4_WCMD_START0_GET(x) (((uint32_t)(x) & PPI_CS_CFG4_WCMD_START0_MASK) >> PPI_CS_CFG4_WCMD_START0_SHIFT) - -/* Bitfield definition for register of struct array CMD: CMD_CFG */ -/* - * CS_VAL (RW) - * - * cs value in current cmd - */ -#define PPI_CMD_CMD_CFG_CS_VAL_MASK (0x20000UL) -#define PPI_CMD_CMD_CFG_CS_VAL_SHIFT (17U) -#define PPI_CMD_CMD_CFG_CS_VAL_SET(x) (((uint32_t)(x) << PPI_CMD_CMD_CFG_CS_VAL_SHIFT) & PPI_CMD_CMD_CFG_CS_VAL_MASK) -#define PPI_CMD_CMD_CFG_CS_VAL_GET(x) (((uint32_t)(x) & PPI_CMD_CMD_CFG_CS_VAL_MASK) >> PPI_CMD_CMD_CFG_CS_VAL_SHIFT) - -/* - * CLK_GATE (RW) - * - * the clock gate enable signal, set to output clock signal - */ -#define PPI_CMD_CMD_CFG_CLK_GATE_MASK (0x10000UL) -#define PPI_CMD_CMD_CFG_CLK_GATE_SHIFT (16U) -#define PPI_CMD_CMD_CFG_CLK_GATE_SET(x) (((uint32_t)(x) << PPI_CMD_CMD_CFG_CLK_GATE_SHIFT) & PPI_CMD_CMD_CFG_CLK_GATE_MASK) -#define PPI_CMD_CMD_CFG_CLK_GATE_GET(x) (((uint32_t)(x) & PPI_CMD_CMD_CFG_CLK_GATE_MASK) >> PPI_CMD_CMD_CFG_CLK_GATE_SHIFT) - -/* - * CYCLE_NUM (RW) - * - * cmd clock cycles - */ -#define PPI_CMD_CMD_CFG_CYCLE_NUM_MASK (0xFFU) -#define PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT (0U) -#define PPI_CMD_CMD_CFG_CYCLE_NUM_SET(x) (((uint32_t)(x) << PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT) & PPI_CMD_CMD_CFG_CYCLE_NUM_MASK) -#define PPI_CMD_CMD_CFG_CYCLE_NUM_GET(x) (((uint32_t)(x) & PPI_CMD_CMD_CFG_CYCLE_NUM_MASK) >> PPI_CMD_CMD_CFG_CYCLE_NUM_SHIFT) - -/* Bitfield definition for register of struct array CMD: AD_CFG */ -/* - * DIR3 (RW) - * - */ -#define PPI_CMD_AD_CFG_DIR3_MASK (0x8000U) -#define PPI_CMD_AD_CFG_DIR3_SHIFT (15U) -#define PPI_CMD_AD_CFG_DIR3_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR3_SHIFT) & PPI_CMD_AD_CFG_DIR3_MASK) -#define PPI_CMD_AD_CFG_DIR3_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR3_MASK) >> PPI_CMD_AD_CFG_DIR3_SHIFT) - -/* - * AD_SEL3 (RW) - * - */ -#define PPI_CMD_AD_CFG_AD_SEL3_MASK (0x4000U) -#define PPI_CMD_AD_CFG_AD_SEL3_SHIFT (14U) -#define PPI_CMD_AD_CFG_AD_SEL3_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL3_SHIFT) & PPI_CMD_AD_CFG_AD_SEL3_MASK) -#define PPI_CMD_AD_CFG_AD_SEL3_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL3_MASK) >> PPI_CMD_AD_CFG_AD_SEL3_SHIFT) - -/* - * BYTE_SEL3 (RW) - * - */ -#define PPI_CMD_AD_CFG_BYTE_SEL3_MASK (0x3000U) -#define PPI_CMD_AD_CFG_BYTE_SEL3_SHIFT (12U) -#define PPI_CMD_AD_CFG_BYTE_SEL3_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL3_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL3_MASK) -#define PPI_CMD_AD_CFG_BYTE_SEL3_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL3_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL3_SHIFT) - -/* - * DIR2 (RW) - * - */ -#define PPI_CMD_AD_CFG_DIR2_MASK (0x800U) -#define PPI_CMD_AD_CFG_DIR2_SHIFT (11U) -#define PPI_CMD_AD_CFG_DIR2_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR2_SHIFT) & PPI_CMD_AD_CFG_DIR2_MASK) -#define PPI_CMD_AD_CFG_DIR2_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR2_MASK) >> PPI_CMD_AD_CFG_DIR2_SHIFT) - -/* - * AD_SEL2 (RW) - * - */ -#define PPI_CMD_AD_CFG_AD_SEL2_MASK (0x400U) -#define PPI_CMD_AD_CFG_AD_SEL2_SHIFT (10U) -#define PPI_CMD_AD_CFG_AD_SEL2_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL2_SHIFT) & PPI_CMD_AD_CFG_AD_SEL2_MASK) -#define PPI_CMD_AD_CFG_AD_SEL2_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL2_MASK) >> PPI_CMD_AD_CFG_AD_SEL2_SHIFT) - -/* - * BYTE_SEL2 (RW) - * - */ -#define PPI_CMD_AD_CFG_BYTE_SEL2_MASK (0x300U) -#define PPI_CMD_AD_CFG_BYTE_SEL2_SHIFT (8U) -#define PPI_CMD_AD_CFG_BYTE_SEL2_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL2_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL2_MASK) -#define PPI_CMD_AD_CFG_BYTE_SEL2_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL2_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL2_SHIFT) - -/* - * DIR1 (RW) - * - */ -#define PPI_CMD_AD_CFG_DIR1_MASK (0x80U) -#define PPI_CMD_AD_CFG_DIR1_SHIFT (7U) -#define PPI_CMD_AD_CFG_DIR1_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR1_SHIFT) & PPI_CMD_AD_CFG_DIR1_MASK) -#define PPI_CMD_AD_CFG_DIR1_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR1_MASK) >> PPI_CMD_AD_CFG_DIR1_SHIFT) - -/* - * AD_SEL1 (RW) - * - */ -#define PPI_CMD_AD_CFG_AD_SEL1_MASK (0x40U) -#define PPI_CMD_AD_CFG_AD_SEL1_SHIFT (6U) -#define PPI_CMD_AD_CFG_AD_SEL1_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL1_SHIFT) & PPI_CMD_AD_CFG_AD_SEL1_MASK) -#define PPI_CMD_AD_CFG_AD_SEL1_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL1_MASK) >> PPI_CMD_AD_CFG_AD_SEL1_SHIFT) - -/* - * BYTE_SEL1 (RW) - * - */ -#define PPI_CMD_AD_CFG_BYTE_SEL1_MASK (0x30U) -#define PPI_CMD_AD_CFG_BYTE_SEL1_SHIFT (4U) -#define PPI_CMD_AD_CFG_BYTE_SEL1_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL1_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL1_MASK) -#define PPI_CMD_AD_CFG_BYTE_SEL1_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL1_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL1_SHIFT) - -/* - * DIR0 (RW) - * - * 0 for OUT; 1 for IN - */ -#define PPI_CMD_AD_CFG_DIR0_MASK (0x8U) -#define PPI_CMD_AD_CFG_DIR0_SHIFT (3U) -#define PPI_CMD_AD_CFG_DIR0_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_DIR0_SHIFT) & PPI_CMD_AD_CFG_DIR0_MASK) -#define PPI_CMD_AD_CFG_DIR0_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_DIR0_MASK) >> PPI_CMD_AD_CFG_DIR0_SHIFT) - -/* - * AD_SEL0 (RW) - * - * 0 for data; 1 for address. - */ -#define PPI_CMD_AD_CFG_AD_SEL0_MASK (0x4U) -#define PPI_CMD_AD_CFG_AD_SEL0_SHIFT (2U) -#define PPI_CMD_AD_CFG_AD_SEL0_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_AD_SEL0_SHIFT) & PPI_CMD_AD_CFG_AD_SEL0_MASK) -#define PPI_CMD_AD_CFG_AD_SEL0_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_AD_SEL0_MASK) >> PPI_CMD_AD_CFG_AD_SEL0_SHIFT) - -/* - * BYTE_SEL0 (RW) - * - * select one of the 4 bytes(11 for 31:24, 10 for 23:16, 01 for 15:8, 00 for 7:0) - */ -#define PPI_CMD_AD_CFG_BYTE_SEL0_MASK (0x3U) -#define PPI_CMD_AD_CFG_BYTE_SEL0_SHIFT (0U) -#define PPI_CMD_AD_CFG_BYTE_SEL0_SET(x) (((uint32_t)(x) << PPI_CMD_AD_CFG_BYTE_SEL0_SHIFT) & PPI_CMD_AD_CFG_BYTE_SEL0_MASK) -#define PPI_CMD_AD_CFG_BYTE_SEL0_GET(x) (((uint32_t)(x) & PPI_CMD_AD_CFG_BYTE_SEL0_MASK) >> PPI_CMD_AD_CFG_BYTE_SEL0_SHIFT) - -/* Bitfield definition for register of struct array CMD: CTRL_CFG */ -/* - * IO_CFG7 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG7_MASK (0x10000000UL) -#define PPI_CMD_CTRL_CFG_IO_CFG7_SHIFT (28U) -#define PPI_CMD_CTRL_CFG_IO_CFG7_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG7_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG7_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG7_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG7_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG7_SHIFT) - -/* - * IO_CFG6 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG6_MASK (0x1000000UL) -#define PPI_CMD_CTRL_CFG_IO_CFG6_SHIFT (24U) -#define PPI_CMD_CTRL_CFG_IO_CFG6_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG6_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG6_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG6_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG6_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG6_SHIFT) - -/* - * IO_CFG5 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG5_MASK (0x100000UL) -#define PPI_CMD_CTRL_CFG_IO_CFG5_SHIFT (20U) -#define PPI_CMD_CTRL_CFG_IO_CFG5_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG5_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG5_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG5_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG5_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG5_SHIFT) - -/* - * IO_CFG4 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG4_MASK (0x10000UL) -#define PPI_CMD_CTRL_CFG_IO_CFG4_SHIFT (16U) -#define PPI_CMD_CTRL_CFG_IO_CFG4_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG4_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG4_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG4_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG4_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG4_SHIFT) - -/* - * IO_CFG3 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG3_MASK (0x1000U) -#define PPI_CMD_CTRL_CFG_IO_CFG3_SHIFT (12U) -#define PPI_CMD_CTRL_CFG_IO_CFG3_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG3_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG3_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG3_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG3_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG3_SHIFT) - -/* - * IO_CFG2 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG2_MASK (0x100U) -#define PPI_CMD_CTRL_CFG_IO_CFG2_SHIFT (8U) -#define PPI_CMD_CTRL_CFG_IO_CFG2_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG2_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG2_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG2_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG2_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG2_SHIFT) - -/* - * IO_CFG1 (RW) - * - */ -#define PPI_CMD_CTRL_CFG_IO_CFG1_MASK (0x10U) -#define PPI_CMD_CTRL_CFG_IO_CFG1_SHIFT (4U) -#define PPI_CMD_CTRL_CFG_IO_CFG1_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG1_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG1_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG1_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG1_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG1_SHIFT) - -/* - * IO_CFG0 (RW) - * - * for OUT, it defines the output value(0 or 1); - * for IN, it defines whether to wait for ready(ready polarity is defined in ctrl_pad_pol) - */ -#define PPI_CMD_CTRL_CFG_IO_CFG0_MASK (0x1U) -#define PPI_CMD_CTRL_CFG_IO_CFG0_SHIFT (0U) -#define PPI_CMD_CTRL_CFG_IO_CFG0_SET(x) (((uint32_t)(x) << PPI_CMD_CTRL_CFG_IO_CFG0_SHIFT) & PPI_CMD_CTRL_CFG_IO_CFG0_MASK) -#define PPI_CMD_CTRL_CFG_IO_CFG0_GET(x) (((uint32_t)(x) & PPI_CMD_CTRL_CFG_IO_CFG0_MASK) >> PPI_CMD_CTRL_CFG_IO_CFG0_SHIFT) - - - -/* CS register group index macro definition */ -#define PPI_CS_0 (0UL) -#define PPI_CS_1 (1UL) -#define PPI_CS_2 (2UL) -#define PPI_CS_3 (3UL) - -/* CMD register group index macro definition */ -#define PPI_CMD_0 (0UL) -#define PPI_CMD_1 (1UL) -#define PPI_CMD_2 (2UL) -#define PPI_CMD_3 (3UL) -#define PPI_CMD_4 (4UL) -#define PPI_CMD_5 (5UL) -#define PPI_CMD_6 (6UL) -#define PPI_CMD_7 (7UL) -#define PPI_CMD_8 (8UL) -#define PPI_CMD_9 (9UL) -#define PPI_CMD_10 (10UL) -#define PPI_CMD_11 (11UL) -#define PPI_CMD_12 (12UL) -#define PPI_CMD_13 (13UL) -#define PPI_CMD_14 (14UL) -#define PPI_CMD_15 (15UL) -#define PPI_CMD_16 (16UL) -#define PPI_CMD_17 (17UL) -#define PPI_CMD_18 (18UL) -#define PPI_CMD_19 (19UL) -#define PPI_CMD_20 (20UL) -#define PPI_CMD_21 (21UL) -#define PPI_CMD_22 (22UL) -#define PPI_CMD_23 (23UL) -#define PPI_CMD_24 (24UL) -#define PPI_CMD_25 (25UL) -#define PPI_CMD_26 (26UL) -#define PPI_CMD_27 (27UL) -#define PPI_CMD_28 (28UL) -#define PPI_CMD_29 (29UL) -#define PPI_CMD_30 (30UL) -#define PPI_CMD_31 (31UL) -#define PPI_CMD_32 (32UL) -#define PPI_CMD_33 (33UL) -#define PPI_CMD_34 (34UL) -#define PPI_CMD_35 (35UL) -#define PPI_CMD_36 (36UL) -#define PPI_CMD_37 (37UL) -#define PPI_CMD_38 (38UL) -#define PPI_CMD_39 (39UL) -#define PPI_CMD_40 (40UL) -#define PPI_CMD_41 (41UL) -#define PPI_CMD_42 (42UL) -#define PPI_CMD_43 (43UL) -#define PPI_CMD_44 (44UL) -#define PPI_CMD_45 (45UL) -#define PPI_CMD_46 (46UL) -#define PPI_CMD_47 (47UL) -#define PPI_CMD_48 (48UL) -#define PPI_CMD_49 (49UL) -#define PPI_CMD_50 (50UL) -#define PPI_CMD_51 (51UL) -#define PPI_CMD_52 (52UL) -#define PPI_CMD_53 (53UL) -#define PPI_CMD_54 (54UL) -#define PPI_CMD_55 (55UL) -#define PPI_CMD_56 (56UL) -#define PPI_CMD_57 (57UL) -#define PPI_CMD_58 (58UL) -#define PPI_CMD_59 (59UL) -#define PPI_CMD_61 (61UL) -#define PPI_CMD_62 (62UL) -#define PPI_CMD_63 (63UL) - - -#endif /* HPM_PPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ppor_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ppor_regs.h deleted file mode 100644 index 32f5f6bcc61..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ppor_regs.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PPOR_H -#define HPM_PPOR_H - -typedef struct { - __W uint32_t RESET_FLAG; /* 0x0: flag indicate reset source */ - __R uint32_t RESET_STATUS; /* 0x4: reset source status */ - __RW uint32_t RESET_HOLD; /* 0x8: reset hold attribute */ - __RW uint32_t RESET_ENABLE; /* 0xC: reset source enable */ - __RW uint32_t RESET_TYPE; /* 0x10: reset type triggered by reset */ - __R uint8_t RESERVED0[8]; /* 0x14 - 0x1B: Reserved */ - __RW uint32_t SOFTWARE_RESET; /* 0x1C: Software reset counter */ -} PPOR_Type; - - -/* Bitfield definition for register: RESET_FLAG */ -/* - * FLAG (W1C) - * - * reset reason of last hard reset, write 1 to clear each bit - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_FLAG_FLAG_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_FLAG_FLAG_SHIFT (0U) -#define PPOR_RESET_FLAG_FLAG_SET(x) (((uint32_t)(x) << PPOR_RESET_FLAG_FLAG_SHIFT) & PPOR_RESET_FLAG_FLAG_MASK) -#define PPOR_RESET_FLAG_FLAG_GET(x) (((uint32_t)(x) & PPOR_RESET_FLAG_FLAG_MASK) >> PPOR_RESET_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: RESET_STATUS */ -/* - * STATUS (RO) - * - * current status of reset sources - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_STATUS_STATUS_SHIFT (0U) -#define PPOR_RESET_STATUS_STATUS_GET(x) (((uint32_t)(x) & PPOR_RESET_STATUS_STATUS_MASK) >> PPOR_RESET_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register: RESET_HOLD */ -/* - * HOLD (RW) - * - * hold arrtibute, when set, SOC keep in reset status until reset source release, or, reset will be released after SOC enter reset status - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_HOLD_HOLD_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_HOLD_HOLD_SHIFT (0U) -#define PPOR_RESET_HOLD_HOLD_SET(x) (((uint32_t)(x) << PPOR_RESET_HOLD_HOLD_SHIFT) & PPOR_RESET_HOLD_HOLD_MASK) -#define PPOR_RESET_HOLD_HOLD_GET(x) (((uint32_t)(x) & PPOR_RESET_HOLD_HOLD_MASK) >> PPOR_RESET_HOLD_HOLD_SHIFT) - -/* Bitfield definition for register: RESET_ENABLE */ -/* - * ENABLE (RW) - * - * enable of reset sources - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_ENABLE_ENABLE_SHIFT (0U) -#define PPOR_RESET_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << PPOR_RESET_ENABLE_ENABLE_SHIFT) & PPOR_RESET_ENABLE_ENABLE_MASK) -#define PPOR_RESET_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & PPOR_RESET_ENABLE_ENABLE_MASK) >> PPOR_RESET_ENABLE_ENABLE_SHIFT) - -/* Bitfield definition for register: RESET_TYPE */ -/* - * TYPE (RW) - * - * reset type of reset sources, 0 for cold reset, all system control setting cleared except debug/fuse/ioc; 1 for hot reset, keep system control setting and debug/fuse/ioc setting, only clear some subsystem - * 0: brownout - * 1: temperature - * 4: debug reset - * 5: jtag soft reset - * 8: cpu0 lockup(not available) - * 9: cpu1 lockup(not available) - * 10: cpu0 request(not available) - * 11: cpu1 request(not available) - * 16: watch dog 0 - * 17: watch dog 1 - * 18: watch dog 2(not available) - * 19: watch dog 3(not available) - * 24: pmic watch dog - * 30: jtag ieee reset - * 31: software - */ -#define PPOR_RESET_TYPE_TYPE_MASK (0xFFFFFFFFUL) -#define PPOR_RESET_TYPE_TYPE_SHIFT (0U) -#define PPOR_RESET_TYPE_TYPE_SET(x) (((uint32_t)(x) << PPOR_RESET_TYPE_TYPE_SHIFT) & PPOR_RESET_TYPE_TYPE_MASK) -#define PPOR_RESET_TYPE_TYPE_GET(x) (((uint32_t)(x) & PPOR_RESET_TYPE_TYPE_MASK) >> PPOR_RESET_TYPE_TYPE_SHIFT) - -/* Bitfield definition for register: SOFTWARE_RESET */ -/* - * COUNTER (RW) - * - * counter decrease in 24MHz and stop at 0, trigger reset when value reach 2, software can write 0 to cancel reset - */ -#define PPOR_SOFTWARE_RESET_COUNTER_MASK (0xFFFFFFFFUL) -#define PPOR_SOFTWARE_RESET_COUNTER_SHIFT (0U) -#define PPOR_SOFTWARE_RESET_COUNTER_SET(x) (((uint32_t)(x) << PPOR_SOFTWARE_RESET_COUNTER_SHIFT) & PPOR_SOFTWARE_RESET_COUNTER_MASK) -#define PPOR_SOFTWARE_RESET_COUNTER_GET(x) (((uint32_t)(x) & PPOR_SOFTWARE_RESET_COUNTER_MASK) >> PPOR_SOFTWARE_RESET_COUNTER_SHIFT) - - - - -#endif /* HPM_PPOR_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_psec_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_psec_regs.h deleted file mode 100644 index a848fbf5d13..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_psec_regs.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PSEC_H -#define HPM_PSEC_H - -typedef struct { - __RW uint32_t SECURE_STATE; /* 0x0: Secure state */ - __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */ - __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */ - __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */ - __R uint32_t EVENT; /* 0x10: Event and escalate status */ - __R uint32_t LIFECYCLE; /* 0x14: Lifecycle */ -} PSEC_Type; - - -/* Bitfield definition for register: SECURE_STATE */ -/* - * ALLOW_NSC (RO) - * - * Non-secure state allow - * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter non-secure state - */ -#define PSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL) -#define PSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U) -#define PSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_NSC_MASK) >> PSEC_SECURE_STATE_ALLOW_NSC_SHIFT) - -/* - * ALLOW_SEC (RO) - * - * Secure state allow - * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state - * 1: system is healthy to enter secure state - */ -#define PSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL) -#define PSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U) -#define PSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_ALLOW_SEC_MASK) >> PSEC_SECURE_STATE_ALLOW_SEC_SHIFT) - -/* - * PMIC_FAIL (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in fail state - * 1: secure state is in fail state - */ -#define PSEC_SECURE_STATE_PMIC_FAIL_MASK (0x80U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SHIFT (7U) -#define PSEC_SECURE_STATE_PMIC_FAIL_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) -#define PSEC_SECURE_STATE_PMIC_FAIL_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_FAIL_MASK) >> PSEC_SECURE_STATE_PMIC_FAIL_SHIFT) - -/* - * PMIC_NSC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in non-secure state - * 1: secure state is in non-secure state - */ -#define PSEC_SECURE_STATE_PMIC_NSC_MASK (0x40U) -#define PSEC_SECURE_STATE_PMIC_NSC_SHIFT (6U) -#define PSEC_SECURE_STATE_PMIC_NSC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_NSC_SHIFT) & PSEC_SECURE_STATE_PMIC_NSC_MASK) -#define PSEC_SECURE_STATE_PMIC_NSC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_NSC_MASK) >> PSEC_SECURE_STATE_PMIC_NSC_SHIFT) - -/* - * PMIC_SEC (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in secure state - * 1: secure state is in secure state - */ -#define PSEC_SECURE_STATE_PMIC_SEC_MASK (0x20U) -#define PSEC_SECURE_STATE_PMIC_SEC_SHIFT (5U) -#define PSEC_SECURE_STATE_PMIC_SEC_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_SEC_SHIFT) & PSEC_SECURE_STATE_PMIC_SEC_MASK) -#define PSEC_SECURE_STATE_PMIC_SEC_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_SEC_MASK) >> PSEC_SECURE_STATE_PMIC_SEC_SHIFT) - -/* - * PMIC_INS (RW) - * - * PMIC secure state one hot indicator - * 0: secure state is not in inspect state - * 1: secure state is in inspect state - */ -#define PSEC_SECURE_STATE_PMIC_INS_MASK (0x10U) -#define PSEC_SECURE_STATE_PMIC_INS_SHIFT (4U) -#define PSEC_SECURE_STATE_PMIC_INS_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_PMIC_INS_SHIFT) & PSEC_SECURE_STATE_PMIC_INS_MASK) -#define PSEC_SECURE_STATE_PMIC_INS_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_PMIC_INS_MASK) >> PSEC_SECURE_STATE_PMIC_INS_SHIFT) - -/* Bitfield definition for register: SECURE_STATE_CONFIG */ -/* - * LOCK (RW) - * - * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset - * 0: not locked, register can be modified - * 1: register locked, write access to the register is ignored - */ -#define PSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U) -#define PSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) -#define PSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> PSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) - -/* - * ALLOW_RESTART (RW) - * - * allow secure state restart from fail state - * 0: restart is not allowed, only hardware reset can recover secure state - * 1: software is allowed to switch to inspect state from fail state - */ -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) -#define PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> PSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) - -/* Bitfield definition for register: VIOLATION_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) -#define PSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> PSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state violations, each bit represents one security event - * 0: event is not a security violation - * 1: event is a security violation - */ -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: ESCALATE_CONFIG */ -/* - * LOCK_NSC (RW) - * - * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) - -/* - * NSC_VIO_CFG (RW) - * - * configuration of non-secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) - -/* - * LOCK_SEC (RW) - * - * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset - * 0: not locked, configuration can be modified - * 1: register locked, write access to the configuration is ignored - */ -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) -#define PSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> PSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) - -/* - * SEC_VIO_CFG (RW) - * - * configuration of secure state escalates, each bit represents one security event - * 0: event is not a security escalate - * 1: event is a security escalate - */ -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) -#define PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> PSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) - -/* Bitfield definition for register: EVENT */ -/* - * EVENT (RO) - * - * local event statue, each bit represents one security event - */ -#define PSEC_EVENT_EVENT_MASK (0xFFFF0000UL) -#define PSEC_EVENT_EVENT_SHIFT (16U) -#define PSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & PSEC_EVENT_EVENT_MASK) >> PSEC_EVENT_EVENT_SHIFT) - -/* - * PMIC_ESC_NSC (RO) - * - * PMIC is escalating non-secure event - */ -#define PSEC_EVENT_PMIC_ESC_NSC_MASK (0x8U) -#define PSEC_EVENT_PMIC_ESC_NSC_SHIFT (3U) -#define PSEC_EVENT_PMIC_ESC_NSC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_NSC_MASK) >> PSEC_EVENT_PMIC_ESC_NSC_SHIFT) - -/* - * PMIC_ESC_SEC (RO) - * - * PMIC is escalting secure event - */ -#define PSEC_EVENT_PMIC_ESC_SEC_MASK (0x4U) -#define PSEC_EVENT_PMIC_ESC_SEC_SHIFT (2U) -#define PSEC_EVENT_PMIC_ESC_SEC_GET(x) (((uint32_t)(x) & PSEC_EVENT_PMIC_ESC_SEC_MASK) >> PSEC_EVENT_PMIC_ESC_SEC_SHIFT) - -/* Bitfield definition for register: LIFECYCLE */ -/* - * LIFECYCLE (RO) - * - * lifecycle status, - * bit7: lifecycle_debate, - * bit6: lifecycle_scribe, - * bit5: lifecycle_no_ret, - * bit4: lifecycle_return, - * bit3: lifecycle_secure, - * bit2: lifecycle_nonsec, - * bit1: lifecycle_create, - * bit0: lifecycle_unknow - */ -#define PSEC_LIFECYCLE_LIFECYCLE_MASK (0xFFU) -#define PSEC_LIFECYCLE_LIFECYCLE_SHIFT (0U) -#define PSEC_LIFECYCLE_LIFECYCLE_GET(x) (((uint32_t)(x) & PSEC_LIFECYCLE_LIFECYCLE_MASK) >> PSEC_LIFECYCLE_LIFECYCLE_SHIFT) - - - - -#endif /* HPM_PSEC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ptpc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ptpc_regs.h deleted file mode 100644 index 5d9609c0c5a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_ptpc_regs.h +++ /dev/null @@ -1,448 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PTPC_H -#define HPM_PTPC_H - -typedef struct { - struct { - __RW uint32_t CTRL0; /* 0x0: Control Register 0 */ - __RW uint32_t CTRL1; /* 0x4: Control Register 1 */ - __R uint32_t TIMEH; /* 0x8: timestamp high */ - __R uint32_t TIMEL; /* 0xC: timestamp low */ - __RW uint32_t TS_UPDTH; /* 0x10: timestamp update high */ - __RW uint32_t TS_UPDTL; /* 0x14: timestamp update low */ - __RW uint32_t ADDEND; /* 0x18: */ - __RW uint32_t TARH; /* 0x1C: */ - __RW uint32_t TARL; /* 0x20: */ - __R uint8_t RESERVED0[8]; /* 0x24 - 0x2B: Reserved */ - __RW uint32_t PPS_CTRL; /* 0x2C: */ - __R uint32_t CAPT_SNAPH; /* 0x30: */ - __RW uint32_t CAPT_SNAPL; /* 0x34: */ - __R uint8_t RESERVED1[4040]; /* 0x38 - 0xFFF: Reserved */ - } PTPC[2]; - __RW uint32_t TIME_SEL; /* 0x2000: */ - __W uint32_t INT_STS; /* 0x2004: */ - __RW uint32_t INT_EN; /* 0x2008: */ - __R uint8_t RESERVED0[4084]; /* 0x200C - 0x2FFF: Reserved */ - __RW uint32_t PTPC_CAN_TS_SEL; /* 0x3000: */ -} PTPC_Type; - - -/* Bitfield definition for register of struct array PTPC: CTRL0 */ -/* - * SUBSEC_DIGITAL_ROLLOVER (RW) - * - * Format for ns counter rollover, - * 1-digital, overflow time 1000000000/0x3B9ACA00 - * 0-binary, overflow time 0x7FFFFFFF - */ -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK (0x200U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT (9U) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) -#define PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_MASK) >> PTPC_PTPC_CTRL0_SUBSEC_DIGITAL_ROLLOVER_SHIFT) - -/* - * CAPT_SNAP_KEEP (RW) - * - * set will keep capture snap till software read capt_snapl. - * If this bit is set, software should read capt_snaph first to avoid wrong result. - * If this bit is cleared, capture result will be updated at each capture event - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK (0x100U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT (8U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_KEEP_SHIFT) - -/* - * CAPT_SNAP_POS_EN (RW) - * - * set will use posege of input capture signal to latch timestamp value - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK (0x80U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT (7U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_POS_EN_SHIFT) - -/* - * CAPT_SNAP_NEG_EN (RW) - * - */ -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK (0x40U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT (6U) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) -#define PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_MASK) >> PTPC_PTPC_CTRL0_CAPT_SNAP_NEG_EN_SHIFT) - -/* - * COMP_EN (RW) - * - * set to enable compare, will be cleared by HW when compare event triggered - */ -#define PTPC_PTPC_CTRL0_COMP_EN_MASK (0x10U) -#define PTPC_PTPC_CTRL0_COMP_EN_SHIFT (4U) -#define PTPC_PTPC_CTRL0_COMP_EN_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_COMP_EN_SHIFT) & PTPC_PTPC_CTRL0_COMP_EN_MASK) -#define PTPC_PTPC_CTRL0_COMP_EN_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_COMP_EN_MASK) >> PTPC_PTPC_CTRL0_COMP_EN_SHIFT) - -/* - * UPDATE_TIMER (WO) - * - * update timer with +/- ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK (0x8U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT (3U) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) -#define PTPC_PTPC_CTRL0_UPDATE_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_UPDATE_TIMER_MASK) >> PTPC_PTPC_CTRL0_UPDATE_TIMER_SHIFT) - -/* - * INIT_TIMER (WO) - * - * initial timer with ts_updt, pulse, clear after set - */ -#define PTPC_PTPC_CTRL0_INIT_TIMER_MASK (0x4U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT (2U) -#define PTPC_PTPC_CTRL0_INIT_TIMER_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) -#define PTPC_PTPC_CTRL0_INIT_TIMER_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_INIT_TIMER_MASK) >> PTPC_PTPC_CTRL0_INIT_TIMER_SHIFT) - -/* - * FINE_COARSE_SEL (RW) - * - * 0: coarse update, ns counter add ss_incr[7:0] each clk - * 1: fine update, ns counter add ss_incr[7:0] each time addend counter overflow - */ -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK (0x2U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT (1U) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) -#define PTPC_PTPC_CTRL0_FINE_COARSE_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_FINE_COARSE_SEL_MASK) >> PTPC_PTPC_CTRL0_FINE_COARSE_SEL_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - */ -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK (0x1U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT (0U) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) -#define PTPC_PTPC_CTRL0_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL0_TIMER_ENABLE_MASK) >> PTPC_PTPC_CTRL0_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CTRL1 */ -/* - * SS_INCR (RW) - * - * constant value used to add ns counter; - * such as for 50MHz timer clock, set it to 8'd20 - */ -#define PTPC_PTPC_CTRL1_SS_INCR_MASK (0xFFU) -#define PTPC_PTPC_CTRL1_SS_INCR_SHIFT (0U) -#define PTPC_PTPC_CTRL1_SS_INCR_SET(x) (((uint32_t)(x) << PTPC_PTPC_CTRL1_SS_INCR_SHIFT) & PTPC_PTPC_CTRL1_SS_INCR_MASK) -#define PTPC_PTPC_CTRL1_SS_INCR_GET(x) (((uint32_t)(x) & PTPC_PTPC_CTRL1_SS_INCR_MASK) >> PTPC_PTPC_CTRL1_SS_INCR_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEH */ -/* - * TIMESTAMP_HIGH (RO) - * - */ -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT (0U) -#define PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_MASK) >> PTPC_PTPC_TIMEH_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TIMEL */ -/* - * TIMESTAMP_LOW (RO) - * - */ -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT (0U) -#define PTPC_PTPC_TIMEL_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TIMEL_TIMESTAMP_LOW_MASK) >> PTPC_PTPC_TIMEL_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTH */ -/* - * SEC_UPDATE (RW) - * - * together with ts_updtl, used to initial or update timestamp - */ -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTH_SEC_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTH_SEC_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTH_SEC_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TS_UPDTL */ -/* - * ADD_SUB (RW) - * - * 1 for sub; 0 for add, used only at update - */ -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK (0x80000000UL) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT (31U) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) -#define PTPC_PTPC_TS_UPDTL_ADD_SUB_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_ADD_SUB_MASK) >> PTPC_PTPC_TS_UPDTL_ADD_SUB_SHIFT) - -/* - * NS_UPDATE (RW) - * - */ -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK (0x7FFFFFFFUL) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT (0U) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_SET(x) (((uint32_t)(x) << PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) -#define PTPC_PTPC_TS_UPDTL_NS_UPDATE_GET(x) (((uint32_t)(x) & PTPC_PTPC_TS_UPDTL_NS_UPDATE_MASK) >> PTPC_PTPC_TS_UPDTL_NS_UPDATE_SHIFT) - -/* Bitfield definition for register of struct array PTPC: ADDEND */ -/* - * ADDEND (RW) - * - * used in fine update mode only - */ -#define PTPC_PTPC_ADDEND_ADDEND_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_ADDEND_ADDEND_SHIFT (0U) -#define PTPC_PTPC_ADDEND_ADDEND_SET(x) (((uint32_t)(x) << PTPC_PTPC_ADDEND_ADDEND_SHIFT) & PTPC_PTPC_ADDEND_ADDEND_MASK) -#define PTPC_PTPC_ADDEND_ADDEND_GET(x) (((uint32_t)(x) & PTPC_PTPC_ADDEND_ADDEND_MASK) >> PTPC_PTPC_ADDEND_ADDEND_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARH */ -/* - * TARGET_TIME_HIGH (RW) - * - * used for generate compare signal if enabled - */ -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT (0U) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) -#define PTPC_PTPC_TARH_TARGET_TIME_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARH_TARGET_TIME_HIGH_MASK) >> PTPC_PTPC_TARH_TARGET_TIME_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: TARL */ -/* - * TARGET_TIME_LOW (RW) - * - */ -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT (0U) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) -#define PTPC_PTPC_TARL_TARGET_TIME_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_TARL_TARGET_TIME_LOW_MASK) >> PTPC_PTPC_TARL_TARGET_TIME_LOW_SHIFT) - -/* Bitfield definition for register of struct array PTPC: PPS_CTRL */ -/* - * PPS_CTRL (RW) - * - */ -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK (0xFU) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT (0U) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_SET(x) (((uint32_t)(x) << PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) -#define PTPC_PTPC_PPS_CTRL_PPS_CTRL_GET(x) (((uint32_t)(x) & PTPC_PTPC_PPS_CTRL_PPS_CTRL_MASK) >> PTPC_PTPC_PPS_CTRL_PPS_CTRL_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPH */ -/* - * CAPT_SNAP_HIGH (RO) - * - * take snapshot for input capture signal, at pos or neg or both; - * the result can be kept or updated at each event according to cfg0.bit8 - */ -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_MASK) >> PTPC_PTPC_CAPT_SNAPH_CAPT_SNAP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array PTPC: CAPT_SNAPL */ -/* - * CAPT_SNAP_LOW (RW) - * - */ -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK (0xFFFFFFFFUL) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT (0U) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) -#define PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_MASK) >> PTPC_PTPC_CAPT_SNAPL_CAPT_SNAP_LOW_SHIFT) - -/* Bitfield definition for register: TIME_SEL */ -/* - * CAN3_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN3_TIME_SEL_MASK (0x8U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT (3U) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN3_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN3_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN3_TIME_SEL_SHIFT) - -/* - * CAN2_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN2_TIME_SEL_MASK (0x4U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT (2U) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN2_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN2_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN2_TIME_SEL_SHIFT) - -/* - * CAN1_TIME_SEL (RW) - * - */ -#define PTPC_TIME_SEL_CAN1_TIME_SEL_MASK (0x2U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT (1U) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN1_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN1_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN1_TIME_SEL_SHIFT) - -/* - * CAN0_TIME_SEL (RW) - * - * set to use ptpc1 for canx - * clr to use ptpc0 for canx - */ -#define PTPC_TIME_SEL_CAN0_TIME_SEL_MASK (0x1U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT (0U) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_SET(x) (((uint32_t)(x) << PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) -#define PTPC_TIME_SEL_CAN0_TIME_SEL_GET(x) (((uint32_t)(x) & PTPC_TIME_SEL_CAN0_TIME_SEL_MASK) >> PTPC_TIME_SEL_CAN0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: INT_STS */ -/* - * COMP_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_STS_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_STS_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS1_SHIFT) & PTPC_INT_STS_COMP_INT_STS1_MASK) -#define PTPC_INT_STS_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS1_MASK) >> PTPC_INT_STS_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_STS_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS1_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_STS_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_STS_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS1_SHIFT) & PTPC_INT_STS_PPS_INT_STS1_MASK) -#define PTPC_INT_STS_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS1_MASK) >> PTPC_INT_STS_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_STS_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_STS_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_COMP_INT_STS0_SHIFT) & PTPC_INT_STS_COMP_INT_STS0_MASK) -#define PTPC_INT_STS_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_COMP_INT_STS0_MASK) >> PTPC_INT_STS_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_STS_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_STS_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_CAPTURE_INT_STS0_MASK) >> PTPC_INT_STS_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (W1C) - * - */ -#define PTPC_INT_STS_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_STS_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_STS_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_STS_PPS_INT_STS0_SHIFT) & PTPC_INT_STS_PPS_INT_STS0_MASK) -#define PTPC_INT_STS_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_STS_PPS_INT_STS0_MASK) >> PTPC_INT_STS_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * COMP_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS1_MASK (0x40000UL) -#define PTPC_INT_EN_COMP_INT_STS1_SHIFT (18U) -#define PTPC_INT_EN_COMP_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS1_SHIFT) & PTPC_INT_EN_COMP_INT_STS1_MASK) -#define PTPC_INT_EN_COMP_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS1_MASK) >> PTPC_INT_EN_COMP_INT_STS1_SHIFT) - -/* - * CAPTURE_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS1_MASK (0x20000UL) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT (17U) -#define PTPC_INT_EN_CAPTURE_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS1_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS1_SHIFT) - -/* - * PPS_INT_STS1 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS1_MASK (0x10000UL) -#define PTPC_INT_EN_PPS_INT_STS1_SHIFT (16U) -#define PTPC_INT_EN_PPS_INT_STS1_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS1_SHIFT) & PTPC_INT_EN_PPS_INT_STS1_MASK) -#define PTPC_INT_EN_PPS_INT_STS1_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS1_MASK) >> PTPC_INT_EN_PPS_INT_STS1_SHIFT) - -/* - * COMP_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_COMP_INT_STS0_MASK (0x4U) -#define PTPC_INT_EN_COMP_INT_STS0_SHIFT (2U) -#define PTPC_INT_EN_COMP_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_COMP_INT_STS0_SHIFT) & PTPC_INT_EN_COMP_INT_STS0_MASK) -#define PTPC_INT_EN_COMP_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_COMP_INT_STS0_MASK) >> PTPC_INT_EN_COMP_INT_STS0_SHIFT) - -/* - * CAPTURE_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_CAPTURE_INT_STS0_MASK (0x2U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT (1U) -#define PTPC_INT_EN_CAPTURE_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) -#define PTPC_INT_EN_CAPTURE_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_CAPTURE_INT_STS0_MASK) >> PTPC_INT_EN_CAPTURE_INT_STS0_SHIFT) - -/* - * PPS_INT_STS0 (RW) - * - */ -#define PTPC_INT_EN_PPS_INT_STS0_MASK (0x1U) -#define PTPC_INT_EN_PPS_INT_STS0_SHIFT (0U) -#define PTPC_INT_EN_PPS_INT_STS0_SET(x) (((uint32_t)(x) << PTPC_INT_EN_PPS_INT_STS0_SHIFT) & PTPC_INT_EN_PPS_INT_STS0_MASK) -#define PTPC_INT_EN_PPS_INT_STS0_GET(x) (((uint32_t)(x) & PTPC_INT_EN_PPS_INT_STS0_MASK) >> PTPC_INT_EN_PPS_INT_STS0_SHIFT) - -/* Bitfield definition for register: PTPC_CAN_TS_SEL */ -/* - * TSU_TBIN3_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK (0xFC000000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT (26U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN3_SEL_SHIFT) - -/* - * TSU_TBIN2_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK (0x3F00000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT (20U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN2_SEL_SHIFT) - -/* - * TSU_TBIN1_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK (0xFC000UL) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT (14U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN1_SEL_SHIFT) - -/* - * TSU_TBIN0_SEL (RW) - * - */ -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK (0x3F00U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT (8U) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SET(x) (((uint32_t)(x) << PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) -#define PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_GET(x) (((uint32_t)(x) & PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_MASK) >> PTPC_PTPC_CAN_TS_SEL_TSU_TBIN0_SEL_SHIFT) - - - -/* PTPC register group index macro definition */ -#define PTPC_PTPC_0 (0UL) -#define PTPC_PTPC_1 (1UL) - - -#endif /* HPM_PTPC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pwmv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pwmv2_regs.h deleted file mode 100644 index bac65481df6..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_pwmv2_regs.h +++ /dev/null @@ -1,1494 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_PWMV2_H -#define HPM_PWMV2_H - -typedef struct { - __RW uint32_t WORK_CTRL0; /* 0x0: */ - __RW uint32_t UNLOCK; /* 0x4: */ - __RW uint32_t SHADOW_VAL[28]; /* 0x8 - 0x74: */ - __RW uint32_t FORCE_MODE; /* 0x78: */ - __RW uint32_t WORK_CTRL1; /* 0x7C: */ - __R uint8_t RESERVED0[128]; /* 0x80 - 0xFF: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x100: */ - __RW uint32_t CFG1; /* 0x104: */ - __RW uint32_t DEAD_AREA; /* 0x108: */ - __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */ - } PWM[8]; - __RW uint32_t TRIGGER_CFG[8]; /* 0x180 - 0x19C: */ - __R uint8_t RESERVED1[80]; /* 0x1A0 - 0x1EF: Reserved */ - __RW uint32_t GLB_CTRL; /* 0x1F0: */ - __RW uint32_t GLB_CTRL2; /* 0x1F4: */ - __R uint8_t RESERVED2[8]; /* 0x1F8 - 0x1FF: Reserved */ - __R uint32_t CNT_RELOAD_WORK[4]; /* 0x200 - 0x20C: */ - __R uint32_t CMP_VAL_WORK[24]; /* 0x210 - 0x26C: */ - __R uint8_t RESERVED3[12]; /* 0x270 - 0x27B: Reserved */ - __R uint32_t FORCE_WORK; /* 0x27C: */ - __R uint8_t RESERVED4[32]; /* 0x280 - 0x29F: Reserved */ - __R uint32_t CNT_VAL[4]; /* 0x2A0 - 0x2AC: */ - __RW uint32_t DAC_VALUE_SV[4]; /* 0x2B0 - 0x2BC: */ - __R uint8_t RESERVED5[64]; /* 0x2C0 - 0x2FF: Reserved */ - __RW uint32_t CAPTURE_POS[8]; /* 0x300 - 0x31C: */ - __R uint8_t RESERVED6[96]; /* 0x320 - 0x37F: Reserved */ - __R uint32_t CAPTURE_NEG[8]; /* 0x380 - 0x39C: */ - __R uint8_t RESERVED7[96]; /* 0x3A0 - 0x3FF: Reserved */ - __RW uint32_t IRQ_STS; /* 0x400: */ - __RW uint32_t IRQ_EN; /* 0x404: */ - __R uint8_t RESERVED8[8]; /* 0x408 - 0x40F: Reserved */ - __W uint32_t IRQ_STS_CMP; /* 0x410: */ - __W uint32_t IRQ_STS_RELOAD; /* 0x414: */ - __W uint32_t IRQ_STS_CAP_POS; /* 0x418: */ - __W uint32_t IRQ_STS_CAP_NEG; /* 0x41C: */ - __W uint32_t IRQ_STS_FAULT; /* 0x420: */ - __W uint32_t IRQ_STS_BURSTEND; /* 0x424: */ - __R uint8_t RESERVED9[8]; /* 0x428 - 0x42F: Reserved */ - __RW uint32_t IRQ_EN_CMP; /* 0x430: */ - __RW uint32_t IRQ_EN_RELOAD; /* 0x434: */ - __RW uint32_t IRQ_EN_CAP_POS; /* 0x438: */ - __RW uint32_t IRQ_EN_CAP_NEG; /* 0x43C: */ - __RW uint32_t IRQ_EN_FAULT; /* 0x440: */ - __RW uint32_t IRQ_EN_BURSTEND; /* 0x444: */ - __R uint8_t RESERVED10[56]; /* 0x448 - 0x47F: Reserved */ - __RW uint32_t DMA_EN; /* 0x480: */ - __R uint8_t RESERVED11[124]; /* 0x484 - 0x4FF: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x500: */ - __RW uint32_t CFG1; /* 0x504: */ - __RW uint32_t CFG2; /* 0x508: */ - __RW uint32_t CFG3; /* 0x50C: */ - } CNT[4]; - __RW uint32_t CNT_GLBCFG; /* 0x540: */ - __R uint8_t RESERVED12[188]; /* 0x544 - 0x5FF: Reserved */ - struct { - __RW uint32_t CFG0; /* 0x600: */ - __RW uint32_t CFG1; /* 0x604: */ - __R uint8_t RESERVED0[8]; /* 0x608 - 0x60F: Reserved */ - } CAL[16]; - __R uint8_t RESERVED13[256]; /* 0x700 - 0x7FF: Reserved */ - struct { - __RW uint32_t CFG; /* 0x800: */ - __R uint8_t RESERVED0[12]; /* 0x804 - 0x80F: Reserved */ - } CMP[24]; -} PWMV2_Type; - - -/* Bitfield definition for register: WORK_CTRL0 */ -/* - * SHADOW_UNLOCK (RW) - * - * write 0x… first to unlock, then set related bits in unlock_sel to unlock following shadow registers(from 0x04 to 0x78), - * otherwise the shadow registers can not be written. - * The shadow registers will be loaded to work registers only when shadow_lock is 1 or lock is not enabled - * This bit can be cleared by set shadow_lock bit in work_ctrl1 - */ -#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK (0x80000000UL) -#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT (31U) -#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SET(x) (((uint32_t)(x) << PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK) -#define PWMV2_WORK_CTRL0_SHADOW_UNLOCK_GET(x) (((uint32_t)(x) & PWMV2_WORK_CTRL0_SHADOW_UNLOCK_MASK) >> PWMV2_WORK_CTRL0_SHADOW_UNLOCK_SHIFT) - -/* Bitfield definition for register: UNLOCK */ -/* - * UNLOCK_BIT (RW) - * - * bit2 to bit 29 for value_shadow, bit30 for force_mode - * the shadow registers can be updated only when related unlock_bit is set; - * this register can only be updated after unlock - */ -#define PWMV2_UNLOCK_UNLOCK_BIT_MASK (0xFFFFFFFFUL) -#define PWMV2_UNLOCK_UNLOCK_BIT_SHIFT (0U) -#define PWMV2_UNLOCK_UNLOCK_BIT_SET(x) (((uint32_t)(x) << PWMV2_UNLOCK_UNLOCK_BIT_SHIFT) & PWMV2_UNLOCK_UNLOCK_BIT_MASK) -#define PWMV2_UNLOCK_UNLOCK_BIT_GET(x) (((uint32_t)(x) & PWMV2_UNLOCK_UNLOCK_BIT_MASK) >> PWMV2_UNLOCK_UNLOCK_BIT_SHIFT) - -/* Bitfield definition for register array: SHADOW_VAL */ -/* - * VALUE (RW) - * - * shadow registers, if used as reload or compare point, shall be 24bit clock cycles plus 1bit half cycle and 7bit high-resolution delay - */ -#define PWMV2_SHADOW_VAL_VALUE_MASK (0xFFFFFFFFUL) -#define PWMV2_SHADOW_VAL_VALUE_SHIFT (0U) -#define PWMV2_SHADOW_VAL_VALUE_SET(x) (((uint32_t)(x) << PWMV2_SHADOW_VAL_VALUE_SHIFT) & PWMV2_SHADOW_VAL_VALUE_MASK) -#define PWMV2_SHADOW_VAL_VALUE_GET(x) (((uint32_t)(x) & PWMV2_SHADOW_VAL_VALUE_MASK) >> PWMV2_SHADOW_VAL_VALUE_SHIFT) - -/* Bitfield definition for register: FORCE_MODE */ -/* - * POLARITY (RW) - * - * one bit for one pwm channel, it's used as shadow register when pwm_cfg0.polarity_opt0 is set. - * output polarity, set to 1 will invert the output(after pwm selection, pair mode, dead area insertion, before force/fault) - */ -#define PWMV2_FORCE_MODE_POLARITY_MASK (0xFF0000UL) -#define PWMV2_FORCE_MODE_POLARITY_SHIFT (16U) -#define PWMV2_FORCE_MODE_POLARITY_SET(x) (((uint32_t)(x) << PWMV2_FORCE_MODE_POLARITY_SHIFT) & PWMV2_FORCE_MODE_POLARITY_MASK) -#define PWMV2_FORCE_MODE_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_FORCE_MODE_POLARITY_MASK) >> PWMV2_FORCE_MODE_POLARITY_SHIFT) - -/* - * FORCE_MODE (RW) - * - * 2bit for each PWM channel(0~7); - * 00: force output 0 - * 01: force output 1 - * 10: output highz(pad_oe_*=0) - * 11: no force - * this field may be changed by software as shadow register , the update time should be defined by chan_cfg.load, only for PWM channels. - */ -#define PWMV2_FORCE_MODE_FORCE_MODE_MASK (0xFFFFU) -#define PWMV2_FORCE_MODE_FORCE_MODE_SHIFT (0U) -#define PWMV2_FORCE_MODE_FORCE_MODE_SET(x) (((uint32_t)(x) << PWMV2_FORCE_MODE_FORCE_MODE_SHIFT) & PWMV2_FORCE_MODE_FORCE_MODE_MASK) -#define PWMV2_FORCE_MODE_FORCE_MODE_GET(x) (((uint32_t)(x) & PWMV2_FORCE_MODE_FORCE_MODE_MASK) >> PWMV2_FORCE_MODE_FORCE_MODE_SHIFT) - -/* Bitfield definition for register: WORK_CTRL1 */ -/* - * SHADOW_LOCK (RW) - * - * one to lock, sofware can't write any shadow registers - * Software have to write 0x…. to work_ctrl0 to clear this bit. - */ -#define PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK (0x80000000UL) -#define PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT (31U) -#define PWMV2_WORK_CTRL1_SHADOW_LOCK_SET(x) (((uint32_t)(x) << PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK) -#define PWMV2_WORK_CTRL1_SHADOW_LOCK_GET(x) (((uint32_t)(x) & PWMV2_WORK_CTRL1_SHADOW_LOCK_MASK) >> PWMV2_WORK_CTRL1_SHADOW_LOCK_SHIFT) - -/* Bitfield definition for register of struct array PWM: CFG0 */ -/* - * TRIG_SEL4 (RW) - * - * for N=0/2/4/6, clear to select 2 compare point(N*2~N*2+1); - * set to select 4 compare point(N*2~N*2+3); - * or use 2 compare point(N*2+2~N*2+3); - * for N=1/3/5/7, this bit is no means, it can work on pair mode, or use 2 compare point (N*2+2~N*2+3); - * assume select ab or abcd, abcd can between 0 and 2T. - * output will be 1 when counter value between a and b; - * if b<=a then output all 0; if b>=(T+a), then output all 1; - */ -#define PWMV2_PWM_CFG0_TRIG_SEL4_MASK (0x1000000UL) -#define PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT (24U) -#define PWMV2_PWM_CFG0_TRIG_SEL4_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK) -#define PWMV2_PWM_CFG0_TRIG_SEL4_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_TRIG_SEL4_MASK) >> PWMV2_PWM_CFG0_TRIG_SEL4_SHIFT) - -/* - * FAULT_SEL_ASYNC (RW) - * - * select from 16bit async fault from pad - */ -#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK (0xF00U) -#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT (8U) -#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) -#define PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_SEL_ASYNC_SHIFT) - -/* - * FAULT_POL_ASYNC (RW) - * - * fault polarity for input fault from pad, 1-active low; 0-active high; - */ -#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK (0x40U) -#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT (6U) -#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) -#define PWMV2_PWM_CFG0_FAULT_POL_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_POL_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_POL_ASYNC_SHIFT) - -/* - * FAULT_EN_ASYNC (RW) - * - * set to enable the input async faults from pad directly - */ -#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK (0x20U) -#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT (5U) -#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK) -#define PWMV2_PWM_CFG0_FAULT_EN_ASYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_ASYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_ASYNC_SHIFT) - -/* - * FAULT_EN_SYNC (RW) - * - * set to enable the input faults from trig_mux(trigger_in[0] for channel0/1, 1 for 23, 2 for 45, 3 for 67) - */ -#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK (0x10U) -#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT (4U) -#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK) -#define PWMV2_PWM_CFG0_FAULT_EN_SYNC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_FAULT_EN_SYNC_MASK) >> PWMV2_PWM_CFG0_FAULT_EN_SYNC_SHIFT) - -/* - * POL_UPDATE_SEL (RW) - * - * used when polarity_opt0 is set, define when to update polarity working register. - * 0: software set work_ctrl1.shadow_lock bit - * 1: update at reload point; - */ -#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK (0x4U) -#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT (2U) -#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) -#define PWMV2_PWM_CFG0_POL_UPDATE_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_POL_UPDATE_SEL_MASK) >> PWMV2_PWM_CFG0_POL_UPDATE_SEL_SHIFT) - -/* - * OUT_POLARITY (RW) - * - * output polarity, set to 1 will invert the output(after pwm selection, pair mode, dead area insertion, before force/fault) - * when polarity_opt0 is set, this bit is controlled by shadow register, can't be writable; read as working register - * use compare channel settings(in cmp_cfg) as shadow register update - */ -#define PWMV2_PWM_CFG0_OUT_POLARITY_MASK (0x2U) -#define PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT (1U) -#define PWMV2_PWM_CFG0_OUT_POLARITY_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK) -#define PWMV2_PWM_CFG0_OUT_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_OUT_POLARITY_MASK) >> PWMV2_PWM_CFG0_OUT_POLARITY_SHIFT) - -/* - * POLARITY_OPT0 (RW) - * - * set to use shadow polarity - */ -#define PWMV2_PWM_CFG0_POLARITY_OPT0_MASK (0x1U) -#define PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT (0U) -#define PWMV2_PWM_CFG0_POLARITY_OPT0_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK) -#define PWMV2_PWM_CFG0_POLARITY_OPT0_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG0_POLARITY_OPT0_MASK) >> PWMV2_PWM_CFG0_POLARITY_OPT0_SHIFT) - -/* Bitfield definition for register of struct array PWM: CFG1 */ -/* - * HIGHZ_EN_N (RW) - * - * 0 to highz pwm outputs(pad_oe*=0), software need set this bit to 1 to enable pwm output - */ -#define PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK (0x10000000UL) -#define PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT (28U) -#define PWMV2_PWM_CFG1_HIGHZ_EN_N_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK) -#define PWMV2_PWM_CFG1_HIGHZ_EN_N_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_HIGHZ_EN_N_MASK) >> PWMV2_PWM_CFG1_HIGHZ_EN_N_SHIFT) - -/* - * FORCE_UPDATE_TIME (RW) - * - * define when to use the shadow register value for working register(force_mode) - * 00: software set work_ctrl1.shadow_lock bit - * 01: use the related counter rld_cmp_sel0 and rld_cmp_sel1, to select one compare point - * 10: related counter reload time(selected by pwm_cnt) - * 11: use force_trig_sel to select one of the input trigger - * NOTE: 00/01 are not recommended since the update time is not controllable, may cause error in complex application. - * 00 is used for initialization or debug, not suggest for real time update - */ -#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK (0xC000000UL) -#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT (26U) -#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) -#define PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_UPDATE_TIME_SHIFT) - -/* - * FAULT_MODE (RW) - * - * 00: force output 0 - * 01: force output 1 - * 1x: output highz(pad_oe_*=0) - */ -#define PWMV2_PWM_CFG1_FAULT_MODE_MASK (0x3000000UL) -#define PWMV2_PWM_CFG1_FAULT_MODE_SHIFT (24U) -#define PWMV2_PWM_CFG1_FAULT_MODE_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_MODE_SHIFT) & PWMV2_PWM_CFG1_FAULT_MODE_MASK) -#define PWMV2_PWM_CFG1_FAULT_MODE_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_MODE_MASK) >> PWMV2_PWM_CFG1_FAULT_MODE_SHIFT) - -/* - * FAULT_REC_TIME (RW) - * - * 00: immediately - * 01: after main counter reload time - * 10: use fault_rec_sel to select one of the input trigger - * 11: software write fault_clear in glb_ctrl2, no effort if pwm_fault is still assert - */ -#define PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK (0xC00000UL) -#define PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT (22U) -#define PWMV2_PWM_CFG1_FAULT_REC_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) -#define PWMV2_PWM_CFG1_FAULT_REC_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_TIME_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_TIME_SHIFT) - -/* - * SW_FORCE_EN (RW) - * - * 0 for hardware force, from trig_mux selected by pwm_force_sel - * 1 for software force, from glb_ctrl.sw_force - */ -#define PWMV2_PWM_CFG1_SW_FORCE_EN_MASK (0x200000UL) -#define PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT (21U) -#define PWMV2_PWM_CFG1_SW_FORCE_EN_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK) -#define PWMV2_PWM_CFG1_SW_FORCE_EN_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_SW_FORCE_EN_MASK) >> PWMV2_PWM_CFG1_SW_FORCE_EN_SHIFT) - -/* - * PAIR_MODE (RW) - * - * if set to 1, PWM work at pair mode, - * pwm_cfg for channel 2m is used for channel 2m+1(m=0,1,2,3), - * except the dead area, which is separate for each channel even in pair mode - * software need set this bit for both channel of one pair, otherwise result unknown. - */ -#define PWMV2_PWM_CFG1_PAIR_MODE_MASK (0x100000UL) -#define PWMV2_PWM_CFG1_PAIR_MODE_SHIFT (20U) -#define PWMV2_PWM_CFG1_PAIR_MODE_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PAIR_MODE_SHIFT) & PWMV2_PWM_CFG1_PAIR_MODE_MASK) -#define PWMV2_PWM_CFG1_PAIR_MODE_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PAIR_MODE_MASK) >> PWMV2_PWM_CFG1_PAIR_MODE_SHIFT) - -/* - * PWM_LOGIC (RW) - * - * valid only for pwm0/2/4/6 when trig_sel4 is set - * 00: ab OR cd; - * 01: ab AND cd; - * 10: ab XOR cd; - * 11: cd - */ -#define PWMV2_PWM_CFG1_PWM_LOGIC_MASK (0xC0000UL) -#define PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT (18U) -#define PWMV2_PWM_CFG1_PWM_LOGIC_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK) -#define PWMV2_PWM_CFG1_PWM_LOGIC_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_LOGIC_MASK) >> PWMV2_PWM_CFG1_PWM_LOGIC_SHIFT) - -/* - * FORCE_TIME (RW) - * - * 00: force immediately - * 01: force at main counter reload time - * 10: force at trig signal selected by force_act_sel - * 11: no force - * the force assert/deassert will happen at the force_time; - * qeo force and value also latched at this time - */ -#define PWMV2_PWM_CFG1_FORCE_TIME_MASK (0x30000UL) -#define PWMV2_PWM_CFG1_FORCE_TIME_SHIFT (16U) -#define PWMV2_PWM_CFG1_FORCE_TIME_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TIME_SHIFT) & PWMV2_PWM_CFG1_FORCE_TIME_MASK) -#define PWMV2_PWM_CFG1_FORCE_TIME_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TIME_MASK) >> PWMV2_PWM_CFG1_FORCE_TIME_SHIFT) - -/* - * FORCE_TRIG_SEL (RW) - * - * select one trigger from 8, should set to pulse in trig_mux, will load shadow register(force)mode) to force_mode_work at this time - */ -#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK (0x7000U) -#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT (12U) -#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) -#define PWMV2_PWM_CFG1_FORCE_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_TRIG_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_TRIG_SEL_SHIFT) - -/* - * FORCE_ACT_SEL (RW) - * - * select one trigger from 8, should set to pulse in trig_mux, will load hw/sw force at this time - */ -#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK (0x700U) -#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT (8U) -#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) -#define PWMV2_PWM_CFG1_FORCE_ACT_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FORCE_ACT_SEL_MASK) >> PWMV2_PWM_CFG1_FORCE_ACT_SEL_SHIFT) - -/* - * PWM_FORCE_SEL (RW) - * - * select one trigger from 8 as force signal, should be level signal, 1 for force active, 0 for no force - */ -#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK (0x70U) -#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT (4U) -#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) -#define PWMV2_PWM_CFG1_PWM_FORCE_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_PWM_FORCE_SEL_MASK) >> PWMV2_PWM_CFG1_PWM_FORCE_SEL_SHIFT) - -/* - * FAULT_REC_SEL (RW) - * - * select one trigger from 8, should set to pulse in trig_mux, used for fault recovery if fault_rec_time is set to 2'b10 - */ -#define PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK (0x7U) -#define PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT (0U) -#define PWMV2_PWM_CFG1_FAULT_REC_SEL_SET(x) (((uint32_t)(x) << PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) -#define PWMV2_PWM_CFG1_FAULT_REC_SEL_GET(x) (((uint32_t)(x) & PWMV2_PWM_CFG1_FAULT_REC_SEL_MASK) >> PWMV2_PWM_CFG1_FAULT_REC_SEL_SHIFT) - -/* Bitfield definition for register of struct array PWM: DEAD_AREA */ -/* - * DEAD_AREA (RW) - * - * 16bit cycle delay plus 8bit hr_delay - * min value is 2 cycles, less than 0x200 will be treated as no dead area; - * NOTE: dead insertion must be configured with pair, that is, for pwm 01/23/45/67. - * otherwise the result maybe UNKNOWN!!! - */ -#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK (0xFFFFFFUL) -#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT (0U) -#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_SET(x) (((uint32_t)(x) << PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK) -#define PWMV2_PWM_DEAD_AREA_DEAD_AREA_GET(x) (((uint32_t)(x) & PWMV2_PWM_DEAD_AREA_DEAD_AREA_MASK) >> PWMV2_PWM_DEAD_AREA_DEAD_AREA_SHIFT) - -/* Bitfield definition for register array: TRIGGER_CFG */ -/* - * TRIGGER_OUT_SEL (RW) - * - * select one from 24 compare result as trigger out, set at compare point, clear at reload point. - */ -#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK (0x1FU) -#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT (0U) -#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SET(x) (((uint32_t)(x) << PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) -#define PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_GET(x) (((uint32_t)(x) & PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_MASK) >> PWMV2_TRIGGER_CFG_TRIGGER_OUT_SEL_SHIFT) - -/* Bitfield definition for register: GLB_CTRL */ -/* - * SW_FORCE (RW) - * - * software write 1 to start software force, if the pwm_cfg.sw_force_en is set, force will take effort - */ -#define PWMV2_GLB_CTRL_SW_FORCE_MASK (0xFF0000UL) -#define PWMV2_GLB_CTRL_SW_FORCE_SHIFT (16U) -#define PWMV2_GLB_CTRL_SW_FORCE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_SW_FORCE_SHIFT) & PWMV2_GLB_CTRL_SW_FORCE_MASK) -#define PWMV2_GLB_CTRL_SW_FORCE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_SW_FORCE_MASK) >> PWMV2_GLB_CTRL_SW_FORCE_SHIFT) - -/* - * OUTPUT_DELAY (RW) - * - * add delay after dead_area insertiong logic, for hr_pwm - */ -#define PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK (0x300U) -#define PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT (8U) -#define PWMV2_GLB_CTRL_OUTPUT_DELAY_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) -#define PWMV2_GLB_CTRL_OUTPUT_DELAY_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_OUTPUT_DELAY_MASK) >> PWMV2_GLB_CTRL_OUTPUT_DELAY_SHIFT) - -/* - * HR_PWM_EN (RW) - * - * set to enable hr pwm, clear to bypass delay chain. - */ -#define PWMV2_GLB_CTRL_HR_PWM_EN_MASK (0x10U) -#define PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT (4U) -#define PWMV2_GLB_CTRL_HR_PWM_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK) -#define PWMV2_GLB_CTRL_HR_PWM_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_HR_PWM_EN_MASK) >> PWMV2_GLB_CTRL_HR_PWM_EN_SHIFT) - -/* - * FRAC_DISABLE (RW) - * - * set to disable bit[7:0] in DAC value when Calculation Unit use it. - */ -#define PWMV2_GLB_CTRL_FRAC_DISABLE_MASK (0x8U) -#define PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT (3U) -#define PWMV2_GLB_CTRL_FRAC_DISABLE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK) -#define PWMV2_GLB_CTRL_FRAC_DISABLE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL_FRAC_DISABLE_MASK) >> PWMV2_GLB_CTRL_FRAC_DISABLE_SHIFT) - -/* Bitfield definition for register: GLB_CTRL2 */ -/* - * DAC_SW_MODE (RW) - * - * set for software DAC mode, software can write dac_value*_sv directly, and dac_valid from moto system is ignored - */ -#define PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK (0xF000000UL) -#define PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT (24U) -#define PWMV2_GLB_CTRL2_DAC_SW_MODE_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK) -#define PWMV2_GLB_CTRL2_DAC_SW_MODE_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DAC_SW_MODE_MASK) >> PWMV2_GLB_CTRL2_DAC_SW_MODE_SHIFT) - -/* - * DEBUG_IN_EN (RW) - * - * set to enable debug_in signal as fault signal, generally disable pwm output - */ -#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK (0x200000UL) -#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT (21U) -#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK) -#define PWMV2_GLB_CTRL2_DEBUG_IN_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_DEBUG_IN_EN_MASK) >> PWMV2_GLB_CTRL2_DEBUG_IN_EN_SHIFT) - -/* - * FAULT_CLEAR (RW) - * - * software write 1 to clear fault event if pwm_cfg.fault_rec_time is 2'b11. - * software need to clear it after the fault signal is de-assert and before next fault - * one bit for one pwm channel - */ -#define PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK (0xFF00U) -#define PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT (8U) -#define PWMV2_GLB_CTRL2_FAULT_CLEAR_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK) -#define PWMV2_GLB_CTRL2_FAULT_CLEAR_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_FAULT_CLEAR_MASK) >> PWMV2_GLB_CTRL2_FAULT_CLEAR_SHIFT) - -/* - * SHADOW_LOCK_EN (RW) - * - * enable shadow_lock feature, if cleared, shadow_lock will be always 0 - */ -#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK (0x1U) -#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT (0U) -#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SET(x) (((uint32_t)(x) << PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK) -#define PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_GET(x) (((uint32_t)(x) & PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_MASK) >> PWMV2_GLB_CTRL2_SHADOW_LOCK_EN_SHIFT) - -/* Bitfield definition for register array: CNT_RELOAD_WORK */ -/* - * VALUE (RO) - * - * counter0 reload working register - */ -#define PWMV2_CNT_RELOAD_WORK_VALUE_MASK (0xFFFFFFFFUL) -#define PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT (0U) -#define PWMV2_CNT_RELOAD_WORK_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CNT_RELOAD_WORK_VALUE_MASK) >> PWMV2_CNT_RELOAD_WORK_VALUE_SHIFT) - -/* Bitfield definition for register array: CMP_VAL_WORK */ -/* - * VALUE (RO) - * - * compare point working register - */ -#define PWMV2_CMP_VAL_WORK_VALUE_MASK (0xFFFFFFFFUL) -#define PWMV2_CMP_VAL_WORK_VALUE_SHIFT (0U) -#define PWMV2_CMP_VAL_WORK_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CMP_VAL_WORK_VALUE_MASK) >> PWMV2_CMP_VAL_WORK_VALUE_SHIFT) - -/* Bitfield definition for register: FORCE_WORK */ -/* - * OUT_POLARITY (RO) - * - * force working register - */ -#define PWMV2_FORCE_WORK_OUT_POLARITY_MASK (0xFF0000UL) -#define PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT (16U) -#define PWMV2_FORCE_WORK_OUT_POLARITY_GET(x) (((uint32_t)(x) & PWMV2_FORCE_WORK_OUT_POLARITY_MASK) >> PWMV2_FORCE_WORK_OUT_POLARITY_SHIFT) - -/* - * FORCE_MODE (RO) - * - * force_mode work register - */ -#define PWMV2_FORCE_WORK_FORCE_MODE_MASK (0xFFFFU) -#define PWMV2_FORCE_WORK_FORCE_MODE_SHIFT (0U) -#define PWMV2_FORCE_WORK_FORCE_MODE_GET(x) (((uint32_t)(x) & PWMV2_FORCE_WORK_FORCE_MODE_MASK) >> PWMV2_FORCE_WORK_FORCE_MODE_SHIFT) - -/* Bitfield definition for register array: CNT_VAL */ -/* - * VALUE (RO) - * - * main counter value - */ -#define PWMV2_CNT_VAL_VALUE_MASK (0xFFFFFFFFUL) -#define PWMV2_CNT_VAL_VALUE_SHIFT (0U) -#define PWMV2_CNT_VAL_VALUE_GET(x) (((uint32_t)(x) & PWMV2_CNT_VAL_VALUE_MASK) >> PWMV2_CNT_VAL_VALUE_SHIFT) - -/* Bitfield definition for register array: DAC_VALUE_SV */ -/* - * VALUE (RW) - * - * save dac0_value when dac0_valid if dac_sw_mode is 0; - * software write dac_value directly if dac_sw_mode is 1 - */ -#define PWMV2_DAC_VALUE_SV_VALUE_MASK (0xFFFFFFFFUL) -#define PWMV2_DAC_VALUE_SV_VALUE_SHIFT (0U) -#define PWMV2_DAC_VALUE_SV_VALUE_SET(x) (((uint32_t)(x) << PWMV2_DAC_VALUE_SV_VALUE_SHIFT) & PWMV2_DAC_VALUE_SV_VALUE_MASK) -#define PWMV2_DAC_VALUE_SV_VALUE_GET(x) (((uint32_t)(x) & PWMV2_DAC_VALUE_SV_VALUE_MASK) >> PWMV2_DAC_VALUE_SV_VALUE_SHIFT) - -/* Bitfield definition for register array: CAPTURE_POS */ -/* - * CAPTURE_POS (RO) - * - * related counter value captured at input negedge - */ -#define PWMV2_CAPTURE_POS_CAPTURE_POS_MASK (0xFFFFFF00UL) -#define PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT (8U) -#define PWMV2_CAPTURE_POS_CAPTURE_POS_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_POS_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_POS_SHIFT) - -/* - * CAPTURE_SELGPIO (RW) - * - * 0: result from CAP[ 7:0], from trgm - * 1: result from CAP[15:8], from gpio - */ -#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK (0x10U) -#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT (4U) -#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SET(x) (((uint32_t)(x) << PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) -#define PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_MASK) >> PWMV2_CAPTURE_POS_CAPTURE_SELGPIO_SHIFT) - -/* - * CNT_INDEX (RW) - * - * related counter - */ -#define PWMV2_CAPTURE_POS_CNT_INDEX_MASK (0x3U) -#define PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT (0U) -#define PWMV2_CAPTURE_POS_CNT_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK) -#define PWMV2_CAPTURE_POS_CNT_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_POS_CNT_INDEX_MASK) >> PWMV2_CAPTURE_POS_CNT_INDEX_SHIFT) - -/* Bitfield definition for register array: CAPTURE_NEG */ -/* - * CAPTURE_NEG (RO) - * - * counter value captured at input negedge - */ -#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK (0xFFFFFF00UL) -#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT (8U) -#define PWMV2_CAPTURE_NEG_CAPTURE_NEG_GET(x) (((uint32_t)(x) & PWMV2_CAPTURE_NEG_CAPTURE_NEG_MASK) >> PWMV2_CAPTURE_NEG_CAPTURE_NEG_SHIFT) - -/* Bitfield definition for register: IRQ_STS */ -/* - * IRQ_CAL_OVERFLOW (W1C) - * - * end of output burst - */ -#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK (0x80000000UL) -#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT (31U) -#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK) -#define PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_MASK) >> PWMV2_IRQ_STS_IRQ_CAL_OVERFLOW_SHIFT) - -/* - * IRQ_BURSTEND (RO) - * - * end of output burst - */ -#define PWMV2_IRQ_STS_IRQ_BURSTEND_MASK (0x20U) -#define PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT (5U) -#define PWMV2_IRQ_STS_IRQ_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_BURSTEND_MASK) >> PWMV2_IRQ_STS_IRQ_BURSTEND_SHIFT) - -/* - * IRQ_FAULT (RO) - * - * for external fault event - */ -#define PWMV2_IRQ_STS_IRQ_FAULT_MASK (0x10U) -#define PWMV2_IRQ_STS_IRQ_FAULT_SHIFT (4U) -#define PWMV2_IRQ_STS_IRQ_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_FAULT_MASK) >> PWMV2_IRQ_STS_IRQ_FAULT_SHIFT) - -/* - * IRQ_CAPTURE_NEG (RO) - * - * capture negedge status - */ -#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK (0x8U) -#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT (3U) -#define PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_NEG_SHIFT) - -/* - * IRQ_CAPTURE_POS (RO) - * - * capture posedge status - */ -#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK (0x4U) -#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT (2U) -#define PWMV2_IRQ_STS_IRQ_CAPTURE_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CAPTURE_POS_MASK) >> PWMV2_IRQ_STS_IRQ_CAPTURE_POS_SHIFT) - -/* - * IRQ_RELOAD (RO) - * - * when clock counter reach the reload time - */ -#define PWMV2_IRQ_STS_IRQ_RELOAD_MASK (0x2U) -#define PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT (1U) -#define PWMV2_IRQ_STS_IRQ_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_RELOAD_MASK) >> PWMV2_IRQ_STS_IRQ_RELOAD_SHIFT) - -/* - * IRQ_CMP (RO) - * - * for 24 channel, compare event - */ -#define PWMV2_IRQ_STS_IRQ_CMP_MASK (0x1U) -#define PWMV2_IRQ_STS_IRQ_CMP_SHIFT (0U) -#define PWMV2_IRQ_STS_IRQ_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_IRQ_CMP_MASK) >> PWMV2_IRQ_STS_IRQ_CMP_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * IRQ_EN_OVERFLOW (RW) - * - * enable interrupt when calculation unit overflow - */ -#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK (0x80000000UL) -#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT (31U) -#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK) -#define PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_MASK) >> PWMV2_IRQ_EN_IRQ_EN_OVERFLOW_SHIFT) - -/* Bitfield definition for register: IRQ_STS_CMP */ -/* - * IRQ_STS_CMP (W1C) - * - * interrupt flag for compare point match event, and each bit means one compare point. - */ -#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK (0xFFFFFFUL) -#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT (0U) -#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK) -#define PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_MASK) >> PWMV2_IRQ_STS_CMP_IRQ_STS_CMP_SHIFT) - -/* Bitfield definition for register: IRQ_STS_RELOAD */ -/* - * IRQ_STS_RELOAD (W1C) - * - * interrupt flag for reload event , and each bit means one main counter. - */ -#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK (0xFU) -#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT (0U) -#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK) -#define PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_MASK) >> PWMV2_IRQ_STS_RELOAD_IRQ_STS_RELOAD_SHIFT) - -/* Bitfield definition for register: IRQ_STS_CAP_POS */ -/* - * IRQ_STS_CAP_POS (W1C) - * - * interrupt flag for posedge capture event , and each bit means one capture channel. - */ -#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK (0xFFU) -#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT (0U) -#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK) -#define PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_MASK) >> PWMV2_IRQ_STS_CAP_POS_IRQ_STS_CAP_POS_SHIFT) - -/* Bitfield definition for register: IRQ_STS_CAP_NEG */ -/* - * IRQ_STS_CAP_NEG (W1C) - * - * interrupt flag for negedge capture event , and each bit means one capture channel. - */ -#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK (0xFFU) -#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT (0U) -#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK) -#define PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_MASK) >> PWMV2_IRQ_STS_CAP_NEG_IRQ_STS_CAP_NEG_SHIFT) - -/* Bitfield definition for register: IRQ_STS_FAULT */ -/* - * IRQ_STS_FAULT (W1C) - * - * interrupt flag for external fault event , and each bit means one external fault channel. - */ -#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK (0xFFU) -#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT (0U) -#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK) -#define PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_MASK) >> PWMV2_IRQ_STS_FAULT_IRQ_STS_FAULT_SHIFT) - -/* Bitfield definition for register: IRQ_STS_BURSTEND */ -/* - * IRQ_STS_BURSTEND (W1C) - * - * interrupt flag for output burst done event , and each bit means one main counter. - */ -#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK (0xFU) -#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT (0U) -#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SET(x) (((uint32_t)(x) << PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK) -#define PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_MASK) >> PWMV2_IRQ_STS_BURSTEND_IRQ_STS_BURSTEND_SHIFT) - -/* Bitfield definition for register: IRQ_EN_CMP */ -/* - * IRQ_EN_CMP (RW) - * - * interrupt enable field for compare point match event, and each bit means one compare point. - */ -#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK (0xFFFFFFUL) -#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT (0U) -#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK) -#define PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_MASK) >> PWMV2_IRQ_EN_CMP_IRQ_EN_CMP_SHIFT) - -/* Bitfield definition for register: IRQ_EN_RELOAD */ -/* - * IRQ_EN_RELOAD (RW) - * - * interrupt enable field for reload event , and each bit means one main counter. - */ -#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK (0xFU) -#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT (0U) -#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK) -#define PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_MASK) >> PWMV2_IRQ_EN_RELOAD_IRQ_EN_RELOAD_SHIFT) - -/* Bitfield definition for register: IRQ_EN_CAP_POS */ -/* - * IRQ_EN_CAP_POS (RW) - * - * interrupt enable field for posedge capture event , and each bit means one capture channel. - */ -#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK (0xFFU) -#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT (0U) -#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK) -#define PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_MASK) >> PWMV2_IRQ_EN_CAP_POS_IRQ_EN_CAP_POS_SHIFT) - -/* Bitfield definition for register: IRQ_EN_CAP_NEG */ -/* - * IRQ_EN_CAP_NEG (RW) - * - * interrupt enable field for negedge capture event , and each bit means one capture channel. - */ -#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK (0xFFU) -#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT (0U) -#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK) -#define PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_MASK) >> PWMV2_IRQ_EN_CAP_NEG_IRQ_EN_CAP_NEG_SHIFT) - -/* Bitfield definition for register: IRQ_EN_FAULT */ -/* - * IRQ_EN_FAULT (RW) - * - * interrupt enable field for external fault event , and each bit means one external fault channel. - */ -#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK (0xFFU) -#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT (0U) -#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK) -#define PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_MASK) >> PWMV2_IRQ_EN_FAULT_IRQ_EN_FAULT_SHIFT) - -/* Bitfield definition for register: IRQ_EN_BURSTEND */ -/* - * IRQ_EN_BURSTEND (RW) - * - * interrupt enable field for output burst done event , and each bit means one main counter. - */ -#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK (0xFU) -#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT (0U) -#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SET(x) (((uint32_t)(x) << PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK) -#define PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_GET(x) (((uint32_t)(x) & PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_MASK) >> PWMV2_IRQ_EN_BURSTEND_IRQ_EN_BURSTEND_SHIFT) - -/* Bitfield definition for register: DMA_EN */ -/* - * DMA3_EN (RW) - * - * enable dma3 - */ -#define PWMV2_DMA_EN_DMA3_EN_MASK (0x80000000UL) -#define PWMV2_DMA_EN_DMA3_EN_SHIFT (31U) -#define PWMV2_DMA_EN_DMA3_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_EN_SHIFT) & PWMV2_DMA_EN_DMA3_EN_MASK) -#define PWMV2_DMA_EN_DMA3_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_EN_MASK) >> PWMV2_DMA_EN_DMA3_EN_SHIFT) - -/* - * DMA3_SEL (RW) - * - * selelct one of compare point(0~23) or one reload point(24~27) as dma0 - */ -#define PWMV2_DMA_EN_DMA3_SEL_MASK (0x1F000000UL) -#define PWMV2_DMA_EN_DMA3_SEL_SHIFT (24U) -#define PWMV2_DMA_EN_DMA3_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA3_SEL_SHIFT) & PWMV2_DMA_EN_DMA3_SEL_MASK) -#define PWMV2_DMA_EN_DMA3_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA3_SEL_MASK) >> PWMV2_DMA_EN_DMA3_SEL_SHIFT) - -/* - * DMA2_EN (RW) - * - * enable dma2 - */ -#define PWMV2_DMA_EN_DMA2_EN_MASK (0x800000UL) -#define PWMV2_DMA_EN_DMA2_EN_SHIFT (23U) -#define PWMV2_DMA_EN_DMA2_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_EN_SHIFT) & PWMV2_DMA_EN_DMA2_EN_MASK) -#define PWMV2_DMA_EN_DMA2_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_EN_MASK) >> PWMV2_DMA_EN_DMA2_EN_SHIFT) - -/* - * DMA2_SEL (RW) - * - * selelct one of compare point(0~23) or one reload point(24~27) as dma0 - */ -#define PWMV2_DMA_EN_DMA2_SEL_MASK (0x1F0000UL) -#define PWMV2_DMA_EN_DMA2_SEL_SHIFT (16U) -#define PWMV2_DMA_EN_DMA2_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA2_SEL_SHIFT) & PWMV2_DMA_EN_DMA2_SEL_MASK) -#define PWMV2_DMA_EN_DMA2_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA2_SEL_MASK) >> PWMV2_DMA_EN_DMA2_SEL_SHIFT) - -/* - * DMA1_EN (RW) - * - * enable dma1 - */ -#define PWMV2_DMA_EN_DMA1_EN_MASK (0x8000U) -#define PWMV2_DMA_EN_DMA1_EN_SHIFT (15U) -#define PWMV2_DMA_EN_DMA1_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_EN_SHIFT) & PWMV2_DMA_EN_DMA1_EN_MASK) -#define PWMV2_DMA_EN_DMA1_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_EN_MASK) >> PWMV2_DMA_EN_DMA1_EN_SHIFT) - -/* - * DMA1_SEL (RW) - * - * selelct one of compare point(0~23) or one reload point(24~27) as dma0 - */ -#define PWMV2_DMA_EN_DMA1_SEL_MASK (0x1F00U) -#define PWMV2_DMA_EN_DMA1_SEL_SHIFT (8U) -#define PWMV2_DMA_EN_DMA1_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA1_SEL_SHIFT) & PWMV2_DMA_EN_DMA1_SEL_MASK) -#define PWMV2_DMA_EN_DMA1_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA1_SEL_MASK) >> PWMV2_DMA_EN_DMA1_SEL_SHIFT) - -/* - * DMA0_EN (RW) - * - * enable dma0 - */ -#define PWMV2_DMA_EN_DMA0_EN_MASK (0x80U) -#define PWMV2_DMA_EN_DMA0_EN_SHIFT (7U) -#define PWMV2_DMA_EN_DMA0_EN_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_EN_SHIFT) & PWMV2_DMA_EN_DMA0_EN_MASK) -#define PWMV2_DMA_EN_DMA0_EN_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_EN_MASK) >> PWMV2_DMA_EN_DMA0_EN_SHIFT) - -/* - * DMA0_SEL (RW) - * - * selelct one of compare point(0~23) or one reload point(24~27) as dma0 - */ -#define PWMV2_DMA_EN_DMA0_SEL_MASK (0x1FU) -#define PWMV2_DMA_EN_DMA0_SEL_SHIFT (0U) -#define PWMV2_DMA_EN_DMA0_SEL_SET(x) (((uint32_t)(x) << PWMV2_DMA_EN_DMA0_SEL_SHIFT) & PWMV2_DMA_EN_DMA0_SEL_MASK) -#define PWMV2_DMA_EN_DMA0_SEL_GET(x) (((uint32_t)(x) & PWMV2_DMA_EN_DMA0_SEL_MASK) >> PWMV2_DMA_EN_DMA0_SEL_SHIFT) - -/* Bitfield definition for register of struct array CNT: CFG0 */ -/* - * RLD_CMP_SEL1 (RW) - * - * select one compare point from 24, set to 0x1F to disable current selection, used for reload value, compare value, force value update - */ -#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK (0x1F000000UL) -#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT (24U) -#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK) -#define PWMV2_CNT_CFG0_RLD_CMP_SEL1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL1_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL1_SHIFT) - -/* - * RLD_CMP_SEL0 (RW) - * - * select one compare point from 24, set to 0x1F to disable current selection - */ -#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK (0x1F0000UL) -#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT (16U) -#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK) -#define PWMV2_CNT_CFG0_RLD_CMP_SEL0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_CMP_SEL0_MASK) >> PWMV2_CNT_CFG0_RLD_CMP_SEL0_SHIFT) - -/* - * RLD_TRIG_SEL (RW) - * - * select one trigger from 8, should set to pulse in trig_mux - */ -#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK (0x7000U) -#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT (12U) -#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK) -#define PWMV2_CNT_CFG0_RLD_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_TRIG_SEL_MASK) >> PWMV2_CNT_CFG0_RLD_TRIG_SEL_SHIFT) - -/* - * RLD_UPDATE_TIME (RW) - * - * define when to use the calculation output value as reload time - * 00: software set work_ctrl1.shadow_lock bit - * 01: use compare point selected by rld_cmp_sel0 or rld_cmp_sel1 - * 10: counter reload time - * 11: use rld_trig_sel to select one of the input trigger - * NOTE: 00 is not recommended since the update time is not controllable, may cause error in complex application. - */ -#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK (0x300U) -#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT (8U) -#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK) -#define PWMV2_CNT_CFG0_RLD_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_RLD_UPDATE_TIME_MASK) >> PWMV2_CNT_CFG0_RLD_UPDATE_TIME_SHIFT) - -/* - * CNT_D_PARAM (RW) - * - * input dac data parameter - */ -#define PWMV2_CNT_CFG0_CNT_D_PARAM_MASK (0x1FU) -#define PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT (0U) -#define PWMV2_CNT_CFG0_CNT_D_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) -#define PWMV2_CNT_CFG0_CNT_D_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG0_CNT_D_PARAM_MASK) >> PWMV2_CNT_CFG0_CNT_D_PARAM_SHIFT) - -/* Bitfield definition for register of struct array CNT: CFG1 */ -/* - * CNT_DAC_INDEX (RW) - * - * select one of the dac value - */ -#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK (0x3000000UL) -#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT (24U) -#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) -#define PWMV2_CNT_CFG1_CNT_DAC_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_DAC_INDEX_MASK) >> PWMV2_CNT_CFG1_CNT_DAC_INDEX_SHIFT) - -/* - * CNT_LU_EN (RW) - * - * set to enable up limit, use cnt_lu_off to select one of the shadow register value as limitation - */ -#define PWMV2_CNT_CFG1_CNT_LU_EN_MASK (0x800000UL) -#define PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT (23U) -#define PWMV2_CNT_CFG1_CNT_LU_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK) -#define PWMV2_CNT_CFG1_CNT_LU_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LU_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LU_EN_SHIFT) - -/* - * CNT_LIM_UP (RW) - * - * up limit offset selection, from one of the shadow_val - */ -#define PWMV2_CNT_CFG1_CNT_LIM_UP_MASK (0x1F0000UL) -#define PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT (16U) -#define PWMV2_CNT_CFG1_CNT_LIM_UP_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) -#define PWMV2_CNT_CFG1_CNT_LIM_UP_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_UP_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_UP_SHIFT) - -/* - * CNT_LL_EN (RW) - * - * set to enable low limit - */ -#define PWMV2_CNT_CFG1_CNT_LL_EN_MASK (0x8000U) -#define PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT (15U) -#define PWMV2_CNT_CFG1_CNT_LL_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK) -#define PWMV2_CNT_CFG1_CNT_LL_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LL_EN_MASK) >> PWMV2_CNT_CFG1_CNT_LL_EN_SHIFT) - -/* - * CNT_LIM_LO (RW) - * - * low limit offset selection, from one of the shadow_val - */ -#define PWMV2_CNT_CFG1_CNT_LIM_LO_MASK (0x1F00U) -#define PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT (8U) -#define PWMV2_CNT_CFG1_CNT_LIM_LO_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) -#define PWMV2_CNT_CFG1_CNT_LIM_LO_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_LIM_LO_MASK) >> PWMV2_CNT_CFG1_CNT_LIM_LO_SHIFT) - -/* - * CNT_IN_OFF (RW) - * - * input data offset selection, from one of the shadow_val, default just shadow reload time - */ -#define PWMV2_CNT_CFG1_CNT_IN_OFF_MASK (0x1FU) -#define PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT (0U) -#define PWMV2_CNT_CFG1_CNT_IN_OFF_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) -#define PWMV2_CNT_CFG1_CNT_IN_OFF_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG1_CNT_IN_OFF_MASK) >> PWMV2_CNT_CFG1_CNT_IN_OFF_SHIFT) - -/* Bitfield definition for register of struct array CNT: CFG2 */ -/* - * CNT_RELOAD_EN (RW) - * - * set to use input signal(selected by cnt_reload_trig) to reload timer - */ -#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK (0x80000000UL) -#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT (31U) -#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK) -#define PWMV2_CNT_CFG2_CNT_RELOAD_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_EN_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_EN_SHIFT) - -/* - * CNT_RELOAD_TRIG (RW) - * - * select one trigger from 8, should set to pulse in trig_mux - */ -#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK (0x7000000UL) -#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT (24U) -#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) -#define PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_MASK) >> PWMV2_CNT_CFG2_CNT_RELOAD_TRIG_SHIFT) - -/* - * CNT_UPDATE_TRIG1 (RW) - * - * select one trigger from 8, should set to pulse in trig_mux - */ -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK (0x700000UL) -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT (20U) -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG1_SHIFT) - -/* - * CNT_UPDATE_EN1 (RW) - * - * set to enable using trig1 to load calculation cell output to counter - */ -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK (0x80000UL) -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT (19U) -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK) -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN1_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN1_SHIFT) - -/* - * CNT_TRIG1 (RW) - * - * change counter value to one of the calculation cell output when cnt_update_triger1 issued - */ -#define PWMV2_CNT_CFG2_CNT_TRIG1_MASK (0xF000U) -#define PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT (12U) -#define PWMV2_CNT_CFG2_CNT_TRIG1_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK) -#define PWMV2_CNT_CFG2_CNT_TRIG1_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG1_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG1_SHIFT) - -/* - * CNT_UPDATE_TRIG0 (RW) - * - * select one trigger from 8, should set to pulse in trig_mux - */ -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK (0x700U) -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT (8U) -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) -#define PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_TRIG0_SHIFT) - -/* - * CNT_UPDATE_EN0 (RW) - * - * set to enable using trig0 to load calculation cell output to counter - */ -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK (0x80U) -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT (7U) -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK) -#define PWMV2_CNT_CFG2_CNT_UPDATE_EN0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_UPDATE_EN0_MASK) >> PWMV2_CNT_CFG2_CNT_UPDATE_EN0_SHIFT) - -/* - * CNT_TRIG0 (RW) - * - * change counter value to one of the calculation cell output when cnt_update_triger0 issued - */ -#define PWMV2_CNT_CFG2_CNT_TRIG0_MASK (0xFU) -#define PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT (0U) -#define PWMV2_CNT_CFG2_CNT_TRIG0_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK) -#define PWMV2_CNT_CFG2_CNT_TRIG0_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG2_CNT_TRIG0_MASK) >> PWMV2_CNT_CFG2_CNT_TRIG0_SHIFT) - -/* Bitfield definition for register of struct array CNT: CFG3 */ -/* - * CNT_START_SEL (RW) - * - * select one trigger from 8, should set to pulse in trig_mux - */ -#define PWMV2_CNT_CFG3_CNT_START_SEL_MASK (0x700000UL) -#define PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT (20U) -#define PWMV2_CNT_CFG3_CNT_START_SEL_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK) -#define PWMV2_CNT_CFG3_CNT_START_SEL_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_START_SEL_MASK) >> PWMV2_CNT_CFG3_CNT_START_SEL_SHIFT) - -/* - * CNT_HW_START_EN (RW) - * - * enable use trigger to start pwm output(at next reload point), by cnt_start_sel - */ -#define PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK (0x20000UL) -#define PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT (17U) -#define PWMV2_CNT_CFG3_CNT_HW_START_EN_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK) -#define PWMV2_CNT_CFG3_CNT_HW_START_EN_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_HW_START_EN_MASK) >> PWMV2_CNT_CFG3_CNT_HW_START_EN_SHIFT) - -/* - * CNT_BURST (RW) - * - * output pwm wave for configured burst(timer period), - * 0 for one burst; 1 for two burst. - * set to 0xFFFF for always output pwm wave - * bit's only used when setting cnt_sw_start or trigger selected by cnt_start_sel - */ -#define PWMV2_CNT_CFG3_CNT_BURST_MASK (0xFFFFU) -#define PWMV2_CNT_CFG3_CNT_BURST_SHIFT (0U) -#define PWMV2_CNT_CFG3_CNT_BURST_SET(x) (((uint32_t)(x) << PWMV2_CNT_CFG3_CNT_BURST_SHIFT) & PWMV2_CNT_CFG3_CNT_BURST_MASK) -#define PWMV2_CNT_CFG3_CNT_BURST_GET(x) (((uint32_t)(x) & PWMV2_CNT_CFG3_CNT_BURST_MASK) >> PWMV2_CNT_CFG3_CNT_BURST_SHIFT) - -/* Bitfield definition for register: CNT_GLBCFG */ -/* - * CNT_SW_START (WO) - * - * set to start pwm output(at next reload point), write only, Auto clear. - * User can disable pwm output before burst end by start again with cnt_burst=0 - */ -#define PWMV2_CNT_GLBCFG_CNT_SW_START_MASK (0xF0000UL) -#define PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT (16U) -#define PWMV2_CNT_GLBCFG_CNT_SW_START_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK) -#define PWMV2_CNT_GLBCFG_CNT_SW_START_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_CNT_SW_START_MASK) >> PWMV2_CNT_GLBCFG_CNT_SW_START_SHIFT) - -/* - * TIMER_RESET (WO) - * - * set to clear current timer. Auto clear - */ -#define PWMV2_CNT_GLBCFG_TIMER_RESET_MASK (0xF00U) -#define PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT (8U) -#define PWMV2_CNT_GLBCFG_TIMER_RESET_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK) -#define PWMV2_CNT_GLBCFG_TIMER_RESET_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_RESET_MASK) >> PWMV2_CNT_GLBCFG_TIMER_RESET_SHIFT) - -/* - * TIMER_ENABLE (RW) - * - * 1 to enable the main cycle counter; 0 to stop the counter; - * NOTE: when counter stopped, the related trigger_out will be cleared to 0, the related pwm output will keep value not changed. - */ -#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK (0xFU) -#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT (0U) -#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_SET(x) (((uint32_t)(x) << PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK) -#define PWMV2_CNT_GLBCFG_TIMER_ENABLE_GET(x) (((uint32_t)(x) & PWMV2_CNT_GLBCFG_TIMER_ENABLE_MASK) >> PWMV2_CNT_GLBCFG_TIMER_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CAL: CFG0 */ -/* - * CAL_LU_PARAM (RW) - * - * up limit parameter - */ -#define PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK (0x1F000000UL) -#define PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT (24U) -#define PWMV2_CAL_CFG0_CAL_LU_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) -#define PWMV2_CAL_CFG0_CAL_LU_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LU_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LU_PARAM_SHIFT) - -/* - * CAL_LL_PARAM (RW) - * - * low limit parameter - */ -#define PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK (0x1F0000UL) -#define PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT (16U) -#define PWMV2_CAL_CFG0_CAL_LL_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) -#define PWMV2_CAL_CFG0_CAL_LL_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_LL_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_LL_PARAM_SHIFT) - -/* - * CAL_T_PARAM (RW) - * - * period parameter - */ -#define PWMV2_CAL_CFG0_CAL_T_PARAM_MASK (0x1F00U) -#define PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT (8U) -#define PWMV2_CAL_CFG0_CAL_T_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) -#define PWMV2_CAL_CFG0_CAL_T_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_T_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_T_PARAM_SHIFT) - -/* - * CAL_D_PARAM (RW) - * - * dac/counter value parameter - */ -#define PWMV2_CAL_CFG0_CAL_D_PARAM_MASK (0x1FU) -#define PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT (0U) -#define PWMV2_CAL_CFG0_CAL_D_PARAM_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) -#define PWMV2_CAL_CFG0_CAL_D_PARAM_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG0_CAL_D_PARAM_MASK) >> PWMV2_CAL_CFG0_CAL_D_PARAM_SHIFT) - -/* Bitfield definition for register of struct array CAL: CFG1 */ -/* - * CAL_T_INDEX (RW) - * - * select one of 4 counter reload time - */ -#define PWMV2_CAL_CFG1_CAL_T_INDEX_MASK (0x30000000UL) -#define PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT (28U) -#define PWMV2_CAL_CFG1_CAL_T_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) -#define PWMV2_CAL_CFG1_CAL_T_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_T_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_T_INDEX_SHIFT) - -/* - * CAL_IN_INDEX (RW) - * - * 0~3 to select one of the dac input value; 4~7 to select one of the current counter value - */ -#define PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK (0x7000000UL) -#define PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT (24U) -#define PWMV2_CAL_CFG1_CAL_IN_INDEX_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) -#define PWMV2_CAL_CFG1_CAL_IN_INDEX_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_INDEX_MASK) >> PWMV2_CAL_CFG1_CAL_IN_INDEX_SHIFT) - -/* - * CAL_LU_EN (RW) - * - * set to enable up limit - */ -#define PWMV2_CAL_CFG1_CAL_LU_EN_MASK (0x800000UL) -#define PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT (23U) -#define PWMV2_CAL_CFG1_CAL_LU_EN_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK) -#define PWMV2_CAL_CFG1_CAL_LU_EN_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LU_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LU_EN_SHIFT) - -/* - * CAL_LIM_UP (RW) - * - * up limit offset selection, select from one of the shadow_val - */ -#define PWMV2_CAL_CFG1_CAL_LIM_UP_MASK (0x1F0000UL) -#define PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT (16U) -#define PWMV2_CAL_CFG1_CAL_LIM_UP_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) -#define PWMV2_CAL_CFG1_CAL_LIM_UP_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_UP_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_UP_SHIFT) - -/* - * CAL_LL_EN (RW) - * - * set to enable low limit - */ -#define PWMV2_CAL_CFG1_CAL_LL_EN_MASK (0x8000U) -#define PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT (15U) -#define PWMV2_CAL_CFG1_CAL_LL_EN_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK) -#define PWMV2_CAL_CFG1_CAL_LL_EN_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LL_EN_MASK) >> PWMV2_CAL_CFG1_CAL_LL_EN_SHIFT) - -/* - * CAL_LIM_LO (RW) - * - * low limit offset selection, select from one of the shadow_val - */ -#define PWMV2_CAL_CFG1_CAL_LIM_LO_MASK (0x1F00U) -#define PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT (8U) -#define PWMV2_CAL_CFG1_CAL_LIM_LO_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) -#define PWMV2_CAL_CFG1_CAL_LIM_LO_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_LIM_LO_MASK) >> PWMV2_CAL_CFG1_CAL_LIM_LO_SHIFT) - -/* - * CAL_IN_OFF (RW) - * - * offset for calculation unit, select from one of the shadow_val. - */ -#define PWMV2_CAL_CFG1_CAL_IN_OFF_MASK (0x1FU) -#define PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT (0U) -#define PWMV2_CAL_CFG1_CAL_IN_OFF_SET(x) (((uint32_t)(x) << PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) -#define PWMV2_CAL_CFG1_CAL_IN_OFF_GET(x) (((uint32_t)(x) & PWMV2_CAL_CFG1_CAL_IN_OFF_MASK) >> PWMV2_CAL_CFG1_CAL_IN_OFF_SHIFT) - -/* Bitfield definition for register of struct array CMP: CFG */ -/* - * CMP_TRIG_SEL (RW) - * - * select one trigger from 8, should set to pulse in trig_mux - */ -#define PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK (0x70000000UL) -#define PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT (28U) -#define PWMV2_CMP_CFG_CMP_TRIG_SEL_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) -#define PWMV2_CMP_CFG_CMP_TRIG_SEL_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_TRIG_SEL_MASK) >> PWMV2_CMP_CFG_CMP_TRIG_SEL_SHIFT) - -/* - * CMP_UPDATE_TIME (RW) - * - * define when to use the shadow register value for working register(trig_cmp) - * 000: software set work_ctrl1.shadow_lock bit - * 001: update immediately(at next cycle) - * 010: related counter reload time - * 011: use cmp_update_trigger(from trig_mux, selected by cmp_trig_sel) - * 100: use the related counter rld_cmp_sel0 to select one compare point - * 101: use the related counter rld_cmp_sel1, to select one compare point - * 11x: reserved, no update. - */ -#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK (0x7000000UL) -#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT (24U) -#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) -#define PWMV2_CMP_CFG_CMP_UPDATE_TIME_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_UPDATE_TIME_MASK) >> PWMV2_CMP_CFG_CMP_UPDATE_TIME_SHIFT) - -/* - * CMP_IN_SEL (RW) - * - * 0x00~0x1B select one of the shadow_val directly - * 0x20~0x2F select one of the calculation cell output - * 0x30~0x37 select one of capture_pos value(low 8bit are 0) - * 0x38+k select T/4 - * 0x3E select 0xFFFFF000 - * 0x3F select 0xFFFFFF00 - * others select 0 - */ -#define PWMV2_CMP_CFG_CMP_IN_SEL_MASK (0x3F0000UL) -#define PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT (16U) -#define PWMV2_CMP_CFG_CMP_IN_SEL_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK) -#define PWMV2_CMP_CFG_CMP_IN_SEL_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_IN_SEL_MASK) >> PWMV2_CMP_CFG_CMP_IN_SEL_SHIFT) - -/* - * CMP_CNT (RW) - * - * select one from 4 counters, only for N>=16. - * for N<16, this field is0, every 4 compare point related to one counter(0123 for counter0, 4567 for counter1….) - */ -#define PWMV2_CMP_CFG_CMP_CNT_MASK (0xC000U) -#define PWMV2_CMP_CFG_CMP_CNT_SHIFT (14U) -#define PWMV2_CMP_CFG_CMP_CNT_SET(x) (((uint32_t)(x) << PWMV2_CMP_CFG_CMP_CNT_SHIFT) & PWMV2_CMP_CFG_CMP_CNT_MASK) -#define PWMV2_CMP_CFG_CMP_CNT_GET(x) (((uint32_t)(x) & PWMV2_CMP_CFG_CMP_CNT_MASK) >> PWMV2_CMP_CFG_CMP_CNT_SHIFT) - - - -/* SHADOW_VAL register group index macro definition */ -#define PWMV2_SHADOW_VAL_0 (0UL) -#define PWMV2_SHADOW_VAL_1 (1UL) -#define PWMV2_SHADOW_VAL_2 (2UL) -#define PWMV2_SHADOW_VAL_3 (3UL) -#define PWMV2_SHADOW_VAL_4 (4UL) -#define PWMV2_SHADOW_VAL_5 (5UL) -#define PWMV2_SHADOW_VAL_6 (6UL) -#define PWMV2_SHADOW_VAL_7 (7UL) -#define PWMV2_SHADOW_VAL_8 (8UL) -#define PWMV2_SHADOW_VAL_9 (9UL) -#define PWMV2_SHADOW_VAL_10 (10UL) -#define PWMV2_SHADOW_VAL_11 (11UL) -#define PWMV2_SHADOW_VAL_12 (12UL) -#define PWMV2_SHADOW_VAL_13 (13UL) -#define PWMV2_SHADOW_VAL_14 (14UL) -#define PWMV2_SHADOW_VAL_15 (15UL) -#define PWMV2_SHADOW_VAL_16 (16UL) -#define PWMV2_SHADOW_VAL_17 (17UL) -#define PWMV2_SHADOW_VAL_18 (18UL) -#define PWMV2_SHADOW_VAL_19 (19UL) -#define PWMV2_SHADOW_VAL_20 (20UL) -#define PWMV2_SHADOW_VAL_21 (21UL) -#define PWMV2_SHADOW_VAL_22 (22UL) -#define PWMV2_SHADOW_VAL_23 (23UL) -#define PWMV2_SHADOW_VAL_24 (24UL) -#define PWMV2_SHADOW_VAL_25 (25UL) -#define PWMV2_SHADOW_VAL_26 (26UL) -#define PWMV2_SHADOW_VAL_27 (27UL) - -/* PWM register group index macro definition */ -#define PWMV2_PWM_0 (0UL) -#define PWMV2_PWM_1 (1UL) -#define PWMV2_PWM_2 (2UL) -#define PWMV2_PWM_3 (3UL) -#define PWMV2_PWM_4 (4UL) -#define PWMV2_PWM_5 (5UL) -#define PWMV2_PWM_6 (6UL) -#define PWMV2_PWM_7 (7UL) - -/* TRIGGER_CFG register group index macro definition */ -#define PWMV2_TRIGGER_CFG_0 (0UL) -#define PWMV2_TRIGGER_CFG_1 (1UL) -#define PWMV2_TRIGGER_CFG_2 (2UL) -#define PWMV2_TRIGGER_CFG_3 (3UL) -#define PWMV2_TRIGGER_CFG_4 (4UL) -#define PWMV2_TRIGGER_CFG_5 (5UL) -#define PWMV2_TRIGGER_CFG_6 (6UL) -#define PWMV2_TRIGGER_CFG_7 (7UL) - -/* CNT_RELOAD_WORK register group index macro definition */ -#define PWMV2_CNT_RELOAD_WORK_0 (0UL) -#define PWMV2_CNT_RELOAD_WORK_1 (1UL) -#define PWMV2_CNT_RELOAD_WORK_2 (2UL) -#define PWMV2_CNT_RELOAD_WORK_3 (3UL) - -/* CMP_VAL_WORK register group index macro definition */ -#define PWMV2_CMP_VAL_WORK_0 (0UL) -#define PWMV2_CMP_VAL_WORK_1 (1UL) -#define PWMV2_CMP_VAL_WORK_2 (2UL) -#define PWMV2_CMP_VAL_WORK_3 (3UL) -#define PWMV2_CMP_VAL_WORK_4 (4UL) -#define PWMV2_CMP_VAL_WORK_5 (5UL) -#define PWMV2_CMP_VAL_WORK_6 (6UL) -#define PWMV2_CMP_VAL_WORK_7 (7UL) -#define PWMV2_CMP_VAL_WORK_8 (8UL) -#define PWMV2_CMP_VAL_WORK_9 (9UL) -#define PWMV2_CMP_VAL_WORK_10 (10UL) -#define PWMV2_CMP_VAL_WORK_11 (11UL) -#define PWMV2_CMP_VAL_WORK_12 (12UL) -#define PWMV2_CMP_VAL_WORK_13 (13UL) -#define PWMV2_CMP_VAL_WORK_14 (14UL) -#define PWMV2_CMP_VAL_WORK_15 (15UL) -#define PWMV2_CMP_VAL_WORK_16 (16UL) -#define PWMV2_CMP_VAL_WORK_17 (17UL) -#define PWMV2_CMP_VAL_WORK_18 (18UL) -#define PWMV2_CMP_VAL_WORK_19 (19UL) -#define PWMV2_CMP_VAL_WORK_20 (20UL) -#define PWMV2_CMP_VAL_WORK_21 (21UL) -#define PWMV2_CMP_VAL_WORK_22 (22UL) -#define PWMV2_CMP_VAL_WORK_23 (23UL) - -/* CNT_VAL register group index macro definition */ -#define PWMV2_CNT_VAL_0 (0UL) -#define PWMV2_CNT_VAL_1 (1UL) -#define PWMV2_CNT_VAL_2 (2UL) -#define PWMV2_CNT_VAL_3 (3UL) - -/* DAC_VALUE_SV register group index macro definition */ -#define PWMV2_DAC_VALUE_SV_0 (0UL) -#define PWMV2_DAC_VALUE_SV_1 (1UL) -#define PWMV2_DAC_VALUE_SV_2 (2UL) -#define PWMV2_DAC_VALUE_SV_3 (3UL) - -/* CAPTURE_POS register group index macro definition */ -#define PWMV2_CAPTURE_POS_0 (0UL) -#define PWMV2_CAPTURE_POS_1 (1UL) -#define PWMV2_CAPTURE_POS_2 (2UL) -#define PWMV2_CAPTURE_POS_3 (3UL) -#define PWMV2_CAPTURE_POS_4 (4UL) -#define PWMV2_CAPTURE_POS_5 (5UL) -#define PWMV2_CAPTURE_POS_6 (6UL) -#define PWMV2_CAPTURE_POS_7 (7UL) - -/* CAPTURE_NEG register group index macro definition */ -#define PWMV2_CAPTURE_NEG_0 (0UL) -#define PWMV2_CAPTURE_NEG_1 (1UL) -#define PWMV2_CAPTURE_NEG_2 (2UL) -#define PWMV2_CAPTURE_NEG_3 (3UL) -#define PWMV2_CAPTURE_NEG_4 (4UL) -#define PWMV2_CAPTURE_NEG_5 (5UL) -#define PWMV2_CAPTURE_NEG_6 (6UL) -#define PWMV2_CAPTURE_NEG_7 (7UL) - -/* CNT register group index macro definition */ -#define PWMV2_CNT_0 (0UL) -#define PWMV2_CNT_1 (1UL) -#define PWMV2_CNT_2 (2UL) -#define PWMV2_CNT_3 (3UL) - -/* CAL register group index macro definition */ -#define PWMV2_CAL_0 (0UL) -#define PWMV2_CAL_1 (1UL) -#define PWMV2_CAL_2 (2UL) -#define PWMV2_CAL_3 (3UL) -#define PWMV2_CAL_4 (4UL) -#define PWMV2_CAL_5 (5UL) -#define PWMV2_CAL_6 (6UL) -#define PWMV2_CAL_7 (7UL) -#define PWMV2_CAL_8 (8UL) -#define PWMV2_CAL_9 (9UL) -#define PWMV2_CAL_10 (10UL) -#define PWMV2_CAL_11 (11UL) -#define PWMV2_CAL_12 (12UL) -#define PWMV2_CAL_13 (13UL) -#define PWMV2_CAL_14 (14UL) -#define PWMV2_CAL_15 (15UL) - -/* CMP register group index macro definition */ -#define PWMV2_CMP_0 (0UL) -#define PWMV2_CMP_1 (1UL) -#define PWMV2_CMP_2 (2UL) -#define PWMV2_CMP_3 (3UL) -#define PWMV2_CMP_4 (4UL) -#define PWMV2_CMP_5 (5UL) -#define PWMV2_CMP_6 (6UL) -#define PWMV2_CMP_7 (7UL) -#define PWMV2_CMP_8 (8UL) -#define PWMV2_CMP_9 (9UL) -#define PWMV2_CMP_10 (10UL) -#define PWMV2_CMP_11 (11UL) -#define PWMV2_CMP_12 (12UL) -#define PWMV2_CMP_13 (13UL) -#define PWMV2_CMP_14 (14UL) -#define PWMV2_CMP_15 (15UL) -#define PWMV2_CMP_16 (16UL) -#define PWMV2_CMP_17 (17UL) -#define PWMV2_CMP_18 (18UL) -#define PWMV2_CMP_19 (19UL) -#define PWMV2_CMP_20 (20UL) -#define PWMV2_CMP_21 (21UL) -#define PWMV2_CMP_22 (22UL) -#define PWMV2_CMP_23 (23UL) - - -#endif /* HPM_PWMV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_qeiv2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_qeiv2_regs.h deleted file mode 100644 index 15eca9a7572..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_qeiv2_regs.h +++ /dev/null @@ -1,2143 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEIV2_H -#define HPM_QEIV2_H - -typedef struct { - __RW uint32_t CR; /* 0x0: Control register */ - __RW uint32_t PHCFG; /* 0x4: Phase configure register */ - __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ - __RW uint32_t PHIDX; /* 0xC: Phase index register */ - __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ - __RW uint32_t READEN; /* 0x14: Read event enable register */ - __RW uint32_t ZCMP; /* 0x18: Z comparator */ - __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ - __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ - __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ - __RW uint32_t SR; /* 0x28: Status register */ - __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ - struct { - __RW uint32_t Z; /* 0x30: Z counter */ - __R uint32_t PH; /* 0x34: Phase counter */ - __RW uint32_t SPD; /* 0x38: Speed counter */ - __R uint32_t TMR; /* 0x3C: Timer counter */ - } COUNT[4]; - __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */ - __RW uint32_t ZCMP2; /* 0x80: Z comparator */ - __RW uint32_t PHCMP2; /* 0x84: Phase comparator */ - __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */ - __RW uint32_t MATCH_CFG; /* 0x8C: */ - __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */ - __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */ - __RW uint32_t QEI_CFG; /* 0x100: qei config register */ - __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */ - __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */ - __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */ - __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */ - __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */ - __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */ - __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */ - __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */ - __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */ - __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */ - __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */ - __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */ - __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */ - __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */ - __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */ - __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */ - __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */ - __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */ - __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */ - __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */ - __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */ - __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */ - __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */ - __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */ - __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */ - __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */ - __R uint8_t RESERVED4[104]; /* 0x178 - 0x1DF: Reserved */ - __R uint32_t TIMESTAMP; /* 0x1E0: timestamp */ - __R uint8_t RESERVED5[12]; /* 0x1E4 - 0x1EF: Reserved */ - __RW uint32_t ADC_THRESHOLD; /* 0x1F0: adc_threshold */ - __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */ - __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */ - __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */ - __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */ - __R uint8_t RESERVED7[4]; /* 0x20C - 0x20F: Reserved */ - __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */ - __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */ - __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */ - __R uint8_t RESERVED8[4]; /* 0x21C - 0x21F: Reserved */ - __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */ - __R uint8_t RESERVED9[12]; /* 0x224 - 0x22F: Reserved */ - __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */ - __R uint8_t RESERVED10[4]; /* 0x234 - 0x237: Reserved */ - __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */ - __R uint8_t RESERVED11[4]; /* 0x23C - 0x23F: Reserved */ - __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */ - __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: uvw_pos0_cfg */ - __R uint8_t RESERVED12[16]; /* 0x270 - 0x27F: Reserved */ - __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */ - __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */ - __RW uint32_t POSITION; /* 0x288: position */ - __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */ - __R uint32_t ANGLE; /* 0x290: */ - __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */ -} QEIV2_Type; - - -/* Bitfield definition for register: CR */ -/* - * READ (WO) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 - */ -#define QEIV2_CR_READ_MASK (0x80000000UL) -#define QEIV2_CR_READ_SHIFT (31U) -#define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK) -#define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT) - -/* - * ZCNTCFG (RW) - * - * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 - * 0- zcnt will increment or decrement when Z input assert - */ -#define QEIV2_CR_ZCNTCFG_MASK (0x400000UL) -#define QEIV2_CR_ZCNTCFG_SHIFT (22U) -#define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK) -#define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT) - -/* - * PHCALIZ (RW) - * - * 1- phcnt will set to phidx when Z input assert(for abz digital signsl) - */ -#define QEIV2_CR_PHCALIZ_MASK (0x200000UL) -#define QEIV2_CR_PHCALIZ_SHIFT (21U) -#define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK) -#define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT) - -/* - * Z_ONLY_EN (RW) - * - * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz) - */ -#define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL) -#define QEIV2_CR_Z_ONLY_EN_SHIFT (20U) -#define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK) -#define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT) - -/* - * H2FDIR0 (RW) - * - */ -#define QEIV2_CR_H2FDIR0_MASK (0x80000UL) -#define QEIV2_CR_H2FDIR0_SHIFT (19U) -#define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK) -#define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT) - -/* - * H2FDIR1 (RW) - * - */ -#define QEIV2_CR_H2FDIR1_MASK (0x40000UL) -#define QEIV2_CR_H2FDIR1_SHIFT (18U) -#define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK) -#define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT) - -/* - * H2RDIR0 (RW) - * - */ -#define QEIV2_CR_H2RDIR0_MASK (0x20000UL) -#define QEIV2_CR_H2RDIR0_SHIFT (17U) -#define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK) -#define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT) - -/* - * H2RDIR1 (RW) - * - */ -#define QEIV2_CR_H2RDIR1_MASK (0x10000UL) -#define QEIV2_CR_H2RDIR1_SHIFT (16U) -#define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK) -#define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT) - -/* - * PAUSEPOS (RW) - * - * 1- pause position output valid when PAUSE assert - */ -#define QEIV2_CR_PAUSEPOS_MASK (0x8000U) -#define QEIV2_CR_PAUSEPOS_SHIFT (15U) -#define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK) -#define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT) - -/* - * PAUSESPD (RW) - * - * 1- pause spdcnt when PAUSE assert - */ -#define QEIV2_CR_PAUSESPD_MASK (0x4000U) -#define QEIV2_CR_PAUSESPD_SHIFT (14U) -#define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK) -#define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT) - -/* - * PAUSEPH (RW) - * - * 1- pause phcnt when PAUSE assert - */ -#define QEIV2_CR_PAUSEPH_MASK (0x2000U) -#define QEIV2_CR_PAUSEPH_SHIFT (13U) -#define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK) -#define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT) - -/* - * PAUSEZ (RW) - * - * 1- pause zcnt when PAUSE assert - */ -#define QEIV2_CR_PAUSEZ_MASK (0x1000U) -#define QEIV2_CR_PAUSEZ_SHIFT (12U) -#define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK) -#define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT) - -/* - * HFDIR0 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) - */ -#define QEIV2_CR_HFDIR0_MASK (0x800U) -#define QEIV2_CR_HFDIR0_SHIFT (11U) -#define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK) -#define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT) - -/* - * HFDIR1 (RW) - * - * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) - */ -#define QEIV2_CR_HFDIR1_MASK (0x400U) -#define QEIV2_CR_HFDIR1_SHIFT (10U) -#define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK) -#define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT) - -/* - * HRDIR0 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) - */ -#define QEIV2_CR_HRDIR0_MASK (0x200U) -#define QEIV2_CR_HRDIR0_SHIFT (9U) -#define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK) -#define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT) - -/* - * HRDIR1 (RW) - * - * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) - */ -#define QEIV2_CR_HRDIR1_MASK (0x100U) -#define QEIV2_CR_HRDIR1_SHIFT (8U) -#define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK) -#define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT) - -/* - * FAULTPOS (RW) - * - */ -#define QEIV2_CR_FAULTPOS_MASK (0x40U) -#define QEIV2_CR_FAULTPOS_SHIFT (6U) -#define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK) -#define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT) - -/* - * SNAPEN (RW) - * - * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert - */ -#define QEIV2_CR_SNAPEN_MASK (0x20U) -#define QEIV2_CR_SNAPEN_SHIFT (5U) -#define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK) -#define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT) - -/* - * RSTCNT (RW) - * - * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx - */ -#define QEIV2_CR_RSTCNT_MASK (0x10U) -#define QEIV2_CR_RSTCNT_SHIFT (4U) -#define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK) -#define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT) - -/* - * RD_SEL (RW) - * - * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read, - * width_snap0,width_snap1, timer_snap0, timer_snap1) - * 0 : same as hpm1000/500/500s; - * 1: use width for position; use timer for angle - */ -#define QEIV2_CR_RD_SEL_MASK (0x8U) -#define QEIV2_CR_RD_SEL_SHIFT (3U) -#define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK) -#define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT) - -/* - * ENCTYP (RW) - * - * 000-abz; 001-pd; 010-ud; 011-UVW(hal) - * 100-single A; 101-single sin; 110: sin&cos - */ -#define QEIV2_CR_ENCTYP_MASK (0x7U) -#define QEIV2_CR_ENCTYP_SHIFT (0U) -#define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK) -#define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT) - -/* Bitfield definition for register: PHCFG */ -/* - * PHMAX (RW) - * - * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax - */ -#define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL) -#define QEIV2_PHCFG_PHMAX_SHIFT (0U) -#define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK) -#define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT) - -/* Bitfield definition for register: WDGCFG */ -/* - * WDGEN (RW) - * - * 1- enable wdog counter - */ -#define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL) -#define QEIV2_WDGCFG_WDGEN_SHIFT (31U) -#define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK) -#define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT) - -/* - * WDOG_CFG (RW) - * - * define as stop if phase_cnt change is less than it - * if 0, then each change of phase_cnt will clear wdog counter; - * if 2, then phase_cnt change larger than 2 will clear wdog counter - */ -#define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL) -#define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U) -#define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK) -#define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT) - -/* - * WDGTO (RW) - * - * watch dog timeout value - */ -#define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL) -#define QEIV2_WDGCFG_WDGTO_SHIFT (0U) -#define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK) -#define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT) - -/* Bitfield definition for register: PHIDX */ -/* - * PHIDX (RW) - * - * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 - */ -#define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL) -#define QEIV2_PHIDX_PHIDX_SHIFT (0U) -#define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK) -#define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT) - -/* Bitfield definition for register: TRGOEN */ -/* - * WDGFEN (RW) - * - * 1- enable trigger output when wdg flag set - */ -#define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL) -#define QEIV2_TRGOEN_WDGFEN_SHIFT (31U) -#define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK) -#define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- enable trigger output when homef flag set - */ -#define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL) -#define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U) -#define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK) -#define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- enable trigger output when poscmpf flag set - */ -#define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL) -#define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U) -#define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK) -#define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- enable trigger output when zphf flag set - */ -#define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL) -#define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U) -#define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK) -#define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT) - -/* - * ZMISSFEN (RW) - * - */ -#define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL) -#define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U) -#define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK) -#define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT) - -/* - * WIDTHTMFEN (RW) - * - */ -#define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL) -#define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U) -#define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) -#define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) - -/* - * POS2CMPFEN (RW) - * - */ -#define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL) -#define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U) -#define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK) -#define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT) - -/* - * DIRCHGFEN (RW) - * - */ -#define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL) -#define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U) -#define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK) -#define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT) - -/* - * CYCLE0FEN (RW) - * - */ -#define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL) -#define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U) -#define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK) -#define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT) - -/* - * CYCLE1FEN (RW) - * - */ -#define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL) -#define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U) -#define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK) -#define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT) - -/* - * PULSE0FEN (RW) - * - */ -#define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL) -#define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U) -#define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK) -#define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT) - -/* - * PULSE1FEN (RW) - * - */ -#define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL) -#define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U) -#define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK) -#define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT) - -/* - * HOME2FEN (RW) - * - */ -#define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL) -#define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U) -#define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK) -#define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT) - -/* - * FAULTFEN (RW) - * - */ -#define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL) -#define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U) -#define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK) -#define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT) - -/* Bitfield definition for register: READEN */ -/* - * WDGFEN (RW) - * - * 1- load counters to their read registers when wdg flag set - */ -#define QEIV2_READEN_WDGFEN_MASK (0x80000000UL) -#define QEIV2_READEN_WDGFEN_SHIFT (31U) -#define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK) -#define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- load counters to their read registers when homef flag set - */ -#define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL) -#define QEIV2_READEN_HOMEFEN_SHIFT (30U) -#define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK) -#define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- load counters to their read registers when poscmpf flag set - */ -#define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL) -#define QEIV2_READEN_POSCMPFEN_SHIFT (29U) -#define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK) -#define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- load counters to their read registers when zphf flag set - */ -#define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL) -#define QEIV2_READEN_ZPHFEN_SHIFT (28U) -#define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK) -#define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT) - -/* - * ZMISSFEN (RW) - * - */ -#define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL) -#define QEIV2_READEN_ZMISSFEN_SHIFT (27U) -#define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK) -#define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT) - -/* - * WIDTHTMFEN (RW) - * - */ -#define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL) -#define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U) -#define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK) -#define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT) - -/* - * POS2CMPFEN (RW) - * - */ -#define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL) -#define QEIV2_READEN_POS2CMPFEN_SHIFT (25U) -#define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK) -#define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT) - -/* - * DIRCHGFEN (RW) - * - */ -#define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL) -#define QEIV2_READEN_DIRCHGFEN_SHIFT (24U) -#define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK) -#define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT) - -/* - * CYCLE0FEN (RW) - * - */ -#define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL) -#define QEIV2_READEN_CYCLE0FEN_SHIFT (23U) -#define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK) -#define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT) - -/* - * CYCLE1FEN (RW) - * - */ -#define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL) -#define QEIV2_READEN_CYCLE1FEN_SHIFT (22U) -#define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK) -#define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT) - -/* - * PULSE0FEN (RW) - * - */ -#define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL) -#define QEIV2_READEN_PULSE0FEN_SHIFT (21U) -#define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK) -#define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT) - -/* - * PULSE1FEN (RW) - * - */ -#define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL) -#define QEIV2_READEN_PULSE1FEN_SHIFT (20U) -#define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK) -#define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT) - -/* - * HOME2FEN (RW) - * - */ -#define QEIV2_READEN_HOME2FEN_MASK (0x80000UL) -#define QEIV2_READEN_HOME2FEN_SHIFT (19U) -#define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK) -#define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT) - -/* - * FAULTFEN (RW) - * - */ -#define QEIV2_READEN_FAULTFEN_MASK (0x40000UL) -#define QEIV2_READEN_FAULTFEN_SHIFT (18U) -#define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK) -#define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT) - -/* Bitfield definition for register: ZCMP */ -/* - * ZCMP (RW) - * - * zcnt postion compare value - */ -#define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) -#define QEIV2_ZCMP_ZCMP_SHIFT (0U) -#define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK) -#define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT) - -/* Bitfield definition for register: PHCMP */ -/* - * PHCMP (RW) - * - * phcnt position compare value - */ -#define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL) -#define QEIV2_PHCMP_PHCMP_SHIFT (0U) -#define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK) -#define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT) - -/* Bitfield definition for register: SPDCMP */ -/* - * SPDCMP (RW) - * - * spdcnt position compare value - */ -#define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) -#define QEIV2_SPDCMP_SPDCMP_SHIFT (0U) -#define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK) -#define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT) - -/* Bitfield definition for register: DMAEN */ -/* - * WDGFEN (RW) - * - * 1- generate dma request when wdg flag set - */ -#define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL) -#define QEIV2_DMAEN_WDGFEN_SHIFT (31U) -#define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK) -#define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT) - -/* - * HOMEFEN (RW) - * - * 1- generate dma request when homef flag set - */ -#define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL) -#define QEIV2_DMAEN_HOMEFEN_SHIFT (30U) -#define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK) -#define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT) - -/* - * POSCMPFEN (RW) - * - * 1- generate dma request when poscmpf flag set - */ -#define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL) -#define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U) -#define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK) -#define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT) - -/* - * ZPHFEN (RW) - * - * 1- generate dma request when zphf flag set - */ -#define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL) -#define QEIV2_DMAEN_ZPHFEN_SHIFT (28U) -#define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK) -#define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT) - -/* - * ZMISSFEN (RW) - * - */ -#define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL) -#define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U) -#define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK) -#define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT) - -/* - * WIDTHTMFEN (RW) - * - */ -#define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL) -#define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U) -#define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK) -#define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT) - -/* - * POS2CMPFEN (RW) - * - */ -#define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL) -#define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U) -#define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK) -#define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT) - -/* - * DIRCHGFEN (RW) - * - */ -#define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL) -#define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U) -#define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK) -#define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT) - -/* - * CYCLE0FEN (RW) - * - */ -#define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL) -#define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U) -#define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK) -#define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT) - -/* - * CYCLE1FEN (RW) - * - */ -#define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL) -#define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U) -#define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK) -#define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT) - -/* - * PULSE0FEN (RW) - * - */ -#define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL) -#define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U) -#define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK) -#define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT) - -/* - * PULSE1FEN (RW) - * - */ -#define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL) -#define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U) -#define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK) -#define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT) - -/* - * HOME2FEN (RW) - * - */ -#define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL) -#define QEIV2_DMAEN_HOME2FEN_SHIFT (19U) -#define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK) -#define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT) - -/* - * FAULTFEN (RW) - * - */ -#define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL) -#define QEIV2_DMAEN_FAULTFEN_SHIFT (18U) -#define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK) -#define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT) - -/* Bitfield definition for register: SR */ -/* - * WDGF (RW) - * - * watchdog flag - */ -#define QEIV2_SR_WDGF_MASK (0x80000000UL) -#define QEIV2_SR_WDGF_SHIFT (31U) -#define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK) -#define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT) - -/* - * HOMEF (RW) - * - * home flag - */ -#define QEIV2_SR_HOMEF_MASK (0x40000000UL) -#define QEIV2_SR_HOMEF_SHIFT (30U) -#define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK) -#define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT) - -/* - * POSCMPF (RW) - * - * postion compare match flag - */ -#define QEIV2_SR_POSCMPF_MASK (0x20000000UL) -#define QEIV2_SR_POSCMPF_SHIFT (29U) -#define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK) -#define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT) - -/* - * ZPHF (RW) - * - * z input flag - */ -#define QEIV2_SR_ZPHF_MASK (0x10000000UL) -#define QEIV2_SR_ZPHF_SHIFT (28U) -#define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK) -#define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT) - -/* - * ZMISSF (RW) - * - */ -#define QEIV2_SR_ZMISSF_MASK (0x8000000UL) -#define QEIV2_SR_ZMISSF_SHIFT (27U) -#define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK) -#define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT) - -/* - * WIDTHTMF (RW) - * - */ -#define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL) -#define QEIV2_SR_WIDTHTMF_SHIFT (26U) -#define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK) -#define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT) - -/* - * POS2CMPF (RW) - * - */ -#define QEIV2_SR_POS2CMPF_MASK (0x2000000UL) -#define QEIV2_SR_POS2CMPF_SHIFT (25U) -#define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK) -#define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT) - -/* - * DIRCHGF (RW) - * - */ -#define QEIV2_SR_DIRCHGF_MASK (0x1000000UL) -#define QEIV2_SR_DIRCHGF_SHIFT (24U) -#define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK) -#define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT) - -/* - * CYCLE0F (RW) - * - */ -#define QEIV2_SR_CYCLE0F_MASK (0x800000UL) -#define QEIV2_SR_CYCLE0F_SHIFT (23U) -#define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK) -#define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT) - -/* - * CYCLE1F (RW) - * - */ -#define QEIV2_SR_CYCLE1F_MASK (0x400000UL) -#define QEIV2_SR_CYCLE1F_SHIFT (22U) -#define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK) -#define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT) - -/* - * PULSE0F (RW) - * - */ -#define QEIV2_SR_PULSE0F_MASK (0x200000UL) -#define QEIV2_SR_PULSE0F_SHIFT (21U) -#define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK) -#define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT) - -/* - * PULSE1F (RW) - * - */ -#define QEIV2_SR_PULSE1F_MASK (0x100000UL) -#define QEIV2_SR_PULSE1F_SHIFT (20U) -#define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK) -#define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT) - -/* - * HOME2F (RW) - * - */ -#define QEIV2_SR_HOME2F_MASK (0x80000UL) -#define QEIV2_SR_HOME2F_SHIFT (19U) -#define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK) -#define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT) - -/* - * FAULTF (RW) - * - */ -#define QEIV2_SR_FAULTF_MASK (0x40000UL) -#define QEIV2_SR_FAULTF_SHIFT (18U) -#define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK) -#define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT) - -/* Bitfield definition for register: IRQEN */ -/* - * WDGIE (RW) - * - * 1- generate interrupt when wdg flag set - */ -#define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL) -#define QEIV2_IRQEN_WDGIE_SHIFT (31U) -#define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK) -#define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT) - -/* - * HOMEIE (RW) - * - * 1- generate interrupt when homef flag set - */ -#define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL) -#define QEIV2_IRQEN_HOMEIE_SHIFT (30U) -#define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK) -#define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT) - -/* - * POSCMPIE (RW) - * - * 1- generate interrupt when poscmpf flag set - */ -#define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL) -#define QEIV2_IRQEN_POSCMPIE_SHIFT (29U) -#define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK) -#define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT) - -/* - * ZPHIE (RW) - * - * 1- generate interrupt when zphf flag set - */ -#define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL) -#define QEIV2_IRQEN_ZPHIE_SHIFT (28U) -#define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK) -#define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT) - -/* - * ZMISSE (RW) - * - */ -#define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL) -#define QEIV2_IRQEN_ZMISSE_SHIFT (27U) -#define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK) -#define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT) - -/* - * WIDTHTME (RW) - * - */ -#define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL) -#define QEIV2_IRQEN_WIDTHTME_SHIFT (26U) -#define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK) -#define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT) - -/* - * POS2CMPE (RW) - * - */ -#define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL) -#define QEIV2_IRQEN_POS2CMPE_SHIFT (25U) -#define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK) -#define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT) - -/* - * DIRCHGE (RW) - * - */ -#define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL) -#define QEIV2_IRQEN_DIRCHGE_SHIFT (24U) -#define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK) -#define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT) - -/* - * CYCLE0E (RW) - * - */ -#define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL) -#define QEIV2_IRQEN_CYCLE0E_SHIFT (23U) -#define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK) -#define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT) - -/* - * CYCLE1E (RW) - * - */ -#define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL) -#define QEIV2_IRQEN_CYCLE1E_SHIFT (22U) -#define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK) -#define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT) - -/* - * PULSE0E (RW) - * - */ -#define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL) -#define QEIV2_IRQEN_PULSE0E_SHIFT (21U) -#define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK) -#define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT) - -/* - * PULSE1E (RW) - * - */ -#define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL) -#define QEIV2_IRQEN_PULSE1E_SHIFT (20U) -#define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK) -#define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT) - -/* - * HOME2E (RW) - * - */ -#define QEIV2_IRQEN_HOME2E_MASK (0x80000UL) -#define QEIV2_IRQEN_HOME2E_SHIFT (19U) -#define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK) -#define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT) - -/* - * FAULTE (RW) - * - */ -#define QEIV2_IRQEN_FAULTE_MASK (0x40000UL) -#define QEIV2_IRQEN_FAULTE_SHIFT (18U) -#define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK) -#define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT) - -/* Bitfield definition for register of struct array COUNT: Z */ -/* - * ZCNT (RW) - * - * zcnt value - */ -#define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) -#define QEIV2_COUNT_Z_ZCNT_SHIFT (0U) -#define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK) -#define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: PH */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL) -#define QEIV2_COUNT_PH_DIR_SHIFT (30U) -#define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL) -#define QEIV2_COUNT_PH_ASTAT_SHIFT (26U) -#define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT) - -/* - * BSTAT (RO) - * - * 1- b input is high - * 0- b input is low - */ -#define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL) -#define QEIV2_COUNT_PH_BSTAT_SHIFT (25U) -#define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT) - -/* - * PHCNT (RO) - * - * phcnt value - */ -#define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) -#define QEIV2_COUNT_PH_PHCNT_SHIFT (0U) -#define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: SPD */ -/* - * DIR (RO) - * - * 1- reverse rotation - * 0- forward rotation - */ -#define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL) -#define QEIV2_COUNT_SPD_DIR_SHIFT (31U) -#define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT) - -/* - * ASTAT (RO) - * - * 1- a input is high - * 0- a input is low - */ -#define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL) -#define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U) -#define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT) - -/* - * BSTAT (RW) - * - * 1- b input is high - * 0- b input is low - */ -#define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL) -#define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U) -#define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK) -#define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT) - -/* - * SPDCNT (RO) - * - * spdcnt value - */ -#define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) -#define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U) -#define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT) - -/* Bitfield definition for register of struct array COUNT: TMR */ -/* - * TMRCNT (RO) - * - * 32 bit free run timer - */ -#define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) -#define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U) -#define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT) - -/* Bitfield definition for register: ZCMP2 */ -/* - * ZCMP2 (RW) - * - */ -#define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL) -#define QEIV2_ZCMP2_ZCMP2_SHIFT (0U) -#define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK) -#define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT) - -/* Bitfield definition for register: PHCMP2 */ -/* - * PHCMP2 (RW) - * - */ -#define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL) -#define QEIV2_PHCMP2_PHCMP2_SHIFT (0U) -#define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK) -#define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT) - -/* Bitfield definition for register: SPDCMP2 */ -/* - * SPDCMP2 (RW) - * - */ -#define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL) -#define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U) -#define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK) -#define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT) - -/* Bitfield definition for register: MATCH_CFG */ -/* - * ZCMPDIS (RW) - * - * 1- postion compare not include zcnt - */ -#define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL) -#define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U) -#define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) -#define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) - -/* - * DIRCMPDIS (RW) - * - * 1- postion compare not include rotation direction - */ -#define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL) -#define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U) -#define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) -#define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) - -/* - * DIRCMP (RW) - * - * 0- position compare need positive rotation - * 1- position compare need negative rotation - */ -#define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL) -#define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U) -#define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK) -#define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT) - -/* - * SPDCMPDIS (RW) - * - */ -#define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL) -#define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U) -#define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) -#define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) - -/* - * PHASE_MATCH_DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) - -/* - * POS_MATCH_DIR (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL) -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U) -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) - -/* - * POS_MATCH_OPT (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL) -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U) -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) - -/* - * ZCMP2DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U) -#define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U) -#define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) -#define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) - -/* - * DIRCMP2DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U) -#define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U) -#define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) -#define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) - -/* - * DIRCMP2 (RW) - * - */ -#define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U) -#define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U) -#define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK) -#define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT) - -/* - * SPDCMP2DIS (RW) - * - */ -#define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U) -#define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U) -#define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) -#define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) - -/* - * PHASE_MATCH_DIS2 (RW) - * - */ -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) -#define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) - -/* - * POS_MATCH2_DIR (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U) -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U) -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) - -/* - * POS_MATCH2_OPT (RW) - * - */ -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U) -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U) -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) -#define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) - -/* Bitfield definition for register array: FILT_CFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL) -#define QEIV2_FILT_CFG_OUTINV_SHIFT (16U) -#define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK) -#define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stable low mode; - * 111-stable high mode - */ -#define QEIV2_FILT_CFG_MODE_MASK (0xE000U) -#define QEIV2_FILT_CFG_MODE_SHIFT (13U) -#define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK) -#define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U) -#define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U) -#define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK) -#define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT) - -/* - * FILTLEN (RW) - * - * This bitfields defines the filter counter length. - */ -#define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU) -#define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U) -#define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK) -#define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT) - -/* Bitfield definition for register: QEI_CFG */ -/* - * SW_PULSE0_RESTART (RW) - * - * set to restart cycle counter for configed pulse_num. HW auto clear - */ -#define QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK (0x80000000UL) -#define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT (31U) -#define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) -#define QEIV2_QEI_CFG_SW_PULSE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) - -/* - * SW_PULSE1_RESTART (RW) - * - */ -#define QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK (0x40000000UL) -#define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT (30U) -#define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) -#define QEIV2_QEI_CFG_SW_PULSE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) - -/* - * SW_CYCLE0_RESTART (RW) - * - * set to restart pulse counter for configed cycle_num. HW auto clear - */ -#define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK (0x20000000UL) -#define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT (29U) -#define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) -#define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) - -/* - * SW_CYCLE1_RESTART (RW) - * - */ -#define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK (0x10000000UL) -#define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT (28U) -#define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) -#define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) - -/* - * PULSE0_ONESHOT (RW) - * - * set to use oneshot mode for configed pulse_num - */ -#define QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK (0x80000UL) -#define QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT (19U) -#define QEIV2_QEI_CFG_PULSE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) -#define QEIV2_QEI_CFG_PULSE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) - -/* - * PULSE1_ONESHOT (RW) - * - */ -#define QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK (0x40000UL) -#define QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT (18U) -#define QEIV2_QEI_CFG_PULSE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) -#define QEIV2_QEI_CFG_PULSE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) - -/* - * CYCLE0_ONESHOT (RW) - * - * set to use oneshot mode for configed cycle_num - */ -#define QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK (0x20000UL) -#define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT (17U) -#define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) -#define QEIV2_QEI_CFG_CYCLE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) - -/* - * CYCLE1_ONESHOT (RW) - * - */ -#define QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK (0x10000UL) -#define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT (16U) -#define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) -#define QEIV2_QEI_CFG_CYCLE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) - -/* - * SPEED_DIR_CHG_EN (RW) - * - * clear counter if detect direction change - */ -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U) -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U) -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) -#define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) - -/* - * TRIG_PULSE0_EN (RW) - * - * set to enable trigger start cycle counter for configed pulse_num(from the selected edge) - */ -#define QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK (0x800U) -#define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT (11U) -#define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) -#define QEIV2_QEI_CFG_TRIG_PULSE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) - -/* - * TRIG_PULSE1_EN (RW) - * - */ -#define QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK (0x400U) -#define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT (10U) -#define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) -#define QEIV2_QEI_CFG_TRIG_PULSE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) - -/* - * TRIG_CYCLE0_EN (RW) - * - * set to enable trigger start pulse counter for configed cycle_num - */ -#define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK (0x200U) -#define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT (9U) -#define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) -#define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) - -/* - * TRIG_CYCLE1_EN (RW) - * - */ -#define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK (0x100U) -#define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT (8U) -#define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) -#define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) - -/* - * UVW_POS_OPT0 (RW) - * - * set to output next area position for QEO use; - * clr to output exact point position for MMC use - */ -#define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U) -#define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U) -#define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) -#define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) - -/* - * NEGEDGE_EN (RW) - * - * bit4: negedge enable - * bit3: posedge enable - * bit2: W in hal enable - * bit1: signal b(or V in hal) enable - * bit0: signal a(or U in hal) enable - * such as: - * 01001: use posedge A - * 11010: use both edge of signal B - * 11111: use both edge of all HAL siganls - */ -#define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U) -#define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U) -#define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) -#define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) - -/* - * POSIDGE_EN (RW) - * - */ -#define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U) -#define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U) -#define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) -#define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) - -/* - * SIGZ_EN (RW) - * - */ -#define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U) -#define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U) -#define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK) -#define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT) - -/* - * SIGB_EN (RW) - * - */ -#define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U) -#define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U) -#define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK) -#define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT) - -/* - * SIGA_EN (RW) - * - */ -#define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U) -#define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U) -#define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK) -#define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT) - -/* Bitfield definition for register: PULSE0_NUM */ -/* - * PULSE0_NUM (RW) - * - * for speed detection, will count the cycle number for configed pulse_num - */ -#define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U) -#define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) -#define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) - -/* Bitfield definition for register: PULSE1_NUM */ -/* - * PULSE1_NUM (RW) - * - */ -#define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U) -#define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) -#define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) - -/* Bitfield definition for register: CYCLE0_CNT */ -/* - * CYCLE0_CNT (RO) - * - */ -#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U) -#define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE0PULSE_CNT */ -/* - * CYCLE0PULSE_CNT (RO) - * - */ -#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U) -#define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE1_CNT */ -/* - * CYCLE1_CNT (RO) - * - */ -#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U) -#define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE1PULSE_CNT */ -/* - * CYCLE1PULSE_CNT (RO) - * - */ -#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U) -#define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT) - -/* Bitfield definition for register: CYCLE0_SNAP0 */ -/* - * CYCLE0_SNAP0 (RO) - * - */ -#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U) -#define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT) - -/* Bitfield definition for register: CYCLE0_SNAP1 */ -/* - * CYCLE0_SNAP1 (RO) - * - */ -#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U) -#define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT) - -/* Bitfield definition for register: CYCLE1_SNAP0 */ -/* - * CYCLE1_SNAP0 (RO) - * - */ -#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U) -#define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT) - -/* Bitfield definition for register: CYCLE1_SNAP1 */ -/* - * CYCLE1_SNAP1 (RO) - * - */ -#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U) -#define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT) - -/* Bitfield definition for register: CYCLE0_NUM */ -/* - * CYCLE0_NUM (RW) - * - */ -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U) -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) -#define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) - -/* Bitfield definition for register: CYCLE1_NUM */ -/* - * CYCLE1_NUM (RW) - * - */ -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL) -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U) -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) -#define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) - -/* Bitfield definition for register: PULSE0_CNT */ -/* - * PULSE0_CNT (RO) - * - */ -#define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U) -#define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT) - -/* Bitfield definition for register: PULSE0CYCLE_CNT */ -/* - * PULSE0CYCLE_CNT (RO) - * - */ -#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U) -#define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT) - -/* Bitfield definition for register: PULSE1_CNT */ -/* - * PULSE1_CNT (RO) - * - */ -#define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U) -#define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT) - -/* Bitfield definition for register: PULSE1CYCLE_CNT */ -/* - * PULSE1CYCLE_CNT (RO) - * - */ -#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U) -#define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT) - -/* Bitfield definition for register: PULSE0_SNAP0 */ -/* - * PULSE0_SNAP0 (RO) - * - */ -#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U) -#define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE0CYCLE_SNAP0 */ -/* - * PULSE0CYCLE_SNAP0 (RO) - * - */ -#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U) -#define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE0_SNAP1 */ -/* - * PULSE0_SNAP1 (RO) - * - */ -#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U) -#define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT) - -/* Bitfield definition for register: PULSE0CYCLE_SNAP1 */ -/* - * PULSE0CYCLE_SNAP1 (RO) - * - */ -#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U) -#define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT) - -/* Bitfield definition for register: PULSE1_SNAP0 */ -/* - * PULSE1_SNAP0 (RO) - * - */ -#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U) -#define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE1CYCLE_SNAP0 */ -/* - * PULSE1CYCLE_SNAP0 (RO) - * - */ -#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U) -#define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT) - -/* Bitfield definition for register: PULSE1_SNAP1 */ -/* - * PULSE1_SNAP1 (RO) - * - */ -#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U) -#define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT) - -/* Bitfield definition for register: PULSE1CYCLE_SNAP1 */ -/* - * PULSE1CYCLE_SNAP1 (RO) - * - */ -#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL) -#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U) -#define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT) - -/* Bitfield definition for register: TIMESTAMP */ -/* - * TIMESTAMP (RO) - * - * for SIN/COS mode, it saves the timestampe of the begining of first ADC sample time; - * for ABZ mode, it saves the timestampe of edge of input signals - */ -#define QEIV2_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL) -#define QEIV2_TIMESTAMP_TIMESTAMP_SHIFT (0U) -#define QEIV2_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & QEIV2_TIMESTAMP_TIMESTAMP_MASK) >> QEIV2_TIMESTAMP_TIMESTAMP_SHIFT) - -/* Bitfield definition for register: ADC_THRESHOLD */ -/* - * LOW_LIMIT (RW) - * - * for SINCOS mode, if (max+min/2) of the two adc result, is small than limit, - * then this value is treated as unvalid, no position output. - * this is uesd to avoid wrong adc resule(such as 0 or same sin cos value) - */ -#define QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK (0xFFFF0000UL) -#define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT (16U) -#define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) -#define QEIV2_ADC_THRESHOLD_LOW_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) - -/* - * HIGH_LIMIT (RW) - * - * high limit for SINCOS mode adc result - */ -#define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK (0xFFFFU) -#define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT (0U) -#define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) -#define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) - -/* Bitfield definition for register: ADCX_CFG0 */ -/* - * X_ADCSEL (RW) - * - */ -#define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U) -#define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U) -#define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) -#define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) - -/* - * X_ADC_ENABLE (RW) - * - */ -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U) -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U) -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) -#define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) - -/* - * X_CHAN (RW) - * - */ -#define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU) -#define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U) -#define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK) -#define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT) - -/* Bitfield definition for register: ADCX_CFG1 */ -/* - * X_PARAM1 (RW) - * - */ -#define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL) -#define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U) -#define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) -#define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) - -/* - * X_PARAM0 (RW) - * - */ -#define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU) -#define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U) -#define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) -#define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) - -/* Bitfield definition for register: ADCX_CFG2 */ -/* - * X_OFFSET (RW) - * - */ -#define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL) -#define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U) -#define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) -#define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) - -/* Bitfield definition for register: ADCY_CFG0 */ -/* - * Y_ADCSEL (RW) - * - */ -#define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U) -#define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U) -#define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) -#define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) - -/* - * Y_ADC_ENABLE (RW) - * - */ -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U) -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U) -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) -#define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) - -/* - * Y_CHAN (RW) - * - */ -#define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU) -#define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U) -#define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) -#define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) - -/* Bitfield definition for register: ADCY_CFG1 */ -/* - * Y_PARAM1 (RW) - * - */ -#define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL) -#define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U) -#define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) -#define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) - -/* - * Y_PARAM0 (RW) - * - */ -#define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU) -#define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U) -#define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) -#define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) - -/* Bitfield definition for register: ADCY_CFG2 */ -/* - * Y_OFFSET (RW) - * - */ -#define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL) -#define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U) -#define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) -#define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) - -/* Bitfield definition for register: CAL_CFG */ -/* - * XY_DELAY (RW) - * - * valid x/y delay, larger than this delay will be treated as invalid data. - * Default 1.25us@200MHz; max 80ms; - */ -#define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL) -#define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U) -#define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK) -#define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT) - -/* Bitfield definition for register: PHASE_PARAM */ -/* - * PHASE_PARAM (RW) - * - */ -#define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL) -#define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U) -#define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) -#define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) - -/* Bitfield definition for register: POS_THRESHOLD */ -/* - * POS_THRESHOLD (RW) - * - */ -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL) -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U) -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) -#define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) - -/* Bitfield definition for register array: UVW_POS */ -/* - * UVW_POS0 (RW) - * - */ -#define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL) -#define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U) -#define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK) -#define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT) - -/* Bitfield definition for register array: UVW_POS_CFG */ -/* - * POS_EN (RW) - * - */ -#define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U) -#define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U) -#define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK) -#define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT) - -/* - * U_POS_SEL (RW) - * - */ -#define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U) -#define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U) -#define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) -#define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) - -/* - * V_POS_SEL (RW) - * - */ -#define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU) -#define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U) -#define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) -#define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) - -/* - * W_POS_SEL (RW) - * - */ -#define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U) -#define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U) -#define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) -#define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) - -/* Bitfield definition for register: PHASE_CNT */ -/* - * PHASE_CNT (RW) - * - */ -#define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL) -#define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U) -#define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) -#define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) - -/* Bitfield definition for register: PHASE_UPDATE */ -/* - * INC (WO) - * - * set to add value to phase_cnt - */ -#define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL) -#define QEIV2_PHASE_UPDATE_INC_SHIFT (31U) -#define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK) -#define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT) - -/* - * DEC (WO) - * - * set to minus value from phase_cnt(set inc and dec same time willl act inc) - */ -#define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL) -#define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U) -#define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK) -#define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT) - -/* - * VALUE (WO) - * - * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation - */ -#define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL) -#define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U) -#define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK) -#define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT) - -/* Bitfield definition for register: POSITION */ -/* - * POSITION (RW) - * - */ -#define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL) -#define QEIV2_POSITION_POSITION_SHIFT (0U) -#define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK) -#define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT) - -/* Bitfield definition for register: POSITION_UPDATE */ -/* - * INC (WO) - * - * set to add value to position - */ -#define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL) -#define QEIV2_POSITION_UPDATE_INC_SHIFT (31U) -#define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK) -#define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT) - -/* - * DEC (WO) - * - * set to minus value from position(set inc and dec same time willl act inc) - */ -#define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL) -#define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U) -#define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK) -#define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT) - -/* - * VALUE (WO) - * - * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation - */ -#define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL) -#define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U) -#define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK) -#define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT) - -/* Bitfield definition for register: ANGLE */ -/* - * ANGLE (RO) - * - */ -#define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL) -#define QEIV2_ANGLE_ANGLE_SHIFT (0U) -#define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT) - -/* Bitfield definition for register: POS_TIMEOUT */ -/* - * ENABLE (RW) - * - * enable position timeout feature, if timeout, send valid again - */ -#define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL) -#define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U) -#define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK) -#define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT) - -/* - * TIMEOUT (RW) - * - * postion timeout value - */ -#define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL) -#define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U) -#define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) -#define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) - - - -/* COUNT register group index macro definition */ -#define QEIV2_COUNT_CURRENT (0UL) -#define QEIV2_COUNT_READ (1UL) -#define QEIV2_COUNT_SNAP0 (2UL) -#define QEIV2_COUNT_SNAP1 (3UL) - -/* FILT_CFG register group index macro definition */ -#define QEIV2_FILT_CFG_FILT_CFG_A (0UL) -#define QEIV2_FILT_CFG_FILT_CFG_B (1UL) -#define QEIV2_FILT_CFG_FILT_CFG_Z (2UL) -#define QEIV2_FILT_CFG_FILT_CFG_H (3UL) -#define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL) -#define QEIV2_FILT_CFG_FILT_CFG_F (5UL) - -/* UVW_POS register group index macro definition */ -#define QEIV2_UVW_POS_UVW_POS0 (0UL) -#define QEIV2_UVW_POS_UVW_POS1 (1UL) -#define QEIV2_UVW_POS_UVW_POS2 (2UL) -#define QEIV2_UVW_POS_UVW_POS3 (3UL) -#define QEIV2_UVW_POS_UVW_POS4 (4UL) -#define QEIV2_UVW_POS_UVW_POS5 (5UL) - -/* UVW_POS_CFG register group index macro definition */ -#define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL) -#define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL) -#define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL) -#define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL) -#define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL) -#define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL) - - -#endif /* HPM_QEIV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_qeov2_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_qeov2_regs.h deleted file mode 100644 index b3952f6a39a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_qeov2_regs.h +++ /dev/null @@ -1,1212 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_QEOV2_H -#define HPM_QEOV2_H - -typedef struct { - struct { - __RW uint32_t MODE; /* 0x0: analog waves mode */ - __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */ - __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */ - __RW uint32_t VD_INJECT; /* 0x14: wave vd inject value */ - __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t VQ_INJECT; /* 0x20: wave vq inject value */ - __R uint8_t RESERVED1[8]; /* 0x24 - 0x2B: Reserved */ - __W uint32_t VD_VQ_LOAD; /* 0x2C: load wave0/1/2 vd vq value */ - __RW uint32_t AMPLITUDE[3]; /* 0x30 - 0x38: wave0 amplitude */ - __RW uint32_t MID_POINT[3]; /* 0x3C - 0x44: wave0 output middle point offset */ - struct { - __RW uint32_t MIN_LEVEL0; /* 0x48: wave0 low area limit value */ - __RW uint32_t MAX_LEVEL0; /* 0x4C: wave0 high area limit value */ - } LIMIT0[3]; - struct { - __RW uint32_t MIN_LEVEL1; /* 0x60: wave0 low area limit value level1 */ - __RW uint32_t MAX_LEVEL1; /* 0x64: wave0 high area limit value level1 */ - } LIMIT1[3]; - __RW uint32_t DEADZONE_SHIFT[3]; /* 0x78 - 0x80: deadzone_shifter_wave0 */ - __RW uint32_t PWM_CYCLE; /* 0x84: pwm_cycle */ - } WAVE; - __R uint8_t RESERVED0[120]; /* 0x88 - 0xFF: Reserved */ - struct { - __RW uint32_t MODE; /* 0x100: wave_a/b/z output mode */ - __RW uint32_t RESOLUTION; /* 0x104: resolution of wave_a/b/z */ - __RW uint32_t PHASE_SHIFT[3]; /* 0x108 - 0x110: wave_a phase shifter */ - __RW uint32_t LINE_WIDTH; /* 0x114: Two-phase orthogonality wave 1/4 period */ - __RW uint32_t WDOG_WIDTH; /* 0x118: wdog width of qeo */ - __W uint32_t POSTION_SYNC; /* 0x11C: sync abz owned postion */ - __RW uint32_t OVERALL_OFFSET; /* 0x120: abz overall position offset */ - __RW uint32_t Z_START; /* 0x124: zero phase start line num */ - __RW uint32_t Z_END; /* 0x128: zero phase end line num */ - __RW uint32_t Z_OFFSET; /* 0x12C: zero phase start and end 1/4 line num */ - __RW uint32_t Z_PULSE_WIDTH; /* 0x130: zero pulse witdth */ - } ABZ; - __R uint8_t RESERVED1[12]; /* 0x134 - 0x13F: Reserved */ - struct { - __RW uint32_t MODE; /* 0x140: pwm mode */ - __RW uint32_t RESOLUTION; /* 0x144: resolution of pwm */ - __RW uint32_t PHASE_SHIFT[4]; /* 0x148 - 0x154: pwm_a phase shifter */ - __RW uint32_t PHASE_TABLE[24]; /* 0x158 - 0x1B4: pwm_phase_table 0 */ - } PWM; - __R uint8_t RESERVED2[64]; /* 0x1B8 - 0x1F7: Reserved */ - __RW uint32_t POSTION_SOFTWARE; /* 0x1F8: softwave inject postion */ - __RW uint32_t POSTION_SEL; /* 0x1FC: select softwave inject postion */ - __R uint32_t STATUS; /* 0x200: qeo status */ - __R uint32_t DEBUG0; /* 0x204: qeo debug 0 */ - __R uint32_t DEBUG1; /* 0x208: qeo debug 1 */ - __R uint32_t DEBUG2; /* 0x20C: qeo debug 2 */ - __R uint32_t DEBUG3; /* 0x210: qeo debug 3 */ - __R uint32_t DEBUG4; /* 0x214: qeo debug 4 */ - __R uint32_t DEBUG5; /* 0x218: qeo debug 5 */ -} QEOV2_Type; - - -/* Bitfield definition for register of struct WAVE: MODE */ -/* - * WAVE2_ABOVE_MAX_LIMIT (RW) - * - * wave2 above max limit mode. - * 0: output all bits are 1. - * 1: output 0x0. - * 2: output as level_max_limit2.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL) -#define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U) -#define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) - -/* - * WAVE2_HIGH_AREA1_LIMIT (RW) - * - * wave2 high area1 limit mode. - * 0: output all bits are 1. - * 1: output as level_max_limit2.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL) -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U) -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) - -/* - * WAVE2_HIGH_AREA0_LIMIT (RW) - * - * wave2 high area0 limit mode. - * 0: output all bits are 1. - * 1: output as level_max_limit2.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL) -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U) -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) - -/* - * WAVE2_LOW_AREA1_LIMIT (RW) - * - * wave2 low area1 limit mode. - * 0: output 0. - * 1: output as level_min_limit2.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL) -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U) -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) - -/* - * WAVE2_LOW_AREA0_LIMIT (RW) - * - * wave2 low area0 limit mode. - * 0: output 0. - * 1: output as level_min_limit2.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL) -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U) -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) - -/* - * WAVE2_BELOW_MIN_LIMIT (RW) - * - * wave2 below min limit mode. - * 0: output 0. - * 1: output all bits are 1. - * 2: output as level_min_limit2.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL) -#define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U) -#define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) - -/* - * WAVE1_ABOVE_MAX_LIMIT (RW) - * - * wave1 above max limit mode. - * 0: output all bits are 1. - * 1: output 0x0. - * 2: output as level_max_limit1.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL) -#define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U) -#define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) - -/* - * WAVE1_HIGH_AREA1_LIMIT (RW) - * - * wave1 high area1 limit mode. - * 0: output all bits are 1. - * 1: output as level_max_limit1.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL) -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U) -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) - -/* - * WAVE1_HIGH_AREA0_LIMIT (RW) - * - * wave1 high area0 limit mode. - * 0: output all bits are 1. - * 1: output as level_max_limit1.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL) -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U) -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) - -/* - * WAVE1_LOW_AREA1_LIMIT (RW) - * - * wave1 low area1 limit mode. - * 0: output 0. - * 1: output as level_min_limit1.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL) -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U) -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) - -/* - * WAVE1_LOW_AREA0_LIMIT (RW) - * - * wave1 low area0 limit mode. - * 0: output 0. - * 1: output as level_min_limit1.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL) -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U) -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) - -/* - * WAVE1_BELOW_MIN_LIMIT (RW) - * - * wave1 below min limit mode. - * 0: output 0. - * 1: output all bits are 1. - * 2: output as level_min_limit1.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL) -#define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U) -#define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) - -/* - * WAVE0_ABOVE_MAX_LIMIT (RW) - * - * wave0 above max limit mode. - * 0: output all bits are 1. - * 1: output 0x0. - * 2: output as level_max_limit0.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U) -#define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U) -#define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) - -/* - * WAVE0_HIGH_AREA1_LIMIT (RW) - * - * wave0 high area1 limit mode. - * 0: output all bits are 1. - * 1: output as level_max_limit0.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U) -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U) -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) - -/* - * WAVE0_HIGH_AREA0_LIMIT (RW) - * - * wave0 high area0 limit mode. - * 0: output all bits are 1. - * 1: output as level_max_limit0.level0_max_limit - */ -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U) -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U) -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) - -/* - * WAVE0_LOW_AREA1_LIMIT (RW) - * - * wave0 low area1 limit mode. - * 0: output 0. - * 1: output as level_min_limit0.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U) -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U) -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) - -/* - * WAVE0_LOW_AREA0_LIMIT (RW) - * - * wave0 low area0 limit mode. - * 0: output 0. - * 1: output as level_min_limit0.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U) -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U) -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) - -/* - * WAVE0_BELOW_MIN_LIMIT (RW) - * - * wave0 below min limit mode. - * 0: output 0. - * 1: output all bits are 1. - * 2: output as level_min_limit0.level1_min_limit - */ -#define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U) -#define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U) -#define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) -#define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) - -/* - * SADDLE_TYPE (RW) - * - * saddle type seclect; - * 0:standard saddle. - * 1: triple-cos saddle. - */ -#define QEOV2_WAVE_MODE_SADDLE_TYPE_MASK (0x80U) -#define QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT (7U) -#define QEOV2_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK) -#define QEOV2_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK) >> QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT) - -/* - * ENABLE_DQ_VALID (RW) - * - * enable vd or vq valid to trigger analog wave calcuation - * 0: disable. - * 1: enable. - */ -#define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK (0x40U) -#define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT (6U) -#define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK) -#define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT) - -/* - * ENABLE_POS_VALID (RW) - * - * enable position valid to trigger analog wave calcuation - * 0: disable. - * 1: enable. - */ -#define QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK (0x20U) -#define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT (5U) -#define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK) -#define QEOV2_WAVE_MODE_ENABLE_POS_VALID_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT) - -/* - * EN_WAVE_VD_VQ_INJECT (RW) - * - * wave VdVq inject enable. - * 0: disable VdVq inject. - * 1: enable VdVq inject. - */ -#define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK (0x10U) -#define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT (4U) -#define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK) -#define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK) >> QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT) - -/* - * VD_VQ_SEL (RW) - * - * vd_vq sel ctrl: - * 0: from CLC. - * 1: from software. - */ -#define QEOV2_WAVE_MODE_VD_VQ_SEL_MASK (0x4U) -#define QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT (2U) -#define QEOV2_WAVE_MODE_VD_VQ_SEL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK) -#define QEOV2_WAVE_MODE_VD_VQ_SEL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK) >> QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT) - -/* - * WAVES_OUTPUT_TYPE (RW) - * - * wave0/1/2 output mode. - * 0: cosine wave. - * 1: saddle wave. - * 2. abs cosine wave. - * 3. saw wave - */ -#define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U) -#define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U) -#define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) -#define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) - -/* Bitfield definition for register of struct WAVE: RESOLUTION */ -/* - * LINES (RW) - * - * wave0/1/2 resolution - */ -#define QEOV2_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_RESOLUTION_LINES_SHIFT (0U) -#define QEOV2_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_WAVE_RESOLUTION_LINES_SHIFT) & QEOV2_WAVE_RESOLUTION_LINES_MASK) -#define QEOV2_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_WAVE_RESOLUTION_LINES_MASK) >> QEOV2_WAVE_RESOLUTION_LINES_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VAL (RW) - * - * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period - */ -#define QEOV2_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT (0U) -#define QEOV2_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK) -#define QEOV2_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK) >> QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: VD_INJECT */ -/* - * VD_VAL (RW) - * - * Vd inject value - */ -#define QEOV2_WAVE_VD_INJECT_VD_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT (0U) -#define QEOV2_WAVE_VD_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK) -#define QEOV2_WAVE_VD_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK) >> QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: VQ_INJECT */ -/* - * VQ_VAL (RW) - * - * Vq inject value - */ -#define QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT (0U) -#define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK) -#define QEOV2_WAVE_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK) >> QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */ -/* - * LOAD (WO) - * - * load wave0/1/2 vd vq value. always read 0 - * 0: vd vq keep previous value. - * 1: load wave0/1/2 vd vq value at sametime. - */ -#define QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U) -#define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U) -#define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK) -#define QEOV2_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * EN_SCAL (RW) - * - * enable wave amplitude scaling. 0: disable; 1: enable - */ -#define QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL) -#define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U) -#define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK) -#define QEOV2_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT) - -/* - * AMP_VAL (RW) - * - * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value. - */ -#define QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU) -#define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U) -#define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK) -#define QEOV2_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VAL (RW) - * - * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value. - */ -#define QEOV2_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_MID_POINT_VAL_SHIFT (0U) -#define QEOV2_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MID_POINT_VAL_SHIFT) & QEOV2_WAVE_MID_POINT_VAL_MASK) -#define QEOV2_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MID_POINT_VAL_MASK) >> QEOV2_WAVE_MID_POINT_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: MIN_LEVEL0 */ -/* - * LIMIT_LEVEL0 (RW) - * - * low area limit level0 - */ -#define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT (0U) -#define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK) -#define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT) - -/* Bitfield definition for register of struct WAVE: MAX_LEVEL0 */ -/* - * LIMIT_LEVEL0 (RW) - * - * high area limit level0 - */ -#define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT (0U) -#define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK) -#define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT) - -/* Bitfield definition for register of struct WAVE: MIN_LEVEL1 */ -/* - * LIMIT_LEVEL1 (RW) - * - * low area limit level1 - */ -#define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT (0U) -#define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK) -#define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT) - -/* Bitfield definition for register of struct WAVE: MAX_LEVEL1 */ -/* - * LIMIT_LEVEL1 (RW) - * - * high area limit level1 - */ -#define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT (0U) -#define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK) -#define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT) - -/* Bitfield definition for register of struct WAVE: WAVE0 */ -/* - * VAL (RW) - * - * wave0 deadzone shifter value - */ -#define QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U) -#define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK) -#define QEOV2_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct WAVE: PWM_CYCLE */ -/* - * VAL (RW) - * - * pwm_cycle - */ -#define QEOV2_WAVE_PWM_CYCLE_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT (0U) -#define QEOV2_WAVE_PWM_CYCLE_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK) -#define QEOV2_WAVE_PWM_CYCLE_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK) >> QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT) - -/* Bitfield definition for register of struct ABZ: MODE */ -/* - * ABZ_OUTPUT_ENABLE (RW) - * - * abz output enable： - * 0：abz output disable, all keep 0 - * 1：abz output enable. - */ -#define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK (0x80000000UL) -#define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT (31U) -#define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK) -#define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK) >> QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT) - -/* - * REVERSE_EDGE_TYPE (RW) - * - * pulse reverse wave，reverse edge point: - * 0: between pulse's posedge and negedge, min period dedicated by the num line_width - * 1: edge change point flow pulse's negedge. - */ -#define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL) -#define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U) -#define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) -#define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) - -/* - * POSITION_SYNC_MODE (RW) - * - * position sync mode: - * 0: only sync integer line part into qeo own position. - * 1: sync integer and fraction part into qeo own position. - */ -#define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK (0x8000000UL) -#define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT (27U) -#define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK) -#define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK) >> QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT) - -/* - * EN_WDOG (RW) - * - * enable abz wdog: - * 0: disable abz wdog. - * 1: enable abz wdog. - */ -#define QEOV2_ABZ_MODE_EN_WDOG_MASK (0x1000000UL) -#define QEOV2_ABZ_MODE_EN_WDOG_SHIFT (24U) -#define QEOV2_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_EN_WDOG_SHIFT) & QEOV2_ABZ_MODE_EN_WDOG_MASK) -#define QEOV2_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_EN_WDOG_MASK) >> QEOV2_ABZ_MODE_EN_WDOG_SHIFT) - -/* - * Z_POLARITY (RW) - * - * wave_z polarity. - * 0: normal output. - * 1: invert normal output - */ -#define QEOV2_ABZ_MODE_Z_POLARITY_MASK (0x100000UL) -#define QEOV2_ABZ_MODE_Z_POLARITY_SHIFT (20U) -#define QEOV2_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_POLARITY_SHIFT) & QEOV2_ABZ_MODE_Z_POLARITY_MASK) -#define QEOV2_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_POLARITY_MASK) >> QEOV2_ABZ_MODE_Z_POLARITY_SHIFT) - -/* - * B_POLARITY (RW) - * - * wave_b polarity. - * 0: normal output. - * 1: invert normal output - */ -#define QEOV2_ABZ_MODE_B_POLARITY_MASK (0x10000UL) -#define QEOV2_ABZ_MODE_B_POLARITY_SHIFT (16U) -#define QEOV2_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_B_POLARITY_SHIFT) & QEOV2_ABZ_MODE_B_POLARITY_MASK) -#define QEOV2_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_B_POLARITY_MASK) >> QEOV2_ABZ_MODE_B_POLARITY_SHIFT) - -/* - * A_POLARITY (RW) - * - * wave_a polarity. - * 0: normal output. - * 1: invert normal output - */ -#define QEOV2_ABZ_MODE_A_POLARITY_MASK (0x1000U) -#define QEOV2_ABZ_MODE_A_POLARITY_SHIFT (12U) -#define QEOV2_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_A_POLARITY_SHIFT) & QEOV2_ABZ_MODE_A_POLARITY_MASK) -#define QEOV2_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_A_POLARITY_MASK) >> QEOV2_ABZ_MODE_A_POLARITY_SHIFT) - -/* - * Z_TYPE (RW) - * - * wave_z type: - * 0: zero pulse type, start and end line number decided by z_start、z_end and z_offset. - * 1: zero pulse type, z output start to high when position= z_start, and mantain numbers of 1/4 line cfg in z_pulse_width register - * 2: reserved - * 3: wave_z output as tree-phase wave same as wave_a/wave_b - */ -#define QEOV2_ABZ_MODE_Z_TYPE_MASK (0x300U) -#define QEOV2_ABZ_MODE_Z_TYPE_SHIFT (8U) -#define QEOV2_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_TYPE_SHIFT) & QEOV2_ABZ_MODE_Z_TYPE_MASK) -#define QEOV2_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_TYPE_MASK) >> QEOV2_ABZ_MODE_Z_TYPE_SHIFT) - -/* - * B_TYPE (RW) - * - * wave_b type: - * 0: Two-phase orthogonality wave_b. - * 1: reverse wave of pulse/reverse type. - * 2: down wave of up/down type. - * 3: Three-phase orthogonality wave_b. - */ -#define QEOV2_ABZ_MODE_B_TYPE_MASK (0x30U) -#define QEOV2_ABZ_MODE_B_TYPE_SHIFT (4U) -#define QEOV2_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_B_TYPE_SHIFT) & QEOV2_ABZ_MODE_B_TYPE_MASK) -#define QEOV2_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_B_TYPE_MASK) >> QEOV2_ABZ_MODE_B_TYPE_SHIFT) - -/* - * A_TYPE (RW) - * - * wave_a type: - * 0: Two-phase orthogonality wave_a. - * 1: pulse wave of pulse/reverse type. - * 2: up wave of up/down type. - * 3: Three-phase orthogonality wave_a. - */ -#define QEOV2_ABZ_MODE_A_TYPE_MASK (0x3U) -#define QEOV2_ABZ_MODE_A_TYPE_SHIFT (0U) -#define QEOV2_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_A_TYPE_SHIFT) & QEOV2_ABZ_MODE_A_TYPE_MASK) -#define QEOV2_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_A_TYPE_MASK) >> QEOV2_ABZ_MODE_A_TYPE_SHIFT) - -/* Bitfield definition for register of struct ABZ: RESOLUTION */ -/* - * LINES (RW) - * - * wave_a/b/z resolution - */ -#define QEOV2_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_RESOLUTION_LINES_SHIFT (0U) -#define QEOV2_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_ABZ_RESOLUTION_LINES_SHIFT) & QEOV2_ABZ_RESOLUTION_LINES_MASK) -#define QEOV2_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_ABZ_RESOLUTION_LINES_MASK) >> QEOV2_ABZ_RESOLUTION_LINES_SHIFT) - -/* Bitfield definition for register of struct ABZ: A */ -/* - * VAL (RW) - * - * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period. - */ -#define QEOV2_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT (0U) -#define QEOV2_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK) -#define QEOV2_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK) >> QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct ABZ: LINE_WIDTH */ -/* - * LINE (RW) - * - * the num of system clk by 1/4 period when using as Two-phase orthogonality. - */ -#define QEOV2_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT (0U) -#define QEOV2_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK) -#define QEOV2_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK) >> QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT) - -/* Bitfield definition for register of struct ABZ: WDOG_WIDTH */ -/* - * WIDTH (RW) - * - * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk. - */ -#define QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U) -#define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK) -#define QEOV2_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT) - -/* Bitfield definition for register of struct ABZ: POSTION_SYNC */ -/* - * POSTION (WO) - * - * load next valid postion into abz owned postion. always read 0 - * 0: sync abz owned postion with next valid postion. - * 1: not sync. - */ -#define QEOV2_ABZ_POSTION_SYNC_POSTION_MASK (0x1U) -#define QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT (0U) -#define QEOV2_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK) -#define QEOV2_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK) >> QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT) - -/* Bitfield definition for register of struct ABZ: OVERALL_OFFSET */ -/* - * VAL (RW) - * - * abz position overall offset, it affects abz position before resolution convert - */ -#define QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT (0U) -#define QEOV2_ABZ_OVERALL_OFFSET_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK) -#define QEOV2_ABZ_OVERALL_OFFSET_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK) >> QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT) - -/* Bitfield definition for register of struct ABZ: Z_START */ -/* - * Z_START (RW) - * - * number of Z start line - */ -#define QEOV2_ABZ_Z_START_Z_START_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_Z_START_Z_START_SHIFT (0U) -#define QEOV2_ABZ_Z_START_Z_START_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_START_Z_START_SHIFT) & QEOV2_ABZ_Z_START_Z_START_MASK) -#define QEOV2_ABZ_Z_START_Z_START_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_START_Z_START_MASK) >> QEOV2_ABZ_Z_START_Z_START_SHIFT) - -/* Bitfield definition for register of struct ABZ: Z_END */ -/* - * Z_END (RW) - * - * number of Z end line - */ -#define QEOV2_ABZ_Z_END_Z_END_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_Z_END_Z_END_SHIFT (0U) -#define QEOV2_ABZ_Z_END_Z_END_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_END_Z_END_SHIFT) & QEOV2_ABZ_Z_END_Z_END_MASK) -#define QEOV2_ABZ_Z_END_Z_END_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_END_Z_END_MASK) >> QEOV2_ABZ_Z_END_Z_END_SHIFT) - -/* Bitfield definition for register of struct ABZ: Z_OFFSET */ -/* - * Z_END_OFFSET (RW) - * - * number of Z end 1/4 line - */ -#define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK (0x300U) -#define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT (8U) -#define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK) -#define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT) - -/* - * Z_START_OFFSET (RW) - * - * number of Z start 1/4 line - */ -#define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK (0x30U) -#define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT (4U) -#define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK) -#define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT) - -/* Bitfield definition for register of struct ABZ: Z_PULSE_WIDTH */ -/* - * VAL (RW) - * - * number of z_pulse_width - */ -#define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT (0U) -#define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK) -#define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK) >> QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT) - -/* Bitfield definition for register of struct PWM: MODE */ -/* - * PWM7_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL) -#define QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT (30U) -#define QEOV2_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT) - -/* - * PWM6_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL) -#define QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT (28U) -#define QEOV2_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT) - -/* - * PWM5_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL) -#define QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT (26U) -#define QEOV2_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT) - -/* - * PWM4_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL) -#define QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT (24U) -#define QEOV2_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT) - -/* - * PWM3_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL) -#define QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT (22U) -#define QEOV2_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT) - -/* - * PWM2_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL) -#define QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT (20U) -#define QEOV2_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT) - -/* - * PWM1_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL) -#define QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT (18U) -#define QEOV2_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT) - -/* - * PWM0_SAFETY (RW) - * - * PWM safety mode phase table - */ -#define QEOV2_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL) -#define QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT (16U) -#define QEOV2_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK) -#define QEOV2_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT) - -/* - * ENABLE_PWM (RW) - * - * enable PWM force output - * 0: disable - * 1: enable - */ -#define QEOV2_PWM_MODE_ENABLE_PWM_MASK (0x8000U) -#define QEOV2_PWM_MODE_ENABLE_PWM_SHIFT (15U) -#define QEOV2_PWM_MODE_ENABLE_PWM_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_ENABLE_PWM_SHIFT) & QEOV2_PWM_MODE_ENABLE_PWM_MASK) -#define QEOV2_PWM_MODE_ENABLE_PWM_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_ENABLE_PWM_MASK) >> QEOV2_PWM_MODE_ENABLE_PWM_SHIFT) - -/* - * PWM_ENTER_SAFETY_MODE (RW) - * - * PWM enter safety mode - * 0: not enter - * 1: enter - */ -#define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U) -#define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U) -#define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) -#define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) - -/* - * PWM_SAFETY_BYPASS (RW) - * - * PWM safety mode bypass - * 0: not bypass - * 1: bypass - */ -#define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U) -#define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U) -#define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK) -#define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) - -/* - * REVISE_UP_DN (RW) - * - * exchange PWM pairs’ output - * 0: not exchange. - * 1: exchange. - */ -#define QEOV2_PWM_MODE_REVISE_UP_DN_MASK (0x10U) -#define QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT (4U) -#define QEOV2_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK) -#define QEOV2_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK) >> QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT) - -/* - * PHASE_NUM (RW) - * - * pwm force phase number. - */ -#define QEOV2_PWM_MODE_PHASE_NUM_MASK (0xFU) -#define QEOV2_PWM_MODE_PHASE_NUM_SHIFT (0U) -#define QEOV2_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PHASE_NUM_SHIFT) & QEOV2_PWM_MODE_PHASE_NUM_MASK) -#define QEOV2_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PHASE_NUM_MASK) >> QEOV2_PWM_MODE_PHASE_NUM_SHIFT) - -/* Bitfield definition for register of struct PWM: RESOLUTION */ -/* - * LINES (RW) - * - * pwm resolution - */ -#define QEOV2_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL) -#define QEOV2_PWM_RESOLUTION_LINES_SHIFT (0U) -#define QEOV2_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_PWM_RESOLUTION_LINES_SHIFT) & QEOV2_PWM_RESOLUTION_LINES_MASK) -#define QEOV2_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_PWM_RESOLUTION_LINES_MASK) >> QEOV2_PWM_RESOLUTION_LINES_SHIFT) - -/* Bitfield definition for register of struct PWM: A */ -/* - * VAL (RW) - * - * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period - */ -#define QEOV2_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL) -#define QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT (0U) -#define QEOV2_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK) -#define QEOV2_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK) >> QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT) - -/* Bitfield definition for register of struct PWM: POSEDGE0 */ -/* - * PWM7 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM7_MASK (0xC000U) -#define QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT (14U) -#define QEOV2_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT) - -/* - * PWM6 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM6_MASK (0x3000U) -#define QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT (12U) -#define QEOV2_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT) - -/* - * PWM5 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM5_MASK (0xC00U) -#define QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT (10U) -#define QEOV2_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT) - -/* - * PWM4 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM4_MASK (0x300U) -#define QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT (8U) -#define QEOV2_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT) - -/* - * PWM3 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM3_MASK (0xC0U) -#define QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT (6U) -#define QEOV2_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT) - -/* - * PWM2 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM2_MASK (0x30U) -#define QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT (4U) -#define QEOV2_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT) - -/* - * PWM1 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM1_MASK (0xCU) -#define QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT (2U) -#define QEOV2_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT) - -/* - * PWM0 (RW) - * - * pwm phase table value - */ -#define QEOV2_PWM_PHASE_TABLE_PWM0_MASK (0x3U) -#define QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT (0U) -#define QEOV2_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK) -#define QEOV2_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT) - -/* Bitfield definition for register: POSTION_SOFTWARE */ -/* - * POSTION_SOFTWAVE (RW) - * - * softwave inject postion - */ -#define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL) -#define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U) -#define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) -#define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) - -/* Bitfield definition for register: POSTION_SEL */ -/* - * POSTION_SEL (RW) - * - * enable softwave inject postion. - * 0: disable. - * 1: enable. - */ -#define QEOV2_POSTION_SEL_POSTION_SEL_MASK (0x1U) -#define QEOV2_POSTION_SEL_POSTION_SEL_SHIFT (0U) -#define QEOV2_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEOV2_POSTION_SEL_POSTION_SEL_SHIFT) & QEOV2_POSTION_SEL_POSTION_SEL_MASK) -#define QEOV2_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEOV2_POSTION_SEL_POSTION_SEL_MASK) >> QEOV2_POSTION_SEL_POSTION_SEL_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * PWM_FOURCE (RO) - * - * qeo_pwm_force observe - */ -#define QEOV2_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL) -#define QEOV2_STATUS_PWM_FOURCE_SHIFT (16U) -#define QEOV2_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEOV2_STATUS_PWM_FOURCE_MASK) >> QEOV2_STATUS_PWM_FOURCE_SHIFT) - -/* - * PWM_SAFETY (RO) - * - * pwm_fault status - */ -#define QEOV2_STATUS_PWM_SAFETY_MASK (0x1U) -#define QEOV2_STATUS_PWM_SAFETY_SHIFT (0U) -#define QEOV2_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_STATUS_PWM_SAFETY_MASK) >> QEOV2_STATUS_PWM_SAFETY_SHIFT) - -/* Bitfield definition for register: DEBUG0 */ -/* - * VALUE_DAC0 (RO) - * - * wave0 - */ -#define QEOV2_DEBUG0_VALUE_DAC0_MASK (0xFFFFFFFFUL) -#define QEOV2_DEBUG0_VALUE_DAC0_SHIFT (0U) -#define QEOV2_DEBUG0_VALUE_DAC0_GET(x) (((uint32_t)(x) & QEOV2_DEBUG0_VALUE_DAC0_MASK) >> QEOV2_DEBUG0_VALUE_DAC0_SHIFT) - -/* Bitfield definition for register: DEBUG1 */ -/* - * QEO_FINISH (RO) - * - * qeo finish observe - */ -#define QEOV2_DEBUG1_QEO_FINISH_MASK (0x10000000UL) -#define QEOV2_DEBUG1_QEO_FINISH_SHIFT (28U) -#define QEOV2_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_QEO_FINISH_MASK) >> QEOV2_DEBUG1_QEO_FINISH_SHIFT) - -/* - * PAD_Z (RO) - * - * pad_z observe - */ -#define QEOV2_DEBUG1_PAD_Z_MASK (0x1000000UL) -#define QEOV2_DEBUG1_PAD_Z_SHIFT (24U) -#define QEOV2_DEBUG1_PAD_Z_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_Z_MASK) >> QEOV2_DEBUG1_PAD_Z_SHIFT) - -/* - * PAD_B (RO) - * - * pad_b observe - */ -#define QEOV2_DEBUG1_PAD_B_MASK (0x100000UL) -#define QEOV2_DEBUG1_PAD_B_SHIFT (20U) -#define QEOV2_DEBUG1_PAD_B_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_B_MASK) >> QEOV2_DEBUG1_PAD_B_SHIFT) - -/* - * PAD_A (RO) - * - * pad_a observe - */ -#define QEOV2_DEBUG1_PAD_A_MASK (0x10000UL) -#define QEOV2_DEBUG1_PAD_A_SHIFT (16U) -#define QEOV2_DEBUG1_PAD_A_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_A_MASK) >> QEOV2_DEBUG1_PAD_A_SHIFT) - -/* Bitfield definition for register: DEBUG2 */ -/* - * ABZ_OWN_POSTION (RO) - * - * abz_own_postion observe - */ -#define QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) -#define QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U) -#define QEOV2_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT) - -/* Bitfield definition for register: DEBUG3 */ -/* - * ABZ_OWN_POSTION (RO) - * - * abz_own_postion observe - */ -#define QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL) -#define QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U) -#define QEOV2_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT) - -/* Bitfield definition for register: DEBUG4 */ -/* - * VALUE_DAC1 (RO) - * - * wave1 - */ -#define QEOV2_DEBUG4_VALUE_DAC1_MASK (0xFFFFFFFFUL) -#define QEOV2_DEBUG4_VALUE_DAC1_SHIFT (0U) -#define QEOV2_DEBUG4_VALUE_DAC1_GET(x) (((uint32_t)(x) & QEOV2_DEBUG4_VALUE_DAC1_MASK) >> QEOV2_DEBUG4_VALUE_DAC1_SHIFT) - -/* Bitfield definition for register: DEBUG5 */ -/* - * VALUE_DAC2 (RO) - * - * wave2 - */ -#define QEOV2_DEBUG5_VALUE_DAC2_MASK (0xFFFFFFFFUL) -#define QEOV2_DEBUG5_VALUE_DAC2_SHIFT (0U) -#define QEOV2_DEBUG5_VALUE_DAC2_GET(x) (((uint32_t)(x) & QEOV2_DEBUG5_VALUE_DAC2_MASK) >> QEOV2_DEBUG5_VALUE_DAC2_SHIFT) - - - -/* PHASE_SHIFT register group index macro definition */ -#define QEOV2_WAVE_PHASE_SHIFT_WAVE0 (0UL) -#define QEOV2_WAVE_PHASE_SHIFT_WAVE1 (1UL) -#define QEOV2_WAVE_PHASE_SHIFT_WAVE2 (2UL) - -/* AMPLITUDE register group index macro definition */ -#define QEOV2_WAVE_AMPLITUDE_WAVE0 (0UL) -#define QEOV2_WAVE_AMPLITUDE_WAVE1 (1UL) -#define QEOV2_WAVE_AMPLITUDE_WAVE2 (2UL) - -/* MID_POINT register group index macro definition */ -#define QEOV2_WAVE_MID_POINT_WAVE0 (0UL) -#define QEOV2_WAVE_MID_POINT_WAVE1 (1UL) -#define QEOV2_WAVE_MID_POINT_WAVE2 (2UL) - -/* LIMIT0 register group index macro definition */ -#define QEOV2_LIMIT0_WAVE0 (0UL) -#define QEOV2_LIMIT0_WAVE1 (1UL) -#define QEOV2_LIMIT0_WAVE2 (2UL) - -/* LIMIT1 register group index macro definition */ -#define QEOV2_LIMIT1_WAVE0 (0UL) -#define QEOV2_LIMIT1_WAVE1 (1UL) -#define QEOV2_LIMIT1_WAVE2 (2UL) - -/* DEADZONE_SHIFT register group index macro definition */ -#define QEOV2_WAVE_DEADZONE_SHIFT_WAVE0 (0UL) -#define QEOV2_WAVE_DEADZONE_SHIFT_WAVE1 (1UL) -#define QEOV2_WAVE_DEADZONE_SHIFT_WAVE2 (2UL) - -/* PHASE_SHIFT register group index macro definition */ -#define QEOV2_ABZ_PHASE_SHIFT_A (0UL) -#define QEOV2_ABZ_PHASE_SHIFT_B (1UL) -#define QEOV2_ABZ_PHASE_SHIFT_Z (2UL) - -/* PHASE_SHIFT register group index macro definition */ -#define QEOV2_PWM_PHASE_SHIFT_A (0UL) -#define QEOV2_PWM_PHASE_SHIFT_B (1UL) -#define QEOV2_PWM_PHASE_SHIFT_C (2UL) -#define QEOV2_PWM_PHASE_SHIFT_D (3UL) - -/* PHASE_TABLE register group index macro definition */ -#define QEOV2_PWM_PHASE_TABLE_POSEDGE0 (0UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE1 (1UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE2 (2UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE3 (3UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE4 (4UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE5 (5UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE6 (6UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE7 (7UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE8 (8UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE9 (9UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE10 (10UL) -#define QEOV2_PWM_PHASE_TABLE_POSEDGE11 (11UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE0 (12UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE1 (13UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE2 (14UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE3 (15UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE4 (16UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE5 (17UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE6 (18UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE7 (19UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE8 (20UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE9 (21UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE10 (22UL) -#define QEOV2_PWM_PHASE_TABLE_NEGEDGE11 (23UL) - - -#endif /* HPM_QEOV2_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rdc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rdc_regs.h deleted file mode 100644 index 30d28023a2f..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rdc_regs.h +++ /dev/null @@ -1,1439 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RDC_H -#define HPM_RDC_H - -typedef struct { - __RW uint32_t RDC_CTL; /* 0x0: rdc control */ - __R uint32_t ACC_I; /* 0x4: accumulate result of i_channel */ - __R uint32_t ACC_Q; /* 0x8: accumulate result of q_channel */ - __RW uint32_t IN_CTL; /* 0xC: input channel selection */ - __RW uint32_t OUT_CTL; /* 0x10: output channel selection */ - __RW uint32_t IIR_B; /* 0x14: IIR parameter for b branch */ - __RW uint32_t IIR_A; /* 0x18: IIR parameter for a branch */ - __R uint8_t RESERVED0[24]; /* 0x1C - 0x33: Reserved */ - __RW uint32_t EXC_TIMMING; /* 0x34: excitation signal timming setting */ - __RW uint32_t EXC_SCALING; /* 0x38: amplitude scaling for excitation */ - __RW uint32_t EXC_OFFSET; /* 0x3C: amplitude offset setting */ - __RW uint32_t PWM_SCALING; /* 0x40: amplitude scaling for excitation */ - __RW uint32_t PWM_OFFSET; /* 0x44: amplitude offset setting */ - __RW uint32_t TRIG_OUT0_CFG; /* 0x48: Configuration for trigger out 0 in clock cycle */ - __RW uint32_t TRIG_OUT1_CFG; /* 0x4C: Configuration for trigger out 1 in clock cycle */ - __RW uint32_t PWM_DZ; /* 0x50: pwm dead zone control in clock cycle */ - __RW uint32_t SYNC_OUT_CTRL; /* 0x54: synchronize output signal control */ - __RW uint32_t EXC_SYNC_DLY; /* 0x58: trigger in delay timming in soc bus cycle */ - __R uint8_t RESERVED1[16]; /* 0x5C - 0x6B: Reserved */ - __RW uint32_t MAX_MIN_POS; /* 0x6C: max min data position of channel */ - __RW uint32_t MAX_I; /* 0x70: max value of i_channel */ - __RW uint32_t MIN_I; /* 0x74: min value of i_channel */ - __RW uint32_t MAX_Q; /* 0x78: max value of q_channel */ - __RW uint32_t MIN_Q; /* 0x7C: min value of q_channel */ - __RW uint32_t THRS_I; /* 0x80: the offset setting for edge detection of the i_channel */ - __RW uint32_t THRS_Q; /* 0x84: the offset setting for edge detection of the q_channel */ - __RW uint32_t EDG_DET_CTL; /* 0x88: the control for edge detection */ - __RW uint32_t ACC_SCALING; /* 0x8C: scaling for accumulation result */ - __RW uint32_t EXC_PERIOD; /* 0x90: period of excitation */ - __R uint8_t RESERVED2[12]; /* 0x94 - 0x9F: Reserved */ - __RW uint32_t SYNC_DELAY_I; /* 0xA0: delay setting in clock cycle for synchronous signal */ - __R uint8_t RESERVED3[4]; /* 0xA4 - 0xA7: Reserved */ - __R uint32_t RISE_DELAY_I; /* 0xA8: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data */ - __R uint32_t FALL_DELAY_I; /* 0xAC: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data */ - __R uint32_t SAMPLE_RISE_I; /* 0xB0: sample value on rising edge of rectify signal */ - __R uint32_t SAMPLE_FALL_I; /* 0xB4: sample value on falling edge of rectify signal */ - __R uint32_t ACC_CNT_I; /* 0xB8: number of accumulation */ - __R uint32_t SIGN_CNT_I; /* 0xBC: sample counter of opposite sign with rectify signal */ - __RW uint32_t SYNC_DELAY_Q; /* 0xC0: delay setting in clock cycle for synchronous signal */ - __R uint8_t RESERVED4[4]; /* 0xC4 - 0xC7: Reserved */ - __R uint32_t RISE_DELAY_Q; /* 0xC8: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data */ - __R uint32_t FALL_DELAY_Q; /* 0xCC: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data */ - __R uint32_t SAMPLE_RISE_Q; /* 0xD0: sample value on rising edge of rectify signal */ - __R uint32_t SAMPLE_FALL_Q; /* 0xD4: sample value on falling edge of rectify signal */ - __R uint32_t ACC_CNT_Q; /* 0xD8: number of accumulation */ - __R uint32_t SIGN_CNT_Q; /* 0xDC: sample counter of opposite sign with rectify signal */ - __RW uint32_t AMP_MAX; /* 0xE0: the maximum of acc amplitude */ - __RW uint32_t AMP_MIN; /* 0xE4: the minimum of acc amplitude */ - __RW uint32_t INT_EN; /* 0xE8: the interrupt mask control */ - __W uint32_t ADC_INT_STATE; /* 0xEC: the interrupt state */ -} RDC_Type; - - -/* Bitfield definition for register: RDC_CTL */ -/* - * TS_SEL (RW) - * - * Time stamp selection for accumulation - * 0: end of accumulation - * 1: start of accumulation - * 2: center of accumulation - */ -#define RDC_RDC_CTL_TS_SEL_MASK (0x300000UL) -#define RDC_RDC_CTL_TS_SEL_SHIFT (20U) -#define RDC_RDC_CTL_TS_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_TS_SEL_SHIFT) & RDC_RDC_CTL_TS_SEL_MASK) -#define RDC_RDC_CTL_TS_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_TS_SEL_MASK) >> RDC_RDC_CTL_TS_SEL_SHIFT) - -/* - * ACC_LEN (RW) - * - * Accumulate time, support on the fly change - * 0：1 cycle - * 1：2 cycles - * … - * 255: 256 cycles - */ -#define RDC_RDC_CTL_ACC_LEN_MASK (0xFF000UL) -#define RDC_RDC_CTL_ACC_LEN_SHIFT (12U) -#define RDC_RDC_CTL_ACC_LEN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_LEN_SHIFT) & RDC_RDC_CTL_ACC_LEN_MASK) -#define RDC_RDC_CTL_ACC_LEN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_LEN_MASK) >> RDC_RDC_CTL_ACC_LEN_SHIFT) - -/* - * ACC_OUT_MASK (RW) - * - * rdc output mask - */ -#define RDC_RDC_CTL_ACC_OUT_MASK_MASK (0x200U) -#define RDC_RDC_CTL_ACC_OUT_MASK_SHIFT (9U) -#define RDC_RDC_CTL_ACC_OUT_MASK_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_OUT_MASK_SHIFT) & RDC_RDC_CTL_ACC_OUT_MASK_MASK) -#define RDC_RDC_CTL_ACC_OUT_MASK_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_OUT_MASK_MASK) >> RDC_RDC_CTL_ACC_OUT_MASK_SHIFT) - -/* - * IIR_EN (RW) - * - * IIR enable for adc input - */ -#define RDC_RDC_CTL_IIR_EN_MASK (0x100U) -#define RDC_RDC_CTL_IIR_EN_SHIFT (8U) -#define RDC_RDC_CTL_IIR_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_IIR_EN_SHIFT) & RDC_RDC_CTL_IIR_EN_MASK) -#define RDC_RDC_CTL_IIR_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_IIR_EN_MASK) >> RDC_RDC_CTL_IIR_EN_SHIFT) - -/* - * RECTIFY_SEL (RW) - * - * Select reference point of rectify signal - * 0: 0 phase of internal exciting signal - * 1: 90 phase of internal exciting signal - * 2: 180 phase of internal exciting signal - * 3: 270 phase of internal exciting signal - * 4: use value on external pin - * 5: use invert value on external pin - */ -#define RDC_RDC_CTL_RECTIFY_SEL_MASK (0x70U) -#define RDC_RDC_CTL_RECTIFY_SEL_SHIFT (4U) -#define RDC_RDC_CTL_RECTIFY_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_RECTIFY_SEL_SHIFT) & RDC_RDC_CTL_RECTIFY_SEL_MASK) -#define RDC_RDC_CTL_RECTIFY_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_RECTIFY_SEL_MASK) >> RDC_RDC_CTL_RECTIFY_SEL_SHIFT) - -/* - * ACC_FAST (RW) - * - * every adc value can be as one accumulate value - */ -#define RDC_RDC_CTL_ACC_FAST_MASK (0x8U) -#define RDC_RDC_CTL_ACC_FAST_SHIFT (3U) -#define RDC_RDC_CTL_ACC_FAST_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_FAST_SHIFT) & RDC_RDC_CTL_ACC_FAST_MASK) -#define RDC_RDC_CTL_ACC_FAST_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_FAST_MASK) >> RDC_RDC_CTL_ACC_FAST_SHIFT) - -/* - * ACC_EN (RW) - * - * Enable rdc accumulate - * 0: rdc disable - * 1: rdc enable - */ -#define RDC_RDC_CTL_ACC_EN_MASK (0x4U) -#define RDC_RDC_CTL_ACC_EN_SHIFT (2U) -#define RDC_RDC_CTL_ACC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_EN_SHIFT) & RDC_RDC_CTL_ACC_EN_MASK) -#define RDC_RDC_CTL_ACC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_EN_MASK) >> RDC_RDC_CTL_ACC_EN_SHIFT) - -/* - * EXC_START (RW1C) - * - * Write 1 start excite signal, always read 0 - * 0: no effect - * 1: start excite signal - */ -#define RDC_RDC_CTL_EXC_START_MASK (0x2U) -#define RDC_RDC_CTL_EXC_START_SHIFT (1U) -#define RDC_RDC_CTL_EXC_START_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_START_SHIFT) & RDC_RDC_CTL_EXC_START_MASK) -#define RDC_RDC_CTL_EXC_START_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_START_MASK) >> RDC_RDC_CTL_EXC_START_SHIFT) - -/* - * EXC_EN (RW) - * - * Enable rdc excite signal - * 0: rdc disable - * 1: rdc enable - */ -#define RDC_RDC_CTL_EXC_EN_MASK (0x1U) -#define RDC_RDC_CTL_EXC_EN_SHIFT (0U) -#define RDC_RDC_CTL_EXC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_EN_SHIFT) & RDC_RDC_CTL_EXC_EN_MASK) -#define RDC_RDC_CTL_EXC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_EN_MASK) >> RDC_RDC_CTL_EXC_EN_SHIFT) - -/* Bitfield definition for register: ACC_I */ -/* - * ACC (RO) - * - * accumulate result of i_channel, this is a signed number - */ -#define RDC_ACC_I_ACC_MASK (0xFFFFFFFFUL) -#define RDC_ACC_I_ACC_SHIFT (0U) -#define RDC_ACC_I_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_I_ACC_MASK) >> RDC_ACC_I_ACC_SHIFT) - -/* Bitfield definition for register: ACC_Q */ -/* - * ACC (RO) - * - * accumulate result of q_channel, this is a signed number - */ -#define RDC_ACC_Q_ACC_MASK (0xFFFFFFFFUL) -#define RDC_ACC_Q_ACC_SHIFT (0U) -#define RDC_ACC_Q_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_Q_ACC_MASK) >> RDC_ACC_Q_ACC_SHIFT) - -/* Bitfield definition for register: IN_CTL */ -/* - * PORT_Q_SEL (RW) - * - * Input port selection for q_channel, - * 0:sel port0 - * 1:sel port1 - */ -#define RDC_IN_CTL_PORT_Q_SEL_MASK (0x100000UL) -#define RDC_IN_CTL_PORT_Q_SEL_SHIFT (20U) -#define RDC_IN_CTL_PORT_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_Q_SEL_SHIFT) & RDC_IN_CTL_PORT_Q_SEL_MASK) -#define RDC_IN_CTL_PORT_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_Q_SEL_MASK) >> RDC_IN_CTL_PORT_Q_SEL_SHIFT) - -/* - * CH_Q_SEL (RW) - * - * Input channel selection for q_channel - * 0: channel 0 selected - * 1: channel 1 selected - * … - * 31: channel 31 selected - */ -#define RDC_IN_CTL_CH_Q_SEL_MASK (0x1F000UL) -#define RDC_IN_CTL_CH_Q_SEL_SHIFT (12U) -#define RDC_IN_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_Q_SEL_SHIFT) & RDC_IN_CTL_CH_Q_SEL_MASK) -#define RDC_IN_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_Q_SEL_MASK) >> RDC_IN_CTL_CH_Q_SEL_SHIFT) - -/* - * PORT_I_SEL (RW) - * - * Input port selection for i_channel, - * 0:sel port0 - * 1:sel port1 - */ -#define RDC_IN_CTL_PORT_I_SEL_MASK (0x100U) -#define RDC_IN_CTL_PORT_I_SEL_SHIFT (8U) -#define RDC_IN_CTL_PORT_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_I_SEL_SHIFT) & RDC_IN_CTL_PORT_I_SEL_MASK) -#define RDC_IN_CTL_PORT_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_I_SEL_MASK) >> RDC_IN_CTL_PORT_I_SEL_SHIFT) - -/* - * CH_I_SEL (RW) - * - * Input channel selection for i_channel - * 0: channel 0 selected - * 1: channel 1 selected - * … - * 31: channel 31 selected - */ -#define RDC_IN_CTL_CH_I_SEL_MASK (0x1FU) -#define RDC_IN_CTL_CH_I_SEL_SHIFT (0U) -#define RDC_IN_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_I_SEL_SHIFT) & RDC_IN_CTL_CH_I_SEL_MASK) -#define RDC_IN_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_I_SEL_MASK) >> RDC_IN_CTL_CH_I_SEL_SHIFT) - -/* Bitfield definition for register: OUT_CTL */ -/* - * CH_Q_SEL (RW) - * - * Output channel selection for q_channel - */ -#define RDC_OUT_CTL_CH_Q_SEL_MASK (0x1F00U) -#define RDC_OUT_CTL_CH_Q_SEL_SHIFT (8U) -#define RDC_OUT_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_Q_SEL_SHIFT) & RDC_OUT_CTL_CH_Q_SEL_MASK) -#define RDC_OUT_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_Q_SEL_MASK) >> RDC_OUT_CTL_CH_Q_SEL_SHIFT) - -/* - * CH_I_SEL (RW) - * - * Output channel selection for i_channel - */ -#define RDC_OUT_CTL_CH_I_SEL_MASK (0x1FU) -#define RDC_OUT_CTL_CH_I_SEL_SHIFT (0U) -#define RDC_OUT_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_I_SEL_SHIFT) & RDC_OUT_CTL_CH_I_SEL_MASK) -#define RDC_OUT_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_I_SEL_MASK) >> RDC_OUT_CTL_CH_I_SEL_SHIFT) - -/* Bitfield definition for register: IIR_B */ -/* - * LOWPASS (RW) - * - * IIR in lowpass mode - */ -#define RDC_IIR_B_LOWPASS_MASK (0x1000000UL) -#define RDC_IIR_B_LOWPASS_SHIFT (24U) -#define RDC_IIR_B_LOWPASS_SET(x) (((uint32_t)(x) << RDC_IIR_B_LOWPASS_SHIFT) & RDC_IIR_B_LOWPASS_MASK) -#define RDC_IIR_B_LOWPASS_GET(x) (((uint32_t)(x) & RDC_IIR_B_LOWPASS_MASK) >> RDC_IIR_B_LOWPASS_SHIFT) - -/* - * IIR_B (RW) - * - * IIR parameter for b branch - */ -#define RDC_IIR_B_IIR_B_MASK (0x7U) -#define RDC_IIR_B_IIR_B_SHIFT (0U) -#define RDC_IIR_B_IIR_B_SET(x) (((uint32_t)(x) << RDC_IIR_B_IIR_B_SHIFT) & RDC_IIR_B_IIR_B_MASK) -#define RDC_IIR_B_IIR_B_GET(x) (((uint32_t)(x) & RDC_IIR_B_IIR_B_MASK) >> RDC_IIR_B_IIR_B_SHIFT) - -/* Bitfield definition for register: IIR_A */ -/* - * IIR_A2 (RW) - * - * IIR parameter a2 for a branch - */ -#define RDC_IIR_A_IIR_A2_MASK (0xFF0000UL) -#define RDC_IIR_A_IIR_A2_SHIFT (16U) -#define RDC_IIR_A_IIR_A2_SET(x) (((uint32_t)(x) << RDC_IIR_A_IIR_A2_SHIFT) & RDC_IIR_A_IIR_A2_MASK) -#define RDC_IIR_A_IIR_A2_GET(x) (((uint32_t)(x) & RDC_IIR_A_IIR_A2_MASK) >> RDC_IIR_A_IIR_A2_SHIFT) - -/* - * IIR_A1 (RW) - * - * IIR parameter a1 for a branch - */ -#define RDC_IIR_A_IIR_A1_MASK (0x1FFU) -#define RDC_IIR_A_IIR_A1_SHIFT (0U) -#define RDC_IIR_A_IIR_A1_SET(x) (((uint32_t)(x) << RDC_IIR_A_IIR_A1_SHIFT) & RDC_IIR_A_IIR_A1_MASK) -#define RDC_IIR_A_IIR_A1_GET(x) (((uint32_t)(x) & RDC_IIR_A_IIR_A1_MASK) >> RDC_IIR_A_IIR_A1_SHIFT) - -/* Bitfield definition for register: EXC_TIMMING */ -/* - * SWAP (RW) - * - * Swap output of PWM and DAC - * 0: disable swap - * 1: swap output - */ -#define RDC_EXC_TIMMING_SWAP_MASK (0x1000000UL) -#define RDC_EXC_TIMMING_SWAP_SHIFT (24U) -#define RDC_EXC_TIMMING_SWAP_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SWAP_SHIFT) & RDC_EXC_TIMMING_SWAP_MASK) -#define RDC_EXC_TIMMING_SWAP_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SWAP_MASK) >> RDC_EXC_TIMMING_SWAP_SHIFT) - -/* - * PWM_PRD (RW) - * - * Pwm period in samples， - * 0：1 sample period - * 1: 2 sample period - * ... - * 15: 16 sample period - */ -#define RDC_EXC_TIMMING_PWM_PRD_MASK (0xF00000UL) -#define RDC_EXC_TIMMING_PWM_PRD_SHIFT (20U) -#define RDC_EXC_TIMMING_PWM_PRD_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_PWM_PRD_SHIFT) & RDC_EXC_TIMMING_PWM_PRD_MASK) -#define RDC_EXC_TIMMING_PWM_PRD_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_PWM_PRD_MASK) >> RDC_EXC_TIMMING_PWM_PRD_SHIFT) - -/* - * SMP_NUM (RW) - * - * Number of sample every excitation period - * 0: 4 point - * 1: 8 point - * … - * 8: 1024 point - */ -#define RDC_EXC_TIMMING_SMP_NUM_MASK (0xF0000UL) -#define RDC_EXC_TIMMING_SMP_NUM_SHIFT (16U) -#define RDC_EXC_TIMMING_SMP_NUM_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_NUM_SHIFT) & RDC_EXC_TIMMING_SMP_NUM_MASK) -#define RDC_EXC_TIMMING_SMP_NUM_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_NUM_MASK) >> RDC_EXC_TIMMING_SMP_NUM_SHIFT) - -/* - * SMP_RATE (RW) - * - * The period for excitation sample in clock cycle， - * 0: not allowed - * 1: 1 cycle - * 2: 2 cycles - * … - * 65535 : 65535 cycles - */ -#define RDC_EXC_TIMMING_SMP_RATE_MASK (0xFFFFU) -#define RDC_EXC_TIMMING_SMP_RATE_SHIFT (0U) -#define RDC_EXC_TIMMING_SMP_RATE_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_RATE_SHIFT) & RDC_EXC_TIMMING_SMP_RATE_MASK) -#define RDC_EXC_TIMMING_SMP_RATE_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_RATE_MASK) >> RDC_EXC_TIMMING_SMP_RATE_SHIFT) - -/* Bitfield definition for register: EXC_SCALING */ -/* - * AMP_EXP (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_EXC_SCALING_AMP_EXP_MASK (0xF0U) -#define RDC_EXC_SCALING_AMP_EXP_SHIFT (4U) -#define RDC_EXC_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_EXP_SHIFT) & RDC_EXC_SCALING_AMP_EXP_MASK) -#define RDC_EXC_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_EXP_MASK) >> RDC_EXC_SCALING_AMP_EXP_SHIFT) - -/* - * AMP_MAN (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_EXC_SCALING_AMP_MAN_MASK (0xFU) -#define RDC_EXC_SCALING_AMP_MAN_SHIFT (0U) -#define RDC_EXC_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_MAN_SHIFT) & RDC_EXC_SCALING_AMP_MAN_MASK) -#define RDC_EXC_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_MAN_MASK) >> RDC_EXC_SCALING_AMP_MAN_SHIFT) - -/* Bitfield definition for register: EXC_OFFSET */ -/* - * AMP_OFFSET (RW) - * - * Offset for excitation - */ -#define RDC_EXC_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) -#define RDC_EXC_OFFSET_AMP_OFFSET_SHIFT (0U) -#define RDC_EXC_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) -#define RDC_EXC_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) >> RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) - -/* Bitfield definition for register: PWM_SCALING */ -/* - * N_POL (RW) - * - * Polarity of exc_n signal - * 0: high active - * 1: low active - */ -#define RDC_PWM_SCALING_N_POL_MASK (0x2000U) -#define RDC_PWM_SCALING_N_POL_SHIFT (13U) -#define RDC_PWM_SCALING_N_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_N_POL_SHIFT) & RDC_PWM_SCALING_N_POL_MASK) -#define RDC_PWM_SCALING_N_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_N_POL_MASK) >> RDC_PWM_SCALING_N_POL_SHIFT) - -/* - * P_POL (RW) - * - * Polarity of exc_p signal - * 0: high active - * 1: low active - */ -#define RDC_PWM_SCALING_P_POL_MASK (0x1000U) -#define RDC_PWM_SCALING_P_POL_SHIFT (12U) -#define RDC_PWM_SCALING_P_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_P_POL_SHIFT) & RDC_PWM_SCALING_P_POL_MASK) -#define RDC_PWM_SCALING_P_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_P_POL_MASK) >> RDC_PWM_SCALING_P_POL_SHIFT) - -/* - * DITHER (RW) - * - * Enable dither of pwm - * 0: disable - * 1: enable - */ -#define RDC_PWM_SCALING_DITHER_MASK (0x100U) -#define RDC_PWM_SCALING_DITHER_SHIFT (8U) -#define RDC_PWM_SCALING_DITHER_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_DITHER_SHIFT) & RDC_PWM_SCALING_DITHER_MASK) -#define RDC_PWM_SCALING_DITHER_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_DITHER_MASK) >> RDC_PWM_SCALING_DITHER_SHIFT) - -/* - * AMP_EXP (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_PWM_SCALING_AMP_EXP_MASK (0xF0U) -#define RDC_PWM_SCALING_AMP_EXP_SHIFT (4U) -#define RDC_PWM_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_EXP_SHIFT) & RDC_PWM_SCALING_AMP_EXP_MASK) -#define RDC_PWM_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_EXP_MASK) >> RDC_PWM_SCALING_AMP_EXP_SHIFT) - -/* - * AMP_MAN (RW) - * - * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp - */ -#define RDC_PWM_SCALING_AMP_MAN_MASK (0xFU) -#define RDC_PWM_SCALING_AMP_MAN_SHIFT (0U) -#define RDC_PWM_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_MAN_SHIFT) & RDC_PWM_SCALING_AMP_MAN_MASK) -#define RDC_PWM_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_MAN_MASK) >> RDC_PWM_SCALING_AMP_MAN_SHIFT) - -/* Bitfield definition for register: PWM_OFFSET */ -/* - * AMP_OFFSET (RW) - * - * Offset for excitation - */ -#define RDC_PWM_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL) -#define RDC_PWM_OFFSET_AMP_OFFSET_SHIFT (0U) -#define RDC_PWM_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) -#define RDC_PWM_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) >> RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) - -/* Bitfield definition for register: TRIG_OUT0_CFG */ -/* - * ENABLE (RW) - * - * Enable trigger out0 - * 0: disable - * 1: enable - */ -#define RDC_TRIG_OUT0_CFG_ENABLE_MASK (0x100000UL) -#define RDC_TRIG_OUT0_CFG_ENABLE_SHIFT (20U) -#define RDC_TRIG_OUT0_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) -#define RDC_TRIG_OUT0_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) >> RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) - -/* - * LEAD_TIM (RW) - * - * Lead time for trigger out0 from center of low level , this is a signed value - * … - * 2: 2 cycle befor center of low level - * 1: 1 cycle before center of low level - * 0: center of low level - * -1: 1cycle after center of low level - * -2: 2cycle after center of low level - */ -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK (0xFFFFFUL) -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT (0U) -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) -#define RDC_TRIG_OUT0_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) - -/* Bitfield definition for register: TRIG_OUT1_CFG */ -/* - * ENABLE (RW) - * - * Enable trigger out1 - * 0: disable - * 1: enable - */ -#define RDC_TRIG_OUT1_CFG_ENABLE_MASK (0x100000UL) -#define RDC_TRIG_OUT1_CFG_ENABLE_SHIFT (20U) -#define RDC_TRIG_OUT1_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) -#define RDC_TRIG_OUT1_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) >> RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) - -/* - * LEAD_TIM (RW) - * - * Lead time for trigger out0 from center of hight level , this is a signed value - * … - * 2: 2 cycle befor center of hight level - * 1: 1 cycle before center of hight level - * 0: center of hight level - * -1: 1cycle after center of hight level - * -2: 2cycle after center of hight level - */ -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK (0xFFFFFUL) -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT (0U) -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) -#define RDC_TRIG_OUT1_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) - -/* Bitfield definition for register: PWM_DZ */ -/* - * DZ_N (RW) - * - * Exc_n dead zone in clock cycle before swap - * 0: no dead zone - * 1: 1 cycle dead zone - * 2: 2 cycle dead zone - * … - */ -#define RDC_PWM_DZ_DZ_N_MASK (0xFF00U) -#define RDC_PWM_DZ_DZ_N_SHIFT (8U) -#define RDC_PWM_DZ_DZ_N_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_N_SHIFT) & RDC_PWM_DZ_DZ_N_MASK) -#define RDC_PWM_DZ_DZ_N_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_N_MASK) >> RDC_PWM_DZ_DZ_N_SHIFT) - -/* - * DZ_P (RW) - * - * Exc_p dead zone in clock cycle before swap - * 0: no dead zone - * 1: 1 cycle dead zone - * 2: 2 cycle dead zone - * … - */ -#define RDC_PWM_DZ_DZ_P_MASK (0xFFU) -#define RDC_PWM_DZ_DZ_P_SHIFT (0U) -#define RDC_PWM_DZ_DZ_P_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_P_SHIFT) & RDC_PWM_DZ_DZ_P_MASK) -#define RDC_PWM_DZ_DZ_P_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_P_MASK) >> RDC_PWM_DZ_DZ_P_SHIFT) - -/* Bitfield definition for register: SYNC_OUT_CTRL */ -/* - * PWM_OUT_DLY (RO) - * - * Delay bettween the delyed trigger and the first pwm pulse in clock cycle - * 1: 1 cycle - * 2: 2 cycle - * … - */ -#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK (0xFFFF0000UL) -#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT (16U) -#define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK) >> RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT) - -/* - * MIN2TRIG_EN (RW) - * - * Enable trigger out from the min point of exciting signal - * 1: enable - * 0: disable - */ -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK (0x20U) -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT (5U) -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) -#define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) - -/* - * MAX2TRIG_EN (RW) - * - * Enable trigger out from the max point of exciting signal - * 1: enable - * 0: disable - */ -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK (0x10U) -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT (4U) -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) -#define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) - -/* - * SYNC_OUT_SEL (RW) - * - * Select output synchornize signal - * 0: 0 phase of internal exciting signal - * 1: 90 phase of internal exciting signal - * 2: 180 phase of internal exciting signal - * 3: 270 phase of internal exciting signal - */ -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK (0x3U) -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT (0U) -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) -#define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) >> RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) - -/* Bitfield definition for register: EXC_SYNC_DLY */ -/* - * DISABLE (RW) - * - * Disable hardware trigger input - * 0: enable - * 1: disable - */ -#define RDC_EXC_SYNC_DLY_DISABLE_MASK (0x1000000UL) -#define RDC_EXC_SYNC_DLY_DISABLE_SHIFT (24U) -#define RDC_EXC_SYNC_DLY_DISABLE_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DISABLE_SHIFT) & RDC_EXC_SYNC_DLY_DISABLE_MASK) -#define RDC_EXC_SYNC_DLY_DISABLE_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DISABLE_MASK) >> RDC_EXC_SYNC_DLY_DISABLE_SHIFT) - -/* - * DELAY (RW) - * - * Trigger in delay timming in bus cycle from rising edge of trigger signal - * 0: 1 cycle - * 1: 2 cycle - * … - * 0xffffff: 2^24 cycle - */ -#define RDC_EXC_SYNC_DLY_DELAY_MASK (0xFFFFFFUL) -#define RDC_EXC_SYNC_DLY_DELAY_SHIFT (0U) -#define RDC_EXC_SYNC_DLY_DELAY_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DELAY_SHIFT) & RDC_EXC_SYNC_DLY_DELAY_MASK) -#define RDC_EXC_SYNC_DLY_DELAY_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DELAY_MASK) >> RDC_EXC_SYNC_DLY_DELAY_SHIFT) - -/* Bitfield definition for register: MAX_MIN_POS */ -/* - * MAX_MIN_POS (RW) - * - * max min value position - * 0: max min value at adc input - * 1: max min value at IIR output - */ -#define RDC_MAX_MIN_POS_MAX_MIN_POS_MASK (0x1U) -#define RDC_MAX_MIN_POS_MAX_MIN_POS_SHIFT (0U) -#define RDC_MAX_MIN_POS_MAX_MIN_POS_SET(x) (((uint32_t)(x) << RDC_MAX_MIN_POS_MAX_MIN_POS_SHIFT) & RDC_MAX_MIN_POS_MAX_MIN_POS_MASK) -#define RDC_MAX_MIN_POS_MAX_MIN_POS_GET(x) (((uint32_t)(x) & RDC_MAX_MIN_POS_MAX_MIN_POS_MASK) >> RDC_MAX_MIN_POS_MAX_MIN_POS_SHIFT) - -/* Bitfield definition for register: MAX_I */ -/* - * MAX (RWC) - * - * Max value of i_channel, write clear - */ -#define RDC_MAX_I_MAX_MASK (0xFFFFFF00UL) -#define RDC_MAX_I_MAX_SHIFT (8U) -#define RDC_MAX_I_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_I_MAX_SHIFT) & RDC_MAX_I_MAX_MASK) -#define RDC_MAX_I_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_I_MAX_MASK) >> RDC_MAX_I_MAX_SHIFT) - -/* - * VALID (RWC) - * - * Max value valid, write clear - * 0: max value is not valid - * 1: max value is valid - */ -#define RDC_MAX_I_VALID_MASK (0x1U) -#define RDC_MAX_I_VALID_SHIFT (0U) -#define RDC_MAX_I_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_I_VALID_SHIFT) & RDC_MAX_I_VALID_MASK) -#define RDC_MAX_I_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_I_VALID_MASK) >> RDC_MAX_I_VALID_SHIFT) - -/* Bitfield definition for register: MIN_I */ -/* - * MIN (RWC) - * - * Min value of i_channel, write clear - */ -#define RDC_MIN_I_MIN_MASK (0xFFFFFF00UL) -#define RDC_MIN_I_MIN_SHIFT (8U) -#define RDC_MIN_I_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_I_MIN_SHIFT) & RDC_MIN_I_MIN_MASK) -#define RDC_MIN_I_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_I_MIN_MASK) >> RDC_MIN_I_MIN_SHIFT) - -/* - * VALID (RWC) - * - * Min value valid, write clear - * 0: min value is not valid - * 1: min value is valid - */ -#define RDC_MIN_I_VALID_MASK (0x1U) -#define RDC_MIN_I_VALID_SHIFT (0U) -#define RDC_MIN_I_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_I_VALID_SHIFT) & RDC_MIN_I_VALID_MASK) -#define RDC_MIN_I_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_I_VALID_MASK) >> RDC_MIN_I_VALID_SHIFT) - -/* Bitfield definition for register: MAX_Q */ -/* - * MAX (RWC) - * - * Max value of q_channel, write clear - */ -#define RDC_MAX_Q_MAX_MASK (0xFFFFFF00UL) -#define RDC_MAX_Q_MAX_SHIFT (8U) -#define RDC_MAX_Q_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_Q_MAX_SHIFT) & RDC_MAX_Q_MAX_MASK) -#define RDC_MAX_Q_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_Q_MAX_MASK) >> RDC_MAX_Q_MAX_SHIFT) - -/* - * VALID (RWC) - * - * Max value valid, write clear - * 0: max value is not valid - * 1: max value is valid - */ -#define RDC_MAX_Q_VALID_MASK (0x1U) -#define RDC_MAX_Q_VALID_SHIFT (0U) -#define RDC_MAX_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_Q_VALID_SHIFT) & RDC_MAX_Q_VALID_MASK) -#define RDC_MAX_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_Q_VALID_MASK) >> RDC_MAX_Q_VALID_SHIFT) - -/* Bitfield definition for register: MIN_Q */ -/* - * MIN (RWC) - * - * Min value of q_channel, write clear - */ -#define RDC_MIN_Q_MIN_MASK (0xFFFFFF00UL) -#define RDC_MIN_Q_MIN_SHIFT (8U) -#define RDC_MIN_Q_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_Q_MIN_SHIFT) & RDC_MIN_Q_MIN_MASK) -#define RDC_MIN_Q_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_Q_MIN_MASK) >> RDC_MIN_Q_MIN_SHIFT) - -/* - * VALID (RWC) - * - * Min value valid, write clear - * 0: min value is not valid - * 1: min value is valid - */ -#define RDC_MIN_Q_VALID_MASK (0x1U) -#define RDC_MIN_Q_VALID_SHIFT (0U) -#define RDC_MIN_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_Q_VALID_SHIFT) & RDC_MIN_Q_VALID_MASK) -#define RDC_MIN_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_Q_VALID_MASK) >> RDC_MIN_Q_VALID_SHIFT) - -/* Bitfield definition for register: THRS_I */ -/* - * THRS (RW) - * - * The offset setting for edge detection of the i_channel, signed number - * … - * 2: the offset is 0x800000+2 - * 1: the offset is 0x800000+1 - * 0: the offset is 0x800000 - * -1: the offset is 0x800000-1 - * -2: the offset is 0x800000-2 - * … - */ -#define RDC_THRS_I_THRS_MASK (0xFFFFFF00UL) -#define RDC_THRS_I_THRS_SHIFT (8U) -#define RDC_THRS_I_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_I_THRS_SHIFT) & RDC_THRS_I_THRS_MASK) -#define RDC_THRS_I_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_I_THRS_MASK) >> RDC_THRS_I_THRS_SHIFT) - -/* - * THRS4ACC (RW) - * - * enable thrs data for accumulate - */ -#define RDC_THRS_I_THRS4ACC_MASK (0x1U) -#define RDC_THRS_I_THRS4ACC_SHIFT (0U) -#define RDC_THRS_I_THRS4ACC_SET(x) (((uint32_t)(x) << RDC_THRS_I_THRS4ACC_SHIFT) & RDC_THRS_I_THRS4ACC_MASK) -#define RDC_THRS_I_THRS4ACC_GET(x) (((uint32_t)(x) & RDC_THRS_I_THRS4ACC_MASK) >> RDC_THRS_I_THRS4ACC_SHIFT) - -/* Bitfield definition for register: THRS_Q */ -/* - * THRS (RW) - * - * The offset setting for edge detection of the q_channel, signed number - * … - * 2: the offset is 0x800000+2 - * 1: the offset is 0x800000+1 - * 0: the offset is 0x800000 - * -1: the offset is 0x800000-1 - * -2: the offset is 0x800000-2 - * … - */ -#define RDC_THRS_Q_THRS_MASK (0xFFFFFF00UL) -#define RDC_THRS_Q_THRS_SHIFT (8U) -#define RDC_THRS_Q_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_Q_THRS_SHIFT) & RDC_THRS_Q_THRS_MASK) -#define RDC_THRS_Q_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_Q_THRS_MASK) >> RDC_THRS_Q_THRS_SHIFT) - -/* - * THRS4ACC (RW) - * - * enable thrs data for accumulate - */ -#define RDC_THRS_Q_THRS4ACC_MASK (0x1U) -#define RDC_THRS_Q_THRS4ACC_SHIFT (0U) -#define RDC_THRS_Q_THRS4ACC_SET(x) (((uint32_t)(x) << RDC_THRS_Q_THRS4ACC_SHIFT) & RDC_THRS_Q_THRS4ACC_MASK) -#define RDC_THRS_Q_THRS4ACC_GET(x) (((uint32_t)(x) & RDC_THRS_Q_THRS4ACC_MASK) >> RDC_THRS_Q_THRS4ACC_SHIFT) - -/* Bitfield definition for register: EDG_DET_CTL */ -/* - * HOLD (RW) - * - * The minimum edge distance in sample - * 0:1 sample - * 1:2 sample - * 2:3 samples - * … - * 63:64 samples - */ -#define RDC_EDG_DET_CTL_HOLD_MASK (0x3F0U) -#define RDC_EDG_DET_CTL_HOLD_SHIFT (4U) -#define RDC_EDG_DET_CTL_HOLD_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_HOLD_SHIFT) & RDC_EDG_DET_CTL_HOLD_MASK) -#define RDC_EDG_DET_CTL_HOLD_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_HOLD_MASK) >> RDC_EDG_DET_CTL_HOLD_SHIFT) - -/* - * FILTER (RW) - * - * The continuous positive or negative number for edge detection - * 0: 1 - * 1: 2 - * … - * 7: 8 - */ -#define RDC_EDG_DET_CTL_FILTER_MASK (0x7U) -#define RDC_EDG_DET_CTL_FILTER_SHIFT (0U) -#define RDC_EDG_DET_CTL_FILTER_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_FILTER_SHIFT) & RDC_EDG_DET_CTL_FILTER_MASK) -#define RDC_EDG_DET_CTL_FILTER_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_FILTER_MASK) >> RDC_EDG_DET_CTL_FILTER_SHIFT) - -/* Bitfield definition for register: ACC_SCALING */ -/* - * TOXIC_LK (RW) - * - * Toxic accumulation data be removed control - * 1: enable - * 0: disable - */ -#define RDC_ACC_SCALING_TOXIC_LK_MASK (0x100U) -#define RDC_ACC_SCALING_TOXIC_LK_SHIFT (8U) -#define RDC_ACC_SCALING_TOXIC_LK_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_TOXIC_LK_SHIFT) & RDC_ACC_SCALING_TOXIC_LK_MASK) -#define RDC_ACC_SCALING_TOXIC_LK_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_TOXIC_LK_MASK) >> RDC_ACC_SCALING_TOXIC_LK_SHIFT) - -/* - * ACC_SHIFT (RW) - * - * Accumulation value shift control, this is a sign number. - * 0: {acc[39],acc[38:8]} - * 1: {acc[39],acc[37:7]} - * 2: {acc[39],acc[36:6]} - * … - * 7: {acc[39],acc[31:1]} - * 8: {acc[39],acc[30:0]} - * 9: acc/2^9 - * 10: acc/2^10 - * … - * 15:acc/2^15 - */ -#define RDC_ACC_SCALING_ACC_SHIFT_MASK (0xFU) -#define RDC_ACC_SCALING_ACC_SHIFT_SHIFT (0U) -#define RDC_ACC_SCALING_ACC_SHIFT_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_ACC_SHIFT_SHIFT) & RDC_ACC_SCALING_ACC_SHIFT_MASK) -#define RDC_ACC_SCALING_ACC_SHIFT_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_ACC_SHIFT_MASK) >> RDC_ACC_SCALING_ACC_SHIFT_SHIFT) - -/* Bitfield definition for register: EXC_PERIOD */ -/* - * EXC_PERIOD (RW) - * - * The num in clock cycle for period of excitation - * 0: invalid value - * 1:1 cycle - * 2:2 cycles - * … - */ -#define RDC_EXC_PERIOD_EXC_PERIOD_MASK (0xFFFFFFFFUL) -#define RDC_EXC_PERIOD_EXC_PERIOD_SHIFT (0U) -#define RDC_EXC_PERIOD_EXC_PERIOD_SET(x) (((uint32_t)(x) << RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) -#define RDC_EXC_PERIOD_EXC_PERIOD_GET(x) (((uint32_t)(x) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) >> RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) - -/* Bitfield definition for register: SYNC_DELAY_I */ -/* - * DELAY (RW) - * - * Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. - * 0: invalid value - * 1: 1 cycles - * 2: 2 cycles - * ... - */ -#define RDC_SYNC_DELAY_I_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_SYNC_DELAY_I_DELAY_SHIFT (0U) -#define RDC_SYNC_DELAY_I_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_I_DELAY_SHIFT) & RDC_SYNC_DELAY_I_DELAY_MASK) -#define RDC_SYNC_DELAY_I_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_I_DELAY_MASK) >> RDC_SYNC_DELAY_I_DELAY_SHIFT) - -/* Bitfield definition for register: RISE_DELAY_I */ -/* - * RISE_DELAY (RO) - * - * Delay value on rising edge of i_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_RISE_DELAY_I_RISE_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_RISE_DELAY_I_RISE_DELAY_SHIFT (0U) -#define RDC_RISE_DELAY_I_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_I_RISE_DELAY_MASK) >> RDC_RISE_DELAY_I_RISE_DELAY_SHIFT) - -/* Bitfield definition for register: FALL_DELAY_I */ -/* - * FALL_DELAY (RO) - * - * Delay value on falling edge of i_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_FALL_DELAY_I_FALL_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_FALL_DELAY_I_FALL_DELAY_SHIFT (0U) -#define RDC_FALL_DELAY_I_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_I_FALL_DELAY_MASK) >> RDC_FALL_DELAY_I_FALL_DELAY_SHIFT) - -/* Bitfield definition for register: SAMPLE_RISE_I */ -/* - * VALUE (RO) - * - * sample value on rising edge of rectify signal - */ -#define RDC_SAMPLE_RISE_I_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_RISE_I_VALUE_SHIFT (8U) -#define RDC_SAMPLE_RISE_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_I_VALUE_MASK) >> RDC_SAMPLE_RISE_I_VALUE_SHIFT) - -/* Bitfield definition for register: SAMPLE_FALL_I */ -/* - * VALUE (RO) - * - * sample value on falling edge of rectify signal - */ -#define RDC_SAMPLE_FALL_I_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_FALL_I_VALUE_SHIFT (8U) -#define RDC_SAMPLE_FALL_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_I_VALUE_MASK) >> RDC_SAMPLE_FALL_I_VALUE_SHIFT) - -/* Bitfield definition for register: ACC_CNT_I */ -/* - * CNT_NEG (RO) - * - * sample number during the negtive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_ACC_CNT_I_CNT_NEG_SHIFT (16U) -#define RDC_ACC_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_NEG_MASK) >> RDC_ACC_CNT_I_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * sample number during the positive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_I_CNT_POS_MASK (0xFFFFU) -#define RDC_ACC_CNT_I_CNT_POS_SHIFT (0U) -#define RDC_ACC_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_POS_MASK) >> RDC_ACC_CNT_I_CNT_POS_SHIFT) - -/* Bitfield definition for register: SIGN_CNT_I */ -/* - * CNT_NEG (RO) - * - * Positive sample counter during negative rectify signal - */ -#define RDC_SIGN_CNT_I_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_SIGN_CNT_I_CNT_NEG_SHIFT (16U) -#define RDC_SIGN_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_NEG_MASK) >> RDC_SIGN_CNT_I_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * Negative sample counter during positive rectify signal - */ -#define RDC_SIGN_CNT_I_CNT_POS_MASK (0xFFFFU) -#define RDC_SIGN_CNT_I_CNT_POS_SHIFT (0U) -#define RDC_SIGN_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_POS_MASK) >> RDC_SIGN_CNT_I_CNT_POS_SHIFT) - -/* Bitfield definition for register: SYNC_DELAY_Q */ -/* - * DELAY (RW) - * - * Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period. - * 0: invalid value - * 1: 1 cycles - * 2: 2 cycles - * ... - */ -#define RDC_SYNC_DELAY_Q_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_SYNC_DELAY_Q_DELAY_SHIFT (0U) -#define RDC_SYNC_DELAY_Q_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_Q_DELAY_SHIFT) & RDC_SYNC_DELAY_Q_DELAY_MASK) -#define RDC_SYNC_DELAY_Q_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_Q_DELAY_MASK) >> RDC_SYNC_DELAY_Q_DELAY_SHIFT) - -/* Bitfield definition for register: RISE_DELAY_Q */ -/* - * RISE_DELAY (RO) - * - * Delay value on rising edge of q_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_RISE_DELAY_Q_RISE_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT (0U) -#define RDC_RISE_DELAY_Q_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_Q_RISE_DELAY_MASK) >> RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT) - -/* Bitfield definition for register: FALL_DELAY_Q */ -/* - * FALL_DELAY (RO) - * - * Delay value on falling edge of q_channel data - * 0: 1 cycle - * 1: 2 cycles - * … - */ -#define RDC_FALL_DELAY_Q_FALL_DELAY_MASK (0xFFFFFFFFUL) -#define RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT (0U) -#define RDC_FALL_DELAY_Q_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_Q_FALL_DELAY_MASK) >> RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT) - -/* Bitfield definition for register: SAMPLE_RISE_Q */ -/* - * VALUE (RO) - * - * sample value on rising edge of rectify signal - */ -#define RDC_SAMPLE_RISE_Q_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_RISE_Q_VALUE_SHIFT (8U) -#define RDC_SAMPLE_RISE_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_Q_VALUE_MASK) >> RDC_SAMPLE_RISE_Q_VALUE_SHIFT) - -/* Bitfield definition for register: SAMPLE_FALL_Q */ -/* - * VALUE (RO) - * - * sample value on falling edge of rectify signal - */ -#define RDC_SAMPLE_FALL_Q_VALUE_MASK (0xFFFFFF00UL) -#define RDC_SAMPLE_FALL_Q_VALUE_SHIFT (8U) -#define RDC_SAMPLE_FALL_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_Q_VALUE_MASK) >> RDC_SAMPLE_FALL_Q_VALUE_SHIFT) - -/* Bitfield definition for register: ACC_CNT_Q */ -/* - * CNT_NEG (RO) - * - * sample number during the negtive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_ACC_CNT_Q_CNT_NEG_SHIFT (16U) -#define RDC_ACC_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_NEG_MASK) >> RDC_ACC_CNT_Q_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * sample number during the positive of rectify signal - * 1: 1 - * 2: 2 - * … - */ -#define RDC_ACC_CNT_Q_CNT_POS_MASK (0xFFFFU) -#define RDC_ACC_CNT_Q_CNT_POS_SHIFT (0U) -#define RDC_ACC_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_POS_MASK) >> RDC_ACC_CNT_Q_CNT_POS_SHIFT) - -/* Bitfield definition for register: SIGN_CNT_Q */ -/* - * CNT_NEG (RO) - * - * Positive sample counter during negative rectify signal - */ -#define RDC_SIGN_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL) -#define RDC_SIGN_CNT_Q_CNT_NEG_SHIFT (16U) -#define RDC_SIGN_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_NEG_MASK) >> RDC_SIGN_CNT_Q_CNT_NEG_SHIFT) - -/* - * CNT_POS (RO) - * - * Negative sample counter during positive rectify signal - */ -#define RDC_SIGN_CNT_Q_CNT_POS_MASK (0xFFFFU) -#define RDC_SIGN_CNT_Q_CNT_POS_SHIFT (0U) -#define RDC_SIGN_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_POS_MASK) >> RDC_SIGN_CNT_Q_CNT_POS_SHIFT) - -/* Bitfield definition for register: AMP_MAX */ -/* - * MAX (RW) - * - * the maximum of acc amplitude - */ -#define RDC_AMP_MAX_MAX_MASK (0xFFFFFFFFUL) -#define RDC_AMP_MAX_MAX_SHIFT (0U) -#define RDC_AMP_MAX_MAX_SET(x) (((uint32_t)(x) << RDC_AMP_MAX_MAX_SHIFT) & RDC_AMP_MAX_MAX_MASK) -#define RDC_AMP_MAX_MAX_GET(x) (((uint32_t)(x) & RDC_AMP_MAX_MAX_MASK) >> RDC_AMP_MAX_MAX_SHIFT) - -/* Bitfield definition for register: AMP_MIN */ -/* - * MIN (RW) - * - * the minimum of acc amplitude - */ -#define RDC_AMP_MIN_MIN_MASK (0xFFFFFFFFUL) -#define RDC_AMP_MIN_MIN_SHIFT (0U) -#define RDC_AMP_MIN_MIN_SET(x) (((uint32_t)(x) << RDC_AMP_MIN_MIN_SHIFT) & RDC_AMP_MIN_MIN_MASK) -#define RDC_AMP_MIN_MIN_GET(x) (((uint32_t)(x) & RDC_AMP_MIN_MIN_MASK) >> RDC_AMP_MIN_MIN_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * INT_EN (RW) - * - * enable interrupt output - */ -#define RDC_INT_EN_INT_EN_MASK (0x80000000UL) -#define RDC_INT_EN_INT_EN_SHIFT (31U) -#define RDC_INT_EN_INT_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_INT_EN_SHIFT) & RDC_INT_EN_INT_EN_MASK) -#define RDC_INT_EN_INT_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_INT_EN_MASK) >> RDC_INT_EN_INT_EN_SHIFT) - -/* - * ACC_VLD_I_EN (RW) - * - * i_channel accumulate valid interrupt enable for i_channel - */ -#define RDC_INT_EN_ACC_VLD_I_EN_MASK (0x8000U) -#define RDC_INT_EN_ACC_VLD_I_EN_SHIFT (15U) -#define RDC_INT_EN_ACC_VLD_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_EN_MASK) -#define RDC_INT_EN_ACC_VLD_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_EN_SHIFT) - -/* - * ACC_VLD_Q_EN (RW) - * - * q_channel accumulate valid interrupt enable for i_channel - */ -#define RDC_INT_EN_ACC_VLD_Q_EN_MASK (0x4000U) -#define RDC_INT_EN_ACC_VLD_Q_EN_SHIFT (14U) -#define RDC_INT_EN_ACC_VLD_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) -#define RDC_INT_EN_ACC_VLD_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) - -/* - * RISING_DELAY_I_EN (RW) - * - * i_channel delayed rectify signal rising edge interrupt enable - */ -#define RDC_INT_EN_RISING_DELAY_I_EN_MASK (0x2000U) -#define RDC_INT_EN_RISING_DELAY_I_EN_SHIFT (13U) -#define RDC_INT_EN_RISING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) -#define RDC_INT_EN_RISING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) >> RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) - -/* - * FALLING_DELAY_I_EN (RW) - * - * i_channel delayed rectify signal falling edge interrupt enable - */ -#define RDC_INT_EN_FALLING_DELAY_I_EN_MASK (0x1000U) -#define RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT (12U) -#define RDC_INT_EN_FALLING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) -#define RDC_INT_EN_FALLING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) - -/* - * RISING_DELAY_Q_EN (RW) - * - * q_channel delayed rectify signal rising edge interrupt enable - */ -#define RDC_INT_EN_RISING_DELAY_Q_EN_MASK (0x800U) -#define RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT (11U) -#define RDC_INT_EN_RISING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) -#define RDC_INT_EN_RISING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) >> RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) - -/* - * FALLING_DELAY_Q_EN (RW) - * - * q_channel delayed rectify signal falling edge interrupt enable - */ -#define RDC_INT_EN_FALLING_DELAY_Q_EN_MASK (0x400U) -#define RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT (10U) -#define RDC_INT_EN_FALLING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) -#define RDC_INT_EN_FALLING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) - -/* - * SAMPLE_RISING_I_EN (RW) - * - * i_channel rising edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_RISING_I_EN_MASK (0x200U) -#define RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT (9U) -#define RDC_INT_EN_SAMPLE_RISING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) -#define RDC_INT_EN_SAMPLE_RISING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) - -/* - * SAMPLE_FALLING_I_EN (RW) - * - * i_channel falling edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK (0x100U) -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT (8U) -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) -#define RDC_INT_EN_SAMPLE_FALLING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) - -/* - * SAMPLE_RISING_Q_EN (RW) - * - * q_channel rising edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK (0x80U) -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT (7U) -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) -#define RDC_INT_EN_SAMPLE_RISING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) - -/* - * SAMPLE_FALLING_Q_EN (RW) - * - * q_channel falling edge interrupt enable - */ -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK (0x40U) -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT (6U) -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) -#define RDC_INT_EN_SAMPLE_FALLING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) - -/* - * ACC_VLD_I_OVH_EN (RW) - * - * i_channel accumulate overflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK (0x20U) -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT (5U) -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) -#define RDC_INT_EN_ACC_VLD_I_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) - -/* - * ACC_VLD_Q_OVH_EN (RW) - * - * q_channel accumulate overflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK (0x10U) -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT (4U) -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) -#define RDC_INT_EN_ACC_VLD_Q_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) - -/* - * ACC_VLD_I_OVL_EN (RW) - * - * i_channel accumulate underflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK (0x8U) -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT (3U) -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) -#define RDC_INT_EN_ACC_VLD_I_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) - -/* - * ACC_VLD_Q_OVL_EN (RW) - * - * q_channel accumulate underflow interrupt enable - */ -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK (0x4U) -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT (2U) -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) -#define RDC_INT_EN_ACC_VLD_Q_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) - -/* - * ACC_AMP_OVH_EN (RW) - * - * accumulate ample overflow interrupt enable - */ -#define RDC_INT_EN_ACC_AMP_OVH_EN_MASK (0x2U) -#define RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT (1U) -#define RDC_INT_EN_ACC_AMP_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) -#define RDC_INT_EN_ACC_AMP_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) - -/* - * ACC_AMP_OVL_EN (RW) - * - * accumulate ample underflow interrupt enable - */ -#define RDC_INT_EN_ACC_AMP_OVL_EN_MASK (0x1U) -#define RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT (0U) -#define RDC_INT_EN_ACC_AMP_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) -#define RDC_INT_EN_ACC_AMP_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) - -/* Bitfield definition for register: ADC_INT_STATE */ -/* - * ACC_VLD_I_STA (W1C) - * - * i_channel accumulate valid interrupt status for i_channel - */ -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK (0x8000U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT (15U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) - -/* - * ACC_VLD_Q_STA (W1C) - * - * q_channel accumulate valid interrupt status for i_channel - */ -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK (0x4000U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT (14U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) - -/* - * RISING_DELAY_I_STA (W1C) - * - * i_channel delayed rectify signal rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK (0x2000U) -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT (13U) -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) -#define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) - -/* - * FALLING_DELAY_I_STA (W1C) - * - * i_channel delayed rectify signal falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK (0x1000U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT (12U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) -#define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) - -/* - * RISING_DELAY_Q_STA (W1C) - * - * q_channel delayed rectify signal rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK (0x800U) -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT (11U) -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) -#define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) - -/* - * FALLING_DELAY_Q_STA (W1C) - * - * q_channel delayed rectify signal falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK (0x400U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT (10U) -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) -#define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) - -/* - * SAMPLE_RISING_I_STA (W1C) - * - * i_channel rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK (0x200U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT (9U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) - -/* - * SAMPLE_FALLING_I_STA (W1C) - * - * i_channel falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK (0x100U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT (8U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) - -/* - * SAMPLE_RISING_Q_STA (W1C) - * - * q_channel rising edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK (0x80U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT (7U) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) - -/* - * SAMPLE_FALLING_Q_STA (W1C) - * - * q_channel falling edge interrupt status - */ -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK (0x40U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT (6U) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) -#define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) - -/* - * ACC_VLD_I_OVH_STA (W1C) - * - * i_channel accumulate overflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK (0x20U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT (5U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) - -/* - * ACC_VLD_Q_OVH_STA (W1C) - * - * q_channel accumulate overflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK (0x10U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT (4U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) - -/* - * ACC_VLD_I_OVL_STA (W1C) - * - * i_channel accumulate underflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK (0x8U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT (3U) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) - -/* - * ACC_VLD_Q_OVL_STA (W1C) - * - * q_channel accumulate underflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK (0x4U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT (2U) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) - -/* - * ACC_AMP_OVH_STA (W1C) - * - * accumulate ample overflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK (0x2U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT (1U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) - -/* - * ACC_AMP_OVL_STA (W1C) - * - * accumulate ample underflow interrupt status - */ -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK (0x1U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT (0U) -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) -#define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) - - - - -#endif /* HPM_RDC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rng_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rng_regs.h deleted file mode 100644 index 1a847f5d090..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rng_regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RNG_H -#define HPM_RNG_H - -typedef struct { - __RW uint32_t CMD; /* 0x0: Command Register */ - __RW uint32_t CTRL; /* 0x4: Control Register */ - __R uint32_t STA; /* 0x8: Status Register */ - __R uint32_t ERR; /* 0xC: Error Registers */ - __R uint32_t FO2B; /* 0x10: FIFO out to bus/cpu */ - __R uint8_t RESERVED0[12]; /* 0x14 - 0x1F: Reserved */ - __R uint32_t R2SK[8]; /* 0x20 - 0x3C: FIFO out to SDP as AES engine key */ -} RNG_Type; - - -/* Bitfield definition for register: CMD */ -/* - * SFTRST (RW) - * - * Soft Reset, Perform a software reset of the RNG This bit is self-clearing. - * 0 Do not perform a software reset. - * 1 Software reset - */ -#define RNG_CMD_SFTRST_MASK (0x40U) -#define RNG_CMD_SFTRST_SHIFT (6U) -#define RNG_CMD_SFTRST_SET(x) (((uint32_t)(x) << RNG_CMD_SFTRST_SHIFT) & RNG_CMD_SFTRST_MASK) -#define RNG_CMD_SFTRST_GET(x) (((uint32_t)(x) & RNG_CMD_SFTRST_MASK) >> RNG_CMD_SFTRST_SHIFT) - -/* - * CLRERR (RW) - * - * Clear the Error, clear the errors in the ESR register and the RNG interrupt. This bit is self-clearing. - * 0 Do not clear the errors and the interrupt. - * 1 Clear the errors and the interrupt. - */ -#define RNG_CMD_CLRERR_MASK (0x20U) -#define RNG_CMD_CLRERR_SHIFT (5U) -#define RNG_CMD_CLRERR_SET(x) (((uint32_t)(x) << RNG_CMD_CLRERR_SHIFT) & RNG_CMD_CLRERR_MASK) -#define RNG_CMD_CLRERR_GET(x) (((uint32_t)(x) & RNG_CMD_CLRERR_MASK) >> RNG_CMD_CLRERR_SHIFT) - -/* - * CLRINT (RW) - * - * Clear the Interrupt, clear the RNG interrupt if an error is not present. This bit is self-clearing. - * 0 Do not clear the interrupt. - * 1 Clear the interrupt - */ -#define RNG_CMD_CLRINT_MASK (0x10U) -#define RNG_CMD_CLRINT_SHIFT (4U) -#define RNG_CMD_CLRINT_SET(x) (((uint32_t)(x) << RNG_CMD_CLRINT_SHIFT) & RNG_CMD_CLRINT_MASK) -#define RNG_CMD_CLRINT_GET(x) (((uint32_t)(x) & RNG_CMD_CLRINT_MASK) >> RNG_CMD_CLRINT_SHIFT) - -/* - * GENSD (RW) - * - * Generate Seed, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_GENSD_MASK (0x2U) -#define RNG_CMD_GENSD_SHIFT (1U) -#define RNG_CMD_GENSD_SET(x) (((uint32_t)(x) << RNG_CMD_GENSD_SHIFT) & RNG_CMD_GENSD_MASK) -#define RNG_CMD_GENSD_GET(x) (((uint32_t)(x) & RNG_CMD_GENSD_MASK) >> RNG_CMD_GENSD_SHIFT) - -/* - * SLFCHK (RW) - * - * Self Test, when both ST and GS triggered, ST first and GS next. - */ -#define RNG_CMD_SLFCHK_MASK (0x1U) -#define RNG_CMD_SLFCHK_SHIFT (0U) -#define RNG_CMD_SLFCHK_SET(x) (((uint32_t)(x) << RNG_CMD_SLFCHK_SHIFT) & RNG_CMD_SLFCHK_MASK) -#define RNG_CMD_SLFCHK_GET(x) (((uint32_t)(x) & RNG_CMD_SLFCHK_MASK) >> RNG_CMD_SLFCHK_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * MIRQERR (RW) - * - * Mask Interrupt Request for Error - */ -#define RNG_CTRL_MIRQERR_MASK (0x40U) -#define RNG_CTRL_MIRQERR_SHIFT (6U) -#define RNG_CTRL_MIRQERR_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQERR_SHIFT) & RNG_CTRL_MIRQERR_MASK) -#define RNG_CTRL_MIRQERR_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQERR_MASK) >> RNG_CTRL_MIRQERR_SHIFT) - -/* - * MIRQDN (RW) - * - * Mask Interrupt Request for Done Event, asks the interrupts generated upon the completion of the seed and self-test modes. The status of these jobs can be viewed by: - * • Reading the STA and viewing the seed done and the self-test done bits (STA[SDN, STDN]). - * • Viewing the RNG_CMD for the generate-seed or the self-test bits (CMD[GS,ST]) being set, indicating that the operation is still taking place. - */ -#define RNG_CTRL_MIRQDN_MASK (0x20U) -#define RNG_CTRL_MIRQDN_SHIFT (5U) -#define RNG_CTRL_MIRQDN_SET(x) (((uint32_t)(x) << RNG_CTRL_MIRQDN_SHIFT) & RNG_CTRL_MIRQDN_MASK) -#define RNG_CTRL_MIRQDN_GET(x) (((uint32_t)(x) & RNG_CTRL_MIRQDN_MASK) >> RNG_CTRL_MIRQDN_SHIFT) - -/* - * AUTRSD (RW) - * - * Auto Reseed - */ -#define RNG_CTRL_AUTRSD_MASK (0x10U) -#define RNG_CTRL_AUTRSD_SHIFT (4U) -#define RNG_CTRL_AUTRSD_SET(x) (((uint32_t)(x) << RNG_CTRL_AUTRSD_SHIFT) & RNG_CTRL_AUTRSD_MASK) -#define RNG_CTRL_AUTRSD_GET(x) (((uint32_t)(x) & RNG_CTRL_AUTRSD_MASK) >> RNG_CTRL_AUTRSD_SHIFT) - -/* - * FUFMOD (RW) - * - * FIFO underflow response mode - * 00 Return all zeros and set the ESR[FUFE]. - * 01 Return all zeros and set the ESR[FUFE]. - * 10 Generate the bus transfer error - * 11 Generate the interrupt and return all zeros (overrides the CTRL[MASKERR]). - */ -#define RNG_CTRL_FUFMOD_MASK (0x3U) -#define RNG_CTRL_FUFMOD_SHIFT (0U) -#define RNG_CTRL_FUFMOD_SET(x) (((uint32_t)(x) << RNG_CTRL_FUFMOD_SHIFT) & RNG_CTRL_FUFMOD_MASK) -#define RNG_CTRL_FUFMOD_GET(x) (((uint32_t)(x) & RNG_CTRL_FUFMOD_MASK) >> RNG_CTRL_FUFMOD_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * SCPF (RO) - * - * Self Check Pass Fail - */ -#define RNG_STA_SCPF_MASK (0xE00000UL) -#define RNG_STA_SCPF_SHIFT (21U) -#define RNG_STA_SCPF_GET(x) (((uint32_t)(x) & RNG_STA_SCPF_MASK) >> RNG_STA_SCPF_SHIFT) - -/* - * FUNCERR (RO) - * - * Error was detected, check ESR register for details - */ -#define RNG_STA_FUNCERR_MASK (0x10000UL) -#define RNG_STA_FUNCERR_SHIFT (16U) -#define RNG_STA_FUNCERR_GET(x) (((uint32_t)(x) & RNG_STA_FUNCERR_MASK) >> RNG_STA_FUNCERR_SHIFT) - -/* - * FSIZE (RO) - * - * Fifo Size, it is 5 in this design. - */ -#define RNG_STA_FSIZE_MASK (0xF000U) -#define RNG_STA_FSIZE_SHIFT (12U) -#define RNG_STA_FSIZE_GET(x) (((uint32_t)(x) & RNG_STA_FSIZE_MASK) >> RNG_STA_FSIZE_SHIFT) - -/* - * FRNNU (RO) - * - * Fifo Level, Indicates the number of random words currently in the output FIFO - */ -#define RNG_STA_FRNNU_MASK (0xF00U) -#define RNG_STA_FRNNU_SHIFT (8U) -#define RNG_STA_FRNNU_GET(x) (((uint32_t)(x) & RNG_STA_FRNNU_MASK) >> RNG_STA_FRNNU_SHIFT) - -/* - * NSDDN (RO) - * - * New seed done. - */ -#define RNG_STA_NSDDN_MASK (0x40U) -#define RNG_STA_NSDDN_SHIFT (6U) -#define RNG_STA_NSDDN_GET(x) (((uint32_t)(x) & RNG_STA_NSDDN_MASK) >> RNG_STA_NSDDN_SHIFT) - -/* - * FSDDN (RO) - * - * 1st Seed done - * When "1", Indicates that the RNG generated the first seed. - */ -#define RNG_STA_FSDDN_MASK (0x20U) -#define RNG_STA_FSDDN_SHIFT (5U) -#define RNG_STA_FSDDN_GET(x) (((uint32_t)(x) & RNG_STA_FSDDN_MASK) >> RNG_STA_FSDDN_SHIFT) - -/* - * SCDN (RO) - * - * Self Check Done - * Indicates whether Self Test is done or not. Can be cleared by the hardware reset or a new self test is - * initiated by setting the CMD[ST]. - * 0 Self test not completed - * 1 Completed a self test since the last reset. - */ -#define RNG_STA_SCDN_MASK (0x10U) -#define RNG_STA_SCDN_SHIFT (4U) -#define RNG_STA_SCDN_GET(x) (((uint32_t)(x) & RNG_STA_SCDN_MASK) >> RNG_STA_SCDN_SHIFT) - -/* - * RSDREQ (RO) - * - * Reseed needed - * Indicates that the RNG needs to be reseeded. This is done by setting the CMD[GS], or - * automatically if the CTRL[ARS] is set. - */ -#define RNG_STA_RSDREQ_MASK (0x8U) -#define RNG_STA_RSDREQ_SHIFT (3U) -#define RNG_STA_RSDREQ_GET(x) (((uint32_t)(x) & RNG_STA_RSDREQ_MASK) >> RNG_STA_RSDREQ_SHIFT) - -/* - * IDLE (RO) - * - * Idle, the RNG is in the idle mode, and internal clocks are disabled, in this mode, access to the FIFO is allowed. Once the FIFO is empty, the RNGB fills the FIFO and then enters idle mode again. - */ -#define RNG_STA_IDLE_MASK (0x4U) -#define RNG_STA_IDLE_SHIFT (2U) -#define RNG_STA_IDLE_GET(x) (((uint32_t)(x) & RNG_STA_IDLE_MASK) >> RNG_STA_IDLE_SHIFT) - -/* - * BUSY (RO) - * - * when 1, means the RNG engine is busy for seeding or random number generation, self test and so on. - */ -#define RNG_STA_BUSY_MASK (0x2U) -#define RNG_STA_BUSY_SHIFT (1U) -#define RNG_STA_BUSY_GET(x) (((uint32_t)(x) & RNG_STA_BUSY_MASK) >> RNG_STA_BUSY_SHIFT) - -/* Bitfield definition for register: ERR */ -/* - * FUFE (RO) - * - * FIFO access error(underflow) - */ -#define RNG_ERR_FUFE_MASK (0x20U) -#define RNG_ERR_FUFE_SHIFT (5U) -#define RNG_ERR_FUFE_GET(x) (((uint32_t)(x) & RNG_ERR_FUFE_MASK) >> RNG_ERR_FUFE_SHIFT) - -/* - * SCKERR (RO) - * - * Self-test error - * Indicates that the RNG failed the most recent self test. This bit is sticky and can only be reset by a - * hardware reset or by writing 1 to the CMD[CE] - */ -#define RNG_ERR_SCKERR_MASK (0x8U) -#define RNG_ERR_SCKERR_SHIFT (3U) -#define RNG_ERR_SCKERR_GET(x) (((uint32_t)(x) & RNG_ERR_SCKERR_MASK) >> RNG_ERR_SCKERR_SHIFT) - -/* Bitfield definition for register: FO2B */ -/* - * FO2B (RO) - * - * SW read the FIFO output. - */ -#define RNG_FO2B_FO2B_MASK (0xFFFFFFFFUL) -#define RNG_FO2B_FO2B_SHIFT (0U) -#define RNG_FO2B_FO2B_GET(x) (((uint32_t)(x) & RNG_FO2B_FO2B_MASK) >> RNG_FO2B_FO2B_SHIFT) - -/* Bitfield definition for register array: R2SK */ -/* - * FO2S0 (RO) - * - * FIFO out to KMAN, will be SDP engine key. - */ -#define RNG_R2SK_FO2S0_MASK (0xFFFFFFFFUL) -#define RNG_R2SK_FO2S0_SHIFT (0U) -#define RNG_R2SK_FO2S0_GET(x) (((uint32_t)(x) & RNG_R2SK_FO2S0_MASK) >> RNG_R2SK_FO2S0_SHIFT) - - - -/* R2SK register group index macro definition */ -#define RNG_R2SK_FO2S0 (0UL) -#define RNG_R2SK_FO2S1 (1UL) -#define RNG_R2SK_FO2S2 (2UL) -#define RNG_R2SK_FO2S3 (3UL) -#define RNG_R2SK_FO2S4 (4UL) -#define RNG_R2SK_FO2S5 (5UL) -#define RNG_R2SK_FO2S6 (6UL) -#define RNG_R2SK_FO2S7 (7UL) - - -#endif /* HPM_RNG_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rtc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rtc_regs.h deleted file mode 100644 index d2325b94590..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_rtc_regs.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_RTC_H -#define HPM_RTC_H - -typedef struct { - __RW uint32_t SECOND; /* 0x0: Second counter */ - __R uint32_t SUBSEC; /* 0x4: Sub-second counter */ - __RW uint32_t SEC_SNAP; /* 0x8: Second counter snap shot */ - __RW uint32_t SUB_SNAP; /* 0xC: Sub-second counter snap shot */ - __RW uint32_t ALARM0; /* 0x10: RTC alarm0 */ - __RW uint32_t ALARM0_INC; /* 0x14: Alarm0 incremental */ - __RW uint32_t ALARM1; /* 0x18: RTC alarm1 */ - __RW uint32_t ALARM1_INC; /* 0x1C: Alarm1 incremental */ - __RW uint32_t ALARM_FLAG; /* 0x20: RTC alarm flag */ - __RW uint32_t ALARM_EN; /* 0x24: RTC alarm enable */ -} RTC_Type; - - -/* Bitfield definition for register: SECOND */ -/* - * SECOND (RW) - * - * second counter - */ -#define RTC_SECOND_SECOND_MASK (0xFFFFFFFFUL) -#define RTC_SECOND_SECOND_SHIFT (0U) -#define RTC_SECOND_SECOND_SET(x) (((uint32_t)(x) << RTC_SECOND_SECOND_SHIFT) & RTC_SECOND_SECOND_MASK) -#define RTC_SECOND_SECOND_GET(x) (((uint32_t)(x) & RTC_SECOND_SECOND_MASK) >> RTC_SECOND_SECOND_SHIFT) - -/* Bitfield definition for register: SUBSEC */ -/* - * SUBSEC (RO) - * - * sub second counter - */ -#define RTC_SUBSEC_SUBSEC_MASK (0xFFFFFFFFUL) -#define RTC_SUBSEC_SUBSEC_SHIFT (0U) -#define RTC_SUBSEC_SUBSEC_GET(x) (((uint32_t)(x) & RTC_SUBSEC_SUBSEC_MASK) >> RTC_SUBSEC_SUBSEC_SHIFT) - -/* Bitfield definition for register: SEC_SNAP */ -/* - * SEC_SNAP (RW) - * - * second snap shot, write to take snap shot - */ -#define RTC_SEC_SNAP_SEC_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SEC_SNAP_SEC_SNAP_SHIFT (0U) -#define RTC_SEC_SNAP_SEC_SNAP_SET(x) (((uint32_t)(x) << RTC_SEC_SNAP_SEC_SNAP_SHIFT) & RTC_SEC_SNAP_SEC_SNAP_MASK) -#define RTC_SEC_SNAP_SEC_SNAP_GET(x) (((uint32_t)(x) & RTC_SEC_SNAP_SEC_SNAP_MASK) >> RTC_SEC_SNAP_SEC_SNAP_SHIFT) - -/* Bitfield definition for register: SUB_SNAP */ -/* - * SUB_SNAP (RW) - * - * sub second snap shot, write to take snap shot - */ -#define RTC_SUB_SNAP_SUB_SNAP_MASK (0xFFFFFFFFUL) -#define RTC_SUB_SNAP_SUB_SNAP_SHIFT (0U) -#define RTC_SUB_SNAP_SUB_SNAP_SET(x) (((uint32_t)(x) << RTC_SUB_SNAP_SUB_SNAP_SHIFT) & RTC_SUB_SNAP_SUB_SNAP_MASK) -#define RTC_SUB_SNAP_SUB_SNAP_GET(x) (((uint32_t)(x) & RTC_SUB_SNAP_SUB_SNAP_MASK) >> RTC_SUB_SNAP_SUB_SNAP_SHIFT) - -/* Bitfield definition for register: ALARM0 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM0_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_ALARM_SHIFT (0U) -#define RTC_ALARM0_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM0_ALARM_SHIFT) & RTC_ALARM0_ALARM_MASK) -#define RTC_ALARM0_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM0_ALARM_MASK) >> RTC_ALARM0_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM0_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM0_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM0_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM0_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM0_INC_INCREASE_SHIFT) & RTC_ALARM0_INC_INCREASE_MASK) -#define RTC_ALARM0_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM0_INC_INCREASE_MASK) >> RTC_ALARM0_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM1 */ -/* - * ALARM (RW) - * - * Alarm time for second counter, on each alarm match, alarm increase ALARM0_INC - */ -#define RTC_ALARM1_ALARM_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_ALARM_SHIFT (0U) -#define RTC_ALARM1_ALARM_SET(x) (((uint32_t)(x) << RTC_ALARM1_ALARM_SHIFT) & RTC_ALARM1_ALARM_MASK) -#define RTC_ALARM1_ALARM_GET(x) (((uint32_t)(x) & RTC_ALARM1_ALARM_MASK) >> RTC_ALARM1_ALARM_SHIFT) - -/* Bitfield definition for register: ALARM1_INC */ -/* - * INCREASE (RW) - * - * adder when ARLAM0 happen, helps to create periodical alarm - */ -#define RTC_ALARM1_INC_INCREASE_MASK (0xFFFFFFFFUL) -#define RTC_ALARM1_INC_INCREASE_SHIFT (0U) -#define RTC_ALARM1_INC_INCREASE_SET(x) (((uint32_t)(x) << RTC_ALARM1_INC_INCREASE_SHIFT) & RTC_ALARM1_INC_INCREASE_MASK) -#define RTC_ALARM1_INC_INCREASE_GET(x) (((uint32_t)(x) & RTC_ALARM1_INC_INCREASE_MASK) >> RTC_ALARM1_INC_INCREASE_SHIFT) - -/* Bitfield definition for register: ALARM_FLAG */ -/* - * ALARM1 (RW) - * - * alarm1 happen - */ -#define RTC_ALARM_FLAG_ALARM1_MASK (0x2U) -#define RTC_ALARM_FLAG_ALARM1_SHIFT (1U) -#define RTC_ALARM_FLAG_ALARM1_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM1_SHIFT) & RTC_ALARM_FLAG_ALARM1_MASK) -#define RTC_ALARM_FLAG_ALARM1_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM1_MASK) >> RTC_ALARM_FLAG_ALARM1_SHIFT) - -/* - * ALARM0 (RW) - * - * alarm0 happen - */ -#define RTC_ALARM_FLAG_ALARM0_MASK (0x1U) -#define RTC_ALARM_FLAG_ALARM0_SHIFT (0U) -#define RTC_ALARM_FLAG_ALARM0_SET(x) (((uint32_t)(x) << RTC_ALARM_FLAG_ALARM0_SHIFT) & RTC_ALARM_FLAG_ALARM0_MASK) -#define RTC_ALARM_FLAG_ALARM0_GET(x) (((uint32_t)(x) & RTC_ALARM_FLAG_ALARM0_MASK) >> RTC_ALARM_FLAG_ALARM0_SHIFT) - -/* Bitfield definition for register: ALARM_EN */ -/* - * ENABLE1 (RW) - * - * alarm1 mask - * 0: alarm1 disabled - * 1: alarm1 enabled - */ -#define RTC_ALARM_EN_ENABLE1_MASK (0x2U) -#define RTC_ALARM_EN_ENABLE1_SHIFT (1U) -#define RTC_ALARM_EN_ENABLE1_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE1_SHIFT) & RTC_ALARM_EN_ENABLE1_MASK) -#define RTC_ALARM_EN_ENABLE1_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE1_MASK) >> RTC_ALARM_EN_ENABLE1_SHIFT) - -/* - * ENABLE0 (RW) - * - * alarm0 mask - * 0: alarm0 disabled - * 1: alarm0 enabled - */ -#define RTC_ALARM_EN_ENABLE0_MASK (0x1U) -#define RTC_ALARM_EN_ENABLE0_SHIFT (0U) -#define RTC_ALARM_EN_ENABLE0_SET(x) (((uint32_t)(x) << RTC_ALARM_EN_ENABLE0_SHIFT) & RTC_ALARM_EN_ENABLE0_MASK) -#define RTC_ALARM_EN_ENABLE0_GET(x) (((uint32_t)(x) & RTC_ALARM_EN_ENABLE0_MASK) >> RTC_ALARM_EN_ENABLE0_SHIFT) - - - - -#endif /* HPM_RTC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sdm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sdm_regs.h deleted file mode 100644 index 98009c8d178..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sdm_regs.h +++ /dev/null @@ -1,859 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDM_H -#define HPM_SDM_H - -typedef struct { - __RW uint32_t CTRL; /* 0x0: SDM control register */ - __RW uint32_t INT_EN; /* 0x4: Interrupt enable register. */ - __R uint32_t STATUS; /* 0x8: Status Registers */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - struct { - __RW uint32_t SDFIFOCTRL; /* 0x10: Data FIFO Path Control Register */ - __RW uint32_t SDCTRLP; /* 0x14: Data Path Control Primary Register */ - __RW uint32_t SDCTRLE; /* 0x18: Data Path Control Extra Register */ - __RW uint32_t SDST; /* 0x1C: Data Path Status */ - __R uint32_t SDATA; /* 0x20: Data */ - __R uint32_t SDFIFO; /* 0x24: FIFO Data */ - __R uint32_t SCAMP; /* 0x28: instant Amplitude Results */ - __RW uint32_t SCHTL; /* 0x2C: Amplitude Threshold for High Limit */ - __RW uint32_t SCHTLZ; /* 0x30: Amplitude Threshold for zero crossing */ - __RW uint32_t SCLLT; /* 0x34: Amplitude Threshold for low limit */ - __RW uint32_t SCCTRL; /* 0x38: Amplitude Path Control */ - __RW uint32_t SCST; /* 0x3C: Amplitude Path Status */ - __R uint8_t RESERVED0[16]; /* 0x40 - 0x4F: Reserved */ - } CH[4]; -} SDM_Type; - - -/* Bitfield definition for register: CTRL */ -/* - * SFTRST (RW) - * - * software reset the module if asserted to be1’b1. - */ -#define SDM_CTRL_SFTRST_MASK (0x80000000UL) -#define SDM_CTRL_SFTRST_SHIFT (31U) -#define SDM_CTRL_SFTRST_SET(x) (((uint32_t)(x) << SDM_CTRL_SFTRST_SHIFT) & SDM_CTRL_SFTRST_MASK) -#define SDM_CTRL_SFTRST_GET(x) (((uint32_t)(x) & SDM_CTRL_SFTRST_MASK) >> SDM_CTRL_SFTRST_SHIFT) - -/* - * CHMD (RW) - * - * Channel Rcv mode - * Bits[2:0] for Ch0. - * Bits[5:3] for Ch1 - * Bits[8:6] for Ch2 - * Bits[11:9] for Ch3 - * 3'b000: Capture at posedge of MCLK - * 3'b001: Capture at both posedge and negedge of MCLK - * 3'b010: Manchestor Mode - * 3'b011: Capture at negedge of MCLK - * 3'b100: Capture at every other posedge of MCLK - * 3'b101: Capture at every other negedge of MCLK - * Others: Undefined - */ -#define SDM_CTRL_CHMD_MASK (0x3FFC000UL) -#define SDM_CTRL_CHMD_SHIFT (14U) -#define SDM_CTRL_CHMD_SET(x) (((uint32_t)(x) << SDM_CTRL_CHMD_SHIFT) & SDM_CTRL_CHMD_MASK) -#define SDM_CTRL_CHMD_GET(x) (((uint32_t)(x) & SDM_CTRL_CHMD_MASK) >> SDM_CTRL_CHMD_SHIFT) - -/* - * SYNC_MCLK (RW) - * - * Asserted to double sync the mclk input pin before its usage inside the module - */ -#define SDM_CTRL_SYNC_MCLK_MASK (0x3C00U) -#define SDM_CTRL_SYNC_MCLK_SHIFT (10U) -#define SDM_CTRL_SYNC_MCLK_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MCLK_SHIFT) & SDM_CTRL_SYNC_MCLK_MASK) -#define SDM_CTRL_SYNC_MCLK_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MCLK_MASK) >> SDM_CTRL_SYNC_MCLK_SHIFT) - -/* - * SYNC_MDAT (RW) - * - * Asserted to double sync the mdat input pin before its usage inside the module - */ -#define SDM_CTRL_SYNC_MDAT_MASK (0x3C0U) -#define SDM_CTRL_SYNC_MDAT_SHIFT (6U) -#define SDM_CTRL_SYNC_MDAT_SET(x) (((uint32_t)(x) << SDM_CTRL_SYNC_MDAT_SHIFT) & SDM_CTRL_SYNC_MDAT_MASK) -#define SDM_CTRL_SYNC_MDAT_GET(x) (((uint32_t)(x) & SDM_CTRL_SYNC_MDAT_MASK) >> SDM_CTRL_SYNC_MDAT_SHIFT) - -/* - * CH_EN (RW) - * - * Channel Enable - */ -#define SDM_CTRL_CH_EN_MASK (0x3CU) -#define SDM_CTRL_CH_EN_SHIFT (2U) -#define SDM_CTRL_CH_EN_SET(x) (((uint32_t)(x) << SDM_CTRL_CH_EN_SHIFT) & SDM_CTRL_CH_EN_MASK) -#define SDM_CTRL_CH_EN_GET(x) (((uint32_t)(x) & SDM_CTRL_CH_EN_MASK) >> SDM_CTRL_CH_EN_SHIFT) - -/* - * IE (RW) - * - * Interrupt Enable - */ -#define SDM_CTRL_IE_MASK (0x2U) -#define SDM_CTRL_IE_SHIFT (1U) -#define SDM_CTRL_IE_SET(x) (((uint32_t)(x) << SDM_CTRL_IE_SHIFT) & SDM_CTRL_IE_MASK) -#define SDM_CTRL_IE_GET(x) (((uint32_t)(x) & SDM_CTRL_IE_MASK) >> SDM_CTRL_IE_SHIFT) - -/* Bitfield definition for register: INT_EN */ -/* - * CH3DRY (RW) - * - * Ch3 Data Ready interrupt enable. - */ -#define SDM_INT_EN_CH3DRY_MASK (0x80U) -#define SDM_INT_EN_CH3DRY_SHIFT (7U) -#define SDM_INT_EN_CH3DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3DRY_SHIFT) & SDM_INT_EN_CH3DRY_MASK) -#define SDM_INT_EN_CH3DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3DRY_MASK) >> SDM_INT_EN_CH3DRY_SHIFT) - -/* - * CH2DRY (RW) - * - * Ch2 Data Ready interrupt enable - */ -#define SDM_INT_EN_CH2DRY_MASK (0x40U) -#define SDM_INT_EN_CH2DRY_SHIFT (6U) -#define SDM_INT_EN_CH2DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2DRY_SHIFT) & SDM_INT_EN_CH2DRY_MASK) -#define SDM_INT_EN_CH2DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2DRY_MASK) >> SDM_INT_EN_CH2DRY_SHIFT) - -/* - * CH1DRY (RW) - * - * Ch1 Data Ready interrupt enable - */ -#define SDM_INT_EN_CH1DRY_MASK (0x20U) -#define SDM_INT_EN_CH1DRY_SHIFT (5U) -#define SDM_INT_EN_CH1DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1DRY_SHIFT) & SDM_INT_EN_CH1DRY_MASK) -#define SDM_INT_EN_CH1DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1DRY_MASK) >> SDM_INT_EN_CH1DRY_SHIFT) - -/* - * CH0DRY (RW) - * - * Ch0 Data Ready interrupt enable - */ -#define SDM_INT_EN_CH0DRY_MASK (0x10U) -#define SDM_INT_EN_CH0DRY_SHIFT (4U) -#define SDM_INT_EN_CH0DRY_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0DRY_SHIFT) & SDM_INT_EN_CH0DRY_MASK) -#define SDM_INT_EN_CH0DRY_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0DRY_MASK) >> SDM_INT_EN_CH0DRY_SHIFT) - -/* - * CH3ERR (RW) - * - * Ch3 Error interrupt enable. - */ -#define SDM_INT_EN_CH3ERR_MASK (0x8U) -#define SDM_INT_EN_CH3ERR_SHIFT (3U) -#define SDM_INT_EN_CH3ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH3ERR_SHIFT) & SDM_INT_EN_CH3ERR_MASK) -#define SDM_INT_EN_CH3ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH3ERR_MASK) >> SDM_INT_EN_CH3ERR_SHIFT) - -/* - * CH2ERR (RW) - * - * Ch2 Error interrupt enable - */ -#define SDM_INT_EN_CH2ERR_MASK (0x4U) -#define SDM_INT_EN_CH2ERR_SHIFT (2U) -#define SDM_INT_EN_CH2ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH2ERR_SHIFT) & SDM_INT_EN_CH2ERR_MASK) -#define SDM_INT_EN_CH2ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH2ERR_MASK) >> SDM_INT_EN_CH2ERR_SHIFT) - -/* - * CH1ERR (RW) - * - * Ch1 Error interrupt enable - */ -#define SDM_INT_EN_CH1ERR_MASK (0x2U) -#define SDM_INT_EN_CH1ERR_SHIFT (1U) -#define SDM_INT_EN_CH1ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH1ERR_SHIFT) & SDM_INT_EN_CH1ERR_MASK) -#define SDM_INT_EN_CH1ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH1ERR_MASK) >> SDM_INT_EN_CH1ERR_SHIFT) - -/* - * CH0ERR (RW) - * - * Ch0 Error interrupt enable - */ -#define SDM_INT_EN_CH0ERR_MASK (0x1U) -#define SDM_INT_EN_CH0ERR_SHIFT (0U) -#define SDM_INT_EN_CH0ERR_SET(x) (((uint32_t)(x) << SDM_INT_EN_CH0ERR_SHIFT) & SDM_INT_EN_CH0ERR_MASK) -#define SDM_INT_EN_CH0ERR_GET(x) (((uint32_t)(x) & SDM_INT_EN_CH0ERR_MASK) >> SDM_INT_EN_CH0ERR_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * CH3DRY (RO) - * - * Ch3 Data Ready. - * De-assert this bit by reading the data (or data fifo) registers. - */ -#define SDM_STATUS_CH3DRY_MASK (0x80U) -#define SDM_STATUS_CH3DRY_SHIFT (7U) -#define SDM_STATUS_CH3DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3DRY_MASK) >> SDM_STATUS_CH3DRY_SHIFT) - -/* - * CH2DRY (RO) - * - * Ch2 Data Ready - */ -#define SDM_STATUS_CH2DRY_MASK (0x40U) -#define SDM_STATUS_CH2DRY_SHIFT (6U) -#define SDM_STATUS_CH2DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2DRY_MASK) >> SDM_STATUS_CH2DRY_SHIFT) - -/* - * CH1DRY (RO) - * - * Ch1 Data Ready - */ -#define SDM_STATUS_CH1DRY_MASK (0x20U) -#define SDM_STATUS_CH1DRY_SHIFT (5U) -#define SDM_STATUS_CH1DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1DRY_MASK) >> SDM_STATUS_CH1DRY_SHIFT) - -/* - * CH0DRY (RO) - * - * Ch0 Data Ready - */ -#define SDM_STATUS_CH0DRY_MASK (0x10U) -#define SDM_STATUS_CH0DRY_SHIFT (4U) -#define SDM_STATUS_CH0DRY_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0DRY_MASK) >> SDM_STATUS_CH0DRY_SHIFT) - -/* - * CH3ERR (RO) - * - * Ch3 Error. - * ORed together by channel related error signals and corresponding error interrupt enable signals. - * De-assert this bit by write-1-clear the corresponding error status bits in the channel status registers. - */ -#define SDM_STATUS_CH3ERR_MASK (0x8U) -#define SDM_STATUS_CH3ERR_SHIFT (3U) -#define SDM_STATUS_CH3ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH3ERR_MASK) >> SDM_STATUS_CH3ERR_SHIFT) - -/* - * CH2ERR (RO) - * - * Ch2 Error - */ -#define SDM_STATUS_CH2ERR_MASK (0x4U) -#define SDM_STATUS_CH2ERR_SHIFT (2U) -#define SDM_STATUS_CH2ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH2ERR_MASK) >> SDM_STATUS_CH2ERR_SHIFT) - -/* - * CH1ERR (RO) - * - * Ch1 Error - */ -#define SDM_STATUS_CH1ERR_MASK (0x2U) -#define SDM_STATUS_CH1ERR_SHIFT (1U) -#define SDM_STATUS_CH1ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH1ERR_MASK) >> SDM_STATUS_CH1ERR_SHIFT) - -/* - * CH0ERR (RO) - * - * Ch0 Error - */ -#define SDM_STATUS_CH0ERR_MASK (0x1U) -#define SDM_STATUS_CH0ERR_SHIFT (0U) -#define SDM_STATUS_CH0ERR_GET(x) (((uint32_t)(x) & SDM_STATUS_CH0ERR_MASK) >> SDM_STATUS_CH0ERR_SHIFT) - -/* Bitfield definition for register of struct array CH: SDFIFOCTRL */ -/* - * GATE_SAMPLES (RW) - * - * The number-1-3 of input PDM bit samples to be gated when CIC_GATE_EN=1. Max 255. So the minimum gated samples is 4 samples when GATE_SAMPLES=0. - */ -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK (0xFF0000UL) -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT (16U) -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK) -#define SDM_CH_SDFIFOCTRL_GATE_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_GATE_SAMPLES_MASK) >> SDM_CH_SDFIFOCTRL_GATE_SAMPLES_SHIFT) - -/* - * THRSH (RW) - * - * FIFO threshold (0,..,16) (fillings > threshold, then gen int) - */ -#define SDM_CH_SDFIFOCTRL_THRSH_MASK (0x1F0U) -#define SDM_CH_SDFIFOCTRL_THRSH_SHIFT (4U) -#define SDM_CH_SDFIFOCTRL_THRSH_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_THRSH_SHIFT) & SDM_CH_SDFIFOCTRL_THRSH_MASK) -#define SDM_CH_SDFIFOCTRL_THRSH_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_THRSH_MASK) >> SDM_CH_SDFIFOCTRL_THRSH_SHIFT) - -/* - * D_RDY_INT_EN (RW) - * - * FIFO data ready interrupt enable - */ -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK (0x4U) -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT (2U) -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) -#define SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_MASK) >> SDM_CH_SDFIFOCTRL_D_RDY_INT_EN_SHIFT) - -/* Bitfield definition for register of struct array CH: SDCTRLP */ -/* - * MANCH_THR (RW) - * - * Manchester Decoding threshold. 3/4 of PERIOD_MCLK[7:0] - */ -#define SDM_CH_SDCTRLP_MANCH_THR_MASK (0xFE000000UL) -#define SDM_CH_SDCTRLP_MANCH_THR_SHIFT (25U) -#define SDM_CH_SDCTRLP_MANCH_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_MANCH_THR_SHIFT) & SDM_CH_SDCTRLP_MANCH_THR_MASK) -#define SDM_CH_SDCTRLP_MANCH_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_MANCH_THR_MASK) >> SDM_CH_SDCTRLP_MANCH_THR_SHIFT) - -/* - * WDOG_THR (RW) - * - * Watch dog threshold for channel failure of CLK halting - */ -#define SDM_CH_SDCTRLP_WDOG_THR_MASK (0x1FE0000UL) -#define SDM_CH_SDCTRLP_WDOG_THR_SHIFT (17U) -#define SDM_CH_SDCTRLP_WDOG_THR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WDOG_THR_SHIFT) & SDM_CH_SDCTRLP_WDOG_THR_MASK) -#define SDM_CH_SDCTRLP_WDOG_THR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WDOG_THR_MASK) >> SDM_CH_SDCTRLP_WDOG_THR_SHIFT) - -/* - * AF_IE (RW) - * - * Acknowledge feedback interrupt enable - */ -#define SDM_CH_SDCTRLP_AF_IE_MASK (0x10000UL) -#define SDM_CH_SDCTRLP_AF_IE_SHIFT (16U) -#define SDM_CH_SDCTRLP_AF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_AF_IE_SHIFT) & SDM_CH_SDCTRLP_AF_IE_MASK) -#define SDM_CH_SDCTRLP_AF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_AF_IE_MASK) >> SDM_CH_SDCTRLP_AF_IE_SHIFT) - -/* - * DFFOVIE (RW) - * - * Ch Data FIFO overflow interrupt enable - */ -#define SDM_CH_SDCTRLP_DFFOVIE_MASK (0x8000U) -#define SDM_CH_SDCTRLP_DFFOVIE_SHIFT (15U) -#define SDM_CH_SDCTRLP_DFFOVIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DFFOVIE_SHIFT) & SDM_CH_SDCTRLP_DFFOVIE_MASK) -#define SDM_CH_SDCTRLP_DFFOVIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DFFOVIE_MASK) >> SDM_CH_SDCTRLP_DFFOVIE_SHIFT) - -/* - * DSATIE (RW) - * - * Ch CIC Data Saturation Interrupt Enable - */ -#define SDM_CH_SDCTRLP_DSATIE_MASK (0x4000U) -#define SDM_CH_SDCTRLP_DSATIE_SHIFT (14U) -#define SDM_CH_SDCTRLP_DSATIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DSATIE_SHIFT) & SDM_CH_SDCTRLP_DSATIE_MASK) -#define SDM_CH_SDCTRLP_DSATIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DSATIE_MASK) >> SDM_CH_SDCTRLP_DSATIE_SHIFT) - -/* - * DRIE (RW) - * - * Ch Data Ready Interrupt Enable - */ -#define SDM_CH_SDCTRLP_DRIE_MASK (0x2000U) -#define SDM_CH_SDCTRLP_DRIE_SHIFT (13U) -#define SDM_CH_SDCTRLP_DRIE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DRIE_SHIFT) & SDM_CH_SDCTRLP_DRIE_MASK) -#define SDM_CH_SDCTRLP_DRIE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DRIE_MASK) >> SDM_CH_SDCTRLP_DRIE_SHIFT) - -/* - * SYNCSEL (RW) - * - * Select the PWM SYNC Source - */ -#define SDM_CH_SDCTRLP_SYNCSEL_MASK (0x1F80U) -#define SDM_CH_SDCTRLP_SYNCSEL_SHIFT (7U) -#define SDM_CH_SDCTRLP_SYNCSEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_SYNCSEL_SHIFT) & SDM_CH_SDCTRLP_SYNCSEL_MASK) -#define SDM_CH_SDCTRLP_SYNCSEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_SYNCSEL_MASK) >> SDM_CH_SDCTRLP_SYNCSEL_SHIFT) - -/* - * FFSYNCCLREN (RW) - * - * Auto clear FIFO when a new SDSYNC event is found. Only valid when WTSYNCEN=1 - */ -#define SDM_CH_SDCTRLP_FFSYNCCLREN_MASK (0x40U) -#define SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT (6U) -#define SDM_CH_SDCTRLP_FFSYNCCLREN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) -#define SDM_CH_SDCTRLP_FFSYNCCLREN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_FFSYNCCLREN_MASK) >> SDM_CH_SDCTRLP_FFSYNCCLREN_SHIFT) - -/* - * WTSYNACLR (RW) - * - * 1: Asserted to Auto clear WTSYNFLG when the SDFFINT is gen - * 0: WTSYNFLG should be cleared manually by WTSYNMCLR - */ -#define SDM_CH_SDCTRLP_WTSYNACLR_MASK (0x20U) -#define SDM_CH_SDCTRLP_WTSYNACLR_SHIFT (5U) -#define SDM_CH_SDCTRLP_WTSYNACLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) -#define SDM_CH_SDCTRLP_WTSYNACLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNACLR_MASK) >> SDM_CH_SDCTRLP_WTSYNACLR_SHIFT) - -/* - * WTSYNMCLR (RW) - * - * 1: Manually clear WTSYNFLG. Auto-clear. - */ -#define SDM_CH_SDCTRLP_WTSYNMCLR_MASK (0x10U) -#define SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT (4U) -#define SDM_CH_SDCTRLP_WTSYNMCLR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) -#define SDM_CH_SDCTRLP_WTSYNMCLR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNMCLR_MASK) >> SDM_CH_SDCTRLP_WTSYNMCLR_SHIFT) - -/* - * WTSYNCEN (RW) - * - * 1: Start to store data only after PWM SYNC event - * 0: Start to store data whenever enabled - */ -#define SDM_CH_SDCTRLP_WTSYNCEN_MASK (0x8U) -#define SDM_CH_SDCTRLP_WTSYNCEN_SHIFT (3U) -#define SDM_CH_SDCTRLP_WTSYNCEN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) -#define SDM_CH_SDCTRLP_WTSYNCEN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_WTSYNCEN_MASK) >> SDM_CH_SDCTRLP_WTSYNCEN_SHIFT) - -/* - * D32 (RW) - * - * 1:32 bit data - * 0:16 bit data - */ -#define SDM_CH_SDCTRLP_D32_MASK (0x4U) -#define SDM_CH_SDCTRLP_D32_SHIFT (2U) -#define SDM_CH_SDCTRLP_D32_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_D32_SHIFT) & SDM_CH_SDCTRLP_D32_MASK) -#define SDM_CH_SDCTRLP_D32_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_D32_MASK) >> SDM_CH_SDCTRLP_D32_SHIFT) - -/* - * DR_OPT (RW) - * - * 1: Use Data FIFO Ready as data ready when fifo fillings are greater than the threshold - * 0: Use Data Reg Ready as data ready - */ -#define SDM_CH_SDCTRLP_DR_OPT_MASK (0x2U) -#define SDM_CH_SDCTRLP_DR_OPT_SHIFT (1U) -#define SDM_CH_SDCTRLP_DR_OPT_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_DR_OPT_SHIFT) & SDM_CH_SDCTRLP_DR_OPT_MASK) -#define SDM_CH_SDCTRLP_DR_OPT_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_DR_OPT_MASK) >> SDM_CH_SDCTRLP_DR_OPT_SHIFT) - -/* - * EN (RW) - * - * Data Path Enable - */ -#define SDM_CH_SDCTRLP_EN_MASK (0x1U) -#define SDM_CH_SDCTRLP_EN_SHIFT (0U) -#define SDM_CH_SDCTRLP_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLP_EN_SHIFT) & SDM_CH_SDCTRLP_EN_MASK) -#define SDM_CH_SDCTRLP_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLP_EN_MASK) >> SDM_CH_SDCTRLP_EN_SHIFT) - -/* Bitfield definition for register of struct array CH: SDCTRLE */ -/* - * CIC_GATE_TYPE (RW) - * - * 1: the gate cycle is determined by SDFIFOCTRLn[GATE_SAMPLES]. - * 0: the gate cycle is determined by the CIC decimation counter, and the minimal gated off PDM bits are determined by SDFIFOCTRLn[GATE_SAMPLES], and at the same time, to keep alignment with normal PCM sampling time. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK (0x80000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT (31U) -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_TYPE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_TYPE_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_TYPE_SHIFT) - -/* - * CIC_GATE_POL (RW) - * - * 1: When mask signal is 1, pause the CIC stage at he rising edge of mask signal. - * 0: When mask signal is 0, pause the CIC stage at he falling edge of mask signal. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_POL_MASK (0x40000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT (30U) -#define SDM_CH_SDCTRLE_CIC_GATE_POL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_POL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_POL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_POL_SHIFT) - -/* - * CIC_GATE_SEL (RW) - * - * Select the mask signal for CIC gate signal. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK (0x3C000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT (26U) -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_SEL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_SEL_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_SEL_SHIFT) - -/* - * CIC_GATE_EN (RW) - * - * 1: the CIC stage can be paused by the mask input. - * 0: the CIC stage won't be paused by the mask input. - */ -#define SDM_CH_SDCTRLE_CIC_GATE_EN_MASK (0x2000000UL) -#define SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT (25U) -#define SDM_CH_SDCTRLE_CIC_GATE_EN_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK) -#define SDM_CH_SDCTRLE_CIC_GATE_EN_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_GATE_EN_MASK) >> SDM_CH_SDCTRLE_CIC_GATE_EN_SHIFT) - -/* - * TIMESTAMP_TYPE (RW) - * - * 1. Use the time (when the data is calculated out) - delta_time_of_filter_span as the timestamp. - * 0: Use the time when the data is calculated out. - */ -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK (0x400000UL) -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT (22U) -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK) -#define SDM_CH_SDCTRLE_TIMESTAMP_TYPE_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_TIMESTAMP_TYPE_MASK) >> SDM_CH_SDCTRLE_TIMESTAMP_TYPE_SHIFT) - -/* - * DFIFO_S_T (RW) - * - * 1: the output of SDFIFO is data and timestamp interleaved. First is data. - * 0: the output of SDFIFO is data only - */ -#define SDM_CH_SDCTRLE_DFIFO_S_T_MASK (0x200000UL) -#define SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT (21U) -#define SDM_CH_SDCTRLE_DFIFO_S_T_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK) -#define SDM_CH_SDCTRLE_DFIFO_S_T_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_DFIFO_S_T_MASK) >> SDM_CH_SDCTRLE_DFIFO_S_T_SHIFT) - -/* - * DATA_S_T (RW) - * - * "1: the read output of SData is data and timestamp interleaved. First is data. - * 0: the read output of SData is data only" - */ -#define SDM_CH_SDCTRLE_DATA_S_T_MASK (0x100000UL) -#define SDM_CH_SDCTRLE_DATA_S_T_SHIFT (20U) -#define SDM_CH_SDCTRLE_DATA_S_T_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_DATA_S_T_SHIFT) & SDM_CH_SDCTRLE_DATA_S_T_MASK) -#define SDM_CH_SDCTRLE_DATA_S_T_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_DATA_S_T_MASK) >> SDM_CH_SDCTRLE_DATA_S_T_SHIFT) - -/* - * SGD_ORDR (RW) - * - * CIC order - * 0: SYNC1 - * 1: SYNC2 - * 2: SYNC3 - * 3: FAST_SYNC - */ -#define SDM_CH_SDCTRLE_SGD_ORDR_MASK (0x60000UL) -#define SDM_CH_SDCTRLE_SGD_ORDR_SHIFT (17U) -#define SDM_CH_SDCTRLE_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) -#define SDM_CH_SDCTRLE_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_SGD_ORDR_MASK) >> SDM_CH_SDCTRLE_SGD_ORDR_SHIFT) - -/* - * PWMSYNC (RW) - * - * Asserted to double sync the PWM trigger signal - */ -#define SDM_CH_SDCTRLE_PWMSYNC_MASK (0x10000UL) -#define SDM_CH_SDCTRLE_PWMSYNC_SHIFT (16U) -#define SDM_CH_SDCTRLE_PWMSYNC_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_PWMSYNC_SHIFT) & SDM_CH_SDCTRLE_PWMSYNC_MASK) -#define SDM_CH_SDCTRLE_PWMSYNC_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_PWMSYNC_MASK) >> SDM_CH_SDCTRLE_PWMSYNC_SHIFT) - -/* - * CIC_SCL (RW) - * - * CIC shift control - */ -#define SDM_CH_SDCTRLE_CIC_SCL_MASK (0x7800U) -#define SDM_CH_SDCTRLE_CIC_SCL_SHIFT (11U) -#define SDM_CH_SDCTRLE_CIC_SCL_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_SCL_SHIFT) & SDM_CH_SDCTRLE_CIC_SCL_MASK) -#define SDM_CH_SDCTRLE_CIC_SCL_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_SCL_MASK) >> SDM_CH_SDCTRLE_CIC_SCL_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation ratio. 0 means div-by-256 - */ -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK (0x7F8U) -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT (3U) -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) -#define SDM_CH_SDCTRLE_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_CIC_DEC_RATIO_MASK) >> SDM_CH_SDCTRLE_CIC_DEC_RATIO_SHIFT) - -/* - * IGN_INI_SAMPLES (RW) - * - * NotZero: Don't store the first samples that are not accurate - * Zero: Store all samples - */ -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK (0x7U) -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT (0U) -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) -#define SDM_CH_SDCTRLE_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SDCTRLE_IGN_INI_SAMPLES_MASK) >> SDM_CH_SDCTRLE_IGN_INI_SAMPLES_SHIFT) - -/* Bitfield definition for register of struct array CH: SDST */ -/* - * PERIOD_MCLK (RO) - * - * maxim of mclk spacing in cycles, using edges of mclk signal. In manchester coding mode, it is just the period of MCLK. In other modes, it is almost the half period. - */ -#define SDM_CH_SDST_PERIOD_MCLK_MASK (0x7F800000UL) -#define SDM_CH_SDST_PERIOD_MCLK_SHIFT (23U) -#define SDM_CH_SDST_PERIOD_MCLK_GET(x) (((uint32_t)(x) & SDM_CH_SDST_PERIOD_MCLK_MASK) >> SDM_CH_SDST_PERIOD_MCLK_SHIFT) - -/* - * SDATA_D0_T1 (RO) - * - * 1: next readout is timestamp - * 0: next readout is data - */ -#define SDM_CH_SDST_SDATA_D0_T1_MASK (0x2000U) -#define SDM_CH_SDST_SDATA_D0_T1_SHIFT (13U) -#define SDM_CH_SDST_SDATA_D0_T1_GET(x) (((uint32_t)(x) & SDM_CH_SDST_SDATA_D0_T1_MASK) >> SDM_CH_SDST_SDATA_D0_T1_SHIFT) - -/* - * SDFIFO_D0_T1 (RO) - * - * 1: next readout is timestamp - * 0: next readout is data - */ -#define SDM_CH_SDST_SDFIFO_D0_T1_MASK (0x1000U) -#define SDM_CH_SDST_SDFIFO_D0_T1_SHIFT (12U) -#define SDM_CH_SDST_SDFIFO_D0_T1_GET(x) (((uint32_t)(x) & SDM_CH_SDST_SDFIFO_D0_T1_MASK) >> SDM_CH_SDST_SDFIFO_D0_T1_SHIFT) - -/* - * FIFO_DR (W1C) - * - * FIFO data ready - */ -#define SDM_CH_SDST_FIFO_DR_MASK (0x200U) -#define SDM_CH_SDST_FIFO_DR_SHIFT (9U) -#define SDM_CH_SDST_FIFO_DR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_FIFO_DR_SHIFT) & SDM_CH_SDST_FIFO_DR_MASK) -#define SDM_CH_SDST_FIFO_DR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FIFO_DR_MASK) >> SDM_CH_SDST_FIFO_DR_SHIFT) - -/* - * AF (W1C) - * - * Achnowledge flag - */ -#define SDM_CH_SDST_AF_MASK (0x100U) -#define SDM_CH_SDST_AF_SHIFT (8U) -#define SDM_CH_SDST_AF_SET(x) (((uint32_t)(x) << SDM_CH_SDST_AF_SHIFT) & SDM_CH_SDST_AF_MASK) -#define SDM_CH_SDST_AF_GET(x) (((uint32_t)(x) & SDM_CH_SDST_AF_MASK) >> SDM_CH_SDST_AF_SHIFT) - -/* - * DOV_ERR (W1C) - * - * Data FIFO Overflow Error. Error flag. - */ -#define SDM_CH_SDST_DOV_ERR_MASK (0x80U) -#define SDM_CH_SDST_DOV_ERR_SHIFT (7U) -#define SDM_CH_SDST_DOV_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DOV_ERR_SHIFT) & SDM_CH_SDST_DOV_ERR_MASK) -#define SDM_CH_SDST_DOV_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DOV_ERR_MASK) >> SDM_CH_SDST_DOV_ERR_SHIFT) - -/* - * DSAT_ERR (W1C) - * - * CIC out Data saturation err. Error flag. - */ -#define SDM_CH_SDST_DSAT_ERR_MASK (0x40U) -#define SDM_CH_SDST_DSAT_ERR_SHIFT (6U) -#define SDM_CH_SDST_DSAT_ERR_SET(x) (((uint32_t)(x) << SDM_CH_SDST_DSAT_ERR_SHIFT) & SDM_CH_SDST_DSAT_ERR_MASK) -#define SDM_CH_SDST_DSAT_ERR_GET(x) (((uint32_t)(x) & SDM_CH_SDST_DSAT_ERR_MASK) >> SDM_CH_SDST_DSAT_ERR_SHIFT) - -/* - * WTSYNFLG (RO) - * - * Wait-for-sync event found - */ -#define SDM_CH_SDST_WTSYNFLG_MASK (0x20U) -#define SDM_CH_SDST_WTSYNFLG_SHIFT (5U) -#define SDM_CH_SDST_WTSYNFLG_GET(x) (((uint32_t)(x) & SDM_CH_SDST_WTSYNFLG_MASK) >> SDM_CH_SDST_WTSYNFLG_SHIFT) - -/* - * FILL (RO) - * - * Data FIFO Fillings - */ -#define SDM_CH_SDST_FILL_MASK (0x1FU) -#define SDM_CH_SDST_FILL_SHIFT (0U) -#define SDM_CH_SDST_FILL_GET(x) (((uint32_t)(x) & SDM_CH_SDST_FILL_MASK) >> SDM_CH_SDST_FILL_SHIFT) - -/* Bitfield definition for register of struct array CH: SDATA */ -/* - * VAL (RO) - * - * Data - */ -#define SDM_CH_SDATA_VAL_MASK (0xFFFFFFFFUL) -#define SDM_CH_SDATA_VAL_SHIFT (0U) -#define SDM_CH_SDATA_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDATA_VAL_MASK) >> SDM_CH_SDATA_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SDFIFO */ -/* - * VAL (RO) - * - * FIFO Data - */ -#define SDM_CH_SDFIFO_VAL_MASK (0xFFFFFFFFUL) -#define SDM_CH_SDFIFO_VAL_SHIFT (0U) -#define SDM_CH_SDFIFO_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SDFIFO_VAL_MASK) >> SDM_CH_SDFIFO_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCAMP */ -/* - * VAL (RO) - * - * instant Amplitude Results - */ -#define SDM_CH_SCAMP_VAL_MASK (0xFFFFU) -#define SDM_CH_SCAMP_VAL_SHIFT (0U) -#define SDM_CH_SCAMP_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCAMP_VAL_MASK) >> SDM_CH_SCAMP_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCHTL */ -/* - * VAL (RW) - * - * Amplitude Threshold for High Limit - */ -#define SDM_CH_SCHTL_VAL_MASK (0xFFFFU) -#define SDM_CH_SCHTL_VAL_SHIFT (0U) -#define SDM_CH_SCHTL_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTL_VAL_SHIFT) & SDM_CH_SCHTL_VAL_MASK) -#define SDM_CH_SCHTL_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTL_VAL_MASK) >> SDM_CH_SCHTL_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCHTLZ */ -/* - * VAL (RW) - * - * Amplitude Threshold for zero crossing - */ -#define SDM_CH_SCHTLZ_VAL_MASK (0xFFFFU) -#define SDM_CH_SCHTLZ_VAL_SHIFT (0U) -#define SDM_CH_SCHTLZ_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCHTLZ_VAL_SHIFT) & SDM_CH_SCHTLZ_VAL_MASK) -#define SDM_CH_SCHTLZ_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCHTLZ_VAL_MASK) >> SDM_CH_SCHTLZ_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCLLT */ -/* - * VAL (RW) - * - * Amplitude Threshold for low limit - */ -#define SDM_CH_SCLLT_VAL_MASK (0xFFFFU) -#define SDM_CH_SCLLT_VAL_SHIFT (0U) -#define SDM_CH_SCLLT_VAL_SET(x) (((uint32_t)(x) << SDM_CH_SCLLT_VAL_SHIFT) & SDM_CH_SCLLT_VAL_MASK) -#define SDM_CH_SCLLT_VAL_GET(x) (((uint32_t)(x) & SDM_CH_SCLLT_VAL_MASK) >> SDM_CH_SCLLT_VAL_SHIFT) - -/* Bitfield definition for register of struct array CH: SCCTRL */ -/* - * HZ_EN (RW) - * - * Zero Crossing Enable - */ -#define SDM_CH_SCCTRL_HZ_EN_MASK (0x800000UL) -#define SDM_CH_SCCTRL_HZ_EN_SHIFT (23U) -#define SDM_CH_SCCTRL_HZ_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HZ_EN_SHIFT) & SDM_CH_SCCTRL_HZ_EN_MASK) -#define SDM_CH_SCCTRL_HZ_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HZ_EN_MASK) >> SDM_CH_SCCTRL_HZ_EN_SHIFT) - -/* - * MF_IE (RW) - * - * Module failure Interrupt enable - */ -#define SDM_CH_SCCTRL_MF_IE_MASK (0x400000UL) -#define SDM_CH_SCCTRL_MF_IE_SHIFT (22U) -#define SDM_CH_SCCTRL_MF_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_MF_IE_SHIFT) & SDM_CH_SCCTRL_MF_IE_MASK) -#define SDM_CH_SCCTRL_MF_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_MF_IE_MASK) >> SDM_CH_SCCTRL_MF_IE_SHIFT) - -/* - * HL_IE (RW) - * - * HLT Interrupt Enable - */ -#define SDM_CH_SCCTRL_HL_IE_MASK (0x200000UL) -#define SDM_CH_SCCTRL_HL_IE_SHIFT (21U) -#define SDM_CH_SCCTRL_HL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_HL_IE_SHIFT) & SDM_CH_SCCTRL_HL_IE_MASK) -#define SDM_CH_SCCTRL_HL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_HL_IE_MASK) >> SDM_CH_SCCTRL_HL_IE_SHIFT) - -/* - * LL_IE (RW) - * - * LLT interrupt Enable - */ -#define SDM_CH_SCCTRL_LL_IE_MASK (0x100000UL) -#define SDM_CH_SCCTRL_LL_IE_SHIFT (20U) -#define SDM_CH_SCCTRL_LL_IE_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_LL_IE_SHIFT) & SDM_CH_SCCTRL_LL_IE_MASK) -#define SDM_CH_SCCTRL_LL_IE_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_LL_IE_MASK) >> SDM_CH_SCCTRL_LL_IE_SHIFT) - -/* - * SGD_ORDR (RW) - * - * CIC order - * 0: SYNC1 - * 1: SYNC2 - * 2: SYNC3 - * 3: FAST_SYNC - */ -#define SDM_CH_SCCTRL_SGD_ORDR_MASK (0xC0000UL) -#define SDM_CH_SCCTRL_SGD_ORDR_SHIFT (18U) -#define SDM_CH_SCCTRL_SGD_ORDR_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_SGD_ORDR_SHIFT) & SDM_CH_SCCTRL_SGD_ORDR_MASK) -#define SDM_CH_SCCTRL_SGD_ORDR_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_SGD_ORDR_MASK) >> SDM_CH_SCCTRL_SGD_ORDR_SHIFT) - -/* - * CIC_DEC_RATIO (RW) - * - * CIC decimation ratio. 0 means div-by-32 - */ -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK (0x1F0U) -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT (4U) -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) -#define SDM_CH_SCCTRL_CIC_DEC_RATIO_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_CIC_DEC_RATIO_MASK) >> SDM_CH_SCCTRL_CIC_DEC_RATIO_SHIFT) - -/* - * IGN_INI_SAMPLES (RW) - * - * NotZero: Ignore the first samples that are not accurate - * Zero: Use all samples - */ -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK (0xEU) -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT (1U) -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) -#define SDM_CH_SCCTRL_IGN_INI_SAMPLES_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_IGN_INI_SAMPLES_MASK) >> SDM_CH_SCCTRL_IGN_INI_SAMPLES_SHIFT) - -/* - * EN (RW) - * - * Amplitude Path Enable - */ -#define SDM_CH_SCCTRL_EN_MASK (0x1U) -#define SDM_CH_SCCTRL_EN_SHIFT (0U) -#define SDM_CH_SCCTRL_EN_SET(x) (((uint32_t)(x) << SDM_CH_SCCTRL_EN_SHIFT) & SDM_CH_SCCTRL_EN_MASK) -#define SDM_CH_SCCTRL_EN_GET(x) (((uint32_t)(x) & SDM_CH_SCCTRL_EN_MASK) >> SDM_CH_SCCTRL_EN_SHIFT) - -/* Bitfield definition for register of struct array CH: SCST */ -/* - * HZ (W1C) - * - * Amplitude rising above HZ event found. - */ -#define SDM_CH_SCST_HZ_MASK (0x8U) -#define SDM_CH_SCST_HZ_SHIFT (3U) -#define SDM_CH_SCST_HZ_SET(x) (((uint32_t)(x) << SDM_CH_SCST_HZ_SHIFT) & SDM_CH_SCST_HZ_MASK) -#define SDM_CH_SCST_HZ_GET(x) (((uint32_t)(x) & SDM_CH_SCST_HZ_MASK) >> SDM_CH_SCST_HZ_SHIFT) - -/* - * MF (W1C) - * - * power modulator Failure found. MCLK not found. Error flag. - */ -#define SDM_CH_SCST_MF_MASK (0x4U) -#define SDM_CH_SCST_MF_SHIFT (2U) -#define SDM_CH_SCST_MF_SET(x) (((uint32_t)(x) << SDM_CH_SCST_MF_SHIFT) & SDM_CH_SCST_MF_MASK) -#define SDM_CH_SCST_MF_GET(x) (((uint32_t)(x) & SDM_CH_SCST_MF_MASK) >> SDM_CH_SCST_MF_SHIFT) - -/* - * CMPH (W1C) - * - * HLT out of range. Error flag. - */ -#define SDM_CH_SCST_CMPH_MASK (0x2U) -#define SDM_CH_SCST_CMPH_SHIFT (1U) -#define SDM_CH_SCST_CMPH_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPH_SHIFT) & SDM_CH_SCST_CMPH_MASK) -#define SDM_CH_SCST_CMPH_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPH_MASK) >> SDM_CH_SCST_CMPH_SHIFT) - -/* - * CMPL (W1C) - * - * LLT out of range. Error flag. - */ -#define SDM_CH_SCST_CMPL_MASK (0x1U) -#define SDM_CH_SCST_CMPL_SHIFT (0U) -#define SDM_CH_SCST_CMPL_SET(x) (((uint32_t)(x) << SDM_CH_SCST_CMPL_SHIFT) & SDM_CH_SCST_CMPL_MASK) -#define SDM_CH_SCST_CMPL_GET(x) (((uint32_t)(x) & SDM_CH_SCST_CMPL_MASK) >> SDM_CH_SCST_CMPL_SHIFT) - - - -/* CH register group index macro definition */ -#define SDM_CH_0 (0UL) -#define SDM_CH_1 (1UL) -#define SDM_CH_2 (2UL) -#define SDM_CH_3 (3UL) - - -#endif /* HPM_SDM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sdp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sdp_regs.h deleted file mode 100644 index 7562ad654a5..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sdp_regs.h +++ /dev/null @@ -1,661 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SDP_H -#define HPM_SDP_H - -typedef struct { - __RW uint32_t SDPCR; /* 0x0: SDP control register */ - __RW uint32_t MODCTRL; /* 0x4: Mod control register. */ - __RW uint32_t PKTCNT; /* 0x8: packet counter registers. */ - __RW uint32_t STA; /* 0xC: Status Registers */ - __RW uint32_t KEYADDR; /* 0x10: Key Address */ - __RW uint32_t KEYDAT; /* 0x14: Key Data */ - __RW uint32_t CIPHIV[4]; /* 0x18 - 0x24: Cipher Initializtion Vector 0 */ - __RW uint32_t HASWRD[8]; /* 0x28 - 0x44: Hash Data Word 0 */ - __RW uint32_t CMDPTR; /* 0x48: Command Pointer */ - __RW uint32_t NPKTPTR; /* 0x4C: Next Packet Address Pointer */ - __RW uint32_t PKTCTL; /* 0x50: Packet Control Registers */ - __RW uint32_t PKTSRC; /* 0x54: Packet Memory Source Address */ - __RW uint32_t PKTDST; /* 0x58: Packet Memory Destination Address */ - __RW uint32_t PKTBUF; /* 0x5C: Packet buffer size. */ -} SDP_Type; - - -/* Bitfield definition for register: SDPCR */ -/* - * SFTRST (RW) - * - * soft reset. - * Write 1 then 0, to reset the SDP block. - */ -#define SDP_SDPCR_SFTRST_MASK (0x80000000UL) -#define SDP_SDPCR_SFTRST_SHIFT (31U) -#define SDP_SDPCR_SFTRST_SET(x) (((uint32_t)(x) << SDP_SDPCR_SFTRST_SHIFT) & SDP_SDPCR_SFTRST_MASK) -#define SDP_SDPCR_SFTRST_GET(x) (((uint32_t)(x) & SDP_SDPCR_SFTRST_MASK) >> SDP_SDPCR_SFTRST_SHIFT) - -/* - * CLKGAT (RW) - * - * Clock Gate for the SDP main logic. - * Write to 1 will clock gate for most logic of the SDP block, dynamic power saving when not use SDP block. - */ -#define SDP_SDPCR_CLKGAT_MASK (0x40000000UL) -#define SDP_SDPCR_CLKGAT_SHIFT (30U) -#define SDP_SDPCR_CLKGAT_SET(x) (((uint32_t)(x) << SDP_SDPCR_CLKGAT_SHIFT) & SDP_SDPCR_CLKGAT_MASK) -#define SDP_SDPCR_CLKGAT_GET(x) (((uint32_t)(x) & SDP_SDPCR_CLKGAT_MASK) >> SDP_SDPCR_CLKGAT_SHIFT) - -/* - * CIPDIS (RO) - * - * Cipher Disable, read the info, whether the CIPHER features is besing disable in this chip or not. - * 1, Cipher is disabled in this chip. - * 0, Cipher is enabled in this chip. - */ -#define SDP_SDPCR_CIPDIS_MASK (0x20000000UL) -#define SDP_SDPCR_CIPDIS_SHIFT (29U) -#define SDP_SDPCR_CIPDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPDIS_MASK) >> SDP_SDPCR_CIPDIS_SHIFT) - -/* - * HASDIS (RO) - * - * HASH Disable, read the info, whether the HASH features is besing disable in this chip or not. - * 1, HASH is disabled in this chip. - * 0, HASH is enabled in this chip. - */ -#define SDP_SDPCR_HASDIS_MASK (0x10000000UL) -#define SDP_SDPCR_HASDIS_SHIFT (28U) -#define SDP_SDPCR_HASDIS_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASDIS_MASK) >> SDP_SDPCR_HASDIS_SHIFT) - -/* - * CIPHEN (RW) - * - * Cipher Enablement, controlled by SW. - * 1, Cipher is Enabled. - * 0, Cipher is Disabled. - */ -#define SDP_SDPCR_CIPHEN_MASK (0x800000UL) -#define SDP_SDPCR_CIPHEN_SHIFT (23U) -#define SDP_SDPCR_CIPHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CIPHEN_SHIFT) & SDP_SDPCR_CIPHEN_MASK) -#define SDP_SDPCR_CIPHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CIPHEN_MASK) >> SDP_SDPCR_CIPHEN_SHIFT) - -/* - * HASHEN (RW) - * - * HASH Enablement, controlled by SW. - * 1, HASH is Enabled. - * 0, HASH is Disabled. - */ -#define SDP_SDPCR_HASHEN_MASK (0x400000UL) -#define SDP_SDPCR_HASHEN_SHIFT (22U) -#define SDP_SDPCR_HASHEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_HASHEN_SHIFT) & SDP_SDPCR_HASHEN_MASK) -#define SDP_SDPCR_HASHEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_HASHEN_MASK) >> SDP_SDPCR_HASHEN_SHIFT) - -/* - * MCPEN (RW) - * - * Memory Copy Enablement, controlled by SW. - * 1, Memory copy is Enabled. - * 0, Memory copy is Disabled. - */ -#define SDP_SDPCR_MCPEN_MASK (0x200000UL) -#define SDP_SDPCR_MCPEN_SHIFT (21U) -#define SDP_SDPCR_MCPEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_MCPEN_SHIFT) & SDP_SDPCR_MCPEN_MASK) -#define SDP_SDPCR_MCPEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_MCPEN_MASK) >> SDP_SDPCR_MCPEN_SHIFT) - -/* - * CONFEN (RW) - * - * Constant Fill to memory, controlled by SW. - * 1, Constant fill is Enabled. - * 0, Constant fill is Disabled. - */ -#define SDP_SDPCR_CONFEN_MASK (0x100000UL) -#define SDP_SDPCR_CONFEN_SHIFT (20U) -#define SDP_SDPCR_CONFEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_CONFEN_SHIFT) & SDP_SDPCR_CONFEN_MASK) -#define SDP_SDPCR_CONFEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_CONFEN_MASK) >> SDP_SDPCR_CONFEN_SHIFT) - -/* - * DCRPDI (RW) - * - * Decryption Disable bit, Write to 1 to disable the decryption. - */ -#define SDP_SDPCR_DCRPDI_MASK (0x80000UL) -#define SDP_SDPCR_DCRPDI_SHIFT (19U) -#define SDP_SDPCR_DCRPDI_SET(x) (((uint32_t)(x) << SDP_SDPCR_DCRPDI_SHIFT) & SDP_SDPCR_DCRPDI_MASK) -#define SDP_SDPCR_DCRPDI_GET(x) (((uint32_t)(x) & SDP_SDPCR_DCRPDI_MASK) >> SDP_SDPCR_DCRPDI_SHIFT) - -/* - * TSTPKT0IRQ (RW) - * - * Test purpose for interrupt when Packet counter reachs "0", but CHAIN=1 in the current packet. - */ -#define SDP_SDPCR_TSTPKT0IRQ_MASK (0x20000UL) -#define SDP_SDPCR_TSTPKT0IRQ_SHIFT (17U) -#define SDP_SDPCR_TSTPKT0IRQ_SET(x) (((uint32_t)(x) << SDP_SDPCR_TSTPKT0IRQ_SHIFT) & SDP_SDPCR_TSTPKT0IRQ_MASK) -#define SDP_SDPCR_TSTPKT0IRQ_GET(x) (((uint32_t)(x) & SDP_SDPCR_TSTPKT0IRQ_MASK) >> SDP_SDPCR_TSTPKT0IRQ_SHIFT) - -/* - * RDSCEN (RW) - * - * when set to "1", the 1st data packet descriptor loacted in the register(CMDPTR, NPKTPTR, ...) - * when set to "0", the 1st data packet descriptor loacted in the memeory(pointed by CMDPTR) - */ -#define SDP_SDPCR_RDSCEN_MASK (0x100U) -#define SDP_SDPCR_RDSCEN_SHIFT (8U) -#define SDP_SDPCR_RDSCEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_RDSCEN_SHIFT) & SDP_SDPCR_RDSCEN_MASK) -#define SDP_SDPCR_RDSCEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_RDSCEN_MASK) >> SDP_SDPCR_RDSCEN_SHIFT) - -/* - * INTEN (RW) - * - * Interrupt Enablement, controlled by SW. - * 1, SDP interrupt is enabled. - * 0, SDP interrupt is disabled. - */ -#define SDP_SDPCR_INTEN_MASK (0x1U) -#define SDP_SDPCR_INTEN_SHIFT (0U) -#define SDP_SDPCR_INTEN_SET(x) (((uint32_t)(x) << SDP_SDPCR_INTEN_SHIFT) & SDP_SDPCR_INTEN_MASK) -#define SDP_SDPCR_INTEN_GET(x) (((uint32_t)(x) & SDP_SDPCR_INTEN_MASK) >> SDP_SDPCR_INTEN_SHIFT) - -/* Bitfield definition for register: MODCTRL */ -/* - * AESALG (RW) - * - * AES algorithem selection. - * 0x0 = AES 128; - * 0x1 = AES 256; - * 0x8 = SM4； - * Others, reserved. - */ -#define SDP_MODCTRL_AESALG_MASK (0xF0000000UL) -#define SDP_MODCTRL_AESALG_SHIFT (28U) -#define SDP_MODCTRL_AESALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESALG_SHIFT) & SDP_MODCTRL_AESALG_MASK) -#define SDP_MODCTRL_AESALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESALG_MASK) >> SDP_MODCTRL_AESALG_SHIFT) - -/* - * AESMOD (RW) - * - * AES mode selection. - * 0x0 = ECB; - * 0x1 = CBC; - * Others, reserved. - */ -#define SDP_MODCTRL_AESMOD_MASK (0xF000000UL) -#define SDP_MODCTRL_AESMOD_SHIFT (24U) -#define SDP_MODCTRL_AESMOD_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESMOD_SHIFT) & SDP_MODCTRL_AESMOD_MASK) -#define SDP_MODCTRL_AESMOD_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESMOD_MASK) >> SDP_MODCTRL_AESMOD_SHIFT) - -/* - * AESKS (RW) - * - * AES Key Selection. - * These regisgers are being used to select the AES key that stored in the 16x128 key ram of the SDP, or select the key from the OTP. Detail as following: - * 0x00: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 bit from this address and 128 bit key from next address as 256 bit AES key. - * 0x01: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * .... - * 0x0E: key from the 16x128, this is the key read address, valid for AES128; AES256 will use 128 from this add and 128 from next add for the AES key. - * 0x0F: key from the 16x128, this is the key read address, valid for AES128, not valid for AES286. - * 0x20: kman_sk0[127:0] from the key manager for AES128; AES256 will use kman_sk0[255:0] as AES key. - * 0x21: kman_sk0[255:128] from the key manager for AES128; not valid for AES256. - * 0x22: kman_sk1[127:0] from the key manager for AES128; AES256 will use kman_sk1[255:0] as AES key. - * 0x23: kman_sk1[255:128] from the key manager for AES128; not valid for AES256. - * 0x24: kman_sk2[127:0] from the key manager for AES128; AES256 will use kman_sk2[255:0] as AES key. - * 0x25: kman_sk2[255:128] from the key manager for AES128; not valid for AES256. - * 0x26: kman_sk3[127:0] from the key manager for AES128; AES256 will use kman_sk3[255:0] as AES key. - * 0x27: kman_sk3[255:128] from the key manager for AES128; not valid for AES256. - * 0x30: exip0_key[127:0] from OTP for AES128; AES256 will use exip0_key[255:0] as AES key. - * 0x31: exip0_key[255:128] from OTP for AES128; not valid for AES256. - * 0x32: exip1_key[127:0] from OTP for AES128; AES256 will use exip1_key[255:0] as AES key. - * 0x33: exip1_key[255:128] from OTP for AES128; not valid for AES256. - * Other values, reserved. - */ -#define SDP_MODCTRL_AESKS_MASK (0xFC0000UL) -#define SDP_MODCTRL_AESKS_SHIFT (18U) -#define SDP_MODCTRL_AESKS_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESKS_SHIFT) & SDP_MODCTRL_AESKS_MASK) -#define SDP_MODCTRL_AESKS_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESKS_MASK) >> SDP_MODCTRL_AESKS_SHIFT) - -/* - * AESDIR (RW) - * - * AES direction - * 1x1, AES Decryption - * 1x0, AES Encryption. - */ -#define SDP_MODCTRL_AESDIR_MASK (0x10000UL) -#define SDP_MODCTRL_AESDIR_SHIFT (16U) -#define SDP_MODCTRL_AESDIR_SET(x) (((uint32_t)(x) << SDP_MODCTRL_AESDIR_SHIFT) & SDP_MODCTRL_AESDIR_MASK) -#define SDP_MODCTRL_AESDIR_GET(x) (((uint32_t)(x) & SDP_MODCTRL_AESDIR_MASK) >> SDP_MODCTRL_AESDIR_SHIFT) - -/* - * HASALG (RW) - * - * HASH Algorithem selection. - * 0x0 SHA1 — - * 0x1 CRC32 — - * 0x2 SHA256 — - */ -#define SDP_MODCTRL_HASALG_MASK (0xF000U) -#define SDP_MODCTRL_HASALG_SHIFT (12U) -#define SDP_MODCTRL_HASALG_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASALG_SHIFT) & SDP_MODCTRL_HASALG_MASK) -#define SDP_MODCTRL_HASALG_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASALG_MASK) >> SDP_MODCTRL_HASALG_SHIFT) - -/* - * HASCHK (RW) - * - * HASH Check Enable Bit. - * 1x1, HASH check need, hash result will compare with the HASHRSLT 0-7 registers; - * 1x0, HASH check is not enabled, HASHRSLT0-7 store the HASH result. - * For SHA1, will use HASHRSLT0-3 words, and HASH 256 will use HASH0-7 words. - */ -#define SDP_MODCTRL_HASCHK_MASK (0x400U) -#define SDP_MODCTRL_HASCHK_SHIFT (10U) -#define SDP_MODCTRL_HASCHK_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASCHK_SHIFT) & SDP_MODCTRL_HASCHK_MASK) -#define SDP_MODCTRL_HASCHK_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASCHK_MASK) >> SDP_MODCTRL_HASCHK_SHIFT) - -/* - * HASOUT (RW) - * - * When hashing is enabled, this bit controls the input or output data of the AES engine is hashed. - * 0 INPUT HASH - * 1 OUTPUT HASH - */ -#define SDP_MODCTRL_HASOUT_MASK (0x200U) -#define SDP_MODCTRL_HASOUT_SHIFT (9U) -#define SDP_MODCTRL_HASOUT_SET(x) (((uint32_t)(x) << SDP_MODCTRL_HASOUT_SHIFT) & SDP_MODCTRL_HASOUT_MASK) -#define SDP_MODCTRL_HASOUT_GET(x) (((uint32_t)(x) & SDP_MODCTRL_HASOUT_MASK) >> SDP_MODCTRL_HASOUT_SHIFT) - -/* - * DINSWP (RW) - * - * Decide whether the SDP byteswaps the input data (big-endian data); - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DINSWP_MASK (0x30U) -#define SDP_MODCTRL_DINSWP_SHIFT (4U) -#define SDP_MODCTRL_DINSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DINSWP_SHIFT) & SDP_MODCTRL_DINSWP_MASK) -#define SDP_MODCTRL_DINSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DINSWP_MASK) >> SDP_MODCTRL_DINSWP_SHIFT) - -/* - * DOUTSWP (RW) - * - * Decide whether the SDP byteswaps the output data (big-endian data); When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_DOUTSWP_MASK (0xCU) -#define SDP_MODCTRL_DOUTSWP_SHIFT (2U) -#define SDP_MODCTRL_DOUTSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_DOUTSWP_SHIFT) & SDP_MODCTRL_DOUTSWP_MASK) -#define SDP_MODCTRL_DOUTSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_DOUTSWP_MASK) >> SDP_MODCTRL_DOUTSWP_SHIFT) - -/* - * KEYSWP (RW) - * - * Decide whether the SDP byteswaps the Key (big-endian data). - * When all bits are set, the data is assumed to be in the big-endian format - */ -#define SDP_MODCTRL_KEYSWP_MASK (0x3U) -#define SDP_MODCTRL_KEYSWP_SHIFT (0U) -#define SDP_MODCTRL_KEYSWP_SET(x) (((uint32_t)(x) << SDP_MODCTRL_KEYSWP_SHIFT) & SDP_MODCTRL_KEYSWP_MASK) -#define SDP_MODCTRL_KEYSWP_GET(x) (((uint32_t)(x) & SDP_MODCTRL_KEYSWP_MASK) >> SDP_MODCTRL_KEYSWP_SHIFT) - -/* Bitfield definition for register: PKTCNT */ -/* - * CNTVAL (RO) - * - * This read-only field shows the current (instantaneous) value of the packet counter - */ -#define SDP_PKTCNT_CNTVAL_MASK (0xFF0000UL) -#define SDP_PKTCNT_CNTVAL_SHIFT (16U) -#define SDP_PKTCNT_CNTVAL_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTVAL_MASK) >> SDP_PKTCNT_CNTVAL_SHIFT) - -/* - * CNTINCR (RW) - * - * The value written to this field is added to the spacket count. - */ -#define SDP_PKTCNT_CNTINCR_MASK (0xFFU) -#define SDP_PKTCNT_CNTINCR_SHIFT (0U) -#define SDP_PKTCNT_CNTINCR_SET(x) (((uint32_t)(x) << SDP_PKTCNT_CNTINCR_SHIFT) & SDP_PKTCNT_CNTINCR_MASK) -#define SDP_PKTCNT_CNTINCR_GET(x) (((uint32_t)(x) & SDP_PKTCNT_CNTINCR_MASK) >> SDP_PKTCNT_CNTINCR_SHIFT) - -/* Bitfield definition for register: STA */ -/* - * TAG (RO) - * - * packet tag. - */ -#define SDP_STA_TAG_MASK (0xFF000000UL) -#define SDP_STA_TAG_SHIFT (24U) -#define SDP_STA_TAG_GET(x) (((uint32_t)(x) & SDP_STA_TAG_MASK) >> SDP_STA_TAG_SHIFT) - -/* - * IRQ (W1C) - * - * interrupt Request, requested when error happen, or when packet processing done, packet counter reach to zero. - */ -#define SDP_STA_IRQ_MASK (0x800000UL) -#define SDP_STA_IRQ_SHIFT (23U) -#define SDP_STA_IRQ_SET(x) (((uint32_t)(x) << SDP_STA_IRQ_SHIFT) & SDP_STA_IRQ_MASK) -#define SDP_STA_IRQ_GET(x) (((uint32_t)(x) & SDP_STA_IRQ_MASK) >> SDP_STA_IRQ_SHIFT) - -/* - * CHN1PKT0 (W1C) - * - * the chain buffer "chain" bit is "1", while packet counter is "0", now, waiting for new buffer data. - */ -#define SDP_STA_CHN1PKT0_MASK (0x100000UL) -#define SDP_STA_CHN1PKT0_SHIFT (20U) -#define SDP_STA_CHN1PKT0_SET(x) (((uint32_t)(x) << SDP_STA_CHN1PKT0_SHIFT) & SDP_STA_CHN1PKT0_MASK) -#define SDP_STA_CHN1PKT0_GET(x) (((uint32_t)(x) & SDP_STA_CHN1PKT0_MASK) >> SDP_STA_CHN1PKT0_SHIFT) - -/* - * AESBSY (RO) - * - * AES Busy - */ -#define SDP_STA_AESBSY_MASK (0x80000UL) -#define SDP_STA_AESBSY_SHIFT (19U) -#define SDP_STA_AESBSY_GET(x) (((uint32_t)(x) & SDP_STA_AESBSY_MASK) >> SDP_STA_AESBSY_SHIFT) - -/* - * HASBSY (RO) - * - * Hashing Busy - */ -#define SDP_STA_HASBSY_MASK (0x40000UL) -#define SDP_STA_HASBSY_SHIFT (18U) -#define SDP_STA_HASBSY_GET(x) (((uint32_t)(x) & SDP_STA_HASBSY_MASK) >> SDP_STA_HASBSY_SHIFT) - -/* - * PKTCNT0 (W1C) - * - * Packet Counter registers reachs to ZERO now. - */ -#define SDP_STA_PKTCNT0_MASK (0x20000UL) -#define SDP_STA_PKTCNT0_SHIFT (17U) -#define SDP_STA_PKTCNT0_SET(x) (((uint32_t)(x) << SDP_STA_PKTCNT0_SHIFT) & SDP_STA_PKTCNT0_MASK) -#define SDP_STA_PKTCNT0_GET(x) (((uint32_t)(x) & SDP_STA_PKTCNT0_MASK) >> SDP_STA_PKTCNT0_SHIFT) - -/* - * PKTDON (W1C) - * - * Packet processing done, will trigger this itnerrrupt when the "PKTINT" bit set in the packet control word. - */ -#define SDP_STA_PKTDON_MASK (0x10000UL) -#define SDP_STA_PKTDON_SHIFT (16U) -#define SDP_STA_PKTDON_SET(x) (((uint32_t)(x) << SDP_STA_PKTDON_SHIFT) & SDP_STA_PKTDON_MASK) -#define SDP_STA_PKTDON_GET(x) (((uint32_t)(x) & SDP_STA_PKTDON_MASK) >> SDP_STA_PKTDON_SHIFT) - -/* - * ERRSET (W1C) - * - * Working mode setup error. - */ -#define SDP_STA_ERRSET_MASK (0x20U) -#define SDP_STA_ERRSET_SHIFT (5U) -#define SDP_STA_ERRSET_SET(x) (((uint32_t)(x) << SDP_STA_ERRSET_SHIFT) & SDP_STA_ERRSET_MASK) -#define SDP_STA_ERRSET_GET(x) (((uint32_t)(x) & SDP_STA_ERRSET_MASK) >> SDP_STA_ERRSET_SHIFT) - -/* - * ERRPKT (W1C) - * - * Packet head access error, or status update error. - */ -#define SDP_STA_ERRPKT_MASK (0x10U) -#define SDP_STA_ERRPKT_SHIFT (4U) -#define SDP_STA_ERRPKT_SET(x) (((uint32_t)(x) << SDP_STA_ERRPKT_SHIFT) & SDP_STA_ERRPKT_MASK) -#define SDP_STA_ERRPKT_GET(x) (((uint32_t)(x) & SDP_STA_ERRPKT_MASK) >> SDP_STA_ERRPKT_SHIFT) - -/* - * ERRSRC (W1C) - * - * Source Buffer Access Error - */ -#define SDP_STA_ERRSRC_MASK (0x8U) -#define SDP_STA_ERRSRC_SHIFT (3U) -#define SDP_STA_ERRSRC_SET(x) (((uint32_t)(x) << SDP_STA_ERRSRC_SHIFT) & SDP_STA_ERRSRC_MASK) -#define SDP_STA_ERRSRC_GET(x) (((uint32_t)(x) & SDP_STA_ERRSRC_MASK) >> SDP_STA_ERRSRC_SHIFT) - -/* - * ERRDST (W1C) - * - * Destination Buffer Error - */ -#define SDP_STA_ERRDST_MASK (0x4U) -#define SDP_STA_ERRDST_SHIFT (2U) -#define SDP_STA_ERRDST_SET(x) (((uint32_t)(x) << SDP_STA_ERRDST_SHIFT) & SDP_STA_ERRDST_MASK) -#define SDP_STA_ERRDST_GET(x) (((uint32_t)(x) & SDP_STA_ERRDST_MASK) >> SDP_STA_ERRDST_SHIFT) - -/* - * ERRHAS (W1C) - * - * Hashing Check Error - */ -#define SDP_STA_ERRHAS_MASK (0x2U) -#define SDP_STA_ERRHAS_SHIFT (1U) -#define SDP_STA_ERRHAS_SET(x) (((uint32_t)(x) << SDP_STA_ERRHAS_SHIFT) & SDP_STA_ERRHAS_MASK) -#define SDP_STA_ERRHAS_GET(x) (((uint32_t)(x) & SDP_STA_ERRHAS_MASK) >> SDP_STA_ERRHAS_SHIFT) - -/* - * ERRCHAIN (W1C) - * - * buffer chain error happen when packet's CHAIN bit=0, but the Packet counter is still not zero. - */ -#define SDP_STA_ERRCHAIN_MASK (0x1U) -#define SDP_STA_ERRCHAIN_SHIFT (0U) -#define SDP_STA_ERRCHAIN_SET(x) (((uint32_t)(x) << SDP_STA_ERRCHAIN_SHIFT) & SDP_STA_ERRCHAIN_MASK) -#define SDP_STA_ERRCHAIN_GET(x) (((uint32_t)(x) & SDP_STA_ERRCHAIN_MASK) >> SDP_STA_ERRCHAIN_SHIFT) - -/* Bitfield definition for register: KEYADDR */ -/* - * INDEX (RW) - * - * To write a key to the SDP KEY RAM, the software must first write the desired key index/subword to this register. - * Key index pointer. The valid indices are 0-[number_keys]. - * In the SDP, there is a 16x128 key ram can store 16 AES128 keys or 8 AES 256 Keys; this index is for addressing the 16 128-bit key addresses. - */ -#define SDP_KEYADDR_INDEX_MASK (0xFF0000UL) -#define SDP_KEYADDR_INDEX_SHIFT (16U) -#define SDP_KEYADDR_INDEX_SET(x) (((uint32_t)(x) << SDP_KEYADDR_INDEX_SHIFT) & SDP_KEYADDR_INDEX_MASK) -#define SDP_KEYADDR_INDEX_GET(x) (((uint32_t)(x) & SDP_KEYADDR_INDEX_MASK) >> SDP_KEYADDR_INDEX_SHIFT) - -/* - * SUBWRD (RW) - * - * Key subword pointer. The valid indices are 0-3. After each write to the key data register, this field - * increments; To write a key, the software must first write the desired key index/subword to this register. - */ -#define SDP_KEYADDR_SUBWRD_MASK (0x3U) -#define SDP_KEYADDR_SUBWRD_SHIFT (0U) -#define SDP_KEYADDR_SUBWRD_SET(x) (((uint32_t)(x) << SDP_KEYADDR_SUBWRD_SHIFT) & SDP_KEYADDR_SUBWRD_MASK) -#define SDP_KEYADDR_SUBWRD_GET(x) (((uint32_t)(x) & SDP_KEYADDR_SUBWRD_MASK) >> SDP_KEYADDR_SUBWRD_SHIFT) - -/* Bitfield definition for register: KEYDAT */ -/* - * KEYDAT (RW) - * - * This register provides the write access to the key/key subword specified by the key index register. - * Writing this location updates the selected subword for the key located at the index - * specified by the key index register. The write also triggers the SUBWORD field of the - * KEY register to increment to the next higher word in the key - */ -#define SDP_KEYDAT_KEYDAT_MASK (0xFFFFFFFFUL) -#define SDP_KEYDAT_KEYDAT_SHIFT (0U) -#define SDP_KEYDAT_KEYDAT_SET(x) (((uint32_t)(x) << SDP_KEYDAT_KEYDAT_SHIFT) & SDP_KEYDAT_KEYDAT_MASK) -#define SDP_KEYDAT_KEYDAT_GET(x) (((uint32_t)(x) & SDP_KEYDAT_KEYDAT_MASK) >> SDP_KEYDAT_KEYDAT_SHIFT) - -/* Bitfield definition for register array: CIPHIV */ -/* - * CIPHIV (RW) - * - * cipher initialization vector. - */ -#define SDP_CIPHIV_CIPHIV_MASK (0xFFFFFFFFUL) -#define SDP_CIPHIV_CIPHIV_SHIFT (0U) -#define SDP_CIPHIV_CIPHIV_SET(x) (((uint32_t)(x) << SDP_CIPHIV_CIPHIV_SHIFT) & SDP_CIPHIV_CIPHIV_MASK) -#define SDP_CIPHIV_CIPHIV_GET(x) (((uint32_t)(x) & SDP_CIPHIV_CIPHIV_MASK) >> SDP_CIPHIV_CIPHIV_SHIFT) - -/* Bitfield definition for register array: HASWRD */ -/* - * HASWRD (RW) - * - * Hash Data Word x - HASH result bit; will store the expected hash result bit if hash check enabled; when hash check is not enabled, the hash engine will store the final hash result[31:0] here. - * If CRC mode enabled, this work store the CRC expected result if the check enabled, or store the final calcuated CRC result. - */ -#define SDP_HASWRD_HASWRD_MASK (0xFFFFFFFFUL) -#define SDP_HASWRD_HASWRD_SHIFT (0U) -#define SDP_HASWRD_HASWRD_SET(x) (((uint32_t)(x) << SDP_HASWRD_HASWRD_SHIFT) & SDP_HASWRD_HASWRD_MASK) -#define SDP_HASWRD_HASWRD_GET(x) (((uint32_t)(x) & SDP_HASWRD_HASWRD_MASK) >> SDP_HASWRD_HASWRD_SHIFT) - -/* Bitfield definition for register: CMDPTR */ -/* - * CMDPTR (RW) - * - * current command addresses the register points to the multiword - * descriptor that is to be executed (or is currently being executed) - */ -#define SDP_CMDPTR_CMDPTR_MASK (0xFFFFFFFFUL) -#define SDP_CMDPTR_CMDPTR_SHIFT (0U) -#define SDP_CMDPTR_CMDPTR_SET(x) (((uint32_t)(x) << SDP_CMDPTR_CMDPTR_SHIFT) & SDP_CMDPTR_CMDPTR_MASK) -#define SDP_CMDPTR_CMDPTR_GET(x) (((uint32_t)(x) & SDP_CMDPTR_CMDPTR_MASK) >> SDP_CMDPTR_CMDPTR_SHIFT) - -/* Bitfield definition for register: NPKTPTR */ -/* - * NPKTPTR (RW) - * - * Next Packet Address Pointer - */ -#define SDP_NPKTPTR_NPKTPTR_MASK (0xFFFFFFFFUL) -#define SDP_NPKTPTR_NPKTPTR_SHIFT (0U) -#define SDP_NPKTPTR_NPKTPTR_SET(x) (((uint32_t)(x) << SDP_NPKTPTR_NPKTPTR_SHIFT) & SDP_NPKTPTR_NPKTPTR_MASK) -#define SDP_NPKTPTR_NPKTPTR_GET(x) (((uint32_t)(x) & SDP_NPKTPTR_NPKTPTR_MASK) >> SDP_NPKTPTR_NPKTPTR_SHIFT) - -/* Bitfield definition for register: PKTCTL */ -/* - * PKTTAG (RW) - * - * packet tag - */ -#define SDP_PKTCTL_PKTTAG_MASK (0xFF000000UL) -#define SDP_PKTCTL_PKTTAG_SHIFT (24U) -#define SDP_PKTCTL_PKTTAG_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTTAG_SHIFT) & SDP_PKTCTL_PKTTAG_MASK) -#define SDP_PKTCTL_PKTTAG_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTTAG_MASK) >> SDP_PKTCTL_PKTTAG_SHIFT) - -/* - * CIPHIV (RW) - * - * Load Initial Vector for the AES in this packet. - */ -#define SDP_PKTCTL_CIPHIV_MASK (0x40U) -#define SDP_PKTCTL_CIPHIV_SHIFT (6U) -#define SDP_PKTCTL_CIPHIV_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CIPHIV_SHIFT) & SDP_PKTCTL_CIPHIV_MASK) -#define SDP_PKTCTL_CIPHIV_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CIPHIV_MASK) >> SDP_PKTCTL_CIPHIV_SHIFT) - -/* - * HASFNL (RW) - * - * Hash Termination packet - */ -#define SDP_PKTCTL_HASFNL_MASK (0x20U) -#define SDP_PKTCTL_HASFNL_SHIFT (5U) -#define SDP_PKTCTL_HASFNL_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASFNL_SHIFT) & SDP_PKTCTL_HASFNL_MASK) -#define SDP_PKTCTL_HASFNL_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASFNL_MASK) >> SDP_PKTCTL_HASFNL_SHIFT) - -/* - * HASINI (RW) - * - * Hash Initialization packat - */ -#define SDP_PKTCTL_HASINI_MASK (0x10U) -#define SDP_PKTCTL_HASINI_SHIFT (4U) -#define SDP_PKTCTL_HASINI_SET(x) (((uint32_t)(x) << SDP_PKTCTL_HASINI_SHIFT) & SDP_PKTCTL_HASINI_MASK) -#define SDP_PKTCTL_HASINI_GET(x) (((uint32_t)(x) & SDP_PKTCTL_HASINI_MASK) >> SDP_PKTCTL_HASINI_SHIFT) - -/* - * CHAIN (RW) - * - * whether the next command pointer register must be loaded into the channel's current descriptor - * pointer. - */ -#define SDP_PKTCTL_CHAIN_MASK (0x8U) -#define SDP_PKTCTL_CHAIN_SHIFT (3U) -#define SDP_PKTCTL_CHAIN_SET(x) (((uint32_t)(x) << SDP_PKTCTL_CHAIN_SHIFT) & SDP_PKTCTL_CHAIN_MASK) -#define SDP_PKTCTL_CHAIN_GET(x) (((uint32_t)(x) & SDP_PKTCTL_CHAIN_MASK) >> SDP_PKTCTL_CHAIN_SHIFT) - -/* - * DCRSEMA (RW) - * - * whether the channel's semaphore must be decremented at the end of the current operation. - * When the semaphore reaches a value of zero, no more operations are issued from the channel. - */ -#define SDP_PKTCTL_DCRSEMA_MASK (0x4U) -#define SDP_PKTCTL_DCRSEMA_SHIFT (2U) -#define SDP_PKTCTL_DCRSEMA_SET(x) (((uint32_t)(x) << SDP_PKTCTL_DCRSEMA_SHIFT) & SDP_PKTCTL_DCRSEMA_MASK) -#define SDP_PKTCTL_DCRSEMA_GET(x) (((uint32_t)(x) & SDP_PKTCTL_DCRSEMA_MASK) >> SDP_PKTCTL_DCRSEMA_SHIFT) - -/* - * PKTINT (RW) - * - * Reflects whether the channel must issue an interrupt upon the completion of the packet - */ -#define SDP_PKTCTL_PKTINT_MASK (0x2U) -#define SDP_PKTCTL_PKTINT_SHIFT (1U) -#define SDP_PKTCTL_PKTINT_SET(x) (((uint32_t)(x) << SDP_PKTCTL_PKTINT_SHIFT) & SDP_PKTCTL_PKTINT_MASK) -#define SDP_PKTCTL_PKTINT_GET(x) (((uint32_t)(x) & SDP_PKTCTL_PKTINT_MASK) >> SDP_PKTCTL_PKTINT_SHIFT) - -/* Bitfield definition for register: PKTSRC */ -/* - * PKTSRC (RW) - * - * Packet Memory Source Address - */ -#define SDP_PKTSRC_PKTSRC_MASK (0xFFFFFFFFUL) -#define SDP_PKTSRC_PKTSRC_SHIFT (0U) -#define SDP_PKTSRC_PKTSRC_SET(x) (((uint32_t)(x) << SDP_PKTSRC_PKTSRC_SHIFT) & SDP_PKTSRC_PKTSRC_MASK) -#define SDP_PKTSRC_PKTSRC_GET(x) (((uint32_t)(x) & SDP_PKTSRC_PKTSRC_MASK) >> SDP_PKTSRC_PKTSRC_SHIFT) - -/* Bitfield definition for register: PKTDST */ -/* - * PKTDST (RW) - * - * Packet Memory Destination Address - */ -#define SDP_PKTDST_PKTDST_MASK (0xFFFFFFFFUL) -#define SDP_PKTDST_PKTDST_SHIFT (0U) -#define SDP_PKTDST_PKTDST_SET(x) (((uint32_t)(x) << SDP_PKTDST_PKTDST_SHIFT) & SDP_PKTDST_PKTDST_MASK) -#define SDP_PKTDST_PKTDST_GET(x) (((uint32_t)(x) & SDP_PKTDST_PKTDST_MASK) >> SDP_PKTDST_PKTDST_SHIFT) - -/* Bitfield definition for register: PKTBUF */ -/* - * PKTBUF (RW) - * - */ -#define SDP_PKTBUF_PKTBUF_MASK (0xFFFFFFFFUL) -#define SDP_PKTBUF_PKTBUF_SHIFT (0U) -#define SDP_PKTBUF_PKTBUF_SET(x) (((uint32_t)(x) << SDP_PKTBUF_PKTBUF_SHIFT) & SDP_PKTBUF_PKTBUF_MASK) -#define SDP_PKTBUF_PKTBUF_GET(x) (((uint32_t)(x) & SDP_PKTBUF_PKTBUF_MASK) >> SDP_PKTBUF_PKTBUF_SHIFT) - - - -/* CIPHIV register group index macro definition */ -#define SDP_CIPHIV_CIPHIV0 (0UL) -#define SDP_CIPHIV_CIPHIV1 (1UL) -#define SDP_CIPHIV_CIPHIV2 (2UL) -#define SDP_CIPHIV_CIPHIV3 (3UL) - -/* HASWRD register group index macro definition */ -#define SDP_HASWRD_HASWRD0 (0UL) -#define SDP_HASWRD_HASWRD1 (1UL) -#define SDP_HASWRD_HASWRD2 (2UL) -#define SDP_HASWRD_HASWRD3 (3UL) -#define SDP_HASWRD_HASWRD4 (4UL) -#define SDP_HASWRD_HASWRD5 (5UL) -#define SDP_HASWRD_HASWRD6 (6UL) -#define SDP_HASWRD_HASWRD7 (7UL) - - -#endif /* HPM_SDP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sei_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sei_regs.h deleted file mode 100644 index 7a06a8d9bab..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sei_regs.h +++ /dev/null @@ -1,3655 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SEI_H -#define HPM_SEI_H - -typedef struct { - struct { - struct { - __RW uint32_t CTRL; /* 0x0: Engine control register */ - __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */ - __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __R uint32_t EXE_STA; /* 0x10: Execution status */ - __R uint32_t EXE_PTR; /* 0x14: Execution pointer */ - __R uint32_t EXE_INST; /* 0x18: Execution instruction */ - __R uint32_t WDG_STA; /* 0x1C: Watch dog status */ - } ENGINE; - struct { - __RW uint32_t CTRL; /* 0x20: Transceiver control register */ - __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */ - __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */ - __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */ - __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __R uint32_t PIN; /* 0x38: Transceiver pin status */ - __R uint32_t STATE; /* 0x3C: FSM of asynchronous */ - } XCVR; - struct { - __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */ - __W uint32_t SW; /* 0x44: Software trigger */ - __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */ - __RW uint32_t PRD; /* 0x4C: Trigger period */ - __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */ - __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */ - __R uint32_t PRD_STS; /* 0x60: Period trigger status */ - __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */ - __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */ - } TRG; - struct { - __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */ - __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */ - __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */ - __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */ - } TRG_TABLE; - struct { - __RW uint32_t MODE; /* 0xC0: command register mode */ - __RW uint32_t IDX; /* 0xC4: command register configuration */ - __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */ - __RW uint32_t CMD; /* 0xE0: command */ - __RW uint32_t SET; /* 0xE4: command bit set register */ - __RW uint32_t CLR; /* 0xE8: command bit clear register */ - __RW uint32_t INV; /* 0xEC: command bit invert register */ - __R uint32_t IN; /* 0xF0: Commad input */ - __R uint32_t OUT; /* 0xF4: Command output */ - __RW uint32_t STS; /* 0xF8: Command status */ - __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */ - } CMD; - struct { - __RW uint32_t MIN; /* 0x100: command start value */ - __RW uint32_t MAX; /* 0x104: command end value */ - __RW uint32_t MSK; /* 0x108: command compare bit enable */ - __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */ - __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */ - __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */ - __RW uint32_t PTC; /* 0x118: command pointer 8 - 11 */ - __RW uint32_t PTD; /* 0x11C: command pointer 12 - 15 */ - } CMD_TABLE[8]; - struct { - __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */ - __RW uint32_t CFG; /* 0x210: Latch configuration */ - __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */ - __R uint32_t TIME; /* 0x218: Latch time */ - __R uint32_t STS; /* 0x21C: Latch status */ - } LATCH[4]; - struct { - __RW uint32_t SMP_EN; /* 0x280: Sample selection register */ - __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */ - __RW uint32_t SMP_DAT; /* 0x288: Sample data */ - __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */ - __RW uint32_t SMP_POS; /* 0x290: Sample override position */ - __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */ - __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */ - __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */ - __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */ - __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */ - __RW uint32_t UPD_DAT; /* 0x2A8: Update data */ - __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */ - __RW uint32_t UPD_POS; /* 0x2B0: Update override position */ - __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */ - __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */ - __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */ - __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */ - __R uint32_t SMP_STS; /* 0x2C4: Sample status */ - __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */ - __R uint32_t TIME_IN; /* 0x2CC: input time */ - __R uint32_t POS_IN; /* 0x2D0: Input position */ - __R uint32_t REV_IN; /* 0x2D4: Input revolution */ - __R uint32_t SPD_IN; /* 0x2D8: Input speed */ - __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */ - __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */ - __R uint32_t UPD_STS; /* 0x2E4: Update status */ - __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */ - } POS; - struct { - __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */ - __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */ - __R uint32_t INT_STS; /* 0x308: Interrupt status */ - __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */ - __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */ - __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */ - __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */ - __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */ - } IRQ; - __R uint8_t RESERVED0[224]; /* 0x320 - 0x3FF: Reserved */ - } CTRL[13]; - __RW uint32_t INSTR[256]; /* 0x3400 - 0x37FC: Instructions */ - struct { - __RW uint32_t MODE; /* 0x3800: */ - __RW uint32_t IDX; /* 0x3804: Data register bit index */ - __RW uint32_t GOLD; /* 0x3808: Gold data for data check */ - __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */ - __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */ - __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */ - __RW uint32_t DATA; /* 0x3820: Data value */ - __RW uint32_t SET; /* 0x3824: Data bit set */ - __RW uint32_t CLR; /* 0x3828: Data bit clear */ - __RW uint32_t INV; /* 0x382C: Data bit invert */ - __R uint32_t IN; /* 0x3830: Data input */ - __R uint32_t OUT; /* 0x3834: Data output */ - __RW uint32_t STS; /* 0x3838: Data status */ - __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */ - } DAT[32]; -} SEI_Type; - - -/* Bitfield definition for register of struct array CTRL: CTRL */ -/* - * WATCH (RW) - * - * Enable watch dog - * 0: Watch dog disabled - * 1: Watch dog enabled - */ -#define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL) -#define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U) -#define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) -#define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) - -/* - * ARMING (RW) - * - * Wait for trigger before excuting - * 0: Execute on enable - * 1: Wait trigger before exection after enabled - */ -#define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL) -#define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U) -#define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) -#define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) - -/* - * EXCEPT (RW) - * - * Explain timout as exception - * 0: when timeout, pointer move to next instruction - * 1: when timeout, pointer jump to timeout vector - */ -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U) -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U) -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) -#define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) - -/* - * REWIND (RW) - * - * Rewind execution pointer - * 0: run - * 1: clean status and rewind - */ -#define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U) -#define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U) -#define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) -#define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) - -/* - * ENABLE (RW) - * - * Enable - * 0: disable - * 1: enable - */ -#define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U) -#define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U) -#define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) -#define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTR_CFG */ -/* - * DAT_CDM (RW) - * - * Select DATA register to receive CDM bit in BiSSC slave mode - * 0: ignore - * 1: command - * 2: data register 2 - * 3: data register 3 - * ... - * 29:data register 29 - * 30: value 0 when send, ignore in receive - * 31: value1 when send, ignore in receive - */ -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) - -/* - * DAT_BASE (RW) - * - * Bias for data register access, if calculated index bigger than 32, index will wrap around - * 0: real data index - * 1: access index is 1 greater than instruction address - * 2: access index is 2 greater than instruction address - * ... - * 31: access index is 31 greater than instruction address - */ -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) - -/* - * POINTER_WDOG (RW) - * - * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME - */ -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) - -/* - * POINTER_INIT (RW) - * - * Initial execute pointer - */ -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) -#define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: WDG_CFG */ -/* - * WDOG_TIME (RW) - * - * Time out count for each instruction, counter in bit time. - */ -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU) -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U) -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) -#define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: EXE_STA */ -/* - * TRIGERED (RO) - * - * Execution has been triggered - * 0: Execution not triggered - * 1: Execution triggered - */ -#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL) -#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U) -#define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT) - -/* - * ARMED (RO) - * - * Waiting for trigger for execution - * 0: Not in waiting status - * 1: In waiting status - */ -#define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL) -#define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U) -#define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT) - -/* - * EXPIRE (RO) - * - * Watchdog timer expired - * 0: Not expired - * 1: Expired - */ -#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U) -#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U) -#define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT) - -/* - * STALL (RO) - * - * Program finished - * 0: Program is executing - * 1: Program finished - */ -#define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U) -#define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U) -#define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: EXE_PTR */ -/* - * HALT_CNT (RO) - * - * Halt count in halt instrution - */ -#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL) -#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U) -#define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT) - -/* - * BIT_CNT (RO) - * - * Bit count in send and receive instruction execution - */ -#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL) -#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U) -#define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT) - -/* - * POINTER (RO) - * - * Current program pointer - */ -#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU) -#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U) -#define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT) - -/* Bitfield definition for register of struct array CTRL: EXE_INST */ -/* - * INST (RO) - * - * Current instruction - */ -#define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U) -#define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT) - -/* Bitfield definition for register of struct array CTRL: WDG_STA */ -/* - * WDOG_CNT (RO) - * - * Current watch dog counter value - */ -#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU) -#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U) -#define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CTRL */ -/* - * TRISMP (RW) - * - * Tipple sampe - * 0: sample 1 time for data transition - * 1: sample 3 times in receive and result in 2oo3 - */ -#define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U) -#define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U) -#define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) -#define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) - -/* - * PAR_CLR (WC) - * - * Clear parity error, this is a self clear bit - * 0: no effect - * 1: clear parity error - */ -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U) -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U) -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) -#define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) - -/* - * RESTART (WC) - * - * Restart tranceiver, this is a self clear bit - * 0: no effect - * 1: reset tranceiver - */ -#define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U) -#define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U) -#define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) -#define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) - -/* - * MODE (RW) - * - * Tranceiver mode - * 0: synchronous maaster - * 1: synchronous slave - * 2: asynchronous mode - * 3: asynchronous mode - */ -#define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U) -#define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U) -#define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK) -#define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: TYPE_CFG */ -/* - * WAIT_LEN (RW) - * - * Number of extra stop bit for asynchronous mode - * 0: 1 bit - * 1: 2 bit - * ... - * 255: 256 bit - */ -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL) -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U) -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) - -/* - * DATA_LEN (RW) - * - * Number of data bit for asynchronous mode - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL) -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U) -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) - -/* - * PAR_POL (RW) - * - * Polarity of parity for asynchronous mode - * 0: even - * 1: odd - */ -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) - -/* - * PAR_EN (RW) - * - * enable parity check for asynchronous mode - * 0: disable - * 1: enable - */ -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) - -/* - * DA_IDLEZ (RW) - * - * Idle state driver of data line - * 0: output - * 1: high-Z - */ -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) - -/* - * CK_IDLEZ (RW) - * - * Idle state driver of clock line - * 0: output - * 1: high-Z - */ -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) - -/* - * DA_IDLEV (RW) - * - * Idle state value of data line - * 0: data'0' - * 1: data'1' - */ -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) - -/* - * CK_IDLEV (RW) - * - * Idle state value of clock line - * 0: data'0' - * 1: data'1' - */ -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) -#define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: BAUD_CFG */ -/* - * SYNC_POINT (RW) - * - * Baud synchronous time, minmum bit time - */ -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL) -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U) -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) -#define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) - -/* - * BAUD_DIV (RW) - * - * Baud rate, bit time in system clock cycle - */ -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU) -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U) -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) -#define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: DATA_CFG */ -/* - * TXD_POINT (RW) - * - * data transmit point in system clcok cycle - */ -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL) -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U) -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) -#define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) - -/* - * RXD_POINT (RW) - * - * data receive point in system clcok cycle - */ -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU) -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U) -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) -#define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CLK_CFG */ -/* - * CK1_POINT (RW) - * - * clock point 1 in system clcok cycle - */ -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL) -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U) -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) -#define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) - -/* - * CK0_POINT (RW) - * - * clock point 0 in system clcok cycle - */ -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU) -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U) -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) -#define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PIN */ -/* - * OE_CK (RO) - * - * CK drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL) -#define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U) -#define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT) - -/* - * DI_CK (RO) - * - * CK state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL) -#define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U) -#define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT) - -/* - * DO_CK (RO) - * - * CK output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL) -#define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U) -#define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT) - -/* - * OE_RX (RO) - * - * RX drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL) -#define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U) -#define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT) - -/* - * DI_RX (RO) - * - * RX state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL) -#define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U) -#define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT) - -/* - * DO_RX (RO) - * - * RX output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL) -#define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U) -#define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT) - -/* - * OE_DE (RO) - * - * DE drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U) -#define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U) -#define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT) - -/* - * DI_DE (RO) - * - * DE state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U) -#define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U) -#define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT) - -/* - * DO_DE (RO) - * - * DE output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U) -#define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U) -#define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT) - -/* - * OE_TX (RO) - * - * TX drive state - * 0: input - * 1: output - */ -#define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U) -#define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U) -#define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT) - -/* - * DI_TX (RO) - * - * TX state - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U) -#define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U) -#define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT) - -/* - * DO_TX (RO) - * - * TX output - * 0: data 0 - * 1: data 1 - */ -#define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U) -#define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U) -#define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT) - -/* Bitfield definition for register of struct array CTRL: STATE */ -/* - * RECV_STATE (RO) - * - * FSM of asynchronous receive - */ -#define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL) -#define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U) -#define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT) - -/* - * SEND_STATE (RO) - * - * FSM of asynchronous transmit - */ -#define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL) -#define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U) -#define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: IN_CFG */ -/* - * REWIND_EN (RW) - * - * enable rewind cmd register by LATCH - */ -#define SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK (0x80000000UL) -#define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT (31U) -#define SEI_CTRL_TRG_IN_CFG_REWIND_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_REWIND_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_EN_SHIFT) - -/* - * REWIND_SEL (RW) - * - * select one LATCH to rewind CMD register - * 0:LATCH[0] - * 1:LATCH[1] - * 2:LATCH[2] - * 3:LATCH[3] - */ -#define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK (0x3000000UL) -#define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT (24U) -#define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_REWIND_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_REWIND_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_REWIND_SEL_SHIFT) - -/* - * PRD_EN (RW) - * - * Enable period trigger (tigger 2) - * 0: periodical trigger disabled - * 1: periodical trigger enabled - */ -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL) -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U) -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) - -/* - * SYNC_SEL (RW) - * - * Synchronize sigal selection (tigger 2) - * 0: trigger in 0 - * 1: trigger in 1 - * ... - * 7: trigger in 7 - */ -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL) -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U) -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) - -/* - * IN1_EN (RW) - * - * Enable trigger 1 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U) -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U) -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) - -/* - * IN1_SEL (RW) - * - * Trigger 1 sigal selection - * 0: trigger in 0 - * 1: trigger in 1 - * ... - * 7: trigger in 7 - */ -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U) -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U) -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) - -/* - * IN0_EN (RW) - * - * Enable trigger 0 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U) -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U) -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) - -/* - * IN0_SEL (RW) - * - * Trigger 0 sigal selection - * 0: trigger in 0 - * 1: trigger in 1 - * ... - * 7: trigger in 7 - */ -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U) -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U) -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) -#define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SW */ -/* - * SOFT (WC) - * - * Software trigger (tigger 3). this bit is self-clear - * 0: trigger source disabled - * 1: trigger source enabled - */ -#define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U) -#define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U) -#define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK) -#define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD_CFG */ -/* - * ARMING (RW) - * - * Wait for trigger synchronous before trigger - * 0: Trigger directly - * 1: Wait trigger source before period trigger - */ -#define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL) -#define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U) -#define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) -#define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) - -/* - * SYNC (RW) - * - * Synchronous - * 0: Not synchronous - * 1: Synchronous every trigger source - */ -#define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U) -#define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U) -#define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) -#define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD */ -/* - * PERIOD (RW) - * - * Trigger period - */ -#define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U) -#define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK) -#define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: OUT_CFG */ -/* - * OUT3_EN (RW) - * - * Enable trigger 3 - * 0: disable trigger 3 - * 1: enable trigger 3 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) - -/* - * OUT3_SEL (RW) - * - * Trigger 3 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) - -/* - * OUT2_EN (RW) - * - * Enable trigger 2 - * 0: disable trigger 2 - * 1: enable trigger 2 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) - -/* - * OUT2_SEL (RW) - * - * Trigger 2 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) - -/* - * OUT1_EN (RW) - * - * Enable trigger 1 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) - -/* - * OUT1_SEL (RW) - * - * Trigger 1 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) - -/* - * OUT0_EN (RW) - * - * Enable trigger 0 - * 0: disable trigger 1 - * 1: enable trigger 1 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) - -/* - * OUT0_SEL (RW) - * - * Trigger 0 sigal selection - * 0: trigger out 0 - * 1: trigger out 1 - * ... - * 7: trigger out 7 - */ -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) -#define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD_STS */ -/* - * TRIGERED (RO) - * - * Period has been triggered - * 0: Not triggered - * 1: Triggered - */ -#define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL) -#define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U) -#define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT) - -/* - * ARMED (RO) - * - * Waiting for trigger - * 0: Not in waiting status - * 1: In waiting status - */ -#define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL) -#define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U) -#define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PRD_CNT */ -/* - * PERIOD_CNT (RO) - * - * Trigger period counter - */ -#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U) -#define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: 0 */ -/* - * CMD_TRIGGER0 (RW) - * - * Trigger command - */ -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U) -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) -#define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) - -/* Bitfield definition for register of struct array CTRL: 0 */ -/* - * TRIGGER0_TIME (RO) - * - * Trigger time - */ -#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U) -#define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MODE */ -/* - * WLEN (RW) - * - * word length - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL) -#define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U) -#define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK) -#define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT) - -/* - * WORDER (RW) - * - * word order - * 0: sample as bit order - * 1: different from bit order - */ -#define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U) -#define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U) -#define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK) -#define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT) - -/* - * BORDER (RW) - * - * bit order - * 0: LSB first - * 1: MSB first - */ -#define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U) -#define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U) -#define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK) -#define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT) - -/* - * SIGNED (RW) - * - * Signed - * 0: unsigned value - * 1: signed value - */ -#define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U) -#define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U) -#define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK) -#define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT) - -/* - * REWIND (WC) - * - * Write 1 to rewind read/write pointer, this is a self clear bit - */ -#define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U) -#define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U) -#define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK) -#define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT) - -/* - * MODE (RW) - * - * Data mode(CMD register only support data mode) - * 0: data mode - * 1: check mode - * 2: CRC mode - */ -#define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U) -#define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U) -#define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK) -#define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT) - -/* Bitfield definition for register of struct array CTRL: IDX */ -/* - * LAST_BIT (RW) - * - * Last bit index for tranceive - */ -#define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL) -#define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U) -#define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) -#define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) - -/* - * FIRST_BIT (RW) - * - * First bit index for tranceive - */ -#define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL) -#define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U) -#define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) -#define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) - -/* - * MAX_BIT (RW) - * - * Highest bit index - */ -#define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U) -#define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U) -#define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) -#define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) - -/* - * MIN_BIT (RW) - * - * Lowest bit index - */ -#define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU) -#define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U) -#define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) -#define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CMD */ -/* - * DATA (RW) - * - * DATA - */ -#define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U) -#define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK) -#define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SET */ -/* - * DATA_SET (RW) - * - * DATA bit set - */ -#define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U) -#define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK) -#define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CLR */ -/* - * DATA_CLR (RW) - * - * DATA bit clear - */ -#define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U) -#define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) -#define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INV */ -/* - * DATA_TGL (RW) - * - * DATA bit toggle - */ -#define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U) -#define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) -#define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: IN */ -/* - * DATA_IN (RO) - * - * Commad input - */ -#define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U) -#define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT) - -/* Bitfield definition for register of struct array CTRL: OUT */ -/* - * DATA_OUT (RO) - * - * Command output - */ -#define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U) -#define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: STS */ -/* - * WORD_IDX (RO) - * - * Word index - */ -#define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL) -#define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U) -#define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT) - -/* - * WORD_CNT (RO) - * - * Word counter - */ -#define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U) -#define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U) -#define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT) - -/* - * BIT_IDX (RO) - * - * Bit index - */ -#define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU) -#define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U) -#define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MIN */ -/* - * CMD_MIN (RW) - * - * minimum command value - */ -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) -#define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MAX */ -/* - * CMD_MAX (RW) - * - * maximum command value - */ -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) -#define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) - -/* Bitfield definition for register of struct array CTRL: MSK */ -/* - * CMD_MASK (RW) - * - * compare mask - */ -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) -#define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTA */ -/* - * PTR3 (RW) - * - * pointer3 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL) -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) - -/* - * PTR2 (RW) - * - * pointer2 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL) -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) - -/* - * PTR1 (RW) - * - * pointer1 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) - -/* - * PTR0 (RW) - * - * pointer0 - */ -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU) -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) -#define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTB */ -/* - * PTR7 (RW) - * - * pointer7 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL) -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) - -/* - * PTR6 (RW) - * - * pointer6 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL) -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) - -/* - * PTR5 (RW) - * - * pointer5 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) - -/* - * PTR4 (RW) - * - * pointer4 - */ -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU) -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) -#define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTC */ -/* - * PTR11 (RW) - * - * pointer11 - */ -#define SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK (0xFF000000UL) -#define SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT (24U) -#define SEI_CTRL_CMD_TABLE_PTC_PTR11_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) -#define SEI_CTRL_CMD_TABLE_PTC_PTR11_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR11_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR11_SHIFT) - -/* - * PTR10 (RW) - * - * pointer10 - */ -#define SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK (0xFF0000UL) -#define SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT (16U) -#define SEI_CTRL_CMD_TABLE_PTC_PTR10_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) -#define SEI_CTRL_CMD_TABLE_PTC_PTR10_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR10_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR10_SHIFT) - -/* - * PTR9 (RW) - * - * pointer9 - */ -#define SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK (0xFF00U) -#define SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT (8U) -#define SEI_CTRL_CMD_TABLE_PTC_PTR9_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) -#define SEI_CTRL_CMD_TABLE_PTC_PTR9_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR9_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR9_SHIFT) - -/* - * PTR8 (RW) - * - * pointer8 - */ -#define SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK (0xFFU) -#define SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_PTC_PTR8_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) -#define SEI_CTRL_CMD_TABLE_PTC_PTR8_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTC_PTR8_MASK) >> SEI_CTRL_CMD_TABLE_PTC_PTR8_SHIFT) - -/* Bitfield definition for register of struct array CTRL: PTD */ -/* - * PTR15 (RW) - * - * pointer15 - */ -#define SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK (0xFF000000UL) -#define SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT (24U) -#define SEI_CTRL_CMD_TABLE_PTD_PTR15_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) -#define SEI_CTRL_CMD_TABLE_PTD_PTR15_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR15_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR15_SHIFT) - -/* - * PTR14 (RW) - * - * pointer14 - */ -#define SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK (0xFF0000UL) -#define SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT (16U) -#define SEI_CTRL_CMD_TABLE_PTD_PTR14_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) -#define SEI_CTRL_CMD_TABLE_PTD_PTR14_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR14_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR14_SHIFT) - -/* - * PTR13 (RW) - * - * pointer13 - */ -#define SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK (0xFF00U) -#define SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT (8U) -#define SEI_CTRL_CMD_TABLE_PTD_PTR13_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) -#define SEI_CTRL_CMD_TABLE_PTD_PTR13_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR13_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR13_SHIFT) - -/* - * PTR12 (RW) - * - * pointer12 - */ -#define SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK (0xFFU) -#define SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT (0U) -#define SEI_CTRL_CMD_TABLE_PTD_PTR12_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) -#define SEI_CTRL_CMD_TABLE_PTD_PTR12_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTD_PTR12_MASK) >> SEI_CTRL_CMD_TABLE_PTD_PTR12_SHIFT) - -/* Bitfield definition for register of struct array CTRL: 0_1 */ -/* - * POINTER (RW) - * - * pointer - */ -#define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL) -#define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U) -#define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) -#define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) - -/* - * CFG_TM (RW) - * - * timeout - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL) -#define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U) -#define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) - -/* - * CFG_RXD (RW) - * - * data received - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK (0xC000U) -#define SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT (14U) -#define SEI_CTRL_LATCH_TRAN_CFG_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_RXD_SHIFT) - -/* - * CFG_TXD (RW) - * - * data send - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U) -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U) -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) - -/* - * CFG_CLK (RW) - * - * clock - * 0: high - * 1: low - * 2: rise - * 3: fall - */ -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U) -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U) -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) - -/* - * CFG_PTR (RW) - * - * pointer - * 0: match - * 1: not match - * 2:entry - * 3:leave - */ -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U) -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U) -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) -#define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) - -/* - * OV_TM (RW) - * - * override timeout check - */ -#define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U) -#define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U) -#define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) - -/* - * OV_RXD (RW) - * - * override RX data check - */ -#define SEI_CTRL_LATCH_TRAN_OV_RXD_MASK (0x8U) -#define SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT (3U) -#define SEI_CTRL_LATCH_TRAN_OV_RXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_RXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_RXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_RXD_SHIFT) - -/* - * OV_TXD (RW) - * - * override TX data check - */ -#define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U) -#define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U) -#define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) - -/* - * OV_CLK (RW) - * - * override clock check - */ -#define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U) -#define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U) -#define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) - -/* - * OV_PTR (RW) - * - * override pointer check - */ -#define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U) -#define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U) -#define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) -#define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: CFG */ -/* - * EN (RW) - * - * Enable latch - * 0: disable - * 1: enable - */ -#define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL) -#define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U) -#define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK) -#define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT) - -/* - * SELECT (RW) - * - * Output select - * 0: state0-state1 - * 1: state1-state2 - * 2: state2-state3 - * 3: state3-state0 - */ -#define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL) -#define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U) -#define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK) -#define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT) - -/* - * DELAY (RW) - * - * Delay in system clock cycle, for state transition - */ -#define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU) -#define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U) -#define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK) -#define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT) - -/* Bitfield definition for register of struct array CTRL: TIME */ -/* - * LAT_TIME (RO) - * - * Latch time - */ -#define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U) -#define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: STS */ -/* - * STATE (RO) - * - * State - */ -#define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL) -#define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U) -#define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT) - -/* - * LAT_CNT (RO) - * - * Latch counter - */ -#define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU) -#define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U) -#define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_EN */ -/* - * ACC_EN (RW) - * - * Position include acceleration - * 0: use acceleration from sample override acceleration register - * 1: use acceleration from motor group - */ -#define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL) -#define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U) -#define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) - -/* - * ACC_SEL (RW) - * - * Data register for acceleration transfer - */ -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL) -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U) -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) - -/* - * SPD_EN (RW) - * - * Position include speed - * 0: use speed from sample override speed register - * 1: use speed from motor group - */ -#define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL) -#define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U) -#define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) - -/* - * SPD_SEL (RW) - * - * Data register for speed transfer - */ -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL) -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U) -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) - -/* - * REV_EN (RW) - * - * Position include revolution - * 0: use revolution from sample override revolution register - * 1: use revolution from motor group - */ -#define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U) -#define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U) -#define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) - -/* - * REV_SEL (RW) - * - * Data register for revolution transfer - */ -#define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U) -#define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U) -#define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) - -/* - * POS_EN (RW) - * - * Position include position - * 0: use position from sample override position register - * 1: use position from motor group - */ -#define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U) -#define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U) -#define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) -#define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) - -/* - * POS_SEL (RW) - * - * Data register for position transfer - */ -#define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU) -#define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U) -#define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) -#define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_CFG */ -/* - * ONCE (RW) - * - * Sample one time - * 0: Sample during windows time - * 1: Close sample window after first sample - */ -#define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL) -#define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U) -#define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) -#define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) - -/* - * LAT_SEL (RW) - * - * Latch selection - * 0: latch 0 - * 1: latch 1 - * 2: latch 2 - * 3: latch 3 - */ -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL) -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U) -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) -#define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) - -/* - * WINDOW (RW) - * - * Sample window, in clock cycle - */ -#define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU) -#define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U) -#define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) -#define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_DAT */ -/* - * DAT_SEL (RW) - * - * Data register sampled, each bit represent a data register - */ -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U) -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) -#define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_POS */ -/* - * POS (RW) - * - * Sample override position - */ -#define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U) -#define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK) -#define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_REV */ -/* - * REV (RW) - * - * Sample override revolution - */ -#define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U) -#define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK) -#define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_SPD */ -/* - * SPD (RW) - * - * Sample override speed - */ -#define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U) -#define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) -#define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_ACC */ -/* - * ACC (RW) - * - * Sample override accelerate - */ -#define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U) -#define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) -#define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_EN */ -/* - * ACC_EN (RW) - * - * Position include acceleration - * 0: use acceleration from update override acceleration register - * 1: use acceleration from data register - */ -#define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL) -#define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U) -#define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) - -/* - * ACC_SEL (RW) - * - * Data register for acceleration transfer - */ -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL) -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U) -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) - -/* - * SPD_EN (RW) - * - * Position include speed - * 0: use speed from update override speed register - * 1: use speed from data register - */ -#define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL) -#define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U) -#define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) - -/* - * SPD_SEL (RW) - * - * Data register for speed transfer - */ -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL) -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U) -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) - -/* - * REV_EN (RW) - * - * Position include revolution - * 0: use revolution from update override revolution register - * 1: use revolution from data register - */ -#define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U) -#define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U) -#define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) - -/* - * REV_SEL (RW) - * - * Data register for revolution transfer - */ -#define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U) -#define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U) -#define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) - -/* - * POS_EN (RW) - * - * Position include position - * 0: use position from update override position register - * 1: use position from data register - */ -#define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U) -#define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U) -#define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) -#define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) - -/* - * POS_SEL (RW) - * - * Data register for position transfer - */ -#define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU) -#define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U) -#define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) -#define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_CFG */ -/* - * TIME_OVRD (RW) - * - * Use override time - * 0: use time sample from motor group - * 1: use override time - */ -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL) -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U) -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) -#define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) - -/* - * ONERR (RW) - * - * Sample one time - * 0: Sample during windows time - * 1: Close sample window after first sample - */ -#define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL) -#define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U) -#define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) -#define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) - -/* - * LAT_SEL (RW) - * - * Latch selection - * 0: latch 0 - * 1: latch 1 - * 2: latch 2 - * 3: latch 3 - */ -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL) -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U) -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) -#define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_DAT */ -/* - * DAT_SEL (RW) - * - * Data register sampled, each bit represent a data register - */ -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U) -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) -#define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_TIME */ -/* - * TIME (RW) - * - * Update override time - */ -#define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U) -#define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) -#define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_POS */ -/* - * POS (RW) - * - * Update override position - */ -#define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U) -#define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK) -#define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_REV */ -/* - * REV (RW) - * - * Update override revolution - */ -#define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U) -#define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK) -#define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_SPD */ -/* - * SPD (RW) - * - * Update override speed - */ -#define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U) -#define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) -#define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_ACC */ -/* - * ACC (RW) - * - * Update override accelerate - */ -#define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U) -#define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) -#define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_VAL */ -/* - * ACC (RO) - * - * Position include acceleration - */ -#define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL) -#define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U) -#define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT) - -/* - * SPD (RO) - * - * Position include speed - */ -#define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL) -#define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U) -#define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT) - -/* - * REV (RO) - * - * Position include revolution - */ -#define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U) -#define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U) -#define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT) - -/* - * POS (RO) - * - * Position include position - */ -#define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U) -#define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U) -#define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SMP_STS */ -/* - * OCCUR (RO) - * - * Sample occured - * 0: Sample not happened - * 1: Sample occured - */ -#define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL) -#define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U) -#define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT) - -/* - * WIN_CNT (RO) - * - * Sample window counter - */ -#define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU) -#define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U) -#define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT) - -/* Bitfield definition for register of struct array CTRL: TIME_IN */ -/* - * TIME (RO) - * - * input time - */ -#define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U) -#define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT) - -/* Bitfield definition for register of struct array CTRL: POS_IN */ -/* - * POS (RO) - * - * Input position - */ -#define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U) -#define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT) - -/* Bitfield definition for register of struct array CTRL: REV_IN */ -/* - * REV (RO) - * - * Input revolution - */ -#define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U) -#define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT) - -/* Bitfield definition for register of struct array CTRL: SPD_IN */ -/* - * SPD (RO) - * - * Input speed - */ -#define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U) -#define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT) - -/* Bitfield definition for register of struct array CTRL: ACC_IN */ -/* - * ACC (RO) - * - * Input accelerate - */ -#define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U) -#define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT) - -/* Bitfield definition for register of struct array CTRL: UPD_STS */ -/* - * UPD_ERR (RO) - * - * Update error - * 0: data receive normally - * 1: data receive error - */ -#define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL) -#define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U) -#define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INT_EN */ -/* - * TRG_ERR3 (RW) - * - * Trigger3 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) - -/* - * TRG_ERR2 (RW) - * - * Trigger2 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) - -/* - * TRG_ERR1 (RW) - * - * Trigger1 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) - -/* - * TRG_ERR0 (RW) - * - * Trigger0 failed - */ -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) - -/* - * TRIGER3 (RW) - * - * Trigger3 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) - -/* - * TRIGER2 (RW) - * - * Trigger2 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) - -/* - * TRIGER1 (RW) - * - * Trigger1 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) - -/* - * TRIGER0 (RW) - * - * Trigger0 - */ -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL) -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U) -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) - -/* - * SMP_ERR (RW) - * - * Sample error - */ -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL) -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U) -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) -#define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) - -/* - * LATCH3 (RW) - * - * Latch3 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U) -#define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) - -/* - * LATCH2 (RW) - * - * Latch2 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U) -#define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) - -/* - * LATCH1 (RW) - * - * Latch1 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U) -#define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) - -/* - * LATCH0 (RW) - * - * Latch0 - */ -#define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL) -#define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U) -#define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) -#define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) - -/* - * TIMEOUT (RW) - * - * Timeout - */ -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U) -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U) -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) -#define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) - -/* - * TRX_ERR (RW) - * - * Transfer error - */ -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U) -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U) -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) -#define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) - -/* - * INSTR1_END (RW) - * - * Instruction 1 end - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) - -/* - * INSTR0_END (RW) - * - * Instruction 0 end - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) - -/* - * PTR1_END (RW) - * - * Pointer 1 end - */ -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) - -/* - * PTR0_END (RW) - * - * Pointer 0 end - */ -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) - -/* - * INSTR1_ST (RW) - * - * Instruction 1 start - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) - -/* - * INSTR0_ST (RW) - * - * Instruction 0 start - */ -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) - -/* - * PTR1_ST (RW) - * - * Pointer 1 start - */ -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U) -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) - -/* - * PTR0_ST (RW) - * - * Pointer 0 start - */ -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U) -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) - -/* - * WDOG (RW) - * - * Watch dog - */ -#define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U) -#define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U) -#define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) -#define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) - -/* - * EXCEPT (RW) - * - * Exception - */ -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U) -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U) -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) -#define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) - -/* - * STALL (RW) - * - * Stall - */ -#define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U) -#define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U) -#define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) -#define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INT_FLAG */ -/* - * TRG_ERR3 (W1C) - * - * Trigger3 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) - -/* - * TRG_ERR2 (W1C) - * - * Trigger2 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) - -/* - * TRG_ERR1 (W1C) - * - * Trigger1 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) - -/* - * TRG_ERR0 (W1C) - * - * Trigger0 failed - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) - -/* - * TRIGER3 (W1C) - * - * Trigger3 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) - -/* - * TRIGER2 (W1C) - * - * Trigger2 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) - -/* - * TRIGER1 (W1C) - * - * Trigger1 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) - -/* - * TRIGER0 (W1C) - * - * Trigger0 - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) - -/* - * SMP_ERR (W1C) - * - * Sample error - */ -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL) -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U) -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) - -/* - * LATCH3 (W1C) - * - * Latch3 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) - -/* - * LATCH2 (W1C) - * - * Latch2 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) - -/* - * LATCH1 (W1C) - * - * Latch1 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) - -/* - * LATCH0 (W1C) - * - * Latch0 - */ -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) - -/* - * TIMEOUT (W1C) - * - * Timeout - */ -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U) -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U) -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) - -/* - * TRX_ERR (W1C) - * - * Transfer error - */ -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U) -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U) -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) - -/* - * INSTR1_END (W1C) - * - * Instruction 1 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) - -/* - * INSTR0_END (W1C) - * - * Instruction 0 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) - -/* - * PTR1_END (W1C) - * - * Pointer 1 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) - -/* - * PTR0_END (W1C) - * - * Pointer 0 end - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) - -/* - * INSTR1_ST (W1C) - * - * Instruction 1 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) - -/* - * INSTR0_ST (W1C) - * - * Instruction 0 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) - -/* - * PTR1_ST (W1C) - * - * Pointer 1 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) - -/* - * PTR0_ST (W1C) - * - * Pointer 0 start - */ -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) - -/* - * WDOG (W1C) - * - * Watch dog - */ -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U) -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U) -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) - -/* - * EXCEPT (W1C) - * - * Exception - */ -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U) -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U) -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) - -/* - * STALL (W1C) - * - * Stall - */ -#define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U) -#define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U) -#define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) -#define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INT_STS */ -/* - * TRG_ERR3 (RO) - * - * Trigger3 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT) - -/* - * TRG_ERR2 (RO) - * - * Trigger2 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT) - -/* - * TRG_ERR1 (RO) - * - * Trigger1 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT) - -/* - * TRG_ERR0 (RO) - * - * Trigger0 failed - */ -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U) -#define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT) - -/* - * TRIGER3 (RO) - * - * Trigger3 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT) - -/* - * TRIGER2 (RO) - * - * Trigger2 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT) - -/* - * TRIGER1 (RO) - * - * Trigger1 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT) - -/* - * TRIGER0 (RO) - * - * Trigger0 - */ -#define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL) -#define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U) -#define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT) - -/* - * SMP_ERR (RO) - * - * Sample error - */ -#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL) -#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U) -#define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT) - -/* - * LATCH3 (RO) - * - * Latch3 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U) -#define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT) - -/* - * LATCH2 (RO) - * - * Latch2 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U) -#define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT) - -/* - * LATCH1 (RO) - * - * Latch1 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U) -#define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT) - -/* - * LATCH0 (RO) - * - * Latch0 - */ -#define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL) -#define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U) -#define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT) - -/* - * TIMEOUT (RO) - * - * Timeout - */ -#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U) -#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U) -#define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT) - -/* - * TRX_ERR (RO) - * - * Transfer error - */ -#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U) -#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U) -#define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT) - -/* - * INSTR1_END (RO) - * - * Instruction 1 end - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT) - -/* - * INSTR0_END (RO) - * - * Instruction 0 end - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT) - -/* - * PTR1_END (RO) - * - * Pointer 1 end - */ -#define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT) - -/* - * PTR0_END (RO) - * - * Pointer 0 end - */ -#define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT) - -/* - * INSTR1_ST (RO) - * - * Instruction 1 start - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U) -#define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT) - -/* - * INSTR0_ST (RO) - * - * Instruction 0 start - */ -#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U) -#define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT) - -/* - * PTR1_ST (RO) - * - * Pointer 1 start - */ -#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U) -#define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT) - -/* - * PTR0_ST (RO) - * - * Pointer 0 start - */ -#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U) -#define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT) - -/* - * WDOG (RO) - * - * Watch dog - */ -#define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U) -#define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U) -#define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT) - -/* - * EXCEPT (RO) - * - * Exception - */ -#define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U) -#define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U) -#define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT) - -/* - * STALL (RO) - * - * Stall - */ -#define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U) -#define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U) -#define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT) - -/* Bitfield definition for register of struct array CTRL: POINTER0 */ -/* - * POINTER (RW) - * - * Match pointer 0 - */ -#define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU) -#define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U) -#define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) -#define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) - -/* Bitfield definition for register of struct array CTRL: POINTER1 */ -/* - * POINTER (RW) - * - * Match pointer 1 - */ -#define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU) -#define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U) -#define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) -#define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INSTR0 */ -/* - * INSTR (RW) - * - * Match instruction 0 - */ -#define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U) -#define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) -#define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) - -/* Bitfield definition for register of struct array CTRL: INSTR1 */ -/* - * INSTR (RW) - * - * Match instruction 1 - */ -#define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL) -#define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U) -#define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) -#define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) - -/* Bitfield definition for register array: INSTR */ -/* - * OP (RW) - * - * operation - * 0: halt - * 1: jump - * 2: send with timeout check - * 3: send without timout check - * 4: wait with timeout check - * 5: wait without timout check - * 6: receive with timeout check - * 7: receive without timout check - */ -#define SEI_INSTR_OP_MASK (0x1C000000UL) -#define SEI_INSTR_OP_SHIFT (26U) -#define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK) -#define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT) - -/* - * CK (RW) - * - * clock - * 0: low - * 1: rise-fall - * 2: fall-rise - * 3: high - */ -#define SEI_INSTR_CK_MASK (0x3000000UL) -#define SEI_INSTR_CK_SHIFT (24U) -#define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK) -#define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT) - -/* - * CRC (RW) - * - * CRC register - * 0: don't calculate CRC - * 1: do not set this value - * 2: data register 2 - * 3: data register 3 - * ... - * 29: data register 29 - * 30: value 0 when send, wait 0 in receive - * 31: value1 when send, wait 1 in receive - */ -#define SEI_INSTR_CRC_MASK (0x1F0000UL) -#define SEI_INSTR_CRC_SHIFT (16U) -#define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK) -#define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT) - -/* - * DAT (RW) - * - * DATA register - * 0: ignore data - * 1: command - * 2: data register 2 - * 3: data register 3 - * ... - * 29: data register 29 - * 30: value 0 when send, wait 0 in receive - * 31: value1 when send, wait 1 in receive - */ -#define SEI_INSTR_DAT_MASK (0x1F00U) -#define SEI_INSTR_DAT_SHIFT (8U) -#define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK) -#define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT) - -/* - * OPR (RW) - * - * [1] When OP is 0, this area is the halt time in baudrate, 0 represents infinite time. - * [2] When OP is 1, this area is the the pointer to the command table. - * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer; - * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER; - * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER. - * [3] When OP is 2-7, this area is the data length as fellow: - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_INSTR_OPR_MASK (0x1FU) -#define SEI_INSTR_OPR_SHIFT (0U) -#define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK) -#define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT) - -/* Bitfield definition for register of struct array DAT: MODE */ -/* - * CRC_LEN (RW) - * - * CRC length - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL) -#define SEI_DAT_MODE_CRC_LEN_SHIFT (24U) -#define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK) -#define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT) - -/* - * WLEN (RW) - * - * word length - * 0: 1 bit - * 1: 2 bit - * ... - * 31: 32 bit - */ -#define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL) -#define SEI_DAT_MODE_WLEN_SHIFT (16U) -#define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK) -#define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT) - -/* - * CRC_SHIFT (RW) - * - * CRC shift mode, this mode is used to perform repeat code check - * 0: CRC - * 1: shift mode - */ -#define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U) -#define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U) -#define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK) -#define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT) - -/* - * CRC_INV (RW) - * - * CRC invert - * 0: use CRC - * 1: use inverted CRC - */ -#define SEI_DAT_MODE_CRC_INV_MASK (0x1000U) -#define SEI_DAT_MODE_CRC_INV_SHIFT (12U) -#define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK) -#define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT) - -/* - * WORDER (RW) - * - * word order - * 0: sample as bit order - * 1: different from bit order - */ -#define SEI_DAT_MODE_WORDER_MASK (0x800U) -#define SEI_DAT_MODE_WORDER_SHIFT (11U) -#define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK) -#define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT) - -/* - * BORDER (RW) - * - * bit order - * 0: LSB first - * 1: MSB first - */ -#define SEI_DAT_MODE_BORDER_MASK (0x400U) -#define SEI_DAT_MODE_BORDER_SHIFT (10U) -#define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK) -#define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT) - -/* - * SIGNED (RW) - * - * Signed - * 0: unsigned value - * 1: signed value - */ -#define SEI_DAT_MODE_SIGNED_MASK (0x200U) -#define SEI_DAT_MODE_SIGNED_SHIFT (9U) -#define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK) -#define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT) - -/* - * REWIND (RW) - * - * Write 1 to rewind read/write pointer, this is a self clear bit - */ -#define SEI_DAT_MODE_REWIND_MASK (0x100U) -#define SEI_DAT_MODE_REWIND_SHIFT (8U) -#define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK) -#define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT) - -/* - * MODE (RW) - * - * Data mode - * 0: data mode - * 1: check mode - * 2: CRC mode - */ -#define SEI_DAT_MODE_MODE_MASK (0x3U) -#define SEI_DAT_MODE_MODE_SHIFT (0U) -#define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK) -#define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT) - -/* Bitfield definition for register of struct array DAT: IDX */ -/* - * LAST_BIT (RW) - * - * Last bit index for tranceive - */ -#define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL) -#define SEI_DAT_IDX_LAST_BIT_SHIFT (24U) -#define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK) -#define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT) - -/* - * FIRST_BIT (RW) - * - * First bit index for tranceive - */ -#define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL) -#define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U) -#define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK) -#define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT) - -/* - * MAX_BIT (RW) - * - * Highest bit index - */ -#define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U) -#define SEI_DAT_IDX_MAX_BIT_SHIFT (8U) -#define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK) -#define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT) - -/* - * MIN_BIT (RW) - * - * Lowest bit index - */ -#define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU) -#define SEI_DAT_IDX_MIN_BIT_SHIFT (0U) -#define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK) -#define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT) - -/* Bitfield definition for register of struct array DAT: GOLD */ -/* - * GOLD_VALUE (RW) - * - * Gold value for check mode - */ -#define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) -#define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U) -#define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK) -#define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT) - -/* Bitfield definition for register of struct array DAT: CRCINIT */ -/* - * CRC_INIT (RW) - * - * CRC initial value - */ -#define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) -#define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U) -#define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK) -#define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT) - -/* Bitfield definition for register of struct array DAT: CRCPOLY */ -/* - * CRC_POLY (RW) - * - * CRC polymonial - */ -#define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) -#define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U) -#define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) -#define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) - -/* Bitfield definition for register of struct array DAT: DATA */ -/* - * DATA (RW) - * - * DATA - */ -#define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SEI_DAT_DATA_DATA_SHIFT (0U) -#define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK) -#define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT) - -/* Bitfield definition for register of struct array DAT: SET */ -/* - * DATA_SET (RW) - * - * DATA bit set - */ -#define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL) -#define SEI_DAT_SET_DATA_SET_SHIFT (0U) -#define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK) -#define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT) - -/* Bitfield definition for register of struct array DAT: CLR */ -/* - * DATA_CLR (RW) - * - * DATA bit clear - */ -#define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) -#define SEI_DAT_CLR_DATA_CLR_SHIFT (0U) -#define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK) -#define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT) - -/* Bitfield definition for register of struct array DAT: INV */ -/* - * DATA_INV (RW) - * - * DATA bit toggle - */ -#define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL) -#define SEI_DAT_INV_DATA_INV_SHIFT (0U) -#define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK) -#define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT) - -/* Bitfield definition for register of struct array DAT: IN */ -/* - * DATA_IN (RO) - * - * Data input - */ -#define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL) -#define SEI_DAT_IN_DATA_IN_SHIFT (0U) -#define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT) - -/* Bitfield definition for register of struct array DAT: OUT */ -/* - * DATA_OUT (RO) - * - * Data output - */ -#define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) -#define SEI_DAT_OUT_DATA_OUT_SHIFT (0U) -#define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT) - -/* Bitfield definition for register of struct array DAT: STS */ -/* - * CRC_IDX (RO) - * - * CRC index - */ -#define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL) -#define SEI_DAT_STS_CRC_IDX_SHIFT (24U) -#define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT) - -/* - * WORD_IDX (RO) - * - * Word index - */ -#define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL) -#define SEI_DAT_STS_WORD_IDX_SHIFT (16U) -#define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT) - -/* - * WORD_CNT (RO) - * - * Word counter - */ -#define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U) -#define SEI_DAT_STS_WORD_CNT_SHIFT (8U) -#define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT) - -/* - * BIT_IDX (RO) - * - * Bit index - */ -#define SEI_DAT_STS_BIT_IDX_MASK (0x1FU) -#define SEI_DAT_STS_BIT_IDX_SHIFT (0U) -#define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT) - - - -/* CMD register group index macro definition */ -#define SEI_CTRL_TRG_TABLE_CMD_0 (0UL) -#define SEI_CTRL_TRG_TABLE_CMD_1 (1UL) -#define SEI_CTRL_TRG_TABLE_CMD_2 (2UL) -#define SEI_CTRL_TRG_TABLE_CMD_3 (3UL) - -/* TIME register group index macro definition */ -#define SEI_CTRL_TRG_TABLE_TIME_0 (0UL) -#define SEI_CTRL_TRG_TABLE_TIME_1 (1UL) -#define SEI_CTRL_TRG_TABLE_TIME_2 (2UL) -#define SEI_CTRL_TRG_TABLE_TIME_3 (3UL) - -/* CMD_TABLE register group index macro definition */ -#define SEI_CMD_TABLE_0 (0UL) -#define SEI_CMD_TABLE_1 (1UL) -#define SEI_CMD_TABLE_2 (2UL) -#define SEI_CMD_TABLE_3 (3UL) -#define SEI_CMD_TABLE_4 (4UL) -#define SEI_CMD_TABLE_5 (5UL) -#define SEI_CMD_TABLE_6 (6UL) -#define SEI_CMD_TABLE_7 (7UL) - -/* TRAN register group index macro definition */ -#define SEI_CTRL_LATCH_TRAN_0_1 (0UL) -#define SEI_CTRL_LATCH_TRAN_1_2 (1UL) -#define SEI_CTRL_LATCH_TRAN_2_3 (2UL) -#define SEI_CTRL_LATCH_TRAN_3_0 (3UL) - -/* LATCH register group index macro definition */ -#define SEI_LATCH_0 (0UL) -#define SEI_LATCH_1 (1UL) -#define SEI_LATCH_2 (2UL) -#define SEI_LATCH_3 (3UL) - -/* CTRL register group index macro definition */ -#define SEI_CTRL_0 (0UL) -#define SEI_CTRL_1 (1UL) -#define SEI_CTRL_2 (2UL) -#define SEI_CTRL_3 (3UL) -#define SEI_CTRL_4 (4UL) -#define SEI_CTRL_5 (5UL) -#define SEI_CTRL_6 (6UL) -#define SEI_CTRL_7 (7UL) -#define SEI_CTRL_8 (8UL) -#define SEI_CTRL_9 (9UL) -#define SEI_CTRL_10 (10UL) -#define SEI_CTRL_11 (11UL) -#define SEI_CTRL_12 (12UL) - -/* INSTR register group index macro definition */ -#define SEI_INSTR_0 (0UL) -#define SEI_INSTR_1 (1UL) -#define SEI_INSTR_2 (2UL) -#define SEI_INSTR_3 (3UL) -#define SEI_INSTR_4 (4UL) -#define SEI_INSTR_5 (5UL) -#define SEI_INSTR_6 (6UL) -#define SEI_INSTR_7 (7UL) -#define SEI_INSTR_8 (8UL) -#define SEI_INSTR_9 (9UL) -#define SEI_INSTR_10 (10UL) -#define SEI_INSTR_11 (11UL) -#define SEI_INSTR_12 (12UL) -#define SEI_INSTR_13 (13UL) -#define SEI_INSTR_14 (14UL) -#define SEI_INSTR_15 (15UL) -#define SEI_INSTR_16 (16UL) -#define SEI_INSTR_17 (17UL) -#define SEI_INSTR_18 (18UL) -#define SEI_INSTR_19 (19UL) -#define SEI_INSTR_20 (20UL) -#define SEI_INSTR_21 (21UL) -#define SEI_INSTR_22 (22UL) -#define SEI_INSTR_23 (23UL) -#define SEI_INSTR_24 (24UL) -#define SEI_INSTR_25 (25UL) -#define SEI_INSTR_26 (26UL) -#define SEI_INSTR_27 (27UL) -#define SEI_INSTR_28 (28UL) -#define SEI_INSTR_29 (29UL) -#define SEI_INSTR_30 (30UL) -#define SEI_INSTR_31 (31UL) -#define SEI_INSTR_32 (32UL) -#define SEI_INSTR_33 (33UL) -#define SEI_INSTR_34 (34UL) -#define SEI_INSTR_35 (35UL) -#define SEI_INSTR_36 (36UL) -#define SEI_INSTR_37 (37UL) -#define SEI_INSTR_38 (38UL) -#define SEI_INSTR_39 (39UL) -#define SEI_INSTR_40 (40UL) -#define SEI_INSTR_41 (41UL) -#define SEI_INSTR_42 (42UL) -#define SEI_INSTR_43 (43UL) -#define SEI_INSTR_44 (44UL) -#define SEI_INSTR_45 (45UL) -#define SEI_INSTR_46 (46UL) -#define SEI_INSTR_47 (47UL) -#define SEI_INSTR_48 (48UL) -#define SEI_INSTR_49 (49UL) -#define SEI_INSTR_50 (50UL) -#define SEI_INSTR_51 (51UL) -#define SEI_INSTR_52 (52UL) -#define SEI_INSTR_53 (53UL) -#define SEI_INSTR_54 (54UL) -#define SEI_INSTR_55 (55UL) -#define SEI_INSTR_56 (56UL) -#define SEI_INSTR_57 (57UL) -#define SEI_INSTR_58 (58UL) -#define SEI_INSTR_59 (59UL) -#define SEI_INSTR_60 (60UL) -#define SEI_INSTR_61 (61UL) -#define SEI_INSTR_62 (62UL) -#define SEI_INSTR_63 (63UL) -#define SEI_INSTR_64 (64UL) -#define SEI_INSTR_65 (65UL) -#define SEI_INSTR_66 (66UL) -#define SEI_INSTR_67 (67UL) -#define SEI_INSTR_68 (68UL) -#define SEI_INSTR_69 (69UL) -#define SEI_INSTR_70 (70UL) -#define SEI_INSTR_71 (71UL) -#define SEI_INSTR_72 (72UL) -#define SEI_INSTR_73 (73UL) -#define SEI_INSTR_74 (74UL) -#define SEI_INSTR_75 (75UL) -#define SEI_INSTR_76 (76UL) -#define SEI_INSTR_77 (77UL) -#define SEI_INSTR_78 (78UL) -#define SEI_INSTR_79 (79UL) -#define SEI_INSTR_80 (80UL) -#define SEI_INSTR_81 (81UL) -#define SEI_INSTR_82 (82UL) -#define SEI_INSTR_83 (83UL) -#define SEI_INSTR_84 (84UL) -#define SEI_INSTR_85 (85UL) -#define SEI_INSTR_86 (86UL) -#define SEI_INSTR_87 (87UL) -#define SEI_INSTR_88 (88UL) -#define SEI_INSTR_89 (89UL) -#define SEI_INSTR_90 (90UL) -#define SEI_INSTR_91 (91UL) -#define SEI_INSTR_92 (92UL) -#define SEI_INSTR_93 (93UL) -#define SEI_INSTR_94 (94UL) -#define SEI_INSTR_95 (95UL) -#define SEI_INSTR_96 (96UL) -#define SEI_INSTR_97 (97UL) -#define SEI_INSTR_98 (98UL) -#define SEI_INSTR_99 (99UL) -#define SEI_INSTR_100 (100UL) -#define SEI_INSTR_101 (101UL) -#define SEI_INSTR_102 (102UL) -#define SEI_INSTR_103 (103UL) -#define SEI_INSTR_104 (104UL) -#define SEI_INSTR_105 (105UL) -#define SEI_INSTR_106 (106UL) -#define SEI_INSTR_107 (107UL) -#define SEI_INSTR_108 (108UL) -#define SEI_INSTR_109 (109UL) -#define SEI_INSTR_110 (110UL) -#define SEI_INSTR_111 (111UL) -#define SEI_INSTR_112 (112UL) -#define SEI_INSTR_113 (113UL) -#define SEI_INSTR_114 (114UL) -#define SEI_INSTR_115 (115UL) -#define SEI_INSTR_116 (116UL) -#define SEI_INSTR_117 (117UL) -#define SEI_INSTR_118 (118UL) -#define SEI_INSTR_119 (119UL) -#define SEI_INSTR_120 (120UL) -#define SEI_INSTR_121 (121UL) -#define SEI_INSTR_122 (122UL) -#define SEI_INSTR_123 (123UL) -#define SEI_INSTR_124 (124UL) -#define SEI_INSTR_125 (125UL) -#define SEI_INSTR_126 (126UL) -#define SEI_INSTR_127 (127UL) -#define SEI_INSTR_128 (128UL) -#define SEI_INSTR_129 (129UL) -#define SEI_INSTR_130 (130UL) -#define SEI_INSTR_131 (131UL) -#define SEI_INSTR_132 (132UL) -#define SEI_INSTR_133 (133UL) -#define SEI_INSTR_134 (134UL) -#define SEI_INSTR_135 (135UL) -#define SEI_INSTR_136 (136UL) -#define SEI_INSTR_137 (137UL) -#define SEI_INSTR_138 (138UL) -#define SEI_INSTR_139 (139UL) -#define SEI_INSTR_140 (140UL) -#define SEI_INSTR_141 (141UL) -#define SEI_INSTR_142 (142UL) -#define SEI_INSTR_143 (143UL) -#define SEI_INSTR_144 (144UL) -#define SEI_INSTR_145 (145UL) -#define SEI_INSTR_146 (146UL) -#define SEI_INSTR_147 (147UL) -#define SEI_INSTR_148 (148UL) -#define SEI_INSTR_149 (149UL) -#define SEI_INSTR_150 (150UL) -#define SEI_INSTR_151 (151UL) -#define SEI_INSTR_152 (152UL) -#define SEI_INSTR_153 (153UL) -#define SEI_INSTR_154 (154UL) -#define SEI_INSTR_155 (155UL) -#define SEI_INSTR_156 (156UL) -#define SEI_INSTR_157 (157UL) -#define SEI_INSTR_158 (158UL) -#define SEI_INSTR_159 (159UL) -#define SEI_INSTR_160 (160UL) -#define SEI_INSTR_161 (161UL) -#define SEI_INSTR_162 (162UL) -#define SEI_INSTR_163 (163UL) -#define SEI_INSTR_164 (164UL) -#define SEI_INSTR_165 (165UL) -#define SEI_INSTR_166 (166UL) -#define SEI_INSTR_167 (167UL) -#define SEI_INSTR_168 (168UL) -#define SEI_INSTR_169 (169UL) -#define SEI_INSTR_170 (170UL) -#define SEI_INSTR_171 (171UL) -#define SEI_INSTR_172 (172UL) -#define SEI_INSTR_173 (173UL) -#define SEI_INSTR_174 (174UL) -#define SEI_INSTR_175 (175UL) -#define SEI_INSTR_176 (176UL) -#define SEI_INSTR_177 (177UL) -#define SEI_INSTR_178 (178UL) -#define SEI_INSTR_179 (179UL) -#define SEI_INSTR_180 (180UL) -#define SEI_INSTR_181 (181UL) -#define SEI_INSTR_182 (182UL) -#define SEI_INSTR_183 (183UL) -#define SEI_INSTR_184 (184UL) -#define SEI_INSTR_185 (185UL) -#define SEI_INSTR_186 (186UL) -#define SEI_INSTR_187 (187UL) -#define SEI_INSTR_188 (188UL) -#define SEI_INSTR_189 (189UL) -#define SEI_INSTR_190 (190UL) -#define SEI_INSTR_191 (191UL) -#define SEI_INSTR_192 (192UL) -#define SEI_INSTR_193 (193UL) -#define SEI_INSTR_194 (194UL) -#define SEI_INSTR_195 (195UL) -#define SEI_INSTR_196 (196UL) -#define SEI_INSTR_197 (197UL) -#define SEI_INSTR_198 (198UL) -#define SEI_INSTR_199 (199UL) -#define SEI_INSTR_200 (200UL) -#define SEI_INSTR_201 (201UL) -#define SEI_INSTR_202 (202UL) -#define SEI_INSTR_203 (203UL) -#define SEI_INSTR_204 (204UL) -#define SEI_INSTR_205 (205UL) -#define SEI_INSTR_206 (206UL) -#define SEI_INSTR_207 (207UL) -#define SEI_INSTR_208 (208UL) -#define SEI_INSTR_209 (209UL) -#define SEI_INSTR_210 (210UL) -#define SEI_INSTR_211 (211UL) -#define SEI_INSTR_212 (212UL) -#define SEI_INSTR_213 (213UL) -#define SEI_INSTR_214 (214UL) -#define SEI_INSTR_215 (215UL) -#define SEI_INSTR_216 (216UL) -#define SEI_INSTR_217 (217UL) -#define SEI_INSTR_218 (218UL) -#define SEI_INSTR_219 (219UL) -#define SEI_INSTR_220 (220UL) -#define SEI_INSTR_221 (221UL) -#define SEI_INSTR_222 (222UL) -#define SEI_INSTR_223 (223UL) -#define SEI_INSTR_224 (224UL) -#define SEI_INSTR_225 (225UL) -#define SEI_INSTR_226 (226UL) -#define SEI_INSTR_227 (227UL) -#define SEI_INSTR_228 (228UL) -#define SEI_INSTR_229 (229UL) -#define SEI_INSTR_230 (230UL) -#define SEI_INSTR_231 (231UL) -#define SEI_INSTR_232 (232UL) -#define SEI_INSTR_233 (233UL) -#define SEI_INSTR_234 (234UL) -#define SEI_INSTR_235 (235UL) -#define SEI_INSTR_236 (236UL) -#define SEI_INSTR_237 (237UL) -#define SEI_INSTR_238 (238UL) -#define SEI_INSTR_239 (239UL) -#define SEI_INSTR_240 (240UL) -#define SEI_INSTR_241 (241UL) -#define SEI_INSTR_242 (242UL) -#define SEI_INSTR_243 (243UL) -#define SEI_INSTR_244 (244UL) -#define SEI_INSTR_245 (245UL) -#define SEI_INSTR_246 (246UL) -#define SEI_INSTR_247 (247UL) -#define SEI_INSTR_248 (248UL) -#define SEI_INSTR_249 (249UL) -#define SEI_INSTR_250 (250UL) -#define SEI_INSTR_251 (251UL) -#define SEI_INSTR_252 (252UL) -#define SEI_INSTR_253 (253UL) -#define SEI_INSTR_254 (254UL) -#define SEI_INSTR_255 (255UL) - -/* DAT register group index macro definition */ -#define SEI_DAT_0 (0UL) -#define SEI_DAT_1 (1UL) -#define SEI_DAT_2 (2UL) -#define SEI_DAT_3 (3UL) -#define SEI_DAT_4 (4UL) -#define SEI_DAT_5 (5UL) -#define SEI_DAT_6 (6UL) -#define SEI_DAT_7 (7UL) -#define SEI_DAT_8 (8UL) -#define SEI_DAT_9 (9UL) -#define SEI_DAT_10 (10UL) -#define SEI_DAT_11 (11UL) -#define SEI_DAT_12 (12UL) -#define SEI_DAT_13 (13UL) -#define SEI_DAT_14 (14UL) -#define SEI_DAT_15 (15UL) -#define SEI_DAT_16 (16UL) -#define SEI_DAT_17 (17UL) -#define SEI_DAT_18 (18UL) -#define SEI_DAT_19 (19UL) -#define SEI_DAT_20 (20UL) -#define SEI_DAT_21 (21UL) -#define SEI_DAT_22 (22UL) -#define SEI_DAT_23 (23UL) -#define SEI_DAT_24 (24UL) -#define SEI_DAT_25 (25UL) -#define SEI_DAT_26 (26UL) -#define SEI_DAT_27 (27UL) -#define SEI_DAT_28 (28UL) -#define SEI_DAT_29 (29UL) -#define SEI_DAT_30 (30UL) -#define SEI_DAT_31 (31UL) - - -#endif /* HPM_SEI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_spi_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_spi_regs.h deleted file mode 100644 index 204a3dc9961..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_spi_regs.h +++ /dev/null @@ -1,1034 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SPI_H -#define HPM_SPI_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t WR_TRANS_CNT; /* 0x4: Transfer count for write data */ - __RW uint32_t RD_TRANS_CNT; /* 0x8: Transfer count for read data */ - __R uint8_t RESERVED1[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t TRANSFMT; /* 0x10: Transfer Format Register */ - __RW uint32_t DIRECTIO; /* 0x14: Direct IO Control Register */ - __R uint8_t RESERVED2[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t TRANSCTRL; /* 0x20: Transfer Control Register */ - __RW uint32_t CMD; /* 0x24: Command Register */ - __RW uint32_t ADDR; /* 0x28: Address Register */ - __RW uint32_t DATA; /* 0x2C: Data Register */ - __RW uint32_t CTRL; /* 0x30: Control Register */ - __R uint32_t STATUS; /* 0x34: Status Register */ - __RW uint32_t INTREN; /* 0x38: Interrupt Enable Register */ - __W uint32_t INTRST; /* 0x3C: Interrupt Status Register */ - __RW uint32_t TIMING; /* 0x40: Interface Timing Register */ - __R uint8_t RESERVED3[28]; /* 0x44 - 0x5F: Reserved */ - __RW uint32_t SLVST; /* 0x60: Slave Status Register */ - __R uint32_t SLVDATACNT; /* 0x64: Slave Data Count Register */ - __R uint32_t SLVDATAWCNT; /* 0x68: WCnt */ - __R uint32_t SLVDATARCNT; /* 0x6C: RCnt */ - __R uint8_t RESERVED4[12]; /* 0x70 - 0x7B: Reserved */ - __R uint32_t CONFIG; /* 0x7C: Configuration Register */ -} SPI_Type; - - -/* Bitfield definition for register: WR_TRANS_CNT */ -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_WR_TRANS_CNT_WRTRANCNT_MASK (0xFFFFFFFFUL) -#define SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT (0U) -#define SPI_WR_TRANS_CNT_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) -#define SPI_WR_TRANS_CNT_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_WR_TRANS_CNT_WRTRANCNT_MASK) >> SPI_WR_TRANS_CNT_WRTRANCNT_SHIFT) - -/* Bitfield definition for register: RD_TRANS_CNT */ -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_RD_TRANS_CNT_RDTRANCNT_MASK (0xFFFFFFFFUL) -#define SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT (0U) -#define SPI_RD_TRANS_CNT_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) -#define SPI_RD_TRANS_CNT_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_RD_TRANS_CNT_RDTRANCNT_MASK) >> SPI_RD_TRANS_CNT_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: TRANSFMT */ -/* - * ADDRLEN (RW) - * - * Address length in bytes - * 0x0: 1 byte - * 0x1: 2 bytes - * 0x2: 3 bytes - * 0x3: 4 bytes - */ -#define SPI_TRANSFMT_ADDRLEN_MASK (0x30000UL) -#define SPI_TRANSFMT_ADDRLEN_SHIFT (16U) -#define SPI_TRANSFMT_ADDRLEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_ADDRLEN_SHIFT) & SPI_TRANSFMT_ADDRLEN_MASK) -#define SPI_TRANSFMT_ADDRLEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_ADDRLEN_MASK) >> SPI_TRANSFMT_ADDRLEN_SHIFT) - -/* - * DATALEN (RW) - * - * The length of each data unit in bits - * The actual bit number of a data unit is (DataLen + 1) - */ -#define SPI_TRANSFMT_DATALEN_MASK (0x1F00U) -#define SPI_TRANSFMT_DATALEN_SHIFT (8U) -#define SPI_TRANSFMT_DATALEN_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATALEN_SHIFT) & SPI_TRANSFMT_DATALEN_MASK) -#define SPI_TRANSFMT_DATALEN_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATALEN_MASK) >> SPI_TRANSFMT_DATALEN_SHIFT) - -/* - * DATAMERGE (RW) - * - * Enable Data Merge mode, which does automatic data split on write and data coalescing on read. - * This bit only takes effect when DataLen = 0x7. Under Data Merge mode, each write to the Data Register will transmit all fourbytes of the write data; each read from the Data Register will retrieve four bytes of received data as a single word data. - * When Data Merge mode is disabled, only the least (DataLen+1) significient bits of the Data Register are valid for read/write operations; no automatic data split/coalescing will be performed. - */ -#define SPI_TRANSFMT_DATAMERGE_MASK (0x80U) -#define SPI_TRANSFMT_DATAMERGE_SHIFT (7U) -#define SPI_TRANSFMT_DATAMERGE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_DATAMERGE_SHIFT) & SPI_TRANSFMT_DATAMERGE_MASK) -#define SPI_TRANSFMT_DATAMERGE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_DATAMERGE_MASK) >> SPI_TRANSFMT_DATAMERGE_SHIFT) - -/* - * MOSIBIDIR (RW) - * - * Bi-directional MOSI in regular (single) mode - * 0x0: MOSI is uni-directional signal in regular mode. - * 0x1: MOSI is bi-directional signal in regular mode. This bi-directional signal replaces the two - */ -#define SPI_TRANSFMT_MOSIBIDIR_MASK (0x10U) -#define SPI_TRANSFMT_MOSIBIDIR_SHIFT (4U) -#define SPI_TRANSFMT_MOSIBIDIR_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_MOSIBIDIR_SHIFT) & SPI_TRANSFMT_MOSIBIDIR_MASK) -#define SPI_TRANSFMT_MOSIBIDIR_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_MOSIBIDIR_MASK) >> SPI_TRANSFMT_MOSIBIDIR_SHIFT) - -/* - * LSB (RW) - * - * Transfer data with the least significant bit first - * 0x0: Most significant bit first - * 0x1: Least significant bit first - */ -#define SPI_TRANSFMT_LSB_MASK (0x8U) -#define SPI_TRANSFMT_LSB_SHIFT (3U) -#define SPI_TRANSFMT_LSB_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_LSB_SHIFT) & SPI_TRANSFMT_LSB_MASK) -#define SPI_TRANSFMT_LSB_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_LSB_MASK) >> SPI_TRANSFMT_LSB_SHIFT) - -/* - * SLVMODE (RW) - * - * SPI Master/Slave mode selection - * 0x0: Master mode - * 0x1: Slave mode - */ -#define SPI_TRANSFMT_SLVMODE_MASK (0x4U) -#define SPI_TRANSFMT_SLVMODE_SHIFT (2U) -#define SPI_TRANSFMT_SLVMODE_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_SLVMODE_SHIFT) & SPI_TRANSFMT_SLVMODE_MASK) -#define SPI_TRANSFMT_SLVMODE_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_SLVMODE_MASK) >> SPI_TRANSFMT_SLVMODE_SHIFT) - -/* - * CPOL (RW) - * - * SPI Clock Polarity - * 0x0: SCLK is LOW in the idle states - * 0x1: SCLK is HIGH in the idle states - */ -#define SPI_TRANSFMT_CPOL_MASK (0x2U) -#define SPI_TRANSFMT_CPOL_SHIFT (1U) -#define SPI_TRANSFMT_CPOL_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPOL_SHIFT) & SPI_TRANSFMT_CPOL_MASK) -#define SPI_TRANSFMT_CPOL_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPOL_MASK) >> SPI_TRANSFMT_CPOL_SHIFT) - -/* - * CPHA (RW) - * - * SPI Clock Phase - * 0x0: Sampling data at odd SCLK edges - * 0x1: Sampling data at even SCLK edges - */ -#define SPI_TRANSFMT_CPHA_MASK (0x1U) -#define SPI_TRANSFMT_CPHA_SHIFT (0U) -#define SPI_TRANSFMT_CPHA_SET(x) (((uint32_t)(x) << SPI_TRANSFMT_CPHA_SHIFT) & SPI_TRANSFMT_CPHA_MASK) -#define SPI_TRANSFMT_CPHA_GET(x) (((uint32_t)(x) & SPI_TRANSFMT_CPHA_MASK) >> SPI_TRANSFMT_CPHA_SHIFT) - -/* Bitfield definition for register: DIRECTIO */ -/* - * DIRECTIOEN (RW) - * - * Enable Direct IO - * 0x0: Disable - * 0x1: Enable - */ -#define SPI_DIRECTIO_DIRECTIOEN_MASK (0x1000000UL) -#define SPI_DIRECTIO_DIRECTIOEN_SHIFT (24U) -#define SPI_DIRECTIO_DIRECTIOEN_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_DIRECTIOEN_SHIFT) & SPI_DIRECTIO_DIRECTIOEN_MASK) -#define SPI_DIRECTIO_DIRECTIOEN_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_DIRECTIOEN_MASK) >> SPI_DIRECTIO_DIRECTIOEN_SHIFT) - -/* - * HOLD_OE (RW) - * - * Output enable for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_OE_MASK (0x200000UL) -#define SPI_DIRECTIO_HOLD_OE_SHIFT (21U) -#define SPI_DIRECTIO_HOLD_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_OE_SHIFT) & SPI_DIRECTIO_HOLD_OE_MASK) -#define SPI_DIRECTIO_HOLD_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_OE_MASK) >> SPI_DIRECTIO_HOLD_OE_SHIFT) - -/* - * WP_OE (RW) - * - * Output enable for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_OE_MASK (0x100000UL) -#define SPI_DIRECTIO_WP_OE_SHIFT (20U) -#define SPI_DIRECTIO_WP_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_OE_SHIFT) & SPI_DIRECTIO_WP_OE_MASK) -#define SPI_DIRECTIO_WP_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_OE_MASK) >> SPI_DIRECTIO_WP_OE_SHIFT) - -/* - * MISO_OE (RW) - * - * Output enable fo the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_OE_MASK (0x80000UL) -#define SPI_DIRECTIO_MISO_OE_SHIFT (19U) -#define SPI_DIRECTIO_MISO_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_OE_SHIFT) & SPI_DIRECTIO_MISO_OE_MASK) -#define SPI_DIRECTIO_MISO_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_OE_MASK) >> SPI_DIRECTIO_MISO_OE_SHIFT) - -/* - * MOSI_OE (RW) - * - * Output enable for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_OE_MASK (0x40000UL) -#define SPI_DIRECTIO_MOSI_OE_SHIFT (18U) -#define SPI_DIRECTIO_MOSI_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_OE_SHIFT) & SPI_DIRECTIO_MOSI_OE_MASK) -#define SPI_DIRECTIO_MOSI_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_OE_MASK) >> SPI_DIRECTIO_MOSI_OE_SHIFT) - -/* - * SCLK_OE (RW) - * - * Output enable for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_OE_MASK (0x20000UL) -#define SPI_DIRECTIO_SCLK_OE_SHIFT (17U) -#define SPI_DIRECTIO_SCLK_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_OE_SHIFT) & SPI_DIRECTIO_SCLK_OE_MASK) -#define SPI_DIRECTIO_SCLK_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_OE_MASK) >> SPI_DIRECTIO_SCLK_OE_SHIFT) - -/* - * CS_OE (RW) - * - * Output enable for SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_OE_MASK (0x10000UL) -#define SPI_DIRECTIO_CS_OE_SHIFT (16U) -#define SPI_DIRECTIO_CS_OE_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_OE_SHIFT) & SPI_DIRECTIO_CS_OE_MASK) -#define SPI_DIRECTIO_CS_OE_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_OE_MASK) >> SPI_DIRECTIO_CS_OE_SHIFT) - -/* - * HOLD_O (RW) - * - * Output value for the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_O_MASK (0x2000U) -#define SPI_DIRECTIO_HOLD_O_SHIFT (13U) -#define SPI_DIRECTIO_HOLD_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_HOLD_O_SHIFT) & SPI_DIRECTIO_HOLD_O_MASK) -#define SPI_DIRECTIO_HOLD_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_O_MASK) >> SPI_DIRECTIO_HOLD_O_SHIFT) - -/* - * WP_O (RW) - * - * Output value for the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_O_MASK (0x1000U) -#define SPI_DIRECTIO_WP_O_SHIFT (12U) -#define SPI_DIRECTIO_WP_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_WP_O_SHIFT) & SPI_DIRECTIO_WP_O_MASK) -#define SPI_DIRECTIO_WP_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_O_MASK) >> SPI_DIRECTIO_WP_O_SHIFT) - -/* - * MISO_O (RW) - * - * Output value for the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_O_MASK (0x800U) -#define SPI_DIRECTIO_MISO_O_SHIFT (11U) -#define SPI_DIRECTIO_MISO_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MISO_O_SHIFT) & SPI_DIRECTIO_MISO_O_MASK) -#define SPI_DIRECTIO_MISO_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_O_MASK) >> SPI_DIRECTIO_MISO_O_SHIFT) - -/* - * MOSI_O (RW) - * - * Output value for the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_O_MASK (0x400U) -#define SPI_DIRECTIO_MOSI_O_SHIFT (10U) -#define SPI_DIRECTIO_MOSI_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_MOSI_O_SHIFT) & SPI_DIRECTIO_MOSI_O_MASK) -#define SPI_DIRECTIO_MOSI_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_O_MASK) >> SPI_DIRECTIO_MOSI_O_SHIFT) - -/* - * SCLK_O (RW) - * - * Output value for the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_O_MASK (0x200U) -#define SPI_DIRECTIO_SCLK_O_SHIFT (9U) -#define SPI_DIRECTIO_SCLK_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_SCLK_O_SHIFT) & SPI_DIRECTIO_SCLK_O_MASK) -#define SPI_DIRECTIO_SCLK_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_O_MASK) >> SPI_DIRECTIO_SCLK_O_SHIFT) - -/* - * CS_O (RW) - * - * Output value for the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_O_MASK (0x100U) -#define SPI_DIRECTIO_CS_O_SHIFT (8U) -#define SPI_DIRECTIO_CS_O_SET(x) (((uint32_t)(x) << SPI_DIRECTIO_CS_O_SHIFT) & SPI_DIRECTIO_CS_O_MASK) -#define SPI_DIRECTIO_CS_O_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_O_MASK) >> SPI_DIRECTIO_CS_O_SHIFT) - -/* - * HOLD_I (RO) - * - * Status of the SPI Flash hold signal - */ -#define SPI_DIRECTIO_HOLD_I_MASK (0x20U) -#define SPI_DIRECTIO_HOLD_I_SHIFT (5U) -#define SPI_DIRECTIO_HOLD_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_HOLD_I_MASK) >> SPI_DIRECTIO_HOLD_I_SHIFT) - -/* - * WP_I (RO) - * - * Status of the SPI Flash write protect signal - */ -#define SPI_DIRECTIO_WP_I_MASK (0x10U) -#define SPI_DIRECTIO_WP_I_SHIFT (4U) -#define SPI_DIRECTIO_WP_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_WP_I_MASK) >> SPI_DIRECTIO_WP_I_SHIFT) - -/* - * MISO_I (RO) - * - * Status of the SPI MISO signal - */ -#define SPI_DIRECTIO_MISO_I_MASK (0x8U) -#define SPI_DIRECTIO_MISO_I_SHIFT (3U) -#define SPI_DIRECTIO_MISO_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MISO_I_MASK) >> SPI_DIRECTIO_MISO_I_SHIFT) - -/* - * MOSI_I (RO) - * - * Status of the SPI MOSI signal - */ -#define SPI_DIRECTIO_MOSI_I_MASK (0x4U) -#define SPI_DIRECTIO_MOSI_I_SHIFT (2U) -#define SPI_DIRECTIO_MOSI_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_MOSI_I_MASK) >> SPI_DIRECTIO_MOSI_I_SHIFT) - -/* - * SCLK_I (RO) - * - * Status of the SPI SCLK signal - */ -#define SPI_DIRECTIO_SCLK_I_MASK (0x2U) -#define SPI_DIRECTIO_SCLK_I_SHIFT (1U) -#define SPI_DIRECTIO_SCLK_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_SCLK_I_MASK) >> SPI_DIRECTIO_SCLK_I_SHIFT) - -/* - * CS_I (RO) - * - * Status of the SPI CS (chip select) signal - */ -#define SPI_DIRECTIO_CS_I_MASK (0x1U) -#define SPI_DIRECTIO_CS_I_SHIFT (0U) -#define SPI_DIRECTIO_CS_I_GET(x) (((uint32_t)(x) & SPI_DIRECTIO_CS_I_MASK) >> SPI_DIRECTIO_CS_I_SHIFT) - -/* Bitfield definition for register: TRANSCTRL */ -/* - * SLVDATAONLY (RW) - * - * Data-only mode (slave mode only) - * 0x0: Disable the data-only mode - * 0x1: Enable the data-only mode - * Note: This mode only works in the uni-directional regular (single) mode so MOSIBiDir, DualQuad and TransMode should be set to 0. - */ -#define SPI_TRANSCTRL_SLVDATAONLY_MASK (0x80000000UL) -#define SPI_TRANSCTRL_SLVDATAONLY_SHIFT (31U) -#define SPI_TRANSCTRL_SLVDATAONLY_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_SLVDATAONLY_SHIFT) & SPI_TRANSCTRL_SLVDATAONLY_MASK) -#define SPI_TRANSCTRL_SLVDATAONLY_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_SLVDATAONLY_MASK) >> SPI_TRANSCTRL_SLVDATAONLY_SHIFT) - -/* - * CMDEN (RW) - * - * SPI command phase enable (Master mode only) - * 0x0: Disable the command phase - * 0x1: Enable the command phase - */ -#define SPI_TRANSCTRL_CMDEN_MASK (0x40000000UL) -#define SPI_TRANSCTRL_CMDEN_SHIFT (30U) -#define SPI_TRANSCTRL_CMDEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_CMDEN_SHIFT) & SPI_TRANSCTRL_CMDEN_MASK) -#define SPI_TRANSCTRL_CMDEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_CMDEN_MASK) >> SPI_TRANSCTRL_CMDEN_SHIFT) - -/* - * ADDREN (RW) - * - * SPI address phase enable (Master mode only) - * 0x0: Disable the address phase - * 0x1: Enable the address phase - */ -#define SPI_TRANSCTRL_ADDREN_MASK (0x20000000UL) -#define SPI_TRANSCTRL_ADDREN_SHIFT (29U) -#define SPI_TRANSCTRL_ADDREN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDREN_SHIFT) & SPI_TRANSCTRL_ADDREN_MASK) -#define SPI_TRANSCTRL_ADDREN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDREN_MASK) >> SPI_TRANSCTRL_ADDREN_SHIFT) - -/* - * ADDRFMT (RW) - * - * SPI address phase format (Master mode only) - * 0x0: Address phase is the regular (single) mode - * 0x1: The format of the address phase is the same as the data phase (DualQuad). - */ -#define SPI_TRANSCTRL_ADDRFMT_MASK (0x10000000UL) -#define SPI_TRANSCTRL_ADDRFMT_SHIFT (28U) -#define SPI_TRANSCTRL_ADDRFMT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_ADDRFMT_SHIFT) & SPI_TRANSCTRL_ADDRFMT_MASK) -#define SPI_TRANSCTRL_ADDRFMT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_ADDRFMT_MASK) >> SPI_TRANSCTRL_ADDRFMT_SHIFT) - -/* - * TRANSMODE (RW) - * - * Transfer mode - * The transfer sequence could be - * 0x0: Write and read at the same time - * 0x1: Write only - * 0x2: Read only - * 0x3: Write, Read - * 0x4: Read, Write - * 0x5: Write, Dummy, Read - * 0x6: Read, Dummy, Write - * 0x7: None Data (must enable CmdEn or AddrEn in master mode) - * 0x8: Dummy, Write - * 0x9: Dummy, Read - * 0xa~0xf: Reserved - */ -#define SPI_TRANSCTRL_TRANSMODE_MASK (0xF000000UL) -#define SPI_TRANSCTRL_TRANSMODE_SHIFT (24U) -#define SPI_TRANSCTRL_TRANSMODE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TRANSMODE_SHIFT) & SPI_TRANSCTRL_TRANSMODE_MASK) -#define SPI_TRANSCTRL_TRANSMODE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TRANSMODE_MASK) >> SPI_TRANSCTRL_TRANSMODE_SHIFT) - -/* - * DUALQUAD (RW) - * - * SPI data phase format - * 0x0: Regular (Single) mode - * 0x1: Dual I/O mode - * 0x2: Quad I/O mode - * 0x3: Reserved - */ -#define SPI_TRANSCTRL_DUALQUAD_MASK (0xC00000UL) -#define SPI_TRANSCTRL_DUALQUAD_SHIFT (22U) -#define SPI_TRANSCTRL_DUALQUAD_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUALQUAD_SHIFT) & SPI_TRANSCTRL_DUALQUAD_MASK) -#define SPI_TRANSCTRL_DUALQUAD_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUALQUAD_MASK) >> SPI_TRANSCTRL_DUALQUAD_SHIFT) - -/* - * TOKENEN (RW) - * - * Token transfer enable (Master mode only) - * Append a one-byte special token following the address phase for SPI read transfers. The value of the special token should be selected in TokenValue. - * 0x0: Disable the one-byte special token - * 0x1: Enable the one-byte special token - */ -#define SPI_TRANSCTRL_TOKENEN_MASK (0x200000UL) -#define SPI_TRANSCTRL_TOKENEN_SHIFT (21U) -#define SPI_TRANSCTRL_TOKENEN_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENEN_SHIFT) & SPI_TRANSCTRL_TOKENEN_MASK) -#define SPI_TRANSCTRL_TOKENEN_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENEN_MASK) >> SPI_TRANSCTRL_TOKENEN_SHIFT) - -/* - * WRTRANCNT (RW) - * - * Transfer count for write data - * WrTranCnt indicates the number of units of data to be transmitted to the SPI bus from the Data Register. The actual transfer count is (WrTranCnt+1). - * WrTranCnt only takes effect when TransMode is 0, 1, 3, 4, 5, 6 or 8. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must be equal to RdTranCnt. - */ -#define SPI_TRANSCTRL_WRTRANCNT_MASK (0x1FF000UL) -#define SPI_TRANSCTRL_WRTRANCNT_SHIFT (12U) -#define SPI_TRANSCTRL_WRTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_WRTRANCNT_SHIFT) & SPI_TRANSCTRL_WRTRANCNT_MASK) -#define SPI_TRANSCTRL_WRTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_WRTRANCNT_MASK) >> SPI_TRANSCTRL_WRTRANCNT_SHIFT) - -/* - * TOKENVALUE (RW) - * - * Token value (Master mode only) - * The value of the one-byte special token following the address phase for SPI read transfers. - * 0x0: token value = 0x00 - * 0x1: token value = 0x69 - */ -#define SPI_TRANSCTRL_TOKENVALUE_MASK (0x800U) -#define SPI_TRANSCTRL_TOKENVALUE_SHIFT (11U) -#define SPI_TRANSCTRL_TOKENVALUE_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_TOKENVALUE_SHIFT) & SPI_TRANSCTRL_TOKENVALUE_MASK) -#define SPI_TRANSCTRL_TOKENVALUE_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_TOKENVALUE_MASK) >> SPI_TRANSCTRL_TOKENVALUE_SHIFT) - -/* - * DUMMYCNT (RW) - * - * Dummy data count. The actual dummy count is (DummyCnt +1). - * The number of dummy cycles on the SPI interface will be (DummyCnt+1)* ((DataLen+1)/SPI IO width) - * The Data pins are put into the high impedance during the dummy data phase. - * DummyCnt is only used for TransMode 5, 6, 8 and 9, which has dummy data phases. - */ -#define SPI_TRANSCTRL_DUMMYCNT_MASK (0x600U) -#define SPI_TRANSCTRL_DUMMYCNT_SHIFT (9U) -#define SPI_TRANSCTRL_DUMMYCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_DUMMYCNT_SHIFT) & SPI_TRANSCTRL_DUMMYCNT_MASK) -#define SPI_TRANSCTRL_DUMMYCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_DUMMYCNT_MASK) >> SPI_TRANSCTRL_DUMMYCNT_SHIFT) - -/* - * RDTRANCNT (RW) - * - * Transfer count for read data - * RdTranCnt indicates the number of units of data to be received from SPI bus and stored to the Data Register. The actual received count is (RdTranCnt+1). - * RdTransCnt only takes effect when TransMode is 0, 2, 3, 4, 5, 6 or 9. - * The size (bit-width) of a data unit is defined by the DataLen field of the Transfer Format Register. - * For TransMode 0, WrTranCnt must equal RdTranCnt. - */ -#define SPI_TRANSCTRL_RDTRANCNT_MASK (0x1FFU) -#define SPI_TRANSCTRL_RDTRANCNT_SHIFT (0U) -#define SPI_TRANSCTRL_RDTRANCNT_SET(x) (((uint32_t)(x) << SPI_TRANSCTRL_RDTRANCNT_SHIFT) & SPI_TRANSCTRL_RDTRANCNT_MASK) -#define SPI_TRANSCTRL_RDTRANCNT_GET(x) (((uint32_t)(x) & SPI_TRANSCTRL_RDTRANCNT_MASK) >> SPI_TRANSCTRL_RDTRANCNT_SHIFT) - -/* Bitfield definition for register: CMD */ -/* - * CMD (RW) - * - * SPI Command - */ -#define SPI_CMD_CMD_MASK (0xFFU) -#define SPI_CMD_CMD_SHIFT (0U) -#define SPI_CMD_CMD_SET(x) (((uint32_t)(x) << SPI_CMD_CMD_SHIFT) & SPI_CMD_CMD_MASK) -#define SPI_CMD_CMD_GET(x) (((uint32_t)(x) & SPI_CMD_CMD_MASK) >> SPI_CMD_CMD_SHIFT) - -/* Bitfield definition for register: ADDR */ -/* - * ADDR (RW) - * - * SPI Address - * (Master mode only) - */ -#define SPI_ADDR_ADDR_MASK (0xFFFFFFFFUL) -#define SPI_ADDR_ADDR_SHIFT (0U) -#define SPI_ADDR_ADDR_SET(x) (((uint32_t)(x) << SPI_ADDR_ADDR_SHIFT) & SPI_ADDR_ADDR_MASK) -#define SPI_ADDR_ADDR_GET(x) (((uint32_t)(x) & SPI_ADDR_ADDR_MASK) >> SPI_ADDR_ADDR_SHIFT) - -/* Bitfield definition for register: DATA */ -/* - * DATA (RW) - * - * Data to transmit or the received data - * For writes, data is enqueued to the TX FIFO. The least significant byte is always transmitted first. If the TX FIFO is full and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * For reads, data is read and dequeued from the RX FIFO. The least significant byte is the first received byte. If the RX FIFO is empty and the SPIActive bit of the status register is 1, the ready signal hready/pready will be deasserted to insert wait states to the transfer. - * The FIFOs decouple the speed of the SPI transfers and the software鈥檚 generation/consumption of data. When the TX FIFO is empty, SPI transfers will hold until more data is written to the TX FIFO; when the RX FIFO is full, SPI transfers will hold until there is more room in the RX FIFO. - * If more data is written to the TX FIFO than the write transfer count (WrTranCnt), the remaining data will stay in the TX FIFO for the next transfer or until the TX FIFO is reset. - */ -#define SPI_DATA_DATA_MASK (0xFFFFFFFFUL) -#define SPI_DATA_DATA_SHIFT (0U) -#define SPI_DATA_DATA_SET(x) (((uint32_t)(x) << SPI_DATA_DATA_SHIFT) & SPI_DATA_DATA_MASK) -#define SPI_DATA_DATA_GET(x) (((uint32_t)(x) & SPI_DATA_DATA_MASK) >> SPI_DATA_DATA_SHIFT) - -/* Bitfield definition for register: CTRL */ -/* - * CS_EN (RW) - * - */ -#define SPI_CTRL_CS_EN_MASK (0xF000000UL) -#define SPI_CTRL_CS_EN_SHIFT (24U) -#define SPI_CTRL_CS_EN_SET(x) (((uint32_t)(x) << SPI_CTRL_CS_EN_SHIFT) & SPI_CTRL_CS_EN_MASK) -#define SPI_CTRL_CS_EN_GET(x) (((uint32_t)(x) & SPI_CTRL_CS_EN_MASK) >> SPI_CTRL_CS_EN_SHIFT) - -/* - * TXTHRES (RW) - * - * Transmit (TX) FIFO Threshold - * The TXFIFOInt interrupt or DMA request would be issued to replenish the TX FIFO when the TX data count is less than or equal to the TX FIFO threshold. - */ -#define SPI_CTRL_TXTHRES_MASK (0xFF0000UL) -#define SPI_CTRL_TXTHRES_SHIFT (16U) -#define SPI_CTRL_TXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_TXTHRES_SHIFT) & SPI_CTRL_TXTHRES_MASK) -#define SPI_CTRL_TXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_TXTHRES_MASK) >> SPI_CTRL_TXTHRES_SHIFT) - -/* - * RXTHRES (RW) - * - * Receive (RX) FIFO Threshold - * The RXFIFOInt interrupt or DMA request would be issued for consuming the RX FIFO when the RX data count is more than or equal to the RX FIFO threshold. - */ -#define SPI_CTRL_RXTHRES_MASK (0xFF00U) -#define SPI_CTRL_RXTHRES_SHIFT (8U) -#define SPI_CTRL_RXTHRES_SET(x) (((uint32_t)(x) << SPI_CTRL_RXTHRES_SHIFT) & SPI_CTRL_RXTHRES_MASK) -#define SPI_CTRL_RXTHRES_GET(x) (((uint32_t)(x) & SPI_CTRL_RXTHRES_MASK) >> SPI_CTRL_RXTHRES_SHIFT) - -/* - * TXDMAEN (RW) - * - * TX DMA enable - */ -#define SPI_CTRL_TXDMAEN_MASK (0x10U) -#define SPI_CTRL_TXDMAEN_SHIFT (4U) -#define SPI_CTRL_TXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_TXDMAEN_SHIFT) & SPI_CTRL_TXDMAEN_MASK) -#define SPI_CTRL_TXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_TXDMAEN_MASK) >> SPI_CTRL_TXDMAEN_SHIFT) - -/* - * RXDMAEN (RW) - * - * RX DMA enable - */ -#define SPI_CTRL_RXDMAEN_MASK (0x8U) -#define SPI_CTRL_RXDMAEN_SHIFT (3U) -#define SPI_CTRL_RXDMAEN_SET(x) (((uint32_t)(x) << SPI_CTRL_RXDMAEN_SHIFT) & SPI_CTRL_RXDMAEN_MASK) -#define SPI_CTRL_RXDMAEN_GET(x) (((uint32_t)(x) & SPI_CTRL_RXDMAEN_MASK) >> SPI_CTRL_RXDMAEN_SHIFT) - -/* - * TXFIFORST (RW) - * - * Transmit FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_TXFIFORST_MASK (0x4U) -#define SPI_CTRL_TXFIFORST_SHIFT (2U) -#define SPI_CTRL_TXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_TXFIFORST_SHIFT) & SPI_CTRL_TXFIFORST_MASK) -#define SPI_CTRL_TXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_TXFIFORST_MASK) >> SPI_CTRL_TXFIFORST_SHIFT) - -/* - * RXFIFORST (RW) - * - * Receive FIFO reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_RXFIFORST_MASK (0x2U) -#define SPI_CTRL_RXFIFORST_SHIFT (1U) -#define SPI_CTRL_RXFIFORST_SET(x) (((uint32_t)(x) << SPI_CTRL_RXFIFORST_SHIFT) & SPI_CTRL_RXFIFORST_MASK) -#define SPI_CTRL_RXFIFORST_GET(x) (((uint32_t)(x) & SPI_CTRL_RXFIFORST_MASK) >> SPI_CTRL_RXFIFORST_SHIFT) - -/* - * SPIRST (RW) - * - * SPI reset - * Write 1 to reset. It is automatically cleared to 0 after the reset operation completes. - */ -#define SPI_CTRL_SPIRST_MASK (0x1U) -#define SPI_CTRL_SPIRST_SHIFT (0U) -#define SPI_CTRL_SPIRST_SET(x) (((uint32_t)(x) << SPI_CTRL_SPIRST_SHIFT) & SPI_CTRL_SPIRST_MASK) -#define SPI_CTRL_SPIRST_GET(x) (((uint32_t)(x) & SPI_CTRL_SPIRST_MASK) >> SPI_CTRL_SPIRST_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * TXNUM_7_6 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_7_6_MASK (0x30000000UL) -#define SPI_STATUS_TXNUM_7_6_SHIFT (28U) -#define SPI_STATUS_TXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_7_6_MASK) >> SPI_STATUS_TXNUM_7_6_SHIFT) - -/* - * RXNUM_7_6 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_7_6_MASK (0x3000000UL) -#define SPI_STATUS_RXNUM_7_6_SHIFT (24U) -#define SPI_STATUS_RXNUM_7_6_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_7_6_MASK) >> SPI_STATUS_RXNUM_7_6_SHIFT) - -/* - * TXFULL (RO) - * - * Transmit FIFO Full flag - */ -#define SPI_STATUS_TXFULL_MASK (0x800000UL) -#define SPI_STATUS_TXFULL_SHIFT (23U) -#define SPI_STATUS_TXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_TXFULL_MASK) >> SPI_STATUS_TXFULL_SHIFT) - -/* - * TXEMPTY (RO) - * - * Transmit FIFO Empty flag - */ -#define SPI_STATUS_TXEMPTY_MASK (0x400000UL) -#define SPI_STATUS_TXEMPTY_SHIFT (22U) -#define SPI_STATUS_TXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_TXEMPTY_MASK) >> SPI_STATUS_TXEMPTY_SHIFT) - -/* - * TXNUM_5_0 (RO) - * - * Number of valid entries in the Transmit FIFO - */ -#define SPI_STATUS_TXNUM_5_0_MASK (0x3F0000UL) -#define SPI_STATUS_TXNUM_5_0_SHIFT (16U) -#define SPI_STATUS_TXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_TXNUM_5_0_MASK) >> SPI_STATUS_TXNUM_5_0_SHIFT) - -/* - * RXFULL (RO) - * - * Receive FIFO Full flag - */ -#define SPI_STATUS_RXFULL_MASK (0x8000U) -#define SPI_STATUS_RXFULL_SHIFT (15U) -#define SPI_STATUS_RXFULL_GET(x) (((uint32_t)(x) & SPI_STATUS_RXFULL_MASK) >> SPI_STATUS_RXFULL_SHIFT) - -/* - * RXEMPTY (RO) - * - * Receive FIFO Empty flag - */ -#define SPI_STATUS_RXEMPTY_MASK (0x4000U) -#define SPI_STATUS_RXEMPTY_SHIFT (14U) -#define SPI_STATUS_RXEMPTY_GET(x) (((uint32_t)(x) & SPI_STATUS_RXEMPTY_MASK) >> SPI_STATUS_RXEMPTY_SHIFT) - -/* - * RXNUM_5_0 (RO) - * - * Number of valid entries in the Receive FIFO - */ -#define SPI_STATUS_RXNUM_5_0_MASK (0x3F00U) -#define SPI_STATUS_RXNUM_5_0_SHIFT (8U) -#define SPI_STATUS_RXNUM_5_0_GET(x) (((uint32_t)(x) & SPI_STATUS_RXNUM_5_0_MASK) >> SPI_STATUS_RXNUM_5_0_SHIFT) - -/* - * SPIACTIVE (RO) - * - * SPI register programming is in progress. - * In master mode, SPIActive becomes 1 after the SPI command register is written and becomes 0 after the transfer is finished. - * In slave mode, SPIActive becomes 1 after the SPI CS signal is asserted and becomes 0 after the SPI CS signal is deasserted. - * Note that due to clock synchronization, it may take at most two spi_clock cycles for SPIActive to change when the corresponding condition happens. - * Note this bit stays 0 when Direct IO Control or the memory-mapped interface is used. - */ -#define SPI_STATUS_SPIACTIVE_MASK (0x1U) -#define SPI_STATUS_SPIACTIVE_SHIFT (0U) -#define SPI_STATUS_SPIACTIVE_GET(x) (((uint32_t)(x) & SPI_STATUS_SPIACTIVE_MASK) >> SPI_STATUS_SPIACTIVE_SHIFT) - -/* Bitfield definition for register: INTREN */ -/* - * SLVCMDEN (RW) - * - * Enable the Slave Command Interrupt. - * Control whether interrupts are triggered whenever slave commands are received. - * (Slave mode only) - */ -#define SPI_INTREN_SLVCMDEN_MASK (0x20U) -#define SPI_INTREN_SLVCMDEN_SHIFT (5U) -#define SPI_INTREN_SLVCMDEN_SET(x) (((uint32_t)(x) << SPI_INTREN_SLVCMDEN_SHIFT) & SPI_INTREN_SLVCMDEN_MASK) -#define SPI_INTREN_SLVCMDEN_GET(x) (((uint32_t)(x) & SPI_INTREN_SLVCMDEN_MASK) >> SPI_INTREN_SLVCMDEN_SHIFT) - -/* - * ENDINTEN (RW) - * - * Enable the End of SPI Transfer interrupt. - * Control whether interrupts are triggered when SPI transfers end. - * (In slave mode, end of read status transaction doesn鈥檛 trigger this interrupt.) - */ -#define SPI_INTREN_ENDINTEN_MASK (0x10U) -#define SPI_INTREN_ENDINTEN_SHIFT (4U) -#define SPI_INTREN_ENDINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_ENDINTEN_SHIFT) & SPI_INTREN_ENDINTEN_MASK) -#define SPI_INTREN_ENDINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_ENDINTEN_MASK) >> SPI_INTREN_ENDINTEN_SHIFT) - -/* - * TXFIFOINTEN (RW) - * - * Enable the SPI Transmit FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are less than or equal to the TX FIFO threshold. - */ -#define SPI_INTREN_TXFIFOINTEN_MASK (0x8U) -#define SPI_INTREN_TXFIFOINTEN_SHIFT (3U) -#define SPI_INTREN_TXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOINTEN_SHIFT) & SPI_INTREN_TXFIFOINTEN_MASK) -#define SPI_INTREN_TXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOINTEN_MASK) >> SPI_INTREN_TXFIFOINTEN_SHIFT) - -/* - * RXFIFOINTEN (RW) - * - * Enable the SPI Receive FIFO Threshold interrupt. - * Control whether interrupts are triggered when the valid entries are greater than or equal to the RX FIFO threshold. - */ -#define SPI_INTREN_RXFIFOINTEN_MASK (0x4U) -#define SPI_INTREN_RXFIFOINTEN_SHIFT (2U) -#define SPI_INTREN_RXFIFOINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOINTEN_SHIFT) & SPI_INTREN_RXFIFOINTEN_MASK) -#define SPI_INTREN_RXFIFOINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOINTEN_MASK) >> SPI_INTREN_RXFIFOINTEN_SHIFT) - -/* - * TXFIFOURINTEN (RW) - * - * Enable the SPI Transmit FIFO Underrun interrupt. - * Control whether interrupts are triggered when the Transmit FIFO run out of data. - * (Slave mode only) - */ -#define SPI_INTREN_TXFIFOURINTEN_MASK (0x2U) -#define SPI_INTREN_TXFIFOURINTEN_SHIFT (1U) -#define SPI_INTREN_TXFIFOURINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_TXFIFOURINTEN_SHIFT) & SPI_INTREN_TXFIFOURINTEN_MASK) -#define SPI_INTREN_TXFIFOURINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_TXFIFOURINTEN_MASK) >> SPI_INTREN_TXFIFOURINTEN_SHIFT) - -/* - * RXFIFOORINTEN (RW) - * - * Enable the SPI Receive FIFO Overrun interrupt. - * Control whether interrupts are triggered when the Receive FIFO overflows. - * (Slave mode only) - */ -#define SPI_INTREN_RXFIFOORINTEN_MASK (0x1U) -#define SPI_INTREN_RXFIFOORINTEN_SHIFT (0U) -#define SPI_INTREN_RXFIFOORINTEN_SET(x) (((uint32_t)(x) << SPI_INTREN_RXFIFOORINTEN_SHIFT) & SPI_INTREN_RXFIFOORINTEN_MASK) -#define SPI_INTREN_RXFIFOORINTEN_GET(x) (((uint32_t)(x) & SPI_INTREN_RXFIFOORINTEN_MASK) >> SPI_INTREN_RXFIFOORINTEN_SHIFT) - -/* Bitfield definition for register: INTRST */ -/* - * SLVCMDINT (W1C) - * - * Slave Command Interrupt. - * This bit is set when Slave Command interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_SLVCMDINT_MASK (0x20U) -#define SPI_INTRST_SLVCMDINT_SHIFT (5U) -#define SPI_INTRST_SLVCMDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_SLVCMDINT_SHIFT) & SPI_INTRST_SLVCMDINT_MASK) -#define SPI_INTRST_SLVCMDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_SLVCMDINT_MASK) >> SPI_INTRST_SLVCMDINT_SHIFT) - -/* - * ENDINT (W1C) - * - * End of SPI Transfer interrupt. - * This bit is set when End of SPI Transfer interrupts occur. - */ -#define SPI_INTRST_ENDINT_MASK (0x10U) -#define SPI_INTRST_ENDINT_SHIFT (4U) -#define SPI_INTRST_ENDINT_SET(x) (((uint32_t)(x) << SPI_INTRST_ENDINT_SHIFT) & SPI_INTRST_ENDINT_MASK) -#define SPI_INTRST_ENDINT_GET(x) (((uint32_t)(x) & SPI_INTRST_ENDINT_MASK) >> SPI_INTRST_ENDINT_SHIFT) - -/* - * TXFIFOINT (W1C) - * - * TX FIFO Threshold interrupt. - * This bit is set when TX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_TXFIFOINT_MASK (0x8U) -#define SPI_INTRST_TXFIFOINT_SHIFT (3U) -#define SPI_INTRST_TXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOINT_SHIFT) & SPI_INTRST_TXFIFOINT_MASK) -#define SPI_INTRST_TXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOINT_MASK) >> SPI_INTRST_TXFIFOINT_SHIFT) - -/* - * RXFIFOINT (W1C) - * - * RX FIFO Threshold interrupt. - * This bit is set when RX FIFO Threshold interrupts occur. - */ -#define SPI_INTRST_RXFIFOINT_MASK (0x4U) -#define SPI_INTRST_RXFIFOINT_SHIFT (2U) -#define SPI_INTRST_RXFIFOINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOINT_SHIFT) & SPI_INTRST_RXFIFOINT_MASK) -#define SPI_INTRST_RXFIFOINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOINT_MASK) >> SPI_INTRST_RXFIFOINT_SHIFT) - -/* - * TXFIFOURINT (W1C) - * - * TX FIFO Underrun interrupt. - * This bit is set when TX FIFO Underrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_TXFIFOURINT_MASK (0x2U) -#define SPI_INTRST_TXFIFOURINT_SHIFT (1U) -#define SPI_INTRST_TXFIFOURINT_SET(x) (((uint32_t)(x) << SPI_INTRST_TXFIFOURINT_SHIFT) & SPI_INTRST_TXFIFOURINT_MASK) -#define SPI_INTRST_TXFIFOURINT_GET(x) (((uint32_t)(x) & SPI_INTRST_TXFIFOURINT_MASK) >> SPI_INTRST_TXFIFOURINT_SHIFT) - -/* - * RXFIFOORINT (W1C) - * - * RX FIFO Overrun interrupt. - * This bit is set when RX FIFO Overrun interrupts occur. - * (Slave mode only) - */ -#define SPI_INTRST_RXFIFOORINT_MASK (0x1U) -#define SPI_INTRST_RXFIFOORINT_SHIFT (0U) -#define SPI_INTRST_RXFIFOORINT_SET(x) (((uint32_t)(x) << SPI_INTRST_RXFIFOORINT_SHIFT) & SPI_INTRST_RXFIFOORINT_MASK) -#define SPI_INTRST_RXFIFOORINT_GET(x) (((uint32_t)(x) & SPI_INTRST_RXFIFOORINT_MASK) >> SPI_INTRST_RXFIFOORINT_SHIFT) - -/* Bitfield definition for register: TIMING */ -/* - * CS2SCLK (RW) - * - * The minimum time between the edges of SPI CS and the edges of SCLK. - * SCLK_period * (CS2SCLK + 1) / 2 - */ -#define SPI_TIMING_CS2SCLK_MASK (0x3000U) -#define SPI_TIMING_CS2SCLK_SHIFT (12U) -#define SPI_TIMING_CS2SCLK_SET(x) (((uint32_t)(x) << SPI_TIMING_CS2SCLK_SHIFT) & SPI_TIMING_CS2SCLK_MASK) -#define SPI_TIMING_CS2SCLK_GET(x) (((uint32_t)(x) & SPI_TIMING_CS2SCLK_MASK) >> SPI_TIMING_CS2SCLK_SHIFT) - -/* - * CSHT (RW) - * - * The minimum time that SPI CS should stay HIGH. - * SCLK_period * (CSHT + 1) / 2 - */ -#define SPI_TIMING_CSHT_MASK (0xF00U) -#define SPI_TIMING_CSHT_SHIFT (8U) -#define SPI_TIMING_CSHT_SET(x) (((uint32_t)(x) << SPI_TIMING_CSHT_SHIFT) & SPI_TIMING_CSHT_MASK) -#define SPI_TIMING_CSHT_GET(x) (((uint32_t)(x) & SPI_TIMING_CSHT_MASK) >> SPI_TIMING_CSHT_SHIFT) - -/* - * SCLK_DIV (RW) - * - * The clock frequency ratio between the clock source and SPI interface SCLK. - * SCLK_period = ((SCLK_DIV + 1) * 2) * (Period of the SPI clock source) - * The SCLK_DIV value 0xff is a special value which indicates that the SCLK frequency should be the same as the spi_clock frequency. - */ -#define SPI_TIMING_SCLK_DIV_MASK (0xFFU) -#define SPI_TIMING_SCLK_DIV_SHIFT (0U) -#define SPI_TIMING_SCLK_DIV_SET(x) (((uint32_t)(x) << SPI_TIMING_SCLK_DIV_SHIFT) & SPI_TIMING_SCLK_DIV_MASK) -#define SPI_TIMING_SCLK_DIV_GET(x) (((uint32_t)(x) & SPI_TIMING_SCLK_DIV_MASK) >> SPI_TIMING_SCLK_DIV_SHIFT) - -/* Bitfield definition for register: SLVST */ -/* - * UNDERRUN (W1C) - * - * Data underrun occurs in the last transaction - */ -#define SPI_SLVST_UNDERRUN_MASK (0x40000UL) -#define SPI_SLVST_UNDERRUN_SHIFT (18U) -#define SPI_SLVST_UNDERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_UNDERRUN_SHIFT) & SPI_SLVST_UNDERRUN_MASK) -#define SPI_SLVST_UNDERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_UNDERRUN_MASK) >> SPI_SLVST_UNDERRUN_SHIFT) - -/* - * OVERRUN (RW) - * - * Data overrun occurs in the last transaction - */ -#define SPI_SLVST_OVERRUN_MASK (0x20000UL) -#define SPI_SLVST_OVERRUN_SHIFT (17U) -#define SPI_SLVST_OVERRUN_SET(x) (((uint32_t)(x) << SPI_SLVST_OVERRUN_SHIFT) & SPI_SLVST_OVERRUN_MASK) -#define SPI_SLVST_OVERRUN_GET(x) (((uint32_t)(x) & SPI_SLVST_OVERRUN_MASK) >> SPI_SLVST_OVERRUN_SHIFT) - -/* - * READY (RW) - * - * Set this bit to indicate that the ATCSPI200 is ready for data transaction. - * When an SPI transaction other than slave status-reading command ends, this bit will be cleared to 0. - */ -#define SPI_SLVST_READY_MASK (0x10000UL) -#define SPI_SLVST_READY_SHIFT (16U) -#define SPI_SLVST_READY_SET(x) (((uint32_t)(x) << SPI_SLVST_READY_SHIFT) & SPI_SLVST_READY_MASK) -#define SPI_SLVST_READY_GET(x) (((uint32_t)(x) & SPI_SLVST_READY_MASK) >> SPI_SLVST_READY_SHIFT) - -/* - * USR_STATUS (RW) - * - * User defined status flags - */ -#define SPI_SLVST_USR_STATUS_MASK (0xFFFFU) -#define SPI_SLVST_USR_STATUS_SHIFT (0U) -#define SPI_SLVST_USR_STATUS_SET(x) (((uint32_t)(x) << SPI_SLVST_USR_STATUS_SHIFT) & SPI_SLVST_USR_STATUS_MASK) -#define SPI_SLVST_USR_STATUS_GET(x) (((uint32_t)(x) & SPI_SLVST_USR_STATUS_MASK) >> SPI_SLVST_USR_STATUS_SHIFT) - -/* Bitfield definition for register: SLVDATACNT */ -/* - * WCNT (RO) - * - * Slave transmitted data count - */ -#define SPI_SLVDATACNT_WCNT_MASK (0x3FF0000UL) -#define SPI_SLVDATACNT_WCNT_SHIFT (16U) -#define SPI_SLVDATACNT_WCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_WCNT_MASK) >> SPI_SLVDATACNT_WCNT_SHIFT) - -/* - * RCNT (RO) - * - * Slave received data count - */ -#define SPI_SLVDATACNT_RCNT_MASK (0x3FFU) -#define SPI_SLVDATACNT_RCNT_SHIFT (0U) -#define SPI_SLVDATACNT_RCNT_GET(x) (((uint32_t)(x) & SPI_SLVDATACNT_RCNT_MASK) >> SPI_SLVDATACNT_RCNT_SHIFT) - -/* Bitfield definition for register: SLVDATAWCNT */ -/* - * VAL (RO) - * - */ -#define SPI_SLVDATAWCNT_VAL_MASK (0xFFFFFFFFUL) -#define SPI_SLVDATAWCNT_VAL_SHIFT (0U) -#define SPI_SLVDATAWCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATAWCNT_VAL_MASK) >> SPI_SLVDATAWCNT_VAL_SHIFT) - -/* Bitfield definition for register: SLVDATARCNT */ -/* - * VAL (RO) - * - */ -#define SPI_SLVDATARCNT_VAL_MASK (0xFFFFFFFFUL) -#define SPI_SLVDATARCNT_VAL_SHIFT (0U) -#define SPI_SLVDATARCNT_VAL_GET(x) (((uint32_t)(x) & SPI_SLVDATARCNT_VAL_MASK) >> SPI_SLVDATARCNT_VAL_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * SLAVE (RO) - * - * Support for SPI Slave mode - */ -#define SPI_CONFIG_SLAVE_MASK (0x4000U) -#define SPI_CONFIG_SLAVE_SHIFT (14U) -#define SPI_CONFIG_SLAVE_GET(x) (((uint32_t)(x) & SPI_CONFIG_SLAVE_MASK) >> SPI_CONFIG_SLAVE_SHIFT) - -/* - * QUADSPI (RO) - * - * Support for Quad I/O SPI - */ -#define SPI_CONFIG_QUADSPI_MASK (0x200U) -#define SPI_CONFIG_QUADSPI_SHIFT (9U) -#define SPI_CONFIG_QUADSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_QUADSPI_MASK) >> SPI_CONFIG_QUADSPI_SHIFT) - -/* - * DUALSPI (RO) - * - * Support for Dual I/O SPI - */ -#define SPI_CONFIG_DUALSPI_MASK (0x100U) -#define SPI_CONFIG_DUALSPI_SHIFT (8U) -#define SPI_CONFIG_DUALSPI_GET(x) (((uint32_t)(x) & SPI_CONFIG_DUALSPI_MASK) >> SPI_CONFIG_DUALSPI_SHIFT) - -/* - * TXFIFOSIZE (RO) - * - * Depth of TX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_TXFIFOSIZE_MASK (0xF0U) -#define SPI_CONFIG_TXFIFOSIZE_SHIFT (4U) -#define SPI_CONFIG_TXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_TXFIFOSIZE_MASK) >> SPI_CONFIG_TXFIFOSIZE_SHIFT) - -/* - * RXFIFOSIZE (RO) - * - * Depth of RX FIFO - * 0x0: 2 words - * 0x1: 4 words - * 0x2: 8 words - * 0x3: 16 words - * 0x4: 32 words - * 0x5: 64 words - * 0x6: 128 words - */ -#define SPI_CONFIG_RXFIFOSIZE_MASK (0xFU) -#define SPI_CONFIG_RXFIFOSIZE_SHIFT (0U) -#define SPI_CONFIG_RXFIFOSIZE_GET(x) (((uint32_t)(x) & SPI_CONFIG_RXFIFOSIZE_MASK) >> SPI_CONFIG_RXFIFOSIZE_SHIFT) - - - - -#endif /* HPM_SPI_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_synt_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_synt_regs.h deleted file mode 100644 index 6026e8d635a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_synt_regs.h +++ /dev/null @@ -1,210 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYNT_H -#define HPM_SYNT_H - -typedef struct { - __RW uint32_t GCR; /* 0x0: Global control register */ - __RW uint32_t RLD; /* 0x4: Counter reload register */ - __RW uint32_t TIMESTAMP_NEW; /* 0x8: timestamp new value register */ - __R uint32_t CNT; /* 0xC: Counter */ - __R uint32_t TIMESTAMP_SAV; /* 0x10: timestamp trig save value */ - __R uint32_t TIMESTAMP_CUR; /* 0x14: timestamp read value */ - __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */ - __RW uint32_t CMP[16]; /* 0x20 - 0x5C: Comparator */ -} SYNT_Type; - - -/* Bitfield definition for register: GCR */ -/* - * TIMESTAMP_INC_NEW (WO) - * - * set to increase the timesamp with new value, auto clr - */ -#define SYNT_GCR_TIMESTAMP_INC_NEW_MASK (0x80000000UL) -#define SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT (31U) -#define SYNT_GCR_TIMESTAMP_INC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) -#define SYNT_GCR_TIMESTAMP_INC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_INC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_INC_NEW_SHIFT) - -/* - * TIMESTAMP_DEC_NEW (WO) - * - * set to decrease the timesamp with new value, auto clr - */ -#define SYNT_GCR_TIMESTAMP_DEC_NEW_MASK (0x40000000UL) -#define SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT (30U) -#define SYNT_GCR_TIMESTAMP_DEC_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) -#define SYNT_GCR_TIMESTAMP_DEC_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEC_NEW_MASK) >> SYNT_GCR_TIMESTAMP_DEC_NEW_SHIFT) - -/* - * TIMESTAMP_SET_NEW (WO) - * - * set the timesamp to new value, auto clr - */ -#define SYNT_GCR_TIMESTAMP_SET_NEW_MASK (0x20000000UL) -#define SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT (29U) -#define SYNT_GCR_TIMESTAMP_SET_NEW_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) -#define SYNT_GCR_TIMESTAMP_SET_NEW_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_SET_NEW_MASK) >> SYNT_GCR_TIMESTAMP_SET_NEW_SHIFT) - -/* - * TIMESTAMP_RESET (WO) - * - * reset timesamp to 0, auto clr - */ -#define SYNT_GCR_TIMESTAMP_RESET_MASK (0x10000000UL) -#define SYNT_GCR_TIMESTAMP_RESET_SHIFT (28U) -#define SYNT_GCR_TIMESTAMP_RESET_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_RESET_SHIFT) & SYNT_GCR_TIMESTAMP_RESET_MASK) -#define SYNT_GCR_TIMESTAMP_RESET_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_RESET_MASK) >> SYNT_GCR_TIMESTAMP_RESET_SHIFT) - -/* - * TIMESTAMP_DEBUG_EN (RW) - * - * set to enable cpu_debug_mode to stop the timesamp - */ -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK (0x20U) -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT (5U) -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) -#define SYNT_GCR_TIMESTAMP_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_DEBUG_EN_MASK) >> SYNT_GCR_TIMESTAMP_DEBUG_EN_SHIFT) - -/* - * TIMESTAMP_ENABLE (RW) - * - * set to enable the timesamp , clr to stop - */ -#define SYNT_GCR_TIMESTAMP_ENABLE_MASK (0x10U) -#define SYNT_GCR_TIMESTAMP_ENABLE_SHIFT (4U) -#define SYNT_GCR_TIMESTAMP_ENABLE_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) -#define SYNT_GCR_TIMESTAMP_ENABLE_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMESTAMP_ENABLE_MASK) >> SYNT_GCR_TIMESTAMP_ENABLE_SHIFT) - -/* - * TIMER_ONESHOT (RW) - * - * set for one shot mode, timer will run only once. - * Software need reset timer first to start another one shot - */ -#define SYNT_GCR_TIMER_ONESHOT_MASK (0x8U) -#define SYNT_GCR_TIMER_ONESHOT_SHIFT (3U) -#define SYNT_GCR_TIMER_ONESHOT_SET(x) (((uint32_t)(x) << SYNT_GCR_TIMER_ONESHOT_SHIFT) & SYNT_GCR_TIMER_ONESHOT_MASK) -#define SYNT_GCR_TIMER_ONESHOT_GET(x) (((uint32_t)(x) & SYNT_GCR_TIMER_ONESHOT_MASK) >> SYNT_GCR_TIMER_ONESHOT_SHIFT) - -/* - * COUNTER_DEBUG_EN (RW) - * - * set to enable cpu_debug_mode to stop the counter - */ -#define SYNT_GCR_COUNTER_DEBUG_EN_MASK (0x4U) -#define SYNT_GCR_COUNTER_DEBUG_EN_SHIFT (2U) -#define SYNT_GCR_COUNTER_DEBUG_EN_SET(x) (((uint32_t)(x) << SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) -#define SYNT_GCR_COUNTER_DEBUG_EN_GET(x) (((uint32_t)(x) & SYNT_GCR_COUNTER_DEBUG_EN_MASK) >> SYNT_GCR_COUNTER_DEBUG_EN_SHIFT) - -/* - * CRST (RW) - * - * 1- Reset counter - */ -#define SYNT_GCR_CRST_MASK (0x2U) -#define SYNT_GCR_CRST_SHIFT (1U) -#define SYNT_GCR_CRST_SET(x) (((uint32_t)(x) << SYNT_GCR_CRST_SHIFT) & SYNT_GCR_CRST_MASK) -#define SYNT_GCR_CRST_GET(x) (((uint32_t)(x) & SYNT_GCR_CRST_MASK) >> SYNT_GCR_CRST_SHIFT) - -/* - * CEN (RW) - * - * 1- Enable counter - */ -#define SYNT_GCR_CEN_MASK (0x1U) -#define SYNT_GCR_CEN_SHIFT (0U) -#define SYNT_GCR_CEN_SET(x) (((uint32_t)(x) << SYNT_GCR_CEN_SHIFT) & SYNT_GCR_CEN_MASK) -#define SYNT_GCR_CEN_GET(x) (((uint32_t)(x) & SYNT_GCR_CEN_MASK) >> SYNT_GCR_CEN_SHIFT) - -/* Bitfield definition for register: RLD */ -/* - * RLD (RW) - * - * counter reload value - */ -#define SYNT_RLD_RLD_MASK (0xFFFFFFFFUL) -#define SYNT_RLD_RLD_SHIFT (0U) -#define SYNT_RLD_RLD_SET(x) (((uint32_t)(x) << SYNT_RLD_RLD_SHIFT) & SYNT_RLD_RLD_MASK) -#define SYNT_RLD_RLD_GET(x) (((uint32_t)(x) & SYNT_RLD_RLD_MASK) >> SYNT_RLD_RLD_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_NEW */ -/* - * VALUE (RW) - * - * new value for timesamp , can be used as set/inc/dec - */ -#define SYNT_TIMESTAMP_NEW_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_TIMESTAMP_NEW_VALUE_SHIFT (0U) -#define SYNT_TIMESTAMP_NEW_VALUE_SET(x) (((uint32_t)(x) << SYNT_TIMESTAMP_NEW_VALUE_SHIFT) & SYNT_TIMESTAMP_NEW_VALUE_MASK) -#define SYNT_TIMESTAMP_NEW_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_NEW_VALUE_MASK) >> SYNT_TIMESTAMP_NEW_VALUE_SHIFT) - -/* Bitfield definition for register: CNT */ -/* - * CNT (RO) - * - * counter - */ -#define SYNT_CNT_CNT_MASK (0xFFFFFFFFUL) -#define SYNT_CNT_CNT_SHIFT (0U) -#define SYNT_CNT_CNT_GET(x) (((uint32_t)(x) & SYNT_CNT_CNT_MASK) >> SYNT_CNT_CNT_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_SAV */ -/* - * VALUE (RO) - * - * use the trigger to save timesamp here - */ -#define SYNT_TIMESTAMP_SAV_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_TIMESTAMP_SAV_VALUE_SHIFT (0U) -#define SYNT_TIMESTAMP_SAV_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_SAV_VALUE_MASK) >> SYNT_TIMESTAMP_SAV_VALUE_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_CUR */ -/* - * VALUE (RO) - * - * current timesamp value - */ -#define SYNT_TIMESTAMP_CUR_VALUE_MASK (0xFFFFFFFFUL) -#define SYNT_TIMESTAMP_CUR_VALUE_SHIFT (0U) -#define SYNT_TIMESTAMP_CUR_VALUE_GET(x) (((uint32_t)(x) & SYNT_TIMESTAMP_CUR_VALUE_MASK) >> SYNT_TIMESTAMP_CUR_VALUE_SHIFT) - -/* Bitfield definition for register array: CMP */ -/* - * CMP (RW) - * - * comparator value, the output will assert when counter count to this value - */ -#define SYNT_CMP_CMP_MASK (0xFFFFFFFFUL) -#define SYNT_CMP_CMP_SHIFT (0U) -#define SYNT_CMP_CMP_SET(x) (((uint32_t)(x) << SYNT_CMP_CMP_SHIFT) & SYNT_CMP_CMP_MASK) -#define SYNT_CMP_CMP_GET(x) (((uint32_t)(x) & SYNT_CMP_CMP_MASK) >> SYNT_CMP_CMP_SHIFT) - - - -/* CMP register group index macro definition */ -#define SYNT_CMP_0 (0UL) -#define SYNT_CMP_1 (1UL) -#define SYNT_CMP_2 (2UL) -#define SYNT_CMP_3 (3UL) -#define SYNT_CMP_4 (4UL) -#define SYNT_CMP_5 (5UL) -#define SYNT_CMP_6 (6UL) -#define SYNT_CMP_7 (7UL) -#define SYNT_CMP_8 (8UL) -#define SYNT_CMP_9 (9UL) -#define SYNT_CMP_10 (10UL) -#define SYNT_CMP_11 (11UL) -#define SYNT_CMP_12 (12UL) -#define SYNT_CMP_13 (13UL) -#define SYNT_CMP_14 (14UL) -#define SYNT_CMP_15 (15UL) - - -#endif /* HPM_SYNT_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sysctl_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sysctl_regs.h deleted file mode 100644 index 6e09b201e2c..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_sysctl_regs.h +++ /dev/null @@ -1,1395 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_SYSCTL_H -#define HPM_SYSCTL_H - -typedef struct { - __RW uint32_t RESOURCE[380]; /* 0x0 - 0x5EC: Resource control register for cpu0_core */ - __R uint8_t RESERVED0[528]; /* 0x5F0 - 0x7FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x800: Group setting */ - __RW uint32_t SET; /* 0x804: Group setting */ - __RW uint32_t CLEAR; /* 0x808: Group setting */ - __RW uint32_t TOGGLE; /* 0x80C: Group setting */ - } GROUP0[4]; - struct { - __RW uint32_t VALUE; /* 0x840: Group setting */ - __RW uint32_t SET; /* 0x844: Group setting */ - __RW uint32_t CLEAR; /* 0x848: Group setting */ - __RW uint32_t TOGGLE; /* 0x84C: Group setting */ - } GROUP1[4]; - __R uint8_t RESERVED1[128]; /* 0x880 - 0x8FF: Reserved */ - struct { - __RW uint32_t VALUE; /* 0x900: Affiliate of Group */ - __RW uint32_t SET; /* 0x904: Affiliate of Group */ - __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */ - __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */ - } AFFILIATE[2]; - struct { - __RW uint32_t VALUE; /* 0x920: Retention Contol */ - __RW uint32_t SET; /* 0x924: Retention Contol */ - __RW uint32_t CLEAR; /* 0x928: Retention Contol */ - __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */ - } RETENTION[2]; - __R uint8_t RESERVED2[1728]; /* 0x940 - 0xFFF: Reserved */ - struct { - __RW uint32_t STATUS; /* 0x1000: Power Setting */ - __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */ - __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */ - __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */ - } POWER[3]; - __R uint8_t RESERVED3[976]; /* 0x1030 - 0x13FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x1400: Reset Setting */ - __RW uint32_t CONFIG; /* 0x1404: Reset Setting */ - __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */ - __RW uint32_t COUNTER; /* 0x140C: Reset Setting */ - } RESET[4]; - __R uint8_t RESERVED4[960]; /* 0x1440 - 0x17FF: Reserved */ - __RW uint32_t CLOCK[73]; /* 0x1800 - 0x1920: Clock setting */ - __R uint8_t RESERVED5[732]; /* 0x1924 - 0x1BFF: Reserved */ - __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */ - __RW uint32_t I2SCLK[2]; /* 0x1C10 - 0x1C14: Clock setting */ - __R uint8_t RESERVED6[1000]; /* 0x1C18 - 0x1FFF: Reserved */ - __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */ - __R uint8_t RESERVED7[1020]; /* 0x2004 - 0x23FF: Reserved */ - struct { - __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */ - __R uint32_t CURRENT; /* 0x2404: Clock measure result */ - __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */ - __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */ - __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */ - } MONITOR[4]; - __R uint8_t RESERVED8[896]; /* 0x2480 - 0x27FF: Reserved */ - struct { - __RW uint32_t LP; /* 0x2800: CPU0 LP control */ - __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */ - __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */ - __R uint32_t WAKEUP_STATUS[6]; /* 0x2840 - 0x2854: CPU0 wakeup IRQ status */ - __R uint8_t RESERVED0[40]; /* 0x2858 - 0x287F: Reserved */ - __RW uint32_t WAKEUP_ENABLE[6]; /* 0x2880 - 0x2894: CPU0 wakeup IRQ enable */ - __R uint8_t RESERVED1[872]; /* 0x2898 - 0x2BFF: Reserved */ - } CPU[2]; -} SYSCTL_Type; - - -/* Bitfield definition for register array: RESOURCE */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any nodes - * 1: any of nodes is changing status - */ -#define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U) -#define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: no change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U) -#define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT) - -/* - * MODE (RW) - * - * resource work mode - * 0:auto turn on and off as system required(recommended) - * 1:always on - * 2:always off - * 3:reserved - */ -#define SYSCTL_RESOURCE_MODE_MASK (0x3U) -#define SYSCTL_RESOURCE_MODE_SHIFT (0U) -#define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK) -#define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK) -#define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK) -#define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK) -#define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP0: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: VALUE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: peripheral is not needed - * 1: periphera is needed - */ -#define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK) -#define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: SET */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: add periphera into this group，periphera is needed - */ -#define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_SET_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK) -#define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: CLEAR */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: delete periphera in this group，periphera is not needed - */ -#define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK) -#define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array GROUP1: TOGGLE */ -/* - * LINK (RW) - * - * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral - * 0: no effect - * 1: toggle the result that whether periphera is needed before - */ -#define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL) -#define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) -#define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: VALUE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * bit0: cpu0 depends on group0 - * bit1: cpu0 depends on group1 - * bit2: cpu0 depends on group2 - * bit3: cpu0 depends on group3 - */ -#define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) -#define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: SET */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0，each bit represents a group - * 0: no effect - * 1: the group is assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK) -#define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: CLEAR */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: the group is not assigned to CPU0 - */ -#define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) -#define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array AFFILIATE: TOGGLE */ -/* - * LINK (RW) - * - * Affiliate groups of cpu0, each bit represents a group - * 0: no effect - * 1: toggle the result that whether the group is assigned to CPU0 before - */ -#define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) -#define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: VALUE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * bit00: soc_mem is kept on while cpu0 stop - * bit01: soc_ctx is kept on while cpu0 stop - * bit02: cpu0_mem is kept on while cpu0 stop - * bit03: cpu0_ctx is kept on while cpu0 stop - * bit04: cpu1_mem is kept on while cpu0 stop - * bit05: cpu1_ctx is kept on while cpu0 stop - * bit06: otn_mem is kept on while cpu0 stop - * bit07: otn_ctx is kept on while cpu0 stop - * bit08: xtal_hold is kept on while cpu0 stop - * bit09: pll0_hold is kept on while cpu0 stop - * bit10: pll1_hold is kept on while cpu0 stop - * bit11: pll2_hold is kept on while cpu0 stop - */ -#define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK) -#define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: SET */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: keep - */ -#define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_SET_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK) -#define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: CLEAR */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: no keep - */ -#define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK) -#define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT) - -/* Bitfield definition for register of struct array RETENTION: TOGGLE */ -/* - * LINK (RW) - * - * retention setting while CPU0 enter stop mode, each bit represents a resource - * 0: no effect - * 1: toggle the result that whether the resource is kept on while CPU0 stop before - */ -#define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU) -#define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U) -#define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) -#define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) - -/* Bitfield definition for register of struct array POWER: STATUS */ -/* - * FLAG (RW) - * - * flag represents power cycle happened from last clear of this bit - * 0: power domain did not edurance power cycle since last clear of this bit - * 1: power domain enduranced power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL) -#define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U) -#define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK) -#define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup power cycle happened from last clear of this bit - * 0: power domain did not edurance wakeup power cycle since last clear of this bit - * 1: power domain enduranced wakeup power cycle since last clear of this bit - */ -#define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) -#define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) - -/* - * LF_DISABLE (RO) - * - * low fanout power switch disable - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U) -#define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT) - -/* - * LF_ACK (RO) - * - * low fanout power switch feedback - * 0: low fanout power switches are turned on - * 1: low fanout power switches are truned off - */ -#define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U) -#define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U) -#define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT) - -/* Bitfield definition for register of struct array POWER: LF_WAIT */ -/* - * WAIT (RW) - * - * wait time for low fan out power switch turn on, default value is 255 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array POWER: OFF_WAIT */ -/* - * WAIT (RW) - * - * wait time for power switch turn off, default value is 15 - * 0: 0 clock cycle - * 1: 1 clock cycles - * . . . - * clock cycles count on 24MHz - */ -#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U) -#define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) -#define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONTROL */ -/* - * FLAG (RW) - * - * flag represents reset happened from last clear of this bit - * 0: domain did not edurance reset cycle since last clear of this bit - * 1: domain enduranced reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U) -#define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT) - -/* - * FLAG_WAKE (RW) - * - * flag represents wakeup reset happened from last clear of this bit - * 0: domain did not edurance wakeup reset cycle since last clear of this bit - * 1: domain enduranced wakeup reset cycle since last clear of this bit - */ -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) -#define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) - -/* - * HOLD (RW) - * - * perform reset and hold in reset, until ths bit cleared by software - * 0: reset is released for function - * 1: reset is assert and hold - */ -#define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U) -#define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U) -#define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK) -#define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT) - -/* - * RESET (RW) - * - * perform reset and release imediately - * 0: reset is released - * 1 reset is asserted and will release automaticly - */ -#define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U) -#define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U) -#define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK) -#define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT) - -/* Bitfield definition for register of struct array RESET: CONFIG */ -/* - * PRE_WAIT (RW) - * - * wait cycle numbers before assert reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) - -/* - * RSTCLK_NUM (RW) - * - * reset clock number(must be even number) - * 0: 0 cycle - * 1: 0 cycles - * 2: 2 cycles - * 3: 2 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) -#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) - -/* - * POST_WAIT (RW) - * - * time guard band for reset release - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U) -#define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) -#define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) - -/* Bitfield definition for register of struct array RESET: COUNTER */ -/* - * COUNTER (RW) - * - * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset - * 0: wait 0 cycle - * 1: wait 1 cycles - * . . . - * Note, clock cycle is base on 24M - */ -#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL) -#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U) -#define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK) -#define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT) - -/* Bitfield definition for register array: CLOCK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_CLOCK_PRESERVE_SHIFT (28U) -#define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK) -#define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux in clock component - * 0:osc0_clk0 - * 1:pll0_clk0 - * 2:pll0_clk1 - * 3:pll1_clk0 - * 4:pll1_clk1 - * 5:pll1_clk2 - * 6:pll2_clk0 - * 7:pll2_clk1 - */ -#define SYSCTL_CLOCK_MUX_MASK (0x700U) -#define SYSCTL_CLOCK_MUX_SHIFT (8U) -#define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK) -#define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT) - -/* - * DIV (RW) - * - * clock divider - * 0: divider by 1 - * 1: divider by 2 - * 2: divider by 3 - * . . . - * 255: divider by 256 - */ -#define SYSCTL_CLOCK_DIV_MASK (0xFFU) -#define SYSCTL_CLOCK_DIV_SHIFT (0U) -#define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK) -#define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT) - -/* Bitfield definition for register array: ADCCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK) -#define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: ana clock N - * 1: ahb0 clock - */ -#define SYSCTL_ADCCLK_MUX_MASK (0x100U) -#define SYSCTL_ADCCLK_MUX_SHIFT (8U) -#define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK) -#define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT) - -/* Bitfield definition for register array: I2SCLK */ -/* - * GLB_BUSY (RO) - * - * global busy - * 0: no changes pending to any clock - * 1: any of nodes is changing status - */ -#define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL) -#define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U) -#define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT) - -/* - * LOC_BUSY (RO) - * - * local busy - * 0: a change is pending for current node - * 1: current node is changing status - */ -#define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL) -#define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U) -#define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT) - -/* - * PRESERVE (RW) - * - * preserve function against global select - * 0: select global clock setting - * 1: not select global clock setting - */ -#define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL) -#define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U) -#define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK) -#define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT) - -/* - * MUX (RW) - * - * current mux - * 0: aud clock N - * 1: aud clock 0 for others , aud clock 1 for i2s0 - */ -#define SYSCTL_I2SCLK_MUX_MASK (0x100U) -#define SYSCTL_I2SCLK_MUX_SHIFT (8U) -#define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK) -#define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT) - -/* Bitfield definition for register: GLOBAL00 */ -/* - * MUX (RW) - * - * global clock override request - * bit0: override to preset0 - * bit1: override to preset1 - * bit2: override to preset2 - * bit3: override to preset3 - * bit4: override to preset4 - * bit5: override to preset5 - * bit6: override to preset6 - * bit7: override to preset7 - */ -#define SYSCTL_GLOBAL00_MUX_MASK (0xFFU) -#define SYSCTL_GLOBAL00_MUX_SHIFT (0U) -#define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK) -#define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CONTROL */ -/* - * VALID (RW) - * - * result is ready for read - * 0: not ready - * 1: result is ready - */ -#define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL) -#define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U) -#define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK) -#define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT) - -/* - * DIV_BUSY (RO) - * - * divider is applying new setting - */ -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U) -#define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT) - -/* - * OUTEN (RW) - * - * enable clock output - */ -#define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U) -#define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) -#define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) - -/* - * DIV (RW) - * - * output divider - */ -#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL) -#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U) -#define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK) -#define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT) - -/* - * HIGH (RW) - * - * clock frequency higher than upper limit - */ -#define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U) -#define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) -#define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) - -/* - * LOW (RW) - * - * clock frequency lower than lower limit - */ -#define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U) -#define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U) -#define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK) -#define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT) - -/* - * START (RW) - * - * start measurement - */ -#define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U) -#define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U) -#define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK) -#define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT) - -/* - * MODE (RW) - * - * work mode, - * 0: register value will be compared to measurement - * 1: upper and lower value will be recordered in register - */ -#define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U) -#define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U) -#define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK) -#define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT) - -/* - * ACCURACY (RW) - * - * measurement accuracy, - * 0: resolution is 1kHz - * 1: resolution is 1Hz - */ -#define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) -#define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) - -/* - * REFERENCE (RW) - * - * refrence clock selection, - * 0: 32k - * 1: 24M - */ -#define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) -#define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) - -/* - * SELECTION (RW) - * - * clock measurement selection - */ -#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U) -#define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) -#define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: CURRENT */ -/* - * FREQUENCY (RO) - * - * self updating measure result - */ -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */ -/* - * FREQUENCY (RW) - * - * lower frequency - */ -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */ -/* - * FREQUENCY (RW) - * - * upper frequency - */ -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) -#define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) - -/* Bitfield definition for register of struct array CPU: LP */ -/* - * WAKE_CNT (RW) - * - * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear - */ -#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL) -#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U) -#define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK) -#define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT) - -/* - * HALT (RW) - * - * halt request for CPU0, - * 0: CPU0 will start to execute after reset or receive wakeup request - * 1: CPU0 will not start after reset, or wakeup after WFI - */ -#define SYSCTL_CPU_LP_HALT_MASK (0x10000UL) -#define SYSCTL_CPU_LP_HALT_SHIFT (16U) -#define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK) -#define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT) - -/* - * WAKE (RO) - * - * CPU0 is waking up - * 0: CPU0 wake up not asserted - * 1: CPU0 wake up asserted - */ -#define SYSCTL_CPU_LP_WAKE_MASK (0x2000U) -#define SYSCTL_CPU_LP_WAKE_SHIFT (13U) -#define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT) - -/* - * EXEC (RO) - * - * CPU0 is executing - * 0: CPU0 is not executing - * 1: CPU0 is executing - */ -#define SYSCTL_CPU_LP_EXEC_MASK (0x1000U) -#define SYSCTL_CPU_LP_EXEC_SHIFT (12U) -#define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT) - -/* - * WAKE_FLAG (RW) - * - * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit - * 0: CPU0 wakeup not happened - * 1: CPU0 wake up happened - */ -#define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U) -#define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) -#define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) - -/* - * SLEEP_FLAG (RW) - * - * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit - * 0: CPU0 sleep not happened - * 1: CPU0 sleep happened - */ -#define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U) -#define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) -#define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) - -/* - * RESET_FLAG (RW) - * - * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit - * 0: CPU0 reset not happened - * 1: CPU0 reset happened - */ -#define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U) -#define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U) -#define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK) -#define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT) - -/* - * MODE (RW) - * - * Low power mode, system behavior after WFI - * 00: CPU clock stop after WFI - * 01: System enter low power mode after WFI - * 10: Keep running after WFI - * 11: reserved - */ -#define SYSCTL_CPU_LP_MODE_MASK (0x3U) -#define SYSCTL_CPU_LP_MODE_SHIFT (0U) -#define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK) -#define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT) - -/* Bitfield definition for register of struct array CPU: LOCK */ -/* - * GPR (RW) - * - * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset - */ -#define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU) -#define SYSCTL_CPU_LOCK_GPR_SHIFT (2U) -#define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK) -#define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT) - -/* - * LOCK (RW) - * - * Lock bit for CPU_LOCK - */ -#define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U) -#define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U) -#define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK) -#define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT) - -/* Bitfield definition for register of struct array CPU: GPR0 */ -/* - * GPR (RW) - * - * register for software to handle resume, can save resume address or status - */ -#define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_GPR_GPR_SHIFT (0U) -#define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK) -#define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT) - -/* Bitfield definition for register of struct array CPU: STATUS0 */ -/* - * STATUS (RO) - * - * IRQ values - */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT) - -/* Bitfield definition for register of struct array CPU: ENABLE0 */ -/* - * ENABLE (RW) - * - * IRQ wakeup enable - */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) - - - -/* RESOURCE register group index macro definition */ -#define SYSCTL_RESOURCE_CPU0 (0UL) -#define SYSCTL_RESOURCE_CPX0 (1UL) -#define SYSCTL_RESOURCE_CPU1 (8UL) -#define SYSCTL_RESOURCE_CPX1 (9UL) -#define SYSCTL_RESOURCE_POW_CPU0 (21UL) -#define SYSCTL_RESOURCE_POW_CPU1 (22UL) -#define SYSCTL_RESOURCE_POW_OTN (23UL) -#define SYSCTL_RESOURCE_RST_SOC (24UL) -#define SYSCTL_RESOURCE_RST_CPU0 (25UL) -#define SYSCTL_RESOURCE_RST_CPU1 (26UL) -#define SYSCTL_RESOURCE_RST_OTN (27UL) -#define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1 (36UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (37UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (38UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (39UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL) -#define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL) -#define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL) -#define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL) -#define SYSCTL_RESOURCE_CLK_TOP_MCT1 (67UL) -#define SYSCTL_RESOURCE_CLK_TOP_AHB0 (68UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIF (69UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIS (70UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIC (71UL) -#define SYSCTL_RESOURCE_CLK_TOP_AXIN (72UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR0 (73UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR1 (74UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR2 (75UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR3 (76UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR4 (77UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR5 (78UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR6 (79UL) -#define SYSCTL_RESOURCE_CLK_TOP_TMR7 (80UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C0 (81UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C1 (82UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C2 (83UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C3 (84UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C4 (85UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C5 (86UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C6 (87UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2C7 (88UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI0 (89UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI1 (90UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI2 (91UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI3 (92UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI4 (93UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI5 (94UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI6 (95UL) -#define SYSCTL_RESOURCE_CLK_TOP_SPI7 (96UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT0 (97UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT1 (98UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT2 (99UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT3 (100UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT4 (101UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT5 (102UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT6 (103UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT7 (104UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT8 (105UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT9 (106UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT10 (107UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT11 (108UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT12 (109UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT13 (110UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT14 (111UL) -#define SYSCTL_RESOURCE_CLK_TOP_URT15 (112UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA0 (113UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (114UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (115UL) -#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (116UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (117UL) -#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (118UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN0 (119UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN1 (120UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN2 (121UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN3 (122UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN4 (123UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN5 (124UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN6 (125UL) -#define SYSCTL_RESOURCE_CLK_TOP_CAN7 (126UL) -#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (127UL) -#define SYSCTL_RESOURCE_CLK_TOP_FEMC (128UL) -#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (129UL) -#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (130UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF0 (131UL) -#define SYSCTL_RESOURCE_CLK_TOP_REF1 (132UL) -#define SYSCTL_RESOURCE_CLK_TOP_NTM0 (133UL) -#define SYSCTL_RESOURCE_CLK_TOP_TSW1 (134UL) -#define SYSCTL_RESOURCE_CLK_TOP_TSW2 (135UL) -#define SYSCTL_RESOURCE_CLK_TOP_TSW3 (136UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (137UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (138UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (139UL) -#define SYSCTL_RESOURCE_CLK_TOP_ADC3 (140UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (141UL) -#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (142UL) -#define SYSCTL_RESOURCE_AHBP (256UL) -#define SYSCTL_RESOURCE_AXIS (257UL) -#define SYSCTL_RESOURCE_AXIC (258UL) -#define SYSCTL_RESOURCE_AXIN (259UL) -#define SYSCTL_RESOURCE_ROM0 (260UL) -#define SYSCTL_RESOURCE_LMM0 (261UL) -#define SYSCTL_RESOURCE_MCT0 (262UL) -#define SYSCTL_RESOURCE_LMM1 (263UL) -#define SYSCTL_RESOURCE_MCT1 (264UL) -#define SYSCTL_RESOURCE_TMR0 (265UL) -#define SYSCTL_RESOURCE_TMR1 (266UL) -#define SYSCTL_RESOURCE_TMR2 (267UL) -#define SYSCTL_RESOURCE_TMR3 (268UL) -#define SYSCTL_RESOURCE_TMR4 (269UL) -#define SYSCTL_RESOURCE_TMR5 (270UL) -#define SYSCTL_RESOURCE_TMR6 (271UL) -#define SYSCTL_RESOURCE_TMR7 (272UL) -#define SYSCTL_RESOURCE_I2C0 (273UL) -#define SYSCTL_RESOURCE_I2C1 (274UL) -#define SYSCTL_RESOURCE_I2C2 (275UL) -#define SYSCTL_RESOURCE_I2C3 (276UL) -#define SYSCTL_RESOURCE_I2C4 (277UL) -#define SYSCTL_RESOURCE_I2C5 (278UL) -#define SYSCTL_RESOURCE_I2C6 (279UL) -#define SYSCTL_RESOURCE_I2C7 (280UL) -#define SYSCTL_RESOURCE_SPI0 (281UL) -#define SYSCTL_RESOURCE_SPI1 (282UL) -#define SYSCTL_RESOURCE_SPI2 (283UL) -#define SYSCTL_RESOURCE_SPI3 (284UL) -#define SYSCTL_RESOURCE_SPI4 (285UL) -#define SYSCTL_RESOURCE_SPI5 (286UL) -#define SYSCTL_RESOURCE_SPI6 (287UL) -#define SYSCTL_RESOURCE_SPI7 (288UL) -#define SYSCTL_RESOURCE_URT0 (289UL) -#define SYSCTL_RESOURCE_URT1 (290UL) -#define SYSCTL_RESOURCE_URT2 (291UL) -#define SYSCTL_RESOURCE_URT3 (292UL) -#define SYSCTL_RESOURCE_URT4 (293UL) -#define SYSCTL_RESOURCE_URT5 (294UL) -#define SYSCTL_RESOURCE_URT6 (295UL) -#define SYSCTL_RESOURCE_URT7 (296UL) -#define SYSCTL_RESOURCE_URT8 (297UL) -#define SYSCTL_RESOURCE_URT9 (298UL) -#define SYSCTL_RESOURCE_URT10 (299UL) -#define SYSCTL_RESOURCE_URT11 (300UL) -#define SYSCTL_RESOURCE_URT12 (301UL) -#define SYSCTL_RESOURCE_URT13 (302UL) -#define SYSCTL_RESOURCE_URT14 (303UL) -#define SYSCTL_RESOURCE_URT15 (304UL) -#define SYSCTL_RESOURCE_CRC0 (305UL) -#define SYSCTL_RESOURCE_TSNS (306UL) -#define SYSCTL_RESOURCE_WDG0 (307UL) -#define SYSCTL_RESOURCE_WDG1 (308UL) -#define SYSCTL_RESOURCE_WDG2 (309UL) -#define SYSCTL_RESOURCE_WDG3 (310UL) -#define SYSCTL_RESOURCE_MBX0 (311UL) -#define SYSCTL_RESOURCE_MBX1 (312UL) -#define SYSCTL_RESOURCE_GPIO (313UL) -#define SYSCTL_RESOURCE_PPI0 (314UL) -#define SYSCTL_RESOURCE_HDMA (315UL) -#define SYSCTL_RESOURCE_LOBS (316UL) -#define SYSCTL_RESOURCE_ADC0 (317UL) -#define SYSCTL_RESOURCE_ADC1 (318UL) -#define SYSCTL_RESOURCE_ADC2 (319UL) -#define SYSCTL_RESOURCE_ADC3 (320UL) -#define SYSCTL_RESOURCE_CMP0 (321UL) -#define SYSCTL_RESOURCE_CMP1 (322UL) -#define SYSCTL_RESOURCE_CMP2 (323UL) -#define SYSCTL_RESOURCE_CMP3 (324UL) -#define SYSCTL_RESOURCE_I2S0 (325UL) -#define SYSCTL_RESOURCE_I2S1 (326UL) -#define SYSCTL_RESOURCE_PDM0 (327UL) -#define SYSCTL_RESOURCE_CLSD (328UL) -#define SYSCTL_RESOURCE_CAN0 (329UL) -#define SYSCTL_RESOURCE_CAN1 (330UL) -#define SYSCTL_RESOURCE_CAN2 (331UL) -#define SYSCTL_RESOURCE_CAN3 (332UL) -#define SYSCTL_RESOURCE_CAN4 (333UL) -#define SYSCTL_RESOURCE_CAN5 (334UL) -#define SYSCTL_RESOURCE_CAN6 (335UL) -#define SYSCTL_RESOURCE_CAN7 (336UL) -#define SYSCTL_RESOURCE_PTPC (337UL) -#define SYSCTL_RESOURCE_QEI0 (338UL) -#define SYSCTL_RESOURCE_QEI1 (339UL) -#define SYSCTL_RESOURCE_QEI2 (340UL) -#define SYSCTL_RESOURCE_QEI3 (341UL) -#define SYSCTL_RESOURCE_QEO0 (342UL) -#define SYSCTL_RESOURCE_QEO1 (343UL) -#define SYSCTL_RESOURCE_QEO2 (344UL) -#define SYSCTL_RESOURCE_QEO3 (345UL) -#define SYSCTL_RESOURCE_PWM0 (346UL) -#define SYSCTL_RESOURCE_PWM1 (347UL) -#define SYSCTL_RESOURCE_PWM2 (348UL) -#define SYSCTL_RESOURCE_PWM3 (349UL) -#define SYSCTL_RESOURCE_RDC0 (350UL) -#define SYSCTL_RESOURCE_RDC1 (351UL) -#define SYSCTL_RESOURCE_SDM0 (352UL) -#define SYSCTL_RESOURCE_SDM1 (353UL) -#define SYSCTL_RESOURCE_PLB0 (354UL) -#define SYSCTL_RESOURCE_SEI0 (355UL) -#define SYSCTL_RESOURCE_MTG0 (356UL) -#define SYSCTL_RESOURCE_MTG1 (357UL) -#define SYSCTL_RESOURCE_VSC0 (358UL) -#define SYSCTL_RESOURCE_VSC1 (359UL) -#define SYSCTL_RESOURCE_CLC0 (360UL) -#define SYSCTL_RESOURCE_CLC1 (361UL) -#define SYSCTL_RESOURCE_EMDS (362UL) -#define SYSCTL_RESOURCE_RNG0 (363UL) -#define SYSCTL_RESOURCE_SDP0 (364UL) -#define SYSCTL_RESOURCE_PKA0 (365UL) -#define SYSCTL_RESOURCE_KMAN (366UL) -#define SYSCTL_RESOURCE_XPI0 (367UL) -#define SYSCTL_RESOURCE_FEMC (368UL) -#define SYSCTL_RESOURCE_RAM0 (369UL) -#define SYSCTL_RESOURCE_RAM1 (370UL) -#define SYSCTL_RESOURCE_XDMA (371UL) -#define SYSCTL_RESOURCE_FFA0 (372UL) -#define SYSCTL_RESOURCE_ETH0 (373UL) -#define SYSCTL_RESOURCE_USB0 (374UL) -#define SYSCTL_RESOURCE_NTM0 (375UL) -#define SYSCTL_RESOURCE_REF0 (376UL) -#define SYSCTL_RESOURCE_REF1 (377UL) -#define SYSCTL_RESOURCE_TSW0 (378UL) -#define SYSCTL_RESOURCE_ESC0 (379UL) - -/* GROUP0 register group index macro definition */ -#define SYSCTL_GROUP0_LINK0 (0UL) -#define SYSCTL_GROUP0_LINK1 (1UL) -#define SYSCTL_GROUP0_LINK2 (2UL) -#define SYSCTL_GROUP0_LINK3 (3UL) - -/* GROUP1 register group index macro definition */ -#define SYSCTL_GROUP1_LINK0 (0UL) -#define SYSCTL_GROUP1_LINK1 (1UL) -#define SYSCTL_GROUP1_LINK2 (2UL) -#define SYSCTL_GROUP1_LINK3 (3UL) - -/* AFFILIATE register group index macro definition */ -#define SYSCTL_AFFILIATE_CPU0 (0UL) -#define SYSCTL_AFFILIATE_CPU1 (1UL) - -/* RETENTION register group index macro definition */ -#define SYSCTL_RETENTION_CPU0 (0UL) -#define SYSCTL_RETENTION_CPU1 (1UL) - -/* POWER register group index macro definition */ -#define SYSCTL_POWER_CPU0 (0UL) -#define SYSCTL_POWER_CPU1 (1UL) -#define SYSCTL_POWER_OTN (2UL) - -/* RESET register group index macro definition */ -#define SYSCTL_RESET_SOC (0UL) -#define SYSCTL_RESET_CPU0 (1UL) -#define SYSCTL_RESET_CPU1 (2UL) -#define SYSCTL_RESET_OTN (3UL) - -/* CLOCK register group index macro definition */ -#define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL) -#define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL) -#define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL) -#define SYSCTL_CLOCK_CLK_TOP_MCT1 (3UL) -#define SYSCTL_CLOCK_CLK_TOP_AHB0 (4UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIF (5UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIS (6UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIC (7UL) -#define SYSCTL_CLOCK_CLK_TOP_AXIN (8UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR4 (13UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR5 (14UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR6 (15UL) -#define SYSCTL_CLOCK_CLK_TOP_TMR7 (16UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C0 (17UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C1 (18UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C2 (19UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C3 (20UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C4 (21UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C5 (22UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C6 (23UL) -#define SYSCTL_CLOCK_CLK_TOP_I2C7 (24UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI0 (25UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI1 (26UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI2 (27UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI3 (28UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI4 (29UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI5 (30UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI6 (31UL) -#define SYSCTL_CLOCK_CLK_TOP_SPI7 (32UL) -#define SYSCTL_CLOCK_CLK_TOP_URT0 (33UL) -#define SYSCTL_CLOCK_CLK_TOP_URT1 (34UL) -#define SYSCTL_CLOCK_CLK_TOP_URT2 (35UL) -#define SYSCTL_CLOCK_CLK_TOP_URT3 (36UL) -#define SYSCTL_CLOCK_CLK_TOP_URT4 (37UL) -#define SYSCTL_CLOCK_CLK_TOP_URT5 (38UL) -#define SYSCTL_CLOCK_CLK_TOP_URT6 (39UL) -#define SYSCTL_CLOCK_CLK_TOP_URT7 (40UL) -#define SYSCTL_CLOCK_CLK_TOP_URT8 (41UL) -#define SYSCTL_CLOCK_CLK_TOP_URT9 (42UL) -#define SYSCTL_CLOCK_CLK_TOP_URT10 (43UL) -#define SYSCTL_CLOCK_CLK_TOP_URT11 (44UL) -#define SYSCTL_CLOCK_CLK_TOP_URT12 (45UL) -#define SYSCTL_CLOCK_CLK_TOP_URT13 (46UL) -#define SYSCTL_CLOCK_CLK_TOP_URT14 (47UL) -#define SYSCTL_CLOCK_CLK_TOP_URT15 (48UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA0 (49UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA1 (50UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA2 (51UL) -#define SYSCTL_CLOCK_CLK_TOP_ANA3 (52UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD0 (53UL) -#define SYSCTL_CLOCK_CLK_TOP_AUD1 (54UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN0 (55UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN1 (56UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN2 (57UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN3 (58UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN4 (59UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN5 (60UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN6 (61UL) -#define SYSCTL_CLOCK_CLK_TOP_CAN7 (62UL) -#define SYSCTL_CLOCK_CLK_TOP_XPI0 (63UL) -#define SYSCTL_CLOCK_CLK_TOP_FEMC (64UL) -#define SYSCTL_CLOCK_CLK_TOP_ETH0 (65UL) -#define SYSCTL_CLOCK_CLK_TOP_PTP0 (66UL) -#define SYSCTL_CLOCK_CLK_TOP_NTM0 (67UL) -#define SYSCTL_CLOCK_CLK_TOP_REF0 (68UL) -#define SYSCTL_CLOCK_CLK_TOP_REF1 (69UL) -#define SYSCTL_CLOCK_CLK_TOP_TSW1 (70UL) -#define SYSCTL_CLOCK_CLK_TOP_TSW2 (71UL) -#define SYSCTL_CLOCK_CLK_TOP_TSW3 (72UL) - -/* ADCCLK register group index macro definition */ -#define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL) -#define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL) - -/* I2SCLK register group index macro definition */ -#define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL) -#define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL) - -/* MONITOR register group index macro definition */ -#define SYSCTL_MONITOR_SLICE0 (0UL) -#define SYSCTL_MONITOR_SLICE1 (1UL) -#define SYSCTL_MONITOR_SLICE2 (2UL) -#define SYSCTL_MONITOR_SLICE3 (3UL) - -/* GPR register group index macro definition */ -#define SYSCTL_CPU_GPR_GPR0 (0UL) -#define SYSCTL_CPU_GPR_GPR1 (1UL) -#define SYSCTL_CPU_GPR_GPR2 (2UL) -#define SYSCTL_CPU_GPR_GPR3 (3UL) -#define SYSCTL_CPU_GPR_GPR4 (4UL) -#define SYSCTL_CPU_GPR_GPR5 (5UL) -#define SYSCTL_CPU_GPR_GPR6 (6UL) -#define SYSCTL_CPU_GPR_GPR7 (7UL) -#define SYSCTL_CPU_GPR_GPR8 (8UL) -#define SYSCTL_CPU_GPR_GPR9 (9UL) -#define SYSCTL_CPU_GPR_GPR10 (10UL) -#define SYSCTL_CPU_GPR_GPR11 (11UL) -#define SYSCTL_CPU_GPR_GPR12 (12UL) -#define SYSCTL_CPU_GPR_GPR13 (13UL) - -/* WAKEUP_STATUS register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL) -#define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL) - -/* WAKEUP_ENABLE register group index macro definition */ -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL) -#define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL) - -/* CPU register group index macro definition */ -#define SYSCTL_CPU_CPU0 (0UL) -#define SYSCTL_CPU_CPU1 (1UL) - - -#endif /* HPM_SYSCTL_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tamp_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tamp_regs.h deleted file mode 100644 index 77a04f69e05..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tamp_regs.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TAMP_H -#define HPM_TAMP_H - -typedef struct { - struct { - __RW uint32_t CONTROL; /* 0x0: Tamper n control */ - __RW uint32_t POLY; /* 0x4: Tamper n Polynomial of LFSR */ - __W uint32_t LFSR; /* 0x8: Tamper n LFSR shift register */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - } TAMP[4]; - __R uint8_t RESERVED0[64]; /* 0x40 - 0x7F: Reserved */ - __RW uint32_t TAMP_FLAG; /* 0x80: Tamper flag */ - __RW uint32_t IRQ_EN; /* 0x84: Tamper interrupt enable */ -} TAMP_Type; - - -/* Bitfield definition for register of struct array TAMP: CONTROL */ -/* - * LOCK (RW) - * - * lock tamper setting - * 0: tamper setting can be changed - * 1: tamper setting will last to next battery domain power cycle - */ -#define TAMP_TAMP_CONTROL_LOCK_MASK (0x80000000UL) -#define TAMP_TAMP_CONTROL_LOCK_SHIFT (31U) -#define TAMP_TAMP_CONTROL_LOCK_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_LOCK_SHIFT) & TAMP_TAMP_CONTROL_LOCK_MASK) -#define TAMP_TAMP_CONTROL_LOCK_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_LOCK_MASK) >> TAMP_TAMP_CONTROL_LOCK_SHIFT) - -/* - * BYPASS (RW) - * - * bypass tamper violation filter - * 0: filter applied - * 1: filter not used - */ -#define TAMP_TAMP_CONTROL_BYPASS_MASK (0x100000UL) -#define TAMP_TAMP_CONTROL_BYPASS_SHIFT (20U) -#define TAMP_TAMP_CONTROL_BYPASS_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_BYPASS_SHIFT) & TAMP_TAMP_CONTROL_BYPASS_MASK) -#define TAMP_TAMP_CONTROL_BYPASS_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_BYPASS_MASK) >> TAMP_TAMP_CONTROL_BYPASS_SHIFT) - -/* - * FILTER (RW) - * - * filter length - * 0: 1 cycle - * 1: 2 cycle - * 15: 65526 cycle - */ -#define TAMP_TAMP_CONTROL_FILTER_MASK (0xF0000UL) -#define TAMP_TAMP_CONTROL_FILTER_SHIFT (16U) -#define TAMP_TAMP_CONTROL_FILTER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_FILTER_SHIFT) & TAMP_TAMP_CONTROL_FILTER_MASK) -#define TAMP_TAMP_CONTROL_FILTER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_FILTER_MASK) >> TAMP_TAMP_CONTROL_FILTER_SHIFT) - -/* - * VALUE (RW) - * - * pin value for passive tamper - */ -#define TAMP_TAMP_CONTROL_VALUE_MASK (0x300U) -#define TAMP_TAMP_CONTROL_VALUE_SHIFT (8U) -#define TAMP_TAMP_CONTROL_VALUE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_VALUE_SHIFT) & TAMP_TAMP_CONTROL_VALUE_MASK) -#define TAMP_TAMP_CONTROL_VALUE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_VALUE_MASK) >> TAMP_TAMP_CONTROL_VALUE_SHIFT) - -/* - * SPEED (RW) - * - * tamper speed selection, (2^SPEED) changes per second - * 0: 1 shift per second - * 1: 2 shifts per second - * . . . - * 15: 32768 shifts per second - */ -#define TAMP_TAMP_CONTROL_SPEED_MASK (0xF0U) -#define TAMP_TAMP_CONTROL_SPEED_SHIFT (4U) -#define TAMP_TAMP_CONTROL_SPEED_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_SPEED_SHIFT) & TAMP_TAMP_CONTROL_SPEED_MASK) -#define TAMP_TAMP_CONTROL_SPEED_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_SPEED_MASK) >> TAMP_TAMP_CONTROL_SPEED_SHIFT) - -/* - * RECOVER (RW) - * - * tamper will recover itself if tamper LFSR goes wrong - * 0: tamper will not recover - * 1: tamper will recover - */ -#define TAMP_TAMP_CONTROL_RECOVER_MASK (0x4U) -#define TAMP_TAMP_CONTROL_RECOVER_SHIFT (2U) -#define TAMP_TAMP_CONTROL_RECOVER_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_RECOVER_SHIFT) & TAMP_TAMP_CONTROL_RECOVER_MASK) -#define TAMP_TAMP_CONTROL_RECOVER_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_RECOVER_MASK) >> TAMP_TAMP_CONTROL_RECOVER_SHIFT) - -/* - * ACTIVE (RW) - * - * select active or passive tamper - * 0: passive tamper - * 1: active tamper - */ -#define TAMP_TAMP_CONTROL_ACTIVE_MASK (0x2U) -#define TAMP_TAMP_CONTROL_ACTIVE_SHIFT (1U) -#define TAMP_TAMP_CONTROL_ACTIVE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ACTIVE_SHIFT) & TAMP_TAMP_CONTROL_ACTIVE_MASK) -#define TAMP_TAMP_CONTROL_ACTIVE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ACTIVE_MASK) >> TAMP_TAMP_CONTROL_ACTIVE_SHIFT) - -/* - * ENABLE (RW) - * - * enable tamper - * 0: tamper disableed - * 1: tamper enabled - */ -#define TAMP_TAMP_CONTROL_ENABLE_MASK (0x1U) -#define TAMP_TAMP_CONTROL_ENABLE_SHIFT (0U) -#define TAMP_TAMP_CONTROL_ENABLE_SET(x) (((uint32_t)(x) << TAMP_TAMP_CONTROL_ENABLE_SHIFT) & TAMP_TAMP_CONTROL_ENABLE_MASK) -#define TAMP_TAMP_CONTROL_ENABLE_GET(x) (((uint32_t)(x) & TAMP_TAMP_CONTROL_ENABLE_MASK) >> TAMP_TAMP_CONTROL_ENABLE_SHIFT) - -/* Bitfield definition for register of struct array TAMP: POLY */ -/* - * POLY (RW) - * - * tamper LFSR polyminal, this is a write once register, once write content is locked, and readout value is "1" - */ -#define TAMP_TAMP_POLY_POLY_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_POLY_POLY_SHIFT (0U) -#define TAMP_TAMP_POLY_POLY_SET(x) (((uint32_t)(x) << TAMP_TAMP_POLY_POLY_SHIFT) & TAMP_TAMP_POLY_POLY_MASK) -#define TAMP_TAMP_POLY_POLY_GET(x) (((uint32_t)(x) & TAMP_TAMP_POLY_POLY_MASK) >> TAMP_TAMP_POLY_POLY_SHIFT) - -/* Bitfield definition for register of struct array TAMP: LFSR */ -/* - * LFSR (WO) - * - * LFSR for active tamper, write only register, always read 0 - */ -#define TAMP_TAMP_LFSR_LFSR_MASK (0xFFFFFFFFUL) -#define TAMP_TAMP_LFSR_LFSR_SHIFT (0U) -#define TAMP_TAMP_LFSR_LFSR_SET(x) (((uint32_t)(x) << TAMP_TAMP_LFSR_LFSR_SHIFT) & TAMP_TAMP_LFSR_LFSR_MASK) -#define TAMP_TAMP_LFSR_LFSR_GET(x) (((uint32_t)(x) & TAMP_TAMP_LFSR_LFSR_MASK) >> TAMP_TAMP_LFSR_LFSR_SHIFT) - -/* Bitfield definition for register: TAMP_FLAG */ -/* - * FLAG (RW) - * - * tamper flag, each bit represents one tamper pin, write 1 to clear the flag - * Note, clear can only be cleared when tamper disappeared - */ -#define TAMP_TAMP_FLAG_FLAG_MASK (0xFFFU) -#define TAMP_TAMP_FLAG_FLAG_SHIFT (0U) -#define TAMP_TAMP_FLAG_FLAG_SET(x) (((uint32_t)(x) << TAMP_TAMP_FLAG_FLAG_SHIFT) & TAMP_TAMP_FLAG_FLAG_MASK) -#define TAMP_TAMP_FLAG_FLAG_GET(x) (((uint32_t)(x) & TAMP_TAMP_FLAG_FLAG_MASK) >> TAMP_TAMP_FLAG_FLAG_SHIFT) - -/* Bitfield definition for register: IRQ_EN */ -/* - * LOCK (RW) - * - * lock bit for IRQ enable - * 0: enable bits can be changed - * 1: enable bits hold until next battery domain power cycle - */ -#define TAMP_IRQ_EN_LOCK_MASK (0x80000000UL) -#define TAMP_IRQ_EN_LOCK_SHIFT (31U) -#define TAMP_IRQ_EN_LOCK_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_LOCK_SHIFT) & TAMP_IRQ_EN_LOCK_MASK) -#define TAMP_IRQ_EN_LOCK_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_LOCK_MASK) >> TAMP_IRQ_EN_LOCK_SHIFT) - -/* - * IRQ_EN (RW) - * - * interrupt enable, each bit represents one tamper pin - * 0: interrupt disabled - * 1: interrupt enabled - */ -#define TAMP_IRQ_EN_IRQ_EN_MASK (0xFFFU) -#define TAMP_IRQ_EN_IRQ_EN_SHIFT (0U) -#define TAMP_IRQ_EN_IRQ_EN_SET(x) (((uint32_t)(x) << TAMP_IRQ_EN_IRQ_EN_SHIFT) & TAMP_IRQ_EN_IRQ_EN_MASK) -#define TAMP_IRQ_EN_IRQ_EN_GET(x) (((uint32_t)(x) & TAMP_IRQ_EN_IRQ_EN_MASK) >> TAMP_IRQ_EN_IRQ_EN_SHIFT) - - - -/* TAMP register group index macro definition */ -#define TAMP_TAMP_TAMP0 (0UL) -#define TAMP_TAMP_TAMP1 (1UL) -#define TAMP_TAMP_TAMP2 (2UL) -#define TAMP_TAMP_TAMP3 (3UL) - - -#endif /* HPM_TAMP_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_trgm_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_trgm_regs.h deleted file mode 100644 index dd96226a487..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_trgm_regs.h +++ /dev/null @@ -1,1157 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TRGM_H -#define HPM_TRGM_H - -typedef struct { - __RW uint32_t FILTCFG[64]; /* 0x0 - 0xFC: Filter configure register */ - __R uint8_t RESERVED0[768]; /* 0x100 - 0x3FF: Reserved */ - __RW uint32_t DMACFG[8]; /* 0x400 - 0x41C: DMA request configure register */ - __R uint8_t RESERVED1[224]; /* 0x420 - 0x4FF: Reserved */ - __RW uint32_t GCR; /* 0x500: */ - __R uint8_t RESERVED2[60]; /* 0x504 - 0x53F: Reserved */ - __RW uint32_t ADC_MATRIX_SEL0; /* 0x540: adc matrix select register0 */ - __RW uint32_t ADC_MATRIX_SEL1; /* 0x544: adc matrix select register1 */ - __RW uint32_t ADC_MATRIX_SEL2; /* 0x548: adc matrix select register2 */ - __RW uint32_t ADC_MATRIX_SEL3; /* 0x54C: adc matrix select register3 */ - __RW uint32_t ADC_MATRIX_SEL4; /* 0x550: adc matrix select register2 */ - __R uint8_t RESERVED3[44]; /* 0x554 - 0x57F: Reserved */ - __RW uint32_t DAC_MATRIX_SEL0; /* 0x580: dac matrix select register0 */ - __RW uint32_t DAC_MATRIX_SEL1; /* 0x584: dac matrix select register1 */ - __RW uint32_t DAC_MATRIX_SEL2; /* 0x588: dac matrix select register2 */ - __RW uint32_t DAC_MATRIX_SEL3; /* 0x58C: dac matrix select register3 */ - __RW uint32_t DAC_MATRIX_SEL4; /* 0x590: dac matrix select register4 */ - __RW uint32_t DAC_MATRIX_SEL5; /* 0x594: dac matrix select register5 */ - __RW uint32_t DAC_MATRIX_SEL6; /* 0x598: dac matrix select register6 */ - __RW uint32_t DAC_MATRIX_SEL7; /* 0x59C: dac matrix select register7 */ - __R uint8_t RESERVED4[32]; /* 0x5A0 - 0x5BF: Reserved */ - __RW uint32_t POS_MATRIX_SEL0; /* 0x5C0: position matrix select register0 */ - __RW uint32_t POS_MATRIX_SEL1; /* 0x5C4: position matrix select register0 */ - __RW uint32_t POS_MATRIX_SEL2; /* 0x5C8: position matrix select register2 */ - __R uint8_t RESERVED5[52]; /* 0x5CC - 0x5FF: Reserved */ - __R uint32_t TRGM_IN[4]; /* 0x600 - 0x60C: trigmux input read register0 */ - __R uint8_t RESERVED6[112]; /* 0x610 - 0x67F: Reserved */ - __R uint32_t TRGM_OUT[8]; /* 0x680 - 0x69C: trigmux output read register0 */ - __R uint8_t RESERVED7[352]; /* 0x6A0 - 0x7FF: Reserved */ - __RW uint32_t PWM_DELAY_CFG; /* 0x800: pwm delay chain config register */ - __RW uint32_t PWM_CALIB_CFG; /* 0x804: pwm delay chain calibration control register */ - __R uint8_t RESERVED8[2040]; /* 0x808 - 0xFFF: Reserved */ - __RW uint32_t TRGOCFG[242]; /* 0x1000 - 0x13C4: Trigger manager output configure register */ -} TRGM_Type; - - -/* Bitfield definition for register array: FILTCFG */ -/* - * OUTINV (RW) - * - * 1- Filter will invert the output - * 0- Filter will not invert the output - */ -#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL) -#define TRGM_FILTCFG_OUTINV_SHIFT (16U) -#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK) -#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT) - -/* - * MODE (RW) - * - * This bitfields defines the filter mode - * 000-bypass; - * 100-rapid change mode; - * 101-delay filter mode; - * 110-stalbe low mode; - * 111-stable high mode - */ -#define TRGM_FILTCFG_MODE_MASK (0xE000U) -#define TRGM_FILTCFG_MODE_SHIFT (13U) -#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK) -#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT) - -/* - * SYNCEN (RW) - * - * set to enable sychronization input signal with TRGM clock - */ -#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U) -#define TRGM_FILTCFG_SYNCEN_SHIFT (12U) -#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK) -#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT) - -/* - * FILTLEN_SHIFT (RW) - * - */ -#define TRGM_FILTCFG_FILTLEN_SHIFT_MASK (0xE00U) -#define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT (9U) -#define TRGM_FILTCFG_FILTLEN_SHIFT_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) -#define TRGM_FILTCFG_FILTLEN_SHIFT_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) - -/* - * FILTLEN_BASE (RW) - * - * This bitfields defines the filter counter length. - */ -#define TRGM_FILTCFG_FILTLEN_BASE_MASK (0x1FFU) -#define TRGM_FILTCFG_FILTLEN_BASE_SHIFT (0U) -#define TRGM_FILTCFG_FILTLEN_BASE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK) -#define TRGM_FILTCFG_FILTLEN_BASE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT) - -/* Bitfield definition for register array: DMACFG */ -/* - * DMAMUX_EN (RW) - * - */ -#define TRGM_DMACFG_DMAMUX_EN_MASK (0x80000000UL) -#define TRGM_DMACFG_DMAMUX_EN_SHIFT (31U) -#define TRGM_DMACFG_DMAMUX_EN_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK) -#define TRGM_DMACFG_DMAMUX_EN_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT) - -/* - * DMASRCSEL (RW) - * - */ -#define TRGM_DMACFG_DMASRCSEL_MASK (0x3FU) -#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U) -#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK) -#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT) - -/* Bitfield definition for register: GCR */ -/* - * TRGOPEN (RW) - * - */ -#define TRGM_GCR_TRGOPEN_MASK (0xFFFFFFFFUL) -#define TRGM_GCR_TRGOPEN_SHIFT (0U) -#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK) -#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT) - -/* Bitfield definition for register: ADC_MATRIX_SEL0 */ -/* - * RDC1_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK (0xFF000000UL) -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SHIFT (24U) -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SHIFT) - -/* - * RDC1_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK (0xFF0000UL) -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SHIFT (16U) -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SHIFT) - -/* - * RDC0_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK (0xFF00U) -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT (8U) -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT) - -/* - * RDC0_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK (0xFFU) -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT (0U) -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT) - -/* Bitfield definition for register: ADC_MATRIX_SEL1 */ -/* - * QEI3_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK (0xFF000000UL) -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SHIFT (24U) -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SHIFT) - -/* - * QEI3_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK (0xFF0000UL) -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SHIFT (16U) -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SHIFT) - -/* - * QEI2_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK (0xFF00U) -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SHIFT (8U) -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SHIFT) - -/* - * QEI2_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK (0xFFU) -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SHIFT (0U) -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SHIFT) - -/* Bitfield definition for register: ADC_MATRIX_SEL2 */ -/* - * VSC1_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK (0xFF000000UL) -#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SHIFT (24U) -#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SHIFT) - -/* - * VSC0_ADC2_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK (0xFF0000UL) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SHIFT (16U) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SHIFT) - -/* - * VSC0_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK (0xFF00U) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SHIFT (8U) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SHIFT) - -/* - * VSC0_ADC0_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK (0xFFU) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SHIFT (0U) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SHIFT) - -/* Bitfield definition for register: ADC_MATRIX_SEL3 */ -/* - * CLC0_IQ_ADC_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK (0xFF000000UL) -#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SHIFT (24U) -#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SHIFT) - -/* - * CLC0_ID_ADC_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK (0xFF0000UL) -#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SHIFT (16U) -#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SHIFT) - -/* - * VSC1_ADC2_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK (0xFF00U) -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SHIFT (8U) -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SHIFT) - -/* - * VSC1_ADC1_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK (0xFFU) -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SHIFT (0U) -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SHIFT) - -/* Bitfield definition for register: ADC_MATRIX_SEL4 */ -/* - * CLC1_VB_ADC_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK (0xFF000000UL) -#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SHIFT (24U) -#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SHIFT) - -/* - * CLC1_IQ_ADC_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK (0xFF0000UL) -#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SHIFT (16U) -#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SHIFT) - -/* - * CLC1_ID_ADC_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK (0xFF00U) -#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SHIFT (8U) -#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SHIFT) - -/* - * CLC0_VB_ADC_SEL (RW) - * - */ -#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK (0xFFU) -#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SHIFT (0U) -#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK) -#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL0 */ -/* - * ACMP3_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT) - -/* - * ACMP2_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT) - -/* - * ACMP1_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT) - -/* - * ACMP0_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL1 */ -/* - * ACMP7_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT) - -/* - * ACMP6_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT) - -/* - * ACMP5_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT) - -/* - * ACMP4_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL2 */ -/* - * PWM0_DAC3_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT) - -/* - * PWM0_DAC2_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT) - -/* - * PWM0_DAC1_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT) - -/* - * PWM0_DAC0_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL3 */ -/* - * PWM1_DAC3_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT) - -/* - * PWM1_DAC2_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT) - -/* - * PWM1_DAC1_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT) - -/* - * PWM1_DAC0_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL4 */ -/* - * PWM2_DAC3_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT) - -/* - * PWM2_DAC2_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT) - -/* - * PWM2_DAC1_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT) - -/* - * PWM2_DAC0_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL5 */ -/* - * PWM3_DAC3_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT) - -/* - * PWM3_DAC2_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT) - -/* - * PWM3_DAC1_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT) - -/* - * PWM3_DAC0_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL6 */ -/* - * QEO1_VQ_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT) - -/* - * QEO1_VD_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT) - -/* - * QEO0_VQ_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT) - -/* - * QEO0_VD_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT) - -/* Bitfield definition for register: DAC_MATRIX_SEL7 */ -/* - * QEO3_VQ_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK (0xFF000000UL) -#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SHIFT (24U) -#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SHIFT) - -/* - * QEO3_VD_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK (0xFF0000UL) -#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SHIFT (16U) -#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SHIFT) - -/* - * QEO2_VQ_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK (0xFF00U) -#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SHIFT (8U) -#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SHIFT) - -/* - * QEO2_VD_DAC_SEL (RW) - * - */ -#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK (0xFFU) -#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SHIFT (0U) -#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK) -#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SHIFT) - -/* Bitfield definition for register: POS_MATRIX_SEL0 */ -/* - * SEI_POSIN3_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK (0xFF000000UL) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SHIFT (24U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SHIFT) - -/* - * SEI_POSIN2_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK (0xFF0000UL) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SHIFT (16U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SHIFT) - -/* - * SEI_POSIN1_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK (0xFF00U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT (8U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) - -/* - * SEI_POSIN0_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK (0xFFU) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT (0U) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) -#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) - -/* Bitfield definition for register: POS_MATRIX_SEL1 */ -/* - * QEO1_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK (0xFF000000UL) -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT (24U) -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) - -/* - * QEO0_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK (0xFF0000UL) -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT (16U) -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) - -/* - * MTG1_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK (0xFF00U) -#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SHIFT (8U) -#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SHIFT) - -/* - * MTG0_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK (0xFFU) -#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SHIFT (0U) -#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SHIFT) - -/* Bitfield definition for register: POS_MATRIX_SEL2 */ -/* - * VSC1_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK (0xFF000000UL) -#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SHIFT (24U) -#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SHIFT) - -/* - * VSC0_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK (0xFF0000UL) -#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SHIFT (16U) -#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SHIFT) - -/* - * QEO3_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK (0xFF00U) -#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SHIFT (8U) -#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SHIFT) - -/* - * QEO2_POS_SEL (RW) - * - */ -#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK (0xFFU) -#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SHIFT (0U) -#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK) -#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SHIFT) - -/* Bitfield definition for register array: TRGM_IN */ -/* - * TRGM_IN (RO) - * - */ -#define TRGM_TRGM_IN_TRGM_IN_MASK (0xFFFFFFFFUL) -#define TRGM_TRGM_IN_TRGM_IN_SHIFT (0U) -#define TRGM_TRGM_IN_TRGM_IN_GET(x) (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT) - -/* Bitfield definition for register array: TRGM_OUT */ -/* - * TRGM_OUT (RO) - * - */ -#define TRGM_TRGM_OUT_TRGM_OUT_MASK (0xFFFFFFFFUL) -#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT (0U) -#define TRGM_TRGM_OUT_TRGM_OUT_GET(x) (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT) - -/* Bitfield definition for register: PWM_DELAY_CFG */ -/* - * DELAY_CHAN_CALIB_SW (RW) - * - */ -#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK (0x3FU) -#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT (0U) -#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SET(x) (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK) -#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_GET(x) (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT) - -/* Bitfield definition for register: PWM_CALIB_CFG */ -/* - * CALIB_SW_START (RW) - * - */ -#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK (0x8000U) -#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT (15U) -#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SET(x) (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK) -#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT) - -/* - * CALIB_PERIOD (RW) - * - */ -#define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_MASK (0x1FU) -#define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SHIFT (0U) -#define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SET(x) (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_PERIOD_MASK) -#define TRGM_PWM_CALIB_CFG_CALIB_PERIOD_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_PERIOD_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_PERIOD_SHIFT) - -/* Bitfield definition for register array: TRGOCFG */ -/* - * OUTINV (RW) - * - * 1- Invert the output - */ -#define TRGM_TRGOCFG_OUTINV_MASK (0x40000UL) -#define TRGM_TRGOCFG_OUTINV_SHIFT (18U) -#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK) -#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT) - -/* - * FEDG2PEN (RW) - * - * 1- The selected input signal falling edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x20000UL) -#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (17U) -#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK) -#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT) - -/* - * REDG2PEN (RW) - * - * 1- The selected input signal rising edge will be convert to an pulse on output. - */ -#define TRGM_TRGOCFG_REDG2PEN_MASK (0x10000UL) -#define TRGM_TRGOCFG_REDG2PEN_SHIFT (16U) -#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK) -#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT) - -/* - * TRIGOSEL (RW) - * - * This bitfield selects one of the TRGM inputs as output. - */ -#define TRGM_TRGOCFG_TRIGOSEL_MASK (0xFFU) -#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U) -#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK) -#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT) - - - -/* FILTCFG register group index macro definition */ -#define TRGM_FILTCFG_PWM0_IN0 (0UL) -#define TRGM_FILTCFG_PWM0_IN1 (1UL) -#define TRGM_FILTCFG_PWM0_IN2 (2UL) -#define TRGM_FILTCFG_PWM0_IN3 (3UL) -#define TRGM_FILTCFG_PWM0_IN4 (4UL) -#define TRGM_FILTCFG_PWM0_IN5 (5UL) -#define TRGM_FILTCFG_PWM0_IN6 (6UL) -#define TRGM_FILTCFG_PWM0_IN7 (7UL) -#define TRGM_FILTCFG_PWM1_IN0 (8UL) -#define TRGM_FILTCFG_PWM1_IN1 (9UL) -#define TRGM_FILTCFG_PWM1_IN2 (10UL) -#define TRGM_FILTCFG_PWM1_IN3 (11UL) -#define TRGM_FILTCFG_PWM1_IN4 (12UL) -#define TRGM_FILTCFG_PWM1_IN5 (13UL) -#define TRGM_FILTCFG_PWM1_IN6 (14UL) -#define TRGM_FILTCFG_PWM1_IN7 (15UL) -#define TRGM_FILTCFG_PWM2_IN0 (16UL) -#define TRGM_FILTCFG_PWM2_IN1 (17UL) -#define TRGM_FILTCFG_PWM2_IN2 (18UL) -#define TRGM_FILTCFG_PWM2_IN3 (19UL) -#define TRGM_FILTCFG_PWM2_IN4 (20UL) -#define TRGM_FILTCFG_PWM2_IN5 (21UL) -#define TRGM_FILTCFG_PWM2_IN6 (22UL) -#define TRGM_FILTCFG_PWM2_IN7 (23UL) -#define TRGM_FILTCFG_PWM3_IN0 (24UL) -#define TRGM_FILTCFG_PWM3_IN1 (25UL) -#define TRGM_FILTCFG_PWM3_IN2 (26UL) -#define TRGM_FILTCFG_PWM3_IN3 (27UL) -#define TRGM_FILTCFG_PWM3_IN4 (28UL) -#define TRGM_FILTCFG_PWM3_IN5 (29UL) -#define TRGM_FILTCFG_PWM3_IN6 (30UL) -#define TRGM_FILTCFG_PWM3_IN7 (31UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN0 (32UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN1 (33UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN2 (34UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN3 (35UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN4 (36UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN5 (37UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN6 (38UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN7 (39UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN8 (40UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN9 (41UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN10 (42UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN11 (43UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN12 (44UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN13 (45UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN14 (46UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN15 (47UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN16 (48UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN17 (49UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN18 (50UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN19 (51UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN20 (52UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN21 (53UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN22 (54UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN23 (55UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN24 (56UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN25 (57UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN26 (58UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN27 (59UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN28 (60UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN29 (61UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN30 (62UL) -#define TRGM_FILTCFG_MOTO_GPIO_IN31 (63UL) - -/* DMACFG register group index macro definition */ -#define TRGM_DMACFG_0 (0UL) -#define TRGM_DMACFG_1 (1UL) -#define TRGM_DMACFG_2 (2UL) -#define TRGM_DMACFG_3 (3UL) -#define TRGM_DMACFG_4 (4UL) -#define TRGM_DMACFG_5 (5UL) -#define TRGM_DMACFG_6 (6UL) -#define TRGM_DMACFG_7 (7UL) - -/* TRGM_IN register group index macro definition */ -#define TRGM_TRGM_IN_0 (0UL) -#define TRGM_TRGM_IN_4 (0UL) -#define TRGM_TRGM_IN_1 (1UL) -#define TRGM_TRGM_IN_5 (1UL) -#define TRGM_TRGM_IN_2 (2UL) -#define TRGM_TRGM_IN_6 (2UL) -#define TRGM_TRGM_IN_3 (3UL) -#define TRGM_TRGM_IN_7 (3UL) - -/* TRGM_OUT register group index macro definition */ -#define TRGM_TRGM_OUT_0 (0UL) -#define TRGM_TRGM_OUT_1 (1UL) -#define TRGM_TRGM_OUT_2 (2UL) -#define TRGM_TRGM_OUT_3 (3UL) -#define TRGM_TRGM_OUT_4 (4UL) -#define TRGM_TRGM_OUT_5 (5UL) -#define TRGM_TRGM_OUT_6 (6UL) -#define TRGM_TRGM_OUT_7 (7UL) - -/* TRGOCFG register group index macro definition */ -#define TRGM_TRGOCFG_MOT_GPIO0 (0UL) -#define TRGM_TRGOCFG_MOT_GPIO1 (1UL) -#define TRGM_TRGOCFG_MOT_GPIO2 (2UL) -#define TRGM_TRGOCFG_MOT_GPIO3 (3UL) -#define TRGM_TRGOCFG_MOT_GPIO4 (4UL) -#define TRGM_TRGOCFG_MOT_GPIO5 (5UL) -#define TRGM_TRGOCFG_MOT_GPIO6 (6UL) -#define TRGM_TRGOCFG_MOT_GPIO7 (7UL) -#define TRGM_TRGOCFG_MOT_GPIO8 (8UL) -#define TRGM_TRGOCFG_MOT_GPIO9 (9UL) -#define TRGM_TRGOCFG_MOT_GPIO10 (10UL) -#define TRGM_TRGOCFG_MOT_GPIO11 (11UL) -#define TRGM_TRGOCFG_MOT_GPIO12 (12UL) -#define TRGM_TRGOCFG_MOT_GPIO13 (13UL) -#define TRGM_TRGOCFG_MOT_GPIO14 (14UL) -#define TRGM_TRGOCFG_MOT_GPIO15 (15UL) -#define TRGM_TRGOCFG_MOT_GPIO16 (16UL) -#define TRGM_TRGOCFG_MOT_GPIO17 (17UL) -#define TRGM_TRGOCFG_MOT_GPIO18 (18UL) -#define TRGM_TRGOCFG_MOT_GPIO19 (19UL) -#define TRGM_TRGOCFG_MOT_GPIO20 (20UL) -#define TRGM_TRGOCFG_MOT_GPIO21 (21UL) -#define TRGM_TRGOCFG_MOT_GPIO22 (22UL) -#define TRGM_TRGOCFG_MOT_GPIO23 (23UL) -#define TRGM_TRGOCFG_MOT_GPIO24 (24UL) -#define TRGM_TRGOCFG_MOT_GPIO25 (25UL) -#define TRGM_TRGOCFG_MOT_GPIO26 (26UL) -#define TRGM_TRGOCFG_MOT_GPIO27 (27UL) -#define TRGM_TRGOCFG_MOT_GPIO28 (28UL) -#define TRGM_TRGOCFG_MOT_GPIO29 (29UL) -#define TRGM_TRGOCFG_MOT_GPIO30 (30UL) -#define TRGM_TRGOCFG_MOT_GPIO31 (31UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC0 (32UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC1 (33UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC2 (34UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC3 (35UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC4 (36UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC5 (37UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC6 (38UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC7 (39UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC8 (40UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC9 (41UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC10 (42UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC11 (43UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC12 (44UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC13 (45UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC14 (46UL) -#define TRGM_TRGOCFG_SDM_PWM_SOC15 (47UL) -#define TRGM_TRGOCFG_ADC0_STRGI (48UL) -#define TRGM_TRGOCFG_ADC1_STRGI (49UL) -#define TRGM_TRGOCFG_ADC2_STRGI (50UL) -#define TRGM_TRGOCFG_ADC3_STRGI (51UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL) -#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL) -#define TRGM_TRGOCFG_ADCX_PTRGI1A (55UL) -#define TRGM_TRGOCFG_ADCX_PTRGI1B (56UL) -#define TRGM_TRGOCFG_ADCX_PTRGI1C (57UL) -#define TRGM_TRGOCFG_ADCX_PTRGI2A (58UL) -#define TRGM_TRGOCFG_ADCX_PTRGI2B (59UL) -#define TRGM_TRGOCFG_ADCX_PTRGI2C (60UL) -#define TRGM_TRGOCFG_ADCX_PTRGI3A (61UL) -#define TRGM_TRGOCFG_ADCX_PTRGI3B (62UL) -#define TRGM_TRGOCFG_ADCX_PTRGI3C (63UL) -#define TRGM_TRGOCFG_VSC0_TRIG_IN0 (64UL) -#define TRGM_TRGOCFG_VSC0_TRIG_IN1 (65UL) -#define TRGM_TRGOCFG_VSC1_TRIG_IN0 (66UL) -#define TRGM_TRGOCFG_VSC1_TRIG_IN1 (67UL) -#define TRGM_TRGOCFG_RDC0_TRIG_IN0 (68UL) -#define TRGM_TRGOCFG_RDC0_TRIG_IN1 (69UL) -#define TRGM_TRGOCFG_RDC1_TRIG_IN0 (70UL) -#define TRGM_TRGOCFG_RDC1_TRIG_IN1 (71UL) -#define TRGM_TRGOCFG_QEI0_TRIG_IN (72UL) -#define TRGM_TRGOCFG_QEI1_TRIG_IN (73UL) -#define TRGM_TRGOCFG_QEI2_TRIG_IN (74UL) -#define TRGM_TRGOCFG_QEI3_TRIG_IN (75UL) -#define TRGM_TRGOCFG_QEI0_PAUSE (76UL) -#define TRGM_TRGOCFG_QEI1_PAUSE (77UL) -#define TRGM_TRGOCFG_QEI2_PAUSE (78UL) -#define TRGM_TRGOCFG_QEI3_PAUSE (79UL) -#define TRGM_TRGOCFG_QEO0_TRIG_IN0 (80UL) -#define TRGM_TRGOCFG_QEO0_TRIG_IN1 (81UL) -#define TRGM_TRGOCFG_QEO1_TRIG_IN0 (82UL) -#define TRGM_TRGOCFG_QEO1_TRIG_IN1 (83UL) -#define TRGM_TRGOCFG_QEO2_TRIG_IN0 (84UL) -#define TRGM_TRGOCFG_QEO2_TRIG_IN1 (85UL) -#define TRGM_TRGOCFG_QEO3_TRIG_IN0 (86UL) -#define TRGM_TRGOCFG_QEO3_TRIG_IN1 (87UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN0 (88UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN1 (89UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN2 (90UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN3 (91UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN4 (92UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN5 (93UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN6 (94UL) -#define TRGM_TRGOCFG_SEI_TRIG_IN7 (95UL) -#define TRGM_TRGOCFG_CMP0_WIN (96UL) -#define TRGM_TRGOCFG_CMP1_WIN (97UL) -#define TRGM_TRGOCFG_CMP2_WIN (98UL) -#define TRGM_TRGOCFG_CMP3_WIN (99UL) -#define TRGM_TRGOCFG_CMP4_WIN (100UL) -#define TRGM_TRGOCFG_CMP5_WIN (101UL) -#define TRGM_TRGOCFG_CMP6_WIN (102UL) -#define TRGM_TRGOCFG_CMP7_WIN (103UL) -#define TRGM_TRGOCFG_GPTMR0_IN2 (104UL) -#define TRGM_TRGOCFG_GPTMR0_IN3 (105UL) -#define TRGM_TRGOCFG_GPTMR0_SYNCI (106UL) -#define TRGM_TRGOCFG_GPTMR1_IN2 (107UL) -#define TRGM_TRGOCFG_GPTMR1_IN3 (108UL) -#define TRGM_TRGOCFG_GPTMR1_SYNCI (109UL) -#define TRGM_TRGOCFG_GPTMR2_IN2 (110UL) -#define TRGM_TRGOCFG_GPTMR2_IN3 (111UL) -#define TRGM_TRGOCFG_GPTMR2_SYNCI (112UL) -#define TRGM_TRGOCFG_GPTMR3_IN2 (113UL) -#define TRGM_TRGOCFG_GPTMR3_IN3 (114UL) -#define TRGM_TRGOCFG_GPTMR3_SYNCI (115UL) -#define TRGM_TRGOCFG_GPTMR4_IN2 (116UL) -#define TRGM_TRGOCFG_GPTMR4_IN3 (117UL) -#define TRGM_TRGOCFG_GPTMR4_SYNCI (118UL) -#define TRGM_TRGOCFG_GPTMR5_IN2 (119UL) -#define TRGM_TRGOCFG_GPTMR5_IN3 (120UL) -#define TRGM_TRGOCFG_GPTMR5_SYNCI (121UL) -#define TRGM_TRGOCFG_GPTMR6_IN2 (122UL) -#define TRGM_TRGOCFG_GPTMR6_IN3 (123UL) -#define TRGM_TRGOCFG_GPTMR6_SYNCI (124UL) -#define TRGM_TRGOCFG_GPTMR7_IN2 (125UL) -#define TRGM_TRGOCFG_GPTMR7_IN3 (126UL) -#define TRGM_TRGOCFG_GPTMR7_SYNCI (127UL) -#define TRGM_TRGOCFG_PLB_IN_00 (128UL) -#define TRGM_TRGOCFG_PLB_IN_01 (129UL) -#define TRGM_TRGOCFG_PLB_IN_02 (130UL) -#define TRGM_TRGOCFG_PLB_IN_03 (131UL) -#define TRGM_TRGOCFG_PLB_IN_04 (132UL) -#define TRGM_TRGOCFG_PLB_IN_05 (133UL) -#define TRGM_TRGOCFG_PLB_IN_06 (134UL) -#define TRGM_TRGOCFG_PLB_IN_07 (135UL) -#define TRGM_TRGOCFG_PLB_IN_08 (136UL) -#define TRGM_TRGOCFG_PLB_IN_09 (137UL) -#define TRGM_TRGOCFG_PLB_IN_10 (138UL) -#define TRGM_TRGOCFG_PLB_IN_11 (139UL) -#define TRGM_TRGOCFG_PLB_IN_12 (140UL) -#define TRGM_TRGOCFG_PLB_IN_13 (141UL) -#define TRGM_TRGOCFG_PLB_IN_14 (142UL) -#define TRGM_TRGOCFG_PLB_IN_15 (143UL) -#define TRGM_TRGOCFG_PLB_IN_16 (144UL) -#define TRGM_TRGOCFG_PLB_IN_17 (145UL) -#define TRGM_TRGOCFG_PLB_IN_18 (146UL) -#define TRGM_TRGOCFG_PLB_IN_19 (147UL) -#define TRGM_TRGOCFG_PLB_IN_20 (148UL) -#define TRGM_TRGOCFG_PLB_IN_21 (149UL) -#define TRGM_TRGOCFG_PLB_IN_22 (150UL) -#define TRGM_TRGOCFG_PLB_IN_23 (151UL) -#define TRGM_TRGOCFG_PLB_IN_24 (152UL) -#define TRGM_TRGOCFG_PLB_IN_25 (153UL) -#define TRGM_TRGOCFG_PLB_IN_26 (154UL) -#define TRGM_TRGOCFG_PLB_IN_27 (155UL) -#define TRGM_TRGOCFG_PLB_IN_28 (156UL) -#define TRGM_TRGOCFG_PLB_IN_29 (157UL) -#define TRGM_TRGOCFG_PLB_IN_30 (158UL) -#define TRGM_TRGOCFG_PLB_IN_31 (159UL) -#define TRGM_TRGOCFG_PLB_IN_32 (160UL) -#define TRGM_TRGOCFG_PLB_IN_33 (161UL) -#define TRGM_TRGOCFG_PLB_IN_34 (162UL) -#define TRGM_TRGOCFG_PLB_IN_35 (163UL) -#define TRGM_TRGOCFG_PLB_IN_36 (164UL) -#define TRGM_TRGOCFG_PLB_IN_37 (165UL) -#define TRGM_TRGOCFG_PLB_IN_38 (166UL) -#define TRGM_TRGOCFG_PLB_IN_39 (167UL) -#define TRGM_TRGOCFG_PLB_IN_40 (168UL) -#define TRGM_TRGOCFG_PLB_IN_41 (169UL) -#define TRGM_TRGOCFG_PLB_IN_42 (170UL) -#define TRGM_TRGOCFG_PLB_IN_43 (171UL) -#define TRGM_TRGOCFG_PLB_IN_44 (172UL) -#define TRGM_TRGOCFG_PLB_IN_45 (173UL) -#define TRGM_TRGOCFG_PLB_IN_46 (174UL) -#define TRGM_TRGOCFG_PLB_IN_47 (175UL) -#define TRGM_TRGOCFG_PLB_IN_48 (176UL) -#define TRGM_TRGOCFG_PLB_IN_49 (177UL) -#define TRGM_TRGOCFG_PLB_IN_50 (178UL) -#define TRGM_TRGOCFG_PLB_IN_51 (179UL) -#define TRGM_TRGOCFG_PLB_IN_52 (180UL) -#define TRGM_TRGOCFG_PLB_IN_53 (181UL) -#define TRGM_TRGOCFG_PLB_IN_54 (182UL) -#define TRGM_TRGOCFG_PLB_IN_55 (183UL) -#define TRGM_TRGOCFG_PLB_IN_56 (184UL) -#define TRGM_TRGOCFG_PLB_IN_57 (185UL) -#define TRGM_TRGOCFG_PLB_IN_58 (186UL) -#define TRGM_TRGOCFG_PLB_IN_59 (187UL) -#define TRGM_TRGOCFG_PLB_IN_60 (188UL) -#define TRGM_TRGOCFG_PLB_IN_61 (189UL) -#define TRGM_TRGOCFG_PLB_IN_62 (190UL) -#define TRGM_TRGOCFG_PLB_IN_63 (191UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN0 (192UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN1 (193UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN2 (194UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN3 (195UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN4 (196UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN5 (197UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN6 (198UL) -#define TRGM_TRGOCFG_PWM0_TRIG_IN7 (199UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN0 (200UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN1 (201UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN2 (202UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN3 (203UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN4 (204UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN5 (205UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN6 (206UL) -#define TRGM_TRGOCFG_PWM1_TRIG_IN7 (207UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN0 (208UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN1 (209UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN2 (210UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN3 (211UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN4 (212UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN5 (213UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN6 (214UL) -#define TRGM_TRGOCFG_PWM2_TRIG_IN7 (215UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN0 (216UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN1 (217UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN2 (218UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN3 (219UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN4 (220UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN5 (221UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN6 (222UL) -#define TRGM_TRGOCFG_PWM3_TRIG_IN7 (223UL) -#define TRGM_TRGOCFG_CAN_PTPC0_CAP (224UL) -#define TRGM_TRGOCFG_CAN_PTPC1_CAP (225UL) -#define TRGM_TRGOCFG_UART_TRIG0 (226UL) -#define TRGM_TRGOCFG_UART_TRIG1 (227UL) -#define TRGM_TRGOCFG_SYNCTIMER_TRIG (228UL) -#define TRGM_TRGOCFG_TRGM_IRQ0 (229UL) -#define TRGM_TRGOCFG_TRGM_IRQ1 (230UL) -#define TRGM_TRGOCFG_TRGM_DMA0 (231UL) -#define TRGM_TRGOCFG_TRGM_DMA1 (232UL) -#define TRGM_TRGOCFG_MTG0_TRIG_IN0 (233UL) -#define TRGM_TRGOCFG_MTG0_TRIG_IN1 (234UL) -#define TRGM_TRGOCFG_MTG0_TRIG_IN2 (235UL) -#define TRGM_TRGOCFG_MTG0_TRIG_IN3 (236UL) -#define TRGM_TRGOCFG_MTG1_TRIG_IN0 (237UL) -#define TRGM_TRGOCFG_MTG1_TRIG_IN1 (238UL) -#define TRGM_TRGOCFG_MTG1_TRIG_IN2 (239UL) -#define TRGM_TRGOCFG_MTG1_TRIG_IN3 (240UL) -#define TRGM_TRGOCFG_ESC_TRIG_IN (241UL) - - -#endif /* HPM_TRGM_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tsns_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tsns_regs.h deleted file mode 100644 index fcaf224c309..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tsns_regs.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSNS_H -#define HPM_TSNS_H - -typedef struct { - __R uint32_t T; /* 0x0: Temperature */ - __R uint32_t TMAX; /* 0x4: Maximum Temperature */ - __R uint32_t TMIN; /* 0x8: Minimum Temperature */ - __R uint32_t AGE; /* 0xC: Sample age */ - __RW uint32_t STATUS; /* 0x10: Status */ - __RW uint32_t CONFIG; /* 0x14: Configuration */ - __RW uint32_t VALIDITY; /* 0x18: Sample validity */ - __RW uint32_t FLAG; /* 0x1C: Temperature flag */ - __RW uint32_t UPPER_LIM_IRQ; /* 0x20: Maximum temperature to interrupt */ - __RW uint32_t LOWER_LIM_IRQ; /* 0x24: Minimum temperature to interrupt */ - __RW uint32_t UPPER_LIM_RST; /* 0x28: Maximum temperature to reset */ - __RW uint32_t LOWER_LIM_RST; /* 0x2C: Minimum temperature to reset */ - __RW uint32_t ASYNC; /* 0x30: Configuration in asynchronous mode */ - __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */ - __RW uint32_t ADVAN; /* 0x38: Advance configuration */ -} TSNS_Type; - - -/* Bitfield definition for register: T */ -/* - * T (RO) - * - * Signed number of temperature in 256 x celsius degree - */ -#define TSNS_T_T_MASK (0xFFFFFFFFUL) -#define TSNS_T_T_SHIFT (0U) -#define TSNS_T_T_GET(x) (((uint32_t)(x) & TSNS_T_T_MASK) >> TSNS_T_T_SHIFT) - -/* Bitfield definition for register: TMAX */ -/* - * T (RO) - * - * maximum temperature ever found - */ -#define TSNS_TMAX_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMAX_T_SHIFT (0U) -#define TSNS_TMAX_T_GET(x) (((uint32_t)(x) & TSNS_TMAX_T_MASK) >> TSNS_TMAX_T_SHIFT) - -/* Bitfield definition for register: TMIN */ -/* - * T (RO) - * - * minimum temperature ever found - */ -#define TSNS_TMIN_T_MASK (0xFFFFFFFFUL) -#define TSNS_TMIN_T_SHIFT (0U) -#define TSNS_TMIN_T_GET(x) (((uint32_t)(x) & TSNS_TMIN_T_MASK) >> TSNS_TMIN_T_SHIFT) - -/* Bitfield definition for register: AGE */ -/* - * AGE (RO) - * - * age of T register in 24MHz clock cycles - */ -#define TSNS_AGE_AGE_MASK (0xFFFFFFFFUL) -#define TSNS_AGE_AGE_SHIFT (0U) -#define TSNS_AGE_AGE_GET(x) (((uint32_t)(x) & TSNS_AGE_AGE_MASK) >> TSNS_AGE_AGE_SHIFT) - -/* Bitfield definition for register: STATUS */ -/* - * VALID (RO) - * - * indicate value in T is valid or not - * 0: not valid - * 1:valid - */ -#define TSNS_STATUS_VALID_MASK (0x80000000UL) -#define TSNS_STATUS_VALID_SHIFT (31U) -#define TSNS_STATUS_VALID_GET(x) (((uint32_t)(x) & TSNS_STATUS_VALID_MASK) >> TSNS_STATUS_VALID_SHIFT) - -/* - * TRIGGER (W1C) - * - * Software trigger for sensing in trigger mode, trigger will be ignored if in sensing or other mode - */ -#define TSNS_STATUS_TRIGGER_MASK (0x1U) -#define TSNS_STATUS_TRIGGER_SHIFT (0U) -#define TSNS_STATUS_TRIGGER_SET(x) (((uint32_t)(x) << TSNS_STATUS_TRIGGER_SHIFT) & TSNS_STATUS_TRIGGER_MASK) -#define TSNS_STATUS_TRIGGER_GET(x) (((uint32_t)(x) & TSNS_STATUS_TRIGGER_MASK) >> TSNS_STATUS_TRIGGER_SHIFT) - -/* Bitfield definition for register: CONFIG */ -/* - * IRQ_EN (RW) - * - * Enable interrupt - */ -#define TSNS_CONFIG_IRQ_EN_MASK (0x80000000UL) -#define TSNS_CONFIG_IRQ_EN_SHIFT (31U) -#define TSNS_CONFIG_IRQ_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_IRQ_EN_SHIFT) & TSNS_CONFIG_IRQ_EN_MASK) -#define TSNS_CONFIG_IRQ_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_IRQ_EN_MASK) >> TSNS_CONFIG_IRQ_EN_SHIFT) - -/* - * RST_EN (RW) - * - * Enable reset - */ -#define TSNS_CONFIG_RST_EN_MASK (0x40000000UL) -#define TSNS_CONFIG_RST_EN_SHIFT (30U) -#define TSNS_CONFIG_RST_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_RST_EN_SHIFT) & TSNS_CONFIG_RST_EN_MASK) -#define TSNS_CONFIG_RST_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_RST_EN_MASK) >> TSNS_CONFIG_RST_EN_SHIFT) - -/* - * COMPARE_MIN_EN (RW) - * - * Enable compare for minimum temperature - */ -#define TSNS_CONFIG_COMPARE_MIN_EN_MASK (0x2000000UL) -#define TSNS_CONFIG_COMPARE_MIN_EN_SHIFT (25U) -#define TSNS_CONFIG_COMPARE_MIN_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) -#define TSNS_CONFIG_COMPARE_MIN_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MIN_EN_MASK) >> TSNS_CONFIG_COMPARE_MIN_EN_SHIFT) - -/* - * COMPARE_MAX_EN (RW) - * - * Enable compare for maximum temperature - */ -#define TSNS_CONFIG_COMPARE_MAX_EN_MASK (0x1000000UL) -#define TSNS_CONFIG_COMPARE_MAX_EN_SHIFT (24U) -#define TSNS_CONFIG_COMPARE_MAX_EN_SET(x) (((uint32_t)(x) << TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) -#define TSNS_CONFIG_COMPARE_MAX_EN_GET(x) (((uint32_t)(x) & TSNS_CONFIG_COMPARE_MAX_EN_MASK) >> TSNS_CONFIG_COMPARE_MAX_EN_SHIFT) - -/* - * SPEED (RW) - * - * cycles of a progressive step in 24M clock, valid from 24-255, default 96 - * 24: 24 cycle for a step - * 25: 25 cycle for a step - * 26: 26 cycle for a step - * ... - * 255: 255 cycle for a step - */ -#define TSNS_CONFIG_SPEED_MASK (0xFF0000UL) -#define TSNS_CONFIG_SPEED_SHIFT (16U) -#define TSNS_CONFIG_SPEED_SET(x) (((uint32_t)(x) << TSNS_CONFIG_SPEED_SHIFT) & TSNS_CONFIG_SPEED_MASK) -#define TSNS_CONFIG_SPEED_GET(x) (((uint32_t)(x) & TSNS_CONFIG_SPEED_MASK) >> TSNS_CONFIG_SPEED_SHIFT) - -/* - * AVERAGE (RW) - * - * Average time, default in 3 - * 0: measure and return - * 1: twice and average - * 2: 4 times and average - * . . . - * 7: 128 times and average - */ -#define TSNS_CONFIG_AVERAGE_MASK (0x700U) -#define TSNS_CONFIG_AVERAGE_SHIFT (8U) -#define TSNS_CONFIG_AVERAGE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_AVERAGE_SHIFT) & TSNS_CONFIG_AVERAGE_MASK) -#define TSNS_CONFIG_AVERAGE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_AVERAGE_MASK) >> TSNS_CONFIG_AVERAGE_SHIFT) - -/* - * CONTINUOUS (RW) - * - * continuous mode that keep sampling temperature peridically - * 0: trigger mode - * 1: continuous mode - */ -#define TSNS_CONFIG_CONTINUOUS_MASK (0x10U) -#define TSNS_CONFIG_CONTINUOUS_SHIFT (4U) -#define TSNS_CONFIG_CONTINUOUS_SET(x) (((uint32_t)(x) << TSNS_CONFIG_CONTINUOUS_SHIFT) & TSNS_CONFIG_CONTINUOUS_MASK) -#define TSNS_CONFIG_CONTINUOUS_GET(x) (((uint32_t)(x) & TSNS_CONFIG_CONTINUOUS_MASK) >> TSNS_CONFIG_CONTINUOUS_SHIFT) - -/* - * ASYNC (RW) - * - * Acynchronous mode, this mode can work without clock, only available function ios compare to certain ADC value - * 0: active mode - * 1: Async mode - */ -#define TSNS_CONFIG_ASYNC_MASK (0x2U) -#define TSNS_CONFIG_ASYNC_SHIFT (1U) -#define TSNS_CONFIG_ASYNC_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ASYNC_SHIFT) & TSNS_CONFIG_ASYNC_MASK) -#define TSNS_CONFIG_ASYNC_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ASYNC_MASK) >> TSNS_CONFIG_ASYNC_SHIFT) - -/* - * ENABLE (RW) - * - * Enable temperature - * 0: disable, temperature sensor is shut down - * 1: enable. Temperature sensor enabled - */ -#define TSNS_CONFIG_ENABLE_MASK (0x1U) -#define TSNS_CONFIG_ENABLE_SHIFT (0U) -#define TSNS_CONFIG_ENABLE_SET(x) (((uint32_t)(x) << TSNS_CONFIG_ENABLE_SHIFT) & TSNS_CONFIG_ENABLE_MASK) -#define TSNS_CONFIG_ENABLE_GET(x) (((uint32_t)(x) & TSNS_CONFIG_ENABLE_MASK) >> TSNS_CONFIG_ENABLE_SHIFT) - -/* Bitfield definition for register: VALIDITY */ -/* - * VALIDITY (RW) - * - * time for temperature values to expire in 24M clock cycles - */ -#define TSNS_VALIDITY_VALIDITY_MASK (0xFFFFFFFFUL) -#define TSNS_VALIDITY_VALIDITY_SHIFT (0U) -#define TSNS_VALIDITY_VALIDITY_SET(x) (((uint32_t)(x) << TSNS_VALIDITY_VALIDITY_SHIFT) & TSNS_VALIDITY_VALIDITY_MASK) -#define TSNS_VALIDITY_VALIDITY_GET(x) (((uint32_t)(x) & TSNS_VALIDITY_VALIDITY_MASK) >> TSNS_VALIDITY_VALIDITY_SHIFT) - -/* Bitfield definition for register: FLAG */ -/* - * RECORD_MIN_CLR (RW) - * - * Clear minimum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MIN_CLR_MASK (0x200000UL) -#define TSNS_FLAG_RECORD_MIN_CLR_SHIFT (21U) -#define TSNS_FLAG_RECORD_MIN_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MIN_CLR_SHIFT) & TSNS_FLAG_RECORD_MIN_CLR_MASK) -#define TSNS_FLAG_RECORD_MIN_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MIN_CLR_MASK) >> TSNS_FLAG_RECORD_MIN_CLR_SHIFT) - -/* - * RECORD_MAX_CLR (RW) - * - * Clear maximum recorder of temerature, write 1 to clear - */ -#define TSNS_FLAG_RECORD_MAX_CLR_MASK (0x100000UL) -#define TSNS_FLAG_RECORD_MAX_CLR_SHIFT (20U) -#define TSNS_FLAG_RECORD_MAX_CLR_SET(x) (((uint32_t)(x) << TSNS_FLAG_RECORD_MAX_CLR_SHIFT) & TSNS_FLAG_RECORD_MAX_CLR_MASK) -#define TSNS_FLAG_RECORD_MAX_CLR_GET(x) (((uint32_t)(x) & TSNS_FLAG_RECORD_MAX_CLR_MASK) >> TSNS_FLAG_RECORD_MAX_CLR_SHIFT) - -/* - * UNDER_TEMP (RW) - * - * Clear under temperature status, write 1 to clear - */ -#define TSNS_FLAG_UNDER_TEMP_MASK (0x20000UL) -#define TSNS_FLAG_UNDER_TEMP_SHIFT (17U) -#define TSNS_FLAG_UNDER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_UNDER_TEMP_SHIFT) & TSNS_FLAG_UNDER_TEMP_MASK) -#define TSNS_FLAG_UNDER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_UNDER_TEMP_MASK) >> TSNS_FLAG_UNDER_TEMP_SHIFT) - -/* - * OVER_TEMP (RW) - * - * Clear over temperature status, write 1 to clear - */ -#define TSNS_FLAG_OVER_TEMP_MASK (0x10000UL) -#define TSNS_FLAG_OVER_TEMP_SHIFT (16U) -#define TSNS_FLAG_OVER_TEMP_SET(x) (((uint32_t)(x) << TSNS_FLAG_OVER_TEMP_SHIFT) & TSNS_FLAG_OVER_TEMP_MASK) -#define TSNS_FLAG_OVER_TEMP_GET(x) (((uint32_t)(x) & TSNS_FLAG_OVER_TEMP_MASK) >> TSNS_FLAG_OVER_TEMP_SHIFT) - -/* - * IRQ (RW) - * - * IRQ flag, write 1 to clear - */ -#define TSNS_FLAG_IRQ_MASK (0x1U) -#define TSNS_FLAG_IRQ_SHIFT (0U) -#define TSNS_FLAG_IRQ_SET(x) (((uint32_t)(x) << TSNS_FLAG_IRQ_SHIFT) & TSNS_FLAG_IRQ_MASK) -#define TSNS_FLAG_IRQ_GET(x) (((uint32_t)(x) & TSNS_FLAG_IRQ_MASK) >> TSNS_FLAG_IRQ_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_IRQ */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_UPPER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_IRQ_T_SHIFT) & TSNS_UPPER_LIM_IRQ_T_MASK) -#define TSNS_UPPER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_IRQ_T_MASK) >> TSNS_UPPER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_IRQ */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_IRQ_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_IRQ_T_SHIFT (0U) -#define TSNS_LOWER_LIM_IRQ_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_IRQ_T_SHIFT) & TSNS_LOWER_LIM_IRQ_T_MASK) -#define TSNS_LOWER_LIM_IRQ_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_IRQ_T_MASK) >> TSNS_LOWER_LIM_IRQ_T_SHIFT) - -/* Bitfield definition for register: UPPER_LIM_RST */ -/* - * T (RW) - * - * Maximum temperature for compare - */ -#define TSNS_UPPER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_UPPER_LIM_RST_T_SHIFT (0U) -#define TSNS_UPPER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_UPPER_LIM_RST_T_SHIFT) & TSNS_UPPER_LIM_RST_T_MASK) -#define TSNS_UPPER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_UPPER_LIM_RST_T_MASK) >> TSNS_UPPER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: LOWER_LIM_RST */ -/* - * T (RW) - * - * Minimum temperature for compare - */ -#define TSNS_LOWER_LIM_RST_T_MASK (0xFFFFFFFFUL) -#define TSNS_LOWER_LIM_RST_T_SHIFT (0U) -#define TSNS_LOWER_LIM_RST_T_SET(x) (((uint32_t)(x) << TSNS_LOWER_LIM_RST_T_SHIFT) & TSNS_LOWER_LIM_RST_T_MASK) -#define TSNS_LOWER_LIM_RST_T_GET(x) (((uint32_t)(x) & TSNS_LOWER_LIM_RST_T_MASK) >> TSNS_LOWER_LIM_RST_T_SHIFT) - -/* Bitfield definition for register: ASYNC */ -/* - * ASYNC_TYPE (RW) - * - * Compare hotter than or colder than in asynchoronous mode - * 0: hotter than - * 1: colder than - */ -#define TSNS_ASYNC_ASYNC_TYPE_MASK (0x1000000UL) -#define TSNS_ASYNC_ASYNC_TYPE_SHIFT (24U) -#define TSNS_ASYNC_ASYNC_TYPE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_ASYNC_TYPE_SHIFT) & TSNS_ASYNC_ASYNC_TYPE_MASK) -#define TSNS_ASYNC_ASYNC_TYPE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_ASYNC_TYPE_MASK) >> TSNS_ASYNC_ASYNC_TYPE_SHIFT) - -/* - * POLARITY (RW) - * - * Polarity of internal comparator - */ -#define TSNS_ASYNC_POLARITY_MASK (0x10000UL) -#define TSNS_ASYNC_POLARITY_SHIFT (16U) -#define TSNS_ASYNC_POLARITY_SET(x) (((uint32_t)(x) << TSNS_ASYNC_POLARITY_SHIFT) & TSNS_ASYNC_POLARITY_MASK) -#define TSNS_ASYNC_POLARITY_GET(x) (((uint32_t)(x) & TSNS_ASYNC_POLARITY_MASK) >> TSNS_ASYNC_POLARITY_SHIFT) - -/* - * VALUE (RW) - * - * Value of async mode to compare - */ -#define TSNS_ASYNC_VALUE_MASK (0x7FFU) -#define TSNS_ASYNC_VALUE_SHIFT (0U) -#define TSNS_ASYNC_VALUE_SET(x) (((uint32_t)(x) << TSNS_ASYNC_VALUE_SHIFT) & TSNS_ASYNC_VALUE_MASK) -#define TSNS_ASYNC_VALUE_GET(x) (((uint32_t)(x) & TSNS_ASYNC_VALUE_MASK) >> TSNS_ASYNC_VALUE_SHIFT) - -/* Bitfield definition for register: ADVAN */ -/* - * ASYNC_IRQ (RO) - * - * interrupt status of asynchronous mode - */ -#define TSNS_ADVAN_ASYNC_IRQ_MASK (0x2000000UL) -#define TSNS_ADVAN_ASYNC_IRQ_SHIFT (25U) -#define TSNS_ADVAN_ASYNC_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ASYNC_IRQ_MASK) >> TSNS_ADVAN_ASYNC_IRQ_SHIFT) - -/* - * ACTIVE_IRQ (RO) - * - * interrupt status of active mode - */ -#define TSNS_ADVAN_ACTIVE_IRQ_MASK (0x1000000UL) -#define TSNS_ADVAN_ACTIVE_IRQ_SHIFT (24U) -#define TSNS_ADVAN_ACTIVE_IRQ_GET(x) (((uint32_t)(x) & TSNS_ADVAN_ACTIVE_IRQ_MASK) >> TSNS_ADVAN_ACTIVE_IRQ_SHIFT) - -/* - * SAMPLING (RO) - * - * temperature sampling is working - */ -#define TSNS_ADVAN_SAMPLING_MASK (0x10000UL) -#define TSNS_ADVAN_SAMPLING_SHIFT (16U) -#define TSNS_ADVAN_SAMPLING_GET(x) (((uint32_t)(x) & TSNS_ADVAN_SAMPLING_MASK) >> TSNS_ADVAN_SAMPLING_SHIFT) - -/* - * NEG_ONLY (RW) - * - * use negative compare polarity only - */ -#define TSNS_ADVAN_NEG_ONLY_MASK (0x2U) -#define TSNS_ADVAN_NEG_ONLY_SHIFT (1U) -#define TSNS_ADVAN_NEG_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_NEG_ONLY_SHIFT) & TSNS_ADVAN_NEG_ONLY_MASK) -#define TSNS_ADVAN_NEG_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_NEG_ONLY_MASK) >> TSNS_ADVAN_NEG_ONLY_SHIFT) - -/* - * POS_ONLY (RW) - * - * use positive compare polarity only - */ -#define TSNS_ADVAN_POS_ONLY_MASK (0x1U) -#define TSNS_ADVAN_POS_ONLY_SHIFT (0U) -#define TSNS_ADVAN_POS_ONLY_SET(x) (((uint32_t)(x) << TSNS_ADVAN_POS_ONLY_SHIFT) & TSNS_ADVAN_POS_ONLY_MASK) -#define TSNS_ADVAN_POS_ONLY_GET(x) (((uint32_t)(x) & TSNS_ADVAN_POS_ONLY_MASK) >> TSNS_ADVAN_POS_ONLY_SHIFT) - - - - -#endif /* HPM_TSNS_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tsw_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tsw_regs.h deleted file mode 100644 index 19d825d0dde..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_tsw_regs.h +++ /dev/null @@ -1,8154 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_TSW_H -#define HPM_TSW_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t LU_MAIN_CTRL; /* 0x4: LU_MAIN control */ - __RW uint32_t LU_MAIN_HITMEM; /* 0x8: LU_MAIN hit */ - __R uint32_t LU_MAIN_PARAM; /* 0xC: LU_MAIN parameter */ - __RW uint32_t LU_MAIN_BYPASS; /* 0x10: LU_MAIN bypass */ - __RW uint32_t LU_MAIN_PCP_REMAP; /* 0x14: LU_MAIN PCP remap */ - __R uint32_t LU_MAIN_VERSION; /* 0x18: LU_MAIN version */ - __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */ - __RW uint32_t LU_MAIN_INTF_ACTION; /* 0x20: LU_MAIN low word of action data for internal frames */ - __R uint8_t RESERVED2[4]; /* 0x24 - 0x27: Reserved */ - __RW uint32_t LU_MAIN_BC_ACTION; /* 0x28: LU_MAIN low word of action data for broadcast frames */ - __R uint8_t RESERVED3[4]; /* 0x2C - 0x2F: Reserved */ - __RW uint32_t LU_MAIN_NN_ACTION; /* 0x30: LU_MAIN low word of action data for unknown frames */ - __R uint8_t RESERVED4[204]; /* 0x34 - 0xFF: Reserved */ - __R uint32_t APB2AXIS_CAM_STS; /* 0x100: status register */ - __R uint8_t RESERVED5[12]; /* 0x104 - 0x10F: Reserved */ - __R uint32_t APB2AXIS_CAM_REQ_CNT; /* 0x110: request count */ - __R uint32_t APB2AXIS_CAM_FILLSTS; /* 0x114: fill status */ - __W uint32_t APB2AXIS_CAM_RESET; /* 0x118: reset */ - __R uint32_t APB2AXIS_CAM_PARAM; /* 0x11C: parameter */ - __RW uint32_t APB2AXI_CAM_REQDATA_0; /* 0x120: data0 */ - __RW uint32_t APB2AXI_CAM_REQDATA_1; /* 0x124: data1 */ - __RW uint32_t APB2AXI_CAM_REQDATA_2; /* 0x128: data2 */ - __R uint8_t RESERVED6[212]; /* 0x12C - 0x1FF: Reserved */ - __R uint32_t APB2AXIS_ALMEM_STS; /* 0x200: status register */ - __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */ - __R uint32_t APB2AXIS_ALMEM_REQ_CNT; /* 0x210: request count */ - __R uint32_t APB2AXIS_ALMEM_FILLSTS; /* 0x214: fill status */ - __W uint32_t APB2AXIS_ALMEM_RESET; /* 0x218: reset */ - __R uint32_t APB2AXIS_ALMEM_PARAM; /* 0x21C: parameter */ - __RW uint32_t APB2AXIS_ALMEM_REQDATA_0; /* 0x220: data0 */ - __RW uint32_t APB2AXIS_ALMEM_REQDATA_1; /* 0x224: data1 */ - __R uint8_t RESERVED8[88]; /* 0x228 - 0x27F: Reserved */ - __R uint32_t AXIS2APB_ALMEM_STS; /* 0x280: status register */ - __R uint8_t RESERVED9[12]; /* 0x284 - 0x28F: Reserved */ - __R uint32_t AXIS2APB_ALMEM_RESP_CNT; /* 0x290: response count */ - __R uint32_t AXIS2APB_ALMEM_FILLSTS; /* 0x294: fill status */ - __RW uint32_t AXIS2APB_ALMEM_RESET; /* 0x298: reset */ - __R uint32_t AXIS2APB_ALMEM_PARAM; /* 0x29C: parameter */ - __RW uint32_t AXIS2APB_ALMEM_RESPDATA_0; /* 0x2A0: data0 */ - __RW uint32_t AXIS2APB_ALMEM_RESPDATA_1; /* 0x2A4: data1 */ - __R uint8_t RESERVED10[344]; /* 0x2A8 - 0x3FF: Reserved */ - __RW uint32_t HITMEM[4]; /* 0x400 - 0x40C: hitmem */ - __R uint8_t RESERVED11[3056]; /* 0x410 - 0xFFF: Reserved */ - __R uint32_t APB2AXIS_LOOKUP_STS; /* 0x1000: status register */ - __R uint8_t RESERVED12[12]; /* 0x1004 - 0x100F: Reserved */ - __R uint32_t APB2AXIS_LOOKUP_REQ_CNT; /* 0x1010: response count */ - __R uint32_t APB2AXIS_LOOKUP_FILLSTS; /* 0x1014: fill status */ - __RW uint32_t APB2AXIS_LOOKUP_RESET; /* 0x1018: reset */ - __R uint32_t APB2AXIS_LOOKUP_PARAM; /* 0x101C: parameter */ - __RW uint32_t APB2AXIS_LOOKUP_REQDATA_0; /* 0x1020: LOOKUP REQUEST Register REQ_DATA_0 */ - __RW uint32_t APB2AXIS_LOOKUP_REQDATA_1; /* 0x1024: LOOKUP REQUEST Register REQ_DATA_1 */ - __R uint8_t RESERVED13[4]; /* 0x1028 - 0x102B: Reserved */ - __RW uint32_t APB2AXIS_LOOKUP_REQDATA_3; /* 0x102C: LOOKUP REQUEST Register REQ_DATA_2 */ - __R uint8_t RESERVED14[80]; /* 0x1030 - 0x107F: Reserved */ - __R uint32_t AXIS2APB_LOOKUP_STS; /* 0x1080: status register */ - __R uint8_t RESERVED15[12]; /* 0x1084 - 0x108F: Reserved */ - __R uint32_t AXIS2APB_LOOKUP_RESP_CNT; /* 0x1090: response count */ - __R uint32_t AXIS2APB_LOOKUP_FILLSTS; /* 0x1094: fill status */ - __RW uint32_t AXIS2APB_LOOKUP_RESET; /* 0x1098: reset */ - __R uint32_t AXIS2APB_LOOKUP_PARAM; /* 0x109C: parameter */ - __RW uint32_t AXIS2APB_LOOKUP_RESPDATA_0; /* 0x10A0: LOOKUP RESPONSE Data Register */ - __R uint8_t RESERVED16[4]; /* 0x10A4 - 0x10A7: Reserved */ - __RW uint32_t AXIS2APB_LOOKUP_RESPDATA_1; /* 0x10A8: LOOKUP RESPONSE Data Register */ - __R uint8_t RESERVED17[3924]; /* 0x10AC - 0x1FFF: Reserved */ - __R uint32_t CENTRAL_CSR_VERSION; /* 0x2000: version register */ - __R uint32_t CENTRAL_CSR_PARAM; /* 0x2004: Parameter Register */ - __RW uint32_t CENTRAL_CSR_CONFIG; /* 0x2008: Configuration Register */ - __R uint32_t CENTRAL_CSR_CB_PARAM; /* 0x200C: CB Parameter Register */ - __R uint32_t CENTRAL_CSR_QCI_CTRL_PARAM; /* 0x2010: QCI Control Parameter Register */ - __R uint8_t RESERVED18[240]; /* 0x2014 - 0x2103: Reserved */ - __R uint32_t CENTRAL_QCI_HWCFG; /* 0x2104: PSPF General CTRAL */ - __R uint8_t RESERVED19[8]; /* 0x2108 - 0x210F: Reserved */ - __RW uint32_t CENTRAL_QCI_FILTERSEL; /* 0x2110: Filter select index */ - __RW uint32_t CENTRAL_QCI_METERSEL; /* 0x2114: Flowmeter select index */ - __RW uint32_t CENTRAL_QCI_GATESEL; /* 0x2118: Gate select index */ - __R uint8_t RESERVED20[4]; /* 0x211C - 0x211F: Reserved */ - __RW uint32_t CENTRAL_QCI_FCTRL; /* 0x2120: FILTER SETTING */ - __RW uint32_t CENTRAL_QCI_FSIZE; /* 0x2124: */ - __R uint8_t RESERVED21[24]; /* 0x2128 - 0x213F: Reserved */ - __R uint32_t QCI_CNT[6]; /* 0x2140 - 0x2154: FILTER COUNTER */ - __R uint8_t RESERVED22[8]; /* 0x2158 - 0x215F: Reserved */ - __RW uint32_t CENTRAL_QCI_MCTRL; /* 0x2160: Flow meter settings */ - __R uint8_t RESERVED23[12]; /* 0x2164 - 0x216F: Reserved */ - __RW uint32_t CENTRAL_QCI_CIR; /* 0x2170: */ - __RW uint32_t CENTRAL_QCI_CBS; /* 0x2174: */ - __RW uint32_t CENTRAL_QCI_EIR; /* 0x2178: */ - __RW uint32_t CENTRAL_QCI_EBS; /* 0x217C: */ - __RW uint32_t CENTRAL_QCI_GCTRL; /* 0x2180: Gate settings */ - __RW uint32_t CENTRAL_QCI_GSTATUS; /* 0x2184: */ - __RW uint32_t CENTRAL_QCI_GLISTINDEX; /* 0x2188: */ - __RW uint32_t CENTRAL_QCI_LISTLEN; /* 0x218C: */ - __RW uint32_t CENTRAL_QCI_ACYCLETM; /* 0x2190: */ - __RW uint32_t CENTRAL_QCI_ABASETM_L; /* 0x2194: */ - __RW uint32_t CENTRAL_QCI_ABASETM_H; /* 0x2198: */ - __R uint8_t RESERVED24[4]; /* 0x219C - 0x219F: Reserved */ - __RW uint32_t CENTRAL_QCI_AENTRY_CTRL; /* 0x21A0: */ - __RW uint32_t CENTRAL_QCI_AENTRY_AENTRY_IVAL; /* 0x21A4: */ - __R uint32_t CENTRAL_QCI_AENTRY_OCYCLETM; /* 0x21A8: */ - __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_L;/* 0x21AC: */ - __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_H;/* 0x21B0: */ - __R uint8_t RESERVED25[7756]; /* 0x21B4 - 0x3FFF: Reserved */ - __RW uint32_t MM2S_DMA_CR; /* 0x4000: mm2s control register */ - __RW uint32_t MM2S_DMA_SR; /* 0x4004: mm2s status */ - __R uint32_t MM2S_DMA_FILL; /* 0x4008: mm2s dma fill status */ - __R uint8_t RESERVED26[16]; /* 0x400C - 0x401B: Reserved */ - __R uint32_t MM2S_DMA_CFG; /* 0x401C: mm2s dma configure */ - __RW uint32_t MM2S_ADDRLO; /* 0x4020: mm2s axi address */ - __R uint8_t RESERVED27[4]; /* 0x4024 - 0x4027: Reserved */ - __RW uint32_t MM2S_LENGTH; /* 0x4028: mm2s axi length */ - __RW uint32_t MM2S_CTRL; /* 0x402C: mm2s command control */ - __R uint32_t MM2S_RESP; /* 0x4030: mm2s response buffer */ - __R uint8_t RESERVED28[76]; /* 0x4034 - 0x407F: Reserved */ - __RW uint32_t S2MM_DMA_CR; /* 0x4080: s2mm dma control */ - __RW uint32_t S2MM_DMA_SR; /* 0x4084: s2mm state */ - __R uint32_t S2MM_DMA_FILL; /* 0x4088: s2mm buffer fill status */ - __R uint8_t RESERVED29[16]; /* 0x408C - 0x409B: Reserved */ - __R uint32_t S2MM_DMA_CFG; /* 0x409C: s2mm dma config status */ - __RW uint32_t S2MM_ADDRLO; /* 0x40A0: s2mm axi address */ - __R uint8_t RESERVED30[4]; /* 0x40A4 - 0x40A7: Reserved */ - __RW uint32_t S2MM_LENGTH; /* 0x40A8: s2mm axi length */ - __RW uint32_t S2MM_CTRL; /* 0x40AC: s2mm command control */ - __R uint32_t S2MM_RESP; /* 0x40B0: s2mm response buffer */ - __R uint8_t RESERVED31[8012]; /* 0x40B4 - 0x5FFF: Reserved */ - __RW uint32_t PTP_EVT_TS_CTL; /* 0x6000: timestamp control */ - __R uint8_t RESERVED32[4]; /* 0x6004 - 0x6007: Reserved */ - __R uint32_t PTP_EVT_PPS_TOD_SEC; /* 0x6008: pps tod seconds */ - __R uint32_t PTP_EVT_PPS_TOD_NS; /* 0x600C: pps tod sun seconds */ - __R uint8_t RESERVED33[12]; /* 0x6010 - 0x601B: Reserved */ - __RW uint32_t PTP_EVT_SCP_SEC0; /* 0x601C: target time seconds */ - __RW uint32_t PTP_EVT_SCP_NS0; /* 0x6020: target time sub seconds */ - __R uint8_t RESERVED34[4]; /* 0x6024 - 0x6027: Reserved */ - __R uint32_t PTP_EVT_TMR_STS; /* 0x6028: timer status */ - __RW uint32_t PTP_EVT_PPS_CMD; /* 0x602C: pps command control */ - __R uint32_t PTP_EVT_ATSLO; /* 0x6030: auxiliray read data sub seconds */ - __R uint32_t PTP_EVT_ATSHI; /* 0x6034: auxiliray read data seconds */ - __R uint8_t RESERVED35[40]; /* 0x6038 - 0x605F: Reserved */ - __RW uint32_t PTP_EVT_PPS0_INTERVAL; /* 0x6060: pps0 interval configure */ - __RW uint32_t PTP_EVT_PPS0_WIDTH; /* 0x6064: pps0 width configure */ - __R uint8_t RESERVED36[24]; /* 0x6068 - 0x607F: Reserved */ - __RW uint32_t PTP_EVT_SCP_SEC1; /* 0x6080: target time seconds */ - __RW uint32_t PTP_EVT_SCP_NS1; /* 0x6084: target time sub seconds */ - __RW uint32_t PTP_EVT_PPS1_INTERVAL; /* 0x6088: pps1 interval configure */ - __RW uint32_t PTP_EVT_PPS1_WIDTH; /* 0x608C: pps1 width configure */ - __R uint8_t RESERVED37[16]; /* 0x6090 - 0x609F: Reserved */ - __RW uint32_t PTP_EVT_SCP_SEC2; /* 0x60A0: target time seconds */ - __RW uint32_t PTP_EVT_SCP_NS2; /* 0x60A4: target time sub seconds */ - __RW uint32_t PTP_EVT_PPS2_INTERVAL; /* 0x60A8: pps2 interval configure */ - __RW uint32_t PTP_EVT_PPS2_WIDTH; /* 0x60AC: pps2 width configure */ - __R uint8_t RESERVED38[16]; /* 0x60B0 - 0x60BF: Reserved */ - __RW uint32_t PTP_EVT_SCP_SEC3; /* 0x60C0: target time seconds */ - __RW uint32_t PTP_EVT_SCP_NS3; /* 0x60C4: target time sub seconds */ - __RW uint32_t PTP_EVT_PPS3_INTERVAL; /* 0x60C8: pps3 interval configure */ - __RW uint32_t PTP_EVT_PPS3_WIDTH; /* 0x60CC: pps3 width configure */ - __R uint8_t RESERVED39[16]; /* 0x60D0 - 0x60DF: Reserved */ - __RW uint32_t PTP_EVT_PPS_CTRL0; /* 0x60E0: pps control 0 register */ - __RW uint32_t PTP_EVT_PPS_SEL; /* 0x60E4: */ - __R uint8_t RESERVED40[8]; /* 0x60E8 - 0x60EF: Reserved */ - __RW uint32_t SOFT_RST_CTRL; /* 0x60F0: softer reset control */ - __R uint8_t RESERVED41[40716]; /* 0x60F4 - 0xFFFF: Reserved */ - __RW uint32_t CPU_PORT_PORT_MAIN_TAGGING; /* 0x10000: PVID Tagging Register */ - __RW uint32_t CPU_PORT_PORT_MAIN_ENNABLE; /* 0x10004: Port Module Enable Register */ - __R uint8_t RESERVED42[10232]; /* 0x10008 - 0x127FF: Reserved */ - __R uint32_t CPU_PORT_EGRESS_STMID_ESELECT; /* 0x12800: Stream Identification */ - __R uint8_t RESERVED43[60]; /* 0x12804 - 0x1283F: Reserved */ - __RW uint32_t CPU_PORT_EGRESS_STMID_CONTROL; /* 0x12840: */ - __RW uint32_t CPU_PORT_EGRESS_STMID_SEQNO; /* 0x12844: */ - __RW uint32_t CPU_PORT_EGRESS_STMID_MATCHCNT; /* 0x12848: */ - __R uint8_t RESERVED44[4]; /* 0x1284C - 0x1284F: Reserved */ - __RW uint32_t CPU_PORT_EGRESS_STMID_MACLO; /* 0x12850: */ - __RW uint32_t CPU_PORT_EGRESS_STMID_MACHI; /* 0x12854: */ - __R uint8_t RESERVED45[4]; /* 0x12858 - 0x1285B: Reserved */ - __RW uint32_t CPU_PORT_EGRESS_STMID_AMACHI;/* 0x1285C: */ - __R uint8_t RESERVED46[416]; /* 0x12860 - 0x129FF: Reserved */ - __RW uint32_t CPU_PORT_EGRESS_FRER_CONTROL;/* 0x12A00: Frame Replication and Elimination */ - __RW uint32_t CPU_PORT_EGRESS_FRER_SIDSEL; /* 0x12A04: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_IRFUNC; /* 0x12A08: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_SRFUNC; /* 0x12A0C: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_FSELECT;/* 0x12A10: */ - __R uint8_t RESERVED47[44]; /* 0x12A14 - 0x12A3F: Reserved */ - __RW uint32_t CPU_PORT_EGRESS_FRER_FCTRL; /* 0x12A40: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_RESETMSEC; /* 0x12A44: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_LATRSPERIOD; /* 0x12A48: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_LATTESTPERIOD; /* 0x12A4C: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_LATERRDIFFALW; /* 0x12A50: */ - __RW uint32_t CPU_PORT_EGRESS_FRER_LATERRCNT; /* 0x12A54: */ - __R uint8_t RESERVED48[8]; /* 0x12A58 - 0x12A5F: Reserved */ - __R uint32_t EGFRCNT[8]; /* 0x12A60 - 0x12A7C: */ - __R uint8_t RESERVED49[5504]; /* 0x12A80 - 0x13FFF: Reserved */ - __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE; /* 0x14000: */ - __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS; /* 0x14004: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG; /* 0x14008: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG; /* 0x1400C: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG; /* 0x14010: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG; /* 0x14014: */ - __W uint32_t CPU_PORT_IGRESS_RX_FDFIFO_RESET; /* 0x14018: */ - __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PARAM; /* 0x1401C: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_STRFWD; /* 0x14020: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK; /* 0x14024: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR; /* 0x14028: */ - __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX; /* 0x1402C: */ - __R uint8_t RESERVED50[2000]; /* 0x14030 - 0x147FF: Reserved */ - __R uint32_t CPU_PORT_IGRESS_STMID_ESELECT; /* 0x14800: Stream Identification */ - __R uint8_t RESERVED51[60]; /* 0x14804 - 0x1483F: Reserved */ - __RW uint32_t CPU_PORT_IGRESS_STMID_CONTROL; /* 0x14840: */ - __RW uint32_t CPU_PORT_IGRESS_STMID_SEQNO; /* 0x14844: */ - __RW uint32_t CPU_PORT_IGRESS_STMID_MATCHCNT; /* 0x14848: */ - __R uint8_t RESERVED52[4]; /* 0x1484C - 0x1484F: Reserved */ - __RW uint32_t CPU_PORT_IGRESS_STMID_MACLO; /* 0x14850: */ - __RW uint32_t CPU_PORT_IGRESS_STMID_MACHI; /* 0x14854: */ - __R uint8_t RESERVED53[4]; /* 0x14858 - 0x1485B: Reserved */ - __RW uint32_t CPU_PORT_IGRESS_STMID_AMACHI;/* 0x1485C: */ - __R uint8_t RESERVED54[416]; /* 0x14860 - 0x149FF: Reserved */ - __RW uint32_t CPU_PORT_IGRESS_FRER_CONTROL;/* 0x14A00: Frame Replication and Elimination */ - __RW uint32_t CPU_PORT_IGRESS_FRER_SIDSEL; /* 0x14A04: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_IRFUNC; /* 0x14A08: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_SRFUNC; /* 0x14A0C: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_FSELECT;/* 0x14A10: */ - __R uint8_t RESERVED55[44]; /* 0x14A14 - 0x14A3F: Reserved */ - __RW uint32_t CPU_PORT_IGRESS_FRER_FCTRL; /* 0x14A40: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_RESETMSEC; /* 0x14A44: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_LATRSPERIOD; /* 0x14A48: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_LATTESTPERIOD; /* 0x14A4C: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_LATERRDIFFALW; /* 0x14A50: */ - __RW uint32_t CPU_PORT_IGRESS_FRER_LATERRCNT; /* 0x14A54: */ - __R uint8_t RESERVED56[8]; /* 0x14A58 - 0x14A5F: Reserved */ - __R uint32_t IGFRCNT[8]; /* 0x14A60 - 0x14A7C: */ - __R uint8_t RESERVED57[13700]; /* 0x14A80 - 0x18003: Reserved */ - __RW uint32_t CPU_PORT_MONITOR_CTRL; /* 0x18004: */ - __W uint32_t CPU_PORT_MONITOR_RESET; /* 0x18008: */ - __R uint32_t CPU_PORT_MONITOR_PARAM; /* 0x1800C: */ - __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD; /* 0x18010: */ - __R uint8_t RESERVED58[4]; /* 0x18014 - 0x18017: Reserved */ - __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR; /* 0x18018: */ - __R uint8_t RESERVED59[4]; /* 0x1801C - 0x1801F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x18020: */ - __R uint8_t RESERVED60[28]; /* 0x18024 - 0x1803F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD; /* 0x18040: */ - __R uint8_t RESERVED61[4]; /* 0x18044 - 0x18047: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR; /* 0x18048: */ - __R uint8_t RESERVED62[4]; /* 0x1804C - 0x1804F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN; /* 0x18050: */ - __R uint8_t RESERVED63[4]; /* 0x18054 - 0x18057: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x18058: */ - __R uint8_t RESERVED64[4]; /* 0x1805C - 0x1805F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UC; /* 0x18060: */ - __R uint8_t RESERVED65[4]; /* 0x18064 - 0x18067: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN; /* 0x18068: */ - __R uint8_t RESERVED66[4]; /* 0x1806C - 0x1806F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_BC; /* 0x18070: */ - __R uint8_t RESERVED67[4]; /* 0x18074 - 0x18077: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI; /* 0x18078: */ - __R uint8_t RESERVED68[4]; /* 0x1807C - 0x1807F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN; /* 0x18080: */ - __R uint8_t RESERVED69[4]; /* 0x18084 - 0x18087: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x18088: */ - __R uint8_t RESERVED70[4]; /* 0x1808C - 0x1808F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x18090: */ - __R uint8_t RESERVED71[4]; /* 0x18094 - 0x18097: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x18098: */ - __R uint8_t RESERVED72[4]; /* 0x1809C - 0x1809F: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x180A0: */ - __R uint8_t RESERVED73[4]; /* 0x180A4 - 0x180A7: Reserved */ - __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x180A8: */ - __R uint8_t RESERVED74[32596]; /* 0x180AC - 0x1FFFF: Reserved */ - struct { - struct { - __R uint32_t MAC_VER; /* 0x20000: */ - __RW uint32_t MAC_MACADDR_L; /* 0x20004: */ - __RW uint32_t MAC_MACADDR_H; /* 0x20008: */ - __RW uint32_t MAC_MAC_CTRL; /* 0x2000C: */ - __R uint32_t MAC_TX_FRAMES; /* 0x20010: */ - __R uint32_t MAC_RX_FRAMES; /* 0x20014: */ - __R uint32_t MAC_TX_OCTETS; /* 0x20018: */ - __R uint32_t MAC_RX_OCTETS; /* 0x2001C: */ - __RW uint32_t MAC_MDIO_CFG; /* 0x20020: */ - __RW uint32_t MAC_MDIO_CTRL; /* 0x20024: */ - __R uint32_t MAC_MDIO_RD_DATA; /* 0x20028: */ - __RW uint32_t MAC_MDIO_WR_DATA; /* 0x2002C: */ - __RW uint32_t MAC_IRQ_CTRL; /* 0x20030: */ - __R uint8_t RESERVED0[460]; /* 0x20034 - 0x201FF: Reserved */ - } MAC[2]; - __R uint8_t RESERVED0[1024]; /* 0x20400 - 0x207FF: Reserved */ - __RW uint32_t RTC_CR; /* 0x20800: ONLY IN PORT1 */ - __RW uint32_t RTC_SR; /* 0x20804: ONLY IN PORT1 */ - __R uint8_t RESERVED1[8]; /* 0x20808 - 0x2080F: Reserved */ - __RW uint32_t RTC_CT_CURTIME_NS; /* 0x20810: ONLY IN PORT1 */ - __R uint32_t RTC_CT_CURTIME_SEC; /* 0x20814: ONLY IN PORT1 */ - __R uint8_t RESERVED2[4]; /* 0x20818 - 0x2081B: Reserved */ - __RW uint32_t RTC_CT_TIMER_INCR; /* 0x2081C: ONLY IN PORT1 */ - __RW uint32_t RTC_OFS_NS; /* 0x20820: ONLY IN PORT1 */ - __RW uint32_t RTC_OFS_SL; /* 0x20824: ONLY IN PORT1 */ - __RW uint32_t RTC_OFS_SH; /* 0x20828: ONLY IN PORT1 */ - __RW uint32_t RTC_OFS_CH; /* 0x2082C: ONLY IN PORT1 */ - __RW uint32_t RTC_ALARM_NS; /* 0x20830: ONLY IN PORT1 */ - __RW uint32_t RTC_ALARM_SL; /* 0x20834: ONLY IN PORT1 */ - __RW uint32_t RTC_ALARM_SH; /* 0x20838: ONLY IN PORT1 */ - __R uint8_t RESERVED3[4]; /* 0x2083C - 0x2083F: Reserved */ - __RW uint32_t RTC_TIMER_A_PERIOD; /* 0x20840: ONLY IN PORT1 */ - __R uint8_t RESERVED4[1984]; /* 0x20844 - 0x21003: Reserved */ - __RW uint32_t TSYN_CR; /* 0x21004: */ - __RW uint32_t TSYN_SR; /* 0x21008: */ - __R uint8_t RESERVED5[4]; /* 0x2100C - 0x2100F: Reserved */ - __R uint32_t TSYN_PTP_TX_STS; /* 0x21010: */ - __RW uint32_t TSYN_PTP_TX_DONE; /* 0x21014: */ - __W uint32_t TSYN_PTP_TX_TRIG; /* 0x21018: */ - __RW uint32_t TSYN_PTP_RX_STS; /* 0x2101C: */ - __RW uint32_t TSYNTMR[5]; /* 0x21020 - 0x21030: */ - __R uint8_t RESERVED6[8]; /* 0x21034 - 0x2103B: Reserved */ - __RW uint32_t TSYN_HCLKDIV; /* 0x2103C: */ - __R uint8_t RESERVED7[1472]; /* 0x21040 - 0x215FF: Reserved */ - __R uint32_t TSYN_RXBUF_RX_FRAME_LENGTH_BYTES; /* 0x21600: */ - __R uint8_t RESERVED8[4]; /* 0x21604 - 0x21607: Reserved */ - __R uint32_t TSYN_RXBUF_RX_TIME_STAMP_L; /* 0x21608: */ - __R uint32_t TSYN_RXBUF_RX_TIME_STAMP_H; /* 0x2160C: */ - __R uint32_t RXDATA[60]; /* 0x21610 - 0x216FC: */ - __R uint8_t RESERVED9[256]; /* 0x21700 - 0x217FF: Reserved */ - struct { - __RW uint32_t TXDATA[60]; /* 0x21800 - 0x218EC: */ - __RW uint32_t TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN; /* 0x218F0: */ - __R uint8_t RESERVED0[4]; /* 0x218F4 - 0x218F7: Reserved */ - __RW uint32_t TSYN_TXBUF_BIN0_TX_TIMESTAMP_L; /* 0x218F8: */ - __RW uint32_t TSYN_TXBUF_BIN0_TX_TIMESTAMP_H; /* 0x218FC: */ - } BIN[8]; - __R uint8_t RESERVED10[4]; /* 0x22000 - 0x22003: Reserved */ - __R uint32_t TSN_SHAPER_HWCFG1; /* 0x22004: */ - __R uint8_t RESERVED11[4]; /* 0x22008 - 0x2200B: Reserved */ - __RW uint32_t TSN_SHAPER_TQAV; /* 0x2200C: */ - __R uint32_t TSN_SHAPER_TQEM; /* 0x22010: */ - __RW uint32_t TSN_SHAPER_FPST; /* 0x22014: */ - __RW uint32_t TSN_SHAPER_MMCT; /* 0x22018: */ - __RW uint32_t TSN_SHAPER_HOLDADV; /* 0x2201C: */ - __R uint8_t RESERVED12[224]; /* 0x22020 - 0x220FF: Reserved */ - __RW uint32_t MXSDU[8]; /* 0x22100 - 0x2211C: */ - __RW uint32_t TXSEL[8]; /* 0x22120 - 0x2213C: */ - __RW uint32_t IDSEL[8]; /* 0x22140 - 0x2215C: */ - __R uint8_t RESERVED13[1696]; /* 0x22160 - 0x227FF: Reserved */ - __RW uint32_t PORT1_QCH0_CFG; /* 0x22800: qch channel0 control */ - __RW uint32_t PORT1_QCH1_CFG; /* 0x22804: qch channel1 control */ - __RW uint32_t PORT1_QCH2_CFG; /* 0x22808: qch channel2 control */ - __RW uint32_t PORT1_QCH3_CFG; /* 0x2280C: qch channel3 control */ - __RW uint32_t PORT1_QCH_ERR_CFG; /* 0x22810: qch clear */ - __R uint8_t RESERVED14[2028]; /* 0x22814 - 0x22FFF: Reserved */ - __RW uint32_t TSN_SHAPER_TAS_CRSR; /* 0x23000: */ - __RW uint32_t TSN_SHAPER_TAS_ACYCLETM; /* 0x23004: */ - __RW uint32_t TSN_SHAPER_TAS_ABASETM_L;/* 0x23008: */ - __RW uint32_t TSN_SHAPER_TAS_ABASETM_H;/* 0x2300C: */ - __RW uint32_t TSN_SHAPER_TAS_LISTLEN; /* 0x23010: */ - __R uint32_t TSN_SHAPER_TAS_OCYCLETM; /* 0x23014: */ - __R uint32_t TSN_SHAPER_TAS_OBASETM_L;/* 0x23018: */ - __R uint32_t TSN_SHAPER_TAS_OBASETM_H;/* 0x2301C: */ - __RW uint32_t MXTK[8]; /* 0x23020 - 0x2303C: */ - __RW uint32_t TXOV[8]; /* 0x23040 - 0x2305C: */ - __R uint8_t RESERVED15[1952]; /* 0x23060 - 0x237FF: Reserved */ - struct { - __RW uint32_t TSN_SHAPER_ACLIST_ENTRY0_L; /* 0x23800: */ - __RW uint32_t TSN_SHAPER_ACLIST_ENTRY0_H; /* 0x23804: */ - } SHACL[256]; - __R uint8_t RESERVED16[45056]; /* 0x24000 - 0x2EFFF: Reserved */ - __R uint32_t TSN_EP_VER; /* 0x2F000: */ - __RW uint32_t TSN_EP_CTRL; /* 0x2F004: */ - __R uint8_t RESERVED17[8]; /* 0x2F008 - 0x2F00F: Reserved */ - __RW uint32_t TSN_EP_TXUF; /* 0x2F010: */ - __R uint32_t TSN_EP_IPCFG; /* 0x2F014: */ - __R uint8_t RESERVED18[8]; /* 0x2F018 - 0x2F01F: Reserved */ - __R uint32_t TSN_EP_TSF_D0; /* 0x2F020: */ - __R uint32_t TSN_EP_TSF_D1; /* 0x2F024: */ - __R uint32_t TSN_EP_TSF_D2; /* 0x2F028: */ - __RW uint32_t TSN_EP_TSF_SR; /* 0x2F02C: */ - __RW uint32_t TSN_EP_MMS_CTRL; /* 0x2F030: */ - __R uint32_t TSN_EP_MMS_STS; /* 0x2F034: */ - __RW uint32_t TSN_EP_MMS_VTIME; /* 0x2F038: */ - __RW uint32_t TSN_EP_MMS_STAT; /* 0x2F03C: */ - __W uint32_t TSN_EP_PTP_UPTM_NS; /* 0x2F040: */ - __W uint32_t TSN_EP_PTP_UPTM_S; /* 0x2F044: */ - __R uint32_t TSN_EP_PTP_SR; /* 0x2F048: */ - __R uint8_t RESERVED19[4020]; /* 0x2F04C - 0x2FFFF: Reserved */ - __RW uint32_t SW_CTRL_PORT_MAIN_TAGGING; /* 0x30000: PVID Tagging Register */ - __RW uint32_t SW_CTRL_PORT_MAIN_ENNABLE; /* 0x30004: Port Module Enable Register */ - __R uint8_t RESERVED20[8184]; /* 0x30008 - 0x31FFF: Reserved */ - __RW uint32_t SW_CTRL_EGRESS_ECSR_QDROP; /* 0x32000: */ - __R uint8_t RESERVED21[8188]; /* 0x32004 - 0x33FFF: Reserved */ - struct { - __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE; /* 0x34000: */ - __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS; /* 0x34004: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG; /* 0x34008: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG; /* 0x3400C: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG; /* 0x34010: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG; /* 0x34014: */ - __W uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_RESET; /* 0x34018: */ - __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM; /* 0x3401C: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD; /* 0x34020: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK; /* 0x34024: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR; /* 0x34028: */ - __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX; /* 0x3402C: */ - __R uint8_t RESERVED0[208]; /* 0x34030 - 0x340FF: Reserved */ - } RXFIFO[2]; - __R uint8_t RESERVED22[15876]; /* 0x34200 - 0x38003: Reserved */ - __RW uint32_t SW_CTRL_MONITOR_CTRL; /* 0x38004: */ - __W uint32_t SW_CTRL_MONITOR_RESET; /* 0x38008: */ - __R uint32_t SW_CTRL_MONITOR_PARAM; /* 0x3800C: */ - __R uint32_t MONITOR_TX_COUNTER_TX_FGOOD; /* 0x38010: */ - __R uint8_t RESERVED23[4]; /* 0x38014 - 0x38017: Reserved */ - __R uint32_t MONITOR_TX_COUNTER_TX_FERROR; /* 0x38018: */ - __R uint8_t RESERVED24[4]; /* 0x3801C - 0x3801F: Reserved */ - __R uint32_t MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x38020: */ - __R uint8_t RESERVED25[28]; /* 0x38024 - 0x3803F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_FGOOD; /* 0x38040: */ - __R uint8_t RESERVED26[4]; /* 0x38044 - 0x38047: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_FERROR; /* 0x38048: */ - __R uint8_t RESERVED27[4]; /* 0x3804C - 0x3804F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_KNOWN; /* 0x38050: */ - __R uint8_t RESERVED28[4]; /* 0x38054 - 0x38057: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x38058: */ - __R uint8_t RESERVED29[4]; /* 0x3805C - 0x3805F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_UC;/* 0x38060: */ - __R uint8_t RESERVED30[4]; /* 0x38064 - 0x38067: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_INTERN; /* 0x38068: */ - __R uint8_t RESERVED31[4]; /* 0x3806C - 0x3806F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_BC;/* 0x38070: */ - __R uint8_t RESERVED32[4]; /* 0x38074 - 0x38077: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_MULTI; /* 0x38078: */ - __R uint8_t RESERVED33[4]; /* 0x3807C - 0x3807F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_VLAN; /* 0x38080: */ - __R uint8_t RESERVED34[4]; /* 0x38084 - 0x38087: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x38088: */ - __R uint8_t RESERVED35[4]; /* 0x3808C - 0x3808F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x38090: */ - __R uint8_t RESERVED36[4]; /* 0x38094 - 0x38097: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x38098: */ - __R uint8_t RESERVED37[4]; /* 0x3809C - 0x3809F: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x380A0: */ - __R uint8_t RESERVED38[4]; /* 0x380A4 - 0x380A7: Reserved */ - __R uint32_t MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x380A8: */ - __R uint8_t RESERVED39[16212]; /* 0x380AC - 0x3BFFF: Reserved */ - __RW uint32_t GPR_CTRL0; /* 0x3C000: control register0 */ - __R uint8_t RESERVED40[4]; /* 0x3C004 - 0x3C007: Reserved */ - __RW uint32_t GPR_CTRL2; /* 0x3C008: control register2 */ - __R uint8_t RESERVED41[16372]; /* 0x3C00C - 0x3FFFF: Reserved */ - } TSNPORT[3]; -} TSW_Type; - - -/* Bitfield definition for register: LU_MAIN_CTRL */ -/* - * BYP_EN (R/W) - * - * MAC lookup bypass - */ -#define TSW_LU_MAIN_CTRL_BYP_EN_MASK (0x1U) -#define TSW_LU_MAIN_CTRL_BYP_EN_SHIFT (0U) -#define TSW_LU_MAIN_CTRL_BYP_EN_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_CTRL_BYP_EN_SHIFT) & TSW_LU_MAIN_CTRL_BYP_EN_MASK) -#define TSW_LU_MAIN_CTRL_BYP_EN_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_CTRL_BYP_EN_MASK) >> TSW_LU_MAIN_CTRL_BYP_EN_SHIFT) - -/* Bitfield definition for register: LU_MAIN_HITMEM */ -/* - * CAMMEMCLR (R/W) - * - * clear the cam memory - */ -#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK (0x2U) -#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT (1U) -#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK) -#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT) - -/* - * HITMEMCLR (R/W) - * - * clears the hit memory - */ -#define TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK (0x1U) -#define TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT (0U) -#define TSW_LU_MAIN_HITMEM_HITMEMCLR_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK) -#define TSW_LU_MAIN_HITMEM_HITMEMCLR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT) - -/* Bitfield definition for register: LU_MAIN_PARAM */ -/* - * NSTR (RO) - * - * number of supported streams - */ -#define TSW_LU_MAIN_PARAM_NSTR_MASK (0xFF00U) -#define TSW_LU_MAIN_PARAM_NSTR_SHIFT (8U) -#define TSW_LU_MAIN_PARAM_NSTR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PARAM_NSTR_MASK) >> TSW_LU_MAIN_PARAM_NSTR_SHIFT) - -/* - * ADDRW_ENTRY (RO) - * - * bit width of entry address vector - */ -#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK (0xFFU) -#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT (0U) -#define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK) >> TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT) - -/* Bitfield definition for register: LU_MAIN_BYPASS */ -/* - * HIT (R/W) - * - * set hit bit to frame, only for debugging - */ -#define TSW_LU_MAIN_BYPASS_HIT_MASK (0x1000000UL) -#define TSW_LU_MAIN_BYPASS_HIT_SHIFT (24U) -#define TSW_LU_MAIN_BYPASS_HIT_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_MASK) -#define TSW_LU_MAIN_BYPASS_HIT_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_MASK) >> TSW_LU_MAIN_BYPASS_HIT_SHIFT) - -/* - * UTAG (R/W) - * - * set internal user tag field - */ -#define TSW_LU_MAIN_BYPASS_UTAG_MASK (0xE00000UL) -#define TSW_LU_MAIN_BYPASS_UTAG_SHIFT (21U) -#define TSW_LU_MAIN_BYPASS_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_UTAG_SHIFT) & TSW_LU_MAIN_BYPASS_UTAG_MASK) -#define TSW_LU_MAIN_BYPASS_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_UTAG_MASK) >> TSW_LU_MAIN_BYPASS_UTAG_SHIFT) - -/* - * HIT_VLAN (R/W) - * - * mark frame to be vlan-tagged - */ -#define TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK (0x100000UL) -#define TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT (20U) -#define TSW_LU_MAIN_BYPASS_HIT_VLAN_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK) -#define TSW_LU_MAIN_BYPASS_HIT_VLAN_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK) >> TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT) - -/* - * DROP (R/W) - * - * mark frame to be dropped - */ -#define TSW_LU_MAIN_BYPASS_DROP_MASK (0x80000UL) -#define TSW_LU_MAIN_BYPASS_DROP_SHIFT (19U) -#define TSW_LU_MAIN_BYPASS_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DROP_SHIFT) & TSW_LU_MAIN_BYPASS_DROP_MASK) -#define TSW_LU_MAIN_BYPASS_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DROP_MASK) >> TSW_LU_MAIN_BYPASS_DROP_SHIFT) - -/* - * QUEUE (R/W) - * - * number of configured buffer depth - */ -#define TSW_LU_MAIN_BYPASS_QUEUE_MASK (0x70000UL) -#define TSW_LU_MAIN_BYPASS_QUEUE_SHIFT (16U) -#define TSW_LU_MAIN_BYPASS_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_QUEUE_SHIFT) & TSW_LU_MAIN_BYPASS_QUEUE_MASK) -#define TSW_LU_MAIN_BYPASS_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_QUEUE_MASK) >> TSW_LU_MAIN_BYPASS_QUEUE_SHIFT) - -/* - * DEST (R/W) - * - * target destination ports of frame - */ -#define TSW_LU_MAIN_BYPASS_DEST_MASK (0xFFFFU) -#define TSW_LU_MAIN_BYPASS_DEST_SHIFT (0U) -#define TSW_LU_MAIN_BYPASS_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DEST_SHIFT) & TSW_LU_MAIN_BYPASS_DEST_MASK) -#define TSW_LU_MAIN_BYPASS_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DEST_MASK) >> TSW_LU_MAIN_BYPASS_DEST_SHIFT) - -/* Bitfield definition for register: LU_MAIN_PCP_REMAP */ -/* - * PCP7 (R/W) - * - * queue value for PCP=7 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP7_MASK (0xE00000UL) -#define TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT (21U) -#define TSW_LU_MAIN_PCP_REMAP_PCP7_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP7_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT) - -/* - * PCP6 (R/W) - * - * queue value for PCP=6 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP6_MASK (0x1C0000UL) -#define TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT (18U) -#define TSW_LU_MAIN_PCP_REMAP_PCP6_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP6_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT) - -/* - * PCP5 (R/W) - * - * queue value for PCP=5 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP5_MASK (0x38000UL) -#define TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT (15U) -#define TSW_LU_MAIN_PCP_REMAP_PCP5_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP5_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT) - -/* - * PCP4 (R/W) - * - * queue value for PCP=4 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP4_MASK (0x7000U) -#define TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT (12U) -#define TSW_LU_MAIN_PCP_REMAP_PCP4_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP4_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT) - -/* - * PCP3 (R/W) - * - * queue value for PCP=3 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP3_MASK (0xE00U) -#define TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT (9U) -#define TSW_LU_MAIN_PCP_REMAP_PCP3_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP3_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT) - -/* - * PCP2 (R/W) - * - * queue value for PCP=2 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP2_MASK (0x1C0U) -#define TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT (6U) -#define TSW_LU_MAIN_PCP_REMAP_PCP2_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP2_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT) - -/* - * PCP1 (R/W) - * - * queue value for PCP=1 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP1_MASK (0x38U) -#define TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT (3U) -#define TSW_LU_MAIN_PCP_REMAP_PCP1_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP1_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT) - -/* - * PCP0 (R/W) - * - * queue value for PCP=0 - */ -#define TSW_LU_MAIN_PCP_REMAP_PCP0_MASK (0x7U) -#define TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT (0U) -#define TSW_LU_MAIN_PCP_REMAP_PCP0_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK) -#define TSW_LU_MAIN_PCP_REMAP_PCP0_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT) - -/* Bitfield definition for register: LU_MAIN_VERSION */ -/* - * VER_HI (RO) - * - * major version - */ -#define TSW_LU_MAIN_VERSION_VER_HI_MASK (0xFF000000UL) -#define TSW_LU_MAIN_VERSION_VER_HI_SHIFT (24U) -#define TSW_LU_MAIN_VERSION_VER_HI_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_HI_MASK) >> TSW_LU_MAIN_VERSION_VER_HI_SHIFT) - -/* - * VER_LO (RO) - * - * minor version - */ -#define TSW_LU_MAIN_VERSION_VER_LO_MASK (0xFF0000UL) -#define TSW_LU_MAIN_VERSION_VER_LO_SHIFT (16U) -#define TSW_LU_MAIN_VERSION_VER_LO_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_LO_MASK) >> TSW_LU_MAIN_VERSION_VER_LO_SHIFT) - -/* - * VER_REV (RO) - * - * revision number - */ -#define TSW_LU_MAIN_VERSION_VER_REV_MASK (0xFFU) -#define TSW_LU_MAIN_VERSION_VER_REV_SHIFT (0U) -#define TSW_LU_MAIN_VERSION_VER_REV_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_REV_MASK) >> TSW_LU_MAIN_VERSION_VER_REV_SHIFT) - -/* Bitfield definition for register: LU_MAIN_INTF_ACTION */ -/* - * UTAG (R/W) - * - * TSN user sideband information from ALMEM - */ -#define TSW_LU_MAIN_INTF_ACTION_UTAG_MASK (0x1C00000UL) -#define TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT (22U) -#define TSW_LU_MAIN_INTF_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK) -#define TSW_LU_MAIN_INTF_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK) >> TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT) - -/* - * QSEL (R/W) - * - * Define the traffic queue selection: - * 00 – use PCP field of VLAN, untagged frames use PCP of PVID - * 01 – use PCP field with global remapping list - * 10 – reserved - * 11 – use value QUEUE of Action List - */ -#define TSW_LU_MAIN_INTF_ACTION_QSEL_MASK (0x300000UL) -#define TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT (20U) -#define TSW_LU_MAIN_INTF_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK) -#define TSW_LU_MAIN_INTF_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK) >> TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT) - -/* - * DROP (R/W) - * - * 1 if frame should be dropped. - */ -#define TSW_LU_MAIN_INTF_ACTION_DROP_MASK (0x80000UL) -#define TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT (19U) -#define TSW_LU_MAIN_INTF_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK) -#define TSW_LU_MAIN_INTF_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK) >> TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT) - -/* - * QUEUE (R/W) - * - * Select the Priority Queue for TSN TX, only used if QSEL=11 - */ -#define TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK (0x70000UL) -#define TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT (16U) -#define TSW_LU_MAIN_INTF_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK) -#define TSW_LU_MAIN_INTF_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT) - -/* - * DEST (R/W) - * - * Select the destination ports of forwarded frame. It is coded in onehot/select way, - * where 0 is always route to null. Every bit is mapped to a port. - * 00000 – to null (frame to clear) - * 00001 – to port 0 (CPU Port) - * 00010 – to port 1 - * 00100 – to port 2 - * 01000 – to port 3 - */ -#define TSW_LU_MAIN_INTF_ACTION_DEST_MASK (0xFFFFU) -#define TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT (0U) -#define TSW_LU_MAIN_INTF_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK) -#define TSW_LU_MAIN_INTF_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK) >> TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT) - -/* Bitfield definition for register: LU_MAIN_BC_ACTION */ -/* - * UTAG (R/W) - * - * TSN user sideband information from ALMEM - */ -#define TSW_LU_MAIN_BC_ACTION_UTAG_MASK (0x1C00000UL) -#define TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT (22U) -#define TSW_LU_MAIN_BC_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK) -#define TSW_LU_MAIN_BC_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK) >> TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT) - -/* - * QSEL (R/W) - * - * Define the traffic queue selection: - * 00 – use PCP field of VLAN, untagged frames use PCP of PVID - * 01 – use PCP field with global remapping list - * 10 – reserved - * 11 – use value QUEUE of Action List - */ -#define TSW_LU_MAIN_BC_ACTION_QSEL_MASK (0x300000UL) -#define TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT (20U) -#define TSW_LU_MAIN_BC_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK) -#define TSW_LU_MAIN_BC_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK) >> TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT) - -/* - * DROP (R/W) - * - * 1 if frame should be dropped. - */ -#define TSW_LU_MAIN_BC_ACTION_DROP_MASK (0x80000UL) -#define TSW_LU_MAIN_BC_ACTION_DROP_SHIFT (19U) -#define TSW_LU_MAIN_BC_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DROP_SHIFT) & TSW_LU_MAIN_BC_ACTION_DROP_MASK) -#define TSW_LU_MAIN_BC_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DROP_MASK) >> TSW_LU_MAIN_BC_ACTION_DROP_SHIFT) - -/* - * QUEUE (R/W) - * - * Select the Priority Queue for TSN TX, only used if QSEL=11 - */ -#define TSW_LU_MAIN_BC_ACTION_QUEUE_MASK (0x70000UL) -#define TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT (16U) -#define TSW_LU_MAIN_BC_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK) -#define TSW_LU_MAIN_BC_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT) - -/* - * DEST (R/W) - * - * Select the destination ports of forwarded frame. It is coded in onehot/select way, - * where 0 is always route to null. Every bit is mapped to a port. - * 00000 – to null (frame to clear) - * 00001 – to port 0 (CPU Port) - * 00010 – to port 1 - * 00100 – to port 2 - * 01000 – to port 3 - */ -#define TSW_LU_MAIN_BC_ACTION_DEST_MASK (0xFFFFU) -#define TSW_LU_MAIN_BC_ACTION_DEST_SHIFT (0U) -#define TSW_LU_MAIN_BC_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DEST_SHIFT) & TSW_LU_MAIN_BC_ACTION_DEST_MASK) -#define TSW_LU_MAIN_BC_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DEST_MASK) >> TSW_LU_MAIN_BC_ACTION_DEST_SHIFT) - -/* Bitfield definition for register: LU_MAIN_NN_ACTION */ -/* - * UTAG (R/W) - * - * TSN user sideband information from ALMEM - */ -#define TSW_LU_MAIN_NN_ACTION_UTAG_MASK (0x1C00000UL) -#define TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT (22U) -#define TSW_LU_MAIN_NN_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK) -#define TSW_LU_MAIN_NN_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK) >> TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT) - -/* - * QSEL (R/W) - * - * Define the traffic queue selection: - * 00 – use PCP field of VLAN, untagged frames use PCP of PVID - * 01 – use PCP field with global remapping list - * 10 – reserved - * 11 – use value QUEUE of Action List - */ -#define TSW_LU_MAIN_NN_ACTION_QSEL_MASK (0x300000UL) -#define TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT (20U) -#define TSW_LU_MAIN_NN_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK) -#define TSW_LU_MAIN_NN_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK) >> TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT) - -/* - * DROP (R/W) - * - * 1 if frame should be dropped. - */ -#define TSW_LU_MAIN_NN_ACTION_DROP_MASK (0x80000UL) -#define TSW_LU_MAIN_NN_ACTION_DROP_SHIFT (19U) -#define TSW_LU_MAIN_NN_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DROP_SHIFT) & TSW_LU_MAIN_NN_ACTION_DROP_MASK) -#define TSW_LU_MAIN_NN_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DROP_MASK) >> TSW_LU_MAIN_NN_ACTION_DROP_SHIFT) - -/* - * QUEUE (R/W) - * - * Select the Priority Queue for TSN TX, only used if QSEL=11 - */ -#define TSW_LU_MAIN_NN_ACTION_QUEUE_MASK (0x70000UL) -#define TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT (16U) -#define TSW_LU_MAIN_NN_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK) -#define TSW_LU_MAIN_NN_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT) - -/* - * DEST (R/W) - * - * Select the destination ports of forwarded frame. It is coded in onehot/select way, - * where 0 is always route to null. Every bit is mapped to a port. - * 00000 – to null (frame to clear) - * 00001 – to port 0 (CPU Port) - * 00010 – to port 1 - * 00100 – to port 2 - * 01000 – to port 3 - */ -#define TSW_LU_MAIN_NN_ACTION_DEST_MASK (0xFFFFU) -#define TSW_LU_MAIN_NN_ACTION_DEST_SHIFT (0U) -#define TSW_LU_MAIN_NN_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DEST_SHIFT) & TSW_LU_MAIN_NN_ACTION_DEST_MASK) -#define TSW_LU_MAIN_NN_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DEST_MASK) >> TSW_LU_MAIN_NN_ACTION_DEST_SHIFT) - -/* Bitfield definition for register: APB2AXIS_CAM_STS */ -/* - * BUSY (RO) - * - * the controller is writing data and/or data is pending - */ -#define TSW_APB2AXIS_CAM_STS_BUSY_MASK (0x2U) -#define TSW_APB2AXIS_CAM_STS_BUSY_SHIFT (1U) -#define TSW_APB2AXIS_CAM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_BUSY_MASK) >> TSW_APB2AXIS_CAM_STS_BUSY_SHIFT) - -/* - * RDY (RO) - * - * the new data is written to data register - */ -#define TSW_APB2AXIS_CAM_STS_RDY_MASK (0x1U) -#define TSW_APB2AXIS_CAM_STS_RDY_SHIFT (0U) -#define TSW_APB2AXIS_CAM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_RDY_MASK) >> TSW_APB2AXIS_CAM_STS_RDY_SHIFT) - -/* Bitfield definition for register: APB2AXIS_CAM_REQ_CNT */ -/* - * WRCNT (RO) - * - * number of streams in queue - */ -#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK (0xFFU) -#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT (0U) -#define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT) - -/* Bitfield definition for register: APB2AXIS_CAM_FILLSTS */ -/* - * FULL (RO) - * - * frame was dropped because the internal descriptor FIFO is full - */ -#define TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK (0x10U) -#define TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT (4U) -#define TSW_APB2AXIS_CAM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO failure, internal controller lost synchronization - */ -#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK (0x1U) -#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT (0U) -#define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT) - -/* Bitfield definition for register: APB2AXIS_CAM_RESET */ -/* - * RESET (W1C) - * - * resets controller and clears all pending stream data - */ -#define TSW_APB2AXIS_CAM_RESET_RESET_MASK (0x1U) -#define TSW_APB2AXIS_CAM_RESET_RESET_SHIFT (0U) -#define TSW_APB2AXIS_CAM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_RESET_RESET_SHIFT) & TSW_APB2AXIS_CAM_RESET_RESET_MASK) -#define TSW_APB2AXIS_CAM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_RESET_RESET_MASK) >> TSW_APB2AXIS_CAM_RESET_RESET_SHIFT) - -/* Bitfield definition for register: APB2AXIS_CAM_PARAM */ -/* - * DEPTH (RO) - * - * number of configured buffer depth - */ -#define TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK (0xFF00U) -#define TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT (8U) -#define TSW_APB2AXIS_CAM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT) - -/* - * WORDLEN_BYTE (RO) - * - * number of configured 32bit words for this controller - */ -#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK (0xFFU) -#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT (0U) -#define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT) - -/* Bitfield definition for register: APB2AXI_CAM_REQDATA_0 */ -/* - * ENTRY_NUM (R/W) - * - * entry number - */ -#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK (0xFFFF0000UL) -#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT (16U) -#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK) -#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT) - -/* - * TYPE (R/W) - * - * select between set, clear or clear all - */ -#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK (0x300U) -#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT (8U) -#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK) -#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT) - -/* - * CH (R/W) - * - * CAM APB2AXIS channel selection - */ -#define TSW_APB2AXI_CAM_REQDATA_0_CH_MASK (0x1U) -#define TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT (0U) -#define TSW_APB2AXI_CAM_REQDATA_0_CH_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK) -#define TSW_APB2AXI_CAM_REQDATA_0_CH_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT) - -/* Bitfield definition for register: APB2AXI_CAM_REQDATA_1 */ -/* - * DESTMAC_LO_PORT_VEC (R/W) - * - * dest-mac[31:0] when CH=0；PORT_VEC when CH=1 - */ -#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK (0xFFFFFFFFUL) -#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT (0U) -#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) -#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) >> TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT) - -/* Bitfield definition for register: APB2AXI_CAM_REQDATA_2 */ -/* - * VID (R/W) - * - * VLAN-ID value (12 bit) for the VLAN_ID table. Use the fefault VLAN-ID(VID=1), if setup an entry for non-VLAN traffic. - */ -#define TSW_APB2AXI_CAM_REQDATA_2_VID_MASK (0xFFF0000UL) -#define TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT (16U) -#define TSW_APB2AXI_CAM_REQDATA_2_VID_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK) -#define TSW_APB2AXI_CAM_REQDATA_2_VID_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT) - -/* - * DESTMAC_HI (R/W) - * - * dest-mac[47:32] when CH=0 - */ -#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK (0xFFFFU) -#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT (0U) -#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK) -#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_STS */ -/* - * BUSY (RO) - * - * the controller is writing data and/or data is pending - */ -#define TSW_APB2AXIS_ALMEM_STS_BUSY_MASK (0x2U) -#define TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT (1U) -#define TSW_APB2AXIS_ALMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_BUSY_MASK) >> TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT) - -/* - * RDY (RO) - * - * the new data is written to data register - */ -#define TSW_APB2AXIS_ALMEM_STS_RDY_MASK (0x1U) -#define TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_RDY_MASK) >> TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_REQ_CNT */ -/* - * WRCNT (RO) - * - * number of streams in queue - */ -#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK (0xFFU) -#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_FILLSTS */ -/* - * FULL (RO) - * - * frame was dropped because the internal descriptor FIFO is full - */ -#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK (0x10U) -#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT (4U) -#define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO failure, internal controller lost synchronization - */ -#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK (0x1U) -#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_RESET */ -/* - * RESET (W1C) - * - * resets controller and clears all pending stream data - */ -#define TSW_APB2AXIS_ALMEM_RESET_RESET_MASK (0x1U) -#define TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK) -#define TSW_APB2AXIS_ALMEM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK) >> TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_PARAM */ -/* - * DEPTH (RO) - * - * number of configured buffer depth - */ -#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK (0xFF00U) -#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT (8U) -#define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT) - -/* - * WORDLEN_BYTE (RO) - * - * number of configured 32bit words for this controller - */ -#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK (0xFFU) -#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_REQDATA_0 */ -/* - * UTAG (R/W) - * - * user sideband information - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK (0x1C00000UL) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT (22U) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT) - -/* - * QSEL (R/W) - * - * define the traffic queue selection - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK (0x300000UL) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT (20U) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT) - -/* - * DROP (R/W) - * - * frame should dropped - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK (0x80000UL) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT (19U) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT) - -/* - * QUEUE (R/W) - * - * select the priority queue if qsel=11 - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK (0x70000UL) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT (16U) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT) - -/* - * DEST (R/W) - * - * destination ports - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK (0xFFFFU) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT) - -/* Bitfield definition for register: APB2AXIS_ALMEM_REQDATA_1 */ -/* - * WR_NRD (R/W) - * - * 1 for write and 0 for read - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK (0x80000000UL) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT (31U) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT) - -/* - * RESP (R/W) - * - * write response enable - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK (0x40000000UL) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT (30U) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT) - -/* - * ENTRY_NUM (R/W) - * - * define the entry number for reading and writing - */ -#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK (0xFFFFU) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT (0U) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) -#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_STS */ -/* - * BUSY (RO) - * - * the controller is writing data and/or data is pending - */ -#define TSW_AXIS2APB_ALMEM_STS_BUSY_MASK (0x2U) -#define TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT (1U) -#define TSW_AXIS2APB_ALMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_BUSY_MASK) >> TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT) - -/* - * RDY (RO) - * - * the new data is written to data register - */ -#define TSW_AXIS2APB_ALMEM_STS_RDY_MASK (0x1U) -#define TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_RDY_MASK) >> TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_RESP_CNT */ -/* - * RDCNT (RO) - * - * number of streams in queue - */ -#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK (0xFFU) -#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_FILLSTS */ -/* - * FULL (RO) - * - * FD FIFO full - */ -#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK (0x10U) -#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT (4U) -#define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO failure - */ -#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK (0x1U) -#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_RESET */ -/* - * RESET (R/W) - * - * Resets controller and clears all pending stream data - */ -#define TSW_AXIS2APB_ALMEM_RESET_RESET_MASK (0x1U) -#define TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK) -#define TSW_AXIS2APB_ALMEM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK) >> TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_PARAM */ -/* - * DEPTH (RO) - * - * number of configured buffer depth - */ -#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK (0xFF00U) -#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT (8U) -#define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT) - -/* - * WORDLEN_BYTE (RO) - * - * number of configured 32bit for this controller - */ -#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK (0xFFU) -#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_RESPDATA_0 */ -/* - * UTAG (R/W) - * - * user sideband information - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK (0x1C00000UL) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT (22U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT) - -/* - * QSEL (R/W) - * - * define the traffic queue selection - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK (0x300000UL) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT (20U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT) - -/* - * DROP (R/W) - * - * frame should dropped - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK (0x80000UL) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT (19U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT) - -/* - * QUEUE (R/W) - * - * select the priority queue if qsel=11 - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK (0x70000UL) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT (16U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT) - -/* - * DEST (R/W) - * - * destination ports - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK (0xFFFFU) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT) - -/* Bitfield definition for register: AXIS2APB_ALMEM_RESPDATA_1 */ -/* - * WR_NRD (R/W) - * - * 1 for write and 0 for read - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK (0x80000000UL) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT (31U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT) - -/* - * RESP (R/W) - * - * write response enable - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK (0x40000000UL) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT (30U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT) - -/* - * ENTRY_NUM (R/W) - * - * define the entry number for reading and writing - */ -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK (0xFFFFU) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT (0U) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK) -#define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT) - -/* Bitfield definition for register array: HITMEM */ -/* - * HITMEM_REG (RW) - * - * Every bit represents a lookup entry starting with bit 0 - * as entry 0. The memory can be written and cleared by the host system via common memory-mapped - * bus access. - */ -#define TSW_HITMEM_HITMEM_REG_MASK (0xFFFFFFFFUL) -#define TSW_HITMEM_HITMEM_REG_SHIFT (0U) -#define TSW_HITMEM_HITMEM_REG_SET(x) (((uint32_t)(x) << TSW_HITMEM_HITMEM_REG_SHIFT) & TSW_HITMEM_HITMEM_REG_MASK) -#define TSW_HITMEM_HITMEM_REG_GET(x) (((uint32_t)(x) & TSW_HITMEM_HITMEM_REG_MASK) >> TSW_HITMEM_HITMEM_REG_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_STS */ -/* - * BUSY (RO) - * - * the controller is writing data and/or data is pending - */ -#define TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK (0x2U) -#define TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT (1U) -#define TSW_APB2AXIS_LOOKUP_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT) - -/* - * RDY (RO) - * - * the new data is written to data register - */ -#define TSW_APB2AXIS_LOOKUP_STS_RDY_MASK (0x1U) -#define TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_RDY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_REQ_CNT */ -/* - * WRCNT (RO) - * - * number of streams in queue - */ -#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK (0xFFU) -#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_FILLSTS */ -/* - * FULL (RO) - * - * FD FIFO full - */ -#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK (0x10U) -#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT (4U) -#define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO failure - */ -#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK (0x1U) -#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_RESET */ -/* - * RESET (R/W) - * - * Resets controller and clears all pending stream data - */ -#define TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK (0x1U) -#define TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK) -#define TSW_APB2AXIS_LOOKUP_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK) >> TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_PARAM */ -/* - * DEPTH (RO) - * - * number of configured buffer depth - */ -#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK (0xFF00U) -#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT (8U) -#define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT) - -/* - * WORDLEN_BYTE (RO) - * - * number of configured 32bit for this controller - */ -#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK (0xFFU) -#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_0 */ -/* - * DESTMAC (RW) - * - * Holding the first four bytes of requested MAC address. - */ -#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK (0xFFFFFFFFUL) -#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK) -#define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_1 */ -/* - * DESTMAC (RW) - * - * Holding the last two bytes of requested MAC address. - */ -#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK (0xFFFFU) -#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK) -#define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT) - -/* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_3 */ -/* - * IS_VLAN (RW) - * - * Tell the LOOKUP module the requested traffic is VLAN tagged. - */ -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK (0x10000UL) -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT (16U) -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK) -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT) - -/* - * VLAN_TCI (RW) - * - * Set the requested traffic VLAN_TCI, if IS_VLAN=1. - */ -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK (0xFFFFU) -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT (0U) -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK) -#define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_STS */ -/* - * BUSY (RO) - * - * the controller is writing data and/or data is pending - */ -#define TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK (0x2U) -#define TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT (1U) -#define TSW_AXIS2APB_LOOKUP_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT) - -/* - * RDY (RO) - * - * the new data is written to data register - */ -#define TSW_AXIS2APB_LOOKUP_STS_RDY_MASK (0x1U) -#define TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_STS_RDY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_RDY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_RESP_CNT */ -/* - * RDCNT (RO) - * - * number of streams in queue - */ -#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK (0xFFU) -#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_FILLSTS */ -/* - * FULL (RO) - * - * FD FIFO full - */ -#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK (0x10U) -#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT (4U) -#define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO failure - */ -#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK (0x1U) -#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_RESET */ -/* - * RESET (R/W) - * - * Resets controller and clears all pending stream data - */ -#define TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK (0x1U) -#define TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK) -#define TSW_AXIS2APB_LOOKUP_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK) >> TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_PARAM */ -/* - * DEPTH (RO) - * - * number of configured buffer depth - */ -#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK (0xFF00U) -#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT (8U) -#define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT) - -/* - * WORDLEN_BYTE (RO) - * - * number of configured 32bit for this controller - */ -#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK (0xFFU) -#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_RESPDATA_0 */ -/* - * DROP_VLAN (RW) - * - * Used for statistics. Shows that drop occurs by VLAN-ID - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK (0x2000000UL) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT (25U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT) - -/* - * HIT (RW) - * - * Is 1, if DESTMAC and VID hit an entry. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK (0x1000000UL) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT (24U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT) - -/* - * UTAG (RW) - * - * TSN user sideband information from ALMEM. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK (0xE00000UL) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT (21U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT) - -/* - * HIT_VLAN (RW) - * - * Is 1, if VID hit entry in VLAN_PORT table. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK (0x100000UL) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT (20U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT) - -/* - * DROP (RW) - * - * Indicate that the frame should be dropped. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK (0x80000UL) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT (19U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT) - -/* - * QUEUE (RW) - * - * TX traffic queue selection. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK (0x70000UL) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT (16U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT) - -/* - * DEST (RW) - * - * Forwarding ports from 0 to 15, Bit 0 is CPU port. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK (0xFFFFU) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT) - -/* Bitfield definition for register: AXIS2APB_LOOKUP_RESPDATA_1 */ -/* - * ENTRY_NUM (RW) - * - * Entry number of ALMEM. - */ -#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK (0xFFFFU) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT (0U) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK) -#define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT) - -/* Bitfield definition for register: CENTRAL_CSR_VERSION */ -/* - * VER_HI (RO) - * - * Major Version number of TSN-SW core. - */ -#define TSW_CENTRAL_CSR_VERSION_VER_HI_MASK (0xFF000000UL) -#define TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT (24U) -#define TSW_CENTRAL_CSR_VERSION_VER_HI_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_HI_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT) - -/* - * VER_LO (RO) - * - * Minor Version number of TSN-SW core. - */ -#define TSW_CENTRAL_CSR_VERSION_VER_LO_MASK (0xFF0000UL) -#define TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT (16U) -#define TSW_CENTRAL_CSR_VERSION_VER_LO_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_LO_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT) - -/* - * VER_REV (RO) - * - * Reversion number of TSN-SW core. - */ -#define TSW_CENTRAL_CSR_VERSION_VER_REV_MASK (0xFFU) -#define TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT (0U) -#define TSW_CENTRAL_CSR_VERSION_VER_REV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_REV_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT) - -/* Bitfield definition for register: CENTRAL_CSR_PARAM */ -/* - * INCL_QCI (RO) - * - * Shows if QCI module is present. - */ -#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK (0x40000UL) -#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT (18U) -#define TSW_CENTRAL_CSR_PARAM_INCL_QCI_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT) - -/* - * INCL_CB0 (RO) - * - * Shows if IP is configured with “lightweight” 802.1CB at CPU-Port. - */ -#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK (0x20000UL) -#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT (17U) -#define TSW_CENTRAL_CSR_PARAM_INCL_CB0_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT) - -/* - * TESTMODE (RO) - * - * Shows if IP is configured in TESTMODE. - */ -#define TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK (0x10000UL) -#define TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT (16U) -#define TSW_CENTRAL_CSR_PARAM_TESTMODE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK) >> TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT) - -/* - * TYPE (RO) - * - * Specify type of switch core - */ -#define TSW_CENTRAL_CSR_PARAM_TYPE_MASK (0xFF00U) -#define TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT (8U) -#define TSW_CENTRAL_CSR_PARAM_TYPE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TYPE_MASK) >> TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT) - -/* - * NPORTS (RO) - * - * Number of TSN ports without counting internal CPU port. For TSN-SE, it returns always 2 - */ -#define TSW_CENTRAL_CSR_PARAM_NPORTS_MASK (0xFFU) -#define TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT (0U) -#define TSW_CENTRAL_CSR_PARAM_NPORTS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_NPORTS_MASK) >> TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT) - -/* Bitfield definition for register: CENTRAL_CSR_CONFIG */ -/* - * MSEC_CYCLES (R/W) - * - * Number of SYS_CLK cycles during 1 ms. It is required to calculate a correct time - */ -#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK (0xFFFFFFUL) -#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT (0U) -#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SET(x) (((uint32_t)(x) << TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK) -#define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK) >> TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT) - -/* Bitfield definition for register: CENTRAL_CSR_CB_PARAM */ -/* - * SID_D (RO) - * - * Number of 802.1CB Stream Identification entries. 2^SID_D entries - */ -#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK (0xFF00U) -#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT (8U) -#define TSW_CENTRAL_CSR_CB_PARAM_SID_D_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT) - -/* - * FRER_D (RO) - * - * Number of 802.1CB Recovery Function entries. 2^FRER_D entries. - */ -#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK (0xFFU) -#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT (0U) -#define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT) - -/* Bitfield definition for register: CENTRAL_CSR_QCI_CTRL_PARAM */ -/* - * QCI_GTD (RO) - * - * (Log) gate table depth. 2**GTD entries. - */ -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK (0xFF0000UL) -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT (16U) -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT) - -/* - * QCI_FMD (RO) - * - * (Log) flow meter depth. 2**FMD entries. - */ -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK (0xFF00U) -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT (8U) -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT) - -/* - * QCI_FTD (RO) - * - * (Log) filter table depth. 2**FTD entries. - */ -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK (0xFFU) -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT (0U) -#define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_HWCFG */ -/* - * FMD (RO) - * - * FMD – parameter - */ -#define TSW_CENTRAL_QCI_HWCFG_FMD_MASK (0xFF0000UL) -#define TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT (16U) -#define TSW_CENTRAL_QCI_HWCFG_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FMD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT) - -/* - * GTD (RO) - * - * GTD – parameter - */ -#define TSW_CENTRAL_QCI_HWCFG_GTD_MASK (0xFF00U) -#define TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT (8U) -#define TSW_CENTRAL_QCI_HWCFG_GTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_GTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT) - -/* - * FTD (RO) - * - * FTD – parameter - */ -#define TSW_CENTRAL_QCI_HWCFG_FTD_MASK (0xFFU) -#define TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT (0U) -#define TSW_CENTRAL_QCI_HWCFG_FTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_FILTERSEL */ -/* - * INDEX (R/W) - * - * Filter select index - * Any written value larger than the maximum index - * (2**FTD-1) will result in a read-back value of <0>. - */ -#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK (0xFFU) -#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT (0U) -#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK) -#define TSW_CENTRAL_QCI_FILTERSEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_METERSEL */ -/* - * INDEX (R/W) - * - * Flowmeter select index - * Any written value larger than the maximum index - * (2**FMD-1) will result in a read-back value of <0>. - */ -#define TSW_CENTRAL_QCI_METERSEL_INDEX_MASK (0xFFU) -#define TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT (0U) -#define TSW_CENTRAL_QCI_METERSEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK) -#define TSW_CENTRAL_QCI_METERSEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_GATESEL */ -/* - * INDEX (R/W) - * - * Gate select index - * Any written value larger than the maximum index - * (2**GTD-1) will result in a read-back value of <0>. - */ -#define TSW_CENTRAL_QCI_GATESEL_INDEX_MASK (0xFFU) -#define TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT (0U) -#define TSW_CENTRAL_QCI_GATESEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK) -#define TSW_CENTRAL_QCI_GATESEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK) >> TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_FCTRL */ -/* - * ENBLK (R/W) - * - * Enable blocking of oversized frames - * (802.1Qci – 8.6.5.1.1 (g)) - */ -#define TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK (0x80000000UL) -#define TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT (31U) -#define TSW_CENTRAL_QCI_FCTRL_ENBLK_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK) -#define TSW_CENTRAL_QCI_FCTRL_ENBLK_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT) - -/* - * ENFSZ (R/W) - * - * 0: No frame size check - * 1: Frame size checking, size defined by FSIZE.MXSZ - * (802.1Qci – 8.6.5.1.1 (e.1)) - */ -#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK (0x40000000UL) -#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT (30U) -#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK) -#define TSW_CENTRAL_QCI_FCTRL_ENFSZ_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT) - -/* - * ENFID (R/W) - * - * 0: No Flow Meter - * 1: Enable Flow Metering - * (802.1Qci – 8.6.5.1.1 (e.2)) - */ -#define TSW_CENTRAL_QCI_FCTRL_ENFID_MASK (0x20000000UL) -#define TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT (29U) -#define TSW_CENTRAL_QCI_FCTRL_ENFID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK) -#define TSW_CENTRAL_QCI_FCTRL_ENFID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT) - -/* - * ENSID (R/W) - * - * 0: Filter match any SID value - * 1: Filter match SID value - * (802.1Qci – 8.6.5.1.1 (b)) - */ -#define TSW_CENTRAL_QCI_FCTRL_ENSID_MASK (0x10000000UL) -#define TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT (28U) -#define TSW_CENTRAL_QCI_FCTRL_ENSID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK) -#define TSW_CENTRAL_QCI_FCTRL_ENSID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT) - -/* - * ENPCP (R/W) - * - * 0: Filter match any PCP value - * 1: Filter match PCP value - * (802.1Qci – 8.6.5.1.1 (c)) - */ -#define TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK (0x8000000UL) -#define TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT (27U) -#define TSW_CENTRAL_QCI_FCTRL_ENPCP_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK) -#define TSW_CENTRAL_QCI_FCTRL_ENPCP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT) - -/* - * PCP (R/W) - * - * Filter priority code point, if enabled by ENPCP - */ -#define TSW_CENTRAL_QCI_FCTRL_PCP_MASK (0x7000000UL) -#define TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT (24U) -#define TSW_CENTRAL_QCI_FCTRL_PCP_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK) -#define TSW_CENTRAL_QCI_FCTRL_PCP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT) - -/* - * FMD (R/W) - * - * Associated Flow Meter – if enabled by ENFID - */ -#define TSW_CENTRAL_QCI_FCTRL_FMD_MASK (0xFF0000UL) -#define TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT (16U) -#define TSW_CENTRAL_QCI_FCTRL_FMD_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK) -#define TSW_CENTRAL_QCI_FCTRL_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK) >> TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT) - -/* - * GID (R/W) - * - * Associated Gate - */ -#define TSW_CENTRAL_QCI_FCTRL_GID_MASK (0xFF00U) -#define TSW_CENTRAL_QCI_FCTRL_GID_SHIFT (8U) -#define TSW_CENTRAL_QCI_FCTRL_GID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_GID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_GID_MASK) -#define TSW_CENTRAL_QCI_FCTRL_GID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_GID_MASK) >> TSW_CENTRAL_QCI_FCTRL_GID_SHIFT) - -/* - * SID (R/W) - * - * Filter Stream ID – if enabled by ENSID - */ -#define TSW_CENTRAL_QCI_FCTRL_SID_MASK (0xFFU) -#define TSW_CENTRAL_QCI_FCTRL_SID_SHIFT (0U) -#define TSW_CENTRAL_QCI_FCTRL_SID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_SID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_SID_MASK) -#define TSW_CENTRAL_QCI_FCTRL_SID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_SID_MASK) >> TSW_CENTRAL_QCI_FCTRL_SID_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_FSIZE */ -/* - * BLK (R/WC) - * - * Stream blocked due to oversize frame. - * Write <1> to clear. - * (802.1Qci – 8.6.5.1.1 (h)) - */ -#define TSW_CENTRAL_QCI_FSIZE_BLK_MASK (0x80000000UL) -#define TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT (31U) -#define TSW_CENTRAL_QCI_FSIZE_BLK_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK) -#define TSW_CENTRAL_QCI_FSIZE_BLK_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK) >> TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT) - -/* - * MXSZ (R/W) - * - * Maximum-SDU size in octets - */ -#define TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK (0xFFFFU) -#define TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT (0U) -#define TSW_CENTRAL_QCI_FSIZE_MXSZ_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK) -#define TSW_CENTRAL_QCI_FSIZE_MXSZ_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK) >> TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT) - -/* Bitfield definition for register array: QCI_CNT */ -/* - * VALUE (RO) - * - * Filter counter (see 802.1Qci 8.6.5.1.1 f) - * CNT0: Frames that matched filter - * CNT1: Frames that passed gate - * CNT2: Frames that did not pass gate - * CNT3: Frames that passed Maximum-SDU size check - * CNT4: Frames that did not pass size check - * CNT5: Frames discarded by Flow Meter operation - * Counters starting at value <0> after reset. - */ -#define TSW_QCI_CNT_VALUE_MASK (0xFFFFFFFFUL) -#define TSW_QCI_CNT_VALUE_SHIFT (0U) -#define TSW_QCI_CNT_VALUE_GET(x) (((uint32_t)(x) & TSW_QCI_CNT_VALUE_MASK) >> TSW_QCI_CNT_VALUE_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_MCTRL */ -/* - * RESET (WO) - * - * Flow Meter reset – self-resetting to <0> - */ -#define TSW_CENTRAL_QCI_MCTRL_RESET_MASK (0x80000000UL) -#define TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT (31U) -#define TSW_CENTRAL_QCI_MCTRL_RESET_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK) -#define TSW_CENTRAL_QCI_MCTRL_RESET_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK) >> TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT) - -/* - * MAFR (RO) - * - * MarkAllFramesRed – cleared by RESET - * (802.1Qci – 8.6.5.1.3 (j)) - */ -#define TSW_CENTRAL_QCI_MCTRL_MAFR_MASK (0x10U) -#define TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT (4U) -#define TSW_CENTRAL_QCI_MCTRL_MAFR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFR_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT) - -/* - * MAFREN (R/W) - * - * MarkAllFramesRedEnable - * (802.1Qci – 8.6.5.1.3 (i)) - */ -#define TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK (0x8U) -#define TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT (3U) -#define TSW_CENTRAL_QCI_MCTRL_MAFREN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK) -#define TSW_CENTRAL_QCI_MCTRL_MAFREN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT) - -/* - * DOY (R/W) - * - * DropOnYellow - * (802.1Qci – 8.6.5.1.3 (h)) - */ -#define TSW_CENTRAL_QCI_MCTRL_DOY_MASK (0x4U) -#define TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT (2U) -#define TSW_CENTRAL_QCI_MCTRL_DOY_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK) -#define TSW_CENTRAL_QCI_MCTRL_DOY_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK) >> TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT) - -/* - * CM (R/W) - * - * Color mode – functionally unused - * (802.1Qci – 8.6.5.1.3 (g)) - */ -#define TSW_CENTRAL_QCI_MCTRL_CM_MASK (0x2U) -#define TSW_CENTRAL_QCI_MCTRL_CM_SHIFT (1U) -#define TSW_CENTRAL_QCI_MCTRL_CM_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CM_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CM_MASK) -#define TSW_CENTRAL_QCI_MCTRL_CM_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CM_MASK) >> TSW_CENTRAL_QCI_MCTRL_CM_SHIFT) - -/* - * CF (R/W) - * - * Coupling flag - * (802.1Qci – 8.6.5.1.3 (f)) - */ -#define TSW_CENTRAL_QCI_MCTRL_CF_MASK (0x1U) -#define TSW_CENTRAL_QCI_MCTRL_CF_SHIFT (0U) -#define TSW_CENTRAL_QCI_MCTRL_CF_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CF_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CF_MASK) -#define TSW_CENTRAL_QCI_MCTRL_CF_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CF_MASK) >> TSW_CENTRAL_QCI_MCTRL_CF_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_CIR */ -/* - * CIR (R/W) - * - * Committed information rate – see Chapter 7.5.2.4. - * (802.1Qci – 8.6.5.1.3 (b)) - */ -#define TSW_CENTRAL_QCI_CIR_CIR_MASK (0xFFFFFFUL) -#define TSW_CENTRAL_QCI_CIR_CIR_SHIFT (0U) -#define TSW_CENTRAL_QCI_CIR_CIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_CIR_CIR_SHIFT) & TSW_CENTRAL_QCI_CIR_CIR_MASK) -#define TSW_CENTRAL_QCI_CIR_CIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_CIR_CIR_MASK) >> TSW_CENTRAL_QCI_CIR_CIR_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_CBS */ -/* - * CBS (R/W) - * - * Committed burst size, in bits (not octets!) - * (802.1Qci – 8.6.5.1.3 (c)) - */ -#define TSW_CENTRAL_QCI_CBS_CBS_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_CBS_CBS_SHIFT (0U) -#define TSW_CENTRAL_QCI_CBS_CBS_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_CBS_CBS_SHIFT) & TSW_CENTRAL_QCI_CBS_CBS_MASK) -#define TSW_CENTRAL_QCI_CBS_CBS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_CBS_CBS_MASK) >> TSW_CENTRAL_QCI_CBS_CBS_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_EIR */ -/* - * EIR (R/W) - * - * Excess information rate – see Chapter 7.5.2.4. - * (802.1Qci – 8.6.5.1.3 (d)) - */ -#define TSW_CENTRAL_QCI_EIR_EIR_MASK (0xFFFFFFUL) -#define TSW_CENTRAL_QCI_EIR_EIR_SHIFT (0U) -#define TSW_CENTRAL_QCI_EIR_EIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_EIR_EIR_SHIFT) & TSW_CENTRAL_QCI_EIR_EIR_MASK) -#define TSW_CENTRAL_QCI_EIR_EIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_EIR_EIR_MASK) >> TSW_CENTRAL_QCI_EIR_EIR_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_EBS */ -/* - * EBS (R/W) - * - * Excess burst size, in bits (not octets) - * (802.1Qci – 8.6.5.1.3 (e)) - */ -#define TSW_CENTRAL_QCI_EBS_EBS_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_EBS_EBS_SHIFT (0U) -#define TSW_CENTRAL_QCI_EBS_EBS_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_EBS_EBS_SHIFT) & TSW_CENTRAL_QCI_EBS_EBS_MASK) -#define TSW_CENTRAL_QCI_EBS_EBS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_EBS_EBS_MASK) >> TSW_CENTRAL_QCI_EBS_EBS_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_GCTRL */ -/* - * IPV (R/W) - * - * Administrative internal priority value specification - * (802.1Qci – 8.6.5.1.2 (c)) - */ -#define TSW_CENTRAL_QCI_GCTRL_IPV_MASK (0xE0U) -#define TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT (5U) -#define TSW_CENTRAL_QCI_GCTRL_IPV_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK) -#define TSW_CENTRAL_QCI_GCTRL_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK) >> TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT) - -/* - * STATE (R/W) - * - * Administrative stream gate state - * (802.1Qci – 8.6.5.1.2 (b)) - */ -#define TSW_CENTRAL_QCI_GCTRL_STATE_MASK (0x10U) -#define TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT (4U) -#define TSW_CENTRAL_QCI_GCTRL_STATE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK) -#define TSW_CENTRAL_QCI_GCTRL_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK) >> TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT) - -/* - * CDOEE (R/W) - * - * Gate – ClosedDueToOctetsExceededEnable - * (802.1Qci – 8.6.5.1.2 (f)) - */ -#define TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK (0x8U) -#define TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT (3U) -#define TSW_CENTRAL_QCI_GCTRL_CDOEE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK) -#define TSW_CENTRAL_QCI_GCTRL_CDOEE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT) - -/* - * CDIRE (R/W) - * - * Gate – ClosedDueToInvalidRxEnable - * (802.1Qci – 8.6.5.1.2 (d)) - */ -#define TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK (0x4U) -#define TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT (2U) -#define TSW_CENTRAL_QCI_GCTRL_CDIRE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK) -#define TSW_CENTRAL_QCI_GCTRL_CDIRE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT) - -/* - * CFGCH (R/W) - * - * Gate – change config (self-resetting to <0>) - */ -#define TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK (0x2U) -#define TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT (1U) -#define TSW_CENTRAL_QCI_GCTRL_CFGCH_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK) -#define TSW_CENTRAL_QCI_GCTRL_CFGCH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK) >> TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT) - -/* - * EN (R/W) - * - * Gate control – enable - */ -#define TSW_CENTRAL_QCI_GCTRL_EN_MASK (0x1U) -#define TSW_CENTRAL_QCI_GCTRL_EN_SHIFT (0U) -#define TSW_CENTRAL_QCI_GCTRL_EN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_EN_SHIFT) & TSW_CENTRAL_QCI_GCTRL_EN_MASK) -#define TSW_CENTRAL_QCI_GCTRL_EN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_EN_MASK) >> TSW_CENTRAL_QCI_GCTRL_EN_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_GSTATUS */ -/* - * IPV (RO) - * - * Operational internal priority value specification - * (802.1Qci – 8.6.5.1.2 (c)) - */ -#define TSW_CENTRAL_QCI_GSTATUS_IPV_MASK (0xE0U) -#define TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT (5U) -#define TSW_CENTRAL_QCI_GSTATUS_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_IPV_MASK) >> TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT) - -/* - * STATE (RO) - * - * Operational stream gate state - * (802.1Qci – 8.6.5.1.2 (b)) - */ -#define TSW_CENTRAL_QCI_GSTATUS_STATE_MASK (0x10U) -#define TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT (4U) -#define TSW_CENTRAL_QCI_GSTATUS_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_STATE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT) - -/* - * CDOE (WC) - * - * Gate – ClosedDueToOctetsExceeded. Write <1> to - * clear. - * (802.1Qci – 8.6.5.1.2 (g)) - */ -#define TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK (0x8U) -#define TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT (3U) -#define TSW_CENTRAL_QCI_GSTATUS_CDOE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK) -#define TSW_CENTRAL_QCI_GSTATUS_CDOE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT) - -/* - * CDIR (WC) - * - * Gate – ClosedDueToInvalidRx. Write <1> to clear. - * (802.1Qci – 8.6.5.1.2 (e)) - */ -#define TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK (0x4U) -#define TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT (2U) -#define TSW_CENTRAL_QCI_GSTATUS_CDIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK) -#define TSW_CENTRAL_QCI_GSTATUS_CDIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT) - -/* - * CFGP (RO) - * - * Configuration change pending - */ -#define TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK (0x2U) -#define TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT (1U) -#define TSW_CENTRAL_QCI_GSTATUS_CFGP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT) - -/* - * CFGERR (WC) - * - * Configuration change error. Write <1> to clear. - */ -#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK (0x1U) -#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT (0U) -#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK) -#define TSW_CENTRAL_QCI_GSTATUS_CFGERR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_GLISTINDEX */ -/* - * IDX (R/W) - * - * Admin list pointer, select entry 0 – 15. - */ -#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK (0xFU) -#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT (0U) -#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK) -#define TSW_CENTRAL_QCI_GLISTINDEX_IDX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK) >> TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_LISTLEN */ -/* - * OLEN (RO) - * - * Operational list length - */ -#define TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK (0xF0000UL) -#define TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT (16U) -#define TSW_CENTRAL_QCI_LISTLEN_OLEN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT) - -/* - * ALEN (R/W) - * - * Administrative list length - */ -#define TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK (0xFU) -#define TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT (0U) -#define TSW_CENTRAL_QCI_LISTLEN_ALEN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK) -#define TSW_CENTRAL_QCI_LISTLEN_ALEN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_ACYCLETM */ -/* - * ACT (R/W) - * - * Administrative cycle time length, nanoseconds. - */ -#define TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK (0x3FFFFFFFUL) -#define TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT (0U) -#define TSW_CENTRAL_QCI_ACYCLETM_ACT_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK) -#define TSW_CENTRAL_QCI_ACYCLETM_ACT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK) >> TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_ABASETM_L */ -/* - * ABTL (R/W) - * - * Administrative base time. Nanoseconds and seconds part. Cycle starts after becoming operational when time is reached by inputs and . - */ -#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK (0x3FFFFFFFUL) -#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT (0U) -#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK) -#define TSW_CENTRAL_QCI_ABASETM_L_ABTL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK) >> TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_ABASETM_H */ -/* - * ABTH (R/W) - * - */ -#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT (0U) -#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK) -#define TSW_CENTRAL_QCI_ABASETM_H_ABTH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK) >> TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_AENTRY_CTRL */ -/* - * STATE (R/W) - * - * AdminList – gate state (1: open) - */ -#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK (0x80000000UL) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT (31U) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT) - -/* - * IPV (R/W) - * - * AdminList – IPV - */ -#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK (0x70000000UL) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT (28U) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT) - -/* - * OCT (R/W) - * - * AdminList – maximum octets (0 – disabled) - */ -#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK (0xFFFFFFFUL) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT (0U) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK) -#define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_AENTRY_AENTRY_IVAL */ -/* - * IVAL (R/W) - * - * AdminList – time interval in clock ticks - */ -#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT (0U) -#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK) -#define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK) >> TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_AENTRY_OCYCLETM */ -/* - * OCT (RO) - * - * OperCycleTime in nanoseconds - */ -#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT (0U) -#define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_AENTRY_OBASETM_L */ -/* - * OBTL (RO) - * - * OperBaseTime – nanoseconds and seconds. Constantly - * updated – OperBaseTime + N * OperCycleTimt. Might - * be non-normalized. - */ -#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT (0U) -#define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT) - -/* Bitfield definition for register: CENTRAL_QCI_AENTRY_OBASETM_H */ -/* - * OBTH (RO) - * - */ -#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK (0xFFFFFFFFUL) -#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT (0U) -#define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT) - -/* Bitfield definition for register: MM2S_DMA_CR */ -/* - * MXLEN (RW) - * - * max axi burst size - */ -#define TSW_MM2S_DMA_CR_MXLEN_MASK (0xFF000000UL) -#define TSW_MM2S_DMA_CR_MXLEN_SHIFT (24U) -#define TSW_MM2S_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_MXLEN_SHIFT) & TSW_MM2S_DMA_CR_MXLEN_MASK) -#define TSW_MM2S_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_MXLEN_MASK) >> TSW_MM2S_DMA_CR_MXLEN_SHIFT) - -/* - * IRQEN (RW) - * - * interrupt request enable - */ -#define TSW_MM2S_DMA_CR_IRQEN_MASK (0x8U) -#define TSW_MM2S_DMA_CR_IRQEN_SHIFT (3U) -#define TSW_MM2S_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_IRQEN_SHIFT) & TSW_MM2S_DMA_CR_IRQEN_MASK) -#define TSW_MM2S_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_IRQEN_MASK) >> TSW_MM2S_DMA_CR_IRQEN_SHIFT) - -/* - * RESET (WO) - * - * do reset when active - */ -#define TSW_MM2S_DMA_CR_RESET_MASK (0x4U) -#define TSW_MM2S_DMA_CR_RESET_SHIFT (2U) -#define TSW_MM2S_DMA_CR_RESET_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_RESET_SHIFT) & TSW_MM2S_DMA_CR_RESET_MASK) -#define TSW_MM2S_DMA_CR_RESET_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_RESET_MASK) >> TSW_MM2S_DMA_CR_RESET_SHIFT) - -/* - * SOE (RW) - * - * stop on error flag - */ -#define TSW_MM2S_DMA_CR_SOE_MASK (0x2U) -#define TSW_MM2S_DMA_CR_SOE_SHIFT (1U) -#define TSW_MM2S_DMA_CR_SOE_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_SOE_SHIFT) & TSW_MM2S_DMA_CR_SOE_MASK) -#define TSW_MM2S_DMA_CR_SOE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_SOE_MASK) >> TSW_MM2S_DMA_CR_SOE_SHIFT) - -/* - * RUN (RW) - * - * run command from queue to data mover - */ -#define TSW_MM2S_DMA_CR_RUN_MASK (0x1U) -#define TSW_MM2S_DMA_CR_RUN_SHIFT (0U) -#define TSW_MM2S_DMA_CR_RUN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_RUN_SHIFT) & TSW_MM2S_DMA_CR_RUN_MASK) -#define TSW_MM2S_DMA_CR_RUN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_RUN_MASK) >> TSW_MM2S_DMA_CR_RUN_SHIFT) - -/* Bitfield definition for register: MM2S_DMA_SR */ -/* - * RBUFF (RO) - * - * response buffer full - */ -#define TSW_MM2S_DMA_SR_RBUFF_MASK (0x80U) -#define TSW_MM2S_DMA_SR_RBUFF_SHIFT (7U) -#define TSW_MM2S_DMA_SR_RBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFF_MASK) >> TSW_MM2S_DMA_SR_RBUFF_SHIFT) - -/* - * RBUFE (RO) - * - * response buffer empty - */ -#define TSW_MM2S_DMA_SR_RBUFE_MASK (0x40U) -#define TSW_MM2S_DMA_SR_RBUFE_SHIFT (6U) -#define TSW_MM2S_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFE_MASK) >> TSW_MM2S_DMA_SR_RBUFE_SHIFT) - -/* - * CBUFF (RO) - * - * command buffer full - */ -#define TSW_MM2S_DMA_SR_CBUFF_MASK (0x20U) -#define TSW_MM2S_DMA_SR_CBUFF_SHIFT (5U) -#define TSW_MM2S_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFF_MASK) >> TSW_MM2S_DMA_SR_CBUFF_SHIFT) - -/* - * CBUFE (RO) - * - * command buffer empty - */ -#define TSW_MM2S_DMA_SR_CBUFE_MASK (0x10U) -#define TSW_MM2S_DMA_SR_CBUFE_SHIFT (4U) -#define TSW_MM2S_DMA_SR_CBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFE_MASK) >> TSW_MM2S_DMA_SR_CBUFE_SHIFT) - -/* - * IRQ (RWC) - * - * interrupt request pending - */ -#define TSW_MM2S_DMA_SR_IRQ_MASK (0x8U) -#define TSW_MM2S_DMA_SR_IRQ_SHIFT (3U) -#define TSW_MM2S_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_SR_IRQ_SHIFT) & TSW_MM2S_DMA_SR_IRQ_MASK) -#define TSW_MM2S_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_IRQ_MASK) >> TSW_MM2S_DMA_SR_IRQ_SHIFT) - -/* - * RSET (RO) - * - * resetting status - */ -#define TSW_MM2S_DMA_SR_RSET_MASK (0x4U) -#define TSW_MM2S_DMA_SR_RSET_SHIFT (2U) -#define TSW_MM2S_DMA_SR_RSET_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RSET_MASK) >> TSW_MM2S_DMA_SR_RSET_SHIFT) - -/* - * BUSY (RO) - * - * busy - */ -#define TSW_MM2S_DMA_SR_BUSY_MASK (0x2U) -#define TSW_MM2S_DMA_SR_BUSY_SHIFT (1U) -#define TSW_MM2S_DMA_SR_BUSY_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_BUSY_MASK) >> TSW_MM2S_DMA_SR_BUSY_SHIFT) - -/* - * STOP (RO) - * - * mm2s is stopped - */ -#define TSW_MM2S_DMA_SR_STOP_MASK (0x1U) -#define TSW_MM2S_DMA_SR_STOP_SHIFT (0U) -#define TSW_MM2S_DMA_SR_STOP_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_STOP_MASK) >> TSW_MM2S_DMA_SR_STOP_SHIFT) - -/* Bitfield definition for register: MM2S_DMA_FILL */ -/* - * RFILL (RO) - * - * response buffer fill level - */ -#define TSW_MM2S_DMA_FILL_RFILL_MASK (0xFFFF0000UL) -#define TSW_MM2S_DMA_FILL_RFILL_SHIFT (16U) -#define TSW_MM2S_DMA_FILL_RFILL_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_FILL_RFILL_MASK) >> TSW_MM2S_DMA_FILL_RFILL_SHIFT) - -/* - * CFILL (RO) - * - * command buffer fill level - */ -#define TSW_MM2S_DMA_FILL_CFILL_MASK (0xFFFFU) -#define TSW_MM2S_DMA_FILL_CFILL_SHIFT (0U) -#define TSW_MM2S_DMA_FILL_CFILL_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_FILL_CFILL_MASK) >> TSW_MM2S_DMA_FILL_CFILL_SHIFT) - -/* Bitfield definition for register: MM2S_DMA_CFG */ -/* - * DBUFD (RO) - * - * data buffer depth - */ -#define TSW_MM2S_DMA_CFG_DBUFD_MASK (0xF000000UL) -#define TSW_MM2S_DMA_CFG_DBUFD_SHIFT (24U) -#define TSW_MM2S_DMA_CFG_DBUFD_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_DBUFD_MASK) >> TSW_MM2S_DMA_CFG_DBUFD_SHIFT) - -/* - * CBUFD (RO) - * - * command buffer depth - */ -#define TSW_MM2S_DMA_CFG_CBUFD_MASK (0xF00000UL) -#define TSW_MM2S_DMA_CFG_CBUFD_SHIFT (20U) -#define TSW_MM2S_DMA_CFG_CBUFD_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_CBUFD_MASK) >> TSW_MM2S_DMA_CFG_CBUFD_SHIFT) - -/* - * ENA64 (RO) - * - * enable support for 64 bit addressing - */ -#define TSW_MM2S_DMA_CFG_ENA64_MASK (0x80000UL) -#define TSW_MM2S_DMA_CFG_ENA64_SHIFT (19U) -#define TSW_MM2S_DMA_CFG_ENA64_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ENA64_MASK) >> TSW_MM2S_DMA_CFG_ENA64_SHIFT) - -/* - * ASIZE (RO) - * - * axi data bus width - */ -#define TSW_MM2S_DMA_CFG_ASIZE_MASK (0x70000UL) -#define TSW_MM2S_DMA_CFG_ASIZE_SHIFT (16U) -#define TSW_MM2S_DMA_CFG_ASIZE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ASIZE_MASK) >> TSW_MM2S_DMA_CFG_ASIZE_SHIFT) - -/* - * VER (RO) - * - * ip version - */ -#define TSW_MM2S_DMA_CFG_VER_MASK (0xFFFFU) -#define TSW_MM2S_DMA_CFG_VER_SHIFT (0U) -#define TSW_MM2S_DMA_CFG_VER_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_VER_MASK) >> TSW_MM2S_DMA_CFG_VER_SHIFT) - -/* Bitfield definition for register: MM2S_ADDRLO */ -/* - * ADDRLO (RW) - * - * axi address - */ -#define TSW_MM2S_ADDRLO_ADDRLO_MASK (0xFFFFFFFFUL) -#define TSW_MM2S_ADDRLO_ADDRLO_SHIFT (0U) -#define TSW_MM2S_ADDRLO_ADDRLO_SET(x) (((uint32_t)(x) << TSW_MM2S_ADDRLO_ADDRLO_SHIFT) & TSW_MM2S_ADDRLO_ADDRLO_MASK) -#define TSW_MM2S_ADDRLO_ADDRLO_GET(x) (((uint32_t)(x) & TSW_MM2S_ADDRLO_ADDRLO_MASK) >> TSW_MM2S_ADDRLO_ADDRLO_SHIFT) - -/* Bitfield definition for register: MM2S_LENGTH */ -/* - * LENGTH (RW) - * - * transfer request length in bytes - */ -#define TSW_MM2S_LENGTH_LENGTH_MASK (0xFFFFU) -#define TSW_MM2S_LENGTH_LENGTH_SHIFT (0U) -#define TSW_MM2S_LENGTH_LENGTH_SET(x) (((uint32_t)(x) << TSW_MM2S_LENGTH_LENGTH_SHIFT) & TSW_MM2S_LENGTH_LENGTH_MASK) -#define TSW_MM2S_LENGTH_LENGTH_GET(x) (((uint32_t)(x) & TSW_MM2S_LENGTH_LENGTH_MASK) >> TSW_MM2S_LENGTH_LENGTH_SHIFT) - -/* Bitfield definition for register: MM2S_CTRL */ -/* - * GO (WO) - * - * commit buffered descriptor to command queue - */ -#define TSW_MM2S_CTRL_GO_MASK (0x80000000UL) -#define TSW_MM2S_CTRL_GO_SHIFT (31U) -#define TSW_MM2S_CTRL_GO_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_GO_SHIFT) & TSW_MM2S_CTRL_GO_MASK) -#define TSW_MM2S_CTRL_GO_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_GO_MASK) >> TSW_MM2S_CTRL_GO_SHIFT) - -/* - * NGENLAST (RW) - * - * no generation of TLAST - */ -#define TSW_MM2S_CTRL_NGENLAST_MASK (0x10U) -#define TSW_MM2S_CTRL_NGENLAST_SHIFT (4U) -#define TSW_MM2S_CTRL_NGENLAST_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_NGENLAST_SHIFT) & TSW_MM2S_CTRL_NGENLAST_MASK) -#define TSW_MM2S_CTRL_NGENLAST_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_NGENLAST_MASK) >> TSW_MM2S_CTRL_NGENLAST_SHIFT) - -/* - * ID (RW) - * - * command id - */ -#define TSW_MM2S_CTRL_ID_MASK (0xFU) -#define TSW_MM2S_CTRL_ID_SHIFT (0U) -#define TSW_MM2S_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_ID_SHIFT) & TSW_MM2S_CTRL_ID_MASK) -#define TSW_MM2S_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_ID_MASK) >> TSW_MM2S_CTRL_ID_SHIFT) - -/* Bitfield definition for register: MM2S_RESP */ -/* - * LAST (RO) - * - * axi-stream with TLAST - */ -#define TSW_MM2S_RESP_LAST_MASK (0x40000000UL) -#define TSW_MM2S_RESP_LAST_SHIFT (30U) -#define TSW_MM2S_RESP_LAST_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_LAST_MASK) >> TSW_MM2S_RESP_LAST_SHIFT) - -/* - * DECERR (RO) - * - * decode error - */ -#define TSW_MM2S_RESP_DECERR_MASK (0x20000000UL) -#define TSW_MM2S_RESP_DECERR_SHIFT (29U) -#define TSW_MM2S_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_DECERR_MASK) >> TSW_MM2S_RESP_DECERR_SHIFT) - -/* - * SLVERR (RO) - * - * slave error - */ -#define TSW_MM2S_RESP_SLVERR_MASK (0x10000000UL) -#define TSW_MM2S_RESP_SLVERR_SHIFT (28U) -#define TSW_MM2S_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_SLVERR_MASK) >> TSW_MM2S_RESP_SLVERR_SHIFT) - -/* - * ID (RO) - * - * command ID feedback - */ -#define TSW_MM2S_RESP_ID_MASK (0xF000000UL) -#define TSW_MM2S_RESP_ID_SHIFT (24U) -#define TSW_MM2S_RESP_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_ID_MASK) >> TSW_MM2S_RESP_ID_SHIFT) - -/* - * LENGTH (RO) - * - * requested length of tansfer in bytes from command - */ -#define TSW_MM2S_RESP_LENGTH_MASK (0xFFFFU) -#define TSW_MM2S_RESP_LENGTH_SHIFT (0U) -#define TSW_MM2S_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_LENGTH_MASK) >> TSW_MM2S_RESP_LENGTH_SHIFT) - -/* Bitfield definition for register: S2MM_DMA_CR */ -/* - * MXLEN (RW) - * - * max axi burst size - */ -#define TSW_S2MM_DMA_CR_MXLEN_MASK (0xFF000000UL) -#define TSW_S2MM_DMA_CR_MXLEN_SHIFT (24U) -#define TSW_S2MM_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_MXLEN_SHIFT) & TSW_S2MM_DMA_CR_MXLEN_MASK) -#define TSW_S2MM_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_MXLEN_MASK) >> TSW_S2MM_DMA_CR_MXLEN_SHIFT) - -/* - * IRQEN (RW) - * - * interrupt request enable - */ -#define TSW_S2MM_DMA_CR_IRQEN_MASK (0x8U) -#define TSW_S2MM_DMA_CR_IRQEN_SHIFT (3U) -#define TSW_S2MM_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_IRQEN_SHIFT) & TSW_S2MM_DMA_CR_IRQEN_MASK) -#define TSW_S2MM_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_IRQEN_MASK) >> TSW_S2MM_DMA_CR_IRQEN_SHIFT) - -/* - * RESET (WO) - * - * do reset when writing 1 - */ -#define TSW_S2MM_DMA_CR_RESET_MASK (0x4U) -#define TSW_S2MM_DMA_CR_RESET_SHIFT (2U) -#define TSW_S2MM_DMA_CR_RESET_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_RESET_SHIFT) & TSW_S2MM_DMA_CR_RESET_MASK) -#define TSW_S2MM_DMA_CR_RESET_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_RESET_MASK) >> TSW_S2MM_DMA_CR_RESET_SHIFT) - -/* - * SOE (RW) - * - * stop on error flag - */ -#define TSW_S2MM_DMA_CR_SOE_MASK (0x2U) -#define TSW_S2MM_DMA_CR_SOE_SHIFT (1U) -#define TSW_S2MM_DMA_CR_SOE_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_SOE_SHIFT) & TSW_S2MM_DMA_CR_SOE_MASK) -#define TSW_S2MM_DMA_CR_SOE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_SOE_MASK) >> TSW_S2MM_DMA_CR_SOE_SHIFT) - -/* - * RUN (RW) - * - * run commands from queue to data mover - */ -#define TSW_S2MM_DMA_CR_RUN_MASK (0x1U) -#define TSW_S2MM_DMA_CR_RUN_SHIFT (0U) -#define TSW_S2MM_DMA_CR_RUN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_RUN_SHIFT) & TSW_S2MM_DMA_CR_RUN_MASK) -#define TSW_S2MM_DMA_CR_RUN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_RUN_MASK) >> TSW_S2MM_DMA_CR_RUN_SHIFT) - -/* Bitfield definition for register: S2MM_DMA_SR */ -/* - * RBUFF (RO) - * - * response buffer full - */ -#define TSW_S2MM_DMA_SR_RBUFF_MASK (0x80U) -#define TSW_S2MM_DMA_SR_RBUFF_SHIFT (7U) -#define TSW_S2MM_DMA_SR_RBUFF_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFF_MASK) >> TSW_S2MM_DMA_SR_RBUFF_SHIFT) - -/* - * RBUFE (RO) - * - * response buffer empty - */ -#define TSW_S2MM_DMA_SR_RBUFE_MASK (0x40U) -#define TSW_S2MM_DMA_SR_RBUFE_SHIFT (6U) -#define TSW_S2MM_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFE_MASK) >> TSW_S2MM_DMA_SR_RBUFE_SHIFT) - -/* - * CBUFF (RO) - * - * command buffer full - */ -#define TSW_S2MM_DMA_SR_CBUFF_MASK (0x20U) -#define TSW_S2MM_DMA_SR_CBUFF_SHIFT (5U) -#define TSW_S2MM_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFF_MASK) >> TSW_S2MM_DMA_SR_CBUFF_SHIFT) - -/* - * CBUFE (RO) - * - * command buffer empty - */ -#define TSW_S2MM_DMA_SR_CBUFE_MASK (0x10U) -#define TSW_S2MM_DMA_SR_CBUFE_SHIFT (4U) -#define TSW_S2MM_DMA_SR_CBUFE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFE_MASK) >> TSW_S2MM_DMA_SR_CBUFE_SHIFT) - -/* - * IRQ (RWC) - * - * interrupt request pending - */ -#define TSW_S2MM_DMA_SR_IRQ_MASK (0x8U) -#define TSW_S2MM_DMA_SR_IRQ_SHIFT (3U) -#define TSW_S2MM_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_SR_IRQ_SHIFT) & TSW_S2MM_DMA_SR_IRQ_MASK) -#define TSW_S2MM_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_IRQ_MASK) >> TSW_S2MM_DMA_SR_IRQ_SHIFT) - -/* - * RSET (RO) - * - * resetting status - */ -#define TSW_S2MM_DMA_SR_RSET_MASK (0x4U) -#define TSW_S2MM_DMA_SR_RSET_SHIFT (2U) -#define TSW_S2MM_DMA_SR_RSET_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RSET_MASK) >> TSW_S2MM_DMA_SR_RSET_SHIFT) - -/* - * BUSY (RO) - * - * busy, issued command and outstanding response - */ -#define TSW_S2MM_DMA_SR_BUSY_MASK (0x2U) -#define TSW_S2MM_DMA_SR_BUSY_SHIFT (1U) -#define TSW_S2MM_DMA_SR_BUSY_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_BUSY_MASK) >> TSW_S2MM_DMA_SR_BUSY_SHIFT) - -/* - * STOP (RO) - * - * s2mm is stopped - */ -#define TSW_S2MM_DMA_SR_STOP_MASK (0x1U) -#define TSW_S2MM_DMA_SR_STOP_SHIFT (0U) -#define TSW_S2MM_DMA_SR_STOP_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_STOP_MASK) >> TSW_S2MM_DMA_SR_STOP_SHIFT) - -/* Bitfield definition for register: S2MM_DMA_FILL */ -/* - * RFILL (RO) - * - * response buffer fill level - */ -#define TSW_S2MM_DMA_FILL_RFILL_MASK (0xFFFF0000UL) -#define TSW_S2MM_DMA_FILL_RFILL_SHIFT (16U) -#define TSW_S2MM_DMA_FILL_RFILL_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_FILL_RFILL_MASK) >> TSW_S2MM_DMA_FILL_RFILL_SHIFT) - -/* - * CFILL (RO) - * - * command buffer fill level - */ -#define TSW_S2MM_DMA_FILL_CFILL_MASK (0xFFFFU) -#define TSW_S2MM_DMA_FILL_CFILL_SHIFT (0U) -#define TSW_S2MM_DMA_FILL_CFILL_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_FILL_CFILL_MASK) >> TSW_S2MM_DMA_FILL_CFILL_SHIFT) - -/* Bitfield definition for register: S2MM_DMA_CFG */ -/* - * DBUFD (RO) - * - * data buffer depth - */ -#define TSW_S2MM_DMA_CFG_DBUFD_MASK (0xF000000UL) -#define TSW_S2MM_DMA_CFG_DBUFD_SHIFT (24U) -#define TSW_S2MM_DMA_CFG_DBUFD_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_DBUFD_MASK) >> TSW_S2MM_DMA_CFG_DBUFD_SHIFT) - -/* - * CBUFD (RO) - * - * command buffer depth - */ -#define TSW_S2MM_DMA_CFG_CBUFD_MASK (0xF00000UL) -#define TSW_S2MM_DMA_CFG_CBUFD_SHIFT (20U) -#define TSW_S2MM_DMA_CFG_CBUFD_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_CBUFD_MASK) >> TSW_S2MM_DMA_CFG_CBUFD_SHIFT) - -/* - * ENA64 (RO) - * - * enabled support for 64 bit - */ -#define TSW_S2MM_DMA_CFG_ENA64_MASK (0x80000UL) -#define TSW_S2MM_DMA_CFG_ENA64_SHIFT (19U) -#define TSW_S2MM_DMA_CFG_ENA64_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ENA64_MASK) >> TSW_S2MM_DMA_CFG_ENA64_SHIFT) - -/* - * ASIZE (RO) - * - * axi data bus width - */ -#define TSW_S2MM_DMA_CFG_ASIZE_MASK (0x70000UL) -#define TSW_S2MM_DMA_CFG_ASIZE_SHIFT (16U) -#define TSW_S2MM_DMA_CFG_ASIZE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ASIZE_MASK) >> TSW_S2MM_DMA_CFG_ASIZE_SHIFT) - -/* - * VER (RO) - * - * IP version - */ -#define TSW_S2MM_DMA_CFG_VER_MASK (0xFFFFU) -#define TSW_S2MM_DMA_CFG_VER_SHIFT (0U) -#define TSW_S2MM_DMA_CFG_VER_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_VER_MASK) >> TSW_S2MM_DMA_CFG_VER_SHIFT) - -/* Bitfield definition for register: S2MM_ADDRLO */ -/* - * ADDRLO (RW) - * - * axi address - */ -#define TSW_S2MM_ADDRLO_ADDRLO_MASK (0xFFFFFFFFUL) -#define TSW_S2MM_ADDRLO_ADDRLO_SHIFT (0U) -#define TSW_S2MM_ADDRLO_ADDRLO_SET(x) (((uint32_t)(x) << TSW_S2MM_ADDRLO_ADDRLO_SHIFT) & TSW_S2MM_ADDRLO_ADDRLO_MASK) -#define TSW_S2MM_ADDRLO_ADDRLO_GET(x) (((uint32_t)(x) & TSW_S2MM_ADDRLO_ADDRLO_MASK) >> TSW_S2MM_ADDRLO_ADDRLO_SHIFT) - -/* Bitfield definition for register: S2MM_LENGTH */ -/* - * LENGTH (RW) - * - * transfer request length in bytes - */ -#define TSW_S2MM_LENGTH_LENGTH_MASK (0xFFFFU) -#define TSW_S2MM_LENGTH_LENGTH_SHIFT (0U) -#define TSW_S2MM_LENGTH_LENGTH_SET(x) (((uint32_t)(x) << TSW_S2MM_LENGTH_LENGTH_SHIFT) & TSW_S2MM_LENGTH_LENGTH_MASK) -#define TSW_S2MM_LENGTH_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_LENGTH_LENGTH_MASK) >> TSW_S2MM_LENGTH_LENGTH_SHIFT) - -/* Bitfield definition for register: S2MM_CTRL */ -/* - * GO (WO) - * - * commit buffered descriptor to command queue - */ -#define TSW_S2MM_CTRL_GO_MASK (0x80000000UL) -#define TSW_S2MM_CTRL_GO_SHIFT (31U) -#define TSW_S2MM_CTRL_GO_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_GO_SHIFT) & TSW_S2MM_CTRL_GO_MASK) -#define TSW_S2MM_CTRL_GO_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_GO_MASK) >> TSW_S2MM_CTRL_GO_SHIFT) - -/* - * ID (RW) - * - * command id - */ -#define TSW_S2MM_CTRL_ID_MASK (0xFU) -#define TSW_S2MM_CTRL_ID_SHIFT (0U) -#define TSW_S2MM_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_ID_SHIFT) & TSW_S2MM_CTRL_ID_MASK) -#define TSW_S2MM_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_ID_MASK) >> TSW_S2MM_CTRL_ID_SHIFT) - -/* Bitfield definition for register: S2MM_RESP */ -/* - * LAST (RO) - * - * axi-stream with last - */ -#define TSW_S2MM_RESP_LAST_MASK (0x40000000UL) -#define TSW_S2MM_RESP_LAST_SHIFT (30U) -#define TSW_S2MM_RESP_LAST_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LAST_MASK) >> TSW_S2MM_RESP_LAST_SHIFT) - -/* - * DECERR (RO) - * - * decode error - */ -#define TSW_S2MM_RESP_DECERR_MASK (0x20000000UL) -#define TSW_S2MM_RESP_DECERR_SHIFT (29U) -#define TSW_S2MM_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_DECERR_MASK) >> TSW_S2MM_RESP_DECERR_SHIFT) - -/* - * SLVERR (RO) - * - * slave error - */ -#define TSW_S2MM_RESP_SLVERR_MASK (0x10000000UL) -#define TSW_S2MM_RESP_SLVERR_SHIFT (28U) -#define TSW_S2MM_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_SLVERR_MASK) >> TSW_S2MM_RESP_SLVERR_SHIFT) - -/* - * ID (RO) - * - * command ID feedback - */ -#define TSW_S2MM_RESP_ID_MASK (0xF000000UL) -#define TSW_S2MM_RESP_ID_SHIFT (24U) -#define TSW_S2MM_RESP_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_ID_MASK) >> TSW_S2MM_RESP_ID_SHIFT) - -/* - * LENGTH (RO) - * - * received packet size when terminated by TLAST - */ -#define TSW_S2MM_RESP_LENGTH_MASK (0xFFFFU) -#define TSW_S2MM_RESP_LENGTH_SHIFT (0U) -#define TSW_S2MM_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LENGTH_MASK) >> TSW_S2MM_RESP_LENGTH_SHIFT) - -/* Bitfield definition for register: PTP_EVT_TS_CTL */ -/* - * ATSEN (RW) - * - * auxiliay snapshot enable - */ -#define TSW_PTP_EVT_TS_CTL_ATSEN_MASK (0x1E000000UL) -#define TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT (25U) -#define TSW_PTP_EVT_TS_CTL_ATSEN_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK) -#define TSW_PTP_EVT_TS_CTL_ATSEN_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK) >> TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT) - -/* - * ATSFC (W1C) - * - * auxiliary snapshot fifo clear - */ -#define TSW_PTP_EVT_TS_CTL_ATSFC_MASK (0x1000000UL) -#define TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT (24U) -#define TSW_PTP_EVT_TS_CTL_ATSFC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK) -#define TSW_PTP_EVT_TS_CTL_ATSFC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK) >> TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT) - -/* - * TSTIG (RW) - * - * timestamp interrupt trigger enable - */ -#define TSW_PTP_EVT_TS_CTL_TSTIG_MASK (0x10U) -#define TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT (4U) -#define TSW_PTP_EVT_TS_CTL_TSTIG_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK) -#define TSW_PTP_EVT_TS_CTL_TSTIG_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK) >> TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS_TOD_SEC */ -/* - * PPS_TOD_SEC (RO) - * - * pps tod seconds - */ -#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT (0U) -#define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK) >> TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS_TOD_NS */ -/* - * PPS_TOD_NS (RO) - * - * pps tod sub seconds - */ -#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK (0x3FFFFFFFUL) -#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT (0U) -#define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK) >> TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_SEC0 */ -/* - * SCP_SEC (RW) - * - * target time seconds - */ -#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT (0U) -#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK) -#define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_NS0 */ -/* - * SCP_NS (RW) - * - * target time sub seconds - */ -#define TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK (0x3FFFFFFFUL) -#define TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT (0U) -#define TSW_PTP_EVT_SCP_NS0_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK) -#define TSW_PTP_EVT_SCP_NS0_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT) - -/* Bitfield definition for register: PTP_EVT_TMR_STS */ -/* - * RD_CNT (RO) - * - * fifo valid count - */ -#define TSW_PTP_EVT_TMR_STS_RD_CNT_MASK (0x3E000000UL) -#define TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT (25U) -#define TSW_PTP_EVT_TMR_STS_RD_CNT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_RD_CNT_MASK) >> TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT) - -/* - * ATSSTM (RO) - * - * auxiliary fifo full error - */ -#define TSW_PTP_EVT_TMR_STS_ATSSTM_MASK (0x1000000UL) -#define TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT (24U) -#define TSW_PTP_EVT_TMR_STS_ATSSTM_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATSSTM_MASK) >> TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT) - -/* - * ATPORT (RO) - * - * auxiliary port - */ -#define TSW_PTP_EVT_TMR_STS_ATPORT_MASK (0xF0000UL) -#define TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT (16U) -#define TSW_PTP_EVT_TMR_STS_ATPORT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATPORT_MASK) >> TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT) - -/* - * PPS_TOD_INTR (RC) - * - * pps tod intrrupt - */ -#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK (0x400U) -#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT (10U) -#define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT) - -/* - * TARGET_TIME3_CFG_ERR (RO) - * - * target time3 configure error - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK (0x200U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT (9U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT) - -/* - * TARGET_TIME3_REACH_INTR (RC) - * - * target time3 reached - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK (0x100U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT (8U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT) - -/* - * TARGET_TIME2_CFG_ERR (RO) - * - * target time2 configure error - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK (0x80U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT (7U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT) - -/* - * TARGET_TIME2_REACH_INTR (RC) - * - * target time2 reached - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK (0x40U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT (6U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT) - -/* - * TARGET_TIME1_CFG_ERR (RO) - * - * target time1 configure error - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK (0x20U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT (5U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT) - -/* - * TARGET_TIME1_REACH_INTR (RC) - * - * target time1 reached - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK (0x10U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT (4U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT) - -/* - * TARGET_TIME0_CFG_ERR (RO) - * - * target time0 configure error - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK (0x8U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT (3U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT) - -/* - * PTP_FIFO_WR_INTR (RC) - * - * auxiliary timestamp trigger snapshot - */ -#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK (0x4U) -#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT (2U) -#define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT) - -/* - * TARGET_TIME0_REACH_INTR (RC) - * - * target time0 reached - */ -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK (0x2U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT (1U) -#define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS_CMD */ -/* - * PPS_MODE3 (RW) - * - * Target Time Register Mode for PPS3 Output - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK (0x60000000UL) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT (29U) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT) - -/* - * PPS_CMD3 (RW) - * - * pps3 command - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK (0x7000000UL) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT (24U) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT) - -/* - * PPS_MODE2 (RW) - * - * Target Time Register Mode for PPS2 Output - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK (0x600000UL) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT (21U) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT) - -/* - * PPS_CMD2 (RW) - * - * pps2 command - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK (0x70000UL) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT (16U) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT) - -/* - * PPS_MODE1 (RW) - * - * Target Time Register Mode for PPS1 Output - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK (0x6000U) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT (13U) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT) - -/* - * PPS_CMD1 (RW) - * - * pps1 command - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK (0x700U) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT (8U) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT) - -/* - * PPS_MODE0 (RW) - * - * Target Time Register Mode for PPS0 Output - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK (0x60U) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT (5U) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT) - -/* - * PPS_EN0 (RW) - * - * flexible PPS0 output mode enable - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK (0x10U) -#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT (4U) -#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_EN0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT) - -/* - * PPS_CMD0 (RW) - * - * pps0 command - */ -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK (0xFU) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT (0U) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK) -#define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT) - -/* Bitfield definition for register: PTP_EVT_ATSLO */ -/* - * STSLO (RO) - * - * auxiliary fifo read sub seconds info - */ -#define TSW_PTP_EVT_ATSLO_STSLO_MASK (0x7FFFFFFFUL) -#define TSW_PTP_EVT_ATSLO_STSLO_SHIFT (0U) -#define TSW_PTP_EVT_ATSLO_STSLO_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_ATSLO_STSLO_MASK) >> TSW_PTP_EVT_ATSLO_STSLO_SHIFT) - -/* Bitfield definition for register: PTP_EVT_ATSHI */ -/* - * STSHI (RO) - * - * auxiliary fifo read seconds info - */ -#define TSW_PTP_EVT_ATSHI_STSHI_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_ATSHI_STSHI_SHIFT (0U) -#define TSW_PTP_EVT_ATSHI_STSHI_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_ATSHI_STSHI_MASK) >> TSW_PTP_EVT_ATSHI_STSHI_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS0_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS0 output signal interval - */ -#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT (0U) -#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK) -#define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS0_WIDTH */ -/* - * PPS_WIDTH (RW) - * - * pps0 output signal width - */ -#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT (0U) -#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK) -#define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_SEC1 */ -/* - * SCP_SEC (RW) - * - * target time seconds - */ -#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT (0U) -#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK) -#define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_NS1 */ -/* - * SCP_NS (RW) - * - * target time sub seconds - */ -#define TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK (0x3FFFFFFFUL) -#define TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT (0U) -#define TSW_PTP_EVT_SCP_NS1_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK) -#define TSW_PTP_EVT_SCP_NS1_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS1_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS1 output signal interval - */ -#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT (0U) -#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK) -#define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS1_WIDTH */ -/* - * PPS_WIDTH (RW) - * - * pps1 output signal width - */ -#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT (0U) -#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK) -#define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_SEC2 */ -/* - * SCP_SEC (RW) - * - * target time seconds - */ -#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT (0U) -#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK) -#define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_NS2 */ -/* - * SCP_NS (RW) - * - * target time sub seconds - */ -#define TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK (0x3FFFFFFFUL) -#define TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT (0U) -#define TSW_PTP_EVT_SCP_NS2_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK) -#define TSW_PTP_EVT_SCP_NS2_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS2_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS2 output signal interval - */ -#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT (0U) -#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK) -#define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS2_WIDTH */ -/* - * PPS_WIDTH (RW) - * - * pps2 output signal width - */ -#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT (0U) -#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK) -#define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_SEC3 */ -/* - * SCP_SEC (RW) - * - * target time seconds - */ -#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT (0U) -#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK) -#define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT) - -/* Bitfield definition for register: PTP_EVT_SCP_NS3 */ -/* - * SCP_NS (RW) - * - * target time sub seconds - */ -#define TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK (0x3FFFFFFFUL) -#define TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT (0U) -#define TSW_PTP_EVT_SCP_NS3_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK) -#define TSW_PTP_EVT_SCP_NS3_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS3_INTERVAL */ -/* - * PPSINT (RW) - * - * PPS3 output signal interval - */ -#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT (0U) -#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK) -#define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS3_WIDTH */ -/* - * PPS_WIDTH (RW) - * - * pps3 output signal width - */ -#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL) -#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT (0U) -#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK) -#define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS_CTRL0 */ -/* - * PPS_TOD_INTR_MSK (RW) - * - * pps tod interrupt enable - */ -#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK (0x8U) -#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT (3U) -#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK) -#define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT) - -/* - * TARGET_RAC_INTR_MSK (RW) - * - * target timmer interrupt mask - */ -#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK (0x4U) -#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT (2U) -#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK) -#define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT) - -/* - * FIFO_WR_INTR_MSK (RW) - * - * auxiliary snapshot fifo write interrupt enable - */ -#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK (0x2U) -#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT (1U) -#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK) -#define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT) - -/* - * TIME_SEL (RW) - * - * timer selection - */ -#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK (0x1U) -#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT (0U) -#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK) -#define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT) - -/* Bitfield definition for register: PTP_EVT_PPS_SEL */ -/* - * PPS3_SEL (RW) - * - * pps selection for pps3 - */ -#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK (0x1F000000UL) -#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT (24U) -#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK) -#define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT) - -/* - * PPS2_SEL (RW) - * - * pps selection for pps2 - */ -#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK (0x1F0000UL) -#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT (16U) -#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK) -#define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT) - -/* - * PPS1_SEL (RW) - * - * pps selection for pps1 - */ -#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK (0x1F00U) -#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT (8U) -#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK) -#define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT) - -/* - * PPS0_SEL (RW) - * - * pps selection for pps0 - */ -#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK (0x1FU) -#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT (0U) -#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK) -#define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT) - -/* Bitfield definition for register: SOFT_RST_CTRL */ -/* - * TSN_CORE_RST (RW) - * - * tsn core reset control - */ -#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK (0x800U) -#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT (11U) -#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK) -#define TSW_SOFT_RST_CTRL_TSN_CORE_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK) >> TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT) - -/* - * PTP_EVT_RST (RW) - * - * ptp event module reset control - */ -#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK (0x400U) -#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT (10U) -#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK) -#define TSW_SOFT_RST_CTRL_PTP_EVT_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK) >> TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT) - -/* - * DMA0_RST (RW) - * - * dma0 reset control - */ -#define TSW_SOFT_RST_CTRL_DMA0_RST_MASK (0x100U) -#define TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT (8U) -#define TSW_SOFT_RST_CTRL_DMA0_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK) -#define TSW_SOFT_RST_CTRL_DMA0_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK) >> TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT) - -/* - * PORT3_RX_RST (RW) - * - * port3 rx reset control - */ -#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK (0x20U) -#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT (5U) -#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK) -#define TSW_SOFT_RST_CTRL_PORT3_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT) - -/* - * PORT3_TX_RST (RW) - * - * port3 tx reset control - */ -#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK (0x10U) -#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT (4U) -#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK) -#define TSW_SOFT_RST_CTRL_PORT3_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT) - -/* - * PORT2_RX_RST (RW) - * - * port2 rx reset control - */ -#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK (0x8U) -#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT (3U) -#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK) -#define TSW_SOFT_RST_CTRL_PORT2_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT) - -/* - * PORT2_TX_RST (RW) - * - * port2 tx reset control - */ -#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK (0x4U) -#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT (2U) -#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK) -#define TSW_SOFT_RST_CTRL_PORT2_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT) - -/* - * PORT1_RX_RST (RW) - * - * port1 rx reset control - */ -#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK (0x2U) -#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT (1U) -#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK) -#define TSW_SOFT_RST_CTRL_PORT1_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT) - -/* - * PORT1_TX_RST (RW) - * - * port1 tx reset control - */ -#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK (0x1U) -#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT (0U) -#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK) -#define TSW_SOFT_RST_CTRL_PORT1_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT) - -/* Bitfield definition for register: CPU_PORT_PORT_MAIN_TAGGING */ -/* - * FORCE (R/W) - * - * The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports - */ -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK (0x20000UL) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT (17U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT) - -/* - * ACCESS (R/W) - * - * Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged - */ -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK (0x10000UL) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT (16U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT) - -/* - * PCP (R/W) - * - * VLAN-TCI: Priority Code Point, used when tagged. - */ -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK (0xE000U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT (13U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT) - -/* - * DEI (R/W) - * - * VLAN-TCI: Drop Eligible Indicator, used when tagged. - */ -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK (0x1000U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT (12U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT) - -/* - * PVID (R/W) - * - * Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1. - */ -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK (0xFFFU) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT (0U) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK) -#define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT) - -/* Bitfield definition for register: CPU_PORT_PORT_MAIN_ENNABLE */ -/* - * EN_SF (R/W) - * - * only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption - */ -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK (0x2U) -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT (1U) -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK) -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT) - -/* - * EN_QCI (R/W) - * - * if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption. - */ -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK (0x1U) -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT (0U) -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK) -#define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_ESELECT */ -/* - * ESEL (RO) - * - * Select entry. Selected entry mapped to 0x40 – 0x5C. - */ -#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK (0xFFU) -#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_CONTROL */ -/* - * SID (R/W) - * - * Stream ID – inserted to header on match - */ -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK (0xFF00U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT (8U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT) - -/* - * SEQGEN (R/W) - * - * Sequence number generation enable - */ -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK (0x80U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT (7U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT) - -/* - * ACTCTL (R/W) - * - * Active Destination MAC – control. See Table 6-6. - */ -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK (0x30U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT (4U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT) - -/* - * SMAC (R/W) - * - * 0: Lookup by Destination MAC 1: Lookup by Source MAC - */ -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK (0x8U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT (3U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT) - -/* - * MODE (R/W) - * - * Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged - */ -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK (0x6U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT (1U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT) - -/* - * EN (R/W) - * - * Enable entry - */ -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK (0x1U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_SEQNO */ -/* - * SEQNO (R/WC) - * - * Sequence number – next number when generating,any write access to clear. - */ -#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK (0xFFFFU) -#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MATCHCNT */ -/* - * MATCH (R/WC) - * - * Entry match counter – any write access to clear. - */ -#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MACLO */ -/* - * MACL (R/WC) - * - * MAC-Address [31:0] used by lookup. - */ -#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MACHI */ -/* - * VID (R/W) - * - * VLAN ID used by lookup. - */ -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK (0xFFF0000UL) -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT (16U) -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT) - -/* - * MATCH (R/W) - * - * MAC-Address [47:31] used by lookup. - */ -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK (0xFFFFU) -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_STMID_AMACHI */ -/* - * APCP (R/W) - * - * Active Destination MAC, PCP - */ -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK (0xF0000000UL) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT (28U) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT) - -/* - * AVID (R/W) - * - * Active Destination MAC, VLAN ID - */ -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK (0xFFF0000UL) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT (16U) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT) - -/* - * AMACH (R/W) - * - * Active Destination MAC, MAC-Address [47:32] - */ -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK (0xFFFFU) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK) -#define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_CONTROL */ -/* - * LATER (R/WC) - * - * Latent error flag – write 1 to clear - */ -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK (0x2U) -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT (1U) -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT) - -/* - * RTENC (R/W) - * - * R-TAG encoding enable. - */ -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK (0x1U) -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_SIDSEL */ -/* - * SID (R/W) - * - * Stream ID selection for host access to IRFUNC and SRFUNC. - */ -#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK (0xFFU) -#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_IRFUNC */ -/* - * FEN (R/W) - * - * Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - */ -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK (0x80000000UL) -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT (31U) -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT) - -/* - * FIDX (R/W) - * - */ -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK (0xFFU) -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_SRFUNC */ -/* - * FEN (R/W) - * - * Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - */ -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK (0x80000000UL) -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT (31U) -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT) - -/* - * FIDX (R/W) - * - */ -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK (0xFFU) -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_FSELECT */ -/* - * FIDX (R/W) - * - * Recovery function selection for host access at offset 0x140+ - */ -#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK (0xFFU) -#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_FCTRL */ -/* - * FRSET (WO) - * - * Reset recovery function – self-resetting to 0 - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK (0x80000000UL) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT (31U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT) - -/* - * PATHS (R/W) - * - * Number of paths (used by latent error detection) - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK (0xFF0000UL) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT (16U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT) - -/* - * HLEN (R/W) - * - * History length (used by Vector recovery algorithm) - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK (0x1F00U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT (8U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT) - -/* - * ALGO (R/W) - * - * Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK (0x10U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT (4U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT) - -/* - * LATEN (R/W) - * - * Latent error detection enable - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK (0x8U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT (3U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT) - -/* - * IND (R/W) - * - * Individual function (802.1CB 10.4.1.10) - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK (0x4U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT (2U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT) - -/* - * TNS (R/W) - * - * TakeNoSequence (802.1CB 10.4.1.9) - */ -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK (0x2U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT (1U) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_RESETMSEC */ -/* - * FSRMS (R/W) - * - * frerSeqRcvyResetMSec (802.1CB 10.4.1.7) - */ -#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK (0xFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATRSPERIOD */ -/* - * FLATR (R/W) - * - * frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4) - */ -#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK (0xFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATTESTPERIOD */ -/* - * FLATT (R/W) - * - * frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2) - */ -#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK (0xFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATERRDIFFALW */ -/* - * FDIFF (R/W) - * - * frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1) - */ -#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) - -/* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATERRCNT */ -/* - * LATERR (R/WC) - * - * Counter – latent error detect. Write any value to clear - */ -#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT (0U) -#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK) -#define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT) - -/* Bitfield definition for register array: EGFRCNT */ -/* - * VALUE (RO) - * - * Frame counters - */ -#define TSW_EGFRCNT_VALUE_MASK (0xFFFFFFFFUL) -#define TSW_EGFRCNT_VALUE_SHIFT (0U) -#define TSW_EGFRCNT_VALUE_GET(x) (((uint32_t)(x) & TSW_EGFRCNT_VALUE_MASK) >> TSW_EGFRCNT_VALUE_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE */ -/* - * FDMEM_CNT_BYTE (RO) - * - * Number of bytes stored in frame drop FIFO - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS */ -/* - * WAIT_FOR_LU (RO) - * - * FD FIFO waits for LookUp information. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK (0x800U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT (11U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT) - -/* - * WAIT_FOR_FRAME (RO) - * - * FD FIFO waits for more frame data. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK (0x400U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT (10U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT) - -/* - * BUSY (RO) - * - * FD FIFO processes data. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK (0x200U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT (9U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT) - -/* - * READY (RO) - * - * FD FIFO ready to work or working. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK (0x100U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT (8U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT) - -/* - * FULL (RO) - * - * FD FIFO full - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK (0x8U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT (3U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT) - -/* - * AMST_FULL (RO) - * - * FD FIFO almost full. Less than 1600 Byte left. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK (0x4U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT (2U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT) - -/* - * AMST_EMPTY (RO) - * - * FD FIFO almost empty. Few bytes in FIFO. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK (0x2U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT (1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO empty - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG */ -/* - * LU_DESC_ERR (R/W1C) - * - * LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK (0x40U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT (6U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT) - -/* - * WRFAIL_FULL (R/W1C) - * - * Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK (0x20U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT (5U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT) - -/* - * DROP_NRDY (R/W1C) - * - * Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK (0x10U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT (4U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT) - -/* - * DROP_FULL_DESC (R/W1C) - * - * Frame was dropped because the internal descriptor FIFO is full. Full by too many frames. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK (0x8U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT (3U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT) - -/* - * DROP_FULL_MEM (R/W1C) - * - * Frame was dropped because the FIFO is full. Full by too much data. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK (0x4U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT (2U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT) - -/* - * DESC_NRDY_ERR (R/W1C) - * - * FD FIFO failure. Descriptor not received correctly. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK (0x2U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT (1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) - -/* - * DESC_SEQ_ERR (R/W1C) - * - * FD FIFO failure. Internal controller lost synchronization. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG */ -/* - * IE (R/W) - * - * Interrupt enable of ERROR_FLAG. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK (0x7FU) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG */ -/* - * NOCUT_ERROR (R/W) - * - * FD_FIFO does not shorten frames which contain an error. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG */ -/* - * DROP_DEST (R/W) - * - * Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0]. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK (0xFFFF0000UL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT (16U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT) - -/* - * MIRROR_TX_EN (R/W) - * - * Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK (0x200U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT (9U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT) - -/* - * MIRROR_RX_EN (R/W) - * - * Incoming frames of this port will be mirrored to the given destination in MIRROR_RX. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK (0x100U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT (8U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT) - -/* - * CT_FPE_OVRD (R/W) - * - * If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK (0x40U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT (6U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT) - -/* - * DISABLE (R/W) - * - * Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK (0x20U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT (5U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT) - -/* - * DROP_ALL (R/W) - * - * Route all frames to DROP_DEST. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK (0x10U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT (4U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT) - -/* - * ERROR_TO_CPU (R/W) - * - * Send error frames to CPU. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK (0x8U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT (3U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT) - -/* - * MIRROR_TO_CPU (R/W) - * - * Duplicate frames to CPU. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK (0x4U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT (2U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) - -/* - * NODROP_ERROR (R/W) - * - * Do not drop frame errors. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK (0x2U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT (1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT) - -/* - * MODE_STORE_FW (R/W) - * - * Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_RESET */ -/* - * SOFTRS (W) - * - * Write 1 to reset FD controller and memory pointers. Register Map content remains untouched - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_PARAM */ -/* - * LU_FIFO_DEPTH (RO) - * - * Number of MAC lookup descriptors the FIFO can store. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK (0xFF000000UL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT (24U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT) - -/* - * FD_DESC_FIFO_DESC (RO) - * - * Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK (0xFF0000UL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT (16U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT) - -/* - * FD_FIFO_DESC (RO) - * - * Number of words (4byte) the Frame Drop FIFO can store. - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK (0xFFFFU) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_STRFWD */ -/* - * PORT (R/W) - * - * If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK (0x1FFFFFFUL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK */ -/* - * PORT (R/W) - * - * Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports). - * bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK (0x1FFFFFFUL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_MIRROR */ -/* - * PORT (R/W) - * - * Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port. - * bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK (0x1FFFFFFUL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX */ -/* - * PORT (R/W) - * - * Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic. - * bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK (0x1FFFFFFUL) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK) -#define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_ESELECT */ -/* - * ESEL (RO) - * - * Select entry. Selected entry mapped to 0x40 – 0x5C. - */ -#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK (0xFFU) -#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_CONTROL */ -/* - * SID (RW) - * - * Stream ID – inserted to header on match - */ -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK (0xFF00U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT (8U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT) - -/* - * SEQGEN (RW) - * - * Sequence number generation enable - */ -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK (0x80U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT (7U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT) - -/* - * ACTCTL (RW) - * - * Active Destination MAC – control. See Table 6-6. - */ -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK (0x30U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT (4U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT) - -/* - * SMAC (RW) - * - * 0: Lookup by Destination MAC 1: Lookup by Source MAC - */ -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK (0x8U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT (3U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT) - -/* - * MODE (RW) - * - * Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged - */ -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK (0x6U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT (1U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT) - -/* - * EN (RW) - * - * Enable entry - */ -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_SEQNO */ -/* - * SEQNO (RWC) - * - * Sequence number – next number when generating,any write access to clear. - */ -#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK (0xFFFFU) -#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MATCHCNT */ -/* - * MATCH (RWC) - * - * Entry match counter – any write access to clear. - */ -#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MACLO */ -/* - * MACL (RWC) - * - * MAC-Address [31:0] used by lookup. - */ -#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MACHI */ -/* - * VID (RW) - * - * VLAN ID used by lookup. - */ -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK (0xFFF0000UL) -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT (16U) -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT) - -/* - * MATCH (RW) - * - * MAC-Address [47:31] used by lookup. - */ -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK (0xFFFFU) -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_STMID_AMACHI */ -/* - * APCP (RW) - * - * Active Destination MAC, PCP - */ -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK (0xF0000000UL) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT (28U) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT) - -/* - * AVID (RW) - * - * Active Destination MAC, VLAN ID - */ -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK (0xFFF0000UL) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT (16U) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT) - -/* - * AMACH (RW) - * - * Active Destination MAC, MAC-Address [47:32] - */ -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK (0xFFFFU) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK) -#define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_CONTROL */ -/* - * LATER (RWC) - * - * Latent error flag – write 1 to clear - */ -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK (0x2U) -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT (1U) -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT) - -/* - * RTENC (RW) - * - * R-TAG encoding enable. - */ -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK (0x1U) -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_SIDSEL */ -/* - * SID (RW) - * - * Stream ID selection for host access to IRFUNC and SRFUNC. - */ -#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK (0xFFU) -#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_IRFUNC */ -/* - * FEN (RW) - * - * Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - */ -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK (0x80000000UL) -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT (31U) -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT) - -/* - * FIDX (RW) - * - */ -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK (0xFFU) -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_SRFUNC */ -/* - * FEN (RW) - * - * Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0. - */ -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK (0x80000000UL) -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT (31U) -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT) - -/* - * FIDX (RW) - * - */ -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK (0xFFU) -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_FSELECT */ -/* - * FIDX (RW) - * - * Recovery function selection for host access at offset 0x140+ - */ -#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK (0xFFU) -#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_FCTRL */ -/* - * FRSET (WO) - * - * Reset recovery function – self-resetting to 0 - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK (0x80000000UL) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT (31U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT) - -/* - * PATHS (RW) - * - * Number of paths (used by latent error detection) - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK (0xFF0000UL) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT (16U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT) - -/* - * HLEN (RW) - * - * History length (used by Vector recovery algorithm) - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK (0x1F00U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT (8U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT) - -/* - * ALGO (RW) - * - * Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK (0x10U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT (4U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT) - -/* - * LATEN (RW) - * - * Latent error detection enable - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK (0x8U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT (3U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT) - -/* - * IND (RW) - * - * Individual function (802.1CB 10.4.1.10) - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK (0x4U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT (2U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT) - -/* - * TNS (RW) - * - * TakeNoSequence (802.1CB 10.4.1.9) - */ -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK (0x2U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT (1U) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_RESETMSEC */ -/* - * FSRMS (RW) - * - * frerSeqRcvyResetMSec (802.1CB 10.4.1.7) - */ -#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK (0xFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATRSPERIOD */ -/* - * FLATR (RW) - * - * frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4) - */ -#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK (0xFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATTESTPERIOD */ -/* - * FLATT (RW) - * - * frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2) - */ -#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK (0xFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATERRDIFFALW */ -/* - * FDIFF (RW) - * - * frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1) - */ -#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) - -/* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATERRCNT */ -/* - * LATERR (RWC) - * - * Counter – latent error detect. Write any value to clear - */ -#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT (0U) -#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK) -#define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT) - -/* Bitfield definition for register array: IGFRCNT */ -/* - * VALUE (RO) - * - * Frame counters - */ -#define TSW_IGFRCNT_VALUE_MASK (0xFFFFFFFFUL) -#define TSW_IGFRCNT_VALUE_SHIFT (0U) -#define TSW_IGFRCNT_VALUE_GET(x) (((uint32_t)(x) & TSW_IGFRCNT_VALUE_MASK) >> TSW_IGFRCNT_VALUE_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_CTRL */ -/* - * EN (R/W) - * - * Enables counter. If deasserted the counter process stops and the counters hold their value. - */ -#define TSW_CPU_PORT_MONITOR_CTRL_EN_MASK (0x1U) -#define TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK) -#define TSW_CPU_PORT_MONITOR_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK) >> TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RESET */ -/* - * RSRX (WO) - * - * Write '1' to reset all RX counters. - */ -#define TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK (0x4U) -#define TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT (2U) -#define TSW_CPU_PORT_MONITOR_RESET_RSRX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK) -#define TSW_CPU_PORT_MONITOR_RESET_RSRX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT) - -/* - * RSTX (WO) - * - * Write '1' to reset all TX counters - */ -#define TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK (0x2U) -#define TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT (1U) -#define TSW_CPU_PORT_MONITOR_RESET_RSTX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK) -#define TSW_CPU_PORT_MONITOR_RESET_RSTX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT) - -/* - * RSALL (WO) - * - * Write '1' to reset all TX&RX counters. - */ -#define TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK (0x1U) -#define TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RESET_RSALL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK) -#define TSW_CPU_PORT_MONITOR_RESET_RSALL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_PARAM */ -/* - * RX_CNT_EN_VEC (RO) - * - * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - */ -#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK (0xFFFF0000UL) -#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT (16U) -#define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT) - -/* - * TX_CNT_EN_VEC (RO) - * - * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - */ -#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK (0xFF00U) -#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT (8U) -#define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT) - -/* - * CNTW (RO) - * - * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter - * are available. - */ -#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK (0x7FU) -#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_PARAM_CNTW_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD */ -/* - * TX_FGOOD (RO) - * - * Good transmitted Frames to TX TSN-EP. - */ -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR */ -/* - * TX_FERROR (RO) - * - * Transmitted Frames with Error to TX TSN-EP. - */ -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL */ -/* - * TX_DROP_OVFL (RO) - * - * Dropped frames by full queue of TSN-EP. - */ -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD */ -/* - * RX_FGOOD (RO) - * - * Good received frame by ingress buffer. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR */ -/* - * RX_FERROR (RO) - * - * Bad received frame by ingress buffer. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN */ -/* - * RX_KNOWN (RO) - * - * Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN */ -/* - * RX_UNKNOWN (RO) - * - * Number of frames passed ingress without hit by MAC table. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_UC */ -/* - * RX_UC (RO) - * - * Number of unicast frames - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN */ -/* - * RX_INTERN (RO) - * - * Number of non-relay frames - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_BC */ -/* - * RX_BC (RO) - * - * Number of Broadcast frames - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI */ -/* - * RX_MULTI (RO) - * - * Number of Multicast frames - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN */ -/* - * RX_VLAN (RO) - * - * Number of VLAN tagged frames - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL */ -/* - * RX_DROP_OVFL (RO) - * - * Dropped frames by ingress overflow. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU */ -/* - * RX_DROP_LU (RO) - * - * Dropped frames by LookUp decision. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR */ -/* - * RX_DROP_ERR (RO) - * - * Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN */ -/* - * RX_DROP_VLAN (RO) - * - * Dropped frames by incompatible VLAN. - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT) - -/* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD */ -/* - * RX_FPE_FGOOD (RO) - * - * Number of preemptable frames. Subset of RX_FGOOD - */ -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK (0xFFFFFFFFUL) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT (0U) -#define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_VER */ -/* - * VER_H (R) - * - * Major version number (higher part of the version) - */ -#define TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK (0xFFFF0000UL) -#define TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT (16U) -#define TSW_TSNPORT_MAC_MAC_VER_VER_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT) - -/* - * VER_L (R) - * - * Minor version number (lower part of the version) - */ -#define TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK (0xFFFFU) -#define TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_VER_VER_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MACADDR_L */ -/* - * MACADDR (R/W) - * - * MAC address - * Lower bits of MAC address (31:0). - * MACADDR only be modified if TX_EN=0 and RX_EN=0. - */ -#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK) -#define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MACADDR_H */ -/* - * PROMISC (R/W) - * - * 0 – disabled - * 1 – enabled - * If promiscuous mode is enabled, then reception of all frames independent from the - * Ethernet destination address is enabled. - * PROMISC can be changed at any time. - */ -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK (0x10000UL) -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT (16U) -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT) - -/* - * MACADDR (R/W) - * - * MAC address (see Chapter 4.1) - * Upper bits of MAC address (47:32). - * MACADDR can only be modified if TX_EN=0 and RX_EN=0. - */ -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK (0xFFFFU) -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK) -#define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MAC_CTRL */ -/* - * FSTIM (R/W) - * - * Fault Stimulation - * See Chapter 11.3, Table 11-1 for details. - * FSTIM is write-locked if CSA=1. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK (0x1F000000UL) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT (24U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT) - -/* - * RCA (R) - * - * active - * 0 – not active - * 1 – active - * See chapter 11.2.3 for details. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK (0x100000UL) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT (20U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT) - -/* - * MCA (R) - * - * active - * 0 – not active - * 1 – active - * See chapter 11.2.3 for details. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK (0x80000UL) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT (19U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT) - -/* - * SEN (R/W) - * - * Safety Enable - * 0 – disabled - * 1 – enabled - * If enabled, then two instances of the logic core of LLEMAC-1G are compared at - * runtime to each other. - * SEN can only be changed if RX_EN and TX_EN can be read as 0. Deactivation delays - * of RX_EN and TX_EN have to be considered. It is possible to change SEN together - * with the activation of RX_EN and TX_EN. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK (0x10000UL) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT (16U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT) - -/* - * CSA (R) - * - * Clock switching active () - * 0 – not active - * 1 – active - * Switching of is commanded if CLKSEL or FSTIM (see Table 11-1) are - * written. Clock switching takes a few clock cycles and this is signaled with CSA=1. - * When CSA=1 then CLKSEL and FSTIM are write-locked and cannot be changed. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK (0x2000U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT (13U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT) - -/* - * RCE (R/W) - * - * enable - * 0 – disabled - * 1 – enabled - * RCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK (0x1000U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT (12U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT) - -/* - * MCE (R/W) - * - * enable - * 0 – disabled - * 1 – enabled - * MCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK (0x800U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT (11U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT) - -/* - * CLKSEL (R/W) - * - * TX path clock selector - * 000 – - * 001 – (recommended setting for this selection) - * 010 – divided by 5 - * 011 – divided by 10 - * 100 – divided by 50 - * 111 – and enables modification of RCE and MCE - * others – - * See Chapter 7 for further details. - * CLKSEL is write-locked if CSA=1. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK (0x700U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT (8U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT) - -/* - * PHYSEL (R/W) - * - * Selection of the PHY (See Chapter 4.6.) - * 00 – MII - * 01 – GMII - * 10 – RGMII - * 11 – reserved - * PHYSEL can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of - * RX_EN and TX_EN have to be considered. PHYSEL can only be changed, if these - * register bits can be read as 0. It is possible to change PHYSEL together with the - * activation of RX_EN and TX_EN. - * PHYSEL drives the output . - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK (0x60U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT (5U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT) - -/* - * GMIIMODE (R/W) - * - * GMII mode / Ethernet speed selection (See Chapter 4.5.) - * 0 – MII: 10Mbit/s or 100Mbit/s - * 1 – GMII: 1GBit/s - * GMIIMODE can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of - * RX_EN and TX_EN have to be considered. GMIIMODE can only be changed, if these - * register bits can be read as 0. It is possible to change GMIIMODE together with the - * activation of RX_EN and TX_EN. - * GMIIMODE drives the outputs and . - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK (0x10U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT (4U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT) - -/* - * JUMBO (R/W) - * - * Jumbo frame support - * 0 – jumbo frames not supported - * 1 – jumbo frame supported (not recommended) - * Jumbo frames are non-standard Ethernet frames with a size bigger than envelope - * frames (which contain 1982 payload bytes). If jumbo frames are not supported, then - * LLEMAC-1G generates the appropriate error signals ( for the TX path - * and for the RX path). - * Although jumbo frames typically contain up to 9000 bytes, the LLEMAC-1G can handle - * an infinite frame size. The problem of jumbo frames is the necessary storage space in - * transmission and reception buffers. LLEMAC-1G does not include storage buffers. - * JUMBO can be activated or deactivated at any time. The new setting becomes valid - * immediately after clock domain crossing. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK (0x8U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT (3U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT) - -/* - * TX_EN (R/W) - * - * TX path enable - * 0 – transmission disabled - Avalon-ST READY for the TX path will be set to 0. - * 1 – transmission enabled - * TX_EN can be activated or deactivated at any time. Deactivation may take some time. - * If during deactivation there is a frame in transmission, then this frame will be - * completed fist. Afterwards bit TX_EN can be read as 0. - * After the transmission is disabled there may be pending frames left, waiting at the TX - * stream interface. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK (0x4U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT (2U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT) - -/* - * RX_EN (R/W) - * - * RX path enable - * 0 – reception disabled – no frames fed to Avalon-ST RX path - * 1 – reception enabled - * RX_EN can be activated or deactivated at any time. Deactivation may take some time. - * If during deactivation there is a frame in reception, then this frame will be completed - * first. Afterwards bit RX_EN can be read as 0. - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK (0x2U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT (1U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT) - -/* - * RESSTAT (R/W) - * - * Software reset of the statistic counters (see Table 3-8) - * 0 – no reset - * 1 – reset active - * RESSTAT will be automatically set to 0 after the counters have been reset - */ -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK (0x1U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK) -#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_TX_FRAMES */ -/* - * TX_FRAMES (R) - * - * Number of successfully transmitted frames. - */ -#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_RX_FRAMES */ -/* - * RX_FRAMES (R) - * - * Number of successfully received frames. - */ -#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_TX_OCTETS */ -/* - * TX_OCTETS (R) - * - * Number of successfully transmitted payload and padding octets. - */ -#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_RX_OCTETS */ -/* - * RX_OCTETS (R) - * - * Number of successfully received payload and padding octets. - */ -#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_CFG */ -/* - * NPRE (R/W) - * - * No Preamble - * With NPRE=1 the preamble generation is suppressed and frames are initiated with - * Start of Frame pattern directly. Suitable in case that all connected PHYs accept - * management frames without a preamble pattern. Recommended to be used if only - * one PHY is connected. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK (0x8000U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT (15U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT) - -/* - * ENABLE (R/W) - * - * Enable the MDIO controller. If the controller is enabled then MDC will be toggled. - * ENABLE can only be read as 1 if a valid MDC_CLKDIV value is set. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK (0x100U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT (8U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT) - -/* - * MDC_CLKDIV (R/W) - * - * Clock Divider to configure MDC clock frequency. Refer to 10.1 Clock Divider for more - * details. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK (0xFFU) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_CTRL */ -/* - * OP (R/W) - * - * Opcode to determine transfer type - * 01 – Write Access - * 10 – Read Access - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK (0xC0000000UL) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT (30U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT) - -/* - * PHYAD (R/W) - * - * Management Frame PHY Address. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK (0x1F000000UL) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT (24U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT) - -/* - * REGAD (R/W) - * - * Management Frame Register Address. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK (0x1F0000UL) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT (16U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT) - -/* - * INIT (R/W) - * - * INIT=1 results in a MDIO write/read transfer if READY=1. If READY=0 while a - * transfer is already pending or if ENABLE=0 then settings INIT=1 has no effect and - * the current transaction is withdrawn. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK (0x100U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT (8U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT) - -/* - * READY (R) - * - * READY=1 indicates a finished transfer and also shows that the controller is ready for a - * new transfer. READY=1 is only possible if ENABLE=1. - * If READY=1 is signaled after a read transfer, then RD_DATA is valid until a new - * transfer is started. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK (0x1U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_RD_DATA */ -/* - * RD_DATA (R) - * - * Read Data is available if READY=1 after a transfer has been started. RD_DATA represents the content of the management data field of the read transfer. - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK (0xFFFFU) -#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_WR_DATA */ -/* - * WR_DATA (R/W) - * - * Data is used for the management data field after a write transfer has been started - */ -#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK (0xFFFFU) -#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK) -#define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MAC_IRQ_CTRL */ -/* - * CAIF (R/W) - * - * Clock activity interrupt flag - * 0 – no interrupt - * 1 – interrupt pending - * See Chapter 11.2.3 for details. - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK (0x800U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT (11U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT) - -/* - * SWIF (R/W) - * - * Safety warning interrupt flag - * 0 – no interrupt - * 1 – interrupt pending - * See Chapter 11.2.2 for details - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK (0x400U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT (10U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT) - -/* - * SEIF (R/W) - * - * Safety Error Interrupt Flag - * 0 – no interrupt - * 1 – interrupt pending - * If SEN=1 and if there is a mismatch between both instances of the logic core of - * LLEMAC-1G then this results in SEIF=1, TX_EN=0 and RX_EN=0. - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK (0x200U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT (9U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT) - -/* - * MDIF (R/W) - * - * MDIO Interrupt Flag - * 1 – A transfer has been finished - * 0 – No transfer done - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK (0x100U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT (8U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT) - -/* - * CAIE (R/W) - * - * Clock activity interrupt enable - * 0 – CAIF disabled - * 1 – CAIF enabled - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK (0x8U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT (3U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT) - -/* - * SWIE (R/W) - * - * Safety warning interrupt enable - * 0 – SWIF disabled - * 1 – SWIF enabled - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK (0x4U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT (2U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT) - -/* - * MDIE (R/W) - * - * MDIO Interrupt Enable - * 0 – Disabled - * 1 – Enabled - */ -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK (0x1U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT (0U) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK) -#define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_CR */ -/* - * TAIE (R/W) - * - * Timer A interrupt enable: interrupt enabled when 1 - */ -#define TSW_TSNPORT_RTC_CR_TAIE_MASK (0x8U) -#define TSW_TSNPORT_RTC_CR_TAIE_SHIFT (3U) -#define TSW_TSNPORT_RTC_CR_TAIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAIE_SHIFT) & TSW_TSNPORT_RTC_CR_TAIE_MASK) -#define TSW_TSNPORT_RTC_CR_TAIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAIE_MASK) >> TSW_TSNPORT_RTC_CR_TAIE_SHIFT) - -/* - * TAEN (R/W) - * - * Timer A enable: timer enabled when 1 - */ -#define TSW_TSNPORT_RTC_CR_TAEN_MASK (0x4U) -#define TSW_TSNPORT_RTC_CR_TAEN_SHIFT (2U) -#define TSW_TSNPORT_RTC_CR_TAEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAEN_SHIFT) & TSW_TSNPORT_RTC_CR_TAEN_MASK) -#define TSW_TSNPORT_RTC_CR_TAEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAEN_MASK) >> TSW_TSNPORT_RTC_CR_TAEN_SHIFT) - -/* - * ALIE (R/W) - * - * Alarm interrupt enable: alarm interrupt enabled when 1 - */ -#define TSW_TSNPORT_RTC_CR_ALIE_MASK (0x2U) -#define TSW_TSNPORT_RTC_CR_ALIE_SHIFT (1U) -#define TSW_TSNPORT_RTC_CR_ALIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_ALIE_SHIFT) & TSW_TSNPORT_RTC_CR_ALIE_MASK) -#define TSW_TSNPORT_RTC_CR_ALIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_ALIE_MASK) >> TSW_TSNPORT_RTC_CR_ALIE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_SR */ -/* - * TAIS (R/WC) - * - * Timer A Interrupt Status: set at rising edge of “timer_clk_a”, write 1 to clear - */ -#define TSW_TSNPORT_RTC_SR_TAIS_MASK (0x8U) -#define TSW_TSNPORT_RTC_SR_TAIS_SHIFT (3U) -#define TSW_TSNPORT_RTC_SR_TAIS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_SR_TAIS_SHIFT) & TSW_TSNPORT_RTC_SR_TAIS_MASK) -#define TSW_TSNPORT_RTC_SR_TAIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_TAIS_MASK) >> TSW_TSNPORT_RTC_SR_TAIS_SHIFT) - -/* - * ALIS (RO) - * - * ALIS ro Alarm Interrupt Status: Always set while RTC-Time >= Alarm-Time - */ -#define TSW_TSNPORT_RTC_SR_ALIS_MASK (0x2U) -#define TSW_TSNPORT_RTC_SR_ALIS_SHIFT (1U) -#define TSW_TSNPORT_RTC_SR_ALIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_ALIS_MASK) >> TSW_TSNPORT_RTC_SR_ALIS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_CT_CURTIME_NS */ -/* - * CT_NS (RO/WU) - * - * Local Time (nanosecond part): Update can be triggered by write access to this register. Value range from 0 – 999999999. - */ -#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK (0x3FFFFFFFUL) -#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT (0U) -#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK) -#define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_CT_CURTIME_SEC */ -/* - * CT_SEC (RO) - * - * Current Time (second part): Update can be triggered by write access to register CURTIME_NS. - */ -#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT (0U) -#define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_CT_TIMER_INCR */ -/* - * NS (RW) - * - * Local time increment – nanoseconds (integer) - */ -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK (0xFF000000UL) -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT (24U) -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK) -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT) - -/* - * FNS (RW) - * - * Local time increment – fractional ns, unsigned, in (1 / 2^24) n - */ -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK (0xFFFFFFUL) -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT (0U) -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK) -#define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_OFS_NS */ -/* - * OFS_NS (R/W) - * - * Real Time Offset (nanoseconds part). Valid value range from 0 – 999999999. - */ -#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK (0x3FFFFFFFUL) -#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT (0U) -#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK) -#define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK) >> TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_OFS_SL */ -/* - * OFS_SL (R/W) - * - * 48 Bit Real Time Offset (seconds lo part) - */ -#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT (0U) -#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK) -#define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK) >> TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_OFS_SH */ -/* - * OFS_SH (R/W) - * - * 48 Bit Real Time Offset (seconds hi part) - */ -#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK (0xFFFFU) -#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT (0U) -#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK) -#define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK) >> TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_OFS_CH */ -/* - * SEXT (RO) - * - * Real Time Offset Change – sign extension of SFNS (Bit 23) - */ -#define TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK (0xFF000000UL) -#define TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT (24U) -#define TSW_TSNPORT_RTC_OFS_CH_SEXT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT) - -/* - * SFNS (R/W) - * - * Real Time Offset Change in fractional nanoseconds, signed value; value range from -2^23 / 2^24 to (2^23-1) / 2^24 nanoseconds. - */ -#define TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK (0xFFFFFFUL) -#define TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT (0U) -#define TSW_TSNPORT_RTC_OFS_CH_SFNS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK) -#define TSW_TSNPORT_RTC_OFS_CH_SFNS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_NS */ -/* - * AL_NS (R/W) - * - * Alarm Time (nanoseconds part). Valid value range from 0 – 999999999. - */ -#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK (0x3FFFFFFFUL) -#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT (0U) -#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK) -#define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK) >> TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_SL */ -/* - * AL_SL (R/W) - * - * Alarm Time (seconds lo part) - */ -#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT (0U) -#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK) -#define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK) >> TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_SH */ -/* - * AL_SH (R/W) - * - * Alarm Time (seconds hi part) - */ -#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK (0xFFFFU) -#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT (0U) -#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK) -#define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK) >> TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: RTC_TIMER_A_PERIOD */ -/* - * PERIOD_NS (R/W) - * - * Timer A Period in ns. This is the period of the timer until the next event, but the half-period of the signal “timer_a_clk”. - */ -#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK (0x1FFFFFFFUL) -#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT (0U) -#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK) -#define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK) >> TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_CR */ -/* - * TMR_ALD (R/W) - * - * Timer Auto Load: automatic reloading of timer when reaching 0. Done flag stays set after countdown. Used for periodic events, when following event shall not be delayed by host interaction. - */ -#define TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK (0x1F0000UL) -#define TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT (16U) -#define TSW_TSNPORT_TSYN_CR_TMR_ALD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK) -#define TSW_TSNPORT_TSYN_CR_TMR_ALD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT) - -/* - * TMR_EN (R/W) - * - * Timer Enable: every bit corresponds to Timer 0 – 4 - */ -#define TSW_TSNPORT_TSYN_CR_TMR_EN_MASK (0x1F00U) -#define TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT (8U) -#define TSW_TSNPORT_TSYN_CR_TMR_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK) -#define TSW_TSNPORT_TSYN_CR_TMR_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT) - -/* - * TMRIE (R/W) - * - * Timer Interrupt Enable - */ -#define TSW_TSNPORT_TSYN_CR_TMRIE_MASK (0x4U) -#define TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT (2U) -#define TSW_TSNPORT_TSYN_CR_TMRIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK) -#define TSW_TSNPORT_TSYN_CR_TMRIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK) >> TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT) - -/* - * RXIE (R/W) - * - * Rx Interrupt Enable - */ -#define TSW_TSNPORT_TSYN_CR_RXIE_MASK (0x2U) -#define TSW_TSNPORT_TSYN_CR_RXIE_SHIFT (1U) -#define TSW_TSNPORT_TSYN_CR_RXIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_RXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_RXIE_MASK) -#define TSW_TSNPORT_TSYN_CR_RXIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_RXIE_MASK) >> TSW_TSNPORT_TSYN_CR_RXIE_SHIFT) - -/* - * TXIE (R/W) - * - * Tx Interrupt Enable - */ -#define TSW_TSNPORT_TSYN_CR_TXIE_MASK (0x1U) -#define TSW_TSNPORT_TSYN_CR_TXIE_SHIFT (0U) -#define TSW_TSNPORT_TSYN_CR_TXIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TXIE_MASK) -#define TSW_TSNPORT_TSYN_CR_TXIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TXIE_MASK) >> TSW_TSNPORT_TSYN_CR_TXIE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_SR */ -/* - * TMR_DN (R/WC) - * - * Timer Done: 1 when timer reached 0 - */ -#define TSW_TSNPORT_TSYN_SR_TMR_DN_MASK (0x1F00U) -#define TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT (8U) -#define TSW_TSNPORT_TSYN_SR_TMR_DN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK) -#define TSW_TSNPORT_TSYN_SR_TMR_DN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK) >> TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT) - -/* - * TMRIS (RO) - * - * Timer Interrupt Status: OR’ed (TMR_DN AND TMR_EN) flags. 1 when timer is enabled and countdown is done - */ -#define TSW_TSNPORT_TSYN_SR_TMRIS_MASK (0x4U) -#define TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT (2U) -#define TSW_TSNPORT_TSYN_SR_TMRIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMRIS_MASK) >> TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT) - -/* - * RXIS (RO) - * - * Rx Interrupt Status, RX buffer data available equal to PTP_RX_STS.AV) - */ -#define TSW_TSNPORT_TSYN_SR_RXIS_MASK (0x2U) -#define TSW_TSNPORT_TSYN_SR_RXIS_SHIFT (1U) -#define TSW_TSNPORT_TSYN_SR_RXIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_RXIS_MASK) >> TSW_TSNPORT_TSYN_SR_RXIS_SHIFT) - -/* - * TXIS (RO) - * - * Tx Done Interrupt Status: OR’ed PTP_TX_DONE - */ -#define TSW_TSNPORT_TSYN_SR_TXIS_MASK (0x1U) -#define TSW_TSNPORT_TSYN_SR_TXIS_SHIFT (0U) -#define TSW_TSNPORT_TSYN_SR_TXIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TXIS_MASK) >> TSW_TSNPORT_TSYN_SR_TXIS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_STS */ -/* - * STS (RO) - * - * Transmission status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission pending - */ -#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK (0xFFU) -#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT (0U) -#define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_DONE */ -/* - * DONE (R/WC) - * - * Transmission done status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission done. - * Writing a ‘1’ clears corresponding bit.. - */ -#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK (0xFFU) -#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT (0U) -#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK) -#define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_TRIG */ -/* - * TRIG (WO) - * - * Trigger PTP TX bin n (bit 0 – 7 correspond to tx bin 0 –7). Writing ‘1’ will trigger transmission. Corresponding bit PTP_TX_STS.STS(n) will be set immediately. - */ -#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK (0xFFU) -#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT (0U) -#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK) -#define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_RX_STS */ -/* - * OV (R/WC) - * - * FIFO overflow flag. PTP frame has been received and there was no free buffer available. Data has been lost. - */ -#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK (0x80000000UL) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT (31U) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT) - -/* - * AV_NXT (R/W) - * - * Read access: buffer data available – reading data from RX_BUF is valid. - * Write access: switch to next RX buffer – shall only be done when buffer not empty (AV=1). Use field RX_SEL as indication when rx buffer switch has been done. - */ -#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK (0x40000000UL) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT (30U) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT) - -/* - * RX_SEL (RO) - * - * Current selected RX buffer for reading (0-7). Can be used to determine when RX buffer has been switched after setting PTP_RX_STS.NXT - */ -#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK (0x7U) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT (0U) -#define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_TMR0 */ -/* - * PERIOD (R/W) - * - * Period in ticks, ticks based on register HCLKDIV and host clock . - */ -#define TSW_TSNPORT_TSYNTMR_PERIOD_MASK (0xFFFFFUL) -#define TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT (0U) -#define TSW_TSNPORT_TSYNTMR_PERIOD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK) -#define TSW_TSNPORT_TSYNTMR_PERIOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK) >> TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_HCLKDIV */ -/* - * PERIOD (R/W) - * - * Period in host clocks . Host clock shall be scaled to ticks of 1/1024th second. Ticks are used by timer TMR0 – TMR4. - */ -#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK (0xFFFFFUL) -#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT (0U) -#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK) -#define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK) >> TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_FRAME_LENGTH_BYTES */ -/* - * RX_FRAME_LENGTH_BYTES (RO) - * - * RX frame length bytes [11:0] - */ -#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK (0xFFFU) -#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT (0U) -#define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_TIME_STAMP_L */ -/* - * RX_TIMESTAMP_LOW (RO) - * - * RX Timestamp [31:0] - */ -#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT (0U) -#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_TIME_STAMP_H */ -/* - * RX_TIMESTAMP_HIGH (RO) - * - * RX Timestamp [63:32] - */ -#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT (0U) -#define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_DATA_WORD0 */ -/* - * RXBUF_DATA_WORD (RO) - * - * RXBUF_DATA_WORD - */ -#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT (0U) -#define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK) >> TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_BIN0_DATA_WORD0 */ -/* - * TXBUF_BIN0_DATA_WORD0 (WO/RO) - * - * TXBUF_BIN0_DATA_WORD0 - */ -#define TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_SHIFT (0U) -#define TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_SHIFT) & TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_MASK) -#define TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_MASK) >> TSW_TSNPORT_BIN_TXDATA_TXBUF_BIN0_DATA_WORD0_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN */ -/* - * TXBUF_BIN0_TQUE (WO/RO) - * - * TXBUF_BIN0_TQUE - */ -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_MASK (0x7000000UL) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_SHIFT (24U) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_MASK) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TQUE_SHIFT) - -/* - * TXBUF_BIN0_TX_LEN (WO/RO) - * - * TXBUF_BIN0_TX_LEN - */ -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_MASK (0xFFU) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_SHIFT (0U) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_MASK) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TQUE_AND_TX_LEN_TXBUF_BIN0_TX_LEN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_BIN0_TX_TIMESTAMP_L */ -/* - * TXBUF_BIN0_TX_TIMESTAMP_L (WO/RO) - * - * TXBUF_BIN0_TX_TIMESTAMP_L - */ -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_SHIFT (0U) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_MASK) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_L_TXBUF_BIN0_TX_TIMESTAMP_L_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_BIN0_TX_TIMESTAMP_H */ -/* - * TXBUF_BIN0_TX_TIMESTAMP_H (WO/RO) - * - * TXBUF_BIN0TX_TIMESTAMP_H - */ -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_SHIFT (0U) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_MASK) -#define TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_BIN0_TX_TIMESTAMP_H_TXBUF_BIN0_TX_TIMESTAMP_H_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_HWCFG1 */ -/* - * LWIDTH (RO) - * - * Scheduler list address width (IP core parameter LWIDTH) - */ -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK (0xFF000000UL) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT (24U) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT) - -/* - * TQC (RO) - * - * Traffic queue count (IP core parameter TQC) - */ -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK (0xFF0000UL) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT (16U) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT) - -/* - * TQD (RO) - * - * Traffic queue depth (IP core parameter TQD) - */ -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK (0xFF00U) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT (8U) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT) - -/* - * DW (RO) - * - * Traffic queue data width (Bytes); fixed to value 4 within - * IP core - */ -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK (0xFFU) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TQAV */ -/* - * AVIE (R/W) - * - * Traffic queue interrupt enable on buffer space available, - * one bit per traffic queue - * Bit[i] = 0: no interrupt - * Bit[i] = 1: interrupt, when AVAIL[i]=1 - */ -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK (0xFF00U) -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT (8U) -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT) - -/* - * AVAIL (RO) - * - * Traffic queue buffer space available for complete packet of size MaxSDU (register MXSDUi) - * Bit[i] = 1: space available - * Bit[i] = 0: no space available or TQ not implemented (I >= TQC) - */ -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK (0xFFU) -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TQEM */ -/* - * EMPTY (RO) - * - * Traffic queue empty - * Bit[i] = 1: traffic queue i is empty - */ -#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK (0xFFU) -#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_FPST */ -/* - * TABLE (R/W) - * - * Frame Preemption Status Table, - * Bit[i] = 1: Preemptable traffic in TQ[i], otherwise - * Express traffic (default) - */ -#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK (0xFFU) -#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK) -#define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK) >> TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MMCT */ -/* - * RQREL (R/W) - * - * Request HOLD-Signal release operation. Will be automatically set to <0> - */ -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK (0x2U) -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT (1U) -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK) -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT) - -/* - * RQHLD (R/W) - * - * Request HOLD-Signal hold operation. Will be automatically set to <0>. - */ -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK (0x1U) -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK) -#define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_HOLDADV */ -/* - * VALUE (R/W) - * - * holdAdvance time for TAS operation Set-And-Hold-MAC in cycles - */ -#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK (0xFFFFU) -#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK) -#define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK) >> TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MXSDU0 */ -/* - * SDU (R/W) - * - * Maximum SDU size for traffic queue n (n = 0 – 7)Returns 0 when n > TQC. Value is size in words (32 bit word size). - */ -#define TSW_TSNPORT_MXSDU_SDU_MASK (0xFFFFU) -#define TSW_TSNPORT_MXSDU_SDU_SHIFT (0U) -#define TSW_TSNPORT_MXSDU_SDU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXSDU_SDU_SHIFT) & TSW_TSNPORT_MXSDU_SDU_MASK) -#define TSW_TSNPORT_MXSDU_SDU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXSDU_SDU_MASK) >> TSW_TSNPORT_MXSDU_SDU_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TXSEL0 */ -/* - * CBS_EN (R/W) - * - * CBS enable traffic queue n (n = 0 – 7). Returns 0 when n > TQC. Must be 0 when changing register IDSLPi. - */ -#define TSW_TSNPORT_TXSEL_CBS_EN_MASK (0xFFFFU) -#define TSW_TSNPORT_TXSEL_CBS_EN_SHIFT (0U) -#define TSW_TSNPORT_TXSEL_CBS_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TXSEL_CBS_EN_SHIFT) & TSW_TSNPORT_TXSEL_CBS_EN_MASK) -#define TSW_TSNPORT_TXSEL_CBS_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TXSEL_CBS_EN_MASK) >> TSW_TSNPORT_TXSEL_CBS_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_IDSEL0 */ -/* - * INT (R/W) - * - * CBS idle slope for traffic queue n (n = 0 – 7). Returns - * 0 when n > TQC. The register must only be written - * when TXSELi.CBE_EN=0. - * The idle slope value is defined as (INT + FRACT / - * 65536). The idle slope is set in bits per tick related to - * . - */ -#define TSW_TSNPORT_IDSEL_INT_MASK (0xF0000UL) -#define TSW_TSNPORT_IDSEL_INT_SHIFT (16U) -#define TSW_TSNPORT_IDSEL_INT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_IDSEL_INT_SHIFT) & TSW_TSNPORT_IDSEL_INT_MASK) -#define TSW_TSNPORT_IDSEL_INT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_IDSEL_INT_MASK) >> TSW_TSNPORT_IDSEL_INT_SHIFT) - -/* - * FRACT (R/W) - * - */ -#define TSW_TSNPORT_IDSEL_FRACT_MASK (0xFFFFU) -#define TSW_TSNPORT_IDSEL_FRACT_SHIFT (0U) -#define TSW_TSNPORT_IDSEL_FRACT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_IDSEL_FRACT_SHIFT) & TSW_TSNPORT_IDSEL_FRACT_MASK) -#define TSW_TSNPORT_IDSEL_FRACT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_IDSEL_FRACT_MASK) >> TSW_TSNPORT_IDSEL_FRACT_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: PORT1_QCH0_CFG */ -/* - * CQF_IN_ERR (WC) - * - * qch queue in error - */ -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK (0x100000UL) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT (20U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT) - -/* - * CQF_NUM (R/W) - * - * qch queue destination buffer select - */ -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK (0x70000UL) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT (16U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT) - -/* - * TAS_GPIO_SEL (R/W) - * - * tas_gpio select - */ -#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK (0x7000U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT (12U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK) -#define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT) - -/* - * AXIS_QCH_EN (R/W) - * - * qch queue in select - */ -#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK (0xFF0U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT (4U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT) - -/* - * CQF_EN (R/W) - * - * qch enable - */ -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK (0x1U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT (0U) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: PORT1_QCH1_CFG */ -/* - * CQF_IN_ERR (WC) - * - * qch queue in error - */ -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK (0x100000UL) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT (20U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT) - -/* - * CQF_NUM (R/W) - * - * qch queue destination buffer select - */ -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK (0x70000UL) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT (16U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT) - -/* - * TAS_GPIO_SEL (R/W) - * - * tas_gpio select - */ -#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK (0x7000U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT (12U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK) -#define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT) - -/* - * AXIS_QCH_EN (R/W) - * - * qch queue in select - */ -#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK (0xFF0U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT (4U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT) - -/* - * CQF_EN (R/W) - * - * qch enable - */ -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK (0x1U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT (0U) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: PORT1_QCH2_CFG */ -/* - * CQF_IN_ERR (WC) - * - * qch queue in error - */ -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK (0x100000UL) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT (20U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT) - -/* - * CQF_NUM (R/W) - * - * qch queue destination buffer select - */ -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK (0x70000UL) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT (16U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT) - -/* - * TAS_GPIO_SEL (R/W) - * - * tas_gpio select - */ -#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK (0x7000U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT (12U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK) -#define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT) - -/* - * AXIS_QCH_EN (R/W) - * - * qch queue in select - */ -#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK (0xFF0U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT (4U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT) - -/* - * CQF_EN (R/W) - * - * qch enable - */ -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK (0x1U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT (0U) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: PORT1_QCH3_CFG */ -/* - * CQF_IN_ERR (WC) - * - * qch queue in error - */ -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK (0x100000UL) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT (20U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT) - -/* - * CQF_NUM (R/W) - * - * qch queue destination buffer select - */ -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK (0x70000UL) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT (16U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT) - -/* - * TAS_GPIO_SEL (R/W) - * - * tas_gpio select - */ -#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK (0x7000U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT (12U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK) -#define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT) - -/* - * AXIS_QCH_EN (R/W) - * - * qch queue in select - */ -#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK (0xFF0U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT (4U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT) - -/* - * CQF_EN (R/W) - * - * qch enable - */ -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK (0x1U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT (0U) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK) -#define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: PORT1_QCH_ERR_CFG */ -/* - * CQF_QUE_ERR (WC) - * - * que gate error for each cqf - */ -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK (0xFF00U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT (8U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT) - -/* - * CQF_NUM_CFG_ERR (RO) - * - * cqf_num config error - */ -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK (0x4U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT (2U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT) - -/* - * AXIS_QCH_CFG_ERR (RO) - * - * axis_qch_en config error - */ -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK (0x2U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT (1U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT) - -/* - * CQF_CLR_CTRL (R/W) - * - * enable cqf buffer auto clear when error - */ -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK (0x1U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT (0U) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK) -#define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_CRSR */ -/* - * ADMINGS (RO) - * - * Admin gate states, fixed 0xFF. Gate states when TAS is disabled. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK (0xFF000000UL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT (24U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT) - -/* - * OPERGS (RO) - * - * Operational gate states of TQ[i] (i = 0 – TQC-1) - * Bit[i]=0 – Gate is closed; no start of frame TX possible - * Bit[i]=1 – Gate is open - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK (0xFF0000UL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT (16U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT) - -/* - * TAS_GPIO_STA (RO) - * - * operational tas gpio gate status of TQ[i] - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK (0xFF00U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT (8U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT) - -/* - * CFGPEND (RO) - * - * Configuration change is pending – Admin basetime not yet reached. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK (0x8U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT (3U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT) - -/* - * CFGERR (R/WC) - * - * Configuration error. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK (0x4U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT (2U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT) - -/* - * CFGCHG (R/W) - * - * Switch configuration; Bit is automatically reset to 0; - * Setting Bit=1 triggers configuration change event. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK (0x2U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT (1U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT) - -/* - * EN (R/W) - * - * Enable time aware scheduling. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK (0x1U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ACYCLETM */ -/* - * CTIME (R/W) - * - * Admin cycletime in nanoseconds. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK (0x3FFFFFFFUL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ABASETM_L */ -/* - * BASETM_L (R/W) - * - * Admin basetime – nanoseconds and seconds part. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK (0x3FFFFFFFUL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ABASETM_H */ -/* - * BASETM_H (R/W) - * - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_LISTLEN */ -/* - * OLISTLEN (RO) - * - * Oper list length. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK (0xFF0000UL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT (16U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT) - -/* - * ALISTLEN (R/W) - * - * Admin list length. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK (0xFFU) -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) -#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OCYCLETM */ -/* - * CTIME (RO) - * - * Operational cycletime in nanoseconds - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK (0x3FFFFFFFUL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OBASETM_L */ -/* - * BASETM_L (RO) - * - * Operational basetime – nanoseconds and seconds part. The operational basetime might occasionally have a non-normalized value (ns >= 10^9) for one clock cycle. - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OBASETM_H */ -/* - * BASETM_H (RO) - * - */ -#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT (0U) -#define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MXTK0 */ -/* - * TICK (R/W) - * - * Maximum SDU size in clock ticks. MXTKi is only supported when TQC > i, otherwise read-only with value 0 - */ -#define TSW_TSNPORT_MXTK_TICK_MASK (0xFFFFFFUL) -#define TSW_TSNPORT_MXTK_TICK_SHIFT (0U) -#define TSW_TSNPORT_MXTK_TICK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXTK_TICK_SHIFT) & TSW_TSNPORT_MXTK_TICK_MASK) -#define TSW_TSNPORT_MXTK_TICK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXTK_TICK_MASK) >> TSW_TSNPORT_MXTK_TICK_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TXOV0 */ -/* - * VALUE (R/WC) - * - * Transmission overrun counter; increments on transmission when gate is closed; any write access will clear register to 0. TXOVi is only supported when TQC > i. - */ -#define TSW_TSNPORT_TXOV_VALUE_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TXOV_VALUE_SHIFT (0U) -#define TSW_TSNPORT_TXOV_VALUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TXOV_VALUE_SHIFT) & TSW_TSNPORT_TXOV_VALUE_MASK) -#define TSW_TSNPORT_TXOV_VALUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TXOV_VALUE_MASK) >> TSW_TSNPORT_TXOV_VALUE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_ACLIST_ENTRY0_L */ -/* - * TAS_GPIO (R/W) - * - * gate states for qch and ptp event source - */ -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_MASK (0x3FC00UL) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_SHIFT (10U) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_MASK) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_TAS_GPIO_SHIFT) - -/* - * OP (R/W) - * - * gate operation: - * 0 – SetGateStates - * 1 – Set-And-Hold-MAC - * 2 – Set-And-Release-MAC - * 3 – undefined - */ -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_MASK (0x300U) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_SHIFT (8U) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_MASK) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_OP_SHIFT) - -/* - * STATE (R/W) - * - * gate state vector; - * 1 – Gate is open - */ -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_MASK (0xFFU) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_SHIFT (0U) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_MASK) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_L_STATE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_ACLIST_ENTRY0_H */ -/* - * TIME (R/W) - * - * Time interval, entry execution in in host clock ticks () - */ -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_SHIFT (0U) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_MASK) -#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY0_H_TIME_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_VER */ -/* - * VER_HI (RO) - * - * major version number - */ -#define TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK (0xFF000000UL) -#define TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT (24U) -#define TSW_TSNPORT_TSN_EP_VER_VER_HI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT) - -/* - * VER_LO (RO) - * - * minor version number - */ -#define TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK (0xFF0000UL) -#define TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT (16U) -#define TSW_TSNPORT_TSN_EP_VER_VER_LO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT) - -/* - * VER_REV (RO) - * - * revision number - */ -#define TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK (0xFFU) -#define TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_VER_VER_REV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_CTRL */ -/* - * FILTDIS (R/W) - * - * Disable filtering of PTP frames (Ethertype = 0x88F7) - */ -#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK (0x80000000UL) -#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT (31U) -#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK) -#define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT) - -/* - * PTP_1S_EN (R/W) - * - * Enable PTPv2 1-step synchronization suppor - */ -#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK (0x40000000UL) -#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT (30U) -#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK) -#define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT) - -/* - * IE_TSF (R/W) - * - * TxTimestampFifo interrupt enable; interrupt will be set when IE_TSF=<1> and TSF_SR.USED>0 - */ -#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK (0x1U) -#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK) -#define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_TXUF */ -/* - * COUNTER (R/WC) - * - * TX buffer underflow counter; incremented when any MAC runs out of data during transmission. The counter is cleared at any write access. The counter is shared by pMAC and eMAC. If underflow event occurs at the same time for pMAC and eMAC, it will be counted as one event. - */ -#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK) -#define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_IPCFG */ -/* - * INCL_RTC (RO) - * - * IP core parameter “INCL_RTC” - */ -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK (0x80000000UL) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT (31U) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT) - -/* - * INCL_SHAP (RO) - * - * IP core parameter “INCL_SHAPER” - */ -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK (0x40000000UL) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT (30U) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT) - -/* - * INCL_FPE (RO) - * - * IP core parameter “INCL_FPE” - */ -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK (0x20000000UL) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT (29U) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT) - -/* - * INCL_TSF (RO) - * - * IP core parameter “INCL_TSF” - */ -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK (0x10000000UL) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT (28U) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT) - -/* - * INCL_TSYNC (RO) - * - * IP core parameter “INCL_TSYNC” - */ -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK (0x8000000UL) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT (27U) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT) - -/* - * INCL_1STEP (RO) - * - * IP core parameter “INCL_1STEP” - */ -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK (0x4000000UL) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT (26U) -#define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D0 */ -/* - * TSF_NS (RO) - * - * Tx-Timestamp-Fifo, lower 32 bit part of local time () at the start of transmission of the packet. Usually nanoseconds part when used with included RTC. - */ -#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D1 */ -/* - * TSF_SEC (RO) - * - * Tx-Timestamp-Fifo, upper 32 bit part of the local time () at the start of the transmission of the packet. Usually seconds part when used with included RTC. - */ -#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D2 */ -/* - * TSF_TQ (RO) - * - * Tx-Timestamp-Fifo, traffic queue of sent packet - */ -#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK (0xE0000000UL) -#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT (29U) -#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT) - -/* - * TSF_USR (RO) - * - * Tx-Timestamp-Fifo, user sideband of sent packet; Note: any read to register will remove actual value from FIFO - */ -#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK (0x7U) -#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_SR */ -/* - * TSF_OV (R/WC) - * - * Overflow of Tx-Timestamp-Fifo. At least one transmitted packet has been sent and timestamp was not stored; write bit to clear flag - */ -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK (0x80000000UL) -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT (31U) -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK) -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT) - -/* - * TSF_USED (RO) - * - * Tx-Timestamp-Fifo currently used entries counter; reading of TSF_Dx is only valid if field value > 0. Any read from TSF_D2 will decrement counter (unless already 0). - */ -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK (0xFFU) -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_CTRL */ -/* - * STATSEL (R/W) - * - * MMS statistic counter selection, value can be read in register - * MMS_STAT - * <000>: Frame reassembly error counter (802.3br, 30.14.1.8) - * <001>: Frames rejected due to wrong SMD (802.3br, 30.14.1.9) - * <010>: Frame assembly ok counter (802.3br, 30.14.1.10) - * <011>: Fragment rx counter (802.3br, 30.14.1.11) - * <100>: Fragment tx counter (802.3br, 30.14.1.12) - * <101>: Hold request counter (802.3br, 30.14.1.13) - * otherwise: <0> - */ -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK (0xE0U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT (5U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT) - -/* - * FRAGSZ (R/W) - * - * Minimum non-final fragment size: 64 x (1 + FRAGSZ) – 4 octets - */ -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK (0x18U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT (3U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT) - -/* - * DISV (R/W) - * - * Disable verification - */ -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK (0x4U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT (2U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT) - -/* - * LINK (R/W) - * - * Link error - */ -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK (0x2U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT (1U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT) - -/* - * EN (R/W) - * - * Enable preemption - */ -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK (0x1U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_STS */ -/* - * VFAIL (RO) - * - * 802.3br verification state failure; verification is done when any bit VFAIL or VOK is <1> - */ -#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK (0x4U) -#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT (2U) -#define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT) - -/* - * VOK (RO) - * - * 802.3br verification state ok; verification is done when any bit VFAIL or VOK is <1> - */ -#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK (0x2U) -#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT (1U) -#define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT) - -/* - * HLD (RO) - * - * HOLD-Signal - */ -#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK (0x1U) -#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_VTIME */ -/* - * VTIME (R/W) - * - * 802.3br verification timeout counter in cycles. Must be set by software in range of 1ms to 128ms. - */ -#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK) >> TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_STAT */ -/* - * COUNTER (R/WC) - * - * Statistic counter of MMS, selected by MMS_CTRL.STATSEL,any write access will clear selected counter - */ -#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK) -#define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_UPTM_NS */ -/* - * UPTM_NS (WO) - * - * PTP SYNC frame “upstreamTxTime” in format “seconds.nanoseconds” as potentially received by another TSN-EP port. The correction field of a transmitted PTP SYNC frame is modified by (egressTimestamp –upstreamTxTime), relative to the LocalClock. The “rateRatio” to the Grandmaster Clock is not taken into account. - */ -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK) -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_UPTM_S */ -/* - * UPTM_NS (WO) - * - */ -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK) -#define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_SR */ -/* - * MEAS_NS (RO) - * - * Measured value of the deviation of the early timestamping for PTP frames. This value is informational only. The deviation is already included to the corrected “correctionField”. - */ -#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK (0xFFFFU) -#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT (0U) -#define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_PORT_MAIN_TAGGING */ -/* - * FORCE (R/W) - * - * The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK (0x20000UL) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT (17U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT) - -/* - * ACCESS (R/W) - * - * Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK (0x10000UL) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT (16U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT) - -/* - * PCP (R/W) - * - * VLAN-TCI: Priority Code Point, used when tagged. - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK (0xE000U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT (13U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT) - -/* - * DEI (R/W) - * - * VLAN-TCI: Drop Eligible Indicator, used when tagged. - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK (0x1000U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT (12U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT) - -/* - * PVID (R/W) - * - * Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1. - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK (0xFFFU) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT (0U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_PORT_MAIN_ENNABLE */ -/* - * EN_SF (R/W) - * - * only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK (0x2U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT (1U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT) - -/* - * EN_QCI (R/W) - * - * if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption. - */ -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK (0x1U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT (0U) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK) -#define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_EGRESS_ECSR_QDROP */ -/* - * DIS_VEC (R/W) - * - * disable drop for each queue when queue not free - */ -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK (0xFF000000UL) -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT (24U) -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK) -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT) - -/* - * EN_VEC (R/W) - * - * Enable/Disable drop in egress when TSN queue not free. - * 1 - drop enabled - * 0 - drop disabled - * TSN-SW: - * bit[i] - from Port[i] - */ -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK (0xFFFFFFUL) -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT (0U) -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK) -#define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE */ -/* - * FDMEM_CNT_BYTE (RO) - * - * Number of bytes stored in frame drop FIFO - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS */ -/* - * WAIT_FOR_LU (RO) - * - * FD FIFO waits for LookUp information. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK (0x800U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT (11U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT) - -/* - * WAIT_FOR_FRAME (RO) - * - * FD FIFO waits for more frame data. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK (0x400U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT (10U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT) - -/* - * BUSY (RO) - * - * FD FIFO processes data. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK (0x200U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT (9U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT) - -/* - * READY (RO) - * - * FD FIFO ready to work or working. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK (0x100U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT (8U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT) - -/* - * FULL (RO) - * - * FD FIFO full - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK (0x8U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT (3U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT) - -/* - * AMST_FULL (RO) - * - * FD FIFO almost full. Less than 1600 Byte left. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK (0x4U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT (2U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT) - -/* - * AMST_EMPTY (RO) - * - * FD FIFO almost empty. Few bytes in FIFO. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK (0x2U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT (1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT) - -/* - * EMPTY (RO) - * - * FD FIFO empty - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK (0x1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG */ -/* - * LU_DESC_ERR (R/W1C) - * - * LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK (0x40U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT (6U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT) - -/* - * WRFAIL_FULL (R/W1C) - * - * Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK (0x20U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT (5U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT) - -/* - * DROP_NRDY (R/W1C) - * - * Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK (0x10U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT (4U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT) - -/* - * DROP_FULL_DESC (R/W1C) - * - * Frame was dropped because the internal descriptor FIFO is full. Full by too many frames. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK (0x8U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT (3U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT) - -/* - * DROP_FULL_MEM (R/W1C) - * - * Frame was dropped because the FIFO is full. Full by too much data. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK (0x4U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT (2U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT) - -/* - * DESC_NRDY_ERR (R/W1C) - * - * FD FIFO failure. Descriptor not received correctly. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK (0x2U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT (1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) - -/* - * DESC_SEQ_ERR (R/W1C) - * - * FD FIFO failure. Internal controller lost synchronization. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK (0x1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG */ -/* - * IE (R/W) - * - * Interrupt enable of ERROR_FLAG. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK (0x7FU) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG */ -/* - * NOCUT_ERROR (R/W) - * - * FD_FIFO does not shorten frames which contain an error. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK (0x1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG */ -/* - * DROP_DEST (R/W) - * - * Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0]. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK (0xFFFF0000UL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT (16U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT) - -/* - * MIRROR_TX_EN (R/W) - * - * Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK (0x200U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT (9U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT) - -/* - * MIRROR_RX_EN (R/W) - * - * Incoming frames of this port will be mirrored to the given destination in MIRROR_RX. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK (0x100U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT (8U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT) - -/* - * CT_FPE_OVRD (R/W) - * - * If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK (0x40U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT (6U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT) - -/* - * DISABLE (R/W) - * - * Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK (0x20U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT (5U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT) - -/* - * DROP_ALL (R/W) - * - * Route all frames to DROP_DEST. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK (0x10U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT (4U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT) - -/* - * ERROR_TO_CPU (R/W) - * - * Send error frames to CPU. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK (0x8U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT (3U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT) - -/* - * MIRROR_TO_CPU (R/W) - * - * Duplicate frames to CPU. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK (0x4U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT (2U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) - -/* - * NODROP_ERROR (R/W) - * - * Do not drop frame errors. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK (0x2U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT (1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT) - -/* - * MODE_STORE_FW (R/W) - * - * Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK (0x1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_RESET */ -/* - * SOFTRS (W) - * - * Write 1 to reset FD controller and memory pointers. Register Map content remains untouched - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK (0x1U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM */ -/* - * LU_FIFO_DEPTH (RO) - * - * Number of MAC lookup descriptors the FIFO can store. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK (0xFF000000UL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT (24U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT) - -/* - * FD_DESC_FIFO_DESC (RO) - * - * Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK (0xFF0000UL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT (16U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT) - -/* - * FD_FIFO_DESC (RO) - * - * Number of words (4byte) the Frame Drop FIFO can store. - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK (0xFFFFU) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD */ -/* - * PORT (R/W) - * - * If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK (0x1FFFFFFUL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK */ -/* - * PORT (R/W) - * - * Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports). - * bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK (0x1FFFFFFUL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR */ -/* - * PORT (R/W) - * - * Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port. - * bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK (0x1FFFFFFUL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX */ -/* - * PORT (R/W) - * - * Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic. - * bit 0 - CPU-Port, - * bit 1 - Port 1, … - */ -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK (0x1FFFFFFUL) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT (0U) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK) -#define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_CTRL */ -/* - * EN (R/W) - * - * Enables counter. If deasserted the counter process stops and the counters hold their value. - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK (0x1U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT (0U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK) -#define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_RESET */ -/* - * RSRX (WO) - * - * Write '1' to reset all RX counters. - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK (0x4U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT (2U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT) - -/* - * RSTX (WO) - * - * Write '1' to reset all TX counters - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK (0x2U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT (1U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT) - -/* - * RSALL (WO) - * - * Write '1' to reset all TX&RX counters. - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK (0x1U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT (0U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK) -#define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_PARAM */ -/* - * RX_CNT_EN_VEC (RO) - * - * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK (0xFFFF0000UL) -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT (16U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT) - -/* - * TX_CNT_EN_VEC (RO) - * - * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available. - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK (0xFF00U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT (8U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT) - -/* - * CNTW (RO) - * - * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter - * are available. - */ -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK (0x7FU) -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT (0U) -#define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_FGOOD */ -/* - * TX_FGOOD (RO) - * - * Good transmitted Frames to TX TSN-EP. - */ -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_FERROR */ -/* - * TX_FERROR (RO) - * - * Transmitted Frames with Error to TX TSN-EP. - */ -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_DROP_OVFL */ -/* - * TX_DROP_OVFL (RO) - * - * Dropped frames by full queue of TSN-EP. - */ -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FGOOD */ -/* - * RX_FGOOD (RO) - * - * Good received frame by ingress buffer. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FERROR */ -/* - * RX_FERROR (RO) - * - * Bad received frame by ingress buffer. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_KNOWN */ -/* - * RX_KNOWN (RO) - * - * Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_UNKNOWN */ -/* - * RX_UNKNOWN (RO) - * - * Number of frames passed ingress without hit by MAC table. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_UC */ -/* - * RX_UC (RO) - * - * Number of unicast frames - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_INTERN */ -/* - * RX_INTERN (RO) - * - * Number of non-relay frames - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_BC */ -/* - * RX_BC (RO) - * - * Number of Broadcast frames - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_MULTI */ -/* - * RX_MULTI (RO) - * - * Number of Multicast frames - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_VLAN */ -/* - * RX_VLAN (RO) - * - * Number of VLAN tagged frames - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_OVFL */ -/* - * RX_DROP_OVFL (RO) - * - * Dropped frames by ingress overflow. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_LU */ -/* - * RX_DROP_LU (RO) - * - * Dropped frames by LookUp decision. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_ERR */ -/* - * RX_DROP_ERR (RO) - * - * Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_VLAN */ -/* - * RX_DROP_VLAN (RO) - * - * Dropped frames by incompatible VLAN. - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FPE_FGOOD */ -/* - * RX_FPE_FGOOD (RO) - * - * Number of preemptable frames. Subset of RX_FGOOD - */ -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK (0xFFFFFFFFUL) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT (0U) -#define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: GPR_CTRL0 */ -/* - * RXCLK_DLY_SEL (RW) - * - * delay value of rxclk_delay_chain - */ -#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK (0x3F00U) -#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT (8U) -#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) -#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT) - -/* - * TXCLK_DLY_SEL (RW) - * - * delay value of txclk_delay_chain - */ -#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK (0x3FU) -#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT (0U) -#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) -#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT) - -/* Bitfield definition for register of struct array TSNPORT: GPR_CTRL2 */ -/* - * MAC_SPEED (RW) - * - * mac speed - */ -#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK (0x300000UL) -#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT (20U) -#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) -#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) >> TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT) - -/* - * PAD_OE_ETH_REFCLK (RW) - * - * refclock output enable when rmii - */ -#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK (0x80000UL) -#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT (19U) -#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) -#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) >> TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT) - -/* - * PHY_INTF_SEL (RW) - * - * phy interface select - */ -#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK (0xE000U) -#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT (13U) -#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) -#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT) - -/* - * RMII_TXCLK_SEL (RW) - * - * txclk select control for RMII - */ -#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK (0x400U) -#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT (10U) -#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) -#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT) - - - -/* HITMEM register group index macro definition */ -#define TSW_HITMEM_HITMEM_REG_1 (0UL) -#define TSW_HITMEM_HITMEM_REG_2 (1UL) -#define TSW_HITMEM_HITMEM_REG_3 (2UL) -#define TSW_HITMEM_HITMEM_REG_4 (3UL) - -/* QCI_CNT register group index macro definition */ -#define TSW_QCI_CNT_CENTRAL_QCI_CNT0 (0UL) -#define TSW_QCI_CNT_CENTRAL_QCI_CNT1 (1UL) -#define TSW_QCI_CNT_CENTRAL_QCI_CNT2 (2UL) -#define TSW_QCI_CNT_CENTRAL_QCI_CNT3 (3UL) -#define TSW_QCI_CNT_CENTRAL_QCI_CNT4 (4UL) -#define TSW_QCI_CNT_CENTRAL_QCI_CNT5 (5UL) - -/* EGFRCNT register group index macro definition */ -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT0 (0UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT1 (1UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT2 (2UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT3 (3UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT4 (4UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT5 (5UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT6 (6UL) -#define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT7 (7UL) - -/* IGFRCNT register group index macro definition */ -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT0 (0UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT1 (1UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT2 (2UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT3 (3UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT4 (4UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT5 (5UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT6 (6UL) -#define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT7 (7UL) - -/* MAC register group index macro definition */ -#define TSW_MAC_EM1 (0UL) -#define TSW_MAC_PM1 (1UL) - -/* TSYNTMR register group index macro definition */ -#define TSW_TSNPORT_TSYNTMR_TSYN_TMR0 (0UL) -#define TSW_TSNPORT_TSYNTMR_TSYN_TMR1 (1UL) -#define TSW_TSNPORT_TSYNTMR_TSYN_TMR2 (2UL) -#define TSW_TSNPORT_TSYNTMR_TSYN_TMR3 (3UL) -#define TSW_TSNPORT_TSYNTMR_TSYN_TMR4 (4UL) - -/* RXDATA register group index macro definition */ -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD0 (0UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD1 (1UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD2 (2UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD3 (3UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD4 (4UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD5 (5UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD6 (6UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD7 (7UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD8 (8UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD9 (9UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD10 (10UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD11 (11UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD12 (12UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD13 (13UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD14 (14UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD15 (15UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD16 (16UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD17 (17UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD18 (18UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD19 (19UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD20 (20UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD21 (21UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD22 (22UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD23 (23UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD24 (24UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD25 (25UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD26 (26UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD27 (27UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD28 (28UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD29 (29UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD30 (30UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD31 (31UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD32 (32UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD33 (33UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD34 (34UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD35 (35UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD36 (36UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD37 (37UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD38 (38UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD39 (39UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD40 (40UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD41 (41UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD42 (42UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD43 (43UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD44 (44UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD45 (45UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD46 (46UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD47 (47UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD48 (48UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD49 (49UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD50 (50UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD51 (51UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD52 (52UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD53 (53UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD54 (54UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD55 (55UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD56 (56UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD57 (57UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD58 (58UL) -#define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD59 (59UL) - -/* TXDATA register group index macro definition */ -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD0 (0UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD1 (1UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD2 (2UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD3 (3UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD4 (4UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD5 (5UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD6 (6UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD7 (7UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD8 (8UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD9 (9UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD10 (10UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD11 (11UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD12 (12UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD13 (13UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD14 (14UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD15 (15UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD16 (16UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD17 (17UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD18 (18UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD19 (19UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD20 (20UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD21 (21UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD22 (22UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD23 (23UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD24 (24UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD25 (25UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD26 (26UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD27 (27UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD28 (28UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD29 (29UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD30 (30UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD31 (31UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD32 (32UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD33 (33UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD34 (34UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD35 (35UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD36 (36UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD37 (37UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD38 (38UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD39 (39UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD40 (40UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD41 (41UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD42 (42UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD43 (43UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD44 (44UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD45 (45UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD46 (46UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD47 (47UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD48 (48UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD49 (49UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD50 (50UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD51 (51UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD52 (52UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD53 (53UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD54 (54UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD55 (55UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD56 (56UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD57 (57UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD58 (58UL) -#define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD59 (59UL) - -/* BIN register group index macro definition */ -#define TSW_BIN_TX0 (0UL) -#define TSW_BIN_TX1 (1UL) -#define TSW_BIN_TX2 (2UL) -#define TSW_BIN_TX3 (3UL) -#define TSW_BIN_TX4 (4UL) -#define TSW_BIN_TX5 (5UL) -#define TSW_BIN_TX6 (6UL) -#define TSW_BIN_TX7 (7UL) - -/* MXSDU register group index macro definition */ -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU0 (0UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU1 (1UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU2 (2UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU3 (3UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU4 (4UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU5 (5UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU6 (6UL) -#define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU7 (7UL) - -/* TXSEL register group index macro definition */ -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL0 (0UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL1 (1UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL2 (2UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL3 (3UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL4 (4UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL5 (5UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL6 (6UL) -#define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL7 (7UL) - -/* IDSEL register group index macro definition */ -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL0 (0UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL1 (1UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL2 (2UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL3 (3UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL04 (4UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL5 (5UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL6 (6UL) -#define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL7 (7UL) - -/* MXTK register group index macro definition */ -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK0 (0UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK1 (1UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK2 (2UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK3 (3UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK4 (4UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK5 (5UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK6 (6UL) -#define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK7 (7UL) - -/* TXOV register group index macro definition */ -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV0 (0UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV1 (1UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV2 (2UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV3 (3UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV4 (4UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV5 (5UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV6 (6UL) -#define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV7 (7UL) - -/* SHACL register group index macro definition */ -#define TSW_SHACL_ENT0 (0UL) -#define TSW_SHACL_ENT1 (1UL) -#define TSW_SHACL_ENT2 (2UL) -#define TSW_SHACL_ENT3 (3UL) -#define TSW_SHACL_ENT4 (4UL) -#define TSW_SHACL_ENT5 (5UL) -#define TSW_SHACL_ENT6 (6UL) -#define TSW_SHACL_ENT7 (7UL) -#define TSW_SHACL_ENT8 (8UL) -#define TSW_SHACL_ENT9 (9UL) -#define TSW_SHACL_ENT10 (10UL) -#define TSW_SHACL_ENT11 (11UL) -#define TSW_SHACL_ENT12 (12UL) -#define TSW_SHACL_ENT13 (13UL) -#define TSW_SHACL_ENT14 (14UL) -#define TSW_SHACL_ENT15 (15UL) -#define TSW_SHACL_ENT16 (16UL) -#define TSW_SHACL_ENT17 (17UL) -#define TSW_SHACL_ENT18 (18UL) -#define TSW_SHACL_ENT19 (19UL) -#define TSW_SHACL_ENT20 (20UL) -#define TSW_SHACL_ENT21 (21UL) -#define TSW_SHACL_ENT22 (22UL) -#define TSW_SHACL_ENT23 (23UL) -#define TSW_SHACL_ENT24 (24UL) -#define TSW_SHACL_ENT25 (25UL) -#define TSW_SHACL_ENT26 (26UL) -#define TSW_SHACL_ENT27 (27UL) -#define TSW_SHACL_ENT28 (28UL) -#define TSW_SHACL_ENT29 (29UL) -#define TSW_SHACL_ENT30 (30UL) -#define TSW_SHACL_ENT31 (31UL) -#define TSW_SHACL_ENT32 (32UL) -#define TSW_SHACL_ENT33 (33UL) -#define TSW_SHACL_ENT34 (34UL) -#define TSW_SHACL_ENT35 (35UL) -#define TSW_SHACL_ENT36 (36UL) -#define TSW_SHACL_ENT37 (37UL) -#define TSW_SHACL_ENT38 (38UL) -#define TSW_SHACL_ENT39 (39UL) -#define TSW_SHACL_ENT40 (40UL) -#define TSW_SHACL_ENT41 (41UL) -#define TSW_SHACL_ENT42 (42UL) -#define TSW_SHACL_ENT43 (43UL) -#define TSW_SHACL_ENT44 (44UL) -#define TSW_SHACL_ENT45 (45UL) -#define TSW_SHACL_ENT46 (46UL) -#define TSW_SHACL_ENT47 (47UL) -#define TSW_SHACL_ENT48 (48UL) -#define TSW_SHACL_ENT49 (49UL) -#define TSW_SHACL_ENT50 (50UL) -#define TSW_SHACL_ENT51 (51UL) -#define TSW_SHACL_ENT52 (52UL) -#define TSW_SHACL_ENT53 (53UL) -#define TSW_SHACL_ENT54 (54UL) -#define TSW_SHACL_ENT55 (55UL) -#define TSW_SHACL_ENT56 (56UL) -#define TSW_SHACL_ENT57 (57UL) -#define TSW_SHACL_ENT58 (58UL) -#define TSW_SHACL_ENT59 (59UL) -#define TSW_SHACL_ENT60 (60UL) -#define TSW_SHACL_ENT61 (61UL) -#define TSW_SHACL_ENT62 (62UL) -#define TSW_SHACL_ENT63 (63UL) -#define TSW_SHACL_ENT64 (64UL) -#define TSW_SHACL_ENT65 (65UL) -#define TSW_SHACL_ENT66 (66UL) -#define TSW_SHACL_ENT67 (67UL) -#define TSW_SHACL_ENT68 (68UL) -#define TSW_SHACL_ENT69 (69UL) -#define TSW_SHACL_ENT70 (70UL) -#define TSW_SHACL_ENT71 (71UL) -#define TSW_SHACL_ENT72 (72UL) -#define TSW_SHACL_ENT73 (73UL) -#define TSW_SHACL_ENT74 (74UL) -#define TSW_SHACL_ENT75 (75UL) -#define TSW_SHACL_ENT76 (76UL) -#define TSW_SHACL_ENT77 (77UL) -#define TSW_SHACL_ENT78 (78UL) -#define TSW_SHACL_ENT79 (79UL) -#define TSW_SHACL_ENT80 (80UL) -#define TSW_SHACL_ENT81 (81UL) -#define TSW_SHACL_ENT82 (82UL) -#define TSW_SHACL_ENT83 (83UL) -#define TSW_SHACL_ENT84 (84UL) -#define TSW_SHACL_ENT85 (85UL) -#define TSW_SHACL_ENT86 (86UL) -#define TSW_SHACL_ENT87 (87UL) -#define TSW_SHACL_ENT88 (88UL) -#define TSW_SHACL_ENT89 (89UL) -#define TSW_SHACL_ENT90 (90UL) -#define TSW_SHACL_ENT91 (91UL) -#define TSW_SHACL_ENT92 (92UL) -#define TSW_SHACL_ENT93 (93UL) -#define TSW_SHACL_ENT94 (94UL) -#define TSW_SHACL_ENT95 (95UL) -#define TSW_SHACL_ENT96 (96UL) -#define TSW_SHACL_ENT97 (97UL) -#define TSW_SHACL_ENT98 (98UL) -#define TSW_SHACL_ENT99 (99UL) -#define TSW_SHACL_ENT100 (100UL) -#define TSW_SHACL_ENT101 (101UL) -#define TSW_SHACL_ENT102 (102UL) -#define TSW_SHACL_ENT103 (103UL) -#define TSW_SHACL_ENT104 (104UL) -#define TSW_SHACL_ENT105 (105UL) -#define TSW_SHACL_ENT106 (106UL) -#define TSW_SHACL_ENT107 (107UL) -#define TSW_SHACL_ENT108 (108UL) -#define TSW_SHACL_ENT109 (109UL) -#define TSW_SHACL_ENT110 (110UL) -#define TSW_SHACL_ENT111 (111UL) -#define TSW_SHACL_ENT112 (112UL) -#define TSW_SHACL_ENT113 (113UL) -#define TSW_SHACL_ENT114 (114UL) -#define TSW_SHACL_ENT115 (115UL) -#define TSW_SHACL_ENT116 (116UL) -#define TSW_SHACL_ENT117 (117UL) -#define TSW_SHACL_ENT118 (118UL) -#define TSW_SHACL_ENT119 (119UL) -#define TSW_SHACL_ENT120 (120UL) -#define TSW_SHACL_ENT121 (121UL) -#define TSW_SHACL_ENT122 (122UL) -#define TSW_SHACL_ENT123 (123UL) -#define TSW_SHACL_ENT124 (124UL) -#define TSW_SHACL_ENT125 (125UL) -#define TSW_SHACL_ENT126 (126UL) -#define TSW_SHACL_ENT127 (127UL) -#define TSW_SHACL_ENT128 (128UL) -#define TSW_SHACL_ENT129 (129UL) -#define TSW_SHACL_ENT130 (130UL) -#define TSW_SHACL_ENT131 (131UL) -#define TSW_SHACL_ENT132 (132UL) -#define TSW_SHACL_ENT133 (133UL) -#define TSW_SHACL_ENT134 (134UL) -#define TSW_SHACL_ENT135 (135UL) -#define TSW_SHACL_ENT136 (136UL) -#define TSW_SHACL_ENT137 (137UL) -#define TSW_SHACL_ENT138 (138UL) -#define TSW_SHACL_ENT139 (139UL) -#define TSW_SHACL_ENT140 (140UL) -#define TSW_SHACL_ENT141 (141UL) -#define TSW_SHACL_ENT142 (142UL) -#define TSW_SHACL_ENT143 (143UL) -#define TSW_SHACL_ENT144 (144UL) -#define TSW_SHACL_ENT145 (145UL) -#define TSW_SHACL_ENT146 (146UL) -#define TSW_SHACL_ENT147 (147UL) -#define TSW_SHACL_ENT148 (148UL) -#define TSW_SHACL_ENT149 (149UL) -#define TSW_SHACL_ENT150 (150UL) -#define TSW_SHACL_ENT151 (151UL) -#define TSW_SHACL_ENT152 (152UL) -#define TSW_SHACL_ENT153 (153UL) -#define TSW_SHACL_ENT154 (154UL) -#define TSW_SHACL_ENT155 (155UL) -#define TSW_SHACL_ENT156 (156UL) -#define TSW_SHACL_ENT157 (157UL) -#define TSW_SHACL_ENT158 (158UL) -#define TSW_SHACL_ENT159 (159UL) -#define TSW_SHACL_ENT160 (160UL) -#define TSW_SHACL_ENT161 (161UL) -#define TSW_SHACL_ENT162 (162UL) -#define TSW_SHACL_ENT163 (163UL) -#define TSW_SHACL_ENT164 (164UL) -#define TSW_SHACL_ENT165 (165UL) -#define TSW_SHACL_ENT166 (166UL) -#define TSW_SHACL_ENT167 (167UL) -#define TSW_SHACL_ENT168 (168UL) -#define TSW_SHACL_ENT169 (169UL) -#define TSW_SHACL_ENT170 (170UL) -#define TSW_SHACL_ENT171 (171UL) -#define TSW_SHACL_ENT172 (172UL) -#define TSW_SHACL_ENT173 (173UL) -#define TSW_SHACL_ENT174 (174UL) -#define TSW_SHACL_ENT175 (175UL) -#define TSW_SHACL_ENT176 (176UL) -#define TSW_SHACL_ENT177 (177UL) -#define TSW_SHACL_ENT178 (178UL) -#define TSW_SHACL_ENT179 (179UL) -#define TSW_SHACL_ENT180 (180UL) -#define TSW_SHACL_ENT181 (181UL) -#define TSW_SHACL_ENT182 (182UL) -#define TSW_SHACL_ENT183 (183UL) -#define TSW_SHACL_ENT184 (184UL) -#define TSW_SHACL_ENT185 (185UL) -#define TSW_SHACL_ENT186 (186UL) -#define TSW_SHACL_ENT187 (187UL) -#define TSW_SHACL_ENT188 (188UL) -#define TSW_SHACL_ENT189 (189UL) -#define TSW_SHACL_ENT190 (190UL) -#define TSW_SHACL_ENT191 (191UL) -#define TSW_SHACL_ENT192 (192UL) -#define TSW_SHACL_ENT193 (193UL) -#define TSW_SHACL_ENT194 (194UL) -#define TSW_SHACL_ENT195 (195UL) -#define TSW_SHACL_ENT196 (196UL) -#define TSW_SHACL_ENT197 (197UL) -#define TSW_SHACL_ENT198 (198UL) -#define TSW_SHACL_ENT199 (199UL) -#define TSW_SHACL_ENT200 (200UL) -#define TSW_SHACL_ENT201 (201UL) -#define TSW_SHACL_ENT202 (202UL) -#define TSW_SHACL_ENT203 (203UL) -#define TSW_SHACL_ENT204 (204UL) -#define TSW_SHACL_ENT205 (205UL) -#define TSW_SHACL_ENT206 (206UL) -#define TSW_SHACL_ENT207 (207UL) -#define TSW_SHACL_ENT208 (208UL) -#define TSW_SHACL_ENT209 (209UL) -#define TSW_SHACL_ENT210 (210UL) -#define TSW_SHACL_ENT211 (211UL) -#define TSW_SHACL_ENT212 (212UL) -#define TSW_SHACL_ENT213 (213UL) -#define TSW_SHACL_ENT214 (214UL) -#define TSW_SHACL_ENT215 (215UL) -#define TSW_SHACL_ENT216 (216UL) -#define TSW_SHACL_ENT217 (217UL) -#define TSW_SHACL_ENT218 (218UL) -#define TSW_SHACL_ENT219 (219UL) -#define TSW_SHACL_ENT220 (220UL) -#define TSW_SHACL_ENT221 (221UL) -#define TSW_SHACL_ENT222 (222UL) -#define TSW_SHACL_ENT223 (223UL) -#define TSW_SHACL_ENT224 (224UL) -#define TSW_SHACL_ENT225 (225UL) -#define TSW_SHACL_ENT226 (226UL) -#define TSW_SHACL_ENT227 (227UL) -#define TSW_SHACL_ENT228 (228UL) -#define TSW_SHACL_ENT229 (229UL) -#define TSW_SHACL_ENT230 (230UL) -#define TSW_SHACL_ENT231 (231UL) -#define TSW_SHACL_ENT232 (232UL) -#define TSW_SHACL_ENT233 (233UL) -#define TSW_SHACL_ENT234 (234UL) -#define TSW_SHACL_ENT235 (235UL) -#define TSW_SHACL_ENT236 (236UL) -#define TSW_SHACL_ENT237 (237UL) -#define TSW_SHACL_ENT238 (238UL) -#define TSW_SHACL_ENT239 (239UL) -#define TSW_SHACL_ENT240 (240UL) -#define TSW_SHACL_ENT241 (241UL) -#define TSW_SHACL_ENT242 (242UL) -#define TSW_SHACL_ENT243 (243UL) -#define TSW_SHACL_ENT244 (244UL) -#define TSW_SHACL_ENT245 (245UL) -#define TSW_SHACL_ENT246 (246UL) -#define TSW_SHACL_ENT247 (247UL) -#define TSW_SHACL_ENT248 (248UL) -#define TSW_SHACL_ENT249 (249UL) -#define TSW_SHACL_ENT250 (250UL) -#define TSW_SHACL_ENT251 (251UL) -#define TSW_SHACL_ENT252 (252UL) -#define TSW_SHACL_ENT253 (253UL) -#define TSW_SHACL_ENT254 (254UL) -#define TSW_SHACL_ENT255 (255UL) - -/* RXFIFO register group index macro definition */ -#define TSW_RXFIFO_E1 (0UL) -#define TSW_RXFIFO_P1 (1UL) - -/* TSNPORT register group index macro definition */ -#define TSW_TSNPORT_PORT1 (0UL) -#define TSW_TSNPORT_PORT2 (1UL) -#define TSW_TSNPORT_PORT3 (2UL) - - -#endif /* HPM_TSW_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_uart_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_uart_regs.h deleted file mode 100644 index c64a4ba9f69..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_uart_regs.h +++ /dev/null @@ -1,1044 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_UART_H -#define HPM_UART_H - -typedef struct { - __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */ - __RW uint32_t IDLE_CFG; /* 0x4: Idle Configuration Register */ - __RW uint32_t ADDR_CFG; /* 0x8: address match config register */ - __RW uint32_t IIR2; /* 0xC: Interrupt Identification Register2 */ - __RW uint32_t CFG; /* 0x10: Configuration Register */ - __RW uint32_t OSCR; /* 0x14: Over Sample Control Register */ - __RW uint32_t FCRR; /* 0x18: FIFO Control Register config */ - __RW uint32_t MOTO_CFG; /* 0x1C: moto system control register */ - union { - __R uint32_t RBR; /* 0x20: Receiver Buffer Register (when DLAB = 0) */ - __W uint32_t THR; /* 0x20: Transmitter Holding Register (when DLAB = 0) */ - __RW uint32_t DLL; /* 0x20: Divisor Latch LSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IER; /* 0x24: Interrupt Enable Register (when DLAB = 0) */ - __RW uint32_t DLM; /* 0x24: Divisor Latch MSB (when DLAB = 1) */ - }; - union { - __RW uint32_t IIR; /* 0x28: Interrupt Identification Register */ - __W uint32_t FCR; /* 0x28: FIFO Control Register */ - }; - __RW uint32_t LCR; /* 0x2C: Line Control Register */ - __RW uint32_t MCR; /* 0x30: Modem Control Register ( */ - __R uint32_t LSR; /* 0x34: Line Status Register */ - __R uint32_t MSR; /* 0x38: Modem Status Register */ - __RW uint32_t GPR; /* 0x3C: GPR Register */ -} UART_Type; - - -/* Bitfield definition for register: IDLE_CFG */ -/* - * TX_IDLE_COND (RW) - * - * IDLE Detection Condition - * 0 - Treat as idle if TX pin is logic one - * 1 - Treat as idle if UART state machine state is idle - */ -#define UART_IDLE_CFG_TX_IDLE_COND_MASK (0x2000000UL) -#define UART_IDLE_CFG_TX_IDLE_COND_SHIFT (25U) -#define UART_IDLE_CFG_TX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_COND_SHIFT) & UART_IDLE_CFG_TX_IDLE_COND_MASK) -#define UART_IDLE_CFG_TX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_COND_MASK) >> UART_IDLE_CFG_TX_IDLE_COND_SHIFT) - -/* - * TX_IDLE_EN (RW) - * - * UART TX Idle Detect Enable - * 0 - Disable - * 1 - Enable - */ -#define UART_IDLE_CFG_TX_IDLE_EN_MASK (0x1000000UL) -#define UART_IDLE_CFG_TX_IDLE_EN_SHIFT (24U) -#define UART_IDLE_CFG_TX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_EN_SHIFT) & UART_IDLE_CFG_TX_IDLE_EN_MASK) -#define UART_IDLE_CFG_TX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_EN_MASK) >> UART_IDLE_CFG_TX_IDLE_EN_SHIFT) - -/* - * TX_IDLE_THR (RW) - * - * Threshold for UART transmit Idle detection (in terms of bits) - */ -#define UART_IDLE_CFG_TX_IDLE_THR_MASK (0xFF0000UL) -#define UART_IDLE_CFG_TX_IDLE_THR_SHIFT (16U) -#define UART_IDLE_CFG_TX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_TX_IDLE_THR_SHIFT) & UART_IDLE_CFG_TX_IDLE_THR_MASK) -#define UART_IDLE_CFG_TX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_TX_IDLE_THR_MASK) >> UART_IDLE_CFG_TX_IDLE_THR_SHIFT) - -/* - * RXEN (RW) - * - * UART receive enable. - * 0 - hold RX input to high, avoide wrong data input when config pinmux - * 1 - bypass RX input from PIN - * software should set it after config pinmux - */ -#define UART_IDLE_CFG_RXEN_MASK (0x800U) -#define UART_IDLE_CFG_RXEN_SHIFT (11U) -#define UART_IDLE_CFG_RXEN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RXEN_SHIFT) & UART_IDLE_CFG_RXEN_MASK) -#define UART_IDLE_CFG_RXEN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RXEN_MASK) >> UART_IDLE_CFG_RXEN_SHIFT) - -/* - * RX_IDLE_COND (RW) - * - * IDLE Detection Condition - * 0 - Treat as idle if RX pin is logic one - * 1 - Treat as idle if UART state machine state is idle - */ -#define UART_IDLE_CFG_RX_IDLE_COND_MASK (0x200U) -#define UART_IDLE_CFG_RX_IDLE_COND_SHIFT (9U) -#define UART_IDLE_CFG_RX_IDLE_COND_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_COND_SHIFT) & UART_IDLE_CFG_RX_IDLE_COND_MASK) -#define UART_IDLE_CFG_RX_IDLE_COND_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_COND_MASK) >> UART_IDLE_CFG_RX_IDLE_COND_SHIFT) - -/* - * RX_IDLE_EN (RW) - * - * UART Idle Detect Enable - * 0 - Disable - * 1 - Enable - * it should be enabled if enable address match feature - */ -#define UART_IDLE_CFG_RX_IDLE_EN_MASK (0x100U) -#define UART_IDLE_CFG_RX_IDLE_EN_SHIFT (8U) -#define UART_IDLE_CFG_RX_IDLE_EN_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_EN_SHIFT) & UART_IDLE_CFG_RX_IDLE_EN_MASK) -#define UART_IDLE_CFG_RX_IDLE_EN_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_EN_MASK) >> UART_IDLE_CFG_RX_IDLE_EN_SHIFT) - -/* - * RX_IDLE_THR (RW) - * - * Threshold for UART Receive Idle detection (in terms of bits) - */ -#define UART_IDLE_CFG_RX_IDLE_THR_MASK (0xFFU) -#define UART_IDLE_CFG_RX_IDLE_THR_SHIFT (0U) -#define UART_IDLE_CFG_RX_IDLE_THR_SET(x) (((uint32_t)(x) << UART_IDLE_CFG_RX_IDLE_THR_SHIFT) & UART_IDLE_CFG_RX_IDLE_THR_MASK) -#define UART_IDLE_CFG_RX_IDLE_THR_GET(x) (((uint32_t)(x) & UART_IDLE_CFG_RX_IDLE_THR_MASK) >> UART_IDLE_CFG_RX_IDLE_THR_SHIFT) - -/* Bitfield definition for register: ADDR_CFG */ -/* - * TXEN_9BIT (RW) - * - * set to use 9bit mode for transmitter, - * will set the MSB for the first character as address flag, keep 0 for others. - */ -#define UART_ADDR_CFG_TXEN_9BIT_MASK (0x100000UL) -#define UART_ADDR_CFG_TXEN_9BIT_SHIFT (20U) -#define UART_ADDR_CFG_TXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_TXEN_9BIT_SHIFT) & UART_ADDR_CFG_TXEN_9BIT_MASK) -#define UART_ADDR_CFG_TXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_TXEN_9BIT_MASK) >> UART_ADDR_CFG_TXEN_9BIT_SHIFT) - -/* - * RXEN_ADDR_MSB (RW) - * - * set to use MSB as address flag at receiver(actually this is done by software set correct MSB in addr0/addr1). - * Clr to use first character as address. - * Only needed if enable address match feature - */ -#define UART_ADDR_CFG_RXEN_ADDR_MSB_MASK (0x80000UL) -#define UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT (19U) -#define UART_ADDR_CFG_RXEN_ADDR_MSB_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) -#define UART_ADDR_CFG_RXEN_ADDR_MSB_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_ADDR_MSB_MASK) >> UART_ADDR_CFG_RXEN_ADDR_MSB_SHIFT) - -/* - * RXEN_9BIT (RW) - * - * set to use 9bit mode for receiver, only valid if rxen_addr_msb is set - */ -#define UART_ADDR_CFG_RXEN_9BIT_MASK (0x40000UL) -#define UART_ADDR_CFG_RXEN_9BIT_SHIFT (18U) -#define UART_ADDR_CFG_RXEN_9BIT_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_RXEN_9BIT_SHIFT) & UART_ADDR_CFG_RXEN_9BIT_MASK) -#define UART_ADDR_CFG_RXEN_9BIT_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_RXEN_9BIT_MASK) >> UART_ADDR_CFG_RXEN_9BIT_SHIFT) - -/* - * A1_EN (RW) - * - * enable addr1 compare for the first character. - * If a1_en OR a0_en, then do not receive data if address not match. - * If ~a1_en AND ~a0_en, the receive all data like before. - * NOTE: should set idle_tmout_en if enable address match feature - */ -#define UART_ADDR_CFG_A1_EN_MASK (0x20000UL) -#define UART_ADDR_CFG_A1_EN_SHIFT (17U) -#define UART_ADDR_CFG_A1_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A1_EN_SHIFT) & UART_ADDR_CFG_A1_EN_MASK) -#define UART_ADDR_CFG_A1_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A1_EN_MASK) >> UART_ADDR_CFG_A1_EN_SHIFT) - -/* - * A0_EN (RW) - * - * enable addr0 compare for the first character - */ -#define UART_ADDR_CFG_A0_EN_MASK (0x10000UL) -#define UART_ADDR_CFG_A0_EN_SHIFT (16U) -#define UART_ADDR_CFG_A0_EN_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_A0_EN_SHIFT) & UART_ADDR_CFG_A0_EN_MASK) -#define UART_ADDR_CFG_A0_EN_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_A0_EN_MASK) >> UART_ADDR_CFG_A0_EN_SHIFT) - -/* - * ADDR1 (RW) - * - * address 1 fileld. - * in 9bit mode, this is the full address byte. - * For other mode(8/7/6/5bit), MSB should be set for address flag. - * If want address==0 to be matched at 8bit mode, should set addr1=0x80 - */ -#define UART_ADDR_CFG_ADDR1_MASK (0xFF00U) -#define UART_ADDR_CFG_ADDR1_SHIFT (8U) -#define UART_ADDR_CFG_ADDR1_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR1_SHIFT) & UART_ADDR_CFG_ADDR1_MASK) -#define UART_ADDR_CFG_ADDR1_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR1_MASK) >> UART_ADDR_CFG_ADDR1_SHIFT) - -/* - * ADDR0 (RW) - * - * address 0 field. - */ -#define UART_ADDR_CFG_ADDR0_MASK (0xFFU) -#define UART_ADDR_CFG_ADDR0_SHIFT (0U) -#define UART_ADDR_CFG_ADDR0_SET(x) (((uint32_t)(x) << UART_ADDR_CFG_ADDR0_SHIFT) & UART_ADDR_CFG_ADDR0_MASK) -#define UART_ADDR_CFG_ADDR0_GET(x) (((uint32_t)(x) & UART_ADDR_CFG_ADDR0_MASK) >> UART_ADDR_CFG_ADDR0_SHIFT) - -/* Bitfield definition for register: IIR2 */ -/* - * RXIDLE_FLAG (W1C) - * - * UART RX IDLE Flag, assert after rxd high and then rx idle timeout, write one clear - * 0 - UART RX is busy - * 1 - UART RX is idle - */ -#define UART_IIR2_RXIDLE_FLAG_MASK (0x80000000UL) -#define UART_IIR2_RXIDLE_FLAG_SHIFT (31U) -#define UART_IIR2_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_RXIDLE_FLAG_SHIFT) & UART_IIR2_RXIDLE_FLAG_MASK) -#define UART_IIR2_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_RXIDLE_FLAG_MASK) >> UART_IIR2_RXIDLE_FLAG_SHIFT) - -/* - * TXIDLE_FLAG (W1C) - * - * UART TX IDLE Flag, assert after txd high and then tx idle timeout, write one clear - * 0 - UART TX is busy - * 1 - UART TX is idle - */ -#define UART_IIR2_TXIDLE_FLAG_MASK (0x40000000UL) -#define UART_IIR2_TXIDLE_FLAG_SHIFT (30U) -#define UART_IIR2_TXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR2_TXIDLE_FLAG_SHIFT) & UART_IIR2_TXIDLE_FLAG_MASK) -#define UART_IIR2_TXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR2_TXIDLE_FLAG_MASK) >> UART_IIR2_TXIDLE_FLAG_SHIFT) - -/* - * ADDR_MATCH (W1C) - * - * address match irq status, assert if either address match(and enabled). Write one clear - * NOTE: the address byte may not moved by DMA at this point. - * User can wait next addr_match_idle irq for the whole data include address - */ -#define UART_IIR2_ADDR_MATCH_MASK (0x20000000UL) -#define UART_IIR2_ADDR_MATCH_SHIFT (29U) -#define UART_IIR2_ADDR_MATCH_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_SHIFT) & UART_IIR2_ADDR_MATCH_MASK) -#define UART_IIR2_ADDR_MATCH_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_MASK) >> UART_IIR2_ADDR_MATCH_SHIFT) - -/* - * ADDR_MATCH_IDLE (W1C) - * - * address match and idle irq status, assert at rx bus idle if address match event triggered. - * Write one clear; - */ -#define UART_IIR2_ADDR_MATCH_IDLE_MASK (0x10000000UL) -#define UART_IIR2_ADDR_MATCH_IDLE_SHIFT (28U) -#define UART_IIR2_ADDR_MATCH_IDLE_SET(x) (((uint32_t)(x) << UART_IIR2_ADDR_MATCH_IDLE_SHIFT) & UART_IIR2_ADDR_MATCH_IDLE_MASK) -#define UART_IIR2_ADDR_MATCH_IDLE_GET(x) (((uint32_t)(x) & UART_IIR2_ADDR_MATCH_IDLE_MASK) >> UART_IIR2_ADDR_MATCH_IDLE_SHIFT) - -/* - * DATA_LOST (W1C) - * - * assert if data lost before address match status, write one clear; - * It will not assert if no address match occurs - */ -#define UART_IIR2_DATA_LOST_MASK (0x8000000UL) -#define UART_IIR2_DATA_LOST_SHIFT (27U) -#define UART_IIR2_DATA_LOST_SET(x) (((uint32_t)(x) << UART_IIR2_DATA_LOST_SHIFT) & UART_IIR2_DATA_LOST_MASK) -#define UART_IIR2_DATA_LOST_GET(x) (((uint32_t)(x) & UART_IIR2_DATA_LOST_MASK) >> UART_IIR2_DATA_LOST_SHIFT) - -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR2_FIFOED_MASK (0xC0U) -#define UART_IIR2_FIFOED_SHIFT (6U) -#define UART_IIR2_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR2_FIFOED_MASK) >> UART_IIR2_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR2_INTRID_MASK (0xFU) -#define UART_IIR2_INTRID_SHIFT (0U) -#define UART_IIR2_INTRID_GET(x) (((uint32_t)(x) & UART_IIR2_INTRID_MASK) >> UART_IIR2_INTRID_SHIFT) - -/* Bitfield definition for register: CFG */ -/* - * FIFOSIZE (RO) - * - * The depth of RXFIFO and TXFIFO - * 0: 16-byte FIFO - * 1: 32-byte FIFO - * 2: 64-byte FIFO - * 3: 128-byte FIFO - */ -#define UART_CFG_FIFOSIZE_MASK (0x3U) -#define UART_CFG_FIFOSIZE_SHIFT (0U) -#define UART_CFG_FIFOSIZE_GET(x) (((uint32_t)(x) & UART_CFG_FIFOSIZE_MASK) >> UART_CFG_FIFOSIZE_SHIFT) - -/* Bitfield definition for register: OSCR */ -/* - * OSC (RW) - * - * Over-sample control - * The value must be an even number; any odd value - * writes to this field will be converted to an even value. - * OSC=0: reserved - * OSC<=8: The over-sample ratio is 8 - * 8 < OSC< 32: The over sample ratio is OSC - */ -#define UART_OSCR_OSC_MASK (0x1FU) -#define UART_OSCR_OSC_SHIFT (0U) -#define UART_OSCR_OSC_SET(x) (((uint32_t)(x) << UART_OSCR_OSC_SHIFT) & UART_OSCR_OSC_MASK) -#define UART_OSCR_OSC_GET(x) (((uint32_t)(x) & UART_OSCR_OSC_MASK) >> UART_OSCR_OSC_SHIFT) - -/* Bitfield definition for register: FCRR */ -/* - * FIFOT4EN (RW) - * - * set to use new 4bit fifo threshold(TFIFOT4 and RFIFOT4) - * clr to use 2bit(TFIFOT and RFIFOT) - */ -#define UART_FCRR_FIFOT4EN_MASK (0x800000UL) -#define UART_FCRR_FIFOT4EN_SHIFT (23U) -#define UART_FCRR_FIFOT4EN_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOT4EN_SHIFT) & UART_FCRR_FIFOT4EN_MASK) -#define UART_FCRR_FIFOT4EN_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOT4EN_MASK) >> UART_FCRR_FIFOT4EN_SHIFT) - -/* - * TFIFOT4 (RW) - * - * txfifo threshold(0 for 1byte, 0xF for 16bytes), uart will send tx_dma_req when data in fifo is less than threshold. - */ -#define UART_FCRR_TFIFOT4_MASK (0xF0000UL) -#define UART_FCRR_TFIFOT4_SHIFT (16U) -#define UART_FCRR_TFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT4_SHIFT) & UART_FCRR_TFIFOT4_MASK) -#define UART_FCRR_TFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT4_MASK) >> UART_FCRR_TFIFOT4_SHIFT) - -/* - * RFIFOT4 (RW) - * - * rxfifo threshold(0 for 1byte, 0xF for 16bytes). - * Uart will send rx_dma_req if data in fifo reachs the threshold, also will set the rxdata irq if enabled - */ -#define UART_FCRR_RFIFOT4_MASK (0xF00U) -#define UART_FCRR_RFIFOT4_SHIFT (8U) -#define UART_FCRR_RFIFOT4_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT4_SHIFT) & UART_FCRR_RFIFOT4_MASK) -#define UART_FCRR_RFIFOT4_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT4_MASK) >> UART_FCRR_RFIFOT4_SHIFT) - -/* - * RFIFOT (RW) - * - * Receiver FIFO trigger level - */ -#define UART_FCRR_RFIFOT_MASK (0xC0U) -#define UART_FCRR_RFIFOT_SHIFT (6U) -#define UART_FCRR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFOT_SHIFT) & UART_FCRR_RFIFOT_MASK) -#define UART_FCRR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFOT_MASK) >> UART_FCRR_RFIFOT_SHIFT) - -/* - * TFIFOT (RW) - * - * Transmitter FIFO trigger level - */ -#define UART_FCRR_TFIFOT_MASK (0x30U) -#define UART_FCRR_TFIFOT_SHIFT (4U) -#define UART_FCRR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFOT_SHIFT) & UART_FCRR_TFIFOT_MASK) -#define UART_FCRR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFOT_MASK) >> UART_FCRR_TFIFOT_SHIFT) - -/* - * DMAE (RW) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCRR_DMAE_MASK (0x8U) -#define UART_FCRR_DMAE_SHIFT (3U) -#define UART_FCRR_DMAE_SET(x) (((uint32_t)(x) << UART_FCRR_DMAE_SHIFT) & UART_FCRR_DMAE_MASK) -#define UART_FCRR_DMAE_GET(x) (((uint32_t)(x) & UART_FCRR_DMAE_MASK) >> UART_FCRR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCRR_TFIFORST_MASK (0x4U) -#define UART_FCRR_TFIFORST_SHIFT (2U) -#define UART_FCRR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_TFIFORST_SHIFT) & UART_FCRR_TFIFORST_MASK) -#define UART_FCRR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_TFIFORST_MASK) >> UART_FCRR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCRR_RFIFORST_MASK (0x2U) -#define UART_FCRR_RFIFORST_SHIFT (1U) -#define UART_FCRR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCRR_RFIFORST_SHIFT) & UART_FCRR_RFIFORST_MASK) -#define UART_FCRR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCRR_RFIFORST_MASK) >> UART_FCRR_RFIFORST_SHIFT) - -/* - * FIFOE (RW) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCRR_FIFOE_MASK (0x1U) -#define UART_FCRR_FIFOE_SHIFT (0U) -#define UART_FCRR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCRR_FIFOE_SHIFT) & UART_FCRR_FIFOE_MASK) -#define UART_FCRR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCRR_FIFOE_MASK) >> UART_FCRR_FIFOE_SHIFT) - -/* Bitfield definition for register: MOTO_CFG */ -/* - * SWTRG (WO) - * - * software trigger. User should avoid use sw/hw trigger at same time, otherwise result unknown. - * Hardware auto reset. - */ -#define UART_MOTO_CFG_SWTRG_MASK (0x80000000UL) -#define UART_MOTO_CFG_SWTRG_SHIFT (31U) -#define UART_MOTO_CFG_SWTRG_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_SWTRG_SHIFT) & UART_MOTO_CFG_SWTRG_MASK) -#define UART_MOTO_CFG_SWTRG_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_SWTRG_MASK) >> UART_MOTO_CFG_SWTRG_SHIFT) - -/* - * TXSTP_BITS (RW) - * - * if TXSTOP_INSERT is enabled, the STOP bits to be inserted between each byte. 0 for 1 bit; 0xFF for 256bits - */ -#define UART_MOTO_CFG_TXSTP_BITS_MASK (0xFF00U) -#define UART_MOTO_CFG_TXSTP_BITS_SHIFT (8U) -#define UART_MOTO_CFG_TXSTP_BITS_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTP_BITS_SHIFT) & UART_MOTO_CFG_TXSTP_BITS_MASK) -#define UART_MOTO_CFG_TXSTP_BITS_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTP_BITS_MASK) >> UART_MOTO_CFG_TXSTP_BITS_SHIFT) - -/* - * HWTRG_EN (RW) - * - * set to enable hardware trigger(trigger from moto is shared by other UART) - */ -#define UART_MOTO_CFG_HWTRG_EN_MASK (0x80U) -#define UART_MOTO_CFG_HWTRG_EN_SHIFT (7U) -#define UART_MOTO_CFG_HWTRG_EN_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_HWTRG_EN_SHIFT) & UART_MOTO_CFG_HWTRG_EN_MASK) -#define UART_MOTO_CFG_HWTRG_EN_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_HWTRG_EN_MASK) >> UART_MOTO_CFG_HWTRG_EN_SHIFT) - -/* - * TRG_MODE (RW) - * - * set to enable trigger mode. - * software should push needed data into txbuffer frist, uart will not start transmission at this time. - * User should send trigger signal(by hw or sw), uart will send all data in txfifo till empty - * NOTE: the hw_trigger should be pulse signal from trig mux. - */ -#define UART_MOTO_CFG_TRG_MODE_MASK (0x40U) -#define UART_MOTO_CFG_TRG_MODE_SHIFT (6U) -#define UART_MOTO_CFG_TRG_MODE_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_MODE_SHIFT) & UART_MOTO_CFG_TRG_MODE_MASK) -#define UART_MOTO_CFG_TRG_MODE_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_MODE_MASK) >> UART_MOTO_CFG_TRG_MODE_SHIFT) - -/* - * TRG_CLR_RFIFO (RW) - * - * set to enable the feature that, clear rxfifo at tx trigger(sw or hw), avoid unexpected data in rxfifo. - */ -#define UART_MOTO_CFG_TRG_CLR_RFIFO_MASK (0x20U) -#define UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT (5U) -#define UART_MOTO_CFG_TRG_CLR_RFIFO_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) -#define UART_MOTO_CFG_TRG_CLR_RFIFO_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TRG_CLR_RFIFO_MASK) >> UART_MOTO_CFG_TRG_CLR_RFIFO_SHIFT) - -/* - * TXSTOP_INSERT (RW) - * - * set to insert STOP bits between each tx byte till tx fifo empty. - * NOTE: there will be no 1.5/2 STOP bits if enabled this feature, LCR.STB should be set to 0 if this bit is set - */ -#define UART_MOTO_CFG_TXSTOP_INSERT_MASK (0x10U) -#define UART_MOTO_CFG_TXSTOP_INSERT_SHIFT (4U) -#define UART_MOTO_CFG_TXSTOP_INSERT_SET(x) (((uint32_t)(x) << UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) -#define UART_MOTO_CFG_TXSTOP_INSERT_GET(x) (((uint32_t)(x) & UART_MOTO_CFG_TXSTOP_INSERT_MASK) >> UART_MOTO_CFG_TXSTOP_INSERT_SHIFT) - -/* Bitfield definition for register: RBR */ -/* - * RBR (RO) - * - * Receive data read port - */ -#define UART_RBR_RBR_MASK (0xFFU) -#define UART_RBR_RBR_SHIFT (0U) -#define UART_RBR_RBR_GET(x) (((uint32_t)(x) & UART_RBR_RBR_MASK) >> UART_RBR_RBR_SHIFT) - -/* Bitfield definition for register: THR */ -/* - * THR (WO) - * - * Transmit data write port - */ -#define UART_THR_THR_MASK (0xFFU) -#define UART_THR_THR_SHIFT (0U) -#define UART_THR_THR_SET(x) (((uint32_t)(x) << UART_THR_THR_SHIFT) & UART_THR_THR_MASK) -#define UART_THR_THR_GET(x) (((uint32_t)(x) & UART_THR_THR_MASK) >> UART_THR_THR_SHIFT) - -/* Bitfield definition for register: DLL */ -/* - * DLL (RW) - * - * Least significant byte of the Divisor Latch - */ -#define UART_DLL_DLL_MASK (0xFFU) -#define UART_DLL_DLL_SHIFT (0U) -#define UART_DLL_DLL_SET(x) (((uint32_t)(x) << UART_DLL_DLL_SHIFT) & UART_DLL_DLL_MASK) -#define UART_DLL_DLL_GET(x) (((uint32_t)(x) & UART_DLL_DLL_MASK) >> UART_DLL_DLL_SHIFT) - -/* Bitfield definition for register: IER */ -/* - * ERXIDLE (RW) - * - * Enable Receive Idle interrupt - * 0 - Disable Idle interrupt - * 1 - Enable Idle interrupt - */ -#define UART_IER_ERXIDLE_MASK (0x80000000UL) -#define UART_IER_ERXIDLE_SHIFT (31U) -#define UART_IER_ERXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ERXIDLE_SHIFT) & UART_IER_ERXIDLE_MASK) -#define UART_IER_ERXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ERXIDLE_MASK) >> UART_IER_ERXIDLE_SHIFT) - -/* - * ETXIDLE (RW) - * - * enable transmit idle interrupt - */ -#define UART_IER_ETXIDLE_MASK (0x40000000UL) -#define UART_IER_ETXIDLE_SHIFT (30U) -#define UART_IER_ETXIDLE_SET(x) (((uint32_t)(x) << UART_IER_ETXIDLE_SHIFT) & UART_IER_ETXIDLE_MASK) -#define UART_IER_ETXIDLE_GET(x) (((uint32_t)(x) & UART_IER_ETXIDLE_MASK) >> UART_IER_ETXIDLE_SHIFT) - -/* - * EADDRM (RW) - * - * enable ADDR_MATCH interrupt - */ -#define UART_IER_EADDRM_MASK (0x20000000UL) -#define UART_IER_EADDRM_SHIFT (29U) -#define UART_IER_EADDRM_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_SHIFT) & UART_IER_EADDRM_MASK) -#define UART_IER_EADDRM_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_MASK) >> UART_IER_EADDRM_SHIFT) - -/* - * EADDRM_IDLE (RW) - * - * enable ADDR_MATCH_IDLE interrupt - */ -#define UART_IER_EADDRM_IDLE_MASK (0x10000000UL) -#define UART_IER_EADDRM_IDLE_SHIFT (28U) -#define UART_IER_EADDRM_IDLE_SET(x) (((uint32_t)(x) << UART_IER_EADDRM_IDLE_SHIFT) & UART_IER_EADDRM_IDLE_MASK) -#define UART_IER_EADDRM_IDLE_GET(x) (((uint32_t)(x) & UART_IER_EADDRM_IDLE_MASK) >> UART_IER_EADDRM_IDLE_SHIFT) - -/* - * EDATLOST (RW) - * - * enable DATA_LOST interrupt - */ -#define UART_IER_EDATLOST_MASK (0x8000000UL) -#define UART_IER_EDATLOST_SHIFT (27U) -#define UART_IER_EDATLOST_SET(x) (((uint32_t)(x) << UART_IER_EDATLOST_SHIFT) & UART_IER_EDATLOST_MASK) -#define UART_IER_EDATLOST_GET(x) (((uint32_t)(x) & UART_IER_EDATLOST_MASK) >> UART_IER_EDATLOST_SHIFT) - -/* - * EMSI (RW) - * - * Enable modem status interrupt - * The interrupt asserts when the status of one of the - * following occurs: - * The status of modem_rin, modem_dcdn, - * modem_dsrn or modem_ctsn (If the auto-cts mode is - * disabled) has been changed. - * If the auto-cts mode is enabled (MCR bit4 (AFE) = 1), - * modem_ctsn would be used to control the transmitter. - */ -#define UART_IER_EMSI_MASK (0x8U) -#define UART_IER_EMSI_SHIFT (3U) -#define UART_IER_EMSI_SET(x) (((uint32_t)(x) << UART_IER_EMSI_SHIFT) & UART_IER_EMSI_MASK) -#define UART_IER_EMSI_GET(x) (((uint32_t)(x) & UART_IER_EMSI_MASK) >> UART_IER_EMSI_SHIFT) - -/* - * ELSI (RW) - * - * Enable receiver line status interrupt - */ -#define UART_IER_ELSI_MASK (0x4U) -#define UART_IER_ELSI_SHIFT (2U) -#define UART_IER_ELSI_SET(x) (((uint32_t)(x) << UART_IER_ELSI_SHIFT) & UART_IER_ELSI_MASK) -#define UART_IER_ELSI_GET(x) (((uint32_t)(x) & UART_IER_ELSI_MASK) >> UART_IER_ELSI_SHIFT) - -/* - * ETHEI (RW) - * - * Enable transmitter holding register interrupt - */ -#define UART_IER_ETHEI_MASK (0x2U) -#define UART_IER_ETHEI_SHIFT (1U) -#define UART_IER_ETHEI_SET(x) (((uint32_t)(x) << UART_IER_ETHEI_SHIFT) & UART_IER_ETHEI_MASK) -#define UART_IER_ETHEI_GET(x) (((uint32_t)(x) & UART_IER_ETHEI_MASK) >> UART_IER_ETHEI_SHIFT) - -/* - * ERBI (RW) - * - * Enable received data available interrupt and the - * character timeout interrupt - * 0: Disable - * 1: Enable - */ -#define UART_IER_ERBI_MASK (0x1U) -#define UART_IER_ERBI_SHIFT (0U) -#define UART_IER_ERBI_SET(x) (((uint32_t)(x) << UART_IER_ERBI_SHIFT) & UART_IER_ERBI_MASK) -#define UART_IER_ERBI_GET(x) (((uint32_t)(x) & UART_IER_ERBI_MASK) >> UART_IER_ERBI_SHIFT) - -/* Bitfield definition for register: DLM */ -/* - * DLM (RW) - * - * Most significant byte of the Divisor Latch - */ -#define UART_DLM_DLM_MASK (0xFFU) -#define UART_DLM_DLM_SHIFT (0U) -#define UART_DLM_DLM_SET(x) (((uint32_t)(x) << UART_DLM_DLM_SHIFT) & UART_DLM_DLM_MASK) -#define UART_DLM_DLM_GET(x) (((uint32_t)(x) & UART_DLM_DLM_MASK) >> UART_DLM_DLM_SHIFT) - -/* Bitfield definition for register: IIR */ -/* - * RXIDLE_FLAG (W1C) - * - * UART IDLE Flag - * 0 - UART is busy - * 1 - UART is idle - * NOTE: when write one to clear this bit, avoid changging FCR register since it's same address as IIR - */ -#define UART_IIR_RXIDLE_FLAG_MASK (0x80000000UL) -#define UART_IIR_RXIDLE_FLAG_SHIFT (31U) -#define UART_IIR_RXIDLE_FLAG_SET(x) (((uint32_t)(x) << UART_IIR_RXIDLE_FLAG_SHIFT) & UART_IIR_RXIDLE_FLAG_MASK) -#define UART_IIR_RXIDLE_FLAG_GET(x) (((uint32_t)(x) & UART_IIR_RXIDLE_FLAG_MASK) >> UART_IIR_RXIDLE_FLAG_SHIFT) - -/* - * FIFOED (RO) - * - * FIFOs enabled - * These two bits are 1 when bit 0 of the FIFO Control - * Register (FIFOE) is set to 1. - */ -#define UART_IIR_FIFOED_MASK (0xC0U) -#define UART_IIR_FIFOED_SHIFT (6U) -#define UART_IIR_FIFOED_GET(x) (((uint32_t)(x) & UART_IIR_FIFOED_MASK) >> UART_IIR_FIFOED_SHIFT) - -/* - * INTRID (RO) - * - * Interrupt ID, see IIR2 for detail decoding - */ -#define UART_IIR_INTRID_MASK (0xFU) -#define UART_IIR_INTRID_SHIFT (0U) -#define UART_IIR_INTRID_GET(x) (((uint32_t)(x) & UART_IIR_INTRID_MASK) >> UART_IIR_INTRID_SHIFT) - -/* Bitfield definition for register: FCR */ -/* - * RFIFOT (WO) - * - * Receiver FIFO trigger level - */ -#define UART_FCR_RFIFOT_MASK (0xC0U) -#define UART_FCR_RFIFOT_SHIFT (6U) -#define UART_FCR_RFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_RFIFOT_SHIFT) & UART_FCR_RFIFOT_MASK) -#define UART_FCR_RFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_RFIFOT_MASK) >> UART_FCR_RFIFOT_SHIFT) - -/* - * TFIFOT (WO) - * - * Transmitter FIFO trigger level - */ -#define UART_FCR_TFIFOT_MASK (0x30U) -#define UART_FCR_TFIFOT_SHIFT (4U) -#define UART_FCR_TFIFOT_SET(x) (((uint32_t)(x) << UART_FCR_TFIFOT_SHIFT) & UART_FCR_TFIFOT_MASK) -#define UART_FCR_TFIFOT_GET(x) (((uint32_t)(x) & UART_FCR_TFIFOT_MASK) >> UART_FCR_TFIFOT_SHIFT) - -/* - * DMAE (WO) - * - * DMA enable - * 0: Disable - * 1: Enable - */ -#define UART_FCR_DMAE_MASK (0x8U) -#define UART_FCR_DMAE_SHIFT (3U) -#define UART_FCR_DMAE_SET(x) (((uint32_t)(x) << UART_FCR_DMAE_SHIFT) & UART_FCR_DMAE_MASK) -#define UART_FCR_DMAE_GET(x) (((uint32_t)(x) & UART_FCR_DMAE_MASK) >> UART_FCR_DMAE_SHIFT) - -/* - * TFIFORST (WO) - * - * Transmitter FIFO reset - * Write 1 to clear all bytes in the TXFIFO and resets its - * counter. The Transmitter Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_TFIFORST_MASK (0x4U) -#define UART_FCR_TFIFORST_SHIFT (2U) -#define UART_FCR_TFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_TFIFORST_SHIFT) & UART_FCR_TFIFORST_MASK) -#define UART_FCR_TFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_TFIFORST_MASK) >> UART_FCR_TFIFORST_SHIFT) - -/* - * RFIFORST (WO) - * - * Receiver FIFO reset - * Write 1 to clear all bytes in the RXFIFO and resets its - * counter. The Receiver Shift Register is not cleared. - * This bit will automatically be cleared. - */ -#define UART_FCR_RFIFORST_MASK (0x2U) -#define UART_FCR_RFIFORST_SHIFT (1U) -#define UART_FCR_RFIFORST_SET(x) (((uint32_t)(x) << UART_FCR_RFIFORST_SHIFT) & UART_FCR_RFIFORST_MASK) -#define UART_FCR_RFIFORST_GET(x) (((uint32_t)(x) & UART_FCR_RFIFORST_MASK) >> UART_FCR_RFIFORST_SHIFT) - -/* - * FIFOE (WO) - * - * FIFO enable - * Write 1 to enable both the transmitter and receiver - * FIFOs. - * The FIFOs are reset when the value of this bit toggles. - */ -#define UART_FCR_FIFOE_MASK (0x1U) -#define UART_FCR_FIFOE_SHIFT (0U) -#define UART_FCR_FIFOE_SET(x) (((uint32_t)(x) << UART_FCR_FIFOE_SHIFT) & UART_FCR_FIFOE_MASK) -#define UART_FCR_FIFOE_GET(x) (((uint32_t)(x) & UART_FCR_FIFOE_MASK) >> UART_FCR_FIFOE_SHIFT) - -/* Bitfield definition for register: LCR */ -/* - * DLAB (RW) - * - * Divisor latch access bit - */ -#define UART_LCR_DLAB_MASK (0x80U) -#define UART_LCR_DLAB_SHIFT (7U) -#define UART_LCR_DLAB_SET(x) (((uint32_t)(x) << UART_LCR_DLAB_SHIFT) & UART_LCR_DLAB_MASK) -#define UART_LCR_DLAB_GET(x) (((uint32_t)(x) & UART_LCR_DLAB_MASK) >> UART_LCR_DLAB_SHIFT) - -/* - * BC (RW) - * - * Break control - */ -#define UART_LCR_BC_MASK (0x40U) -#define UART_LCR_BC_SHIFT (6U) -#define UART_LCR_BC_SET(x) (((uint32_t)(x) << UART_LCR_BC_SHIFT) & UART_LCR_BC_MASK) -#define UART_LCR_BC_GET(x) (((uint32_t)(x) & UART_LCR_BC_MASK) >> UART_LCR_BC_SHIFT) - -/* - * SPS (RW) - * - * Stick parity - * 1: Parity bit is constant 0 or 1, depending on bit4 (EPS). - * 0: Disable the sticky bit parity. - */ -#define UART_LCR_SPS_MASK (0x20U) -#define UART_LCR_SPS_SHIFT (5U) -#define UART_LCR_SPS_SET(x) (((uint32_t)(x) << UART_LCR_SPS_SHIFT) & UART_LCR_SPS_MASK) -#define UART_LCR_SPS_GET(x) (((uint32_t)(x) & UART_LCR_SPS_MASK) >> UART_LCR_SPS_SHIFT) - -/* - * EPS (RW) - * - * Even parity select - * 1: Even parity (an even number of logic-1 is in the data - * and parity bits) - * 0: Old parity. - */ -#define UART_LCR_EPS_MASK (0x10U) -#define UART_LCR_EPS_SHIFT (4U) -#define UART_LCR_EPS_SET(x) (((uint32_t)(x) << UART_LCR_EPS_SHIFT) & UART_LCR_EPS_MASK) -#define UART_LCR_EPS_GET(x) (((uint32_t)(x) & UART_LCR_EPS_MASK) >> UART_LCR_EPS_SHIFT) - -/* - * PEN (RW) - * - * Parity enable - * When this bit is set, a parity bit is generated in - * transmitted data before the first STOP bit and the parity - * bit would be checked for the received data. - */ -#define UART_LCR_PEN_MASK (0x8U) -#define UART_LCR_PEN_SHIFT (3U) -#define UART_LCR_PEN_SET(x) (((uint32_t)(x) << UART_LCR_PEN_SHIFT) & UART_LCR_PEN_MASK) -#define UART_LCR_PEN_GET(x) (((uint32_t)(x) & UART_LCR_PEN_MASK) >> UART_LCR_PEN_SHIFT) - -/* - * STB (RW) - * - * Number of STOP bits - * 0: 1 bits - * 1: The number of STOP bit is based on the WLS setting - * When WLS = 0, STOP bit is 1.5 bits - * When WLS = 1, 2, 3, STOP bit is 2 bits - */ -#define UART_LCR_STB_MASK (0x4U) -#define UART_LCR_STB_SHIFT (2U) -#define UART_LCR_STB_SET(x) (((uint32_t)(x) << UART_LCR_STB_SHIFT) & UART_LCR_STB_MASK) -#define UART_LCR_STB_GET(x) (((uint32_t)(x) & UART_LCR_STB_MASK) >> UART_LCR_STB_SHIFT) - -/* - * WLS (RW) - * - * Word length setting - * 0: 5 bits - * 1: 6 bits - * 2: 7 bits - * 3: 8 bits - */ -#define UART_LCR_WLS_MASK (0x3U) -#define UART_LCR_WLS_SHIFT (0U) -#define UART_LCR_WLS_SET(x) (((uint32_t)(x) << UART_LCR_WLS_SHIFT) & UART_LCR_WLS_MASK) -#define UART_LCR_WLS_GET(x) (((uint32_t)(x) & UART_LCR_WLS_MASK) >> UART_LCR_WLS_SHIFT) - -/* Bitfield definition for register: MCR */ -/* - * AFE (RW) - * - * Auto flow control enable - * 0: Disable - * 1: The auto-CTS and auto-RTS setting is based on the - * RTS bit setting: - * When RTS = 0, auto-CTS only - * When RTS = 1, auto-CTS and auto-RTS - */ -#define UART_MCR_AFE_MASK (0x20U) -#define UART_MCR_AFE_SHIFT (5U) -#define UART_MCR_AFE_SET(x) (((uint32_t)(x) << UART_MCR_AFE_SHIFT) & UART_MCR_AFE_MASK) -#define UART_MCR_AFE_GET(x) (((uint32_t)(x) & UART_MCR_AFE_MASK) >> UART_MCR_AFE_SHIFT) - -/* - * LOOP (RW) - * - * Enable loopback mode - * 0: Disable - * 1: Enable - */ -#define UART_MCR_LOOP_MASK (0x10U) -#define UART_MCR_LOOP_SHIFT (4U) -#define UART_MCR_LOOP_SET(x) (((uint32_t)(x) << UART_MCR_LOOP_SHIFT) & UART_MCR_LOOP_MASK) -#define UART_MCR_LOOP_GET(x) (((uint32_t)(x) & UART_MCR_LOOP_MASK) >> UART_MCR_LOOP_SHIFT) - -/* - * RTS (RW) - * - * Request to send - * This bit controls the modem_rtsn output. - * 0: The modem_rtsn output signal will be driven HIGH - * 1: The modem_rtsn output signal will be driven LOW - */ -#define UART_MCR_RTS_MASK (0x2U) -#define UART_MCR_RTS_SHIFT (1U) -#define UART_MCR_RTS_SET(x) (((uint32_t)(x) << UART_MCR_RTS_SHIFT) & UART_MCR_RTS_MASK) -#define UART_MCR_RTS_GET(x) (((uint32_t)(x) & UART_MCR_RTS_MASK) >> UART_MCR_RTS_SHIFT) - -/* Bitfield definition for register: LSR */ -/* - * RXIDLE (RO) - * - * rxidle after timeout, clear after rx idle condition not match - */ -#define UART_LSR_RXIDLE_MASK (0x80000000UL) -#define UART_LSR_RXIDLE_SHIFT (31U) -#define UART_LSR_RXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_RXIDLE_MASK) >> UART_LSR_RXIDLE_SHIFT) - -/* - * TXIDLE (RO) - * - * txidle after timeout, clear after tx idle condition not match - */ -#define UART_LSR_TXIDLE_MASK (0x40000000UL) -#define UART_LSR_TXIDLE_SHIFT (30U) -#define UART_LSR_TXIDLE_GET(x) (((uint32_t)(x) & UART_LSR_TXIDLE_MASK) >> UART_LSR_TXIDLE_SHIFT) - -/* - * RFIFO_NUM (RO) - * - * data bytes in rxfifo not read - */ -#define UART_LSR_RFIFO_NUM_MASK (0x1F0000UL) -#define UART_LSR_RFIFO_NUM_SHIFT (16U) -#define UART_LSR_RFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_RFIFO_NUM_MASK) >> UART_LSR_RFIFO_NUM_SHIFT) - -/* - * TFIFO_NUM (RO) - * - * data bytes in txfifo not sent - */ -#define UART_LSR_TFIFO_NUM_MASK (0x1F00U) -#define UART_LSR_TFIFO_NUM_SHIFT (8U) -#define UART_LSR_TFIFO_NUM_GET(x) (((uint32_t)(x) & UART_LSR_TFIFO_NUM_MASK) >> UART_LSR_TFIFO_NUM_SHIFT) - -/* - * ERRF (RO) - * - * Error in RXFIFO - * In the FIFO mode, this bit is set when there is at least - * one parity error, framing error, or line break - * associated with data in the RXFIFO. It is cleared when - * this register is read and there is no more error for the - * rest of data in the RXFIFO. - */ -#define UART_LSR_ERRF_MASK (0x80U) -#define UART_LSR_ERRF_SHIFT (7U) -#define UART_LSR_ERRF_GET(x) (((uint32_t)(x) & UART_LSR_ERRF_MASK) >> UART_LSR_ERRF_SHIFT) - -/* - * TEMT (RO) - * - * Transmitter empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) and the Transmitter Shift Register (TSR) are - * both empty. Otherwise, it is zero. - */ -#define UART_LSR_TEMT_MASK (0x40U) -#define UART_LSR_TEMT_SHIFT (6U) -#define UART_LSR_TEMT_GET(x) (((uint32_t)(x) & UART_LSR_TEMT_MASK) >> UART_LSR_TEMT_SHIFT) - -/* - * THRE (RO) - * - * Transmitter Holding Register empty - * This bit is 1 when the THR (TXFIFO in the FIFO - * mode) is empty. Otherwise, it is zero. - * If the THRE interrupt is enabled, an interrupt is - * triggered when THRE becomes 1. - */ -#define UART_LSR_THRE_MASK (0x20U) -#define UART_LSR_THRE_SHIFT (5U) -#define UART_LSR_THRE_GET(x) (((uint32_t)(x) & UART_LSR_THRE_MASK) >> UART_LSR_THRE_SHIFT) - -/* - * LBREAK (RO) - * - * Line break - * This bit is set when the uart_sin input signal was held - * LOWfor longer than the time for a full-word - * transmission. A full-word transmission is the - * transmission of the START, data, parity, and STOP - * bits. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the line break for - * the received data at the top of the RXFIFO. - */ -#define UART_LSR_LBREAK_MASK (0x10U) -#define UART_LSR_LBREAK_SHIFT (4U) -#define UART_LSR_LBREAK_GET(x) (((uint32_t)(x) & UART_LSR_LBREAK_MASK) >> UART_LSR_LBREAK_SHIFT) - -/* - * FE (RO) - * - * Framing error - * This bit is set when the received STOP bit is not - * HIGH. It is cleared when this register is read. - * In the FIFO mode, this bit indicates the framing error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_FE_MASK (0x8U) -#define UART_LSR_FE_SHIFT (3U) -#define UART_LSR_FE_GET(x) (((uint32_t)(x) & UART_LSR_FE_MASK) >> UART_LSR_FE_SHIFT) - -/* - * PE (RO) - * - * Parity error - * This bit is set when the received parity does not match - * with the parity selected in the LCR[5:4]. It is cleared - * when this register is read. - * In the FIFO mode, this bit indicates the parity error - * for the received data at the top of the RXFIFO. - */ -#define UART_LSR_PE_MASK (0x4U) -#define UART_LSR_PE_SHIFT (2U) -#define UART_LSR_PE_GET(x) (((uint32_t)(x) & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT) - -/* - * OE (RO) - * - * Overrun error - * This bit indicates that data in the Receiver Buffer - * Register (RBR) is overrun. - */ -#define UART_LSR_OE_MASK (0x2U) -#define UART_LSR_OE_SHIFT (1U) -#define UART_LSR_OE_GET(x) (((uint32_t)(x) & UART_LSR_OE_MASK) >> UART_LSR_OE_SHIFT) - -/* - * DR (RO) - * - * Data ready. - * This bit is set when there are incoming received data - * in the Receiver Buffer Register (RBR). It is cleared - * when all of the received data are read. - */ -#define UART_LSR_DR_MASK (0x1U) -#define UART_LSR_DR_SHIFT (0U) -#define UART_LSR_DR_GET(x) (((uint32_t)(x) & UART_LSR_DR_MASK) >> UART_LSR_DR_SHIFT) - -/* Bitfield definition for register: MSR */ -/* - * CTS (RO) - * - * Clear to send - * 0: The modem_ctsn input signal is HIGH. - * 1: The modem_ctsn input signal is LOW. - */ -#define UART_MSR_CTS_MASK (0x10U) -#define UART_MSR_CTS_SHIFT (4U) -#define UART_MSR_CTS_GET(x) (((uint32_t)(x) & UART_MSR_CTS_MASK) >> UART_MSR_CTS_SHIFT) - -/* - * DCTS (RC) - * - * Delta clear to send - * This bit is set when the state of the modem_ctsn input - * signal has been changed since the last time this - * register is read. - */ -#define UART_MSR_DCTS_MASK (0x1U) -#define UART_MSR_DCTS_SHIFT (0U) -#define UART_MSR_DCTS_GET(x) (((uint32_t)(x) & UART_MSR_DCTS_MASK) >> UART_MSR_DCTS_SHIFT) - -/* Bitfield definition for register: GPR */ -/* - * DATA (RW) - * - * A one-byte storage register - */ -#define UART_GPR_DATA_MASK (0xFFU) -#define UART_GPR_DATA_SHIFT (0U) -#define UART_GPR_DATA_SET(x) (((uint32_t)(x) << UART_GPR_DATA_SHIFT) & UART_GPR_DATA_MASK) -#define UART_GPR_DATA_GET(x) (((uint32_t)(x) & UART_GPR_DATA_MASK) >> UART_GPR_DATA_SHIFT) - - - - -#endif /* HPM_UART_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_usb_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_usb_regs.h deleted file mode 100644 index ffaaefb4024..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_usb_regs.h +++ /dev/null @@ -1,2271 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_USB_H -#define HPM_USB_H - -typedef struct { - __R uint8_t RESERVED0[128]; /* 0x0 - 0x7F: Reserved */ - __RW uint32_t GPTIMER0LD; /* 0x80: General Purpose Timer #0 Load Register */ - __RW uint32_t GPTIMER0CTRL; /* 0x84: General Purpose Timer #0 Controller Register */ - __RW uint32_t GPTIMER1LD; /* 0x88: General Purpose Timer #1 Load Register */ - __RW uint32_t GPTIMER1CTRL; /* 0x8C: General Purpose Timer #1 Controller Register */ - __RW uint32_t SBUSCFG; /* 0x90: System Bus Config Register */ - __R uint8_t RESERVED1[172]; /* 0x94 - 0x13F: Reserved */ - __RW uint32_t USBCMD; /* 0x140: USB Command Register */ - __RW uint32_t USBSTS; /* 0x144: USB Status Register */ - __RW uint32_t USBINTR; /* 0x148: Interrupt Enable Register */ - __RW uint32_t FRINDEX; /* 0x14C: USB Frame Index Register */ - __R uint8_t RESERVED2[4]; /* 0x150 - 0x153: Reserved */ - union { - __RW uint32_t DEVICEADDR; /* 0x154: Device Address Register */ - __RW uint32_t PERIODICLISTBASE; /* 0x154: Frame List Base Address Register */ - }; - union { - __RW uint32_t ASYNCLISTADDR; /* 0x158: Next Asynch. Address Register */ - __RW uint32_t ENDPTLISTADDR; /* 0x158: Endpoint List Address Register */ - }; - __R uint8_t RESERVED3[4]; /* 0x15C - 0x15F: Reserved */ - __RW uint32_t BURSTSIZE; /* 0x160: Programmable Burst Size Register */ - __RW uint32_t TXFILLTUNING; /* 0x164: TX FIFO Fill Tuning Register */ - __R uint8_t RESERVED4[16]; /* 0x168 - 0x177: Reserved */ - __RW uint32_t ENDPTNAK; /* 0x178: Endpoint NAK Register */ - __RW uint32_t ENDPTNAKEN; /* 0x17C: Endpoint NAK Enable Register */ - __R uint8_t RESERVED5[4]; /* 0x180 - 0x183: Reserved */ - __RW uint32_t PORTSC1; /* 0x184: Port Status & Control */ - __R uint8_t RESERVED6[28]; /* 0x188 - 0x1A3: Reserved */ - __RW uint32_t OTGSC; /* 0x1A4: On-The-Go Status & control Register */ - __RW uint32_t USBMODE; /* 0x1A8: USB Device Mode Register */ - __RW uint32_t ENDPTSETUPSTAT; /* 0x1AC: Endpoint Setup Status Register */ - __RW uint32_t ENDPTPRIME; /* 0x1B0: Endpoint Prime Register */ - __RW uint32_t ENDPTFLUSH; /* 0x1B4: Endpoint Flush Register */ - __R uint32_t ENDPTSTAT; /* 0x1B8: Endpoint Status Register */ - __RW uint32_t ENDPTCOMPLETE; /* 0x1BC: Endpoint Complete Register */ - __RW uint32_t ENDPTCTRL[16]; /* 0x1C0 - 0x1FC: Endpoint Control0 Register... Endpoint Control7 Register */ - __RW uint32_t OTG_CTRL0; /* 0x200: */ - __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */ - __RW uint32_t PHY_CTRL0; /* 0x210: */ - __RW uint32_t PHY_CTRL1; /* 0x214: */ - __R uint8_t RESERVED8[8]; /* 0x218 - 0x21F: Reserved */ - __RW uint32_t TOP_STATUS; /* 0x220: */ - __RW uint32_t PHY_STATUS; /* 0x224: */ -} USB_Type; - - -/* Bitfield definition for register: GPTIMER0LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER0LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER0LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER0LD_GPTLD_SHIFT) & USB_GPTIMER0LD_GPTLD_MASK) -#define USB_GPTIMER0LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER0LD_GPTLD_MASK) >> USB_GPTIMER0LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER0CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER0CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRUN_SHIFT) & USB_GPTIMER0CTRL_GPTRUN_MASK) -#define USB_GPTIMER0CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRUN_MASK) >> USB_GPTIMER0CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in n_GPTIMER0LD - */ -#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER0CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTRST_SHIFT) & USB_GPTIMER0CTRL_GPTRST_MASK) -#define USB_GPTIMER0CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTRST_MASK) >> USB_GPTIMER0CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software; - * In repeat mode, the timer will count down to zero, generate an interrupt and automatically reload the - * counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER0CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER0CTRL_GPTMODE_SHIFT) & USB_GPTIMER0CTRL_GPTMODE_MASK) -#define USB_GPTIMER0CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTMODE_MASK) >> USB_GPTIMER0CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER0CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER0CTRL_GPTCNT_MASK) >> USB_GPTIMER0CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: GPTIMER1LD */ -/* - * GPTLD (RW) - * - * GPTLD - * General Purpose Timer Load Value - * These bit fields are loaded to GPTCNT bits when GPTRST bit is set '1b'. - * This value represents the time in microseconds minus 1 for the timer duration. - * Example: for a one millisecond timer, load 1000-1=999 or 0x0003E7. - * NOTE: Max value is 0xFFFFFF or 16.777215 seconds. - */ -#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFUL) -#define USB_GPTIMER1LD_GPTLD_SHIFT (0U) -#define USB_GPTIMER1LD_GPTLD_SET(x) (((uint32_t)(x) << USB_GPTIMER1LD_GPTLD_SHIFT) & USB_GPTIMER1LD_GPTLD_MASK) -#define USB_GPTIMER1LD_GPTLD_GET(x) (((uint32_t)(x) & USB_GPTIMER1LD_GPTLD_MASK) >> USB_GPTIMER1LD_GPTLD_SHIFT) - -/* Bitfield definition for register: GPTIMER1CTRL */ -/* - * GPTRUN (RW) - * - * GPTRUN - * General Purpose Timer Run - * GPTCNT bits are not effected when setting or clearing this bit. - * 0 - Stop counting - * 1 - Run - */ -#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000UL) -#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -#define USB_GPTIMER1CTRL_GPTRUN_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRUN_SHIFT) & USB_GPTIMER1CTRL_GPTRUN_MASK) -#define USB_GPTIMER1CTRL_GPTRUN_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRUN_MASK) >> USB_GPTIMER1CTRL_GPTRUN_SHIFT) - -/* - * GPTRST (WO) - * - * GPTRST - * General Purpose Timer Reset - * 0 - No action - * 1 - Load counter value from GPTLD bits in USB_n_GPTIMER1LD - */ -#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000UL) -#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -#define USB_GPTIMER1CTRL_GPTRST_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTRST_SHIFT) & USB_GPTIMER1CTRL_GPTRST_MASK) -#define USB_GPTIMER1CTRL_GPTRST_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTRST_MASK) >> USB_GPTIMER1CTRL_GPTRST_SHIFT) - -/* - * GPTMODE (RW) - * - * GPTMODE - * General Purpose Timer Mode - * In one shot mode, the timer will count down to zero, generate an interrupt, and stop until the counter is - * reset by software. In repeat mode, the timer will count down to zero, generate an interrupt and - * automatically reload the counter value from GPTLD bits to start again. - * 0 - One Shot Mode - * 1 - Repeat Mode - */ -#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000UL) -#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -#define USB_GPTIMER1CTRL_GPTMODE_SET(x) (((uint32_t)(x) << USB_GPTIMER1CTRL_GPTMODE_SHIFT) & USB_GPTIMER1CTRL_GPTMODE_MASK) -#define USB_GPTIMER1CTRL_GPTMODE_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTMODE_MASK) >> USB_GPTIMER1CTRL_GPTMODE_SHIFT) - -/* - * GPTCNT (RO) - * - * GPTCNT - * General Purpose Timer Counter. - * This field is the count value of the countdown timer. - */ -#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFUL) -#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) -#define USB_GPTIMER1CTRL_GPTCNT_GET(x) (((uint32_t)(x) & USB_GPTIMER1CTRL_GPTCNT_MASK) >> USB_GPTIMER1CTRL_GPTCNT_SHIFT) - -/* Bitfield definition for register: SBUSCFG */ -/* - * AHBBRST (RW) - * - * AHBBRST - * AHB master interface Burst configuration - * These bits control AHB master transfer type sequence (or priority). - * NOTE: This register overrides n_BURSTSIZE register when its value is not zero. - * 000 - Incremental burst of unspecified length only - * 001 - INCR4 burst, then single transfer - * 010 - INCR8 burst, INCR4 burst, then single transfer - * 011 - INCR16 burst, INCR8 burst, INCR4 burst, then single transfer - * 100 - Reserved, don't use - * 101 - INCR4 burst, then incremental burst of unspecified length - * 110 - INCR8 burst, INCR4 burst, then incremental burst of unspecified length - * 111 - INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length - */ -#define USB_SBUSCFG_AHBBRST_MASK (0x7U) -#define USB_SBUSCFG_AHBBRST_SHIFT (0U) -#define USB_SBUSCFG_AHBBRST_SET(x) (((uint32_t)(x) << USB_SBUSCFG_AHBBRST_SHIFT) & USB_SBUSCFG_AHBBRST_MASK) -#define USB_SBUSCFG_AHBBRST_GET(x) (((uint32_t)(x) & USB_SBUSCFG_AHBBRST_MASK) >> USB_SBUSCFG_AHBBRST_SHIFT) - -/* Bitfield definition for register: USBCMD */ -/* - * ITC (RW) - * - * ITC - * Interrupt Threshold Control -Read/Write. - * The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. - * ITC contains the maximum interrupt interval measured in micro-frames. Valid values are - * shown below. - * Value Maximum Interrupt Interval - * 00000000 - Immediate (no threshold) - * 00000001 - 1 micro-frame - * 00000010 - 2 micro-frames - * 00000100 - 4 micro-frames - * 00001000 - 8 micro-frames - * 00010000 - 16 micro-frames - * 00100000 - 32 micro-frames - * 01000000 - 64 micro-frames - */ -#define USB_USBCMD_ITC_MASK (0xFF0000UL) -#define USB_USBCMD_ITC_SHIFT (16U) -#define USB_USBCMD_ITC_SET(x) (((uint32_t)(x) << USB_USBCMD_ITC_SHIFT) & USB_USBCMD_ITC_MASK) -#define USB_USBCMD_ITC_GET(x) (((uint32_t)(x) & USB_USBCMD_ITC_MASK) >> USB_USBCMD_ITC_SHIFT) - -/* - * FS_2 (RW) - * - * FS_2 - * Frame List Size - (Read/Write or Read Only). [host mode only] - * This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one. - * This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. - * NOTE: This field is made up from USBCMD bits 15, 3 and 2. - * Value Meaning - * 0b000 - 1024 elements (4096 bytes) Default value - * 0b001 - 512 elements (2048 bytes) - * 0b010 - 256 elements (1024 bytes) - * 0b011 - 128 elements (512 bytes) - * 0b100 - 64 elements (256 bytes) - * 0b101 - 32 elements (128 bytes) - * 0b110 - 16 elements (64 bytes) - * 0b111 - 8 elements (32 bytes) - */ -#define USB_USBCMD_FS_2_MASK (0x8000U) -#define USB_USBCMD_FS_2_SHIFT (15U) -#define USB_USBCMD_FS_2_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_2_SHIFT) & USB_USBCMD_FS_2_MASK) -#define USB_USBCMD_FS_2_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_2_MASK) >> USB_USBCMD_FS_2_SHIFT) - -/* - * ATDTW (RW) - * - * ATDTW - * Add dTD TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure proper addition of a new dTD to an active (primed) endpoint's - * linked list. This bit is set and cleared by software. - * This bit would also be cleared by hardware when state machine is hazard region for which adding a dTD - * to a primed endpoint may go unrecognized. - */ -#define USB_USBCMD_ATDTW_MASK (0x4000U) -#define USB_USBCMD_ATDTW_SHIFT (14U) -#define USB_USBCMD_ATDTW_SET(x) (((uint32_t)(x) << USB_USBCMD_ATDTW_SHIFT) & USB_USBCMD_ATDTW_MASK) -#define USB_USBCMD_ATDTW_GET(x) (((uint32_t)(x) & USB_USBCMD_ATDTW_MASK) >> USB_USBCMD_ATDTW_SHIFT) - -/* - * SUTW (RW) - * - * SUTW - * Setup TripWire - Read/Write. [device mode only] - * This bit is used as a semaphore to ensure that the setup data payload of 8 bytes is extracted from a QH by the DCD without being corrupted. - * If the setup lockout mode is off (SLOM bit in USB core register n_USBMODE, see USBMODE ) then - * there is a hazard when new setup data arrives while the DCD is copying the setup data payload - * from the QH for a previous setup packet. This bit is set and cleared by software. - * This bit would also be cleared by hardware when a hazard detected. - */ -#define USB_USBCMD_SUTW_MASK (0x2000U) -#define USB_USBCMD_SUTW_SHIFT (13U) -#define USB_USBCMD_SUTW_SET(x) (((uint32_t)(x) << USB_USBCMD_SUTW_SHIFT) & USB_USBCMD_SUTW_MASK) -#define USB_USBCMD_SUTW_GET(x) (((uint32_t)(x) & USB_USBCMD_SUTW_MASK) >> USB_USBCMD_SUTW_SHIFT) - -/* - * PRM (WO) - * - * Asynchronous Schedule start- Write only， host mode only。 - * this bit is used to notify hostcontroller to start async schedule immediately. - */ -#define USB_USBCMD_PRM_MASK (0x1000U) -#define USB_USBCMD_PRM_SHIFT (12U) -#define USB_USBCMD_PRM_SET(x) (((uint32_t)(x) << USB_USBCMD_PRM_SHIFT) & USB_USBCMD_PRM_MASK) -#define USB_USBCMD_PRM_GET(x) (((uint32_t)(x) & USB_USBCMD_PRM_MASK) >> USB_USBCMD_PRM_SHIFT) - -/* - * ASPE (RW) - * - * ASPE - * Asynchronous Schedule Park Mode Enable - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1h and is R/W. - * Otherwise the bit must be a zero and is RO. Software uses this bit to enable or disable Park mode. - * When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled. - * NOTE: ASPE bit reset value: '0b' for OTG controller . - */ -#define USB_USBCMD_ASPE_MASK (0x800U) -#define USB_USBCMD_ASPE_SHIFT (11U) -#define USB_USBCMD_ASPE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASPE_SHIFT) & USB_USBCMD_ASPE_MASK) -#define USB_USBCMD_ASPE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASPE_MASK) >> USB_USBCMD_ASPE_SHIFT) - -/* - * ASP (RW) - * - * ASP - * Asynchronous Schedule Park Mode Count - Read/Write. - * If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 3h and is R/W. Otherwise it defaults to zero and is Read-Only. - * It contains a count of the number of successive transactions the host controller is allowed to - * execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. - * Valid values are 1h to 3h. Software must not write a zero to this bit when Park Mode Enable is a one as this will result in undefined behavior. - * This field is set to 3h in all controller core. - */ -#define USB_USBCMD_ASP_MASK (0x300U) -#define USB_USBCMD_ASP_SHIFT (8U) -#define USB_USBCMD_ASP_SET(x) (((uint32_t)(x) << USB_USBCMD_ASP_SHIFT) & USB_USBCMD_ASP_MASK) -#define USB_USBCMD_ASP_GET(x) (((uint32_t)(x) & USB_USBCMD_ASP_MASK) >> USB_USBCMD_ASP_SHIFT) - -/* - * IAA (RW) - * - * IAA - * Interrupt on Async Advance Doorbell - Read/Write. - * This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. - * When the host controller has evicted all appropriate cached schedule states, - * it sets the Interrupt on Async Advance status bit in the USBSTS register. - * If the Interrupt on Sync Advance Enable bit in the USBINTR register is one, then the host controller will assert an interrupt at the next interrupt threshold. - * The host controller sets this bit to zero after it has set the Interrupt on Sync Advance status bit in the USBSTS register to one. - * Software should not write a one to this bit when the asynchronous schedule is inactive. Doing so will yield undefined results. - * This bit is only used in host mode. Writing a one to this bit when device mode is selected will have undefined results. - */ -#define USB_USBCMD_IAA_MASK (0x40U) -#define USB_USBCMD_IAA_SHIFT (6U) -#define USB_USBCMD_IAA_SET(x) (((uint32_t)(x) << USB_USBCMD_IAA_SHIFT) & USB_USBCMD_IAA_MASK) -#define USB_USBCMD_IAA_GET(x) (((uint32_t)(x) & USB_USBCMD_IAA_MASK) >> USB_USBCMD_IAA_SHIFT) - -/* - * ASE (RW) - * - * ASE - * Asynchronous Schedule Enable - Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Asynchronous Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Asynchronous Schedule. - * 1 - Use the ASYNCLISTADDR register to access the Asynchronous Schedule. - */ -#define USB_USBCMD_ASE_MASK (0x20U) -#define USB_USBCMD_ASE_SHIFT (5U) -#define USB_USBCMD_ASE_SET(x) (((uint32_t)(x) << USB_USBCMD_ASE_SHIFT) & USB_USBCMD_ASE_MASK) -#define USB_USBCMD_ASE_GET(x) (((uint32_t)(x) & USB_USBCMD_ASE_MASK) >> USB_USBCMD_ASE_SHIFT) - -/* - * PSE (RW) - * - * PSE - * Periodic Schedule Enable- Read/Write. Default 0b. - * This bit controls whether the host controller skips processing the Periodic Schedule. - * Only the host controller uses this bit. - * Values Meaning - * 0 - Do not process the Periodic Schedule - * 1 - Use the PERIODICLISTBASE register to access the Periodic Schedule. - */ -#define USB_USBCMD_PSE_MASK (0x10U) -#define USB_USBCMD_PSE_SHIFT (4U) -#define USB_USBCMD_PSE_SET(x) (((uint32_t)(x) << USB_USBCMD_PSE_SHIFT) & USB_USBCMD_PSE_MASK) -#define USB_USBCMD_PSE_GET(x) (((uint32_t)(x) & USB_USBCMD_PSE_MASK) >> USB_USBCMD_PSE_SHIFT) - -/* - * FS_1 (RW) - * - * FS_1 - * See description at bit 15 - */ -#define USB_USBCMD_FS_1_MASK (0xCU) -#define USB_USBCMD_FS_1_SHIFT (2U) -#define USB_USBCMD_FS_1_SET(x) (((uint32_t)(x) << USB_USBCMD_FS_1_SHIFT) & USB_USBCMD_FS_1_MASK) -#define USB_USBCMD_FS_1_GET(x) (((uint32_t)(x) & USB_USBCMD_FS_1_MASK) >> USB_USBCMD_FS_1_SHIFT) - -/* - * RST (RW) - * - * RST - * Controller Reset (RESET) - Read/Write. Software uses this bit to reset the controller. - * This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. - * Host operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. - * Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. - * Attempting to reset an actively running host controller will result in undefined behavior. - * Device operation mode: - * When software writes a one to this bit, the Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. - * Writing a one to this bit when the device is in the attached state is not recommended, because the effect on an attached host is undefined. - * In order to ensure that the device is not in an attached state before initiating a device controller reset, all primed endpoints should be flushed and the USBCMD Run/Stop bit should be set to 0. - */ -#define USB_USBCMD_RST_MASK (0x2U) -#define USB_USBCMD_RST_SHIFT (1U) -#define USB_USBCMD_RST_SET(x) (((uint32_t)(x) << USB_USBCMD_RST_SHIFT) & USB_USBCMD_RST_MASK) -#define USB_USBCMD_RST_GET(x) (((uint32_t)(x) & USB_USBCMD_RST_MASK) >> USB_USBCMD_RST_SHIFT) - -/* - * RS (RW) - * - * RS - * Run/Stop (RS) - Read/Write. Default 0b. 1=Run. 0=Stop. - * Host operation mode: - * When set to '1b', the Controller proceeds with the execution of the schedule. The Controller continues execution as long as this bit is set to a one. - * When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts. - * The HC Halted bit in the status register indicates when the Controller has finished the transaction and has entered the stopped state. - * Software should not write a one to this field unless the controller is in the Halted state (that is, HCHalted in the USBSTS register is a one). - * Device operation mode: - * Writing a one to this bit will cause the controller to enable a pull-up on D+ and initiate an attach event. - * This control bit is not directly connected to the pull-up enable, as the pull-up will become disabled upon transitioning into high-speed mode. - * Software should use this bit to prevent an attach event before the controller has been properly initialized. Writing a 0 to this will cause a detach event. - */ -#define USB_USBCMD_RS_MASK (0x1U) -#define USB_USBCMD_RS_SHIFT (0U) -#define USB_USBCMD_RS_SET(x) (((uint32_t)(x) << USB_USBCMD_RS_SHIFT) & USB_USBCMD_RS_MASK) -#define USB_USBCMD_RS_GET(x) (((uint32_t)(x) & USB_USBCMD_RS_MASK) >> USB_USBCMD_RS_SHIFT) - -/* Bitfield definition for register: USBSTS */ -/* - * TI1 (RWC) - * - * TI1 - * General Purpose Timer Interrupt 1(GPTINT1)--R/WC. - * This bit is set when the counter in the GPTIMER1CTRL register transitions to zero, writing a one to this - * bit will clear it. - */ -#define USB_USBSTS_TI1_MASK (0x2000000UL) -#define USB_USBSTS_TI1_SHIFT (25U) -#define USB_USBSTS_TI1_SET(x) (((uint32_t)(x) << USB_USBSTS_TI1_SHIFT) & USB_USBSTS_TI1_MASK) -#define USB_USBSTS_TI1_GET(x) (((uint32_t)(x) & USB_USBSTS_TI1_MASK) >> USB_USBSTS_TI1_SHIFT) - -/* - * TI0 (RWC) - * - * TI0 - * General Purpose Timer Interrupt 0(GPTINT0)--R/WC. - * This bit is set when the counter in the GPTIMER0CTRL register transitions to zero, writing a one to this - * bit clears it. - */ -#define USB_USBSTS_TI0_MASK (0x1000000UL) -#define USB_USBSTS_TI0_SHIFT (24U) -#define USB_USBSTS_TI0_SET(x) (((uint32_t)(x) << USB_USBSTS_TI0_SHIFT) & USB_USBSTS_TI0_MASK) -#define USB_USBSTS_TI0_GET(x) (((uint32_t)(x) & USB_USBSTS_TI0_MASK) >> USB_USBSTS_TI0_SHIFT) - -/* - * UPI (RWC) - * - * USB Host Periodic Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the periodic schedule. - * This bit is also set by the Host Controller when a short packet is detected and the packet is on the periodic schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero. - */ -#define USB_USBSTS_UPI_MASK (0x80000UL) -#define USB_USBSTS_UPI_SHIFT (19U) -#define USB_USBSTS_UPI_SET(x) (((uint32_t)(x) << USB_USBSTS_UPI_SHIFT) & USB_USBSTS_UPI_MASK) -#define USB_USBSTS_UPI_GET(x) (((uint32_t)(x) & USB_USBSTS_UPI_MASK) >> USB_USBSTS_UPI_SHIFT) - -/* - * UAI (RWC) - * - * USB Host Asynchronous Interrupt – RWC. Default = 0b. - * This bit is set by the Host Controller when the cause of an interrupt is a completion of a USB transaction - * where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the asynchronous schedule. - * This bit is also set by the Host when a short packet is detected and the packet is on the asynchronous schedule. - * A short packet is when the actual number of bytes received was less than expected. - * This bit is not used by the device controller and will always be zero - */ -#define USB_USBSTS_UAI_MASK (0x40000UL) -#define USB_USBSTS_UAI_SHIFT (18U) -#define USB_USBSTS_UAI_SET(x) (((uint32_t)(x) << USB_USBSTS_UAI_SHIFT) & USB_USBSTS_UAI_MASK) -#define USB_USBSTS_UAI_GET(x) (((uint32_t)(x) & USB_USBSTS_UAI_MASK) >> USB_USBSTS_UAI_SHIFT) - -/* - * NAKI (RO) - * - * NAKI - * NAK Interrupt Bit--RO. - * This bit is set by hardware when for a particular endpoint both the TX/RX Endpoint NAK bit and - * corresponding TX/RX Endpoint NAK Enable bit are set. This bit is automatically cleared by hardware - * when all Enabled TX/RX Endpoint NAK bits are cleared. - */ -#define USB_USBSTS_NAKI_MASK (0x10000UL) -#define USB_USBSTS_NAKI_SHIFT (16U) -#define USB_USBSTS_NAKI_GET(x) (((uint32_t)(x) & USB_USBSTS_NAKI_MASK) >> USB_USBSTS_NAKI_SHIFT) - -/* - * AS (RO) - * - * AS - * Asynchronous Schedule Status - Read Only. - * This bit reports the current real status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. - * When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_AS_MASK (0x8000U) -#define USB_USBSTS_AS_SHIFT (15U) -#define USB_USBSTS_AS_GET(x) (((uint32_t)(x) & USB_USBSTS_AS_MASK) >> USB_USBSTS_AS_SHIFT) - -/* - * PS (RO) - * - * PS - * Periodic Schedule Status - Read Only. - * This bit reports the current real status of the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the status is enabled. - * The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. - * When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). - * Only used in the host operation mode. - */ -#define USB_USBSTS_PS_MASK (0x4000U) -#define USB_USBSTS_PS_SHIFT (14U) -#define USB_USBSTS_PS_GET(x) (((uint32_t)(x) & USB_USBSTS_PS_MASK) >> USB_USBSTS_PS_SHIFT) - -/* - * RCL (RO) - * - * RCL - * Reclamation - Read Only. - * This is a read-only status bit used to detect an empty asynchronous schedule. - * Only used in the host operation mode. - */ -#define USB_USBSTS_RCL_MASK (0x2000U) -#define USB_USBSTS_RCL_SHIFT (13U) -#define USB_USBSTS_RCL_GET(x) (((uint32_t)(x) & USB_USBSTS_RCL_MASK) >> USB_USBSTS_RCL_SHIFT) - -/* - * HCH (RO) - * - * HCH - * HCHaIted - Read Only. - * This bit is a zero whenever the Run/Stop bit is a one. - * The Controller sets this bit to one after it has stopped executing because of the Run/Stop bit being set to 0, - * either by software or by the Controller hardware (for example, an internal error). - * Only used in the host operation mode. - * Default value is '0b' for OTG core . - * This is because OTG core is not operating as host in default. Please see CM bit in USB_n_USBMODE - * register. - * NOTE: HCH bit reset value: '0b' for OTG controller core . - */ -#define USB_USBSTS_HCH_MASK (0x1000U) -#define USB_USBSTS_HCH_SHIFT (12U) -#define USB_USBSTS_HCH_GET(x) (((uint32_t)(x) & USB_USBSTS_HCH_MASK) >> USB_USBSTS_HCH_SHIFT) - -/* - * SLI (RWC) - * - * SLI - * DCSuspend - R/WC. - * When a controller enters a suspend state from an active state, this bit will be set to a one. The device controller clears the bit upon exiting from a suspend state. - * Only used in device operation mode. - */ -#define USB_USBSTS_SLI_MASK (0x100U) -#define USB_USBSTS_SLI_SHIFT (8U) -#define USB_USBSTS_SLI_SET(x) (((uint32_t)(x) << USB_USBSTS_SLI_SHIFT) & USB_USBSTS_SLI_MASK) -#define USB_USBSTS_SLI_GET(x) (((uint32_t)(x) & USB_USBSTS_SLI_MASK) >> USB_USBSTS_SLI_SHIFT) - -/* - * SRI (RWC) - * - * SRI - * SOF Received - R/WC. - * When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. - * When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected. - * Therefore, this bit will be set roughly every 1ms in device FS mode and every 125ms in HS mode and will be synchronized to the actual SOF that is received. - * Because the device controller is initialized to FS before connect, this bit will be set at an interval of 1ms during the prelude to connect and chirp. - * In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. - * Software writes a 1 to this bit to clear it. - */ -#define USB_USBSTS_SRI_MASK (0x80U) -#define USB_USBSTS_SRI_SHIFT (7U) -#define USB_USBSTS_SRI_SET(x) (((uint32_t)(x) << USB_USBSTS_SRI_SHIFT) & USB_USBSTS_SRI_MASK) -#define USB_USBSTS_SRI_GET(x) (((uint32_t)(x) & USB_USBSTS_SRI_MASK) >> USB_USBSTS_SRI_SHIFT) - -/* - * URI (RWC) - * - * URI - * USB Reset Received - R/WC. - * When the device controller detects a USB Reset and enters the default state, this bit will be set to a one. - * Software can write a 1 to this bit to clear the USB Reset Received status bit. - * Only used in device operation mode. - */ -#define USB_USBSTS_URI_MASK (0x40U) -#define USB_USBSTS_URI_SHIFT (6U) -#define USB_USBSTS_URI_SET(x) (((uint32_t)(x) << USB_USBSTS_URI_SHIFT) & USB_USBSTS_URI_MASK) -#define USB_USBSTS_URI_GET(x) (((uint32_t)(x) & USB_USBSTS_URI_MASK) >> USB_USBSTS_URI_SHIFT) - -/* - * AAI (RWC) - * - * AAI - * Interrupt on Async Advance - R/WC. - * System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule - * by writing a one to the Interrupt on Async Advance Doorbell bit in the n_USBCMD register. This status bit indicates the assertion of that interrupt source. - * Only used in host operation mode. - */ -#define USB_USBSTS_AAI_MASK (0x20U) -#define USB_USBSTS_AAI_SHIFT (5U) -#define USB_USBSTS_AAI_SET(x) (((uint32_t)(x) << USB_USBSTS_AAI_SHIFT) & USB_USBSTS_AAI_MASK) -#define USB_USBSTS_AAI_GET(x) (((uint32_t)(x) & USB_USBSTS_AAI_MASK) >> USB_USBSTS_AAI_SHIFT) - -/* - * SEI (RWC) - * - * System Error – RWC. Default = 0b. - * In the BVCI implementation of the USBHS core, this bit is not used, and will always be cleared to '0b'. - * In the AMBA implementation, this bit will be set to '1b' when an Error response is seen by the master interface (HRESP[1:0]=ERROR) - */ -#define USB_USBSTS_SEI_MASK (0x10U) -#define USB_USBSTS_SEI_SHIFT (4U) -#define USB_USBSTS_SEI_SET(x) (((uint32_t)(x) << USB_USBSTS_SEI_SHIFT) & USB_USBSTS_SEI_MASK) -#define USB_USBSTS_SEI_GET(x) (((uint32_t)(x) & USB_USBSTS_SEI_MASK) >> USB_USBSTS_SEI_SHIFT) - -/* - * FRI (RWC) - * - * FRI - * Frame List Rollover - R/WC. - * The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to - * zero. The exact value at which the rollover occurs depends on the frame list size. For example. If the - * frame list size (as programmed in the Frame List Size field of the USB_n_USBCMD register) is 1024, the - * Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host - * Controller sets this bit to a one every time FHINDEX [12] toggles. - * Only used in host operation mode. - */ -#define USB_USBSTS_FRI_MASK (0x8U) -#define USB_USBSTS_FRI_SHIFT (3U) -#define USB_USBSTS_FRI_SET(x) (((uint32_t)(x) << USB_USBSTS_FRI_SHIFT) & USB_USBSTS_FRI_MASK) -#define USB_USBSTS_FRI_GET(x) (((uint32_t)(x) & USB_USBSTS_FRI_MASK) >> USB_USBSTS_FRI_SHIFT) - -/* - * PCI (RWC) - * - * PCI - * Port Change Detect - R/WC. - * The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, - * or the Force Port Resume bit is set as the result of a J-K transition on the suspended port. - * The Device Controller sets this bit to a one when the port controller enters the full or high-speed operational state. - * When the port controller exits the full or high-speed operation states due to Reset or Suspend events, - * the notification mechanisms are the USB Reset Received bit and the DCSuspend bits Respectively. - */ -#define USB_USBSTS_PCI_MASK (0x4U) -#define USB_USBSTS_PCI_SHIFT (2U) -#define USB_USBSTS_PCI_SET(x) (((uint32_t)(x) << USB_USBSTS_PCI_SHIFT) & USB_USBSTS_PCI_MASK) -#define USB_USBSTS_PCI_GET(x) (((uint32_t)(x) & USB_USBSTS_PCI_MASK) >> USB_USBSTS_PCI_SHIFT) - -/* - * UEI (RWC) - * - * UEI - * USB Error Interrupt (USBERRINT) - R/WC. - * When completion of a USB transaction results in an error condition, this bit is set by the Host/Device Controller. - * This bit is set along with the USBINT bit, if the TD on which the error interrupt occurred also had its interrupt on complete (IOC) bit set. - */ -#define USB_USBSTS_UEI_MASK (0x2U) -#define USB_USBSTS_UEI_SHIFT (1U) -#define USB_USBSTS_UEI_SET(x) (((uint32_t)(x) << USB_USBSTS_UEI_SHIFT) & USB_USBSTS_UEI_MASK) -#define USB_USBSTS_UEI_GET(x) (((uint32_t)(x) & USB_USBSTS_UEI_MASK) >> USB_USBSTS_UEI_SHIFT) - -/* - * UI (RWC) - * - * UI - * USB Interrupt (USBINT) - R/WC. - * This bit is set by the Host/Device Controller when the cause of an interrupt is a completion of a USB - * transaction where the Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set. - * This bit is also set by the Host/Device Controller when a short packet is detected. A short packet is when - * the actual number of bytes received was less than the expected number of bytes. - */ -#define USB_USBSTS_UI_MASK (0x1U) -#define USB_USBSTS_UI_SHIFT (0U) -#define USB_USBSTS_UI_SET(x) (((uint32_t)(x) << USB_USBSTS_UI_SHIFT) & USB_USBSTS_UI_MASK) -#define USB_USBSTS_UI_GET(x) (((uint32_t)(x) & USB_USBSTS_UI_MASK) >> USB_USBSTS_UI_SHIFT) - -/* Bitfield definition for register: USBINTR */ -/* - * TIE1 (RW) - * - * TIE1 - * General Purpose Timer #1 Interrupt Enable - * When this bit is one and the TI1 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE1_MASK (0x2000000UL) -#define USB_USBINTR_TIE1_SHIFT (25U) -#define USB_USBINTR_TIE1_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE1_SHIFT) & USB_USBINTR_TIE1_MASK) -#define USB_USBINTR_TIE1_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE1_MASK) >> USB_USBINTR_TIE1_SHIFT) - -/* - * TIE0 (RW) - * - * TIE0 - * General Purpose Timer #0 Interrupt Enable - * When this bit is one and the TI0 bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_TIE0_MASK (0x1000000UL) -#define USB_USBINTR_TIE0_SHIFT (24U) -#define USB_USBINTR_TIE0_SET(x) (((uint32_t)(x) << USB_USBINTR_TIE0_SHIFT) & USB_USBINTR_TIE0_MASK) -#define USB_USBINTR_TIE0_GET(x) (((uint32_t)(x) & USB_USBINTR_TIE0_MASK) >> USB_USBINTR_TIE0_SHIFT) - -/* - * UPIE (RW) - * - * UPIE - * USB Host Periodic Interrupt Enable - * When this bit is one, and the UPI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UPIE_MASK (0x80000UL) -#define USB_USBINTR_UPIE_SHIFT (19U) -#define USB_USBINTR_UPIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UPIE_SHIFT) & USB_USBINTR_UPIE_MASK) -#define USB_USBINTR_UPIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UPIE_MASK) >> USB_USBINTR_UPIE_SHIFT) - -/* - * UAIE (RW) - * - * UAIE - * USB Host Asynchronous Interrupt Enable - * When this bit is one, and the UAI bit in the n_USBSTS register is one, host controller will issue an - * interrupt at the next interrupt threshold. - */ -#define USB_USBINTR_UAIE_MASK (0x40000UL) -#define USB_USBINTR_UAIE_SHIFT (18U) -#define USB_USBINTR_UAIE_SET(x) (((uint32_t)(x) << USB_USBINTR_UAIE_SHIFT) & USB_USBINTR_UAIE_MASK) -#define USB_USBINTR_UAIE_GET(x) (((uint32_t)(x) & USB_USBINTR_UAIE_MASK) >> USB_USBINTR_UAIE_SHIFT) - -/* - * NAKE (RO) - * - * NAKE - * NAK Interrupt Enable - * When this bit is one and the NAKI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_NAKE_MASK (0x10000UL) -#define USB_USBINTR_NAKE_SHIFT (16U) -#define USB_USBINTR_NAKE_GET(x) (((uint32_t)(x) & USB_USBINTR_NAKE_MASK) >> USB_USBINTR_NAKE_SHIFT) - -/* - * SLE (RW) - * - * SLE - * Sleep Interrupt Enable - * When this bit is one and the SLI bit in n_n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_SLE_MASK (0x100U) -#define USB_USBINTR_SLE_SHIFT (8U) -#define USB_USBINTR_SLE_SET(x) (((uint32_t)(x) << USB_USBINTR_SLE_SHIFT) & USB_USBINTR_SLE_MASK) -#define USB_USBINTR_SLE_GET(x) (((uint32_t)(x) & USB_USBINTR_SLE_MASK) >> USB_USBINTR_SLE_SHIFT) - -/* - * SRE (RW) - * - * SRE - * SOF Received Interrupt Enable - * When this bit is one and the SRI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_SRE_MASK (0x80U) -#define USB_USBINTR_SRE_SHIFT (7U) -#define USB_USBINTR_SRE_SET(x) (((uint32_t)(x) << USB_USBINTR_SRE_SHIFT) & USB_USBINTR_SRE_MASK) -#define USB_USBINTR_SRE_GET(x) (((uint32_t)(x) & USB_USBINTR_SRE_MASK) >> USB_USBINTR_SRE_SHIFT) - -/* - * URE (RW) - * - * URE - * USB Reset Interrupt Enable - * When this bit is one and the URI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in device operation mode. - */ -#define USB_USBINTR_URE_MASK (0x40U) -#define USB_USBINTR_URE_SHIFT (6U) -#define USB_USBINTR_URE_SET(x) (((uint32_t)(x) << USB_USBINTR_URE_SHIFT) & USB_USBINTR_URE_MASK) -#define USB_USBINTR_URE_GET(x) (((uint32_t)(x) & USB_USBINTR_URE_MASK) >> USB_USBINTR_URE_SHIFT) - -/* - * AAE (RW) - * - * AAE - * Async Advance Interrupt Enable - * When this bit is one and the AAI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_AAE_MASK (0x20U) -#define USB_USBINTR_AAE_SHIFT (5U) -#define USB_USBINTR_AAE_SET(x) (((uint32_t)(x) << USB_USBINTR_AAE_SHIFT) & USB_USBINTR_AAE_MASK) -#define USB_USBINTR_AAE_GET(x) (((uint32_t)(x) & USB_USBINTR_AAE_MASK) >> USB_USBINTR_AAE_SHIFT) - -/* - * SEE (RW) - * - * SEE - * System Error Interrupt Enable - * When this bit is one and the SEI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_SEE_MASK (0x10U) -#define USB_USBINTR_SEE_SHIFT (4U) -#define USB_USBINTR_SEE_SET(x) (((uint32_t)(x) << USB_USBINTR_SEE_SHIFT) & USB_USBINTR_SEE_MASK) -#define USB_USBINTR_SEE_GET(x) (((uint32_t)(x) & USB_USBINTR_SEE_MASK) >> USB_USBINTR_SEE_SHIFT) - -/* - * FRE (RW) - * - * FRE - * Frame List Rollover Interrupt Enable - * When this bit is one and the FRI bit in n_USBSTS register is a one the controller will issue an interrupt. - * Only used in host operation mode. - */ -#define USB_USBINTR_FRE_MASK (0x8U) -#define USB_USBINTR_FRE_SHIFT (3U) -#define USB_USBINTR_FRE_SET(x) (((uint32_t)(x) << USB_USBINTR_FRE_SHIFT) & USB_USBINTR_FRE_MASK) -#define USB_USBINTR_FRE_GET(x) (((uint32_t)(x) & USB_USBINTR_FRE_MASK) >> USB_USBINTR_FRE_SHIFT) - -/* - * PCE (RW) - * - * PCE - * Port Change Detect Interrupt Enable - * When this bit is one and the PCI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_PCE_MASK (0x4U) -#define USB_USBINTR_PCE_SHIFT (2U) -#define USB_USBINTR_PCE_SET(x) (((uint32_t)(x) << USB_USBINTR_PCE_SHIFT) & USB_USBINTR_PCE_MASK) -#define USB_USBINTR_PCE_GET(x) (((uint32_t)(x) & USB_USBINTR_PCE_MASK) >> USB_USBINTR_PCE_SHIFT) - -/* - * UEE (RWC) - * - * UEE - * USB Error Interrupt Enable - * When this bit is one and the UEI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UEE_MASK (0x2U) -#define USB_USBINTR_UEE_SHIFT (1U) -#define USB_USBINTR_UEE_SET(x) (((uint32_t)(x) << USB_USBINTR_UEE_SHIFT) & USB_USBINTR_UEE_MASK) -#define USB_USBINTR_UEE_GET(x) (((uint32_t)(x) & USB_USBINTR_UEE_MASK) >> USB_USBINTR_UEE_SHIFT) - -/* - * UE (RW) - * - * UE - * USB Interrupt Enable - * When this bit is one and the UI bit in n_USBSTS register is a one the controller will issue an interrupt. - */ -#define USB_USBINTR_UE_MASK (0x1U) -#define USB_USBINTR_UE_SHIFT (0U) -#define USB_USBINTR_UE_SET(x) (((uint32_t)(x) << USB_USBINTR_UE_SHIFT) & USB_USBINTR_UE_MASK) -#define USB_USBINTR_UE_GET(x) (((uint32_t)(x) & USB_USBINTR_UE_MASK) >> USB_USBINTR_UE_SHIFT) - -/* Bitfield definition for register: FRINDEX */ -/* - * FRINDEX (RW) - * - * FRINDEX - * Frame Index. - * The value, in this register, increments at the end of each time frame (micro-frame). Bits [N: 3] are used for the Frame List current index. - * This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. - * The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. - * USBCMD [Frame List Size] Number Elements N - * In device mode the value is the current frame number of the last frame transmitted. It is not used as an index. - * In either mode bits 2:0 indicate the current microframe. - * The bit field values description below is represented as (Frame List Size) Number Elements N. - * 00000000000000 - (1024) 12 - * 00000000000001 - (512) 11 - * 00000000000010 - (256) 10 - * 00000000000011 - (128) 9 - * 00000000000100 - (64) 8 - * 00000000000101 - (32) 7 - * 00000000000110 - (16) 6 - * 00000000000111 - (8) 5 - */ -#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) -#define USB_FRINDEX_FRINDEX_SHIFT (0U) -#define USB_FRINDEX_FRINDEX_SET(x) (((uint32_t)(x) << USB_FRINDEX_FRINDEX_SHIFT) & USB_FRINDEX_FRINDEX_MASK) -#define USB_FRINDEX_FRINDEX_GET(x) (((uint32_t)(x) & USB_FRINDEX_FRINDEX_MASK) >> USB_FRINDEX_FRINDEX_SHIFT) - -/* Bitfield definition for register: DEVICEADDR */ -/* - * USBADR (RW) - * - * USBADR - * Device Address. - * These bits correspond to the USB device address - */ -#define USB_DEVICEADDR_USBADR_MASK (0xFE000000UL) -#define USB_DEVICEADDR_USBADR_SHIFT (25U) -#define USB_DEVICEADDR_USBADR_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADR_SHIFT) & USB_DEVICEADDR_USBADR_MASK) -#define USB_DEVICEADDR_USBADR_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADR_MASK) >> USB_DEVICEADDR_USBADR_SHIFT) - -/* - * USBADRA (RW) - * - * USBADRA - * Device Address Advance. Default=0. - * When this bit is '0', any writes to USBADR are instantaneous. - * When this bit is written to a '1' at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. - * After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register. - * Hardware will automatically clear this bit on the following conditions: - * 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register). - * 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated). - * 3) Device Reset occurs (USBADR is reset to 0). - * NOTE: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program the USBADR field. - * This mechanism will ensure this specification is met when the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. - * If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase (before the prime of the status phase), - * the USBADR will be programmed instantly at the correct time and meet the 2ms USB requirement. - */ -#define USB_DEVICEADDR_USBADRA_MASK (0x1000000UL) -#define USB_DEVICEADDR_USBADRA_SHIFT (24U) -#define USB_DEVICEADDR_USBADRA_SET(x) (((uint32_t)(x) << USB_DEVICEADDR_USBADRA_SHIFT) & USB_DEVICEADDR_USBADRA_MASK) -#define USB_DEVICEADDR_USBADRA_GET(x) (((uint32_t)(x) & USB_DEVICEADDR_USBADRA_MASK) >> USB_DEVICEADDR_USBADRA_SHIFT) - -/* Bitfield definition for register: PERIODICLISTBASE */ -/* - * BASEADR (RW) - * - * BASEADR - * Base Address (Low). - * These bits correspond to memory address signals [31:12], respectively. - * Only used by the host controller. - */ -#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000UL) -#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) -#define USB_PERIODICLISTBASE_BASEADR_SET(x) (((uint32_t)(x) << USB_PERIODICLISTBASE_BASEADR_SHIFT) & USB_PERIODICLISTBASE_BASEADR_MASK) -#define USB_PERIODICLISTBASE_BASEADR_GET(x) (((uint32_t)(x) & USB_PERIODICLISTBASE_BASEADR_MASK) >> USB_PERIODICLISTBASE_BASEADR_SHIFT) - -/* Bitfield definition for register: ASYNCLISTADDR */ -/* - * ASYBASE (RW) - * - * ASYBASE - * Link Pointer Low (LPL). - * These bits correspond to memory address signals [31:5], respectively. This field may only reference a - * Queue Head (QH). - * Only used by the host controller. - */ -#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0UL) -#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) -#define USB_ASYNCLISTADDR_ASYBASE_SET(x) (((uint32_t)(x) << USB_ASYNCLISTADDR_ASYBASE_SHIFT) & USB_ASYNCLISTADDR_ASYBASE_MASK) -#define USB_ASYNCLISTADDR_ASYBASE_GET(x) (((uint32_t)(x) & USB_ASYNCLISTADDR_ASYBASE_MASK) >> USB_ASYNCLISTADDR_ASYBASE_SHIFT) - -/* Bitfield definition for register: ENDPTLISTADDR */ -/* - * EPBASE (RW) - * - * EPBASE - * Endpoint List Pointer(Low). These bits correspond to memory address signals [31:11], respectively. - * This field will reference a list of up to 32 Queue Head (QH) (that is, one queue head per endpoint & direction). - */ -#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800UL) -#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) -#define USB_ENDPTLISTADDR_EPBASE_SET(x) (((uint32_t)(x) << USB_ENDPTLISTADDR_EPBASE_SHIFT) & USB_ENDPTLISTADDR_EPBASE_MASK) -#define USB_ENDPTLISTADDR_EPBASE_GET(x) (((uint32_t)(x) & USB_ENDPTLISTADDR_EPBASE_MASK) >> USB_ENDPTLISTADDR_EPBASE_SHIFT) - -/* Bitfield definition for register: BURSTSIZE */ -/* - * TXPBURST (RW) - * - * TXPBURST - * Programmable TX Burst Size. - * Default value is determined by TXBURST bits in n_HWTXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from system - * memory to the USB bus. - */ -#define USB_BURSTSIZE_TXPBURST_MASK (0xFF00U) -#define USB_BURSTSIZE_TXPBURST_SHIFT (8U) -#define USB_BURSTSIZE_TXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_TXPBURST_SHIFT) & USB_BURSTSIZE_TXPBURST_MASK) -#define USB_BURSTSIZE_TXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_TXPBURST_MASK) >> USB_BURSTSIZE_TXPBURST_SHIFT) - -/* - * RXPBURST (RW) - * - * RXPBURST - * Programmable RX Burst Size. - * Default value is determined by TXBURST bits in n_HWRXBUF. - * This register represents the maximum length of a the burst in 32-bit words while moving data from the - * USB bus to system memory. - */ -#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) -#define USB_BURSTSIZE_RXPBURST_SHIFT (0U) -#define USB_BURSTSIZE_RXPBURST_SET(x) (((uint32_t)(x) << USB_BURSTSIZE_RXPBURST_SHIFT) & USB_BURSTSIZE_RXPBURST_MASK) -#define USB_BURSTSIZE_RXPBURST_GET(x) (((uint32_t)(x) & USB_BURSTSIZE_RXPBURST_MASK) >> USB_BURSTSIZE_RXPBURST_SHIFT) - -/* Bitfield definition for register: TXFILLTUNING */ -/* - * TXFIFOTHRES (RW) - * - * TXFIFOTHRES - * FIFO Burst Threshold. (Read/Write) - * This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus. - * The minimum value is 2 and this value should be a low as possible to maximize USB performance. - * A higher value can be used in systems with unpredictable latency and/or insufficient bandwidth - * where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory. - * This value is ignored if the Stream Disable bit in USB_n_USBMODE register is set. - */ -#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000UL) -#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) -#define USB_TXFILLTUNING_TXFIFOTHRES_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) -#define USB_TXFILLTUNING_TXFIFOTHRES_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) >> USB_TXFILLTUNING_TXFIFOTHRES_SHIFT) - -/* - * TXSCHHEALTH (RWC) - * - * TXSCHHEALTH - * Scheduler Health Counter. (Read/Write To Clear) - * Table continues on the next page - * This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES - * before running out of time to send the packet before the next Start-Of-Frame. - * This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH. - * Writing to this register will clear the counter and this counter will max. at 31. - */ -#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) -#define USB_TXFILLTUNING_TXSCHHEALTH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) -#define USB_TXFILLTUNING_TXSCHHEALTH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) >> USB_TXFILLTUNING_TXSCHHEALTH_SHIFT) - -/* - * TXSCHOH (RW) - * - * TXSCHOH - * Scheduler Overhead. (Read/Write) [Default = 0] - * This register adds an additional fixed offset to the schedule time estimator described above as Tff. - * As an approximation, the value chosen for this register should limit the number of back-off events captured - * in the TXSCHHEALTH to less than 10 per second in a highly utilized bus. - * Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization. - * The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode. - * The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode. - * Default value is '08h' for OTG controller core . - */ -#define USB_TXFILLTUNING_TXSCHOH_MASK (0x7FU) -#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) -#define USB_TXFILLTUNING_TXSCHOH_SET(x) (((uint32_t)(x) << USB_TXFILLTUNING_TXSCHOH_SHIFT) & USB_TXFILLTUNING_TXSCHOH_MASK) -#define USB_TXFILLTUNING_TXSCHOH_GET(x) (((uint32_t)(x) & USB_TXFILLTUNING_TXSCHOH_MASK) >> USB_TXFILLTUNING_TXSCHOH_SHIFT) - -/* Bitfield definition for register: ENDPTNAK */ -/* - * EPTN (RWC) - * - * EPTN - * TX Endpoint NAK - R/WC. - * Each TX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received IN token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPTN_MASK (0xFFFF0000UL) -#define USB_ENDPTNAK_EPTN_SHIFT (16U) -#define USB_ENDPTNAK_EPTN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPTN_SHIFT) & USB_ENDPTNAK_EPTN_MASK) -#define USB_ENDPTNAK_EPTN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPTN_MASK) >> USB_ENDPTNAK_EPTN_SHIFT) - -/* - * EPRN (RWC) - * - * EPRN - * RX Endpoint NAK - R/WC. - * Each RX endpoint has 1 bit in this field. The bit is set when the - * device sends a NAK handshake on a received OUT or PING token for the corresponding endpoint. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAK_EPRN_MASK (0xFFFFU) -#define USB_ENDPTNAK_EPRN_SHIFT (0U) -#define USB_ENDPTNAK_EPRN_SET(x) (((uint32_t)(x) << USB_ENDPTNAK_EPRN_SHIFT) & USB_ENDPTNAK_EPRN_MASK) -#define USB_ENDPTNAK_EPRN_GET(x) (((uint32_t)(x) & USB_ENDPTNAK_EPRN_MASK) >> USB_ENDPTNAK_EPRN_SHIFT) - -/* Bitfield definition for register: ENDPTNAKEN */ -/* - * EPTNE (RW) - * - * EPTNE - * TX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding TX Endpoint NAK bit. If this bit is set and the - * corresponding TX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000UL) -#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) -#define USB_ENDPTNAKEN_EPTNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPTNE_SHIFT) & USB_ENDPTNAKEN_EPTNE_MASK) -#define USB_ENDPTNAKEN_EPTNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPTNE_MASK) >> USB_ENDPTNAKEN_EPTNE_SHIFT) - -/* - * EPRNE (RW) - * - * EPRNE - * RX Endpoint NAK Enable - R/W. - * Each bit is an enable bit for the corresponding RX Endpoint NAK bit. If this bit is set and the - * corresponding RX Endpoint NAK bit is set, the NAK Interrupt bit is set. - * Bit [N] - Endpoint #[N], N is 0-7 - */ -#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFFFU) -#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) -#define USB_ENDPTNAKEN_EPRNE_SET(x) (((uint32_t)(x) << USB_ENDPTNAKEN_EPRNE_SHIFT) & USB_ENDPTNAKEN_EPRNE_MASK) -#define USB_ENDPTNAKEN_EPRNE_GET(x) (((uint32_t)(x) & USB_ENDPTNAKEN_EPRNE_MASK) >> USB_ENDPTNAKEN_EPRNE_SHIFT) - -/* Bitfield definition for register: PORTSC1 */ -/* - * STS (RW) - * - * STS - * Serial Transceiver Select - * 1 Serial Interface Engine is selected - * 0 Parallel Interface signals is selected - * Serial Interface Engine can be used in combination with UTMI+/ULPI physical interface to provide FS/LS signaling instead of the parallel interface signals. - * When this bit is set '1b', serial interface engine will be used instead of parallel interface signals. - */ -#define USB_PORTSC1_STS_MASK (0x20000000UL) -#define USB_PORTSC1_STS_SHIFT (29U) -#define USB_PORTSC1_STS_SET(x) (((uint32_t)(x) << USB_PORTSC1_STS_SHIFT) & USB_PORTSC1_STS_MASK) -#define USB_PORTSC1_STS_GET(x) (((uint32_t)(x) & USB_PORTSC1_STS_MASK) >> USB_PORTSC1_STS_SHIFT) - -/* - * PTW (RW) - * - * PTW - * Parallel Transceiver Width - * This bit has no effect if serial interface engine is used. - * 0 - Select the 8-bit UTMI interface [60MHz] - * 1 - Select the 16-bit UTMI interface [30MHz] - */ -#define USB_PORTSC1_PTW_MASK (0x10000000UL) -#define USB_PORTSC1_PTW_SHIFT (28U) -#define USB_PORTSC1_PTW_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTW_SHIFT) & USB_PORTSC1_PTW_MASK) -#define USB_PORTSC1_PTW_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTW_MASK) >> USB_PORTSC1_PTW_SHIFT) - -/* - * PSPD (RO) - * - * PSPD - * Port Speed - Read Only. - * This register field indicates the speed at which the port is operating. - * 00 - Full Speed - * 01 - Low Speed - * 10 - High Speed - * 11 - Undefined - */ -#define USB_PORTSC1_PSPD_MASK (0xC000000UL) -#define USB_PORTSC1_PSPD_SHIFT (26U) -#define USB_PORTSC1_PSPD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PSPD_MASK) >> USB_PORTSC1_PSPD_SHIFT) - -/* - * PFSC (RW) - * - * PFSC - * Port Force Full Speed Connect - Read/Write. Default = 0b. - * When this bit is set to '1b', the port will be forced to only connect at Full Speed, It disables the chirp - * sequence that allows the port to identify itself as High Speed. - * 0 - Normal operation - * 1 - Forced to full speed - */ -#define USB_PORTSC1_PFSC_MASK (0x1000000UL) -#define USB_PORTSC1_PFSC_SHIFT (24U) -#define USB_PORTSC1_PFSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PFSC_SHIFT) & USB_PORTSC1_PFSC_MASK) -#define USB_PORTSC1_PFSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PFSC_MASK) >> USB_PORTSC1_PFSC_SHIFT) - -/* - * PHCD (RW) - * - * PHCD - * PHY Low Power Suspend - Clock Disable (PLPSCD) - Read/Write. Default = 0b. - * When this bit is set to '1b', the PHY clock is disabled. Reading this bit will indicate the status of the PHY - * clock. - * NOTE: The PHY clock cannot be disabled if it is being used as the system clock. - * In device mode, The PHY can be put into Low Power Suspend when the device is not running (USBCMD - * Run/Stop=0b) or the host has signalled suspend (PORTSC1 SUSPEND=1b). PHY Low power suspend - * will be cleared automatically when the host initials resume. Before forcing a resume from the device, the - * device controller driver must clear this bit. - * In host mode, the PHY can be put into Low Power Suspend when the downstream device has been put - * into suspend mode or when no downstream device is connected. Low power suspend is completely - * under the control of software. - * 0 - Enable PHY clock - * 1 - Disable PHY clock - */ -#define USB_PORTSC1_PHCD_MASK (0x800000UL) -#define USB_PORTSC1_PHCD_SHIFT (23U) -#define USB_PORTSC1_PHCD_SET(x) (((uint32_t)(x) << USB_PORTSC1_PHCD_SHIFT) & USB_PORTSC1_PHCD_MASK) -#define USB_PORTSC1_PHCD_GET(x) (((uint32_t)(x) & USB_PORTSC1_PHCD_MASK) >> USB_PORTSC1_PHCD_SHIFT) - -/* - * WKOC (RW) - * - * WKOC - * Wake on Over-current Enable (WKOC_E) - Read/Write. Default = 0b. - * Writing this bit to a one enables the port to be sensitive to over-current conditions as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero. - */ -#define USB_PORTSC1_WKOC_MASK (0x400000UL) -#define USB_PORTSC1_WKOC_SHIFT (22U) -#define USB_PORTSC1_WKOC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKOC_SHIFT) & USB_PORTSC1_WKOC_MASK) -#define USB_PORTSC1_WKOC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKOC_MASK) >> USB_PORTSC1_WKOC_SHIFT) - -/* - * WKDC (RW) - * - * WKDC - * Wake on Disconnect Enable (WKDSCNNT_E) - Read/Write. Default=0b. Writing this bit to a one enables - * the port to be sensitive to device disconnects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKDC_MASK (0x200000UL) -#define USB_PORTSC1_WKDC_SHIFT (21U) -#define USB_PORTSC1_WKDC_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKDC_SHIFT) & USB_PORTSC1_WKDC_MASK) -#define USB_PORTSC1_WKDC_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKDC_MASK) >> USB_PORTSC1_WKDC_SHIFT) - -/* - * WKCN (RW) - * - * WKCN - * Wake on Connect Enable (WKCNNT_E) - Read/Write. Default=0b. - * Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. - * This field is zero if Port Power(PORTSC1) is zero or in device mode. - */ -#define USB_PORTSC1_WKCN_MASK (0x100000UL) -#define USB_PORTSC1_WKCN_SHIFT (20U) -#define USB_PORTSC1_WKCN_SET(x) (((uint32_t)(x) << USB_PORTSC1_WKCN_SHIFT) & USB_PORTSC1_WKCN_MASK) -#define USB_PORTSC1_WKCN_GET(x) (((uint32_t)(x) & USB_PORTSC1_WKCN_MASK) >> USB_PORTSC1_WKCN_SHIFT) - -/* - * PTC (RW) - * - * PTC - * Port Test Control - Read/Write. Default = 0000b. - * Refer to Port Test Mode for the operational model for using these test modes and the USB Specification Revision 2.0, Chapter 7 for details on each test mode. - * The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. - * Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. - * Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. - * NOTE: Low speed operations are not supported as a peripheral device. - * Any other value than zero indicates that the port is operating in test mode. - * Value Specific Test - * 0000 - TEST_MODE_DISABLE - * 0001 - J_STATE - * 0010 - K_STATE - * 0011 - SE0 (host) / NAK (device) - * 0100 - Packet - * 0101 - FORCE_ENABLE_HS - * 0110 - FORCE_ENABLE_FS - * 0111 - FORCE_ENABLE_LS - * 1000-1111 - Reserved - */ -#define USB_PORTSC1_PTC_MASK (0xF0000UL) -#define USB_PORTSC1_PTC_SHIFT (16U) -#define USB_PORTSC1_PTC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PTC_SHIFT) & USB_PORTSC1_PTC_MASK) -#define USB_PORTSC1_PTC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PTC_MASK) >> USB_PORTSC1_PTC_SHIFT) - -/* - * PP (RW) - * - * PP - * Port Power (PP)-Read/Write or Read Only. - * The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: - * PPC - * PP Operation - * 0 - * 1b Read Only - Host controller does not have port power control switches. Each port is hard-wired to power. - * 1 - * 1b/0b - Read/Write. OTG controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). - * When power is not available on a port (that is, PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. - * When an over-current condition is detected on a powered port and PPC is a one, - * the PP bit in each affected port may be transitional by the host controller driver from a one to a zero (removing power from the port). - * This feature is implemented in all controller cores (PPC = 1). - */ -#define USB_PORTSC1_PP_MASK (0x1000U) -#define USB_PORTSC1_PP_SHIFT (12U) -#define USB_PORTSC1_PP_SET(x) (((uint32_t)(x) << USB_PORTSC1_PP_SHIFT) & USB_PORTSC1_PP_MASK) -#define USB_PORTSC1_PP_GET(x) (((uint32_t)(x) & USB_PORTSC1_PP_MASK) >> USB_PORTSC1_PP_SHIFT) - -/* - * LS (RO) - * - * LS - * Line Status-Read Only. These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal - * lines. - * In host mode, the use of linestate by the host controller driver is not necessary (unlike EHCI), because - * the port controller state machine and the port routing manage the connection of LS and FS. - * In device mode, the use of linestate by the device controller driver is not necessary. - * The encoding of the bits are: - * Bits [11:10] Meaning - * 00 - SE0 - * 01 - K-state - * 10 - J-state - * 11 - Undefined - */ -#define USB_PORTSC1_LS_MASK (0xC00U) -#define USB_PORTSC1_LS_SHIFT (10U) -#define USB_PORTSC1_LS_GET(x) (((uint32_t)(x) & USB_PORTSC1_LS_MASK) >> USB_PORTSC1_LS_SHIFT) - -/* - * HSP (RO) - * - * HSP - * High-Speed Port - Read Only. Default = 0b. - * When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the - * host/device connected to the port is not in a high-speed mode. - * NOTE: HSP is redundant with PSPD(bit 27, 26) but remained for compatibility. - */ -#define USB_PORTSC1_HSP_MASK (0x200U) -#define USB_PORTSC1_HSP_SHIFT (9U) -#define USB_PORTSC1_HSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_HSP_MASK) >> USB_PORTSC1_HSP_SHIFT) - -/* - * PR (RW) - * - * PR - * Port Reset - Read/Write or Read Only. Default = 0b. - * In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset. Default 0. - * When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. - * This bit will automatically change to zero after the reset sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. - * In Device Mode: This bit is a read only status bit. Device reset from the USB bus is also indicated in the USBSTS register. - */ -#define USB_PORTSC1_PR_MASK (0x100U) -#define USB_PORTSC1_PR_SHIFT (8U) -#define USB_PORTSC1_PR_SET(x) (((uint32_t)(x) << USB_PORTSC1_PR_SHIFT) & USB_PORTSC1_PR_MASK) -#define USB_PORTSC1_PR_GET(x) (((uint32_t)(x) & USB_PORTSC1_PR_MASK) >> USB_PORTSC1_PR_SHIFT) - -/* - * SUSP (RW) - * - * SUSP - * Suspend - Read/Write or Read Only. Default = 0b. - * 1=Port in suspend state. 0=Port not in suspend state. - * In Host Mode: Read/Write. - * Port Enabled Bit and Suspend bit of this register define the port states as follows: - * Bits [Port Enabled, Suspend] Port State - * 0x Disable - * 10 Enable - * 11 Suspend - * When in suspend state, downstream propagation of data is blocked on this port, except for port reset. - * The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. - * In the suspend state, the port is sensitive to resume detection. - * Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. - * The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. - * If host software sets this bit to a one when the port is not enabled (that is, Port enabled bit is a zero) the results are undefined. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: Read Only. - * In device mode this bit is a read only status bit. - */ -#define USB_PORTSC1_SUSP_MASK (0x80U) -#define USB_PORTSC1_SUSP_SHIFT (7U) -#define USB_PORTSC1_SUSP_SET(x) (((uint32_t)(x) << USB_PORTSC1_SUSP_SHIFT) & USB_PORTSC1_SUSP_MASK) -#define USB_PORTSC1_SUSP_GET(x) (((uint32_t)(x) & USB_PORTSC1_SUSP_MASK) >> USB_PORTSC1_SUSP_SHIFT) - -/* - * FPR (RW) - * - * FPR - * Force Port Resume -Read/Write. 1= Resume detected/driven on port. 0=No resume (K-state) detected driven on port. Default = 0. - * In Host Mode: - * Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. - * This bit will automatically change to zero after the resume sequence is complete. - * This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. - * Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. - * The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. - * Writing a zero has no effect because the port controller will time the resume operation, clear the bit the port control state switches to HS or FS idle. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * This bit is not-EHCI compatible. - * In Device mode: - * After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. - * The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. - * The bit will be cleared when the device returns to normal operation. - * Also, when this bit wil be cleared because a K-to-J transition detected, the Port Change Detect bit in the USBSTS register is also set to one. - */ -#define USB_PORTSC1_FPR_MASK (0x40U) -#define USB_PORTSC1_FPR_SHIFT (6U) -#define USB_PORTSC1_FPR_SET(x) (((uint32_t)(x) << USB_PORTSC1_FPR_SHIFT) & USB_PORTSC1_FPR_MASK) -#define USB_PORTSC1_FPR_GET(x) (((uint32_t)(x) & USB_PORTSC1_FPR_MASK) >> USB_PORTSC1_FPR_SHIFT) - -/* - * OCC (RW) - * - * OCC - * Over-current Change-R/WC. Default=0. - * This bit is set '1b' by hardware when there is a change to Over-current Active. Software can clear this bit by writing a one to this bit position. - */ -#define USB_PORTSC1_OCC_MASK (0x20U) -#define USB_PORTSC1_OCC_SHIFT (5U) -#define USB_PORTSC1_OCC_SET(x) (((uint32_t)(x) << USB_PORTSC1_OCC_SHIFT) & USB_PORTSC1_OCC_MASK) -#define USB_PORTSC1_OCC_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCC_MASK) >> USB_PORTSC1_OCC_SHIFT) - -/* - * OCA (RO) - * - * OCA - * Over-current Active-Read Only. Default 0. - * This bit will automatically transition from one to zero when the over current condition is removed. - * 0 - This port does not have an over-current condition. - * 1 - This port currently has an over-current condition - */ -#define USB_PORTSC1_OCA_MASK (0x10U) -#define USB_PORTSC1_OCA_SHIFT (4U) -#define USB_PORTSC1_OCA_GET(x) (((uint32_t)(x) & USB_PORTSC1_OCA_MASK) >> USB_PORTSC1_OCA_SHIFT) - -/* - * PEC (RWC) - * - * PEC - * Port Enable/Disable Change-R/WC. 1=Port enabled/disabled status has changed. 0=No change. Default = 0. - * In Host Mode: - * For the root hub, this bit is set to a one only when a port is disabled due to disconnect on the port or - * due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). - * Software clears this by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero. - * In Device mode: - * The device port is always enabled, so this bit is always '0b'. - */ -#define USB_PORTSC1_PEC_MASK (0x8U) -#define USB_PORTSC1_PEC_SHIFT (3U) -#define USB_PORTSC1_PEC_SET(x) (((uint32_t)(x) << USB_PORTSC1_PEC_SHIFT) & USB_PORTSC1_PEC_MASK) -#define USB_PORTSC1_PEC_GET(x) (((uint32_t)(x) & USB_PORTSC1_PEC_MASK) >> USB_PORTSC1_PEC_SHIFT) - -/* - * PE (RWC) - * - * PE - * Port Enabled/Disabled-Read/Write. 1=Enable. 0=Disable. Default 0. - * In Host Mode: - * Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. - * Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. - * Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. - * When the port is disabled, (0b) downstream propagation of data is blocked except for reset. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * The device port is always enabled, so this bit is always '1b'. - */ -#define USB_PORTSC1_PE_MASK (0x4U) -#define USB_PORTSC1_PE_SHIFT (2U) -#define USB_PORTSC1_PE_SET(x) (((uint32_t)(x) << USB_PORTSC1_PE_SHIFT) & USB_PORTSC1_PE_MASK) -#define USB_PORTSC1_PE_GET(x) (((uint32_t)(x) & USB_PORTSC1_PE_MASK) >> USB_PORTSC1_PE_SHIFT) - -/* - * CSC (RWC) - * - * CSC - * Connect Status Change-R/WC. 1 =Change in Current Connect Status. 0=No change. Default 0. - * In Host Mode: - * Indicates a change has occurred in the port's Current Connect Status. - * The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. - * For example, the insertion status changes twice before system software has cleared the changed condition, - * hub hardware will be 'setting' an already-set bit (that is, the bit will remain set). Software clears this bit by writing a one to it. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * This bit is undefined in device controller mode. - */ -#define USB_PORTSC1_CSC_MASK (0x2U) -#define USB_PORTSC1_CSC_SHIFT (1U) -#define USB_PORTSC1_CSC_SET(x) (((uint32_t)(x) << USB_PORTSC1_CSC_SHIFT) & USB_PORTSC1_CSC_MASK) -#define USB_PORTSC1_CSC_GET(x) (((uint32_t)(x) & USB_PORTSC1_CSC_MASK) >> USB_PORTSC1_CSC_SHIFT) - -/* - * CCS (RWC) - * - * CCS - * Current Connect Status-Read Only. - * In Host Mode: - * 1=Device is present on port. 0=No device is present. Default = 0. - * This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. - * This field is zero if Port Power(PORTSC1) is zero in host mode. - * In Device Mode: - * 1=Attached. 0=Not Attached. Default=0. - * A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. - * A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. - * It does not state the device being disconnected or Suspended. - */ -#define USB_PORTSC1_CCS_MASK (0x1U) -#define USB_PORTSC1_CCS_SHIFT (0U) -#define USB_PORTSC1_CCS_SET(x) (((uint32_t)(x) << USB_PORTSC1_CCS_SHIFT) & USB_PORTSC1_CCS_MASK) -#define USB_PORTSC1_CCS_GET(x) (((uint32_t)(x) & USB_PORTSC1_CCS_MASK) >> USB_PORTSC1_CCS_SHIFT) - -/* Bitfield definition for register: OTGSC */ -/* - * ASVIE (RW) - * - * ASVIE - * A Session Valid Interrupt Enable - Read/Write. - */ -#define USB_OTGSC_ASVIE_MASK (0x4000000UL) -#define USB_OTGSC_ASVIE_SHIFT (26U) -#define USB_OTGSC_ASVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIE_SHIFT) & USB_OTGSC_ASVIE_MASK) -#define USB_OTGSC_ASVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIE_MASK) >> USB_OTGSC_ASVIE_SHIFT) - -/* - * AVVIE (RW) - * - * AVVIE - * A VBus Valid Interrupt Enable - Read/Write. - * Setting this bit enables the A VBus valid interrupt. - */ -#define USB_OTGSC_AVVIE_MASK (0x2000000UL) -#define USB_OTGSC_AVVIE_SHIFT (25U) -#define USB_OTGSC_AVVIE_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIE_SHIFT) & USB_OTGSC_AVVIE_MASK) -#define USB_OTGSC_AVVIE_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIE_MASK) >> USB_OTGSC_AVVIE_SHIFT) - -/* - * IDIE (RW) - * - * IDIE - * USB ID Interrupt Enable - Read/Write. - * Setting this bit enables the USB ID interrupt. - */ -#define USB_OTGSC_IDIE_MASK (0x1000000UL) -#define USB_OTGSC_IDIE_SHIFT (24U) -#define USB_OTGSC_IDIE_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIE_SHIFT) & USB_OTGSC_IDIE_MASK) -#define USB_OTGSC_IDIE_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIE_MASK) >> USB_OTGSC_IDIE_SHIFT) - -/* - * ASVIS (RWC) - * - * ASVIS - * A Session Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the A session valid threshold. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_ASVIS_MASK (0x40000UL) -#define USB_OTGSC_ASVIS_SHIFT (18U) -#define USB_OTGSC_ASVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_ASVIS_SHIFT) & USB_OTGSC_ASVIS_MASK) -#define USB_OTGSC_ASVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_ASVIS_MASK) >> USB_OTGSC_ASVIS_SHIFT) - -/* - * AVVIS (RWC) - * - * AVVIS - * A VBus Valid Interrupt Status - Read/Write to Clear. - * This bit is set when VBus has either risen above or fallen below the VBus valid threshold on an A device. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_AVVIS_MASK (0x20000UL) -#define USB_OTGSC_AVVIS_SHIFT (17U) -#define USB_OTGSC_AVVIS_SET(x) (((uint32_t)(x) << USB_OTGSC_AVVIS_SHIFT) & USB_OTGSC_AVVIS_MASK) -#define USB_OTGSC_AVVIS_GET(x) (((uint32_t)(x) & USB_OTGSC_AVVIS_MASK) >> USB_OTGSC_AVVIS_SHIFT) - -/* - * IDIS (RWC) - * - * IDIS - * USB ID Interrupt Status - Read/Write. - * This bit is set when a change on the ID input has been detected. - * Software must write a one to clear this bit. - */ -#define USB_OTGSC_IDIS_MASK (0x10000UL) -#define USB_OTGSC_IDIS_SHIFT (16U) -#define USB_OTGSC_IDIS_SET(x) (((uint32_t)(x) << USB_OTGSC_IDIS_SHIFT) & USB_OTGSC_IDIS_MASK) -#define USB_OTGSC_IDIS_GET(x) (((uint32_t)(x) & USB_OTGSC_IDIS_MASK) >> USB_OTGSC_IDIS_SHIFT) - -/* - * ASV (RO) - * - * ASV - * A Session Valid - Read Only. - * Indicates VBus is above the A session valid threshold. - */ -#define USB_OTGSC_ASV_MASK (0x400U) -#define USB_OTGSC_ASV_SHIFT (10U) -#define USB_OTGSC_ASV_GET(x) (((uint32_t)(x) & USB_OTGSC_ASV_MASK) >> USB_OTGSC_ASV_SHIFT) - -/* - * AVV (RO) - * - * AVV - * A VBus Valid - Read Only. - * Indicates VBus is above the A VBus valid threshold. - */ -#define USB_OTGSC_AVV_MASK (0x200U) -#define USB_OTGSC_AVV_SHIFT (9U) -#define USB_OTGSC_AVV_GET(x) (((uint32_t)(x) & USB_OTGSC_AVV_MASK) >> USB_OTGSC_AVV_SHIFT) - -/* - * ID (RO) - * - * ID - * USB ID - Read Only. - * 0 = A device, 1 = B device - */ -#define USB_OTGSC_ID_MASK (0x100U) -#define USB_OTGSC_ID_SHIFT (8U) -#define USB_OTGSC_ID_GET(x) (((uint32_t)(x) & USB_OTGSC_ID_MASK) >> USB_OTGSC_ID_SHIFT) - -/* - * IDPU (RW) - * - * IDPU - * ID Pullup - Read/Write - * This bit provide control over the ID pull-up resistor; 0 = off, 1 = on [default]. When this bit is 0, the ID input - * will not be sampled. - */ -#define USB_OTGSC_IDPU_MASK (0x20U) -#define USB_OTGSC_IDPU_SHIFT (5U) -#define USB_OTGSC_IDPU_SET(x) (((uint32_t)(x) << USB_OTGSC_IDPU_SHIFT) & USB_OTGSC_IDPU_MASK) -#define USB_OTGSC_IDPU_GET(x) (((uint32_t)(x) & USB_OTGSC_IDPU_MASK) >> USB_OTGSC_IDPU_SHIFT) - -/* - * VC (RW) - * - * VC - * VBUS Charge - Read/Write. - * Setting this bit causes the VBus line to be charged. This is used for VBus pulsing during SRP. - */ -#define USB_OTGSC_VC_MASK (0x2U) -#define USB_OTGSC_VC_SHIFT (1U) -#define USB_OTGSC_VC_SET(x) (((uint32_t)(x) << USB_OTGSC_VC_SHIFT) & USB_OTGSC_VC_MASK) -#define USB_OTGSC_VC_GET(x) (((uint32_t)(x) & USB_OTGSC_VC_MASK) >> USB_OTGSC_VC_SHIFT) - -/* - * VD (RW) - * - * VD - * VBUS_Discharge - Read/Write. - * Setting this bit causes VBus to discharge through a resistor. - */ -#define USB_OTGSC_VD_MASK (0x1U) -#define USB_OTGSC_VD_SHIFT (0U) -#define USB_OTGSC_VD_SET(x) (((uint32_t)(x) << USB_OTGSC_VD_SHIFT) & USB_OTGSC_VD_MASK) -#define USB_OTGSC_VD_GET(x) (((uint32_t)(x) & USB_OTGSC_VD_MASK) >> USB_OTGSC_VD_SHIFT) - -/* Bitfield definition for register: USBMODE */ -/* - * SDIS (RW) - * - * SDIS - * Stream Disable Mode. (0 - Inactive [default]; 1 - Active) - * Device Mode: Setting to a '1' disables double priming on both RX and TX for low bandwidth systems. - * This mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems. - * Note: In High Speed Mode, all packets received are responded to with a NYET handshake when stream disable is active. - * Host Mode: Setting to a '1' ensures that overruns/underruns of the latency FIFO are eliminated for low bandwidth systems - * where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB. - * NOTE: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING and TXTTFILLTUNING [MPH Only] to characterize the adjustments needed for - * the scheduler when using this feature. - * NOTE: The use of this feature substantially limits of the overall USB performance that can be achieved. - */ -#define USB_USBMODE_SDIS_MASK (0x10U) -#define USB_USBMODE_SDIS_SHIFT (4U) -#define USB_USBMODE_SDIS_SET(x) (((uint32_t)(x) << USB_USBMODE_SDIS_SHIFT) & USB_USBMODE_SDIS_MASK) -#define USB_USBMODE_SDIS_GET(x) (((uint32_t)(x) & USB_USBMODE_SDIS_MASK) >> USB_USBMODE_SDIS_SHIFT) - -/* - * SLOM (RW) - * - * SLOM - * Setup Lockout Mode. In device mode, this bit controls behavior of the setup lock mechanism. See Control Endpoint Operation Model . - * 0 - Setup Lockouts On (default); - * 1 - Setup Lockouts Off. DCD requires use of Setup Data Buffer Tripwire in USBCMD. - */ -#define USB_USBMODE_SLOM_MASK (0x8U) -#define USB_USBMODE_SLOM_SHIFT (3U) -#define USB_USBMODE_SLOM_SET(x) (((uint32_t)(x) << USB_USBMODE_SLOM_SHIFT) & USB_USBMODE_SLOM_MASK) -#define USB_USBMODE_SLOM_GET(x) (((uint32_t)(x) & USB_USBMODE_SLOM_MASK) >> USB_USBMODE_SLOM_SHIFT) - -/* - * ES (RW) - * - * ES - * Endian Select - Read/Write. This bit can change the byte alignment of the transfer buffers to match the - * host microprocessor. The bit fields in the microprocessor interface and the data structures are unaffected - * by the value of this bit because they are based upon the 32-bit word. - * Bit Meaning - * 0 - Little Endian [Default] - * 1 - Big Endian - */ -#define USB_USBMODE_ES_MASK (0x4U) -#define USB_USBMODE_ES_SHIFT (2U) -#define USB_USBMODE_ES_SET(x) (((uint32_t)(x) << USB_USBMODE_ES_SHIFT) & USB_USBMODE_ES_MASK) -#define USB_USBMODE_ES_GET(x) (((uint32_t)(x) & USB_USBMODE_ES_MASK) >> USB_USBMODE_ES_SHIFT) - -/* - * CM (RW) - * - * CM - * Controller Mode - R/WO. Controller mode is defaulted to the proper mode for host only and device only - * implementations. For those designs that contain both host & device capability, the controller defaults to - * an idle state and needs to be initialized to the desired operating mode after reset. For combination host/ - * device controllers, this register can only be written once after reset. If it is necessary to switch modes, - * software must reset the controller by writing to the RESET bit in the USBCMD register before - * reprogramming this register. - * For OTG controller core, reset value is '00b'. - * 00 - Idle [Default for combination host/device] - * 01 - Reserved - * 10 - Device Controller [Default for device only controller] - * 11 - Host Controller [Default for host only controller] - */ -#define USB_USBMODE_CM_MASK (0x3U) -#define USB_USBMODE_CM_SHIFT (0U) -#define USB_USBMODE_CM_SET(x) (((uint32_t)(x) << USB_USBMODE_CM_SHIFT) & USB_USBMODE_CM_MASK) -#define USB_USBMODE_CM_GET(x) (((uint32_t)(x) & USB_USBMODE_CM_MASK) >> USB_USBMODE_CM_SHIFT) - -/* Bitfield definition for register: ENDPTSETUPSTAT */ -/* - * ENDPTSETUPSTAT (RWC) - * - * ENDPTSETUPSTAT - * Setup Endpoint Status. For every setup transaction that is received, a corresponding bit in this register is set to one. - * Software must clear or acknowledge the setup transfer by writing a one to a respective bit after it has read the setup data from Queue head. - * The response to a setup packet as in the order of operations and total response time is crucial to limit bus time outs while the setup lock out mechanism is engaged. - * This register is only used in device mode. - */ -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SET(x) (((uint32_t)(x) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) -#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_GET(x) (((uint32_t)(x) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) >> USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) - -/* Bitfield definition for register: ENDPTPRIME */ -/* - * PETB (RWS) - * - * PETB - * Prime Endpoint Transmit Buffer - R/WS. For each endpoint a corresponding bit is used to request that a - * buffer is prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction. - * Software should write a one to the corresponding bit when posting a new transfer descriptor to an - * endpoint queue head. Hardware automatically uses this bit to begin parsing for a new transfer descriptor - * from the queue head and prepare a transmit buffer. Hardware clears this bit when the associated - * endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PETB_MASK (0xFFFF0000UL) -#define USB_ENDPTPRIME_PETB_SHIFT (16U) -#define USB_ENDPTPRIME_PETB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PETB_SHIFT) & USB_ENDPTPRIME_PETB_MASK) -#define USB_ENDPTPRIME_PETB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PETB_MASK) >> USB_ENDPTPRIME_PETB_SHIFT) - -/* - * PERB (RWS) - * - * PERB - * Prime Endpoint Receive Buffer - R/WS. For each endpoint, a corresponding bit is used to request a buffer prepare for a receive operation for when a USB host initiates a USB OUT transaction. - * Software should write a one to the corresponding bit whenever posting a new transfer descriptor to an endpoint queue head. - * Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. - * Hardware clears this bit when the associated endpoint(s) is (are) successfully primed. - * NOTE: These bits are momentarily set by hardware during hardware re-priming operations when a dTD - * is retired, and the dQH is updated. - * PERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTPRIME_PERB_MASK (0xFFFFU) -#define USB_ENDPTPRIME_PERB_SHIFT (0U) -#define USB_ENDPTPRIME_PERB_SET(x) (((uint32_t)(x) << USB_ENDPTPRIME_PERB_SHIFT) & USB_ENDPTPRIME_PERB_MASK) -#define USB_ENDPTPRIME_PERB_GET(x) (((uint32_t)(x) & USB_ENDPTPRIME_PERB_MASK) >> USB_ENDPTPRIME_PERB_SHIFT) - -/* Bitfield definition for register: ENDPTFLUSH */ -/* - * FETB (RWS) - * - * FETB - * Flush Endpoint Transmit Buffer - R/WS. Writing one to a bit(s) in this register causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FETB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FETB_MASK (0xFFFF0000UL) -#define USB_ENDPTFLUSH_FETB_SHIFT (16U) -#define USB_ENDPTFLUSH_FETB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FETB_SHIFT) & USB_ENDPTFLUSH_FETB_MASK) -#define USB_ENDPTFLUSH_FETB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FETB_MASK) >> USB_ENDPTFLUSH_FETB_SHIFT) - -/* - * FERB (RWS) - * - * FERB - * Flush Endpoint Receive Buffer - R/WS. Writing one to a bit(s) causes the associated endpoint(s) to clear any primed buffers. - * If a packet is in progress for one of the associated endpoints, then that transfer continues until completion. - * Hardware clears this register after the endpoint flush operation is successful. - * FERB[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTFLUSH_FERB_MASK (0xFFFFU) -#define USB_ENDPTFLUSH_FERB_SHIFT (0U) -#define USB_ENDPTFLUSH_FERB_SET(x) (((uint32_t)(x) << USB_ENDPTFLUSH_FERB_SHIFT) & USB_ENDPTFLUSH_FERB_MASK) -#define USB_ENDPTFLUSH_FERB_GET(x) (((uint32_t)(x) & USB_ENDPTFLUSH_FERB_MASK) >> USB_ENDPTFLUSH_FERB_SHIFT) - -/* Bitfield definition for register: ENDPTSTAT */ -/* - * ETBR (RO) - * - * ETBR - * Endpoint Transmit Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective endpoint buffer. - * This bit is set to one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. - * There is always a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. - * This delay time varies based upon the current USB traffic and the number of bits set in the ENDPRIME register. - * Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations when a dTD is retired, and the dQH is updated. - * ETBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ETBR_MASK (0xFFFF0000UL) -#define USB_ENDPTSTAT_ETBR_SHIFT (16U) -#define USB_ENDPTSTAT_ETBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ETBR_MASK) >> USB_ENDPTSTAT_ETBR_SHIFT) - -/* - * ERBR (RO) - * - * ERBR - * Endpoint Receive Buffer Ready -- Read Only. One bit for each endpoint indicates status of the respective - * endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a - * corresponding bit in the ENDPRIME register. There is always a delay between setting a bit in the - * ENDPRIME register and endpoint indicating ready. This delay time varies based upon the current USB - * traffic and the number of bits set in the ENDPRIME register. Buffer ready is cleared by USB reset, by the - * USB DMA system, or through the ENDPTFLUSH register. - * NOTE: These bits are momentarily cleared by hardware during hardware endpoint re-priming operations - * when a dTD is retired, and the dQH is updated. - * ERBR[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTSTAT_ERBR_MASK (0xFFFFU) -#define USB_ENDPTSTAT_ERBR_SHIFT (0U) -#define USB_ENDPTSTAT_ERBR_GET(x) (((uint32_t)(x) & USB_ENDPTSTAT_ERBR_MASK) >> USB_ENDPTSTAT_ERBR_SHIFT) - -/* Bitfield definition for register: ENDPTCOMPLETE */ -/* - * ETCE (RWC) - * - * ETCE - * Endpoint Transmit Complete Event - R/WC. Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. - * If the corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the USBINT . Writing one clears the corresponding bit in this register. - * ETCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000UL) -#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) -#define USB_ENDPTCOMPLETE_ETCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ETCE_SHIFT) & USB_ENDPTCOMPLETE_ETCE_MASK) -#define USB_ENDPTCOMPLETE_ETCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ETCE_MASK) >> USB_ENDPTCOMPLETE_ETCE_SHIFT) - -/* - * ERCE (RWC) - * - * ERCE - * Endpoint Receive Complete Event - RW/C. Each bit indicates a received event (OUT/SETUP) occurred - * and software should read the corresponding endpoint queue to determine the transfer status. If the - * corresponding IOC bit is set in the Transfer Descriptor, then this bit is set simultaneously with the - * USBINT . Writing one clears the corresponding bit in this register. - * ERCE[N] - Endpoint #N, N is in 0..7 - */ -#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU) -#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) -#define USB_ENDPTCOMPLETE_ERCE_SET(x) (((uint32_t)(x) << USB_ENDPTCOMPLETE_ERCE_SHIFT) & USB_ENDPTCOMPLETE_ERCE_MASK) -#define USB_ENDPTCOMPLETE_ERCE_GET(x) (((uint32_t)(x) & USB_ENDPTCOMPLETE_ERCE_MASK) >> USB_ENDPTCOMPLETE_ERCE_SHIFT) - -/* Bitfield definition for register array: ENDPTCTRL */ -/* - * TXE (RW) - * - * TXE - * TX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_TXE_MASK (0x800000UL) -#define USB_ENDPTCTRL_TXE_SHIFT (23U) -#define USB_ENDPTCTRL_TXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXE_SHIFT) & USB_ENDPTCTRL_TXE_MASK) -#define USB_ENDPTCTRL_TXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXE_MASK) >> USB_ENDPTCTRL_TXE_SHIFT) - -/* - * TXR (WS) - * - * TXR - * TX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the Host and device. - */ -#define USB_ENDPTCTRL_TXR_MASK (0x400000UL) -#define USB_ENDPTCTRL_TXR_SHIFT (22U) -#define USB_ENDPTCTRL_TXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXR_SHIFT) & USB_ENDPTCTRL_TXR_MASK) -#define USB_ENDPTCTRL_TXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXR_MASK) >> USB_ENDPTCTRL_TXR_SHIFT) - -/* - * TXT (RW) - * - * TXT - * TX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_TXT_MASK (0xC0000UL) -#define USB_ENDPTCTRL_TXT_SHIFT (18U) -#define USB_ENDPTCTRL_TXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXT_SHIFT) & USB_ENDPTCTRL_TXT_MASK) -#define USB_ENDPTCTRL_TXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXT_MASK) >> USB_ENDPTCTRL_TXT_SHIFT) - -/* - * TXS (RW) - * - * TXS - * TX Endpoint Stall - Read/Write - * 0 End Point OK - * 1 End Point Stalled - * This bit will be cleared automatically upon receipt of a SETUP request if this Endpoint is configured - * as a Control Endpoint and this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. - * This control will continue to STALL until this bit is either cleared by software or automatically cleared as above for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. - * In most systems, it is unlikely the DCD software will observe this delay. However, should the DCD observe that the stall bit is not set after writing a one to it then follow this procedure: - * continually write this stall bit until it is set or until a new setup has been received by checking the associated endptsetupstat Bit. - */ -#define USB_ENDPTCTRL_TXS_MASK (0x10000UL) -#define USB_ENDPTCTRL_TXS_SHIFT (16U) -#define USB_ENDPTCTRL_TXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_TXS_SHIFT) & USB_ENDPTCTRL_TXS_MASK) -#define USB_ENDPTCTRL_TXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_TXS_MASK) >> USB_ENDPTCTRL_TXS_SHIFT) - -/* - * RXE (RW) - * - * RXE - * RX Endpoint Enable - * 0 Disabled [Default] - * 1 Enabled - * An Endpoint should be enabled only after it has been configured. - */ -#define USB_ENDPTCTRL_RXE_MASK (0x80U) -#define USB_ENDPTCTRL_RXE_SHIFT (7U) -#define USB_ENDPTCTRL_RXE_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXE_SHIFT) & USB_ENDPTCTRL_RXE_MASK) -#define USB_ENDPTCTRL_RXE_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXE_MASK) >> USB_ENDPTCTRL_RXE_SHIFT) - -/* - * RXR (WS) - * - * RXR - * RX Data Toggle Reset (WS) - * Write 1 - Reset PID Sequence - * Whenever a configuration event is received for this Endpoint, software must write a one to this bit in order - * to synchronize the data PID's between the host and device. - */ -#define USB_ENDPTCTRL_RXR_MASK (0x40U) -#define USB_ENDPTCTRL_RXR_SHIFT (6U) -#define USB_ENDPTCTRL_RXR_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXR_SHIFT) & USB_ENDPTCTRL_RXR_MASK) -#define USB_ENDPTCTRL_RXR_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXR_MASK) >> USB_ENDPTCTRL_RXR_SHIFT) - -/* - * RXT (RW) - * - * RXT - * RX Endpoint Type - Read/Write - * 00 Control - * 01 Isochronous - * 10 Bulk - * 11 Interrupt - */ -#define USB_ENDPTCTRL_RXT_MASK (0xCU) -#define USB_ENDPTCTRL_RXT_SHIFT (2U) -#define USB_ENDPTCTRL_RXT_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXT_SHIFT) & USB_ENDPTCTRL_RXT_MASK) -#define USB_ENDPTCTRL_RXT_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXT_MASK) >> USB_ENDPTCTRL_RXT_SHIFT) - -/* - * RXS (RW) - * - * RXS - * RX Endpoint Stall - Read/Write - * 0 End Point OK. [Default] - * 1 End Point Stalled - * This bit is set automatically upon receipt of a SETUP request if this Endpoint is configured as a Control - * Endpointand this bit will continue to be cleared by hardware until the associated ENDPTSETUPSTAT bit - * is cleared. - * Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host. This - * control will continue to STALL until this bit is either cleared by software or automatically cleared as above - * for control endpoints. - * NOTE: [CONTROL ENDPOINT TYPES ONLY]: there is a slight delay (50 clocks max) between the - * ENDPTSETUPSTAT begin cleared and hardware continuing to clear this bit. In most systems, it - * is unlikely the DCD software will observe this delay. However, should the DCD observe that the - * stall bit is not set after writing a one to it then follow this procedure: continually write this stall bit - * until it is set or until a new setup has been received by checking the associated endptsetupstat - * Bit. - */ -#define USB_ENDPTCTRL_RXS_MASK (0x1U) -#define USB_ENDPTCTRL_RXS_SHIFT (0U) -#define USB_ENDPTCTRL_RXS_SET(x) (((uint32_t)(x) << USB_ENDPTCTRL_RXS_SHIFT) & USB_ENDPTCTRL_RXS_MASK) -#define USB_ENDPTCTRL_RXS_GET(x) (((uint32_t)(x) & USB_ENDPTCTRL_RXS_MASK) >> USB_ENDPTCTRL_RXS_SHIFT) - -/* Bitfield definition for register: OTG_CTRL0 */ -/* - * OTG_WKDPDMCHG_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK (0x2000000UL) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT (25U) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) -#define USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_MASK) >> USB_OTG_CTRL0_OTG_WKDPDMCHG_EN_SHIFT) - -/* - * AUTORESUME_EN (RW) - * - */ -#define USB_OTG_CTRL0_AUTORESUME_EN_MASK (0x80000UL) -#define USB_OTG_CTRL0_AUTORESUME_EN_SHIFT (19U) -#define USB_OTG_CTRL0_AUTORESUME_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) -#define USB_OTG_CTRL0_AUTORESUME_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_AUTORESUME_EN_MASK) >> USB_OTG_CTRL0_AUTORESUME_EN_SHIFT) - -/* - * OTG_VBUS_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK (0x20000UL) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT (17U) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_VBUS_WAKEUP_EN_SHIFT) - -/* - * OTG_ID_WAKEUP_EN (RW) - * - */ -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK (0x10000UL) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT (16U) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) -#define USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_MASK) >> USB_OTG_CTRL0_OTG_ID_WAKEUP_EN_SHIFT) - -/* - * OTG_VBUS_SOURCE_SEL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK (0x2000U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT (13U) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) -#define USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_MASK) >> USB_OTG_CTRL0_OTG_VBUS_SOURCE_SEL_SHIFT) - -/* - * OTG_UTMI_SUSPENDM_SW (RW) - * - * default 0 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK (0x1000U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT (12U) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_SUSPENDM_SW_SHIFT) - -/* - * OTG_UTMI_RESET_SW (RW) - * - * default 1 for naneng usbphy - */ -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK (0x800U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT (11U) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) -#define USB_OTG_CTRL0_OTG_UTMI_RESET_SW_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_UTMI_RESET_SW_MASK) >> USB_OTG_CTRL0_OTG_UTMI_RESET_SW_SHIFT) - -/* - * OTG_WAKEUP_INT_ENABLE (RW) - * - */ -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK (0x400U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT (10U) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) -#define USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_MASK) >> USB_OTG_CTRL0_OTG_WAKEUP_INT_ENABLE_SHIFT) - -/* - * OTG_POWER_MASK (RW) - * - */ -#define USB_OTG_CTRL0_OTG_POWER_MASK_MASK (0x200U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT (9U) -#define USB_OTG_CTRL0_OTG_POWER_MASK_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) -#define USB_OTG_CTRL0_OTG_POWER_MASK_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_POWER_MASK_MASK) >> USB_OTG_CTRL0_OTG_POWER_MASK_SHIFT) - -/* - * OTG_OVER_CUR_POL (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK (0x100U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT (8U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_POL_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_POL_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_POL_SHIFT) - -/* - * OTG_OVER_CUR_DIS (RW) - * - */ -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK (0x80U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT (7U) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) -#define USB_OTG_CTRL0_OTG_OVER_CUR_DIS_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_OTG_OVER_CUR_DIS_MASK) >> USB_OTG_CTRL0_OTG_OVER_CUR_DIS_SHIFT) - -/* - * SER_MODE_SUSPEND_EN (RW) - * - * for naneng usbphy, only switch to serial mode when suspend - */ -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK (0x10U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT (4U) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SET(x) (((uint32_t)(x) << USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) -#define USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_GET(x) (((uint32_t)(x) & USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_MASK) >> USB_OTG_CTRL0_SER_MODE_SUSPEND_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL0 */ -/* - * GPIO_ID_SEL_N (RW) - * - */ -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK (0x2000000UL) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT (25U) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) -#define USB_PHY_CTRL0_GPIO_ID_SEL_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_GPIO_ID_SEL_N_MASK) >> USB_PHY_CTRL0_GPIO_ID_SEL_N_SHIFT) - -/* - * ID_DIG_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK (0x4000U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT (14U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_SHIFT) - -/* - * SESS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK (0x2000U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT (13U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_SHIFT) - -/* - * VBUS_VALID_OVERRIDE (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK (0x1000U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT (12U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_SHIFT) - -/* - * ID_DIG_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK (0x4U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT (2U) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_ID_DIG_OVERRIDE_EN_SHIFT) - -/* - * SESS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK (0x2U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT (1U) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_SESS_VALID_OVERRIDE_EN_SHIFT) - -/* - * VBUS_VALID_OVERRIDE_EN (RW) - * - */ -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK (0x1U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT (0U) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SET(x) (((uint32_t)(x) << USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) -#define USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_GET(x) (((uint32_t)(x) & USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_MASK) >> USB_PHY_CTRL0_VBUS_VALID_OVERRIDE_EN_SHIFT) - -/* Bitfield definition for register: PHY_CTRL1 */ -/* - * UTMI_CFG_RST_N (RW) - * - */ -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK (0x100000UL) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT (20U) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) -#define USB_PHY_CTRL1_UTMI_CFG_RST_N_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_CFG_RST_N_MASK) >> USB_PHY_CTRL1_UTMI_CFG_RST_N_SHIFT) - -/* - * UTMI_OTG_SUSPENDM (RW) - * - * OTG suspend, not utmi_suspendm - */ -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK (0x2U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT (1U) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SET(x) (((uint32_t)(x) << USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) -#define USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_GET(x) (((uint32_t)(x) & USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_MASK) >> USB_PHY_CTRL1_UTMI_OTG_SUSPENDM_SHIFT) - -/* Bitfield definition for register: TOP_STATUS */ -/* - * WAKEUP_INT_STATUS (RW) - * - */ -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK (0x80000000UL) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT (31U) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_SET(x) (((uint32_t)(x) << USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) -#define USB_TOP_STATUS_WAKEUP_INT_STATUS_GET(x) (((uint32_t)(x) & USB_TOP_STATUS_WAKEUP_INT_STATUS_MASK) >> USB_TOP_STATUS_WAKEUP_INT_STATUS_SHIFT) - -/* Bitfield definition for register: PHY_STATUS */ -/* - * UTMI_CLK_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_CLK_VALID_MASK (0x80000000UL) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT (31U) -#define USB_PHY_STATUS_UTMI_CLK_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) -#define USB_PHY_STATUS_UTMI_CLK_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_CLK_VALID_MASK) >> USB_PHY_STATUS_UTMI_CLK_VALID_SHIFT) - -/* - * LINE_STATE (RW) - * - */ -#define USB_PHY_STATUS_LINE_STATE_MASK (0xC0U) -#define USB_PHY_STATUS_LINE_STATE_SHIFT (6U) -#define USB_PHY_STATUS_LINE_STATE_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_LINE_STATE_SHIFT) & USB_PHY_STATUS_LINE_STATE_MASK) -#define USB_PHY_STATUS_LINE_STATE_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_LINE_STATE_MASK) >> USB_PHY_STATUS_LINE_STATE_SHIFT) - -/* - * HOST_DISCONNECT (RW) - * - */ -#define USB_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U) -#define USB_PHY_STATUS_HOST_DISCONNECT_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) -#define USB_PHY_STATUS_HOST_DISCONNECT_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_HOST_DISCONNECT_MASK) >> USB_PHY_STATUS_HOST_DISCONNECT_SHIFT) - -/* - * ID_DIG (RW) - * - */ -#define USB_PHY_STATUS_ID_DIG_MASK (0x10U) -#define USB_PHY_STATUS_ID_DIG_SHIFT (4U) -#define USB_PHY_STATUS_ID_DIG_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_ID_DIG_SHIFT) & USB_PHY_STATUS_ID_DIG_MASK) -#define USB_PHY_STATUS_ID_DIG_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_ID_DIG_MASK) >> USB_PHY_STATUS_ID_DIG_SHIFT) - -/* - * UTMI_SESS_VALID (RW) - * - */ -#define USB_PHY_STATUS_UTMI_SESS_VALID_MASK (0x4U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT (2U) -#define USB_PHY_STATUS_UTMI_SESS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) -#define USB_PHY_STATUS_UTMI_SESS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_UTMI_SESS_VALID_MASK) >> USB_PHY_STATUS_UTMI_SESS_VALID_SHIFT) - -/* - * VBUS_VALID (RW) - * - */ -#define USB_PHY_STATUS_VBUS_VALID_MASK (0x1U) -#define USB_PHY_STATUS_VBUS_VALID_SHIFT (0U) -#define USB_PHY_STATUS_VBUS_VALID_SET(x) (((uint32_t)(x) << USB_PHY_STATUS_VBUS_VALID_SHIFT) & USB_PHY_STATUS_VBUS_VALID_MASK) -#define USB_PHY_STATUS_VBUS_VALID_GET(x) (((uint32_t)(x) & USB_PHY_STATUS_VBUS_VALID_MASK) >> USB_PHY_STATUS_VBUS_VALID_SHIFT) - - - -/* ENDPTCTRL register group index macro definition */ -#define USB_ENDPTCTRL_ENDPTCTRL0 (0UL) -#define USB_ENDPTCTRL_ENDPTCTRL1 (1UL) -#define USB_ENDPTCTRL_ENDPTCTRL2 (2UL) -#define USB_ENDPTCTRL_ENDPTCTRL3 (3UL) -#define USB_ENDPTCTRL_ENDPTCTRL4 (4UL) -#define USB_ENDPTCTRL_ENDPTCTRL5 (5UL) -#define USB_ENDPTCTRL_ENDPTCTRL6 (6UL) -#define USB_ENDPTCTRL_ENDPTCTRL7 (7UL) -#define USB_ENDPTCTRL_ENDPTCTRL8 (8UL) -#define USB_ENDPTCTRL_ENDPTCTRL9 (9UL) -#define USB_ENDPTCTRL_ENDPTCTRL10 (10UL) -#define USB_ENDPTCTRL_ENDPTCTRL11 (11UL) -#define USB_ENDPTCTRL_ENDPTCTRL12 (12UL) -#define USB_ENDPTCTRL_ENDPTCTRL13 (13UL) -#define USB_ENDPTCTRL_ENDPTCTRL14 (14UL) -#define USB_ENDPTCTRL_ENDPTCTRL15 (15UL) - - -#endif /* HPM_USB_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_vsc_regs.h b/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_vsc_regs.h deleted file mode 100644 index 7d1f0f0cd3a..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/soc/HPM6E00/ip/hpm_vsc_regs.h +++ /dev/null @@ -1,759 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - - -#ifndef HPM_VSC_H -#define HPM_VSC_H - -typedef struct { - __RW uint32_t ABC_MODE; /* 0x0: abc mode */ - __RW uint32_t ADC_CHAN_ASSIGN; /* 0x4: assign adc_chan for value_a/b/c */ - __RW uint32_t VALUE_A_DATA_OPT; /* 0x8: value_a data operation mode */ - __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */ - __RW uint32_t VALUE_B_DATA_OPT; /* 0x10: value_b data operation mode */ - __R uint8_t RESERVED1[4]; /* 0x14 - 0x17: Reserved */ - __RW uint32_t VALUE_C_DATA_OPT; /* 0x18: value_c data operation mode */ - __R uint8_t RESERVED2[4]; /* 0x1C - 0x1F: Reserved */ - __RW uint32_t VALUE_A_OFFSET; /* 0x20: value_a offset */ - __RW uint32_t VALUE_B_OFFSET; /* 0x24: value_b_offset */ - __RW uint32_t VALUE_C_OFFSET; /* 0x28: value_c offset */ - __RW uint32_t IRQ_STATUS; /* 0x2C: irq status */ - __RW uint32_t VALUE_A_SW; /* 0x30: value_a software inject value */ - __RW uint32_t VALUE_B_SW; /* 0x34: value_b software inject value */ - __RW uint32_t VALUE_C_SW; /* 0x38: value_c software inject value */ - __W uint32_t VALUE_SW_READY; /* 0x3C: software inject value_a/value_b/value_c ready */ - __W uint32_t TRIGGER_SW; /* 0x40: software trigger event */ - __RW uint32_t TIMELOCK; /* 0x44: timestamp mode and postion capture ctrl */ - __RW uint32_t POSITION_SW; /* 0x48: position software inject value */ - __RW uint32_t ADC_WAIT_CYCLE; /* 0x4C: adc wait cycle after trigger adc capture event */ - __RW uint32_t POS_WAIT_CYCLE; /* 0x50: pos wait cycle after trigger adc capture event */ - __RW uint32_t IRQ_ENABLE; /* 0x54: irq bit enable */ - __RW uint32_t ADC_PHASE_TOLERATE; /* 0x58: adc phase tolerate */ - __RW uint32_t POS_POLE; /* 0x5C: position pole num */ - __R uint8_t RESERVED3[160]; /* 0x60 - 0xFF: Reserved */ - __R uint32_t ID_POSEDGE; /* 0x100: posedge order Id value */ - __R uint32_t IQ_POSEDGE; /* 0x104: posedge order Iq value */ - __R uint32_t ID_NEGEDGE; /* 0x108: negedge order Id value */ - __R uint32_t IQ_NEGEDGE; /* 0x10C: negedge order Iq value */ - __R uint32_t ALPHA_POSEDGE; /* 0x110: posedge order alpha value */ - __R uint32_t BETA_POSEDGE; /* 0x114: posedge order beta value */ - __R uint32_t ALPHA_NEGEDGE; /* 0x118: negedge order alpha value */ - __R uint32_t BETA_NEGEDGE; /* 0x11C: negedge order beta value */ - __R uint32_t TIMESTAMP_LOCKED; /* 0x120: timestamp_locked */ - __R uint32_t DEBUG_STATUS0; /* 0x124: debug_status0 */ -} VSC_Type; - - -/* Bitfield definition for register: ABC_MODE */ -/* - * PHASE_ABSENT_MODE (RW) - * - * whether using value_a and value_b instead of three phase - */ -#define VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK (0x80000000UL) -#define VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT (31U) -#define VSC_ABC_MODE_PHASE_ABSENT_MODE_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT) & VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK) -#define VSC_ABC_MODE_PHASE_ABSENT_MODE_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_PHASE_ABSENT_MODE_MASK) >> VSC_ABC_MODE_PHASE_ABSENT_MODE_SHIFT) - -/* - * VALUE_C_WIDTH (RW) - * - * numbers of value_c for each convert - */ -#define VSC_ABC_MODE_VALUE_C_WIDTH_MASK (0xF000000UL) -#define VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT (24U) -#define VSC_ABC_MODE_VALUE_C_WIDTH_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_C_WIDTH_MASK) -#define VSC_ABC_MODE_VALUE_C_WIDTH_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_C_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_C_WIDTH_SHIFT) - -/* - * VALUE_B_WIDTH (RW) - * - * numbers of value_b for each convert - */ -#define VSC_ABC_MODE_VALUE_B_WIDTH_MASK (0xF00000UL) -#define VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT (20U) -#define VSC_ABC_MODE_VALUE_B_WIDTH_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_B_WIDTH_MASK) -#define VSC_ABC_MODE_VALUE_B_WIDTH_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_B_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_B_WIDTH_SHIFT) - -/* - * VALUE_A_WIDTH (RW) - * - * numbers of value_a for each convert - */ -#define VSC_ABC_MODE_VALUE_A_WIDTH_MASK (0xF0000UL) -#define VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT (16U) -#define VSC_ABC_MODE_VALUE_A_WIDTH_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT) & VSC_ABC_MODE_VALUE_A_WIDTH_MASK) -#define VSC_ABC_MODE_VALUE_A_WIDTH_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_A_WIDTH_MASK) >> VSC_ABC_MODE_VALUE_A_WIDTH_SHIFT) - -/* - * VALUE_C_LOC (RW) - * - * the adc index of value_c: - * 2'b:00: resevered; - * 2'b:01: from adc0; - * 2'b:10: from adc1; - * 2'b:11: from adc2; - */ -#define VSC_ABC_MODE_VALUE_C_LOC_MASK (0x3000U) -#define VSC_ABC_MODE_VALUE_C_LOC_SHIFT (12U) -#define VSC_ABC_MODE_VALUE_C_LOC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_C_LOC_SHIFT) & VSC_ABC_MODE_VALUE_C_LOC_MASK) -#define VSC_ABC_MODE_VALUE_C_LOC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_C_LOC_MASK) >> VSC_ABC_MODE_VALUE_C_LOC_SHIFT) - -/* - * VALUE_B_LOC (RW) - * - * the adc index of value_b: - * 2'b:00: resevered; - * 2'b:01: from adc0; - * 2'b:10: from adc1; - * 2'b:11: from adc2; - */ -#define VSC_ABC_MODE_VALUE_B_LOC_MASK (0x300U) -#define VSC_ABC_MODE_VALUE_B_LOC_SHIFT (8U) -#define VSC_ABC_MODE_VALUE_B_LOC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_B_LOC_SHIFT) & VSC_ABC_MODE_VALUE_B_LOC_MASK) -#define VSC_ABC_MODE_VALUE_B_LOC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_B_LOC_MASK) >> VSC_ABC_MODE_VALUE_B_LOC_SHIFT) - -/* - * VALUE_A_LOC (RW) - * - * the adc index of value_a: - * 2'b:00: resevered; - * 2'b:01: from adc0; - * 2'b:10: from adc1; - * 2'b:11: from adc2; - */ -#define VSC_ABC_MODE_VALUE_A_LOC_MASK (0x30U) -#define VSC_ABC_MODE_VALUE_A_LOC_SHIFT (4U) -#define VSC_ABC_MODE_VALUE_A_LOC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_VALUE_A_LOC_SHIFT) & VSC_ABC_MODE_VALUE_A_LOC_MASK) -#define VSC_ABC_MODE_VALUE_A_LOC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_VALUE_A_LOC_MASK) >> VSC_ABC_MODE_VALUE_A_LOC_SHIFT) - -/* - * ENABLE_VSC (RW) - * - * enable vsc convert: - * 0: disable vsc convert - * 1: enable vsc convert - */ -#define VSC_ABC_MODE_ENABLE_VSC_MASK (0x8U) -#define VSC_ABC_MODE_ENABLE_VSC_SHIFT (3U) -#define VSC_ABC_MODE_ENABLE_VSC_SET(x) (((uint32_t)(x) << VSC_ABC_MODE_ENABLE_VSC_SHIFT) & VSC_ABC_MODE_ENABLE_VSC_MASK) -#define VSC_ABC_MODE_ENABLE_VSC_GET(x) (((uint32_t)(x) & VSC_ABC_MODE_ENABLE_VSC_MASK) >> VSC_ABC_MODE_ENABLE_VSC_SHIFT) - -/* Bitfield definition for register: ADC_CHAN_ASSIGN */ -/* - * VALUE_C_CHAN (RW) - * - * value_c's adc chan - */ -#define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK (0x1F0000UL) -#define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT (16U) -#define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SET(x) (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK) -#define VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_GET(x) (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_C_CHAN_SHIFT) - -/* - * VALUE_B_CHAN (RW) - * - * value_b's adc chan - */ -#define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK (0x1F00U) -#define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT (8U) -#define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SET(x) (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK) -#define VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_GET(x) (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_B_CHAN_SHIFT) - -/* - * VALUE_A_CHAN (RW) - * - * value_a's adc chan - */ -#define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK (0x1FU) -#define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT (0U) -#define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SET(x) (((uint32_t)(x) << VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT) & VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK) -#define VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_GET(x) (((uint32_t)(x) & VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_MASK) >> VSC_ADC_CHAN_ASSIGN_VALUE_A_CHAN_SHIFT) - -/* Bitfield definition for register: VALUE_A_DATA_OPT */ -/* - * OPT_3 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_A_DATA_OPT_OPT_3_MASK (0xF000U) -#define VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT (12U) -#define VSC_VALUE_A_DATA_OPT_OPT_3_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_3_MASK) -#define VSC_VALUE_A_DATA_OPT_OPT_3_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_3_SHIFT) - -/* - * OPT_2 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_A_DATA_OPT_OPT_2_MASK (0xF00U) -#define VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT (8U) -#define VSC_VALUE_A_DATA_OPT_OPT_2_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_2_MASK) -#define VSC_VALUE_A_DATA_OPT_OPT_2_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_2_SHIFT) - -/* - * OPT_1 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_A_DATA_OPT_OPT_1_MASK (0xF0U) -#define VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT (4U) -#define VSC_VALUE_A_DATA_OPT_OPT_1_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_1_MASK) -#define VSC_VALUE_A_DATA_OPT_OPT_1_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_1_SHIFT) - -/* - * OPT_0 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_A_DATA_OPT_OPT_0_MASK (0xFU) -#define VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT (0U) -#define VSC_VALUE_A_DATA_OPT_OPT_0_SET(x) (((uint32_t)(x) << VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_A_DATA_OPT_OPT_0_MASK) -#define VSC_VALUE_A_DATA_OPT_OPT_0_GET(x) (((uint32_t)(x) & VSC_VALUE_A_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_A_DATA_OPT_OPT_0_SHIFT) - -/* Bitfield definition for register: VALUE_B_DATA_OPT */ -/* - * OPT_3 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_B_DATA_OPT_OPT_3_MASK (0xF000U) -#define VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT (12U) -#define VSC_VALUE_B_DATA_OPT_OPT_3_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_3_MASK) -#define VSC_VALUE_B_DATA_OPT_OPT_3_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_3_SHIFT) - -/* - * OPT_2 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_B_DATA_OPT_OPT_2_MASK (0xF00U) -#define VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT (8U) -#define VSC_VALUE_B_DATA_OPT_OPT_2_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_2_MASK) -#define VSC_VALUE_B_DATA_OPT_OPT_2_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_2_SHIFT) - -/* - * OPT_1 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_B_DATA_OPT_OPT_1_MASK (0xF0U) -#define VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT (4U) -#define VSC_VALUE_B_DATA_OPT_OPT_1_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_1_MASK) -#define VSC_VALUE_B_DATA_OPT_OPT_1_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_1_SHIFT) - -/* - * OPT_0 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_B_DATA_OPT_OPT_0_MASK (0xFU) -#define VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT (0U) -#define VSC_VALUE_B_DATA_OPT_OPT_0_SET(x) (((uint32_t)(x) << VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_B_DATA_OPT_OPT_0_MASK) -#define VSC_VALUE_B_DATA_OPT_OPT_0_GET(x) (((uint32_t)(x) & VSC_VALUE_B_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_B_DATA_OPT_OPT_0_SHIFT) - -/* Bitfield definition for register: VALUE_C_DATA_OPT */ -/* - * OPT_3 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_C_DATA_OPT_OPT_3_MASK (0xF000U) -#define VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT (12U) -#define VSC_VALUE_C_DATA_OPT_OPT_3_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_3_MASK) -#define VSC_VALUE_C_DATA_OPT_OPT_3_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_3_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_3_SHIFT) - -/* - * OPT_2 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_C_DATA_OPT_OPT_2_MASK (0xF00U) -#define VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT (8U) -#define VSC_VALUE_C_DATA_OPT_OPT_2_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_2_MASK) -#define VSC_VALUE_C_DATA_OPT_OPT_2_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_2_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_2_SHIFT) - -/* - * OPT_1 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_C_DATA_OPT_OPT_1_MASK (0xF0U) -#define VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT (4U) -#define VSC_VALUE_C_DATA_OPT_OPT_1_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_1_MASK) -#define VSC_VALUE_C_DATA_OPT_OPT_1_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_1_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_1_SHIFT) - -/* - * OPT_0 (RW) - * - * 0: PLUS_MUL_1 - * 1: PLUS_MUL_2 - * 5: PLUS_DIV_2 - * 6: PLUS_DIV_3 - * 7: PLUS_DIV_4 - * 8: MINUS MUL 1 - * 9: MINUS MUL 2 - * 13: MINUS DIV 2 - * 14: MINUS DIV 3 - * 15: MINUS DIV 4 - */ -#define VSC_VALUE_C_DATA_OPT_OPT_0_MASK (0xFU) -#define VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT (0U) -#define VSC_VALUE_C_DATA_OPT_OPT_0_SET(x) (((uint32_t)(x) << VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT) & VSC_VALUE_C_DATA_OPT_OPT_0_MASK) -#define VSC_VALUE_C_DATA_OPT_OPT_0_GET(x) (((uint32_t)(x) & VSC_VALUE_C_DATA_OPT_OPT_0_MASK) >> VSC_VALUE_C_DATA_OPT_OPT_0_SHIFT) - -/* Bitfield definition for register: VALUE_A_OFFSET */ -/* - * VALUE_A_OFFSET (RW) - * - * value_a offset - */ -#define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK (0xFFFFFFFFUL) -#define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT (0U) -#define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SET(x) (((uint32_t)(x) << VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT) & VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK) -#define VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_GET(x) (((uint32_t)(x) & VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_MASK) >> VSC_VALUE_A_OFFSET_VALUE_A_OFFSET_SHIFT) - -/* Bitfield definition for register: VALUE_B_OFFSET */ -/* - * VALUE_B_OFFSET (RW) - * - * value_b_offset - */ -#define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK (0xFFFFFFFFUL) -#define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT (0U) -#define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SET(x) (((uint32_t)(x) << VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT) & VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK) -#define VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_GET(x) (((uint32_t)(x) & VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_MASK) >> VSC_VALUE_B_OFFSET_VALUE_B_OFFSET_SHIFT) - -/* Bitfield definition for register: VALUE_C_OFFSET */ -/* - * VALUE_C_OFFSET (RW) - * - * value_c offset - */ -#define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK (0xFFFFFFFFUL) -#define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT (0U) -#define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SET(x) (((uint32_t)(x) << VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT) & VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK) -#define VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_GET(x) (((uint32_t)(x) & VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_MASK) >> VSC_VALUE_C_OFFSET_VALUE_C_OFFSET_SHIFT) - -/* Bitfield definition for register: IRQ_STATUS */ -/* - * IRQ_STATUS (RW) - * - * irq status bit: - * bit0: vsc convert done irq. - * bit1: in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq. - * bit2: value_c overflow during capture process. - * bit3: value_b_overflow during capture process. - * bit4: value_a_overflow during capture process. - * bit5: adc2 chan not capture enough adc value. - * bit6: adc1 chan not capture enough adc value. - * bit7: adc0 chan not capture enough adc value. - * bit8: position not got valid before pos_wait_cycle timeout. - * bit9: adc2 wait cycle timeout. - * bit10: adc1 wait cycle timeout. - * bit11: adc0 wait cycle timeout. - * bit12: trigger_in break vsc convert even if adc or position is ready. - */ -#define VSC_IRQ_STATUS_IRQ_STATUS_MASK (0xFFFFFFFFUL) -#define VSC_IRQ_STATUS_IRQ_STATUS_SHIFT (0U) -#define VSC_IRQ_STATUS_IRQ_STATUS_SET(x) (((uint32_t)(x) << VSC_IRQ_STATUS_IRQ_STATUS_SHIFT) & VSC_IRQ_STATUS_IRQ_STATUS_MASK) -#define VSC_IRQ_STATUS_IRQ_STATUS_GET(x) (((uint32_t)(x) & VSC_IRQ_STATUS_IRQ_STATUS_MASK) >> VSC_IRQ_STATUS_IRQ_STATUS_SHIFT) - -/* Bitfield definition for register: VALUE_A_SW */ -/* - * VALUE_A_SW (RW) - * - * value_a_sw - */ -#define VSC_VALUE_A_SW_VALUE_A_SW_MASK (0xFFFFFFFFUL) -#define VSC_VALUE_A_SW_VALUE_A_SW_SHIFT (0U) -#define VSC_VALUE_A_SW_VALUE_A_SW_SET(x) (((uint32_t)(x) << VSC_VALUE_A_SW_VALUE_A_SW_SHIFT) & VSC_VALUE_A_SW_VALUE_A_SW_MASK) -#define VSC_VALUE_A_SW_VALUE_A_SW_GET(x) (((uint32_t)(x) & VSC_VALUE_A_SW_VALUE_A_SW_MASK) >> VSC_VALUE_A_SW_VALUE_A_SW_SHIFT) - -/* Bitfield definition for register: VALUE_B_SW */ -/* - * VALUE_B_SW (RW) - * - * value_b_sw - */ -#define VSC_VALUE_B_SW_VALUE_B_SW_MASK (0xFFFFFFFFUL) -#define VSC_VALUE_B_SW_VALUE_B_SW_SHIFT (0U) -#define VSC_VALUE_B_SW_VALUE_B_SW_SET(x) (((uint32_t)(x) << VSC_VALUE_B_SW_VALUE_B_SW_SHIFT) & VSC_VALUE_B_SW_VALUE_B_SW_MASK) -#define VSC_VALUE_B_SW_VALUE_B_SW_GET(x) (((uint32_t)(x) & VSC_VALUE_B_SW_VALUE_B_SW_MASK) >> VSC_VALUE_B_SW_VALUE_B_SW_SHIFT) - -/* Bitfield definition for register: VALUE_C_SW */ -/* - * VALUE_C_SW (RW) - * - * value_c_sw - */ -#define VSC_VALUE_C_SW_VALUE_C_SW_MASK (0xFFFFFFFFUL) -#define VSC_VALUE_C_SW_VALUE_C_SW_SHIFT (0U) -#define VSC_VALUE_C_SW_VALUE_C_SW_SET(x) (((uint32_t)(x) << VSC_VALUE_C_SW_VALUE_C_SW_SHIFT) & VSC_VALUE_C_SW_VALUE_C_SW_MASK) -#define VSC_VALUE_C_SW_VALUE_C_SW_GET(x) (((uint32_t)(x) & VSC_VALUE_C_SW_VALUE_C_SW_MASK) >> VSC_VALUE_C_SW_VALUE_C_SW_SHIFT) - -/* Bitfield definition for register: VALUE_SW_READY */ -/* - * VALUE_SW_READY (W1C) - * - * software inject value_a/value_b/value_c ready - */ -#define VSC_VALUE_SW_READY_VALUE_SW_READY_MASK (0x1U) -#define VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT (0U) -#define VSC_VALUE_SW_READY_VALUE_SW_READY_SET(x) (((uint32_t)(x) << VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT) & VSC_VALUE_SW_READY_VALUE_SW_READY_MASK) -#define VSC_VALUE_SW_READY_VALUE_SW_READY_GET(x) (((uint32_t)(x) & VSC_VALUE_SW_READY_VALUE_SW_READY_MASK) >> VSC_VALUE_SW_READY_VALUE_SW_READY_SHIFT) - -/* Bitfield definition for register: TRIGGER_SW */ -/* - * TRIGGER_SW (W1C) - * - * software trigger to start waiting adc capture value, same as hardwire trigger_in - */ -#define VSC_TRIGGER_SW_TRIGGER_SW_MASK (0x1U) -#define VSC_TRIGGER_SW_TRIGGER_SW_SHIFT (0U) -#define VSC_TRIGGER_SW_TRIGGER_SW_SET(x) (((uint32_t)(x) << VSC_TRIGGER_SW_TRIGGER_SW_SHIFT) & VSC_TRIGGER_SW_TRIGGER_SW_MASK) -#define VSC_TRIGGER_SW_TRIGGER_SW_GET(x) (((uint32_t)(x) & VSC_TRIGGER_SW_TRIGGER_SW_MASK) >> VSC_TRIGGER_SW_TRIGGER_SW_SHIFT) - -/* Bitfield definition for register: TIMELOCK */ -/* - * POSITION_CAPTURE_MODE (RW) - * - * postion capture mode: - * 00: position use last valid data when adc value capture finish - * 01: position use frist valid data after adc value capture - * 10: position use last valid data before adc value capture - * other: reserved - */ -#define VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK (0x3000U) -#define VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT (12U) -#define VSC_TIMELOCK_POSITION_CAPTURE_MODE_SET(x) (((uint32_t)(x) << VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT) & VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK) -#define VSC_TIMELOCK_POSITION_CAPTURE_MODE_GET(x) (((uint32_t)(x) & VSC_TIMELOCK_POSITION_CAPTURE_MODE_MASK) >> VSC_TIMELOCK_POSITION_CAPTURE_MODE_SHIFT) - -/* - * ADC_TIMESTAMP_SEL (RW) - * - * adc timestamp select： - * 0：reserved; - * 1: from value_a; - * 2: from value_b; - * 3: from value_c; - */ -#define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK (0x30U) -#define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT (4U) -#define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SET(x) (((uint32_t)(x) << VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT) & VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK) -#define VSC_TIMELOCK_ADC_TIMESTAMP_SEL_GET(x) (((uint32_t)(x) & VSC_TIMELOCK_ADC_TIMESTAMP_SEL_MASK) >> VSC_TIMELOCK_ADC_TIMESTAMP_SEL_SHIFT) - -/* - * VALUE_COUNTER_SEL (RW) - * - * adc timestamp use which number index of adc_timestamp_sel used. - */ -#define VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK (0xFU) -#define VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT (0U) -#define VSC_TIMELOCK_VALUE_COUNTER_SEL_SET(x) (((uint32_t)(x) << VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT) & VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK) -#define VSC_TIMELOCK_VALUE_COUNTER_SEL_GET(x) (((uint32_t)(x) & VSC_TIMELOCK_VALUE_COUNTER_SEL_MASK) >> VSC_TIMELOCK_VALUE_COUNTER_SEL_SHIFT) - -/* Bitfield definition for register: POSITION_SW */ -/* - * POSITION_SW (RW) - * - * position_sw - */ -#define VSC_POSITION_SW_POSITION_SW_MASK (0xFFFFFFFFUL) -#define VSC_POSITION_SW_POSITION_SW_SHIFT (0U) -#define VSC_POSITION_SW_POSITION_SW_SET(x) (((uint32_t)(x) << VSC_POSITION_SW_POSITION_SW_SHIFT) & VSC_POSITION_SW_POSITION_SW_MASK) -#define VSC_POSITION_SW_POSITION_SW_GET(x) (((uint32_t)(x) & VSC_POSITION_SW_POSITION_SW_MASK) >> VSC_POSITION_SW_POSITION_SW_SHIFT) - -/* Bitfield definition for register: ADC_WAIT_CYCLE */ -/* - * ADC_WAIT_CYCLE (RW) - * - * adc wait cycle after trigger adc capture event - */ -#define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK (0xFFFFFFFFUL) -#define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT (0U) -#define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SET(x) (((uint32_t)(x) << VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT) & VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK) -#define VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_GET(x) (((uint32_t)(x) & VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_MASK) >> VSC_ADC_WAIT_CYCLE_ADC_WAIT_CYCLE_SHIFT) - -/* Bitfield definition for register: POS_WAIT_CYCLE */ -/* - * POS_WAIT_CYCLE (RW) - * - * position wait cycle after trigger adc capture event - */ -#define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK (0xFFFFFFFFUL) -#define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT (0U) -#define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SET(x) (((uint32_t)(x) << VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT) & VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK) -#define VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_GET(x) (((uint32_t)(x) & VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_MASK) >> VSC_POS_WAIT_CYCLE_POS_WAIT_CYCLE_SHIFT) - -/* Bitfield definition for register: IRQ_ENABLE */ -/* - * IRQ_ENABLE (RW) - * - * irq enable bit: - * bit0: vsc convert done irq. - * bit1: in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq. - * bit2: value_c overflow during capture process. - * bit3: value_b_overflow during capture process. - * bit4: value_a_overflow during capture process. - * bit5: adc2 chan not capture enough adc value. - * bit6: adc1 chan not capture enough adc value. - * bit7: adc0 chan not capture enough adc value. - * bit8: position not got valid before pos_wait_cycle timeout. - * bit9: adc2 wait cycle timeout. - * bit10: adc1 wait cycle timeout. - * bit11: adc0 wait cycle timeout. - * bit12: trigger_in break vsc convert even if adc or position is ready. - */ -#define VSC_IRQ_ENABLE_IRQ_ENABLE_MASK (0xFFFFFFFFUL) -#define VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT (0U) -#define VSC_IRQ_ENABLE_IRQ_ENABLE_SET(x) (((uint32_t)(x) << VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT) & VSC_IRQ_ENABLE_IRQ_ENABLE_MASK) -#define VSC_IRQ_ENABLE_IRQ_ENABLE_GET(x) (((uint32_t)(x) & VSC_IRQ_ENABLE_IRQ_ENABLE_MASK) >> VSC_IRQ_ENABLE_IRQ_ENABLE_SHIFT) - -/* Bitfield definition for register: ADC_PHASE_TOLERATE */ -/* - * ADC_PHASE_TOLERATE (RW) - * - * in adc three-phase mode, if ABS(value_a+value_b+value_c) > adc_phase_tolerate, will trigger irq. - */ -#define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK (0xFFFFFFFFUL) -#define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT (0U) -#define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SET(x) (((uint32_t)(x) << VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT) & VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK) -#define VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_GET(x) (((uint32_t)(x) & VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_MASK) >> VSC_ADC_PHASE_TOLERATE_ADC_PHASE_TOLERATE_SHIFT) - -/* Bitfield definition for register: POS_POLE */ -/* - * POS_POLE (RW) - * - * pole number - */ -#define VSC_POS_POLE_POS_POLE_MASK (0xFFFFU) -#define VSC_POS_POLE_POS_POLE_SHIFT (0U) -#define VSC_POS_POLE_POS_POLE_SET(x) (((uint32_t)(x) << VSC_POS_POLE_POS_POLE_SHIFT) & VSC_POS_POLE_POS_POLE_MASK) -#define VSC_POS_POLE_POS_POLE_GET(x) (((uint32_t)(x) & VSC_POS_POLE_POS_POLE_MASK) >> VSC_POS_POLE_POS_POLE_SHIFT) - -/* Bitfield definition for register: ID_POSEDGE */ -/* - * ID_POSEDGE (RO) - * - * posedge order Id value - */ -#define VSC_ID_POSEDGE_ID_POSEDGE_MASK (0xFFFFFFFFUL) -#define VSC_ID_POSEDGE_ID_POSEDGE_SHIFT (0U) -#define VSC_ID_POSEDGE_ID_POSEDGE_GET(x) (((uint32_t)(x) & VSC_ID_POSEDGE_ID_POSEDGE_MASK) >> VSC_ID_POSEDGE_ID_POSEDGE_SHIFT) - -/* Bitfield definition for register: IQ_POSEDGE */ -/* - * IQ_POSEDGE (RO) - * - * posedge order Iq value - */ -#define VSC_IQ_POSEDGE_IQ_POSEDGE_MASK (0xFFFFFFFFUL) -#define VSC_IQ_POSEDGE_IQ_POSEDGE_SHIFT (0U) -#define VSC_IQ_POSEDGE_IQ_POSEDGE_GET(x) (((uint32_t)(x) & VSC_IQ_POSEDGE_IQ_POSEDGE_MASK) >> VSC_IQ_POSEDGE_IQ_POSEDGE_SHIFT) - -/* Bitfield definition for register: ID_NEGEDGE */ -/* - * ID_NEGEDGE (RO) - * - * negedge order Id value - */ -#define VSC_ID_NEGEDGE_ID_NEGEDGE_MASK (0xFFFFFFFFUL) -#define VSC_ID_NEGEDGE_ID_NEGEDGE_SHIFT (0U) -#define VSC_ID_NEGEDGE_ID_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_ID_NEGEDGE_ID_NEGEDGE_MASK) >> VSC_ID_NEGEDGE_ID_NEGEDGE_SHIFT) - -/* Bitfield definition for register: IQ_NEGEDGE */ -/* - * IQ_NEGEDGE (RO) - * - * negedge order Iq value - */ -#define VSC_IQ_NEGEDGE_IQ_NEGEDGE_MASK (0xFFFFFFFFUL) -#define VSC_IQ_NEGEDGE_IQ_NEGEDGE_SHIFT (0U) -#define VSC_IQ_NEGEDGE_IQ_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_IQ_NEGEDGE_IQ_NEGEDGE_MASK) >> VSC_IQ_NEGEDGE_IQ_NEGEDGE_SHIFT) - -/* Bitfield definition for register: ALPHA_POSEDGE */ -/* - * ALPHA_POSEDGE (RO) - * - * posedge order alpha value - */ -#define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_MASK (0xFFFFFFFFUL) -#define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_SHIFT (0U) -#define VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_GET(x) (((uint32_t)(x) & VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_MASK) >> VSC_ALPHA_POSEDGE_ALPHA_POSEDGE_SHIFT) - -/* Bitfield definition for register: BETA_POSEDGE */ -/* - * BETA_POSEDGE (RO) - * - * posedge order beta value - */ -#define VSC_BETA_POSEDGE_BETA_POSEDGE_MASK (0xFFFFFFFFUL) -#define VSC_BETA_POSEDGE_BETA_POSEDGE_SHIFT (0U) -#define VSC_BETA_POSEDGE_BETA_POSEDGE_GET(x) (((uint32_t)(x) & VSC_BETA_POSEDGE_BETA_POSEDGE_MASK) >> VSC_BETA_POSEDGE_BETA_POSEDGE_SHIFT) - -/* Bitfield definition for register: ALPHA_NEGEDGE */ -/* - * ALPHA_NEGEDGE (RO) - * - * negedge order alpha value - */ -#define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_MASK (0xFFFFFFFFUL) -#define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_SHIFT (0U) -#define VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_MASK) >> VSC_ALPHA_NEGEDGE_ALPHA_NEGEDGE_SHIFT) - -/* Bitfield definition for register: BETA_NEGEDGE */ -/* - * BETA_NEGEDGE (RO) - * - * negedge order beta value - */ -#define VSC_BETA_NEGEDGE_BETA_NEGEDGE_MASK (0xFFFFFFFFUL) -#define VSC_BETA_NEGEDGE_BETA_NEGEDGE_SHIFT (0U) -#define VSC_BETA_NEGEDGE_BETA_NEGEDGE_GET(x) (((uint32_t)(x) & VSC_BETA_NEGEDGE_BETA_NEGEDGE_MASK) >> VSC_BETA_NEGEDGE_BETA_NEGEDGE_SHIFT) - -/* Bitfield definition for register: TIMESTAMP_LOCKED */ -/* - * TIMESTAMP_LOCKED (RO) - * - * timestamp_locked - */ -#define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_MASK (0xFFFFFFFFUL) -#define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_SHIFT (0U) -#define VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_GET(x) (((uint32_t)(x) & VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_MASK) >> VSC_TIMESTAMP_LOCKED_TIMESTAMP_LOCKED_SHIFT) - -/* Bitfield definition for register: DEBUG_STATUS0 */ -/* - * VALUE_A_COUNTER (RO) - * - * value_a_counter - */ -#define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_MASK (0xF00U) -#define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_SHIFT (8U) -#define VSC_DEBUG_STATUS0_VALUE_A_COUNTER_GET(x) (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_A_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_A_COUNTER_SHIFT) - -/* - * VALUE_B_COUNTER (RO) - * - * value_b_counter - */ -#define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_MASK (0xF0U) -#define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_SHIFT (4U) -#define VSC_DEBUG_STATUS0_VALUE_B_COUNTER_GET(x) (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_B_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_B_COUNTER_SHIFT) - -/* - * VALUE_C_COUNTER (RO) - * - * value_c_counter - */ -#define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_MASK (0xFU) -#define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_SHIFT (0U) -#define VSC_DEBUG_STATUS0_VALUE_C_COUNTER_GET(x) (((uint32_t)(x) & VSC_DEBUG_STATUS0_VALUE_C_COUNTER_MASK) >> VSC_DEBUG_STATUS0_VALUE_C_COUNTER_SHIFT) - - - - -#endif /* HPM_VSC_H */ diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c deleted file mode 100644 index c1134d4d343..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_crc32.h" - - -uint32_t crc32(const uint8_t *buf, uint32_t len) -{ - uint8_t i; - uint32_t crc = 0xFFFFFFFF; - while (len--) { - crc ^= *buf++; - for (i = 0; i < 8; ++i) { - if (crc & 1) - crc = (crc >> 1) ^ 0xEDB88320; - else - crc = (crc >> 1); - } - } - - return ~crc; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h deleted file mode 100644 index 82245e8c43d..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_crc32.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2023 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifndef _HPM_CRC32_H -#define _HPM_CRC32_H - -#include -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -uint32_t crc32(const uint8_t *buf, uint32_t len); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ -#endif \ No newline at end of file diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c deleted file mode 100644 index 513c5a85e61..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_ffssi.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" - -int __ffssi2(int x) -{ - uint32_t i = 0; - if (!x) { - return 0; - } - for (i = 0; (i < sizeof(x) * 8 - 1); i++) { - if ((x >> i) & 1) { - break; - } - } - return i + 1; -} diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c deleted file mode 100644 index 027d8c660ec..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_sbrk.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2021 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#ifdef __GNUC__ -#include -#include -#include "hpm_common.h" - -void *_sbrk(int incr) -{ - extern char __heap_start__, __heap_end__; - static char *heap_end; - char *prev_heap_end; - void *ret; - - if (heap_end == NULL) - { - heap_end = &__heap_start__; - } - - prev_heap_end = heap_end; - - if ((unsigned int)heap_end + (unsigned int)incr > (unsigned int)(&__heap_end__)) - { - errno = ENOMEM; - - ret = (void *)-1; - } - else - { - heap_end = (char *)((unsigned int)heap_end + (unsigned int)incr); - - ret = (void *)prev_heap_end; - } - - return ret; -} -#endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c b/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c deleted file mode 100644 index 4db7f7583e2..00000000000 --- a/bsp/hpmicro/libraries/hpm_sdk/utils/hpm_swap.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2021-2024 HPMicro - * - * SPDX-License-Identifier: BSD-3-Clause - * - */ - -#include "hpm_common.h" - -#if !defined(__riscv_xandes) || defined(__zcc__) -uint32_t __bswapsi2 (uint32_t u) -{ - return ((((u) & 0xff000000) >> 24) - | (((u) & 0x00ff0000) >> 8) - | (((u) & 0x0000ff00) << 8) - | (((u) & 0x000000ff) << 24)); -} - -uint64_t __bswapdi2 (uint64_t u) -{ - return ((((u) & 0xff00000000000000ull) >> 56) - | (((u) & 0x00ff000000000000ull) >> 40) - | (((u) & 0x0000ff0000000000ull) >> 24) - | (((u) & 0x000000ff00000000ull) >> 8) - | (((u) & 0x00000000ff000000ull) << 8) - | (((u) & 0x0000000000ff0000ull) << 24) - | (((u) & 0x000000000000ff00ull) << 40) - | (((u) & 0x00000000000000ffull) << 56)); -} -#endif